[
  {
    "path": "Kconfig",
    "content": "config RTL8822CE\n\ttristate \"Realtek 8822C PCIE WiFi\"\n\tdepends on PCI\n\t---help---\n\t  Help message of RTL8822CE\n\n"
  },
  {
    "path": "Makefile",
    "content": "EXTRA_CFLAGS += $(USER_EXTRA_CFLAGS)\nEXTRA_CFLAGS += -O1\n#EXTRA_CFLAGS += -O3\n#EXTRA_CFLAGS += -Wall\n#EXTRA_CFLAGS += -Wextra\n#EXTRA_CFLAGS += -Werror\n#EXTRA_CFLAGS += -pedantic\n#EXTRA_CFLAGS += -Wshadow -Wpointer-arith -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes\n\nEXTRA_CFLAGS += -Wno-unused-variable\n#EXTRA_CFLAGS += -Wno-unused-value\n#EXTRA_CFLAGS += -Wno-unused-label\n#EXTRA_CFLAGS += -Wno-unused-parameter\nEXTRA_CFLAGS += -Wno-unused-function\nEXTRA_CFLAGS += -Wno-unused\n#EXTRA_CFLAGS += -Wno-uninitialized\n\nGCC_VER_49 := $(shell echo `$(CC) -dumpversion | cut -f1-2 -d.` \\>= 4.9 | bc )\nifeq ($(GCC_VER_49),1)\nEXTRA_CFLAGS += -Wno-date-time\t# Fix compile error && warning on gcc 4.9 and later\nendif\n\nEXTRA_CFLAGS += -I$(src)/include\n\nEXTRA_LDFLAGS += --strip-debug\n\nCONFIG_AUTOCFG_CP = n\n\n########################## WIFI IC ############################\nCONFIG_MULTIDRV = n\nCONFIG_RTL8188E = n\nCONFIG_RTL8812A = n\nCONFIG_RTL8821A = n\nCONFIG_RTL8192E = n\nCONFIG_RTL8723B = n\nCONFIG_RTL8814A = n\nCONFIG_RTL8723C = n\nCONFIG_RTL8188F = n\nCONFIG_RTL8188GTV = n\nCONFIG_RTL8822B = n\nCONFIG_RTL8723D = n\nCONFIG_RTL8821C = n\nCONFIG_RTL8710B = n\nCONFIG_RTL8192F = n\nCONFIG_RTL8822C = y\n######################### Interface ###########################\nCONFIG_USB_HCI = n\nCONFIG_PCI_HCI = y\nCONFIG_SDIO_HCI = n\nCONFIG_GSPI_HCI = n\n########################## Features ###########################\nCONFIG_MP_INCLUDED = y\nCONFIG_POWER_SAVING = y\nCONFIG_IPS_MODE = default\nCONFIG_LPS_MODE = default\nCONFIG_USB_AUTOSUSPEND = n\nCONFIG_HW_PWRP_DETECTION = n\nCONFIG_BT_COEXIST = y\nCONFIG_WAPI_SUPPORT = n\nCONFIG_EFUSE_CONFIG_FILE = y\nCONFIG_EXT_CLK = n\nCONFIG_TRAFFIC_PROTECT = n\nCONFIG_LOAD_PHY_PARA_FROM_FILE = y\nCONFIG_TXPWR_BY_RATE = y\nCONFIG_TXPWR_BY_RATE_EN = auto\nCONFIG_TXPWR_LIMIT = y\nCONFIG_TXPWR_LIMIT_EN = n\nCONFIG_RTW_CHPLAN = 0xFF\nCONFIG_RTW_ADAPTIVITY_EN = enable\nCONFIG_RTW_ADAPTIVITY_MODE = normal\nCONFIG_SIGNAL_SCALE_MAPPING = n\nCONFIG_80211W = y\nCONFIG_REDUCE_TX_CPU_LOADING = n\nCONFIG_BR_EXT = y\nCONFIG_TDLS = n\nCONFIG_WIFI_MONITOR = n\nCONFIG_MCC_MODE = n\nCONFIG_APPEND_VENDOR_IE_ENABLE = n\nCONFIG_RTW_NAPI = y\nCONFIG_RTW_GRO = y\nCONFIG_RTW_NETIF_SG = y\nCONFIG_RTW_IPCAM_APPLICATION = n\nCONFIG_RTW_REPEATER_SON = n\nCONFIG_RTW_WIFI_HAL = n\nCONFIG_ICMP_VOQ = n\nCONFIG_IP_R_MONITOR = n #arp VOQ and high rate\nCONFIG_RTW_DISABLE_HW_PDN = n\nCONFIG_RTW_IOT_CCK_PD_INIT = n\n########################## Debug ###########################\nCONFIG_RTW_DEBUG = y\n# default log level is _DRV_INFO_ = 4,\n# please refer to \"How_to_set_driver_debug_log_level.doc\" to set the available level.\nCONFIG_RTW_LOG_LEVEL = 4\n######################## Wake On Lan ##########################\nCONFIG_WOWLAN = n\n#bit2: deauth, bit1: unicast, bit0: magic pkt.\nCONFIG_WAKEUP_TYPE = 0x7\nCONFIG_WOW_LPS_MODE = default\n#bit0: disBBRF off, #bit1: Wireless remote controller (WRC)\nCONFIG_SUSPEND_TYPE = 0\nCONFIG_WOW_STA_MIX = n\nCONFIG_GPIO_WAKEUP = n\nCONFIG_WAKEUP_GPIO_IDX = default\nCONFIG_HIGH_ACTIVE_DEV2HST = n\n######### only for USB #########\nCONFIG_ONE_PIN_GPIO = n\nCONFIG_HIGH_ACTIVE_HST2DEV = n\nCONFIG_PNO_SUPPORT = n\nCONFIG_PNO_SET_DEBUG = n\nCONFIG_AP_WOWLAN = n\n######### Notify SDIO Host Keep Power During Syspend ##########\nCONFIG_RTW_SDIO_PM_KEEP_POWER = y\n###################### MP HW TX MODE FOR VHT #######################\nCONFIG_MP_VHT_HW_TX_MODE = n\n###################### Platform Related #######################\nCONFIG_PLATFORM_I386_PC = y\nCONFIG_PLATFORM_ANDROID_X86 = n\nCONFIG_PLATFORM_ANDROID_INTEL_X86 = n\nCONFIG_PLATFORM_JB_X86 = n\nCONFIG_PLATFORM_ARM_S3C2K4 = n\nCONFIG_PLATFORM_ARM_PXA2XX = n\nCONFIG_PLATFORM_ARM_S3C6K4 = n\nCONFIG_PLATFORM_MIPS_RMI = n\nCONFIG_PLATFORM_RTD2880B = n\nCONFIG_PLATFORM_MIPS_AR9132 = n\nCONFIG_PLATFORM_RTK_DMP = n\nCONFIG_PLATFORM_MIPS_PLM = n\nCONFIG_PLATFORM_MSTAR389 = n\nCONFIG_PLATFORM_MT53XX = n\nCONFIG_PLATFORM_ARM_MX51_241H = n\nCONFIG_PLATFORM_FS_MX61 = n\nCONFIG_PLATFORM_ACTIONS_ATJ227X = n\nCONFIG_PLATFORM_TEGRA3_CARDHU = n\nCONFIG_PLATFORM_TEGRA4_DALMORE = n\nCONFIG_PLATFORM_ARM_TCC8900 = n\nCONFIG_PLATFORM_ARM_TCC8920 = n\nCONFIG_PLATFORM_ARM_TCC8920_JB42 = n\nCONFIG_PLATFORM_ARM_TCC8930_JB42 = n\nCONFIG_PLATFORM_ARM_RK2818 = n\nCONFIG_PLATFORM_ARM_RK3066 = n\nCONFIG_PLATFORM_ARM_RK3188 = n\nCONFIG_PLATFORM_ARM_URBETTER = n\nCONFIG_PLATFORM_ARM_TI_PANDA = n\nCONFIG_PLATFORM_MIPS_JZ4760 = n\nCONFIG_PLATFORM_DMP_PHILIPS = n\nCONFIG_PLATFORM_MSTAR_TITANIA12 = n\nCONFIG_PLATFORM_MSTAR = n\nCONFIG_PLATFORM_SZEBOOK = n\nCONFIG_PLATFORM_ARM_SUNxI = n\nCONFIG_PLATFORM_ARM_SUN6I = n\nCONFIG_PLATFORM_ARM_SUN7I = n\nCONFIG_PLATFORM_ARM_SUN8I_W3P1 = n\nCONFIG_PLATFORM_ARM_SUN8I_W5P1 = n\nCONFIG_PLATFORM_ACTIONS_ATM702X = n\nCONFIG_PLATFORM_ACTIONS_ATV5201 = n\nCONFIG_PLATFORM_ACTIONS_ATM705X = n\nCONFIG_PLATFORM_ARM_SUN50IW1P1 = n\nCONFIG_PLATFORM_ARM_RTD299X = n\nCONFIG_PLATFORM_ARM_LGE = n\nCONFIG_PLATFORM_ARM_SPREADTRUM_6820 = n\nCONFIG_PLATFORM_ARM_SPREADTRUM_8810 = n\nCONFIG_PLATFORM_ARM_WMT = n\nCONFIG_PLATFORM_TI_DM365 = n\nCONFIG_PLATFORM_MOZART = n\nCONFIG_PLATFORM_RTK119X = n\nCONFIG_PLATFORM_RTK119X_AM = n\nCONFIG_PLATFORM_RTK129X = n\nCONFIG_PLATFORM_RTK390X = n\nCONFIG_PLATFORM_NOVATEK_NT72668 = n\nCONFIG_PLATFORM_HISILICON = n\nCONFIG_PLATFORM_HISILICON_HI3798 = n\nCONFIG_PLATFORM_NV_TK1 = n\nCONFIG_PLATFORM_NV_TK1_UBUNTU = n\nCONFIG_PLATFORM_RTL8197D = n\nCONFIG_PLATFORM_AML_S905 = n\nCONFIG_PLATFORM_ZTE_ZX296716 = n\n########### CUSTOMER ################################\nCONFIG_CUSTOMER_HUAWEI_GENERAL = n\n\nCONFIG_DRVEXT_MODULE = n\n\nexport TopDIR ?= $(shell pwd)\n\n########### COMMON  #################################\nifeq ($(CONFIG_GSPI_HCI), y)\nHCI_NAME = gspi\nendif\n\nifeq ($(CONFIG_SDIO_HCI), y)\nHCI_NAME = sdio\nendif\n\nifeq ($(CONFIG_USB_HCI), y)\nHCI_NAME = usb\nendif\n\nifeq ($(CONFIG_PCI_HCI), y)\nHCI_NAME = pci\nendif\n\n\n_OS_INTFS_FILES :=\tos_dep/osdep_service.o \\\n\t\t\tos_dep/linux/os_intfs.o \\\n\t\t\tos_dep/linux/$(HCI_NAME)_intf.o \\\n\t\t\tos_dep/linux/$(HCI_NAME)_ops_linux.o \\\n\t\t\tos_dep/linux/ioctl_linux.o \\\n\t\t\tos_dep/linux/xmit_linux.o \\\n\t\t\tos_dep/linux/mlme_linux.o \\\n\t\t\tos_dep/linux/recv_linux.o \\\n\t\t\tos_dep/linux/ioctl_cfg80211.o \\\n\t\t\tos_dep/linux/rtw_cfgvendor.o \\\n\t\t\tos_dep/linux/wifi_regd.o \\\n\t\t\tos_dep/linux/rtw_android.o \\\n\t\t\tos_dep/linux/rtw_proc.o \\\n\t\t\tos_dep/linux/rtw_rhashtable.o\n\nifeq ($(CONFIG_MP_INCLUDED), y)\n_OS_INTFS_FILES += os_dep/linux/ioctl_mp.o\nendif\n\nifeq ($(CONFIG_SDIO_HCI), y)\n_OS_INTFS_FILES += os_dep/linux/custom_gpio_linux.o\n_OS_INTFS_FILES += os_dep/linux/$(HCI_NAME)_ops_linux.o\nendif\n\nifeq ($(CONFIG_GSPI_HCI), y)\n_OS_INTFS_FILES += os_dep/linux/custom_gpio_linux.o\n_OS_INTFS_FILES += os_dep/linux/$(HCI_NAME)_ops_linux.o\nendif\n\n\n_HAL_INTFS_FILES :=\thal/hal_intf.o \\\n\t\t\thal/hal_com.o \\\n\t\t\thal/hal_com_phycfg.o \\\n\t\t\thal/hal_phy.o \\\n\t\t\thal/hal_dm.o \\\n\t\t\thal/hal_dm_acs.o \\\n\t\t\thal/hal_btcoex_wifionly.o \\\n\t\t\thal/hal_btcoex.o \\\n\t\t\thal/hal_mp.o \\\n\t\t\thal/hal_mcc.o \\\n\t\t\thal/hal_hci/hal_$(HCI_NAME).o \\\n\t\t\thal/led/hal_led.o \\\n\t\t\thal/led/hal_$(HCI_NAME)_led.o\n\n\nEXTRA_CFLAGS += -I$(src)/platform\n_PLATFORM_FILES := platform/platform_ops.o\n\nEXTRA_CFLAGS += -I$(src)/hal/btc\n\n########### HAL_RTL8188E #################################\nifeq ($(CONFIG_RTL8188E), y)\n\nRTL871X = rtl8188e\nifeq ($(CONFIG_SDIO_HCI), y)\nMODULE_NAME = 8189es\nendif\n\nifeq ($(CONFIG_GSPI_HCI), y)\nMODULE_NAME = 8189es\nendif\n\nifeq ($(CONFIG_USB_HCI), y)\nMODULE_NAME = 8188eu\nendif\n\nifeq ($(CONFIG_PCI_HCI), y)\nMODULE_NAME = 8188ee\nendif\nEXTRA_CFLAGS += -DCONFIG_RTL8188E\n\n_HAL_INTFS_FILES +=\thal/HalPwrSeqCmd.o \\\n\t\t\t\t\thal/$(RTL871X)/Hal8188EPwrSeq.o\\\n \t\t\t\t\thal/$(RTL871X)/$(RTL871X)_xmit.o\\\n\t\t\t\t\thal/$(RTL871X)/$(RTL871X)_sreset.o\n\n_HAL_INTFS_FILES +=\thal/$(RTL871X)/$(RTL871X)_hal_init.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_phycfg.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rf6052.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_dm.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rxdesc.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_cmd.o \\\n\t\t\thal/$(RTL871X)/hal8188e_s_fw.o \\\n\t\t\thal/$(RTL871X)/hal8188e_t_fw.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o\n\nifeq ($(CONFIG_SDIO_HCI), y)\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o\nelse\nifeq ($(CONFIG_GSPI_HCI), y)\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o\nelse\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o\nendif\nendif\n\nifeq ($(CONFIG_USB_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_USB.o\nendif\nifeq ($(CONFIG_PCI_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_PCIE.o\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_SDIO.o\nendif\n\nendif\n\n########### HAL_RTL8192E #################################\nifeq ($(CONFIG_RTL8192E), y)\n\nRTL871X = rtl8192e\nifeq ($(CONFIG_SDIO_HCI), y)\nMODULE_NAME = 8192es\nendif\n\nifeq ($(CONFIG_USB_HCI), y)\nMODULE_NAME = 8192eu\nendif\n\nifeq ($(CONFIG_PCI_HCI), y)\nMODULE_NAME = 8192ee\nendif\nEXTRA_CFLAGS += -DCONFIG_RTL8192E\n_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \\\n\t\t\t\t\thal/$(RTL871X)/Hal8192EPwrSeq.o\\\n\t\t\t\t\thal/$(RTL871X)/$(RTL871X)_xmit.o\\\n\t\t\t\t\thal/$(RTL871X)/$(RTL871X)_sreset.o\n\n_HAL_INTFS_FILES +=\thal/$(RTL871X)/$(RTL871X)_hal_init.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_phycfg.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rf6052.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_dm.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rxdesc.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_cmd.o \\\n\t\t\thal/$(RTL871X)/hal8192e_fw.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o\n\nifeq ($(CONFIG_SDIO_HCI), y)\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o\nelse\nifeq ($(CONFIG_GSPI_HCI), y)\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o\nelse\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o\nendif\nendif\n\nifeq ($(CONFIG_USB_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_USB.o\nendif\nifeq ($(CONFIG_PCI_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_PCIE.o\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_SDIO.o\nendif\n\nifeq ($(CONFIG_BT_COEXIST), y)\n_BTC_FILES += hal/btc/halbtc8192e1ant.o \\\n\t\t\t\thal/btc/halbtc8192e2ant.o\nendif\n\nendif\n\n########### HAL_RTL8812A_RTL8821A #################################\n\nifneq ($(CONFIG_RTL8812A)_$(CONFIG_RTL8821A), n_n)\n\nRTL871X = rtl8812a\nifeq ($(CONFIG_USB_HCI), y)\nMODULE_NAME = 8812au\nendif\nifeq ($(CONFIG_PCI_HCI), y)\nMODULE_NAME = 8812ae\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\nMODULE_NAME = 8812as\nendif\n\n_HAL_INTFS_FILES +=  hal/HalPwrSeqCmd.o \\\n\t\t\t\t\thal/$(RTL871X)/Hal8812PwrSeq.o \\\n\t\t\t\t\thal/$(RTL871X)/Hal8821APwrSeq.o\\\n\t\t\t\t\thal/$(RTL871X)/$(RTL871X)_xmit.o\\\n\t\t\t\t\thal/$(RTL871X)/$(RTL871X)_sreset.o\n\n_HAL_INTFS_FILES +=\thal/$(RTL871X)/$(RTL871X)_hal_init.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_phycfg.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rf6052.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_dm.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rxdesc.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_cmd.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o\n\nifeq ($(CONFIG_SDIO_HCI), y)\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o\nelse\nifeq ($(CONFIG_GSPI_HCI), y)\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o\nelse\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o\nendif\nendif\n\nifeq ($(CONFIG_RTL8812A), y)\nifeq ($(CONFIG_USB_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8812A_USB.o\nendif\nifeq ($(CONFIG_PCI_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8812A_PCIE.o\nendif\nendif\nifeq ($(CONFIG_RTL8821A), y)\nifeq ($(CONFIG_USB_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_USB.o\nendif\nifeq ($(CONFIG_PCI_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_PCIE.o\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_SDIO.o\nendif\nendif\n\nifeq ($(CONFIG_RTL8812A), y)\nEXTRA_CFLAGS += -DCONFIG_RTL8812A\n_HAL_INTFS_FILES +=\thal/rtl8812a/hal8812a_fw.o\nendif\n\nifeq ($(CONFIG_RTL8821A), y)\n\nifeq ($(CONFIG_RTL8812A), n)\n\nRTL871X = rtl8821a\nifeq ($(CONFIG_USB_HCI), y)\nifeq ($(CONFIG_BT_COEXIST), y)\nMODULE_NAME := 8821au\nelse\nMODULE_NAME := 8811au\nendif\nendif\nifeq ($(CONFIG_PCI_HCI), y)\nMODULE_NAME := 8821ae\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\nMODULE_NAME := 8821as\nendif\n\nendif\n\nEXTRA_CFLAGS += -DCONFIG_RTL8821A\n\n_HAL_INTFS_FILES +=\thal/rtl8812a/hal8821a_fw.o\n\t\t\nendif\n\nifeq ($(CONFIG_BT_COEXIST), y)\nifeq ($(CONFIG_RTL8812A), y)\n_BTC_FILES += hal/btc/halbtc8812a1ant.o \\\n\t\t\t\thal/btc/halbtc8812a2ant.o\nendif\nifeq ($(CONFIG_RTL8821A), y)\n_BTC_FILES += hal/btc/halbtc8821a1ant.o \\\n\t\t\t\thal/btc/halbtc8821a2ant.o\nendif\nendif\n\nendif\n\n########### HAL_RTL8723B #################################\nifeq ($(CONFIG_RTL8723B), y)\n\nRTL871X = rtl8723b\nifeq ($(CONFIG_USB_HCI), y)\nMODULE_NAME = 8723bu\nendif\nifeq ($(CONFIG_PCI_HCI), y)\nMODULE_NAME = 8723be\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\nMODULE_NAME = 8723bs\nendif\n\nEXTRA_CFLAGS += -DCONFIG_RTL8723B\n\n_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \\\n\t\t\t\t\thal/$(RTL871X)/Hal8723BPwrSeq.o\\\n\t\t\t\t\thal/$(RTL871X)/$(RTL871X)_sreset.o\n\n_HAL_INTFS_FILES +=\thal/$(RTL871X)/$(RTL871X)_hal_init.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_phycfg.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rf6052.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_dm.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rxdesc.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_cmd.o \\\n\t\t\thal/$(RTL871X)/hal8723b_fw.o\n\n_HAL_INTFS_FILES +=\t\\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o\n\nifeq ($(CONFIG_PCI_HCI), y)\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o\nelse\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o\nendif\n\nifeq ($(CONFIG_USB_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_USB.o\nendif\nifeq ($(CONFIG_PCI_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_PCIE.o\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_SDIO.o\nendif\n\n_BTC_FILES += hal/btc/halbtc8723bwifionly.o\nifeq ($(CONFIG_BT_COEXIST), y)\n_BTC_FILES += hal/btc/halbtc8723b1ant.o \\\n\t\t\t\thal/btc/halbtc8723b2ant.o\nendif\n\nendif\n\n########### HAL_RTL8814A #################################\nifeq ($(CONFIG_RTL8814A), y)\n## ADD NEW VHT MP HW TX MODE ##\n#EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE\n#CONFIG_MP_VHT_HW_TX_MODE = y\n##########################################\nRTL871X = rtl8814a\nifeq ($(CONFIG_USB_HCI), y)\nMODULE_NAME = 8814au\nendif\nifeq ($(CONFIG_PCI_HCI), y)\nMODULE_NAME = 8814ae\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\nMODULE_NAME = 8814as\nendif\n\nEXTRA_CFLAGS += -DCONFIG_RTL8814A\n\n_HAL_INTFS_FILES +=  hal/HalPwrSeqCmd.o \\\n\t\t\t\t\thal/$(RTL871X)/Hal8814PwrSeq.o \\\n\t\t\t\t\thal/$(RTL871X)/$(RTL871X)_xmit.o\\\n\t\t\t\t\thal/$(RTL871X)/$(RTL871X)_sreset.o\n\n_HAL_INTFS_FILES +=\thal/$(RTL871X)/$(RTL871X)_hal_init.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_phycfg.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rf6052.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_dm.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rxdesc.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_cmd.o \\\n\t\t\thal/$(RTL871X)/hal8814a_fw.o\n\n\n_HAL_INTFS_FILES +=\t\\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o\n\nifeq ($(CONFIG_SDIO_HCI), y)\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o\nelse\nifeq ($(CONFIG_GSPI_HCI), y)\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o\nelse\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o\nendif\nendif\n\nifeq ($(CONFIG_USB_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8814A_USB.o\nendif\nifeq ($(CONFIG_PCI_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8814A_PCIE.o\nendif\n\nifeq ($(CONFIG_BT_COEXIST), y)\n_BTC_FILES += hal/btc/halbtc8814a2ant.o\nendif\nendif\n\n########### HAL_RTL8723C #################################\nifeq ($(CONFIG_RTL8723C), y)\n\nRTL871X = rtl8703b\nifeq ($(CONFIG_USB_HCI), y)\nMODULE_NAME = 8723cu\nMODULE_SUB_NAME = 8703bu\nendif\nifeq ($(CONFIG_PCI_HCI), y)\nMODULE_NAME = 8723ce\nMODULE_SUB_NAME = 8703be\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\nMODULE_NAME = 8723cs\nMODULE_SUB_NAME = 8703bs\nendif\n\nEXTRA_CFLAGS += -DCONFIG_RTL8703B\n\n_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \\\n\t\t\t\t\thal/$(RTL871X)/Hal8703BPwrSeq.o\\\n\t\t\t\t\thal/$(RTL871X)/$(RTL871X)_sreset.o\n\n_HAL_INTFS_FILES +=\thal/$(RTL871X)/$(RTL871X)_hal_init.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_phycfg.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rf6052.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_dm.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rxdesc.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_cmd.o \\\n\t\t\thal/$(RTL871X)/hal8703b_fw.o\n\n_HAL_INTFS_FILES +=\t\\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o\n\nifeq ($(CONFIG_PCI_HCI), y)\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o\nelse\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o\nendif\n\nifeq ($(CONFIG_USB_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8703B_USB.o\nendif\nifeq ($(CONFIG_PCI_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8703B_PCIE.o\nendif\n\nifeq ($(CONFIG_BT_COEXIST), y)\n_BTC_FILES += hal/btc/halbtc8703b1ant.o\nendif\n\nendif\n\n########### HAL_RTL8723D #################################\nifeq ($(CONFIG_RTL8723D), y)\n\nRTL871X = rtl8723d\nifeq ($(CONFIG_USB_HCI), y)\nMODULE_NAME = 8723du\nMODULE_SUB_NAME = 8723du\nendif\nifeq ($(CONFIG_PCI_HCI), y)\nMODULE_NAME = 8723de\nMODULE_SUB_NAME = 8723de\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\nMODULE_NAME = 8723ds\nMODULE_SUB_NAME = 8723ds\nendif\n\nEXTRA_CFLAGS += -DCONFIG_RTL8723D\n\n_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \\\n\t\t\t\t\thal/$(RTL871X)/Hal8723DPwrSeq.o\\\n\t\t\t\t\thal/$(RTL871X)/$(RTL871X)_sreset.o\n\n_HAL_INTFS_FILES +=\thal/$(RTL871X)/$(RTL871X)_hal_init.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_phycfg.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rf6052.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_dm.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rxdesc.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_cmd.o \\\n\t\t\thal/$(RTL871X)/hal8723d_fw.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_lps_poff.o\n\n\n_HAL_INTFS_FILES +=\t\\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o\n\nifeq ($(CONFIG_PCI_HCI), y)\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o\nelse\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o\nendif\n\nifeq ($(CONFIG_USB_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723D_USB.o\nendif\nifeq ($(CONFIG_PCI_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723D_PCIE.o\nendif\n\nifeq ($(CONFIG_BT_COEXIST), y)\n_BTC_FILES += hal/btc/halbtc8723d1ant.o \\\n\t\t\t\thal/btc/halbtc8723d2ant.o\nendif\n\nendif\n\n########### HAL_RTL8188F #################################\nifeq ($(CONFIG_RTL8188F), y)\n\nRTL871X = rtl8188f\nifeq ($(CONFIG_USB_HCI), y)\nMODULE_NAME = 8188fu\nendif\nifeq ($(CONFIG_PCI_HCI), y)\nMODULE_NAME = 8188fe\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\nMODULE_NAME = 8189fs\nendif\n\nEXTRA_CFLAGS += -DCONFIG_RTL8188F\n\n_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \\\n\t\t\t\t\thal/$(RTL871X)/Hal8188FPwrSeq.o\\\n\t\t\t\t\thal/$(RTL871X)/$(RTL871X)_sreset.o\n\n_HAL_INTFS_FILES +=\thal/$(RTL871X)/$(RTL871X)_hal_init.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_phycfg.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rf6052.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_dm.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rxdesc.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_cmd.o \\\n\t\t\thal/$(RTL871X)/hal8188f_fw.o\n\n_HAL_INTFS_FILES +=\t\\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o\n\nifeq ($(CONFIG_PCI_HCI), y)\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o\nelse\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o\nendif\n\nifeq ($(CONFIG_USB_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188F_USB.o\nendif\n\nifeq ($(CONFIG_SDIO_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188F_SDIO.o\nendif\n\nendif\n\n########### HAL_RTL8188GTV #################################\nifeq ($(CONFIG_RTL8188GTV), y)\n\nRTL871X = rtl8188gtv\nifeq ($(CONFIG_USB_HCI), y)\nMODULE_NAME = 8188gtvu\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\nMODULE_NAME = 8189gtvs\nendif\n\nEXTRA_CFLAGS += -DCONFIG_RTL8188GTV\n\n_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \\\n\t\t\t\t\thal/$(RTL871X)/Hal8188GTVPwrSeq.o\\\n\t\t\t\t\thal/$(RTL871X)/$(RTL871X)_sreset.o\n\n_HAL_INTFS_FILES +=\thal/$(RTL871X)/$(RTL871X)_hal_init.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_phycfg.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rf6052.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_dm.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rxdesc.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_cmd.o \\\n\t\t\thal/$(RTL871X)/hal8188gtv_fw.o\n\n_HAL_INTFS_FILES +=\t\\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o\n\nifeq ($(CONFIG_PCI_HCI), y)\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o\nelse\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o\nendif\n\nifeq ($(CONFIG_USB_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188GTV_USB.o\nendif\n\nifeq ($(CONFIG_SDIO_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188GTV_SDIO.o\nendif\n\nendif\n\n########### HAL_RTL8822B #################################\nifeq ($(CONFIG_RTL8822B), y)\nRTL871X := rtl8822b\nifeq ($(CONFIG_USB_HCI), y)\nifeq ($(CONFIG_BT_COEXIST), n)\nMODULE_NAME = 8812bu\nelse\nMODULE_NAME = 88x2bu\nendif\nendif\nifeq ($(CONFIG_PCI_HCI), y)\nMODULE_NAME = 88x2be\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\nMODULE_NAME = 88x2bs\nendif\n\nendif\n########### HAL_RTL8821C #################################\nifeq ($(CONFIG_RTL8821C), y)\nRTL871X := rtl8821c\nifeq ($(CONFIG_USB_HCI), y)\nMODULE_NAME = 8821cu\nendif\nifeq ($(CONFIG_PCI_HCI), y)\nMODULE_NAME = 8821ce\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\nMODULE_NAME = 8821cs\nendif\n\nendif\n\n########### HAL_RTL8710B #################################\nifeq ($(CONFIG_RTL8710B), y)\n\nRTL871X = rtl8710b\nifeq ($(CONFIG_USB_HCI), y)\nMODULE_NAME = 8710bu\nMODULE_SUB_NAME = 8710bu\nendif\n\nEXTRA_CFLAGS += -DCONFIG_RTL8710B\n\n_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \\\n\t\t\t\t\thal/$(RTL871X)/Hal8710BPwrSeq.o\\\n\t\t\t\t\thal/$(RTL871X)/$(RTL871X)_sreset.o\n\n_HAL_INTFS_FILES +=\thal/$(RTL871X)/$(RTL871X)_hal_init.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_phycfg.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rf6052.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_dm.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rxdesc.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_cmd.o \\\n\t\t\thal/$(RTL871X)/hal8710b_fw.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_lps_poff.o\n\n\n_HAL_INTFS_FILES +=\t\\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o\n\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o\n\nifeq ($(CONFIG_USB_HCI), y)\n_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8710B_USB.o\nendif\n\nendif\n\n########### HAL_RTL8192F #################################\nifeq ($(CONFIG_RTL8192F), y)\n\nRTL871X = rtl8192f\nifeq ($(CONFIG_USB_HCI), y)\nMODULE_NAME = 8192fu\nMODULE_SUB_NAME = 8192fu\nendif\nifeq ($(CONFIG_PCI_HCI), y)\nMODULE_NAME = 8192fe\nMODULE_SUB_NAME = 8192fe\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\nMODULE_NAME = 8192fs\nMODULE_SUB_NAME = 8192fs\nendif\n\nEXTRA_CFLAGS += -DCONFIG_RTL8192F\n\n_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \\\n\t\t\t\t\thal/$(RTL871X)/Hal8192FPwrSeq.o\\\n\t\t\t\t\thal/$(RTL871X)/$(RTL871X)_sreset.o\n\n_HAL_INTFS_FILES +=\thal/$(RTL871X)/$(RTL871X)_hal_init.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_phycfg.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rf6052.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_dm.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_rxdesc.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_cmd.o \\\n\t\t\thal/$(RTL871X)/hal8192f_fw.o \\\n\t\t\thal/$(RTL871X)/$(RTL871X)_lps_poff.o\n\n\n_HAL_INTFS_FILES +=\t\\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \\\n\t\t\thal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o\n\t\t\t\nifeq ($(CONFIG_PCI_HCI), y)\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o\nelse\n_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o\nendif\n\nifeq ($(CONFIG_SDIO_HCI), y)\n_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_SDIO.o\nendif\n\nifeq ($(CONFIG_USB_HCI), y)\n_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_USB.o\nendif\n\nifeq ($(CONFIG_PCI_HCI), y)\n_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_PCIE.o\nendif\n\nendif\n\n########### HAL_RTL8822C #################################\nifeq ($(CONFIG_RTL8822C), y)\nRTL871X := rtl8822c\nifeq ($(CONFIG_USB_HCI), y)\nifeq ($(CONFIG_BT_COEXIST), n)\nMODULE_NAME = 8812cu\nelse\nMODULE_NAME = 88x2cu\nendif\nendif\nifeq ($(CONFIG_PCI_HCI), y)\nMODULE_NAME = rtl88x2ce\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\nMODULE_NAME = 88x2cs\nendif\n\nendif\n\n########### AUTO_CFG  #################################\n\nifeq ($(CONFIG_AUTOCFG_CP), y)\n\nifeq ($(CONFIG_MULTIDRV), y)\n$(shell cp $(TopDIR)/autoconf_multidrv_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)\nelse\nifeq ($(CONFIG_RTL8188E)$(CONFIG_SDIO_HCI),yy)\n$(shell cp $(TopDIR)/autoconf_rtl8189e_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)\nelse ifeq ($(CONFIG_RTL8188F)$(CONFIG_SDIO_HCI),yy)\n$(shell cp $(TopDIR)/autoconf_rtl8189f_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)\nelse ifeq ($(CONFIG_RTL8723C),y)\n$(shell cp $(TopDIR)/autoconf_rtl8723c_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)\nelse\n$(shell cp $(TopDIR)/autoconf_$(RTL871X)_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)\nendif\nendif\n\nendif\n\n########### END OF PATH  #################################\n\nifeq ($(CONFIG_USB_HCI), y)\nifeq ($(CONFIG_USB_AUTOSUSPEND), y)\nEXTRA_CFLAGS += -DCONFIG_USB_AUTOSUSPEND\nendif\nendif\n\nifeq ($(CONFIG_MP_INCLUDED), y)\n#MODULE_NAME := $(MODULE_NAME)_mp\nEXTRA_CFLAGS += -DCONFIG_MP_INCLUDED\nendif\n\nifeq ($(CONFIG_POWER_SAVING), y)\nifneq ($(CONFIG_IPS_MODE), default)\nEXTRA_CFLAGS += -DRTW_IPS_MODE=$(CONFIG_IPS_MODE)\nendif\nifneq ($(CONFIG_LPS_MODE), default)\nEXTRA_CFLAGS += -DRTW_LPS_MODE=$(CONFIG_LPS_MODE)\nendif\nifneq ($(CONFIG_WOW_LPS_MODE), default)\nEXTRA_CFLAGS += -DRTW_WOW_LPS_MODE=$(CONFIG_WOW_LPS_MODE)\nendif\nEXTRA_CFLAGS += -DCONFIG_POWER_SAVING\nendif\n\nifeq ($(CONFIG_HW_PWRP_DETECTION), y)\nEXTRA_CFLAGS += -DCONFIG_HW_PWRP_DETECTION\nendif\n\nifeq ($(CONFIG_BT_COEXIST), y)\nEXTRA_CFLAGS += -DCONFIG_BT_COEXIST\nendif\n\nifeq ($(CONFIG_WAPI_SUPPORT), y)\nEXTRA_CFLAGS += -DCONFIG_WAPI_SUPPORT\nendif\n\n\nifeq ($(CONFIG_EFUSE_CONFIG_FILE), y)\nEXTRA_CFLAGS += -DCONFIG_EFUSE_CONFIG_FILE\n\n#EFUSE_MAP_PATH\nUSER_EFUSE_MAP_PATH ?=\nifneq ($(USER_EFUSE_MAP_PATH),)\nEXTRA_CFLAGS += -DEFUSE_MAP_PATH=\\\"$(USER_EFUSE_MAP_PATH)\\\"\nelse ifeq ($(MODULE_NAME), 8189es)\nEXTRA_CFLAGS += -DEFUSE_MAP_PATH=\\\"/system/etc/wifi/wifi_efuse_8189e.map\\\"\nelse ifeq ($(MODULE_NAME), 8723bs)\nEXTRA_CFLAGS += -DEFUSE_MAP_PATH=\\\"/system/etc/wifi/wifi_efuse_8723bs.map\\\"\nelse\nEXTRA_CFLAGS += -DEFUSE_MAP_PATH=\\\"/system/etc/wifi/wifi_efuse_$(MODULE_NAME).map\\\"\nendif\n\n#WIFIMAC_PATH\nUSER_WIFIMAC_PATH ?=\nifneq ($(USER_WIFIMAC_PATH),)\nEXTRA_CFLAGS += -DWIFIMAC_PATH=\\\"$(USER_WIFIMAC_PATH)\\\"\nelse\nEXTRA_CFLAGS += -DWIFIMAC_PATH=\\\"/data/wifimac.txt\\\"\nendif\n\nendif\n\nifeq ($(CONFIG_EXT_CLK), y)\nEXTRA_CFLAGS += -DCONFIG_EXT_CLK\nendif\n\nifeq ($(CONFIG_TRAFFIC_PROTECT), y)\nEXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT\nendif\n\nifeq ($(CONFIG_LOAD_PHY_PARA_FROM_FILE), y)\nEXTRA_CFLAGS += -DCONFIG_LOAD_PHY_PARA_FROM_FILE\n#EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER\nEXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\\\"/lib/firmware/\\\"\nendif\n\nifeq ($(CONFIG_TXPWR_BY_RATE), n)\nEXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE=0\nelse ifeq ($(CONFIG_TXPWR_BY_RATE), y)\nEXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE=1\nendif\nifeq ($(CONFIG_TXPWR_BY_RATE_EN), n)\nEXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=0\nelse ifeq ($(CONFIG_TXPWR_BY_RATE_EN), y)\nEXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=1\nelse ifeq ($(CONFIG_TXPWR_BY_RATE_EN), auto)\nEXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=2\nendif\n\nifeq ($(CONFIG_TXPWR_LIMIT), n)\nEXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT=0\nelse ifeq ($(CONFIG_TXPWR_LIMIT), y)\nEXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT=1\nendif\nifeq ($(CONFIG_TXPWR_LIMIT_EN), n)\nEXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=0\nelse ifeq ($(CONFIG_TXPWR_LIMIT_EN), y)\nEXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=1\nelse ifeq ($(CONFIG_TXPWR_LIMIT_EN), auto)\nEXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=2\nendif\n\nifneq ($(CONFIG_RTW_CHPLAN), 0xFF)\nEXTRA_CFLAGS += -DCONFIG_RTW_CHPLAN=$(CONFIG_RTW_CHPLAN)\nendif\n\nifeq ($(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY), y)\nEXTRA_CFLAGS += -DCONFIG_CALIBRATE_TX_POWER_BY_REGULATORY\nendif\n\nifeq ($(CONFIG_CALIBRATE_TX_POWER_TO_MAX), y)\nEXTRA_CFLAGS += -DCONFIG_CALIBRATE_TX_POWER_TO_MAX\nendif\n\nifeq ($(CONFIG_RTW_ADAPTIVITY_EN), disable)\nEXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_EN=0\nelse ifeq ($(CONFIG_RTW_ADAPTIVITY_EN), enable)\nEXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_EN=1\nendif\n\nifeq ($(CONFIG_RTW_ADAPTIVITY_MODE), normal)\nEXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_MODE=0\nelse ifeq ($(CONFIG_RTW_ADAPTIVITY_MODE), carrier_sense)\nEXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_MODE=1\nendif\n\nifeq ($(CONFIG_SIGNAL_SCALE_MAPPING), y)\nEXTRA_CFLAGS += -DCONFIG_SIGNAL_SCALE_MAPPING\nendif\n\nifeq ($(CONFIG_80211W), y)\nEXTRA_CFLAGS += -DCONFIG_IEEE80211W\nendif\n\nifeq ($(CONFIG_WOWLAN), y)\nEXTRA_CFLAGS += -DCONFIG_WOWLAN -DRTW_WAKEUP_EVENT=$(CONFIG_WAKEUP_TYPE)\nEXTRA_CFLAGS += -DRTW_SUSPEND_TYPE=$(CONFIG_SUSPEND_TYPE)\nifeq ($(CONFIG_WOW_STA_MIX), y)\nEXTRA_CFLAGS += -DRTW_WOW_STA_MIX\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER\nendif\nendif\n\nifeq ($(CONFIG_AP_WOWLAN), y)\nEXTRA_CFLAGS += -DCONFIG_AP_WOWLAN\nifeq ($(CONFIG_SDIO_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER\nendif\nendif\n\nifeq ($(CONFIG_PNO_SUPPORT), y)\nEXTRA_CFLAGS += -DCONFIG_PNO_SUPPORT\nifeq ($(CONFIG_PNO_SET_DEBUG), y)\nEXTRA_CFLAGS += -DCONFIG_PNO_SET_DEBUG\nendif\nendif\n\nifeq ($(CONFIG_GPIO_WAKEUP), y)\nEXTRA_CFLAGS += -DCONFIG_GPIO_WAKEUP\nifeq ($(CONFIG_ONE_PIN_GPIO), y)\nEXTRA_CFLAGS += -DCONFIG_RTW_ONE_PIN_GPIO\nendif\nifeq ($(CONFIG_HIGH_ACTIVE_DEV2HST), y)\nEXTRA_CFLAGS += -DHIGH_ACTIVE_DEV2HST=1\nelse\nEXTRA_CFLAGS += -DHIGH_ACTIVE_DEV2HST=0\nendif\nendif\n\nifeq ($(CONFIG_HIGH_ACTIVE_HST2DEV), y)\nEXTRA_CFLAGS += -DHIGH_ACTIVE_HST2DEV=1\nelse\nEXTRA_CFLAGS += -DHIGH_ACTIVE_HST2DEV=0\nendif\n\nifneq ($(CONFIG_WAKEUP_GPIO_IDX), default)\nEXTRA_CFLAGS += -DWAKEUP_GPIO_IDX=$(CONFIG_WAKEUP_GPIO_IDX)\nendif\n\nifeq ($(CONFIG_RTW_SDIO_PM_KEEP_POWER), y)\nifeq ($(CONFIG_SDIO_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER\nendif\nendif\n\nifeq ($(CONFIG_REDUCE_TX_CPU_LOADING), y)\nEXTRA_CFLAGS += -DCONFIG_REDUCE_TX_CPU_LOADING\nendif\n\nifeq ($(CONFIG_BR_EXT), y)\nBR_NAME = br0\nEXTRA_CFLAGS += -DCONFIG_BR_EXT\nEXTRA_CFLAGS += '-DCONFIG_BR_EXT_BRNAME=\"'$(BR_NAME)'\"'\nendif\n\n\nifeq ($(CONFIG_TDLS), y)\nEXTRA_CFLAGS += -DCONFIG_TDLS\nendif\n\nifeq ($(CONFIG_WIFI_MONITOR), y)\nEXTRA_CFLAGS += -DCONFIG_WIFI_MONITOR\nendif\n\nifeq ($(CONFIG_MCC_MODE), y)\nEXTRA_CFLAGS += -DCONFIG_MCC_MODE\nendif\n\nifeq ($(CONFIG_RTW_NAPI), y)\nEXTRA_CFLAGS += -DCONFIG_RTW_NAPI\nendif\n\nifeq ($(CONFIG_RTW_GRO), y)\nEXTRA_CFLAGS += -DCONFIG_RTW_GRO\nendif\n\nifeq ($(CONFIG_RTW_REPEATER_SON), y)\nEXTRA_CFLAGS += -DCONFIG_RTW_REPEATER_SON\nendif\n\nifeq ($(CONFIG_RTW_IPCAM_APPLICATION), y)\nEXTRA_CFLAGS += -DCONFIG_RTW_IPCAM_APPLICATION\nifeq ($(CONFIG_WIFI_MONITOR), n)\nEXTRA_CFLAGS += -DCONFIG_WIFI_MONITOR\nendif\nendif\n\nifeq ($(CONFIG_RTW_NETIF_SG), y)\nEXTRA_CFLAGS += -DCONFIG_RTW_NETIF_SG\nendif\n\nifeq ($(CONFIG_ICMP_VOQ), y)\nEXTRA_CFLAGS += -DCONFIG_ICMP_VOQ\nendif\n\nifeq ($(CONFIG_IP_R_MONITOR), y)\nEXTRA_CFLAGS += -DCONFIG_IP_R_MONITOR\nendif\n\nifeq ($(CONFIG_RTW_DISABLE_HW_PDN), y)\nEXTRA_CFLAGS += -DCONFIG_RTW_DISABLE_HW_PDN\nendif\n\nifeq ($(CONFIG_RTW_IOT_CCK_PD_INIT), y)\nEXTRA_CFLAGS += -DCONFIG_RTW_IOT_CCK_PD_INIT\nendif\n\nifeq ($(CONFIG_RTW_WIFI_HAL), y)\n#EXTRA_CFLAGS += -DCONFIG_RTW_WIFI_HAL_DEBUG\nEXTRA_CFLAGS += -DCONFIG_RTW_WIFI_HAL\nEXTRA_CFLAGS += -DCONFIG_RTW_CFGVEDNOR_LLSTATS\nEXTRA_CFLAGS += -DCONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI\nEXTRA_CFLAGS += -DCONFIG_RTW_CFGVEDNOR_RSSIMONITOR\nEXTRA_CFLAGS += -DCONFIG_RTW_CFGVENDOR_WIFI_LOGGER\nendif\n\nifeq ($(CONFIG_MP_VHT_HW_TX_MODE), y)\nEXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE\nifeq ($(CONFIG_PLATFORM_I386_PC), y)\n## For I386 X86 ToolChain use Hardware FLOATING\nEXTRA_CFLAGS += -mhard-float\nelse\n## For ARM ToolChain use Hardware FLOATING\nEXTRA_CFLAGS += -mfloat-abi=hard\nendif\nendif\n\nifeq ($(CONFIG_APPEND_VENDOR_IE_ENABLE), y)\nEXTRA_CFLAGS += -DCONFIG_APPEND_VENDOR_IE_ENABLE\nendif\n\nifeq ($(CONFIG_RTW_DEBUG), y)\nEXTRA_CFLAGS += -DCONFIG_RTW_DEBUG\nEXTRA_CFLAGS += -DRTW_LOG_LEVEL=$(CONFIG_RTW_LOG_LEVEL)\nendif\n\nEXTRA_CFLAGS += -DDM_ODM_SUPPORT_TYPE=0x04\n\nifeq ($(CONFIG_PLATFORM_I386_PC), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nSUBARCH := $(shell uname -m | sed -e s/i.86/i386/)\nARCH ?= $(SUBARCH)\nCROSS_COMPILE ?=\nKVER  := $(shell uname -r)\nKSRC := /lib/modules/$(KVER)/build\nMODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/\nINSTALL_PREFIX :=\nSTAGINGMODDIR := /lib/modules/$(KVER)/kernel/drivers/staging\nendif\n\nifeq ($(CONFIG_PLATFORM_NV_TK1), y)\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_NV_TK1\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\n# default setting for Android 4.1, 4.2\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_PLATFORM_ANDROID\n# Enable this for Android 5.0\nEXTRA_CFLAGS += -DCONFIG_RADIO_WORK\nEXTRA_CFLAGS += -DRTW_VENDOR_EXT_SUPPORT\nEXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC\nARCH ?= arm\n\nCROSS_COMPILE := /mnt/newdisk/android_sdk/nvidia_tk1/android_L/prebuilts/gcc/linux-x86/arm/arm-eabi-4.8/bin/arm-eabi-\nKSRC :=/mnt/newdisk/android_sdk/nvidia_tk1/android_L/out/target/product/shieldtablet/obj/KERNEL/\nMODULE_NAME = wlan\nendif\n\nifeq ($(CONFIG_PLATFORM_NV_TK1_UBUNTU), y)\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_NV_TK1\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\n\nARCH ?= arm\n\nCROSS_COMPILE ?=\nKVER := $(shell uname -r)\nKSRC := /lib/modules/$(KVER)/build\nMODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/\nINSTALL_PREFIX :=\nendif\n\nifeq ($(CONFIG_PLATFORM_ACTIONS_ATM702X), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ACTIONS_ATM702X\n#ARCH := arm\nARCH := $(R_ARCH)\n#CROSS_COMPILE := arm-none-linux-gnueabi-\nCROSS_COMPILE := $(R_CROSS_COMPILE)\nKVER:= 3.4.0\n#KSRC := ../../../../build/out/kernel\nKSRC := $(KERNEL_BUILD_PATH)\nMODULE_NAME :=wlan\nendif\n\n\nifeq ($(CONFIG_PLATFORM_ACTIONS_ATM705X), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\n#EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC\n# default setting for Android 4.1, 4.2, 4.3, 4.4\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_ACTIONS_ATM705X\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\n\n# Enable this for Android 5.0\nEXTRA_CFLAGS += -DCONFIG_RADIO_WORK\n\nifeq ($(CONFIG_SDIO_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS\n_PLATFORM_FILES += platform/platform_arm_act_sdio.o\nendif\n\nARCH := arm\nCROSS_COMPILE := /opt/arm-2011.09/bin/arm-none-linux-gnueabi-\nKSRC := /home/android_sdk/Action-semi/705a_android_L/android/kernel\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_SUN50IW1P1), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN50IW1P1\nEXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT\n# default setting for Android 4.1, 4.2\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nEXTRA_CFLAGS += -DCONFIG_RESUME_IN_WORKQUEUE\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS\n\n# Enable this for Android 5.0\nEXTRA_CFLAGS += -DCONFIG_RADIO_WORK\n\nifeq ($(CONFIG_USB_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX\n_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\n_PLATFORM_FILES += platform/platform_ARM_SUN50IW1P1_sdio.o\nendif\n\nARCH := arm64\n# ===Cross compile setting for Android 5.1(64) SDK ===\nCROSS_COMPILE := /home/android_sdk/Allwinner/a64/android-51/lichee/out/sun50iw1p1/android/common/buildroot/external-toolchain/bin/aarch64-linux-gnu-\nKSRC :=/home/android_sdk/Allwinner/a64/android-51/lichee/linux-3.10/\nendif\n\nifeq ($(CONFIG_PLATFORM_TI_AM3517), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_SHUTTLE\nCROSS_COMPILE := arm-eabi-\nKSRC := $(shell pwd)/../../../Android/kernel\nARCH := arm\nendif\n\nifeq ($(CONFIG_PLATFORM_MSTAR_TITANIA12), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR -DCONFIG_PLATFORM_MSTAR_TITANIA12\nARCH:=mips\nCROSS_COMPILE:= /usr/src/Mstar_kernel/mips-4.3/bin/mips-linux-gnu-\nKVER:= 2.6.28.9\nKSRC:= /usr/src/Mstar_kernel/2.6.28.9/\nendif\n\nifeq ($(CONFIG_PLATFORM_MSTAR), y)\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_MSTAR\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_MSTAR_HIGH\nifeq ($(CONFIG_USB_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX -DCONFIG_FIX_NR_BULKIN_BUFFER\nendif\nARCH:=arm\nCROSS_COMPILE:= /usr/src/bin/arm-none-linux-gnueabi-\nKVER:= 3.1.10\nKSRC:= /usr/src/Mstar_kernel/3.1.10/\nendif\n\nifeq ($(CONFIG_PLATFORM_ANDROID_X86), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nSUBARCH := $(shell uname -m | sed -e s/i.86/i386/)\nARCH := $(SUBARCH)\nCROSS_COMPILE := /media/DATA-2/android-x86/ics-x86_20120130/prebuilt/linux-x86/toolchain/i686-unknown-linux-gnu-4.2.1/bin/i686-unknown-linux-gnu-\nKSRC := /media/DATA-2/android-x86/ics-x86_20120130/out/target/product/generic_x86/obj/kernel\nMODULE_NAME :=wlan\nendif\n\nifeq ($(CONFIG_PLATFORM_ANDROID_INTEL_X86), y)\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_ANDROID_INTEL_X86\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_INTEL_BYT\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nEXTRA_CFLAGS += -DCONFIG_SKIP_SIGNAL_SCALE_MAPPING\nifeq ($(CONFIG_SDIO_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_RESUME_IN_WORKQUEUE\nendif\nendif\n\nifeq ($(CONFIG_PLATFORM_JB_X86), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nSUBARCH := $(shell uname -m | sed -e s/i.86/i386/)\nARCH := $(SUBARCH)\nCROSS_COMPILE := /home/android_sdk/android-x86_JB/prebuilts/gcc/linux-x86/x86/i686-linux-android-4.7/bin/i686-linux-android-\nKSRC := /home/android_sdk/android-x86_JB/out/target/product/x86/obj/kernel/\nMODULE_NAME :=wlan\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_PXA2XX), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nARCH := arm\nCROSS_COMPILE := arm-none-linux-gnueabi-\nKVER  := 2.6.34.1\nKSRC ?= /usr/src/linux-2.6.34.1\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_S3C2K4), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nARCH := arm\nCROSS_COMPILE := arm-linux-\nKVER  := 2.6.24.7_$(ARCH)\nKSRC := /usr/src/kernels/linux-$(KVER)\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_S3C6K4), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nARCH := arm\nCROSS_COMPILE := arm-none-linux-gnueabi-\nKVER  := 2.6.34.1\nKSRC ?= /usr/src/linux-2.6.34.1\nendif\n\nifeq ($(CONFIG_PLATFORM_RTD2880B), y)\nEXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTD2880B\nARCH:=\nCROSS_COMPILE:=\nKVER:=\nKSRC:=\nendif\n\nifeq ($(CONFIG_PLATFORM_MIPS_RMI), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nARCH:=mips\nCROSS_COMPILE:=mipsisa32r2-uclibc-\nKVER:=\nKSRC:= /root/work/kernel_realtek\nendif\n\nifeq ($(CONFIG_PLATFORM_MIPS_PLM), y)\nEXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN\nARCH:=mips\nCROSS_COMPILE:=mipsisa32r2-uclibc-\nKVER:=\nKSRC:= /root/work/kernel_realtek\nendif\n\nifeq ($(CONFIG_PLATFORM_MSTAR389), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR389\nARCH:=mips\nCROSS_COMPILE:= mips-linux-gnu-\nKVER:= 2.6.28.10\nKSRC:= /home/mstar/mstar_linux/2.6.28.9/\nendif\n\nifeq ($(CONFIG_PLATFORM_MIPS_AR9132), y)\nEXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN\nARCH := mips\nCROSS_COMPILE := mips-openwrt-linux-\nKSRC := /home/alex/test_openwrt/tmp/linux-2.6.30.9\nendif\n\nifeq ($(CONFIG_PLATFORM_DMP_PHILIPS), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM\nARCH := mips\n#CROSS_COMPILE:=/usr/local/msdk-4.3.6-mips-EL-2.6.12.6-0.9.30.3/bin/mipsel-linux-\nCROSS_COMPILE:=/usr/local/toolchain_mipsel/bin/mipsel-linux-\nKSRC ?=/usr/local/Jupiter/linux-2.6.12\nendif\n\nifeq ($(CONFIG_PLATFORM_RTK_DMP), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM  -DCONFIG_WIRELESS_EXT\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS\nifeq ($(CONFIG_USB_HCI), y)\n_PLATFORM_FILES += platform/platform_RTK_DMP_usb.o\nendif\nARCH:=mips\nCROSS_COMPILE:=mipsel-linux-\nKVER:=\nKSRC ?= /usr/src/DMP_Kernel/jupiter/linux-2.6.12\nendif\n\nifeq ($(CONFIG_PLATFORM_MT53XX), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MT53XX\nARCH:= arm\nCROSS_COMPILE:= arm11_mtk_le-\nKVER:= 2.6.27\nKSRC?= /proj/mtk00802/BD_Compare/BDP/Dev/BDP_V301/BDP_Linux/linux-2.6.27\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_MX51_241H), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_WISTRON_PLATFORM\nARCH := arm\nCROSS_COMPILE := /opt/freescale/usr/local/gcc-4.1.2-glibc-2.5-nptl-3/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-\nKVER  := 2.6.31\nKSRC ?= /lib/modules/2.6.31-770-g0e46b52/source\nendif\n\nifeq ($(CONFIG_PLATFORM_FS_MX61), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nARCH := arm\nCROSS_COMPILE := /home/share/CusEnv/FreeScale/arm-eabi-4.4.3/bin/arm-eabi-\nKSRC ?= /home/share/CusEnv/FreeScale/FS_kernel_env\nendif\n\n\n\nifeq ($(CONFIG_PLATFORM_ACTIONS_ATJ227X), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATJ227X\nARCH := mips\nCROSS_COMPILE := /home/cnsd4/project/actions/tools-2.6.27/bin/mipsel-linux-gnu-\nKVER  := 2.6.27\nKSRC := /home/cnsd4/project/actions/linux-2.6.27.28\nendif\n\nifeq ($(CONFIG_PLATFORM_TI_DM365), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_TI_DM365\nEXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_RX\nEXTRA_CFLAGS += -DCONFIG_SINGLE_XMIT_BUF -DCONFIG_SINGLE_RECV_BUF\nARCH := arm\n#CROSS_COMPILE := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/arm/v5t_le/bin/arm_v5t_le-\n#KSRC := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/lsp/ti-davinci/linux-dm365\nCROSS_COMPILE := /opt/montavista/pro5.0/devkit/arm/v5t_le/bin/arm-linux-\nKSRC:= /home/vivotek/lsp/DM365/kernel_platform/kernel/linux-2.6.18\nKERNELOUTPUT := ${PRODUCTDIR}/tmp\nKVER  := 2.6.18\nendif\n\nifeq ($(CONFIG_PLATFORM_MOZART), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MOZART\nARCH := arm\nCROSS_COMPILE := /home/vivotek/lsp/mozart3v2/Mozart3e_Toolchain/build_arm_nofpu/usr/bin/arm-linux-\nKVER  := $(shell uname -r)\nKSRC:= /opt/Vivotek/lsp/mozart3v2/kernel_platform/kernel/mozart_kernel-1.17\nKERNELOUTPUT := /home/pink/sample/ODM/IP8136W-VINT/tmp/kernel\nendif\n\nifeq ($(CONFIG_PLATFORM_TEGRA3_CARDHU), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\n# default setting for Android 4.1, 4.2\nEXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nARCH := arm\nCROSS_COMPILE := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-\nKSRC := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/out/target/product/cardhu/obj/KERNEL\nMODULE_NAME := wlan\nendif\n\nifeq ($(CONFIG_PLATFORM_TEGRA4_DALMORE), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\n# default setting for Android 4.1, 4.2\nEXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nARCH := arm\nCROSS_COMPILE := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-\nKSRC := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/out/target/product/dalmore/obj/KERNEL\nMODULE_NAME := wlan\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_TCC8900), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nARCH := arm\nCROSS_COMPILE := /home/android_sdk/Telechips/SDK_2304_20110613/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-\nKSRC := /home/android_sdk/Telechips/SDK_2304_20110613/kernel\nMODULE_NAME := wlan\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_TCC8920), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nARCH := arm\nCROSS_COMPILE := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-\nKSRC := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/kernel\nMODULE_NAME := wlan\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_TCC8920_JB42), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\n# default setting for Android 4.1, 4.2\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nARCH := arm\nCROSS_COMPILE := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-\nKSRC := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/kernel\nMODULE_NAME := wlan\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_RK2818), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS\nARCH := arm\nCROSS_COMPILE := /usr/src/release_fae_version/toolchain/arm-eabi-4.4.0/bin/arm-eabi-\nKSRC := /usr/src/release_fae_version/kernel25_A7_281x\nMODULE_NAME := wlan\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_RK3188), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS\n# default setting for Android 4.1, 4.2, 4.3, 4.4\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\n# default setting for Power control\nEXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC\nEXTRA_CFLAGS += -DRTW_SUPPORT_PLATFORM_SHUTDOWN\n# default setting for Special function\nARCH := arm\nCROSS_COMPILE := /home/android_sdk/Rockchip/Rk3188/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-\nKSRC := /home/android_sdk/Rockchip/Rk3188/kernel\nMODULE_NAME := wlan\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_RK3066), y)\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_RK3066\nEXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211\nifeq ($(CONFIG_SDIO_HCI), y)\nEXTRA_CFLAGS += -DRTW_SUPPORT_PLATFORM_SHUTDOWN\nendif\nEXTRA_CFLAGS += -fno-pic\nARCH := arm\nCROSS_COMPILE := /home/android_sdk/Rockchip/rk3066_20130607/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/bin/arm-linux-androideabi-\n#CROSS_COMPILE := /home/android_sdk/Rockchip/Rk3066sdk/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/bin/arm-linux-androideabi-\nKSRC := /home/android_sdk/Rockchip/Rk3066sdk/kernel\nMODULE_NAME :=wlan\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_URBETTER), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE\nARCH := arm\nCROSS_COMPILE := /media/DATA-1/urbetter/arm-2009q3/bin/arm-none-linux-gnueabi-\nKSRC := /media/DATA-1/urbetter/ics-urbetter/kernel\nMODULE_NAME := wlan\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_TI_PANDA), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE\nARCH := arm\n#CROSS_COMPILE := /media/DATA-1/aosp/ics-aosp_20111227/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-\n#KSRC := /media/DATA-1/aosp/android-omap-panda-3.0_20120104\nCROSS_COMPILE := /media/DATA-1/android-4.0/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-\nKSRC := /media/DATA-1/android-4.0/panda_kernel/omap\nMODULE_NAME := wlan\nendif\n\nifeq ($(CONFIG_PLATFORM_MIPS_JZ4760), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_MINIMAL_MEMORY_USAGE\nARCH ?= mips\nCROSS_COMPILE ?= /mnt/sdb5/Ingenic/Umido/mips-4.3/bin/mips-linux-gnu-\nKSRC ?= /mnt/sdb5/Ingenic/Umido/kernel\nendif\n\nifeq ($(CONFIG_PLATFORM_SZEBOOK), y)\nEXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN\nARCH:=arm\nCROSS_COMPILE:=/opt/crosstool2/bin/armeb-unknown-linux-gnueabi-\nKVER:= 2.6.31.6\nKSRC:= ../code/linux-2.6.31.6-2020/\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_SUNxI), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUNxI\n# default setting for Android 4.1, 4.2\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\n\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS\nifeq ($(CONFIG_USB_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX\n_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\n# default setting for A10-EVB mmc0\n#EXTRA_CFLAGS += -DCONFIG_WITS_EVB_V13\n_PLATFORM_FILES += platform/platform_ARM_SUNxI_sdio.o\nendif\n\nARCH := arm\n#CROSS_COMPILE := arm-none-linux-gnueabi-\nCROSS_COMPILE=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/buildroot/output/external-toolchain/bin/arm-none-linux-gnueabi-\nKVER  := 3.0.8\n#KSRC:= ../lichee/linux-3.0/\nKSRC=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/linux-3.0\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_SUN6I), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN6I\nEXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT\n# default setting for Android 4.1, 4.2, 4.3, 4.4\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nEXTRA_CFLAGS +=  -DCONFIG_QOS_OPTIMIZATION\n\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS\nifeq ($(CONFIG_USB_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX\n_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\n# default setting for A31-EVB mmc0\nEXTRA_CFLAGS += -DCONFIG_A31_EVB\n_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o\nendif\n\nARCH := arm\n#Android-JB42\n#CROSS_COMPILE := /home/android_sdk/Allwinner/a31/android-jb42/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi-\n#KSRC :=/home/android_sdk/Allwinner/a31/android-jb42/lichee/linux-3.3\n#ifeq ($(CONFIG_USB_HCI), y)\n#MODULE_NAME := 8188eu_sw\n#endif\n# ==== Cross compile setting for kitkat-a3x_v4.5 =====\nCROSS_COMPILE := /home/android_sdk/Allwinner/a31/kitkat-a3x_v4.5/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi-\nKSRC :=/home/android_sdk/Allwinner/a31/kitkat-a3x_v4.5/lichee/linux-3.3\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_SUN7I), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN7I\nEXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT\n# default setting for Android 4.1, 4.2, 4.3, 4.4\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nEXTRA_CFLAGS +=  -DCONFIG_QOS_OPTIMIZATION\n\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS\nifeq ($(CONFIG_USB_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX\n_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\n_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o\nendif\n\nARCH := arm\n# ===Cross compile setting for Android 4.2 SDK ===\n#CROSS_COMPILE := /home/android_sdk/Allwinner/a20_evb/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-\n#KSRC := /home/android_sdk/Allwinner/a20_evb/lichee/linux-3.3\n# ==== Cross compile setting for Android 4.3 SDK =====\n#CROSS_COMPILE := /home/android_sdk/Allwinner/a20/android-jb43/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-\n#KSRC := /home/android_sdk/Allwinner/a20/android-jb43/lichee/linux-3.4\n# ==== Cross compile setting for kitkat-a20_v4.4 =====\nCROSS_COMPILE := /home/android_sdk/Allwinner/a20/kitkat-a20_v4.4/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-\nKSRC := /home/android_sdk/Allwinner/a20/kitkat-a20_v4.4/lichee/linux-3.4\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_SUN8I_W3P1), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I_W3P1\nEXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT\n# default setting for Android 4.1, 4.2\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\n\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS\nifeq ($(CONFIG_USB_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX\n_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\n_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o\nendif\n\nARCH := arm\n# ===Cross compile setting for Android 4.2 SDK ===\n#CROSS_COMPILE := /home/android_sdk/Allwinner/a23/android-jb42/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-\n#KSRC :=/home/android_sdk/Allwinner/a23/android-jb42/lichee/linux-3.4\n# ===Cross compile setting for Android 4.4 SDK ===\nCROSS_COMPILE := /home/android_sdk/Allwinner/a23/android-kk44/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-\nKSRC :=/home/android_sdk/Allwinner/a23/android-kk44/lichee/linux-3.4\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_SUN8I_W5P1), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I_W5P1\nEXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT\n# default setting for Android 4.1, 4.2\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\n\n# Enable this for Android 5.0\nEXTRA_CFLAGS += -DCONFIG_RADIO_WORK\n\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS\nifeq ($(CONFIG_USB_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX\n_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\n_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o\nendif\n\nARCH := arm\n# ===Cross compile setting for Android L SDK ===\nCROSS_COMPILE := /home/android_sdk/Allwinner/a33/android-L/lichee/out/sun8iw5p1/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-\nKSRC :=/home/android_sdk/Allwinner/a33/android-L/lichee/linux-3.4\nendif\n\nifeq ($(CONFIG_PLATFORM_ACTIONS_ATV5201), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATV5201\nEXTRA_CFLAGS += -DCONFIG_SDIO_DISABLE_RXFIFO_POLLING_LOOP\nARCH := mips\nCROSS_COMPILE := mipsel-linux-gnu-\nKVER  := $(KERNEL_VER)\nKSRC:= $(CFGDIR)/../../kernel/linux-$(KERNEL_VER)\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_RTD299X), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nifeq ($(CONFIG_ANDROID), y)\n# Enable this for Android 5.0\nEXTRA_CFLAGS += -DCONFIG_RADIO_WORK\nendif\n#ARCH, CROSS_COMPILE, KSRC,and  MODDESTDIR are provided by external makefile\nINSTALL_PREFIX :=\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_RTD299X_LG), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DRTW_P2P_GROUP_INTERFACE=1\nEXTRA_CFLAGS += -DCONFIG_IFACE_NUMBER=3\n#EXTRA_CFLAGS += -DCONFIG_FIX_HWPORT\nEXTRA_CFLAGS += -DLGE_PRIVATE\nEXTRA_CFLAGS += -DPURE_SUPPLICANT\nEXTRA_CFLAGS += -DCONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP -DCONFIG_RTW_IOCTL_SET_COUNTRY\nEXTRA_CFLAGS += -DDBG_RX_DFRAME_RAW_DATA\nEXTRA_CFLAGS += -DRTW_REDUCE_SCAN_SWITCH_CH_TIME\nARCH ?= arm\nKVER ?=\n\nifneq ($(PLATFORM), WEBOS)\n$(info PLATFORM is empty)\nCROSS_COMPILE ?= /mnt/newdisk/LGE/arm-lg115x-linux-gnueabi-4.8-2016.03-x86_64/bin/arm-lg115x-linux-gnueabi-\nKSRC ?= /mnt/newdisk/LGE/linux-rockhopper_k3lp_drd4tv_423\nendif\n\nCROSS_COMPILE ?=\nKSRC ?= $(LINUX_SRC)\nINSTALL_PREFIX ?=\nendif\n\nifeq ($(CONFIG_PLATFORM_HISILICON), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_HISILICON\nifeq ($(SUPPORT_CONCURRENT),y)\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nendif\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nARCH := arm\nifeq ($(CROSS_COMPILE),)\n       CROSS_COMPILE = arm-hisiv200-linux-\nendif\nMODULE_NAME := rtl8192eu\nifeq ($(KSRC),)\n       KSRC := ../../../../../../kernel/linux-3.4.y\nendif\nendif\n\nifeq ($(CONFIG_PLATFORM_HISILICON_HI3798), y)\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON_HI3798\n#EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON_HI3798_MV200_HDMI_DONGLE\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\n# default setting for Android\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211\nEXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT\n# default setting for Android 5.x and later\n#EXTRA_CFLAGS += -DCONFIG_RADIO_WORK\n\n# If system could power on and recognize Wi-Fi SDIO automatically,\n# platfrom operations are not necessary.\n#ifeq ($(CONFIG_SDIO_HCI), y)\n#EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS\n#_PLATFORM_FILES += platform/platform_hisilicon_hi3798_sdio.o\n#EXTRA_CFLAGS += -DCONFIG_HISI_SDIO_ID=1\n#endif\n\nARCH ?= arm\nCROSS_COMPILE ?= /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/tools/linux/toolchains/arm-histbv310-linux/bin/arm-histbv310-linux-\nifndef KSRC\nKSRC := /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/source/kernel/linux-3.18.y\nKSRC += O=/HiSTBAndroidV600R003C00SPC021_git_0512/out/target/product/Hi3798MV200/obj/KERNEL_OBJ\nendif\n\nifeq ($(CONFIG_RTL8822B), y)\nifeq ($(CONFIG_SDIO_HCI), y)\nCONFIG_RTL8822BS ?= m\nUSER_MODULE_NAME := rtl8822bs\nendif\nendif\n\nendif\n\n# Platform setting\nifeq ($(CONFIG_PLATFORM_ARM_SPREADTRUM_6820), y)\nifeq ($(CONFIG_ANDROID_2X), y)\nEXTRA_CFLAGS += -DANDROID_2X\nendif\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_SPRD\nEXTRA_CFLAGS += -DPLATFORM_SPREADTRUM_6820\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nifeq ($(RTL871X), rtl8188e)\nEXTRA_CFLAGS += -DSOFTAP_PS_DURATION=50\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS\n_PLATFORM_FILES += platform/platform_sprd_sdio.o\nendif\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_SPREADTRUM_8810), y)\nifeq ($(CONFIG_ANDROID_2X), y)\nEXTRA_CFLAGS += -DANDROID_2X\nendif\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_SPRD\nEXTRA_CFLAGS += -DPLATFORM_SPREADTRUM_8810\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nifeq ($(RTL871X), rtl8188e)\nEXTRA_CFLAGS += -DSOFTAP_PS_DURATION=50\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS\n_PLATFORM_FILES += platform/platform_sprd_sdio.o\nendif\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_WMT), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS\nifeq ($(CONFIG_SDIO_HCI), y)\n_PLATFORM_FILES += platform/platform_ARM_WMT_sdio.o\nendif\nARCH := arm\nCROSS_COMPILE := /home/android_sdk/WonderMedia/wm8880-android4.4/toolchain/arm_201103_gcc4.5.2/mybin/arm_1103_le-\nKSRC := /home/android_sdk/WonderMedia/wm8880-android4.4/kernel4.4/\nMODULE_NAME :=8189es_kk\nendif\n\nifeq ($(CONFIG_PLATFORM_RTK119X), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\n#EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN7I\nEXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT\n# default setting for Android 4.1, 4.2\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\n#EXTRA_CFLAGS +=  -DCONFIG_QOS_OPTIMIZATION\nEXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION\n\n#EXTRA_CFLAGS += -DCONFIG_#PLATFORM_OPS\nifeq ($(CONFIG_USB_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX\n#_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\n_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o\nendif\n\nARCH := arm\n\n# ==== Cross compile setting for Android 4.4 SDK =====\n#CROSS_COMPILE := arm-linux-gnueabihf-\nKVER  := 3.10.24\n#KSRC :=/home/android_sdk/Allwinner/a20/android-kitkat44/lichee/linux-3.4\nCROSS_COMPILE := /home/realtek/software_phoenix/phoenix/toolchain/usr/local/arm-2013.11/bin/arm-linux-gnueabihf-\nKSRC := /home/realtek/software_phoenix/linux-kernel\nMODULE_NAME := 8192eu\n\nendif\n\nifeq ($(CONFIG_PLATFORM_RTK119X_AM), y)\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_RTK119X_AM\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE -DCONFIG_FULL_CH_IN_P2P_HANDSHAKE\nEXTRA_CFLAGS += -DCONFIG_IFACE_NUMBER=3\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\n\nifeq ($(CONFIG_USB_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX\nendif\n\nARCH := arm\n\n#CROSS_COMPILE := arm-linux-gnueabihf-\nKVER  := 3.10.24\n#KSRC :=\nCROSS_COMPILE :=\nendif\n\nifeq ($(CONFIG_PLATFORM_RTK129X), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DRTK_129X_PLATFORM\nEXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT\n# default setting for Android 4.1, 4.2\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\n#EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_QOS_OPTIMIZATION\nEXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION\n# Enable this for Android 5.0\nEXTRA_CFLAGS += -DCONFIG_RADIO_WORK\nifeq ($(CONFIG_RTL8821C)$(CONFIG_SDIO_HCI),yy)\nEXTRA_CFLAGS += -DCONFIG_WAKEUP_GPIO_INPUT_MODE\nEXTRA_CFLAGS += -DCONFIG_BT_WAKE_HST_OPEN_DRAIN\nendif\nEXTRA_CFLAGS += -Wno-error=date-time\n# default setting for Android 7.0\nifeq ($(RTK_ANDROID_VERSION), nougat)\nEXTRA_CFLAGS += -DRTW_P2P_GROUP_INTERFACE=1\nendif\n#EXTRA_CFLAGS += -DCONFIG_#PLATFORM_OPS\nifeq ($(CONFIG_USB_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX\nendif\n\nARCH := arm64\n\n# ==== Cross compile setting for Android 4.4 SDK =====\n#CROSS_COMPILE := arm-linux-gnueabihf-\n#KVER  := 4.1.10\n#CROSS_COMPILE := $(CROSS)\n#KSRC := $(LINUX_KERNEL_PATH)\nCROSS_COMPILE := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/phoenix/toolchain/asdk64-4.9.4-a53-EL-3.10-g2.19-a64nt-160307/bin/asdk64-linux-\nKSRC := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/linux-kernel\nendif\n\nifeq ($(CONFIG_PLATFORM_RTK390X), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_RTK390X\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nEXTRA_CFLAGS += -DCONFIG_RTW_NETIF_SG\nifeq ($(CONFIG_USB_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX\nendif\n\nARCH:=rlx\n\nCROSS_COMPILE:=mips-linux-\nKSRC:= /home/realtek/share/Develop/IPCAM_SDK/RealSil/rts3901_sdk_v1.2_vanilla/linux-3.10\n\nendif\n\nifeq ($(CONFIG_PLATFORM_NOVATEK_NT72668), y)\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_NOVATEK_NT72668\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nEXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_RX\nEXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX\nARCH ?= arm\nCROSS_COMPILE := arm-linux-gnueabihf-\nKVER := 3.8.0\nKSRC := /Custom/Novatek/TCL/linux-3.8_header\n#KSRC := $(KERNELDIR)\nendif\n\nifeq ($(CONFIG_PLATFORM_ARM_TCC8930_JB42), y)\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\n# default setting for Android 4.1, 4.2\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT\nARCH := arm\nCROSS_COMPILE := /home/android_sdk/Telechips/v13.05_r1-tcc-android-4.2.2_tcc893x-evm_build/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-\nKSRC := /home/android_sdk/Telechips/v13.05_r1-tcc-android-4.2.2_tcc893x-evm_build/kernel\nMODULE_NAME := wlan\nendif \n\nifeq ($(CONFIG_PLATFORM_RTL8197D), y)\nEXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTL8197D\nexport DIR_LINUX=$(shell pwd)/../SDK/rlxlinux-sdk321-v50/linux-2.6.30\nARCH ?= rlx\nCROSS_COMPILE:= $(DIR_LINUX)/../toolchain/rsdk-1.5.5-5281-EB-2.6.30-0.9.30.3-110714/bin/rsdk-linux-\nKSRC := $(DIR_LINUX)\nendif\n\nifeq ($(CONFIG_PLATFORM_AML_S905), y)\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_AML_S905\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -fno-pic\n# default setting for Android\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211\nEXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT\n# default setting for Android 5.x and later\nEXTRA_CFLAGS += -DCONFIG_RADIO_WORK\n\nifeq ($(CONFIG_SDIO_HCI), y)\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS\n_PLATFORM_FILES += platform/platform_aml_s905_sdio.o\nendif\n\nARCH ?= arm64\nCROSS_COMPILE ?= /4.4_S905L_8822bs_compile/gcc-linaro-aarch64-linux-gnu-4.9-2014.09_linux/bin/aarch64-linux-gnu-\nifndef KSRC\nKSRC := /4.4_S905L_8822bs_compile/common\n# To locate output files in a separate directory.\nKSRC += O=/4.4_S905L_8822bs_compile/KERNEL_OBJ\nendif\n\nifeq ($(CONFIG_RTL8822B), y)\nifeq ($(CONFIG_SDIO_HCI), y)\nCONFIG_RTL8822BS ?= m\nUSER_MODULE_NAME := 8822bs\nendif\nendif\n\nendif\n\nifeq ($(CONFIG_PLATFORM_ZTE_ZX296716), y)\nEXTRA_CFLAGS += -Wno-error=date-time\nEXTRA_CFLAGS += -DCONFIG_PLATFORM_ZTE_ZX296716\nEXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN\n# default setting for Android\nEXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE\nEXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211\nEXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT\n# default setting for Android 5.x and later\n#EXTRA_CFLAGS += -DCONFIG_RADIO_WORK\n\nifeq ($(CONFIG_SDIO_HCI), y)\n# mark this temporarily\n#EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS\n#_PLATFORM_FILES += platform/platform_zte_zx296716_sdio.o\nendif\n\nARCH ?= arm64\nCROSS_COMPILE ?=\nKSRC ?=\n\nifeq ($(CONFIG_RTL8822B), y)\nifeq ($(CONFIG_SDIO_HCI), y)\nCONFIG_RTL8822BS ?= m\nUSER_MODULE_NAME := 8822bs\nendif\nendif\n\nendif\n\n########### CUSTOMER ################################\nifeq ($(CONFIG_CUSTOMER_HUAWEI_GENERAL), y)\nCONFIG_CUSTOMER_HUAWEI = y\nendif\n\nifeq ($(CONFIG_CUSTOMER_HUAWEI), y)\nEXTRA_CFLAGS += -DCONFIG_HUAWEI_PROC\nendif\n\nifeq ($(CONFIG_MULTIDRV), y)\n\nifeq ($(CONFIG_SDIO_HCI), y)\nMODULE_NAME := rtw_sdio\nendif\n\nifeq ($(CONFIG_USB_HCI), y)\nMODULE_NAME := rtw_usb\nendif\n\nifeq ($(CONFIG_PCI_HCI), y)\nMODULE_NAME := rtw_pci\nendif\n\n\nendif\n\nUSER_MODULE_NAME ?=\nifneq ($(USER_MODULE_NAME),)\nMODULE_NAME := $(USER_MODULE_NAME)\nendif\n\nifneq ($(KERNELRELEASE),)\n\n########### this part for *.mk ############################\ninclude $(src)/hal/phydm/phydm.mk\n\n########### HAL_RTL8822B #################################\nifeq ($(CONFIG_RTL8822B), y)\ninclude $(src)/rtl8822b.mk\nendif\n\n########### HAL_RTL8821C #################################\nifeq ($(CONFIG_RTL8821C), y)\ninclude $(src)/rtl8821c.mk\nendif\n\n########### HAL_RTL8822C #################################\nifeq ($(CONFIG_RTL8822C), y)\ninclude $(src)/rtl8822c.mk\nendif\n\nrtk_core :=\tcore/rtw_cmd.o \\\n\t\tcore/rtw_security.o \\\n\t\tcore/rtw_debug.o \\\n\t\tcore/rtw_io.o \\\n\t\tcore/rtw_ioctl_query.o \\\n\t\tcore/rtw_ioctl_set.o \\\n\t\tcore/rtw_ieee80211.o \\\n\t\tcore/rtw_mlme.o \\\n\t\tcore/rtw_mlme_ext.o \\\n\t\tcore/rtw_mi.o \\\n\t\tcore/rtw_wlan_util.o \\\n\t\tcore/rtw_vht.o \\\n\t\tcore/rtw_pwrctrl.o \\\n\t\tcore/rtw_rf.o \\\n\t\tcore/rtw_chplan.o \\\n\t\tcore/rtw_recv.o \\\n\t\tcore/rtw_sta_mgt.o \\\n\t\tcore/rtw_ap.o \\\n\t\tcore/mesh/rtw_mesh.o \\\n\t\tcore/mesh/rtw_mesh_pathtbl.o \\\n\t\tcore/mesh/rtw_mesh_hwmp.o \\\n\t\tcore/rtw_xmit.o\t\\\n\t\tcore/rtw_p2p.o \\\n\t\tcore/rtw_rson.o \\\n\t\tcore/rtw_tdls.o \\\n\t\tcore/rtw_br_ext.o \\\n\t\tcore/rtw_iol.o \\\n\t\tcore/rtw_sreset.o \\\n\t\tcore/rtw_btcoex_wifionly.o \\\n\t\tcore/rtw_btcoex.o \\\n\t\tcore/rtw_beamforming.o \\\n\t\tcore/rtw_odm.o \\\n\t\tcore/rtw_rm.o \\\n\t\tcore/rtw_rm_fsm.o \\\n\t\tcore/efuse/rtw_efuse.o \n\nifeq ($(CONFIG_SDIO_HCI), y)\nrtk_core += core/rtw_sdio.o\nendif\n\n$(MODULE_NAME)-y += $(rtk_core)\n\n$(MODULE_NAME)-$(CONFIG_WAPI_SUPPORT) += core/rtw_wapi.o\t\\\n\t\t\t\t\tcore/rtw_wapi_sms4.o\n\n$(MODULE_NAME)-y += $(_OS_INTFS_FILES)\n$(MODULE_NAME)-y += $(_HAL_INTFS_FILES)\n$(MODULE_NAME)-y += $(_PHYDM_FILES)\n$(MODULE_NAME)-y += $(_BTC_FILES)\n$(MODULE_NAME)-y += $(_PLATFORM_FILES)\n\n$(MODULE_NAME)-$(CONFIG_MP_INCLUDED) += core/rtw_mp.o\n\nifeq ($(CONFIG_RTL8723B), y)\n$(MODULE_NAME)-$(CONFIG_MP_INCLUDED)+= core/rtw_bt_mp.o\nendif\n\nobj-$(CONFIG_RTL8822CE) := $(MODULE_NAME).o\n\nelse\n\nexport CONFIG_RTL8822CE = m\n\nall: modules\n\nmodules:\n\t$(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd)  modules\n\nstrip:\n\t$(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded\n\ninstall:\n\tinstall -p -m 644 $(MODULE_NAME).ko  $(MODDESTDIR)\n\t/sbin/depmod -a ${KVER}\n\nuninstall:\n\trm -f $(MODDESTDIR)/$(MODULE_NAME).ko\n\t/sbin/depmod -a ${KVER}\n\nbackup_rtlwifi:\n\t@echo \"Making backup rtlwifi drivers\"\nifneq (,$(wildcard $(STAGINGMODDIR)/rtl*))\n\t@tar cPf $(wildcard $(STAGINGMODDIR))/backup_rtlwifi_driver.tar $(wildcard $(STAGINGMODDIR)/rtl*)\n\t@rm -rf $(wildcard $(STAGINGMODDIR)/rtl*)\nendif\nifneq (,$(wildcard $(MODDESTDIR)realtek))\n\t@tar cPf $(MODDESTDIR)backup_rtlwifi_driver.tar $(MODDESTDIR)realtek\n\t@rm -fr $(MODDESTDIR)realtek\nendif\nifneq (,$(wildcard $(MODDESTDIR)rtl*))\n\t@tar cPf $(MODDESTDIR)../backup_rtlwifi_driver.tar $(wildcard $(MODDESTDIR)rtl*)\n\t@rm -fr $(wildcard $(MODDESTDIR)rtl*)\nendif\n\t@/sbin/depmod -a ${KVER}\n\t@echo \"Please reboot your system\"\n\nrestore_rtlwifi:\n\t@echo \"Restoring backups\"\nifneq (,$(wildcard $(STAGINGMODDIR)/backup_rtlwifi_driver.tar))\n\t@tar xPf $(STAGINGMODDIR)/backup_rtlwifi_driver.tar\n\t@rm $(STAGINGMODDIR)/backup_rtlwifi_driver.tar\nendif\nifneq (,$(wildcard $(MODDESTDIR)backup_rtlwifi_driver.tar))\n\t@tar xPf $(MODDESTDIR)backup_rtlwifi_driver.tar\n\t@rm $(MODDESTDIR)backup_rtlwifi_driver.tar\nendif\nifneq (,$(wildcard $(MODDESTDIR)../backup_rtlwifi_driver.tar))\n\t@tar xPf $(MODDESTDIR)../backup_rtlwifi_driver.tar\n\t@rm $(MODDESTDIR)../backup_rtlwifi_driver.tar\nendif\n\t@/sbin/depmod -a ${KVER}\n\t@echo \"Please reboot your system\"\n\nconfig_r:\n\t@echo \"make config\"\n\t/bin/bash script/Configure script/config.in\n\n\n.PHONY: modules clean\n\nclean:\n\t#$(MAKE) -C $(KSRC) M=$(shell pwd) clean\n\tcd hal ; rm -fr */*/*/*.mod.c */*/*/*.mod */*/*/*.o */*/*/.*.cmd */*/*/*.ko\n\tcd hal ; rm -fr */*/*.mod.c */*/*.mod */*/*.o */*/.*.cmd */*/*.ko\n\tcd hal ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko\n\tcd hal ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko\n\tcd core ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko\n\tcd core ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko\n\tcd os_dep/linux ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko\n\tcd os_dep ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko\n\tcd platform ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko\n\trm -fr Module.symvers ; rm -fr Module.markers ; rm -fr modules.order\n\trm -fr *.mod.c *.mod *.o .*.cmd *.ko *~\n\trm -fr .tmp_versions\nendif\n\n"
  },
  {
    "path": "README.md",
    "content": "[![](https://sourcerer.io/fame/juanro49/juanro49/rtl88x2ce-dkms/images/0)](https://sourcerer.io/fame/juanro49/juanro49/rtl88x2ce-dkms/links/0)[![](https://sourcerer.io/fame/juanro49/juanro49/rtl88x2ce-dkms/images/1)](https://sourcerer.io/fame/juanro49/juanro49/rtl88x2ce-dkms/links/1)[![](https://sourcerer.io/fame/juanro49/juanro49/rtl88x2ce-dkms/images/2)](https://sourcerer.io/fame/juanro49/juanro49/rtl88x2ce-dkms/links/2)[![](https://sourcerer.io/fame/juanro49/juanro49/rtl88x2ce-dkms/images/3)](https://sourcerer.io/fame/juanro49/juanro49/rtl88x2ce-dkms/links/3)[![](https://sourcerer.io/fame/juanro49/juanro49/rtl88x2ce-dkms/images/4)](https://sourcerer.io/fame/juanro49/juanro49/rtl88x2ce-dkms/links/4)[![](https://sourcerer.io/fame/juanro49/juanro49/rtl88x2ce-dkms/images/5)](https://sourcerer.io/fame/juanro49/juanro49/rtl88x2ce-dkms/links/5)[![](https://sourcerer.io/fame/juanro49/juanro49/rtl88x2ce-dkms/images/6)](https://sourcerer.io/fame/juanro49/juanro49/rtl88x2ce-dkms/links/6)[![](https://sourcerer.io/fame/juanro49/juanro49/rtl88x2ce-dkms/images/7)](https://sourcerer.io/fame/juanro49/juanro49/rtl88x2ce-dkms/links/7)\n\n# RTL88x2CE dkms module driver\n\nDownload complete driver package with guides [from this repo](https://github.com/XAIOThaifeng/realtek-linux/tree/master/RTL8822CE).\n\n## Instalación\n\n### [PatoJAD Repo](https://patojad.com.ar/repositorio/) (desactualizado)\n```\necho 'deb https://gitlab.com/patojad/repository/raw/patojad/debs/ patojad main\n' | sudo tee /etc/apt/sources.list.d/patojad.list\nwget -qO - https://gitlab.com/LynxOS/repository/raw/lynxos/LynxPub.gpg | apt-key add -\nsudo apt update\nsudo apt install rtl88x2ce-dkms\n```\n\n### Paquete deb\n```\nwget https://github.com/juanro49/rtl88x2ce-dkms/releases/download/5.7.3_35403_20210523/rtl88x2ce-dkms_35403_amd64.deb\nsudo dpkg -i rtl88x2ce-dkms_35403_amd64.deb\n```\n\n### Desde código fuente\n```\ngit clone https://github.com/juanro49/rtl88x2ce-dkms.git\nsudo cp rtl88x2ce-dkms/rtw88_blacklist.conf /etc/modprobe.d/rtw88_blacklist.conf\nsudo mkdir /usr/src/rtl88x2ce-35403\nsudo cp -Rv rtl88x2ce-dkms/* /usr/src/rtl88x2ce-35403/\nsudo dkms add -m rtl88x2ce -v 35403\nsudo dkms build -m rtl88x2ce -v 35403\nsudo dkms install -m rtl88x2ce -v 35403\n```\n\n## Iniciar módulo\n\n`sudo modprobe rtl88x2ce`\n\n\nDriver testeado en:\n\n[MSI Alpha 15](https://plume.nogafam.es/~/ElBlogDeJuanro/Review%20portatil%20MSI%20Alpha%2015%20A3DDK) con [SparkyLinux Rolling](https://sparkylinux.org/)\n\nNetwork controller: Realtek Semiconductor Co., Ltd. RTL8822CE 802.11ac PCIe Wireless Network Adapter\n\n## Donaciones\n[<img src=\"https://coindrop.to/embed-button.png\" border-radius=\"10px\" height=\"57\" width=\"200px\" alt=\"Coindrop.to me\">](https://coindrop.to/juanro49) [<img alt=\"Donate using Liberapay\" border-radius=\"10px\" height=\"57\" width=\"200px\" src=\"https://liberapay.com/assets/widgets/donate.svg\">](https://liberapay.com/juanro49/donate) [<img src=\"https://cesium.duniter.io/img/duniter_button.svg\" border-radius=\"10px\" height=\"57\" width=\"200px\" alt=\"moneda libre G1\">](https://cesium.duniter.io/api/#/v1/payment/5eETo8btrVGYTTyC5nAvqCPmLBok4aRLhxiGP7dy3Wqw?comment=Donaci%C3%B3n%20github)\n\n"
  },
  {
    "path": "clean",
    "content": "#!/bin/bash\nrmmod 8192cu\nrmmod 8192ce\nrmmod 8192du\nrmmod 8192de\n"
  },
  {
    "path": "core/efuse/rtw_efuse.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_EFUSE_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\n#include \"../hal/efuse/efuse_mask.h\"\n\n/*------------------------Define local variable------------------------------*/\nu8\tfakeEfuseBank = {0};\nu32\tfakeEfuseUsedBytes = {0};\nu8\tfakeEfuseContent[EFUSE_MAX_HW_SIZE] = {0};\nu8\tfakeEfuseInitMap[EFUSE_MAX_MAP_LEN] = {0};\nu8\tfakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN] = {0};\n\nu32\tBTEfuseUsedBytes = {0};\nu8\tBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];\nu8\tBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN] = {0};\nu8\tBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN] = {0};\n\nu32\tfakeBTEfuseUsedBytes = {0};\nu8\tfakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];\nu8\tfakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN] = {0};\nu8\tfakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN] = {0};\n\nu8\tmaskfileBuffer[64];\nu8\tbtmaskfileBuffer[64];\n\n/*------------------------Define local variable------------------------------*/\nBOOLEAN rtw_file_efuse_IsMasked(PADAPTER pAdapter, u16 Offset, u8 *maskbuf)\n{\n\tint r = Offset / 16;\n\tint c = (Offset % 16) / 2;\n\tint result = 0;\n\n\tif (pAdapter->registrypriv.boffefusemask)\n\t\treturn FALSE;\n\n\tif (c < 4) /* Upper double word */\n\t\tresult = (maskbuf[r] & (0x10 << c));\n\telse\n\t\tresult = (maskbuf[r] & (0x01 << (c - 4)));\n\n\treturn (result > 0) ? 0 : 1;\n}\nBOOLEAN efuse_IsBT_Masked(PADAPTER pAdapter, u16 Offset)\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);\n\n\tif (pAdapter->registrypriv.boffefusemask)\n\t\treturn FALSE;\n\n#ifdef CONFIG_USB_HCI\n\tif (IS_HARDWARE_TYPE_8822C(pAdapter))\n\t\treturn (IS_BT_MASKED(8822C, _MUSB, Offset)) ? TRUE : FALSE;\n#endif\n#ifdef CONFIG_PCI_HCI\n\tif (IS_HARDWARE_TYPE_8822C(pAdapter))\n\t\treturn (IS_BT_MASKED(8822C, _MPCIE, Offset)) ? TRUE : FALSE;\n#endif\n#ifdef CONFIG_SDIO_HCI\n\tif (IS_HARDWARE_TYPE_8822C(pAdapter))\n\t\treturn (IS_BT_MASKED(8822C, _MSDIO, Offset)) ? TRUE : FALSE;\n#endif\n\n\treturn FALSE;\n}\n\nvoid rtw_bt_efuse_mask_array(PADAPTER pAdapter, u8 *pArray)\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);\n\n#ifdef CONFIG_USB_HCI\nif (IS_HARDWARE_TYPE_8822CU(pAdapter))\n\t\tGET_MASK_ARRAY(8822C, _MUSB, pArray);\n#endif\n#ifdef CONFIG_PCI_HCI\n\tif (IS_HARDWARE_TYPE_8822CE(pAdapter))\n\t\tGET_MASK_ARRAY(8822C, _MPCIE, pArray);\n#endif\n#ifdef CONFIG_SDIO_HCI\n\tif (IS_HARDWARE_TYPE_8822CS(pAdapter))\n\t\tGET_MASK_ARRAY(8822C, _MSDIO, pArray);\n#endif\n\n}\n\nu16 rtw_get_bt_efuse_mask_arraylen(PADAPTER pAdapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\n#ifdef CONFIG_USB_HCI\n\tif (IS_HARDWARE_TYPE_8822CU(pAdapter))\n\t\treturn GET_BT_MASK_ARRAY_LEN(8822C, _MUSB);\n#endif\n#ifdef CONFIG_PCI_HCI\n\tif (IS_HARDWARE_TYPE_8822CE(pAdapter))\n\t\treturn GET_BT_MASK_ARRAY_LEN(8822C, _MPCIE);\n#endif\n#ifdef CONFIG_SDIO_HCI\n\tif (IS_HARDWARE_TYPE_8822CS(pAdapter))\n\t\treturn GET_BT_MASK_ARRAY_LEN(8822C, _MSDIO);\n#endif\n\treturn 0;\n}\n\nBOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset)\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);\n\n\tif (pAdapter->registrypriv.boffefusemask)\n\t\treturn FALSE;\n\n#ifdef CONFIG_USB_HCI\n#if defined(CONFIG_RTL8188E)\n\tif (IS_HARDWARE_TYPE_8188E(pAdapter))\n\t\treturn (IS_MASKED(8188E, _MUSB, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8812A)\n\tif (IS_HARDWARE_TYPE_8812(pAdapter))\n\t\treturn (IS_MASKED(8812A, _MUSB, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8821A)\n#if 0\n\tif (IS_HARDWARE_TYPE_8811AU(pAdapter))\n\t\treturn (IS_MASKED(8811A, _MUSB, Offset)) ? TRUE : FALSE;\n#endif\n\tif (IS_HARDWARE_TYPE_8821(pAdapter))\n\t\treturn (IS_MASKED(8821A, _MUSB, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8192E)\n\tif (IS_HARDWARE_TYPE_8192E(pAdapter))\n\t\treturn (IS_MASKED(8192E, _MUSB, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8723B)\n\tif (IS_HARDWARE_TYPE_8723B(pAdapter))\n\t\treturn (IS_MASKED(8723B, _MUSB, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8703B)\n\tif (IS_HARDWARE_TYPE_8703B(pAdapter))\n\t\treturn (IS_MASKED(8703B, _MUSB, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8814A)\n\tif (IS_HARDWARE_TYPE_8814A(pAdapter))\n\t\treturn (IS_MASKED(8814A, _MUSB, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8188F)\n\tif (IS_HARDWARE_TYPE_8188F(pAdapter))\n\t\treturn (IS_MASKED(8188F, _MUSB, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8188GTV)\n\tif (IS_HARDWARE_TYPE_8188GTV(pAdapter))\n\t\treturn (IS_MASKED(8188GTV, _MUSB, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8822B)\n\tif (IS_HARDWARE_TYPE_8822B(pAdapter))\n\t\treturn (IS_MASKED(8822B, _MUSB, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8723D)\n\tif (IS_HARDWARE_TYPE_8723D(pAdapter))\n\t\treturn (IS_MASKED(8723D, _MUSB, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8710B)\n\tif (IS_HARDWARE_TYPE_8710B(pAdapter))\n\t\treturn (IS_MASKED(8710B, _MUSB, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8821C)\n\tif (IS_HARDWARE_TYPE_8821CU(pAdapter))\n\t\treturn (IS_MASKED(8821C, _MUSB, Offset)) ? TRUE : FALSE;\n#endif\n\n#if defined(CONFIG_RTL8192F)\n\tif (IS_HARDWARE_TYPE_8192FU(pAdapter))\n\t\treturn (IS_MASKED(8192F, _MUSB, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8822C)\n\tif (IS_HARDWARE_TYPE_8822C(pAdapter))\n\t\treturn (IS_MASKED(8822C, _MUSB, Offset)) ? TRUE : FALSE;\n#endif\n#endif /*CONFIG_USB_HCI*/\n\n#ifdef CONFIG_PCI_HCI\n#if defined(CONFIG_RTL8188E)\n\tif (IS_HARDWARE_TYPE_8188E(pAdapter))\n\t\treturn (IS_MASKED(8188E, _MPCIE, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8192E)\n\tif (IS_HARDWARE_TYPE_8192E(pAdapter))\n\t\treturn (IS_MASKED(8192E, _MPCIE, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8812A)\n\tif (IS_HARDWARE_TYPE_8812(pAdapter))\n\t\treturn (IS_MASKED(8812A, _MPCIE, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8821A)\n\tif (IS_HARDWARE_TYPE_8821(pAdapter))\n\t\treturn (IS_MASKED(8821A, _MPCIE, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8723B)\n\tif (IS_HARDWARE_TYPE_8723B(pAdapter))\n\t\treturn (IS_MASKED(8723B, _MPCIE, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8814A)\n\tif (IS_HARDWARE_TYPE_8814A(pAdapter))\n\t\treturn (IS_MASKED(8814A, _MPCIE, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8822B)\n\tif (IS_HARDWARE_TYPE_8822B(pAdapter))\n\t\treturn (IS_MASKED(8822B, _MPCIE, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8821C)\n\tif (IS_HARDWARE_TYPE_8821CE(pAdapter))\n\t\treturn (IS_MASKED(8821C, _MPCIE, Offset)) ? TRUE : FALSE;\n#endif\n\n#if defined(CONFIG_RTL8192F)\n\tif (IS_HARDWARE_TYPE_8192FE(pAdapter))\n\t\treturn (IS_MASKED(8192F, _MPCIE, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8822C)\n\tif (IS_HARDWARE_TYPE_8822C(pAdapter))\n\t\treturn (IS_MASKED(8822C, _MPCIE, Offset)) ? TRUE : FALSE;\n#endif\n#endif /*CONFIG_PCI_HCI*/\n\n#ifdef CONFIG_SDIO_HCI\n#ifdef CONFIG_RTL8188E_SDIO\n\tif (IS_HARDWARE_TYPE_8188E(pAdapter))\n\t\treturn (IS_MASKED(8188E, _MSDIO, Offset)) ? TRUE : FALSE;\n#endif\n#ifdef CONFIG_RTL8723B\n\tif (IS_HARDWARE_TYPE_8723BS(pAdapter))\n\t\treturn (IS_MASKED(8723B, _MSDIO, Offset)) ? TRUE : FALSE;\n#endif\n#ifdef CONFIG_RTL8188F\n\tif (IS_HARDWARE_TYPE_8188F(pAdapter))\n\t\treturn (IS_MASKED(8188F, _MSDIO, Offset)) ? TRUE : FALSE;\n#endif\n#ifdef CONFIG_RTL8188GTV\n\tif (IS_HARDWARE_TYPE_8188GTV(pAdapter))\n\t\treturn (IS_MASKED(8188GTV, _MSDIO, Offset)) ? TRUE : FALSE;\n#endif\n#ifdef CONFIG_RTL8192E\n\tif (IS_HARDWARE_TYPE_8192ES(pAdapter))\n\t\treturn (IS_MASKED(8192E, _MSDIO, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8821A)\n\tif (IS_HARDWARE_TYPE_8821S(pAdapter))\n\t\treturn (IS_MASKED(8821A, _MSDIO, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8821C)\n\tif (IS_HARDWARE_TYPE_8821CS(pAdapter))\n\t\treturn (IS_MASKED(8821C, _MSDIO, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8822B)\n\tif (IS_HARDWARE_TYPE_8822B(pAdapter))\n\t\treturn (IS_MASKED(8822B, _MSDIO, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8192F)\n\tif (IS_HARDWARE_TYPE_8192FS(pAdapter))\n\t\treturn (IS_MASKED(8192F, _MSDIO, Offset)) ? TRUE : FALSE;\n#endif\n#if defined(CONFIG_RTL8822C)\n\tif (IS_HARDWARE_TYPE_8822C(pAdapter))\n\t\treturn (IS_MASKED(8822C, _MSDIO, Offset)) ? TRUE : FALSE;\n#endif\n#endif /*CONFIG_SDIO_HCI*/\n\n\treturn FALSE;\n}\n\nvoid rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray)\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);\n\n#ifdef CONFIG_USB_HCI\n#if defined(CONFIG_RTL8188E)\n\tif (IS_HARDWARE_TYPE_8188E(pAdapter))\n\t\tGET_MASK_ARRAY(8188E, _MUSB, pArray);\n#endif\n#if defined(CONFIG_RTL8812A)\n\tif (IS_HARDWARE_TYPE_8812(pAdapter))\n\t\tGET_MASK_ARRAY(8812A, _MUSB, pArray);\n#endif\n#if defined(CONFIG_RTL8821A)\n\tif (IS_HARDWARE_TYPE_8821(pAdapter))\n\t\tGET_MASK_ARRAY(8821A, _MUSB, pArray);\n#endif\n#if defined(CONFIG_RTL8192E)\n\tif (IS_HARDWARE_TYPE_8192E(pAdapter))\n\t\tGET_MASK_ARRAY(8192E, _MUSB, pArray);\n#endif\n#if defined(CONFIG_RTL8723B)\n\tif (IS_HARDWARE_TYPE_8723B(pAdapter))\n\t\tGET_MASK_ARRAY(8723B, _MUSB, pArray);\n#endif\n#if defined(CONFIG_RTL8703B)\n\tif (IS_HARDWARE_TYPE_8703B(pAdapter))\n\t\tGET_MASK_ARRAY(8703B, _MUSB, pArray);\n#endif\n#if defined(CONFIG_RTL8188F)\n\tif (IS_HARDWARE_TYPE_8188F(pAdapter))\n\t\tGET_MASK_ARRAY(8188F, _MUSB, pArray);\n#endif\n#if defined(CONFIG_RTL8188GTV)\n\tif (IS_HARDWARE_TYPE_8188GTV(pAdapter))\n\t\tGET_MASK_ARRAY(8188GTV, _MUSB, pArray);\n#endif\n#if defined(CONFIG_RTL8814A)\n\tif (IS_HARDWARE_TYPE_8814A(pAdapter))\n\t\tGET_MASK_ARRAY(8814A, _MUSB, pArray);\n#endif\n#if defined(CONFIG_RTL8822B)\n\tif (IS_HARDWARE_TYPE_8822B(pAdapter))\n\t\tGET_MASK_ARRAY(8822B, _MUSB, pArray);\n#endif\n#if defined(CONFIG_RTL8821C)\n\tif (IS_HARDWARE_TYPE_8821CU(pAdapter))\n\t\tGET_MASK_ARRAY(8821C, _MUSB, pArray);\n#endif\n#if defined(CONFIG_RTL8192F)\n\tif (IS_HARDWARE_TYPE_8192FU(pAdapter))\n\t\tGET_MASK_ARRAY(8192F, _MUSB, pArray);\n#endif\n#if defined(CONFIG_RTL8822C)\n\tif (IS_HARDWARE_TYPE_8822C(pAdapter))\n\t\tGET_MASK_ARRAY(8822C, _MUSB, pArray);\n#endif\n#endif /*CONFIG_USB_HCI*/\n\n#ifdef CONFIG_PCI_HCI\n#if defined(CONFIG_RTL8188E)\n\tif (IS_HARDWARE_TYPE_8188E(pAdapter))\n\t\tGET_MASK_ARRAY(8188E, _MPCIE, pArray);\n#endif\n#if defined(CONFIG_RTL8192E)\n\tif (IS_HARDWARE_TYPE_8192E(pAdapter))\n\t\tGET_MASK_ARRAY(8192E, _MPCIE, pArray);\n#endif\n#if defined(CONFIG_RTL8812A)\n\tif (IS_HARDWARE_TYPE_8812(pAdapter))\n\t\tGET_MASK_ARRAY(8812A, _MPCIE, pArray);\n#endif\n#if defined(CONFIG_RTL8821A)\n\tif (IS_HARDWARE_TYPE_8821(pAdapter))\n\t\tGET_MASK_ARRAY(8821A, _MPCIE, pArray);\n#endif\n#if defined(CONFIG_RTL8723B)\n\tif (IS_HARDWARE_TYPE_8723B(pAdapter))\n\t\tGET_MASK_ARRAY(8723B, _MPCIE, pArray);\n#endif\n#if defined(CONFIG_RTL8814A)\n\tif (IS_HARDWARE_TYPE_8814A(pAdapter))\n\t\tGET_MASK_ARRAY(8814A, _MPCIE, pArray);\n#endif\n#if defined(CONFIG_RTL8822B)\n\tif (IS_HARDWARE_TYPE_8822B(pAdapter))\n\t\tGET_MASK_ARRAY(8822B, _MPCIE, pArray);\n#endif\n#if defined(CONFIG_RTL8821C)\n\tif (IS_HARDWARE_TYPE_8821CE(pAdapter))\n\t\tGET_MASK_ARRAY(8821C, _MPCIE, pArray);\n#endif\n#if defined(CONFIG_RTL8192F)\n\tif (IS_HARDWARE_TYPE_8192FE(pAdapter))\n\t\tGET_MASK_ARRAY(8192F, _MPCIE, pArray);\n#endif\n#if defined(CONFIG_RTL8822C)\n\tif (IS_HARDWARE_TYPE_8822C(pAdapter))\n\t\tGET_MASK_ARRAY(8822C, _MPCIE, pArray);\n#endif\n#endif /*CONFIG_PCI_HCI*/\n\n#ifdef CONFIG_SDIO_HCI\n#if defined(CONFIG_RTL8188E)\n\tif (IS_HARDWARE_TYPE_8188E(pAdapter))\n\t\tGET_MASK_ARRAY(8188E, _MSDIO, pArray);\n#endif\n#if defined(CONFIG_RTL8723B)\n\tif (IS_HARDWARE_TYPE_8723BS(pAdapter))\n\t\tGET_MASK_ARRAY(8723B, _MSDIO, pArray);\n#endif\n#if defined(CONFIG_RTL8188F)\n\tif (IS_HARDWARE_TYPE_8188F(pAdapter))\n\t\tGET_MASK_ARRAY(8188F, _MSDIO, pArray);\n#endif\n#if defined(CONFIG_RTL8188GTV)\n\tif (IS_HARDWARE_TYPE_8188GTV(pAdapter))\n\t\tGET_MASK_ARRAY(8188GTV, _MSDIO, pArray);\n#endif\n#if defined(CONFIG_RTL8192E)\n\tif (IS_HARDWARE_TYPE_8192ES(pAdapter))\n\t\tGET_MASK_ARRAY(8192E, _MSDIO, pArray);\n#endif\n#if defined(CONFIG_RTL8821A)\n\tif (IS_HARDWARE_TYPE_8821S(pAdapter))\n\t\tGET_MASK_ARRAY(8821A, _MSDIO, pArray);\n#endif\n#if defined(CONFIG_RTL8821C)\n\tif (IS_HARDWARE_TYPE_8821CS(pAdapter))\n\t\tGET_MASK_ARRAY(8821C , _MSDIO, pArray);\n#endif\n#if defined(CONFIG_RTL8822B)\n\tif (IS_HARDWARE_TYPE_8822B(pAdapter))\n\t\tGET_MASK_ARRAY(8822B , _MSDIO, pArray);\n#endif\n#if defined(CONFIG_RTL8192F)\n\tif (IS_HARDWARE_TYPE_8192FS(pAdapter))\n\t\tGET_MASK_ARRAY(8192F, _MSDIO, pArray);\n#endif\n#if defined(CONFIG_RTL8822C)\n\tif (IS_HARDWARE_TYPE_8822C(pAdapter))\n\t\tGET_MASK_ARRAY(8822C , _MSDIO, pArray);\n#endif\n#endif /*CONFIG_SDIO_HCI*/\n}\n\nu16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\n#ifdef CONFIG_USB_HCI\n#if defined(CONFIG_RTL8188E)\n\tif (IS_HARDWARE_TYPE_8188E(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8188E, _MUSB);\n#endif\n#if defined(CONFIG_RTL8812A)\n\tif (IS_HARDWARE_TYPE_8812(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8812A, _MUSB);\n#endif\n#if defined(CONFIG_RTL8821A)\n\tif (IS_HARDWARE_TYPE_8821(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8821A, _MUSB);\n#endif\n#if defined(CONFIG_RTL8192E)\n\tif (IS_HARDWARE_TYPE_8192E(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8192E, _MUSB);\n#endif\n#if defined(CONFIG_RTL8723B)\n\tif (IS_HARDWARE_TYPE_8723B(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8723B, _MUSB);\n#endif\n#if defined(CONFIG_RTL8703B)\n\tif (IS_HARDWARE_TYPE_8703B(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8703B, _MUSB);\n#endif\n#if defined(CONFIG_RTL8188F)\n\tif (IS_HARDWARE_TYPE_8188F(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8188F, _MUSB);\n#endif\n#if defined(CONFIG_RTL8188GTV)\n\tif (IS_HARDWARE_TYPE_8188GTV(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8188GTV, _MUSB);\n#endif\n#if defined(CONFIG_RTL8814A)\n\tif (IS_HARDWARE_TYPE_8814A(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8814A, _MUSB);\n#endif\n#if defined(CONFIG_RTL8822B)\n\tif (IS_HARDWARE_TYPE_8822B(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8822B, _MUSB);\n#endif\n#if defined(CONFIG_RTL8821C)\n\tif (IS_HARDWARE_TYPE_8821CU(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8821C, _MUSB);\n#endif\n#if defined(CONFIG_RTL8192F)\n\tif (IS_HARDWARE_TYPE_8192FU(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8192F, _MUSB);\n#endif\n#if defined(CONFIG_RTL8822C)\n\tif (IS_HARDWARE_TYPE_8822C(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8822C, _MUSB);\n#endif\n#endif /*CONFIG_USB_HCI*/\n\n#ifdef CONFIG_PCI_HCI\n#if defined(CONFIG_RTL8188E)\n\tif (IS_HARDWARE_TYPE_8188E(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8188E, _MPCIE);\n#endif\n#if defined(CONFIG_RTL8192E)\n\tif (IS_HARDWARE_TYPE_8192E(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8192E, _MPCIE);\n#endif\n#if defined(CONFIG_RTL8812A)\n\tif (IS_HARDWARE_TYPE_8812(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8812A, _MPCIE);\n#endif\n#if defined(CONFIG_RTL8821A)\n\tif (IS_HARDWARE_TYPE_8821(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8821A, _MPCIE);\n#endif\n#if defined(CONFIG_RTL8723B)\n\tif (IS_HARDWARE_TYPE_8723B(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8723B, _MPCIE);\n#endif\n#if defined(CONFIG_RTL8814A)\n\tif (IS_HARDWARE_TYPE_8814A(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8814A, _MPCIE);\n#endif\n#if defined(CONFIG_RTL8822B)\n\tif (IS_HARDWARE_TYPE_8822B(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8822B, _MPCIE);\n#endif\n#if defined(CONFIG_RTL8821C)\n\tif (IS_HARDWARE_TYPE_8821CE(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8821C, _MPCIE);\n#endif\n#if defined(CONFIG_RTL8192F)\n\tif (IS_HARDWARE_TYPE_8192FE(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8192F, _MPCIE);\n#endif\n#if defined(CONFIG_RTL8822C)\n\tif (IS_HARDWARE_TYPE_8822C(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8822C, _MPCIE);\n#endif\n#endif /*CONFIG_PCI_HCI*/\n\n#ifdef CONFIG_SDIO_HCI\n#if defined(CONFIG_RTL8188E)\n\tif (IS_HARDWARE_TYPE_8188E(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8188E, _MSDIO);\n#endif\n#if defined(CONFIG_RTL8723B)\n\tif (IS_HARDWARE_TYPE_8723BS(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8723B, _MSDIO);\n#endif\n#if defined(CONFIG_RTL8188F)\n\tif (IS_HARDWARE_TYPE_8188F(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8188F, _MSDIO);\n#endif\n#if defined(CONFIG_RTL8188GTV)\n\tif (IS_HARDWARE_TYPE_8188GTV(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8188GTV, _MSDIO);\n#endif\n#if defined(CONFIG_RTL8192E)\n\tif (IS_HARDWARE_TYPE_8192ES(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8192E, _MSDIO);\n#endif\n#if defined(CONFIG_RTL8821A)\n\tif (IS_HARDWARE_TYPE_8821S(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8821A, _MSDIO);\n#endif\n#if defined(CONFIG_RTL8821C)\n\tif (IS_HARDWARE_TYPE_8821CS(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8821C, _MSDIO);\n#endif\n#if defined(CONFIG_RTL8822B)\n\tif (IS_HARDWARE_TYPE_8822B(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8822B, _MSDIO);\n#endif\n#if defined(CONFIG_RTL8192F)\n\tif (IS_HARDWARE_TYPE_8192FS(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8192F, _MSDIO);\n#endif\n#if defined(CONFIG_RTL8822C)\n\tif (IS_HARDWARE_TYPE_8822C(pAdapter))\n\t\treturn GET_MASK_ARRAY_LEN(8822C, _MSDIO);\n#endif\n#endif/*CONFIG_SDIO_HCI*/\n\treturn 0;\n}\n\nstatic void rtw_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)\n{\n\tu16 i = 0;\n\n\tif (padapter->registrypriv.boffefusemask == 0) {\n\t\tfor (i = 0; i < cnts; i++) {\n\t\t\tif (padapter->registrypriv.bFileMaskEfuse == _TRUE) {\n\t\t\t\t\tif (rtw_file_efuse_IsMasked(padapter, addr + i, maskfileBuffer)) /*use file efuse mask.*/\n\t\t\t\t\t\tdata[i] = 0xff;\n\t\t\t\t\telse\n\t\t\t\t\t\tRTW_DBG(\"data[%x] = %x\\n\", i, data[i]);\n\t\t\t} else {\n\t\t\t\t\tif (efuse_IsMasked(padapter, addr + i))\n\t\t\t\t\t\tdata[i] = 0xff;\n\t\t\t\t\telse\n\t\t\t\t\t\tRTW_DBG(\"data[%x] = %x\\n\", i, data[i]);\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic void rtw_bt_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)\n{\n\tu16 i = 0;\n\n\tif (padapter->registrypriv.boffefusemask == 0) {\n\t\t\tfor (i = 0; i < cnts; i++) {\n\t\t\t\tif (padapter->registrypriv.bBTFileMaskEfuse == _TRUE) {\n\t\t\t\t\t\tif (rtw_file_efuse_IsMasked(padapter, addr + i, btmaskfileBuffer)) /*use BT file efuse mask.*/\n\t\t\t\t\t\t\tdata[i] = 0xff;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tRTW_DBG(\"data[%x] = %x\\n\", i, data[i]);\n\t\t\t\t} else {\n\t\t\t\t\t\tif (efuse_IsBT_Masked(padapter, addr + i)) /*use drv internal efuse mask.*/\n\t\t\t\t\t\t\tdata[i] = 0xff;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tRTW_DBG(\"data[%x] = %x\\n\", i, data[i]);\n\t\t\t\t\t}\n\t\t\t}\n\t}\n\n}\n\n\nu8 rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)\n{\n\tu8\tret = _SUCCESS;\n\tu16\tmapLen = 0;\n\n\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);\n\n\tret = rtw_efuse_map_read(padapter, addr, cnts , data);\n\n\trtw_mask_map_read(padapter, addr, cnts , data);\n\n\treturn ret;\n\n}\n\n/* ***********************************************************\n *\t\t\t\tEfuse related code\n * *********************************************************** */\nstatic u8 hal_EfuseSwitchToBank(\n\tPADAPTER\tpadapter,\n\tu8\t\t\tbank,\n\tu8\t\t\tbPseudoTest)\n{\n\tu8 bRet = _FALSE;\n\tu32 value32 = 0;\n#ifdef HAL_EFUSE_MEMORY\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);\n\tPEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;\n#endif\n\n\n\tRTW_INFO(\"%s: Efuse switch bank to %d\\n\", __FUNCTION__, bank);\n\tif (bPseudoTest) {\n#ifdef HAL_EFUSE_MEMORY\n\t\tpEfuseHal->fakeEfuseBank = bank;\n#else\n\t\tfakeEfuseBank = bank;\n#endif\n\t\tbRet = _TRUE;\n\t} else {\n\t\tvalue32 = rtw_read32(padapter, 0x34);\n\t\tbRet = _TRUE;\n\t\tswitch (bank) {\n\t\tcase 0:\n\t\t\tvalue32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tvalue32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0);\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tvalue32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1);\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\tvalue32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tvalue32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);\n\t\t\tbRet = _FALSE;\n\t\t\tbreak;\n\t\t}\n\t\trtw_write32(padapter, 0x34, value32);\n\t}\n\n\treturn bRet;\n}\n\nvoid rtw_efuse_analyze(PADAPTER\tpadapter, u8 Type, u8 Fake)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tPEFUSE_HAL\t\tpEfuseHal = &(pHalData->EfuseHal);\n\tu16\teFuse_Addr = 0;\n\tu8 offset, wden;\n\tu16\t i, j;\n\tu8\tu1temp = 0;\n\tu8\tefuseHeader = 0, efuseExtHdr = 0, efuseData[EFUSE_MAX_WORD_UNIT*2] = {0}, dataCnt = 0;\n\tu16\tefuseHeader2Byte = 0;\n\tu8\t*eFuseWord = NULL;// [EFUSE_MAX_SECTION_NUM][EFUSE_MAX_WORD_UNIT];\n\tu8\toffset_2_0 = 0;\n\tu8\tpgSectionCnt = 0;\n\tu8\twd_cnt = 0;\n\tu8\tmax_section = 64;\n\tu16\tmapLen = 0, maprawlen = 0;\n\tboolean\tbExtHeader = _FALSE;\n\tu8\tefuseType = EFUSE_WIFI;\n\tboolean\tbPseudoTest = _FALSE;\n\tu8\tbank = 0, startBank = 0, endBank = 1-1;\n\tboolean\tbCheckNextBank = FALSE;\n\tu8\tprotectBytesBank = 0;\n\tu16\tefuse_max = 0;\n\tu8\tParseEfuseExtHdr, ParseEfuseHeader, ParseOffset, ParseWDEN, ParseOffset2_0;\n\n\teFuseWord = rtw_zmalloc(EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2));\n\n\tRTW_INFO(\"\\n\");\n\tif (Type == 0) {\n\t\tif (Fake == 0) {\n\t\t\tRTW_INFO(\"\\n\\tEFUSE_Analyze Wifi Content\\n\");\n\t\t\tefuseType = EFUSE_WIFI;\n\t\t\tbPseudoTest = FALSE;\n\t\t\tstartBank = 0;\n\t\t\tendBank = 0;\n\t\t} else {\n\t\t\tRTW_INFO(\"\\n\\tEFUSE_Analyze Wifi Pseudo Content\\n\");\n\t\t\tefuseType = EFUSE_WIFI;\n\t\t\tbPseudoTest = TRUE;\n\t\t\tstartBank = 0;\n\t\t\tendBank = 0;\n\t\t}\n\t} else {\n\t\tif (Fake == 0) {\n\t\t\tRTW_INFO(\"\\n\\tEFUSE_Analyze BT Content\\n\");\n\t\t\tefuseType = EFUSE_BT;\n\t\t\tbPseudoTest = FALSE;\n\t\t\tstartBank = 1;\n\t\t\tendBank = EFUSE_MAX_BANK - 1;\n\t\t} else {\n\t\t\tRTW_INFO(\"\\n\\tEFUSE_Analyze BT Pseudo Content\\n\");\n\t\t\tefuseType = EFUSE_BT;\n\t\t\tbPseudoTest = TRUE;\n\t\t\tstartBank = 1;\n\t\t\tendBank = EFUSE_MAX_BANK - 1;\n\t\t\tif (IS_HARDWARE_TYPE_8821(padapter))\n\t\t\t\tendBank = 3 - 1;/*EFUSE_MAX_BANK_8821A - 1;*/\n\t\t}\n\t}\n\n\tRTW_INFO(\"\\n\\r 1Byte header, [7:4]=offset, [3:0]=word enable\\n\");\n\tRTW_INFO(\"\\n\\r 2Byte header, header[7:5]=offset[2:0], header[4:0]=0x0F\\n\");\n\tRTW_INFO(\"\\n\\r 2Byte header, extHeader[7:4]=offset[6:3], extHeader[3:0]=word enable\\n\");\n\n\tEFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, bPseudoTest);\n\tEFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_MAX_SECTION, (void *)&max_section, bPseudoTest);\n\tEFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_PROTECT_BYTES_BANK, (void *)&protectBytesBank, bPseudoTest);\n\tEFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_CONTENT_LEN_BANK, (void *)&efuse_max, bPseudoTest);\n\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (void *)&maprawlen, _FALSE);\n\n\t_rtw_memset(eFuseWord, 0xff, EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2));\n\t_rtw_memset(pEfuseHal->fakeEfuseInitMap, 0xff, EFUSE_MAX_MAP_LEN);\n\n\tif (IS_HARDWARE_TYPE_8821(padapter))\n\t\tendBank = 3 - 1;/*EFUSE_MAX_BANK_8821A - 1;*/\n\n\tfor (bank = startBank; bank <= endBank; bank++) {\n\t\tif (!hal_EfuseSwitchToBank(padapter, bank, bPseudoTest)) {\n\t\t\tRTW_INFO(\"EFUSE_SwitchToBank() Fail!!\\n\");\n\t\t\tgoto out_free_buffer;\n\t\t}\n\n\t\teFuse_Addr = bank * EFUSE_MAX_BANK_SIZE;\n\n\t\tefuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);\n\n\t\tif (efuseHeader == 0xFF && bank == startBank && Fake != TRUE) {\n\t\t\tRTW_INFO(\"Non-PGed Efuse\\n\");\n\t\t\tgoto out_free_buffer;\n\t\t}\n\t\tRTW_INFO(\"EFUSE_REAL_CONTENT_LEN = %d\\n\", maprawlen);\n\n\t\twhile ((efuseHeader != 0xFF) && ((efuseType == EFUSE_WIFI && (eFuse_Addr < maprawlen)) || (efuseType == EFUSE_BT && (eFuse_Addr < (endBank + 1) * EFUSE_MAX_BANK_SIZE)))) {\n\n\t\t\tRTW_INFO(\"Analyzing: Offset: 0x%X\\n\", eFuse_Addr);\n\n\t\t\t/* Check PG header for section num.*/\n\t\t\tif (EXT_HEADER(efuseHeader)) {\n\t\t\t\tbExtHeader = TRUE;\n\t\t\t\toffset_2_0 = GET_HDR_OFFSET_2_0(efuseHeader);\n\t\t\t\tefuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);\n\n\t\t\t\tif (efuseExtHdr != 0xff) {\n\t\t\t\t\tif (ALL_WORDS_DISABLED(efuseExtHdr)) {\n\t\t\t\t\t\t/* Read next pg header*/\n\t\t\t\t\t\tefuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t} else {\n\t\t\t\t\t\toffset = ((efuseExtHdr & 0xF0) >> 1) | offset_2_0;\n\t\t\t\t\t\twden = (efuseExtHdr & 0x0F);\n\t\t\t\t\t\tefuseHeader2Byte = (efuseExtHdr<<8)|efuseHeader;\n\t\t\t\t\t\tRTW_INFO(\"Find efuseHeader2Byte = 0x%04X, offset=%d, wden=0x%x\\n\",\n\t\t\t\t\t\t\t\t\t\tefuseHeader2Byte, offset, wden);\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tRTW_INFO(\"Error, efuse[%d]=0xff, efuseExtHdr=0xff\\n\", eFuse_Addr-1);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\toffset = ((efuseHeader >> 4) & 0x0f);\n\t\t\t\twden = (efuseHeader & 0x0f);\n\t\t\t}\n\n\t\t\t_rtw_memset(efuseData, '\\0', EFUSE_MAX_WORD_UNIT * 2);\n\t\t\tdataCnt = 0;\n\n\t\t\tif (offset < max_section) {\n\t\t\t\tfor (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {\n\t\t\t\t\t/* Check word enable condition in the section\t*/\n\t\t\t\t\tif (!(wden & (0x01<<i))) {\n\t\t\t\t\t\tif (!((efuseType == EFUSE_WIFI && (eFuse_Addr + 2 < maprawlen)) ||\n\t\t\t\t\t\t\t\t(efuseType == EFUSE_BT && (eFuse_Addr + 2 < (endBank + 1) * EFUSE_MAX_BANK_SIZE)))) {\n\t\t\t\t\t\t\tRTW_INFO(\"eFuse_Addr exceeds, break\\n\");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t}\n\t\t\t\t\t\tefuse_OneByteRead(padapter, eFuse_Addr++, &efuseData[dataCnt++], bPseudoTest);\n\t\t\t\t\t\teFuseWord[(offset * 8) + (i * 2)] = (efuseData[dataCnt - 1]);\n\t\t\t\t\t\tefuse_OneByteRead(padapter, eFuse_Addr++, &efuseData[dataCnt++], bPseudoTest);\n\t\t\t\t\t\teFuseWord[(offset * 8) + (i * 2 + 1)] = (efuseData[dataCnt - 1]);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (bExtHeader) {\n\t\t\t\tRTW_INFO(\"Efuse PG Section (%d) = \", pgSectionCnt);\n\t\t\t\tRTW_INFO(\"[ %04X ], [\", efuseHeader2Byte);\n\n\t\t\t} else {\n\t\t\t\tRTW_INFO(\"Efuse PG Section (%d) = \", pgSectionCnt);\n\t\t\t\tRTW_INFO(\"[ %02X ], [\", efuseHeader);\n\t\t\t}\n\n\t\t\tfor (j = 0; j < dataCnt; j++)\n\t\t\t\tRTW_INFO(\" %02X \", efuseData[j]);\n\n\t\t\tRTW_INFO(\"]\\n\");\n\n\n\t\t\tif (bExtHeader) {\n\t\t\t\tParseEfuseExtHdr = (efuseHeader2Byte & 0xff00) >> 8;\n\t\t\t\tParseEfuseHeader = (efuseHeader2Byte & 0xff);\n\t\t\t\tParseOffset2_0 = GET_HDR_OFFSET_2_0(ParseEfuseHeader);\n\t\t\t\tParseOffset = ((ParseEfuseExtHdr & 0xF0) >> 1) | ParseOffset2_0;\n\t\t\t\tParseWDEN = (ParseEfuseExtHdr & 0x0F);\n\t\t\t\tRTW_INFO(\"Header=0x%x, ExtHeader=0x%x, \", ParseEfuseHeader, ParseEfuseExtHdr);\n\t\t\t} else {\n\t\t\t\tParseEfuseHeader = efuseHeader;\n\t\t\t\tParseOffset = ((ParseEfuseHeader >> 4) & 0x0f);\n\t\t\t\tParseWDEN = (ParseEfuseHeader & 0x0f);\n\t\t\t\tRTW_INFO(\"Header=0x%x, \", ParseEfuseHeader);\n\t\t\t}\n\t\t\tRTW_INFO(\"offset=0x%x(%d), word enable=0x%x\\n\", ParseOffset, ParseOffset, ParseWDEN);\n\n\t\t\twd_cnt = 0;\n\t\t\tfor (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {\n\t\t\t\tif (!(wden & (0x01 << i))) {\n\t\t\t\t\tRTW_INFO(\"Map[ %02X ] = %02X %02X\\n\", ((offset * EFUSE_MAX_WORD_UNIT * 2) + (i * 2)), efuseData[wd_cnt * 2 + 0], efuseData[wd_cnt * 2 + 1]);\n\t\t\t\t\twd_cnt++;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tpgSectionCnt++;\n\t\t\tbExtHeader = FALSE;\n\t\t\tefuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);\n\t\t\tif (efuseHeader == 0xFF) {\n\t\t\t\tif ((eFuse_Addr + protectBytesBank) >= efuse_max)\n\t\t\t\t\tbCheckNextBank = TRUE;\n\t\t\t\telse\n\t\t\t\t\tbCheckNextBank = FALSE;\n\t\t\t}\n\t\t}\n\t\tif (!bCheckNextBank) {\n\t\t\tRTW_INFO(\"Not need to check next bank, eFuse_Addr=%d, protectBytesBank=%d, efuse_max=%d\\n\",\n\t\t\t\teFuse_Addr, protectBytesBank, efuse_max);\n\t\t\tbreak;\n\t\t}\n\t}\n\t/* switch bank back to 0 for BT/wifi later use*/\n\thal_EfuseSwitchToBank(padapter, 0, bPseudoTest);\n\n\t/* 3. Collect 16 sections and 4 word unit into Efuse map.*/\n\tfor (i = 0; i < max_section; i++) {\n\t\tfor (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) {\n\t\t\tpEfuseHal->fakeEfuseInitMap[(i*8)+(j*2)] = (eFuseWord[(i*8)+(j*2)]);\n\t\t\tpEfuseHal->fakeEfuseInitMap[(i*8)+((j*2)+1)] =  (eFuseWord[(i*8)+((j*2)+1)]);\n\t\t}\n\t}\n\n\tRTW_INFO(\"\\n\\tEFUSE Analyze Map\\n\");\n\ti = 0;\n\tj = 0;\n\n\tfor (i = 0; i < mapLen; i++) {\n\t\tif (i % 16 == 0)\n\t\t\tRTW_PRINT_SEL(RTW_DBGDUMP, \"0x%03x: \", i);\n\t\t\t_RTW_PRINT_SEL(RTW_DBGDUMP, \"%02X%s\"\n\t\t\t\t, pEfuseHal->fakeEfuseInitMap[i]\n\t\t\t\t, ((i + 1) % 16 == 0) ? \"\\n\" : (((i + 1) % 8 == 0) ? \"\t  \" : \" \")\n\t\t\t);\n\t\t}\n\t_RTW_PRINT_SEL(RTW_DBGDUMP, \"\\n\");\n\nout_free_buffer:\n\tif (eFuseWord)\n\t\trtw_mfree((u8 *)eFuseWord, EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2));\n}\n\nvoid efuse_PreUpdateAction(\n\tPADAPTER\tpAdapter,\n\tu32\t\t\t*BackupRegs)\n{\n\tif (IS_HARDWARE_TYPE_8812AU(pAdapter) || IS_HARDWARE_TYPE_8822BU(pAdapter)) {\n\t\t/* <20131115, Kordan> Turn off Rx to prevent from being busy when writing the EFUSE. (Asked by Chunchu.)*/\n\t\tBackupRegs[0] = phy_query_mac_reg(pAdapter, REG_RCR, bMaskDWord);\n\t\tBackupRegs[1] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord);\n\t\tBackupRegs[2] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord);\n#ifdef CONFIG_RTL8812A\n\t\tBackupRegs[3] = phy_query_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord);\n#endif\n\t\tPlatformEFIOWrite4Byte(pAdapter, REG_RCR, 0x1);\n\t\tPlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0, 0);\n\t\tPlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+1, 0);\n\t\tPlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+2, 0);\n\t\tPlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+3, 0);\n\t\tPlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+4, 0);\n\t\tPlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+5, 0);\n#ifdef CONFIG_RTL8812A\n\t\t/* <20140410, Kordan> 0x11 = 0x4E, lower down LX_SPS0 voltage. (Asked by Chunchu)*/\n\t\tphy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskByte1, 0x4E);\n#endif\n\t\tRTW_INFO(\" %s , done\\n\", __func__);\n\n\t\t}\n}\n\n\nvoid efuse_PostUpdateAction(\n\tPADAPTER\tpAdapter,\n\tu32\t\t\t*BackupRegs)\n{\n\tif (IS_HARDWARE_TYPE_8812AU(pAdapter) || IS_HARDWARE_TYPE_8822BU(pAdapter)) {\n\t\t/* <20131115, Kordan> Turn on Rx and restore the registers. (Asked by Chunchu.)*/\n\t\tphy_set_mac_reg(pAdapter, REG_RCR, bMaskDWord, BackupRegs[0]);\n\t\tphy_set_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord, BackupRegs[1]);\n\t\tphy_set_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord, BackupRegs[2]);\n#ifdef CONFIG_RTL8812A\n\t\tphy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord, BackupRegs[3]);\n#endif\n\tRTW_INFO(\" %s , done\\n\", __func__);\n\t}\n}\n\n\n#ifdef RTW_HALMAC\n#include \"../../hal/hal_halmac.h\"\n\nvoid Efuse_PowerSwitch(PADAPTER adapter, u8 write, u8 pwrstate)\n{\n}\n\nvoid BTEfuse_PowerSwitch(PADAPTER adapter, u8 write, u8 pwrstate)\n{\n}\n\nu8 efuse_GetCurrentSize(PADAPTER adapter, u16 *size)\n{\n\t*size = 0;\n\n\treturn _FAIL;\n}\n\nu16 efuse_GetMaxSize(PADAPTER adapter)\n{\n\tstruct dvobj_priv *d;\n\tu32 size = 0;\n\tint err;\n\n\td = adapter_to_dvobj(adapter);\n\terr = rtw_halmac_get_physical_efuse_size(d, &size);\n\tif (err)\n\t\treturn 0;\n\n\treturn size;\n}\n\nu16 efuse_GetavailableSize(PADAPTER adapter)\n{\n\tstruct dvobj_priv *d;\n\tu32 size = 0;\n\tint err;\n\n\td = adapter_to_dvobj(adapter);\n\terr = rtw_halmac_get_available_efuse_size(d, &size);\n\tif (err)\n\t\treturn 0;\n\n\treturn size;\n}\n\n\nu8 efuse_bt_GetCurrentSize(PADAPTER adapter, u16 *usesize)\n{\n\tu8 *efuse_map;\n\n\t*usesize = 0;\n\tefuse_map = rtw_malloc(EFUSE_BT_MAP_LEN);\n\tif (efuse_map == NULL) {\n\t\tRTW_DBG(\"%s: malloc FAIL\\n\", __FUNCTION__);\n\t\treturn _FAIL;\n\t}\n\n\t/* for get bt phy efuse last use byte */\n\thal_ReadEFuse_BT_logic_map(adapter, 0x00, EFUSE_BT_MAP_LEN, efuse_map);\n\t*usesize = fakeBTEfuseUsedBytes;\n\n\tif (efuse_map)\n\t\trtw_mfree(efuse_map, EFUSE_BT_MAP_LEN);\n\n\treturn _SUCCESS;\n}\n\nu16 efuse_bt_GetMaxSize(PADAPTER adapter)\n{\n\treturn EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK;\n}\n\nvoid EFUSE_GetEfuseDefinition(PADAPTER adapter, u8 efusetype, u8 type, void *out, BOOLEAN test)\n{\n\tstruct dvobj_priv *d;\n\tu32 v32 = 0;\n\n\n\td = adapter_to_dvobj(adapter);\n\n\tif (adapter->hal_func.EFUSEGetEfuseDefinition) {\n\t\tadapter->hal_func.EFUSEGetEfuseDefinition(adapter, efusetype, type, out, test);\n\t\treturn;\n\t}\n\n\tif (EFUSE_WIFI == efusetype) {\n\t\tswitch (type) {\n\t\tcase TYPE_EFUSE_MAP_LEN:\n\t\t\trtw_halmac_get_logical_efuse_size(d, &v32);\n\t\t\t*(u16 *)out = (u16)v32;\n\t\t\treturn;\n\n\t\tcase TYPE_EFUSE_REAL_CONTENT_LEN:\n\t\t\trtw_halmac_get_physical_efuse_size(d, &v32);\n\t\t\t*(u16 *)out = (u16)v32;\n\t\t\treturn;\n\t\t}\n\t} else if (EFUSE_BT == efusetype) {\n\t\tswitch (type) {\n\t\tcase TYPE_EFUSE_MAP_LEN:\n\t\t\t*(u16 *)out = EFUSE_BT_MAP_LEN;\n\t\t\treturn;\n\n\t\tcase TYPE_EFUSE_REAL_CONTENT_LEN:\n\t\t\t*(u16 *)out = EFUSE_BT_REAL_CONTENT_LEN;\n\t\t\treturn;\n\t\t}\n\t}\n}\n\n/*\n * read/write raw efuse data\n */\nu8 rtw_efuse_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data)\n{\n\tstruct dvobj_priv *d;\n\tu8 *efuse = NULL;\n\tu32 size, i;\n\tint err;\n\n\n\td = adapter_to_dvobj(adapter);\n\terr = rtw_halmac_get_physical_efuse_size(d, &size);\n\tif (err){\n\t\tsize = EFUSE_MAX_SIZE;\n\t\tRTW_INFO(\" physical_efuse_size err size %d\\n\", size);\n\t}\n\n\tif ((addr + cnts) > size)\n\t\treturn _FAIL;\n\n\tif (_TRUE == write) {\n\t\terr = rtw_halmac_write_physical_efuse(d, addr, cnts, data);\n\t\tif (err)\n\t\t\treturn _FAIL;\n\t} else {\n\t\tif (cnts > 16)\n\t\t\tefuse = rtw_zmalloc(size);\n\n\t\tif (efuse) {\n\t\t\terr = rtw_halmac_read_physical_efuse_map(d, efuse, size);\n\t\t\tif (err) {\n\t\t\t\trtw_mfree(efuse, size);\n\t\t\t\treturn _FAIL;\n\t\t\t}\n\n\t\t\t_rtw_memcpy(data, efuse + addr, cnts);\n\t\t\trtw_mfree(efuse, size);\n\t\t} else {\n\t\t\terr = rtw_halmac_read_physical_efuse(d, addr, cnts, data);\n\t\t\tif (err)\n\t\t\t\treturn _FAIL;\n\t\t}\n\t}\n\n\treturn _SUCCESS;\n}\n\nstatic inline void dump_buf(u8 *buf, u32 len)\n{\n\tu32 i;\n\n\tRTW_INFO(\"-----------------Len %d----------------\\n\", len);\n\tfor (i = 0; i < len; i++)\n\t\tprintk(\"%2.2x-\", *(buf + i));\n\tprintk(\"\\n\");\n}\n\n/*\n * read/write raw efuse data\n */\nu8 rtw_efuse_bt_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data)\n{\n\tstruct dvobj_priv *d;\n\tu8 *efuse = NULL;\n\tu32 size, i;\n\tint err = _FAIL;\n\n\n\td = adapter_to_dvobj(adapter);\n\n\tsize = EFUSE_BT_REAL_CONTENT_LEN;\n\n\tif ((addr + cnts) > size)\n\t\treturn _FAIL;\n\n\tif (_TRUE == write) {\n\t\terr = rtw_halmac_write_bt_physical_efuse(d, addr, cnts, data);\n\t\tif (err == -1) {\n\t\t\tRTW_ERR(\"%s: rtw_halmac_write_bt_physical_efuse fail!\\n\", __FUNCTION__);\n\t\t\treturn _FAIL;\n\t\t}\n\t\tRTW_INFO(\"%s: rtw_halmac_write_bt_physical_efuse OK! data 0x%x\\n\", __FUNCTION__, *data);\n\t} else {\n\t\tefuse = rtw_zmalloc(size);\n\n\t\tif (efuse) {\n\t\t\terr = rtw_halmac_read_bt_physical_efuse_map(d, efuse, size);\n\n\t\t\tif (err == -1) {\n\t\t\t\tRTW_ERR(\"%s: rtw_halmac_read_bt_physical_efuse_map fail!\\n\", __FUNCTION__);\n\t\t\t\trtw_mfree(efuse, size);\n\t\t\t\treturn _FAIL;\n\t\t\t}\n\t\t\tdump_buf(efuse + addr, cnts);\n\n\t\t\t_rtw_memcpy(data, efuse + addr, cnts);\n\n\t\t\tRTW_INFO(\"%s: rtw_halmac_read_bt_physical_efuse_map ok! data 0x%x\\n\", __FUNCTION__, *data);\n\t\t\trtw_mfree(efuse, size);\n\t\t}\n\t}\n\n\treturn _SUCCESS;\n}\n\nu8 rtw_efuse_map_read(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)\n{\n\tstruct dvobj_priv *d;\n\tu8 *efuse = NULL;\n\tu32 size, i;\n\tint err;\n\tu32\tbackupRegs[4] = {0};\n\tu8 status = _SUCCESS;\n\n\tefuse_PreUpdateAction(adapter, backupRegs);\n\n\td = adapter_to_dvobj(adapter);\n\terr = rtw_halmac_get_logical_efuse_size(d, &size);\n\tif (err) {\n\t\tstatus = _FAIL;\n\t\tRTW_DBG(\"halmac_get_logical_efuse_size fail\\n\");\n\t\tgoto exit;\n\t}\n\t/* size error handle */\n\tif ((addr + cnts) > size) {\n\t\tif (addr < size)\n\t\t\tcnts = size - addr;\n\t\telse {\n\t\t\tstatus = _FAIL;\n\t\t\tRTW_DBG(\" %s() ,addr + cnts) > size fail\\n\", __func__);\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\tif (cnts > 16)\n\t\tefuse = rtw_zmalloc(size);\n\n\tif (efuse) {\n\t\terr = rtw_halmac_read_logical_efuse_map(d, efuse, size, NULL, 0);\n\t\tif (err) {\n\t\t\trtw_mfree(efuse, size);\n\t\t\tstatus = _FAIL;\n\t\t\tRTW_DBG(\" %s() ,halmac_read_logical_efus map fail\\n\", __func__);\n\t\t\tgoto exit;\n\t\t}\n\n\t\t_rtw_memcpy(data, efuse + addr, cnts);\n\t\trtw_mfree(efuse, size);\n\t} else {\n\t\terr = rtw_halmac_read_logical_efuse(d, addr, cnts, data);\n\t\tif (err) {\n\t\t\tstatus = _FAIL;\n\t\t\tRTW_DBG(\" %s() ,halmac_read_logical_efus data fail\\n\", __func__);\n\t\t\tgoto exit;\n\t\t}\n\t}\n\tstatus = _SUCCESS;\nexit:\n\tefuse_PostUpdateAction(adapter, backupRegs);\n\n\treturn status;\n}\n\nu8 rtw_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)\n{\n\tstruct dvobj_priv *d;\n\tu8 *efuse = NULL;\n\tu32 size, i;\n\tint err;\n\tu8 mask_buf[64] = \"\";\n\tu16 mask_len = sizeof(u8) * rtw_get_efuse_mask_arraylen(adapter);\n\tu32 backupRegs[4] = {0};\n\tu8 status = _SUCCESS;;\n\n\tefuse_PreUpdateAction(adapter, backupRegs);\n\n\td = adapter_to_dvobj(adapter);\n\terr = rtw_halmac_get_logical_efuse_size(d, &size);\n\tif (err) {\n\t\tstatus = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tif ((addr + cnts) > size) {\n\t\tstatus = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tefuse = rtw_zmalloc(size);\n\tif (!efuse) {\n\t\tstatus = _FAIL;\n\t\tgoto exit;\n\t}\n\n\terr = rtw_halmac_read_logical_efuse_map(d, efuse, size, NULL, 0);\n\tif (err) {\n\t\trtw_mfree(efuse, size);\n\t\tstatus = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t_rtw_memcpy(efuse + addr, data, cnts);\n\n\tif (adapter->registrypriv.boffefusemask == 0) {\n\t\tRTW_INFO(\"Use mask Array Len: %d\\n\", mask_len);\n\n\t\tif (mask_len != 0) {\n\t\t\tif (adapter->registrypriv.bFileMaskEfuse == _TRUE)\n\t\t\t\t_rtw_memcpy(mask_buf, maskfileBuffer, mask_len);\n\t\t\telse\n\t\t\t\trtw_efuse_mask_array(adapter, mask_buf);\n\n\t\t\terr = rtw_halmac_write_logical_efuse_map(d, efuse, size, mask_buf, mask_len);\n\t\t} else\n\t\t\terr = rtw_halmac_write_logical_efuse_map(d, efuse, size, NULL, 0);\n\t} else {\n\t\t_rtw_memset(mask_buf, 0xFF, sizeof(mask_buf));\n\t\tRTW_INFO(\"Efuse mask off\\n\");\n\t\terr = rtw_halmac_write_logical_efuse_map(d, efuse, size, mask_buf, size/16);\n\t}\n\n\tif (err) {\n\t\trtw_mfree(efuse, size);\n\t\tstatus = _FAIL;\n\t\tgoto exit;\n\t}\n\n\trtw_mfree(efuse, size);\n\tstatus = _SUCCESS;\nexit :\n\tefuse_PostUpdateAction(adapter, backupRegs);\n\n\treturn status;\n}\n\nint Efuse_PgPacketRead(PADAPTER adapter, u8 offset, u8 *data, BOOLEAN test)\n{\n\treturn _FALSE;\n}\n\nint Efuse_PgPacketWrite(PADAPTER adapter, u8 offset, u8 word_en, u8 *data, BOOLEAN test)\n{\n\treturn _FALSE;\n}\n\nu8 rtw_BT_efuse_map_read(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)\n{\n\thal_ReadEFuse_BT_logic_map(adapter, addr, cnts, data);\n\n\trtw_bt_mask_map_read(adapter, addr, cnts, data);\n\n\treturn _SUCCESS;\n}\n\nstatic u16\nhal_EfuseGetCurrentSize_BT(\n\tPADAPTER\tpadapter,\n\tu8\t\t\tbPseudoTest)\n{\n#ifdef HAL_EFUSE_MEMORY\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(padapter);\n\tPEFUSE_HAL\t\tpEfuseHal = &pHalData->EfuseHal;\n#endif\n\tu16 btusedbytes;\n\tu16\tefuse_addr;\n\tu8\tbank, startBank;\n\tu8\thoffset = 0, hworden = 0;\n\tu8\tefuse_data, word_cnts = 0;\n\tu16\tretU2 = 0;\n\tu8 bContinual = _TRUE;\n\n\n\tbtusedbytes = fakeBTEfuseUsedBytes;\n\n\tefuse_addr = (u16)((btusedbytes % EFUSE_BT_REAL_BANK_CONTENT_LEN));\n\tstartBank = (u8)(1 + (btusedbytes / EFUSE_BT_REAL_BANK_CONTENT_LEN));\n\n\tRTW_INFO(\"%s: start from bank=%d addr=0x%X\\n\", __FUNCTION__, startBank, efuse_addr);\n\tretU2 = EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK;\n\n\tfor (bank = startBank; bank < 3; bank++) {\n\t\tif (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == _FALSE) {\n\t\t\tRTW_ERR(\"%s: switch bank(%d) Fail!!\\n\", __FUNCTION__, bank);\n\t\t\t/* bank = EFUSE_MAX_BANK; */\n\t\t\tbreak;\n\t\t}\n\n\t\t/* only when bank is switched we have to reset the efuse_addr. */\n\t\tif (bank != startBank)\n\t\t\tefuse_addr = 0;\n\n\n\t\twhile (AVAILABLE_EFUSE_ADDR(efuse_addr)) {\n\t\t\tif (rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &efuse_data) == _FALSE) {\n\t\t\t\tRTW_ERR(\"%s: efuse_OneByteRead Fail! addr=0x%X !!\\n\", __FUNCTION__, efuse_addr);\n\t\t\t\t/* bank = EFUSE_MAX_BANK; */\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tRTW_INFO(\"%s: efuse_OneByteRead ! addr=0x%X !efuse_data=0x%X! bank =%d\\n\", __FUNCTION__, efuse_addr, efuse_data, bank);\n\n\t\t\tif (efuse_data == 0xFF)\n\t\t\t\tbreak;\n\n\t\t\tif (EXT_HEADER(efuse_data)) {\n\t\t\t\thoffset = GET_HDR_OFFSET_2_0(efuse_data);\n\t\t\t\tefuse_addr++;\n\t\t\t\trtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &efuse_data);\n\t\t\t\tRTW_INFO(\"%s: efuse_OneByteRead EXT_HEADER ! addr=0x%X !efuse_data=0x%X! bank =%d\\n\", __FUNCTION__, efuse_addr, efuse_data, bank);\n\n\t\t\t\tif (ALL_WORDS_DISABLED(efuse_data)) {\n\t\t\t\t\tefuse_addr++;\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\t/*\t\t\t\thoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); */\n\t\t\t\thoffset |= ((efuse_data & 0xF0) >> 1);\n\t\t\t\thworden = efuse_data & 0x0F;\n\t\t\t} else {\n\t\t\t\thoffset = (efuse_data >> 4) & 0x0F;\n\t\t\t\thworden =  efuse_data & 0x0F;\n\t\t\t}\n\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\": Offset=%d Worden=%#X\\n\",\n\t\t\t\t FUNC_ADPT_ARG(padapter), hoffset, hworden);\n\n\t\t\tword_cnts = Efuse_CalculateWordCnts(hworden);\n\t\t\t/* read next header */\n\t\t\tefuse_addr += (word_cnts * 2) + 1;\n\t\t}\n\t\t/* Check if we need to check next bank efuse */\n\t\tif (efuse_addr < retU2)\n\t\t\tbreak;/* don't need to check next bank. */\n\t}\n\tretU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;\n\n\tfakeBTEfuseUsedBytes = retU2;\n\tRTW_INFO(\"%s: CurrentSize=%d\\n\", __FUNCTION__, retU2);\n\treturn retU2;\n}\n\nu8 rtw_BT_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)\n{\n#define RT_ASSERT_RET(expr)\t\t\t\t\t\t\t\t\t\\\n\tif (!(expr)) {\t\t\t\t\t\t\t\t\t\t\\\n\t\tprintk(\"Assertion failed! %s at ......\\n\", #expr);\t\t\t\t\\\n\t\tprintk(\"\t  ......%s,%s, line=%d\\n\",__FILE__, __FUNCTION__, __LINE__);\t\\\n\t\treturn _FAIL;\t\\\n\t}\n\n\tu8\toffset, word_en;\n\tu8 *efuse = NULL;\n\tu8\t*map;\n\tu8\tnewdata[PGPKT_DATA_SIZE];\n\ts32 i = 0, j = 0, idx = 0, chk_total_byte = 0;\n\tu8\tret = _SUCCESS;\n\tu16 mapLen = 1024;\n\tu16 startAddr = 0;\n\n\tif ((addr + cnts) > mapLen)\n\t\treturn _FAIL;\n\n\tRT_ASSERT_RET(PGPKT_DATA_SIZE == 8); /* have to be 8 byte alignment */\n\tRT_ASSERT_RET((mapLen & 0x7) == 0); /* have to be PGPKT_DATA_SIZE alignment for memcpy */\n\n\tefuse = rtw_zmalloc(mapLen);\n\tif (!efuse)\n\t\treturn _FAIL;\n\n\tmap = rtw_zmalloc(mapLen);\n\tif (map == NULL) {\n\t\trtw_mfree(efuse, mapLen);\n\t\treturn _FAIL;\n\t}\n\n\t_rtw_memset(map, 0xFF, mapLen);\n\n\tret = rtw_BT_efuse_map_read(adapter, 0, mapLen, map);\n\tif (ret == _FAIL)\n\t\tgoto exit;\n\n\t_rtw_memcpy(efuse , map, mapLen);\n\t_rtw_memcpy(efuse + addr, data, cnts);\n\n\tif (adapter->registrypriv.boffefusemask == 0) {\n\t\tfor (i = 0; i < cnts; i++) {\n\t\t\tif (adapter->registrypriv.bFileMaskEfuse == _TRUE) {\n\t\t\t\tif (rtw_file_efuse_IsMasked(adapter, addr + i, btmaskfileBuffer)) /*use file efuse mask. */\n\t\t\t\t\tefuse[addr + i] = map[addr + i];\n\t\t\t} else {\n\t\t\t\tif (efuse_IsBT_Masked(adapter, addr + i))\n\t\t\t\t\tefuse[addr + i] = map[addr + i];\n\t\t\t}\n\t\t\tRTW_INFO(\"%s , efuse[%x] = %x, map = %x\\n\", __func__, addr + i, efuse[ addr + i], map[addr + i]);\n\t\t}\n\t}\n\t/* precheck pg efuse data byte*/\n\tchk_total_byte = 0;\n\tidx = 0;\n\toffset = (addr >> 3);\n\n\twhile (idx < cnts) {\n\t\tword_en = 0xF;\n\t\tj = (addr + idx) & 0x7;\n\t\tfor (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {\n\t\t\tif (efuse[addr + idx] != map[addr + idx])\n\t\t\t\tword_en &= ~BIT(i >> 1);\n\t\t}\n\n\t\tif (word_en != 0xF) {\n\t\t\tchk_total_byte += Efuse_CalculateWordCnts(word_en) * 2;\n\n\t\t\tif (offset >= EFUSE_MAX_SECTION_BASE) /* Over EFUSE_MAX_SECTION 16 for 2 ByteHeader */\n\t\t\t\tchk_total_byte += 2;\n\t\t\telse\n\t\t\t\tchk_total_byte += 1;\n\t\t}\n\n\t\toffset++;\n\t}\n\n\tRTW_INFO(\"Total PG bytes Count = %d\\n\", chk_total_byte);\n\tstartAddr = hal_EfuseGetCurrentSize_BT(adapter, _FALSE);\n\tRTW_INFO(\"%s: startAddr=%#X\\n\", __func__, startAddr);\n\n\tif (!AVAILABLE_EFUSE_ADDR(startAddr + chk_total_byte)) {\n\t\tRTW_INFO(\"%s: startAddr(0x%X) + PG data len %d >= efuse BT available offset (0x%X)\\n\",\n\t\t\t __func__, startAddr, chk_total_byte, EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK);\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tidx = 0;\n\toffset = (addr >> 3);\n\twhile (idx < cnts) {\n\t\tword_en = 0xF;\n\t\tj = (addr + idx) & 0x7;\n\t\t_rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE);\n\t\tfor (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {\n\t\t\tif (efuse[addr + idx] != map[addr + idx]) {\n\t\t\t\tword_en &= ~BIT(i >> 1);\n\t\t\t\tnewdata[i] = efuse[addr + idx];\n\t\t\t}\n\t\t}\n\n\t\tif (word_en != 0xF) {\n\t\t\tret = EfusePgPacketWrite_BT(adapter, offset, word_en, newdata, _FALSE);\n\t\t\tRTW_INFO(\"offset=%x\\n\", offset);\n\t\t\tRTW_INFO(\"word_en=%x\\n\", word_en);\n\t\t\tRTW_INFO(\"%s: data=\", __FUNCTION__);\n\t\t\tfor (i = 0; i < PGPKT_DATA_SIZE; i++)\n\t\t\t\tRTW_INFO(\"0x%02X \", newdata[i]);\n\t\t\tRTW_INFO(\"\\n\");\n\t\t\tif (ret == _FAIL)\n\t\t\t\tbreak;\n\t\t}\n\t\toffset++;\n\t}\nexit:\n\trtw_mfree(map, mapLen);\n\treturn ret;\n}\n\nvoid hal_ReadEFuse_BT_logic_map(\n\tPADAPTER\tpadapter,\n\tu16\t\t\t_offset,\n\tu16\t\t\t_size_byte,\n\tu8\t\t\t*pbuf\n)\n{\n\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(padapter);\n\tPEFUSE_HAL\t\tpEfuseHal = &pHalData->EfuseHal;\n\n\tu8\t*efuseTbl, *phyefuse;\n\tu8\tbank;\n\tu16\teFuse_Addr = 0;\n\tu8\tefuseHeader, efuseExtHdr, efuseData;\n\tu8\toffset, wden;\n\tu16\ti, total, used;\n\tu8\tefuse_usage;\n\n\n\t/* */\n\t/* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */\n\t/* */\n\tif ((_offset + _size_byte) > EFUSE_BT_MAP_LEN) {\n\t\tRTW_INFO(\"%s: Invalid offset(%#x) with read bytes(%#x)!!\\n\", __FUNCTION__, _offset, _size_byte);\n\t\treturn;\n\t}\n\n\tefuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN);\n\tphyefuse = rtw_malloc(EFUSE_BT_REAL_CONTENT_LEN);\n\tif (efuseTbl == NULL || phyefuse == NULL) {\n\t\tRTW_INFO(\"%s: efuseTbl or phyefuse malloc fail!\\n\", __FUNCTION__);\n\t\tgoto exit;\n\t}\n\n\t/* 0xff will be efuse default value instead of 0x00. */\n\t_rtw_memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);\n\t_rtw_memset(phyefuse, 0xFF, EFUSE_BT_REAL_CONTENT_LEN);\n\n\tif (rtw_efuse_bt_access(padapter, _FALSE, 0, EFUSE_BT_REAL_CONTENT_LEN, phyefuse))\n\t\tdump_buf(phyefuse, EFUSE_BT_REAL_BANK_CONTENT_LEN);\n\n\ttotal = BANK_NUM;\n\tfor (bank = 1; bank <= total; bank++) { /* 8723d Max bake 0~2 */\n\t\teFuse_Addr = 0;\n\n\t\twhile (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {\n\t\t\t/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); */\n\t\t\tefuseHeader = phyefuse[eFuse_Addr++];\n\n\t\t\tif (efuseHeader == 0xFF)\n\t\t\t\tbreak;\n\t\t\tRTW_INFO(\"%s: efuse[%#X]=0x%02x (header)\\n\", __FUNCTION__, (((bank - 1) * EFUSE_BT_REAL_CONTENT_LEN) + eFuse_Addr - 1), efuseHeader);\n\n\t\t\t/* Check PG header for section num. */\n\t\t\tif (EXT_HEADER(efuseHeader)) {\t/* extended header */\n\t\t\t\toffset = GET_HDR_OFFSET_2_0(efuseHeader);\n\t\t\t\tRTW_INFO(\"%s: extended header offset_2_0=0x%X\\n\", __FUNCTION__, offset);\n\n\t\t\t\t/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); */\n\t\t\t\tefuseExtHdr = phyefuse[eFuse_Addr++];\n\n\t\t\t\tRTW_INFO(\"%s: efuse[%#X]=0x%02x (ext header)\\n\", __FUNCTION__, (((bank - 1) * EFUSE_BT_REAL_CONTENT_LEN) + eFuse_Addr - 1), efuseExtHdr);\n\t\t\t\tif (ALL_WORDS_DISABLED(efuseExtHdr))\n\t\t\t\t\tcontinue;\n\n\t\t\t\toffset |= ((efuseExtHdr & 0xF0) >> 1);\n\t\t\t\twden = (efuseExtHdr & 0x0F);\n\t\t\t} else {\n\t\t\t\toffset = ((efuseHeader >> 4) & 0x0f);\n\t\t\t\twden = (efuseHeader & 0x0f);\n\t\t\t}\n\n\t\t\tif (offset < EFUSE_BT_MAX_SECTION) {\n\t\t\t\tu16 addr;\n\n\t\t\t\t/* Get word enable value from PG header */\n\t\t\t\tRTW_INFO(\"%s: Offset=%d Worden=%#X\\n\", __FUNCTION__, offset, wden);\n\n\t\t\t\taddr = offset * PGPKT_DATA_SIZE;\n\t\t\t\tfor (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {\n\t\t\t\t\t/* Check word enable condition in the section */\n\t\t\t\t\tif (!(wden & (0x01 << i))) {\n\t\t\t\t\t\tefuseData = 0;\n\t\t\t\t\t\t/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */\n\t\t\t\t\t\tefuseData = phyefuse[eFuse_Addr++];\n\n\t\t\t\t\t\tRTW_INFO(\"%s: efuse[%#X]=0x%02X\\n\", __FUNCTION__, eFuse_Addr - 1, efuseData);\n\t\t\t\t\t\tefuseTbl[addr] = efuseData;\n\n\t\t\t\t\t\tefuseData = 0;\n\t\t\t\t\t\t/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */\n\t\t\t\t\t\tefuseData = phyefuse[eFuse_Addr++];\n\n\t\t\t\t\t\tRTW_INFO(\"%s: efuse[%#X]=0x%02X\\n\", __FUNCTION__, eFuse_Addr - 1, efuseData);\n\t\t\t\t\t\tefuseTbl[addr + 1] = efuseData;\n\t\t\t\t\t}\n\t\t\t\t\taddr += 2;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tRTW_INFO(\"%s: offset(%d) is illegal!!\\n\", __FUNCTION__, offset);\n\t\t\t\teFuse_Addr += Efuse_CalculateWordCnts(wden) * 2;\n\t\t\t}\n\t\t}\n\n\t\tif ((eFuse_Addr - 1) < total) {\n\t\t\tRTW_INFO(\"%s: bank(%d) data end at %#x\\n\", __FUNCTION__, bank, eFuse_Addr - 1);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* switch bank back to bank 0 for later BT and wifi use. */\n\t//hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);\n\n\t/* Copy from Efuse map to output pointer memory!!! */\n\tfor (i = 0; i < _size_byte; i++)\n\t\tpbuf[i] = efuseTbl[_offset + i];\n\t/* Calculate Efuse utilization */\n\ttotal = EFUSE_BT_REAL_BANK_CONTENT_LEN;\n\n\tused = eFuse_Addr - 1;\n\n\tif (total)\n\t\tefuse_usage = (u8)((used * 100) / total);\n\telse\n\t\tefuse_usage = 100;\n\n\tfakeBTEfuseUsedBytes = used;\n\tRTW_INFO(\"%s: BTEfuseUsed last Bytes = %#x\\n\", __FUNCTION__, fakeBTEfuseUsedBytes);\n\nexit:\n\tif (efuseTbl)\n\t\trtw_mfree(efuseTbl, EFUSE_BT_MAP_LEN);\n\tif (phyefuse)\n\t\trtw_mfree(phyefuse, EFUSE_BT_REAL_BANK_CONTENT_LEN);\n}\n\n\nstatic u8 hal_EfusePartialWriteCheck(\n\tPADAPTER\t\tpadapter,\n\tu8\t\t\t\tefuseType,\n\tu16\t\t\t\t*pAddr,\n\tPPGPKT_STRUCT\tpTargetPkt,\n\tu8\t\t\t\tbPseudoTest)\n{\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(padapter);\n\tPEFUSE_HAL\t\tpEfuseHal = &pHalData->EfuseHal;\n\tu8\tbRet = _FALSE;\n\tu16\tstartAddr = 0, efuse_max_available_len = EFUSE_BT_REAL_BANK_CONTENT_LEN, efuse_max = EFUSE_BT_REAL_BANK_CONTENT_LEN;\n\tu8\tefuse_data = 0;\n\n\tstartAddr = (u16)fakeBTEfuseUsedBytes;\n\n\tstartAddr %= efuse_max;\n\tRTW_INFO(\"%s: startAddr=%#X\\n\", __FUNCTION__, startAddr);\n\n\twhile (1) {\n\t\tif (startAddr >= efuse_max_available_len) {\n\t\t\tbRet = _FALSE;\n\t\t\tRTW_INFO(\"%s: startAddr(%d) >= efuse_max_available_len(%d)\\n\",\n\t\t\t\t__FUNCTION__, startAddr, efuse_max_available_len);\n\t\t\tbreak;\n\t\t}\n\t\tif (rtw_efuse_bt_access(padapter, _FALSE, startAddr, 1, &efuse_data)&& (efuse_data != 0xFF)) {\n\t\t\tbRet = _FALSE;\n\t\t\tRTW_INFO(\"%s: Something Wrong! last bytes(%#X=0x%02X) is not 0xFF\\n\",\n\t\t\t\t __FUNCTION__, startAddr, efuse_data);\n\t\t\tbreak;\n\t\t} else {\n\t\t\t/* not used header, 0xff */\n\t\t\t*pAddr = startAddr;\n\t\t\t/*\t\t\tRTW_INFO(\"%s: Started from unused header offset=%d\\n\", __FUNCTION__, startAddr)); */\n\t\t\tbRet = _TRUE;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn bRet;\n}\n\n\nstatic u8 hal_EfusePgPacketWrite2ByteHeader(\n\tPADAPTER\t\tpadapter,\n\tu8\t\t\t\tefuseType,\n\tu16\t\t\t\t*pAddr,\n\tPPGPKT_STRUCT\tpTargetPkt,\n\tu8\t\t\t\tbPseudoTest)\n{\n\tu16\tefuse_addr, efuse_max_available_len = EFUSE_BT_REAL_BANK_CONTENT_LEN;\n\tu8\tpg_header = 0, tmp_header = 0;\n\tu8\trepeatcnt = 0;\n\n\t/*\tRTW_INFO(\"%s\\n\", __FUNCTION__); */\n\n\tefuse_addr = *pAddr;\n\tif (efuse_addr >= efuse_max_available_len) {\n\t\tRTW_INFO(\"%s: addr(%d) over avaliable(%d)!!\\n\", __FUNCTION__, efuse_addr, efuse_max_available_len);\n\t\treturn _FALSE;\n\t}\n\n\tpg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F;\n\t/*\tRTW_INFO(\"%s: pg_header=0x%x\\n\", __FUNCTION__, pg_header); */\n\n\tdo {\n\n\t\trtw_efuse_bt_access(padapter, _TRUE, efuse_addr, 1, &pg_header);\n\t\trtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &tmp_header);\n\n\t\tif (tmp_header != 0xFF)\n\t\t\tbreak;\n\t\tif (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {\n\t\t\tRTW_INFO(\"%s: Repeat over limit for pg_header!!\\n\", __FUNCTION__);\n\t\t\treturn _FALSE;\n\t\t}\n\t} while (1);\n\n\tif (tmp_header != pg_header) {\n\t\tRTW_ERR(\"%s: PG Header Fail!!(pg=0x%02X read=0x%02X)\\n\", __FUNCTION__, pg_header, tmp_header);\n\t\treturn _FALSE;\n\t}\n\n\t/* to write ext_header */\n\tefuse_addr++;\n\tpg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en;\n\n\tdo {\n\t\trtw_efuse_bt_access(padapter, _TRUE, efuse_addr, 1, &pg_header);\n\t\trtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &tmp_header);\n\n\t\tif (tmp_header != 0xFF)\n\t\t\tbreak;\n\t\tif (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {\n\t\t\tRTW_INFO(\"%s: Repeat over limit for ext_header!!\\n\", __FUNCTION__);\n\t\t\treturn _FALSE;\n\t\t}\n\t} while (1);\n\n\tif (tmp_header != pg_header) {\t/* offset PG fail */\n\t\tRTW_ERR(\"%s: PG EXT Header Fail!!(pg=0x%02X read=0x%02X)\\n\", __FUNCTION__, pg_header, tmp_header);\n\t\treturn _FALSE;\n\t}\n\n\t*pAddr = efuse_addr;\n\n\treturn _TRUE;\n}\n\n\nstatic u8 hal_EfusePgPacketWrite1ByteHeader(\n\tPADAPTER\t\tpAdapter,\n\tu8\t\t\t\tefuseType,\n\tu16\t\t\t\t*pAddr,\n\tPPGPKT_STRUCT\tpTargetPkt,\n\tu8\t\t\t\tbPseudoTest)\n{\n\tu8\tbRet = _FALSE;\n\tu8\tpg_header = 0, tmp_header = 0;\n\tu16\tefuse_addr = *pAddr;\n\tu8\trepeatcnt = 0;\n\n\n\t/*\tRTW_INFO(\"%s\\n\", __FUNCTION__); */\n\tpg_header = ((pTargetPkt->offset << 4) & 0xf0) | pTargetPkt->word_en;\n\n\tdo {\n\t\trtw_efuse_bt_access(pAdapter, _TRUE, efuse_addr, 1, &pg_header);\n\t\trtw_efuse_bt_access(pAdapter, _FALSE, efuse_addr, 1, &tmp_header);\n\n\t\tif (tmp_header != 0xFF)\n\t\t\tbreak;\n\t\tif (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {\n\t\t\tRTW_INFO(\"%s: Repeat over limit for pg_header!!\\n\", __FUNCTION__);\n\t\t\treturn _FALSE;\n\t\t}\n\t} while (1);\n\n\tif (tmp_header != pg_header) {\n\t\tRTW_ERR(\"%s: PG Header Fail!!(pg=0x%02X read=0x%02X)\\n\", __FUNCTION__, pg_header, tmp_header);\n\t\treturn _FALSE;\n\t}\n\n\t*pAddr = efuse_addr;\n\n\treturn _TRUE;\n}\n\nstatic u8 hal_EfusePgPacketWriteHeader(\n\tPADAPTER\t\tpadapter,\n\tu8\t\t\t\tefuseType,\n\tu16\t\t\t\t*pAddr,\n\tPPGPKT_STRUCT\tpTargetPkt,\n\tu8\t\t\t\tbPseudoTest)\n{\n\tu8 bRet = _FALSE;\n\n\tif (pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE)\n\t\tbRet = hal_EfusePgPacketWrite2ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);\n\telse\n\t\tbRet = hal_EfusePgPacketWrite1ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);\n\n\treturn bRet;\n}\n\n\nstatic u8\nHal_EfuseWordEnableDataWrite(\n\tPADAPTER\tpadapter,\n\tu16\t\t\tefuse_addr,\n\tu8\t\t\tword_en,\n\tu8\t\t\t*data,\n\tu8\t\t\tbPseudoTest)\n{\n\tu16\ttmpaddr = 0;\n\tu16\tstart_addr = efuse_addr;\n\tu8\tbadworden = 0x0F;\n\tu8\ttmpdata[PGPKT_DATA_SIZE];\n\n\n\t/*\tRTW_INFO(\"%s: efuse_addr=%#x word_en=%#x\\n\", __FUNCTION__, efuse_addr, word_en); */\n\t_rtw_memset(tmpdata, 0xFF, PGPKT_DATA_SIZE);\n\n\tif (!(word_en & BIT(0))) {\n\t\ttmpaddr = start_addr;\n\t\trtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[0]);\n\t\trtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[1]);\n\t\trtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[0]);\n\t\trtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[1]);\n\t\tif ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1]))\n\t\t\tbadworden &= (~BIT(0));\n\t}\n\tif (!(word_en & BIT(1))) {\n\t\ttmpaddr = start_addr;\n\t\trtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[2]);\n\t\trtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[3]);\n\t\trtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[2]);\n\t\trtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[3]);\n\t\tif ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3]))\n\t\t\tbadworden &= (~BIT(1));\n\t}\n\tif (!(word_en & BIT(2))) {\n\t\ttmpaddr = start_addr;\n\t\trtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[4]);\n\t\trtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[5]);\n\t\trtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[4]);\n\t\trtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[5]);\n\t\tif ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5]))\n\t\t\tbadworden &= (~BIT(2));\n\t}\n\tif (!(word_en & BIT(3))) {\n\t\ttmpaddr = start_addr;\n\t\trtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[6]);\n\t\trtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[7]);\n\t\trtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[6]);\n\t\trtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[7]);\n\n\t\tif ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7]))\n\t\t\tbadworden &= (~BIT(3));\n\t}\n\n\treturn badworden;\n}\n\nstatic void\nhal_EfuseConstructPGPkt(\n\tu8\t\t\t\toffset,\n\tu8\t\t\t\tword_en,\n\tu8\t\t\t\t*pData,\n\tPPGPKT_STRUCT\tpTargetPkt)\n{\n\t_rtw_memset(pTargetPkt->data, 0xFF, PGPKT_DATA_SIZE);\n\tpTargetPkt->offset = offset;\n\tpTargetPkt->word_en = word_en;\n\tefuse_WordEnableDataRead(word_en, pData, pTargetPkt->data);\n\tpTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);\n}\n\nstatic u8\nhal_EfusePgPacketWriteData(\n\tPADAPTER\t\tpAdapter,\n\tu8\t\t\t\tefuseType,\n\tu16\t\t\t\t*pAddr,\n\tPPGPKT_STRUCT\tpTargetPkt,\n\tu8\t\t\t\tbPseudoTest)\n{\n\tu16\tefuse_addr;\n\tu8\tbadworden;\n\n\tefuse_addr = *pAddr;\n\tbadworden = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr + 1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest);\n\tif (badworden != 0x0F) {\n\t\tRTW_INFO(\"%s: Fail!!\\n\", __FUNCTION__);\n\t\treturn _FALSE;\n\t} else\n\t\tRTW_INFO(\"%s: OK!!\\n\", __FUNCTION__);\n\n\treturn _TRUE;\n}\n\nu8 efuse_OneByteRead(struct _ADAPTER *a, u16 addr, u8 *data, u8 bPseudoTest)\n{\n\t\tstruct dvobj_priv *d;\n\t\tint err;\n\t\tu8 ret = _TRUE;\n\n\t\td = adapter_to_dvobj(a);\n\t\terr = rtw_halmac_read_physical_efuse(d, addr, 1, data);\n\t\tif (err) {\n\t\t\tRTW_ERR(\"%s: addr=0x%x FAIL!!!\\n\", __FUNCTION__, addr);\n\t\t\tret = _FALSE;\n\t\t}\n\n\t\treturn ret;\n\n}\n\n\nstatic u8\nhal_BT_EfusePgCheckAvailableAddr(\n\tPADAPTER\tpAdapter,\n\tu8\t\tbPseudoTest)\n{\n\tu16\tmax_available = EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK;\n\tu16\tcurrent_size = 0;\n\n\t RTW_INFO(\"%s: max_available=%d\\n\", __FUNCTION__, max_available);\n\tcurrent_size = hal_EfuseGetCurrentSize_BT(pAdapter, bPseudoTest);\n\tif (current_size >= max_available) {\n\t\tRTW_INFO(\"%s: Error!! current_size(%d)>max_available(%d)\\n\", __FUNCTION__, current_size, max_available);\n\t\treturn _FALSE;\n\t}\n\treturn _TRUE;\n}\n\nu8 EfusePgPacketWrite_BT(\n\tPADAPTER\tpAdapter,\n\tu8\t\t\toffset,\n\tu8\t\t\tword_en,\n\tu8\t\t\t*pData,\n\tu8\t\t\tbPseudoTest)\n{\n\tPGPKT_STRUCT targetPkt;\n\tu16 startAddr = 0;\n\tu8 efuseType = EFUSE_BT;\n\n\tif (!hal_BT_EfusePgCheckAvailableAddr(pAdapter, bPseudoTest))\n\t\treturn _FALSE;\n\n\thal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);\n\n\tif (!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))\n\t\treturn _FALSE;\n\n\tif (!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))\n\t\treturn _FALSE;\n\n\tif (!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))\n\t\treturn _FALSE;\n\n\treturn _TRUE;\n}\n\n\n#else /* !RTW_HALMAC */\n/* ------------------------------------------------------------------------------ */\n#define REG_EFUSE_CTRL\t\t0x0030\n#define EFUSE_CTRL\t\t\tREG_EFUSE_CTRL\t\t/* E-Fuse Control. */\n/* ------------------------------------------------------------------------------ */\n\n\nBOOLEAN\nEfuse_Read1ByteFromFakeContent(\n\t\tPADAPTER\tpAdapter,\n\t\tu16\t\tOffset,\n\t\tu8\t\t*Value);\nBOOLEAN\nEfuse_Read1ByteFromFakeContent(\n\t\tPADAPTER\tpAdapter,\n\t\tu16\t\tOffset,\n\t\tu8\t\t*Value)\n{\n\tif (Offset >= EFUSE_MAX_HW_SIZE)\n\t\treturn _FALSE;\n\t/* DbgPrint(\"Read fake content, offset = %d\\n\", Offset); */\n\tif (fakeEfuseBank == 0)\n\t\t*Value = fakeEfuseContent[Offset];\n\telse\n\t\t*Value = fakeBTEfuseContent[fakeEfuseBank - 1][Offset];\n\treturn _TRUE;\n}\n\nBOOLEAN\nEfuse_Write1ByteToFakeContent(\n\t\t\tPADAPTER\tpAdapter,\n\t\t\tu16\t\tOffset,\n\t\t\tu8\t\tValue);\nBOOLEAN\nEfuse_Write1ByteToFakeContent(\n\t\t\tPADAPTER\tpAdapter,\n\t\t\tu16\t\tOffset,\n\t\t\tu8\t\tValue)\n{\n\tif (Offset >= EFUSE_MAX_HW_SIZE)\n\t\treturn _FALSE;\n\tif (fakeEfuseBank == 0)\n\t\tfakeEfuseContent[Offset] = Value;\n\telse\n\t\tfakeBTEfuseContent[fakeEfuseBank - 1][Offset] = Value;\n\treturn _TRUE;\n}\n\n/*-----------------------------------------------------------------------------\n * Function:\tEfuse_PowerSwitch\n *\n * Overview:\tWhen we want to enable write operation, we should change to\n *\t\t\t\tpwr on state. When we stop write, we should switch to 500k mode\n *\t\t\t\tand disable LDO 2.5V.\n *\n * Input:       NONE\n *\n * Output:      NONE\n *\n * Return:      NONE\n *\n * Revised History:\n * When\t\t\tWho\t\tRemark\n * 11/17/2008\tMHC\t\tCreate Version 0.\n *\n *---------------------------------------------------------------------------*/\nvoid\nEfuse_PowerSwitch(\n\t\tPADAPTER\tpAdapter,\n\t\tu8\t\tbWrite,\n\t\tu8\t\tPwrState)\n{\n\tpAdapter->hal_func.EfusePowerSwitch(pAdapter, bWrite, PwrState);\n}\n\nvoid\nBTEfuse_PowerSwitch(\n\t\tPADAPTER\tpAdapter,\n\t\tu8\t\tbWrite,\n\t\tu8\t\tPwrState)\n{\n\tif (pAdapter->hal_func.BTEfusePowerSwitch)\n\t\tpAdapter->hal_func.BTEfusePowerSwitch(pAdapter, bWrite, PwrState);\n}\n\n/*-----------------------------------------------------------------------------\n * Function:\tefuse_GetCurrentSize\n *\n * Overview:\tGet current efuse size!!!\n *\n * Input:       NONE\n *\n * Output:      NONE\n *\n * Return:      NONE\n *\n * Revised History:\n * When\t\t\tWho\t\tRemark\n * 11/16/2008\tMHC\t\tCreate Version 0.\n *\n *---------------------------------------------------------------------------*/\nu16\nEfuse_GetCurrentSize(\n\tPADAPTER\t\tpAdapter,\n\tu8\t\t\tefuseType,\n\tBOOLEAN\t\tbPseudoTest)\n{\n\tu16 ret = 0;\n\n\tret = pAdapter->hal_func.EfuseGetCurrentSize(pAdapter, efuseType, bPseudoTest);\n\n\treturn ret;\n}\n\n/*\n *\tDescription:\n *\t\tExecute E-Fuse read byte operation.\n *\t\tRefered from SD1 Richard.\n *\n *\tAssumption:\n *\t\t1. Boot from E-Fuse and successfully auto-load.\n *\t\t2. PASSIVE_LEVEL (USB interface)\n *\n *\tCreated by Roger, 2008.10.21.\n *   */\nvoid\nReadEFuseByte(\n\tPADAPTER\tAdapter,\n\tu16\t\t\t_offset,\n\tu8\t\t\t*pbuf,\n\tBOOLEAN\tbPseudoTest)\n{\n\tu32\tvalue32;\n\tu8\treadbyte;\n\tu16\tretry;\n\t/* systime start=rtw_get_current_time(); */\n\n\tif (bPseudoTest) {\n\t\tEfuse_Read1ByteFromFakeContent(Adapter, _offset, pbuf);\n\t\treturn;\n\t}\n\tif (IS_HARDWARE_TYPE_8723B(Adapter)) {\n\t\t/* <20130121, Kordan> For SMIC S55 EFUSE specificatoin. */\n\t\t/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */\n\t\tphy_set_mac_reg(Adapter, EFUSE_TEST, BIT11, 0);\n\t}\n\t/* Write Address */\n\trtw_write8(Adapter, EFUSE_CTRL + 1, (_offset & 0xff));\n\treadbyte = rtw_read8(Adapter, EFUSE_CTRL + 2);\n\trtw_write8(Adapter, EFUSE_CTRL + 2, ((_offset >> 8) & 0x03) | (readbyte & 0xfc));\n\n\t/* Write bit 32 0 */\n\treadbyte = rtw_read8(Adapter, EFUSE_CTRL + 3);\n\trtw_write8(Adapter, EFUSE_CTRL + 3, (readbyte & 0x7f));\n\n\t/* Check bit 32 read-ready */\n\tretry = 0;\n\tvalue32 = rtw_read32(Adapter, EFUSE_CTRL);\n\t/* while(!(((value32 >> 24) & 0xff) & 0x80)  && (retry<10)) */\n\twhile (!(((value32 >> 24) & 0xff) & 0x80)  && (retry < 10000)) {\n\t\tvalue32 = rtw_read32(Adapter, EFUSE_CTRL);\n\t\tretry++;\n\t}\n\n\t/* 20100205 Joseph: Add delay suggested by SD1 Victor. */\n\t/* This fix the problem that Efuse read error in high temperature condition. */\n\t/* Designer says that there shall be some delay after ready bit is set, or the */\n\t/* result will always stay on last data we read. */\n\trtw_udelay_os(50);\n\tvalue32 = rtw_read32(Adapter, EFUSE_CTRL);\n\n\t*pbuf = (u8)(value32 & 0xff);\n\t/* RTW_INFO(\"ReadEFuseByte _offset:%08u, in %d ms\\n\",_offset ,rtw_get_passing_time_ms(start)); */\n\n}\n\n/*\n *\tDescription:\n *\t\t1. Execute E-Fuse read byte operation according as map offset and\n *\t\t    save to E-Fuse table.\n *\t\t2. Refered from SD1 Richard.\n *\n *\tAssumption:\n *\t\t1. Boot from E-Fuse and successfully auto-load.\n *\t\t2. PASSIVE_LEVEL (USB interface)\n *\n *\tCreated by Roger, 2008.10.21.\n *\n *\t2008/12/12 MH\t1. Reorganize code flow and reserve bytes. and add description.\n *\t\t\t\t\t2. Add efuse utilization collect.\n *\t2008/12/22 MH\tRead Efuse must check if we write section 1 data again!!! Sec1\n *\t\t\t\t\twrite addr must be after sec5.\n *   */\n\nvoid\nefuse_ReadEFuse(\n\tPADAPTER\tAdapter,\n\tu8\t\tefuseType,\n\tu16\t\t_offset,\n\tu16\t\t_size_byte,\n\tu8\t*pbuf,\n\tBOOLEAN\tbPseudoTest\n);\nvoid\nefuse_ReadEFuse(\n\tPADAPTER\tAdapter,\n\tu8\t\tefuseType,\n\tu16\t\t_offset,\n\tu16\t\t_size_byte,\n\tu8\t*pbuf,\n\tBOOLEAN\tbPseudoTest\n)\n{\n\tAdapter->hal_func.ReadEFuse(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);\n}\n\nvoid\nEFUSE_GetEfuseDefinition(\n\t\t\tPADAPTER\tpAdapter,\n\t\t\tu8\t\tefuseType,\n\t\t\tu8\t\ttype,\n\t\t\tvoid\t\t*pOut,\n\t\t\tBOOLEAN\t\tbPseudoTest\n)\n{\n\tpAdapter->hal_func.EFUSEGetEfuseDefinition(pAdapter, efuseType, type, pOut, bPseudoTest);\n}\n\n\n/*  11/16/2008 MH Read one byte from real Efuse. */\nu8\nefuse_OneByteRead(\n\t\tPADAPTER\tpAdapter,\n\t\tu16\t\t\taddr,\n\t\tu8\t\t\t*data,\n\t\tBOOLEAN\t\tbPseudoTest)\n{\n\tu32\ttmpidx = 0;\n\tu8\tbResult;\n\tu8\treadbyte;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\n\t/* RTW_INFO(\"===> EFUSE_OneByteRead(), addr = %x\\n\", addr); */\n\t/* RTW_INFO(\"===> EFUSE_OneByteRead() start, 0x34 = 0x%X\\n\", rtw_read32(pAdapter, EFUSE_TEST)); */\n\n\tif (bPseudoTest) {\n\t\tbResult = Efuse_Read1ByteFromFakeContent(pAdapter, addr, data);\n\t\treturn bResult;\n\t}\n\n#ifdef CONFIG_RTL8710B\n\t/* <20171208, Peter>, Dont do the following write16(0x34) */\n\tif (IS_HARDWARE_TYPE_8710B(pAdapter)) {\n\t\tbResult = pAdapter->hal_func.efuse_indirect_read4(pAdapter, addr, data);\n\t\treturn bResult;\n\t}\n#endif\n\n\tif (IS_HARDWARE_TYPE_8723B(pAdapter) ||\n\t    (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||\n\t    (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))\n\t   ) {\n\t\t/* <20130121, Kordan> For SMIC EFUSE specificatoin. */\n\t\t/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8])\t */\n\t\t/* phy_set_mac_reg(pAdapter, 0x34, BIT11, 0); */\n\t\trtw_write16(pAdapter, 0x34, rtw_read16(pAdapter, 0x34) & (~BIT11));\n\t}\n\n\t/* -----------------e-fuse reg ctrl --------------------------------- */\n\t/* address\t\t\t */\n\trtw_write8(pAdapter, EFUSE_CTRL + 1, (u8)(addr & 0xff));\n\trtw_write8(pAdapter, EFUSE_CTRL + 2, ((u8)((addr >> 8) & 0x03)) |\n\t\t   (rtw_read8(pAdapter, EFUSE_CTRL + 2) & 0xFC));\n\n\t/* rtw_write8(pAdapter, EFUSE_CTRL+3,  0x72); */ /* read cmd\t */\n\t/* Write bit 32 0 */\n\treadbyte = rtw_read8(pAdapter, EFUSE_CTRL + 3);\n\trtw_write8(pAdapter, EFUSE_CTRL + 3, (readbyte & 0x7f));\n\n\twhile (!(0x80 & rtw_read8(pAdapter, EFUSE_CTRL + 3)) && (tmpidx < 1000)) {\n\t\trtw_mdelay_os(1);\n\t\ttmpidx++;\n\t}\n\tif (tmpidx < 100) {\n\t\t*data = rtw_read8(pAdapter, EFUSE_CTRL);\n\t\tbResult = _TRUE;\n\t} else {\n\t\t*data = 0xff;\n\t\tbResult = _FALSE;\n\t\tRTW_INFO(\"%s: [ERROR] addr=0x%x bResult=%d time out 1s !!!\\n\", __FUNCTION__, addr, bResult);\n\t\tRTW_INFO(\"%s: [ERROR] EFUSE_CTRL =0x%08x !!!\\n\", __FUNCTION__, rtw_read32(pAdapter, EFUSE_CTRL));\n\t}\n\n\treturn bResult;\n}\n\n/*  11/16/2008 MH Write one byte to reald Efuse. */\nu8\nefuse_OneByteWrite(\n\t\tPADAPTER\tpAdapter,\n\t\tu16\t\t\taddr,\n\t\tu8\t\t\tdata,\n\t\tBOOLEAN\t\tbPseudoTest)\n{\n\tu8\ttmpidx = 0;\n\tu8\tbResult = _FALSE;\n\tu32 efuseValue = 0;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\n\t/* RTW_INFO(\"===> EFUSE_OneByteWrite(), addr = %x data=%x\\n\", addr, data); */\n\t/* RTW_INFO(\"===> EFUSE_OneByteWrite() start, 0x34 = 0x%X\\n\", rtw_read32(pAdapter, EFUSE_TEST)); */\n\n\tif (bPseudoTest) {\n\t\tbResult = Efuse_Write1ByteToFakeContent(pAdapter, addr, data);\n\t\treturn bResult;\n\t}\n\n\tEfuse_PowerSwitch(pAdapter, _TRUE, _TRUE);\n\n\t/* -----------------e-fuse reg ctrl ---------------------------------\t */\n\t/* address\t\t\t */\n\n\n\tefuseValue = rtw_read32(pAdapter, EFUSE_CTRL);\n\tefuseValue |= (BIT21 | BIT31);\n\tefuseValue &= ~(0x3FFFF);\n\tefuseValue |= ((addr << 8 | data) & 0x3FFFF);\n\n\t/* <20130227, Kordan> 8192E MP chip A-cut had better not set 0x34[11] until B-Cut. */\n\tif (IS_HARDWARE_TYPE_8723B(pAdapter) ||\n\t    (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||\n\t    (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))\n\t   ) {\n\t\t/* <20130121, Kordan> For SMIC EFUSE specificatoin. */\n\t\t/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */\n\t\t/* phy_set_mac_reg(pAdapter, 0x34, BIT11, 1); */\n\t\trtw_write16(pAdapter, 0x34, rtw_read16(pAdapter, 0x34) | (BIT11));\n\t\trtw_write32(pAdapter, EFUSE_CTRL, 0x90600000 | ((addr << 8 | data)));\n\t} else\n\t\trtw_write32(pAdapter, EFUSE_CTRL, efuseValue);\n\n\trtw_mdelay_os(1);\n\n\twhile ((0x80 &  rtw_read8(pAdapter, EFUSE_CTRL + 3)) && (tmpidx < 100)) {\n\t\trtw_mdelay_os(1);\n\t\ttmpidx++;\n\t}\n\n\tif (tmpidx < 100)\n\t\tbResult = _TRUE;\n\telse {\n\t\tbResult = _FALSE;\n\t\tRTW_INFO(\"%s: [ERROR] addr=0x%x ,efuseValue=0x%x ,bResult=%d time out 1s !!!\\n\",\n\t\t\t __FUNCTION__, addr, efuseValue, bResult);\n\t\tRTW_INFO(\"%s: [ERROR] EFUSE_CTRL =0x%08x !!!\\n\", __FUNCTION__, rtw_read32(pAdapter, EFUSE_CTRL));\n\t}\n\n\t/* disable Efuse program enable */\n\tif (IS_HARDWARE_TYPE_8723B(pAdapter) ||\n\t    (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||\n\t    (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))\n\t   )\n\t\tphy_set_mac_reg(pAdapter, EFUSE_TEST, BIT(11), 0);\n\n\tEfuse_PowerSwitch(pAdapter, _TRUE, _FALSE);\n\n\treturn bResult;\n}\n\nint\nEfuse_PgPacketRead(PADAPTER\tpAdapter,\n\t\t\tu8\t\t\toffset,\n\t\t\tu8\t\t\t*data,\n\t\t\tBOOLEAN\t\tbPseudoTest)\n{\n\tint\tret = 0;\n\n\tret =  pAdapter->hal_func.Efuse_PgPacketRead(pAdapter, offset, data, bPseudoTest);\n\n\treturn ret;\n}\n\nint\nEfuse_PgPacketWrite(PADAPTER\tpAdapter,\n\t\t\tu8\t\t\toffset,\n\t\t\tu8\t\t\tword_en,\n\t\t\tu8\t\t\t*data,\n\t\t\tBOOLEAN\t\tbPseudoTest)\n{\n\tint ret;\n\n\tret =  pAdapter->hal_func.Efuse_PgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest);\n\n\treturn ret;\n}\n\n\nint\nEfuse_PgPacketWrite_BT(PADAPTER\tpAdapter,\n\t\t\tu8\t\t\toffset,\n\t\t\tu8\t\t\tword_en,\n\t\t\tu8\t\t\t*data,\n\t\t\tBOOLEAN\t\tbPseudoTest)\n{\n\tint ret;\n\n\tret =  pAdapter->hal_func.Efuse_PgPacketWrite_BT(pAdapter, offset, word_en, data, bPseudoTest);\n\n\treturn ret;\n}\n\n\nu8\nEfuse_WordEnableDataWrite(PADAPTER\tpAdapter,\n\t\t\t\tu16\t\tefuse_addr,\n\t\t\t\tu8\t\tword_en,\n\t\t\t\tu8\t\t*data,\n\t\t\t\tBOOLEAN\t\tbPseudoTest)\n{\n\tu8\tret = 0;\n\n\tret =  pAdapter->hal_func.Efuse_WordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest);\n\n\treturn ret;\n}\n\nstatic u8 efuse_read8(PADAPTER padapter, u16 address, u8 *value)\n{\n\treturn efuse_OneByteRead(padapter, address, value, _FALSE);\n}\n\nstatic u8 efuse_write8(PADAPTER padapter, u16 address, u8 *value)\n{\n\treturn efuse_OneByteWrite(padapter, address, *value, _FALSE);\n}\n\n/*\n * read/wirte raw efuse data\n */\nu8 rtw_efuse_access(PADAPTER padapter, u8 bWrite, u16 start_addr, u16 cnts, u8 *data)\n{\n\tint i = 0;\n\tu16\treal_content_len = 0, max_available_size = 0;\n\tu8 res = _FAIL ;\n\tu8(*rw8)(PADAPTER, u16, u8 *);\n\tu32\tbackupRegs[4] = {0};\n\n\n\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (void *)&real_content_len, _FALSE);\n\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (void *)&max_available_size, _FALSE);\n\n\tif (start_addr > real_content_len)\n\t\treturn _FAIL;\n\n\tif (_TRUE == bWrite) {\n\t\tif ((start_addr + cnts) > max_available_size)\n\t\t\treturn _FAIL;\n\t\trw8 = &efuse_write8;\n\t} else\n\t\trw8 = &efuse_read8;\n\n\tefuse_PreUpdateAction(padapter, backupRegs);\n\n\tEfuse_PowerSwitch(padapter, bWrite, _TRUE);\n\n\t/* e-fuse one byte read / write */\n\tfor (i = 0; i < cnts; i++) {\n\t\tif (start_addr >= real_content_len) {\n\t\t\tres = _FAIL;\n\t\t\tbreak;\n\t\t}\n\n\t\tres = rw8(padapter, start_addr++, data++);\n\t\tif (_FAIL == res)\n\t\t\tbreak;\n\t}\n\n\tEfuse_PowerSwitch(padapter, bWrite, _FALSE);\n\n\tefuse_PostUpdateAction(padapter, backupRegs);\n\n\treturn res;\n}\n/* ------------------------------------------------------------------------------ */\nu16 efuse_GetMaxSize(PADAPTER padapter)\n{\n\tu16\tmax_size;\n\n\tmax_size = 0;\n\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI , TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (void *)&max_size, _FALSE);\n\treturn max_size;\n}\n/* ------------------------------------------------------------------------------ */\nu8 efuse_GetCurrentSize(PADAPTER padapter, u16 *size)\n{\n\tEfuse_PowerSwitch(padapter, _FALSE, _TRUE);\n\t*size = Efuse_GetCurrentSize(padapter, EFUSE_WIFI, _FALSE);\n\tEfuse_PowerSwitch(padapter, _FALSE, _FALSE);\n\n\treturn _SUCCESS;\n}\n/* ------------------------------------------------------------------------------ */\nu16 efuse_bt_GetMaxSize(PADAPTER padapter)\n{\n\tu16\tmax_size;\n\n\tmax_size = 0;\n\tEFUSE_GetEfuseDefinition(padapter, EFUSE_BT , TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (void *)&max_size, _FALSE);\n\treturn max_size;\n}\n\nu8 efuse_bt_GetCurrentSize(PADAPTER padapter, u16 *size)\n{\n\tEfuse_PowerSwitch(padapter, _FALSE, _TRUE);\n\t*size = Efuse_GetCurrentSize(padapter, EFUSE_BT, _FALSE);\n\tEfuse_PowerSwitch(padapter, _FALSE, _FALSE);\n\n\treturn _SUCCESS;\n}\n\nu8 rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)\n{\n\tu16\tmapLen = 0;\n\n\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);\n\n\tif ((addr + cnts) > mapLen)\n\t\treturn _FAIL;\n\n\tEfuse_PowerSwitch(padapter, _FALSE, _TRUE);\n\n\tefuse_ReadEFuse(padapter, EFUSE_WIFI, addr, cnts, data, _FALSE);\n\n\tEfuse_PowerSwitch(padapter, _FALSE, _FALSE);\n\n\treturn _SUCCESS;\n}\n\nu8 rtw_BT_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)\n{\n\tu16\tmapLen = 0;\n\n\tEFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);\n\n\tif ((addr + cnts) > mapLen)\n\t\treturn _FAIL;\n\n\tEfuse_PowerSwitch(padapter, _FALSE, _TRUE);\n\n\tefuse_ReadEFuse(padapter, EFUSE_BT, addr, cnts, data, _FALSE);\n\n\tEfuse_PowerSwitch(padapter, _FALSE, _FALSE);\n\n\treturn _SUCCESS;\n}\n\n/* ------------------------------------------------------------------------------ */\nu8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)\n{\n#define RT_ASSERT_RET(expr)\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif (!(expr)) {\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tprintk(\"Assertion failed! %s at ......\\n\", #expr);\t\t\t\t\t\t\t\\\n\t\tprintk(\"      ......%s,%s, line=%d\\n\",__FILE__, __FUNCTION__, __LINE__);\t\\\n\t\treturn _FAIL;\t\\\n\t}\n\n\tu8 *efuse = NULL;\n\tu8\toffset, word_en;\n\tu8\t*map = NULL;\n\tu8\tnewdata[PGPKT_DATA_SIZE];\n\ts32\ti, j, idx, chk_total_byte;\n\tu8\tret = _SUCCESS;\n\tu16\tmapLen = 0, startAddr = 0, efuse_max_available_len = 0;\n\tu32\tbackupRegs[4] = {0};\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tPEFUSE_HAL\tpEfuseHal = &pHalData->EfuseHal;\n\n\n\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);\n\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_max_available_len, _FALSE);\n\n\tif ((addr + cnts) > mapLen)\n\t\treturn _FAIL;\n\n\tRT_ASSERT_RET(PGPKT_DATA_SIZE == 8); /* have to be 8 byte alignment */\n\tRT_ASSERT_RET((mapLen & 0x7) == 0); /* have to be PGPKT_DATA_SIZE alignment for memcpy */\n\n\tefuse = rtw_zmalloc(mapLen);\n\tif (!efuse)\n\t\treturn _FAIL;\n\n\tmap = rtw_zmalloc(mapLen);\n\tif (map == NULL) {\n\t\trtw_mfree(efuse, mapLen);\n\t\treturn _FAIL;\n\t}\n\n\t_rtw_memset(map, 0xFF, mapLen);\n\n\tret = rtw_efuse_map_read(padapter, 0, mapLen, map);\n\tif (ret == _FAIL)\n\t\tgoto exit;\n\n\t_rtw_memcpy(efuse , map, mapLen);\n\t_rtw_memcpy(efuse + addr, data, cnts);\n\n\tif (padapter->registrypriv.boffefusemask == 0) {\n\t\tfor (i = 0; i < cnts; i++) {\n\t\t\tif (padapter->registrypriv.bFileMaskEfuse == _TRUE) {\n\t\t\t\tif (rtw_file_efuse_IsMasked(padapter, addr + i), maskfileBuffer) /*use file efuse mask. */\n\t\t\t\t\tefuse[addr + i] = map[addr + i];\n\t\t\t} else {\n\t\t\t\tif (efuse_IsMasked(padapter, addr + i))\n\t\t\t\t\tefuse[addr + i] = map[addr + i];\n\t\t\t}\n\t\t\tRTW_INFO(\"%s , data[%d] = %x, map[addr+i]= %x\\n\", __func__, addr + i, efuse[ addr + i], map[addr + i]);\n\t\t}\n\t}\n\t/*Efuse_PowerSwitch(padapter, _TRUE, _TRUE);*/\n\n\tchk_total_byte = 0;\n\tidx = 0;\n\toffset = (addr >> 3);\n\n\twhile (idx < cnts) {\n\t\tword_en = 0xF;\n\t\tj = (addr + idx) & 0x7;\n\t\tfor (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {\n\t\t\tif (efuse[addr + idx] != map[addr + idx])\n\t\t\t\tword_en &= ~BIT(i >> 1);\n\t\t}\n\n\t\tif (word_en != 0xF) {\n\t\t\tchk_total_byte += Efuse_CalculateWordCnts(word_en) * 2;\n\n\t\t\tif (offset >= EFUSE_MAX_SECTION_BASE) /* Over EFUSE_MAX_SECTION 16 for 2 ByteHeader */\n\t\t\t\tchk_total_byte += 2;\n\t\t\telse\n\t\t\t\tchk_total_byte += 1;\n\t\t}\n\n\t\toffset++;\n\t}\n\n\tRTW_INFO(\"Total PG bytes Count = %d\\n\", chk_total_byte);\n\trtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr);\n\n\tif (startAddr == 0) {\n\t\tstartAddr = Efuse_GetCurrentSize(padapter, EFUSE_WIFI, _FALSE);\n\t\tRTW_INFO(\"%s: Efuse_GetCurrentSize startAddr=%#X\\n\", __func__, startAddr);\n\t}\n\tRTW_DBG(\"%s: startAddr=%#X\\n\", __func__, startAddr);\n\n\tif ((startAddr + chk_total_byte) >= efuse_max_available_len) {\n\t\tRTW_INFO(\"%s: startAddr(0x%X) + PG data len %d >= efuse_max_available_len(0x%X)\\n\",\n\t\t\t __func__, startAddr, chk_total_byte, efuse_max_available_len);\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tefuse_PreUpdateAction(padapter, backupRegs);\n\n\tidx = 0;\n\toffset = (addr >> 3);\n\twhile (idx < cnts) {\n\t\tword_en = 0xF;\n\t\tj = (addr + idx) & 0x7;\n\t\t_rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE);\n\t\tfor (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {\n\t\t\tif (efuse[addr + idx] != map[addr + idx]) {\n\t\t\t\tword_en &= ~BIT(i >> 1);\n\t\t\t\tnewdata[i] = efuse[addr + idx];\n#ifdef CONFIG_RTL8723B\n\t\t\t\tif (addr + idx == 0x8) {\n\t\t\t\t\tif (IS_C_CUT(pHalData->version_id) || IS_B_CUT(pHalData->version_id)) {\n\t\t\t\t\t\tif (pHalData->adjuseVoltageVal == 6) {\n\t\t\t\t\t\t\tnewdata[i] = map[addr + idx];\n\t\t\t\t\t\t\tRTW_INFO(\" %s ,\\n adjuseVoltageVal = %d ,newdata[%d] = %x\\n\", __func__, pHalData->adjuseVoltageVal, i, newdata[i]);\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n#endif\n\t\t\t}\n\t\t}\n\n\t\tif (word_en != 0xF) {\n\t\t\tret = Efuse_PgPacketWrite(padapter, offset, word_en, newdata, _FALSE);\n\t\t\tRTW_INFO(\"offset=%x\\n\", offset);\n\t\t\tRTW_INFO(\"word_en=%x\\n\", word_en);\n\n\t\t\tfor (i = 0; i < PGPKT_DATA_SIZE; i++)\n\t\t\t\tRTW_INFO(\"data=%x \\t\", newdata[i]);\n\t\t\tif (ret == _FAIL)\n\t\t\t\tbreak;\n\t\t}\n\n\t\toffset++;\n\t}\n\n\t/*Efuse_PowerSwitch(padapter, _TRUE, _FALSE);*/\n\n\tefuse_PostUpdateAction(padapter, backupRegs);\n\nexit:\n\n\trtw_mfree(map, mapLen);\n\trtw_mfree(efuse, mapLen);\n\n\treturn ret;\n}\n\n\nu8 rtw_BT_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)\n{\n#define RT_ASSERT_RET(expr)\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif (!(expr)) {\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tprintk(\"Assertion failed! %s at ......\\n\", #expr);\t\t\t\t\t\t\t\\\n\t\tprintk(\"      ......%s,%s, line=%d\\n\",__FILE__, __FUNCTION__, __LINE__);\t\\\n\t\treturn _FAIL;\t\\\n\t}\n\n\tu8\toffset, word_en;\n\tu8\t*map;\n\tu8\tnewdata[PGPKT_DATA_SIZE];\n\ts32\ti = 0, j = 0, idx;\n\tu8\tret = _SUCCESS;\n\tu16\tmapLen = 0;\n\n\tEFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);\n\n\tif ((addr + cnts) > mapLen)\n\t\treturn _FAIL;\n\n\tRT_ASSERT_RET(PGPKT_DATA_SIZE == 8); /* have to be 8 byte alignment */\n\tRT_ASSERT_RET((mapLen & 0x7) == 0); /* have to be PGPKT_DATA_SIZE alignment for memcpy */\n\n\tmap = rtw_zmalloc(mapLen);\n\tif (map == NULL)\n\t\treturn _FAIL;\n\n\tret = rtw_BT_efuse_map_read(padapter, 0, mapLen, map);\n\tif (ret == _FAIL)\n\t\tgoto exit;\n\tRTW_INFO(\"OFFSET\\tVALUE(hex)\\n\");\n\tfor (i = 0; i < 1024; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */\n\t\tRTW_INFO(\"0x%03x\\t\", i);\n\t\tfor (j = 0; j < 8; j++)\n\t\t\tRTW_INFO(\"%02X \", map[i + j]);\n\t\tRTW_INFO(\"\\t\");\n\t\tfor (; j < 16; j++)\n\t\t\tRTW_INFO(\"%02X \", map[i + j]);\n\t\tRTW_INFO(\"\\n\");\n\t}\n\tRTW_INFO(\"\\n\");\n\tEfuse_PowerSwitch(padapter, _TRUE, _TRUE);\n\n\tidx = 0;\n\toffset = (addr >> 3);\n\twhile (idx < cnts) {\n\t\tword_en = 0xF;\n\t\tj = (addr + idx) & 0x7;\n\t\t_rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE);\n\t\tfor (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {\n\t\t\tif (data[idx] != map[addr + idx]) {\n\t\t\t\tword_en &= ~BIT(i >> 1);\n\t\t\t\tnewdata[i] = data[idx];\n\t\t\t}\n\t\t}\n\n\t\tif (word_en != 0xF) {\n\t\t\tRTW_INFO(\"offset=%x\\n\", offset);\n\t\t\tRTW_INFO(\"word_en=%x\\n\", word_en);\n\t\t\tRTW_INFO(\"%s: data=\", __FUNCTION__);\n\t\t\tfor (i = 0; i < PGPKT_DATA_SIZE; i++)\n\t\t\t\tRTW_INFO(\"0x%02X \", newdata[i]);\n\t\t\tRTW_INFO(\"\\n\");\n\t\t\tret = Efuse_PgPacketWrite_BT(padapter, offset, word_en, newdata, _FALSE);\n\t\t\tif (ret == _FAIL)\n\t\t\t\tbreak;\n\t\t}\n\n\t\toffset++;\n\t}\n\n\tEfuse_PowerSwitch(padapter, _TRUE, _FALSE);\n\nexit:\n\n\trtw_mfree(map, mapLen);\n\n\treturn ret;\n}\n\n/*-----------------------------------------------------------------------------\n * Function:\tEfuse_ReadAllMap\n *\n * Overview:\tRead All Efuse content\n *\n * Input:       NONE\n *\n * Output:      NONE\n *\n * Return:      NONE\n *\n * Revised History:\n * When\t\t\tWho\t\tRemark\n * 11/11/2008\tMHC\t\tCreate Version 0.\n *\n *---------------------------------------------------------------------------*/\nvoid\nEfuse_ReadAllMap(\n\t\t\tPADAPTER\tpAdapter,\n\t\t\tu8\t\tefuseType,\n\t\t\tu8\t\t*Efuse,\n\t\t\tBOOLEAN\t\tbPseudoTest);\nvoid\nEfuse_ReadAllMap(\n\t\t\tPADAPTER\tpAdapter,\n\t\t\tu8\t\tefuseType,\n\t\t\tu8\t\t*Efuse,\n\t\t\tBOOLEAN\t\tbPseudoTest)\n{\n\tu16\tmapLen = 0;\n\n\tEfuse_PowerSwitch(pAdapter, _FALSE, _TRUE);\n\n\tEFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, bPseudoTest);\n\n\tefuse_ReadEFuse(pAdapter, efuseType, 0, mapLen, Efuse, bPseudoTest);\n\n\tEfuse_PowerSwitch(pAdapter, _FALSE, _FALSE);\n}\n\n/*-----------------------------------------------------------------------------\n * Function:\tefuse_ShadowWrite1Byte\n *\t\t\tefuse_ShadowWrite2Byte\n *\t\t\tefuse_ShadowWrite4Byte\n *\n * Overview:\tWrite efuse modify map by one/two/four byte.\n *\n * Input:       NONE\n *\n * Output:      NONE\n *\n * Return:      NONE\n *\n * Revised History:\n * When\t\t\tWho\t\tRemark\n * 11/12/2008\tMHC\t\tCreate Version 0.\n *\n *---------------------------------------------------------------------------*/\n#ifdef PLATFORM\nstatic void\nefuse_ShadowWrite1Byte(\n\t\tPADAPTER\tpAdapter,\n\t\tu16\t\tOffset,\n\t\tu8\t\tValue);\n#endif /* PLATFORM */\nstatic void\nefuse_ShadowWrite1Byte(\n\t\tPADAPTER\tpAdapter,\n\t\tu16\t\tOffset,\n\t\tu8\t\tValue)\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);\n\n\tpHalData->efuse_eeprom_data[Offset] = Value;\n\n}\t/* efuse_ShadowWrite1Byte */\n\n/* ---------------Write Two Bytes */\nstatic void\nefuse_ShadowWrite2Byte(\n\t\tPADAPTER\tpAdapter,\n\t\tu16\t\tOffset,\n\t\tu16\t\tValue)\n{\n\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);\n\n\n\tpHalData->efuse_eeprom_data[Offset] = Value & 0x00FF;\n\tpHalData->efuse_eeprom_data[Offset + 1] = Value >> 8;\n\n}\t/* efuse_ShadowWrite1Byte */\n\n/* ---------------Write Four Bytes */\nstatic void\nefuse_ShadowWrite4Byte(\n\t\tPADAPTER\tpAdapter,\n\t\tu16\t\tOffset,\n\t\tu32\t\tValue)\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);\n\n\tpHalData->efuse_eeprom_data[Offset] = (u8)(Value & 0x000000FF);\n\tpHalData->efuse_eeprom_data[Offset + 1] = (u8)((Value >> 8) & 0x0000FF);\n\tpHalData->efuse_eeprom_data[Offset + 2] = (u8)((Value >> 16) & 0x00FF);\n\tpHalData->efuse_eeprom_data[Offset + 3] = (u8)((Value >> 24) & 0xFF);\n\n}\t/* efuse_ShadowWrite1Byte */\n\n\n/*-----------------------------------------------------------------------------\n * Function:\tEFUSE_ShadowWrite\n *\n * Overview:\tWrite efuse modify map for later update operation to use!!!!!\n *\n * Input:       NONE\n *\n * Output:      NONE\n *\n * Return:      NONE\n *\n * Revised History:\n * When\t\t\tWho\t\tRemark\n * 11/12/2008\tMHC\t\tCreate Version 0.\n *\n *---------------------------------------------------------------------------*/\nvoid\nEFUSE_ShadowWrite(\n\t\tPADAPTER\tpAdapter,\n\t\tu8\t\tType,\n\t\tu16\t\tOffset,\n\t\tu32\t\tValue);\nvoid\nEFUSE_ShadowWrite(\n\t\tPADAPTER\tpAdapter,\n\t\tu8\t\tType,\n\t\tu16\t\tOffset,\n\t\tu32\t\tValue)\n{\n#if (MP_DRIVER == 0)\n\treturn;\n#endif\n\tif (pAdapter->registrypriv.mp_mode == 0)\n\t\treturn;\n\n\n\tif (Type == 1)\n\t\tefuse_ShadowWrite1Byte(pAdapter, Offset, (u8)Value);\n\telse if (Type == 2)\n\t\tefuse_ShadowWrite2Byte(pAdapter, Offset, (u16)Value);\n\telse if (Type == 4)\n\t\tefuse_ShadowWrite4Byte(pAdapter, Offset, (u32)Value);\n\n}\t/* EFUSE_ShadowWrite */\n\n#endif /* !RTW_HALMAC */\n/*-----------------------------------------------------------------------------\n * Function:\tefuse_ShadowRead1Byte\n *\t\t\tefuse_ShadowRead2Byte\n *\t\t\tefuse_ShadowRead4Byte\n *\n * Overview:\tRead from efuse init map by one/two/four bytes !!!!!\n *\n * Input:       NONE\n *\n * Output:      NONE\n *\n * Return:      NONE\n *\n * Revised History:\n * When\t\t\tWho\t\tRemark\n * 11/12/2008\tMHC\t\tCreate Version 0.\n *\n *---------------------------------------------------------------------------*/\nstatic void\nefuse_ShadowRead1Byte(\n\t\tPADAPTER\tpAdapter,\n\t\tu16\t\tOffset,\n\t\tu8\t\t*Value)\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);\n\n\t*Value = pHalData->efuse_eeprom_data[Offset];\n\n}\t/* EFUSE_ShadowRead1Byte */\n\n/* ---------------Read Two Bytes */\nstatic void\nefuse_ShadowRead2Byte(\n\t\tPADAPTER\tpAdapter,\n\t\tu16\t\tOffset,\n\t\tu16\t\t*Value)\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);\n\n\t*Value = pHalData->efuse_eeprom_data[Offset];\n\t*Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8;\n\n}\t/* EFUSE_ShadowRead2Byte */\n\n/* ---------------Read Four Bytes */\nstatic void\nefuse_ShadowRead4Byte(\n\t\tPADAPTER\tpAdapter,\n\t\tu16\t\tOffset,\n\t\tu32\t\t*Value)\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);\n\n\t*Value = pHalData->efuse_eeprom_data[Offset];\n\t*Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8;\n\t*Value |= pHalData->efuse_eeprom_data[Offset + 2] << 16;\n\t*Value |= pHalData->efuse_eeprom_data[Offset + 3] << 24;\n\n}\t/* efuse_ShadowRead4Byte */\n\n/*-----------------------------------------------------------------------------\n * Function:\tEFUSE_ShadowRead\n *\n * Overview:\tRead from pHalData->efuse_eeprom_data\n *---------------------------------------------------------------------------*/\nvoid\nEFUSE_ShadowRead(\n\t\t\tPADAPTER\tpAdapter,\n\t\t\tu8\t\tType,\n\t\t\tu16\t\tOffset,\n\t\t\tu32\t\t*Value)\n{\n\tif (Type == 1)\n\t\tefuse_ShadowRead1Byte(pAdapter, Offset, (u8 *)Value);\n\telse if (Type == 2)\n\t\tefuse_ShadowRead2Byte(pAdapter, Offset, (u16 *)Value);\n\telse if (Type == 4)\n\t\tefuse_ShadowRead4Byte(pAdapter, Offset, (u32 *)Value);\n\n}\t/* EFUSE_ShadowRead */\n\n/*  11/16/2008 MH Add description. Get current efuse area enabled word!!. */\nu8\nEfuse_CalculateWordCnts(u8\tword_en)\n{\n\tu8 word_cnts = 0;\n\tif (!(word_en & BIT(0)))\n\t\tword_cnts++; /* 0 : write enable */\n\tif (!(word_en & BIT(1)))\n\t\tword_cnts++;\n\tif (!(word_en & BIT(2)))\n\t\tword_cnts++;\n\tif (!(word_en & BIT(3)))\n\t\tword_cnts++;\n\treturn word_cnts;\n}\n\n/*-----------------------------------------------------------------------------\n * Function:\tefuse_WordEnableDataRead\n *\n * Overview:\tRead allowed word in current efuse section data.\n *\n * Input:       NONE\n *\n * Output:      NONE\n *\n * Return:      NONE\n *\n * Revised History:\n * When\t\t\tWho\t\tRemark\n * 11/16/2008\tMHC\t\tCreate Version 0.\n * 11/21/2008\tMHC\t\tFix Write bug when we only enable late word.\n *\n *---------------------------------------------------------------------------*/\nvoid\nefuse_WordEnableDataRead(u8\tword_en,\n\t\t\t\tu8\t*sourdata,\n\t\t\t\tu8\t*targetdata)\n{\n\tif (!(word_en & BIT(0))) {\n\t\ttargetdata[0] = sourdata[0];\n\t\ttargetdata[1] = sourdata[1];\n\t}\n\tif (!(word_en & BIT(1))) {\n\t\ttargetdata[2] = sourdata[2];\n\t\ttargetdata[3] = sourdata[3];\n\t}\n\tif (!(word_en & BIT(2))) {\n\t\ttargetdata[4] = sourdata[4];\n\t\ttargetdata[5] = sourdata[5];\n\t}\n\tif (!(word_en & BIT(3))) {\n\t\ttargetdata[6] = sourdata[6];\n\t\ttargetdata[7] = sourdata[7];\n\t}\n}\n\n/*-----------------------------------------------------------------------------\n * Function:\tEFUSE_ShadowMapUpdate\n *\n * Overview:\tTransfer current EFUSE content to shadow init and modify map.\n *\n * Input:       NONE\n *\n * Output:      NONE\n *\n * Return:      NONE\n *\n * Revised History:\n * When\t\t\tWho\t\tRemark\n * 11/13/2008\tMHC\t\tCreate Version 0.\n *\n *---------------------------------------------------------------------------*/\nvoid EFUSE_ShadowMapUpdate(\n\tPADAPTER\tpAdapter,\n\tu8\t\tefuseType,\n\tBOOLEAN\tbPseudoTest)\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);\n\tu16\tmapLen = 0;\n#ifdef RTW_HALMAC\n\tu8 *efuse_map = NULL;\n\tint err;\n\n\n\tmapLen = EEPROM_MAX_SIZE;\n\tefuse_map = pHalData->efuse_eeprom_data;\n\t/* efuse default content is 0xFF */\n\t_rtw_memset(efuse_map, 0xFF, EEPROM_MAX_SIZE);\n\n\tEFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, bPseudoTest);\n\tif (!mapLen) {\n\t\tRTW_WARN(\"%s: <ERROR> fail to get efuse size!\\n\", __FUNCTION__);\n\t\tmapLen = EEPROM_MAX_SIZE;\n\t}\n\tif (mapLen > EEPROM_MAX_SIZE) {\n\t\tRTW_WARN(\"%s: <ERROR> size of efuse data(%d) is large than expected(%d)!\\n\",\n\t\t\t __FUNCTION__, mapLen, EEPROM_MAX_SIZE);\n\t\tmapLen = EEPROM_MAX_SIZE;\n\t}\n\n\tif (pHalData->bautoload_fail_flag == _FALSE) {\n\t\terr = rtw_halmac_read_logical_efuse_map(adapter_to_dvobj(pAdapter), efuse_map, mapLen, NULL, 0);\n\t\tif (err)\n\t\t\tRTW_ERR(\"%s: <ERROR> fail to get efuse map!\\n\", __FUNCTION__);\n\t}\n#else /* !RTW_HALMAC */\n\tEFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, bPseudoTest);\n\n\tif (pHalData->bautoload_fail_flag == _TRUE)\n\t\t_rtw_memset(pHalData->efuse_eeprom_data, 0xFF, mapLen);\n\telse {\n#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE\n\t\tif (_SUCCESS != retriveAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pHalData->efuse_eeprom_data)) {\n#endif\n\n\t\t\tEfuse_ReadAllMap(pAdapter, efuseType, pHalData->efuse_eeprom_data, bPseudoTest);\n\n#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE\n\t\t\tstoreAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pHalData->efuse_eeprom_data);\n\t\t}\n#endif\n\t}\n\n\t/* PlatformMoveMemory((void *)&pHalData->EfuseMap[EFUSE_MODIFY_MAP][0], */\n\t/* (void *)&pHalData->EfuseMap[EFUSE_INIT_MAP][0], mapLen); */\n#endif /* !RTW_HALMAC */\n\n\trtw_mask_map_read(pAdapter, 0x00, mapLen, pHalData->efuse_eeprom_data);\n\n\trtw_dump_cur_efuse(pAdapter);\n} /* EFUSE_ShadowMapUpdate */\n\nconst u8 _mac_hidden_max_bw_to_hal_bw_cap[MAC_HIDDEN_MAX_BW_NUM] = {\n\t0,\n\t0,\n\t(BW_CAP_160M | BW_CAP_80M | BW_CAP_40M | BW_CAP_20M | BW_CAP_10M | BW_CAP_5M),\n\t(BW_CAP_5M),\n\t(BW_CAP_10M | BW_CAP_5M),\n\t(BW_CAP_20M | BW_CAP_10M | BW_CAP_5M),\n\t(BW_CAP_40M | BW_CAP_20M | BW_CAP_10M | BW_CAP_5M),\n\t(BW_CAP_80M | BW_CAP_40M | BW_CAP_20M | BW_CAP_10M | BW_CAP_5M),\n};\n\nconst u8 _mac_hidden_proto_to_hal_proto_cap[MAC_HIDDEN_PROTOCOL_NUM] = {\n\t0,\n\t0,\n\t(PROTO_CAP_11N | PROTO_CAP_11G | PROTO_CAP_11B),\n\t(PROTO_CAP_11AC | PROTO_CAP_11N | PROTO_CAP_11G | PROTO_CAP_11B),\n};\n\nu8 mac_hidden_wl_func_to_hal_wl_func(u8 func)\n{\n\tu8 wl_func = 0;\n\n\tif (func & BIT0)\n\t\twl_func |= WL_FUNC_MIRACAST;\n\tif (func & BIT1)\n\t\twl_func |= WL_FUNC_P2P;\n\tif (func & BIT2)\n\t\twl_func |= WL_FUNC_TDLS;\n\tif (func & BIT3)\n\t\twl_func |= WL_FUNC_FTM;\n\n\treturn wl_func;\n}\n\n#ifdef PLATFORM_LINUX\n#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE\n/* #include <rtw_eeprom.h> */\n\nint isAdaptorInfoFileValid(void)\n{\n\treturn _TRUE;\n}\n\nint storeAdaptorInfoFile(char *path, u8 *efuse_data)\n{\n\tint ret = _SUCCESS;\n\n\tif (path && efuse_data) {\n\t\tret = rtw_store_to_file(path, efuse_data, EEPROM_MAX_SIZE_512);\n\t\tif (ret == EEPROM_MAX_SIZE)\n\t\t\tret = _SUCCESS;\n\t\telse\n\t\t\tret = _FAIL;\n\t} else {\n\t\tRTW_INFO(\"%s NULL pointer\\n\", __FUNCTION__);\n\t\tret =  _FAIL;\n\t}\n\treturn ret;\n}\n\nint retriveAdaptorInfoFile(char *path, u8 *efuse_data)\n{\n\tint ret = _SUCCESS;\n\tmm_segment_t oldfs;\n\tstruct file *fp;\n\n\tif (path && efuse_data) {\n\n\t\tret = rtw_retrieve_from_file(path, efuse_data, EEPROM_MAX_SIZE);\n\n\t\tif (ret == EEPROM_MAX_SIZE)\n\t\t\tret = _SUCCESS;\n\t\telse\n\t\t\tret = _FAIL;\n\n#if 0\n\t\tif (isAdaptorInfoFileValid())\n\t\t\treturn 0;\n\t\telse\n\t\t\treturn _FAIL;\n#endif\n\n\t} else {\n\t\tRTW_INFO(\"%s NULL pointer\\n\", __FUNCTION__);\n\t\tret = _FAIL;\n\t}\n\treturn ret;\n}\n#endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */\n\nu8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepatch, u8 *buf, u32 len)\n{\n\tchar *ptmpbuf = NULL, *ptr;\n\tu8 val8;\n\tu32 count, i, j;\n\tint err;\n\tu32 bufsize = 4096;\n\n\tptmpbuf = rtw_zmalloc(bufsize);\n\tif (ptmpbuf == NULL)\n\t\treturn _FALSE;\n\n\tcount = rtw_retrieve_from_file(filepatch, ptmpbuf, bufsize);\n\tif (count <= 90) {\n\t\trtw_mfree(ptmpbuf, bufsize);\n\t\tRTW_ERR(\"%s, filepatch %s, size=%d, FAIL!!\\n\", __FUNCTION__, filepatch, count);\n\t\treturn _FALSE;\n\t}\n\n\ti = 0;\n\tj = 0;\n\tptr = ptmpbuf;\n\twhile ((j < len) && (i < count)) {\n\t\tif (ptmpbuf[i] == '\\0')\n\t\t\tbreak;\n\n\t\tptr = strpbrk(&ptmpbuf[i], \" \\t\\n\\r\");\n\t\tif (ptr) {\n\t\t\tif (ptr == &ptmpbuf[i]) {\n\t\t\t\ti++;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\t/* Add string terminating null */\n\t\t\t*ptr = 0;\n\t\t} else {\n\t\t\tptr = &ptmpbuf[count-1];\n\t\t}\n\n\t\terr = sscanf(&ptmpbuf[i], \"%hhx\", &val8);\n\t\tif (err != 1) {\n\t\t\tRTW_WARN(\"Something wrong to parse efuse file, string=%s\\n\", &ptmpbuf[i]);\n\t\t} else {\n\t\t\tbuf[j] = val8;\n\t\t\tRTW_DBG(\"i=%d, j=%d, 0x%02x\\n\", i, j, buf[j]);\n\t\t\tj++;\n\t\t}\n\n\t\ti = ptr - ptmpbuf + 1;\n\t}\n\n\trtw_mfree(ptmpbuf, bufsize);\n\tRTW_INFO(\"%s, filepatch %s, size=%d, done\\n\", __FUNCTION__, filepatch, count);\n\treturn _TRUE;\n}\n\n#ifdef CONFIG_EFUSE_CONFIG_FILE\nu32 rtw_read_efuse_from_file(const char *path, u8 *buf, int map_size)\n{\n\tu32 i;\n\tu8 c;\n\tu8 temp[3];\n\tu8 temp_i;\n\tu8 end = _FALSE;\n\tu32 ret = _FAIL;\n\n\tu8 *file_data = NULL;\n\tu32 file_size, read_size, pos = 0;\n\tu8 *map = NULL;\n\n\tif (rtw_is_file_readable_with_size(path, &file_size) != _TRUE) {\n\t\tRTW_PRINT(\"%s %s is not readable\\n\", __func__, path);\n\t\tgoto exit;\n\t}\n\n\tfile_data = rtw_vmalloc(file_size);\n\tif (!file_data) {\n\t\tRTW_ERR(\"%s rtw_vmalloc(%d) fail\\n\", __func__, file_size);\n\t\tgoto exit;\n\t}\n\n\tread_size = rtw_retrieve_from_file(path, file_data, file_size);\n\tif (read_size == 0) {\n\t\tRTW_ERR(\"%s read from %s fail\\n\", __func__, path);\n\t\tgoto exit;\n\t}\n\n\tmap = rtw_vmalloc(map_size);\n\tif (!map) {\n\t\tRTW_ERR(\"%s rtw_vmalloc(%d) fail\\n\", __func__, map_size);\n\t\tgoto exit;\n\t}\n\t_rtw_memset(map, 0xff, map_size);\n\n\ttemp[2] = 0; /* end of string '\\0' */\n\n\tfor (i = 0 ; i < map_size ; i++) {\n\t\ttemp_i = 0;\n\n\t\twhile (1) {\n\t\t\tif (pos >= read_size) {\n\t\t\t\tend = _TRUE;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tc = file_data[pos++];\n\n\t\t\t/* bypass spece or eol or null before first hex digit */\n\t\t\tif (temp_i == 0 && (is_eol(c) == _TRUE || is_space(c) == _TRUE || is_null(c) == _TRUE))\n\t\t\t\tcontinue;\n\n\t\t\tif (IsHexDigit(c) == _FALSE) {\n\t\t\t\tRTW_ERR(\"%s invalid 8-bit hex format for offset:0x%03x\\n\", __func__, i);\n\t\t\t\tgoto exit;\n\t\t\t}\n\n\t\t\ttemp[temp_i++] = c;\n\n\t\t\tif (temp_i == 2) {\n\t\t\t\t/* parse value */\n\t\t\t\tif (sscanf(temp, \"%hhx\", &map[i]) != 1) {\n\t\t\t\t\tRTW_ERR(\"%s sscanf fail for offset:0x%03x\\n\", __func__, i);\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tif (end == _TRUE) {\n\t\t\tif (temp_i != 0) {\n\t\t\t\tRTW_ERR(\"%s incomplete 8-bit hex format for offset:0x%03x\\n\", __func__, i);\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tRTW_PRINT(\"efuse file:%s, 0x%03x byte content read\\n\", path, i);\n\n\t_rtw_memcpy(buf, map, map_size);\n\n\tret = _SUCCESS;\n\nexit:\n\tif (file_data)\n\t\trtw_vmfree(file_data, file_size);\n\tif (map)\n\t\trtw_vmfree(map, map_size);\n\n\treturn ret;\n}\n\nu32 rtw_read_macaddr_from_file(const char *path, u8 *buf)\n{\n\tu32 i;\n\tu8 temp[3];\n\tu32 ret = _FAIL;\n\n\tu8 file_data[17];\n\tu32 read_size, pos = 0;\n\tu8 addr[ETH_ALEN];\n\n\tif (rtw_is_file_readable(path) != _TRUE) {\n\t\tRTW_PRINT(\"%s %s is not readable\\n\", __func__, path);\n\t\tgoto exit;\n\t}\n\n\tread_size = rtw_retrieve_from_file(path, file_data, 17);\n\tif (read_size != 17) {\n\t\tRTW_ERR(\"%s read from %s fail\\n\", __func__, path);\n\t\tgoto exit;\n\t}\n\n\ttemp[2] = 0; /* end of string '\\0' */\n\n\tfor (i = 0 ; i < ETH_ALEN ; i++) {\n\t\tif (IsHexDigit(file_data[i * 3]) == _FALSE || IsHexDigit(file_data[i * 3 + 1]) == _FALSE) {\n\t\t\tRTW_ERR(\"%s invalid 8-bit hex format for address offset:%u\\n\", __func__, i);\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (i < ETH_ALEN - 1 && file_data[i * 3 + 2] != ':') {\n\t\t\tRTW_ERR(\"%s invalid separator after address offset:%u\\n\", __func__, i);\n\t\t\tgoto exit;\n\t\t}\n\n\t\ttemp[0] = file_data[i * 3];\n\t\ttemp[1] = file_data[i * 3 + 1];\n\t\tif (sscanf(temp, \"%hhx\", &addr[i]) != 1) {\n\t\t\tRTW_ERR(\"%s sscanf fail for address offset:0x%03x\\n\", __func__, i);\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\t_rtw_memcpy(buf, addr, ETH_ALEN);\n\n\tRTW_PRINT(\"wifi_mac file: %s\\n\", path);\n#ifdef CONFIG_RTW_DEBUG\n\tRTW_INFO(MAC_FMT\"\\n\", MAC_ARG(buf));\n#endif\n\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n#endif /* CONFIG_EFUSE_CONFIG_FILE */\n\n#endif /* PLATFORM_LINUX */\n"
  },
  {
    "path": "core/mesh/rtw_mesh.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_MESH_C_\n\n#ifdef CONFIG_RTW_MESH\n#include <drv_types.h>\n\nconst char *_rtw_mesh_plink_str[] = {\n\t\"UNKNOWN\",\n\t\"LISTEN\",\n\t\"OPN_SNT\",\n\t\"OPN_RCVD\",\n\t\"CNF_RCVD\",\n\t\"ESTAB\",\n\t\"HOLDING\",\n\t\"BLOCKED\",\n};\n\nconst char *_rtw_mesh_ps_str[] = {\n\t\"UNKNOWN\",\n\t\"ACTIVE\",\n\t\"LSLEEP\",\n\t\"DSLEEP\",\n};\n\nconst char *_action_self_protected_str[] = {\n\t\"ACT_SELF_PROTECTED_RSVD\",\n\t\"MESH_OPEN\",\n\t\"MESH_CONF\",\n\t\"MESH_CLOSE\",\n\t\"MESH_GK_INFORM\",\n\t\"MESH_GK_ACK\",\n};\n\ninline u8 *rtw_set_ie_mesh_id(u8 *buf, u32 *buf_len, const char *mesh_id, u8 id_len)\n{\n\treturn rtw_set_ie(buf, WLAN_EID_MESH_ID, id_len, mesh_id, buf_len);\n}\n\ninline u8 *rtw_set_ie_mesh_config(u8 *buf, u32 *buf_len\n\t, u8 path_sel_proto, u8 path_sel_metric, u8 congest_ctl_mode, u8 sync_method, u8 auth_proto\n\t, u8 num_of_peerings, bool cto_mgate, bool cto_as\n\t, bool accept_peerings, bool mcca_sup, bool mcca_en, bool forwarding\n\t, bool mbca_en, bool tbtt_adj, bool ps_level)\n{\n\n\tu8 conf[7] = {0};\n\n\tSET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(conf, path_sel_proto);\n\tSET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(conf, path_sel_metric);\n\tSET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(conf, congest_ctl_mode);\n\tSET_MESH_CONF_ELE_SYNC_METHOD_ID(conf, sync_method);\n\tSET_MESH_CONF_ELE_AUTH_PROTO_ID(conf, auth_proto);\n\n\tSET_MESH_CONF_ELE_CTO_MGATE(conf, cto_mgate);\n\tSET_MESH_CONF_ELE_NUM_OF_PEERINGS(conf, num_of_peerings);\n\tSET_MESH_CONF_ELE_CTO_AS(conf, cto_as);\n\n\tSET_MESH_CONF_ELE_ACCEPT_PEERINGS(conf, accept_peerings);\n\tSET_MESH_CONF_ELE_MCCA_SUP(conf, mcca_sup);\n\tSET_MESH_CONF_ELE_MCCA_EN(conf, mcca_en);\n\tSET_MESH_CONF_ELE_FORWARDING(conf, forwarding);\n\tSET_MESH_CONF_ELE_MBCA_EN(conf, mbca_en);\n\tSET_MESH_CONF_ELE_TBTT_ADJ(conf, tbtt_adj);\n\tSET_MESH_CONF_ELE_PS_LEVEL(conf, ps_level);\n\n\treturn rtw_set_ie(buf, WLAN_EID_MESH_CONFIG, 7, conf, buf_len);\n}\n\ninline u8 *rtw_set_ie_mpm(u8 *buf, u32 *buf_len\n\t, u8 proto_id, u16 llid, u16 *plid, u16 *reason, u8 *chosen_pmk)\n{\n\tu8 data[24] = {0};\n\tu8 *pos = data;\n\n\tRTW_PUT_LE16(pos, proto_id);\n\tpos += 2;\n\n\tRTW_PUT_LE16(pos, llid);\n\tpos += 2;\n\n\tif (plid) {\n\t\tRTW_PUT_LE16(pos, *plid);\n\t\tpos += 2;\n\t}\n\n\tif (reason) {\n\t\tRTW_PUT_LE16(pos, *reason);\n\t\tpos += 2;\n\t}\n\n\tif (chosen_pmk) {\n\t\t_rtw_memcpy(pos, chosen_pmk, 16);\n\t\tpos += 16;\n\t}\n\n\treturn rtw_set_ie(buf, WLAN_EID_MPM, pos - data, data, buf_len);\n}\n\nbool rtw_bss_is_forwarding(WLAN_BSSID_EX *bss)\n{\n\tu8 *ie;\n\tint ie_len;\n\tbool ret = 0;\n\n\tie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,\n\t\t\tBSS_EX_TLV_IES_LEN(bss));\n\tif (!ie || ie_len != 7)\n\t\tgoto exit;\n\n\tret = GET_MESH_CONF_ELE_FORWARDING(ie + 2);\n\nexit:\n\treturn ret;\n}\n\nbool rtw_bss_is_cto_mgate(WLAN_BSSID_EX *bss)\n{\n\tu8 *ie;\n\tint ie_len;\n\tbool ret = 0;\n\n\tie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,\n\t\t\tBSS_EX_TLV_IES_LEN(bss));\n\tif (!ie || ie_len != 7)\n\t\tgoto exit;\n\n\tret = GET_MESH_CONF_ELE_CTO_MGATE(ie + 2);\n\nexit:\n\treturn ret;\n}\n\nint rtw_bss_is_same_mbss(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b)\n{\n\tint ret = 0;\n\tu8 *a_mconf_ie, *b_mconf_ie;\n\tsint a_mconf_ie_len, b_mconf_ie_len;\n\n\tif (a->InfrastructureMode != Ndis802_11_mesh)\n\t\tgoto exit;\n\ta_mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(a), WLAN_EID_MESH_CONFIG, &a_mconf_ie_len, BSS_EX_TLV_IES_LEN(a));\n\tif (!a_mconf_ie || a_mconf_ie_len != 7)\n\t\tgoto exit;\n\tif (b->InfrastructureMode != Ndis802_11_mesh)\n\t\tgoto exit;\n\tb_mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(b), WLAN_EID_MESH_CONFIG, &b_mconf_ie_len, BSS_EX_TLV_IES_LEN(b));\n\tif (!b_mconf_ie || b_mconf_ie_len != 7)\n\t\tgoto exit;\n\n\tif (a->mesh_id.SsidLength != b->mesh_id.SsidLength\n\t\t|| _rtw_memcmp(a->mesh_id.Ssid, b->mesh_id.Ssid, a->mesh_id.SsidLength) == _FALSE)\n\t\tgoto exit;\n\n\tif (_rtw_memcmp(a_mconf_ie + 2, b_mconf_ie + 2, 5) == _FALSE)\n\t\tgoto exit;\n\n\tret = 1;\n\nexit:\n\treturn ret;\n}\n\nint rtw_bss_is_candidate_mesh_peer(WLAN_BSSID_EX *self, WLAN_BSSID_EX *target, u8 ch, u8 add_peer)\n{\n\tint ret = 0;\n\tu8 *mconf_ie;\n\tsint mconf_ie_len;\n\tint i, j;\n\n\tif (!rtw_bss_is_same_mbss(self, target))\n\t\tgoto exit;\n\n\tif (ch && self->Configuration.DSConfig != target->Configuration.DSConfig)\n\t\tgoto exit;\n\n\tif (add_peer) {\n\t\t/* Accept additional mesh peerings */\n\t\tmconf_ie = rtw_get_ie(BSS_EX_TLV_IES(target), WLAN_EID_MESH_CONFIG, &mconf_ie_len, BSS_EX_TLV_IES_LEN(target));\n\t\tif (!mconf_ie || mconf_ie_len != 7)\n\t\t\tgoto exit;\n\t\tif (GET_MESH_CONF_ELE_ACCEPT_PEERINGS(mconf_ie + 2) == 0)\n\t\t\tgoto exit;\n\t}\n\n\t/* BSSBasicRateSet */\n\tfor (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {\n\t\tif (target->SupportedRates[i] == 0)\n\t\t\tbreak;\t\n\t\tif (target->SupportedRates[i] & 0x80) {\n\t\t\tu8 match = 0;\n\n\t\t\tif (!ch) {\n\t\t\t\t/* off-channel, check target with our hardcode capability */\n\t\t\t\tif (target->Configuration.DSConfig > 14)\n\t\t\t\t\tmatch = rtw_is_basic_rate_ofdm(target->SupportedRates[i]);\n\t\t\t\telse\n\t\t\t\t\tmatch = rtw_is_basic_rate_mix(target->SupportedRates[i]);\n\t\t\t} else { \n\t\t\t\tfor (j = 0; j < NDIS_802_11_LENGTH_RATES_EX; j++) {\n\t\t\t\t\tif (self->SupportedRates[j] == 0)\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tif (self->SupportedRates[j] == target->SupportedRates[i]) {\n\t\t\t\t\t\tmatch = 1;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (!match)\n\t\t\t\tgoto exit;\n\t\t}\n\t}\n\n\n\t/* BSSBasicMCSSet */\n\n\t/* 802.1X connected to AS ? */\n\n\tret = 1;\n\nexit:\n\treturn ret;\n}\n\nvoid rtw_mesh_bss_peering_status(WLAN_BSSID_EX *bss, u8 *nop, u8 *accept)\n{\n\tu8 *ie;\n\tint ie_len;\n\n\tif (nop)\n\t\t*nop = 0;\n\tif (accept)\n\t\t*accept = 0;\n\n\tie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,\n\t\t\tBSS_EX_TLV_IES_LEN(bss));\n\tif (!ie || ie_len != 7)\n\t\tgoto exit;\n\n\tif (nop)\n\t\t*nop = GET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2);\n\tif (accept)\n\t\t*accept = GET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2);\n\nexit:\n\treturn;\n}\n\n#if CONFIG_RTW_MESH_ACNODE_PREVENT\nvoid rtw_mesh_update_scanned_acnode_status(_adapter *adapter, struct wlan_network *scanned)\n{\n\tbool acnode;\n\tu8 nop, accept;\n\n\trtw_mesh_bss_peering_status(&scanned->network, &nop, &accept);\n\n\tacnode = !nop && accept;\n\n\tif (acnode && scanned->acnode_stime == 0) {\n\t\tscanned->acnode_stime = rtw_get_current_time();\n\t\tif (scanned->acnode_stime == 0)\n\t\t\tscanned->acnode_stime++;\n\t} else if (!acnode) {\n\t\tscanned->acnode_stime = 0;\n\t\tscanned->acnode_notify_etime = 0;\n\t}\n}\n\nbool rtw_mesh_scanned_is_acnode_confirmed(_adapter *adapter, struct wlan_network *scanned)\n{\n\treturn scanned->acnode_stime\n\t\t\t&& rtw_get_passing_time_ms(scanned->acnode_stime)\n\t\t\t\t> adapter->mesh_cfg.peer_sel_policy.acnode_conf_timeout_ms;\n}\n\nstatic bool rtw_mesh_scanned_is_acnode_allow_notify(_adapter *adapter, struct wlan_network *scanned)\n{\n\treturn scanned->acnode_notify_etime\n\t\t\t&& rtw_time_after(scanned->acnode_notify_etime, rtw_get_current_time());\n}\n\nbool rtw_mesh_acnode_prevent_allow_sacrifice(_adapter *adapter)\n{\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tbool allow = 0;\n\n\tif (!mcfg->peer_sel_policy.acnode_prevent\n\t\t|| mcfg->max_peer_links <= 1\n\t\t|| stapriv->asoc_list_cnt < mcfg->max_peer_links)\n\t\tgoto exit;\n\n#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\tif (rtw_mesh_cto_mgate_required(adapter))\n\t\tgoto exit;\n#endif\n\n\tallow = 1;\n\nexit:\n\treturn allow;\n}\n\nstatic bool rtw_mesh_acnode_candidate_exist(_adapter *adapter)\n{\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\t_queue *queue = &(mlme->scanned_queue);\n\t_list *head, *list;\n\t_irqL irqL;\n\tstruct wlan_network *scanned = NULL;\n\tstruct sta_info *sta = NULL;\n\tbool need = 0;\n\n\t_enter_critical_bh(&(mlme->scanned_queue.lock), &irqL);\n\n\thead = get_list_head(queue);\n\tlist = get_next(head);\n\twhile (!rtw_end_of_queue_search(head, list)) {\n\t\tscanned = LIST_CONTAINOR(list, struct wlan_network, list);\n\t\tlist = get_next(list);\n\n\t\tif (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms\n\t\t\t&& rtw_mesh_scanned_is_acnode_confirmed(adapter, scanned)\n\t\t\t&& (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi)\n\t\t\t#if CONFIG_RTW_MACADDR_ACL\n\t\t\t&& rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE\n\t\t\t#endif\n\t\t\t&& rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 1, 1)\n\t\t\t#if CONFIG_RTW_MESH_PEER_BLACKLIST\n\t\t\t&& !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)\n\t\t\t#endif\n\t\t\t#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\t\t\t&& rtw_mesh_cto_mgate_network_filter(adapter, scanned)\n\t\t\t#endif\n\t\t) {\n\t\t\tneed = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t_exit_critical_bh(&(mlme->scanned_queue.lock), &irqL);\n\n\treturn need;\n}\n\nstatic int rtw_mesh_acnode_prevent_sacrifice_chk(_adapter *adapter, struct sta_info **sac, struct sta_info *com)\n{\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tint updated = 0;\n\n\t/*\n\t* TODO: compare next_hop reference cnt of forwarding info\n\t* don't sacrifice working next_hop or choose sta with least cnt\n\t*/\n\n\tif (*sac == NULL) {\n\t\tupdated = 1;\n\t\tgoto exit;\n\t}\n\n#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\tif (mcfg->peer_sel_policy.cto_mgate_require\n\t\t&& !mcfg->dot11MeshGateAnnouncementProtocol\n\t) {\n\t\tif (IS_CTO_MGATE_CONF_TIMEOUT(com->plink)) {\n\t\t\tif (!IS_CTO_MGATE_CONF_TIMEOUT((*sac)->plink)) {\n\t\t\t\t/* blacklist > not blacklist */\n\t\t\t\tupdated = 1;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t} else if (!IS_CTO_MGATE_CONF_DISABLED(com->plink)) {\n\t\t\tif (IS_CTO_MGATE_CONF_DISABLED((*sac)->plink)) {\n\t\t\t\t/* confirming > disabled */\n\t\t\t\tupdated = 1;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\t}\n#endif\n\nexit:\n\tif (updated)\n\t\t*sac = com;\n\n\treturn updated;\n}\n\nstruct sta_info *_rtw_mesh_acnode_prevent_pick_sacrifice(_adapter *adapter)\n{\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\t_list *head, *list;\n\tstruct sta_info *sta, *sacrifice = NULL;\n\tu8 nop;\n\n\thead = &stapriv->asoc_list;\n\tlist = get_next(head);\n\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\tsta = LIST_CONTAINOR(list, struct sta_info, asoc_list);\n\t\tlist = get_next(list);\n\n\t\tif (!sta->plink || !sta->plink->scanned) {\n\t\t\trtw_warn_on(1);\n\t\t\tcontinue;\n\t\t}\n\n\t\trtw_mesh_bss_peering_status(&sta->plink->scanned->network, &nop, NULL);\n\t\tif (nop < 2)\n\t\t\tcontinue;\n\n\t\trtw_mesh_acnode_prevent_sacrifice_chk(adapter, &sacrifice, sta);\n\t}\n\n\treturn sacrifice;\n}\n\nstruct sta_info *rtw_mesh_acnode_prevent_pick_sacrifice(_adapter *adapter)\n{\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct sta_info *sacrifice = NULL;\n\n\tenter_critical_bh(&stapriv->asoc_list_lock);\n\n\tsacrifice = _rtw_mesh_acnode_prevent_pick_sacrifice(adapter);\n\n\texit_critical_bh(&stapriv->asoc_list_lock);\n\n\treturn sacrifice;\n}\n\nstatic void rtw_mesh_acnode_rsvd_chk(_adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tu8 acnode_rsvd = 0;\n\n\tif (rtw_mesh_acnode_prevent_allow_sacrifice(adapter)\n\t\t&& rtw_mesh_acnode_prevent_pick_sacrifice(adapter)\n\t\t&& rtw_mesh_acnode_candidate_exist(adapter))\n\t\tacnode_rsvd = 1;\n\n\tif (plink_ctl->acnode_rsvd != acnode_rsvd) {\n\t\tplink_ctl->acnode_rsvd = acnode_rsvd;\n\t\tRTW_INFO(FUNC_ADPT_FMT\" acnode_rsvd = %d\\n\", FUNC_ADPT_ARG(adapter), plink_ctl->acnode_rsvd);\n\t\tupdate_beacon(adapter, WLAN_EID_MESH_CONFIG, NULL, 1, 0);\n\t}\n}\n\nstatic void rtw_mesh_acnode_set_notify_etime(_adapter *adapter, u8 *rframe_whdr)\n{\n\tif (adapter->mesh_info.plink_ctl.acnode_rsvd) {\n\t\tstruct wlan_network *scanned = rtw_find_network(&adapter->mlmepriv.scanned_queue, get_addr2_ptr(rframe_whdr));\n\n\t\tif (rtw_mesh_scanned_is_acnode_confirmed(adapter, scanned)) {\n\t\t\tscanned->acnode_notify_etime = rtw_get_current_time()\n\t\t\t\t+ rtw_ms_to_systime(adapter->mesh_cfg.peer_sel_policy.acnode_notify_timeout_ms);\n\t\t\tif (scanned->acnode_notify_etime == 0)\n\t\t\t\tscanned->acnode_notify_etime++;\n\t\t}\n\t}\n}\n\nvoid dump_mesh_acnode_prevent_settings(void *sel, _adapter *adapter)\n{\n\tstruct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;\n\n\tRTW_PRINT_SEL(sel, \"%-6s %-12s %-14s\\n\"\n\t\t, \"enable\", \"conf_timeout\", \"nofity_timeout\");\n\tRTW_PRINT_SEL(sel, \"%6u %12u %14u\\n\"\n\t\t, peer_sel_policy->acnode_prevent\n\t\t, peer_sel_policy->acnode_conf_timeout_ms\n\t\t, peer_sel_policy->acnode_notify_timeout_ms);\n}\n#endif /* CONFIG_RTW_MESH_ACNODE_PREVENT */\n\n#if CONFIG_RTW_MESH_PEER_BLACKLIST\nint rtw_mesh_peer_blacklist_add(_adapter *adapter, const u8 *addr)\n{\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\n\treturn rtw_blacklist_add(&plink_ctl->peer_blacklist, addr\n\t\t, mcfg->peer_sel_policy.peer_blacklist_timeout_ms);\n}\n\nint rtw_mesh_peer_blacklist_del(_adapter *adapter, const u8 *addr)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\n\treturn rtw_blacklist_del(&plink_ctl->peer_blacklist, addr);\n}\n\nint rtw_mesh_peer_blacklist_search(_adapter *adapter, const u8 *addr)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\n\treturn rtw_blacklist_search(&plink_ctl->peer_blacklist, addr);\n}\n\nvoid rtw_mesh_peer_blacklist_flush(_adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\n\trtw_blacklist_flush(&plink_ctl->peer_blacklist);\n}\n\nvoid dump_mesh_peer_blacklist(void *sel, _adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\n\tdump_blacklist(sel, &plink_ctl->peer_blacklist, \"blacklist\");\n}\n\nvoid dump_mesh_peer_blacklist_settings(void *sel, _adapter *adapter)\n{\n\tstruct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;\n\n\tRTW_PRINT_SEL(sel, \"%-12s %-17s\\n\"\n\t\t, \"conf_timeout\", \"blacklist_timeout\");\n\tRTW_PRINT_SEL(sel, \"%12u %17u\\n\"\n\t\t, peer_sel_policy->peer_conf_timeout_ms\n\t\t, peer_sel_policy->peer_blacklist_timeout_ms);\n}\n#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */\n\n#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\nu8 rtw_mesh_cto_mgate_required(_adapter *adapter)\n{\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\n\treturn mcfg->peer_sel_policy.cto_mgate_require\n\t\t&& !rtw_bss_is_cto_mgate(&(mlmeext->mlmext_info.network));\n}\n\nu8 rtw_mesh_cto_mgate_network_filter(_adapter *adapter, struct wlan_network *scanned)\n{\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\n\treturn !rtw_mesh_cto_mgate_required(adapter)\n\t\t\t|| (rtw_bss_is_cto_mgate(&scanned->network)\n\t\t\t\t&& !rtw_mesh_cto_mgate_blacklist_search(adapter, scanned->network.MacAddress));\n}\n\nint rtw_mesh_cto_mgate_blacklist_add(_adapter *adapter, const u8 *addr)\n{\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\n\treturn rtw_blacklist_add(&plink_ctl->cto_mgate_blacklist, addr\n\t\t, mcfg->peer_sel_policy.cto_mgate_blacklist_timeout_ms);\n}\n\nint rtw_mesh_cto_mgate_blacklist_del(_adapter *adapter, const u8 *addr)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\n\treturn rtw_blacklist_del(&plink_ctl->cto_mgate_blacklist, addr);\n}\n\nint rtw_mesh_cto_mgate_blacklist_search(_adapter *adapter, const u8 *addr)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\n\treturn rtw_blacklist_search(&plink_ctl->cto_mgate_blacklist, addr);\n}\n\nvoid rtw_mesh_cto_mgate_blacklist_flush(_adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\n\trtw_blacklist_flush(&plink_ctl->cto_mgate_blacklist);\n}\n\nvoid dump_mesh_cto_mgate_blacklist(void *sel, _adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\n\tdump_blacklist(sel, &plink_ctl->cto_mgate_blacklist, \"blacklist\");\n}\n\nvoid dump_mesh_cto_mgate_blacklist_settings(void *sel, _adapter *adapter)\n{\n\tstruct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;\n\n\tRTW_PRINT_SEL(sel, \"%-12s %-17s\\n\"\n\t\t, \"conf_timeout\", \"blacklist_timeout\");\n\tRTW_PRINT_SEL(sel, \"%12u %17u\\n\"\n\t\t, peer_sel_policy->cto_mgate_conf_timeout_ms\n\t\t, peer_sel_policy->cto_mgate_blacklist_timeout_ms);\n}\n\nstatic void rtw_mesh_cto_mgate_blacklist_chk(_adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\t_queue *blist = &plink_ctl->cto_mgate_blacklist;\n\t_list *list, *head;\n\tstruct blacklist_ent *ent = NULL;\n\tstruct wlan_network *scanned = NULL;\n\n\tenter_critical_bh(&blist->lock);\n\thead = &blist->queue;\n\tlist = get_next(head);\n\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\tent = LIST_CONTAINOR(list, struct blacklist_ent, list);\n\t\tlist = get_next(list);\n\n\t\tif (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {\n\t\t\trtw_list_delete(&ent->list);\n\t\t\trtw_mfree(ent, sizeof(struct blacklist_ent));\n\t\t\tcontinue;\n\t\t}\n\n\t\tscanned = rtw_find_network(&adapter->mlmepriv.scanned_queue, ent->addr);\n\t\tif (!scanned)\n\t\t\tcontinue;\n\n\t\tif (rtw_bss_is_forwarding(&scanned->network)) {\n\t\t\trtw_list_delete(&ent->list);\n\t\t\trtw_mfree(ent, sizeof(struct blacklist_ent));\n\t\t}\n\t}\n\n\texit_critical_bh(&blist->lock);\n}\n#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */\n\nvoid rtw_chk_candidate_peer_notify(_adapter *adapter, struct wlan_network *scanned)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tbool acnode = 0;\n\n\tif (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl))\n\t\tgoto exit;\n\n\tif (plink_ctl->num >= RTW_MESH_MAX_PEER_CANDIDATES)\n\t\tgoto exit;\n\n#if CONFIG_RTW_MESH_ACNODE_PREVENT\n\tif (plink_ctl->acnode_rsvd) {\n\t\tacnode = rtw_mesh_scanned_is_acnode_confirmed(adapter, scanned);\n\t\tif (acnode && !rtw_mesh_scanned_is_acnode_allow_notify(adapter, scanned))\n\t\t\tgoto exit;\n\t}\n#endif\n\n\t/* wpa_supplicant's auto peer will initiate peering when candidate peer is reported without max_peer_links consideration */\n\tif (plink_ctl->num >= mcfg->max_peer_links + acnode ? 1 : 0)\n\t\tgoto exit;\n\n\tif (rtw_get_passing_time_ms(scanned->last_scanned) >= mcfg->peer_sel_policy.scanr_exp_ms\n\t\t|| (mcfg->rssi_threshold && mcfg->rssi_threshold > scanned->network.Rssi)\n\t\t|| !rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 1, 1)\n\t\t#if CONFIG_RTW_MACADDR_ACL\n\t\t|| rtw_access_ctrl(adapter, scanned->network.MacAddress) == _FALSE\n\t\t#endif\n\t\t|| rtw_mesh_plink_get(adapter, scanned->network.MacAddress)\n\t\t#if CONFIG_RTW_MESH_PEER_BLACKLIST\n\t\t|| rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)\n\t\t#endif\n\t\t#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\t\t|| !rtw_mesh_cto_mgate_network_filter(adapter, scanned)\n\t\t#endif\n\t)\n\t\tgoto exit;\n\n#if CONFIG_RTW_MESH_ACNODE_PREVENT\n\tif (acnode) {\n\t\tscanned->acnode_notify_etime = 0;\n\t\tRTW_INFO(FUNC_ADPT_FMT\" acnode \"MAC_FMT\"\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(scanned->network.MacAddress));\n\t}\n#endif\n\n#ifdef CONFIG_IOCTL_CFG80211\n\trtw_cfg80211_notify_new_peer_candidate(adapter->rtw_wdev\n\t\t, scanned->network.MacAddress\n\t\t, BSS_EX_TLV_IES(&scanned->network)\n\t\t, BSS_EX_TLV_IES_LEN(&scanned->network)\n\t\t, scanned->network.Rssi\n\t\t, GFP_ATOMIC\n\t);\n#endif\n\nexit:\n\treturn;\n}\n\nvoid rtw_mesh_peer_status_chk(_adapter *adapter)\n{\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tstruct mesh_plink_ent *plink;\n\t_list *head, *list;\n\tstruct sta_info *sta = NULL;\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tint stainfo_offset;\n#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\tu8 cto_mgate, forwarding, mgate;\n#endif\n\tu8 flush;\n\ts8 flush_list[NUM_STA];\n\tu8 flush_num = 0;\n\tint i;\n\n#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\tif (rtw_mesh_cto_mgate_required(adapter)) {\n\t\t/* active scan on operating channel */\n\t\tissue_probereq_ex(adapter, &adapter->mlmepriv.cur_network.network.mesh_id, NULL, 0, 0, 0, 0);\n\t}\n#endif\n\n\tenter_critical_bh(&(plink_ctl->lock));\n\n\t/* check established peers */\n\tenter_critical_bh(&stapriv->asoc_list_lock);\n\n\thead = &stapriv->asoc_list;\n\tlist = get_next(head);\n\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\tsta = LIST_CONTAINOR(list, struct sta_info, asoc_list);\n\t\tlist = get_next(list);\n\n\t\tif (!sta->plink || !sta->plink->scanned) {\n\t\t\trtw_warn_on(1);\n\t\t\tcontinue;\n\t\t}\n\t\tplink = sta->plink;\n\t\tflush = 0;\n\n\t\t/* remove unsuitable peer */\n\t\tif (!rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &plink->scanned->network, 1, 0)\n\t\t\t#if CONFIG_RTW_MACADDR_ACL\n\t\t\t|| rtw_access_ctrl(adapter, plink->addr) == _FALSE\n\t\t\t#endif\n\t\t) {\n\t\t\tflush = 1;\n\t\t\tgoto flush_add;\n\t\t}\n\n\t\t#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\t\tcto_mgate = rtw_bss_is_cto_mgate(&(plink->scanned->network));\n\t\tforwarding = rtw_bss_is_forwarding(&(plink->scanned->network));\n\t\tmgate = rtw_mesh_gate_search(minfo->mesh_paths, sta->cmn.mac_addr);\n\n\t\t/* CTO_MGATE required, remove peer without CTO_MGATE */\n\t\tif (rtw_mesh_cto_mgate_required(adapter) && !cto_mgate) {\n\t\t\tflush = 1;\n\t\t\tgoto flush_add;\n\t\t}\n\n\t\t/* cto_mgate_conf status update */\n\t\tif (IS_CTO_MGATE_CONF_DISABLED(plink)) {\n\t\t\tif (cto_mgate && !forwarding && !mgate)\n\t\t\t\tSET_CTO_MGATE_CONF_END_TIME(plink, mcfg->peer_sel_policy.cto_mgate_conf_timeout_ms);\n\t\t\telse\n\t\t\t\trtw_mesh_cto_mgate_blacklist_del(adapter, sta->cmn.mac_addr);\n\t\t} else {\n\t\t\t/* cto_mgate_conf ongoing */\n\t\t\tif (cto_mgate && !forwarding && !mgate) {\n\t\t\t\tif (IS_CTO_MGATE_CONF_TIMEOUT(plink)) {\n\t\t\t\t\trtw_mesh_cto_mgate_blacklist_add(adapter, sta->cmn.mac_addr);\n\n\t\t\t\t\t/* CTO_MGATE required, remove peering can't achieve CTO_MGATE */\n\t\t\t\t\tif (rtw_mesh_cto_mgate_required(adapter)) {\n\t\t\t\t\t\tflush = 1;\n\t\t\t\t\t\tgoto flush_add;\n\t\t\t\t\t}\t\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tSET_CTO_MGATE_CONF_DISABLED(plink);\n\t\t\t\trtw_mesh_cto_mgate_blacklist_del(adapter, sta->cmn.mac_addr);\n\t\t\t}\n\t\t}\n\t\t#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */\n\nflush_add:\n\t\tif (flush) {\n\t\t\trtw_list_delete(&sta->asoc_list);\n\t\t\tstapriv->asoc_list_cnt--;\n\t\t\tSTA_SET_MESH_PLINK(sta, NULL);\n\n\t\t\tstainfo_offset = rtw_stainfo_offset(stapriv, sta);\n\t\t\tif (stainfo_offset_valid(stainfo_offset))\n\t\t\t\tflush_list[flush_num++] = stainfo_offset;\n\t\t\telse\n\t\t\t\trtw_warn_on(1);\n\t\t}\n\t}\n\n\texit_critical_bh(&stapriv->asoc_list_lock);\n\n\t/* check non-established peers */\n\tfor (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {\n\t\tplink = &plink_ctl->ent[i];\n\t\tif (plink->valid != _TRUE || plink->plink_state == RTW_MESH_PLINK_ESTAB)\n\t\t\tcontinue;\n\n\t\t/* remove unsuitable peer */\n\t\tif (!rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &plink->scanned->network, 1, 1)\n\t\t\t#if CONFIG_RTW_MACADDR_ACL\n\t\t\t|| rtw_access_ctrl(adapter, plink->addr) == _FALSE\n\t\t\t#endif\n\t\t) {\n\t\t\t_rtw_mesh_expire_peer_ent(adapter, plink);\n\t\t\tcontinue;\n\t\t}\n\n\t\t#if CONFIG_RTW_MESH_PEER_BLACKLIST\n\t\t/* peer confirm check timeout, add to black list */\n\t\tif (IS_PEER_CONF_TIMEOUT(plink)) {\n\t\t\trtw_mesh_peer_blacklist_add(adapter, plink->addr);\n\t\t\t_rtw_mesh_expire_peer_ent(adapter, plink);\n\t\t}\n\t\t#endif\n\t}\n\n\texit_critical_bh(&(plink_ctl->lock));\n\n\tif (flush_num) {\n\t\tu8 sta_addr[ETH_ALEN];\n\t\tu8 updated = _FALSE;\n\n\t\tfor (i = 0; i < flush_num; i++) {\n\t\t\tsta = rtw_get_stainfo_by_offset(stapriv, flush_list[i]);\n\t\t\t_rtw_memcpy(sta_addr, sta->cmn.mac_addr, ETH_ALEN);\n\n\t\t\tupdated |= ap_free_sta(adapter, sta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _FALSE);\n\t\t\trtw_mesh_expire_peer(adapter, sta_addr);\n\t\t}\n\n\t\tassociated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL);\n\t}\n\n#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\t/* loop cto_mgate_blacklist to remove ent according to scan_r */\n\trtw_mesh_cto_mgate_blacklist_chk(adapter);\n#endif\n\n#if CONFIG_RTW_MESH_ACNODE_PREVENT\n\trtw_mesh_acnode_rsvd_chk(adapter);\n#endif\n\n\treturn;\n}\n\n#if CONFIG_RTW_MESH_OFFCH_CAND\nstatic u8 rtw_mesh_offch_cto_mgate_required(_adapter *adapter)\n{\n#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\t_queue *queue = &(mlme->scanned_queue);\n\t_list *head, *pos;\n\tstruct wlan_network *scanned = NULL;\n\tu8 ret = 0;\n\n\tif (!rtw_mesh_cto_mgate_required(adapter))\n\t\tgoto exit;\n\n\tenter_critical_bh(&(mlme->scanned_queue.lock));\n\n\thead = get_list_head(queue);\n\tpos = get_next(head);\n\twhile (!rtw_end_of_queue_search(head, pos)) {\n\t\tscanned = LIST_CONTAINOR(pos, struct wlan_network, list);\n\n\t\tif (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms\n\t\t\t&& (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi)\n\t\t\t#if CONFIG_RTW_MACADDR_ACL\n\t\t\t&& rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE\n\t\t\t#endif\n\t\t\t&& rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 1, 1)\n\t\t\t&& rtw_bss_is_cto_mgate(&scanned->network)\n\t\t\t#if CONFIG_RTW_MESH_PEER_BLACKLIST\n\t\t\t&& !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)\n\t\t\t#endif\n\t\t\t&& !rtw_mesh_cto_mgate_blacklist_search(adapter, scanned->network.MacAddress)\n\t\t)\n\t\t\tbreak;\n\n\t\tpos = get_next(pos);\n\t}\n\n\tif (rtw_end_of_queue_search(head, pos))\n\t\tret = 1;\n\n\texit_critical_bh(&(mlme->scanned_queue.lock));\n\nexit:\n\treturn ret;\n#else\n\treturn 0;\n#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */\n}\n\nu8 rtw_mesh_offch_candidate_accepted(_adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tu8 ret = 0;\n\n\tif (!adapter->mesh_cfg.peer_sel_policy.offch_cand)\n\t\tgoto exit;\n\n\tret = MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)\n\t\t&& (!plink_ctl->num || rtw_mesh_offch_cto_mgate_required(adapter))\n\t\t;\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (ret) {\n\t\tstruct mi_state mstate_no_self;\n\n\t\trtw_mi_status_no_self(adapter, &mstate_no_self);\n\t\tif (MSTATE_STA_LD_NUM(&mstate_no_self))\n\t\t\tret = 0;\n\t}\n#endif\n\nexit:\n\treturn ret;\n}\n\n/*\n * this function is called under off channel candidate is required \n * the channel with maximum candidate count is selected\n*/\nu8 rtw_mesh_select_operating_ch(_adapter *adapter)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\t_queue *queue = &(mlme->scanned_queue);\n\t_list *head, *pos;\n\t_irqL irqL;\n\tstruct wlan_network *scanned = NULL;\n\tint i;\n\t/* statistics for candidate accept peering */\n\tu8 cand_ap_cnt[MAX_CHANNEL_NUM] = {0};\n\tu8 max_cand_ap_ch = 0;\n\tu8 max_cand_ap_cnt = 0;\n\t/* statistics for candidate including not accept peering */\n\tu8 cand_cnt[MAX_CHANNEL_NUM] = {0};\n\tu8 max_cand_ch = 0;\n\tu8 max_cand_cnt = 0;\n\n\t_enter_critical_bh(&(mlme->scanned_queue.lock), &irqL);\n\n\thead = get_list_head(queue);\n\tpos = get_next(head);\n\twhile (!rtw_end_of_queue_search(head, pos)) {\n\t\tscanned = LIST_CONTAINOR(pos, struct wlan_network, list);\n\t\tpos = get_next(pos);\n\n\t\tif (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms\n\t\t\t&& (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi)\n\t\t\t#if CONFIG_RTW_MACADDR_ACL\n\t\t\t&& rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE\n\t\t\t#endif\n\t\t\t&& rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 0, 0)\n\t\t\t#if CONFIG_RTW_MESH_PEER_BLACKLIST\n\t\t\t&& !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)\n\t\t\t#endif\n\t\t\t#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\t\t\t&& rtw_mesh_cto_mgate_network_filter(adapter, scanned)\n\t\t\t#endif\n\t\t) {\n\t\t\tint ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, scanned->network.Configuration.DSConfig);\n\n\t\t\tif (ch_set_idx >= 0\n\t\t\t\t&& !CH_IS_NON_OCP(&rfctl->channel_set[ch_set_idx])\n\t\t\t) {\n\t\t\t\tu8 nop, accept;\n\n\t\t\t\trtw_mesh_bss_peering_status(&scanned->network, &nop, &accept);\n\t\t\t\tcand_cnt[ch_set_idx]++;\n\t\t\t\tif (max_cand_cnt < cand_cnt[ch_set_idx]) {\n\t\t\t\t\tmax_cand_cnt = cand_cnt[ch_set_idx];\n\t\t\t\t\tmax_cand_ch = rfctl->channel_set[ch_set_idx].ChannelNum;\n\t\t\t\t}\n\t\t\t\tif (accept) {\n\t\t\t\t\tcand_ap_cnt[ch_set_idx]++;\n\t\t\t\t\tif (max_cand_ap_cnt < cand_ap_cnt[ch_set_idx]) {\n\t\t\t\t\t\tmax_cand_ap_cnt = cand_ap_cnt[ch_set_idx];\n\t\t\t\t\t\tmax_cand_ap_ch = rfctl->channel_set[ch_set_idx].ChannelNum;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t_exit_critical_bh(&(mlme->scanned_queue.lock), &irqL);\n\n\treturn max_cand_ap_ch ? max_cand_ap_ch : max_cand_ch;\n}\n\nvoid dump_mesh_offch_cand_settings(void *sel, _adapter *adapter)\n{\n\tstruct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;\n\n\tRTW_PRINT_SEL(sel, \"%-6s %-11s\\n\"\n\t\t, \"enable\", \"find_int_ms\");\n\tRTW_PRINT_SEL(sel, \"%6u %11u\\n\"\n\t\t, peer_sel_policy->offch_cand, peer_sel_policy->offch_find_int_ms);\n}\n#endif /* CONFIG_RTW_MESH_OFFCH_CAND */\n\nvoid dump_mesh_peer_sel_policy(void *sel, _adapter *adapter)\n{\n\tstruct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;\n\n\tRTW_PRINT_SEL(sel, \"%-12s\\n\", \"scanr_exp_ms\");\n\tRTW_PRINT_SEL(sel, \"%12u\\n\", peer_sel_policy->scanr_exp_ms);\n}\n\nvoid dump_mesh_networks(void *sel, _adapter *adapter)\n{\n#if CONFIG_RTW_MESH_ACNODE_PREVENT\n#define NSTATE_TITLE_FMT_ACN \" %-5s\"\n#define NSTATE_VALUE_FMT_ACN \" %5d\"\n#define NSTATE_TITLE_ARG_ACN , \"acn\"\n#define NSTATE_VALUE_ARG_ACN , (acn_ms < 99999 ? acn_ms : 99999)\n#else\n#define NSTATE_TITLE_FMT_ACN \"\"\n#define NSTATE_VALUE_FMT_ACN \"\"\n#define NSTATE_TITLE_ARG_ACN\n#define NSTATE_VALUE_ARG_ACN\n#endif\n\n\tstruct mlme_priv *mlme = &(adapter->mlmepriv);\n\t_queue *queue = &(mlme->scanned_queue);\n\tstruct wlan_network\t*network;\n\t_list *list, *head;\n\tu8 same_mbss;\n\tu8 candidate;\n\tstruct mesh_plink_ent *plink;\n\tu8 blocked;\n\tu8 established;\n\ts32 age_ms;\n#if CONFIG_RTW_MESH_ACNODE_PREVENT\n\ts32 acn_ms;\n#endif\n\tu8 *mesh_conf_ie;\n\tsint mesh_conf_ie_len;\n\tstruct wlan_network **mesh_networks;\n\tu8 mesh_network_cnt = 0;\n\tint i;\n\n\tmesh_networks = rtw_zvmalloc(mlme->max_bss_cnt * sizeof(struct wlan_network *));\n\tif (!mesh_networks)\n\t\treturn;\n\n\tenter_critical_bh(&queue->lock);\n\thead = get_list_head(queue);\n\tlist = get_next(head);\n\n\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\tnetwork = LIST_CONTAINOR(list, struct wlan_network, list);\n\t\tlist = get_next(list);\n\n\t\tif (network->network.InfrastructureMode != Ndis802_11_mesh)\n\t\t\tcontinue;\n\n\t\tmesh_conf_ie = rtw_get_ie(BSS_EX_TLV_IES(&network->network), WLAN_EID_MESH_CONFIG\n\t\t\t, &mesh_conf_ie_len, BSS_EX_TLV_IES_LEN(&network->network));\n\t\tif (!mesh_conf_ie || mesh_conf_ie_len != 7)\n\t\t\tcontinue;\n\n\t\tmesh_networks[mesh_network_cnt++] = network;\n\t}\n\n\texit_critical_bh(&queue->lock);\n\n\tRTW_PRINT_SEL(sel, \"  %-17s %-3s %-4s %-5s %-32s %-3s %-3s %-3s\"\n\t\tNSTATE_TITLE_FMT_ACN\n\t\t\"\\n\"\n\t\t, \"bssid\", \"ch\", \"rssi\", \"age\", \"mesh_id\", \"nop\", \"fwd\", \"cto\"\n\t\tNSTATE_TITLE_ARG_ACN\n\t);\n\n\tfor (i = 0; i < mesh_network_cnt; i++) {\n\t\tnetwork = mesh_networks[i];\n\n\t\tif (network->network.InfrastructureMode != Ndis802_11_mesh)\n\t\t\tcontinue;\n\n\t\tmesh_conf_ie = rtw_get_ie(BSS_EX_TLV_IES(&network->network), WLAN_EID_MESH_CONFIG\n\t\t\t, &mesh_conf_ie_len, BSS_EX_TLV_IES_LEN(&network->network));\n\t\tif (!mesh_conf_ie || mesh_conf_ie_len != 7)\n\t\t\tcontinue;\n\n\t\tage_ms = rtw_get_passing_time_ms(network->last_scanned);\n\t\t#if CONFIG_RTW_MESH_ACNODE_PREVENT\n\t\tif (network->acnode_stime == 0)\n\t\t\tacn_ms = 0;\n\t\telse\n\t\t\tacn_ms = rtw_get_passing_time_ms(network->acnode_stime);\n\t\t#endif\n\t\tsame_mbss = 0;\n\t\tcandidate = 0;\n\t\tplink = NULL;\n\t\tblocked = 0;\n\t\testablished = 0;\n\n\t\tif (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)) {\n\t\t\tplink = rtw_mesh_plink_get(adapter, network->network.MacAddress);\n\t\t\tif (plink && plink->plink_state == RTW_MESH_PLINK_ESTAB)\n\t\t\t\testablished = 1;\n\t\t\telse if (plink && plink->plink_state == RTW_MESH_PLINK_BLOCKED)\n\t\t\t\tblocked = 1;\n\t\t\telse if (plink)\n\t\t\t\t;\n\t\t\telse if (rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &network->network, 0, 1))\n\t\t\t\tcandidate = 1;\n\t\t\telse if (rtw_bss_is_same_mbss(&mlme->cur_network.network, &network->network))\n\t\t\t\tsame_mbss = 1;\n\t\t}\n\n\t\tRTW_PRINT_SEL(sel, \"%c \"MAC_FMT\" %3d %4ld %5d %-32s %c%2u %3u %c%c \"\n\t\t\tNSTATE_VALUE_FMT_ACN\n\t\t\t\"\\n\"\n\t\t\t, established ? 'E' : (blocked ? 'B' : (plink ? 'N' : (candidate ? 'C' : (same_mbss ? 'S' : ' '))))\n\t\t\t, MAC_ARG(network->network.MacAddress)\n\t\t\t, network->network.Configuration.DSConfig\n\t\t\t, network->network.Rssi\n\t\t\t, age_ms < 99999 ? age_ms : 99999\n\t\t\t, network->network.mesh_id.Ssid\n\t\t\t, GET_MESH_CONF_ELE_ACCEPT_PEERINGS(mesh_conf_ie + 2) ? '+' : ' '\n\t\t\t, GET_MESH_CONF_ELE_NUM_OF_PEERINGS(mesh_conf_ie + 2)\n\t\t\t, GET_MESH_CONF_ELE_FORWARDING(mesh_conf_ie + 2)\n\t\t\t, GET_MESH_CONF_ELE_CTO_MGATE(mesh_conf_ie + 2) ? 'G' : ' '\n\t\t\t, GET_MESH_CONF_ELE_CTO_AS(mesh_conf_ie + 2) ? 'A' : ' '\n\t\t\tNSTATE_VALUE_ARG_ACN\n\t\t);\n\t}\n\n\trtw_vmfree(mesh_networks, mlme->max_bss_cnt * sizeof(struct wlan_network *));\n}\n\nvoid rtw_mesh_adjust_chbw(u8 req_ch, u8 *req_bw, u8 *req_offset)\n{\n\tif (req_ch >= 5 && req_ch <= 9) {\n\t\t/* prevent secondary channel offset mismatch */\n\t\tif (*req_bw > CHANNEL_WIDTH_20) {\n\t\t\t*req_bw = CHANNEL_WIDTH_20;\n\t\t\t*req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t}\n\t}\n}\n\nvoid rtw_mesh_sae_check_frames(_adapter *adapter, const u8 *buf, u32 len, u8 tx, u16 alg, u16 seq, u16 status)\n{\n#if CONFIG_RTW_MESH_PEER_BLACKLIST\n\tif (tx && seq == 1)\n\t\trtw_mesh_plink_set_peer_conf_timeout(adapter, GetAddr1Ptr(buf));\n#endif\n}\n\n#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS\n#ifdef CONFIG_RTW_MESH_AEK\nstatic int rtw_mpm_ampe_dec(_adapter *adapter, struct mesh_plink_ent *plink\n\t, u8 *fhead, size_t flen, u8* fbody, u8 *mic_ie, u8 *ampe_buf)\n{\t\n\tint ret = _FAIL, verify_ret;\n\tconst u8 *aad[] = {adapter_mac_addr(adapter), plink->addr, fbody};\n\tconst size_t aad_len[] = {ETH_ALEN, ETH_ALEN, mic_ie - fbody};\n\tu8 *iv_crypt;\n\tsize_t iv_crypt_len = flen - (mic_ie + 2 - fhead);\n\n\tiv_crypt = rtw_malloc(iv_crypt_len);\n\tif (!iv_crypt)\n\t\tgoto exit;\n\n\t_rtw_memcpy(iv_crypt, mic_ie + 2, iv_crypt_len);\n\n\tverify_ret = aes_siv_decrypt(plink->aek, iv_crypt, iv_crypt_len\n\t\t, 3, aad, aad_len, ampe_buf);\n\n\trtw_mfree(iv_crypt, iv_crypt_len);\n\n\tif (verify_ret) {\n\t\tRTW_WARN(\"verify error, aek_valid=%u\\n\", plink->aek_valid);\n\t\tgoto exit;\n\t} else if (*ampe_buf != WLAN_EID_AMPE) {\n\t\tRTW_WARN(\"plaintext is not AMPE IE\\n\");\n\t\tgoto exit;\n\t} else if (AES_BLOCK_SIZE + 2 + *(ampe_buf + 1) > iv_crypt_len) {\n\t\tRTW_WARN(\"plaintext AMPE IE length is not valid\\n\");\n\t\tgoto exit;\n\t}\n\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n\nstatic int rtw_mpm_ampe_enc(_adapter *adapter, struct mesh_plink_ent *plink\n\t, u8* fbody, u8 *mic_ie, u8 *ampe_buf, bool inverse)\n{\n\tint ret = _FAIL, protect_ret;\n\tconst u8 *aad[3];\n\tconst size_t aad_len[3] = {ETH_ALEN, ETH_ALEN, mic_ie - fbody};\n\tu8 *ampe_ie;\n\tsize_t ampe_ie_len = *(ampe_buf + 1) + 2; /* including id & len */\n\n\tif (inverse) {\n\t\taad[0] = plink->addr;\n\t\taad[1] = adapter_mac_addr(adapter);\n\t} else {\n\t\taad[0] = adapter_mac_addr(adapter);\n\t\taad[1] = plink->addr;\n\t}\n\taad[2] = fbody;\n\n\tampe_ie = rtw_malloc(ampe_ie_len);\n\tif (!ampe_ie)\n\t\tgoto exit;\n\n\t_rtw_memcpy(ampe_ie, ampe_buf, ampe_ie_len);\n\n\tprotect_ret = aes_siv_encrypt(plink->aek, ampe_ie, ampe_ie_len\n\t\t, 3, aad, aad_len, mic_ie + 2);\n\n\trtw_mfree(ampe_ie, ampe_ie_len);\n\n\tif (protect_ret) {\n\t\tRTW_WARN(\"protect error, aek_valid=%u\\n\", plink->aek_valid);\n\t\tgoto exit;\n\t}\n\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n#endif /* CONFIG_RTW_MESH_AEK */\n\nstatic int rtw_mpm_tx_ies_sync_bss(_adapter *adapter, struct mesh_plink_ent *plink\n\t, u8 *fhead, size_t flen, u8* fbody, u8 tlv_ies_offset, u8 *mpm_ie, u8 *mic_ie\n\t, u8 **nbuf, size_t *nlen)\n{\n\tint ret = _FAIL;\n\tstruct mlme_priv *mlme = &(adapter->mlmepriv);\n\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info);\n\tWLAN_BSSID_EX *network = &(mlmeinfo->network);\n\tuint left;\n\tu8 *pos;\n\n\tuint mpm_ielen = *(mpm_ie + 1);\n\tu8 *fpos;\n\tu8 *new_buf = NULL;\n\tsize_t new_len = 0;\n\n\tu8 *new_fhead;\n\tsize_t new_flen;\n\tu8 *new_fbody;\n\tu8 *new_mic_ie;\n\n#ifdef CONFIG_RTW_MESH_AEK\n\tu8 *ampe_buf = NULL;\n\tsize_t ampe_buf_len = 0;\n\n\t/* decode */\n\tif (mic_ie) {\n\t\tampe_buf_len = flen - (mic_ie + 2 + AES_BLOCK_SIZE - fhead);\n\t\tampe_buf = rtw_malloc(ampe_buf_len);\n\t\tif (!ampe_buf)\n\t\t\tgoto exit;\n\n\t\tif (rtw_mpm_ampe_dec(adapter, plink, fhead, flen, fbody, mic_ie, ampe_buf) != _SUCCESS)\n\t\t\tgoto exit;\n\n\t\tif (*(ampe_buf + 1) >= 68) {\n\t\t\t_rtw_memcpy(plink->sel_pcs, ampe_buf + 2, 4);\n\t\t\t_rtw_memcpy(plink->l_nonce, ampe_buf + 6, 32);\n\t\t\t_rtw_memcpy(plink->p_nonce, ampe_buf + 38, 32);\n\t\t}\n\t}\n#endif\n\n\t/* count for new frame length  */\n\tnew_len = sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset;\n\tleft = BSS_EX_TLV_IES_LEN(network);\n\tpos = BSS_EX_TLV_IES(network);\n\twhile (left >= 2) {\n\t\tu8 id, elen;\n\t\n\t\tid = *pos++;\n\t\telen = *pos++;\n\t\tleft -= 2;\n\n\t\tif (elen > left)\n\t\t\tbreak;\n\n\t\tswitch (id) {\n\t\tcase WLAN_EID_SSID:\n\t\tcase WLAN_EID_DS_PARAMS:\n\t\tcase WLAN_EID_TIM:\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tnew_len += 2 + elen;\n\t\t}\n\n\t\tleft -= elen;\n\t\tpos += elen;\n\t}\n\tnew_len += mpm_ielen + 2;\n\tif (mic_ie)\n\t\tnew_len += AES_BLOCK_SIZE + 2 + ampe_buf_len;\n\n\t/* alloc new frame */\n\tnew_buf = rtw_malloc(new_len);\n\tif (!new_buf) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\t/* build new frame  */\n\t_rtw_memcpy(new_buf, fhead, sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset);\n\tnew_fhead = new_buf;\n\tnew_flen = new_len;\n\tnew_fbody = new_fhead + sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tfpos = new_fbody + tlv_ies_offset;\n\tleft = BSS_EX_TLV_IES_LEN(network);\n\tpos = BSS_EX_TLV_IES(network);\n\twhile (left >= 2) {\n\t\tu8 id, elen;\n\t\n\t\tid = *pos++;\n\t\telen = *pos++;\n\t\tleft -= 2;\n\n\t\tif (elen > left)\n\t\t\tbreak;\n\n\t\tswitch (id) {\n\t\tcase WLAN_EID_SSID:\n\t\tcase WLAN_EID_DS_PARAMS:\n\t\tcase WLAN_EID_TIM:\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tfpos = rtw_set_ie(fpos, id, elen, pos, NULL);\n\t\t\tif (id == WLAN_EID_MESH_CONFIG)\n\t\t\t\tfpos = rtw_set_ie(fpos, WLAN_EID_MPM, mpm_ielen, mpm_ie + 2, NULL);\n\t\t}\n\n\t\tleft -= elen;\n\t\tpos += elen;\n\t}\n\tif (mic_ie) {\n\t\tnew_mic_ie = fpos;\n\t\t*fpos++ = WLAN_EID_MIC;\n\t\t*fpos++ = AES_BLOCK_SIZE;\n\t}\n\n#ifdef CONFIG_RTW_MESH_AEK\n\t/* encode */\n\tif (mic_ie) {\n\t\tint enc_ret = rtw_mpm_ampe_enc(adapter, plink, new_fbody, new_mic_ie, ampe_buf, 0);\n\t\tif (enc_ret != _SUCCESS)\n\t\t\tgoto exit;\n\t}\n#endif\n\n\t*nlen = new_len;\n\t*nbuf = new_buf;\n\n\tret = _SUCCESS;\n\nexit:\n\tif (ret != _SUCCESS && new_buf)\n\t\trtw_mfree(new_buf, new_len);\n\n#ifdef CONFIG_RTW_MESH_AEK\n\tif (ampe_buf)\n\t\trtw_mfree(ampe_buf, ampe_buf_len);\n#endif\n\n\treturn ret;\n}\n#endif /* CONFIG_RTW_MPM_TX_IES_SYNC_BSS */\n\nstruct mpm_frame_info {\n\tu8 *aid;\n\tu16 aid_v;\n\tu8 *pid;\n\tu16 pid_v;\n\tu8 *llid;\n\tu16 llid_v;\n\tu8 *plid;\n\tu16 plid_v;\n\tu8 *reason;\n\tu16 reason_v;\n\tu8 *chosen_pmk;\n};\n\n/*\n* pid:00000 llid:00000 chosen_pmk:0x00000000000000000000000000000000\n* aid:00000 pid:00000 llid:00000 plid:00000 chosen_pmk:0x00000000000000000000000000000000\n* pid:00000 llid:00000 plid:00000 reason:00000 chosen_pmk:0x00000000000000000000000000000000\n*/\n#define MPM_LOG_BUF_LEN 92 /* this length is limited for legal combination */\nstatic void rtw_mpm_info_msg(struct mpm_frame_info *mpm_info, u8 *mpm_log_buf)\n{\n\tint cnt = 0;\n\n\tif (mpm_info->aid) {\n\t\tcnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, \"aid:%u \", mpm_info->aid_v);\n\t\tif (cnt >= MPM_LOG_BUF_LEN - 1)\n\t\t\tgoto exit;\n\t}\n\tif (mpm_info->pid) {\n\t\tcnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, \"pid:%u \", mpm_info->pid_v);\n\t\tif (cnt >= MPM_LOG_BUF_LEN - 1)\n\t\t\tgoto exit;\n\t}\n\tif (mpm_info->llid) {\n\t\tcnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, \"llid:%u \", mpm_info->llid_v);\n\t\tif (cnt >= MPM_LOG_BUF_LEN - 1)\n\t\t\tgoto exit;\n\t}\n\tif (mpm_info->plid) {\n\t\tcnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, \"plid:%u \", mpm_info->plid_v);\n\t\tif (cnt >= MPM_LOG_BUF_LEN - 1)\n\t\t\tgoto exit;\n\t}\n\tif (mpm_info->reason) {\n\t\tcnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, \"reason:%u \", mpm_info->reason_v);\n\t\tif (cnt >= MPM_LOG_BUF_LEN - 1)\n\t\t\tgoto exit;\n\t}\n\tif (mpm_info->chosen_pmk) {\n\t\tcnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, \"chosen_pmk:0x\"KEY_FMT, KEY_ARG(mpm_info->chosen_pmk));\n\t\tif (cnt >= MPM_LOG_BUF_LEN - 1)\n\t\t\tgoto exit;\n\t}\n\nexit:\n\treturn;\n}\n\nstatic int rtw_mpm_check_frames(_adapter *adapter, u8 action, const u8 **buf, size_t *len, u8 tx)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tstruct mesh_plink_ent *plink = NULL;\n\tu8 *nbuf = NULL;\n\tsize_t nlen = 0;\n\tu8 *fhead = (u8 *)*buf;\n\tsize_t flen = *len;\n\tu8 *peer_addr = tx ? GetAddr1Ptr(fhead) : get_addr2_ptr(fhead);\n\tu8 *frame_body = fhead + sizeof(struct rtw_ieee80211_hdr_3addr);\n\tstruct mpm_frame_info mpm_info;\n\tu8 tlv_ies_offset;\n\tu8 *mpm_ie = NULL;\n\tuint mpm_ielen = 0;\n\tu8 *mic_ie = NULL;\n\tuint mic_ielen = 0;\n\tint ret = 0;\n\tu8 mpm_log_buf[MPM_LOG_BUF_LEN] = {0};\n\n\tif (action == RTW_ACT_SELF_PROTECTED_MESH_OPEN)\n\t\ttlv_ies_offset = 4;\n\telse if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF)\n\t\ttlv_ies_offset = 6;\n\telse if (action == RTW_ACT_SELF_PROTECTED_MESH_CLOSE)\n\t\ttlv_ies_offset = 2;\n\telse {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tplink = rtw_mesh_plink_get(adapter, peer_addr);\n\tif (!plink && (tx == _TRUE || action == RTW_ACT_SELF_PROTECTED_MESH_CONF)) {\n\t\t/* warning message if no plink when: 1.TX all MPM or 2.RX CONF */\n\t\tRTW_WARN(\"RTW_%s:%s without plink of \"MAC_FMT\"\\n\"\n\t\t\t, (tx == _TRUE) ? \"Tx\" : \"Rx\", action_self_protected_str(action), MAC_ARG(peer_addr));\n\t\tgoto exit;\n\t}\n\n\t_rtw_memset(&mpm_info, 0, sizeof(struct mpm_frame_info));\n\n\tif (action == RTW_ACT_SELF_PROTECTED_MESH_CONF) {\n\t\tmpm_info.aid = (u8 *)frame_body + 4;\n\t\tmpm_info.aid_v = RTW_GET_LE16(mpm_info.aid);\n\t}\n\n\tmpm_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset\n\t\t, WLAN_EID_MPM, &mpm_ielen\n\t\t, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);\n\tif (!mpm_ie || mpm_ielen < 2 + 2)\n\t\tgoto exit;\n\n\tmpm_info.pid = mpm_ie + 2;\n\tmpm_info.pid_v = RTW_GET_LE16(mpm_info.pid);\n\tmpm_info.llid = mpm_info.pid + 2;\n\tmpm_info.llid_v = RTW_GET_LE16(mpm_info.llid);\n\n\tswitch (action) {\n\tcase RTW_ACT_SELF_PROTECTED_MESH_OPEN:\n\t\t/* pid:2, llid:2, (chosen_pmk:16) */\n\t\tif (mpm_info.pid_v == 0 && mpm_ielen == 4)\n\t\t\t;\n\t\telse if (mpm_info.pid_v == 1 && mpm_ielen == 20)\n\t\t\tmpm_info.chosen_pmk = mpm_info.llid + 2;\n\t\telse\n\t\t\tgoto exit;\n\t\tbreak;\n\tcase RTW_ACT_SELF_PROTECTED_MESH_CONF:\n\t\t/* pid:2, llid:2, plid:2, (chosen_pmk:16) */\n\t\tmpm_info.plid = mpm_info.llid + 2;\n\t\tmpm_info.plid_v = RTW_GET_LE16(mpm_info.plid);\n\t\tif (mpm_info.pid_v == 0 && mpm_ielen == 6)\n\t\t\t;\n\t\telse if (mpm_info.pid_v == 1 && mpm_ielen == 22)\n\t\t\tmpm_info.chosen_pmk = mpm_info.plid + 2;\n\t\telse\n\t\t\tgoto exit;\n\t\tbreak;\n\tcase RTW_ACT_SELF_PROTECTED_MESH_CLOSE:\n\t\t/* pid:2, llid:2, (plid:2), reason:2, (chosen_pmk:16) */\n\t\tif (mpm_info.pid_v == 0 && mpm_ielen == 6) {\n\t\t\t/* MPM, without plid */\n\t\t\tmpm_info.reason = mpm_info.llid + 2;\n\t\t\tmpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);\n\t\t} else if (mpm_info.pid_v == 0 && mpm_ielen == 8) {\n\t\t\t/* MPM, with plid */\n\t\t\tmpm_info.plid = mpm_info.llid + 2;\n\t\t\tmpm_info.plid_v = RTW_GET_LE16(mpm_info.plid);\n\t\t\tmpm_info.reason = mpm_info.plid + 2;\n\t\t\tmpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);\n\t\t} else if (mpm_info.pid_v == 1 && mpm_ielen == 22) {\n\t\t\t/* AMPE, without plid */\n\t\t\tmpm_info.reason = mpm_info.llid + 2;\n\t\t\tmpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);\n\t\t\tmpm_info.chosen_pmk = mpm_info.reason + 2;\n\t\t} else if (mpm_info.pid_v == 1 && mpm_ielen == 24) {\n\t\t\t/* AMPE, with plid */\n\t\t\tmpm_info.plid = mpm_info.llid + 2;\n\t\t\tmpm_info.plid_v = RTW_GET_LE16(mpm_info.plid);\n\t\t\tmpm_info.reason = mpm_info.plid + 2;\n\t\t\tmpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);\n\t\t\tmpm_info.chosen_pmk = mpm_info.reason + 2;\n\t\t} else\n\t\t\tgoto exit;\n\t\tbreak;\n\t};\n\n\tif (mpm_info.pid_v == 1) {\n\t\tmic_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset\n\t\t\t, WLAN_EID_MIC, &mic_ielen\n\t\t\t, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);\n\t\tif (!mic_ie || mic_ielen != AES_BLOCK_SIZE)\n\t\t\tgoto exit;\n\t}\n\n#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS\n\tif ((action == RTW_ACT_SELF_PROTECTED_MESH_OPEN || action == RTW_ACT_SELF_PROTECTED_MESH_CONF)\n\t\t&& tx == _TRUE\n\t) {\n#define DBG_RTW_MPM_TX_IES_SYNC_BSS 0\n\n\t\tif (mpm_info.pid_v == 1 && (!plink || !MESH_PLINK_AEK_VALID(plink))) {\n\t\t\tRTW_WARN(\"AEK not ready, IEs can't sync with BSS\\n\");\n\t\t\tgoto bypass_sync_bss;\n\t\t}\n\n\t\tif (DBG_RTW_MPM_TX_IES_SYNC_BSS) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" before:\\n\", FUNC_ADPT_ARG(adapter));\n\t\t\tdump_ies(RTW_DBGDUMP\n\t\t\t\t, fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset\n\t\t\t\t, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);\n\t\t}\n\n\t\trtw_mpm_tx_ies_sync_bss(adapter, plink\n\t\t\t, fhead, flen, frame_body, tlv_ies_offset, mpm_ie, mic_ie\n\t\t\t, &nbuf, &nlen);\n\t\tif (!nbuf)\n\t\t\tgoto exit;\n\n\t\t/* update pointer & len for new frame */\n\t\tfhead = nbuf;\n\t\tflen = nlen;\n\t\tframe_body = fhead + sizeof(struct rtw_ieee80211_hdr_3addr);\n\t\tif (mpm_info.pid_v == 1) {\n\t\t\tmic_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset\n\t\t\t\t, WLAN_EID_MIC, &mic_ielen\n\t\t\t\t, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);\n\t\t}\n\n\t\tif (DBG_RTW_MPM_TX_IES_SYNC_BSS) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" after:\\n\", FUNC_ADPT_ARG(adapter));\n\t\t\tdump_ies(RTW_DBGDUMP\n\t\t\t\t, fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset\n\t\t\t\t, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);\n\t\t}\n\t}\nbypass_sync_bss:\n#endif /* CONFIG_RTW_MPM_TX_IES_SYNC_BSS */\n\n\tif (!plink)\n\t\tgoto mpm_log;\n\n#if CONFIG_RTW_MESH_PEER_BLACKLIST\n\tif (action == RTW_ACT_SELF_PROTECTED_MESH_OPEN) {\n\t\tif (tx)\n\t\t\trtw_mesh_plink_set_peer_conf_timeout(adapter, peer_addr);\n\n\t} else\n#endif\n#if CONFIG_RTW_MESH_ACNODE_PREVENT\n\tif (action == RTW_ACT_SELF_PROTECTED_MESH_CLOSE) {\n\t\tif (tx && mpm_info.reason && mpm_info.reason_v == WLAN_REASON_MESH_MAX_PEERS) {\n\t\t\tif (rtw_mesh_scanned_is_acnode_confirmed(adapter, plink->scanned)\n\t\t\t\t&& rtw_mesh_acnode_prevent_allow_sacrifice(adapter)\n\t\t\t) {\n\t\t\t\tstruct sta_info *sac = rtw_mesh_acnode_prevent_pick_sacrifice(adapter);\n\n\t\t\t\tif (sac) {\n\t\t\t\t\tstruct sta_priv *stapriv = &adapter->stapriv;\n\t\t\t\t\t_irqL irqL;\n\t\t\t\t\tu8 sta_addr[ETH_ALEN];\n\t\t\t\t\tu8 updated = _FALSE;\n\n\t\t\t\t\t_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);\n\t\t\t\t\tif (!rtw_is_list_empty(&sac->asoc_list)) {\n\t\t\t\t\t\trtw_list_delete(&sac->asoc_list);\n\t\t\t\t\t\tstapriv->asoc_list_cnt--;\n\t\t\t\t\t\tSTA_SET_MESH_PLINK(sac, NULL);\n\t\t\t\t\t}\n\t\t\t\t\t_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" sacrifice \"MAC_FMT\" for acnode\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(sac->cmn.mac_addr));\n\n\t\t\t\t\t_rtw_memcpy(sta_addr, sac->cmn.mac_addr, ETH_ALEN);\n\t\t\t\t\tupdated = ap_free_sta(adapter, sac, 0, 0, 1);\n\t\t\t\t\trtw_mesh_expire_peer(stapriv->padapter, sta_addr);\n\n\t\t\t\t\tassociated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else\n#endif\n\tif (action == RTW_ACT_SELF_PROTECTED_MESH_CONF) {\n\t\t_irqL irqL;\n\t\tu8 *ies = NULL;\n\t\tu16 ies_len = 0;\n\n\t\t_enter_critical_bh(&(plink_ctl->lock), &irqL);\n\n\t\tplink = _rtw_mesh_plink_get(adapter, peer_addr);\n\t\tif (!plink)\n\t\t\tgoto release_plink_ctl;\n\n\t\tif (tx == _FALSE) {\n\t\t\ties = plink->rx_conf_ies;\n\t\t\ties_len = plink->rx_conf_ies_len;\n\t\t\tplink->rx_conf_ies = NULL;\n\t\t\tplink->rx_conf_ies_len = 0;\n\n\t\t\tplink->llid = mpm_info.plid_v;\n\t\t\tplink->plid = mpm_info.llid_v;\n\t\t\tplink->peer_aid = mpm_info.aid_v;\n\t\t\tif (mpm_info.pid_v == 1)\n\t\t\t\t_rtw_memcpy(plink->chosen_pmk, mpm_info.chosen_pmk, 16);\n\t\t}\n\t\t#ifdef CONFIG_RTW_MESH_DRIVER_AID\n\t\telse {\n\t\t\ties = plink->tx_conf_ies;\n\t\t\ties_len = plink->tx_conf_ies_len;\n\t\t\tplink->tx_conf_ies = NULL;\n\t\t\tplink->tx_conf_ies_len = 0;\n\t\t}\n\t\t#endif\n\n\t\tif (ies && ies_len)\n\t\t\trtw_mfree(ies, ies_len);\n\n\t\t#ifndef CONFIG_RTW_MESH_DRIVER_AID\n\t\tif (tx == _TRUE)\n\t\t\tgoto release_plink_ctl; /* no need to copy tx conf ies */\n\t\t#endif\n\n\t\t/* copy mesh confirm IEs */\n\t\tif (mpm_info.pid_v == 1) /* not include MIC & encrypted AMPE */\n\t\t\ties_len = (mic_ie - fhead) - sizeof(struct rtw_ieee80211_hdr_3addr) - 2;\n\t\telse\n\t\t\ties_len = flen - sizeof(struct rtw_ieee80211_hdr_3addr) - 2;\n\n\t\ties = rtw_zmalloc(ies_len);\n\t\tif (ies) {\n\t\t\t_rtw_memcpy(ies, fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + 2, ies_len);\n\t\t\tif (tx == _FALSE) {\n\t\t\t\tplink->rx_conf_ies = ies;\n\t\t\t\tplink->rx_conf_ies_len = ies_len;\n\t\t\t}\n\t\t\t#ifdef CONFIG_RTW_MESH_DRIVER_AID\t\n\t\t\telse {\n\t\t\t\tplink->tx_conf_ies = ies;\n\t\t\t\tplink->tx_conf_ies_len = ies_len;\n\t\t\t}\n\t\t\t#endif\n\t\t}\n\nrelease_plink_ctl:\n\t\t_exit_critical_bh(&(plink_ctl->lock), &irqL);\n\t}\n\nmpm_log:\n\trtw_mpm_info_msg(&mpm_info, mpm_log_buf);\n\tRTW_INFO(\"RTW_%s:%s %s\\n\"\n\t\t, (tx == _TRUE) ? \"Tx\" : \"Rx\"\n\t\t, action_self_protected_str(action)\n\t\t, mpm_log_buf\n\t);\n\n\tret = 1;\n\nexit:\n\tif (nbuf) {\n\t\tif (ret == 1) {\n\t\t\t*buf = nbuf;\n\t\t\t*len = nlen;\n\t\t} else\n\t\t\trtw_mfree(nbuf, nlen);\n\t}\n\n\treturn ret;\n}\n\nstatic int rtw_mesh_check_frames(_adapter *adapter, const u8 **buf, size_t *len, u8 tx)\n{\n\tint is_mesh_frame = -1;\n\tconst u8 *frame_body;\n\tu8 category, action;\n\n\tframe_body = *buf + sizeof(struct rtw_ieee80211_hdr_3addr);\n\tcategory = frame_body[0];\n\n\tif (category == RTW_WLAN_CATEGORY_SELF_PROTECTED) {\n\t\taction = frame_body[1];\n\t\tswitch (action) {\n\t\tcase RTW_ACT_SELF_PROTECTED_MESH_OPEN:\n\t\tcase RTW_ACT_SELF_PROTECTED_MESH_CONF:\n\t\tcase RTW_ACT_SELF_PROTECTED_MESH_CLOSE:\n\t\t\trtw_mpm_check_frames(adapter, action, buf, len, tx);\n\t\t\tis_mesh_frame = action;\n\t\t\tbreak;\n\t\tcase RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM:\n\t\tcase RTW_ACT_SELF_PROTECTED_MESH_GK_ACK:\n\t\t\tRTW_INFO(\"RTW_%s:%s\\n\", (tx == _TRUE) ? \"Tx\" : \"Rx\", action_self_protected_str(action));\n\t\t\tis_mesh_frame = action;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t};\n\t}\n\n\treturn is_mesh_frame;\n}\n\nint rtw_mesh_check_frames_tx(_adapter *adapter, const u8 **buf, size_t *len)\n{\n\treturn rtw_mesh_check_frames(adapter, buf, len, _TRUE);\n}\n\nint rtw_mesh_check_frames_rx(_adapter *adapter, const u8 *buf, size_t len)\n{\n\treturn rtw_mesh_check_frames(adapter, &buf, &len, _FALSE);\n}\n\nint rtw_mesh_on_auth(_adapter *adapter, union recv_frame *rframe)\n{\n\tu8 *whdr = rframe->u.hdr.rx_data;\n\n#if CONFIG_RTW_MACADDR_ACL\n\tif (rtw_access_ctrl(adapter, get_addr2_ptr(whdr)) == _FALSE)\n\t\treturn _SUCCESS;\n#endif\n\n\tif (!rtw_mesh_plink_get(adapter, get_addr2_ptr(whdr))) {\n\t\t#if CONFIG_RTW_MESH_ACNODE_PREVENT\n\t\trtw_mesh_acnode_set_notify_etime(adapter, whdr);\n\t\t#endif\n\n\t\tif (adapter_to_rfctl(adapter)->offch_state == OFFCHS_NONE)\n\t\t\tissue_probereq(adapter, &adapter->mlmepriv.cur_network.network.mesh_id, get_addr2_ptr(whdr));\n\n\t\t/* only peer being added (checked by notify conditions) is allowed */\n\t\treturn _SUCCESS;\n\t}\n\n\trtw_cfg80211_rx_mframe(adapter, rframe, NULL);\n\treturn _SUCCESS;\n}\n\nunsigned int on_action_self_protected(_adapter *adapter, union recv_frame *rframe)\n{\n\tunsigned int ret = _FAIL;\n\tstruct sta_info *sta = NULL;\n\tu8 *pframe = rframe->u.hdr.rx_data;\n\tuint frame_len = rframe->u.hdr.len;\n\tu8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));\n\tu8 category;\n\tu8 action;\n\n\t/* check RA matches or not */\n\tif (!_rtw_memcmp(adapter_mac_addr(adapter), GetAddr1Ptr(pframe), ETH_ALEN))\n\t\tgoto exit;\n\n\tcategory = frame_body[0];\n\tif (category != RTW_WLAN_CATEGORY_SELF_PROTECTED)\n\t\tgoto exit;\n\n\taction = frame_body[1];\n\tswitch (action) {\n\tcase RTW_ACT_SELF_PROTECTED_MESH_OPEN:\n\tcase RTW_ACT_SELF_PROTECTED_MESH_CONF:\n\tcase RTW_ACT_SELF_PROTECTED_MESH_CLOSE:\n\tcase RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM:\n\tcase RTW_ACT_SELF_PROTECTED_MESH_GK_ACK:\n\t\tif (!(MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)))\n\t\t\tgoto exit;\n#ifdef CONFIG_IOCTL_CFG80211\n\t\t#if CONFIG_RTW_MACADDR_ACL\n\t\tif (rtw_access_ctrl(adapter, get_addr2_ptr(pframe)) == _FALSE)\n\t\t\tgoto exit;\n\t\t#endif\n\t\t#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\t\tif (rtw_mesh_cto_mgate_required(adapter)\n\t\t\t/* only peer being added (checked by notify conditions) is allowed */\n\t\t\t&& !rtw_mesh_plink_get(adapter, get_addr2_ptr(pframe)))\n\t\t\tgoto exit;\n\t\t#endif\n\t\trtw_cfg80211_rx_action(adapter, rframe, NULL);\n\t\tret = _SUCCESS;\n#endif /* CONFIG_IOCTL_CFG80211 */\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\nexit:\n\treturn ret;\n}\n\nconst u8 ae_to_mesh_ctrl_len[] = {\n\t6,\n\t12, /* MESH_FLAGS_AE_A4 */\n\t18, /* MESH_FLAGS_AE_A5_A6 */\n\t0,\n};\n\nunsigned int on_action_mesh(_adapter *adapter, union recv_frame *rframe)\n{\n\tunsigned int ret = _FAIL;\n\tstruct sta_info *sta = NULL;\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tu8 *pframe = rframe->u.hdr.rx_data;\n\tuint frame_len = rframe->u.hdr.len;\n\tu8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));\n\tu8 category;\n\tu8 action;\n\n\tif (!MLME_IS_MESH(adapter))\n\t\tgoto exit;\n\n\t/* check stainfo exist? */\n\n\tcategory = frame_body[0];\n\tif (category != RTW_WLAN_CATEGORY_MESH)\n\t\tgoto exit;\n\n\taction = frame_body[1];\n\tswitch (action) {\n\tcase RTW_ACT_MESH_HWMP_PATH_SELECTION:\n\t\trtw_mesh_rx_path_sel_frame(adapter, rframe);\n\t\tret = _SUCCESS;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\nexit:\n\treturn ret;\n}\n\nbool rtw_mesh_update_bss_peering_status(_adapter *adapter, WLAN_BSSID_EX *bss)\n{\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tu8 num_of_peerings = stapriv->asoc_list_cnt;\n\tbool accept_peerings = stapriv->asoc_list_cnt < mcfg->max_peer_links;\n\tu8 *ie;\n\tint ie_len;\n\tbool updated = 0;\n\n#if CONFIG_RTW_MESH_ACNODE_PREVENT\n\taccept_peerings |= plink_ctl->acnode_rsvd;\n#endif\n\n\tie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len, BSS_EX_TLV_IES_LEN(bss));\n\tif (!ie || ie_len != 7) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (GET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2) != num_of_peerings) {\n\t\tSET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2, num_of_peerings);\n\t\tupdated = 1;\n\t}\n\n\tif (GET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2) != accept_peerings) {\n\t\tSET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2, accept_peerings);\n\t\tupdated = 1;\n\t}\n\nexit:\n\treturn updated;\n}\n\nbool rtw_mesh_update_bss_formation_info(_adapter *adapter, WLAN_BSSID_EX *bss)\n{\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tu8 cto_mgate = (minfo->num_gates || mcfg->dot11MeshGateAnnouncementProtocol);\n\tu8 cto_as = 0;\n\tu8 *ie;\n\tint ie_len;\n\tbool updated = 0;\n\n\tie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,\n\t\t\tBSS_EX_TLV_IES_LEN(bss));\n\tif (!ie || ie_len != 7) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (GET_MESH_CONF_ELE_CTO_MGATE(ie + 2) != cto_mgate) {\n\t\tSET_MESH_CONF_ELE_CTO_MGATE(ie + 2, cto_mgate);\n\t\tupdated = 1;\n\t}\n\n\tif (GET_MESH_CONF_ELE_CTO_AS(ie + 2) != cto_as) {\n\t\tSET_MESH_CONF_ELE_CTO_AS(ie + 2, cto_as);\n\t\tupdated = 1;\n\t}\n\nexit:\n\treturn updated;\n}\n\nbool rtw_mesh_update_bss_forwarding_state(_adapter *adapter, WLAN_BSSID_EX *bss)\n{\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tu8 forward = mcfg->dot11MeshForwarding;\n\tu8 *ie;\n\tint ie_len;\n\tbool updated = 0;\n\n\tie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,\n\t\t\tBSS_EX_TLV_IES_LEN(bss));\n\tif (!ie || ie_len != 7) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (GET_MESH_CONF_ELE_FORWARDING(ie + 2) != forward) {\n\t\tSET_MESH_CONF_ELE_FORWARDING(ie + 2, forward);\n\t\tupdated = 1;\n\t}\n\nexit:\n\treturn updated;\n}\n\nstruct mesh_plink_ent *_rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tstruct mesh_plink_ent *ent = NULL;\n\tint i;\n\n\tfor (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {\n\t\tif (plink_ctl->ent[i].valid == _TRUE\n\t\t\t&& _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE\n\t\t) {\n\t\t\tent = &plink_ctl->ent[i];\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn ent;\n}\n\nstruct mesh_plink_ent *rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tstruct mesh_plink_ent *ent = NULL;\n\t_irqL irqL;\n\n\t_enter_critical_bh(&(plink_ctl->lock), &irqL);\n\tent = _rtw_mesh_plink_get(adapter, hwaddr);\n\t_exit_critical_bh(&(plink_ctl->lock), &irqL);\n\n\treturn ent;\n}\n\nstruct mesh_plink_ent *rtw_mesh_plink_get_no_estab_by_idx(_adapter *adapter, u8 idx)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tstruct mesh_plink_ent *ent = NULL;\n\tint i, j = 0;\n\t_irqL irqL;\n\n\t_enter_critical_bh(&(plink_ctl->lock), &irqL);\n\tfor (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {\n\t\tif (plink_ctl->ent[i].valid == _TRUE\n\t\t\t&& plink_ctl->ent[i].plink_state != RTW_MESH_PLINK_ESTAB\n\t\t) {\n\t\t\tif (j == idx) {\n\t\t\t\tent = &plink_ctl->ent[i];\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tj++;\n\t\t}\n\t}\n\t_exit_critical_bh(&(plink_ctl->lock), &irqL);\n\n\treturn ent;\n}\n\nint _rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tstruct mesh_plink_ent *ent = NULL;\n\tu8 exist = _FALSE;\n\tint i;\n\n\tfor (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {\n\t\tif (plink_ctl->ent[i].valid == _TRUE\n\t\t\t&& _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE\n\t\t) {\n\t\t\tent = &plink_ctl->ent[i];\n\t\t\texist = _TRUE;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (ent == NULL && plink_ctl->ent[i].valid == _FALSE)\n\t\t\tent = &plink_ctl->ent[i];\n\t}\n\n\tif (exist == _FALSE && ent) {\n\t\t_rtw_memcpy(ent->addr, hwaddr, ETH_ALEN);\n\t\tent->valid = _TRUE;\n\t\t#ifdef CONFIG_RTW_MESH_AEK\n\t\tent->aek_valid = 0;\n\t\t#endif\n\t\tent->llid = 0;\n\t\tent->plid = 0;\n\t\t_rtw_memset(ent->chosen_pmk, 0, 16);\n\t\t#ifdef CONFIG_RTW_MESH_AEK\n\t\t_rtw_memset(ent->sel_pcs, 0, 4);\n\t\t_rtw_memset(ent->l_nonce, 0, 32);\n\t\t_rtw_memset(ent->p_nonce, 0, 32);\n\t\t#endif\n\t\tent->plink_state = RTW_MESH_PLINK_LISTEN;\n\t\t#ifndef CONFIG_RTW_MESH_DRIVER_AID\n\t\tent->aid = 0;\n\t\t#endif\n\t\tent->peer_aid = 0;\n\t\tSET_PEER_CONF_DISABLED(ent);\n\t\tSET_CTO_MGATE_CONF_DISABLED(ent);\n\t\tplink_ctl->num++;\n\t}\n\n\treturn exist == _TRUE ? RTW_ALREADY : (ent ? _SUCCESS : _FAIL);\n}\n\nint rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\t_irqL irqL;\n\tint ret;\n\n\t_enter_critical_bh(&(plink_ctl->lock), &irqL);\n\tret = _rtw_mesh_plink_add(adapter, hwaddr);\n\t_exit_critical_bh(&(plink_ctl->lock), &irqL);\n\n\treturn ret;\n}\n\nint rtw_mesh_plink_set_state(_adapter *adapter, const u8 *hwaddr, u8 state)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tstruct mesh_plink_ent *ent = NULL;\n\t_irqL irqL;\n\n\t_enter_critical_bh(&(plink_ctl->lock), &irqL);\n\tent = _rtw_mesh_plink_get(adapter, hwaddr);\n\tif (ent)\n\t\tent->plink_state = state;\n\t_exit_critical_bh(&(plink_ctl->lock), &irqL);\n\n\treturn ent ? _SUCCESS : _FAIL;\n}\n\n#ifdef CONFIG_RTW_MESH_AEK\nint rtw_mesh_plink_set_aek(_adapter *adapter, const u8 *hwaddr, const u8 *aek)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tstruct mesh_plink_ent *ent = NULL;\n\t_irqL irqL;\n\n\t_enter_critical_bh(&(plink_ctl->lock), &irqL);\n\tent = _rtw_mesh_plink_get(adapter, hwaddr);\n\tif (ent) {\n\t\t_rtw_memcpy(ent->aek, aek, 32);\n\t\tent->aek_valid = 1;\n\t}\n\t_exit_critical_bh(&(plink_ctl->lock), &irqL);\n\n\treturn ent ? _SUCCESS : _FAIL;\n}\n#endif\n\n#if CONFIG_RTW_MESH_PEER_BLACKLIST\nint rtw_mesh_plink_set_peer_conf_timeout(_adapter *adapter, const u8 *hwaddr)\n{\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tstruct mesh_plink_ent *ent = NULL;\n\t_irqL irqL;\n\n\t_enter_critical_bh(&(plink_ctl->lock), &irqL);\n\tent = _rtw_mesh_plink_get(adapter, hwaddr);\n\tif (ent) {\n\t\tif (IS_PEER_CONF_DISABLED(ent))\n\t\t\tSET_PEER_CONF_END_TIME(ent, mcfg->peer_sel_policy.peer_conf_timeout_ms);\n\t}\n\t_exit_critical_bh(&(plink_ctl->lock), &irqL);\n\n\treturn ent ? _SUCCESS : _FAIL;\n}\n#endif\n\nvoid _rtw_mesh_plink_del_ent(_adapter *adapter, struct mesh_plink_ent *ent)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\n\tent->valid = _FALSE;\n\t#ifdef CONFIG_RTW_MESH_DRIVER_AID\n\tif (ent->tx_conf_ies && ent->tx_conf_ies_len)\n\t\trtw_mfree(ent->tx_conf_ies, ent->tx_conf_ies_len);\n\tent->tx_conf_ies = NULL;\n\tent->tx_conf_ies_len = 0;\n\t#endif\n\tif (ent->rx_conf_ies && ent->rx_conf_ies_len)\n\t\trtw_mfree(ent->rx_conf_ies, ent->rx_conf_ies_len);\n\tent->rx_conf_ies = NULL;\n\tent->rx_conf_ies_len = 0;\n\tif (ent->scanned)\n\t\tent->scanned = NULL;\n\tplink_ctl->num--;\n}\n\nint rtw_mesh_plink_del(_adapter *adapter, const u8 *hwaddr)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tstruct mesh_plink_ent *ent = NULL;\n\tu8 exist = _FALSE;\n\tint i;\n\t_irqL irqL;\n\n\t_enter_critical_bh(&(plink_ctl->lock), &irqL);\n\tfor (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {\n\t\tif (plink_ctl->ent[i].valid == _TRUE\n\t\t\t&& _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE\n\t\t) {\n\t\t\tent = &plink_ctl->ent[i];\n\t\t\texist = _TRUE;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (exist == _TRUE)\n\t\t_rtw_mesh_plink_del_ent(adapter, ent);\n\n\t_exit_critical_bh(&(plink_ctl->lock), &irqL);\n\n\treturn exist == _TRUE ? _SUCCESS : RTW_ALREADY;\n}\n\nvoid rtw_mesh_plink_ctl_init(_adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tint i;\n\n\t_rtw_spinlock_init(&plink_ctl->lock);\n\tplink_ctl->num = 0;\n\tfor (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++)\n\t\tplink_ctl->ent[i].valid = _FALSE;\n\n#if CONFIG_RTW_MESH_PEER_BLACKLIST\n\t_rtw_init_queue(&plink_ctl->peer_blacklist);\n#endif\n#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\t_rtw_init_queue(&plink_ctl->cto_mgate_blacklist);\n#endif\n}\n\nvoid rtw_mesh_plink_ctl_deinit(_adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tstruct mesh_plink_ent *ent;\n\tint i;\n\t_irqL irqL;\n\n\t_enter_critical_bh(&(plink_ctl->lock), &irqL);\n\tfor (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {\n\t\tent = &plink_ctl->ent[i];\n\t\t#ifdef CONFIG_RTW_MESH_DRIVER_AID\n\t\tif (ent->tx_conf_ies && ent->tx_conf_ies_len)\n\t\t\trtw_mfree(ent->tx_conf_ies, ent->tx_conf_ies_len);\n\t\t#endif\n\t\tif (ent->rx_conf_ies && ent->rx_conf_ies_len)\n\t\t\trtw_mfree(ent->rx_conf_ies, ent->rx_conf_ies_len);\n\t}\n\t_exit_critical_bh(&(plink_ctl->lock), &irqL);\n\n\t_rtw_spinlock_free(&plink_ctl->lock);\n\n#if CONFIG_RTW_MESH_PEER_BLACKLIST\n\trtw_mesh_peer_blacklist_flush(adapter);\n\t_rtw_deinit_queue(&plink_ctl->peer_blacklist);\n#endif\n#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\trtw_mesh_cto_mgate_blacklist_flush(adapter);\n\t_rtw_deinit_queue(&plink_ctl->cto_mgate_blacklist);\n#endif\n}\n\nvoid dump_mesh_plink_ctl(void *sel, _adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tstruct mesh_plink_ent *ent;\n\tint i;\n\n\tRTW_PRINT_SEL(sel, \"num:%u\\n\", plink_ctl->num);\n\t#if CONFIG_RTW_MESH_ACNODE_PREVENT\n\tRTW_PRINT_SEL(sel, \"acnode_rsvd:%u\\n\", plink_ctl->acnode_rsvd);\n\t#endif\n\n\tfor (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++)  {\n\t\tent = &plink_ctl->ent[i];\n\t\tif (!ent->valid)\n\t\t\tcontinue;\n\n\t\tRTW_PRINT_SEL(sel, \"\\n\");\n\t\tRTW_PRINT_SEL(sel, \"peer:\"MAC_FMT\"\\n\", MAC_ARG(ent->addr));\n\t\tRTW_PRINT_SEL(sel, \"plink_state:%s\\n\", rtw_mesh_plink_str(ent->plink_state));\n\n\t\t#ifdef CONFIG_RTW_MESH_AEK\n\t\tif (ent->aek_valid)\n\t\t\tRTW_PRINT_SEL(sel, \"aek:\"KEY_FMT KEY_FMT\"\\n\", KEY_ARG(ent->aek), KEY_ARG(ent->aek + 16));\n\t\t#endif\n\n\t\tRTW_PRINT_SEL(sel, \"llid:%u, plid:%u\\n\", ent->llid, ent->plid);\n\t\t#ifndef CONFIG_RTW_MESH_DRIVER_AID\n\t\tRTW_PRINT_SEL(sel, \"aid:%u\\n\", ent->aid);\n\t\t#endif\n\t\tRTW_PRINT_SEL(sel, \"peer_aid:%u\\n\", ent->peer_aid);\n\n\t\tRTW_PRINT_SEL(sel, \"chosen_pmk:\"KEY_FMT\"\\n\", KEY_ARG(ent->chosen_pmk));\n\n\t\t#ifdef CONFIG_RTW_MESH_AEK\n\t\tRTW_PRINT_SEL(sel, \"sel_pcs:%02x%02x%02x%02x\\n\"\n\t\t\t, ent->sel_pcs[0], ent->sel_pcs[1], ent->sel_pcs[2], ent->sel_pcs[3]);\n\t\tRTW_PRINT_SEL(sel, \"l_nonce:\"KEY_FMT KEY_FMT\"\\n\", KEY_ARG(ent->l_nonce), KEY_ARG(ent->l_nonce + 16));\n\t\tRTW_PRINT_SEL(sel, \"p_nonce:\"KEY_FMT KEY_FMT\"\\n\", KEY_ARG(ent->p_nonce), KEY_ARG(ent->p_nonce + 16));\n\t\t#endif\n\n\t\t#ifdef CONFIG_RTW_MESH_DRIVER_AID\n\t\tRTW_PRINT_SEL(sel, \"tx_conf_ies:%p, len:%u\\n\", ent->tx_conf_ies, ent->tx_conf_ies_len);\n\t\t#endif\n\t\tRTW_PRINT_SEL(sel, \"rx_conf_ies:%p, len:%u\\n\", ent->rx_conf_ies, ent->rx_conf_ies_len);\n\t\tRTW_PRINT_SEL(sel, \"scanned:%p\\n\", ent->scanned);\n\n\t\t#if CONFIG_RTW_MESH_PEER_BLACKLIST\n\t\tif (!IS_PEER_CONF_DISABLED(ent)) {\n\t\t\tif (!IS_PEER_CONF_TIMEOUT(ent))\n\t\t\t\tRTW_PRINT_SEL(sel, \"peer_conf:%d\\n\", rtw_systime_to_ms(ent->peer_conf_end_time - rtw_get_current_time()));\n\t\t\telse\n\t\t\t\tRTW_PRINT_SEL(sel, \"peer_conf:TIMEOUT\\n\");\n\t\t}\n\t\t#endif\n\n\t\t#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\t\tif (!IS_CTO_MGATE_CONF_DISABLED(ent)) {\n\t\t\tif (!IS_CTO_MGATE_CONF_TIMEOUT(ent))\n\t\t\t\tRTW_PRINT_SEL(sel, \"cto_mgate_conf:%d\\n\", rtw_systime_to_ms(ent->cto_mgate_conf_end_time - rtw_get_current_time()));\n\t\t\telse\n\t\t\t\tRTW_PRINT_SEL(sel, \"cto_mgate_conf:TIMEOUT\\n\");\n\t\t}\n\t\t#endif\n\t}\n}\n\n/* this function is called with plink_ctl being locked */\nint rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *plink, struct sta_info *sta)\n{\n#ifndef DBG_RTW_MESH_PEER_ESTABLISH\n#define DBG_RTW_MESH_PEER_ESTABLISH 0\n#endif\n\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tu8 *tlv_ies;\n\tu16 tlv_ieslen;\n\tstruct rtw_ieee802_11_elems elems;\n\t_irqL irqL;\n\tint i;\n\tint ret = _FAIL;\n\n\tif (!plink->rx_conf_ies || !plink->rx_conf_ies_len) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" no rx confirm from sta \"MAC_FMT\"\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));\n\t\tgoto exit;\n\t}\n\n\tif (plink->rx_conf_ies_len < 4) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" confirm from sta \"MAC_FMT\" too short\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));\n\t\tgoto exit;\n\t}\n\n#ifdef CONFIG_RTW_MESH_DRIVER_AID\n\tif (!plink->tx_conf_ies || !plink->tx_conf_ies_len) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" no tx confirm to sta \"MAC_FMT\"\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));\n\t\tgoto exit;\n\t}\n\n\tif (plink->tx_conf_ies_len < 4) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" confirm to sta \"MAC_FMT\" too short\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));\n\t\tgoto exit;\n\t}\n#endif\n\n\ttlv_ies = plink->rx_conf_ies + 4;\n\ttlv_ieslen = plink->rx_conf_ies_len - 4;\n\n\tif (DBG_RTW_MESH_PEER_ESTABLISH)\n\t\tdump_ies(RTW_DBGDUMP, tlv_ies, tlv_ieslen);\n\n\tif (rtw_ieee802_11_parse_elems(tlv_ies, tlv_ieslen, &elems, 1) == ParseFailed) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" sta \"MAC_FMT\" sent invalid confirm\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));\n\t\tgoto exit;\n\t}\n\n\tSET_PEER_CONF_DISABLED(plink);\n\tif (rtw_bss_is_cto_mgate(&plink->scanned->network)\n\t\t&& !rtw_bss_is_forwarding(&plink->scanned->network))\n\t\tSET_CTO_MGATE_CONF_END_TIME(plink, mcfg->peer_sel_policy.cto_mgate_conf_timeout_ms);\n\telse\n\t\tSET_CTO_MGATE_CONF_DISABLED(plink);\n\n\tsta->state &= (~WIFI_FW_AUTH_SUCCESS);\n\tsta->state |= WIFI_FW_ASSOC_STATE;\n\n\trtw_ap_parse_sta_capability(adapter, sta, plink->rx_conf_ies);\n\n\tif (rtw_ap_parse_sta_supported_rates(adapter, sta, tlv_ies, tlv_ieslen) != _STATS_SUCCESSFUL_)\n\t\tgoto exit;\n\t\n\tif (rtw_ap_parse_sta_security_ie(adapter, sta, &elems) != _STATS_SUCCESSFUL_)\n\t\tgoto exit;\n\n\trtw_ap_parse_sta_wmm_ie(adapter, sta, tlv_ies, tlv_ieslen);\n#ifdef CONFIG_RTS_FULL_BW\n\t/*check vendor IE*/\n\trtw_parse_sta_vendor_ie_8812(adapter, sta, tlv_ies, tlv_ieslen);\n#endif/*CONFIG_RTS_FULL_BW*/\n\n\trtw_ap_parse_sta_ht_ie(adapter, sta, &elems);\n\trtw_ap_parse_sta_vht_ie(adapter, sta, &elems);\n\n\t/* AID */\n#ifdef CONFIG_RTW_MESH_DRIVER_AID\n\tsta->cmn.aid = RTW_GET_LE16(plink->tx_conf_ies + 2);\n#else\n\tsta->cmn.aid = plink->aid;\n#endif\n\tstapriv->sta_aid[sta->cmn.aid - 1] = sta;\n\tRTW_INFO(FUNC_ADPT_FMT\" sta \"MAC_FMT\" aid:%u\\n\"\n\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr), sta->cmn.aid);\n\n\tsta->state &= (~WIFI_FW_ASSOC_STATE);\n\tsta->state |= WIFI_FW_ASSOC_SUCCESS;\n\n\tsta->local_mps = RTW_MESH_PS_ACTIVE;\n\n\trtw_ewma_err_rate_init(&sta->metrics.err_rate);\n\trtw_ewma_err_rate_add(&sta->metrics.err_rate, 1);\n\t/* init data_rate to 1M */\n\tsta->metrics.data_rate = 10;\n\tsta->alive = _TRUE;\n\n\t_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);\n\tif (rtw_is_list_empty(&sta->asoc_list)) {\n\t\tSTA_SET_MESH_PLINK(sta, plink);\n\t\t/* TBD: up layer timeout mechanism */\n\t\t/* sta->expire_to = mcfg->plink_timeout / 2; */\n\t\trtw_list_insert_tail(&sta->asoc_list, &stapriv->asoc_list);\n\t\tstapriv->asoc_list_cnt++;\n\t}\n\t_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);\n\n\tbss_cap_update_on_sta_join(adapter, sta);\n\tsta_info_update(adapter, sta);\n\treport_add_sta_event(adapter, sta->cmn.mac_addr);\n\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n\nvoid rtw_mesh_expire_peer_notify(_adapter *adapter, const u8 *peer_addr)\n{\n\tu8 null_ssid[2] = {0, 0};\n\n#ifdef CONFIG_IOCTL_CFG80211\n\trtw_cfg80211_notify_new_peer_candidate(adapter->rtw_wdev\n\t\t, peer_addr\n\t\t, null_ssid\n\t\t, 2\n\t\t, 0\n\t\t, GFP_ATOMIC\n\t);\n#endif\n\n\treturn;\n}\n\nstatic u8 *rtw_mesh_construct_peer_mesh_close(_adapter *adapter, struct mesh_plink_ent *plink, u16 reason, u32 *len)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tu8 *frame = NULL, *pos;\n\tu32 flen;\n\tstruct rtw_ieee80211_hdr *whdr;\n\n\tif (minfo->mesh_auth_id && !MESH_PLINK_AEK_VALID(plink))\n\t\tgoto exit;\n\n\tflen = sizeof(struct rtw_ieee80211_hdr_3addr)\n\t\t+ 2 /* category, action */\n\t\t+ 2 + minfo->mesh_id_len /* mesh id */\n\t\t+ 2 + 8 + (minfo->mesh_auth_id ? 16 : 0) /* mpm */\n\t\t+ (minfo->mesh_auth_id ? 2 + AES_BLOCK_SIZE : 0) /* mic */\n\t\t+ (minfo->mesh_auth_id ? 70 : 0) /* ampe */\n\t\t;\n\n\tpos = frame = rtw_zmalloc(flen);\n\tif (!frame)\n\t\tgoto exit;\n\n\twhdr = (struct rtw_ieee80211_hdr *)frame;\n\t_rtw_memcpy(whdr->addr1, adapter_mac_addr(adapter), ETH_ALEN);\n\t_rtw_memcpy(whdr->addr2, plink->addr, ETH_ALEN);\n\t_rtw_memcpy(whdr->addr3, adapter_mac_addr(adapter), ETH_ALEN);\n\n\tset_frame_sub_type(frame, WIFI_ACTION);\n\n\tpos += sizeof(struct rtw_ieee80211_hdr_3addr);\n\t*(pos++) = RTW_WLAN_CATEGORY_SELF_PROTECTED;\n\t*(pos++) = RTW_ACT_SELF_PROTECTED_MESH_CLOSE;\n\n\tpos = rtw_set_ie_mesh_id(pos, NULL, minfo->mesh_id, minfo->mesh_id_len);\n\n\tpos = rtw_set_ie_mpm(pos, NULL\n\t\t, minfo->mesh_auth_id ? 1 : 0\n\t\t, plink->plid\n\t\t, &plink->llid\n\t\t, &reason\n\t\t, minfo->mesh_auth_id ? plink->chosen_pmk : NULL);\n\n#ifdef CONFIG_RTW_MESH_AEK\n\tif (minfo->mesh_auth_id) {\n\t\tu8 ampe_buf[70];\n\t\tint enc_ret;\n\n\t\t*pos = WLAN_EID_MIC;\n\t\t*(pos + 1) = AES_BLOCK_SIZE;\n\n\t\tampe_buf[0] = WLAN_EID_AMPE;\n\t\tampe_buf[1] = 68;\n\t\t_rtw_memcpy(ampe_buf + 2, plink->sel_pcs, 4);\n\t\t_rtw_memcpy(ampe_buf + 6, plink->p_nonce, 32);\n\t\t_rtw_memcpy(ampe_buf + 38, plink->l_nonce, 32);\n\n\t\tenc_ret = rtw_mpm_ampe_enc(adapter, plink\n\t\t\t, frame + sizeof(struct rtw_ieee80211_hdr_3addr)\n\t\t\t, pos, ampe_buf, 1);\n\t\tif (enc_ret != _SUCCESS) {\n\t\t\trtw_mfree(frame, flen);\n\t\t\tframe = NULL;\n\t\t\tgoto exit;\n\t\t}\n\t}\n#endif\n\n\t*len = flen;\n\nexit:\n\treturn frame;\n}\n\nvoid _rtw_mesh_expire_peer_ent(_adapter *adapter, struct mesh_plink_ent *plink)\n{\n#if defined(CONFIG_RTW_MESH_STA_DEL_DISASOC)\n\t_rtw_mesh_plink_del_ent(adapter, plink);\n\trtw_cfg80211_indicate_sta_disassoc(adapter, plink->addr, 0);\n#else\n\tu8 *frame = NULL;\n\tu32 flen;\n\n\tif (plink->plink_state == RTW_MESH_PLINK_ESTAB)\n\t\tframe = rtw_mesh_construct_peer_mesh_close(adapter, plink, WLAN_REASON_MESH_CLOSE, &flen);\n\n\tif (frame) {\n\t\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\t\tstruct wireless_dev *wdev = adapter->rtw_wdev;\n\t\ts32 freq = rtw_ch2freq(mlmeext->cur_channel);\n\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\t\trtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, flen, GFP_ATOMIC);\n\t\t#else\n\t\tcfg80211_rx_action(adapter->pnetdev, freq, frame, flen, GFP_ATOMIC);\n\t\t#endif\n\n\t\trtw_mfree(frame, flen);\n\t} else {\n\t\trtw_mesh_expire_peer_notify(adapter, plink->addr);\n\t\tRTW_INFO(FUNC_ADPT_FMT\" set \"MAC_FMT\" plink unknown\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(plink->addr));\n\t\tplink->plink_state = RTW_MESH_PLINK_UNKNOWN;\n\t}\n#endif\n}\n\nvoid rtw_mesh_expire_peer(_adapter *adapter, const u8 *peer_addr)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\tstruct mesh_plink_ent *plink;\n\t_irqL irqL;\n\n\t_enter_critical_bh(&(plink_ctl->lock), &irqL);\n\n\tplink = _rtw_mesh_plink_get(adapter, peer_addr);\n\tif (!plink)\n\t\tgoto exit;\n\n\t_rtw_mesh_expire_peer_ent(adapter, plink);\n\nexit:\n\t_exit_critical_bh(&(plink_ctl->lock), &irqL);\n}\n\nu8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps)\n{\n\t_irqL irqL;\n\t_list *head, *list;\n\tstruct sta_info *sta;\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tu8 sta_alive_num = 0, i;\n\tchar sta_alive_list[NUM_STA];\n\tu8 annc_cnt = 0;\n\n\tif (rtw_linked_check(adapter) == _FALSE)\n\t\tgoto exit;\n\n\t_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);\n\n\thead = &stapriv->asoc_list;\n\tlist = get_next(head);\n\twhile ((rtw_end_of_queue_search(head, list)) == _FALSE) {\n\t\tint stainfo_offset;\n\n\t\tsta = LIST_CONTAINOR(list, struct sta_info, asoc_list);\n\t\tlist = get_next(list);\n\n\t\tstainfo_offset = rtw_stainfo_offset(stapriv, sta);\n\t\tif (stainfo_offset_valid(stainfo_offset))\n\t\t\tsta_alive_list[sta_alive_num++] = stainfo_offset;\n\t}\n\t_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);\n\n\tfor (i = 0; i < sta_alive_num; i++) {\n\t\tsta = rtw_get_stainfo_by_offset(stapriv, sta_alive_list[i]);\n\t\tif (!sta)\n\t\t\tcontinue;\n\n\t\tissue_qos_nulldata(adapter, sta->cmn.mac_addr, 7, ps, 3, 500);\n\t\tannc_cnt++;\n\t}\n\nexit:\n\treturn annc_cnt;\n}\n\nstatic void mpath_tx_tasklet_hdl(void *priv)\n{\n\t_adapter *adapter = (_adapter *)priv;\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct xmit_frame *xframe;\n\t_list *list, *head;\n\t_list tmp;\n\tu32 tmp_len;\n\ts32 res;\n\n\t_rtw_init_listhead(&tmp);\n\n\twhile (1) {\n\t\ttmp_len = 0;\n\t\tenter_critical_bh(&minfo->mpath_tx_queue.lock);\n\t\tif (minfo->mpath_tx_queue_len) {\n\t\t\trtw_list_splice_init(&minfo->mpath_tx_queue.queue, &tmp);\n\t\t\ttmp_len = minfo->mpath_tx_queue_len;\n\t\t\tminfo->mpath_tx_queue_len = 0;\n\t\t}\n\t\texit_critical_bh(&minfo->mpath_tx_queue.lock);\n\n\t\tif (!tmp_len)\n\t\t\tbreak;\n\n\t\thead = &tmp;\n\t\tlist = get_next(head);\n\t\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\t\txframe = LIST_CONTAINOR(list, struct xmit_frame, list);\n\t\t\tlist = get_next(list);\n\t\t\trtw_list_delete(&xframe->list);\n\t\t\tres = rtw_xmit_posthandle(adapter, xframe, xframe->pkt);\n\t\t\tif (res < 0) {\n\t\t\t\t#ifdef DBG_TX_DROP_FRAME\n\t\t\t\tRTW_INFO(\"DBG_TX_DROP_FRAME %s rtw_xmit fail\\n\", __FUNCTION__);\n\t\t\t\t#endif\n\t\t\t\tadapter->xmitpriv.tx_drop++;\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic void rtw_mpath_tx_queue_flush(_adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct xmit_frame *xframe;\n\t_list *list, *head;\n\t_list tmp;\n\n\t_rtw_init_listhead(&tmp);\n\n\tenter_critical_bh(&minfo->mpath_tx_queue.lock);\n\trtw_list_splice_init(&minfo->mpath_tx_queue.queue, &tmp);\n\tminfo->mpath_tx_queue_len = 0;\n\texit_critical_bh(&minfo->mpath_tx_queue.lock);\n\n\thead = &tmp;\n\tlist = get_next(head);\n\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\txframe = LIST_CONTAINOR(list, struct xmit_frame, list);\n\t\tlist = get_next(list);\n\t\trtw_list_delete(&xframe->list);\n\t\trtw_free_xmitframe(&adapter->xmitpriv, xframe);\n\t}\n}\n\n#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */\n#if defined(CONFIG_SLUB)\n#include <linux/slub_def.h>\n#elif defined(CONFIG_SLAB)\n#include <linux/slab_def.h>\n#endif\ntypedef struct kmem_cache rtw_mcache;\n#endif\n\nrtw_mcache *rtw_mcache_create(const char *name, size_t size)\n{\n#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */\n\treturn kmem_cache_create(name, size, 0, 0, NULL);\n#else\n\t#error \"TBD\\n\";\n#endif\n}\n\nvoid rtw_mcache_destroy(rtw_mcache *s)\n{\n#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */\n\tkmem_cache_destroy(s);\n#else\n\t#error \"TBD\\n\";\n#endif\n}\n\nvoid *_rtw_mcache_alloc(rtw_mcache *cachep)\n{\n#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */\n\treturn kmem_cache_alloc(cachep, GFP_ATOMIC);\n#else\n\t#error \"TBD\\n\";\n#endif\n}\n\nvoid _rtw_mcache_free(rtw_mcache *cachep, void *objp)\n{\n#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */\n\tkmem_cache_free(cachep, objp);\n#else\n\t#error \"TBD\\n\";\n#endif\n}\n\n#ifdef DBG_MEM_ALLOC\ninline void *dbg_rtw_mcache_alloc(rtw_mcache *cachep, const enum mstat_f flags, const char *func, const int line)\n{\n\tvoid *p;\n\tu32 sz = cachep->size;\n\n\tif (match_mstat_sniff_rules(flags, sz))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s(%u)\\n\", func, line, __func__, sz);\n\n\tp = _rtw_mcache_alloc(cachep);\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL\n\t\t, sz\n\t);\n\n\treturn p;\n}\n\ninline void dbg_rtw_mcache_free(rtw_mcache *cachep, void *pbuf, const enum mstat_f flags, const char *func, const int line)\n{\n\tu32 sz = cachep->size;\n\n\tif (match_mstat_sniff_rules(flags, sz))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s(%u)\\n\", func, line, __func__, sz);\n\n\t_rtw_mcache_free(cachep, pbuf);\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, MSTAT_FREE\n\t\t, sz\n\t);\n}\n\n#define rtw_mcache_alloc(cachep) dbg_rtw_mcache_alloc(cachep, MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)\n#define rtw_mcache_free(cachep, objp) dbg_rtw_mcache_free(cachep, objp, MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)\n#else\n#define rtw_mcache_alloc(cachep) _rtw_mcache_alloc(cachep)\n#define rtw_mcache_free(cachep, objp) _rtw_mcache_free(cachep, objp)\n#endif /* DBG_MEM_ALLOC */\n\n/* Mesh Received Cache */\n#define RTW_MRC_BUCKETS\t\t\t256 /* must be a power of 2 */\n#define RTW_MRC_QUEUE_MAX_LEN\t4\n#define RTW_MRC_TIMEOUT_MS\t\t(3 * 1000)\n\n/**\n * struct rtw_mrc_entry - entry in the Mesh Received Cache\n *\n * @seqnum: mesh sequence number of the frame\n * @exp_time: expiration time of the entry\n * @msa: mesh source address of the frame\n * @list: hashtable list pointer\n *\n * The Mesh Received Cache keeps track of the latest received frames that\n * have been received by a mesh interface and discards received frames\n * that are found in the cache.\n */\nstruct rtw_mrc_entry {\n\trtw_hlist_node list;\n\tsystime exp_time;\n\tu32 seqnum;\n\tu8 msa[ETH_ALEN];\n};\n\nstruct rtw_mrc {\n\trtw_hlist_head bucket[RTW_MRC_BUCKETS];\n\tu32 idx_mask;\n\trtw_mcache *cache;\n};\n\nstatic int rtw_mrc_init(_adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tchar cache_name[IFNAMSIZ + 8 + 1];\n\tint i;\n\n\tminfo->mrc = rtw_malloc(sizeof(struct rtw_mrc));\n\tif (!minfo->mrc)\n\t\treturn -ENOMEM;\n\tminfo->mrc->idx_mask = RTW_MRC_BUCKETS - 1;\n\tfor (i = 0; i < RTW_MRC_BUCKETS; i++)\n\t\trtw_hlist_head_init(&minfo->mrc->bucket[i]);\n\n\tsprintf(cache_name, \"rtw_mrc_%s\", ADPT_ARG(adapter));\n\tminfo->mrc->cache = rtw_mcache_create(cache_name, sizeof(struct rtw_mrc_entry));\n\n\treturn 0;\n}\n\nstatic void rtw_mrc_free(_adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct rtw_mrc *mrc = minfo->mrc;\n\tstruct rtw_mrc_entry *p;\n\trtw_hlist_node *np, *n;\n\tint i;\n\n\tif (!mrc)\n\t\treturn;\n\n\tfor (i = 0; i < RTW_MRC_BUCKETS; i++) {\n\t\trtw_hlist_for_each_entry_safe(p, np, n, &mrc->bucket[i], list) {\n\t\t\trtw_hlist_del(&p->list);\n\t\t\trtw_mcache_free(mrc->cache, p);\n\t\t}\n\t}\n\n\trtw_mcache_destroy(mrc->cache);\n\n\trtw_mfree(mrc, sizeof(struct rtw_mrc));\n\tminfo->mrc = NULL;\n}\n\n/**\n * rtw_mrc_check - Check frame in mesh received cache and add if absent.\n *\n * @adapter:\tinterface\n * @msa:\t\tmesh source address\n * @seq:\t\tmesh seq number\n *\n * Returns: 0 if the frame is not in the cache, nonzero otherwise.\n *\n * Checks using the mesh source address and the mesh sequence number if we have\n * received this frame lately. If the frame is not in the cache, it is added to\n * it.\n */\nstatic int rtw_mrc_check(_adapter *adapter, const u8 *msa, u32 seq)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct rtw_mrc *mrc = minfo->mrc;\n\tint entries = 0;\n\tu8 idx;\n\tstruct rtw_mrc_entry *p;\n\trtw_hlist_node *np, *n;\n\tu8 timeout;\n\n\tif (!mrc)\n\t\treturn -1;\n\n\tidx = seq & mrc->idx_mask;\n\trtw_hlist_for_each_entry_safe(p, np, n, &mrc->bucket[idx], list) {\n\t\t++entries;\n\t\ttimeout = rtw_time_after(rtw_get_current_time(), p->exp_time);\n\t\tif (timeout || entries == RTW_MRC_QUEUE_MAX_LEN) {\n\t\t\tif (!timeout)\n\t\t\t\tminfo->mshstats.mrc_del_qlen++;\n\n\t\t\trtw_hlist_del(&p->list);\n\t\t\trtw_mcache_free(mrc->cache, p);\n\t\t\t--entries;\n\t\t} else if ((seq == p->seqnum) && _rtw_memcmp(msa, p->msa, ETH_ALEN) == _TRUE)\n\t\t\treturn -1;\n\t}\n\n\tp = rtw_mcache_alloc(mrc->cache);\n\tif (!p)\n\t\treturn 0;\n\n\tp->seqnum = seq;\n\tp->exp_time = rtw_get_current_time() + rtw_ms_to_systime(RTW_MRC_TIMEOUT_MS);\n\t_rtw_memcpy(p->msa, msa, ETH_ALEN);\n\trtw_hlist_add_head(&p->list, &mrc->bucket[idx]);\n\treturn 0;\n}\n\nstatic int rtw_mesh_decache(_adapter *adapter, const u8 *msa, u32 seq)\n{\n\treturn rtw_mrc_check(adapter, msa, seq);\n}\n\n#ifndef RTW_MESH_SCAN_RESULT_EXP_MS\n#define RTW_MESH_SCAN_RESULT_EXP_MS (10 * 1000)\n#endif\n\n#ifndef RTW_MESH_ACNODE_PREVENT\n#define RTW_MESH_ACNODE_PREVENT 0\n#endif\n#ifndef RTW_MESH_ACNODE_CONF_TIMEOUT_MS\n#define RTW_MESH_ACNODE_CONF_TIMEOUT_MS (20 * 1000)\n#endif\n#ifndef RTW_MESH_ACNODE_NOTIFY_TIMEOUT_MS\n#define RTW_MESH_ACNODE_NOTIFY_TIMEOUT_MS (2 * 1000)\n#endif\n\n#ifndef RTW_MESH_OFFCH_CAND\n#define RTW_MESH_OFFCH_CAND 1\n#endif\n#ifndef RTW_MESH_OFFCH_CAND_FIND_INT_MS\n#define RTW_MESH_OFFCH_CAND_FIND_INT_MS (10 * 1000)\n#endif\n\n#ifndef RTW_MESH_PEER_CONF_TIMEOUT_MS\n#define RTW_MESH_PEER_CONF_TIMEOUT_MS (20 * 1000)\n#endif\n#ifndef RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS\n#define RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS (20 * 1000)\n#endif\n\n#ifndef RTW_MESH_CTO_MGATE_REQUIRE\n#define RTW_MESH_CTO_MGATE_REQUIRE 0\n#endif\n#ifndef RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS\n#define RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS (20 * 1000)\n#endif\n#ifndef RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS\n#define RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS (20 * 1000)\n#endif\n\nvoid rtw_mesh_cfg_init_peer_sel_policy(struct rtw_mesh_cfg *mcfg)\n{\n\tstruct mesh_peer_sel_policy *sel_policy = &mcfg->peer_sel_policy;\n\n\tsel_policy->scanr_exp_ms = RTW_MESH_SCAN_RESULT_EXP_MS;\n\n#if CONFIG_RTW_MESH_ACNODE_PREVENT\n\tsel_policy->acnode_prevent = RTW_MESH_ACNODE_PREVENT;\n\tsel_policy->acnode_conf_timeout_ms = RTW_MESH_ACNODE_CONF_TIMEOUT_MS;\n\tsel_policy->acnode_notify_timeout_ms = RTW_MESH_ACNODE_NOTIFY_TIMEOUT_MS;\n#endif\n\n#if CONFIG_RTW_MESH_OFFCH_CAND\n\tsel_policy->offch_cand = RTW_MESH_OFFCH_CAND;\n\tsel_policy->offch_find_int_ms = RTW_MESH_OFFCH_CAND_FIND_INT_MS;\n#endif\n\n#if CONFIG_RTW_MESH_PEER_BLACKLIST\n\tsel_policy->peer_conf_timeout_ms = RTW_MESH_PEER_CONF_TIMEOUT_MS;\n\tsel_policy->peer_blacklist_timeout_ms = RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS;\n#endif\n\n#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\tsel_policy->cto_mgate_require = RTW_MESH_CTO_MGATE_REQUIRE;\n\tsel_policy->cto_mgate_conf_timeout_ms = RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS;\n\tsel_policy->cto_mgate_blacklist_timeout_ms = RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS;\n#endif\n}\n\nvoid rtw_mesh_cfg_init(_adapter *adapter)\n{\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\n\tmcfg->max_peer_links = RTW_MESH_MAX_PEER_LINKS;\n\tmcfg->plink_timeout = RTW_MESH_PEER_LINK_TIMEOUT;\n\n\tmcfg->dot11MeshTTL = RTW_MESH_TTL;\n\tmcfg->element_ttl = RTW_MESH_DEFAULT_ELEMENT_TTL;\n\tmcfg->dot11MeshHWMPmaxPREQretries = RTW_MESH_MAX_PREQ_RETRIES;\n\tmcfg->path_refresh_time = RTW_MESH_PATH_REFRESH_TIME;\n\tmcfg->min_discovery_timeout = RTW_MESH_MIN_DISCOVERY_TIMEOUT;\n\tmcfg->dot11MeshHWMPactivePathTimeout = RTW_MESH_PATH_TIMEOUT;\n\tmcfg->dot11MeshHWMPpreqMinInterval = RTW_MESH_PREQ_MIN_INT;\n\tmcfg->dot11MeshHWMPperrMinInterval = RTW_MESH_PERR_MIN_INT;\n\tmcfg->dot11MeshHWMPnetDiameterTraversalTime = RTW_MESH_DIAM_TRAVERSAL_TIME;\n\tmcfg->dot11MeshHWMPRootMode = RTW_IEEE80211_ROOTMODE_NO_ROOT;\n\tmcfg->dot11MeshHWMPRannInterval = RTW_MESH_RANN_INTERVAL;\n\tmcfg->dot11MeshGateAnnouncementProtocol = _FALSE;\n\tmcfg->dot11MeshForwarding = _TRUE;\n\tmcfg->rssi_threshold = 0;\n\tmcfg->dot11MeshHWMPactivePathToRootTimeout = RTW_MESH_PATH_TO_ROOT_TIMEOUT;\n\tmcfg->dot11MeshHWMProotInterval = RTW_MESH_ROOT_INTERVAL;\n\tmcfg->dot11MeshHWMPconfirmationInterval = RTW_MESH_ROOT_CONFIRMATION_INTERVAL;\n\tmcfg->path_gate_timeout_factor = 3;\n\trtw_mesh_cfg_init_peer_sel_policy(mcfg);\n#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK\n\tmcfg->sane_metric_delta = RTW_MESH_SANE_METRIC_DELTA;\n\tmcfg->max_root_add_chk_cnt = RTW_MESH_MAX_ROOT_ADD_CHK_CNT;\n#endif\n\n#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\tmcfg->b2u_flags_msrc = 0;\n\tmcfg->b2u_flags_mfwd = RTW_MESH_B2U_GA_UCAST;\n#endif\n}\n\nvoid rtw_mesh_cfg_init_max_peer_links(_adapter *adapter, u8 stack_conf)\n{\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\n\tmcfg->max_peer_links = RTW_MESH_MAX_PEER_LINKS;\n\n\tif (mcfg->max_peer_links > stack_conf)\n\t\tmcfg->max_peer_links = stack_conf;\n}\n\nvoid rtw_mesh_cfg_init_plink_timeout(_adapter *adapter, u32 stack_conf)\n{\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\n\tmcfg->plink_timeout = stack_conf;\n}\n\nvoid rtw_mesh_init_mesh_info(_adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\n\t_rtw_memset(minfo, 0, sizeof(struct rtw_mesh_info));\n\n\trtw_mesh_plink_ctl_init(adapter);\n\t\n\tminfo->last_preq = rtw_get_current_time();\n\t/* minfo->last_sn_update = rtw_get_current_time(); */\n\tminfo->next_perr = rtw_get_current_time();\n\t\n\tATOMIC_SET(&minfo->mpaths, 0);\n\trtw_mesh_pathtbl_init(adapter);\n\n\t_rtw_init_queue(&minfo->mpath_tx_queue);\n\ttasklet_init(&minfo->mpath_tx_tasklet\n\t\t, (void(*)(unsigned long))mpath_tx_tasklet_hdl\n\t\t, (unsigned long)adapter);\n\n\trtw_mrc_init(adapter);\n\n\t_rtw_init_listhead(&minfo->preq_queue.list);\n\t_rtw_spinlock_init(&minfo->mesh_preq_queue_lock);\n\t\n\trtw_init_timer(&adapter->mesh_path_timer, adapter, rtw_ieee80211_mesh_path_timer, adapter);\n\trtw_init_timer(&adapter->mesh_path_root_timer, adapter, rtw_ieee80211_mesh_path_root_timer, adapter);\n\trtw_init_timer(&adapter->mesh_atlm_param_req_timer, adapter, rtw_mesh_atlm_param_req_timer, adapter);\n\t_init_workitem(&adapter->mesh_work, rtw_mesh_work_hdl, NULL);\n}\n\nvoid rtw_mesh_deinit_mesh_info(_adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\n\ttasklet_kill(&minfo->mpath_tx_tasklet);\n\trtw_mpath_tx_queue_flush(adapter);\n\t_rtw_deinit_queue(&adapter->mesh_info.mpath_tx_queue);\n\n\trtw_mrc_free(adapter);\n\n\trtw_mesh_pathtbl_unregister(adapter);\n\n\trtw_mesh_plink_ctl_deinit(adapter);\n\n\t_cancel_workitem_sync(&adapter->mesh_work);\n\t_cancel_timer_ex(&adapter->mesh_path_timer);\n\t_cancel_timer_ex(&adapter->mesh_path_root_timer);\n\t_cancel_timer_ex(&adapter->mesh_atlm_param_req_timer);\n}\n\n/**\n * rtw_mesh_nexthop_resolve - lookup next hop; conditionally start path discovery\n *\n * @skb: 802.11 frame to be sent\n * @sdata: network subif the frame will be sent through\n *\n * Lookup next hop for given skb and start path discovery if no\n * forwarding information is found.\n *\n * Returns: 0 if the next hop was found and -ENOENT if the frame was queued.\n * skb is freeed here if no mpath could be allocated.\n */\nint rtw_mesh_nexthop_resolve(_adapter *adapter,\n\t\t\tstruct xmit_frame *xframe)\n{\n\tstruct pkt_attrib *attrib = &xframe->attrib;\n\tstruct rtw_mesh_path *mpath;\n\tstruct xmit_frame *xframe_to_free = NULL;\n\tu8 *target_addr = attrib->mda;\n\tint err = 0;\n\tint ret = _SUCCESS;\n\n\trtw_rcu_read_lock();\n\terr = rtw_mesh_nexthop_lookup(adapter, target_addr, attrib->msa, attrib->ra);\n\tif (!err)\n\t\tgoto endlookup;\n\n\t/* no nexthop found, start resolving */\n\tmpath = rtw_mesh_path_lookup(adapter, target_addr);\n\tif (!mpath) {\n\t\tmpath = rtw_mesh_path_add(adapter, target_addr);\n\t\tif (IS_ERR(mpath)) {\n\t\t\txframe->pkt = NULL; /* free pkt outside */\n\t\t\trtw_mesh_path_discard_frame(adapter, xframe);\n\t\t\terr = PTR_ERR(mpath);\n\t\t\tret = _FAIL;\n\t\t\tgoto endlookup;\n\t\t}\n\t}\n\n\tif (!(mpath->flags & RTW_MESH_PATH_RESOLVING))\n\t\trtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START);\n\n\tenter_critical_bh(&mpath->frame_queue.lock);\n\n\tif (mpath->frame_queue_len >= RTW_MESH_FRAME_QUEUE_LEN) {\n\t\txframe_to_free = LIST_CONTAINOR(get_next(get_list_head(&mpath->frame_queue)), struct xmit_frame, list);\n\t\trtw_list_delete(&(xframe_to_free->list));\n\t\tmpath->frame_queue_len--;\n\t}\n\n\trtw_list_insert_tail(&xframe->list, get_list_head(&mpath->frame_queue));\n\tmpath->frame_queue_len++;\n\n\texit_critical_bh(&mpath->frame_queue.lock);\n\n\tret = RTW_RA_RESOLVING;\n\tif (xframe_to_free)\n\t\trtw_mesh_path_discard_frame(adapter, xframe_to_free);\n\nendlookup:\n\trtw_rcu_read_unlock();\n\treturn ret;\n}\n\n/**\n * rtw_mesh_nexthop_lookup - put the appropriate next hop on a mesh frame. Calling\n * this function is considered \"using\" the associated mpath, so preempt a path\n * refresh if this mpath expires soon.\n *\n * @skb: 802.11 frame to be sent\n * @sdata: network subif the frame will be sent through\n *\n * Returns: 0 if the next hop was found. Nonzero otherwise.\n */\nint rtw_mesh_nexthop_lookup(_adapter *adapter,\n\tconst u8 *mda, const u8 *msa, u8 *ra)\n{\n\tstruct rtw_mesh_path *mpath;\n\tstruct sta_info *next_hop;\n\tconst u8 *target_addr = mda;\n\tint err = -ENOENT;\n\tstruct registry_priv  *registry_par = &adapter->registrypriv;\n\tu8 peer_alive_based_preq = registry_par->peer_alive_based_preq;\n\tBOOLEAN nexthop_alive = _TRUE;\n\n\trtw_rcu_read_lock();\n\tmpath = rtw_mesh_path_lookup(adapter, target_addr);\n\n\tif (!mpath || !(mpath->flags & RTW_MESH_PATH_ACTIVE))\n\t\tgoto endlookup;\n\n\tnext_hop = rtw_rcu_dereference(mpath->next_hop);\n\tif (next_hop) {\n\t\t_rtw_memcpy(ra, next_hop->cmn.mac_addr, ETH_ALEN);\n\t\terr = 0;\n\t}\n\n\tif (peer_alive_based_preq && next_hop)\n\t\tnexthop_alive = next_hop->alive;\n\n\tif (_rtw_memcmp(adapter_mac_addr(adapter), msa, ETH_ALEN) == _TRUE &&\n\t    !(mpath->flags & RTW_MESH_PATH_RESOLVING) &&\n\t    !(mpath->flags & RTW_MESH_PATH_FIXED)) {\n\t\tu8 flags = RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH;\n\n\t\tif (peer_alive_based_preq && nexthop_alive == _FALSE) {\n\t\t\tflags |= RTW_PREQ_Q_F_BCAST_PREQ;\n\t\t\trtw_mesh_queue_preq(mpath, flags);\n\t\t} else if (rtw_time_after(rtw_get_current_time(),\n\t\t\tmpath->exp_time -\n\t\t\trtw_ms_to_systime(adapter->mesh_cfg.path_refresh_time))) {\n\t\t\trtw_mesh_queue_preq(mpath, flags);\n\t\t}\n\t/* Avoid keeping trying unicast PREQ toward root,\n\t   when next_hop leaves */\n\t} else if (peer_alive_based_preq &&\n\t\t   _rtw_memcmp(adapter_mac_addr(adapter), msa, ETH_ALEN) == _TRUE &&\n\t\t   (mpath->flags & RTW_MESH_PATH_RESOLVING) &&\n\t\t   !(mpath->flags & RTW_MESH_PATH_FIXED) &&\n\t\t   !(mpath->flags & RTW_MESH_PATH_BCAST_PREQ) &&\n\t\t   mpath->is_root && nexthop_alive == _FALSE) {\n\t\tenter_critical_bh(&mpath->state_lock);\n\t\tmpath->flags |= RTW_MESH_PATH_BCAST_PREQ;\n\t\texit_critical_bh(&mpath->state_lock);\n\t}\n\nendlookup:\n\trtw_rcu_read_unlock();\n\treturn err;\n}\n\n#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\nstatic bool rtw_mesh_data_bmc_to_uc(_adapter *adapter\n\t, const u8 *da, const u8 *sa, const u8 *mda, const u8 *msa\n\t, u8 ae_need, const u8 *ori_ta, u8 mfwd_ttl\n\t, _list *b2u_list, u8 *b2u_num, u32 *b2u_mseq)\n{\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct xmit_priv *xmitpriv = &adapter->xmitpriv;\n\t_irqL irqL;\n\t_list *head, *list;\n\tstruct sta_info *sta;\n\tchar b2u_sta_id[NUM_STA];\n\tu8 b2u_sta_num = 0;\n\tbool bmc_need = _FALSE;\n\tint i;\n\n\t_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);\n\thead = &stapriv->asoc_list;\n\tlist = get_next(head);\n\n\twhile ((rtw_end_of_queue_search(head, list)) == _FALSE) {\n\t\tint stainfo_offset;\n\n\t\tsta = LIST_CONTAINOR(list, struct sta_info, asoc_list);\n\t\tlist = get_next(list);\n\t\n\t\tstainfo_offset = rtw_stainfo_offset(stapriv, sta);\n\t\tif (stainfo_offset_valid(stainfo_offset))\n\t\t\tb2u_sta_id[b2u_sta_num++] = stainfo_offset;\n\t}\n\t_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);\n\n\tif (!b2u_sta_num)\n\t\tgoto exit;\n\n\tfor (i = 0; i < b2u_sta_num; i++) {\n\t\tstruct xmit_frame *b2uframe;\n\t\tstruct pkt_attrib *attrib;\n\n\t\tsta = rtw_get_stainfo_by_offset(stapriv, b2u_sta_id[i]);\n\t\tif (!(sta->state & _FW_LINKED)\n\t\t\t|| _rtw_memcmp(sta->cmn.mac_addr, msa, ETH_ALEN) == _TRUE\n\t\t\t|| (ori_ta && _rtw_memcmp(sta->cmn.mac_addr, ori_ta, ETH_ALEN) == _TRUE)\n\t\t\t|| is_broadcast_mac_addr(sta->cmn.mac_addr)\n\t\t\t|| is_zero_mac_addr(sta->cmn.mac_addr))\n\t\t\tcontinue;\n\n\t\tb2uframe = rtw_alloc_xmitframe(xmitpriv);\n\t\tif (!b2uframe) {\n\t\t\tbmc_need = _TRUE;\n\t\t\tbreak;\n\t\t}\n\n\t\tif ((*b2u_num)++ == 0 && !ori_ta) {\n\t\t\t*b2u_mseq = (cpu_to_le32(adapter->mesh_info.mesh_seqnum));\n\t\t\tadapter->mesh_info.mesh_seqnum++;\n\t\t}\n\n\t\tattrib = &b2uframe->attrib;\n\n\t\tattrib->mb2u = 1;\n\t\tattrib->mseq = *b2u_mseq;\n\t\tattrib->mfwd_ttl = ori_ta ? mfwd_ttl : 0;\n\t\t_rtw_memcpy(attrib->ra, sta->cmn.mac_addr, ETH_ALEN);\n\t\t_rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN);\n\t\t_rtw_memcpy(attrib->mda, mda, ETH_ALEN);\n\t\t_rtw_memcpy(attrib->msa, msa, ETH_ALEN);\n\t\t_rtw_memcpy(attrib->dst, da, ETH_ALEN);\n\t\t_rtw_memcpy(attrib->src, sa, ETH_ALEN);\n\t\tattrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA;\n\n\t\trtw_list_insert_tail(&b2uframe->list, b2u_list);\n\t}\n\nexit:\n\treturn bmc_need;\n}\n\nvoid dump_mesh_b2u_flags(void *sel, _adapter *adapter)\n{\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\n\tRTW_PRINT_SEL(sel, \"%4s %4s\\n\", \"msrc\", \"mfwd\");\n\tRTW_PRINT_SEL(sel, \"0x%02x 0x%02x\\n\", mcfg->b2u_flags_msrc, mcfg->b2u_flags_mfwd);\n}\n#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */\n\nint rtw_mesh_addr_resolve(_adapter *adapter, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list)\n{\n\tstruct pkt_file pktfile;\n\tstruct ethhdr etherhdr;\n\tstruct pkt_attrib *attrib;\n\tstruct rtw_mesh_path *mpath = NULL, *mppath = NULL;\n\tu8 is_da_mcast;\n\tu8 ae_need;\n#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\tbool bmc_need = _TRUE;\n\tu8 b2u_num = 0;\n\tu32 b2u_mseq = 0;\n#endif\n\tint res = _SUCCESS;\n\n\t_rtw_open_pktfile(pkt, &pktfile);\n\tif (_rtw_pktfile_read(&pktfile, (u8 *)&etherhdr, ETH_HLEN) != ETH_HLEN) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\t\n\txframe->pkt = pkt;\n#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\t_rtw_init_listhead(b2u_list);\n#endif\n\n\tis_da_mcast = IS_MCAST(etherhdr.h_dest);\n\tif (!is_da_mcast) {\n\t\tstruct sta_info *next_hop; \n\t\tbool mpp_lookup = 1;\n\t\n\t\tmpath = rtw_mesh_path_lookup(adapter, etherhdr.h_dest);\n\t\tif (mpath) {\n\t\t\tmpp_lookup = 0;\n\t\t\tnext_hop = rtw_rcu_dereference(mpath->next_hop);\n\t\t\tif (!next_hop\n\t\t\t\t|| !(mpath->flags & (RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVING))\n\t\t\t) {\n\t\t\t\t/* mpath is not valid, search mppath */\n\t\t\t\tmpp_lookup = 1;\n\t\t\t}\n\t\t}\n\n\t\tif (mpp_lookup) {\n\t\t\tmppath = rtw_mpp_path_lookup(adapter, etherhdr.h_dest);\n\t\t\tif (mppath)\n\t\t\t\tmppath->exp_time = rtw_get_current_time();\n\t\t}\n\n\t\tif (mppath && mpath)\n\t\t\trtw_mesh_path_del(adapter, mpath->dst);\n\n\t\tae_need = _rtw_memcmp(adapter_mac_addr(adapter), etherhdr.h_source, ETH_ALEN) == _FALSE\n\t\t\t|| (mppath && _rtw_memcmp(mppath->mpp, etherhdr.h_dest, ETH_ALEN) == _FALSE);\n\t} else {\n\t\tae_need = _rtw_memcmp(adapter_mac_addr(adapter), etherhdr.h_source, ETH_ALEN) == _FALSE;\n\n\t\t#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\t\tif (rtw_msrc_b2u_policy_chk(adapter->mesh_cfg.b2u_flags_msrc, etherhdr.h_dest)) {\n\t\t\tbmc_need = rtw_mesh_data_bmc_to_uc(adapter\n\t\t\t\t, etherhdr.h_dest, etherhdr.h_source\n\t\t\t\t, etherhdr.h_dest, adapter_mac_addr(adapter), ae_need, NULL, 0\n\t\t\t\t, b2u_list, &b2u_num, &b2u_mseq);\n\t\t\tif (bmc_need == _FALSE) {\n\t\t\t\tres = RTW_BMC_NO_NEED;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\t\t#endif\n\t}\n\n\tattrib = &xframe->attrib;\n\n#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\tif (b2u_num) {\n\t\tattrib->mb2u = 1;\n\t\tattrib->mseq = b2u_mseq;\n\t} else\n\t\tattrib->mb2u = 0;\n#endif\n\n\tattrib->mfwd_ttl = 0;\n\t_rtw_memcpy(attrib->dst, etherhdr.h_dest, ETH_ALEN);\n\t_rtw_memcpy(attrib->src, etherhdr.h_source, ETH_ALEN);\n\t_rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN);\n\n\tif (is_da_mcast) {\n\t\tattrib->mesh_frame_mode = ae_need ? MESH_BMCAST_PX_DATA : MESH_BMCAST_DATA;\n\t\t_rtw_memcpy(attrib->ra, attrib->dst, ETH_ALEN);\n\t\t_rtw_memcpy(attrib->msa, adapter_mac_addr(adapter), ETH_ALEN);\n\t} else {\n\t\tattrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA;\n\t\t_rtw_memcpy(attrib->mda, (mppath && ae_need) ? mppath->mpp : attrib->dst, ETH_ALEN);\n\t\t_rtw_memcpy(attrib->msa, adapter_mac_addr(adapter), ETH_ALEN);\n\t\t/* RA needs to be resolved */\n\t\tres = rtw_mesh_nexthop_resolve(adapter, xframe);\n\t}\n\nexit:\n\treturn res;\n}\n\ns8 rtw_mesh_tx_set_whdr_mctrl_len(u8 mesh_frame_mode, struct pkt_attrib *attrib)\n{\n\tu8 ret = 0;\n\tswitch (mesh_frame_mode) {\n\tcase MESH_UCAST_DATA:\n\t\tattrib->hdrlen = WLAN_HDR_A4_QOS_LEN;\n\t\t/* mesh flag + mesh TTL + Mesh SN. no ext addr. */\n\t\tattrib->meshctrl_len = 6;\n\t\tbreak;\n\tcase MESH_BMCAST_DATA:\n\t\tattrib->hdrlen = WLAN_HDR_A3_QOS_LEN;\n\t\t/* mesh flag + mesh TTL + Mesh SN. no ext addr. */\n\t\tattrib->meshctrl_len = 6;\n\t\tbreak;\n\tcase MESH_UCAST_PX_DATA:\n\t\tattrib->hdrlen = WLAN_HDR_A4_QOS_LEN;\n\t\t/* mesh flag + mesh TTL + Mesh SN + extaddr1 + extaddr2. */\n\t\tattrib->meshctrl_len = 18;\n\t\tbreak;\n\tcase MESH_BMCAST_PX_DATA:\n\t\tattrib->hdrlen = WLAN_HDR_A3_QOS_LEN;\n\t\t/* mesh flag + mesh TTL + Mesh SN + extaddr1 */\n\t\tattrib->meshctrl_len = 12;\n\t\tbreak;\n\tdefault:\n\t\tRTW_WARN(\"Invalid mesh frame mode:%u\\n\", mesh_frame_mode);\n\t\tret = -1;\n\t\tbreak;\n\t}\t\t\t\t\n\n\treturn ret;\n}\n\nvoid rtw_mesh_tx_build_mctrl(_adapter *adapter, struct pkt_attrib *attrib, u8 *buf)\n{\n\tstruct rtw_ieee80211s_hdr *mctrl = (struct rtw_ieee80211s_hdr *)buf;\n\n\t_rtw_memset(mctrl, 0, XATTRIB_GET_MCTRL_LEN(attrib));\n\n\tif (attrib->mfwd_ttl\n\t\t#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\t\t|| attrib->mb2u\n\t\t#endif\n\t) {\n\t\t#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\t\tif (!attrib->mfwd_ttl)\n\t\t\tmctrl->ttl = adapter->mesh_cfg.dot11MeshTTL;\n\t\telse\n\t\t#endif\n\t\t\tmctrl->ttl = attrib->mfwd_ttl;\n\n\t\tmctrl->seqnum = (cpu_to_le32(attrib->mseq));\n\t} else {\n\t\tmctrl->ttl = adapter->mesh_cfg.dot11MeshTTL;\n\t\tmctrl->seqnum = (cpu_to_le32(adapter->mesh_info.mesh_seqnum));\n\t\tadapter->mesh_info.mesh_seqnum++;\n\t}\n\n\tswitch (attrib->mesh_frame_mode){\n\tcase MESH_UCAST_DATA:\n\tcase MESH_BMCAST_DATA:\n\t\tbreak;\n\tcase MESH_UCAST_PX_DATA:\n\t\tmctrl->flags |= MESH_FLAGS_AE_A5_A6;\n\t\t_rtw_memcpy(mctrl->eaddr1, attrib->dst, ETH_ALEN);\n\t\t_rtw_memcpy(mctrl->eaddr2, attrib->src, ETH_ALEN);\n\t\tbreak;\n\tcase MESH_BMCAST_PX_DATA:\n\t\tmctrl->flags |= MESH_FLAGS_AE_A4;\n\t\t_rtw_memcpy(mctrl->eaddr1, attrib->src, ETH_ALEN);\n\t\tbreak;\n\tcase MESH_MHOP_UCAST_ACT:\n\t\t/* TBD */\n\t\tbreak;\n\tcase MESH_MHOP_BMCAST_ACT:\n\t\t/* TBD */\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nu8 rtw_mesh_tx_build_whdr(_adapter *adapter, struct pkt_attrib *attrib\n\t, u16 *fctrl, struct rtw_ieee80211_hdr *whdr)\n{\n\tswitch (attrib->mesh_frame_mode) {\n\tcase MESH_UCAST_DATA:\t\t/* 1, 1, RA, TA, mDA(=DA),\tmSA(=SA) */\n\tcase MESH_UCAST_PX_DATA:\t/* 1, 1, RA, TA, mDA,\t\tmSA,\t\t[DA, SA] */\n\t\tSetToDs(fctrl);\n\t\tSetFrDs(fctrl);\n\t\t_rtw_memcpy(whdr->addr1, attrib->ra, ETH_ALEN);\n\t\t_rtw_memcpy(whdr->addr2, attrib->ta, ETH_ALEN);\n\t\t_rtw_memcpy(whdr->addr3, attrib->mda, ETH_ALEN);\n\t\t_rtw_memcpy(whdr->addr4, attrib->msa, ETH_ALEN);\n\t\tbreak;\n\tcase MESH_BMCAST_DATA:\t\t/* 0, 1, RA(DA), TA, mSA(SA) */\n\tcase MESH_BMCAST_PX_DATA:\t/* 0, 1, RA(DA), TA, mSA,\t\t[SA] */\n\t\tSetFrDs(fctrl);\n\t\t_rtw_memcpy(whdr->addr1, attrib->ra, ETH_ALEN);\n\t\t_rtw_memcpy(whdr->addr2, attrib->ta, ETH_ALEN);\n\t\t_rtw_memcpy(whdr->addr3, attrib->msa, ETH_ALEN);\n\t\tbreak;\n\tcase MESH_MHOP_UCAST_ACT:\n\t\t/* TBD */\n\t\tRTW_INFO(\"MESH_MHOP_UCAST_ACT\\n\");\n\t\tbreak;\n\tcase MESH_MHOP_BMCAST_ACT:\n\t\t/* TBD */\n\t\tRTW_INFO(\"MESH_MHOP_BMCAST_ACT\\n\");\n\t\tbreak;\n\tdefault:\n\t\tRTW_WARN(\"Invalid mesh frame mode\\n\");\n\t\tbreak;\n\t}\n\t\n\treturn 0;\n}\n\nint rtw_mesh_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta)\n{\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;\n\tu8 *whdr = get_recvframe_data(rframe);\n\tu8 is_ra_bmc = 0;\n\tu8 a4_shift = 0;\n\tu8 ps;\n\tu8 *qc;\n\tu8 mps_mode = RTW_MESH_PS_UNKNOWN;\n\tsint ret = _FAIL;\n\n\tif (!(MLME_STATE(adapter) & WIFI_ASOC_STATE))\n\t\tgoto exit;\n\n\tif (!rattrib->qos)\n\t\tgoto exit;\n\n\tswitch (rattrib->to_fr_ds) {\n\tcase 1:\n\t\tif (!IS_MCAST(GetAddr1Ptr(whdr)))\n\t\t\tgoto exit;\n\t\t*sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr));\n\t\tif (*sta == NULL) {\n\t\t\tret = _SUCCESS; /* return _SUCCESS to drop at sta checking */\n\t\t\tgoto exit;\n\t\t}\n\t\t_rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);\n\t\t_rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);\n\t\t_rtw_memcpy(rattrib->mda, GetAddr1Ptr(whdr), ETH_ALEN);\n\t\t_rtw_memcpy(rattrib->msa, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */\n\t\t_rtw_memcpy(rattrib->dst, GetAddr1Ptr(whdr), ETH_ALEN);\n\t\t_rtw_memcpy(rattrib->src, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */\n\t\t_rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN);\n\t\tis_ra_bmc = 1;\n\t\tbreak;\n\tcase 3:\n\t\tif (IS_MCAST(GetAddr1Ptr(whdr)))\n\t\t\tgoto exit;\n\t\t*sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr));\n\t\tif (*sta == NULL) {\n\t\t\tret = _SUCCESS; /* return _SUCCESS to drop at sta checking */\n\t\t\tgoto exit;\n\t\t}\n\t\t_rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);\n\t\t_rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);\n\t\t_rtw_memcpy(rattrib->mda, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */\n\t\t_rtw_memcpy(rattrib->msa, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */\n\t\t_rtw_memcpy(rattrib->dst, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */\n\t\t_rtw_memcpy(rattrib->src, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */\n\t\t_rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN);\n\t\ta4_shift = ETH_ALEN;\n\t\tbreak;\n\tdefault:\n\t\tgoto exit;\n\t}\n\n\tqc = whdr + WLAN_HDR_A3_LEN + a4_shift;\n\tps = GetPwrMgt(whdr);\n\tmps_mode = ps ? (is_ra_bmc || (get_mps_lv(qc)) ? RTW_MESH_PS_DSLEEP : RTW_MESH_PS_LSLEEP) : RTW_MESH_PS_ACTIVE;\n\n\tif (ps) {\n\t\tif (!((*sta)->state & WIFI_SLEEP_STATE))\n\t\t\tstop_sta_xmit(adapter, *sta);\n\t} else {\n\t\tif ((*sta)->state & WIFI_SLEEP_STATE)\n\t\t\twakeup_sta_to_xmit(adapter, *sta);\n\t}\n\n\tif (is_ra_bmc)\n\t\t(*sta)->nonpeer_mps = mps_mode;\n\telse {\n\t\t(*sta)->peer_mps = mps_mode;\n\t\tif (mps_mode != RTW_MESH_PS_ACTIVE && (*sta)->nonpeer_mps == RTW_MESH_PS_ACTIVE)\n\t\t\t(*sta)->nonpeer_mps = RTW_MESH_PS_DSLEEP;\n\t}\n\n\tif (get_frame_sub_type(whdr) & BIT(6)) {\n\t\t/* No data, will not indicate to upper layer, temporily count it here */\n\t\tcount_rx_stats(adapter, rframe, *sta);\n\t\tret = RTW_RX_HANDLED;\n\t\tgoto exit;\n\t}\n\n\trattrib->mesh_ctrl_present = get_mctrl_present(qc) ? 1 : 0;\n\tif (!rattrib->mesh_ctrl_present)\n\t\tgoto exit;\n\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n\nint rtw_mesh_rx_data_validate_mctrl(_adapter *adapter, union recv_frame *rframe\n\t, const struct rtw_ieee80211s_hdr *mctrl, const u8 *mda, const u8 *msa\n\t, u8 *mctrl_len\n\t, const u8 **da, const u8 **sa)\n{\n\tstruct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;\n\tu8 mlen;\n\tu8 ae;\n\tint ret = _SUCCESS;\n\n\tae = mctrl->flags & MESH_FLAGS_AE;\n\tmlen = ae_to_mesh_ctrl_len[ae];\n\tswitch (rattrib->to_fr_ds) {\n\tcase 1:\n\t\t*da = mda;\n\t\tif (ae == MESH_FLAGS_AE_A4)\n\t\t\t*sa = mctrl->eaddr1;\n\t\telse if (ae == 0)\n\t\t\t*sa = msa;\n\t\telse\n\t\t\tret = _FAIL;\n\t\tbreak;\n\tcase 3:\n\t\tif (ae == MESH_FLAGS_AE_A5_A6) {\n\t\t\t*da = mctrl->eaddr1;\n\t\t\t*sa = mctrl->eaddr2;\n\t\t} else if (ae == 0) {\n\t\t\t*da = mda;\n\t\t\t*sa = msa;\n\t\t} else\n\t\t\tret = _FAIL;\n\t\tbreak;\n\tdefault:\n\t\tret = _FAIL;\n\t}\n\n\tif (ret == _FAIL) {\n\t\t#ifdef DBG_RX_DROP_FRAME\n\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" invalid tfDS:%u AE:%u combination ra=\"MAC_FMT\" ta=\"MAC_FMT\"\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), rattrib->to_fr_ds, ae, MAC_ARG(rattrib->ra), MAC_ARG(rattrib->ta));\n\t\t#endif\n\t\t*mctrl_len = 0;\n\t} else\n\t\t*mctrl_len = mlen;\n\n\treturn ret;\t\n}\n\ninline int rtw_mesh_rx_validate_mctrl_non_amsdu(_adapter *adapter, union recv_frame *rframe)\n{\n\tstruct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;\n\tconst u8 *da, *sa;\n\tint ret;\n\n\tret = rtw_mesh_rx_data_validate_mctrl(adapter, rframe\n\t\t\t, (struct rtw_ieee80211s_hdr *)(get_recvframe_data(rframe) + rattrib->hdrlen + rattrib->iv_len)\n\t\t\t, rattrib->mda, rattrib->msa\n\t\t\t, &rattrib->mesh_ctrl_len\n\t\t\t, &da, &sa);\n\n\tif (ret == _SUCCESS) {\n\t\t_rtw_memcpy(rattrib->dst, da, ETH_ALEN);\n\t\t_rtw_memcpy(rattrib->src, sa, ETH_ALEN);\n\t}\n\n\treturn ret;\n}\n\n/**\n * rtw_mesh_rx_nexthop_resolve - lookup next hop; conditionally start path discovery\n *\n * @skb: 802.11 frame to be sent\n * @sdata: network subif the frame will be sent through\n *\n * Lookup next hop for given skb and start path discovery if no\n * forwarding information is found.\n *\n * Returns: 0 if the next hop was found and -ENOENT if the frame was queued.\n * skb is freeed here if no mpath could be allocated.\n */\nstatic int rtw_mesh_rx_nexthop_resolve(_adapter *adapter,\n\tconst u8 *mda, const u8 *msa, u8 *ra)\n{\n\tstruct rtw_mesh_path *mpath;\n\tstruct xmit_frame *xframe_to_free = NULL;\n\tint err = 0;\n\tint ret = _SUCCESS;\n\n\trtw_rcu_read_lock();\n\terr = rtw_mesh_nexthop_lookup(adapter, mda, msa, ra);\n\tif (!err)\n\t\tgoto endlookup;\n\n\t/* no nexthop found, start resolving */\n\tmpath = rtw_mesh_path_lookup(adapter, mda);\n\tif (!mpath) {\n\t\tmpath = rtw_mesh_path_add(adapter, mda);\n\t\tif (IS_ERR(mpath)) {\n\t\t\terr = PTR_ERR(mpath);\n\t\t\tret = _FAIL;\n\t\t\tgoto endlookup;\n\t\t}\n\t}\n\n\tif (!(mpath->flags & RTW_MESH_PATH_RESOLVING))\n\t\trtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START);\n\n\tret = _FAIL;\n\nendlookup:\n\trtw_rcu_read_unlock();\n\treturn ret;\n}\n\n#define RTW_MESH_DECACHE_BMC 1\n#define RTW_MESH_DECACHE_UC 0\n\n#define RTW_MESH_FORWARD_MDA_SELF_COND 0\n#define DBG_RTW_MESH_FORWARD_MDA_SELF_COND 0\nint rtw_mesh_rx_msdu_act_check(union recv_frame *rframe\n\t, const u8 *mda, const u8 *msa\n\t, const u8 *da, const u8 *sa\n\t, struct rtw_ieee80211s_hdr *mctrl\n\t, struct xmit_frame **fwd_frame, _list *b2u_list)\n{\n\t_adapter *adapter = rframe->u.hdr.adapter;\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;\n\tstruct rtw_mesh_path *mppath;\n\tu8 is_mda_bmc = IS_MCAST(mda); \n\tu8 is_mda_self = !is_mda_bmc && _rtw_memcmp(mda, adapter_mac_addr(adapter), ETH_ALEN);\n\tstruct xmit_frame *xframe;\n\tstruct pkt_attrib *xattrib;\n\tu8 fwd_ra[ETH_ALEN] = {0};\n\tu8 fwd_mpp[ETH_ALEN] = {0}; /* forward to other gate */\n\tu32 fwd_mseq;\n\tint act = 0;\n\tu8 ae_need;\n#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\tbool bmc_need = _TRUE;\n\tu8 b2u_num = 0;\n#endif\n\n\t/* fwd info lifetime update */\n\t#if 0\n\tif (!is_mda_self)\n\t\tmDA(A3) fwinfo.lifetime\n\tmSA(A4) fwinfo.lifetime\n\tPrecursor-to-mDA(A2) fwinfo.lifetime\n\t#endif\n\n\t/* update/create pxoxy info for SA, mSA */\n\tif ((mctrl->flags & MESH_FLAGS_AE)\n\t\t&& sa != msa && _rtw_memcmp(sa, msa, ETH_ALEN) == _FALSE\n\t) {\n\t\tconst u8 *proxied_addr = sa;\n\t\tconst u8 *mpp_addr = msa;\n\n\t\trtw_rcu_read_lock();\n\t\tmppath = rtw_mpp_path_lookup(adapter, proxied_addr);\n\t\tif (!mppath)\n\t\t\trtw_mpp_path_add(adapter, proxied_addr, mpp_addr);\n\t\telse {\n\t\t\tenter_critical_bh(&mppath->state_lock);\n\t\t\tif (_rtw_memcmp(mppath->mpp, mpp_addr, ETH_ALEN) == _FALSE)\n\t\t\t\t_rtw_memcpy(mppath->mpp, mpp_addr, ETH_ALEN);\n\t\t\tmppath->exp_time = rtw_get_current_time();\n\t\t\texit_critical_bh(&mppath->state_lock);\n\t\t}\n\t\trtw_rcu_read_unlock();\n\t}\n\n\t/* mSA is self, need no further process */\n\tif (_rtw_memcmp(msa, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)\n\t\tgoto exit;\n\n\tfwd_mseq = le32_to_cpu(mctrl->seqnum);\n\n\t/* check duplicate MSDU from mSA */\n\tif (((RTW_MESH_DECACHE_BMC && is_mda_bmc)\n\t\t\t|| (RTW_MESH_DECACHE_UC && !is_mda_bmc))\n\t\t&& rtw_mesh_decache(adapter, msa, fwd_mseq)\n\t) {\n\t\tminfo->mshstats.dropped_frames_duplicate++;\n\t\tgoto exit;\n\t}\n\n\tif (is_mda_bmc) {\n\t\t/* mDA is bmc addr */\n\t\tact |= RTW_RX_MSDU_ACT_INDICATE;\n\t\tif (!mcfg->dot11MeshForwarding)\n\t\t\tgoto exit;\n\t\tgoto fwd_chk;\n\n\t} else if (!is_mda_self) {\n\t\t/* mDA is unicast but not self */\n\t\tif (!mcfg->dot11MeshForwarding) {\n\t\t\trtw_mesh_path_error_tx(adapter\n\t\t\t\t, adapter->mesh_cfg.element_ttl\n\t\t\t\t, mda, 0\n\t\t\t\t, WLAN_REASON_MESH_PATH_NOFORWARD\n\t\t\t\t, rattrib->ta\n\t\t\t);\n\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" mDA(\"MAC_FMT\") not self, !dot11MeshForwarding\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(mda));\n\t\t\t#endif\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (rtw_mesh_rx_nexthop_resolve(adapter, mda, msa, fwd_ra) != _SUCCESS) {\n\t\t\t/* mDA is unknown */\n\t\t\trtw_mesh_path_error_tx(adapter\n\t\t\t\t, adapter->mesh_cfg.element_ttl\n\t\t\t\t, mda, 0\n\t\t\t\t, WLAN_REASON_MESH_PATH_NOFORWARD\n\t\t\t\t, rattrib->ta\n\t\t\t);\n\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" mDA(\"MAC_FMT\") unknown\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(mda));\n\t\t\t#endif\n\t\t\tminfo->mshstats.dropped_frames_no_route++;\n\t\t\tgoto exit;\n\n\t\t} else {\n\t\t\t/* mDA is known in fwd info */\n\t\t\t#if 0\n\t\t\tif\t(TA is not in precursors)\n\t\t\t\tgoto exit;\n\t\t\t#endif\n\t\t\tgoto fwd_chk;\n\t\t}\n\n\t} else {\n\t\t/* mDA is self */\n\t\t#if RTW_MESH_FORWARD_MDA_SELF_COND\n\t\tif (da == mda\n\t\t\t|| _rtw_memcmp(da, adapter_mac_addr(adapter), ETH_ALEN)\n\t\t) {\n\t\t\t/* DA is self, indicate */\n\t\t\tact |= RTW_RX_MSDU_ACT_INDICATE;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (rtw_get_iface_by_macddr(adapter, da)) {\n\t\t\t/* DA is buddy, indicate */\n\t\t\tact |= RTW_RX_MSDU_ACT_INDICATE;\n\t\t\t#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" DA(\"MAC_FMT\") is buddy(\"ADPT_FMT\")\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(da), ADPT_ARG(rtw_get_iface_by_macddr(adapter, da)));\n\t\t\t#endif\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* DA is not self or buddy */\n\t\tif (rtw_mesh_nexthop_lookup(adapter, da, msa, fwd_ra) == 0) {\n\t\t\t/* DA is known in fwd info */\n\t\t\tif (!mcfg->dot11MeshForwarding) {\n\t\t\t\t/* path error to? */\n\t\t\t\t#if defined(DBG_RX_DROP_FRAME) || DBG_RTW_MESH_FORWARD_MDA_SELF_COND\n\t\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" DA(\"MAC_FMT\") not self, !dot11MeshForwarding\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(da));\n\t\t\t\t#endif\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tmda = da;\n\t\t\t#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" fwd to DA(\"MAC_FMT\"), fwd_RA(\"MAC_FMT\")\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(fwd_ra));\n\t\t\t#endif\n\t\t\tgoto fwd_chk;\n\t\t}\n\n\t\trtw_rcu_read_lock();\n\t\tmppath = rtw_mpp_path_lookup(adapter, da);\n\t\tif (mppath) {\n\t\t\tif (_rtw_memcmp(mppath->mpp, adapter_mac_addr(adapter), ETH_ALEN) == _FALSE) {\n\t\t\t\t/* DA is proxied by others */\n\t\t\t\tif (!mcfg->dot11MeshForwarding) {\n\t\t\t\t\t/* path error to? */\n\t\t\t\t\t#if defined(DBG_RX_DROP_FRAME) || DBG_RTW_MESH_FORWARD_MDA_SELF_COND\n\t\t\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" DA(\"MAC_FMT\") is proxied by (\"MAC_FMT\"), !dot11MeshForwarding\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(mppath->mpp));\n\t\t\t\t\t#endif\n\t\t\t\t\trtw_rcu_read_unlock();\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t\t_rtw_memcpy(fwd_mpp, mppath->mpp, ETH_ALEN);\n\t\t\t\tmda = fwd_mpp;\n\t\t\t\tmsa = adapter_mac_addr(adapter);\n\t\t\t\trtw_rcu_read_unlock();\n\n\t\t\t\t/* resolve RA */\n\t\t\t\tif (rtw_mesh_nexthop_lookup(adapter, mda, msa, fwd_ra) != 0) {\n\t\t\t\t\tminfo->mshstats.dropped_frames_no_route++;\n\t\t\t\t\t#if defined(DBG_RX_DROP_FRAME) || DBG_RTW_MESH_FORWARD_MDA_SELF_COND\n\t\t\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" DA(\"MAC_FMT\") is proxied by (\"MAC_FMT\"), RA resolve fail\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(mppath->mpp));\n\t\t\t\t\t#endif\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t\t#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" DA(\"MAC_FMT\") is proxied by (\"MAC_FMT\"), fwd_RA(\"MAC_FMT\")\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(mppath->mpp), MAC_ARG(fwd_ra));\n\t\t\t\t#endif\n\t\t\t\tgoto fwd_chk; /*  forward to other gate */\n\t\t\t} else {\n\t\t\t\t#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" DA(\"MAC_FMT\") is proxied by self\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(da));\n\t\t\t\t#endif\n\t\t\t}\n\t\t}\n\t\trtw_rcu_read_unlock();\n\n\t\tif (!mppath) {\n\t\t\t#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" DA(\"MAC_FMT\") unknown\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(da));\n\t\t\t#endif\n\t\t\t/* DA is unknown */\n\t\t\t#if 0 /* TODO: flags with AE bit */\n\t\t\trtw_mesh_path_error_tx(adapter\n\t\t\t\t, adapter->mesh_cfg.element_ttl\n\t\t\t\t, mda, adapter->mesh_info.last_sn_update\n\t\t\t\t, WLAN_REASON_MESH_PATH_NOPROXY\n\t\t\t\t, msa\n\t\t\t);\n\t\t\t#endif\n\t\t}\n\n\t\t/*\n\t\t* indicate to DS for both cases:\n\t\t* 1.) DA is proxied by self\n\t\t* 2.) DA is unknown\n\t\t*/\n\t\t#endif /* RTW_MESH_FORWARD_MDA_SELF_COND */\n\t\tact |= RTW_RX_MSDU_ACT_INDICATE;\n\t\tgoto exit;\n\t}\n\nfwd_chk:\n\n\tif (adapter->stapriv.asoc_list_cnt <= 1)\n\t\tgoto exit;\n\n\tif (mctrl->ttl == 1) {\n\t\tminfo->mshstats.dropped_frames_ttl++;\n\t\tif (!act) {\n\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" ttl reaches 0, not forwarding\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter));\n\t\t\t#endif\n\t\t}\n\t\tgoto exit;\n\t}\n\n#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\t_rtw_init_listhead(b2u_list);\n#endif\n\n\tae_need = _rtw_memcmp(da , mda, ETH_ALEN) == _FALSE\n\t\t|| _rtw_memcmp(sa , msa, ETH_ALEN) == _FALSE;\n\n#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\tif (is_mda_bmc\n\t\t&& rtw_mfwd_b2u_policy_chk(mcfg->b2u_flags_mfwd, mda, rattrib->to_fr_ds == 3)\n\t) {\n\t\tbmc_need = rtw_mesh_data_bmc_to_uc(adapter\n\t\t\t, da, sa, mda, msa, ae_need, rframe->u.hdr.psta->cmn.mac_addr, mctrl->ttl - 1\n\t\t\t, b2u_list, &b2u_num, &fwd_mseq);\n\t}\n\n\tif (bmc_need == _TRUE)\n#endif\n\t{\n\t\txframe = rtw_alloc_xmitframe(&adapter->xmitpriv);\n\t\tif (!xframe) {\n\t\t\t#ifdef DBG_TX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_TX_DROP_FRAME \"FUNC_ADPT_FMT\" rtw_alloc_xmitframe fail\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter));\n\t\t\t#endif\n\t\t\tgoto exit;\n\t\t}\n\n\t\txattrib = &xframe->attrib;\n\n#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\t\tif (b2u_num)\n\t\t\txattrib->mb2u = 1;\n\t\telse\n\t\t\txattrib->mb2u = 0;\n#endif\n\t\txattrib->mfwd_ttl = mctrl->ttl - 1;\n\t\txattrib->mseq = fwd_mseq;\n\t\t_rtw_memcpy(xattrib->dst, da, ETH_ALEN);\n\t\t_rtw_memcpy(xattrib->src, sa, ETH_ALEN);\n\t\t_rtw_memcpy(xattrib->mda, mda, ETH_ALEN);\n\t\t_rtw_memcpy(xattrib->msa, msa, ETH_ALEN);\n\t\t_rtw_memcpy(xattrib->ta, adapter_mac_addr(adapter), ETH_ALEN);\n\n\t\tif (is_mda_bmc) {\n\t\t\txattrib->mesh_frame_mode = ae_need ? MESH_BMCAST_PX_DATA : MESH_BMCAST_DATA;\n\t\t\t_rtw_memcpy(xattrib->ra, mda, ETH_ALEN);\n\t\t} else {\n\t\t\txattrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA;\n\t\t\t_rtw_memcpy(xattrib->ra, fwd_ra, ETH_ALEN);\n\t\t}\n\n\t\t*fwd_frame = xframe;\n\t}\n\n\tact |= RTW_RX_MSDU_ACT_FORWARD;\n\tif (is_mda_bmc)\n\t\tminfo->mshstats.fwded_mcast++;\n\telse\n\t\tminfo->mshstats.fwded_unicast++;\n\tminfo->mshstats.fwded_frames++;\n\nexit:\n\treturn act;\n}\n\nvoid dump_mesh_stats(void *sel, _adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct rtw_mesh_stats *stats = &minfo->mshstats;\n\n\tRTW_PRINT_SEL(sel, \"fwd_bmc:%u\\n\", stats->fwded_mcast);\n\tRTW_PRINT_SEL(sel, \"fwd_uc:%u\\n\", stats->fwded_unicast);\n\n\tRTW_PRINT_SEL(sel, \"drop_ttl:%u\\n\", stats->dropped_frames_ttl);\n\tRTW_PRINT_SEL(sel, \"drop_no_route:%u\\n\", stats->dropped_frames_no_route);\n\tRTW_PRINT_SEL(sel, \"drop_congestion:%u\\n\", stats->dropped_frames_congestion);\n\tRTW_PRINT_SEL(sel, \"drop_dup:%u\\n\", stats->dropped_frames_duplicate);\n\n\tRTW_PRINT_SEL(sel, \"mrc_del_qlen:%u\\n\", stats->mrc_del_qlen);\n}\n#endif /* CONFIG_RTW_MESH */\n\n"
  },
  {
    "path": "core/mesh/rtw_mesh.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_MESH_H_\n#define __RTW_MESH_H_\n\n#ifndef CONFIG_AP_MODE\n\t#error \"CONFIG_RTW_MESH can't be enabled when CONFIG_AP_MODE is not defined\\n\"\n#endif\n\n#define RTW_MESH_TTL\t\t\t\t31\n#define RTW_MESH_PERR_MIN_INT\t\t\t100\n#define RTW_MESH_DEFAULT_ELEMENT_TTL\t\t31\n#define RTW_MESH_RANN_INTERVAL\t\t\t5000\n#define RTW_MESH_PATH_TO_ROOT_TIMEOUT\t\t6000\n#define RTW_MESH_DIAM_TRAVERSAL_TIME\t\t50\n#define RTW_MESH_PATH_TIMEOUT\t\t\t5000\n#define RTW_MESH_PREQ_MIN_INT\t\t\t10\n#define RTW_MESH_MAX_PREQ_RETRIES\t\t4\n#define RTW_MESH_MIN_DISCOVERY_TIMEOUT \t\t(2 * RTW_MESH_DIAM_TRAVERSAL_TIME)\n#define RTW_MESH_ROOT_CONFIRMATION_INTERVAL\t2000\n#define RTW_MESH_PATH_REFRESH_TIME\t\t1000\n#define RTW_MESH_ROOT_INTERVAL\t\t\t5000\n\n#define RTW_MESH_SANE_METRIC_DELTA\t\t100\n#define RTW_MESH_MAX_ROOT_ADD_CHK_CNT\t\t2\n\n#define RTW_MESH_PLINK_UNKNOWN\t0\n#define RTW_MESH_PLINK_LISTEN\t1\n#define RTW_MESH_PLINK_OPN_SNT\t2\n#define RTW_MESH_PLINK_OPN_RCVD 3\n#define RTW_MESH_PLINK_CNF_RCVD 4\n#define RTW_MESH_PLINK_ESTAB\t5\n#define RTW_MESH_PLINK_HOLDING\t6\n#define RTW_MESH_PLINK_BLOCKED\t7\n\nextern const char *_rtw_mesh_plink_str[];\n#define rtw_mesh_plink_str(s) ((s <= RTW_MESH_PLINK_BLOCKED) ? _rtw_mesh_plink_str[s] : _rtw_mesh_plink_str[RTW_MESH_PLINK_UNKNOWN])\n\n#define RTW_MESH_PS_UNKNOWN 0\n#define RTW_MESH_PS_ACTIVE 1\n#define RTW_MESH_PS_LSLEEP 2\n#define RTW_MESH_PS_DSLEEP 3\n\nextern const char *_rtw_mesh_ps_str[];\n#define rtw_mesh_ps_str(mps) ((mps <= RTW_MESH_PS_DSLEEP) ? _rtw_mesh_ps_str[mps] : _rtw_mesh_ps_str[RTW_MESH_PS_UNKNOWN])\n\n#define GET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(_iec)\t\tLE_BITS_TO_1BYTE(((u8 *)(_iec)) + 0, 0, 8)\n#define GET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(_iec)\t\tLE_BITS_TO_1BYTE(((u8 *)(_iec)) + 1, 0, 8)\n#define GET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(_iec)\tLE_BITS_TO_1BYTE(((u8 *)(_iec)) + 2, 0, 8)\n#define GET_MESH_CONF_ELE_SYNC_METHOD_ID(_iec)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_iec)) + 3, 0, 8)\n#define GET_MESH_CONF_ELE_AUTH_PROTO_ID(_iec)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_iec)) + 4, 0, 8)\n\n#define GET_MESH_CONF_ELE_MESH_FORMATION(_iec)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 0, 8)\n#define GET_MESH_CONF_ELE_CTO_MGATE(_iec)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 0, 1)\n#define GET_MESH_CONF_ELE_NUM_OF_PEERINGS(_iec)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 1, 6)\n#define GET_MESH_CONF_ELE_CTO_AS(_iec)\t\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 7, 1)\n\n#define GET_MESH_CONF_ELE_MESH_CAP(_iec)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 0, 8)\n#define GET_MESH_CONF_ELE_ACCEPT_PEERINGS(_iec)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 0, 1)\n#define GET_MESH_CONF_ELE_MCCA_SUP(_iec)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 1, 1)\n#define GET_MESH_CONF_ELE_MCCA_EN(_iec)\t\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 2, 1)\n#define GET_MESH_CONF_ELE_FORWARDING(_iec)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 3, 1)\n#define GET_MESH_CONF_ELE_MBCA_EN(_iec)\t\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 4, 1)\n#define GET_MESH_CONF_ELE_TBTT_ADJ(_iec)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 5, 1)\n#define GET_MESH_CONF_ELE_PS_LEVEL(_iec)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 6, 1)\n\n#define SET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(_iec, _val)\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 0, 0, 8, _val)\n#define SET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(_iec, _val)\tSET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 1, 0, 8, _val)\n#define SET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(_iec, _val)\tSET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 2, 0, 8, _val)\n#define SET_MESH_CONF_ELE_SYNC_METHOD_ID(_iec, _val)\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 3, 0, 8, _val)\n#define SET_MESH_CONF_ELE_AUTH_PROTO_ID(_iec, _val)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 4, 0, 8, _val)\n\n#define SET_MESH_CONF_ELE_CTO_MGATE(_iec, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 0, 1, _val)\n#define SET_MESH_CONF_ELE_NUM_OF_PEERINGS(_iec, _val)\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 1, 6, _val)\n#define SET_MESH_CONF_ELE_CTO_AS(_iec, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 7, 1, _val)\n\n#define SET_MESH_CONF_ELE_ACCEPT_PEERINGS(_iec, _val)\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 0, 1, _val)\n#define SET_MESH_CONF_ELE_MCCA_SUP(_iec, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 1, 1, _val)\n#define SET_MESH_CONF_ELE_MCCA_EN(_iec, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 2, 1, _val)\n#define SET_MESH_CONF_ELE_FORWARDING(_iec, _val)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 3, 1, _val)\n#define SET_MESH_CONF_ELE_MBCA_EN(_iec, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 4, 1, _val)\n#define SET_MESH_CONF_ELE_TBTT_ADJ(_iec, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 5, 1, _val)\n#define SET_MESH_CONF_ELE_PS_LEVEL(_iec, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 6, 1, _val)\n\n/* Mesh flags */\n#define MESH_FLAGS_AE\t\t0x3 /* mask */\n#define MESH_FLAGS_AE_A4 \t0x1\n#define MESH_FLAGS_AE_A5_A6\t0x2\n\n/* Max number of paths */\n#define RTW_MESH_MAX_PATHS 1024\n\n#define RTW_PREQ_Q_F_START\t0x1\n#define RTW_PREQ_Q_F_REFRESH\t0x2\n#define RTW_PREQ_Q_F_CHK\t0x4\n#define RTW_PREQ_Q_F_PEER_AKA\t0x8\n#define RTW_PREQ_Q_F_BCAST_PREQ\t0x10 /* force path_dicover using broadcast */\nstruct rtw_mesh_preq_queue {\n\t_list list;\n\tu8 dst[ETH_ALEN];\n\tu8 flags;\n};\n\nextern const u8 ae_to_mesh_ctrl_len[];\n\nenum mesh_frame_type {\n\tMESH_UCAST_DATA\t\t= 0x0,\n\tMESH_BMCAST_DATA\t= 0x1,\n\tMESH_UCAST_PX_DATA\t= 0x2,\n\tMESH_BMCAST_PX_DATA\t= 0x3,\n\tMESH_MHOP_UCAST_ACT\t= 0x4,\n\tMESH_MHOP_BMCAST_ACT\t= 0x5,\n};\n\nenum mpath_sel_frame_type {\n\tMPATH_PREQ = 0,\n\tMPATH_PREP,\n\tMPATH_PERR,\n\tMPATH_RANN\n};\n\n/**\n * enum rtw_mesh_deferred_task_flags - mesh deferred tasks\n *\n *\n *\n * @RTW_MESH_WORK_HOUSEKEEPING: run the periodic mesh housekeeping tasks\n * @RTW_MESH_WORK_ROOT: the mesh root station needs to send a frame\n * @RTW_MESH_WORK_DRIFT_ADJUST: time to compensate for clock drift relative to other\n * mesh nodes\n * @RTW_MESH_WORK_MBSS_CHANGED: rebuild beacon and notify driver of BSS changes\n */\nenum rtw_mesh_deferred_task_flags {\n\tRTW_MESH_WORK_HOUSEKEEPING,\n\tRTW_MESH_WORK_ROOT,\n\tRTW_MESH_WORK_DRIFT_ADJUST,\n\tRTW_MESH_WORK_MBSS_CHANGED,\n};\n\n#define RTW_MESH_MAX_PEER_CANDIDATES 15 /* aid consideration */\n#define RTW_MESH_MAX_PEER_LINKS 8\n#define RTW_MESH_PEER_LINK_TIMEOUT 20\n\n#define RTW_MESH_PEER_CONF_DISABLED 0 /* special time value means no confirmation ongoing */\n#if CONFIG_RTW_MESH_PEER_BLACKLIST\n#define IS_PEER_CONF_DISABLED(plink) ((plink)->peer_conf_end_time == RTW_MESH_PEER_CONF_DISABLED)\n#define IS_PEER_CONF_TIMEOUT(plink)(!IS_PEER_CONF_DISABLED(plink) && rtw_time_after(rtw_get_current_time(), (plink)->peer_conf_end_time))\n#define SET_PEER_CONF_DISABLED(plink) (plink)->peer_conf_end_time = RTW_MESH_PEER_CONF_DISABLED\n#define SET_PEER_CONF_END_TIME(plink, timeout_ms) \\\n\tdo { \\\n\t\t(plink)->peer_conf_end_time = rtw_get_current_time() + rtw_ms_to_systime(timeout_ms); \\\n\t\tif ((plink)->peer_conf_end_time == RTW_MESH_PEER_CONF_DISABLED) \\\n\t\t\t(plink)->peer_conf_end_time++; \\\n\t} while (0)\n#else\n#define IS_PEER_CONF_DISABLED(plink) 1\n#define IS_PEER_CONF_TIMEOUT(plink) 0\n#define SET_PEER_CONF_DISABLED(plink) do {} while (0)\n#define SET_PEER_CONF_END_TIME(plink, timeout_ms) do {} while (0)\n#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */\n\n#define RTW_MESH_CTO_MGATE_CONF_DISABLED 0 /* special time value means no confirmation ongoing */\n#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n#define IS_CTO_MGATE_CONF_DISABLED(plink) ((plink)->cto_mgate_conf_end_time == RTW_MESH_CTO_MGATE_CONF_DISABLED)\n#define IS_CTO_MGATE_CONF_TIMEOUT(plink)(!IS_CTO_MGATE_CONF_DISABLED(plink) && rtw_time_after(rtw_get_current_time(), (plink)->cto_mgate_conf_end_time))\n#define SET_CTO_MGATE_CONF_DISABLED(plink) (plink)->cto_mgate_conf_end_time = RTW_MESH_CTO_MGATE_CONF_DISABLED\n#define SET_CTO_MGATE_CONF_END_TIME(plink, timeout_ms) \\\n\tdo { \\\n\t\t(plink)->cto_mgate_conf_end_time = rtw_get_current_time() + rtw_ms_to_systime(timeout_ms); \\\n\t\tif ((plink)->cto_mgate_conf_end_time == RTW_MESH_CTO_MGATE_CONF_DISABLED) \\\n\t\t\t(plink)->cto_mgate_conf_end_time++; \\\n\t} while (0)\n#else\n#define IS_CTO_MGATE_CONF_DISABLED(plink) 1\n#define IS_CTO_MGATE_CONF_TIMEOUT(plink) 0\n#define SET_CTO_MGATE_CONF_DISABLED(plink) do {} while (0)\n#define SET_CTO_MGATE_CONF_END_TIME(plink, timeout_ms) do {} while (0)\n#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */\n\nstruct mesh_plink_ent {\n\tu8 valid;\n\tu8 addr[ETH_ALEN];\n\tu8 plink_state;\n\n#ifdef CONFIG_RTW_MESH_AEK\n\tu8 aek_valid;\n\tu8 aek[32];\n#endif\n\n\tu16 llid;\n\tu16 plid;\n#ifndef CONFIG_RTW_MESH_DRIVER_AID\n\tu16 aid; /* aid assigned from upper layer */\n#endif\n\tu16 peer_aid; /* aid assigned from peer */\n\n\tu8 chosen_pmk[16];\n\n#ifdef CONFIG_RTW_MESH_AEK\n\tu8 sel_pcs[4];\n\tu8 l_nonce[32];\n\tu8 p_nonce[32];\n#endif\n\n#ifdef CONFIG_RTW_MESH_DRIVER_AID\n\tu8 *tx_conf_ies;\n\tu16 tx_conf_ies_len;\n#endif\n\tu8 *rx_conf_ies;\n\tu16 rx_conf_ies_len;\n\n\tstruct wlan_network *scanned;\n\n#if CONFIG_RTW_MESH_PEER_BLACKLIST\n\tsystime peer_conf_end_time;\n#endif\n#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\tsystime cto_mgate_conf_end_time;\n#endif\n};\n\n#ifdef CONFIG_RTW_MESH_AEK\n#define MESH_PLINK_AEK_VALID(ent) ent->aek_valid\n#else\n#define MESH_PLINK_AEK_VALID(ent) 0\n#endif\n\nstruct mesh_plink_pool {\n\t_lock lock;\n\tu8 num; /* current ent being used */\n\tstruct mesh_plink_ent ent[RTW_MESH_MAX_PEER_CANDIDATES];\n\n#if CONFIG_RTW_MESH_ACNODE_PREVENT\n\tu8 acnode_rsvd;\n#endif\n\n#if CONFIG_RTW_MESH_PEER_BLACKLIST\n\t_queue peer_blacklist;\n#endif\n#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\t_queue cto_mgate_blacklist;\n#endif\n};\n\nstruct mesh_peer_sel_policy {\n\tu32 scanr_exp_ms;\n\n#if CONFIG_RTW_MESH_ACNODE_PREVENT\n\tu8 acnode_prevent;\n\tu32 acnode_conf_timeout_ms;\n\tu32 acnode_notify_timeout_ms;\n#endif\n\n#if CONFIG_RTW_MESH_OFFCH_CAND\n\tu8 offch_cand;\n\tu32 offch_find_int_ms; /* 0 means no offch find triggerred by driver self*/\n#endif\n\n#if CONFIG_RTW_MESH_PEER_BLACKLIST\n\tu32 peer_conf_timeout_ms;\n\tu32 peer_blacklist_timeout_ms;\n#endif\n\n#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\tu8 cto_mgate_require;\n\tu32 cto_mgate_conf_timeout_ms;\n\tu32 cto_mgate_blacklist_timeout_ms;\n#endif\n};\n\n/* b2u flags */\n#define RTW_MESH_B2U_ALL\t\tBIT0\n#define RTW_MESH_B2U_GA_UCAST\tBIT1 /* Group addressed unicast frame, forward only */\n#define RTW_MESH_B2U_BCAST\t\tBIT2\n#define RTW_MESH_B2U_IP_MCAST\tBIT3\n\n#define rtw_msrc_b2u_policy_chk(flags, mda) ( \\\n\t(flags & RTW_MESH_B2U_ALL) \\\n\t|| ((flags & RTW_MESH_B2U_BCAST) && is_broadcast_mac_addr(mda)) \\\n\t|| ((flags & RTW_MESH_B2U_IP_MCAST) && (IP_MCAST_MAC(mda) || ICMPV6_MCAST_MAC(mda))) \\\n\t)\n\n#define rtw_mfwd_b2u_policy_chk(flags, mda, ucst) ( \\\n\t(flags & RTW_MESH_B2U_ALL) \\\n\t|| ((flags & RTW_MESH_B2U_GA_UCAST) && ucst) \\\n\t|| ((flags & RTW_MESH_B2U_BCAST) && is_broadcast_mac_addr(mda)) \\\n\t|| ((flags & RTW_MESH_B2U_IP_MCAST) && (IP_MCAST_MAC(mda) || ICMPV6_MCAST_MAC(mda))) \\\n\t)\n\n/**\n * @sane_metric_delta: Controlling if trigger additional path check mechanism\n * @max_root_add_chk_cnt: The retry cnt to send additional root confirmation\n *\tPREQ through old(last) path\n */\nstruct rtw_mesh_cfg {\n\tu8 max_peer_links; /* peering limit */\n\tu32 plink_timeout; /* seconds */\n\n\tu8 dot11MeshTTL;\n\tu8 element_ttl;\n\tu32 path_refresh_time;\n\tu16 dot11MeshHWMPpreqMinInterval;\n\tu16 dot11MeshHWMPnetDiameterTraversalTime;\n\tu32 dot11MeshHWMPactivePathTimeout;\n\tu8 dot11MeshHWMPmaxPREQretries;\n\tu16 min_discovery_timeout;\n\tu16 dot11MeshHWMPconfirmationInterval;\n\tu16 dot11MeshHWMPperrMinInterval;\n\tu8 dot11MeshHWMPRootMode;\n\tBOOLEAN dot11MeshForwarding;\n\ts32 rssi_threshold; /* in dBm, 0: no specified */\n\tu16 dot11MeshHWMPRannInterval;\n\tBOOLEAN dot11MeshGateAnnouncementProtocol;\n\tu32 dot11MeshHWMPactivePathToRootTimeout;\n\tu16 dot11MeshHWMProotInterval;\n\tu8 path_gate_timeout_factor;\n#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK\n\tu16 sane_metric_delta;\n\tu8 max_root_add_chk_cnt;\n#endif\n\n\tstruct mesh_peer_sel_policy peer_sel_policy;\n\n#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\tu8 b2u_flags_msrc;\n\tu8 b2u_flags_mfwd;\n#endif\n};\n\nstruct rtw_mesh_stats {\n\tu32 fwded_mcast;\t\t/* Mesh forwarded multicast frames */\n\tu32 fwded_unicast;\t\t/* Mesh forwarded unicast frames */\n\tu32 fwded_frames;\t\t/* Mesh total forwarded frames */\n\tu32 dropped_frames_ttl;\t/* Not transmitted since mesh_ttl == 0*/\n\tu32 dropped_frames_no_route;\t/* Not transmitted, no route found */\n\tu32 dropped_frames_congestion;/* Not forwarded due to congestion */\n\tu32 dropped_frames_duplicate;\n\n\tu32 mrc_del_qlen; /* MRC entry deleted cause by queue length limit */\n};\n\nstruct rtw_mrc;\n\nstruct rtw_mesh_info {\n\tu8 mesh_id[NDIS_802_11_LENGTH_SSID];\n\tsize_t mesh_id_len;\n\t/* Active Path Selection Protocol Identifier */\n\tu8 mesh_pp_id;\n\t/* Active Path Selection Metric Identifier */\n\tu8 mesh_pm_id;\n\t/* Congestion Control Mode Identifier */\n\tu8 mesh_cc_id;\n\t/* Synchronization Protocol Identifier */\n\tu8 mesh_sp_id;\n\t/* Authentication Protocol Identifier */\n\tu8 mesh_auth_id;\n\n\tstruct mesh_plink_pool plink_ctl;\n\n\tu32 mesh_seqnum;\n\t/* MSTA's own hwmp sequence number */\n\tu32 sn;\n\tsystime last_preq;\n\tsystime last_sn_update;\n\tsystime next_perr;\n\t/* Last used Path Discovery ID */\n\tu32 preq_id;\n\t\n\tATOMIC_T mpaths;\n\tstruct rtw_mesh_table *mesh_paths;\n\tstruct rtw_mesh_table *mpp_paths;\n\tint mesh_paths_generation;\n\tint mpp_paths_generation;\n\n\tint num_gates;\n\tstruct rtw_mesh_path *max_addr_gate;\n\tbool max_addr_gate_is_larger_than_self;\n\n\tstruct rtw_mesh_stats mshstats;\n\n\t_queue mpath_tx_queue;\n\tu32 mpath_tx_queue_len;\n\t_tasklet mpath_tx_tasklet;\n\n\tstruct rtw_mrc *mrc;\n\n\t_lock mesh_preq_queue_lock;\n\tstruct rtw_mesh_preq_queue preq_queue;\n\tint preq_queue_len;\n};\n\nextern const char *_action_self_protected_str[];\n#define action_self_protected_str(action) ((action < RTW_ACT_SELF_PROTECTED_NUM) ? _action_self_protected_str[action] : _action_self_protected_str[0])\n\nu8 *rtw_set_ie_mesh_id(u8 *buf, u32 *buf_len, const char *mesh_id, u8 id_len);\nu8 *rtw_set_ie_mesh_config(u8 *buf, u32 *buf_len\n\t, u8 path_sel_proto, u8 path_sel_metric, u8 congest_ctl_mode, u8 sync_method, u8 auth_proto\n\t, u8 num_of_peerings, bool cto_mgate, bool cto_as\n\t, bool accept_peerings, bool mcca_sup, bool mcca_en, bool forwarding\n\t, bool mbca_en, bool tbtt_adj, bool ps_level);\n\nint rtw_bss_is_same_mbss(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b);\nint rtw_bss_is_candidate_mesh_peer(WLAN_BSSID_EX *self, WLAN_BSSID_EX *target, u8 ch, u8 add_peer);\n\nvoid rtw_chk_candidate_peer_notify(_adapter *adapter, struct wlan_network *scanned);\n\nvoid rtw_mesh_peer_status_chk(_adapter *adapter);\n\n#if CONFIG_RTW_MESH_ACNODE_PREVENT\nvoid rtw_mesh_update_scanned_acnode_status(_adapter *adapter, struct wlan_network *scanned);\nbool rtw_mesh_scanned_is_acnode_confirmed(_adapter *adapter, struct wlan_network *scanned);\nbool rtw_mesh_acnode_prevent_allow_sacrifice(_adapter *adapter);\nstruct sta_info *rtw_mesh_acnode_prevent_pick_sacrifice(_adapter *adapter);\nvoid dump_mesh_acnode_prevent_settings(void *sel, _adapter *adapter);\n#endif\n\n#if CONFIG_RTW_MESH_OFFCH_CAND\nu8 rtw_mesh_offch_candidate_accepted(_adapter *adapter);\nu8 rtw_mesh_select_operating_ch(_adapter *adapter);\nvoid dump_mesh_offch_cand_settings(void *sel, _adapter *adapter);\n#endif\n\n#if CONFIG_RTW_MESH_PEER_BLACKLIST\nint rtw_mesh_peer_blacklist_add(_adapter *adapter, const u8 *addr);\nint rtw_mesh_peer_blacklist_del(_adapter *adapter, const u8 *addr);\nint rtw_mesh_peer_blacklist_search(_adapter *adapter, const u8 *addr);\nvoid rtw_mesh_peer_blacklist_flush(_adapter *adapter);\nvoid dump_mesh_peer_blacklist(void *sel, _adapter *adapter);\nvoid dump_mesh_peer_blacklist_settings(void *sel, _adapter *adapter);\n#endif\n#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\nu8 rtw_mesh_cto_mgate_required(_adapter *adapter);\nu8 rtw_mesh_cto_mgate_network_filter(_adapter *adapter, struct wlan_network *scanned);\nint rtw_mesh_cto_mgate_blacklist_add(_adapter *adapter, const u8 *addr);\nint rtw_mesh_cto_mgate_blacklist_del(_adapter *adapter, const u8 *addr);\nint rtw_mesh_cto_mgate_blacklist_search(_adapter *adapter, const u8 *addr);\nvoid rtw_mesh_cto_mgate_blacklist_flush(_adapter *adapter);\nvoid dump_mesh_cto_mgate_blacklist(void *sel, _adapter *adapter);\nvoid dump_mesh_cto_mgate_blacklist_settings(void *sel, _adapter *adapter);\n#endif\nvoid dump_mesh_peer_sel_policy(void *sel, _adapter *adapter);\nvoid dump_mesh_networks(void *sel, _adapter *adapter);\n\nvoid rtw_mesh_adjust_chbw(u8 req_ch, u8 *req_bw, u8 *req_offset);\n\nvoid rtw_mesh_sae_check_frames(_adapter *adapter, const u8 *buf, u32 len, u8 tx, u16 alg, u16 seq, u16 status);\nint rtw_mesh_check_frames_tx(_adapter *adapter, const u8 **buf, size_t *len);\nint rtw_mesh_check_frames_rx(_adapter *adapter, const u8 *buf, size_t len);\n\nint rtw_mesh_on_auth(_adapter *adapter, union recv_frame *rframe);\nunsigned int on_action_self_protected(_adapter *adapter, union recv_frame *rframe);\n\nbool rtw_mesh_update_bss_peering_status(_adapter *adapter, WLAN_BSSID_EX *bss);\nbool rtw_mesh_update_bss_formation_info(_adapter *adapter, WLAN_BSSID_EX *bss);\nbool rtw_mesh_update_bss_forwarding_state(_adapter *adapter, WLAN_BSSID_EX *bss);\n\nstruct mesh_plink_ent *_rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr);\nstruct mesh_plink_ent *rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr);\nstruct mesh_plink_ent *rtw_mesh_plink_get_no_estab_by_idx(_adapter *adapter, u8 idx);\nint _rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr);\nint rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr);\nint rtw_mesh_plink_set_state(_adapter *adapter, const u8 *hwaddr, u8 state);\n#ifdef CONFIG_RTW_MESH_AEK\nint rtw_mesh_plink_set_aek(_adapter *adapter, const u8 *hwaddr, const u8 *aek);\n#endif\n#if CONFIG_RTW_MESH_PEER_BLACKLIST\nint rtw_mesh_plink_set_peer_conf_timeout(_adapter *adapter, const u8 *hwaddr);\n#endif\nvoid _rtw_mesh_plink_del_ent(_adapter *adapter, struct mesh_plink_ent *ent);\nint rtw_mesh_plink_del(_adapter *adapter, const u8 *hwaddr);\nvoid rtw_mesh_plink_ctl_init(_adapter *adapter);\nvoid rtw_mesh_plink_ctl_deinit(_adapter *adapter);\nvoid dump_mesh_plink_ctl(void *sel, _adapter *adapter);\n\nint rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *plink, struct sta_info *sta);\nvoid _rtw_mesh_expire_peer_ent(_adapter *adapter, struct mesh_plink_ent *plink);\nvoid rtw_mesh_expire_peer(_adapter *adapter, const u8 *peer_addr);\nu8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps);\n\nunsigned int on_action_mesh(_adapter *adapter, union recv_frame *rframe);\n\nvoid rtw_mesh_cfg_init(_adapter *adapter);\nvoid rtw_mesh_cfg_init_max_peer_links(_adapter *adapter, u8 stack_conf);\nvoid rtw_mesh_cfg_init_plink_timeout(_adapter *adapter, u32 stack_conf);\nvoid rtw_mesh_init_mesh_info(_adapter *adapter);\nvoid rtw_mesh_deinit_mesh_info(_adapter *adapter);\n\n#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\nvoid dump_mesh_b2u_flags(void *sel, _adapter *adapter);\n#endif\n\nint rtw_mesh_addr_resolve(_adapter *adapter, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list);\n\ns8 rtw_mesh_tx_set_whdr_mctrl_len(u8 mesh_frame_mode, struct pkt_attrib *attrib);\nvoid rtw_mesh_tx_build_mctrl(_adapter *adapter, struct pkt_attrib *attrib, u8 *buf);\nu8 rtw_mesh_tx_build_whdr(_adapter *adapter, struct pkt_attrib *attrib\n\t, u16 *fctrl, struct rtw_ieee80211_hdr *whdr);\n\nint rtw_mesh_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta);\nint rtw_mesh_rx_data_validate_mctrl(_adapter *adapter, union recv_frame *rframe\n\t, const struct rtw_ieee80211s_hdr *mctrl, const u8 *mda, const u8 *msa\n\t, u8 *mctrl_len, const u8 **da, const u8 **sa);\nint rtw_mesh_rx_validate_mctrl_non_amsdu(_adapter *adapter, union recv_frame *rframe);\n\nint rtw_mesh_rx_msdu_act_check(union recv_frame *rframe\n\t, const u8 *mda, const u8 *msa\n\t, const u8 *da, const u8 *sa\n\t, struct rtw_ieee80211s_hdr *mctrl\n\t, struct xmit_frame **fwd_frame, _list *b2u_list);\n\nvoid dump_mesh_stats(void *sel, _adapter *adapter);\n\n#if defined(PLATFORM_LINUX) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32))\n#define rtw_lockdep_assert_held(l) lockdep_assert_held(l)\n#define rtw_lockdep_is_held(l) lockdep_is_held(l)\n#else\n#error \"TBD\\n\"\n#endif\n\n#include \"rtw_mesh_pathtbl.h\"\n#include \"rtw_mesh_hwmp.h\"\n#endif /* __RTW_MESH_H_ */\n\n"
  },
  {
    "path": "core/mesh/rtw_mesh_hwmp.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_HWMP_C_\n\n#ifdef CONFIG_RTW_MESH\n#include <drv_types.h>\n#include <hal_data.h>\n\n#define RTW_TEST_FRAME_LEN\t8192\n#define RTW_MAX_METRIC\t0xffffffff\n#define RTW_ARITH_SHIFT\t8\n#define RTW_LINK_FAIL_THRESH 95\n#define RTW_MAX_PREQ_QUEUE_LEN\t64\n#define RTW_ATLM_REQ_CYCLE 1000\n\n#define rtw_ilog2(n)\t\t\t\\\n(\t\t\t\t\t\\\n\t(n) < 2 ? 0 :\t\t\t\\\n\t(n) & (1ULL << 63) ? 63 :\t\\\n\t(n) & (1ULL << 62) ? 62 :\t\\\n\t(n) & (1ULL << 61) ? 61 :\t\\\n\t(n) & (1ULL << 60) ? 60 :\t\\\n\t(n) & (1ULL << 59) ? 59 :\t\\\n\t(n) & (1ULL << 58) ? 58 :\t\\\n\t(n) & (1ULL << 57) ? 57 :\t\\\n\t(n) & (1ULL << 56) ? 56 :\t\\\n\t(n) & (1ULL << 55) ? 55 :\t\\\n\t(n) & (1ULL << 54) ? 54 :\t\\\n\t(n) & (1ULL << 53) ? 53 :\t\\\n\t(n) & (1ULL << 52) ? 52 :\t\\\n\t(n) & (1ULL << 51) ? 51 :\t\\\n\t(n) & (1ULL << 50) ? 50 :\t\\\n\t(n) & (1ULL << 49) ? 49 :\t\\\n\t(n) & (1ULL << 48) ? 48 :\t\\\n\t(n) & (1ULL << 47) ? 47 :\t\\\n\t(n) & (1ULL << 46) ? 46 :\t\\\n\t(n) & (1ULL << 45) ? 45 :\t\\\n\t(n) & (1ULL << 44) ? 44 :\t\\\n\t(n) & (1ULL << 43) ? 43 :\t\\\n\t(n) & (1ULL << 42) ? 42 :\t\\\n\t(n) & (1ULL << 41) ? 41 :\t\\\n\t(n) & (1ULL << 40) ? 40 :\t\\\n\t(n) & (1ULL << 39) ? 39 :\t\\\n\t(n) & (1ULL << 38) ? 38 :\t\\\n\t(n) & (1ULL << 37) ? 37 :\t\\\n\t(n) & (1ULL << 36) ? 36 :\t\\\n\t(n) & (1ULL << 35) ? 35 :\t\\\n\t(n) & (1ULL << 34) ? 34 :\t\\\n\t(n) & (1ULL << 33) ? 33 :\t\\\n\t(n) & (1ULL << 32) ? 32 :\t\\\n\t(n) & (1ULL << 31) ? 31 :\t\\\n\t(n) & (1ULL << 30) ? 30 :\t\\\n\t(n) & (1ULL << 29) ? 29 :\t\\\n\t(n) & (1ULL << 28) ? 28 :\t\\\n\t(n) & (1ULL << 27) ? 27 :\t\\\n\t(n) & (1ULL << 26) ? 26 :\t\\\n\t(n) & (1ULL << 25) ? 25 :\t\\\n\t(n) & (1ULL << 24) ? 24 :\t\\\n\t(n) & (1ULL << 23) ? 23 :\t\\\n\t(n) & (1ULL << 22) ? 22 :\t\\\n\t(n) & (1ULL << 21) ? 21 :\t\\\n\t(n) & (1ULL << 20) ? 20 :\t\\\n\t(n) & (1ULL << 19) ? 19 :\t\\\n\t(n) & (1ULL << 18) ? 18 :\t\\\n\t(n) & (1ULL << 17) ? 17 :\t\\\n\t(n) & (1ULL << 16) ? 16 :\t\\\n\t(n) & (1ULL << 15) ? 15 :\t\\\n\t(n) & (1ULL << 14) ? 14 :\t\\\n\t(n) & (1ULL << 13) ? 13 :\t\\\n\t(n) & (1ULL << 12) ? 12 :\t\\\n\t(n) & (1ULL << 11) ? 11 :\t\\\n\t(n) & (1ULL << 10) ? 10 :\t\\\n\t(n) & (1ULL <<  9) ?  9 :\t\\\n\t(n) & (1ULL <<  8) ?  8 :\t\\\n\t(n) & (1ULL <<  7) ?  7 :\t\\\n\t(n) & (1ULL <<  6) ?  6 :\t\\\n\t(n) & (1ULL <<  5) ?  5 :\t\\\n\t(n) & (1ULL <<  4) ?  4 :\t\\\n\t(n) & (1ULL <<  3) ?  3 :\t\\\n\t(n) & (1ULL <<  2) ?  2 :\t\\\n\t1\t\t\t\t\\\n)\n\nenum rtw_mpath_frame_type {\n\tRTW_MPATH_PREQ = 0,\n\tRTW_MPATH_PREP,\n\tRTW_MPATH_PERR,\n\tRTW_MPATH_RANN\n};\n\nstatic inline u32 rtw_u32_field_get(const u8 *preq_elem, int shift, BOOLEAN ae)\n{\n\tif (ae)\n\t\tshift += 6;\n\treturn LE_BITS_TO_4BYTE(preq_elem + shift, 0, 32);\n}\n\nstatic inline u16 rtw_u16_field_get(const u8 *preq_elem, int shift, BOOLEAN ae)\n{\n\tif (ae)\n\t\tshift += 6;\n\treturn LE_BITS_TO_2BYTE(preq_elem + shift, 0, 16);\n}\n\n/* HWMP IE processing macros */\n#define RTW_AE_F\t\t\t(1<<6)\n#define RTW_AE_F_SET(x)\t\t\t(*x & RTW_AE_F)\n#define RTW_PREQ_IE_FLAGS(x)\t\t(*(x))\n#define RTW_PREQ_IE_HOPCOUNT(x)\t\t(*(x + 1))\n#define RTW_PREQ_IE_TTL(x)\t\t(*(x + 2))\n#define RTW_PREQ_IE_PREQ_ID(x)\t\trtw_u32_field_get(x, 3, 0)\n#define RTW_PREQ_IE_ORIG_ADDR(x)\t(x + 7)\n#define RTW_PREQ_IE_ORIG_SN(x)\t\trtw_u32_field_get(x, 13, 0)\n#define RTW_PREQ_IE_LIFETIME(x)\t\trtw_u32_field_get(x, 17, RTW_AE_F_SET(x))\n#define RTW_PREQ_IE_METRIC(x) \t\trtw_u32_field_get(x, 21, RTW_AE_F_SET(x))\n#define RTW_PREQ_IE_TARGET_F(x)\t\t(*(RTW_AE_F_SET(x) ? x + 32 : x + 26))\n#define RTW_PREQ_IE_TARGET_ADDR(x) \t(RTW_AE_F_SET(x) ? x + 33 : x + 27)\n#define RTW_PREQ_IE_TARGET_SN(x) \trtw_u32_field_get(x, 33, RTW_AE_F_SET(x))\n\n#define RTW_PREP_IE_FLAGS(x)\t\tRTW_PREQ_IE_FLAGS(x)\n#define RTW_PREP_IE_HOPCOUNT(x)\t\tRTW_PREQ_IE_HOPCOUNT(x)\n#define RTW_PREP_IE_TTL(x)\t\tRTW_PREQ_IE_TTL(x)\n#define RTW_PREP_IE_ORIG_ADDR(x)\t(RTW_AE_F_SET(x) ? x + 27 : x + 21)\n#define RTW_PREP_IE_ORIG_SN(x)\t\trtw_u32_field_get(x, 27, RTW_AE_F_SET(x))\n#define RTW_PREP_IE_LIFETIME(x)\t\trtw_u32_field_get(x, 13, RTW_AE_F_SET(x))\n#define RTW_PREP_IE_METRIC(x)\t\trtw_u32_field_get(x, 17, RTW_AE_F_SET(x))\n#define RTW_PREP_IE_TARGET_ADDR(x)\t(x + 3)\n#define RTW_PREP_IE_TARGET_SN(x)\trtw_u32_field_get(x, 9, 0)\n\n#define RTW_PERR_IE_TTL(x)\t\t(*(x))\n#define RTW_PERR_IE_TARGET_FLAGS(x)\t(*(x + 2))\n#define RTW_PERR_IE_TARGET_ADDR(x)\t(x + 3)\n#define RTW_PERR_IE_TARGET_SN(x)\trtw_u32_field_get(x, 9, 0)\n#define RTW_PERR_IE_TARGET_RCODE(x)\trtw_u16_field_get(x, 13, 0)\n\n#define RTW_TU_TO_SYSTIME(x)\t(rtw_us_to_systime((x) * 1024))\n#define RTW_TU_TO_EXP_TIME(x)\t(rtw_get_current_time() + RTW_TU_TO_SYSTIME(x))\n#define RTW_MSEC_TO_TU(x) (x*1000/1024)\n#define RTW_SN_GT(x, y) ((s32)(y - x) < 0)\n#define RTW_SN_LT(x, y) ((s32)(x - y) < 0)\n#define RTW_MAX_SANE_SN_DELTA 32\n\nstatic inline u32 RTW_SN_DELTA(u32 x, u32 y)\n{\n\treturn x >= y ? x - y : y - x;\n}\n\n#define rtw_net_traversal_jiffies(adapter) \\\n\trtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPnetDiameterTraversalTime)\n#define rtw_default_lifetime(adapter) \\\n\tRTW_MSEC_TO_TU(adapter->mesh_cfg.dot11MeshHWMPactivePathTimeout)\n#define rtw_min_preq_int_jiff(adapter) \\\n\t(rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPpreqMinInterval))\n#define rtw_max_preq_retries(adapter) (adapter->mesh_cfg.dot11MeshHWMPmaxPREQretries)\n#define rtw_disc_timeout_jiff(adapter) \\\n\trtw_ms_to_systime(adapter->mesh_cfg.min_discovery_timeout)\n#define rtw_root_path_confirmation_jiffies(adapter) \\\n\trtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPconfirmationInterval)\n\nstatic inline BOOLEAN rtw_ether_addr_equal(const u8 *addr1, const u8 *addr2)\n{\n\treturn _rtw_memcmp(addr1, addr2, ETH_ALEN);\n}\n\n#ifdef PLATFORM_LINUX\n#define rtw_print_ratelimit()\tprintk_ratelimit()\n#define rtw_mod_timer(ptimer, expires) mod_timer(&(ptimer)->timer, expires)\n#else\n\n#endif\n\n#define RTW_MESH_EWMA_PRECISION 20\n#define RTW_MESH_EWMA_WEIGHT_RCP 8\n#define RTW_TOTAL_PKT_MIN_THRESHOLD 1\ninline void rtw_ewma_err_rate_init(struct rtw_ewma_err_rate *e)\n{\n\te->internal = 0;\n}\ninline unsigned long rtw_ewma_err_rate_read(struct rtw_ewma_err_rate *e)\n{\n\treturn e->internal >> (RTW_MESH_EWMA_PRECISION);\n}\ninline void rtw_ewma_err_rate_add(struct rtw_ewma_err_rate *e,\n\t\t\t\t  unsigned long val)\n{\n\tunsigned long internal = e->internal;\n\tunsigned long weight_rcp = rtw_ilog2(RTW_MESH_EWMA_WEIGHT_RCP);\n\tunsigned long precision = RTW_MESH_EWMA_PRECISION;\n\n\t(e->internal) = internal ? (((internal << weight_rcp) - internal) +\n\t\t\t(val << precision)) >> weight_rcp :\n\t\t\t(val << precision);\n}\n\nstatic const u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\nstatic int rtw_mesh_path_sel_frame_tx(enum rtw_mpath_frame_type mpath_action, u8 flags,\n\t\t\t\t      const u8 *originator_addr, u32 originator_sn,\n\t\t\t\t      u8 target_flags, const u8 *target,\n\t\t\t\t      u32 target_sn, const u8 *da, u8 hopcount, u8 ttl,\n\t\t\t\t      u32 lifetime, u32 metric, u32 preq_id, \n\t\t\t\t      _adapter *adapter)\n{\n\tstruct xmit_priv *pxmitpriv = &(adapter->xmitpriv);\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\tstruct xmit_frame *pmgntframe = NULL;\n\tstruct rtw_ieee80211_hdr *pwlanhdr = NULL;\n\tstruct pkt_attrib *pattrib = NULL;\n\tu8 category = RTW_WLAN_CATEGORY_MESH;\n\tu8 action = RTW_ACT_MESH_HWMP_PATH_SELECTION;\n\tu16 *fctrl = NULL;\n\tu8 *pos, ie_len;\n\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn -1;\n\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(adapter, pattrib);\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpos = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pos;\n\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pos, WIFI_ACTION);\n\n\tpos += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tpos = rtw_set_fixed_ie(pos, 1, &(category), &(pattrib->pktlen));\n\tpos = rtw_set_fixed_ie(pos, 1, &(action), &(pattrib->pktlen));\n\n\tswitch (mpath_action) {\n\tcase RTW_MPATH_PREQ:\n\t\tRTW_HWMP_DBG(\"sending PREQ to \"MAC_FMT\"\\n\", MAC_ARG(target));\n\t\tie_len = 37;\n\t\tpattrib->pktlen += (ie_len + 2);\n\t\t*pos++ = WLAN_EID_PREQ;\n\t\tbreak;\n\tcase RTW_MPATH_PREP:\n\t\tRTW_HWMP_DBG(\"sending PREP to \"MAC_FMT\"\\n\", MAC_ARG(originator_addr));\n\t\tie_len = 31;\n\t\tpattrib->pktlen += (ie_len + 2);\n\t\t*pos++ = WLAN_EID_PREP;\n\t\tbreak;\n\tcase RTW_MPATH_RANN:\n\t\tRTW_HWMP_DBG(\"sending RANN from \"MAC_FMT\"\\n\", MAC_ARG(originator_addr));\n\t\tie_len = sizeof(struct rtw_ieee80211_rann_ie);\n\t\tpattrib->pktlen += (ie_len + 2);\n\t\t*pos++ = WLAN_EID_RANN;\n\t\tbreak;\n\tdefault:\n\t\trtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);\n\t\trtw_free_xmitframe(pxmitpriv, pmgntframe);\n\t\treturn _FAIL;\n\t}\n\t*pos++ = ie_len;\n\t*pos++ = flags;\n\t*pos++ = hopcount;\n\t*pos++ = ttl;\n\tif (mpath_action == RTW_MPATH_PREP) {\n\t\t_rtw_memcpy(pos, target, ETH_ALEN);\n\t\tpos += ETH_ALEN;\n\t\t*(u32 *)pos = cpu_to_le32(target_sn);\n\t\tpos += 4;\n\t} else {\n\t\tif (mpath_action == RTW_MPATH_PREQ) {\n\t\t\t*(u32 *)pos = cpu_to_le32(preq_id);\n\t\t\tpos += 4;\n\t\t}\n\t\t_rtw_memcpy(pos, originator_addr, ETH_ALEN);\n\t\tpos += ETH_ALEN;\n\t\t*(u32 *)pos = cpu_to_le32(originator_sn);\n\t\tpos += 4;\n\t}\n\t*(u32 *)pos = cpu_to_le32(lifetime);\n\tpos += 4;\n\t*(u32 *)pos = cpu_to_le32(metric);\n\tpos += 4;\n\tif (mpath_action == RTW_MPATH_PREQ) {\n\t\t*pos++ = 1; /* support only 1 destination now */\n\t\t*pos++ = target_flags;\n\t\t_rtw_memcpy(pos, target, ETH_ALEN);\n\t\tpos += ETH_ALEN;\n\t\t*(u32 *)pos = cpu_to_le32(target_sn);\n\t\tpos += 4;\n\t} else if (mpath_action == RTW_MPATH_PREP) {\n\t\t_rtw_memcpy(pos, originator_addr, ETH_ALEN);\n\t\tpos += ETH_ALEN;\n\t\t*(u32 *)pos = cpu_to_le32(originator_sn);\n\t\tpos += 4;\n\t}\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\tdump_mgntframe(adapter, pmgntframe);\n\treturn 0;\n}\n\nint rtw_mesh_path_error_tx(_adapter *adapter,\n\t\t\t   u8 ttl, const u8 *target, u32 target_sn,\n\t\t\t   u16 perr_reason_code, const u8 *ra)\n{\n\n\tstruct xmit_priv *pxmitpriv = &(adapter->xmitpriv);\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\tstruct xmit_frame *pmgntframe = NULL;\n\tstruct rtw_ieee80211_hdr *pwlanhdr = NULL;\n\tstruct pkt_attrib *pattrib = NULL;\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tu8 category = RTW_WLAN_CATEGORY_MESH;\n\tu8 action = RTW_ACT_MESH_HWMP_PATH_SELECTION;\n\tu8 *pos, ie_len;\n\tu16 *fctrl = NULL;\n\n\tif (rtw_time_before(rtw_get_current_time(), minfo->next_perr))\n\t\treturn -1;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn -1;\n\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(adapter, pattrib);\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpos = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pos;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pos, WIFI_ACTION);\n\n\tpos += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tpos = rtw_set_fixed_ie(pos, 1, &(category), &(pattrib->pktlen));\n\tpos = rtw_set_fixed_ie(pos, 1, &(action), &(pattrib->pktlen));\n\n\tie_len = 15;\n\tpattrib->pktlen += (2 + ie_len);\n\t*pos++ = WLAN_EID_PERR;\n\t*pos++ = ie_len;\n\t/* ttl */\n\t*pos++ = ttl;\n\t/* The Number of Destinations N */\n\t*pos++ = 1;\n\t/* Flags format | B7 | B6 | B5:B0 | = | rsvd | AE | rsvd | */\n\t*pos = 0;\n\tpos++;\n\t_rtw_memcpy(pos, target, ETH_ALEN);\n\tpos += ETH_ALEN;\n\t*(u32 *)pos = cpu_to_le32(target_sn);\n\tpos += 4;\n\t*(u16 *)pos = cpu_to_le16(perr_reason_code);\n\n\tadapter->mesh_info.next_perr = RTW_TU_TO_EXP_TIME(\n\t\t\t\tadapter->mesh_cfg.dot11MeshHWMPperrMinInterval);\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\t/* Send directly. Rewrite it if deferred tx is needed */\n\tdump_mgntframe(adapter, pmgntframe);\n\n\tRTW_HWMP_DBG(\"TX PERR toward \"MAC_FMT\", ra = \"MAC_FMT\"\\n\", MAC_ARG(target), MAC_ARG(ra));\n\t\n\treturn 0;\n}\n\nstatic u32 rtw_get_vht_bitrate(u8 mcs, u8 bw, u8 nss, u8 sgi)\n{\n\tstatic const u32 base[4][10] = {\n\t\t{   6500000,\n\t\t   13000000,\n\t\t   19500000,\n\t\t   26000000,\n\t\t   39000000,\n\t\t   52000000,\n\t\t   58500000,\n\t\t   65000000,\n\t\t   78000000,\n\t\t/* not in the spec, but some devices use this: */\n\t\t   86500000,\n\t\t},\n\t\t{  13500000,\n\t\t   27000000,\n\t\t   40500000,\n\t\t   54000000,\n\t\t   81000000,\n\t\t  108000000,\n\t\t  121500000,\n\t\t  135000000,\n\t\t  162000000,\n\t\t  180000000,\n\t\t},\n\t\t{  29300000,\n\t\t   58500000,\n\t\t   87800000,\n\t\t  117000000,\n\t\t  175500000,\n\t\t  234000000,\n\t\t  263300000,\n\t\t  292500000,\n\t\t  351000000,\n\t\t  390000000,\n\t\t},\n\t\t{  58500000,\n\t\t  117000000,\n\t\t  175500000,\n\t\t  234000000,\n\t\t  351000000,\n\t\t  468000000,\n\t\t  526500000,\n\t\t  585000000,\n\t\t  702000000,\n\t\t  780000000,\n\t\t},\n\t};\n\tu32 bitrate;\n\tint bw_idx;\n\n\tif (mcs > 9) {\n\t\tRTW_HWMP_INFO(\"Invalid mcs = %d\\n\", mcs);\n\t\treturn 0;\n\t}\n\n\tif (nss > 4 || nss < 1) {\n\t\tRTW_HWMP_INFO(\"Now only support nss = 1, 2, 3, 4\\n\");\n\t}\n\n\tswitch (bw) {\n\tcase CHANNEL_WIDTH_160:\n\t\tbw_idx = 3;\n\t\tbreak;\n\tcase CHANNEL_WIDTH_80:\n\t\tbw_idx = 2;\n\t\tbreak;\n\tcase CHANNEL_WIDTH_40:\n\t\tbw_idx = 1;\n\t\tbreak;\n\tcase CHANNEL_WIDTH_20:\n\t\tbw_idx = 0;\n\t\tbreak;\n\tdefault:\n\t\tRTW_HWMP_INFO(\"bw = %d currently not supported\\n\", bw);\n\t\treturn 0;\n\t}\n\n\tbitrate = base[bw_idx][mcs];\n\tbitrate *= nss;\n\n\tif (sgi)\n\t\tbitrate = (bitrate / 9) * 10;\n\n\t/* do NOT round down here */\n\treturn (bitrate + 50000) / 100000;\n}\n\nstatic u32 rtw_get_ht_bitrate(u8 mcs, u8 bw, u8 sgi)\n{\n\tint modulation, streams, bitrate;\n\n\t/* the formula below does only work for MCS values smaller than 32 */\n\tif (mcs >= 32) {\n\t\tRTW_HWMP_INFO(\"Invalid mcs = %d\\n\", mcs);\n\t\treturn 0;\n\t}\n\n\tif (bw > 1) {\n\t\tRTW_HWMP_INFO(\"Now HT only support bw = 0(20Mhz), 1(40Mhz)\\n\");\n\t\treturn 0;\n\t}\n\n\tmodulation = mcs & 7;\n\tstreams = (mcs >> 3) + 1;\n\n\tbitrate = (bw == 1) ? 13500000 : 6500000;\n\n\tif (modulation < 4)\n\t\tbitrate *= (modulation + 1);\n\telse if (modulation == 4)\n\t\tbitrate *= (modulation + 2);\n\telse\n\t\tbitrate *= (modulation + 3);\n\n\tbitrate *= streams;\n\n\tif (sgi)\n\t\tbitrate = (bitrate / 9) * 10;\n\n\t/* do NOT round down here */\n\treturn (bitrate + 50000) / 100000;\n}\n\n/**\n * @bw: 0(20Mhz), 1(40Mhz), 2(80Mhz), 3(160Mhz)\n * @rate_idx: DESC_RATEXXXX & 0x7f\n * @sgi: DESC_RATEXXXX >> 7\n * Returns: bitrate in 100kbps\n */\nstatic u32 rtw_desc_rate_to_bitrate(u8 bw, u8 rate_idx, u8 sgi)\n{\n\tu32 bitrate;\n\n\tif (rate_idx <= DESC_RATE54M){\n\t\tu16 ofdm_rate[12] = {10, 20, 55, 110,\n\t\t\t60, 90, 120, 180, 240, 360, 480, 540};\n\t\tbitrate = ofdm_rate[rate_idx];\n\t} else if ((DESC_RATEMCS0 <= rate_idx) &&\n\t\t   (rate_idx <= DESC_RATEMCS31)) {\n\t\tu8 mcs = rate_idx - DESC_RATEMCS0;\n\t\tbitrate = rtw_get_ht_bitrate(mcs, bw, sgi);\n\t} else if ((DESC_RATEVHTSS1MCS0 <= rate_idx) &&\n\t\t   (rate_idx <= DESC_RATEVHTSS4MCS9)) {\n\t\tu8 mcs = (rate_idx - DESC_RATEVHTSS1MCS0) % 10;\n\t\tu8 nss = ((rate_idx - DESC_RATEVHTSS1MCS0) / 10) + 1;\n\t\tbitrate = rtw_get_vht_bitrate(mcs, bw, nss, sgi);\n\t} else {\n\t\t/* 60Ghz ??? */\n\t\tbitrate = 1;\n\t}\n\n\treturn bitrate;\n}\n\nstatic u32 rtw_airtime_link_metric_get(_adapter *adapter, struct sta_info *sta)\n{\n\tstruct dm_struct *dm = adapter_to_phydm(adapter);\n\tint device_constant = phydm_get_plcp(dm, sta->cmn.mac_id) << RTW_ARITH_SHIFT;\n\tu32 test_frame_len = RTW_TEST_FRAME_LEN << RTW_ARITH_SHIFT;\n\tu32 s_unit = 1 << RTW_ARITH_SHIFT;\n\tu32 err;\n\tu16 rate;\n\tu32 tx_time, estimated_retx;\n\tu64 result;\n\t/* The fail_avg should <= 100 here */\n\tu32 fail_avg = (u32)rtw_ewma_err_rate_read(&sta->metrics.err_rate);\n\n\tif (fail_avg > RTW_LINK_FAIL_THRESH)\n\t\treturn RTW_MAX_METRIC;\n\n\trate = sta->metrics.data_rate;\n\t/* rate unit is 100Kbps, min rate = 10 */\n\tif (rate < 10) {\n\t\tRTW_HWMP_INFO(\"rate = %d\\n\", rate);\n\t\treturn RTW_MAX_METRIC;\n\t}\n\n\terr = (fail_avg << RTW_ARITH_SHIFT) / 100;\n\n\t/* test_frame_len*10 to adjust the unit of rate(100kbps/unit) */\n\ttx_time = (device_constant + 10 * test_frame_len / rate);\n\testimated_retx = ((1 << (2 * RTW_ARITH_SHIFT)) / (s_unit - err));\n\tresult = (tx_time * estimated_retx) >> (2 * RTW_ARITH_SHIFT);\n\t/* Convert us to 0.01 TU(10.24us). x/10.24 = x*100/1024 */\n\tresult = (result * 100) >> 10;\n\n\treturn (u32)result;\n}\n\nvoid rtw_ieee80211s_update_metric(_adapter *adapter, u8 mac_id,\n\t\t\t\t  u8 per, u8 rate,\n\t\t\t\t  u8 bw, u8 total_pkt)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\tstruct sta_info *sta;\n\tu8 rate_idx;\n\tu8 sgi;\n\n\tsta = macid_ctl->sta[mac_id];\n\tif (!sta)\n\t\treturn;\n\n\t/* if RA, use reported rate */\n\tif (adapter->fix_rate == 0xff) {\n\t\trate_idx = rate & 0x7f;\n\t\tsgi = rate >> 7;\n\t} else {\n\t\trate_idx = adapter->fix_rate & 0x7f;\n\t\tsgi = adapter->fix_rate >> 7;\n\t}\n\tsta->metrics.data_rate = rtw_desc_rate_to_bitrate(bw, rate_idx, sgi);\n\n\tif (total_pkt < RTW_TOTAL_PKT_MIN_THRESHOLD)\n\t\treturn;\n\n\t/* TBD: sta->metrics.overhead = phydm_get_plcp(void *dm_void, u16 macid); */\n\tsta->metrics.total_pkt = total_pkt;\n\n\trtw_ewma_err_rate_add(&sta->metrics.err_rate, per);\n\tif (rtw_ewma_err_rate_read(&sta->metrics.err_rate) > \n\t\t\tRTW_LINK_FAIL_THRESH)\n\t\trtw_mesh_plink_broken(sta);\n}\n\nstatic void rtw_hwmp_preq_frame_process(_adapter *adapter,\n\t\t\t\t\tstruct rtw_ieee80211_hdr_3addr *mgmt,\n\t\t\t\t\tconst u8 *preq_elem, u32 originator_metric)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;\n\tstruct rtw_mesh_path *path = NULL;\n\tconst u8 *target_addr, *originator_addr;\n\tconst u8 *da;\n\tu8 target_flags, ttl, flags, to_gate_ask = 0;\n\tu32 originator_sn, target_sn, lifetime, target_metric = 0;\n\tBOOLEAN reply = _FALSE;\n\tBOOLEAN forward = _TRUE;\n\tBOOLEAN preq_is_gate;\n\n\t/* Update target SN, if present */\n\ttarget_addr = RTW_PREQ_IE_TARGET_ADDR(preq_elem);\n\toriginator_addr = RTW_PREQ_IE_ORIG_ADDR(preq_elem);\n\ttarget_sn = RTW_PREQ_IE_TARGET_SN(preq_elem);\n\toriginator_sn = RTW_PREQ_IE_ORIG_SN(preq_elem);\n\ttarget_flags = RTW_PREQ_IE_TARGET_F(preq_elem);\n\t/* PREQ gate announcements */\n\tflags = RTW_PREQ_IE_FLAGS(preq_elem);\n\tpreq_is_gate = !!(flags & RTW_IEEE80211_PREQ_IS_GATE_FLAG);\n\n\tRTW_HWMP_DBG(\"received PREQ from \"MAC_FMT\"\\n\", MAC_ARG(originator_addr));\n\n\tif (rtw_ether_addr_equal(target_addr, adapter_mac_addr(adapter))) {\n\t\tRTW_HWMP_DBG(\"PREQ is for us\\n\");\n#ifdef CONFIG_RTW_MESH_ON_DMD_GANN\n\t\trtw_rcu_read_lock();\n\t\tpath = rtw_mesh_path_lookup(adapter, originator_addr);\n\t\tif (path) {\n\t\t\tif (preq_is_gate)\n\t\t\t\trtw_mesh_path_add_gate(path);\n\t\t\telse if (path->is_gate) {\n\t\t\t\tenter_critical_bh(&path->state_lock);\n\t\t\t\trtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);\n\t\t\t\texit_critical_bh(&path->state_lock);\n\t\t\t}\n\t\t}\n\t\tpath = NULL;\n\t\trtw_rcu_read_unlock();\n#endif\n\t\tforward = _FALSE;\n\t\treply = _TRUE;\n\t\tto_gate_ask = 1;\n\t\ttarget_metric = 0;\n\t\tif (rtw_time_after(rtw_get_current_time(), minfo->last_sn_update +\n\t\t\t\t\trtw_net_traversal_jiffies(adapter)) ||\n\t\t    rtw_time_before(rtw_get_current_time(), minfo->last_sn_update)) {\n\t\t\t++minfo->sn;\n\t\t\tminfo->last_sn_update = rtw_get_current_time();\n\t\t}\n\t\ttarget_sn = minfo->sn;\n\t} else if (is_broadcast_mac_addr(target_addr) &&\n\t\t   (target_flags & RTW_IEEE80211_PREQ_TO_FLAG)) {\n\t\trtw_rcu_read_lock();\n\t\tpath = rtw_mesh_path_lookup(adapter, originator_addr);\n\t\tif (path) {\n\t\t\tif (flags & RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG) {\n\t\t\t\treply = _TRUE;\n\t\t\t\ttarget_addr = adapter_mac_addr(adapter);\n\t\t\t\ttarget_sn = ++minfo->sn;\n\t\t\t\ttarget_metric = 0;\n\t\t\t\tminfo->last_sn_update = rtw_get_current_time();\n\t\t\t}\n\n\t\t\tif (preq_is_gate) {\n\t\t\t\tlifetime = RTW_PREQ_IE_LIFETIME(preq_elem);\n\t\t\t\tpath->gate_ann_int = lifetime;\n\t\t\t\tpath->gate_asked = false;\n\t\t\t\trtw_mesh_path_add_gate(path);\n\t\t\t} else if (path->is_gate) {\n\t\t\t\tenter_critical_bh(&path->state_lock);\n\t\t\t\trtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);\n\t\t\t\texit_critical_bh(&path->state_lock);\n\t\t\t}\n\t\t}\n\t\trtw_rcu_read_unlock();\n\t} else {\n\t\trtw_rcu_read_lock();\n#ifdef CONFIG_RTW_MESH_ON_DMD_GANN\n\t\tpath = rtw_mesh_path_lookup(adapter, originator_addr);\n\t\tif (path) {\n\t\t\tif (preq_is_gate)\n\t\t\t\trtw_mesh_path_add_gate(path);\n\t\t\telse if (path->is_gate) {\n\t\t\t\tenter_critical_bh(&path->state_lock);\n\t\t\t\trtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);\n\t\t\t\texit_critical_bh(&path->state_lock);\n\t\t\t}\n\t\t}\n\t\tpath = NULL;\n#endif\n\t\tpath = rtw_mesh_path_lookup(adapter, target_addr);\n\t\tif (path) {\n\t\t\tif ((!(path->flags & RTW_MESH_PATH_SN_VALID)) ||\n\t\t\t\t\tRTW_SN_LT(path->sn, target_sn)) {\n\t\t\t\tpath->sn = target_sn;\n\t\t\t\tpath->flags |= RTW_MESH_PATH_SN_VALID;\n\t\t\t} else if ((!(target_flags & RTW_IEEE80211_PREQ_TO_FLAG)) &&\n\t\t\t\t\t(path->flags & RTW_MESH_PATH_ACTIVE)) {\n\t\t\t\treply = _TRUE;\n\t\t\t\ttarget_metric = path->metric;\n\t\t\t\ttarget_sn = path->sn;\n\t\t\t\t/* Case E2 of sec 13.10.9.3 IEEE 802.11-2012*/\n\t\t\t\ttarget_flags |= RTW_IEEE80211_PREQ_TO_FLAG;\n\t\t\t}\n\t\t}\n\t\trtw_rcu_read_unlock();\n\t}\n\n\tif (reply) {\n\t\tlifetime = RTW_PREQ_IE_LIFETIME(preq_elem);\n\t\tttl = mshcfg->element_ttl;\n\t\tif (ttl != 0 && !to_gate_ask) {\n\t\t\tRTW_HWMP_DBG(\"replying to the PREQ\\n\");\n\t\t\trtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, 0, originator_addr,\n\t\t\t\t\t\t   originator_sn, 0, target_addr,\n\t\t\t\t\t\t   target_sn, mgmt->addr2, 0, ttl,\n\t\t\t\t\t\t   lifetime, target_metric, 0,\n\t\t\t\t\t\t   adapter);\n\t\t} else if (ttl != 0 && to_gate_ask) {\n\t\t\tRTW_HWMP_DBG(\"replying to the PREQ (PREQ for us)\\n\");\n\t\t\tif (mshcfg->dot11MeshGateAnnouncementProtocol) {\n\t\t\t\t/* BIT 7 is used to identify the prep is from mesh gate */\n\t\t\t\tto_gate_ask = RTW_IEEE80211_PREQ_IS_GATE_FLAG | BIT(7);\n\t\t\t} else {\n\t\t\t\tto_gate_ask = 0;\n\t\t\t}\n\n\t\t\trtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, to_gate_ask, originator_addr,\n\t\t\t\t\t\t   originator_sn, 0, target_addr,\n\t\t\t\t\t\t   target_sn, mgmt->addr2, 0, ttl,\n\t\t\t\t\t\t   lifetime, target_metric, 0,\n\t\t\t\t\t\t   adapter);\n\t\t} else {\n\t\t\tminfo->mshstats.dropped_frames_ttl++;\n\t\t}\n\t}\n\n\tif (forward && mshcfg->dot11MeshForwarding) {\n\t\tu32 preq_id;\n\t\tu8 hopcount;\n\n\t\tttl = RTW_PREQ_IE_TTL(preq_elem);\n\t\tlifetime = RTW_PREQ_IE_LIFETIME(preq_elem);\n\t\tif (ttl <= 1) {\n\t\t\tminfo->mshstats.dropped_frames_ttl++;\n\t\t\treturn;\n\t\t}\n\t\tRTW_HWMP_DBG(\"forwarding the PREQ from \"MAC_FMT\"\\n\", MAC_ARG(originator_addr));\n\t\t--ttl;\n\t\tpreq_id = RTW_PREQ_IE_PREQ_ID(preq_elem);\n\t\thopcount = RTW_PREQ_IE_HOPCOUNT(preq_elem) + 1;\n\t\tda = (path && path->is_root) ?\n\t\t\tpath->rann_snd_addr : bcast_addr;\n\n\t\tif (flags & RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG) {\n\t\t\ttarget_addr = RTW_PREQ_IE_TARGET_ADDR(preq_elem);\n\t\t\ttarget_sn = RTW_PREQ_IE_TARGET_SN(preq_elem);\n\t\t}\n\n\t\trtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, originator_addr,\n\t\t\t\t\t   originator_sn, target_flags, target_addr,\n\t\t\t\t\t   target_sn, da, hopcount, ttl, lifetime,\n\t\t\t\t\t   originator_metric, preq_id, adapter);\n\t\tif (!is_multicast_mac_addr(da))\n\t\t\tminfo->mshstats.fwded_unicast++;\n\t\telse\n\t\t\tminfo->mshstats.fwded_mcast++;\n\t\tminfo->mshstats.fwded_frames++;\n\t}\n}\n\nstatic inline struct sta_info *\nrtw_next_hop_deref_protected(struct rtw_mesh_path *path)\n{\n\treturn rtw_rcu_dereference_protected(path->next_hop,\n\t\t\t\t\t rtw_lockdep_is_held(&path->state_lock));\n}\n\nstatic void rtw_hwmp_prep_frame_process(_adapter *adapter,\n\t\t\t\t\tstruct rtw_ieee80211_hdr_3addr *mgmt,\n\t\t\t\t\tconst u8 *prep_elem, u32 metric)\n{\n\tstruct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;\n\tstruct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats;\n\tstruct rtw_mesh_path *path;\n\tconst u8 *target_addr, *originator_addr;\n\tu8 ttl, hopcount, flags;\n\tu8 next_hop[ETH_ALEN];\n\tu32 target_sn, originator_sn, lifetime;\n\n\tRTW_HWMP_DBG(\"received PREP from \"MAC_FMT\"\\n\",\n\t\t  MAC_ARG(RTW_PREP_IE_TARGET_ADDR(prep_elem)));\n\n\toriginator_addr = RTW_PREP_IE_ORIG_ADDR(prep_elem);\n\tif (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter))) {\n\t\t/* destination, no forwarding required */\n\t\trtw_rcu_read_lock();\n\t\ttarget_addr = RTW_PREP_IE_TARGET_ADDR(prep_elem);\n\t\tpath = rtw_mesh_path_lookup(adapter, target_addr);\n\t\tif (path && path->gate_asked) {\n\t\t\tflags = RTW_PREP_IE_FLAGS(prep_elem);\n\t\t\tif (flags & BIT(7)) {\n\t\t\t\tenter_critical_bh(&path->state_lock);\n\t\t\t\tpath->gate_asked = false;\n\t\t\t\texit_critical_bh(&path->state_lock);\n\t\t\t\tif (!(flags & RTW_IEEE80211_PREQ_IS_GATE_FLAG)) {\n\t\t\t\t\tenter_critical_bh(&path->state_lock);\n\t\t\t\t\trtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);\n\t\t\t\t\texit_critical_bh(&path->state_lock);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\trtw_rcu_read_unlock();\n\t\treturn;\n\t}\n\n\tif (!mshcfg->dot11MeshForwarding)\n\t\treturn;\n\n\tttl = RTW_PREP_IE_TTL(prep_elem);\n\tif (ttl <= 1) {\n\t\tmshstats->dropped_frames_ttl++;\n\t\treturn;\n\t}\n\n\trtw_rcu_read_lock();\n\tpath = rtw_mesh_path_lookup(adapter, originator_addr);\n\tif (path)\n\t\tenter_critical_bh(&path->state_lock);\n\telse\n\t\tgoto fail;\n\tif (!(path->flags & RTW_MESH_PATH_ACTIVE)) {\n\t\texit_critical_bh(&path->state_lock);\n\t\tgoto fail;\n\t}\n\t_rtw_memcpy(next_hop, rtw_next_hop_deref_protected(path)->cmn.mac_addr, ETH_ALEN);\n\texit_critical_bh(&path->state_lock);\n\t--ttl;\n\tflags = RTW_PREP_IE_FLAGS(prep_elem);\n\tlifetime = RTW_PREP_IE_LIFETIME(prep_elem);\n\thopcount = RTW_PREP_IE_HOPCOUNT(prep_elem) + 1;\n\ttarget_addr = RTW_PREP_IE_TARGET_ADDR(prep_elem);\n\ttarget_sn = RTW_PREP_IE_TARGET_SN(prep_elem);\n\toriginator_sn = RTW_PREP_IE_ORIG_SN(prep_elem);\n\n\trtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, flags, originator_addr, originator_sn, 0,\n\t\t\t\t   target_addr, target_sn, next_hop, hopcount,\n\t\t\t\t   ttl, lifetime, metric, 0, adapter);\n\trtw_rcu_read_unlock();\n\n\tmshstats->fwded_unicast++;\n\tmshstats->fwded_frames++;\n\treturn;\n\nfail:\n\trtw_rcu_read_unlock();\n\tmshstats->dropped_frames_no_route++;\n}\n\nstatic void rtw_hwmp_perr_frame_process(_adapter *adapter,\n\t\t\t\t\tstruct rtw_ieee80211_hdr_3addr *mgmt,\n\t\t\t\t\tconst u8 *perr_elem)\n{\n\tstruct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;\n\tstruct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats;\n\tstruct rtw_mesh_path *path;\n\tu8 ttl;\n\tconst u8 *ta, *target_addr;\n\tu32 target_sn;\n\tu16 perr_reason_code;\n\n\tta = mgmt->addr2;\n\tttl = RTW_PERR_IE_TTL(perr_elem);\n\tif (ttl <= 1) {\n\t\tmshstats->dropped_frames_ttl++;\n\t\treturn;\n\t}\n\tttl--;\n\ttarget_addr = RTW_PERR_IE_TARGET_ADDR(perr_elem);\n\ttarget_sn = RTW_PERR_IE_TARGET_SN(perr_elem);\n\tperr_reason_code = RTW_PERR_IE_TARGET_RCODE(perr_elem);\n\n\tRTW_HWMP_DBG(\"received PERR toward target \"MAC_FMT\"\\n\", MAC_ARG(target_addr));\n\n\trtw_rcu_read_lock();\n\tpath = rtw_mesh_path_lookup(adapter, target_addr);\n\tif (path) {\n\t\tstruct sta_info *sta;\n\n\t\tenter_critical_bh(&path->state_lock);\n\t\tsta = rtw_next_hop_deref_protected(path);\n\t\tif (path->flags & RTW_MESH_PATH_ACTIVE &&\n\t\t    rtw_ether_addr_equal(ta, sta->cmn.mac_addr) &&\n\t\t    !(path->flags & RTW_MESH_PATH_FIXED) &&\n\t\t    (!(path->flags & RTW_MESH_PATH_SN_VALID) ||\n\t\t    RTW_SN_GT(target_sn, path->sn)  || target_sn == 0)) {\n\t\t\tpath->flags &= ~RTW_MESH_PATH_ACTIVE;\n\t\t\tif (target_sn != 0)\n\t\t\t\tpath->sn = target_sn;\n\t\t\telse\n\t\t\t\tpath->sn += 1;\n\t\t\texit_critical_bh(&path->state_lock);\n\t\t\tif (!mshcfg->dot11MeshForwarding)\n\t\t\t\tgoto endperr;\n\t\t\trtw_mesh_path_error_tx(adapter, ttl, target_addr,\n\t\t\t\t\t       target_sn, perr_reason_code,\n\t\t\t\t\t       bcast_addr);\n\t\t} else\n\t\t\texit_critical_bh(&path->state_lock);\n\t}\nendperr:\n\trtw_rcu_read_unlock();\n}\n\nstatic void rtw_hwmp_rann_frame_process(_adapter *adapter,\n\t\t\t\t\tstruct rtw_ieee80211_hdr_3addr *mgmt,\n\t\t\t\t\tconst struct rtw_ieee80211_rann_ie *rann)\n{\n\tstruct sta_info *sta;\n\tstruct sta_priv *pstapriv = &adapter->stapriv;\n\tstruct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;\n\tstruct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats;\n\tstruct rtw_mesh_path *path;\n\tu8 ttl, flags, hopcount;\n\tconst u8 *originator_addr;\n\tu32 originator_sn, metric, metric_txsta, interval;\n\tBOOLEAN root_is_gate;\n\n\tttl = rann->rann_ttl;\n\tflags = rann->rann_flags;\n\troot_is_gate = !!(flags & RTW_RANN_FLAG_IS_GATE);\n\toriginator_addr = rann->rann_addr;\n\toriginator_sn = le32_to_cpu(rann->rann_seq);\n\tinterval = le32_to_cpu(rann->rann_interval);\n\thopcount = rann->rann_hopcount;\n\thopcount++;\n\tmetric = le32_to_cpu(rann->rann_metric);\n\n\t/*  Ignore our own RANNs */\n\tif (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter)))\n\t\treturn;\n\n\tRTW_HWMP_DBG(\"received RANN from \"MAC_FMT\" via neighbour \"MAC_FMT\" (is_gate=%d)\\n\",\n\t\t  MAC_ARG(originator_addr), MAC_ARG(mgmt->addr2), root_is_gate);\n\n\trtw_rcu_read_lock();\n\tsta = rtw_get_stainfo(pstapriv, mgmt->addr2);\n\tif (!sta) {\n\t\trtw_rcu_read_unlock();\n\t\treturn;\n\t}\n\n\tmetric_txsta = rtw_airtime_link_metric_get(adapter, sta);\n\n\tpath = rtw_mesh_path_lookup(adapter, originator_addr);\n\tif (!path) {\n\t\tpath = rtw_mesh_path_add(adapter, originator_addr);\n\t\tif (IS_ERR(path)) {\n\t\t\trtw_rcu_read_unlock();\n\t\t\tmshstats->dropped_frames_no_route++;\n\t\t\treturn;\n\t\t}\n\t}\n\n\tif (!(RTW_SN_LT(path->sn, originator_sn)) &&\n\t    !(path->sn == originator_sn && metric < path->rann_metric)) {\n\t\trtw_rcu_read_unlock();\n\t\treturn;\n\t}\n\n\tif ((!(path->flags & (RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVING)) ||\n\t     (rtw_time_after(rtw_get_current_time(), path->last_preq_to_root +\n\t\t\t\t  rtw_root_path_confirmation_jiffies(adapter)) ||\n\t     rtw_time_before(rtw_get_current_time(), path->last_preq_to_root))) &&\n\t     !(path->flags & RTW_MESH_PATH_FIXED) && (ttl != 0)) {\n\t\tu8 preq_node_flag = RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH;\n\n\t\tRTW_HWMP_DBG(\"time to refresh root path \"MAC_FMT\"\\n\",\n\t\t\t  MAC_ARG(originator_addr));\n#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK\n\t\tif (RTW_SN_LT(path->sn, originator_sn) &&\n\t\t    (path->rann_metric + mshcfg->sane_metric_delta < metric) &&\n\t\t    _rtw_memcmp(bcast_addr, path->rann_snd_addr, ETH_ALEN) == _FALSE) {\n\t\t\tRTW_HWMP_DBG(\"Trigger additional check for root \"\n\t\t\t\t     \"confirm PREQ. rann_snd_addr = \"MAC_FMT\n\t\t\t\t     \"add_chk_rann_snd_addr= \"MAC_FMT\"\\n\",\n\t\t\t\t\tMAC_ARG(mgmt->addr2),\n\t\t\t\t\tMAC_ARG(path->rann_snd_addr));\n\t\t\t_rtw_memcpy(path->add_chk_rann_snd_addr,\n\t\t\t\t    path->rann_snd_addr, ETH_ALEN);\n\t\t\tpreq_node_flag |= RTW_PREQ_Q_F_CHK;\n\t\t\t\n\t\t}\n#endif\n\t\trtw_mesh_queue_preq(path, preq_node_flag);\n\t\tpath->last_preq_to_root = rtw_get_current_time();\n\t}\n\n\tpath->sn = originator_sn;\n\tpath->rann_metric = metric + metric_txsta;\n\tpath->is_root = _TRUE;\n\t/* Recording RANNs sender address to send individually\n\t * addressed PREQs destined for root mesh STA */\n\t_rtw_memcpy(path->rann_snd_addr, mgmt->addr2, ETH_ALEN);\n\n\tif (root_is_gate) {\n\t\tpath->gate_ann_int = interval;\n\t\tpath->gate_asked = false;\n\t\trtw_mesh_path_add_gate(path);\n\t} else if (path->is_gate) {\n\t\tenter_critical_bh(&path->state_lock);\n\t\trtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);\n\t\texit_critical_bh(&path->state_lock);\n\t}\n\n\tif (ttl <= 1) {\n\t\tmshstats->dropped_frames_ttl++;\n\t\trtw_rcu_read_unlock();\n\t\treturn;\n\t}\n\tttl--;\n\n\tif (mshcfg->dot11MeshForwarding) {\n\t\trtw_mesh_path_sel_frame_tx(RTW_MPATH_RANN, flags, originator_addr,\n\t\t\t\t\t   originator_sn, 0, NULL, 0, bcast_addr,\n\t\t\t\t\t   hopcount, ttl, interval,\n\t\t\t\t\t   metric + metric_txsta, 0, adapter);\n\t}\n\n\trtw_rcu_read_unlock();\n}\n\nstatic u32 rtw_hwmp_route_info_get(_adapter *adapter,\n\t\t\t\t   struct rtw_ieee80211_hdr_3addr *mgmt,\n\t\t\t\t   const u8 *hwmp_ie, enum rtw_mpath_frame_type action)\n{\n\tstruct rtw_mesh_path *path;\n\tstruct sta_priv *pstapriv = &adapter->stapriv;\n\tstruct sta_info *sta;\n\tBOOLEAN fresh_info;\n\tconst u8 *originator_addr, *ta;\n\tu32 originator_sn, originator_metric;\n\tunsigned long originator_lifetime, exp_time;\n\tu32 last_hop_metric, new_metric;\n\tBOOLEAN process = _TRUE;\n\n\trtw_rcu_read_lock();\n\tsta = rtw_get_stainfo(pstapriv, mgmt->addr2);\n\tif (!sta) {\n\t\trtw_rcu_read_unlock();\n\t\treturn 0;\n\t}\n\n\tlast_hop_metric = rtw_airtime_link_metric_get(adapter, sta);\n\t/* Update and check originator routing info */\n\tfresh_info = _TRUE;\n\n\tswitch (action) {\n\tcase RTW_MPATH_PREQ:\n\t\toriginator_addr = RTW_PREQ_IE_ORIG_ADDR(hwmp_ie);\n\t\toriginator_sn = RTW_PREQ_IE_ORIG_SN(hwmp_ie);\n\t\toriginator_lifetime = RTW_PREQ_IE_LIFETIME(hwmp_ie);\n\t\toriginator_metric = RTW_PREQ_IE_METRIC(hwmp_ie);\n\t\tbreak;\n\tcase RTW_MPATH_PREP:\n\t\t/* Note: For coding, the naming is not consist with spec */\n\t\toriginator_addr = RTW_PREP_IE_TARGET_ADDR(hwmp_ie);\n\t\toriginator_sn = RTW_PREP_IE_TARGET_SN(hwmp_ie);\n\t\toriginator_lifetime = RTW_PREP_IE_LIFETIME(hwmp_ie);\n\t\toriginator_metric = RTW_PREP_IE_METRIC(hwmp_ie);\n\t\tbreak;\n\tdefault:\n\t\trtw_rcu_read_unlock();\n\t\treturn 0;\n\t}\n\tnew_metric = originator_metric + last_hop_metric;\n\tif (new_metric < originator_metric)\n\t\tnew_metric = RTW_MAX_METRIC;\n\texp_time = RTW_TU_TO_EXP_TIME(originator_lifetime);\n\n\tif (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter))) {\n\t\tprocess = _FALSE;\n\t\tfresh_info = _FALSE;\n\t} else {\n\t\tpath = rtw_mesh_path_lookup(adapter, originator_addr);\n\t\tif (path) {\n\t\t\tenter_critical_bh(&path->state_lock);\n\t\t\tif (path->flags & RTW_MESH_PATH_FIXED)\n\t\t\t\tfresh_info = _FALSE;\n\t\t\telse if ((path->flags & RTW_MESH_PATH_ACTIVE) &&\n\t\t\t    (path->flags & RTW_MESH_PATH_SN_VALID)) {\n\t\t\t\tif (RTW_SN_GT(path->sn, originator_sn) ||\n\t\t\t\t    (path->sn == originator_sn &&\n\t\t\t\t     new_metric >= path->metric)) {\n\t\t\t\t\tprocess = _FALSE;\n\t\t\t\t\tfresh_info = _FALSE;\n\t\t\t\t}\n\t\t\t} else if (!(path->flags & RTW_MESH_PATH_ACTIVE)) {\n\t\t\t\tBOOLEAN have_sn, newer_sn, bounced;\n\n\t\t\t\thave_sn = path->flags & RTW_MESH_PATH_SN_VALID;\n\t\t\t\tnewer_sn = have_sn && RTW_SN_GT(originator_sn, path->sn);\n\t\t\t\tbounced = have_sn &&\n\t\t\t\t\t  (RTW_SN_DELTA(originator_sn, path->sn) >\n\t\t\t\t\t\t\tRTW_MAX_SANE_SN_DELTA);\n\n\t\t\t\tif (!have_sn || newer_sn) {\n\t\t\t\t} else if (bounced) {\n\t\t\t\t} else {\n\t\t\t\t\tprocess = _FALSE;\n\t\t\t\t\tfresh_info = _FALSE;\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tpath = rtw_mesh_path_add(adapter, originator_addr);\n\t\t\tif (IS_ERR(path)) {\n\t\t\t\trtw_rcu_read_unlock();\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t\tenter_critical_bh(&path->state_lock);\n\t\t}\n\n\t\tif (fresh_info) {\n\t\t\trtw_mesh_path_assign_nexthop(path, sta);\n\t\t\tpath->flags |= RTW_MESH_PATH_SN_VALID;\n\t\t\tpath->metric = new_metric;\n\t\t\tpath->sn = originator_sn;\n\t\t\tpath->exp_time = rtw_time_after(path->exp_time, exp_time)\n\t\t\t\t\t  ?  path->exp_time : exp_time;\n\t\t\trtw_mesh_path_activate(path);\n#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK\n\t\t\tif (path->is_root && (action == RTW_MPATH_PREP)) {\n\t\t\t\t_rtw_memcpy(path->rann_snd_addr, \n\t\t\t\tmgmt->addr2, ETH_ALEN);\n\t\t\t\tpath->rann_metric = new_metric;\n\t\t\t}\n#endif\n\t\t\texit_critical_bh(&path->state_lock);\n\t\t\trtw_mesh_path_tx_pending(path);\n\t\t} else\n\t\t\texit_critical_bh(&path->state_lock);\n\t}\n\n\t/* Update and check transmitter routing info */\n\tta = mgmt->addr2;\n\tif (rtw_ether_addr_equal(originator_addr, ta))\n\t\tfresh_info = _FALSE;\n\telse {\n\t\tfresh_info = _TRUE;\n\n\t\tpath = rtw_mesh_path_lookup(adapter, ta);\n\t\tif (path) {\n\t\t\tenter_critical_bh(&path->state_lock);\n\t\t\tif ((path->flags & RTW_MESH_PATH_FIXED) ||\n\t\t\t\t((path->flags & RTW_MESH_PATH_ACTIVE) &&\n\t\t\t\t\t(last_hop_metric > path->metric)))\n\t\t\t\tfresh_info = _FALSE;\n\t\t} else {\n\t\t\tpath = rtw_mesh_path_add(adapter, ta);\n\t\t\tif (IS_ERR(path)) {\n\t\t\t\trtw_rcu_read_unlock();\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t\tenter_critical_bh(&path->state_lock);\n\t\t}\n\n\t\tif (fresh_info) {\n\t\t\trtw_mesh_path_assign_nexthop(path, sta);\n\t\t\tpath->metric = last_hop_metric;\n\t\t\tpath->exp_time = rtw_time_after(path->exp_time, exp_time)\n\t\t\t\t\t  ?  path->exp_time : exp_time;\n\t\t\trtw_mesh_path_activate(path);\n\t\t\texit_critical_bh(&path->state_lock);\n\t\t\trtw_mesh_path_tx_pending(path);\n\t\t} else\n\t\t\texit_critical_bh(&path->state_lock);\n\t}\n\n\trtw_rcu_read_unlock();\n\n\treturn process ? new_metric : 0;\n}\n\nstatic void rtw_mesh_rx_hwmp_frame_cnts(_adapter *adapter, u8 *addr)\n{\n\tstruct sta_info *sta;\n\n\tsta = rtw_get_stainfo(&adapter->stapriv, addr);\n\tif (sta)\n\t\tsta->sta_stats.rx_hwmp_pkts++;\n}\n\nvoid rtw_mesh_rx_path_sel_frame(_adapter *adapter, union recv_frame *rframe)\n{\n\tstruct mesh_plink_ent *plink = NULL;\n\tstruct rtw_ieee802_11_elems elems;\n\tu32 path_metric;\n\tstruct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib;\n\tu8 *pframe = rframe->u.hdr.rx_data, *start;\n\tuint frame_len = rframe->u.hdr.len, left;\n\tstruct rtw_ieee80211_hdr_3addr *frame_hdr = (struct rtw_ieee80211_hdr_3addr *)pframe;\n\tu8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));\n\tParseRes parse_res;\n\n\tplink = rtw_mesh_plink_get(adapter, get_addr2_ptr(pframe));\n\tif (!plink || plink->plink_state != RTW_MESH_PLINK_ESTAB)\n\t\treturn;\n\n\trtw_mesh_rx_hwmp_frame_cnts(adapter, get_addr2_ptr(pframe));\n\n\t/* Mesh action frame IE offset = 2 */\n\tattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\tleft = frame_len - attrib->hdrlen - attrib->iv_len - attrib->icv_len - 2;\n\tstart = pframe + attrib->hdrlen + 2;\n\n\tparse_res = rtw_ieee802_11_parse_elems(start, left, &elems, 1);\n\tif (parse_res == ParseFailed)\n\t\tRTW_HWMP_INFO(FUNC_ADPT_FMT\" Path Select Frame ParseFailed\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter));\n\telse if (parse_res == ParseUnknown)\n\t\tRTW_HWMP_INFO(FUNC_ADPT_FMT\" Path Select Frame ParseUnknown\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter));\n\n\tif (elems.preq) {\n\t\tif (elems.preq_len != 37)\n\t\t\t/* Right now we support just 1 destination and no AE */\n\t\t\treturn;\n\t\tpath_metric = rtw_hwmp_route_info_get(adapter, frame_hdr, elems.preq,\n\t\t\t\t\t\t  MPATH_PREQ);\n\t\tif (path_metric)\n\t\t\trtw_hwmp_preq_frame_process(adapter, frame_hdr, elems.preq,\n\t\t\t\t\t\tpath_metric);\n\t}\n\tif (elems.prep) {\n\t\tif (elems.prep_len != 31)\n\t\t\t/* Right now we support no AE */\n\t\t\treturn;\n\t\tpath_metric = rtw_hwmp_route_info_get(adapter, frame_hdr, elems.prep,\n\t\t\t\t\t\t  MPATH_PREP);\n\t\tif (path_metric)\n\t\t\trtw_hwmp_prep_frame_process(adapter, frame_hdr, elems.prep,\n\t\t\t\t\t\tpath_metric);\n\t}\n\tif (elems.perr) {\n\t\tif (elems.perr_len != 15)\n\t\t\t/* Right now we support only one destination per PERR */\n\t\t\treturn;\n\t\trtw_hwmp_perr_frame_process(adapter, frame_hdr, elems.perr);\n\t}\n\tif (elems.rann)\n\t\trtw_hwmp_rann_frame_process(adapter, frame_hdr, (struct rtw_ieee80211_rann_ie *)elems.rann);\n}\n\nvoid rtw_mesh_queue_preq(struct rtw_mesh_path *path, u8 flags)\n{\n\t_adapter *adapter = path->adapter;\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct rtw_mesh_preq_queue *preq_node;\n\n\tpreq_node = rtw_malloc(sizeof(struct rtw_mesh_preq_queue));\n\tif (!preq_node) {\n\t\tRTW_HWMP_INFO(\"could not allocate PREQ node\\n\");\n\t\treturn;\n\t}\n\n\tenter_critical_bh(&minfo->mesh_preq_queue_lock);\n\tif (minfo->preq_queue_len == RTW_MAX_PREQ_QUEUE_LEN) {\n\t\texit_critical_bh(&minfo->mesh_preq_queue_lock);\n\t\trtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue));\n\t\tif (rtw_print_ratelimit())\n\t\t\tRTW_HWMP_INFO(\"PREQ node queue full\\n\");\n\t\treturn;\n\t}\n\n\t_rtw_spinlock(&path->state_lock);\n\tif (path->flags & RTW_MESH_PATH_REQ_QUEUED) {\n\t\t_rtw_spinunlock(&path->state_lock);\n\t\texit_critical_bh(&minfo->mesh_preq_queue_lock);\n\t\trtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue));\n\t\treturn;\n\t}\n\n\t_rtw_memcpy(preq_node->dst, path->dst, ETH_ALEN);\n\tpreq_node->flags = flags;\n\n\tpath->flags |= RTW_MESH_PATH_REQ_QUEUED;\n#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK\n\tif (flags & RTW_PREQ_Q_F_CHK)\n\t\tpath->flags |= RTW_MESH_PATH_ROOT_ADD_CHK;\n#endif\n\tif (flags & RTW_PREQ_Q_F_PEER_AKA)\n\t\tpath->flags |= RTW_MESH_PATH_PEER_AKA;\n\tif (flags & RTW_PREQ_Q_F_BCAST_PREQ)\n\t\tpath->flags |= RTW_MESH_PATH_BCAST_PREQ;\n\t_rtw_spinunlock(&path->state_lock);\n\n\trtw_list_insert_tail(&preq_node->list, &minfo->preq_queue.list);\n\t++minfo->preq_queue_len;\n\texit_critical_bh(&minfo->mesh_preq_queue_lock);\n\n\tif (rtw_time_after(rtw_get_current_time(), minfo->last_preq + rtw_min_preq_int_jiff(adapter)))\n\t\trtw_mesh_work(&adapter->mesh_work);\n\n\telse if (rtw_time_before(rtw_get_current_time(), minfo->last_preq)) {\n\t\t/* systime wrapped around issue */\n\t\tminfo->last_preq = rtw_get_current_time() - rtw_min_preq_int_jiff(adapter) - 1;\n\t\trtw_mesh_work(&adapter->mesh_work);\n\t} else\n\t\trtw_mod_timer(&adapter->mesh_path_timer, minfo->last_preq +\n\t\t\t\t\trtw_min_preq_int_jiff(adapter) + 1);\n}\n\nstatic const u8 *rtw_hwmp_preq_da(struct rtw_mesh_path *path,\n\t\t\t    BOOLEAN is_root_add_chk, BOOLEAN da_is_peer,\n\t\t\t    BOOLEAN force_preq_bcast)\n{\n\tconst u8 *da;\n\n\tif (da_is_peer)\n\t\tda = path->dst;\n\telse if (force_preq_bcast)\n\t\tda = bcast_addr;\n\telse if (path->is_root)\n#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK\n\t\tda = is_root_add_chk ? path->add_chk_rann_snd_addr:\n\t\t\t\t       path->rann_snd_addr;\n#else\n\t\tda = path->rann_snd_addr;\n#endif\n\telse\n\t\tda = bcast_addr;\n\n\treturn da;\n}\n\nvoid rtw_mesh_path_start_discovery(_adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;\n\tstruct rtw_mesh_preq_queue *preq_node;\n\tstruct rtw_mesh_path *path;\n\tu8 ttl, target_flags = 0;\n\tconst u8 *da;\n\tu32 lifetime;\n\tu8 flags = 0;\n\tBOOLEAN is_root_add_chk = _FALSE;\n\tBOOLEAN da_is_peer, force_preq_bcast;\n\n\tenter_critical_bh(&minfo->mesh_preq_queue_lock);\n\tif (!minfo->preq_queue_len ||\n\t\trtw_time_before(rtw_get_current_time(), minfo->last_preq +\n\t\t\t\trtw_min_preq_int_jiff(adapter))) {\n\t\texit_critical_bh(&minfo->mesh_preq_queue_lock);\n\t\treturn;\n\t}\n\n\tpreq_node = rtw_list_first_entry(&minfo->preq_queue.list,\n\t\t\tstruct rtw_mesh_preq_queue, list);\n\trtw_list_delete(&preq_node->list); /* list_del_init(&preq_node->list); */\n\t--minfo->preq_queue_len;\n\texit_critical_bh(&minfo->mesh_preq_queue_lock);\n\n\trtw_rcu_read_lock();\n\tpath = rtw_mesh_path_lookup(adapter, preq_node->dst);\n\tif (!path)\n\t\tgoto enddiscovery;\n\n\tenter_critical_bh(&path->state_lock);\n\tif (path->flags & (RTW_MESH_PATH_DELETED | RTW_MESH_PATH_FIXED)) {\n\t\texit_critical_bh(&path->state_lock);\n\t\tgoto enddiscovery;\n\t}\n\tpath->flags &= ~RTW_MESH_PATH_REQ_QUEUED;\n\tif (preq_node->flags & RTW_PREQ_Q_F_START) {\n\t\tif (path->flags & RTW_MESH_PATH_RESOLVING) {\n\t\t\texit_critical_bh(&path->state_lock);\n\t\t\tgoto enddiscovery;\n\t\t} else {\n\t\t\tpath->flags &= ~RTW_MESH_PATH_RESOLVED;\n\t\t\tpath->flags |= RTW_MESH_PATH_RESOLVING;\n\t\t\tpath->discovery_retries = 0;\n\t\t\tpath->discovery_timeout = rtw_disc_timeout_jiff(adapter);\n\t\t}\n\t} else if (!(path->flags & RTW_MESH_PATH_RESOLVING) ||\n\t\t\tpath->flags & RTW_MESH_PATH_RESOLVED) {\n\t\tpath->flags &= ~RTW_MESH_PATH_RESOLVING;\n\t\texit_critical_bh(&path->state_lock);\n\t\tgoto enddiscovery;\n\t}\n\n\tminfo->last_preq = rtw_get_current_time();\n\n\tif (rtw_time_after(rtw_get_current_time(), minfo->last_sn_update +\n\t\t\t\trtw_net_traversal_jiffies(adapter)) ||\n\t    rtw_time_before(rtw_get_current_time(), minfo->last_sn_update)) {\n\t\t++minfo->sn;\n\t\tminfo->last_sn_update = rtw_get_current_time();\n\t}\n\tlifetime = rtw_default_lifetime(adapter);\n\tttl = mshcfg->element_ttl;\n\tif (ttl == 0) {\n\t\tminfo->mshstats.dropped_frames_ttl++;\n\t\texit_critical_bh(&path->state_lock);\n\t\tgoto enddiscovery;\n\t}\n\n\tif (preq_node->flags & RTW_PREQ_Q_F_REFRESH)\n\t\ttarget_flags |= RTW_IEEE80211_PREQ_TO_FLAG;\n\telse\n\t\ttarget_flags &= ~RTW_IEEE80211_PREQ_TO_FLAG;\n\n#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK\n\tis_root_add_chk = !!(path->flags & RTW_MESH_PATH_ROOT_ADD_CHK);\n#endif\n\tda_is_peer = !!(path->flags & RTW_MESH_PATH_PEER_AKA);\n\tforce_preq_bcast = !!(path->flags & RTW_MESH_PATH_BCAST_PREQ);\n\texit_critical_bh(&path->state_lock);\n\n\tda = rtw_hwmp_preq_da(path, is_root_add_chk,\n\t\t\t      da_is_peer, force_preq_bcast);\n\n#ifdef CONFIG_RTW_MESH_ON_DMD_GANN\n\tflags = (mshcfg->dot11MeshGateAnnouncementProtocol)\n\t\t? RTW_IEEE80211_PREQ_IS_GATE_FLAG : 0;\n#endif\n\trtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, adapter_mac_addr(adapter), minfo->sn,\n\t\t\t\t   target_flags, path->dst, path->sn, da, 0,\n\t\t\t\t   ttl, lifetime, 0, minfo->preq_id++, adapter);\n\trtw_mod_timer(&path->timer, rtw_get_current_time() + path->discovery_timeout);\n\nenddiscovery:\n\trtw_rcu_read_unlock();\n\trtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue));\n}\n\nvoid rtw_mesh_path_timer(void *ctx)\n{\n\tstruct rtw_mesh_path *path = (void *) ctx;\n\t_adapter *adapter = path->adapter;\n\tint ret;\n\tu8 retry = 0;\n#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK\n\tstruct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;\n#endif\n\t/* TBD: Proctect for suspend */\n#if 0\n\tif (suspending)\n\t\treturn;\n#endif\n\tenter_critical_bh(&path->state_lock);\n\tif (path->flags & RTW_MESH_PATH_RESOLVED ||\n\t\t\t(!(path->flags & RTW_MESH_PATH_RESOLVING))) {\n\t\tpath->flags &= ~(RTW_MESH_PATH_RESOLVING |\n\t\t\t\t RTW_MESH_PATH_RESOLVED |\n\t\t\t\t RTW_MESH_PATH_ROOT_ADD_CHK |\n\t\t\t\t RTW_MESH_PATH_PEER_AKA |\n\t\t\t\t RTW_MESH_PATH_BCAST_PREQ);\n\t\texit_critical_bh(&path->state_lock);\n\t} else if (path->discovery_retries < rtw_max_preq_retries(adapter)) {\n\t\t++path->discovery_retries;\n\t\tpath->discovery_timeout *= 2;\n\t\tpath->flags &= ~RTW_MESH_PATH_REQ_QUEUED;\n#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK\n\t\tif (path->discovery_retries > mshcfg->max_root_add_chk_cnt)\n\t\t\tpath->flags &= ~RTW_MESH_PATH_ROOT_ADD_CHK;\n#endif\n\t\tif (path->gate_asked)\n\t\t\tretry |= RTW_PREQ_Q_F_REFRESH;\n\n\t\texit_critical_bh(&path->state_lock);\n\t\trtw_mesh_queue_preq(path, retry);\n\t} else {\n\t\tpath->flags &= ~(RTW_MESH_PATH_RESOLVING |\n\t\t\t\t  RTW_MESH_PATH_RESOLVED |\n\t\t\t\t  RTW_MESH_PATH_REQ_QUEUED |\n\t\t\t\t  RTW_MESH_PATH_ROOT_ADD_CHK |\n\t\t\t\t  RTW_MESH_PATH_PEER_AKA |\n\t\t\t\t  RTW_MESH_PATH_BCAST_PREQ);\n\t\tpath->exp_time = rtw_get_current_time();\n\t\texit_critical_bh(&path->state_lock);\n\t\tif (!path->is_gate && rtw_mesh_gate_num(adapter) > 0) {\n\t\t\tret = rtw_mesh_path_send_to_gates(path);\n\t\t\tif (ret)\n\t\t\t\tRTW_HWMP_DBG(\"no gate was reachable\\n\");\n\t\t} else\n\t\t\trtw_mesh_path_flush_pending(path);\n\t}\n}\n\n\nvoid rtw_mesh_path_tx_root_frame(_adapter *adapter)\n{\n\tstruct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tu32 interval = mshcfg->dot11MeshHWMPRannInterval;\n\tu8 flags, target_flags = 0;\n\n\tflags = (mshcfg->dot11MeshGateAnnouncementProtocol)\n\t\t\t? RTW_RANN_FLAG_IS_GATE : 0;\n\n\tswitch (mshcfg->dot11MeshHWMPRootMode) {\n\tcase RTW_IEEE80211_PROACTIVE_RANN:\n\t\trtw_mesh_path_sel_frame_tx(RTW_MPATH_RANN, flags, adapter_mac_addr(adapter),\n\t\t\t\t\t   ++minfo->sn, 0, NULL, 0, bcast_addr,\n\t\t\t\t\t   0, mshcfg->element_ttl,\n\t\t\t\t\t   interval, 0, 0, adapter);\n\t\tbreak;\n\tcase RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP:\n\t\tflags |= RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG;\n\tcase RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP:\n\t\tinterval = mshcfg->dot11MeshHWMPactivePathToRootTimeout;\n\t\ttarget_flags |= RTW_IEEE80211_PREQ_TO_FLAG |\n\t\t\t\tRTW_IEEE80211_PREQ_USN_FLAG;\n\t\trtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, adapter_mac_addr(adapter),\n\t\t\t\t\t   ++minfo->sn, target_flags,\n\t\t\t\t\t   (u8 *) bcast_addr, 0, bcast_addr,\n\t\t\t\t\t   0, mshcfg->element_ttl, interval,\n\t\t\t\t\t   0, minfo->preq_id++, adapter);\n\t\tbreak;\n\tdefault:\n\t\tRTW_HWMP_INFO(\"Proactive mechanism not supported\\n\");\n\t\treturn;\n\t}\n}\n\nvoid rtw_mesh_work(_workitem *work)\n{\n\t/* use kernel global workqueue */\n\t_set_workitem(work);\n}\n\nvoid rtw_ieee80211_mesh_path_timer(void *ctx)\n{\n\t_adapter *adapter = (_adapter *)ctx;\n\trtw_mesh_work(&adapter->mesh_work);\n}\n\nvoid rtw_ieee80211_mesh_path_root_timer(void *ctx)\n{\n\t_adapter *adapter = (_adapter *)ctx;\n\n\trtw_set_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags);\n\n\trtw_mesh_work(&adapter->mesh_work);\n}\n\nstatic void rtw_ieee80211_mesh_rootpath(_adapter *adapter)\n{\n\tu32 interval;\n\n\trtw_mesh_path_tx_root_frame(adapter);\n\n\tif (adapter->mesh_cfg.dot11MeshHWMPRootMode == RTW_IEEE80211_PROACTIVE_RANN)\n\t\tinterval = adapter->mesh_cfg.dot11MeshHWMPRannInterval;\n\telse\n\t\tinterval = adapter->mesh_cfg.dot11MeshHWMProotInterval;\n\n\trtw_mod_timer(&adapter->mesh_path_root_timer,\n\t\t  RTW_TU_TO_EXP_TIME(interval));\n}\n\nBOOLEAN rtw_ieee80211_mesh_root_setup(_adapter *adapter)\n{\n\tBOOLEAN root_enabled = _FALSE;\n\n\tif (adapter->mesh_cfg.dot11MeshHWMPRootMode > RTW_IEEE80211_ROOTMODE_ROOT) {\n\t\trtw_set_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags);\n\t\troot_enabled = _TRUE;\n\t}\n\telse {\n\t\trtw_clear_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags);\n\t\t/* stop running timer */\n\t\t_cancel_timer_ex(&adapter->mesh_path_root_timer);\n\t\troot_enabled = _FALSE;\n\t}\n\n\treturn root_enabled;\n}\n\nvoid rtw_mesh_work_hdl(_workitem *work)\n{\n\t_adapter *adapter = container_of(work, _adapter, mesh_work);\n\n\twhile(adapter->mesh_info.preq_queue_len) {\n\t\tif (rtw_time_after(rtw_get_current_time(),\n\t\t       adapter->mesh_info.last_preq + rtw_min_preq_int_jiff(adapter)))\n\t\t       /* It will consume preq_queue_len */\n\t\t       rtw_mesh_path_start_discovery(adapter);\n\t\telse {\n\t\t\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\n\t\t\trtw_mod_timer(&adapter->mesh_path_timer,\n\t\t\t\tminfo->last_preq + rtw_min_preq_int_jiff(adapter) + 1);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (rtw_test_and_clear_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags))\n\t\trtw_ieee80211_mesh_rootpath(adapter);\n}\n\n#ifndef RTW_PER_CMD_SUPPORT_FW\nstatic void rtw_update_metric_directly(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\tu8 i;\n\n\tfor (i = 0; i < macid_ctl->num; i++) {\n\t\tu8 role;\n\t\trole = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]);\n\t\tif (role == H2C_MSR_ROLE_MESH) {\n\t\t\tstruct sta_info *sta = macid_ctl->sta[i];\n\t\t\tu8 rate_idx, sgi, bw;\n\t\t\tu32 rate;\n\n\t\t\tif (!sta)\n\t\t\t\tcontinue;\n\t\t\trate_idx = rtw_get_current_tx_rate(adapter, sta);\n\t\t\tsgi = rtw_get_current_tx_sgi(adapter, sta);\n\t\t\tbw = sta->cmn.bw_mode;\n\t\t\trate = rtw_desc_rate_to_bitrate(bw, rate_idx, sgi);\n\t\t\tsta->metrics.data_rate = rate;\n\t\t}\n\t}\n}\n#endif\n\nvoid rtw_mesh_atlm_param_req_timer(void *ctx)\n{\n\t_adapter *adapter = (_adapter *)ctx;\n\tu8 ret = _FAIL;\n\n#ifdef RTW_PER_CMD_SUPPORT_FW\n\tret = rtw_req_per_cmd(adapter);\n\tif (ret == _FAIL)\n\t\tRTW_HWMP_INFO(\"rtw_req_per_cmd fail\\n\");\n#else\n\trtw_update_metric_directly(adapter);\n#endif\n\t_set_timer(&adapter->mesh_atlm_param_req_timer, RTW_ATLM_REQ_CYCLE);\n}\n\n#endif /* CONFIG_RTW_MESH */\n\n"
  },
  {
    "path": "core/mesh/rtw_mesh_hwmp.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_MESH_HWMP_H_\n#define __RTW_MESH_HWMP_H_\n\n#ifndef DBG_RTW_HWMP\n#define DBG_RTW_HWMP 0\n#endif\n#if DBG_RTW_HWMP\n#define RTW_HWMP_DBG(fmt, arg...) RTW_PRINT(fmt, ##arg)\n#else\n#define RTW_HWMP_DBG(fmt, arg...) RTW_DBG(fmt, ##arg)\n#endif\n\n#ifndef INFO_RTW_HWMP\n#define INFO_RTW_HWMP 0\n#endif\n#if INFO_RTW_HWMP\n#define RTW_HWMP_INFO(fmt, arg...) RTW_PRINT(fmt, ##arg)\n#else\n#define RTW_HWMP_INFO(fmt, arg...) RTW_INFO(fmt, ##arg)\n#endif\n\n\nvoid rtw_ewma_err_rate_init(struct rtw_ewma_err_rate *e);\nunsigned long rtw_ewma_err_rate_read(struct rtw_ewma_err_rate *e);\nvoid rtw_ewma_err_rate_add(struct rtw_ewma_err_rate *e, unsigned long val);\nint rtw_mesh_path_error_tx(_adapter *adapter,\n\t\t\t   u8 ttl, const u8 *target, u32 target_sn,\n\t\t\t   u16 target_rcode, const u8 *ra);\nvoid rtw_ieee80211s_update_metric(_adapter *adapter, u8 mac_id,\n\t\t\t\t  u8 per, u8 rate,\n\t\t\t\t  u8 bw, u8 total_pkt);\nvoid rtw_mesh_rx_path_sel_frame(_adapter *adapter, union recv_frame *rframe);\nvoid rtw_mesh_queue_preq(struct rtw_mesh_path *mpath, u8 flags);\nvoid rtw_mesh_path_start_discovery(_adapter *adapter);\nvoid rtw_mesh_path_timer(void *ctx);\nvoid rtw_mesh_path_tx_root_frame(_adapter *adapter);\nvoid rtw_mesh_work_hdl(_workitem *work);\nvoid rtw_ieee80211_mesh_path_timer(void *ctx);\nvoid rtw_ieee80211_mesh_path_root_timer(void *ctx);\nBOOLEAN rtw_ieee80211_mesh_root_setup(_adapter *adapter);\nvoid rtw_mesh_work(_workitem *work);\nvoid rtw_mesh_atlm_param_req_timer(void *ctx);\n\n#endif /* __RTW_MESH_HWMP_H_ */\n\n\n"
  },
  {
    "path": "core/mesh/rtw_mesh_pathtbl.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_MESH_PATHTBL_C_\n\n#ifdef CONFIG_RTW_MESH\n#include <drv_types.h>\n#include <linux/jhash.h>\n\n#ifdef PLATFORM_LINUX\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))\nstatic void rtw_mpath_free_rcu(struct rtw_mesh_path *mpath)\n{\n\tkfree_rcu(mpath, rcu);\n\trtw_mstat_update(MSTAT_TYPE_PHY, MSTAT_FREE, sizeof(struct rtw_mesh_path));\n}\n#else\nstatic void rtw_mpath_free_rcu_callback(rtw_rcu_head *head)\n{\n\tstruct rtw_mesh_path *mpath;\n\n\tmpath = container_of(head, struct rtw_mesh_path, rcu);\n\trtw_mfree(mpath, sizeof(struct rtw_mesh_path));\n}\n\nstatic void rtw_mpath_free_rcu(struct rtw_mesh_path *mpath)\n{\n\tcall_rcu(&mpath->rcu, rtw_mpath_free_rcu_callback);\n}\n#endif\n#endif /* PLATFORM_LINUX */\n\nstatic void rtw_mesh_path_free_rcu(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath);\n\nstatic u32 rtw_mesh_table_hash(const void *addr, u32 len, u32 seed)\n{\n\t/* Use last four bytes of hw addr as hash index */\n\treturn jhash_1word(*(u32 *)(addr+2), seed);\n}\n\nstatic const rtw_rhashtable_params rtw_mesh_rht_params = {\n\t.nelem_hint = 2,\n\t.automatic_shrinking = true,\n\t.key_len = ETH_ALEN,\n\t.key_offset = offsetof(struct rtw_mesh_path, dst),\n\t.head_offset = offsetof(struct rtw_mesh_path, rhash),\n\t.hashfn = rtw_mesh_table_hash,\n};\n\nstatic inline bool rtw_mpath_expired(struct rtw_mesh_path *mpath)\n{\n\treturn (mpath->flags & RTW_MESH_PATH_ACTIVE) &&\n\t       rtw_time_after(rtw_get_current_time(), mpath->exp_time) &&\n\t       !(mpath->flags & RTW_MESH_PATH_FIXED);\n}\n\nstatic void rtw_mesh_path_rht_free(void *ptr, void *tblptr)\n{\n\tstruct rtw_mesh_path *mpath = ptr;\n\tstruct rtw_mesh_table *tbl = tblptr;\n\n\trtw_mesh_path_free_rcu(tbl, mpath);\n}\n\nstatic struct rtw_mesh_table *rtw_mesh_table_alloc(void)\n{\n\tstruct rtw_mesh_table *newtbl;\n\n\tnewtbl = rtw_malloc(sizeof(struct rtw_mesh_table));\n\tif (!newtbl)\n\t\treturn NULL;\n\n\trtw_hlist_head_init(&newtbl->known_gates);\n\tATOMIC_SET(&newtbl->entries,  0);\n\t_rtw_spinlock_init(&newtbl->gates_lock);\n\n\treturn newtbl;\n}\n\nstatic void rtw_mesh_table_free(struct rtw_mesh_table *tbl)\n{\n\trtw_rhashtable_free_and_destroy(&tbl->rhead,\n\t\t\t\t    rtw_mesh_path_rht_free, tbl);\n\trtw_mfree(tbl, sizeof(struct rtw_mesh_table));\n}\n\n/**\n *\n * rtw_mesh_path_assign_nexthop - update mesh path next hop\n *\n * @mpath: mesh path to update\n * @sta: next hop to assign\n *\n * Locking: mpath->state_lock must be held when calling this function\n */\nvoid rtw_mesh_path_assign_nexthop(struct rtw_mesh_path *mpath, struct sta_info *sta)\n{\n\tstruct xmit_frame *xframe;\n\t_list *list, *head;\n\n\trtw_rcu_assign_pointer(mpath->next_hop, sta);\n\n\tenter_critical_bh(&mpath->frame_queue.lock);\n\thead = &mpath->frame_queue.queue;\n\tlist = get_next(head);\n\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\txframe = LIST_CONTAINOR(list, struct xmit_frame, list);\n\t\tlist = get_next(list);\n\t\t_rtw_memcpy(xframe->attrib.ra, sta->cmn.mac_addr, ETH_ALEN);\n\t}\n\n\texit_critical_bh(&mpath->frame_queue.lock);\n}\n\nstatic void rtw_prepare_for_gate(struct xmit_frame *xframe, char *dst_addr,\n\t\t\t     struct rtw_mesh_path *gate_mpath)\n{\n\tstruct pkt_attrib *attrib = &xframe->attrib;\n\tchar *next_hop;\n\n\tif (attrib->mesh_frame_mode == MESH_UCAST_DATA)\n\t\tattrib->mesh_frame_mode = MESH_UCAST_PX_DATA;\n\n\t/* update next hop */\n\trtw_rcu_read_lock();\n\tnext_hop = rtw_rcu_dereference(gate_mpath->next_hop)->cmn.mac_addr;\n\t_rtw_memcpy(attrib->ra, next_hop, ETH_ALEN);\n\trtw_rcu_read_unlock();\n\t_rtw_memcpy(attrib->mda, dst_addr, ETH_ALEN);\n}\n\n/**\n *\n * rtw_mesh_path_move_to_queue - Move or copy frames from one mpath queue to another\n *\n * This function is used to transfer or copy frames from an unresolved mpath to\n * a gate mpath.  The function also adds the Address Extension field and\n * updates the next hop.\n *\n * If a frame already has an Address Extension field, only the next hop and\n * destination addresses are updated.\n *\n * The gate mpath must be an active mpath with a valid mpath->next_hop.\n *\n * @mpath: An active mpath the frames will be sent to (i.e. the gate)\n * @from_mpath: The failed mpath\n * @copy: When true, copy all the frames to the new mpath queue.  When false,\n * move them.\n */\nstatic void rtw_mesh_path_move_to_queue(struct rtw_mesh_path *gate_mpath,\n\t\t\t\t    struct rtw_mesh_path *from_mpath,\n\t\t\t\t    bool copy)\n{\n\tstruct xmit_frame *fskb;\n\t_list *list, *head;\n\t_list failq;\n\tu32 failq_len;\n\t_irqL flags;\n\n\tif (rtw_warn_on(gate_mpath == from_mpath))\n\t\treturn;\n\tif (rtw_warn_on(!gate_mpath->next_hop))\n\t\treturn;\n\n\t_rtw_init_listhead(&failq);\n\n\t_enter_critical_bh(&from_mpath->frame_queue.lock, &flags);\n\trtw_list_splice_init(&from_mpath->frame_queue.queue, &failq);\n\tfailq_len = from_mpath->frame_queue_len;\n\tfrom_mpath->frame_queue_len = 0;\n\t_exit_critical_bh(&from_mpath->frame_queue.lock, &flags);\n\n\thead = &failq;\n\tlist = get_next(head);\n\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\tif (gate_mpath->frame_queue_len >= RTW_MESH_FRAME_QUEUE_LEN) {\n\t\t\tRTW_MPATH_DBG(FUNC_ADPT_FMT\" mpath queue for gate %pM is full!\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(gate_mpath->adapter), gate_mpath->dst);\n\t\t\tbreak;\n\t\t}\n\n\t\tfskb = LIST_CONTAINOR(list, struct xmit_frame, list);\n\t\tlist = get_next(list);\n\n\t\trtw_list_delete(&fskb->list);\n\t\tfailq_len--;\n\t\trtw_prepare_for_gate(fskb, gate_mpath->dst, gate_mpath);\n\t\t_enter_critical_bh(&gate_mpath->frame_queue.lock, &flags);\n\t\trtw_list_insert_tail(&fskb->list, get_list_head(&gate_mpath->frame_queue));\n\t\tgate_mpath->frame_queue_len++;\n\t\t_exit_critical_bh(&gate_mpath->frame_queue.lock, &flags);\n\n\t\t#if 0 /* TODO: copy */\n\t\tskb = rtw_skb_copy(fskb);\n\t\tif (rtw_warn_on(!skb))\n\t\t\tbreak;\n\n\t\trtw_prepare_for_gate(skb, gate_mpath->dst, gate_mpath);\n\t\tskb_queue_tail(&gate_mpath->frame_queue, skb);\n\n\t\tif (copy)\n\t\t\tcontinue;\n\n\t\t__skb_unlink(fskb, &failq);\n\t\trtw_skb_free(fskb);\n\t\t#endif\n\t}\n\n\tRTW_MPATH_DBG(FUNC_ADPT_FMT\" mpath queue for gate %pM has %d frames\\n\"\n\t\t, FUNC_ADPT_ARG(gate_mpath->adapter), gate_mpath->dst, gate_mpath->frame_queue_len);\n\n\tif (!copy)\n\t\treturn;\n\n\t_enter_critical_bh(&from_mpath->frame_queue.lock, &flags);\n\trtw_list_splice(&failq, &from_mpath->frame_queue.queue);\n\tfrom_mpath->frame_queue_len += failq_len;\n\t_exit_critical_bh(&from_mpath->frame_queue.lock, &flags);\n}\n\n\nstatic struct rtw_mesh_path *rtw_mpath_lookup(struct rtw_mesh_table *tbl, const u8 *dst)\n{\n\tstruct rtw_mesh_path *mpath;\n\n\tif (!tbl)\n\t\treturn NULL;\n\n\tmpath = rtw_rhashtable_lookup_fast(&tbl->rhead, dst, rtw_mesh_rht_params);\n\n\tif (mpath && rtw_mpath_expired(mpath)) {\n\t\tenter_critical_bh(&mpath->state_lock);\n\t\tmpath->flags &= ~RTW_MESH_PATH_ACTIVE;\n\t\texit_critical_bh(&mpath->state_lock);\n\t}\n\treturn mpath;\n}\n\n/**\n * rtw_mesh_path_lookup - look up a path in the mesh path table\n * @sdata: local subif\n * @dst: hardware address (ETH_ALEN length) of destination\n *\n * Returns: pointer to the mesh path structure, or NULL if not found\n *\n * Locking: must be called within a read rcu section.\n */\nstruct rtw_mesh_path *\nrtw_mesh_path_lookup(_adapter *adapter, const u8 *dst)\n{\n\treturn rtw_mpath_lookup(adapter->mesh_info.mesh_paths, dst);\n}\n\nstruct rtw_mesh_path *\nrtw_mpp_path_lookup(_adapter *adapter, const u8 *dst)\n{\n\treturn rtw_mpath_lookup(adapter->mesh_info.mpp_paths, dst);\n}\n\nstatic struct rtw_mesh_path *\n__rtw_mesh_path_lookup_by_idx(struct rtw_mesh_table *tbl, int idx)\n{\n\tint i = 0, ret;\n\tstruct rtw_mesh_path *mpath = NULL;\n\trtw_rhashtable_iter iter;\n\n\tif (!tbl)\n\t\treturn NULL;\n\n\tret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);\n\tif (ret)\n\t\treturn NULL;\n\n\tret = rtw_rhashtable_walk_start(&iter);\n\tif (ret && ret != -EAGAIN)\n\t\tgoto err;\n\n\twhile ((mpath = rtw_rhashtable_walk_next(&iter))) {\n\t\tif (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)\n\t\t\tcontinue;\n\t\tif (IS_ERR(mpath))\n\t\t\tbreak;\n\t\tif (i++ == idx)\n\t\t\tbreak;\n\t}\nerr:\n\trtw_rhashtable_walk_stop(&iter);\n\trtw_rhashtable_walk_exit(&iter);\n\n\tif (IS_ERR(mpath) || !mpath)\n\t\treturn NULL;\n\n\tif (rtw_mpath_expired(mpath)) {\n\t\tenter_critical_bh(&mpath->state_lock);\n\t\tmpath->flags &= ~RTW_MESH_PATH_ACTIVE;\n\t\texit_critical_bh(&mpath->state_lock);\n\t}\n\treturn mpath;\n}\n\n/**\n * rtw_mesh_path_lookup_by_idx - look up a path in the mesh path table by its index\n * @idx: index\n * @sdata: local subif, or NULL for all entries\n *\n * Returns: pointer to the mesh path structure, or NULL if not found.\n *\n * Locking: must be called within a read rcu section.\n */\nstruct rtw_mesh_path *\nrtw_mesh_path_lookup_by_idx(_adapter *adapter, int idx)\n{\n\treturn __rtw_mesh_path_lookup_by_idx(adapter->mesh_info.mesh_paths, idx);\n}\n\nvoid dump_mpath(void *sel, _adapter *adapter)\n{\n\tstruct rtw_mesh_path *mpath;\n\tint idx = 0;\n\tchar dst[ETH_ALEN];\n\tchar next_hop[ETH_ALEN];\n\tu32 sn, metric, qlen;\n\tu32 exp_ms = 0, dto_ms;\n\tu8 drty;\n\tenum rtw_mesh_path_flags flags;\n\n\tRTW_PRINT_SEL(sel, \"%-17s %-17s %-10s %-10s %-4s %-6s %-6s %-4s flags\\n\"\n\t\t, \"dst\", \"next_hop\", \"sn\", \"metric\", \"qlen\", \"exp_ms\", \"dto_ms\", \"drty\"\n\t);\n\n\tdo {\n\t\trtw_rcu_read_lock();\n\n\t\tmpath = rtw_mesh_path_lookup_by_idx(adapter, idx);\n\t\tif (mpath) {\n\t\t\t_rtw_memcpy(dst, mpath->dst, ETH_ALEN);\n\t\t\t_rtw_memcpy(next_hop, mpath->next_hop->cmn.mac_addr, ETH_ALEN);\n\t\t\tsn = mpath->sn;\n\t\t\tmetric = mpath->metric;\n\t\t\tqlen = mpath->frame_queue_len;\n\t\t\tif (rtw_time_after(mpath->exp_time, rtw_get_current_time()))\n\t\t\t\texp_ms = rtw_get_remaining_time_ms(mpath->exp_time);\n\t\t\tdto_ms = rtw_systime_to_ms(mpath->discovery_timeout);\n\t\t\tdrty = mpath->discovery_retries;\n\t\t\tflags = mpath->flags;\n\t\t}\n\n\t\trtw_rcu_read_unlock();\n\n\t\tif (mpath) {\n\t\t\tRTW_PRINT_SEL(sel, MAC_FMT\" \"MAC_FMT\" %10u %10u %4u %6u %6u %4u%s%s%s%s%s%s%s%s%s%s\\n\"\n\t\t\t\t, MAC_ARG(dst), MAC_ARG(next_hop), sn, metric, qlen\n\t\t\t\t, exp_ms < 999999 ? exp_ms : 999999\n\t\t\t\t, dto_ms < 999999 ? dto_ms : 999999\n\t\t\t\t, drty\n\t\t\t\t, (flags & RTW_MESH_PATH_ACTIVE) ? \" ACT\" : \"\"\n\t\t\t\t, (flags & RTW_MESH_PATH_RESOLVING) ? \" RSVING\" : \"\"\n\t\t\t\t, (flags & RTW_MESH_PATH_SN_VALID) ? \" SN_VALID\" : \"\"\n\t\t\t\t, (flags & RTW_MESH_PATH_FIXED) ?  \" FIXED\" : \"\"\n\t\t\t\t, (flags & RTW_MESH_PATH_RESOLVED) ? \" RSVED\" : \"\"\n\t\t\t\t, (flags & RTW_MESH_PATH_REQ_QUEUED) ? \" REQ_IN_Q\" : \"\"\n\t\t\t\t, (flags & RTW_MESH_PATH_DELETED) ? \" DELETED\" : \"\"\n\t\t\t\t, (flags & RTW_MESH_PATH_ROOT_ADD_CHK) ? \" R_ADD_CHK\" : \"\"\n\t\t\t\t, (flags & RTW_MESH_PATH_PEER_AKA) ? \" PEER_AKA\" : \"\"\n\t\t\t\t, (flags & RTW_MESH_PATH_BCAST_PREQ) ? \" BC_PREQ\" : \"\"\n\t\t\t);\n\t\t}\n\n\t\tidx++;\n\t} while (mpath);\n}\n\n/**\n * rtw_mpp_path_lookup_by_idx - look up a path in the proxy path table by its index\n * @idx: index\n * @sdata: local subif, or NULL for all entries\n *\n * Returns: pointer to the proxy path structure, or NULL if not found.\n *\n * Locking: must be called within a read rcu section.\n */\nstruct rtw_mesh_path *\nrtw_mpp_path_lookup_by_idx(_adapter *adapter, int idx)\n{\n\treturn __rtw_mesh_path_lookup_by_idx(adapter->mesh_info.mpp_paths, idx);\n}\n\n/**\n * rtw_mesh_path_add_gate - add the given mpath to a mesh gate to our path table\n * @mpath: gate path to add to table\n */\nint rtw_mesh_path_add_gate(struct rtw_mesh_path *mpath)\n{\n\tstruct rtw_mesh_cfg *mcfg;\n\tstruct rtw_mesh_info *minfo;\n\tstruct rtw_mesh_table *tbl;\n\tint err, ori_num_gates;\n\n\trtw_rcu_read_lock();\n\ttbl = mpath->adapter->mesh_info.mesh_paths;\n\tif (!tbl) {\n\t\terr = -ENOENT;\n\t\tgoto err_rcu;\n\t}\n\n\tenter_critical_bh(&mpath->state_lock);\n\tmcfg = &mpath->adapter->mesh_cfg;\n\tmpath->gate_timeout = rtw_get_current_time() +\n\t\t\t      rtw_ms_to_systime(mcfg->path_gate_timeout_factor *\n\t\t\t\t\t        mpath->gate_ann_int);\n\tif (mpath->is_gate) {\n\t\terr = -EEXIST;\n\t\texit_critical_bh(&mpath->state_lock);\n\t\tgoto err_rcu;\n\t}\n\n\tminfo = &mpath->adapter->mesh_info;\n\tmpath->is_gate = true;\n\t_rtw_spinlock(&tbl->gates_lock);\n\tori_num_gates = minfo->num_gates;\n\tminfo->num_gates++;\n\trtw_hlist_add_head_rcu(&mpath->gate_list, &tbl->known_gates);\n\n\tif (ori_num_gates == 0\n\t\t|| rtw_macaddr_is_larger(mpath->dst, minfo->max_addr_gate->dst)\n\t) {\n\t\tminfo->max_addr_gate = mpath;\n\t\tminfo->max_addr_gate_is_larger_than_self =\n\t\t\trtw_macaddr_is_larger(mpath->dst, adapter_mac_addr(mpath->adapter));\n\t}\n\n\t_rtw_spinunlock(&tbl->gates_lock);\n\n\texit_critical_bh(&mpath->state_lock);\n\n\tif (ori_num_gates == 0) {\n\t\tupdate_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE, 0);\n\t\t#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER\n\t\tif (!rtw_mesh_cto_mgate_required(mpath->adapter))\n\t\t\trtw_netif_carrier_on(mpath->adapter->pnetdev);\n\t\t#endif\n\t}\n\n\tRTW_MPATH_DBG(\n\t\t  FUNC_ADPT_FMT\" Mesh path: Recorded new gate: %pM. %d known gates\\n\",\n\t\t  FUNC_ADPT_ARG(mpath->adapter),\n\t\t  mpath->dst, mpath->adapter->mesh_info.num_gates);\n\terr = 0;\nerr_rcu:\n\trtw_rcu_read_unlock();\n\treturn err;\n}\n\n/**\n * rtw_mesh_gate_del - remove a mesh gate from the list of known gates\n * @tbl: table which holds our list of known gates\n * @mpath: gate mpath\n */\nvoid rtw_mesh_gate_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath)\n{\n\tstruct rtw_mesh_cfg *mcfg;\n\tstruct rtw_mesh_info *minfo;\n\tint ori_num_gates;\n\n\trtw_lockdep_assert_held(&mpath->state_lock);\n\tif (!mpath->is_gate)\n\t\treturn;\n\n\tmcfg = &mpath->adapter->mesh_cfg;\n\tminfo = &mpath->adapter->mesh_info;\n\n\tmpath->is_gate = false;\n\tenter_critical_bh(&tbl->gates_lock);\n\trtw_hlist_del_rcu(&mpath->gate_list);\n\tori_num_gates = minfo->num_gates;\n\tminfo->num_gates--;\n\n\tif (ori_num_gates == 1) {\n\t\tminfo->max_addr_gate = NULL;\n\t\tminfo->max_addr_gate_is_larger_than_self = 0;\n\t} else if (minfo->max_addr_gate == mpath) {\n\t\tstruct rtw_mesh_path *gate, *max_addr_gate = NULL;\n\t\trtw_hlist_node *node;\n\n\t\trtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {\n\t\t\tif (!max_addr_gate || rtw_macaddr_is_larger(gate->dst, max_addr_gate->dst))\n\t\t\t\tmax_addr_gate = gate;\n\t\t}\n\t\tminfo->max_addr_gate = max_addr_gate;\n\t\tminfo->max_addr_gate_is_larger_than_self =\n\t\t\trtw_macaddr_is_larger(max_addr_gate->dst, adapter_mac_addr(mpath->adapter));\n\t}\n\n\texit_critical_bh(&tbl->gates_lock);\n\n\tif (ori_num_gates == 1) {\n\t\tupdate_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE, 0);\n\t\t#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER\n\t\tif (rtw_mesh_cto_mgate_required(mpath->adapter))\n\t\t\trtw_netif_carrier_off(mpath->adapter->pnetdev);\n\t\t#endif\n\t}\n\n\tRTW_MPATH_DBG(\n\t\t  FUNC_ADPT_FMT\" Mesh path: Deleted gate: %pM. %d known gates\\n\",\n\t\t  FUNC_ADPT_ARG(mpath->adapter),\n\t\t  mpath->dst, mpath->adapter->mesh_info.num_gates);\n}\n\n/**\n * rtw_mesh_gate_search - search a mesh gate from the list of known gates\n * @tbl: table which holds our list of known gates\n * @addr: address of gate\n */\nbool rtw_mesh_gate_search(struct rtw_mesh_table *tbl, const u8 *addr)\n{\n\tstruct rtw_mesh_path *gate;\n\trtw_hlist_node *node;\n\tbool exist = 0;\n\n\trtw_rcu_read_lock();\n\trtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {\n\t\tif (_rtw_memcmp(gate->dst, addr, ETH_ALEN) == _TRUE) {\n\t\t\texist = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\trtw_rcu_read_unlock();\n\n\treturn exist;\n}\n\n/**\n * rtw_mesh_gate_num - number of gates known to this interface\n * @sdata: subif data\n */\nint rtw_mesh_gate_num(_adapter *adapter)\n{\n\treturn adapter->mesh_info.num_gates;\n}\n\nbool rtw_mesh_is_primary_gate(_adapter *adapter)\n{\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\n\treturn mcfg->dot11MeshGateAnnouncementProtocol\n\t\t&& !minfo->max_addr_gate_is_larger_than_self;\n}\n\nvoid dump_known_gates(void *sel, _adapter *adapter)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct rtw_mesh_table *tbl;\n\tstruct rtw_mesh_path *gate;\n\trtw_hlist_node *node;\n\n\tif (!rtw_mesh_gate_num(adapter))\n\t\tgoto exit;\n\n\trtw_rcu_read_lock();\n\n\ttbl = minfo->mesh_paths;\n\tif (!tbl)\n\t\tgoto unlock;\n\n\tRTW_PRINT_SEL(sel, \"num:%d\\n\", rtw_mesh_gate_num(adapter));\n\n\trtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {\n\t\tRTW_PRINT_SEL(sel, \"%c\"MAC_FMT\"\\n\"\n\t\t\t, gate == minfo->max_addr_gate ? '*' : ' '\n\t\t\t, MAC_ARG(gate->dst));\n\t}\n\nunlock:\n\trtw_rcu_read_unlock();\nexit:\n\treturn;\n}\n\nstatic\nstruct rtw_mesh_path *rtw_mesh_path_new(_adapter *adapter,\n\t\t\t\tconst u8 *dst)\n{\n\tstruct rtw_mesh_path *new_mpath;\n\n\tnew_mpath = rtw_zmalloc(sizeof(struct rtw_mesh_path));\n\tif (!new_mpath)\n\t\treturn NULL;\n\n\t_rtw_memcpy(new_mpath->dst, dst, ETH_ALEN);\n\t_rtw_memset(new_mpath->rann_snd_addr, 0xFF, ETH_ALEN);\n\tnew_mpath->is_root = false;\n\tnew_mpath->adapter = adapter;\n\tnew_mpath->flags = 0;\n\tnew_mpath->gate_asked = false;\n\t_rtw_init_queue(&new_mpath->frame_queue);\n\tnew_mpath->frame_queue_len = 0;\n\tnew_mpath->exp_time = rtw_get_current_time();\n\t_rtw_spinlock_init(&new_mpath->state_lock);\n\trtw_init_timer(&new_mpath->timer, adapter, rtw_mesh_path_timer, new_mpath);\n\n\treturn new_mpath;\n}\n\n/**\n * rtw_mesh_path_add - allocate and add a new path to the mesh path table\n * @dst: destination address of the path (ETH_ALEN length)\n * @sdata: local subif\n *\n * Returns: 0 on success\n *\n * State: the initial state of the new path is set to 0\n */\nstruct rtw_mesh_path *rtw_mesh_path_add(_adapter *adapter,\n\t\t\t\tconst u8 *dst)\n{\n\tstruct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths;\n\tstruct rtw_mesh_path *mpath, *new_mpath;\n\tint ret;\n\n\tif (!tbl)\n\t\treturn ERR_PTR(-ENOTSUPP);\n\n\tif (_rtw_memcmp(dst, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)\n\t\t/* never add ourselves as neighbours */\n\t\treturn ERR_PTR(-ENOTSUPP);\n\n\tif (is_multicast_mac_addr(dst))\n\t\treturn ERR_PTR(-ENOTSUPP);\n\n\tif (ATOMIC_INC_UNLESS(&adapter->mesh_info.mpaths, RTW_MESH_MAX_MPATHS) == 0)\n\t\treturn ERR_PTR(-ENOSPC);\n\n\tnew_mpath = rtw_mesh_path_new(adapter, dst);\n\tif (!new_mpath)\n\t\treturn ERR_PTR(-ENOMEM);\n\n\tdo {\n\t\tret = rtw_rhashtable_lookup_insert_fast(&tbl->rhead,\n\t\t\t\t\t\t    &new_mpath->rhash,\n\t\t\t\t\t\t    rtw_mesh_rht_params);\n\n\t\tif (ret == -EEXIST)\n\t\t\tmpath = rtw_rhashtable_lookup_fast(&tbl->rhead,\n\t\t\t\t\t\t       dst,\n\t\t\t\t\t\t       rtw_mesh_rht_params);\n\n\t} while (unlikely(ret == -EEXIST && !mpath));\n\n\tif (ret && ret != -EEXIST)\n\t\treturn ERR_PTR(ret);\n\n\t/* At this point either new_mpath was added, or we found a\n\t * matching entry already in the table; in the latter case\n\t * free the unnecessary new entry.\n\t */\n\tif (ret == -EEXIST) {\n\t\trtw_mfree(new_mpath, sizeof(struct rtw_mesh_path));\n\t\tnew_mpath = mpath;\n\t}\n\tadapter->mesh_info.mesh_paths_generation++;\n\treturn new_mpath;\n}\n\nint rtw_mpp_path_add(_adapter *adapter,\n\t\t const u8 *dst, const u8 *mpp)\n{\n\tstruct rtw_mesh_table *tbl = adapter->mesh_info.mpp_paths;\n\tstruct rtw_mesh_path *new_mpath;\n\tint ret;\n\n\tif (!tbl)\n\t\treturn -ENOTSUPP;\n\n\tif (_rtw_memcmp(dst, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)\n\t\t/* never add ourselves as neighbours */\n\t\treturn -ENOTSUPP;\n\n\tif (is_multicast_mac_addr(dst))\n\t\treturn -ENOTSUPP;\n\n\tnew_mpath = rtw_mesh_path_new(adapter, dst);\n\n\tif (!new_mpath)\n\t\treturn -ENOMEM;\n\n\t_rtw_memcpy(new_mpath->mpp, mpp, ETH_ALEN);\n\tret = rtw_rhashtable_lookup_insert_fast(&tbl->rhead,\n\t\t\t\t\t    &new_mpath->rhash,\n\t\t\t\t\t    rtw_mesh_rht_params);\n\n\tadapter->mesh_info.mpp_paths_generation++;\n\treturn ret;\n}\n\nvoid dump_mpp(void *sel, _adapter *adapter)\n{\n\tstruct rtw_mesh_path *mpath;\n\tint idx = 0;\n\tchar dst[ETH_ALEN];\n\tchar mpp[ETH_ALEN];\n\n\tRTW_PRINT_SEL(sel, \"%-17s %-17s\\n\", \"dst\", \"mpp\");\n\n\tdo {\n\t\trtw_rcu_read_lock();\n\n\t\tmpath = rtw_mpp_path_lookup_by_idx(adapter, idx);\n\t\tif (mpath) {\n\t\t\t_rtw_memcpy(dst, mpath->dst, ETH_ALEN);\n\t\t\t_rtw_memcpy(mpp, mpath->mpp, ETH_ALEN);\n\t\t}\n\n\t\trtw_rcu_read_unlock();\n\n\t\tif (mpath) {\n\t\t\tRTW_PRINT_SEL(sel, MAC_FMT\" \"MAC_FMT\"\\n\"\n\t\t\t\t, MAC_ARG(dst), MAC_ARG(mpp));\n\t\t}\n\n\t\tidx++;\n\t} while (mpath);\n}\n\n/**\n * rtw_mesh_plink_broken - deactivates paths and sends perr when a link breaks\n *\n * @sta: broken peer link\n *\n * This function must be called from the rate control algorithm if enough\n * delivery errors suggest that a peer link is no longer usable.\n */\nvoid rtw_mesh_plink_broken(struct sta_info *sta)\n{\n\t_adapter *adapter = sta->padapter;\n\tstruct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths;\n\tstatic const u8 bcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tstruct rtw_mesh_path *mpath;\n\trtw_rhashtable_iter iter;\n\tint ret;\n\n\tif (!tbl)\n\t\treturn;\n\n\tret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);\n\tif (ret)\n\t\treturn;\n\n\tret = rtw_rhashtable_walk_start(&iter);\n\tif (ret && ret != -EAGAIN)\n\t\tgoto out;\n\n\twhile ((mpath = rtw_rhashtable_walk_next(&iter))) {\n\t\tif (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)\n\t\t\tcontinue;\n\t\tif (IS_ERR(mpath))\n\t\t\tbreak;\n\t\tif (rtw_rcu_access_pointer(mpath->next_hop) == sta &&\n\t\t    mpath->flags & RTW_MESH_PATH_ACTIVE &&\n\t\t    !(mpath->flags & RTW_MESH_PATH_FIXED)) {\n\t\t\tenter_critical_bh(&mpath->state_lock);\n\t\t\tmpath->flags &= ~RTW_MESH_PATH_ACTIVE;\n\t\t\t++mpath->sn;\n\t\t\texit_critical_bh(&mpath->state_lock);\n\t\t\trtw_mesh_path_error_tx(adapter,\n\t\t\t\tadapter->mesh_cfg.element_ttl,\n\t\t\t\tmpath->dst, mpath->sn,\n\t\t\t\tWLAN_REASON_MESH_PATH_DEST_UNREACHABLE, bcast);\n\t\t}\n\t}\nout:\n\trtw_rhashtable_walk_stop(&iter);\n\trtw_rhashtable_walk_exit(&iter);\n}\n\nstatic void rtw_mesh_path_free_rcu(struct rtw_mesh_table *tbl,\n\t\t\t       struct rtw_mesh_path *mpath)\n{\n\t_adapter *adapter = mpath->adapter;\n\n\tenter_critical_bh(&mpath->state_lock);\n\tmpath->flags |= RTW_MESH_PATH_RESOLVING | RTW_MESH_PATH_DELETED;\n\trtw_mesh_gate_del(tbl, mpath);\n\texit_critical_bh(&mpath->state_lock);\n\t_cancel_timer_ex(&mpath->timer);\n\tATOMIC_DEC(&adapter->mesh_info.mpaths);\n\tATOMIC_DEC(&tbl->entries);\n\t_rtw_spinlock_free(&mpath->state_lock);\n\n\trtw_mesh_path_flush_pending(mpath);\n\n\trtw_mpath_free_rcu(mpath);\n}\n\nstatic void __rtw_mesh_path_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath)\n{\n\trtw_rhashtable_remove_fast(&tbl->rhead, &mpath->rhash, rtw_mesh_rht_params);\n\trtw_mesh_path_free_rcu(tbl, mpath);\n}\n\n/**\n * rtw_mesh_path_flush_by_nexthop - Deletes mesh paths if their next hop matches\n *\n * @sta: mesh peer to match\n *\n * RCU notes: this function is called when a mesh plink transitions from\n * PLINK_ESTAB to any other state, since PLINK_ESTAB state is the only one that\n * allows path creation. This will happen before the sta can be freed (because\n * sta_info_destroy() calls this) so any reader in a rcu read block will be\n * protected against the plink disappearing.\n */\nvoid rtw_mesh_path_flush_by_nexthop(struct sta_info *sta)\n{\n\t_adapter *adapter = sta->padapter;\n\tstruct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths;\n\tstruct rtw_mesh_path *mpath;\n\trtw_rhashtable_iter iter;\n\tint ret;\n\n\tif (!tbl)\n\t\treturn;\n\n\tret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);\n\tif (ret)\n\t\treturn;\n\n\tret = rtw_rhashtable_walk_start(&iter);\n\tif (ret && ret != -EAGAIN)\n\t\tgoto out;\n\n\twhile ((mpath = rtw_rhashtable_walk_next(&iter))) {\n\t\tif (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)\n\t\t\tcontinue;\n\t\tif (IS_ERR(mpath))\n\t\t\tbreak;\n\n\t\tif (rtw_rcu_access_pointer(mpath->next_hop) == sta)\n\t\t\t__rtw_mesh_path_del(tbl, mpath);\n\t}\nout:\n\trtw_rhashtable_walk_stop(&iter);\n\trtw_rhashtable_walk_exit(&iter);\n}\n\nstatic void rtw_mpp_flush_by_proxy(_adapter *adapter,\n\t\t\t       const u8 *proxy)\n{\n\tstruct rtw_mesh_table *tbl = adapter->mesh_info.mpp_paths;\n\tstruct rtw_mesh_path *mpath;\n\trtw_rhashtable_iter iter;\n\tint ret;\n\n\tif (!tbl)\n\t\treturn;\n\n\tret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);\n\tif (ret)\n\t\treturn;\n\n\tret = rtw_rhashtable_walk_start(&iter);\n\tif (ret && ret != -EAGAIN)\n\t\tgoto out;\n\n\twhile ((mpath = rtw_rhashtable_walk_next(&iter))) {\n\t\tif (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)\n\t\t\tcontinue;\n\t\tif (IS_ERR(mpath))\n\t\t\tbreak;\n\n\t\tif (_rtw_memcmp(mpath->mpp, proxy, ETH_ALEN) == _TRUE)\n\t\t\t__rtw_mesh_path_del(tbl, mpath);\n\t}\nout:\n\trtw_rhashtable_walk_stop(&iter);\n\trtw_rhashtable_walk_exit(&iter);\n}\n\nstatic void rtw_table_flush_by_iface(struct rtw_mesh_table *tbl)\n{\n\tstruct rtw_mesh_path *mpath;\n\trtw_rhashtable_iter iter;\n\tint ret;\n\n\tif (!tbl)\n\t\treturn;\n\t\n\tret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);\n\tif (ret)\n\t\treturn;\n\n\tret = rtw_rhashtable_walk_start(&iter);\n\tif (ret && ret != -EAGAIN)\n\t\tgoto out;\n\n\twhile ((mpath = rtw_rhashtable_walk_next(&iter))) {\n\t\tif (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)\n\t\t\tcontinue;\n\t\tif (IS_ERR(mpath))\n\t\t\tbreak;\n\t\t__rtw_mesh_path_del(tbl, mpath);\n\t}\nout:\n\trtw_rhashtable_walk_stop(&iter);\n\trtw_rhashtable_walk_exit(&iter);\n}\n\n/**\n * rtw_mesh_path_flush_by_iface - Deletes all mesh paths associated with a given iface\n *\n * This function deletes both mesh paths as well as mesh portal paths.\n *\n * @sdata: interface data to match\n *\n */\nvoid rtw_mesh_path_flush_by_iface(_adapter *adapter)\n{\n\trtw_table_flush_by_iface(adapter->mesh_info.mesh_paths);\n\trtw_table_flush_by_iface(adapter->mesh_info.mpp_paths);\n}\n\n/**\n * rtw_table_path_del - delete a path from the mesh or mpp table\n *\n * @tbl: mesh or mpp path table\n * @sdata: local subif\n * @addr: dst address (ETH_ALEN length)\n *\n * Returns: 0 if successful\n */\nstatic int rtw_table_path_del(struct rtw_mesh_table *tbl,\n\t\t\t  const u8 *addr)\n{\n\tstruct rtw_mesh_path *mpath;\n\n\tif (!tbl)\n\t\treturn -ENXIO;\n\n\trtw_rcu_read_lock();\n\tmpath = rtw_rhashtable_lookup_fast(&tbl->rhead, addr, rtw_mesh_rht_params);\n\tif (!mpath) {\n\t\trtw_rcu_read_unlock();\n\t\treturn -ENXIO;\n\t}\n\n\t__rtw_mesh_path_del(tbl, mpath);\n\trtw_rcu_read_unlock();\n\treturn 0;\n}\n\n\n/**\n * rtw_mesh_path_del - delete a mesh path from the table\n *\n * @addr: dst address (ETH_ALEN length)\n * @sdata: local subif\n *\n * Returns: 0 if successful\n */\nint rtw_mesh_path_del(_adapter *adapter, const u8 *addr)\n{\n\tint err;\n\n\t/* flush relevant mpp entries first */\n\trtw_mpp_flush_by_proxy(adapter, addr);\n\n\terr = rtw_table_path_del(adapter->mesh_info.mesh_paths, addr);\n\tadapter->mesh_info.mesh_paths_generation++;\n\treturn err;\n}\n\n/**\n * rtw_mesh_path_tx_pending - sends pending frames in a mesh path queue\n *\n * @mpath: mesh path to activate\n *\n * Locking: the state_lock of the mpath structure must NOT be held when calling\n * this function.\n */\nvoid rtw_mesh_path_tx_pending(struct rtw_mesh_path *mpath)\n{\n\tif (mpath->flags & RTW_MESH_PATH_ACTIVE) {\n\t\tstruct rtw_mesh_info *minfo = &mpath->adapter->mesh_info;\n\t\t_list q;\n\t\tu32 q_len = 0;\n\n\t\t_rtw_init_listhead(&q);\n\n\t\t/* move to local queue */\n\t\tenter_critical_bh(&mpath->frame_queue.lock);\n\t\tif (mpath->frame_queue_len) {\n\t\t\trtw_list_splice_init(&mpath->frame_queue.queue, &q);\n\t\t\tq_len = mpath->frame_queue_len;\n\t\t\tmpath->frame_queue_len = 0;\n\t\t}\n\t\texit_critical_bh(&mpath->frame_queue.lock);\n\n\t\tif (q_len) {\n\t\t\t/* move to mpath_tx_queue */\n\t\t\tenter_critical_bh(&minfo->mpath_tx_queue.lock);\n\t\t\trtw_list_splice_tail(&q, &minfo->mpath_tx_queue.queue);\n\t\t\tminfo->mpath_tx_queue_len += q_len;\n\t\t\texit_critical_bh(&minfo->mpath_tx_queue.lock);\n\n\t\t\t/* schedule mpath_tx_tasklet */\n\t\t\ttasklet_hi_schedule(&minfo->mpath_tx_tasklet);\n\t\t}\n\t}\n}\n\n/**\n * rtw_mesh_path_send_to_gates - sends pending frames to all known mesh gates\n *\n * @mpath: mesh path whose queue will be emptied\n *\n * If there is only one gate, the frames are transferred from the failed mpath\n * queue to that gate's queue.  If there are more than one gates, the frames\n * are copied from each gate to the next.  After frames are copied, the\n * mpath queues are emptied onto the transmission queue.\n */\nint rtw_mesh_path_send_to_gates(struct rtw_mesh_path *mpath)\n{\n\t_adapter *adapter = mpath->adapter;\n\tstruct rtw_mesh_table *tbl;\n\tstruct rtw_mesh_path *from_mpath = mpath;\n\tstruct rtw_mesh_path *gate;\n\tbool copy = false;\n\trtw_hlist_node *node;\n\n\ttbl = adapter->mesh_info.mesh_paths;\n\tif (!tbl)\n\t\treturn 0;\n\n\trtw_rcu_read_lock();\n\trtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {\n\t\tif (gate->flags & RTW_MESH_PATH_ACTIVE) {\n\t\t\tRTW_MPATH_DBG(FUNC_ADPT_FMT\" Forwarding to %pM\\n\",\n\t\t\t\tFUNC_ADPT_ARG(adapter), gate->dst);\n\t\t\trtw_mesh_path_move_to_queue(gate, from_mpath, copy);\n\t\t\tfrom_mpath = gate;\n\t\t\tcopy = true;\n\t\t} else {\n\t\t\tRTW_MPATH_DBG(\n\t\t\t\t  FUNC_ADPT_FMT\" Not forwarding to %pM (flags %#x)\\n\",\n\t\t\t\t  FUNC_ADPT_ARG(adapter), gate->dst, gate->flags);\n\t\t}\n\t}\n\n\trtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {\n\t\tRTW_MPATH_DBG(FUNC_ADPT_FMT\" Sending to %pM\\n\",\n\t\t\tFUNC_ADPT_ARG(adapter), gate->dst);\n\t\trtw_mesh_path_tx_pending(gate);\n\t}\n\trtw_rcu_read_unlock();\n\n\treturn (from_mpath == mpath) ? -EHOSTUNREACH : 0;\n}\n\n/**\n * rtw_mesh_path_discard_frame - discard a frame whose path could not be resolved\n *\n * @skb: frame to discard\n * @sdata: network subif the frame was to be sent through\n *\n * Locking: the function must me called within a rcu_read_lock region\n */\nvoid rtw_mesh_path_discard_frame(_adapter *adapter,\n\t\t\t     struct xmit_frame *xframe)\n{\n\trtw_free_xmitframe(&adapter->xmitpriv, xframe);\n\tadapter->mesh_info.mshstats.dropped_frames_no_route++;\n}\n\n/**\n * rtw_mesh_path_flush_pending - free the pending queue of a mesh path\n *\n * @mpath: mesh path whose queue has to be freed\n *\n * Locking: the function must me called within a rcu_read_lock region\n */\nvoid rtw_mesh_path_flush_pending(struct rtw_mesh_path *mpath)\n{\n\tstruct xmit_frame *xframe;\n\t_list *list, *head;\n\t_list tmp;\n\n\t_rtw_init_listhead(&tmp);\n\n\tenter_critical_bh(&mpath->frame_queue.lock);\n\trtw_list_splice_init(&mpath->frame_queue.queue, &tmp);\n\tmpath->frame_queue_len = 0;\n\texit_critical_bh(&mpath->frame_queue.lock);\n\n\thead = &tmp;\n\tlist = get_next(head);\n\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\txframe = LIST_CONTAINOR(list, struct xmit_frame, list);\n\t\tlist = get_next(list);\n\t\trtw_list_delete(&xframe->list);\n\t\trtw_mesh_path_discard_frame(mpath->adapter, xframe);\n\t}\n}\n\n/**\n * rtw_mesh_path_fix_nexthop - force a specific next hop for a mesh path\n *\n * @mpath: the mesh path to modify\n * @next_hop: the next hop to force\n *\n * Locking: this function must be called holding mpath->state_lock\n */\nvoid rtw_mesh_path_fix_nexthop(struct rtw_mesh_path *mpath, struct sta_info *next_hop)\n{\n\tenter_critical_bh(&mpath->state_lock);\n\trtw_mesh_path_assign_nexthop(mpath, next_hop);\n\tmpath->sn = 0xffff;\n\tmpath->metric = 0;\n\tmpath->hop_count = 0;\n\tmpath->exp_time = 0;\n\tmpath->flags = RTW_MESH_PATH_FIXED | RTW_MESH_PATH_SN_VALID;\n\trtw_mesh_path_activate(mpath);\n\texit_critical_bh(&mpath->state_lock);\n\trtw_ewma_err_rate_init(&next_hop->metrics.err_rate);\n\t/* init it at a low value - 0 start is tricky */\n\trtw_ewma_err_rate_add(&next_hop->metrics.err_rate, 1);\n\trtw_mesh_path_tx_pending(mpath);\n}\n\nint rtw_mesh_pathtbl_init(_adapter *adapter)\n{\n\tstruct rtw_mesh_table *tbl_path, *tbl_mpp;\n\tint ret;\n\n\ttbl_path = rtw_mesh_table_alloc();\n\tif (!tbl_path)\n\t\treturn -ENOMEM;\n\n\ttbl_mpp = rtw_mesh_table_alloc();\n\tif (!tbl_mpp) {\n\t\tret = -ENOMEM;\n\t\tgoto free_path;\n\t}\n\n\trtw_rhashtable_init(&tbl_path->rhead, &rtw_mesh_rht_params);\n\trtw_rhashtable_init(&tbl_mpp->rhead, &rtw_mesh_rht_params);\n\n\tadapter->mesh_info.mesh_paths = tbl_path;\n\tadapter->mesh_info.mpp_paths = tbl_mpp;\n\n\treturn 0;\n\nfree_path:\n\trtw_mesh_table_free(tbl_path);\n\treturn ret;\n}\n\nstatic\nvoid rtw_mesh_path_tbl_expire(_adapter *adapter,\n\t\t\t  struct rtw_mesh_table *tbl)\n{\n\tstruct rtw_mesh_path *mpath;\n\trtw_rhashtable_iter iter;\n\tint ret;\n\n\tif (!tbl)\n\t\treturn;\n\n\tret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);\n\tif (ret)\n\t\treturn;\n\n\tret = rtw_rhashtable_walk_start(&iter);\n\tif (ret && ret != -EAGAIN)\n\t\tgoto out;\n\n\twhile ((mpath = rtw_rhashtable_walk_next(&iter))) {\n\t\tif (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)\n\t\t\tcontinue;\n\t\tif (IS_ERR(mpath))\n\t\t\tbreak;\n\t\tif ((!(mpath->flags & RTW_MESH_PATH_RESOLVING)) &&\n\t\t    (!(mpath->flags & RTW_MESH_PATH_FIXED)) &&\n\t\t     rtw_time_after(rtw_get_current_time(), mpath->exp_time + RTW_MESH_PATH_EXPIRE))\n\t\t\t__rtw_mesh_path_del(tbl, mpath);\n\n\t\tif (mpath->is_gate &&  /* need not to deal with non-gate case */\n\t\t    rtw_time_after(rtw_get_current_time(), mpath->gate_timeout)) {\n\t\t\tRTW_MPATH_DBG(FUNC_ADPT_FMT\"mpath [%pM] expired systime is %lu systime is %lu\\n\",\n\t\t\t\t      FUNC_ADPT_ARG(adapter), mpath->dst,\n\t\t\t\t      mpath->gate_timeout, rtw_get_current_time());\n\t\t\tenter_critical_bh(&mpath->state_lock);\n\t\t\tif (mpath->gate_asked) { /* asked gate before */\n\t\t\t\trtw_mesh_gate_del(tbl, mpath);\n\t\t\t\texit_critical_bh(&mpath->state_lock);\n\t\t\t} else {\n\t\t\t\tmpath->gate_asked = true;\n\t\t\t\tmpath->gate_timeout = rtw_get_current_time() + rtw_ms_to_systime(mpath->gate_ann_int);\n\t\t\t\texit_critical_bh(&mpath->state_lock);\n\t\t\t\trtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH);\n\t\t\t\tRTW_MPATH_DBG(FUNC_ADPT_FMT\"mpath [%pM] ask mesh gate existence (is_root=%d)\\n\",\n\t\t\t\t      FUNC_ADPT_ARG(adapter), mpath->dst, mpath->is_root);\n\t\t\t}\n\t\t}\n\t}\n\nout:\n\trtw_rhashtable_walk_stop(&iter);\n\trtw_rhashtable_walk_exit(&iter);\n}\n\nvoid rtw_mesh_path_expire(_adapter *adapter)\n{\n\trtw_mesh_path_tbl_expire(adapter, adapter->mesh_info.mesh_paths);\n\trtw_mesh_path_tbl_expire(adapter, adapter->mesh_info.mpp_paths);\n}\n\nvoid rtw_mesh_pathtbl_unregister(_adapter *adapter)\n{\n\tif (adapter->mesh_info.mesh_paths) {\n\t\trtw_mesh_table_free(adapter->mesh_info.mesh_paths);\n\t\tadapter->mesh_info.mesh_paths = NULL;\n\t}\n\n\tif (adapter->mesh_info.mpp_paths) {\n\t\trtw_mesh_table_free(adapter->mesh_info.mpp_paths);\n\t\tadapter->mesh_info.mpp_paths = NULL;\n\t}\n}\n#endif /* CONFIG_RTW_MESH */\n\n"
  },
  {
    "path": "core/mesh/rtw_mesh_pathtbl.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_MESH_PATHTBL_H_\n#define __RTW_MESH_PATHTBL_H_\n\n#ifndef DBG_RTW_MPATH\n#define DBG_RTW_MPATH 1\n#endif\n#if DBG_RTW_MPATH\n#define RTW_MPATH_DBG(fmt, arg...) RTW_PRINT(fmt, ##arg)\n#else\n#define RTW_MPATH_DBG(fmt, arg...) do {} while (0)\n#endif\n\n/**\n * enum rtw_mesh_path_flags - mesh path flags\n *\n * @RTW_MESH_PATH_ACTIVE: the mesh path can be used for forwarding\n * @RTW_MESH_PATH_RESOLVING: the discovery process is running for this mesh path\n * @RTW_MESH_PATH_SN_VALID: the mesh path contains a valid destination sequence\n *\tnumber\n * @RTW_MESH_PATH_FIXED: the mesh path has been manually set and should not be\n *\tmodified\n * @RTW_MESH_PATH_RESOLVED: the mesh path can has been resolved\n * @RTW_MESH_PATH_REQ_QUEUED: there is an unsent path request for this destination\n *\talready queued up, waiting for the discovery process to start.\n * @RTW_MESH_PATH_DELETED: the mesh path has been deleted and should no longer\n *\tbe used\n * @RTW_MESH_PATH_ROOT_ADD_CHK: root additional check in root mode.\n *\tWith this flag, It will try the last used rann_snd_addr\n * @RTW_MESH_PATH_PEER_AKA: only used toward a peer, only used in active keep\n *\talive mechanism. PREQ's da = path dst\n * @RTW_MESH_PATH_BCAST_PREQ: for re-checking next hop resolve toward root.\n *\tUse it to force path_discover sending broadcast PREQ for root.\n * \n * RTW_MESH_PATH_RESOLVED is used by the mesh path timer to\n * decide when to stop or cancel the mesh path discovery.\n */\nenum rtw_mesh_path_flags {\n\tRTW_MESH_PATH_ACTIVE =\t\tBIT(0),\n\tRTW_MESH_PATH_RESOLVING =\tBIT(1),\n\tRTW_MESH_PATH_SN_VALID =\tBIT(2),\n\tRTW_MESH_PATH_FIXED\t=\tBIT(3),\n\tRTW_MESH_PATH_RESOLVED =\tBIT(4),\n\tRTW_MESH_PATH_REQ_QUEUED =\tBIT(5),\n\tRTW_MESH_PATH_DELETED =\t\tBIT(6),\n\tRTW_MESH_PATH_ROOT_ADD_CHK =\tBIT(7),\n\tRTW_MESH_PATH_PEER_AKA =\tBIT(8),\n\tRTW_MESH_PATH_BCAST_PREQ =\tBIT(9),\t\n};\n\n/**\n * struct rtw_mesh_path - mesh path structure\n *\n * @dst: mesh path destination mac address\n * @mpp: mesh proxy mac address\n * @rhash: rhashtable list pointer\n * @gate_list: list pointer for known gates list\n * @sdata: mesh subif\n * @next_hop: mesh neighbor to which frames for this destination will be\n *\tforwarded\n * @timer: mesh path discovery timer\n * @frame_queue: pending queue for frames sent to this destination while the\n *\tpath is unresolved\n * @rcu: rcu head for freeing mesh path\n * @sn: target sequence number\n * @metric: current metric to this destination\n * @hop_count: hops to destination\n * @exp_time: in jiffies, when the path will expire or when it expired\n * @discovery_timeout: timeout (lapse in jiffies) used for the last discovery\n *\tretry\n * @discovery_retries: number of discovery retries\n * @flags: mesh path flags, as specified on &enum rtw_mesh_path_flags\n * @state_lock: mesh path state lock used to protect changes to the\n * mpath itself.  No need to take this lock when adding or removing\n * an mpath to a hash bucket on a path table.\n * @rann_snd_addr: the RANN sender address\n * @rann_metric: the aggregated path metric towards the root node\n * @last_preq_to_root: Timestamp of last PREQ sent to root\n * @is_root: the destination station of this path is a root node\n * @is_gate: the destination station of this path is a mesh gate\n *\n *\n * The dst address is unique in the mesh path table. Since the mesh_path is\n * protected by RCU, deleting the next_hop STA must remove / substitute the\n * mesh_path structure and wait until that is no longer reachable before\n * destroying the STA completely.\n */\nstruct rtw_mesh_path {\n\tu8 dst[ETH_ALEN];\n\tu8 mpp[ETH_ALEN];\t/* used for MPP or MAP */\n\trtw_rhash_head rhash;\n\trtw_hlist_node gate_list;\n\t_adapter *adapter;\n\tstruct sta_info __rcu *next_hop;\n\t_timer timer;\n\t_queue frame_queue;\n\tu32 frame_queue_len;\n\trtw_rcu_head rcu;\n\tu32 sn;\n\tu32 metric;\n\tu8 hop_count;\n\tsystime exp_time;\n\tsystime discovery_timeout;\n\tsystime gate_timeout;\n\tu32 gate_ann_int;    /* gate announce interval */\n\tu8 discovery_retries;\n\tenum rtw_mesh_path_flags flags;\n\t_lock state_lock;\n\tu8 rann_snd_addr[ETH_ALEN];\n#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK\n\tu8 add_chk_rann_snd_addr[ETH_ALEN];\n#endif\n\tu32 rann_metric;\n\tunsigned long last_preq_to_root;\n\tbool is_root;\n\tbool is_gate;\n\tbool gate_asked;\n};\n\n/**\n * struct rtw_mesh_table\n *\n * @known_gates: list of known mesh gates and their mpaths by the station. The\n * gate's mpath may or may not be resolved and active.\n * @gates_lock: protects updates to known_gates\n * @rhead: the rhashtable containing struct mesh_paths, keyed by dest addr\n * @entries: number of entries in the table\n */\nstruct rtw_mesh_table {\n\trtw_hlist_head known_gates;\n\t_lock gates_lock;\n\trtw_rhashtable rhead;\n\tATOMIC_T entries;\n};\n\n#define RTW_MESH_PATH_EXPIRE (600 * HZ)\n\n/* Maximum number of paths per interface */\n#define RTW_MESH_MAX_MPATHS\t\t1024\n\n/* Number of frames buffered per destination for unresolved destinations */\n#define RTW_MESH_FRAME_QUEUE_LEN\t10\n\nint rtw_mesh_nexthop_lookup(_adapter *adapter,\n\tconst u8 *mda, const u8 *msa, u8 *ra);\nint rtw_mesh_nexthop_resolve(_adapter *adapter,\n\t\t\t struct xmit_frame *xframe);\n\nstruct rtw_mesh_path *rtw_mesh_path_lookup(_adapter *adapter,\n\t\t\t\t   const u8 *dst);\nstruct rtw_mesh_path *rtw_mpp_path_lookup(_adapter *adapter,\n\t\t\t\t  const u8 *dst);\nint rtw_mpp_path_add(_adapter *adapter,\n\t\t const u8 *dst, const u8 *mpp);\nvoid dump_mpp(void *sel, _adapter *adapter);\n\nstruct rtw_mesh_path *\nrtw_mesh_path_lookup_by_idx(_adapter *adapter, int idx);\nvoid dump_mpath(void *sel, _adapter *adapter);\n\nstruct rtw_mesh_path *\nrtw_mpp_path_lookup_by_idx(_adapter *adapter, int idx);\nvoid rtw_mesh_path_fix_nexthop(struct rtw_mesh_path *mpath, struct sta_info *next_hop);\nvoid rtw_mesh_path_expire(_adapter *adapter);\n\nstruct rtw_mesh_path *\nrtw_mesh_path_add(_adapter *adapter, const u8 *dst);\n\nint rtw_mesh_path_add_gate(struct rtw_mesh_path *mpath);\nvoid rtw_mesh_gate_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath);\nbool rtw_mesh_gate_search(struct rtw_mesh_table *tbl, const u8 *addr);\nint rtw_mesh_path_send_to_gates(struct rtw_mesh_path *mpath);\nint rtw_mesh_gate_num(_adapter *adapter);\nbool rtw_mesh_is_primary_gate(_adapter *adapter);\nvoid dump_known_gates(void *sel, _adapter *adapter);\n\nvoid rtw_mesh_plink_broken(struct sta_info *sta);\n\nvoid rtw_mesh_path_assign_nexthop(struct rtw_mesh_path *mpath, struct sta_info *sta);\nvoid rtw_mesh_path_flush_pending(struct rtw_mesh_path *mpath);\nvoid rtw_mesh_path_tx_pending(struct rtw_mesh_path *mpath);\nint rtw_mesh_pathtbl_init(_adapter *adapter);\nvoid rtw_mesh_pathtbl_unregister(_adapter *adapter);\nint rtw_mesh_path_del(_adapter *adapter, const u8 *addr);\n\nvoid rtw_mesh_path_flush_by_nexthop(struct sta_info *sta);\nvoid rtw_mesh_path_discard_frame(_adapter *adapter,\n\t\t\t     struct xmit_frame *xframe);\n\nstatic inline void rtw_mesh_path_activate(struct rtw_mesh_path *mpath)\n{\n\tmpath->flags |= RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVED;\n}\n\nvoid rtw_mesh_path_flush_by_iface(_adapter *adapter);\n\n#endif /* __RTW_MESH_PATHTBL_H_ */\n\n"
  },
  {
    "path": "core/rtw_ap.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_AP_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\n#ifdef CONFIG_AP_MODE\n\nextern unsigned char\tRTW_WPA_OUI[];\nextern unsigned char\tWMM_OUI[];\nextern unsigned char\tWPS_OUI[];\nextern unsigned char\tP2P_OUI[];\nextern unsigned char\tWFD_OUI[];\n\nvoid init_mlme_ap_info(_adapter *padapter)\n{\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\t_rtw_spinlock_init(&pmlmepriv->bcn_update_lock);\n\t/* pmlmeext->bstart_bss = _FALSE; */\n}\n\nvoid free_mlme_ap_info(_adapter *padapter)\n{\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\tstop_ap_mode(padapter);\n\t_rtw_spinlock_free(&pmlmepriv->bcn_update_lock);\n\n}\n\n/*\n* Set TIM IE\n* return length of total TIM IE\n*/\nu8 rtw_set_tim_ie(u8 dtim_cnt, u8 dtim_period\n\t, const u8 *tim_bmp, u8 tim_bmp_len, u8 *tim_ie)\n{\n\tu8 *p = tim_ie;\n\tu8 i, n1, n2;\n\tu8 bmp_len;\n\n\tif (rtw_bmp_not_empty(tim_bmp, tim_bmp_len)) {\n\t\t/* find the first nonzero octet in tim_bitmap */\n\t\tfor (i = 0; i < tim_bmp_len; i++)\n\t\t\tif (tim_bmp[i])\n\t\t\t\tbreak;\n\t\tn1 = i & 0xFE;\n\t\n\t\t/* find the last nonzero octet in tim_bitmap, except octet 0 */\n\t\tfor (i = tim_bmp_len - 1; i > 0; i--)\n\t\t\tif (tim_bmp[i])\n\t\t\t\tbreak;\n\t\tn2 = i;\n\t\tbmp_len = n2 - n1 + 1;\n\t} else {\n\t\tn1 = n2 = 0;\n\t\tbmp_len = 1;\n\t}\n\n\t*p++ = WLAN_EID_TIM;\n\t*p++ = 2 + 1 + bmp_len;\n\t*p++ = dtim_cnt;\n\t*p++ = dtim_period;\n\t*p++ = (rtw_bmp_is_set(tim_bmp, tim_bmp_len, 0) ? BIT0 : 0) | n1;\n\t_rtw_memcpy(p, tim_bmp + n1, bmp_len);\n\n#if 0\n\tRTW_INFO(\"n1:%u, n2:%u, bmp_offset:%u, bmp_len:%u\\n\", n1, n2, n1 / 2, bmp_len);\n\tRTW_INFO_DUMP(\"tim_ie: \", tim_ie + 2, 2 + 1 + bmp_len);\n#endif\n\treturn 2 + 2 + 1 + bmp_len;\n}\n\nstatic void update_BCNTIM(_adapter *padapter)\n{\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network);\n\tunsigned char *pie = pnetwork_mlmeext->IEs;\n\n#if 0\n\n\n\t/* update TIM IE */\n\t/* if(rtw_tim_map_anyone_be_set(padapter, pstapriv->tim_bitmap)) */\n#endif\n\tif (_TRUE) {\n\t\tu8 *p, *dst_ie, *premainder_ie = NULL, *pbackup_remainder_ie = NULL;\n\t\tuint offset, tmp_len, tim_ielen, tim_ie_offset, remainder_ielen;\n\n\t\tp = rtw_get_ie(pie + _FIXED_IE_LENGTH_, _TIM_IE_, &tim_ielen, pnetwork_mlmeext->IELength - _FIXED_IE_LENGTH_);\n\t\tif (p != NULL && tim_ielen > 0) {\n\t\t\ttim_ielen += 2;\n\n\t\t\tpremainder_ie = p + tim_ielen;\n\n\t\t\ttim_ie_offset = (sint)(p - pie);\n\n\t\t\tremainder_ielen = pnetwork_mlmeext->IELength - tim_ie_offset - tim_ielen;\n\n\t\t\t/*append TIM IE from dst_ie offset*/\n\t\t\tdst_ie = p;\n\t\t} else {\n\t\t\ttim_ielen = 0;\n\n\t\t\t/*calculate head_len*/\n\t\t\toffset = _FIXED_IE_LENGTH_;\n\n\t\t\t/* get ssid_ie len */\n\t\t\tp = rtw_get_ie(pie + _BEACON_IE_OFFSET_, _SSID_IE_, &tmp_len, (pnetwork_mlmeext->IELength - _BEACON_IE_OFFSET_));\n\t\t\tif (p != NULL)\n\t\t\t\toffset += tmp_len + 2;\n\n\t\t\t/*get supported rates len*/\n\t\t\tp = rtw_get_ie(pie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &tmp_len, (pnetwork_mlmeext->IELength - _BEACON_IE_OFFSET_));\n\t\t\tif (p !=  NULL)\n\t\t\t\toffset += tmp_len + 2;\n\n\t\t\t/*DS Parameter Set IE, len=3*/\n\t\t\toffset += 3;\n\n\t\t\tpremainder_ie = pie + offset;\n\n\t\t\tremainder_ielen = pnetwork_mlmeext->IELength - offset - tim_ielen;\n\n\t\t\t/*append TIM IE from offset*/\n\t\t\tdst_ie = pie + offset;\n\n\t\t}\n\n\t\tif (remainder_ielen > 0) {\n\t\t\tpbackup_remainder_ie = rtw_malloc(remainder_ielen);\n\t\t\tif (pbackup_remainder_ie && premainder_ie)\n\t\t\t\t_rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);\n\t\t}\n\n\t\t/* append TIM IE */\n\t\tdst_ie += rtw_set_tim_ie(0, 1, pstapriv->tim_bitmap, pstapriv->aid_bmp_len, dst_ie);\n\n\t\t/*copy remainder IE*/\n\t\tif (pbackup_remainder_ie) {\n\t\t\t_rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen);\n\n\t\t\trtw_mfree(pbackup_remainder_ie, remainder_ielen);\n\t\t}\n\n\t\toffset = (uint)(dst_ie - pie);\n\t\tpnetwork_mlmeext->IELength = offset + remainder_ielen;\n\n\t}\n}\n\nvoid rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len)\n{\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\tu8\tbmatch = _FALSE;\n\tu8\t*pie = pnetwork->IEs;\n\tu8\t*p = NULL, *dst_ie = NULL, *premainder_ie = NULL, *pbackup_remainder_ie = NULL;\n\tu32\ti, offset, ielen, ie_offset, remainder_ielen = 0;\n\n\tfor (i = sizeof(NDIS_802_11_FIXED_IEs); i < pnetwork->IELength;) {\n\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i);\n\n\t\tif (pIE->ElementID > index)\n\t\t\tbreak;\n\t\telse if (pIE->ElementID == index) { /* already exist the same IE */\n\t\t\tp = (u8 *)pIE;\n\t\t\tielen = pIE->Length;\n\t\t\tbmatch = _TRUE;\n\t\t\tbreak;\n\t\t}\n\n\t\tp = (u8 *)pIE;\n\t\tielen = pIE->Length;\n\t\ti += (pIE->Length + 2);\n\t}\n\n\tif (p != NULL && ielen > 0) {\n\t\tielen += 2;\n\n\t\tpremainder_ie = p + ielen;\n\n\t\tie_offset = (sint)(p - pie);\n\n\t\tremainder_ielen = pnetwork->IELength - ie_offset - ielen;\n\n\t\tif (bmatch)\n\t\t\tdst_ie = p;\n\t\telse\n\t\t\tdst_ie = (p + ielen);\n\t}\n\n\tif (dst_ie == NULL)\n\t\treturn;\n\n\tif (remainder_ielen > 0) {\n\t\tpbackup_remainder_ie = rtw_malloc(remainder_ielen);\n\t\tif (pbackup_remainder_ie && premainder_ie)\n\t\t\t_rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);\n\t}\n\n\t*dst_ie++ = index;\n\t*dst_ie++ = len;\n\n\t_rtw_memcpy(dst_ie, data, len);\n\tdst_ie += len;\n\n\t/* copy remainder IE */\n\tif (pbackup_remainder_ie) {\n\t\t_rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen);\n\n\t\trtw_mfree(pbackup_remainder_ie, remainder_ielen);\n\t}\n\n\toffset = (uint)(dst_ie - pie);\n\tpnetwork->IELength = offset + remainder_ielen;\n}\n\nvoid rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index)\n{\n\tu8 *p, *dst_ie = NULL, *premainder_ie = NULL, *pbackup_remainder_ie = NULL;\n\tuint offset, ielen, ie_offset, remainder_ielen = 0;\n\tu8\t*pie = pnetwork->IEs;\n\n\tp = rtw_get_ie(pie + _FIXED_IE_LENGTH_, index, &ielen, pnetwork->IELength - _FIXED_IE_LENGTH_);\n\tif (p != NULL && ielen > 0) {\n\t\tielen += 2;\n\n\t\tpremainder_ie = p + ielen;\n\n\t\tie_offset = (sint)(p - pie);\n\n\t\tremainder_ielen = pnetwork->IELength - ie_offset - ielen;\n\n\t\tdst_ie = p;\n\t} else\n\t\treturn;\n\n\tif (remainder_ielen > 0) {\n\t\tpbackup_remainder_ie = rtw_malloc(remainder_ielen);\n\t\tif (pbackup_remainder_ie && premainder_ie)\n\t\t\t_rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);\n\t}\n\n\t/* copy remainder IE */\n\tif (pbackup_remainder_ie) {\n\t\t_rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen);\n\n\t\trtw_mfree(pbackup_remainder_ie, remainder_ielen);\n\t}\n\n\toffset = (uint)(dst_ie - pie);\n\tpnetwork->IELength = offset + remainder_ielen;\n}\n\n\nu8 chk_sta_is_alive(struct sta_info *psta);\nu8 chk_sta_is_alive(struct sta_info *psta)\n{\n\tu8 ret = _FALSE;\n#ifdef DBG_EXPIRATION_CHK\n\tRTW_INFO(\"sta:\"MAC_FMT\", rssi:%d, rx:\"STA_PKTS_FMT\", expire_to:%u, %s%ssq_len:%u\\n\"\n\t\t , MAC_ARG(psta->cmn.mac_addr)\n\t\t , psta->cmn.rssi_stat.rssi\n\t\t /* , STA_RX_PKTS_ARG(psta) */\n\t\t , STA_RX_PKTS_DIFF_ARG(psta)\n\t\t , psta->expire_to\n\t\t , psta->state & WIFI_SLEEP_STATE ? \"PS, \" : \"\"\n\t\t , psta->state & WIFI_STA_ALIVE_CHK_STATE ? \"SAC, \" : \"\"\n\t\t , psta->sleepq_len\n\t\t);\n#endif\n\n\t/* if(sta_last_rx_pkts(psta) == sta_rx_pkts(psta)) */\n\tif ((psta->sta_stats.last_rx_data_pkts + psta->sta_stats.last_rx_ctrl_pkts) == (psta->sta_stats.rx_data_pkts + psta->sta_stats.rx_ctrl_pkts)) {\n#if 0\n\t\tif (psta->state & WIFI_SLEEP_STATE)\n\t\t\tret = _TRUE;\n#endif\n\t} else\n\t\tret = _TRUE;\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(psta->padapter)) {\n\t\tu8 bcn_alive, hwmp_alive;\n\n\t\thwmp_alive = (psta->sta_stats.rx_hwmp_pkts !=\n\t\t\t      psta->sta_stats.last_rx_hwmp_pkts);\n\t\tbcn_alive = (psta->sta_stats.rx_beacon_pkts != \n\t\t\t     psta->sta_stats.last_rx_beacon_pkts);\n\t\t/* The reference for nexthop_lookup */\n\t\tpsta->alive = ret || hwmp_alive || bcn_alive;\n\t\t/* The reference for expire_timeout_chk */\n\t\t/* Exclude bcn_alive to avoid a misjudge condition\n\t\t   that a peer unexpectedly leave and restart quickly*/\n\t\tret = ret || hwmp_alive;\n\t}\n#endif\n\n\tsta_update_last_rx_pkts(psta);\n\n\treturn ret;\n}\n\n/**\n * issue_aka_chk_frame - issue active keep alive check frame\n *\taka = active keep alive\n */\n#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK\nstatic int issue_aka_chk_frame(_adapter *adapter, struct sta_info *psta)\n{\n\tint ret = _FAIL;\n\tu8 *target_addr = psta->cmn.mac_addr;\n\n\tif (MLME_IS_AP(adapter)) {\n\t\t/* issue null data to check sta alive */\n\t\tif (psta->state & WIFI_SLEEP_STATE)\n\t\t\tret = issue_nulldata(adapter, target_addr, 0, 1, 50);\n\t\telse\n\t\t\tret = issue_nulldata(adapter, target_addr, 0, 3, 50);\n\t}\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(adapter)) {\n\t\tstruct rtw_mesh_path *mpath;\n\n\t\trtw_rcu_read_lock();\n\t\tmpath = rtw_mesh_path_lookup(adapter, target_addr);\n\t\tif (!mpath) {\n\t\t\tmpath = rtw_mesh_path_add(adapter, target_addr);\n\t\t\tif (IS_ERR(mpath)) {\n\t\t\t\trtw_rcu_read_unlock();\n\t\t\t\tRTW_ERR(FUNC_ADPT_FMT\" rtw_mesh_path_add for \"MAC_FMT\" fail.\\n\",\n\t\t\t\t\tFUNC_ADPT_ARG(adapter), MAC_ARG(target_addr));\n\t\t\t\treturn _FAIL;\n\t\t\t}\n\t\t}\n\t\tif (mpath->flags & RTW_MESH_PATH_ACTIVE)\n\t\t\tret = _SUCCESS;\n\t\telse {\n\t\t\tu8 flags = RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_PEER_AKA;\n\t\t\t/* issue PREQ to check peer alive */\n\t\t\trtw_mesh_queue_preq(mpath, flags);\n\t\t\tret = _FALSE;\n\t\t}\n\t\trtw_rcu_read_unlock();\n\t}\n#endif\n\treturn ret;\n}\n#endif\n\n#ifdef RTW_CONFIG_RFREG18_WA\nstatic void rtw_check_restore_rf18(_adapter *padapter)\n{\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(padapter);\n\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n\tu32 reg;\n\tu8 union_ch = 0, union_bw = 0, union_offset = 0, setchbw = _FALSE;\n\t\t\n\treg = rtw_hal_read_rfreg(padapter, 0, 0x18, 0x3FF);\n\tif ((reg & 0xFF) == 0)\n\t\t\tsetchbw = _TRUE;\n\treg = rtw_hal_read_rfreg(padapter, 1, 0x18, 0x3FF);\n\tif ((reg & 0xFF) == 0)\n\t\t\tsetchbw = _TRUE;\n\n\tif (setchbw) {\n\t\tif (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset)) {\n\t\t\tRTW_INFO(\"Hit RF(0x18)=0!! restore original channel setting.\\n\");\n\t\t\tunion_ch =  pmlmeext->cur_channel;\n\t\t\tunion_offset = pmlmeext->cur_ch_offset ;\n\t\t\tunion_bw = pmlmeext->cur_bwmode;\n\t\t} else {\n\t\t\tRTW_INFO(\"Hit RF(0x18)=0!! set ch(%x) offset(%x) bwmode(%x)\\n\", union_ch, union_offset, union_bw);\n\t\t}\n\t\t/*\tInitial the channel_bw setting procedure.\t*/\n\t\tpHalData->current_channel = 0;\n\t\tset_channel_bwmode(padapter, union_ch, union_offset, union_bw);\n\t}\n}\n#endif\n\nvoid\texpire_timeout_chk(_adapter *padapter)\n{\n\t_irqL irqL;\n\t_list\t*phead, *plist;\n\tu8 updated = _FALSE;\n\tstruct sta_info *psta = NULL;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tu8 chk_alive_num = 0;\n\tchar chk_alive_list[NUM_STA];\n\tint i;\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(padapter)\n\t\t&& check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)\n\t) {\n\t\tstruct rtw_mesh_cfg *mcfg = &padapter->mesh_cfg;\n\n\t\trtw_mesh_path_expire(padapter);\n\n\t\t/* TBD: up layer timeout mechanism */\n\t\t/* if (!mcfg->plink_timeout)\n\t\t\treturn; */\n#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK\n\t\treturn;\n#endif\n\t}\n#endif\n\n#ifdef CONFIG_MCC_MODE\n\t/*\tthen driver may check fail due to not recv client's frame under sitesurvey,\n\t *\tdon't expire timeout chk under MCC under sitesurvey */\n\n\tif (rtw_hal_mcc_link_status_chk(padapter, __func__) == _FALSE)\n\t\treturn;\n#endif\n\n\t_enter_critical_bh(&pstapriv->auth_list_lock, &irqL);\n\n\tphead = &pstapriv->auth_list;\n\tplist = get_next(phead);\n\n\t/* check auth_queue */\n#ifdef DBG_EXPIRATION_CHK\n\tif (rtw_end_of_queue_search(phead, plist) == _FALSE) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" auth_list, cnt:%u\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), pstapriv->auth_list_cnt);\n\t}\n#endif\n\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, auth_list);\n\n\t\tplist = get_next(plist);\n\n\n#ifdef CONFIG_ATMEL_RC_PATCH\n\t\tif (_rtw_memcmp((void *)(pstapriv->atmel_rc_pattern), (void *)(psta->cmn.mac_addr), ETH_ALEN) == _TRUE)\n\t\t\tcontinue;\n\t\tif (psta->flag_atmel_rc)\n\t\t\tcontinue;\n#endif\n\t\tif (psta->expire_to > 0) {\n\t\t\tpsta->expire_to--;\n\t\t\tif (psta->expire_to == 0) {\n\t\t\t\trtw_list_delete(&psta->auth_list);\n\t\t\t\tpstapriv->auth_list_cnt--;\n\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" auth expire \"MAC_FMT\"\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));\n\n\t\t\t\t_exit_critical_bh(&pstapriv->auth_list_lock, &irqL);\n\n\t\t\t\t/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\t */\n\t\t\t\trtw_free_stainfo(padapter, psta);\n\t\t\t\t/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\t */\n\n\t\t\t\t_enter_critical_bh(&pstapriv->auth_list_lock, &irqL);\n\t\t\t}\n\t\t}\n\n\t}\n\n\t_exit_critical_bh(&pstapriv->auth_list_lock, &irqL);\n\tpsta = NULL;\n\n\n\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\tphead = &pstapriv->asoc_list;\n\tplist = get_next(phead);\n\n\t/* check asoc_queue */\n#ifdef DBG_EXPIRATION_CHK\n\tif (rtw_end_of_queue_search(phead, plist) == _FALSE) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" asoc_list, cnt:%u\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), pstapriv->asoc_list_cnt);\n\t}\n#endif\n\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);\n\t\tplist = get_next(plist);\n#ifdef CONFIG_ATMEL_RC_PATCH\n\t\tRTW_INFO(\"%s:%d  psta=%p, %02x,%02x||%02x,%02x  \\n\\n\", __func__,  __LINE__,\n\t\t\tpsta, pstapriv->atmel_rc_pattern[0], pstapriv->atmel_rc_pattern[5], psta->cmn.mac_addr[0], psta->cmn.mac_addr[5]);\n\t\tif (_rtw_memcmp((void *)pstapriv->atmel_rc_pattern, (void *)(psta->cmn.mac_addr), ETH_ALEN) == _TRUE)\n\t\t\tcontinue;\n\t\tif (psta->flag_atmel_rc)\n\t\t\tcontinue;\n\t\tRTW_INFO(\"%s: debug line:%d\\n\", __func__, __LINE__);\n#endif\n#ifdef CONFIG_AUTO_AP_MODE\n\t\tif (psta->isrc)\n\t\t\tcontinue;\n#endif\n\t\tif (chk_sta_is_alive(psta) || !psta->expire_to) {\n\t\t\tpsta->expire_to = pstapriv->expire_to;\n\t\t\tpsta->keep_alive_trycnt = 0;\n#ifdef CONFIG_TX_MCAST2UNI\n\t\t\tpsta->under_exist_checking = 0;\n#endif\t/* CONFIG_TX_MCAST2UNI */\n\t\t} else\n\t\t\tpsta->expire_to--;\n\n#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK\n#ifdef CONFIG_80211N_HT\n#ifdef CONFIG_TX_MCAST2UNI\n\t\tif ((psta->flags & WLAN_STA_HT) && (psta->htpriv.agg_enable_bitmap || psta->under_exist_checking)) {\n\t\t\t/* check sta by delba(addba) for 11n STA */\n\t\t\t/* ToDo: use CCX report to check for all STAs */\n\t\t\t/* RTW_INFO(\"asoc check by DELBA/ADDBA! (pstapriv->expire_to=%d s)(psta->expire_to=%d s), [%02x, %d]\\n\", pstapriv->expire_to*2, psta->expire_to*2, psta->htpriv.agg_enable_bitmap, psta->under_exist_checking); */\n\n\t\t\tif (psta->expire_to <= (pstapriv->expire_to - 50)) {\n\t\t\t\tRTW_INFO(\"asoc expire by DELBA/ADDBA! (%d s)\\n\", (pstapriv->expire_to - psta->expire_to) * 2);\n\t\t\t\tpsta->under_exist_checking = 0;\n\t\t\t\tpsta->expire_to = 0;\n\t\t\t} else if (psta->expire_to <= (pstapriv->expire_to - 3) && (psta->under_exist_checking == 0)) {\n\t\t\t\tRTW_INFO(\"asoc check by DELBA/ADDBA! (%d s)\\n\", (pstapriv->expire_to - psta->expire_to) * 2);\n\t\t\t\tpsta->under_exist_checking = 1;\n\t\t\t\t/* tear down TX AMPDU */\n\t\t\t\tsend_delba(padapter, 1, psta->cmn.mac_addr);/*  */ /* originator */\n\t\t\t\tpsta->htpriv.agg_enable_bitmap = 0x0;/* reset */\n\t\t\t\tpsta->htpriv.candidate_tid_bitmap = 0x0;/* reset */\n\t\t\t}\n\t\t}\n#endif /* CONFIG_TX_MCAST2UNI */\n#endif /* CONFIG_80211N_HT */\n#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */\n\n\t\tif (psta->expire_to <= 0) {\n\t\t\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\n\t\t\tif (padapter->registrypriv.wifi_spec == 1) {\n\t\t\t\tpsta->expire_to = pstapriv->expire_to;\n\t\t\t\tcontinue;\n\t\t\t}\n\n#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK\n#ifdef CONFIG_80211N_HT\n\n#define KEEP_ALIVE_TRYCNT (3)\n\n\t\t\tif (psta->keep_alive_trycnt > 0 && psta->keep_alive_trycnt <= KEEP_ALIVE_TRYCNT) {\n\t\t\t\tif (psta->state & WIFI_STA_ALIVE_CHK_STATE)\n\t\t\t\t\tpsta->state ^= WIFI_STA_ALIVE_CHK_STATE;\n\t\t\t\telse\n\t\t\t\t\tpsta->keep_alive_trycnt = 0;\n\n\t\t\t} else if ((psta->keep_alive_trycnt > KEEP_ALIVE_TRYCNT) && !(psta->state & WIFI_STA_ALIVE_CHK_STATE))\n\t\t\t\tpsta->keep_alive_trycnt = 0;\n\t\t\tif ((psta->htpriv.ht_option == _TRUE) && (psta->htpriv.ampdu_enable == _TRUE)) {\n\t\t\t\tuint priority = 1; /* test using BK */\n\t\t\t\tu8 issued = 0;\n\n\t\t\t\t/* issued = (psta->htpriv.agg_enable_bitmap>>priority)&0x1; */\n\t\t\t\tissued |= (psta->htpriv.candidate_tid_bitmap >> priority) & 0x1;\n\n\t\t\t\tif (0 == issued) {\n\t\t\t\t\tif (!(psta->state & WIFI_STA_ALIVE_CHK_STATE)) {\n\t\t\t\t\t\tpsta->htpriv.candidate_tid_bitmap |= BIT((u8)priority);\n\n\t\t\t\t\t\tif (psta->state & WIFI_SLEEP_STATE)\n\t\t\t\t\t\t\tpsta->expire_to = 2; /* 2x2=4 sec */\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tpsta->expire_to = 1; /* 2 sec */\n\n\t\t\t\t\t\tpsta->state |= WIFI_STA_ALIVE_CHK_STATE;\n\n\t\t\t\t\t\t/* add_ba_hdl(padapter, (u8*)paddbareq_parm); */\n\n\t\t\t\t\t\tRTW_INFO(\"issue addba_req to check if sta alive, keep_alive_trycnt=%d\\n\", psta->keep_alive_trycnt);\n\n\t\t\t\t\t\tissue_addba_req(padapter, psta->cmn.mac_addr, (u8)priority);\n\n\t\t\t\t\t\t_set_timer(&psta->addba_retry_timer, ADDBA_TO);\n\n\t\t\t\t\t\tpsta->keep_alive_trycnt++;\n\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (psta->keep_alive_trycnt > 0 && psta->state & WIFI_STA_ALIVE_CHK_STATE) {\n\t\t\t\tpsta->keep_alive_trycnt = 0;\n\t\t\t\tpsta->state ^= WIFI_STA_ALIVE_CHK_STATE;\n\t\t\t\tRTW_INFO(\"change to another methods to check alive if staion is at ps mode\\n\");\n\t\t\t}\n\n#endif /* CONFIG_80211N_HT */\n#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK\t */\n\t\t\tif (psta->state & WIFI_SLEEP_STATE) {\n\t\t\t\tif (!(psta->state & WIFI_STA_ALIVE_CHK_STATE)) {\n\t\t\t\t\t/* to check if alive by another methods if staion is at ps mode.\t\t\t\t\t */\n\t\t\t\t\tpsta->expire_to = pstapriv->expire_to;\n\t\t\t\t\tpsta->state |= WIFI_STA_ALIVE_CHK_STATE;\n\n\t\t\t\t\t/* RTW_INFO(\"alive chk, sta:\" MAC_FMT \" is at ps mode!\\n\", MAC_ARG(psta->cmn.mac_addr)); */\n\n\t\t\t\t\t/* to update bcn with tim_bitmap for this station */\n\t\t\t\t\trtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid);\n\t\t\t\t\tupdate_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0);\n\n\t\t\t\t\tif (!pmlmeext->active_keep_alive_check)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t{\n\t\t\t\tint stainfo_offset;\n\n\t\t\t\tstainfo_offset = rtw_stainfo_offset(pstapriv, psta);\n\t\t\t\tif (stainfo_offset_valid(stainfo_offset))\n\t\t\t\t\tchk_alive_list[chk_alive_num++] = stainfo_offset;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t} else {\n\t\t\t/* TODO: Aging mechanism to digest frames in sleep_q to avoid running out of xmitframe */\n\t\t\tif (psta->sleepq_len > (NR_XMITFRAME / pstapriv->asoc_list_cnt)\n\t\t\t    && padapter->xmitpriv.free_xmitframe_cnt < ((NR_XMITFRAME / pstapriv->asoc_list_cnt) / 2)\n\t\t\t   ) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" sta:\"MAC_FMT\", sleepq_len:%u, free_xmitframe_cnt:%u, asoc_list_cnt:%u, clear sleep_q\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)\n\t\t\t\t\t, psta->sleepq_len, padapter->xmitpriv.free_xmitframe_cnt, pstapriv->asoc_list_cnt);\n\t\t\t\twakeup_sta_to_xmit(padapter, psta);\n\t\t\t}\n\t\t}\n\t}\n\n\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\tif (chk_alive_num) {\n#if defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK)\n\t\tu8 backup_ch = 0, backup_bw = 0, backup_offset = 0;\n\t\tu8 union_ch = 0, union_bw = 0, union_offset = 0;\n\t\tu8 switch_channel_by_drv = _TRUE;\n\t\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n#endif\n\t\tchar del_asoc_list[NUM_STA];\n\n\t\t_rtw_memset(del_asoc_list, NUM_STA, NUM_STA);\n\n\t\t#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK\n\t\tif (pmlmeext->active_keep_alive_check) {\n\t\t\t#ifdef CONFIG_MCC_MODE\n\t\t\tif (MCC_EN(padapter)) {\n\t\t\t\t/* driver doesn't switch channel under MCC */\n\t\t\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))\n\t\t\t\t\tswitch_channel_by_drv = _FALSE;\n\t\t\t}\n\t\t\t#endif\n\n\t\t\tif (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset)\n\t\t\t\t|| pmlmeext->cur_channel != union_ch)\n\t\t\t\tswitch_channel_by_drv = _FALSE;\n\n\t\t\t/* switch to correct channel of current network  before issue keep-alive frames */\n\t\t\tif (switch_channel_by_drv == _TRUE && rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) {\n\t\t\t\tbackup_ch = rtw_get_oper_ch(padapter);\n\t\t\t\tbackup_bw = rtw_get_oper_bw(padapter);\n\t\t\t\tbackup_offset = rtw_get_oper_choffset(padapter);\n\t\t\t\tset_channel_bwmode(padapter, union_ch, union_offset, union_bw);\n\t\t\t}\n\t\t}\n\t\t#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */\n\n\t\t/* check loop */\n\t\tfor (i = 0; i < chk_alive_num; i++) {\n\t\t\t#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK\n\t\t\tint ret = _FAIL;\n\t\t\t#endif\n\n\t\t\tpsta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]);\n\n\t\t\t#ifdef CONFIG_ATMEL_RC_PATCH\n\t\t\tif (_rtw_memcmp(pstapriv->atmel_rc_pattern, psta->cmn.mac_addr, ETH_ALEN) == _TRUE)\n\t\t\t\tcontinue;\n\t\t\tif (psta->flag_atmel_rc)\n\t\t\t\tcontinue;\n\t\t\t#endif\n\n\t\t\tif (!(psta->state & _FW_LINKED))\n\t\t\t\tcontinue;\n\n\t\t\t#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK\n\t\t\tif (pmlmeext->active_keep_alive_check) {\n\t\t\t\t/* issue active keep alive frame to check */\n\t\t\t\tret = issue_aka_chk_frame(padapter, psta);\n\n\t\t\t\tpsta->keep_alive_trycnt++;\n\t\t\t\tif (ret == _SUCCESS) {\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" asoc check, \"MAC_FMT\" is alive\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));\n\t\t\t\t\tpsta->expire_to = pstapriv->expire_to;\n\t\t\t\t\tpsta->keep_alive_trycnt = 0;\n\t\t\t\t\tcontinue;\n\t\t\t\t} else if (psta->keep_alive_trycnt <= 3) {\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" asoc check, \"MAC_FMT\" keep_alive_trycnt=%d\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter) , MAC_ARG(psta->cmn.mac_addr), psta->keep_alive_trycnt);\n\t\t\t\t\tpsta->expire_to = 1;\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t}\n\t\t\t#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */\n\n\t\t\tpsta->keep_alive_trycnt = 0;\n\t\t\tdel_asoc_list[i] = chk_alive_list[i];\n\t\t\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\t\t\tif (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {\n\t\t\t\trtw_list_delete(&psta->asoc_list);\n\t\t\t\tpstapriv->asoc_list_cnt--;\n\t\t\t\tSTA_SET_MESH_PLINK(psta, NULL);\n\t\t\t}\n\t\t\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\t\t}\n\n\t\t/* delete loop */\n\t\tfor (i = 0; i < chk_alive_num; i++) {\n\t\t\tu8 sta_addr[ETH_ALEN];\n\n\t\t\tif (del_asoc_list[i] >= NUM_STA)\n\t\t\t\tcontinue;\n\n\t\t\tpsta = rtw_get_stainfo_by_offset(pstapriv, del_asoc_list[i]);\n\t\t\t_rtw_memcpy(sta_addr, psta->cmn.mac_addr, ETH_ALEN);\n\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" asoc expire \"MAC_FMT\", state=0x%x\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr), psta->state);\n\t\t\tupdated |= ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _FALSE);\n\t\t\t#ifdef CONFIG_RTW_MESH\n\t\t\tif (MLME_IS_MESH(padapter))\n\t\t\t\trtw_mesh_expire_peer(padapter, sta_addr);\n\t\t\t#endif\n\t\t}\n\n\t\t#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK\n\t\tif (pmlmeext->active_keep_alive_check) {\n\t\t\t/* back to the original operation channel */\n\t\t\tif (switch_channel_by_drv == _TRUE && backup_ch > 0)\n\t\t\t\tset_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw);\n\t\t}\n\t\t#endif\n\t}\n\n#ifdef RTW_CONFIG_RFREG18_WA\n\trtw_check_restore_rf18(padapter);\n#endif\n\tassociated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);\n}\n\nvoid rtw_ap_update_sta_ra_info(_adapter *padapter, struct sta_info *psta)\n{\n\tunsigned char sta_band = 0;\n\tu64 tx_ra_bitmap = 0;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tWLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;\n\n\tif (!psta)\n\t\treturn;\n\n\tif (!(psta->state & _FW_LINKED))\n\t\treturn;\n\n\trtw_hal_update_sta_ra_info(padapter, psta);\n\ttx_ra_bitmap = psta->cmn.ra_info.ramask;\n\n\tif (pcur_network->Configuration.DSConfig > 14) {\n\n\t\tif (tx_ra_bitmap & 0xffff000)\n\t\t\tsta_band |= WIRELESS_11_5N;\n\n\t\tif (tx_ra_bitmap & 0xff0)\n\t\t\tsta_band |= WIRELESS_11A;\n\n\t\t/* 5G band */\n#ifdef CONFIG_80211AC_VHT\n\t\tif (psta->vhtpriv.vht_option)\n\t\t\tsta_band = WIRELESS_11_5AC;\n#endif\n\t} else {\n\t\tif (tx_ra_bitmap & 0xffff000)\n\t\t\tsta_band |= WIRELESS_11_24N;\n\n\t\tif (tx_ra_bitmap & 0xff0)\n\t\t\tsta_band |= WIRELESS_11G;\n\n\t\tif (tx_ra_bitmap & 0x0f)\n\t\t\tsta_band |= WIRELESS_11B;\n\t}\n\n\tpsta->wireless_mode = sta_band;\n\trtw_hal_update_sta_wset(padapter, psta);\n\tRTW_INFO(\"%s=> mac_id:%d , tx_ra_bitmap:0x%016llx, networkType:0x%02x\\n\",\n\t\t\t__FUNCTION__, psta->cmn.mac_id, tx_ra_bitmap, psta->wireless_mode);\n}\n\n#ifdef CONFIG_BMC_TX_RATE_SELECT\nu8 rtw_ap_find_mini_tx_rate(_adapter *adapter)\n{\n\t_irqL irqL;\n\t_list\t*phead, *plist;\n\tu8 miini_tx_rate = ODM_RATEVHTSS4MCS9, sta_tx_rate;\n\tstruct sta_info *psta = NULL;\n\tstruct sta_priv *pstapriv = &adapter->stapriv;\n\n\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\tphead = &pstapriv->asoc_list;\n\tplist = get_next(phead);\n\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);\n\t\tplist = get_next(plist);\n\n\t\tsta_tx_rate = psta->cmn.ra_info.curr_tx_rate & 0x7F;\n\t\tif (sta_tx_rate < miini_tx_rate)\n\t\t\tmiini_tx_rate = sta_tx_rate;\n\t}\n\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\treturn miini_tx_rate;\n}\n\nu8 rtw_ap_find_bmc_rate(_adapter *adapter, u8 tx_rate)\n{\n\tPHAL_DATA_TYPE\thal_data = GET_HAL_DATA(adapter);\n\tu8 tx_ini_rate = ODM_RATE6M;\n\n\tswitch (tx_rate) {\n\tcase ODM_RATEVHTSS3MCS9:\n\tcase ODM_RATEVHTSS3MCS8:\n\tcase ODM_RATEVHTSS3MCS7:\n\tcase ODM_RATEVHTSS3MCS6:\n\tcase ODM_RATEVHTSS3MCS5:\n\tcase ODM_RATEVHTSS3MCS4:\n\tcase ODM_RATEVHTSS3MCS3:\n\tcase ODM_RATEVHTSS2MCS9:\n\tcase ODM_RATEVHTSS2MCS8:\n\tcase ODM_RATEVHTSS2MCS7:\n\tcase ODM_RATEVHTSS2MCS6:\n\tcase ODM_RATEVHTSS2MCS5:\n\tcase ODM_RATEVHTSS2MCS4:\n\tcase ODM_RATEVHTSS2MCS3:\n\tcase ODM_RATEVHTSS1MCS9:\n\tcase ODM_RATEVHTSS1MCS8:\n\tcase ODM_RATEVHTSS1MCS7:\n\tcase ODM_RATEVHTSS1MCS6:\n\tcase ODM_RATEVHTSS1MCS5:\n\tcase ODM_RATEVHTSS1MCS4:\n\tcase ODM_RATEVHTSS1MCS3:\n\tcase ODM_RATEMCS15:\n\tcase ODM_RATEMCS14:\n\tcase ODM_RATEMCS13:\n\tcase ODM_RATEMCS12:\n\tcase ODM_RATEMCS11:\n\tcase ODM_RATEMCS7:\n\tcase ODM_RATEMCS6:\n\tcase ODM_RATEMCS5:\n\tcase ODM_RATEMCS4:\n\tcase ODM_RATEMCS3:\n\tcase ODM_RATE54M:\n\tcase ODM_RATE48M:\n\tcase ODM_RATE36M:\n\tcase ODM_RATE24M:\n\t\ttx_ini_rate = ODM_RATE24M;\n\t\tbreak;\n\tcase ODM_RATEVHTSS3MCS2:\n\tcase ODM_RATEVHTSS3MCS1:\n\tcase ODM_RATEVHTSS2MCS2:\n\tcase ODM_RATEVHTSS2MCS1:\n\tcase ODM_RATEVHTSS1MCS2:\n\tcase ODM_RATEVHTSS1MCS1:\n\tcase ODM_RATEMCS10:\n\tcase ODM_RATEMCS9:\n\tcase ODM_RATEMCS2:\n\tcase ODM_RATEMCS1:\n\tcase ODM_RATE18M:\n\tcase ODM_RATE12M:\n\t\ttx_ini_rate = ODM_RATE12M;\n\t\tbreak;\n\tcase ODM_RATEVHTSS3MCS0:\n\tcase ODM_RATEVHTSS2MCS0:\n\tcase ODM_RATEVHTSS1MCS0:\n\tcase ODM_RATEMCS8:\n\tcase ODM_RATEMCS0:\n\tcase ODM_RATE9M:\n\tcase ODM_RATE6M:\n\t\ttx_ini_rate = ODM_RATE6M;\n\t\tbreak;\n\tcase ODM_RATE11M:\n\tcase ODM_RATE5_5M:\n\tcase ODM_RATE2M:\n\tcase ODM_RATE1M:\n\t\ttx_ini_rate = ODM_RATE1M;\n\t\tbreak;\n\tdefault:\n\t\ttx_ini_rate = ODM_RATE6M;\n\t\tbreak;\n\t}\n\n\tif (hal_data->current_band_type == BAND_ON_5G)\n\t\tif (tx_ini_rate < ODM_RATE6M)\n\t\t\ttx_ini_rate = ODM_RATE6M;\n\n\treturn tx_ini_rate;\n}\n\nvoid rtw_update_bmc_sta_tx_rate(_adapter *adapter)\n{\n\tstruct sta_info *psta = NULL;\n\tu8 tx_rate;\n\n\tpsta = rtw_get_bcmc_stainfo(adapter);\n\tif (psta == NULL) {\n\t\tRTW_ERR(ADPT_FMT \"could not get bmc_sta !!\\n\", ADPT_ARG(adapter));\n\t\treturn;\n\t}\n\n\tif (adapter->bmc_tx_rate != MGN_UNKNOWN) {\n\t\tpsta->init_rate = adapter->bmc_tx_rate;\n\t\tgoto _exit;\n\t}\n\n\tif (adapter->stapriv.asoc_sta_count <= 2)\n\t\tgoto _exit;\n\n\ttx_rate = rtw_ap_find_mini_tx_rate(adapter);\n\t#ifdef CONFIG_BMC_TX_LOW_RATE\n\ttx_rate = rtw_ap_find_bmc_rate(adapter, tx_rate);\n\t#endif\n\n\tpsta->init_rate = hw_rate_to_m_rate(tx_rate);\n\n_exit:\n\tRTW_INFO(ADPT_FMT\" BMC Tx rate - %s\\n\", ADPT_ARG(adapter), MGN_RATE_STR(psta->init_rate));\n}\n#endif\n\nvoid rtw_init_bmc_sta_tx_rate(_adapter *padapter, struct sta_info *psta)\n{\n#ifdef CONFIG_BMC_TX_LOW_RATE\n\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n#endif\n\tu8 rate_idx = 0;\n\tu8 brate_table[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M,\n\t\tMGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M};\n\n\tif (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))\n\t\treturn;\n\n\tif (padapter->bmc_tx_rate != MGN_UNKNOWN)\n\t\tpsta->init_rate = padapter->bmc_tx_rate;\n\telse {\n\t\t#ifdef CONFIG_BMC_TX_LOW_RATE\n\t\tif (IsEnableHWOFDM(pmlmeext->cur_wireless_mode) && (psta->cmn.ra_info.ramask && 0xFF0))\n\t\t\trate_idx = get_lowest_rate_idx_ex(psta->cmn.ra_info.ramask, 4); /*from basic rate*/\n\t\telse\n\t\t\trate_idx = get_lowest_rate_idx(psta->cmn.ra_info.ramask); /*from basic rate*/\n\t\t#else\n\t\trate_idx = get_highest_rate_idx(psta->cmn.ra_info.ramask); /*from basic rate*/\n\t\t#endif\n\t\tif (rate_idx < 12)\n\t\t\tpsta->init_rate = brate_table[rate_idx];\n\t\telse\n\t\t\tpsta->init_rate = MGN_1M;\n\t}\n\n\tRTW_INFO(ADPT_FMT\" BMC Init Tx rate - %s\\n\", ADPT_ARG(padapter), MGN_RATE_STR(psta->init_rate));\n}\n\nvoid update_bmc_sta(_adapter *padapter)\n{\n\t_irqL\tirqL;\n\tunsigned char\tnetwork_type;\n\tint supportRateNum = 0;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tWLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;\n\tstruct sta_info *psta = rtw_get_bcmc_stainfo(padapter);\n\n\tif (psta) {\n\t\tpsta->cmn.aid = 0;/* default set to 0 */\n#ifdef CONFIG_RTW_MESH\n\t\tif (MLME_IS_MESH(padapter))\n\t\t\tpsta->qos_option = 1;\n\t\telse\n#endif\n\t\t\tpsta->qos_option = 0;\n#ifdef CONFIG_80211N_HT\n\t\tpsta->htpriv.ht_option = _FALSE;\n#endif /* CONFIG_80211N_HT */\n\n\t\tpsta->ieee8021x_blocked = 0;\n\n\t\t_rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats));\n\n\t\t/* psta->dot118021XPrivacy = _NO_PRIVACY_; */ /* !!! remove it, because it has been set before this. */\n\n\t\tsupportRateNum = rtw_get_rateset_len((u8 *)&pcur_network->SupportedRates);\n\t\tnetwork_type = rtw_check_network_type((u8 *)&pcur_network->SupportedRates, supportRateNum, pcur_network->Configuration.DSConfig);\n\t\tif (IsSupportedTxCCK(network_type))\n\t\t\tnetwork_type = WIRELESS_11B;\n\t\telse if (network_type == WIRELESS_INVALID) { /* error handling */\n\t\t\tif (pcur_network->Configuration.DSConfig > 14)\n\t\t\t\tnetwork_type = WIRELESS_11A;\n\t\t\telse\n\t\t\t\tnetwork_type = WIRELESS_11B;\n\t\t}\n\t\tupdate_sta_basic_rate(psta, network_type);\n\t\tpsta->wireless_mode = network_type;\n\n\t\trtw_hal_update_sta_ra_info(padapter, psta);\n\n\t\t_enter_critical_bh(&psta->lock, &irqL);\n\t\tpsta->state = _FW_LINKED;\n\t\t_exit_critical_bh(&psta->lock, &irqL);\n\n\t\trtw_sta_media_status_rpt(padapter, psta, 1);\n\t\trtw_init_bmc_sta_tx_rate(padapter, psta);\n\n\t} else\n\t\tRTW_INFO(\"add_RATid_bmc_sta error!\\n\");\n\n}\n\n#if defined(CONFIG_80211N_HT) && defined(CONFIG_BEAMFORMING)\nvoid update_sta_info_apmode_ht_bf_cap(_adapter *padapter, struct sta_info *psta)\n{\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct ht_priv\t*phtpriv_ap = &pmlmepriv->htpriv;\n\tstruct ht_priv\t*phtpriv_sta = &psta->htpriv;\n\n\tu8 cur_beamform_cap = 0;\n\n\t/*Config Tx beamforming setting*/\n\tif (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&\n\t\tGET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP((u8 *)(&phtpriv_sta->ht_cap))) {\n\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);\n\t\t/*Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/\n\t\tSET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 6);\n\t}\n\n\tif (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&\n\t\tGET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP((u8 *)(&phtpriv_sta->ht_cap))) {\n\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);\n\t\t/*Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/\n\t\tSET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 4);\n\t}\n\tif (cur_beamform_cap)\n\t\tRTW_INFO(\"Client STA(%d) HT Beamforming Cap = 0x%02X\\n\", psta->cmn.aid, cur_beamform_cap);\n\n\tphtpriv_sta->beamform_cap = cur_beamform_cap;\n\tpsta->cmn.bf_info.ht_beamform_cap = cur_beamform_cap;\n\n}\n#endif /*CONFIG_80211N_HT && CONFIG_BEAMFORMING*/\n\n/* notes:\n * AID: 1~MAX for sta and 0 for bc/mc in ap/adhoc mode  */\nvoid update_sta_info_apmode(_adapter *padapter, struct sta_info *psta)\n{\n\t_irqL\tirqL;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n#ifdef CONFIG_80211N_HT\n\tstruct ht_priv\t*phtpriv_ap = &pmlmepriv->htpriv;\n\tstruct ht_priv\t*phtpriv_sta = &psta->htpriv;\n#endif /* CONFIG_80211N_HT */\n\tu8\tcur_ldpc_cap = 0, cur_stbc_cap = 0;\n\t/* set intf_tag to if1 */\n\t/* psta->intf_tag = 0; */\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\t/*alloc macid when call rtw_alloc_stainfo(),release macid when call rtw_free_stainfo()*/\n\n\tif (!MLME_IS_MESH(padapter) && psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)\n\t\tpsta->ieee8021x_blocked = _TRUE;\n\telse\n\t\tpsta->ieee8021x_blocked = _FALSE;\n\n\n\t/* update sta's cap */\n\n\t/* ERP */\n\tVCS_update(padapter, psta);\n#ifdef CONFIG_80211N_HT\n\t/* HT related cap */\n\tif (phtpriv_sta->ht_option) {\n\t\t/* check if sta supports rx ampdu */\n\t\tphtpriv_sta->ampdu_enable = phtpriv_ap->ampdu_enable;\n\n\t\tphtpriv_sta->rx_ampdu_min_spacing = (phtpriv_sta->ht_cap.ampdu_params_info & IEEE80211_HT_CAP_AMPDU_DENSITY) >> 2;\n\n\t\t/* bwmode */\n\t\tif ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH))\n\t\t\tpsta->cmn.bw_mode = CHANNEL_WIDTH_40;\n\t\telse\n\t\t\tpsta->cmn.bw_mode = CHANNEL_WIDTH_20;\n\n\t\tif (phtpriv_sta->op_present\n\t\t\t&& !GET_HT_OP_ELE_STA_CHL_WIDTH(phtpriv_sta->ht_op))\n\t\t\tpsta->cmn.bw_mode = CHANNEL_WIDTH_20;\n\n\t\tif (psta->ht_40mhz_intolerant)\n\t\t\tpsta->cmn.bw_mode = CHANNEL_WIDTH_20;\n\n\t\tif (pmlmeext->cur_bwmode < psta->cmn.bw_mode)\n\t\t\tpsta->cmn.bw_mode = pmlmeext->cur_bwmode;\n\n\t\tphtpriv_sta->ch_offset = pmlmeext->cur_ch_offset;\n\n\n\t\t/* check if sta support s Short GI 20M */\n\t\tif ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_20))\n\t\t\tphtpriv_sta->sgi_20m = _TRUE;\n\n\t\t/* check if sta support s Short GI 40M */\n\t\tif ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)) {\n\t\t\tif (psta->cmn.bw_mode == CHANNEL_WIDTH_40) /* according to psta->bw_mode */\n\t\t\t\tphtpriv_sta->sgi_40m = _TRUE;\n\t\t\telse\n\t\t\t\tphtpriv_sta->sgi_40m = _FALSE;\n\t\t}\n\n\t\tpsta->qos_option = _TRUE;\n\n\t\t/* B0 Config LDPC Coding Capability */\n\t\tif (TEST_FLAG(phtpriv_ap->ldpc_cap, LDPC_HT_ENABLE_TX) &&\n\t\t    GET_HT_CAP_ELE_LDPC_CAP((u8 *)(&phtpriv_sta->ht_cap))) {\n\t\t\tSET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX));\n\t\t\tRTW_INFO(\"Enable HT Tx LDPC for STA(%d)\\n\", psta->cmn.aid);\n\t\t}\n\n\t\t/* B7 B8 B9 Config STBC setting */\n\t\tif (TEST_FLAG(phtpriv_ap->stbc_cap, STBC_HT_ENABLE_TX) &&\n\t\t    GET_HT_CAP_ELE_RX_STBC((u8 *)(&phtpriv_sta->ht_cap))) {\n\t\t\tSET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX));\n\t\t\tRTW_INFO(\"Enable HT Tx STBC for STA(%d)\\n\", psta->cmn.aid);\n\t\t}\n\n\t\t#ifdef CONFIG_BEAMFORMING\n\t\tupdate_sta_info_apmode_ht_bf_cap(padapter, psta);\n\t\t#endif\n\t} else {\n\t\tphtpriv_sta->ampdu_enable = _FALSE;\n\n\t\tphtpriv_sta->sgi_20m = _FALSE;\n\t\tphtpriv_sta->sgi_40m = _FALSE;\n\t\tpsta->cmn.bw_mode = CHANNEL_WIDTH_20;\n\t\tphtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t}\n\n\tphtpriv_sta->ldpc_cap = cur_ldpc_cap;\n\tphtpriv_sta->stbc_cap = cur_stbc_cap;\n\n\t/* Rx AMPDU */\n\tsend_delba(padapter, 0, psta->cmn.mac_addr);/* recipient */\n\n\t/* TX AMPDU */\n\tsend_delba(padapter, 1, psta->cmn.mac_addr);/*  */ /* originator */\n\tphtpriv_sta->agg_enable_bitmap = 0x0;/* reset */\n\tphtpriv_sta->candidate_tid_bitmap = 0x0;/* reset */\n#endif /* CONFIG_80211N_HT */\n\n#ifdef CONFIG_80211AC_VHT\n\tupdate_sta_vht_info_apmode(padapter, psta);\n#endif\n\tpsta->cmn.ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta));\n\tupdate_ldpc_stbc_cap(psta);\n\n\t/* todo: init other variables */\n\n\t_rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats));\n\n\n\t/* add ratid */\n\t/* add_RATid(padapter, psta); */ /* move to ap_sta_info_defer_update() */\n\n\t/* ap mode */\n\trtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);\n\n\t_enter_critical_bh(&psta->lock, &irqL);\n\n\t/* Check encryption */\n\tif (!MLME_IS_MESH(padapter) && psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)\n\t\tpsta->state |= WIFI_UNDER_KEY_HANDSHAKE;\n\n\tpsta->state |= _FW_LINKED;\n\n\t_exit_critical_bh(&psta->lock, &irqL);\n}\n\nstatic void update_ap_info(_adapter *padapter, struct sta_info *psta)\n{\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tWLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n#ifdef CONFIG_80211N_HT\n\tstruct ht_priv\t*phtpriv_ap = &pmlmepriv->htpriv;\n#endif /* CONFIG_80211N_HT */\n\n\tpsta->wireless_mode = pmlmeext->cur_wireless_mode;\n\n\tpsta->bssratelen = rtw_get_rateset_len(pnetwork->SupportedRates);\n\t_rtw_memcpy(psta->bssrateset, pnetwork->SupportedRates, psta->bssratelen);\n\n#ifdef CONFIG_80211N_HT\n\t/* HT related cap */\n\tif (phtpriv_ap->ht_option) {\n\t\t/* check if sta supports rx ampdu */\n\t\t/* phtpriv_ap->ampdu_enable = phtpriv_ap->ampdu_enable; */\n\n\t\t/* check if sta support s Short GI 20M */\n\t\tif ((phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_20))\n\t\t\tphtpriv_ap->sgi_20m = _TRUE;\n\t\t/* check if sta support s Short GI 40M */\n\t\tif ((phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_40))\n\t\t\tphtpriv_ap->sgi_40m = _TRUE;\n\n\t\tpsta->qos_option = _TRUE;\n\t} else {\n\t\tphtpriv_ap->ampdu_enable = _FALSE;\n\n\t\tphtpriv_ap->sgi_20m = _FALSE;\n\t\tphtpriv_ap->sgi_40m = _FALSE;\n\t}\n\n\tpsta->cmn.bw_mode = pmlmeext->cur_bwmode;\n\tphtpriv_ap->ch_offset = pmlmeext->cur_ch_offset;\n\n\tphtpriv_ap->agg_enable_bitmap = 0x0;/* reset */\n\tphtpriv_ap->candidate_tid_bitmap = 0x0;/* reset */\n\n\t_rtw_memcpy(&psta->htpriv, &pmlmepriv->htpriv, sizeof(struct ht_priv));\n\n#ifdef CONFIG_80211AC_VHT\n\t_rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv));\n#endif /* CONFIG_80211AC_VHT */\n\n#endif /* CONFIG_80211N_HT */\n\n\tpsta->state |= WIFI_AP_STATE; /* Aries, add,fix bug of flush_cam_entry at STOP AP mode , 0724 */\n}\n\nstatic void rtw_set_hw_wmm_param(_adapter *padapter)\n{\n\tu8\tAIFS, ECWMin, ECWMax, aSifsTime;\n\tu8\tacm_mask;\n\tu16\tTXOP;\n\tu32\tacParm, i;\n\tu32\tedca[4], inx[4];\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct xmit_priv\t\t*pxmitpriv = &padapter->xmitpriv;\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\n\tacm_mask = 0;\n#ifdef CONFIG_80211N_HT\n\tif (pregpriv->ht_enable &&\n\t\t(is_supported_5g(pmlmeext->cur_wireless_mode) ||\n\t    (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)))\n\t\taSifsTime = 16;\n\telse\n#endif /* CONFIG_80211N_HT */\n\t\taSifsTime = 10;\n\n\tif (pmlmeinfo->WMM_enable == 0) {\n\t\tpadapter->mlmepriv.acm_mask = 0;\n\n\t\tAIFS = aSifsTime + (2 * pmlmeinfo->slotTime);\n\n\t\tif (pmlmeext->cur_wireless_mode & (WIRELESS_11G | WIRELESS_11A)) {\n\t\t\tECWMin = 4;\n\t\t\tECWMax = 10;\n\t\t} else if (pmlmeext->cur_wireless_mode & WIRELESS_11B) {\n\t\t\tECWMin = 5;\n\t\t\tECWMax = 10;\n\t\t} else {\n\t\t\tECWMin = 4;\n\t\t\tECWMax = 10;\n\t\t}\n\n\t\tTXOP = 0;\n\t\tacParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));\n\n\t\tECWMin = 2;\n\t\tECWMax = 3;\n\t\tTXOP = 0x2f;\n\t\tacParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));\n\n\t} else {\n\t\tedca[0] = edca[1] = edca[2] = edca[3] = 0;\n\n\t\t/*TODO:*/\n\t\tacm_mask = 0;\n\t\tpadapter->mlmepriv.acm_mask = acm_mask;\n\n#if 0\n\t\t/* BK */\n\t\t/* AIFS = AIFSN * slot time + SIFS - r2t phy delay */\n#endif\n\t\tAIFS = (7 * pmlmeinfo->slotTime) + aSifsTime;\n\t\tECWMin = 4;\n\t\tECWMax = 10;\n\t\tTXOP = 0;\n\t\tacParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));\n\t\tedca[XMIT_BK_QUEUE] = acParm;\n\t\tRTW_INFO(\"WMM(BK): %x\\n\", acParm);\n\n\t\t/* BE */\n\t\tAIFS = (3 * pmlmeinfo->slotTime) + aSifsTime;\n\t\tECWMin = 4;\n\t\tECWMax = 6;\n\t\tTXOP = 0;\n\t\tacParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));\n\t\tedca[XMIT_BE_QUEUE] = acParm;\n\t\tRTW_INFO(\"WMM(BE): %x\\n\", acParm);\n\n\t\t/* VI */\n\t\tAIFS = (1 * pmlmeinfo->slotTime) + aSifsTime;\n\t\tECWMin = 3;\n\t\tECWMax = 4;\n\t\tTXOP = 94;\n\t\tacParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));\n\t\tedca[XMIT_VI_QUEUE] = acParm;\n\t\tRTW_INFO(\"WMM(VI): %x\\n\", acParm);\n\n\t\t/* VO */\n\t\tAIFS = (1 * pmlmeinfo->slotTime) + aSifsTime;\n\t\tECWMin = 2;\n\t\tECWMax = 3;\n\t\tTXOP = 47;\n\t\tacParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));\n\t\tedca[XMIT_VO_QUEUE] = acParm;\n\t\tRTW_INFO(\"WMM(VO): %x\\n\", acParm);\n\n\n\t\tif (padapter->registrypriv.acm_method == 1)\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_ACM_CTRL, (u8 *)(&acm_mask));\n\t\telse\n\t\t\tpadapter->mlmepriv.acm_mask = acm_mask;\n\n\t\tinx[0] = 0;\n\t\tinx[1] = 1;\n\t\tinx[2] = 2;\n\t\tinx[3] = 3;\n\n\t\tif (pregpriv->wifi_spec == 1) {\n\t\t\tu32\tj, tmp, change_inx = _FALSE;\n\n\t\t\t/* entry indx: 0->vo, 1->vi, 2->be, 3->bk. */\n\t\t\tfor (i = 0 ; i < 4 ; i++) {\n\t\t\t\tfor (j = i + 1 ; j < 4 ; j++) {\n\t\t\t\t\t/* compare CW and AIFS */\n\t\t\t\t\tif ((edca[j] & 0xFFFF) < (edca[i] & 0xFFFF))\n\t\t\t\t\t\tchange_inx = _TRUE;\n\t\t\t\t\telse if ((edca[j] & 0xFFFF) == (edca[i] & 0xFFFF)) {\n\t\t\t\t\t\t/* compare TXOP */\n\t\t\t\t\t\tif ((edca[j] >> 16) > (edca[i] >> 16))\n\t\t\t\t\t\t\tchange_inx = _TRUE;\n\t\t\t\t\t}\n\n\t\t\t\t\tif (change_inx) {\n\t\t\t\t\t\ttmp = edca[i];\n\t\t\t\t\t\tedca[i] = edca[j];\n\t\t\t\t\t\tedca[j] = tmp;\n\n\t\t\t\t\t\ttmp = inx[i];\n\t\t\t\t\t\tinx[i] = inx[j];\n\t\t\t\t\t\tinx[j] = tmp;\n\n\t\t\t\t\t\tchange_inx = _FALSE;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tfor (i = 0 ; i < 4 ; i++) {\n\t\t\tpxmitpriv->wmm_para_seq[i] = inx[i];\n\t\t\tRTW_INFO(\"wmm_para_seq(%d): %d\\n\", i, pxmitpriv->wmm_para_seq[i]);\n\t\t}\n\n\t}\n\n}\n#ifdef CONFIG_80211N_HT\nstatic void update_hw_ht_param(_adapter *padapter)\n{\n\tunsigned char\t\tmax_AMPDU_len;\n\tunsigned char\t\tmin_MPDU_spacing;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\n\t/* handle A-MPDU parameter field */\n\t/*\n\t\tAMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k\n\t\tAMPDU_para [4:2]:Min MPDU Start Spacing\n\t*/\n\tmax_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;\n\n\tmin_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2;\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing));\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len));\n\n\t/*  */\n\t/* Config SM Power Save setting */\n\t/*  */\n\tpmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2;\n\tif (pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) {\n#if 0\n\t\tu8 i;\n\t\t/* update the MCS rates */\n\t\tfor (i = 0; i < 16; i++)\n\t\t\tpmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];\n#endif\n\t\tRTW_INFO(\"%s(): WLAN_HT_CAP_SM_PS_STATIC\\n\", __FUNCTION__);\n\t}\n\n\t/*  */\n\t/* Config current HT Protection mode. */\n\t/*  */\n\t/* pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; */\n\n}\n#endif /* CONFIG_80211N_HT */\nstatic void rtw_ap_check_scan(_adapter *padapter)\n{\n\t_irqL\tirqL;\n\t_list\t\t*plist, *phead;\n\tu32\tdelta_time, lifetime;\n\tstruct\twlan_network\t*pnetwork = NULL;\n\tWLAN_BSSID_EX *pbss = NULL;\n\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\t_queue\t*queue\t= &(pmlmepriv->scanned_queue);\n\tu8 do_scan = _FALSE;\n\tu8 reason = RTW_AUTO_SCAN_REASON_UNSPECIFIED;\n\n\tlifetime = SCANQUEUE_LIFETIME; /* 20 sec */\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\tphead = get_list_head(queue);\n\tif (rtw_end_of_queue_search(phead, get_next(phead)) == _TRUE)\n\t\tif (padapter->registrypriv.wifi_spec) {\n\t\t\tdo_scan = _TRUE;\n\t\t\treason |= RTW_AUTO_SCAN_REASON_2040_BSS;\n\t\t}\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n#ifdef CONFIG_RTW_ACS\n\tif (padapter->registrypriv.acs_auto_scan) {\n\t\tdo_scan = _TRUE;\n\t\treason |= RTW_AUTO_SCAN_REASON_ACS;\n\t\trtw_acs_start(padapter);\n\t}\n#endif/*CONFIG_RTW_ACS*/\n\n\tif (_TRUE == do_scan) {\n\t\tRTW_INFO(\"%s : drv scans by itself and wait_completed\\n\", __func__);\n\t\trtw_drv_scan_by_self(padapter, reason);\n\t\trtw_scan_wait_completed(padapter);\n\t}\n\n#ifdef CONFIG_RTW_ACS\n\tif (padapter->registrypriv.acs_auto_scan)\n\t\trtw_acs_stop(padapter);\n#endif\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\n\twhile (1) {\n\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\n\t\tif (rtw_chset_search_ch(adapter_to_chset(padapter), pnetwork->network.Configuration.DSConfig) >= 0\n\t\t    && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE\n\t\t    && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))) {\n\t\t\tdelta_time = (u32) rtw_get_passing_time_ms(pnetwork->last_scanned);\n\n\t\t\tif (delta_time < lifetime) {\n\n\t\t\t\tuint ie_len = 0;\n\t\t\t\tu8 *pbuf = NULL;\n\t\t\t\tu8 *ie = NULL;\n\n\t\t\t\tpbss = &pnetwork->network;\n\t\t\t\tie = pbss->IEs;\n\n\t\t\t\t/*check if HT CAP INFO IE exists or not*/\n\t\t\t\tpbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pbss->IELength - _BEACON_IE_OFFSET_));\n\t\t\t\tif (pbuf == NULL) {\n\t\t\t\t\t/* HT CAP INFO IE don't exist, it is b/g mode bss.*/\n\n\t\t\t\t\tif (_FALSE == ATOMIC_READ(&pmlmepriv->olbc))\n\t\t\t\t\t\tATOMIC_SET(&pmlmepriv->olbc, _TRUE);\n\n\t\t\t\t\tif (_FALSE == ATOMIC_READ(&pmlmepriv->olbc_ht))\n\t\t\t\t\t\tATOMIC_SET(&pmlmepriv->olbc_ht, _TRUE);\n\t\t\t\t\t\n\t\t\t\t\tif (padapter->registrypriv.wifi_spec)\n\t\t\t\t\t\tRTW_INFO(\"%s: %s is a/b/g ap\\n\", __func__, pnetwork->network.Ssid.Ssid);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tplist = get_next(plist);\n\n\t}\n\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n#ifdef CONFIG_80211N_HT\n\tpmlmepriv->num_sta_no_ht = 0; /* reset to 0 after ap do scanning*/\n#endif\n}\n\nvoid rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter)\n{\n\tWLAN_BSSID_EX *pnetwork = &(adapter->mlmepriv.cur_network.network);\n\tstruct sta_info *sta = NULL;\n\n\t/* update cur_wireless_mode */\n\tupdate_wireless_mode(adapter);\n\n\t/* update RRSR and RTS_INIT_RATE register after set channel and bandwidth */\n\tUpdateBrateTbl(adapter, pnetwork->SupportedRates);\n\trtw_hal_set_hwreg(adapter, HW_VAR_BASIC_RATE, pnetwork->SupportedRates);\n\n\t/* update capability after cur_wireless_mode updated */\n\tupdate_capinfo(adapter, rtw_get_capability(pnetwork));\n\n\t/* update bc/mc sta_info */\n\tupdate_bmc_sta(adapter);\n\n\t/* update AP's sta info */\n\tsta = rtw_get_stainfo(&adapter->stapriv, pnetwork->MacAddress);\n\tif (!sta) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" !sta for macaddr=\"MAC_FMT\"\\n\", FUNC_ADPT_ARG(adapter), MAC_ARG(pnetwork->MacAddress));\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tupdate_ap_info(adapter, sta);\n}\n\n#ifdef CONFIG_FW_HANDLE_TXBCN\nbool rtw_ap_nums_check(_adapter *adapter)\n{\n\tif (rtw_ap_get_nums(adapter) < CONFIG_LIMITED_AP_NUM)\n\t\treturn _TRUE;\n\treturn _FALSE;\n}\nu8 rtw_ap_allocate_vapid(struct dvobj_priv *dvobj)\n{\n\tu8 vap_id;\n\n\tfor (vap_id = 0; vap_id < CONFIG_LIMITED_AP_NUM; vap_id++) {\n\t\tif (!(dvobj->vap_map & BIT(vap_id)))\n\t\t\tbreak;\n\t}\n\n\tif (vap_id < CONFIG_LIMITED_AP_NUM)\n\t\tdvobj->vap_map |= BIT(vap_id);\n\n\treturn vap_id;\n}\nu8 rtw_ap_release_vapid(struct dvobj_priv *dvobj, u8 vap_id)\n{\n\tif (vap_id >= CONFIG_LIMITED_AP_NUM) {\n\t\tRTW_ERR(\"%s - vapid(%d) failed\\n\", __func__, vap_id);\n\t\trtw_warn_on(1);\n\t\treturn _FAIL;\n\t}\n\tdvobj->vap_map &= ~ BIT(vap_id);\n\treturn _SUCCESS;\n}\n#endif\nstatic void _rtw_iface_undersurvey_chk(const char *func, _adapter *adapter)\n{\n\tint i;\n\t_adapter *iface;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mlme_priv *pmlmepriv;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif ((iface) && rtw_is_adapter_up(iface)) {\n\t\t\tpmlmepriv = &iface->mlmepriv;\n\t\t\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))\n\t\t\t\tRTW_ERR(\"%s (\"ADPT_FMT\") under survey\\n\", func, ADPT_ARG(iface));\n\t\t}\n\t}\n}\nvoid start_bss_network(_adapter *padapter, struct createbss_parm *parm)\n{\n#define DUMP_ADAPTERS_STATUS 0\n\tu8 mlme_act = MLME_ACTION_UNKNOWN;\n\tu8 val8;\n\tu16 bcn_interval;\n\tu32\tacparm;\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct security_priv *psecuritypriv = &(padapter->securitypriv);\n\tWLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; /* used as input */\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network);\n\tstruct dvobj_priv *pdvobj = padapter->dvobj;\n\ts16 req_ch = REQ_CH_NONE, req_bw = REQ_BW_NONE, req_offset = REQ_OFFSET_NONE;\n\tu8 ch_to_set = 0, bw_to_set, offset_to_set;\n\tu8 doiqk = _FALSE;\n\t/* use for check ch bw offset can be allowed or not */\n\tu8 chbw_allow = _TRUE;\n\tint i;\n\tu8 ifbmp_ch_changed = 0;\n\n\tif (parm->req_ch != 0) {\n\t\t/* bypass other setting, go checking ch, bw, offset */\n\t\tmlme_act = MLME_OPCH_SWITCH;\n\t\treq_ch = parm->req_ch;\n\t\treq_bw = parm->req_bw;\n\t\treq_offset = parm->req_offset;\n\t\tgoto chbw_decision;\n\t} else {\n\t\t/* request comes from upper layer */\n\t\tif (MLME_IS_AP(padapter))\n\t\t\tmlme_act = MLME_AP_STARTED;\n\t\telse if (MLME_IS_MESH(padapter))\n\t\t\tmlme_act = MLME_MESH_STARTED;\n\t\telse\n\t\t\trtw_warn_on(1);\n\t\treq_ch = 0;\n\t\t_rtw_memcpy(pnetwork_mlmeext, pnetwork, pnetwork->Length);\n\t}\n\n\tbcn_interval = (u16)pnetwork->Configuration.BeaconPeriod;\n\n\t/* check if there is wps ie, */\n\t/* if there is wpsie in beacon, the hostapd will update beacon twice when stating hostapd, */\n\t/* and at first time the security ie ( RSN/WPA IE) will not include in beacon. */\n\tif (NULL == rtw_get_wps_ie(pnetwork->IEs + _FIXED_IE_LENGTH_, pnetwork->IELength - _FIXED_IE_LENGTH_, NULL, NULL))\n\t\tpmlmeext->bstart_bss = _TRUE;\n\n\t/* todo: update wmm, ht cap */\n\t/* pmlmeinfo->WMM_enable; */\n\t/* pmlmeinfo->HT_enable; */\n\tif (pmlmepriv->qospriv.qos_option)\n\t\tpmlmeinfo->WMM_enable = _TRUE;\n#ifdef CONFIG_80211N_HT\n\tif (pmlmepriv->htpriv.ht_option) {\n\t\tpmlmeinfo->WMM_enable = _TRUE;\n\t\tpmlmeinfo->HT_enable = _TRUE;\n\t\t/* pmlmeinfo->HT_info_enable = _TRUE; */\n\t\t/* pmlmeinfo->HT_caps_enable = _TRUE; */\n\n\t\tupdate_hw_ht_param(padapter);\n\t}\n#endif /* #CONFIG_80211N_HT */\n\n#ifdef CONFIG_80211AC_VHT\n\tif (pmlmepriv->vhtpriv.vht_option) {\n\t\tpmlmeinfo->VHT_enable = _TRUE;\n\t\tupdate_hw_vht_param(padapter);\n\t}\n#endif /* CONFIG_80211AC_VHT */\n\n\tif (pmlmepriv->cur_network.join_res != _TRUE) { /* setting only at  first time */\n\t\t/* WEP Key will be set before this function, do not clear CAM. */\n\t\tif ((psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) && (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_)\n\t\t\t&& !MLME_IS_MESH(padapter) /* mesh group key is set before this function */\n\t\t)\n\t\t\tflush_all_cam_entry(padapter);\t/* clear CAM */\n\t}\n\n\t/* set MSR to AP_Mode\t\t */\n\tSet_MSR(padapter, _HW_STATE_AP_);\n\n\t/* Set BSSID REG */\n\trtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pnetwork->MacAddress);\n\n\t/* Set Security */\n\tval8 = (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) ? 0xcc : 0xcf;\n\trtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));\n\n\t/* Beacon Control related register */\n\trtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&bcn_interval));\n\n\trtw_hal_rcr_set_chk_bssid(padapter, mlme_act);\n\nchbw_decision:\n\tifbmp_ch_changed = rtw_ap_chbw_decision(padapter, parm->ifbmp, parm->excl_ifbmp\n\t\t\t\t\t\t, req_ch, req_bw, req_offset\n\t\t\t\t\t\t, &ch_to_set, &bw_to_set, &offset_to_set, &chbw_allow);\n\n\tfor (i = 0; i < pdvobj->iface_nums; i++) {\n\t\tif (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i])\n\t\t\tcontinue;\n\n\t\t/* let pnetwork_mlme == pnetwork_mlmeext */\n\t\t_rtw_memcpy(&(pdvobj->padapters[i]->mlmepriv.cur_network.network)\n\t\t\t, &(pdvobj->padapters[i]->mlmeextpriv.mlmext_info.network)\n\t\t\t, pdvobj->padapters[i]->mlmeextpriv.mlmext_info.network.Length);\n\n\t\trtw_start_bss_hdl_after_chbw_decided(pdvobj->padapters[i]);\n\n\t\t/* Set EDCA param reg after update cur_wireless_mode & update_capinfo */\n\t\tif (pregpriv->wifi_spec == 1)\n\t\t\trtw_set_hw_wmm_param(pdvobj->padapters[i]);\n\t}\n\n#if defined(CONFIG_DFS_MASTER)\n\trtw_dfs_rd_en_decision(padapter, mlme_act, parm->excl_ifbmp);\n#endif\n\n#ifdef CONFIG_MCC_MODE\n\tif (MCC_EN(padapter)) {\n\t\t/* \n\t\t* due to check under rtw_ap_chbw_decision\n\t\t* if under MCC mode, means req channel setting is the same as current channel setting\n\t\t* if not under MCC mode, mean req channel setting is not the same as current channel setting\n\t\t*/\n\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\": req channel setting is the same as current channel setting, go to update BCN\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter));\n\n\t\t\t\tgoto update_beacon;\n\n\t\t}\n\t}\n\n\t/* issue null data to AP for all interface connecting to AP before switch channel setting for softap */\n\trtw_hal_mcc_issue_null_data(padapter, chbw_allow, 1);\n#endif /* CONFIG_MCC_MODE */\n\n\tif (!IS_CH_WAITING(adapter_to_rfctl(padapter))) {\n\t\tdoiqk = _TRUE;\n\t\trtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);\n\t}\n\n\tif (ch_to_set != 0) {\n\t\tset_channel_bwmode(padapter, ch_to_set, offset_to_set, bw_to_set);\n\t\trtw_mi_update_union_chan_inf(padapter, ch_to_set, offset_to_set, bw_to_set);\n\t}\n\n\tdoiqk = _FALSE;\n\trtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);\n\n#ifdef CONFIG_MCC_MODE\n\t/* after set_channel_bwmode for backup IQK */\n\trtw_hal_set_mcc_setting_start_bss_network(padapter, chbw_allow);\n#endif\n\n#if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))\n\tfor (i = 0; i < pdvobj->iface_nums; i++) {\n\t\tif (!(ifbmp_ch_changed & BIT(i)) || !pdvobj->padapters[i])\n\t\t\tcontinue;\n\n\t\t{\n\t\t\tu8 ht_option = 0;\n\n\t\t\t#ifdef CONFIG_80211N_HT\n\t\t\tht_option = pdvobj->padapters[i]->mlmepriv.htpriv.ht_option;\n\t\t\t#endif\n\n\t\t\trtw_cfg80211_ch_switch_notify(pdvobj->padapters[i]\n\t\t\t\t, pdvobj->padapters[i]->mlmeextpriv.cur_channel\n\t\t\t\t, pdvobj->padapters[i]->mlmeextpriv.cur_bwmode\n\t\t\t\t, pdvobj->padapters[i]->mlmeextpriv.cur_ch_offset\n\t\t\t\t, ht_option);\n\t\t}\n\t}\n#endif /* defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) */\n\n\tif (DUMP_ADAPTERS_STATUS) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" done\\n\", FUNC_ADPT_ARG(padapter));\n\t\tdump_adapters_status(RTW_DBGDUMP , adapter_to_dvobj(padapter));\n\t}\n\n#ifdef CONFIG_MCC_MODE\nupdate_beacon:\n#endif\n\n\tfor (i = 0; i < pdvobj->iface_nums; i++) {\n\t\tstruct mlme_priv *mlme;\n\n\t\tif (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i])\n\t\t\tcontinue;\n\n\t\t/* update beacon content only if bstart_bss is _TRUE */\n\t\tif (pdvobj->padapters[i]->mlmeextpriv.bstart_bss != _TRUE)\n\t\t\tcontinue;\n\n\t\tmlme = &(pdvobj->padapters[i]->mlmepriv);\n\n\t\t#ifdef CONFIG_80211N_HT\n\t\tif ((ATOMIC_READ(&mlme->olbc) == _TRUE) || (ATOMIC_READ(&mlme->olbc_ht) == _TRUE)) {\n\t\t\t/* AP is not starting a 40 MHz BSS in presence of an 802.11g BSS. */\n\t\t\tmlme->ht_op_mode &= (~HT_INFO_OPERATION_MODE_OP_MODE_MASK);\n\t\t\tmlme->ht_op_mode |= OP_MODE_MAY_BE_LEGACY_STAS;\n\t\t\tupdate_beacon(pdvobj->padapters[i], _HT_ADD_INFO_IE_, NULL, _FALSE, 0);\n\t\t}\n\t\t#endif\n\n\t\tupdate_beacon(pdvobj->padapters[i], _TIM_IE_, NULL, _FALSE, 0);\n\t}\n\n\tif (mlme_act != MLME_OPCH_SWITCH\n\t\t&& pmlmeext->bstart_bss == _TRUE\n\t) {\n#ifdef CONFIG_SUPPORT_MULTI_BCN\n\t\t_irqL irqL;\n\n\t\t_enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL);\n\t\tif (rtw_is_list_empty(&padapter->list)) {\n\t\t\t#ifdef CONFIG_FW_HANDLE_TXBCN\n\t\t\tpadapter->vap_id = rtw_ap_allocate_vapid(pdvobj);\n\t\t\t#endif\n\t\t\trtw_list_insert_tail(&padapter->list, get_list_head(&pdvobj->ap_if_q));\n\t\t\tpdvobj->nr_ap_if++;\n\t\t\tpdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL / pdvobj->nr_ap_if;\n\t\t}\n\t\t_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);\n\n\t\t#ifdef CONFIG_SWTIMER_BASED_TXBCN\n\t\trtw_ap_set_mbid_num(padapter, pdvobj->nr_ap_if);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pdvobj->inter_bcn_space));\n\t\t#endif /*CONFIG_SWTIMER_BASED_TXBCN*/\n\n#endif /*CONFIG_SUPPORT_MULTI_BCN*/\n\n\t\t#ifdef CONFIG_HW_P0_TSF_SYNC\n\t\tcorrect_TSF(padapter, mlme_act);\n\t\t#endif\n\t}\n\n\trtw_scan_wait_completed(padapter);\n\n\t_rtw_iface_undersurvey_chk(__func__, padapter);\n\t/* send beacon */\n\tResumeTxBeacon(padapter);\n\t{\n#if !defined(CONFIG_INTERRUPT_BASED_TXBCN)\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_PCI_BCN_POLLING)\n#ifdef CONFIG_SWTIMER_BASED_TXBCN\n\t\tif (pdvobj->nr_ap_if == 1\n\t\t\t&& mlme_act != MLME_OPCH_SWITCH\n\t\t) {\n\t\t\tRTW_INFO(\"start SW BCN TIMER!\\n\");\n\t\t\t_set_timer(&pdvobj->txbcn_timer, bcn_interval);\n\t\t}\n#else\n\t\tfor (i = 0; i < pdvobj->iface_nums; i++) {\n\t\t\tif (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i])\n\t\t\t\tcontinue;\n\n\t\t\tif (send_beacon(pdvobj->padapters[i]) == _FAIL)\n\t\t\t\tRTW_INFO(ADPT_FMT\" issue_beacon, fail!\\n\", ADPT_ARG(pdvobj->padapters[i]));\n\t\t}\n#endif\n#endif\n#endif /* !defined(CONFIG_INTERRUPT_BASED_TXBCN) */\n\n#ifdef CONFIG_FW_HANDLE_TXBCN\n\t\tif (mlme_act != MLME_OPCH_SWITCH)\n\t\t\trtw_ap_mbid_bcn_en(padapter, padapter->vap_id);\n#endif\n\t}\n}\n\nint rtw_check_beacon_data(_adapter *padapter, u8 *pbuf,  int len)\n{\n\tint ret = _SUCCESS;\n\tu8 *p;\n\tu8 *pHT_caps_ie = NULL;\n\tu8 *pHT_info_ie = NULL;\n\tu16 cap, ht_cap = _FALSE;\n\tuint ie_len = 0;\n\tint group_cipher, pairwise_cipher;\n\tu32 akm;\n\tu8 mfp_opt = MFP_NO;\n\tu8\tchannel, network_type;\n\tu8 OUI1[] = {0x00, 0x50, 0xf2, 0x01};\n\tu8 WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01};\n\tHT_CAP_AMPDU_DENSITY best_ampdu_density;\n\tstruct registry_priv *pregistrypriv = &padapter->registrypriv;\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tWLAN_BSSID_EX *pbss_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;\n\tu8 *ie = pbss_network->IEs;\n\tu8 vht_cap = _FALSE;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tu8 rf_num = 0;\n\tint ret_rm;\n\t/* SSID */\n\t/* Supported rates */\n\t/* DS Params */\n\t/* WLAN_EID_COUNTRY */\n\t/* ERP Information element */\n\t/* Extended supported rates */\n\t/* WPA/WPA2 */\n\t/* Wi-Fi Wireless Multimedia Extensions */\n\t/* ht_capab, ht_oper */\n\t/* WPS IE */\n\n\tRTW_INFO(\"%s, len=%d\\n\", __FUNCTION__, len);\n\n\tif (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))\n\t\treturn _FAIL;\n\n\n\tif (len > MAX_IE_SZ)\n\t\treturn _FAIL;\n\n\tpbss_network->IELength = len;\n\n\t_rtw_memset(ie, 0, MAX_IE_SZ);\n\n\t_rtw_memcpy(ie, pbuf, pbss_network->IELength);\n\n\n\tif (pbss_network->InfrastructureMode != Ndis802_11APMode\n\t\t&& pbss_network->InfrastructureMode != Ndis802_11_mesh\n\t) {\n\t\trtw_warn_on(1);\n\t\treturn _FAIL;\n\t}\n\n\n\trtw_ap_check_scan(padapter);\n\n\n\tpbss_network->Rssi = 0;\n\n\t_rtw_memcpy(pbss_network->MacAddress, adapter_mac_addr(padapter), ETH_ALEN);\n\n\t/* beacon interval */\n\tp = rtw_get_beacon_interval_from_ie(ie);/* ie + 8;\t */ /* 8: TimeStamp, 2: Beacon Interval 2:Capability */\n\t/* pbss_network->Configuration.BeaconPeriod = le16_to_cpu(*(unsigned short*)p); */\n\tpbss_network->Configuration.BeaconPeriod = RTW_GET_LE16(p);\n\n\t/* capability */\n\t/* cap = *(unsigned short *)rtw_get_capability_from_ie(ie); */\n\t/* cap = le16_to_cpu(cap); */\n\tcap = RTW_GET_LE16(ie);\n\n\t/* SSID */\n\tp = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SSID_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));\n\tif (p && ie_len > 0) {\n\t\t_rtw_memset(&pbss_network->Ssid, 0, sizeof(NDIS_802_11_SSID));\n\t\t_rtw_memcpy(pbss_network->Ssid.Ssid, (p + 2), ie_len);\n\t\tpbss_network->Ssid.SsidLength = ie_len;\n#ifdef CONFIG_P2P\n\t\t_rtw_memcpy(padapter->wdinfo.p2p_group_ssid, pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength);\n\t\tpadapter->wdinfo.p2p_group_ssid_len = pbss_network->Ssid.SsidLength;\n#endif\n\t}\n\n#ifdef CONFIG_RTW_MESH\n\t/* Mesh ID */\n\tif (MLME_IS_MESH(padapter)) {\n\t\tp = rtw_get_ie(ie + _BEACON_IE_OFFSET_, WLAN_EID_MESH_ID, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));\n\t\tif (p && ie_len > 0) {\n\t\t\t_rtw_memset(&pbss_network->mesh_id, 0, sizeof(NDIS_802_11_SSID));\n\t\t\t_rtw_memcpy(pbss_network->mesh_id.Ssid, (p + 2), ie_len);\n\t\t\tpbss_network->mesh_id.SsidLength = ie_len;\n\t\t}\n\t}\n#endif\n\n\t/* chnnel */\n\tchannel = 0;\n\tpbss_network->Configuration.Length = 0;\n\tp = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _DSSET_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));\n\tif (p && ie_len > 0)\n\t\tchannel = *(p + 2);\n\n\tpbss_network->Configuration.DSConfig = channel;\n\n\t/*\tsupport rate ie & ext support ie & IElen & SupportedRates\t*/\n\tnetwork_type = rtw_update_rate_bymode(pbss_network, pregistrypriv->wireless_mode);\n\n\t/* parsing ERP_IE */\n\tp = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));\n\tif (p && ie_len > 0)  {\n\t\tif(padapter->registrypriv.wireless_mode == WIRELESS_11B ) {\n\n\t\t\tpbss_network->IELength = pbss_network->IELength - *(p+1) - 2;\n\t\t\tret_rm = rtw_ies_remove_ie(ie , &len, _BEACON_IE_OFFSET_, _ERPINFO_IE_,NULL,0);\n\t\t\tRTW_DBG(\"%s, remove_ie of ERP_IE=%d\\n\", __FUNCTION__, ret_rm);\n\t\t} else \n\t\t\tERP_IE_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)p);\n\n\t}\n\n\t/* update privacy/security */\n\tif (cap & BIT(4))\n\t\tpbss_network->Privacy = 1;\n\telse\n\t\tpbss_network->Privacy = 0;\n\n\tpsecuritypriv->wpa_psk = 0;\n\n\t/* wpa2 */\n\takm = 0;\n\tgroup_cipher = 0;\n\tpairwise_cipher = 0;\n\tpsecuritypriv->wpa2_group_cipher = _NO_PRIVACY_;\n\tpsecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_;\n\tp = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));\n\tif (p && ie_len > 0) {\n\t\tif (rtw_parse_wpa2_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, &akm, &mfp_opt) == _SUCCESS) {\n\t\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;\n\t\t\tpsecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK;\n\t\t\tpsecuritypriv->dot8021xalg = 1;/* psk,  todo:802.1x */\n\t\t\tpsecuritypriv->wpa_psk |= BIT(1);\n\n\t\t\tpsecuritypriv->wpa2_group_cipher = group_cipher;\n\t\t\tpsecuritypriv->wpa2_pairwise_cipher = pairwise_cipher;\n\n\t\t\t/*\n\t\t\tKernel < v5.1, the auth_type set as NL80211_AUTHTYPE_AUTOMATIC \n\t\t\tin cfg80211_rtw_start_ap().\n\t\t\tif the AKM SAE in the RSN IE, we have to update the auth_type for SAE\n\t\t\tin rtw_check_beacon_data().\n\t\t\t*/\n\t\t\tif (CHECK_BIT(WLAN_AKM_TYPE_SAE, akm))\n\t\t\t\tpsecuritypriv->auth_type = NL80211_AUTHTYPE_SAE;\n#if 0\n\t\t\tswitch (group_cipher) {\n\t\t\tcase WPA_CIPHER_NONE:\n\t\t\t\tpsecuritypriv->wpa2_group_cipher = _NO_PRIVACY_;\n\t\t\t\tbreak;\n\t\t\tcase WPA_CIPHER_WEP40:\n\t\t\t\tpsecuritypriv->wpa2_group_cipher = _WEP40_;\n\t\t\t\tbreak;\n\t\t\tcase WPA_CIPHER_TKIP:\n\t\t\t\tpsecuritypriv->wpa2_group_cipher = _TKIP_;\n\t\t\t\tbreak;\n\t\t\tcase WPA_CIPHER_CCMP:\n\t\t\t\tpsecuritypriv->wpa2_group_cipher = _AES_;\n\t\t\t\tbreak;\n\t\t\tcase WPA_CIPHER_WEP104:\n\t\t\t\tpsecuritypriv->wpa2_group_cipher = _WEP104_;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tswitch (pairwise_cipher) {\n\t\t\tcase WPA_CIPHER_NONE:\n\t\t\t\tpsecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_;\n\t\t\t\tbreak;\n\t\t\tcase WPA_CIPHER_WEP40:\n\t\t\t\tpsecuritypriv->wpa2_pairwise_cipher = _WEP40_;\n\t\t\t\tbreak;\n\t\t\tcase WPA_CIPHER_TKIP:\n\t\t\t\tpsecuritypriv->wpa2_pairwise_cipher = _TKIP_;\n\t\t\t\tbreak;\n\t\t\tcase WPA_CIPHER_CCMP:\n\t\t\t\tpsecuritypriv->wpa2_pairwise_cipher = _AES_;\n\t\t\t\tbreak;\n\t\t\tcase WPA_CIPHER_WEP104:\n\t\t\t\tpsecuritypriv->wpa2_pairwise_cipher = _WEP104_;\n\t\t\t\tbreak;\n\t\t\t}\n#endif\n\t\t}\n\n\t}\n\n\t/* wpa */\n\tie_len = 0;\n\tgroup_cipher = 0;\n\tpairwise_cipher = 0;\n\tpsecuritypriv->wpa_group_cipher = _NO_PRIVACY_;\n\tpsecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_;\n\tfor (p = ie + _BEACON_IE_OFFSET_; ; p += (ie_len + 2)) {\n\t\tp = rtw_get_ie(p, _SSN_IE_1_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2)));\n\t\tif ((p) && (_rtw_memcmp(p + 2, OUI1, 4))) {\n\t\t\tif (rtw_parse_wpa_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {\n\t\t\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;\n\t\t\t\tpsecuritypriv->ndisauthtype = Ndis802_11AuthModeWPAPSK;\n\t\t\t\tpsecuritypriv->dot8021xalg = 1;/* psk,  todo:802.1x */\n\n\t\t\t\tpsecuritypriv->wpa_psk |= BIT(0);\n\n\t\t\t\tpsecuritypriv->wpa_group_cipher = group_cipher;\n\t\t\t\tpsecuritypriv->wpa_pairwise_cipher = pairwise_cipher;\n\n#if 0\n\t\t\t\tswitch (group_cipher) {\n\t\t\t\tcase WPA_CIPHER_NONE:\n\t\t\t\t\tpsecuritypriv->wpa_group_cipher = _NO_PRIVACY_;\n\t\t\t\t\tbreak;\n\t\t\t\tcase WPA_CIPHER_WEP40:\n\t\t\t\t\tpsecuritypriv->wpa_group_cipher = _WEP40_;\n\t\t\t\t\tbreak;\n\t\t\t\tcase WPA_CIPHER_TKIP:\n\t\t\t\t\tpsecuritypriv->wpa_group_cipher = _TKIP_;\n\t\t\t\t\tbreak;\n\t\t\t\tcase WPA_CIPHER_CCMP:\n\t\t\t\t\tpsecuritypriv->wpa_group_cipher = _AES_;\n\t\t\t\t\tbreak;\n\t\t\t\tcase WPA_CIPHER_WEP104:\n\t\t\t\t\tpsecuritypriv->wpa_group_cipher = _WEP104_;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\tswitch (pairwise_cipher) {\n\t\t\t\tcase WPA_CIPHER_NONE:\n\t\t\t\t\tpsecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_;\n\t\t\t\t\tbreak;\n\t\t\t\tcase WPA_CIPHER_WEP40:\n\t\t\t\t\tpsecuritypriv->wpa_pairwise_cipher = _WEP40_;\n\t\t\t\t\tbreak;\n\t\t\t\tcase WPA_CIPHER_TKIP:\n\t\t\t\t\tpsecuritypriv->wpa_pairwise_cipher = _TKIP_;\n\t\t\t\t\tbreak;\n\t\t\t\tcase WPA_CIPHER_CCMP:\n\t\t\t\t\tpsecuritypriv->wpa_pairwise_cipher = _AES_;\n\t\t\t\t\tbreak;\n\t\t\t\tcase WPA_CIPHER_WEP104:\n\t\t\t\t\tpsecuritypriv->wpa_pairwise_cipher = _WEP104_;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n#endif\n\t\t\t}\n\n\t\t\tbreak;\n\n\t\t}\n\n\t\tif ((p == NULL) || (ie_len == 0))\n\t\t\tbreak;\n\n\t}\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(padapter)) {\n\t\t/* MFP is mandatory for secure mesh */\n\t\tif (padapter->mesh_info.mesh_auth_id)\n\t\t\tmfp_opt = MFP_REQUIRED;\n\t} else\n#endif\n\tif (mfp_opt == MFP_INVALID) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" invalid MFP setting\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn _FAIL;\n\t}\n\tpsecuritypriv->mfp_opt = mfp_opt;\n\n\t/* wmm */\n\tie_len = 0;\n\tpmlmepriv->qospriv.qos_option = 0;\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(padapter))\n\t\tpmlmepriv->qospriv.qos_option = 1;\n#endif\n\tif (pregistrypriv->wmm_enable) {\n\t\tfor (p = ie + _BEACON_IE_OFFSET_; ; p += (ie_len + 2)) {\n\t\t\tp = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2)));\n\t\t\tif ((p) && _rtw_memcmp(p + 2, WMM_PARA_IE, 6)) {\n\t\t\t\tpmlmepriv->qospriv.qos_option = 1;\n\n\t\t\t\t*(p + 8) |= BIT(7); /* QoS Info, support U-APSD */\n\n\t\t\t\t/* disable all ACM bits since the WMM admission control is not supported */\n\t\t\t\t*(p + 10) &= ~BIT(4); /* BE */\n\t\t\t\t*(p + 14) &= ~BIT(4); /* BK */\n\t\t\t\t*(p + 18) &= ~BIT(4); /* VI */\n\t\t\t\t*(p + 22) &= ~BIT(4); /* VO */\n\n\t\t\t\tWMM_param_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)p);\n\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif ((p == NULL) || (ie_len == 0))\n\t\t\t\tbreak;\n\t\t}\n\t}\n#ifdef CONFIG_80211N_HT\n\tif(padapter->registrypriv.ht_enable &&\n\t\tis_supported_ht(padapter->registrypriv.wireless_mode)) {\n\t\t/* parsing HT_CAP_IE */\n\t\tp = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));\n\t\tif (p && ie_len > 0) {\n\t\t\tu8 rf_type = 0;\n\t\t\tHT_CAP_AMPDU_FACTOR max_rx_ampdu_factor = MAX_AMPDU_FACTOR_64K;\n\t\t\tstruct rtw_ieee80211_ht_cap *pht_cap = (struct rtw_ieee80211_ht_cap *)(p + 2);\n\n\t\t\tif (0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" HT_CAP_IE from upper layer:\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\t\tdump_ht_cap_ie_content(RTW_DBGDUMP, p + 2, ie_len);\n\t\t\t}\n\n\t\t\tpHT_caps_ie = p;\n\n\t\t\tht_cap = _TRUE;\n\t\t\tnetwork_type |= WIRELESS_11_24N;\n\n\t\t\trtw_ht_use_default_setting(padapter);\n\n\t\t\t/* Update HT Capabilities Info field */\n\t\t\tif (pmlmepriv->htpriv.sgi_20m == _FALSE)\n\t\t\t\tpht_cap->cap_info &= ~(IEEE80211_HT_CAP_SGI_20);\n\n\t\t\tif (pmlmepriv->htpriv.sgi_40m == _FALSE)\n\t\t\t\tpht_cap->cap_info &= ~(IEEE80211_HT_CAP_SGI_40);\n\n\t\t\tif (!TEST_FLAG(pmlmepriv->htpriv.ldpc_cap, LDPC_HT_ENABLE_RX))\n\t\t\t\tpht_cap->cap_info &= ~(IEEE80211_HT_CAP_LDPC_CODING);\n\n\t\t\tif (!TEST_FLAG(pmlmepriv->htpriv.stbc_cap, STBC_HT_ENABLE_TX))\n\t\t\t\tpht_cap->cap_info &= ~(IEEE80211_HT_CAP_TX_STBC);\n\n\t\t\tif (!TEST_FLAG(pmlmepriv->htpriv.stbc_cap, STBC_HT_ENABLE_RX))\n\t\t\t\tpht_cap->cap_info &= ~(IEEE80211_HT_CAP_RX_STBC_3R);\n\n\t\t\t/* Update A-MPDU Parameters field */\n\t\t\tpht_cap->ampdu_params_info &= ~(IEEE80211_HT_CAP_AMPDU_FACTOR | IEEE80211_HT_CAP_AMPDU_DENSITY);\n\n\t\t\tif ((psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_CCMP) ||\n\t\t\t\t(psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_CCMP)) {\n\t\t\t\trtw_hal_get_def_var(padapter, HW_VAR_BEST_AMPDU_DENSITY, &best_ampdu_density);\n\t\t\t\tpht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & (best_ampdu_density << 2));\n\t\t\t} else\n\t\t\t\tpht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & 0x00);\n\n\t\t\trtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor);\n\t\t\tpht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_FACTOR & max_rx_ampdu_factor); /* set  Max Rx AMPDU size  to 64K */\n\n\t\t\t_rtw_memcpy(&(pmlmeinfo->HT_caps), pht_cap, sizeof(struct HT_caps_element));\n\n\t\t\t/* Update Supported MCS Set field */\n\t\t\t{\n\t\t\t\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);\n\t\t\t\tu8 rx_nss = 0;\n\t\t\t\tint i;\n\n\t\t\t\trtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));\n\t\t\t\trx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num);\n\n\t\t\t\t/* RX MCS Bitmask */\n\t\t\t\tswitch (rx_nss) {\n\t\t\t\tcase 1:\n\t\t\t\t\tset_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_1R);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 2:\n\t\t\t\t\tset_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_2R);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 3:\n\t\t\t\t\tset_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_3R);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 4:\n\t\t\t\t\tset_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_4R);\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tRTW_WARN(\"rf_type:%d or rx_nss:%u is not expected\\n\", rf_type, hal_spec->rx_nss_num);\n\t\t\t\t}\n\t\t\t\tfor (i = 0; i < 10; i++)\n\t\t\t\t\t*(HT_CAP_ELE_RX_MCS_MAP(pht_cap) + i) &= padapter->mlmeextpriv.default_supported_mcs_set[i];\n\t\t\t}\n\n#ifdef CONFIG_BEAMFORMING\n\t\t\t/* Use registry value to enable HT Beamforming. */\n\t\t\t/* ToDo: use configure file to set these capability. */\n\t\t\tpht_cap->tx_BF_cap_info = 0;\n\n\t\t\t/* HT Beamformer */\n\t\t\tif (TEST_FLAG(pmlmepriv->htpriv.beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {\n\t\t\t\t/* Transmit NDP Capable */\n\t\t\t\tSET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(pht_cap, 1);\n\t\t\t\t/* Explicit Compressed Steering Capable */\n\t\t\t\tSET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pht_cap, 1);\n\t\t\t\t/* Compressed Steering Number Antennas */\n\t\t\t\tSET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pht_cap, 1);\n\t\t\t\trtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num);\n\t\t\t\tSET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pht_cap, rf_num);\n\t\t\t}\n\n\t\t\t/* HT Beamformee */\n\t\t\tif (TEST_FLAG(pmlmepriv->htpriv.beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) {\n\t\t\t\t/* Receive NDP Capable */\n\t\t\t\tSET_HT_CAP_TXBF_RECEIVE_NDP_CAP(pht_cap, 1);\n\t\t\t\t/* Explicit Compressed Beamforming Feedback Capable */\n\t\t\t\tSET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pht_cap, 2);\n\t\t\t\trtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);\n\t\t\t\tSET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pht_cap, rf_num);\n\t\t\t}\n#endif /* CONFIG_BEAMFORMING */\n\n\t\t\t_rtw_memcpy(&pmlmepriv->htpriv.ht_cap, p + 2, ie_len);\n\n\t\t\tif (0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" HT_CAP_IE driver masked:\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\t\tdump_ht_cap_ie_content(RTW_DBGDUMP, p + 2, ie_len);\n\t\t\t}\n\t\t}\n\n\t\t/* parsing HT_INFO_IE */\n\t\tp = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));\n\t\tif (p && ie_len > 0) {\n\t\t\tpHT_info_ie = p;\n\t\t\tif (channel == 0)\n\t\t\t\tpbss_network->Configuration.DSConfig = GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2);\n\t\t\telse if (channel != GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2)) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" ch inconsistent, DSSS:%u, HT primary:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), channel, GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2));\n\t\t\t}\n\t\t}\n\t}\n#endif /* CONFIG_80211N_HT */\n\tpmlmepriv->cur_network.network_type = network_type;\n\n#ifdef CONFIG_80211N_HT\n\tpmlmepriv->htpriv.ht_option = _FALSE;\n\n\tif ((psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_TKIP) ||\n\t    (psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_TKIP)) {\n\t\t/* todo: */\n\t\t/* ht_cap = _FALSE; */\n\t}\n\n\t/* ht_cap\t */\n\tif (padapter->registrypriv.ht_enable &&\n\t\tis_supported_ht(padapter->registrypriv.wireless_mode) && ht_cap == _TRUE) {\n\n\t\tpmlmepriv->htpriv.ht_option = _TRUE;\n\t\tpmlmepriv->qospriv.qos_option = 1;\n\n\t\tpmlmepriv->htpriv.ampdu_enable = pregistrypriv->ampdu_enable ? _TRUE : _FALSE;\n\n\t\tHT_caps_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_caps_ie);\n\n\t\tHT_info_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_info_ie);\n\t}\n#endif\n\n#ifdef CONFIG_80211AC_VHT\n\tpmlmepriv->ori_vht_en = 0;\n\tpmlmepriv->vhtpriv.vht_option = _FALSE;\n\n\tif (pmlmepriv->htpriv.ht_option == _TRUE\n\t\t&& pbss_network->Configuration.DSConfig > 14\n\t\t&& REGSTY_IS_11AC_ENABLE(pregistrypriv)\n\t\t&& is_supported_vht(pregistrypriv->wireless_mode)\n\t\t&& (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))\n\t) {\n\t\t/* Parsing VHT CAP IE */\n\t\tp = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));\n\t\tif (p && ie_len > 0)\n\t\t\tvht_cap = _TRUE;\n\n\t\t/* Parsing VHT OPERATION IE */\n\n\t\tif (vht_cap == _TRUE\n\t\t\t&& MLME_IS_MESH(padapter) /* allow only mesh temporarily before VHT IE checking is ready */\n\t\t) {\n\t\t\trtw_check_for_vht20(padapter, ie + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_);\n\t\t\tpmlmepriv->ori_vht_en = 1;\n\t\t\tpmlmepriv->vhtpriv.vht_option = _TRUE;\n\t\t} else if (REGSTY_IS_11AC_AUTO(pregistrypriv)) {\n\t\t\trtw_vht_ies_detach(padapter, pbss_network);\n\t\t\trtw_vht_ies_attach(padapter, pbss_network);\n\t\t}\n\t}\n\n\tif (pmlmepriv->vhtpriv.vht_option == _FALSE)\n\t\trtw_vht_ies_detach(padapter, pbss_network);\n#endif /* CONFIG_80211AC_VHT */\n\n#ifdef CONFIG_80211N_HT\n\tif(padapter->registrypriv.ht_enable &&\n\t\t\t\t\tis_supported_ht(padapter->registrypriv.wireless_mode) &&\n\t\tpbss_network->Configuration.DSConfig <= 14 && padapter->registrypriv.wifi_spec == 1 &&\n\t\tpbss_network->IELength + 10 <= MAX_IE_SZ) {\n\t\tuint len = 0;\n\n\t\tSET_EXT_CAPABILITY_ELE_BSS_COEXIST(pmlmepriv->ext_capab_ie_data, 1);\n\t\tpmlmepriv->ext_capab_ie_len = 10;\n\t\trtw_set_ie(pbss_network->IEs + pbss_network->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len);\n\t\tpbss_network->IELength += pmlmepriv->ext_capab_ie_len;\n\t}\n#endif /* CONFIG_80211N_HT */\n\n\tpbss_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pbss_network);\n\n\trtw_ies_get_chbw(pbss_network->IEs + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_\n\t\t, &pmlmepriv->ori_ch, &pmlmepriv->ori_bw, &pmlmepriv->ori_offset, 1, 1);\n\trtw_warn_on(pmlmepriv->ori_ch == 0);\n\n\t{\n\t\t/* alloc sta_info for ap itself */\n\n\t\tstruct sta_info *sta;\n\n\t\tsta = rtw_get_stainfo(&padapter->stapriv, pbss_network->MacAddress);\n\t\tif (!sta) {\n\t\t\tsta = rtw_alloc_stainfo(&padapter->stapriv, pbss_network->MacAddress);\n\t\t\tif (sta == NULL)\n\t\t\t\treturn _FAIL;\n\t\t}\n\t}\n\n\trtw_startbss_cmd(padapter, RTW_CMDF_WAIT_ACK);\n\t{\n\t\tint sk_band = RTW_GET_SCAN_BAND_SKIP(padapter);\n\n\t\tif (sk_band)\n\t\t\tRTW_CLR_SCAN_BAND_SKIP(padapter, sk_band);\n\t}\n\n\trtw_indicate_connect(padapter);\n\n\tpmlmepriv->cur_network.join_res = _TRUE;/* for check if already set beacon */\n\n\t/* update bc/mc sta_info */\n\t/* update_bmc_sta(padapter); */\n\n\treturn ret;\n\n}\n\n#if CONFIG_RTW_MACADDR_ACL\nvoid rtw_macaddr_acl_init(_adapter *adapter, u8 period)\n{\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct wlan_acl_pool *acl;\n\t_queue *acl_node_q;\n\tint i;\n\t_irqL irqL;\n\n\tif (period >= RTW_ACL_PERIOD_NUM) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tacl = &stapriv->acl_list[period];\n\tacl_node_q = &acl->acl_node_q;\n\n\t_rtw_spinlock_init(&(acl_node_q->lock));\n\n\t_enter_critical_bh(&(acl_node_q->lock), &irqL);\n\t_rtw_init_listhead(&(acl_node_q->queue));\n\tacl->num = 0;\n\tacl->mode = RTW_ACL_MODE_DISABLED;\n\tfor (i = 0; i < NUM_ACL; i++) {\n\t\t_rtw_init_listhead(&acl->aclnode[i].list);\n\t\tacl->aclnode[i].valid = _FALSE;\n\t}\n\t_exit_critical_bh(&(acl_node_q->lock), &irqL);\n}\n\nstatic void _rtw_macaddr_acl_deinit(_adapter *adapter, u8 period, bool clear_only)\n{\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct wlan_acl_pool *acl;\n\t_queue *acl_node_q;\n\t_irqL irqL;\n\t_list *head, *list;\n\tstruct rtw_wlan_acl_node *acl_node;\n\n\tif (period >= RTW_ACL_PERIOD_NUM) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tacl = &stapriv->acl_list[period];\n\tacl_node_q = &acl->acl_node_q;\n\n\t_enter_critical_bh(&(acl_node_q->lock), &irqL);\n\thead = get_list_head(acl_node_q);\n\tlist = get_next(head);\n\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\tacl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list);\n\t\tlist = get_next(list);\n\n\t\tif (acl_node->valid == _TRUE) {\n\t\t\tacl_node->valid = _FALSE;\n\t\t\trtw_list_delete(&acl_node->list);\n\t\t\tacl->num--;\n\t\t}\n\t}\n\t_exit_critical_bh(&(acl_node_q->lock), &irqL);\n\n\tif (!clear_only)\n\t\t_rtw_spinlock_free(&(acl_node_q->lock));\n\n\trtw_warn_on(acl->num);\n\tacl->mode = RTW_ACL_MODE_DISABLED;\n}\n\nvoid rtw_macaddr_acl_deinit(_adapter *adapter, u8 period)\n{\n\t_rtw_macaddr_acl_deinit(adapter, period, 0);\n}\n\nvoid rtw_macaddr_acl_clear(_adapter *adapter, u8 period)\n{\n\t_rtw_macaddr_acl_deinit(adapter, period, 1);\n}\n\nvoid rtw_set_macaddr_acl(_adapter *adapter, u8 period, int mode)\n{\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct wlan_acl_pool *acl;\n\n\tif (period >= RTW_ACL_PERIOD_NUM) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tacl = &stapriv->acl_list[period];\n\n\tRTW_INFO(FUNC_ADPT_FMT\" p=%u, mode=%d\\n\"\n\t\t, FUNC_ADPT_ARG(adapter), period, mode);\n\n\tacl->mode = mode;\n}\n\nint rtw_acl_add_sta(_adapter *adapter, u8 period, const u8 *addr)\n{\n\t_irqL irqL;\n\t_list *list, *head;\n\tu8 existed = 0;\n\tint i = -1, ret = 0;\n\tstruct rtw_wlan_acl_node *acl_node;\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct wlan_acl_pool *acl;\n\t_queue *acl_node_q;\n\n\tif (period >= RTW_ACL_PERIOD_NUM) {\n\t\trtw_warn_on(1);\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\n\tacl = &stapriv->acl_list[period];\n\tacl_node_q = &acl->acl_node_q;\n\n\t_enter_critical_bh(&(acl_node_q->lock), &irqL);\n\n\thead = get_list_head(acl_node_q);\n\tlist = get_next(head);\n\n\t/* search for existed entry */\n\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\tacl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list);\n\t\tlist = get_next(list);\n\n\t\tif (_rtw_memcmp(acl_node->addr, addr, ETH_ALEN)) {\n\t\t\tif (acl_node->valid == _TRUE) {\n\t\t\t\texisted = 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\tif (existed)\n\t\tgoto release_lock;\n\n\tif (acl->num >= NUM_ACL)\n\t\tgoto release_lock;\n\n\t/* find empty one and use */\n\tfor (i = 0; i < NUM_ACL; i++) {\n\n\t\tacl_node = &acl->aclnode[i];\n\t\tif (acl_node->valid == _FALSE) {\n\n\t\t\t_rtw_init_listhead(&acl_node->list);\n\t\t\t_rtw_memcpy(acl_node->addr, addr, ETH_ALEN);\n\t\t\tacl_node->valid = _TRUE;\n\n\t\t\trtw_list_insert_tail(&acl_node->list, get_list_head(acl_node_q));\n\t\t\tacl->num++;\n\t\t\tbreak;\n\t\t}\n\t}\n\nrelease_lock:\n\t_exit_critical_bh(&(acl_node_q->lock), &irqL);\n\n\tif (!existed && (i < 0 || i >= NUM_ACL))\n\t\tret = -1;\n\n\tRTW_INFO(FUNC_ADPT_FMT\" p=%u \"MAC_FMT\" %s (acl_num=%d)\\n\"\n\t\t , FUNC_ADPT_ARG(adapter), period, MAC_ARG(addr)\n\t\t, (existed ? \"existed\" : ((i < 0 || i >= NUM_ACL) ? \"no room\" : \"added\"))\n\t\t , acl->num);\nexit:\n\treturn ret;\n}\n\nint rtw_acl_remove_sta(_adapter *adapter, u8 period, const u8 *addr)\n{\n\t_irqL irqL;\n\t_list *list, *head;\n\tint ret = 0;\n\tstruct rtw_wlan_acl_node *acl_node;\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct wlan_acl_pool *acl;\n\t_queue\t*acl_node_q;\n\tu8 is_baddr = is_broadcast_mac_addr(addr);\n\tu8 match = 0;\n\n\tif (period >= RTW_ACL_PERIOD_NUM) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tacl = &stapriv->acl_list[period];\n\tacl_node_q = &acl->acl_node_q;\n\n\t_enter_critical_bh(&(acl_node_q->lock), &irqL);\n\n\thead = get_list_head(acl_node_q);\n\tlist = get_next(head);\n\n\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\tacl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list);\n\t\tlist = get_next(list);\n\n\t\tif (is_baddr || _rtw_memcmp(acl_node->addr, addr, ETH_ALEN)) {\n\t\t\tif (acl_node->valid == _TRUE) {\n\t\t\t\tacl_node->valid = _FALSE;\n\t\t\t\trtw_list_delete(&acl_node->list);\n\t\t\t\tacl->num--;\n\t\t\t\tmatch = 1;\n\t\t\t}\n\t\t}\n\t}\n\n\t_exit_critical_bh(&(acl_node_q->lock), &irqL);\n\n\tRTW_INFO(FUNC_ADPT_FMT\" p=%u \"MAC_FMT\" %s (acl_num=%d)\\n\"\n\t\t , FUNC_ADPT_ARG(adapter), period, MAC_ARG(addr)\n\t\t , is_baddr ? \"clear all\" : (match ? \"match\" : \"no found\")\n\t\t , acl->num);\n\nexit:\n\treturn ret;\n}\n#endif /* CONFIG_RTW_MACADDR_ACL */\n\nu8 rtw_ap_set_sta_key(_adapter *adapter, const u8 *addr, u8 alg, const u8 *key, u8 keyid, u8 gk)\n{\n\tstruct cmd_priv *cmdpriv = &adapter->cmdpriv;\n\tstruct cmd_obj *cmd;\n\tstruct set_stakey_parm *param;\n\tu8\tres = _SUCCESS;\n\n\tcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (cmd == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tparam = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm));\n\tif (param == NULL) {\n\t\trtw_mfree((u8 *) cmd, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tinit_h2fwcmd_w_parm_no_rsp(cmd, param, _SetStaKey_CMD_);\n\n\t_rtw_memcpy(param->addr, addr, ETH_ALEN);\n\tparam->algorithm = alg;\n\tparam->keyid = keyid;\n\t_rtw_memcpy(param->key, key, 16);\n\tparam->gk = gk;\n\n\tres = rtw_enqueue_cmd(cmdpriv, cmd);\n\nexit:\n\treturn res;\n}\n\nu8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta)\n{\n\treturn rtw_ap_set_sta_key(padapter\n\t\t, psta->cmn.mac_addr\n\t\t, psta->dot118021XPrivacy\n\t\t, psta->dot118021x_UncstKey.skey\n\t\t, 0\n\t\t, 0\n\t);\n}\n\nstatic int rtw_ap_set_key(_adapter *padapter, u8 *key, u8 alg, int keyid, u8 set_tx)\n{\n\tu8 keylen;\n\tstruct cmd_obj *pcmd;\n\tstruct setkey_parm *psetkeyparm;\n\tstruct cmd_priv\t*pcmdpriv = &(padapter->cmdpriv);\n\tint res = _SUCCESS;\n\n\t/* RTW_INFO(\"%s\\n\", __FUNCTION__); */\n\n\tpcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (pcmd == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tpsetkeyparm = (struct setkey_parm *)rtw_zmalloc(sizeof(struct setkey_parm));\n\tif (psetkeyparm == NULL) {\n\t\trtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t_rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm));\n\n\tpsetkeyparm->keyid = (u8)keyid;\n\tif (is_wep_enc(alg))\n\t\tpadapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid);\n\n\tpsetkeyparm->algorithm = alg;\n\n\tpsetkeyparm->set_tx = set_tx;\n\n\tswitch (alg) {\n\tcase _WEP40_:\n\t\tkeylen = 5;\n\t\tbreak;\n\tcase _WEP104_:\n\t\tkeylen = 13;\n\t\tbreak;\n\tcase _TKIP_:\n\tcase _TKIP_WTMIC_:\n\tcase _AES_:\n\tdefault:\n\t\tkeylen = 16;\n\t}\n\n\t_rtw_memcpy(&(psetkeyparm->key[0]), key, keylen);\n\n\tpcmd->cmdcode = _SetKey_CMD_;\n\tpcmd->parmbuf = (u8 *)psetkeyparm;\n\tpcmd->cmdsz = (sizeof(struct setkey_parm));\n\tpcmd->rsp = NULL;\n\tpcmd->rspsz = 0;\n\n\n\t_rtw_init_listhead(&pcmd->list);\n\n\tres = rtw_enqueue_cmd(pcmdpriv, pcmd);\n\nexit:\n\n\treturn res;\n}\n\nint rtw_ap_set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid)\n{\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\treturn rtw_ap_set_key(padapter, key, alg, keyid, 1);\n}\n\nint rtw_ap_set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid, u8 set_tx)\n{\n\tu8 alg;\n\n\tswitch (keylen) {\n\tcase 5:\n\t\talg = _WEP40_;\n\t\tbreak;\n\tcase 13:\n\t\talg = _WEP104_;\n\t\tbreak;\n\tdefault:\n\t\talg = _NO_PRIVACY_;\n\t}\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\treturn rtw_ap_set_key(padapter, key, alg, keyid, set_tx);\n}\n\nu8 rtw_ap_bmc_frames_hdl(_adapter *padapter)\n{\n#define HIQ_XMIT_COUNTS (6)\n\t_irqL irqL;\n\tstruct sta_info *psta_bmc;\n\t_list\t*xmitframe_plist, *xmitframe_phead;\n\tstruct xmit_frame *pxmitframe = NULL;\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tstruct sta_priv  *pstapriv = &padapter->stapriv;\n\tbool update_tim = _FALSE;\n\n\n\tif (padapter->registrypriv.wifi_spec != 1)\n\t\treturn H2C_SUCCESS;\n\n\n\tpsta_bmc = rtw_get_bcmc_stainfo(padapter);\n\tif (!psta_bmc)\n\t\treturn H2C_SUCCESS;\n\n\n\t_enter_critical_bh(&pxmitpriv->lock, &irqL);\n\n\tif ((rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) && (psta_bmc->sleepq_len > 0)) {\n\t\tint tx_counts = 0;\n\n\t\t_update_beacon(padapter, _TIM_IE_, NULL, _FALSE, 0, \"update TIM with TIB=1\");\n\n\t\tRTW_INFO(\"sleepq_len of bmc_sta = %d\\n\", psta_bmc->sleepq_len);\n\n\t\txmitframe_phead = get_list_head(&psta_bmc->sleep_q);\n\t\txmitframe_plist = get_next(xmitframe_phead);\n\n\t\twhile ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {\n\t\t\tpxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);\n\n\t\t\txmitframe_plist = get_next(xmitframe_plist);\n\n\t\t\trtw_list_delete(&pxmitframe->list);\n\n\t\t\tpsta_bmc->sleepq_len--;\n\t\t\ttx_counts++;\n\n\t\t\tif (psta_bmc->sleepq_len > 0)\n\t\t\t\tpxmitframe->attrib.mdata = 1;\n\t\t\telse\n\t\t\t\tpxmitframe->attrib.mdata = 0;\n\n\t\t\tif (tx_counts == HIQ_XMIT_COUNTS)\n\t\t\t\tpxmitframe->attrib.mdata = 0;\n\n\t\t\tpxmitframe->attrib.triggered = 1;\n\n\t\t\tif (xmitframe_hiq_filter(pxmitframe) == _TRUE)\n\t\t\t\tpxmitframe->attrib.qsel = QSLT_HIGH;/*HIQ*/\n\n\t\t\trtw_hal_xmitframe_enqueue(padapter, pxmitframe);\n\n\t\t\tif (tx_counts == HIQ_XMIT_COUNTS)\n\t\t\t\tbreak;\n\n\t\t}\n\n\t} else {\n\t\tif (psta_bmc->sleepq_len == 0) {\n\n\t\t\t/*RTW_INFO(\"sleepq_len of bmc_sta = %d\\n\", psta_bmc->sleepq_len);*/\n\n\t\t\tif (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0))\n\t\t\t\tupdate_tim = _TRUE;\n\n\t\t\trtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0);\n\t\t\trtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0);\n\n\t\t\tif (update_tim == _TRUE) {\n\t\t\t\tRTW_INFO(\"clear TIB\\n\");\n\t\t\t\t_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, \"bmc sleepq and HIQ empty\");\n\t\t\t}\n\t\t}\n\t}\n\n\t_exit_critical_bh(&pxmitpriv->lock, &irqL);\n\n#if 0\n\t/* HIQ Check */\n\trtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty);\n\n\twhile (_FALSE == empty && rtw_get_passing_time_ms(start) < 3000) {\n\t\trtw_msleep_os(100);\n\t\trtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty);\n\t}\n\n\n\tprintk(\"check if hiq empty=%d\\n\", empty);\n#endif\n\n\treturn H2C_SUCCESS;\n}\n\n#ifdef CONFIG_NATIVEAP_MLME\n\nstatic void associated_stainfo_update(_adapter *padapter, struct sta_info *psta, u32 sta_info_type)\n{\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\tRTW_INFO(\"%s: \"MAC_FMT\", updated_type=0x%x\\n\", __func__, MAC_ARG(psta->cmn.mac_addr), sta_info_type);\n#ifdef CONFIG_80211N_HT\n\tif (sta_info_type & STA_INFO_UPDATE_BW) {\n\n\t\tif ((psta->flags & WLAN_STA_HT) && !psta->ht_20mhz_set) {\n\t\t\tif (pmlmepriv->sw_to_20mhz) {\n\t\t\t\tpsta->cmn.bw_mode = CHANNEL_WIDTH_20;\n\t\t\t\t/*psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;*/\n\t\t\t\tpsta->htpriv.sgi_40m = _FALSE;\n\t\t\t} else {\n\t\t\t\t/*TODO: Switch back to 40MHZ?80MHZ*/\n\t\t\t}\n\t\t}\n\t}\n#endif /* CONFIG_80211N_HT */\n\t/*\n\t\tif (sta_info_type & STA_INFO_UPDATE_RATE) {\n\n\t\t}\n\t*/\n\n\tif (sta_info_type & STA_INFO_UPDATE_PROTECTION_MODE)\n\t\tVCS_update(padapter, psta);\n\n\t/*\n\t\tif (sta_info_type & STA_INFO_UPDATE_CAP) {\n\n\t\t}\n\n\t\tif (sta_info_type & STA_INFO_UPDATE_HT_CAP) {\n\n\t\t}\n\n\t\tif (sta_info_type & STA_INFO_UPDATE_VHT_CAP) {\n\n\t\t}\n\t*/\n\n}\n\nstatic void update_bcn_ext_capab_ie(_adapter *padapter)\n{\n\tsint ie_len = 0;\n\tunsigned char\t*pbuf;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);\n\tu8 *ie = pnetwork->IEs;\n\tu8 null_extcap_data[8] = {0};\n\n\tpbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_CAP_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));\n\tif (pbuf && ie_len > 0)\n\t\trtw_remove_bcn_ie(padapter, pnetwork, _EXT_CAP_IE_);\n\n\tif ((pmlmepriv->ext_capab_ie_len > 0) &&\n\t    (_rtw_memcmp(pmlmepriv->ext_capab_ie_data, null_extcap_data, sizeof(null_extcap_data)) == _FALSE))\n\t\trtw_add_bcn_ie(padapter, pnetwork, _EXT_CAP_IE_, pmlmepriv->ext_capab_ie_data, pmlmepriv->ext_capab_ie_len);\n\n}\n\nstatic void update_bcn_erpinfo_ie(_adapter *padapter)\n{\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);\n\tunsigned char *p, *ie = pnetwork->IEs;\n\tu32 len = 0;\n\n\tRTW_INFO(\"%s, ERP_enable=%d\\n\", __FUNCTION__, pmlmeinfo->ERP_enable);\n\n\tif (!pmlmeinfo->ERP_enable)\n\t\treturn;\n\n\t/* parsing ERP_IE */\n\tp = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &len, (pnetwork->IELength - _BEACON_IE_OFFSET_));\n\tif (p && len > 0) {\n\t\tPNDIS_802_11_VARIABLE_IEs pIE = (PNDIS_802_11_VARIABLE_IEs)p;\n\n\t\tif (pmlmepriv->num_sta_non_erp == 1)\n\t\t\tpIE->data[0] |= RTW_ERP_INFO_NON_ERP_PRESENT | RTW_ERP_INFO_USE_PROTECTION;\n\t\telse\n\t\t\tpIE->data[0] &= ~(RTW_ERP_INFO_NON_ERP_PRESENT | RTW_ERP_INFO_USE_PROTECTION);\n\n\t\tif (pmlmepriv->num_sta_no_short_preamble > 0)\n\t\t\tpIE->data[0] |= RTW_ERP_INFO_BARKER_PREAMBLE_MODE;\n\t\telse\n\t\t\tpIE->data[0] &= ~(RTW_ERP_INFO_BARKER_PREAMBLE_MODE);\n\n\t\tERP_IE_handler(padapter, pIE);\n\t}\n\n}\n\nstatic void update_bcn_htcap_ie(_adapter *padapter)\n{\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n}\n\nstatic void update_bcn_htinfo_ie(_adapter *padapter)\n{\n#ifdef CONFIG_80211N_HT\n\t/*\n\tu8 beacon_updated = _FALSE;\n\tu32 sta_info_update_type = STA_INFO_UPDATE_NONE;\n\t*/\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);\n\tunsigned char *p, *ie = pnetwork->IEs;\n\tu32 len = 0;\n\n\tif (pmlmepriv->htpriv.ht_option == _FALSE)\n\t\treturn;\n\n\tif (pmlmeinfo->HT_info_enable != 1)\n\t\treturn;\n\n\n\tRTW_INFO(\"%s current operation mode=0x%X\\n\",\n\t\t __FUNCTION__, pmlmepriv->ht_op_mode);\n\n\tRTW_INFO(\"num_sta_40mhz_intolerant(%d), 20mhz_width_req(%d), intolerant_ch_rpt(%d), olbc(%d)\\n\",\n\t\tpmlmepriv->num_sta_40mhz_intolerant, pmlmepriv->ht_20mhz_width_req, pmlmepriv->ht_intolerant_ch_reported, ATOMIC_READ(&pmlmepriv->olbc));\n\n\t/*parsing HT_INFO_IE, currently only update ht_op_mode - pht_info->infos[1] & pht_info->infos[2] for wifi logo test*/\n\tp = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &len, (pnetwork->IELength - _BEACON_IE_OFFSET_));\n\tif (p && len > 0) {\n\t\tstruct HT_info_element *pht_info = NULL;\n\n\t\tpht_info = (struct HT_info_element *)(p + 2);\n\n\t\t/* for STA Channel Width/Secondary Channel Offset*/\n\t\tif ((pmlmepriv->sw_to_20mhz == 0) && (pmlmeext->cur_channel <= 14)) {\n\t\t\tif ((pmlmepriv->num_sta_40mhz_intolerant > 0) || (pmlmepriv->ht_20mhz_width_req == _TRUE)\n\t\t\t    || (pmlmepriv->ht_intolerant_ch_reported == _TRUE) || (ATOMIC_READ(&pmlmepriv->olbc) == _TRUE)) {\n\t\t\t\tSET_HT_OP_ELE_2ND_CHL_OFFSET(pht_info, 0);\n\t\t\t\tSET_HT_OP_ELE_STA_CHL_WIDTH(pht_info, 0);\n\n\t\t\t\tpmlmepriv->sw_to_20mhz = 1;\n\t\t\t\t/*\n\t\t\t\tsta_info_update_type |= STA_INFO_UPDATE_BW;\n\t\t\t\tbeacon_updated = _TRUE;\n\t\t\t\t*/\n\n\t\t\t\tRTW_INFO(\"%s:switching to 20Mhz\\n\", __FUNCTION__);\n\n\t\t\t\t/*TODO : cur_bwmode/cur_ch_offset switches to 20Mhz*/\n\t\t\t}\n\t\t} else {\n\n\t\t\tif ((pmlmepriv->num_sta_40mhz_intolerant == 0) && (pmlmepriv->ht_20mhz_width_req == _FALSE)\n\t\t\t    && (pmlmepriv->ht_intolerant_ch_reported == _FALSE) && (ATOMIC_READ(&pmlmepriv->olbc) == _FALSE)) {\n\n\t\t\t\tif (pmlmeext->cur_bwmode >= CHANNEL_WIDTH_40) {\n\n\t\t\t\t\tSET_HT_OP_ELE_STA_CHL_WIDTH(pht_info, 1);\n\n\t\t\t\t\tSET_HT_OP_ELE_2ND_CHL_OFFSET(pht_info,\n\t\t\t\t\t\t(pmlmeext->cur_ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) ?\n\t\t\t\t\t\tHT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE : HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW);\n\n\t\t\t\t\tpmlmepriv->sw_to_20mhz = 0;\n\t\t\t\t\t/*\n\t\t\t\t\tsta_info_update_type |= STA_INFO_UPDATE_BW;\n\t\t\t\t\tbeacon_updated = _TRUE;\n\t\t\t\t\t*/\n\n\t\t\t\t\tRTW_INFO(\"%s:switching back to 40Mhz\\n\", __FUNCTION__);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/* to update  ht_op_mode*/\n\t\t*(u16 *)(pht_info->infos + 1) = cpu_to_le16(pmlmepriv->ht_op_mode);\n\n\t}\n\n\t/*associated_clients_update(padapter, beacon_updated, sta_info_update_type);*/\n#endif /* CONFIG_80211N_HT */\n}\n\nstatic void update_bcn_rsn_ie(_adapter *padapter)\n{\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n}\n\nstatic void update_bcn_wpa_ie(_adapter *padapter)\n{\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n}\n\nstatic void update_bcn_wmm_ie(_adapter *padapter)\n{\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n}\n\nstatic void update_bcn_wps_ie(_adapter *padapter)\n{\n\tu8 *pwps_ie = NULL, *pwps_ie_src, *premainder_ie, *pbackup_remainder_ie = NULL;\n\tuint wps_ielen = 0, wps_offset, remainder_ielen;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);\n\tunsigned char *ie = pnetwork->IEs;\n\tu32 ielen = pnetwork->IELength;\n\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\tpwps_ie = rtw_get_wps_ie(ie + _FIXED_IE_LENGTH_, ielen - _FIXED_IE_LENGTH_, NULL, &wps_ielen);\n\n\tif (pwps_ie == NULL || wps_ielen == 0)\n\t\treturn;\n\n\tpwps_ie_src = pmlmepriv->wps_beacon_ie;\n\tif (pwps_ie_src == NULL)\n\t\treturn;\n\n\twps_offset = (uint)(pwps_ie - ie);\n\n\tpremainder_ie = pwps_ie + wps_ielen;\n\n\tremainder_ielen = ielen - wps_offset - wps_ielen;\n\n\tif (remainder_ielen > 0) {\n\t\tpbackup_remainder_ie = rtw_malloc(remainder_ielen);\n\t\tif (pbackup_remainder_ie)\n\t\t\t_rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);\n\t}\n\n\twps_ielen = (uint)pwps_ie_src[1];/* to get ie data len */\n\tif ((wps_offset + wps_ielen + 2 + remainder_ielen) <= MAX_IE_SZ) {\n\t\t_rtw_memcpy(pwps_ie, pwps_ie_src, wps_ielen + 2);\n\t\tpwps_ie += (wps_ielen + 2);\n\n\t\tif (pbackup_remainder_ie)\n\t\t\t_rtw_memcpy(pwps_ie, pbackup_remainder_ie, remainder_ielen);\n\n\t\t/* update IELength */\n\t\tpnetwork->IELength = wps_offset + (wps_ielen + 2) + remainder_ielen;\n\t}\n\n\tif (pbackup_remainder_ie)\n\t\trtw_mfree(pbackup_remainder_ie, remainder_ielen);\n\n\t/* deal with the case without set_tx_beacon_cmd() in update_beacon() */\n#if defined(CONFIG_INTERRUPT_BASED_TXBCN) || defined(CONFIG_PCI_HCI)\n\tif ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {\n\t\tu8 sr = 0;\n\t\trtw_get_wps_attr_content(pwps_ie_src,  wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);\n\n\t\tif (sr) {\n\t\t\tset_fwstate(pmlmepriv, WIFI_UNDER_WPS);\n\t\t\tRTW_INFO(\"%s, set WIFI_UNDER_WPS\\n\", __func__);\n\t\t} else {\n\t\t\tclr_fwstate(pmlmepriv, WIFI_UNDER_WPS);\n\t\t\tRTW_INFO(\"%s, clr WIFI_UNDER_WPS\\n\", __func__);\n\t\t}\n\t}\n#endif\n}\n\nstatic void update_bcn_p2p_ie(_adapter *padapter)\n{\n\n}\n\nstatic void update_bcn_vendor_spec_ie(_adapter *padapter, u8 *oui)\n{\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\tif (_rtw_memcmp(RTW_WPA_OUI, oui, 4))\n\t\tupdate_bcn_wpa_ie(padapter);\n\telse if (_rtw_memcmp(WMM_OUI, oui, 4))\n\t\tupdate_bcn_wmm_ie(padapter);\n\telse if (_rtw_memcmp(WPS_OUI, oui, 4))\n\t\tupdate_bcn_wps_ie(padapter);\n\telse if (_rtw_memcmp(P2P_OUI, oui, 4))\n\t\tupdate_bcn_p2p_ie(padapter);\n\telse\n\t\tRTW_INFO(\"unknown OUI type!\\n\");\n\n\n}\n\nvoid _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, u8 flags, const char *tag)\n{\n\t_irqL irqL;\n\tstruct mlme_priv *pmlmepriv;\n\tstruct mlme_ext_priv *pmlmeext;\n\tbool updated = 1; /* treat as upadated by default */\n\n\tif (!padapter)\n\t\treturn;\n\n\tpmlmepriv = &(padapter->mlmepriv);\n\tpmlmeext = &(padapter->mlmeextpriv);\n\n\tif (pmlmeext->bstart_bss == _FALSE)\n\t\treturn;\n\n\t_enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);\n\n\tswitch (ie_id) {\n\tcase _TIM_IE_:\n\t\tupdate_BCNTIM(padapter);\n\t\tbreak;\n\n\tcase _ERPINFO_IE_:\n\t\tupdate_bcn_erpinfo_ie(padapter);\n\t\tbreak;\n\n\tcase _HT_CAPABILITY_IE_:\n\t\tupdate_bcn_htcap_ie(padapter);\n\t\tbreak;\n\n\tcase _RSN_IE_2_:\n\t\tupdate_bcn_rsn_ie(padapter);\n\t\tbreak;\n\n\tcase _HT_ADD_INFO_IE_:\n\t\tupdate_bcn_htinfo_ie(padapter);\n\t\tbreak;\n\n\tcase _EXT_CAP_IE_:\n\t\tupdate_bcn_ext_capab_ie(padapter);\n\t\tbreak;\n\n#ifdef CONFIG_RTW_MESH\n\tcase WLAN_EID_MESH_CONFIG:\n\t\tupdated = rtw_mesh_update_bss_peering_status(padapter, &(pmlmeext->mlmext_info.network));\n\t\tupdated |= rtw_mesh_update_bss_formation_info(padapter, &(pmlmeext->mlmext_info.network));\n\t\tupdated |= rtw_mesh_update_bss_forwarding_state(padapter, &(pmlmeext->mlmext_info.network));\n\t\tbreak;\n#endif\n\n\tcase _VENDOR_SPECIFIC_IE_:\n\t\tupdate_bcn_vendor_spec_ie(padapter, oui);\n\t\tbreak;\n\n\tcase 0xFF:\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (updated)\n\t\tpmlmepriv->update_bcn = _TRUE;\n\n\t_exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);\n\n#ifndef CONFIG_INTERRUPT_BASED_TXBCN\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_PCI_BCN_POLLING)\n\tif (tx && updated) {\n\t\t/* send_beacon(padapter); */ /* send_beacon must execute on TSR level */\n\t\tif (0)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" ie_id:%u - %s\\n\", FUNC_ADPT_ARG(padapter), ie_id, tag);\n\t\tif(flags == RTW_CMDF_WAIT_ACK)\n\t\t\tset_tx_beacon_cmd(padapter, RTW_CMDF_WAIT_ACK);\n\t\telse\n\t\t\tset_tx_beacon_cmd(padapter, 0);\n\t}\n#else\n\t{\n\t\t/* PCI will issue beacon when BCN interrupt occurs.\t\t */\n\t}\n#endif\n#endif /* !CONFIG_INTERRUPT_BASED_TXBCN */\n}\n\n#ifdef CONFIG_80211N_HT\n\nvoid rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_len)\n{\n\tstruct sta_info *psta;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tu8 beacon_updated = _FALSE;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tu8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);\n\tuint frame_body_len = frame_len - sizeof(struct rtw_ieee80211_hdr_3addr);\n\tu8 category, action;\n\n\tpsta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));\n\tif (psta == NULL)\n\t\treturn;\n\n\n\tcategory = frame_body[0];\n\taction = frame_body[1];\n\n\tif (frame_body_len > 0) {\n\t\tif ((frame_body[2] == EID_BSSCoexistence) && (frame_body[3] > 0)) {\n\t\t\tu8 ie_data = frame_body[4];\n\n\t\t\tif (ie_data & RTW_WLAN_20_40_BSS_COEX_40MHZ_INTOL) {\n\t\t\t\tif (psta->ht_40mhz_intolerant == 0) {\n\t\t\t\t\tpsta->ht_40mhz_intolerant = 1;\n\t\t\t\t\tpmlmepriv->num_sta_40mhz_intolerant++;\n\t\t\t\t\tbeacon_updated = _TRUE;\n\t\t\t\t}\n\t\t\t} else if (ie_data & RTW_WLAN_20_40_BSS_COEX_20MHZ_WIDTH_REQ)\t{\n\t\t\t\tif (pmlmepriv->ht_20mhz_width_req == _FALSE) {\n\t\t\t\t\tpmlmepriv->ht_20mhz_width_req = _TRUE;\n\t\t\t\t\tbeacon_updated = _TRUE;\n\t\t\t\t}\n\t\t\t} else\n\t\t\t\tbeacon_updated = _FALSE;\n\t\t}\n\t}\n\n\tif (frame_body_len > 8) {\n\t\t/* if EID_BSSIntolerantChlReport ie exists */\n\t\tif ((frame_body[5] == EID_BSSIntolerantChlReport) && (frame_body[6] > 0)) {\n\t\t\t/*todo:*/\n\t\t\tif (pmlmepriv->ht_intolerant_ch_reported == _FALSE) {\n\t\t\t\tpmlmepriv->ht_intolerant_ch_reported = _TRUE;\n\t\t\t\tbeacon_updated = _TRUE;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (beacon_updated) {\n\n\t\tupdate_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE, 0);\n\n\t\tassociated_stainfo_update(padapter, psta, STA_INFO_UPDATE_BW);\n\t}\n\n\n\n}\n\nvoid rtw_process_ht_action_smps(_adapter *padapter, u8 *ta, u8 ctrl_field)\n{\n\tu8 e_field, m_field;\n\tstruct sta_info *psta;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\tpsta = rtw_get_stainfo(pstapriv, ta);\n\tif (psta == NULL)\n\t\treturn;\n\n\te_field = (ctrl_field & BIT(0)) ? 1 : 0; /*SM Power Save Enabled*/\n\tm_field = (ctrl_field & BIT(1)) ? 1 : 0; /*SM Mode, 0:static SMPS, 1:dynamic SMPS*/\n\n\tif (e_field) {\n\t\tif (m_field) { /*mode*/\n\t\t\tpsta->htpriv.smps_cap = WLAN_HT_CAP_SM_PS_DYNAMIC;\n\t\t\tRTW_ERR(\"Don't support dynamic SMPS\\n\");\n\t\t}\n\t\telse\n\t\t\tpsta->htpriv.smps_cap = WLAN_HT_CAP_SM_PS_STATIC;\n\t} else {\n\t\t/*disable*/\n\t\tpsta->htpriv.smps_cap = WLAN_HT_CAP_SM_PS_DISABLED;\n\t}\n\n\tif (psta->htpriv.smps_cap != WLAN_HT_CAP_SM_PS_DYNAMIC)\n\t\trtw_ssmps_wk_cmd(padapter, psta, e_field, 1);\n}\n\n/*\nop_mode\nSet to 0 (HT pure) under the followign conditions\n\t- all STAs in the BSS are 20/40 MHz HT in 20/40 MHz BSS or\n\t- all STAs in the BSS are 20 MHz HT in 20 MHz BSS\nSet to 1 (HT non-member protection) if there may be non-HT STAs\n\tin both the primary and the secondary channel\nSet to 2 if only HT STAs are associated in BSS,\n\thowever and at least one 20 MHz HT STA is associated\nSet to 3 (HT mixed mode) when one or more non-HT STAs are associated\n\t(currently non-GF HT station is considered as non-HT STA also)\n*/\nint rtw_ht_operation_update(_adapter *padapter)\n{\n\tu16 cur_op_mode, new_op_mode;\n\tint op_mode_changes = 0;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct ht_priv\t*phtpriv_ap = &pmlmepriv->htpriv;\n\n\tif (pmlmepriv->htpriv.ht_option == _FALSE)\n\t\treturn 0;\n\n\t/*if (!iface->conf->ieee80211n || iface->conf->ht_op_mode_fixed)\n\t\treturn 0;*/\n\n\tRTW_INFO(\"%s current operation mode=0x%X\\n\",\n\t\t __FUNCTION__, pmlmepriv->ht_op_mode);\n\n\tif (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)\n\t    && pmlmepriv->num_sta_ht_no_gf) {\n\t\tpmlmepriv->ht_op_mode |=\n\t\t\tHT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT;\n\t\top_mode_changes++;\n\t} else if ((pmlmepriv->ht_op_mode &\n\t\t    HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT) &&\n\t\t   pmlmepriv->num_sta_ht_no_gf == 0) {\n\t\tpmlmepriv->ht_op_mode &=\n\t\t\t~HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT;\n\t\top_mode_changes++;\n\t}\n\n\tif (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) &&\n\t    (pmlmepriv->num_sta_no_ht || ATOMIC_READ(&pmlmepriv->olbc_ht))) {\n\t\tpmlmepriv->ht_op_mode |= HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT;\n\t\top_mode_changes++;\n\t} else if ((pmlmepriv->ht_op_mode &\n\t\t    HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) &&\n\t\t   (pmlmepriv->num_sta_no_ht == 0 && !ATOMIC_READ(&pmlmepriv->olbc_ht))) {\n\t\tpmlmepriv->ht_op_mode &=\n\t\t\t~HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT;\n\t\top_mode_changes++;\n\t}\n\n\t/* Note: currently we switch to the MIXED op mode if HT non-greenfield\n\t * station is associated. Probably it's a theoretical case, since\n\t * it looks like all known HT STAs support greenfield.\n\t */\n\tnew_op_mode = 0;\n\tif (pmlmepriv->num_sta_no_ht /*||\n\t    (pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/)\n\t\tnew_op_mode = OP_MODE_MIXED;\n\telse if ((phtpriv_ap->ht_cap.cap_info & IEEE80211_HT_CAP_SUP_WIDTH)\n\t\t && pmlmepriv->num_sta_ht_20mhz)\n\t\tnew_op_mode = OP_MODE_20MHZ_HT_STA_ASSOCED;\n\telse if (ATOMIC_READ(&pmlmepriv->olbc_ht))\n\t\tnew_op_mode = OP_MODE_MAY_BE_LEGACY_STAS;\n\telse\n\t\tnew_op_mode = OP_MODE_PURE;\n\n\tcur_op_mode = pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_OP_MODE_MASK;\n\tif (cur_op_mode != new_op_mode) {\n\t\tpmlmepriv->ht_op_mode &= ~HT_INFO_OPERATION_MODE_OP_MODE_MASK;\n\t\tpmlmepriv->ht_op_mode |= new_op_mode;\n\t\top_mode_changes++;\n\t}\n\n\tRTW_INFO(\"%s new operation mode=0x%X changes=%d\\n\",\n\t\t __FUNCTION__, pmlmepriv->ht_op_mode, op_mode_changes);\n\n\treturn op_mode_changes;\n\n}\n\n#endif /* CONFIG_80211N_HT */\n\nvoid associated_clients_update(_adapter *padapter, u8 updated, u32 sta_info_type)\n{\n\t/* update associcated stations cap. */\n\tif (updated == _TRUE) {\n\t\t_irqL irqL;\n\t\t_list\t*phead, *plist;\n\t\tstruct sta_info *psta = NULL;\n\t\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\t\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\t\tphead = &pstapriv->asoc_list;\n\t\tplist = get_next(phead);\n\n\t\t/* check asoc_queue */\n\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);\n\n\t\t\tplist = get_next(plist);\n\n\t\t\tassociated_stainfo_update(padapter, psta, sta_info_type);\n\t\t}\n\n\t\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\t}\n\n}\n\n/* called > TSR LEVEL for USB or SDIO Interface*/\nvoid bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)\n{\n\tu8 beacon_updated = _FALSE;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n\n\n#if 0\n\tif (!(psta->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) &&\n\t    !psta->no_short_preamble_set) {\n\t\tpsta->no_short_preamble_set = 1;\n\t\tpmlmepriv->num_sta_no_short_preamble++;\n\t\tif ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&\n\t\t    (pmlmepriv->num_sta_no_short_preamble == 1))\n\t\t\tieee802_11_set_beacons(hapd->iface);\n\t}\n#endif\n\n\n\tif (!(psta->flags & WLAN_STA_SHORT_PREAMBLE)) {\n\t\tif (!psta->no_short_preamble_set) {\n\t\t\tpsta->no_short_preamble_set = 1;\n\n\t\t\tpmlmepriv->num_sta_no_short_preamble++;\n\n\t\t\tif ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&\n\t\t\t    (pmlmepriv->num_sta_no_short_preamble == 1))\n\t\t\t\tbeacon_updated = _TRUE;\n\t\t}\n\t} else {\n\t\tif (psta->no_short_preamble_set) {\n\t\t\tpsta->no_short_preamble_set = 0;\n\n\t\t\tpmlmepriv->num_sta_no_short_preamble--;\n\n\t\t\tif ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&\n\t\t\t    (pmlmepriv->num_sta_no_short_preamble == 0))\n\t\t\t\tbeacon_updated = _TRUE;\n\t\t}\n\t}\n\n#if 0\n\tif (psta->flags & WLAN_STA_NONERP && !psta->nonerp_set) {\n\t\tpsta->nonerp_set = 1;\n\t\tpmlmepriv->num_sta_non_erp++;\n\t\tif (pmlmepriv->num_sta_non_erp == 1)\n\t\t\tieee802_11_set_beacons(hapd->iface);\n\t}\n#endif\n\n\tif (psta->flags & WLAN_STA_NONERP) {\n\t\tif (!psta->nonerp_set) {\n\t\t\tpsta->nonerp_set = 1;\n\n\t\t\tpmlmepriv->num_sta_non_erp++;\n\n\t\t\tif (pmlmepriv->num_sta_non_erp == 1) {\n\t\t\t\tbeacon_updated = _TRUE;\n\t\t\t\tupdate_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE, 0);\n\t\t\t}\n\t\t}\n\n\t} else {\n\t\tif (psta->nonerp_set) {\n\t\t\tpsta->nonerp_set = 0;\n\n\t\t\tpmlmepriv->num_sta_non_erp--;\n\n\t\t\tif (pmlmepriv->num_sta_non_erp == 0) {\n\t\t\t\tbeacon_updated = _TRUE;\n\t\t\t\tupdate_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE, 0);\n\t\t\t}\n\t\t}\n\n\t}\n\n\n#if 0\n\tif (!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT) &&\n\t    !psta->no_short_slot_time_set) {\n\t\tpsta->no_short_slot_time_set = 1;\n\t\tpmlmepriv->num_sta_no_short_slot_time++;\n\t\tif ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&\n\t\t    (pmlmepriv->num_sta_no_short_slot_time == 1))\n\t\t\tieee802_11_set_beacons(hapd->iface);\n\t}\n#endif\n\n\tif (!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT)) {\n\t\tif (!psta->no_short_slot_time_set) {\n\t\t\tpsta->no_short_slot_time_set = 1;\n\n\t\t\tpmlmepriv->num_sta_no_short_slot_time++;\n\n\t\t\tif ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&\n\t\t\t    (pmlmepriv->num_sta_no_short_slot_time == 1))\n\t\t\t\tbeacon_updated = _TRUE;\n\t\t}\n\t} else {\n\t\tif (psta->no_short_slot_time_set) {\n\t\t\tpsta->no_short_slot_time_set = 0;\n\n\t\t\tpmlmepriv->num_sta_no_short_slot_time--;\n\n\t\t\tif ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&\n\t\t\t    (pmlmepriv->num_sta_no_short_slot_time == 0))\n\t\t\t\tbeacon_updated = _TRUE;\n\t\t}\n\t}\n\n#ifdef CONFIG_80211N_HT\n\tif(padapter->registrypriv.ht_enable &&\n\t\tis_supported_ht(padapter->registrypriv.wireless_mode)) {\n\t\tif (psta->flags & WLAN_STA_HT) {\n\t\t\tu16 ht_capab = le16_to_cpu(psta->htpriv.ht_cap.cap_info);\n\n\t\t\tRTW_INFO(\"HT: STA \" MAC_FMT \" HT Capabilities Info: 0x%04x\\n\",\n\t\t\t\tMAC_ARG(psta->cmn.mac_addr), ht_capab);\n\n\t\t\tif (psta->no_ht_set) {\n\t\t\t\tpsta->no_ht_set = 0;\n\t\t\t\tpmlmepriv->num_sta_no_ht--;\n\t\t\t}\n\n\t\t\tif ((ht_capab & IEEE80211_HT_CAP_GRN_FLD) == 0) {\n\t\t\t\tif (!psta->no_ht_gf_set) {\n\t\t\t\t\tpsta->no_ht_gf_set = 1;\n\t\t\t\t\tpmlmepriv->num_sta_ht_no_gf++;\n\t\t\t\t}\n\t\t\t\tRTW_INFO(\"%s STA \" MAC_FMT \" - no \"\n\t\t\t\t\t \"greenfield, num of non-gf stations %d\\n\",\n\t\t\t\t\t __FUNCTION__, MAC_ARG(psta->cmn.mac_addr),\n\t\t\t\t\t pmlmepriv->num_sta_ht_no_gf);\n\t\t\t}\n\n\t\t\tif ((ht_capab & IEEE80211_HT_CAP_SUP_WIDTH) == 0) {\n\t\t\t\tif (!psta->ht_20mhz_set) {\n\t\t\t\t\tpsta->ht_20mhz_set = 1;\n\t\t\t\t\tpmlmepriv->num_sta_ht_20mhz++;\n\t\t\t\t}\n\t\t\t\tRTW_INFO(\"%s STA \" MAC_FMT \" - 20 MHz HT, \"\n\t\t\t\t\t \"num of 20MHz HT STAs %d\\n\",\n\t\t\t\t\t __FUNCTION__, MAC_ARG(psta->cmn.mac_addr),\n\t\t\t\t\t pmlmepriv->num_sta_ht_20mhz);\n\t\t\t}\n\n\t\t\tif (((ht_capab & RTW_IEEE80211_HT_CAP_40MHZ_INTOLERANT) != 0) &&\n\t\t\t\t(psta->ht_40mhz_intolerant == 0)) {\n\t\t\t\tpsta->ht_40mhz_intolerant = 1;\n\t\t\t\tpmlmepriv->num_sta_40mhz_intolerant++;\n\t\t\t\tRTW_INFO(\"%s STA \" MAC_FMT \" - 40MHZ_INTOLERANT, \",\n\t\t\t\t\t   __FUNCTION__, MAC_ARG(psta->cmn.mac_addr));\n\t\t\t}\n\n\t\t} else {\n\t\t\tif (!psta->no_ht_set) {\n\t\t\t\tpsta->no_ht_set = 1;\n\t\t\t\tpmlmepriv->num_sta_no_ht++;\n\t\t\t}\n\t\t\tif (pmlmepriv->htpriv.ht_option == _TRUE) {\n\t\t\t\tRTW_INFO(\"%s STA \" MAC_FMT\n\t\t\t\t\t \" - no HT, num of non-HT stations %d\\n\",\n\t\t\t\t\t __FUNCTION__, MAC_ARG(psta->cmn.mac_addr),\n\t\t\t\t\t pmlmepriv->num_sta_no_ht);\n\t\t\t}\n\t\t}\n\n\t\tif (rtw_ht_operation_update(padapter) > 0) {\n\t\t\tupdate_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0);\n\t\t\tupdate_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE, 0);\n\t\t\tbeacon_updated = _TRUE;\n\t\t}\n\t}\n#endif /* CONFIG_80211N_HT */\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(padapter)) {\n\t\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\t\tupdate_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE, 0);\n\t\tif (pstapriv->asoc_list_cnt == 1)\n\t\t\t_set_timer(&padapter->mesh_atlm_param_req_timer, 0);\n\t\tbeacon_updated = _TRUE;\n\t}\n#endif\n\n\tif (beacon_updated)\n\t\tupdate_beacon(padapter, 0xFF, NULL, _TRUE, 0);\n\n\t/* update associcated stations cap. */\n\tassociated_clients_update(padapter,  beacon_updated, STA_INFO_UPDATE_ALL);\n\n\tRTW_INFO(\"%s, updated=%d\\n\", __func__, beacon_updated);\n\n}\n\nu8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta)\n{\n\tu8 beacon_updated = _FALSE;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n\n\tif (!psta)\n\t\treturn beacon_updated;\n\n\tif (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) {\n\t\trtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);\n\t\tbeacon_updated = _TRUE;\n\t\tupdate_beacon(padapter, _TIM_IE_, NULL, _FALSE, 0);\n\t}\n\n\tif (psta->no_short_preamble_set) {\n\t\tpsta->no_short_preamble_set = 0;\n\t\tpmlmepriv->num_sta_no_short_preamble--;\n\t\tif (pmlmeext->cur_wireless_mode > WIRELESS_11B\n\t\t    && pmlmepriv->num_sta_no_short_preamble == 0)\n\t\t\tbeacon_updated = _TRUE;\n\t}\n\n\tif (psta->nonerp_set) {\n\t\tpsta->nonerp_set = 0;\n\t\tpmlmepriv->num_sta_non_erp--;\n\t\tif (pmlmepriv->num_sta_non_erp == 0) {\n\t\t\tbeacon_updated = _TRUE;\n\t\t\tupdate_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE, 0);\n\t\t}\n\t}\n\n\tif (psta->no_short_slot_time_set) {\n\t\tpsta->no_short_slot_time_set = 0;\n\t\tpmlmepriv->num_sta_no_short_slot_time--;\n\t\tif (pmlmeext->cur_wireless_mode > WIRELESS_11B\n\t\t    && pmlmepriv->num_sta_no_short_slot_time == 0)\n\t\t\tbeacon_updated = _TRUE;\n\t}\n\n#ifdef CONFIG_80211N_HT\n\tif (psta->no_ht_gf_set) {\n\t\tpsta->no_ht_gf_set = 0;\n\t\tpmlmepriv->num_sta_ht_no_gf--;\n\t}\n\n\tif (psta->no_ht_set) {\n\t\tpsta->no_ht_set = 0;\n\t\tpmlmepriv->num_sta_no_ht--;\n\t}\n\n\tif (psta->ht_20mhz_set) {\n\t\tpsta->ht_20mhz_set = 0;\n\t\tpmlmepriv->num_sta_ht_20mhz--;\n\t}\n\n\tif (psta->ht_40mhz_intolerant) {\n\t\tpsta->ht_40mhz_intolerant = 0;\n\t\tif (pmlmepriv->num_sta_40mhz_intolerant > 0)\n\t\t\tpmlmepriv->num_sta_40mhz_intolerant--;\n\t\telse\n\t\t\trtw_warn_on(1);\n\t}\n\n\tif (rtw_ht_operation_update(padapter) > 0) {\n\t\tupdate_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0);\n\t\tupdate_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE, 0);\n\t}\n#endif /* CONFIG_80211N_HT */\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(padapter)) {\n\t\tupdate_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE, 0);\n\t\tif (pstapriv->asoc_list_cnt == 0)\n\t\t\t_cancel_timer_ex(&padapter->mesh_atlm_param_req_timer);\n\t\tbeacon_updated = _TRUE;\n\t}\n#endif\n\n\tif (beacon_updated == _TRUE)\n\t\tupdate_beacon(padapter, 0xFF, NULL, _TRUE, 0);\n\n#if 0\n\t/* update associated stations cap. */\n\tassociated_clients_update(padapter,  beacon_updated, STA_INFO_UPDATE_ALL); /* move it to avoid deadlock */\n#endif\n\n\tRTW_INFO(\"%s, updated=%d\\n\", __func__, beacon_updated);\n\n\treturn beacon_updated;\n\n}\n\nu8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue)\n{\n\t_irqL irqL;\n\tu8 beacon_updated = _FALSE;\n\n\tif (!psta)\n\t\treturn beacon_updated;\n\n\tif (active == _TRUE) {\n#ifdef CONFIG_80211N_HT\n\t\t/* tear down Rx AMPDU */\n\t\tsend_delba(padapter, 0, psta->cmn.mac_addr);/* recipient */\n\n\t\t/* tear down TX AMPDU */\n\t\tsend_delba(padapter, 1, psta->cmn.mac_addr);/*  */ /* originator */\n\n#endif /* CONFIG_80211N_HT */\n\n\t\tif (!MLME_IS_MESH(padapter))\n\t\t\tissue_deauth(padapter, psta->cmn.mac_addr, reason);\n\t}\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(padapter))\n\t\trtw_mesh_path_flush_by_nexthop(psta);\n#endif\n\n#ifdef CONFIG_BEAMFORMING\n\tbeamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, psta->cmn.mac_addr, ETH_ALEN, 1);\n#endif\n\n#ifdef CONFIG_80211N_HT\n\tpsta->htpriv.agg_enable_bitmap = 0x0;/* reset */\n\tpsta->htpriv.candidate_tid_bitmap = 0x0;/* reset */\n#endif\n\n\t/* clear cam entry / key */\n\trtw_clearstakey_cmd(padapter, psta, enqueue);\n\n\n\t_enter_critical_bh(&psta->lock, &irqL);\n\tpsta->state &= ~(_FW_LINKED | WIFI_UNDER_KEY_HANDSHAKE);\n\n\tif ((psta->auth_len != 0) && (psta->pauth_frame != NULL)) {\n\t\trtw_mfree(psta->pauth_frame, psta->auth_len);\n\t\tpsta->pauth_frame = NULL;\n\t\tpsta->auth_len = 0;\n\t}\n\t_exit_critical_bh(&psta->lock, &irqL);\n\n\tif (!MLME_IS_MESH(padapter)) {\n#ifdef CONFIG_IOCTL_CFG80211\n\t\t#ifdef COMPAT_KERNEL_RELEASE\n\t\trtw_cfg80211_indicate_sta_disassoc(padapter, psta->cmn.mac_addr, reason);\n\t\t#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)\n\t\trtw_cfg80211_indicate_sta_disassoc(padapter, psta->cmn.mac_addr, reason);\n\t\t#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */\n\t\t/* will call rtw_cfg80211_indicate_sta_disassoc() in cmd_thread for old API context */\n\t\t#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */\n#else\n\t\trtw_indicate_sta_disassoc_event(padapter, psta);\n#endif\n\t}\n\n\tbeacon_updated = bss_cap_update_on_sta_leave(padapter, psta);\n\n\treport_del_sta_event(padapter, psta->cmn.mac_addr, reason, enqueue, _FALSE);\n\n\treturn beacon_updated;\n\n}\n\nint rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset)\n{\n\t_irqL irqL;\n\t_list\t*phead, *plist;\n\tint ret = 0;\n\tstruct sta_info *psta = NULL;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\n\tif ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)\n\t\treturn ret;\n\n\tRTW_INFO(FUNC_NDEV_FMT\" with ch:%u, offset:%u\\n\",\n\t\t FUNC_NDEV_ARG(padapter->pnetdev), new_ch, ch_offset);\n\n\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\tphead = &pstapriv->asoc_list;\n\tplist = get_next(phead);\n\n\t/* for each sta in asoc_queue */\n\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);\n\t\tplist = get_next(plist);\n\n\t\tissue_action_spct_ch_switch(padapter, psta->cmn.mac_addr, new_ch, ch_offset);\n\t\tpsta->expire_to = ((pstapriv->expire_to * 2) > 5) ? 5 : (pstapriv->expire_to * 2);\n\t}\n\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\tissue_action_spct_ch_switch(padapter, bc_addr, new_ch, ch_offset);\n\n\treturn ret;\n}\n\nint rtw_sta_flush(_adapter *padapter, bool enqueue)\n{\n\t_irqL irqL;\n\t_list\t*phead, *plist;\n\tint ret = 0;\n\tstruct sta_info *psta = NULL;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tu8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tu8 flush_num = 0;\n\tchar flush_list[NUM_STA];\n\tint i;\n\n\tif (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))\n\t\treturn ret;\n\n\tRTW_INFO(FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(padapter->pnetdev));\n\n\t/* pick sta from sta asoc_queue */\n\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\tphead = &pstapriv->asoc_list;\n\tplist = get_next(phead);\n\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\tint stainfo_offset;\n\n\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);\n\t\tplist = get_next(plist);\n\n\t\trtw_list_delete(&psta->asoc_list);\n\t\tpstapriv->asoc_list_cnt--;\n\t\tSTA_SET_MESH_PLINK(psta, NULL);\n\n\t\tstainfo_offset = rtw_stainfo_offset(pstapriv, psta);\n\t\tif (stainfo_offset_valid(stainfo_offset))\n\t\t\tflush_list[flush_num++] = stainfo_offset;\n\t\telse\n\t\t\trtw_warn_on(1);\n\t}\n\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\t/* call ap_free_sta() for each sta picked */\n\tfor (i = 0; i < flush_num; i++) {\n\t\tu8 sta_addr[ETH_ALEN];\n\n\t\tpsta = rtw_get_stainfo_by_offset(pstapriv, flush_list[i]);\n\t\t_rtw_memcpy(sta_addr, psta->cmn.mac_addr, ETH_ALEN);\n\n\t\tap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, enqueue);\n\t\t#ifdef CONFIG_RTW_MESH\n\t\tif (MLME_IS_MESH(padapter))\n\t\t\trtw_mesh_expire_peer(padapter, sta_addr);\n\t\t#endif\n\t}\n\n\tif (!MLME_IS_MESH(padapter))\n\t\tissue_deauth(padapter, bc_addr, WLAN_REASON_DEAUTH_LEAVING);\n\n\tassociated_clients_update(padapter, _TRUE, STA_INFO_UPDATE_ALL);\n\n\treturn ret;\n}\n\n/* called > TSR LEVEL for USB or SDIO Interface*/\nvoid sta_info_update(_adapter *padapter, struct sta_info *psta)\n{\n\tint flags = psta->flags;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\n\t/* update wmm cap. */\n\tif (WLAN_STA_WME & flags)\n\t\tpsta->qos_option = 1;\n\telse\n\t\tpsta->qos_option = 0;\n\n\tif (pmlmepriv->qospriv.qos_option == 0)\n\t\tpsta->qos_option = 0;\n\n\n#ifdef CONFIG_80211N_HT\n\t/* update 802.11n ht cap. */\n\tif (WLAN_STA_HT & flags) {\n\t\tpsta->htpriv.ht_option = _TRUE;\n\t\tpsta->qos_option = 1;\n\n\t\tpsta->htpriv.smps_cap = (psta->htpriv.ht_cap.cap_info & IEEE80211_HT_CAP_SM_PS) >> 2;\n\t} else\n\t\tpsta->htpriv.ht_option = _FALSE;\n\n\tif (pmlmepriv->htpriv.ht_option == _FALSE)\n\t\tpsta->htpriv.ht_option = _FALSE;\n#endif\n\n#ifdef CONFIG_80211AC_VHT\n\t/* update 802.11AC vht cap. */\n\tif (WLAN_STA_VHT & flags)\n\t\tpsta->vhtpriv.vht_option = _TRUE;\n\telse\n\t\tpsta->vhtpriv.vht_option = _FALSE;\n\n\tif (pmlmepriv->vhtpriv.vht_option == _FALSE)\n\t\tpsta->vhtpriv.vht_option = _FALSE;\n#endif\n\n\tupdate_sta_info_apmode(padapter, psta);\n}\n\n/* called >= TSR LEVEL for USB or SDIO Interface*/\nvoid ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta)\n{\n\tif (psta->state & _FW_LINKED)\n\t\trtw_hal_update_ra_mask(psta); /* DM_RATR_STA_INIT */\n}\n/* restore hw setting from sw data structures */\nvoid rtw_ap_restore_network(_adapter *padapter)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct sta_info *psta;\n\tstruct security_priv *psecuritypriv = &(padapter->securitypriv);\n\t_irqL irqL;\n\t_list\t*phead, *plist;\n\tu8 chk_alive_num = 0;\n\tchar chk_alive_list[NUM_STA];\n\tint i;\n\n\trtw_setopmode_cmd(padapter\n\t\t, MLME_IS_AP(padapter) ? Ndis802_11APMode : Ndis802_11_mesh\n\t\t, RTW_CMDF_DIRECTLY\n\t);\n\n\tset_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);\n\n\trtw_startbss_cmd(padapter, RTW_CMDF_DIRECTLY);\n\n\tif ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||\n\t    (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) {\n\t\t/* restore group key, WEP keys is restored in ips_leave() */\n\t\trtw_set_key(padapter, psecuritypriv, psecuritypriv->dot118021XGrpKeyid, 0, _FALSE);\n\t}\n\n\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\tphead = &pstapriv->asoc_list;\n\tplist = get_next(phead);\n\n\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\tint stainfo_offset;\n\n\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);\n\t\tplist = get_next(plist);\n\n\t\tstainfo_offset = rtw_stainfo_offset(pstapriv, psta);\n\t\tif (stainfo_offset_valid(stainfo_offset))\n\t\t\tchk_alive_list[chk_alive_num++] = stainfo_offset;\n\t}\n\n\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\tfor (i = 0; i < chk_alive_num; i++) {\n\t\tpsta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]);\n\n\t\tif (psta == NULL)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" sta_info is null\\n\", FUNC_ADPT_ARG(padapter));\n\t\telse if (psta->state & _FW_LINKED) {\n\t\t\trtw_sta_media_status_rpt(padapter, psta, 1);\n\t\t\tUpdate_RA_Entry(padapter, psta);\n\t\t\t/* pairwise key */\n\t\t\t/* per sta pairwise key and settings */\n\t\t\tif ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||\n\t\t\t    (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_))\n\t\t\t\trtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _FALSE);\n\t\t}\n\t}\n\n}\n\nvoid start_ap_mode(_adapter *padapter)\n{\n\tint i;\n\tstruct sta_info *psta = NULL;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n#ifdef CONFIG_CONCURRENT_MODE\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n#endif\n\n\tpmlmepriv->update_bcn = _FALSE;\n\n\t/*init_mlme_ap_info(padapter);*/\n\n\tpmlmeext->bstart_bss = _FALSE;\n\n\tpmlmepriv->num_sta_non_erp = 0;\n\n\tpmlmepriv->num_sta_no_short_slot_time = 0;\n\n\tpmlmepriv->num_sta_no_short_preamble = 0;\n\n\tpmlmepriv->num_sta_ht_no_gf = 0;\n#ifdef CONFIG_80211N_HT\n\tpmlmepriv->num_sta_no_ht = 0;\n#endif /* CONFIG_80211N_HT */\n\tpmlmeinfo->HT_info_enable = 0;\n\tpmlmeinfo->HT_caps_enable = 0;\n\tpmlmeinfo->HT_enable = 0;\n\n\tpmlmepriv->num_sta_ht_20mhz = 0;\n\tpmlmepriv->num_sta_40mhz_intolerant = 0;\n\tATOMIC_SET(&pmlmepriv->olbc, _FALSE);\n\tATOMIC_SET(&pmlmepriv->olbc_ht, _FALSE);\n\n#ifdef CONFIG_80211N_HT\n\tpmlmepriv->ht_20mhz_width_req = _FALSE;\n\tpmlmepriv->ht_intolerant_ch_reported = _FALSE;\n\tpmlmepriv->ht_op_mode = 0;\n\tpmlmepriv->sw_to_20mhz = 0;\n#endif\n\n\t_rtw_memset(pmlmepriv->ext_capab_ie_data, 0, sizeof(pmlmepriv->ext_capab_ie_data));\n\tpmlmepriv->ext_capab_ie_len = 0;\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tpsecuritypriv->dot118021x_bmc_cam_id = INVALID_SEC_MAC_CAM_ID;\n#endif\n\n\tfor (i = 0 ;  i < pstapriv->max_aid; i++)\n\t\tpstapriv->sta_aid[i] = NULL;\n\n\tpsta = rtw_get_bcmc_stainfo(padapter);\n\t/*_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/\n\tif (psta)\n\t\trtw_free_stainfo(padapter, psta);\n\t/*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/\n\n\trtw_init_bcmc_stainfo(padapter);\n\n\tif (rtw_mi_get_ap_num(padapter))\n\t\tRTW_SET_SCAN_BAND_SKIP(padapter, BAND_5G);\n\n}\n\nvoid rtw_ap_bcmc_sta_flush(_adapter *padapter)\n{\n#ifdef CONFIG_CONCURRENT_MODE\n\tint cam_id = -1;\n\tu8 *addr = adapter_mac_addr(padapter);\n\n\tcam_id = rtw_iface_bcmc_id_get(padapter);\n\tif (cam_id != INVALID_SEC_MAC_CAM_ID) {\n\t\tRTW_PRINT(\"clear group key for \"ADPT_FMT\" addr:\"MAC_FMT\", camid:%d\\n\",\n\t\t\tADPT_ARG(padapter), MAC_ARG(addr), cam_id);\n\t\tclear_cam_entry(padapter, cam_id);\n\t\trtw_camid_free(padapter, cam_id);\n\t\trtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID);\t/*init default value*/\n\t}\n#else\n\tinvalidate_cam_all(padapter);\n#endif\n}\n\nvoid stop_ap_mode(_adapter *padapter)\n{\n\tu8 self_action = MLME_ACTION_UNKNOWN;\n\tstruct sta_info *psta = NULL;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n#ifdef CONFIG_SUPPORT_MULTI_BCN\n\tstruct dvobj_priv *pdvobj = padapter->dvobj;\n\t_irqL irqL;\n#endif\n\n\tRTW_INFO(\"%s -\"ADPT_FMT\"\\n\", __func__, ADPT_ARG(padapter));\n\n\tif (MLME_IS_AP(padapter))\n\t\tself_action = MLME_AP_STOPPED;\n\telse if (MLME_IS_MESH(padapter))\n\t\tself_action = MLME_MESH_STOPPED;\n\telse\n\t\trtw_warn_on(1);\n\n\tpmlmepriv->update_bcn = _FALSE;\n\t/*pmlmeext->bstart_bss = _FALSE;*/\n\tpadapter->netif_up = _FALSE;\n\t/* _rtw_spinlock_free(&pmlmepriv->bcn_update_lock); */\n\n\t/* reset and init security priv , this can refine with rtw_reset_securitypriv */\n\t_rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof(struct security_priv));\n\tpadapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;\n\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled;\n\n#ifdef CONFIG_DFS_MASTER\n\trtw_dfs_rd_en_decision(padapter, self_action, 0);\n#endif\n\n\t/* free scan queue */\n\trtw_free_network_queue(padapter, _TRUE);\n\n#if CONFIG_RTW_MACADDR_ACL\n\trtw_macaddr_acl_clear(padapter, RTW_ACL_PERIOD_BSS);\n#endif\n\n\trtw_sta_flush(padapter, _TRUE);\n\trtw_ap_bcmc_sta_flush(padapter);\n\n\t/* free_assoc_sta_resources\t */\n\trtw_free_all_stainfo(padapter);\n\n\tpsta = rtw_get_bcmc_stainfo(padapter);\n\tif (psta) {\n\t\trtw_sta_mstatus_disc_rpt(padapter, psta->cmn.mac_id);\n\t\t/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\t\t */\n\t\trtw_free_stainfo(padapter, psta);\n\t\t/*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/\n\t}\n\n\trtw_free_mlme_priv_ie_data(pmlmepriv);\n\n#ifdef CONFIG_SUPPORT_MULTI_BCN\n\tif (pmlmeext->bstart_bss == _TRUE) {\n\t\t#ifdef CONFIG_FW_HANDLE_TXBCN\n\t\tu8 free_apid = CONFIG_LIMITED_AP_NUM;\n\t\t#endif\n\n\t\t_enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL);\n\t\tpdvobj->nr_ap_if--;\n\t\tif (pdvobj->nr_ap_if > 0)\n\t\t\tpdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL / pdvobj->nr_ap_if;\n\t\telse\n\t\t\tpdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL;\n\t\t#ifdef CONFIG_FW_HANDLE_TXBCN\n\t\trtw_ap_release_vapid(pdvobj, padapter->vap_id);\n\t\tfree_apid = padapter->vap_id;\n\t\tpadapter->vap_id = CONFIG_LIMITED_AP_NUM;\n\t\t#endif\n\t\trtw_list_delete(&padapter->list);\n\t\t_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);\n\t\t#ifdef CONFIG_FW_HANDLE_TXBCN\n\t\trtw_ap_mbid_bcn_dis(padapter, free_apid);\n\t\t#endif\n\n\t\t#ifdef CONFIG_SWTIMER_BASED_TXBCN\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pdvobj->inter_bcn_space));\n\n\t\tif (pdvobj->nr_ap_if == 0)\n\t\t\t_cancel_timer_ex(&pdvobj->txbcn_timer);\n\t\t#endif\n\t}\n#endif\n\n\tpmlmeext->bstart_bss = _FALSE;\n\n\trtw_hal_rcr_set_chk_bssid(padapter, self_action);\n\n#ifdef CONFIG_HW_P0_TSF_SYNC\n\tcorrect_TSF(padapter, self_action);\n#endif\n\n#ifdef CONFIG_BT_COEXIST\n\trtw_btcoex_MediaStatusNotify(padapter, 0); /* disconnect */\n#endif\n\n}\n\n#endif /* CONFIG_NATIVEAP_MLME */\n\nvoid rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset)\n{\n#define UPDATE_VHT_CAP 1\n#define UPDATE_HT_CAP 1\n#ifdef CONFIG_80211AC_VHT\n\tstruct vht_priv *vhtpriv = &adapter->mlmepriv.vhtpriv;\n#endif\n\t{\n\t\tu8 *p;\n\t\tint ie_len;\n\t\tu8 old_ch = bss->Configuration.DSConfig;\n\t\tbool change_band = _FALSE;\n\n\t\tif ((ch <= 14 && old_ch >= 36) || (ch >= 36 && old_ch <= 14))\n\t\t\tchange_band = _TRUE;\n\n\t\t/* update channel in IE */\n\t\tp = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));\n\t\tif (p && ie_len > 0)\n\t\t\t*(p + 2) = ch;\n\n\t\tbss->Configuration.DSConfig = ch;\n\n\t\t/* band is changed, update ERP, support rate, ext support rate IE */\n\t\tif (change_band == _TRUE)\n\t\t\tchange_band_update_ie(adapter, bss, ch);\n\t}\n\n#ifdef CONFIG_80211AC_VHT\n\tif (vhtpriv->vht_option == _TRUE) {\n\t\tu8 *vht_cap_ie, *vht_op_ie;\n\t\tint vht_cap_ielen, vht_op_ielen;\n\t\tu8\tcenter_freq;\n\n\t\tvht_cap_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_VHTCapability, &vht_cap_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));\n\t\tvht_op_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_VHTOperation, &vht_op_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));\n\t\tcenter_freq = rtw_get_center_ch(ch, bw, offset);\n\n\t\t/* update vht cap ie */\n\t\tif (vht_cap_ie && vht_cap_ielen) {\n\t\t\t#if UPDATE_VHT_CAP\n\t\t\t/* if ((bw == CHANNEL_WIDTH_160 || bw == CHANNEL_WIDTH_80_80) && pvhtpriv->sgi_160m)\n\t\t\t\tSET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvht_cap_ie + 2, 1);\n\t\t\telse */\n\t\t\t\tSET_VHT_CAPABILITY_ELE_SHORT_GI160M(vht_cap_ie + 2, 0);\n\n\t\t\tif (bw >= CHANNEL_WIDTH_80 && vhtpriv->sgi_80m)\n\t\t\t\tSET_VHT_CAPABILITY_ELE_SHORT_GI80M(vht_cap_ie + 2, 1);\n\t\t\telse\n\t\t\t\tSET_VHT_CAPABILITY_ELE_SHORT_GI80M(vht_cap_ie + 2, 0);\n\t\t\t#endif\n\t\t}\n\n\t\t/* update vht op ie */\n\t\tif (vht_op_ie && vht_op_ielen) {\n\t\t\tif (bw < CHANNEL_WIDTH_80) {\n\t\t\t\tSET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0);\n\t\t\t\tSET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0);\n\t\t\t\tSET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0);\n\t\t\t} else if (bw == CHANNEL_WIDTH_80) {\n\t\t\t\tSET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 1);\n\t\t\t\tSET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, center_freq);\n\t\t\t\tSET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0);\n\t\t\t} else {\n\t\t\t\tRTW_ERR(FUNC_ADPT_FMT\" unsupported BW:%u\\n\", FUNC_ADPT_ARG(adapter), bw);\n\t\t\t\trtw_warn_on(1);\n\t\t\t}\n\t\t}\n\t}\n#endif /* CONFIG_80211AC_VHT */\n#ifdef CONFIG_80211N_HT\n\t{\n\t\tstruct ht_priv\t*htpriv = &adapter->mlmepriv.htpriv;\n\t\tu8 *ht_cap_ie, *ht_op_ie;\n\t\tint ht_cap_ielen, ht_op_ielen;\n\n\t\tht_cap_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_HTCapability, &ht_cap_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));\n\t\tht_op_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_HTInfo, &ht_op_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));\n\n\t\t/* update ht cap ie */\n\t\tif (ht_cap_ie && ht_cap_ielen) {\n\t\t\t#if UPDATE_HT_CAP\n\t\t\tif (bw >= CHANNEL_WIDTH_40)\n\t\t\t\tSET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2, 1);\n\t\t\telse\n\t\t\t\tSET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2, 0);\n\n\t\t\tif (bw >= CHANNEL_WIDTH_40 && htpriv->sgi_40m)\n\t\t\t\tSET_HT_CAP_ELE_SHORT_GI40M(ht_cap_ie + 2, 1);\n\t\t\telse\n\t\t\t\tSET_HT_CAP_ELE_SHORT_GI40M(ht_cap_ie + 2, 0);\n\n\t\t\tif (htpriv->sgi_20m)\n\t\t\t\tSET_HT_CAP_ELE_SHORT_GI20M(ht_cap_ie + 2, 1);\n\t\t\telse\n\t\t\t\tSET_HT_CAP_ELE_SHORT_GI20M(ht_cap_ie + 2, 0);\n\t\t\t#endif\n\t\t}\n\n\t\t/* update ht op ie */\n\t\tif (ht_op_ie && ht_op_ielen) {\n\t\t\tSET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2, ch);\n\t\t\tswitch (offset) {\n\t\t\tcase HAL_PRIME_CHNL_OFFSET_LOWER:\n\t\t\t\tSET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCA);\n\t\t\t\tbreak;\n\t\t\tcase HAL_PRIME_CHNL_OFFSET_UPPER:\n\t\t\t\tSET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCB);\n\t\t\t\tbreak;\n\t\t\tcase HAL_PRIME_CHNL_OFFSET_DONT_CARE:\n\t\t\tdefault:\n\t\t\t\tSET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCN);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif (bw >= CHANNEL_WIDTH_40)\n\t\t\t\tSET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2, 1);\n\t\t\telse\n\t\t\t\tSET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2, 0);\n\t\t}\n\t}\n#endif /* CONFIG_80211N_HT */\n}\n\nstatic u8 rtw_ap_update_chbw_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp\n\t, u8 cur_ie_ch[], u8 cur_ie_bw[], u8 cur_ie_offset[]\n\t, u8 dec_ch[], u8 dec_bw[], u8 dec_offset[]\n\t, const char *caller)\n{\n\t_adapter *iface;\n\tstruct mlme_ext_priv *mlmeext;\n\tWLAN_BSSID_EX *network;\n\tu8 ifbmp_ch_changed = 0;\n\tint i;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tif (!(ifbmp & BIT(i)) || !dvobj->padapters)\n\t\t\tcontinue;\n\n\t\tiface = dvobj->padapters[i];\n\t\tmlmeext = &(iface->mlmeextpriv);\n\n\t\tif (MLME_IS_ASOC(iface)) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" %u,%u,%u => %u,%u,%u%s\\n\", caller, ADPT_ARG(iface)\n\t\t\t\t, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset\n\t\t\t\t, dec_ch[i], dec_bw[i], dec_offset[i]\n\t\t\t\t, MLME_IS_OPCH_SW(iface) ? \" OPCH_SW\" : \"\");\n\t\t} else {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" %u,%u,%u => %u,%u,%u%s\\n\", caller, ADPT_ARG(iface)\n\t\t\t\t, cur_ie_ch[i], cur_ie_bw[i], cur_ie_offset[i]\n\t\t\t\t, dec_ch[i], dec_bw[i], dec_offset[i]\n\t\t\t\t, MLME_IS_OPCH_SW(iface) ? \" OPCH_SW\" : \"\");\n\t\t}\n\t}\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tif (!(ifbmp & BIT(i)) || !dvobj->padapters)\n\t\t\tcontinue;\n\n\t\tiface = dvobj->padapters[i];\n\t\tmlmeext = &(iface->mlmeextpriv);\n\t\tnetwork = &(mlmeext->mlmext_info.network);\n\n\t\t/* ch setting differs from mlmeext.network IE */\n\t\tif (cur_ie_ch[i] != dec_ch[i]\n\t\t\t|| cur_ie_bw[i] != dec_bw[i]\n\t\t\t|| cur_ie_offset[i] != dec_offset[i])\n\t\t\tifbmp_ch_changed |= BIT(i);\n\n\t\t/* ch setting differs from existing one */\n\t\tif (MLME_IS_ASOC(iface)\n\t\t\t&& (mlmeext->cur_channel != dec_ch[i]\n\t\t\t\t|| mlmeext->cur_bwmode != dec_bw[i]\n\t\t\t\t|| mlmeext->cur_ch_offset != dec_offset[i])\n\t\t) {\n\t\t\tif (rtw_linked_check(iface) == _TRUE) {\n\t\t\t\t#ifdef CONFIG_SPCT_CH_SWITCH\n\t\t\t\tif (1)\n\t\t\t\t\trtw_ap_inform_ch_switch(iface, dec_ch[i], dec_offset[i]);\n\t\t\t\telse\n\t\t\t\t#endif\n\t\t\t\t\trtw_sta_flush(iface, _FALSE);\n\t\t\t}\n\t\t}\n\n\t\tmlmeext->cur_channel = dec_ch[i];\n\t\tmlmeext->cur_bwmode = dec_bw[i];\n\t\tmlmeext->cur_ch_offset = dec_offset[i];\n\n\t\trtw_ap_update_bss_chbw(iface, network, dec_ch[i], dec_bw[i], dec_offset[i]);\n\t}\n\n\treturn ifbmp_ch_changed;\n}\n\nstatic u8 rtw_ap_ch_specific_chk(_adapter *adapter, u8 ch, u8 *bw, u8 *offset, const char *caller)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tRT_CHANNEL_INFO *chset = adapter_to_chset(adapter);\n\tu8 ret = _SUCCESS;\n\n\tif (rtw_chset_search_ch(chset, ch) < 0) {\n\t\tRTW_WARN(\"%s ch:%u doesn't fit in chplan\\n\", caller, ch);\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\trtw_adjust_chbw(adapter, ch, bw, offset);\n\n\tif (!rtw_get_offset_by_chbw(ch, *bw, offset)) {\n\t\tRTW_WARN(\"%s %u,%u has no valid offset\\n\", caller, ch, *bw);\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\twhile (!rtw_chset_is_chbw_valid(chset, ch, *bw, *offset)\n\t\t|| (rtw_odm_dfs_domain_unknown(dvobj) && rtw_is_dfs_chbw(ch, *bw, *offset))\n\t) {\n\t\tif (*bw > CHANNEL_WIDTH_20)\n\t\t\t(*bw)--;\n\t\tif (*bw == CHANNEL_WIDTH_20) {\n\t\t\t*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (rtw_odm_dfs_domain_unknown(dvobj) && rtw_is_dfs_chbw(ch, *bw, *offset)) {\n\t\tRTW_WARN(\"%s DFS channel %u can't be used\\n\", caller, ch);\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\nexit:\n\treturn ret;\n}\n\nstatic bool rtw_ap_choose_chbw(_adapter *adapter, u8 sel_ch, u8 max_bw, u8 cur_ch\n\t, u8 *ch, u8 *bw, u8 *offset, u8 mesh_only, const char *caller)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tbool ch_avail = _FALSE;\n\n#if defined(CONFIG_DFS_MASTER)\n\tif (!rtw_odm_dfs_domain_unknown(dvobj)) {\n\t\tif (rfctl->radar_detected\n\t\t\t&& rfctl->dbg_dfs_choose_dfs_ch_first\n\t\t) {\n\t\t\tch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw\n\t\t\t\t\t\t, ch, bw, offset\n\t\t\t\t\t\t, RTW_CHF_2G | RTW_CHF_NON_DFS\n\t\t\t\t\t\t, cur_ch\n\t\t\t\t\t\t, rfctl->ch_sel_same_band_prefer, mesh_only);\n\t\t\tif (ch_avail == _TRUE) {\n\t\t\t\tRTW_INFO(\"%s choose 5G DFS channel for debug\\n\", caller);\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\n\t\tif (rfctl->radar_detected\n\t\t\t&& rfctl->dfs_ch_sel_d_flags\n\t\t) {\n\t\t\tch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw\n\t\t\t\t\t\t, ch, bw, offset\n\t\t\t\t\t\t, rfctl->dfs_ch_sel_d_flags\n\t\t\t\t\t\t, cur_ch\n\t\t\t\t\t\t, rfctl->ch_sel_same_band_prefer, mesh_only);\n\t\t\tif (ch_avail == _TRUE) {\n\t\t\t\tRTW_INFO(\"%s choose with dfs_ch_sel_d_flags:0x%02x for debug\\n\"\n\t\t\t\t\t, caller, rfctl->dfs_ch_sel_d_flags);\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\n\t\tch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw\n\t\t\t\t\t, ch, bw, offset\n\t\t\t\t\t, 0\n\t\t\t\t\t, cur_ch\n\t\t\t\t\t, rfctl->ch_sel_same_band_prefer, mesh_only);\n\t} else\n#endif /* defined(CONFIG_DFS_MASTER) */\n\t{\n\t\tch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw\n\t\t\t\t\t, ch, bw, offset\n\t\t\t\t\t, RTW_CHF_DFS\n\t\t\t\t\t, cur_ch\n\t\t\t\t\t, rfctl->ch_sel_same_band_prefer, mesh_only);\n\t}\n#if defined(CONFIG_DFS_MASTER)\nexit:\n#endif\n\tif (ch_avail == _FALSE)\n\t\tRTW_WARN(\"%s no available channel\\n\", caller);\n\n\treturn ch_avail;\n}\n\nu8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp\n\t, s16 req_ch, s8 req_bw, s8 req_offset\n\t, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tRT_CHANNEL_INFO *chset = adapter_to_chset(adapter);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tbool ch_avail = _FALSE;\n\tu8 cur_ie_ch[CONFIG_IFACE_NUMBER] = {0};\n\tu8 cur_ie_bw[CONFIG_IFACE_NUMBER] = {0};\n\tu8 cur_ie_offset[CONFIG_IFACE_NUMBER] = {0};\n\tu8 dec_ch[CONFIG_IFACE_NUMBER] = {0};\n\tu8 dec_bw[CONFIG_IFACE_NUMBER] = {0};\n\tu8 dec_offset[CONFIG_IFACE_NUMBER] = {0};\n\tu8 u_ch = 0, u_bw = 0, u_offset = 0;\n\tstruct mlme_ext_priv *mlmeext;\n\tWLAN_BSSID_EX *network;\n\tstruct mi_state mstate;\n\tstruct mi_state mstate_others;\n\tbool set_u_ch = _FALSE;\n\tu8 ifbmp_others = 0xFF & ~ifbmp & ~excl_ifbmp;\n\tu8 ifbmp_ch_changed = 0;\n\tbool ifbmp_all_mesh = 0;\n\t_adapter *iface;\n\tint i;\n\n#ifdef CONFIG_RTW_MESH\n\tfor (i = 0; i < dvobj->iface_nums; i++)\n\t\tif ((ifbmp & BIT(i)) && dvobj->padapters)\n\t\t\tif (!MLME_IS_MESH(dvobj->padapters[i]))\n\t\t\t\tbreak;\n\tifbmp_all_mesh = i >= dvobj->iface_nums ? 1 : 0;\n#endif\n\n\tRTW_INFO(\"%s ifbmp:0x%02x excl_ifbmp:0x%02x req:%d,%d,%d\\n\", __func__\n\t\t, ifbmp, excl_ifbmp, req_ch, req_bw, req_offset);\n\trtw_mi_status_by_ifbmp(dvobj, ifbmp, &mstate);\n\trtw_mi_status_by_ifbmp(dvobj, ifbmp_others, &mstate_others);\n\tRTW_INFO(\"%s others ld_sta_num:%u, lg_sta_num:%u, ap_num:%u, mesh_num:%u\\n\"\n\t\t, __func__, MSTATE_STA_LD_NUM(&mstate_others), MSTATE_STA_LG_NUM(&mstate_others)\n\t\t, MSTATE_AP_NUM(&mstate_others), MSTATE_MESH_NUM(&mstate_others));\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tif (!(ifbmp & BIT(i)) || !dvobj->padapters[i])\n\t\t\tcontinue;\n\t\tiface = dvobj->padapters[i];\n\t\tmlmeext = &(iface->mlmeextpriv);\n\t\tnetwork = &(mlmeext->mlmext_info.network);\n\n\t\t/* get current IE channel settings */\n\t\trtw_ies_get_chbw(BSS_EX_TLV_IES(network), BSS_EX_TLV_IES_LEN(network)\n\t\t\t, &cur_ie_ch[i], &cur_ie_bw[i], &cur_ie_offset[i], 1, 1);\n\n\t\t/* prepare temporary channel setting decision */\n\t\tif (req_ch == 0) {\n\t\t\t/* request comes from upper layer, use cur_ie values */\n\t\t\tdec_ch[i] = cur_ie_ch[i];\n\t\t\tdec_bw[i] = cur_ie_bw[i];\n\t\t\tdec_offset[i] = cur_ie_offset[i];\n\t\t} else {\n\t\t\t/* use chbw of cur_ie updated with specifying req as temporary decision */\n\t\t\tdec_ch[i] = (req_ch <= REQ_CH_NONE) ? cur_ie_ch[i] : req_ch;\n\t\t\tif (req_bw <= REQ_BW_NONE) {\n\t\t\t\tif (req_bw == REQ_BW_ORI)\n\t\t\t\t\tdec_bw[i] = iface->mlmepriv.ori_bw;\n\t\t\t\telse\n\t\t\t\t\tdec_bw[i] = cur_ie_bw[i];\n\t\t\t} else\n\t\t\t\tdec_bw[i] = req_bw;\n\t\t\tdec_offset[i] = (req_offset <= REQ_OFFSET_NONE) ? cur_ie_offset[i] : req_offset;\n\t\t}\n\t}\n\n\tif (MSTATE_STA_LD_NUM(&mstate_others) || MSTATE_STA_LG_NUM(&mstate_others)\n\t\t|| MSTATE_AP_NUM(&mstate_others) || MSTATE_MESH_NUM(&mstate_others)\n\t) {\n\t\t/* has linked/linking STA or has AP/Mesh mode */\n\t\trtw_warn_on(!rtw_mi_get_ch_setting_union_by_ifbmp(dvobj, ifbmp_others, &u_ch, &u_bw, &u_offset));\n\t\tRTW_INFO(\"%s others union:%u,%u,%u\\n\", __func__, u_ch, u_bw, u_offset);\n\t}\n\n#ifdef CONFIG_MCC_MODE\n\tif (MCC_EN(adapter) && req_ch == 0) {\n\t\tif (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {\n\t\t\tu8 if_id = adapter->iface_id;\n\n\t\t\tmlmeext = &(adapter->mlmeextpriv);\n\n\t\t\t/* check channel settings are the same */\n\t\t\tif (cur_ie_ch[if_id] == mlmeext->cur_channel\n\t\t\t\t&& cur_ie_bw[if_id] == mlmeext->cur_bwmode\n\t\t\t\t&& cur_ie_offset[if_id] == mlmeext->cur_ch_offset) {\n\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\"req ch settings are the same as current ch setting, go to exit\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(adapter));\n\n\t\t\t\t*chbw_allow = _FALSE;\n\t\t\t\tgoto exit;\n\t\t\t} else {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\"request channel settings are not the same as current channel setting(%d,%d,%d,%d,%d,%d), restart MCC\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(adapter)\n\t\t\t\t\t, cur_ie_ch[if_id], cur_ie_bw[if_id], cur_ie_offset[if_id]\n\t\t\t\t\t, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);\n\n\t\t\t\trtw_hal_set_mcc_setting_disconnect(adapter);\n\t\t\t}\n\t\t}\t\n\t}\n#endif /* CONFIG_MCC_MODE */\n\n\tif (MSTATE_STA_LG_NUM(&mstate_others) && !MSTATE_STA_LD_NUM(&mstate_others)) {\n\t\t/* has linking STA but no linked STA */\n\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tif (!(ifbmp & BIT(i)) || !dvobj->padapters[i])\n\t\t\t\tcontinue;\n\t\t\tiface = dvobj->padapters[i];\n\n\t\t\trtw_adjust_chbw(iface, dec_ch[i], &dec_bw[i], &dec_offset[i]);\n\t\t\t#ifdef CONFIG_RTW_MESH\n\t\t\tif (MLME_IS_MESH(iface))\n\t\t\t\trtw_mesh_adjust_chbw(dec_ch[i], &dec_bw[i], &dec_offset[i]);\n\t\t\t#endif\n\n\t\t\tif (rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch[i], dec_bw[i], dec_offset[i])) {\n\t\t\t\trtw_chset_sync_chbw(chset\n\t\t\t\t\t, &dec_ch[i], &dec_bw[i], &dec_offset[i]\n\t\t\t\t\t, &u_ch, &u_bw, &u_offset);\n\t\t\t\tset_u_ch = _TRUE;\n\n\t\t\t\t/* channel bw offset can be allowed, not need MCC */\n\t\t\t\t*chbw_allow = _TRUE;\n\t\t\t} else {\n\t\t\t\t#ifdef CONFIG_MCC_MODE\n\t\t\t\tif (MCC_EN(iface)) {\n\t\t\t\t\tmlmeext = &(iface->mlmeextpriv);\n\t\t\t\t\tmlmeext->cur_channel = *ch = dec_ch[i];\n\t\t\t\t\tmlmeext->cur_bwmode = *bw = dec_bw[i];\n\t\t\t\t\tmlmeext->cur_ch_offset = *offset = dec_offset[i];\n\n\t\t\t\t\t/* channel bw offset can not be allowed, need MCC */\n\t\t\t\t\t*chbw_allow = _FALSE;\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" enable mcc: %u,%u,%u\\n\", FUNC_ADPT_ARG(iface)\n\t\t\t\t\t\t , *ch, *bw, *offset);\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t\t#endif /* CONFIG_MCC_MODE */\n\n\t\t\t\t/* set this for possible ch change when join down*/\n\t\t\t\tset_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING);\n\t\t\t}\n\t\t}\n\n\t} else if (MSTATE_STA_LD_NUM(&mstate_others)\n\t\t|| MSTATE_AP_NUM(&mstate_others) || MSTATE_MESH_NUM(&mstate_others)\n\t) {\n\t\t/* has linked STA mode or AP/Mesh mode */\n\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tif (!(ifbmp & BIT(i)) || !dvobj->padapters[i])\n\t\t\t\tcontinue;\n\t\t\tiface = dvobj->padapters[i];\n\n\t\t\trtw_adjust_chbw(iface, u_ch, &dec_bw[i], &dec_offset[i]);\n\t\t\t#ifdef CONFIG_RTW_MESH\n\t\t\tif (MLME_IS_MESH(iface))\n\t\t\t\trtw_mesh_adjust_chbw(u_ch, &dec_bw[i], &dec_offset[i]);\n\t\t\t#endif\n\n\t\t\t#ifdef CONFIG_MCC_MODE\n\t\t\tif (MCC_EN(iface)) {\n\t\t\t\tif (!rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch[i], dec_bw[i], dec_offset[i])) {\n\t\t\t\t\tmlmeext = &(iface->mlmeextpriv);\n\t\t\t\t\tmlmeext->cur_channel = *ch = dec_ch[i] = cur_ie_ch[i];\n\t\t\t\t\tmlmeext->cur_bwmode = *bw = dec_bw[i] = cur_ie_bw[i];\n\t\t\t\t\tmlmeext->cur_ch_offset = *offset = dec_offset[i] = cur_ie_offset[i];\n\t\t\t\t\t/* channel bw offset can not be allowed, need MCC */\n\t\t\t\t\t*chbw_allow = _FALSE;\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" enable mcc: %u,%u,%u\\n\", FUNC_ADPT_ARG(iface)\n\t\t\t\t\t\t , *ch, *bw, *offset);\n\t\t\t\t\tgoto exit;\n\t\t\t\t} else\n\t\t\t\t\t/* channel bw offset can be allowed, not need MCC */\n\t\t\t\t\t*chbw_allow = _TRUE;\n\t\t\t}\n\t\t\t#endif /* CONFIG_MCC_MODE */\n\n\t\t\tif (req_ch == 0 && dec_bw[i] > u_bw\n\t\t\t\t&& rtw_is_dfs_chbw(u_ch, u_bw, u_offset)\n\t\t\t) {\n\t\t\t\t/* request comes from upper layer, prevent from additional channel waiting */\n\t\t\t\tdec_bw[i] = u_bw;\n\t\t\t\tif (dec_bw[i] == CHANNEL_WIDTH_20)\n\t\t\t\t\tdec_offset[i] = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t\t}\n\n\t\t\t/* follow */\n\t\t\trtw_chset_sync_chbw(chset\n\t\t\t\t, &dec_ch[i], &dec_bw[i], &dec_offset[i]\n\t\t\t\t, &u_ch, &u_bw, &u_offset);\n\t\t}\n\n\t\tset_u_ch = _TRUE;\n\n\t} else {\n\t\t/* autonomous decision */\n\t\tu8 ori_ch = 0;\n\t\tu8 max_bw;\n\n\t\t/* autonomous decision, not need MCC */\n\t\t*chbw_allow = _TRUE;\n\n\t\tif (req_ch <= REQ_CH_NONE) /* channel is not specified */\n\t\t\tgoto choose_chbw;\n\n\t\t/* get tmp dec union of ifbmp */\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tif (!(ifbmp & BIT(i)) || !dvobj->padapters[i])\n\t\t\t\tcontinue;\n\t\t\tif (u_ch == 0) {\n\t\t\t\tu_ch = dec_ch[i];\n\t\t\t\tu_bw = dec_bw[i];\n\t\t\t\tu_offset = dec_offset[i];\n\t\t\t\trtw_adjust_chbw(adapter, u_ch, &u_bw, &u_offset);\n\t\t\t\trtw_get_offset_by_chbw(u_ch, u_bw, &u_offset);\n\t\t\t} else {\n\t\t\t\tu8 tmp_ch = dec_ch[i];\n\t\t\t\tu8 tmp_bw = dec_bw[i];\n\t\t\t\tu8 tmp_offset = dec_offset[i];\n\t\t\t\t\n\t\t\t\trtw_adjust_chbw(adapter, tmp_ch, &tmp_bw, &tmp_offset);\n\t\t\t\trtw_get_offset_by_chbw(tmp_ch, tmp_bw, &tmp_offset);\n\n\t\t\t\trtw_warn_on(!rtw_is_chbw_grouped(u_ch, u_bw, u_offset, tmp_ch, tmp_bw, tmp_offset));\n\t\t\t\trtw_sync_chbw(&tmp_ch, &tmp_bw, &tmp_offset, &u_ch, &u_bw, &u_offset);\n\t\t\t}\n\t\t}\n\n\t\t#ifdef CONFIG_RTW_MESH\n\t\t/* if ifbmp are all mesh, apply bw restriction */\n\t\tif (ifbmp_all_mesh)\n\t\t\trtw_mesh_adjust_chbw(u_ch, &u_bw, &u_offset);\n\t\t#endif\n\n\t\tRTW_INFO(\"%s ifbmp:0x%02x tmp union:%u,%u,%u\\n\", __func__, ifbmp, u_ch, u_bw, u_offset);\n\n\t\t/* check if tmp dec union is usable */\n\t\tif (rtw_ap_ch_specific_chk(adapter, u_ch, &u_bw, &u_offset, __func__) == _FAIL) {\n\t\t\t/* channel can't be used */\n\t\t\tif (req_ch > 0) {\n\t\t\t\t/* specific channel and not from IE => don't change channel setting */\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tgoto choose_chbw;\n\t\t} else if (rtw_chset_is_chbw_non_ocp(chset, u_ch, u_bw, u_offset)) {\n\t\t\tRTW_WARN(\"%s DFS channel %u,%u under non ocp\\n\", __func__, u_ch, u_bw);\n\t\t\tif (req_ch > 0 && req_bw > REQ_BW_NONE) {\n\t\t\t\t/* change_chbw with specific channel and specific bw, goto update_bss_chbw directly */\n\t\t\t\tgoto update_bss_chbw;\n\t\t\t}\n\t\t} else\n\t\t\tgoto update_bss_chbw;\n\nchoose_chbw:\n\t\treq_ch = req_ch > 0 ? req_ch : 0;\n\t\tmax_bw = req_bw > REQ_BW_NONE ? req_bw : CHANNEL_WIDTH_20;\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tif (!(ifbmp & BIT(i)) || !dvobj->padapters[i])\n\t\t\t\tcontinue;\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tmlmeext = &(iface->mlmeextpriv);\n\n\t\t\tif (req_bw <= REQ_BW_NONE) {\n\t\t\t\tif (req_bw == REQ_BW_ORI) {\n\t\t\t\t\tif (max_bw < iface->mlmepriv.ori_bw)\n\t\t\t\t\t\tmax_bw = iface->mlmepriv.ori_bw;\n\t\t\t\t} else {\n\t\t\t\t\tif (max_bw < cur_ie_bw[i])\n\t\t\t\t\t\tmax_bw = cur_ie_bw[i];\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (MSTATE_AP_NUM(&mstate) || MSTATE_MESH_NUM(&mstate)) {\n\t\t\t\tif (ori_ch == 0)\n\t\t\t\t\tori_ch = mlmeext->cur_channel;\n\t\t\t\telse if (ori_ch != mlmeext->cur_channel)\n\t\t\t\t\trtw_warn_on(1);\n\t\t\t} else {\n\t\t\t\tif (ori_ch == 0)\n\t\t\t\t\tori_ch = cur_ie_ch[i];\n\t\t\t\telse if (ori_ch != cur_ie_ch[i])\n\t\t\t\t\trtw_warn_on(1);\n\t\t\t}\n\t\t}\n\n\t\tch_avail = rtw_ap_choose_chbw(adapter, req_ch, max_bw\n\t\t\t, ori_ch, &u_ch, &u_bw, &u_offset, ifbmp_all_mesh, __func__);\n\t\tif (ch_avail == _FALSE)\n\t\t\tgoto exit;\n\nupdate_bss_chbw:\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tif (!(ifbmp & BIT(i)) || !dvobj->padapters[i])\n\t\t\t\tcontinue;\n\t\t\tiface = dvobj->padapters[i];\n\n\t\t\tdec_ch[i] = u_ch;\n\t\t\tif (dec_bw[i] > u_bw)\n\t\t\t\tdec_bw[i] = u_bw;\n\t\t\tif (dec_bw[i] == CHANNEL_WIDTH_20)\n\t\t\t\tdec_offset[i] = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t\telse\n\t\t\t\tdec_offset[i] = u_offset;\n\n\t\t\t#ifdef CONFIG_RTW_MESH\n\t\t\tif (MLME_IS_MESH(iface))\n\t\t\t\trtw_mesh_adjust_chbw(dec_ch[i], &dec_bw[i], &dec_offset[i]);\n\t\t\t#endif\n\t\t}\n\n\t\tset_u_ch = _TRUE;\n\t}\n\n\tifbmp_ch_changed = rtw_ap_update_chbw_by_ifbmp(dvobj, ifbmp\n\t\t\t\t\t\t\t, cur_ie_ch, cur_ie_bw, cur_ie_offset\n\t\t\t\t\t\t\t, dec_ch, dec_bw, dec_offset\n\t\t\t\t\t\t\t, __func__);\n\n\tif (u_ch != 0)\n\t\tRTW_INFO(\"%s union:%u,%u,%u\\n\", __func__, u_ch, u_bw, u_offset);\n\n\tif (rtw_mi_check_fwstate(adapter, _FW_UNDER_SURVEY)) {\n\t\t/* scanning, leave ch setting to scan state machine */\n\t\tset_u_ch = _FALSE;\n\t}\n\n\tif (set_u_ch == _TRUE) {\n\t\t*ch = u_ch;\n\t\t*bw = u_bw;\n\t\t*offset = u_offset;\n\t}\nexit:\n\treturn ifbmp_ch_changed;\n}\n\nu8 rtw_ap_sta_states_check(_adapter *adapter)\n{\n\tstruct sta_info *psta;\n\tstruct sta_priv *pstapriv = &adapter->stapriv;\n\t_list *plist, *phead;\n\t_irqL irqL;\n\tu8 rst = _FALSE;\n\n\tif (!MLME_IS_AP(adapter) && !MLME_IS_MESH(adapter))\n\t\treturn _FALSE;\n\n\tif (pstapriv->auth_list_cnt !=0)\n\t\treturn _TRUE;\n\n\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\tphead = &pstapriv->asoc_list;\n\tplist = get_next(phead);\n\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\n\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);\n\t\tplist = get_next(plist);\n\n\t\tif (!(psta->state & _FW_LINKED)) {\n\t\t\tRTW_INFO(ADPT_FMT\"- SoftAP/Mesh - sta under linking, its state = 0x%x\\n\", ADPT_ARG(adapter), psta->state);\n\t\t\trst = _TRUE;\n\t\t\tbreak;\n\t\t} else if (psta->state & WIFI_UNDER_KEY_HANDSHAKE) {\n\t\t\tRTW_INFO(ADPT_FMT\"- SoftAP/Mesh - sta under key handshaking, its state = 0x%x\\n\", ADPT_ARG(adapter), psta->state);\n\t\t\trst = _TRUE;\n\t\t\tbreak;\n\t\t}\n\t}\n\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\treturn rst;\n}\n\n/*#define DBG_SWTIMER_BASED_TXBCN*/\n#ifdef CONFIG_SWTIMER_BASED_TXBCN\nvoid tx_beacon_handlder(struct dvobj_priv *pdvobj)\n{\n#define BEACON_EARLY_TIME\t\t20\t/* unit:TU*/\n\t_irqL irqL;\n\t_list\t*plist, *phead;\n\tu32 timestamp[2];\n\tu32 bcn_interval_us; /* unit : usec */\n\tu64 time;\n\tu32 cur_tick, time_offset; /* unit : usec */\n\tu32 inter_bcn_space_us; /* unit : usec */\n\tu32 txbcn_timer_ms; /* unit : ms */\n\tint nr_vap, idx, bcn_idx;\n\tint i;\n\tu8 val8, late = 0;\n\t_adapter *padapter = NULL;\n\n\ti = 0;\n\n\t/* get first ap mode interface */\n\t_enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL);\n\tif (rtw_is_list_empty(&pdvobj->ap_if_q.queue) || (pdvobj->nr_ap_if == 0)) {\n\t\tRTW_INFO(\"[%s] ERROR: ap_if_q is empty!or nr_ap = %d\\n\", __func__, pdvobj->nr_ap_if);\n\t\t_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);\n\t\treturn;\n\t} else\n\t\tpadapter = LIST_CONTAINOR(get_next(&(pdvobj->ap_if_q.queue)), struct _ADAPTER, list);\n\t_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);\n\n\tif (NULL == padapter) {\n\t\tRTW_INFO(\"[%s] ERROR: no any ap interface!\\n\", __func__);\n\t\treturn;\n\t}\n\n\n\tbcn_interval_us = DEFAULT_BCN_INTERVAL * NET80211_TU_TO_US;\n\tif (0 == bcn_interval_us) {\n\t\tRTW_INFO(\"[%s] ERROR: beacon interval = 0\\n\", __func__);\n\t\treturn;\n\t}\n\n\t/* read TSF */\n\ttimestamp[1] = rtw_read32(padapter, 0x560 + 4);\n\ttimestamp[0] = rtw_read32(padapter, 0x560);\n\twhile (timestamp[1]) {\n\t\ttime = (0xFFFFFFFF % bcn_interval_us + 1) * timestamp[1] + timestamp[0];\n\t\ttimestamp[0] = (u32)time;\n\t\ttimestamp[1] = (u32)(time >> 32);\n\t}\n\tcur_tick = timestamp[0] % bcn_interval_us;\n\n\n\t_enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL);\n\n\tnr_vap = (pdvobj->nr_ap_if - 1);\n\tif (nr_vap > 0) {\n\t\tinter_bcn_space_us = pdvobj->inter_bcn_space * NET80211_TU_TO_US; /* beacon_interval / (nr_vap+1); */\n\t\tidx = cur_tick / inter_bcn_space_us;\n\t\tif (idx < nr_vap)\t/* if (idx < (nr_vap+1))*/\n\t\t\tbcn_idx = idx + 1;\t/* bcn_idx = (idx + 1) % (nr_vap+1);*/\n\t\telse\n\t\t\tbcn_idx = 0;\n\n\t\t/* to get padapter based on bcn_idx */\n\t\tpadapter = NULL;\n\t\tphead = get_list_head(&pdvobj->ap_if_q);\n\t\tplist = get_next(phead);\n\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\tpadapter = LIST_CONTAINOR(plist, struct _ADAPTER, list);\n\n\t\t\tplist = get_next(plist);\n\n\t\t\tif (i == bcn_idx)\n\t\t\t\tbreak;\n\n\t\t\ti++;\n\t\t}\n\t\tif ((NULL == padapter) || (i > pdvobj->nr_ap_if)) {\n\t\t\tRTW_INFO(\"[%s] ERROR: nr_ap_if = %d, padapter=%p, bcn_idx=%d, index=%d\\n\",\n\t\t\t\t__func__, pdvobj->nr_ap_if, padapter, bcn_idx, i);\n\t\t\t_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);\n\t\t\treturn;\n\t\t}\n#ifdef DBG_SWTIMER_BASED_TXBCN\n\t\tRTW_INFO(\"BCN_IDX=%d, cur_tick=%d, padapter=%p\\n\", bcn_idx, cur_tick, padapter);\n#endif\n\t\tif (((idx + 2 == nr_vap + 1) && (idx < nr_vap + 1)) || (0 == bcn_idx)) {\n\t\t\ttime_offset = bcn_interval_us - cur_tick - BEACON_EARLY_TIME * NET80211_TU_TO_US;\n\t\t\tif ((s32)time_offset < 0)\n\t\t\t\ttime_offset += inter_bcn_space_us;\n\n\t\t} else {\n\t\t\ttime_offset = (idx + 2) * inter_bcn_space_us - cur_tick - BEACON_EARLY_TIME * NET80211_TU_TO_US;\n\t\t\tif (time_offset > (inter_bcn_space_us + (inter_bcn_space_us >> 1))) {\n\t\t\t\ttime_offset -= inter_bcn_space_us;\n\t\t\t\tlate = 1;\n\t\t\t}\n\t\t}\n\t} else\n\t\t/*#endif*/ { /* MBSSID */\n\t\ttime_offset = 2 * bcn_interval_us - cur_tick - BEACON_EARLY_TIME * NET80211_TU_TO_US;\n\t\tif (time_offset > (bcn_interval_us + (bcn_interval_us >> 1))) {\n\t\t\ttime_offset -= bcn_interval_us;\n\t\t\tlate = 1;\n\t\t}\n\t}\n\t_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);\n\n#ifdef DBG_SWTIMER_BASED_TXBCN\n\tRTW_INFO(\"set sw bcn timer %d us\\n\", time_offset);\n#endif\n\ttxbcn_timer_ms = time_offset / NET80211_TU_TO_US;\n\t_set_timer(&pdvobj->txbcn_timer, txbcn_timer_ms);\n\n\tif (padapter) {\n#ifdef CONFIG_BCN_RECOVERY\n\t\trtw_ap_bcn_recovery(padapter);\n#endif /*CONFIG_BCN_RECOVERY*/\n\n#ifdef CONFIG_BCN_XMIT_PROTECT\n\t\trtw_ap_bcn_queue_empty_check(padapter, txbcn_timer_ms);\n#endif /*CONFIG_BCN_XMIT_PROTECT*/\n\n#ifdef DBG_SWTIMER_BASED_TXBCN\n\t\tRTW_INFO(\"padapter=%p, PORT=%d\\n\", padapter, padapter->hw_port);\n#endif\n\t\t/* bypass TX BCN queue if op ch is switching/waiting */\n\t\tif (!check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING)\n\t\t\t&& !IS_CH_WAITING(adapter_to_rfctl(padapter))\n\t\t) {\n\t\t\t/*update_beacon(padapter, _TIM_IE_, NULL, _FALSE, 0);*/\n\t\t\t/*issue_beacon(padapter, 0);*/\n\t\t\tsend_beacon(padapter);\n\t\t}\n\t}\n\n#if 0\n\t/* handle any buffered BC/MC frames*/\n\t/* Don't dynamically change DIS_ATIM due to HW will auto send ACQ after HIQ empty.*/\n\tval8 = *((unsigned char *)priv->beaconbuf + priv->timoffset + 4);\n\tif (val8 & 0x01) {\n\t\tprocess_mcast_dzqueue(priv);\n\t\tpriv->pkt_in_dtimQ = 0;\n\t}\n#endif\n\n}\n\nvoid tx_beacon_timer_handlder(void *ctx)\n{\n\tstruct dvobj_priv *pdvobj = (struct dvobj_priv *)ctx;\n\t_adapter *padapter = pdvobj->padapters[0];\n\n\tif (padapter)\n\t\tset_tx_beacon_cmd(padapter, 0);\n}\n#endif\n\nvoid rtw_ap_parse_sta_capability(_adapter *adapter, struct sta_info *sta, u8 *cap)\n{\n\tsta->capability = RTW_GET_LE16(cap);\n\tif (sta->capability & WLAN_CAPABILITY_SHORT_PREAMBLE)\n\t\tsta->flags |= WLAN_STA_SHORT_PREAMBLE;\n\telse\n\t\tsta->flags &= ~WLAN_STA_SHORT_PREAMBLE;\n}\n\nu16 rtw_ap_parse_sta_supported_rates(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len)\n{\n\tu8 rate_set[12];\n\tu8 rate_num;\n\tint i;\n\tu16 status = _STATS_SUCCESSFUL_;\n\n\trtw_ies_get_supported_rate(tlv_ies, tlv_ies_len, rate_set, &rate_num);\n\tif (rate_num == 0) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" sta \"MAC_FMT\" with no supported rate\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));\n\t\tstatus = _STATS_FAILURE_;\n\t\tgoto exit;\n\t}\n\n\t_rtw_memcpy(sta->bssrateset, rate_set, rate_num);\n\tsta->bssratelen = rate_num;\n\n\tif (MLME_IS_AP(adapter)) {\n\t\t/* this function force only CCK rates to be bassic rate... */\n\t\tUpdateBrateTblForSoftAP(sta->bssrateset, sta->bssratelen);\n\t}\n\n\t/* if (hapd->iface->current_mode->mode == HOSTAPD_MODE_IEEE80211G) */ /* ? */\n\tsta->flags |= WLAN_STA_NONERP;\n\tfor (i = 0; i < sta->bssratelen; i++) {\n\t\tif ((sta->bssrateset[i] & 0x7f) > 22) {\n\t\t\tsta->flags &= ~WLAN_STA_NONERP;\n\t\t\tbreak;\n\t\t}\n\t}\n\nexit:\n\treturn status;\n}\n\nu16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems)\n{\n\tstruct security_priv *sec = &adapter->securitypriv;\n\tu8 *wpa_ie;\n\tint wpa_ie_len;\n\tint group_cipher = 0, pairwise_cipher = 0;\n\tu32 akm = 0;\n\tu8 mfp_opt = MFP_NO;\n\tu16 status = _STATS_SUCCESSFUL_;\n\n\tsta->dot8021xalg = 0;\n\tsta->wpa_psk = 0;\n\tsta->wpa_group_cipher = 0;\n\tsta->wpa2_group_cipher = 0;\n\tsta->wpa_pairwise_cipher = 0;\n\tsta->wpa2_pairwise_cipher = 0;\n\t_rtw_memset(sta->wpa_ie, 0, sizeof(sta->wpa_ie));\n\n\tif ((sec->wpa_psk & BIT(1)) && elems->rsn_ie) {\n\t\twpa_ie = elems->rsn_ie;\n\t\twpa_ie_len = elems->rsn_ie_len;\n\n\t\tif (rtw_parse_wpa2_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, &akm, &mfp_opt) == _SUCCESS) {\n\t\t\tsta->dot8021xalg = 1;/* psk, todo:802.1x */\n\t\t\tsta->wpa_psk |= BIT(1);\n\n\t\t\tsta->wpa2_group_cipher = group_cipher & sec->wpa2_group_cipher;\n\t\t\tsta->wpa2_pairwise_cipher = pairwise_cipher & sec->wpa2_pairwise_cipher;\n\n\t\t\tsta->akm_suite_type = akm;\n\t\t\tif ((CHECK_BIT(WLAN_AKM_TYPE_SAE, akm)) && (MFP_NO == mfp_opt))\n\t\t\t\tstatus = WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION;\n\n\t\t\tif (!sta->wpa2_group_cipher)\n\t\t\t\tstatus = WLAN_STATUS_GROUP_CIPHER_NOT_VALID;\n\n\t\t\tif (!sta->wpa2_pairwise_cipher)\n\t\t\t\tstatus = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID;\n\t\t} else\n\t\t\tstatus = WLAN_STATUS_INVALID_IE;\n\n\t}\n\telse if ((sec->wpa_psk & BIT(0)) && elems->wpa_ie) {\n\t\twpa_ie = elems->wpa_ie;\n\t\twpa_ie_len = elems->wpa_ie_len;\n\n\t\tif (rtw_parse_wpa_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {\n\t\t\tsta->dot8021xalg = 1;/* psk, todo:802.1x */\n\t\t\tsta->wpa_psk |= BIT(0);\n\n\t\t\tsta->wpa_group_cipher = group_cipher & sec->wpa_group_cipher;\n\t\t\tsta->wpa_pairwise_cipher = pairwise_cipher & sec->wpa_pairwise_cipher;\n\n\t\t\tif (!sta->wpa_group_cipher)\n\t\t\t\tstatus = WLAN_STATUS_GROUP_CIPHER_NOT_VALID;\n\n\t\t\tif (!sta->wpa_pairwise_cipher)\n\t\t\t\tstatus = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID;\n\t\t} else\n\t\t\tstatus = WLAN_STATUS_INVALID_IE;\n\n\t} else {\n\t\twpa_ie = NULL;\n\t\twpa_ie_len = 0;\n\t}\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(adapter)) {\n\t\t/* MFP is mandatory for secure mesh */\n\t\tif (adapter->mesh_info.mesh_auth_id)\n\t\t\tsta->flags |= WLAN_STA_MFP;\n\t} else\n#endif\n\tif ((sec->mfp_opt == MFP_REQUIRED && mfp_opt == MFP_NO) || mfp_opt == MFP_INVALID) \n\t\tstatus = WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION;\n\telse if (sec->mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL)\n\t\tsta->flags |= WLAN_STA_MFP;\n\n\tif ((sec->auth_type == NL80211_AUTHTYPE_SAE) &&\n\t\t(CHECK_BIT(WLAN_AKM_TYPE_SAE, sta->akm_suite_type)) &&\n\t\t(WLAN_AUTH_OPEN == sta->authalg)) {\n\t\t/* WPA3-SAE, PMK caching */\n\t\tif (rtw_cached_pmkid(adapter, sta->cmn.mac_addr) == -1) {\n\t\t\tRTW_INFO(\"SAE: No PMKSA cache entry found\\n\");\n\t\t\tstatus = WLAN_STATUS_INVALID_PMKID;\n\t\t} else {\n\t\t\tRTW_INFO(\"SAE: PMKSA cache entry found\\n\");\n\t\t}\n\t}\n\n\tif (status != _STATS_SUCCESSFUL_)\n\t\tgoto exit;\n\n\tif (!MLME_IS_AP(adapter))\n\t\tgoto exit;\n\n\tsta->flags &= ~(WLAN_STA_WPS | WLAN_STA_MAYBE_WPS);\n\t/* if (hapd->conf->wps_state && wpa_ie == NULL) { */ /* todo: to check ap if supporting WPS */\n\tif (wpa_ie == NULL) {\n\t\tif (elems->wps_ie) {\n\t\t\tRTW_INFO(\"STA included WPS IE in \"\n\t\t\t\t \"(Re)Association Request - assume WPS is \"\n\t\t\t\t \"used\\n\");\n\t\t\tsta->flags |= WLAN_STA_WPS;\n\t\t\t/* wpabuf_free(sta->wps_ie); */\n\t\t\t/* sta->wps_ie = wpabuf_alloc_copy(elems.wps_ie + 4, */\n\t\t\t/*\t\t\t\telems.wps_ie_len - 4); */\n\t\t} else {\n\t\t\tRTW_INFO(\"STA did not include WPA/RSN IE \"\n\t\t\t\t \"in (Re)Association Request - possible WPS \"\n\t\t\t\t \"use\\n\");\n\t\t\tsta->flags |= WLAN_STA_MAYBE_WPS;\n\t\t}\n\n\t\t/* AP support WPA/RSN, and sta is going to do WPS, but AP is not ready */\n\t\t/* that the selected registrar of AP is _FLASE */\n\t\tif ((sec->wpa_psk > 0)\n\t\t\t&& (sta->flags & (WLAN_STA_WPS | WLAN_STA_MAYBE_WPS))\n\t\t) {\n\t\t\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\n\t\t\tif (mlme->wps_beacon_ie) {\n\t\t\t\tu8 selected_registrar = 0;\n\n\t\t\t\trtw_get_wps_attr_content(mlme->wps_beacon_ie, mlme->wps_beacon_ie_len, WPS_ATTR_SELECTED_REGISTRAR, &selected_registrar, NULL);\n\n\t\t\t\tif (!selected_registrar) {\n\t\t\t\t\tRTW_INFO(\"selected_registrar is _FALSE , or AP is not ready to do WPS\\n\");\n\t\t\t\t\tstatus = _STATS_UNABLE_HANDLE_STA_;\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t} else {\n\t\tint copy_len;\n\n\t\tif (sec->wpa_psk == 0) {\n\t\t\tRTW_INFO(\"STA \" MAC_FMT\n\t\t\t\t\": WPA/RSN IE in association request, but AP don't support WPA/RSN\\n\",\n\t\t\t\tMAC_ARG(sta->cmn.mac_addr));\n\t\t\tstatus = WLAN_STATUS_INVALID_IE;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (elems->wps_ie) {\n\t\t\tRTW_INFO(\"STA included WPS IE in \"\n\t\t\t\t \"(Re)Association Request - WPS is \"\n\t\t\t\t \"used\\n\");\n\t\t\tsta->flags |= WLAN_STA_WPS;\n\t\t\tcopy_len = 0;\n\t\t} else\n\t\t\tcopy_len = ((wpa_ie_len + 2) > sizeof(sta->wpa_ie)) ? (sizeof(sta->wpa_ie)) : (wpa_ie_len + 2);\n\n\t\tif (copy_len > 0)\n\t\t\t_rtw_memcpy(sta->wpa_ie, wpa_ie - 2, copy_len);\n\t}\n\nexit:\n\treturn status;\n}\n\nvoid rtw_ap_parse_sta_wmm_ie(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len)\n{\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\tunsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01};\n\tu8 *p;\n\n\tsta->flags &= ~WLAN_STA_WME;\n\tsta->qos_option = 0;\n\tsta->qos_info = 0;\n\tsta->has_legacy_ac = _TRUE;\n\tsta->uapsd_vo = 0;\n\tsta->uapsd_vi = 0;\n\tsta->uapsd_be = 0;\n\tsta->uapsd_bk = 0;\n\n\tif (!mlme->qospriv.qos_option)\n\t\tgoto exit;\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(adapter)) {\n\t\t/* QoS is mandatory in mesh */\n\t\tsta->flags |= WLAN_STA_WME;\n\t}\n#endif\n\n\tp = rtw_get_ie_ex(tlv_ies, tlv_ies_len, WLAN_EID_VENDOR_SPECIFIC, WMM_IE, 6, NULL, NULL);\n\tif (!p)\n\t\tgoto exit;\n\n\tsta->flags |= WLAN_STA_WME;\n\tsta->qos_option = 1;\n\tsta->qos_info = *(p + 8);\n\tsta->max_sp_len = (sta->qos_info >> 5) & 0x3;\n\n\tif ((sta->qos_info & 0xf) != 0xf)\n\t\tsta->has_legacy_ac = _TRUE;\n\telse\n\t\tsta->has_legacy_ac = _FALSE;\n\n\tif (sta->qos_info & 0xf) {\n\t\tif (sta->qos_info & BIT(0))\n\t\t\tsta->uapsd_vo = BIT(0) | BIT(1);\n\t\telse\n\t\t\tsta->uapsd_vo = 0;\n\n\t\tif (sta->qos_info & BIT(1))\n\t\t\tsta->uapsd_vi = BIT(0) | BIT(1);\n\t\telse\n\t\t\tsta->uapsd_vi = 0;\n\n\t\tif (sta->qos_info & BIT(2))\n\t\t\tsta->uapsd_bk = BIT(0) | BIT(1);\n\t\telse\n\t\t\tsta->uapsd_bk = 0;\n\n\t\tif (sta->qos_info & BIT(3))\n\t\t\tsta->uapsd_be = BIT(0) | BIT(1);\n\t\telse\n\t\t\tsta->uapsd_be = 0;\n\t}\n\nexit:\n\treturn;\n}\n\nvoid rtw_ap_parse_sta_ht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems)\n{\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\n\tsta->flags &= ~WLAN_STA_HT;\n\n#ifdef CONFIG_80211N_HT\n\tif (mlme->htpriv.ht_option == _FALSE)\n\t\tgoto exit;\n\n\t/* save HT capabilities in the sta object */\n\t_rtw_memset(&sta->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap));\n\tif (elems->ht_capabilities && elems->ht_capabilities_len >= sizeof(struct rtw_ieee80211_ht_cap)) {\n\t\tsta->flags |= WLAN_STA_HT;\n\t\tsta->flags |= WLAN_STA_WME;\n\t\t_rtw_memcpy(&sta->htpriv.ht_cap, elems->ht_capabilities, sizeof(struct rtw_ieee80211_ht_cap));\n\n\t\tif (elems->ht_operation && elems->ht_operation_len == HT_OP_IE_LEN) {\n\t\t\t_rtw_memcpy(sta->htpriv.ht_op, elems->ht_operation, HT_OP_IE_LEN);\n\t\t\tsta->htpriv.op_present = 1;\n\t\t}\n\t}\nexit:\n#endif\n\n\treturn;\n}\n\nvoid rtw_ap_parse_sta_vht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems)\n{\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\n\tsta->flags &= ~WLAN_STA_VHT;\n\n#ifdef CONFIG_80211AC_VHT\n\tif (mlme->vhtpriv.vht_option == _FALSE)\n\t\tgoto exit;\n\n\t_rtw_memset(&sta->vhtpriv, 0, sizeof(struct vht_priv));\n\tif (elems->vht_capabilities && elems->vht_capabilities_len == VHT_CAP_IE_LEN) {\n\t\tsta->flags |= WLAN_STA_VHT;\n\t\t_rtw_memcpy(sta->vhtpriv.vht_cap, elems->vht_capabilities, VHT_CAP_IE_LEN);\n\n\t\tif (elems->vht_operation && elems->vht_operation_len== VHT_OP_IE_LEN) {\n\t\t\t_rtw_memcpy(sta->vhtpriv.vht_op, elems->vht_operation, VHT_OP_IE_LEN);\n\t\t\tsta->vhtpriv.op_present = 1;\n\t\t}\n\n\t\tif (elems->vht_op_mode_notify && elems->vht_op_mode_notify_len == 1) {\n\t\t\t_rtw_memcpy(&sta->vhtpriv.vht_op_mode_notify, elems->vht_op_mode_notify, 1);\n\t\t\tsta->vhtpriv.notify_present = 1;\n\t\t}\n\t}\nexit:\n#endif\n\n\treturn;\n}\n#endif /* CONFIG_AP_MODE */\n\n"
  },
  {
    "path": "core/rtw_beamforming.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_BEAMFORMING_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\n#ifdef CONFIG_BEAMFORMING\n\n#ifdef RTW_BEAMFORMING_VERSION_2\n\nstruct ndpa_sta_info {\n\tu16 aid:12;\n\tu16 feedback_type:1;\n\tu16 nc_index:3;\n};\n\nstatic void _get_txvector_parameter(PADAPTER adapter, struct sta_info *sta, u8 *g_id, u16 *p_aid)\n{\n\tstruct mlme_priv *mlme;\n\tu16 aid;\n\tu8 *bssid;\n\tu16 val16;\n\tu8 i;\n\n\n\tmlme = &adapter->mlmepriv;\n\n\tif (check_fwstate(mlme, WIFI_AP_STATE)) {\n\t\t/*\n\t\t * Sent by an AP and addressed to a STA associated with that AP\n\t\t * or sent by a DLS or TDLS STA in a direct path to\n\t\t * a DLS or TDLS peer STA\n\t\t */\n\n\t\taid = sta->cmn.aid;\n\t\tbssid = adapter_mac_addr(adapter);\n\t\tRTW_INFO(\"%s: AID=0x%x BSSID=\" MAC_FMT \"\\n\",\n\t\t\t __FUNCTION__, sta->cmn.aid, MAC_ARG(bssid));\n\n\t\t/* AID[0:8] */\n\t\taid &= 0x1FF;\n\t\t/* BSSID[44:47] xor BSSID[40:43] */\n\t\tval16 = ((bssid[5] & 0xF0) >> 4) ^ (bssid[5] & 0xF);\n\t\t/* (dec(AID[0:8]) + dec(BSSID)*2^5) mod 2^9 */\n\t\t*p_aid = (aid + (val16 << 5)) & 0x1FF;\n\t\t*g_id = 63;\n\t} else if ((check_fwstate(mlme, WIFI_ADHOC_STATE) == _TRUE)\n\t\t   || (check_fwstate(mlme, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {\n\t\t/*\n\t\t * Otherwise, includes\n\t\t * 1. Sent to an IBSS STA\n\t\t * 2. Sent by an AP to a non associated STA\n\t\t * 3. Sent to a STA for which it is not known\n\t\t *    which condition is applicable\n\t\t */\n\t\t*p_aid = 0;\n\t\t*g_id = 63;\n\t} else {\n\t\t/* Addressed to AP */\n\t\tbssid = sta->cmn.mac_addr;\n\t\tRTW_INFO(\"%s: BSSID=\" MAC_FMT \"\\n\", __FUNCTION__, MAC_ARG(bssid));\n\n\t\t/* BSSID[39:47] */\n\t\t*p_aid = (bssid[5] << 1) | (bssid[4] >> 7);\n\t\t*g_id = 0;\n\t}\n\n\tRTW_INFO(\"%s: GROUP_ID=0x%02x PARTIAL_AID=0x%04x\\n\",\n\t\t __FUNCTION__, *g_id, *p_aid);\n}\n\n/*\n * Parameters\n *\tadapter\t\tstruct _adapter*\n *\tsta\t\tstruct sta_info*\n *\tsta_bf_cap\tbeamforming capabe of sta\n *\tsounding_dim\tNumber of Sounding Dimensions\n *\tcomp_steering\tCompressed Steering Number of Beamformer Antennas Supported\n */\nstatic void _get_sta_beamform_cap(PADAPTER adapter, struct sta_info *sta,\n\tu8 *sta_bf_cap, u8 *sounding_dim, u8 *comp_steering)\n{\n\tstruct beamforming_info *info;\n\tstruct ht_priv *ht;\n#ifdef CONFIG_80211AC_VHT\n\tstruct vht_priv *vht;\n#endif /* CONFIG_80211AC_VHT */\n\tu16 bf_cap;\n\n\n\t*sta_bf_cap = 0;\n\t*sounding_dim = 0;\n\t*comp_steering = 0;\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tht = &adapter->mlmepriv.htpriv;\n#ifdef CONFIG_80211AC_VHT\n\tvht = &adapter->mlmepriv.vhtpriv;\n#endif /* CONFIG_80211AC_VHT */\n\n\tif (is_supported_ht(sta->wireless_mode) == _TRUE) {\n\t\t/* HT */\n\t\tbf_cap = ht->beamform_cap;\n\n\t\tif (TEST_FLAG(bf_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) {\n\t\t\tinfo->beamforming_cap |= BEAMFORMEE_CAP_HT_EXPLICIT;\n\t\t\t*sta_bf_cap |= BEAMFORMER_CAP_HT_EXPLICIT;\n\t\t\t*sounding_dim = (bf_cap & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6;\n\t\t}\n\t\tif (TEST_FLAG(bf_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {\n\t\t\tinfo->beamforming_cap |= BEAMFORMER_CAP_HT_EXPLICIT;\n\t\t\t*sta_bf_cap |= BEAMFORMEE_CAP_HT_EXPLICIT;\n\t\t\t*comp_steering = (bf_cap & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4;\n\t\t}\n\t}\n\n#ifdef CONFIG_80211AC_VHT\n\tif (is_supported_vht(sta->wireless_mode) == _TRUE) {\n\t\t/* VHT */\n\t\tbf_cap = vht->beamform_cap;\n\n\t\t/* We are SU Beamformee because the STA is SU Beamformer */\n\t\tif (TEST_FLAG(bf_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {\n\t\t\tinfo->beamforming_cap |= BEAMFORMEE_CAP_VHT_SU;\n\t\t\t*sta_bf_cap |= BEAMFORMER_CAP_VHT_SU;\n\n\t\t\t/* We are MU Beamformee because the STA is MU Beamformer */\n\t\t\tif (TEST_FLAG(bf_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) {\n\t\t\t\tinfo->beamforming_cap |= BEAMFORMEE_CAP_VHT_MU;\n\t\t\t\t*sta_bf_cap |= BEAMFORMER_CAP_VHT_MU;\n\t\t\t}\n\n\t\t\t*sounding_dim = (bf_cap & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12;\n\t\t}\n\t\t/* We are SU Beamformer because the STA is SU Beamformee */\n\t\tif (TEST_FLAG(bf_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {\n\t\t\tinfo->beamforming_cap |= BEAMFORMER_CAP_VHT_SU;\n\t\t\t*sta_bf_cap |= BEAMFORMEE_CAP_VHT_SU;\n\n\t\t\t/* We are MU Beamformer because the STA is MU Beamformee */\n\t\t\tif (TEST_FLAG(bf_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) {\n\t\t\t\tinfo->beamforming_cap |= BEAMFORMER_CAP_VHT_MU;\n\t\t\t\t*sta_bf_cap |= BEAMFORMEE_CAP_VHT_MU;\n\t\t\t}\n\n\t\t\t*comp_steering = (bf_cap & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8;\n\t\t}\n\t}\n#endif /* CONFIG_80211AC_VHT */\n}\n\nstatic u8 _send_ht_ndpa_packet(PADAPTER adapter, u8 *ra, enum channel_width bw)\n{\n\t/* General */\n\tstruct xmit_priv\t\t*pxmitpriv;\n\tstruct mlme_ext_priv\t\t*pmlmeext;\n\tstruct mlme_ext_info\t\t*pmlmeinfo;\n\tstruct xmit_frame\t\t*pmgntframe;\n\t/* Beamforming */\n\tstruct beamforming_info\t\t*info;\n\tstruct beamformee_entry\t\t*bfee;\n\tstruct ndpa_sta_info\t\tsta_info;\n\tu8 ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xE0, 0x4C};\n\t/* MISC */\n\tstruct pkt_attrib\t\t*attrib;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tenum MGN_RATE txrate;\n\tu8 *pframe;\n\tu16 duration = 0;\n\tu8 aSifsTime = 0;\n\n\n\tRTW_INFO(\"+%s: Send to \" MAC_FMT \"\\n\", __FUNCTION__, MAC_ARG(ra));\n\n\tpxmitpriv = &adapter->xmitpriv;\n\tpmlmeext = &adapter->mlmeextpriv;\n\tpmlmeinfo = &pmlmeext->mlmext_info;\n\tbfee = rtw_bf_bfee_get_entry_by_addr(adapter, ra);\n\tif (!bfee) {\n\t\tRTW_ERR(\"%s: Cann't find beamformee entry!\\n\", __FUNCTION__);\n\t\treturn _FALSE;\n\t}\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (!pmgntframe) {\n\t\tRTW_ERR(\"%s: alloc mgnt frame fail!\\n\", __FUNCTION__);\n\t\treturn _FALSE;\n\t}\n\n\ttxrate = beamforming_get_htndp_tx_rate(GET_PDM_ODM(adapter), bfee->comp_steering_num_of_bfer);\n\n\t/* update attribute */\n\tattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(adapter, attrib);\n\t/*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */\n\tattrib->subtype = WIFI_ACTION_NOACK;\n\tattrib->bwmode = bw;\n\t/*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */\n\tattrib->order = 1;\n\tattrib->rate = (u8)txrate;\n\tattrib->bf_pkt_type = 0;\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\t/* Frame control */\n\tpwlanhdr->frame_ctl = 0;\n\tset_frame_sub_type(pframe, attrib->subtype);\n\tset_order_bit(pframe);\n\n\t/* Duration */\n\tif (pmlmeext->cur_wireless_mode == WIRELESS_11B)\n\t\taSifsTime = 10;\n\telse\n\t\taSifsTime = 16;\n\tduration = 2 * aSifsTime + 40;\n\tif (bw == CHANNEL_WIDTH_40)\n\t\tduration += 87;\n\telse\n\t\tduration += 180;\n\tset_duration(pframe, duration);\n\n\t/* DA */\n\t_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);\n\t/* SA */\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);\n\t/* BSSID */\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);\n\n\t/* HT control field */\n\tSET_HT_CTRL_CSI_STEERING(pframe + 24, 3);\n\tSET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1);\n\n\t/*\n\t * Frame Body\n\t * Category field: vender-specific value, 0x7F\n\t * OUI: 0x00E04C\n\t */\n\t_rtw_memcpy(pframe + 28, ActionHdr, 4);\n\n\tattrib->pktlen = 32;\n\tattrib->last_txcmdsz = attrib->pktlen;\n\n\tdump_mgntframe(adapter, pmgntframe);\n\n\treturn _TRUE;\n}\n\nstatic u8 _send_vht_ndpa_packet(PADAPTER adapter, u8 *ra, u16 aid, enum channel_width bw)\n{\n\t/* General */\n\tstruct xmit_priv\t\t*pxmitpriv;\n\tstruct mlme_ext_priv\t\t*pmlmeext;\n\tstruct xmit_frame\t\t*pmgntframe;\n\t/* Beamforming */\n\tstruct beamforming_info\t\t*info;\n\tstruct beamformee_entry\t\t*bfee;\n\tstruct ndpa_sta_info\t\tsta_info;\n\t/* MISC */\n\tstruct pkt_attrib\t\t*attrib;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tu8 *pframe;\n\tenum MGN_RATE txrate;\n\tu16 duration = 0;\n\tu8 sequence = 0, aSifsTime = 0;\n\n\n\tRTW_INFO(\"+%s: Send to \" MAC_FMT \"\\n\", __FUNCTION__, MAC_ARG(ra));\n\n\tpxmitpriv = &adapter->xmitpriv;\n\tpmlmeext = &adapter->mlmeextpriv;\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tbfee = rtw_bf_bfee_get_entry_by_addr(adapter, ra);\n\tif (!bfee) {\n\t\tRTW_ERR(\"%s: Cann't find beamformee entry!\\n\", __FUNCTION__);\n\t\treturn _FALSE;\n\t}\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (!pmgntframe) {\n\t\tRTW_ERR(\"%s: alloc mgnt frame fail!\\n\", __FUNCTION__);\n\t\treturn _FALSE;\n\t}\n\n\ttxrate = beamforming_get_vht_ndp_tx_rate(GET_PDM_ODM(adapter), bfee->comp_steering_num_of_bfer);\n\n\t/* update attribute */\n\tattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(adapter, attrib);\n\t/*pattrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */\n\tattrib->subtype = WIFI_NDPA;\n\tattrib->bwmode = bw;\n\t/*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */\n\tattrib->rate = (u8)txrate;\n\tattrib->bf_pkt_type = 0;\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET);\n\tpframe = pmgntframe->buf_addr + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\t/* Frame control */\n\tpwlanhdr->frame_ctl = 0;\n\tset_frame_sub_type(pframe, attrib->subtype);\n\n\t/* Duration */\n\tif (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))\n\t\taSifsTime = 16;\n\telse\n\t\taSifsTime = 10;\n\tduration = 2 * aSifsTime + 44;\n\tif (bw == CHANNEL_WIDTH_80)\n\t\tduration += 40;\n\telse if (bw == CHANNEL_WIDTH_40)\n\t\tduration += 87;\n\telse\n\t\tduration += 180;\n\tset_duration(pframe, duration);\n\n\t/* RA */\n\t_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);\n\n\t/* TA */\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);\n\n\t/* Sounding Sequence, bit0~1 is reserved */\n\tsequence = info->sounding_sequence << 2;\n\tif (info->sounding_sequence >= 0x3f)\n\t\tinfo->sounding_sequence = 0;\n\telse\n\t\tinfo->sounding_sequence++;\n\t_rtw_memcpy(pframe + 16, &sequence, 1);\n\n\t/* STA Info */\n\t/*\n\t * \"AID12\" Equal to 0 if the STA is an AP, mesh STA or\n\t * STA that is a member of an IBSS\n\t */\n\tif (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _FALSE)\n\t\taid = 0;\n\tsta_info.aid = aid;\n\t/* \"Feedback Type\" set to 0 for SU */\n\tsta_info.feedback_type = 0;\n\t/* \"Nc Index\" reserved if the Feedback Type field indicates SU */\n\tsta_info.nc_index = 0;\n\t_rtw_memcpy(pframe + 17, (u8 *)&sta_info, 2);\n\n\tattrib->pktlen = 19;\n\tattrib->last_txcmdsz = attrib->pktlen;\n\n\tdump_mgntframe(adapter, pmgntframe);\n\n\treturn _TRUE;\n}\n\nstatic u8 _send_vht_mu_ndpa_packet(PADAPTER adapter, enum channel_width bw)\n{\n\t/* General */\n\tstruct xmit_priv\t\t*pxmitpriv;\n\tstruct mlme_ext_priv\t\t*pmlmeext;\n\tstruct xmit_frame\t\t*pmgntframe;\n\t/* Beamforming */\n\tstruct beamforming_info\t\t*info;\n\tstruct sounding_info\t\t*sounding;\n\tstruct beamformee_entry\t\t*bfee;\n\tstruct ndpa_sta_info\t\tsta_info;\n\t/* MISC */\n\tstruct pkt_attrib\t\t*attrib;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tenum MGN_RATE txrate;\n\tu8 *pframe;\n\tu8 *ra = NULL;\n\tu16 duration = 0;\n\tu8 sequence = 0, aSifsTime = 0;\n\tu8 i;\n\n\n\tRTW_INFO(\"+%s\\n\", __FUNCTION__);\n\n\tpxmitpriv = &adapter->xmitpriv;\n\tpmlmeext = &adapter->mlmeextpriv;\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tsounding = &info->sounding_info;\n\n\ttxrate = MGN_VHT2SS_MCS0;\n\n\t/*\n\t * Fill the first MU BFee entry (STA1) MAC addr to destination address then\n\t * HW will change A1 to broadcast addr.\n\t * 2015.05.28. Suggested by SD1 Chunchu.\n\t */\n\tbfee = &info->bfee_entry[sounding->mu_sounding_list[0]];\n\tra = bfee->mac_addr;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (!pmgntframe) {\n\t\tRTW_ERR(\"%s: alloc mgnt frame fail!\\n\", __FUNCTION__);\n\t\treturn _FALSE;\n\t}\n\n\t/* update attribute */\n\tattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(adapter, attrib);\n\t/*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */\n\tattrib->subtype = WIFI_NDPA;\n\tattrib->bwmode = bw;\n\t/*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */\n\tattrib->rate = (u8)txrate;\n\t/* Set TxBFPktType of Tx desc to unicast type if there is only one MU STA for HW design */\n\tif (info->sounding_info.candidate_mu_bfee_cnt > 1)\n\t\tattrib->bf_pkt_type = 1;\n\telse\n\t\tattrib->bf_pkt_type = 0;\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET);\n\tpframe = pmgntframe->buf_addr + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\t/* Frame control */\n\tpwlanhdr->frame_ctl = 0;\n\tset_frame_sub_type(pframe, attrib->subtype);\n\n\t/* Duration */\n\tif (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))\n\t\taSifsTime = 16;\n\telse\n\t\taSifsTime = 10;\n\tduration = 2 * aSifsTime + 44;\n\tif (bw == CHANNEL_WIDTH_80)\n\t\tduration += 40;\n\telse if (bw == CHANNEL_WIDTH_40)\n\t\tduration += 87;\n\telse\n\t\tduration += 180;\n\tset_duration(pframe, duration);\n\n\t/* RA */\n\t_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);\n\n\t/* TA */\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);\n\n\t/* Sounding Sequence, bit0~1 is reserved */\n\tsequence = info->sounding_sequence << 2;\n\tif (info->sounding_sequence >= 0x3f)\n\t\tinfo->sounding_sequence = 0;\n\telse\n\t\tinfo->sounding_sequence++;\n\t_rtw_memcpy(pframe + 16, &sequence, 1);\n\n\tattrib->pktlen = 17;\n\n\t/*\n\t * Construct STA info. for multiple STAs\n\t * STA Info1, ..., STA Info n\n\t */\n\tfor (i = 0; i < sounding->candidate_mu_bfee_cnt; i++) {\n\t\tbfee = &info->bfee_entry[sounding->mu_sounding_list[i]];\n\t\tsta_info.aid = bfee->aid;\n\t\tsta_info.feedback_type = 1; /* 1'b1: MU */\n\t\tsta_info.nc_index = 0;\n\t\t_rtw_memcpy(pframe + attrib->pktlen, (u8 *)&sta_info, 2);\n\t\tattrib->pktlen += 2;\n\t}\n\n\tattrib->last_txcmdsz = attrib->pktlen;\n\n\tdump_mgntframe(adapter, pmgntframe);\n\n\treturn _TRUE;\n}\n\nstatic u8 _send_bf_report_poll(PADAPTER adapter, u8 *ra, u8 bFinalPoll)\n{\n\t/* General */\n\tstruct xmit_priv *pxmitpriv;\n\tstruct xmit_frame *pmgntframe;\n\t/* MISC */\n\tstruct pkt_attrib *attrib;\n\tstruct rtw_ieee80211_hdr *pwlanhdr;\n\tu8 *pframe;\n\n\n\tRTW_INFO(\"+%s: Send to \" MAC_FMT \"\\n\", __FUNCTION__, MAC_ARG(ra));\n\n\tpxmitpriv = &adapter->xmitpriv;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (!pmgntframe) {\n\t\tRTW_ERR(\"%s: alloc mgnt frame fail!\\n\", __FUNCTION__);\n\t\treturn _FALSE;\n\t}\n\n\t/* update attribute */\n\tattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(adapter, attrib);\n\t/*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */\n\tattrib->subtype = WIFI_BF_REPORT_POLL;\n\tattrib->bwmode = CHANNEL_WIDTH_20;\n\t/*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */\n\tattrib->rate = MGN_6M;\n\tif (bFinalPoll)\n\t\tattrib->bf_pkt_type = 3;\n\telse\n\t\tattrib->bf_pkt_type = 2;\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET);\n\tpframe = pmgntframe->buf_addr + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\t/* Frame control */\n\tpwlanhdr->frame_ctl = 0;\n\tset_frame_sub_type(pframe, attrib->subtype);\n\n\t/* Duration */\n\tset_duration(pframe, 100);\n\n\t/* RA */\n\t_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);\n\n\t/* TA */\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);\n\n\t/* Feedback Segment Retransmission Bitmap */\n\tpframe[16] = 0xFF;\n\n\tattrib->pktlen = 17;\n\tattrib->last_txcmdsz = attrib->pktlen;\n\n\tdump_mgntframe(adapter, pmgntframe);\n\n\treturn _TRUE;\n}\n\nstatic void _sounding_update_min_period(PADAPTER adapter, u16 period, u8 leave)\n{\n\tstruct beamforming_info *info;\n\tstruct beamformee_entry *bfee;\n\tu8 i = 0;\n\tu16 min_val = 0xFFFF;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\tif (_TRUE == leave) {\n\t\t/*\n\t\t * When a BFee left,\n\t\t * we need to find the latest min sounding period\n\t\t * from the remaining BFees\n\t\t */\n\t\tfor (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {\n\t\t\tbfee = &info->bfee_entry[i];\n\t\t\tif ((bfee->used == _TRUE)\n\t\t\t    && (bfee->sound_period < min_val))\n\t\t\t\tmin_val = bfee->sound_period;\n\t\t}\n\n\t\tif (min_val == 0xFFFF)\n\t\t\tinfo->sounding_info.min_sounding_period = 0;\n\t\telse\n\t\t\tinfo->sounding_info.min_sounding_period = min_val;\n\t} else {\n\t\tif ((info->sounding_info.min_sounding_period == 0)\n\t\t    || (period < info->sounding_info.min_sounding_period))\n\t\t\tinfo->sounding_info.min_sounding_period = period;\n\t}\n}\n\nstatic void _sounding_init(struct sounding_info *sounding)\n{\n\t_rtw_memset(sounding->su_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_SU);\n\t_rtw_memset(sounding->mu_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_MU);\n\tsounding->state = SOUNDING_STATE_NONE;\n\tsounding->su_bfee_curidx = 0xFF;\n\tsounding->candidate_mu_bfee_cnt = 0;\n\tsounding->min_sounding_period = 0;\n\tsounding->sound_remain_cnt_per_period = 0;\n}\n\nstatic void _sounding_reset_vars(PADAPTER adapter)\n{\n\tstruct beamforming_info\t*info;\n\tstruct sounding_info *sounding;\n\tu8 idx;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tsounding = &info->sounding_info;\n\n\t_rtw_memset(sounding->su_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_SU);\n\t_rtw_memset(sounding->mu_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_MU);\n\tsounding->su_bfee_curidx = 0xFF;\n\tsounding->candidate_mu_bfee_cnt = 0;\n\n\t/* Clear bSound flag for the new period */\n\tfor (idx = 0; idx < MAX_BEAMFORMEE_ENTRY_NUM; idx++) {\n\t\tif ((info->bfee_entry[idx].used == _TRUE)\n\t\t    && (info->bfee_entry[idx].sounding == _TRUE)) {\n\t\t\tinfo->bfee_entry[idx].sounding = _FALSE;\n\t\t\tinfo->bfee_entry[idx].bCandidateSoundingPeer = _FALSE;\n\t\t}\n\t}\n}\n\n/*\n * Return\n *\t0\tPrepare sounding list OK\n *\t-1\tFail to prepare sounding list, because no beamformee need to souding\n *\t-2\tFail to prepare sounding list, because beamformee state not ready\n *\n */\nstatic int _sounding_get_list(PADAPTER adapter)\n{\n\tstruct beamforming_info\t*info;\n\tstruct sounding_info *sounding;\n\tstruct beamformee_entry *bfee;\n\tu8 i, mu_idx = 0, su_idx = 0, not_ready = 0;\n\tint ret = 0;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tsounding = &info->sounding_info;\n\n\t/* Add MU BFee list first because MU priority is higher than SU */\n\tfor (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {\n\t\tbfee = &info->bfee_entry[i];\n\t\tif (bfee->used == _FALSE)\n\t\t\tcontinue;\n\n\t\tif (bfee->state != BEAMFORM_ENTRY_HW_STATE_ADDED) {\n\t\t\tRTW_ERR(\"%s: Invalid BFee idx(%d) Hw state=%d\\n\", __FUNCTION__, i, bfee->state);\n\t\t\tnot_ready++;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/*\n\t\t * Decrease BFee's SoundCnt per period\n\t\t * If the remain count is 0,\n\t\t * then it can be sounded at this time\n\t\t */\n\t\tif (bfee->SoundCnt) {\n\t\t\tbfee->SoundCnt--;\n\t\t\tif (bfee->SoundCnt)\n\t\t\t\tcontinue;\n\t\t}\n\n\t\t/*\n\t\t * <tynli_Note>\n\t\t *\tIf the STA supports MU BFee capability then we add it to MUSoundingList directly\n\t\t *\tbecause we can only sound one STA by unicast NDPA with MU cap enabled to get correct channel info.\n\t\t *\tSuggested by BB team Luke Lee. 2015.11.25.\n\t\t */\n\t\tif (bfee->cap & BEAMFORMEE_CAP_VHT_MU) {\n\t\t\t/* MU BFee */\n\t\t\tif (mu_idx >= MAX_NUM_BEAMFORMEE_MU) {\n\t\t\t\tRTW_ERR(\"%s: Too much MU bfee entry(Limit:%d)\\n\", __FUNCTION__, MAX_NUM_BEAMFORMEE_MU);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (bfee->bApplySounding == _TRUE) {\n\t\t\t\tbfee->bCandidateSoundingPeer = _TRUE;\n\t\t\t\tbfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, sounding->min_sounding_period);\n\t\t\t\tsounding->mu_sounding_list[mu_idx] = i;\n\t\t\t\tmu_idx++;\n\t\t\t}\n\t\t} else if (bfee->cap & (BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) {\n\t\t\t/* SU BFee (HT/VHT) */\n\t\t\tif (su_idx >= MAX_NUM_BEAMFORMEE_SU) {\n\t\t\t\tRTW_ERR(\"%s: Too much SU bfee entry(Limit:%d)\\n\", __FUNCTION__, MAX_NUM_BEAMFORMEE_SU);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (bfee->bDeleteSounding == _TRUE) {\n\t\t\t\tsounding->su_sounding_list[su_idx] = i;\n\t\t\t\tsu_idx++;\n\t\t\t} else if ((bfee->bApplySounding == _TRUE)\n\t\t\t    && (bfee->bSuspendSUCap == _FALSE)) {\n\t\t\t\tbfee->bCandidateSoundingPeer = _TRUE;\n\t\t\t\tbfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, sounding->min_sounding_period);\n\t\t\t\tsounding->su_sounding_list[su_idx] = i;\n\t\t\t\tsu_idx++;\n\t\t\t}\n\t\t}\n\t}\n\n\tsounding->candidate_mu_bfee_cnt = mu_idx;\n\n\tif (su_idx + mu_idx == 0) {\n\t\tret = -1;\n\t\tif (not_ready)\n\t\t\tret = -2;\n\t}\n\n\tRTW_INFO(\"-%s: There are %d SU and %d MU BFees in this sounding period\\n\", __FUNCTION__, su_idx, mu_idx);\n\n\treturn ret;\n}\n\nstatic void _sounding_handler(PADAPTER adapter)\n{\n\tstruct beamforming_info\t*info;\n\tstruct sounding_info *sounding;\n\tstruct beamformee_entry *bfee;\n\tu8 su_idx, i;\n\tu32 timeout_period = 0;\n\tu8 set_timer = _FALSE;\n\tint ret = 0;\n\tstatic u16 wait_cnt = 0;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tsounding = &info->sounding_info;\n\n\tRTW_DBG(\"+%s: state=%d\\n\", __FUNCTION__, sounding->state);\n\tif ((sounding->state != SOUNDING_STATE_INIT)\n\t    && (sounding->state != SOUNDING_STATE_SU_SOUNDDOWN)\n\t    && (sounding->state != SOUNDING_STATE_MU_SOUNDDOWN)\n\t    && (sounding->state != SOUNDING_STATE_SOUNDING_TIMEOUT)) {\n\t\tRTW_WARN(\"%s: Invalid State(%d) and return!\\n\", __FUNCTION__, sounding->state);\n\t\treturn;\n\t}\n\n\tif (sounding->state == SOUNDING_STATE_INIT) {\n\t\tRTW_INFO(\"%s: Sounding start\\n\", __FUNCTION__);\n\n\t\t/* Init Var */\n\t\t_sounding_reset_vars(adapter);\n\n\t\t/* Get the sounding list of this sounding period */\n\t\tret = _sounding_get_list(adapter);\n\t\tif (ret == -1) {\n\t\t\twait_cnt = 0;\n\t\t\tsounding->state = SOUNDING_STATE_NONE;\n\t\t\tRTW_ERR(\"%s: No BFees found, set to SOUNDING_STATE_NONE\\n\", __FUNCTION__);\n\t\t\tinfo->sounding_running--;\n\t\t\treturn;\n\t\t}\n\t\tif (ret == -2) {\n\t\t\tRTW_WARN(\"%s: Temporarily cann't find BFee to sounding\\n\", __FUNCTION__);\n\t\t\tif (wait_cnt < 5) {\n\t\t\t\twait_cnt++;\n\t\t\t} else {\n\t\t\t\twait_cnt = 0;\n\t\t\t\tsounding->state = SOUNDING_STATE_NONE;\n\t\t\t\tRTW_ERR(\"%s: Wait changing state timeout!! Set to SOUNDING_STATE_NONE\\n\", __FUNCTION__);\n\t\t\t}\n\t\t\tinfo->sounding_running--;\n\t\t\treturn;\n\t\t}\n\t\tif (ret != 0) {\n\t\t\twait_cnt = 0;\n\t\t\tRTW_ERR(\"%s: Unkown state(%d)!\\n\", __FUNCTION__, ret);\n\t\t\tinfo->sounding_running--;\n\t\t\treturn;\n\n\t\t}\n\n\t\twait_cnt = 0;\n\n\t\tif (check_fwstate(&adapter->mlmepriv, WIFI_SITE_MONITOR) == _TRUE) {\n\t\t\tRTW_INFO(\"%s: Sounding abort! scanning APs...\\n\", __FUNCTION__);\n\t\t\tinfo->sounding_running--;\n\t\t\treturn;\n\t\t}\n\n\t\trtw_ps_deny(adapter, PS_DENY_BEAMFORMING);\n\t\tLeaveAllPowerSaveModeDirect(adapter);\n\t}\n\n\t/* Get non-sound SU BFee index */\n\tfor (i = 0; i < MAX_NUM_BEAMFORMEE_SU; i++) {\n\t\tsu_idx = sounding->su_sounding_list[i];\n\t\tif (su_idx >= MAX_BEAMFORMEE_ENTRY_NUM)\n\t\t\tcontinue;\n\t\tbfee = &info->bfee_entry[su_idx];\n\t\tif (_FALSE == bfee->sounding)\n\t\t\tbreak;\n\t}\n\tif (i < MAX_NUM_BEAMFORMEE_SU) {\n\t\tsounding->su_bfee_curidx = su_idx;\n\t\t/* Set to sounding start state */\n\t\tsounding->state = SOUNDING_STATE_SU_START;\n\t\tRTW_DBG(\"%s: Set to SOUNDING_STATE_SU_START\\n\", __FUNCTION__);\n\n\t\tbfee->sounding = _TRUE;\n\t\t/* Reset sounding timeout flag for the new sounding */\n\t\tbfee->bSoundingTimeout = _FALSE;\n\n\t\tif (_TRUE == bfee->bDeleteSounding) {\n\t\t\tu8 res = _FALSE;\n\t\t\trtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 0);\n\t\t\treturn;\n\t\t}\n\n\t\t/* Start SU sounding */\n\t\tif (bfee->cap & BEAMFORMEE_CAP_VHT_SU)\n\t\t\t_send_vht_ndpa_packet(adapter, bfee->mac_addr, bfee->aid, bfee->sound_bw);\n\t\telse if (bfee->cap & BEAMFORMEE_CAP_HT_EXPLICIT)\n\t\t\t_send_ht_ndpa_packet(adapter, bfee->mac_addr, bfee->sound_bw);\n\n\t\t/* Set sounding timeout timer */\n\t\t_set_timer(&info->sounding_timeout_timer, SU_SOUNDING_TIMEOUT);\n\t\treturn;\n\t}\n\n\tif (sounding->candidate_mu_bfee_cnt > 0) {\n\t\t/*\n\t\t * If there is no SU BFee then find MU BFee and perform MU sounding\n\t\t *\n\t\t * <tynli_note> Need to check the MU starting condition. 2015.12.15.\n\t\t */\n\t\tsounding->state = SOUNDING_STATE_MU_START;\n\t\tRTW_DBG(\"%s: Set to SOUNDING_STATE_MU_START\\n\", __FUNCTION__);\n\n\t\t/* Update MU BFee info */\n\t\tfor (i = 0; i < sounding->candidate_mu_bfee_cnt; i++) {\n\t\t\tbfee = &info->bfee_entry[sounding->mu_sounding_list[i]];\n\t\t\tbfee->sounding = _TRUE;\n\t\t}\n\n\t\t/* Send MU NDPA */\n\t\tbfee = &info->bfee_entry[sounding->mu_sounding_list[0]];\n\t\t_send_vht_mu_ndpa_packet(adapter, bfee->sound_bw);\n\n\t\t/* Send BF report poll if more than 1 MU STA */\n\t\tfor (i = 1; i < sounding->candidate_mu_bfee_cnt; i++) {\n\t\t\tbfee = &info->bfee_entry[sounding->mu_sounding_list[i]];\n\n\t\t\tif (i == (sounding->candidate_mu_bfee_cnt - 1))/* The last STA*/\n\t\t\t\t_send_bf_report_poll(adapter, bfee->mac_addr, _TRUE);\n\t\t\telse\n\t\t\t\t_send_bf_report_poll(adapter, bfee->mac_addr, _FALSE);\n\t\t}\n\n\t\tsounding->candidate_mu_bfee_cnt = 0;\n\n\t\t/* Set sounding timeout timer */\n\t\t_set_timer(&info->sounding_timeout_timer, MU_SOUNDING_TIMEOUT);\n\t\treturn;\n\t}\n\n\tinfo->sounding_running--;\n\tsounding->state = SOUNDING_STATE_INIT;\n\tRTW_INFO(\"%s: Sounding finished!\\n\", __FUNCTION__);\n\trtw_ps_deny_cancel(adapter, PS_DENY_BEAMFORMING);\n}\n\nstatic void _sounding_force_stop(PADAPTER adapter)\n{\n\tstruct beamforming_info\t*info;\n\tstruct sounding_info *sounding;\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tsounding = &info->sounding_info;\n\n\tif ((sounding->state == SOUNDING_STATE_SU_START)\n\t    || (sounding->state == SOUNDING_STATE_MU_START)) {\n\t\tu8 res = _FALSE;\n\t\t_cancel_timer_ex(&info->sounding_timeout_timer);\n\t\trtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 1);\n\t\treturn;\n\t}\n\n\tinfo->sounding_running--;\n\tsounding->state = SOUNDING_STATE_INIT;\n\tRTW_INFO(\"%s: Sounding finished!\\n\", __FUNCTION__);\n\trtw_ps_deny_cancel(adapter, PS_DENY_BEAMFORMING);\n}\n\nstatic void _sounding_timer_handler(void *FunctionContext)\n{\n\tPADAPTER adapter;\n\tstruct beamforming_info\t*info;\n\tstruct sounding_info *sounding;\n\tstatic u8 delay = 0;\n\n\n\tRTW_DBG(\"+%s\\n\", __FUNCTION__);\n\n\tadapter = (PADAPTER)FunctionContext;\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tsounding = &info->sounding_info;\n\n\tif (SOUNDING_STATE_NONE == sounding->state) {\n\t\tRTW_INFO(\"%s: Stop!\\n\", __FUNCTION__);\n\t\tif (info->sounding_running)\n\t\t\tRTW_WARN(\"%s: souding_running=%d when thread stop!\\n\",\n\t\t\t\t __FUNCTION__, info->sounding_running);\n\t\treturn;\n\t}\n\n\t_set_timer(&info->sounding_timer, sounding->min_sounding_period);\n\n\tif (!info->sounding_running) {\n\t\tif (SOUNDING_STATE_INIT != sounding->state) {\n\t\t\tRTW_WARN(\"%s: state(%d) != SOUNDING_STATE_INIT!!\\n\", __FUNCTION__, sounding->state);\n\t\t\tsounding->state = SOUNDING_STATE_INIT;\n\t\t}\n\t\tdelay = 0;\n\t\tinfo->sounding_running++;\n\t\trtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 1);\n\t} else {\n\t\tif (delay != 0xFF)\n\t\t\tdelay++;\n\t\tRTW_WARN(\"%s: souding is still processing...(state:%d, running:%d, delay:%d)\\n\",\n\t\t\t __FUNCTION__, sounding->state, info->sounding_running, delay);\n\t\tif (delay > 3) {\n\t\t\tRTW_WARN(\"%s: Stop sounding!!\\n\", __FUNCTION__);\n\t\t\t_sounding_force_stop(adapter);\n\t\t}\n\t}\n}\n\nstatic void _sounding_timeout_timer_handler(void *FunctionContext)\n{\n\tPADAPTER adapter;\n\tstruct beamforming_info\t*info;\n\tstruct sounding_info *sounding;\n\tstruct beamformee_entry *bfee;\n\n\n\tRTW_WARN(\"+%s\\n\", __FUNCTION__);\n\n\tadapter = (PADAPTER)FunctionContext;\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tsounding = &info->sounding_info;\n\n\tif (SOUNDING_STATE_SU_START == sounding->state) {\n\t\tsounding->state = SOUNDING_STATE_SOUNDING_TIMEOUT;\n\t\tRTW_ERR(\"%s: Set to SU SOUNDING_STATE_SOUNDING_TIMEOUT\\n\", __FUNCTION__);\n\t\t/* SU BFee */\n\t\tbfee = &info->bfee_entry[sounding->su_bfee_curidx];\n\t\tbfee->bSoundingTimeout = _TRUE;\n\t\tRTW_WARN(\"%s: The BFee entry[%d] is Sounding Timeout!\\n\", __FUNCTION__, sounding->su_bfee_curidx);\n\t} else if (SOUNDING_STATE_MU_START == sounding->state) {\n\t\tsounding->state = SOUNDING_STATE_SOUNDING_TIMEOUT;\n\t\tRTW_ERR(\"%s: Set to MU SOUNDING_STATE_SOUNDING_TIMEOUT\\n\", __FUNCTION__);\n\t} else {\n\t\tRTW_WARN(\"%s: unexpected sounding state:0x%02x\\n\", __FUNCTION__, sounding->state);\n\t\treturn;\n\t}\n\n\trtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 1);\n}\n\nstatic struct beamformer_entry *_bfer_get_free_entry(PADAPTER adapter)\n{\n\tu8 i = 0;\n\tstruct beamforming_info *info;\n\tstruct beamformer_entry *bfer;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\tfor (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) {\n\t\tbfer = &info->bfer_entry[i];\n\t\tif (bfer->used == _FALSE)\n\t\t\treturn bfer;\n\t}\n\n\treturn NULL;\n}\n\nstatic struct beamformer_entry *_bfer_get_entry_by_addr(PADAPTER adapter, u8 *ra)\n{\n\tu8 i = 0;\n\tstruct beamforming_info *info;\n\tstruct beamformer_entry *bfer;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\tfor (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) {\n\t\tbfer = &info->bfer_entry[i];\n\t\tif (bfer->used == _FALSE)\n\t\t\tcontinue;\n\t\tif (_rtw_memcmp(ra, bfer->mac_addr, ETH_ALEN) == _TRUE)\n\t\t\treturn bfer;\n\t}\n\n\treturn NULL;\n}\n\nstatic struct beamformer_entry *_bfer_add_entry(PADAPTER adapter,\n\tstruct sta_info *sta, u8 bf_cap, u8 sounding_dim, u8 comp_steering)\n{\n\tstruct mlme_priv *mlme;\n\tstruct beamforming_info *info;\n\tstruct beamformer_entry *bfer;\n\tu8 *bssid;\n\tu16 val16;\n\tu8 i;\n\n\n\tmlme = &adapter->mlmepriv;\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\tbfer = _bfer_get_entry_by_addr(adapter, sta->cmn.mac_addr);\n\tif (!bfer) {\n\t\tbfer = _bfer_get_free_entry(adapter);\n\t\tif (!bfer)\n\t\t\treturn NULL;\n\t}\n\n\tbfer->used = _TRUE;\n\t_get_txvector_parameter(adapter, sta, &bfer->g_id, &bfer->p_aid);\n\t_rtw_memcpy(bfer->mac_addr, sta->cmn.mac_addr, ETH_ALEN);\n\tbfer->cap = bf_cap;\n\tbfer->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT;\n\tbfer->NumofSoundingDim = sounding_dim;\n\n\tif (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_MU)) {\n\t\tinfo->beamformer_mu_cnt += 1;\n\t\tbfer->aid = sta->cmn.aid;\n\t} else if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) {\n\t\tinfo->beamformer_su_cnt += 1;\n\n\t\t/* Record HW idx info */\n\t\tfor (i = 0; i < MAX_NUM_BEAMFORMER_SU; i++) {\n\t\t\tif ((info->beamformer_su_reg_maping & BIT(i)) == 0) {\n\t\t\t\tinfo->beamformer_su_reg_maping |= BIT(i);\n\t\t\t\tbfer->su_reg_index = i;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tRTW_INFO(\"%s: Add BFer entry beamformer_su_reg_maping=%#x, su_reg_index=%d\\n\",\n\t\t\t __FUNCTION__, info->beamformer_su_reg_maping, bfer->su_reg_index);\n\t}\n\n\treturn bfer;\n}\n\nstatic void _bfer_remove_entry(PADAPTER adapter, struct beamformer_entry *entry)\n{\n\tstruct beamforming_info *info;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\tentry->state = BEAMFORM_ENTRY_HW_STATE_DELETE_INIT;\n\n\tif (TEST_FLAG(entry->cap, BEAMFORMER_CAP_VHT_MU)) {\n\t\tinfo->beamformer_mu_cnt -= 1;\n\t\t_rtw_memset(entry->gid_valid, 0, 8);\n\t\t_rtw_memset(entry->user_position, 0, 16);\n\t} else if (TEST_FLAG(entry->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) {\n\t\tinfo->beamformer_su_cnt -= 1;\n\t}\n\n\tif (info->beamformer_mu_cnt == 0)\n\t\tinfo->beamforming_cap &= ~BEAMFORMEE_CAP_VHT_MU;\n\tif (info->beamformer_su_cnt == 0)\n\t\tinfo->beamforming_cap &= ~(BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT);\n}\n\nstatic u8 _bfer_set_entry_gid(PADAPTER adapter, u8 *addr, u8 *gid, u8 *position)\n{\n\tstruct beamformer_entry bfer;\n\n\tmemset(&bfer, 0, sizeof(bfer));\n\tmemcpy(bfer.mac_addr, addr, ETH_ALEN);\n\n\t/* Parsing Membership Status Array */\n\tmemcpy(bfer.gid_valid, gid, 8);\n\n\t/* Parsing User Position Array */\n\tmemcpy(bfer.user_position, position, 16);\n\n\t/* Config HW GID table */\n\trtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_GID_TABLE, (u8 *) &bfer,\n\t\t\tsizeof(bfer), 1);\n\n\treturn _SUCCESS;\n}\n\nstatic struct beamformee_entry *_bfee_get_free_entry(PADAPTER adapter)\n{\n\tu8 i = 0;\n\tstruct beamforming_info *info;\n\tstruct beamformee_entry *bfee;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\tfor (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {\n\t\tbfee = &info->bfee_entry[i];\n\t\tif (bfee->used == _FALSE)\n\t\t\treturn bfee;\n\t}\n\n\treturn NULL;\n}\n\nstatic struct beamformee_entry *_bfee_get_entry_by_addr(PADAPTER adapter, u8 *ra)\n{\n\tu8 i = 0;\n\tstruct beamforming_info *info;\n\tstruct beamformee_entry *bfee;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\tfor (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {\n\t\tbfee = &info->bfee_entry[i];\n\t\tif (bfee->used == _FALSE)\n\t\t\tcontinue;\n\t\tif (_rtw_memcmp(ra, bfee->mac_addr, ETH_ALEN) == _TRUE)\n\t\t\treturn bfee;\n\t}\n\n\treturn NULL;\n}\n\nstatic u8 _bfee_get_first_su_entry_idx(PADAPTER adapter, struct beamformee_entry *ignore)\n{\n\tstruct beamforming_info *info;\n\tstruct beamformee_entry *bfee;\n\tu8 i;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\tfor (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {\n\t\tbfee = &info->bfee_entry[i];\n\t\tif (ignore && (bfee == ignore))\n\t\t\tcontinue;\n\t\tif (bfee->used == _FALSE)\n\t\t\tcontinue;\n\t\tif ((!TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU))\n\t\t    && TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT))\n\t\t\treturn i;\n\t}\n\n\treturn 0xFF;\n}\n\n/*\n * Description:\n *\tGet the first entry index of MU Beamformee.\n *\n * Return Value:\n *\tIndex of the first MU sta, or 0xFF for invalid index.\n *\n * 2015.05.25. Created by tynli.\n *\n */\nstatic u8 _bfee_get_first_mu_entry_idx(PADAPTER adapter, struct beamformee_entry *ignore)\n{\n\tstruct beamforming_info *info;\n\tstruct beamformee_entry *bfee;\n\tu8 i;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\tfor (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {\n\t\tbfee = &info->bfee_entry[i];\n\t\tif (ignore && (bfee == ignore))\n\t\t\tcontinue;\n\t\tif (bfee->used == _FALSE)\n\t\t\tcontinue;\n\t\tif (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU))\n\t\t\treturn i;\n\t}\n\n\treturn 0xFF;\n}\n\nstatic struct beamformee_entry *_bfee_add_entry(PADAPTER adapter,\n\tstruct sta_info *sta, u8 bf_cap, u8 sounding_dim, u8 comp_steering)\n{\n\tstruct mlme_priv *mlme;\n\tstruct beamforming_info *info;\n\tstruct beamformee_entry *bfee;\n\tu8 *bssid;\n\tu16 val16;\n\tu8 i;\n\n\n\tmlme = &adapter->mlmepriv;\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\tbfee = _bfee_get_entry_by_addr(adapter, sta->cmn.mac_addr);\n\tif (!bfee) {\n\t\tbfee = _bfee_get_free_entry(adapter);\n\t\tif (!bfee)\n\t\t\treturn NULL;\n\t}\n\n\tbfee->used = _TRUE;\n\tbfee->aid = sta->cmn.aid;\n\tbfee->mac_id = sta->cmn.mac_id;\n\tbfee->sound_bw = sta->cmn.bw_mode;\n\n\t_get_txvector_parameter(adapter, sta, &bfee->g_id, &bfee->p_aid);\n\tsta->cmn.bf_info.g_id = bfee->g_id;\n\tsta->cmn.bf_info.p_aid = bfee->p_aid;\n\n\t_rtw_memcpy(bfee->mac_addr, sta->cmn.mac_addr, ETH_ALEN);\n\tbfee->txbf = _FALSE;\n\tbfee->sounding = _FALSE;\n\tbfee->sound_period = 40;\n\t_sounding_update_min_period(adapter, bfee->sound_period, _FALSE);\n\tbfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, info->sounding_info.min_sounding_period);\n\tbfee->cap = bf_cap;\n\tbfee->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT;\n\n\tbfee->bCandidateSoundingPeer = _FALSE;\n\tbfee->bSoundingTimeout = _FALSE;\n\tbfee->bDeleteSounding = _FALSE;\n\tbfee->bApplySounding = _TRUE;\n\n\tbfee->tx_timestamp = 0;\n\tbfee->tx_bytes = 0;\n\n\tbfee->LogStatusFailCnt = 0;\n\tbfee->NumofSoundingDim = sounding_dim;\n\tbfee->comp_steering_num_of_bfer = comp_steering;\n\tbfee->bSuspendSUCap = _FALSE;\n\n\tif (TEST_FLAG(bf_cap, BEAMFORMEE_CAP_VHT_MU)) {\n\t\tinfo->beamformee_mu_cnt += 1;\n\t\tinfo->first_mu_bfee_index = _bfee_get_first_mu_entry_idx(adapter, NULL);\n\n\t\tif (_TRUE == info->bEnableSUTxBFWorkAround) {\n\t\t\t/* When the first MU BFee added, discard SU BFee bfee's capability */\n\t\t\tif ((info->beamformee_mu_cnt == 1) && (info->beamformee_su_cnt > 0)) {\n\t\t\t\tif (info->TargetSUBFee) {\n\t\t\t\t\tinfo->TargetSUBFee->bSuspendSUCap = _TRUE;\n\t\t\t\t\tinfo->TargetSUBFee->bDeleteSounding = _TRUE;\n\t\t\t\t} else {\n\t\t\t\t\tRTW_ERR(\"%s: UNEXPECTED!! info->TargetSUBFee is NULL!\", __FUNCTION__);\n\t\t\t\t}\n\t\t\t\tinfo->TargetSUBFee = NULL;\n\t\t\t\t_rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));\n\t\t\t\trtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 0);\n\t\t\t}\n\t\t}\n\n\t\t/* Record HW idx info */\n\t\tfor (i = 0; i < MAX_NUM_BEAMFORMEE_MU; i++) {\n\t\t\tif ((info->beamformee_mu_reg_maping & BIT(i)) == 0) {\n\t\t\t\tinfo->beamformee_mu_reg_maping |= BIT(i);\n\t\t\t\tbfee->mu_reg_index = i;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tRTW_INFO(\"%s: Add BFee entry beamformee_mu_reg_maping=%#x, mu_reg_index=%d\\n\",\n\t\t\t __FUNCTION__, info->beamformee_mu_reg_maping, bfee->mu_reg_index);\n\n\t} else if (TEST_FLAG(bf_cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) {\n\t\tinfo->beamformee_su_cnt += 1;\n\n\t\tif (_TRUE == info->bEnableSUTxBFWorkAround) {\n\t\t\t/* Record the first SU BFee index. We only allow the first SU BFee to be sound */\n\t\t\tif ((info->beamformee_su_cnt == 1) && (info->beamformee_mu_cnt == 0)) {\n\t\t\t\tinfo->TargetSUBFee = bfee;\n\t\t\t\t_rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));\n\t\t\t\tbfee->bSuspendSUCap = _FALSE;\n\t\t\t} else {\n\t\t\t\tbfee->bSuspendSUCap = _TRUE;\n\t\t\t}\n\t\t}\n\n\t\t/* Record HW idx info */\n\t\tfor (i = 0; i < MAX_NUM_BEAMFORMEE_SU; i++) {\n\t\t\tif ((info->beamformee_su_reg_maping & BIT(i)) == 0) {\n\t\t\t\tinfo->beamformee_su_reg_maping |= BIT(i);\n\t\t\t\tbfee->su_reg_index = i;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tRTW_INFO(\"%s: Add BFee entry beamformee_su_reg_maping=%#x, su_reg_index=%d\\n\",\n\t\t\t __FUNCTION__, info->beamformee_su_reg_maping, bfee->su_reg_index);\n\t}\n\n\treturn bfee;\n}\n\nstatic void _bfee_remove_entry(PADAPTER adapter, struct beamformee_entry *entry)\n{\n\tstruct beamforming_info *info;\n\tu8 idx;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\tentry->state = BEAMFORM_ENTRY_HW_STATE_DELETE_INIT;\n\n\tif (TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_MU)) {\n\t\tinfo->beamformee_mu_cnt -= 1;\n\t\tinfo->first_mu_bfee_index = _bfee_get_first_mu_entry_idx(adapter, entry);\n\n\t\tif (_TRUE == info->bEnableSUTxBFWorkAround) {\n\t\t\tif ((info->beamformee_mu_cnt == 0) && (info->beamformee_su_cnt > 0)) {\n\t\t\t\tidx = _bfee_get_first_su_entry_idx(adapter, NULL);\n\t\t\t\tinfo->TargetSUBFee = &info->bfee_entry[idx];\n\t\t\t\t_rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));\n\t\t\t\tinfo->TargetSUBFee->bSuspendSUCap = _FALSE;\n\t\t\t}\n\t\t}\n\t} else if (TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) {\n\t\tinfo->beamformee_su_cnt -= 1;\n\n\t\t/* When the target SU BFee leaves, disable workaround */\n\t\tif ((_TRUE == info->bEnableSUTxBFWorkAround)\n\t\t    && (entry == info->TargetSUBFee)) {\n\t\t\tentry->bSuspendSUCap = _TRUE;\n\t\t\tinfo->TargetSUBFee = NULL;\n\t\t\t_rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));\n\t\t\trtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 0);\n\t\t}\n\t}\n\n\tif (info->beamformee_mu_cnt == 0)\n\t\tinfo->beamforming_cap &= ~BEAMFORMER_CAP_VHT_MU;\n\tif (info->beamformee_su_cnt == 0)\n\t\tinfo->beamforming_cap &= ~(BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT);\n\n\t_sounding_update_min_period(adapter, 0, _TRUE);\n}\n\nstatic enum beamforming_cap _bfee_get_entry_cap_by_macid(PADAPTER adapter, u8 macid)\n{\n\tstruct beamforming_info *info;\n\tstruct beamformee_entry *bfee;\n\tu8 i;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\tfor (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) {\n\t\tbfee = &info->bfee_entry[i];\n\t\tif (bfee->used == _FALSE)\n\t\t\tcontinue;\n\t\tif (bfee->mac_id == macid)\n\t\t\treturn bfee->cap;\n\t}\n\n\treturn BEAMFORMING_CAP_NONE;\n}\n\nstatic void _beamforming_enter(PADAPTER adapter, void *p)\n{\n\tstruct mlme_priv *mlme;\n\tstruct ht_priv *htpriv;\n#ifdef CONFIG_80211AC_VHT\n\tstruct vht_priv *vhtpriv;\n#endif\n\tstruct mlme_ext_priv *mlme_ext;\n\tstruct sta_info *sta, *sta_copy;\n\tstruct beamforming_info *info;\n\tstruct beamformer_entry *bfer = NULL;\n\tstruct beamformee_entry *bfee = NULL;\n\tu8 wireless_mode;\n\tu8 sta_bf_cap;\n\tu8 sounding_dim = 0; /* number of sounding dimensions */\n\tu8 comp_steering_num = 0; /* compressed steering number */\n\n\n\tmlme = &adapter->mlmepriv;\n\thtpriv = &mlme->htpriv;\n#ifdef CONFIG_80211AC_VHT\n\tvhtpriv = &mlme->vhtpriv;\n#endif\n\tmlme_ext = &adapter->mlmeextpriv;\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\tsta_copy = (struct sta_info *)p;\n\tsta = rtw_get_stainfo(&adapter->stapriv, sta_copy->cmn.mac_addr);\n\tif (!sta) {\n\t\tRTW_ERR(\"%s: Cann't find STA info for \" MAC_FMT \"\\n\",\n\t\t\t__FUNCTION__, MAC_ARG(sta_copy->cmn.mac_addr));\n\t\treturn;\n\t}\n\tif (sta != sta_copy) {\n\t\tRTW_WARN(\"%s: Origin sta(fake)=%p realsta=%p for \" MAC_FMT \"\\n\",\n\t\t__FUNCTION__, sta_copy, sta, MAC_ARG(sta_copy->cmn.mac_addr));\n\t}\n\n\t/* The current setting does not support Beaforming */\n\twireless_mode = sta->wireless_mode;\n\tif ((is_supported_ht(wireless_mode) == _FALSE)\n\t    && (is_supported_vht(wireless_mode) == _FALSE)) {\n\t\tRTW_WARN(\"%s: Not support HT or VHT mode\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tif ((0 == htpriv->beamform_cap)\n#ifdef CONFIG_80211AC_VHT\n\t    && (0 == vhtpriv->beamform_cap)\n#endif\n\t   ) {\n\t\tRTW_INFO(\"The configuration disabled Beamforming! Skip...\\n\");\n\t\treturn;\n\t}\n\n\t_get_sta_beamform_cap(adapter, sta,\n\t\t\t      &sta_bf_cap, &sounding_dim, &comp_steering_num);\n\tRTW_INFO(\"STA Beamforming Capability=0x%02X\\n\", sta_bf_cap);\n\tif (sta_bf_cap == BEAMFORMING_CAP_NONE)\n\t\treturn;\n\tif ((sta_bf_cap & BEAMFORMEE_CAP_HT_EXPLICIT)\n\t    || (sta_bf_cap & BEAMFORMEE_CAP_VHT_SU)\n\t    || (sta_bf_cap & BEAMFORMEE_CAP_VHT_MU))\n\t\tsta_bf_cap |= BEAMFORMEE_CAP;\n\tif ((sta_bf_cap & BEAMFORMER_CAP_HT_EXPLICIT)\n\t    || (sta_bf_cap & BEAMFORMER_CAP_VHT_SU)\n\t    || (sta_bf_cap & BEAMFORMER_CAP_VHT_MU))\n\t\tsta_bf_cap |= BEAMFORMER_CAP;\n\n\tif (sta_bf_cap & BEAMFORMER_CAP) {\n\t\t/* The other side is beamformer */\n\t\tbfer = _bfer_add_entry(adapter, sta, sta_bf_cap, sounding_dim, comp_steering_num);\n\t\tif (!bfer)\n\t\t\tRTW_ERR(\"%s: Fail to allocate bfer entry!\\n\", __FUNCTION__);\n\t}\n\tif (sta_bf_cap & BEAMFORMEE_CAP) {\n\t\t/* The other side is beamformee */\n\t\tbfee = _bfee_add_entry(adapter, sta, sta_bf_cap, sounding_dim, comp_steering_num);\n\t\tif (!bfee)\n\t\t\tRTW_ERR(\"%s: Fail to allocate bfee entry!\\n\", __FUNCTION__);\n\t}\n\tif (!bfer && !bfee)\n\t\treturn;\n\n\trtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_ENTER, (u8*)sta);\n\n\t/* Perform sounding if there is BFee */\n\tif ((info->beamformee_su_cnt != 0)\n\t    || (info->beamformee_mu_cnt != 0)) {\n\t\tif (SOUNDING_STATE_NONE == info->sounding_info.state) {\n\t\t\tinfo->sounding_info.state = SOUNDING_STATE_INIT;\n\t\t\t/* Start sounding after 2 sec */\n\t\t\t_set_timer(&info->sounding_timer, 2000);\n\t\t}\n\t}\n}\n\nstatic void _beamforming_reset(PADAPTER adapter)\n{\n\tRTW_ERR(\"%s: Not ready!!\\n\", __FUNCTION__);\n}\n\nstatic void _beamforming_leave(PADAPTER adapter, u8 *ra)\n{\n\tstruct beamforming_info *info;\n\tstruct beamformer_entry *bfer = NULL;\n\tstruct beamformee_entry *bfee = NULL;\n\tu8 bHwStateAddInit = _FALSE;\n\n\n\tRTW_INFO(\"+%s\\n\", __FUNCTION__);\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tbfer = _bfer_get_entry_by_addr(adapter, ra);\n\tbfee = _bfee_get_entry_by_addr(adapter, ra);\n\n\tif (!bfer && !bfee) {\n\t\tRTW_WARN(\"%s: \" MAC_FMT \" is neither beamforming ee or er!!\\n\",\n\t\t\t__FUNCTION__, MAC_ARG(ra));\n\t\treturn;\n\t}\n\n\tif (bfer)\n\t\t_bfer_remove_entry(adapter, bfer);\n\n\tif (bfee)\n\t\t_bfee_remove_entry(adapter, bfee);\n\n\trtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_LEAVE, ra);\n\n\t/* Stop sounding if there is no any BFee */\n\tif ((info->beamformee_su_cnt == 0)\n\t    && (info->beamformee_mu_cnt == 0)) {\n\t\t_cancel_timer_ex(&info->sounding_timer);\n\t\t_sounding_init(&info->sounding_info);\n\t}\n\n\tRTW_INFO(\"-%s\\n\", __FUNCTION__);\n}\n\nstatic void _beamforming_sounding_down(PADAPTER adapter, u8 status)\n{\n\tstruct beamforming_info\t*info;\n\tstruct sounding_info *sounding;\n\tstruct beamformee_entry *bfee;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tsounding = &info->sounding_info;\n\n\tRTW_INFO(\"+%s: sounding=%d, status=0x%02x\\n\", __FUNCTION__, sounding->state, status);\n\n\tif (sounding->state == SOUNDING_STATE_MU_START) {\n\t\tRTW_INFO(\"%s: MU sounding done\\n\", __FUNCTION__);\n\t\tsounding->state = SOUNDING_STATE_MU_SOUNDDOWN;\n\t\tRTW_INFO(\"%s: Set to SOUNDING_STATE_MU_SOUNDDOWN\\n\", __FUNCTION__);\n\t\tinfo->SetHalSoundownOnDemandCnt++;\n\t\trtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status);\n\t} else if (sounding->state == SOUNDING_STATE_SU_START) {\n\t\tRTW_INFO(\"%s: SU entry[%d] sounding down\\n\", __FUNCTION__, sounding->su_bfee_curidx);\n\t\tbfee = &info->bfee_entry[sounding->su_bfee_curidx];\n\t\tsounding->state = SOUNDING_STATE_SU_SOUNDDOWN;\n\t\tRTW_INFO(\"%s: Set to SOUNDING_STATE_SU_SOUNDDOWN\\n\", __FUNCTION__);\n\n\t\t/*\n\t\t * <tynli_note>\n\t\t *\tbfee->bSoundingTimeout this flag still cannot avoid\n\t\t *\told sound down event happens in the new sounding period.\n\t\t *\t2015.12.10\n\t\t */\n\t\tif (_TRUE == bfee->bSoundingTimeout) {\n\t\t\tRTW_WARN(\"%s: The entry[%d] is bSoundingTimeout!\\n\", __FUNCTION__, sounding->su_bfee_curidx);\n\t\t\tbfee->bSoundingTimeout = _FALSE;\n\t\t\treturn;\n\t\t}\n\n\t\tif (_TRUE == status) {\n\t\t\t/* success */\n\t\t\tbfee->LogStatusFailCnt = 0;\n\t\t\tinfo->SetHalSoundownOnDemandCnt++;\n\t\t\trtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status);\n\t\t} else if (_TRUE == bfee->bDeleteSounding) {\n\t\t\tRTW_WARN(\"%s: Delete entry[%d] sounding info!\\n\", __FUNCTION__, sounding->su_bfee_curidx);\n\t\t\trtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status);\n\t\t\tbfee->bDeleteSounding = _FALSE;\n\t\t} else {\n\t\t\tbfee->LogStatusFailCnt++;\n\t\t\tRTW_WARN(\"%s: LogStatusFailCnt=%d\\n\", __FUNCTION__, bfee->LogStatusFailCnt);\n\t\t\tif (bfee->LogStatusFailCnt > 30) {\n\t\t\t\tRTW_ERR(\"%s: LogStatusFailCnt > 30, Stop SOUNDING!!\\n\", __FUNCTION__);\n\t\t\t\trtw_bf_cmd(adapter, BEAMFORMING_CTRL_LEAVE, bfee->mac_addr, ETH_ALEN, 1);\n\t\t\t}\n\t\t}\n\t} else {\n\t\tRTW_WARN(\"%s: unexpected sounding state:0x%02x\\n\", __FUNCTION__, sounding->state);\n\t\treturn;\n\t}\n\n\trtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 0);\n}\n\nstatic void _c2h_snd_txbf(PADAPTER adapter, u8 *buf, u8 buf_len)\n{\n\tstruct beamforming_info\t*info;\n\tu8 res;\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\t_cancel_timer_ex(&info->sounding_timeout_timer);\n\n\tres = C2H_SND_TXBF_GET_SND_RESULT(buf) ? _TRUE : _FALSE;\n\tRTW_INFO(\"+%s: %s\\n\", __FUNCTION__, res==_TRUE?\"Success\":\"Fail!\");\n\n\trtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 1);\n}\n\n/*\n * Description:\n *\tThis function is for phydm only\n */\nenum beamforming_cap rtw_bf_bfee_get_entry_cap_by_macid(void *mlme, u8 macid)\n{\n\tPADAPTER adapter;\n\tenum beamforming_cap cap = BEAMFORMING_CAP_NONE;\n\n\n\tadapter = mlme_to_adapter((struct mlme_priv *)mlme);\n\tcap = _bfee_get_entry_cap_by_macid(adapter, macid);\n\n\treturn cap;\n}\n\nstruct beamformer_entry *rtw_bf_bfer_get_entry_by_addr(PADAPTER adapter, u8 *ra)\n{\n\treturn _bfer_get_entry_by_addr(adapter, ra);\n}\n\nstruct beamformee_entry *rtw_bf_bfee_get_entry_by_addr(PADAPTER adapter, u8 *ra)\n{\n\treturn _bfee_get_entry_by_addr(adapter, ra);\n}\n\nvoid rtw_bf_get_ndpa_packet(PADAPTER adapter, union recv_frame *precv_frame)\n{\n\tRTW_DBG(\"+%s\\n\", __FUNCTION__);\n}\n\nu32 rtw_bf_get_report_packet(PADAPTER adapter, union recv_frame *precv_frame)\n{\n\tu32 ret = _SUCCESS;\n\tstruct beamforming_info *info;\n\tstruct beamformee_entry *bfee = NULL;\n\tu8 *pframe;\n\tu32 frame_len;\n\tu8 *ta;\n\tu8 *frame_body;\n\tu8 category, action;\n\tu8 *pMIMOCtrlField, *pCSIMatrix;\n\tu8 Nc = 0, Nr = 0, CH_W = 0, Ng = 0, CodeBook = 0;\n\tu16 CSIMatrixLen = 0;\n\n\n\tRTW_INFO(\"+%s\\n\", __FUNCTION__);\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tpframe = precv_frame->u.hdr.rx_data;\n\tframe_len = precv_frame->u.hdr.len;\n\n\t/* Memory comparison to see if CSI report is the same with previous one */\n\tta = get_addr2_ptr(pframe);\n\tbfee = _bfee_get_entry_by_addr(adapter, ta);\n\tif (!bfee)\n\t\treturn _FAIL;\n\n\tframe_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);\n\tcategory = frame_body[0];\n\taction = frame_body[1];\n\n\tif ((category == RTW_WLAN_CATEGORY_VHT)\n\t    && (action == RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING)) {\n\t\tpMIMOCtrlField = pframe + 26;\n\t\tNc = (*pMIMOCtrlField) & 0x7;\n\t\tNr = ((*pMIMOCtrlField) & 0x38) >> 3;\n\t\tCH_W =  (((*pMIMOCtrlField) & 0xC0) >> 6);\n\t\tNg = (*(pMIMOCtrlField+1)) & 0x3;\n\t\tCodeBook = ((*(pMIMOCtrlField+1)) & 0x4) >> 2;\n\t\t/*\n\t\t * 24+(1+1+3)+2\n\t\t * ==> MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)\n\t\t */\n\t\tpCSIMatrix = pMIMOCtrlField + 3 + Nc;\n\t\tCSIMatrixLen = frame_len - 26 - 3 - Nc;\n\t\tinfo->TargetCSIInfo.bVHT = _TRUE;\n\t} else if ((category == RTW_WLAN_CATEGORY_HT)\n\t\t   && (action == RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING)) {\n\t\tpMIMOCtrlField = pframe + 26;\n\t\tNc = (*pMIMOCtrlField) & 0x3;\n\t\tNr = ((*pMIMOCtrlField) & 0xC) >> 2;\n\t\tCH_W = ((*pMIMOCtrlField) & 0x10) >> 4;\n\t\tNg = ((*pMIMOCtrlField) & 0x60) >> 5;\n\t\tCodeBook = ((*(pMIMOCtrlField+1)) & 0x6) >> 1;\n\t\t/*\n\t\t * 24+(1+1+6)+2\n\t\t * ==> MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)\n\t\t */\n\t\tpCSIMatrix = pMIMOCtrlField + 6 + Nr;\n\t\tCSIMatrixLen = frame_len  - 26 - 6 - Nr;\n\t\tinfo->TargetCSIInfo.bVHT = _FALSE;\n\t}\n\n\t/* Update current CSI report info */\n\tif ((_TRUE == info->bEnableSUTxBFWorkAround)\n\t    && (info->TargetSUBFee == bfee)) {\n\t\tif ((info->TargetCSIInfo.Nc != Nc) || (info->TargetCSIInfo.Nr != Nr) ||\n\t\t\t(info->TargetCSIInfo.ChnlWidth != CH_W) || (info->TargetCSIInfo.Ng != Ng) ||\n\t\t\t(info->TargetCSIInfo.CodeBook != CodeBook)) {\n\t\t\tinfo->TargetCSIInfo.Nc = Nc;\n\t\t\tinfo->TargetCSIInfo.Nr = Nr;\n\t\t\tinfo->TargetCSIInfo.ChnlWidth = CH_W;\n\t\t\tinfo->TargetCSIInfo.Ng = Ng;\n\t\t\tinfo->TargetCSIInfo.CodeBook = CodeBook;\n\n\t\t\trtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 1);\n\t\t}\n\t}\n\n\tRTW_INFO(\"%s: pkt type=%d-%d, Nc=%d, Nr=%d, CH_W=%d, Ng=%d, CodeBook=%d\\n\",\n\t\t __FUNCTION__, category, action, Nc, Nr, CH_W, Ng, CodeBook);\n\n\treturn ret;\n}\n\nu8 rtw_bf_send_vht_gid_mgnt_packet(PADAPTER adapter, u8 *ra, u8 *gid, u8 *position)\n{\n\t/* General */\n\tstruct xmit_priv *xmitpriv;\n\tstruct mlme_priv *mlmepriv;\n\tstruct xmit_frame *pmgntframe;\n\t/* MISC */\n\tstruct pkt_attrib *attrib;\n\tstruct rtw_ieee80211_hdr *wlanhdr;\n\tu8 *pframe, *ptr;\n\n\n\txmitpriv = &adapter->xmitpriv;\n\tmlmepriv = &adapter->mlmepriv;\n\n\tpmgntframe = alloc_mgtxmitframe(xmitpriv);\n\tif (!pmgntframe)\n\t\treturn _FALSE;\n\n\t/* update attribute */\n\tattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(adapter, attrib);\n\tattrib->rate = MGN_6M;\n\tattrib->bwmode = CHANNEL_WIDTH_20;\n\tattrib->subtype = WIFI_ACTION;\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)pmgntframe->buf_addr + TXDESC_OFFSET;\n\twlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\twlanhdr->frame_ctl = 0;\n\tset_frame_sub_type(pframe, attrib->subtype);\n\tset_duration(pframe, 0);\n\tSetFragNum(pframe, 0);\n\tSetSeqNum(pframe, 0);\n\n\t_rtw_memcpy(wlanhdr->addr1, ra, ETH_ALEN);\n\t_rtw_memcpy(wlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);\n\t_rtw_memcpy(wlanhdr->addr3, get_bssid(mlmepriv), ETH_ALEN);\n\n\tpframe[24] = RTW_WLAN_CATEGORY_VHT;\n\tpframe[25] = RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT;\n\t/* Set Membership Status Array */\n\tptr = pframe + 26;\n\t_rtw_memcpy(ptr, gid, 8);\n\t/* Set User Position Array */\n\tptr = pframe + 34;\n\t_rtw_memcpy(ptr, position, 16);\n\n\tattrib->pktlen = 54;\n\tattrib->last_txcmdsz = attrib->pktlen;\n\n\tdump_mgntframe(adapter, pmgntframe);\n\n\treturn _TRUE;\n}\n\n/*\n * Description:\n *\tOn VHT GID management frame by an MU beamformee.\n */\nvoid rtw_bf_get_vht_gid_mgnt_packet(PADAPTER adapter, union recv_frame *precv_frame)\n{\n\tu8 *pframe;\n\tu8 *ta, *gid, *position;\n\n\n\tRTW_DBG(\"+%s\\n\", __FUNCTION__);\n\n\tpframe = precv_frame->u.hdr.rx_data;\n\n\t/* Get address by Addr2 */\n\tta = get_addr2_ptr(pframe);\n\t/* Remove signaling TA */\n\tta[0] &= 0xFE;\n\n\t/* Membership Status Array */\n\tgid = pframe + 26;\n\t/* User Position Array */\n\tposition= pframe + 34;\n\n\t_bfer_set_entry_gid(adapter, ta, gid, position);\n}\n\nvoid rtw_bf_init(PADAPTER adapter)\n{\n\tstruct beamforming_info\t*info;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tinfo->beamforming_cap = BEAMFORMING_CAP_NONE;\n\tinfo->beamforming_state = BEAMFORMING_STATE_IDLE;\n/*\n\tinfo->bfee_entry[MAX_BEAMFORMEE_ENTRY_NUM];\n\tinfo->bfer_entry[MAX_BEAMFORMER_ENTRY_NUM];\n*/\n\tinfo->sounding_sequence = 0;\n\tinfo->beamformee_su_cnt = 0;\n\tinfo->beamformer_su_cnt = 0;\n\tinfo->beamformee_su_reg_maping = 0;\n\tinfo->beamformer_su_reg_maping = 0;\n\tinfo->beamformee_mu_cnt = 0;\n\tinfo->beamformer_mu_cnt = 0;\n\tinfo->beamformee_mu_reg_maping = 0;\n\tinfo->first_mu_bfee_index = 0xFF;\n\tinfo->mu_bfer_curidx = 0xFF;\n\tinfo->cur_csi_rpt_rate = HALMAC_OFDM24;\n\n\t_sounding_init(&info->sounding_info);\n\trtw_init_timer(&info->sounding_timer, adapter, _sounding_timer_handler, adapter);\n\trtw_init_timer(&info->sounding_timeout_timer, adapter, _sounding_timeout_timer_handler, adapter);\n\n\tinfo->SetHalBFEnterOnDemandCnt = 0;\n\tinfo->SetHalBFLeaveOnDemandCnt = 0;\n\tinfo->SetHalSoundownOnDemandCnt = 0;\n\n\tinfo->bEnableSUTxBFWorkAround = _TRUE;\n\tinfo->TargetSUBFee = NULL;\n\n\tinfo->sounding_running = 0;\n}\n\nvoid rtw_bf_cmd_hdl(PADAPTER adapter, u8 type, u8 *pbuf)\n{\n\tswitch (type) {\n\tcase BEAMFORMING_CTRL_ENTER:\n\t\t_beamforming_enter(adapter, pbuf);\n\t\tbreak;\n\n\tcase BEAMFORMING_CTRL_LEAVE:\n\t\tif (pbuf == NULL)\n\t\t\t_beamforming_reset(adapter);\n\t\telse\n\t\t\t_beamforming_leave(adapter, pbuf);\n\t\tbreak;\n\n\tcase BEAMFORMING_CTRL_START_PERIOD:\n\t\t_sounding_handler(adapter);\n\t\tbreak;\n\n\tcase BEAMFORMING_CTRL_END_PERIOD:\n\t\t_beamforming_sounding_down(adapter, *pbuf);\n\t\tbreak;\n\n\tcase BEAMFORMING_CTRL_SET_GID_TABLE:\n\t\trtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_SET_GID_TABLE, pbuf);\n\t\tbreak;\n\n\tcase BEAMFORMING_CTRL_SET_CSI_REPORT:\n\t\trtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_CSI_REPORT, pbuf);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nu8 rtw_bf_cmd(PADAPTER adapter, s32 type, u8 *pbuf, s32 size, u8 enqueue)\n{\n\tstruct cmd_obj *ph2c;\n\tstruct drvextra_cmd_parm *pdrvextra_cmd_parm;\n\tstruct cmd_priv\t*pcmdpriv = &adapter->cmdpriv;\n\tu8 *wk_buf;\n\tu8 res = _SUCCESS;\n\n\n\tif (!enqueue) {\n\t\trtw_bf_cmd_hdl(adapter, type, pbuf);\n\t\tgoto exit;\n\t}\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tif (pbuf != NULL) {\n\t\twk_buf = rtw_zmalloc(size);\n\t\tif (wk_buf == NULL) {\n\t\t\trtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));\n\t\t\trtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t_rtw_memcpy(wk_buf, pbuf, size);\n\t} else {\n\t\twk_buf = NULL;\n\t\tsize = 0;\n\t}\n\n\tpdrvextra_cmd_parm->ec_id = BEAMFORMING_WK_CID;\n\tpdrvextra_cmd_parm->type = type;\n\tpdrvextra_cmd_parm->size = size;\n\tpdrvextra_cmd_parm->pbuf = wk_buf;\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\treturn res;\n}\n\nvoid rtw_bf_update_attrib(PADAPTER adapter, struct pkt_attrib *attrib, struct sta_info *sta)\n{\n\tif (sta) {\n\t\tattrib->txbf_g_id = sta->cmn.bf_info.g_id;\n\t\tattrib->txbf_p_aid = sta->cmn.bf_info.p_aid;\n\t}\n}\n\nvoid rtw_bf_c2h_handler(PADAPTER adapter, u8 id, u8 *buf, u8 buf_len)\n{\n\tswitch (id) {\n\tcase CMD_ID_C2H_SND_TXBF:\n\t\t_c2h_snd_txbf(adapter, buf, buf_len);\n\t\tbreak;\n\t}\n}\n\n#define toMbps(bytes, secs)\t(rtw_division64(bytes >> 17, secs))\nvoid rtw_bf_update_traffic(PADAPTER adapter)\n{\n\tstruct beamforming_info\t*info;\n\tstruct sounding_info *sounding;\n\tstruct beamformee_entry *bfee;\n\tstruct sta_info *sta;\n\tu8 bfee_cnt, sounding_idx, i;\n\tu16 tp[MAX_BEAMFORMEE_ENTRY_NUM] = {0};\n\tu8 tx_rate[MAX_BEAMFORMEE_ENTRY_NUM] = {0};\n\tu64 tx_bytes, last_bytes;\n\tu32 time;\n\tsystime last_timestamp;\n\tu8 set_timer = _FALSE;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tsounding = &info->sounding_info;\n\n\t/* Check any bfee exist? */\n\tbfee_cnt = info->beamformee_su_cnt + info->beamformee_mu_cnt;\n\tif (bfee_cnt == 0)\n\t\treturn;\n\n\tfor (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {\n\t\tbfee = &info->bfee_entry[i];\n\t\tif (_FALSE == bfee->used)\n\t\t\tcontinue;\n\n\t\tsta = rtw_get_stainfo(&adapter->stapriv, bfee->mac_addr);\n\t\tif (!sta) {\n\t\t\tRTW_ERR(\"%s: Cann't find sta_info for \" MAC_FMT \"!\\n\", __FUNCTION__, MAC_ARG(bfee->mac_addr));\n\t\t\tcontinue;\n\t\t}\n\n\t\tlast_timestamp = bfee->tx_timestamp;\n\t\tlast_bytes = bfee->tx_bytes;\n\t\tbfee->tx_timestamp = rtw_get_current_time();\n\t\tbfee->tx_bytes = sta->sta_stats.tx_bytes;\n\t\tif (last_timestamp) {\n\t\t\tif (bfee->tx_bytes >= last_bytes)\n\t\t\t\ttx_bytes = bfee->tx_bytes - last_bytes;\n\t\t\telse\n\t\t\t\ttx_bytes = bfee->tx_bytes + (~last_bytes);\n\t\t\ttime = rtw_get_time_interval_ms(last_timestamp, bfee->tx_timestamp);\n\t\t\ttime = (time > 1000) ? time/1000 : 1;\n\t\t\ttp[i] = toMbps(tx_bytes, time);\n\t\t\ttx_rate[i] = rtw_get_current_tx_rate(adapter, sta);\n\t\t\tRTW_INFO(\"%s: BFee idx(%d), MadId(%d), TxTP=%lld bytes (%d Mbps), txrate=%d\\n\",\n\t\t\t\t __FUNCTION__, i, bfee->mac_id, tx_bytes, tp[i], tx_rate[i]);\n\t\t}\n\t}\n\n\tsounding_idx = phydm_get_beamforming_sounding_info(GET_PDM_ODM(adapter), tp, MAX_BEAMFORMEE_ENTRY_NUM, tx_rate);\n\n\tfor (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {\n\t\tbfee = &info->bfee_entry[i];\n\t\tif (_FALSE == bfee->used) {\n\t\t\tif (sounding_idx & BIT(i))\n\t\t\t\tRTW_WARN(\"%s: bfee(%d) not in used but need sounding?!\\n\", __FUNCTION__, i);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (sounding_idx & BIT(i)) {\n\t\t\tif (_FALSE == bfee->bApplySounding) {\n\t\t\t\tbfee->bApplySounding = _TRUE;\n\t\t\t\tbfee->SoundCnt = 0;\n\t\t\t\tset_timer = _TRUE;\n\t\t\t}\n\t\t} else {\n\t\t\tif (_TRUE == bfee->bApplySounding) {\n\t\t\t\tbfee->bApplySounding = _FALSE;\n\t\t\t\tbfee->bDeleteSounding = _TRUE;\n\t\t\t\tbfee->SoundCnt = 0;\n\t\t\t\tset_timer = _TRUE;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (_TRUE == set_timer) {\n\t\tif (SOUNDING_STATE_NONE == info->sounding_info.state) {\n\t\t\tinfo->sounding_info.state = SOUNDING_STATE_INIT;\n\t\t\t_set_timer(&info->sounding_timer, 0);\n\t\t}\n\t}\n}\n\n#else /* !RTW_BEAMFORMING_VERSION_2 */\n\n/*PHYDM_BF - (BEAMFORMING_SUPPORT == 1)*/\nu32\trtw_beamforming_get_report_frame(PADAPTER\t Adapter, union recv_frame *precv_frame)\n{\n\tu32\tret = _SUCCESS;\n\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(Adapter);\n\tstruct dm_struct\t\t*pDM_Odm = &(pHalData->odmpriv);\n\n\tret = beamforming_get_report_frame(pDM_Odm, precv_frame);\n\treturn ret;\n}\n\nvoid\trtw_beamforming_get_ndpa_frame(PADAPTER\t Adapter, union recv_frame *precv_frame)\n{\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(Adapter);\n\tstruct dm_struct\t\t*pDM_Odm = &(pHalData->odmpriv);\n\n\tbeamforming_get_ndpa_frame(pDM_Odm, precv_frame);\n}\n\nvoid\tbeamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf)\n{\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(padapter);\n\tstruct dm_struct\t\t*pDM_Odm = &(pHalData->odmpriv);\n\n\t/*(BEAMFORMING_SUPPORT == 1)- for PHYDM beamfoming*/\n\tswitch (type) {\n\tcase BEAMFORMING_CTRL_ENTER: {\n\t\tstruct sta_info\t*psta = (void *)pbuf;\n\t\tu16\t\t\tstaIdx = psta->cmn.mac_id;\n\n\t\tbeamforming_enter(pDM_Odm, staIdx, adapter_mac_addr(psta->padapter));\n\t\tbreak;\n\t}\n\tcase BEAMFORMING_CTRL_LEAVE:\n\t\tbeamforming_leave(pDM_Odm, pbuf);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\n\t}\n}\n\nu8\tbeamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enqueue)\n{\n\tstruct cmd_obj\t*ph2c;\n\tstruct drvextra_cmd_parm\t*pdrvextra_cmd_parm;\n\tstruct cmd_priv\t*pcmdpriv = &padapter->cmdpriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8\tres = _SUCCESS;\n\n\t/*20170214 ad_hoc mode and mp_mode not support BF*/\n\tif ((padapter->registrypriv.mp_mode == 1)\n\t\t|| (pmlmeinfo->state == WIFI_FW_ADHOC_STATE))\n\t\treturn res;\n\n\tif (enqueue) {\n\t\tu8\t*wk_buf;\n\n\t\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\t\tif (ph2c == NULL) {\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\t\tif (pdrvextra_cmd_parm == NULL) {\n\t\t\trtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (pbuf != NULL) {\n\t\t\twk_buf = rtw_zmalloc(size);\n\t\t\tif (wk_buf == NULL) {\n\t\t\t\trtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));\n\t\t\t\trtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));\n\t\t\t\tres = _FAIL;\n\t\t\t\tgoto exit;\n\t\t\t}\n\n\t\t\t_rtw_memcpy(wk_buf, pbuf, size);\n\t\t} else {\n\t\t\twk_buf = NULL;\n\t\t\tsize = 0;\n\t\t}\n\n\t\tpdrvextra_cmd_parm->ec_id = BEAMFORMING_WK_CID;\n\t\tpdrvextra_cmd_parm->type = type;\n\t\tpdrvextra_cmd_parm->size = size;\n\t\tpdrvextra_cmd_parm->pbuf = wk_buf;\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\t} else\n\t\tbeamforming_wk_hdl(padapter, type, pbuf);\n\nexit:\n\n\n\treturn res;\n}\n\nvoid update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta)\n{\n\tif (psta) {\n\t\tpattrib->txbf_g_id = psta->cmn.bf_info.g_id;\n\t\tpattrib->txbf_p_aid = psta->cmn.bf_info.p_aid;\n\t}\n}\n#endif /* !RTW_BEAMFORMING_VERSION_2 */\n\n#endif /* CONFIG_BEAMFORMING */\n"
  },
  {
    "path": "core/rtw_br_ext.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_BR_EXT_C_\n\n#ifdef __KERNEL__\n\t#include <linux/version.h>\n\t#include <linux/if_arp.h>\n\t#include <net/ip.h>\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0))\n\t#include <net/ipx.h>\n\t#include <linux/atalk.h>\n#endif\n\t#include <linux/udp.h>\n\t#include <linux/if_pppox.h>\n#endif\n\n#if 1\t/* rtw_wifi_driver */\n\t#include <drv_types.h>\n#else\t/* rtw_wifi_driver */\n\t#include \"./8192cd_cfg.h\"\n\n\t#ifndef __KERNEL__\n\t\t#include \"./sys-support.h\"\n\t#endif\n\n\t#include \"./8192cd.h\"\n\t#include \"./8192cd_headers.h\"\n\t#include \"./8192cd_br_ext.h\"\n\t#include \"./8192cd_debug.h\"\n#endif /* rtw_wifi_driver */\n\n#ifdef CL_IPV6_PASS\n\t#ifdef __KERNEL__\n\t\t#include <linux/ipv6.h>\n\t\t#include <linux/icmpv6.h>\n\t\t#include <net/ndisc.h>\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))\n\t\t\t#include <net/ip6_checksum.h>\n\t\t#else\n\t\t\t#include <net/checksum.h>\n\t\t#endif\n\t#endif\n#endif\n\n#ifdef CONFIG_BR_EXT\n\n/* #define BR_EXT_DEBUG */\n\n#define NAT25_IPV4\t\t01\n#define NAT25_IPV6\t\t02\n#define NAT25_IPX\t\t03\n#define NAT25_APPLE\t\t04\n#define NAT25_PPPOE\t\t05\n\n#define RTL_RELAY_TAG_LEN (ETH_ALEN)\n#define TAG_HDR_LEN\t\t4\n\n#define MAGIC_CODE\t\t0x8186\n#define MAGIC_CODE_LEN\t2\n#define WAIT_TIME_PPPOE\t5\t/* waiting time for pppoe server in sec */\n\n/*-----------------------------------------------------------------\n  How database records network address:\n           0    1    2    3    4    5    6    7    8    9   10\n        |----|----|----|----|----|----|----|----|----|----|----|\n  IPv4  |type|                             |      IP addr      |\n  IPX   |type|      Net addr     |          Node addr          |\n  IPX   |type|      Net addr     |Sckt addr|\n  Apple |type| Network |node|\n  PPPoE |type|   SID   |           AC MAC            |\n-----------------------------------------------------------------*/\n\n\n/* Find a tag in pppoe frame and return the pointer */\nstatic __inline__ unsigned char *__nat25_find_pppoe_tag(struct pppoe_hdr *ph, unsigned short type)\n{\n\tunsigned char *cur_ptr, *start_ptr;\n\tunsigned short tagLen, tagType;\n\n\tstart_ptr = cur_ptr = (unsigned char *)ph->tag;\n\twhile ((cur_ptr - start_ptr) < ntohs(ph->length)) {\n\t\t/* prevent un-alignment access */\n\t\ttagType = (unsigned short)((cur_ptr[0] << 8) + cur_ptr[1]);\n\t\ttagLen  = (unsigned short)((cur_ptr[2] << 8) + cur_ptr[3]);\n\t\tif (tagType == type)\n\t\t\treturn cur_ptr;\n\t\tcur_ptr = cur_ptr + TAG_HDR_LEN + tagLen;\n\t}\n\treturn 0;\n}\n\n\nstatic __inline__ int __nat25_add_pppoe_tag(struct sk_buff *skb, struct pppoe_tag *tag)\n{\n\tstruct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN);\n\tint data_len;\n\n\tdata_len = tag->tag_len + TAG_HDR_LEN;\n\tif (skb_tailroom(skb) < data_len) {\n\t\t_DEBUG_ERR(\"skb_tailroom() failed in add SID tag!\\n\");\n\t\treturn -1;\n\t}\n\n\tskb_put(skb, data_len);\n\t/* have a room for new tag */\n\tmemmove(((unsigned char *)ph->tag + data_len), (unsigned char *)ph->tag, ntohs(ph->length));\n\tph->length = htons(ntohs(ph->length) + data_len);\n\tmemcpy((unsigned char *)ph->tag, tag, data_len);\n\treturn data_len;\n}\n\nstatic int skb_pull_and_merge(struct sk_buff *skb, unsigned char *src, int len)\n{\n\tint tail_len;\n\tunsigned long end, tail;\n\n\tif ((src + len) > skb_tail_pointer(skb) || skb->len < len)\n\t\treturn -1;\n\n\ttail = (unsigned long)skb_tail_pointer(skb);\n\tend = (unsigned long)src + len;\n\tif (tail < end)\n\t\treturn -1;\n\n\ttail_len = (int)(tail - end);\n\tif (tail_len > 0)\n\t\tmemmove(src, src + len, tail_len);\n\n\tskb_trim(skb, skb->len - len);\n\treturn 0;\n}\n\nstatic __inline__ unsigned long __nat25_timeout(_adapter *priv)\n{\n\tunsigned long timeout;\n\n\ttimeout = jiffies - NAT25_AGEING_TIME * HZ;\n\n\treturn timeout;\n}\n\n\nstatic __inline__ int  __nat25_has_expired(_adapter *priv,\n\t\tstruct nat25_network_db_entry *fdb)\n{\n\tif (time_before_eq(fdb->ageing_timer, __nat25_timeout(priv)))\n\t\treturn 1;\n\n\treturn 0;\n}\n\n\nstatic __inline__ void __nat25_generate_ipv4_network_addr(unsigned char *networkAddr,\n\t\tunsigned int *ipAddr)\n{\n\tmemset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);\n\n\tnetworkAddr[0] = NAT25_IPV4;\n\tmemcpy(networkAddr + 7, (unsigned char *)ipAddr, 4);\n}\n\n\n#ifdef _NET_INET_IPX_H_\nstatic __inline__ void __nat25_generate_ipx_network_addr_with_node(unsigned char *networkAddr,\n\t\tunsigned int *ipxNetAddr, unsigned char *ipxNodeAddr)\n{\n\tmemset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);\n\n\tnetworkAddr[0] = NAT25_IPX;\n\tmemcpy(networkAddr + 1, (unsigned char *)ipxNetAddr, 4);\n\tmemcpy(networkAddr + 5, ipxNodeAddr, 6);\n}\n\n\nstatic __inline__ void __nat25_generate_ipx_network_addr_with_socket(unsigned char *networkAddr,\n\t\tunsigned int *ipxNetAddr, unsigned short *ipxSocketAddr)\n{\n\tmemset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);\n\n\tnetworkAddr[0] = NAT25_IPX;\n\tmemcpy(networkAddr + 1, (unsigned char *)ipxNetAddr, 4);\n\tmemcpy(networkAddr + 5, (unsigned char *)ipxSocketAddr, 2);\n}\n\n\nstatic __inline__ void __nat25_generate_apple_network_addr(unsigned char *networkAddr,\n\t\tunsigned short *network, unsigned char *node)\n{\n\tmemset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);\n\n\tnetworkAddr[0] = NAT25_APPLE;\n\tmemcpy(networkAddr + 1, (unsigned char *)network, 2);\n\tnetworkAddr[3] = *node;\n}\n#endif\n\n\nstatic __inline__ void __nat25_generate_pppoe_network_addr(unsigned char *networkAddr,\n\t\tunsigned char *ac_mac, unsigned short *sid)\n{\n\tmemset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);\n\n\tnetworkAddr[0] = NAT25_PPPOE;\n\tmemcpy(networkAddr + 1, (unsigned char *)sid, 2);\n\tmemcpy(networkAddr + 3, (unsigned char *)ac_mac, 6);\n}\n\n\n#ifdef CL_IPV6_PASS\nstatic  void __nat25_generate_ipv6_network_addr(unsigned char *networkAddr,\n\t\tunsigned int *ipAddr)\n{\n\tmemset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);\n\n\tnetworkAddr[0] = NAT25_IPV6;\n\tmemcpy(networkAddr + 1, (unsigned char *)ipAddr, 16);\n}\n\n\nstatic unsigned char *scan_tlv(unsigned char *data, int len, unsigned char tag, unsigned char len8b)\n{\n\twhile (len > 0) {\n\t\tif (*data == tag && *(data + 1) == len8b && len >= len8b * 8)\n\t\t\treturn data + 2;\n\n\t\tlen -= (*(data + 1)) * 8;\n\t\tdata += (*(data + 1)) * 8;\n\t}\n\treturn NULL;\n}\n\n\nstatic int update_nd_link_layer_addr(unsigned char *data, int len, unsigned char *replace_mac)\n{\n\tstruct icmp6hdr *icmphdr = (struct icmp6hdr *)data;\n\tunsigned char *mac;\n\n\tif (icmphdr->icmp6_type == NDISC_ROUTER_SOLICITATION) {\n\t\tif (len >= 8) {\n\t\t\tmac = scan_tlv(&data[8], len - 8, 1, 1);\n\t\t\tif (mac) {\n\t\t\t\tRTW_INFO(\"Router Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\\n\",\n\t\t\t\t\tmac[0], mac[1], mac[2], mac[3], mac[4], mac[5],\n\t\t\t\t\treplace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);\n\t\t\t\tmemcpy(mac, replace_mac, 6);\n\t\t\t\treturn 1;\n\t\t\t}\n\t\t}\n\t} else if (icmphdr->icmp6_type == NDISC_ROUTER_ADVERTISEMENT) {\n\t\tif (len >= 16) {\n\t\t\tmac = scan_tlv(&data[16], len - 16, 1, 1);\n\t\t\tif (mac) {\n\t\t\t\tRTW_INFO(\"Router Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\\n\",\n\t\t\t\t\tmac[0], mac[1], mac[2], mac[3], mac[4], mac[5],\n\t\t\t\t\treplace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);\n\t\t\t\tmemcpy(mac, replace_mac, 6);\n\t\t\t\treturn 1;\n\t\t\t}\n\t\t}\n\t} else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_SOLICITATION) {\n\t\tif (len >= 24) {\n\t\t\tmac = scan_tlv(&data[24], len - 24, 1, 1);\n\t\t\tif (mac) {\n\t\t\t\tRTW_INFO(\"Neighbor Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\\n\",\n\t\t\t\t\tmac[0], mac[1], mac[2], mac[3], mac[4], mac[5],\n\t\t\t\t\treplace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);\n\t\t\t\tmemcpy(mac, replace_mac, 6);\n\t\t\t\treturn 1;\n\t\t\t}\n\t\t}\n\t} else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_ADVERTISEMENT) {\n\t\tif (len >= 24) {\n\t\t\tmac = scan_tlv(&data[24], len - 24, 2, 1);\n\t\t\tif (mac) {\n\t\t\t\tRTW_INFO(\"Neighbor Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\\n\",\n\t\t\t\t\tmac[0], mac[1], mac[2], mac[3], mac[4], mac[5],\n\t\t\t\t\treplace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);\n\t\t\t\tmemcpy(mac, replace_mac, 6);\n\t\t\t\treturn 1;\n\t\t\t}\n\t\t}\n\t} else if (icmphdr->icmp6_type == NDISC_REDIRECT) {\n\t\tif (len >= 40) {\n\t\t\tmac = scan_tlv(&data[40], len - 40, 2, 1);\n\t\t\tif (mac) {\n\t\t\t\tRTW_INFO(\"Redirect,  replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\\n\",\n\t\t\t\t\tmac[0], mac[1], mac[2], mac[3], mac[4], mac[5],\n\t\t\t\t\treplace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);\n\t\t\t\tmemcpy(mac, replace_mac, 6);\n\t\t\t\treturn 1;\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n\n#ifdef SUPPORT_RX_UNI2MCAST\nstatic void convert_ipv6_mac_to_mc(struct sk_buff *skb)\n{\n\tstruct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN);\n\tunsigned char *dst_mac = skb->data;\n\n\t/* dst_mac[0] = 0xff; */\n\t/* dst_mac[1] = 0xff; */\n\t/*modified by qinjunjie,ipv6 multicast address ix 0x33-33-xx-xx-xx-xx*/\n\tdst_mac[0] = 0x33;\n\tdst_mac[1] = 0x33;\n\tmemcpy(&dst_mac[2], &iph->daddr.s6_addr32[3], 4);\n#if defined(__LINUX_2_6__)\n\t/*modified by qinjunjie,warning:should not remove next line*/\n\tskb->pkt_type = PACKET_MULTICAST;\n#endif\n}\n#endif /* CL_IPV6_PASS */\n#endif /* SUPPORT_RX_UNI2MCAST */\n\n\nstatic __inline__ int __nat25_network_hash(unsigned char *networkAddr)\n{\n\tif (networkAddr[0] == NAT25_IPV4) {\n\t\tunsigned long x;\n\n\t\tx = networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10];\n\n#ifdef _NET_INET_IPX_H_\n\t\treturn x & (NAT25_HASH_SIZE - 1);\n\t} else if (networkAddr[0] == NAT25_IPX) {\n\t\tunsigned long x;\n\n\t\tx = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^\n\t\t    networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10];\n\n\t\treturn x & (NAT25_HASH_SIZE - 1);\n\t} else if (networkAddr[0] == NAT25_APPLE) {\n\t\tunsigned long x;\n\n\t\tx = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3];\n\n\t\treturn x & (NAT25_HASH_SIZE - 1);\n\t} else if (networkAddr[0] == NAT25_PPPOE) {\n\t\tunsigned long x;\n\n\t\tx = networkAddr[0] ^ networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ networkAddr[6] ^ networkAddr[7] ^ networkAddr[8];\n\n#endif\n\t\treturn x & (NAT25_HASH_SIZE - 1);\n\t}\n#ifdef CL_IPV6_PASS\n\telse if (networkAddr[0] == NAT25_IPV6) {\n\t\tunsigned long x;\n\n\t\tx = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^\n\t\t    networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10] ^\n\t\t    networkAddr[11] ^ networkAddr[12] ^ networkAddr[13] ^ networkAddr[14] ^ networkAddr[15] ^\n\t\t    networkAddr[16];\n\n\t\treturn x & (NAT25_HASH_SIZE - 1);\n\t}\n#endif\n\telse {\n\t\tunsigned long x = 0;\n\t\tint i;\n\n\t\tfor (i = 0; i < MAX_NETWORK_ADDR_LEN; i++)\n\t\t\tx ^= networkAddr[i];\n\n\t\treturn x & (NAT25_HASH_SIZE - 1);\n\t}\n}\n\n\nstatic __inline__ void __network_hash_link(_adapter *priv,\n\t\tstruct nat25_network_db_entry *ent, int hash)\n{\n\t/* Caller must _enter_critical_bh already! */\n\t/* _irqL irqL; */\n\t/* _enter_critical_bh(&priv->br_ext_lock, &irqL); */\n\n\tent->next_hash = priv->nethash[hash];\n\tif (ent->next_hash != NULL)\n\t\tent->next_hash->pprev_hash = &ent->next_hash;\n\tpriv->nethash[hash] = ent;\n\tent->pprev_hash = &priv->nethash[hash];\n\n\t/* _exit_critical_bh(&priv->br_ext_lock, &irqL); */\n}\n\n\nstatic __inline__ void __network_hash_unlink(struct nat25_network_db_entry *ent)\n{\n\t/* Caller must _enter_critical_bh already! */\n\t/* _irqL irqL; */\n\t/* _enter_critical_bh(&priv->br_ext_lock, &irqL); */\n\n\t*(ent->pprev_hash) = ent->next_hash;\n\tif (ent->next_hash != NULL)\n\t\tent->next_hash->pprev_hash = ent->pprev_hash;\n\tent->next_hash = NULL;\n\tent->pprev_hash = NULL;\n\n\t/* _exit_critical_bh(&priv->br_ext_lock, &irqL); */\n}\n\n\nstatic int __nat25_db_network_lookup_and_replace(_adapter *priv,\n\t\tstruct sk_buff *skb, unsigned char *networkAddr)\n{\n\tstruct nat25_network_db_entry *db;\n\t_irqL irqL;\n\t_enter_critical_bh(&priv->br_ext_lock, &irqL);\n\n\tdb = priv->nethash[__nat25_network_hash(networkAddr)];\n\twhile (db != NULL) {\n\t\tif (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) {\n\t\t\tif (!__nat25_has_expired(priv, db)) {\n\t\t\t\t/* replace the destination mac address */\n\t\t\t\tmemcpy(skb->data, db->macAddr, ETH_ALEN);\n\t\t\t\tatomic_inc(&db->use_count);\n\n#ifdef CL_IPV6_PASS\n\t\t\t\tRTW_INFO(\"NAT25: Lookup M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\"\n\t\t\t\t\t \"%02x%02x%02x%02x%02x%02x\\n\",\n\t\t\t\t\t db->macAddr[0],\n\t\t\t\t\t db->macAddr[1],\n\t\t\t\t\t db->macAddr[2],\n\t\t\t\t\t db->macAddr[3],\n\t\t\t\t\t db->macAddr[4],\n\t\t\t\t\t db->macAddr[5],\n\t\t\t\t\t db->networkAddr[0],\n\t\t\t\t\t db->networkAddr[1],\n\t\t\t\t\t db->networkAddr[2],\n\t\t\t\t\t db->networkAddr[3],\n\t\t\t\t\t db->networkAddr[4],\n\t\t\t\t\t db->networkAddr[5],\n\t\t\t\t\t db->networkAddr[6],\n\t\t\t\t\t db->networkAddr[7],\n\t\t\t\t\t db->networkAddr[8],\n\t\t\t\t\t db->networkAddr[9],\n\t\t\t\t\t db->networkAddr[10],\n\t\t\t\t\t db->networkAddr[11],\n\t\t\t\t\t db->networkAddr[12],\n\t\t\t\t\t db->networkAddr[13],\n\t\t\t\t\t db->networkAddr[14],\n\t\t\t\t\t db->networkAddr[15],\n\t\t\t\t\t db->networkAddr[16]);\n#else\n\t\t\t\tRTW_INFO(\"NAT25: Lookup M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\\n\",\n\t\t\t\t\t db->macAddr[0],\n\t\t\t\t\t db->macAddr[1],\n\t\t\t\t\t db->macAddr[2],\n\t\t\t\t\t db->macAddr[3],\n\t\t\t\t\t db->macAddr[4],\n\t\t\t\t\t db->macAddr[5],\n\t\t\t\t\t db->networkAddr[0],\n\t\t\t\t\t db->networkAddr[1],\n\t\t\t\t\t db->networkAddr[2],\n\t\t\t\t\t db->networkAddr[3],\n\t\t\t\t\t db->networkAddr[4],\n\t\t\t\t\t db->networkAddr[5],\n\t\t\t\t\t db->networkAddr[6],\n\t\t\t\t\t db->networkAddr[7],\n\t\t\t\t\t db->networkAddr[8],\n\t\t\t\t\t db->networkAddr[9],\n\t\t\t\t\t db->networkAddr[10]);\n#endif\n\t\t\t}\n\t\t\t_exit_critical_bh(&priv->br_ext_lock, &irqL);\n\t\t\treturn 1;\n\t\t}\n\n\t\tdb = db->next_hash;\n\t}\n\n\t_exit_critical_bh(&priv->br_ext_lock, &irqL);\n\treturn 0;\n}\n\n\nstatic void __nat25_db_network_insert(_adapter *priv,\n\t\t      unsigned char *macAddr, unsigned char *networkAddr)\n{\n\tstruct nat25_network_db_entry *db;\n\tint hash;\n\t_irqL irqL;\n\t_enter_critical_bh(&priv->br_ext_lock, &irqL);\n\n\thash = __nat25_network_hash(networkAddr);\n\tdb = priv->nethash[hash];\n\twhile (db != NULL) {\n\t\tif (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) {\n\t\t\tmemcpy(db->macAddr, macAddr, ETH_ALEN);\n\t\t\tdb->ageing_timer = jiffies;\n\t\t\t_exit_critical_bh(&priv->br_ext_lock, &irqL);\n\t\t\treturn;\n\t\t}\n\n\t\tdb = db->next_hash;\n\t}\n\n\tdb = (struct nat25_network_db_entry *) rtw_malloc(sizeof(*db));\n\tif (db == NULL) {\n\t\t_exit_critical_bh(&priv->br_ext_lock, &irqL);\n\t\treturn;\n\t}\n\n\tmemcpy(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN);\n\tmemcpy(db->macAddr, macAddr, ETH_ALEN);\n\tatomic_set(&db->use_count, 1);\n\tdb->ageing_timer = jiffies;\n\n\t__network_hash_link(priv, db, hash);\n\n\t_exit_critical_bh(&priv->br_ext_lock, &irqL);\n}\n\n\nstatic void __nat25_db_print(_adapter *priv)\n{\n\t_irqL irqL;\n\t_enter_critical_bh(&priv->br_ext_lock, &irqL);\n\n#ifdef BR_EXT_DEBUG\n\tstatic int counter = 0;\n\tint i, j;\n\tstruct nat25_network_db_entry *db;\n\n\tcounter++;\n\tif ((counter % 16) != 0)\n\t\treturn;\n\n\tfor (i = 0, j = 0; i < NAT25_HASH_SIZE; i++) {\n\t\tdb = priv->nethash[i];\n\n\t\twhile (db != NULL) {\n#ifdef CL_IPV6_PASS\n\t\t\tpanic_printk(\"NAT25: DB(%d) H(%02d) C(%d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\"\n\t\t\t\t     \"%02x%02x%02x%02x%02x%02x\\n\",\n\t\t\t\t     j,\n\t\t\t\t     i,\n\t\t\t\t     atomic_read(&db->use_count),\n\t\t\t\t     db->macAddr[0],\n\t\t\t\t     db->macAddr[1],\n\t\t\t\t     db->macAddr[2],\n\t\t\t\t     db->macAddr[3],\n\t\t\t\t     db->macAddr[4],\n\t\t\t\t     db->macAddr[5],\n\t\t\t\t     db->networkAddr[0],\n\t\t\t\t     db->networkAddr[1],\n\t\t\t\t     db->networkAddr[2],\n\t\t\t\t     db->networkAddr[3],\n\t\t\t\t     db->networkAddr[4],\n\t\t\t\t     db->networkAddr[5],\n\t\t\t\t     db->networkAddr[6],\n\t\t\t\t     db->networkAddr[7],\n\t\t\t\t     db->networkAddr[8],\n\t\t\t\t     db->networkAddr[9],\n\t\t\t\t     db->networkAddr[10],\n\t\t\t\t     db->networkAddr[11],\n\t\t\t\t     db->networkAddr[12],\n\t\t\t\t     db->networkAddr[13],\n\t\t\t\t     db->networkAddr[14],\n\t\t\t\t     db->networkAddr[15],\n\t\t\t\t     db->networkAddr[16]);\n#else\n\t\t\tpanic_printk(\"NAT25: DB(%d) H(%02d) C(%d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\\n\",\n\t\t\t\t     j,\n\t\t\t\t     i,\n\t\t\t\t     atomic_read(&db->use_count),\n\t\t\t\t     db->macAddr[0],\n\t\t\t\t     db->macAddr[1],\n\t\t\t\t     db->macAddr[2],\n\t\t\t\t     db->macAddr[3],\n\t\t\t\t     db->macAddr[4],\n\t\t\t\t     db->macAddr[5],\n\t\t\t\t     db->networkAddr[0],\n\t\t\t\t     db->networkAddr[1],\n\t\t\t\t     db->networkAddr[2],\n\t\t\t\t     db->networkAddr[3],\n\t\t\t\t     db->networkAddr[4],\n\t\t\t\t     db->networkAddr[5],\n\t\t\t\t     db->networkAddr[6],\n\t\t\t\t     db->networkAddr[7],\n\t\t\t\t     db->networkAddr[8],\n\t\t\t\t     db->networkAddr[9],\n\t\t\t\t     db->networkAddr[10]);\n#endif\n\t\t\tj++;\n\n\t\t\tdb = db->next_hash;\n\t\t}\n\t}\n#endif\n\n\t_exit_critical_bh(&priv->br_ext_lock, &irqL);\n}\n\n\n\n\n/*\n *\tNAT2.5 interface\n */\n\nvoid nat25_db_cleanup(_adapter *priv)\n{\n\tint i;\n\t_irqL irqL;\n\t_enter_critical_bh(&priv->br_ext_lock, &irqL);\n\n\tfor (i = 0; i < NAT25_HASH_SIZE; i++) {\n\t\tstruct nat25_network_db_entry *f;\n\t\tf = priv->nethash[i];\n\t\twhile (f != NULL) {\n\t\t\tstruct nat25_network_db_entry *g;\n\n\t\t\tg = f->next_hash;\n\t\t\tif (priv->scdb_entry == f) {\n\t\t\t\tmemset(priv->scdb_mac, 0, ETH_ALEN);\n\t\t\t\tmemset(priv->scdb_ip, 0, 4);\n\t\t\t\tpriv->scdb_entry = NULL;\n\t\t\t}\n\t\t\t__network_hash_unlink(f);\n\t\t\trtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry));\n\n\t\t\tf = g;\n\t\t}\n\t}\n\n\t_exit_critical_bh(&priv->br_ext_lock, &irqL);\n}\n\n\nvoid nat25_db_expire(_adapter *priv)\n{\n\tint i;\n\t_irqL irqL;\n\t_enter_critical_bh(&priv->br_ext_lock, &irqL);\n\n\t/* if(!priv->ethBrExtInfo.nat25_disable) */\n\t{\n\t\tfor (i = 0; i < NAT25_HASH_SIZE; i++) {\n\t\t\tstruct nat25_network_db_entry *f;\n\t\t\tf = priv->nethash[i];\n\n\t\t\twhile (f != NULL) {\n\t\t\t\tstruct nat25_network_db_entry *g;\n\t\t\t\tg = f->next_hash;\n\n\t\t\t\tif (__nat25_has_expired(priv, f)) {\n\t\t\t\t\tif (atomic_dec_and_test(&f->use_count)) {\n#ifdef BR_EXT_DEBUG\n#ifdef CL_IPV6_PASS\n\t\t\t\t\t\tpanic_printk(\"NAT25 Expire H(%02d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\"\n\t\t\t\t\t\t\t\"%02x%02x%02x%02x%02x%02x\\n\",\n\t\t\t\t\t\t\t     i,\n\t\t\t\t\t\t\t     f->macAddr[0],\n\t\t\t\t\t\t\t     f->macAddr[1],\n\t\t\t\t\t\t\t     f->macAddr[2],\n\t\t\t\t\t\t\t     f->macAddr[3],\n\t\t\t\t\t\t\t     f->macAddr[4],\n\t\t\t\t\t\t\t     f->macAddr[5],\n\t\t\t\t\t\t\t     f->networkAddr[0],\n\t\t\t\t\t\t\t     f->networkAddr[1],\n\t\t\t\t\t\t\t     f->networkAddr[2],\n\t\t\t\t\t\t\t     f->networkAddr[3],\n\t\t\t\t\t\t\t     f->networkAddr[4],\n\t\t\t\t\t\t\t     f->networkAddr[5],\n\t\t\t\t\t\t\t     f->networkAddr[6],\n\t\t\t\t\t\t\t     f->networkAddr[7],\n\t\t\t\t\t\t\t     f->networkAddr[8],\n\t\t\t\t\t\t\t     f->networkAddr[9],\n\t\t\t\t\t\t\t     f->networkAddr[10],\n\t\t\t\t\t\t\t     f->networkAddr[11],\n\t\t\t\t\t\t\t     f->networkAddr[12],\n\t\t\t\t\t\t\t     f->networkAddr[13],\n\t\t\t\t\t\t\t     f->networkAddr[14],\n\t\t\t\t\t\t\t     f->networkAddr[15],\n\t\t\t\t\t\t\tf->networkAddr[16]);\n#else\n\n\t\t\t\t\t\tpanic_printk(\"NAT25 Expire H(%02d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\\n\",\n\t\t\t\t\t\t\t     i,\n\t\t\t\t\t\t\t     f->macAddr[0],\n\t\t\t\t\t\t\t     f->macAddr[1],\n\t\t\t\t\t\t\t     f->macAddr[2],\n\t\t\t\t\t\t\t     f->macAddr[3],\n\t\t\t\t\t\t\t     f->macAddr[4],\n\t\t\t\t\t\t\t     f->macAddr[5],\n\t\t\t\t\t\t\t     f->networkAddr[0],\n\t\t\t\t\t\t\t     f->networkAddr[1],\n\t\t\t\t\t\t\t     f->networkAddr[2],\n\t\t\t\t\t\t\t     f->networkAddr[3],\n\t\t\t\t\t\t\t     f->networkAddr[4],\n\t\t\t\t\t\t\t     f->networkAddr[5],\n\t\t\t\t\t\t\t     f->networkAddr[6],\n\t\t\t\t\t\t\t     f->networkAddr[7],\n\t\t\t\t\t\t\t     f->networkAddr[8],\n\t\t\t\t\t\t\t     f->networkAddr[9],\n\t\t\t\t\t\t\tf->networkAddr[10]);\n#endif\n#endif\n\t\t\t\t\t\tif (priv->scdb_entry == f) {\n\t\t\t\t\t\t\tmemset(priv->scdb_mac, 0, ETH_ALEN);\n\t\t\t\t\t\t\tmemset(priv->scdb_ip, 0, 4);\n\t\t\t\t\t\t\tpriv->scdb_entry = NULL;\n\t\t\t\t\t\t}\n\t\t\t\t\t\t__network_hash_unlink(f);\n\t\t\t\t\t\trtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry));\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tf = g;\n\t\t\t}\n\t\t}\n\t}\n\n\t_exit_critical_bh(&priv->br_ext_lock, &irqL);\n}\n\n\n#ifdef SUPPORT_TX_MCAST2UNI\nstatic int checkIPMcAndReplace(_adapter *priv, struct sk_buff *skb, unsigned int *dst_ip)\n{\n\tstruct stat_info\t*pstat;\n\tstruct list_head\t*phead, *plist;\n\tint i;\n\n\tphead = &priv->asoc_list;\n\tplist = phead->next;\n\n\twhile (plist != phead) {\n\t\tpstat = list_entry(plist, struct stat_info, asoc_list);\n\t\tplist = plist->next;\n\n\t\tif (pstat->ipmc_num == 0)\n\t\t\tcontinue;\n\n\t\tfor (i = 0; i < MAX_IP_MC_ENTRY; i++) {\n\t\t\tif (pstat->ipmc[i].used && !memcmp(&pstat->ipmc[i].mcmac[3], ((unsigned char *)dst_ip) + 1, 3)) {\n\t\t\t\tmemcpy(skb->data, pstat->ipmc[i].mcmac, ETH_ALEN);\n\t\t\t\treturn 1;\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n#endif\n\nint nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method)\n{\n\tunsigned short protocol;\n\tunsigned char networkAddr[MAX_NETWORK_ADDR_LEN];\n\n\tif (skb == NULL)\n\t\treturn -1;\n\n\tif ((method <= NAT25_MIN) || (method >= NAT25_MAX))\n\t\treturn -1;\n\n\tprotocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN));\n\n\t/*---------------------------------------------------*/\n\t/*                 Handle IP frame                  */\n\t/*---------------------------------------------------*/\n\tif (protocol == __constant_htons(ETH_P_IP)) {\n\t\tstruct iphdr *iph = (struct iphdr *)(skb->data + ETH_HLEN);\n\n\t\tif (((unsigned char *)(iph) + (iph->ihl << 2)) >= (skb->data + ETH_HLEN + skb->len)) {\n\t\t\tDEBUG_WARN(\"NAT25: malformed IP packet !\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tswitch (method) {\n\t\tcase NAT25_CHECK:\n\t\t\treturn -1;\n\n\t\tcase NAT25_INSERT: {\n\t\t\t/* some muticast with source IP is all zero, maybe other case is illegal */\n\t\t\t/* in class A, B, C, host address is all zero or all one is illegal */\n\t\t\tif (iph->saddr == 0)\n\t\t\t\treturn 0;\n\t\t\tRTW_INFO(\"NAT25: Insert IP, SA=%08x, DA=%08x\\n\", iph->saddr, iph->daddr);\n\t\t\t__nat25_generate_ipv4_network_addr(networkAddr, &iph->saddr);\n\t\t\t/* record source IP address and , source mac address into db */\n\t\t\t__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);\n\n\t\t\t__nat25_db_print(priv);\n\t\t}\n\t\treturn 0;\n\n\t\tcase NAT25_LOOKUP: {\n\t\t\tRTW_INFO(\"NAT25: Lookup IP, SA=%08x, DA=%08x\\n\", iph->saddr, iph->daddr);\n#ifdef SUPPORT_TX_MCAST2UNI\n\t\t\tif (priv->pshare->rf_ft_var.mc2u_disable ||\n\t\t\t    ((((OPMODE & (WIFI_STATION_STATE | WIFI_ASOC_STATE))\n\t\t\t       == (WIFI_STATION_STATE | WIFI_ASOC_STATE)) &&\n\t\t\t      !checkIPMcAndReplace(priv, skb, &iph->daddr)) ||\n\t\t\t     (OPMODE & WIFI_ADHOC_STATE)))\n#endif\n\t\t\t{\n\t\t\t\t__nat25_generate_ipv4_network_addr(networkAddr, &iph->daddr);\n\n\t\t\t\tif (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) {\n\t\t\t\t\tif (*((unsigned char *)&iph->daddr + 3) == 0xff) {\n\t\t\t\t\t\t/* L2 is unicast but L3 is broadcast, make L2 bacome broadcast */\n\t\t\t\t\t\tRTW_INFO(\"NAT25: Set DA as boardcast\\n\");\n\t\t\t\t\t\tmemset(skb->data, 0xff, ETH_ALEN);\n\t\t\t\t\t} else {\n\t\t\t\t\t\t/* forward unknow IP packet to upper TCP/IP */\n\t\t\t\t\t\tRTW_INFO(\"NAT25: Replace DA with BR's MAC\\n\");\n\t\t\t\t\t\tif ((*(u32 *)priv->br_mac) == 0 && (*(u16 *)(priv->br_mac + 4)) == 0) {\n\t\t\t\t\t\t\tvoid netdev_br_init(struct net_device *netdev);\n\t\t\t\t\t\t\tprintk(\"Re-init netdev_br_init() due to br_mac==0!\\n\");\n\t\t\t\t\t\t\tnetdev_br_init(priv->pnetdev);\n\t\t\t\t\t\t}\n\t\t\t\t\t\tmemcpy(skb->data, priv->br_mac, ETH_ALEN);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\treturn 0;\n\n\t\tdefault:\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/*---------------------------------------------------*/\n\t/*                 Handle ARP frame                 */\n\t/*---------------------------------------------------*/\n\telse if (protocol == __constant_htons(ETH_P_ARP)) {\n\t\tstruct arphdr *arp = (struct arphdr *)(skb->data + ETH_HLEN);\n\t\tunsigned char *arp_ptr = (unsigned char *)(arp + 1);\n\t\tunsigned int *sender, *target;\n\n\t\tif (arp->ar_pro != __constant_htons(ETH_P_IP)) {\n\t\t\tDEBUG_WARN(\"NAT25: arp protocol unknown (%4x)!\\n\", htons(arp->ar_pro));\n\t\t\treturn -1;\n\t\t}\n\n\t\tswitch (method) {\n\t\tcase NAT25_CHECK:\n\t\t\treturn 0;\t/* skb_copy for all ARP frame */\n\n\t\tcase NAT25_INSERT: {\n\t\t\tRTW_INFO(\"NAT25: Insert ARP, MAC=%02x%02x%02x%02x%02x%02x\\n\", arp_ptr[0],\n\t\t\t\tarp_ptr[1], arp_ptr[2], arp_ptr[3], arp_ptr[4], arp_ptr[5]);\n\n\t\t\t/* change to ARP sender mac address to wlan STA address */\n\t\t\tmemcpy(arp_ptr, GET_MY_HWADDR(priv), ETH_ALEN);\n\n\t\t\tarp_ptr += arp->ar_hln;\n\t\t\tsender = (unsigned int *)arp_ptr;\n\n\t\t\t__nat25_generate_ipv4_network_addr(networkAddr, sender);\n\n\t\t\t__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);\n\n\t\t\t__nat25_db_print(priv);\n\t\t}\n\t\treturn 0;\n\n\t\tcase NAT25_LOOKUP: {\n\t\t\tRTW_INFO(\"NAT25: Lookup ARP\\n\");\n\n\t\t\tarp_ptr += arp->ar_hln;\n\t\t\tsender = (unsigned int *)arp_ptr;\n\t\t\tarp_ptr += (arp->ar_hln + arp->ar_pln);\n\t\t\ttarget = (unsigned int *)arp_ptr;\n\n\t\t\t__nat25_generate_ipv4_network_addr(networkAddr, target);\n\n\t\t\t__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);\n\n\t\t\t/* change to ARP target mac address to Lookup result */\n\t\t\tarp_ptr = (unsigned char *)(arp + 1);\n\t\t\tarp_ptr += (arp->ar_hln + arp->ar_pln);\n\t\t\tmemcpy(arp_ptr, skb->data, ETH_ALEN);\n\t\t}\n\t\treturn 0;\n\n\t\tdefault:\n\t\t\treturn -1;\n\t\t}\n\t}\n\n#ifdef _NET_INET_IPX_H_\n\t/*---------------------------------------------------*/\n\t/*         Handle IPX and Apple Talk frame          */\n\t/*---------------------------------------------------*/\n\telse if ((protocol == __constant_htons(ETH_P_IPX)) ||\n\t\t (protocol == __constant_htons(ETH_P_ATALK)) ||\n\t\t (protocol == __constant_htons(ETH_P_AARP))) {\n\t\tunsigned char ipx_header[2] = {0xFF, 0xFF};\n\t\tstruct ipxhdr\t*ipx = NULL;\n\t\tstruct elapaarp\t*ea = NULL;\n\t\tstruct ddpehdr\t*ddp = NULL;\n\t\tunsigned char *framePtr = skb->data + ETH_HLEN;\n\n\t\tif (protocol == __constant_htons(ETH_P_IPX)) {\n\t\t\tRTW_INFO(\"NAT25: Protocol=IPX (Ethernet II)\\n\");\n\t\t\tipx = (struct ipxhdr *)framePtr;\n\t\t} else { /* if(protocol <= __constant_htons(ETH_FRAME_LEN)) */\n\t\t\tif (!memcmp(ipx_header, framePtr, 2)) {\n\t\t\t\tRTW_INFO(\"NAT25: Protocol=IPX (Ethernet 802.3)\\n\");\n\t\t\t\tipx = (struct ipxhdr *)framePtr;\n\t\t\t} else {\n\t\t\t\tunsigned char ipx_8022_type =  0xE0;\n\t\t\t\tunsigned char snap_8022_type = 0xAA;\n\n\t\t\t\tif (*framePtr == snap_8022_type) {\n\t\t\t\t\tunsigned char ipx_snap_id[5] = {0x0, 0x0, 0x0, 0x81, 0x37};\t\t/* IPX SNAP ID */\n\t\t\t\t\tunsigned char aarp_snap_id[5] = {0x00, 0x00, 0x00, 0x80, 0xF3};\t/* Apple Talk AARP SNAP ID */\n\t\t\t\t\tunsigned char ddp_snap_id[5] = {0x08, 0x00, 0x07, 0x80, 0x9B};\t/* Apple Talk DDP SNAP ID */\n\n\t\t\t\t\tframePtr += 3;\t/* eliminate the 802.2 header */\n\n\t\t\t\t\tif (!memcmp(ipx_snap_id, framePtr, 5)) {\n\t\t\t\t\t\tframePtr += 5;\t/* eliminate the SNAP header */\n\n\t\t\t\t\t\tRTW_INFO(\"NAT25: Protocol=IPX (Ethernet SNAP)\\n\");\n\t\t\t\t\t\tipx = (struct ipxhdr *)framePtr;\n\t\t\t\t\t} else if (!memcmp(aarp_snap_id, framePtr, 5)) {\n\t\t\t\t\t\tframePtr += 5;\t/* eliminate the SNAP header */\n\n\t\t\t\t\t\tea = (struct elapaarp *)framePtr;\n\t\t\t\t\t} else if (!memcmp(ddp_snap_id, framePtr, 5)) {\n\t\t\t\t\t\tframePtr += 5;\t/* eliminate the SNAP header */\n\n\t\t\t\t\t\tddp = (struct ddpehdr *)framePtr;\n\t\t\t\t\t} else {\n\t\t\t\t\t\tDEBUG_WARN(\"NAT25: Protocol=Ethernet SNAP %02x%02x%02x%02x%02x\\n\", framePtr[0],\n\t\t\t\t\t\t\tframePtr[1], framePtr[2], framePtr[3], framePtr[4]);\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\t\t\t\t} else if (*framePtr == ipx_8022_type) {\n\t\t\t\t\tframePtr += 3;\t/* eliminate the 802.2 header */\n\n\t\t\t\t\tif (!memcmp(ipx_header, framePtr, 2)) {\n\t\t\t\t\t\tRTW_INFO(\"NAT25: Protocol=IPX (Ethernet 802.2)\\n\");\n\t\t\t\t\t\tipx = (struct ipxhdr *)framePtr;\n\t\t\t\t\t} else\n\t\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/*   IPX  */\n\t\tif (ipx != NULL) {\n\t\t\tswitch (method) {\n\t\t\tcase NAT25_CHECK:\n\t\t\t\tif (!memcmp(skb->data + ETH_ALEN, ipx->ipx_source.node, ETH_ALEN)) {\n\t\t\t\t\tRTW_INFO(\"NAT25: Check IPX skb_copy\\n\");\n\t\t\t\t\treturn 0;\n\t\t\t\t}\n\t\t\t\treturn -1;\n\n\t\t\tcase NAT25_INSERT: {\n\t\t\t\tRTW_INFO(\"NAT25: Insert IPX, Dest=%08x,%02x%02x%02x%02x%02x%02x,%04x Source=%08x,%02x%02x%02x%02x%02x%02x,%04x\\n\",\n\t\t\t\t\t ipx->ipx_dest.net,\n\t\t\t\t\t ipx->ipx_dest.node[0],\n\t\t\t\t\t ipx->ipx_dest.node[1],\n\t\t\t\t\t ipx->ipx_dest.node[2],\n\t\t\t\t\t ipx->ipx_dest.node[3],\n\t\t\t\t\t ipx->ipx_dest.node[4],\n\t\t\t\t\t ipx->ipx_dest.node[5],\n\t\t\t\t\t ipx->ipx_dest.sock,\n\t\t\t\t\t ipx->ipx_source.net,\n\t\t\t\t\t ipx->ipx_source.node[0],\n\t\t\t\t\t ipx->ipx_source.node[1],\n\t\t\t\t\t ipx->ipx_source.node[2],\n\t\t\t\t\t ipx->ipx_source.node[3],\n\t\t\t\t\t ipx->ipx_source.node[4],\n\t\t\t\t\t ipx->ipx_source.node[5],\n\t\t\t\t\t ipx->ipx_source.sock);\n\n\t\t\t\tif (!memcmp(skb->data + ETH_ALEN, ipx->ipx_source.node, ETH_ALEN)) {\n\t\t\t\t\tRTW_INFO(\"NAT25: Use IPX Net, and Socket as network addr\\n\");\n\n\t\t\t\t\t__nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_source.net, &ipx->ipx_source.sock);\n\n\t\t\t\t\t/* change IPX source node addr to wlan STA address */\n\t\t\t\t\tmemcpy(ipx->ipx_source.node, GET_MY_HWADDR(priv), ETH_ALEN);\n\t\t\t\t} else\n\t\t\t\t\t__nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_source.net, ipx->ipx_source.node);\n\n\t\t\t\t__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);\n\n\t\t\t\t__nat25_db_print(priv);\n\t\t\t}\n\t\t\treturn 0;\n\n\t\t\tcase NAT25_LOOKUP: {\n\t\t\t\tif (!memcmp(GET_MY_HWADDR(priv), ipx->ipx_dest.node, ETH_ALEN)) {\n\t\t\t\t\tRTW_INFO(\"NAT25: Lookup IPX, Modify Destination IPX Node addr\\n\");\n\n\t\t\t\t\t__nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_dest.net, &ipx->ipx_dest.sock);\n\n\t\t\t\t\t__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);\n\n\t\t\t\t\t/* replace IPX destination node addr with Lookup destination MAC addr */\n\t\t\t\t\tmemcpy(ipx->ipx_dest.node, skb->data, ETH_ALEN);\n\t\t\t\t} else {\n\t\t\t\t\t__nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_dest.net, ipx->ipx_dest.node);\n\n\t\t\t\t\t__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);\n\t\t\t\t}\n\t\t\t}\n\t\t\treturn 0;\n\n\t\t\tdefault:\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\n\t\t/*   AARP  */\n\t\telse if (ea != NULL) {\n\t\t\t/* Sanity check fields. */\n\t\t\tif (ea->hw_len != ETH_ALEN || ea->pa_len != AARP_PA_ALEN) {\n\t\t\t\tDEBUG_WARN(\"NAT25: Appletalk AARP Sanity check fail!\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\tswitch (method) {\n\t\t\tcase NAT25_CHECK:\n\t\t\t\treturn 0;\n\n\t\t\tcase NAT25_INSERT: {\n\t\t\t\t/* change to AARP source mac address to wlan STA address */\n\t\t\t\tmemcpy(ea->hw_src, GET_MY_HWADDR(priv), ETH_ALEN);\n\n\t\t\t\tRTW_INFO(\"NAT25: Insert AARP, Source=%d,%d Destination=%d,%d\\n\",\n\t\t\t\t\t ea->pa_src_net,\n\t\t\t\t\t ea->pa_src_node,\n\t\t\t\t\t ea->pa_dst_net,\n\t\t\t\t\t ea->pa_dst_node);\n\n\t\t\t\t__nat25_generate_apple_network_addr(networkAddr, &ea->pa_src_net, &ea->pa_src_node);\n\n\t\t\t\t__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);\n\n\t\t\t\t__nat25_db_print(priv);\n\t\t\t}\n\t\t\treturn 0;\n\n\t\t\tcase NAT25_LOOKUP: {\n\t\t\t\tRTW_INFO(\"NAT25: Lookup AARP, Source=%d,%d Destination=%d,%d\\n\",\n\t\t\t\t\t ea->pa_src_net,\n\t\t\t\t\t ea->pa_src_node,\n\t\t\t\t\t ea->pa_dst_net,\n\t\t\t\t\t ea->pa_dst_node);\n\n\t\t\t\t__nat25_generate_apple_network_addr(networkAddr, &ea->pa_dst_net, &ea->pa_dst_node);\n\n\t\t\t\t__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);\n\n\t\t\t\t/* change to AARP destination mac address to Lookup result */\n\t\t\t\tmemcpy(ea->hw_dst, skb->data, ETH_ALEN);\n\t\t\t}\n\t\t\treturn 0;\n\n\t\t\tdefault:\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\n\t\t/*   DDP  */\n\t\telse if (ddp != NULL) {\n\t\t\tswitch (method) {\n\t\t\tcase NAT25_CHECK:\n\t\t\t\treturn -1;\n\n\t\t\tcase NAT25_INSERT: {\n\t\t\t\tRTW_INFO(\"NAT25: Insert DDP, Source=%d,%d Destination=%d,%d\\n\",\n\t\t\t\t\t ddp->deh_snet,\n\t\t\t\t\t ddp->deh_snode,\n\t\t\t\t\t ddp->deh_dnet,\n\t\t\t\t\t ddp->deh_dnode);\n\n\t\t\t\t__nat25_generate_apple_network_addr(networkAddr, &ddp->deh_snet, &ddp->deh_snode);\n\n\t\t\t\t__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);\n\n\t\t\t\t__nat25_db_print(priv);\n\t\t\t}\n\t\t\treturn 0;\n\n\t\t\tcase NAT25_LOOKUP: {\n\t\t\t\tRTW_INFO(\"NAT25: Lookup DDP, Source=%d,%d Destination=%d,%d\\n\",\n\t\t\t\t\t ddp->deh_snet,\n\t\t\t\t\t ddp->deh_snode,\n\t\t\t\t\t ddp->deh_dnet,\n\t\t\t\t\t ddp->deh_dnode);\n\n\t\t\t\t__nat25_generate_apple_network_addr(networkAddr, &ddp->deh_dnet, &ddp->deh_dnode);\n\n\t\t\t\t__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);\n\t\t\t}\n\t\t\treturn 0;\n\n\t\t\tdefault:\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\n\t\treturn -1;\n\t}\n#endif\n\n\t/*---------------------------------------------------*/\n\t/*                Handle PPPoE frame                */\n\t/*---------------------------------------------------*/\n\telse if ((protocol == __constant_htons(ETH_P_PPP_DISC)) ||\n\t\t (protocol == __constant_htons(ETH_P_PPP_SES))) {\n\t\tstruct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN);\n\t\tunsigned short *pMagic;\n\n\t\tswitch (method) {\n\t\tcase NAT25_CHECK:\n\t\t\tif (ph->sid == 0)\n\t\t\t\treturn 0;\n\t\t\treturn 1;\n\n\t\tcase NAT25_INSERT:\n\t\t\tif (ph->sid == 0) {\t/* Discovery phase according to tag */\n\t\t\t\tif (ph->code == PADI_CODE || ph->code == PADR_CODE) {\n\t\t\t\t\tif (priv->ethBrExtInfo.addPPPoETag) {\n\t\t\t\t\t\tstruct pppoe_tag *tag, *pOldTag;\n\t\t\t\t\t\tunsigned char tag_buf[40];\n\t\t\t\t\t\tint old_tag_len = 0;\n\n\t\t\t\t\t\ttag = (struct pppoe_tag *)tag_buf;\n\t\t\t\t\t\tpOldTag = (struct pppoe_tag *)__nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID));\n\t\t\t\t\t\tif (pOldTag) { /* if SID existed, copy old value and delete it */\n\t\t\t\t\t\t\told_tag_len = ntohs(pOldTag->tag_len);\n\t\t\t\t\t\t\tif (old_tag_len + TAG_HDR_LEN + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN > sizeof(tag_buf)) {\n\t\t\t\t\t\t\t\tDEBUG_ERR(\"SID tag length too long!\\n\");\n\t\t\t\t\t\t\t\treturn -1;\n\t\t\t\t\t\t\t}\n\n\t\t\t\t\t\t\tmemcpy(tag->tag_data + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN,\n\t\t\t\t\t\t\t       pOldTag->tag_data, old_tag_len);\n\n\t\t\t\t\t\t\tif (skb_pull_and_merge(skb, (unsigned char *)pOldTag, TAG_HDR_LEN + old_tag_len) < 0) {\n\t\t\t\t\t\t\t\tDEBUG_ERR(\"call skb_pull_and_merge() failed in PADI/R packet!\\n\");\n\t\t\t\t\t\t\t\treturn -1;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tph->length = htons(ntohs(ph->length) - TAG_HDR_LEN - old_tag_len);\n\t\t\t\t\t\t}\n\n\t\t\t\t\t\ttag->tag_type = PTT_RELAY_SID;\n\t\t\t\t\t\ttag->tag_len = htons(MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN + old_tag_len);\n\n\t\t\t\t\t\t/* insert the magic_code+client mac in relay tag */\n\t\t\t\t\t\tpMagic = (unsigned short *)tag->tag_data;\n\t\t\t\t\t\t*pMagic = htons(MAGIC_CODE);\n\t\t\t\t\t\tmemcpy(tag->tag_data + MAGIC_CODE_LEN, skb->data + ETH_ALEN, ETH_ALEN);\n\n\t\t\t\t\t\t/* Add relay tag */\n\t\t\t\t\t\tif (__nat25_add_pppoe_tag(skb, tag) < 0)\n\t\t\t\t\t\t\treturn -1;\n\n\t\t\t\t\t\tRTW_INFO(\"NAT25: Insert PPPoE, forward %s packet\\n\",\n\t\t\t\t\t\t\t(ph->code == PADI_CODE ? \"PADI\" : \"PADR\"));\n\t\t\t\t\t} else { /* not add relay tag */\n\t\t\t\t\t\tif (priv->pppoe_connection_in_progress &&\n\t\t\t\t\t\t    memcmp(skb->data + ETH_ALEN, priv->pppoe_addr, ETH_ALEN))\t {\n\t\t\t\t\t\t\tDEBUG_ERR(\"Discard PPPoE packet due to another PPPoE connection is in progress!\\n\");\n\t\t\t\t\t\t\treturn -2;\n\t\t\t\t\t\t}\n\n\t\t\t\t\t\tif (priv->pppoe_connection_in_progress == 0)\n\t\t\t\t\t\t\tmemcpy(priv->pppoe_addr, skb->data + ETH_ALEN, ETH_ALEN);\n\n\t\t\t\t\t\tpriv->pppoe_connection_in_progress = WAIT_TIME_PPPOE;\n\t\t\t\t\t}\n\t\t\t\t} else\n\t\t\t\t\treturn -1;\n\t\t\t} else {\t/* session phase */\n\t\t\t\tRTW_INFO(\"NAT25: Insert PPPoE, insert session packet to %s\\n\", skb->dev->name);\n\n\t\t\t\t__nat25_generate_pppoe_network_addr(networkAddr, skb->data, &(ph->sid));\n\n\t\t\t\t__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);\n\n\t\t\t\t__nat25_db_print(priv);\n\n\t\t\t\tif (!priv->ethBrExtInfo.addPPPoETag &&\n\t\t\t\t    priv->pppoe_connection_in_progress &&\n\t\t\t\t    !memcmp(skb->data + ETH_ALEN, priv->pppoe_addr, ETH_ALEN))\n\t\t\t\t\tpriv->pppoe_connection_in_progress = 0;\n\t\t\t}\n\t\t\treturn 0;\n\n\t\tcase NAT25_LOOKUP:\n\t\t\tif (ph->code == PADO_CODE || ph->code == PADS_CODE) {\n\t\t\t\tif (priv->ethBrExtInfo.addPPPoETag) {\n\t\t\t\t\tstruct pppoe_tag *tag;\n\t\t\t\t\tunsigned char *ptr;\n\t\t\t\t\tunsigned short tagType, tagLen;\n\t\t\t\t\tint offset = 0;\n\n\t\t\t\t\tptr = __nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID));\n\t\t\t\t\tif (ptr == 0) {\n\t\t\t\t\t\tDEBUG_ERR(\"Fail to find PTT_RELAY_SID in FADO!\\n\");\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\n\t\t\t\t\ttag = (struct pppoe_tag *)ptr;\n\t\t\t\t\ttagType = (unsigned short)((ptr[0] << 8) + ptr[1]);\n\t\t\t\t\ttagLen = (unsigned short)((ptr[2] << 8) + ptr[3]);\n\n\t\t\t\t\tif ((tagType != ntohs(PTT_RELAY_SID)) || (tagLen < (MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN))) {\n\t\t\t\t\t\tDEBUG_ERR(\"Invalid PTT_RELAY_SID tag length [%d]!\\n\", tagLen);\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\n\t\t\t\t\tpMagic = (unsigned short *)tag->tag_data;\n\t\t\t\t\tif (ntohs(*pMagic) != MAGIC_CODE) {\n\t\t\t\t\t\tDEBUG_ERR(\"Can't find MAGIC_CODE in %s packet!\\n\",\n\t\t\t\t\t\t\t(ph->code == PADO_CODE ? \"PADO\" : \"PADS\"));\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\n\t\t\t\t\tmemcpy(skb->data, tag->tag_data + MAGIC_CODE_LEN, ETH_ALEN);\n\n\t\t\t\t\tif (tagLen > MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN)\n\t\t\t\t\t\toffset = TAG_HDR_LEN;\n\n\t\t\t\t\tif (skb_pull_and_merge(skb, ptr + offset, TAG_HDR_LEN + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN - offset) < 0) {\n\t\t\t\t\t\tDEBUG_ERR(\"call skb_pull_and_merge() failed in PADO packet!\\n\");\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\t\t\t\t\tph->length = htons(ntohs(ph->length) - (TAG_HDR_LEN + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN - offset));\n\t\t\t\t\tif (offset > 0)\n\t\t\t\t\t\ttag->tag_len = htons(tagLen - MAGIC_CODE_LEN - RTL_RELAY_TAG_LEN);\n\n\t\t\t\t\tRTW_INFO(\"NAT25: Lookup PPPoE, forward %s Packet from %s\\n\",\n\t\t\t\t\t\t(ph->code == PADO_CODE ? \"PADO\" : \"PADS\"),\tskb->dev->name);\n\t\t\t\t} else { /* not add relay tag */\n\t\t\t\t\tif (!priv->pppoe_connection_in_progress) {\n\t\t\t\t\t\tDEBUG_ERR(\"Discard PPPoE packet due to no connection in progresss!\\n\");\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\t\t\t\t\tmemcpy(skb->data, priv->pppoe_addr, ETH_ALEN);\n\t\t\t\t\tpriv->pppoe_connection_in_progress = WAIT_TIME_PPPOE;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif (ph->sid != 0) {\n\t\t\t\t\tRTW_INFO(\"NAT25: Lookup PPPoE, lookup session packet from %s\\n\", skb->dev->name);\n\t\t\t\t\t__nat25_generate_pppoe_network_addr(networkAddr, skb->data + ETH_ALEN, &(ph->sid));\n\n\t\t\t\t\t__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);\n\n\t\t\t\t\t__nat25_db_print(priv);\n\t\t\t\t} else\n\t\t\t\t\treturn -1;\n\n\t\t\t}\n\t\t\treturn 0;\n\n\t\tdefault:\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/*---------------------------------------------------*/\n\t/*                 Handle EAP frame                 */\n\t/*---------------------------------------------------*/\n\telse if (protocol == __constant_htons(0x888e)) {\n\t\tswitch (method) {\n\t\tcase NAT25_CHECK:\n\t\t\treturn -1;\n\n\t\tcase NAT25_INSERT:\n\t\t\treturn 0;\n\n\t\tcase NAT25_LOOKUP:\n\t\t\treturn 0;\n\n\t\tdefault:\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/*---------------------------------------------------*/\n\t/*         Handle C-Media proprietary frame         */\n\t/*---------------------------------------------------*/\n\telse if ((protocol == __constant_htons(0xe2ae)) ||\n\t\t (protocol == __constant_htons(0xe2af))) {\n\t\tswitch (method) {\n\t\tcase NAT25_CHECK:\n\t\t\treturn -1;\n\n\t\tcase NAT25_INSERT:\n\t\t\treturn 0;\n\n\t\tcase NAT25_LOOKUP:\n\t\t\treturn 0;\n\n\t\tdefault:\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/*---------------------------------------------------*/\n\t/*         Handle IPV6 frame      \t\t\t\t\t\t\t */\n\t/*---------------------------------------------------*/\n#ifdef CL_IPV6_PASS\n\telse if (protocol == __constant_htons(ETH_P_IPV6)) {\n\t\tstruct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN);\n\n\t\tif (sizeof(*iph) >= (skb->len - ETH_HLEN)) {\n\t\t\tDEBUG_WARN(\"NAT25: malformed IPv6 packet !\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tswitch (method) {\n\t\tcase NAT25_CHECK:\n\t\t\tif (skb->data[0] & 1)\n\t\t\t\treturn 0;\n\t\t\treturn -1;\n\n\t\tcase NAT25_INSERT: {\n\t\t\tRTW_INFO(\"NAT25: Insert IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x,\"\n\t\t\t\t\" DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\\n\",\n\t\t\t\tiph->saddr.s6_addr16[0], iph->saddr.s6_addr16[1], iph->saddr.s6_addr16[2], iph->saddr.s6_addr16[3],\n\t\t\t\tiph->saddr.s6_addr16[4], iph->saddr.s6_addr16[5], iph->saddr.s6_addr16[6], iph->saddr.s6_addr16[7],\n\t\t\t\tiph->daddr.s6_addr16[0], iph->daddr.s6_addr16[1], iph->daddr.s6_addr16[2], iph->daddr.s6_addr16[3],\n\t\t\t\tiph->daddr.s6_addr16[4], iph->daddr.s6_addr16[5], iph->daddr.s6_addr16[6], iph->daddr.s6_addr16[7]);\n\n\t\t\tif (memcmp(&iph->saddr, \"\\x0\\x0\\x0\\x0\\x0\\x0\\x0\\x0\\x0\\x0\\x0\\x0\\x0\\x0\\x0\\x0\", 16)) {\n\t\t\t\t__nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->saddr);\n\t\t\t\t__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);\n\t\t\t\t__nat25_db_print(priv);\n\n\t\t\t\tif (iph->nexthdr == IPPROTO_ICMPV6 &&\n\t\t\t\t    skb->len > (ETH_HLEN +  sizeof(*iph) + 4)) {\n\t\t\t\t\tif (update_nd_link_layer_addr(skb->data + ETH_HLEN + sizeof(*iph),\n\t\t\t\t\t\tskb->len - ETH_HLEN - sizeof(*iph), GET_MY_HWADDR(priv))) {\n\t\t\t\t\t\tstruct icmp6hdr  *hdr = (struct icmp6hdr *)(skb->data + ETH_HLEN + sizeof(*iph));\n\t\t\t\t\t\thdr->icmp6_cksum = 0;\n\t\t\t\t\t\thdr->icmp6_cksum = csum_ipv6_magic(&iph->saddr, &iph->daddr,\n\t\t\t\t\t\t\tiph->payload_len,\n\t\t\t\t\t\t\tIPPROTO_ICMPV6,\n\t\t\t\t\t\t\tcsum_partial((__u8 *)hdr, iph->payload_len, 0));\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\treturn 0;\n\n\t\tcase NAT25_LOOKUP:\n\t\t\tRTW_INFO(\"NAT25: Lookup IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x,\"\n\t\t\t\t \" DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\\n\",\n\t\t\t\tiph->saddr.s6_addr16[0], iph->saddr.s6_addr16[1], iph->saddr.s6_addr16[2], iph->saddr.s6_addr16[3],\n\t\t\t\tiph->saddr.s6_addr16[4], iph->saddr.s6_addr16[5], iph->saddr.s6_addr16[6], iph->saddr.s6_addr16[7],\n\t\t\t\tiph->daddr.s6_addr16[0], iph->daddr.s6_addr16[1], iph->daddr.s6_addr16[2], iph->daddr.s6_addr16[3],\n\t\t\t\tiph->daddr.s6_addr16[4], iph->daddr.s6_addr16[5], iph->daddr.s6_addr16[6], iph->daddr.s6_addr16[7]);\n\n\n\t\t\t__nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->daddr);\n\t\t\tif (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) {\n#ifdef SUPPORT_RX_UNI2MCAST\n\t\t\t\tif (iph->daddr.s6_addr[0] == 0xff)\n\t\t\t\t\tconvert_ipv6_mac_to_mc(skb);\n#endif\n\t\t\t}\n\t\t\treturn 0;\n\n\t\tdefault:\n\t\t\treturn -1;\n\t\t}\n\t}\n#endif /* CL_IPV6_PASS */\n\n\treturn -1;\n}\n\n\nint nat25_handle_frame(_adapter *priv, struct sk_buff *skb)\n{\n#ifdef BR_EXT_DEBUG\n\tif ((!priv->ethBrExtInfo.nat25_disable) && (!(skb->data[0] & 1))) {\n\t\tpanic_printk(\"NAT25: Input Frame: DA=%02x%02x%02x%02x%02x%02x SA=%02x%02x%02x%02x%02x%02x\\n\",\n\t\t\t     skb->data[0],\n\t\t\t     skb->data[1],\n\t\t\t     skb->data[2],\n\t\t\t     skb->data[3],\n\t\t\t     skb->data[4],\n\t\t\t     skb->data[5],\n\t\t\t     skb->data[6],\n\t\t\t     skb->data[7],\n\t\t\t     skb->data[8],\n\t\t\t     skb->data[9],\n\t\t\t     skb->data[10],\n\t\t\t     skb->data[11]);\n\t}\n#endif\n\n\tif (!(skb->data[0] & 1)) {\n\t\tint is_vlan_tag = 0, i, retval = 0;\n\t\tunsigned short vlan_hdr = 0;\n\n\t\tif (*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_8021Q)) {\n\t\t\tis_vlan_tag = 1;\n\t\t\tvlan_hdr = *((unsigned short *)(skb->data + ETH_ALEN * 2 + 2));\n\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\t*((unsigned short *)(skb->data + ETH_ALEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + ETH_ALEN * 2 - 2 - i * 2));\n\t\t\tskb_pull(skb, 4);\n\t\t}\n\n\t\tif (!priv->ethBrExtInfo.nat25_disable) {\n\t\t\t_irqL irqL;\n\t\t\t_enter_critical_bh(&priv->br_ext_lock, &irqL);\n\t\t\t/*\n\t\t\t *\tThis function look up the destination network address from\n\t\t\t *\tthe NAT2.5 database. Return value = -1 means that the\n\t\t\t *\tcorresponding network protocol is NOT support.\n\t\t\t */\n\t\t\tif (!priv->ethBrExtInfo.nat25sc_disable &&\n\t\t\t    (*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_IP)) &&\n\t\t\t    !memcmp(priv->scdb_ip, skb->data + ETH_HLEN + 16, 4)) {\n\t\t\t\tmemcpy(skb->data, priv->scdb_mac, ETH_ALEN);\n\n\t\t\t\t_exit_critical_bh(&priv->br_ext_lock, &irqL);\n\t\t\t} else {\n\t\t\t\t_exit_critical_bh(&priv->br_ext_lock, &irqL);\n\n\t\t\t\tretval = nat25_db_handle(priv, skb, NAT25_LOOKUP);\n\t\t\t}\n\t\t} else {\n\t\t\tif (((*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_IP)) &&\n\t\t\t     !memcmp(priv->br_ip, skb->data + ETH_HLEN + 16, 4)) ||\n\t\t\t    ((*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_ARP)) &&\n\t\t\t     !memcmp(priv->br_ip, skb->data + ETH_HLEN + 24, 4))) {\n\t\t\t\t/* for traffic to upper TCP/IP */\n\t\t\t\tretval = nat25_db_handle(priv, skb, NAT25_LOOKUP);\n\t\t\t}\n\t\t}\n\n\t\tif (is_vlan_tag) {\n\t\t\tskb_push(skb, 4);\n\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\t*((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2));\n\t\t\t*((unsigned short *)(skb->data + ETH_ALEN * 2)) = __constant_htons(ETH_P_8021Q);\n\t\t\t*((unsigned short *)(skb->data + ETH_ALEN * 2 + 2)) = vlan_hdr;\n\t\t}\n\n\t\tif (retval == -1) {\n\t\t\t/* DEBUG_ERR(\"NAT25: Lookup fail!\\n\"); */\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n#if 0\nvoid mac_clone(_adapter *priv, unsigned char *addr)\n{\n\tstruct sockaddr sa;\n\n\tmemcpy(sa.sa_data, addr, ETH_ALEN);\n\tRTW_INFO(\"MAC Clone: Addr=%02x%02x%02x%02x%02x%02x\\n\",\n\t\t addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);\n\trtl8192cd_set_hwaddr(priv->dev, &sa);\n}\n\n\nint mac_clone_handle_frame(_adapter *priv, struct sk_buff *skb)\n{\n\tif (priv->ethBrExtInfo.macclone_enable && !priv->macclone_completed) {\n\t\tif (!(skb->data[ETH_ALEN] & 1)) {\t/* check any other particular MAC add */\n\t\t\tif (memcmp(skb->data + ETH_ALEN, GET_MY_HWADDR(priv), ETH_ALEN) &&\n\t\t\t    ((priv->dev->br_port) &&\n\t\t\t     memcmp(skb->data + ETH_ALEN, priv->br_mac, ETH_ALEN))) {\n\t\t\t\tmac_clone(priv, skb->data + ETH_ALEN);\n\t\t\t\tpriv->macclone_completed = 1;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n#endif /* 0 */\n\n#define SERVER_PORT\t\t\t67\n#define CLIENT_PORT\t\t\t68\n#define DHCP_MAGIC\t\t\t0x63825363\n#define BROADCAST_FLAG\t\t0x8000\n\nstruct dhcpMessage {\n\tu_int8_t op;\n\tu_int8_t htype;\n\tu_int8_t hlen;\n\tu_int8_t hops;\n\tu_int32_t xid;\n\tu_int16_t secs;\n\tu_int16_t flags;\n\tu_int32_t ciaddr;\n\tu_int32_t yiaddr;\n\tu_int32_t siaddr;\n\tu_int32_t giaddr;\n\tu_int8_t chaddr[16];\n\tu_int8_t sname[64];\n\tu_int8_t file[128];\n\tu_int32_t cookie;\n\tu_int8_t options[308]; /* 312 - cookie */\n};\n\nvoid dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb)\n{\n\tif (skb == NULL)\n\t\treturn;\n\n\tif (!priv->ethBrExtInfo.dhcp_bcst_disable) {\n\t\tunsigned short protocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN));\n\n\t\tif (protocol == __constant_htons(ETH_P_IP)) { /* IP */\n\t\t\tstruct iphdr *iph = (struct iphdr *)(skb->data + ETH_HLEN);\n\n\t\t\tif (iph->protocol == IPPROTO_UDP) { /* UDP */\n\t\t\t\tstruct udphdr *udph = (struct udphdr *)((SIZE_PTR)iph + (iph->ihl << 2));\n\n\t\t\t\tif ((udph->source == __constant_htons(CLIENT_PORT))\n\t\t\t\t    && (udph->dest == __constant_htons(SERVER_PORT))) { /* DHCP request */\n\t\t\t\t\tstruct dhcpMessage *dhcph =\n\t\t\t\t\t\t(struct dhcpMessage *)((SIZE_PTR)udph + sizeof(struct udphdr));\n\n\t\t\t\t\tif (dhcph->cookie == __constant_htonl(DHCP_MAGIC)) { /* match magic word */\n\t\t\t\t\t\tif (!(dhcph->flags & htons(BROADCAST_FLAG))) { /* if not broadcast */\n\t\t\t\t\t\t\tregister int sum = 0;\n\n\t\t\t\t\t\t\tRTW_INFO(\"DHCP: change flag of DHCP request to broadcast.\\n\");\n\t\t\t\t\t\t\t/* or BROADCAST flag */\n\t\t\t\t\t\t\tdhcph->flags |= htons(BROADCAST_FLAG);\n\t\t\t\t\t\t\t/* recalculate checksum */\n\t\t\t\t\t\t\tsum = ~(udph->check) & 0xffff;\n\t\t\t\t\t\t\tsum += dhcph->flags;\n\t\t\t\t\t\t\twhile (sum >> 16)\n\t\t\t\t\t\t\t\tsum = (sum & 0xffff) + (sum >> 16);\n\t\t\t\t\t\t\tudph->check = ~sum;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\n\nvoid *scdb_findEntry(_adapter *priv, unsigned char *macAddr,\n\t\t     unsigned char *ipAddr)\n{\n\tunsigned char networkAddr[MAX_NETWORK_ADDR_LEN];\n\tstruct nat25_network_db_entry *db;\n\tint hash;\n\t/* _irqL irqL; */\n\t/* _enter_critical_bh(&priv->br_ext_lock, &irqL); */\n\n\t__nat25_generate_ipv4_network_addr(networkAddr, (unsigned int *)ipAddr);\n\thash = __nat25_network_hash(networkAddr);\n\tdb = priv->nethash[hash];\n\twhile (db != NULL) {\n\t\tif (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) {\n\t\t\t/* _exit_critical_bh(&priv->br_ext_lock, &irqL); */\n\t\t\treturn (void *)db;\n\t\t}\n\n\t\tdb = db->next_hash;\n\t}\n\n\t/* _exit_critical_bh(&priv->br_ext_lock, &irqL); */\n\treturn NULL;\n}\n\n#endif /* CONFIG_BR_EXT */\n"
  },
  {
    "path": "core/rtw_bt_mp.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n\n#include <drv_types.h>\n#include <rtw_bt_mp.h>\n\n#if defined(CONFIG_RTL8723B)\n\t#include <rtl8723b_hal.h>\n#endif\n\n#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A)\nvoid MPh2c_timeout_handle(void *FunctionContext)\n{\n\tPADAPTER pAdapter;\n\tPMPT_CONTEXT pMptCtx;\n\n\n\tRTW_INFO(\"[MPT], MPh2c_timeout_handle\\n\");\n\n\tpAdapter = (PADAPTER)FunctionContext;\n\tpMptCtx = &pAdapter->mppriv.mpt_ctx;\n\n\tpMptCtx->bMPh2c_timeout = _TRUE;\n\n\tif ((_FALSE == pMptCtx->MptH2cRspEvent)\n\t    || ((_TRUE == pMptCtx->MptH2cRspEvent)\n\t\t&& (_FALSE == pMptCtx->MptBtC2hEvent)))\n\t\t_rtw_up_sema(&pMptCtx->MPh2c_Sema);\n}\n\nu32 WaitC2Hevent(PADAPTER pAdapter, u8 *C2H_event, u32 delay_time)\n{\n\tPMPT_CONTEXT\t\tpMptCtx = &(pAdapter->mppriv.mpt_ctx);\n\tpMptCtx->bMPh2c_timeout = _FALSE;\n\n\tif (pAdapter->registrypriv.mp_mode == 0) {\n\t\tRTW_INFO(\"[MPT], Error!! WaitC2Hevent mp_mode == 0!!\\n\");\n\t\treturn _FALSE;\n\t}\n\n\t_set_timer(&pMptCtx->MPh2c_timeout_timer, delay_time);\n\n\t_rtw_down_sema(&pMptCtx->MPh2c_Sema);\n\n\tif (pMptCtx->bMPh2c_timeout == _TRUE) {\n\t\t*C2H_event = _FALSE;\n\n\t\treturn _FALSE;\n\t}\n\n\t/* for safty, cancel timer here again */\n\t_cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);\n\n\treturn _TRUE;\n}\n\nBT_CTRL_STATUS\nmptbt_CheckC2hFrame(\n\tPADAPTER\t\tAdapter,\n\tPBT_H2C\t\t\tpH2c,\n\tPBT_EXT_C2H\t\tpExtC2h\n)\n{\n\tBT_CTRL_STATUS\tc2hStatus = BT_STATUS_C2H_SUCCESS;\n\n\t/* RTW_INFO(\"[MPT], MPT rsp C2H hex: %x %x %x  %x %x %x\\n\"), pExtC2h , pExtC2h+1 ,pExtC2h+2 ,pExtC2h+3 ,pExtC2h+4 ,pExtC2h+5); */\n\n\tRTW_INFO(\"[MPT], statusCode = 0x%x\\n\", pExtC2h->statusCode);\n\tRTW_INFO(\"[MPT], retLen = %d\\n\", pExtC2h->retLen);\n\tRTW_INFO(\"[MPT], opCodeVer : req/rsp=%d/%d\\n\", pH2c->opCodeVer, pExtC2h->opCodeVer);\n\tRTW_INFO(\"[MPT], reqNum : req/rsp=%d/%d\\n\", pH2c->reqNum, pExtC2h->reqNum);\n\tif (pExtC2h->reqNum != pH2c->reqNum) {\n\t\tc2hStatus = BT_STATUS_C2H_REQNUM_MISMATCH;\n\t\tRTW_INFO(\"[MPT], Error!! C2H reqNum Mismatch!!\\n\");\n\t} else if (pExtC2h->opCodeVer != pH2c->opCodeVer) {\n\t\tc2hStatus = BT_STATUS_OPCODE_L_VERSION_MISMATCH;\n\t\tRTW_INFO(\"[MPT], Error!! OPCode version L mismatch!!\\n\");\n\t}\n\n\treturn c2hStatus;\n}\n\nBT_CTRL_STATUS\nmptbt_SendH2c(\n\tPADAPTER\tAdapter,\n\tPBT_H2C\tpH2c,\n\tu16\t\th2cCmdLen\n)\n{\n\t/* KIRQL\t\t\t\tOldIrql = KeGetCurrentIrql(); */\n\tBT_CTRL_STATUS\th2cStatus = BT_STATUS_H2C_SUCCESS;\n\tPMPT_CONTEXT\t\tpMptCtx = &(Adapter->mppriv.mpt_ctx);\n\tu8\t\t\t\ti;\n\n\tRTW_INFO(\"[MPT], mptbt_SendH2c()=========>\\n\");\n\n\t/* PlatformResetEvent(&pMptCtx->MptH2cRspEvent); */\n\t/* PlatformResetEvent(&pMptCtx->MptBtC2hEvent); */\n\n\t/*\tif(OldIrql == PASSIVE_LEVEL)\n\t *\t{ */\n\t/* RTPRINT_DATA(FMPBT, FMPBT_H2C_CONTENT, (\"[MPT], MPT H2C hex:\\n\"), pH2c, h2cCmdLen); */\n\n\tfor (i = 0; i < BT_H2C_MAX_RETRY; i++) {\n\t\tRTW_INFO(\"[MPT], Send H2C command to wifi!!!\\n\");\n\n\t\tpMptCtx->MptH2cRspEvent = _FALSE;\n\t\tpMptCtx->MptBtC2hEvent = _FALSE;\n\n#if defined(CONFIG_RTL8723B)\n\t\trtl8723b_set_FwBtMpOper_cmd(Adapter, pH2c->opCode, pH2c->opCodeVer, pH2c->reqNum, pH2c->buf);\n#endif\n\t\tpMptCtx->h2cReqNum++;\n\t\tpMptCtx->h2cReqNum %= 16;\n\n\t\tif (WaitC2Hevent(Adapter, &pMptCtx->MptH2cRspEvent, 100)) {\n\t\t\tRTW_INFO(\"[MPT], Received WiFi MptH2cRspEvent!!!\\n\");\n\t\t\tif (WaitC2Hevent(Adapter, &pMptCtx->MptBtC2hEvent, 400)) {\n\t\t\t\tRTW_INFO(\"[MPT], Received MptBtC2hEvent!!!\\n\");\n\t\t\t\tbreak;\n\t\t\t} else {\n\t\t\t\tRTW_INFO(\"[MPT], Error!!BT MptBtC2hEvent timeout!!\\n\");\n\t\t\t\th2cStatus = BT_STATUS_H2C_BT_NO_RSP;\n\t\t\t}\n\t\t} else {\n\t\t\tRTW_INFO(\"[MPT], Error!!WiFi  MptH2cRspEvent timeout!!\\n\");\n\t\t\th2cStatus = BT_STATUS_H2C_TIMTOUT;\n\t\t}\n\t}\n\t/*\t}\n\t *\telse\n\t *\t{\n\t * \t\tRT_ASSERT(FALSE, (\"[MPT],  mptbt_SendH2c() can only run under PASSIVE_LEVEL!!\\n\"));\n\t *\t\th2cStatus = BT_STATUS_WRONG_LEVEL;\n\t *\t} */\n\n\tRTW_INFO(\"[MPT], mptbt_SendH2c()<=========\\n\");\n\treturn h2cStatus;\n}\n\n\n\nBT_CTRL_STATUS\nmptbt_CheckBtRspStatus(\n\tPADAPTER\t\t\tAdapter,\n\tPBT_EXT_C2H\t\t\tpExtC2h\n)\n{\n\tBT_CTRL_STATUS\tretStatus = BT_OP_STATUS_SUCCESS;\n\n\tswitch (pExtC2h->statusCode) {\n\tcase BT_OP_STATUS_SUCCESS:\n\t\tretStatus = BT_STATUS_BT_OP_SUCCESS;\n\t\tRTW_INFO(\"[MPT], BT status : BT_STATUS_SUCCESS\\n\");\n\t\tbreak;\n\tcase BT_OP_STATUS_VERSION_MISMATCH:\n\t\tretStatus = BT_STATUS_OPCODE_L_VERSION_MISMATCH;\n\t\tRTW_INFO(\"[MPT], BT status : BT_STATUS_OPCODE_L_VERSION_MISMATCH\\n\");\n\t\tbreak;\n\tcase BT_OP_STATUS_UNKNOWN_OPCODE:\n\t\tretStatus = BT_STATUS_UNKNOWN_OPCODE_L;\n\t\tRTW_INFO(\"[MPT], BT status : BT_STATUS_UNKNOWN_OPCODE_L\\n\");\n\t\tbreak;\n\tcase BT_OP_STATUS_ERROR_PARAMETER:\n\t\tretStatus = BT_STATUS_PARAMETER_FORMAT_ERROR_L;\n\t\tRTW_INFO(\"[MPT], BT status : BT_STATUS_PARAMETER_FORMAT_ERROR_L\\n\");\n\t\tbreak;\n\tdefault:\n\t\tretStatus = BT_STATUS_UNKNOWN_STATUS_L;\n\t\tRTW_INFO(\"[MPT], BT status : BT_STATUS_UNKNOWN_STATUS_L\\n\");\n\t\tbreak;\n\t}\n\n\treturn retStatus;\n}\n\n\n\nBT_CTRL_STATUS\nmptbt_BtFwOpCodeProcess(\n\tPADAPTER\t\tAdapter,\n\tu8\t\t\tbtFwOpCode,\n\tu8\t\t\topCodeVer,\n\tu8\t\t\t*pH2cPar,\n\tu8\t\t\th2cParaLen\n)\n{\n\tu8\t\t\t\tH2C_Parameter[6] = {0};\n\tPBT_H2C\t\t\t\tpH2c = (PBT_H2C)&H2C_Parameter[0];\n\tPMPT_CONTEXT\t\tpMptCtx = &(Adapter->mppriv.mpt_ctx);\n\tPBT_EXT_C2H\t\t\tpExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0];\n\tu16\t\t\t\tparaLen = 0, i;\n\tBT_CTRL_STATUS\th2cStatus = BT_STATUS_H2C_SUCCESS, c2hStatus = BT_STATUS_C2H_SUCCESS;\n\tBT_CTRL_STATUS\tretStatus = BT_STATUS_H2C_BT_NO_RSP;\n\n\tif (Adapter->registrypriv.mp_mode == 0) {\n\t\tRTW_INFO(\"[MPT], Error!! mptbt_BtFwOpCodeProces mp_mode == 0!!\\n\");\n\t\treturn _FALSE;\n\t}\n\n\tpH2c->opCode = btFwOpCode;\n\tpH2c->opCodeVer = opCodeVer;\n\tpH2c->reqNum = pMptCtx->h2cReqNum;\n\t/* PlatformMoveMemory(&pH2c->buf[0], pH2cPar, h2cParaLen); */\n\t/* _rtw_memcpy(&pH2c->buf[0], pH2cPar, h2cParaLen); */\n\t_rtw_memcpy(pH2c->buf, pH2cPar, h2cParaLen);\n\n\tRTW_INFO(\"[MPT], pH2c->opCode=%d\\n\", pH2c->opCode);\n\tRTW_INFO(\"[MPT], pH2c->opCodeVer=%d\\n\", pH2c->opCodeVer);\n\tRTW_INFO(\"[MPT], pH2c->reqNum=%d\\n\", pH2c->reqNum);\n\tRTW_INFO(\"[MPT], h2c parameter length=%d\\n\", h2cParaLen);\n\tfor (i = 0; i < h2cParaLen; i++)\n\t\tRTW_INFO(\"[MPT], parameter[%d]=0x%02x\\n\", i, pH2c->buf[i]);\n\n\th2cStatus = mptbt_SendH2c(Adapter, pH2c, h2cParaLen + 2);\n\tif (BT_STATUS_H2C_SUCCESS == h2cStatus) {\n\t\t/* if reach here, it means H2C get the correct c2h response, */\n\t\tc2hStatus = mptbt_CheckC2hFrame(Adapter, pH2c, pExtC2h);\n\t\tif (BT_STATUS_C2H_SUCCESS == c2hStatus)\n\t\t\tretStatus = mptbt_CheckBtRspStatus(Adapter, pExtC2h);\n\t\telse {\n\t\t\tRTW_INFO(\"[MPT], Error!! C2H failed for pH2c->opCode=%d\\n\", pH2c->opCode);\n\t\t\t/* check c2h status error, return error status code to upper layer. */\n\t\t\tretStatus = c2hStatus;\n\t\t}\n\t} else {\n\t\tRTW_INFO(\"[MPT], Error!! H2C failed for pH2c->opCode=%d\\n\", pH2c->opCode);\n\t\t/* check h2c status error, return error status code to upper layer. */\n\t\tretStatus = h2cStatus;\n\t}\n\n\treturn retStatus;\n}\n\n\n\n\nu16\nmptbt_BtReady(\n\tPADAPTER\t\tAdapter,\n\tPBT_REQ_CMD\tpBtReq,\n\tPBT_RSP_CMD\tpBtRsp\n)\n{\n\tu8\t\t\t\th2cParaBuf[6] = {0};\n\tu8\t\t\t\th2cParaLen = 0;\n\tu16\t\t\t\tparaLen = 0;\n\tu8\t\t\t\tretStatus = BT_STATUS_BT_OP_SUCCESS;\n\tu8\t\t\t\tbtOpcode;\n\tu8\t\t\t\tbtOpcodeVer = 0;\n\tPMPT_CONTEXT\t\tpMptCtx = &(Adapter->mppriv.mpt_ctx);\n\tPBT_EXT_C2H\t\t\tpExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0];\n\tu8\t\t\t\ti;\n\tu8\t\t\t\tbtFwVer = 0, bdAddr[6] = {0};\n\tu16\t\t\t\tbtRealFwVer = 0;\n\tu16\t\t\t\t*pu2Tmp = NULL;\n\n\t/*  */\n\t/* check upper layer parameters */\n\t/*  */\n\n\t/* 1. check upper layer opcode version */\n\tif (pBtReq->opCodeVer != 1) {\n\t\tRTW_INFO(\"[MPT], Error!! Upper OP code version not match!!!\\n\");\n\t\tpBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;\n\t\treturn paraLen;\n\t}\n\n\tpBtRsp->pParamStart[0] = MP_BT_NOT_READY;\n\tparaLen = 10;\n\t/*  */\n\t/* execute lower layer opcodes */\n\t/*  */\n\n\t/* Get BT FW version */\n\t/* fill h2c parameters */\n\tbtOpcode = BT_LO_OP_GET_BT_VERSION;\n\t/* execute h2c and check respond c2h from bt fw is correct or not */\n\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t/* ckeck bt return status. */\n\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\treturn paraLen;\n\t} else {\n\t\tpu2Tmp = (u16 *)&pExtC2h->buf[0];\n\t\tbtRealFwVer = *pu2Tmp;\n\t\tbtFwVer = pExtC2h->buf[1];\n\t\tRTW_INFO(\"[MPT], btRealFwVer=0x%x, btFwVer=0x%x\\n\", btRealFwVer, btFwVer);\n\t}\n\n\t/* Get BD Address */\n\t/* fill h2c parameters */\n\tbtOpcode = BT_LO_OP_GET_BD_ADDR_L;\n\t/* execute h2c and check respond c2h from bt fw is correct or not */\n\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t/* ckeck bt return status. */\n\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\treturn paraLen;\n\t} else {\n\t\tbdAddr[5] = pExtC2h->buf[0];\n\t\tbdAddr[4] = pExtC2h->buf[1];\n\t\tbdAddr[3] = pExtC2h->buf[2];\n\t}\n\n\t/* fill h2c parameters */\n\tbtOpcode = BT_LO_OP_GET_BD_ADDR_H;\n\t/* execute h2c and check respond c2h from bt fw is correct or not */\n\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t/* ckeck bt return status. */\n\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\treturn paraLen;\n\t} else {\n\t\tbdAddr[2] = pExtC2h->buf[0];\n\t\tbdAddr[1] = pExtC2h->buf[1];\n\t\tbdAddr[0] = pExtC2h->buf[2];\n\t}\n\tRTW_INFO(\"[MPT], Local BDAddr:\");\n\tfor (i = 0; i < 6; i++)\n\t\tRTW_INFO(\" 0x%x \", bdAddr[i]);\n\tpBtRsp->status = BT_STATUS_SUCCESS;\n\tpBtRsp->pParamStart[0] = MP_BT_READY;\n\tpu2Tmp = (u16 *)&pBtRsp->pParamStart[1];\n\t*pu2Tmp = btRealFwVer;\n\tpBtRsp->pParamStart[3] = btFwVer;\n\tfor (i = 0; i < 6; i++)\n\t\tpBtRsp->pParamStart[4 + i] = bdAddr[5 - i];\n\n\treturn paraLen;\n}\n\nvoid mptbt_close_WiFiRF(PADAPTER Adapter)\n{\n\tphy_set_bb_reg(Adapter, 0x824, 0xF, 0x0);\n\tphy_set_bb_reg(Adapter, 0x824, 0x700000, 0x0);\n\tphy_set_rf_reg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x0);\n}\n\nvoid mptbt_open_WiFiRF(PADAPTER\tAdapter)\n{\n\tphy_set_bb_reg(Adapter, 0x824, 0x700000, 0x3);\n\tphy_set_bb_reg(Adapter, 0x824, 0xF, 0x2);\n\tphy_set_rf_reg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x3);\n}\n\nu32 mptbt_switch_RF(PADAPTER\tAdapter, u8\tEnter)\n{\n\tu16\ttmp_2byte = 0;\n\n\t/* Enter test mode */\n\tif (Enter) {\n\t\t/* 1>. close WiFi RF */\n\t\tmptbt_close_WiFiRF(Adapter);\n\n\t\t/* 2>. change ant switch to BT */\n\t\ttmp_2byte = rtw_read16(Adapter, 0x860);\n\t\ttmp_2byte = tmp_2byte | BIT(9);\n\t\ttmp_2byte = tmp_2byte & (~BIT(8));\n\t\trtw_write16(Adapter, 0x860, tmp_2byte);\n\t\trtw_write16(Adapter, 0x870, 0x300);\n\t} else {\n\t\t/* 1>. Open WiFi RF */\n\t\tmptbt_open_WiFiRF(Adapter);\n\n\t\t/* 2>. change ant switch back */\n\t\ttmp_2byte = rtw_read16(Adapter, 0x860);\n\t\ttmp_2byte = tmp_2byte | BIT(8);\n\t\ttmp_2byte = tmp_2byte & (~BIT(9));\n\t\trtw_write16(Adapter, 0x860, tmp_2byte);\n\t\trtw_write16(Adapter, 0x870, 0x300);\n\t}\n\n\treturn 0;\n}\n\nu16\nmptbt_BtSetMode(\n\tPADAPTER\t\tAdapter,\n\tPBT_REQ_CMD\tpBtReq,\n\tPBT_RSP_CMD\tpBtRsp\n)\n{\n\tu8\t\t\t\th2cParaBuf[6] = {0};\n\tu8\t\t\t\th2cParaLen = 0;\n\tu16\t\t\t\tparaLen = 0;\n\tu8\t\t\t\tretStatus = BT_STATUS_BT_OP_SUCCESS;\n\tu8\t\t\t\tbtOpcode;\n\tu8\t\t\t\tbtOpcodeVer = 0;\n\tu8\t\t\t\tbtModeToSet = 0;\n\n\t/*  */\n\t/* check upper layer parameters */\n\t/*  */\n\t/* 1. check upper layer opcode version */\n\tif (pBtReq->opCodeVer != 1) {\n\t\tRTW_INFO(\"[MPT], Error!! Upper OP code version not match!!!\\n\");\n\t\tpBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;\n\t\treturn paraLen;\n\t}\n\t/* 2. check upper layer parameter length */\n\tif (1 == pBtReq->paraLength) {\n\t\tbtModeToSet = pBtReq->pParamStart[0];\n\t\tRTW_INFO(\"[MPT], BtTestMode=%d\\n\", btModeToSet);\n\t} else {\n\t\tRTW_INFO(\"[MPT], Error!! wrong parameter length=%d (should be 1)\\n\", pBtReq->paraLength);\n\t\tpBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;\n\t\treturn paraLen;\n\t}\n\n\t/*  */\n\t/* execute lower layer opcodes */\n\t/*  */\n\n\t/* 1. fill h2c parameters\t */\n\t/* check bt mode */\n\tbtOpcode = BT_LO_OP_SET_BT_MODE;\n\tif (btModeToSet >= MP_BT_MODE_MAX) {\n\t\tpBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\treturn paraLen;\n\t} else {\n\t\tmptbt_switch_RF(Adapter, 1);\n\n\t\th2cParaBuf[0] = btModeToSet;\n\t\th2cParaLen = 1;\n\t\t/* 2. execute h2c and check respond c2h from bt fw is correct or not */\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t}\n\n\t/* 3. construct respond status code and data. */\n\tif (BT_STATUS_BT_OP_SUCCESS == retStatus)\n\t\tpBtRsp->status = BT_STATUS_SUCCESS;\n\telse {\n\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t}\n\n\treturn paraLen;\n}\n\n\nvoid\nMPTBT_FwC2hBtMpCtrl(\n\tPADAPTER\tAdapter,\n\tu8\t\t*tmpBuf,\n\tu8\t\tlength\n)\n{\n\tu32 i;\n\tPMPT_CONTEXT\tpMptCtx = &(Adapter->mppriv.mpt_ctx);\n\tPBT_EXT_C2H pExtC2h = (PBT_EXT_C2H)tmpBuf;\n\n\tif (GET_HAL_DATA(Adapter)->bBTFWReady == _FALSE || Adapter->registrypriv.mp_mode == 0) {\n\t\t/* RTW_INFO(\"Ignore C2H BT MP Info since not in MP mode\\n\"); */\n\t\treturn;\n\t}\n\tif (length > 32 || length < 3) {\n\t\tRTW_INFO(\"\\n [MPT], pExtC2h->buf hex: length=%d > 32 || < 3\\n\", length);\n\t\treturn;\n\t}\n\n\t/* cancel_timeout for h2c handle */\n\t_cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);\n\n\tfor (i = 0; i < length; i++)\n\t\tRTW_INFO(\"[MPT], %s, buf[%d]=0x%02x \", __FUNCTION__, i, tmpBuf[i]);\n\tRTW_INFO(\"[MPT], pExtC2h->extendId=0x%x\\n\", pExtC2h->extendId);\n\n\tswitch (pExtC2h->extendId) {\n\tcase EXT_C2H_WIFI_FW_ACTIVE_RSP:\n\t\tRTW_INFO(\"[MPT], EXT_C2H_WIFI_FW_ACTIVE_RSP\\n\");\n#if 0\n\t\tRTW_INFO(\"[MPT], pExtC2h->buf hex:\\n\");\n\t\tfor (i = 0; i < (length - 3); i++)\n\t\t\tRTW_INFO(\" 0x%x \", pExtC2h->buf[i]);\n#endif\n\t\tif ((_FALSE == pMptCtx->bMPh2c_timeout)\n\t\t    && (_FALSE == pMptCtx->MptH2cRspEvent)) {\n\t\t\tpMptCtx->MptH2cRspEvent = _TRUE;\n\t\t\t_rtw_up_sema(&pMptCtx->MPh2c_Sema);\n\t\t}\n\t\tbreak;\n\n\tcase EXT_C2H_TRIG_BY_BT_FW:\n\t\tRTW_INFO(\"[MPT], EXT_C2H_TRIG_BY_BT_FW\\n\");\n\t\t_rtw_memcpy(&pMptCtx->c2hBuf[0], tmpBuf, length);\n\t\tRTW_INFO(\"[MPT], pExtC2h->statusCode=0x%x\\n\", pExtC2h->statusCode);\n\t\tRTW_INFO(\"[MPT], pExtC2h->retLen=0x%x\\n\", pExtC2h->retLen);\n\t\tRTW_INFO(\"[MPT], pExtC2h->opCodeVer=0x%x\\n\", pExtC2h->opCodeVer);\n\t\tRTW_INFO(\"[MPT], pExtC2h->reqNum=0x%x\\n\", pExtC2h->reqNum);\n\t\tfor (i = 0; i < (length - 3); i++)\n\t\t\tRTW_INFO(\"[MPT], pExtC2h->buf[%d]=0x%02x\\n\", i, pExtC2h->buf[i]);\n\n\t\tif ((_FALSE == pMptCtx->bMPh2c_timeout)\n\t\t    && (_TRUE == pMptCtx->MptH2cRspEvent)\n\t\t    && (_FALSE == pMptCtx->MptBtC2hEvent)) {\n\t\t\tpMptCtx->MptBtC2hEvent = _TRUE;\n\t\t\t_rtw_up_sema(&pMptCtx->MPh2c_Sema);\n\t\t}\n\t\tbreak;\n\n\tdefault:\n\t\tRTW_INFO(\"[MPT], EXT_C2H Target not found,pExtC2h->extendId =%d ,pExtC2h->reqNum=%d\\n\", pExtC2h->extendId, pExtC2h->reqNum);\n\t\tbreak;\n\t}\n\n\n\n}\n\n\nu16\nmptbt_BtGetGeneral(\n\t\tPADAPTER\t\tAdapter,\n\t\tPBT_REQ_CMD\tpBtReq,\n\t\tPBT_RSP_CMD\tpBtRsp\n)\n{\n\tPMPT_CONTEXT\t\tpMptCtx = &(Adapter->mppriv.mpt_ctx);\n\tPBT_EXT_C2H\t\tpExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0];\n\tu8\t\t\t\th2cParaBuf[6] = {0};\n\tu8\t\t\t\th2cParaLen = 0;\n\tu16\t\t\t\tparaLen = 0;\n\tu8\t\t\t\tretStatus = BT_STATUS_BT_OP_SUCCESS;\n\tu8\t\t\t\tbtOpcode, bdAddr[6] = {0};\n\tu8\t\t\t\tbtOpcodeVer = 0;\n\tu8\t\t\t\tgetType = 0, i;\n\tu16\t\t\t\tgetParaLen = 0, validParaLen = 0;\n\tu8\t\t\t\tregType = 0, reportType = 0;\n\tu32\t\t\t\tregAddr = 0, regValue = 0;\n\tu32 \t\t\t\t*pu4Tmp;\n\tu16 \t\t\t\t*pu2Tmp;\n\tu8 \t\t\t\t*pu1Tmp;\n\n\t/*  */\n\t/* check upper layer parameters */\n\t/*  */\n\n\t/* check upper layer opcode version */\n\tif (pBtReq->opCodeVer != 1) {\n\t\tRTW_INFO(\"[MPT], Error!! Upper OP code version not match!!!\\n\");\n\t\tpBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;\n\t\treturn paraLen;\n\t}\n\t/* check upper layer parameter length */\n\tif (pBtReq->paraLength < 1) {\n\t\tRTW_INFO(\"[MPT], Error!! wrong parameter length=%d (should larger than 1)\\n\", pBtReq->paraLength);\n\t\tpBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;\n\t\treturn paraLen;\n\t}\n\tgetParaLen = pBtReq->paraLength - 1;\n\tgetType = pBtReq->pParamStart[0];\n\n\tRTW_INFO(\"[MPT], getType=%d, getParaLen=%d\\n\", getType, getParaLen);\n\n\t/* check parameter first */\n\tswitch (getType) {\n\tcase BT_GGET_REG:\n\t\tRTW_INFO(\"[MPT], [BT_GGET_REG]\\n\");\n\t\tvalidParaLen = 5;\n\t\tif (getParaLen == validParaLen) {\n\t\t\tbtOpcode = BT_LO_OP_READ_REG;\n\t\t\tregType = pBtReq->pParamStart[1];\n\t\t\tpu4Tmp = (u32 *)&pBtReq->pParamStart[2];\n\t\t\tregAddr = *pu4Tmp;\n\t\t\tRTW_INFO(\"[MPT], BT_GGET_REG regType=0x%02x, regAddr=0x%08x!!\\n\",\n\t\t\t\t regType, regAddr);\n\t\t\tif (regType >= BT_REG_MAX) {\n\t\t\t\tpBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\t\t\treturn paraLen;\n\t\t\t} else {\n\t\t\t\tif (((BT_REG_RF == regType) && (regAddr > 0x7f)) ||\n\t\t\t\t    ((BT_REG_MODEM == regType) && (regAddr > 0x1ff)) ||\n\t\t\t\t    ((BT_REG_BLUEWIZE == regType) && (regAddr > 0xfff)) ||\n\t\t\t\t    ((BT_REG_VENDOR == regType) && (regAddr > 0xfff)) ||\n\t\t\t\t    ((BT_REG_LE == regType) && (regAddr > 0xfff))) {\n\t\t\t\t\tpBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\t\t\t\treturn paraLen;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tcase BT_GGET_STATUS:\n\t\tRTW_INFO(\"[MPT], [BT_GGET_STATUS]\\n\");\n\t\tvalidParaLen = 0;\n\t\tbreak;\n\tcase BT_GGET_REPORT:\n\t\tRTW_INFO(\"[MPT], [BT_GGET_REPORT]\\n\");\n\t\tvalidParaLen = 1;\n\t\tif (getParaLen == validParaLen) {\n\t\t\treportType = pBtReq->pParamStart[1];\n\t\t\tRTW_INFO(\"[MPT], BT_GGET_REPORT reportType=0x%x!!\\n\", reportType);\n\t\t\tif (reportType >= BT_REPORT_MAX) {\n\t\t\t\tpBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\t\t\treturn paraLen;\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tdefault: {\n\t\tRTW_INFO(\"[MPT], Error!! getType=%d, out of range\\n\", getType);\n\t\tpBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\treturn paraLen;\n\t}\n\tbreak;\n\t}\n\tif (getParaLen != validParaLen) {\n\t\tRTW_INFO(\"[MPT], Error!! wrong parameter length=%d for BT_GET_GEN_CMD cmd id=0x%x, paraLen should=0x%x\\n\",\n\t\t\t getParaLen, getType, validParaLen);\n\t\tpBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;\n\t\treturn paraLen;\n\t}\n\n\t/*  */\n\t/* execute lower layer opcodes */\n\t/*  */\n\tif (BT_GGET_REG == getType) {\n\t\t/* fill h2c parameters */\n\t\t/* here we should write reg value first then write the address, adviced by Austin */\n\t\tbtOpcode = BT_LO_OP_READ_REG;\n\t\th2cParaBuf[0] = regType;\n\t\th2cParaBuf[1] = pBtReq->pParamStart[2];\n\t\th2cParaBuf[2] = pBtReq->pParamStart[3];\n\t\th2cParaLen = 3;\n\t\t/* execute h2c and check respond c2h from bt fw is correct or not */\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t/* construct respond status code and data. */\n\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\treturn paraLen;\n\t\t}\n\n\t\tpu2Tmp = (u16 *)&pExtC2h->buf[0];\n\t\tregValue = *pu2Tmp;\n\t\tRTW_INFO(\"[MPT], read reg regType=0x%02x, regAddr=0x%08x, regValue=0x%04x\\n\",\n\t\t\t regType, regAddr, regValue);\n\n\t\tpu4Tmp = (u32 *)&pBtRsp->pParamStart[0];\n\t\t*pu4Tmp = regValue;\n\t\tparaLen = 4;\n\t} else if (BT_GGET_STATUS == getType) {\n\t\tbtOpcode = BT_LO_OP_GET_BT_STATUS;\n\t\th2cParaLen = 0;\n\t\t/* execute h2c and check respond c2h from bt fw is correct or not */\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t/* construct respond status code and data. */\n\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\treturn paraLen;\n\t\t}\n\n\t\tpBtRsp->pParamStart[0] = pExtC2h->buf[0];\n\t\tpBtRsp->pParamStart[1] = pExtC2h->buf[1];\n\t\tRTW_INFO(\"[MPT], read bt status, testMode=0x%x, testStatus=0x%x\\n\",\n\t\t\t pBtRsp->pParamStart[0], pBtRsp->pParamStart[1]);\n\t\tparaLen = 2;\n\t} else if (BT_GGET_REPORT == getType) {\n\t\tswitch (reportType) {\n\t\tcase BT_REPORT_RX_PACKET_CNT: {\n\t\t\tRTW_INFO(\"[MPT], [Rx Packet Counts]\\n\");\n\t\t\tbtOpcode = BT_LO_OP_GET_RX_PKT_CNT_L;\n\t\t\th2cParaLen = 0;\n\t\t\t/* execute h2c and check respond c2h from bt fw is correct or not */\n\t\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t\t/* construct respond status code and data. */\n\t\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\t\treturn paraLen;\n\t\t\t}\n\t\t\tpBtRsp->pParamStart[0] = pExtC2h->buf[0];\n\t\t\tpBtRsp->pParamStart[1] = pExtC2h->buf[1];\n\n\t\t\tbtOpcode = BT_LO_OP_GET_RX_PKT_CNT_H;\n\t\t\th2cParaLen = 0;\n\t\t\t/* execute h2c and check respond c2h from bt fw is correct or not */\n\t\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t\t/* construct respond status code and data. */\n\t\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\t\treturn paraLen;\n\t\t\t}\n\t\t\tpBtRsp->pParamStart[2] = pExtC2h->buf[0];\n\t\t\tpBtRsp->pParamStart[3] = pExtC2h->buf[1];\n\t\t\tparaLen = 4;\n\t\t}\n\t\tbreak;\n\t\tcase BT_REPORT_RX_ERROR_BITS: {\n\t\t\tRTW_INFO(\"[MPT], [Rx Error Bits]\\n\");\n\t\t\tbtOpcode = BT_LO_OP_GET_RX_ERROR_BITS_L;\n\t\t\th2cParaLen = 0;\n\t\t\t/* execute h2c and check respond c2h from bt fw is correct or not */\n\t\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t\t/* construct respond status code and data. */\n\t\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\t\treturn paraLen;\n\t\t\t}\n\t\t\tpBtRsp->pParamStart[0] = pExtC2h->buf[0];\n\t\t\tpBtRsp->pParamStart[1] = pExtC2h->buf[1];\n\n\t\t\tbtOpcode = BT_LO_OP_GET_RX_ERROR_BITS_H;\n\t\t\th2cParaLen = 0;\n\t\t\t/* execute h2c and check respond c2h from bt fw is correct or not */\n\t\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t\t/* construct respond status code and data. */\n\t\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\t\treturn paraLen;\n\t\t\t}\n\t\t\tpBtRsp->pParamStart[2] = pExtC2h->buf[0];\n\t\t\tpBtRsp->pParamStart[3] = pExtC2h->buf[1];\n\t\t\tparaLen = 4;\n\t\t}\n\t\tbreak;\n\t\tcase BT_REPORT_RSSI: {\n\t\t\tRTW_INFO(\"[MPT], [RSSI]\\n\");\n\t\t\tbtOpcode = BT_LO_OP_GET_RSSI;\n\t\t\th2cParaLen = 0;\n\t\t\t/* execute h2c and check respond c2h from bt fw is correct or not */\n\t\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t\t/* construct respond status code and data. */\n\t\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\t\treturn paraLen;\n\t\t\t}\n\t\t\tpBtRsp->pParamStart[0] = pExtC2h->buf[0];\n\t\t\tpBtRsp->pParamStart[1] = pExtC2h->buf[1];\n\t\t\tparaLen = 2;\n\t\t}\n\t\tbreak;\n\t\tcase BT_REPORT_CFO_HDR_QUALITY: {\n\t\t\tRTW_INFO(\"[MPT], [CFO & Header Quality]\\n\");\n\t\t\tbtOpcode = BT_LO_OP_GET_CFO_HDR_QUALITY_L;\n\t\t\th2cParaLen = 0;\n\t\t\t/* execute h2c and check respond c2h from bt fw is correct or not */\n\t\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t\t/* construct respond status code and data. */\n\t\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\t\treturn paraLen;\n\t\t\t}\n\t\t\tpBtRsp->pParamStart[0] = pExtC2h->buf[0];\n\t\t\tpBtRsp->pParamStart[1] = pExtC2h->buf[1];\n\n\t\t\tbtOpcode = BT_LO_OP_GET_CFO_HDR_QUALITY_H;\n\t\t\th2cParaLen = 0;\n\t\t\t/* execute h2c and check respond c2h from bt fw is correct or not */\n\t\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t\t/* construct respond status code and data. */\n\t\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\t\treturn paraLen;\n\t\t\t}\n\t\t\tpBtRsp->pParamStart[2] = pExtC2h->buf[0];\n\t\t\tpBtRsp->pParamStart[3] = pExtC2h->buf[1];\n\t\t\tparaLen = 4;\n\t\t}\n\t\tbreak;\n\t\tcase BT_REPORT_CONNECT_TARGET_BD_ADDR: {\n\t\t\tRTW_INFO(\"[MPT], [Connected Target BD ADDR]\\n\");\n\t\t\tbtOpcode = BT_LO_OP_GET_TARGET_BD_ADDR_L;\n\t\t\th2cParaLen = 0;\n\t\t\t/* execute h2c and check respond c2h from bt fw is correct or not */\n\t\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t\t/* construct respond status code and data. */\n\t\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\t\treturn paraLen;\n\t\t\t}\n\t\t\tbdAddr[5] = pExtC2h->buf[0];\n\t\t\tbdAddr[4] = pExtC2h->buf[1];\n\t\t\tbdAddr[3] = pExtC2h->buf[2];\n\n\t\t\tbtOpcode = BT_LO_OP_GET_TARGET_BD_ADDR_H;\n\t\t\th2cParaLen = 0;\n\t\t\t/* execute h2c and check respond c2h from bt fw is correct or not */\n\t\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t\t/* construct respond status code and data. */\n\t\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\t\treturn paraLen;\n\t\t\t}\n\t\t\tbdAddr[2] = pExtC2h->buf[0];\n\t\t\tbdAddr[1] = pExtC2h->buf[1];\n\t\t\tbdAddr[0] = pExtC2h->buf[2];\n\n\t\t\tRTW_INFO(\"[MPT], Connected Target BDAddr:%s\", bdAddr);\n\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\tpBtRsp->pParamStart[i] = bdAddr[5 - i];\n\t\t\tparaLen = 6;\n\t\t}\n\t\tbreak;\n\t\tdefault:\n\t\t\tpBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\t\treturn paraLen;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tpBtRsp->status = BT_STATUS_SUCCESS;\n\treturn paraLen;\n}\n\n\n\nu16\nmptbt_BtSetGeneral(\n\t\tPADAPTER\t\tAdapter,\n\t\tPBT_REQ_CMD\tpBtReq,\n\t\tPBT_RSP_CMD\tpBtRsp\n)\n{\n\tu8\t\t\t\th2cParaBuf[6] = {0};\n\tu8\t\t\t\th2cParaLen = 0;\n\tu16\t\t\t\tparaLen = 0;\n\tu8\t\t\t\tretStatus = BT_STATUS_BT_OP_SUCCESS;\n\tu8\t\t\t\tbtOpcode;\n\tu8\t\t\t\tbtOpcodeVer = 0;\n\tu8\t\t\t\tsetType = 0;\n\tu16\t\t\t\tsetParaLen = 0, validParaLen = 0;\n\tu8\t\t\t\tregType = 0, bdAddr[6] = {0}, calVal = 0;\n\tu32\t\t\t\tregAddr = 0, regValue = 0;\n\tu32 \t\t\t\t*pu4Tmp;\n\tu16 \t\t\t\t*pu2Tmp;\n\tu8 \t\t\t\t*pu1Tmp;\n\n\t/*  */\n\t/* check upper layer parameters */\n\t/*  */\n\n\t/* check upper layer opcode version */\n\tif (pBtReq->opCodeVer != 1) {\n\t\tRTW_INFO(\"[MPT], Error!! Upper OP code version not match!!!\\n\");\n\t\tpBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;\n\t\treturn paraLen;\n\t}\n\t/* check upper layer parameter length */\n\tif (pBtReq->paraLength < 1) {\n\t\tRTW_INFO(\"[MPT], Error!! wrong parameter length=%d (should larger than 1)\\n\", pBtReq->paraLength);\n\t\tpBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;\n\t\treturn paraLen;\n\t}\n\tsetParaLen = pBtReq->paraLength - 1;\n\tsetType = pBtReq->pParamStart[0];\n\n\tRTW_INFO(\"[MPT], setType=%d, setParaLen=%d\\n\", setType, setParaLen);\n\n\t/* check parameter first */\n\tswitch (setType) {\n\tcase BT_GSET_REG:\n\t\tRTW_INFO(\"[MPT], [BT_GSET_REG]\\n\");\n\t\tvalidParaLen = 9;\n\t\tif (setParaLen == validParaLen) {\n\t\t\tbtOpcode = BT_LO_OP_WRITE_REG_VALUE;\n\t\t\tregType = pBtReq->pParamStart[1];\n\t\t\tpu4Tmp = (u32 *)&pBtReq->pParamStart[2];\n\t\t\tregAddr = *pu4Tmp;\n\t\t\tpu4Tmp = (u32 *)&pBtReq->pParamStart[6];\n\t\t\tregValue = *pu4Tmp;\n\t\t\tRTW_INFO(\"[MPT], BT_GSET_REG regType=0x%x, regAddr=0x%x, regValue=0x%x!!\\n\",\n\t\t\t\t regType, regAddr, regValue);\n\t\t\tif (regType >= BT_REG_MAX) {\n\t\t\t\tpBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\t\t\treturn paraLen;\n\t\t\t} else {\n\t\t\t\tif (((BT_REG_RF == regType) && (regAddr > 0x7f)) ||\n\t\t\t\t    ((BT_REG_MODEM == regType) && (regAddr > 0x1ff)) ||\n\t\t\t\t    ((BT_REG_BLUEWIZE == regType) && (regAddr > 0xfff)) ||\n\t\t\t\t    ((BT_REG_VENDOR == regType) && (regAddr > 0xfff)) ||\n\t\t\t\t    ((BT_REG_LE == regType) && (regAddr > 0xfff))) {\n\t\t\t\t\tpBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\t\t\t\treturn paraLen;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tcase BT_GSET_RESET:\n\t\tRTW_INFO(\"[MPT], [BT_GSET_RESET]\\n\");\n\t\tvalidParaLen = 0;\n\t\tbreak;\n\tcase BT_GSET_TARGET_BD_ADDR:\n\t\tRTW_INFO(\"[MPT], [BT_GSET_TARGET_BD_ADDR]\\n\");\n\t\tvalidParaLen = 6;\n\t\tif (setParaLen == validParaLen) {\n\t\t\tbtOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_H;\n\t\t\tif ((pBtReq->pParamStart[1] == 0) &&\n\t\t\t    (pBtReq->pParamStart[2] == 0) &&\n\t\t\t    (pBtReq->pParamStart[3] == 0) &&\n\t\t\t    (pBtReq->pParamStart[4] == 0) &&\n\t\t\t    (pBtReq->pParamStart[5] == 0) &&\n\t\t\t    (pBtReq->pParamStart[6] == 0)) {\n\t\t\t\tRTW_INFO(\"[MPT], Error!! targetBDAddr=all zero\\n\");\n\t\t\t\tpBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\t\t\treturn paraLen;\n\t\t\t}\n\t\t\tif ((pBtReq->pParamStart[1] == 0xff) &&\n\t\t\t    (pBtReq->pParamStart[2] == 0xff) &&\n\t\t\t    (pBtReq->pParamStart[3] == 0xff) &&\n\t\t\t    (pBtReq->pParamStart[4] == 0xff) &&\n\t\t\t    (pBtReq->pParamStart[5] == 0xff) &&\n\t\t\t    (pBtReq->pParamStart[6] == 0xff)) {\n\t\t\t\tRTW_INFO(\"[MPT], Error!! targetBDAddr=all 0xf\\n\");\n\t\t\t\tpBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\t\t\treturn paraLen;\n\t\t\t}\n\t\t\tbdAddr[0] = pBtReq->pParamStart[6];\n\t\t\tbdAddr[1] = pBtReq->pParamStart[5];\n\t\t\tbdAddr[2] = pBtReq->pParamStart[4];\n\t\t\tbdAddr[3] = pBtReq->pParamStart[3];\n\t\t\tbdAddr[4] = pBtReq->pParamStart[2];\n\t\t\tbdAddr[5] = pBtReq->pParamStart[1];\n\t\t\tRTW_INFO(\"[MPT], target BDAddr:%x,%x,%x,%x,%x,%x\\n\",\n\t\t\t\tbdAddr[0], bdAddr[1], bdAddr[2], bdAddr[3], bdAddr[4], bdAddr[5]);\n\t\t}\n\t\tbreak;\n\tcase BT_GSET_TX_PWR_FINETUNE:\n\t\tRTW_INFO(\"[MPT], [BT_GSET_TX_PWR_FINETUNE]\\n\");\n\t\tvalidParaLen = 1;\n\t\tif (setParaLen == validParaLen) {\n\t\t\tbtOpcode = BT_LO_OP_SET_TX_POWER_CALIBRATION;\n\t\t\tcalVal = pBtReq->pParamStart[1];\n\t\t\tif ((calVal < 1) || (calVal > 9)) {\n\t\t\t\tpBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\t\t\treturn paraLen;\n\t\t\t}\n\t\t\tRTW_INFO(\"[MPT], calVal=%d\\n\", calVal);\n\t\t}\n\t\tbreak;\n\tcase BT_SET_TRACKING_INTERVAL:\n\t\tRTW_INFO(\"[MPT], [BT_SET_TRACKING_INTERVAL] setParaLen =%d\\n\", setParaLen);\n\n\t\tvalidParaLen = 1;\n\t\tif (setParaLen == validParaLen)\n\t\t\tcalVal = pBtReq->pParamStart[1];\n\t\tbreak;\n\tcase BT_SET_THERMAL_METER:\n\t\tRTW_INFO(\"[MPT], [BT_SET_THERMAL_METER] setParaLen =%d\\n\", setParaLen);\n\t\tvalidParaLen = 1;\n\t\tif (setParaLen == validParaLen)\n\t\t\tcalVal = pBtReq->pParamStart[1];\n\t\tbreak;\n\tcase BT_ENABLE_CFO_TRACKING:\n\t\tRTW_INFO(\"[MPT], [BT_ENABLE_CFO_TRACKING] setParaLen =%d\\n\", setParaLen);\n\t\tvalidParaLen = 1;\n\t\tif (setParaLen == validParaLen)\n\t\t\tcalVal = pBtReq->pParamStart[1];\n\t\tbreak;\n\tcase BT_GSET_UPDATE_BT_PATCH:\n\n\t\tbreak;\n\tdefault: {\n\t\tRTW_INFO(\"[MPT], Error!! setType=%d, out of range\\n\", setType);\n\t\tpBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\treturn paraLen;\n\t}\n\tbreak;\n\t}\n\tif (setParaLen != validParaLen) {\n\t\tRTW_INFO(\"[MPT], Error!! wrong parameter length=%d for BT_SET_GEN_CMD cmd id=0x%x, paraLen should=0x%x\\n\",\n\t\t\t setParaLen, setType, validParaLen);\n\t\tpBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;\n\t\treturn paraLen;\n\t}\n\n\t/*  */\n\t/* execute lower layer opcodes */\n\t/*  */\n\tif (BT_GSET_REG == setType) {\n\t\t/* fill h2c parameters */\n\t\t/* here we should write reg value first then write the address, adviced by Austin */\n\t\tbtOpcode = BT_LO_OP_WRITE_REG_VALUE;\n\t\th2cParaBuf[0] = pBtReq->pParamStart[6];\n\t\th2cParaBuf[1] = pBtReq->pParamStart[7];\n\t\th2cParaBuf[2] = pBtReq->pParamStart[8];\n\t\th2cParaLen = 3;\n\t\t/* execute h2c and check respond c2h from bt fw is correct or not */\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t/* construct respond status code and data. */\n\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\treturn paraLen;\n\t\t}\n\n\t\t/* write reg address */\n\t\tbtOpcode = BT_LO_OP_WRITE_REG_ADDR;\n\t\th2cParaBuf[0] = regType;\n\t\th2cParaBuf[1] = pBtReq->pParamStart[2];\n\t\th2cParaBuf[2] = pBtReq->pParamStart[3];\n\t\th2cParaLen = 3;\n\t\t/* execute h2c and check respond c2h from bt fw is correct or not */\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t/* construct respond status code and data. */\n\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\treturn paraLen;\n\t\t}\n\t} else if (BT_GSET_RESET == setType) {\n\t\tbtOpcode = BT_LO_OP_RESET;\n\t\th2cParaLen = 0;\n\t\t/* execute h2c and check respond c2h from bt fw is correct or not */\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t/* construct respond status code and data. */\n\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\treturn paraLen;\n\t\t}\n\t} else if (BT_GSET_TARGET_BD_ADDR == setType) {\n\t\t/* fill h2c parameters */\n\t\tbtOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_L;\n\t\th2cParaBuf[0] = pBtReq->pParamStart[1];\n\t\th2cParaBuf[1] = pBtReq->pParamStart[2];\n\t\th2cParaBuf[2] = pBtReq->pParamStart[3];\n\t\th2cParaLen = 3;\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t/* ckeck bt return status. */\n\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\treturn paraLen;\n\t\t}\n\n\t\tbtOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_H;\n\t\th2cParaBuf[0] = pBtReq->pParamStart[4];\n\t\th2cParaBuf[1] = pBtReq->pParamStart[5];\n\t\th2cParaBuf[2] = pBtReq->pParamStart[6];\n\t\th2cParaLen = 3;\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t/* ckeck bt return status. */\n\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\treturn paraLen;\n\t\t}\n\t} else if (BT_GSET_TX_PWR_FINETUNE == setType) {\n\t\t/* fill h2c parameters */\n\t\tbtOpcode = BT_LO_OP_SET_TX_POWER_CALIBRATION;\n\t\th2cParaBuf[0] = calVal;\n\t\th2cParaLen = 1;\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t/* ckeck bt return status. */\n\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\treturn paraLen;\n\t\t}\n\t} else if (BT_SET_TRACKING_INTERVAL == setType) {\n\t\t/*\tBT_LO_OP_SET_TRACKING_INTERVAL\t\t\t\t\t\t\t\t= 0x22, */\n\t\t/*\tBT_LO_OP_SET_THERMAL_METER\t\t\t\t\t\t\t\t\t= 0x23, */\n\t\t/*\tBT_LO_OP_ENABLE_CFO_TRACKING\t\t\t\t\t\t\t\t\t= 0x24, */\n\t\tbtOpcode = BT_LO_OP_SET_TRACKING_INTERVAL;\n\t\th2cParaBuf[0] = calVal;\n\t\th2cParaLen = 1;\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t/* ckeck bt return status. */\n\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\treturn paraLen;\n\t\t}\n\t} else if (BT_SET_THERMAL_METER == setType) {\n\t\tbtOpcode = BT_LO_OP_SET_THERMAL_METER;\n\t\th2cParaBuf[0] = calVal;\n\t\th2cParaLen = 1;\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t/* ckeck bt return status. */\n\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\treturn paraLen;\n\t\t}\n\t} else if (BT_ENABLE_CFO_TRACKING == setType) {\n\t\tbtOpcode = BT_LO_OP_ENABLE_CFO_TRACKING;\n\t\th2cParaBuf[0] = calVal;\n\t\th2cParaLen = 1;\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t\t/* ckeck bt return status. */\n\t\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\t\treturn paraLen;\n\t\t}\n\t}\n\n\tpBtRsp->status = BT_STATUS_SUCCESS;\n\treturn paraLen;\n}\n\n\n\nu16\nmptbt_BtSetTxRxPars(\n\t\tPADAPTER\t\tAdapter,\n\t\tPBT_REQ_CMD\tpBtReq,\n\t\tPBT_RSP_CMD\tpBtRsp\n)\n{\n\tu8\t\t\t\th2cParaBuf[6] = {0};\n\tu8\t\t\t\th2cParaLen = 0;\n\tu16\t\t\t\tparaLen = 0;\n\tu8\t\t\t\tretStatus = BT_STATUS_BT_OP_SUCCESS;\n\tu8\t\t\t\tbtOpcode;\n\tu8\t\t\t\tbtOpcodeVer = 0;\n\tPBT_TXRX_PARAMETERS pTxRxPars = (PBT_TXRX_PARAMETERS)&pBtReq->pParamStart[0];\n\tu16\t\t\t\tlenTxRx = sizeof(BT_TXRX_PARAMETERS);\n\tu8\t\t\t\ti;\n\tu8\t\t\t\tbdAddr[6] = {0};\n\n\t/*  */\n\t/* check upper layer parameters */\n\t/*  */\n\n\t/* 1. check upper layer opcode version */\n\tif (pBtReq->opCodeVer != 1) {\n\t\tRTW_INFO(\"[MPT], Error!! Upper OP code version not match!!!\\n\");\n\t\tpBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;\n\t\treturn paraLen;\n\t}\n\t/* 2. check upper layer parameter length */\n\tif (pBtReq->paraLength == sizeof(BT_TXRX_PARAMETERS)) {\n\t\tRTW_INFO(\"[MPT], pTxRxPars->txrxChannel=0x%x\\n\", pTxRxPars->txrxChannel);\n\t\tRTW_INFO(\"[MPT], pTxRxPars->txrxTxPktCnt=0x%8x\\n\", pTxRxPars->txrxTxPktCnt);\n\t\tRTW_INFO(\"[MPT], pTxRxPars->txrxTxPktInterval=0x%x\\n\", pTxRxPars->txrxTxPktInterval);\n\t\tRTW_INFO(\"[MPT], pTxRxPars->txrxPayloadType=0x%x\\n\", pTxRxPars->txrxPayloadType);\n\t\tRTW_INFO(\"[MPT], pTxRxPars->txrxPktType=0x%x\\n\", pTxRxPars->txrxPktType);\n\t\tRTW_INFO(\"[MPT], pTxRxPars->txrxPayloadLen=0x%x\\n\", pTxRxPars->txrxPayloadLen);\n\t\tRTW_INFO(\"[MPT], pTxRxPars->txrxPktHeader=0x%x\\n\", pTxRxPars->txrxPktHeader);\n\t\tRTW_INFO(\"[MPT], pTxRxPars->txrxWhitenCoeff=0x%x\\n\", pTxRxPars->txrxWhitenCoeff);\n\t\tbdAddr[0] = pTxRxPars->txrxBdaddr[5];\n\t\tbdAddr[1] = pTxRxPars->txrxBdaddr[4];\n\t\tbdAddr[2] = pTxRxPars->txrxBdaddr[3];\n\t\tbdAddr[3] = pTxRxPars->txrxBdaddr[2];\n\t\tbdAddr[4] = pTxRxPars->txrxBdaddr[1];\n\t\tbdAddr[5] = pTxRxPars->txrxBdaddr[0];\n\t\tRTW_INFO(\"[MPT], pTxRxPars->txrxBdaddr: %s\", &bdAddr[0]);\n\t\tRTW_INFO(\"[MPT], pTxRxPars->txrxTxGainIndex=0x%x\\n\", pTxRxPars->txrxTxGainIndex);\n\t} else {\n\t\tRTW_INFO(\"[MPT], Error!! pBtReq->paraLength=%d, correct Len=%d\\n\", pBtReq->paraLength, lenTxRx);\n\t\tpBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;\n\t\treturn paraLen;\n\t}\n\n\t/*  */\n\t/* execute lower layer opcodes */\n\t/*  */\n\n\t/* fill h2c parameters */\n\tbtOpcode = BT_LO_OP_SET_PKT_HEADER;\n\tif (pTxRxPars->txrxPktHeader > 0x3ffff) {\n\t\tRTW_INFO(\"[MPT], Error!! pTxRxPars->txrxPktHeader=0x%x is out of range, (should be between 0x0~0x3ffff)\\n\", pTxRxPars->txrxPktHeader);\n\t\tpBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\treturn paraLen;\n\t} else {\n\t\th2cParaBuf[0] = (u8)(pTxRxPars->txrxPktHeader & 0xff);\n\t\th2cParaBuf[1] = (u8)((pTxRxPars->txrxPktHeader & 0xff00) >> 8);\n\t\th2cParaBuf[2] = (u8)((pTxRxPars->txrxPktHeader & 0xff0000) >> 16);\n\t\th2cParaLen = 3;\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t}\n\n\t/* ckeck bt return status. */\n\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\treturn paraLen;\n\t}\n\n\t/* fill h2c parameters */\n\tbtOpcode = BT_LO_OP_SET_PKT_TYPE_LEN;\n\t{\n\t\tu16\tpayloadLenLimit = 0;\n\t\tswitch (pTxRxPars->txrxPktType) {\n\t\tcase MP_BT_PKT_DH1:\n\t\t\tpayloadLenLimit = 27 * 8;\n\t\t\tbreak;\n\t\tcase MP_BT_PKT_DH3:\n\t\t\tpayloadLenLimit = 183 * 8;\n\t\t\tbreak;\n\t\tcase MP_BT_PKT_DH5:\n\t\t\tpayloadLenLimit = 339 * 8;\n\t\t\tbreak;\n\t\tcase MP_BT_PKT_2DH1:\n\t\t\tpayloadLenLimit = 54 * 8;\n\t\t\tbreak;\n\t\tcase MP_BT_PKT_2DH3:\n\t\t\tpayloadLenLimit = 367 * 8;\n\t\t\tbreak;\n\t\tcase MP_BT_PKT_2DH5:\n\t\t\tpayloadLenLimit = 679 * 8;\n\t\t\tbreak;\n\t\tcase MP_BT_PKT_3DH1:\n\t\t\tpayloadLenLimit = 83 * 8;\n\t\t\tbreak;\n\t\tcase MP_BT_PKT_3DH3:\n\t\t\tpayloadLenLimit = 552 * 8;\n\t\t\tbreak;\n\t\tcase MP_BT_PKT_3DH5:\n\t\t\tpayloadLenLimit = 1021 * 8;\n\t\t\tbreak;\n\t\tcase MP_BT_PKT_LE:\n\t\t\tpayloadLenLimit = 39 * 8;\n\t\t\tbreak;\n\t\tdefault: {\n\t\t\tRTW_INFO(\"[MPT], Error!! Unknown pTxRxPars->txrxPktType=0x%x\\n\", pTxRxPars->txrxPktType);\n\t\t\tpBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\t\treturn paraLen;\n\t\t}\n\t\tbreak;\n\t\t}\n\n\t\tif (pTxRxPars->txrxPayloadLen > payloadLenLimit) {\n\t\t\tRTW_INFO(\"[MPT], Error!! pTxRxPars->txrxPayloadLen=0x%x, (should smaller than %d)\\n\",\n\t\t\t\t pTxRxPars->txrxPayloadLen, payloadLenLimit);\n\t\t\tpBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\t\treturn paraLen;\n\t\t}\n\n\t\th2cParaBuf[0] = pTxRxPars->txrxPktType;\n\t\th2cParaBuf[1] = (u8)((pTxRxPars->txrxPayloadLen & 0xff));\n\t\th2cParaBuf[2] = (u8)((pTxRxPars->txrxPayloadLen & 0xff00) >> 8);\n\t\th2cParaLen = 3;\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t}\n\n\t/* ckeck bt return status. */\n\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\treturn paraLen;\n\t}\n\n\t/* fill h2c parameters */\n\tbtOpcode = BT_LO_OP_SET_PKT_CNT_L_PL_TYPE;\n\tif (pTxRxPars->txrxPayloadType > MP_BT_PAYLOAD_MAX) {\n\t\tRTW_INFO(\"[MPT], Error!! pTxRxPars->txrxPayloadType=0x%x, (should be between 0~4)\\n\", pTxRxPars->txrxPayloadType);\n\t\tpBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\treturn paraLen;\n\t} else {\n\t\th2cParaBuf[0] = (u8)((pTxRxPars->txrxTxPktCnt & 0xff));\n\t\th2cParaBuf[1] = (u8)((pTxRxPars->txrxTxPktCnt & 0xff00) >> 8);\n\t\th2cParaBuf[2] = pTxRxPars->txrxPayloadType;\n\t\th2cParaLen = 3;\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t}\n\n\t/* ckeck bt return status. */\n\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\treturn paraLen;\n\t}\n\n\t/* fill h2c parameters */\n\tbtOpcode = BT_LO_OP_SET_PKT_CNT_H_PKT_INTV;\n\tif (pTxRxPars->txrxTxPktInterval > 15) {\n\t\tRTW_INFO(\"[MPT], Error!! pTxRxPars->txrxTxPktInterval=0x%x, (should be between 0~15)\\n\", pTxRxPars->txrxTxPktInterval);\n\t\tpBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\treturn paraLen;\n\t} else {\n\t\th2cParaBuf[0] = (u8)((pTxRxPars->txrxTxPktCnt & 0xff0000) >> 16);\n\t\th2cParaBuf[1] = (u8)((pTxRxPars->txrxTxPktCnt & 0xff000000) >> 24);\n\t\th2cParaBuf[2] = pTxRxPars->txrxTxPktInterval;\n\t\th2cParaLen = 3;\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t}\n\n\t/* ckeck bt return status. */\n\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\treturn paraLen;\n\t}\n\n\t/* fill h2c parameters */\n\tbtOpcode = BT_LO_OP_SET_WHITENCOEFF;\n\t{\n\t\th2cParaBuf[0] = pTxRxPars->txrxWhitenCoeff;\n\t\th2cParaLen = 1;\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t}\n\n\t/* ckeck bt return status. */\n\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\treturn paraLen;\n\t}\n\n\n\t/* fill h2c parameters */\n\tbtOpcode = BT_LO_OP_SET_CHNL_TX_GAIN;\n\tif ((pTxRxPars->txrxChannel > 78) ||\n\t    (pTxRxPars->txrxTxGainIndex > 7)) {\n\t\tRTW_INFO(\"[MPT], Error!! pTxRxPars->txrxChannel=0x%x, (should be between 0~78)\\n\", pTxRxPars->txrxChannel);\n\t\tRTW_INFO(\"[MPT], Error!! pTxRxPars->txrxTxGainIndex=0x%x, (should be between 0~7)\\n\", pTxRxPars->txrxTxGainIndex);\n\t\tpBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\treturn paraLen;\n\t} else {\n\t\th2cParaBuf[0] = pTxRxPars->txrxChannel;\n\t\th2cParaBuf[1] = pTxRxPars->txrxTxGainIndex;\n\t\th2cParaLen = 2;\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t}\n\n\t/* ckeck bt return status. */\n\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\treturn paraLen;\n\t}\n\n\t/* fill h2c parameters */\n\tbtOpcode = BT_LO_OP_SET_BD_ADDR_L;\n\tif ((pTxRxPars->txrxBdaddr[0] == 0) &&\n\t    (pTxRxPars->txrxBdaddr[1] == 0) &&\n\t    (pTxRxPars->txrxBdaddr[2] == 0) &&\n\t    (pTxRxPars->txrxBdaddr[3] == 0) &&\n\t    (pTxRxPars->txrxBdaddr[4] == 0) &&\n\t    (pTxRxPars->txrxBdaddr[5] == 0)) {\n\t\tRTW_INFO(\"[MPT], Error!! pTxRxPars->txrxBdaddr=all zero\\n\");\n\t\tpBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\treturn paraLen;\n\t}\n\tif ((pTxRxPars->txrxBdaddr[0] == 0xff) &&\n\t    (pTxRxPars->txrxBdaddr[1] == 0xff) &&\n\t    (pTxRxPars->txrxBdaddr[2] == 0xff) &&\n\t    (pTxRxPars->txrxBdaddr[3] == 0xff) &&\n\t    (pTxRxPars->txrxBdaddr[4] == 0xff) &&\n\t    (pTxRxPars->txrxBdaddr[5] == 0xff)) {\n\t\tRTW_INFO(\"[MPT], Error!! pTxRxPars->txrxBdaddr=all 0xf\\n\");\n\t\tpBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\treturn paraLen;\n\t}\n\n\t{\n\t\th2cParaBuf[0] = pTxRxPars->txrxBdaddr[0];\n\t\th2cParaBuf[1] = pTxRxPars->txrxBdaddr[1];\n\t\th2cParaBuf[2] = pTxRxPars->txrxBdaddr[2];\n\t\th2cParaLen = 3;\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t}\n\t/* ckeck bt return status. */\n\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\treturn paraLen;\n\t}\n\n\tbtOpcode = BT_LO_OP_SET_BD_ADDR_H;\n\t{\n\t\th2cParaBuf[0] = pTxRxPars->txrxBdaddr[3];\n\t\th2cParaBuf[1] = pTxRxPars->txrxBdaddr[4];\n\t\th2cParaBuf[2] = pTxRxPars->txrxBdaddr[5];\n\t\th2cParaLen = 3;\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t}\n\t/* ckeck bt return status. */\n\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\treturn paraLen;\n\t}\n\n\tpBtRsp->status = BT_STATUS_SUCCESS;\n\treturn paraLen;\n}\n\n\n\nu16\nmptbt_BtTestCtrl(\n\t\tPADAPTER\t\tAdapter,\n\t\tPBT_REQ_CMD\tpBtReq,\n\t\tPBT_RSP_CMD\tpBtRsp\n)\n{\n\tu8\t\t\t\th2cParaBuf[6] = {0};\n\tu8\t\t\t\th2cParaLen = 0;\n\tu16\t\t\t\tparaLen = 0;\n\tu8\t\t\t\tretStatus = BT_STATUS_BT_OP_SUCCESS;\n\tu8\t\t\t\tbtOpcode;\n\tu8\t\t\t\tbtOpcodeVer = 0;\n\tu8\t\t\t\ttestCtrl = 0;\n\n\t/*  */\n\t/* check upper layer parameters */\n\t/*  */\n\n\t/* 1. check upper layer opcode version */\n\tif (pBtReq->opCodeVer != 1) {\n\t\tRTW_INFO(\"[MPT], Error!! Upper OP code version not match!!!\\n\");\n\t\tpBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;\n\t\treturn paraLen;\n\t}\n\t/* 2. check upper layer parameter length */\n\tif (1 == pBtReq->paraLength) {\n\t\ttestCtrl = pBtReq->pParamStart[0];\n\t\tRTW_INFO(\"[MPT], testCtrl=%d\\n\", testCtrl);\n\t} else {\n\t\tRTW_INFO(\"[MPT], Error!! wrong parameter length=%d (should be 1)\\n\", pBtReq->paraLength);\n\t\tpBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;\n\t\treturn paraLen;\n\t}\n\n\t/*  */\n\t/* execute lower layer opcodes */\n\t/*  */\n\n\t/* 1. fill h2c parameters\t */\n\t/* check bt mode */\n\tbtOpcode = BT_LO_OP_TEST_CTRL;\n\tif (testCtrl >= MP_BT_TEST_MAX) {\n\t\tRTW_INFO(\"[MPT], Error!! testCtrl=0x%x, (should be between smaller or equal to 0x%x)\\n\",\n\t\t\t testCtrl, MP_BT_TEST_MAX - 1);\n\t\tpBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;\n\t\treturn paraLen;\n\t} else {\n\t\th2cParaBuf[0] = testCtrl;\n\t\th2cParaLen = 1;\n\t\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);\n\t}\n\n\t/* 3. construct respond status code and data. */\n\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\treturn paraLen;\n\t}\n\n\tpBtRsp->status = BT_STATUS_SUCCESS;\n\treturn paraLen;\n}\n\n\nu16\nmptbt_TestBT(\n\t\tPADAPTER\t\tAdapter,\n\t\tPBT_REQ_CMD\tpBtReq,\n\t\tPBT_RSP_CMD\tpBtRsp\n)\n{\n\n\tu8\t\t\t\th2cParaBuf[6] = {0};\n\tu8\t\t\t\th2cParaLen = 0;\n\tu16\t\t\t\tparaLen = 0;\n\tu8\t\t\t\tretStatus = BT_STATUS_BT_OP_SUCCESS;\n\tu8\t\t\t\tbtOpcode;\n\tu8\t\t\t\tbtOpcodeVer = 0;\n\tu8\t\t\t\ttestCtrl = 0;\n\n\t/* 1. fill h2c parameters\t */\n\tbtOpcode =  0x11;\n\th2cParaBuf[0] = 0x11;\n\th2cParaBuf[1] = 0x0;\n\th2cParaBuf[2] = 0x0;\n\th2cParaBuf[3] = 0x0;\n\th2cParaBuf[4] = 0x0;\n\th2cParaLen = 1;\n\t/*\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); */\n\tretStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, h2cParaBuf, h2cParaLen);\n\n\n\t/* 3. construct respond status code and data. */\n\tif (BT_STATUS_BT_OP_SUCCESS != retStatus) {\n\t\tpBtRsp->status = ((btOpcode << 8) | retStatus);\n\t\tRTW_INFO(\"[MPT], Error!! status code=0x%x\\n\", pBtRsp->status);\n\t\treturn paraLen;\n\t}\n\n\tpBtRsp->status = BT_STATUS_SUCCESS;\n\treturn paraLen;\n}\n\nvoid\nmptbt_BtControlProcess(\n\tPADAPTER\tAdapter,\n\tvoid\t\t\t*pInBuf\n)\n{\n\tu8\t\t\tH2C_Parameter[6] = {0};\n\tPBT_H2C\t\tpH2c = (PBT_H2C)&H2C_Parameter[0];\n\tPMPT_CONTEXT\tpMptCtx = &(Adapter->mppriv.mpt_ctx);\n\tPBT_REQ_CMD\tpBtReq = (PBT_REQ_CMD)pInBuf;\n\tPBT_RSP_CMD\tpBtRsp;\n\tu8\t\t\ti;\n\n\n\tRTW_INFO(\"[MPT], mptbt_BtControlProcess()=========>\\n\");\n\n\tRTW_INFO(\"[MPT], input opCodeVer=%d\\n\", pBtReq->opCodeVer);\n\tRTW_INFO(\"[MPT], input OpCode=%d\\n\", pBtReq->OpCode);\n\tRTW_INFO(\"[MPT], paraLength=%d\\n\", pBtReq->paraLength);\n\tif (pBtReq->paraLength) {\n\t\t/* RTW_INFO(\"[MPT], parameters(hex):0x%x %d\\n\",&pBtReq->pParamStart[0], pBtReq->paraLength); */\n\t}\n\n\t_rtw_memset((void *)pMptCtx->mptOutBuf, 0, 100);\n\tpMptCtx->mptOutLen = 4; /* length of (BT_RSP_CMD.status+BT_RSP_CMD.paraLength) */\n\n\tpBtRsp = (PBT_RSP_CMD)pMptCtx->mptOutBuf;\n\tpBtRsp->status = BT_STATUS_SUCCESS;\n\tpBtRsp->paraLength = 0x0;\n\n\t/* The following we should maintain the User OP codes sent by upper layer */\n\tswitch (pBtReq->OpCode) {\n\tcase BT_UP_OP_BT_READY:\n\t\tRTW_INFO(\"[MPT], OPcode : [BT_READY]\\n\");\n\t\tpBtRsp->paraLength = mptbt_BtReady(Adapter, pBtReq, pBtRsp);\n\t\tbreak;\n\tcase BT_UP_OP_BT_SET_MODE:\n\t\tRTW_INFO(\"[MPT], OPcode : [BT_SET_MODE]\\n\");\n\t\tpBtRsp->paraLength = mptbt_BtSetMode(Adapter, pBtReq, pBtRsp);\n\t\tbreak;\n\tcase BT_UP_OP_BT_SET_TX_RX_PARAMETER:\n\t\tRTW_INFO(\"[MPT], OPcode : [BT_SET_TXRX_PARAMETER]\\n\");\n\t\tpBtRsp->paraLength = mptbt_BtSetTxRxPars(Adapter, pBtReq, pBtRsp);\n\t\tbreak;\n\tcase BT_UP_OP_BT_SET_GENERAL:\n\t\tRTW_INFO(\"[MPT], OPcode : [BT_SET_GENERAL]\\n\");\n\t\tpBtRsp->paraLength = mptbt_BtSetGeneral(Adapter, pBtReq, pBtRsp);\n\t\tbreak;\n\tcase BT_UP_OP_BT_GET_GENERAL:\n\t\tRTW_INFO(\"[MPT], OPcode : [BT_GET_GENERAL]\\n\");\n\t\tpBtRsp->paraLength = mptbt_BtGetGeneral(Adapter, pBtReq, pBtRsp);\n\t\tbreak;\n\tcase BT_UP_OP_BT_TEST_CTRL:\n\t\tRTW_INFO(\"[MPT], OPcode : [BT_TEST_CTRL]\\n\");\n\t\tpBtRsp->paraLength = mptbt_BtTestCtrl(Adapter, pBtReq, pBtRsp);\n\t\tbreak;\n\tcase BT_UP_OP_TEST_BT:\n\t\tRTW_INFO(\"[MPT], OPcode : [TEST_BT]\\n\");\n\t\tpBtRsp->paraLength = mptbt_TestBT(Adapter, pBtReq, pBtRsp);\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(\"[MPT], Error!! OPcode : UNDEFINED!!!!\\n\");\n\t\tpBtRsp->status = BT_STATUS_UNKNOWN_OPCODE_U;\n\t\tpBtRsp->paraLength = 0x0;\n\t\tbreak;\n\t}\n\n\tpMptCtx->mptOutLen += pBtRsp->paraLength;\n\n\tRTW_INFO(\"[MPT], pMptCtx->mptOutLen=%d, pBtRsp->paraLength=%d\\n\", pMptCtx->mptOutLen, pBtRsp->paraLength);\n\tRTW_INFO(\"[MPT], mptbt_BtControlProcess()<=========\\n\");\n}\n\n#endif\n"
  },
  {
    "path": "core/rtw_btcoex.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#include <drv_types.h>\n#include <hal_data.h>\n#ifdef CONFIG_BT_COEXIST\n#include <hal_btcoex.h>\n\nvoid rtw_btcoex_Initialize(PADAPTER padapter)\n{\n\thal_btcoex_Initialize(padapter);\n}\n\nvoid rtw_btcoex_PowerOnSetting(PADAPTER padapter)\n{\n\thal_btcoex_PowerOnSetting(padapter);\n}\n\nvoid rtw_btcoex_AntInfoSetting(PADAPTER padapter)\n{\n\thal_btcoex_AntInfoSetting(padapter);\n}\n\nvoid rtw_btcoex_PowerOffSetting(PADAPTER padapter)\n{\n\thal_btcoex_PowerOffSetting(padapter);\n}\n\nvoid rtw_btcoex_PreLoadFirmware(PADAPTER padapter)\n{\n\thal_btcoex_PreLoadFirmware(padapter);\n}\n\nvoid rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly)\n{\n\thal_btcoex_InitHwConfig(padapter, bWifiOnly);\n}\n\nvoid rtw_btcoex_IpsNotify(PADAPTER padapter, u8 type)\n{\n\tPHAL_DATA_TYPE\tpHalData;\n\n\tpHalData = GET_HAL_DATA(padapter);\n\tif (_FALSE == pHalData->EEPROMBluetoothCoexist)\n\t\treturn;\n\n\thal_btcoex_IpsNotify(padapter, type);\n}\n\nvoid rtw_btcoex_LpsNotify(PADAPTER padapter, u8 type)\n{\n\tPHAL_DATA_TYPE\tpHalData;\n\n\tpHalData = GET_HAL_DATA(padapter);\n\tif (_FALSE == pHalData->EEPROMBluetoothCoexist)\n\t\treturn;\n\n\thal_btcoex_LpsNotify(padapter, type);\n}\n\nvoid rtw_btcoex_ScanNotify(PADAPTER padapter, u8 type)\n{\n\tPHAL_DATA_TYPE\tpHalData;\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\tstruct bt_coex_info *pcoex_info = &padapter->coex_info;\n\tPBT_MGNT\tpBtMgnt = &pcoex_info->BtMgnt;\n#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */\n\n\tpHalData = GET_HAL_DATA(padapter);\n\tif (_FALSE == pHalData->EEPROMBluetoothCoexist)\n\t\treturn;\n\n\tif (_FALSE == type) {\n\t\t#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_buddy_check_fwstate(padapter, WIFI_SITE_MONITOR))\n\t\t\treturn;\n\t\t#endif\n\n\t\tif (DEV_MGMT_TX_NUM(adapter_to_dvobj(padapter))\n\t\t\t|| DEV_ROCH_NUM(adapter_to_dvobj(padapter)))\n\t\t\treturn;\n\t}\n\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\tif (pBtMgnt->ExtConfig.bEnableWifiScanNotify)\n\t\trtw_btcoex_SendScanNotify(padapter, type);\n#endif /* CONFIG_BT_COEXIST_SOCKET_TRX\t */\n\n\thal_btcoex_ScanNotify(padapter, type);\n}\n\nvoid rtw_btcoex_ConnectNotify(PADAPTER padapter, u8 action)\n{\n\tPHAL_DATA_TYPE\tpHalData;\n\n\tpHalData = GET_HAL_DATA(padapter);\n\tif (_FALSE == pHalData->EEPROMBluetoothCoexist)\n\t\treturn;\n\n#ifdef DBG_CONFIG_ERROR_RESET\n\tif (_TRUE == rtw_hal_sreset_inprogress(padapter)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": [BTCoex] under reset, skip notify!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter));\n\t\treturn;\n\t}\n#endif /* DBG_CONFIG_ERROR_RESET */\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (_FALSE == action) {\n\t\tif (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING))\n\t\t\treturn;\n\t}\n#endif\n\n\thal_btcoex_ConnectNotify(padapter, action);\n}\n\nvoid rtw_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus)\n{\n\tPHAL_DATA_TYPE\tpHalData;\n\n\tpHalData = GET_HAL_DATA(padapter);\n\tif (_FALSE == pHalData->EEPROMBluetoothCoexist)\n\t\treturn;\n\n#ifdef DBG_CONFIG_ERROR_RESET\n\tif (_TRUE == rtw_hal_sreset_inprogress(padapter)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": [BTCoex] under reset, skip notify!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter));\n\t\treturn;\n\t}\n#endif /* DBG_CONFIG_ERROR_RESET */\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (RT_MEDIA_DISCONNECT == mediaStatus) {\n\t\tif (rtw_mi_buddy_check_fwstate(padapter, WIFI_ASOC_STATE))\n\t\t\treturn;\n\t}\n#endif /* CONFIG_CONCURRENT_MODE */\n\n\tif ((RT_MEDIA_CONNECT == mediaStatus)\n\t    && (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE))\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_DL_RSVD_PAGE, NULL);\n\n\thal_btcoex_MediaStatusNotify(padapter, mediaStatus);\n}\n\nvoid rtw_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType)\n{\n\tPHAL_DATA_TYPE\tpHalData;\n\n\tpHalData = GET_HAL_DATA(padapter);\n\tif (_FALSE == pHalData->EEPROMBluetoothCoexist)\n\t\treturn;\n\n\thal_btcoex_SpecialPacketNotify(padapter, pktType);\n}\n\nvoid rtw_btcoex_IQKNotify(PADAPTER padapter, u8 state)\n{\n\tPHAL_DATA_TYPE\tpHalData;\n\n\tpHalData = GET_HAL_DATA(padapter);\n\tif (_FALSE == pHalData->EEPROMBluetoothCoexist)\n\t\treturn;\n\n\thal_btcoex_IQKNotify(padapter, state);\n}\n\nvoid rtw_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)\n{\n\tPHAL_DATA_TYPE\tpHalData;\n\n\tpHalData = GET_HAL_DATA(padapter);\n\tif (_FALSE == pHalData->EEPROMBluetoothCoexist)\n\t\treturn;\n\n\thal_btcoex_BtInfoNotify(padapter, length, tmpBuf);\n}\n\nvoid rtw_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)\n{\n\tPHAL_DATA_TYPE\tpHalData;\n\n\tpHalData = GET_HAL_DATA(padapter);\n\tif (_FALSE == pHalData->EEPROMBluetoothCoexist)\n\t\treturn;\n\n\tif (padapter->registrypriv.mp_mode == 1)\n\t\treturn;\n\n\thal_btcoex_BtMpRptNotify(padapter, length, tmpBuf);\n}\n\nvoid rtw_btcoex_SuspendNotify(PADAPTER padapter, u8 state)\n{\n\tPHAL_DATA_TYPE\tpHalData;\n\n\tpHalData = GET_HAL_DATA(padapter);\n\tif (_FALSE == pHalData->EEPROMBluetoothCoexist)\n\t\treturn;\n\n\thal_btcoex_SuspendNotify(padapter, state);\n}\n\nvoid rtw_btcoex_HaltNotify(PADAPTER padapter)\n{\n\tPHAL_DATA_TYPE\tpHalData;\n\tu8 do_halt = 1;\n\n\tpHalData = GET_HAL_DATA(padapter);\n\tif (_FALSE == pHalData->EEPROMBluetoothCoexist)\n\t\tdo_halt = 0;\n\n\tif (_FALSE == padapter->bup) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": bup=%d Skip!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter), padapter->bup);\n\t\tdo_halt = 0;\n\t}\n\n\tif (rtw_is_surprise_removed(padapter)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": bSurpriseRemoved=%s Skip!\\n\",\n\t\t\tFUNC_ADPT_ARG(padapter), rtw_is_surprise_removed(padapter) ? \"True\" : \"False\");\n\t\tdo_halt = 0;\n\t}\n\n\thal_btcoex_HaltNotify(padapter, do_halt);\n}\n\nvoid rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type)\n{\n\thal_btcoex_switchband_notify(under_scan, band_type);\n}\n\nvoid rtw_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length)\n{\n\thal_btcoex_WlFwDbgInfoNotify(padapter, tmpBuf, length);\n}\n\nvoid rtw_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id)\n{\n\thal_btcoex_rx_rate_change_notify(padapter, is_data_frame, rate_id);\n}\n\nvoid rtw_btcoex_SwitchBtTRxMask(PADAPTER padapter)\n{\n\thal_btcoex_SwitchBtTRxMask(padapter);\n}\n\nvoid rtw_btcoex_Switch(PADAPTER padapter, u8 enable)\n{\n\thal_btcoex_SetBTCoexist(padapter, enable);\n}\n\nu8 rtw_btcoex_IsBtDisabled(PADAPTER padapter)\n{\n\treturn hal_btcoex_IsBtDisabled(padapter);\n}\n\nvoid rtw_btcoex_Handler(PADAPTER padapter)\n{\n\tPHAL_DATA_TYPE\tpHalData;\n\n\tpHalData = GET_HAL_DATA(padapter);\n\n\tif (_FALSE == pHalData->EEPROMBluetoothCoexist)\n\t\treturn;\n\n\thal_btcoex_Hanlder(padapter);\n}\n\ns32 rtw_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter)\n{\n\ts32 coexctrl;\n\n\tcoexctrl = hal_btcoex_IsBTCoexRejectAMPDU(padapter);\n\n\treturn coexctrl;\n}\n\ns32 rtw_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter)\n{\n\ts32 coexctrl;\n\n\tcoexctrl = hal_btcoex_IsBTCoexCtrlAMPDUSize(padapter);\n\n\treturn coexctrl;\n}\n\nu32 rtw_btcoex_GetAMPDUSize(PADAPTER padapter)\n{\n\tu32 size;\n\n\tsize = hal_btcoex_GetAMPDUSize(padapter);\n\n\treturn size;\n}\n\nvoid rtw_btcoex_SetManualControl(PADAPTER padapter, u8 manual)\n{\n\tif (_TRUE == manual)\n\t\thal_btcoex_SetManualControl(padapter, _TRUE);\n\telse\n\t\thal_btcoex_SetManualControl(padapter, _FALSE);\n}\n\nu8 rtw_btcoex_1Ant(PADAPTER padapter)\n{\n\treturn hal_btcoex_1Ant(padapter);\n}\n\nu8 rtw_btcoex_IsBtControlLps(PADAPTER padapter)\n{\n\treturn hal_btcoex_IsBtControlLps(padapter);\n}\n\nu8 rtw_btcoex_IsLpsOn(PADAPTER padapter)\n{\n\treturn hal_btcoex_IsLpsOn(padapter);\n}\n\nu8 rtw_btcoex_RpwmVal(PADAPTER padapter)\n{\n\treturn hal_btcoex_RpwmVal(padapter);\n}\n\nu8 rtw_btcoex_LpsVal(PADAPTER padapter)\n{\n\treturn hal_btcoex_LpsVal(padapter);\n}\n\nu32 rtw_btcoex_GetRaMask(PADAPTER padapter)\n{\n\treturn hal_btcoex_GetRaMask(padapter);\n}\n\nu8 rtw_btcoex_query_reduced_wl_pwr_lvl(PADAPTER padapter)\n{\n\treturn hal_btcoex_query_reduced_wl_pwr_lvl(padapter);\n}\n\nvoid rtw_btcoex_set_reduced_wl_pwr_lvl(PADAPTER padapter, u8 val)\n{\n\thal_btcoex_set_reduced_wl_pwr_lvl(padapter, val);\n}\n\nvoid rtw_btcoex_do_reduce_wl_pwr_lvl(PADAPTER padapter)\n{\n\thal_btcoex_do_reduce_wl_pwr_lvl(padapter);\n}\n\nvoid rtw_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen)\n{\n\thal_btcoex_RecordPwrMode(padapter, pCmdBuf, cmdLen);\n}\n\nvoid rtw_btcoex_DisplayBtCoexInfo(PADAPTER padapter, u8 *pbuf, u32 bufsize)\n{\n\thal_btcoex_DisplayBtCoexInfo(padapter, pbuf, bufsize);\n}\n\nvoid rtw_btcoex_SetDBG(PADAPTER padapter, u32 *pDbgModule)\n{\n\thal_btcoex_SetDBG(padapter, pDbgModule);\n}\n\nu32 rtw_btcoex_GetDBG(PADAPTER padapter, u8 *pStrBuf, u32 bufSize)\n{\n\treturn hal_btcoex_GetDBG(padapter, pStrBuf, bufSize);\n}\n\nu8 rtw_btcoex_IncreaseScanDeviceNum(PADAPTER padapter)\n{\n\treturn hal_btcoex_IncreaseScanDeviceNum(padapter);\n}\n\nu8 rtw_btcoex_IsBtLinkExist(PADAPTER padapter)\n{\n\treturn hal_btcoex_IsBtLinkExist(padapter);\n}\n\nvoid rtw_btcoex_SetBtPatchVersion(PADAPTER padapter, u16 btHciVer, u16 btPatchVer)\n{\n\thal_btcoex_SetBtPatchVersion(padapter, btHciVer, btPatchVer);\n}\n\nvoid rtw_btcoex_SetHciVersion(PADAPTER  padapter, u16 hciVersion)\n{\n\thal_btcoex_SetHciVersion(padapter, hciVersion);\n}\n\nvoid rtw_btcoex_StackUpdateProfileInfo(void)\n{\n\thal_btcoex_StackUpdateProfileInfo();\n}\n\nvoid rtw_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON)\n{\n\thal_btcoex_pta_off_on_notify(padapter, bBTON);\n}\n\n#ifdef CONFIG_RF4CE_COEXIST\nvoid rtw_btcoex_SetRf4ceLinkState(PADAPTER padapter, u8 state)\n{\n\thal_btcoex_set_rf4ce_link_state(state);\n}\n\nu8 rtw_btcoex_GetRf4ceLinkState(PADAPTER padapter)\n{\n\treturn hal_btcoex_get_rf4ce_link_state();\n}\n#endif\n\n/* ==================================================\n * Below Functions are called by BT-Coex\n * ================================================== */\nvoid rtw_btcoex_rx_ampdu_apply(PADAPTER padapter)\n{\n\trtw_rx_ampdu_apply(padapter);\n}\n\nvoid rtw_btcoex_LPS_Enter(PADAPTER padapter)\n{\n\tstruct pwrctrl_priv *pwrpriv;\n\tu8 lpsVal;\n\n\n\tpwrpriv = adapter_to_pwrctl(padapter);\n\n\tpwrpriv->bpower_saving = _TRUE;\n\tlpsVal = rtw_btcoex_LpsVal(padapter);\n\trtw_set_ps_mode(padapter, PS_MODE_MIN, 0, lpsVal, \"BTCOEX\");\n}\n\nu8 rtw_btcoex_LPS_Leave(PADAPTER padapter)\n{\n\tstruct pwrctrl_priv *pwrpriv;\n\n\n\tpwrpriv = adapter_to_pwrctl(padapter);\n\n\tif (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {\n\t\trtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, \"BTCOEX\");\n\t\tpwrpriv->bpower_saving = _FALSE;\n\t}\n\n\treturn _TRUE;\n}\n\nu16 rtw_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data)\n{\n\treturn hal_btcoex_btreg_read(padapter, type, addr, data);\n}\n\nu16 rtw_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val)\n{\n\treturn hal_btcoex_btreg_write(padapter, type, addr, val);\n}\n\nu16 rtw_btcoex_btset_testmode(PADAPTER padapter, u8 type)\n{\n\treturn hal_btcoex_btset_testode(padapter, type);\n}\n\nu8 rtw_btcoex_get_reduce_wl_txpwr(PADAPTER padapter)\n{\n\treturn rtw_btcoex_query_reduced_wl_pwr_lvl(padapter);\n}\n\nu8 rtw_btcoex_get_bt_coexist(PADAPTER padapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n\treturn pHalData->EEPROMBluetoothCoexist;\n}\n\nu8 rtw_btcoex_get_chip_type(PADAPTER padapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n\treturn pHalData->EEPROMBluetoothType;\n}\n\nu8 rtw_btcoex_get_pg_ant_num(PADAPTER padapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n\treturn pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1;\n}\n\nu8 rtw_btcoex_get_pg_single_ant_path(PADAPTER padapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n\treturn pHalData->ant_path;\n}\n\nu8 rtw_btcoex_get_pg_rfe_type(PADAPTER padapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n\treturn pHalData->rfe_type;\n}\n\nu8 rtw_btcoex_is_tfbga_package_type(PADAPTER padapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n#ifdef CONFIG_RTL8723B\n\tif ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA80)\n\t    || (pHalData->PackageType == PACKAGE_TFBGA90))\n\t\treturn _TRUE;\n#endif\n\n\treturn _FALSE;\n}\n\nu8 rtw_btcoex_get_ant_div_cfg(PADAPTER padapter)\n{\n\tPHAL_DATA_TYPE pHalData;\n\n\tpHalData = GET_HAL_DATA(padapter);\n\t\n\treturn (pHalData->AntDivCfg == 0) ? _FALSE : _TRUE;\n}\n\n/* ==================================================\n * Below Functions are BT-Coex socket related function\n * ================================================== */\n\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n_adapter *pbtcoexadapter; /* = NULL; */ /* do not initialise globals to 0 or NULL */\nu8 rtw_btcoex_btinfo_cmd(_adapter *adapter, u8 *buf, u16 len)\n{\n\tstruct cmd_obj *ph2c;\n\tstruct drvextra_cmd_parm *pdrvextra_cmd_parm;\n\tu8 *btinfo;\n\tstruct cmd_priv *pcmdpriv = &adapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tbtinfo = rtw_zmalloc(len);\n\tif (btinfo == NULL) {\n\t\trtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));\n\t\trtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm->ec_id = BTINFO_WK_CID;\n\tpdrvextra_cmd_parm->type = 0;\n\tpdrvextra_cmd_parm->size = len;\n\tpdrvextra_cmd_parm->pbuf = btinfo;\n\n\t_rtw_memcpy(btinfo, buf, len);\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\treturn res;\n}\n\nu8 rtw_btcoex_send_event_to_BT(_adapter *padapter, u8 status,  u8 event_code, u8 opcode_low, u8 opcode_high, u8 *dbg_msg)\n{\n\tu8 localBuf[6] = \"\";\n\tu8 *pRetPar;\n\tu8\tlen = 0, tx_event_length = 0;\n\trtw_HCI_event *pEvent;\n\n\tpEvent = (rtw_HCI_event *)(&localBuf[0]);\n\n\tpEvent->EventCode = event_code;\n\tpEvent->Data[0] = 0x1;\t/* packet # */\n\tpEvent->Data[1] = opcode_low;\n\tpEvent->Data[2] = opcode_high;\n\tlen = len + 3;\n\n\t/* Return parameters starts from here */\n\tpRetPar = &pEvent->Data[len];\n\tpRetPar[0] = status;\t\t/* status */\n\n\tlen++;\n\tpEvent->Length = len;\n\n\t/* total tx event length + EventCode length + sizeof(length) */\n\ttx_event_length = pEvent->Length + 2;\n#if 0\n\trtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, dbg_msg);\n#endif\n\tstatus = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);\n\n\treturn status;\n}\n\n/*\nRef:\nRealtek Wi-Fi Driver\nHost Controller Interface for\nBluetooth 3.0 + HS V1.4 2013/02/07\n\nWindow team code & BT team code\n */\n\n\nu8 rtw_btcoex_parse_BT_info_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)\n{\n#define BT_INFO_LENGTH 8\n\n\tu8 curPollEnable = pcmd[0];\n\tu8 curPollTime = pcmd[1];\n\tu8 btInfoReason = pcmd[2];\n\tu8 btInfoLen = pcmd[3];\n\tu8 btinfo[BT_INFO_LENGTH];\n\n\tu8 localBuf[6] = \"\";\n\tu8 *pRetPar;\n\tu8\tlen = 0, tx_event_length = 0;\n\tRTW_HCI_STATUS status = HCI_STATUS_SUCCESS;\n\trtw_HCI_event *pEvent;\n\n\t/* RTW_INFO(\"%s\\n\",__func__);\n\tRTW_INFO(\"current Poll Enable: %d, currrent Poll Time: %d\\n\",curPollEnable,curPollTime);\n\tRTW_INFO(\"BT Info reason: %d, BT Info length: %d\\n\",btInfoReason,btInfoLen);\n\tRTW_INFO(\"%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\\n\"\n\t\t,pcmd[4],pcmd[5],pcmd[6],pcmd[7],pcmd[8],pcmd[9],pcmd[10],pcmd[11]);*/\n\n\t_rtw_memset(btinfo, 0, BT_INFO_LENGTH);\n\n#if 1\n\tif (BT_INFO_LENGTH != btInfoLen) {\n\t\tstatus = HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE;\n\t\tRTW_INFO(\"Error BT Info Length: %d\\n\", btInfoLen);\n\t\t/* return _FAIL; */\n\t} else\n#endif\n\t{\n\t\tif (0x1 == btInfoReason || 0x2 == btInfoReason) {\n\t\t\t_rtw_memcpy(btinfo, &pcmd[4], btInfoLen);\n\t\t\tbtinfo[0] = btInfoReason;\n\t\t\trtw_btcoex_btinfo_cmd(padapter, btinfo, btInfoLen);\n\t\t} else\n\t\t\tRTW_INFO(\"Other BT info reason\\n\");\n\t}\n\n\t/* send complete event to BT */\n\t{\n\n\t\tpEvent = (rtw_HCI_event *)(&localBuf[0]);\n\n\t\tpEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;\n\t\tpEvent->Data[0] = 0x1;\t/* packet # */\n\t\tpEvent->Data[1] = HCIOPCODELOW(HCI_BT_INFO_NOTIFY, OGF_EXTENSION);\n\t\tpEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_INFO_NOTIFY, OGF_EXTENSION);\n\t\tlen = len + 3;\n\n\t\t/* Return parameters starts from here */\n\t\tpRetPar = &pEvent->Data[len];\n\t\tpRetPar[0] = status;\t\t/* status */\n\n\t\tlen++;\n\t\tpEvent->Length = len;\n\n\t\t/* total tx event length + EventCode length + sizeof(length) */\n\t\ttx_event_length = pEvent->Length + 2;\n#if 0\n\t\trtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, \"BT_info_event\");\n#endif\n\t\tstatus = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);\n\n\t\treturn status;\n\t\t/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */\n\t}\n}\n\nu8 rtw_btcoex_parse_BT_patch_ver_info_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)\n{\n\tRTW_HCI_STATUS status = HCI_STATUS_SUCCESS;\n\tu16\t\tbtPatchVer = 0x0, btHciVer = 0x0;\n\t/* u16\t\t*pU2tmp; */\n\n\tu8 localBuf[6] = \"\";\n\tu8 *pRetPar;\n\tu8\tlen = 0, tx_event_length = 0;\n\trtw_HCI_event *pEvent;\n\n\tbtHciVer = pcmd[0] | pcmd[1] << 8;\n\tbtPatchVer = pcmd[2] | pcmd[3] << 8;\n\n\n\tRTW_INFO(\"%s, cmd:%02x %02x %02x %02x\\n\", __func__, pcmd[0] , pcmd[1] , pcmd[2] , pcmd[3]);\n\tRTW_INFO(\"%s, HCI Ver:%d, Patch Ver:%d\\n\", __func__, btHciVer, btPatchVer);\n\n\trtw_btcoex_SetBtPatchVersion(padapter, btHciVer, btPatchVer);\n\n\n\t/* send complete event to BT */\n\t{\n\t\tpEvent = (rtw_HCI_event *)(&localBuf[0]);\n\n\n\t\tpEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;\n\t\tpEvent->Data[0] = 0x1;\t/* packet # */\n\t\tpEvent->Data[1] = HCIOPCODELOW(HCI_BT_PATCH_VERSION_NOTIFY, OGF_EXTENSION);\n\t\tpEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_PATCH_VERSION_NOTIFY, OGF_EXTENSION);\n\t\tlen = len + 3;\n\n\t\t/* Return parameters starts from here */\n\t\tpRetPar = &pEvent->Data[len];\n\t\tpRetPar[0] = status;\t\t/* status */\n\n\t\tlen++;\n\t\tpEvent->Length = len;\n\n\t\t/* total tx event length + EventCode length + sizeof(length) */\n\t\ttx_event_length = pEvent->Length + 2;\n#if 0\n\t\trtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, \"BT_patch_event\");\n#endif\n\t\tstatus = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);\n\t\treturn status;\n\t\t/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */\n\t}\n}\n\nu8 rtw_btcoex_parse_HCI_Ver_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)\n{\n\tRTW_HCI_STATUS status = HCI_STATUS_SUCCESS;\n\tu16 hciver = pcmd[0] | pcmd[1] << 8;\n\n\tu8 localBuf[6] = \"\";\n\tu8 *pRetPar;\n\tu8\tlen = 0, tx_event_length = 0;\n\trtw_HCI_event *pEvent;\n\n\tstruct bt_coex_info *pcoex_info = &padapter->coex_info;\n\tPBT_MGNT\tpBtMgnt = &pcoex_info->BtMgnt;\n\tpBtMgnt->ExtConfig.HCIExtensionVer = hciver;\n\tRTW_INFO(\"%s, HCI Version: %d\\n\", __func__, pBtMgnt->ExtConfig.HCIExtensionVer);\n\tif (pBtMgnt->ExtConfig.HCIExtensionVer  < 4) {\n\t\tstatus = HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE;\n\t\tRTW_INFO(\"%s, Version = %d, HCI Version < 4\\n\", __func__, pBtMgnt->ExtConfig.HCIExtensionVer);\n\t} else\n\t\trtw_btcoex_SetHciVersion(padapter, hciver);\n\t/* send complete event to BT */\n\t{\n\t\tpEvent = (rtw_HCI_event *)(&localBuf[0]);\n\n\n\t\tpEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;\n\t\tpEvent->Data[0] = 0x1;\t/* packet # */\n\t\tpEvent->Data[1] = HCIOPCODELOW(HCI_EXTENSION_VERSION_NOTIFY, OGF_EXTENSION);\n\t\tpEvent->Data[2] = HCIOPCODEHIGHT(HCI_EXTENSION_VERSION_NOTIFY, OGF_EXTENSION);\n\t\tlen = len + 3;\n\n\t\t/* Return parameters starts from here */\n\t\tpRetPar = &pEvent->Data[len];\n\t\tpRetPar[0] = status;\t\t/* status */\n\n\t\tlen++;\n\t\tpEvent->Length = len;\n\n\t\t/* total tx event length + EventCode length + sizeof(length) */\n\t\ttx_event_length = pEvent->Length + 2;\n\n\t\tstatus = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);\n\t\treturn status;\n\t\t/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */\n\t}\n\n}\n\nu8 rtw_btcoex_parse_WIFI_scan_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)\n{\n\tRTW_HCI_STATUS status = HCI_STATUS_SUCCESS;\n\n\tu8 localBuf[6] = \"\";\n\tu8 *pRetPar;\n\tu8\tlen = 0, tx_event_length = 0;\n\trtw_HCI_event *pEvent;\n\n\tstruct bt_coex_info *pcoex_info = &padapter->coex_info;\n\tPBT_MGNT\tpBtMgnt = &pcoex_info->BtMgnt;\n\tpBtMgnt->ExtConfig.bEnableWifiScanNotify = pcmd[0];\n\tRTW_INFO(\"%s, bEnableWifiScanNotify: %d\\n\", __func__, pBtMgnt->ExtConfig.bEnableWifiScanNotify);\n\n\t/* send complete event to BT */\n\t{\n\t\tpEvent = (rtw_HCI_event *)(&localBuf[0]);\n\n\n\t\tpEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;\n\t\tpEvent->Data[0] = 0x1;\t/* packet # */\n\t\tpEvent->Data[1] = HCIOPCODELOW(HCI_ENABLE_WIFI_SCAN_NOTIFY, OGF_EXTENSION);\n\t\tpEvent->Data[2] = HCIOPCODEHIGHT(HCI_ENABLE_WIFI_SCAN_NOTIFY, OGF_EXTENSION);\n\t\tlen = len + 3;\n\n\t\t/* Return parameters starts from here */\n\t\tpRetPar = &pEvent->Data[len];\n\t\tpRetPar[0] = status;\t\t/* status */\n\n\t\tlen++;\n\t\tpEvent->Length = len;\n\n\t\t/* total tx event length + EventCode length + sizeof(length) */\n\t\ttx_event_length = pEvent->Length + 2;\n\n\t\tstatus = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);\n\t\treturn status;\n\t\t/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */\n\t}\n}\n\nu8 rtw_btcoex_parse_HCI_link_status_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)\n{\n\tRTW_HCI_STATUS\tstatus = HCI_STATUS_SUCCESS;\n\tstruct bt_coex_info\t*pcoex_info = &padapter->coex_info;\n\tPBT_MGNT\tpBtMgnt = &pcoex_info->BtMgnt;\n\t/* PBT_DBG\t\tpBtDbg=&padapter->MgntInfo.BtInfo.BtDbg; */\n\tu8\t\ti, numOfHandle = 0, numOfAcl = 0;\n\tu16\t\tconHandle;\n\tu8\t\tbtProfile, btCoreSpec, linkRole;\n\tu8\t\t*pTriple;\n\n\tu8 localBuf[6] = \"\";\n\tu8 *pRetPar;\n\tu8\tlen = 0, tx_event_length = 0;\n\trtw_HCI_event *pEvent;\n\n\t/* pBtDbg->dbgHciInfo.hciCmdCntLinkStatusNotify++; */\n\t/* RT_DISP_DATA(FIOCTL, IOCTL_BT_HCICMD_EXT, \"LinkStatusNotify, Hex Data :\\n\",  */\n\t/*\t\t&pHciCmd->Data[0], pHciCmd->Length); */\n\n\tRTW_INFO(\"BTLinkStatusNotify\\n\");\n\n\t/* Current only RTL8723 support this command. */\n\t/* pBtMgnt->bSupportProfile = TRUE; */\n\tpBtMgnt->bSupportProfile = _FALSE;\n\n\tpBtMgnt->ExtConfig.NumberOfACL = 0;\n\tpBtMgnt->ExtConfig.NumberOfSCO = 0;\n\n\tnumOfHandle = pcmd[0];\n\t/* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, (\"numOfHandle = 0x%x\\n\", numOfHandle)); */\n\t/* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, (\"HCIExtensionVer = %d\\n\", pBtMgnt->ExtConfig.HCIExtensionVer)); */\n\tRTW_INFO(\"numOfHandle = 0x%x\\n\", numOfHandle);\n\tRTW_INFO(\"HCIExtensionVer = %d\\n\", pBtMgnt->ExtConfig.HCIExtensionVer);\n\n\tpTriple = &pcmd[1];\n\tfor (i = 0; i < numOfHandle; i++) {\n\t\tif (pBtMgnt->ExtConfig.HCIExtensionVer < 1) {\n\t\t\tconHandle = *((u8 *)&pTriple[0]);\n\t\t\tbtProfile = pTriple[2];\n\t\t\tbtCoreSpec = pTriple[3];\n\t\t\tif (BT_PROFILE_SCO == btProfile)\n\t\t\t\tpBtMgnt->ExtConfig.NumberOfSCO++;\n\t\t\telse {\n\t\t\t\tpBtMgnt->ExtConfig.NumberOfACL++;\n\t\t\t\tpBtMgnt->ExtConfig.aclLink[i].ConnectHandle = conHandle;\n\t\t\t\tpBtMgnt->ExtConfig.aclLink[i].BTProfile = btProfile;\n\t\t\t\tpBtMgnt->ExtConfig.aclLink[i].BTCoreSpec = btCoreSpec;\n\t\t\t}\n\t\t\t/* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, */\n\t\t\t/*\t(\"Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d\\n\", */\n\t\t\t/*\t\tconHandle, btProfile, btCoreSpec)); */\n\t\t\tRTW_INFO(\"Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d\\n\", conHandle, btProfile, btCoreSpec);\n\t\t\tpTriple += 4;\n\t\t} else if (pBtMgnt->ExtConfig.HCIExtensionVer >= 1) {\n\t\t\tconHandle = *((u16 *)&pTriple[0]);\n\t\t\tbtProfile = pTriple[2];\n\t\t\tbtCoreSpec = pTriple[3];\n\t\t\tlinkRole = pTriple[4];\n\t\t\tif (BT_PROFILE_SCO == btProfile)\n\t\t\t\tpBtMgnt->ExtConfig.NumberOfSCO++;\n\t\t\telse {\n\t\t\t\tpBtMgnt->ExtConfig.NumberOfACL++;\n\t\t\t\tpBtMgnt->ExtConfig.aclLink[i].ConnectHandle = conHandle;\n\t\t\t\tpBtMgnt->ExtConfig.aclLink[i].BTProfile = btProfile;\n\t\t\t\tpBtMgnt->ExtConfig.aclLink[i].BTCoreSpec = btCoreSpec;\n\t\t\t\tpBtMgnt->ExtConfig.aclLink[i].linkRole = linkRole;\n\t\t\t}\n\t\t\t/* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, */\n\t\t\tRTW_INFO(\"Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d, LinkRole=%d\\n\",\n\t\t\t\t conHandle, btProfile, btCoreSpec, linkRole);\n\t\t\tpTriple += 5;\n\t\t}\n\t}\n\trtw_btcoex_StackUpdateProfileInfo();\n\n\t/* send complete event to BT */\n\t{\n\t\tpEvent = (rtw_HCI_event *)(&localBuf[0]);\n\n\n\t\tpEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;\n\t\tpEvent->Data[0] = 0x1;\t/* packet # */\n\t\tpEvent->Data[1] = HCIOPCODELOW(HCI_LINK_STATUS_NOTIFY, OGF_EXTENSION);\n\t\tpEvent->Data[2] = HCIOPCODEHIGHT(HCI_LINK_STATUS_NOTIFY, OGF_EXTENSION);\n\t\tlen = len + 3;\n\n\t\t/* Return parameters starts from here */\n\t\tpRetPar = &pEvent->Data[len];\n\t\tpRetPar[0] = status;\t\t/* status */\n\n\t\tlen++;\n\t\tpEvent->Length = len;\n\n\t\t/* total tx event length + EventCode length + sizeof(length) */\n\t\ttx_event_length = pEvent->Length + 2;\n\n\t\tstatus = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);\n\t\treturn status;\n\t\t/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */\n\t}\n\n\n}\n\nu8 rtw_btcoex_parse_HCI_BT_coex_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)\n{\n\tu8 localBuf[6] = \"\";\n\tu8 *pRetPar;\n\tu8\tlen = 0, tx_event_length = 0;\n\trtw_HCI_event *pEvent;\n\tRTW_HCI_STATUS\tstatus = HCI_STATUS_SUCCESS;\n\n\t{\n\t\tpEvent = (rtw_HCI_event *)(&localBuf[0]);\n\n\n\t\tpEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;\n\t\tpEvent->Data[0] = 0x1;\t/* packet # */\n\t\tpEvent->Data[1] = HCIOPCODELOW(HCI_BT_COEX_NOTIFY, OGF_EXTENSION);\n\t\tpEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_COEX_NOTIFY, OGF_EXTENSION);\n\t\tlen = len + 3;\n\n\t\t/* Return parameters starts from here */\n\t\tpRetPar = &pEvent->Data[len];\n\t\tpRetPar[0] = status;\t\t/* status */\n\n\t\tlen++;\n\t\tpEvent->Length = len;\n\n\t\t/* total tx event length + EventCode length + sizeof(length) */\n\t\ttx_event_length = pEvent->Length + 2;\n\n\t\tstatus = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);\n\t\treturn status;\n\t\t/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */\n\t}\n}\n\nu8 rtw_btcoex_parse_HCI_BT_operation_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)\n{\n\tu8 localBuf[6] = \"\";\n\tu8 *pRetPar;\n\tu8\tlen = 0, tx_event_length = 0;\n\trtw_HCI_event *pEvent;\n\tRTW_HCI_STATUS\tstatus = HCI_STATUS_SUCCESS;\n\n\tRTW_INFO(\"%s, OP code: %d\\n\", __func__, pcmd[0]);\n\n\tswitch (pcmd[0]) {\n\tcase HCI_BT_OP_NONE:\n\t\tRTW_INFO(\"[bt operation] : Operation None!!\\n\");\n\t\tbreak;\n\tcase HCI_BT_OP_INQUIRY_START:\n\t\tRTW_INFO(\"[bt operation] : Inquiry start!!\\n\");\n\t\tbreak;\n\tcase HCI_BT_OP_INQUIRY_FINISH:\n\t\tRTW_INFO(\"[bt operation] : Inquiry finished!!\\n\");\n\t\tbreak;\n\tcase HCI_BT_OP_PAGING_START:\n\t\tRTW_INFO(\"[bt operation] : Paging is started!!\\n\");\n\t\tbreak;\n\tcase HCI_BT_OP_PAGING_SUCCESS:\n\t\tRTW_INFO(\"[bt operation] : Paging complete successfully!!\\n\");\n\t\tbreak;\n\tcase HCI_BT_OP_PAGING_UNSUCCESS:\n\t\tRTW_INFO(\"[bt operation] : Paging complete unsuccessfully!!\\n\");\n\t\tbreak;\n\tcase HCI_BT_OP_PAIRING_START:\n\t\tRTW_INFO(\"[bt operation] : Pairing start!!\\n\");\n\t\tbreak;\n\tcase HCI_BT_OP_PAIRING_FINISH:\n\t\tRTW_INFO(\"[bt operation] : Pairing finished!!\\n\");\n\t\tbreak;\n\tcase HCI_BT_OP_BT_DEV_ENABLE:\n\t\tRTW_INFO(\"[bt operation] : BT Device is enabled!!\\n\");\n\t\tbreak;\n\tcase HCI_BT_OP_BT_DEV_DISABLE:\n\t\tRTW_INFO(\"[bt operation] : BT Device is disabled!!\\n\");\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(\"[bt operation] : Unknown, error!!\\n\");\n\t\tbreak;\n\t}\n\n\t/* send complete event to BT */\n\t{\n\t\tpEvent = (rtw_HCI_event *)(&localBuf[0]);\n\n\n\t\tpEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;\n\t\tpEvent->Data[0] = 0x1;\t/* packet # */\n\t\tpEvent->Data[1] = HCIOPCODELOW(HCI_BT_OPERATION_NOTIFY, OGF_EXTENSION);\n\t\tpEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_OPERATION_NOTIFY, OGF_EXTENSION);\n\t\tlen = len + 3;\n\n\t\t/* Return parameters starts from here */\n\t\tpRetPar = &pEvent->Data[len];\n\t\tpRetPar[0] = status;\t\t/* status */\n\n\t\tlen++;\n\t\tpEvent->Length = len;\n\n\t\t/* total tx event length + EventCode length + sizeof(length) */\n\t\ttx_event_length = pEvent->Length + 2;\n\n\t\tstatus = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);\n\t\treturn status;\n\t\t/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */\n\t}\n}\n\nu8 rtw_btcoex_parse_BT_AFH_MAP_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)\n{\n\tu8 localBuf[6] = \"\";\n\tu8 *pRetPar;\n\tu8\tlen = 0, tx_event_length = 0;\n\trtw_HCI_event *pEvent;\n\tRTW_HCI_STATUS\tstatus = HCI_STATUS_SUCCESS;\n\n\t{\n\t\tpEvent = (rtw_HCI_event *)(&localBuf[0]);\n\n\n\t\tpEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;\n\t\tpEvent->Data[0] = 0x1;\t/* packet # */\n\t\tpEvent->Data[1] = HCIOPCODELOW(HCI_BT_AFH_MAP_NOTIFY, OGF_EXTENSION);\n\t\tpEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_AFH_MAP_NOTIFY, OGF_EXTENSION);\n\t\tlen = len + 3;\n\n\t\t/* Return parameters starts from here */\n\t\tpRetPar = &pEvent->Data[len];\n\t\tpRetPar[0] = status;\t\t/* status */\n\n\t\tlen++;\n\t\tpEvent->Length = len;\n\n\t\t/* total tx event length + EventCode length + sizeof(length) */\n\t\ttx_event_length = pEvent->Length + 2;\n\n\t\tstatus = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);\n\t\treturn status;\n\t\t/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */\n\t}\n}\n\nu8 rtw_btcoex_parse_BT_register_val_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)\n{\n\n\tu8 localBuf[6] = \"\";\n\tu8 *pRetPar;\n\tu8\tlen = 0, tx_event_length = 0;\n\trtw_HCI_event *pEvent;\n\tRTW_HCI_STATUS\tstatus = HCI_STATUS_SUCCESS;\n\n\t{\n\t\tpEvent = (rtw_HCI_event *)(&localBuf[0]);\n\n\n\t\tpEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;\n\t\tpEvent->Data[0] = 0x1;\t/* packet # */\n\t\tpEvent->Data[1] = HCIOPCODELOW(HCI_BT_REGISTER_VALUE_NOTIFY, OGF_EXTENSION);\n\t\tpEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_REGISTER_VALUE_NOTIFY, OGF_EXTENSION);\n\t\tlen = len + 3;\n\n\t\t/* Return parameters starts from here */\n\t\tpRetPar = &pEvent->Data[len];\n\t\tpRetPar[0] = status;\t\t/* status */\n\n\t\tlen++;\n\t\tpEvent->Length = len;\n\n\t\t/* total tx event length + EventCode length + sizeof(length) */\n\t\ttx_event_length = pEvent->Length + 2;\n\n\t\tstatus = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);\n\t\treturn status;\n\t\t/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */\n\t}\n}\n\nu8 rtw_btcoex_parse_HCI_BT_abnormal_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)\n{\n\tu8 localBuf[6] = \"\";\n\tu8 *pRetPar;\n\tu8\tlen = 0, tx_event_length = 0;\n\trtw_HCI_event *pEvent;\n\tRTW_HCI_STATUS\tstatus = HCI_STATUS_SUCCESS;\n\n\t{\n\t\tpEvent = (rtw_HCI_event *)(&localBuf[0]);\n\n\n\t\tpEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;\n\t\tpEvent->Data[0] = 0x1;\t/* packet # */\n\t\tpEvent->Data[1] = HCIOPCODELOW(HCI_BT_ABNORMAL_NOTIFY, OGF_EXTENSION);\n\t\tpEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_ABNORMAL_NOTIFY, OGF_EXTENSION);\n\t\tlen = len + 3;\n\n\t\t/* Return parameters starts from here */\n\t\tpRetPar = &pEvent->Data[len];\n\t\tpRetPar[0] = status;\t\t/* status */\n\n\t\tlen++;\n\t\tpEvent->Length = len;\n\n\t\t/* total tx event length + EventCode length + sizeof(length) */\n\t\ttx_event_length = pEvent->Length + 2;\n\n\t\tstatus = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);\n\t\treturn status;\n\t\t/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */\n\t}\n}\n\nu8 rtw_btcoex_parse_HCI_query_RF_status_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)\n{\n\tu8 localBuf[6] = \"\";\n\tu8 *pRetPar;\n\tu8\tlen = 0, tx_event_length = 0;\n\trtw_HCI_event *pEvent;\n\tRTW_HCI_STATUS\tstatus = HCI_STATUS_SUCCESS;\n\n\t{\n\t\tpEvent = (rtw_HCI_event *)(&localBuf[0]);\n\n\n\t\tpEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;\n\t\tpEvent->Data[0] = 0x1;\t/* packet # */\n\t\tpEvent->Data[1] = HCIOPCODELOW(HCI_QUERY_RF_STATUS, OGF_EXTENSION);\n\t\tpEvent->Data[2] = HCIOPCODEHIGHT(HCI_QUERY_RF_STATUS, OGF_EXTENSION);\n\t\tlen = len + 3;\n\n\t\t/* Return parameters starts from here */\n\t\tpRetPar = &pEvent->Data[len];\n\t\tpRetPar[0] = status;\t\t/* status */\n\n\t\tlen++;\n\t\tpEvent->Length = len;\n\n\t\t/* total tx event length + EventCode length + sizeof(length) */\n\t\ttx_event_length = pEvent->Length + 2;\n\n\t\tstatus = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);\n\t\treturn status;\n\t\t/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */\n\t}\n}\n\n/*****************************************\n* HCI cmd format :\n*| 15 - 0\t\t\t\t\t\t|\n*| OPcode (OCF|OGF<<10)\t\t|\n*| 15 - 8\t\t|7 - 0\t\t\t|\n*|Cmd para\t|Cmd para Length\t|\n*|Cmd para......\t\t\t\t|\n******************************************/\n\n/* bit 0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15\n *\t |\tOCF\t\t\t             |\t   OGF       | */\nvoid rtw_btcoex_parse_hci_extend_cmd(_adapter *padapter, u8 *pcmd, u16 len, const u16 hci_OCF)\n{\n\n\tRTW_INFO(\"%s: OCF: %x\\n\", __func__, hci_OCF);\n\tswitch (hci_OCF) {\n\tcase HCI_EXTENSION_VERSION_NOTIFY:\n\t\tRTW_INFO(\"HCI_EXTENSION_VERSION_NOTIFY\\n\");\n\t\trtw_btcoex_parse_HCI_Ver_notify_cmd(padapter, pcmd, len);\n\t\tbreak;\n\tcase HCI_LINK_STATUS_NOTIFY:\n\t\tRTW_INFO(\"HCI_LINK_STATUS_NOTIFY\\n\");\n\t\trtw_btcoex_parse_HCI_link_status_notify_cmd(padapter, pcmd, len);\n\t\tbreak;\n\tcase HCI_BT_OPERATION_NOTIFY:\n\t\t/* only for 8723a 2ant */\n\t\tRTW_INFO(\"HCI_BT_OPERATION_NOTIFY\\n\");\n\t\trtw_btcoex_parse_HCI_BT_operation_notify_cmd(padapter, pcmd, len);\n\t\t/*  */\n\t\tbreak;\n\tcase HCI_ENABLE_WIFI_SCAN_NOTIFY:\n\t\tRTW_INFO(\"HCI_ENABLE_WIFI_SCAN_NOTIFY\\n\");\n\t\trtw_btcoex_parse_WIFI_scan_notify_cmd(padapter, pcmd, len);\n\t\tbreak;\n\tcase HCI_QUERY_RF_STATUS:\n\t\t/* only for 8723b 2ant */\n\t\tRTW_INFO(\"HCI_QUERY_RF_STATUS\\n\");\n\t\trtw_btcoex_parse_HCI_query_RF_status_cmd(padapter, pcmd, len);\n\t\tbreak;\n\tcase HCI_BT_ABNORMAL_NOTIFY:\n\t\tRTW_INFO(\"HCI_BT_ABNORMAL_NOTIFY\\n\");\n\t\trtw_btcoex_parse_HCI_BT_abnormal_notify_cmd(padapter, pcmd, len);\n\t\tbreak;\n\tcase HCI_BT_INFO_NOTIFY:\n\t\tRTW_INFO(\"HCI_BT_INFO_NOTIFY\\n\");\n\t\trtw_btcoex_parse_BT_info_notify_cmd(padapter, pcmd, len);\n\t\tbreak;\n\tcase HCI_BT_COEX_NOTIFY:\n\t\tRTW_INFO(\"HCI_BT_COEX_NOTIFY\\n\");\n\t\trtw_btcoex_parse_HCI_BT_coex_notify_cmd(padapter, pcmd, len);\n\t\tbreak;\n\tcase HCI_BT_PATCH_VERSION_NOTIFY:\n\t\tRTW_INFO(\"HCI_BT_PATCH_VERSION_NOTIFY\\n\");\n\t\trtw_btcoex_parse_BT_patch_ver_info_cmd(padapter, pcmd, len);\n\t\tbreak;\n\tcase HCI_BT_AFH_MAP_NOTIFY:\n\t\tRTW_INFO(\"HCI_BT_AFH_MAP_NOTIFY\\n\");\n\t\trtw_btcoex_parse_BT_AFH_MAP_notify_cmd(padapter, pcmd, len);\n\t\tbreak;\n\tcase HCI_BT_REGISTER_VALUE_NOTIFY:\n\t\tRTW_INFO(\"HCI_BT_REGISTER_VALUE_NOTIFY\\n\");\n\t\trtw_btcoex_parse_BT_register_val_notify_cmd(padapter, pcmd, len);\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(\"ERROR!!! Unknown OCF: %x\\n\", hci_OCF);\n\t\tbreak;\n\n\t}\n}\n\nvoid rtw_btcoex_parse_hci_cmd(_adapter *padapter, u8 *pcmd, u16 len)\n{\n\tu16 opcode = pcmd[0] | pcmd[1] << 8;\n\tu16 hci_OGF = HCI_OGF(opcode);\n\tu16 hci_OCF = HCI_OCF(opcode);\n\tu8 cmdlen = len - 3;\n\tu8 pare_len = pcmd[2];\n\n\tRTW_INFO(\"%s OGF: %x,OCF: %x\\n\", __func__, hci_OGF, hci_OCF);\n\tswitch (hci_OGF) {\n\tcase OGF_EXTENSION:\n\t\tRTW_INFO(\"HCI_EXTENSION_CMD_OGF\\n\");\n\t\trtw_btcoex_parse_hci_extend_cmd(padapter, &pcmd[3], cmdlen, hci_OCF);\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(\"Other OGF: %x\\n\", hci_OGF);\n\t\tbreak;\n\t}\n}\n\nu16 rtw_btcoex_parse_recv_data(u8 *msg, u8 msg_size)\n{\n\tu8 cmp_msg1[32] = attend_ack;\n\tu8 cmp_msg2[32] = leave_ack;\n\tu8 cmp_msg3[32] = bt_leave;\n\tu8 cmp_msg4[32] = invite_req;\n\tu8 cmp_msg5[32] = attend_req;\n\tu8 cmp_msg6[32] = invite_rsp;\n\tu8 res = OTHER;\n\n\tif (_rtw_memcmp(cmp_msg1, msg, msg_size) == _TRUE) {\n\t\t/*RTW_INFO(\"%s, msg:%s\\n\",__func__,msg);*/\n\t\tres = RX_ATTEND_ACK;\n\t} else if (_rtw_memcmp(cmp_msg2, msg, msg_size) == _TRUE) {\n\t\t/*RTW_INFO(\"%s, msg:%s\\n\",__func__,msg);*/\n\t\tres = RX_LEAVE_ACK;\n\t} else if (_rtw_memcmp(cmp_msg3, msg, msg_size) == _TRUE) {\n\t\t/*RTW_INFO(\"%s, msg:%s\\n\",__func__,msg);*/\n\t\tres = RX_BT_LEAVE;\n\t} else if (_rtw_memcmp(cmp_msg4, msg, msg_size) == _TRUE) {\n\t\t/*RTW_INFO(\"%s, msg:%s\\n\",__func__,msg);*/\n\t\tres = RX_INVITE_REQ;\n\t} else if (_rtw_memcmp(cmp_msg5, msg, msg_size) == _TRUE)\n\t\tres = RX_ATTEND_REQ;\n\telse if (_rtw_memcmp(cmp_msg6, msg, msg_size) == _TRUE)\n\t\tres = RX_INVITE_RSP;\n\telse {\n\t\t/*RTW_INFO(\"%s, %s\\n\", __func__, msg);*/\n\t\tres = OTHER;\n\t}\n\n\t/*RTW_INFO(\"%s, res:%d\\n\", __func__, res);*/\n\n\treturn res;\n}\n\nvoid rtw_btcoex_recvmsgbysocket(void *data)\n{\n\tu8 recv_data[255];\n\tu8 tx_msg[255] = leave_ack;\n\tu32 len = 0;\n\tu16 recv_length = 0;\n\tu16 parse_res = 0;\n#if 0\n\tu8 para_len = 0, polling_enable = 0, poling_interval = 0, reason = 0, btinfo_len = 0;\n\tu8 btinfo[BT_INFO_LEN] = {0};\n#endif\n\n\tstruct bt_coex_info *pcoex_info = NULL;\n\tstruct sock *sk = NULL;\n\tstruct sk_buff *skb = NULL;\n\n\t/*RTW_INFO(\"%s\\n\",__func__);*/\n\n\tif (pbtcoexadapter == NULL) {\n\t\tRTW_INFO(\"%s: btcoexadapter NULL!\\n\", __func__);\n\t\treturn;\n\t}\n\n\tpcoex_info = &pbtcoexadapter->coex_info;\n\tsk = pcoex_info->sk_store;\n\n\tif (sk == NULL) {\n\t\tRTW_INFO(\"%s: critical error when receive socket data!\\n\", __func__);\n\t\treturn;\n\t}\n\n\tlen = skb_queue_len(&sk->sk_receive_queue);\n\twhile (len > 0) {\n\t\tskb = skb_dequeue(&sk->sk_receive_queue);\n\n\t\t/*important: cut the udp header from skb->data! header length is 8 byte*/\n\t\trecv_length = skb->len - 8;\n\t\t_rtw_memset(recv_data, 0, sizeof(recv_data));\n\t\t_rtw_memcpy(recv_data, skb->data + 8, recv_length);\n\n\t\tparse_res = rtw_btcoex_parse_recv_data(recv_data, recv_length);\n#if 0\n\t\tif (RX_ATTEND_ACK == parse_res) {\n\t\t\t/* attend ack */\n\t\t\tpcoex_info->BT_attend = _TRUE;\n\t\t\tRTW_INFO(\"RX_ATTEND_ACK!,sock_open:%d, BT_attend:%d\\n\", pcoex_info->sock_open, pcoex_info->BT_attend);\n\t\t} else if (RX_ATTEND_REQ == parse_res) {\n\t\t\t/* attend req from BT */\n\t\t\tpcoex_info->BT_attend = _TRUE;\n\t\t\tRTW_INFO(\"RX_BT_ATTEND_REQ!,sock_open:%d, BT_attend:%d\\n\", pcoex_info->sock_open, pcoex_info->BT_attend);\n\t\t\trtw_btcoex_sendmsgbysocket(pbtcoexadapter, attend_ack, sizeof(attend_ack), _FALSE);\n\t\t} else if (RX_INVITE_REQ == parse_res) {\n\t\t\t/* invite req from BT */\n\t\t\tpcoex_info->BT_attend = _TRUE;\n\t\t\tRTW_INFO(\"RX_INVITE_REQ!,sock_open:%d, BT_attend:%d\\n\", pcoex_info->sock_open, pcoex_info->BT_attend);\n\t\t\trtw_btcoex_sendmsgbysocket(pbtcoexadapter, invite_rsp, sizeof(invite_rsp), _FALSE);\n\t\t} else if (RX_INVITE_RSP == parse_res) {\n\t\t\t/* invite rsp */\n\t\t\tpcoex_info->BT_attend = _TRUE;\n\t\t\tRTW_INFO(\"RX_INVITE_RSP!,sock_open:%d, BT_attend:%d\\n\", pcoex_info->sock_open, pcoex_info->BT_attend);\n\t\t} else if (RX_LEAVE_ACK == parse_res) {\n\t\t\t/* mean BT know wifi  will leave */\n\t\t\tpcoex_info->BT_attend = _FALSE;\n\t\t\tRTW_INFO(\"RX_LEAVE_ACK!,sock_open:%d, BT_attend:%d\\n\", pcoex_info->sock_open, pcoex_info->BT_attend);\n\t\t} else if (RX_BT_LEAVE == parse_res) {\n\t\t\t/* BT leave */\n\t\t\trtw_btcoex_sendmsgbysocket(pbtcoexadapter, leave_ack, sizeof(leave_ack), _FALSE); /*  no ack */\n\t\t\tpcoex_info->BT_attend = _FALSE;\n\t\t\tRTW_INFO(\"RX_BT_LEAVE!sock_open:%d, BT_attend:%d\\n\", pcoex_info->sock_open, pcoex_info->BT_attend);\n\t\t} else {\n\t\t\t/* todo: check if recv data are really hci cmds */\n\t\t\tif (_TRUE == pcoex_info->BT_attend)\n\t\t\t\trtw_btcoex_parse_hci_cmd(pbtcoexadapter, recv_data, recv_length);\n\t\t}\n#endif\n\t\tswitch (parse_res) {\n\t\tcase RX_ATTEND_ACK:\n\t\t\t/* attend ack */\n\t\t\tpcoex_info->BT_attend = _TRUE;\n\t\t\tRTW_INFO(\"RX_ATTEND_ACK!,sock_open:%d, BT_attend:%d\\n\", pcoex_info->sock_open, pcoex_info->BT_attend);\n\t\t\trtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);\n\t\t\tbreak;\n\n\t\tcase RX_ATTEND_REQ:\n\t\t\tpcoex_info->BT_attend = _TRUE;\n\t\t\tRTW_INFO(\"RX_BT_ATTEND_REQ!,sock_open:%d, BT_attend:%d\\n\", pcoex_info->sock_open, pcoex_info->BT_attend);\n\t\t\trtw_btcoex_sendmsgbysocket(pbtcoexadapter, attend_ack, sizeof(attend_ack), _FALSE);\n\t\t\trtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);\n\t\t\tbreak;\n\n\t\tcase RX_INVITE_REQ:\n\t\t\t/* invite req from BT */\n\t\t\tpcoex_info->BT_attend = _TRUE;\n\t\t\tRTW_INFO(\"RX_INVITE_REQ!,sock_open:%d, BT_attend:%d\\n\", pcoex_info->sock_open, pcoex_info->BT_attend);\n\t\t\trtw_btcoex_sendmsgbysocket(pbtcoexadapter, invite_rsp, sizeof(invite_rsp), _FALSE);\n\t\t\trtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);\n\t\t\tbreak;\n\n\t\tcase RX_INVITE_RSP:\n\t\t\t/*invite rsp*/\n\t\t\tpcoex_info->BT_attend = _TRUE;\n\t\t\tRTW_INFO(\"RX_INVITE_RSP!,sock_open:%d, BT_attend:%d\\n\", pcoex_info->sock_open, pcoex_info->BT_attend);\n\t\t\trtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);\n\t\t\tbreak;\n\n\t\tcase RX_LEAVE_ACK:\n\t\t\t/* mean BT know wifi  will leave */\n\t\t\tpcoex_info->BT_attend = _FALSE;\n\t\t\tRTW_INFO(\"RX_LEAVE_ACK!,sock_open:%d, BT_attend:%d\\n\", pcoex_info->sock_open, pcoex_info->BT_attend);\n\t\t\trtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);\n\t\t\tbreak;\n\n\t\tcase RX_BT_LEAVE:\n\t\t\t/* BT leave */\n\t\t\trtw_btcoex_sendmsgbysocket(pbtcoexadapter, leave_ack, sizeof(leave_ack), _FALSE); /* no ack */\n\t\t\tpcoex_info->BT_attend = _FALSE;\n\t\t\tRTW_INFO(\"RX_BT_LEAVE!sock_open:%d, BT_attend:%d\\n\", pcoex_info->sock_open, pcoex_info->BT_attend);\n\t\t\trtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tif (_TRUE == pcoex_info->BT_attend)\n\t\t\t\trtw_btcoex_parse_hci_cmd(pbtcoexadapter, recv_data, recv_length);\n\t\t\telse\n\t\t\t\tRTW_INFO(\"ERROR!! BT is UP\\n\");\n\t\t\tbreak;\n\n\t\t}\n\n\t\tlen--;\n\t\tkfree_skb(skb);\n\t}\n}\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0))\n\tvoid rtw_btcoex_recvmsg_init(struct sock *sk_in, s32 bytes)\n#else\n\tvoid rtw_btcoex_recvmsg_init(struct sock *sk_in)\n#endif\n{\n\tstruct bt_coex_info *pcoex_info = NULL;\n\n\tif (pbtcoexadapter == NULL) {\n\t\tRTW_INFO(\"%s: btcoexadapter NULL\\n\", __func__);\n\t\treturn;\n\t}\n\tpcoex_info = &pbtcoexadapter->coex_info;\n\tpcoex_info->sk_store = sk_in;\n\tif (pcoex_info->btcoex_wq != NULL)\n\t\tqueue_delayed_work(pcoex_info->btcoex_wq, &pcoex_info->recvmsg_work, 0);\n\telse\n\t\tRTW_INFO(\"%s: BTCOEX workqueue NULL\\n\", __func__);\n}\n\nu8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool force)\n{\n\tu8 error;\n\tstruct msghdr\tudpmsg;\n\tmm_segment_t\toldfs;\n\tstruct iovec\tiov;\n\tstruct bt_coex_info *pcoex_info = &padapter->coex_info;\n\n\t/* RTW_INFO(\"%s: msg:%s, force:%s\\n\", __func__, msg, force == _TRUE?\"TRUE\":\"FALSE\"); */\n\tif (_FALSE == force) {\n\t\tif (_FALSE == pcoex_info->BT_attend) {\n\t\t\tRTW_INFO(\"TX Blocked: WiFi-BT disconnected\\n\");\n\t\t\treturn _FAIL;\n\t\t}\n\t}\n\n\tiov.iov_base\t = (void *)msg;\n\tiov.iov_len\t = msg_size;\n\tudpmsg.msg_name\t = &pcoex_info->bt_sockaddr;\n\tudpmsg.msg_namelen\t= sizeof(struct sockaddr_in);\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))\n\t/* referece:sock_xmit in kernel code\n\t * WRITE for sock_sendmsg, READ for sock_recvmsg\n\t * third parameter for msg_iovlen\n\t * last parameter for iov_len\n\t */\n\tiov_iter_init(&udpmsg.msg_iter, WRITE, &iov, 1, msg_size);\n#else\n\tudpmsg.msg_iov\t = &iov;\n\tudpmsg.msg_iovlen\t= 1;\n#endif\n\tudpmsg.msg_control\t= NULL;\n\tudpmsg.msg_controllen = 0;\n\tudpmsg.msg_flags\t= MSG_DONTWAIT | MSG_NOSIGNAL;\n\toldfs = get_fs();\n\tset_fs(KERNEL_DS);\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))\n\terror = sock_sendmsg(pcoex_info->udpsock, &udpmsg);\n#else\n\terror = sock_sendmsg(pcoex_info->udpsock, &udpmsg, msg_size);\n#endif\n\tset_fs(oldfs);\n\tif (error < 0) {\n\t\tRTW_INFO(\"Error when sendimg msg, error:%d\\n\", error);\n\t\treturn _FAIL;\n\t} else\n\t\treturn _SUCCESS;\n}\n\nu8 rtw_btcoex_create_kernel_socket(_adapter *padapter)\n{\n\ts8 kernel_socket_err;\n\tu8 tx_msg[255] = attend_req;\n\tstruct bt_coex_info *pcoex_info = &padapter->coex_info;\n\ts32 sock_reuse = 1;\n\tu8 status = _FAIL;\n\n\tRTW_INFO(\"%s CONNECT_PORT %d\\n\", __func__, CONNECT_PORT);\n\n\tif (NULL == pcoex_info) {\n\t\tRTW_INFO(\"coex_info: NULL\\n\");\n\t\tstatus =  _FAIL;\n\t}\n\n\tkernel_socket_err = sock_create(PF_INET, SOCK_DGRAM, 0, &pcoex_info->udpsock);\n\n\tif (kernel_socket_err < 0) {\n\t\tRTW_INFO(\"Error during creation of socket error:%d\\n\", kernel_socket_err);\n\t\tstatus = _FAIL;\n\t} else {\n\t\t_rtw_memset(&(pcoex_info->wifi_sockaddr), 0, sizeof(pcoex_info->wifi_sockaddr));\n\t\tpcoex_info->wifi_sockaddr.sin_family = AF_INET;\n\t\tpcoex_info->wifi_sockaddr.sin_port = htons(CONNECT_PORT);\n\t\tpcoex_info->wifi_sockaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);\n\n\t\t_rtw_memset(&(pcoex_info->bt_sockaddr), 0, sizeof(pcoex_info->bt_sockaddr));\n\t\tpcoex_info->bt_sockaddr.sin_family = AF_INET;\n\t\tpcoex_info->bt_sockaddr.sin_port = htons(CONNECT_PORT_BT);\n\t\tpcoex_info->bt_sockaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);\n\n\t\tpcoex_info->sk_store = NULL;\n\t\tkernel_socket_err = pcoex_info->udpsock->ops->bind(pcoex_info->udpsock, (struct sockaddr *)&pcoex_info->wifi_sockaddr,\n\t\t\t\t    sizeof(pcoex_info->wifi_sockaddr));\n\t\tif (kernel_socket_err == 0) {\n\t\t\tRTW_INFO(\"binding socket success\\n\");\n\t\t\tpcoex_info->udpsock->sk->sk_data_ready = rtw_btcoex_recvmsg_init;\n\t\t\tpcoex_info->sock_open |=  KERNEL_SOCKET_OK;\n\t\t\tpcoex_info->BT_attend = _FALSE;\n\t\t\tRTW_INFO(\"WIFI sending attend_req\\n\");\n\t\t\trtw_btcoex_sendmsgbysocket(padapter, attend_req, sizeof(attend_req), _TRUE);\n\t\t\tstatus = _SUCCESS;\n\t\t} else {\n\t\t\tpcoex_info->BT_attend = _FALSE;\n\t\t\tsock_release(pcoex_info->udpsock); /* bind fail release socket */\n\t\t\tRTW_INFO(\"Error binding socket: %d\\n\", kernel_socket_err);\n\t\t\tstatus = _FAIL;\n\t\t}\n\n\t}\n\n\treturn status;\n}\n\nvoid rtw_btcoex_close_kernel_socket(_adapter *padapter)\n{\n\tstruct bt_coex_info *pcoex_info = &padapter->coex_info;\n\tif (pcoex_info->sock_open & KERNEL_SOCKET_OK) {\n\t\tRTW_INFO(\"release kernel socket\\n\");\n\t\tsock_release(pcoex_info->udpsock);\n\t\tpcoex_info->sock_open &= ~(KERNEL_SOCKET_OK);\n\t\tif (_TRUE == pcoex_info->BT_attend)\n\t\t\tpcoex_info->BT_attend = _FALSE;\n\n\t\tRTW_INFO(\"sock_open:%d, BT_attend:%d\\n\", pcoex_info->sock_open, pcoex_info->BT_attend);\n\t}\n}\n\nvoid rtw_btcoex_init_socket(_adapter *padapter)\n{\n\n\tu8 is_invite = _FALSE;\n\tstruct bt_coex_info *pcoex_info = &padapter->coex_info;\n\tRTW_INFO(\"%s\\n\", __func__);\n\tif (_FALSE == pcoex_info->is_exist) {\n\t\t_rtw_memset(pcoex_info, 0, sizeof(struct bt_coex_info));\n\t\tpcoex_info->btcoex_wq = create_workqueue(\"BTCOEX\");\n\t\tINIT_DELAYED_WORK(&pcoex_info->recvmsg_work,\n\t\t\t\t  (void *)rtw_btcoex_recvmsgbysocket);\n\t\tpbtcoexadapter = padapter;\n\t\t/* We expect BT is off if BT don't send ack to wifi */\n\t\tRTW_INFO(\"We expect BT is off if BT send ack to wifi\\n\");\n\t\trtw_btcoex_pta_off_on_notify(pbtcoexadapter, _FALSE);\n\t\tif (rtw_btcoex_create_kernel_socket(padapter) == _SUCCESS)\n\t\t\tpcoex_info->is_exist = _TRUE;\n\t\telse {\n\t\t\tpcoex_info->is_exist = _FALSE;\n\t\t\tpbtcoexadapter = NULL;\n\t\t}\n\n\t\tRTW_INFO(\"%s: pbtcoexadapter:%p, coex_info->is_exist: %s\\n\"\n\t\t\t, __func__, pbtcoexadapter, pcoex_info->is_exist == _TRUE ? \"TRUE\" : \"FALSE\");\n\t}\n}\n\nvoid rtw_btcoex_close_socket(_adapter *padapter)\n{\n\tstruct bt_coex_info *pcoex_info = &padapter->coex_info;\n\n\tRTW_INFO(\"%s--coex_info->is_exist: %s, pcoex_info->BT_attend:%s\\n\"\n\t\t, __func__, pcoex_info->is_exist == _TRUE ? \"TRUE\" : \"FALSE\", pcoex_info->BT_attend == _TRUE ? \"TRUE\" : \"FALSE\");\n\n\tif (_TRUE == pcoex_info->is_exist) {\n\t\tif (_TRUE == pcoex_info->BT_attend) {\n\t\t\t/*inform BT wifi leave*/\n\t\t\trtw_btcoex_sendmsgbysocket(padapter, wifi_leave, sizeof(wifi_leave), _FALSE);\n\t\t\tmsleep(50);\n\t\t}\n\n\t\tif (pcoex_info->btcoex_wq != NULL) {\n\t\t\tflush_workqueue(pcoex_info->btcoex_wq);\n\t\t\tdestroy_workqueue(pcoex_info->btcoex_wq);\n\t\t}\n\n\t\trtw_btcoex_close_kernel_socket(padapter);\n\t\tpbtcoexadapter = NULL;\n\t\tpcoex_info->is_exist = _FALSE;\n\t}\n}\n\nvoid rtw_btcoex_dump_tx_msg(u8 *tx_msg, u8 len, u8 *msg_name)\n{\n\tu8\ti = 0;\n\tRTW_INFO(\"======> Msg name: %s\\n\", msg_name);\n\tfor (i = 0; i < len; i++)\n\t\tprintk(\"%02x \", tx_msg[i]);\n\tprintk(\"\\n\");\n\tRTW_INFO(\"Msg name: %s <======\\n\", msg_name);\n}\n\n/* Porting from Windows team */\nvoid rtw_btcoex_SendEventExtBtCoexControl(PADAPTER padapter, u8 bNeedDbgRsp, u8 dataLen, void *pData)\n{\n\tu8\t\t\tlen = 0, tx_event_length = 0;\n\tu8 \t\t\tlocalBuf[32] = \"\";\n\tu8\t\t\t*pRetPar;\n\tu8\t\t\topCode = 0;\n\tu8\t\t\t*pInBuf = (u8 *)pData;\n\tu8\t\t\t*pOpCodeContent;\n\trtw_HCI_event *pEvent;\n\n\topCode = pInBuf[0];\n\n\tRTW_INFO(\"%s, OPCode:%02x\\n\", __func__, opCode);\n\n\tpEvent = (rtw_HCI_event *)(&localBuf[0]);\n\n\t/* len += bthci_ExtensionEventHeaderRtk(&localBuf[0], */\n\t/*\tHCI_EVENT_EXT_BT_COEX_CONTROL); */\n\tpEvent->EventCode = HCI_EVENT_EXTENSION_RTK;\n\tpEvent->Data[0] = HCI_EVENT_EXT_BT_COEX_CONTROL;\t/* extension event code */\n\tlen++;\n\n\t/* Return parameters starts from here */\n\tpRetPar = &pEvent->Data[len];\n\t_rtw_memcpy(&pRetPar[0], pData, dataLen);\n\n\tlen += dataLen;\n\n\tpEvent->Length = len;\n\n\t/* total tx event length + EventCode length + sizeof(length) */\n\ttx_event_length = pEvent->Length + 2;\n#if 0\n\trtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, \"BT COEX CONTROL\", _FALSE);\n#endif\n\trtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);\n\n}\n\n/* Porting from Windows team */\nvoid rtw_btcoex_SendEventExtBtInfoControl(PADAPTER padapter, u8 dataLen, void *pData)\n{\n\trtw_HCI_event *pEvent;\n\tu8\t\t\t*pRetPar;\n\tu8\t\t\tlen = 0, tx_event_length = 0;\n\tu8 \t\t\tlocalBuf[32] = \"\";\n\n\tstruct bt_coex_info *pcoex_info = &padapter->coex_info;\n\tPBT_MGNT\t\tpBtMgnt = &pcoex_info->BtMgnt;\n\n\t/* RTW_INFO(\"%s\\n\",__func__);*/\n\tif (pBtMgnt->ExtConfig.HCIExtensionVer < 4) { /* not support */\n\t\tRTW_INFO(\"ERROR: HCIExtensionVer = %d, HCIExtensionVer<4 !!!!\\n\", pBtMgnt->ExtConfig.HCIExtensionVer);\n\t\treturn;\n\t}\n\n\tpEvent = (rtw_HCI_event *)(&localBuf[0]);\n\n\t/* len += bthci_ExtensionEventHeaderRtk(&localBuf[0], */\n\t/*\t\tHCI_EVENT_EXT_BT_INFO_CONTROL); */\n\tpEvent->EventCode = HCI_EVENT_EXTENSION_RTK;\n\tpEvent->Data[0] = HCI_EVENT_EXT_BT_INFO_CONTROL;\t\t/* extension event code */\n\tlen++;\n\n\t/* Return parameters starts from here */\n\tpRetPar = &pEvent->Data[len];\n\t_rtw_memcpy(&pRetPar[0], pData, dataLen);\n\n\tlen += dataLen;\n\n\tpEvent->Length = len;\n\n\t/* total tx event length + EventCode length + sizeof(length) */\n\ttx_event_length = pEvent->Length + 2;\n#if 0\n\trtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, \"BT INFO CONTROL\");\n#endif\n\trtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);\n\n}\n\nvoid rtw_btcoex_SendScanNotify(PADAPTER padapter, u8 scanType)\n{\n\tu8\tlen = 0, tx_event_length = 0;\n\tu8 \tlocalBuf[7] = \"\";\n\tu8\t*pRetPar;\n\tu8\t*pu1Temp;\n\trtw_HCI_event *pEvent;\n\tstruct bt_coex_info *pcoex_info = &padapter->coex_info;\n\tPBT_MGNT\t\tpBtMgnt = &pcoex_info->BtMgnt;\n\n\t/*\tif(!pBtMgnt->BtOperationOn)\n\t *\t\treturn; */\n\n\tpEvent = (rtw_HCI_event *)(&localBuf[0]);\n\n\t/*\tlen += bthci_ExtensionEventHeaderRtk(&localBuf[0],\n\t *\t\t\tHCI_EVENT_EXT_WIFI_SCAN_NOTIFY); */\n\n\tpEvent->EventCode = HCI_EVENT_EXTENSION_RTK;\n\tpEvent->Data[0] = HCI_EVENT_EXT_WIFI_SCAN_NOTIFY;\t\t/* extension event code */\n\tlen++;\n\n\t/* Return parameters starts from here */\n\t/* pRetPar = &PPacketIrpEvent->Data[len]; */\n\t/* pu1Temp = (u8 *)&pRetPar[0]; */\n\t/* *pu1Temp = scanType; */\n\tpEvent->Data[len] = scanType;\n\tlen += 1;\n\n\tpEvent->Length = len;\n\n\t/* total tx event length + EventCode length + sizeof(length) */\n\ttx_event_length = pEvent->Length + 2;\n#if 0\n\trtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, \"WIFI SCAN OPERATION\");\n#endif\n\trtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);\n}\n#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */\n#endif /* CONFIG_BT_COEXIST */\n\nvoid rtw_btcoex_set_ant_info(PADAPTER padapter)\n{\n#ifdef CONFIG_BT_COEXIST\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);\n\n\tif (hal->EEPROMBluetoothCoexist == _TRUE) {\n\t\tu8 bMacPwrCtrlOn = _FALSE;\n\n\t\trtw_btcoex_AntInfoSetting(padapter);\n\t\trtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);\n\t\tif (bMacPwrCtrlOn == _TRUE)\n\t\t\trtw_btcoex_PowerOnSetting(padapter);\n\t}\n\telse\n#endif\n\t\trtw_btcoex_wifionly_AntInfoSetting(padapter);\n}\n\n"
  },
  {
    "path": "core/rtw_btcoex_wifionly.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#include <drv_types.h>\n#include <hal_btcoex_wifionly.h>\n#include <hal_data.h>\n\nvoid rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter)\n{\n\thal_btcoex_wifionly_switchband_notify(padapter);\n}\n\nvoid rtw_btcoex_wifionly_scan_notify(PADAPTER padapter)\n{\n\thal_btcoex_wifionly_scan_notify(padapter);\n}\n\nvoid rtw_btcoex_wifionly_connect_notify(PADAPTER padapter)\n{\n\thal_btcoex_wifionly_connect_notify(padapter);\n}\n\nvoid rtw_btcoex_wifionly_hw_config(PADAPTER padapter)\n{\n\thal_btcoex_wifionly_hw_config(padapter);\n}\n\nvoid rtw_btcoex_wifionly_initialize(PADAPTER padapter)\n{\n\thal_btcoex_wifionly_initlizevariables(padapter);\n}\n\nvoid rtw_btcoex_wifionly_AntInfoSetting(PADAPTER padapter)\n{\n\thal_btcoex_wifionly_AntInfoSetting(padapter);\n}\n"
  },
  {
    "path": "core/rtw_chplan.c",
    "content": "/******************************************************************************\r\n *\r\n * Copyright(c) 2007 - 2018 Realtek Corporation.\r\n *\r\n * This program is free software; you can redistribute it and/or modify it\r\n * under the terms of version 2 of the GNU General Public License as\r\n * published by the Free Software Foundation.\r\n *\r\n * This program is distributed in the hope that it will be useful, but WITHOUT\r\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r\n * more details.\r\n *\r\n *****************************************************************************/\r\n#define _RTW_CHPLAN_C_\r\n\r\n#include <drv_types.h>\r\n\r\n#define RTW_DOMAIN_MAP_VER\t\"41e\"\r\n#define RTW_COUNTRY_MAP_VER\t\"24\"\r\n\r\n#ifdef LEGACY_CHANNEL_PLAN_REF\r\n/********************************************************\r\nChannelPlan definitions\r\n*********************************************************/\r\nstatic RT_CHANNEL_PLAN legacy_channel_plan[] = {\r\n\t/* 0x00, RTW_CHPLAN_FCC */\t\t\t\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 32},\r\n\t/* 0x01, RTW_CHPLAN_IC */\t\t\t\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 31},\r\n\t/* 0x02, RTW_CHPLAN_ETSI */\t\t\t\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 32},\r\n\t/* 0x03, RTW_CHPLAN_SPAIN */\t\t\t\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},\r\n\t/* 0x04, RTW_CHPLAN_FRANCE */\t\t\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},\r\n\t/* 0x05, RTW_CHPLAN_MKK */\t\t\t\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},\r\n\t/* 0x06, RTW_CHPLAN_MKK1 */\t\t\t\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},\r\n\t/* 0x07, RTW_CHPLAN_ISRAEL */\t\t\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64}, 21},\r\n\t/* 0x08, RTW_CHPLAN_TELEC */\t\t\t\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 40, 44, 48, 52, 56, 60, 64}, 22},\r\n\t/* 0x09, RTW_CHPLAN_GLOBAL_DOAMIN */\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14},\r\n\t/* 0x0A, RTW_CHPLAN_WORLD_WIDE_13 */\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},\r\n\t/* 0x0B, RTW_CHPLAN_TAIWAN */\t\t\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 26},\r\n\t/* 0x0C, RTW_CHPLAN_CHINA */\t\t\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 149, 153, 157, 161, 165}, 18},\r\n\t/* 0x0D, RTW_CHPLAN_SINGAPORE_INDIA_MEXICO */\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 24},\r\n\t/* 0x0E, RTW_CHPLAN_KOREA */\t\t\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165}, 31},\r\n\t/* 0x0F, RTW_CHPLAN_TURKEY */\t\t\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64}, 19},\r\n\t/* 0x10, RTW_CHPLAN_JAPAN */\t\t\t\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 32},\r\n\t/* 0x11, RTW_CHPLAN_FCC_NO_DFS */\t\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 149, 153, 157, 161, 165}, 20},\r\n\t/* 0x12, RTW_CHPLAN_JAPAN_NO_DFS */\t\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48}, 17},\r\n\t/* 0x13, RTW_CHPLAN_WORLD_WIDE_5G */\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 37},\r\n\t/* 0x14, RTW_CHPLAN_TAIWAN_NO_DFS */\t\t\t{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 56, 60, 64, 149, 153, 157, 161, 165}, 19},\r\n};\r\n#endif\r\n\r\nenum rtw_rd_2g {\r\n\tRTW_RD_2G_NULL = 0,\r\n\tRTW_RD_2G_WORLD = 1,\t/* Worldwird 13 */\r\n\tRTW_RD_2G_ETSI1 = 2,\t/* Europe */\r\n\tRTW_RD_2G_FCC1 = 3,\t\t/* US */\r\n\tRTW_RD_2G_MKK1 = 4,\t\t/* Japan */\r\n\tRTW_RD_2G_ETSI2 = 5,\t/* France */\r\n\tRTW_RD_2G_GLOBAL = 6,\t/* Global domain */\r\n\tRTW_RD_2G_MKK2 = 7,\t\t/* Japan */\r\n\tRTW_RD_2G_FCC2 = 8,\t\t/* US */\r\n\tRTW_RD_2G_IC1 = 9,\t\t/* Canada */\r\n\tRTW_RD_2G_WORLD1 = 10,\t/* Worldwide 11 */\r\n\tRTW_RD_2G_KCC1 = 11,\t/* Korea */\r\n\tRTW_RD_2G_IC2 = 12,\t\t/* Canada */\r\n\r\n\tRTW_RD_2G_MAX,\r\n};\r\n\r\nenum rtw_rd_5g {\r\n\tRTW_RD_5G_NULL = 0,\t\t/*\t*/\r\n\tRTW_RD_5G_ETSI1 = 1,\t/* Europe */\r\n\tRTW_RD_5G_ETSI2 = 2,\t/* Australia, New Zealand */\r\n\tRTW_RD_5G_ETSI3 = 3,\t/* Russia */\r\n\tRTW_RD_5G_FCC1 = 4,\t\t/* US */\r\n\tRTW_RD_5G_FCC2 = 5,\t\t/* FCC w/o DFS Channels */\r\n\tRTW_RD_5G_FCC3 = 6,\t\t/* Bolivia, Chile, El Salvador, Venezuela */\r\n\tRTW_RD_5G_FCC4 = 7,\t\t/* Venezuela */\r\n\tRTW_RD_5G_FCC5 = 8,\t\t/* China */\r\n\tRTW_RD_5G_FCC6 = 9,\t\t/*\t*/\r\n\tRTW_RD_5G_FCC7 = 10,\t/* US(w/o Weather radar) */\r\n\tRTW_RD_5G_IC1 = 11,\t\t/* Canada(w/o Weather radar) */\r\n\tRTW_RD_5G_KCC1 = 12,\t/* Korea */\r\n\tRTW_RD_5G_MKK1 = 13,\t/* Japan */\r\n\tRTW_RD_5G_MKK2 = 14,\t/* Japan (W52, W53) */\r\n\tRTW_RD_5G_MKK3 = 15,\t/* Japan (W56) */\r\n\tRTW_RD_5G_NCC1 = 16,\t/* Taiwan, (w/o Weather radar) */\r\n\tRTW_RD_5G_NCC2 = 17,\t/* Taiwan, Band2, Band4 */\r\n\tRTW_RD_5G_NCC3 = 18,\t/* Taiwan w/o DFS, Band4 only */\r\n\tRTW_RD_5G_ETSI4 = 19,\t/* Europe w/o DFS, Band1 only */\r\n\tRTW_RD_5G_ETSI5 = 20,\t/* Australia, New Zealand(w/o Weather radar) */\r\n\tRTW_RD_5G_FCC8 = 21,\t/* Latin America */\r\n\tRTW_RD_5G_ETSI6 = 22,\t/* Israel, Bahrain, Egypt, India, China, Malaysia */\r\n\tRTW_RD_5G_ETSI7 = 23,\t/* China */\r\n\tRTW_RD_5G_ETSI8 = 24,\t/* Jordan */\r\n\tRTW_RD_5G_ETSI9 = 25,\t/* Lebanon */\r\n\tRTW_RD_5G_ETSI10 = 26,\t/* Qatar */\r\n\tRTW_RD_5G_ETSI11 = 27,\t/* Russia */\r\n\tRTW_RD_5G_NCC4 = 28,\t/* Taiwan, (w/o Weather radar) */\r\n\tRTW_RD_5G_ETSI12 = 29,\t/* Indonesia */\r\n\tRTW_RD_5G_FCC9 = 30,\t/* (w/o Weather radar) */\r\n\tRTW_RD_5G_ETSI13 = 31,\t/* (w/o Weather radar) */\r\n\tRTW_RD_5G_FCC10 = 32,\t/* Argentina(w/o Weather radar) */\r\n\tRTW_RD_5G_MKK4 = 33,\t/* Japan (W52) */\r\n\tRTW_RD_5G_ETSI14 = 34,\t/* Russia */\r\n\tRTW_RD_5G_FCC11 = 35,\t/* US(include CH144) */\r\n\tRTW_RD_5G_ETSI15 = 36,\t/* Malaysia */\r\n\tRTW_RD_5G_MKK5 = 37,\t/* Japan */\r\n\tRTW_RD_5G_ETSI16 = 38,\t/* Europe */\r\n\tRTW_RD_5G_ETSI17 = 39,\t/* Europe */\r\n\tRTW_RD_5G_FCC12 = 40,\t/* FCC */\r\n\tRTW_RD_5G_FCC13 = 41,\t/* FCC */\r\n\tRTW_RD_5G_FCC14 = 42,\t/* FCC w/o Weather radar(w/o 5600~5650MHz) */\r\n\tRTW_RD_5G_FCC15 = 43,\t/* FCC w/o Band3 */\r\n\tRTW_RD_5G_FCC16 = 44,\t/* FCC w/o Band3 */\r\n\tRTW_RD_5G_ETSI18 = 45,\t/* ETSI w/o DFS Band2&3 */\r\n\tRTW_RD_5G_ETSI19 = 46,\t/* Europe */\r\n\tRTW_RD_5G_FCC17 = 47,\t/* FCC w/o Weather radar(w/o 5600~5650MHz) */\r\n\tRTW_RD_5G_ETSI20 = 48,\t/* Europe */\r\n\tRTW_RD_5G_IC2 = 49,\t\t/* Canada(w/o Weather radar), include ch144 */\r\n\tRTW_RD_5G_ETSI21 = 50,\t/* Australia, New Zealand(w/o Weather radar) */\r\n\tRTW_RD_5G_FCC18 = 51,\t/*  */\r\n\tRTW_RD_5G_WORLD = 52,\t/* Worldwide */\r\n\tRTW_RD_5G_CHILE1 = 53,\t/* Chile */\r\n\tRTW_RD_5G_ACMA1 = 54,\t/* Australia, New Zealand (w/o Weather radar) (w/o Ch120~Ch128) */\r\n\tRTW_RD_5G_WORLD1 = 55,\t/* 5G Worldwide Band1&2 */\r\n\tRTW_RD_5G_CHILE2 = 56,\t/* Chile (Band2,Band3) */\r\n\tRTW_RD_5G_KCC2 = 57,\t/* Korea (New standard) */\r\n\tRTW_RD_5G_KCC3 = 58,\t/* Korea (2018 Dec 05 New standard, include ch144) */\r\n\tRTW_RD_5G_MKK6 = 59,\t/* Japan */\r\n\tRTW_RD_5G_MKK7 = 60,\t/* Japan */\r\n\tRTW_RD_5G_MKK8 = 61,\t/* Japan */\r\n\tRTW_RD_5G_MEX1 = 62,\t/* Mexico */\r\n\tRTW_RD_5G_ETSI22 = 63,\t/* Europe */\r\n\r\n\t/* === Below are driver defined for legacy channel plan compatible, DON'T assign index ==== */\r\n\tRTW_RD_5G_OLD_FCC1,\r\n\tRTW_RD_5G_OLD_NCC1,\r\n\tRTW_RD_5G_OLD_KCC1,\r\n\r\n\tRTW_RD_5G_MAX,\r\n};\r\n\r\nstruct ch_list_t {\r\n\tu8 *len_ch;\r\n};\r\n\r\n#define CH_LIST_ENT(_len, arg...) \\\r\n\t{.len_ch = (u8[_len + 1]) {_len, ##arg}, }\r\n\r\n#define CH_LIST_LEN(_ch_list) (_ch_list.len_ch[0])\r\n#define CH_LIST_CH(_ch_list, _i) (_ch_list.len_ch[_i + 1])\r\n\r\nstruct chplan_ent_t {\r\n\tu8 rd_2g;\r\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\r\n\tu8 rd_5g;\r\n#endif\r\n\tu8 regd; /* value of REGULATION_TXPWR_LMT */\r\n};\r\n\r\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\r\n#define CHPLAN_ENT(i2g, i5g, regd) {i2g, i5g, regd}\r\n#else\r\n#define CHPLAN_ENT(i2g, i5g, regd) {i2g, regd}\r\n#endif\r\n\r\nstatic struct ch_list_t RTW_ChannelPlan2G[] = {\r\n\t/* 0, RTW_RD_2G_NULL */\t\tCH_LIST_ENT(0),\r\n\t/* 1, RTW_RD_2G_WORLD */\tCH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),\r\n\t/* 2, RTW_RD_2G_ETSI1 */\t\tCH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),\r\n\t/* 3, RTW_RD_2G_FCC1 */\t\tCH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11),\r\n\t/* 4, RTW_RD_2G_MKK1 */\t\tCH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14),\r\n\t/* 5, RTW_RD_2G_ETSI2 */\t\tCH_LIST_ENT(4, 10, 11, 12, 13),\r\n\t/* 6, RTW_RD_2G_GLOBAL */\tCH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14),\r\n\t/* 7, RTW_RD_2G_MKK2 */\t\tCH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),\r\n\t/* 8, RTW_RD_2G_FCC2 */\t\tCH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),\r\n\t/* 9, RTW_RD_2G_IC1 */\t\tCH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),\r\n\t/* 10, RTW_RD_2G_WORLD1 */\tCH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11),\r\n\t/* 11, RTW_RD_2G_KCC1 */\tCH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),\r\n\t/* 12, RTW_RD_2G_IC2 */\t\tCH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11),\r\n};\r\n\r\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\r\nstatic struct ch_list_t RTW_ChannelPlan5G[] = {\r\n\t/* 0, RTW_RD_5G_NULL */\t\tCH_LIST_ENT(0),\r\n\t/* 1, RTW_RD_5G_ETSI1 */\t\tCH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140),\r\n\t/* 2, RTW_RD_5G_ETSI2 */\t\tCH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 3, RTW_RD_5G_ETSI3 */\t\tCH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165),\r\n\t/* 4, RTW_RD_5G_FCC1 */\t\tCH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 5, RTW_RD_5G_FCC2 */\t\tCH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165),\r\n\t/* 6, RTW_RD_5G_FCC3 */\t\tCH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165),\r\n\t/* 7, RTW_RD_5G_FCC4 */\t\tCH_LIST_ENT(12, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161),\r\n\t/* 8, RTW_RD_5G_FCC5 */\t\tCH_LIST_ENT(5, 149, 153, 157, 161, 165),\r\n\t/* 9, RTW_RD_5G_FCC6 */\t\tCH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64),\r\n\t/* 10, RTW_RD_5G_FCC7 */\tCH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 11, RTW_RD_5G_IC1 */\t\tCH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 12, RTW_RD_5G_KCC1 */\tCH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161),\r\n\t/* 13, RTW_RD_5G_MKK1 */\tCH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140),\r\n\t/* 14, RTW_RD_5G_MKK2 */\tCH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64),\r\n\t/* 15, RTW_RD_5G_MKK3 */\tCH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140),\r\n\t/* 16, RTW_RD_5G_NCC1 */\tCH_LIST_ENT(16, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 17, RTW_RD_5G_NCC2 */\tCH_LIST_ENT(8, 56, 60, 64, 149, 153, 157, 161, 165),\r\n\t/* 18, RTW_RD_5G_NCC3 */\tCH_LIST_ENT(5, 149, 153, 157, 161, 165),\r\n\t/* 19, RTW_RD_5G_ETSI4 */\tCH_LIST_ENT(4, 36, 40, 44, 48),\r\n\t/* 20, RTW_RD_5G_ETSI5 */\tCH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 21, RTW_RD_5G_FCC8 */\tCH_LIST_ENT(4, 149, 153, 157, 161),\r\n\t/* 22, RTW_RD_5G_ETSI6 */\tCH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64),\r\n\t/* 23, RTW_RD_5G_ETSI7 */\tCH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165),\r\n\t/* 24, RTW_RD_5G_ETSI8 */\tCH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165),\r\n\t/* 25, RTW_RD_5G_ETSI9 */\tCH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140),\r\n\t/* 26, RTW_RD_5G_ETSI10 */\tCH_LIST_ENT(5, 149, 153, 157, 161, 165),\r\n\t/* 27, RTW_RD_5G_ETSI11 */\tCH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 28, RTW_RD_5G_NCC4 */\tCH_LIST_ENT(17, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 29, RTW_RD_5G_ETSI12 */\tCH_LIST_ENT(4, 149, 153, 157, 161),\r\n\t/* 30, RTW_RD_5G_FCC9 */\tCH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 31, RTW_RD_5G_ETSI13 */\tCH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140),\r\n\t/* 32, RTW_RD_5G_FCC10 */\tCH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161),\r\n\t/* 33, RTW_RD_5G_MKK4 */\tCH_LIST_ENT(4, 36, 40, 44, 48),\r\n\t/* 34, RTW_RD_5G_ETSI14 */\tCH_LIST_ENT(11, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140),\r\n\t/* 35, RTW_RD_5G_FCC11 */\tCH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165),\r\n\t/* 36, RTW_RD_5G_ETSI15 */\tCH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 149, 153, 157, 161, 165),\r\n\t/* 37, RTW_RD_5G_MKK5 */\tCH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 38, RTW_RD_5G_ETSI16 */\tCH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 39, RTW_RD_5G_ETSI17 */\tCH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 40, RTW_RD_5G_FCC12*/\tCH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 41, RTW_RD_5G_FCC13 */\tCH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 42, RTW_RD_5G_FCC14 */\tCH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 43, RTW_RD_5G_FCC15 */\tCH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165),\r\n\t/* 44, RTW_RD_5G_FCC16 */\tCH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165),\r\n\t/* 45, RTW_RD_5G_ETSI18 */\tCH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165),\r\n\t/* 46, RTW_RD_5G_ETSI19 */\tCH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 47, RTW_RD_5G_FCC17 */\tCH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140),\r\n\t/* 48, RTW_RD_5G_ETSI20 */\tCH_LIST_ENT(9, 52, 56, 60, 64, 149, 153, 157, 161, 165),\r\n\t/* 49, RTW_RD_5G_IC2 */\t\tCH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 144, 149, 153, 157, 161, 165),\r\n\t/* 50, RTW_RD_5G_ETSI21 */\tCH_LIST_ENT(13, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 51, RTW_RD_5G_FCC18 */\tCH_LIST_ENT(8, 100, 104, 108, 112, 116, 132, 136, 140),\r\n\t/* 52, RTW_RD_5G_WORLD */\tCH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165),\r\n\t/* 53, RTW_RD_5G_CHILE1 */\tCH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165),\r\n\t/* 54, RTW_RD_5G_ACMA1 */\tCH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 55, RTW_RD_5G_WORLD1 */\tCH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64),\r\n\t/* 56, RTW_RD_5G_CHILE2 */\tCH_LIST_ENT(16, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144),\r\n\t/* 57, RTW_RD_5G_KCC2 */\tCH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 58, RTW_RD_5G_KCC3 */\tCH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165),\r\n\t/* 59, RTW_RD_5G_MKK6 */\tCH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 149, 153, 157, 161, 165),\r\n\t/* 60, RTW_RD_5G_MKK7 */\tCH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 61, RTW_RD_5G_MKK8 */\tCH_LIST_ENT(23, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 62, RTW_RD_5G_MEX1 */\tCH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* 63, RTW_RD_5G_ETSI22 */\tCH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),\r\n\r\n\t/* === Below are driver defined for legacy channel plan compatible, NO static index assigned ==== */\r\n\t/* RTW_RD_5G_OLD_FCC1 */\tCH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* RTW_RD_5G_OLD_NCC1 */\tCH_LIST_ENT(15, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165),\r\n\t/* RTW_RD_5G_OLD_KCC1 */\tCH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165),\r\n};\r\n#endif /* CONFIG_IEEE80211_BAND_5GHZ */\r\n\r\nstatic struct chplan_ent_t RTW_ChannelPlanMap[RTW_CHPLAN_MAX] = {\r\n\t/* ===== 0x00 ~ 0x1F, legacy channel plan ===== */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_KCC1,\t\tTXPWR_LMT_FCC),\t\t/* 0x00, RTW_CHPLAN_FCC */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_OLD_FCC1,\tTXPWR_LMT_FCC),\t\t/* 0x01, RTW_CHPLAN_IC */\r\n\tCHPLAN_ENT(RTW_RD_2G_ETSI1,\t\tRTW_RD_5G_ETSI1,\tTXPWR_LMT_ETSI),\t/* 0x02, RTW_CHPLAN_ETSI */\r\n\tCHPLAN_ENT(RTW_RD_2G_ETSI1,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_ETSI),\t/* 0x03, RTW_CHPLAN_SPAIN */\r\n\tCHPLAN_ENT(RTW_RD_2G_ETSI1,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_ETSI),\t/* 0x04, RTW_CHPLAN_FRANCE */\r\n\tCHPLAN_ENT(RTW_RD_2G_MKK1,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_MKK),\t\t/* 0x05, RTW_CHPLAN_MKK */\r\n\tCHPLAN_ENT(RTW_RD_2G_MKK1,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_MKK),\t\t/* 0x06, RTW_CHPLAN_MKK1 */\r\n\tCHPLAN_ENT(RTW_RD_2G_ETSI1,\t\tRTW_RD_5G_FCC6,\t\tTXPWR_LMT_ETSI),\t/* 0x07, RTW_CHPLAN_ISRAEL */\r\n\tCHPLAN_ENT(RTW_RD_2G_MKK1,\t\tRTW_RD_5G_FCC6,\t\tTXPWR_LMT_MKK),\t\t/* 0x08, RTW_CHPLAN_TELEC */\r\n\tCHPLAN_ENT(RTW_RD_2G_MKK1,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_WW),\t\t/* 0x09, RTW_CHPLAN_GLOBAL_DOAMIN */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_WW),\t\t/* 0x0A, RTW_CHPLAN_WORLD_WIDE_13 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_OLD_NCC1,\tTXPWR_LMT_FCC),\t\t/* 0x0B, RTW_CHPLAN_TAIWAN */\r\n\tCHPLAN_ENT(RTW_RD_2G_ETSI1,\t\tRTW_RD_5G_FCC5,\t\tTXPWR_LMT_ETSI),\t/* 0x0C, RTW_CHPLAN_CHINA */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_FCC3,\t\tTXPWR_LMT_WW),\t\t/* 0x0D, RTW_CHPLAN_SINGAPORE_INDIA_MEXICO */ /* ETSI:Singapore, India. FCC:Mexico => WW */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_OLD_KCC1,\tTXPWR_LMT_ETSI),\t/* 0x0E, RTW_CHPLAN_KOREA */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_FCC6,\t\tTXPWR_LMT_ETSI),\t/* 0x0F, RTW_CHPLAN_TURKEY */\r\n\tCHPLAN_ENT(RTW_RD_2G_ETSI1,\t\tRTW_RD_5G_ETSI1,\tTXPWR_LMT_MKK),\t\t/* 0x10, RTW_CHPLAN_JAPAN */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_FCC2,\t\tTXPWR_LMT_FCC),\t\t/* 0x11, RTW_CHPLAN_FCC_NO_DFS */\r\n\tCHPLAN_ENT(RTW_RD_2G_ETSI1,\t\tRTW_RD_5G_FCC7,\t\tTXPWR_LMT_MKK),\t\t/* 0x12, RTW_CHPLAN_JAPAN_NO_DFS */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_FCC1,\t\tTXPWR_LMT_WW),\t\t/* 0x13, RTW_CHPLAN_WORLD_WIDE_5G */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_NCC2,\t\tTXPWR_LMT_FCC),\t\t/* 0x14, RTW_CHPLAN_TAIWAN_NO_DFS */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_FCC7,\t\tTXPWR_LMT_ETSI),\t/* 0x15, RTW_CHPLAN_ETSI_NO_DFS */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_NCC1,\t\tTXPWR_LMT_ETSI),\t/* 0x16, RTW_CHPLAN_KOREA_NO_DFS */\r\n\tCHPLAN_ENT(RTW_RD_2G_MKK1,\t\tRTW_RD_5G_FCC7,\t\tTXPWR_LMT_MKK),\t\t/* 0x17, RTW_CHPLAN_JAPAN_NO_DFS */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_FCC5,\t\tTXPWR_LMT_ETSI),\t/* 0x18, RTW_CHPLAN_PAKISTAN_NO_DFS */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_FCC5,\t\tTXPWR_LMT_FCC),\t\t/* 0x19, RTW_CHPLAN_TAIWAN2_NO_DFS */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_WW),\t\t/* 0x1A, */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_WW),\t\t/* 0x1B, */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_WW),\t\t/* 0x1C, */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_WW),\t\t/* 0x1D, */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_WW),\t\t/* 0x1E, */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_FCC1,\t\tTXPWR_LMT_WW),\t\t/* 0x1F, RTW_CHPLAN_WORLD_WIDE_ONLY_5G */\r\n\r\n\t/* ===== 0x20 ~ 0x7F, new channel plan ===== */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_WW),\t\t/* 0x20, RTW_CHPLAN_WORLD_NULL */\r\n\tCHPLAN_ENT(RTW_RD_2G_ETSI1,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_ETSI),\t/* 0x21, RTW_CHPLAN_ETSI1_NULL */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_FCC),\t\t/* 0x22, RTW_CHPLAN_FCC1_NULL */\r\n\tCHPLAN_ENT(RTW_RD_2G_MKK1,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_MKK),\t\t/* 0x23, RTW_CHPLAN_MKK1_NULL */\r\n\tCHPLAN_ENT(RTW_RD_2G_ETSI2,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_ETSI),\t/* 0x24, RTW_CHPLAN_ETSI2_NULL */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_FCC1,\t\tTXPWR_LMT_FCC),\t\t/* 0x25, RTW_CHPLAN_FCC1_FCC1 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_ETSI1,\tTXPWR_LMT_ETSI),\t/* 0x26, RTW_CHPLAN_WORLD_ETSI1 */\r\n\tCHPLAN_ENT(RTW_RD_2G_MKK1,\t\tRTW_RD_5G_MKK1,\t\tTXPWR_LMT_MKK),\t\t/* 0x27, RTW_CHPLAN_MKK1_MKK1 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_KCC1,\t\tTXPWR_LMT_KCC),\t\t/* 0x28, RTW_CHPLAN_WORLD_KCC1 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_FCC2,\t\tTXPWR_LMT_FCC),\t\t/* 0x29, RTW_CHPLAN_WORLD_FCC2 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC2,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_FCC),\t\t/* 0x2A, RTW_CHPLAN_FCC2_NULL */\r\n\tCHPLAN_ENT(RTW_RD_2G_IC1,\t\tRTW_RD_5G_IC2,\t\tTXPWR_LMT_IC),\t\t/* 0x2B, RTW_CHPLAN_IC1_IC2 */\r\n\tCHPLAN_ENT(RTW_RD_2G_MKK2,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_MKK),\t\t/* 0x2C, RTW_CHPLAN_MKK2_NULL */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_CHILE1,\tTXPWR_LMT_CHILE),\t/* 0x2D, RTW_CHPLAN_WORLD_CHILE1 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD1,\tRTW_RD_5G_WORLD1,\tTXPWR_LMT_WW),\t\t/* 0x2E, RTW_CHPLAN_WORLD1_WORLD1 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_CHILE2,\tTXPWR_LMT_CHILE),\t/* 0x2F, RTW_CHPLAN_WORLD_CHILE2 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_FCC3,\t\tTXPWR_LMT_FCC),\t\t/* 0x30, RTW_CHPLAN_WORLD_FCC3 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_FCC4,\t\tTXPWR_LMT_FCC),\t\t/* 0x31, RTW_CHPLAN_WORLD_FCC4 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_FCC5,\t\tTXPWR_LMT_FCC),\t\t/* 0x32, RTW_CHPLAN_WORLD_FCC5 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_FCC6,\t\tTXPWR_LMT_FCC),\t\t/* 0x33, RTW_CHPLAN_WORLD_FCC6 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_FCC7,\t\tTXPWR_LMT_FCC),\t\t/* 0x34, RTW_CHPLAN_FCC1_FCC7 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_ETSI2,\tTXPWR_LMT_ETSI),\t/* 0x35, RTW_CHPLAN_WORLD_ETSI2 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_ETSI3,\tTXPWR_LMT_ETSI),\t/* 0x36, RTW_CHPLAN_WORLD_ETSI3 */\r\n\tCHPLAN_ENT(RTW_RD_2G_MKK1,\t\tRTW_RD_5G_MKK2,\t\tTXPWR_LMT_MKK),\t\t/* 0x37, RTW_CHPLAN_MKK1_MKK2 */\r\n\tCHPLAN_ENT(RTW_RD_2G_MKK1,\t\tRTW_RD_5G_MKK3,\t\tTXPWR_LMT_MKK),\t\t/* 0x38, RTW_CHPLAN_MKK1_MKK3 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_NCC1,\t\tTXPWR_LMT_FCC),\t\t/* 0x39, RTW_CHPLAN_FCC1_NCC1 */\r\n\tCHPLAN_ENT(RTW_RD_2G_ETSI1,\t\tRTW_RD_5G_ETSI1,\tTXPWR_LMT_ETSI),\t/* 0x3A, RTW_CHPLAN_ETSI1_ETSI1 */\r\n\tCHPLAN_ENT(RTW_RD_2G_ETSI1,\t\tRTW_RD_5G_ACMA1,\tTXPWR_LMT_ACMA),\t/* 0x3B, RTW_CHPLAN_ETSI1_ACMA1 */\r\n\tCHPLAN_ENT(RTW_RD_2G_ETSI1,\t\tRTW_RD_5G_ETSI6,\tTXPWR_LMT_ETSI),\t/* 0x3C, RTW_CHPLAN_ETSI1_ETSI6 */\r\n\tCHPLAN_ENT(RTW_RD_2G_ETSI1,\t\tRTW_RD_5G_ETSI12,\tTXPWR_LMT_ETSI),\t/* 0x3D, RTW_CHPLAN_ETSI1_ETSI12 */\r\n\tCHPLAN_ENT(RTW_RD_2G_KCC1,\t\tRTW_RD_5G_KCC2,\t\tTXPWR_LMT_KCC),\t\t/* 0x3E, RTW_CHPLAN_KCC1_KCC2 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_FCC11,\tTXPWR_LMT_FCC),\t\t/* 0x3F, RTW_CHPLAN_FCC1_FCC11*/\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_NCC2,\t\tTXPWR_LMT_FCC),\t\t/* 0x40, RTW_CHPLAN_FCC1_NCC2 */\r\n\tCHPLAN_ENT(RTW_RD_2G_GLOBAL,\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_WW),\t\t/* 0x41, RTW_CHPLAN_GLOBAL_NULL */\r\n\tCHPLAN_ENT(RTW_RD_2G_ETSI1,\t\tRTW_RD_5G_ETSI4,\tTXPWR_LMT_ETSI),\t/* 0x42, RTW_CHPLAN_ETSI1_ETSI4 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_FCC2,\t\tTXPWR_LMT_FCC),\t\t/* 0x43, RTW_CHPLAN_FCC1_FCC2 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_NCC3,\t\tTXPWR_LMT_FCC),\t\t/* 0x44, RTW_CHPLAN_FCC1_NCC3 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_ACMA1,\tTXPWR_LMT_ACMA),\t/* 0x45, RTW_CHPLAN_WORLD_ACMA1 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_FCC8,\t\tTXPWR_LMT_FCC),\t\t/* 0x46, RTW_CHPLAN_FCC1_FCC8 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_ETSI6,\tTXPWR_LMT_ETSI),\t/* 0x47, RTW_CHPLAN_WORLD_ETSI6 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_ETSI7,\tTXPWR_LMT_ETSI),\t/* 0x48, RTW_CHPLAN_WORLD_ETSI7 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_ETSI8,\tTXPWR_LMT_ETSI),\t/* 0x49, RTW_CHPLAN_WORLD_ETSI8 */\r\n\tCHPLAN_ENT(RTW_RD_2G_IC2,\t\tRTW_RD_5G_IC2,\t\tTXPWR_LMT_IC),\t\t/* 0x4A, RTW_CHPLAN_IC2_IC2 */\r\n\tCHPLAN_ENT(RTW_RD_2G_KCC1,\t\tRTW_RD_5G_KCC3,\t\tTXPWR_LMT_KCC),\t\t/* 0x4B, RTW_CHPLAN_KCC1_KCC3 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_FCC15,\tTXPWR_LMT_FCC),\t\t/* 0x4C, RTW_CHPLAN_FCC1_FCC15 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC2,\t\tRTW_RD_5G_MEX1,\t\tTXPWR_LMT_MEXICO),\t/* 0x4D, RTW_CHPLAN_FCC2_MEX1 */\r\n\tCHPLAN_ENT(RTW_RD_2G_ETSI1,\t\tRTW_RD_5G_ETSI22,\tTXPWR_LMT_ETSI),\t/* 0x4E, RTW_CHPLAN_ETSI1_ETSI22 */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_WW),\t\t/* 0x4F, */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_ETSI9,\tTXPWR_LMT_ETSI),\t/* 0x50, RTW_CHPLAN_WORLD_ETSI9 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_ETSI10,\tTXPWR_LMT_ETSI),\t/* 0x51, RTW_CHPLAN_WORLD_ETSI10 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_ETSI11,\tTXPWR_LMT_ETSI),\t/* 0x52, RTW_CHPLAN_WORLD_ETSI11 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_NCC4,\t\tTXPWR_LMT_FCC),\t\t/* 0x53, RTW_CHPLAN_FCC1_NCC4 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_ETSI12,\tTXPWR_LMT_ETSI),\t/* 0x54, RTW_CHPLAN_WORLD_ETSI12 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_FCC9,\t\tTXPWR_LMT_FCC),\t\t/* 0x55, RTW_CHPLAN_FCC1_FCC9 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_ETSI13,\tTXPWR_LMT_ETSI),\t/* 0x56, RTW_CHPLAN_WORLD_ETSI13 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_FCC10,\tTXPWR_LMT_FCC),\t\t/* 0x57, RTW_CHPLAN_FCC1_FCC10 */\r\n\tCHPLAN_ENT(RTW_RD_2G_MKK2,\t\tRTW_RD_5G_MKK4,\t\tTXPWR_LMT_MKK),\t\t/* 0x58, RTW_CHPLAN_MKK2_MKK4 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_ETSI14,\tTXPWR_LMT_ETSI),\t/* 0x59, RTW_CHPLAN_WORLD_ETSI14 */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_WW),\t\t/* 0x5A, */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_WW),\t\t/* 0x5B, */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_WW),\t\t/* 0x5C, */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_WW),\t\t/* 0x5D, */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_WW),\t\t/* 0x5E, */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_NULL,\t\tTXPWR_LMT_WW),\t\t/* 0x5F, */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_FCC5,\t\tTXPWR_LMT_FCC),\t\t/* 0x60, RTW_CHPLAN_FCC1_FCC5 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC2,\t\tRTW_RD_5G_FCC7,\t\tTXPWR_LMT_FCC),\t\t/* 0x61, RTW_CHPLAN_FCC2_FCC7 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC2,\t\tRTW_RD_5G_FCC1,\t\tTXPWR_LMT_FCC),\t\t/* 0x62, RTW_CHPLAN_FCC2_FCC1 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_ETSI15,\tTXPWR_LMT_ETSI),\t/* 0x63, RTW_CHPLAN_WORLD_ETSI15 */\r\n\tCHPLAN_ENT(RTW_RD_2G_MKK2,\t\tRTW_RD_5G_MKK5,\t\tTXPWR_LMT_MKK),\t\t/* 0x64, RTW_CHPLAN_MKK2_MKK5 */\r\n\tCHPLAN_ENT(RTW_RD_2G_ETSI1,\t\tRTW_RD_5G_ETSI16,\tTXPWR_LMT_ETSI),\t/* 0x65, RTW_CHPLAN_ETSI1_ETSI16 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_FCC14,\tTXPWR_LMT_FCC),\t\t/* 0x66, RTW_CHPLAN_FCC1_FCC14 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_FCC12,\tTXPWR_LMT_FCC),\t\t/* 0x67, RTW_CHPLAN_FCC1_FCC12 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC2,\t\tRTW_RD_5G_FCC14,\tTXPWR_LMT_FCC),\t\t/* 0x68, RTW_CHPLAN_FCC2_FCC14 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC2,\t\tRTW_RD_5G_FCC12,\tTXPWR_LMT_FCC),\t\t/* 0x69, RTW_CHPLAN_FCC2_FCC12 */\r\n\tCHPLAN_ENT(RTW_RD_2G_ETSI1,\t\tRTW_RD_5G_ETSI17,\tTXPWR_LMT_ETSI),\t/* 0x6A, RTW_CHPLAN_ETSI1_ETSI17 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_FCC16,\tTXPWR_LMT_FCC),\t\t/* 0x6B, RTW_CHPLAN_WORLD_FCC16 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_FCC13,\tTXPWR_LMT_FCC),\t\t/* 0x6C, RTW_CHPLAN_WORLD_FCC13 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC2,\t\tRTW_RD_5G_FCC15,\tTXPWR_LMT_FCC),\t\t/* 0x6D, RTW_CHPLAN_FCC2_FCC15 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_FCC12,\tTXPWR_LMT_FCC),\t\t/* 0x6E, RTW_CHPLAN_WORLD_FCC12 */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_ETSI8,\tTXPWR_LMT_ETSI),\t/* 0x6F, RTW_CHPLAN_NULL_ETSI8 */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_ETSI18,\tTXPWR_LMT_ETSI),\t/* 0x70, RTW_CHPLAN_NULL_ETSI18 */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_ETSI17,\tTXPWR_LMT_ETSI),\t/* 0x71, RTW_CHPLAN_NULL_ETSI17 */\r\n\tCHPLAN_ENT(RTW_RD_2G_NULL,\t\tRTW_RD_5G_ETSI19,\tTXPWR_LMT_ETSI),\t/* 0x72, RTW_CHPLAN_NULL_ETSI19 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_FCC7,\t\tTXPWR_LMT_FCC),\t\t/* 0x73, RTW_CHPLAN_WORLD_FCC7 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC2,\t\tRTW_RD_5G_FCC17,\tTXPWR_LMT_FCC),\t\t/* 0x74, RTW_CHPLAN_FCC2_FCC17 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_ETSI20,\tTXPWR_LMT_ETSI),\t/* 0x75, RTW_CHPLAN_WORLD_ETSI20 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC2,\t\tRTW_RD_5G_FCC11,\tTXPWR_LMT_FCC),\t\t/* 0x76, RTW_CHPLAN_FCC2_FCC11 */\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_ETSI21,\tTXPWR_LMT_ETSI),\t/* 0x77, RTW_CHPLAN_WORLD_ETSI21 */\r\n\tCHPLAN_ENT(RTW_RD_2G_FCC1,\t\tRTW_RD_5G_FCC18,\tTXPWR_LMT_FCC),\t\t/* 0x78, RTW_CHPLAN_FCC1_FCC18 */\r\n\tCHPLAN_ENT(RTW_RD_2G_MKK2,\t\tRTW_RD_5G_MKK1,\t\tTXPWR_LMT_MKK),\t\t/* 0x79, RTW_CHPLAN_MKK2_MKK1 */\r\n};\r\n\r\nstatic struct chplan_ent_t RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE =\r\n\tCHPLAN_ENT(RTW_RD_2G_WORLD,\t\tRTW_RD_5G_FCC1,\t\tTXPWR_LMT_FCC);\t\t/* 0x7F, Realtek Define */\r\n\r\nu8 rtw_chplan_get_default_regd(u8 id)\r\n{\r\n\tu8 regd;\r\n\r\n\tif (id == RTW_CHPLAN_REALTEK_DEFINE)\r\n\t\tregd = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.regd;\r\n\telse\r\n\t\tregd = RTW_ChannelPlanMap[id].regd;\r\n\r\n\treturn regd;\r\n}\r\n\r\nbool rtw_chplan_is_empty(u8 id)\r\n{\r\n\tstruct chplan_ent_t *chplan_map;\r\n\r\n\tif (id == RTW_CHPLAN_REALTEK_DEFINE)\r\n\t\tchplan_map = &RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE;\r\n\telse\r\n\t\tchplan_map = &RTW_ChannelPlanMap[id];\r\n\r\n\tif (chplan_map->rd_2g == RTW_RD_2G_NULL\r\n\t\t#ifdef CONFIG_IEEE80211_BAND_5GHZ\r\n\t\t&& chplan_map->rd_5g == RTW_RD_5G_NULL\r\n\t\t#endif\r\n\t)\r\n\t\treturn _TRUE;\r\n\r\n\treturn _FALSE;\r\n}\r\n\r\nbool rtw_regsty_is_excl_chs(struct registry_priv *regsty, u8 ch)\r\n{\r\n\tint i;\r\n\r\n\tfor (i = 0; i < MAX_CHANNEL_NUM; i++) {\r\n\t\tif (regsty->excl_chs[i] == 0)\r\n\t\t\tbreak;\r\n\t\tif (regsty->excl_chs[i] == ch)\r\n\t\t\treturn _TRUE;\r\n\t}\r\n\treturn _FALSE;\r\n}\r\n\r\ninline static u8 rtw_rd_5g_band1_passive(u8 rtw_rd_5g)\r\n{\r\n\tu8 passive = 0;\r\n\r\n\tswitch (rtw_rd_5g) {\r\n\tcase RTW_RD_5G_FCC13:\r\n\tcase RTW_RD_5G_FCC16:\r\n\tcase RTW_RD_5G_ETSI18:\r\n\tcase RTW_RD_5G_ETSI19:\r\n\tcase RTW_RD_5G_WORLD:\r\n\tcase RTW_RD_5G_WORLD1:\r\n\tcase RTW_RD_5G_MKK6:\r\n\tcase RTW_RD_5G_MKK7:\r\n\tcase RTW_RD_5G_ETSI22:\r\n\t\tpassive = 1;\r\n\t};\r\n\r\n\treturn passive;\r\n}\r\n\r\ninline static u8 rtw_rd_5g_band4_passive(u8 rtw_rd_5g)\r\n{\r\n\tu8 passive = 0;\r\n\r\n\tswitch (rtw_rd_5g) {\r\n\tcase RTW_RD_5G_MKK5:\r\n\tcase RTW_RD_5G_ETSI16:\r\n\tcase RTW_RD_5G_ETSI18:\r\n\tcase RTW_RD_5G_ETSI19:\r\n\tcase RTW_RD_5G_WORLD:\r\n\tcase RTW_RD_5G_MKK8:\r\n\tcase RTW_RD_5G_ETSI22:\r\n\t\tpassive = 1;\r\n\t};\r\n\r\n\treturn passive;\r\n}\r\n\r\nu8 init_channel_set(_adapter *padapter, u8 ChannelPlan, RT_CHANNEL_INFO *channel_set)\r\n{\r\n\tstruct registry_priv *regsty = adapter_to_regsty(padapter);\r\n\tu8\tindex, chanset_size = 0;\r\n\tu8\tb5GBand = _FALSE, b2_4GBand = _FALSE;\r\n\tu8\trd_2g = 0, rd_5g = 0;\r\n#ifdef CONFIG_DFS_MASTER\r\n\tint i;\r\n#endif\r\n\r\n\tif (!rtw_is_channel_plan_valid(ChannelPlan)) {\r\n\t\tRTW_ERR(\"ChannelPlan ID 0x%02X error !!!!!\\n\", ChannelPlan);\r\n\t\treturn chanset_size;\r\n\t}\r\n\r\n\t_rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);\r\n\r\n\tif (IsSupported24G(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_2G))\r\n\t\tb2_4GBand = _TRUE;\r\n\r\n\tif (is_supported_5g(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_5G))\r\n\t\tb5GBand = _TRUE;\r\n\r\n\tif (b2_4GBand == _FALSE && b5GBand == _FALSE) {\r\n\t\tRTW_WARN(\"HW band_cap has no intersection with SW wireless_mode setting\\n\");\r\n\t\treturn chanset_size;\r\n\t}\r\n\r\n\tif (b2_4GBand) {\r\n\t\tif (ChannelPlan == RTW_CHPLAN_REALTEK_DEFINE)\r\n\t\t\trd_2g = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.rd_2g;\r\n\t\telse\r\n\t\t\trd_2g = RTW_ChannelPlanMap[ChannelPlan].rd_2g;\r\n\r\n\t\tfor (index = 0; index < CH_LIST_LEN(RTW_ChannelPlan2G[rd_2g]); index++) {\r\n\t\t\tif (rtw_regsty_is_excl_chs(regsty, CH_LIST_CH(RTW_ChannelPlan2G[rd_2g], index)) == _TRUE)\r\n\t\t\t\tcontinue;\r\n\r\n\t\t\tif (chanset_size >= MAX_CHANNEL_NUM) {\r\n\t\t\t\tRTW_WARN(\"chset size can't exceed MAX_CHANNEL_NUM(%u)\\n\", MAX_CHANNEL_NUM);\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\r\n\t\t\tchannel_set[chanset_size].ChannelNum = CH_LIST_CH(RTW_ChannelPlan2G[rd_2g], index);\r\n\r\n\t\t\tif (ChannelPlan == RTW_CHPLAN_GLOBAL_DOAMIN\r\n\t\t\t\t|| rd_2g == RTW_RD_2G_GLOBAL\r\n\t\t\t) {\r\n\t\t\t\t/* Channel 1~11 is active, and 12~14 is passive */\r\n\t\t\t\tif (channel_set[chanset_size].ChannelNum >= 1 && channel_set[chanset_size].ChannelNum <= 11)\r\n\t\t\t\t\tchannel_set[chanset_size].ScanType = SCAN_ACTIVE;\r\n\t\t\t\telse if ((channel_set[chanset_size].ChannelNum  >= 12 && channel_set[chanset_size].ChannelNum  <= 14))\r\n\t\t\t\t\tchannel_set[chanset_size].ScanType  = SCAN_PASSIVE;\r\n\t\t\t} else if (ChannelPlan == RTW_CHPLAN_WORLD_WIDE_13\r\n\t\t\t\t|| ChannelPlan == RTW_CHPLAN_WORLD_WIDE_5G\r\n\t\t\t\t|| rd_2g == RTW_RD_2G_WORLD\r\n\t\t\t) {\r\n\t\t\t\t/* channel 12~13, passive scan */\r\n\t\t\t\tif (channel_set[chanset_size].ChannelNum <= 11)\r\n\t\t\t\t\tchannel_set[chanset_size].ScanType = SCAN_ACTIVE;\r\n\t\t\t\telse\r\n\t\t\t\t\tchannel_set[chanset_size].ScanType = SCAN_PASSIVE;\r\n\t\t\t} else\r\n\t\t\t\tchannel_set[chanset_size].ScanType = SCAN_ACTIVE;\r\n\r\n\t\t\tchanset_size++;\r\n\t\t}\r\n\t}\r\n\r\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\r\n\tif (b5GBand) {\r\n\t\tif (ChannelPlan == RTW_CHPLAN_REALTEK_DEFINE)\r\n\t\t\trd_5g = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.rd_5g;\r\n\t\telse\r\n\t\t\trd_5g = RTW_ChannelPlanMap[ChannelPlan].rd_5g;\r\n\r\n\t\tfor (index = 0; index < CH_LIST_LEN(RTW_ChannelPlan5G[rd_5g]); index++) {\r\n\t\t\tif (rtw_regsty_is_excl_chs(regsty, CH_LIST_CH(RTW_ChannelPlan5G[rd_5g], index)) == _TRUE)\r\n\t\t\t\tcontinue;\r\n\t\t\t#ifndef CONFIG_DFS\r\n\t\t\tif (rtw_is_dfs_ch(CH_LIST_CH(RTW_ChannelPlan5G[rd_5g], index)))\r\n\t\t\t\tcontinue;\r\n\t\t\t#endif\r\n\r\n\t\t\tif (chanset_size >= MAX_CHANNEL_NUM) {\r\n\t\t\t\tRTW_WARN(\"chset size can't exceed MAX_CHANNEL_NUM(%u)\\n\", MAX_CHANNEL_NUM);\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\r\n\t\t\tchannel_set[chanset_size].ChannelNum = CH_LIST_CH(RTW_ChannelPlan5G[rd_5g], index);\r\n\r\n\t\t\tif ((ChannelPlan == RTW_CHPLAN_WORLD_WIDE_5G) /* all channels passive */\r\n\t\t\t\t|| (rtw_is_5g_band1(channel_set[chanset_size].ChannelNum)\r\n\t\t\t\t\t&& rtw_rd_5g_band1_passive(rd_5g)) /* band1 passive */\r\n\t\t\t\t|| (rtw_is_5g_band4(channel_set[chanset_size].ChannelNum)\r\n\t\t\t\t\t&& rtw_rd_5g_band4_passive(rd_5g)) /* band4 passive */\r\n\t\t\t\t|| (rtw_is_dfs_ch(channel_set[chanset_size].ChannelNum)) /* DFS channel(band2, 3) passive */\r\n\t\t\t)\r\n\t\t\t\tchannel_set[chanset_size].ScanType = SCAN_PASSIVE;\r\n\t\t\telse\r\n\t\t\t\tchannel_set[chanset_size].ScanType = SCAN_ACTIVE;\r\n\r\n\t\t\tchanset_size++;\r\n\t\t}\r\n\t}\r\n\r\n\t#ifdef CONFIG_DFS_MASTER\r\n\tfor (i = 0; i < chanset_size; i++)\r\n\t\tchannel_set[i].non_ocp_end_time = rtw_get_current_time();\r\n\t#endif\r\n#endif /* CONFIG_IEEE80211_BAND_5GHZ */\r\n\r\n\tif (chanset_size)\r\n\t\tRTW_INFO(FUNC_ADPT_FMT\" ChannelPlan ID:0x%02x, ch num:%d\\n\"\r\n\t\t\t, FUNC_ADPT_ARG(padapter), ChannelPlan, chanset_size);\r\n\telse\r\n\t\tRTW_WARN(FUNC_ADPT_FMT\" ChannelPlan ID:0x%02x, final chset has no channel\\n\"\r\n\t\t\t, FUNC_ADPT_ARG(padapter), ChannelPlan);\r\n\r\n\treturn chanset_size;\r\n}\r\n\r\n#ifdef CONFIG_80211AC_VHT\r\n#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val) , .en_11ac = (_val)\r\n#else\r\n#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val)\r\n#endif\r\n\r\n#if RTW_DEF_MODULE_REGULATORY_CERT\r\n#define COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_val) , .def_module_flags = (_val)\r\n#else\r\n#define COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_val)\r\n#endif\r\n\r\n/* has def_module_flags specified, used by common map and HAL dfference map */\r\n#define COUNTRY_CHPLAN_ENT(_alpha2, _chplan, _en_11ac, _def_module_flags) \\\r\n\t{.alpha2 = (_alpha2), .chplan = (_chplan) \\\r\n\t\tCOUNTRY_CHPLAN_ASSIGN_EN_11AC(_en_11ac) \\\r\n\t\tCOUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_def_module_flags) \\\r\n\t}\r\n\r\n#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP\r\n\r\n#include \"../platform/custom_country_chplan.h\"\r\n\r\n#elif RTW_DEF_MODULE_REGULATORY_CERT\r\n\r\n/* leave def_module_flags empty, def_module_flags check is done on country_chplan_map */\r\n#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AE_HMC_M2) /* 2013 certify */\r\nstatic const struct country_chplan RTL8821AE_HMC_M2_country_chplan_exc_map[] = {\r\n\tCOUNTRY_CHPLAN_ENT(\"CA\", 0x34, 1, 0), /* Canada */\r\n\tCOUNTRY_CHPLAN_ENT(\"CL\", 0x30, 1, 0), /* Chile */\r\n\tCOUNTRY_CHPLAN_ENT(\"CN\", 0x51, 1, 0), /* China */\r\n\tCOUNTRY_CHPLAN_ENT(\"CO\", 0x34, 1, 0), /* Colombia */\r\n\tCOUNTRY_CHPLAN_ENT(\"CR\", 0x34, 1, 0), /* Costa Rica */\r\n\tCOUNTRY_CHPLAN_ENT(\"DO\", 0x34, 1, 0), /* Dominican Republic */\r\n\tCOUNTRY_CHPLAN_ENT(\"EC\", 0x34, 1, 0), /* Ecuador */\r\n\tCOUNTRY_CHPLAN_ENT(\"GT\", 0x34, 1, 0), /* Guatemala */\r\n\tCOUNTRY_CHPLAN_ENT(\"KR\", 0x28, 1, 0), /* South Korea */\r\n\tCOUNTRY_CHPLAN_ENT(\"MX\", 0x34, 1, 0), /* Mexico */\r\n\tCOUNTRY_CHPLAN_ENT(\"MY\", 0x47, 1, 0), /* Malaysia */\r\n\tCOUNTRY_CHPLAN_ENT(\"NI\", 0x34, 1, 0), /* Nicaragua */\r\n\tCOUNTRY_CHPLAN_ENT(\"PA\", 0x34, 1, 0), /* Panama */\r\n\tCOUNTRY_CHPLAN_ENT(\"PE\", 0x34, 1, 0), /* Peru */\r\n\tCOUNTRY_CHPLAN_ENT(\"PR\", 0x34, 1, 0), /* Puerto Rico */\r\n\tCOUNTRY_CHPLAN_ENT(\"PY\", 0x34, 1, 0), /* Paraguay */\r\n\tCOUNTRY_CHPLAN_ENT(\"TW\", 0x39, 1, 0), /* Taiwan */\r\n\tCOUNTRY_CHPLAN_ENT(\"UA\", 0x36, 0, 0), /* Ukraine */\r\n\tCOUNTRY_CHPLAN_ENT(\"US\", 0x34, 1, 0), /* United States of America (USA) */\r\n};\r\n#endif\r\n\r\n#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AU) /* 2014 certify */\r\nstatic const struct country_chplan RTL8821AU_country_chplan_exc_map[] = {\r\n\tCOUNTRY_CHPLAN_ENT(\"CA\", 0x34, 1, 0), /* Canada */\r\n\tCOUNTRY_CHPLAN_ENT(\"KR\", 0x28, 1, 0), /* South Korea */\r\n\tCOUNTRY_CHPLAN_ENT(\"RU\", 0x59, 0, 0), /* Russia(fac/gost), Kaliningrad */\r\n\tCOUNTRY_CHPLAN_ENT(\"TW\", 0x39, 1, 0), /* Taiwan */\r\n\tCOUNTRY_CHPLAN_ENT(\"UA\", 0x36, 0, 0), /* Ukraine */\r\n\tCOUNTRY_CHPLAN_ENT(\"US\", 0x34, 1, 0), /* United States of America (USA) */\r\n};\r\n#endif\r\n\r\n#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AENF_NGFF) /* 2014 certify */\r\nstatic const struct country_chplan RTL8812AENF_NGFF_country_chplan_exc_map[] = {\r\n\tCOUNTRY_CHPLAN_ENT(\"TW\", 0x39, 1, 0), /* Taiwan */\r\n\tCOUNTRY_CHPLAN_ENT(\"US\", 0x34, 1, 0), /* United States of America (USA) */\r\n};\r\n#endif\r\n\r\n#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AEBT_HMC) /* 2013 certify */\r\nstatic const struct country_chplan RTL8812AEBT_HMC_country_chplan_exc_map[] = {\r\n\tCOUNTRY_CHPLAN_ENT(\"CA\", 0x34, 1, 0), /* Canada */\r\n\tCOUNTRY_CHPLAN_ENT(\"KR\", 0x28, 1, 0), /* South Korea */\r\n\tCOUNTRY_CHPLAN_ENT(\"RU\", 0x59, 0, 0), /* Russia(fac/gost), Kaliningrad */\r\n\tCOUNTRY_CHPLAN_ENT(\"TW\", 0x39, 1, 0), /* Taiwan */\r\n\tCOUNTRY_CHPLAN_ENT(\"UA\", 0x36, 0, 0), /* Ukraine */\r\n\tCOUNTRY_CHPLAN_ENT(\"US\", 0x34, 1, 0), /* United States of America (USA) */\r\n};\r\n#endif\r\n\r\n#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8188EE_HMC_M2) /* 2012 certify */\r\nstatic const struct country_chplan RTL8188EE_HMC_M2_country_chplan_exc_map[] = {\r\n\tCOUNTRY_CHPLAN_ENT(\"AW\", 0x34, 1, 0), /* Aruba */\r\n\tCOUNTRY_CHPLAN_ENT(\"BB\", 0x34, 1, 0), /* Barbados */\r\n\tCOUNTRY_CHPLAN_ENT(\"CA\", 0x20, 1, 0), /* Canada */\r\n\tCOUNTRY_CHPLAN_ENT(\"CO\", 0x34, 1, 0), /* Colombia */\r\n\tCOUNTRY_CHPLAN_ENT(\"CR\", 0x34, 1, 0), /* Costa Rica */\r\n\tCOUNTRY_CHPLAN_ENT(\"DO\", 0x34, 1, 0), /* Dominican Republic */\r\n\tCOUNTRY_CHPLAN_ENT(\"EC\", 0x34, 1, 0), /* Ecuador */\r\n\tCOUNTRY_CHPLAN_ENT(\"GT\", 0x34, 1, 0), /* Guatemala */\r\n\tCOUNTRY_CHPLAN_ENT(\"HT\", 0x34, 1, 0), /* Haiti */\r\n\tCOUNTRY_CHPLAN_ENT(\"KR\", 0x28, 1, 0), /* South Korea */\r\n\tCOUNTRY_CHPLAN_ENT(\"MX\", 0x34, 1, 0), /* Mexico */\r\n\tCOUNTRY_CHPLAN_ENT(\"NI\", 0x34, 1, 0), /* Nicaragua */\r\n\tCOUNTRY_CHPLAN_ENT(\"PA\", 0x34, 1, 0), /* Panama */\r\n\tCOUNTRY_CHPLAN_ENT(\"PE\", 0x34, 1, 0), /* Peru */\r\n\tCOUNTRY_CHPLAN_ENT(\"PR\", 0x34, 1, 0), /* Puerto Rico */\r\n\tCOUNTRY_CHPLAN_ENT(\"PY\", 0x34, 1, 0), /* Paraguay */\r\n\tCOUNTRY_CHPLAN_ENT(\"SC\", 0x34, 1, 0), /* Seychelles */\r\n\tCOUNTRY_CHPLAN_ENT(\"TW\", 0x39, 1, 0), /* Taiwan */\r\n\tCOUNTRY_CHPLAN_ENT(\"US\", 0x34, 1, 0), /* United States of America (USA) */\r\n\tCOUNTRY_CHPLAN_ENT(\"VC\", 0x34, 1, 0), /* Saint Vincent and the Grenadines */\r\n};\r\n#endif\r\n\r\n#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BE_HMC_M2) /* 2013 certify */\r\nstatic const struct country_chplan RTL8723BE_HMC_M2_country_chplan_exc_map[] = {\r\n\tCOUNTRY_CHPLAN_ENT(\"AW\", 0x34, 1, 0), /* Aruba */\r\n\tCOUNTRY_CHPLAN_ENT(\"BS\", 0x34, 1, 0), /* Bahamas */\r\n\tCOUNTRY_CHPLAN_ENT(\"CA\", 0x20, 1, 0), /* Canada */\r\n\tCOUNTRY_CHPLAN_ENT(\"CO\", 0x34, 1, 0), /* Colombia */\r\n\tCOUNTRY_CHPLAN_ENT(\"CR\", 0x34, 1, 0), /* Costa Rica */\r\n\tCOUNTRY_CHPLAN_ENT(\"DO\", 0x34, 1, 0), /* Dominican Republic */\r\n\tCOUNTRY_CHPLAN_ENT(\"EC\", 0x34, 1, 0), /* Ecuador */\r\n\tCOUNTRY_CHPLAN_ENT(\"GT\", 0x34, 1, 0), /* Guatemala */\r\n\tCOUNTRY_CHPLAN_ENT(\"KR\", 0x28, 1, 0), /* South Korea */\r\n\tCOUNTRY_CHPLAN_ENT(\"MX\", 0x34, 1, 0), /* Mexico */\r\n\tCOUNTRY_CHPLAN_ENT(\"NI\", 0x34, 1, 0), /* Nicaragua */\r\n\tCOUNTRY_CHPLAN_ENT(\"PA\", 0x34, 1, 0), /* Panama */\r\n\tCOUNTRY_CHPLAN_ENT(\"PE\", 0x34, 1, 0), /* Peru */\r\n\tCOUNTRY_CHPLAN_ENT(\"PR\", 0x34, 1, 0), /* Puerto Rico */\r\n\tCOUNTRY_CHPLAN_ENT(\"PY\", 0x34, 1, 0), /* Paraguay */\r\n\tCOUNTRY_CHPLAN_ENT(\"TW\", 0x39, 1, 0), /* Taiwan */\r\n\tCOUNTRY_CHPLAN_ENT(\"US\", 0x34, 1, 0), /* United States of America (USA) */\r\n};\r\n#endif\r\n\r\n#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BS_NGFF1216) /* 2014 certify */\r\nstatic const struct country_chplan RTL8723BS_NGFF1216_country_chplan_exc_map[] = {\r\n\tCOUNTRY_CHPLAN_ENT(\"BB\", 0x34, 1, 0), /* Barbados */\r\n\tCOUNTRY_CHPLAN_ENT(\"CA\", 0x20, 1, 0), /* Canada */\r\n\tCOUNTRY_CHPLAN_ENT(\"CO\", 0x34, 1, 0), /* Colombia */\r\n\tCOUNTRY_CHPLAN_ENT(\"CR\", 0x34, 1, 0), /* Costa Rica */\r\n\tCOUNTRY_CHPLAN_ENT(\"DO\", 0x34, 1, 0), /* Dominican Republic */\r\n\tCOUNTRY_CHPLAN_ENT(\"EC\", 0x34, 1, 0), /* Ecuador */\r\n\tCOUNTRY_CHPLAN_ENT(\"GT\", 0x34, 1, 0), /* Guatemala */\r\n\tCOUNTRY_CHPLAN_ENT(\"HT\", 0x34, 1, 0), /* Haiti */\r\n\tCOUNTRY_CHPLAN_ENT(\"KR\", 0x28, 1, 0), /* South Korea */\r\n\tCOUNTRY_CHPLAN_ENT(\"MX\", 0x34, 1, 0), /* Mexico */\r\n\tCOUNTRY_CHPLAN_ENT(\"NI\", 0x34, 1, 0), /* Nicaragua */\r\n\tCOUNTRY_CHPLAN_ENT(\"PA\", 0x34, 1, 0), /* Panama */\r\n\tCOUNTRY_CHPLAN_ENT(\"PE\", 0x34, 1, 0), /* Peru */\r\n\tCOUNTRY_CHPLAN_ENT(\"PR\", 0x34, 1, 0), /* Puerto Rico */\r\n\tCOUNTRY_CHPLAN_ENT(\"PY\", 0x34, 1, 0), /* Paraguay */\r\n\tCOUNTRY_CHPLAN_ENT(\"TW\", 0x39, 1, 0), /* Taiwan */\r\n\tCOUNTRY_CHPLAN_ENT(\"US\", 0x34, 1, 0), /* United States of America (USA) */\r\n};\r\n#endif\r\n\r\n#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8192EEBT_HMC_M2) /* 2013 certify */\r\nstatic const struct country_chplan RTL8192EEBT_HMC_M2_country_chplan_exc_map[] = {\r\n\tCOUNTRY_CHPLAN_ENT(\"AW\", 0x34, 1, 0), /* Aruba */\r\n\tCOUNTRY_CHPLAN_ENT(\"CA\", 0x20, 1, 0), /* Canada */\r\n\tCOUNTRY_CHPLAN_ENT(\"CO\", 0x34, 1, 0), /* Colombia */\r\n\tCOUNTRY_CHPLAN_ENT(\"CR\", 0x34, 1, 0), /* Costa Rica */\r\n\tCOUNTRY_CHPLAN_ENT(\"DO\", 0x34, 1, 0), /* Dominican Republic */\r\n\tCOUNTRY_CHPLAN_ENT(\"EC\", 0x34, 1, 0), /* Ecuador */\r\n\tCOUNTRY_CHPLAN_ENT(\"GT\", 0x34, 1, 0), /* Guatemala */\r\n\tCOUNTRY_CHPLAN_ENT(\"KR\", 0x28, 1, 0), /* South Korea */\r\n\tCOUNTRY_CHPLAN_ENT(\"MX\", 0x34, 1, 0), /* Mexico */\r\n\tCOUNTRY_CHPLAN_ENT(\"NI\", 0x34, 1, 0), /* Nicaragua */\r\n\tCOUNTRY_CHPLAN_ENT(\"PA\", 0x34, 1, 0), /* Panama */\r\n\tCOUNTRY_CHPLAN_ENT(\"PE\", 0x34, 1, 0), /* Peru */\r\n\tCOUNTRY_CHPLAN_ENT(\"PR\", 0x34, 1, 0), /* Puerto Rico */\r\n\tCOUNTRY_CHPLAN_ENT(\"PY\", 0x34, 1, 0), /* Paraguay */\r\n\tCOUNTRY_CHPLAN_ENT(\"SC\", 0x34, 1, 0), /* Seychelles */\r\n\tCOUNTRY_CHPLAN_ENT(\"ST\", 0x34, 1, 0), /* Sao Tome and Principe */\r\n\tCOUNTRY_CHPLAN_ENT(\"TW\", 0x39, 1, 0), /* Taiwan */\r\n\tCOUNTRY_CHPLAN_ENT(\"US\", 0x34, 1, 0), /* United States of America (USA) */\r\n};\r\n#endif\r\n\r\n#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723DE_NGFF1630) /* 2016 certify */\r\nstatic const struct country_chplan RTL8723DE_NGFF1630_country_chplan_exc_map[] = {\r\n\tCOUNTRY_CHPLAN_ENT(\"CA\", 0x2A, 1, 0), /* Canada */\r\n\tCOUNTRY_CHPLAN_ENT(\"KR\", 0x28, 1, 0), /* South Korea */\r\n\tCOUNTRY_CHPLAN_ENT(\"MX\", 0x34, 1, 0), /* Mexico */\r\n};\r\n#endif\r\n\r\n#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8822BE) /* 2016 certify */\r\nstatic const struct country_chplan RTL8822BE_country_chplan_exc_map[] = {\r\n\tCOUNTRY_CHPLAN_ENT(\"KR\", 0x28, 1, 0), /* South Korea */\r\n};\r\n#endif\r\n\r\n#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821CE) /* 2016 certify */\r\nstatic const struct country_chplan RTL8821CE_country_chplan_exc_map[] = {\r\n\tCOUNTRY_CHPLAN_ENT(\"KR\", 0x28, 1, 0), /* South Korea */\r\n};\r\n#endif\r\n\r\n/**\r\n * rtw_def_module_get_chplan_from_country -\r\n * @country_code: string of country code\r\n * @return:\r\n * Return NULL for case referring to common map\r\n */\r\nstatic const struct country_chplan *rtw_def_module_get_chplan_from_country(const char *country_code)\r\n{\r\n\tconst struct country_chplan *ent = NULL;\r\n\tconst struct country_chplan *hal_map = NULL;\r\n\tu16 hal_map_sz = 0;\r\n\tint i;\r\n\r\n\t/* TODO: runtime selection for multi driver */\r\n#if (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AE_HMC_M2)\r\n\thal_map = RTL8821AE_HMC_M2_country_chplan_exc_map;\r\n\thal_map_sz = sizeof(RTL8821AE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan);\r\n#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AU)\r\n\thal_map = RTL8821AU_country_chplan_exc_map;\r\n\thal_map_sz = sizeof(RTL8821AU_country_chplan_exc_map) / sizeof(struct country_chplan);\r\n#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AENF_NGFF)\r\n\thal_map = RTL8812AENF_NGFF_country_chplan_exc_map;\r\n\thal_map_sz = sizeof(RTL8812AENF_NGFF_country_chplan_exc_map) / sizeof(struct country_chplan);\r\n#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AEBT_HMC)\r\n\thal_map = RTL8812AEBT_HMC_country_chplan_exc_map;\r\n\thal_map_sz = sizeof(RTL8812AEBT_HMC_country_chplan_exc_map) / sizeof(struct country_chplan);\r\n#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8188EE_HMC_M2)\r\n\thal_map = RTL8188EE_HMC_M2_country_chplan_exc_map;\r\n\thal_map_sz = sizeof(RTL8188EE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan);\r\n#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BE_HMC_M2)\r\n\thal_map = RTL8723BE_HMC_M2_country_chplan_exc_map;\r\n\thal_map_sz = sizeof(RTL8723BE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan);\r\n#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BS_NGFF1216)\r\n\thal_map = RTL8723BS_NGFF1216_country_chplan_exc_map;\r\n\thal_map_sz = sizeof(RTL8723BS_NGFF1216_country_chplan_exc_map) / sizeof(struct country_chplan);\r\n#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8192EEBT_HMC_M2)\r\n\thal_map = RTL8192EEBT_HMC_M2_country_chplan_exc_map;\r\n\thal_map_sz = sizeof(RTL8192EEBT_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan);\r\n#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723DE_NGFF1630)\r\n\thal_map = RTL8723DE_NGFF1630_country_chplan_exc_map;\r\n\thal_map_sz = sizeof(RTL8723DE_NGFF1630_country_chplan_exc_map) / sizeof(struct country_chplan);\r\n#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8822BE)\r\n\thal_map = RTL8822BE_country_chplan_exc_map;\r\n\thal_map_sz = sizeof(RTL8822BE_country_chplan_exc_map) / sizeof(struct country_chplan);\r\n#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821CE)\r\n\thal_map = RTL8821CE_country_chplan_exc_map;\r\n\thal_map_sz = sizeof(RTL8821CE_country_chplan_exc_map) / sizeof(struct country_chplan);\r\n#endif\r\n\r\n\tif (hal_map == NULL || hal_map_sz == 0)\r\n\t\tgoto exit;\r\n\r\n\tfor (i = 0; i < hal_map_sz; i++) {\r\n\t\tif (strncmp(country_code, hal_map[i].alpha2, 2) == 0) {\r\n\t\t\tent = &hal_map[i];\r\n\t\t\tbreak;\r\n\t\t}\r\n\t}\r\n\r\nexit:\r\n\treturn ent;\r\n}\r\n#endif /* CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP or RTW_DEF_MODULE_REGULATORY_CERT */\r\n\r\nstatic const struct country_chplan country_chplan_map[] = {\r\n\tCOUNTRY_CHPLAN_ENT(\"AD\", 0x26, 1, 0x000), /* Andorra */\r\n\tCOUNTRY_CHPLAN_ENT(\"AE\", 0x35, 1, 0x7FB), /* United Arab Emirates */\r\n\tCOUNTRY_CHPLAN_ENT(\"AF\", 0x42, 1, 0x000), /* Afghanistan */\r\n\tCOUNTRY_CHPLAN_ENT(\"AG\", 0x76, 1, 0x000), /* Antigua & Barbuda */\r\n\tCOUNTRY_CHPLAN_ENT(\"AI\", 0x26, 1, 0x000), /* Anguilla(UK) */\r\n\tCOUNTRY_CHPLAN_ENT(\"AL\", 0x26, 1, 0x7F1), /* Albania */\r\n\tCOUNTRY_CHPLAN_ENT(\"AM\", 0x26, 1, 0x6B0), /* Armenia */\r\n\tCOUNTRY_CHPLAN_ENT(\"AN\", 0x76, 1, 0x7F1), /* Netherlands Antilles */\r\n\tCOUNTRY_CHPLAN_ENT(\"AO\", 0x47, 1, 0x6E0), /* Angola */\r\n\tCOUNTRY_CHPLAN_ENT(\"AQ\", 0x26, 1, 0x000), /* Antarctica */\r\n\tCOUNTRY_CHPLAN_ENT(\"AR\", 0x61, 1, 0x7F3), /* Argentina */\r\n\tCOUNTRY_CHPLAN_ENT(\"AS\", 0x76, 1, 0x000), /* American Samoa */\r\n\tCOUNTRY_CHPLAN_ENT(\"AT\", 0x26, 1, 0x7FB), /* Austria */\r\n\tCOUNTRY_CHPLAN_ENT(\"AU\", 0x45, 1, 0x7FB), /* Australia */\r\n\tCOUNTRY_CHPLAN_ENT(\"AW\", 0x76, 1, 0x0B0), /* Aruba */\r\n\tCOUNTRY_CHPLAN_ENT(\"AZ\", 0x26, 1, 0x7F1), /* Azerbaijan */\r\n\tCOUNTRY_CHPLAN_ENT(\"BA\", 0x26, 1, 0x7F1), /* Bosnia & Herzegovina */\r\n\tCOUNTRY_CHPLAN_ENT(\"BB\", 0x76, 1, 0x650), /* Barbados */\r\n\tCOUNTRY_CHPLAN_ENT(\"BD\", 0x26, 1, 0x7F1), /* Bangladesh */\r\n\tCOUNTRY_CHPLAN_ENT(\"BE\", 0x26, 1, 0x7FB), /* Belgium */\r\n\tCOUNTRY_CHPLAN_ENT(\"BF\", 0x26, 1, 0x6B0), /* Burkina Faso */\r\n\tCOUNTRY_CHPLAN_ENT(\"BG\", 0x26, 1, 0x7F1), /* Bulgaria */\r\n\tCOUNTRY_CHPLAN_ENT(\"BH\", 0x48, 1, 0x7F1), /* Bahrain */\r\n\tCOUNTRY_CHPLAN_ENT(\"BI\", 0x26, 1, 0x6B0), /* Burundi */\r\n\tCOUNTRY_CHPLAN_ENT(\"BJ\", 0x26, 1, 0x6B0), /* Benin */\r\n\tCOUNTRY_CHPLAN_ENT(\"BM\", 0x76, 1, 0x600), /* Bermuda (UK) */\r\n\tCOUNTRY_CHPLAN_ENT(\"BN\", 0x47, 1, 0x610), /* Brunei */\r\n\tCOUNTRY_CHPLAN_ENT(\"BO\", 0x73, 1, 0x7F1), /* Bolivia */\r\n\tCOUNTRY_CHPLAN_ENT(\"BR\", 0x62, 1, 0x7F1), /* Brazil */\r\n\tCOUNTRY_CHPLAN_ENT(\"BS\", 0x76, 1, 0x620), /* Bahamas */\r\n\tCOUNTRY_CHPLAN_ENT(\"BT\", 0x26, 1, 0x000), /* Bhutan */\r\n\tCOUNTRY_CHPLAN_ENT(\"BV\", 0x26, 1, 0x000), /* Bouvet Island (Norway) */\r\n\tCOUNTRY_CHPLAN_ENT(\"BW\", 0x35, 1, 0x6F1), /* Botswana */\r\n\tCOUNTRY_CHPLAN_ENT(\"BY\", 0x26, 1, 0x7F1), /* Belarus */\r\n\tCOUNTRY_CHPLAN_ENT(\"BZ\", 0x76, 1, 0x000), /* Belize */\r\n\tCOUNTRY_CHPLAN_ENT(\"CA\", 0x2B, 1, 0x7FB), /* Canada */\r\n\tCOUNTRY_CHPLAN_ENT(\"CC\", 0x26, 1, 0x000), /* Cocos (Keeling) Islands (Australia) */\r\n\tCOUNTRY_CHPLAN_ENT(\"CD\", 0x26, 1, 0x6B0), /* Congo, Republic of the */\r\n\tCOUNTRY_CHPLAN_ENT(\"CF\", 0x26, 1, 0x6B0), /* Central African Republic */\r\n\tCOUNTRY_CHPLAN_ENT(\"CG\", 0x26, 1, 0x6B0), /* Congo, Democratic Republic of the. Zaire */\r\n\tCOUNTRY_CHPLAN_ENT(\"CH\", 0x26, 1, 0x7FB), /* Switzerland */\r\n\tCOUNTRY_CHPLAN_ENT(\"CI\", 0x42, 1, 0x7F1), /* Cote d'Ivoire */\r\n\tCOUNTRY_CHPLAN_ENT(\"CK\", 0x26, 1, 0x000), /* Cook Islands */\r\n\tCOUNTRY_CHPLAN_ENT(\"CL\", 0x2D, 1, 0x7F1), /* Chile */\r\n\tCOUNTRY_CHPLAN_ENT(\"CM\", 0x26, 1, 0x6B0), /* Cameroon */\r\n\tCOUNTRY_CHPLAN_ENT(\"CN\", 0x48, 1, 0x7FB), /* China */\r\n\tCOUNTRY_CHPLAN_ENT(\"CO\", 0x76, 1, 0x7F1), /* Colombia */\r\n\tCOUNTRY_CHPLAN_ENT(\"CR\", 0x76, 1, 0x7F1), /* Costa Rica */\r\n\tCOUNTRY_CHPLAN_ENT(\"CV\", 0x26, 1, 0x6B0), /* Cape Verde */\r\n\tCOUNTRY_CHPLAN_ENT(\"CX\", 0x45, 1, 0x000), /* Christmas Island (Australia) */\r\n\tCOUNTRY_CHPLAN_ENT(\"CY\", 0x26, 1, 0x7FB), /* Cyprus */\r\n\tCOUNTRY_CHPLAN_ENT(\"CZ\", 0x26, 1, 0x7FB), /* Czech Republic */\r\n\tCOUNTRY_CHPLAN_ENT(\"DE\", 0x26, 1, 0x7FB), /* Germany */\r\n\tCOUNTRY_CHPLAN_ENT(\"DJ\", 0x26, 1, 0x680), /* Djibouti */\r\n\tCOUNTRY_CHPLAN_ENT(\"DK\", 0x26, 1, 0x7FB), /* Denmark */\r\n\tCOUNTRY_CHPLAN_ENT(\"DM\", 0x76, 1, 0x000), /* Dominica */\r\n\tCOUNTRY_CHPLAN_ENT(\"DO\", 0x76, 1, 0x7F1), /* Dominican Republic */\r\n\tCOUNTRY_CHPLAN_ENT(\"DZ\", 0x26, 1, 0x7F1), /* Algeria */\r\n\tCOUNTRY_CHPLAN_ENT(\"EC\", 0x76, 1, 0x7F1), /* Ecuador */\r\n\tCOUNTRY_CHPLAN_ENT(\"EE\", 0x26, 1, 0x7FB), /* Estonia */\r\n\tCOUNTRY_CHPLAN_ENT(\"EG\", 0x47, 1, 0x7F1), /* Egypt */\r\n\tCOUNTRY_CHPLAN_ENT(\"EH\", 0x47, 1, 0x680), /* Western Sahara */\r\n\tCOUNTRY_CHPLAN_ENT(\"ER\", 0x26, 1, 0x000), /* Eritrea */\r\n\tCOUNTRY_CHPLAN_ENT(\"ES\", 0x26, 1, 0x7FB), /* Spain, Canary Islands, Ceuta, Melilla */\r\n\tCOUNTRY_CHPLAN_ENT(\"ET\", 0x26, 1, 0x4B0), /* Ethiopia */\r\n\tCOUNTRY_CHPLAN_ENT(\"FI\", 0x26, 1, 0x7FB), /* Finland */\r\n\tCOUNTRY_CHPLAN_ENT(\"FJ\", 0x76, 1, 0x600), /* Fiji */\r\n\tCOUNTRY_CHPLAN_ENT(\"FK\", 0x26, 1, 0x000), /* Falkland Islands (Islas Malvinas) (UK) */\r\n\tCOUNTRY_CHPLAN_ENT(\"FM\", 0x76, 1, 0x000), /* Micronesia, Federated States of (USA) */\r\n\tCOUNTRY_CHPLAN_ENT(\"FO\", 0x26, 1, 0x000), /* Faroe Islands (Denmark) */\r\n\tCOUNTRY_CHPLAN_ENT(\"FR\", 0x26, 1, 0x7FB), /* France */\r\n\tCOUNTRY_CHPLAN_ENT(\"GA\", 0x26, 1, 0x6B0), /* Gabon */\r\n\tCOUNTRY_CHPLAN_ENT(\"GB\", 0x26, 1, 0x7FB), /* Great Britain (United Kingdom; England) */\r\n\tCOUNTRY_CHPLAN_ENT(\"GD\", 0x76, 1, 0x0B0), /* Grenada */\r\n\tCOUNTRY_CHPLAN_ENT(\"GE\", 0x26, 1, 0x600), /* Georgia */\r\n\tCOUNTRY_CHPLAN_ENT(\"GF\", 0x26, 1, 0x080), /* French Guiana */\r\n\tCOUNTRY_CHPLAN_ENT(\"GG\", 0x26, 1, 0x000), /* Guernsey (UK) */\r\n\tCOUNTRY_CHPLAN_ENT(\"GH\", 0x26, 1, 0x7F1), /* Ghana */\r\n\tCOUNTRY_CHPLAN_ENT(\"GI\", 0x26, 1, 0x600), /* Gibraltar (UK) */\r\n\tCOUNTRY_CHPLAN_ENT(\"GL\", 0x26, 1, 0x600), /* Greenland (Denmark) */\r\n\tCOUNTRY_CHPLAN_ENT(\"GM\", 0x26, 1, 0x6B0), /* Gambia */\r\n\tCOUNTRY_CHPLAN_ENT(\"GN\", 0x26, 1, 0x610), /* Guinea */\r\n\tCOUNTRY_CHPLAN_ENT(\"GP\", 0x26, 1, 0x600), /* Guadeloupe (France) */\r\n\tCOUNTRY_CHPLAN_ENT(\"GQ\", 0x26, 1, 0x6B0), /* Equatorial Guinea */\r\n\tCOUNTRY_CHPLAN_ENT(\"GR\", 0x26, 1, 0x7FB), /* Greece */\r\n\tCOUNTRY_CHPLAN_ENT(\"GS\", 0x26, 1, 0x000), /* South Georgia and the Sandwich Islands (UK) */\r\n\tCOUNTRY_CHPLAN_ENT(\"GT\", 0x61, 1, 0x7F1), /* Guatemala */\r\n\tCOUNTRY_CHPLAN_ENT(\"GU\", 0x76, 1, 0x600), /* Guam (USA) */\r\n\tCOUNTRY_CHPLAN_ENT(\"GW\", 0x26, 1, 0x6B0), /* Guinea-Bissau */\r\n\tCOUNTRY_CHPLAN_ENT(\"GY\", 0x44, 1, 0x000), /* Guyana */\r\n\tCOUNTRY_CHPLAN_ENT(\"HK\", 0x35, 1, 0x7FB), /* Hong Kong */\r\n\tCOUNTRY_CHPLAN_ENT(\"HM\", 0x45, 1, 0x000), /* Heard and McDonald Islands (Australia) */\r\n\tCOUNTRY_CHPLAN_ENT(\"HN\", 0x32, 1, 0x7F1), /* Honduras */\r\n\tCOUNTRY_CHPLAN_ENT(\"HR\", 0x26, 1, 0x7F9), /* Croatia */\r\n\tCOUNTRY_CHPLAN_ENT(\"HT\", 0x76, 1, 0x650), /* Haiti */\r\n\tCOUNTRY_CHPLAN_ENT(\"HU\", 0x26, 1, 0x7FB), /* Hungary */\r\n\tCOUNTRY_CHPLAN_ENT(\"ID\", 0x3D, 0, 0x7F3), /* Indonesia */\r\n\tCOUNTRY_CHPLAN_ENT(\"IE\", 0x26, 1, 0x7FB), /* Ireland */\r\n\tCOUNTRY_CHPLAN_ENT(\"IL\", 0x47, 1, 0x7F1), /* Israel */\r\n\tCOUNTRY_CHPLAN_ENT(\"IM\", 0x26, 1, 0x000), /* Isle of Man (UK) */\r\n\tCOUNTRY_CHPLAN_ENT(\"IN\", 0x48, 1, 0x7F1), /* India */\r\n\tCOUNTRY_CHPLAN_ENT(\"IO\", 0x26, 1, 0x000), /* British Indian Ocean Territory (UK) */\r\n\tCOUNTRY_CHPLAN_ENT(\"IQ\", 0x26, 1, 0x000), /* Iraq */\r\n\tCOUNTRY_CHPLAN_ENT(\"IR\", 0x26, 0, 0x000), /* Iran */\r\n\tCOUNTRY_CHPLAN_ENT(\"IS\", 0x26, 1, 0x7FB), /* Iceland */\r\n\tCOUNTRY_CHPLAN_ENT(\"IT\", 0x26, 1, 0x7FB), /* Italy */\r\n\tCOUNTRY_CHPLAN_ENT(\"JE\", 0x26, 1, 0x000), /* Jersey (UK) */\r\n\tCOUNTRY_CHPLAN_ENT(\"JM\", 0x32, 1, 0x7F1), /* Jamaica */\r\n\tCOUNTRY_CHPLAN_ENT(\"JO\", 0x49, 1, 0x7FB), /* Jordan */\r\n\tCOUNTRY_CHPLAN_ENT(\"JP\", 0x27, 1, 0x7FF), /* Japan- Telec */\r\n\tCOUNTRY_CHPLAN_ENT(\"KE\", 0x47, 1, 0x7F9), /* Kenya */\r\n\tCOUNTRY_CHPLAN_ENT(\"KG\", 0x26, 1, 0x7F1), /* Kyrgyzstan */\r\n\tCOUNTRY_CHPLAN_ENT(\"KH\", 0x26, 1, 0x7F1), /* Cambodia */\r\n\tCOUNTRY_CHPLAN_ENT(\"KI\", 0x26, 1, 0x000), /* Kiribati */\r\n\tCOUNTRY_CHPLAN_ENT(\"KM\", 0x26, 1, 0x000), /* Comoros */\r\n\tCOUNTRY_CHPLAN_ENT(\"KN\", 0x76, 1, 0x000), /* Saint Kitts and Nevis */\r\n\tCOUNTRY_CHPLAN_ENT(\"KR\", 0x4B, 1, 0x7FB), /* South Korea */\r\n\tCOUNTRY_CHPLAN_ENT(\"KW\", 0x47, 1, 0x7FB), /* Kuwait */\r\n\tCOUNTRY_CHPLAN_ENT(\"KY\", 0x76, 1, 0x000), /* Cayman Islands (UK) */\r\n\tCOUNTRY_CHPLAN_ENT(\"KZ\", 0x26, 1, 0x700), /* Kazakhstan */\r\n\tCOUNTRY_CHPLAN_ENT(\"LA\", 0x26, 1, 0x000), /* Laos */\r\n\tCOUNTRY_CHPLAN_ENT(\"LB\", 0x26, 1, 0x7F1), /* Lebanon */\r\n\tCOUNTRY_CHPLAN_ENT(\"LC\", 0x76, 1, 0x000), /* Saint Lucia */\r\n\tCOUNTRY_CHPLAN_ENT(\"LI\", 0x26, 1, 0x7FB), /* Liechtenstein */\r\n\tCOUNTRY_CHPLAN_ENT(\"LK\", 0x26, 1, 0x7F1), /* Sri Lanka */\r\n\tCOUNTRY_CHPLAN_ENT(\"LR\", 0x26, 1, 0x6B0), /* Liberia */\r\n\tCOUNTRY_CHPLAN_ENT(\"LS\", 0x26, 1, 0x7F1), /* Lesotho */\r\n\tCOUNTRY_CHPLAN_ENT(\"LT\", 0x26, 1, 0x7FB), /* Lithuania */\r\n\tCOUNTRY_CHPLAN_ENT(\"LU\", 0x26, 1, 0x7FB), /* Luxembourg */\r\n\tCOUNTRY_CHPLAN_ENT(\"LV\", 0x26, 1, 0x7FB), /* Latvia */\r\n\tCOUNTRY_CHPLAN_ENT(\"LY\", 0x26, 1, 0x000), /* Libya */\r\n\tCOUNTRY_CHPLAN_ENT(\"MA\", 0x47, 1, 0x7F1), /* Morocco */\r\n\tCOUNTRY_CHPLAN_ENT(\"MC\", 0x26, 1, 0x7FB), /* Monaco */\r\n\tCOUNTRY_CHPLAN_ENT(\"MD\", 0x26, 1, 0x7F1), /* Moldova */\r\n\tCOUNTRY_CHPLAN_ENT(\"ME\", 0x26, 1, 0x7F1), /* Montenegro */\r\n\tCOUNTRY_CHPLAN_ENT(\"MF\", 0x76, 1, 0x000), /* Saint Martin */\r\n\tCOUNTRY_CHPLAN_ENT(\"MG\", 0x26, 1, 0x620), /* Madagascar */\r\n\tCOUNTRY_CHPLAN_ENT(\"MH\", 0x76, 1, 0x000), /* Marshall Islands (USA) */\r\n\tCOUNTRY_CHPLAN_ENT(\"MK\", 0x26, 1, 0x7F1), /* Republic of Macedonia (FYROM) */\r\n\tCOUNTRY_CHPLAN_ENT(\"ML\", 0x26, 1, 0x6B0), /* Mali */\r\n\tCOUNTRY_CHPLAN_ENT(\"MM\", 0x26, 1, 0x000), /* Burma (Myanmar) */\r\n\tCOUNTRY_CHPLAN_ENT(\"MN\", 0x26, 1, 0x000), /* Mongolia */\r\n\tCOUNTRY_CHPLAN_ENT(\"MO\", 0x35, 1, 0x600), /* Macau */\r\n\tCOUNTRY_CHPLAN_ENT(\"MP\", 0x76, 1, 0x000), /* Northern Mariana Islands (USA) */\r\n\tCOUNTRY_CHPLAN_ENT(\"MQ\", 0x26, 1, 0x640), /* Martinique (France) */\r\n\tCOUNTRY_CHPLAN_ENT(\"MR\", 0x26, 1, 0x6A0), /* Mauritania */\r\n\tCOUNTRY_CHPLAN_ENT(\"MS\", 0x26, 1, 0x000), /* Montserrat (UK) */\r\n\tCOUNTRY_CHPLAN_ENT(\"MT\", 0x26, 1, 0x7FB), /* Malta */\r\n\tCOUNTRY_CHPLAN_ENT(\"MU\", 0x26, 1, 0x6B0), /* Mauritius */\r\n\tCOUNTRY_CHPLAN_ENT(\"MV\", 0x47, 1, 0x000), /* Maldives */\r\n\tCOUNTRY_CHPLAN_ENT(\"MW\", 0x26, 1, 0x6B0), /* Malawi */\r\n\tCOUNTRY_CHPLAN_ENT(\"MX\", 0x4D, 1, 0x7F1), /* Mexico */\r\n\tCOUNTRY_CHPLAN_ENT(\"MY\", 0x63, 1, 0x7F1), /* Malaysia */\r\n\tCOUNTRY_CHPLAN_ENT(\"MZ\", 0x26, 1, 0x7F1), /* Mozambique */\r\n\tCOUNTRY_CHPLAN_ENT(\"NA\", 0x26, 1, 0x700), /* Namibia */\r\n\tCOUNTRY_CHPLAN_ENT(\"NC\", 0x26, 1, 0x000), /* New Caledonia */\r\n\tCOUNTRY_CHPLAN_ENT(\"NE\", 0x26, 1, 0x6B0), /* Niger */\r\n\tCOUNTRY_CHPLAN_ENT(\"NF\", 0x45, 1, 0x000), /* Norfolk Island (Australia) */\r\n\tCOUNTRY_CHPLAN_ENT(\"NG\", 0x75, 1, 0x7F9), /* Nigeria */\r\n\tCOUNTRY_CHPLAN_ENT(\"NI\", 0x76, 1, 0x7F1), /* Nicaragua */\r\n\tCOUNTRY_CHPLAN_ENT(\"NL\", 0x26, 1, 0x7FB), /* Netherlands */\r\n\tCOUNTRY_CHPLAN_ENT(\"NO\", 0x26, 1, 0x7FB), /* Norway */\r\n\tCOUNTRY_CHPLAN_ENT(\"NP\", 0x48, 1, 0x6F0), /* Nepal */\r\n\tCOUNTRY_CHPLAN_ENT(\"NR\", 0x26, 1, 0x000), /* Nauru */\r\n\tCOUNTRY_CHPLAN_ENT(\"NU\", 0x45, 1, 0x000), /* Niue */\r\n\tCOUNTRY_CHPLAN_ENT(\"NZ\", 0x45, 1, 0x7FB), /* New Zealand */\r\n\tCOUNTRY_CHPLAN_ENT(\"OM\", 0x26, 1, 0x7F9), /* Oman */\r\n\tCOUNTRY_CHPLAN_ENT(\"PA\", 0x76, 1, 0x7F1), /* Panama */\r\n\tCOUNTRY_CHPLAN_ENT(\"PE\", 0x76, 1, 0x7F1), /* Peru */\r\n\tCOUNTRY_CHPLAN_ENT(\"PF\", 0x26, 1, 0x000), /* French Polynesia (France) */\r\n\tCOUNTRY_CHPLAN_ENT(\"PG\", 0x35, 1, 0x7F1), /* Papua New Guinea */\r\n\tCOUNTRY_CHPLAN_ENT(\"PH\", 0x35, 1, 0x7F1), /* Philippines */\r\n\tCOUNTRY_CHPLAN_ENT(\"PK\", 0x51, 1, 0x7F1), /* Pakistan */\r\n\tCOUNTRY_CHPLAN_ENT(\"PL\", 0x26, 1, 0x7FB), /* Poland */\r\n\tCOUNTRY_CHPLAN_ENT(\"PM\", 0x26, 1, 0x000), /* Saint Pierre and Miquelon (France) */\r\n\tCOUNTRY_CHPLAN_ENT(\"PR\", 0x76, 1, 0x7F1), /* Puerto Rico */\r\n\tCOUNTRY_CHPLAN_ENT(\"PT\", 0x26, 1, 0x7FB), /* Portugal */\r\n\tCOUNTRY_CHPLAN_ENT(\"PW\", 0x76, 1, 0x000), /* Palau */\r\n\tCOUNTRY_CHPLAN_ENT(\"PY\", 0x76, 1, 0x7F1), /* Paraguay */\r\n\tCOUNTRY_CHPLAN_ENT(\"QA\", 0x35, 1, 0x7F9), /* Qatar */\r\n\tCOUNTRY_CHPLAN_ENT(\"RE\", 0x26, 1, 0x000), /* Reunion (France) */\r\n\tCOUNTRY_CHPLAN_ENT(\"RO\", 0x26, 1, 0x7F1), /* Romania */\r\n\tCOUNTRY_CHPLAN_ENT(\"RS\", 0x26, 1, 0x7F1), /* Serbia, Kosovo */\r\n\tCOUNTRY_CHPLAN_ENT(\"RU\", 0x59, 1, 0x7FB), /* Russia(fac/gost), Kaliningrad */\r\n\tCOUNTRY_CHPLAN_ENT(\"RW\", 0x26, 1, 0x0B0), /* Rwanda */\r\n\tCOUNTRY_CHPLAN_ENT(\"SA\", 0x35, 1, 0x7FB), /* Saudi Arabia */\r\n\tCOUNTRY_CHPLAN_ENT(\"SB\", 0x26, 1, 0x000), /* Solomon Islands */\r\n\tCOUNTRY_CHPLAN_ENT(\"SC\", 0x76, 1, 0x690), /* Seychelles */\r\n\tCOUNTRY_CHPLAN_ENT(\"SE\", 0x26, 1, 0x7FB), /* Sweden */\r\n\tCOUNTRY_CHPLAN_ENT(\"SG\", 0x35, 1, 0x7FB), /* Singapore */\r\n\tCOUNTRY_CHPLAN_ENT(\"SH\", 0x26, 1, 0x000), /* Saint Helena (UK) */\r\n\tCOUNTRY_CHPLAN_ENT(\"SI\", 0x26, 1, 0x7FB), /* Slovenia */\r\n\tCOUNTRY_CHPLAN_ENT(\"SJ\", 0x26, 1, 0x000), /* Svalbard (Norway) */\r\n\tCOUNTRY_CHPLAN_ENT(\"SK\", 0x26, 1, 0x7FB), /* Slovakia */\r\n\tCOUNTRY_CHPLAN_ENT(\"SL\", 0x26, 1, 0x6B0), /* Sierra Leone */\r\n\tCOUNTRY_CHPLAN_ENT(\"SM\", 0x26, 1, 0x000), /* San Marino */\r\n\tCOUNTRY_CHPLAN_ENT(\"SN\", 0x26, 1, 0x7F1), /* Senegal */\r\n\tCOUNTRY_CHPLAN_ENT(\"SO\", 0x26, 1, 0x000), /* Somalia */\r\n\tCOUNTRY_CHPLAN_ENT(\"SR\", 0x74, 1, 0x000), /* Suriname */\r\n\tCOUNTRY_CHPLAN_ENT(\"ST\", 0x76, 1, 0x680), /* Sao Tome and Principe */\r\n\tCOUNTRY_CHPLAN_ENT(\"SV\", 0x30, 1, 0x7F1), /* El Salvador */\r\n\tCOUNTRY_CHPLAN_ENT(\"SX\", 0x76, 1, 0x000), /* Sint Marteen */\r\n\tCOUNTRY_CHPLAN_ENT(\"SZ\", 0x26, 1, 0x020), /* Swaziland */\r\n\tCOUNTRY_CHPLAN_ENT(\"TC\", 0x26, 1, 0x000), /* Turks and Caicos Islands (UK) */\r\n\tCOUNTRY_CHPLAN_ENT(\"TD\", 0x26, 1, 0x6B0), /* Chad */\r\n\tCOUNTRY_CHPLAN_ENT(\"TF\", 0x26, 1, 0x680), /* French Southern and Antarctic Lands (FR Southern Territories) */\r\n\tCOUNTRY_CHPLAN_ENT(\"TG\", 0x26, 1, 0x6B0), /* Togo */\r\n\tCOUNTRY_CHPLAN_ENT(\"TH\", 0x35, 1, 0x7F1), /* Thailand */\r\n\tCOUNTRY_CHPLAN_ENT(\"TJ\", 0x26, 1, 0x640), /* Tajikistan */\r\n\tCOUNTRY_CHPLAN_ENT(\"TK\", 0x45, 1, 0x000), /* Tokelau */\r\n\tCOUNTRY_CHPLAN_ENT(\"TM\", 0x26, 1, 0x000), /* Turkmenistan */\r\n\tCOUNTRY_CHPLAN_ENT(\"TN\", 0x47, 1, 0x7F1), /* Tunisia */\r\n\tCOUNTRY_CHPLAN_ENT(\"TO\", 0x26, 1, 0x000), /* Tonga */\r\n\tCOUNTRY_CHPLAN_ENT(\"TR\", 0x26, 1, 0x7F1), /* Turkey, Northern Cyprus */\r\n\tCOUNTRY_CHPLAN_ENT(\"TT\", 0x76, 1, 0x3F1), /* Trinidad & Tobago */\r\n\tCOUNTRY_CHPLAN_ENT(\"TV\", 0x21, 0, 0x000), /* Tuvalu */\r\n\tCOUNTRY_CHPLAN_ENT(\"TW\", 0x76, 1, 0x7FF), /* Taiwan */\r\n\tCOUNTRY_CHPLAN_ENT(\"TZ\", 0x26, 1, 0x6F0), /* Tanzania */\r\n\tCOUNTRY_CHPLAN_ENT(\"UA\", 0x36, 1, 0x7FB), /* Ukraine */\r\n\tCOUNTRY_CHPLAN_ENT(\"UG\", 0x26, 1, 0x6F1), /* Uganda */\r\n\tCOUNTRY_CHPLAN_ENT(\"US\", 0x76, 1, 0x7FF), /* United States of America (USA) */\r\n\tCOUNTRY_CHPLAN_ENT(\"UY\", 0x30, 1, 0x7F1), /* Uruguay */\r\n\tCOUNTRY_CHPLAN_ENT(\"UZ\", 0x47, 1, 0x6F0), /* Uzbekistan */\r\n\tCOUNTRY_CHPLAN_ENT(\"VA\", 0x26, 1, 0x000), /* Holy See (Vatican City) */\r\n\tCOUNTRY_CHPLAN_ENT(\"VC\", 0x76, 1, 0x010), /* Saint Vincent and the Grenadines */\r\n\tCOUNTRY_CHPLAN_ENT(\"VE\", 0x30, 1, 0x7F1), /* Venezuela */\r\n\tCOUNTRY_CHPLAN_ENT(\"VG\", 0x76, 1, 0x000), /* British Virgin Islands (UK) */\r\n\tCOUNTRY_CHPLAN_ENT(\"VI\", 0x76, 1, 0x000), /* United States Virgin Islands (USA) */\r\n\tCOUNTRY_CHPLAN_ENT(\"VN\", 0x35, 1, 0x7F1), /* Vietnam */\r\n\tCOUNTRY_CHPLAN_ENT(\"VU\", 0x26, 1, 0x000), /* Vanuatu */\r\n\tCOUNTRY_CHPLAN_ENT(\"WF\", 0x26, 1, 0x000), /* Wallis and Futuna (France) */\r\n\tCOUNTRY_CHPLAN_ENT(\"WS\", 0x76, 1, 0x000), /* Samoa */\r\n\tCOUNTRY_CHPLAN_ENT(\"YE\", 0x26, 1, 0x040), /* Yemen */\r\n\tCOUNTRY_CHPLAN_ENT(\"YT\", 0x26, 1, 0x680), /* Mayotte (France) */\r\n\tCOUNTRY_CHPLAN_ENT(\"ZA\", 0x35, 1, 0x7F1), /* South Africa */\r\n\tCOUNTRY_CHPLAN_ENT(\"ZM\", 0x26, 1, 0x6B0), /* Zambia */\r\n\tCOUNTRY_CHPLAN_ENT(\"ZW\", 0x26, 1, 0x7F1), /* Zimbabwe */\r\n};\r\n\r\n/*\r\n* rtw_get_chplan_from_country -\r\n* @country_code: string of country code\r\n*\r\n* Return pointer of struct country_chplan entry or NULL when unsupported country_code is given\r\n*/\r\nconst struct country_chplan *rtw_get_chplan_from_country(const char *country_code)\r\n{\r\n#if RTW_DEF_MODULE_REGULATORY_CERT\r\n\tconst struct country_chplan *exc_ent = NULL;\r\n#endif\r\n\tconst struct country_chplan *ent = NULL;\r\n\tconst struct country_chplan *map = NULL;\r\n\tu16 map_sz = 0;\r\n\tchar code[2];\r\n\tint i;\r\n\r\n\tcode[0] = alpha_to_upper(country_code[0]);\r\n\tcode[1] = alpha_to_upper(country_code[1]);\r\n\r\n#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP\r\n\tmap = CUSTOMIZED_country_chplan_map;\r\n\tmap_sz = sizeof(CUSTOMIZED_country_chplan_map) / sizeof(struct country_chplan);\r\n#else\r\n\t#if RTW_DEF_MODULE_REGULATORY_CERT\r\n\texc_ent = rtw_def_module_get_chplan_from_country(code);\r\n\t#endif\r\n\tmap = country_chplan_map;\r\n\tmap_sz = sizeof(country_chplan_map) / sizeof(struct country_chplan);\r\n#endif\r\n\r\n\tfor (i = 0; i < map_sz; i++) {\r\n\t\tif (strncmp(code, map[i].alpha2, 2) == 0) {\r\n\t\t\tent = &map[i];\r\n\t\t\tbreak;\r\n\t\t}\r\n\t}\r\n\r\n\t#if RTW_DEF_MODULE_REGULATORY_CERT\r\n\tif (!ent || !(COUNTRY_CHPLAN_DEF_MODULE_FALGS(ent) & RTW_DEF_MODULE_REGULATORY_CERT))\r\n\t\texc_ent = ent = NULL;\r\n\tif (exc_ent)\r\n\t\tent = exc_ent;\r\n\t#endif\r\n\r\n\treturn ent;\r\n}\r\n\r\nvoid dump_country_chplan(void *sel, const struct country_chplan *ent)\r\n{\r\n\tRTW_PRINT_SEL(sel, \"\\\"%c%c\\\", 0x%02X%s\\n\"\r\n\t\t, ent->alpha2[0], ent->alpha2[1], ent->chplan\r\n\t\t, COUNTRY_CHPLAN_EN_11AC(ent) ? \" ac\" : \"\"\r\n\t);\r\n}\r\n\r\nvoid dump_country_chplan_map(void *sel)\r\n{\r\n\tconst struct country_chplan *ent;\r\n\tu8 code[2];\r\n\r\n#if RTW_DEF_MODULE_REGULATORY_CERT\r\n\tRTW_PRINT_SEL(sel, \"RTW_DEF_MODULE_REGULATORY_CERT:0x%x\\n\", RTW_DEF_MODULE_REGULATORY_CERT);\r\n#endif\r\n#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP\r\n\tRTW_PRINT_SEL(sel, \"CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP\\n\");\r\n#endif\r\n\r\n\tfor (code[0] = 'A'; code[0] <= 'Z'; code[0]++) {\r\n\t\tfor (code[1] = 'A'; code[1] <= 'Z'; code[1]++) {\r\n\t\t\tent = rtw_get_chplan_from_country(code);\r\n\t\t\tif (!ent)\r\n\t\t\t\tcontinue;\r\n\r\n\t\t\tdump_country_chplan(sel, ent);\r\n\t\t}\r\n\t}\r\n}\r\n\r\nvoid dump_chplan_id_list(void *sel)\r\n{\r\n\tu8 first = 1;\r\n\tint i;\r\n\r\n\tfor (i = 0; i < RTW_CHPLAN_MAX; i++) {\r\n\t\tif (!rtw_is_channel_plan_valid(i))\r\n\t\t\tcontinue;\r\n\r\n\t\tif (first) {\r\n\t\t\tRTW_PRINT_SEL(sel, \"0x%02X \", i);\r\n\t\t\tfirst = 0;\r\n\t\t} else\r\n\t\t\t_RTW_PRINT_SEL(sel, \"0x%02X \", i);\r\n\t}\r\n\r\n\t_RTW_PRINT_SEL(sel, \"0x7F\\n\");\r\n}\r\n\r\nvoid dump_chplan_test(void *sel)\r\n{\r\n\tint i, j;\r\n\r\n\t/* check invalid channel */\r\n\tfor (i = 0; i < RTW_RD_2G_MAX; i++) {\r\n\t\tfor (j = 0; j < CH_LIST_LEN(RTW_ChannelPlan2G[i]); j++) {\r\n\t\t\tif (rtw_ch2freq(CH_LIST_CH(RTW_ChannelPlan2G[i], j)) == 0)\r\n\t\t\t\tRTW_PRINT_SEL(sel, \"invalid ch:%u at (%d,%d)\\n\", CH_LIST_CH(RTW_ChannelPlan2G[i], j), i, j);\r\n\t\t}\r\n\t}\r\n\r\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\r\n\tfor (i = 0; i < RTW_RD_5G_MAX; i++) {\r\n\t\tfor (j = 0; j < CH_LIST_LEN(RTW_ChannelPlan5G[i]); j++) {\r\n\t\t\tif (rtw_ch2freq(CH_LIST_CH(RTW_ChannelPlan5G[i], j)) == 0)\r\n\t\t\t\tRTW_PRINT_SEL(sel, \"invalid ch:%u at (%d,%d)\\n\", CH_LIST_CH(RTW_ChannelPlan5G[i], j), i, j);\r\n\t\t}\r\n\t}\r\n#endif\r\n}\r\n\r\nvoid dump_chplan_ver(void *sel)\r\n{\r\n\tRTW_PRINT_SEL(sel, \"%s-%s\\n\", RTW_DOMAIN_MAP_VER, RTW_COUNTRY_MAP_VER);\r\n}\r\n"
  },
  {
    "path": "core/rtw_chplan.h",
    "content": "/******************************************************************************\r\n *\r\n * Copyright(c) 2007 - 2018 Realtek Corporation.\r\n *\r\n * This program is free software; you can redistribute it and/or modify it\r\n * under the terms of version 2 of the GNU General Public License as\r\n * published by the Free Software Foundation.\r\n *\r\n * This program is distributed in the hope that it will be useful, but WITHOUT\r\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r\n * more details.\r\n *\r\n *****************************************************************************/\r\n#ifndef __RTW_CHPLAN_H__\r\n#define __RTW_CHPLAN_H__\r\n\r\nenum rtw_chplan_id {\r\n\t/* ===== 0x00 ~ 0x1F, legacy channel plan ===== */\r\n\tRTW_CHPLAN_FCC = 0x00,\r\n\tRTW_CHPLAN_IC = 0x01,\r\n\tRTW_CHPLAN_ETSI = 0x02,\r\n\tRTW_CHPLAN_SPAIN = 0x03,\r\n\tRTW_CHPLAN_FRANCE = 0x04,\r\n\tRTW_CHPLAN_MKK = 0x05,\r\n\tRTW_CHPLAN_MKK1 = 0x06,\r\n\tRTW_CHPLAN_ISRAEL = 0x07,\r\n\tRTW_CHPLAN_TELEC = 0x08,\r\n\tRTW_CHPLAN_GLOBAL_DOAMIN = 0x09,\r\n\tRTW_CHPLAN_WORLD_WIDE_13 = 0x0A,\r\n\tRTW_CHPLAN_TAIWAN = 0x0B,\r\n\tRTW_CHPLAN_CHINA = 0x0C,\r\n\tRTW_CHPLAN_SINGAPORE_INDIA_MEXICO = 0x0D,\r\n\tRTW_CHPLAN_KOREA = 0x0E,\r\n\tRTW_CHPLAN_TURKEY = 0x0F,\r\n\tRTW_CHPLAN_JAPAN = 0x10,\r\n\tRTW_CHPLAN_FCC_NO_DFS = 0x11,\r\n\tRTW_CHPLAN_JAPAN_NO_DFS = 0x12,\r\n\tRTW_CHPLAN_WORLD_WIDE_5G = 0x13,\r\n\tRTW_CHPLAN_TAIWAN_NO_DFS = 0x14,\r\n\r\n\t/* ===== 0x20 ~ 0x7F, new channel plan ===== */\r\n\tRTW_CHPLAN_WORLD_NULL = 0x20,\r\n\tRTW_CHPLAN_ETSI1_NULL = 0x21,\r\n\tRTW_CHPLAN_FCC1_NULL = 0x22,\r\n\tRTW_CHPLAN_MKK1_NULL = 0x23,\r\n\tRTW_CHPLAN_ETSI2_NULL = 0x24,\r\n\tRTW_CHPLAN_FCC1_FCC1 = 0x25,\r\n\tRTW_CHPLAN_WORLD_ETSI1 = 0x26,\r\n\tRTW_CHPLAN_MKK1_MKK1 = 0x27,\r\n\tRTW_CHPLAN_WORLD_KCC1 = 0x28,\r\n\tRTW_CHPLAN_WORLD_FCC2 = 0x29,\r\n\tRTW_CHPLAN_FCC2_NULL = 0x2A,\r\n\tRTW_CHPLAN_IC1_IC2 = 0x2B,\r\n\tRTW_CHPLAN_MKK2_NULL = 0x2C,\r\n\tRTW_CHPLAN_WORLD_CHILE1= 0x2D,\r\n\tRTW_CHPLAN_WORLD1_WORLD1 = 0x2E,\r\n\tRTW_CHPLAN_WORLD_CHILE2 = 0x2F,\r\n\tRTW_CHPLAN_WORLD_FCC3 = 0x30,\r\n\tRTW_CHPLAN_WORLD_FCC4 = 0x31,\r\n\tRTW_CHPLAN_WORLD_FCC5 = 0x32,\r\n\tRTW_CHPLAN_WORLD_FCC6 = 0x33,\r\n\tRTW_CHPLAN_FCC1_FCC7 = 0x34,\r\n\tRTW_CHPLAN_WORLD_ETSI2 = 0x35,\r\n\tRTW_CHPLAN_WORLD_ETSI3 = 0x36,\r\n\tRTW_CHPLAN_MKK1_MKK2 = 0x37,\r\n\tRTW_CHPLAN_MKK1_MKK3 = 0x38,\r\n\tRTW_CHPLAN_FCC1_NCC1 = 0x39,\r\n\tRTW_CHPLAN_ETSI1_ETSI1 = 0x3A,\r\n\tRTW_CHPLAN_ETSI1_ACMA1 = 0x3B,\r\n\tRTW_CHPLAN_ETSI1_ETSI6 = 0x3C,\r\n\tRTW_CHPLAN_ETSI1_ETSI12 = 0x3D,\r\n\tRTW_CHPLAN_KCC1_KCC2 = 0x3E,\r\n\tRTW_CHPLAN_FCC1_FCC11 = 0x3F,\r\n\tRTW_CHPLAN_FCC1_NCC2 = 0x40,\r\n\tRTW_CHPLAN_GLOBAL_NULL = 0x41,\r\n\tRTW_CHPLAN_ETSI1_ETSI4 = 0x42,\r\n\tRTW_CHPLAN_FCC1_FCC2 = 0x43,\r\n\tRTW_CHPLAN_FCC1_NCC3 = 0x44,\r\n\tRTW_CHPLAN_WORLD_ACMA1 = 0x45,\r\n\tRTW_CHPLAN_FCC1_FCC8 = 0x46,\r\n\tRTW_CHPLAN_WORLD_ETSI6 = 0x47,\r\n\tRTW_CHPLAN_WORLD_ETSI7 = 0x48,\r\n\tRTW_CHPLAN_WORLD_ETSI8 = 0x49,\r\n\tRTW_CHPLAN_IC2_IC2 = 0x4A,\r\n\tRTW_CHPLAN_KCC1_KCC3 = 0x4B,\r\n\tRTW_CHPLAN_FCC1_FCC15 = 0x4C,\r\n\tRTW_CHPLAN_FCC2_MEX1 = 0x4D,\r\n\tRTW_CHPLAN_ETSI1_ETSI22 = 0x4E,\r\n\tRTW_CHPLAN_WORLD_ETSI9 = 0x50,\r\n\tRTW_CHPLAN_WORLD_ETSI10 = 0x51,\r\n\tRTW_CHPLAN_WORLD_ETSI11 = 0x52,\r\n\tRTW_CHPLAN_FCC1_NCC4 = 0x53,\r\n\tRTW_CHPLAN_WORLD_ETSI12 = 0x54,\r\n\tRTW_CHPLAN_FCC1_FCC9 = 0x55,\r\n\tRTW_CHPLAN_WORLD_ETSI13 = 0x56,\r\n\tRTW_CHPLAN_FCC1_FCC10 = 0x57,\r\n\tRTW_CHPLAN_MKK2_MKK4 = 0x58,\r\n\tRTW_CHPLAN_WORLD_ETSI14 = 0x59,\r\n\tRTW_CHPLAN_FCC1_FCC5 = 0x60,\r\n\tRTW_CHPLAN_FCC2_FCC7 = 0x61,\r\n\tRTW_CHPLAN_FCC2_FCC1 = 0x62,\r\n\tRTW_CHPLAN_WORLD_ETSI15 = 0x63,\r\n\tRTW_CHPLAN_MKK2_MKK5 = 0x64,\r\n\tRTW_CHPLAN_ETSI1_ETSI16 = 0x65,\r\n\tRTW_CHPLAN_FCC1_FCC14 = 0x66,\r\n\tRTW_CHPLAN_FCC1_FCC12 = 0x67,\r\n\tRTW_CHPLAN_FCC2_FCC14 = 0x68,\r\n\tRTW_CHPLAN_FCC2_FCC12 = 0x69,\r\n\tRTW_CHPLAN_ETSI1_ETSI17 = 0x6A,\r\n\tRTW_CHPLAN_WORLD_FCC16 = 0x6B,\r\n\tRTW_CHPLAN_WORLD_FCC13 = 0x6C,\r\n\tRTW_CHPLAN_FCC2_FCC15 = 0x6D,\r\n\tRTW_CHPLAN_WORLD_FCC12 = 0x6E,\r\n\tRTW_CHPLAN_NULL_ETSI8 = 0x6F,\r\n\tRTW_CHPLAN_NULL_ETSI18 = 0x70,\r\n\tRTW_CHPLAN_NULL_ETSI17 = 0x71,\r\n\tRTW_CHPLAN_NULL_ETSI19 = 0x72,\r\n\tRTW_CHPLAN_WORLD_FCC7 = 0x73,\r\n\tRTW_CHPLAN_FCC2_FCC17 = 0x74,\r\n\tRTW_CHPLAN_WORLD_ETSI20 = 0x75,\r\n\tRTW_CHPLAN_FCC2_FCC11 = 0x76,\r\n\tRTW_CHPLAN_WORLD_ETSI21 = 0x77,\r\n\tRTW_CHPLAN_FCC1_FCC18 = 0x78,\r\n\tRTW_CHPLAN_MKK2_MKK1 = 0x79,\r\n\r\n\tRTW_CHPLAN_MAX,\r\n\tRTW_CHPLAN_REALTEK_DEFINE = 0x7F,\r\n\tRTW_CHPLAN_UNSPECIFIED = 0xFF,\r\n};\r\n\r\nu8 rtw_chplan_get_default_regd(u8 id);\r\nbool rtw_chplan_is_empty(u8 id);\r\n#define rtw_is_channel_plan_valid(chplan) (((chplan) < RTW_CHPLAN_MAX || (chplan) == RTW_CHPLAN_REALTEK_DEFINE) && !rtw_chplan_is_empty(chplan))\r\n#define rtw_is_legacy_channel_plan(chplan) ((chplan) < 0x20)\r\n\r\nstruct _RT_CHANNEL_INFO;\r\nu8 init_channel_set(_adapter *padapter, u8 ChannelPlan, struct _RT_CHANNEL_INFO *channel_set);\r\n\r\n#define IS_ALPHA2_NO_SPECIFIED(_alpha2) ((*((u16 *)(_alpha2))) == 0xFFFF)\r\n\r\n#define RTW_MODULE_RTL8821AE_HMC_M2\t\tBIT0\t/* RTL8821AE(HMC + M.2) */\r\n#define RTW_MODULE_RTL8821AU\t\t\tBIT1\t/* RTL8821AU */\r\n#define RTW_MODULE_RTL8812AENF_NGFF\t\tBIT2\t/* RTL8812AENF(8812AE+8761)_NGFF */\r\n#define RTW_MODULE_RTL8812AEBT_HMC\t\tBIT3\t/* RTL8812AEBT(8812AE+8761)_HMC */\r\n#define RTW_MODULE_RTL8188EE_HMC_M2\t\tBIT4\t/* RTL8188EE(HMC + M.2) */\r\n#define RTW_MODULE_RTL8723BE_HMC_M2\t\tBIT5\t/* RTL8723BE(HMC + M.2) */\r\n#define RTW_MODULE_RTL8723BS_NGFF1216\tBIT6\t/* RTL8723BS(NGFF1216) */\r\n#define RTW_MODULE_RTL8192EEBT_HMC_M2\tBIT7\t/* RTL8192EEBT(8192EE+8761AU)_(HMC + M.2) */\r\n#define RTW_MODULE_RTL8723DE_NGFF1630\tBIT8\t/* RTL8723DE(NGFF1630) */\r\n#define RTW_MODULE_RTL8822BE\t\t\tBIT9\t/* RTL8822BE */\r\n#define RTW_MODULE_RTL8821CE\t\t\tBIT10\t/* RTL8821CE */\r\n\r\nstruct country_chplan {\r\n\tchar alpha2[2];\r\n\tu8 chplan;\r\n#ifdef CONFIG_80211AC_VHT\r\n\tu8 en_11ac;\r\n#endif\r\n#if RTW_DEF_MODULE_REGULATORY_CERT\r\n\tu16 def_module_flags; /* RTW_MODULE_RTLXXX */\r\n#endif\r\n};\r\n\r\n#ifdef CONFIG_80211AC_VHT\r\n#define COUNTRY_CHPLAN_EN_11AC(_ent) ((_ent)->en_11ac)\r\n#else\r\n#define COUNTRY_CHPLAN_EN_11AC(_ent) 0\r\n#endif\r\n\r\n#if RTW_DEF_MODULE_REGULATORY_CERT\r\n#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) ((_ent)->def_module_flags)\r\n#else\r\n#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) 0\r\n#endif\r\n\r\nconst struct country_chplan *rtw_get_chplan_from_country(const char *country_code);\r\n\r\nvoid dump_country_chplan(void *sel, const struct country_chplan *ent);\r\nvoid dump_country_chplan_map(void *sel);\r\nvoid dump_chplan_id_list(void *sel);\r\nvoid dump_chplan_test(void *sel);\r\nvoid dump_chplan_ver(void *sel);\r\n\r\n#endif /* __RTW_CHPLAN_H__ */\r\n"
  },
  {
    "path": "core/rtw_cmd.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_CMD_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\n#ifndef DBG_CMD_EXECUTE\n\t#define DBG_CMD_EXECUTE 0\n#endif\n\n/*\nCaller and the rtw_cmd_thread can protect cmd_q by spin_lock.\nNo irqsave is necessary.\n*/\n\nsint\t_rtw_init_cmd_priv(struct\tcmd_priv *pcmdpriv)\n{\n\tsint res = _SUCCESS;\n\n\n\t_rtw_init_sema(&(pcmdpriv->cmd_queue_sema), 0);\n\t/* _rtw_init_sema(&(pcmdpriv->cmd_done_sema), 0); */\n\t_rtw_init_sema(&(pcmdpriv->start_cmdthread_sema), 0);\n\n\t_rtw_init_queue(&(pcmdpriv->cmd_queue));\n\n\t/* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */\n\n\tpcmdpriv->cmd_seq = 1;\n\n\tpcmdpriv->cmd_allocated_buf = rtw_zmalloc(MAX_CMDSZ + CMDBUFF_ALIGN_SZ);\n\n\tif (pcmdpriv->cmd_allocated_buf == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpcmdpriv->cmd_buf = pcmdpriv->cmd_allocated_buf  +  CMDBUFF_ALIGN_SZ - ((SIZE_PTR)(pcmdpriv->cmd_allocated_buf) & (CMDBUFF_ALIGN_SZ - 1));\n\n\tpcmdpriv->rsp_allocated_buf = rtw_zmalloc(MAX_RSPSZ + 4);\n\n\tif (pcmdpriv->rsp_allocated_buf == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpcmdpriv->rsp_buf = pcmdpriv->rsp_allocated_buf  +  4 - ((SIZE_PTR)(pcmdpriv->rsp_allocated_buf) & 3);\n\n\tpcmdpriv->cmd_issued_cnt = pcmdpriv->cmd_done_cnt = pcmdpriv->rsp_cnt = 0;\n\n\t_rtw_mutex_init(&pcmdpriv->sctx_mutex);\nexit:\n\n\n\treturn res;\n\n}\n\n#ifdef CONFIG_C2H_WK\nstatic void c2h_wk_callback(_workitem *work)\n{\n\tstruct evt_priv *evtpriv = container_of(work, struct evt_priv, c2h_wk);\n\t_adapter *adapter = container_of(evtpriv, _adapter, evtpriv);\n\tu8 *c2h_evt;\n\tc2h_id_filter direct_hdl_filter = rtw_hal_c2h_id_handle_directly;\n\tu8 id, seq, plen;\n\tu8 *payload;\n\n\tevtpriv->c2h_wk_alive = _TRUE;\n\n\twhile (!rtw_cbuf_empty(evtpriv->c2h_queue)) {\n\t\tc2h_evt = (u8 *)rtw_cbuf_pop(evtpriv->c2h_queue);\n\t\tif (c2h_evt != NULL) {\n\t\t\t/* This C2H event is read, clear it */\n\t\t\tc2h_evt_clear(adapter);\n\t\t} else {\n\t\t\tc2h_evt = (u8 *)rtw_malloc(C2H_REG_LEN);\n\t\t\tif (c2h_evt == NULL) {\n\t\t\t\trtw_warn_on(1);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\t/* This C2H event is not read, read & clear now */\n\t\t\tif (rtw_hal_c2h_evt_read(adapter, c2h_evt) != _SUCCESS) {\n\t\t\t\trtw_mfree(c2h_evt, C2H_REG_LEN);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t}\n\n\t\t/* Special pointer to trigger c2h_evt_clear only */\n\t\tif ((void *)c2h_evt == (void *)evtpriv)\n\t\t\tcontinue;\n\n\t\tif (!rtw_hal_c2h_valid(adapter, c2h_evt)\n\t\t\t|| rtw_hal_c2h_reg_hdr_parse(adapter, c2h_evt, &id, &seq, &plen, &payload) != _SUCCESS\n\t\t) {\n\t\t\trtw_mfree(c2h_evt, C2H_REG_LEN);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (direct_hdl_filter(adapter, id, seq, plen, payload) == _TRUE) {\n\t\t\t/* Handle directly */\n\t\t\trtw_hal_c2h_handler(adapter, id, seq, plen, payload);\n\t\t\trtw_mfree(c2h_evt, C2H_REG_LEN);\n\t\t} else {\n\t\t\t/* Enqueue into cmd_thread for others */\n\t\t\trtw_c2h_reg_wk_cmd(adapter, c2h_evt);\n\t\t\trtw_mfree(c2h_evt, C2H_REG_LEN);\n\t\t}\n\t}\n\n\tevtpriv->c2h_wk_alive = _FALSE;\n}\n#endif /* CONFIG_C2H_WK */\n\nsint _rtw_init_evt_priv(struct evt_priv *pevtpriv)\n{\n\tsint res = _SUCCESS;\n\n\n#ifdef CONFIG_H2CLBK\n\t_rtw_init_sema(&(pevtpriv->lbkevt_done), 0);\n\tpevtpriv->lbkevt_limit = 0;\n\tpevtpriv->lbkevt_num = 0;\n\tpevtpriv->cmdevt_parm = NULL;\n#endif\n\n\t/* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */\n\tATOMIC_SET(&pevtpriv->event_seq, 0);\n\tpevtpriv->evt_done_cnt = 0;\n\n#ifdef CONFIG_EVENT_THREAD_MODE\n\n\t_rtw_init_sema(&(pevtpriv->evt_notify), 0);\n\n\tpevtpriv->evt_allocated_buf = rtw_zmalloc(MAX_EVTSZ + 4);\n\tif (pevtpriv->evt_allocated_buf == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tpevtpriv->evt_buf = pevtpriv->evt_allocated_buf  +  4 - ((unsigned int)(pevtpriv->evt_allocated_buf) & 3);\n\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\tpevtpriv->allocated_c2h_mem = rtw_zmalloc(C2H_MEM_SZ + 4);\n\n\tif (pevtpriv->allocated_c2h_mem == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpevtpriv->c2h_mem = pevtpriv->allocated_c2h_mem +  4\\\n\t\t\t    - ((u32)(pevtpriv->allocated_c2h_mem) & 3);\n#endif /* end of CONFIG_SDIO_HCI */\n\n\t_rtw_init_queue(&(pevtpriv->evt_queue));\n\nexit:\n\n#endif /* end of CONFIG_EVENT_THREAD_MODE */\n\n#ifdef CONFIG_C2H_WK\n\t_init_workitem(&pevtpriv->c2h_wk, c2h_wk_callback, NULL);\n\tpevtpriv->c2h_wk_alive = _FALSE;\n\tpevtpriv->c2h_queue = rtw_cbuf_alloc(C2H_QUEUE_MAX_LEN + 1);\n#endif\n\n\n\treturn res;\n}\n\nvoid _rtw_free_evt_priv(struct\tevt_priv *pevtpriv)\n{\n\n\n#ifdef CONFIG_EVENT_THREAD_MODE\n\t_rtw_free_sema(&(pevtpriv->evt_notify));\n\n\tif (pevtpriv->evt_allocated_buf)\n\t\trtw_mfree(pevtpriv->evt_allocated_buf, MAX_EVTSZ + 4);\n#endif\n\n#ifdef CONFIG_C2H_WK\n\t_cancel_workitem_sync(&pevtpriv->c2h_wk);\n\twhile (pevtpriv->c2h_wk_alive)\n\t\trtw_msleep_os(10);\n\n\twhile (!rtw_cbuf_empty(pevtpriv->c2h_queue)) {\n\t\tvoid *c2h;\n\t\tc2h = rtw_cbuf_pop(pevtpriv->c2h_queue);\n\t\tif (c2h != NULL && c2h != (void *)pevtpriv)\n\t\t\trtw_mfree(c2h, 16);\n\t}\n\trtw_cbuf_free(pevtpriv->c2h_queue);\n#endif\n\n\n\n}\n\nvoid _rtw_free_cmd_priv(struct\tcmd_priv *pcmdpriv)\n{\n\n\tif (pcmdpriv) {\n\t\t_rtw_spinlock_free(&(pcmdpriv->cmd_queue.lock));\n\t\t_rtw_free_sema(&(pcmdpriv->cmd_queue_sema));\n\t\t/* _rtw_free_sema(&(pcmdpriv->cmd_done_sema)); */\n\t\t_rtw_free_sema(&(pcmdpriv->start_cmdthread_sema));\n\n\t\tif (pcmdpriv->cmd_allocated_buf)\n\t\t\trtw_mfree(pcmdpriv->cmd_allocated_buf, MAX_CMDSZ + CMDBUFF_ALIGN_SZ);\n\n\t\tif (pcmdpriv->rsp_allocated_buf)\n\t\t\trtw_mfree(pcmdpriv->rsp_allocated_buf, MAX_RSPSZ + 4);\n\n\t\t_rtw_mutex_free(&pcmdpriv->sctx_mutex);\n\t}\n}\n\n/*\nCalling Context:\n\nrtw_enqueue_cmd can only be called between kernel thread,\nsince only spin_lock is used.\n\nISR/Call-Back functions can't call this sub-function.\n\n*/\n#ifdef DBG_CMD_QUEUE\nextern u8 dump_cmd_id;\n#endif\n\nsint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head)\n{\n\t_irqL irqL;\n\n\n\tif (obj == NULL)\n\t\tgoto exit;\n\n\t/* _enter_critical_bh(&queue->lock, &irqL); */\n\t_enter_critical(&queue->lock, &irqL);\n\n\tif (to_head)\n\t\trtw_list_insert_head(&obj->list, &queue->queue);\n\telse\n\t\trtw_list_insert_tail(&obj->list, &queue->queue);\n\n#ifdef DBG_CMD_QUEUE\n\tif (dump_cmd_id) {\n\t\tprintk(\"%s===> cmdcode:0x%02x\\n\", __FUNCTION__, obj->cmdcode);\n\t\tif (obj->cmdcode == GEN_CMD_CODE(_Set_MLME_EVT)) {\n\t\t\tif (obj->parmbuf) {\n\t\t\t\tstruct C2HEvent_Header *pc2h_evt_hdr = (struct C2HEvent_Header *)(obj->parmbuf);\n\t\t\t\tprintk(\"pc2h_evt_hdr->ID:0x%02x(%d)\\n\", pc2h_evt_hdr->ID, pc2h_evt_hdr->ID);\n\t\t\t}\n\t\t}\n\t\tif (obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) {\n\t\t\tif (obj->parmbuf) {\n\t\t\t\tstruct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)(obj->parmbuf);\n\t\t\t\tprintk(\"pdrvextra_cmd_parm->ec_id:0x%02x\\n\", pdrvextra_cmd_parm->ec_id);\n\t\t\t}\n\t\t}\n\t}\n\n\tif (queue->queue.prev->next != &queue->queue) {\n\t\tRTW_INFO(\"[%d] head %p, tail %p, tail->prev->next %p[tail], tail->next %p[head]\\n\", __LINE__,\n\t\t\t&queue->queue, queue->queue.prev, queue->queue.prev->prev->next, queue->queue.prev->next);\n\n\t\tRTW_INFO(\"==========%s============\\n\", __FUNCTION__);\n\t\tRTW_INFO(\"head:%p,obj_addr:%p\\n\", &queue->queue, obj);\n\t\tRTW_INFO(\"padapter: %p\\n\", obj->padapter);\n\t\tRTW_INFO(\"cmdcode: 0x%02x\\n\", obj->cmdcode);\n\t\tRTW_INFO(\"res: %d\\n\", obj->res);\n\t\tRTW_INFO(\"parmbuf: %p\\n\", obj->parmbuf);\n\t\tRTW_INFO(\"cmdsz: %d\\n\", obj->cmdsz);\n\t\tRTW_INFO(\"rsp: %p\\n\", obj->rsp);\n\t\tRTW_INFO(\"rspsz: %d\\n\", obj->rspsz);\n\t\tRTW_INFO(\"sctx: %p\\n\", obj->sctx);\n\t\tRTW_INFO(\"list->next: %p\\n\", obj->list.next);\n\t\tRTW_INFO(\"list->prev: %p\\n\", obj->list.prev);\n\t}\n#endif /* DBG_CMD_QUEUE */\n\n\t/* _exit_critical_bh(&queue->lock, &irqL);\t */\n\t_exit_critical(&queue->lock, &irqL);\n\nexit:\n\n\n\treturn _SUCCESS;\n}\n\nstruct\tcmd_obj\t*_rtw_dequeue_cmd(_queue *queue)\n{\n\t_irqL irqL;\n\tstruct cmd_obj *obj;\n\n\n\t/* _enter_critical_bh(&(queue->lock), &irqL); */\n\t_enter_critical(&queue->lock, &irqL);\n\n#ifdef DBG_CMD_QUEUE\n\tif (queue->queue.prev->next != &queue->queue) {\n\t\tRTW_INFO(\"[%d] head %p, tail %p, tail->prev->next %p[tail], tail->next %p[head]\\n\", __LINE__,\n\t\t\t&queue->queue, queue->queue.prev, queue->queue.prev->prev->next, queue->queue.prev->next);\n\t}\n#endif /* DBG_CMD_QUEUE */\n\n\n\tif (rtw_is_list_empty(&(queue->queue)))\n\t\tobj = NULL;\n\telse {\n\t\tobj = LIST_CONTAINOR(get_next(&(queue->queue)), struct cmd_obj, list);\n\n#ifdef DBG_CMD_QUEUE\n\t\tif (queue->queue.prev->next != &queue->queue) {\n\t\t\tRTW_INFO(\"==========%s============\\n\", __FUNCTION__);\n\t\t\tRTW_INFO(\"head:%p,obj_addr:%p\\n\", &queue->queue, obj);\n\t\t\tRTW_INFO(\"padapter: %p\\n\", obj->padapter);\n\t\t\tRTW_INFO(\"cmdcode: 0x%02x\\n\", obj->cmdcode);\n\t\t\tRTW_INFO(\"res: %d\\n\", obj->res);\n\t\t\tRTW_INFO(\"parmbuf: %p\\n\", obj->parmbuf);\n\t\t\tRTW_INFO(\"cmdsz: %d\\n\", obj->cmdsz);\n\t\t\tRTW_INFO(\"rsp: %p\\n\", obj->rsp);\n\t\t\tRTW_INFO(\"rspsz: %d\\n\", obj->rspsz);\n\t\t\tRTW_INFO(\"sctx: %p\\n\", obj->sctx);\n\t\t\tRTW_INFO(\"list->next: %p\\n\", obj->list.next);\n\t\t\tRTW_INFO(\"list->prev: %p\\n\", obj->list.prev);\n\t\t}\n\n\t\tif (dump_cmd_id) {\n\t\t\tRTW_INFO(\"%s===> cmdcode:0x%02x\\n\", __FUNCTION__, obj->cmdcode);\n\t\t\tif (obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) {\n\t\t\t\tif (obj->parmbuf) {\n\t\t\t\t\tstruct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)(obj->parmbuf);\n\t\t\t\t\tprintk(\"pdrvextra_cmd_parm->ec_id:0x%02x\\n\", pdrvextra_cmd_parm->ec_id);\n\t\t\t\t}\n\t\t\t}\n\n\t\t}\n#endif /* DBG_CMD_QUEUE */\n\n\t\trtw_list_delete(&obj->list);\n\t}\n\n\t/* _exit_critical_bh(&(queue->lock), &irqL); */\n\t_exit_critical(&queue->lock, &irqL);\n\n\n\treturn obj;\n}\n\nu32\trtw_init_cmd_priv(struct cmd_priv *pcmdpriv)\n{\n\tu32\tres;\n\tres = _rtw_init_cmd_priv(pcmdpriv);\n\treturn res;\n}\n\nu32\trtw_init_evt_priv(struct\tevt_priv *pevtpriv)\n{\n\tint\tres;\n\tres = _rtw_init_evt_priv(pevtpriv);\n\treturn res;\n}\n\nvoid rtw_free_evt_priv(struct\tevt_priv *pevtpriv)\n{\n\t_rtw_free_evt_priv(pevtpriv);\n}\n\nvoid rtw_free_cmd_priv(struct\tcmd_priv *pcmdpriv)\n{\n\t_rtw_free_cmd_priv(pcmdpriv);\n}\n\nint rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj);\nint rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj)\n{\n\tu8 bAllow = _FALSE; /* set to _TRUE to allow enqueuing cmd when hw_init_completed is _FALSE */\n\n#ifdef SUPPORT_HW_RFOFF_DETECTED\n\t/* To decide allow or not */\n\tif ((adapter_to_pwrctl(pcmdpriv->padapter)->bHWPwrPindetect)\n\t    && (!pcmdpriv->padapter->registrypriv.usbss_enable)\n\t   ) {\n\t\tif (cmd_obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) {\n\t\t\tstruct drvextra_cmd_parm\t*pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf;\n\t\t\tif (pdrvextra_cmd_parm->ec_id == POWER_SAVING_CTRL_WK_CID) {\n\t\t\t\t/* RTW_INFO(\"==>enqueue POWER_SAVING_CTRL_WK_CID\\n\"); */\n\t\t\t\tbAllow = _TRUE;\n\t\t\t}\n\t\t}\n\t}\n#endif\n\n\tif (cmd_obj->cmdcode == GEN_CMD_CODE(_SetChannelPlan))\n\t\tbAllow = _TRUE;\n\n\tif (cmd_obj->no_io)\n\t\tbAllow = _TRUE;\n\n\tif ((!rtw_is_hw_init_completed(pcmdpriv->padapter) && (bAllow == _FALSE))\n\t    || ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _FALSE\t/* com_thread not running */\n\t   ) {\n\t\tif (DBG_CMD_EXECUTE)\n\t\t\tRTW_INFO(ADPT_FMT\" drop \"CMD_FMT\" hw_init_completed:%u, cmdthd_running:%u\\n\", ADPT_ARG(cmd_obj->padapter)\n\t\t\t\t, CMD_ARG(cmd_obj), rtw_get_hw_init_completed(cmd_obj->padapter), ATOMIC_READ(&pcmdpriv->cmdthd_running));\n\t\tif (0)\n\t\t\trtw_warn_on(1);\n\n\t\treturn _FAIL;\n\t}\n\treturn _SUCCESS;\n}\n\n\n\nu32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj)\n{\n\tint res = _FAIL;\n\tPADAPTER padapter = pcmdpriv->padapter;\n\n\n\tif (cmd_obj == NULL)\n\t\tgoto exit;\n\n\tcmd_obj->padapter = padapter;\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t/* change pcmdpriv to primary's pcmdpriv */\n\tif (!is_primary_adapter(padapter))\n\t\tpcmdpriv = &(GET_PRIMARY_ADAPTER(padapter)->cmdpriv);\n#endif\n\n\tres = rtw_cmd_filter(pcmdpriv, cmd_obj);\n\tif ((_FAIL == res) || (cmd_obj->cmdsz > MAX_CMDSZ)) {\n\t\tif (cmd_obj->cmdsz > MAX_CMDSZ) {\n\t\t\tRTW_INFO(\"%s failed due to obj->cmdsz(%d) > MAX_CMDSZ(%d)\\n\", __func__, cmd_obj->cmdsz, MAX_CMDSZ);\n\t\t\trtw_warn_on(1);\n\t\t}\n\n\t\tif (cmd_obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) {\n\t\t\tstruct drvextra_cmd_parm *extra_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf;\n\n\t\t\tif (extra_parm->pbuf && extra_parm->size > 0)\n\t\t\t\trtw_mfree(extra_parm->pbuf, extra_parm->size);\n\t\t}\n\t\trtw_free_cmd_obj(cmd_obj);\n\t\tgoto exit;\n\t}\n\n\tres = _rtw_enqueue_cmd(&pcmdpriv->cmd_queue, cmd_obj, 0);\n\n\tif (res == _SUCCESS)\n\t\t_rtw_up_sema(&pcmdpriv->cmd_queue_sema);\n\nexit:\n\n\n\treturn res;\n}\n\nstruct\tcmd_obj\t*rtw_dequeue_cmd(struct cmd_priv *pcmdpriv)\n{\n\tstruct cmd_obj *cmd_obj;\n\n\n\tcmd_obj = _rtw_dequeue_cmd(&pcmdpriv->cmd_queue);\n\n\treturn cmd_obj;\n}\n\nvoid rtw_cmd_clr_isr(struct\tcmd_priv *pcmdpriv)\n{\n\tpcmdpriv->cmd_done_cnt++;\n\t/* _rtw_up_sema(&(pcmdpriv->cmd_done_sema)); */\n}\n\nvoid rtw_free_cmd_obj(struct cmd_obj *pcmd)\n{\n\tif (pcmd->parmbuf != NULL) {\n\t\t/* free parmbuf in cmd_obj */\n\t\trtw_mfree((unsigned char *)pcmd->parmbuf, pcmd->cmdsz);\n\t}\n\tif (pcmd->rsp != NULL) {\n\t\tif (pcmd->rspsz != 0) {\n\t\t\t/* free rsp in cmd_obj */\n\t\t\trtw_mfree((unsigned char *)pcmd->rsp, pcmd->rspsz);\n\t\t}\n\t}\n\n\t/* free cmd_obj */\n\trtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj));\n}\n\n\nvoid rtw_stop_cmd_thread(_adapter *adapter)\n{\n\tif (adapter->cmdThread) {\n\t\t_rtw_up_sema(&adapter->cmdpriv.cmd_queue_sema);\n\t\trtw_thread_stop(adapter->cmdThread);\n\t\tadapter->cmdThread = NULL;\n\t}\n}\n\nthread_return rtw_cmd_thread(thread_context context)\n{\n\tu8 ret;\n\tstruct cmd_obj *pcmd;\n\tu8 *pcmdbuf, *prspbuf;\n\tsystime cmd_start_time;\n\tu32 cmd_process_time;\n\tu8(*cmd_hdl)(_adapter *padapter, u8 *pbuf);\n\tvoid (*pcmd_callback)(_adapter *dev, struct cmd_obj *pcmd);\n\tPADAPTER padapter = (PADAPTER)context;\n\tstruct cmd_priv *pcmdpriv = &(padapter->cmdpriv);\n\tstruct drvextra_cmd_parm *extra_parm = NULL;\n\t_irqL irqL;\n\n\tthread_enter(\"RTW_CMD_THREAD\");\n\n\tpcmdbuf = pcmdpriv->cmd_buf;\n\tprspbuf = pcmdpriv->rsp_buf;\n\tATOMIC_SET(&(pcmdpriv->cmdthd_running), _TRUE);\n\t_rtw_up_sema(&pcmdpriv->start_cmdthread_sema);\n\n\n\twhile (1) {\n\t\tif (_rtw_down_sema(&pcmdpriv->cmd_queue_sema) == _FAIL) {\n\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" _rtw_down_sema(&pcmdpriv->cmd_queue_sema) return _FAIL, break\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\tbreak;\n\t\t}\n\n\t\tif (RTW_CANNOT_RUN(padapter)) {\n\t\t\tRTW_DBG(FUNC_ADPT_FMT \"- bDriverStopped(%s) bSurpriseRemoved(%s)\\n\",\n\t\t\t\tFUNC_ADPT_ARG(padapter),\n\t\t\t\trtw_is_drv_stopped(padapter) ? \"True\" : \"False\",\n\t\t\t\trtw_is_surprise_removed(padapter) ? \"True\" : \"False\");\n\t\t\tbreak;\n\t\t}\n\n\t\t_enter_critical(&pcmdpriv->cmd_queue.lock, &irqL);\n\t\tif (rtw_is_list_empty(&(pcmdpriv->cmd_queue.queue))) {\n\t\t\t/* RTW_INFO(\"%s: cmd queue is empty!\\n\", __func__); */\n\t\t\t_exit_critical(&pcmdpriv->cmd_queue.lock, &irqL);\n\t\t\tcontinue;\n\t\t}\n\t\t_exit_critical(&pcmdpriv->cmd_queue.lock, &irqL);\n\n_next:\n\t\tif (RTW_CANNOT_RUN(padapter)) {\n\t\t\tRTW_PRINT(\"%s: DriverStopped(%s) SurpriseRemoved(%s) break at line %d\\n\",\n\t\t\t\t  __func__\n\t\t\t\t, rtw_is_drv_stopped(padapter) ? \"True\" : \"False\"\n\t\t\t\t, rtw_is_surprise_removed(padapter) ? \"True\" : \"False\"\n\t\t\t\t  , __LINE__);\n\t\t\tbreak;\n\t\t}\n\n\t\tpcmd = rtw_dequeue_cmd(pcmdpriv);\n\t\tif (!pcmd) {\n#ifdef CONFIG_LPS_LCLK\n\t\t\trtw_unregister_cmd_alive(padapter);\n#endif\n\t\t\tcontinue;\n\t\t}\n\n\t\tcmd_start_time = rtw_get_current_time();\n\t\tpcmdpriv->cmd_issued_cnt++;\n\n\t\tif (pcmd->cmdsz > MAX_CMDSZ) {\n\t\t\tRTW_ERR(\"%s cmdsz:%d > MAX_CMDSZ:%d\\n\", __func__, pcmd->cmdsz, MAX_CMDSZ);\n\t\t\tpcmd->res = H2C_PARAMETERS_ERROR;\n\t\t\tgoto post_process;\n\t\t}\n\n\t\tif (pcmd->cmdcode >= (sizeof(wlancmds) / sizeof(struct cmd_hdl))) {\n\t\t\tRTW_ERR(\"%s undefined cmdcode:%d\\n\", __func__, pcmd->cmdcode);\n\t\t\tpcmd->res = H2C_PARAMETERS_ERROR;\n\t\t\tgoto post_process;\n\t\t}\n\n\t\tcmd_hdl = wlancmds[pcmd->cmdcode].h2cfuns;\n\t\tif (!cmd_hdl) {\n\t\t\tRTW_ERR(\"%s no cmd_hdl for cmdcode:%d\\n\", __func__, pcmd->cmdcode);\n\t\t\tpcmd->res = H2C_PARAMETERS_ERROR;\n\t\t\tgoto post_process;\n\t\t}\n\n\t\tif (_FAIL == rtw_cmd_filter(pcmdpriv, pcmd)) {\n\t\t\tpcmd->res = H2C_DROPPED;\n\t\t\tif (pcmd->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) {\n\t\t\t\textra_parm = (struct drvextra_cmd_parm *)pcmd->parmbuf;\n\t\t\t\tif (extra_parm && extra_parm->pbuf && extra_parm->size > 0)\n\t\t\t\t\trtw_mfree(extra_parm->pbuf, extra_parm->size);\n\t\t\t}\n\t\t\t#ifdef CONFIG_DFS\n\t\t\telse if (pcmd->cmdcode == GEN_CMD_CODE(_SetChannelSwitch))\n\t\t\t\tadapter_to_rfctl(padapter)->csa_ch = 0;\n\t\t\t#endif\n\t\t\tgoto post_process;\n\t\t}\n\n#ifdef CONFIG_LPS_LCLK\n\t\tif (pcmd->no_io)\n\t\t\trtw_unregister_cmd_alive(padapter);\n\t\telse {\n\t\t\tif (rtw_register_cmd_alive(padapter) != _SUCCESS) {\n\t\t\t\tif (DBG_CMD_EXECUTE)\n\t\t\t\t\tRTW_PRINT(\"%s: wait to leave LPS_LCLK\\n\", __func__);\n\n\t\t\t\tpcmd->res = H2C_ENQ_HEAD;\n\t\t\t\tret = _rtw_enqueue_cmd(&pcmdpriv->cmd_queue, pcmd, 1);\n\t\t\t\tif (ret == _SUCCESS) {\n\t\t\t\t\tif (DBG_CMD_EXECUTE)\n\t\t\t\t\t\tRTW_INFO(ADPT_FMT\" \"CMD_FMT\" ENQ_HEAD\\n\", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd));\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\tRTW_INFO(ADPT_FMT\" \"CMD_FMT\" ENQ_HEAD_FAIL\\n\", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd));\n\t\t\t\tpcmd->res = H2C_ENQ_HEAD_FAIL;\n\t\t\t\trtw_warn_on(1);\n\t\t\t}\n\t\t}\n#endif /* CONFIG_LPS_LCLK */\n\n\t\tif (DBG_CMD_EXECUTE)\n\t\t\tRTW_INFO(ADPT_FMT\" \"CMD_FMT\" %sexecute\\n\", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd)\n\t\t\t\t, pcmd->res == H2C_ENQ_HEAD ? \"ENQ_HEAD \" : (pcmd->res == H2C_ENQ_HEAD_FAIL ? \"ENQ_HEAD_FAIL \" : \"\"));\n\n\t\t_rtw_memcpy(pcmdbuf, pcmd->parmbuf, pcmd->cmdsz);\n\t\tret = cmd_hdl(pcmd->padapter, pcmdbuf);\n\t\tpcmd->res = ret;\n\n\t\tpcmdpriv->cmd_seq++;\n\npost_process:\n\n\t\t_enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);\n\t\tif (pcmd->sctx) {\n\t\t\tif (0)\n\t\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" pcmd->sctx\\n\", FUNC_ADPT_ARG(pcmd->padapter));\n\t\t\tif (pcmd->res == H2C_SUCCESS)\n\t\t\t\trtw_sctx_done(&pcmd->sctx);\n\t\t\telse\n\t\t\t\trtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_ERROR);\n\t\t}\n\t\t_exit_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);\n\n\t\tcmd_process_time = rtw_get_passing_time_ms(cmd_start_time);\n\t\tif (cmd_process_time > 1000) {\n\t\t\tRTW_INFO(ADPT_FMT\" \"CMD_FMT\" process_time=%d\\n\", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd), cmd_process_time);\n\t\t\tif (0)\n\t\t\t\trtw_warn_on(1);\n\t\t}\n\n\t\t/* call callback function for post-processed */\n\t\tif (pcmd->cmdcode < (sizeof(rtw_cmd_callback) / sizeof(struct _cmd_callback))) {\n\t\t\tpcmd_callback = rtw_cmd_callback[pcmd->cmdcode].callback;\n\t\t\tif (pcmd_callback == NULL) {\n\t\t\t\trtw_free_cmd_obj(pcmd);\n\t\t\t} else {\n\t\t\t\t/* todo: !!! fill rsp_buf to pcmd->rsp if (pcmd->rsp!=NULL) */\n\t\t\t\tpcmd_callback(pcmd->padapter, pcmd);/* need conider that free cmd_obj in rtw_cmd_callback */\n\t\t\t}\n\t\t} else {\n\t\t\trtw_free_cmd_obj(pcmd);\n\t\t}\n\n\t\tflush_signals_thread();\n\n\t\tgoto _next;\n\n\t}\n\n#ifdef CONFIG_LPS_LCLK\n\trtw_unregister_cmd_alive(padapter);\n#endif\n\n\t/* to avoid enqueue cmd after free all cmd_obj */\n\tATOMIC_SET(&(pcmdpriv->cmdthd_running), _FALSE);\n\n\t/* free all cmd_obj resources */\n\tdo {\n\t\tpcmd = rtw_dequeue_cmd(pcmdpriv);\n\t\tif (pcmd == NULL)\n\t\t\tbreak;\n\n\t\tif (0)\n\t\t\tRTW_INFO(\"%s: leaving... drop \"CMD_FMT\"\\n\", __func__, CMD_ARG(pcmd));\n\n\t\tif (pcmd->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) {\n\t\t\textra_parm = (struct drvextra_cmd_parm *)pcmd->parmbuf;\n\t\t\tif (extra_parm->pbuf && extra_parm->size > 0)\n\t\t\t\trtw_mfree(extra_parm->pbuf, extra_parm->size);\n\t\t}\n\t\t#ifdef CONFIG_DFS\n\t\telse if (pcmd->cmdcode == GEN_CMD_CODE(_SetChannelSwitch))\n\t\t\tadapter_to_rfctl(padapter)->csa_ch = 0;\n\t\t#endif\n\n\t\t_enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);\n\t\tif (pcmd->sctx) {\n\t\t\tif (0)\n\t\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" pcmd->sctx\\n\", FUNC_ADPT_ARG(pcmd->padapter));\n\t\t\trtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_DROP);\n\t\t}\n\t\t_exit_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);\n\n\t\trtw_free_cmd_obj(pcmd);\n\t} while (1);\n\n\tRTW_INFO(FUNC_ADPT_FMT \" Exit\\n\", FUNC_ADPT_ARG(padapter));\n\n\trtw_thread_wait_stop();\n\n\treturn 0;\n}\n\n\n#ifdef CONFIG_EVENT_THREAD_MODE\nu32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj)\n{\n\t_irqL irqL;\n\tint\tres;\n\t_queue *queue = &pevtpriv->evt_queue;\n\n\n\tres = _SUCCESS;\n\n\tif (obj == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t_enter_critical_bh(&queue->lock, &irqL);\n\n\trtw_list_insert_tail(&obj->list, &queue->queue);\n\n\t_exit_critical_bh(&queue->lock, &irqL);\n\n\t/* rtw_evt_notify_isr(pevtpriv); */\n\nexit:\n\n\n\treturn res;\n}\n\nstruct evt_obj *rtw_dequeue_evt(_queue *queue)\n{\n\t_irqL irqL;\n\tstruct\tevt_obj\t*pevtobj;\n\n\n\t_enter_critical_bh(&queue->lock, &irqL);\n\n\tif (rtw_is_list_empty(&(queue->queue)))\n\t\tpevtobj = NULL;\n\telse {\n\t\tpevtobj = LIST_CONTAINOR(get_next(&(queue->queue)), struct evt_obj, list);\n\t\trtw_list_delete(&pevtobj->list);\n\t}\n\n\t_exit_critical_bh(&queue->lock, &irqL);\n\n\n\treturn pevtobj;\n}\n\nvoid rtw_free_evt_obj(struct evt_obj *pevtobj)\n{\n\n\tif (pevtobj->parmbuf)\n\t\trtw_mfree((unsigned char *)pevtobj->parmbuf, pevtobj->evtsz);\n\n\trtw_mfree((unsigned char *)pevtobj, sizeof(struct evt_obj));\n\n}\n\nvoid rtw_evt_notify_isr(struct evt_priv *pevtpriv)\n{\n\tpevtpriv->evt_done_cnt++;\n\t_rtw_up_sema(&(pevtpriv->evt_notify));\n}\n#endif\n\n\n/*\nu8 rtw_setstandby_cmd(unsigned char  *adapter)\n*/\nu8 rtw_setstandby_cmd(_adapter *padapter, uint action)\n{\n\tstruct cmd_obj\t\t\t*ph2c;\n\tstruct usb_suspend_parm\t*psetusbsuspend;\n\tstruct cmd_priv\t\t\t*pcmdpriv = &padapter->cmdpriv;\n\n\tu8 ret = _SUCCESS;\n\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpsetusbsuspend = (struct usb_suspend_parm *)rtw_zmalloc(sizeof(struct usb_suspend_parm));\n\tif (psetusbsuspend == NULL) {\n\t\trtw_mfree((u8 *) ph2c, sizeof(struct\tcmd_obj));\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpsetusbsuspend->action = action;\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, psetusbsuspend, GEN_CMD_CODE(_SetUsbSuspend));\n\n\tret = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\n\n\treturn ret;\n}\n\nvoid rtw_init_sitesurvey_parm(_adapter *padapter, struct sitesurvey_parm *pparm)\n{\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n\n\t_rtw_memset(pparm, 0, sizeof(struct sitesurvey_parm));\n\tpparm->scan_mode = pmlmepriv->scan_mode;\n}\n\n/*\nrtw_sitesurvey_cmd(~)\n\t### NOTE:#### (!!!!)\n\tMUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock\n*/\nu8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm)\n{\n\tu8 res = _FAIL;\n\tstruct cmd_obj\t\t*ph2c;\n\tstruct sitesurvey_parm\t*psurveyPara;\n\tstruct cmd_priv\t*pcmdpriv = &padapter->cmdpriv;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\n#ifdef CONFIG_LPS\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\trtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SCAN, 0);\n#endif\n\n#ifdef CONFIG_P2P_PS\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\tp2p_ps_wk_cmd(padapter, P2P_PS_SCAN, 1);\n#endif /* CONFIG_P2P_PS */\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL)\n\t\treturn _FAIL;\n\n\tpsurveyPara = (struct sitesurvey_parm *)rtw_zmalloc(sizeof(struct sitesurvey_parm));\n\tif (psurveyPara == NULL) {\n\t\trtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj));\n\t\treturn _FAIL;\n\t}\n\n\tif (pparm)\n\t\t_rtw_memcpy(psurveyPara, pparm, sizeof(struct sitesurvey_parm));\n\telse\n\t\tpsurveyPara->scan_mode = pmlmepriv->scan_mode;\n\n\trtw_free_network_queue(padapter, _FALSE);\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, psurveyPara, GEN_CMD_CODE(_SiteSurvey));\n\n\tset_fwstate(pmlmepriv, _FW_UNDER_SURVEY);\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\n\tif (res == _SUCCESS) {\n\t\tu32 scan_timeout_ms;\n\n\t\tpmlmepriv->scan_start_time = rtw_get_current_time();\n\t\tscan_timeout_ms = rtw_scan_timeout_decision(padapter);\n\t\tmlme_set_scan_to_timer(pmlmepriv,scan_timeout_ms);\n\n\t\trtw_led_control(padapter, LED_CTL_SITE_SURVEY);\n\t} else\n\t\t_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);\n\n\n\treturn res;\n}\n\nu8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset)\n{\n\tstruct cmd_obj\t\t\t*ph2c;\n\tstruct setdatarate_parm\t*pbsetdataratepara;\n\tstruct cmd_priv\t\t*pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpbsetdataratepara = (struct setdatarate_parm *)rtw_zmalloc(sizeof(struct setdatarate_parm));\n\tif (pbsetdataratepara == NULL) {\n\t\trtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pbsetdataratepara, GEN_CMD_CODE(_SetDataRate));\n#ifdef MP_FIRMWARE_OFFLOAD\n\tpbsetdataratepara->curr_rateidx = *(u32 *)rateset;\n\t/*\t_rtw_memcpy(pbsetdataratepara, rateset, sizeof(u32)); */\n#else\n\tpbsetdataratepara->mac_id = 5;\n\t_rtw_memcpy(pbsetdataratepara->datarates, rateset, NumRates);\n#endif\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\nexit:\n\n\n\treturn res;\n}\n\nu8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset)\n{\n\tstruct cmd_obj\t\t\t*ph2c;\n\tstruct setbasicrate_parm\t*pssetbasicratepara;\n\tstruct cmd_priv\t\t*pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tpssetbasicratepara = (struct setbasicrate_parm *)rtw_zmalloc(sizeof(struct setbasicrate_parm));\n\n\tif (pssetbasicratepara == NULL) {\n\t\trtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pssetbasicratepara, _SetBasicRate_CMD_);\n\n\t_rtw_memcpy(pssetbasicratepara->basicrates, rateset, NumRates);\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\nexit:\n\n\n\treturn res;\n}\n\n\n/*\nunsigned char rtw_setphy_cmd(unsigned char  *adapter)\n\n1.  be called only after rtw_update_registrypriv_dev_network( ~) or mp testing program\n2.  for AdHoc/Ap mode or mp mode?\n\n*/\nu8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch)\n{\n\tstruct cmd_obj\t\t\t*ph2c;\n\tstruct setphy_parm\t\t*psetphypara;\n\tstruct cmd_priv\t\t\t*pcmdpriv = &padapter->cmdpriv;\n\t/*\tstruct mlme_priv\t\t\t*pmlmepriv = &padapter->mlmepriv;\n\t *\tstruct registry_priv*\t\tpregistry_priv = &padapter->registrypriv; */\n\tu8\tres = _SUCCESS;\n\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tpsetphypara = (struct setphy_parm *)rtw_zmalloc(sizeof(struct setphy_parm));\n\n\tif (psetphypara == NULL) {\n\t\trtw_mfree((u8 *) ph2c, sizeof(struct\tcmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, psetphypara, _SetPhy_CMD_);\n\n\n\tpsetphypara->modem = modem;\n\tpsetphypara->rfchannel = ch;\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\nexit:\n\treturn res;\n}\n\nu8 rtw_getmacreg_cmd(_adapter *padapter, u8 len, u32 addr)\n{\n\tstruct cmd_obj *ph2c;\n\tstruct readMAC_parm *preadmacparm;\n\tstruct cmd_priv *pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tpreadmacparm = (struct readMAC_parm *)rtw_zmalloc(sizeof(struct readMAC_parm));\n\n\tif (preadmacparm == NULL) {\n\t\trtw_mfree((u8 *) ph2c, sizeof(struct\tcmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, preadmacparm, GEN_CMD_CODE(_GetMACReg));\n\n\tpreadmacparm->len = len;\n\tpreadmacparm->addr = addr;\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\treturn res;\n}\n\nvoid rtw_usb_catc_trigger_cmd(_adapter *padapter, const char *caller)\n{\n\tRTW_INFO(\"%s caller:%s\\n\", __func__, caller);\n\trtw_getmacreg_cmd(padapter, 1, 0x1c4);\n}\n\nu8 rtw_setbbreg_cmd(_adapter *padapter, u8 offset, u8 val)\n{\n\tstruct cmd_obj\t\t\t*ph2c;\n\tstruct writeBB_parm\t\t*pwritebbparm;\n\tstruct cmd_priv\t\t\t*pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tpwritebbparm = (struct writeBB_parm *)rtw_zmalloc(sizeof(struct writeBB_parm));\n\n\tif (pwritebbparm == NULL) {\n\t\trtw_mfree((u8 *) ph2c, sizeof(struct\tcmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pwritebbparm, GEN_CMD_CODE(_SetBBReg));\n\n\tpwritebbparm->offset = offset;\n\tpwritebbparm->value = val;\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\nexit:\n\treturn res;\n}\n\nu8 rtw_getbbreg_cmd(_adapter  *padapter, u8 offset, u8 *pval)\n{\n\tstruct cmd_obj\t\t\t*ph2c;\n\tstruct readBB_parm\t\t*prdbbparm;\n\tstruct cmd_priv\t\t\t*pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tprdbbparm = (struct readBB_parm *)rtw_zmalloc(sizeof(struct readBB_parm));\n\n\tif (prdbbparm == NULL) {\n\t\trtw_mfree((unsigned char *) ph2c, sizeof(struct\tcmd_obj));\n\t\treturn _FAIL;\n\t}\n\n\t_rtw_init_listhead(&ph2c->list);\n\tph2c->cmdcode = GEN_CMD_CODE(_GetBBReg);\n\tph2c->parmbuf = (unsigned char *)prdbbparm;\n\tph2c->cmdsz =  sizeof(struct readBB_parm);\n\tph2c->rsp = pval;\n\tph2c->rspsz = sizeof(struct readBB_rsp);\n\n\tprdbbparm->offset = offset;\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\nexit:\n\treturn res;\n}\n\nu8 rtw_setrfreg_cmd(_adapter  *padapter, u8 offset, u32 val)\n{\n\tstruct cmd_obj\t\t\t*ph2c;\n\tstruct writeRF_parm\t\t*pwriterfparm;\n\tstruct cmd_priv\t\t\t*pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tpwriterfparm = (struct writeRF_parm *)rtw_zmalloc(sizeof(struct writeRF_parm));\n\n\tif (pwriterfparm == NULL) {\n\t\trtw_mfree((u8 *) ph2c, sizeof(struct\tcmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pwriterfparm, GEN_CMD_CODE(_SetRFReg));\n\n\tpwriterfparm->offset = offset;\n\tpwriterfparm->value = val;\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\nexit:\n\treturn res;\n}\n\nu8 rtw_getrfreg_cmd(_adapter  *padapter, u8 offset, u8 *pval)\n{\n\tstruct cmd_obj\t\t\t*ph2c;\n\tstruct readRF_parm\t\t*prdrfparm;\n\tstruct cmd_priv\t\t\t*pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tprdrfparm = (struct readRF_parm *)rtw_zmalloc(sizeof(struct readRF_parm));\n\tif (prdrfparm == NULL) {\n\t\trtw_mfree((u8 *) ph2c, sizeof(struct\tcmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t_rtw_init_listhead(&ph2c->list);\n\tph2c->cmdcode = GEN_CMD_CODE(_GetRFReg);\n\tph2c->parmbuf = (unsigned char *)prdrfparm;\n\tph2c->cmdsz =  sizeof(struct readRF_parm);\n\tph2c->rsp = pval;\n\tph2c->rspsz = sizeof(struct readRF_rsp);\n\n\tprdrfparm->offset = offset;\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\n\n\treturn res;\n}\n\nvoid rtw_getbbrfreg_cmdrsp_callback(_adapter\t*padapter,  struct cmd_obj *pcmd)\n{\n\n\t/* rtw_free_cmd_obj(pcmd); */\n\trtw_mfree((unsigned char *) pcmd->parmbuf, pcmd->cmdsz);\n\trtw_mfree((unsigned char *) pcmd, sizeof(struct cmd_obj));\n\n#ifdef CONFIG_MP_INCLUDED\n\tif (padapter->registrypriv.mp_mode == 1)\n\t\tpadapter->mppriv.workparam.bcompleted = _TRUE;\n#endif\n}\n\nvoid rtw_readtssi_cmdrsp_callback(_adapter\t*padapter,  struct cmd_obj *pcmd)\n{\n\n\trtw_mfree((unsigned char *) pcmd->parmbuf, pcmd->cmdsz);\n\trtw_mfree((unsigned char *) pcmd, sizeof(struct cmd_obj));\n\n#ifdef CONFIG_MP_INCLUDED\n\tif (padapter->registrypriv.mp_mode == 1)\n\t\tpadapter->mppriv.workparam.bcompleted = _TRUE;\n#endif\n\n}\n\nstatic u8 rtw_createbss_cmd(_adapter  *adapter, int flags, bool adhoc\n\t, u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset)\n{\n\tstruct cmd_obj *cmdobj;\n\tstruct createbss_parm *parm;\n\tstruct cmd_priv *pcmdpriv = &adapter->cmdpriv;\n\tstruct submit_ctx sctx;\n\tu8 res = _SUCCESS;\n\n\tif (req_ch > 0 && req_bw >= 0 && req_offset >= 0) {\n\t\tif (!rtw_chset_is_chbw_valid(adapter_to_chset(adapter), req_ch, req_bw, req_offset)) {\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\t/* prepare cmd parameter */\n\tparm = (struct createbss_parm *)rtw_zmalloc(sizeof(*parm));\n\tif (parm == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tif (adhoc) {\n\t\t/* for now, adhoc doesn't support ch,bw,offset request */\n\t\tparm->adhoc = 1;\n\t} else {\n\t\tparm->adhoc = 0;\n\t\tparm->ifbmp = ifbmp;\n\t\tparm->excl_ifbmp = excl_ifbmp;\n\t\tparm->req_ch = req_ch;\n\t\tparm->req_bw = req_bw;\n\t\tparm->req_offset = req_offset;\n\t}\n\n\tif (flags & RTW_CMDF_DIRECTLY) {\n\t\t/* no need to enqueue, do the cmd hdl directly and free cmd parameter */\n\t\tif (H2C_SUCCESS != createbss_hdl(adapter, (u8 *)parm))\n\t\t\tres = _FAIL;\n\t\trtw_mfree((u8 *)parm, sizeof(*parm));\n\t} else {\n\t\t/* need enqueue, prepare cmd_obj and enqueue */\n\t\tcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));\n\t\tif (cmdobj == NULL) {\n\t\t\tres = _FAIL;\n\t\t\trtw_mfree((u8 *)parm, sizeof(*parm));\n\t\t\tgoto exit;\n\t\t}\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_CreateBss));\n\n\t\tif (flags & RTW_CMDF_WAIT_ACK) {\n\t\t\tcmdobj->sctx = &sctx;\n\t\t\trtw_sctx_init(&sctx, 2000);\n\t\t}\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, cmdobj);\n\n\t\tif (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {\n\t\t\trtw_sctx_wait(&sctx, __func__);\n\t\t\t_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t\tif (sctx.status == RTW_SCTX_SUBMITTED)\n\t\t\t\tcmdobj->sctx = NULL;\n\t\t\t_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t}\n\t}\n\nexit:\n\treturn res;\n}\n\ninline u8 rtw_create_ibss_cmd(_adapter *adapter, int flags)\n{\n\treturn rtw_createbss_cmd(adapter, flags\n\t\t, 1\n\t\t, 0, 0\n\t\t, 0, REQ_BW_NONE, REQ_OFFSET_NONE /* for now, adhoc doesn't support ch,bw,offset request */\n\t);\n}\n\ninline u8 rtw_startbss_cmd(_adapter *adapter, int flags)\n{\n\treturn rtw_createbss_cmd(adapter, flags\n\t\t, 0\n\t\t, BIT(adapter->iface_id), 0\n\t\t, 0, REQ_BW_NONE, REQ_OFFSET_NONE /* excute entire AP setup cmd */\n\t);\n}\n\ninline u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags\n\t, u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset)\n{\n\treturn rtw_createbss_cmd(adapter, flags\n\t\t, 0\n\t\t, ifbmp, excl_ifbmp\n\t\t, req_ch, req_bw, req_offset\n\t);\n}\n\n#ifdef CONFIG_RTW_80211R\nstatic void rtw_ft_validate_akm_type(_adapter  *padapter,\n\tstruct wlan_network *pnetwork)\n{\n\tstruct security_priv *psecuritypriv = &(padapter->securitypriv);\n\tstruct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);\n\tu32 tmp_len;\n\tu8 *ptmp;\n\n\t/*IEEE802.11-2012 Std. Table 8-101-AKM suite selectors*/\n\tif (rtw_ft_valid_akm(padapter, psecuritypriv->rsn_akm_suite_type)) {\n\t\tptmp = rtw_get_ie(&pnetwork->network.IEs[12], \n\t\t\t\t_MDIE_, &tmp_len, (pnetwork->network.IELength-12));\n\t\tif (ptmp) {\n\t\t\tpft_roam->mdid = *(u16 *)(ptmp+2);\n\t\t\tpft_roam->ft_cap = *(ptmp+4);\n\n\t\t\tRTW_INFO(\"FT: target \" MAC_FMT \" mdid=(0x%2x), capacity=(0x%2x)\\n\", \n\t\t\t\tMAC_ARG(pnetwork->network.MacAddress), pft_roam->mdid, pft_roam->ft_cap);\n\t\t\trtw_ft_set_flags(padapter, RTW_FT_PEER_EN);\n\n\t\t\tif (rtw_ft_otd_roam_en(padapter))\n\t\t\t\trtw_ft_set_flags(padapter, RTW_FT_PEER_OTD_EN);\n\t\t} else {\n\t\t\t/* Don't use FT roaming if target AP cannot support FT */\n\t\t\trtw_ft_clr_flags(padapter, (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN));\n\t\t\trtw_ft_reset_status(padapter);\n\t\t}\n\t} else {\n\t\t/* It could be a non-FT connection */\n\t\trtw_ft_clr_flags(padapter, (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN));\n\t\trtw_ft_reset_status(padapter);\n\t}\t\n}\n#endif\n\nu8 rtw_joinbss_cmd(_adapter  *padapter, struct wlan_network *pnetwork)\n{\n\tu8\t*auth, res = _SUCCESS;\n\tuint\tt_len = 0;\n\tWLAN_BSSID_EX\t\t*psecnetwork;\n\tstruct cmd_obj\t\t*pcmd;\n\tstruct cmd_priv\t\t*pcmdpriv = &padapter->cmdpriv;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct qos_priv\t\t*pqospriv = &pmlmepriv->qospriv;\n\tstruct security_priv\t*psecuritypriv = &padapter->securitypriv;\n\tstruct registry_priv\t*pregistrypriv = &padapter->registrypriv;\n#ifdef CONFIG_80211N_HT\n\tstruct ht_priv\t\t\t*phtpriv = &pmlmepriv->htpriv;\n#endif /* CONFIG_80211N_HT */\n#ifdef CONFIG_80211AC_VHT\n\tstruct vht_priv\t\t*pvhtpriv = &pmlmepriv->vhtpriv;\n#endif /* CONFIG_80211AC_VHT */\n\tNDIS_802_11_NETWORK_INFRASTRUCTURE ndis_network_mode = pnetwork->network.InfrastructureMode;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tu32 tmp_len;\n\tu8 *ptmp = NULL;\n\n\trtw_led_control(padapter, LED_CTL_START_TO_LINK);\n\n\tpcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (pcmd == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n#if 0\n\t/*  for IEs is pointer */\n\tt_len = sizeof(u32) + sizeof(NDIS_802_11_MAC_ADDRESS) + 2 +\n\t\tsizeof(NDIS_802_11_SSID) + sizeof(u32) +\n\t\tsizeof(NDIS_802_11_RSSI) + sizeof(NDIS_802_11_NETWORK_TYPE) +\n\t\tsizeof(NDIS_802_11_CONFIGURATION) +\n\t\tsizeof(NDIS_802_11_NETWORK_INFRASTRUCTURE) +\n\t\tsizeof(NDIS_802_11_RATES_EX) + sizeof(WLAN_PHY_INFO) + sizeof(u32) + MAX_IE_SZ;\n#endif\n\t/* for IEs is fix buf size */\n\tt_len = sizeof(WLAN_BSSID_EX);\n\n\n\t/* for hidden ap to set fw_state here */\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) != _TRUE) {\n\t\tswitch (ndis_network_mode) {\n\t\tcase Ndis802_11IBSS:\n\t\t\tset_fwstate(pmlmepriv, WIFI_ADHOC_STATE);\n\t\t\tbreak;\n\n\t\tcase Ndis802_11Infrastructure:\n\t\t\tset_fwstate(pmlmepriv, WIFI_STATION_STATE);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\trtw_warn_on(1);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tpmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->network.IEs, pnetwork->network.IELength);\n\n#ifdef CONFIG_80211AC_VHT\n\t/* save AP beamform_cap info for BCM IOT issue */\n\tif (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM)\n\t\tpvhtpriv->ap_is_mu_bfer =\n\t\t\tget_vht_mu_bfer_cap(pnetwork->network.IEs,\n\t\t\t\tpnetwork->network.IELength);\n#endif\n\t/*\n\t\tModified by Arvin 2015/05/13\n\t\tSolution for allocating a new WLAN_BSSID_EX to avoid race condition issue between disconnect and joinbss\n\t*/\n\tpsecnetwork = (WLAN_BSSID_EX *)rtw_zmalloc(sizeof(WLAN_BSSID_EX));\n\tif (psecnetwork == NULL) {\n\t\tif (pcmd != NULL)\n\t\t\trtw_mfree((unsigned char *)pcmd, sizeof(struct\tcmd_obj));\n\n\t\tres = _FAIL;\n\n\n\t\tgoto exit;\n\t}\n\n\t_rtw_memset(psecnetwork, 0, t_len);\n\n\t_rtw_memcpy(psecnetwork, &pnetwork->network, get_WLAN_BSSID_EX_sz(&pnetwork->network));\n\n\tauth = &psecuritypriv->authenticator_ie[0];\n\tpsecuritypriv->authenticator_ie[0] = (unsigned char)psecnetwork->IELength;\n\n\tif ((psecnetwork->IELength - 12) < (256 - 1))\n\t\t_rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], psecnetwork->IELength - 12);\n\telse\n\t\t_rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], (256 - 1));\n\n\tpsecnetwork->IELength = 0;\n\t/* Added by Albert 2009/02/18 */\n\t/* If the the driver wants to use the bssid to create the connection. */\n\t/* If not,  we have to copy the connecting AP's MAC address to it so that */\n\t/* the driver just has the bssid information for PMKIDList searching. */\n\n\tif (pmlmepriv->assoc_by_bssid == _FALSE)\n\t\t_rtw_memcpy(&pmlmepriv->assoc_bssid[0], &pnetwork->network.MacAddress[0], ETH_ALEN);\n\n\t/* copy fixed ie */\n\t_rtw_memcpy(psecnetwork->IEs, pnetwork->network.IEs, 12);\n\tpsecnetwork->IELength = 12;\n\n\tpsecnetwork->IELength += rtw_restruct_sec_ie(padapter, psecnetwork->IEs + psecnetwork->IELength);\n\n\n\tpqospriv->qos_option = 0;\n\n\tif (pregistrypriv->wmm_enable) {\n#ifdef CONFIG_WMMPS_STA\t\n\t\trtw_uapsd_use_default_setting(padapter);\n#endif /* CONFIG_WMMPS_STA */\t\t\n\t\ttmp_len = rtw_restruct_wmm_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength, psecnetwork->IELength);\n\n\t\tif (psecnetwork->IELength != tmp_len) {\n\t\t\tpsecnetwork->IELength = tmp_len;\n\t\t\tpqospriv->qos_option = 1; /* There is WMM IE in this corresp. beacon */\n\t\t} else {\n\t\t\tpqospriv->qos_option = 0;/* There is no WMM IE in this corresp. beacon */\n\t\t}\n\t}\n\n#ifdef CONFIG_80211N_HT\n\tphtpriv->ht_option = _FALSE;\n\tif (pregistrypriv->ht_enable && is_supported_ht(pregistrypriv->wireless_mode)) {\n\t\tptmp = rtw_get_ie(&pnetwork->network.IEs[12], _HT_CAPABILITY_IE_, &tmp_len, pnetwork->network.IELength - 12);\n\t\tif (ptmp && tmp_len > 0) {\n\t\t\t/*\tAdded by Albert 2010/06/23 */\n\t\t\t/*\tFor the WEP mode, we will use the bg mode to do the connection to avoid some IOT issue. */\n\t\t\t/*\tEspecially for Realtek 8192u SoftAP. */\n\t\t\tif ((padapter->securitypriv.dot11PrivacyAlgrthm != _WEP40_) &&\n\t\t\t    (padapter->securitypriv.dot11PrivacyAlgrthm != _WEP104_) &&\n\t\t\t    (padapter->securitypriv.dot11PrivacyAlgrthm != _TKIP_)) {\n\t\t\t\trtw_ht_use_default_setting(padapter);\n\n\t\t\t\t/* rtw_restructure_ht_ie */\n\t\t\t\trtw_restructure_ht_ie(padapter, &pnetwork->network.IEs[12], &psecnetwork->IEs[0],\n\t\t\t\t\tpnetwork->network.IELength - 12, &psecnetwork->IELength,\n\t\t\t\t\tpnetwork->network.Configuration.DSConfig);\n\t\t\t}\n\t\t}\n\t}\n\n#ifdef CONFIG_80211AC_VHT\n\tpvhtpriv->vht_option = _FALSE;\n\tif (phtpriv->ht_option\n\t\t&& REGSTY_IS_11AC_ENABLE(pregistrypriv)\n\t\t&& is_supported_vht(pregistrypriv->wireless_mode)\n\t\t&& (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))\n\t\t&& ((padapter->registrypriv.wifi_spec == 0) || (pnetwork->network.Configuration.DSConfig > 14))\n\t) {\n\t\trtw_restructure_vht_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0],\n\t\t\tpnetwork->network.IELength, &psecnetwork->IELength);\n\t}\n#endif\n#endif /* CONFIG_80211N_HT */\n\n\trtw_append_exented_cap(padapter, &psecnetwork->IEs[0], &psecnetwork->IELength);\n\n#ifdef CONFIG_RTW_80211R\n\trtw_ft_validate_akm_type(padapter, pnetwork);\n#endif\n\n#if 0\n\tpsecuritypriv->supplicant_ie[0] = (u8)psecnetwork->IELength;\n\n\tif (psecnetwork->IELength < (256 - 1))\n\t\t_rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], psecnetwork->IELength);\n\telse\n\t\t_rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], (256 - 1));\n#endif\n\n\tpcmd->cmdsz = sizeof(WLAN_BSSID_EX);\n\n\t_rtw_init_listhead(&pcmd->list);\n\tpcmd->cmdcode = _JoinBss_CMD_;/* GEN_CMD_CODE(_JoinBss) */\n\tpcmd->parmbuf = (unsigned char *)psecnetwork;\n\tpcmd->rsp = NULL;\n\tpcmd->rspsz = 0;\n\n\tres = rtw_enqueue_cmd(pcmdpriv, pcmd);\n\nexit:\n\n\n\treturn res;\n}\n\nu8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags) /* for sta_mode */\n{\n\tstruct cmd_obj *cmdobj = NULL;\n\tstruct disconnect_parm *param = NULL;\n\tstruct cmd_priv *cmdpriv = &padapter->cmdpriv;\n\tstruct cmd_priv *pcmdpriv = &padapter->cmdpriv;\n\tstruct submit_ctx sctx;\n\tu8 res = _SUCCESS;\n\n\t/* prepare cmd parameter */\n\tparam = (struct disconnect_parm *)rtw_zmalloc(sizeof(*param));\n\tif (param == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tparam->deauth_timeout_ms = deauth_timeout_ms;\n\n\tif (flags & RTW_CMDF_DIRECTLY) {\n\t\t/* no need to enqueue, do the cmd hdl directly and free cmd parameter */\n\t\tif (disconnect_hdl(padapter, (u8 *)param) != H2C_SUCCESS)\n\t\t\tres = _FAIL;\n\t\trtw_mfree((u8 *)param, sizeof(*param));\n\n\t} else {\n\t\tcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));\n\t\tif (cmdobj == NULL) {\n\t\t\tres = _FAIL;\n\t\t\trtw_mfree((u8 *)param, sizeof(*param));\n\t\t\tgoto exit;\n\t\t}\n\t\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, param, _DisConnect_CMD_);\n\t\tif (flags & RTW_CMDF_WAIT_ACK) {\n\t\t\tcmdobj->sctx = &sctx;\n\t\t\trtw_sctx_init(&sctx, 2000);\n\t\t}\n\t\tres = rtw_enqueue_cmd(cmdpriv, cmdobj);\n\t\tif (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {\n\t\t\trtw_sctx_wait(&sctx, __func__);\n\t\t\t_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t\tif (sctx.status == RTW_SCTX_SUBMITTED)\n\t\t\t\tcmdobj->sctx = NULL;\n\t\t\t_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t}\n\t}\n\nexit:\n\n\n\treturn res;\n}\n\nu8 rtw_setopmode_cmd(_adapter  *adapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags)\n{\n\tstruct cmd_obj *cmdobj;\n\tstruct setopmode_parm *parm;\n\tstruct cmd_priv *pcmdpriv = &adapter->cmdpriv;\n\tstruct submit_ctx sctx;\n\tu8 res = _SUCCESS;\n\n\t/* prepare cmd parameter */\n\tparm = (struct setopmode_parm *)rtw_zmalloc(sizeof(*parm));\n\tif (parm == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tparm->mode = (u8)networktype;\n\n\tif (flags & RTW_CMDF_DIRECTLY) {\n\t\t/* no need to enqueue, do the cmd hdl directly and free cmd parameter */\n\t\tif (H2C_SUCCESS != setopmode_hdl(adapter, (u8 *)parm))\n\t\t\tres = _FAIL;\n\t\trtw_mfree((u8 *)parm, sizeof(*parm));\n\t} else {\n\t\t/* need enqueue, prepare cmd_obj and enqueue */\n\t\tcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));\n\t\tif (cmdobj == NULL) {\n\t\t\tres = _FAIL;\n\t\t\trtw_mfree((u8 *)parm, sizeof(*parm));\n\t\t\tgoto exit;\n\t\t}\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, parm, _SetOpMode_CMD_);\n\n\t\tif (flags & RTW_CMDF_WAIT_ACK) {\n\t\t\tcmdobj->sctx = &sctx;\n\t\t\trtw_sctx_init(&sctx, 2000);\n\t\t}\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, cmdobj);\n\n\t\tif (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {\n\t\t\trtw_sctx_wait(&sctx, __func__);\n\t\t\t_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t\tif (sctx.status == RTW_SCTX_SUBMITTED)\n\t\t\t\tcmdobj->sctx = NULL;\n\t\t\t_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t}\n\t}\n\nexit:\n\treturn res;\n}\n\nu8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool enqueue)\n{\n\tstruct cmd_obj\t\t\t*ph2c;\n\tstruct set_stakey_parm\t*psetstakey_para;\n\tstruct cmd_priv\t\t\t*pcmdpriv = &padapter->cmdpriv;\n\tstruct set_stakey_rsp\t\t*psetstakey_rsp = NULL;\n\n\tstruct mlme_priv\t\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct security_priv\t\t*psecuritypriv = &padapter->securitypriv;\n\tu8\tres = _SUCCESS;\n\n\n\tpsetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm));\n\tif (psetstakey_para == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t_rtw_memcpy(psetstakey_para->addr, sta->cmn.mac_addr, ETH_ALEN);\n\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE))\n\t\tpsetstakey_para->algorithm = (unsigned char) psecuritypriv->dot11PrivacyAlgrthm;\n\telse\n\t\tGET_ENCRY_ALGO(psecuritypriv, sta, psetstakey_para->algorithm, _FALSE);\n\n\tif (key_type == GROUP_KEY) {\n\t\t_rtw_memcpy(&psetstakey_para->key, &psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, 16);\n\t\tpsetstakey_para->gk = 1;\n\t} else if (key_type == UNICAST_KEY)\n\t\t_rtw_memcpy(&psetstakey_para->key, &sta->dot118021x_UncstKey, 16);\n#ifdef CONFIG_TDLS\n\telse if (key_type == TDLS_KEY) {\n\t\t_rtw_memcpy(&psetstakey_para->key, sta->tpk.tk, 16);\n\t\tpsetstakey_para->algorithm = (u8)sta->dot118021XPrivacy;\n\t}\n#endif /* CONFIG_TDLS */\n\n\t/* jeff: set this becasue at least sw key is ready */\n\tpadapter->securitypriv.busetkipkey = _TRUE;\n\n\tif (enqueue) {\n\t\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\t\tif (ph2c == NULL) {\n\t\t\trtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpsetstakey_rsp = (struct set_stakey_rsp *)rtw_zmalloc(sizeof(struct set_stakey_rsp));\n\t\tif (psetstakey_rsp == NULL) {\n\t\t\trtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));\n\t\t\trtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_);\n\t\tph2c->rsp = (u8 *) psetstakey_rsp;\n\t\tph2c->rspsz = sizeof(struct set_stakey_rsp);\n\t\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\t} else {\n\t\tset_stakey_hdl(padapter, (u8 *)psetstakey_para);\n\t\trtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));\n\t}\nexit:\n\n\n\treturn res;\n}\n\nu8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue)\n{\n\tstruct cmd_obj\t\t\t*ph2c;\n\tstruct set_stakey_parm\t*psetstakey_para;\n\tstruct cmd_priv\t\t\t*pcmdpriv = &padapter->cmdpriv;\n\tstruct set_stakey_rsp\t\t*psetstakey_rsp = NULL;\n\ts16 cam_id = 0;\n\tu8\tres = _SUCCESS;\n\n\tif (!sta) {\n\t\tRTW_ERR(\"%s sta == NULL\\n\", __func__);\n\t\tgoto exit;\n\t}\n\n\tif (!enqueue) {\n\t\twhile ((cam_id = rtw_camid_search(padapter, sta->cmn.mac_addr, -1, -1)) >= 0) {\n\t\t\tRTW_PRINT(\"clear key for addr:\"MAC_FMT\", camid:%d\\n\", MAC_ARG(sta->cmn.mac_addr), cam_id);\n\t\t\tclear_cam_entry(padapter, cam_id);\n\t\t\trtw_camid_free(padapter, cam_id);\n\t\t}\n\t} else {\n\t\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\t\tif (ph2c == NULL) {\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpsetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm));\n\t\tif (psetstakey_para == NULL) {\n\t\t\trtw_mfree((u8 *) ph2c, sizeof(struct\tcmd_obj));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpsetstakey_rsp = (struct set_stakey_rsp *)rtw_zmalloc(sizeof(struct set_stakey_rsp));\n\t\tif (psetstakey_rsp == NULL) {\n\t\t\trtw_mfree((u8 *) ph2c, sizeof(struct\tcmd_obj));\n\t\t\trtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_);\n\t\tph2c->rsp = (u8 *) psetstakey_rsp;\n\t\tph2c->rspsz = sizeof(struct set_stakey_rsp);\n\n\t\t_rtw_memcpy(psetstakey_para->addr, sta->cmn.mac_addr, ETH_ALEN);\n\n\t\tpsetstakey_para->algorithm = _NO_PRIVACY_;\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\n\t}\n\nexit:\n\n\n\treturn res;\n}\n\nu8 rtw_setrttbl_cmd(_adapter  *padapter, struct setratable_parm *prate_table)\n{\n\tstruct cmd_obj\t\t\t*ph2c;\n\tstruct setratable_parm\t*psetrttblparm;\n\tstruct cmd_priv\t\t\t*pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tpsetrttblparm = (struct setratable_parm *)rtw_zmalloc(sizeof(struct setratable_parm));\n\n\tif (psetrttblparm == NULL) {\n\t\trtw_mfree((unsigned char *) ph2c, sizeof(struct\tcmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, psetrttblparm, GEN_CMD_CODE(_SetRaTable));\n\n\t_rtw_memcpy(psetrttblparm, prate_table, sizeof(struct setratable_parm));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\nexit:\n\treturn res;\n\n}\n\nu8 rtw_getrttbl_cmd(_adapter  *padapter, struct getratable_rsp *pval)\n{\n\tstruct cmd_obj\t\t\t*ph2c;\n\tstruct getratable_parm\t*pgetrttblparm;\n\tstruct cmd_priv\t\t\t*pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tpgetrttblparm = (struct getratable_parm *)rtw_zmalloc(sizeof(struct getratable_parm));\n\n\tif (pgetrttblparm == NULL) {\n\t\trtw_mfree((unsigned char *) ph2c, sizeof(struct\tcmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t/*\tinit_h2fwcmd_w_parm_no_rsp(ph2c, psetrttblparm, GEN_CMD_CODE(_SetRaTable)); */\n\n\t_rtw_init_listhead(&ph2c->list);\n\tph2c->cmdcode = GEN_CMD_CODE(_GetRaTable);\n\tph2c->parmbuf = (unsigned char *)pgetrttblparm;\n\tph2c->cmdsz =  sizeof(struct getratable_parm);\n\tph2c->rsp = (u8 *)pval;\n\tph2c->rspsz = sizeof(struct getratable_rsp);\n\n\tpgetrttblparm->rsvd = 0x0;\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\nexit:\n\treturn res;\n\n}\n\nu8 rtw_setassocsta_cmd(_adapter  *padapter, u8 *mac_addr)\n{\n\tstruct cmd_priv\t\t*pcmdpriv = &padapter->cmdpriv;\n\tstruct cmd_obj\t\t\t*ph2c;\n\tstruct set_assocsta_parm\t*psetassocsta_para;\n\tstruct set_stakey_rsp\t\t*psetassocsta_rsp = NULL;\n\n\tu8\tres = _SUCCESS;\n\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpsetassocsta_para = (struct set_assocsta_parm *)rtw_zmalloc(sizeof(struct set_assocsta_parm));\n\tif (psetassocsta_para == NULL) {\n\t\trtw_mfree((u8 *) ph2c, sizeof(struct\tcmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpsetassocsta_rsp = (struct set_stakey_rsp *)rtw_zmalloc(sizeof(struct set_assocsta_rsp));\n\tif (psetassocsta_rsp == NULL) {\n\t\trtw_mfree((u8 *) ph2c, sizeof(struct\tcmd_obj));\n\t\trtw_mfree((u8 *) psetassocsta_para, sizeof(struct set_assocsta_parm));\n\t\treturn _FAIL;\n\t}\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, psetassocsta_para, _SetAssocSta_CMD_);\n\tph2c->rsp = (u8 *) psetassocsta_rsp;\n\tph2c->rspsz = sizeof(struct set_assocsta_rsp);\n\n\t_rtw_memcpy(psetassocsta_para->addr, mac_addr, ETH_ALEN);\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\n\n\treturn res;\n}\n\nu8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr)\n{\n\tstruct cmd_priv\t\t*pcmdpriv = &padapter->cmdpriv;\n\tstruct cmd_obj\t\t*ph2c;\n\tstruct addBaReq_parm\t*paddbareq_parm;\n\n\tu8\tres = _SUCCESS;\n\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpaddbareq_parm = (struct addBaReq_parm *)rtw_zmalloc(sizeof(struct addBaReq_parm));\n\tif (paddbareq_parm == NULL) {\n\t\trtw_mfree((unsigned char *)ph2c, sizeof(struct\tcmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpaddbareq_parm->tid = tid;\n\t_rtw_memcpy(paddbareq_parm->addr, addr, ETH_ALEN);\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, paddbareq_parm, GEN_CMD_CODE(_AddBAReq));\n\n\t/* RTW_INFO(\"rtw_addbareq_cmd, tid=%d\\n\", tid); */\n\n\t/* rtw_enqueue_cmd(pcmdpriv, ph2c);\t */\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\n\n\treturn res;\n}\n\nu8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u16 start_seq)\n{\n\tstruct cmd_priv *pcmdpriv = &padapter->cmdpriv;\n\tstruct cmd_obj *ph2c;\n\tstruct addBaRsp_parm *paddBaRsp_parm;\n\tu8 res = _SUCCESS;\n\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpaddBaRsp_parm = (struct addBaRsp_parm *)rtw_zmalloc(sizeof(struct addBaRsp_parm));\n\n\tif (paddBaRsp_parm == NULL) {\n\t\trtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t_rtw_memcpy(paddBaRsp_parm->addr, addr, ETH_ALEN);\n\tpaddBaRsp_parm->tid = tid;\n\tpaddBaRsp_parm->status = status;\n\tpaddBaRsp_parm->size = size;\n\tpaddBaRsp_parm->start_seq = start_seq;\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, paddBaRsp_parm, GEN_CMD_CODE(_AddBARsp));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\n\n\treturn res;\n}\n/* add for CONFIG_IEEE80211W, none 11w can use it */\nu8 rtw_reset_securitypriv_cmd(_adapter *padapter)\n{\n\tstruct cmd_obj\t\t*ph2c;\n\tstruct drvextra_cmd_parm  *pdrvextra_cmd_parm;\n\tstruct cmd_priv\t*pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm->ec_id = RESET_SECURITYPRIV;\n\tpdrvextra_cmd_parm->type = 0;\n\tpdrvextra_cmd_parm->size = 0;\n\tpdrvextra_cmd_parm->pbuf = NULL;\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\n\t/* rtw_enqueue_cmd(pcmdpriv, ph2c);\t */\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\n\n\treturn res;\n\n}\n\nvoid free_assoc_resources_hdl(_adapter *padapter, u8 lock_scanned_queue)\n{\n\trtw_free_assoc_resources(padapter, lock_scanned_queue);\n}\n\nu8 rtw_free_assoc_resources_cmd(_adapter *padapter, u8 lock_scanned_queue, int flags)\n{\n\tstruct cmd_obj *cmd;\n\tstruct drvextra_cmd_parm  *pdrvextra_cmd_parm;\n\tstruct cmd_priv\t*pcmdpriv = &padapter->cmdpriv;\n\tstruct submit_ctx sctx;\n\tu8\tres = _SUCCESS;\n\n\tif (flags & RTW_CMDF_DIRECTLY) {\n\t\tfree_assoc_resources_hdl(padapter, lock_scanned_queue);\n\t}\n\telse {\n\t\tcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\t\tif (cmd == NULL) {\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\t\tif (pdrvextra_cmd_parm == NULL) {\n\t\t\trtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpdrvextra_cmd_parm->ec_id = FREE_ASSOC_RESOURCES;\n\t\tpdrvextra_cmd_parm->type = lock_scanned_queue;\n\t\tpdrvextra_cmd_parm->size = 0;\n\t\tpdrvextra_cmd_parm->pbuf = NULL;\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(cmd, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\t\tif (flags & RTW_CMDF_WAIT_ACK) {\n\t\t\tcmd->sctx = &sctx;\n\t\t\trtw_sctx_init(&sctx, 2000);\n\t\t}\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, cmd);\n\n\t\tif (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {\n\t\t\trtw_sctx_wait(&sctx, __func__);\n\t\t\t_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t\tif (sctx.status == RTW_SCTX_SUBMITTED)\n\t\t\t\tcmd->sctx = NULL;\n\t\t\t_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t}\n\t}\nexit:\n\treturn res;\n\n}\n\nu8 rtw_dynamic_chk_wk_cmd(_adapter *padapter)\n{\n\tstruct cmd_obj\t\t*ph2c;\n\tstruct drvextra_cmd_parm  *pdrvextra_cmd_parm;\n\tstruct cmd_priv\t*pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\n\t/* only  primary padapter does this cmd */\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm->ec_id = DYNAMIC_CHK_WK_CID;\n\tpdrvextra_cmd_parm->type = 0;\n\tpdrvextra_cmd_parm->size = 0;\n\tpdrvextra_cmd_parm->pbuf = NULL;\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\n\t/* rtw_enqueue_cmd(pcmdpriv, ph2c);\t */\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\n\n\treturn res;\n\n}\n\nu8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags)\n{\n\tstruct cmd_obj *pcmdobj;\n\tstruct set_ch_parm *set_ch_parm;\n\tstruct cmd_priv *pcmdpriv = &padapter->cmdpriv;\n\tstruct submit_ctx sctx;\n\tu8 res = _SUCCESS;\n\n\n\tRTW_INFO(FUNC_NDEV_FMT\" ch:%u, bw:%u, ch_offset:%u\\n\",\n\t\t FUNC_NDEV_ARG(padapter->pnetdev), ch, bw, ch_offset);\n\n\t/* check input parameter */\n\n\t/* prepare cmd parameter */\n\tset_ch_parm = (struct set_ch_parm *)rtw_zmalloc(sizeof(*set_ch_parm));\n\tif (set_ch_parm == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tset_ch_parm->ch = ch;\n\tset_ch_parm->bw = bw;\n\tset_ch_parm->ch_offset = ch_offset;\n\n\tif (flags & RTW_CMDF_DIRECTLY) {\n\t\t/* no need to enqueue, do the cmd hdl directly and free cmd parameter */\n\t\tif (H2C_SUCCESS != rtw_set_chbw_hdl(padapter, (u8 *)set_ch_parm))\n\t\t\tres = _FAIL;\n\n\t\trtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm));\n\t} else {\n\t\t/* need enqueue, prepare cmd_obj and enqueue */\n\t\tpcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct\tcmd_obj));\n\t\tif (pcmdobj == NULL) {\n\t\t\trtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(pcmdobj, set_ch_parm, GEN_CMD_CODE(_SetChannel));\n\n\t\tif (flags & RTW_CMDF_WAIT_ACK) {\n\t\t\tpcmdobj->sctx = &sctx;\n\t\t\trtw_sctx_init(&sctx, 10 * 1000);\n\t\t}\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, pcmdobj);\n\n\t\tif (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {\n\t\t\trtw_sctx_wait(&sctx, __func__);\n\t\t\t_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t\tif (sctx.status == RTW_SCTX_SUBMITTED)\n\t\t\t\tpcmdobj->sctx = NULL;\n\t\t\t_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t}\n\t}\n\n\t/* do something based on res... */\n\nexit:\n\n\tRTW_INFO(FUNC_NDEV_FMT\" res:%u\\n\", FUNC_NDEV_ARG(padapter->pnetdev), res);\n\n\n\treturn res;\n}\n\nu8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const struct country_chplan *country_ent, u8 swconfig)\n{\n\tstruct cmd_obj *cmdobj;\n\tstruct\tSetChannelPlan_param *parm;\n\tstruct cmd_priv *pcmdpriv = &adapter->cmdpriv;\n\tstruct submit_ctx sctx;\n\tu8 res = _SUCCESS;\n\n\n\t/* check if allow software config */\n\tif (swconfig && rtw_hal_is_disable_sw_channel_plan(adapter) == _TRUE) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t/* if country_entry is provided, replace chplan */\n\tif (country_ent)\n\t\tchplan = country_ent->chplan;\n\n\t/* check input parameter */\n\tif (!rtw_is_channel_plan_valid(chplan)) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t/* prepare cmd parameter */\n\tparm = (struct SetChannelPlan_param *)rtw_zmalloc(sizeof(*parm));\n\tif (parm == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tparm->country_ent = country_ent;\n\tparm->channel_plan = chplan;\n\n\tif (flags & RTW_CMDF_DIRECTLY) {\n\t\t/* no need to enqueue, do the cmd hdl directly and free cmd parameter */\n\t\tif (H2C_SUCCESS != set_chplan_hdl(adapter, (u8 *)parm))\n\t\t\tres = _FAIL;\n\t\trtw_mfree((u8 *)parm, sizeof(*parm));\n\t} else {\n\t\t/* need enqueue, prepare cmd_obj and enqueue */\n\t\tcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));\n\t\tif (cmdobj == NULL) {\n\t\t\tres = _FAIL;\n\t\t\trtw_mfree((u8 *)parm, sizeof(*parm));\n\t\t\tgoto exit;\n\t\t}\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_SetChannelPlan));\n\n\t\tif (flags & RTW_CMDF_WAIT_ACK) {\n\t\t\tcmdobj->sctx = &sctx;\n\t\t\trtw_sctx_init(&sctx, 2000);\n\t\t}\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, cmdobj);\n\n\t\tif (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {\n\t\t\trtw_sctx_wait(&sctx, __func__);\n\t\t\t_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t\tif (sctx.status == RTW_SCTX_SUBMITTED)\n\t\t\t\tcmdobj->sctx = NULL;\n\t\t\t_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t\tif (sctx.status != RTW_SCTX_DONE_SUCCESS)\n\t\t\t\tres = _FAIL;\n\t\t}\n\n\t\t/* allow set channel plan when cmd_thread is not running */\n\t\tif (res != _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {\n\t\t\tparm = (struct SetChannelPlan_param *)rtw_zmalloc(sizeof(*parm));\n\t\t\tif (parm == NULL) {\n\t\t\t\tres = _FAIL;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tparm->country_ent = country_ent;\n\t\t\tparm->channel_plan = chplan;\n\n\t\t\tif (H2C_SUCCESS != set_chplan_hdl(adapter, (u8 *)parm))\n\t\t\t\tres = _FAIL;\n\t\t\telse\n\t\t\t\tres = _SUCCESS;\n\t\t\trtw_mfree((u8 *)parm, sizeof(*parm));\n\t\t}\n\t}\n\nexit:\n\treturn res;\n}\n\ninline u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 swconfig)\n{\n\treturn _rtw_set_chplan_cmd(adapter, flags, chplan, NULL, swconfig);\n}\n\ninline u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, u8 swconfig)\n{\n\tconst struct country_chplan *ent;\n\n\tif (is_alpha(country_code[0]) == _FALSE\n\t    || is_alpha(country_code[1]) == _FALSE\n\t   ) {\n\t\tRTW_PRINT(\"%s input country_code is not alpha2\\n\", __func__);\n\t\treturn _FAIL;\n\t}\n\n\tent = rtw_get_chplan_from_country(country_code);\n\n\tif (ent == NULL) {\n\t\tRTW_PRINT(\"%s unsupported country_code:\\\"%c%c\\\"\\n\", __func__, country_code[0], country_code[1]);\n\t\treturn _FAIL;\n\t}\n\n\tRTW_PRINT(\"%s country_code:\\\"%c%c\\\" mapping to chplan:0x%02x\\n\", __func__, country_code[0], country_code[1], ent->chplan);\n\n\treturn _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_UNSPECIFIED, ent, swconfig);\n}\n\nu8 rtw_led_blink_cmd(_adapter *padapter, void *pLed)\n{\n\tstruct\tcmd_obj\t*pcmdobj;\n\tstruct\tLedBlink_param *ledBlink_param;\n\tstruct\tcmd_priv   *pcmdpriv = &padapter->cmdpriv;\n\n\tu8\tres = _SUCCESS;\n\n\n\n\tpcmdobj = (struct\tcmd_obj *)rtw_zmalloc(sizeof(struct\tcmd_obj));\n\tif (pcmdobj == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tledBlink_param = (struct\tLedBlink_param *)rtw_zmalloc(sizeof(struct\tLedBlink_param));\n\tif (ledBlink_param == NULL) {\n\t\trtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tledBlink_param->pLed = pLed;\n\n\tinit_h2fwcmd_w_parm_no_rsp(pcmdobj, ledBlink_param, GEN_CMD_CODE(_LedBlink));\n\tres = rtw_enqueue_cmd(pcmdpriv, pcmdobj);\n\nexit:\n\n\n\treturn res;\n}\n\nu8 rtw_set_csa_cmd(_adapter *adapter)\n{\n\tstruct cmd_obj *cmdobj;\n\tstruct cmd_priv *cmdpriv = &adapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\tcmdobj = rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (cmdobj == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tinit_h2fwcmd_w_parm_no_parm_rsp(cmdobj, GEN_CMD_CODE(_SetChannelSwitch));\n\tres = rtw_enqueue_cmd(cmdpriv, cmdobj);\n\nexit:\n\treturn res;\n}\n\nu8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option)\n{\n\tu8 res = _SUCCESS;\n#ifdef CONFIG_TDLS\n\tstruct\tcmd_obj\t*pcmdobj;\n\tstruct\tTDLSoption_param\t*TDLSoption;\n\tstruct\tmlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct\tcmd_priv   *pcmdpriv = &padapter->cmdpriv;\n\n\tpcmdobj = (struct\tcmd_obj *)rtw_zmalloc(sizeof(struct\tcmd_obj));\n\tif (pcmdobj == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tTDLSoption = (struct TDLSoption_param *)rtw_zmalloc(sizeof(struct TDLSoption_param));\n\tif (TDLSoption == NULL) {\n\t\trtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t_rtw_spinlock(&(padapter->tdlsinfo.cmd_lock));\n\tif (addr != NULL)\n\t\t_rtw_memcpy(TDLSoption->addr, addr, 6);\n\tTDLSoption->option = option;\n\t_rtw_spinunlock(&(padapter->tdlsinfo.cmd_lock));\n\tinit_h2fwcmd_w_parm_no_rsp(pcmdobj, TDLSoption, GEN_CMD_CODE(_TDLS));\n\tres = rtw_enqueue_cmd(pcmdpriv, pcmdobj);\n\nexit:\n#endif /* CONFIG_TDLS */\n\n\treturn res;\n}\n\nu8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter)\n{\n\tstruct cmd_obj *ph2c;\n\tstruct drvextra_cmd_parm\t*pdrvextra_cmd_parm;\n\tstruct cmd_priv *pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm->ec_id = EN_HW_UPDATE_TSF_WK_CID;\n\tpdrvextra_cmd_parm->type = 0;\n\tpdrvextra_cmd_parm->size = 0;\n\tpdrvextra_cmd_parm->pbuf = NULL;\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\treturn res;\n}\n\nu8 rtw_periodic_tsf_update_end_cmd(_adapter *adapter)\n{\n\tstruct cmd_obj *cmdobj;\n\tstruct drvextra_cmd_parm *parm;\n\tstruct cmd_priv *cmdpriv = &adapter->cmdpriv;\n\tu8 res = _SUCCESS;\n\n\tcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (cmdobj == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tparm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (parm == NULL) {\n\t\trtw_mfree((unsigned char *)cmdobj, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tparm->ec_id = PERIOD_TSF_UPDATE_END_WK_CID;\n\tparm->type = 0;\n\tparm->size = 0;\n\tparm->pbuf = NULL;\n\n\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\tres = rtw_enqueue_cmd(cmdpriv, cmdobj);\n\nexit:\n\treturn res;\n}\nu8 rtw_ssmps_wk_hdl(_adapter *adapter, struct ssmps_cmd_parm *ssmp_param)\n{\n\tu8 res = _SUCCESS;\n\tstruct sta_info *sta = ssmp_param->sta;\n\tu8 smps = ssmp_param->smps;\n\n\tif (sta == NULL)\n\t\treturn _FALSE;\n\n\tif (smps)\n\t\trtw_ssmps_enter(adapter, sta);\n\telse\n\t\trtw_ssmps_leave(adapter, sta);\n\treturn res;\n}\n\nu8 rtw_ssmps_wk_cmd(_adapter *adapter, struct sta_info *sta, u8 smps, u8 enqueue)\n{\n\tstruct cmd_obj *cmdobj;\n\tstruct drvextra_cmd_parm *cmd_parm;\n\tstruct ssmps_cmd_parm *ssmp_param;\n\tstruct cmd_priv\t*pcmdpriv = &adapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\tif (enqueue) {\n\t\tcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\t\tif (cmdobj == NULL) {\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tcmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\t\tif (cmd_parm == NULL) {\n\t\t\trtw_mfree((unsigned char *)cmdobj, sizeof(struct cmd_obj));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tssmp_param = (struct ssmps_cmd_parm *)rtw_zmalloc(sizeof(struct ssmps_cmd_parm));\n\t\tif (ssmp_param == NULL) {\n\t\t\trtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));\n\t\t\trtw_mfree((u8 *)cmd_parm, sizeof(struct drvextra_cmd_parm));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tssmp_param->smps = smps;\n\t\tssmp_param->sta = sta;\n\n\t\tcmd_parm->ec_id = SSMPS_WK_CID;\n\t\tcmd_parm->type = 0;\n\t\tcmd_parm->size = sizeof(struct ssmps_cmd_parm);\n\t\tcmd_parm->pbuf = (u8 *)ssmp_param;\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, cmdobj);\n\t} else {\n\t\tstruct ssmps_cmd_parm tmp_ssmp_param;\n\n\t\ttmp_ssmp_param.smps = smps;\n\t\ttmp_ssmp_param.sta = sta;\n\t\trtw_ssmps_wk_hdl(adapter, &tmp_ssmp_param);\n\t}\n\nexit:\n\treturn res;\n}\n\n#ifdef CONFIG_SUPPORT_STATIC_SMPS\nu8 _ssmps_chk_by_tp(_adapter *adapter, u8 from_timer)\n{\n\tu8 enter_smps = _FALSE;\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\tstruct sta_priv *pstapriv = &adapter->stapriv;\n\tstruct sta_info *psta;\n\tu32 tx_tp_mbits, rx_tp_mbits;\n\n\tif (!MLME_IS_STA(adapter) ||\n\t\t!hal_is_mimo_support(adapter) ||\n\t\t!pmlmeext->ssmps_en ||\n\t\t(pmlmeext->cur_channel > 14)\n\t)\n\t\treturn enter_smps;\n\n\tpsta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));\n\tif (psta == NULL) {\n\t\tRTW_ERR(ADPT_FMT\" sta == NULL\\n\", ADPT_ARG(adapter));\n\t\trtw_warn_on(1);\n\t\treturn enter_smps;\n\t}\n\n\tif (psta->cmn.mimo_type == RF_1T1R)\n\t\treturn enter_smps;\n\n\ttx_tp_mbits = psta->sta_stats.tx_tp_kbits >> 10;\n\trx_tp_mbits = psta->sta_stats.rx_tp_kbits >> 10;\n\n\t#ifdef DBG_STATIC_SMPS\n\tif (pmlmeext->ssmps_test) {\n\t\tenter_smps = (pmlmeext->ssmps_test_en == 1) ? _TRUE : _FALSE;\n\t}\n\telse\n\t#endif\n\t{\n\t\tif ((tx_tp_mbits <= pmlmeext->ssmps_tx_tp_th) &&\n\t\t\t(rx_tp_mbits <= pmlmeext->ssmps_rx_tp_th))\n\t\t\tenter_smps = _TRUE;\n\t\telse\n\t\t\tenter_smps = _FALSE;\n\t}\n\n\tif (1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" tx_tp:%d [%d], rx_tp:%d [%d] , SSMPS enter :%s\\n\",\n\t\t\tFUNC_ADPT_ARG(adapter),\n\t\t\ttx_tp_mbits, pmlmeext->ssmps_tx_tp_th,\n\t\t\trx_tp_mbits, pmlmeext->ssmps_rx_tp_th,\n\t\t\t(enter_smps == _TRUE) ? \"True\" : \"False\");\n\t\t#ifdef DBG_STATIC_SMPS\n\t\tRTW_INFO(FUNC_ADPT_FMT\" test:%d test_en:%d\\n\",\n\t\t\tFUNC_ADPT_ARG(adapter),\n\t\t\tpmlmeext->ssmps_test,\n\t\t\tpmlmeext->ssmps_test_en);\n\t\t#endif\n\t}\n\n\tif (enter_smps) {\n\t\tif (!from_timer && psta->cmn.sm_ps != SM_PS_STATIC)\n\t\t\trtw_ssmps_enter(adapter, psta);\n\t} else {\n\t\tif (!from_timer && psta->cmn.sm_ps != SM_PS_DISABLE)\n\t\t\trtw_ssmps_leave(adapter, psta);\n\t\telse {\n\t\t\tu8 ps_change = _FALSE;\n\n\t\t\tif (enter_smps && psta->cmn.sm_ps != SM_PS_STATIC)\n\t\t\t\tps_change = _TRUE;\n\t\t\telse if (!enter_smps && psta->cmn.sm_ps != SM_PS_DISABLE)\n\t\t\t\tps_change = _TRUE;\n\n\t\t\tif (ps_change)\n\t\t\t\trtw_ssmps_wk_cmd(adapter, psta, enter_smps, 1);\n\t\t}\n\t}\n\n\treturn enter_smps;\n}\n#endif /*CONFIG_SUPPORT_STATIC_SMPS*/\n\n#ifdef CONFIG_CTRL_TXSS_BY_TP\nvoid rtw_ctrl_txss_update_mimo_type(_adapter *adapter, struct sta_info *sta)\n{\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\n\tpmlmeext->txss_momi_type_bk = sta->cmn.mimo_type;\n}\n\nu8 rtw_ctrl_txss(_adapter *adapter, struct sta_info *sta, bool tx_1ss)\n{\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\tu8 lps_changed = _FALSE;\n\tu8 rst = _SUCCESS;\n\n\tif (pmlmeext->txss_1ss == tx_1ss)\n\t\treturn _FALSE;\n\n\tif (pwrpriv->bLeisurePs && pwrpriv->pwr_mode != PS_MODE_ACTIVE) {\n\t\tlps_changed = _TRUE;\n\t\tLPS_Leave(adapter, \"LPS_CTRL_TXSS\");\n\t}\n\n\tRTW_INFO(ADPT_FMT\" STA [\" MAC_FMT \"] set tx to %d ss\\n\",\n\t\tADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr),\n\t\t(tx_1ss) ? 1 : rtw_get_sta_tx_nss(adapter, sta));\n\n\t/*ra re-registed*/\n\tsta->cmn.mimo_type = (tx_1ss) ? RF_1T1R : pmlmeext->txss_momi_type_bk;\n\trtw_phydm_ra_registed(adapter, sta);\n\n\t/*configure trx mode*/\n\trtw_phydm_trx_cfg(adapter, tx_1ss);\n\tpmlmeext->txss_1ss = tx_1ss;\n\n\tif (lps_changed)\n\t\tLPS_Enter(adapter, \"LPS_CTRL_TXSS\");\n\n\treturn rst;\n}\n\nu8 rtw_ctrl_txss_wk_hdl(_adapter *adapter, struct txss_cmd_parm *txss_param)\n{\n\tif (!txss_param->sta)\n\t\treturn _FALSE;\n\n\treturn rtw_ctrl_txss(adapter, txss_param->sta, txss_param->tx_1ss);\n}\n\nu8 rtw_ctrl_txss_wk_cmd(_adapter *adapter, struct sta_info *sta, bool tx_1ss, u8 flag)\n{\n\tstruct cmd_obj *cmdobj;\n\tstruct drvextra_cmd_parm *cmd_parm;\n\tstruct txss_cmd_parm *txss_param;\n\tstruct cmd_priv *pcmdpriv = &adapter->cmdpriv;\n\tstruct submit_ctx sctx;\n\tu8\tres = _SUCCESS;\n\n\ttxss_param = (struct txss_cmd_parm *)rtw_zmalloc(sizeof(struct txss_cmd_parm));\n\tif (txss_param == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\ttxss_param->tx_1ss = tx_1ss;\n\ttxss_param->sta = sta;\n\n\tif (flag & RTW_CMDF_DIRECTLY) {\n\t\tres = rtw_ctrl_txss_wk_hdl(adapter, txss_param);\n\t\trtw_mfree((u8 *)txss_param, sizeof(*txss_param));\n\t} else {\n\t\tcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\t\tif (cmdobj == NULL) {\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tcmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\t\tif (cmd_parm == NULL) {\n\t\t\trtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tcmd_parm->ec_id = TXSS_WK_CID;\n\t\tcmd_parm->type = 0;\n\t\tcmd_parm->size = sizeof(struct txss_cmd_parm);\n\t\tcmd_parm->pbuf = (u8 *)txss_param;\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\t\tif (flag & RTW_CMDF_WAIT_ACK) {\n\t\t\tcmdobj->sctx = &sctx;\n\t\t\trtw_sctx_init(&sctx, 10 * 1000);\n\t\t}\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, cmdobj);\n\t\tif (res == _SUCCESS && (flag & RTW_CMDF_WAIT_ACK)) {\n\t\t\trtw_sctx_wait(&sctx, __func__);\n\t\t\t_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t\tif (sctx.status == RTW_SCTX_SUBMITTED)\n\t\t\t\tcmdobj->sctx = NULL;\n\t\t\t_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t\tif (sctx.status != RTW_SCTX_DONE_SUCCESS)\n\t\t\t\tres = _FAIL;\n\t\t}\n\t}\n\nexit:\n\treturn res;\n}\n\nvoid rtw_ctrl_tx_ss_by_tp(_adapter *adapter, u8 from_timer)\n{\n\tbool tx_1ss  = _FALSE; /*change tx from 2ss to 1ss*/\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\tstruct sta_priv *pstapriv = &adapter->stapriv;\n\tstruct sta_info *psta;\n\tu32 tx_tp_mbits;\n\n\tif (!MLME_IS_STA(adapter) ||\n\t\t!hal_is_mimo_support(adapter) ||\n\t\t!pmlmeext->txss_ctrl_en\n\t)\n\t\treturn;\n\n\tpsta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));\n\tif (psta == NULL) {\n\t\tRTW_ERR(ADPT_FMT\" sta == NULL\\n\", ADPT_ARG(adapter));\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\ttx_tp_mbits = psta->sta_stats.tx_tp_kbits >> 10;\n\tif (tx_tp_mbits >= pmlmeext->txss_tp_th) {\n\t\ttx_1ss = _FALSE;\n\t} else {\n\t\tif (pmlmeext->txss_tp_chk_cnt && --pmlmeext->txss_tp_chk_cnt)\n\t\t\ttx_1ss = _FALSE;\n\t\telse\n\t\t\ttx_1ss = _TRUE;\n\t}\n\n\tif (1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" tx_tp:%d [%d] tx_1ss(%d):%s\\n\",\n\t\t\tFUNC_ADPT_ARG(adapter),\n\t\t\ttx_tp_mbits, pmlmeext->txss_tp_th,\n\t\t\tpmlmeext->txss_tp_chk_cnt,\n\t\t\t(tx_1ss == _TRUE) ? \"True\" : \"False\");\n\t}\n\n\tif (pmlmeext->txss_1ss != tx_1ss) {\n\t\tif (from_timer)\n\t\t\trtw_ctrl_txss_wk_cmd(adapter, psta, tx_1ss, 0);\n\t\telse\n\t\t\trtw_ctrl_txss(adapter, psta, tx_1ss);\n\t}\n}\n#ifdef DBG_CTRL_TXSS\nvoid dbg_ctrl_txss(_adapter *adapter, bool tx_1ss)\n{\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\tstruct sta_priv *pstapriv = &adapter->stapriv;\n\tstruct sta_info *psta;\n\n\tif (!MLME_IS_STA(adapter) ||\n\t\t!hal_is_mimo_support(adapter)\n\t)\n\t\treturn;\n\n\tpsta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));\n\tif (psta == NULL) {\n\t\tRTW_ERR(ADPT_FMT\" sta == NULL\\n\", ADPT_ARG(adapter));\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\trtw_ctrl_txss(adapter, psta, tx_1ss);\n}\n#endif\n#endif /*CONFIG_CTRL_TXSS_BY_TP*/\n\n#ifdef CONFIG_LPS\n#ifdef CONFIG_LPS_CHK_BY_TP\n#ifdef LPS_BCN_CNT_MONITOR\nstatic u8 _bcn_cnt_expected(struct sta_info *psta)\n{\n\t_adapter *adapter = psta->padapter;\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8 dtim = rtw_get_bcn_dtim_period(adapter);\n\tu8 bcn_cnt = 0;\n\n\tif ((pmlmeinfo->bcn_interval !=0) && (dtim != 0))\n\t\tbcn_cnt = 2000 / pmlmeinfo->bcn_interval / dtim * 4 / 5; /*2s*/\n\tif (0)\n\t\tRTW_INFO(\"%s bcn_cnt:%d\\n\", __func__, bcn_cnt);\n\n\tif (bcn_cnt == 0) {\n\t\tRTW_ERR(FUNC_ADPT_FMT\" bcn_cnt == 0\\n\", FUNC_ADPT_ARG(adapter));\n\t\trtw_warn_on(1);\n\t}\n\n\treturn bcn_cnt;\n}\n#endif\nu8 _lps_chk_by_tp(_adapter *adapter, u8 from_timer)\n{\n\tu8 enter_ps = _FALSE;\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tstruct sta_priv *pstapriv = &adapter->stapriv;\n\tstruct sta_info *psta;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\tu32 tx_tp_mbits, rx_tp_mbits, bi_tp_mbits;\n\tu8 rx_bcn_cnt;\n\n\tpsta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));\n\tif (psta == NULL) {\n\t\tRTW_ERR(ADPT_FMT\" sta == NULL\\n\", ADPT_ARG(adapter));\n\t\trtw_warn_on(1);\n\t\treturn enter_ps;\n\t}\n\n\trx_bcn_cnt = rtw_get_bcn_cnt(psta->padapter);\n\tpsta->sta_stats.acc_tx_bytes = psta->sta_stats.tx_bytes;\n\tpsta->sta_stats.acc_rx_bytes = psta->sta_stats.rx_bytes;\n\n#if 1\n\ttx_tp_mbits = psta->sta_stats.tx_tp_kbits >> 10;\n\trx_tp_mbits = psta->sta_stats.rx_tp_kbits >> 10;\n\tbi_tp_mbits = tx_tp_mbits + rx_tp_mbits;\n#else\n\ttx_tp_mbits = psta->sta_stats.smooth_tx_tp_kbits >> 10;\n\trx_tp_mbits = psta->sta_stats.smooth_rx_tp_kbits >> 10;\n\tbi_tp_mbits = tx_tp_mbits + rx_tp_mbits;\n#endif\n\n\tif ((bi_tp_mbits >= pwrpriv->lps_bi_tp_th) ||\n\t\t(tx_tp_mbits >= pwrpriv->lps_tx_tp_th) ||\n\t\t(rx_tp_mbits >= pwrpriv->lps_rx_tp_th)) {\n\t\tenter_ps = _FALSE;\n\t\tpwrpriv->lps_chk_cnt = pwrpriv->lps_chk_cnt_th;\n\t}\n\telse {\n#ifdef LPS_BCN_CNT_MONITOR\n\t\tu8 bcn_cnt = _bcn_cnt_expected(psta);\n\n\t\tif (bcn_cnt && (rx_bcn_cnt < bcn_cnt)) {\n\t\t\tpwrpriv->lps_chk_cnt = 2;\n\t\t\tRTW_ERR(FUNC_ADPT_FMT\" BCN_CNT:%d(%d) invalid\\n\",\n\t\t\t\tFUNC_ADPT_ARG(adapter), rx_bcn_cnt, bcn_cnt);\n\t\t}\n#endif\n\n\t\tif (pwrpriv->lps_chk_cnt && --pwrpriv->lps_chk_cnt)\n\t\t\tenter_ps = _FALSE;\n\t\telse\n\t\t\tenter_ps = _TRUE;\n\t}\n\n\tif (1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" tx_tp:%d [%d], rx_tp:%d [%d], bi_tp:%d [%d], enter_ps(%d):%s\\n\",\n\t\t\tFUNC_ADPT_ARG(adapter),\n\t\t\ttx_tp_mbits, pwrpriv->lps_tx_tp_th,\n\t\t\trx_tp_mbits, pwrpriv->lps_rx_tp_th,\n\t\t\tbi_tp_mbits, pwrpriv->lps_bi_tp_th,\n\t\t\tpwrpriv->lps_chk_cnt,\n\t\t\t(enter_ps == _TRUE) ? \"True\" : \"False\");\n\t\tRTW_INFO(FUNC_ADPT_FMT\" tx_pkt_cnt :%d [%d], rx_pkt_cnt :%d [%d]\\n\",\n\t\t\tFUNC_ADPT_ARG(adapter),\n\t\t\tpmlmepriv->LinkDetectInfo.NumTxOkInPeriod,\n\t\t\tpwrpriv->lps_tx_pkts,\n\t\t\tpmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod,\n\t\t\tpwrpriv->lps_rx_pkts);\n\t\tif (!adapter->bsta_tp_dump)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" bcn_cnt:%d (per-%d second)\\n\",\n\t\t\tFUNC_ADPT_ARG(adapter),\n\t\t\trx_bcn_cnt,\n\t\t\t2);\n\t}\n\n\tif (enter_ps) {\n\t\tif (!from_timer)\n\t\t\tLPS_Enter(adapter, \"TRAFFIC_IDLE\");\n\t} else {\n\t\tif (!from_timer)\n\t\t\tLPS_Leave(adapter, \"TRAFFIC_BUSY\");\n\t\telse {\n\t\t\t#ifdef CONFIG_CONCURRENT_MODE\n\t\t\t#ifndef CONFIG_FW_MULTI_PORT_SUPPORT\n\t\t\tif (adapter->hw_port == HW_PORT0)\n\t\t\t#endif\n\t\t\t#endif\n\t\t\t\trtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_TRAFFIC_BUSY, 0);\n\t\t}\n\t}\n\n\treturn enter_ps;\n}\n#endif\n\nstatic u8 _lps_chk_by_pkt_cnts(_adapter *padapter, u8 from_timer, u8 bBusyTraffic)\n{\t\t\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tu8\tbEnterPS = _FALSE;\n\n\t/* check traffic for  powersaving. */\n\tif (((pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod) > 8) ||\n\t\t#ifdef CONFIG_LPS_SLOW_TRANSITION\n\t\t(pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 2)\n\t\t#else /* CONFIG_LPS_SLOW_TRANSITION */\n\t\t(pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 4)\n\t\t#endif /* CONFIG_LPS_SLOW_TRANSITION */\n\t) {\n\t\t#ifdef DBG_RX_COUNTER_DUMP\n\t\tif (padapter->dump_rx_cnt_mode & DUMP_DRV_TRX_COUNTER_DATA)\n\t\t\tRTW_INFO(\"(-)Tx = %d, Rx = %d\\n\", pmlmepriv->LinkDetectInfo.NumTxOkInPeriod, pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod);\n\t\t#endif\n\n\t\tbEnterPS = _FALSE;\n\t\t#ifdef CONFIG_LPS_SLOW_TRANSITION\n\t\tif (bBusyTraffic == _TRUE) {\n\t\t\tif (pmlmepriv->LinkDetectInfo.TrafficTransitionCount <= 4)\n\t\t\t\tpmlmepriv->LinkDetectInfo.TrafficTransitionCount = 4;\n\n\t\t\tpmlmepriv->LinkDetectInfo.TrafficTransitionCount++;\n\n\t\t\t/* RTW_INFO(\"Set TrafficTransitionCount to %d\\n\", pmlmepriv->LinkDetectInfo.TrafficTransitionCount); */\n\n\t\t\tif (pmlmepriv->LinkDetectInfo.TrafficTransitionCount > 30/*TrafficTransitionLevel*/)\n\t\t\t\tpmlmepriv->LinkDetectInfo.TrafficTransitionCount = 30;\n\t\t}\n\t\t#endif /* CONFIG_LPS_SLOW_TRANSITION */\n\t} else {\n\t\t#ifdef DBG_RX_COUNTER_DUMP\n\t\tif (padapter->dump_rx_cnt_mode & DUMP_DRV_TRX_COUNTER_DATA)\n\t\t\tRTW_INFO(\"(+)Tx = %d, Rx = %d\\n\", pmlmepriv->LinkDetectInfo.NumTxOkInPeriod, pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod);\n\t\t#endif\n\n\t\t#ifdef CONFIG_LPS_SLOW_TRANSITION\n\t\tif (pmlmepriv->LinkDetectInfo.TrafficTransitionCount >= 2)\n\t\t\tpmlmepriv->LinkDetectInfo.TrafficTransitionCount -= 2;\n\t\telse\n\t\t\tpmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0;\n\n\t\tif (pmlmepriv->LinkDetectInfo.TrafficTransitionCount == 0)\n\t\t\tbEnterPS = _TRUE;\n\t\t#else /* CONFIG_LPS_SLOW_TRANSITION */\n\t\t\tbEnterPS = _TRUE;\n\t\t#endif /* CONFIG_LPS_SLOW_TRANSITION */\n\t}\n\n\t#ifdef CONFIG_DYNAMIC_DTIM\n\tif (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount == 8)\n\t\tbEnterPS = _FALSE;\n\n\tRTW_INFO(\"LowPowerTransitionCount=%d\\n\", pmlmepriv->LinkDetectInfo.LowPowerTransitionCount);\n\t#endif /* CONFIG_DYNAMIC_DTIM */\n\n\t/* LeisurePS only work in infra mode. */\n\tif (bEnterPS) {\n\t\tif (!from_timer) {\n\t\t\t#ifdef CONFIG_DYNAMIC_DTIM\n\t\t\tif (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount < 8)\n\t\t\t\tadapter_to_pwrctl(padapter)->dtim = 1;\n\t\t\telse\n\t\t\t\tadapter_to_pwrctl(padapter)->dtim = 3;\n\t\t\t#endif /* CONFIG_DYNAMIC_DTIM */\n\t\t\tLPS_Enter(padapter, \"TRAFFIC_IDLE\");\n\t\t} else {\n\t\t\t/* do this at caller */\n\t\t\t/* rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_ENTER, 0); */\n\t\t\t/* rtw_hal_dm_watchdog_in_lps(padapter); */\n\t\t}\n\n\t\t#ifdef CONFIG_DYNAMIC_DTIM\n\t\tif (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE)\n\t\t\tpmlmepriv->LinkDetectInfo.LowPowerTransitionCount++;\n\t\t#endif /* CONFIG_DYNAMIC_DTIM */\n\t} else {\n\t\t#ifdef CONFIG_DYNAMIC_DTIM\n\t\tif (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount != 8)\n\t\t\tpmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0;\n\t\telse\n\t\t\tpmlmepriv->LinkDetectInfo.LowPowerTransitionCount++;\n\t\t#endif /* CONFIG_DYNAMIC_DTIM */\n\n\t\tif (!from_timer)\n\t\t\tLPS_Leave(padapter, \"TRAFFIC_BUSY\");\n\t\telse {\n\t\t\t#ifdef CONFIG_CONCURRENT_MODE\n\t\t\t#ifndef CONFIG_FW_MULTI_PORT_SUPPORT\n\t\t\tif (padapter->hw_port == HW_PORT0)\n\t\t\t#endif\n\t\t\t#endif\n\t\t\t\trtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_TRAFFIC_BUSY, 0);\n\t\t}\n\t}\n\n\treturn bEnterPS;\n}\n#endif /* CONFIG_LPS */\n\n/* from_timer == 1 means driver is in LPS */\nu8 traffic_status_watchdog(_adapter *padapter, u8 from_timer)\n{\n\tu8\tbEnterPS = _FALSE;\n\tu16 BusyThresholdHigh;\n\tu16\tBusyThresholdLow;\n\tu16\tBusyThreshold;\n\tu8\tbBusyTraffic = _FALSE, bTxBusyTraffic = _FALSE, bRxBusyTraffic = _FALSE;\n\tu8\tbHigherBusyTraffic = _FALSE, bHigherBusyRxTraffic = _FALSE, bHigherBusyTxTraffic = _FALSE;\n\n\tstruct mlme_priv\t\t*pmlmepriv = &(padapter->mlmepriv);\n#ifdef CONFIG_TDLS\n\tstruct tdls_info *ptdlsinfo = &(padapter->tdlsinfo);\n\tstruct tdls_txmgmt txmgmt;\n\tu8 baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };\n#endif /* CONFIG_TDLS */\n#ifdef CONFIG_TRAFFIC_PROTECT\n\tRT_LINK_DETECT_T *link_detect = &pmlmepriv->LinkDetectInfo;\n#endif\n\n#ifdef CONFIG_BT_COEXIST\n\tif (padapter->registrypriv.wifi_spec != 1) {\n\t\tBusyThresholdHigh = 25;\n\t\tBusyThresholdLow = 10;\n\t} else\n#endif /* CONFIG_BT_COEXIST */\n\t{\n\t\tBusyThresholdHigh = 100;\n\t\tBusyThresholdLow = 75;\n\t}\n\tBusyThreshold = BusyThresholdHigh;\n\n\n\t/*  */\n\t/* Determine if our traffic is busy now */\n\t/*  */\n\tif ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t    /*&& !MgntInitAdapterInProgress(pMgntInfo)*/) {\n\t\t/* if we raise bBusyTraffic in last watchdog, using lower threshold. */\n\t\tif (pmlmepriv->LinkDetectInfo.bBusyTraffic)\n\t\t\tBusyThreshold = BusyThresholdLow;\n\n\t\tif (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > BusyThreshold ||\n\t\t    pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > BusyThreshold) {\n\t\t\tbBusyTraffic = _TRUE;\n\n\t\t\tif (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > pmlmepriv->LinkDetectInfo.NumTxOkInPeriod)\n\t\t\t\tbRxBusyTraffic = _TRUE;\n\t\t\telse\n\t\t\t\tbTxBusyTraffic = _TRUE;\n\t\t}\n\n\t\t/* Higher Tx/Rx data. */\n\t\tif (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > 4000 ||\n\t\t    pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > 4000) {\n\t\t\tbHigherBusyTraffic = _TRUE;\n\n\t\t\tif (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > pmlmepriv->LinkDetectInfo.NumTxOkInPeriod)\n\t\t\t\tbHigherBusyRxTraffic = _TRUE;\n\t\t\telse\n\t\t\t\tbHigherBusyTxTraffic = _TRUE;\n\t\t}\n\n#ifdef CONFIG_TRAFFIC_PROTECT\n#define TX_ACTIVE_TH 10\n#define RX_ACTIVE_TH 20\n#define TRAFFIC_PROTECT_PERIOD_MS 4500\n\n\t\tif (link_detect->NumTxOkInPeriod > TX_ACTIVE_TH\n\t\t    || link_detect->NumRxUnicastOkInPeriod > RX_ACTIVE_TH) {\n\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" acqiure wake_lock for %u ms(tx:%d,rx_unicast:%d)\\n\",\n\t\t\t\t FUNC_ADPT_ARG(padapter),\n\t\t\t\t TRAFFIC_PROTECT_PERIOD_MS,\n\t\t\t\t link_detect->NumTxOkInPeriod,\n\t\t\t\t link_detect->NumRxUnicastOkInPeriod);\n\n\t\t\trtw_lock_traffic_suspend_timeout(TRAFFIC_PROTECT_PERIOD_MS);\n\t\t}\n#endif\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_AUTOSETUP\n\t\t/* TDLS_WATCHDOG_PERIOD * 2sec, periodically send */\n\t\tif (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _TRUE) {\n\t\t\tif ((ptdlsinfo->watchdog_count % TDLS_WATCHDOG_PERIOD) == 0) {\n\t\t\t\t_rtw_memcpy(txmgmt.peer, baddr, ETH_ALEN);\n\t\t\t\tissue_tdls_dis_req(padapter, &txmgmt);\n\t\t\t}\n\t\t\tptdlsinfo->watchdog_count++;\n\t\t}\n#endif /* CONFIG_TDLS_AUTOSETUP */\n#endif /* CONFIG_TDLS */\n\n#ifdef CONFIG_SUPPORT_STATIC_SMPS\n\t\t_ssmps_chk_by_tp(padapter, from_timer);\n#endif\n#ifdef CONFIG_CTRL_TXSS_BY_TP\n\t\trtw_ctrl_tx_ss_by_tp(padapter, from_timer);\n#endif\n\n#ifdef CONFIG_LPS\n\t\tif (adapter_to_pwrctl(padapter)->bLeisurePs && MLME_IS_STA(padapter)) {\n\t\t\t#ifdef CONFIG_LPS_CHK_BY_TP\n\t\t\tif (adapter_to_pwrctl(padapter)->lps_chk_by_tp)\n\t\t\t\tbEnterPS = _lps_chk_by_tp(padapter, from_timer);\n\t\t\telse\n\t\t\t#endif /*CONFIG_LPS_CHK_BY_TP*/\n\t\t\t\tbEnterPS = _lps_chk_by_pkt_cnts(padapter, from_timer, bBusyTraffic);\n\t\t}\n#endif /* CONFIG_LPS */\n\n\t} else {\n#ifdef CONFIG_LPS\n\t\tif (!from_timer && rtw_mi_get_assoc_if_num(padapter) == 0)\n\t\t\tLPS_Leave(padapter, \"NON_LINKED\");\n#endif\n\t}\n\n\tsession_tracker_chk_cmd(padapter, NULL);\n\n#ifdef CONFIG_BEAMFORMING\n#ifdef RTW_BEAMFORMING_VERSION_2\n\trtw_bf_update_traffic(padapter);\n#endif /* RTW_BEAMFORMING_VERSION_2 */\n#endif /* CONFIG_BEAMFORMING */\n\n\tpmlmepriv->LinkDetectInfo.NumRxOkInPeriod = 0;\n\tpmlmepriv->LinkDetectInfo.NumTxOkInPeriod = 0;\n\tpmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod = 0;\n\tpmlmepriv->LinkDetectInfo.bBusyTraffic = bBusyTraffic;\n\tpmlmepriv->LinkDetectInfo.bTxBusyTraffic = bTxBusyTraffic;\n\tpmlmepriv->LinkDetectInfo.bRxBusyTraffic = bRxBusyTraffic;\n\tpmlmepriv->LinkDetectInfo.bHigherBusyTraffic = bHigherBusyTraffic;\n\tpmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic = bHigherBusyRxTraffic;\n\tpmlmepriv->LinkDetectInfo.bHigherBusyTxTraffic = bHigherBusyTxTraffic;\n\n\treturn bEnterPS;\n\n}\n\n\n/* for 11n Logo 4.2.31/4.2.32 */\nstatic void dynamic_update_bcn_check(_adapter *padapter)\n{\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\n\tif (!padapter->registrypriv.wifi_spec)\n\t\treturn;\n\n\tif (!padapter->registrypriv.ht_enable || !is_supported_ht(padapter->registrypriv.wireless_mode))\n\t\treturn;\n\n\tif (!MLME_IS_AP(padapter))\n\t\treturn;\n\n\tif (pmlmeext->bstart_bss) {\n\t\t/* In 10 * 2 = 20s, there are no legacy AP, update HT info  */\n\t\tstatic u8 count = 1;\n\n\t\tif (count % 10 == 0) {\n\t\t\tcount = 1;\n#ifdef CONFIG_80211N_HT\n\t\t\tif (_FALSE == ATOMIC_READ(&pmlmepriv->olbc)\n\t\t\t\t&& _FALSE == ATOMIC_READ(&pmlmepriv->olbc_ht)) {\n\n\t\t\t\tif (rtw_ht_operation_update(padapter) > 0) {\n\t\t\t\t\tupdate_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0);\n\t\t\t\t\tupdate_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE, 0);\n\t\t\t\t}\n\t\t\t}\n#endif /* CONFIG_80211N_HT */\n\t\t}\n\n#ifdef CONFIG_80211N_HT\n\t\t/* In 2s, there are any legacy AP, update HT info, and then reset count  */\n\n\t\tif (_FALSE != ATOMIC_READ(&pmlmepriv->olbc)\n\t\t\t&& _FALSE != ATOMIC_READ(&pmlmepriv->olbc_ht)) {\n\t\t\t\t\t\n\t\t\tif (rtw_ht_operation_update(padapter) > 0) {\n\t\t\t\tupdate_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0);\n\t\t\t\tupdate_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE, 0);\n\n\t\t\t}\n\t\t\tATOMIC_SET(&pmlmepriv->olbc, _FALSE);\n\t\t\tATOMIC_SET(&pmlmepriv->olbc_ht, _FALSE);\n\t\t\tcount = 0;\n\t\t}\n#endif /* CONFIG_80211N_HT */\n\t\tcount ++;\n\t}\n}\nvoid rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter)\n{\n\t#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK\n\t#ifdef CONFIG_AP_MODE\n\tif (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {\n\t\texpire_timeout_chk(padapter);\n\t\t#ifdef CONFIG_RTW_MESH\n\t\tif (MLME_IS_MESH(padapter) && MLME_IS_ASOC(padapter))\n\t\t\trtw_mesh_peer_status_chk(padapter);\n\t\t#endif\n\t}\n\t#endif\n\t#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */\n\tdynamic_update_bcn_check(padapter);\n\n\tlinked_status_chk(padapter, 0);\n\ttraffic_status_watchdog(padapter, 0);\n\n\t/* for debug purpose */\n\t_linked_info_dump(padapter);\n\n#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR\n        rtw_cfgvendor_rssi_monitor_evt(padapter);\n#endif\n\n\n}\nvoid rtw_dynamic_chk_wk_hdl(_adapter *padapter)\n{\n\trtw_mi_dynamic_chk_wk_hdl(padapter);\n#ifdef CONFIG_MP_INCLUDED\n\tif (rtw_mp_mode_check(padapter) == _FALSE)\n#endif\n\t{\n#ifdef DBG_CONFIG_ERROR_DETECT\n\t\trtw_hal_sreset_xmit_status_check(padapter);\n\t\trtw_hal_sreset_linked_status_check(padapter);\n#endif\n\t}\n\n\t/* if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING|_FW_UNDER_SURVEY)==_FALSE) */\n\t{\n#ifdef DBG_RX_COUNTER_DUMP\n\t\trtw_dump_rx_counters(padapter);\n#endif\n\t\tdm_DynamicUsbTxAgg(padapter, 0);\n\t}\n\trtw_hal_dm_watchdog(padapter);\n\n\t/* check_hw_pbc(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type); */\n\n#ifdef CONFIG_BT_COEXIST\n\t/* BT-Coexist */\n\trtw_btcoex_Handler(padapter);\n#endif\n\n#ifdef CONFIG_IPS_CHECK_IN_WD\n\t/* always call rtw_ps_processor() at last one. */\n\trtw_ps_processor(padapter);\n#endif\n\n#ifdef CONFIG_MCC_MODE\n\trtw_hal_mcc_sw_status_check(padapter);\n#endif /* CONFIG_MCC_MODE */\n\n\trtw_hal_periodic_tsf_update_chk(padapter);\n}\n\n#ifdef CONFIG_LPS\nstruct lps_ctrl_wk_parm {\n\ts8 lps_level;\n\t#ifdef CONFIG_LPS_1T1R\n\ts8 lps_1t1r;\n\t#endif\n};\n\nvoid lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type, u8 *buf)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct lps_ctrl_wk_parm *parm = (struct lps_ctrl_wk_parm *)buf;\n\tu8\tmstatus;\n\n\tif ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)\n\t    || (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))\n\t\treturn;\n\n\tswitch (lps_ctrl_type) {\n\tcase LPS_CTRL_SCAN:\n\t\t/* RTW_INFO(\"LPS_CTRL_SCAN\\n\"); */\n#ifdef CONFIG_BT_COEXIST\n\t\trtw_btcoex_ScanNotify(padapter, _TRUE);\n#endif /* CONFIG_BT_COEXIST */\n\t\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {\n\t\t\t/* connect */\n\t\t\tLPS_Leave(padapter, \"LPS_CTRL_SCAN\");\n\t\t}\n\t\tbreak;\n\tcase LPS_CTRL_JOINBSS:\n\t\t/* RTW_INFO(\"LPS_CTRL_JOINBSS\\n\"); */\n\t\tLPS_Leave(padapter, \"LPS_CTRL_JOINBSS\");\n\t\tbreak;\n\tcase LPS_CTRL_CONNECT:\n\t\t/* RTW_INFO(\"LPS_CTRL_CONNECT\\n\"); */\n\t\tmstatus = 1;/* connect */\n\t\t/* Reset LPS Setting */\n\t\tpwrpriv->LpsIdleCount = 0;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus));\n#ifdef CONFIG_BT_COEXIST\n\t\trtw_btcoex_MediaStatusNotify(padapter, mstatus);\n#endif /* CONFIG_BT_COEXIST */\n\t\tbreak;\n\tcase LPS_CTRL_DISCONNECT:\n\t\t/* RTW_INFO(\"LPS_CTRL_DISCONNECT\\n\"); */\n\t\tmstatus = 0;/* disconnect */\n#ifdef CONFIG_BT_COEXIST\n\t\trtw_btcoex_MediaStatusNotify(padapter, mstatus);\n#endif /* CONFIG_BT_COEXIST */\n\t\tLPS_Leave(padapter, \"LPS_CTRL_DISCONNECT\");\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus));\n\t\tbreak;\n\tcase LPS_CTRL_SPECIAL_PACKET:\n\t\t/* RTW_INFO(\"LPS_CTRL_SPECIAL_PACKET\\n\"); */\n\t\trtw_set_lps_deny(padapter, LPS_DELAY_MS);\n#ifdef CONFIG_BT_COEXIST\n\t\trtw_btcoex_SpecialPacketNotify(padapter, PACKET_DHCP);\n#endif /* CONFIG_BT_COEXIST */\n\t\tLPS_Leave(padapter, \"LPS_CTRL_SPECIAL_PACKET\");\n\t\tbreak;\n\tcase LPS_CTRL_LEAVE:\n\t\tLPS_Leave(padapter, \"LPS_CTRL_LEAVE\");\n\t\tbreak;\n\tcase LPS_CTRL_LEAVE_SET_OPTION:\n\t\tLPS_Leave(padapter, \"LPS_CTRL_LEAVE_SET_OPTION\");\n\t\tif (parm) {\n\t\t\tif (parm->lps_level >= 0)\n\t\t\t\tpwrpriv->lps_level = parm->lps_level;\n\t\t\t#ifdef CONFIG_LPS_1T1R\n\t\t\tif (parm->lps_1t1r >= 0)\n\t\t\t\tpwrpriv->lps_1t1r = parm->lps_1t1r;\n\t\t\t#endif\n\t\t}\n\t\tbreak;\n\tcase LPS_CTRL_LEAVE_CFG80211_PWRMGMT:\n\t\tLPS_Leave(padapter, \"CFG80211_PWRMGMT\");\n\t\tbreak;\n\tcase LPS_CTRL_TRAFFIC_BUSY:\n\t\tLPS_Leave(padapter, \"LPS_CTRL_TRAFFIC_BUSY\");\n\t\tbreak;\n\tcase LPS_CTRL_TX_TRAFFIC_LEAVE:\n\t\tLPS_Leave(padapter, \"LPS_CTRL_TX_TRAFFIC_LEAVE\");\n\t\tbreak;\n\tcase LPS_CTRL_RX_TRAFFIC_LEAVE:\n\t\tLPS_Leave(padapter, \"LPS_CTRL_RX_TRAFFIC_LEAVE\");\n\t\tbreak;\n\tcase LPS_CTRL_ENTER:\n\t\tLPS_Enter(padapter, \"TRAFFIC_IDLE_1\");\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n}\n\nstatic u8 _rtw_lps_ctrl_wk_cmd(_adapter *adapter, u8 lps_ctrl_type, s8 lps_level, s8 lps_1t1r, u8 flags)\n{\n\tstruct cmd_obj *cmdobj;\n\tstruct drvextra_cmd_parm *parm;\n\tstruct lps_ctrl_wk_parm *wk_parm = NULL;\n\tstruct cmd_priv\t*pcmdpriv = &adapter->cmdpriv;\n\tstruct submit_ctx sctx;\n\tu8\tres = _SUCCESS;\n\n\tif (lps_ctrl_type == LPS_CTRL_LEAVE_SET_OPTION) {\n\t\twk_parm = rtw_zmalloc(sizeof(*wk_parm));\n\t\tif (wk_parm == NULL) {\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\t\twk_parm->lps_level = lps_level;\n\t\t#ifdef CONFIG_LPS_1T1R\n\t\twk_parm->lps_1t1r = lps_1t1r;\n\t\t#endif\n\t}\n\n\tif (flags & RTW_CMDF_DIRECTLY) {\n\t\t/* no need to enqueue, do the cmd hdl directly */\n\t\tlps_ctrl_wk_hdl(adapter, lps_ctrl_type, (u8 *)wk_parm);\n\t\tif (wk_parm)\n\t\t\trtw_mfree(wk_parm, sizeof(*wk_parm));\n\t} else {\n\t\t/* need enqueue, prepare cmd_obj and enqueue */\n\t\tparm = rtw_zmalloc(sizeof(*parm));\n\t\tif (parm == NULL) {\n\t\t\tif (wk_parm)\n\t\t\t\trtw_mfree(wk_parm, sizeof(*wk_parm));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tparm->ec_id = LPS_CTRL_WK_CID;\n\t\tparm->type = lps_ctrl_type;\n\t\tparm->size = wk_parm ? sizeof(*wk_parm) : 0;\n\t\tparm->pbuf = (u8 *)wk_parm;\n\n\t\tcmdobj = rtw_zmalloc(sizeof(*cmdobj));\n\t\tif (cmdobj == NULL) {\n\t\t\trtw_mfree(parm, sizeof(*parm));\n\t\t\tif (wk_parm)\n\t\t\t\trtw_mfree(wk_parm, sizeof(*wk_parm));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\t\tif (flags & RTW_CMDF_WAIT_ACK) {\n\t\t\tcmdobj->sctx = &sctx;\n\t\t\trtw_sctx_init(&sctx, 2000);\n\t\t}\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, cmdobj);\n\n\t\tif (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {\n\t\t\trtw_sctx_wait(&sctx, __func__);\n\t\t\t_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t\tif (sctx.status == RTW_SCTX_SUBMITTED)\n\t\t\t\tcmdobj->sctx = NULL;\n\t\t\t_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t\tif (sctx.status != RTW_SCTX_DONE_SUCCESS)\n\t\t\t\tres = _FAIL;\n\t\t}\n\t}\n\nexit:\n\treturn res;\n}\n\nu8 rtw_lps_ctrl_wk_cmd(_adapter *adapter, u8 lps_ctrl_type, u8 flags)\n{\n\treturn _rtw_lps_ctrl_wk_cmd(adapter, lps_ctrl_type, -1, -1, flags);\n}\n\nu8 rtw_lps_ctrl_leave_set_level_cmd(_adapter *adapter, u8 lps_level, u8 flags)\n{\n\treturn _rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_LEAVE_SET_OPTION, lps_level, -1, flags);\n}\n\n#ifdef CONFIG_LPS_1T1R\nu8 rtw_lps_ctrl_leave_set_1t1r_cmd(_adapter *adapter, u8 lps_1t1r, u8 flags)\n{\n\treturn _rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_LEAVE_SET_OPTION, -1, lps_1t1r, flags);\n}\n#endif\n\nvoid rtw_dm_in_lps_hdl(_adapter *padapter)\n{\n\trtw_hal_set_hwreg(padapter, HW_VAR_DM_IN_LPS_LCLK, NULL);\n}\n\nu8 rtw_dm_in_lps_wk_cmd(_adapter *padapter)\n{\n\tstruct cmd_obj\t*ph2c;\n\tstruct drvextra_cmd_parm\t*pdrvextra_cmd_parm;\n\tstruct cmd_priv\t*pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm->ec_id = DM_IN_LPS_WK_CID;\n\tpdrvextra_cmd_parm->type = 0;\n\tpdrvextra_cmd_parm->size = 0;\n\tpdrvextra_cmd_parm->pbuf = NULL;\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\n\treturn res;\n\n}\n\nvoid rtw_lps_change_dtim_hdl(_adapter *padapter, u8 dtim)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\n\tif (dtim <= 0 || dtim > 16)\n\t\treturn;\n\n#ifdef CONFIG_BT_COEXIST\n\tif (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)\n\t\treturn;\n#endif\n\n#ifdef CONFIG_LPS_LCLK\n\t_enter_pwrlock(&pwrpriv->lock);\n#endif\n\n\tif (pwrpriv->dtim != dtim) {\n\t\tRTW_INFO(\"change DTIM from %d to %d, bFwCurrentInPSMode=%d, ps_mode=%d\\n\", pwrpriv->dtim, dtim,\n\t\t\t pwrpriv->bFwCurrentInPSMode, pwrpriv->pwr_mode);\n\n\t\tpwrpriv->dtim = dtim;\n\t}\n\n\tif ((pwrpriv->bFwCurrentInPSMode == _TRUE) && (pwrpriv->pwr_mode > PS_MODE_ACTIVE)) {\n\t\tu8 ps_mode = pwrpriv->pwr_mode;\n\n\t\t/* RTW_INFO(\"change DTIM from %d to %d, ps_mode=%d\\n\", pwrpriv->dtim, dtim, ps_mode); */\n\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode));\n\t}\n\n#ifdef CONFIG_LPS_LCLK\n\t_exit_pwrlock(&pwrpriv->lock);\n#endif\n\n}\n\n#endif\n\nu8 rtw_lps_change_dtim_cmd(_adapter *padapter, u8 dtim)\n{\n\tstruct cmd_obj\t*ph2c;\n\tstruct drvextra_cmd_parm\t*pdrvextra_cmd_parm;\n\tstruct cmd_priv\t*pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\t/*\n\t#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (padapter->hw_port != HW_PORT0)\n\t\t\treturn res;\n\t#endif\n\t*/\n\t{\n\t\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\t\tif (ph2c == NULL) {\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\t\tif (pdrvextra_cmd_parm == NULL) {\n\t\t\trtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpdrvextra_cmd_parm->ec_id = LPS_CHANGE_DTIM_CID;\n\t\tpdrvextra_cmd_parm->type = dtim;\n\t\tpdrvextra_cmd_parm->size = 0;\n\t\tpdrvextra_cmd_parm->pbuf = NULL;\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\t}\n\nexit:\n\n\treturn res;\n\n}\n\n#if (RATE_ADAPTIVE_SUPPORT == 1)\nvoid rpt_timer_setting_wk_hdl(_adapter *padapter, u16 minRptTime)\n{\n\trtw_hal_set_hwreg(padapter, HW_VAR_RPT_TIMER_SETTING, (u8 *)(&minRptTime));\n}\n\nu8 rtw_rpt_timer_cfg_cmd(_adapter *padapter, u16 minRptTime)\n{\n\tstruct cmd_obj\t\t*ph2c;\n\tstruct drvextra_cmd_parm\t*pdrvextra_cmd_parm;\n\tstruct cmd_priv\t*pcmdpriv = &padapter->cmdpriv;\n\n\tu8\tres = _SUCCESS;\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm->ec_id = RTP_TIMER_CFG_WK_CID;\n\tpdrvextra_cmd_parm->type = minRptTime;\n\tpdrvextra_cmd_parm->size = 0;\n\tpdrvextra_cmd_parm->pbuf = NULL;\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\nexit:\n\n\n\treturn res;\n\n}\n\n#endif\n\n#ifdef CONFIG_ANTENNA_DIVERSITY\nvoid antenna_select_wk_hdl(_adapter *padapter, u8 antenna)\n{\n\trtw_hal_set_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &antenna, _TRUE);\n}\n\nu8 rtw_antenna_select_cmd(_adapter *padapter, u8 antenna, u8 enqueue)\n{\n\tstruct cmd_obj\t\t*ph2c;\n\tstruct drvextra_cmd_parm\t*pdrvextra_cmd_parm;\n\tstruct cmd_priv\t*pcmdpriv = &padapter->cmdpriv;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tu8\tbSupportAntDiv = _FALSE;\n\tu8\tres = _SUCCESS;\n\tint\ti;\n\n\trtw_hal_get_def_var(padapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv));\n\tif (_FALSE == bSupportAntDiv)\n\t\treturn _FAIL;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tif (rtw_linked_check(dvobj->padapters[i]))\n\t\t\treturn _FAIL;\n\t}\n\n\tif (_TRUE == enqueue) {\n\t\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\t\tif (ph2c == NULL) {\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\t\tif (pdrvextra_cmd_parm == NULL) {\n\t\t\trtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpdrvextra_cmd_parm->ec_id = ANT_SELECT_WK_CID;\n\t\tpdrvextra_cmd_parm->type = antenna;\n\t\tpdrvextra_cmd_parm->size = 0;\n\t\tpdrvextra_cmd_parm->pbuf = NULL;\n\t\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\t} else\n\t\tantenna_select_wk_hdl(padapter, antenna);\nexit:\n\n\n\treturn res;\n\n}\n#endif\n\nvoid rtw_dm_ra_mask_hdl(_adapter *padapter, struct sta_info *psta)\n{\n\tif (psta)\n\t\tset_sta_rate(padapter, psta);\n}\n\nu8 rtw_dm_ra_mask_wk_cmd(_adapter *padapter, u8 *psta)\n{\n\tstruct cmd_obj\t*ph2c;\n\tstruct drvextra_cmd_parm\t*pdrvextra_cmd_parm;\n\tstruct cmd_priv\t*pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm->ec_id = DM_RA_MSK_WK_CID;\n\tpdrvextra_cmd_parm->type = 0;\n\tpdrvextra_cmd_parm->size = 0;\n\tpdrvextra_cmd_parm->pbuf = psta;\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\n\treturn res;\n\n}\n\nvoid power_saving_wk_hdl(_adapter *padapter)\n{\n\trtw_ps_processor(padapter);\n}\n\n/* add for CONFIG_IEEE80211W, none 11w can use it */\nvoid reset_securitypriv_hdl(_adapter *padapter)\n{\n\trtw_reset_securitypriv(padapter);\n}\n\n#ifdef CONFIG_P2P\nu8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType)\n{\n\tstruct cmd_obj\t*ph2c;\n\tstruct drvextra_cmd_parm\t*pdrvextra_cmd_parm;\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\tstruct cmd_priv\t*pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))\n\t\treturn res;\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm->ec_id = P2P_PROTO_WK_CID;\n\tpdrvextra_cmd_parm->type = intCmdType;\t/*\tAs the command tppe. */\n\tpdrvextra_cmd_parm->size = 0;\n\tpdrvextra_cmd_parm->pbuf = NULL;\t\t/*\tMust be NULL here */\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\n\n\treturn res;\n\n}\n\n#ifdef CONFIG_IOCTL_CFG80211\nstatic u8 _p2p_roch_cmd(_adapter *adapter\n\t, u64 cookie, struct wireless_dev *wdev\n\t, struct ieee80211_channel *ch, enum nl80211_channel_type ch_type\n\t, unsigned int duration\n\t, u8 flags\n)\n{\n\tstruct cmd_obj *cmdobj;\n\tstruct drvextra_cmd_parm *parm;\n\tstruct p2p_roch_parm *roch_parm;\n\tstruct cmd_priv *pcmdpriv = &adapter->cmdpriv;\n\tstruct submit_ctx sctx;\n\tu8 cancel = duration ? 0 : 1;\n\tu8\tres = _SUCCESS;\n\n\troch_parm = (struct p2p_roch_parm *)rtw_zmalloc(sizeof(struct p2p_roch_parm));\n\tif (roch_parm == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\troch_parm->cookie = cookie;\n\troch_parm->wdev = wdev;\n\tif (!cancel) {\n\t\t_rtw_memcpy(&roch_parm->ch, ch, sizeof(struct ieee80211_channel));\n\t\troch_parm->ch_type = ch_type;\n\t\troch_parm->duration = duration;\n\t}\n\n\tif (flags & RTW_CMDF_DIRECTLY) {\n\t\t/* no need to enqueue, do the cmd hdl directly and free cmd parameter */\n\t\tif (H2C_SUCCESS != p2p_protocol_wk_hdl(adapter, cancel ? P2P_CANCEL_RO_CH_WK : P2P_RO_CH_WK, (u8 *)roch_parm))\n\t\t\tres = _FAIL;\n\t\trtw_mfree((u8 *)roch_parm, sizeof(*roch_parm));\n\t} else {\n\t\t/* need enqueue, prepare cmd_obj and enqueue */\n\t\tparm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\t\tif (parm == NULL) {\n\t\t\trtw_mfree((u8 *)roch_parm, sizeof(*roch_parm));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tparm->ec_id = P2P_PROTO_WK_CID;\n\t\tparm->type = cancel ? P2P_CANCEL_RO_CH_WK : P2P_RO_CH_WK;\n\t\tparm->size = sizeof(*roch_parm);\n\t\tparm->pbuf = (u8 *)roch_parm;\n\n\t\tcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));\n\t\tif (cmdobj == NULL) {\n\t\t\tres = _FAIL;\n\t\t\trtw_mfree((u8 *)roch_parm, sizeof(*roch_parm));\n\t\t\trtw_mfree((u8 *)parm, sizeof(*parm));\n\t\t\tgoto exit;\n\t\t}\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\t\tif (flags & RTW_CMDF_WAIT_ACK) {\n\t\t\tcmdobj->sctx = &sctx;\n\t\t\trtw_sctx_init(&sctx, 10 * 1000);\n\t\t}\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, cmdobj);\n\n\t\tif (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {\n\t\t\trtw_sctx_wait(&sctx, __func__);\n\t\t\t_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t\tif (sctx.status == RTW_SCTX_SUBMITTED)\n\t\t\t\tcmdobj->sctx = NULL;\n\t\t\t_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t\tif (sctx.status != RTW_SCTX_DONE_SUCCESS)\n\t\t\t\tres = _FAIL;\n\t\t}\n\t}\n\nexit:\n\treturn res;\n}\n\ninline u8 p2p_roch_cmd(_adapter *adapter\n\t, u64 cookie, struct wireless_dev *wdev\n\t, struct ieee80211_channel *ch, enum nl80211_channel_type ch_type\n\t, unsigned int duration\n\t, u8 flags\n)\n{\n\treturn _p2p_roch_cmd(adapter, cookie, wdev, ch, ch_type, duration, flags);\n}\n\ninline u8 p2p_cancel_roch_cmd(_adapter *adapter, u64 cookie, struct wireless_dev *wdev, u8 flags)\n{\n\treturn _p2p_roch_cmd(adapter, cookie, wdev, NULL, 0, 0, flags);\n}\n\n#endif /* CONFIG_IOCTL_CFG80211 */\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_IOCTL_CFG80211 \ninline u8 rtw_mgnt_tx_cmd(_adapter *adapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack, u8 flags)\n{\n\tstruct cmd_obj *cmdobj;\n\tstruct drvextra_cmd_parm *parm;\n\tstruct mgnt_tx_parm *mgnt_parm;\n\tstruct cmd_priv *pcmdpriv = &adapter->cmdpriv;\n\tstruct submit_ctx sctx;\n\tu8\tres = _SUCCESS;\n\n\tmgnt_parm = (struct mgnt_tx_parm *)rtw_zmalloc(sizeof(struct mgnt_tx_parm));\n\tif (mgnt_parm == NULL) {\n\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t}\n\n\tmgnt_parm->tx_ch = tx_ch;\n\tmgnt_parm->no_cck = no_cck;\n\tmgnt_parm->buf = buf;\n\tmgnt_parm->len = len;\n\tmgnt_parm->wait_ack = wait_ack;\n\n\tif (flags & RTW_CMDF_DIRECTLY) {\n\t\t/* no need to enqueue, do the cmd hdl directly and free cmd parameter */\n\t\tif (H2C_SUCCESS != rtw_mgnt_tx_handler(adapter, (u8 *)mgnt_parm))\n\t\t\tres = _FAIL;\n\t\trtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm));\n\t} else {\n\t\t/* need enqueue, prepare cmd_obj and enqueue */\n\t\tparm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\t\tif (parm == NULL) {\n\t\t\trtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tparm->ec_id = MGNT_TX_WK_CID;\n\t\tparm->type = 0;\n\t\tparm->size = sizeof(*mgnt_parm);\n\t\tparm->pbuf = (u8 *)mgnt_parm;\n\n\t\tcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));\n\t\tif (cmdobj == NULL) {\n\t\t\tres = _FAIL;\n\t\t\trtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm));\n\t\t\trtw_mfree((u8 *)parm, sizeof(*parm));\n\t\t\tgoto exit;\n\t\t}\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\t\tif (flags & RTW_CMDF_WAIT_ACK) {\n\t\t\tcmdobj->sctx = &sctx;\n\t\t\trtw_sctx_init(&sctx, 10 * 1000);\n\t\t}\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, cmdobj);\n\n\t\tif (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {\n\t\t\trtw_sctx_wait(&sctx, __func__);\n\t\t\t_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t\tif (sctx.status == RTW_SCTX_SUBMITTED)\n\t\t\t\tcmdobj->sctx = NULL;\n\t\t\t_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t\tif (sctx.status != RTW_SCTX_DONE_SUCCESS)\n\t\t\t\tres = _FAIL;\n\t\t}\n\t}\n\nexit:\n\treturn res;\n}\n#endif\n\nu8 rtw_ps_cmd(_adapter *padapter)\n{\n\tstruct cmd_obj\t\t*ppscmd;\n\tstruct drvextra_cmd_parm\t*pdrvextra_cmd_parm;\n\tstruct cmd_priv\t*pcmdpriv = &padapter->cmdpriv;\n\n\tu8\tres = _SUCCESS;\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (!is_primary_adapter(padapter))\n\t\tgoto exit;\n#endif\n\n\tppscmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ppscmd == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((unsigned char *)ppscmd, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm->ec_id = POWER_SAVING_CTRL_WK_CID;\n\tpdrvextra_cmd_parm->type = 0;\n\tpdrvextra_cmd_parm->size = 0;\n\tpdrvextra_cmd_parm->pbuf = NULL;\n\tinit_h2fwcmd_w_parm_no_rsp(ppscmd, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ppscmd);\n\nexit:\n\n\n\treturn res;\n\n}\n\n#ifdef CONFIG_DFS\nvoid rtw_dfs_ch_switch_hdl(struct dvobj_priv *dvobj)\n{\n\tstruct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);\n\t_adapter *pri_adapter = dvobj_get_primary_adapter(dvobj);\n\tu8 ifbmp_m = rtw_mi_get_ap_mesh_ifbmp(pri_adapter);\n\tu8 ifbmp_s = rtw_mi_get_ld_sta_ifbmp(pri_adapter);\n\ts16 req_ch;\n\n\trtw_hal_macid_sleep_all_used(pri_adapter);\n\n\tif (rtw_chset_search_ch(rfctl->channel_set, rfctl->csa_ch) >= 0\n\t\t&& !rtw_chset_is_ch_non_ocp(rfctl->channel_set, rfctl->csa_ch)\n\t) {\n\t\t/* CSA channel available and valid */\n\t\treq_ch = rfctl->csa_ch;\n\t\tRTW_INFO(\"%s valid CSA ch%u\\n\", __func__, rfctl->csa_ch);\n\t} else if (ifbmp_m) {\n\t\t/* no available or valid CSA channel, having AP/MESH ifaces */\n\t\treq_ch = REQ_CH_NONE;\n\t\tRTW_INFO(\"%s ch sel by AP/MESH ifaces\\n\", __func__);\n\t} else {\n\t\t/* no available or valid CSA channel and no AP/MESH ifaces */\n\t\tif (!IsSupported24G(dvobj_to_regsty(dvobj)->wireless_mode)\n\t\t\t#ifdef CONFIG_DFS_MASTER\n\t\t\t|| rfctl->radar_detected\n\t\t\t#endif\n\t\t)\n\t\t\treq_ch = 36;\n\t\telse\n\t\t\treq_ch = 1;\n\t\tRTW_INFO(\"%s switch to ch%d\\n\", __func__, req_ch);\n\t}\n\n\t/*  issue deauth for all asoc STA ifaces */\n\tif (ifbmp_s) {\n\t\t_adapter *iface;\n\t\tint i;\n\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tif (!iface || !(ifbmp_s & BIT(iface->iface_id)))\n\t\t\t\tcontinue;\n\t\t\tset_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING);\n\n\t\t\t/* TODO: true op ch switching */\n\t\t\tissue_deauth(iface, get_bssid(&iface->mlmepriv), WLAN_REASON_DEAUTH_LEAVING);\n\t\t}\n\t}\n\n#ifdef CONFIG_AP_MODE\n\tif (ifbmp_m) {\n\t\t/* trigger channel selection without consideraton of asoc STA ifaces */\n\t\trtw_change_bss_chbw_cmd(dvobj_get_primary_adapter(dvobj), RTW_CMDF_DIRECTLY\n\t\t\t, ifbmp_m, ifbmp_s, req_ch, REQ_BW_ORI, REQ_OFFSET_NONE);\n\t} else\n#endif\n\t{\n\t\t/* no AP/MESH iface, switch DFS status and channel directly */\n\t\trtw_warn_on(req_ch <= 0);\n\t\t#ifdef CONFIG_DFS_MASTER\n\t\trtw_dfs_rd_en_decision(pri_adapter, MLME_OPCH_SWITCH, ifbmp_s);\n\t\t#endif\n\t\tset_channel_bwmode(pri_adapter, req_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n\t}\n\n\t/* make asoc STA ifaces disconnect */\n\t/* TODO: true op ch switching */\n\tif (ifbmp_s) {\n\t\t_adapter *iface;\n\t\tint i;\n\t\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tif (!iface || !(ifbmp_s & BIT(iface->iface_id)))\n\t\t\t\tcontinue;\n\t\t\trtw_disassoc_cmd(iface, 0, RTW_CMDF_DIRECTLY);\n\t\t\trtw_indicate_disconnect(iface, 0, _FALSE);\n\t\t\trtw_free_assoc_resources(iface, _TRUE);\n\t\t\trtw_free_network_queue(iface, _TRUE);\n\t\t}\n\t}\n\n\trfctl->csa_ch = 0;\n\n\trtw_hal_macid_wakeup_all_used(pri_adapter);\n\trtw_mi_os_xmit_schedule(pri_adapter);\n}\n#endif /* CONFIG_DFS */\n\n#ifdef CONFIG_AP_MODE\n\nstatic void rtw_chk_hi_queue_hdl(_adapter *padapter)\n{\n\tstruct sta_info *psta_bmc;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tsystime start = rtw_get_current_time();\n\tu8 empty = _FALSE;\n\n\tpsta_bmc = rtw_get_bcmc_stainfo(padapter);\n\tif (!psta_bmc)\n\t\treturn;\n\n\trtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty);\n\n\twhile (_FALSE == empty && rtw_get_passing_time_ms(start) < rtw_get_wait_hiq_empty_ms()) {\n\t\trtw_msleep_os(100);\n\t\trtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty);\n\t}\n\n\tif (psta_bmc->sleepq_len == 0) {\n\t\tif (empty == _SUCCESS) {\n\t\t\tbool update_tim = _FALSE;\n\n\t\t\tif (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0))\n\t\t\t\tupdate_tim = _TRUE;\n\n\t\t\trtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0);\n\t\t\trtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0);\n\n\t\t\tif (update_tim == _TRUE)\n\t\t\t\t_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0,\"bmc sleepq and HIQ empty\");\n\t\t} else /* re check again */\n\t\t\trtw_chk_hi_queue_cmd(padapter);\n\n\t}\n\n}\n\nu8 rtw_chk_hi_queue_cmd(_adapter *padapter)\n{\n\tstruct cmd_obj\t*ph2c;\n\tstruct drvextra_cmd_parm\t*pdrvextra_cmd_parm;\n\tstruct cmd_priv\t*pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm->ec_id = CHECK_HIQ_WK_CID;\n\tpdrvextra_cmd_parm->type = 0;\n\tpdrvextra_cmd_parm->size = 0;\n\tpdrvextra_cmd_parm->pbuf = NULL;\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\n\treturn res;\n\n}\n\n#ifdef CONFIG_DFS_MASTER\nu8 rtw_dfs_rd_hdl(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\n\tif (!rfctl->radar_detect_enabled)\n\t\tgoto exit;\n\n\tif (dvobj->oper_channel != rfctl->radar_detect_ch\n\t\t|| rtw_get_passing_time_ms(rtw_get_on_oper_ch_time(adapter)) < 300\n\t) {\n\t\t/* offchannel, bypass radar detect */\n\t\tgoto cac_status_chk;\n\t}\n\n\tif (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl)) {\n\t\t/* non_ocp, bypass radar detect */\n\t\tgoto cac_status_chk;\n\t}\n\n\tif (!rfctl->dbg_dfs_fake_radar_detect_cnt\n\t\t&& rtw_odm_radar_detect(adapter) != _TRUE)\n\t\tgoto cac_status_chk;\n\n\tif (!rfctl->dbg_dfs_fake_radar_detect_cnt\n\t\t&& rfctl->dbg_dfs_radar_detect_trigger_non\n\t) {\n\t\t/* radar detect debug mode, trigger no mlme flow */\n\t\tRTW_INFO(\"%s radar detected on test mode, trigger no mlme flow\\n\", __func__);\n\t\tgoto cac_status_chk;\n\t}\n\n\tif (rfctl->dbg_dfs_fake_radar_detect_cnt != 0) {\n\t\tRTW_INFO(\"%s fake radar detected, cnt:%d\\n\", __func__\n\t\t\t, rfctl->dbg_dfs_fake_radar_detect_cnt);\n\t\trfctl->dbg_dfs_fake_radar_detect_cnt--;\n\t} else\n\t\tRTW_INFO(\"%s radar detected\\n\", __func__);\n\n\trfctl->radar_detected = 1;\n\n\trtw_chset_update_non_ocp(rfctl->channel_set\n\t\t, rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset);\n\n\trtw_dfs_ch_switch_hdl(dvobj);\n\n\tif (rfctl->radar_detect_enabled)\n\t\tgoto set_timer;\n\tgoto exit;\n\ncac_status_chk:\n\n\tif (!IS_CAC_STOPPED(rfctl)\n\t\t&& ((IS_UNDER_CAC(rfctl) && rfctl->cac_force_stop)\n\t\t\t|| !IS_CH_WAITING(rfctl)\n\t\t\t)\n\t) {\n\t\tu8 pause = 0x00;\n\n\t\trtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause);\n\t\trfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;\n\n\t\tif (rtw_mi_check_fwstate(adapter, WIFI_UNDER_LINKING|WIFI_SITE_MONITOR) == _FALSE) {\n\t\t\tu8 doiqk = _TRUE;\n\t\t\tu8 u_ch, u_bw, u_offset;\n\n\t\t\trtw_hal_set_hwreg(adapter , HW_VAR_DO_IQK , &doiqk);\n\n\t\t\tif (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset))\n\t\t\t\tset_channel_bwmode(adapter, u_ch, u_offset, u_bw);\n\t\t\telse\n\t\t\t\trtw_warn_on(1);\n\n\t\t\tdoiqk = _FALSE;\n\t\t\trtw_hal_set_hwreg(adapter , HW_VAR_DO_IQK , &doiqk);\n\n\t\t\tResumeTxBeacon(adapter);\n\t\t\trtw_mi_tx_beacon_hdl(adapter);\n\t\t}\n\t}\n\nset_timer:\n\t_set_timer(&rfctl->radar_detect_timer\n\t\t, rtw_odm_radar_detect_polling_int_ms(dvobj));\n\nexit:\n\treturn H2C_SUCCESS;\n}\n\nu8 rtw_dfs_rd_cmd(_adapter *adapter, bool enqueue)\n{\n\tstruct cmd_obj *cmdobj;\n\tstruct drvextra_cmd_parm *parm;\n\tstruct cmd_priv *cmdpriv = &adapter->cmdpriv;\n\tu8 res = _FAIL;\n\n\tif (enqueue) {\n\t\tcmdobj = rtw_zmalloc(sizeof(struct cmd_obj));\n\t\tif (cmdobj == NULL)\n\t\t\tgoto exit;\n\n\t\tparm = rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\t\tif (parm == NULL) {\n\t\t\trtw_mfree(cmdobj, sizeof(struct cmd_obj));\n\t\t\tgoto exit;\n\t\t}\n\n\t\tparm->ec_id = DFS_RADAR_DETECT_WK_CID;\n\t\tparm->type = 0;\n\t\tparm->size = 0;\n\t\tparm->pbuf = NULL;\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\t\tres = rtw_enqueue_cmd(cmdpriv, cmdobj);\n\t} else {\n\t\trtw_dfs_rd_hdl(adapter);\n\t\tres = _SUCCESS;\n\t}\n\nexit:\n\treturn res;\n}\n\nvoid rtw_dfs_rd_timer_hdl(void *ctx)\n{\n\tstruct rf_ctl_t *rfctl = (struct rf_ctl_t *)ctx;\n\tstruct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);\n\n\trtw_dfs_rd_cmd(dvobj_get_primary_adapter(dvobj), _TRUE);\n}\n\nstatic void rtw_dfs_rd_enable(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool bypass_cac)\n{\n\tstruct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);\n\t_adapter *adapter = dvobj_get_primary_adapter(dvobj);\n\n\tRTW_INFO(\"%s on %u,%u,%u\\n\", __func__, ch, bw, offset);\n\n\tif (bypass_cac)\n\t\trfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;\n\telse if (rtw_is_cac_reset_needed(rfctl, ch, bw, offset) == _TRUE)\n\t\trtw_reset_cac(rfctl, ch, bw, offset);\n\n\trfctl->radar_detect_by_others = _FALSE;\n\trfctl->radar_detect_ch = ch;\n\trfctl->radar_detect_bw = bw;\n\trfctl->radar_detect_offset = offset;\n\n\trfctl->radar_detected = 0;\n\n\tif (IS_CH_WAITING(rfctl))\n\t\tStopTxBeacon(adapter);\n\n\tif (!rfctl->radar_detect_enabled) {\n\t\tRTW_INFO(\"%s set radar_detect_enabled\\n\", __func__);\n\t\trfctl->radar_detect_enabled = 1;\n\t\t#ifdef CONFIG_LPS\n\t\tLPS_Leave(adapter, \"RADAR_DETECT_EN\");\n\t\t#endif\n\t\t_set_timer(&rfctl->radar_detect_timer\n\t\t\t, rtw_odm_radar_detect_polling_int_ms(dvobj));\n\n\t\tif (rtw_rfctl_overlap_radar_detect_ch(rfctl)) {\n\t\t\tif (IS_CH_WAITING(rfctl)) {\n\t\t\t\tu8 pause = 0xFF;\n\n\t\t\t\trtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause);\n\t\t\t}\n\t\t\trtw_odm_radar_detect_enable(adapter);\n\t\t}\n\t}\n}\n\nstatic void rtw_dfs_rd_disable(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool by_others)\n{\n\t_adapter *adapter = dvobj_get_primary_adapter(rfctl_to_dvobj(rfctl));\n\n\trfctl->radar_detect_by_others = by_others;\n\n\tif (rfctl->radar_detect_enabled) {\n\t\tbool overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl);\n\n\t\tRTW_INFO(\"%s clear radar_detect_enabled\\n\", __func__);\n\n\t\trfctl->radar_detect_enabled = 0;\n\t\trfctl->radar_detected = 0;\n\t\trfctl->radar_detect_ch = 0;\n\t\trfctl->radar_detect_bw = 0;\n\t\trfctl->radar_detect_offset = 0;\n\t\trfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;\n\t\t_cancel_timer_ex(&rfctl->radar_detect_timer);\n\n\t\tif (rtw_mi_check_fwstate(adapter, WIFI_UNDER_LINKING|WIFI_SITE_MONITOR) == _FALSE) {\n\t\t\tResumeTxBeacon(adapter);\n\t\t\trtw_mi_tx_beacon_hdl(adapter);\n\t\t}\n\n\t\tif (overlap_radar_detect_ch) {\n\t\t\tu8 pause = 0x00;\n\n\t\t\trtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause);\n\t\t\trtw_odm_radar_detect_disable(adapter);\n\t\t}\n\t}\n\n\tif (by_others) {\n\t\trfctl->radar_detect_ch = ch;\n\t\trfctl->radar_detect_bw = bw;\n\t\trfctl->radar_detect_offset = offset;\n\t}\n}\n\nvoid rtw_dfs_rd_en_decision(_adapter *adapter, u8 mlme_act, u8 excl_ifbmp)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\tstruct mi_state mstate;\n\tu8 ifbmp;\n\tu8 u_ch, u_bw, u_offset;\n\tbool ld_sta_in_dfs = _FALSE;\n\tbool sync_ch = _FALSE; /* _FALSE: asign channel directly */\n\tbool needed = _FALSE;\n\n\tif (mlme_act == MLME_OPCH_SWITCH\n\t\t|| mlme_act == MLME_ACTION_NONE\n\t) {\n\t\tifbmp = ~excl_ifbmp;\n\t\trtw_mi_status_by_ifbmp(dvobj, ifbmp, &mstate);\n\t\trtw_mi_get_ch_setting_union_by_ifbmp(dvobj, ifbmp, &u_ch, &u_bw, &u_offset);\n\t} else {\n\t\tifbmp = ~excl_ifbmp & ~BIT(adapter->iface_id);\n\t\trtw_mi_status_by_ifbmp(dvobj, ifbmp, &mstate);\n\t\trtw_mi_get_ch_setting_union_by_ifbmp(dvobj, ifbmp, &u_ch, &u_bw, &u_offset);\n\t\tif (u_ch != 0)\n\t\t\tsync_ch = _TRUE;\n\n\t\tswitch (mlme_act) {\n\t\tcase MLME_STA_CONNECTING:\n\t\t\tMSTATE_STA_LG_NUM(&mstate)++;\n\t\t\tbreak;\n\t\tcase MLME_STA_CONNECTED:\n\t\t\tMSTATE_STA_LD_NUM(&mstate)++;\n\t\t\tbreak;\n\t\tcase MLME_STA_DISCONNECTED:\n\t\t\tbreak;\n#ifdef CONFIG_AP_MODE\n\t\tcase MLME_AP_STARTED:\n\t\t\tMSTATE_AP_NUM(&mstate)++;\n\t\t\tbreak;\n\t\tcase MLME_AP_STOPPED:\n\t\t\tbreak;\n#endif\n#ifdef CONFIG_RTW_MESH\n\t\tcase MLME_MESH_STARTED:\n\t\t\tMSTATE_MESH_NUM(&mstate)++;\n\t\t\tbreak;\n\t\tcase MLME_MESH_STOPPED:\n\t\t\tbreak;\n#endif\n\t\tdefault:\n\t\t\trtw_warn_on(1);\n\t\t\tbreak;\n\t\t}\n\n\t\tif (sync_ch == _TRUE) {\n\t\t\tif (!MLME_IS_OPCH_SW(adapter)) {\n\t\t\t\tif (!rtw_is_chbw_grouped(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset, u_ch, u_bw, u_offset)) {\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" can't sync %u,%u,%u with %u,%u,%u\\n\", FUNC_ADPT_ARG(adapter)\n\t\t\t\t\t\t, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset, u_ch, u_bw, u_offset);\n\t\t\t\t\tgoto apply;\n\t\t\t\t}\n\n\t\t\t\trtw_sync_chbw(&mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset\n\t\t\t\t\t, &u_ch, &u_bw, &u_offset);\n\t\t\t}\n\t\t} else {\n\t\t\tu_ch = mlmeext->cur_channel;\n\t\t\tu_bw = mlmeext->cur_bwmode;\n\t\t\tu_offset = mlmeext->cur_ch_offset;\n\t\t}\n\t}\n\n\tif (MSTATE_STA_LG_NUM(&mstate) > 0) {\n\t\t/* STA mode is linking */\n\t\tgoto apply;\n\t}\n\n\tif (MSTATE_STA_LD_NUM(&mstate) > 0) {\n\t\tif (rtw_is_dfs_chbw(u_ch, u_bw, u_offset)) {\n\t\t\t/*\n\t\t\t* if operate as slave w/o radar detect,\n\t\t\t* rely on AP on which STA mode connects\n\t\t\t*/\n\t\t\tif (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_odm_dfs_domain_unknown(dvobj))\n\t\t\t\tneeded = _TRUE;\n\t\t\tld_sta_in_dfs = _TRUE;\n\t\t}\n\t\tgoto apply;\n\t}\n\n\tif (!MSTATE_AP_NUM(&mstate) && !MSTATE_MESH_NUM(&mstate)) {\n\t\t/* No working AP/Mesh mode */\n\t\tgoto apply;\n\t}\n\n\tif (rtw_is_dfs_chbw(u_ch, u_bw, u_offset))\n\t\tneeded = _TRUE;\n\napply:\n\n\tRTW_INFO(FUNC_ADPT_FMT\" needed:%d, mlme_act:%u, excl_ifbmp:0x%02x\\n\"\n\t\t, FUNC_ADPT_ARG(adapter), needed, mlme_act, excl_ifbmp);\n\tRTW_INFO(FUNC_ADPT_FMT\" ld_sta_num:%u, lg_sta_num:%u, ap_num:%u, mesh_num:%u, %u,%u,%u\\n\"\n\t\t, FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_STA_LG_NUM(&mstate)\n\t\t, MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate)\n\t\t, u_ch, u_bw, u_offset);\n\n\tif (needed == _TRUE)\n\t\trtw_dfs_rd_enable(rfctl, u_ch, u_bw, u_offset, ld_sta_in_dfs);\n\telse\n\t\trtw_dfs_rd_disable(rfctl, u_ch, u_bw, u_offset, ld_sta_in_dfs);\n}\n\nu8 rtw_dfs_rd_en_decision_cmd(_adapter *adapter)\n{\n\tstruct cmd_obj *cmdobj;\n\tstruct drvextra_cmd_parm *parm;\n\tstruct cmd_priv *cmdpriv = &adapter->cmdpriv;\n\tu8 res = _FAIL;\n\n\tcmdobj = rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (cmdobj == NULL)\n\t\tgoto exit;\n\n\tparm = rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (parm == NULL) {\n\t\trtw_mfree(cmdobj, sizeof(struct cmd_obj));\n\t\tgoto exit;\n\t}\n\n\tparm->ec_id = DFS_RADAR_DETECT_EN_DEC_WK_CID;\n\tparm->type = 0;\n\tparm->size = 0;\n\tparm->pbuf = NULL;\n\n\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\tres = rtw_enqueue_cmd(cmdpriv, cmdobj);\n\nexit:\n\treturn res;\n}\n#endif /* CONFIG_DFS_MASTER */\n\n#endif /* CONFIG_AP_MODE */\n\n#ifdef CONFIG_BT_COEXIST\nstruct btinfo {\n\tu8 cid;\n\tu8 len;\n\n\tu8 bConnection:1;\n\tu8 bSCOeSCO:1;\n\tu8 bInQPage:1;\n\tu8 bACLBusy:1;\n\tu8 bSCOBusy:1;\n\tu8 bHID:1;\n\tu8 bA2DP:1;\n\tu8 bFTP:1;\n\n\tu8 retry_cnt:4;\n\tu8 rsvd_34:1;\n\tu8 rsvd_35:1;\n\tu8 rsvd_36:1;\n\tu8 rsvd_37:1;\n\n\tu8 rssi;\n\n\tu8 rsvd_50:1;\n\tu8 rsvd_51:1;\n\tu8 rsvd_52:1;\n\tu8 rsvd_53:1;\n\tu8 rsvd_54:1;\n\tu8 rsvd_55:1;\n\tu8 eSCO_SCO:1;\n\tu8 Master_Slave:1;\n\n\tu8 rsvd_6;\n\tu8 rsvd_7;\n};\n\nvoid btinfo_evt_dump(void *sel, void *buf)\n{\n\tstruct btinfo *info = (struct btinfo *)buf;\n\n\tRTW_PRINT_SEL(sel, \"cid:0x%02x, len:%u\\n\", info->cid, info->len);\n\n\tif (info->len > 2)\n\t\tRTW_PRINT_SEL(sel, \"byte2:%s%s%s%s%s%s%s%s\\n\"\n\t\t\t      , info->bConnection ? \"bConnection \" : \"\"\n\t\t\t      , info->bSCOeSCO ? \"bSCOeSCO \" : \"\"\n\t\t\t      , info->bInQPage ? \"bInQPage \" : \"\"\n\t\t\t      , info->bACLBusy ? \"bACLBusy \" : \"\"\n\t\t\t      , info->bSCOBusy ? \"bSCOBusy \" : \"\"\n\t\t\t      , info->bHID ? \"bHID \" : \"\"\n\t\t\t      , info->bA2DP ? \"bA2DP \" : \"\"\n\t\t\t      , info->bFTP ? \"bFTP\" : \"\"\n\t\t\t     );\n\n\tif (info->len > 3)\n\t\tRTW_PRINT_SEL(sel, \"retry_cnt:%u\\n\", info->retry_cnt);\n\n\tif (info->len > 4)\n\t\tRTW_PRINT_SEL(sel, \"rssi:%u\\n\", info->rssi);\n\n\tif (info->len > 5)\n\t\tRTW_PRINT_SEL(sel, \"byte5:%s%s\\n\"\n\t\t\t      , info->eSCO_SCO ? \"eSCO_SCO \" : \"\"\n\t\t\t      , info->Master_Slave ? \"Master_Slave \" : \"\"\n\t\t\t     );\n}\n\nstatic void rtw_btinfo_hdl(_adapter *adapter, u8 *buf, u16 buf_len)\n{\n#define BTINFO_WIFI_FETCH 0x23\n#define BTINFO_BT_AUTO_RPT 0x27\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\tstruct btinfo_8761ATV *info = (struct btinfo_8761ATV *)buf;\n#else /* !CONFIG_BT_COEXIST_SOCKET_TRX */\n\tstruct btinfo *info = (struct btinfo *)buf;\n#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */\n\tu8 cmd_idx;\n\tu8 len;\n\n\tcmd_idx = info->cid;\n\n\tif (info->len > buf_len - 2) {\n\t\trtw_warn_on(1);\n\t\tlen = buf_len - 2;\n\t} else\n\t\tlen = info->len;\n\n\t/* #define DBG_PROC_SET_BTINFO_EVT */\n#ifdef DBG_PROC_SET_BTINFO_EVT\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\tRTW_INFO(\"%s: btinfo[0]=%x,btinfo[1]=%x,btinfo[2]=%x,btinfo[3]=%x btinfo[4]=%x,btinfo[5]=%x,btinfo[6]=%x,btinfo[7]=%x\\n\"\n\t\t, __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);\n#else/* !CONFIG_BT_COEXIST_SOCKET_TRX */\n\tbtinfo_evt_dump(RTW_DBGDUMP, info);\n#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */\n#endif /* DBG_PROC_SET_BTINFO_EVT */\n\n\t/* transform BT-FW btinfo to WiFI-FW C2H format and notify */\n\tif (cmd_idx == BTINFO_WIFI_FETCH)\n\t\tbuf[1] = 0;\n\telse if (cmd_idx == BTINFO_BT_AUTO_RPT)\n\t\tbuf[1] = 2;\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\telse if (0x01 == cmd_idx || 0x02 == cmd_idx)\n\t\tbuf[1] = buf[0];\n#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */\n\trtw_btcoex_BtInfoNotify(adapter , len + 1, &buf[1]);\n}\n\nu8 rtw_btinfo_cmd(_adapter *adapter, u8 *buf, u16 len)\n{\n\tstruct cmd_obj *ph2c;\n\tstruct drvextra_cmd_parm *pdrvextra_cmd_parm;\n\tu8 *btinfo;\n\tstruct cmd_priv *pcmdpriv = &adapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tbtinfo = rtw_zmalloc(len);\n\tif (btinfo == NULL) {\n\t\trtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));\n\t\trtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm->ec_id = BTINFO_WK_CID;\n\tpdrvextra_cmd_parm->type = 0;\n\tpdrvextra_cmd_parm->size = len;\n\tpdrvextra_cmd_parm->pbuf = btinfo;\n\n\t_rtw_memcpy(btinfo, buf, len);\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\treturn res;\n}\n\nstatic void rtw_btc_reduce_wl_txpwr_hdl(_adapter *adapter, u32 pwr_lvl)\n{\n\trtw_btcoex_set_reduced_wl_pwr_lvl(adapter, pwr_lvl);\n\trtw_btcoex_do_reduce_wl_pwr_lvl(adapter);\n\n\tRTW_INFO(FUNC_ADPT_FMT \": BTC reduce WL TxPwr %d dB!\\n\",\n\t\t FUNC_ADPT_ARG(adapter), pwr_lvl);\n}\n\nu8 rtw_btc_reduce_wl_txpwr_cmd(_adapter *adapter, u32 val)\n{\n\tstruct cmd_obj *pcmdobj;\n\tstruct drvextra_cmd_parm *pdrvextra_cmd_parm;\n\tstruct cmd_priv *pcmdpriv = &adapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\tpcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (pcmdobj == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm->ec_id = BTC_REDUCE_WL_TXPWR_CID;\n\tpdrvextra_cmd_parm->type = val;\n\tpdrvextra_cmd_parm->size = 0;\n\tpdrvextra_cmd_parm->pbuf = NULL;\n\n\tinit_h2fwcmd_w_parm_no_rsp(pcmdobj, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, pcmdobj);\n\nexit:\n\treturn res;\n}\n#endif /* CONFIG_BT_COEXIST */\n\nu8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len)\n{\n\tstruct cmd_obj *pcmdobj;\n\tstruct drvextra_cmd_parm *pdrvextra_cmd_parm;\n\tu8 *ph2c_content;\n\tstruct cmd_priv *pcmdpriv = &adapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\tpcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (pcmdobj == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tph2c_content = rtw_zmalloc(len);\n\tif (ph2c_content == NULL) {\n\t\trtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));\n\t\trtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm->ec_id = TEST_H2C_CID;\n\tpdrvextra_cmd_parm->type = 0;\n\tpdrvextra_cmd_parm->size = len;\n\tpdrvextra_cmd_parm->pbuf = ph2c_content;\n\n\t_rtw_memcpy(ph2c_content, buf, len);\n\n\tinit_h2fwcmd_w_parm_no_rsp(pcmdobj, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, pcmdobj);\n\nexit:\n\treturn res;\n}\n\n#ifdef CONFIG_MP_INCLUDED\nstatic s32 rtw_mp_cmd_hdl(_adapter *padapter, u8 mp_cmd_id)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tint ret = H2C_SUCCESS;\n\tuint status = _SUCCESS;\n\n\tif (mp_cmd_id == MP_START) {\n\t\tif (padapter->registrypriv.mp_mode == 0) {\n\t\t\trtw_intf_stop(padapter);\n\t\t\trtw_hal_deinit(padapter);\n\t\t\tpadapter->registrypriv.mp_mode = 1;\n#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1)\n\t\tpadapter->mppriv.CureFuseBTCoex = pHalData->EEPROMBluetoothCoexist;\n\t\tpHalData->EEPROMBluetoothCoexist = _FALSE;\n#endif\n#ifdef CONFIG_RF_POWER_TRIM\n\t\t\tif (!IS_HARDWARE_TYPE_8814A(padapter) && !IS_HARDWARE_TYPE_8822B(padapter) && !IS_HARDWARE_TYPE_8822C(padapter)) {\n\t\t\t\tpadapter->registrypriv.RegPwrTrimEnable = 1;\n\t\t\t\trtw_hal_read_chip_info(padapter);\n\t\t\t}\n#endif /*CONFIG_RF_POWER_TRIM*/\n\t\t\trtw_reset_drv_sw(padapter);\n#ifdef CONFIG_NEW_NETDEV_HDL\n\t\t\tif (!rtw_is_hw_init_completed(padapter)) {\n\t\t\t\tstatus = rtw_hal_init(padapter);\n\t\t\t\tif (status == _FAIL) {\n\t\t\t\t\tret = H2C_REJECTED;\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t\trtw_hal_iface_init(padapter);\n\t\t\t}\n#else\n\t\t\tstatus = rtw_hal_init(padapter);\n\t\t\tif (status == _FAIL) {\n\t\t\t\tret = H2C_REJECTED;\n\t\t\t\tgoto exit;\n\t\t\t}\n#endif /*CONFIG_NEW_NETDEV_HDL*/\n#ifndef RTW_HALMAC\n\t\t\trtw_intf_start(padapter);\n#endif /* !RTW_HALMAC */\n#ifdef RTW_HALMAC /*for New IC*/\n\t\t\tMPT_InitializeAdapter(padapter, 1);\n#endif /* CONFIG_MP_INCLUDED */\n\t\t}\n\n\t\tif (padapter->registrypriv.mp_mode == 0) {\n\t\t\tret = H2C_REJECTED;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (padapter->mppriv.mode == MP_OFF) {\n\t\t\tif (mp_start_test(padapter) == _FAIL) {\n\t\t\t\tret = H2C_REJECTED;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tpadapter->mppriv.mode = MP_ON;\n\t\t\tMPT_PwrCtlDM(padapter, 0);\n\t\t}\n\t\tpadapter->mppriv.bmac_filter = _FALSE;\n#ifdef CONFIG_RTL8723B\n#ifdef CONFIG_USB_HCI\n\t\trtw_write32(padapter, 0x765, 0x0000);\n\t\trtw_write32(padapter, 0x948, 0x0280);\n#else\n\t\trtw_write32(padapter, 0x765, 0x0000);\n\t\trtw_write32(padapter, 0x948, 0x0000);\n#endif\n#ifdef CONFIG_FOR_RTL8723BS_VQ0\n\t\trtw_write32(padapter, 0x765, 0x0000);\n\t\trtw_write32(padapter, 0x948, 0x0280);\n#endif\n\t\trtw_write8(padapter, 0x66, 0x27); /*Open BT uart Log*/\n\t\trtw_write8(padapter, 0xc50, 0x20); /*for RX init Gain*/\n#endif\n\t\todm_write_dig(&pHalData->odmpriv, 0x20);\n\n\t} else if (mp_cmd_id == MP_STOP) {\n\t\tif (padapter->registrypriv.mp_mode == 1) {\n\t\t\tMPT_DeInitAdapter(padapter);\n\t\t\trtw_intf_stop(padapter);\n\t\t\trtw_hal_deinit(padapter);\n\t\t\tpadapter->registrypriv.mp_mode = 0;\n#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1)\n\t\t\tpHalData->EEPROMBluetoothCoexist = padapter->mppriv.CureFuseBTCoex;\n#endif\n\t\t\trtw_reset_drv_sw(padapter);\n#ifdef CONFIG_NEW_NETDEV_HDL\n\t\t\tif (!rtw_is_hw_init_completed(padapter)) {\n\t\t\t\tstatus = rtw_hal_init(padapter);\n\t\t\t\tif (status == _FAIL) {\n\t\t\t\t\tret = H2C_REJECTED;\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t\trtw_hal_iface_init(padapter);\n\t\t\t}\n#else\n\t\t\tstatus = rtw_hal_init(padapter);\n\t\t\tif (status == _FAIL) {\n\t\t\t\tret = H2C_REJECTED;\n\t\t\t\tgoto exit;\n\t\t\t}\n#endif /*CONFIG_NEW_NETDEV_HDL*/\n#ifndef RTW_HALMAC\n\t\t\trtw_intf_start(padapter);\n#endif /* !RTW_HALMAC */\n\t\t}\n\n\t\tif (padapter->mppriv.mode != MP_OFF) {\n\t\t\tmp_stop_test(padapter);\n\t\t\tpadapter->mppriv.mode = MP_OFF;\n\t\t}\n\n\t} else {\n\t\tRTW_INFO(FUNC_ADPT_FMT\"invalid id:%d\\n\", FUNC_ADPT_ARG(padapter), mp_cmd_id);\n\t\tret = H2C_PARAMETERS_ERROR;\n\t\trtw_warn_on(1);\n\t}\n\nexit:\n\treturn ret;\n}\n\nu8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags)\n{\n\tstruct cmd_obj *cmdobj;\n\tstruct drvextra_cmd_parm *parm;\n\tstruct cmd_priv *pcmdpriv = &adapter->cmdpriv;\n\tstruct submit_ctx sctx;\n\tu8\tres = _SUCCESS;\n\n\tparm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (parm == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tparm->ec_id = MP_CMD_WK_CID;\n\tparm->type = mp_cmd_id;\n\tparm->size = 0;\n\tparm->pbuf = NULL;\n\n\tif (flags & RTW_CMDF_DIRECTLY) {\n\t\t/* no need to enqueue, do the cmd hdl directly and free cmd parameter */\n\t\tif (H2C_SUCCESS != rtw_mp_cmd_hdl(adapter, mp_cmd_id))\n\t\t\tres = _FAIL;\n\t\trtw_mfree((u8 *)parm, sizeof(*parm));\n\t} else {\n\t\t/* need enqueue, prepare cmd_obj and enqueue */\n\t\tcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));\n\t\tif (cmdobj == NULL) {\n\t\t\tres = _FAIL;\n\t\t\trtw_mfree((u8 *)parm, sizeof(*parm));\n\t\t\tgoto exit;\n\t\t}\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\t\tif (flags & RTW_CMDF_WAIT_ACK) {\n\t\t\tcmdobj->sctx = &sctx;\n\t\t\trtw_sctx_init(&sctx, 10 * 1000);\n\t\t}\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, cmdobj);\n\n\t\tif (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {\n\t\t\trtw_sctx_wait(&sctx, __func__);\n\t\t\t_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t\tif (sctx.status == RTW_SCTX_SUBMITTED)\n\t\t\t\tcmdobj->sctx = NULL;\n\t\t\t_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\t\tif (sctx.status != RTW_SCTX_DONE_SUCCESS)\n\t\t\t\tres = _FAIL;\n\t\t}\n\t}\n\nexit:\n\treturn res;\n}\n#endif\t/*CONFIG_MP_INCLUDED*/\n\n#ifdef CONFIG_RTW_CUSTOMER_STR\nstatic s32 rtw_customer_str_cmd_hdl(_adapter *adapter, u8 write, const u8 *cstr)\n{\n\tint ret = H2C_SUCCESS;\n\n\tif (write)\n\t\tret = rtw_hal_h2c_customer_str_write(adapter, cstr);\n\telse\n\t\tret = rtw_hal_h2c_customer_str_req(adapter);\n\n\treturn ret == _SUCCESS ? H2C_SUCCESS : H2C_REJECTED;\n}\n\nstatic u8 rtw_customer_str_cmd(_adapter *adapter, u8 write, const u8 *cstr)\n{\n\tstruct cmd_obj *cmdobj;\n\tstruct drvextra_cmd_parm *parm;\n\tu8 *str = NULL;\n\tstruct cmd_priv *pcmdpriv = &adapter->cmdpriv;\n\tstruct submit_ctx sctx;\n\tu8 res = _SUCCESS;\n\n\tparm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (parm == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tif (write) {\n\t\tstr = rtw_zmalloc(RTW_CUSTOMER_STR_LEN);\n\t\tif (str == NULL) {\n\t\t\trtw_mfree((u8 *)parm, sizeof(struct drvextra_cmd_parm));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\tparm->ec_id = CUSTOMER_STR_WK_CID;\n\tparm->type = write;\n\tparm->size = write ? RTW_CUSTOMER_STR_LEN : 0;\n\tparm->pbuf = write ? str : NULL;\n\n\tif (write)\n\t\t_rtw_memcpy(str, cstr, RTW_CUSTOMER_STR_LEN);\n\n\t/* need enqueue, prepare cmd_obj and enqueue */\n\tcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));\n\tif (cmdobj == NULL) {\n\t\tres = _FAIL;\n\t\trtw_mfree((u8 *)parm, sizeof(*parm));\n\t\tif (write)\n\t\t\trtw_mfree(str, RTW_CUSTOMER_STR_LEN);\n\t\tgoto exit;\n\t}\n\n\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\tcmdobj->sctx = &sctx;\n\trtw_sctx_init(&sctx, 2 * 1000);\n\n\tres = rtw_enqueue_cmd(pcmdpriv, cmdobj);\n\n\tif (res == _SUCCESS) {\n\t\trtw_sctx_wait(&sctx, __func__);\n\t\t_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\tif (sctx.status == RTW_SCTX_SUBMITTED)\n\t\t\tcmdobj->sctx = NULL;\n\t\t_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\tif (sctx.status != RTW_SCTX_DONE_SUCCESS)\n\t\t\tres = _FAIL;\n\t}\n\nexit:\n\treturn res;\n}\n\ninline u8 rtw_customer_str_req_cmd(_adapter *adapter)\n{\n\treturn rtw_customer_str_cmd(adapter, 0, NULL);\n}\n\ninline u8 rtw_customer_str_write_cmd(_adapter *adapter, const u8 *cstr)\n{\n\treturn rtw_customer_str_cmd(adapter, 1, cstr);\n}\n#endif /* CONFIG_RTW_CUSTOMER_STR */\n\nu8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *pbuf, u16 length, u8 type)\n{\n\tstruct cmd_obj *ph2c;\n\tstruct drvextra_cmd_parm *pdrvextra_cmd_parm;\n\tstruct cmd_priv *pcmdpriv = &padapter->cmdpriv;\n\tu8 *extra_cmd_buf;\n\tu8 res = _SUCCESS;\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\textra_cmd_buf = rtw_zmalloc(length);\n\tif (extra_cmd_buf == NULL) {\n\t\trtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));\n\t\trtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t_rtw_memcpy(extra_cmd_buf, pbuf, length);\n\tpdrvextra_cmd_parm->ec_id = C2H_WK_CID;\n\tpdrvextra_cmd_parm->type = type;\n\tpdrvextra_cmd_parm->size = length;\n\tpdrvextra_cmd_parm->pbuf = extra_cmd_buf;\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\treturn res;\n}\n\n#ifdef CONFIG_FW_C2H_REG\ninline u8 rtw_c2h_reg_wk_cmd(_adapter *adapter, u8 *c2h_evt)\n{\n\treturn rtw_c2h_wk_cmd(adapter, c2h_evt, c2h_evt ? C2H_REG_LEN : 0, C2H_TYPE_REG);\n}\n#endif\n\n#ifdef CONFIG_FW_C2H_PKT\ninline u8 rtw_c2h_packet_wk_cmd(_adapter *adapter, u8 *c2h_evt, u16 length)\n{\n\treturn rtw_c2h_wk_cmd(adapter, c2h_evt, length, C2H_TYPE_PKT);\n}\n#endif\n\nu8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void *), void *context)\n{\n\tstruct cmd_priv *pcmdpriv;\n\tstruct cmd_obj *ph2c;\n\tstruct RunInThread_param *parm;\n\ts32 res = _SUCCESS;\n\n\n\tpcmdpriv = &padapter->cmdpriv;\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (NULL == ph2c) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tparm = (struct RunInThread_param *)rtw_zmalloc(sizeof(struct RunInThread_param));\n\tif (NULL == parm) {\n\t\trtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tparm->func = func;\n\tparm->context = context;\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, parm, GEN_CMD_CODE(_RunInThreadCMD));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\nexit:\n\n\n\treturn res;\n}\n\n#ifdef CONFIG_FW_C2H_REG\ns32 c2h_evt_hdl(_adapter *adapter, u8 *c2h_evt, c2h_id_filter filter)\n{\n\ts32 ret = _FAIL;\n\tu8 buf[C2H_REG_LEN] = {0};\n\tu8 id, seq, plen;\n\tu8 *payload;\n\n\tif (!c2h_evt) {\n\t\t/* No c2h event in cmd_obj, read c2h event before handling*/\n\t\tif (rtw_hal_c2h_evt_read(adapter, buf) != _SUCCESS)\n\t\t\tgoto exit;\n\t\tc2h_evt = buf;\n\t}\n\n\trtw_hal_c2h_reg_hdr_parse(adapter, c2h_evt, &id, &seq, &plen, &payload);\n\n\tif (filter && filter(adapter, id, seq, plen, payload) == _FALSE)\n\t\tgoto exit;\n\n\tret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload);\n\nexit:\n\treturn ret;\n}\n#endif /* CONFIG_FW_C2H_REG */\n\nu8 session_tracker_cmd(_adapter *adapter, u8 cmd, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)\n{\n\tstruct cmd_priv\t*cmdpriv = &adapter->cmdpriv;\n\tstruct cmd_obj *cmdobj;\n\tstruct drvextra_cmd_parm *cmd_parm;\n\tstruct st_cmd_parm *st_parm;\n\tu8\tres = _SUCCESS;\n\n\tcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (cmdobj == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tcmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (cmd_parm == NULL) {\n\t\trtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tst_parm = (struct st_cmd_parm *)rtw_zmalloc(sizeof(struct st_cmd_parm));\n\tif (st_parm == NULL) {\n\t\trtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));\n\t\trtw_mfree((u8 *)cmd_parm, sizeof(struct drvextra_cmd_parm));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tst_parm->cmd = cmd;\n\tst_parm->sta = sta;\n\tif (cmd != ST_CMD_CHK) {\n\t\t_rtw_memcpy(&st_parm->local_naddr, local_naddr, 4);\n\t\t_rtw_memcpy(&st_parm->local_port, local_port, 2);\n\t\t_rtw_memcpy(&st_parm->remote_naddr, remote_naddr, 4);\n\t\t_rtw_memcpy(&st_parm->remote_port, remote_port, 2);\n\t}\n\n\tcmd_parm->ec_id = SESSION_TRACKER_WK_CID;\n\tcmd_parm->type = 0;\n\tcmd_parm->size = sizeof(struct st_cmd_parm);\n\tcmd_parm->pbuf = (u8 *)st_parm;\n\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\tcmdobj->no_io = 1;\n\n\tres = rtw_enqueue_cmd(cmdpriv, cmdobj);\n\nexit:\n\treturn res;\n}\n\ninline u8 session_tracker_chk_cmd(_adapter *adapter, struct sta_info *sta)\n{\n\treturn session_tracker_cmd(adapter, ST_CMD_CHK, sta, NULL, NULL, NULL, NULL);\n}\n\ninline u8 session_tracker_add_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)\n{\n\treturn session_tracker_cmd(adapter, ST_CMD_ADD, sta, local_naddr, local_port, remote_naddr, remote_port);\n}\n\ninline u8 session_tracker_del_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)\n{\n\treturn session_tracker_cmd(adapter, ST_CMD_DEL, sta, local_naddr, local_port, remote_naddr, remote_port);\n}\n\nvoid session_tracker_chk_for_sta(_adapter *adapter, struct sta_info *sta)\n{\n\tstruct st_ctl_t *st_ctl = &sta->st_ctl;\n\tint i;\n\t_irqL irqL;\n\t_list *plist, *phead, *pnext;\n\t_list dlist;\n\tstruct session_tracker *st = NULL;\n\tu8 op_wfd_mode = MIRACAST_DISABLED;\n\n\tif (DBG_SESSION_TRACKER)\n\t\tRTW_INFO(FUNC_ADPT_FMT\" sta:%p\\n\", FUNC_ADPT_ARG(adapter), sta);\n\n\tif (!(sta->state & _FW_LINKED))\n\t\tgoto exit;\n\n\tfor (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) {\n\t\tif (st_ctl->reg[i].s_proto != 0)\n\t\t\tbreak;\n\t}\n\tif (i >= SESSION_TRACKER_REG_ID_NUM)\n\t\tgoto chk_sta;\n\n\t_rtw_init_listhead(&dlist);\n\n\t_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);\n\n\tphead = &st_ctl->tracker_q.queue;\n\tplist = get_next(phead);\n\tpnext = get_next(plist);\n\twhile (rtw_end_of_queue_search(phead, plist) == _FALSE) {\n\t\tst = LIST_CONTAINOR(plist, struct session_tracker, list);\n\t\tplist = pnext;\n\t\tpnext = get_next(pnext);\n\n\t\tif (st->status != ST_STATUS_ESTABLISH\n\t\t\t&& rtw_get_passing_time_ms(st->set_time) > ST_EXPIRE_MS\n\t\t) {\n\t\t\trtw_list_delete(&st->list);\n\t\t\trtw_list_insert_tail(&st->list, &dlist);\n\t\t}\n\n\t\t/* TODO: check OS for status update */\n\t\tif (st->status == ST_STATUS_CHECK)\n\t\t\tst->status = ST_STATUS_ESTABLISH;\n\n\t\tif (st->status != ST_STATUS_ESTABLISH)\n\t\t\tcontinue;\n\n\t\t#ifdef CONFIG_WFD\n\t\tif (0)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" local:%u, remote:%u, rtsp:%u, %u, %u\\n\", FUNC_ADPT_ARG(adapter)\n\t\t\t\t, ntohs(st->local_port), ntohs(st->remote_port), adapter->wfd_info.rtsp_ctrlport, adapter->wfd_info.tdls_rtsp_ctrlport\n\t\t\t\t, adapter->wfd_info.peer_rtsp_ctrlport);\n\t\tif (ntohs(st->local_port) == adapter->wfd_info.rtsp_ctrlport)\n\t\t\top_wfd_mode |= MIRACAST_SINK;\n\t\tif (ntohs(st->local_port) == adapter->wfd_info.tdls_rtsp_ctrlport)\n\t\t\top_wfd_mode |= MIRACAST_SINK;\n\t\tif (ntohs(st->remote_port) == adapter->wfd_info.peer_rtsp_ctrlport)\n\t\t\top_wfd_mode |= MIRACAST_SOURCE;\n\t\t#endif\n\t}\n\n\t_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);\n\n\tplist = get_next(&dlist);\n\twhile (rtw_end_of_queue_search(&dlist, plist) == _FALSE) {\n\t\tst = LIST_CONTAINOR(plist, struct session_tracker, list);\n\t\tplist = get_next(plist);\n\t\trtw_mfree((u8 *)st, sizeof(struct session_tracker));\n\t}\n\nchk_sta:\n\tif (STA_OP_WFD_MODE(sta) != op_wfd_mode) {\n\t\tSTA_SET_OP_WFD_MODE(sta, op_wfd_mode);\n\t\trtw_sta_media_status_rpt_cmd(adapter, sta, 1);\n\t}\n\nexit:\n\treturn;\n}\n\nvoid session_tracker_chk_for_adapter(_adapter *adapter)\n{\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct sta_info *sta;\n\tint i;\n\t_irqL irqL;\n\t_list *plist, *phead;\n\tu8 op_wfd_mode = MIRACAST_DISABLED;\n\n\t_enter_critical_bh(&stapriv->sta_hash_lock, &irqL);\n\n\tfor (i = 0; i < NUM_STA; i++) {\n\t\tphead = &(stapriv->sta_hash[i]);\n\t\tplist = get_next(phead);\n\n\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\tsta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\t\t\tplist = get_next(plist);\n\n\t\t\tsession_tracker_chk_for_sta(adapter, sta);\n\n\t\t\top_wfd_mode |= STA_OP_WFD_MODE(sta);\n\t\t}\n\t}\n\n\t_exit_critical_bh(&stapriv->sta_hash_lock, &irqL);\n\n#ifdef CONFIG_WFD\n\tadapter->wfd_info.op_wfd_mode = MIRACAST_MODE_REVERSE(op_wfd_mode);\n#endif\n}\n\nvoid session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm)\n{\n\tu8 cmd = parm->cmd;\n\tstruct sta_info *sta = parm->sta;\n\n\tif (cmd == ST_CMD_CHK) {\n\t\tif (sta)\n\t\t\tsession_tracker_chk_for_sta(adapter, sta);\n\t\telse\n\t\t\tsession_tracker_chk_for_adapter(adapter);\n\n\t\tgoto exit;\n\n\t} else if (cmd == ST_CMD_ADD || cmd == ST_CMD_DEL) {\n\t\tstruct st_ctl_t *st_ctl;\n\t\tu32 local_naddr = parm->local_naddr;\n\t\tu16 local_port = parm->local_port;\n\t\tu32 remote_naddr = parm->remote_naddr;\n\t\tu16 remote_port = parm->remote_port;\n\t\tstruct session_tracker *st = NULL;\n\t\t_irqL irqL;\n\t\t_list *plist, *phead;\n\t\tu8 free_st = 0;\n\t\tu8 alloc_st = 0;\n\n\t\tif (DBG_SESSION_TRACKER)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" cmd:%u, sta:%p, local:\"IP_FMT\":\"PORT_FMT\", remote:\"IP_FMT\":\"PORT_FMT\"\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), cmd, sta\n\t\t\t\t, IP_ARG(&local_naddr), PORT_ARG(&local_port)\n\t\t\t\t, IP_ARG(&remote_naddr), PORT_ARG(&remote_port)\n\t\t\t);\n\n\t\tif (!(sta->state & _FW_LINKED))\n\t\t\tgoto exit;\n\n\t\tst_ctl = &sta->st_ctl;\n\n\t\t_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);\n\n\t\tphead = &st_ctl->tracker_q.queue;\n\t\tplist = get_next(phead);\n\t\twhile (rtw_end_of_queue_search(phead, plist) == _FALSE) {\n\t\t\tst = LIST_CONTAINOR(plist, struct session_tracker, list);\n\n\t\t\tif (st->local_naddr == local_naddr\n\t\t\t\t&& st->local_port == local_port\n\t\t\t\t&& st->remote_naddr == remote_naddr\n\t\t\t\t&& st->remote_port == remote_port)\n\t\t\t\tbreak;\n\n\t\t\tplist = get_next(plist);\n\t\t}\n\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tst = NULL;\n\n\t\tswitch (cmd) {\n\t\tcase ST_CMD_DEL:\n\t\t\tif (st) {\n\t\t\t\trtw_list_delete(plist);\n\t\t\t\tfree_st = 1;\n\t\t\t}\n\t\t\tgoto unlock;\n\t\tcase ST_CMD_ADD:\n\t\t\tif (!st)\n\t\t\t\talloc_st = 1;\n\t\t}\n\nunlock:\n\t\t_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);\n\n\t\tif (free_st) {\n\t\t\trtw_mfree((u8 *)st, sizeof(struct session_tracker));\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (alloc_st) {\n\t\t\tst = (struct session_tracker *)rtw_zmalloc(sizeof(struct session_tracker));\n\t\t\tif (!st)\n\t\t\t\tgoto exit;\n\n\t\t\tst->local_naddr = local_naddr;\n\t\t\tst->local_port = local_port;\n\t\t\tst->remote_naddr = remote_naddr;\n\t\t\tst->remote_port = remote_port;\n\t\t\tst->set_time = rtw_get_current_time();\n\t\t\tst->status = ST_STATUS_CHECK;\n\n\t\t\t_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);\n\t\t\trtw_list_insert_tail(&st->list, phead);\n\t\t\t_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);\n\t\t}\n\t}\n\nexit:\n\treturn;\n}\n\n#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW)\nstatic s32 rtw_req_per_cmd_hdl(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\tstruct macid_bmp req_macid_bmp, *macid_bmp;\n\tu8 i, ret = _FAIL;\n\n\tmacid_bmp = &macid_ctl->if_g[adapter->iface_id];\n\t_rtw_memcpy(&req_macid_bmp, macid_bmp, sizeof(struct macid_bmp));\n\n\t/* Clear none mesh's macid */\n\tfor (i = 0; i < macid_ctl->num; i++) {\n\t\tu8 role;\n\t\trole = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]);\n\t\tif (role != H2C_MSR_ROLE_MESH)\n\t\t\trtw_macid_map_clr(&req_macid_bmp, i);\n\t}\n\n\t/* group_macid: always be 0 in NIC, so only pass macid_bitmap.m0\n\t * rpt_type: 0 includes all info in 1, use 0 for now \n\t * macid_bitmap: pass m0 only for NIC\n\t */\n\tret = rtw_hal_set_req_per_rpt_cmd(adapter, 0, 0, req_macid_bmp.m0);\n\n\treturn ret;\n}\n\nu8 rtw_req_per_cmd(_adapter *adapter)\n{\n\tstruct cmd_obj *cmdobj;\n\tstruct drvextra_cmd_parm *parm;\n\tstruct cmd_priv *pcmdpriv = &adapter->cmdpriv;\n\tstruct submit_ctx sctx;\n\tu8 res = _SUCCESS;\n\n\tparm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (parm == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tparm->ec_id = REQ_PER_CMD_WK_CID;\n\tparm->type = 0;\n\tparm->size = 0;\n\tparm->pbuf = NULL;\n\n\tcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));\n\tif (cmdobj == NULL) {\n\t\tres = _FAIL;\n\t\trtw_mfree((u8 *)parm, sizeof(*parm));\n\t\tgoto exit;\n\t}\n\n\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, cmdobj);\n\nexit:\n\treturn res;\n}\n#endif\n\nu8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf)\n{\n\tint ret = H2C_SUCCESS;\n\tstruct drvextra_cmd_parm *pdrvextra_cmd;\n\n\tif (!pbuf)\n\t\treturn H2C_PARAMETERS_ERROR;\n\n\tpdrvextra_cmd = (struct drvextra_cmd_parm *)pbuf;\n\n\tswitch (pdrvextra_cmd->ec_id) {\n\tcase STA_MSTATUS_RPT_WK_CID:\n\t\trtw_sta_media_status_rpt_cmd_hdl(padapter, (struct sta_media_status_rpt_cmd_parm *)pdrvextra_cmd->pbuf);\n\t\tbreak;\n\n\tcase DYNAMIC_CHK_WK_CID:/*only  primary padapter go to this cmd, but execute dynamic_chk_wk_hdl() for two interfaces */\n\t\trtw_dynamic_chk_wk_hdl(padapter);\n\t\tbreak;\n\tcase POWER_SAVING_CTRL_WK_CID:\n\t\tpower_saving_wk_hdl(padapter);\n\t\tbreak;\n#ifdef CONFIG_LPS\n\tcase LPS_CTRL_WK_CID:\n\t\tlps_ctrl_wk_hdl(padapter, (u8)pdrvextra_cmd->type, pdrvextra_cmd->pbuf);\n\t\tbreak;\n\tcase DM_IN_LPS_WK_CID:\n\t\trtw_dm_in_lps_hdl(padapter);\n\t\tbreak;\n\tcase LPS_CHANGE_DTIM_CID:\n\t\trtw_lps_change_dtim_hdl(padapter, (u8)pdrvextra_cmd->type);\n\t\tbreak;\n#endif\n#if (RATE_ADAPTIVE_SUPPORT == 1)\n\tcase RTP_TIMER_CFG_WK_CID:\n\t\trpt_timer_setting_wk_hdl(padapter, pdrvextra_cmd->type);\n\t\tbreak;\n#endif\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\tcase ANT_SELECT_WK_CID:\n\t\tantenna_select_wk_hdl(padapter, pdrvextra_cmd->type);\n\t\tbreak;\n#endif\n#ifdef CONFIG_P2P_PS\n\tcase P2P_PS_WK_CID:\n\t\tp2p_ps_wk_hdl(padapter, pdrvextra_cmd->type);\n\t\tbreak;\n#endif\n#ifdef CONFIG_P2P\n\tcase P2P_PROTO_WK_CID:\n\t\t/*\n\t\t* Commented by Albert 2011/07/01\n\t\t* I used the type_size as the type command\n\t\t*/\n\t\tret = p2p_protocol_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);\n\t\tbreak;\n#endif\n#ifdef CONFIG_AP_MODE\n\tcase CHECK_HIQ_WK_CID:\n\t\trtw_chk_hi_queue_hdl(padapter);\n\t\tbreak;\n#endif\n\t/* add for CONFIG_IEEE80211W, none 11w can use it */\n\tcase RESET_SECURITYPRIV:\n\t\treset_securitypriv_hdl(padapter);\n\t\tbreak;\n\tcase FREE_ASSOC_RESOURCES:\n\t\tfree_assoc_resources_hdl(padapter, (u8)pdrvextra_cmd->type);\n\t\tbreak;\n\tcase C2H_WK_CID:\n\t\tswitch (pdrvextra_cmd->type) {\n\t\t#ifdef CONFIG_FW_C2H_REG\n\t\tcase C2H_TYPE_REG:\n\t\t\tc2h_evt_hdl(padapter, pdrvextra_cmd->pbuf, NULL);\n\t\t\tbreak;\n\t\t#endif\n\t\t#ifdef CONFIG_FW_C2H_PKT\n\t\tcase C2H_TYPE_PKT:\n\t\t\trtw_hal_c2h_pkt_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->size);\n\t\t\tbreak;\n\t\t#endif\n\t\tdefault:\n\t\t\tRTW_ERR(\"unknown C2H type:%d\\n\", pdrvextra_cmd->type);\n\t\t\trtw_warn_on(1);\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n#ifdef CONFIG_BEAMFORMING\n\tcase BEAMFORMING_WK_CID:\n\t\tbeamforming_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);\n\t\tbreak;\n#endif\n\tcase DM_RA_MSK_WK_CID:\n\t\trtw_dm_ra_mask_hdl(padapter, (struct sta_info *)pdrvextra_cmd->pbuf);\n\t\tbreak;\n#ifdef CONFIG_BT_COEXIST\n\tcase BTINFO_WK_CID:\n\t\trtw_btinfo_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->size);\n\t\tbreak;\n\tcase BTC_REDUCE_WL_TXPWR_CID:\n\t\trtw_btc_reduce_wl_txpwr_hdl(padapter, pdrvextra_cmd->type);\n\t\tbreak;\n#endif\n#ifdef CONFIG_DFS_MASTER\n\tcase DFS_RADAR_DETECT_WK_CID:\n\t\trtw_dfs_rd_hdl(padapter);\n\t\tbreak;\n\tcase DFS_RADAR_DETECT_EN_DEC_WK_CID:\n\t\trtw_dfs_rd_en_decision(padapter, MLME_ACTION_NONE, 0);\n\t\tbreak;\n#endif\n\tcase SESSION_TRACKER_WK_CID:\n\t\tsession_tracker_cmd_hdl(padapter, (struct st_cmd_parm *)pdrvextra_cmd->pbuf);\n\t\tbreak;\n\tcase EN_HW_UPDATE_TSF_WK_CID:\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_EN_HW_UPDATE_TSF, NULL);\n\t\tbreak;\n\tcase PERIOD_TSF_UPDATE_END_WK_CID:\n\t\trtw_hal_periodic_tsf_update_chk(padapter);\n\t\tbreak;\n\tcase TEST_H2C_CID:\n\t\trtw_hal_fill_h2c_cmd(padapter, pdrvextra_cmd->pbuf[0], pdrvextra_cmd->size - 1, &pdrvextra_cmd->pbuf[1]);\n\t\tbreak;\n\tcase MP_CMD_WK_CID:\n#ifdef CONFIG_MP_INCLUDED\n\t\tret = rtw_mp_cmd_hdl(padapter, pdrvextra_cmd->type);\n#endif\n\t\tbreak;\n#ifdef CONFIG_RTW_CUSTOMER_STR\n\tcase CUSTOMER_STR_WK_CID:\n\t\tret = rtw_customer_str_cmd_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);\n\t\tbreak;\n#endif\n\n#ifdef CONFIG_RTW_REPEATER_SON\n\tcase RSON_SCAN_WK_CID:\n\t\trtw_rson_scan_cmd_hdl(padapter, pdrvextra_cmd->type);\n\t\tbreak;\n#endif\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tcase MGNT_TX_WK_CID:\n\t\tret = rtw_mgnt_tx_handler(padapter, pdrvextra_cmd->pbuf);\n\t\tbreak;\n#endif /* CONFIG_IOCTL_CFG80211 */\n#ifdef CONFIG_MCC_MODE\n\tcase MCC_CMD_WK_CID:\n\t\tret = rtw_mcc_cmd_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);\n\t\tbreak;\n#endif /* CONFIG_MCC_MODE */\n#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW)\n\tcase REQ_PER_CMD_WK_CID:\n\t\tret = rtw_req_per_cmd_hdl(padapter);\n\t\tbreak;\n#endif\n#ifdef CONFIG_SUPPORT_STATIC_SMPS\n\tcase SSMPS_WK_CID :\n\t\trtw_ssmps_wk_hdl(padapter, (struct ssmps_cmd_parm *)pdrvextra_cmd->pbuf);\n\t\tbreak;\n#endif\n#ifdef CONFIG_CTRL_TXSS_BY_TP\n\tcase TXSS_WK_CID :\n\t\trtw_ctrl_txss_wk_hdl(padapter, (struct txss_cmd_parm *)pdrvextra_cmd->pbuf);\n\t\tbreak;\n#endif\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (pdrvextra_cmd->pbuf && pdrvextra_cmd->size > 0)\n\t\trtw_mfree(pdrvextra_cmd->pbuf, pdrvextra_cmd->size);\n\n\treturn ret;\n}\n\nvoid rtw_survey_cmd_callback(_adapter\t*padapter ,  struct cmd_obj *pcmd)\n{\n\tstruct\tmlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n\n\tif (pcmd->res == H2C_DROPPED) {\n\t\t/* TODO: cancel timer and do timeout handler directly... */\n\t\t/* need to make timeout handlerOS independent */\n\t\tmlme_set_scan_to_timer(pmlmepriv, 1);\n\t} else if (pcmd->res != H2C_SUCCESS) {\n\t\tmlme_set_scan_to_timer(pmlmepriv, 1);\n\t}\n\n\t/* free cmd */\n\trtw_free_cmd_obj(pcmd);\n\n}\nvoid rtw_disassoc_cmd_callback(_adapter\t*padapter,  struct cmd_obj *pcmd)\n{\n\t_irqL\tirqL;\n\tstruct\tmlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n\n\tif (pcmd->res != H2C_SUCCESS) {\n\t\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\t\tset_fwstate(pmlmepriv, _FW_LINKED);\n\t\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\t\tgoto exit;\n\t}\n#ifdef CONFIG_BR_EXT\n\telse /* clear bridge database */\n\t\tnat25_db_cleanup(padapter);\n#endif /* CONFIG_BR_EXT */\n\n\t/* free cmd */\n\trtw_free_cmd_obj(pcmd);\n\nexit:\n\treturn;\n}\n\n\nvoid rtw_getmacreg_cmdrsp_callback(_adapter *padapter,  struct cmd_obj *pcmd)\n{\n\n\n\trtw_free_cmd_obj(pcmd);\n\n}\n\nvoid rtw_joinbss_cmd_callback(_adapter\t*padapter,  struct cmd_obj *pcmd)\n{\n\tstruct\tmlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n\n\tif (pcmd->res == H2C_DROPPED) {\n\t\t/* TODO: cancel timer and do timeout handler directly... */\n\t\t/* need to make timeout handlerOS independent */\n\t\t_set_timer(&pmlmepriv->assoc_timer, 1);\n\t} else if (pcmd->res != H2C_SUCCESS)\n\t\t_set_timer(&pmlmepriv->assoc_timer, 1);\n\n\trtw_free_cmd_obj(pcmd);\n\n}\n\nvoid rtw_create_ibss_post_hdl(_adapter *padapter, int status)\n{\n\t_irqL irqL;\n\tstruct wlan_network *pwlan = NULL;\n\tstruct\tmlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tWLAN_BSSID_EX *pdev_network = &padapter->registrypriv.dev_network;\n\tstruct wlan_network *mlme_cur_network = &(pmlmepriv->cur_network);\n\n\tif (status != H2C_SUCCESS)\n\t\t_set_timer(&pmlmepriv->assoc_timer, 1);\n\n\t_cancel_timer_ex(&pmlmepriv->assoc_timer);\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\n\t{\n\t\t_irqL irqL;\n\n\t\tpwlan = _rtw_alloc_network(pmlmepriv);\n\t\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\t\tif (pwlan == NULL) {\n\t\t\tpwlan = rtw_get_oldest_wlan_network(&pmlmepriv->scanned_queue);\n\t\t\tif (pwlan == NULL) {\n\t\t\t\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\t\t\t\tgoto createbss_cmd_fail;\n\t\t\t}\n\t\t\tpwlan->last_scanned = rtw_get_current_time();\n\t\t} else\n\t\t\trtw_list_insert_tail(&(pwlan->list), &pmlmepriv->scanned_queue.queue);\n\n\t\tpdev_network->Length = get_WLAN_BSSID_EX_sz(pdev_network);\n\t\t_rtw_memcpy(&(pwlan->network), pdev_network, pdev_network->Length);\n\t\t/* pwlan->fixed = _TRUE; */\n\n\t\t/* copy pdev_network information to pmlmepriv->cur_network */\n\t\t_rtw_memcpy(&mlme_cur_network->network, pdev_network, (get_WLAN_BSSID_EX_sz(pdev_network)));\n\n#if 0\n\t\t/* reset DSConfig */\n\t\tmlme_cur_network->network.Configuration.DSConfig = (u32)rtw_ch2freq(pdev_network->Configuration.DSConfig);\n#endif\n\n\t\t_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);\n\t\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\t\t/* we will set _FW_LINKED when there is one more sat to join us (rtw_stassoc_event_callback) */\n\t}\n\ncreatebss_cmd_fail:\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\treturn;\n}\n\n\n\nvoid rtw_setstaKey_cmdrsp_callback(_adapter\t*padapter ,  struct cmd_obj *pcmd)\n{\n\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct set_stakey_rsp *psetstakey_rsp = (struct set_stakey_rsp *)(pcmd->rsp);\n\tstruct sta_info\t*psta = rtw_get_stainfo(pstapriv, psetstakey_rsp->addr);\n\n\n\tif (psta == NULL) {\n\t\tgoto exit;\n\t}\n\n\t/* psta->cmn.aid = psta->cmn.mac_id = psetstakey_rsp->keyid; */ /* CAM_ID(CAM_ENTRY) */\n\nexit:\n\n\trtw_free_cmd_obj(pcmd);\n\n\n}\nvoid rtw_setassocsta_cmdrsp_callback(_adapter\t*padapter,  struct cmd_obj *pcmd)\n{\n\t_irqL\tirqL;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct set_assocsta_parm *passocsta_parm = (struct set_assocsta_parm *)(pcmd->parmbuf);\n\tstruct set_assocsta_rsp *passocsta_rsp = (struct set_assocsta_rsp *)(pcmd->rsp);\n\tstruct sta_info\t*psta = rtw_get_stainfo(pstapriv, passocsta_parm->addr);\n\n\n\tif (psta == NULL) {\n\t\tgoto exit;\n\t}\n\n\tpsta->cmn.aid = psta->cmn.mac_id = passocsta_rsp->cam_id;\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\n\tif ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) && (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE))\n\t\t_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);\n\n\tset_fwstate(pmlmepriv, _FW_LINKED);\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\nexit:\n\trtw_free_cmd_obj(pcmd);\n\n}\n\nvoid rtw_getrttbl_cmd_cmdrsp_callback(_adapter\t*padapter,  struct cmd_obj *pcmd);\nvoid rtw_getrttbl_cmd_cmdrsp_callback(_adapter\t*padapter,  struct cmd_obj *pcmd)\n{\n\n\trtw_free_cmd_obj(pcmd);\n#ifdef CONFIG_MP_INCLUDED\n\tif (padapter->registrypriv.mp_mode == 1)\n\t\tpadapter->mppriv.workparam.bcompleted = _TRUE;\n#endif\n\n\n}\n"
  },
  {
    "path": "core/rtw_debug.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_DEBUG_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\n#ifdef CONFIG_SDIO_MONITOR\n#include \"../hal/hal_halmac.h\"\n#endif\n\n#ifdef CONFIG_RTW_DEBUG\nconst char *rtw_log_level_str[] = {\n\t\"_DRV_NONE_ = 0\",\n\t\"_DRV_ALWAYS_ = 1\",\n\t\"_DRV_ERR_ = 2\",\n\t\"_DRV_WARNING_ = 3\",\n\t\"_DRV_INFO_ = 4\",\n\t\"_DRV_DEBUG_ = 5\",\n\t\"_DRV_MAX_ = 6\",\n};\n#endif\n\n#ifdef CONFIG_DEBUG_RTL871X\n\tu64 GlobalDebugComponents = 0;\n#endif /* CONFIG_DEBUG_RTL871X */\n\n#include <rtw_version.h>\n\n#ifdef CONFIG_TDLS\n\t#define TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE\t41\n#endif\n\nvoid dump_drv_version(void *sel)\n{\n\tRTW_PRINT_SEL(sel, \"%s %s\\n\", DRV_NAME, DRIVERVERSION);\n\tRTW_PRINT_SEL(sel, \"build time: %s %s\\n\", __DATE__, __TIME__);\n}\n\nvoid dump_drv_cfg(void *sel)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))\n\tchar *kernel_version = utsname()->release;\n\n\tRTW_PRINT_SEL(sel, \"\\nKernel Version: %s\\n\", kernel_version);\n#endif\n\n\tRTW_PRINT_SEL(sel, \"Driver Version: %s\\n\", DRIVERVERSION);\n\tRTW_PRINT_SEL(sel, \"------------------------------------------------\\n\");\n#ifdef CONFIG_IOCTL_CFG80211\n\tRTW_PRINT_SEL(sel, \"CFG80211\\n\");\n#ifdef RTW_USE_CFG80211_STA_EVENT\n\tRTW_PRINT_SEL(sel, \"RTW_USE_CFG80211_STA_EVENT\\n\");\n#endif\n\t#ifdef CONFIG_RADIO_WORK\n\tRTW_PRINT_SEL(sel, \"CONFIG_RADIO_WORK\\n\");\n\t#endif\n#else\n\tRTW_PRINT_SEL(sel, \"WEXT\\n\");\n#endif\n\n\tRTW_PRINT_SEL(sel, \"DBG:%d\\n\", DBG);\n#ifdef CONFIG_RTW_DEBUG\n\tRTW_PRINT_SEL(sel, \"CONFIG_RTW_DEBUG\\n\");\n#endif\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tRTW_PRINT_SEL(sel, \"CONFIG_CONCURRENT_MODE\\n\");\n#endif\n\n#ifdef CONFIG_POWER_SAVING\n\tRTW_PRINT_SEL(sel, \"CONFIG_POWER_SAVING\\n\");\n#endif\n\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\tRTW_PRINT_SEL(sel, \"LOAD_PHY_PARA_FROM_FILE - REALTEK_CONFIG_PATH=%s\\n\", REALTEK_CONFIG_PATH);\n\t#if defined(CONFIG_MULTIDRV) || defined(REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER)\n\tRTW_PRINT_SEL(sel, \"LOAD_PHY_PARA_FROM_FILE - REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER\\n\");\n\t#endif\n\n/* configurations about TX power */\n#ifdef CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY\n\tRTW_PRINT_SEL(sel, \"CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY\\n\");\n#endif\n#ifdef CONFIG_CALIBRATE_TX_POWER_TO_MAX\n\tRTW_PRINT_SEL(sel, \"CONFIG_CALIBRATE_TX_POWER_TO_MAX\\n\");\n#endif\n#endif\n\tRTW_PRINT_SEL(sel, \"RTW_DEF_MODULE_REGULATORY_CERT=0x%02x\\n\", RTW_DEF_MODULE_REGULATORY_CERT);\n\n\tRTW_PRINT_SEL(sel, \"CONFIG_TXPWR_BY_RATE=%d\\n\", CONFIG_TXPWR_BY_RATE);\n\tRTW_PRINT_SEL(sel, \"CONFIG_TXPWR_BY_RATE_EN=%d\\n\", CONFIG_TXPWR_BY_RATE_EN);\n\tRTW_PRINT_SEL(sel, \"CONFIG_TXPWR_LIMIT=%d\\n\", CONFIG_TXPWR_LIMIT);\n\tRTW_PRINT_SEL(sel, \"CONFIG_TXPWR_LIMIT_EN=%d\\n\", CONFIG_TXPWR_LIMIT_EN);\n\n\n#ifdef CONFIG_DISABLE_ODM\n\tRTW_PRINT_SEL(sel, \"CONFIG_DISABLE_ODM\\n\");\n#endif\n\n#ifdef CONFIG_MINIMAL_MEMORY_USAGE\n\tRTW_PRINT_SEL(sel, \"CONFIG_MINIMAL_MEMORY_USAGE\\n\");\n#endif\n\n\tRTW_PRINT_SEL(sel, \"CONFIG_RTW_ADAPTIVITY_EN = %d\\n\", CONFIG_RTW_ADAPTIVITY_EN);\n#if (CONFIG_RTW_ADAPTIVITY_EN)\n\tRTW_PRINT_SEL(sel, \"ADAPTIVITY_MODE = %s\\n\", (CONFIG_RTW_ADAPTIVITY_MODE) ? \"carrier_sense\" : \"normal\");\n#endif\n\n#ifdef CONFIG_WOWLAN\n\tRTW_PRINT_SEL(sel, \"CONFIG_WOWLAN - \");\n\n#ifdef CONFIG_GPIO_WAKEUP\n\tRTW_PRINT_SEL(sel, \"CONFIG_GPIO_WAKEUP - WAKEUP_GPIO_IDX:%d\\n\", WAKEUP_GPIO_IDX);\n#endif\n#endif\n\n#ifdef CONFIG_TDLS\n\tRTW_PRINT_SEL(sel, \"CONFIG_TDLS\\n\");\n#endif\n\n#ifdef CONFIG_RTW_80211R\n\tRTW_PRINT_SEL(sel, \"CONFIG_RTW_80211R\\n\");\n#endif\n\n#ifdef CONFIG_RTW_NETIF_SG\n\tRTW_PRINT_SEL(sel, \"CONFIG_RTW_NETIF_SG\\n\");\n#endif\n\n#ifdef CONFIG_RTW_WIFI_HAL\n\tRTW_PRINT_SEL(sel, \"CONFIG_RTW_WIFI_HAL\\n\");\n#endif\n\n#ifdef CONFIG_RTW_TPT_MODE\n\tRTW_PRINT_SEL(sel, \"CONFIG_RTW_TPT_MODE\\n\");\n#endif \n\n#ifdef CONFIG_USB_HCI\n#ifdef CONFIG_SUPPORT_USB_INT\n\tRTW_PRINT_SEL(sel, \"CONFIG_SUPPORT_USB_INT\\n\");\n#endif\n#ifdef CONFIG_USB_INTERRUPT_IN_PIPE\n\tRTW_PRINT_SEL(sel, \"CONFIG_USB_INTERRUPT_IN_PIPE\\n\");\n#endif\n#ifdef CONFIG_USB_TX_AGGREGATION\n\tRTW_PRINT_SEL(sel, \"CONFIG_USB_TX_AGGREGATION\\n\");\n#endif\n#ifdef CONFIG_USB_RX_AGGREGATION\n\tRTW_PRINT_SEL(sel, \"CONFIG_USB_RX_AGGREGATION\\n\");\n#endif\n#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX\n\tRTW_PRINT_SEL(sel, \"CONFIG_USE_USB_BUFFER_ALLOC_TX\\n\");\n#endif\n#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX\n\tRTW_PRINT_SEL(sel, \"CONFIG_USE_USB_BUFFER_ALLOC_RX\\n\");\n#endif\n#ifdef CONFIG_PREALLOC_RECV_SKB\n\tRTW_PRINT_SEL(sel, \"CONFIG_PREALLOC_RECV_SKB\\n\");\n#endif\n#ifdef CONFIG_FIX_NR_BULKIN_BUFFER\n\tRTW_PRINT_SEL(sel, \"CONFIG_FIX_NR_BULKIN_BUFFER\\n\");\n#endif\n#endif /*CONFIG_USB_HCI*/\n\n#ifdef CONFIG_SDIO_HCI\n#ifdef CONFIG_TX_AGGREGATION\n\tRTW_PRINT_SEL(sel, \"CONFIG_TX_AGGREGATION\\n\");\n#endif\n#ifdef CONFIG_RX_AGGREGATION\n\tRTW_PRINT_SEL(sel, \"CONFIG_RX_AGGREGATION\\n\");\n#endif\n#ifdef RTW_XMIT_THREAD_HIGH_PRIORITY\n\tRTW_PRINT_SEL(sel, \"RTW_XMIT_THREAD_HIGH_PRIORITY\\n\");\n#endif\n#ifdef RTW_XMIT_THREAD_HIGH_PRIORITY_AGG\n\tRTW_PRINT_SEL(sel, \"RTW_XMIT_THREAD_HIGH_PRIORITY_AGG\\n\");\n#endif\n#ifdef DBG_SDIO\n\tRTW_PRINT_SEL(sel, \"DBG_SDIO = %d\\n\", DBG_SDIO);\n#endif\n#ifdef CONFIG_RTW_DISABLE_HW_PDN\n\tRTW_PRINT_SEL(sel, \"CONFIG_RTW_DISABLE_HW_PDN\\n\");\n#endif\n#endif /*CONFIG_SDIO_HCI*/\n\n#ifdef CONFIG_PCI_HCI\n#endif\n\n\tRTW_PRINT_SEL(sel, \"CONFIG_IFACE_NUMBER = %d\\n\", CONFIG_IFACE_NUMBER);\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\tRTW_PRINT_SEL(sel, \"CONFIG_MI_WITH_MBSSID_CAM\\n\");\n#endif\n#ifdef CONFIG_SWTIMER_BASED_TXBCN\n\tRTW_PRINT_SEL(sel, \"CONFIG_SWTIMER_BASED_TXBCN\\n\");\n#endif\n#ifdef CONFIG_FW_HANDLE_TXBCN\n\tRTW_PRINT_SEL(sel, \"CONFIG_FW_HANDLE_TXBCN\\n\");\n\tRTW_PRINT_SEL(sel, \"CONFIG_LIMITED_AP_NUM = %d\\n\", CONFIG_LIMITED_AP_NUM);\n#endif\n#ifdef CONFIG_CLIENT_PORT_CFG\n\tRTW_PRINT_SEL(sel, \"CONFIG_CLIENT_PORT_CFG\\n\");\n#endif\n#ifdef CONFIG_PCI_TX_POLLING\n\tRTW_PRINT_SEL(sel, \"CONFIG_PCI_TX_POLLING\\n\");\n#endif\n#ifdef CONFIG_PCI_TX_POLLING_V2\n\tRTW_PRINT_SEL(sel, \"CONFIG_PCI_TX_POLLING_V2\\n\");\n#endif\n\n\tRTW_PRINT_SEL(sel, \"\\n=== XMIT-INFO ===\\n\");\n\tRTW_PRINT_SEL(sel, \"NR_XMITFRAME = %d\\n\", NR_XMITFRAME);\n\tRTW_PRINT_SEL(sel, \"NR_XMITBUFF = %d\\n\", NR_XMITBUFF);\n\tRTW_PRINT_SEL(sel, \"MAX_XMITBUF_SZ = %d\\n\", MAX_XMITBUF_SZ);\n\tRTW_PRINT_SEL(sel, \"NR_XMIT_EXTBUFF = %d\\n\", NR_XMIT_EXTBUFF);\n\tRTW_PRINT_SEL(sel, \"MAX_XMIT_EXTBUF_SZ = %d\\n\", MAX_XMIT_EXTBUF_SZ);\n\tRTW_PRINT_SEL(sel, \"MAX_CMDBUF_SZ = %d\\n\", MAX_CMDBUF_SZ);\n\n\tRTW_PRINT_SEL(sel, \"\\n=== RECV-INFO ===\\n\");\n\tRTW_PRINT_SEL(sel, \"NR_RECVFRAME = %d\\n\", NR_RECVFRAME);\n\tRTW_PRINT_SEL(sel, \"NR_RECVBUFF = %d\\n\", NR_RECVBUFF);\n\tRTW_PRINT_SEL(sel, \"MAX_RECVBUF_SZ = %d\\n\", MAX_RECVBUF_SZ);\n\n}\n\nvoid dump_log_level(void *sel)\n{\n#ifdef CONFIG_RTW_DEBUG\n\tint i;\n\n\tRTW_PRINT_SEL(sel, \"drv_log_level:%d\\n\", rtw_drv_log_level);\n\tfor (i = 0; i <= _DRV_MAX_; i++) {\n\t\tif (rtw_log_level_str[i])\n\t\t\tRTW_PRINT_SEL(sel, \"%c %s = %d\\n\",\n\t\t\t\t(rtw_drv_log_level == i) ? '+' : ' ', rtw_log_level_str[i], i);\n\t}\n#else\n\tRTW_PRINT_SEL(sel, \"CONFIG_RTW_DEBUG is disabled\\n\");\n#endif\n}\n\n#ifdef CONFIG_SDIO_HCI\nvoid sd_f0_reg_dump(void *sel, _adapter *adapter)\n{\n\tint i;\n\n\tfor (i = 0x0; i <= 0xff; i++) {\n\t\tif (i % 16 == 0)\n\t\t\tRTW_PRINT_SEL(sel, \"0x%02x \", i);\n\n\t\t_RTW_PRINT_SEL(sel, \"%02x \", rtw_sd_f0_read8(adapter, i));\n\n\t\tif (i % 16 == 15)\n\t\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t\telse if (i % 8 == 7)\n\t\t\t_RTW_PRINT_SEL(sel, \"\\t\");\n\t}\n}\n\nvoid sdio_local_reg_dump(void *sel, _adapter *adapter)\n{\n\tint i, j = 1;\n\n\tfor (i = 0x0; i < 0x100; i += 4) {\n\t\tif (j % 4 == 1)\n\t\t\tRTW_PRINT_SEL(sel, \"0x%02x\", i);\n\t\t_RTW_PRINT_SEL(sel, \" 0x%08x \", rtw_read32(adapter, (0x1025 << 16) | i));\n\t\tif ((j++) % 4 == 0)\n\t\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n}\n\n#ifdef CONFIG_SDIO_MONITOR\nu32 sd_monitor_sdio_clk(_adapter *adapter, u8 clk_moni_mode)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tu32 try_cnt = 0, clk_cnt = 0;\n\t\n\t/* switch to sdio clk monitor mode */\n\trtw_halmac_set_sdio_clk_monitor(dvobj, clk_moni_mode);\n\n\tdo {\n\t\tclk_cnt = rtw_halmac_sdio_get_lk_cnt(dvobj);\n\t\tif (clk_cnt > 0)\n\t\t\tbreak;\n\n\t\tif (try_cnt >= 100) {\n\t\t\tclk_cnt = 0;\n\t\t\tbreak;\n\t\t}\n\n\t\trtw_msleep_os(1);\n\t\ttry_cnt++;\n\t} while (1);\n\n\treturn clk_cnt;\n}\n#endif\n#endif /* CONFIG_SDIO_HCI */\n\nvoid mac_reg_dump(void *sel, _adapter *adapter)\n{\n\tint i, j = 1;\n\n\tRTW_PRINT_SEL(sel, \"======= MAC REG =======\\n\");\n\n\tfor (i = 0x0; i < 0x800; i += 4) {\n\t\tif (j % 4 == 1)\n\t\t\tRTW_PRINT_SEL(sel, \"0x%04x\", i);\n\t\t_RTW_PRINT_SEL(sel, \" 0x%08x \", rtw_read32(adapter, i));\n\t\tif ((j++) % 4 == 0)\n\t\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\n#ifdef CONFIG_RTL8814A\n\t{\n\t\tfor (i = 0x1000; i < 0x1650; i += 4) {\n\t\t\tif (j % 4 == 1)\n\t\t\t\tRTW_PRINT_SEL(sel, \"0x%04x\", i);\n\t\t\t_RTW_PRINT_SEL(sel, \" 0x%08x \", rtw_read32(adapter, i));\n\t\t\tif ((j++) % 4 == 0)\n\t\t\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t\t}\n\t}\n#endif /* CONFIG_RTL8814A */\n\n#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) ||defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822C)\n\tfor (i = 0x1000; i < 0x1800; i += 4) {\n\t\tif (j % 4 == 1)\n\t\t\tRTW_PRINT_SEL(sel, \"0x%04x\", i);\n\t\t_RTW_PRINT_SEL(sel, \" 0x%08x \", rtw_read32(adapter, i));\n\t\tif ((j++) % 4 == 0)\n\t\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n#endif /* CONFIG_RTL8822B  or 8821c or 8192f*/\n\n}\n\nvoid bb_reg_dump(void *sel, _adapter *adapter)\n{\n\tint i, j = 1;\n\n\tRTW_PRINT_SEL(sel, \"======= BB REG =======\\n\");\n\tfor (i = 0x800; i < 0x1000; i += 4) {\n\t\tif (j % 4 == 1)\n\t\t\tRTW_PRINT_SEL(sel, \"0x%04x\", i);\n\t\t_RTW_PRINT_SEL(sel, \" 0x%08x \", rtw_read32(adapter, i));\n\t\tif ((j++) % 4 == 0)\n\t\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\n#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)\n\tfor (i = 0x1800; i < 0x2000; i += 4) {\n\t\tif (j % 4 == 1)\n\t\t\tRTW_PRINT_SEL(sel, \"0x%04x\", i);\n\t\t_RTW_PRINT_SEL(sel, \" 0x%08x \", rtw_read32(adapter, i));\n\t\tif ((j++) % 4 == 0)\n\t\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n#endif /* CONFIG_RTL8822B */\n\n#if defined(CONFIG_RTL8822C)\n\tfor (i = 0x2c00; i < 0x2c60; i += 4) {\n\t\tif (j % 4 == 1)\n\t\t\tRTW_PRINT_SEL(sel, \"0x%04x\", i);\n\t\t_RTW_PRINT_SEL(sel, \" 0x%08x \", rtw_read32(adapter, i));\n\t\tif ((j++) % 4 == 0)\n\t\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\n\tfor (i = 0x2d00; i < 0x2df0; i += 4) {\n\t\tif (j % 4 == 1)\n\t\t\tRTW_PRINT_SEL(sel, \"0x%04x\", i);\n\t\t_RTW_PRINT_SEL(sel, \" 0x%08x \", rtw_read32(adapter, i));\n\t\tif ((j++) % 4 == 0)\n\t\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\t\n\n\tfor (i = 0x4000; i < 0x4060; i += 4) {\n\t\tif (j % 4 == 1)\n\t\t\tRTW_PRINT_SEL(sel, \"0x%04x\", i);\n\t\t_RTW_PRINT_SEL(sel, \" 0x%08x \", rtw_read32(adapter, i));\n\t\tif ((j++) % 4 == 0)\n\t\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\t\n\n\tfor (i = 0x4100; i < 0x4200; i += 4) {\n\t\tif (j % 4 == 1)\n\t\t\tRTW_PRINT_SEL(sel, \"0x%04x\", i);\n\t\t_RTW_PRINT_SEL(sel, \" 0x%08x \", rtw_read32(adapter, i));\n\t\tif ((j++) % 4 == 0)\n\t\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\t\n\n#endif /* CONFIG_RTL8822C */\n\n}\n\nvoid bb_reg_dump_ex(void *sel, _adapter *adapter)\n{\n\tint i;\n\n\tRTW_PRINT_SEL(sel, \"======= BB REG =======\\n\");\n\tfor (i = 0x800; i < 0x1000; i += 4) {\n\t\tRTW_PRINT_SEL(sel, \"0x%04x\", i);\n\t\t_RTW_PRINT_SEL(sel, \" 0x%08x \", rtw_read32(adapter, i));\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\n#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)\n\tfor (i = 0x1800; i < 0x2000; i += 4) {\n\t\tRTW_PRINT_SEL(sel, \"0x%04x\", i);\n\t\t_RTW_PRINT_SEL(sel, \" 0x%08x \", rtw_read32(adapter, i));\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n#endif /* CONFIG_RTL8822B */\n}\n\nvoid rf_reg_dump(void *sel, _adapter *adapter)\n{\n\tHAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);\n\tint i, j = 1, path;\n\tu32 value;\n\tu8 rf_type = 0;\n\tu8 path_nums = hal->NumTotalRFPath;\n\n\tRTW_PRINT_SEL(sel, \"======= RF REG =======\\n\");\n\n\tfor (path = 0; path < path_nums; path++) {\n\t\tRTW_PRINT_SEL(sel, \"RF_Path(%x)\\n\", path);\n\t\tfor (i = 0; i < 0x100; i++) {\n\t\t\tvalue = rtw_hal_read_rfreg(adapter, path, i, 0xffffffff);\n\t\t\tif (j % 4 == 1)\n\t\t\t\tRTW_PRINT_SEL(sel, \"0x%02x \", i);\n\t\t\t_RTW_PRINT_SEL(sel, \" 0x%08x \", value);\n\t\t\tif ((j++) % 4 == 0)\n\t\t\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t\t}\n\t}\n}\n\nvoid rtw_sink_rtp_seq_dbg(_adapter *adapter, u8 *ehdr_pos)\n{\n\tstruct recv_priv *precvpriv = &(adapter->recvpriv);\n\tif (precvpriv->sink_udpport > 0) {\n\t\tif (*((u16 *)(ehdr_pos + 0x24)) == cpu_to_be16(precvpriv->sink_udpport)) {\n\t\t\tprecvpriv->pre_rtp_rxseq = precvpriv->cur_rtp_rxseq;\n\t\t\tprecvpriv->cur_rtp_rxseq = be16_to_cpu(*((u16 *)(ehdr_pos + 0x2C)));\n\t\t\tif (precvpriv->pre_rtp_rxseq + 1 != precvpriv->cur_rtp_rxseq)\n\t\t\t\tRTW_INFO(\"%s : RTP Seq num from %d to %d\\n\", __FUNCTION__, precvpriv->pre_rtp_rxseq, precvpriv->cur_rtp_rxseq);\n\t\t}\n\t}\n}\n\nvoid sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta)\n{\n\tstruct recv_reorder_ctrl *reorder_ctl;\n\tint i;\n\n\tfor (i = 0; i < 16; i++) {\n\t\treorder_ctl = &sta->recvreorder_ctrl[i];\n\t\tif (reorder_ctl->ampdu_size != RX_AMPDU_SIZE_INVALID || reorder_ctl->indicate_seq != 0xFFFF) {\n\t\t\tRTW_PRINT_SEL(sel, \"tid=%d, enable=%d, ampdu_size=%u, indicate_seq=%u\\n\"\n\t\t\t\t, i, reorder_ctl->enable, reorder_ctl->ampdu_size, reorder_ctl->indicate_seq\n\t\t\t\t     );\n\t\t}\n\t}\n}\n\nvoid dump_tx_rate_bmp(void *sel, struct dvobj_priv *dvobj)\n{\n\t_adapter *adapter = dvobj_get_primary_adapter(dvobj);\n\tstruct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);\n\tu8 bw;\n\n\tRTW_PRINT_SEL(sel, \"%-6s\", \"bw\");\n\tif (hal_chk_proto_cap(adapter, PROTO_CAP_11AC))\n\t\t_RTW_PRINT_SEL(sel, \" %-11s\", \"vht\");\n\n\t_RTW_PRINT_SEL(sel, \" %-11s %-4s %-3s\\n\", \"ht\", \"ofdm\", \"cck\");\n\n\tfor (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) {\n\t\tif (!hal_is_bw_support(adapter, bw))\n\t\t\tcontinue;\n\n\t\tRTW_PRINT_SEL(sel, \"%6s\", ch_width_str(bw));\n\t\tif (hal_chk_proto_cap(adapter, PROTO_CAP_11AC)) {\n\t\t\t_RTW_PRINT_SEL(sel, \" %03x %03x %03x\"\n\t\t\t\t, RATE_BMP_GET_VHT_3SS(rfctl->rate_bmp_vht_by_bw[bw])\n\t\t\t\t, RATE_BMP_GET_VHT_2SS(rfctl->rate_bmp_vht_by_bw[bw])\n\t\t\t\t, RATE_BMP_GET_VHT_1SS(rfctl->rate_bmp_vht_by_bw[bw])\n\t\t\t);\n\t\t}\n\n\t\t_RTW_PRINT_SEL(sel, \" %02x %02x %02x %02x\"\n\t\t\t, bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_4SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0\n\t\t\t, bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_3SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0\n\t\t\t, bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_2SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0\n\t\t\t, bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_1SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0\n\t\t);\n\n\t\t_RTW_PRINT_SEL(sel, \"  %03x   %01x\\n\"\n\t\t\t, bw <= CHANNEL_WIDTH_20 ? RATE_BMP_GET_OFDM(rfctl->rate_bmp_cck_ofdm) : 0\n\t\t\t, bw <= CHANNEL_WIDTH_20 ? RATE_BMP_GET_CCK(rfctl->rate_bmp_cck_ofdm) : 0\n\t\t);\n\t}\n}\n\nvoid dump_adapters_status(void *sel, struct dvobj_priv *dvobj)\n{\n\tstruct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);\n\tint i;\n\t_adapter *iface;\n\tu8 u_ch, u_bw, u_offset;\n#if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG)\n\tchar str_val[64] = {'\\0'};\n#endif\n\tdump_mi_status(sel, dvobj);\n\n#if defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)\n\tRTW_PRINT_SEL(sel, \"[AP] LIMITED_AP_NUM:%d\\n\", CONFIG_LIMITED_AP_NUM);\n\tRTW_PRINT_SEL(sel, \"[AP] vap_map:0x%02x\\n\", dvobj->vap_map);\n#endif\n#ifdef CONFIG_HW_P0_TSF_SYNC\n\tRTW_PRINT_SEL(sel, \"[AP] p0 tsf sync port = %d\\n\", dvobj->p0_tsf.sync_port);\n\tRTW_PRINT_SEL(sel, \"[AP] p0 tsf timer offset = %d\\n\", dvobj->p0_tsf.offset);\n#endif\n#ifdef CONFIG_CLIENT_PORT_CFG\n\tRTW_PRINT_SEL(sel, \"[CLT] clt_num = %d\\n\", dvobj->clt_port.num);\n\tRTW_PRINT_SEL(sel, \"[CLT] clt_map = 0x%02x\\n\", dvobj->clt_port.bmp);\n#endif\n#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\tRTW_PRINT_SEL(sel, \"[MI] default port id:%d\\n\\n\", dvobj->dft.port_id);\n#endif /* CONFIG_FW_MULTI_PORT_SUPPORT */\n\n\tRTW_PRINT_SEL(sel, \"dev status:%s%s\\n\\n\"\n\t\t, dev_is_surprise_removed(dvobj) ? \" SR\" : \"\"\n\t\t, dev_is_drv_stopped(dvobj) ? \" DS\" : \"\"\n\t);\n\n#ifdef CONFIG_P2P\n#define P2P_INFO_TITLE_FMT\t\" %-3s %-4s\"\n#define P2P_INFO_TITLE_ARG\t, \"lch\", \"p2ps\"\n#ifdef CONFIG_IOCTL_CFG80211\n#define P2P_INFO_VALUE_FMT\t\" %3u %c%3u\"\n#define P2P_INFO_VALUE_ARG\t, iface->wdinfo.listen_channel, iface->wdev_data.p2p_enabled ? 'e' : ' ', rtw_p2p_state(&iface->wdinfo)\n#else\n#define P2P_INFO_VALUE_FMT\t\" %3u %4u\"\n#define P2P_INFO_VALUE_ARG\t, iface->wdinfo.listen_channel, rtw_p2p_state(&iface->wdinfo)\n#endif\n#define P2P_INFO_DASH\t\t\"---------\"\n#else\n#define P2P_INFO_TITLE_FMT\t\"\"\n#define P2P_INFO_TITLE_ARG\n#define P2P_INFO_VALUE_FMT\t\"\"\n#define P2P_INFO_VALUE_ARG\n#define P2P_INFO_DASH\n#endif\n\n#ifdef DBG_TSF_UPDATE\n#define TSF_PAUSE_TIME_TITLE_FMT \" %-5s\"\n#define TSF_PAUSE_TIME_TITLE_ARG , \"tsfup\"\n#define TSF_PAUSE_TIME_VALUE_FMT \" %5d\"\n#define TSF_PAUSE_TIME_VALUE_ARG , ((iface->mlmeextpriv.tsf_update_required && iface->mlmeextpriv.tsf_update_pause_stime) ? (rtw_get_passing_time_ms(iface->mlmeextpriv.tsf_update_pause_stime) > 99999 ? 99999 : rtw_get_passing_time_ms(iface->mlmeextpriv.tsf_update_pause_stime)) : 0)\n#else\n#define TSF_PAUSE_TIME_TITLE_FMT \"\"\n#define TSF_PAUSE_TIME_TITLE_ARG\n#define TSF_PAUSE_TIME_VALUE_FMT \"\"\n#define TSF_PAUSE_TIME_VALUE_ARG\n#endif\n\n#if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG)\n#define INFO_FMT\t\" %-4s\"\n#define INFO_ARG\t, \"info\"\n#define INFO_CNT_FMT\t\" %-20s\"\n#define INFO_CNT_ARG\t, str_val\n#else\n#define INFO_FMT\t\"\"\n#define INFO_ARG\n#define INFO_CNT_FMT\t\"\"\n#define INFO_CNT_ARG\n#endif\n\n\tRTW_PRINT_SEL(sel, \"%-2s %-15s %c %-3s %-3s %-3s %-17s %-4s %-7s\"\n\t\tP2P_INFO_TITLE_FMT\n\t\tTSF_PAUSE_TIME_TITLE_FMT\n\t\t\" %s\"INFO_FMT\"\\n\"\n\t\t, \"id\", \"ifname\", ' ', \"bup\", \"nup\", \"ncd\", \"macaddr\", \"port\", \"ch\"\n\t\tP2P_INFO_TITLE_ARG\n\t\tTSF_PAUSE_TIME_TITLE_ARG\n\t\t, \"status\"INFO_ARG);\n\n\tRTW_PRINT_SEL(sel, \"---------------------------------------------------------------\"\n\t\tP2P_INFO_DASH\n\t\t\"-------\\n\");\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface) {\n\t\t\t#if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG)\n\t\t\t_rtw_memset(&str_val, '\\0', sizeof(str_val));\n\t\t\t#endif\n\t\t\t#if defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)\n\t\t\tif (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) {\n\t\t\t\tu8 len;\n\t\t\t\tchar *p = str_val;\n\t\t\t\tchar tmp_str[10] = {'\\0'};\n\n\t\t\t\tlen = snprintf(tmp_str, sizeof(tmp_str), \"%s\", \"ap_id:\");\n\t\t\t\tstrncpy(p, tmp_str, len);\n\t\t\t\tp += len;\n\t\t\t\t_rtw_memset(&tmp_str, '\\0', sizeof(tmp_str));\n\t\t\t\t#ifdef DBG_HW_PORT\n\t\t\t\tlen = snprintf(tmp_str, sizeof(tmp_str), \"%d (%d,%d)\", iface->vap_id, iface->hw_port, iface->client_port);\n\t\t\t\t#else\n\t\t\t\tlen = snprintf(tmp_str, sizeof(tmp_str), \"%d\", iface->vap_id);\n\t\t\t\t#endif\n\t\t\t\tstrncpy(p, tmp_str, len);\n\t\t\t}\n\t\t\t#endif\n\t\t\t#ifdef CONFIG_CLIENT_PORT_CFG\n\t\t\tif (MLME_IS_STA(iface)) {\n\t\t\t\tu8 len;\n\t\t\t\tchar *p = str_val;\n\t\t\t\tchar tmp_str[10] = {'\\0'};\n\n\t\t\t\tlen = snprintf(tmp_str, sizeof(tmp_str), \"%s\", \"c_pid:\");\n\t\t\t\tstrncpy(p, tmp_str, len);\n\t\t\t\tp += len;\n\t\t\t\t_rtw_memset(&tmp_str, '\\0', sizeof(tmp_str));\n\t\t\t\t#ifdef DBG_HW_PORT\n\t\t\t\tlen = snprintf(tmp_str, sizeof(tmp_str), \"%d (%d,%d)\", iface->client_port, iface->hw_port, iface->client_port);\n\t\t\t\t#else\n\t\t\t\tlen = snprintf(tmp_str, sizeof(tmp_str), \"%d\", iface->client_port);\n\t\t\t\t#endif\n\t\t\t\tstrncpy(p, tmp_str, len);\n\t\t\t}\n\t\t\t#endif\n\n\t\t\tRTW_PRINT_SEL(sel, \"%2d %-15s %c %3u %3u %3u \"MAC_FMT\" %4hhu %3u,%u,%u\"\n\t\t\t\tP2P_INFO_VALUE_FMT\n\t\t\t\tTSF_PAUSE_TIME_VALUE_FMT\n\t\t\t\t\" \"MLME_STATE_FMT\" \" INFO_CNT_FMT\"\\n\"\n\t\t\t\t, i, iface->registered ? ADPT_ARG(iface) : NULL\n\t\t\t\t, iface->registered ? 'R' : ' '\n\t\t\t\t, iface->bup\n\t\t\t\t, iface->netif_up\n\t\t\t\t, iface->net_closed\n\t\t\t\t, MAC_ARG(adapter_mac_addr(iface))\n\t\t\t\t, rtw_hal_get_port(iface)\n\t\t\t\t, iface->mlmeextpriv.cur_channel\n\t\t\t\t, iface->mlmeextpriv.cur_bwmode\n\t\t\t\t, iface->mlmeextpriv.cur_ch_offset\n\t\t\t\tP2P_INFO_VALUE_ARG\n\t\t\t\tTSF_PAUSE_TIME_VALUE_ARG\n\t\t\t\t, MLME_STATE_ARG(iface)\n\t\t\t\tINFO_CNT_ARG\n\t\t\t);\n\t\t}\n\t}\n\n\tRTW_PRINT_SEL(sel, \"---------------------------------------------------------------\"\n\t\tP2P_INFO_DASH\n\t\t\"-------\\n\");\n\n\trtw_mi_get_ch_setting_union(dvobj_get_primary_adapter(dvobj), &u_ch, &u_bw, &u_offset);\n\tRTW_PRINT_SEL(sel, \"%55s %3u,%u,%u\\n\"\n\t\t, \"union:\"\n\t\t, u_ch, u_bw, u_offset\n\t);\n\n\tRTW_PRINT_SEL(sel, \"%55s %3u,%u,%u offch_state:%d\\n\"\n\t\t, \"oper:\"\n\t\t, dvobj->oper_channel\n\t\t, dvobj->oper_bwmode\n\t\t, dvobj->oper_ch_offset\n\t\t, rfctl->offch_state\n\t);\n\n#ifdef CONFIG_DFS_MASTER\n\tif (rfctl->radar_detect_ch != 0) {\n\t\tRTW_PRINT_SEL(sel, \"%55s %3u,%u,%u\"\n\t\t\t, \"radar_detect:\"\n\t\t\t, rfctl->radar_detect_ch\n\t\t\t, rfctl->radar_detect_bw\n\t\t\t, rfctl->radar_detect_offset\n\t\t);\n\n\t\tif (rfctl->radar_detect_by_others)\n\t\t\t_RTW_PRINT_SEL(sel, \", by AP of STA link\");\n\t\telse {\n\t\t\tu32 non_ocp_ms;\n\t\t\tu32 cac_ms;\n\t\t\tu8 dfs_domain = rtw_odm_get_dfs_domain(dvobj);\n\n\t\t\t_RTW_PRINT_SEL(sel, \", domain:%u\", dfs_domain);\n\n\t\t\trtw_get_ch_waiting_ms(rfctl\n\t\t\t\t, rfctl->radar_detect_ch\n\t\t\t\t, rfctl->radar_detect_bw\n\t\t\t\t, rfctl->radar_detect_offset\n\t\t\t\t, &non_ocp_ms\n\t\t\t\t, &cac_ms\n\t\t\t);\n\n\t\t\tif (non_ocp_ms)\n\t\t\t\t_RTW_PRINT_SEL(sel, \", non_ocp:%d\", non_ocp_ms);\n\t\t\tif (cac_ms)\n\t\t\t\t_RTW_PRINT_SEL(sel, \", cac:%d\", cac_ms);\n\t\t}\n\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n#endif /* CONFIG_DFS_MASTER */\n}\n\n#define SEC_CAM_ENT_ID_TITLE_FMT \"%-2s\"\n#define SEC_CAM_ENT_ID_TITLE_ARG \"id\"\n#define SEC_CAM_ENT_ID_VALUE_FMT \"%2u\"\n#define SEC_CAM_ENT_ID_VALUE_ARG(id) (id)\n\n#define SEC_CAM_ENT_TITLE_FMT \"%-6s %-17s %-32s %-3s %-7s %-2s %-2s %-5s\"\n#define SEC_CAM_ENT_TITLE_ARG \"ctrl\", \"addr\", \"key\", \"kid\", \"type\", \"MK\", \"GK\", \"valid\"\n#define SEC_CAM_ENT_VALUE_FMT \"0x%04x \"MAC_FMT\" \"KEY_FMT\" %3u %-7s %2u %2u %5u\"\n#define SEC_CAM_ENT_VALUE_ARG(ent) \\\n\t(ent)->ctrl \\\n\t, MAC_ARG((ent)->mac) \\\n\t, KEY_ARG((ent)->key) \\\n\t, ((ent)->ctrl) & 0x03 \\\n\t, security_type_str((((ent)->ctrl) >> 2) & 0x07) \\\n\t, (((ent)->ctrl) >> 5) & 0x01 \\\n\t, (((ent)->ctrl) >> 6) & 0x01 \\\n\t, (((ent)->ctrl) >> 15) & 0x01\n\nvoid dump_sec_cam_ent(void *sel, struct sec_cam_ent *ent, int id)\n{\n\tif (id >= 0) {\n\t\tRTW_PRINT_SEL(sel, SEC_CAM_ENT_ID_VALUE_FMT \" \" SEC_CAM_ENT_VALUE_FMT\"\\n\"\n\t\t\t, SEC_CAM_ENT_ID_VALUE_ARG(id), SEC_CAM_ENT_VALUE_ARG(ent));\n\t} else\n\t\tRTW_PRINT_SEL(sel, SEC_CAM_ENT_VALUE_FMT\"\\n\", SEC_CAM_ENT_VALUE_ARG(ent));\n}\n\nvoid dump_sec_cam_ent_title(void *sel, u8 has_id)\n{\n\tif (has_id) {\n\t\tRTW_PRINT_SEL(sel, SEC_CAM_ENT_ID_TITLE_FMT \" \" SEC_CAM_ENT_TITLE_FMT\"\\n\"\n\t\t\t, SEC_CAM_ENT_ID_TITLE_ARG, SEC_CAM_ENT_TITLE_ARG);\n\t} else\n\t\tRTW_PRINT_SEL(sel, SEC_CAM_ENT_TITLE_FMT\"\\n\", SEC_CAM_ENT_TITLE_ARG);\n}\n\nvoid dump_sec_cam(void *sel, _adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\tstruct sec_cam_ent ent;\n\tint i;\n\n\tRTW_PRINT_SEL(sel, \"HW sec cam:\\n\");\n\tdump_sec_cam_ent_title(sel, 1);\n\tfor (i = 0; i < cam_ctl->num; i++) {\n\t\trtw_sec_read_cam_ent(adapter, i, (u8 *)(&ent.ctrl), ent.mac, ent.key);\n\t\tdump_sec_cam_ent(sel , &ent, i);\n\t}\n}\n\nvoid dump_sec_cam_cache(void *sel, _adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\tint i;\n\n\tRTW_PRINT_SEL(sel, \"SW sec cam cache:\\n\");\n\tdump_sec_cam_ent_title(sel, 1);\n\tfor (i = 0; i < cam_ctl->num; i++) {\n\t\tif (dvobj->cam_cache[i].ctrl != 0)\n\t\t\tdump_sec_cam_ent(sel, &dvobj->cam_cache[i], i);\n\t}\n\n}\n\nstatic u8 fwdl_test_chksum_fail = 0;\nstatic u8 fwdl_test_wintint_rdy_fail = 0;\n\nbool rtw_fwdl_test_trigger_chksum_fail(void)\n{\n\tif (fwdl_test_chksum_fail) {\n\t\tRTW_PRINT(\"fwdl test case: trigger chksum_fail\\n\");\n\t\tfwdl_test_chksum_fail--;\n\t\treturn _TRUE;\n\t}\n\treturn _FALSE;\n}\n\nbool rtw_fwdl_test_trigger_wintint_rdy_fail(void)\n{\n\tif (fwdl_test_wintint_rdy_fail) {\n\t\tRTW_PRINT(\"fwdl test case: trigger wintint_rdy_fail\\n\");\n\t\tfwdl_test_wintint_rdy_fail--;\n\t\treturn _TRUE;\n\t}\n\treturn _FALSE;\n}\n\nstatic u8 del_rx_ampdu_test_no_tx_fail = 0;\n\nbool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void)\n{\n\tif (del_rx_ampdu_test_no_tx_fail) {\n\t\tRTW_PRINT(\"del_rx_ampdu test case: trigger no_tx_fail\\n\");\n\t\tdel_rx_ampdu_test_no_tx_fail--;\n\t\treturn _TRUE;\n\t}\n\treturn _FALSE;\n}\n\nstatic u32 g_wait_hiq_empty_ms = 0;\n\nu32 rtw_get_wait_hiq_empty_ms(void)\n{\n\treturn g_wait_hiq_empty_ms;\n}\n\nstatic systime sta_linking_test_start_time = 0;\nstatic u32 sta_linking_test_wait_ms = 0;\nstatic u8 sta_linking_test_force_fail = 0;\n\nvoid rtw_sta_linking_test_set_start(void)\n{\n\tsta_linking_test_start_time = rtw_get_current_time();\n}\n\nbool rtw_sta_linking_test_wait_done(void)\n{\n\treturn rtw_get_passing_time_ms(sta_linking_test_start_time) >= sta_linking_test_wait_ms;\n}\n\nbool rtw_sta_linking_test_force_fail(void)\n{\n\treturn sta_linking_test_force_fail;\n}\n\n#ifdef CONFIG_AP_MODE\nstatic u16 ap_linking_test_force_auth_fail = 0;\nstatic u16 ap_linking_test_force_asoc_fail = 0;\n\nu16 rtw_ap_linking_test_force_auth_fail(void)\n{\n\treturn ap_linking_test_force_auth_fail;\n}\n\nu16 rtw_ap_linking_test_force_asoc_fail(void)\n{\n\treturn ap_linking_test_force_asoc_fail;\n}\n#endif\n\n#ifdef CONFIG_PROC_DEBUG\nssize_t proc_set_write_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu32 addr, val, len;\n\n\tif (count < 3) {\n\t\tRTW_INFO(\"argument size is less than 3\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%x %x %x\", &addr, &val, &len);\n\n\t\tif (num !=  3) {\n\t\t\tRTW_INFO(\"invalid write_reg parameter!\\n\");\n\t\t\treturn count;\n\t\t}\n\n\t\tswitch (len) {\n\t\tcase 1:\n\t\t\trtw_write8(padapter, addr, (u8)val);\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\trtw_write16(padapter, addr, (u16)val);\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\trtw_write32(padapter, addr, val);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tRTW_INFO(\"error write length=%d\", len);\n\t\t\tbreak;\n\t\t}\n\n\t}\n\n\treturn count;\n\n}\n\nstatic u32 proc_get_read_addr = 0xeeeeeeee;\nstatic u32 proc_get_read_len = 0x4;\n\nint proc_get_read_reg(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (proc_get_read_addr == 0xeeeeeeee) {\n\t\tRTW_PRINT_SEL(m, \"address not initialized\\n\");\n\t\treturn 0;\n\t}\n\n\tswitch (proc_get_read_len) {\n\tcase 1:\n\t\tRTW_PRINT_SEL(m, \"rtw_read8(0x%x)=0x%x\\n\", proc_get_read_addr, rtw_read8(padapter, proc_get_read_addr));\n\t\tbreak;\n\tcase 2:\n\t\tRTW_PRINT_SEL(m, \"rtw_read16(0x%x)=0x%x\\n\", proc_get_read_addr, rtw_read16(padapter, proc_get_read_addr));\n\t\tbreak;\n\tcase 4:\n\t\tRTW_PRINT_SEL(m, \"rtw_read32(0x%x)=0x%x\\n\", proc_get_read_addr, rtw_read32(padapter, proc_get_read_addr));\n\t\tbreak;\n\tdefault:\n\t\tRTW_PRINT_SEL(m, \"error read length=%d\\n\", proc_get_read_len);\n\t\tbreak;\n\t}\n\n\treturn 0;\n}\n\nssize_t proc_set_read_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tchar tmp[16];\n\tu32 addr, len;\n\n\tif (count < 2) {\n\t\tRTW_INFO(\"argument size is less than 2\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%x %x\", &addr, &len);\n\n\t\tif (num !=  2) {\n\t\t\tRTW_INFO(\"invalid read_reg parameter!\\n\");\n\t\t\treturn count;\n\t\t}\n\n\t\tproc_get_read_addr = addr;\n\n\t\tproc_get_read_len = len;\n\t}\n\n\treturn count;\n\n}\n\nint proc_get_rx_stat(struct seq_file *m, void *v)\n{\n\t_irqL\t irqL;\n\t_list\t*plist, *phead;\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct sta_info *psta = NULL;\n\tstruct stainfo_stats\t*pstats = NULL;\n\tstruct sta_priv\t\t*pstapriv = &(adapter->stapriv);\n\tu32 i, j;\n\tu8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tu8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};\n\n\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\tfor (i = 0; i < NUM_STA; i++) {\n\t\tphead = &(pstapriv->sta_hash[i]);\n\t\tplist = get_next(phead);\n\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\t\t\tplist = get_next(plist);\n\t\t\tpstats = &psta->sta_stats;\n\n\t\t\tif (pstats == NULL)\n\t\t\t\tcontinue;\n\t\t\tif ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) !=  _TRUE)\n\t\t\t\t&& (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE)\n\t\t\t\t&& (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) {\n\t\t\t\tRTW_PRINT_SEL(m, \"MAC :\\t\\t\"MAC_FMT \"\\n\", MAC_ARG(psta->cmn.mac_addr));\n\t\t\t\tRTW_PRINT_SEL(m, \"data_rx_cnt :\\t%llu\\n\", sta_rx_data_uc_pkts(psta) - pstats->last_rx_data_uc_pkts);\n\t\t\t\tpstats->last_rx_data_uc_pkts = sta_rx_data_uc_pkts(psta);\n\t\t\t\tRTW_PRINT_SEL(m, \"duplicate_cnt :\\t%u\\n\", pstats->duplicate_cnt);\n\t\t\t\tpstats->duplicate_cnt = 0;\n\t\t\t\tRTW_PRINT_SEL(m, \"rx_per_rate_cnt :\\n\");\n\n\t\t\t\tfor (j = 0; j < 0x60; j++) {\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%08u  \", pstats->rxratecnt[j]);\n\t\t\t\t\tpstats->rxratecnt[j] = 0;\n\t\t\t\t\tif ((j%8) == 7)\n\t\t\t\t\t\tRTW_PRINT_SEL(m, \"\\n\");\n\t\t\t\t}\n\t\t\t\tRTW_PRINT_SEL(m, \"\\n\");\n\t\t\t}\n\t\t}\n\t}\n\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\treturn 0;\n}\n\nint proc_get_tx_stat(struct seq_file *m, void *v)\n{\n\t_irqL\tirqL;\n\t_list\t*plist, *phead;\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct sta_info *psta = NULL;\n\tu8 sta_mac[NUM_STA][ETH_ALEN] = {{0}};\n\tuint mac_id[NUM_STA];\n\tstruct stainfo_stats\t*pstats = NULL;\n\tstruct sta_priv\t*pstapriv = &(adapter->stapriv);\n\tstruct sta_priv\t*pstapriv_primary = &(GET_PRIMARY_ADAPTER(adapter))->stapriv;\n\tu32 i, macid_rec_idx = 0;\n\tu8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tu8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};\n\tstruct submit_ctx gotc2h;\n\n\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\tfor (i = 0; i < NUM_STA; i++) {\n\t\tphead = &(pstapriv->sta_hash[i]);\n\t\tplist = get_next(phead);\n\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\t\t\tplist = get_next(plist);\n\t\t\tif ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) !=  _TRUE)\n\t\t\t\t&& (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE)\n\t\t\t\t&& (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) {\n\t\t\t\t_rtw_memcpy(&sta_mac[macid_rec_idx][0], psta->cmn.mac_addr, ETH_ALEN);\n\t\t\t\tmac_id[macid_rec_idx] = psta->cmn.mac_id;\n\t\t\t\tmacid_rec_idx++;\n\t\t\t}\n\t\t}\n\t}\n\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\tfor (i = 0; i < macid_rec_idx; i++) {\n\t\t_rtw_memcpy(pstapriv_primary->c2h_sta_mac, &sta_mac[i][0], ETH_ALEN);\n\t\tpstapriv_primary->c2h_adapter_id = adapter->iface_id;\n\t\trtw_sctx_init(&gotc2h, 60);\n\t\tpstapriv_primary->gotc2h = &gotc2h;\n\t\trtw_hal_reqtxrpt(adapter, mac_id[i]);\n\t\tif (rtw_sctx_wait(&gotc2h, __func__)) {\n\t\t\tpsta = rtw_get_stainfo(pstapriv, &sta_mac[i][0]);\n\t\t\tif(psta) {\n\t\t\t\tpstats = &psta->sta_stats;\n#ifndef ROKU_PRIVATE\n\t\t\t\tRTW_PRINT_SEL(m, \"data_sent_cnt :\\t%u\\n\", pstats->tx_ok_cnt + pstats->tx_fail_cnt);\n\t\t\t\tRTW_PRINT_SEL(m, \"success_cnt :\\t%u\\n\", pstats->tx_ok_cnt);\n\t\t\t\tRTW_PRINT_SEL(m, \"failure_cnt :\\t%u\\n\", pstats->tx_fail_cnt);\n\t\t\t\tRTW_PRINT_SEL(m, \"retry_cnt :\\t%u\\n\\n\", pstats->tx_retry_cnt);\n#else\n\t\t\t\tRTW_PRINT_SEL(m, \"MAC: \" MAC_FMT \" sent: %u fail: %u retry: %u\\n\",\n\t\t\t\tMAC_ARG(&sta_mac[i][0]), pstats->tx_ok_cnt, pstats->tx_fail_cnt, pstats->tx_retry_cnt);\n#endif /* ROKU_PRIVATE */\n\n\t\t\t} else\n\t\t\t\tRTW_PRINT_SEL(m, \"STA is gone\\n\");\n\t\t} else {\n\t\t\t//to avoid c2h modify counters\n\t\t\tpstapriv_primary->gotc2h = NULL;\n\t\t\t_rtw_memset(pstapriv_primary->c2h_sta_mac, 0, ETH_ALEN);\n\t\t\tpstapriv_primary->c2h_adapter_id = CONFIG_IFACE_NUMBER;\n\t\t\tRTW_PRINT_SEL(m, \"Warming : Query timeout, operation abort!!\\n\");\n\t\t\tbreak;\n\t\t}\n\t\tpstapriv_primary->gotc2h = NULL;\n\t\t_rtw_memset(pstapriv_primary->c2h_sta_mac, 0, ETH_ALEN);\n\t\tpstapriv_primary->c2h_adapter_id = CONFIG_IFACE_NUMBER;\n\t}\n\treturn 0;\n}\n\nint proc_get_fwstate(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\tRTW_PRINT_SEL(m, \"fwstate=0x%x\\n\", get_fwstate(pmlmepriv));\n\n\treturn 0;\n}\n\nint proc_get_sec_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct security_priv *sec = &padapter->securitypriv;\n\n\tRTW_PRINT_SEL(m, \"auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\\n\",\n\t\tsec->dot11AuthAlgrthm, sec->dot11PrivacyAlgrthm,\n\t\tsec->ndisauthtype, sec->ndisencryptstatus);\n\n\tRTW_PRINT_SEL(m, \"hw_decrypted=%d\\n\", sec->hw_decrypted);\n\n#ifdef DBG_SW_SEC_CNT\n\tRTW_PRINT_SEL(m, \"wep_sw_enc_cnt=%llu, %llu, %llu\\n\"\n\t\t, sec->wep_sw_enc_cnt_bc , sec->wep_sw_enc_cnt_mc, sec->wep_sw_enc_cnt_uc);\n\tRTW_PRINT_SEL(m, \"wep_sw_dec_cnt=%llu, %llu, %llu\\n\"\n\t\t, sec->wep_sw_dec_cnt_bc , sec->wep_sw_dec_cnt_mc, sec->wep_sw_dec_cnt_uc);\n\n\tRTW_PRINT_SEL(m, \"tkip_sw_enc_cnt=%llu, %llu, %llu\\n\"\n\t\t, sec->tkip_sw_enc_cnt_bc , sec->tkip_sw_enc_cnt_mc, sec->tkip_sw_enc_cnt_uc);\n\tRTW_PRINT_SEL(m, \"tkip_sw_dec_cnt=%llu, %llu, %llu\\n\"\n\t\t, sec->tkip_sw_dec_cnt_bc , sec->tkip_sw_dec_cnt_mc, sec->tkip_sw_dec_cnt_uc);\n\n\tRTW_PRINT_SEL(m, \"aes_sw_enc_cnt=%llu, %llu, %llu\\n\"\n\t\t, sec->aes_sw_enc_cnt_bc , sec->aes_sw_enc_cnt_mc, sec->aes_sw_enc_cnt_uc);\n\tRTW_PRINT_SEL(m, \"aes_sw_dec_cnt=%llu, %llu, %llu\\n\"\n\t\t, sec->aes_sw_dec_cnt_bc , sec->aes_sw_dec_cnt_mc, sec->aes_sw_dec_cnt_uc);\n#endif /* DBG_SW_SEC_CNT */\n\n\treturn 0;\n}\n\nint proc_get_mlmext_state(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tRTW_PRINT_SEL(m, \"pmlmeinfo->state=0x%x\\n\", pmlmeinfo->state);\n\n\treturn 0;\n}\n\n#ifdef CONFIG_LAYER2_ROAMING\nint proc_get_roam_flags(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_PRINT_SEL(m, \"0x%02x\\n\", rtw_roam_flags(adapter));\n\n\treturn 0;\n}\n\nssize_t proc_set_roam_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tchar tmp[32];\n\tu8 flags;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhx\", &flags);\n\n\t\tif (num == 1)\n\t\t\trtw_assign_roam_flags(adapter, flags);\n\t}\n\n\treturn count;\n\n}\n\nint proc_get_roam_param(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\n\tRTW_PRINT_SEL(m, \"%12s %15s %26s %16s\\n\", \"rssi_diff_th\", \"scanr_exp_ms\", \"scan_interval(unit:2 sec)\", \"rssi_threshold\");\n\tRTW_PRINT_SEL(m, \"%-15u %-13u %-27u %-11u\\n\"\n\t\t, mlme->roam_rssi_diff_th\n\t\t, mlme->roam_scanr_exp_ms\n\t\t, mlme->roam_scan_int\n\t\t, mlme->roam_rssi_threshold\n\t);\n\n\treturn 0;\n}\n\nssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\n\tchar tmp[32];\n\tu8 rssi_diff_th;\n\tu32 scanr_exp_ms;\n\tu32 scan_int;\n\tu8 rssi_threshold;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhu %u %u %hhu\", &rssi_diff_th, &scanr_exp_ms, &scan_int, &rssi_threshold);\n\n\t\tif (num >= 1)\n\t\t\tmlme->roam_rssi_diff_th = rssi_diff_th;\n\t\tif (num >= 2)\n\t\t\tmlme->roam_scanr_exp_ms = scanr_exp_ms;\n\t\tif (num >= 3)\n\t\t\tmlme->roam_scan_int = scan_int;\n\t\tif (num >= 4)\n\t\t\tmlme->roam_rssi_threshold = rssi_threshold;\n\t}\n\n\treturn count;\n\n}\n\nssize_t proc_set_roam_tgt_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tchar tmp[32];\n\tu8 addr[ETH_ALEN];\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhx:%hhx:%hhx:%hhx:%hhx:%hhx\", addr, addr + 1, addr + 2, addr + 3, addr + 4, addr + 5);\n\t\tif (num == 6)\n\t\t\t_rtw_memcpy(adapter->mlmepriv.roam_tgt_addr, addr, ETH_ALEN);\n\n\t\tRTW_INFO(\"set roam_tgt_addr to \"MAC_FMT\"\\n\", MAC_ARG(adapter->mlmepriv.roam_tgt_addr));\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_LAYER2_ROAMING */\n\n#ifdef CONFIG_RTW_80211R\nssize_t proc_set_ft_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tchar tmp[32];\n\tu8 flags;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%hhx\", &flags);\n\n\t\tif (num == 1)\n\t\t\tadapter->mlmepriv.ft_roam.ft_flags = flags;\n\t}\n\n\treturn count;\n\n}\n\nint proc_get_ft_flags(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_PRINT_SEL(m, \"0x%02x\\n\", adapter->mlmepriv.ft_roam.ft_flags);\n\n\treturn 0;\n}\n#endif\n\nint proc_get_qos_option(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\tRTW_PRINT_SEL(m, \"qos_option=%d\\n\", pmlmepriv->qospriv.qos_option);\n\n\treturn 0;\n}\n\nint proc_get_ht_option(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n#ifdef CONFIG_80211N_HT\n\tRTW_PRINT_SEL(m, \"ht_option=%d\\n\", pmlmepriv->htpriv.ht_option);\n#endif /* CONFIG_80211N_HT */\n\n\treturn 0;\n}\n\nint proc_get_rf_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\n\tRTW_PRINT_SEL(m, \"cur_ch=%d, cur_bw=%d, cur_ch_offet=%d\\n\",\n\t\tpmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);\n\n\tRTW_PRINT_SEL(m, \"oper_ch=%d, oper_bw=%d, oper_ch_offet=%d\\n\",\n\t\trtw_get_oper_ch(padapter), rtw_get_oper_bw(padapter),  rtw_get_oper_choffset(padapter));\n\n\treturn 0;\n}\n\nint proc_get_scan_param(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\tstruct ss_res *ss = &mlmeext->sitesurvey_res;\n\n#define SCAN_PARAM_TITLE_FMT \"%10s\"\n#define SCAN_PARAM_VALUE_FMT \"%-10u\"\n#define SCAN_PARAM_TITLE_ARG , \"scan_ch_ms\"\n#define SCAN_PARAM_VALUE_ARG , ss->scan_ch_ms\n#ifdef CONFIG_80211N_HT\n#define SCAN_PARAM_TITLE_FMT_HT \" %15s %13s\"\n#define SCAN_PARAM_VALUE_FMT_HT \" %-15u %-13u\"\n#define SCAN_PARAM_TITLE_ARG_HT , \"rx_ampdu_accept\", \"rx_ampdu_size\"\n#define SCAN_PARAM_VALUE_ARG_HT , ss->rx_ampdu_accept, ss->rx_ampdu_size\n#else\n#define SCAN_PARAM_TITLE_FMT_HT \"\"\n#define SCAN_PARAM_VALUE_FMT_HT \"\"\n#define SCAN_PARAM_TITLE_ARG_HT\n#define SCAN_PARAM_VALUE_ARG_HT\n#endif\n#ifdef CONFIG_SCAN_BACKOP\n#define SCAN_PARAM_TITLE_FMT_BACKOP \" %9s %12s\"\n#define SCAN_PARAM_VALUE_FMT_BACKOP \" %-9u %-12u\"\n#define SCAN_PARAM_TITLE_ARG_BACKOP , \"backop_ms\", \"scan_cnt_max\"\n#define SCAN_PARAM_VALUE_ARG_BACKOP , ss->backop_ms, ss->scan_cnt_max\n#else\n#define SCAN_PARAM_TITLE_FMT_BACKOP \"\"\n#define SCAN_PARAM_VALUE_FMT_BACKOP \"\"\n#define SCAN_PARAM_TITLE_ARG_BACKOP\n#define SCAN_PARAM_VALUE_ARG_BACKOP\n#endif\n\n\tRTW_PRINT_SEL(m,\n\t\tSCAN_PARAM_TITLE_FMT\n\t\tSCAN_PARAM_TITLE_FMT_HT\n\t\tSCAN_PARAM_TITLE_FMT_BACKOP\n\t\t\"\\n\"\n\t\tSCAN_PARAM_TITLE_ARG\n\t\tSCAN_PARAM_TITLE_ARG_HT\n\t\tSCAN_PARAM_TITLE_ARG_BACKOP\n\t);\n\n\tRTW_PRINT_SEL(m,\n\t\tSCAN_PARAM_VALUE_FMT\n\t\tSCAN_PARAM_VALUE_FMT_HT\n\t\tSCAN_PARAM_VALUE_FMT_BACKOP\n\t\t\"\\n\"\n\t\tSCAN_PARAM_VALUE_ARG\n\t\tSCAN_PARAM_VALUE_ARG_HT\n\t\tSCAN_PARAM_VALUE_ARG_BACKOP\n\t);\n\n\treturn 0;\n}\n\nssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\tstruct ss_res *ss = &mlmeext->sitesurvey_res;\n\n\tchar tmp[32] = {0};\n\n\tu16 scan_ch_ms;\n#define SCAN_PARAM_INPUT_FMT \"%hu\"\n#define SCAN_PARAM_INPUT_ARG , &scan_ch_ms\n#ifdef CONFIG_80211N_HT\n\tu8 rx_ampdu_accept;\n\tu8 rx_ampdu_size;\n#define SCAN_PARAM_INPUT_FMT_HT \" %hhu %hhu\"\n#define SCAN_PARAM_INPUT_ARG_HT , &rx_ampdu_accept, &rx_ampdu_size\n#else\n#define SCAN_PARAM_INPUT_FMT_HT \"\"\n#define SCAN_PARAM_INPUT_ARG_HT\n#endif\n#ifdef CONFIG_SCAN_BACKOP\n\tu16 backop_ms;\n\tu8 scan_cnt_max;\n#define SCAN_PARAM_INPUT_FMT_BACKOP \" %hu %hhu\"\n#define SCAN_PARAM_INPUT_ARG_BACKOP , &backop_ms, &scan_cnt_max\n#else\n#define SCAN_PARAM_INPUT_FMT_BACKOP \"\"\n#define SCAN_PARAM_INPUT_ARG_BACKOP\n#endif\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp,\n\t\t\tSCAN_PARAM_INPUT_FMT\n\t\t\tSCAN_PARAM_INPUT_FMT_HT\n\t\t\tSCAN_PARAM_INPUT_FMT_BACKOP\n\t\t\tSCAN_PARAM_INPUT_ARG\n\t\t\tSCAN_PARAM_INPUT_ARG_HT\n\t\t\tSCAN_PARAM_INPUT_ARG_BACKOP\n\t\t);\n\n\t\tif (num-- > 0)\n\t\t\tss->scan_ch_ms = scan_ch_ms;\n#ifdef CONFIG_80211N_HT\n\t\tif (num-- > 0)\n\t\t\tss->rx_ampdu_accept = rx_ampdu_accept;\n\t\tif (num-- > 0)\n\t\t\tss->rx_ampdu_size = rx_ampdu_size;\n#endif\n#ifdef CONFIG_SCAN_BACKOP\n\t\tif (num-- > 0)\n\t\t\tss->backop_ms = backop_ms;\n\t\tif (num-- > 0)\n\t\t\tss->scan_cnt_max = scan_cnt_max;\n#endif\n\t}\n\n\treturn count;\n}\n\nint proc_get_scan_abort(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tu32 pass_ms;\n\n\tpass_ms = rtw_scan_abort_timeout(adapter, 10000);\n\n\tRTW_PRINT_SEL(m, \"%u\\n\", pass_ms);\n\n\treturn 0;\n}\n\n#ifdef CONFIG_RTW_REPEATER_SON\nint proc_get_rson_data(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar rson_data_str[256];\n\n\trtw_rson_get_property_str(padapter, rson_data_str);\n\tRTW_PRINT_SEL(m, \"%s\\n\", rson_data_str);\n\treturn 0;\n}\n\nssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);\n\tchar tmp[64] = {0};\n\tint num;\n\tu8 field[10], value[64];\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tnum = sscanf(tmp, \"%s %s\", field, value);\n\t\tif (num != 2) {\n\t\t\tRTW_INFO(\"Invalid format : echo <field> <value> > son_data\\n\");\n\t\t\treturn count;\n\t\t}\n\t\tRTW_INFO(\"field=%s  value=%s\\n\", field, value);\n\t\tnum = rtw_rson_set_property(padapter, field, value);\n\t\tif (num != 1) {\n\t\t\tRTW_INFO(\"Invalid field(%s) or value(%s)\\n\", field, value);\n\t\t\treturn count;\n\t\t}\n\t}\n\treturn count;\n}\n#endif /*CONFIG_RTW_REPEATER_SON*/\n\nint proc_get_survey_info(struct seq_file *m, void *v)\n{\n\t_irqL irqL;\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\t_queue\t*queue\t= &(pmlmepriv->scanned_queue);\n\tstruct wlan_network\t*pnetwork = NULL;\n\t_list\t*plist, *phead;\n\ts32 notify_signal;\n\ts16 notify_noise = 0;\n\tu16  index = 0, ie_cap = 0;\n\tunsigned char *ie_wpa = NULL, *ie_wpa2 = NULL, *ie_wps = NULL;\n\tunsigned char *ie_p2p = NULL, *ssid = NULL;\n\tchar flag_str[64];\n\tint ielen = 0;\n\tu32 wpsielen = 0;\n#ifdef CONFIG_RTW_MESH\n\tconst char *ssid_title_str = \"ssid/mesh_id\";\n#else\n\tconst char *ssid_title_str = \"ssid\";\n#endif\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\tphead = get_list_head(queue);\n\tif (!phead)\n\t\tgoto _exit;\n\tplist = get_next(phead);\n\tif (!plist)\n\t\tgoto _exit;\n\n#ifdef CONFIG_RTW_REPEATER_SON\n\trtw_rson_show_survey_info(m, plist, phead);\n#else\n\n\tRTW_PRINT_SEL(m, \"%5s  %-17s  %3s  %-3s  %-4s  %-4s  %5s  %32s  %32s\\n\", \"index\", \"bssid\", \"ch\", \"RSSI\", \"SdBm\", \"Noise\", \"age\", \"flag\", ssid_title_str);\n\twhile (1) {\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\t\tif (!pnetwork)\n\t\t\tbreak;\n\n\t\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE &&\n\t\t    is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) {\n\t\t\tnotify_signal = translate_percentage_to_dbm(padapter->recvpriv.signal_strength);/* dbm */\n\t\t} else {\n\t\t\tnotify_signal = translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength);/* dbm */\n\t\t}\n\n#ifdef CONFIG_BACKGROUND_NOISE_MONITOR\n\t\tif (IS_NM_ENABLE(padapter))\n\t\t\tnotify_noise = rtw_noise_query_by_chan_num(padapter, pnetwork->network.Configuration.DSConfig);\n#endif\n\n\t\tie_wpa = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &ielen, pnetwork->network.IELength - 12);\n\t\tie_wpa2 = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &ielen, pnetwork->network.IELength - 12);\n\t\tie_cap = rtw_get_capability(&pnetwork->network);\n\t\tie_wps = rtw_get_wps_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &wpsielen);\n\t\tie_p2p = rtw_get_p2p_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &ielen);\n\t\tssid = pnetwork->network.Ssid.Ssid;\n\t\tsprintf(flag_str, \"%s%s%s%s%s%s%s\",\n\t\t\t(ie_wpa) ? \"[WPA]\" : \"\",\n\t\t\t(ie_wpa2) ? \"[WPA2]\" : \"\",\n\t\t\t(!ie_wpa && !ie_wpa && ie_cap & BIT(4)) ? \"[WEP]\" : \"\",\n\t\t\t(ie_wps) ? \"[WPS]\" : \"\",\n\t\t\t(pnetwork->network.InfrastructureMode == Ndis802_11IBSS) ? \"[IBSS]\" :\n\t\t\t\t(pnetwork->network.InfrastructureMode == Ndis802_11_mesh) ? \"[MESH]\" : \"\",\n\t\t\t(ie_cap & BIT(0)) ? \"[ESS]\" : \"\",\n\t\t\t(ie_p2p) ? \"[P2P]\" : \"\");\n\t\tRTW_PRINT_SEL(m, \"%5d  \"MAC_FMT\"  %3d  %3d  %4d  %4d    %5d  %32s  %32s\\n\",\n\t\t\t++index,\n\t\t\tMAC_ARG(pnetwork->network.MacAddress),\n\t\t\tpnetwork->network.Configuration.DSConfig,\n\t\t\t(int)pnetwork->network.Rssi,\n\t\t\tnotify_signal,\n\t\t\tnotify_noise,\n\t\t\trtw_get_passing_time_ms(pnetwork->last_scanned),\n\t\t\tflag_str,\n\t\t\tpnetwork->network.InfrastructureMode == Ndis802_11_mesh ? pnetwork->network.mesh_id.Ssid : pnetwork->network.Ssid.Ssid\n\t\t);\n\t\tplist = get_next(plist);\n\t}\n#endif\n_exit:\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\treturn 0;\n}\n\nssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8 _status = _FALSE;\n\tu8 ssc_chk;\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n#if 1\n\tssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);\n\tif (ssc_chk != SS_ALLOW)\n\t\tgoto exit;\n\n\trtw_ps_deny(padapter, PS_DENY_SCAN);\n\tif (_FAIL == rtw_pwr_wakeup(padapter))\n\t\tgoto cancel_ps_deny;\n\tif (!rtw_is_adapter_up(padapter)) {\n\t\tRTW_INFO(\"scan abort!! adapter cannot use\\n\");\n\t\tgoto cancel_ps_deny;\n\t}\n#else\n#ifdef CONFIG_MP_INCLUDED\n\tif (rtw_mp_mode_check(padapter)) {\n\t\tRTW_INFO(\"MP mode block Scan request\\n\");\n\t\tgoto exit;\n\t}\n#endif\n\tif (rtw_is_scan_deny(padapter)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT  \": scan deny\\n\", FUNC_ADPT_ARG(padapter));\n\t\tgoto exit;\n\t}\n\n\trtw_ps_deny(padapter, PS_DENY_SCAN);\n\tif (_FAIL == rtw_pwr_wakeup(padapter))\n\t\tgoto cancel_ps_deny;\n\n\tif (!rtw_is_adapter_up(padapter)) {\n\t\tRTW_INFO(\"scan abort!! adapter cannot use\\n\");\n\t\tgoto cancel_ps_deny;\n\t}\n\n\tif (rtw_mi_busy_traffic_check(padapter, _FALSE)) {\n\t\tRTW_INFO(\"scan abort!! BusyTraffic == _TRUE\\n\");\n\t\tgoto cancel_ps_deny;\n\t}\n\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {\n\t\tRTW_INFO(\"scan abort!! AP mode process WPS\\n\");\n\t\tgoto cancel_ps_deny;\n\t}\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) {\n\t\tRTW_INFO(\"scan abort!! fwstate=0x%x\\n\", pmlmepriv->fw_state);\n\t\tgoto cancel_ps_deny;\n\t}\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_buddy_check_fwstate(padapter,\n\t\t       _FW_UNDER_SURVEY | _FW_UNDER_LINKING | WIFI_UNDER_WPS)) {\n\t\tRTW_INFO(\"scan abort!! buddy_fwstate check failed\\n\");\n\t\tgoto cancel_ps_deny;\n\t}\n#endif\n#endif\n\t_status = rtw_set_802_11_bssid_list_scan(padapter, NULL);\n\ncancel_ps_deny:\n\trtw_ps_deny_cancel(padapter, PS_DENY_SCAN);\nexit:\n\treturn count;\n}\n#ifdef ROKU_PRIVATE\nint proc_get_infra_ap(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\tstruct sta_info *psta;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct ht_priv_infra_ap *phtpriv = &pmlmepriv->htpriv_infra_ap;\n#ifdef CONFIG_80211AC_VHT\n\tstruct vht_priv_infra_ap *pvhtpriv = &pmlmepriv->vhtpriv_infra_ap;\n#endif\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct wlan_network *cur_network = &(pmlmepriv->cur_network);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {\n\t\tpsta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);\n\t\tif (psta) {\n\t\t\tunsigned int i, j;\n\t\t\tunsigned int Rx_ss = 0, Tx_ss = 0;\n\t\t\tstruct recv_reorder_ctrl *preorder_ctrl;\n\n\t\t\tRTW_PRINT_SEL(m, \"SSID=%s\\n\", pmlmeinfo->network.Ssid.Ssid);\n\t\t\tRTW_PRINT_SEL(m, \"sta's macaddr:\" MAC_FMT \"\\n\", MAC_ARG(psta->cmn.mac_addr));\n\t\t\tRTW_PRINT_SEL(m, \"Supported rate=\");\n\t\t\tfor (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {\n\t\t\t\tif (pmlmeinfo->SupportedRates_infra_ap[i] == 0)\n\t\t\t\t\tbreak;\n\t\t\t\tRTW_PRINT_SEL(m, \" 0x%x\", pmlmeinfo->SupportedRates_infra_ap[i]);\n\t\t\t}\n\t\t\tRTW_PRINT_SEL(m, \"\\n\");\n#ifdef CONFIG_80211N_HT\n\t\t\tif (pmlmeinfo->ht_vht_received & BIT(0)) {\n\t\t\t\tRTW_PRINT_SEL(m, \"Supported MCS set=\");\n\t\t\t\tfor (i = 0; i < 16 ; i++)\n\t\t\t\t\tRTW_PRINT_SEL(m, \" 0x%02x\",  phtpriv->MCS_set_infra_ap[i]);\n\t\t\t\tRTW_PRINT_SEL(m, \"\\n\");\n\t\t\t\tRTW_PRINT_SEL(m, \"highest supported data rate=0x%x\\n\", phtpriv->rx_highest_data_rate_infra_ap);\n\t\t\t\tRTW_PRINT_SEL(m, \"HT_supported_channel_width_set=0x%x\\n\", phtpriv->channel_width_infra_ap);\n\t\t\t\tRTW_PRINT_SEL(m, \"sgi_20m=%d, sgi_40m=%d\\n\", phtpriv->sgi_20m_infra_ap, phtpriv->sgi_40m_infra_ap);\n\t\t\t\tRTW_PRINT_SEL(m, \"ldpc_cap=0x%x, stbc_cap=0x%x\\n\", phtpriv->ldpc_cap_infra_ap, phtpriv->stbc_cap_infra_ap);\n\t\t\t\tRTW_PRINT_SEL(m, \"HT_number_of_stream=%d\\n\", phtpriv->Rx_ss_infra_ap);\n\t\t\t}\n#endif\n\n#ifdef CONFIG_80211AC_VHT\n\t\t\tif (pmlmeinfo->ht_vht_received & BIT(1)) {\n\t\t\t\tRTW_PRINT_SEL(m, \"VHT_supported_channel_width_set=0x%x\\n\", pvhtpriv->channel_width_infra_ap);\n\t\t\t\tRTW_PRINT_SEL(m, \"vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\\n\", pvhtpriv->ldpc_cap_infra_ap, pvhtpriv->stbc_cap_infra_ap, pvhtpriv->beamform_cap_infra_ap);\n\t\t\t\tRTW_PRINT_SEL(m, \"Rx_vht_mcs_map=0x%x, Tx_vht_mcs_map=0x%x\\n\", *(u16 *)pvhtpriv->vht_mcs_map_infra_ap, *(u16 *)pvhtpriv->vht_mcs_map_tx_infra_ap);\n\t\t\t\tRTW_PRINT_SEL(m, \"VHT_number_of_stream=%d\\n\", pvhtpriv->number_of_streams_infra_ap);\n\t\t\t}\n#endif\n\t\t} else\n\t\t\tRTW_PRINT_SEL(m, \"can't get sta's macaddr, cur_network's macaddr:\" MAC_FMT \"\\n\", MAC_ARG(cur_network->network.MacAddress));\n\t} else\n\t\tRTW_PRINT_SEL(m, \"this only applies to STA mode\\n\");\n\treturn 0;\n}\n\n#endif /* ROKU_PRIVATE */\n\nint proc_get_ap_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\tstruct sta_info *psta;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct wlan_network *cur_network = &(pmlmepriv->cur_network);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\t/* ap vendor */\n\tchar vendor[VENDOR_NAME_LEN] = {0};\n\tget_assoc_AP_Vendor(vendor,pmlmeinfo->assoc_AP_vendor);\n\tRTW_PRINT_SEL(m,\"AP Vendor %s\\n\", vendor);\n\n\tpsta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);\n\tif (psta) {\n\t\tRTW_PRINT_SEL(m, \"SSID=%s\\n\", cur_network->network.Ssid.Ssid);\n\t\tRTW_PRINT_SEL(m, \"sta's macaddr:\" MAC_FMT \"\\n\", MAC_ARG(psta->cmn.mac_addr));\n\t\tRTW_PRINT_SEL(m, \"cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\\n\", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);\n\t\tRTW_PRINT_SEL(m, \"wireless_mode=0x%x, rtsen=%d, cts2slef=%d\\n\", psta->wireless_mode, psta->rtsen, psta->cts2self);\n\t\tRTW_PRINT_SEL(m, \"state=0x%x, aid=%d, macid=%d, raid=%d\\n\",\n\t\t\tpsta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);\n#ifdef CONFIG_80211N_HT\n\t\tRTW_PRINT_SEL(m, \"qos_en=%d, ht_en=%d, init_rate=%d\\n\", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);\n\t\tRTW_PRINT_SEL(m, \"bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\\n\"\n\t\t\t, psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m);\n\t\tRTW_PRINT_SEL(m, \"ampdu_enable = %d\\n\", psta->htpriv.ampdu_enable);\n\t\tRTW_PRINT_SEL(m, \"agg_enable_bitmap=%x, candidate_tid_bitmap=%x\\n\", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);\n\t\tRTW_PRINT_SEL(m, \"ldpc_cap=0x%x, stbc_cap=0x%x, beamform_cap=0x%x\\n\", psta->htpriv.ldpc_cap, psta->htpriv.stbc_cap, psta->htpriv.beamform_cap);\n#endif /* CONFIG_80211N_HT */\n#ifdef CONFIG_80211AC_VHT\n\t\tRTW_PRINT_SEL(m, \"vht_en=%d, vht_sgi_80m=%d\\n\", psta->vhtpriv.vht_option, psta->vhtpriv.sgi_80m);\n\t\tRTW_PRINT_SEL(m, \"vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\\n\", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap);\n\t\tRTW_PRINT_SEL(m, \"vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\\n\", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len);\n#endif\n\t\tsta_rx_reorder_ctl_dump(m, psta);\n\t} else\n\t\tRTW_PRINT_SEL(m, \"can't get sta's macaddr, cur_network's macaddr:\" MAC_FMT \"\\n\", MAC_ARG(cur_network->network.MacAddress));\n\n\treturn 0;\n}\n\nssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct recv_priv  *precvpriv = &padapter->recvpriv;\n\tchar cmd[32] = {0};\n\tu8 cnt = 0;\n\n\tif (count > sizeof(cmd)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(cmd, buffer, count)) {\n\t\tint num = sscanf(cmd, \"%hhx\", &cnt);\n\n\t\tif (num == 1 && cnt == 0) {\n\t\t\tprecvpriv->dbg_rx_ampdu_drop_count = 0;\n\t\t\tprecvpriv->dbg_rx_ampdu_forced_indicate_count = 0;\n\t\t\tprecvpriv->dbg_rx_ampdu_loss_count = 0;\n\t\t\tprecvpriv->dbg_rx_dup_mgt_frame_drop_count = 0;\n\t\t\tprecvpriv->dbg_rx_ampdu_window_shift_cnt = 0;\n\t\t\tprecvpriv->dbg_rx_conflic_mac_addr_cnt = 0;\n\t\t\tprecvpriv->dbg_rx_drop_count = 0;\n\t\t}\n\t}\n\n\treturn count;\n}\n\nint proc_get_trx_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\tint i;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tstruct recv_priv  *precvpriv = &padapter->recvpriv;\n\tstruct hw_xmit *phwxmit;\n\tu16 vo_params[4], vi_params[4], be_params[4], bk_params[4];\n\n\tpadapter->hal_func.read_wmmedca_reg(padapter, vo_params, vi_params, be_params, bk_params);\n\n\tRTW_PRINT_SEL(m, \"wmm_edca_vo, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\\n\", vo_params[0], vo_params[1], vo_params[2], vo_params[3]);\n\tRTW_PRINT_SEL(m, \"wmm_edca_vi, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\\n\", vi_params[0], vi_params[1], vi_params[2], vi_params[3]);\n\tRTW_PRINT_SEL(m, \"wmm_edca_be, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\\n\", be_params[0], be_params[1], be_params[2], be_params[3]);\n\tRTW_PRINT_SEL(m, \"wmm_edca_bk, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\\n\", bk_params[0], bk_params[1], bk_params[2], bk_params[3]);\n\n\tdump_os_queue(m, padapter);\n\n\tRTW_PRINT_SEL(m, \"free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d\\n\"\n\t\t, pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt);\n\tRTW_PRINT_SEL(m, \"free_ext_xmitbuf_cnt=%d, free_xframe_ext_cnt=%d\\n\"\n\t\t, pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt);\n\tRTW_PRINT_SEL(m, \"free_recvframe_cnt=%d\\n\"\n\t\t      , precvpriv->free_recvframe_cnt);\n\n\tfor (i = 0; i < 4; i++) {\n\t\tphwxmit = pxmitpriv->hwxmits + i;\n\t\tRTW_PRINT_SEL(m, \"%d, hwq.accnt=%d\\n\", i, phwxmit->accnt);\n\t}\n\n\trtw_hal_get_hwreg(padapter, HW_VAR_DUMP_MAC_TXFIFO, (u8 *)m);\n\n#ifdef CONFIG_USB_HCI\n\tRTW_PRINT_SEL(m, \"rx_urb_pending_cn=%d\\n\", ATOMIC_READ(&(precvpriv->rx_pending_cnt)));\n#endif\n\n\tdump_rx_bh_tk(m, &GET_PRIMARY_ADAPTER(padapter)->recvpriv);\n\n\t/* Folowing are RX info */\n\tRTW_PRINT_SEL(m, \"RX: Count of Packets dropped by Driver: %llu\\n\", (unsigned long long)precvpriv->dbg_rx_drop_count);\n\t/* Counts of packets whose seq_num is less than preorder_ctrl->indicate_seq, Ex delay, retransmission, redundant packets and so on */\n\tRTW_PRINT_SEL(m, \"Rx: Counts of Packets Whose Seq_Num Less Than Reorder Control Seq_Num: %llu\\n\", (unsigned long long)precvpriv->dbg_rx_ampdu_drop_count);\n\t/* How many times the Rx Reorder Timer is triggered. */\n\tRTW_PRINT_SEL(m, \"Rx: Reorder Time-out Trigger Counts: %llu\\n\", (unsigned long long)precvpriv->dbg_rx_ampdu_forced_indicate_count);\n\t/* Total counts of packets loss */\n\tRTW_PRINT_SEL(m, \"Rx: Packet Loss Counts: %llu\\n\", (unsigned long long)precvpriv->dbg_rx_ampdu_loss_count);\n\tRTW_PRINT_SEL(m, \"Rx: Duplicate Management Frame Drop Count: %llu\\n\", (unsigned long long)precvpriv->dbg_rx_dup_mgt_frame_drop_count);\n\tRTW_PRINT_SEL(m, \"Rx: AMPDU BA window shift Count: %llu\\n\", (unsigned long long)precvpriv->dbg_rx_ampdu_window_shift_cnt);\n\t/*The same mac addr counts*/\n\tRTW_PRINT_SEL(m, \"Rx: Conflict MAC Address Frames Count: %llu\\n\", (unsigned long long)precvpriv->dbg_rx_conflic_mac_addr_cnt);\n\treturn 0;\n}\n\nint proc_get_rate_ctl(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8 data_rate = 0, sgi = 0, data_fb = 0;\n\n\tif (adapter->fix_rate != 0xff) {\n\t\tdata_rate = adapter->fix_rate & 0x7F;\n\t\tsgi = adapter->fix_rate >> 7;\n\t\tdata_fb = adapter->data_fb ? 1 : 0;\n\t\tRTW_PRINT_SEL(m, \"FIXED %s%s%s\\n\"\n\t\t\t, HDATA_RATE(data_rate)\n\t\t\t, data_rate > DESC_RATE54M ? (sgi ? \" SGI\" : \" LGI\") : \"\"\n\t\t\t, data_fb ? \" FB\" : \"\"\n\t\t);\n\t\tRTW_PRINT_SEL(m, \"0x%02x %u\\n\", adapter->fix_rate, adapter->data_fb);\n\t} else\n\t\tRTW_PRINT_SEL(m, \"RA\\n\");\n\n\treturn 0;\n}\n\n#ifdef \tCONFIG_PHDYM_FW_FIXRATE\nvoid phydm_fw_fix_rate(void *dm_void, u8 en, u8\tmacid, u8 bw, u8 rate);\n#endif\nssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tchar tmp[32];\n\tu8 fix_rate = 0xFF;\n#ifdef \tCONFIG_PHDYM_FW_FIXRATE\n\tu8 bw = 0;\n#else\n\tu8 data_fb = 0;\n#endif\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n#ifdef \tCONFIG_PHDYM_FW_FIXRATE\n\t\tstruct dm_struct *dm = adapter_to_phydm(adapter);\n\t\tu8 en = 1, macid = 255;\n\t\t_irqL\tirqL;\n\t\t_list\t*plist, *phead;\n\t\tstruct sta_info *psta = NULL;\n\t\tstruct sta_priv\t*pstapriv = &(adapter->stapriv);\n\t\tu8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\t\tu8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};\n\t\tuint mac_id[NUM_STA];\n\t\tint i, macid_rec_idx = 0;\n\t\tint num = sscanf(tmp, \"%hhx %hhu %hhu\", &fix_rate, &bw, &macid);\n\n\t\tif (num < 1) {\n\t\t\tRTW_INFO(\"Invalid input!! \\\"ex: echo <rate> <bw> <macid> > /proc/.../rate_ctl\\\"\\n\");\n\t\t\treturn count;\n\t\t}\n\n\t\tif ((fix_rate == 0) || (fix_rate == 0xFF))\n\t\t\ten = 0;\n\t\t\t\n\t\tif (macid != 255) {\n\t\t\tRTW_INFO(\"Call phydm_fw_fix_rate()--en[%d] mac_id[%d] bw[%d] fix_rate[%d]\\n\", en, macid, bw, fix_rate);\n\t\t\tphydm_fw_fix_rate(dm, en, macid, bw, fix_rate);\n\t\t\treturn count;\n\t\t}\n\n\t\t/*\tno specific macid, apply to all macids except bc/mc macid */\n\t\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\t\tfor (i = 0; i < NUM_STA; i++) {\n\t\t\tphead = &(pstapriv->sta_hash[i]);\n\t\t\tplist = get_next(phead);\n\t\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\t\t\t\tplist = get_next(plist);\n\t\t\t\tif ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) !=  _TRUE)\n\t\t\t\t\t&& (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE)\n\t\t\t\t\t&& (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) {\n\t\t\t\t\t\tmac_id[macid_rec_idx] = psta->cmn.mac_id;\n\t\t\t\t\t\tmacid_rec_idx++;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\t\tfor (i = 0; i < macid_rec_idx; i++) {\n\t\t\tRTW_INFO(\"Call phydm_fw_fix_rate()--en[%d] mac_id[%d] bw[%d] fix_rate[%d]\\n\", en, mac_id[i], bw, fix_rate);\n\t\t\tphydm_fw_fix_rate(dm, en, mac_id[i], bw, fix_rate);\n\t\t}\n#else\n\t\tint num = sscanf(tmp, \"%hhx %hhu\", &fix_rate, &data_fb);\n\n\t\tif (num >= 1) {\n\t\t\tu8 fix_rate_ori = adapter->fix_rate;\n\n\t\t\tadapter->fix_rate = fix_rate;\n\t\t\tif (fix_rate == 0xFF)\n\t\t\t\thal_data->ForcedDataRate = 0;\n\t\t\telse\n\t\t\t\thal_data->ForcedDataRate = hw_rate_to_m_rate(fix_rate & 0x7F);\n\n\t\t\tif (adapter->fix_bw != 0xFF && fix_rate_ori != fix_rate)\n\t\t\t\trtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));\n\t\t}\n\t\tif (num >= 2)\n\t\t\tadapter->data_fb = data_fb ? 1 : 0;\n#endif\n\t}\n\n\treturn count;\n}\n\n#ifdef CONFIG_AP_MODE\nint proc_get_bmc_tx_rate(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (!MLME_IS_AP(adapter) && !MLME_IS_MESH(adapter)) {\n\t\tRTW_PRINT_SEL(m, \"[ERROR] Not in SoftAP/Mesh mode !!\\n\");\n\t\treturn 0;\n\t}\n\n\tRTW_PRINT_SEL(m, \" BMC Tx rate - %s\\n\", MGN_RATE_STR(adapter->bmc_tx_rate));\n\treturn 0;\n}\n\nssize_t proc_set_bmc_tx_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu8 bmc_tx_rate;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhx\", &bmc_tx_rate);\n\n\t\tif (num >= 1)\n\t\t\t/*adapter->bmc_tx_rate = hw_rate_to_m_rate(bmc_tx_rate);*/\n\t\t\tadapter->bmc_tx_rate = bmc_tx_rate;\n\t}\n\n\treturn count;\n}\n#endif /*CONFIG_AP_MODE*/\n\n\nint proc_get_tx_power_offset(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_PRINT_SEL(m, \"Tx power offset - %u\\n\", adapter->power_offset);\n\treturn 0;\n}\n\nssize_t proc_set_tx_power_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu8 power_offset = 0;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhu\", &power_offset);\n\n\t\tif (num >= 1) {\n\t\t\tif (power_offset > 5)\n\t\t\t\tpower_offset = 0;\n\n\t\t\tadapter->power_offset = power_offset;\n\t\t}\n\t}\n\n\treturn count;\n}\n\nint proc_get_bw_ctl(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8 data_bw = 0;\n\n\tif (adapter->fix_bw != 0xff) {\n\t\tdata_bw = adapter->fix_bw;\n\t\tRTW_PRINT_SEL(m, \"FIXED %s\\n\", ch_width_str(data_bw));\n\t} else\n\t\tRTW_PRINT_SEL(m, \"Auto\\n\");\n\n\treturn 0;\n}\n\nssize_t proc_set_bw_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu8 fix_bw;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%hhu\", &fix_bw);\n\n\t\tif (num >= 1) {\n\t\t\tu8 fix_bw_ori = adapter->fix_bw;\n\n\t\t\tadapter->fix_bw = fix_bw;\n\n\t\t\tif (adapter->fix_rate != 0xFF && fix_bw_ori != fix_bw)\n\t\t\t\trtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));\n\t\t}\n\t}\n\n\treturn count;\n}\n\n#ifdef DBG_RX_COUNTER_DUMP\nint proc_get_rx_cnt_dump(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\tint i;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_PRINT_SEL(m, \"BIT0- Dump RX counters of DRV\\n\");\n\tRTW_PRINT_SEL(m, \"BIT1- Dump RX counters of MAC\\n\");\n\tRTW_PRINT_SEL(m, \"BIT2- Dump RX counters of PHY\\n\");\n\tRTW_PRINT_SEL(m, \"BIT3- Dump TRX data frame of DRV\\n\");\n\tRTW_PRINT_SEL(m, \"dump_rx_cnt_mode = 0x%02x\\n\", adapter->dump_rx_cnt_mode);\n\n\treturn 0;\n}\nssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu8 dump_rx_cnt_mode;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhx\", &dump_rx_cnt_mode);\n\n\t\tif (num == 1) {\n\t\t\trtw_dump_phy_rxcnts_preprocess(adapter, dump_rx_cnt_mode);\n\t\t\tadapter->dump_rx_cnt_mode = dump_rx_cnt_mode;\n\t\t}\n\t}\n\n\treturn count;\n}\n#endif\n\nssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tchar tmp[32];\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count))\n\t\tsscanf(tmp, \"%hhu %hhu\", &fwdl_test_chksum_fail, &fwdl_test_wintint_rdy_fail);\n\n\treturn count;\n}\n\nssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tchar tmp[32];\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count))\n\t\tsscanf(tmp, \"%hhu\", &del_rx_ampdu_test_no_tx_fail);\n\n\treturn count;\n}\n\nssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tchar tmp[32];\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count))\n\t\tsscanf(tmp, \"%u\", &g_wait_hiq_empty_ms);\n\n\treturn count;\n}\n\nssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tchar tmp[32];\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tu32 wait_ms = 0;\n\t\tu8 force_fail = 0;\n\t\tint num = sscanf(tmp, \"%u %hhu\", &wait_ms, &force_fail);\n\n\t\tif (num >= 1)\n\t\t\tsta_linking_test_wait_ms = wait_ms;\n\t\tif (num >= 2)\n\t\t\tsta_linking_test_force_fail = force_fail;\n\t}\n\n\treturn count;\n}\n\n#ifdef CONFIG_AP_MODE\nssize_t proc_set_ap_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tchar tmp[32];\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tu16 force_auth_fail = 0;\n\t\tu16 force_asoc_fail = 0;\n\t\tint num = sscanf(tmp, \"%hu %hu\", &force_auth_fail, &force_asoc_fail);\n\n\t\tif (num >= 1)\n\t\t\tap_linking_test_force_auth_fail = force_auth_fail;\n\t\tif (num >= 2)\n\t\t\tap_linking_test_force_asoc_fail = force_asoc_fail;\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_AP_MODE */\n\nint proc_get_ps_dbg_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = padapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &dvobj->drv_dbg;\n\n\tRTW_PRINT_SEL(m, \"dbg_sdio_alloc_irq_cnt=%d\\n\", pdbgpriv->dbg_sdio_alloc_irq_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_sdio_free_irq_cnt=%d\\n\", pdbgpriv->dbg_sdio_free_irq_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_sdio_alloc_irq_error_cnt=%d\\n\", pdbgpriv->dbg_sdio_alloc_irq_error_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_sdio_free_irq_error_cnt=%d\\n\", pdbgpriv->dbg_sdio_free_irq_error_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_sdio_init_error_cnt=%d\\n\", pdbgpriv->dbg_sdio_init_error_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_sdio_deinit_error_cnt=%d\\n\", pdbgpriv->dbg_sdio_deinit_error_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_suspend_error_cnt=%d\\n\", pdbgpriv->dbg_suspend_error_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_suspend_cnt=%d\\n\", pdbgpriv->dbg_suspend_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_resume_cnt=%d\\n\", pdbgpriv->dbg_resume_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_resume_error_cnt=%d\\n\", pdbgpriv->dbg_resume_error_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_deinit_fail_cnt=%d\\n\", pdbgpriv->dbg_deinit_fail_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_carddisable_cnt=%d\\n\", pdbgpriv->dbg_carddisable_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_ps_insuspend_cnt=%d\\n\", pdbgpriv->dbg_ps_insuspend_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_dev_unload_inIPS_cnt=%d\\n\", pdbgpriv->dbg_dev_unload_inIPS_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_scan_pwr_state_cnt=%d\\n\", pdbgpriv->dbg_scan_pwr_state_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_downloadfw_pwr_state_cnt=%d\\n\", pdbgpriv->dbg_downloadfw_pwr_state_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_carddisable_error_cnt=%d\\n\", pdbgpriv->dbg_carddisable_error_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_fw_read_ps_state_fail_cnt=%d\\n\", pdbgpriv->dbg_fw_read_ps_state_fail_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_leave_ips_fail_cnt=%d\\n\", pdbgpriv->dbg_leave_ips_fail_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_leave_lps_fail_cnt=%d\\n\", pdbgpriv->dbg_leave_lps_fail_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_h2c_leave32k_fail_cnt=%d\\n\", pdbgpriv->dbg_h2c_leave32k_fail_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_diswow_dload_fw_fail_cnt=%d\\n\", pdbgpriv->dbg_diswow_dload_fw_fail_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_enwow_dload_fw_fail_cnt=%d\\n\", pdbgpriv->dbg_enwow_dload_fw_fail_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_ips_drvopen_fail_cnt=%d\\n\", pdbgpriv->dbg_ips_drvopen_fail_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_poll_fail_cnt=%d\\n\", pdbgpriv->dbg_poll_fail_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_rpwm_toogle_cnt=%d\\n\", pdbgpriv->dbg_rpwm_toogle_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_rpwm_timeout_fail_cnt=%d\\n\", pdbgpriv->dbg_rpwm_timeout_fail_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_sreset_cnt=%d\\n\", pdbgpriv->dbg_sreset_cnt);\n\tRTW_PRINT_SEL(m, \"dbg_fw_mem_dl_error_cnt=%d\\n\", pdbgpriv->dbg_fw_mem_dl_error_cnt);\n\n\treturn 0;\n}\nssize_t proc_set_ps_dbg_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = adapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &dvobj->drv_dbg;\n\tchar tmp[32];\n\tu8 ps_dbg_cmd_id;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhx\", &ps_dbg_cmd_id);\n\n\t\tif (num == 1 && ps_dbg_cmd_id == 1) /*Clean all*/\n\t\t\t_rtw_memset(pdbgpriv, 0, sizeof(struct debug_priv));\n\n\t}\n\n\treturn count;\n}\n\n\n#ifdef CONFIG_DBG_COUNTER\n\nint proc_get_rx_logs(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rx_logs *rx_logs = &padapter->rx_logs;\n\n\tRTW_PRINT_SEL(m,\n\t\t      \"intf_rx=%d\\n\"\n\t\t      \"intf_rx_err_recvframe=%d\\n\"\n\t\t      \"intf_rx_err_skb=%d\\n\"\n\t\t      \"intf_rx_report=%d\\n\"\n\t\t      \"core_rx=%d\\n\"\n\t\t      \"core_rx_pre=%d\\n\"\n\t\t      \"core_rx_pre_ver_err=%d\\n\"\n\t\t      \"core_rx_pre_mgmt=%d\\n\"\n\t\t      \"core_rx_pre_mgmt_err_80211w=%d\\n\"\n\t\t      \"core_rx_pre_mgmt_err=%d\\n\"\n\t\t      \"core_rx_pre_ctrl=%d\\n\"\n\t\t      \"core_rx_pre_ctrl_err=%d\\n\"\n\t\t      \"core_rx_pre_data=%d\\n\"\n\t\t      \"core_rx_pre_data_wapi_seq_err=%d\\n\"\n\t\t      \"core_rx_pre_data_wapi_key_err=%d\\n\"\n\t\t      \"core_rx_pre_data_handled=%d\\n\"\n\t\t      \"core_rx_pre_data_err=%d\\n\"\n\t\t      \"core_rx_pre_data_unknown=%d\\n\"\n\t\t      \"core_rx_pre_unknown=%d\\n\"\n\t\t      \"core_rx_enqueue=%d\\n\"\n\t\t      \"core_rx_dequeue=%d\\n\"\n\t\t      \"core_rx_post=%d\\n\"\n\t\t      \"core_rx_post_decrypt=%d\\n\"\n\t\t      \"core_rx_post_decrypt_wep=%d\\n\"\n\t\t      \"core_rx_post_decrypt_tkip=%d\\n\"\n\t\t      \"core_rx_post_decrypt_aes=%d\\n\"\n\t\t      \"core_rx_post_decrypt_wapi=%d\\n\"\n\t\t      \"core_rx_post_decrypt_hw=%d\\n\"\n\t\t      \"core_rx_post_decrypt_unknown=%d\\n\"\n\t\t      \"core_rx_post_decrypt_err=%d\\n\"\n\t\t      \"core_rx_post_defrag_err=%d\\n\"\n\t\t      \"core_rx_post_portctrl_err=%d\\n\"\n\t\t      \"core_rx_post_indicate=%d\\n\"\n\t\t      \"core_rx_post_indicate_in_oder=%d\\n\"\n\t\t      \"core_rx_post_indicate_reoder=%d\\n\"\n\t\t      \"core_rx_post_indicate_err=%d\\n\"\n\t\t      \"os_indicate=%d\\n\"\n\t\t      \"os_indicate_ap_mcast=%d\\n\"\n\t\t      \"os_indicate_ap_forward=%d\\n\"\n\t\t      \"os_indicate_ap_self=%d\\n\"\n\t\t      \"os_indicate_err=%d\\n\"\n\t\t      \"os_netif_ok=%d\\n\"\n\t\t      \"os_netif_err=%d\\n\",\n\t\t      rx_logs->intf_rx,\n\t\t      rx_logs->intf_rx_err_recvframe,\n\t\t      rx_logs->intf_rx_err_skb,\n\t\t      rx_logs->intf_rx_report,\n\t\t      rx_logs->core_rx,\n\t\t      rx_logs->core_rx_pre,\n\t\t      rx_logs->core_rx_pre_ver_err,\n\t\t      rx_logs->core_rx_pre_mgmt,\n\t\t      rx_logs->core_rx_pre_mgmt_err_80211w,\n\t\t      rx_logs->core_rx_pre_mgmt_err,\n\t\t      rx_logs->core_rx_pre_ctrl,\n\t\t      rx_logs->core_rx_pre_ctrl_err,\n\t\t      rx_logs->core_rx_pre_data,\n\t\t      rx_logs->core_rx_pre_data_wapi_seq_err,\n\t\t      rx_logs->core_rx_pre_data_wapi_key_err,\n\t\t      rx_logs->core_rx_pre_data_handled,\n\t\t      rx_logs->core_rx_pre_data_err,\n\t\t      rx_logs->core_rx_pre_data_unknown,\n\t\t      rx_logs->core_rx_pre_unknown,\n\t\t      rx_logs->core_rx_enqueue,\n\t\t      rx_logs->core_rx_dequeue,\n\t\t      rx_logs->core_rx_post,\n\t\t      rx_logs->core_rx_post_decrypt,\n\t\t      rx_logs->core_rx_post_decrypt_wep,\n\t\t      rx_logs->core_rx_post_decrypt_tkip,\n\t\t      rx_logs->core_rx_post_decrypt_aes,\n\t\t      rx_logs->core_rx_post_decrypt_wapi,\n\t\t      rx_logs->core_rx_post_decrypt_hw,\n\t\t      rx_logs->core_rx_post_decrypt_unknown,\n\t\t      rx_logs->core_rx_post_decrypt_err,\n\t\t      rx_logs->core_rx_post_defrag_err,\n\t\t      rx_logs->core_rx_post_portctrl_err,\n\t\t      rx_logs->core_rx_post_indicate,\n\t\t      rx_logs->core_rx_post_indicate_in_oder,\n\t\t      rx_logs->core_rx_post_indicate_reoder,\n\t\t      rx_logs->core_rx_post_indicate_err,\n\t\t      rx_logs->os_indicate,\n\t\t      rx_logs->os_indicate_ap_mcast,\n\t\t      rx_logs->os_indicate_ap_forward,\n\t\t      rx_logs->os_indicate_ap_self,\n\t\t      rx_logs->os_indicate_err,\n\t\t      rx_logs->os_netif_ok,\n\t\t      rx_logs->os_netif_err\n\t\t     );\n\n\treturn 0;\n}\n\nint proc_get_tx_logs(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct tx_logs *tx_logs = &padapter->tx_logs;\n\n\tRTW_PRINT_SEL(m,\n\t\t      \"os_tx=%d\\n\"\n\t\t      \"os_tx_err_up=%d\\n\"\n\t\t      \"os_tx_err_xmit=%d\\n\"\n\t\t      \"os_tx_m2u=%d\\n\"\n\t\t      \"os_tx_m2u_ignore_fw_linked=%d\\n\"\n\t\t      \"os_tx_m2u_ignore_self=%d\\n\"\n\t\t      \"os_tx_m2u_entry=%d\\n\"\n\t\t      \"os_tx_m2u_entry_err_xmit=%d\\n\"\n\t\t      \"os_tx_m2u_entry_err_skb=%d\\n\"\n\t\t      \"os_tx_m2u_stop=%d\\n\"\n\t\t      \"core_tx=%d\\n\"\n\t\t      \"core_tx_err_pxmitframe=%d\\n\"\n\t\t      \"core_tx_err_brtx=%d\\n\"\n\t\t      \"core_tx_upd_attrib=%d\\n\"\n\t\t      \"core_tx_upd_attrib_adhoc=%d\\n\"\n\t\t      \"core_tx_upd_attrib_sta=%d\\n\"\n\t\t      \"core_tx_upd_attrib_ap=%d\\n\"\n\t\t      \"core_tx_upd_attrib_unknown=%d\\n\"\n\t\t      \"core_tx_upd_attrib_dhcp=%d\\n\"\n\t\t      \"core_tx_upd_attrib_icmp=%d\\n\"\n\t\t      \"core_tx_upd_attrib_active=%d\\n\"\n\t\t      \"core_tx_upd_attrib_err_ucast_sta=%d\\n\"\n\t\t      \"core_tx_upd_attrib_err_ucast_ap_link=%d\\n\"\n\t\t      \"core_tx_upd_attrib_err_sta=%d\\n\"\n\t\t      \"core_tx_upd_attrib_err_link=%d\\n\"\n\t\t      \"core_tx_upd_attrib_err_sec=%d\\n\"\n\t\t      \"core_tx_ap_enqueue_warn_fwstate=%d\\n\"\n\t\t      \"core_tx_ap_enqueue_warn_sta=%d\\n\"\n\t\t      \"core_tx_ap_enqueue_warn_nosta=%d\\n\"\n\t\t      \"core_tx_ap_enqueue_warn_link=%d\\n\"\n\t\t      \"core_tx_ap_enqueue_warn_trigger=%d\\n\"\n\t\t      \"core_tx_ap_enqueue_mcast=%d\\n\"\n\t\t      \"core_tx_ap_enqueue_ucast=%d\\n\"\n\t\t      \"core_tx_ap_enqueue=%d\\n\"\n\t\t      \"intf_tx=%d\\n\"\n\t\t      \"intf_tx_pending_ac=%d\\n\"\n\t\t      \"intf_tx_pending_fw_under_survey=%d\\n\"\n\t\t      \"intf_tx_pending_fw_under_linking=%d\\n\"\n\t\t      \"intf_tx_pending_xmitbuf=%d\\n\"\n\t\t      \"intf_tx_enqueue=%d\\n\"\n\t\t      \"core_tx_enqueue=%d\\n\"\n\t\t      \"core_tx_enqueue_class=%d\\n\"\n\t\t      \"core_tx_enqueue_class_err_sta=%d\\n\"\n\t\t      \"core_tx_enqueue_class_err_nosta=%d\\n\"\n\t\t      \"core_tx_enqueue_class_err_fwlink=%d\\n\"\n\t\t      \"intf_tx_direct=%d\\n\"\n\t\t      \"intf_tx_direct_err_coalesce=%d\\n\"\n\t\t      \"intf_tx_dequeue=%d\\n\"\n\t\t      \"intf_tx_dequeue_err_coalesce=%d\\n\"\n\t\t      \"intf_tx_dump_xframe=%d\\n\"\n\t\t      \"intf_tx_dump_xframe_err_txdesc=%d\\n\"\n\t\t      \"intf_tx_dump_xframe_err_port=%d\\n\",\n\t\t      tx_logs->os_tx,\n\t\t      tx_logs->os_tx_err_up,\n\t\t      tx_logs->os_tx_err_xmit,\n\t\t      tx_logs->os_tx_m2u,\n\t\t      tx_logs->os_tx_m2u_ignore_fw_linked,\n\t\t      tx_logs->os_tx_m2u_ignore_self,\n\t\t      tx_logs->os_tx_m2u_entry,\n\t\t      tx_logs->os_tx_m2u_entry_err_xmit,\n\t\t      tx_logs->os_tx_m2u_entry_err_skb,\n\t\t      tx_logs->os_tx_m2u_stop,\n\t\t      tx_logs->core_tx,\n\t\t      tx_logs->core_tx_err_pxmitframe,\n\t\t      tx_logs->core_tx_err_brtx,\n\t\t      tx_logs->core_tx_upd_attrib,\n\t\t      tx_logs->core_tx_upd_attrib_adhoc,\n\t\t      tx_logs->core_tx_upd_attrib_sta,\n\t\t      tx_logs->core_tx_upd_attrib_ap,\n\t\t      tx_logs->core_tx_upd_attrib_unknown,\n\t\t      tx_logs->core_tx_upd_attrib_dhcp,\n\t\t      tx_logs->core_tx_upd_attrib_icmp,\n\t\t      tx_logs->core_tx_upd_attrib_active,\n\t\t      tx_logs->core_tx_upd_attrib_err_ucast_sta,\n\t\t      tx_logs->core_tx_upd_attrib_err_ucast_ap_link,\n\t\t      tx_logs->core_tx_upd_attrib_err_sta,\n\t\t      tx_logs->core_tx_upd_attrib_err_link,\n\t\t      tx_logs->core_tx_upd_attrib_err_sec,\n\t\t      tx_logs->core_tx_ap_enqueue_warn_fwstate,\n\t\t      tx_logs->core_tx_ap_enqueue_warn_sta,\n\t\t      tx_logs->core_tx_ap_enqueue_warn_nosta,\n\t\t      tx_logs->core_tx_ap_enqueue_warn_link,\n\t\t      tx_logs->core_tx_ap_enqueue_warn_trigger,\n\t\t      tx_logs->core_tx_ap_enqueue_mcast,\n\t\t      tx_logs->core_tx_ap_enqueue_ucast,\n\t\t      tx_logs->core_tx_ap_enqueue,\n\t\t      tx_logs->intf_tx,\n\t\t      tx_logs->intf_tx_pending_ac,\n\t\t      tx_logs->intf_tx_pending_fw_under_survey,\n\t\t      tx_logs->intf_tx_pending_fw_under_linking,\n\t\t      tx_logs->intf_tx_pending_xmitbuf,\n\t\t      tx_logs->intf_tx_enqueue,\n\t\t      tx_logs->core_tx_enqueue,\n\t\t      tx_logs->core_tx_enqueue_class,\n\t\t      tx_logs->core_tx_enqueue_class_err_sta,\n\t\t      tx_logs->core_tx_enqueue_class_err_nosta,\n\t\t      tx_logs->core_tx_enqueue_class_err_fwlink,\n\t\t      tx_logs->intf_tx_direct,\n\t\t      tx_logs->intf_tx_direct_err_coalesce,\n\t\t      tx_logs->intf_tx_dequeue,\n\t\t      tx_logs->intf_tx_dequeue_err_coalesce,\n\t\t      tx_logs->intf_tx_dump_xframe,\n\t\t      tx_logs->intf_tx_dump_xframe_err_txdesc,\n\t\t      tx_logs->intf_tx_dump_xframe_err_port\n\t\t     );\n\n\treturn 0;\n}\n\nint proc_get_int_logs(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_PRINT_SEL(m,\n\t\t      \"all=%d\\n\"\n\t\t      \"err=%d\\n\"\n\t\t      \"tbdok=%d\\n\"\n\t\t      \"tbder=%d\\n\"\n\t\t      \"bcnderr=%d\\n\"\n\t\t      \"bcndma=%d\\n\"\n\t\t      \"bcndma_e=%d\\n\"\n\t\t      \"rx=%d\\n\"\n\t\t      \"rx_rdu=%d\\n\"\n\t\t      \"rx_fovw=%d\\n\"\n\t\t      \"txfovw=%d\\n\"\n\t\t      \"mgntok=%d\\n\"\n\t\t      \"highdok=%d\\n\"\n\t\t      \"bkdok=%d\\n\"\n\t\t      \"bedok=%d\\n\"\n\t\t      \"vidok=%d\\n\"\n\t\t      \"vodok=%d\\n\",\n\t\t      padapter->int_logs.all,\n\t\t      padapter->int_logs.err,\n\t\t      padapter->int_logs.tbdok,\n\t\t      padapter->int_logs.tbder,\n\t\t      padapter->int_logs.bcnderr,\n\t\t      padapter->int_logs.bcndma,\n\t\t      padapter->int_logs.bcndma_e,\n\t\t      padapter->int_logs.rx,\n\t\t      padapter->int_logs.rx_rdu,\n\t\t      padapter->int_logs.rx_fovw,\n\t\t      padapter->int_logs.txfovw,\n\t\t      padapter->int_logs.mgntok,\n\t\t      padapter->int_logs.highdok,\n\t\t      padapter->int_logs.bkdok,\n\t\t      padapter->int_logs.bedok,\n\t\t      padapter->int_logs.vidok,\n\t\t      padapter->int_logs.vodok\n\t\t     );\n\n\treturn 0;\n}\n\n#endif /* CONFIG_DBG_COUNTER */\n\nint proc_get_hw_status(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = padapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &dvobj->drv_dbg;\n\tstruct registry_priv *regsty = dvobj_to_regsty(dvobj);\n\n\tif (regsty->check_hw_status == 0)\n\t\tRTW_PRINT_SEL(m, \"RX FIFO full count: not check in watch dog\\n\");\n\telse if (pdbgpriv->dbg_rx_fifo_last_overflow == 1\n\t    && pdbgpriv->dbg_rx_fifo_curr_overflow == 1\n\t    && pdbgpriv->dbg_rx_fifo_diff_overflow == 1\n\t   )\n\t\tRTW_PRINT_SEL(m, \"RX FIFO full count: no implementation\\n\");\n\telse {\n\t\tRTW_PRINT_SEL(m, \"RX FIFO full count: last_time=%llu, current_time=%llu, differential=%llu\\n\"\n\t\t\t, pdbgpriv->dbg_rx_fifo_last_overflow, pdbgpriv->dbg_rx_fifo_curr_overflow, pdbgpriv->dbg_rx_fifo_diff_overflow);\n\t}\n\n\treturn 0;\n}\n\nssize_t proc_set_hw_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = padapter->dvobj;\n\tstruct registry_priv *regsty = dvobj_to_regsty(dvobj);\n\tchar tmp[32];\n\tu32 enable;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d \", &enable);\n\n\t\tif (num == 1 && regsty && enable <= 1) {\n\t\t\tregsty->check_hw_status = enable;\n\t\t\tRTW_INFO(\"check_hw_status=%d\\n\", regsty->check_hw_status);\n\t\t}\n\t}\n\n\treturn count;\n}\n\n#ifdef CONFIG_HUAWEI_PROC\nint proc_get_huawei_trx_info(struct seq_file *sel, void *v)\n{\n\tstruct net_device *dev = sel->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dm_struct *dm = adapter_to_phydm(padapter);\n\tstruct sta_info *psta;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\tstruct ra_sta_info *ra_info;\n\tu8 curr_tx_sgi = _FALSE;\n\tu8 curr_tx_rate = 0;\n\tu8 mac_id;\n#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA\n\tu8 isCCKrate, rf_path;\n\tPHAL_DATA_TYPE\tpHalData =  GET_HAL_DATA(padapter);\n\tstruct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;\n#endif\n\n\tif (!dm->is_linked) {\n\t\tRTW_PRINT_SEL(sel, \"NO link\\n\\n\");\n\t\treturn 0;\n\t}\n\n\t/*============  tx info ============\t*/\n\tfor (mac_id = 0; mac_id < macid_ctl->num; mac_id++) {\n\t\tif (rtw_macid_is_used(macid_ctl, mac_id) && !rtw_macid_is_bmc(macid_ctl, mac_id)) {\n\t\t\tpsta = macid_ctl->sta[mac_id];\n\t\t\tif (!psta)\n\t\t\t\tcontinue;\n\n\t\t\tRTW_PRINT_SEL(sel, \"STA [\" MAC_FMT \"]\\n\", MAC_ARG(psta->cmn.mac_addr));\n\n\t\t\tra_info = &psta->cmn.ra_info;\n\t\t\tcurr_tx_sgi = rtw_get_current_tx_sgi(padapter, psta);\n\t\t\tcurr_tx_rate = rtw_get_current_tx_rate(padapter, psta);\n\t\t\tRTW_PRINT_SEL(sel, \"curr_tx_rate : %s (%s)\\n\",\n\t\t\t\t\tHDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? \"S\" : \"L\");\n\t\t\tRTW_PRINT_SEL(sel, \"curr_tx_bw : %s\\n\", ch_width_str(ra_info->curr_tx_bw));\n\t\t}\n\t}\n\n\t/*============  rx info ============\t*/\n\tRTW_PRINT_SEL(sel, \"rx_rate : %s\\n\", HDATA_RATE(dm->rx_rate));\n#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA\n\tisCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? TRUE : FALSE;\n\n\tfor (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {\n\t\tif (!isCCKrate)\n\t\t\t_RTW_PRINT_SEL(sel , \"RF_PATH_%d : rx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\\n\",\n\t\t\t\trf_path, psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);\n\t}\n#endif\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\treturn 0;\n}\n#endif /* CONFIG_HUAWEI_PROC */\n\nint proc_get_trx_info_debug(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\t/*============  tx info ============\t*/\n\trtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, m);\n\n\t/*============  rx info ============\t*/\n\trtw_hal_set_odm_var(padapter, HAL_ODM_RX_INFO_DUMP, m, _FALSE);\n\n\treturn 0;\n}\n\nint proc_get_rx_signal(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_PRINT_SEL(m, \"rssi:%d\\n\", padapter->recvpriv.rssi);\n#ifdef CONFIG_MP_INCLUDED\n\tif (padapter->registrypriv.mp_mode == 1) {\n\t\tstruct dm_struct *odm = adapter_to_phydm(padapter);\n\t\tif (padapter->mppriv.antenna_rx == ANTENNA_A)\n\t\t\tRTW_PRINT_SEL(m, \"Antenna: A\\n\");\n\t\telse if (padapter->mppriv.antenna_rx == ANTENNA_B)\n\t\t\tRTW_PRINT_SEL(m, \"Antenna: B\\n\");\n\t\telse if (padapter->mppriv.antenna_rx == ANTENNA_C)\n\t\t\tRTW_PRINT_SEL(m, \"Antenna: C\\n\");\n\t\telse if (padapter->mppriv.antenna_rx == ANTENNA_D)\n\t\t\tRTW_PRINT_SEL(m, \"Antenna: D\\n\");\n\t\telse if (padapter->mppriv.antenna_rx == ANTENNA_AB)\n\t\t\tRTW_PRINT_SEL(m, \"Antenna: AB\\n\");\n\t\telse if (padapter->mppriv.antenna_rx == ANTENNA_BC)\n\t\t\tRTW_PRINT_SEL(m, \"Antenna: BC\\n\");\n\t\telse if (padapter->mppriv.antenna_rx == ANTENNA_CD)\n\t\t\tRTW_PRINT_SEL(m, \"Antenna: CD\\n\");\n\t\telse\n\t\t\tRTW_PRINT_SEL(m, \"Antenna: __\\n\");\n\n\t\tRTW_PRINT_SEL(m, \"rx_rate = %s\\n\", HDATA_RATE(odm->rx_rate));\n\t\treturn 0;\n\t} else \n#endif\n\t{\n\t\t/* RTW_PRINT_SEL(m, \"rxpwdb:%d\\n\", padapter->recvpriv.rxpwdb); */\n\t\tRTW_PRINT_SEL(m, \"signal_strength:%u\\n\", padapter->recvpriv.signal_strength);\n\t\tRTW_PRINT_SEL(m, \"signal_qual:%u\\n\", padapter->recvpriv.signal_qual);\n\t}\n#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA\n\trtw_odm_get_perpkt_rssi(m, padapter);\n\trtw_get_raw_rssi_info(m, padapter);\n#endif\n\treturn 0;\n}\n\nssize_t proc_set_rx_signal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu32 is_signal_dbg, signal_strength;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%u %u\", &is_signal_dbg, &signal_strength);\n\n\t\tif (num < 1)\n\t\t\treturn count;\n\n\t\tis_signal_dbg = is_signal_dbg == 0 ? 0 : 1;\n\n\t\tif (is_signal_dbg && num < 2)\n\t\t\treturn count;\n\n\t\tsignal_strength = signal_strength > 100 ? 100 : signal_strength;\n\n\t\tpadapter->recvpriv.is_signal_dbg = is_signal_dbg;\n\t\tpadapter->recvpriv.signal_strength_dbg = signal_strength;\n\n\t\tif (is_signal_dbg)\n\t\t\tRTW_INFO(\"set %s %u\\n\", \"DBG_SIGNAL_STRENGTH\", signal_strength);\n\t\telse\n\t\t\tRTW_INFO(\"set %s\\n\", \"HW_SIGNAL_STRENGTH\");\n\n\t}\n\n\treturn count;\n\n}\n\nint proc_get_mac_rptbuf(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu16 i;\n\tu16 mac_id;\n\tu32 shcut_addr = 0;\n\tu32 read_addr = 0;\n#ifdef CONFIG_RTL8814A\n\tRTW_PRINT_SEL(m, \"TX ShortCut:\\n\");\n\tfor (mac_id = 0; mac_id < 64; mac_id++) {\n\t\trtw_write16(padapter, 0x140, 0x662 | ((mac_id & BIT5) >> 5));\n\t\tshcut_addr = 0x8000;\n\t\tshcut_addr = shcut_addr | ((mac_id & 0x1f) << 7);\n\t\tRTW_PRINT_SEL(m, \"mac_id=%d, 0x140=%x =>\\n\", mac_id, 0x662 | ((mac_id & BIT5) >> 5));\n\t\tfor (i = 0; i < 30; i++) {\n\t\t\tread_addr = 0;\n\t\t\tread_addr = shcut_addr | (i << 2);\n\t\t\tRTW_PRINT_SEL(m, \"i=%02d: MAC_%04x= %08x \", i, read_addr, rtw_read32(padapter, read_addr));\n\t\t\tif (!((i + 1) % 4))\n\t\t\t\tRTW_PRINT_SEL(m, \"\\n\");\n\t\t\tif (i == 29)\n\t\t\t\tRTW_PRINT_SEL(m, \"\\n\");\n\t\t}\n\t}\n#endif /* CONFIG_RTL8814A */\n\treturn 0;\n}\n\n#ifdef CONFIG_80211N_HT\n\nint proc_get_ht_enable(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\n\tif (pregpriv)\n\t\tRTW_PRINT_SEL(m, \"%d\\n\", pregpriv->ht_enable);\n\n\treturn 0;\n}\n\nssize_t proc_set_ht_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\tchar tmp[32];\n\tu32 mode;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d \", &mode);\n\n\t\tif ( num == 1 && pregpriv && mode < 2) {\n\t\t\tpregpriv->ht_enable = mode;\n\t\t\tRTW_INFO(\"ht_enable=%d\\n\", pregpriv->ht_enable);\n\t\t}\n\t}\n\n\treturn count;\n\n}\n\nint proc_get_bw_mode(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\n\tif (pregpriv)\n\t\tRTW_PRINT_SEL(m, \"0x%02x\\n\", pregpriv->bw_mode);\n\n\treturn 0;\n}\n\nssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\tchar tmp[32];\n\tu32 mode;\n\tu8 bw_2g;\n\tu8 bw_5g;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%x \", &mode);\n\t\tbw_5g = mode >> 4;\n\t\tbw_2g = mode & 0x0f;\n\n\t\tif (num == 1 && pregpriv && bw_2g <= 4 && bw_5g <= 4) {\n\t\t\tpregpriv->bw_mode = mode;\n\t\t\tprintk(\"bw_mode=0x%x\\n\", mode);\n\t\t}\n\t}\n\n\treturn count;\n\n}\n\nint proc_get_ampdu_enable(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\n\tif (pregpriv)\n\t\tRTW_PRINT_SEL(m, \"%d\\n\", pregpriv->ampdu_enable);\n\n\treturn 0;\n}\n\nssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\tchar tmp[32];\n\tu32 mode;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d \", &mode);\n\n\t\tif (num == 1 && pregpriv && mode < 2) {\n\t\t\tpregpriv->ampdu_enable = mode;\n\t\t\tprintk(\"ampdu_enable=%d\\n\", mode);\n\t\t}\n\n\t}\n\n\treturn count;\n\n}\n\n\nvoid dump_regsty_rx_ampdu_size_limit(void *sel, _adapter *adapter)\n{\n\tstruct registry_priv *regsty = adapter_to_regsty(adapter);\n\tint i;\n\n\tRTW_PRINT_SEL(sel, \"%-3s %-3s %-3s %-3s %-4s\\n\"\n\t\t, \"\", \"20M\", \"40M\", \"80M\", \"160M\");\n\tfor (i = 0; i < 4; i++)\n\t\tRTW_PRINT_SEL(sel, \"%dSS %3u %3u %3u %4u\\n\", i + 1\n\t\t\t, regsty->rx_ampdu_sz_limit_by_nss_bw[i][0]\n\t\t\t, regsty->rx_ampdu_sz_limit_by_nss_bw[i][1]\n\t\t\t, regsty->rx_ampdu_sz_limit_by_nss_bw[i][2]\n\t\t\t, regsty->rx_ampdu_sz_limit_by_nss_bw[i][3]);\n}\n\nint proc_get_rx_ampdu(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\t_RTW_PRINT_SEL(m, \"accept: \");\n\tif (padapter->fix_rx_ampdu_accept == RX_AMPDU_ACCEPT_INVALID)\n\t\tRTW_PRINT_SEL(m, \"%u%s\\n\", rtw_rx_ampdu_is_accept(padapter), \"(auto)\");\n\telse\n\t\tRTW_PRINT_SEL(m, \"%u%s\\n\", padapter->fix_rx_ampdu_accept, \"(fixed)\");\n\n\t_RTW_PRINT_SEL(m, \"size: \");\n\tif (padapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID) {\n\t\tRTW_PRINT_SEL(m, \"%u%s\\n\", rtw_rx_ampdu_size(padapter), \"(auto) with conditional limit:\");\n\t\tdump_regsty_rx_ampdu_size_limit(m, padapter);\n\t} else\n\t\tRTW_PRINT_SEL(m, \"%u%s\\n\", padapter->fix_rx_ampdu_size, \"(fixed)\");\n\tRTW_PRINT_SEL(m, \"\\n\");\n\n\tRTW_PRINT_SEL(m, \"%19s %17s\\n\", \"fix_rx_ampdu_accept\", \"fix_rx_ampdu_size\");\n\n\t_RTW_PRINT_SEL(m, \"%-19d %-17u\\n\"\n\t\t, padapter->fix_rx_ampdu_accept\n\t\t, padapter->fix_rx_ampdu_size);\n\n\treturn 0;\n}\n\nssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu8 accept;\n\tu8 size;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhu %hhu\", &accept, &size);\n\n\t\tif (num >= 1)\n\t\t\trtw_rx_ampdu_set_accept(padapter, accept, RX_AMPDU_DRV_FIXED);\n\t\tif (num >= 2)\n\t\t\trtw_rx_ampdu_set_size(padapter, size, RX_AMPDU_DRV_FIXED);\n\n\t\trtw_rx_ampdu_apply(padapter);\n\t}\n\n\treturn count;\n}\n\nint proc_get_rx_ampdu_factor(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\n\tif (padapter)\n\t\tRTW_PRINT_SEL(m, \"rx ampdu factor = %x\\n\", padapter->driver_rx_ampdu_factor);\n\n\treturn 0;\n}\n\nssize_t proc_set_rx_ampdu_factor(struct file *file, const char __user *buffer\n\t\t\t\t , size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu32 factor;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d \", &factor);\n\n\t\tif (padapter && (num == 1)) {\n\t\t\tRTW_INFO(\"padapter->driver_rx_ampdu_factor = %x\\n\", factor);\n\n\t\t\tif (factor  > 0x03)\n\t\t\t\tpadapter->driver_rx_ampdu_factor = 0xFF;\n\t\t\telse\n\t\t\t\tpadapter->driver_rx_ampdu_factor = factor;\n\t\t}\n\t}\n\n\treturn count;\n}\n\nint proc_get_tx_max_agg_num(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\n\tif (padapter)\n\t\tRTW_PRINT_SEL(m, \"tx max AMPDU num = 0x%02x\\n\", padapter->driver_tx_max_agg_num);\n\n\treturn 0;\n}\n\nssize_t proc_set_tx_max_agg_num(struct file *file, const char __user *buffer\n\t\t\t\t , size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu8 agg_num;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhx \", &agg_num);\n\n\t\tif (padapter && (num == 1)) {\n\t\t\tRTW_INFO(\"padapter->driver_tx_max_agg_num = 0x%02x\\n\", agg_num);\n\n\t\t\tpadapter->driver_tx_max_agg_num = agg_num;\n\t\t}\n\t}\n\n\treturn count;\n}\n\nint proc_get_rx_ampdu_density(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\n\tif (padapter)\n\t\tRTW_PRINT_SEL(m, \"rx ampdu densityg = %x\\n\", padapter->driver_rx_ampdu_spacing);\n\n\treturn 0;\n}\n\nssize_t proc_set_rx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu32 density;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d \", &density);\n\n\t\tif (padapter && (num == 1)) {\n\t\t\tRTW_INFO(\"padapter->driver_rx_ampdu_spacing = %x\\n\", density);\n\n\t\t\tif (density > 0x07)\n\t\t\t\tpadapter->driver_rx_ampdu_spacing = 0xFF;\n\t\t\telse\n\t\t\t\tpadapter->driver_rx_ampdu_spacing = density;\n\t\t}\n\t}\n\n\treturn count;\n}\n\nint proc_get_tx_ampdu_density(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\n\tif (padapter)\n\t\tRTW_PRINT_SEL(m, \"tx ampdu density = %x\\n\", padapter->driver_ampdu_spacing);\n\n\treturn 0;\n}\n\nssize_t proc_set_tx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu32 density;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d \", &density);\n\n\t\tif (padapter && (num == 1)) {\n\t\t\tRTW_INFO(\"padapter->driver_ampdu_spacing = %x\\n\", density);\n\n\t\t\tif (density > 0x07)\n\t\t\t\tpadapter->driver_ampdu_spacing = 0xFF;\n\t\t\telse\n\t\t\t\tpadapter->driver_ampdu_spacing = density;\n\t\t}\n\t}\n\n\treturn count;\n}\n\nint proc_get_tx_quick_addba_req(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\n\tif (padapter)\n\t\tRTW_PRINT_SEL(m, \"tx_quick_addba_req = %x\\n\", pregpriv->tx_quick_addba_req);\n\n\treturn 0;\n}\n\nssize_t proc_set_tx_quick_addba_req(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\tchar tmp[32];\n\tu32 enable;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d \", &enable);\n\n\t\tif (padapter && (num == 1)) {\n\t\t\tpregpriv->tx_quick_addba_req = enable;\n\t\t\tRTW_INFO(\"tx_quick_addba_req = %d\\n\", pregpriv->tx_quick_addba_req);\n\t\t}\n\t}\n\n\treturn count;\n}\n#ifdef CONFIG_TX_AMSDU\nint proc_get_tx_amsdu(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\n\tif (padapter)\n\t{\n\t\tRTW_PRINT_SEL(m, \"tx amsdu = %d\\n\", padapter->tx_amsdu);\n\t\tRTW_PRINT_SEL(m, \"amsdu set timer conut = %u\\n\", pxmitpriv->amsdu_debug_set_timer);\n\t\tRTW_PRINT_SEL(m, \"amsdu  time out count = %u\\n\", pxmitpriv->amsdu_debug_timeout);\n\t\tRTW_PRINT_SEL(m, \"amsdu coalesce one count = %u\\n\", pxmitpriv->amsdu_debug_coalesce_one);\n\t\tRTW_PRINT_SEL(m, \"amsdu coalesce two count = %u\\n\", pxmitpriv->amsdu_debug_coalesce_two);\n\t}\n\n\treturn 0;\n}\n\nssize_t proc_set_tx_amsdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tchar tmp[32];\n\tu32 amsdu;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d \", &amsdu);\n\n\t\tif (padapter && (num == 1)) {\n\t\t\tRTW_INFO(\"padapter->tx_amsdu = %x\\n\", amsdu);\n\n\t\t\tif (amsdu > 3)\n\t\t\t\tpadapter->tx_amsdu = 0;\n\t\t\telse if(amsdu == 3)\n\t\t\t{\n\t\t\t\tpxmitpriv->amsdu_debug_set_timer = 0;\n\t\t\t\tpxmitpriv->amsdu_debug_timeout = 0;\n\t\t\t\tpxmitpriv->amsdu_debug_coalesce_one = 0;\n\t\t\t\tpxmitpriv->amsdu_debug_coalesce_two = 0;\n\t\t\t}\n\t\t\telse\n\t\t\t\tpadapter->tx_amsdu = amsdu;\n\t\t}\n\t}\n\n\treturn count;\n}\n\nint proc_get_tx_amsdu_rate(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (padapter)\n\t\tRTW_PRINT_SEL(m, \"tx amsdu rate = %d Mbps\\n\", padapter->tx_amsdu_rate);\n\n\treturn 0;\n}\n\nssize_t proc_set_tx_amsdu_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu32 amsdu_rate;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d \", &amsdu_rate);\n\n\t\tif (padapter && (num == 1)) {\n\t\t\tRTW_INFO(\"padapter->tx_amsdu_rate = %x\\n\", amsdu_rate);\n\t\t\tpadapter->tx_amsdu_rate = amsdu_rate;\n\t\t}\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_TX_AMSDU */\n#endif /* CONFIG_80211N_HT */\n\nint proc_get_en_fwps(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\n\tif (pregpriv)\n\t\tRTW_PRINT_SEL(m, \"check_fw_ps = %d , 1:enable get FW PS state , 0: disable get FW PS state\\n\"\n\t\t\t      , pregpriv->check_fw_ps);\n\n\treturn 0;\n}\n\nssize_t proc_set_en_fwps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\tchar tmp[32];\n\tu32 mode;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d \", &mode);\n\n\t\tif (num == 1 && pregpriv &&  mode < 2) {\n\t\t\tpregpriv->check_fw_ps = mode;\n\t\t\tRTW_INFO(\"pregpriv->check_fw_ps=%d\\n\", pregpriv->check_fw_ps);\n\t\t}\n\n\t}\n\n\treturn count;\n}\n\n/*\nint proc_get_two_path_rssi(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif(padapter)\n\t\tRTW_PRINT_SEL(m, \"%d %d\\n\",\n\t\t\tpadapter->recvpriv.RxRssi[0], padapter->recvpriv.RxRssi[1]);\n\n\treturn 0;\n}\n*/\n#ifdef CONFIG_80211N_HT\nvoid rtw_dump_dft_phy_cap(void *sel, _adapter *adapter)\n{\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tstruct ht_priv\t*phtpriv = &pmlmepriv->htpriv;\n\t#ifdef CONFIG_80211AC_VHT\n\tstruct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;\n\t#endif\n\n\t#ifdef CONFIG_80211AC_VHT\n\tRTW_PRINT_SEL(sel, \"[DFT CAP] VHT STBC Tx : %s\\n\", (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) ? \"V\" : \"X\");\n\tRTW_PRINT_SEL(sel, \"[DFT CAP] VHT STBC Rx : %s\\n\", (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) ? \"V\" : \"X\");\n\t#endif\n\tRTW_PRINT_SEL(sel, \"[DFT CAP] HT STBC Tx : %s\\n\", (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX)) ? \"V\" : \"X\");\n\tRTW_PRINT_SEL(sel, \"[DFT CAP] HT STBC Rx : %s\\n\\n\", (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) ? \"V\" : \"X\");\n\n\t#ifdef CONFIG_80211AC_VHT\n\tRTW_PRINT_SEL(sel, \"[DFT CAP] VHT LDPC Tx : %s\\n\", (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX)) ? \"V\" : \"X\");\n\tRTW_PRINT_SEL(sel, \"[DFT CAP] VHT LDPC Rx : %s\\n\", (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) ? \"V\" : \"X\");\n\t#endif\n\tRTW_PRINT_SEL(sel, \"[DFT CAP] HT LDPC Tx : %s\\n\", (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX)) ? \"V\" : \"X\");\n\tRTW_PRINT_SEL(sel, \"[DFT CAP] HT LDPC Rx : %s\\n\\n\", (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX)) ? \"V\" : \"X\");\n\n\t#ifdef CONFIG_BEAMFORMING\n\t#ifdef CONFIG_80211AC_VHT\n\tRTW_PRINT_SEL(sel, \"[DFT CAP] VHT MU Bfer : %s\\n\", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) ? \"V\" : \"X\");\n\tRTW_PRINT_SEL(sel, \"[DFT CAP] VHT MU Bfee : %s\\n\", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) ? \"V\" : \"X\");\n\tRTW_PRINT_SEL(sel, \"[DFT CAP] VHT SU Bfer : %s\\n\", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) ? \"V\" : \"X\");\n\tRTW_PRINT_SEL(sel, \"[DFT CAP] VHT SU Bfee : %s\\n\", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) ? \"V\" : \"X\");\n\t#endif\n\tRTW_PRINT_SEL(sel, \"[DFT CAP] HT Bfer : %s\\n\", (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE))  ? \"V\" : \"X\");\n\tRTW_PRINT_SEL(sel, \"[DFT CAP] HT Bfee : %s\\n\", (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) ? \"V\" : \"X\");\n\t#endif\n}\n\nvoid rtw_get_dft_phy_cap(void *sel, _adapter *adapter)\n{\n\tRTW_PRINT_SEL(sel, \"\\n ======== PHY CAP protocol ========\\n\");\n\trtw_ht_use_default_setting(adapter);\n\t#ifdef CONFIG_80211AC_VHT\n\trtw_vht_use_default_setting(adapter);\n\t#endif\n\t#ifdef CONFIG_80211N_HT\n\trtw_dump_dft_phy_cap(sel, adapter);\n\t#endif\n}\n\nvoid rtw_dump_drv_phy_cap(void *sel, _adapter *adapter)\n{\n\tstruct registry_priv\t*pregistry_priv = &adapter->registrypriv;\n\n\tRTW_PRINT_SEL(sel, \"\\n ======== DRV's configuration ========\\n\");\n\t#if 0\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] TRx Capability : 0x%08x\\n\", phy_spec->trx_cap);\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] Tx Stream Num Index : %d\\n\", (phy_spec->trx_cap >> 24) & 0xFF); /*Tx Stream Num Index [31:24]*/\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] Rx Stream Num Index : %d\\n\", (phy_spec->trx_cap >> 16) & 0xFF); /*Rx Stream Num Index [23:16]*/\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] Tx Path Num Index : %d\\n\", (phy_spec->trx_cap >> 8) & 0xFF);/*Tx Path Num Index\t[15:8]*/\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] Rx Path Num Index : %d\\n\", (phy_spec->trx_cap & 0xFF));/*Rx Path Num Index\t[7:0]*/\n\t#endif\n\t#ifdef CONFIG_80211N_HT\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] STBC Capability : 0x%02x\\n\", pregistry_priv->stbc_cap);\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] VHT STBC Tx : %s\\n\", (TEST_FLAG(pregistry_priv->stbc_cap, BIT1)) ? \"V\" : \"X\"); /*BIT1: Enable VHT STBC Tx*/\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] VHT STBC Rx : %s\\n\", (TEST_FLAG(pregistry_priv->stbc_cap, BIT0)) ? \"V\" : \"X\"); /*BIT0: Enable VHT STBC Rx*/\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] HT STBC Tx : %s\\n\", (TEST_FLAG(pregistry_priv->stbc_cap, BIT5)) ? \"V\" : \"X\"); /*BIT5: Enable HT STBC Tx*/\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] HT STBC Rx : %s\\n\\n\", (TEST_FLAG(pregistry_priv->stbc_cap, BIT4)) ? \"V\" : \"X\"); /*BIT4: Enable HT STBC Rx*/\n\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] LDPC Capability : 0x%02x\\n\", pregistry_priv->ldpc_cap);\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] VHT LDPC Tx : %s\\n\", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT1)) ? \"V\" : \"X\"); /*BIT1: Enable VHT LDPC Tx*/\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] VHT LDPC Rx : %s\\n\", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT0)) ? \"V\" : \"X\"); /*BIT0: Enable VHT LDPC Rx*/\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] HT LDPC Tx : %s\\n\", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT5)) ? \"V\" : \"X\"); /*BIT5: Enable HT LDPC Tx*/\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] HT LDPC Rx : %s\\n\\n\", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT4)) ? \"V\" : \"X\"); /*BIT4: Enable HT LDPC Rx*/\n\t#endif /* CONFIG_80211N_HT */\n\t#ifdef CONFIG_BEAMFORMING\n\t#if 0\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] TxBF parameter : 0x%08x\\n\", phy_spec->txbf_param);\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] VHT Sounding Dim : %d\\n\", (phy_spec->txbf_param >> 24) & 0xFF); /*VHT Sounding Dim [31:24]*/\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] VHT Steering Ant : %d\\n\", (phy_spec->txbf_param >> 16) & 0xFF); /*VHT Steering Ant [23:16]*/\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] HT Sounding Dim : %d\\n\", (phy_spec->txbf_param >> 8) & 0xFF); /*HT Sounding Dim [15:8]*/\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] HT Steering Ant : %d\\n\", phy_spec->txbf_param & 0xFF); /*HT Steering Ant [7:0]*/\n\t#endif\n\n\t/*\n\t * BIT0: Enable VHT SU Beamformer\n\t * BIT1: Enable VHT SU Beamformee\n\t * BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer\n\t * BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee\n\t * BIT4: Enable HT Beamformer\n\t * BIT5: Enable HT Beamformee\n\t */\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] TxBF Capability : 0x%02x\\n\", pregistry_priv->beamform_cap);\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] VHT MU Bfer : %s\\n\", (TEST_FLAG(pregistry_priv->beamform_cap, BIT2)) ? \"V\" : \"X\");\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] VHT MU Bfee : %s\\n\", (TEST_FLAG(pregistry_priv->beamform_cap, BIT3)) ? \"V\" : \"X\");\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] VHT SU Bfer : %s\\n\", (TEST_FLAG(pregistry_priv->beamform_cap, BIT0)) ? \"V\" : \"X\");\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] VHT SU Bfee : %s\\n\", (TEST_FLAG(pregistry_priv->beamform_cap, BIT1)) ? \"V\" : \"X\");\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] HT Bfer : %s\\n\", (TEST_FLAG(pregistry_priv->beamform_cap, BIT4))  ? \"V\" : \"X\");\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] HT Bfee : %s\\n\", (TEST_FLAG(pregistry_priv->beamform_cap, BIT5)) ? \"V\" : \"X\");\n\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] Tx Bfer rf_num : %d\\n\", pregistry_priv->beamformer_rf_num);\n\tRTW_PRINT_SEL(sel, \"[DRV CAP] Tx Bfee rf_num : %d\\n\", pregistry_priv->beamformee_rf_num);\n\t#endif\n}\n\nint proc_get_stbc_cap(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\n\tif (pregpriv)\n\t\tRTW_PRINT_SEL(m, \"0x%02x\\n\", pregpriv->stbc_cap);\n\n\treturn 0;\n}\n\nssize_t proc_set_stbc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\tchar tmp[32];\n\tu32 mode;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d \", &mode);\n\n\t\tif (num == 1 && pregpriv) {\n\t\t\tpregpriv->stbc_cap = mode;\n\t\t\tRTW_INFO(\"stbc_cap = 0x%02x\\n\", mode);\n\t\t}\n\t}\n\n\treturn count;\n}\nint proc_get_rx_stbc(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\n\tif (pregpriv)\n\t\tRTW_PRINT_SEL(m, \"%d\\n\", pregpriv->rx_stbc);\n\n\treturn 0;\n}\n\nssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\tchar tmp[32];\n\tu32 mode;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d \", &mode);\n\n\t\tif (num == 1 && pregpriv && (mode == 0 || mode == 1 || mode == 2 || mode == 3)) {\n\t\t\tpregpriv->rx_stbc = mode;\n\t\t\tprintk(\"rx_stbc=%d\\n\", mode);\n\t\t}\n\t}\n\n\treturn count;\n\n}\nint proc_get_ldpc_cap(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\n\tif (pregpriv)\n\t\tRTW_PRINT_SEL(m, \"0x%02x\\n\", pregpriv->ldpc_cap);\n\n\treturn 0;\n}\n\nssize_t proc_set_ldpc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\tchar tmp[32];\n\tu32 mode;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d \", &mode);\n\n\t\tif (num == 1 && pregpriv) {\n\t\t\tpregpriv->ldpc_cap = mode;\n\t\t\tRTW_INFO(\"ldpc_cap = 0x%02x\\n\", mode);\n\t\t}\n\t}\n\n\treturn count;\n}\n#ifdef CONFIG_BEAMFORMING\nint proc_get_txbf_cap(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\n\tif (pregpriv)\n\t\tRTW_PRINT_SEL(m, \"0x%02x\\n\", pregpriv->beamform_cap);\n\n\treturn 0;\n}\n\nssize_t proc_set_txbf_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\tchar tmp[32];\n\tu32 mode;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d \", &mode);\n\n\t\tif (num == 1 && pregpriv) {\n\t\t\tpregpriv->beamform_cap = mode;\n\t\t\tRTW_INFO(\"beamform_cap = 0x%02x\\n\", mode);\n\t\t}\n\t}\n\n\treturn count;\n}\n#endif\n#endif /* CONFIG_80211N_HT */\n\n/*int proc_get_rssi_disp(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\treturn 0;\n}\n*/\n\n/*ssize_t proc_set_rssi_disp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu32 enable=0;\n\n\tif (count < 1)\n\t{\n\t\tRTW_INFO(\"argument size is less than 1\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%x\", &enable);\n\n\t\tif (num !=  1) {\n\t\t\tRTW_INFO(\"invalid set_rssi_disp parameter!\\n\");\n\t\t\treturn count;\n\t\t}\n\n\t\tif(enable)\n\t\t{\n\t\t\tRTW_INFO(\"Linked info Function Enable\\n\");\n\t\t\tpadapter->bLinkInfoDump = enable ;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tRTW_INFO(\"Linked info Function Disable\\n\");\n\t\t\tpadapter->bLinkInfoDump = 0 ;\n\t\t}\n\n\t}\n\n\treturn count;\n\n}\n\n*/\n#ifdef CONFIG_AP_MODE\n\nint proc_get_all_sta_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_irqL irqL;\n\tstruct sta_info *psta;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tint i;\n\t_list\t*plist, *phead;\n\n\tRTW_MAP_DUMP_SEL(m, \"sta_dz_bitmap=\", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);\n\tRTW_MAP_DUMP_SEL(m, \"tim_bitmap=\", pstapriv->tim_bitmap, pstapriv->aid_bmp_len);\n\n\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\tfor (i = 0; i < NUM_STA; i++) {\n\t\tphead = &(pstapriv->sta_hash[i]);\n\t\tplist = get_next(phead);\n\n\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\n\t\t\tplist = get_next(plist);\n\n\t\t\t/* if(extra_arg == psta->cmn.aid) */\n\t\t\t{\n\t\t\t\tRTW_PRINT_SEL(m, \"==============================\\n\");\n\t\t\t\tRTW_PRINT_SEL(m, \"sta's macaddr:\" MAC_FMT \"\\n\", MAC_ARG(psta->cmn.mac_addr));\n\t\t\t\tRTW_PRINT_SEL(m, \"rtsen=%d, cts2slef=%d\\n\", psta->rtsen, psta->cts2self);\n\t\t\t\tRTW_PRINT_SEL(m, \"state=0x%x, aid=%d, macid=%d, raid=%d\\n\",\n\t\t\t\t\tpsta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);\n#ifdef CONFIG_RTS_FULL_BW\n\t\t\t\tif(psta->vendor_8812)\n\t\t\t\t\tRTW_PRINT_SEL(m,\"Vendor Realtek 8812\\n\");\n#endif/*CONFIG_RTS_FULL_BW*/\n#ifdef CONFIG_80211N_HT\n\t\t\t\tRTW_PRINT_SEL(m, \"qos_en=%d, ht_en=%d, init_rate=%d\\n\", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);\n\t\t\t\tRTW_PRINT_SEL(m, \"bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\\n\"\n\t\t\t\t\t, psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m);\n\t\t\t\tRTW_PRINT_SEL(m, \"ampdu_enable = %d\\n\", psta->htpriv.ampdu_enable);\n\t\t\t\tRTW_PRINT_SEL(m, \"tx_amsdu_enable = %d\\n\", psta->htpriv.tx_amsdu_enable);\n\t\t\t\tRTW_PRINT_SEL(m, \"agg_enable_bitmap=%x, candidate_tid_bitmap=%x\\n\", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);\n#endif /* CONFIG_80211N_HT */\n#ifdef CONFIG_80211AC_VHT\n\t\t\t\tRTW_PRINT_SEL(m, \"vht_en=%d, vht_sgi_80m=%d\\n\", psta->vhtpriv.vht_option, psta->vhtpriv.sgi_80m);\n\t\t\t\tRTW_PRINT_SEL(m, \"vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\\n\", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap);\n\t\t\t\tRTW_PRINT_SEL(m, \"vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\\n\", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len);\n#endif\n\t\t\t\tRTW_PRINT_SEL(m, \"sleepq_len=%d\\n\", psta->sleepq_len);\n\t\t\t\tRTW_PRINT_SEL(m, \"sta_xmitpriv.vo_q_qcnt=%d\\n\", psta->sta_xmitpriv.vo_q.qcnt);\n\t\t\t\tRTW_PRINT_SEL(m, \"sta_xmitpriv.vi_q_qcnt=%d\\n\", psta->sta_xmitpriv.vi_q.qcnt);\n\t\t\t\tRTW_PRINT_SEL(m, \"sta_xmitpriv.be_q_qcnt=%d\\n\", psta->sta_xmitpriv.be_q.qcnt);\n\t\t\t\tRTW_PRINT_SEL(m, \"sta_xmitpriv.bk_q_qcnt=%d\\n\", psta->sta_xmitpriv.bk_q.qcnt);\n\n\t\t\t\tRTW_PRINT_SEL(m, \"capability=0x%x\\n\", psta->capability);\n\t\t\t\tRTW_PRINT_SEL(m, \"flags=0x%x\\n\", psta->flags);\n\t\t\t\tRTW_PRINT_SEL(m, \"wpa_psk=0x%x\\n\", psta->wpa_psk);\n\t\t\t\tRTW_PRINT_SEL(m, \"wpa2_group_cipher=0x%x\\n\", psta->wpa2_group_cipher);\n\t\t\t\tRTW_PRINT_SEL(m, \"wpa2_pairwise_cipher=0x%x\\n\", psta->wpa2_pairwise_cipher);\n\t\t\t\tRTW_PRINT_SEL(m, \"qos_info=0x%x\\n\", psta->qos_info);\n\t\t\t\tRTW_PRINT_SEL(m, \"dot118021XPrivacy=0x%x\\n\", psta->dot118021XPrivacy);\n\n\t\t\t\tsta_rx_reorder_ctl_dump(m, psta);\n\n#ifdef CONFIG_TDLS\n\t\t\t\tRTW_PRINT_SEL(m, \"tdls_sta_state=0x%08x\\n\", psta->tdls_sta_state);\n\t\t\t\tRTW_PRINT_SEL(m, \"PeerKey_Lifetime=%d\\n\", psta->TDLS_PeerKey_Lifetime);\n#endif /* CONFIG_TDLS */\n\t\t\t\tRTW_PRINT_SEL(m, \"rx_data_uc_pkts=%llu\\n\", sta_rx_data_uc_pkts(psta));\n\t\t\t\tRTW_PRINT_SEL(m, \"rx_data_mc_pkts=%llu\\n\", psta->sta_stats.rx_data_mc_pkts);\n\t\t\t\tRTW_PRINT_SEL(m, \"rx_data_bc_pkts=%llu\\n\", psta->sta_stats.rx_data_bc_pkts);\n\t\t\t\tRTW_PRINT_SEL(m, \"rx_uc_bytes=%llu\\n\", sta_rx_uc_bytes(psta));\n\t\t\t\tRTW_PRINT_SEL(m, \"rx_mc_bytes=%llu\\n\", psta->sta_stats.rx_mc_bytes);\n\t\t\t\tRTW_PRINT_SEL(m, \"rx_bc_bytes=%llu\\n\", psta->sta_stats.rx_bc_bytes);\n\t\t\t\tif (psta->sta_stats.rx_tp_kbits >> 10)\n\t\t\t\t\tRTW_PRINT_SEL(m, \"rx_tp =%d (Mbps)\\n\", psta->sta_stats.rx_tp_kbits >> 10);\n\t\t\t\telse\n\t\t\t\t\tRTW_PRINT_SEL(m, \"rx_tp =%d (Kbps)\\n\", psta->sta_stats.rx_tp_kbits);\n\n\t\t\t\tRTW_PRINT_SEL(m, \"tx_data_pkts=%llu\\n\", psta->sta_stats.tx_pkts);\n\t\t\t\tRTW_PRINT_SEL(m, \"tx_bytes=%llu\\n\", psta->sta_stats.tx_bytes);\n\t\t\t\tif (psta->sta_stats.tx_tp_kbits >> 10)\n\t\t\t\t\tRTW_PRINT_SEL(m, \"tx_tp =%d (Mbps)\\n\", psta->sta_stats.tx_tp_kbits >> 10);\n\t\t\t\telse\n\t\t\t\t\tRTW_PRINT_SEL(m, \"tx_tp =%d (Kbps)\\n\", psta->sta_stats.tx_tp_kbits);\n#ifdef CONFIG_RTW_80211K\n\t\t\t\tRTW_PRINT_SEL(m, \"rm_en_cap=\"RM_CAP_FMT\"\\n\", RM_CAP_ARG(psta->rm_en_cap));\n#endif\n\t\t\t\tdump_st_ctl(m, &psta->st_ctl);\n\n\t\t\t\tif (STA_OP_WFD_MODE(psta))\n\t\t\t\t\tRTW_PRINT_SEL(m, \"op_wfd_mode:0x%02x\\n\", STA_OP_WFD_MODE(psta));\n\n\t\t\t\tRTW_PRINT_SEL(m, \"==============================\\n\");\n\t\t\t}\n\n\t\t}\n\n\t}\n\n\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\treturn 0;\n}\n\n#endif\n\n#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER\nint proc_get_rtkm_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct recv_priv\t*precvpriv = &padapter->recvpriv;\n\tstruct recv_buf *precvbuf;\n\n\tprecvbuf = (struct recv_buf *)precvpriv->precv_buf;\n\n\tRTW_PRINT_SEL(m, \"============[RTKM Info]============\\n\");\n\tRTW_PRINT_SEL(m, \"MAX_RTKM_NR_PREALLOC_RECV_SKB: %d\\n\", rtw_rtkm_get_nr_recv_skb());\n\tRTW_PRINT_SEL(m, \"MAX_RTKM_RECVBUF_SZ: %d\\n\", rtw_rtkm_get_buff_size());\n\n\tRTW_PRINT_SEL(m, \"============[Driver Info]============\\n\");\n\tRTW_PRINT_SEL(m, \"NR_PREALLOC_RECV_SKB: %d\\n\", NR_PREALLOC_RECV_SKB);\n\tRTW_PRINT_SEL(m, \"MAX_RECVBUF_SZ: %d\\n\", precvbuf->alloc_sz);\n\n\treturn 0;\n}\n#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */\n\n#ifdef DBG_MEMORY_LEAK\n#include <asm/atomic.h>\nextern atomic_t _malloc_cnt;;\nextern atomic_t _malloc_size;;\n\nint proc_get_malloc_cnt(struct seq_file *m, void *v)\n{\n\tRTW_PRINT_SEL(m, \"_malloc_cnt=%d\\n\", atomic_read(&_malloc_cnt));\n\tRTW_PRINT_SEL(m, \"_malloc_size=%d\\n\", atomic_read(&_malloc_size));\n\n\treturn 0;\n}\n#endif /* DBG_MEMORY_LEAK */\n\n#ifdef CONFIG_FIND_BEST_CHANNEL\nint proc_get_best_channel(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tu32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0;\n\n\tfor (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {\n\t\tif (rfctl->channel_set[i].ChannelNum == 1)\n\t\t\tindex_24G = i;\n\t\tif (rfctl->channel_set[i].ChannelNum == 36)\n\t\t\tindex_5G = i;\n\t}\n\n\tfor (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {\n\t\t/* 2.4G */\n\t\tif (rfctl->channel_set[i].ChannelNum == 6) {\n\t\t\tif (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_24G].rx_count) {\n\t\t\t\tindex_24G = i;\n\t\t\t\tbest_channel_24G = rfctl->channel_set[i].ChannelNum;\n\t\t\t}\n\t\t}\n\n\t\t/* 5G */\n\t\tif (rfctl->channel_set[i].ChannelNum >= 36\n\t\t    && rfctl->channel_set[i].ChannelNum < 140) {\n\t\t\t/* Find primary channel */\n\t\t\tif (((rfctl->channel_set[i].ChannelNum - 36) % 8 == 0)\n\t\t\t    && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {\n\t\t\t\tindex_5G = i;\n\t\t\t\tbest_channel_5G = rfctl->channel_set[i].ChannelNum;\n\t\t\t}\n\t\t}\n\n\t\tif (rfctl->channel_set[i].ChannelNum >= 149\n\t\t    && rfctl->channel_set[i].ChannelNum < 165) {\n\t\t\t/* find primary channel */\n\t\t\tif (((rfctl->channel_set[i].ChannelNum - 149) % 8 == 0)\n\t\t\t    && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {\n\t\t\t\tindex_5G = i;\n\t\t\t\tbest_channel_5G = rfctl->channel_set[i].ChannelNum;\n\t\t\t}\n\t\t}\n#if 1 /* debug */\n\t\tRTW_PRINT_SEL(m, \"The rx cnt of channel %3d = %d\\n\",\n\t\t\trfctl->channel_set[i].ChannelNum, rfctl->channel_set[i].rx_count);\n#endif\n\t}\n\n\tRTW_PRINT_SEL(m, \"best_channel_5G = %d\\n\", best_channel_5G);\n\tRTW_PRINT_SEL(m, \"best_channel_24G = %d\\n\", best_channel_24G);\n\n\treturn 0;\n}\n\nssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tchar tmp[32];\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint i;\n\t\tfor (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++)\n\t\t\trfctl->channel_set[i].rx_count = 0;\n\n\t\tRTW_INFO(\"set %s\\n\", \"Clean Best Channel Count\");\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_FIND_BEST_CHANNEL */\n\n#ifdef CONFIG_BT_COEXIST\nint proc_get_btcoex_dbg(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\tPADAPTER padapter;\n\tchar buf[512] = {0};\n\tpadapter = (PADAPTER)rtw_netdev_priv(dev);\n\n\trtw_btcoex_GetDBG(padapter, buf, 512);\n\n\t_RTW_PRINT_SEL(m, \"%s\", buf);\n\n\treturn 0;\n}\n\nssize_t proc_set_btcoex_dbg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\tPADAPTER padapter;\n\tu8 tmp[80] = {0};\n\tu32 module[2] = {0};\n\tu32 num;\n\n\tpadapter = (PADAPTER)rtw_netdev_priv(dev);\n\n\t/*\tRTW_INFO(\"+\" FUNC_ADPT_FMT \"\\n\", FUNC_ADPT_ARG(padapter)); */\n\n\tif (NULL == buffer) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input buffer is NULL!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter));\n\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is 0!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter));\n\n\t\treturn -EFAULT;\n\t}\n\n\tnum = count;\n\tif (num > (sizeof(tmp) - 1))\n\t\tnum = (sizeof(tmp) - 1);\n\n\tif (copy_from_user(tmp, buffer, num)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": copy buffer from user space FAIL!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter));\n\n\t\treturn -EFAULT;\n\t}\n\n\tnum = sscanf(tmp, \"%x %x\", module, module + 1);\n\tif (1 == num) {\n\t\tif (0 == module[0])\n\t\t\t_rtw_memset(module, 0, sizeof(module));\n\t\telse\n\t\t\t_rtw_memset(module, 0xFF, sizeof(module));\n\t} else if (2 != num) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input(\\\"%s\\\") format incorrect!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter), tmp);\n\n\t\tif (0 == num)\n\t\t\treturn -EFAULT;\n\t}\n\n\tRTW_INFO(FUNC_ADPT_FMT \": input 0x%08X 0x%08X\\n\",\n\t\t FUNC_ADPT_ARG(padapter), module[0], module[1]);\n\trtw_btcoex_SetDBG(padapter, module);\n\n\treturn count;\n}\n\nint proc_get_btcoex_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\tPADAPTER padapter;\n\tconst u32 bufsize = 40 * 100;\n\tu8 *pbuf = NULL;\n\n\tpadapter = (PADAPTER)rtw_netdev_priv(dev);\n\n\tpbuf = rtw_zmalloc(bufsize);\n\tif (NULL == pbuf)\n\t\treturn -ENOMEM;\n\n\trtw_btcoex_DisplayBtCoexInfo(padapter, pbuf, bufsize);\n\n\t_RTW_PRINT_SEL(m, \"%s\\n\", pbuf);\n\n\trtw_mfree(pbuf, bufsize);\n\n\treturn 0;\n}\n\n#ifdef CONFIG_RF4CE_COEXIST\nint proc_get_rf4ce_state(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8 state = 0, voice = 0;\n\n\tstate = rtw_btcoex_GetRf4ceLinkState(adapter);\n\n\tRTW_PRINT_SEL(m, \"RF4CE %s\\n\", state?\"Connected\":\"Disconnect\");\n\n\treturn 0;\n}\n\n/* This interface is designed for user space application to inform RF4CE state\n * Initial define for DHC 1295 E387 project\n *\n * echo state voice > rf4ce_state\n * state\n *\t0: RF4CE disconnected\n *\t1: RF4CE connected\n */\nssize_t proc_set_rf4ce_state(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu8 state;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhx\", &state);\n\n\t\tif (num >= 1)\n\t\t\trtw_btcoex_SetRf4ceLinkState(adapter, state);\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_RF4CE_COEXIST */\n#endif /* CONFIG_BT_COEXIST */\n\n#if defined(DBG_CONFIG_ERROR_DETECT)\nint proc_get_sreset(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv *psdpriv = padapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &psdpriv->drv_dbg;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct sreset_priv *psrtpriv = &pHalData->srestpriv;\n\n\tif (psrtpriv->dbg_sreset_ctrl == _TRUE) {\n\t\tRTW_PRINT_SEL(m, \"self_dect_tx_cnt:%llu\\n\", psrtpriv->self_dect_tx_cnt);\n\t\tRTW_PRINT_SEL(m, \"self_dect_rx_cnt:%llu\\n\", psrtpriv->self_dect_rx_cnt);\n\t\tRTW_PRINT_SEL(m, \"self_dect_fw_cnt:%llu\\n\", psrtpriv->self_dect_fw_cnt);\n\t\tRTW_PRINT_SEL(m, \"tx_dma_status_cnt:%llu\\n\", psrtpriv->tx_dma_status_cnt);\n\t\tRTW_PRINT_SEL(m, \"rx_dma_status_cnt:%llu\\n\", psrtpriv->rx_dma_status_cnt);\n\t\tRTW_PRINT_SEL(m, \"self_dect_case:%d\\n\", psrtpriv->self_dect_case);\n\t\tRTW_PRINT_SEL(m, \"dbg_sreset_cnt:%d\\n\", pdbgpriv->dbg_sreset_cnt);\n\t}\n\treturn 0;\n}\n\nssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct sreset_priv *psrtpriv = &pHalData->srestpriv;\n\tchar tmp[32];\n\ts32 trigger_point;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d\", &trigger_point);\n\n\t\tif (num < 1)\n\t\t\treturn count;\n\n\t\tif (trigger_point == SRESET_TGP_NULL)\n\t\t\trtw_hal_sreset_reset(padapter);\n\t\telse if (trigger_point == SRESET_TGP_INFO)\n\t\t\tpsrtpriv->dbg_sreset_ctrl = _TRUE;\n\t\telse\n\t\t\tsreset_set_trigger_point(padapter, trigger_point);\n\t}\n\n\treturn count;\n\n}\n#endif /* DBG_CONFIG_ERROR_DETECT */\n\n#ifdef CONFIG_PCI_HCI\n\nssize_t proc_set_pci_bridge_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct pci_dev  *pdev = pdvobjpriv->ppcidev;\n\tstruct pci_dev  *bridge_pdev = pdev->bus->self;\n\n\tchar tmp[32] = { 0 };\n\tint num;\n\n\tu32 reg = 0, value = 0;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tnum = sscanf(tmp, \"%x %x\", &reg, &value);\n\t\tif (num != 2) {\n\t\t\tRTW_INFO(\"invalid parameter!\\n\");\n\t\t\treturn count;\n\t\t}\n\n\t\tif (reg >= 0x1000) {\n\t\t\tRTW_INFO(\"invalid register!\\n\");\n\t\t\treturn count;\n\t\t}\n\n\t\tif (value > 0xFF) {\n\t\t\tRTW_INFO(\"invalid value! Only one byte\\n\");\n\t\t\treturn count;\n\t\t}\n\n\t\tRTW_INFO(FUNC_ADPT_FMT \": register 0x%x value 0x%x\\n\",\n\t\t\tFUNC_ADPT_ARG(padapter), reg, value);\n\n\t\tpci_write_config_byte(bridge_pdev, reg, value);\n\t}\n\treturn count;\n}\n\n\nint proc_get_pci_bridge_conf_space(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);\n\tstruct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct pci_dev  *pdev = pdvobjpriv->ppcidev;\n\tstruct pci_dev  *bridge_pdev = pdev->bus->self;\n\n\tu32 tmp[4] = { 0 };\n\tu32 i, j;\n\n\tRTW_PRINT_SEL(m, \"\\n*****  PCI Host Device Configuration Space*****\\n\\n\");\n\n\tfor (i = 0; i < 0x1000; i += 0x10) {\n\t\tfor (j = 0 ; j < 4 ; j++)\n\t\t\tpci_read_config_dword(bridge_pdev, i + j * 4, tmp+j);\n\n\t\tRTW_PRINT_SEL(m, \"%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\\n\",\n\t\t\ti, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,\n\t\t\ttmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,\n\t\t\ttmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,\n\t\t\ttmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);\n\t}\n\treturn 0;\n}\n\n\nssize_t proc_set_pci_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct pci_dev  *pdev = pdvobjpriv->ppcidev;\n\n\tchar tmp[32] = { 0 };\n\tint num;\n\n\tu32 reg = 0, value = 0;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tnum = sscanf(tmp, \"%x %x\", &reg, &value);\n\n\t\tif (num != 2) {\n\t\t\tRTW_INFO(\"invalid parameter!\\n\");\n\t\t\treturn count;\n\t\t}\n\n\n\t\tif (reg >= 0x1000) {\n\t\t\tRTW_INFO(\"invalid register!\\n\");\n\t\t\treturn count;\n\t\t}\n\n\t\tif (value > 0xFF) {\n\t\t\tRTW_INFO(\"invalid value! Only one byte\\n\");\n\t\t\treturn count;\n\t\t}\n\n\t\tRTW_INFO(FUNC_ADPT_FMT \": register 0x%x value 0x%x\\n\",\n\t\t\tFUNC_ADPT_ARG(padapter), reg, value);\n\n\t\tpci_write_config_byte(pdev, reg, value);\n\n\n\t}\n\treturn count;\n}\n\n\nint proc_get_pci_conf_space(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);\n\tstruct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct pci_dev  *pdev = pdvobjpriv->ppcidev;\n\tstruct pci_dev  *bridge_pdev = pdev->bus->self;\n\n\tu32 tmp[4] = { 0 };\n\tu32 i, j;\n\n\tRTW_PRINT_SEL(m, \"\\n*****  PCI Device Configuration Space *****\\n\\n\");\n\n\tfor (i = 0; i < 0x1000; i += 0x10) {\n\t\tfor (j = 0 ; j < 4 ; j++)\n\t\t\tpci_read_config_dword(pdev, i + j * 4, tmp+j);\n\n\t\tRTW_PRINT_SEL(m, \"%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\\n\",\n\t\t\ti, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,\n\t\t\ttmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,\n\t\t\ttmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,\n\t\t\ttmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);\n\t}\n\n\treturn 0;\n}\n\n\nint proc_get_pci_aspm(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct pci_priv\t*pcipriv = &(pdvobjpriv->pcipriv);\n\tu8 tmp8 = 0;\n\tu16 tmp16 = 0;\n\tu32 tmp32 = 0;\n\tu8 l1_idle = 0;\n\n\n\tRTW_PRINT_SEL(m, \"***** ASPM Capability *****\\n\");\n\n\tpci_read_config_dword(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCAP, &tmp32);\n\n\tRTW_PRINT_SEL(m, \"CLK REQ:\t%s\\n\", (tmp32&PCI_EXP_LNKCAP_CLKPM) ? \"Enable\" : \"Disable\");\n\tRTW_PRINT_SEL(m, \"ASPM L0s:\t%s\\n\", (tmp32&BIT10) ? \"Enable\" : \"Disable\");\n\tRTW_PRINT_SEL(m, \"ASPM L1:\t%s\\n\", (tmp32&BIT11) ? \"Enable\" : \"Disable\");\n\n\ttmp8 = rtw_hal_pci_l1off_capability(padapter);\n\tRTW_PRINT_SEL(m, \"ASPM L1OFF:\t%s\\n\", tmp8 ? \"Enable\" : \"Disable\");\n\n\tRTW_PRINT_SEL(m, \"***** ASPM CTRL Reg *****\\n\");\n\n\tpci_read_config_word(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCTL, &tmp16);\n\n\tRTW_PRINT_SEL(m, \"CLK REQ:\t%s\\n\", (tmp16&PCI_EXP_LNKCTL_CLKREQ_EN) ? \"Enable\" : \"Disable\");\n\tRTW_PRINT_SEL(m, \"ASPM L0s:\t%s\\n\", (tmp16&BIT0) ? \"Enable\" : \"Disable\");\n\tRTW_PRINT_SEL(m, \"ASPM L1:\t%s\\n\", (tmp16&BIT1) ? \"Enable\" : \"Disable\");\n\n\ttmp8 = rtw_hal_pci_l1off_nic_support(padapter);\n\tRTW_PRINT_SEL(m, \"ASPM L1OFF:\t%s\\n\", tmp8 ? \"Enable\" : \"Disable\");\n\n\tRTW_PRINT_SEL(m, \"***** ASPM Backdoor *****\\n\");\n\n\ttmp8 = rtw_hal_pci_dbi_read(padapter, 0x719);\n\tRTW_PRINT_SEL(m, \"CLK REQ:\t%s\\n\", (tmp8 & BIT4) ? \"Enable\" : \"Disable\");\n\n\ttmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f);\n\tl1_idle = tmp8 & 0x38;\n\tRTW_PRINT_SEL(m, \"ASPM L0s:\t%s\\n\", (tmp8&BIT7) ? \"Enable\" : \"Disable\");\n\n\ttmp8 = rtw_hal_pci_dbi_read(padapter, 0x719);\n\tRTW_PRINT_SEL(m, \"ASPM L1:\t%s\\n\", (tmp8 & BIT3) ? \"Enable\" : \"Disable\");\n\n\ttmp8 = rtw_hal_pci_dbi_read(padapter, 0x718);\n\tRTW_PRINT_SEL(m, \"ASPM L1OFF:\t%s\\n\", (tmp8 & BIT5) ? \"Enable\" : \"Disable\");\n\n\tRTW_PRINT_SEL(m, \"********* MISC **********\\n\");\n\tRTW_PRINT_SEL(m, \"ASPM L1 Idel Time: 0x%x\\n\", l1_idle>>3);\n\tRTW_PRINT_SEL(m, \"*************************\\n\");\n\n\treturn 0;\n}\n\nint proc_get_rx_ring(struct seq_file *m, void *v)\n{\n\t_irqL irqL;\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct recv_priv *precvpriv = &padapter->recvpriv;\n\tstruct rtw_rx_ring *rx_ring = &precvpriv->rx_ring[RX_MPDU_QUEUE];\n\tint i, j;\n\n\tRTW_PRINT_SEL(m, \"rx ring (%p)\\n\", rx_ring);\n\tRTW_PRINT_SEL(m, \"  dma: 0x%08x\\n\", (int) rx_ring->dma);\n\tRTW_PRINT_SEL(m, \"  idx: %d\\n\", rx_ring->idx);\n\n\t_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);\n\tfor (i = 0; i < precvpriv->rxringcount; i++) {\n#ifdef CONFIG_TRX_BD_ARCH\n\t\tstruct rx_buf_desc *entry = &rx_ring->buf_desc[i];\n#else\n\t\tstruct recv_stat *entry = &rx_ring->desc[i];\n#endif\n\t\tstruct sk_buff *skb = rx_ring->rx_buf[i];\n\n\t\tRTW_PRINT_SEL(m, \"  desc[%03d]: %p, rx_buf[%03d]: 0x%08x\\n\",\n\t\t\ti, entry, i, cpu_to_le32(*((dma_addr_t *)skb->cb)));\n\n\t\tfor (j = 0; j < sizeof(*entry) / 4; j++) {\n\t\t\tif ((j % 4) == 0)\n\t\t\t\tRTW_PRINT_SEL(m, \"  0x%03x\", j);\n\n\t\t\tRTW_PRINT_SEL(m, \" 0x%08x \", ((int *) entry)[j]);\n\n\t\t\tif ((j % 4) == 3)\n\t\t\t\tRTW_PRINT_SEL(m, \"\\n\");\n\t\t}\n\t}\n\t_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);\n\n\treturn 0;\n}\n\nint proc_get_tx_ring(struct seq_file *m, void *v)\n{\n\t_irqL irqL;\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tint i, j, k;\n\n\t_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);\n\tfor (i = 0; i < PCI_MAX_TX_QUEUE_COUNT; i++) {\n\t\tstruct rtw_tx_ring *tx_ring = &pxmitpriv->tx_ring[i];\n\n\t\tRTW_PRINT_SEL(m, \"tx ring[%d] (%p)\\n\", i, tx_ring);\n\t\tRTW_PRINT_SEL(m, \"  dma: 0x%08x\\n\", (int) tx_ring->dma);\n\t\tRTW_PRINT_SEL(m, \"  idx: %d\\n\", tx_ring->idx);\n\t\tRTW_PRINT_SEL(m, \"  entries: %d\\n\", tx_ring->entries);\n\t\t/*\t\tRTW_PRINT_SEL(m, \"  queue: %d\\n\", tx_ring->queue); */\n\t\tRTW_PRINT_SEL(m, \"  qlen: %d\\n\", tx_ring->qlen);\n\n\t\tfor (j = 0; j < pxmitpriv->txringcount[i]; j++) {\n#ifdef CONFIG_TRX_BD_ARCH\n\t\t\tstruct tx_buf_desc *entry = &tx_ring->buf_desc[j];\n\t\t\tRTW_PRINT_SEL(m, \"  buf_desc[%03d]: %p\\n\", j, entry);\n#else\n\t\t\tstruct tx_desc *entry = &tx_ring->desc[j];\n\t\t\tRTW_PRINT_SEL(m, \"  desc[%03d]: %p\\n\", j, entry);\n#endif\n\n\t\t\tfor (k = 0; k < sizeof(*entry) / 4; k++) {\n\t\t\t\tif ((k % 4) == 0)\n\t\t\t\t\tRTW_PRINT_SEL(m, \"  0x%03x\", k);\n\n\t\t\t\tRTW_PRINT_SEL(m, \" 0x%08x \", ((int *) entry)[k]);\n\n\t\t\t\tif ((k % 4) == 3)\n\t\t\t\t\tRTW_PRINT_SEL(m, \"\\n\");\n\t\t\t}\n\t\t}\n\t}\n\t_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);\n\n\treturn 0;\n}\n\n#ifdef DBG_TXBD_DESC_DUMP\nint proc_get_tx_ring_ext(struct seq_file *m, void *v)\n{\n\t_irqL irqL;\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tstruct rtw_tx_desc_backup *pbuf;\n\tint i, j, k, idx;\n\n\tRTW_PRINT_SEL(m, \"<<<< tx ring ext dump settings >>>>\\n\");\n\tRTW_PRINT_SEL(m, \" - backup frame num: %d\\n\", TX_BAK_FRMAE_CNT);\n\tRTW_PRINT_SEL(m, \" - backup max. desc size: %d bytes\\n\", TX_BAK_DESC_LEN);\n\tRTW_PRINT_SEL(m, \" - backup data size: %d bytes\\n\\n\", TX_BAK_DATA_LEN);\n\n\tif (!pxmitpriv->dump_txbd_desc) {\n\t\tRTW_PRINT_SEL(m, \"Dump function is disabled.\\n\");\n\t\treturn 0;\n\t}\n\n\t_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);\n\tfor (i = 0; i < HW_QUEUE_ENTRY; i++) {\n\t\tstruct rtw_tx_ring *tx_ring = &pxmitpriv->tx_ring[i];\n\n\t\tidx = rtw_get_tx_desc_backup(padapter, i, &pbuf);\n\n\t\tRTW_PRINT_SEL(m, \"Tx ring[%d]\", i);\n\t\tswitch (i) {\n\t\tcase 0:\n\t\t\tRTW_PRINT_SEL(m, \" (VO)\\n\");\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tRTW_PRINT_SEL(m, \" (VI)\\n\");\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tRTW_PRINT_SEL(m, \" (BE)\\n\");\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\tRTW_PRINT_SEL(m, \" (BK)\\n\");\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\tRTW_PRINT_SEL(m, \" (BCN)\\n\");\n\t\t\tbreak;\n\t\tcase 5:\n\t\t\tRTW_PRINT_SEL(m, \" (MGT)\\n\");\n\t\t\tbreak;\n\t\tcase 6:\n\t\t\tRTW_PRINT_SEL(m, \" (HIGH)\\n\");\n\t\t\tbreak;\n\t\tcase 7:\n\t\t\tRTW_PRINT_SEL(m, \" (TXCMD)\\n\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tRTW_PRINT_SEL(m, \" (?)\\n\");\n\t\t\tbreak;\n\t\t}\n\n\t\tRTW_PRINT_SEL(m, \"  Entries: %d\\n\", TX_BAK_FRMAE_CNT);\n\t\tRTW_PRINT_SEL(m, \"  Last idx: %d\\n\", idx);\n\n\t\tfor (j = 0; j < TX_BAK_FRMAE_CNT; j++) {\n\t\t\tRTW_PRINT_SEL(m, \"  desc[%03d]:\\n\", j);\n\n\t\t\tfor (k = 0; k < (pbuf->tx_desc_size) / 4; k++) {\n\t\t\t\tif ((k % 4) == 0)\n\t\t\t\t\tRTW_PRINT_SEL(m, \"  0x%03x\", k);\n\n\t\t\t\tRTW_PRINT_SEL(m, \" 0x%08x \", ((int *)pbuf->tx_bak_desc)[k]);\n\n\t\t\t\tif ((k % 4) == 3)\n\t\t\t\t\tRTW_PRINT_SEL(m, \"\\n\");\n\t\t\t}\n\n#if 1 /* data dump */\n\t\t\tif (pbuf->tx_desc_size) {\n\t\t\t\tRTW_PRINT_SEL(m, \"  data[%03d]:\\n\", j);\n\n\t\t\t\tfor (k = 0; k < (TX_BAK_DATA_LEN) / 4; k++) {\n\t\t\t\t\tif ((k % 4) == 0)\n\t\t\t\t\t\tRTW_PRINT_SEL(m, \"  0x%03x\", k);\n\n\t\t\t\t\tRTW_PRINT_SEL(m, \" 0x%08x \", ((int *)pbuf->tx_bak_data_hdr)[k]);\n\n\t\t\t\t\tif ((k % 4) == 3)\n\t\t\t\t\t\tRTW_PRINT_SEL(m, \"\\n\");\n\t\t\t\t}\n\t\t\t\tRTW_PRINT_SEL(m, \"\\n\");\n\t\t\t}\n#endif\n\n\t\t\tRTW_PRINT_SEL(m, \"  R/W pointer: %d/%d\\n\", pbuf->tx_bak_rp, pbuf->tx_bak_wp);\n\n\t\t\tpbuf = pbuf + 1;\n\t\t}\n\t\tRTW_PRINT_SEL(m, \"\\n\");\n\t}\n\t_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);\n\n\treturn 0;\n}\n\nssize_t proc_set_tx_ring_ext(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\t_irqL irqL;\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\tchar tmp[32];\n\tu32 reset = 0;\n\tu32 dump = 0;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%u %u\", &dump, &reset);\n\n\t\tif (num != 2) {\n\t\t\tRTW_INFO(\"invalid parameter!\\n\");\n\t\t\treturn count;\n\t\t}\n\n\t\t_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);\n\t\tpxmitpriv->dump_txbd_desc = (BOOLEAN) dump;\n\n\t\tif (reset == 1)\n\t\t\trtw_tx_desc_backup_reset();\n\n\t\t_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);\n\n\t}\n\n\treturn count;\n}\n\n#endif\n\n#endif\n\n#ifdef CONFIG_WOWLAN\nint proc_get_pattern_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tstruct registry_priv *pregistrypriv = &padapter->registrypriv;\n\tu8 pattern_num = 0, val8;\n\tchar str_1[128];\n\tchar *p_str;\n\tint i = 0 , j = 0, k = 0;\n\tint len = 0, max_len = 0, total = 0;\n\n\tp_str = str_1;\n\tmax_len = sizeof(str_1);\n\n\ttotal = pwrpriv->wowlan_pattern_idx;\n\n\trtw_set_default_pattern(padapter);\n\n\t/*show pattern*/\n\tRTW_PRINT_SEL(m, \"\\n======[Pattern Info.]======\\n\");\n\tRTW_PRINT_SEL(m, \"pattern number: %d\\n\", total);\n\tRTW_PRINT_SEL(m, \"support default patterns: %c\\n\",\n\t\t      (pwrpriv->default_patterns_en) ? 'Y' : 'N');\n\n\tfor (k = 0; k < total ; k++) {\n\t\tRTW_PRINT_SEL(m, \"\\npattern idx: %d\\n\", k);\n\t\tRTW_PRINT_SEL(m, \"pattern content:\\n\");\n\n\t\tp_str = str_1;\n\t\tmax_len = sizeof(str_1);\n\t\tfor (i = 0 ; i < MAX_WKFM_PATTERN_SIZE / 8 ; i++) {\n\t\t\t_rtw_memset(p_str, 0, max_len);\n\t\t\tlen = 0;\n\t\t\tfor (j = 0 ; j < 8 ; j++) {\n\t\t\t\tval8 = pwrpriv->patterns[k].content[i * 8 + j];\n\t\t\t\tlen += snprintf(p_str + len, max_len - len,\n\t\t\t\t\t\t\"%02x \", val8);\n\t\t\t}\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", p_str);\n\t\t}\n\t\tRTW_PRINT_SEL(m, \"\\npattern mask:\\n\");\n\t\tfor (i = 0 ; i < MAX_WKFM_SIZE / 8 ; i++) {\n\t\t\t_rtw_memset(p_str, 0, max_len);\n\t\t\tlen = 0;\n\t\t\tfor (j = 0 ; j < 8 ; j++) {\n\t\t\t\tval8 = pwrpriv->patterns[k].mask[i * 8 + j];\n\t\t\t\tlen += snprintf(p_str + len, max_len - len,\n\t\t\t\t\t\t\"%02x \", val8);\n\t\t\t}\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", p_str);\n\t\t}\n\n\t\tRTW_PRINT_SEL(m, \"\\npriv_pattern_len:\\n\");\n\t\tRTW_PRINT_SEL(m, \"pattern_len: %d\\n\", pwrpriv->patterns[k].len);\n\t\tRTW_PRINT_SEL(m, \"*****************\\n\");\n\t}\n\n\treturn 0;\n}\n\nssize_t proc_set_pattern_info(struct file *file, const char __user *buffer,\n\t\t\t      size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tstruct wowlan_ioctl_param poidparam;\n\tu8 tmp[MAX_WKFM_PATTERN_SIZE] = {0};\n\tint ret = 0, num = 0;\n\tu8 index = 0;\n\n\tpoidparam.subcode = 0;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (pwrpriv->wowlan_pattern_idx >= MAX_WKFM_CAM_NUM) {\n\t\tRTW_INFO(\"WARNING: priv-pattern is full(idx: %d)\\n\",\n\t\t\t pwrpriv->wowlan_pattern_idx);\n\t\tRTW_INFO(\"WARNING: please clean priv-pattern first\\n\");\n\t\treturn -ENOMEM;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tif (strncmp(tmp, \"clean\", 5) == 0) {\n\t\t\tpoidparam.subcode = WOWLAN_PATTERN_CLEAN;\n\t\t\trtw_hal_set_hwreg(padapter,\n\t\t\t\t\t  HW_VAR_WOWLAN, (u8 *)&poidparam);\n\t\t} else {\n\t\t\tindex = pwrpriv->wowlan_pattern_idx;\n\t\t\tret = rtw_wowlan_parser_pattern_cmd(tmp,\n\t\t\t\t\t    pwrpriv->patterns[index].content,\n\t\t\t\t\t    &pwrpriv->patterns[index].len,\n\t\t\t\t\t    pwrpriv->patterns[index].mask);\n\t\t\tif (ret == _TRUE)\n\t\t\t\tpwrpriv->wowlan_pattern_idx++;\n\t\t}\n\t}\n\n\treturn count;\n}\n\nint proc_get_wakeup_event(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv  *registry_par = &padapter->registrypriv;\n\n\tRTW_PRINT_SEL(m, \"wakeup event: %#02x\\n\", registry_par->wakeup_event);\n\treturn 0;\n}\n\nssize_t proc_set_wakeup_event(struct file *file, const char __user *buffer,\n\t\t\t      size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n\tstruct registry_priv  *registry_par = &padapter->registrypriv;\n\tu32 wakeup_event = 0;\n\n\tu8 tmp[8] = {0};\n\tint ret = 0, num = 0;\n\tu8 index = 0;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count))\n\t\tnum = sscanf(tmp, \"%u\", &wakeup_event);\n\telse\n\t\treturn -EFAULT;\n\n\tif (num == 1 && wakeup_event <= 0x07) {\n\t\tregistry_par->wakeup_event = wakeup_event;\n\n\t\tif (wakeup_event & BIT(1))\n\t\t\tpwrctrlpriv->default_patterns_en = _TRUE;\n\t\telse\n\t\t\tpwrctrlpriv->default_patterns_en = _FALSE;\n\n\t\trtw_wow_pattern_sw_reset(padapter);\n\n\t\tRTW_INFO(\"%s: wakeup_event: %#2x, default pattern: %d\\n\",\n\t\t\t __func__, registry_par->wakeup_event,\n\t\t\t pwrctrlpriv->default_patterns_en);\n\t} else {\n\t\treturn -EINVAL;\n\t}\n\n\treturn count;\n}\n\nint proc_get_wakeup_reason(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tu8 val = pwrpriv->wowlan_last_wake_reason;\n\n\tRTW_PRINT_SEL(m, \"last wake reason: %#02x\\n\", val);\n\treturn 0;\n}\n#endif /*CONFIG_WOWLAN*/\n\n#ifdef CONFIG_GPIO_WAKEUP\nint proc_get_wowlan_gpio_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tu8 val = pwrpriv->is_high_active;\n\n\tRTW_PRINT_SEL(m, \"wakeup_gpio_idx: %d\\n\", WAKEUP_GPIO_IDX);\n\tRTW_PRINT_SEL(m, \"high_active: %d\\n\", val);\n\n\treturn 0;\n}\n\nssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer,\n\t\t\t\t  size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tchar tmp[32] = {0};\n\tint num = 0;\n\tu32 is_high_active = 0;\n\tu8 val8 = 0;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tnum = sscanf(tmp, \"%u\", &is_high_active);\n\n\t\tif (num != 1) {\n\t\t\tRTW_INFO(\"Invalid format\\n\");\n\t\t\treturn count;\n\t\t}\n\n\t\tis_high_active = is_high_active == 0 ? 0 : 1;\n\n\t\tpwrpriv->is_high_active = is_high_active;\n\n\t\trtw_ps_deny(padapter, PS_DENY_IOCTL);\n\t\tLeaveAllPowerSaveModeDirect(padapter);\n\n\t\t#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE\n\t\tif (pwrpriv->is_high_active == 0)\n\t\t\trtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX);\n\t\telse\n\t\t\trtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, 0);\n\t\t#else\n\t\tval8 = (pwrpriv->is_high_active == 0) ? 1 : 0;\n\t\trtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _TRUE);\n\t\trtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8);\n\t\t#endif\n\t\trtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);\n\n\t\tRTW_INFO(\"set %s %d\\n\", \"gpio_high_active\",\n\t\t\t pwrpriv->is_high_active);\n\t\tRTW_INFO(\"%s: set GPIO_%d %d as default.\\n\",\n\t\t\t __func__, WAKEUP_GPIO_IDX, val8);\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_GPIO_WAKEUP */\n\n#ifdef CONFIG_P2P_WOWLAN\nint proc_get_p2p_wowlan_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\tstruct p2p_wowlan_info\t peerinfo = pwdinfo->p2p_wow_info;\n\tif (_TRUE == peerinfo.is_trigger) {\n\t\tRTW_PRINT_SEL(m, \"is_trigger: TRUE\\n\");\n\t\tswitch (peerinfo.wowlan_recv_frame_type) {\n\t\tcase P2P_WOWLAN_RECV_NEGO_REQ:\n\t\t\tRTW_PRINT_SEL(m, \"Frame Type: Nego Request\\n\");\n\t\t\tbreak;\n\t\tcase P2P_WOWLAN_RECV_INVITE_REQ:\n\t\t\tRTW_PRINT_SEL(m, \"Frame Type: Invitation Request\\n\");\n\t\t\tbreak;\n\t\tcase P2P_WOWLAN_RECV_PROVISION_REQ:\n\t\t\tRTW_PRINT_SEL(m, \"Frame Type: Provision Request\\n\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t\tRTW_PRINT_SEL(m, \"Peer Addr: \"MAC_FMT\"\\n\", MAC_ARG(peerinfo.wowlan_peer_addr));\n\t\tRTW_PRINT_SEL(m, \"Peer WPS Config: %x\\n\", peerinfo.wowlan_peer_wpsconfig);\n\t\tRTW_PRINT_SEL(m, \"Persistent Group: %d\\n\", peerinfo.wowlan_peer_is_persistent);\n\t\tRTW_PRINT_SEL(m, \"Intivation Type: %d\\n\", peerinfo.wowlan_peer_invitation_type);\n\t} else\n\t\tRTW_PRINT_SEL(m, \"is_trigger: False\\n\");\n\treturn 0;\n}\n#endif /* CONFIG_P2P_WOWLAN */\n#ifdef CONFIG_BCN_CNT_CONFIRM_HDL\nint proc_get_new_bcn_max(struct seq_file *m, void *v)\n{\n\textern int new_bcn_max;\n\n\tRTW_PRINT_SEL(m, \"%d\", new_bcn_max);\n\treturn 0;\n}\n\nssize_t proc_set_new_bcn_max(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tchar tmp[32];\n\textern int new_bcn_max;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count))\n\t\tsscanf(tmp, \"%d \", &new_bcn_max);\n\n\treturn count;\n}\n#endif\n#ifdef CONFIG_POWER_SAVING\nint proc_get_ps_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tu8 ips_mode = pwrpriv->ips_mode_req;\n\tu8 lps_mode = pwrpriv->power_mgnt;\n\tu8 lps_level = pwrpriv->lps_level;\n#ifdef CONFIG_LPS_1T1R\n\tu8 lps_1t1r = pwrpriv->lps_1t1r;\n#endif\n#ifdef CONFIG_WOWLAN\n\tu8 wow_lps_mode = pwrpriv->wowlan_power_mgmt;\n\tu8 wow_lps_level = pwrpriv->wowlan_lps_level;\n\t#ifdef CONFIG_LPS_1T1R\n\tu8 wow_lps_1t1r = pwrpriv->wowlan_lps_1t1r;\n\t#endif\n#endif /* CONFIG_WOWLAN */\n\tchar *str = \"\";\n\n\tRTW_PRINT_SEL(m, \"======Power Saving Info:======\\n\");\n\tRTW_PRINT_SEL(m, \"*IPS:\\n\");\n\n\tif (ips_mode == IPS_NORMAL) {\n#ifdef CONFIG_FWLPS_IN_IPS\n\t\tstr = \"FW_LPS_IN_IPS\";\n#else\n\t\tstr = \"Card Disable\";\n#endif\n\t} else if (ips_mode == IPS_NONE)\n\t\tstr = \"NO IPS\";\n\telse if (ips_mode == IPS_LEVEL_2)\n\t\tstr = \"IPS_LEVEL_2\";\n\telse\n\t\tstr = \"invalid ips_mode\";\n\n\tRTW_PRINT_SEL(m, \" IPS mode: %s\\n\", str);\n\tRTW_PRINT_SEL(m, \" IPS enter count:%d, IPS leave count:%d\\n\",\n\t\t      pwrpriv->ips_enter_cnts, pwrpriv->ips_leave_cnts);\n\tRTW_PRINT_SEL(m, \"------------------------------\\n\");\n\tRTW_PRINT_SEL(m, \"*LPS:\\n\");\n\n\tif (lps_mode == PS_MODE_ACTIVE)\n\t\tstr = \"NO LPS\";\n\telse if (lps_mode == PS_MODE_MIN)\n\t\tstr = \"MIN\";\n\telse if (lps_mode == PS_MODE_MAX)\n\t\tstr = \"MAX\";\n\telse if (lps_mode == PS_MODE_DTIM)\n\t\tstr = \"DTIM\";\n\telse\n\t\tsprintf(str, \"%d\", lps_mode);\n\n\tRTW_PRINT_SEL(m, \" LPS mode: %s\\n\", str);\n\n\tif (pwrpriv->dtim != 0)\n\t\tRTW_PRINT_SEL(m, \" DTIM: %d\\n\", pwrpriv->dtim);\n\tRTW_PRINT_SEL(m, \" LPS enter count:%d, LPS leave count:%d\\n\",\n\t\t      pwrpriv->lps_enter_cnts, pwrpriv->lps_leave_cnts);\n\n\tif (lps_level == LPS_LCLK)\n\t\tstr = \"LPS_LCLK\";\n\telse if  (lps_level == LPS_PG)\n\t\tstr = \"LPS_PG\";\n\telse\n\t\tstr = \"LPS_NORMAL\";\n\tRTW_PRINT_SEL(m, \" LPS level: %s\\n\", str);\n\n#ifdef CONFIG_LPS_1T1R\n\tRTW_PRINT_SEL(m, \" LPS 1T1R: %d\\n\", lps_1t1r);\n#endif\n\n#ifdef CONFIG_WOWLAN\n\tRTW_PRINT_SEL(m, \"------------------------------\\n\");\n\tRTW_PRINT_SEL(m, \"*WOW LPS:\\n\");\n\n\tif (wow_lps_mode == PS_MODE_ACTIVE)\n\t\tstr = \"NO LPS\";\n\telse if (wow_lps_mode == PS_MODE_MIN)\n\t\tstr = \"MIN\";\n\telse if (wow_lps_mode == PS_MODE_MAX)\n\t\tstr = \"MAX\";\n\telse if (wow_lps_mode == PS_MODE_DTIM)\n\t\tstr = \"DTIM\";\n\telse\n\t\tsprintf(str, \"%d\", wow_lps_mode);\n\n\tRTW_PRINT_SEL(m, \" WOW LPS mode: %s\\n\", str);\n\n\tif (wow_lps_level == LPS_LCLK)\n\t\tstr = \"LPS_LCLK\";\n\telse if  (wow_lps_level == LPS_PG)\n\t\tstr = \"LPS_PG\";\n\telse\n\t\tstr = \"LPS_NORMAL\";\n\tRTW_PRINT_SEL(m, \" WOW LPS level: %s\\n\", str);\n\n\t#ifdef CONFIG_LPS_1T1R\n\tRTW_PRINT_SEL(m, \" WOW LPS 1T1R: %d\\n\", wow_lps_1t1r);\n\t#endif\n#endif /* CONFIG_WOWLAN */\n\n\tRTW_PRINT_SEL(m, \"=============================\\n\");\n\treturn 0;\n}\n\nssize_t proc_set_ps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\tstruct _ADAPTER *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tchar tmp[8];\n\tint num = 0;\n\tint mode = 0;\n\tint en = 0;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (!buffer || copy_from_user(tmp, buffer, count))\n\t\tgoto exit;\n\n\tnum = sscanf(tmp, \"%d %d\", &mode, &en);\n\tif (num >  2) {\n\t\tRTW_ERR(\"%s: invalid parameter!\\n\", __FUNCTION__);\n\t\tgoto exit;\n\t}\n\n\tif (num == 1 && mode == 0) {\n\t\t/* back to original LPS/IPS Mode */\n\t\tRTW_INFO(\"%s: back to original LPS/IPS Mode\\n\", __FUNCTION__);\n\n\t\trtw_pm_set_lps(adapter, adapter->registrypriv.power_mgnt);\n\t\t\n\t\trtw_pm_set_ips(adapter, adapter->registrypriv.ips_mode);\n\n#ifdef CONFIG_WOWLAN\n\t\tRTW_INFO(\"%s: back to original WOW LPS Mode\\n\", __FUNCTION__);\n\n\t\trtw_pm_set_wow_lps(adapter, adapter->registrypriv.wow_power_mgnt);\n#endif /* CONFIG_WOWLAN */\n\n\t\tgoto exit;\n\t}\n\t\n\tif (mode == 1) { \n\t\t/* LPS */\n\t\tRTW_INFO(\"%s: LPS: %s, en=%d\\n\", __FUNCTION__, (en == 0) ? \"disable\":\"enable\", en);\t\n\t\tif (rtw_pm_set_lps(adapter, en) != 0 )\n\t\t\tRTW_ERR(\"%s: invalid parameter, mode=%d, level=%d\\n\", __FUNCTION__, mode, en);\n\t\t\n\t} else if (mode == 2) {\n\t\t/* IPS */\n\t\tRTW_INFO(\"%s: IPS: %s, en=%d\\n\", __FUNCTION__, (en == 0) ? \"disable\":\"enable\", en);\t\n\t\tif (rtw_pm_set_ips(adapter, en) != 0 )\n\t\t\tRTW_ERR(\"%s: invalid parameter, mode=%d, level=%d\\n\", __FUNCTION__, mode, en);\n\t}\n#ifdef CONFIG_WOWLAN\n\telse if (mode == 3) {\n\t\t/* WOW LPS */\n\t\tRTW_INFO(\"%s: WOW LPS: %s, en=%d\\n\", __FUNCTION__, (en == 0) ? \"disable\":\"enable\", en);\n\t\tif (rtw_pm_set_wow_lps(adapter, en) != 0 )\n\t\t\tRTW_ERR(\"%s: invalid parameter, mode=%d, level=%d\\n\", __FUNCTION__, mode, en);\n\t}\n#endif /* CONFIG_WOWLAN */\n\telse\n\t\tRTW_ERR(\"%s: invalid parameter, mode = %d!\\n\", __FUNCTION__, mode);\n\nexit:\n\treturn count;\n}\n\n#ifdef CONFIG_WMMPS_STA\nint proc_get_wmmps_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\tchar *uapsd_max_sp_str=\"\";\n\n\tif (pregpriv){\n\t\tswitch(pregpriv->uapsd_max_sp_len) {\n\t\t\tcase 0:\n\t\t\t\tuapsd_max_sp_str = \"NO_LIMIT\";\n\t\t\t\tbreak;\n\t\t\tcase 1:\n\t\t\t\tuapsd_max_sp_str = \"TWO_MSDU\";\n\t\t\t\tbreak;\n\t\t\tcase 2:\n\t\t\t\tuapsd_max_sp_str = \"FOUR_MSDU\";\n\t\t\t\tbreak;\n\t\t\tcase 3:\n\t\t\t\tuapsd_max_sp_str = \"SIX_MSDU\";\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tuapsd_max_sp_str = \"UNSPECIFIED\";\n\t\t\t\tbreak;\n\t\t}\n\n\t\tRTW_PRINT_SEL(m, \"====== WMMPS_STA Info:======\\n\");\n\t\tRTW_PRINT_SEL(m, \"uapsd_max_sp_len=0x%02x (%s)\\n\", pregpriv->uapsd_max_sp_len, uapsd_max_sp_str);\n\t\tRTW_PRINT_SEL(m, \"uapsd_ac_enable=0x%02x\\n\", pregpriv->uapsd_ac_enable);\n\t\tRTW_PRINT_SEL(m, \"BIT0 - AC_VO UAPSD: %s\\n\", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VO) ? \"Enabled\" : \"Disabled\");\n\t\tRTW_PRINT_SEL(m, \"BIT1 - AC_VI UAPSD: %s\\n\", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VI) ? \"Enabled\" : \"Disabled\");\n\t\tRTW_PRINT_SEL(m, \"BIT2 - AC_BK UAPSD: %s\\n\", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BK) ? \"Enabled\" : \"Disabled\");\n\t\tRTW_PRINT_SEL(m, \"BIT3 - AC_BE UAPSD: %s\\n\", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BE) ? \"Enabled\" : \"Disabled\");\n\t\tRTW_PRINT_SEL(m, \"============================\\n\");\n\t}\n\n\treturn 0;\n}\n\nssize_t proc_set_wmmps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\tchar tmp[32];\n\tu8 uapsd_ac_setting;\n\tu8 uapsd_max_sp_len_setting;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhu %hhx\", &uapsd_max_sp_len_setting, &uapsd_ac_setting);\n\n\t\tif (pregpriv) {\n\t\t\tif (num >= 1) {\n\t\t\t\tpregpriv->uapsd_max_sp_len = uapsd_max_sp_len_setting;\n\t\t\t\tRTW_INFO(\"uapsd_max_sp_len = %d\\n\", pregpriv->uapsd_max_sp_len);\n\t\t\t}\n\n\t\t\tif (num >= 2) {\n\t\t\t\tpregpriv->uapsd_ac_enable = uapsd_ac_setting;\n\t\t\t\tRTW_INFO(\"uapsd_ac_enable = 0x%02x\\n\", pregpriv->uapsd_ac_enable);\n\t\t\t}\n\t\t}\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_WMMPS_STA */\n#endif /* CONFIG_POWER_SAVING */\n\n#ifdef CONFIG_TDLS\nint proc_get_tdls_enable(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv *pregpriv = &padapter->registrypriv;\n\n\tif (pregpriv)\n\t\tRTW_PRINT_SEL(m, \"TDLS is %s !\\n\", (rtw_is_tdls_enabled(padapter) == _TRUE) ? \"enabled\" : \"disabled\");\n\n\treturn 0;\n}\n\nssize_t proc_set_tdls_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\tchar tmp[32];\n\tu32 en_tdls = 0;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d \", &en_tdls);\n\n\t\tif (num == 1 && pregpriv) {\n\t\t\tif (en_tdls > 0)\n\t\t\t\trtw_enable_tdls_func(padapter);\n\t\t\telse\n\t\t\t\trtw_disable_tdls_func(padapter, _TRUE);\n\t\t}\n\t}\n\n\treturn count;\n}\n\nstatic int proc_tdls_display_tdls_function_info(struct seq_file *m)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\tu8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE;\n\tu8 SpaceBtwnItemAndValueTmp = 0;\n\tBOOLEAN FirstMatchFound = _FALSE;\n\tint j = 0;\n\n\tRTW_PRINT_SEL(m, \"============[TDLS Function Info]============\\n\");\n\tRTW_PRINT_SEL(m, \"%-*s = %s\\n\", SpaceBtwnItemAndValue, \"TDLS Enable\", (rtw_is_tdls_enabled(padapter) == _TRUE) ? \"_TRUE\" : \"_FALSE\");\n\tRTW_PRINT_SEL(m, \"%-*s = %s\\n\", SpaceBtwnItemAndValue, \"TDLS Driver Setup\", (ptdlsinfo->driver_setup == _TRUE) ? \"_TRUE\" : \"_FALSE\");\n\tRTW_PRINT_SEL(m, \"%-*s = %s\\n\", SpaceBtwnItemAndValue, \"TDLS Prohibited\", (ptdlsinfo->ap_prohibited == _TRUE) ? \"_TRUE\" : \"_FALSE\");\n\tRTW_PRINT_SEL(m, \"%-*s = %s\\n\", SpaceBtwnItemAndValue, \"TDLS Channel Switch Prohibited\", (ptdlsinfo->ch_switch_prohibited == _TRUE) ? \"_TRUE\" : \"_FALSE\");\n\tRTW_PRINT_SEL(m, \"%-*s = %s\\n\", SpaceBtwnItemAndValue, \"TDLS Link Established\", (ptdlsinfo->link_established == _TRUE) ? \"_TRUE\" : \"_FALSE\");\n\tRTW_PRINT_SEL(m, \"%-*s = %d/%d\\n\", SpaceBtwnItemAndValue, \"TDLS STA Num (Linked/Allowed)\", ptdlsinfo->sta_cnt, MAX_ALLOWED_TDLS_STA_NUM);\n\tRTW_PRINT_SEL(m, \"%-*s = %s\\n\", SpaceBtwnItemAndValue, \"TDLS Allowed STA Num Reached\", (ptdlsinfo->sta_maximum == _TRUE) ? \"_TRUE\" : \"_FALSE\");\n\n#ifdef CONFIG_TDLS_CH_SW\n\tRTW_PRINT_SEL(m, \"%-*s =\", SpaceBtwnItemAndValue, \"TDLS CH SW State\");\n\tif (ptdlsinfo->chsw_info.ch_sw_state == TDLS_STATE_NONE)\n\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValueTmp, \" \", \"TDLS_STATE_NONE\");\n\telse {\n\t\tfor (j = 0; j < 32; j++) {\n\t\t\tif (ptdlsinfo->chsw_info.ch_sw_state & BIT(j)) {\n\t\t\t\tif (FirstMatchFound ==  _FALSE) {\n\t\t\t\t\tSpaceBtwnItemAndValueTmp = 1;\n\t\t\t\t\tFirstMatchFound = _TRUE;\n\t\t\t\t} else\n\t\t\t\t\tSpaceBtwnItemAndValueTmp = SpaceBtwnItemAndValue + 3;\n\t\t\t\tswitch (BIT(j)) {\n\t\t\t\tcase TDLS_INITIATOR_STATE:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValueTmp, \" \", \"TDLS_INITIATOR_STATE\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase TDLS_RESPONDER_STATE:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValueTmp, \" \", \"TDLS_RESPONDER_STATE\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase TDLS_LINKED_STATE:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValueTmp, \" \", \"TDLS_LINKED_STATE\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase TDLS_WAIT_PTR_STATE:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValueTmp, \" \", \"TDLS_WAIT_PTR_STATE\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase TDLS_ALIVE_STATE:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValueTmp, \" \", \"TDLS_ALIVE_STATE\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase TDLS_CH_SWITCH_ON_STATE:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValueTmp, \" \", \"TDLS_CH_SWITCH_ON_STATE\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase TDLS_PEER_AT_OFF_STATE:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValueTmp, \" \", \"TDLS_PEER_AT_OFF_STATE\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase TDLS_CH_SW_INITIATOR_STATE:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValueTmp, \" \", \"TDLS_CH_SW_INITIATOR_STATE\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase TDLS_WAIT_CH_RSP_STATE:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValue, \" \", \"TDLS_WAIT_CH_RSP_STATE\");\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*sBIT(%d)\\n\", SpaceBtwnItemAndValueTmp, \" \", j);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tRTW_PRINT_SEL(m, \"%-*s = %s\\n\", SpaceBtwnItemAndValue, \"TDLS CH SW On\", (ATOMIC_READ(&ptdlsinfo->chsw_info.chsw_on) == _TRUE) ? \"_TRUE\" : \"_FALSE\");\n\tRTW_PRINT_SEL(m, \"%-*s = %d\\n\", SpaceBtwnItemAndValue, \"TDLS CH SW Off-Channel Num\", ptdlsinfo->chsw_info.off_ch_num);\n\tRTW_PRINT_SEL(m, \"%-*s = %d\\n\", SpaceBtwnItemAndValue, \"TDLS CH SW Channel Offset\", ptdlsinfo->chsw_info.ch_offset);\n\tRTW_PRINT_SEL(m, \"%-*s = %d\\n\", SpaceBtwnItemAndValue, \"TDLS CH SW Current Time\", ptdlsinfo->chsw_info.cur_time);\n\tRTW_PRINT_SEL(m, \"%-*s = %s\\n\", SpaceBtwnItemAndValue, \"TDLS CH SW Delay Switch Back\", (ptdlsinfo->chsw_info.delay_switch_back == _TRUE) ? \"_TRUE\" : \"_FALSE\");\n\tRTW_PRINT_SEL(m, \"%-*s = %d\\n\", SpaceBtwnItemAndValue, \"TDLS CH SW Dump Back\", ptdlsinfo->chsw_info.dump_stack);\n#endif\n\n\tRTW_PRINT_SEL(m, \"%-*s = %s\\n\", SpaceBtwnItemAndValue, \"TDLS Device Discovered\", (ptdlsinfo->dev_discovered == _TRUE) ? \"_TRUE\" : \"_FALSE\");\n\n\treturn 0;\n}\n\nstatic int proc_tdls_display_network_info(struct seq_file *m)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct wlan_network *cur_network = &(pmlmepriv->cur_network);\n\tint i = 0;\n\tu8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE;\n\n\t/* Display the linked AP/GO info */\n\tRTW_PRINT_SEL(m, \"============[Associated AP/GO Info]============\\n\");\n\n\tif ((pmlmepriv->fw_state & WIFI_STATION_STATE) && (pmlmepriv->fw_state & _FW_LINKED)) {\n\t\tRTW_PRINT_SEL(m, \"%-*s = %s\\n\", SpaceBtwnItemAndValue, \"BSSID\", cur_network->network.Ssid.Ssid);\n\t\tRTW_PRINT_SEL(m, \"%-*s = \"MAC_FMT\"\\n\", SpaceBtwnItemAndValue, \"Mac Address\", MAC_ARG(cur_network->network.MacAddress));\n\n\t\tRTW_PRINT_SEL(m, \"%-*s = \", SpaceBtwnItemAndValue, \"Wireless Mode\");\n\t\tfor (i = 0; i < 8; i++) {\n\t\t\tif (pmlmeext->cur_wireless_mode & BIT(i)) {\n\t\t\t\tswitch (BIT(i)) {\n\t\t\t\tcase WIRELESS_11B:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%4s\", \"11B \");\n\t\t\t\t\tbreak;\n\t\t\t\tcase WIRELESS_11G:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%4s\", \"11G \");\n\t\t\t\t\tbreak;\n\t\t\t\tcase WIRELESS_11A:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%4s\", \"11A \");\n\t\t\t\t\tbreak;\n\t\t\t\tcase WIRELESS_11_24N:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%7s\", \"11_24N \");\n\t\t\t\t\tbreak;\n\t\t\t\tcase WIRELESS_11_5N:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%6s\", \"11_5N \");\n\t\t\t\t\tbreak;\n\t\t\t\tcase WIRELESS_AUTO:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%5s\", \"AUTO \");\n\t\t\t\t\tbreak;\n\t\t\t\tcase WIRELESS_11AC:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%5s\", \"11AC \");\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tRTW_PRINT_SEL(m, \"\\n\");\n\n\t\tRTW_PRINT_SEL(m, \"%-*s = \", SpaceBtwnItemAndValue, \"Privacy\");\n\t\tswitch (padapter->securitypriv.dot11PrivacyAlgrthm) {\n\t\tcase _NO_PRIVACY_:\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"NO PRIVACY\");\n\t\t\tbreak;\n\t\tcase _WEP40_:\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"WEP 40\");\n\t\t\tbreak;\n\t\tcase _TKIP_:\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"TKIP\");\n\t\t\tbreak;\n\t\tcase _TKIP_WTMIC_:\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"TKIP WTMIC\");\n\t\t\tbreak;\n\t\tcase _AES_:\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"AES\");\n\t\t\tbreak;\n\t\tcase _WEP104_:\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"WEP 104\");\n\t\t\tbreak;\n\t\tcase _WEP_WPA_MIXED_:\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"WEP/WPA Mixed\");\n\t\t\tbreak;\n\t\tcase _SMS4_:\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"SMS4\");\n\t\t\tbreak;\n#ifdef CONFIG_IEEE80211W\n\t\tcase _BIP_:\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"BIP\");\n\t\t\tbreak;\n#endif /* CONFIG_IEEE80211W */\n\t\t}\n\n\t\tRTW_PRINT_SEL(m, \"%-*s = %d\\n\", SpaceBtwnItemAndValue, \"Channel\", pmlmeext->cur_channel);\n\t\tRTW_PRINT_SEL(m, \"%-*s = \", SpaceBtwnItemAndValue, \"Channel Offset\");\n\t\tswitch (pmlmeext->cur_ch_offset) {\n\t\tcase HAL_PRIME_CHNL_OFFSET_DONT_CARE:\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"N/A\");\n\t\t\tbreak;\n\t\tcase HAL_PRIME_CHNL_OFFSET_LOWER:\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"Lower\");\n\t\t\tbreak;\n\t\tcase HAL_PRIME_CHNL_OFFSET_UPPER:\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"Upper\");\n\t\t\tbreak;\n\t\t}\n\n\t\tRTW_PRINT_SEL(m, \"%-*s = \", SpaceBtwnItemAndValue, \"Bandwidth Mode\");\n\t\tswitch (pmlmeext->cur_bwmode) {\n\t\tcase CHANNEL_WIDTH_20:\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"20MHz\");\n\t\t\tbreak;\n\t\tcase CHANNEL_WIDTH_40:\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"40MHz\");\n\t\t\tbreak;\n\t\tcase CHANNEL_WIDTH_80:\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"80MHz\");\n\t\t\tbreak;\n\t\tcase CHANNEL_WIDTH_160:\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"160MHz\");\n\t\t\tbreak;\n\t\tcase CHANNEL_WIDTH_80_80:\n\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"80MHz + 80MHz\");\n\t\t\tbreak;\n\t\t}\n\t} else\n\t\tRTW_PRINT_SEL(m, \"No association with AP/GO exists!\\n\");\n\n\treturn 0;\n}\n\nstatic int proc_tdls_display_tdls_sta_info(struct seq_file *m)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\tstruct sta_info *psta;\n\tint i = 0, j = 0;\n\t_irqL irqL;\n\t_list\t*plist, *phead;\n\tu8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE;\n\tu8 SpaceBtwnItemAndValueTmp = 0;\n\tu8 NumOfTdlsStaToShow = 0;\n\tBOOLEAN FirstMatchFound = _FALSE;\n\n\t/* Search for TDLS sta info to display */\n\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\tfor (i = 0; i < NUM_STA; i++) {\n\t\tphead = &(pstapriv->sta_hash[i]);\n\t\tplist = get_next(phead);\n\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\t\t\tplist = get_next(plist);\n\t\t\tif (psta->tdls_sta_state != TDLS_STATE_NONE) {\n\t\t\t\t/* We got one TDLS sta info to show */\n\t\t\t\tRTW_PRINT_SEL(m, \"============[TDLS Peer STA Info: STA %d]============\\n\", ++NumOfTdlsStaToShow);\n\t\t\t\tRTW_PRINT_SEL(m, \"%-*s = \"MAC_FMT\"\\n\", SpaceBtwnItemAndValue, \"Mac Address\", MAC_ARG(psta->cmn.mac_addr));\n\t\t\t\tRTW_PRINT_SEL(m, \"%-*s =\", SpaceBtwnItemAndValue, \"TDLS STA State\");\n\t\t\t\tSpaceBtwnItemAndValueTmp = 0;\n\t\t\t\tFirstMatchFound = _FALSE;\n\t\t\t\tfor (j = 0; j < 32; j++) {\n\t\t\t\t\tif (psta->tdls_sta_state & BIT(j)) {\n\t\t\t\t\t\tif (FirstMatchFound ==  _FALSE) {\n\t\t\t\t\t\t\tSpaceBtwnItemAndValueTmp = 1;\n\t\t\t\t\t\t\tFirstMatchFound = _TRUE;\n\t\t\t\t\t\t} else\n\t\t\t\t\t\t\tSpaceBtwnItemAndValueTmp = SpaceBtwnItemAndValue + 3;\n\t\t\t\t\t\tswitch (BIT(j)) {\n\t\t\t\t\t\tcase TDLS_INITIATOR_STATE:\n\t\t\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValueTmp, \" \", \"TDLS_INITIATOR_STATE\");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase TDLS_RESPONDER_STATE:\n\t\t\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValueTmp, \" \", \"TDLS_RESPONDER_STATE\");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase TDLS_LINKED_STATE:\n\t\t\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValueTmp, \" \", \"TDLS_LINKED_STATE\");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase TDLS_WAIT_PTR_STATE:\n\t\t\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValueTmp, \" \", \"TDLS_WAIT_PTR_STATE\");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase TDLS_ALIVE_STATE:\n\t\t\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValueTmp, \" \", \"TDLS_ALIVE_STATE\");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase TDLS_CH_SWITCH_ON_STATE:\n\t\t\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValueTmp, \" \", \"TDLS_CH_SWITCH_ON_STATE\");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase TDLS_PEER_AT_OFF_STATE:\n\t\t\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValueTmp, \" \", \"TDLS_PEER_AT_OFF_STATE\");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase TDLS_CH_SW_INITIATOR_STATE:\n\t\t\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValueTmp, \" \", \"TDLS_CH_SW_INITIATOR_STATE\");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase TDLS_WAIT_CH_RSP_STATE:\n\t\t\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*s%s\\n\", SpaceBtwnItemAndValue, \" \", \"TDLS_WAIT_CH_RSP_STATE\");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tdefault:\n\t\t\t\t\t\t\tRTW_PRINT_SEL(m, \"%-*sBIT(%d)\\n\", SpaceBtwnItemAndValueTmp, \" \", j);\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tRTW_PRINT_SEL(m, \"%-*s = \", SpaceBtwnItemAndValue, \"Wireless Mode\");\n\t\t\t\tfor (j = 0; j < 8; j++) {\n\t\t\t\t\tif (psta->wireless_mode & BIT(j)) {\n\t\t\t\t\t\tswitch (BIT(j)) {\n\t\t\t\t\t\tcase WIRELESS_11B:\n\t\t\t\t\t\t\tRTW_PRINT_SEL(m, \"%4s\", \"11B \");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase WIRELESS_11G:\n\t\t\t\t\t\t\tRTW_PRINT_SEL(m, \"%4s\", \"11G \");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase WIRELESS_11A:\n\t\t\t\t\t\t\tRTW_PRINT_SEL(m, \"%4s\", \"11A \");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase WIRELESS_11_24N:\n\t\t\t\t\t\t\tRTW_PRINT_SEL(m, \"%7s\", \"11_24N \");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase WIRELESS_11_5N:\n\t\t\t\t\t\t\tRTW_PRINT_SEL(m, \"%6s\", \"11_5N \");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase WIRELESS_AUTO:\n\t\t\t\t\t\t\tRTW_PRINT_SEL(m, \"%5s\", \"AUTO \");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase WIRELESS_11AC:\n\t\t\t\t\t\t\tRTW_PRINT_SEL(m, \"%5s\", \"11AC \");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tRTW_PRINT_SEL(m, \"\\n\");\n\n\t\t\t\tRTW_PRINT_SEL(m, \"%-*s = \", SpaceBtwnItemAndValue, \"Bandwidth Mode\");\n\t\t\t\tswitch (psta->cmn.bw_mode) {\n\t\t\t\tcase CHANNEL_WIDTH_20:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"20MHz\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase CHANNEL_WIDTH_40:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"40MHz\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase CHANNEL_WIDTH_80:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"80MHz\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase CHANNEL_WIDTH_160:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"160MHz\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase CHANNEL_WIDTH_80_80:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"80MHz + 80MHz\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase CHANNEL_WIDTH_5:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"5MHz\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase CHANNEL_WIDTH_10:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"10MHz\");\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"(%d)%s\\n\", psta->cmn.bw_mode, \"invalid\");\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\tRTW_PRINT_SEL(m, \"%-*s = \", SpaceBtwnItemAndValue, \"Privacy\");\n\t\t\t\tswitch (psta->dot118021XPrivacy) {\n\t\t\t\tcase _NO_PRIVACY_:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"NO PRIVACY\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase _WEP40_:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"WEP 40\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase _TKIP_:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"TKIP\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase _TKIP_WTMIC_:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"TKIP WTMIC\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase _AES_:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"AES\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase _WEP104_:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"WEP 104\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase _WEP_WPA_MIXED_:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"WEP/WPA Mixed\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase _SMS4_:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"SMS4\");\n\t\t\t\t\tbreak;\n#ifdef CONFIG_IEEE80211W\n\t\t\t\tcase _BIP_:\n\t\t\t\t\tRTW_PRINT_SEL(m, \"%s\\n\", \"BIP\");\n\t\t\t\t\tbreak;\n#endif /* CONFIG_IEEE80211W */\n\t\t\t\t}\n\n\t\t\t\tRTW_PRINT_SEL(m, \"%-*s = %d sec/%d sec\\n\", SpaceBtwnItemAndValue, \"TPK Lifetime (Current/Expire)\", psta->TPK_count, psta->TDLS_PeerKey_Lifetime);\n\t\t\t\tRTW_PRINT_SEL(m, \"%-*s = %llu\\n\", SpaceBtwnItemAndValue, \"Tx Packets Over Direct Link\", psta->sta_stats.tx_pkts);\n\t\t\t\tRTW_PRINT_SEL(m, \"%-*s = %llu\\n\", SpaceBtwnItemAndValue, \"Rx Packets Over Direct Link\", psta->sta_stats.rx_data_pkts);\n\t\t\t}\n\t\t}\n\t}\n\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\tif (NumOfTdlsStaToShow == 0) {\n\t\tRTW_PRINT_SEL(m, \"============[TDLS Peer STA Info]============\\n\");\n\t\tRTW_PRINT_SEL(m, \"No TDLS direct link exists!\\n\");\n\t}\n\n\treturn 0;\n}\n\nint proc_get_tdls_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct wlan_network *cur_network = &(pmlmepriv->cur_network);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\tstruct sta_info *psta;\n\tint i = 0, j = 0;\n\t_irqL irqL;\n\t_list\t*plist, *phead;\n\tu8 SpaceBtwnItemAndValue = 41;\n\tu8 SpaceBtwnItemAndValueTmp = 0;\n\tu8 NumOfTdlsStaToShow = 0;\n\tBOOLEAN FirstMatchFound = _FALSE;\n\n\tif (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) {\n\t\tRTW_PRINT_SEL(m, \"No tdls info can be shown since hal doesn't support tdls\\n\");\n\t\treturn 0;\n\t}\n\n\tproc_tdls_display_tdls_function_info(m);\n\tproc_tdls_display_network_info(m);\n\tproc_tdls_display_tdls_sta_info(m);\n\n\treturn 0;\n}\n#endif\n\nint proc_get_monitor(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\tif (WIFI_MONITOR_STATE == get_fwstate(pmlmepriv)) {\n\t\tRTW_PRINT_SEL(m, \"Monitor mode : Enable\\n\");\n\n\t\tRTW_PRINT_SEL(m, \"ch=%d, ch_offset=%d, bw=%d\\n\",\n\t\t\trtw_get_oper_ch(padapter), rtw_get_oper_choffset(padapter), rtw_get_oper_bw(padapter));\n\t} else\n\t\tRTW_PRINT_SEL(m, \"Monitor mode : Disable\\n\");\n\n\treturn 0;\n}\n\nssize_t proc_set_monitor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tchar tmp[32];\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8 target_chan, target_offset, target_bw;\n\n\tif (count < 3) {\n\t\tRTW_INFO(\"argument size is less than 3\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%hhu %hhu %hhu\", &target_chan, &target_offset, &target_bw);\n\n\t\tif (num != 3) {\n\t\t\tRTW_INFO(\"invalid write_reg parameter!\\n\");\n\t\t\treturn count;\n\t\t}\n\n\t\tpadapter->mlmeextpriv.cur_channel  = target_chan;\n\t\tset_channel_bwmode(padapter, target_chan, target_offset, target_bw);\n\t}\n\n\treturn count;\n}\n#ifdef DBG_XMIT_BLOCK\nint proc_get_xmit_block(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_xmit_block(m, padapter);\n\n\treturn 0;\n}\n\nssize_t proc_set_xmit_block(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu8 xb_mode, xb_reason;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhx %hhx\", &xb_mode, &xb_reason);\n\n\t\tif (num != 2) {\n\t\t\tRTW_INFO(\"invalid parameter!\\n\");\n\t\t\treturn count;\n\t\t}\n\n\t\tif (xb_mode == 0)/*set*/\n\t\t\trtw_set_xmit_block(padapter, xb_reason);\n\t\telse if (xb_mode == 1)/*clear*/\n\t\t\trtw_clr_xmit_block(padapter, xb_reason);\n\t\telse\n\t\t\tRTW_INFO(\"invalid parameter!\\n\");\n\t}\n\n\treturn count;\n}\n#endif\n\n#include <hal_data.h>\nint proc_get_efuse_map(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);\n\tstruct pwrctrl_priv *pwrctrlpriv  = adapter_to_pwrctl(padapter);\n\tPEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;\n\tint i, j;\n\tu8 ips_mode = IPS_NUM;\n\tu16 mapLen;\n\n\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);\n\tif (mapLen > EFUSE_MAX_MAP_LEN)\n\t\tmapLen = EFUSE_MAX_MAP_LEN;\n\n\tips_mode = pwrctrlpriv->ips_mode;\n\trtw_pm_set_ips(padapter, IPS_NONE);\n\n\tif (pHalData->efuse_file_status == EFUSE_FILE_LOADED) {\n\t\tRTW_PRINT_SEL(m, \"File eFuse Map loaded! file path:%s\\nDriver eFuse Map From File\\n\", EFUSE_MAP_PATH);\n\t\tif (pHalData->bautoload_fail_flag)\n\t\t\tRTW_PRINT_SEL(m, \"File Autoload fail!!!\\n\");\n\t} else if (pHalData->efuse_file_status ==  EFUSE_FILE_FAILED) {\n\t\tRTW_PRINT_SEL(m, \"Open File eFuse Map Fail ! file path:%s\\nDriver eFuse Map From Default\\n\", EFUSE_MAP_PATH);\n\t\tif (pHalData->bautoload_fail_flag)\n\t\t\tRTW_PRINT_SEL(m, \"HW Autoload fail!!!\\n\");\n\t} else {\n\t\tRTW_PRINT_SEL(m, \"Driver eFuse Map From HW\\n\");\n\t\tif (pHalData->bautoload_fail_flag)\n\t\t\tRTW_PRINT_SEL(m, \"HW Autoload fail!!!\\n\");\n\t}\n\tfor (i = 0; i < mapLen; i += 16) {\n\t\tRTW_PRINT_SEL(m, \"0x%02x\\t\", i);\n\t\tfor (j = 0; j < 8; j++)\n\t\t\tRTW_PRINT_SEL(m, \"%02X \", pHalData->efuse_eeprom_data[i + j]);\n\t\tRTW_PRINT_SEL(m, \"\\t\");\n\t\tfor (; j < 16; j++)\n\t\t\tRTW_PRINT_SEL(m, \"%02X \", pHalData->efuse_eeprom_data[i + j]);\n\t\tRTW_PRINT_SEL(m, \"\\n\");\n\t}\n\n\tif (rtw_efuse_map_read(padapter, 0, mapLen, pEfuseHal->fakeEfuseInitMap) == _FAIL) {\n\t\tRTW_PRINT_SEL(m, \"WARN - Read Realmap Failed\\n\");\n\t\treturn 0;\n\t}\n\n\tRTW_PRINT_SEL(m, \"\\n\");\n\tRTW_PRINT_SEL(m, \"HW eFuse Map\\n\");\n\tfor (i = 0; i < mapLen; i += 16) {\n\t\tRTW_PRINT_SEL(m, \"0x%02x\\t\", i);\n\t\tfor (j = 0; j < 8; j++)\n\t\t\tRTW_PRINT_SEL(m, \"%02X \", pEfuseHal->fakeEfuseInitMap[i + j]);\n\t\tRTW_PRINT_SEL(m, \"\\t\");\n\t\tfor (; j < 16; j++)\n\t\t\tRTW_PRINT_SEL(m, \"%02X \", pEfuseHal->fakeEfuseInitMap[i + j]);\n\t\tRTW_PRINT_SEL(m, \"\\n\");\n\t}\n\n\trtw_pm_set_ips(padapter, ips_mode);\n\n\treturn 0;\n}\n\nssize_t proc_set_efuse_map(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n#if 0\n\tchar tmp[256] = {0};\n\tu32 addr, cnts;\n\tu8 efuse_data;\n\n\tint jj, kk;\n\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct pwrctrl_priv *pwrctrlpriv  = adapter_to_pwrctl(padapter);\n\tu8 ips_mode = IPS_NUM;\n\n\tif (count < 3) {\n\t\tRTW_INFO(\"argument size is less than 3\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%x %d %x\", &addr, &cnts, &efuse_data);\n\n\t\tif (num != 3) {\n\t\t\tRTW_INFO(\"invalid write_reg parameter!\\n\");\n\t\t\treturn count;\n\t\t}\n\t}\n\tips_mode = pwrctrlpriv->ips_mode;\n\trtw_pm_set_ips(padapter, IPS_NONE);\n\tif (rtw_efuse_map_write(padapter, addr, cnts, &efuse_data) == _FAIL)\n\t\tRTW_INFO(\"WARN - rtw_efuse_map_write error!!\\n\");\n\trtw_pm_set_ips(padapter, ips_mode);\n#endif\n\treturn count;\n}\n\n#ifdef CONFIG_IEEE80211W\nssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct\tsta_priv *pstapriv = &padapter->stapriv;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\tstruct sta_info *psta;\n\t_list\t*plist, *phead;\n\t_irqL\t irqL;\n\tchar tmp[16];\n\tu8\tmac_addr[NUM_STA][ETH_ALEN];\n\tu32 key_type;\n\tu8 index;\n\n\tif (count > 2) {\n\t\tRTW_INFO(\"argument size is more than 2\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {\n\n\t\tint num = sscanf(tmp, \"%x\", &key_type);\n\n\t\tif (num !=  1) {\n\t\t\tRTW_INFO(\"invalid read_reg parameter!\\n\");\n\t\t\treturn count;\n\t\t}\n\t\tRTW_INFO(\"0: set sa query request , key_type=%d\\n\", key_type);\n\t}\n\n\tif ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)\n\t    && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) {\n\t\tRTW_INFO(\"STA:\"MAC_FMT\"\\n\", MAC_ARG(get_my_bssid(&(pmlmeinfo->network))));\n\t\t/* TX unicast sa_query to AP */\n\t\tissue_action_SA_Query(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, 0, (u8)key_type);\n\t} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) {\n\t\t/* TX unicast sa_query to every client STA */\n\t\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\t\tfor (index = 0; index < NUM_STA; index++) {\n\t\t\tpsta = NULL;\n\n\t\t\tphead = &(pstapriv->sta_hash[index]);\n\t\t\tplist = get_next(phead);\n\n\t\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\t\t\t\tplist = get_next(plist);\n\t\t\t\t_rtw_memcpy(&mac_addr[psta->cmn.mac_id][0], psta->cmn.mac_addr, ETH_ALEN);\n\t\t\t}\n\t\t}\n\t\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\t\tfor (index = 0; index < macid_ctl->num && index < NUM_STA; index++) {\n\t\t\tif (rtw_macid_is_used(macid_ctl, index) && !rtw_macid_is_bmc(macid_ctl, index)) {\n\t\t\t\tif (!_rtw_memcmp(get_my_bssid(&(pmlmeinfo->network)), &mac_addr[index][0], ETH_ALEN)\n\t\t\t\t    && !IS_MCAST(&mac_addr[index][0])) {\n\t\t\t\t\tissue_action_SA_Query(padapter, &mac_addr[index][0], 0, 0, (u8)key_type);\n\t\t\t\t\tRTW_INFO(\"STA[%u]:\"MAC_FMT\"\\n\", index , MAC_ARG(&mac_addr[index][0]));\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\treturn count;\n}\n\nint proc_get_tx_sa_query(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_PRINT_SEL(m, \"%s\\n\", __func__);\n\treturn 0;\n}\n\nssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct\tsta_priv *pstapriv = &padapter->stapriv;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\tstruct sta_info *psta;\n\t_list\t*plist, *phead;\n\t_irqL\t irqL;\n\tchar tmp[16];\n\tu8\tmac_addr[NUM_STA][ETH_ALEN];\n\tu8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tu32 key_type;\n\tu8 index;\n\n\n\tif (count > 2) {\n\t\tRTW_INFO(\"argument size is more than 2\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {\n\n\t\tint num = sscanf(tmp, \"%x\", &key_type);\n\n\t\tif (num !=  1) {\n\t\t\tRTW_INFO(\"invalid read_reg parameter!\\n\");\n\t\t\treturn count;\n\t\t}\n\t\tRTW_INFO(\"key_type=%d\\n\", key_type);\n\t}\n\tif (key_type < 0 || key_type > 4)\n\t\treturn count;\n\n\tif ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)\n\t    && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {\n\t\tif (key_type == 3) /* key_type 3 only for AP mode */\n\t\t\treturn count;\n\t\t/* TX unicast deauth to AP */\n\t\tissue_deauth_11w(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, (u8)key_type);\n\t} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {\n\t\tu8 updated = _FALSE;\n\n\t\tif (key_type == 3)\n\t\t\tissue_deauth_11w(padapter, bc_addr, 0, IEEE80211W_RIGHT_KEY);\n\n\t\t/* TX unicast deauth to every client STA */\n\t\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\t\tfor (index = 0; index < NUM_STA; index++) {\n\t\t\tpsta = NULL;\n\n\t\t\tphead = &(pstapriv->sta_hash[index]);\n\t\t\tplist = get_next(phead);\n\n\t\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\t\t\t\tplist = get_next(plist);\n\t\t\t\t_rtw_memcpy(&mac_addr[psta->cmn.mac_id][0], psta->cmn.mac_addr, ETH_ALEN);\n\t\t\t}\n\t\t}\n\t\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\t\tfor (index = 0; index < macid_ctl->num && index < NUM_STA; index++) {\n\t\t\tif (rtw_macid_is_used(macid_ctl, index) && !rtw_macid_is_bmc(macid_ctl, index)) {\n\t\t\t\tif (!_rtw_memcmp(get_my_bssid(&(pmlmeinfo->network)), &mac_addr[index][0], ETH_ALEN)) {\n\t\t\t\t\tif (key_type != 3)\n\t\t\t\t\t\tissue_deauth_11w(padapter, &mac_addr[index][0], 0, (u8)key_type);\n\n\t\t\t\t\tpsta = rtw_get_stainfo(pstapriv, &mac_addr[index][0]);\n\t\t\t\t\tif (psta && key_type != IEEE80211W_WRONG_KEY && key_type != IEEE80211W_NO_KEY) {\n\t\t\t\t\t\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\t\t\t\t\t\tif (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {\n\t\t\t\t\t\t\trtw_list_delete(&psta->asoc_list);\n\t\t\t\t\t\t\tpstapriv->asoc_list_cnt--;\n\t\t\t\t\t\t\tupdated |= ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE);\n\n\t\t\t\t\t\t}\n\t\t\t\t\t\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\t\t\t\t\t}\n\n\t\t\t\t\tRTW_INFO(\"STA[%u]:\"MAC_FMT\"\\n\", index , MAC_ARG(&mac_addr[index][0]));\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tassociated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);\n\t}\n\n\treturn count;\n}\n\nint proc_get_tx_deauth(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_PRINT_SEL(m, \"%s\\n\", __func__);\n\treturn 0;\n}\n\nssize_t proc_set_tx_auth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct\tsta_priv *pstapriv = &padapter->stapriv;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\tstruct sta_info *psta;\n\t_list\t*plist, *phead;\n\t_irqL\t irqL;\n\tchar tmp[16];\n\tu8\tmac_addr[NUM_STA][ETH_ALEN];\n\tu8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tu32 tx_auth;\n\tu8 index;\n\n\n\tif (count > 2) {\n\t\tRTW_INFO(\"argument size is more than 2\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {\n\n\t\tint num = sscanf(tmp, \"%x\", &tx_auth);\n\n\t\tif (num !=  1) {\n\t\t\tRTW_INFO(\"invalid read_reg parameter!\\n\");\n\t\t\treturn count;\n\t\t}\n\t\tRTW_INFO(\"1: setnd auth, 2: send assoc request. tx_auth=%d\\n\", tx_auth);\n\t}\n\n\tif ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)\n\t    && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {\n\t\tif (tx_auth == 1) {\n\t\t\t/* TX unicast auth to AP */\n\t\t\tissue_auth(padapter, NULL, 0);\n\t\t} else if (tx_auth == 2) {\n\t\t\t/* TX unicast auth to AP */\n\t\t\tissue_assocreq(padapter);\n\t\t}\n\t}\n\n\treturn count;\n}\n\nint proc_get_tx_auth(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_PRINT_SEL(m, \"%s\\n\", __func__);\n\treturn 0;\n}\n#endif /* CONFIG_IEEE80211W */\n\n#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA\nstatic u32 phase_idx;\nint proc_get_pathb_phase(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_PRINT_SEL(m, \"PathB phase index =%d\\n\", phase_idx);\n\treturn 0;\n}\n\nssize_t proc_set_pathb_phase(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[255];\n\tint num;\n\tu32 tmp_idx;\n\n\tif (NULL == buffer) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input buffer is NULL!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is 0!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tnum = sscanf(tmp, \"%u\", &tmp_idx);\n\t\tif ((tmp_idx < 0) || (tmp_idx > 11)) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \"Invalid input value\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\treturn count;\n\t\t}\n\t\tphase_idx = tmp_idx;\n\t\trtw_hal_set_pathb_phase(padapter, phase_idx);\n\t}\n\treturn count;\n}\n#endif\n\n#ifdef CONFIG_MCC_MODE\nint proc_get_mcc_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_adapters_status(m, adapter_to_dvobj(adapter));\n\trtw_hal_dump_mcc_info(m, adapter_to_dvobj(adapter));\n\treturn 0;\n}\n\nint proc_get_mcc_policy_table(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\trtw_hal_dump_mcc_policy_table(m);\n\treturn 0;\n}\n\nssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[255];\n\tu32 en_mcc = 0;\n\n\tif (NULL == buffer) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input buffer is NULL!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is 0!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is too large\\n\", FUNC_ADPT_ARG(padapter));\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\t\t_adapter *iface = NULL;\n\t\tu8 i = 0;\n\t\tint num = sscanf(tmp, \"%u\", &en_mcc);\n\n\t\tif (num < 1) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": input parameters < 1\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tRTW_INFO(\"%s: en_mcc = %d\\n\", __func__, en_mcc);\n\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tif (!iface)\n\t\t\t\tcontinue;\n\t\t\tiface->registrypriv.en_mcc = en_mcc;\n\t\t}\n\t}\n\n\treturn count;\n}\n\nssize_t proc_set_mcc_duration(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[255];\n\tu32 enable_runtime_duration = 0, mcc_duration = 0, type = 0;\n\n\tif (NULL == buffer) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input buffer is NULL!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is 0!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is too large\\n\", FUNC_ADPT_ARG(padapter));\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%u %u %u\", &enable_runtime_duration, &type, &mcc_duration);\n\n\t\tif (num < 1) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": input parameters < 1\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tif (num > 3) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": input parameters > 2\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tif (num == 2) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": input parameters > 2\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tif (num >= 1) {\n\t\t\tSET_MCC_RUNTIME_DURATION(padapter, enable_runtime_duration);\n\t\t\tRTW_INFO(\"runtime duration:%s\\n\", enable_runtime_duration ? \"enable\":\"disable\");\n\t\t}\n\n\t\tif (num == 3) {\n\t\t\tRTW_INFO(\"type:%d, mcc duration:%d\\n\", type, mcc_duration);\n\t\t\trtw_set_mcc_duration_cmd(padapter, type, mcc_duration);\n\t\t}\n\t}\n\n\treturn count;\n}\n\n#ifdef CONFIG_MCC_PHYDM_OFFLOAD\nssize_t proc_set_mcc_phydm_offload_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[255];\n\tu32 mcc_phydm_enable = 0;\n\n\tif (NULL == buffer) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input buffer is NULL!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is 0!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is too large\\n\", FUNC_ADPT_ARG(padapter));\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\t\tu8 i = 0;\n\t\tint num = sscanf(tmp, \"%u\", &mcc_phydm_enable);\n\n\t\tif (num < 1) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": input parameters < 1\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tRTW_INFO(\"%s: mcc phydm enable = %d\\n\", __func__, mcc_phydm_enable);\n\t\trtw_set_mcc_phydm_offload_enable_cmd(padapter, mcc_phydm_enable, _TRUE);\n\t}\n\n\treturn count;\n}\n#endif\n\nssize_t proc_set_mcc_single_tx_criteria(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[255];\n\tu32 mcc_single_tx_criteria = 0;\n\n\tif (NULL == buffer) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input buffer is NULL!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is 0!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is too large\\n\", FUNC_ADPT_ARG(padapter));\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\t\t_adapter *iface = NULL;\n\t\tu8 i = 0;\n\t\tint num = sscanf(tmp, \"%u\", &mcc_single_tx_criteria);\n\n\t\tif (num < 1) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": input parameters < 1\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tRTW_INFO(\"%s: mcc_single_tx_criteria = %d\\n\", __func__, mcc_single_tx_criteria);\n\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tif (!iface)\n\t\t\t\tcontinue;\n\t\t\tiface->registrypriv.rtw_mcc_single_tx_cri = mcc_single_tx_criteria;\n\t\t}\n\n\n\t}\n\n\treturn count;\n}\n\n\nssize_t proc_set_mcc_ap_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[255];\n\tu32 mcc_ap_bw20_target_tp = 0;\n\n\tif (NULL == buffer) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input buffer is NULL!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is 0!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is too large\\n\", FUNC_ADPT_ARG(padapter));\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%u\", &mcc_ap_bw20_target_tp);\n\n\t\tif (num < 1) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": input parameters < 1\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tRTW_INFO(\"%s: mcc_ap_bw20_target_tp = %d\\n\", __func__, mcc_ap_bw20_target_tp);\n\n\t\tpadapter->registrypriv.rtw_mcc_ap_bw20_target_tx_tp = mcc_ap_bw20_target_tp;\n\n\n\t}\n\n\treturn count;\n}\n\nssize_t proc_set_mcc_ap_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[255];\n\tu32 mcc_ap_bw40_target_tp = 0;\n\n\tif (NULL == buffer) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input buffer is NULL!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is 0!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is too large\\n\", FUNC_ADPT_ARG(padapter));\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%u\", &mcc_ap_bw40_target_tp);\n\n\t\tif (num < 1) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": input parameters < 1\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tRTW_INFO(\"%s: mcc_ap_bw40_target_tp = %d\\n\", __func__, mcc_ap_bw40_target_tp);\n\n\t\tpadapter->registrypriv.rtw_mcc_ap_bw40_target_tx_tp = mcc_ap_bw40_target_tp;\n\n\n\t}\n\n\treturn count;\n}\n\nssize_t proc_set_mcc_ap_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[255];\n\tu32 mcc_ap_bw80_target_tp = 0;\n\n\tif (NULL == buffer) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input buffer is NULL!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is 0!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is too large\\n\", FUNC_ADPT_ARG(padapter));\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%u\", &mcc_ap_bw80_target_tp);\n\n\t\tif (num < 1) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": input parameters < 1\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tRTW_INFO(\"%s: mcc_ap_bw80_target_tp = %d\\n\", __func__, mcc_ap_bw80_target_tp);\n\n\t\tpadapter->registrypriv.rtw_mcc_ap_bw80_target_tx_tp = mcc_ap_bw80_target_tp;\n\n\n\t}\n\n\treturn count;\n}\n\nssize_t proc_set_mcc_sta_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[255];\n\tu32 mcc_sta_bw20_target_tp = 0;\n\n\tif (NULL == buffer) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input buffer is NULL!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is 0!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is too large\\n\", FUNC_ADPT_ARG(padapter));\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%u\", &mcc_sta_bw20_target_tp);\n\n\t\tif (num < 1) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": input parameters < 1\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tRTW_INFO(\"%s: mcc_sta_bw20_target_tp = %d\\n\", __func__, mcc_sta_bw20_target_tp);\n\n\t\tpadapter->registrypriv.rtw_mcc_sta_bw20_target_tx_tp = mcc_sta_bw20_target_tp;\n\n\n\t}\n\n\treturn count;\n}\n\nssize_t proc_set_mcc_sta_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[255];\n\tu32 mcc_sta_bw40_target_tp = 0;\n\n\tif (NULL == buffer) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input buffer is NULL!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is 0!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is too large\\n\", FUNC_ADPT_ARG(padapter));\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%u\", &mcc_sta_bw40_target_tp);\n\n\t\tif (num < 1) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": input parameters < 1\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tRTW_INFO(\"%s: mcc_sta_bw40_target_tp = %d\\n\", __func__, mcc_sta_bw40_target_tp);\n\n\t\tpadapter->registrypriv.rtw_mcc_sta_bw40_target_tx_tp = mcc_sta_bw40_target_tp;\n\n\n\t}\n\n\treturn count;\n}\n\nssize_t proc_set_mcc_sta_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[255];\n\tu32 mcc_sta_bw80_target_tp = 0;\n\n\tif (NULL == buffer) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input buffer is NULL!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is 0!\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is too large\\n\", FUNC_ADPT_ARG(padapter));\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%u\", &mcc_sta_bw80_target_tp);\n\n\t\tif (num < 1) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": input parameters < 1\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tRTW_INFO(\"%s: mcc_sta_bw80_target_tp = %d\\n\", __func__, mcc_sta_bw80_target_tp);\n\n\t\tpadapter->registrypriv.rtw_mcc_sta_bw80_target_tx_tp = mcc_sta_bw80_target_tp;\n\n\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_MCC_MODE */\n\nint proc_get_ack_timeout(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8 ack_timeout_val;\n#ifdef CONFIG_RTL8821C\n\tu8 ack_timeout_val_cck;\n#endif\n\n\tack_timeout_val = rtw_read8(padapter, REG_ACKTO);\n\n#ifdef CONFIG_RTL8821C\n\tack_timeout_val_cck = rtw_read8(padapter, REG_ACKTO_CCK_8821C);\n\tRTW_PRINT_SEL(m, \"Current CCK packet ACK Timeout = %d us (0x%x).\\n\", ack_timeout_val_cck, ack_timeout_val_cck);\n\tRTW_PRINT_SEL(m, \"Current non-CCK packet ACK Timeout = %d us (0x%x).\\n\", ack_timeout_val, ack_timeout_val);\n#else\n\tRTW_PRINT_SEL(m, \"Current ACK Timeout = %d us (0x%x).\\n\", ack_timeout_val, ack_timeout_val);\n#endif\n\n\treturn 0;\n}\n\nssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu32 ack_timeout_ms, ack_timeout_ms_cck;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%u %u\", &ack_timeout_ms, &ack_timeout_ms_cck);\n\n#ifdef CONFIG_RTL8821C\n\t\tif (num < 2) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": input parameters < 2\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\treturn -EINVAL;\n\t\t}\n#else\n\t\tif (num < 1) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": input parameters < 1\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\treturn -EINVAL;\n\t\t}\n#endif\n\t\t/* This register sets the Ack time out value after Tx unicast packet. It is in units of us. */\n\t\trtw_write8(padapter, REG_ACKTO, (u8)ack_timeout_ms);\n\n#ifdef CONFIG_RTL8821C\n\t\t/* This register sets the Ack time out value after Tx unicast CCK packet. It is in units of us. */\n\t\trtw_write8(padapter, REG_ACKTO_CCK_8821C, (u8)ack_timeout_ms_cck);\n\t\tRTW_INFO(\"Set CCK packet ACK Timeout to %d us.\\n\", ack_timeout_ms_cck);\n\t\tRTW_INFO(\"Set non-CCK packet ACK Timeout to %d us.\\n\", ack_timeout_ms);\n#else\n\t\tRTW_INFO(\"Set ACK Timeout to %d us.\\n\", ack_timeout_ms);\n#endif\n\t}\n\n\treturn count;\n}\n\nssize_t proc_set_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\t_adapter *pri_adapter = GET_PRIMARY_ADAPTER(adapter);\n\tHAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);\n\tchar tmp[32];\n\tu32 iqk_offload_enable = 0, ch_switch_offload_enable = 0;\n\n\tif (buffer == NULL) {\n\t\tRTW_INFO(\"input buffer is NULL!\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(\"input length is 0!\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\tRTW_INFO(\"input length is too large\\n\");\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%d %d\", &iqk_offload_enable, &ch_switch_offload_enable);\n\n\t\tif (num < 2) {\n\t\t\tRTW_INFO(\"input parameters < 1\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tif (hal->RegIQKFWOffload != iqk_offload_enable) {\n\t\t\thal->RegIQKFWOffload = iqk_offload_enable;\n\t\t\trtw_run_in_thread_cmd(pri_adapter, ((void *)(rtw_hal_update_iqk_fw_offload_cap)), pri_adapter);\n\t\t}\n\n\t\tif (hal->ch_switch_offload != ch_switch_offload_enable)\n\t\t\thal->ch_switch_offload = ch_switch_offload_enable;\n\t}\n\n\treturn count;\n}\n\nint proc_get_fw_offload(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);\n\n\n\tRTW_PRINT_SEL(m, \"IQK FW offload:%s\\n\", hal->RegIQKFWOffload?\"enable\":\"disable\");\n\tRTW_PRINT_SEL(m, \"Channel switch FW offload:%s\\n\", hal->ch_switch_offload?\"enable\":\"disable\");\n\treturn 0;\n}\n#ifdef CONFIG_FW_HANDLE_TXBCN\nextern void rtw_hal_set_fw_ap_bcn_offload_cmd(_adapter *adapter, bool fw_bcn_en, u8 tbtt_rpt_map);\nssize_t proc_set_fw_tbtt_rpt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu32 fw_tbtt_rpt, fw_bcn_offload;\n\n\n\tif (buffer == NULL) {\n\t\tRTW_INFO(\"input buffer is NULL!\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(\"input length is 0!\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\tRTW_INFO(\"input length is too large\\n\");\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%d %x\",&fw_bcn_offload, &fw_tbtt_rpt);\n\n\t\tif (num < 2) {\n\t\t\tRTW_INFO(\"input parameters < 2\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t\trtw_hal_set_fw_ap_bcn_offload_cmd(adapter, fw_bcn_offload, fw_tbtt_rpt);\n\t}\n\n\treturn count;\n}\n\nint proc_get_fw_tbtt_rpt(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\n\tRTW_PRINT_SEL(m, \"FW BCN offload:%s\\n\", dvobj->fw_bcn_offload ? \"enable\" : \"disable\");\n\tRTW_PRINT_SEL(m, \"FW TBTT RPT:%x\\n\", dvobj->vap_tbtt_rpt_map);\n\treturn 0;\n}\n\n#endif\n\n#ifdef CONFIG_CTRL_TXSS_BY_TP\nssize_t proc_set_txss_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\n\tchar tmp[32];\n\tu32 enable = 0;\n\tu32 txss_tx_tp = 0;\n\tint txss_chk_cnt = 0;\n\n\tif (buffer == NULL) {\n\t\tRTW_INFO(\"input buffer is NULL!\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(\"input length is 0!\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\tRTW_INFO(\"input length is too large\\n\");\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%u %u %d\",\n\t\t\t&enable, &txss_tx_tp, &txss_chk_cnt);\n\n\t\tif (num < 1) {\n\t\t\tRTW_INFO(\"input parameters < 1\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tpmlmeext->txss_ctrl_en = enable;\n\n\t\tif (txss_tx_tp)\n\t\t\tpmlmeext->txss_tp_th = txss_tx_tp;\n\t\tif (txss_chk_cnt)\n\t\t\tpmlmeext->txss_tp_chk_cnt = txss_chk_cnt;\n\n\t\tRTW_INFO(\"%s txss_ctl_en :%s , txss_tp_th:%d, tp_chk_cnt:%d\\n\",\n\t\t\t__func__, pmlmeext->txss_tp_th ? \"Y\" : \"N\",\n\t\t\tpmlmeext->txss_tp_th, pmlmeext->txss_tp_chk_cnt);\n\n\t}\n\n\treturn count;\n}\n\nint proc_get_txss_tp(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\n\tRTW_PRINT_SEL(m, \"TXSS  Control - %s\\n\", pmlmeext->txss_ctrl_en ? \"enable\" : \"disable\");\n\tRTW_PRINT_SEL(m, \"TXSS  Tx TP TH - %d\\n\", pmlmeext->txss_tp_th);\n\tRTW_PRINT_SEL(m, \"TXSS  check cnt - %d\\n\", pmlmeext->txss_tp_chk_cnt);\n\n\treturn 0;\n}\n#ifdef DBG_CTRL_TXSS\nssize_t proc_set_txss_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\n\tchar tmp[32];\n\tu32 tx_1ss = 0;\n\n\tif (buffer == NULL) {\n\t\tRTW_INFO(\"input buffer is NULL!\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(\"input length is 0!\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\tRTW_INFO(\"input length is too large\\n\");\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%u\",\t&tx_1ss);\n\n\t\tif (num < 1) {\n\t\t\tRTW_INFO(\"input parameters < 1\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tpmlmeext->txss_ctrl_en = _FALSE;\n\n\t\tdbg_ctrl_txss(adapter, tx_1ss);\n\n\t\tRTW_INFO(\"%s set tx to  1ss :%s\\n\", __func__, tx_1ss ? \"Y\" : \"N\");\n\t}\n\n\treturn count;\n}\n\nint proc_get_txss_ctrl(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\n\tRTW_PRINT_SEL(m, \"TXSS  1ss - %s\\n\", pmlmeext->txss_1ss ? \"Y\" : \"N\");\n\n\treturn 0;\n}\n#endif\n#endif\n\n#ifdef CONFIG_DBG_RF_CAL\nint proc_get_iqk_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\treturn 0;\n}\n\nssize_t proc_set_iqk(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu32 recovery, clear, segment;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d %d %d\", &recovery, &clear, &segment);\n\n\t\tif (num != 3) {\n\t\t\tRTW_INFO(\"Invalid format\\n\");\n\t\t\treturn count;\n\t\t}\n\n\t\trtw_hal_iqk_test(padapter, recovery, clear, segment);\n\t}\n\n\treturn count;\n\n}\n\nint proc_get_lck_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\treturn 0;\n}\n\nssize_t proc_set_lck(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu32 trigger;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d\", &trigger);\n\n\t\tif (num != 1) {\n\t\t\tRTW_INFO(\"Invalid format\\n\");\n\t\t\treturn count;\n\t\t}\n\n\t\trtw_hal_lck_test(padapter);\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_DBG_RF_CAL */\n\n#ifdef CONFIG_LPS_CHK_BY_TP\nssize_t proc_set_lps_chk_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\tchar tmp[32];\n\tu32 enable = 0;\n\tu32 lps_tx_tp = 0, lps_rx_tp = 0, lps_bi_tp = 0;\n\tint lps_chk_cnt_th = 0;\n\tu32 lps_tx_pkts = 0, lps_rx_pkts = 0;\n\n\tif (buffer == NULL) {\n\t\tRTW_INFO(\"input buffer is NULL!\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(\"input length is 0!\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\tRTW_INFO(\"input length is too large\\n\");\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%u %u %u %u %d %u %u\",\n\t\t\t&enable, &lps_tx_tp, &lps_rx_tp, &lps_bi_tp,\n\t\t\t&lps_chk_cnt_th, &lps_tx_pkts, &lps_rx_pkts);\n\n\t\tif (num < 1) {\n\t\t\tRTW_INFO(\"input parameters < 1\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tpwrpriv->lps_chk_by_tp = enable;\n\n\t\tif (lps_tx_tp) {\n\t\t\tpwrpriv->lps_tx_tp_th = lps_tx_tp;\n\t\t\tpwrpriv->lps_rx_tp_th = lps_tx_tp;\n\t\t\tpwrpriv->lps_bi_tp_th = lps_tx_tp;\n\t\t}\n\t\tif (lps_rx_tp)\n\t\t\tpwrpriv->lps_rx_tp_th = lps_rx_tp;\n\t\tif (lps_bi_tp)\n\t\t\tpwrpriv->lps_bi_tp_th = lps_bi_tp;\n\n\t\tif (lps_chk_cnt_th)\n\t\t\tpwrpriv->lps_chk_cnt_th = lps_chk_cnt_th;\n\n\t\tif (lps_tx_pkts)\n\t\t\tpwrpriv->lps_tx_pkts = lps_tx_pkts;\n\n\t\tif (lps_rx_pkts)\n\t\t\tpwrpriv->lps_rx_pkts = lps_rx_pkts;\n\n\t\tRTW_INFO(\"%s lps_chk_by_tp:%s , lps_tx_tp_th:%d, lps_tx_tp_th:%d, lps_bi_tp:%d\\n\",\n\t\t\t__func__, pwrpriv->lps_chk_by_tp ? \"Y\" : \"N\",\n\t\t\tpwrpriv->lps_tx_tp_th, pwrpriv->lps_tx_tp_th, pwrpriv->lps_bi_tp_th);\n\t\tRTW_INFO(\"%s lps_chk_cnt_th:%d , lps_tx_pkts:%d, lps_rx_pkts:%d\\n\",\n\t\t\t__func__, pwrpriv->lps_chk_cnt_th, pwrpriv->lps_tx_pkts, pwrpriv->lps_rx_pkts);\n\t}\n\n\treturn count;\n}\n\nint proc_get_lps_chk_tp(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\n\tRTW_PRINT_SEL(m, \"LPS chk by tp - %s\\n\", pwrpriv->lps_chk_by_tp ? \"enable\" : \"disable\");\n\tRTW_PRINT_SEL(m, \"LPS Tx TP TH - %d(Mbps)\\n\", pwrpriv->lps_tx_tp_th);\n\tRTW_PRINT_SEL(m, \"LPS Rx TP TH - %d(Mbps)\\n\", pwrpriv->lps_rx_tp_th);\n\tRTW_PRINT_SEL(m, \"LPS BI TP TH - %d(Mbps)\\n\", pwrpriv->lps_bi_tp_th);\n\n\tRTW_PRINT_SEL(m, \"LPS CHK CNT - %d\\n\", pwrpriv->lps_chk_cnt_th);\n\tRTW_PRINT_SEL(m, \"LPS Tx PKTs - %d\\n\", pwrpriv->lps_tx_pkts);\n\tRTW_PRINT_SEL(m, \"LPS Rx PKTs - %d\\n\", pwrpriv->lps_rx_pkts);\n\treturn 0;\n}\n#endif /*CONFIG_LPS_CHK_BY_TP*/\n#ifdef CONFIG_SUPPORT_STATIC_SMPS\nssize_t proc_set_smps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\tchar tmp[32];\n\tu32 enable = 0;\n\tu32 smps_en, smps_tx_tp = 0, smps_rx_tp = 0;\n\tu32 smps_test = 0, smps_test_en = 0;\n\n\tif (buffer == NULL) {\n\t\tRTW_INFO(\"input buffer is NULL!\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(\"input length is 0!\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\tRTW_INFO(\"input length is too large\\n\");\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%u %u %u %u %u\", &smps_en, &smps_tx_tp, &smps_rx_tp,\n\t\t\t&smps_test, &smps_test_en);\n\n\t\tif (num < 1) {\n\t\t\tRTW_INFO(\"input parameters < 1\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tpmlmeext->ssmps_en = smps_en;\n\t\tif (smps_tx_tp) {\n\t\t\tpmlmeext->ssmps_tx_tp_th= smps_tx_tp;\n\t\t\tpmlmeext->ssmps_rx_tp_th= smps_tx_tp;\n\t\t}\n\t\tif (smps_rx_tp)\n\t\t\tpmlmeext->ssmps_rx_tp_th = smps_rx_tp;\n\n\t\t#ifdef DBG_STATIC_SMPS\n\t\tif (num > 3) {\n\t\t\tpmlmeext->ssmps_test = smps_test;\n\t\t\tpmlmeext->ssmps_test_en = smps_test_en;\n\t\t}\n\t\t#endif\n\t\tRTW_INFO(\"SM PS : %s tx_tp_th:%d, rx_tp_th:%d\\n\",\n\t\t\t(smps_en) ? \"Enable\" : \"Disable\",\n\t\t\tpmlmeext->ssmps_tx_tp_th,\n\t\t\tpmlmeext->ssmps_rx_tp_th);\n\t\t#ifdef DBG_STATIC_SMPS\n\t\tRTW_INFO(\"SM PS : %s ssmps_test_en:%d\\n\",\n\t\t\t(smps_test) ? \"Enable\" : \"Disable\",\n\t\t\tpmlmeext->ssmps_test_en);\n\t\t#endif\n\t}\n\n\treturn count;\n}\n\nint proc_get_smps(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\n\tRTW_PRINT_SEL(m, \"Static SMPS %s\\n\", pmlmeext->ssmps_en ? \"enable\" : \"disable\");\n\tRTW_PRINT_SEL(m, \"Tx TP TH %d\\n\", pmlmeext->ssmps_tx_tp_th);\n\tRTW_PRINT_SEL(m, \"Rx TP TH %d\\n\", pmlmeext->ssmps_rx_tp_th);\n\t#ifdef DBG_STATIC_SMPS\n\tRTW_PRINT_SEL(m, \"test %d, test_en:%d\\n\", pmlmeext->ssmps_test, pmlmeext->ssmps_test_en);\n\t#endif\n\treturn 0;\n}\n#endif /*CONFIG_SUPPORT_STATIC_SMPS*/\n\n#endif /* CONFIG_PROC_DEBUG */\n#define RTW_BUFDUMP_BSIZE\t\t16\n#if 1\ninline void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring,\n\t\t\t\t\tbool _idx_show, const u8 *_hexdata, int _hexdatalen)\n{\n#ifdef CONFIG_RTW_DEBUG\n\tint __i;\n\tu8 *ptr = (u8 *)_hexdata;\n\n\tif (_loglevel <= rtw_drv_log_level) {\n\t\tif (_titlestring) {\n\t\t\tif (sel == RTW_DBGDUMP)\n\t\t\t\tRTW_PRINT(\"\");\n\t\t\t_RTW_PRINT_SEL(sel, \"%s\", _titlestring);\n\t\t\tif (_hexdatalen >= RTW_BUFDUMP_BSIZE)\n\t\t\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t\t}\n\n\t\tfor (__i = 0; __i < _hexdatalen; __i++) {\n\t\t\tif (((__i % RTW_BUFDUMP_BSIZE) == 0) && (_hexdatalen >= RTW_BUFDUMP_BSIZE)) {\n\t\t\t\tif (sel == RTW_DBGDUMP)\n\t\t\t\t\tRTW_PRINT(\"\");\n\t\t\t\tif (_idx_show)\n\t\t\t\t\t_RTW_PRINT_SEL(sel, \"0x%03X: \", __i);\n\t\t\t}\n\t\t\t_RTW_PRINT_SEL(sel, \"%02X%s\", ptr[__i], (((__i + 1) % 4) == 0) ? \"  \" : \" \");\n\t\t\tif ((__i + 1 < _hexdatalen) && ((__i + 1) % RTW_BUFDUMP_BSIZE) == 0)\n\t\t\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t\t}\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n#endif\n}\n#else\ninline void _RTW_STR_DUMP_SEL(void *sel, char *str_out)\n{\n\tif (sel == RTW_DBGDUMP)\n\t\t_dbgdump(\"%s\\n\", str_out);\n\t#if defined(_seqdump)\n\telse\n\t\t_seqdump(sel, \"%s\\n\", str_out);\n\t#endif /*_seqdump*/\n}\ninline void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring,\n\t\t\t\t\tbool _idx_show, u8 *_hexdata, int _hexdatalen)\n{\n\tint __i, len;\n\tint __j, idx;\n\tint block_num, remain_byte;\n\tchar str_out[128] = {'\\0'};\n\tchar str_val[32] = {'\\0'};\n\tchar *p = NULL;\n\tu8 *ptr = (u8 *)_hexdata;\n\n\tif (_loglevel <= rtw_drv_log_level) {\n\t\t/*dump title*/\n\t\tp = &str_out[0];\n\t\tif (_titlestring) {\n\t\t\tif (sel == RTW_DBGDUMP) {\n\t\t\t\tlen = snprintf(str_val, sizeof(str_val), \"%s\", DRIVER_PREFIX);\n\t\t\t\tstrncpy(p, str_val, len);\n\t\t\t\tp += len;\n\t\t\t}\n\t\t\tlen = snprintf(str_val, sizeof(str_val), \"%s\", _titlestring);\n\t\t\tstrncpy(p, str_val, len);\n\t\t\tp += len;\n\t\t}\n\t\tif (p != &str_out[0]) {\n\t\t\t_RTW_STR_DUMP_SEL(sel, str_out);\n\t\t\t_rtw_memset(&str_out, '\\0', sizeof(str_out));\n\t\t}\n\n\t\t/*dump buffer*/\n\t\tblock_num = _hexdatalen / RTW_BUFDUMP_BSIZE;\n\t\tremain_byte = _hexdatalen % RTW_BUFDUMP_BSIZE;\n\t\tfor (__i = 0; __i < block_num; __i++) {\n\t\t\tp = &str_out[0];\n\t\t\tif (sel == RTW_DBGDUMP) {\n\t\t\t\tlen = snprintf(str_val, sizeof(str_val), \"%s\", DRIVER_PREFIX);\n\t\t\t\tstrncpy(p, str_val, len);\n\t\t\t\tp += len;\n\t\t\t}\n\t\t\tif (_idx_show) {\n\t\t\t\tlen = snprintf(str_val, sizeof(str_val), \"0x%03X: \", __i * RTW_BUFDUMP_BSIZE);\n\t\t\t\tstrncpy(p, str_val, len);\n\t\t\t\tp += len;\n\t\t\t}\n\t\t\tfor (__j =0; __j < RTW_BUFDUMP_BSIZE; __j++) {\n\t\t\t\tidx = __i * RTW_BUFDUMP_BSIZE + __j;\n\t\t\t\tlen = snprintf(str_val, sizeof(str_val), \"%02X%s\", ptr[idx], (((__j + 1) % 4) == 0) ? \"  \" : \" \");\n\t\t\t\tstrncpy(p, str_val, len);\n\t\t\t\tp += len;\n\t\t\t}\n\t\t\t_RTW_STR_DUMP_SEL(sel, str_out);\n\t\t\t_rtw_memset(&str_out, '\\0', sizeof(str_out));\n\t\t}\n\n\t\tp = &str_out[0];\n\t\tif ((sel == RTW_DBGDUMP) && remain_byte) {\n\t\t\tlen = snprintf(str_val, sizeof(str_val), \"%s\", DRIVER_PREFIX);\n\t\t\tstrncpy(p, str_val, len);\n\t\t\tp += len;\n\t\t}\n\t\tif (_idx_show && remain_byte) {\n\t\t\tlen = snprintf(str_val, sizeof(str_val), \"0x%03X: \", block_num * RTW_BUFDUMP_BSIZE);\n\t\t\tstrncpy(p, str_val, len);\n\t\t\tp += len;\n\t\t}\n\t\tfor (__i = 0; __i < remain_byte; __i++) {\n\t\t\tidx = block_num * RTW_BUFDUMP_BSIZE + __i;\n\t\t\tlen = snprintf(str_val, sizeof(str_val), \"%02X%s\", ptr[idx], (((__i + 1) % 4) == 0) ? \"  \" : \" \");\n\t\t\tstrncpy(p, str_val, len);\n\t\t\tp += len;\n\t\t}\n\t\t_RTW_STR_DUMP_SEL(sel, str_out);\n\t}\n}\n\n#endif\n"
  },
  {
    "path": "core/rtw_eeprom.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_EEPROM_C_\n\n#include <drv_conf.h>\n#include <osdep_service.h>\n#include <drv_types.h>\n\nvoid up_clk(_adapter\t*padapter,\t u16 *x)\n{\n\t*x = *x | _EESK;\n\trtw_write8(padapter, EE_9346CR, (u8)*x);\n\trtw_udelay_os(CLOCK_RATE);\n\n\n}\n\nvoid down_clk(_adapter\t*padapter, u16 *x)\n{\n\t*x = *x & ~_EESK;\n\trtw_write8(padapter, EE_9346CR, (u8)*x);\n\trtw_udelay_os(CLOCK_RATE);\n}\n\nvoid shift_out_bits(_adapter *padapter, u16 data, u16 count)\n{\n\tu16 x, mask;\n\n\tif (rtw_is_surprise_removed(padapter)) {\n\t\tgoto out;\n\t}\n\tmask = 0x01 << (count - 1);\n\tx = rtw_read8(padapter, EE_9346CR);\n\n\tx &= ~(_EEDO | _EEDI);\n\n\tdo {\n\t\tx &= ~_EEDI;\n\t\tif (data & mask)\n\t\t\tx |= _EEDI;\n\t\tif (rtw_is_surprise_removed(padapter)) {\n\t\t\tgoto out;\n\t\t}\n\t\trtw_write8(padapter, EE_9346CR, (u8)x);\n\t\trtw_udelay_os(CLOCK_RATE);\n\t\tup_clk(padapter, &x);\n\t\tdown_clk(padapter, &x);\n\t\tmask = mask >> 1;\n\t} while (mask);\n\tif (rtw_is_surprise_removed(padapter)) {\n\t\tgoto out;\n\t}\n\tx &= ~_EEDI;\n\trtw_write8(padapter, EE_9346CR, (u8)x);\nout:\n\treturn;\n}\n\nu16 shift_in_bits(_adapter *padapter)\n{\n\tu16 x, d = 0, i;\n\tif (rtw_is_surprise_removed(padapter)) {\n\t\tgoto out;\n\t}\n\tx = rtw_read8(padapter, EE_9346CR);\n\n\tx &= ~(_EEDO | _EEDI);\n\td = 0;\n\n\tfor (i = 0; i < 16; i++) {\n\t\td = d << 1;\n\t\tup_clk(padapter, &x);\n\t\tif (rtw_is_surprise_removed(padapter)) {\n\t\t\tgoto out;\n\t\t}\n\t\tx = rtw_read8(padapter, EE_9346CR);\n\n\t\tx &= ~(_EEDI);\n\t\tif (x & _EEDO)\n\t\t\td |= 1;\n\n\t\tdown_clk(padapter, &x);\n\t}\nout:\n\n\treturn d;\n}\n\nvoid standby(_adapter\t*padapter)\n{\n\tu8   x;\n\tx = rtw_read8(padapter, EE_9346CR);\n\n\tx &= ~(_EECS | _EESK);\n\trtw_write8(padapter, EE_9346CR, x);\n\n\trtw_udelay_os(CLOCK_RATE);\n\tx |= _EECS;\n\trtw_write8(padapter, EE_9346CR, x);\n\trtw_udelay_os(CLOCK_RATE);\n}\n\nu16 wait_eeprom_cmd_done(_adapter *padapter)\n{\n\tu8\tx;\n\tu16\ti, res = _FALSE;\n\tstandby(padapter);\n\tfor (i = 0; i < 200; i++) {\n\t\tx = rtw_read8(padapter, EE_9346CR);\n\t\tif (x & _EEDO) {\n\t\t\tres = _TRUE;\n\t\t\tgoto exit;\n\t\t}\n\t\trtw_udelay_os(CLOCK_RATE);\n\t}\nexit:\n\treturn res;\n}\n\nvoid eeprom_clean(_adapter *padapter)\n{\n\tu16 x;\n\tif (rtw_is_surprise_removed(padapter)) {\n\t\tgoto out;\n\t}\n\tx = rtw_read8(padapter, EE_9346CR);\n\tif (rtw_is_surprise_removed(padapter)) {\n\t\tgoto out;\n\t}\n\tx &= ~(_EECS | _EEDI);\n\trtw_write8(padapter, EE_9346CR, (u8)x);\n\tif (rtw_is_surprise_removed(padapter)) {\n\t\tgoto out;\n\t}\n\tup_clk(padapter, &x);\n\tif (rtw_is_surprise_removed(padapter)) {\n\t\tgoto out;\n\t}\n\tdown_clk(padapter, &x);\nout:\n\treturn;\n}\n\nvoid eeprom_write16(_adapter *padapter, u16 reg, u16 data)\n{\n\tu8 x;\n\tx = rtw_read8(padapter, EE_9346CR);\n\n\tx &= ~(_EEDI | _EEDO | _EESK | _EEM0);\n\tx |= _EEM1 | _EECS;\n\trtw_write8(padapter, EE_9346CR, x);\n\n\tshift_out_bits(padapter, EEPROM_EWEN_OPCODE, 5);\n\n\tif (padapter->EepromAddressSize == 8)\t/* CF+ and SDIO */\n\t\tshift_out_bits(padapter, 0, 6);\n\telse\t\t\t\t\t\t\t\t\t/* USB */\n\t\tshift_out_bits(padapter, 0, 4);\n\n\tstandby(padapter);\n\n\t/* Commented out by rcnjko, 2004.0\n\t * \t  Erase this particular word.  Write the erase opcode and register\n\t *    number in that order. The opcode is 3bits in length; reg is 6 bits long. */\n/*\tshift_out_bits(Adapter, EEPROM_ERASE_OPCODE, 3);\n *\tshift_out_bits(Adapter, reg, Adapter->EepromAddressSize);\n *\n *\tif (wait_eeprom_cmd_done(Adapter ) == FALSE)\n *\t{\n *\t\treturn;\n *\t} */\n\n\n\tstandby(padapter);\n\n\t/* write the new word to the EEPROM */\n\n\t/* send the write opcode the EEPORM */\n\tshift_out_bits(padapter, EEPROM_WRITE_OPCODE, 3);\n\n\t/* select which word in the EEPROM that we are writing to. */\n\tshift_out_bits(padapter, reg, padapter->EepromAddressSize);\n\n\t/* write the data to the selected EEPROM word. */\n\tshift_out_bits(padapter, data, 16);\n\n\tif (wait_eeprom_cmd_done(padapter) == _FALSE)\n\n\t\tgoto exit;\n\n\tstandby(padapter);\n\n\tshift_out_bits(padapter, EEPROM_EWDS_OPCODE, 5);\n\tshift_out_bits(padapter, reg, 4);\n\n\teeprom_clean(padapter);\nexit:\n\treturn;\n}\n\nu16 eeprom_read16(_adapter *padapter, u16 reg)  /* ReadEEprom */\n{\n\n\tu16 x;\n\tu16 data = 0;\n\n\tif (rtw_is_surprise_removed(padapter)) {\n\t\tgoto out;\n\t}\n\t/* select EEPROM, reset bits, set _EECS */\n\tx = rtw_read8(padapter, EE_9346CR);\n\n\tif (rtw_is_surprise_removed(padapter)) {\n\t\tgoto out;\n\t}\n\n\tx &= ~(_EEDI | _EEDO | _EESK | _EEM0);\n\tx |= _EEM1 | _EECS;\n\trtw_write8(padapter, EE_9346CR, (unsigned char)x);\n\n\t/* write the read opcode and register number in that order */\n\t/* The opcode is 3bits in length, reg is 6 bits long */\n\tshift_out_bits(padapter, EEPROM_READ_OPCODE, 3);\n\tshift_out_bits(padapter, reg, padapter->EepromAddressSize);\n\n\t/* Now read the data (16 bits) in from the selected EEPROM word */\n\tdata = shift_in_bits(padapter);\n\n\teeprom_clean(padapter);\nout:\n\n\treturn data;\n\n\n}\n\n\n\n\n/* From even offset */\nvoid eeprom_read_sz(_adapter *padapter, u16 reg, u8 *data, u32 sz)\n{\n\n\tu16 x, data16;\n\tu32 i;\n\tif (rtw_is_surprise_removed(padapter)) {\n\t\tgoto out;\n\t}\n\t/* select EEPROM, reset bits, set _EECS */\n\tx = rtw_read8(padapter, EE_9346CR);\n\n\tif (rtw_is_surprise_removed(padapter)) {\n\t\tgoto out;\n\t}\n\n\tx &= ~(_EEDI | _EEDO | _EESK | _EEM0);\n\tx |= _EEM1 | _EECS;\n\trtw_write8(padapter, EE_9346CR, (unsigned char)x);\n\n\t/* write the read opcode and register number in that order */\n\t/* The opcode is 3bits in length, reg is 6 bits long */\n\tshift_out_bits(padapter, EEPROM_READ_OPCODE, 3);\n\tshift_out_bits(padapter, reg, padapter->EepromAddressSize);\n\n\n\tfor (i = 0; i < sz; i += 2) {\n\t\tdata16 = shift_in_bits(padapter);\n\t\tdata[i] = data16 & 0xff;\n\t\tdata[i + 1] = data16 >> 8;\n\t}\n\n\teeprom_clean(padapter);\nout:\n\treturn;\n}\n\n\n/* addr_off : address offset of the entry in eeprom (not the tuple number of eeprom (reg); that is addr_off !=reg) */\nu8 eeprom_read(_adapter *padapter, u32 addr_off, u8 sz, u8 *rbuf)\n{\n\tu8 quotient, remainder, addr_2align_odd;\n\tu16 reg, stmp , i = 0, idx = 0;\n\treg = (u16)(addr_off >> 1);\n\taddr_2align_odd = (u8)(addr_off & 0x1);\n\n\tif (addr_2align_odd) { /* read that start at high part: e.g  1,3,5,7,9,... */\n\t\tstmp = eeprom_read16(padapter, reg);\n\t\trbuf[idx++] = (u8)((stmp >> 8) & 0xff); /* return hogh-part of the short */\n\t\treg++;\n\t\tsz--;\n\t}\n\n\tquotient = sz >> 1;\n\tremainder = sz & 0x1;\n\n\tfor (i = 0 ; i < quotient; i++) {\n\t\tstmp = eeprom_read16(padapter, reg + i);\n\t\trbuf[idx++] = (u8)(stmp & 0xff);\n\t\trbuf[idx++] = (u8)((stmp >> 8) & 0xff);\n\t}\n\n\treg = reg + i;\n\tif (remainder) { /* end of read at lower part of short : 0,2,4,6,... */\n\t\tstmp = eeprom_read16(padapter, reg);\n\t\trbuf[idx] = (u8)(stmp & 0xff);\n\t}\n\treturn _TRUE;\n}\n\n\n\nvoid read_eeprom_content(_adapter\t*padapter)\n{\n\n\n\n}\n"
  },
  {
    "path": "core/rtw_ieee80211.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _IEEE80211_C\n\n#ifdef CONFIG_PLATFORM_INTEL_BYT\n\t#include <linux/fs.h>\n#endif\n#include <drv_types.h>\n\n\nu8 RTW_WPA_OUI_TYPE[] = { 0x00, 0x50, 0xf2, 1 };\nu16 RTW_WPA_VERSION = 1;\nu8 WPA_AUTH_KEY_MGMT_NONE[] = { 0x00, 0x50, 0xf2, 0 };\nu8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[] = { 0x00, 0x50, 0xf2, 1 };\nu8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[] = { 0x00, 0x50, 0xf2, 2 };\nu8 WPA_CIPHER_SUITE_NONE[] = { 0x00, 0x50, 0xf2, 0 };\nu8 WPA_CIPHER_SUITE_WEP40[] = { 0x00, 0x50, 0xf2, 1 };\nu8 WPA_CIPHER_SUITE_TKIP[] = { 0x00, 0x50, 0xf2, 2 };\nu8 WPA_CIPHER_SUITE_WRAP[] = { 0x00, 0x50, 0xf2, 3 };\nu8 WPA_CIPHER_SUITE_CCMP[] = { 0x00, 0x50, 0xf2, 4 };\nu8 WPA_CIPHER_SUITE_WEP104[] = { 0x00, 0x50, 0xf2, 5 };\n\nu16 RSN_VERSION_BSD = 1;\nu8 RSN_CIPHER_SUITE_NONE[] = { 0x00, 0x0f, 0xac, 0 };\nu8 RSN_CIPHER_SUITE_WEP40[] = { 0x00, 0x0f, 0xac, 1 };\nu8 RSN_CIPHER_SUITE_TKIP[] = { 0x00, 0x0f, 0xac, 2 };\nu8 RSN_CIPHER_SUITE_WRAP[] = { 0x00, 0x0f, 0xac, 3 };\nu8 RSN_CIPHER_SUITE_CCMP[] = { 0x00, 0x0f, 0xac, 4 };\nu8 RSN_CIPHER_SUITE_WEP104[] = { 0x00, 0x0f, 0xac, 5 };\n\nu8 WLAN_AKM_8021X[] = {0x00, 0x0f, 0xac, 1};\nu8 WLAN_AKM_PSK[] = {0x00, 0x0f, 0xac, 2};\nu8 WLAN_AKM_FT_8021X[] = {0x00, 0x0f, 0xac, 3};\nu8 WLAN_AKM_FT_PSK[] = {0x00, 0x0f, 0xac, 4};\nu8 WLAN_AKM_8021X_SHA256[] = {0x00, 0x0f, 0xac, 5};\nu8 WLAN_AKM_PSK_SHA256[] = {0x00, 0x0f, 0xac, 6};\nu8 WLAN_AKM_TDLS[] = {0x00, 0x0f, 0xac, 7};\nu8 WLAN_AKM_SAE[] = {0x00, 0x0f, 0xac, 8};\nu8 WLAN_AKM_FT_OVER_SAE[] = {0x00, 0x0f, 0xac, 9};\nu8 WLAN_AKM_8021X_SUITE_B[] = {0x00, 0x0f, 0xac, 11};\nu8 WLAN_AKM_8021X_SUITE_B_192[] = {0x00, 0x0f, 0xac, 12};\nu8 WLAN_AKM_FILS_SHA256[] = {0x00, 0x0f, 0xac, 14};\nu8 WLAN_AKM_FILS_SHA384[] = {0x00, 0x0f, 0xac, 15};\nu8 WLAN_AKM_FT_FILS_SHA256[] = {0x00, 0x0f, 0xac, 16};\nu8 WLAN_AKM_FT_FILS_SHA384[] = {0x00, 0x0f, 0xac, 17};\n/* -----------------------------------------------------------\n * for adhoc-master to generate ie and provide supported-rate to fw\n * ----------------------------------------------------------- */\n\nu8\tWIFI_CCKRATES[] = {\n\t(IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK),\n\t(IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK),\n\t(IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK),\n\t(IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK)\n};\n\nu8\tWIFI_OFDMRATES[] = {\n\t(IEEE80211_OFDM_RATE_6MB),\n\t(IEEE80211_OFDM_RATE_9MB),\n\t(IEEE80211_OFDM_RATE_12MB),\n\t(IEEE80211_OFDM_RATE_18MB),\n\t(IEEE80211_OFDM_RATE_24MB),\n\tIEEE80211_OFDM_RATE_36MB,\n\tIEEE80211_OFDM_RATE_48MB,\n\tIEEE80211_OFDM_RATE_54MB\n};\n\nu8 mgn_rates_cck[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};\nu8 mgn_rates_ofdm[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M};\nu8 mgn_rates_mcs0_7[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7};\nu8 mgn_rates_mcs8_15[8] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15};\nu8 mgn_rates_mcs16_23[8] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23};\nu8 mgn_rates_mcs24_31[8] = {MGN_MCS24, MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29, MGN_MCS30, MGN_MCS31};\nu8 mgn_rates_vht1ss[10] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4\n\t, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9\n\t\t\t  };\nu8 mgn_rates_vht2ss[10] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4\n\t, MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9\n\t\t\t  };\nu8 mgn_rates_vht3ss[10] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4\n\t, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9\n\t\t\t  };\nu8 mgn_rates_vht4ss[10] = {MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4\n\t, MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9\n\t\t\t  };\n\nstatic const char *const _rate_section_str[] = {\n\t\"CCK\",\n\t\"OFDM\",\n\t\"HT_1SS\",\n\t\"HT_2SS\",\n\t\"HT_3SS\",\n\t\"HT_4SS\",\n\t\"VHT_1SS\",\n\t\"VHT_2SS\",\n\t\"VHT_3SS\",\n\t\"VHT_4SS\",\n\t\"RATE_SECTION_UNKNOWN\",\n};\n\nconst char *rate_section_str(u8 section)\n{\n\tsection = (section >= RATE_SECTION_NUM) ? RATE_SECTION_NUM : section;\n\treturn _rate_section_str[section];\n}\n\nstruct rate_section_ent rates_by_sections[RATE_SECTION_NUM] = {\n\t{RF_1TX, 4, mgn_rates_cck},\n\t{RF_1TX, 8, mgn_rates_ofdm},\n\t{RF_1TX, 8, mgn_rates_mcs0_7},\n\t{RF_2TX, 8, mgn_rates_mcs8_15},\n\t{RF_3TX, 8, mgn_rates_mcs16_23},\n\t{RF_4TX, 8, mgn_rates_mcs24_31},\n\t{RF_1TX, 10, mgn_rates_vht1ss},\n\t{RF_2TX, 10, mgn_rates_vht2ss},\n\t{RF_3TX, 10, mgn_rates_vht3ss},\n\t{RF_4TX, 10, mgn_rates_vht4ss},\n};\n\nint rtw_get_bit_value_from_ieee_value(u8 val)\n{\n\tunsigned char dot11_rate_table[] = {2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108, 0}; /* last element must be zero!! */\n\n\tint i = 0;\n\twhile (dot11_rate_table[i] != 0) {\n\t\tif (dot11_rate_table[i] == val)\n\t\t\treturn BIT(i);\n\t\ti++;\n\t}\n\treturn 0;\n}\nuint rtw_get_cckrate_size(u8 *rate, u32 rate_length)\n{\n\tint i = 0;\n\twhile(i < rate_length){\n\t\tRTW_DBG(\"%s, rate[%d]=%u\\n\", __FUNCTION__, i, rate[i]);\n\t\tif (((rate[i] & 0x7f) == 2) || ((rate[i] & 0x7f) == 4) ||\n\t\t\t((rate[i] & 0x7f) == 11)  || ((rate[i] & 0x7f) == 22))\n\t\t\ti++;\n\t\telse\n\t\t\tbreak;\n\t}\n\treturn i;\n}\n\nuint\trtw_is_cckrates_included(u8 *rate)\n{\n\tu32\ti = 0;\n\n\twhile (rate[i] != 0) {\n\t\tif ((((rate[i]) & 0x7f) == 2)\t|| (((rate[i]) & 0x7f) == 4) ||\n\t\t    (((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) == 22))\n\t\t\treturn _TRUE;\n\t\ti++;\n\t}\n\n\treturn _FALSE;\n}\n\nuint\trtw_is_cckratesonly_included(u8 *rate)\n{\n\tu32 i = 0;\n\n\n\twhile (rate[i] != 0) {\n\t\tif ((((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) &&\n\t\t    (((rate[i]) & 0x7f) != 11)  && (((rate[i]) & 0x7f) != 22))\n\t\t\treturn _FALSE;\n\n\t\ti++;\n\t}\n\n\treturn _TRUE;\n\n}\n\nint rtw_check_network_type(unsigned char *rate, int ratelen, int channel)\n{\n\tif (channel > 14) {\n\t\tif ((rtw_is_cckrates_included(rate)) == _TRUE)\n\t\t\treturn WIRELESS_INVALID;\n\t\telse\n\t\t\treturn WIRELESS_11A;\n\t} else { /* could be pure B, pure G, or B/G */\n\t\tif ((rtw_is_cckratesonly_included(rate)) == _TRUE)\n\t\t\treturn WIRELESS_11B;\n\t\telse if ((rtw_is_cckrates_included(rate)) == _TRUE)\n\t\t\treturn\tWIRELESS_11BG;\n\t\telse\n\t\t\treturn WIRELESS_11G;\n\t}\n\n}\n\nu8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source,\n\t\t     unsigned int *frlen)\n{\n\t_rtw_memcpy((void *)pbuf, (void *)source, len);\n\t*frlen = *frlen + len;\n\treturn pbuf + len;\n}\n\n/* rtw_set_ie will update frame length */\nu8 *rtw_set_ie\n(\n\tu8 *pbuf,\n\tsint index,\n\tuint len,\n\tconst u8 *source,\n\tuint *frlen /* frame length */\n)\n{\n\t*pbuf = (u8)index;\n\n\t*(pbuf + 1) = (u8)len;\n\n\tif (len > 0)\n\t\t_rtw_memcpy((void *)(pbuf + 2), (void *)source, len);\n\n\tif (frlen)\n\t\t*frlen = *frlen + (len + 2);\n\n\treturn pbuf + len + 2;\n}\n\ninline u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode,\n\t\t\t\tu8 new_ch, u8 ch_switch_cnt)\n{\n\tu8 ie_data[3];\n\n\tie_data[0] = ch_switch_mode;\n\tie_data[1] = new_ch;\n\tie_data[2] = ch_switch_cnt;\n\treturn rtw_set_ie(buf, WLAN_EID_CHANNEL_SWITCH,  3, ie_data, buf_len);\n}\n\ninline u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset)\n{\n\tif (ch_offset == SCN)\n\t\treturn HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\telse if (ch_offset == SCA)\n\t\treturn HAL_PRIME_CHNL_OFFSET_LOWER;\n\telse if (ch_offset == SCB)\n\t\treturn HAL_PRIME_CHNL_OFFSET_UPPER;\n\n\treturn HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n}\n\ninline u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset)\n{\n\tif (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)\n\t\treturn SCN;\n\telse if (ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)\n\t\treturn SCA;\n\telse if (ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)\n\t\treturn SCB;\n\n\treturn SCN;\n}\n\ninline u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset)\n{\n\treturn rtw_set_ie(buf, WLAN_EID_SECONDARY_CHANNEL_OFFSET,  1, &secondary_ch_offset, buf_len);\n}\n\ninline u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl,\n\t\tu8 flags, u16 reason, u16 precedence)\n{\n\tu8 ie_data[6];\n\n\tie_data[0] = ttl;\n\tie_data[1] = flags;\n\tRTW_PUT_LE16((u8 *)&ie_data[2], reason);\n\tRTW_PUT_LE16((u8 *)&ie_data[4], precedence);\n\n\treturn rtw_set_ie(buf, 0x118,  6, ie_data, buf_len);\n}\n\n/*----------------------------------------------------------------------------\nindex: the information element id index, limit is the limit for search\n-----------------------------------------------------------------------------*/\nu8 *rtw_get_ie(const u8 *pbuf, sint index, sint *len, sint limit)\n{\n\tsint tmp, i;\n\tconst u8 *p;\n\tif (limit < 1) {\n\t\treturn NULL;\n\t}\n\n\tp = pbuf;\n\ti = 0;\n\t*len = 0;\n\twhile (1) {\n\t\tif (*p == index) {\n\t\t\t*len = *(p + 1);\n\t\t\treturn (u8 *)p;\n\t\t} else {\n\t\t\ttmp = *(p + 1);\n\t\t\tp += (tmp + 2);\n\t\t\ti += (tmp + 2);\n\t\t}\n\t\tif (i >= limit)\n\t\t\tbreak;\n\t}\n\treturn NULL;\n}\n\n/**\n * rtw_get_ie_ex - Search specific IE from a series of IEs\n * @in_ie: Address of IEs to search\n * @in_len: Length limit from in_ie\n * @eid: Element ID to match\n * @oui: OUI to match\n * @oui_len: OUI length\n * @ie: If not NULL and the specific IE is found, the IE will be copied to the buf starting from the specific IE\n * @ielen: If not NULL and the specific IE is found, will set to the length of the entire IE\n *\n * Returns: The address of the specific IE found, or NULL\n */\nu8 *rtw_get_ie_ex(const u8 *in_ie, uint in_len, u8 eid, const u8 *oui, u8 oui_len, u8 *ie, uint *ielen)\n{\n\tuint cnt;\n\tconst u8 *target_ie = NULL;\n\n\n\tif (ielen)\n\t\t*ielen = 0;\n\n\tif (!in_ie || in_len <= 0)\n\t\treturn (u8 *)target_ie;\n\n\tcnt = 0;\n\n\twhile (cnt < in_len) {\n\t\tif (eid == in_ie[cnt]\n\t\t    && (!oui || _rtw_memcmp(&in_ie[cnt + 2], oui, oui_len) == _TRUE)) {\n\t\t\ttarget_ie = &in_ie[cnt];\n\n\t\t\tif (ie)\n\t\t\t\t_rtw_memcpy(ie, &in_ie[cnt], in_ie[cnt + 1] + 2);\n\n\t\t\tif (ielen)\n\t\t\t\t*ielen = in_ie[cnt + 1] + 2;\n\n\t\t\tbreak;\n\t\t} else {\n\t\t\tcnt += in_ie[cnt + 1] + 2; /* goto next\t */\n\t\t}\n\n\t}\n\n\treturn (u8 *)target_ie;\n}\n\n/**\n * rtw_ies_remove_ie - Find matching IEs and remove\n * @ies: Address of IEs to search\n * @ies_len: Pointer of length of ies, will update to new length\n * @offset: The offset to start scarch\n * @eid: Element ID to match\n * @oui: OUI to match\n * @oui_len: OUI length\n *\n * Returns: _SUCCESS: ies is updated, _FAIL: not updated\n */\nint rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len)\n{\n\tint ret = _FAIL;\n\tu8 *target_ie;\n\tu32 target_ielen;\n\tu8 *start;\n\tuint search_len;\n\n\tif (!ies || !ies_len || *ies_len <= offset)\n\t\tgoto exit;\n\n\tstart = ies + offset;\n\tsearch_len = *ies_len - offset;\n\n\twhile (1) {\n\t\ttarget_ie = rtw_get_ie_ex(start, search_len, eid, oui, oui_len, NULL, &target_ielen);\n\t\tif (target_ie && target_ielen) {\n\t\t\tu8 *remain_ies = target_ie + target_ielen;\n\t\t\tuint remain_len = search_len - (remain_ies - start);\n\n\t\t\t_rtw_memmove(target_ie, remain_ies, remain_len);\n\t\t\t*ies_len = *ies_len - target_ielen;\n\t\t\tret = _SUCCESS;\n\n\t\t\tstart = target_ie;\n\t\t\tsearch_len = remain_len;\n\t\t} else\n\t\t\tbreak;\n\t}\nexit:\n\treturn ret;\n}\n\nvoid rtw_set_supported_rate(u8 *SupportedRates, uint mode)\n{\n\n\t_rtw_memset(SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX);\n\n\tswitch (mode) {\n\tcase WIRELESS_11B:\n\t\t_rtw_memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN);\n\t\tbreak;\n\n\tcase WIRELESS_11G:\n\tcase WIRELESS_11A:\n\tcase WIRELESS_11_5N:\n\tcase WIRELESS_11A_5N: /* Todo: no basic rate for ofdm ? */\n\tcase WIRELESS_11_5AC:\n\t\t_rtw_memcpy(SupportedRates, WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN);\n\t\tbreak;\n\n\tcase WIRELESS_11BG:\n\tcase WIRELESS_11G_24N:\n\tcase WIRELESS_11_24N:\n\tcase WIRELESS_11BG_24N:\n\t\t_rtw_memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN);\n\t\t_rtw_memcpy(SupportedRates + IEEE80211_CCK_RATE_LEN, WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN);\n\t\tbreak;\n\n\t}\n}\n\nvoid rtw_filter_suppport_rateie(WLAN_BSSID_EX *pbss_network, u8 keep)\n{\n\tu8 i, idx = 0, new_rate[NDIS_802_11_LENGTH_RATES_EX], *p;\n\tint ret = 0;\n\tuint iscck, isofdm, ie_orilen = 0, remain_len;\n\tu8 *remain_ies;\n\n\tp = rtw_get_ie(pbss_network->IEs + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &ie_orilen, (pbss_network->IELength - _BEACON_IE_OFFSET_));\n\tif (!p)\n\t\treturn;\n\n\t_rtw_memset(new_rate, 0, NDIS_802_11_LENGTH_RATES_EX);\n\tfor (i=0; i < ie_orilen; i++) {\n\t\tiscck = rtw_is_cck_rate(p[i+2]);\n\t\tisofdm= rtw_is_ofdm_rate(p[i+2]);\n\t\tif (((keep == CCK) && iscck)\n\t\t\t|| ((keep == OFDM) && isofdm))\n\t\t\tnew_rate[idx++]= rtw_is_basic_rate_ofdm(p[i+2]) ? p[i+2]|IEEE80211_BASIC_RATE_MASK : p[i+2];\n\t}\n\t/*\tupdate rate ie\t*/\n\tp[1] = idx;\n\t_rtw_memcpy(p+2, new_rate, idx);\n\t/*\tupdate remain ie & IELength*/\n\tremain_ies = p + 2 + ie_orilen;\n\tremain_len = pbss_network->IELength - (remain_ies - pbss_network->IEs);\n\t_rtw_memmove(p+2+idx, remain_ies, remain_len);\n\tpbss_network->IELength -= (ie_orilen - idx);\n}\n \n\n/*\n\tAdjust those items by given wireless_mode\n\t\t1. pbss_network->IELength\n\t\t2. pbss_network->IE (SUPPORTRATE & EXT_SUPPORTRATE)\n\t\t3. pbss_network->SupportedRates\n*/\n\nu8 rtw_update_rate_bymode(WLAN_BSSID_EX *pbss_network, u32 mode)\n{\n\tu8 network_type, *p, *ie = pbss_network->IEs;\n\tsint ie_len;\n\tuint network_ielen = pbss_network->IELength;\n\n\tif (mode == WIRELESS_11B) {\n\t\t/*only keep CCK in support_rate IE and remove whole ext_support_rate IE*/\n\t\trtw_filter_suppport_rateie(pbss_network, CCK);\n\t\tp = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ie_len, pbss_network->IELength - _BEACON_IE_OFFSET_);\n\t\tif (p) {\n\t\t\trtw_ies_remove_ie(ie , &network_ielen, _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, NULL, 0);\n\t\t\tpbss_network->IELength -= ie_len;\n\t\t}\n\t\tnetwork_type = WIRELESS_11B;\n\t} else if ((mode & WIRELESS_11B) == 0) {\n\t\t/* Remove CCK in support_rate IE */\n\t\trtw_filter_suppport_rateie(pbss_network, OFDM);\n\t\tif (pbss_network->Configuration.DSConfig > 14)\n\t\t\tnetwork_type = WIRELESS_11A;\n\t\telse\n\t\t\tnetwork_type = WIRELESS_11G;\n\t} else\n\t\tnetwork_type = WIRELESS_11BG;\t\t/*\tdo nothing\t*/\n\n\trtw_set_supported_rate(pbss_network->SupportedRates, network_type);\n\treturn network_type;\n}\n\nuint\trtw_get_rateset_len(u8\t*rateset)\n{\n\tuint i = 0;\n\twhile (1) {\n\t\tif ((rateset[i]) == 0)\n\t\t\tbreak;\n\n\t\tif (i > 12)\n\t\t\tbreak;\n\n\t\ti++;\n\t}\n\treturn i;\n}\n\nint rtw_generate_ie(struct registry_priv *pregistrypriv)\n{\n\tu8\twireless_mode;\n\tint\tsz = 0, rateLen;\n\tWLAN_BSSID_EX\t*pdev_network = &pregistrypriv->dev_network;\n\tu8\t*ie = pdev_network->IEs;\n\n\n\t/* timestamp will be inserted by hardware */\n\tsz += 8;\n\tie += sz;\n\n\t/* beacon interval : 2bytes */\n\t*(u16 *)ie = cpu_to_le16((u16)pdev_network->Configuration.BeaconPeriod); /* BCN_INTERVAL; */\n\tsz += 2;\n\tie += 2;\n\n\t/* capability info */\n\t*(u16 *)ie = 0;\n\n\t*(u16 *)ie |= cpu_to_le16(cap_IBSS);\n\n\tif (pregistrypriv->preamble == PREAMBLE_SHORT)\n\t\t*(u16 *)ie |= cpu_to_le16(cap_ShortPremble);\n\n\tif (pdev_network->Privacy)\n\t\t*(u16 *)ie |= cpu_to_le16(cap_Privacy);\n\n\tsz += 2;\n\tie += 2;\n\n\t/* SSID */\n\tie = rtw_set_ie(ie, _SSID_IE_, pdev_network->Ssid.SsidLength, pdev_network->Ssid.Ssid, &sz);\n\n\t/* supported rates */\n\tif (pregistrypriv->wireless_mode == WIRELESS_11ABGN) {\n\t\tif (pdev_network->Configuration.DSConfig > 14)\n\t\t\twireless_mode = WIRELESS_11A_5N;\n\t\telse\n\t\t\twireless_mode = WIRELESS_11BG_24N;\n\t} else if (pregistrypriv->wireless_mode == WIRELESS_MODE_MAX) { /* WIRELESS_11ABGN | WIRELESS_11AC */\n\t\tif (pdev_network->Configuration.DSConfig > 14)\n\t\t\twireless_mode = WIRELESS_11_5AC;\n\t\telse\n\t\t\twireless_mode = WIRELESS_11BG_24N;\n\t} else\n\t\twireless_mode = pregistrypriv->wireless_mode;\n\n\trtw_set_supported_rate(pdev_network->SupportedRates, wireless_mode) ;\n\n\trateLen = rtw_get_rateset_len(pdev_network->SupportedRates);\n\n\tif (rateLen > 8) {\n\t\tie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, 8, pdev_network->SupportedRates, &sz);\n\t\t/* ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz); */\n\t} else\n\t\tie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, rateLen, pdev_network->SupportedRates, &sz);\n\n\t/* DS parameter set */\n\tie = rtw_set_ie(ie, _DSSET_IE_, 1, (u8 *)&(pdev_network->Configuration.DSConfig), &sz);\n\n\n\t/* IBSS Parameter Set */\n\n\tie = rtw_set_ie(ie, _IBSS_PARA_IE_, 2, (u8 *)&(pdev_network->Configuration.ATIMWindow), &sz);\n\n\tif (rateLen > 8)\n\t\tie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz);\n\n#ifdef CONFIG_80211N_HT\n\t/* HT Cap. */\n\tif (is_supported_ht(pregistrypriv->wireless_mode)\n\t    && (pregistrypriv->ht_enable == _TRUE)) {\n\t\t/* todo: */\n\t}\n#endif /* CONFIG_80211N_HT */\n\n\t/* pdev_network->IELength =  sz; */ /* update IELength */\n\n\n\t/* return _SUCCESS; */\n\n\treturn sz;\n\n}\n\nunsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit)\n{\n\tint len;\n\tu16 val16;\n\tunsigned char wpa_oui_type[] = {0x00, 0x50, 0xf2, 0x01};\n\tu8 *pbuf = pie;\n\tint limit_new = limit;\n\n\twhile (1) {\n\t\tpbuf = rtw_get_ie(pbuf, _WPA_IE_ID_, &len, limit_new);\n\n\t\tif (pbuf) {\n\n\t\t\t/* check if oui matches... */\n\t\t\tif (_rtw_memcmp((pbuf + 2), wpa_oui_type, sizeof(wpa_oui_type)) == _FALSE)\n\n\t\t\t\tgoto check_next_ie;\n\n\t\t\t/* check version... */\n\t\t\t_rtw_memcpy((u8 *)&val16, (pbuf + 6), sizeof(val16));\n\n\t\t\tval16 = le16_to_cpu(val16);\n\t\t\tif (val16 != 0x0001)\n\t\t\t\tgoto check_next_ie;\n\n\t\t\t*wpa_ie_len = *(pbuf + 1);\n\n\t\t\treturn pbuf;\n\n\t\t} else {\n\n\t\t\t*wpa_ie_len = 0;\n\t\t\treturn NULL;\n\t\t}\n\ncheck_next_ie:\n\n\t\tlimit_new = limit - (pbuf - pie) - 2 - len;\n\n\t\tif (limit_new <= 0)\n\t\t\tbreak;\n\n\t\tpbuf += (2 + len);\n\n\t}\n\n\t*wpa_ie_len = 0;\n\n\treturn NULL;\n\n}\n\nunsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit)\n{\n\n\treturn rtw_get_ie(pie, _WPA2_IE_ID_, rsn_ie_len, limit);\n\n}\n\nint rtw_get_wpa_cipher_suite(u8 *s)\n{\n\tif (_rtw_memcmp(s, WPA_CIPHER_SUITE_NONE, WPA_SELECTOR_LEN) == _TRUE)\n\t\treturn WPA_CIPHER_NONE;\n\tif (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP40, WPA_SELECTOR_LEN) == _TRUE)\n\t\treturn WPA_CIPHER_WEP40;\n\tif (_rtw_memcmp(s, WPA_CIPHER_SUITE_TKIP, WPA_SELECTOR_LEN) == _TRUE)\n\t\treturn WPA_CIPHER_TKIP;\n\tif (_rtw_memcmp(s, WPA_CIPHER_SUITE_CCMP, WPA_SELECTOR_LEN) == _TRUE)\n\t\treturn WPA_CIPHER_CCMP;\n\tif (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP104, WPA_SELECTOR_LEN) == _TRUE)\n\t\treturn WPA_CIPHER_WEP104;\n\n\treturn 0;\n}\n\nint rtw_get_wpa2_cipher_suite(u8 *s)\n{\n\tif (_rtw_memcmp(s, RSN_CIPHER_SUITE_NONE, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WPA_CIPHER_NONE;\n\tif (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP40, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WPA_CIPHER_WEP40;\n\tif (_rtw_memcmp(s, RSN_CIPHER_SUITE_TKIP, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WPA_CIPHER_TKIP;\n\tif (_rtw_memcmp(s, RSN_CIPHER_SUITE_CCMP, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WPA_CIPHER_CCMP;\n\tif (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP104, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WPA_CIPHER_WEP104;\n\n\treturn 0;\n}\n\nu32 rtw_get_akm_suite_bitmap(u8 *s)\n{\n\tif (_rtw_memcmp(s, WLAN_AKM_8021X, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WLAN_AKM_TYPE_8021X;\n\tif (_rtw_memcmp(s, WLAN_AKM_PSK, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WLAN_AKM_TYPE_PSK;\n\tif (_rtw_memcmp(s, WLAN_AKM_FT_8021X, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WLAN_AKM_TYPE_FT_8021X;\n\tif (_rtw_memcmp(s, WLAN_AKM_FT_PSK, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WLAN_AKM_TYPE_FT_PSK;\n\tif (_rtw_memcmp(s, WLAN_AKM_8021X_SHA256, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WLAN_AKM_TYPE_8021X_SHA256;\n\tif (_rtw_memcmp(s, WLAN_AKM_PSK_SHA256, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WLAN_AKM_TYPE_PSK_SHA256;\n\tif (_rtw_memcmp(s, WLAN_AKM_TDLS, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WLAN_AKM_TYPE_TDLS;\n\tif (_rtw_memcmp(s, WLAN_AKM_SAE, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WLAN_AKM_TYPE_SAE;\n\tif (_rtw_memcmp(s, WLAN_AKM_FT_OVER_SAE, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WLAN_AKM_TYPE_FT_OVER_SAE;\n\tif (_rtw_memcmp(s, WLAN_AKM_8021X_SUITE_B, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WLAN_AKM_TYPE_8021X_SUITE_B;\n\tif (_rtw_memcmp(s, WLAN_AKM_8021X_SUITE_B_192, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WLAN_AKM_TYPE_8021X_SUITE_B_192;\n\tif (_rtw_memcmp(s, WLAN_AKM_FILS_SHA256, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WLAN_AKM_TYPE_FILS_SHA256;\n\tif (_rtw_memcmp(s, WLAN_AKM_FILS_SHA384, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WLAN_AKM_TYPE_FILS_SHA384;\n\tif (_rtw_memcmp(s, WLAN_AKM_FT_FILS_SHA256, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WLAN_AKM_TYPE_FT_FILS_SHA256;\n\tif (_rtw_memcmp(s, WLAN_AKM_FT_FILS_SHA384, RSN_SELECTOR_LEN) == _TRUE)\n\t\treturn WLAN_AKM_TYPE_FT_FILS_SHA384;\n\n\treturn 0;\n}\n\nint rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher,\n\tint *pairwise_cipher, u32 *akm)\n{\n\tint i, ret = _SUCCESS;\n\tint left, count;\n\tu8 *pos;\n\tu8 SUITE_1X[4] = {0x00, 0x50, 0xf2, 1};\n\n\tif (wpa_ie_len <= 0) {\n\t\t/* No WPA IE - fail silently */\n\t\treturn _FAIL;\n\t}\n\n\n\tif ((*wpa_ie != _WPA_IE_ID_) || (*(wpa_ie + 1) != (u8)(wpa_ie_len - 2)) ||\n\t    (_rtw_memcmp(wpa_ie + 2, RTW_WPA_OUI_TYPE, WPA_SELECTOR_LEN) != _TRUE))\n\t\treturn _FAIL;\n\n\tpos = wpa_ie;\n\n\tpos += 8;\n\tleft = wpa_ie_len - 8;\n\n\n\t/* group_cipher */\n\tif (left >= WPA_SELECTOR_LEN) {\n\n\t\t*group_cipher = rtw_get_wpa_cipher_suite(pos);\n\n\t\tpos += WPA_SELECTOR_LEN;\n\t\tleft -= WPA_SELECTOR_LEN;\n\n\t} else if (left > 0) {\n\n\t\treturn _FAIL;\n\t}\n\n\n\t/* pairwise_cipher */\n\tif (left >= 2) {\n\t\t/* count = le16_to_cpu(*(u16*)pos);\t */\n\t\tcount = RTW_GET_LE16(pos);\n\t\tpos += 2;\n\t\tleft -= 2;\n\n\t\tif (count == 0 || left < count * WPA_SELECTOR_LEN) {\n\t\t\treturn _FAIL;\n\t\t}\n\n\t\tfor (i = 0; i < count; i++) {\n\t\t\t*pairwise_cipher |= rtw_get_wpa_cipher_suite(pos);\n\n\t\t\tpos += WPA_SELECTOR_LEN;\n\t\t\tleft -= WPA_SELECTOR_LEN;\n\t\t}\n\n\t} else if (left == 1) {\n\t\treturn _FAIL;\n\t}\n\n\tif (akm) {\n\t\tif (left >= 6) {\n\t\t\tpos += 2;\n\t\t\tif (_rtw_memcmp(pos, SUITE_1X, 4) == 1) {\n\t\t\t\t*akm = WLAN_AKM_TYPE_8021X;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn ret;\n\n}\n\nint rtw_rsne_info_parse(const u8 *ie, uint ie_len, struct rsne_info *info)\n{\n\tconst u8 *pos = ie;\n\tu16 cnt;\n\n\t_rtw_memset(info, 0, sizeof(struct rsne_info));\n\n\tif (ie + ie_len < pos + 4)\n\t\tgoto err;\n\n\tif (*ie != WLAN_EID_RSN || *(ie + 1) != ie_len - 2)\n\t\tgoto err;\n\tpos += 2 + 2;\n\n\t/* Group CS */\n\tif (ie + ie_len < pos + 4) {\n\t\tif (ie + ie_len != pos)\n\t\t\tgoto err;\n\t\tgoto exit;\n\t}\n\tinfo->gcs = (u8 *)pos;\n\tpos += 4;\n\n\t/* Pairwise CS */\n\tif (ie + ie_len < pos + 2) {\n\t\tif (ie + ie_len != pos)\n\t\t\tgoto err;\n\t\tgoto exit;\n\t}\n\tcnt = RTW_GET_LE16(pos);\n\tpos += 2;\n\tif (ie + ie_len < pos + 4 * cnt) {\n\t\tif (ie + ie_len != pos)\n\t\t\tgoto err;\n\t\tgoto exit;\n\t}\n\tinfo->pcs_cnt = cnt;\n\tinfo->pcs_list = (u8 *)pos;\n\tpos += 4 * cnt;\n\n\t/* AKM */\n\tif (ie + ie_len < pos + 2) {\n\t\tif (ie + ie_len != pos)\n\t\t\tgoto err;\n\t\tgoto exit;\n\t}\n\tcnt = RTW_GET_LE16(pos);\n\tpos += 2;\n\tif (ie + ie_len < pos + 4 * cnt) {\n\t\tif (ie + ie_len != pos)\n\t\t\tgoto err;\n\t\tgoto exit;\n\t}\n\tinfo->akm_cnt = cnt;\n\tinfo->akm_list = (u8 *)pos;\n\tpos += 4 * cnt;\n\n\t/* RSN cap */\n\tif (ie + ie_len < pos + 2) {\n\t\tif (ie + ie_len != pos)\n\t\t\tgoto err;\n\t\tgoto exit;\n\t}\n\tinfo->cap = (u8 *)pos;\n\tpos += 2;\n\n\t/* PMKID */\n\tif (ie + ie_len < pos + 2) {\n\t\tif (ie + ie_len != pos)\n\t\t\tgoto err;\n\t\tgoto exit;\n\t}\n\tcnt = RTW_GET_LE16(pos);\n\tpos += 2;\n\tif (ie + ie_len < pos + 16 * cnt) {\n\t\tif (ie + ie_len != pos)\n\t\t\tgoto err;\n\t\tgoto exit;\n\t}\n\tinfo->pmkid_cnt = cnt;\n\tinfo->pmkid_list = (u8 *)pos;\n\tpos += 16 * cnt;\n\n\t/* Group Mgmt CS */\n\tif (ie + ie_len < pos + 4) {\n\t\tif (ie + ie_len != pos)\n\t\t\tgoto err;\n\t\tgoto exit;\n\t}\n\tinfo->gmcs = (u8 *)pos;\n\nexit:\n\treturn _SUCCESS;\n\nerr:\n\tinfo->err = 1;\n\treturn _FAIL;\n}\n\nint rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher,\n\tint *pairwise_cipher, u32 *akm, u8 *mfp_opt)\n{\n\tstruct rsne_info info;\n\tint i, ret = _SUCCESS;\n\n\tret = rtw_rsne_info_parse(rsn_ie, rsn_ie_len, &info);\n\tif (ret != _SUCCESS)\n\t\tgoto exit;\n\n\tif (group_cipher) {\n\t\tif (info.gcs)\n\t\t\t*group_cipher = rtw_get_wpa2_cipher_suite(info.gcs);\n\t\telse\n\t\t\t*group_cipher = 0;\n\t}\n\n\tif (pairwise_cipher) {\n\t\t*pairwise_cipher = 0;\n\t\tfor (i = 0; i < info.pcs_cnt; i++)\n\t\t\t*pairwise_cipher |= rtw_get_wpa2_cipher_suite(info.pcs_list + 4 * i);\n\t}\n\n\tif (akm) {\n\t\t*akm = 0;\n\t\tfor (i = 0; i < info.akm_cnt; i++)\n\t\t\t*akm |= rtw_get_akm_suite_bitmap(info.akm_list + 4 * i);\n\t}\n\n\tif (mfp_opt) {\n\t\t*mfp_opt = MFP_NO;\n\t\tif (info.cap)\n\t\t\t*mfp_opt = GET_RSN_CAP_MFP_OPTION(info.cap);\n\t}\n\nexit:\n\treturn ret;\n}\n\n/* #ifdef CONFIG_WAPI_SUPPORT */\nint rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len)\n{\n\tint len = 0;\n\tu8 authmode;\n\tuint\tcnt;\n\tu8 wapi_oui1[4] = {0x0, 0x14, 0x72, 0x01};\n\tu8 wapi_oui2[4] = {0x0, 0x14, 0x72, 0x02};\n\n\n\tif (wapi_len)\n\t\t*wapi_len = 0;\n\n\tif (!in_ie || in_len <= 0)\n\t\treturn len;\n\n\tcnt = (_TIMESTAMP_ + _BEACON_ITERVAL_ + _CAPABILITY_);\n\n\twhile (cnt < in_len) {\n\t\tauthmode = in_ie[cnt];\n\n\t\t/* if(authmode==_WAPI_IE_) */\n\t\tif (authmode == _WAPI_IE_ && (_rtw_memcmp(&in_ie[cnt + 6], wapi_oui1, 4) == _TRUE ||\n\t\t\t_rtw_memcmp(&in_ie[cnt + 6], wapi_oui2, 4) == _TRUE)) {\n\t\t\tif (wapi_ie)\n\t\t\t\t_rtw_memcpy(wapi_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);\n\n\t\t\tif (wapi_len)\n\t\t\t\t*wapi_len = in_ie[cnt + 1] + 2;\n\n\t\t\tcnt += in_ie[cnt + 1] + 2; /* get next */\n\t\t} else {\n\t\t\tcnt += in_ie[cnt + 1] + 2; /* get next */\n\t\t}\n\t}\n\n\tif (wapi_len)\n\t\tlen = *wapi_len;\n\n\n\treturn len;\n\n}\n/* #endif */\n\nint rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie, u16 *wpa_len)\n{\n\tu8 authmode, sec_idx;\n\tu8 wpa_oui[4] = {0x0, 0x50, 0xf2, 0x01};\n\tuint\tcnt;\n\n\n\t/* Search required WPA or WPA2 IE and copy to sec_ie[ ] */\n\n\tcnt = (_TIMESTAMP_ + _BEACON_ITERVAL_ + _CAPABILITY_);\n\n\tsec_idx = 0;\n\n\twhile (cnt < in_len) {\n\t\tauthmode = in_ie[cnt];\n\n\t\tif ((authmode == _WPA_IE_ID_) && (_rtw_memcmp(&in_ie[cnt + 2], &wpa_oui[0], 4) == _TRUE)) {\n\n\t\t\tif (wpa_ie)\n\t\t\t\t_rtw_memcpy(wpa_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);\n\n\t\t\t*wpa_len = in_ie[cnt + 1] + 2;\n\t\t\tcnt += in_ie[cnt + 1] + 2; /* get next */\n\t\t} else {\n\t\t\tif (authmode == _WPA2_IE_ID_) {\n\n\t\t\t\tif (rsn_ie)\n\t\t\t\t\t_rtw_memcpy(rsn_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);\n\n\t\t\t\t*rsn_len = in_ie[cnt + 1] + 2;\n\t\t\t\tcnt += in_ie[cnt + 1] + 2; /* get next */\n\t\t\t} else {\n\t\t\t\tcnt += in_ie[cnt + 1] + 2; /* get next */\n\t\t\t}\n\t\t}\n\n\t}\n\n\n\treturn *rsn_len + *wpa_len;\n\n}\n\nu8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen)\n{\n\tu8 match = _FALSE;\n\tu8 eid, wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};\n\n\tif (ie_ptr == NULL)\n\t\treturn match;\n\n\teid = ie_ptr[0];\n\n\tif ((eid == _WPA_IE_ID_) && (_rtw_memcmp(&ie_ptr[2], wps_oui, 4) == _TRUE)) {\n\t\t/* RTW_INFO(\"==> found WPS_IE.....\\n\"); */\n\t\t*wps_ielen = ie_ptr[1] + 2;\n\t\tmatch = _TRUE;\n\t}\n\treturn match;\n}\n\nu8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, enum bss_type frame_type)\n{\n\tu8\t*wps = NULL;\n\n\tRTW_INFO(\"[%s] frame_type = %d\\n\", __FUNCTION__, frame_type);\n\tswitch (frame_type) {\n\tcase BSS_TYPE_BCN:\n\tcase BSS_TYPE_PROB_RSP: {\n\t\t/*\tBeacon or Probe Response */\n\t\twps = rtw_get_wps_ie(in_ie + _PROBERSP_IE_OFFSET_, in_len - _PROBERSP_IE_OFFSET_, wps_ie, wps_ielen);\n\t\tbreak;\n\t}\n\tcase BSS_TYPE_PROB_REQ: {\n\t\t/*\tProbe Request */\n\t\twps = rtw_get_wps_ie(in_ie + _PROBEREQ_IE_OFFSET_ , in_len - _PROBEREQ_IE_OFFSET_ , wps_ie, wps_ielen);\n\t\tbreak;\n\t}\n\tdefault:\n\tcase BSS_TYPE_UNDEF:\n\t\tbreak;\n\t}\n\treturn wps;\n}\n\n/**\n * rtw_get_wps_ie - Search WPS IE from a series of IEs\n * @in_ie: Address of IEs to search\n * @in_len: Length limit from in_ie\n * @wps_ie: If not NULL and WPS IE is found, WPS IE will be copied to the buf starting from wps_ie\n * @wps_ielen: If not NULL and WPS IE is found, will set to the length of the entire WPS IE\n *\n * Returns: The address of the WPS IE found, or NULL\n */\nu8 *rtw_get_wps_ie(const u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen)\n{\n\tuint cnt;\n\tconst u8 *wpsie_ptr = NULL;\n\tu8 eid, wps_oui[4] = {0x00, 0x50, 0xf2, 0x04};\n\n\tif (wps_ielen)\n\t\t*wps_ielen = 0;\n\n\tif (!in_ie) {\n\t\trtw_warn_on(1);\n\t\treturn (u8 *)wpsie_ptr;\n\t}\n\n\tif (in_len <= 0)\n\t\treturn (u8 *)wpsie_ptr;\n\n\tcnt = 0;\n\n\twhile (cnt + 1 + 4 < in_len) {\n\t\teid = in_ie[cnt];\n\n\t\tif (cnt + 1 + 4 >= MAX_IE_SZ) {\n\t\t\trtw_warn_on(1);\n\t\t\treturn NULL;\n\t\t}\n\n\t\tif (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], wps_oui, 4) == _TRUE) {\n\t\t\twpsie_ptr = in_ie + cnt;\n\n\t\t\tif (wps_ie)\n\t\t\t\t_rtw_memcpy(wps_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);\n\n\t\t\tif (wps_ielen)\n\t\t\t\t*wps_ielen = in_ie[cnt + 1] + 2;\n\n\t\t\tbreak;\n\t\t} else\n\t\t\tcnt += in_ie[cnt + 1] + 2;\n\n\t}\n\n\treturn (u8 *)wpsie_ptr;\n}\n\n/**\n * rtw_get_wps_attr - Search a specific WPS attribute from a given WPS IE\n * @wps_ie: Address of WPS IE to search\n * @wps_ielen: Length limit from wps_ie\n * @target_attr_id: The attribute ID of WPS attribute to search\n * @buf_attr: If not NULL and the WPS attribute is found, WPS attribute will be copied to the buf starting from buf_attr\n * @len_attr: If not NULL and the WPS attribute is found, will set to the length of the entire WPS attribute\n *\n * Returns: the address of the specific WPS attribute found, or NULL\n */\nu8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_attr, u32 *len_attr)\n{\n\tu8 *attr_ptr = NULL;\n\tu8 *target_attr_ptr = NULL;\n\tu8 wps_oui[4] = {0x00, 0x50, 0xF2, 0x04};\n\n\tif (len_attr)\n\t\t*len_attr = 0;\n\n\tif ((wps_ie[0] != _VENDOR_SPECIFIC_IE_) ||\n\t    (_rtw_memcmp(wps_ie + 2, wps_oui , 4) != _TRUE))\n\t\treturn attr_ptr;\n\n\t/* 6 = 1(Element ID) + 1(Length) + 4(WPS OUI) */\n\tattr_ptr = wps_ie + 6; /* goto first attr */\n\n\twhile (attr_ptr - wps_ie < wps_ielen) {\n\t\t/* 4 = 2(Attribute ID) + 2(Length) */\n\t\tu16 attr_id = RTW_GET_BE16(attr_ptr);\n\t\tu16 attr_data_len = RTW_GET_BE16(attr_ptr + 2);\n\t\tu16 attr_len = attr_data_len + 4;\n\n\t\t/* RTW_INFO(\"%s attr_ptr:%p, id:%u, length:%u\\n\", __FUNCTION__, attr_ptr, attr_id, attr_data_len); */\n\t\tif (attr_id == target_attr_id) {\n\t\t\ttarget_attr_ptr = attr_ptr;\n\n\t\t\tif (buf_attr)\n\t\t\t\t_rtw_memcpy(buf_attr, attr_ptr, attr_len);\n\n\t\t\tif (len_attr)\n\t\t\t\t*len_attr = attr_len;\n\n\t\t\tbreak;\n\t\t} else {\n\t\t\tattr_ptr += attr_len; /* goto next */\n\t\t}\n\n\t}\n\n\treturn target_attr_ptr;\n}\n\n/**\n * rtw_get_wps_attr_content - Search a specific WPS attribute content from a given WPS IE\n * @wps_ie: Address of WPS IE to search\n * @wps_ielen: Length limit from wps_ie\n * @target_attr_id: The attribute ID of WPS attribute to search\n * @buf_content: If not NULL and the WPS attribute is found, WPS attribute content will be copied to the buf starting from buf_content\n * @len_content: If not NULL and the WPS attribute is found, will set to the length of the WPS attribute content\n *\n * Returns: the address of the specific WPS attribute content found, or NULL\n */\nu8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_content, uint *len_content)\n{\n\tu8 *attr_ptr;\n\tu32 attr_len;\n\n\tif (len_content)\n\t\t*len_content = 0;\n\n\tattr_ptr = rtw_get_wps_attr(wps_ie, wps_ielen, target_attr_id, NULL, &attr_len);\n\n\tif (attr_ptr && attr_len) {\n\t\tif (buf_content)\n\t\t\t_rtw_memcpy(buf_content, attr_ptr + 4, attr_len - 4);\n\n\t\tif (len_content)\n\t\t\t*len_content = attr_len - 4;\n\n\t\treturn attr_ptr + 4;\n\t}\n\n\treturn NULL;\n}\n\nstatic int rtw_ieee802_11_parse_vendor_specific(u8 *pos, uint elen,\n\t\tstruct rtw_ieee802_11_elems *elems,\n\t\tint show_errors)\n{\n\tunsigned int oui;\n\n\t/* first 3 bytes in vendor specific information element are the IEEE\n\t * OUI of the vendor. The following byte is used a vendor specific\n\t * sub-type. */\n\tif (elen < 4) {\n\t\tif (show_errors) {\n\t\t\tRTW_INFO(\"short vendor specific \"\n\t\t\t\t \"information element ignored (len=%lu)\\n\",\n\t\t\t\t (unsigned long) elen);\n\t\t}\n\t\treturn -1;\n\t}\n\n\toui = RTW_GET_BE24(pos);\n\tswitch (oui) {\n\tcase OUI_MICROSOFT:\n\t\t/* Microsoft/Wi-Fi information elements are further typed and\n\t\t * subtyped */\n\t\tswitch (pos[3]) {\n\t\tcase 1:\n\t\t\t/* Microsoft OUI (00:50:F2) with OUI Type 1:\n\t\t\t * real WPA information element */\n\t\t\telems->wpa_ie = pos;\n\t\t\telems->wpa_ie_len = elen;\n\t\t\tbreak;\n\t\tcase WME_OUI_TYPE: /* this is a Wi-Fi WME info. element */\n\t\t\tif (elen < 5) {\n\t\t\t\tRTW_DBG(\"short WME \"\n\t\t\t\t\t\"information element ignored \"\n\t\t\t\t\t\"(len=%lu)\\n\",\n\t\t\t\t\t(unsigned long) elen);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tswitch (pos[4]) {\n\t\t\tcase WME_OUI_SUBTYPE_INFORMATION_ELEMENT:\n\t\t\tcase WME_OUI_SUBTYPE_PARAMETER_ELEMENT:\n\t\t\t\telems->wme = pos;\n\t\t\t\telems->wme_len = elen;\n\t\t\t\tbreak;\n\t\t\tcase WME_OUI_SUBTYPE_TSPEC_ELEMENT:\n\t\t\t\telems->wme_tspec = pos;\n\t\t\t\telems->wme_tspec_len = elen;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tRTW_DBG(\"unknown WME \"\n\t\t\t\t\t\"information element ignored \"\n\t\t\t\t\t\"(subtype=%d len=%lu)\\n\",\n\t\t\t\t\tpos[4], (unsigned long) elen);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\t/* Wi-Fi Protected Setup (WPS) IE */\n\t\t\telems->wps_ie = pos;\n\t\t\telems->wps_ie_len = elen;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tRTW_DBG(\"Unknown Microsoft \"\n\t\t\t\t\"information element ignored \"\n\t\t\t\t\"(type=%d len=%lu)\\n\",\n\t\t\t\tpos[3], (unsigned long) elen);\n\t\t\treturn -1;\n\t\t}\n\t\tbreak;\n\n\tcase OUI_BROADCOM:\n\t\tswitch (pos[3]) {\n\t\tcase VENDOR_HT_CAPAB_OUI_TYPE:\n\t\t\telems->vendor_ht_cap = pos;\n\t\t\telems->vendor_ht_cap_len = elen;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tRTW_DBG(\"Unknown Broadcom \"\n\t\t\t\t\"information element ignored \"\n\t\t\t\t\"(type=%d len=%lu)\\n\",\n\t\t\t\tpos[3], (unsigned long) elen);\n\t\t\treturn -1;\n\t\t}\n\t\tbreak;\n\n\tdefault:\n\t\tRTW_DBG(\"unknown vendor specific information \"\n\t\t\t\"element ignored (vendor OUI %02x:%02x:%02x \"\n\t\t\t\"len=%lu)\\n\",\n\t\t\tpos[0], pos[1], pos[2], (unsigned long) elen);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n\n}\n\n/**\n * ieee802_11_parse_elems - Parse information elements in management frames\n * @start: Pointer to the start of IEs\n * @len: Length of IE buffer in octets\n * @elems: Data structure for parsed elements\n * @show_errors: Whether to show parsing errors in debug log\n * Returns: Parsing result\n */\nParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len,\n\t\t\t\t    struct rtw_ieee802_11_elems *elems,\n\t\t\t\t    int show_errors)\n{\n\tuint left = len;\n\tu8 *pos = start;\n\tint unknown = 0;\n\n\t_rtw_memset(elems, 0, sizeof(*elems));\n\n\twhile (left >= 2) {\n\t\tu8 id, elen;\n\n\t\tid = *pos++;\n\t\telen = *pos++;\n\t\tleft -= 2;\n\n\t\tif (elen > left) {\n\t\t\tif (show_errors) {\n\t\t\t\tRTW_INFO(\"IEEE 802.11 element \"\n\t\t\t\t\t \"parse failed (id=%d elen=%d \"\n\t\t\t\t\t \"left=%lu)\\n\",\n\t\t\t\t\t id, elen, (unsigned long) left);\n\t\t\t}\n\t\t\treturn ParseFailed;\n\t\t}\n\n\t\tswitch (id) {\n\t\tcase WLAN_EID_SSID:\n\t\t\telems->ssid = pos;\n\t\t\telems->ssid_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_SUPP_RATES:\n\t\t\telems->supp_rates = pos;\n\t\t\telems->supp_rates_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_FH_PARAMS:\n\t\t\telems->fh_params = pos;\n\t\t\telems->fh_params_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_DS_PARAMS:\n\t\t\telems->ds_params = pos;\n\t\t\telems->ds_params_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_CF_PARAMS:\n\t\t\telems->cf_params = pos;\n\t\t\telems->cf_params_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_TIM:\n\t\t\telems->tim = pos;\n\t\t\telems->tim_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_IBSS_PARAMS:\n\t\t\telems->ibss_params = pos;\n\t\t\telems->ibss_params_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_CHALLENGE:\n\t\t\telems->challenge = pos;\n\t\t\telems->challenge_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_ERP_INFO:\n\t\t\telems->erp_info = pos;\n\t\t\telems->erp_info_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_EXT_SUPP_RATES:\n\t\t\telems->ext_supp_rates = pos;\n\t\t\telems->ext_supp_rates_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_VENDOR_SPECIFIC:\n\t\t\tif (rtw_ieee802_11_parse_vendor_specific(pos, elen,\n\t\t\t\t\telems,\n\t\t\t\t\tshow_errors))\n\t\t\t\tunknown++;\n\t\t\tbreak;\n\t\tcase WLAN_EID_RSN:\n\t\t\telems->rsn_ie = pos;\n\t\t\telems->rsn_ie_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_PWR_CAPABILITY:\n\t\t\telems->power_cap = pos;\n\t\t\telems->power_cap_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_SUPPORTED_CHANNELS:\n\t\t\telems->supp_channels = pos;\n\t\t\telems->supp_channels_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_MOBILITY_DOMAIN:\n\t\t\telems->mdie = pos;\n\t\t\telems->mdie_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_FAST_BSS_TRANSITION:\n\t\t\telems->ftie = pos;\n\t\t\telems->ftie_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_TIMEOUT_INTERVAL:\n\t\t\telems->timeout_int = pos;\n\t\t\telems->timeout_int_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_HT_CAP:\n\t\t\telems->ht_capabilities = pos;\n\t\t\telems->ht_capabilities_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_HT_OPERATION:\n\t\t\telems->ht_operation = pos;\n\t\t\telems->ht_operation_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_VHT_CAPABILITY:\n\t\t\telems->vht_capabilities = pos;\n\t\t\telems->vht_capabilities_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_VHT_OPERATION:\n\t\t\telems->vht_operation = pos;\n\t\t\telems->vht_operation_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_VHT_OP_MODE_NOTIFY:\n\t\t\telems->vht_op_mode_notify = pos;\n\t\t\telems->vht_op_mode_notify_len = elen;\n\t\t\tbreak;\n\t\tcase _EID_RRM_EN_CAP_IE_:\n\t\t\telems->rm_en_cap = pos;\n\t\t\telems->rm_en_cap_len = elen;\n\t\t\tbreak;\n#ifdef CONFIG_RTW_MESH\n\t\tcase WLAN_EID_PREQ:\n\t\t\telems->preq = pos;\n\t\t\telems->preq_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_PREP:\n\t\t\telems->prep = pos;\n\t\t\telems->prep_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_PERR:\n\t\t\telems->perr = pos;\n\t\t\telems->perr_len = elen;\n\t\t\tbreak;\n\t\tcase WLAN_EID_RANN:\n\t\t\telems->rann = pos;\n\t\t\telems->rann_len = elen;\n\t\t\tbreak;\n#endif\n\t\tdefault:\n\t\t\tunknown++;\n\t\t\tif (!show_errors)\n\t\t\t\tbreak;\n\t\t\tRTW_DBG(\"IEEE 802.11 element parse \"\n\t\t\t\t\"ignored unknown element (id=%d elen=%d)\\n\",\n\t\t\t\tid, elen);\n\t\t\tbreak;\n\t\t}\n\n\t\tleft -= elen;\n\t\tpos += elen;\n\t}\n\n\tif (left)\n\t\treturn ParseFailed;\n\n\treturn unknown ? ParseUnknown : ParseOK;\n\n}\n\nstatic u8 key_char2num(u8 ch);\nstatic u8 key_char2num(u8 ch)\n{\n\tif ((ch >= '0') && (ch <= '9'))\n\t\treturn ch - '0';\n\telse if ((ch >= 'a') && (ch <= 'f'))\n\t\treturn ch - 'a' + 10;\n\telse if ((ch >= 'A') && (ch <= 'F'))\n\t\treturn ch - 'A' + 10;\n\telse\n\t\treturn 0xff;\n}\n\nu8 str_2char2num(u8 hch, u8 lch);\nu8 str_2char2num(u8 hch, u8 lch)\n{\n\treturn (key_char2num(hch) * 10) + key_char2num(lch);\n}\n\nu8 key_2char2num(u8 hch, u8 lch);\nu8 key_2char2num(u8 hch, u8 lch)\n{\n\treturn (key_char2num(hch) << 4) | key_char2num(lch);\n}\n\nvoid macstr2num(u8 *dst, u8 *src);\nvoid macstr2num(u8 *dst, u8 *src)\n{\n\tint\tjj, kk;\n\tfor (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)\n\t\tdst[jj] = key_2char2num(src[kk], src[kk + 1]);\n}\n\nu8 convert_ip_addr(u8 hch, u8 mch, u8 lch)\n{\n\treturn (key_char2num(hch) * 100) + (key_char2num(mch) * 10) + key_char2num(lch);\n}\n\n#ifdef CONFIG_PLATFORM_INTEL_BYT\n#define MAC_ADDRESS_LEN 12\n\nint rtw_get_mac_addr_intel(unsigned char *buf)\n{\n\tint ret = 0;\n\tint i;\n\tstruct file *fp = NULL;\n\tmm_segment_t oldfs;\n\tunsigned char c_mac[MAC_ADDRESS_LEN];\n\tchar fname[] = \"/config/wifi/mac.txt\";\n\tint jj, kk;\n\n\tRTW_INFO(\"%s Enter\\n\", __FUNCTION__);\n\n\tret = rtw_retrieve_from_file(fname, c_mac, MAC_ADDRESS_LEN);\n\tif (ret < MAC_ADDRESS_LEN)\n\t\treturn -1;\n\n\tfor (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 2)\n\t\tbuf[jj] = key_2char2num(c_mac[kk], c_mac[kk + 1]);\n\n\tRTW_INFO(\"%s: read from file mac address: \"MAC_FMT\"\\n\",\n\t\t __FUNCTION__, MAC_ARG(buf));\n\n\treturn 0;\n}\n#endif /* CONFIG_PLATFORM_INTEL_BYT */\n\n/*\n * Description:\n * rtw_check_invalid_mac_address:\n * This is only used for checking mac address valid or not.\n *\n * Input:\n * adapter: mac_address pointer.\n * check_local_bit: check locally bit or not.\n *\n * Output:\n * _TRUE: The mac address is invalid.\n * _FALSE: The mac address is valid.\n *\n * Auther: Isaac.Li\n */\nu8 rtw_check_invalid_mac_address(u8 *mac_addr, u8 check_local_bit)\n{\n\tu8 null_mac_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};\n\tu8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tu8 res = _FALSE;\n\n\tif (_rtw_memcmp(mac_addr, null_mac_addr, ETH_ALEN)) {\n\t\tres = _TRUE;\n\t\tgoto func_exit;\n\t}\n\n\tif (_rtw_memcmp(mac_addr, multi_mac_addr, ETH_ALEN)) {\n\t\tres = _TRUE;\n\t\tgoto func_exit;\n\t}\n\n\tif (mac_addr[0] & BIT0) {\n\t\tres = _TRUE;\n\t\tgoto func_exit;\n\t}\n\n\tif (check_local_bit == _TRUE) {\n\t\tif (mac_addr[0] & BIT1) {\n\t\t\tres = _TRUE;\n\t\t\tgoto func_exit;\n\t\t}\n\t}\n\nfunc_exit:\n\treturn res;\n}\n\nextern char *rtw_initmac;\n/**\n * rtw_macaddr_cfg - Decide the mac address used\n * @out: buf to store mac address decided\n * @hw_mac_addr: mac address from efuse/epprom\n */\nvoid rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr)\n{\n#define DEFAULT_RANDOM_MACADDR 1\n\tu8 mac[ETH_ALEN];\n\n\tif (out == NULL) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\t/* Users specify the mac address */\n\tif (rtw_initmac) {\n\t\tint jj, kk;\n\n\t\tfor (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)\n\t\t\tmac[jj] = key_2char2num(rtw_initmac[kk], rtw_initmac[kk + 1]);\n\n\t\tgoto err_chk;\n\t}\n\n\t/* platform specified */\n#ifdef CONFIG_PLATFORM_INTEL_BYT\n\tif (rtw_get_mac_addr_intel(mac) == 0)\n\t\tgoto err_chk;\n#endif\n\n\t/* Use the mac address stored in the Efuse */\n\tif (hw_mac_addr) {\n\t\t_rtw_memcpy(mac, hw_mac_addr, ETH_ALEN);\n\t\tgoto err_chk;\n\t}\n\nerr_chk:\n\tif (rtw_check_invalid_mac_address(mac, _TRUE) == _TRUE) {\n#if DEFAULT_RANDOM_MACADDR\n\t\tRTW_ERR(\"invalid mac addr:\"MAC_FMT\", assign random MAC\\n\", MAC_ARG(mac));\n\t\t*((u32 *)(&mac[2])) = rtw_random32();\n\t\tmac[0] = 0x00;\n\t\tmac[1] = 0xe0;\n\t\tmac[2] = 0x4c;\n#else\n\t\tRTW_ERR(\"invalid mac addr:\"MAC_FMT\", assign default one\\n\", MAC_ARG(mac));\n\t\tmac[0] = 0x00;\n\t\tmac[1] = 0xe0;\n\t\tmac[2] = 0x4c;\n\t\tmac[3] = 0x87;\n\t\tmac[4] = 0x00;\n\t\tmac[5] = 0x00;\n#endif\n\t}\n\n\t_rtw_memcpy(out, mac, ETH_ALEN);\n\tRTW_INFO(\"%s mac addr:\"MAC_FMT\"\\n\", __func__, MAC_ARG(out));\n}\n\n#ifdef CONFIG_80211N_HT\nvoid dump_ht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len)\n{\n\tif (buf_len != HT_CAP_IE_LEN) {\n\t\tRTW_PRINT_SEL(sel, \"Invalid HT capability IE len:%d != %d\\n\", buf_len, HT_CAP_IE_LEN);\n\t\treturn;\n\t}\n\n\tRTW_PRINT_SEL(sel, \"cap_info:%02x%02x:%s\\n\", *(buf), *(buf + 1)\n\t\t, GET_HT_CAP_ELE_CHL_WIDTH(buf) ? \" 40MHz\" : \" 20MHz\");\n\tRTW_PRINT_SEL(sel, \"A-MPDU Parameters:\"HT_AMPDU_PARA_FMT\"\\n\"\n\t\t      , HT_AMPDU_PARA_ARG(HT_CAP_ELE_AMPDU_PARA(buf)));\n\tRTW_PRINT_SEL(sel, \"Supported MCS Set:\"HT_SUP_MCS_SET_FMT\"\\n\"\n\t\t      , HT_SUP_MCS_SET_ARG(HT_CAP_ELE_SUP_MCS_SET(buf)));\n}\n\nvoid dump_ht_cap_ie(void *sel, const u8 *ie, u32 ie_len)\n{\n\tconst u8 *ht_cap_ie;\n\tsint ht_cap_ielen;\n\n\tht_cap_ie = rtw_get_ie(ie, WLAN_EID_HT_CAP, &ht_cap_ielen, ie_len);\n\tif (!ie || ht_cap_ie != ie)\n\t\treturn;\n\n\tdump_ht_cap_ie_content(sel, ht_cap_ie + 2, ht_cap_ielen);\n}\n\nconst char *const _ht_sc_offset_str[] = {\n\t\"SCN\",\n\t\"SCA\",\n\t\"SC-RSVD\",\n\t\"SCB\",\n};\n\nvoid dump_ht_op_ie_content(void *sel, const u8 *buf, u32 buf_len)\n{\n\tif (buf_len != HT_OP_IE_LEN) {\n\t\tRTW_PRINT_SEL(sel, \"Invalid HT operation IE len:%d != %d\\n\", buf_len, HT_OP_IE_LEN);\n\t\treturn;\n\t}\n\n\tRTW_PRINT_SEL(sel, \"ch:%u%s %s\\n\"\n\t\t, GET_HT_OP_ELE_PRI_CHL(buf)\n\t\t, GET_HT_OP_ELE_STA_CHL_WIDTH(buf) ? \"\" : \" 20MHz only\"\n\t\t, ht_sc_offset_str(GET_HT_OP_ELE_2ND_CHL_OFFSET(buf))\n\t);\n}\n\nvoid dump_ht_op_ie(void *sel, const u8 *ie, u32 ie_len)\n{\n\tconst u8 *ht_op_ie;\n\tsint ht_op_ielen;\n\n\tht_op_ie = rtw_get_ie(ie, WLAN_EID_HT_OPERATION, &ht_op_ielen, ie_len);\n\tif (!ie || ht_op_ie != ie)\n\t\treturn;\n\n\tdump_ht_op_ie_content(sel, ht_op_ie + 2, ht_op_ielen);\n}\n#endif /* CONFIG_80211N_HT */\n\nvoid dump_ies(void *sel, const u8 *buf, u32 buf_len)\n{\n\tconst u8 *pos = buf;\n\tu8 id, len;\n\n\twhile (pos - buf + 1 < buf_len) {\n\t\tid = *pos;\n\t\tlen = *(pos + 1);\n\n\t\tRTW_PRINT_SEL(sel, \"%s ID:%u, LEN:%u\\n\", __FUNCTION__, id, len);\n#ifdef CONFIG_80211N_HT\n\t\tdump_ht_cap_ie(sel, pos, len + 2);\n\t\tdump_ht_op_ie(sel, pos, len + 2);\n#endif\n#ifdef CONFIG_80211AC_VHT\n\t\tdump_vht_cap_ie(sel, pos, len + 2);\n\t\tdump_vht_op_ie(sel, pos, len + 2);\n#endif\n\t\tdump_wps_ie(sel, pos, len + 2);\n#ifdef CONFIG_P2P\n\t\tdump_p2p_ie(sel, pos, len + 2);\n#ifdef CONFIG_WFD\n\t\tdump_wfd_ie(sel, pos, len + 2);\n#endif\n#endif\n\n\t\tpos += (2 + len);\n\t}\n}\n\nvoid dump_wps_ie(void *sel, const u8 *ie, u32 ie_len)\n{\n\tconst u8 *pos = ie;\n\tu16 id;\n\tu16 len;\n\n\tconst u8 *wps_ie;\n\tuint wps_ielen;\n\n\twps_ie = rtw_get_wps_ie(ie, ie_len, NULL, &wps_ielen);\n\tif (wps_ie != ie || wps_ielen == 0)\n\t\treturn;\n\n\tpos += 6;\n\twhile (pos - ie + 4 <= ie_len) {\n\t\tid = RTW_GET_BE16(pos);\n\t\tlen = RTW_GET_BE16(pos + 2);\n\n\t\tRTW_PRINT_SEL(sel, \"%s ID:0x%04x, LEN:%u%s\\n\", __func__, id, len\n\t\t\t, ((pos - ie + 4 + len) <= ie_len) ? \"\" : \"(exceed ie_len)\");\n\n\t\tpos += (4 + len);\n\t}\n}\n\n/**\n * rtw_ies_get_chbw - get operation ch, bw, offset from IEs of BSS.\n * @ies: pointer of the first tlv IE\n * @ies_len: length of @ies\n * @ch: pointer of ch, used as output\n * @bw: pointer of bw, used as output\n * @offset: pointer of offset, used as output\n * @ht: check HT IEs\n * @vht: check VHT IEs, if true imply ht is true\n */\nvoid rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht)\n{\n\tu8 *p;\n\tint\tie_len;\n\n\t*ch = 0;\n\t*bw = CHANNEL_WIDTH_20;\n\t*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\n\tp = rtw_get_ie(ies, _DSSET_IE_, &ie_len, ies_len);\n\tif (p && ie_len > 0)\n\t\t*ch = *(p + 2);\n\n#ifdef CONFIG_80211N_HT\n\tif (ht || vht) {\n\t\tu8 *ht_cap_ie, *ht_op_ie;\n\t\tint ht_cap_ielen, ht_op_ielen;\n\n\t\tht_cap_ie = rtw_get_ie(ies, EID_HTCapability, &ht_cap_ielen, ies_len);\n\t\tif (ht_cap_ie && ht_cap_ielen) {\n\t\t\tif (GET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2))\n\t\t\t\t*bw = CHANNEL_WIDTH_40;\n\t\t}\n\n\t\tht_op_ie = rtw_get_ie(ies, EID_HTInfo, &ht_op_ielen, ies_len);\n\t\tif (ht_op_ie && ht_op_ielen) {\n\t\t\tif (*ch == 0)\n\t\t\t\t*ch = GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2);\n\t\t\telse if (*ch != 0 && *ch != GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2)) {\n\t\t\t\tRTW_INFO(\"%s ch inconsistent, DSSS:%u, HT primary:%u\\n\"\n\t\t\t\t\t, __func__, *ch, GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2));\n\t\t\t}\n\n\t\t\tif (!GET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2))\n\t\t\t\t*bw = CHANNEL_WIDTH_20;\n\n\t\t\tif (*bw == CHANNEL_WIDTH_40) {\n\t\t\t\tswitch (GET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2)) {\n\t\t\t\tcase SCA:\n\t\t\t\t\t*offset = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\t\t\t\tbreak;\n\t\t\t\tcase SCB:\n\t\t\t\t\t*offset = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n#ifdef CONFIG_80211AC_VHT\n\t\tif (vht) {\n\t\t\tu8 *vht_op_ie;\n\t\t\tint vht_op_ielen;\n\n\t\t\tvht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len);\n\t\t\tif (vht_op_ie && vht_op_ielen) {\n\t\t\t\tif (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2) >= 1)\n\t\t\t\t\t*bw = CHANNEL_WIDTH_80;\n\t\t\t}\n\t\t}\n#endif /* CONFIG_80211AC_VHT */\n\n\t}\n#endif /* CONFIG_80211N_HT */\n}\n\nvoid rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht)\n{\n\trtw_ies_get_chbw(bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)\n\t\t, bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)\n\t\t, ch, bw, offset, ht, vht);\n\n\tif (*ch == 0)\n\t\t*ch = bss->Configuration.DSConfig;\n\telse if (*ch != bss->Configuration.DSConfig) {\n\t\tRTW_INFO(\"inconsistent ch - ies:%u bss->Configuration.DSConfig:%u\\n\"\n\t\t\t , *ch, bss->Configuration.DSConfig);\n\t\t*ch = bss->Configuration.DSConfig;\n\t\trtw_warn_on(1);\n\t}\n}\n\n/**\n * rtw_is_chbw_grouped - test if the two ch settings can be grouped together\n * @ch_a: ch of set a\n * @bw_a: bw of set a\n * @offset_a: offset of set a\n * @ch_b: ch of set b\n * @bw_b: bw of set b\n * @offset_b: offset of set b\n */\nbool rtw_is_chbw_grouped(u8 ch_a, u8 bw_a, u8 offset_a\n\t\t\t , u8 ch_b, u8 bw_b, u8 offset_b)\n{\n\tbool is_grouped = _FALSE;\n\n\tif (ch_a != ch_b) {\n\t\t/* ch is different */\n\t\tgoto exit;\n\t} else if ((bw_a == CHANNEL_WIDTH_40 || bw_a == CHANNEL_WIDTH_80)\n\t\t   && (bw_b == CHANNEL_WIDTH_40 || bw_b == CHANNEL_WIDTH_80)\n\t\t  ) {\n\t\tif (offset_a != offset_b)\n\t\t\tgoto exit;\n\t}\n\n\tis_grouped = _TRUE;\n\nexit:\n\treturn is_grouped;\n}\n\n/**\n * rtw_sync_chbw - obey g_ch, adjust g_bw, g_offset, bw, offset\n * @req_ch: pointer of the request ch, may be modified further\n * @req_bw: pointer of the request bw, may be modified further\n * @req_offset: pointer of the request offset, may be modified further\n * @g_ch: pointer of the ongoing group ch\n * @g_bw: pointer of the ongoing group bw, may be modified further\n * @g_offset: pointer of the ongoing group offset, may be modified further\n */\nvoid rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset\n\t\t   , u8 *g_ch, u8 *g_bw, u8 *g_offset)\n{\n\n\t*req_ch = *g_ch;\n\n\tif (*req_bw == CHANNEL_WIDTH_80 && *g_ch <= 14) {\n\t\t/*2.4G ch, downgrade to 40Mhz */\n\t\t*req_bw = CHANNEL_WIDTH_40;\n\t}\n\n\tswitch (*req_bw) {\n\tcase CHANNEL_WIDTH_80:\n\t\tif (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80)\n\t\t\t*req_offset = *g_offset;\n\t\telse if (*g_bw == CHANNEL_WIDTH_20)\n\t\t\trtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset);\n\n\t\tif (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) {\n\t\t\tRTW_ERR(\"%s req 80MHz BW without offset, down to 20MHz\\n\", __func__);\n\t\t\trtw_warn_on(1);\n\t\t\t*req_bw = CHANNEL_WIDTH_20;\n\t\t}\n\t\tbreak;\n\tcase CHANNEL_WIDTH_40:\n\t\tif (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80)\n\t\t\t*req_offset = *g_offset;\n\t\telse if (*g_bw == CHANNEL_WIDTH_20)\n\t\t\trtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset);\n\n\t\tif (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) {\n\t\t\tRTW_ERR(\"%s req 40MHz BW without offset, down to 20MHz\\n\", __func__);\n\t\t\trtw_warn_on(1);\n\t\t\t*req_bw = CHANNEL_WIDTH_20;\n\t\t}\n\t\tbreak;\n\tcase CHANNEL_WIDTH_20:\n\t\t*req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tbreak;\n\tdefault:\n\t\tRTW_ERR(\"%s req unsupported BW:%u\\n\", __func__, *req_bw);\n\t\trtw_warn_on(1);\n\t}\n\n\tif (*req_bw > *g_bw) {\n\t\t*g_bw = *req_bw;\n\t\t*g_offset = *req_offset;\n\t}\n}\n\n/**\n * rtw_get_p2p_merged_len - Get merged ie length from muitiple p2p ies.\n * @in_ie: Pointer of the first p2p ie\n * @in_len: Total len of muiltiple p2p ies\n * Returns: Length of merged p2p ie length\n */\nu32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len)\n{\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\tu8 OUI[4] = { 0x50, 0x6f, 0x9a, 0x09 };\n\tint i = 0;\n\tint len = 0;\n\n\twhile (i < in_len) {\n\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(in_ie + i);\n\n\t\tif (pIE->ElementID == _VENDOR_SPECIFIC_IE_ && _rtw_memcmp(pIE->data, OUI, 4)) {\n\t\t\tlen += pIE->Length - 4; /* 4 is P2P OUI length, don't count it in this loop */\n\t\t}\n\n\t\ti += (pIE->Length + 2);\n\t}\n\n\treturn len + 4;\t/* Append P2P OUI length at last. */\n}\n\n/**\n * rtw_p2p_merge_ies - Merge muitiple p2p ies into one\n * @in_ie: Pointer of the first p2p ie\n * @in_len: Total len of muiltiple p2p ies\n * @merge_ie: Pointer of merged ie\n * Returns: Length of merged p2p ie\n */\nint rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie)\n{\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\tu8 len = 0;\n\tu8 OUI[4] = { 0x50, 0x6f, 0x9a, 0x09 };\n\tu8 ELOUI[6] = { 0xDD, 0x00, 0x50, 0x6f, 0x9a, 0x09 };\t/* EID;Len;OUI, Len would copy at the end of function */\n\tint i = 0;\n\n\tif (merge_ie != NULL) {\n\t\t/* Set first P2P OUI */\n\t\t_rtw_memcpy(merge_ie, ELOUI, 6);\n\t\tmerge_ie += 6;\n\n\t\twhile (i < in_len) {\n\t\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(in_ie + i);\n\n\t\t\t/* Take out the rest of P2P OUIs */\n\t\t\tif (pIE->ElementID == _VENDOR_SPECIFIC_IE_ && _rtw_memcmp(pIE->data, OUI, 4)) {\n\t\t\t\t_rtw_memcpy(merge_ie, pIE->data + 4, pIE->Length - 4);\n\t\t\t\tlen += pIE->Length - 4;\n\t\t\t\tmerge_ie += pIE->Length - 4;\n\t\t\t}\n\n\t\t\ti += (pIE->Length + 2);\n\t\t}\n\n\t\treturn len + 4;\t/* 4 is for P2P OUI */\n\n\t}\n\n\treturn 0;\n}\n\nvoid dump_p2p_ie(void *sel, const u8 *ie, u32 ie_len)\n{\n\tconst u8 *pos = ie;\n\tu8 id;\n\tu16 len;\n\n\tconst u8 *p2p_ie;\n\tuint p2p_ielen;\n\n\tp2p_ie = rtw_get_p2p_ie(ie, ie_len, NULL, &p2p_ielen);\n\tif (p2p_ie != ie || p2p_ielen == 0)\n\t\treturn;\n\n\tpos += 6;\n\twhile (pos - ie + 3 <= ie_len) {\n\t\tid = *pos;\n\t\tlen = RTW_GET_LE16(pos + 1);\n\n\t\tRTW_PRINT_SEL(sel, \"%s ID:%u, LEN:%u%s\\n\", __func__, id, len\n\t\t\t, ((pos - ie + 3 + len) <= ie_len) ? \"\" : \"(exceed ie_len)\");\n\n\t\tpos += (3 + len);\n\t}\n}\n\n/**\n * rtw_get_p2p_ie - Search P2P IE from a series of IEs\n * @in_ie: Address of IEs to search\n * @in_len: Length limit from in_ie\n * @p2p_ie: If not NULL and P2P IE is found, P2P IE will be copied to the buf starting from p2p_ie\n * @p2p_ielen: If not NULL and P2P IE is found, will set to the length of the entire P2P IE\n *\n * Returns: The address of the P2P IE found, or NULL\n */\nu8 *rtw_get_p2p_ie(const u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen)\n{\n\tuint cnt;\n\tconst u8 *p2p_ie_ptr = NULL;\n\tu8 eid, p2p_oui[4] = {0x50, 0x6F, 0x9A, 0x09};\n\n\tif (p2p_ielen)\n\t\t*p2p_ielen = 0;\n\n\tif (!in_ie || in_len < 0) {\n\t\trtw_warn_on(1);\n\t\treturn (u8 *)p2p_ie_ptr;\n\t}\n\n\tif (in_len <= 0)\n\t\treturn (u8 *)p2p_ie_ptr;\n\n\tcnt = 0;\n\n\twhile (cnt + 1 + 4 < in_len) {\n\t\teid = in_ie[cnt];\n\n\t\tif (cnt + 1 + 4 >= MAX_IE_SZ) {\n\t\t\trtw_warn_on(1);\n\t\t\treturn NULL;\n\t\t}\n\n\t\tif (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], p2p_oui, 4) == _TRUE) {\n\t\t\tp2p_ie_ptr = in_ie + cnt;\n\n\t\t\tif (p2p_ie)\n\t\t\t\t_rtw_memcpy(p2p_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);\n\n\t\t\tif (p2p_ielen)\n\t\t\t\t*p2p_ielen = in_ie[cnt + 1] + 2;\n\n\t\t\tbreak;\n\t\t} else\n\t\t\tcnt += in_ie[cnt + 1] + 2;\n\n\t}\n\n\treturn (u8 *)p2p_ie_ptr;\n}\n\n/**\n * rtw_get_p2p_attr - Search a specific P2P attribute from a given P2P IE\n * @p2p_ie: Address of P2P IE to search\n * @p2p_ielen: Length limit from p2p_ie\n * @target_attr_id: The attribute ID of P2P attribute to search\n * @buf_attr: If not NULL and the P2P attribute is found, P2P attribute will be copied to the buf starting from buf_attr\n * @len_attr: If not NULL and the P2P attribute is found, will set to the length of the entire P2P attribute\n *\n * Returns: the address of the specific WPS attribute found, or NULL\n */\nu8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id , u8 *buf_attr, u32 *len_attr)\n{\n\tu8 *attr_ptr = NULL;\n\tu8 *target_attr_ptr = NULL;\n\tu8 p2p_oui[4] = {0x50, 0x6F, 0x9A, 0x09};\n\n\tif (len_attr)\n\t\t*len_attr = 0;\n\n\tif (!p2p_ie\n\t    || p2p_ielen <= 6\n\t    || (p2p_ie[0] != WLAN_EID_VENDOR_SPECIFIC)\n\t    || (_rtw_memcmp(p2p_ie + 2, p2p_oui, 4) != _TRUE))\n\t\treturn attr_ptr;\n\n\t/* 6 = 1(Element ID) + 1(Length) + 3 (OUI) + 1(OUI Type) */\n\tattr_ptr = p2p_ie + 6; /* goto first attr */\n\n\twhile ((attr_ptr - p2p_ie + 3) <= p2p_ielen) {\n\t\t/* 3 = 1(Attribute ID) + 2(Length) */\n\t\tu8 attr_id = *attr_ptr;\n\t\tu16 attr_data_len = RTW_GET_LE16(attr_ptr + 1);\n\t\tu16 attr_len = attr_data_len + 3;\n\n\t\tif (0)\n\t\t\tRTW_INFO(\"%s attr_ptr:%p, id:%u, length:%u\\n\", __func__, attr_ptr, attr_id, attr_data_len);\n\n\t\tif ((attr_ptr - p2p_ie + attr_len) > p2p_ielen)\n\t\t\tbreak;\n\n\t\tif (attr_id == target_attr_id) {\n\t\t\ttarget_attr_ptr = attr_ptr;\n\n\t\t\tif (buf_attr)\n\t\t\t\t_rtw_memcpy(buf_attr, attr_ptr, attr_len);\n\n\t\t\tif (len_attr)\n\t\t\t\t*len_attr = attr_len;\n\n\t\t\tbreak;\n\t\t} else\n\t\t\tattr_ptr += attr_len;\n\t}\n\n\treturn target_attr_ptr;\n}\n\n/**\n * rtw_get_p2p_attr_content - Search a specific P2P attribute content from a given P2P IE\n * @p2p_ie: Address of P2P IE to search\n * @p2p_ielen: Length limit from p2p_ie\n * @target_attr_id: The attribute ID of P2P attribute to search\n * @buf_content: If not NULL and the P2P attribute is found, P2P attribute content will be copied to the buf starting from buf_content\n * @len_content: If not NULL and the P2P attribute is found, will set to the length of the P2P attribute content\n *\n * Returns: the address of the specific P2P attribute content found, or NULL\n */\nu8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id , u8 *buf_content, uint *len_content)\n{\n\tu8 *attr_ptr;\n\tu32 attr_len;\n\n\tif (len_content)\n\t\t*len_content = 0;\n\n\tattr_ptr = rtw_get_p2p_attr(p2p_ie, p2p_ielen, target_attr_id, NULL, &attr_len);\n\n\tif (attr_ptr && attr_len) {\n\t\tif (buf_content)\n\t\t\t_rtw_memcpy(buf_content, attr_ptr + 3, attr_len - 3);\n\n\t\tif (len_content)\n\t\t\t*len_content = attr_len - 3;\n\n\t\treturn attr_ptr + 3;\n\t}\n\n\treturn NULL;\n}\n\nu32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr)\n{\n\tu32 a_len;\n\n\t*pbuf = attr_id;\n\n\t/* *(u16*)(pbuf + 1) = cpu_to_le16(attr_len); */\n\tRTW_PUT_LE16(pbuf + 1, attr_len);\n\n\tif (pdata_attr)\n\t\t_rtw_memcpy(pbuf + 3, pdata_attr, attr_len);\n\n\ta_len = attr_len + 3;\n\n\treturn a_len;\n}\n\nuint rtw_del_p2p_ie(u8 *ies, uint ies_len_ori, const char *msg)\n{\n#define DBG_DEL_P2P_IE 0\n\n\tu8 *target_ie;\n\tu32 target_ie_len;\n\tuint ies_len = ies_len_ori;\n\tint index = 0;\n\n\twhile (1) {\n\t\ttarget_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &target_ie_len);\n\t\tif (target_ie && target_ie_len) {\n\t\t\tu8 *next_ie = target_ie + target_ie_len;\n\t\t\tuint remain_len = ies_len - (next_ie - ies);\n\n\t\t\tif (DBG_DEL_P2P_IE && msg) {\n\t\t\t\tRTW_INFO(\"%s %d before\\n\", __func__, index);\n\t\t\t\tdump_ies(RTW_DBGDUMP, ies, ies_len);\n\n\t\t\t\tRTW_INFO(\"ies:%p, ies_len:%u\\n\", ies, ies_len);\n\t\t\t\tRTW_INFO(\"target_ie:%p, target_ie_len:%u\\n\", target_ie, target_ie_len);\n\t\t\t\tRTW_INFO(\"next_ie:%p, remain_len:%u\\n\", next_ie, remain_len);\n\t\t\t}\n\n\t\t\t_rtw_memmove(target_ie, next_ie, remain_len);\n\t\t\t_rtw_memset(target_ie + remain_len, 0, target_ie_len);\n\t\t\ties_len -= target_ie_len;\n\n\t\t\tif (DBG_DEL_P2P_IE && msg) {\n\t\t\t\tRTW_INFO(\"%s %d after\\n\", __func__, index);\n\t\t\t\tdump_ies(RTW_DBGDUMP, ies, ies_len);\n\t\t\t}\n\n\t\t\tindex++;\n\t\t} else\n\t\t\tbreak;\n\t}\n\n\treturn ies_len;\n}\n\nuint rtw_del_p2p_attr(u8 *ie, uint ielen_ori, u8 attr_id)\n{\n#define DBG_DEL_P2P_ATTR 0\n\n\tu8 *target_attr;\n\tu32 target_attr_len;\n\tuint ielen = ielen_ori;\n\tint index = 0;\n\n\twhile (1) {\n\t\ttarget_attr = rtw_get_p2p_attr(ie, ielen, attr_id, NULL, &target_attr_len);\n\t\tif (target_attr && target_attr_len) {\n\t\t\tu8 *next_attr = target_attr + target_attr_len;\n\t\t\tuint remain_len = ielen - (next_attr - ie);\n\n\t\t\tif (DBG_DEL_P2P_ATTR) {\n\t\t\t\tRTW_INFO(\"%s %d before\\n\", __func__, index);\n\t\t\t\tdump_ies(RTW_DBGDUMP, ie, ielen);\n\n\t\t\t\tRTW_INFO(\"ie:%p, ielen:%u\\n\", ie, ielen);\n\t\t\t\tRTW_INFO(\"target_attr:%p, target_attr_len:%u\\n\", target_attr, target_attr_len);\n\t\t\t\tRTW_INFO(\"next_attr:%p, remain_len:%u\\n\", next_attr, remain_len);\n\t\t\t}\n\n\t\t\t_rtw_memmove(target_attr, next_attr, remain_len);\n\t\t\t_rtw_memset(target_attr + remain_len, 0, target_attr_len);\n\t\t\t*(ie + 1) -= target_attr_len;\n\t\t\tielen -= target_attr_len;\n\n\t\t\tif (DBG_DEL_P2P_ATTR) {\n\t\t\t\tRTW_INFO(\"%s %d after\\n\", __func__, index);\n\t\t\t\tdump_ies(RTW_DBGDUMP, ie, ielen);\n\t\t\t}\n\n\t\t\tindex++;\n\t\t} else\n\t\t\tbreak;\n\t}\n\n\treturn ielen;\n}\n\ninline u8 *rtw_bss_ex_get_p2p_ie(WLAN_BSSID_EX *bss_ex, u8 *p2p_ie, uint *p2p_ielen)\n{\n\treturn rtw_get_p2p_ie(BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex), p2p_ie, p2p_ielen);\n}\n\nvoid rtw_bss_ex_del_p2p_ie(WLAN_BSSID_EX *bss_ex)\n{\n#define DBG_BSS_EX_DEL_P2P_IE 0\n\n\tu8 *ies = BSS_EX_TLV_IES(bss_ex);\n\tuint ies_len_ori = BSS_EX_TLV_IES_LEN(bss_ex);\n\tuint ies_len;\n\n\ties_len = rtw_del_p2p_ie(ies, ies_len_ori, DBG_BSS_EX_DEL_P2P_IE ? __func__ : NULL);\n\tbss_ex->IELength -= ies_len_ori - ies_len;\n}\n\nvoid rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id)\n{\n#define DBG_BSS_EX_DEL_P2P_ATTR 0\n\n\tu8 *ies = BSS_EX_TLV_IES(bss_ex);\n\tuint ies_len = BSS_EX_TLV_IES_LEN(bss_ex);\n\n\tu8 *ie;\n\tuint ie_len, ie_len_ori;\n\n\tint index = 0;\n\n\twhile (1) {\n\t\tie = rtw_get_p2p_ie(ies, ies_len, NULL, &ie_len_ori);\n\t\tif (ie) {\n\t\t\tu8 *next_ie_ori = ie + ie_len_ori;\n\t\t\tuint remain_len = bss_ex->IELength - (next_ie_ori - bss_ex->IEs);\n\t\t\tu8 has_target_attr = 0;\n\n\t\t\tif (DBG_BSS_EX_DEL_P2P_ATTR) {\n\t\t\t\tif (rtw_get_p2p_attr(ie, ie_len_ori, attr_id, NULL, NULL)) {\n\t\t\t\t\tRTW_INFO(\"%s %d before\\n\", __func__, index);\n\t\t\t\t\tdump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex));\n\n\t\t\t\t\tRTW_INFO(\"ies:%p, ies_len:%u\\n\", ies, ies_len);\n\t\t\t\t\tRTW_INFO(\"ie:%p, ie_len_ori:%u\\n\", ie, ie_len_ori);\n\t\t\t\t\tRTW_INFO(\"next_ie_ori:%p, remain_len:%u\\n\", next_ie_ori, remain_len);\n\t\t\t\t\thas_target_attr = 1;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tie_len = rtw_del_p2p_attr(ie, ie_len_ori, attr_id);\n\t\t\tif (ie_len != ie_len_ori) {\n\t\t\t\tu8 *next_ie = ie + ie_len;\n\n\t\t\t\t_rtw_memmove(next_ie, next_ie_ori, remain_len);\n\t\t\t\t_rtw_memset(next_ie + remain_len, 0, ie_len_ori - ie_len);\n\t\t\t\tbss_ex->IELength -= ie_len_ori - ie_len;\n\n\t\t\t\ties = next_ie;\n\t\t\t} else\n\t\t\t\ties = next_ie_ori;\n\n\t\t\tif (DBG_BSS_EX_DEL_P2P_ATTR) {\n\t\t\t\tif (has_target_attr) {\n\t\t\t\t\tRTW_INFO(\"%s %d after\\n\", __func__, index);\n\t\t\t\t\tdump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex));\n\t\t\t\t}\n\t\t\t}\n\n\t\t\ties_len = remain_len;\n\n\t\t\tindex++;\n\t\t} else\n\t\t\tbreak;\n\t}\n}\n\nvoid dump_wfd_ie(void *sel, const u8 *ie, u32 ie_len)\n{\n\tconst u8 *pos = ie;\n\tu8 id;\n\tu16 len;\n\n\tconst u8 *wfd_ie;\n\tuint wfd_ielen;\n\n\twfd_ie = rtw_get_wfd_ie(ie, ie_len, NULL, &wfd_ielen);\n\tif (wfd_ie != ie || wfd_ielen == 0)\n\t\treturn;\n\n\tpos += 6;\n\twhile (pos - ie + 3 <= ie_len) {\n\t\tid = *pos;\n\t\tlen = RTW_GET_BE16(pos + 1);\n\n\t\tRTW_PRINT_SEL(sel, \"%s ID:%u, LEN:%u%s\\n\", __func__, id, len\n\t\t\t, ((pos - ie + 3 + len) <= ie_len) ? \"\" : \"(exceed ie_len)\");\n\n\t\tpos += (3 + len);\n\t}\n}\n\n/**\n * rtw_get_wfd_ie - Search WFD IE from a series of IEs\n * @in_ie: Address of IEs to search\n * @in_len: Length limit from in_ie\n * @wfd_ie: If not NULL and WFD IE is found, WFD IE will be copied to the buf starting from wfd_ie\n * @wfd_ielen: If not NULL and WFD IE is found, will set to the length of the entire WFD IE\n *\n * Returns: The address of the P2P IE found, or NULL\n */\nu8 *rtw_get_wfd_ie(const u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen)\n{\n\tuint cnt;\n\tconst u8 *wfd_ie_ptr = NULL;\n\tu8 eid, wfd_oui[4] = {0x50, 0x6F, 0x9A, 0x0A};\n\n\tif (wfd_ielen)\n\t\t*wfd_ielen = 0;\n\n\tif (!in_ie || in_len < 0) {\n\t\trtw_warn_on(1);\n\t\treturn (u8 *)wfd_ie_ptr;\n\t}\n\n\tif (in_len <= 0)\n\t\treturn (u8 *)wfd_ie_ptr;\n\n\tcnt = 0;\n\n\twhile (cnt + 1 + 4 < in_len) {\n\t\teid = in_ie[cnt];\n\n\t\tif (cnt + 1 + 4 >= MAX_IE_SZ) {\n\t\t\trtw_warn_on(1);\n\t\t\treturn NULL;\n\t\t}\n\n\t\tif (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], wfd_oui, 4) == _TRUE) {\n\t\t\twfd_ie_ptr = in_ie + cnt;\n\n\t\t\tif (wfd_ie)\n\t\t\t\t_rtw_memcpy(wfd_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);\n\n\t\t\tif (wfd_ielen)\n\t\t\t\t*wfd_ielen = in_ie[cnt + 1] + 2;\n\n\t\t\tbreak;\n\t\t} else\n\t\t\tcnt += in_ie[cnt + 1] + 2;\n\n\t}\n\n\treturn (u8 *)wfd_ie_ptr;\n}\n\n/**\n * rtw_get_wfd_attr - Search a specific WFD attribute from a given WFD IE\n * @wfd_ie: Address of WFD IE to search\n * @wfd_ielen: Length limit from wfd_ie\n * @target_attr_id: The attribute ID of WFD attribute to search\n * @buf_attr: If not NULL and the WFD attribute is found, WFD attribute will be copied to the buf starting from buf_attr\n * @len_attr: If not NULL and the WFD attribute is found, will set to the length of the entire WFD attribute\n *\n * Returns: the address of the specific WPS attribute found, or NULL\n */\nu8 *rtw_get_wfd_attr(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr)\n{\n\tu8 *attr_ptr = NULL;\n\tu8 *target_attr_ptr = NULL;\n\tu8 wfd_oui[4] = {0x50, 0x6F, 0x9A, 0x0A};\n\n\tif (len_attr)\n\t\t*len_attr = 0;\n\n\tif (!wfd_ie\n\t    || wfd_ielen <= 6\n\t    || (wfd_ie[0] != WLAN_EID_VENDOR_SPECIFIC)\n\t    || (_rtw_memcmp(wfd_ie + 2, wfd_oui, 4) != _TRUE))\n\t\treturn attr_ptr;\n\n\t/* 6 = 1(Element ID) + 1(Length) + 3 (OUI) + 1(OUI Type) */\n\tattr_ptr = wfd_ie + 6; /* goto first attr */\n\n\twhile ((attr_ptr - wfd_ie + 3) <= wfd_ielen) {\n\t\t/* 3 = 1(Attribute ID) + 2(Length) */\n\t\tu8 attr_id = *attr_ptr;\n\t\tu16 attr_data_len = RTW_GET_BE16(attr_ptr + 1);\n\t\tu16 attr_len = attr_data_len + 3;\n\n\t\tif (0)\n\t\t\tRTW_INFO(\"%s attr_ptr:%p, id:%u, length:%u\\n\", __func__, attr_ptr, attr_id, attr_data_len);\n\n\t\tif ((attr_ptr - wfd_ie + attr_len) > wfd_ielen)\n\t\t\tbreak;\n\n\t\tif (attr_id == target_attr_id) {\n\t\t\ttarget_attr_ptr = attr_ptr;\n\n\t\t\tif (buf_attr)\n\t\t\t\t_rtw_memcpy(buf_attr, attr_ptr, attr_len);\n\n\t\t\tif (len_attr)\n\t\t\t\t*len_attr = attr_len;\n\n\t\t\tbreak;\n\t\t} else\n\t\t\tattr_ptr += attr_len;\n\t}\n\n\treturn target_attr_ptr;\n}\n\n/**\n * rtw_get_wfd_attr_content - Search a specific WFD attribute content from a given WFD IE\n * @wfd_ie: Address of WFD IE to search\n * @wfd_ielen: Length limit from wfd_ie\n * @target_attr_id: The attribute ID of WFD attribute to search\n * @buf_content: If not NULL and the WFD attribute is found, WFD attribute content will be copied to the buf starting from buf_content\n * @len_content: If not NULL and the WFD attribute is found, will set to the length of the WFD attribute content\n *\n * Returns: the address of the specific WFD attribute content found, or NULL\n */\nu8 *rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content)\n{\n\tu8 *attr_ptr;\n\tu32 attr_len;\n\n\tif (len_content)\n\t\t*len_content = 0;\n\n\tattr_ptr = rtw_get_wfd_attr(wfd_ie, wfd_ielen, target_attr_id, NULL, &attr_len);\n\n\tif (attr_ptr && attr_len) {\n\t\tif (buf_content)\n\t\t\t_rtw_memcpy(buf_content, attr_ptr + 3, attr_len - 3);\n\n\t\tif (len_content)\n\t\t\t*len_content = attr_len - 3;\n\n\t\treturn attr_ptr + 3;\n\t}\n\n\treturn NULL;\n}\n\nuint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg)\n{\n#define DBG_DEL_WFD_IE 0\n\n\tu8 *target_ie;\n\tu32 target_ie_len;\n\tuint ies_len = ies_len_ori;\n\tint index = 0;\n\n\twhile (1) {\n\t\ttarget_ie = rtw_get_wfd_ie(ies, ies_len, NULL, &target_ie_len);\n\t\tif (target_ie && target_ie_len) {\n\t\t\tu8 *next_ie = target_ie + target_ie_len;\n\t\t\tuint remain_len = ies_len - (next_ie - ies);\n\n\t\t\tif (DBG_DEL_WFD_IE && msg) {\n\t\t\t\tRTW_INFO(\"%s %d before\\n\", __func__, index);\n\t\t\t\tdump_ies(RTW_DBGDUMP, ies, ies_len);\n\n\t\t\t\tRTW_INFO(\"ies:%p, ies_len:%u\\n\", ies, ies_len);\n\t\t\t\tRTW_INFO(\"target_ie:%p, target_ie_len:%u\\n\", target_ie, target_ie_len);\n\t\t\t\tRTW_INFO(\"next_ie:%p, remain_len:%u\\n\", next_ie, remain_len);\n\t\t\t}\n\n\t\t\t_rtw_memmove(target_ie, next_ie, remain_len);\n\t\t\t_rtw_memset(target_ie + remain_len, 0, target_ie_len);\n\t\t\ties_len -= target_ie_len;\n\n\t\t\tif (DBG_DEL_WFD_IE && msg) {\n\t\t\t\tRTW_INFO(\"%s %d after\\n\", __func__, index);\n\t\t\t\tdump_ies(RTW_DBGDUMP, ies, ies_len);\n\t\t\t}\n\n\t\t\tindex++;\n\t\t} else\n\t\t\tbreak;\n\t}\n\n\treturn ies_len;\n}\n\nuint rtw_del_wfd_attr(u8 *ie, uint ielen_ori, u8 attr_id)\n{\n#define DBG_DEL_WFD_ATTR 0\n\n\tu8 *target_attr;\n\tu32 target_attr_len;\n\tuint ielen = ielen_ori;\n\tint index = 0;\n\n\twhile (1) {\n\t\ttarget_attr = rtw_get_wfd_attr(ie, ielen, attr_id, NULL, &target_attr_len);\n\t\tif (target_attr && target_attr_len) {\n\t\t\tu8 *next_attr = target_attr + target_attr_len;\n\t\t\tuint remain_len = ielen - (next_attr - ie);\n\n\t\t\tif (DBG_DEL_WFD_ATTR) {\n\t\t\t\tRTW_INFO(\"%s %d before\\n\", __func__, index);\n\t\t\t\tdump_ies(RTW_DBGDUMP, ie, ielen);\n\n\t\t\t\tRTW_INFO(\"ie:%p, ielen:%u\\n\", ie, ielen);\n\t\t\t\tRTW_INFO(\"target_attr:%p, target_attr_len:%u\\n\", target_attr, target_attr_len);\n\t\t\t\tRTW_INFO(\"next_attr:%p, remain_len:%u\\n\", next_attr, remain_len);\n\t\t\t}\n\n\t\t\t_rtw_memmove(target_attr, next_attr, remain_len);\n\t\t\t_rtw_memset(target_attr + remain_len, 0, target_attr_len);\n\t\t\t*(ie + 1) -= target_attr_len;\n\t\t\tielen -= target_attr_len;\n\n\t\t\tif (DBG_DEL_WFD_ATTR) {\n\t\t\t\tRTW_INFO(\"%s %d after\\n\", __func__, index);\n\t\t\t\tdump_ies(RTW_DBGDUMP, ie, ielen);\n\t\t\t}\n\n\t\t\tindex++;\n\t\t} else\n\t\t\tbreak;\n\t}\n\n\treturn ielen;\n}\n\ninline u8 *rtw_bss_ex_get_wfd_ie(WLAN_BSSID_EX *bss_ex, u8 *wfd_ie, uint *wfd_ielen)\n{\n\treturn rtw_get_wfd_ie(BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex), wfd_ie, wfd_ielen);\n}\n\nvoid rtw_bss_ex_del_wfd_ie(WLAN_BSSID_EX *bss_ex)\n{\n#define DBG_BSS_EX_DEL_WFD_IE 0\n\tu8 *ies = BSS_EX_TLV_IES(bss_ex);\n\tuint ies_len_ori = BSS_EX_TLV_IES_LEN(bss_ex);\n\tuint ies_len;\n\n\ties_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_BSS_EX_DEL_WFD_IE ? __func__ : NULL);\n\tbss_ex->IELength -= ies_len_ori - ies_len;\n}\n\nvoid rtw_bss_ex_del_wfd_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id)\n{\n#define DBG_BSS_EX_DEL_WFD_ATTR 0\n\n\tu8 *ies = BSS_EX_TLV_IES(bss_ex);\n\tuint ies_len = BSS_EX_TLV_IES_LEN(bss_ex);\n\n\tu8 *ie;\n\tuint ie_len, ie_len_ori;\n\n\tint index = 0;\n\n\twhile (1) {\n\t\tie = rtw_get_wfd_ie(ies, ies_len, NULL, &ie_len_ori);\n\t\tif (ie) {\n\t\t\tu8 *next_ie_ori = ie + ie_len_ori;\n\t\t\tuint remain_len = bss_ex->IELength - (next_ie_ori - bss_ex->IEs);\n\t\t\tu8 has_target_attr = 0;\n\n\t\t\tif (DBG_BSS_EX_DEL_WFD_ATTR) {\n\t\t\t\tif (rtw_get_wfd_attr(ie, ie_len_ori, attr_id, NULL, NULL)) {\n\t\t\t\t\tRTW_INFO(\"%s %d before\\n\", __func__, index);\n\t\t\t\t\tdump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex));\n\n\t\t\t\t\tRTW_INFO(\"ies:%p, ies_len:%u\\n\", ies, ies_len);\n\t\t\t\t\tRTW_INFO(\"ie:%p, ie_len_ori:%u\\n\", ie, ie_len_ori);\n\t\t\t\t\tRTW_INFO(\"next_ie_ori:%p, remain_len:%u\\n\", next_ie_ori, remain_len);\n\t\t\t\t\thas_target_attr = 1;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tie_len = rtw_del_wfd_attr(ie, ie_len_ori, attr_id);\n\t\t\tif (ie_len != ie_len_ori) {\n\t\t\t\tu8 *next_ie = ie + ie_len;\n\n\t\t\t\t_rtw_memmove(next_ie, next_ie_ori, remain_len);\n\t\t\t\t_rtw_memset(next_ie + remain_len, 0, ie_len_ori - ie_len);\n\t\t\t\tbss_ex->IELength -= ie_len_ori - ie_len;\n\n\t\t\t\ties = next_ie;\n\t\t\t} else\n\t\t\t\ties = next_ie_ori;\n\n\t\t\tif (DBG_BSS_EX_DEL_WFD_ATTR) {\n\t\t\t\tif (has_target_attr) {\n\t\t\t\t\tRTW_INFO(\"%s %d after\\n\", __func__, index);\n\t\t\t\t\tdump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex));\n\t\t\t\t}\n\t\t\t}\n\n\t\t\ties_len = remain_len;\n\n\t\t\tindex++;\n\t\t} else\n\t\t\tbreak;\n\t}\n}\n\n/* Baron adds to avoid FreeBSD warning */\nint ieee80211_is_empty_essid(const char *essid, int essid_len)\n{\n\t/* Single white space is for Linksys APs */\n\tif (essid_len == 1 && essid[0] == ' ')\n\t\treturn 1;\n\n\t/* Otherwise, if the entire essid is 0, we assume it is hidden */\n\twhile (essid_len) {\n\t\tessid_len--;\n\t\tif (essid[essid_len] != '\\0')\n\t\t\treturn 0;\n\t}\n\n\treturn 1;\n}\n\nint ieee80211_get_hdrlen(u16 fc)\n{\n\tint hdrlen = 24;\n\n\tswitch (WLAN_FC_GET_TYPE(fc)) {\n\tcase RTW_IEEE80211_FTYPE_DATA:\n\t\tif (fc & RTW_IEEE80211_STYPE_QOS_DATA)\n\t\t\thdrlen += 2;\n\t\tif ((fc & RTW_IEEE80211_FCTL_FROMDS) && (fc & RTW_IEEE80211_FCTL_TODS))\n\t\t\thdrlen += 6; /* Addr4 */\n\t\tbreak;\n\tcase RTW_IEEE80211_FTYPE_CTL:\n\t\tswitch (WLAN_FC_GET_STYPE(fc)) {\n\t\tcase RTW_IEEE80211_STYPE_CTS:\n\t\tcase RTW_IEEE80211_STYPE_ACK:\n\t\t\thdrlen = 10;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\thdrlen = 16;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\t}\n\n\treturn hdrlen;\n}\n\nu8\trtw_ht_mcsset_to_nss(u8 *supp_mcs_set)\n{\n\tu8 nss = 1;\n\n\tif (supp_mcs_set[3])\n\t\tnss = 4;\n\telse if (supp_mcs_set[2])\n\t\tnss = 3;\n\telse if (supp_mcs_set[1])\n\t\tnss = 2;\n\telse if (supp_mcs_set[0])\n\t\tnss = 1;\n\telse\n\t\tRTW_INFO(\"%s,%d, warning! supp_mcs_set is zero\\n\", __func__, __LINE__);\n\t/* RTW_INFO(\"%s HT: %dSS\\n\", __FUNCTION__, nss); */\n\treturn nss;\n}\n\nu32\trtw_ht_mcs_set_to_bitmap(u8 *mcs_set, u8 nss)\n{\n\tu8 i;\n\tu32 bitmap = 0;\n\n\tfor (i = 0; i < nss; i++)\n\t\tbitmap |= mcs_set[i] << (i * 8);\n\n\tRTW_INFO(\"ht_mcs_set=%02x %02x %02x %02x, nss=%u, bitmap=%08x\\n\"\n\t\t, mcs_set[0], mcs_set[1], mcs_set[2], mcs_set[3], nss, bitmap);\n\n\treturn bitmap;\n}\n\n/* show MCS rate, unit: 100Kbps */\nu16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI, unsigned char *MCS_rate)\n{\n\tu16 max_rate = 0;\n\n\tif (MCS_rate[3]) {\n\t\tif (MCS_rate[3] & BIT(7))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 6000 : 5400) : ((short_GI) ? 2889 : 2600);\n\t\telse if (MCS_rate[3] & BIT(6))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 5400 : 4860) : ((short_GI) ? 2600 : 2340);\n\t\telse if (MCS_rate[3] & BIT(5))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 4800 : 4320) : ((short_GI) ? 2311 : 2080);\n\t\telse if (MCS_rate[3] & BIT(4))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 3600 : 3240) : ((short_GI) ? 1733 : 1560);\n\t\telse if (MCS_rate[3] & BIT(3))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 2400 : 2160) : ((short_GI) ? 1156 : 1040);\n\t\telse if (MCS_rate[3] & BIT(2))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 1800 : 1620) : ((short_GI) ? 867 : 780);\n\t\telse if (MCS_rate[3] & BIT(1))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 1200 : 1080) : ((short_GI) ? 578 : 520);\n\t\telse if (MCS_rate[3] & BIT(0))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 600 : 540) : ((short_GI) ? 289 : 260);\n\t} else if (MCS_rate[2]) {\n\t\tif (MCS_rate[2] & BIT(7))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 4500 : 4050) : ((short_GI) ? 2167 : 1950);\n\t\telse if (MCS_rate[2] & BIT(6))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 4050 : 3645) : ((short_GI) ? 1950 : 1750);\n\t\telse if (MCS_rate[2] & BIT(5))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 3600 : 3240) : ((short_GI) ? 1733 : 1560);\n\t\telse if (MCS_rate[2] & BIT(4))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 2700 : 2430) : ((short_GI) ? 1300 : 1170);\n\t\telse if (MCS_rate[2] & BIT(3))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 1800 : 1620) : ((short_GI) ? 867 : 780);\n\t\telse if (MCS_rate[2] & BIT(2))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 1350 : 1215) : ((short_GI) ? 650 : 585);\n\t\telse if (MCS_rate[2] & BIT(1))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 900 : 810) : ((short_GI) ? 433 : 390);\n\t\telse if (MCS_rate[2] & BIT(0))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 450 : 405) : ((short_GI) ? 217 : 195);\n\t} else if (MCS_rate[1]) {\n\t\tif (MCS_rate[1] & BIT(7))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 3000 : 2700) : ((short_GI) ? 1444 : 1300);\n\t\telse if (MCS_rate[1] & BIT(6))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 2700 : 2430) : ((short_GI) ? 1300 : 1170);\n\t\telse if (MCS_rate[1] & BIT(5))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 2400 : 2160) : ((short_GI) ? 1156 : 1040);\n\t\telse if (MCS_rate[1] & BIT(4))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 1800 : 1620) : ((short_GI) ? 867 : 780);\n\t\telse if (MCS_rate[1] & BIT(3))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 1200 : 1080) : ((short_GI) ? 578 : 520);\n\t\telse if (MCS_rate[1] & BIT(2))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 900 : 810) : ((short_GI) ? 433 : 390);\n\t\telse if (MCS_rate[1] & BIT(1))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 600 : 540) : ((short_GI) ? 289 : 260);\n\t\telse if (MCS_rate[1] & BIT(0))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 300 : 270) : ((short_GI) ? 144 : 130);\n\t} else {\n\t\tif (MCS_rate[0] & BIT(7))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 1500 : 1350) : ((short_GI) ? 722 : 650);\n\t\telse if (MCS_rate[0] & BIT(6))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 1350 : 1215) : ((short_GI) ? 650 : 585);\n\t\telse if (MCS_rate[0] & BIT(5))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 1200 : 1080) : ((short_GI) ? 578 : 520);\n\t\telse if (MCS_rate[0] & BIT(4))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 900 : 810) : ((short_GI) ? 433 : 390);\n\t\telse if (MCS_rate[0] & BIT(3))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 600 : 540) : ((short_GI) ? 289 : 260);\n\t\telse if (MCS_rate[0] & BIT(2))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 450 : 405) : ((short_GI) ? 217 : 195);\n\t\telse if (MCS_rate[0] & BIT(1))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 300 : 270) : ((short_GI) ? 144 : 130);\n\t\telse if (MCS_rate[0] & BIT(0))\n\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65);\n\t}\n\n\treturn max_rate;\n}\n\nint rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8 *category, u8 *action)\n{\n\tconst u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr);\n\tu16 fc;\n\tu8 c;\n\tu8 a = ACT_PUBLIC_MAX;\n\n\tfc = le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)frame)->frame_ctl);\n\n\tif ((fc & (RTW_IEEE80211_FCTL_FTYPE | RTW_IEEE80211_FCTL_STYPE))\n\t    != (RTW_IEEE80211_FTYPE_MGMT | RTW_IEEE80211_STYPE_ACTION)\n\t   )\n\t\treturn _FALSE;\n\n\tc = frame_body[0];\n\n\tswitch (c) {\n\tcase RTW_WLAN_CATEGORY_P2P: /* vendor-specific */\n\t\tbreak;\n\tdefault:\n\t\ta = frame_body[1];\n\t}\n\n\tif (category)\n\t\t*category = c;\n\tif (action)\n\t\t*action = a;\n\n\treturn _TRUE;\n}\n\nstatic const char *_action_public_str[] = {\n\t\"ACT_PUB_BSSCOEXIST\",\n\t\"ACT_PUB_DSE_ENABLE\",\n\t\"ACT_PUB_DSE_DEENABLE\",\n\t\"ACT_PUB_DSE_REG_LOCATION\",\n\t\"ACT_PUB_EXT_CHL_SWITCH\",\n\t\"ACT_PUB_DSE_MSR_REQ\",\n\t\"ACT_PUB_DSE_MSR_RPRT\",\n\t\"ACT_PUB_MP\",\n\t\"ACT_PUB_DSE_PWR_CONSTRAINT\",\n\t\"ACT_PUB_VENDOR\",\n\t\"ACT_PUB_GAS_INITIAL_REQ\",\n\t\"ACT_PUB_GAS_INITIAL_RSP\",\n\t\"ACT_PUB_GAS_COMEBACK_REQ\",\n\t\"ACT_PUB_GAS_COMEBACK_RSP\",\n\t\"ACT_PUB_TDLS_DISCOVERY_RSP\",\n\t\"ACT_PUB_LOCATION_TRACK\",\n\t\"ACT_PUB_RSVD\",\n};\n\nconst char *action_public_str(u8 action)\n{\n\taction = (action >= ACT_PUBLIC_MAX) ? ACT_PUBLIC_MAX : action;\n\treturn _action_public_str[action];\n}\n\n"
  },
  {
    "path": "core/rtw_io.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n/*\n\nThe purpose of rtw_io.c\n\na. provides the API\n\nb. provides the protocol engine\n\nc. provides the software interface between caller and the hardware interface\n\n\nCompiler Flag Option:\n\n1. CONFIG_SDIO_HCI:\n    a. USE_SYNC_IRP:  Only sync operations are provided.\n    b. USE_ASYNC_IRP:Both sync/async operations are provided.\n\n2. CONFIG_USB_HCI:\n   a. USE_ASYNC_IRP: Both sync/async operations are provided.\n\n3. CONFIG_CFIO_HCI:\n   b. USE_SYNC_IRP: Only sync operations are provided.\n\n\nOnly sync read/rtw_write_mem operations are provided.\n\njackson@realtek.com.tw\n\n*/\n\n#define _RTW_IO_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_PLATFORM_RTL8197D)\n\t#define rtw_le16_to_cpu(val)\t\tval\n\t#define rtw_le32_to_cpu(val)\t\tval\n\t#define rtw_cpu_to_le16(val)\t\tval\n\t#define rtw_cpu_to_le32(val)\t\tval\n#else\n\t#define rtw_le16_to_cpu(val)\t\tle16_to_cpu(val)\n\t#define rtw_le32_to_cpu(val)\t\tle32_to_cpu(val)\n\t#define rtw_cpu_to_le16(val)\t\tcpu_to_le16(val)\n\t#define rtw_cpu_to_le32(val)\t\tcpu_to_le32(val)\n#endif\n\n\nu8 _rtw_read8(_adapter *adapter, u32 addr)\n{\n\tu8 r_val;\n\t/* struct\tio_queue  \t*pio_queue = (struct io_queue *)adapter->pio_queue; */\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct\tintf_hdl\t\t*pintfhdl = &(pio_priv->intf);\n\tu8(*_read8)(struct intf_hdl *pintfhdl, u32 addr);\n\t_read8 = pintfhdl->io_ops._read8;\n\n\tr_val = _read8(pintfhdl, addr);\n\treturn r_val;\n}\n\nu16 _rtw_read16(_adapter *adapter, u32 addr)\n{\n\tu16 r_val;\n\t/* struct\tio_queue  \t*pio_queue = (struct io_queue *)adapter->pio_queue; */\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct\tintf_hdl\t\t*pintfhdl = &(pio_priv->intf);\n\tu16(*_read16)(struct intf_hdl *pintfhdl, u32 addr);\n\t_read16 = pintfhdl->io_ops._read16;\n\n\tr_val = _read16(pintfhdl, addr);\n\treturn rtw_le16_to_cpu(r_val);\n}\n\nu32 _rtw_read32(_adapter *adapter, u32 addr)\n{\n\tu32 r_val;\n\t/* struct\tio_queue  \t*pio_queue = (struct io_queue *)adapter->pio_queue; */\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct\tintf_hdl\t\t*pintfhdl = &(pio_priv->intf);\n\tu32(*_read32)(struct intf_hdl *pintfhdl, u32 addr);\n\t_read32 = pintfhdl->io_ops._read32;\n\n\tr_val = _read32(pintfhdl, addr);\n\treturn rtw_le32_to_cpu(r_val);\n\n}\n\nint _rtw_write8(_adapter *adapter, u32 addr, u8 val)\n{\n\t/* struct\tio_queue  \t*pio_queue = (struct io_queue *)adapter->pio_queue; */\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct\tintf_hdl\t\t*pintfhdl = &(pio_priv->intf);\n\tint (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);\n\tint ret;\n\t_write8 = pintfhdl->io_ops._write8;\n\n\tret = _write8(pintfhdl, addr, val);\n\n\treturn RTW_STATUS_CODE(ret);\n}\nint _rtw_write16(_adapter *adapter, u32 addr, u16 val)\n{\n\t/* struct\tio_queue  \t*pio_queue = (struct io_queue *)adapter->pio_queue; */\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct\tintf_hdl\t\t*pintfhdl = &(pio_priv->intf);\n\tint (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);\n\tint ret;\n\t_write16 = pintfhdl->io_ops._write16;\n\n\tval = rtw_cpu_to_le16(val);\n\tret = _write16(pintfhdl, addr, val);\n\n\treturn RTW_STATUS_CODE(ret);\n}\nint _rtw_write32(_adapter *adapter, u32 addr, u32 val)\n{\n\t/* struct\tio_queue  \t*pio_queue = (struct io_queue *)adapter->pio_queue; */\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct\tintf_hdl\t\t*pintfhdl = &(pio_priv->intf);\n\tint (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);\n\tint ret;\n\t_write32 = pintfhdl->io_ops._write32;\n\n\tval = rtw_cpu_to_le32(val);\n\tret = _write32(pintfhdl, addr, val);\n\n\treturn RTW_STATUS_CODE(ret);\n}\n\nint _rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *pdata)\n{\n\t/* struct\tio_queue  \t*pio_queue = (struct io_queue *)adapter->pio_queue; */\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct\tintf_hdl\t*pintfhdl = (struct intf_hdl *)(&(pio_priv->intf));\n\tint (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);\n\tint ret;\n\t_writeN = pintfhdl->io_ops._writeN;\n\n\tret = _writeN(pintfhdl, addr, length, pdata);\n\n\treturn RTW_STATUS_CODE(ret);\n}\n\n#ifdef CONFIG_SDIO_HCI\nu8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr)\n{\n\tu8 r_val = 0x00;\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct intf_hdl *pintfhdl = &(pio_priv->intf);\n\tu8(*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr);\n\n\t_sd_f0_read8 = pintfhdl->io_ops._sd_f0_read8;\n\n\tif (_sd_f0_read8)\n\t\tr_val = _sd_f0_read8(pintfhdl, addr);\n\telse\n\t\tRTW_WARN(FUNC_ADPT_FMT\" _sd_f0_read8 callback is NULL\\n\", FUNC_ADPT_ARG(adapter));\n\n\treturn r_val;\n}\n\n#ifdef CONFIG_SDIO_INDIRECT_ACCESS\nu8 _rtw_sd_iread8(_adapter *adapter, u32 addr)\n{\n\tu8 r_val = 0x00;\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct intf_hdl *pintfhdl = &(pio_priv->intf);\n\tu8(*_sd_iread8)(struct intf_hdl *pintfhdl, u32 addr);\n\n\t_sd_iread8 = pintfhdl->io_ops._sd_iread8;\n\n\tif (_sd_iread8)\n\t\tr_val = _sd_iread8(pintfhdl, addr);\n\telse\n\t\tRTW_ERR(FUNC_ADPT_FMT\" _sd_iread8 callback is NULL\\n\", FUNC_ADPT_ARG(adapter));\n\n\treturn r_val;\n}\n\nu16 _rtw_sd_iread16(_adapter *adapter, u32 addr)\n{\n\tu16 r_val = 0x00;\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct intf_hdl *pintfhdl = &(pio_priv->intf);\n\tu16(*_sd_iread16)(struct intf_hdl *pintfhdl, u32 addr);\n\n\t_sd_iread16 = pintfhdl->io_ops._sd_iread16;\n\n\tif (_sd_iread16)\n\t\tr_val = _sd_iread16(pintfhdl, addr);\n\telse\n\t\tRTW_ERR(FUNC_ADPT_FMT\" _sd_iread16 callback is NULL\\n\", FUNC_ADPT_ARG(adapter));\n\n\treturn r_val;\n}\n\nu32 _rtw_sd_iread32(_adapter *adapter, u32 addr)\n{\n\tu32 r_val = 0x00;\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct intf_hdl *pintfhdl = &(pio_priv->intf);\n\tu32(*_sd_iread32)(struct intf_hdl *pintfhdl, u32 addr);\n\n\t_sd_iread32 = pintfhdl->io_ops._sd_iread32;\n\n\tif (_sd_iread32)\n\t\tr_val = _sd_iread32(pintfhdl, addr);\n\telse\n\t\tRTW_ERR(FUNC_ADPT_FMT\" _sd_iread32 callback is NULL\\n\", FUNC_ADPT_ARG(adapter));\n\n\treturn r_val;\n}\n\nint _rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val)\n{\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct intf_hdl *pintfhdl = &(pio_priv->intf);\n\tint (*_sd_iwrite8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);\n\tint ret = -1;\n\n\t_sd_iwrite8 = pintfhdl->io_ops._sd_iwrite8;\n\n\tif (_sd_iwrite8)\n\t\tret = _sd_iwrite8(pintfhdl, addr, val);\n\telse\n\t\tRTW_ERR(FUNC_ADPT_FMT\" _sd_iwrite8 callback is NULL\\n\", FUNC_ADPT_ARG(adapter));\n\n\treturn RTW_STATUS_CODE(ret);\n}\n\nint _rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val)\n{\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct intf_hdl *pintfhdl = &(pio_priv->intf);\n\tint (*_sd_iwrite16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);\n\tint ret = -1;\n\n\t_sd_iwrite16 = pintfhdl->io_ops._sd_iwrite16;\n\n\tif (_sd_iwrite16)\n\t\tret = _sd_iwrite16(pintfhdl, addr, val);\n\telse\n\t\tRTW_ERR(FUNC_ADPT_FMT\" _sd_iwrite16 callback is NULL\\n\", FUNC_ADPT_ARG(adapter));\n\n\treturn RTW_STATUS_CODE(ret);\n}\nint _rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val)\n{\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct intf_hdl *pintfhdl = &(pio_priv->intf);\n\tint (*_sd_iwrite32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);\n\tint ret = -1;\n\n\t_sd_iwrite32 = pintfhdl->io_ops._sd_iwrite32;\n\n\tif (_sd_iwrite32)\n\t\tret = _sd_iwrite32(pintfhdl, addr, val);\n\telse\n\t\tRTW_ERR(FUNC_ADPT_FMT\" _sd_iwrite32 callback is NULL\\n\", FUNC_ADPT_ARG(adapter));\n\n\treturn RTW_STATUS_CODE(ret);\n}\n\n#endif /* CONFIG_SDIO_INDIRECT_ACCESS */\n\n#endif /* CONFIG_SDIO_HCI */\n\nint _rtw_write8_async(_adapter *adapter, u32 addr, u8 val)\n{\n\t/* struct\tio_queue  \t*pio_queue = (struct io_queue *)adapter->pio_queue; */\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct\tintf_hdl\t\t*pintfhdl = &(pio_priv->intf);\n\tint (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);\n\tint ret;\n\t_write8_async = pintfhdl->io_ops._write8_async;\n\n\tret = _write8_async(pintfhdl, addr, val);\n\n\treturn RTW_STATUS_CODE(ret);\n}\nint _rtw_write16_async(_adapter *adapter, u32 addr, u16 val)\n{\n\t/* struct\tio_queue  \t*pio_queue = (struct io_queue *)adapter->pio_queue; */\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct\tintf_hdl\t\t*pintfhdl = &(pio_priv->intf);\n\tint (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val);\n\tint ret;\n\t_write16_async = pintfhdl->io_ops._write16_async;\n\tval = rtw_cpu_to_le16(val);\n\tret = _write16_async(pintfhdl, addr, val);\n\n\treturn RTW_STATUS_CODE(ret);\n}\nint _rtw_write32_async(_adapter *adapter, u32 addr, u32 val)\n{\n\t/* struct\tio_queue  \t*pio_queue = (struct io_queue *)adapter->pio_queue; */\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct\tintf_hdl\t\t*pintfhdl = &(pio_priv->intf);\n\tint (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val);\n\tint ret;\n\t_write32_async = pintfhdl->io_ops._write32_async;\n\tval = rtw_cpu_to_le32(val);\n\tret = _write32_async(pintfhdl, addr, val);\n\n\treturn RTW_STATUS_CODE(ret);\n}\n\nvoid _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)\n{\n\tvoid (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);\n\t/* struct\tio_queue  \t*pio_queue = (struct io_queue *)adapter->pio_queue; */\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct\tintf_hdl\t\t*pintfhdl = &(pio_priv->intf);\n\n\n\tif (RTW_CANNOT_RUN(adapter)) {\n\t\treturn;\n\t}\n\n\t_read_mem = pintfhdl->io_ops._read_mem;\n\n\t_read_mem(pintfhdl, addr, cnt, pmem);\n\n\n}\n\nvoid _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)\n{\n\tvoid (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);\n\t/* struct\tio_queue  \t*pio_queue = (struct io_queue *)adapter->pio_queue; */\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct\tintf_hdl\t\t*pintfhdl = &(pio_priv->intf);\n\n\n\t_write_mem = pintfhdl->io_ops._write_mem;\n\n\t_write_mem(pintfhdl, addr, cnt, pmem);\n\n\n}\n\nvoid _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)\n{\n\tu32(*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);\n\t/* struct\tio_queue  \t*pio_queue = (struct io_queue *)adapter->pio_queue; */\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct\tintf_hdl\t\t*pintfhdl = &(pio_priv->intf);\n\n\n\tif (RTW_CANNOT_RUN(adapter)) {\n\t\treturn;\n\t}\n\n\t_read_port = pintfhdl->io_ops._read_port;\n\n\t_read_port(pintfhdl, addr, cnt, pmem);\n\n\n}\n\nvoid _rtw_read_port_cancel(_adapter *adapter)\n{\n\tvoid (*_read_port_cancel)(struct intf_hdl *pintfhdl);\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct intf_hdl *pintfhdl = &(pio_priv->intf);\n\n\t_read_port_cancel = pintfhdl->io_ops._read_port_cancel;\n\n\tRTW_DISABLE_FUNC(adapter, DF_RX_BIT);\n\n\tif (_read_port_cancel)\n\t\t_read_port_cancel(pintfhdl);\n}\n\nu32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)\n{\n\tu32(*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);\n\t/* struct\tio_queue  \t*pio_queue = (struct io_queue *)adapter->pio_queue; */\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct\tintf_hdl\t\t*pintfhdl = &(pio_priv->intf);\n\tu32 ret = _SUCCESS;\n\n\n\t_write_port = pintfhdl->io_ops._write_port;\n\n\tret = _write_port(pintfhdl, addr, cnt, pmem);\n\n\n\treturn ret;\n}\n\nu32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms)\n{\n\tint ret = _SUCCESS;\n\tstruct xmit_buf *pxmitbuf = (struct xmit_buf *)pmem;\n\tstruct submit_ctx sctx;\n\n\trtw_sctx_init(&sctx, timeout_ms);\n\tpxmitbuf->sctx = &sctx;\n\n\tret = _rtw_write_port(adapter, addr, cnt, pmem);\n\n\tif (ret == _SUCCESS) {\n\t\tret = rtw_sctx_wait(&sctx, __func__);\n\n\t\tif (ret != _SUCCESS)\n\t\t\tpxmitbuf->sctx = NULL;\n\t}\n\n\treturn ret;\n}\n\nvoid _rtw_write_port_cancel(_adapter *adapter)\n{\n\tvoid (*_write_port_cancel)(struct intf_hdl *pintfhdl);\n\tstruct io_priv *pio_priv = &adapter->iopriv;\n\tstruct intf_hdl *pintfhdl = &(pio_priv->intf);\n\n\t_write_port_cancel = pintfhdl->io_ops._write_port_cancel;\n\n\tRTW_DISABLE_FUNC(adapter, DF_TX_BIT);\n\n\tif (_write_port_cancel)\n\t\t_write_port_cancel(pintfhdl);\n}\nint rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter, struct _io_ops *pops))\n{\n\tstruct io_priv\t*piopriv = &padapter->iopriv;\n\tstruct intf_hdl *pintf = &piopriv->intf;\n\n\tif (set_intf_ops == NULL)\n\t\treturn _FAIL;\n\n\tpiopriv->padapter = padapter;\n\tpintf->padapter = padapter;\n\tpintf->pintf_dev = adapter_to_dvobj(padapter);\n\n\tset_intf_ops(padapter, &pintf->io_ops);\n\n\treturn _SUCCESS;\n}\n\n/*\n* Increase and check if the continual_io_error of this @param dvobjprive is larger than MAX_CONTINUAL_IO_ERR\n* @return _TRUE:\n* @return _FALSE:\n*/\nint rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj)\n{\n\tint ret = _FALSE;\n\tint value;\n\n\tvalue = ATOMIC_INC_RETURN(&dvobj->continual_io_error);\n\tif (value > MAX_CONTINUAL_IO_ERR) {\n\t\tRTW_INFO(\"[dvobj:%p][ERROR] continual_io_error:%d > %d\\n\", dvobj, value, MAX_CONTINUAL_IO_ERR);\n\t\tret = _TRUE;\n\t} else {\n\t\t/* RTW_INFO(\"[dvobj:%p] continual_io_error:%d\\n\", dvobj, value); */\n\t}\n\treturn ret;\n}\n\n/*\n* Set the continual_io_error of this @param dvobjprive to 0\n*/\nvoid rtw_reset_continual_io_error(struct dvobj_priv *dvobj)\n{\n\tATOMIC_SET(&dvobj->continual_io_error, 0);\n}\n\n#ifdef DBG_IO\n#define RTW_IO_SNIFF_TYPE_RANGE\t0 /* specific address range is accessed */\n#define RTW_IO_SNIFF_TYPE_VALUE\t1 /* value match for sniffed range */\n\nstruct rtw_io_sniff_ent {\n\tu8 chip;\n\tu8 hci;\n\tu32 addr;\n\tu8 type;\n\tunion {\n\t\tu32 end_addr;\n\t\tstruct {\n\t\t\tu32 mask;\n\t\t\tu32 val;\n\t\t\tbool equal;\n\t\t} vm; /* value match */\n\t} u;\n\tbool trace;\n\tchar *tag;\n};\n\n#define RTW_IO_SNIFF_RANGE_ENT(_chip, _hci, _addr, _end_addr, _trace, _tag) \\\n\t{.chip = _chip, .hci = _hci, .addr = _addr, .u.end_addr = _end_addr, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_RANGE,}\n\n#define RTW_IO_SNIFF_VALUE_ENT(_chip, _hci, _addr, _mask, _val, _equal, _trace, _tag) \\\n\t{.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = _val, .u.vm.equal = _equal, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,}\n\n/* part or all sniffed range is enabled (not all 0) */\n#define RTW_IO_SNIFF_EN_ENT(_chip, _hci, _addr, _mask, _trace, _tag) \\\n\t{.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = 0, .u.vm.equal = 0, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,}\n\n/* part or all sniffed range is disabled (not all 1) */\n#define RTW_IO_SNIFF_DIS_ENT(_chip, _hci, _addr, _mask, _trace, _tag) \\\n\t{.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = 0xFFFFFFFF, .u.vm.equal = 0, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,}\n\nconst struct rtw_io_sniff_ent read_sniff[] = {\n#ifdef DBG_IO_HCI_EN_CHK\n\tRTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_SDIO, 0x02, 0x1FC, 1, \"SDIO 0x02[8:2] not all 0\"),\n\tRTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_USB, 0x02, 0x1E0, 1, \"USB 0x02[8:5] not all 0\"),\n\tRTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_PCIE, 0x02, 0x01C, 1, \"PCI 0x02[4:2] not all 0\"),\n#endif\n#ifdef DBG_IO_SNIFF_EXAMPLE\n\tRTW_IO_SNIFF_RANGE_ENT(MAX_CHIP_TYPE, 0, 0x522, 0x522, 0, \"read TXPAUSE\"),\n\tRTW_IO_SNIFF_DIS_ENT(MAX_CHIP_TYPE, 0, 0x02, 0x3, 0, \"0x02[1:0] not all 1\"),\n#endif\n};\n\nconst int read_sniff_num = sizeof(read_sniff) / sizeof(struct rtw_io_sniff_ent);\n\nconst struct rtw_io_sniff_ent write_sniff[] = {\n#ifdef DBG_IO_HCI_EN_CHK\n\tRTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_SDIO, 0x02, 0x1FC, 1, \"SDIO 0x02[8:2] not all 0\"),\n\tRTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_USB, 0x02, 0x1E0, 1, \"USB 0x02[8:5] not all 0\"),\n\tRTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_PCIE, 0x02, 0x01C, 1, \"PCI 0x02[4:2] not all 0\"),\n#endif\n#ifdef DBG_IO_8822C_1TX_PATH_EN\n\tRTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x1a04, 0xc0000000, 0x02, 1, 0, \"write tx_path_en_cck A enabled\"),\n\tRTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x1a04, 0xc0000000, 0x01, 1, 0, \"write tx_path_en_cck B enabled\"),\n\tRTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x1a04, 0xc0000000, 0x03, 1, 1, \"write tx_path_en_cck AB enabled\"),\n\tRTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x03, 0x01, 1, 0, \"write tx_path_en_ofdm_1sts A enabled\"),\n\tRTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x03, 0x02, 1, 0, \"write tx_path_en_ofdm_1sts B enabled\"),\n\tRTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x03, 0x03, 1, 1, \"write tx_path_en_ofdm_1sts AB enabled\"),\n\tRTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x30, 0x01, 1, 0, \"write tx_path_en_ofdm_2sts A enabled\"),\n\tRTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x30, 0x02, 1, 0, \"write tx_path_en_ofdm_2sts B enabled\"),\n\tRTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x30, 0x03, 1, 1, \"write tx_path_en_ofdm_2sts AB enabled\"),\n#endif\n#ifdef DBG_IO_SNIFF_EXAMPLE\n\tRTW_IO_SNIFF_RANGE_ENT(MAX_CHIP_TYPE, 0, 0x522, 0x522, 0, \"write TXPAUSE\"),\n\tRTW_IO_SNIFF_DIS_ENT(MAX_CHIP_TYPE, 0, 0x02, 0x3, 0, \"0x02[1:0] not all 1\"),\n#endif\n};\n\nconst int write_sniff_num = sizeof(write_sniff) / sizeof(struct rtw_io_sniff_ent);\n\nstatic bool match_io_sniff_ranges(_adapter *adapter\n\t, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u16 len)\n{\n\n\t/* check if IO range after sniff end address */\n\tif (addr > sniff->u.end_addr)\n\t\treturn 0;\n\n\treturn 1;\n}\n\nstatic bool match_io_sniff_value(_adapter *adapter\n\t, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val)\n{\n\tu8 sniff_len;\n\ts8 mask_shift;\n\tu32 mask;\n\ts8 value_shift;\n\tu32 value;\n\tbool ret = 0;\n\n\t/* check if IO range after sniff end address */\n\tsniff_len = 4;\n\twhile (!(sniff->u.vm.mask & (0xFF << ((sniff_len - 1) * 8)))) {\n\t\tsniff_len--;\n\t\tif (sniff_len == 0)\n\t\t\tgoto exit;\n\t}\n\tif (sniff->addr + sniff_len <= addr)\n\t\tgoto exit;\n\n\t/* align to IO addr */\n\tmask_shift = (sniff->addr - addr) * 8;\n\tvalue_shift = mask_shift + bitshift(sniff->u.vm.mask);\n\tif (mask_shift > 0)\n\t\tmask = sniff->u.vm.mask << mask_shift;\n\telse if (mask_shift < 0)\n\t\tmask = sniff->u.vm.mask >> -mask_shift;\n\telse\n\t\tmask = sniff->u.vm.mask;\n\n\tif (value_shift > 0)\n\t\tvalue = sniff->u.vm.val << value_shift;\n\telse if (mask_shift < 0)\n\t\tvalue = sniff->u.vm.val >> -value_shift;\n\telse\n\t\tvalue = sniff->u.vm.val;\n\n\tif ((sniff->u.vm.equal && (mask & val) == (mask & value))\n\t\t|| (!sniff->u.vm.equal && (mask & val) != (mask & value))\n\t) {\n\t\tret = 1;\n\t\tif (0)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" addr:0x%x len:%u val:0x%x (i:%d sniff_len:%u m_shift:%d mask:0x%x v_shifd:%d value:0x%x equal:%d)\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), addr, len, val, i, sniff_len, mask_shift, mask, value_shift, value, sniff->u.vm.equal);\n\t}\n\nexit:\n\treturn ret;\n}\n\nstatic bool match_io_sniff(_adapter *adapter\n\t, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val)\n{\n\tbool ret = 0;\n\n\tif (sniff->chip != MAX_CHIP_TYPE\n\t\t&& sniff->chip != rtw_get_chip_type(adapter))\n\t\tgoto exit;\n\tif (sniff->hci\n\t\t&& !(sniff->hci & rtw_get_intf_type(adapter)))\n\t\tgoto exit;\n\tif (sniff->addr >= addr + len) /* IO range below sniff start address */\n\t\tgoto exit;\n\n\tswitch (sniff->type) {\n\tcase RTW_IO_SNIFF_TYPE_RANGE:\n\t\tret = match_io_sniff_ranges(adapter, sniff, i, addr, len);\n\t\tbreak;\n\tcase RTW_IO_SNIFF_TYPE_VALUE:\n\t\tif (len == 1 || len == 2 || len == 4)\n\t\t\tret = match_io_sniff_value(adapter, sniff, i, addr, len, val);\n\t\tbreak;\n\tdefault:\n\t\trtw_warn_on(1);\n\t\tbreak;\n\t}\n\nexit:\n\treturn ret;\n}\n\nu32 match_read_sniff(_adapter *adapter, u32 addr, u16 len, u32 val)\n{\n\tint i;\n\tbool trace = 0;\n\tu32 match = 0;\n\n\tfor (i = 0; i < read_sniff_num; i++) {\n\t\tif (match_io_sniff(adapter, &read_sniff[i], i, addr, len, val)) {\n\t\t\tmatch++;\n\t\t\ttrace |= read_sniff[i].trace;\n\t\t\tif (read_sniff[i].tag)\n\t\t\t\tRTW_INFO(\"DBG_IO TAG %s\\n\", read_sniff[i].tag);\n\t\t}\n\t}\n\n\trtw_warn_on(trace);\n\n\treturn match;\n}\n\nu32 match_write_sniff(_adapter *adapter, u32 addr, u16 len, u32 val)\n{\n\tint i;\n\tbool trace = 0;\n\tu32 match = 0;\n\n\tfor (i = 0; i < write_sniff_num; i++) {\n\t\tif (match_io_sniff(adapter, &write_sniff[i], i, addr, len, val)) {\n\t\t\tmatch++;\n\t\t\ttrace |= write_sniff[i].trace;\n\t\t\tif (write_sniff[i].tag)\n\t\t\t\tRTW_INFO(\"DBG_IO TAG %s\\n\", write_sniff[i].tag);\n\t\t}\n\t}\n\n\trtw_warn_on(trace);\n\n\treturn match;\n}\n\nstruct rf_sniff_ent {\n\tu8 path;\n\tu16 reg;\n\tu32 mask;\n};\n\nstruct rf_sniff_ent rf_read_sniff_ranges[] = {\n\t/* example for all path addr 0x55 with all RF Reg mask */\n\t/* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */\n};\n\nstruct rf_sniff_ent rf_write_sniff_ranges[] = {\n\t/* example for all path addr 0x55 with all RF Reg mask */\n\t/* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */\n};\n\nint rf_read_sniff_num = sizeof(rf_read_sniff_ranges) / sizeof(struct rf_sniff_ent);\nint rf_write_sniff_num = sizeof(rf_write_sniff_ranges) / sizeof(struct rf_sniff_ent);\n\nbool match_rf_read_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask)\n{\n\tint i;\n\n\tfor (i = 0; i < rf_read_sniff_num; i++) {\n\t\tif (rf_read_sniff_ranges[i].path == MAX_RF_PATH || rf_read_sniff_ranges[i].path == path)\n\t\t\tif (addr == rf_read_sniff_ranges[i].reg && (mask & rf_read_sniff_ranges[i].mask))\n\t\t\t\treturn _TRUE;\n\t}\n\n\treturn _FALSE;\n}\n\nbool match_rf_write_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask)\n{\n\tint i;\n\n\tfor (i = 0; i < rf_write_sniff_num; i++) {\n\t\tif (rf_write_sniff_ranges[i].path == MAX_RF_PATH || rf_write_sniff_ranges[i].path == path)\n\t\t\tif (addr == rf_write_sniff_ranges[i].reg && (mask & rf_write_sniff_ranges[i].mask))\n\t\t\t\treturn _TRUE;\n\t}\n\n\treturn _FALSE;\n}\n\nu8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line)\n{\n\tu8 val = _rtw_read8(adapter, addr);\n\n\tif (match_read_sniff(adapter, addr, 1, val)) {\n\t\tRTW_INFO(\"DBG_IO %s:%d rtw_read8(0x%04x) return 0x%02x\\n\"\n\t\t\t, caller, line, addr, val);\n\t}\n\n\treturn val;\n}\n\nu16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line)\n{\n\tu16 val = _rtw_read16(adapter, addr);\n\n\tif (match_read_sniff(adapter, addr, 2, val)) {\n\t\tRTW_INFO(\"DBG_IO %s:%d rtw_read16(0x%04x) return 0x%04x\\n\"\n\t\t\t, caller, line, addr, val);\n\t}\n\n\treturn val;\n}\n\nu32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line)\n{\n\tu32 val = _rtw_read32(adapter, addr);\n\n\tif (match_read_sniff(adapter, addr, 4, val)) {\n\t\tRTW_INFO(\"DBG_IO %s:%d rtw_read32(0x%04x) return 0x%08x\\n\"\n\t\t\t, caller, line, addr, val);\n\t}\n\n\treturn val;\n}\n\nint dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line)\n{\n\tif (match_write_sniff(adapter, addr, 1, val)) {\n\t\tRTW_INFO(\"DBG_IO %s:%d rtw_write8(0x%04x, 0x%02x)\\n\"\n\t\t\t, caller, line, addr, val);\n\t}\n\n\treturn _rtw_write8(adapter, addr, val);\n}\nint dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line)\n{\n\tif (match_write_sniff(adapter, addr, 2, val)) {\n\t\tRTW_INFO(\"DBG_IO %s:%d rtw_write16(0x%04x, 0x%04x)\\n\"\n\t\t\t, caller, line, addr, val);\n\t}\n\n\treturn _rtw_write16(adapter, addr, val);\n}\nint dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line)\n{\n\tif (match_write_sniff(adapter, addr, 4, val)) {\n\t\tRTW_INFO(\"DBG_IO %s:%d rtw_write32(0x%04x, 0x%08x)\\n\"\n\t\t\t, caller, line, addr, val);\n\t}\n\n\treturn _rtw_write32(adapter, addr, val);\n}\nint dbg_rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *data, const char *caller, const int line)\n{\n\tif (match_write_sniff(adapter, addr, length, 0)) {\n\t\tRTW_INFO(\"DBG_IO %s:%d rtw_writeN(0x%04x, %u)\\n\"\n\t\t\t, caller, line, addr, length);\n\t}\n\n\treturn _rtw_writeN(adapter, addr, length, data);\n}\n\n#ifdef CONFIG_SDIO_HCI\nu8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line)\n{\n\tu8 val = _rtw_sd_f0_read8(adapter, addr);\n\n#if 0\n\tif (match_read_sniff(adapter, addr, 1, val)) {\n\t\tRTW_INFO(\"DBG_IO %s:%d rtw_sd_f0_read8(0x%04x) return 0x%02x\\n\"\n\t\t\t, caller, line, addr, val);\n\t}\n#endif\n\n\treturn val;\n}\n\n#ifdef CONFIG_SDIO_INDIRECT_ACCESS\nu8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line)\n{\n\tu8 val = rtw_sd_iread8(adapter, addr);\n\n\tif (match_read_sniff(adapter, addr, 1, val)) {\n\t\tRTW_INFO(\"DBG_IO %s:%d rtw_sd_iread8(0x%04x) return 0x%02x\\n\"\n\t\t\t, caller, line, addr, val);\n\t}\n\n\treturn val;\n}\n\nu16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line)\n{\n\tu16 val = _rtw_sd_iread16(adapter, addr);\n\n\tif (match_read_sniff(adapter, addr, 2, val)) {\n\t\tRTW_INFO(\"DBG_IO %s:%d rtw_sd_iread16(0x%04x) return 0x%04x\\n\"\n\t\t\t, caller, line, addr, val);\n\t}\n\n\treturn val;\n}\n\nu32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line)\n{\n\tu32 val = _rtw_sd_iread32(adapter, addr);\n\n\tif (match_read_sniff(adapter, addr, 4, val)) {\n\t\tRTW_INFO(\"DBG_IO %s:%d rtw_sd_iread32(0x%04x) return 0x%08x\\n\"\n\t\t\t, caller, line, addr, val);\n\t}\n\n\treturn val;\n}\n\nint dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line)\n{\n\tif (match_write_sniff(adapter, addr, 1, val)) {\n\t\tRTW_INFO(\"DBG_IO %s:%d rtw_sd_iwrite8(0x%04x, 0x%02x)\\n\"\n\t\t\t, caller, line, addr, val);\n\t}\n\n\treturn _rtw_sd_iwrite8(adapter, addr, val);\n}\nint dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line)\n{\n\tif (match_write_sniff(adapter, addr, 2, val)) {\n\t\tRTW_INFO(\"DBG_IO %s:%d rtw_sd_iwrite16(0x%04x, 0x%04x)\\n\"\n\t\t\t, caller, line, addr, val);\n\t}\n\n\treturn _rtw_sd_iwrite16(adapter, addr, val);\n}\nint dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line)\n{\n\tif (match_write_sniff(adapter, addr, 4, val)) {\n\t\tRTW_INFO(\"DBG_IO %s:%d rtw_sd_iwrite32(0x%04x, 0x%08x)\\n\"\n\t\t\t, caller, line, addr, val);\n\t}\n\n\treturn _rtw_sd_iwrite32(adapter, addr, val);\n}\n\n#endif /* CONFIG_SDIO_INDIRECT_ACCESS */\n\n#endif /* CONFIG_SDIO_HCI */\n\n#endif\n"
  },
  {
    "path": "core/rtw_ioctl_query.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_IOCTL_QUERY_C_\n\n#include <drv_types.h>\n\n\n"
  },
  {
    "path": "core/rtw_ioctl_set.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_IOCTL_SET_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\n\nextern void indicate_wx_scan_complete_event(_adapter *padapter);\n\n#define IS_MAC_ADDRESS_BROADCAST(addr) \\\n\t(\\\n\t ((addr[0] == 0xff) && (addr[1] == 0xff) && \\\n\t  (addr[2] == 0xff) && (addr[3] == 0xff) && \\\n\t  (addr[4] == 0xff) && (addr[5] == 0xff)) ? _TRUE : _FALSE \\\n\t)\n\nu8 rtw_validate_bssid(u8 *bssid)\n{\n\tu8 ret = _TRUE;\n\n\tif (is_zero_mac_addr(bssid)\n\t    || is_broadcast_mac_addr(bssid)\n\t    || is_multicast_mac_addr(bssid)\n\t   )\n\t\tret = _FALSE;\n\n\treturn ret;\n}\n\nu8 rtw_validate_ssid(NDIS_802_11_SSID *ssid)\n{\n#ifdef CONFIG_VALIDATE_SSID\n\tu8\t i;\n#endif\n\tu8\tret = _TRUE;\n\n\n\tif (ssid->SsidLength > 32) {\n\t\tret = _FALSE;\n\t\tgoto exit;\n\t}\n\n#ifdef CONFIG_VALIDATE_SSID\n\tfor (i = 0; i < ssid->SsidLength; i++) {\n\t\t/* wifi, printable ascii code must be supported */\n\t\tif (!((ssid->Ssid[i] >= 0x20) && (ssid->Ssid[i] <= 0x7e))) {\n\t\t\tret = _FALSE;\n\t\t\tbreak;\n\t\t}\n\t}\n#endif /* CONFIG_VALIDATE_SSID */\n\nexit:\n\n\n\treturn ret;\n}\n\nu8 rtw_do_join(_adapter *padapter);\nu8 rtw_do_join(_adapter *padapter)\n{\n\t_irqL\tirqL;\n\t_list\t*plist, *phead;\n\tu8 *pibss = NULL;\n\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tstruct sitesurvey_parm parm;\n\t_queue\t*queue\t= &(pmlmepriv->scanned_queue);\n\tu8 ret = _SUCCESS;\n\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\n\n\tpmlmepriv->cur_network.join_res = -2;\n\n\tset_fwstate(pmlmepriv, _FW_UNDER_LINKING);\n\n\tpmlmepriv->pscanned = plist;\n\n\tpmlmepriv->to_join = _TRUE;\n\n\trtw_init_sitesurvey_parm(padapter, &parm);\n\t_rtw_memcpy(&parm.ssid[0], &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));\n\tparm.ssid_num = 1;\n\n\tif (pmlmepriv->assoc_ch) {\n\t\tparm.ch_num = 1;\n\t\tparm.ch[0].hw_value = pmlmepriv->assoc_ch;\n\t\tparm.ch[0].flags = 0;\n\t}\n\n\tif (_rtw_queue_empty(queue) == _TRUE) {\n\t\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\t\t_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);\n\n\t\t/* when set_ssid/set_bssid for rtw_do_join(), but scanning queue is empty */\n\t\t/* we try to issue sitesurvey firstly\t */\n\n\t\tif (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE\n\t\t    || rtw_to_roam(padapter) > 0\n\t\t   ) {\n\t\t\tu8 ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);\n\n\t\t\tif ((ssc_chk == SS_ALLOW) || (ssc_chk == SS_DENY_BUSY_TRAFFIC) ){\n\t\t\t\t/* submit site_survey_cmd */\n\t\t\t\tret = rtw_sitesurvey_cmd(padapter, &parm);\n\t\t\t\tif (_SUCCESS != ret)\n\t\t\t\t\tpmlmepriv->to_join = _FALSE;\n\t\t\t} else {\n\t\t\t\t/*if (ssc_chk == SS_DENY_BUDDY_UNDER_SURVEY)*/\n\t\t\t\tpmlmepriv->to_join = _FALSE;\n\t\t\t\tret = _FAIL;\n\t\t\t}\n\t\t} else {\n\t\t\tpmlmepriv->to_join = _FALSE;\n\t\t\tret = _FAIL;\n\t\t}\n\n\t\tgoto exit;\n\t} else {\n\t\tint select_ret;\n\t\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\t\tselect_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv);\n\t\tif (select_ret == _SUCCESS) {\n\t\t\tpmlmepriv->to_join = _FALSE;\n\t\t\t_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);\n\t\t} else {\n\t\t\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {\n\t\t\t\t/* submit createbss_cmd to change to a ADHOC_MASTER */\n\n\t\t\t\t/* pmlmepriv->lock has been acquired by caller... */\n\t\t\t\tWLAN_BSSID_EX    *pdev_network = &(padapter->registrypriv.dev_network);\n\n\t\t\t\t/*pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;*/\n\t\t\t\tinit_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);\n\n\t\t\t\tpibss = padapter->registrypriv.dev_network.MacAddress;\n\n\t\t\t\t_rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID));\n\t\t\t\t_rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));\n\n\t\t\t\trtw_update_registrypriv_dev_network(padapter);\n\n\t\t\t\trtw_generate_random_ibss(pibss);\n\n\t\t\t\tif (rtw_create_ibss_cmd(padapter, 0) != _SUCCESS) {\n\t\t\t\t\tret =  _FALSE;\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\n\t\t\t\tpmlmepriv->to_join = _FALSE;\n\n\n\t\t\t} else {\n\t\t\t\t/* can't associate ; reset under-linking\t\t\t */\n\t\t\t\t_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);\n\n\t\t\t\t/* when set_ssid/set_bssid for rtw_do_join(), but there are no desired bss in scanning queue */\n\t\t\t\t/* we try to issue sitesurvey firstly\t\t\t */\n\t\t\t\tif (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE\n\t\t\t\t    || rtw_to_roam(padapter) > 0\n\t\t\t\t   ) {\n\t\t\t\t\tu8 ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);\n\n\t\t\t\t\tif ((ssc_chk == SS_ALLOW) || (ssc_chk == SS_DENY_BUSY_TRAFFIC)){\n\t\t\t\t\t\t/* RTW_INFO((\"rtw_do_join() when   no desired bss in scanning queue\\n\"); */\n\t\t\t\t\t\tret = rtw_sitesurvey_cmd(padapter, &parm);\n\t\t\t\t\t\tif (_SUCCESS != ret)\n\t\t\t\t\t\t\tpmlmepriv->to_join = _FALSE;\n\t\t\t\t\t} else {\n\t\t\t\t\t\t/*if (ssc_chk == SS_DENY_BUDDY_UNDER_SURVEY) {\n\t\t\t\t\t\t} else {*/\n\t\t\t\t\t\tret = _FAIL;\n\t\t\t\t\t\tpmlmepriv->to_join = _FALSE;\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tret = _FAIL;\n\t\t\t\t\tpmlmepriv->to_join = _FALSE;\n\t\t\t\t}\n\t\t\t}\n\n\t\t}\n\n\t}\n\nexit:\n\n\treturn ret;\n}\n\nu8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid)\n{\n\t_irqL irqL;\n\tu8 status = _SUCCESS;\n\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n\n\tRTW_PRINT(\"set bssid:%pM\\n\", bssid);\n\n\tif ((bssid[0] == 0x00 && bssid[1] == 0x00 && bssid[2] == 0x00 && bssid[3] == 0x00 && bssid[4] == 0x00 && bssid[5] == 0x00) ||\n\t    (bssid[0] == 0xFF && bssid[1] == 0xFF && bssid[2] == 0xFF && bssid[3] == 0xFF && bssid[4] == 0xFF && bssid[5] == 0xFF)) {\n\t\tstatus = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\n\n\tRTW_INFO(\"Set BSSID under fw_state=0x%08x\\n\", get_fwstate(pmlmepriv));\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE)\n\t\tgoto handle_tkip_countermeasure;\n\telse if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE)\n\t\tgoto release_mlme_lock;\n\n\tif (check_fwstate(pmlmepriv, _FW_LINKED | WIFI_ADHOC_MASTER_STATE) == _TRUE) {\n\n\t\tif (_rtw_memcmp(&pmlmepriv->cur_network.network.MacAddress, bssid, ETH_ALEN) == _TRUE) {\n\t\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE)\n\t\t\t\tgoto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */\n\t\t} else {\n\n\t\t\trtw_disassoc_cmd(padapter, 0, 0);\n\n\t\t\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t\t\trtw_indicate_disconnect(padapter, 0, _FALSE);\n\n\t\t\trtw_free_assoc_resources_cmd(padapter, _TRUE, 0);\n\n\t\t\tif ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {\n\t\t\t\t_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);\n\t\t\t\tset_fwstate(pmlmepriv, WIFI_ADHOC_STATE);\n\t\t\t}\n\t\t}\n\t}\n\nhandle_tkip_countermeasure:\n\tif (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {\n\t\tstatus = _FAIL;\n\t\tgoto release_mlme_lock;\n\t}\n\n\t_rtw_memset(&pmlmepriv->assoc_ssid, 0, sizeof(NDIS_802_11_SSID));\n\t_rtw_memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN);\n\tpmlmepriv->assoc_ch = 0;\n\tpmlmepriv->assoc_by_bssid = _TRUE;\n\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE)\n\t\tpmlmepriv->to_join = _TRUE;\n\telse\n\t\tstatus = rtw_do_join(padapter);\n\nrelease_mlme_lock:\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\nexit:\n\n\n\treturn status;\n}\n\nu8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid)\n{\n\t_irqL irqL;\n\tu8 status = _SUCCESS;\n\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct wlan_network *pnetwork = &pmlmepriv->cur_network;\n\n\n\tRTW_PRINT(\"set ssid [%s] fw_state=0x%08x\\n\",\n\t\t  ssid->Ssid, get_fwstate(pmlmepriv));\n\n\tif (!rtw_is_hw_init_completed(padapter)) {\n\t\tstatus = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\n\tRTW_INFO(\"Set SSID under fw_state=0x%08x\\n\", get_fwstate(pmlmepriv));\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE)\n\t\tgoto handle_tkip_countermeasure;\n\telse if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE)\n\t\tgoto release_mlme_lock;\n\n\tif (check_fwstate(pmlmepriv, _FW_LINKED | WIFI_ADHOC_MASTER_STATE) == _TRUE) {\n\n\t\tif ((pmlmepriv->assoc_ssid.SsidLength == ssid->SsidLength) &&\n\t\t    (_rtw_memcmp(&pmlmepriv->assoc_ssid.Ssid, ssid->Ssid, ssid->SsidLength) == _TRUE)) {\n\t\t\tif ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE)) {\n\n\t\t\t\tif (rtw_is_same_ibss(padapter, pnetwork) == _FALSE) {\n\t\t\t\t\t/* if in WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE, create bss or rejoin again */\n\t\t\t\t\trtw_disassoc_cmd(padapter, 0, 0);\n\n\t\t\t\t\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t\t\t\t\trtw_indicate_disconnect(padapter, 0, _FALSE);\n\n\t\t\t\t\trtw_free_assoc_resources_cmd(padapter, _TRUE, 0);\n\n\t\t\t\t\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) {\n\t\t\t\t\t\t_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);\n\t\t\t\t\t\tset_fwstate(pmlmepriv, WIFI_ADHOC_STATE);\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tgoto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */\n\t\t\t\t}\n\t\t\t}\n#ifdef CONFIG_LPS\n\t\t\telse\n\t\t\t\trtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_JOINBSS, 0);\n#endif\n\t\t} else {\n\n\t\t\trtw_disassoc_cmd(padapter, 0, 0);\n\n\t\t\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t\t\trtw_indicate_disconnect(padapter, 0, _FALSE);\n\n\t\t\trtw_free_assoc_resources_cmd(padapter, _TRUE, 0);\n\n\t\t\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) {\n\t\t\t\t_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);\n\t\t\t\tset_fwstate(pmlmepriv, WIFI_ADHOC_STATE);\n\t\t\t}\n\t\t}\n\t}\n\nhandle_tkip_countermeasure:\n\tif (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {\n\t\tstatus = _FAIL;\n\t\tgoto release_mlme_lock;\n\t}\n\n\tif (rtw_validate_ssid(ssid) == _FALSE) {\n\t\tstatus = _FAIL;\n\t\tgoto release_mlme_lock;\n\t}\n\n\t_rtw_memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(NDIS_802_11_SSID));\n\tpmlmepriv->assoc_by_bssid = _FALSE;\n\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE)\n\t\tpmlmepriv->to_join = _TRUE;\n\telse\n\t\tstatus = rtw_do_join(padapter);\n\nrelease_mlme_lock:\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\nexit:\n\n\n\treturn status;\n\n}\n\nu8 rtw_set_802_11_connect(_adapter *padapter,\n\t\t\t  u8 *bssid, NDIS_802_11_SSID *ssid, u16 ch)\n{\n\t_irqL irqL;\n\tu8 status = _SUCCESS;\n\tbool bssid_valid = _TRUE;\n\tbool ssid_valid = _TRUE;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n\n\tif (!ssid || rtw_validate_ssid(ssid) == _FALSE)\n\t\tssid_valid = _FALSE;\n\n\tif (!bssid || rtw_validate_bssid(bssid) == _FALSE)\n\t\tbssid_valid = _FALSE;\n\n\tif (ssid_valid == _FALSE && bssid_valid == _FALSE) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" ssid:%p, ssid_valid:%d, bssid:%p, bssid_valid:%d\\n\",\n\t\t\tFUNC_ADPT_ARG(padapter), ssid, ssid_valid, bssid, bssid_valid);\n\t\tstatus = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tif (!rtw_is_hw_init_completed(padapter)) {\n\t\tstatus = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\n\tRTW_PRINT(FUNC_ADPT_FMT\"  fw_state=0x%08x\\n\",\n\t\t  FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv));\n\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE)\n\t\tgoto handle_tkip_countermeasure;\n\telse if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE)\n\t\tgoto release_mlme_lock;\n\nhandle_tkip_countermeasure:\n\tif (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {\n\t\tstatus = _FAIL;\n\t\tgoto release_mlme_lock;\n\t}\n\n\tif (ssid && ssid_valid)\n\t\t_rtw_memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(NDIS_802_11_SSID));\n\telse\n\t\t_rtw_memset(&pmlmepriv->assoc_ssid, 0, sizeof(NDIS_802_11_SSID));\n\n\tif (bssid && bssid_valid) {\n\t\t_rtw_memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN);\n\t\tpmlmepriv->assoc_by_bssid = _TRUE;\n\t} else\n\t\tpmlmepriv->assoc_by_bssid = _FALSE;\n\n\tpmlmepriv->assoc_ch = ch;\n\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE)\n\t\tpmlmepriv->to_join = _TRUE;\n\telse\n\t\tstatus = rtw_do_join(padapter);\n\nrelease_mlme_lock:\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\nexit:\n\n\n\treturn status;\n}\n\nu8 rtw_set_802_11_infrastructure_mode(_adapter *padapter,\n\t\t\t      NDIS_802_11_NETWORK_INFRASTRUCTURE networktype)\n{\n\t_irqL irqL;\n\tstruct\tmlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct\twlan_network\t*cur_network = &pmlmepriv->cur_network;\n\tNDIS_802_11_NETWORK_INFRASTRUCTURE *pold_state = &(cur_network->network.InfrastructureMode);\n\tu8 ap2sta_mode = _FALSE;\n\tu8 ret = _TRUE;\n\n\tif (*pold_state != networktype) {\n\t\t/* RTW_INFO(\"change mode, old_mode=%d, new_mode=%d, fw_state=0x%x\\n\", *pold_state, networktype, get_fwstate(pmlmepriv)); */\n\n\t\tif (*pold_state == Ndis802_11APMode\n\t\t\t|| *pold_state == Ndis802_11_mesh\n\t\t) {\n\t\t\t/* change to other mode from Ndis802_11APMode/Ndis802_11_mesh */\n\t\t\tcur_network->join_res = -1;\n\t\t\tap2sta_mode = _TRUE;\n#ifdef CONFIG_NATIVEAP_MLME\n\t\t\tstop_ap_mode(padapter);\n#endif\n\t\t}\n\n\t\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\n\t\tif ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) || (*pold_state == Ndis802_11IBSS))\n\t\t\trtw_disassoc_cmd(padapter, 0, 0);\n\n\t\tif ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ||\n\t\t    (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE))\n\t\t\trtw_free_assoc_resources_cmd(padapter, _TRUE, 0);\n\n\t\tif ((*pold_state == Ndis802_11Infrastructure) || (*pold_state == Ndis802_11IBSS)) {\n\t\t\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {\n\t\t\t\trtw_indicate_disconnect(padapter, 0, _FALSE); /*will clr Linked_state; before this function, we must have checked whether issue dis-assoc_cmd or not*/\n\t\t\t}\n\t\t}\n\n\t\t*pold_state = networktype;\n\n\t\t_clr_fwstate_(pmlmepriv, ~WIFI_NULL_STATE);\n\n\t\tswitch (networktype) {\n\t\tcase Ndis802_11IBSS:\n\t\t\tset_fwstate(pmlmepriv, WIFI_ADHOC_STATE);\n\t\t\tbreak;\n\n\t\tcase Ndis802_11Infrastructure:\n\t\t\tset_fwstate(pmlmepriv, WIFI_STATION_STATE);\n\n\t\t\tif (ap2sta_mode)\n\t\t\t\trtw_init_bcmc_stainfo(padapter);\n\t\t\tbreak;\n\n\t\tcase Ndis802_11APMode:\n\t\t\tset_fwstate(pmlmepriv, WIFI_AP_STATE);\n#ifdef CONFIG_NATIVEAP_MLME\n\t\t\tstart_ap_mode(padapter);\n\t\t\t/* rtw_indicate_connect(padapter); */\n#endif\n\n\t\t\tbreak;\n\n#ifdef CONFIG_RTW_MESH\n\t\tcase Ndis802_11_mesh:\n\t\t\tset_fwstate(pmlmepriv, WIFI_MESH_STATE);\n\t\t\tstart_ap_mode(padapter);\n\t\t\tbreak;\n#endif\n\n\t\tcase Ndis802_11AutoUnknown:\n\t\tcase Ndis802_11InfrastructureMax:\n\t\t\tbreak;\n\t\tcase Ndis802_11Monitor:\n\t\t\tset_fwstate(pmlmepriv, WIFI_MONITOR_STATE);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tret = _FALSE;\n\t\t\trtw_warn_on(1);\n\t\t}\n\n\t\t/* SecClearAllKeys(adapter); */\n\n\n\t\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\t}\n\n\treturn ret;\n}\n\n\nu8 rtw_set_802_11_disassociate(_adapter *padapter)\n{\n\t_irqL irqL;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {\n\n\t\trtw_disassoc_cmd(padapter, 0, 0);\n\t\trtw_indicate_disconnect(padapter, 0, _FALSE);\n\t\t/* modify for CONFIG_IEEE80211W, none 11w can use it */\n\t\trtw_free_assoc_resources_cmd(padapter, _TRUE, 0);\n\t\tif (_FAIL == rtw_pwr_wakeup(padapter))\n\t\t\tRTW_INFO(\"%s(): rtw_pwr_wakeup fail !!!\\n\", __FUNCTION__);\n\t}\n\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\n\n\treturn _TRUE;\n}\n\n#if 1\nu8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm)\n{\n\t_irqL\tirqL;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tu8\tres = _TRUE;\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\tres = rtw_sitesurvey_cmd(padapter, pparm);\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\n\treturn res;\n}\n\n#else\nu8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm)\n{\n\t_irqL\tirqL;\n\tstruct\tmlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tu8\tres = _TRUE;\n\n\n\n\tif (padapter == NULL) {\n\t\tres = _FALSE;\n\t\tgoto exit;\n\t}\n\tif (!rtw_is_hw_init_completed(padapter)) {\n\t\tres = _FALSE;\n\t\tgoto exit;\n\t}\n\n\tif ((check_fwstate(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) ||\n\t    (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)) {\n\t\t/* Scan or linking is in progress, do nothing. */\n\t\tres = _TRUE;\n\n\n\t} else {\n\t\tif (rtw_is_scan_deny(padapter)) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\": scan deny\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\tindicate_wx_scan_complete_event(padapter);\n\t\t\treturn _SUCCESS;\n\t\t}\n\n\t\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\n\t\tres = rtw_sitesurvey_cmd(padapter, pparm);\n\n\t\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\t}\nexit:\n\n\n\treturn res;\n}\n#endif\nu8 rtw_set_802_11_authentication_mode(_adapter *padapter, NDIS_802_11_AUTHENTICATION_MODE authmode)\n{\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tint res;\n\tu8 ret;\n\n\n\n\tpsecuritypriv->ndisauthtype = authmode;\n\n\n\tif (psecuritypriv->ndisauthtype > 3)\n\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;\n\n#ifdef CONFIG_WAPI_SUPPORT\n\tif (psecuritypriv->ndisauthtype == 6)\n\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;\n#endif\n\n\tres = rtw_set_auth(padapter, psecuritypriv);\n\n\tif (res == _SUCCESS)\n\t\tret = _TRUE;\n\telse\n\t\tret = _FALSE;\n\n\n\treturn ret;\n}\n\nu8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep)\n{\n\n\tu8\t\tbdefaultkey;\n\tu8\t\tbtransmitkey;\n\tsint\t\tkeyid, res;\n\tstruct security_priv *psecuritypriv = &(padapter->securitypriv);\n\tu8\t\tret = _SUCCESS;\n\n\n\tbdefaultkey = (wep->KeyIndex & 0x40000000) > 0 ? _FALSE : _TRUE; /* for ??? */\n\tbtransmitkey = (wep->KeyIndex & 0x80000000) > 0 ? _TRUE  : _FALSE;\t/* for ??? */\n\tkeyid = wep->KeyIndex & 0x3fffffff;\n\n\tif (keyid >= 4) {\n\t\tret = _FALSE;\n\t\tgoto exit;\n\t}\n\n\tswitch (wep->KeyLength) {\n\tcase 5:\n\t\tpsecuritypriv->dot11PrivacyAlgrthm = _WEP40_;\n\t\tbreak;\n\tcase 13:\n\t\tpsecuritypriv->dot11PrivacyAlgrthm = _WEP104_;\n\t\tbreak;\n\tdefault:\n\t\tpsecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;\n\t\tbreak;\n\t}\n\n\n\t_rtw_memcpy(&(psecuritypriv->dot11DefKey[keyid].skey[0]), &(wep->KeyMaterial), wep->KeyLength);\n\n\tpsecuritypriv->dot11DefKeylen[keyid] = wep->KeyLength;\n\n\tpsecuritypriv->dot11PrivacyKeyIndex = keyid;\n\n\n\tres = rtw_set_key(padapter, psecuritypriv, keyid, 1, _TRUE);\n\n\tif (res == _FAIL)\n\t\tret = _FALSE;\nexit:\n\n\n\treturn ret;\n\n}\n\n/*\n* rtw_get_cur_max_rate -\n* @adapter: pointer to _adapter structure\n*\n* Return 0 or 100Kbps\n*/\nu16 rtw_get_cur_max_rate(_adapter *adapter)\n{\n\tint j;\n\tint\ti = 0;\n\tu16\trate = 0, max_rate = 0;\n\tstruct mlme_priv\t*pmlmepriv = &adapter->mlmepriv;\n\tWLAN_BSSID_EX\t*pcur_bss = &pmlmepriv->cur_network.network;\n\tint\tsta_bssrate_len = 0;\n\tunsigned char\tsta_bssrate[NumRates];\n\tstruct sta_info *psta = NULL;\n\tu8\tshort_GI = 0;\n#ifdef CONFIG_80211N_HT\n\tu8\trf_type = 0;\n#endif\n\n#ifdef CONFIG_MP_INCLUDED\n\tif (adapter->registrypriv.mp_mode == 1) {\n\t\tif (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)\n\t\t\treturn 0;\n\t}\n#endif\n\n\tif ((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE)\n\t    && (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE))\n\t\treturn 0;\n\n\tpsta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));\n\tif (psta == NULL)\n\t\treturn 0;\n\n\tshort_GI = query_ra_short_GI(psta, rtw_get_tx_bw_mode(adapter, psta));\n\n#ifdef CONFIG_80211N_HT\n\tif (is_supported_ht(psta->wireless_mode)) {\n\t\trtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));\n\t\tmax_rate = rtw_mcs_rate(rf_type\n\t\t\t, (psta->cmn.bw_mode == CHANNEL_WIDTH_40) ? 1 : 0\n\t\t\t, short_GI\n\t\t\t, psta->htpriv.ht_cap.supp_mcs_set\n\t\t);\n\t}\n#ifdef CONFIG_80211AC_VHT\n\telse if (is_supported_vht(psta->wireless_mode))\n\t\tmax_rate = ((rtw_vht_mcs_to_data_rate(psta->cmn.bw_mode, short_GI, pmlmepriv->vhtpriv.vht_highest_rate) + 1) >> 1) * 10;\n#endif /* CONFIG_80211AC_VHT */\n\telse\n#endif /* CONFIG_80211N_HT */\n\t{\n\t\t/*station mode show :station && ap support rate; softap :show ap support rate*/\t\n\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)\n\t\t\tget_rate_set(adapter, sta_bssrate, &sta_bssrate_len);/*get sta rate and length*/\n\n\n\t\twhile ((pcur_bss->SupportedRates[i] != 0) && (pcur_bss->SupportedRates[i] != 0xFF)) {\n\t\t\trate = pcur_bss->SupportedRates[i] & 0x7F;/*AP support rates*/\n\t\t\t/*RTW_INFO(\"%s rate=%02X \\n\", __func__, rate);*/\n\n\t\t\t/*check STA  support rate or not */\n\t\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {\n\t\t\t\tfor (j = 0; j < sta_bssrate_len; j++) {\n\t\t\t\t\t/* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */\n\t\t\t\t\tif ((rate | IEEE80211_BASIC_RATE_MASK)\n\t\t\t\t\t    == (sta_bssrate[j] | IEEE80211_BASIC_RATE_MASK)) {\n\t\t\t\t\t\tif (rate > max_rate) {\n\t\t\t\t\t\t\tmax_rate = rate;\n\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\n\t\t\t\tif (rate > max_rate)\n\t\t\t\t\tmax_rate = rate;\n\n\t\t\t}\n\t\t\ti++;\n\t\t}\n\n\t\tmax_rate = max_rate * 10 / 2;\n\t}\n\treturn max_rate;\n}\n\n/*\n* rtw_set_scan_mode -\n* @adapter: pointer to _adapter structure\n* @scan_mode:\n*\n* Return _SUCCESS or _FAIL\n*/\nint rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode)\n{\n\tif (scan_mode != SCAN_ACTIVE && scan_mode != SCAN_PASSIVE)\n\t\treturn _FAIL;\n\n\tadapter->mlmepriv.scan_mode = scan_mode;\n\n\treturn _SUCCESS;\n}\n\n/*\n* rtw_set_channel_plan -\n* @adapter: pointer to _adapter structure\n* @channel_plan:\n*\n* Return _SUCCESS or _FAIL\n*/\nint rtw_set_channel_plan(_adapter *adapter, u8 channel_plan)\n{\n\t/* handle by cmd_thread to sync with scan operation */\n\treturn rtw_set_chplan_cmd(adapter, RTW_CMDF_WAIT_ACK, channel_plan, 1);\n}\n\n/*\n* rtw_set_country -\n* @adapter: pointer to _adapter structure\n* @country_code: string of country code\n*\n* Return _SUCCESS or _FAIL\n*/\nint rtw_set_country(_adapter *adapter, const char *country_code)\n{\n#ifdef CONFIG_RTW_IOCTL_SET_COUNTRY\n\treturn rtw_set_country_cmd(adapter, RTW_CMDF_WAIT_ACK, country_code, 1);\n#else\n\tRTW_INFO(\"%s(): not applied\\n\", __func__);\n\treturn _SUCCESS;\n#endif\n}\n\n/*\n* rtw_set_band -\n* @adapter: pointer to _adapter structure\n* @band: band to set\n*\n* Return _SUCCESS or _FAIL\n*/\nint rtw_set_band(_adapter *adapter, u8 band)\n{\n\tif (rtw_band_valid(band)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" band:%d\\n\", FUNC_ADPT_ARG(adapter), band);\n\t\tadapter->setband = band;\n\t\treturn _SUCCESS;\n\t}\n\n\tRTW_PRINT(FUNC_ADPT_FMT\" band:%d fail\\n\", FUNC_ADPT_ARG(adapter), band);\n\treturn _FAIL;\n}\n"
  },
  {
    "path": "core/rtw_iol.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include <drv_types.h>\n\n#ifdef CONFIG_IOL\nstruct xmit_frame\t*rtw_IOL_accquire_xmit_frame(ADAPTER *adapter)\n{\n\tstruct xmit_frame\t*xmit_frame;\n\tstruct xmit_buf\t*xmitbuf;\n\tstruct pkt_attrib\t*pattrib;\n\tstruct xmit_priv\t*pxmitpriv = &(adapter->xmitpriv);\n\n#if 1\n\txmit_frame = rtw_alloc_xmitframe(pxmitpriv);\n\tif (xmit_frame == NULL) {\n\t\tRTW_INFO(\"%s rtw_alloc_xmitframe return null\\n\", __FUNCTION__);\n\t\tgoto exit;\n\t}\n\n\txmitbuf = rtw_alloc_xmitbuf(pxmitpriv);\n\tif (xmitbuf == NULL) {\n\t\tRTW_INFO(\"%s rtw_alloc_xmitbuf return null\\n\", __FUNCTION__);\n\t\trtw_free_xmitframe(pxmitpriv, xmit_frame);\n\t\txmit_frame = NULL;\n\t\tgoto exit;\n\t}\n\n\txmit_frame->frame_tag = MGNT_FRAMETAG;\n\txmit_frame->pxmitbuf = xmitbuf;\n\txmit_frame->buf_addr = xmitbuf->pbuf;\n\txmitbuf->priv_data = xmit_frame;\n\n\tpattrib = &xmit_frame->attrib;\n\tupdate_mgntframe_attrib(adapter, pattrib);\n\tpattrib->qsel = QSLT_BEACON;/* Beacon\t */\n\tpattrib->subtype = WIFI_BEACON;\n\tpattrib->pktlen = pattrib->last_txcmdsz = 0;\n\n#else\n\txmit_frame = alloc_mgtxmitframe(pxmitpriv);\n\tif (xmit_frame == NULL)\n\t\tRTW_INFO(\"%s alloc_mgtxmitframe return null\\n\", __FUNCTION__);\n\telse {\n\t\tpattrib = &xmit_frame->attrib;\n\t\tupdate_mgntframe_attrib(adapter, pattrib);\n\t\tpattrib->qsel = QSLT_BEACON;\n\t\tpattrib->pktlen = pattrib->last_txcmdsz = 0;\n\t}\n#endif\n\nexit:\n\treturn xmit_frame;\n}\n\n\nint rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len)\n{\n\tstruct pkt_attrib\t*pattrib = &xmit_frame->attrib;\n\tu16 buf_offset;\n\tu32 ori_len;\n\n\tbuf_offset = TXDESC_OFFSET;\n\tori_len = buf_offset + pattrib->pktlen;\n\n\t/* check if the io_buf can accommodate new cmds */\n\tif (ori_len + cmd_len + 8 > MAX_XMITBUF_SZ) {\n\t\tRTW_INFO(\"%s %u is large than MAX_XMITBUF_SZ:%u, can't accommodate new cmds\\n\", __FUNCTION__\n\t\t\t , ori_len + cmd_len + 8, MAX_XMITBUF_SZ);\n\t\treturn _FAIL;\n\t}\n\n\t_rtw_memcpy(xmit_frame->buf_addr + buf_offset + pattrib->pktlen, IOL_cmds, cmd_len);\n\tpattrib->pktlen += cmd_len;\n\tpattrib->last_txcmdsz += cmd_len;\n\n\t/* RTW_INFO(\"%s ori:%u + cmd_len:%u = %u\\n\", __FUNCTION__, ori_len, cmd_len, buf_offset+pattrib->pktlen); */\n\n\treturn _SUCCESS;\n}\n\nbool rtw_IOL_applied(ADAPTER *adapter)\n{\n\tif (1 == adapter->registrypriv.fw_iol)\n\t\treturn _TRUE;\n\n#ifdef CONFIG_USB_HCI\n\tif ((2 == adapter->registrypriv.fw_iol) && (IS_FULL_SPEED_USB(adapter)))\n\t\treturn _TRUE;\n#endif\n\n\treturn _FALSE;\n}\n\nint rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)\n{\n\treturn rtw_hal_iol_cmd(adapter, xmit_frame, max_wating_ms, bndy_cnt);\n}\n\n#ifdef CONFIG_IOL_NEW_GENERATION\nint rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary)\n{\n\treturn _SUCCESS;\n}\nint _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask)\n{\n\tstruct ioreg_cfg cmd = {8, IOREG_CMD_WB_REG, 0x0, 0x0, 0x0};\n\n\t/* RTW_PUT_LE16((u8*)&cmd.address, addr);\t */\n\t/* RTW_PUT_LE32((u8*)&cmd.value, (u32)value);\t */\n\tcmd.address = cpu_to_le16(addr);\n\tcmd.data = cpu_to_le32(value);\n\n\tif (mask != 0xFF) {\n\t\tcmd.length = 12;\n\t\t/* RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);\t */\n\t\tcmd.mask = cpu_to_le32(mask);\n\t}\n\n\t/* RTW_INFO(\"%s addr:0x%04x,value:0x%08x,mask:0x%08x\\n\", __FUNCTION__, addr,value,mask); */\n\n\treturn rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);\n\n}\nint _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask)\n{\n\tstruct ioreg_cfg cmd = {8, IOREG_CMD_WW_REG, 0x0, 0x0, 0x0};\n\n\t/* RTW_PUT_LE16((u8*)&cmd.address, addr);\t */\n\t/* RTW_PUT_LE32((u8*)&cmd.value, (u32)value);\t */\n\tcmd.address = cpu_to_le16(addr);\n\tcmd.data = cpu_to_le32(value);\n\n\tif (mask != 0xFFFF) {\n\t\tcmd.length = 12;\n\t\t/* RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);\t */\n\t\tcmd.mask =  cpu_to_le32(mask);\n\t}\n\n\t/* RTW_INFO(\"%s addr:0x%04x,value:0x%08x,mask:0x%08x\\n\", __FUNCTION__, addr,value,mask); */\n\n\treturn rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);\n\n}\nint _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask)\n{\n\tstruct ioreg_cfg cmd = {8, IOREG_CMD_WD_REG, 0x0, 0x0, 0x0};\n\n\t/* RTW_PUT_LE16((u8*)&cmd.address, addr);\t */\n\t/* RTW_PUT_LE32((u8*)&cmd.value, (u32)value);\t */\n\tcmd.address = cpu_to_le16(addr);\n\tcmd.data = cpu_to_le32(value);\n\n\tif (mask != 0xFFFFFFFF) {\n\t\tcmd.length = 12;\n\t\t/* RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);\t */\n\t\tcmd.mask =  cpu_to_le32(mask);\n\t}\n\n\t/* RTW_INFO(\"%s addr:0x%04x,value:0x%08x,mask:0x%08x\\n\", __FU2NCTION__, addr,value,mask); */\n\n\treturn rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);\n\n}\n\nint _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask)\n{\n\tstruct ioreg_cfg cmd = {8, IOREG_CMD_W_RF, 0x0, 0x0, 0x0};\n\n\t/* RTW_PUT_LE16((u8*)&cmd.address, addr);\t */\n\t/* RTW_PUT_LE32((u8*)&cmd.value, (u32)value);\t */\n\tcmd.address = (rf_path << 8) | ((addr) & 0xFF);\n\tcmd.data = cpu_to_le32(value);\n\n\tif (mask != 0x000FFFFF) {\n\t\tcmd.length = 12;\n\t\t/* RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);\t */\n\t\tcmd.mask =  cpu_to_le32(mask);\n\t}\n\n\t/* RTW_INFO(\"%s rf_path:0x%02x addr:0x%04x,value:0x%08x,mask:0x%08x\\n\", __FU2NCTION__,rf_path, addr,value,mask); */\n\n\treturn rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);\n\n}\n\n\n\nint rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)\n{\n\tstruct ioreg_cfg cmd = {4, IOREG_CMD_DELAY_US, 0x0, 0x0, 0x0};\n\t/* RTW_PUT_LE16((u8*)&cmd.address, us);\t */\n\tcmd.address = cpu_to_le16(us);\n\n\t/* RTW_INFO(\"%s %u\\n\", __FUNCTION__, us); */\n\treturn rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);\n}\n\nint rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)\n{\n\tstruct ioreg_cfg cmd = {4, IOREG_CMD_DELAY_US, 0x0, 0x0, 0x0};\n\n\t/* RTW_PUT_LE16((u8*)&cmd.address, ms);\t */\n\tcmd.address = cpu_to_le16(ms);\n\n\t/* RTW_INFO(\"%s %u\\n\", __FUNCTION__, ms); */\n\treturn rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);\n}\nint rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame)\n{\n\tstruct ioreg_cfg cmd = {4, IOREG_CMD_END, 0xFFFF, 0xFF, 0x0};\n\treturn rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);\n\n}\n\nu8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame)\n{\n\tu8 is_cmd_bndy = _FALSE;\n\tif (((pxmit_frame->attrib.pktlen + 32) % 256) + 8 >= 256) {\n\t\trtw_IOL_append_END_cmd(pxmit_frame);\n\t\tpxmit_frame->attrib.pktlen = ((((pxmit_frame->attrib.pktlen + 32) / 256) + 1) * 256);\n\n\t\t/* printk(\"==> %s, pktlen(%d)\\n\",__FUNCTION__,pxmit_frame->attrib.pktlen); */\n\t\tpxmit_frame->attrib.last_txcmdsz = pxmit_frame->attrib.pktlen;\n\t\tis_cmd_bndy = _TRUE;\n\t}\n\treturn is_cmd_bndy;\n}\n\nvoid rtw_IOL_cmd_buf_dump(ADAPTER *Adapter, int buf_len, u8 *pbuf)\n{\n\tint i;\n\tint j = 1;\n\n\tprintk(\"###### %s ######\\n\", __FUNCTION__);\n\tfor (i = 0; i < buf_len; i++) {\n\t\tprintk(\"%02x-\", *(pbuf + i));\n\n\t\tif (j % 32 == 0)\n\t\t\tprintk(\"\\n\");\n\t\tj++;\n\t}\n\tprintk(\"\\n\");\n\tprintk(\"============= ioreg_cmd len = %d ===============\\n\", buf_len);\n}\n\n\n#else /* CONFIG_IOL_NEW_GENERATION */\nint rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary)\n{\n\tIOL_CMD cmd = {0x0, IOL_CMD_LLT, 0x0, 0x0};\n\n\tRTW_PUT_BE32((u8 *)&cmd.value, (u32)page_boundary);\n\n\treturn rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);\n}\n\nint _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value)\n{\n\tIOL_CMD cmd = {0x0, IOL_CMD_WB_REG, 0x0, 0x0};\n\n\tRTW_PUT_BE16((u8 *)&cmd.address, (u16)addr);\n\tRTW_PUT_BE32((u8 *)&cmd.value, (u32)value);\n\n\treturn rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);\n}\n\nint _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value)\n{\n\tIOL_CMD cmd = {0x0, IOL_CMD_WW_REG, 0x0, 0x0};\n\n\tRTW_PUT_BE16((u8 *)&cmd.address, (u16)addr);\n\tRTW_PUT_BE32((u8 *)&cmd.value, (u32)value);\n\n\treturn rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);\n}\n\nint _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value)\n{\n\tIOL_CMD cmd = {0x0, IOL_CMD_WD_REG, 0x0, 0x0};\n\tu8 *pos = (u8 *)&cmd;\n\n\tRTW_PUT_BE16((u8 *)&cmd.address, (u16)addr);\n\tRTW_PUT_BE32((u8 *)&cmd.value, (u32)value);\n\n\treturn rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);\n}\n\n#ifdef DBG_IO\nint dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line)\n{\n\tif (match_write_sniff(xmit_frame->padapter, addr, 1, value)) {\n\t\tRTW_INFO(\"DBG_IO %s:%d IOL_WB(0x%04x, 0x%02x)\\n\"\n\t\t\t, caller, line, addr, value);\n\t}\n\n\treturn _rtw_IOL_append_WB_cmd(xmit_frame, addr, value);\n}\n\nint dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line)\n{\n\tif (match_write_sniff(xmit_frame->padapter, addr, 2, value)) {\n\t\tRTW_INFO(\"DBG_IO %s:%d IOL_WW(0x%04x, 0x%04x)\\n\"\n\t\t\t, caller, line, addr, value);\n\t}\n\n\treturn _rtw_IOL_append_WW_cmd(xmit_frame, addr, value);\n}\n\nint dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line)\n{\n\tif (match_write_sniff(xmit_frame->padapter, addr, 4, value)) {\n\t\tRTW_INFO(\"DBG_IO %s:%d IOL_WD(0x%04x, 0x%08x)\\n\"\n\t\t\t, caller, line, addr, value);\n\t}\n\n\treturn _rtw_IOL_append_WD_cmd(xmit_frame, addr, value);\n}\n#endif\n\nint rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)\n{\n\tIOL_CMD cmd = {0x0, IOL_CMD_DELAY_US, 0x0, 0x0};\n\n\tRTW_PUT_BE32((u8 *)&cmd.value, (u32)us);\n\n\t/* RTW_INFO(\"%s %u\\n\", __FUNCTION__, us); */\n\n\treturn rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);\n}\n\nint rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)\n{\n\tIOL_CMD cmd = {0x0, IOL_CMD_DELAY_MS, 0x0, 0x0};\n\n\tRTW_PUT_BE32((u8 *)&cmd.value, (u32)ms);\n\n\t/* RTW_INFO(\"%s %u\\n\", __FUNCTION__, ms); */\n\n\treturn rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);\n}\n\nint rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame)\n{\n\tIOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0};\n\n\n\treturn rtw_IOL_append_cmds(xmit_frame, (u8 *)&end_cmd, 8);\n\n}\n\nint rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms)\n{\n\tstruct xmit_frame\t*xmit_frame;\n\n\txmit_frame = rtw_IOL_accquire_xmit_frame(adapter);\n\tif (xmit_frame == NULL)\n\t\treturn _FAIL;\n\n\tif (rtw_IOL_append_cmds(xmit_frame, IOL_cmds, cmd_num << 3) == _FAIL)\n\t\treturn _FAIL;\n\n\treturn rtw_IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms, 0);\n}\n\nint rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms)\n{\n\tIOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0};\n\treturn rtw_IOL_exec_cmd_array_sync(adapter, (u8 *)&end_cmd, 1, max_wating_ms);\n}\n#endif /* CONFIG_IOL_NEW_GENERATION */\n\n\n\n\n#endif /* CONFIG_IOL */\n"
  },
  {
    "path": "core/rtw_mem.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include <drv_types.h>\n#include <rtw_mem.h>\n\nMODULE_LICENSE(\"GPL\");\nMODULE_DESCRIPTION(\"Realtek Wireless Lan Driver\");\nMODULE_AUTHOR(\"Realtek Semiconductor Corp.\");\nMODULE_VERSION(\"DRIVERVERSION\");\n\nstruct sk_buff_head rtk_skb_mem_q;\nstruct u8 *rtk_buf_mem[NR_RECVBUFF];\n\nstruct u8\t*rtw_get_buf_premem(int index)\n{\n\tprintk(\"%s, rtk_buf_mem index : %d\\n\", __func__, index);\n\treturn rtk_buf_mem[index];\n}\n\nu16 rtw_rtkm_get_buff_size(void)\n{\n\treturn MAX_RTKM_RECVBUF_SZ;\n}\nEXPORT_SYMBOL(rtw_rtkm_get_buff_size);\n\nu8 rtw_rtkm_get_nr_recv_skb(void)\n{\n\treturn MAX_RTKM_NR_PREALLOC_RECV_SKB;\n}\nEXPORT_SYMBOL(rtw_rtkm_get_nr_recv_skb);\n\nstruct sk_buff *rtw_alloc_skb_premem(u16 in_size)\n{\n\tstruct sk_buff *skb = NULL;\n\n\tif (in_size > MAX_RTKM_RECVBUF_SZ) {\n\t\tpr_info(\"warning %s: driver buffer size(%d) > rtkm buffer size(%d)\\n\", __func__, in_size, MAX_RTKM_RECVBUF_SZ);\n\t\tWARN_ON(1);\n\t\treturn skb;\n\t}\n\n\tskb = skb_dequeue(&rtk_skb_mem_q);\n\n\tprintk(\"%s, rtk_skb_mem_q len : %d\\n\", __func__, skb_queue_len(&rtk_skb_mem_q));\n\n\treturn skb;\n}\nEXPORT_SYMBOL(rtw_alloc_skb_premem);\n\nint rtw_free_skb_premem(struct sk_buff *pskb)\n{\n\tif (!pskb)\n\t\treturn -1;\n\n\tif (skb_queue_len(&rtk_skb_mem_q) >= MAX_RTKM_NR_PREALLOC_RECV_SKB)\n\t\treturn -1;\n\n\tskb_queue_tail(&rtk_skb_mem_q, pskb);\n\n\tprintk(\"%s, rtk_skb_mem_q len : %d\\n\", __func__, skb_queue_len(&rtk_skb_mem_q));\n\n\treturn 0;\n}\nEXPORT_SYMBOL(rtw_free_skb_premem);\n\nstatic int __init rtw_mem_init(void)\n{\n\tint i;\n\tSIZE_PTR tmpaddr = 0;\n\tSIZE_PTR alignment = 0;\n\tstruct sk_buff *pskb = NULL;\n\n\tprintk(\"%s\\n\", __func__);\n\tpr_info(\"MAX_RTKM_NR_PREALLOC_RECV_SKB: %d\\n\", MAX_RTKM_NR_PREALLOC_RECV_SKB);\n\tpr_info(\"MAX_RTKM_RECVBUF_SZ: %d\\n\", MAX_RTKM_RECVBUF_SZ);\n\n#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX\n\tfor (i = 0; i < NR_RECVBUFF; i++)\n\t\trtk_buf_mem[i] = usb_buffer_alloc(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma);\n#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */\n\n\tskb_queue_head_init(&rtk_skb_mem_q);\n\n\tfor (i = 0; i < MAX_RTKM_NR_PREALLOC_RECV_SKB; i++) {\n\t\tpskb = __dev_alloc_skb(MAX_RTKM_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);\n\t\tif (pskb) {\n\t\t\ttmpaddr = (SIZE_PTR)pskb->data;\n\t\t\talignment = tmpaddr & (RECVBUFF_ALIGN_SZ - 1);\n\t\t\tskb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignment));\n\n\t\t\tskb_queue_tail(&rtk_skb_mem_q, pskb);\n\t\t} else\n\t\t\tprintk(\"%s, alloc skb memory fail!\\n\", __func__);\n\n\t\tpskb = NULL;\n\t}\n\n\tprintk(\"%s, rtk_skb_mem_q len : %d\\n\", __func__, skb_queue_len(&rtk_skb_mem_q));\n\n\treturn 0;\n\n}\n\nstatic void __exit rtw_mem_exit(void)\n{\n\tif (skb_queue_len(&rtk_skb_mem_q))\n\t\tprintk(\"%s, rtk_skb_mem_q len : %d\\n\", __func__, skb_queue_len(&rtk_skb_mem_q));\n\n\tskb_queue_purge(&rtk_skb_mem_q);\n\n\tprintk(\"%s\\n\", __func__);\n}\n\nmodule_init(rtw_mem_init);\nmodule_exit(rtw_mem_exit);\n"
  },
  {
    "path": "core/rtw_mi.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_MI_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\nvoid rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mi_state *iface_state = &dvobj->iface_state;\n\n\tiface_state->union_ch = ch;\n\tiface_state->union_bw = bw;\n\tiface_state->union_offset = offset;\n}\n\n#ifdef DBG_IFACE_STATUS\n#ifdef CONFIG_P2P\nstatic u8 _rtw_mi_p2p_listen_scan_chk(_adapter *adapter)\n{\n\tint i;\n\t_adapter *iface;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tu8 p2p_listen_scan_state = _FALSE;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_LISTEN) ||\n\t\t\trtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_SCAN)) {\n\t\t\tp2p_listen_scan_state = _TRUE;\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn p2p_listen_scan_state;\n}\n#endif\n#endif\n\nu8 rtw_mi_stayin_union_ch_chk(_adapter *adapter)\n{\n\tu8 rst = _TRUE;\n\tu8 u_ch, u_bw, u_offset;\n\tu8 o_ch, o_bw, o_offset;\n\n\tu_ch = rtw_mi_get_union_chan(adapter);\n\tu_bw = rtw_mi_get_union_bw(adapter);\n\tu_offset = rtw_mi_get_union_offset(adapter);\n\n\to_ch = rtw_get_oper_ch(adapter);\n\to_bw = rtw_get_oper_bw(adapter);\n\to_offset = rtw_get_oper_choffset(adapter);\n\n\tif ((u_ch != o_ch) || (u_bw != o_bw) || (u_offset != o_offset))\n\t\trst = _FALSE;\n\n\t#ifdef DBG_IFACE_STATUS\n\tif (rst == _FALSE) {\n\t\tRTW_ERR(\"%s Not stay in union channel\\n\", __func__);\n\t\tif (GET_HAL_DATA(adapter)->bScanInProcess == _TRUE)\n\t\t\tRTW_ERR(\"ScanInProcess\\n\");\n\t\t#ifdef CONFIG_P2P\n\t\tif (_rtw_mi_p2p_listen_scan_chk(adapter))\n\t\t\tRTW_ERR(\"P2P in listen or scan state\\n\");\n\t\t#endif\n\t\tRTW_ERR(\"union ch, bw, offset: %u,%u,%u\\n\", u_ch, u_bw, u_offset);\n\t\tRTW_ERR(\"oper ch, bw, offset: %u,%u,%u\\n\", o_ch, o_bw, o_offset);\n\t\tRTW_ERR(\"=========================\\n\");\n\t}\n\t#endif\n\treturn rst;\n}\n\nu8 rtw_mi_stayin_union_band_chk(_adapter *adapter)\n{\n\tu8 rst = _TRUE;\n\tu8 u_ch, o_ch;\n\tu8 u_band, o_band;\n\n\tu_ch = rtw_mi_get_union_chan(adapter);\n\to_ch = rtw_get_oper_ch(adapter);\n\tu_band = (u_ch > 14) ? BAND_ON_5G : BAND_ON_2_4G;\n\to_band = (o_ch > 14) ? BAND_ON_5G : BAND_ON_2_4G;\n\n\tif (u_ch != o_ch)\n\t\tif(u_band != o_band)\n\t\t\trst = _FALSE;\n\n\t#ifdef DBG_IFACE_STATUS\n\tif (rst == _FALSE)\n\t\tRTW_ERR(\"%s Not stay in union band\\n\", __func__);\n\t#endif\n\n\treturn rst;\n}\n\n/* Find union about ch, bw, ch_offset of all linked/linking interfaces */\nint rtw_mi_get_ch_setting_union_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, u8 *ch, u8 *bw, u8 *offset)\n{\n\t_adapter *iface;\n\tstruct mlme_ext_priv *mlmeext;\n\tint i;\n\tu8 ch_ret = 0;\n\tu8 bw_ret = CHANNEL_WIDTH_20;\n\tu8 offset_ret = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\tint num = 0;\n\n\tif (ch)\n\t\t*ch = 0;\n\tif (bw)\n\t\t*bw = CHANNEL_WIDTH_20;\n\tif (offset)\n\t\t*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (!iface || !(ifbmp & BIT(iface->iface_id)))\n\t\t\tcontinue;\n\n\t\tmlmeext = &iface->mlmeextpriv;\n\n\t\tif (!check_fwstate(&iface->mlmepriv, _FW_LINKED | _FW_UNDER_LINKING))\n\t\t\tcontinue;\n\n\t\tif (check_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING))\n\t\t\tcontinue;\n\n\t\tif (num == 0) {\n\t\t\tch_ret = mlmeext->cur_channel;\n\t\t\tbw_ret = mlmeext->cur_bwmode;\n\t\t\toffset_ret = mlmeext->cur_ch_offset;\n\t\t\tnum++;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (ch_ret != mlmeext->cur_channel) {\n\t\t\tnum = 0;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (bw_ret < mlmeext->cur_bwmode) {\n\t\t\tbw_ret = mlmeext->cur_bwmode;\n\t\t\toffset_ret = mlmeext->cur_ch_offset;\n\t\t} else if (bw_ret == mlmeext->cur_bwmode && offset_ret != mlmeext->cur_ch_offset) {\n\t\t\tnum = 0;\n\t\t\tbreak;\n\t\t}\n\n\t\tnum++;\n\t}\n\n\tif (num) {\n\t\tif (ch)\n\t\t\t*ch = ch_ret;\n\t\tif (bw)\n\t\t\t*bw = bw_ret;\n\t\tif (offset)\n\t\t\t*offset = offset_ret;\n\t}\n\n\treturn num;\n}\n\ninline int rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset)\n{\n\treturn rtw_mi_get_ch_setting_union_by_ifbmp(adapter_to_dvobj(adapter), 0xFF, ch, bw, offset);\n}\n\ninline int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset)\n{\n\treturn rtw_mi_get_ch_setting_union_by_ifbmp(adapter_to_dvobj(adapter), 0xFF & ~BIT(adapter->iface_id), ch, bw, offset);\n}\n\n/* For now, not return union_ch/bw/offset */\nvoid rtw_mi_status_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, struct mi_state *mstate)\n{\n\t_adapter *iface;\n\tint i;\n\n\t_rtw_memset(mstate, 0, sizeof(struct mi_state));\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (!iface || !(ifbmp & BIT(iface->iface_id)))\n\t\t\tcontinue;\n\n\t\tif (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) {\n\t\t\tMSTATE_STA_NUM(mstate)++;\n\t\t\tif (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) {\n\t\t\t\tMSTATE_STA_LD_NUM(mstate)++;\n\n\t\t\t\t#ifdef CONFIG_TDLS\n\t\t\t\tif (iface->tdlsinfo.link_established == _TRUE)\n\t\t\t\t\tMSTATE_TDLS_LD_NUM(mstate)++;\n\t\t\t\t#endif\n\t\t\t\t#ifdef CONFIG_P2P\n\t\t\t\tif (MLME_IS_GC(iface))\n\t\t\t\t\tMSTATE_P2P_GC_NUM(mstate)++;\n\t\t\t\t#endif\n\t\t\t}\n\t\t\tif (check_fwstate(&iface->mlmepriv, _FW_UNDER_LINKING) == _TRUE)\n\t\t\t\tMSTATE_STA_LG_NUM(mstate)++;\n\n#ifdef CONFIG_AP_MODE\n\t\t} else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE ) {\n\t\t\tif (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) {\n\t\t\t\tMSTATE_AP_NUM(mstate)++;\n\t\t\t\tif (iface->stapriv.asoc_sta_count > 2)\n\t\t\t\t\tMSTATE_AP_LD_NUM(mstate)++;\n\t\t\t\t#ifdef CONFIG_P2P\n\t\t\t\tif (MLME_IS_GO(iface))\n\t\t\t\t\tMSTATE_P2P_GO_NUM(mstate)++;\n\t\t\t\t#endif\n\t\t\t} else\n\t\t\t\tMSTATE_AP_STARTING_NUM(mstate)++;\n#endif\n\n\t\t} else if (check_fwstate(&iface->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE\n\t\t\t&& check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE\n\t\t) {\n\t\t\tMSTATE_ADHOC_NUM(mstate)++;\n\t\t\tif (iface->stapriv.asoc_sta_count > 2)\n\t\t\t\tMSTATE_ADHOC_LD_NUM(mstate)++;\n\n#ifdef CONFIG_RTW_MESH\n\t\t} else if (check_fwstate(&iface->mlmepriv, WIFI_MESH_STATE) == _TRUE\n\t\t\t&& check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE\n\t\t) {\n\t\t\tMSTATE_MESH_NUM(mstate)++;\n\t\t\tif (iface->stapriv.asoc_sta_count > 2)\n\t\t\t\tMSTATE_MESH_LD_NUM(mstate)++;\n#endif\n\n\t\t}\n\n\t\tif (check_fwstate(&iface->mlmepriv, WIFI_UNDER_WPS) == _TRUE)\n\t\t\tMSTATE_WPS_NUM(mstate)++;\n\n\t\tif (check_fwstate(&iface->mlmepriv, WIFI_SITE_MONITOR) == _TRUE) {\n\t\t\tMSTATE_SCAN_NUM(mstate)++;\n\n\t\t\tif (mlmeext_scan_state(&iface->mlmeextpriv) != SCAN_DISABLE\n\t\t\t\t&& mlmeext_scan_state(&iface->mlmeextpriv) != SCAN_BACK_OP)\n\t\t\t\tMSTATE_SCAN_ENTER_NUM(mstate)++;\n\t\t}\n\n#ifdef CONFIG_IOCTL_CFG80211\n\t\tif (rtw_cfg80211_get_is_mgmt_tx(iface))\n\t\t\tMSTATE_MGMT_TX_NUM(mstate)++;\n\t\t#ifdef CONFIG_P2P\n\t\tif (rtw_cfg80211_get_is_roch(iface) == _TRUE)\n\t\t\tMSTATE_ROCH_NUM(mstate)++;\n\t\t#endif\n#endif /* CONFIG_IOCTL_CFG80211 */\n#ifdef CONFIG_P2P\n\t\tif (MLME_IS_PD(iface))\n\t\t\tMSTATE_P2P_DV_NUM(mstate)++;\n#endif\n\t}\n}\n\ninline void rtw_mi_status(_adapter *adapter, struct mi_state *mstate)\n{\n\treturn rtw_mi_status_by_ifbmp(adapter_to_dvobj(adapter), 0xFF, mstate);\n}\n\ninline void rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate)\n{\n\treturn rtw_mi_status_by_ifbmp(adapter_to_dvobj(adapter), 0xFF & ~BIT(adapter->iface_id), mstate);\n}\n\ninline void rtw_mi_status_no_others(_adapter *adapter, struct mi_state *mstate)\n{\n\treturn rtw_mi_status_by_ifbmp(adapter_to_dvobj(adapter), BIT(adapter->iface_id), mstate);\n}\n\n/* For now, not handle union_ch/bw/offset */\ninline void rtw_mi_status_merge(struct mi_state *d, struct mi_state *a)\n{\n\td->sta_num += a->sta_num;\n\td->ld_sta_num += a->ld_sta_num;\n\td->lg_sta_num += a->lg_sta_num;\n#ifdef CONFIG_TDLS\n\td->ld_tdls_num += a->ld_tdls_num;\n#endif\n#ifdef CONFIG_AP_MODE\n\td->ap_num += a->ap_num;\n\td->ld_ap_num += a->ld_ap_num;\n#endif\n\td->adhoc_num += a->adhoc_num;\n\td->ld_adhoc_num += a->ld_adhoc_num;\n#ifdef CONFIG_RTW_MESH\n\td->mesh_num += a->mesh_num;\n\td->ld_mesh_num += a->ld_mesh_num;\n#endif\n\td->scan_num += a->scan_num;\n\td->scan_enter_num += a->scan_enter_num;\n\td->uwps_num += a->uwps_num;\n#ifdef CONFIG_IOCTL_CFG80211\n\t#ifdef CONFIG_P2P\n\td->roch_num += a->roch_num;\n\t#endif\n\td->mgmt_tx_num += a->mgmt_tx_num;\n#endif\n}\n\nvoid dump_mi_status(void *sel, struct dvobj_priv *dvobj)\n{\n\tRTW_PRINT_SEL(sel, \"== dvobj-iface_state ==\\n\");\n\tRTW_PRINT_SEL(sel, \"sta_num:%d\\n\", DEV_STA_NUM(dvobj));\n\tRTW_PRINT_SEL(sel, \"linking_sta_num:%d\\n\", DEV_STA_LG_NUM(dvobj));\n\tRTW_PRINT_SEL(sel, \"linked_sta_num:%d\\n\", DEV_STA_LD_NUM(dvobj));\n#ifdef CONFIG_TDLS\n\tRTW_PRINT_SEL(sel, \"linked_tdls_num:%d\\n\", DEV_TDLS_LD_NUM(dvobj));\n#endif\n#ifdef CONFIG_AP_MODE\n\tRTW_PRINT_SEL(sel, \"ap_num:%d\\n\", DEV_AP_NUM(dvobj));\n\tRTW_PRINT_SEL(sel, \"starting_ap_num:%d\\n\", DEV_AP_STARTING_NUM(dvobj));\n\tRTW_PRINT_SEL(sel, \"linked_ap_num:%d\\n\", DEV_AP_LD_NUM(dvobj));\n#endif\n\tRTW_PRINT_SEL(sel, \"adhoc_num:%d\\n\", DEV_ADHOC_NUM(dvobj));\n\tRTW_PRINT_SEL(sel, \"linked_adhoc_num:%d\\n\", DEV_ADHOC_LD_NUM(dvobj));\n#ifdef CONFIG_RTW_MESH\n\tRTW_PRINT_SEL(sel, \"mesh_num:%d\\n\", DEV_MESH_NUM(dvobj));\n\tRTW_PRINT_SEL(sel, \"linked_mesh_num:%d\\n\", DEV_MESH_LD_NUM(dvobj));\n#endif\n#ifdef CONFIG_P2P\n\tRTW_PRINT_SEL(sel, \"p2p_device_num:%d\\n\", DEV_P2P_DV_NUM(dvobj));\n\tRTW_PRINT_SEL(sel, \"p2p_gc_num:%d\\n\", DEV_P2P_GC_NUM(dvobj));\n\tRTW_PRINT_SEL(sel, \"p2p_go_num:%d\\n\", DEV_P2P_GO_NUM(dvobj));\n#endif\n\tRTW_PRINT_SEL(sel, \"scan_num:%d\\n\", DEV_SCAN_NUM(dvobj));\n\tRTW_PRINT_SEL(sel, \"under_wps_num:%d\\n\", DEV_WPS_NUM(dvobj));\n#if defined(CONFIG_IOCTL_CFG80211)\n\t#if defined(CONFIG_P2P)\n\tRTW_PRINT_SEL(sel, \"roch_num:%d\\n\", DEV_ROCH_NUM(dvobj));\n\t#endif\n\tRTW_PRINT_SEL(sel, \"mgmt_tx_num:%d\\n\", DEV_MGMT_TX_NUM(dvobj));\n#endif\n\tRTW_PRINT_SEL(sel, \"union_ch:%d\\n\", DEV_U_CH(dvobj));\n\tRTW_PRINT_SEL(sel, \"union_bw:%d\\n\", DEV_U_BW(dvobj));\n\tRTW_PRINT_SEL(sel, \"union_offset:%d\\n\", DEV_U_OFFSET(dvobj));\n\tRTW_PRINT_SEL(sel, \"================\\n\\n\");\n}\n\nvoid dump_dvobj_mi_status(void *sel, const char *fun_name, _adapter *adapter)\n{\n\tRTW_INFO(\"\\n[ %s ] call %s\\n\", fun_name, __func__);\n\tdump_mi_status(sel, adapter_to_dvobj(adapter));\n}\n\ninline void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state)\n{\n\t_adapter *adapter = container_of(pmlmepriv, _adapter, mlmepriv);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mi_state *iface_state = &dvobj->iface_state;\n\tstruct mi_state tmp_mstate;\n\tu8 u_ch, u_offset, u_bw;\n\n\tif (state == WIFI_MONITOR_STATE\n\t\t|| state == 0xFFFFFFFF\n\t)\n\t\treturn;\n\n\tif (0)\n\t\tRTW_INFO(\"%s => will change or clean state to 0x%08x\\n\", __func__, state);\n\n\trtw_mi_status(adapter, &tmp_mstate);\n\t_rtw_memcpy(iface_state, &tmp_mstate, sizeof(struct mi_state));\n\n\tif (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset))\n\t\trtw_mi_update_union_chan_inf(adapter , u_ch, u_offset , u_bw);\n\telse {\n\t\tif (0) {\n\t\t\tdump_adapters_status(RTW_DBGDUMP , dvobj);\n\t\t\tRTW_INFO(\"%s-[ERROR] cannot get union channel\\n\", __func__);\n\t\t\trtw_warn_on(1);\n\t\t}\n\t}\n\n#ifdef DBG_IFACE_STATUS\n\tDBG_IFACE_STATUS_DUMP(adapter);\n#endif\n}\nu8 rtw_mi_check_status(_adapter *adapter, u8 type)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mi_state *iface_state = &dvobj->iface_state;\n\tu8 ret = _FALSE;\n\n#ifdef DBG_IFACE_STATUS\n\tDBG_IFACE_STATUS_DUMP(adapter);\n\tRTW_INFO(\"%s-\"ADPT_FMT\" check type:%d\\n\", __func__, ADPT_ARG(adapter), type);\n#endif\n\n\tswitch (type) {\n\tcase MI_LINKED:\n\t\tif (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_NUM(iface_state) || MSTATE_ADHOC_NUM(iface_state) || MSTATE_MESH_NUM(iface_state)) /*check_fwstate(&iface->mlmepriv, _FW_LINKED)*/\n\t\t\tret = _TRUE;\n\t\tbreak;\n\tcase MI_ASSOC:\n\t\tif (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_LD_NUM(iface_state) || MSTATE_ADHOC_LD_NUM(iface_state) || MSTATE_MESH_LD_NUM(iface_state))\n\t\t\tret = _TRUE;\n\t\tbreak;\n\tcase MI_UNDER_WPS:\n\t\tif (MSTATE_WPS_NUM(iface_state))\n\t\t\tret = _TRUE;\n\t\tbreak;\n\n\tcase MI_AP_MODE:\n\t\tif (MSTATE_AP_NUM(iface_state))\n\t\t\tret = _TRUE;\n\t\tbreak;\n\tcase MI_AP_ASSOC:\n\t\tif (MSTATE_AP_LD_NUM(iface_state))\n\t\t\tret = _TRUE;\n\t\tbreak;\n\n\tcase MI_ADHOC:\n\t\tif (MSTATE_ADHOC_NUM(iface_state))\n\t\t\tret = _TRUE;\n\t\tbreak;\n\tcase MI_ADHOC_ASSOC:\n\t\tif (MSTATE_ADHOC_LD_NUM(iface_state))\n\t\t\tret = _TRUE;\n\t\tbreak;\n\n#ifdef CONFIG_RTW_MESH\n\tcase MI_MESH:\n\t\tif (MSTATE_MESH_NUM(iface_state))\n\t\t\tret = _TRUE;\n\t\tbreak;\n\tcase MI_MESH_ASSOC:\n\t\tif (MSTATE_MESH_LD_NUM(iface_state))\n\t\t\tret = _TRUE;\n\t\tbreak;\n#endif\n\n\tcase MI_STA_NOLINK: /* this is misleading, but not used now */\n\t\tif (MSTATE_STA_NUM(iface_state) && (!(MSTATE_STA_LD_NUM(iface_state) || MSTATE_STA_LG_NUM(iface_state))))\n\t\t\tret = _TRUE;\n\t\tbreak;\n\tcase MI_STA_LINKED:\n\t\tif (MSTATE_STA_LD_NUM(iface_state))\n\t\t\tret = _TRUE;\n\t\tbreak;\n\tcase MI_STA_LINKING:\n\t\tif (MSTATE_STA_LG_NUM(iface_state))\n\t\t\tret = _TRUE;\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\treturn ret;\n}\n\n/*\n* return value : 0 is failed or have not interface meet condition\n* return value : !0 is success or interface numbers which meet condition\n* return value of ops_func must be _TRUE or _FALSE\n*/\nstatic u8 _rtw_mi_process(_adapter *padapter, bool exclude_self,\n\t\t  void *data, u8(*ops_func)(_adapter *padapter, void *data))\n{\n\tint i;\n\t_adapter *iface;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\tu8 ret = 0;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif ((iface) && rtw_is_adapter_up(iface)) {\n\n\t\t\tif ((exclude_self) && (iface == padapter))\n\t\t\t\tcontinue;\n\n\t\t\tif (ops_func)\n\t\t\t\tif (_TRUE == ops_func(iface, data))\n\t\t\t\t\tret++;\n\t\t}\n\t}\n\treturn ret;\n}\nstatic u8 _rtw_mi_process_without_schk(_adapter *padapter, bool exclude_self,\n\t\t  void *data, u8(*ops_func)(_adapter *padapter, void *data))\n{\n\tint i;\n\t_adapter *iface;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\tu8 ret = 0;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface) {\n\t\t\tif ((exclude_self) && (iface == padapter))\n\t\t\t\tcontinue;\n\n\t\t\tif (ops_func)\n\t\t\t\tif (ops_func(iface, data) == _TRUE)\n\t\t\t\t\tret++;\n\t\t}\n\t}\n\treturn ret;\n}\n\nstatic u8 _rtw_mi_netif_caroff_qstop(_adapter *padapter, void *data)\n{\n\tstruct net_device *pnetdev = padapter->pnetdev;\n\n\trtw_netif_carrier_off(pnetdev);\n\trtw_netif_stop_queue(pnetdev);\n\treturn _TRUE;\n}\nu8 rtw_mi_netif_caroff_qstop(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_caroff_qstop);\n}\nu8 rtw_mi_buddy_netif_caroff_qstop(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_caroff_qstop);\n}\n\nstatic u8 _rtw_mi_netif_caron_qstart(_adapter *padapter, void *data)\n{\n\tstruct net_device *pnetdev = padapter->pnetdev;\n\n\trtw_netif_carrier_on(pnetdev);\n\trtw_netif_start_queue(pnetdev);\n\treturn _TRUE;\n}\nu8 rtw_mi_netif_caron_qstart(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_caron_qstart);\n}\nu8 rtw_mi_buddy_netif_caron_qstart(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_caron_qstart);\n}\n\nstatic u8 _rtw_mi_netif_stop_queue(_adapter *padapter, void *data)\n{\n\tstruct net_device *pnetdev = padapter->pnetdev;\n\n\trtw_netif_stop_queue(pnetdev);\n\treturn _TRUE;\n}\nu8 rtw_mi_netif_stop_queue(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_stop_queue);\n}\nu8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_stop_queue);\n}\n\nstatic u8 _rtw_mi_netif_wake_queue(_adapter *padapter, void *data)\n{\n\tstruct net_device *pnetdev = padapter->pnetdev;\n\n\tif (pnetdev)\n\t\trtw_netif_wake_queue(pnetdev);\n\treturn _TRUE;\n}\nu8 rtw_mi_netif_wake_queue(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_wake_queue);\n}\nu8 rtw_mi_buddy_netif_wake_queue(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_wake_queue);\n}\n\nstatic u8 _rtw_mi_netif_carrier_on(_adapter *padapter, void *data)\n{\n\tstruct net_device *pnetdev = padapter->pnetdev;\n\n\tif (pnetdev)\n\t\trtw_netif_carrier_on(pnetdev);\n\treturn _TRUE;\n}\nu8 rtw_mi_netif_carrier_on(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_carrier_on);\n}\nu8 rtw_mi_buddy_netif_carrier_on(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_carrier_on);\n}\n\nstatic u8 _rtw_mi_netif_carrier_off(_adapter *padapter, void *data)\n{\n\tstruct net_device *pnetdev = padapter->pnetdev;\n\n\tif (pnetdev)\n\t\trtw_netif_carrier_off(pnetdev);\n\treturn _TRUE;\n}\nu8 rtw_mi_netif_carrier_off(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_carrier_off);\n}\nu8 rtw_mi_buddy_netif_carrier_off(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_carrier_off);\n}\n\nstatic u8 _rtw_mi_scan_abort(_adapter *adapter, void *data)\n{\n\tbool bwait = *(bool *)data;\n\n\tif (bwait)\n\t\trtw_scan_abort(adapter);\n\telse\n\t\trtw_scan_abort_no_wait(adapter);\n\n\treturn _TRUE;\n}\nvoid rtw_mi_scan_abort(_adapter *adapter, bool bwait)\n{\n\tbool in_data = bwait;\n\n\t_rtw_mi_process(adapter, _FALSE, &in_data, _rtw_mi_scan_abort);\n\n}\nvoid rtw_mi_buddy_scan_abort(_adapter *adapter, bool bwait)\n{\n\tbool in_data = bwait;\n\n\t_rtw_mi_process(adapter, _TRUE, &in_data, _rtw_mi_scan_abort);\n}\n\nstatic u32 _rtw_mi_start_drv_threads(_adapter *adapter, bool exclude_self)\n{\n\tint i;\n\t_adapter *iface = NULL;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tu32 _status = _SUCCESS;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface) {\n\t\t\tif ((exclude_self) && (iface == adapter))\n\t\t\t\tcontinue;\n\t\t\tif (rtw_start_drv_threads(iface) == _FAIL) {\n\t\t\t\t_status = _FAIL;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\treturn _status;\n}\nu32 rtw_mi_start_drv_threads(_adapter *adapter)\n{\n\treturn _rtw_mi_start_drv_threads(adapter, _FALSE);\n}\nu32 rtw_mi_buddy_start_drv_threads(_adapter *adapter)\n{\n\treturn _rtw_mi_start_drv_threads(adapter, _TRUE);\n}\n\nstatic void _rtw_mi_stop_drv_threads(_adapter *adapter, bool exclude_self)\n{\n\tint i;\n\t_adapter *iface = NULL;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface) {\n\t\t\tif ((exclude_self) && (iface == adapter))\n\t\t\t\tcontinue;\n\t\t\trtw_stop_drv_threads(iface);\n\t\t}\n\t}\n}\nvoid rtw_mi_stop_drv_threads(_adapter *adapter)\n{\n\t_rtw_mi_stop_drv_threads(adapter, _FALSE);\n}\nvoid rtw_mi_buddy_stop_drv_threads(_adapter *adapter)\n{\n\t_rtw_mi_stop_drv_threads(adapter, _TRUE);\n}\n\nstatic u8 _rtw_mi_cancel_all_timer(_adapter *adapter, void *data)\n{\n\trtw_cancel_all_timer(adapter);\n\treturn _TRUE;\n}\nvoid rtw_mi_cancel_all_timer(_adapter *adapter)\n{\n\t_rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_cancel_all_timer);\n}\nvoid rtw_mi_buddy_cancel_all_timer(_adapter *adapter)\n{\n\t_rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_cancel_all_timer);\n}\n\nstatic u8 _rtw_mi_reset_drv_sw(_adapter *adapter, void *data)\n{\n\trtw_reset_drv_sw(adapter);\n\treturn _TRUE;\n}\nvoid rtw_mi_reset_drv_sw(_adapter *adapter)\n{\n\t_rtw_mi_process_without_schk(adapter, _FALSE, NULL, _rtw_mi_reset_drv_sw);\n}\nvoid rtw_mi_buddy_reset_drv_sw(_adapter *adapter)\n{\n\t_rtw_mi_process_without_schk(adapter, _TRUE, NULL, _rtw_mi_reset_drv_sw);\n}\n\nstatic u8 _rtw_mi_intf_start(_adapter *adapter, void *data)\n{\n\trtw_intf_start(adapter);\n\treturn _TRUE;\n}\nvoid rtw_mi_intf_start(_adapter *adapter)\n{\n\t_rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_intf_start);\n}\nvoid rtw_mi_buddy_intf_start(_adapter *adapter)\n{\n\t_rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_intf_start);\n}\n\nstatic u8 _rtw_mi_intf_stop(_adapter *adapter, void *data)\n{\n\trtw_intf_stop(adapter);\n\treturn _TRUE;\n}\nvoid rtw_mi_intf_stop(_adapter *adapter)\n{\n\t_rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_intf_stop);\n}\nvoid rtw_mi_buddy_intf_stop(_adapter *adapter)\n{\n\t_rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_intf_stop);\n}\n\n#ifdef CONFIG_NEW_NETDEV_HDL\nu8 rtw_mi_hal_iface_init(_adapter *padapter)\n{\n\tint i;\n\t_adapter *iface;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\tu8 ret = _TRUE;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface && iface->netif_up)\n\t\t\trtw_hal_iface_init(padapter);\n\t}\n\treturn ret;\n}\n#endif\n\nstatic u8 _rtw_mi_suspend_free_assoc_resource(_adapter *padapter, void *data)\n{\n\treturn rtw_suspend_free_assoc_resource(padapter);\n}\nvoid rtw_mi_suspend_free_assoc_resource(_adapter *adapter)\n{\n\t_rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_suspend_free_assoc_resource);\n}\nvoid rtw_mi_buddy_suspend_free_assoc_resource(_adapter *adapter)\n{\n\t_rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_suspend_free_assoc_resource);\n}\n\nstatic u8 _rtw_mi_is_scan_deny(_adapter *adapter, void *data)\n{\n\treturn rtw_is_scan_deny(adapter);\n}\n\nu8 rtw_mi_is_scan_deny(_adapter *adapter)\n{\n\treturn _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_is_scan_deny);\n\n}\nu8 rtw_mi_buddy_is_scan_deny(_adapter *adapter)\n{\n\treturn _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_is_scan_deny);\n}\n\n#ifdef CONFIG_SET_SCAN_DENY_TIMER\nstatic u8 _rtw_mi_set_scan_deny(_adapter *adapter, void *data)\n{\n\tu32 ms = *(u32 *)data;\n\n\trtw_set_scan_deny(adapter, ms);\n\treturn _TRUE;\n}\nvoid rtw_mi_set_scan_deny(_adapter *adapter, u32 ms)\n{\n\tu32 in_data = ms;\n\n\t_rtw_mi_process(adapter, _FALSE, &in_data, _rtw_mi_set_scan_deny);\n}\nvoid rtw_mi_buddy_set_scan_deny(_adapter *adapter, u32 ms)\n{\n\tu32 in_data = ms;\n\n\t_rtw_mi_process(adapter, _TRUE, &in_data, _rtw_mi_set_scan_deny);\n}\n#endif /*CONFIG_SET_SCAN_DENY_TIMER*/\n\nstatic u8 _rtw_mi_beacon_update(_adapter *padapter, void *data)\n{\n\tif (!MLME_IS_STA(padapter)\n\t    && check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE) {\n\t\tRTW_INFO(ADPT_FMT\" - update_beacon\\n\", ADPT_ARG(padapter));\n\t\tupdate_beacon(padapter, 0xFF, NULL, _TRUE, 0);\n\t}\n\treturn _TRUE;\n}\n\nvoid rtw_mi_beacon_update(_adapter *padapter)\n{\n\t_rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_beacon_update);\n}\n\nvoid rtw_mi_buddy_beacon_update(_adapter *padapter)\n{\n\t_rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_beacon_update);\n}\n\nstatic u8 _rtw_mi_hal_dump_macaddr(_adapter *padapter, void *data)\n{\n\tu8 mac_addr[ETH_ALEN] = {0};\n\n\trtw_hal_get_hwreg(padapter, HW_VAR_MAC_ADDR, mac_addr);\n\tRTW_INFO(ADPT_FMT\"MAC Address =\"MAC_FMT\"\\n\", ADPT_ARG(padapter), MAC_ARG(mac_addr));\n\treturn _TRUE;\n}\nvoid rtw_mi_hal_dump_macaddr(_adapter *padapter)\n{\n\t_rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_hal_dump_macaddr);\n}\nvoid rtw_mi_buddy_hal_dump_macaddr(_adapter *padapter)\n{\n\t_rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_hal_dump_macaddr);\n}\n\n#ifdef CONFIG_PCI_HCI\nstatic u8 _rtw_mi_xmit_tasklet_schedule(_adapter *padapter, void *data)\n{\n\tif (rtw_txframes_pending(padapter)) {\n\t\t/* try to deal with the pending packets */\n\t\ttasklet_hi_schedule(&(padapter->xmitpriv.xmit_tasklet));\n\t}\n\treturn _TRUE;\n}\nvoid rtw_mi_xmit_tasklet_schedule(_adapter *padapter)\n{\n\t_rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_xmit_tasklet_schedule);\n}\nvoid rtw_mi_buddy_xmit_tasklet_schedule(_adapter *padapter)\n{\n\t_rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_xmit_tasklet_schedule);\n}\n#endif\n\nu8 _rtw_mi_busy_traffic_check(_adapter *padapter, void *data)\n{\n\tu32 passtime;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tbool check_sc_interval = *(bool *)data;\n\n\tif (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE) {\n\t\tif (check_sc_interval) {\n\t\t\t/* Miracast can't do AP scan*/\n\t\t\tpasstime = rtw_get_passing_time_ms(pmlmepriv->lastscantime);\n\t\t\tif (passtime > BUSY_TRAFFIC_SCAN_DENY_PERIOD) {\n\t\t\t\tRTW_INFO(ADPT_FMT\" bBusyTraffic == _TRUE\\n\", ADPT_ARG(padapter));\n\t\t\t\treturn _TRUE;\n\t\t\t}\n\t\t} else\n\t\t\treturn _TRUE;\n\t}\n\n\treturn _FALSE;\n}\n\nu8 rtw_mi_busy_traffic_check(_adapter *padapter, bool check_sc_interval)\n{\n\tbool in_data = check_sc_interval;\n\n\treturn _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_busy_traffic_check);\n}\nu8 rtw_mi_buddy_busy_traffic_check(_adapter *padapter, bool check_sc_interval)\n{\n\tbool in_data = check_sc_interval;\n\n\treturn _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_busy_traffic_check);\n}\nstatic u8 _rtw_mi_check_mlmeinfo_state(_adapter *padapter, void *data)\n{\n\tu32 state = *(u32 *)data;\n\tstruct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv;\n\n\t/*if (mlmeext_msr(mlmeext) == state)*/\n\tif (check_mlmeinfo_state(mlmeext, state))\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\n\nu8 rtw_mi_check_mlmeinfo_state(_adapter *padapter, u32 state)\n{\n\tu32 in_data = state;\n\n\treturn _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_check_mlmeinfo_state);\n}\n\nu8 rtw_mi_buddy_check_mlmeinfo_state(_adapter *padapter, u32 state)\n{\n\tu32 in_data = state;\n\n\treturn _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_check_mlmeinfo_state);\n}\n\n/*#define DBG_DUMP_FW_STATE*/\n#ifdef DBG_DUMP_FW_STATE\nstatic void rtw_dbg_dump_fwstate(_adapter *padapter, sint state)\n{\n\tu8 buf[32] = {0};\n\n\tif (state & WIFI_FW_NULL_STATE) {\n\t\t_rtw_memset(buf, 0, 32);\n\t\tsprintf(buf, \"WIFI_FW_NULL_STATE\");\n\t\tRTW_INFO(FUNC_ADPT_FMT\"fwstate-%s\\n\", FUNC_ADPT_ARG(padapter), buf);\n\t}\n\n\tif (state & _FW_LINKED) {\n\t\t_rtw_memset(buf, 0, 32);\n\t\tsprintf(buf, \"_FW_LINKED\");\n\t\tRTW_INFO(FUNC_ADPT_FMT\"fwstate-%s\\n\", FUNC_ADPT_ARG(padapter), buf);\n\t}\n\n\tif (state & _FW_UNDER_LINKING) {\n\t\t_rtw_memset(buf, 0, 32);\n\t\tsprintf(buf, \"_FW_UNDER_LINKING\");\n\t\tRTW_INFO(FUNC_ADPT_FMT\"fwstate-%s\\n\", FUNC_ADPT_ARG(padapter), buf);\n\t}\n\n\tif (state & _FW_UNDER_SURVEY) {\n\t\t_rtw_memset(buf, 0, 32);\n\t\tsprintf(buf, \"_FW_UNDER_SURVEY\");\n\t\tRTW_INFO(FUNC_ADPT_FMT\"fwstate-%s\\n\", FUNC_ADPT_ARG(padapter), buf);\n\t}\n}\n#endif\n\nstatic u8 _rtw_mi_check_fwstate(_adapter *padapter, void *data)\n{\n\tu8 ret = _FALSE;\n\n\tsint state = *(sint *)data;\n\n\tif ((state == WIFI_FW_NULL_STATE) &&\n\t    (padapter->mlmepriv.fw_state == WIFI_FW_NULL_STATE))\n\t\tret = _TRUE;\n\telse if (_TRUE == check_fwstate(&padapter->mlmepriv, state))\n\t\tret = _TRUE;\n#ifdef DBG_DUMP_FW_STATE\n\tif (ret)\n\t\trtw_dbg_dump_fwstate(padapter, state);\n#endif\n\treturn ret;\n}\nu8 rtw_mi_check_fwstate(_adapter *padapter, sint state)\n{\n\tsint in_data = state;\n\n\treturn _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_check_fwstate);\n}\nu8 rtw_mi_buddy_check_fwstate(_adapter *padapter, sint state)\n{\n\tsint in_data = state;\n\n\treturn _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_check_fwstate);\n}\n\nstatic u8 _rtw_mi_traffic_statistics(_adapter *padapter , void *data)\n{\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\n\t/* Tx */\n\tpdvobjpriv->traffic_stat.tx_bytes += padapter->xmitpriv.tx_bytes;\n\tpdvobjpriv->traffic_stat.tx_pkts += padapter->xmitpriv.tx_pkts;\n\tpdvobjpriv->traffic_stat.tx_drop += padapter->xmitpriv.tx_drop;\n\n\t/* Rx */\n\tpdvobjpriv->traffic_stat.rx_bytes += padapter->recvpriv.rx_bytes;\n\tpdvobjpriv->traffic_stat.rx_pkts += padapter->recvpriv.rx_pkts;\n\tpdvobjpriv->traffic_stat.rx_drop += padapter->recvpriv.rx_drop;\n\treturn _TRUE;\n}\nu8 rtw_mi_traffic_statistics(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_traffic_statistics);\n}\n\nstatic u8 _rtw_mi_check_miracast_enabled(_adapter *padapter , void *data)\n{\n\treturn is_miracast_enabled(padapter);\n}\nu8 rtw_mi_check_miracast_enabled(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_check_miracast_enabled);\n}\n\n#ifdef CONFIG_XMIT_THREAD_MODE\nstatic u8 _rtw_mi_check_pending_xmitbuf(_adapter *padapter , void *data)\n{\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\n\treturn check_pending_xmitbuf(pxmitpriv);\n}\nu8 rtw_mi_check_pending_xmitbuf(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_check_pending_xmitbuf);\n}\nu8 rtw_mi_buddy_check_pending_xmitbuf(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_check_pending_xmitbuf);\n}\n#endif\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\nstatic u8 _rtw_mi_dequeue_writeport(_adapter *padapter , bool exclude_self)\n{\n\tint i;\n\tu8\tqueue_empty = _TRUE;\n\t_adapter *iface;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif ((iface) && rtw_is_adapter_up(iface)) {\n\n\t\t\tif ((exclude_self) && (iface == padapter))\n\t\t\t\tcontinue;\n\n\t\t\tqueue_empty &= _dequeue_writeport(iface);\n\t\t}\n\t}\n\treturn queue_empty;\n}\nu8 rtw_mi_dequeue_writeport(_adapter *padapter)\n{\n\treturn _rtw_mi_dequeue_writeport(padapter, _FALSE);\n}\nu8 rtw_mi_buddy_dequeue_writeport(_adapter *padapter)\n{\n\treturn _rtw_mi_dequeue_writeport(padapter, _TRUE);\n}\n#endif\nstatic void _rtw_mi_adapter_reset(_adapter *padapter , u8 exclude_self)\n{\n\tint i;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tif (dvobj->padapters[i]) {\n\t\t\tif ((exclude_self) && (dvobj->padapters[i] == padapter))\n\t\t\t\tcontinue;\n\t\t\tdvobj->padapters[i] = NULL;\n\t\t}\n\t}\n}\n\nvoid rtw_mi_adapter_reset(_adapter *padapter)\n{\n\t_rtw_mi_adapter_reset(padapter, _FALSE);\n}\n\nvoid rtw_mi_buddy_adapter_reset(_adapter *padapter)\n{\n\t_rtw_mi_adapter_reset(padapter, _TRUE);\n}\n\nstatic u8 _rtw_mi_dynamic_check_timer_handlder(_adapter *adapter, void *data)\n{\n\trtw_iface_dynamic_check_timer_handlder(adapter);\n\treturn _TRUE;\n}\nu8 rtw_mi_dynamic_check_timer_handlder(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_dynamic_check_timer_handlder);\n}\nu8 rtw_mi_buddy_dynamic_check_timer_handlder(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_dynamic_check_timer_handlder);\n}\n\nstatic u8 _rtw_mi_dynamic_chk_wk_hdl(_adapter *adapter, void *data)\n{\n\trtw_iface_dynamic_chk_wk_hdl(adapter);\n\treturn _TRUE;\n}\nu8 rtw_mi_dynamic_chk_wk_hdl(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_dynamic_chk_wk_hdl);\n}\nu8 rtw_mi_buddy_dynamic_chk_wk_hdl(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_dynamic_chk_wk_hdl);\n}\n\nstatic u8 _rtw_mi_os_xmit_schedule(_adapter *adapter, void *data)\n{\n\trtw_os_xmit_schedule(adapter);\n\treturn _TRUE;\n}\nu8 rtw_mi_os_xmit_schedule(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_os_xmit_schedule);\n}\nu8 rtw_mi_buddy_os_xmit_schedule(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_os_xmit_schedule);\n}\n\nstatic u8 _rtw_mi_report_survey_event(_adapter *adapter, void *data)\n{\n\tunion recv_frame *precv_frame = (union recv_frame *)data;\n\n\treport_survey_event(adapter, precv_frame);\n\treturn _TRUE;\n}\nu8 rtw_mi_report_survey_event(_adapter *padapter, union recv_frame *precv_frame)\n{\n\treturn _rtw_mi_process(padapter, _FALSE, precv_frame, _rtw_mi_report_survey_event);\n}\nu8 rtw_mi_buddy_report_survey_event(_adapter *padapter, union recv_frame *precv_frame)\n{\n\treturn _rtw_mi_process(padapter, _TRUE, precv_frame, _rtw_mi_report_survey_event);\n}\n\nstatic u8 _rtw_mi_sreset_adapter_hdl(_adapter *adapter, void *data)\n{\n\tu8 bstart = *(u8 *)data;\n\n\tif (bstart)\n\t\tsreset_start_adapter(adapter);\n\telse\n\t\tsreset_stop_adapter(adapter);\n\treturn _TRUE;\n}\nu8 rtw_mi_sreset_adapter_hdl(_adapter *padapter, u8 bstart)\n{\n\tu8 in_data = bstart;\n\n\treturn _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_sreset_adapter_hdl);\n}\nu8 rtw_mi_buddy_sreset_adapter_hdl(_adapter *padapter, u8 bstart)\n{\n\tu8 in_data = bstart;\n\n\treturn _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_sreset_adapter_hdl);\n}\nstatic u8 _rtw_mi_tx_beacon_hdl(_adapter *adapter, void *data)\n{\n\tif ((MLME_IS_AP(adapter) || MLME_IS_MESH(adapter))\n\t\t&& check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE\n\t) {\n\t\tadapter->mlmepriv.update_bcn = _TRUE;\n#ifndef CONFIG_INTERRUPT_BASED_TXBCN\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_PCI_BCN_POLLING)\n\t\ttx_beacon_hdl(adapter, NULL);\n#endif\n#endif\n\t}\n\treturn _TRUE;\n}\nu8 rtw_mi_tx_beacon_hdl(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_tx_beacon_hdl);\n}\nu8 rtw_mi_buddy_tx_beacon_hdl(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_sreset_adapter_hdl);\n}\n\nstatic u8 _rtw_mi_set_tx_beacon_cmd(_adapter *adapter, void *data)\n{\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\n\tif (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {\n\t\tif (pmlmepriv->update_bcn == _TRUE)\n\t\t\tset_tx_beacon_cmd(adapter, 0);\n\t}\n\treturn _TRUE;\n}\nu8 rtw_mi_set_tx_beacon_cmd(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_set_tx_beacon_cmd);\n}\nu8 rtw_mi_buddy_set_tx_beacon_cmd(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_set_tx_beacon_cmd);\n}\n\n#ifdef CONFIG_P2P\nstatic u8 _rtw_mi_p2p_chk_state(_adapter *adapter, void *data)\n{\n\tstruct wifidirect_info *pwdinfo = &(adapter->wdinfo);\n\tenum P2P_STATE state = *(enum P2P_STATE *)data;\n\n\treturn rtw_p2p_chk_state(pwdinfo, state);\n}\nu8 rtw_mi_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state)\n{\n\tu8 in_data = p2p_state;\n\n\treturn _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_p2p_chk_state);\n}\nu8 rtw_mi_buddy_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state)\n{\n\tu8 in_data  = p2p_state;\n\n\treturn _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_p2p_chk_state);\n}\nstatic u8 _rtw_mi_stay_in_p2p_mode(_adapter *adapter, void *data)\n{\n\tstruct wifidirect_info *pwdinfo = &(adapter->wdinfo);\n\n\tif (rtw_p2p_role(pwdinfo) != P2P_ROLE_DISABLE)\n\t\treturn _TRUE;\n\treturn _FALSE;\n}\nu8 rtw_mi_stay_in_p2p_mode(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_stay_in_p2p_mode);\n}\nu8 rtw_mi_buddy_stay_in_p2p_mode(_adapter *padapter)\n{\n\treturn _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_stay_in_p2p_mode);\n}\n#endif /*CONFIG_P2P*/\n\n_adapter *rtw_get_iface_by_id(_adapter *padapter, u8 iface_id)\n{\n\t_adapter *iface = NULL;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\tif ((padapter == NULL) || (iface_id >= CONFIG_IFACE_NUMBER)) {\n\t\trtw_warn_on(1);\n\t\treturn iface;\n\t}\n\n\treturn  dvobj->padapters[iface_id];\n}\n\n_adapter *rtw_get_iface_by_macddr(_adapter *padapter, const u8 *mac_addr)\n{\n\tint i;\n\t_adapter *iface = NULL;\n\tu8 bmatch = _FALSE;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif ((iface) && (_rtw_memcmp(mac_addr, adapter_mac_addr(iface), ETH_ALEN))) {\n\t\t\tbmatch = _TRUE;\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (bmatch)\n\t\treturn iface;\n\telse\n\t\treturn NULL;\n}\n\n_adapter *rtw_get_iface_by_hwport(_adapter *padapter, u8 hw_port)\n{\n\tint i;\n\t_adapter *iface = NULL;\n\tu8 bmatch = _FALSE;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif ((iface) && (hw_port == iface->hw_port)) {\n\t\t\tbmatch = _TRUE;\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (bmatch)\n\t\treturn iface;\n\telse\n\t\treturn NULL;\n}\n\n/*#define CONFIG_SKB_ALLOCATED*/\n#define DBG_SKB_PROCESS\n#ifdef DBG_SKB_PROCESS\nvoid rtw_dbg_skb_process(_adapter *padapter, union recv_frame *precvframe, union recv_frame *pcloneframe)\n{\n\t_pkt *pkt_copy, *pkt_org;\n\n\tpkt_org = precvframe->u.hdr.pkt;\n\tpkt_copy = pcloneframe->u.hdr.pkt;\n\t/*\n\t\tRTW_INFO(\"%s ===== ORG SKB =====\\n\", __func__);\n\t\tRTW_INFO(\" SKB head(%p)\\n\", pkt_org->head);\n\t\tRTW_INFO(\" SKB data(%p)\\n\", pkt_org->data);\n\t\tRTW_INFO(\" SKB tail(%p)\\n\", pkt_org->tail);\n\t\tRTW_INFO(\" SKB end(%p)\\n\", pkt_org->end);\n\n\t\tRTW_INFO(\" recv frame head(%p)\\n\", precvframe->u.hdr.rx_head);\n\t\tRTW_INFO(\" recv frame data(%p)\\n\", precvframe->u.hdr.rx_data);\n\t\tRTW_INFO(\" recv frame tail(%p)\\n\", precvframe->u.hdr.rx_tail);\n\t\tRTW_INFO(\" recv frame end(%p)\\n\", precvframe->u.hdr.rx_end);\n\n\t\tRTW_INFO(\"%s ===== COPY SKB =====\\n\", __func__);\n\t\tRTW_INFO(\" SKB head(%p)\\n\", pkt_copy->head);\n\t\tRTW_INFO(\" SKB data(%p)\\n\", pkt_copy->data);\n\t\tRTW_INFO(\" SKB tail(%p)\\n\", pkt_copy->tail);\n\t\tRTW_INFO(\" SKB end(%p)\\n\", pkt_copy->end);\n\n\t\tRTW_INFO(\" recv frame head(%p)\\n\", pcloneframe->u.hdr.rx_head);\n\t\tRTW_INFO(\" recv frame data(%p)\\n\", pcloneframe->u.hdr.rx_data);\n\t\tRTW_INFO(\" recv frame tail(%p)\\n\", pcloneframe->u.hdr.rx_tail);\n\t\tRTW_INFO(\" recv frame end(%p)\\n\", pcloneframe->u.hdr.rx_end);\n\t*/\n\t/*\n\t\tRTW_INFO(\"%s => recv_frame adapter(%p,%p)\\n\", __func__, precvframe->u.hdr.adapter, pcloneframe->u.hdr.adapter);\n\t\tRTW_INFO(\"%s => recv_frame dev(%p,%p)\\n\", __func__, pkt_org->dev , pkt_copy->dev);\n\t\tRTW_INFO(\"%s => recv_frame len(%d,%d)\\n\", __func__, precvframe->u.hdr.len, pcloneframe->u.hdr.len);\n\t*/\n\tif (precvframe->u.hdr.len != pcloneframe->u.hdr.len)\n\t\tRTW_INFO(\"%s [WARN]  recv_frame length(%d:%d) compare failed\\n\", __func__, precvframe->u.hdr.len, pcloneframe->u.hdr.len);\n\n\tif (_rtw_memcmp(&precvframe->u.hdr.attrib, &pcloneframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib)) == _FALSE)\n\t\tRTW_INFO(\"%s [WARN]  recv_frame attrib compare failed\\n\", __func__);\n\n\tif (_rtw_memcmp(precvframe->u.hdr.rx_data, pcloneframe->u.hdr.rx_data, precvframe->u.hdr.len) == _FALSE)\n\t\tRTW_INFO(\"%s [WARN]  recv_frame rx_data compare failed\\n\", __func__);\n\n}\n#endif\n\nstatic s32 _rtw_mi_buddy_clone_bcmc_packet(_adapter *adapter, union recv_frame *precvframe, u8 *pphy_status, union recv_frame *pcloneframe)\n{\n\ts32 ret = _SUCCESS;\n#ifdef CONFIG_SKB_ALLOCATED\n\tu8 *pbuf = precvframe->u.hdr.rx_data;\n#endif\n\tstruct rx_pkt_attrib *pattrib = NULL;\n\n\tif (pcloneframe) {\n\t\tpcloneframe->u.hdr.adapter = adapter;\n\n\t\t_rtw_init_listhead(&pcloneframe->u.hdr.list);\n\t\tpcloneframe->u.hdr.precvbuf = NULL;\t/*can't access the precvbuf for new arch.*/\n\t\tpcloneframe->u.hdr.len = 0;\n\n\t\t_rtw_memcpy(&pcloneframe->u.hdr.attrib, &precvframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib));\n\n\t\tpattrib = &pcloneframe->u.hdr.attrib;\n#ifdef CONFIG_SKB_ALLOCATED\n\t\tif (rtw_os_alloc_recvframe(adapter, pcloneframe, pbuf, NULL) == _SUCCESS)\n#else\n\t\tif (rtw_os_recvframe_duplicate_skb(adapter, pcloneframe, precvframe->u.hdr.pkt) == _SUCCESS)\n#endif\n\t\t{\n#ifdef CONFIG_SKB_ALLOCATED\n\t\t\trecvframe_put(pcloneframe, pattrib->pkt_len);\n#endif\n\n#ifdef DBG_SKB_PROCESS\n\t\t\trtw_dbg_skb_process(adapter, precvframe, pcloneframe);\n#endif\n\n\t\t\tif (pphy_status)\n\t\t\t\trx_query_phy_status(pcloneframe, pphy_status);\n\n\t\t\tret = rtw_recv_entry(pcloneframe);\n\t\t} else {\n\t\t\tret = -1;\n\t\t\tRTW_INFO(\"%s()-%d: rtw_os_alloc_recvframe() failed!\\n\", __func__, __LINE__);\n\t\t}\n\n\t}\n\treturn ret;\n}\n\nvoid rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvframe, u8 *pphy_status)\n{\n\tint i;\n\ts32 ret = _SUCCESS;\n\t_adapter *iface = NULL;\n\tunion recv_frame *pcloneframe = NULL;\n\tstruct recv_priv *precvpriv = &padapter->recvpriv;/*primary_padapter*/\n\t_queue *pfree_recv_queue = &precvpriv->free_recv_queue;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tu8 *fhead = get_recvframe_data(precvframe);\n\tu8 type = GetFrameType(fhead);\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (!iface || iface == padapter)\n\t\t\tcontinue;\n\t\tif (rtw_is_adapter_up(iface) == _FALSE || iface->registered == 0)\n\t\t\tcontinue;\n\t\tif (type == WIFI_DATA_TYPE && !adapter_allow_bmc_data_rx(iface))\n\t\t\tcontinue;\n\n\t\tpcloneframe = rtw_alloc_recvframe(pfree_recv_queue);\n\t\tif (pcloneframe) {\n\t\t\tret = _rtw_mi_buddy_clone_bcmc_packet(iface, precvframe, pphy_status, pcloneframe);\n\t\t\tif (_SUCCESS != ret) {\n\t\t\t\tif (ret == -1)\n\t\t\t\t\trtw_free_recvframe(pcloneframe, pfree_recv_queue);\n\t\t\t\t/*RTW_INFO(ADPT_FMT\"-clone BC/MC frame failed\\n\", ADPT_ARG(iface));*/\n\t\t\t}\n\t\t}\n\t}\n\n}\n\n#ifdef CONFIG_PCI_HCI\n/*API be created temporary for MI, caller is interrupt-handler, PCIE's interrupt handler cannot apply to multi-AP*/\n_adapter *rtw_mi_get_ap_adapter(_adapter *padapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tint i;\n\t_adapter *iface = NULL;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (!iface)\n\t\t\tcontinue;\n\n\t\tif (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE\n\t\t    && check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE)\n\t\t\tbreak;\n\n\t}\n\treturn iface;\n}\n#endif\n\nu8 rtw_mi_get_ld_sta_ifbmp(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tint i;\n\t_adapter *iface = NULL;\n\tu8 ifbmp = 0;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (!iface)\n\t\t\tcontinue;\n\n\t\tif (MLME_IS_STA(iface) && MLME_IS_ASOC(iface))\n\t\t\tifbmp |= BIT(i);\n\t}\n\n\treturn ifbmp;\n}\n\nu8 rtw_mi_get_ap_mesh_ifbmp(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tint i;\n\t_adapter *iface = NULL;\n\tu8 ifbmp = 0;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (!iface)\n\t\t\tcontinue;\n\n\t\tif (CHK_MLME_STATE(iface, WIFI_AP_STATE | WIFI_MESH_STATE)\n\t\t\t&& MLME_IS_ASOC(iface))\n\t\t\tifbmp |= BIT(i);\n\t}\n\n\treturn ifbmp;\n}\n\nvoid rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b)\n{\n#ifdef CONFIG_CONCURRENT_MODE\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\n\tint i;\n\t_adapter *iface = NULL;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (!iface)\n\t\t\tcontinue;\n\n\t\tif (macid_ctl->iface_bmc[iface->iface_id] != INVALID_SEC_MAC_CAM_ID) {\n\t\t\tif (macid_ctl->iface_bmc[iface->iface_id] == camid_a)\n\t\t\t\tmacid_ctl->iface_bmc[iface->iface_id] = camid_b;\n\t\t\telse if (macid_ctl->iface_bmc[iface->iface_id] == camid_b)\n\t\t\t\tmacid_ctl->iface_bmc[iface->iface_id] = camid_a;\n\t\t\tiface->securitypriv.dot118021x_bmc_cam_id  = macid_ctl->iface_bmc[iface->iface_id];\n\t\t}\n\t}\n#endif\n}\n\nu8 rtw_mi_get_assoc_if_num(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tu8 n_assoc_iface = 0;\n#if 1\n\tu8 i;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tif (check_fwstate(&(dvobj->padapters[i]->mlmepriv), WIFI_ASOC_STATE))\n\t\t\tn_assoc_iface++;\n\t}\n#else\n\tn_assoc_iface = DEV_STA_LD_NUM(dvobj) + DEV_AP_NUM(dvobj) + DEV_ADHOC_NUM(dvobj) + DEV_MESH_NUM(dvobj);\n#endif\n\treturn n_assoc_iface;\n}\n"
  },
  {
    "path": "core/rtw_mlme.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2019 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_MLME_C_\n\n#include <hal_data.h>\n\nextern void indicate_wx_scan_complete_event(_adapter *padapter);\nextern u8 rtw_do_join(_adapter *padapter);\n\n\nvoid rtw_init_mlme_timer(_adapter *padapter)\n{\n\tstruct\tmlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n\trtw_init_timer(&(pmlmepriv->assoc_timer), padapter, rtw_join_timeout_handler, padapter);\n\trtw_init_timer(&(pmlmepriv->scan_to_timer), padapter, rtw_scan_timeout_handler, padapter);\n\n#ifdef CONFIG_SET_SCAN_DENY_TIMER\n\trtw_init_timer(&(pmlmepriv->set_scan_deny_timer), padapter, rtw_set_scan_deny_timer_hdl, padapter);\n#endif\n\n#ifdef RTK_DMP_PLATFORM\n\t_init_workitem(&(pmlmepriv->Linkup_workitem), Linkup_workitem_callback, padapter);\n\t_init_workitem(&(pmlmepriv->Linkdown_workitem), Linkdown_workitem_callback, padapter);\n#endif\n}\n\nsint\t_rtw_init_mlme_priv(_adapter *padapter)\n{\n\tsint\ti;\n\tu8\t*pbuf;\n\tstruct wlan_network\t*pnetwork;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tsint\tres = _SUCCESS;\n\n\n\t/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */\n\t/* _rtw_memset((u8 *)pmlmepriv, 0, sizeof(struct mlme_priv)); */\n\n\n\t/*qos_priv*/\n\t/*pmlmepriv->qospriv.qos_option = pregistrypriv->wmm_enable;*/\n\n\t/*ht_priv*/\n#ifdef CONFIG_80211N_HT\n\tpmlmepriv->htpriv.ampdu_enable = _FALSE;/*set to disabled*/\n#endif\n\n\tpmlmepriv->nic_hdl = (u8 *)padapter;\n\n\tpmlmepriv->pscanned = NULL;\n\tinit_fwstate(pmlmepriv, WIFI_STATION_STATE);\n\tpmlmepriv->cur_network.network.InfrastructureMode = Ndis802_11AutoUnknown;\n\tpmlmepriv->scan_mode = SCAN_ACTIVE; /* 1: active, 0: pasive. Maybe someday we should rename this varable to \"active_mode\" (Jeff) */\n\n\t_rtw_spinlock_init(&(pmlmepriv->lock));\n\t_rtw_init_queue(&(pmlmepriv->free_bss_pool));\n\t_rtw_init_queue(&(pmlmepriv->scanned_queue));\n\n\tset_scanned_network_val(pmlmepriv, 0);\n\n\t_rtw_memset(&pmlmepriv->assoc_ssid, 0, sizeof(NDIS_802_11_SSID));\n\n\tif (padapter->registrypriv.max_bss_cnt != 0)\n\t\tpmlmepriv->max_bss_cnt = padapter->registrypriv.max_bss_cnt;\n\telse if (rfctl->max_chan_nums <= MAX_CHANNEL_NUM_2G)\n\t\tpmlmepriv->max_bss_cnt = MAX_BSS_CNT;\n\telse\n\t\tpmlmepriv->max_bss_cnt = MAX_BSS_CNT + MAX_BSS_CNT;\n\n\n\tpbuf = rtw_zvmalloc(pmlmepriv->max_bss_cnt * (sizeof(struct wlan_network)));\n\n\tif (pbuf == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tpmlmepriv->free_bss_buf = pbuf;\n\n\tpnetwork = (struct wlan_network *)pbuf;\n\n\tfor (i = 0; i < pmlmepriv->max_bss_cnt; i++) {\n\t\t_rtw_init_listhead(&(pnetwork->list));\n\n\t\trtw_list_insert_tail(&(pnetwork->list), &(pmlmepriv->free_bss_pool.queue));\n\n\t\tpnetwork++;\n\t}\n\n\t/* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */\n\n\trtw_clear_scan_deny(padapter);\n#ifdef CONFIG_ARP_KEEP_ALIVE\n\tpmlmepriv->bGetGateway = 0;\n\tpmlmepriv->GetGatewayTryCnt = 0;\n#endif\n\n#ifdef CONFIG_LAYER2_ROAMING\n#define RTW_ROAM_SCAN_RESULT_EXP_MS (5*1000)\n#define RTW_ROAM_RSSI_DIFF_TH 10\n#define RTW_ROAM_SCAN_INTERVAL (5)    /* 5*(2 second)*/\n#define RTW_ROAM_RSSI_THRESHOLD 70\n\n\tpmlmepriv->roam_flags = 0\n\t\t\t\t| RTW_ROAM_ON_EXPIRED\n#ifdef CONFIG_LAYER2_ROAMING_RESUME\n\t\t\t\t| RTW_ROAM_ON_RESUME\n#endif\n#ifdef CONFIG_LAYER2_ROAMING_ACTIVE\n\t\t\t\t| RTW_ROAM_ACTIVE\n#endif\n\t\t\t\t;\n\n\tpmlmepriv->roam_scanr_exp_ms = RTW_ROAM_SCAN_RESULT_EXP_MS;\n\tpmlmepriv->roam_rssi_diff_th = RTW_ROAM_RSSI_DIFF_TH;\n\tpmlmepriv->roam_scan_int \t = RTW_ROAM_SCAN_INTERVAL;\n\tpmlmepriv->roam_rssi_threshold = RTW_ROAM_RSSI_THRESHOLD;\n\tpmlmepriv->need_to_roam = _FALSE;\n\tpmlmepriv->last_roaming = rtw_get_current_time();\n#endif /* CONFIG_LAYER2_ROAMING */\n\n#ifdef CONFIG_RTW_80211R\n\trtw_ft_info_init(&pmlmepriv->ft_roam);\n#endif\n#ifdef CONFIG_LAYER2_ROAMING\n#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)\n\trtw_roam_nb_info_init(padapter);\n\tpmlmepriv->ch_cnt = 0;\n#endif\t\n#endif\n\trtw_init_mlme_timer(padapter);\n\nexit:\n\n\n\treturn res;\n}\n\nvoid rtw_mfree_mlme_priv_lock(struct mlme_priv *pmlmepriv);\nvoid rtw_mfree_mlme_priv_lock(struct mlme_priv *pmlmepriv)\n{\n\t_rtw_spinlock_free(&pmlmepriv->lock);\n\t_rtw_spinlock_free(&(pmlmepriv->free_bss_pool.lock));\n\t_rtw_spinlock_free(&(pmlmepriv->scanned_queue.lock));\n}\n\nstatic void rtw_free_mlme_ie_data(u8 **ppie, u32 *plen)\n{\n\tif (*ppie) {\n\t\trtw_mfree(*ppie, *plen);\n\t\t*plen = 0;\n\t\t*ppie = NULL;\n\t}\n}\n\nvoid rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv)\n{\n#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)\n\trtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len);\n\trtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len);\n\trtw_free_mlme_ie_data(&pmlmepriv->wps_beacon_ie, &pmlmepriv->wps_beacon_ie_len);\n\trtw_free_mlme_ie_data(&pmlmepriv->wps_probe_req_ie, &pmlmepriv->wps_probe_req_ie_len);\n\trtw_free_mlme_ie_data(&pmlmepriv->wps_probe_resp_ie, &pmlmepriv->wps_probe_resp_ie_len);\n\trtw_free_mlme_ie_data(&pmlmepriv->wps_assoc_resp_ie, &pmlmepriv->wps_assoc_resp_ie_len);\n\n\trtw_free_mlme_ie_data(&pmlmepriv->p2p_beacon_ie, &pmlmepriv->p2p_beacon_ie_len);\n\trtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_req_ie, &pmlmepriv->p2p_probe_req_ie_len);\n\trtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_resp_ie, &pmlmepriv->p2p_probe_resp_ie_len);\n\trtw_free_mlme_ie_data(&pmlmepriv->p2p_go_probe_resp_ie, &pmlmepriv->p2p_go_probe_resp_ie_len);\n\trtw_free_mlme_ie_data(&pmlmepriv->p2p_assoc_req_ie, &pmlmepriv->p2p_assoc_req_ie_len);\n\trtw_free_mlme_ie_data(&pmlmepriv->p2p_assoc_resp_ie, &pmlmepriv->p2p_assoc_resp_ie_len);\n#endif\n\n#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)\n\trtw_free_mlme_ie_data(&pmlmepriv->wfd_beacon_ie, &pmlmepriv->wfd_beacon_ie_len);\n\trtw_free_mlme_ie_data(&pmlmepriv->wfd_probe_req_ie, &pmlmepriv->wfd_probe_req_ie_len);\n\trtw_free_mlme_ie_data(&pmlmepriv->wfd_probe_resp_ie, &pmlmepriv->wfd_probe_resp_ie_len);\n\trtw_free_mlme_ie_data(&pmlmepriv->wfd_go_probe_resp_ie, &pmlmepriv->wfd_go_probe_resp_ie_len);\n\trtw_free_mlme_ie_data(&pmlmepriv->wfd_assoc_req_ie, &pmlmepriv->wfd_assoc_req_ie_len);\n\trtw_free_mlme_ie_data(&pmlmepriv->wfd_assoc_resp_ie, &pmlmepriv->wfd_assoc_resp_ie_len);\n#endif\n\n#ifdef CONFIG_RTW_80211R\n\trtw_free_mlme_ie_data(&pmlmepriv->auth_rsp, &pmlmepriv->auth_rsp_len);\n#endif\n}\n\n#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)\nint rtw_mlme_update_wfd_ie_data(struct mlme_priv *mlme, u8 type, u8 *ie, u32 ie_len)\n{\n\t_adapter *adapter = mlme_to_adapter(mlme);\n\tstruct wifi_display_info *wfd_info = &adapter->wfd_info;\n\tu8 clear = 0;\n\tu8 **t_ie = NULL;\n\tu32 *t_ie_len = NULL;\n\tint ret = _FAIL;\n\n\tif (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))\n\t\tgoto success;\n\n\tif (wfd_info->wfd_enable == _TRUE)\n\t\tgoto success; /* WFD IE is build by self */\n\n\tif (!ie && !ie_len)\n\t\tclear = 1;\n\telse if (!ie || !ie_len) {\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" type:%u, ie:%p, ie_len:%u\"\n\t\t\t  , FUNC_ADPT_ARG(adapter), type, ie, ie_len);\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tswitch (type) {\n\tcase MLME_BEACON_IE:\n\t\tt_ie = &mlme->wfd_beacon_ie;\n\t\tt_ie_len = &mlme->wfd_beacon_ie_len;\n\t\tbreak;\n\tcase MLME_PROBE_REQ_IE:\n\t\tt_ie = &mlme->wfd_probe_req_ie;\n\t\tt_ie_len = &mlme->wfd_probe_req_ie_len;\n\t\tbreak;\n\tcase MLME_PROBE_RESP_IE:\n\t\tt_ie = &mlme->wfd_probe_resp_ie;\n\t\tt_ie_len = &mlme->wfd_probe_resp_ie_len;\n\t\tbreak;\n\tcase MLME_GO_PROBE_RESP_IE:\n\t\tt_ie = &mlme->wfd_go_probe_resp_ie;\n\t\tt_ie_len = &mlme->wfd_go_probe_resp_ie_len;\n\t\tbreak;\n\tcase MLME_ASSOC_REQ_IE:\n\t\tt_ie = &mlme->wfd_assoc_req_ie;\n\t\tt_ie_len = &mlme->wfd_assoc_req_ie_len;\n\t\tbreak;\n\tcase MLME_ASSOC_RESP_IE:\n\t\tt_ie = &mlme->wfd_assoc_resp_ie;\n\t\tt_ie_len = &mlme->wfd_assoc_resp_ie_len;\n\t\tbreak;\n\tdefault:\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" unsupported type:%u\"\n\t\t\t  , FUNC_ADPT_ARG(adapter), type);\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (*t_ie) {\n\t\tu32 free_len = *t_ie_len;\n\t\t*t_ie_len = 0;\n\t\trtw_mfree(*t_ie, free_len);\n\t\t*t_ie = NULL;\n\t}\n\n\tif (!clear) {\n\t\t*t_ie = rtw_malloc(ie_len);\n\t\tif (*t_ie == NULL) {\n\t\t\tRTW_ERR(FUNC_ADPT_FMT\" type:%u, rtw_malloc() fail\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), type);\n\t\t\tgoto exit;\n\t\t}\n\t\t_rtw_memcpy(*t_ie, ie, ie_len);\n\t\t*t_ie_len = ie_len;\n\t}\n\n\tif (*t_ie && *t_ie_len) {\n\t\tu8 *attr_content;\n\t\tu32 attr_contentlen = 0;\n\n\t\tattr_content = rtw_get_wfd_attr_content(*t_ie, *t_ie_len, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen);\n\t\tif (attr_content && attr_contentlen) {\n\t\t\tif (RTW_GET_BE16(attr_content + 2) != wfd_info->rtsp_ctrlport) {\n\t\t\t\twfd_info->rtsp_ctrlport = RTW_GET_BE16(attr_content + 2);\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" type:%u, RTSP CTRL port = %u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(adapter), type, wfd_info->rtsp_ctrlport);\n\t\t\t}\n\t\t}\n\t}\n\nsuccess:\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n#endif /* defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) */\n\nvoid _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv)\n{\n\t_adapter *adapter = mlme_to_adapter(pmlmepriv);\n\tif (NULL == pmlmepriv) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\trtw_free_mlme_priv_ie_data(pmlmepriv);\n\n\tif (pmlmepriv) {\n\t\trtw_mfree_mlme_priv_lock(pmlmepriv);\n\n\t\tif (pmlmepriv->free_bss_buf)\n\t\t\trtw_vmfree(pmlmepriv->free_bss_buf, pmlmepriv->max_bss_cnt * sizeof(struct wlan_network));\n\t}\nexit:\n\treturn;\n}\n\nsint\t_rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork)\n{\n\t_irqL irqL;\n\n\n\tif (pnetwork == NULL)\n\t\tgoto exit;\n\n\t_enter_critical_bh(&queue->lock, &irqL);\n\n\trtw_list_insert_tail(&pnetwork->list, &queue->queue);\n\n\t_exit_critical_bh(&queue->lock, &irqL);\n\nexit:\n\n\n\treturn _SUCCESS;\n}\n\n/*\nstruct\twlan_network *_rtw_dequeue_network(_queue *queue)\n{\n\t_irqL irqL;\n\n\tstruct wlan_network *pnetwork;\n\n\n\t_enter_critical_bh(&queue->lock, &irqL);\n\n\tif (_rtw_queue_empty(queue) == _TRUE)\n\n\t\tpnetwork = NULL;\n\n\telse\n\t{\n\t\tpnetwork = LIST_CONTAINOR(get_next(&queue->queue), struct wlan_network, list);\n\n\t\trtw_list_delete(&(pnetwork->list));\n\t}\n\n\t_exit_critical_bh(&queue->lock, &irqL);\n\n\n\treturn pnetwork;\n}\n*/\n\nstruct\twlan_network *_rtw_alloc_network(struct\tmlme_priv *pmlmepriv) /* (_queue *free_queue) */\n{\n\t_irqL\tirqL;\n\tstruct\twlan_network\t*pnetwork;\n\t_queue *free_queue = &pmlmepriv->free_bss_pool;\n\t_list *plist = NULL;\n\n\n\t_enter_critical_bh(&free_queue->lock, &irqL);\n\n\tif (_rtw_queue_empty(free_queue) == _TRUE) {\n\t\tpnetwork = NULL;\n\t\tgoto exit;\n\t}\n\tplist = get_next(&(free_queue->queue));\n\n\tpnetwork = LIST_CONTAINOR(plist , struct wlan_network, list);\n\n\trtw_list_delete(&pnetwork->list);\n\n\tpnetwork->network_type = 0;\n\tpnetwork->fixed = _FALSE;\n\tpnetwork->last_scanned = rtw_get_current_time();\n#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT\n\tpnetwork->acnode_stime = 0;\n\tpnetwork->acnode_notify_etime = 0;\n#endif\n\n\tpnetwork->aid = 0;\n\tpnetwork->join_res = 0;\n\n\tpmlmepriv->num_of_scanned++;\n\nexit:\n\t_exit_critical_bh(&free_queue->lock, &irqL);\n\n\n\treturn pnetwork;\n}\n\nvoid _rtw_free_network(struct\tmlme_priv *pmlmepriv , struct wlan_network *pnetwork, u8 isfreeall)\n{\n\tu32 delta_time;\n\tu32 lifetime = SCANQUEUE_LIFETIME;\n\t_irqL irqL;\n\t_queue *free_queue = &(pmlmepriv->free_bss_pool);\n\n\n\tif (pnetwork == NULL)\n\t\tgoto exit;\n\n\tif (pnetwork->fixed == _TRUE)\n\t\tgoto exit;\n\n\tif ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||\n\t    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))\n\t\tlifetime = 1;\n\n\tif (!isfreeall) {\n\t\tdelta_time = (u32) rtw_get_passing_time_ms(pnetwork->last_scanned);\n\t\tif (delta_time < lifetime) /* unit:msec */\n\t\t\tgoto exit;\n\t}\n\n\t_enter_critical_bh(&free_queue->lock, &irqL);\n\n\trtw_list_delete(&(pnetwork->list));\n\n\trtw_list_insert_tail(&(pnetwork->list), &(free_queue->queue));\n\n\tpmlmepriv->num_of_scanned--;\n\n\n\t/* RTW_INFO(\"_rtw_free_network:SSID=%s\\n\", pnetwork->network.Ssid.Ssid); */\n\n\t_exit_critical_bh(&free_queue->lock, &irqL);\n\nexit:\n\treturn;\n}\n\nvoid _rtw_free_network_nolock(struct\tmlme_priv *pmlmepriv, struct wlan_network *pnetwork)\n{\n\n\t_queue *free_queue = &(pmlmepriv->free_bss_pool);\n\n\n\tif (pnetwork == NULL)\n\t\tgoto exit;\n\n\tif (pnetwork->fixed == _TRUE)\n\t\tgoto exit;\n\n\t/* _enter_critical(&free_queue->lock, &irqL); */\n\n\trtw_list_delete(&(pnetwork->list));\n\n\trtw_list_insert_tail(&(pnetwork->list), get_list_head(free_queue));\n\n\tpmlmepriv->num_of_scanned--;\n\n\t/* _exit_critical(&free_queue->lock, &irqL); */\n\nexit:\n\treturn;\n}\n\nvoid _rtw_free_network_queue(_adapter *padapter, u8 isfreeall)\n{\n\t_irqL irqL;\n\t_list *phead, *plist;\n\tstruct wlan_network *pnetwork;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\t_queue *scanned_queue = &pmlmepriv->scanned_queue;\n\n\n\n\t_enter_critical_bh(&scanned_queue->lock, &irqL);\n\n\tphead = get_list_head(scanned_queue);\n\tplist = get_next(phead);\n\n\twhile (rtw_end_of_queue_search(phead, plist) == _FALSE) {\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\n\t\tplist = get_next(plist);\n\n\t\t_rtw_free_network(pmlmepriv, pnetwork, isfreeall);\n\n\t}\n\n\t_exit_critical_bh(&scanned_queue->lock, &irqL);\n\n\n}\n\n\n\n\nsint rtw_if_up(_adapter *padapter)\n{\n\n\tsint res;\n\n\tif (RTW_CANNOT_RUN(padapter) ||\n\t    (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _FALSE)) {\n\t\tres = _FALSE;\n\t} else\n\t\tres =  _TRUE;\n\n\treturn res;\n}\n\n\nvoid rtw_generate_random_ibss(u8 *pibss)\n{\n\t*((u32 *)(&pibss[2])) = rtw_random32();\n\tpibss[0] = 0x02; /* in ad-hoc mode local bit must set to 1 */\n\tpibss[1] = 0x11;\n\tpibss[2] = 0x87;\n}\n\nu8 *rtw_get_capability_from_ie(u8 *ie)\n{\n\treturn ie + 8 + 2;\n}\n\n\nu16 rtw_get_capability(WLAN_BSSID_EX *bss)\n{\n\tu16\tval;\n\n\t_rtw_memcpy((u8 *)&val, rtw_get_capability_from_ie(bss->IEs), 2);\n\n\treturn le16_to_cpu(val);\n}\n\nu8 *rtw_get_timestampe_from_ie(u8 *ie)\n{\n\treturn ie + 0;\n}\n\nu8 *rtw_get_beacon_interval_from_ie(u8 *ie)\n{\n\treturn ie + 8;\n}\n\n\nint\trtw_init_mlme_priv(_adapter *padapter) /* (struct\tmlme_priv *pmlmepriv) */\n{\n\tint\tres;\n\tres = _rtw_init_mlme_priv(padapter);/* (pmlmepriv); */\n\treturn res;\n}\n\nvoid rtw_free_mlme_priv(struct mlme_priv *pmlmepriv)\n{\n\t_rtw_free_mlme_priv(pmlmepriv);\n}\n\nint\trtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork);\nint\trtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork)\n{\n\tint\tres;\n\tres = _rtw_enqueue_network(queue, pnetwork);\n\treturn res;\n}\n\n/*\nstatic struct\twlan_network *rtw_dequeue_network(_queue *queue)\n{\n\tstruct wlan_network *pnetwork;\n\tpnetwork = _rtw_dequeue_network(queue);\n\treturn pnetwork;\n}\n*/\n\nstruct\twlan_network *rtw_alloc_network(struct\tmlme_priv *pmlmepriv);\nstruct\twlan_network *rtw_alloc_network(struct\tmlme_priv *pmlmepriv) /* (_queue\t*free_queue) */\n{\n\tstruct\twlan_network\t*pnetwork;\n\tpnetwork = _rtw_alloc_network(pmlmepriv);\n\treturn pnetwork;\n}\n\nvoid rtw_free_network(struct mlme_priv *pmlmepriv, struct\twlan_network *pnetwork, u8 is_freeall);\nvoid rtw_free_network(struct mlme_priv *pmlmepriv, struct\twlan_network *pnetwork, u8 is_freeall)/* (struct\twlan_network *pnetwork, _queue\t*free_queue) */\n{\n\t_rtw_free_network(pmlmepriv, pnetwork, is_freeall);\n}\n\nvoid rtw_free_network_nolock(_adapter *padapter, struct wlan_network *pnetwork);\nvoid rtw_free_network_nolock(_adapter *padapter, struct wlan_network *pnetwork)\n{\n\t_rtw_free_network_nolock(&(padapter->mlmepriv), pnetwork);\n#ifdef CONFIG_IOCTL_CFG80211\n\trtw_cfg80211_unlink_bss(padapter, pnetwork);\n#endif /* CONFIG_IOCTL_CFG80211 */\n}\n\n\nvoid rtw_free_network_queue(_adapter *dev, u8 isfreeall)\n{\n\t_rtw_free_network_queue(dev, isfreeall);\n}\n\nstruct wlan_network *_rtw_find_network(_queue *scanned_queue, const u8 *addr)\n{\n\t_list\t*phead, *plist;\n\tstruct\twlan_network *pnetwork = NULL;\n\tu8 zero_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};\n\n\tif (_rtw_memcmp(zero_addr, addr, ETH_ALEN)) {\n\t\tpnetwork = NULL;\n\t\tgoto exit;\n\t}\n\n\tphead = get_list_head(scanned_queue);\n\tplist = get_next(phead);\n\n\twhile (plist != phead) {\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network , list);\n\n\t\tif (_rtw_memcmp(addr, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE)\n\t\t\tbreak;\n\n\t\tplist = get_next(plist);\n\t}\n\n\tif (plist == phead)\n\t\tpnetwork = NULL;\n\nexit:\n\treturn pnetwork;\n}\n\nstruct wlan_network *rtw_find_network(_queue *scanned_queue, const u8 *addr)\n{\n\tstruct\twlan_network *pnetwork;\n\t_irqL irqL;\n\n\t _enter_critical_bh(&scanned_queue->lock, &irqL);\n\tpnetwork = _rtw_find_network(scanned_queue, addr);\n\t_exit_critical_bh(&scanned_queue->lock, &irqL);\n\n\treturn pnetwork;\n}\n\nint rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork)\n{\n\tint ret = _TRUE;\n\tstruct security_priv *psecuritypriv = &adapter->securitypriv;\n\n\tif ((psecuritypriv->dot11PrivacyAlgrthm != _NO_PRIVACY_) &&\n\t    (pnetwork->network.Privacy == 0))\n\t\tret = _FALSE;\n\telse if ((psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_) &&\n\t\t (pnetwork->network.Privacy == 1))\n\t\tret = _FALSE;\n\telse\n\t\tret = _TRUE;\n\n\treturn ret;\n\n}\n\ninline int is_same_ess(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b)\n{\n\treturn (a->Ssid.SsidLength == b->Ssid.SsidLength)\n\t       &&  _rtw_memcmp(a->Ssid.Ssid, b->Ssid.Ssid, a->Ssid.SsidLength) == _TRUE;\n}\n\nint is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature)\n{\n\tu16 s_cap, d_cap;\n\n\n\tif (rtw_bug_check(dst, src, &s_cap, &d_cap) == _FALSE)\n\t\treturn _FALSE;\n\n\t_rtw_memcpy((u8 *)&s_cap, rtw_get_capability_from_ie(src->IEs), 2);\n\t_rtw_memcpy((u8 *)&d_cap, rtw_get_capability_from_ie(dst->IEs), 2);\n\n\n\ts_cap = le16_to_cpu(s_cap);\n\td_cap = le16_to_cpu(d_cap);\n\n\n#ifdef CONFIG_P2P\n\tif ((feature == 1) && /* 1: P2P supported */\n\t    (_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN) == _TRUE)\n\t   )\n\t\treturn _TRUE;\n#endif\n\n\t/* Wi-Fi driver doesn't consider the situation of BCN and ProbRsp sent from the same hidden AP, \n\t  * it considers these two packets are sent from different AP. \n\t  * Therefore, the scan queue may store two scan results of the same hidden AP, likes below.\n\t  *\n\t  *  index            bssid              ch    RSSI   SdBm  Noise   age          flag             ssid\n\t  *    1    00:e0:4c:55:50:01    153   -73     -73        0     7044   [WPS][ESS]     RTK5G\n\t  *    3    00:e0:4c:55:50:01    153   -73     -73        0     7044   [WPS][ESS]\n\t  *\n\t  * Original rules will compare Ssid, SsidLength, MacAddress, s_cap, d_cap at the same time.\n\t  * Wi-Fi driver will assume that the BCN and ProbRsp sent from the same hidden AP are the same network\n\t  * after we add an additional rule to compare SsidLength and Ssid.\n\t  * It means the scan queue will not store two scan results of the same hidden AP, it only store ProbRsp.\n\t  * For customer request.\n\t  */\n\t  \n\tif (((_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN)) == _TRUE) &&\n\t\t((s_cap & WLAN_CAPABILITY_IBSS) == (d_cap & WLAN_CAPABILITY_IBSS)) &&\n\t\t((s_cap & WLAN_CAPABILITY_BSS) == (d_cap & WLAN_CAPABILITY_BSS))) {\n\t\tif ((src->Ssid.SsidLength == dst->Ssid.SsidLength) && \n\t\t\t(((_rtw_memcmp(src->Ssid.Ssid, dst->Ssid.Ssid, src->Ssid.SsidLength)) == _TRUE) || //Case of normal AP\n\t\t\t(is_all_null(src->Ssid.Ssid, src->Ssid.SsidLength) == _TRUE || is_all_null(dst->Ssid.Ssid, dst->Ssid.SsidLength) == _TRUE))) //Case of hidden AP\n\t\t\treturn _TRUE;\n\t\telse if ((src->Ssid.SsidLength == 0 || dst->Ssid.SsidLength == 0)) //Case of hidden AP\n\t\t\treturn _TRUE;\n\t\telse\n\t\t\treturn _FALSE;\n\t} else {\n\t\treturn _FALSE;\n\t}\n}\n\nstruct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network)\n{\n\t_list *phead, *plist;\n\tstruct wlan_network *found = NULL;\n\n\tphead = get_list_head(scanned_queue);\n\tplist = get_next(phead);\n\n\twhile (plist != phead) {\n\t\tfound = LIST_CONTAINOR(plist, struct wlan_network , list);\n\n\t\tif (is_same_network(&network->network, &found->network, 0))\n\t\t\tbreak;\n\n\t\tplist = get_next(plist);\n\t}\n\n\tif (plist == phead)\n\t\tfound = NULL;\n\n\treturn found;\n}\n\nstruct wlan_network *rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network)\n{\n\t_irqL irqL;\n\tstruct wlan_network *found = NULL;\n\n\tif (scanned_queue == NULL || network == NULL)\n\t\tgoto exit;\n\n\t_enter_critical_bh(&scanned_queue->lock, &irqL);\n\tfound = _rtw_find_same_network(scanned_queue, network);\n\t_exit_critical_bh(&scanned_queue->lock, &irqL);\n\nexit:\n\treturn found;\n}\n\nstruct\twlan_network\t*rtw_get_oldest_wlan_network(_queue *scanned_queue)\n{\n\t_list\t*plist, *phead;\n\n\n\tstruct\twlan_network\t*pwlan = NULL;\n\tstruct\twlan_network\t*oldest = NULL;\n\tphead = get_list_head(scanned_queue);\n\n\tplist = get_next(phead);\n\n\twhile (1) {\n\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tpwlan = LIST_CONTAINOR(plist, struct wlan_network, list);\n\n\t\tif (pwlan->fixed != _TRUE) {\n\t\t\tif (oldest == NULL || rtw_time_after(oldest->last_scanned, pwlan->last_scanned))\n\t\t\t\toldest = pwlan;\n\t\t}\n\n\t\tplist = get_next(plist);\n\t}\n\treturn oldest;\n\n}\n\nvoid update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src,\n\t\t    _adapter *padapter, bool update_ie)\n{\n#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1\n\tu8 ss_ori = dst->PhyInfo.SignalStrength;\n\tu8 sq_ori = dst->PhyInfo.SignalQuality;\n\tu8 ss_smp = src->PhyInfo.SignalStrength;\n\tlong rssi_smp = src->Rssi;\n#endif\n\tlong rssi_ori = dst->Rssi;\n\n\tu8 sq_smp = src->PhyInfo.SignalQuality;\n\tu8 ss_final;\n\tu8 sq_final;\n\tlong rssi_final;\n\n\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\trtw_hal_antdiv_rssi_compared(padapter, dst, src); /* this will update src.Rssi, need consider again */\n#endif\n\n#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1\n\tif (strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" %s(\"MAC_FMT\", ch%u) ss_ori:%3u, sq_ori:%3u, rssi_ori:%3ld, ss_smp:%3u, sq_smp:%3u, rssi_smp:%3ld\\n\"\n\t\t\t , FUNC_ADPT_ARG(padapter)\n\t\t\t, src->Ssid.Ssid, MAC_ARG(src->MacAddress), src->Configuration.DSConfig\n\t\t\t , ss_ori, sq_ori, rssi_ori\n\t\t\t , ss_smp, sq_smp, rssi_smp\n\t\t\t);\n\t}\n#endif\n\n\t/* The rule below is 1/5 for sample value, 4/5 for history value */\n\tif (check_fwstate(&padapter->mlmepriv, _FW_LINKED) && is_same_network(&(padapter->mlmepriv.cur_network.network), src, 0)) {\n\t\t/* Take the recvpriv's value for the connected AP*/\n\t\tss_final = padapter->recvpriv.signal_strength;\n\t\tsq_final = padapter->recvpriv.signal_qual;\n\t\t/* the rssi value here is undecorated, and will be used for antenna diversity */\n\t\tif (sq_smp != 101) /* from the right channel */\n\t\t\trssi_final = (src->Rssi + dst->Rssi * 4) / 5;\n\t\telse\n\t\t\trssi_final = rssi_ori;\n\t} else {\n\t\tif (sq_smp != 101) { /* from the right channel */\n\t\t\tss_final = ((u32)(src->PhyInfo.SignalStrength) + (u32)(dst->PhyInfo.SignalStrength) * 4) / 5;\n\t\t\tsq_final = ((u32)(src->PhyInfo.SignalQuality) + (u32)(dst->PhyInfo.SignalQuality) * 4) / 5;\n\t\t\trssi_final = (src->Rssi + dst->Rssi * 4) / 5;\n\t\t} else {\n\t\t\t/* bss info not receving from the right channel, use the original RX signal infos */\n\t\t\tss_final = dst->PhyInfo.SignalStrength;\n\t\t\tsq_final = dst->PhyInfo.SignalQuality;\n\t\t\trssi_final = dst->Rssi;\n\t\t}\n\n\t}\n\n\tif (update_ie) {\n\t\tdst->Reserved[0] = src->Reserved[0];\n\t\tdst->Reserved[1] = src->Reserved[1];\n\t\t_rtw_memcpy((u8 *)dst, (u8 *)src, get_WLAN_BSSID_EX_sz(src));\n\t}\n\n\tdst->PhyInfo.SignalStrength = ss_final;\n\tdst->PhyInfo.SignalQuality = sq_final;\n\tdst->Rssi = rssi_final;\n\n#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1\n\tif (strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" %s(\"MAC_FMT\"), SignalStrength:%u, SignalQuality:%u, RawRSSI:%ld\\n\"\n\t\t\t , FUNC_ADPT_ARG(padapter)\n\t\t\t, dst->Ssid.Ssid, MAC_ARG(dst->MacAddress), dst->PhyInfo.SignalStrength, dst->PhyInfo.SignalQuality, dst->Rssi);\n\t}\n#endif\n\n#if 0 /* old codes, may be useful one day...\n * \tRTW_INFO(\"update_network: rssi=0x%lx dst->Rssi=%d ,dst->Rssi=0x%lx , src->Rssi=0x%lx\",(dst->Rssi+src->Rssi)/2,dst->Rssi,dst->Rssi,src->Rssi); */\n\tif (check_fwstate(&padapter->mlmepriv, _FW_LINKED) && is_same_network(&(padapter->mlmepriv.cur_network.network), src)) {\n\n\t\t/* RTW_INFO(\"b:ssid=%s update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\\n\",src->Ssid.Ssid,src->Rssi,padapter->recvpriv.signal); */\n\t\tif (padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) {\n\t\t\tpadapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX;\n\t\t\tlast_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index];\n\t\t\tpadapter->recvpriv.signal_qual_data.total_val -= last_evm;\n\t\t}\n\t\tpadapter->recvpriv.signal_qual_data.total_val += query_rx_pwr_percentage(src->Rssi);\n\n\t\tpadapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = query_rx_pwr_percentage(src->Rssi);\n\t\tif (padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX)\n\t\t\tpadapter->recvpriv.signal_qual_data.index = 0;\n\n\t\t/* RTW_INFO(\"Total SQ=%d  pattrib->signal_qual= %d\\n\", padapter->recvpriv.signal_qual_data.total_val, src->Rssi); */\n\n\t\t/* <1> Showed on UI for user,in percentage. */\n\t\ttmpVal = padapter->recvpriv.signal_qual_data.total_val / padapter->recvpriv.signal_qual_data.total_num;\n\t\tpadapter->recvpriv.signal = (u8)tmpVal; /* Link quality */\n\n\t\tsrc->Rssi = translate_percentage_to_dbm(padapter->recvpriv.signal) ;\n\t} else {\n\t\t/*\tRTW_INFO(\"ELSE:ssid=%s update_network: src->rssi=0x%d dst->rssi=%d\\n\",src->Ssid.Ssid,src->Rssi,dst->Rssi); */\n\t\tsrc->Rssi = (src->Rssi + dst->Rssi) / 2; /* dBM */\n\t}\n\n\t/*\tRTW_INFO(\"a:update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\\n\",src->Rssi,padapter->recvpriv.signal); */\n\n#endif\n\n}\n\nstatic void update_current_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork)\n{\n\tstruct\tmlme_priv\t*pmlmepriv = &(adapter->mlmepriv);\n\n\n\trtw_bug_check(&(pmlmepriv->cur_network.network),\n\t\t      &(pmlmepriv->cur_network.network),\n\t\t      &(pmlmepriv->cur_network.network),\n\t\t      &(pmlmepriv->cur_network.network));\n\n\tif ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) && (is_same_network(&(pmlmepriv->cur_network.network), pnetwork, 0))) {\n\n\t\t/* if(pmlmepriv->cur_network.network.IELength<= pnetwork->IELength) */\n\t\t{\n\t\t\tupdate_network(&(pmlmepriv->cur_network.network), pnetwork, adapter, _TRUE);\n\t\t\trtw_update_protection(adapter, (pmlmepriv->cur_network.network.IEs) + sizeof(NDIS_802_11_FIXED_IEs),\n\t\t\t\t      pmlmepriv->cur_network.network.IELength);\n\t\t}\n\t}\n\n\n}\n\n\n/*\n\nCaller must hold pmlmepriv->lock first.\n\n\n*/\nbool rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target)\n{\n\t_irqL irqL;\n\t_list\t*plist, *phead;\n\tu32\tbssid_ex_sz;\n\tstruct mlme_priv\t*pmlmepriv = &(adapter->mlmepriv);\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *pwdinfo = &(adapter->wdinfo);\n#endif /* CONFIG_P2P */\n\t_queue\t*queue\t= &(pmlmepriv->scanned_queue);\n\tstruct wlan_network\t*pnetwork = NULL;\n\tstruct wlan_network\t*choice = NULL;\n\tint target_find = 0;\n\tu8 feature = 0;\n\tbool update_ie = _FALSE;\n\n\t_enter_critical_bh(&queue->lock, &irqL);\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\n#if 0\n\tRTW_INFO(\"%s => ssid:%s , rssi:%ld , ss:%d\\n\",\n\t\t__func__, target->Ssid.Ssid, target->Rssi, target->PhyInfo.SignalStrength);\n#endif\n\n#ifdef CONFIG_P2P\n\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))\n\t\tfeature = 1; /* p2p enable */\n#endif\n\n\twhile (1) {\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\n\t\trtw_bug_check(pnetwork, pnetwork, pnetwork, pnetwork);\n\n#ifdef CONFIG_P2P\n\t\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) &&\n\t\t    (_rtw_memcmp(pnetwork->network.MacAddress, target->MacAddress, ETH_ALEN) == _TRUE)) {\n\t\t\ttarget_find = 1;\n\t\t\tbreak;\n\t\t}\n#endif\n\n\t\tif (is_same_network(&(pnetwork->network), target, feature)) {\n\t\t\ttarget_find = 1;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (rtw_roam_flags(adapter)) {\n\t\t\t/* TODO: don't  select netowrk in the same ess as choice if it's new enough*/\n\t\t}\n\t\tif (pnetwork->fixed) {\n\t\t\tplist = get_next(plist);\n\t\t\tcontinue;\n\t\t}\n\t\t\t\n#ifdef CONFIG_RSSI_PRIORITY\n\t\tif ((choice == NULL) || (pnetwork->network.PhyInfo.SignalStrength < choice->network.PhyInfo.SignalStrength))\n\t\t\t#ifdef CONFIG_RTW_MESH\n\t\t\tif (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter)\n\t\t\t\t|| !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network))\n\t\t\t#endif\n\t\t\t\tchoice = pnetwork;\n#else\n\t\tif (choice == NULL || rtw_time_after(choice->last_scanned, pnetwork->last_scanned))\n\t\t\t#ifdef CONFIG_RTW_MESH\n\t\t\tif (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter)\n\t\t\t\t|| !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network))\n\t\t\t#endif\n\t\t\t\tchoice = pnetwork;\n#endif\n\t\tplist = get_next(plist);\n\n\t}\n\n\n\t/* If we didn't find a match, then get a new network slot to initialize\n\t * with this beacon's information */\n\t/* if (rtw_end_of_queue_search(phead,plist)== _TRUE) { */\n\tif (!target_find) {\n\t\tif (_rtw_queue_empty(&(pmlmepriv->free_bss_pool)) == _TRUE) {\n\t\t\t/* If there are no more slots, expire the choice */\n\t\t\t/* list_del_init(&choice->list); */\n\t\t\tpnetwork = choice;\n\t\t\tif (pnetwork == NULL)\n\t\t\t\tgoto unlock_scan_queue;\n\n#ifdef CONFIG_RSSI_PRIORITY\n\t\tRTW_DBG(\"%s => ssid:%s ,bssid:\"MAC_FMT\"  will be deleted from scanned_queue (rssi:%ld , ss:%d)\\n\",\n\t\t\t__func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Rssi, pnetwork->network.PhyInfo.SignalStrength);\n#else\n\t\tRTW_DBG(\"%s => ssid:%s ,bssid:\"MAC_FMT\" will be deleted from scanned_queue\\n\",\n\t\t\t__func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress));\n#endif\n\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\t\t\trtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(target->PhyInfo.Optimum_antenna), NULL);\n#endif\n\t\t\t_rtw_memcpy(&(pnetwork->network), target,  get_WLAN_BSSID_EX_sz(target));\n\t\t\t/* pnetwork->last_scanned = rtw_get_current_time(); */\n\t\t\t/* variable initialize */\n\t\t\tpnetwork->fixed = _FALSE;\n\t\t\tpnetwork->last_scanned = rtw_get_current_time();\n\t\t\t#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT\n\t\t\tpnetwork->acnode_stime = 0;\n\t\t\tpnetwork->acnode_notify_etime = 0;\n\t\t\t#endif\n\n\t\t\tpnetwork->network_type = 0;\n\t\t\tpnetwork->aid = 0;\n\t\t\tpnetwork->join_res = 0;\n\n\t\t\t/* bss info not receving from the right channel */\n\t\t\tif (pnetwork->network.PhyInfo.SignalQuality == 101)\n\t\t\t\tpnetwork->network.PhyInfo.SignalQuality = 0;\n\t\t} else {\n\t\t\t/* Otherwise just pull from the free list */\n\n\t\t\tpnetwork = rtw_alloc_network(pmlmepriv); /* will update scan_time */\n\t\t\tif (pnetwork == NULL)\n\t\t\t\tgoto unlock_scan_queue;\n\n\t\t\tbssid_ex_sz = get_WLAN_BSSID_EX_sz(target);\n\t\t\ttarget->Length = bssid_ex_sz;\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\t\t\trtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(target->PhyInfo.Optimum_antenna), NULL);\n#endif\n\t\t\t_rtw_memcpy(&(pnetwork->network), target, bssid_ex_sz);\n\n\t\t\tpnetwork->last_scanned = rtw_get_current_time();\n\n\t\t\t/* bss info not receving from the right channel */\n\t\t\tif (pnetwork->network.PhyInfo.SignalQuality == 101)\n\t\t\t\tpnetwork->network.PhyInfo.SignalQuality = 0;\n\n\t\t\trtw_list_insert_tail(&(pnetwork->list), &(queue->queue));\n\n\t\t}\n\t} else {\n\t\t/* we have an entry and we are going to update it. But this entry may\n\t\t * be already expired. In this case we do the same as we found a new\n\t\t * net and call the new_net handler\n\t\t */\n\t\t#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT\n\t\tsystime last_scanned = pnetwork->last_scanned;\n\t\t#endif\n\n\t\tpnetwork->last_scanned = rtw_get_current_time();\n\n\t\t/* target.Reserved[0]==BSS_TYPE_BCN, means that scanned network is a bcn frame. */\n\t\tif ((pnetwork->network.IELength > target->IELength) && (target->Reserved[0] == BSS_TYPE_BCN))\n\t\t\tupdate_ie = _FALSE;\n\n\t\tif (MLME_IS_MESH(adapter)\n\t\t\t/* probe resp(3) > beacon(1) > probe req(2) */\n\t\t\t|| (target->Reserved[0] != BSS_TYPE_PROB_REQ\n\t\t\t\t&& target->Reserved[0] >= pnetwork->network.Reserved[0])\n\t\t)\n\t\t\tupdate_ie = _TRUE;\n\t\telse\n\t\t\tupdate_ie = _FALSE;\n\n\t\t#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT\n\t\tif (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter)\n\t\t\t|| pnetwork->network.Configuration.DSConfig != target->Configuration.DSConfig\n\t\t\t|| rtw_get_passing_time_ms(last_scanned) > adapter->mesh_cfg.peer_sel_policy.scanr_exp_ms\n\t\t\t|| !rtw_bss_is_same_mbss(&pnetwork->network, target)\n\t\t) {\n\t\t\tpnetwork->acnode_stime = 0;\n\t\t\tpnetwork->acnode_notify_etime = 0;\n\t\t}\n\t\t#endif\n\t\tupdate_network(&(pnetwork->network), target, adapter, update_ie);\n\t}\n\n\t#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT\n\tif (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter))\n\t\trtw_mesh_update_scanned_acnode_status(adapter, pnetwork);\n\t#endif\n\nunlock_scan_queue:\n\t_exit_critical_bh(&queue->lock, &irqL);\n\n#ifdef CONFIG_RTW_MESH\n\tif (pnetwork && MLME_IS_MESH(adapter)\n\t\t&& check_fwstate(pmlmepriv, WIFI_ASOC_STATE)\n\t\t&& !check_fwstate(pmlmepriv, WIFI_SITE_MONITOR)\n\t)\n\t\trtw_chk_candidate_peer_notify(adapter, pnetwork);\n#endif\n\n\treturn update_ie;\n}\n\nvoid rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork);\nvoid rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork)\n{\n\tbool update_ie;\n\t/* _queue\t*queue\t= &(pmlmepriv->scanned_queue); */\n\n\t/* _enter_critical_bh(&queue->lock, &irqL); */\n\n#if defined(CONFIG_P2P) && defined(CONFIG_P2P_REMOVE_GROUP_INFO)\n\tif (adapter->registrypriv.wifi_spec == 0)\n\t\trtw_bss_ex_del_p2p_attr(pnetwork, P2P_ATTR_GROUP_INFO);\n#endif\n\n\tif (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))\n\t\trtw_bss_ex_del_wfd_ie(pnetwork);\n\n\t/* Wi-Fi driver will update the current network if the scan result of the connected AP be updated by scan. */\n\tupdate_ie = rtw_update_scanned_network(adapter, pnetwork);\n\n\tif (update_ie)\n\t\tupdate_current_network(adapter, pnetwork);\n\n\t/* _exit_critical_bh(&queue->lock, &irqL); */\n\n}\n\n/* select the desired network based on the capability of the (i)bss.\n * check items: (1) security\n *\t\t\t   (2) network_type\n *\t\t\t   (3) WMM\n *\t\t\t   (4) HT\n * (5) others */\nint rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork);\nint rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork)\n{\n\tstruct security_priv *psecuritypriv = &adapter->securitypriv;\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tu32 desired_encmode;\n\tu32 privacy;\n\n\t/* u8 wps_ie[512]; */\n\tuint wps_ielen;\n\n\tint bselected = _TRUE;\n\n\tdesired_encmode = psecuritypriv->ndisencryptstatus;\n\tprivacy = pnetwork->network.Privacy;\n\n\tif (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {\n\t\tif (rtw_get_wps_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_, pnetwork->network.IELength - _FIXED_IE_LENGTH_, NULL, &wps_ielen) != NULL)\n\t\t\treturn _TRUE;\n\t\telse\n\t\t\treturn _FALSE;\n\t}\n\tif (adapter->registrypriv.wifi_spec == 1) { /* for  correct flow of 8021X  to do.... */\n\t\tu8 *p = NULL;\n\t\tuint ie_len = 0;\n\n\t\tif ((desired_encmode == Ndis802_11EncryptionDisabled) && (privacy != 0))\n\t\t\tbselected = _FALSE;\n\n\t\tif (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) {\n\t\t\tp = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_));\n\t\t\tif (p && ie_len > 0)\n\t\t\t\tbselected = _TRUE;\n\t\t\telse\n\t\t\t\tbselected = _FALSE;\n\t\t}\n\t}\n\n\n\tif ((desired_encmode != Ndis802_11EncryptionDisabled) && (privacy == 0)) {\n\t\tRTW_INFO(\"desired_encmode: %d, privacy: %d\\n\", desired_encmode, privacy);\n\t\tbselected = _FALSE;\n\t}\n\n\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {\n\t\tif (pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode)\n\t\t\tbselected = _FALSE;\n\t}\n\n\n\treturn bselected;\n}\n\n/* TODO: Perry : For Power Management */\nvoid rtw_atimdone_event_callback(_adapter\t*adapter , u8 *pbuf)\n{\n\n\treturn;\n}\n\n\nvoid rtw_survey_event_callback(_adapter\t*adapter, u8 *pbuf)\n{\n\t_irqL  irqL;\n\tu32 len;\n\tWLAN_BSSID_EX *pnetwork;\n\tstruct\tmlme_priv\t*pmlmepriv = &(adapter->mlmepriv);\n\n\n\tpnetwork = (WLAN_BSSID_EX *)pbuf;\n\n\tlen = get_WLAN_BSSID_EX_sz(pnetwork);\n\tif (len > (sizeof(WLAN_BSSID_EX))) {\n\t\treturn;\n\t}\n\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\n\t/* update IBSS_network 's timestamp */\n\tif ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) {\n\t\tif (_rtw_memcmp(&(pmlmepriv->cur_network.network.MacAddress), pnetwork->MacAddress, ETH_ALEN)) {\n\t\t\tstruct wlan_network *ibss_wlan = NULL;\n\t\t\t_irqL\tirqL;\n\n\t\t\t_rtw_memcpy(pmlmepriv->cur_network.network.IEs, pnetwork->IEs, 8);\n\t\t\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\t\t\tibss_wlan = _rtw_find_network(&pmlmepriv->scanned_queue,  pnetwork->MacAddress);\n\t\t\tif (ibss_wlan) {\n\t\t\t\t_rtw_memcpy(ibss_wlan->network.IEs , pnetwork->IEs, 8);\n\t\t\t\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\t\t}\n\t}\n\n\t/* lock pmlmepriv->lock when you accessing network_q */\n\tif ((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _FALSE) {\n\t\tif (pnetwork->Ssid.Ssid[0] == 0)\n\t\t\tpnetwork->Ssid.SsidLength = 0;\n\t\trtw_add_network(adapter, pnetwork);\n\t}\n\nexit:\n\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\n\n\treturn;\n}\n\nvoid rtw_surveydone_event_callback(_adapter\t*adapter, u8 *pbuf)\n{\n\t_irqL  irqL;\n\tstruct sitesurvey_parm parm;\n\tstruct\tmlme_priv\t*pmlmepriv = &(adapter->mlmepriv);\n#ifdef CONFIG_RTW_80211R\n\tstruct mlme_ext_priv\t*pmlmeext = &adapter->mlmeextpriv;\n#endif\n\n#ifdef CONFIG_MLME_EXT\n\tmlmeext_surveydone_event_callback(adapter);\n#endif\n\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\tif (pmlmepriv->wps_probe_req_ie) {\n\t\tu32 free_len = pmlmepriv->wps_probe_req_ie_len;\n\t\tpmlmepriv->wps_probe_req_ie_len = 0;\n\t\trtw_mfree(pmlmepriv->wps_probe_req_ie, free_len);\n\t\tpmlmepriv->wps_probe_req_ie = NULL;\n\t}\n\n\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _FALSE) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" fw_state:0x%x\\n\", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv));\n\t\t/* rtw_warn_on(1); */\n\t}\n\n\t_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\n\t_cancel_timer_ex(&pmlmepriv->scan_to_timer);\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\n#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS\n\trtw_set_signal_stat_timer(&adapter->recvpriv);\n#endif\n\n\tif (pmlmepriv->to_join == _TRUE) {\n\t\tif ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) {\n\t\t\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) {\n\t\t\t\tset_fwstate(pmlmepriv, _FW_UNDER_LINKING);\n\n\t\t\t\tif (rtw_select_and_join_from_scanned_queue(pmlmepriv) == _SUCCESS)\n\t\t\t\t\t_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);\n\t\t\t\telse {\n\t\t\t\t\tWLAN_BSSID_EX    *pdev_network = &(adapter->registrypriv.dev_network);\n\t\t\t\t\tu8 *pibss = adapter->registrypriv.dev_network.MacAddress;\n\n\t\t\t\t\t/* pmlmepriv->fw_state ^= _FW_UNDER_SURVEY; */ /* because don't set assoc_timer */\n\t\t\t\t\t_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);\n\n\n\t\t\t\t\t_rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID));\n\t\t\t\t\t_rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));\n\n\t\t\t\t\trtw_update_registrypriv_dev_network(adapter);\n\t\t\t\t\trtw_generate_random_ibss(pibss);\n\n\t\t\t\t\t/*pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;*/\n\t\t\t\t\tinit_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);\n\n\t\t\t\t\tif (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS)\n\t\t\t\t\t\tRTW_ERR(\"rtw_create_ibss_cmd FAIL\\n\");\n\n\t\t\t\t\tpmlmepriv->to_join = _FALSE;\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tint s_ret;\n\t\t\tset_fwstate(pmlmepriv, _FW_UNDER_LINKING);\n\t\t\tpmlmepriv->to_join = _FALSE;\n\t\t\ts_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv);\n\t\t\tif (_SUCCESS == s_ret)\n\t\t\t\t_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);\n\t\t\telse if (s_ret == 2) { /* there is no need to wait for join */\n\t\t\t\t_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);\n\t\t\t\trtw_indicate_connect(adapter);\n\t\t\t} else {\n\t\t\t\tRTW_INFO(\"try_to_join, but select scanning queue fail, to_roam:%d\\n\", rtw_to_roam(adapter));\n\n\t\t\t\tif (rtw_to_roam(adapter) != 0) {\n\t\t\t\t\tu8 ssc_chk = rtw_sitesurvey_condition_check(adapter, _FALSE);\n\n\t\t\t\t\trtw_init_sitesurvey_parm(adapter, &parm);\n\t\t\t\t\t_rtw_memcpy(&parm.ssid[0], &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));\n\t\t\t\t\tparm.ssid_num = 1;\n\n\t\t\t\t\tif (rtw_dec_to_roam(adapter) == 0\n\t\t\t\t\t\t|| (ssc_chk != SS_ALLOW && ssc_chk != SS_DENY_BUSY_TRAFFIC)\n\t\t\t\t\t\t|| _SUCCESS != rtw_sitesurvey_cmd(adapter, &parm)\n\t\t\t\t\t   ) {\n\t\t\t\t\t\trtw_set_to_roam(adapter, 0);\n\t\t\t\t\t\trtw_free_assoc_resources(adapter, _TRUE);\n\t\t\t\t\t\trtw_indicate_disconnect(adapter, 0, _FALSE);\n\t\t\t\t\t} else\n\t\t\t\t\t\tpmlmepriv->to_join = _TRUE;\n\t\t\t\t} else\n\t\t\t\t\trtw_indicate_disconnect(adapter, 0, _FALSE);\n\t\t\t\t_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);\n\t\t\t}\n\t\t}\n\t} else {\n\t\tif (rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) {\n\t\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE)\n\t\t\t    && check_fwstate(pmlmepriv, _FW_LINKED)) {\n\t\t\t\tif (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) {\n#ifdef CONFIG_RTW_80211R\n\t\t\t\t\trtw_ft_start_roam(adapter,\n\t\t\t\t\t\t(u8 *)pmlmepriv->roam_network->network.MacAddress);\n#else\n\t\t\t\t\treceive_disconnect(adapter, pmlmepriv->cur_network.network.MacAddress\n\t\t\t\t\t\t, WLAN_REASON_ACTIVE_ROAM, _FALSE);\n#endif\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t/* RTW_INFO(\"scan complete in %dms\\n\",rtw_get_passing_time_ms(pmlmepriv->scan_start_time)); */\n\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\n#ifdef CONFIG_P2P_PS\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\tp2p_ps_wk_cmd(adapter, P2P_PS_SCAN_DONE, 0);\n#endif /* CONFIG_P2P_PS */\n\n\trtw_mi_os_xmit_schedule(adapter);\n\n#ifdef CONFIG_DRVEXT_MODULE_WSC\n\tdrvext_surveydone_callback(&adapter->drvextpriv);\n#endif\n\n#ifdef DBG_CONFIG_ERROR_DETECT\n\t{\n\t\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\t\tif (pmlmeext->sitesurvey_res.bss_cnt == 0) {\n\t\t\t/* rtw_hal_sreset_reset(adapter); */\n\t\t}\n\t}\n#endif\n\n#ifdef CONFIG_IOCTL_CFG80211\n\trtw_cfg80211_surveydone_event_callback(adapter);\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n\trtw_indicate_scan_done(adapter, _FALSE);\n\n#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_IOCTL_CFG80211)\n\trtw_cfg80211_indicate_scan_done_for_buddy(adapter, _FALSE);\n#endif\n\n#ifdef CONFIG_RTW_MESH\n\t#if CONFIG_RTW_MESH_OFFCH_CAND\n\tif (rtw_mesh_offch_candidate_accepted(adapter)) {\n\t\tu8 ch;\n\n\t\tch = rtw_mesh_select_operating_ch(adapter);\n\t\tif (ch && pmlmepriv->cur_network.network.Configuration.DSConfig != ch) {\n\t\t\tu8 ifbmp = rtw_mi_get_ap_mesh_ifbmp(adapter);\n\n\t\t\tif (ifbmp) {\n\t\t\t\t/* switch to selected channel */\n\t\t\t\trtw_change_bss_chbw_cmd(adapter, RTW_CMDF_DIRECTLY, ifbmp, 0, ch, REQ_BW_ORI, REQ_OFFSET_NONE);\n\t\t\t\tissue_probereq_ex(adapter, &pmlmepriv->cur_network.network.mesh_id, NULL, 0, 0, 0, 0);\n\t\t\t} else\n\t\t\t\trtw_warn_on(1);\n\t\t}\n\t}\n\t#endif\n#endif /* CONFIG_RTW_MESH */\n}\n\nu8 _rtw_sitesurvey_condition_check(const char *caller, _adapter *adapter, bool check_sc_interval)\n{\n\tu8 ss_condition = SS_ALLOW;\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tstruct registry_priv *registry_par = &adapter->registrypriv;\n\n\n#ifdef CONFIG_MP_INCLUDED\n\tif (rtw_mp_mode_check(adapter)) {\n\t\tRTW_INFO(\"%s (\"ADPT_FMT\") MP mode block Scan request\\n\", caller, ADPT_ARG(adapter));\n\t\tss_condition = SS_DENY_MP_MODE;\n\t\tgoto _exit;\n\t}\n#endif\n\n#ifdef DBG_LA_MODE\n\tif(registry_par->la_mode_en == 1 && MLME_IS_ASOC(adapter)) {\n\t\tRTW_INFO(\"%s (\"ADPT_FMT\") LA debug mode block Scan request\\n\", caller, ADPT_ARG(adapter));\n\t\tss_condition = SS_DENY_LA_MODE;\n\t\tgoto _exit;\n\t}\n#endif\n\n#ifdef CONFIG_RTW_REPEATER_SON\n\tif (adapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) {\n\t\tRTW_INFO(\"%s (\"ADPT_FMT\") blocking scan for under rson scanning process\\n\", caller, ADPT_ARG(adapter));\n\t\tss_condition = SS_DENY_RSON_SCANING;\n\t\tgoto _exit;\n\t}\n#endif\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (adapter_wdev_data(adapter)->block_scan == _TRUE) {\n\t\tRTW_INFO(\"%s (\"ADPT_FMT\") wdev_priv.block_scan is set\\n\", caller, ADPT_ARG(adapter));\n\t\tss_condition = SS_DENY_BLOCK_SCAN;\n\t\tgoto _exit;\n\t}\n#endif\n\n\tif (adapter_to_dvobj(adapter)->scan_deny == _TRUE) {\n\t\tRTW_INFO(\"%s (\"ADPT_FMT\") tpt mode, scan deny!\\n\", caller, ADPT_ARG(adapter));\n\t\tss_condition = SS_DENY_BLOCK_SCAN;\n\t\tgoto _exit;\n\t}\n\n\tif (rtw_is_scan_deny(adapter)) {\n\t\tRTW_INFO(\"%s (\"ADPT_FMT\") : scan deny\\n\", caller, ADPT_ARG(adapter));\n\t\tss_condition = SS_DENY_BY_DRV;\n\t\tgoto _exit;\n\t}\n\n\tif (registry_par->adaptivity_en\n\t    && rtw_phydm_get_edcca_flag(adapter)\n\t    && rtw_is_2g_ch(GET_HAL_DATA(adapter)->current_channel)) {\n\t\tRTW_WARN(FUNC_ADPT_FMT\": Adaptivity block scan! (ch=%u)\\n\",\n\t\t\t FUNC_ADPT_ARG(adapter),\n\t\t\t GET_HAL_DATA(adapter)->current_channel);\n\t\tss_condition = SS_DENY_ADAPTIVITY;\n\t\tgoto _exit;\n\t}\n\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE)){\n\t\tif(check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {\n\t\t\tRTW_INFO(\"%s (\"ADPT_FMT\") : scan abort!! AP mode process WPS\\n\", caller, ADPT_ARG(adapter));\n\t\t\tss_condition = SS_DENY_SELF_AP_UNDER_WPS;\n\t\t\tgoto _exit;\n\t\t} else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) {\n\t\t\tRTW_INFO(\"%s (\"ADPT_FMT\") : scan abort!!AP mode under linking (fwstate=0x%x)\\n\",\n\t\t\t\tcaller, ADPT_ARG(adapter), pmlmepriv->fw_state);\n\t\t\tss_condition = SS_DENY_SELF_AP_UNDER_LINKING;\n\t\t\tgoto _exit;\n\t\t} else if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) {\n\t\t\tRTW_INFO(\"%s (\"ADPT_FMT\") : scan abort!!AP mode under survey (fwstate=0x%x)\\n\",\n\t\t\t\tcaller, ADPT_ARG(adapter), pmlmepriv->fw_state);\n\t\t\tss_condition = SS_DENY_SELF_AP_UNDER_SURVEY;\n\t\t\tgoto _exit;\n\t\t}\n\t} else {\n\t\tif (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) {\n\t\t\tRTW_INFO(\"%s (\"ADPT_FMT\") : scan abort!!STA mode under linking (fwstate=0x%x)\\n\",\n\t\t\t\tcaller, ADPT_ARG(adapter), pmlmepriv->fw_state);\n\t\t\tss_condition = SS_DENY_SELF_STA_UNDER_LINKING;\n\t\t\tgoto _exit;\n\t\t} else if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) {\n\t\t\tRTW_INFO(\"%s (\"ADPT_FMT\") : scan abort!!STA mode under survey (fwstate=0x%x)\\n\",\n\t\t\t\tcaller, ADPT_ARG(adapter), pmlmepriv->fw_state);\n\t\t\tss_condition = SS_DENY_SELF_STA_UNDER_SURVEY;\n\t\t\tgoto _exit;\n\t\t}\n\t}\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_buddy_check_fwstate(adapter, _FW_UNDER_LINKING | WIFI_UNDER_WPS)) {\n\t\tRTW_INFO(\"%s (\"ADPT_FMT\") : scan abort!! buddy_intf under linking or wps\\n\", caller, ADPT_ARG(adapter));\n\t\tss_condition = SS_DENY_BUDDY_UNDER_LINK_WPS;\n\t\tgoto _exit;\n\n\t} else if (rtw_mi_buddy_check_fwstate(adapter, _FW_UNDER_SURVEY)) {\n\t\tRTW_INFO(\"%s (\"ADPT_FMT\") : scan abort!! buddy_intf under survey\\n\", caller, ADPT_ARG(adapter));\n\t\tss_condition = SS_DENY_BUDDY_UNDER_SURVEY;\n\t\tgoto _exit;\n\t}\n#endif /* CONFIG_CONCURRENT_MODE */\n\n\tif (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE) {\n\t\tRTW_INFO(\"%s (\"ADPT_FMT\") : scan abort!! BusyTraffic\\n\",\n\t\t\t caller, ADPT_ARG(adapter));\n\t\tss_condition = SS_DENY_BUSY_TRAFFIC;\n\t\tgoto _exit;\n\t}\n\t/*\n\t * Rule for Android.\n\t * If scan interval > BUSY_TRAFFIC_SCAN_DENY_PERIOD,\n\t * it is a periodical background scan.\n\t * Skip background scan when other interface is busy.\n\t */\n\tif ((rtw_get_passing_time_ms(pmlmepriv->lastscantime) > BUSY_TRAFFIC_SCAN_DENY_PERIOD)\n\t    && rtw_mi_buddy_busy_traffic_check(adapter, _FALSE)) {\n\t\tRTW_INFO(\"%s (\"ADPT_FMT\") : scan abort!! others BusyTraffic\\n\",\n\t\t\t caller, ADPT_ARG(adapter));\n\t\tss_condition = SS_DENY_BUSY_TRAFFIC;\n\t\tgoto _exit;\n\t}\n\n_exit :\n\treturn ss_condition;\n}\n\nvoid rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf)\n{\n\n}\n\nvoid rtw_fwdbg_event_callback(_adapter *adapter , u8 *pbuf)\n{\n\n}\n\nstatic void free_scanqueue(struct\tmlme_priv *pmlmepriv)\n{\n\t_irqL irqL, irqL0;\n\t_queue *free_queue = &pmlmepriv->free_bss_pool;\n\t_queue *scan_queue = &pmlmepriv->scanned_queue;\n\t_list\t*plist, *phead, *ptemp;\n\n\n\t_enter_critical_bh(&scan_queue->lock, &irqL0);\n\t_enter_critical_bh(&free_queue->lock, &irqL);\n\n\tphead = get_list_head(scan_queue);\n\tplist = get_next(phead);\n\n\twhile (plist != phead) {\n\t\tptemp = get_next(plist);\n\t\trtw_list_delete(plist);\n\t\trtw_list_insert_tail(plist, &free_queue->queue);\n\t\tplist = ptemp;\n\t\tpmlmepriv->num_of_scanned--;\n\t}\n\n\t_exit_critical_bh(&free_queue->lock, &irqL);\n\t_exit_critical_bh(&scan_queue->lock, &irqL0);\n\n}\n\nvoid rtw_reset_rx_info(_adapter *adapter)\n{\n\tstruct recv_priv  *precvpriv = &adapter->recvpriv;\n\n\tprecvpriv->dbg_rx_ampdu_drop_count = 0;\n\tprecvpriv->dbg_rx_ampdu_forced_indicate_count = 0;\n\tprecvpriv->dbg_rx_ampdu_loss_count = 0;\n\tprecvpriv->dbg_rx_dup_mgt_frame_drop_count = 0;\n\tprecvpriv->dbg_rx_ampdu_window_shift_cnt = 0;\n\tprecvpriv->dbg_rx_drop_count = 0;\n\tprecvpriv->dbg_rx_conflic_mac_addr_cnt = 0;\n}\n\n/*\n*rtw_free_assoc_resources: the caller has to lock pmlmepriv->lock\n*/\nvoid rtw_free_assoc_resources(_adapter *adapter, u8 lock_scanned_queue)\n{\n\t_irqL irqL;\n\tstruct wlan_network *pwlan = NULL;\n\tstruct\tmlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tstruct wlan_network *tgt_network = &pmlmepriv->cur_network;\n\n\n#ifdef CONFIG_TDLS\n\tstruct tdls_info *ptdlsinfo = &adapter->tdlsinfo;\n#endif /* CONFIG_TDLS */\n\n\n\tRTW_INFO(\"%s-\"ADPT_FMT\" tgt_network MacAddress=\" MAC_FMT\" ssid=%s\\n\",\n\t\t__func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress), tgt_network->network.Ssid.Ssid);\n\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {\n\t\tstruct sta_info *psta;\n\n\t\tpsta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress);\n\n#ifdef CONFIG_TDLS\n\t\trtw_free_all_tdls_sta(adapter, _TRUE);\n\t\trtw_reset_tdls_info(adapter);\n\n\t\tif (ptdlsinfo->link_established == _TRUE)\n\t\t\trtw_tdls_cmd(adapter, NULL, TDLS_RS_RCR);\n#endif /* CONFIG_TDLS */\n\n\t\t/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */\n\t\trtw_free_stainfo(adapter, psta);\n\t\t/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */\n\n\t}\n\n\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {\n\t\tstruct sta_info *psta;\n\n\t\trtw_free_all_stainfo(adapter);\n\n\t\tpsta = rtw_get_bcmc_stainfo(adapter);\n\t\t/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\t\t */\n\t\trtw_free_stainfo(adapter, psta);\n\t\t/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\t\t */\n\n\t\trtw_init_bcmc_stainfo(adapter);\n\t}\n\n\tif (lock_scanned_queue)\n\t\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tif (check_fwstate(pmlmepriv, WIFI_UNDER_WPS) || (pmlmepriv->wpa_phase == _TRUE)){\n\t\tRTW_INFO(\"Dont free disconnecting network of scanned_queue due to uner %s %s phase\\n\\n\",\n\t\t\tcheck_fwstate(pmlmepriv, WIFI_UNDER_WPS) ? \"WPS\" : \"\",\n\t\t\t(pmlmepriv->wpa_phase == _TRUE) ? \"WPA\" : \"\");\n\t} else {\n\t\tpwlan = _rtw_find_same_network(&pmlmepriv->scanned_queue, tgt_network);\n\t\tif (pwlan) {\n\t\t\tpwlan->fixed = _FALSE;\n\n\t\t\tRTW_INFO(\"Free disconnecting network of scanned_queue\\n\");\n\t\t\trtw_free_network_nolock(adapter, pwlan);\n#ifdef CONFIG_P2P\n\t\t\tif (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) {\n\t\t\t\trtw_set_scan_deny(adapter, 2000);\n\t\t\t\t/* rtw_clear_scan_deny(adapter); */\n\t\t\t}\n#endif /* CONFIG_P2P */\n\t\t} else\n\t\t\tRTW_ERR(\"Free disconnecting network of scanned_queue failed due to pwlan == NULL\\n\\n\");\n\t}\n\n\tif ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) && (adapter->stapriv.asoc_sta_count == 1))\n\t    /*||check_fwstate(pmlmepriv, WIFI_STATION_STATE)*/) {\n\t\tif (pwlan)\n\t\t\trtw_free_network_nolock(adapter, pwlan);\n\t}\n\n\tif (lock_scanned_queue)\n\t\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tadapter->securitypriv.key_mask = 0;\n\n\trtw_reset_rx_info(adapter);\n\n\n}\n\n/*\n*rtw_indicate_connect: the caller has to lock pmlmepriv->lock\n*/\nvoid rtw_indicate_connect(_adapter *padapter)\n{\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\n\tpmlmepriv->to_join = _FALSE;\n\n\tif (!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) {\n\n\t\tset_fwstate(pmlmepriv, _FW_LINKED);\n\n\t\trtw_led_control(padapter, LED_CTL_LINK);\n\n\t\trtw_os_indicate_connect(padapter);\n\t}\n\n\trtw_set_to_roam(padapter, 0);\n\tif (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))\n\t\trtw_mi_set_scan_deny(padapter, 3000);\n\n\n}\n\n\n/*\n*rtw_indicate_disconnect: the caller has to lock pmlmepriv->lock\n*/\nvoid rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated)\n{\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t*cur_network = &(pmlmeinfo->network);\n#ifdef CONFIG_WAPI_SUPPORT\n\tstruct sta_info *psta;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n#endif\n\tu8 *wps_ie = NULL;\n\tuint wpsie_len = 0;\n\n\tif (check_fwstate(pmlmepriv, WIFI_UNDER_WPS))\n\t\tpmlmepriv->wpa_phase = _TRUE;\n\n\t_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING | WIFI_UNDER_WPS | WIFI_OP_CH_SWITCHING | WIFI_UNDER_KEY_HANDSHAKE);\n\n\t/* force to clear cur_network_scanned's SELECTED REGISTRAR */\n\tif (pmlmepriv->cur_network_scanned) {\n\t\tWLAN_BSSID_EX\t*current_joined_bss = &(pmlmepriv->cur_network_scanned->network);\n\t\tif (current_joined_bss) {\n\t\t\twps_ie = rtw_get_wps_ie(current_joined_bss->IEs + _FIXED_IE_LENGTH_,\n\t\t\t\tcurrent_joined_bss->IELength - _FIXED_IE_LENGTH_, NULL, &wpsie_len);\n\t\t\tif (wps_ie && wpsie_len > 0) {\n\t\t\t\tu8 *attr = NULL;\n\t\t\t\tu32 attr_len;\n\t\t\t\tattr = rtw_get_wps_attr(wps_ie, wpsie_len, WPS_ATTR_SELECTED_REGISTRAR,\n\t\t\t\t\t\t\tNULL, &attr_len);\n\t\t\t\tif (attr)\n\t\t\t\t\t*(attr + 4) = 0;\n\t\t\t}\n\t\t}\n\t}\n\t/* RTW_INFO(\"clear wps when %s\\n\", __func__); */\n\n\tif (rtw_to_roam(padapter) > 0)\n\t\t_clr_fwstate_(pmlmepriv, _FW_LINKED);\n\n#ifdef CONFIG_WAPI_SUPPORT\n\tpsta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE))\n\t\trtw_wapi_return_one_sta_info(padapter, psta->cmn.mac_addr);\n\telse if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) ||\n\t\t check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE))\n\t\trtw_wapi_return_all_sta_info(padapter);\n#endif\n\n\tif (check_fwstate(&padapter->mlmepriv, _FW_LINKED)\n\t    || (rtw_to_roam(padapter) <= 0)\n\t   ) {\n\n\t\trtw_os_indicate_disconnect(padapter, reason, locally_generated);\n\n\t\t/* set ips_deny_time to avoid enter IPS before LPS leave */\n\t\trtw_set_ips_deny(padapter, 3000);\n\n\t\t_clr_fwstate_(pmlmepriv, _FW_LINKED);\n\n\t\trtw_led_control(padapter, LED_CTL_NO_LINK);\n\n\t\trtw_clear_scan_deny(padapter);\n\t}\n\n#ifdef CONFIG_P2P_PS\n\tp2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1);\n#endif /* CONFIG_P2P_PS */\n\n#ifdef CONFIG_LPS\n\trtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_DISCONNECT, 0);\n#endif\n\n#ifdef CONFIG_BEAMFORMING\n\tbeamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, cur_network->MacAddress, ETH_ALEN, 1);\n#endif /*CONFIG_BEAMFORMING*/\n\n}\n\ninline void rtw_indicate_scan_done(_adapter *padapter, bool aborted)\n{\n\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n\n\trtw_os_indicate_scan_done(padapter, aborted);\n\n#ifdef CONFIG_IPS\n\tif (is_primary_adapter(padapter)\n\t    && (_FALSE == adapter_to_pwrctl(padapter)->bInSuspend)\n\t    && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE | WIFI_UNDER_LINKING) == _FALSE)) {\n\t\tstruct pwrctrl_priv *pwrpriv;\n\n\t\tpwrpriv = adapter_to_pwrctl(padapter);\n\t\trtw_set_ips_deny(padapter, 0);\n#ifdef CONFIG_IPS_CHECK_IN_WD\n\t\t_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 1);\n#else /* !CONFIG_IPS_CHECK_IN_WD */\n\t\t_rtw_set_pwr_state_check_timer(pwrpriv, 1);\n#endif /* !CONFIG_IPS_CHECK_IN_WD */\n\t}\n#endif /* CONFIG_IPS */\n}\n\nstatic u32 _rtw_wait_scan_done(_adapter *adapter, u8 abort, u32 timeout_ms)\n{\n\tsystime start;\n\tu32 pass_ms;\n\tstruct mlme_priv *pmlmepriv = &(adapter->mlmepriv);\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\n\tstart = rtw_get_current_time();\n\n\tpmlmeext->scan_abort = abort;\n\n\twhile (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)\n\t       && rtw_get_passing_time_ms(start) <= timeout_ms) {\n\n\t\tif (RTW_CANNOT_RUN(adapter))\n\t\t\tbreak;\n\n\t\tRTW_INFO(FUNC_NDEV_FMT\"fw_state=_FW_UNDER_SURVEY!\\n\", FUNC_NDEV_ARG(adapter->pnetdev));\n\t\trtw_msleep_os(20);\n\t}\n\n\tif (_TRUE == abort) {\n\t\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) {\n\t\t\tif (!RTW_CANNOT_RUN(adapter))\n\t\t\t\tRTW_INFO(FUNC_NDEV_FMT\"waiting for scan_abort time out!\\n\", FUNC_NDEV_ARG(adapter->pnetdev));\n#ifdef CONFIG_PLATFORM_MSTAR\n\t\t\t/*_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);*/\n\t\t\tset_survey_timer(pmlmeext, 0);\n\t\t\tmlme_set_scan_to_timer(pmlmepriv, 50);\n#endif\n\t\t\trtw_indicate_scan_done(adapter, _TRUE);\n\t\t}\n\t}\n\n\tpmlmeext->scan_abort = _FALSE;\n\tpass_ms = rtw_get_passing_time_ms(start);\n\n\treturn pass_ms;\n\n}\n\nvoid rtw_scan_wait_completed(_adapter *adapter)\n{\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct ss_res *ss = &pmlmeext->sitesurvey_res;\n\n\t_rtw_wait_scan_done(adapter, _FALSE, ss->scan_timeout_ms);\n}\n\nu32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms)\n{\n\treturn _rtw_wait_scan_done(adapter, _TRUE, timeout_ms);\n}\n\nvoid rtw_scan_abort_no_wait(_adapter *adapter)\n{\n\tstruct mlme_priv *pmlmepriv = &(adapter->mlmepriv);\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))\n\t\tpmlmeext->scan_abort = _TRUE;\n}\n\nvoid rtw_scan_abort(_adapter *adapter)\n{\n\trtw_scan_abort_timeout(adapter, 200);\n}\n\nstatic u32 _rtw_wait_join_done(_adapter *adapter, u8 abort, u32 timeout_ms)\n{\n\tsystime start;\n\tu32 pass_ms;\n\tstruct mlme_priv *pmlmepriv = &(adapter->mlmepriv);\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\n\tstart = rtw_get_current_time();\n\n\tpmlmeext->join_abort = abort;\n\tif (abort)\n\t\tset_link_timer(pmlmeext, 1);\n\n\twhile (rtw_get_passing_time_ms(start) <= timeout_ms\n\t\t&& (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)\n\t\t\t#ifdef CONFIG_IOCTL_CFG80211\n\t\t\t|| rtw_cfg80211_is_connect_requested(adapter)\n\t\t\t#endif\n\t\t\t)\n\t) {\n\t\tif (RTW_CANNOT_RUN(adapter))\n\t\t\tbreak;\n\n\t\tRTW_INFO(FUNC_ADPT_FMT\" linking...\\n\", FUNC_ADPT_ARG(adapter));\n\t\trtw_msleep_os(20);\n\t}\n\n\tif (abort) {\n\t\tif (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)\n\t\t\t#ifdef CONFIG_IOCTL_CFG80211\n\t\t\t|| rtw_cfg80211_is_connect_requested(adapter)\n\t\t\t#endif\n\t\t) {\n\t\t\tif (!RTW_CANNOT_RUN(adapter))\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" waiting for join_abort time out!\\n\", FUNC_ADPT_ARG(adapter));\n\t\t}\n\t}\n\n\tpmlmeext->join_abort = 0;\n\tpass_ms = rtw_get_passing_time_ms(start);\n\n\treturn pass_ms;\n}\n\nu32 rtw_join_abort_timeout(_adapter *adapter, u32 timeout_ms)\n{\n\treturn _rtw_wait_join_done(adapter, _TRUE, timeout_ms);\n}\n\nstatic struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wlan_network *pnetwork)\n{\n\tint i;\n\tstruct sta_info *psta = NULL;\n\tstruct recv_reorder_ctrl *preorder_ctrl;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n#ifdef CONFIG_RTS_FULL_BW\n\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tstruct wlan_network  *cur_network = &(pmlmepriv->cur_network);\n#endif/*CONFIG_RTS_FULL_BW*/\n\n\tpsta = rtw_get_stainfo(pstapriv, pnetwork->network.MacAddress);\n\tif (psta == NULL)\n\t\tpsta = rtw_alloc_stainfo(pstapriv, pnetwork->network.MacAddress);\n\n\tif (psta) { /* update ptarget_sta */\n\t\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\t\tpsta->cmn.aid  = pnetwork->join_res;\n\n\t\tupdate_sta_info(padapter, psta);\n\n\t\t/* update station supportRate */\n\t\tpsta->bssratelen = rtw_get_rateset_len(pnetwork->network.SupportedRates);\n\t\t_rtw_memcpy(psta->bssrateset, pnetwork->network.SupportedRates, psta->bssratelen);\n\t\trtw_hal_update_sta_ra_info(padapter, psta);\n\n\t\tpsta->wireless_mode = pmlmeext->cur_wireless_mode;\n\t\trtw_hal_update_sta_wset(padapter, psta);\n\n\t\t/* sta mode */\n\t\trtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);\n\n\t\t/* security related */\n#ifdef CONFIG_RTW_80211R\n\t\tif ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)\n\t\t\t&& (psta->ft_pairwise_key_installed == _FALSE)) {\n#else\n\t\tif (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) {\n#endif\n\t\t\tu8 *ie;\n\t\t\tsint ie_len;\n\t\t\tu8 mfp_opt = MFP_NO;\n\n\t\t\tpadapter->securitypriv.binstallGrpkey = _FALSE;\n\t\t\tpadapter->securitypriv.busetkipkey = _FALSE;\n\t\t\tpadapter->securitypriv.bgrpkey_handshake = _FALSE;\n\n\t\t\tie = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, WLAN_EID_RSN\n\t\t\t\t, &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_));\n\t\t\tif (ie && ie_len > 0\n\t\t\t\t&& rtw_parse_wpa2_ie(ie, ie_len + 2, NULL, NULL, NULL, &mfp_opt) == _SUCCESS\n\t\t\t) {\n\t\t\t\tif (padapter->securitypriv.mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL)\n\t\t\t\t\tpsta->flags |= WLAN_STA_MFP;\n\t\t\t}\n\n\t\t\tpsta->ieee8021x_blocked = _TRUE;\n\t\t\tpsta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;\n\n\t\t\t_rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof(union Keytype));\n\t\t\t_rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof(union Keytype));\n\t\t\t_rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof(union Keytype));\n\t\t}\n\n\t\t/*\tCommented by Albert 2012/07/21 */\n\t\t/*\tWhen doing the WPS, the wps_ie_len won't equal to 0 */\n\t\t/*\tAnd the Wi-Fi driver shouldn't allow the data packet to be tramsmitted. */\n\t\tif (padapter->securitypriv.wps_ie_len != 0) {\n\t\t\tpsta->ieee8021x_blocked = _TRUE;\n\t\t\tpadapter->securitypriv.wps_ie_len = 0;\n\t\t}\n\n\n\t\t/* for A-MPDU Rx reordering buffer control for sta_info */\n\t\t/* if A-MPDU Rx is enabled, reseting  rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff */\n\t\t/* todo: check if AP can send A-MPDU packets */\n\t\tfor (i = 0; i < 16 ; i++) {\n\t\t\t/* preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; */\n\t\t\tpreorder_ctrl = &psta->recvreorder_ctrl[i];\n\t\t\tpreorder_ctrl->enable = _FALSE;\n\t\t\tpreorder_ctrl->indicate_seq = 0xffff;\n\t\t\trtw_clear_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack);\n\t\t\t#ifdef DBG_RX_SEQ\n\t\t\tRTW_INFO(\"DBG_RX_SEQ \"FUNC_ADPT_FMT\" tid:%u SN_CLEAR indicate_seq:%u preorder_ctrl->rec_abba_rsp_ack:%lu\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter)\n\t\t\t\t, i\n\t\t\t\t, preorder_ctrl->indicate_seq\n\t\t\t\t,preorder_ctrl->rec_abba_rsp_ack\n\t\t\t\t);\n\t\t\t#endif\n\t\t\tpreorder_ctrl->wend_b = 0xffff;\n\t\t\tpreorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */\n\t\t\tpreorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID;\n\t\t}\n\t}\n\n#ifdef\tCONFIG_RTW_80211K\n\t_rtw_memcpy(&psta->rm_en_cap, pnetwork->network.PhyInfo.rm_en_cap, 5);\n#endif\n#ifdef CONFIG_RTS_FULL_BW\n\trtw_parse_sta_vendor_ie_8812(padapter, psta, BSS_EX_TLV_IES(&cur_network->network), BSS_EX_TLV_IES_LEN(&cur_network->network));\n#endif\n\treturn psta;\n\n}\n\n/* pnetwork : returns from rtw_joinbss_event_callback\n * ptarget_wlan: found from scanned_queue */\nstatic void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network *ptarget_wlan, struct wlan_network  *pnetwork)\n{\n\tstruct mlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tstruct wlan_network  *cur_network = &(pmlmepriv->cur_network);\n\tsint tmp_fw_state = 0x0;\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\t/* why not use ptarget_wlan?? */\n\t_rtw_memcpy(&cur_network->network, &pnetwork->network, pnetwork->network.Length);\n\t/* some IEs in pnetwork is wrong, so we should use ptarget_wlan IEs */\n\tcur_network->network.IELength = ptarget_wlan->network.IELength;\n\t_rtw_memcpy(&cur_network->network.IEs[0], &ptarget_wlan->network.IEs[0], MAX_IE_SZ);\n\n\tcur_network->aid = pnetwork->join_res;\n\n\n#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS\n\trtw_set_signal_stat_timer(&padapter->recvpriv);\n#endif\n\tpadapter->recvpriv.signal_strength = ptarget_wlan->network.PhyInfo.SignalStrength;\n\tpadapter->recvpriv.signal_qual = ptarget_wlan->network.PhyInfo.SignalQuality;\n\t/* the ptarget_wlan->network.Rssi is raw data, we use ptarget_wlan->network.PhyInfo.SignalStrength instead (has scaled) */\n\tpadapter->recvpriv.rssi = translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength);\n#if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1\n\tRTW_INFO(FUNC_ADPT_FMT\" signal_strength:%3u, rssi:%3d, signal_qual:%3u\"\n\t\t \"\\n\"\n\t\t , FUNC_ADPT_ARG(padapter)\n\t\t , padapter->recvpriv.signal_strength\n\t\t , padapter->recvpriv.rssi\n\t\t , padapter->recvpriv.signal_qual\n\t\t);\n#endif\n#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS\n\trtw_set_signal_stat_timer(&padapter->recvpriv);\n#endif\n\n\t/* update fw_state */ /* will clr _FW_UNDER_LINKING here indirectly */\n\n\tswitch (pnetwork->network.InfrastructureMode) {\n\tcase Ndis802_11Infrastructure:\n\t\t/* Check encryption */\n\t\tif (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)\n\t\t\ttmp_fw_state = tmp_fw_state | WIFI_UNDER_KEY_HANDSHAKE;\n\n\t\tif (check_fwstate(pmlmepriv, WIFI_UNDER_WPS))\n\t\t\ttmp_fw_state = tmp_fw_state | WIFI_UNDER_WPS;\n\n\t\tinit_fwstate(pmlmepriv, WIFI_STATION_STATE | tmp_fw_state);\n\n\t\tbreak;\n\tcase Ndis802_11IBSS:\n\t\t/*pmlmepriv->fw_state = WIFI_ADHOC_STATE;*/\n\t\tinit_fwstate(pmlmepriv, WIFI_ADHOC_STATE);\n\t\tbreak;\n\tdefault:\n\t\t/*pmlmepriv->fw_state = WIFI_NULL_STATE;*/\n\t\tinit_fwstate(pmlmepriv, WIFI_NULL_STATE);\n\t\tbreak;\n\t}\n\n\trtw_update_protection(padapter, (cur_network->network.IEs) + sizeof(NDIS_802_11_FIXED_IEs),\n\t\t\t      (cur_network->network.IELength));\n\n#ifdef CONFIG_80211N_HT\n\trtw_update_ht_cap(padapter, cur_network->network.IEs, cur_network->network.IELength, (u8) cur_network->network.Configuration.DSConfig);\n#endif\n}\n\n/* Notes: the fucntion could be > passive_level (the same context as Rx tasklet)\n * pnetwork : returns from rtw_joinbss_event_callback\n * ptarget_wlan: found from scanned_queue\n * if join_res > 0, for (fw_state==WIFI_STATION_STATE), we check if  \"ptarget_sta\" & \"ptarget_wlan\" exist.\n * if join_res > 0, for (fw_state==WIFI_ADHOC_STATE), we only check if \"ptarget_wlan\" exist.\n * if join_res > 0, update \"cur_network->network\" from \"pnetwork->network\" if (ptarget_wlan !=NULL).\n */\n/* #define REJOIN */\nvoid rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status)\n{\n\t_irqL irqL;\n\tstatic u8 retry = 0;\n\tstruct sta_info *ptarget_sta = NULL, *pcur_sta = NULL;\n\tstruct\tsta_priv *pstapriv = &adapter->stapriv;\n\tstruct\tmlme_priv\t*pmlmepriv = &(adapter->mlmepriv);\n\tstruct wlan_network\t*pnetwork\t= (struct wlan_network *)pbuf;\n\tstruct wlan_network\t*cur_network = &(pmlmepriv->cur_network);\n\tstruct wlan_network\t*pcur_wlan = NULL, *ptarget_wlan = NULL;\n\tunsigned int\t\tthe_same_macaddr = _FALSE;\n\n\trtw_get_encrypt_decrypt_from_registrypriv(adapter);\n\n\tthe_same_macaddr = _rtw_memcmp(pnetwork->network.MacAddress, cur_network->network.MacAddress, ETH_ALEN);\n\n\tpnetwork->network.Length = get_WLAN_BSSID_EX_sz(&pnetwork->network);\n\tif (pnetwork->network.Length > sizeof(WLAN_BSSID_EX))\n\t\tgoto exit;\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\n\tpmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0;\n\tpmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0;\n\n\n\tif (pnetwork->join_res > 0) {\n\t\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\t\tretry = 0;\n\t\tif (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) {\n\t\t\t/* s1. find ptarget_wlan */\n\t\t\tif (check_fwstate(pmlmepriv, _FW_LINKED)) {\n\t\t\t\tif (the_same_macaddr == _TRUE)\n\t\t\t\t\tptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);\n\t\t\t\telse {\n\t\t\t\t\tpcur_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);\n\t\t\t\t\tif (pcur_wlan)\n\t\t\t\t\t\tpcur_wlan->fixed = _FALSE;\n\n\t\t\t\t\tpcur_sta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);\n\t\t\t\t\tif (pcur_sta) {\n\t\t\t\t\t\t/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */\n\t\t\t\t\t\trtw_free_stainfo(adapter,  pcur_sta);\n\t\t\t\t\t\t/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */\n\t\t\t\t\t}\n\n\t\t\t\t\tptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress);\n\t\t\t\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {\n\t\t\t\t\t\tif (ptarget_wlan)\n\t\t\t\t\t\t\tptarget_wlan->fixed = _TRUE;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t} else {\n\t\t\t\tptarget_wlan = _rtw_find_same_network(&pmlmepriv->scanned_queue, pnetwork);\n\t\t\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {\n\t\t\t\t\tif (ptarget_wlan)\n\t\t\t\t\t\tptarget_wlan->fixed = _TRUE;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* s2. update cur_network */\n\t\t\tif (ptarget_wlan)\n\t\t\t\trtw_joinbss_update_network(adapter, ptarget_wlan, pnetwork);\n\t\t\telse {\n\t\t\t\tRTW_PRINT(\"Can't find ptarget_wlan when joinbss_event callback\\n\");\n\t\t\t\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\t\t\t\tgoto ignore_joinbss_callback;\n\t\t\t}\n\n\n\t\t\t/* s3. find ptarget_sta & update ptarget_sta after update cur_network only for station mode */\n\t\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {\n\t\t\t\tptarget_sta = rtw_joinbss_update_stainfo(adapter, pnetwork);\n\t\t\t\tif (ptarget_sta == NULL) {\n\t\t\t\t\tRTW_ERR(\"Can't update stainfo when joinbss_event callback\\n\");\n\t\t\t\t\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\t\t\t\t\tgoto ignore_joinbss_callback;\n\t\t\t\t}\n\n\t\t\t\t/* Queue TX packets before FW/HW ready */\n\t\t\t\t/* clear in mlmeext_joinbss_event_callback() */\n\t\t\t\trtw_xmit_queue_set(ptarget_sta);\n\t\t\t}\n\n\t\t\t/* s4. indicate connect\t\t\t */\n\t\t\tif (MLME_IS_STA(adapter) || MLME_IS_ADHOC(adapter)) {\n\t\t\t\tpmlmepriv->cur_network_scanned = ptarget_wlan;\n\t\t\t\trtw_indicate_connect(adapter);\n\t\t\t}\n\n\t\t\t/* s5. Cancle assoc_timer\t\t\t\t\t */\n\t\t\t_cancel_timer_ex(&pmlmepriv->assoc_timer);\n\n\n\t\t} else {\n\t\t\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\t\t\tgoto ignore_joinbss_callback;\n\t\t}\n\n\t\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\t} else if (pnetwork->join_res == -4) {\n\t\trtw_reset_securitypriv(adapter);\n\t\tpmlmepriv->join_status = status;\n\t\t_set_timer(&pmlmepriv->assoc_timer, 1);\n\n\t\t/* rtw_free_assoc_resources(adapter, _TRUE); */\n\n\t\tif ((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _TRUE) {\n\t\t\t_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);\n\t\t}\n\n\t} else { /* if join_res < 0 (join fails), then try again */\n\n#ifdef REJOIN\n\t\tres = _FAIL;\n\t\tif (retry < 2) {\n\t\t\tres = rtw_select_and_join_from_scanned_queue(pmlmepriv);\n\t\t}\n\n\t\tif (res == _SUCCESS) {\n\t\t\t/* extend time of assoc_timer */\n\t\t\t_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);\n\t\t\tretry++;\n\t\t} else if (res == 2) { /* there is no need to wait for join */\n\t\t\t_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);\n\t\t\trtw_indicate_connect(adapter);\n\t\t} else {\n#endif\n\t\t\tpmlmepriv->join_status = status;\n\t\t\t_set_timer(&pmlmepriv->assoc_timer, 1);\n\t\t\t/* rtw_free_assoc_resources(adapter, _TRUE); */\n\t\t\t_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);\n\n#ifdef REJOIN\n\t\t\tretry = 0;\n\t\t}\n#endif\n\t}\n\nignore_joinbss_callback:\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\nexit:\n\treturn;\n}\n\nvoid rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf)\n{\n\tstruct wlan_network\t*pnetwork\t= (struct wlan_network *)pbuf;\n\n\n\tmlmeext_joinbss_event_callback(adapter, pnetwork->join_res);\n\n\trtw_mi_os_xmit_schedule(adapter);\n\n}\n\nvoid rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool connected)\n{\n\tstruct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;\n\tbool miracast_enabled = 0;\n\tbool miracast_sink = 0;\n\tu8 role = H2C_MSR_ROLE_RSVD;\n\n\tif (sta == NULL) {\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" sta is NULL\\n\"\n\t\t\t  , FUNC_ADPT_ARG(adapter));\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tif (sta->cmn.mac_id >= macid_ctl->num) {\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" invalid macid:%u\\n\"\n\t\t\t  , FUNC_ADPT_ARG(adapter), sta->cmn.mac_id);\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tif (!rtw_macid_is_used(macid_ctl, sta->cmn.mac_id)) {\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" macid:%u not is used, set connected to 0\\n\"\n\t\t\t  , FUNC_ADPT_ARG(adapter), sta->cmn.mac_id);\n\t\tconnected = 0;\n\t\trtw_warn_on(1);\n\t}\n\n\tif (connected && !rtw_macid_is_bmc(macid_ctl, sta->cmn.mac_id)) {\n\t\tmiracast_enabled = STA_OP_WFD_MODE(sta) != 0 && is_miracast_enabled(adapter);\n\t\tmiracast_sink = miracast_enabled && (STA_OP_WFD_MODE(sta) & MIRACAST_SINK);\n\n#ifdef CONFIG_TDLS\n\t\tif (sta->tdls_sta_state & TDLS_LINKED_STATE)\n\t\t\trole = H2C_MSR_ROLE_TDLS;\n\t\telse\n#endif\n\t\tif (MLME_IS_STA(adapter)) {\n\t\t\tif (MLME_IS_GC(adapter))\n\t\t\t\trole = H2C_MSR_ROLE_GO;\n\t\t\telse\n\t\t\t\trole = H2C_MSR_ROLE_AP;\n\t\t} else if (MLME_IS_AP(adapter)) {\n\t\t\tif (MLME_IS_GO(adapter))\n\t\t\t\trole = H2C_MSR_ROLE_GC;\n\t\t\telse\n\t\t\t\trole = H2C_MSR_ROLE_STA;\n\t\t} else if (MLME_IS_ADHOC(adapter) || MLME_IS_ADHOC_MASTER(adapter))\n\t\t\trole = H2C_MSR_ROLE_ADHOC;\n\t\telse if (MLME_IS_MESH(adapter))\n\t\t\trole = H2C_MSR_ROLE_MESH;\n\n#ifdef CONFIG_WFD\n\t\tif (role == H2C_MSR_ROLE_GC\n\t\t\t|| role == H2C_MSR_ROLE_GO\n\t\t\t|| role == H2C_MSR_ROLE_TDLS\n\t\t) {\n\t\t\tif (adapter->wfd_info.rtsp_ctrlport\n\t\t\t\t|| adapter->wfd_info.tdls_rtsp_ctrlport\n\t\t\t\t|| adapter->wfd_info.peer_rtsp_ctrlport)\n\t\t\t\trtw_wfd_st_switch(sta, 1);\n\t\t}\n#endif\n\t}\n\n\trtw_hal_set_FwMediaStatusRpt_single_cmd(adapter\n\t\t, connected\n\t\t, miracast_enabled\n\t\t, miracast_sink\n\t\t, role\n\t\t, sta->cmn.mac_id\n\t);\n}\n\nu8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected)\n{\n\tstruct cmd_priv\t*cmdpriv = &adapter->cmdpriv;\n\tstruct cmd_obj *cmdobj;\n\tstruct drvextra_cmd_parm *cmd_parm;\n\tstruct sta_media_status_rpt_cmd_parm *rpt_parm;\n\tu8\tres = _SUCCESS;\n\n\tcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (cmdobj == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tcmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (cmd_parm == NULL) {\n\t\trtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\trpt_parm = (struct sta_media_status_rpt_cmd_parm *)rtw_zmalloc(sizeof(struct sta_media_status_rpt_cmd_parm));\n\tif (rpt_parm == NULL) {\n\t\trtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));\n\t\trtw_mfree((u8 *)cmd_parm, sizeof(struct drvextra_cmd_parm));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\trpt_parm->sta = sta;\n\trpt_parm->connected = connected;\n\n\tcmd_parm->ec_id = STA_MSTATUS_RPT_WK_CID;\n\tcmd_parm->type = 0;\n\tcmd_parm->size = sizeof(struct sta_media_status_rpt_cmd_parm);\n\tcmd_parm->pbuf = (u8 *)rpt_parm;\n\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\tres = rtw_enqueue_cmd(cmdpriv, cmdobj);\n\nexit:\n\treturn res;\n}\n\ninline void rtw_sta_media_status_rpt_cmd_hdl(_adapter *adapter, struct sta_media_status_rpt_cmd_parm *parm)\n{\n\trtw_sta_media_status_rpt(adapter, parm->sta, parm->connected);\n}\n\nvoid rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf)\n{\n\t_irqL irqL;\n\tstruct sta_info *psta;\n\tstruct mlme_priv *pmlmepriv = &(adapter->mlmepriv);\n\tstruct stassoc_event\t*pstassoc\t= (struct stassoc_event *)pbuf;\n\tstruct wlan_network\t*cur_network = &(pmlmepriv->cur_network);\n\tstruct wlan_network\t*ptarget_wlan = NULL;\n\n\n#if CONFIG_RTW_MACADDR_ACL\n\tif (rtw_access_ctrl(adapter, pstassoc->macaddr) == _FALSE)\n\t\treturn;\n#endif\n\n#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)\n\tif (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {\n\t\tpsta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr);\n\t\tif (psta) {\n\t\t\tu8 *passoc_req = NULL;\n\t\t\tu32 assoc_req_len = 0;\n\n\t\t\trtw_sta_media_status_rpt(adapter, psta, 1);\n\n#ifdef CONFIG_MCC_MODE\n\t\t\trtw_hal_mcc_update_macid_bitmap(adapter, psta->cmn.mac_id, _TRUE);\n#endif /* CONFIG_MCC_MODE */\n\n#ifndef CONFIG_AUTO_AP_MODE\n\t\t\tap_sta_info_defer_update(adapter, psta);\n\n\t\t\tif (!MLME_IS_MESH(adapter)) {\n\t\t\t\t/* report to upper layer */\n\t\t\t\tRTW_INFO(\"indicate_sta_assoc_event to upper layer - hostapd\\n\");\n\t\t\t\t#ifdef CONFIG_IOCTL_CFG80211\n\t\t\t\t_enter_critical_bh(&psta->lock, &irqL);\n\t\t\t\tif (psta->passoc_req && psta->assoc_req_len > 0) {\n\t\t\t\t\tpassoc_req = rtw_zmalloc(psta->assoc_req_len);\n\t\t\t\t\tif (passoc_req) {\n\t\t\t\t\t\tassoc_req_len = psta->assoc_req_len;\n\t\t\t\t\t\t_rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len);\n\n\t\t\t\t\t\trtw_mfree(psta->passoc_req , psta->assoc_req_len);\n\t\t\t\t\t\tpsta->passoc_req = NULL;\n\t\t\t\t\t\tpsta->assoc_req_len = 0;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t_exit_critical_bh(&psta->lock, &irqL);\n\n\t\t\t\tif (passoc_req && assoc_req_len > 0) {\n\t\t\t\t\trtw_cfg80211_indicate_sta_assoc(adapter, passoc_req, assoc_req_len);\n\t\t\t\t\trtw_mfree(passoc_req, assoc_req_len);\n\t\t\t\t}\n\t\t\t\t#else /* !CONFIG_IOCTL_CFG80211\t */\n\t\t\t\trtw_indicate_sta_assoc_event(adapter, psta);\n\t\t\t\t#endif /* !CONFIG_IOCTL_CFG80211 */\n\t\t\t}\n#endif /* !CONFIG_AUTO_AP_MODE */\n\n#ifdef CONFIG_BEAMFORMING\n\t\t\tbeamforming_wk_cmd(adapter, BEAMFORMING_CTRL_ENTER, (u8 *)psta, sizeof(struct sta_info), 0);\n#endif/*CONFIG_BEAMFORMING*/\n\t\t\tif (is_wep_enc(adapter->securitypriv.dot11PrivacyAlgrthm))\n\t\t\t\trtw_ap_wep_pk_setting(adapter, psta);\n\t\t}\n\t\tgoto exit;\n\t}\n#endif /* defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */\n\n\t/* for AD-HOC mode */\n\tpsta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr);\n\tif (psta == NULL) {\n\t\tRTW_ERR(FUNC_ADPT_FMT\" get no sta_info with \"MAC_FMT\"\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(pstassoc->macaddr));\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\trtw_sta_media_status_rpt(adapter, psta, 1);\n\n\tif (adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)\n\t\tpsta->dot118021XPrivacy = adapter->securitypriv.dot11PrivacyAlgrthm;\n\n\n\tpsta->ieee8021x_blocked = _FALSE;\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\n\tif ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||\n\t    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) {\n\t\tif (adapter->stapriv.asoc_sta_count == 2) {\n\t\t\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\t\t\tptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);\n\t\t\tpmlmepriv->cur_network_scanned = ptarget_wlan;\n\t\t\tif (ptarget_wlan)\n\t\t\t\tptarget_wlan->fixed = _TRUE;\n\t\t\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\t\t\t/* a sta + bc/mc_stainfo (not Ibss_stainfo) */\n\t\t\trtw_indicate_connect(adapter);\n\t\t}\n\t}\n\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\n\n\tmlmeext_sta_add_event_callback(adapter, psta);\n\n#ifdef CONFIG_RTL8711\n\t/* submit SetStaKey_cmd to tell fw, fw will allocate an CAM entry for this sta\t */\n\trtw_setstakey_cmd(adapter, psta, GROUP_KEY, _TRUE);\n#endif\n\nexit:\n#ifdef CONFIG_RTS_FULL_BW\n\trtw_set_rts_bw(adapter);\n#endif/*CONFIG_RTS_FULL_BW*/\n\treturn;\n}\n\n#ifdef CONFIG_IEEE80211W\nvoid rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf)\n{\n\t_irqL irqL;\n\tstruct sta_info *psta;\n\tstruct stadel_event *pstadel = (struct stadel_event *)pbuf;\n\tstruct sta_priv *pstapriv = &adapter->stapriv;\n\n\n\tpsta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr);\n\n\tif (psta) {\n\t\tu8 updated = _FALSE;\n\n\t\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\t\tif (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {\n\t\t\trtw_list_delete(&psta->asoc_list);\n\t\t\tpstapriv->asoc_list_cnt--;\n\t\t\tupdated = ap_free_sta(adapter, psta, _TRUE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE);\n\t\t}\n\t\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\t\tassociated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL);\n\t}\n\n\n\n}\n#endif /* CONFIG_IEEE80211W */\n\n#ifdef CONFIG_RTW_80211R\nvoid rtw_ft_info_init(struct ft_roam_info *pft)\n{\n\t_rtw_memset(pft, 0, sizeof(struct ft_roam_info));\n\tpft->ft_flags = 0\n\t\t| RTW_FT_EN\n\t\t| RTW_FT_OTD_EN\n#ifdef CONFIG_RTW_BTM_ROAM\n\t\t| RTW_FT_BTM_ROAM\n#endif\n\t\t;\n\tpft->ft_updated_bcn = _FALSE;\n}\n\nu8 rtw_ft_chk_roaming_candidate(\n\t_adapter *padapter, struct wlan_network *competitor)\n{\n\tu8 *pmdie;\n\tu32 mdie_len = 0;\n\tstruct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);\n\n\tif (!(pmdie = rtw_get_ie(&competitor->network.IEs[12],\n\t\t\t_MDIE_, &mdie_len, competitor->network.IELength-12)))\n\t\treturn _FALSE;\n\n\tif (!_rtw_memcmp(&pft_roam->mdid, (pmdie+2), 2))\n\t\treturn _FALSE;\n\n\t/*The candidate don't support over-the-DS*/\n\tif (rtw_ft_valid_otd_candidate(padapter, pmdie)) {\n\t\tRTW_INFO(\"FT: ignore the candidate(\"\n\t\t\tMAC_FMT \") for over-the-DS\\n\", \n\t\t\tMAC_ARG(competitor->network.MacAddress));\n\t\t\trtw_ft_clr_flags(padapter, RTW_FT_PEER_OTD_EN);\n\t\treturn _FALSE;\t\n\t}\n\n\treturn _TRUE;\n}\n\nvoid rtw_ft_update_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork)\n{\n\tstruct sta_priv\t\t*pstapriv = &padapter->stapriv;\n\tstruct sta_info\t\t*psta = NULL;\n\n\tpsta = rtw_get_stainfo(pstapriv, pnetwork->MacAddress);\n\tif (psta == NULL)\n\t\tpsta = rtw_alloc_stainfo(pstapriv, pnetwork->MacAddress);\n\n\tif (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) {\n\n\t\tpadapter->securitypriv.binstallGrpkey = _FALSE;\n\t\tpadapter->securitypriv.busetkipkey = _FALSE;\n\t\tpadapter->securitypriv.bgrpkey_handshake = _FALSE;\n\n\t\tpsta->ieee8021x_blocked = _TRUE;\n\t\tpsta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;\n\n\t\t_rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof(union Keytype));\n\t\t_rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof(union Keytype));\n\t\t_rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof(union Keytype));\n\t}\n\n}\n\nvoid rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf)\n{\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct stassoc_event *pstassoc = (struct stassoc_event *)pbuf;\n\tstruct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);\n\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&(pmlmeinfo->network);\n\tstruct cfg80211_ft_event_params ft_evt_parms;\n\t_irqL irqL;\n\n\t_rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms));\n\trtw_ft_update_stainfo(padapter, pnetwork);\n\tft_evt_parms.ies_len = pft_roam->ft_event.ies_len;\n\tft_evt_parms.ies =  rtw_zmalloc(ft_evt_parms.ies_len);\n\tif (ft_evt_parms.ies)\n\t\t_rtw_memcpy((void *)ft_evt_parms.ies, pft_roam->ft_event.ies, ft_evt_parms.ies_len);\n\t else\n\t\tgoto err_2;\n\n\tft_evt_parms.target_ap = rtw_zmalloc(ETH_ALEN);\n\tif (ft_evt_parms.target_ap)\n\t\t_rtw_memcpy((void *)ft_evt_parms.target_ap, pstassoc->macaddr, ETH_ALEN);\n\telse\n\t\tgoto err_1;\n\n\tft_evt_parms.ric_ies = pft_roam->ft_event.ric_ies;\n\tft_evt_parms.ric_ies_len = pft_roam->ft_event.ric_ies_len;\n\n\trtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA, &irqL);\n\trtw_cfg80211_ft_event(padapter, &ft_evt_parms);\n\tRTW_INFO(\"%s: to \"MAC_FMT\"\\n\", __func__, MAC_ARG(ft_evt_parms.target_ap));\n\n\trtw_mfree((u8 *)pft_roam->ft_event.target_ap, ETH_ALEN);\nerr_1:\n\trtw_mfree((u8 *)ft_evt_parms.ies, ft_evt_parms.ies_len);\nerr_2:\n\treturn;\n}\n#endif\n\n#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)\nvoid rtw_roam_nb_info_init(_adapter *padapter)\n{\n\tstruct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);\n\t\n\t_rtw_memset(&pnb->nb_rpt, 0, sizeof(pnb->nb_rpt));\n\t_rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list));\n\t_rtw_memset(&pnb->roam_target_addr, 0, ETH_ALEN);\n\tpnb->nb_rpt_valid = _FALSE;\n\tpnb->nb_rpt_ch_list_num = 0;\n\tpnb->preference_en = _FALSE;\n\tpnb->nb_rpt_is_same = _TRUE;\n\tpnb->last_nb_rpt_entries = 0;\n#ifdef CONFIG_RTW_WNM\n\trtw_init_timer(&pnb->roam_scan_timer, \n\t\tpadapter, rtw_wnm_roam_scan_hdl, \n\t\tpadapter);\n#endif\n}\n\nu8 rtw_roam_nb_scan_list_set(\n\t_adapter *padapter, struct sitesurvey_parm *pparm)\n{\n\tu8 ret = _FALSE;\n\tu32 i;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct roam_nb_info *pnb = &(pmlmepriv->nb_info);\n\n\tif (!rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE))\n\t\treturn ret;\n\n\tif (!pmlmepriv->need_to_roam)\n\t\treturn ret;\n\n\tif ((!pmlmepriv->nb_info.nb_rpt_valid) || (!pnb->nb_rpt_ch_list_num))\n\t\treturn ret;\n\n\tif (!pparm)\n\t\treturn ret;\n\n\trtw_init_sitesurvey_parm(padapter, pparm);\n\tif (rtw_roam_busy_scan(padapter, pnb)) {\n\t\tpparm->ch_num = 1;\n\t\tpparm->ch[pmlmepriv->ch_cnt].hw_value = \n\t\t\tpnb->nb_rpt_ch_list[pmlmepriv->ch_cnt].hw_value;\n\t\tpmlmepriv->ch_cnt++;\n\t\tret = _TRUE;\n\t\tif (pmlmepriv->ch_cnt == pnb->nb_rpt_ch_list_num) {\n\t\t\tpmlmepriv->nb_info.nb_rpt_valid = _FALSE;\n\t\t\tpmlmepriv->ch_cnt = 0;\n\t\t}\n\t\tgoto set_bssid_list;\n\t}\n\n\tpparm->ch_num = (pnb->nb_rpt_ch_list_num > RTW_CHANNEL_SCAN_AMOUNT)?\n\t\t(RTW_CHANNEL_SCAN_AMOUNT):(pnb->nb_rpt_ch_list_num);\n\tfor (i=0; i<pparm->ch_num; i++) {\n\t\tpparm->ch[i].hw_value = pnb->nb_rpt_ch_list[i].hw_value;\n\t\tpparm->ch[i].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN;\n\t}\n\n\tpmlmepriv->nb_info.nb_rpt_valid = _FALSE;\n\tpmlmepriv->ch_cnt = 0;\t\t\n\tret = _TRUE;\n\nset_bssid_list:\n\trtw_set_802_11_bssid_list_scan(padapter, pparm);\n\treturn ret;\n}\n#endif\n\nvoid rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id)\n{\n\tstruct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;\n\n\tif (mac_id >= 0 && mac_id < macid_ctl->num) {\n\t\tu8 id_is_shared = mac_id == RTW_DEFAULT_MGMT_MACID; /* TODO: real shared macid judgment */\n\n\t\tRTW_INFO(FUNC_ADPT_FMT\" - mac_id=%d%s\\n\", FUNC_ADPT_ARG(adapter)\n\t\t\t, mac_id, id_is_shared ? \" shared\" : \"\");\n\n\t\tif (!id_is_shared) {\n\t\t\trtw_hal_set_FwMediaStatusRpt_single_cmd(adapter, 0, 0, 0, 0, mac_id);\n\t\t\t/*\n\t\t\t * For safety, prevent from keeping macid sleep.\n\t\t\t * If we can sure all power mode enter/leave are paired,\n\t\t\t * this check can be removed.\n\t\t\t * Lucas@20131113\n\t\t\t */\n\t\t\t/* wakeup macid after disconnect. */\n\t\t\t/*if (MLME_IS_STA(adapter))*/\n\t\t\trtw_hal_macid_wakeup(adapter, mac_id);\n\t\t}\n\t} else {\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" invalid macid:%u\\n\"\n\t\t\t  , FUNC_ADPT_ARG(adapter), mac_id);\n\t\trtw_warn_on(1);\n\t}\n}\nvoid rtw_sta_mstatus_report(_adapter *adapter)\n{\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tstruct wlan_network *tgt_network = &pmlmepriv->cur_network;\n\tstruct sta_info *psta = NULL;\n\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {\n\t\tpsta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress);\n\t\tif (psta)\n\t\t\trtw_sta_mstatus_disc_rpt(adapter, psta->cmn.mac_id);\n\t\telse {\n\t\t\tRTW_INFO(\"%s \"ADPT_FMT\" - mac_addr: \"MAC_FMT\" psta == NULL\\n\", __func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress));\n\t\t\trtw_warn_on(1);\n\t\t}\n\t}\n}\n\nvoid rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf)\n{\n\t_irqL irqL, irqL2;\n\n\tstruct sta_info *psta;\n\tstruct wlan_network *pwlan = NULL;\n\tWLAN_BSSID_EX    *pdev_network = NULL;\n\tu8 *pibss = NULL;\n\tstruct\tmlme_priv\t*pmlmepriv = &(adapter->mlmepriv);\n\tstruct\tstadel_event *pstadel\t= (struct stadel_event *)pbuf;\n\tstruct wlan_network *tgt_network = &(pmlmepriv->cur_network);\n\n\tRTW_INFO(\"%s(mac_id=%d)=\" MAC_FMT \"\\n\", __func__, pstadel->mac_id, MAC_ARG(pstadel->macaddr));\n\trtw_sta_mstatus_disc_rpt(adapter, pstadel->mac_id);\n\n#ifdef CONFIG_MCC_MODE\n\trtw_hal_mcc_update_macid_bitmap(adapter, pstadel->mac_id, _FALSE);\n#endif /* CONFIG_MCC_MODE */\n\n\tpsta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr);\n\n\tif (psta == NULL) {\n\t\tRTW_INFO(\"%s(mac_id=%d)=\" MAC_FMT \" psta == NULL\\n\", __func__, pstadel->mac_id, MAC_ARG(pstadel->macaddr));\n\t\t/*rtw_warn_on(1);*/\n\t}\n\n\tif (psta)\n\t\trtw_wfd_st_switch(psta, 0);\n\n\tif (MLME_IS_MESH(adapter)) {\n\t\trtw_free_stainfo(adapter, psta);\n\t\tgoto exit;\n\t}\n\n\tif (MLME_IS_AP(adapter)) {\n#ifdef CONFIG_IOCTL_CFG80211\n#ifdef COMPAT_KERNEL_RELEASE\n\n#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)\n\t\trtw_cfg80211_indicate_sta_disassoc(adapter, pstadel->macaddr, *(u16 *)pstadel->rsvd);\n#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n\t\trtw_free_stainfo(adapter, psta);\n\n\t\tgoto exit;\n\t}\n\n\tmlmeext_sta_del_event_callback(adapter);\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL2);\n\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {\n\t\tu16 reason = *((unsigned short *)(pstadel->rsvd));\n\t\tbool roam = _FALSE;\n\t\tstruct wlan_network *roam_target = NULL;\n\n#ifdef CONFIG_LAYER2_ROAMING\n#ifdef CONFIG_RTW_80211R\n\t\tif (rtw_ft_roam_expired(adapter, reason))\n\t\t\tpmlmepriv->ft_roam.ft_roam_on_expired = _TRUE;\n\t\telse\n\t\t\tpmlmepriv->ft_roam.ft_roam_on_expired = _FALSE;\n#endif\n\t\tif (adapter->registrypriv.wifi_spec == 1)\n\t\t\troam = _FALSE;\n\t\telse if (reason == WLAN_REASON_EXPIRATION_CHK && rtw_chk_roam_flags(adapter, RTW_ROAM_ON_EXPIRED))\n\t\t\troam = _TRUE;\n\t\telse if (reason == WLAN_REASON_ACTIVE_ROAM && rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) {\n\t\t\troam = _TRUE;\n\t\t\troam_target = pmlmepriv->roam_network;\n\t\t}\n\t\tif (roam == _TRUE) {\n\t\t\tif (rtw_to_roam(adapter) > 0)\n\t\t\t\trtw_dec_to_roam(adapter); /* this stadel_event is caused by roaming, decrease to_roam */\n\t\t\telse if (rtw_to_roam(adapter) == 0)\n\t\t\t\trtw_set_to_roam(adapter, adapter->registrypriv.max_roaming_times);\n\t\t} else\n\t\t\trtw_set_to_roam(adapter, 0);\n#endif /* CONFIG_LAYER2_ROAMING */\n\n\t\trtw_free_uc_swdec_pending_queue(adapter);\n\n\t\trtw_free_assoc_resources(adapter, _TRUE);\n\t\trtw_free_mlme_priv_ie_data(pmlmepriv);\n\n\t\trtw_indicate_disconnect(adapter, *(u16 *)pstadel->rsvd, pstadel->locally_generated);\n\n\t\t_rtw_roaming(adapter, roam_target);\n\t}\n\n\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) ||\n\t    check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) {\n\n\t\t/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */\n\t\trtw_free_stainfo(adapter,  psta);\n\t\t/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */\n\n\t\tif (adapter->stapriv.asoc_sta_count == 1) { /* a sta + bc/mc_stainfo (not Ibss_stainfo) */\n\t\t\t/* rtw_indicate_disconnect(adapter); */ /* removed@20091105 */\n\t\t\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\t\t\t/* free old ibss network */\n\t\t\t/* pwlan = _rtw_find_network(&pmlmepriv->scanned_queue, pstadel->macaddr); */\n\t\t\tpwlan = _rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress);\n\t\t\tif (pwlan) {\n\t\t\t\tpwlan->fixed = _FALSE;\n\t\t\t\trtw_free_network_nolock(adapter, pwlan);\n\t\t\t}\n\t\t\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\t\t\t/* re-create ibss */\n\t\t\tpdev_network = &(adapter->registrypriv.dev_network);\n\t\t\tpibss = adapter->registrypriv.dev_network.MacAddress;\n\n\t\t\t_rtw_memcpy(pdev_network, &tgt_network->network, get_WLAN_BSSID_EX_sz(&tgt_network->network));\n\n\t\t\t_rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID));\n\t\t\t_rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));\n\n\t\t\trtw_update_registrypriv_dev_network(adapter);\n\n\t\t\trtw_generate_random_ibss(pibss);\n\n\t\t\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) {\n\t\t\t\tset_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);\n\t\t\t\t_clr_fwstate_(pmlmepriv, WIFI_ADHOC_STATE);\n\t\t\t}\n\n\t\t\tif (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS)\n\t\t\t\tRTW_ERR(\"rtw_create_ibss_cmd FAIL\\n\");\n\n\t\t}\n\n\t}\n\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL2);\nexit:\n\t#ifdef CONFIG_RTS_FULL_BW\n\trtw_set_rts_bw(adapter);\n\t#endif/*CONFIG_RTS_FULL_BW*/\n\treturn;\n}\n\n\nvoid rtw_cpwm_event_callback(PADAPTER padapter, u8 *pbuf)\n{\n#ifdef CONFIG_LPS_LCLK\n\tstruct reportpwrstate_parm *preportpwrstate;\n#endif\n\n\n#ifdef CONFIG_LPS_LCLK\n\tpreportpwrstate = (struct reportpwrstate_parm *)pbuf;\n\tpreportpwrstate->state |= (u8)(adapter_to_pwrctl(padapter)->cpwm_tog + 0x80);\n\tcpwm_int_hdl(padapter, preportpwrstate);\n#endif\n\n\n}\n\n\nvoid rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf)\n{\n\n\tWMMOnAssocRsp(padapter);\n\n\n}\n\n/*\n* rtw_join_timeout_handler - Timeout/failure handler for CMD JoinBss\n*/\nvoid rtw_join_timeout_handler(void *ctx)\n{\n\t_adapter *adapter = (_adapter *)ctx;\n\t_irqL irqL;\n\tstruct\tmlme_priv *pmlmepriv = &adapter->mlmepriv;\n\n#if 0\n\tif (rtw_is_drv_stopped(adapter)) {\n\t\t_rtw_up_sema(&pmlmepriv->assoc_terminate);\n\t\treturn;\n\t}\n#endif\n\n\n\n\tRTW_INFO(\"%s, fw_state=%x\\n\", __FUNCTION__, get_fwstate(pmlmepriv));\n\n\tif (RTW_CANNOT_RUN(adapter))\n\t\treturn;\n\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\n#ifdef CONFIG_LAYER2_ROAMING\n\tif (rtw_to_roam(adapter) > 0) { /* join timeout caused by roaming */\n\t\twhile (1) {\n\t\t\trtw_dec_to_roam(adapter);\n\t\t\tif (rtw_to_roam(adapter) != 0) { /* try another */\n\t\t\t\tint do_join_r;\n\t\t\t\tRTW_INFO(\"%s try another roaming\\n\", __FUNCTION__);\n\t\t\t\tdo_join_r = rtw_do_join(adapter);\n\t\t\t\tif (_SUCCESS != do_join_r) {\n\t\t\t\t\tRTW_INFO(\"%s roaming do_join return %d\\n\", __FUNCTION__ , do_join_r);\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t} else {\n\t\t\t\tRTW_INFO(\"%s We've try roaming but fail\\n\", __FUNCTION__);\n#ifdef CONFIG_RTW_80211R\n\t\t\t\trtw_ft_clr_flags(adapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN);\n\t\t\t\trtw_ft_reset_status(adapter);\n#endif\n\t\t\t\trtw_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t} else\n#endif\n\t{\n\t\trtw_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE);\n\t\tfree_scanqueue(pmlmepriv);/* ??? */\n\n#ifdef CONFIG_IOCTL_CFG80211\n\t\t/* indicate disconnect for the case that join_timeout and check_fwstate != FW_LINKED */\n\t\trtw_cfg80211_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE);\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n\t}\n\n\tpmlmepriv->join_status = 0; /* reset */\n\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\n\n#ifdef CONFIG_DRVEXT_MODULE_WSC\n\tdrvext_assoc_fail_indicate(&adapter->drvextpriv);\n#endif\n\n\n\n}\n\n/*\n* rtw_scan_timeout_handler - Timeout/Faliure handler for CMD SiteSurvey\n* @adapter: pointer to _adapter structure\n*/\nvoid rtw_scan_timeout_handler(void *ctx)\n{\n\t_adapter *adapter = (_adapter *)ctx;\n\t_irqL irqL;\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tRTW_INFO(FUNC_ADPT_FMT\" fw_state=%x\\n\", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv));\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\n\t_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);\n\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\n#ifdef CONFIG_IOCTL_CFG80211\n\trtw_cfg80211_surveydone_event_callback(adapter);\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n\trtw_indicate_scan_done(adapter, _TRUE);\n\n#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_IOCTL_CFG80211)\n\trtw_cfg80211_indicate_scan_done_for_buddy(adapter, _TRUE);\n#endif\n}\n\nvoid rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason)\n{\n#if defined(CONFIG_RTW_MESH) && defined(CONFIG_DFS_MASTER)\n#if CONFIG_RTW_MESH_OFFCH_CAND \n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n#endif\n#endif\n\tu8 u_ch;\n\tu32 interval_ms = 0xffffffff; /* 0xffffffff: special value to make min() works well, also means no auto scan */\n\n\t*reason = RTW_AUTO_SCAN_REASON_UNSPECIFIED;\n\trtw_mi_get_ch_setting_union(adapter, &u_ch, NULL, NULL);\n\n\tif (hal_chk_bw_cap(adapter, BW_CAP_40M)\n\t\t&& is_client_associated_to_ap(adapter) == _TRUE\n\t\t&& u_ch >= 1 && u_ch <= 14\n\t\t&& adapter->registrypriv.wifi_spec\n\t\t/* TODO: AP Connected is 40MHz capability? */\n\t) {\n\t\tinterval_ms = rtw_min(interval_ms, 60 * 1000);\n\t\t*reason |= RTW_AUTO_SCAN_REASON_2040_BSS;\n\t}\n\n#ifdef CONFIG_RTW_MESH\n\t#if CONFIG_RTW_MESH_OFFCH_CAND\n\tif (adapter->mesh_cfg.peer_sel_policy.offch_find_int_ms\n\t\t&& rtw_mesh_offch_candidate_accepted(adapter)\n\t\t#ifdef CONFIG_DFS_MASTER\n\t\t&& (!rfctl->radar_detect_ch || (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl)))\n\t\t#endif\n\t) {\n\t\tinterval_ms = rtw_min(interval_ms, adapter->mesh_cfg.peer_sel_policy.offch_find_int_ms);\n\t\t*reason |= RTW_AUTO_SCAN_REASON_MESH_OFFCH_CAND;\n\t}\n\t#endif\n#endif /* CONFIG_RTW_MESH */\n\n\tif (interval_ms == 0xffffffff)\n\t\tinterval_ms = 0;\n\n\trtw_mlme_set_auto_scan_int(adapter, interval_ms);\n\treturn;\n}\n\nvoid rtw_drv_scan_by_self(_adapter *padapter, u8 reason)\n{\n\tstruct sitesurvey_parm parm;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tint i;\n#if 1\n\tu8 ssc_chk;\n\n\tssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);\n\tif( ssc_chk == SS_DENY_BUSY_TRAFFIC) {\n\t\t#ifdef CONFIG_LAYER2_ROAMING\n\t\tif (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE) && pmlmepriv->need_to_roam == _TRUE)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" need to roam, don't care BusyTraffic\\n\", FUNC_ADPT_ARG(padapter));\n\t\telse\n\t\t#endif\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" exit BusyTraffic\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\tgoto exit;\n\t}\n\telse if (ssc_chk != SS_ALLOW)\n\t\tgoto exit;\n\n\tif (!rtw_is_adapter_up(padapter))\n\t\tgoto exit;\n#else\n\tif (rtw_is_scan_deny(padapter))\n\t\tgoto exit;\n\n\tif (!rtw_is_adapter_up(padapter))\n\t\tgoto exit;\n\n\tif (rtw_mi_busy_traffic_check(padapter, _FALSE)) {\n#ifdef CONFIG_LAYER2_ROAMING\n\t\tif (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE) && pmlmepriv->need_to_roam == _TRUE) {\n\t\t\tRTW_INFO(\"need to roam, don't care BusyTraffic\\n\");\n\t\t} else\n#endif\n\t\t{\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" exit BusyTraffic\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\tgoto exit;\n\t\t}\n\t}\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" WIFI_AP_STATE && WIFI_UNDER_WPS\\n\", FUNC_ADPT_ARG(padapter));\n\t\tgoto exit;\n\t}\n\tif (check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY | _FW_UNDER_LINKING)) == _TRUE) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" _FW_UNDER_SURVEY|_FW_UNDER_LINKING\\n\", FUNC_ADPT_ARG(padapter));\n\t\tgoto exit;\n\t}\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_buddy_check_fwstate(padapter, (_FW_UNDER_SURVEY | _FW_UNDER_LINKING | WIFI_UNDER_WPS))) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\", but buddy_intf is under scanning or linking or wps_phase\\n\", FUNC_ADPT_ARG(padapter));\n\t\tgoto exit;\n\t}\n#endif\n#endif\n\n\tRTW_INFO(FUNC_ADPT_FMT\" reason:0x%02x\\n\", FUNC_ADPT_ARG(padapter), reason);\n\n\t/* only for 20/40 BSS */\n\tif (reason == RTW_AUTO_SCAN_REASON_2040_BSS) {\n\t\trtw_init_sitesurvey_parm(padapter, &parm);\n\t\tfor (i=0;i<14;i++) {\n\t\t\tparm.ch[i].hw_value = i + 1;\n\t\t\tparm.ch[i].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN;\n\t\t}\n\t\tparm.ch_num = 14;\n\t\trtw_set_802_11_bssid_list_scan(padapter, &parm);\n\t\tgoto exit;\n\t}\n\n#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)\n\tif ((reason == RTW_AUTO_SCAN_REASON_ROAM) \n\t\t&& (rtw_roam_nb_scan_list_set(padapter, &parm)))\n\t\tgoto exit;\n#endif\n\n\trtw_set_802_11_bssid_list_scan(padapter, NULL);\nexit:\n\treturn;\n}\n\nstatic void rtw_auto_scan_handler(_adapter *padapter)\n{\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tu8 reason = RTW_AUTO_SCAN_REASON_UNSPECIFIED;\n\n\trtw_mlme_reset_auto_scan_int(padapter, &reason);\n\n#ifdef CONFIG_P2P\n\tif (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE))\n\t\tgoto exit;\n#endif\n\n#ifdef CONFIG_TDLS\n\tif (padapter->tdlsinfo.link_established == _TRUE)\n\t\tgoto exit;\n#endif\n\n\tif (pmlmepriv->auto_scan_int_ms == 0\n\t    || rtw_get_passing_time_ms(pmlmepriv->scan_start_time) < pmlmepriv->auto_scan_int_ms)\n\t\tgoto exit;\n\n\trtw_drv_scan_by_self(padapter, reason);\n\nexit:\n\treturn;\n}\nstatic u8 is_drv_in_lps(_adapter *adapter)\n{\n\tu8 is_in_lps = _FALSE;\n\n\t#ifdef CONFIG_LPS_LCLK_WD_TIMER /* to avoid leaving lps 32k frequently*/\n\tif ((adapter_to_pwrctl(adapter)->bFwCurrentInPSMode == _TRUE)\n\t#ifdef CONFIG_BT_COEXIST\n\t\t&& (rtw_btcoex_IsBtControlLps(adapter) == _FALSE)\n\t#endif\n\t\t)\n\t\tis_in_lps = _TRUE;\n\t#endif /* CONFIG_LPS_LCLK_WD_TIMER*/\n\treturn is_in_lps;\n}\nvoid rtw_iface_dynamic_check_timer_handlder(_adapter *adapter)\n{\n#ifdef CONFIG_AP_MODE\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n#endif /* CONFIG_AP_MODE */\n\n\tif (adapter->net_closed == _TRUE)\n\t\treturn;\n\t#ifdef CONFIG_LPS_LCLK_WD_TIMER /* to avoid leaving lps 32k frequently*/\n\tif (is_drv_in_lps(adapter)) {\n\t\tu8 bEnterPS;\n\n\t\tlinked_status_chk(adapter, 1);\n\n\t\tbEnterPS = traffic_status_watchdog(adapter, 1);\n\t\tif (bEnterPS) {\n\t\t\t/* rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_ENTER, 0); */\n\t\t\trtw_hal_dm_watchdog_in_lps(adapter);\n\t\t} else {\n\t\t\t/* call rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0) in traffic_status_watchdog() */\n\t\t}\n\t}\n\t#endif /* CONFIG_LPS_LCLK_WD_TIMER\t*/\n\n\t/* auto site survey */\n\trtw_auto_scan_handler(adapter);\n\n#ifdef CONFIG_AP_MODE\n\tif (MLME_IS_AP(adapter)|| MLME_IS_MESH(adapter)) {\n\t\t#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK\n\t\texpire_timeout_chk(adapter);\n\t\t#endif /* !CONFIG_ACTIVE_KEEP_ALIVE_CHECK */\n\n\t\t#ifdef CONFIG_BMC_TX_RATE_SELECT\n\t\trtw_update_bmc_sta_tx_rate(adapter);\n\t\t#endif /*CONFIG_BMC_TX_RATE_SELECT*/\n\t}\n#endif /*CONFIG_AP_MODE*/\n\n\n#ifdef CONFIG_BR_EXT\n\n#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))\n\trcu_read_lock();\n#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) */\n\n#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))\n\tif (adapter->pnetdev->br_port\n#else\t/* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */\n\tif (rcu_dereference(adapter->pnetdev->rx_handler_data)\n#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */\n\t\t&& (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE)) {\n\t\t/* expire NAT2.5 entry */\n\t\tvoid nat25_db_expire(_adapter *priv);\n\t\tnat25_db_expire(adapter);\n\n\t\tif (adapter->pppoe_connection_in_progress > 0)\n\t\t\tadapter->pppoe_connection_in_progress--;\n\t\t/* due to rtw_dynamic_check_timer_handlder() is called every 2 seconds */\n\t\tif (adapter->pppoe_connection_in_progress > 0)\n\t\t\tadapter->pppoe_connection_in_progress--;\n\t}\n\n#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))\n\trcu_read_unlock();\n#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) */\n\n#endif /* CONFIG_BR_EXT */\n\n}\n\n/*TP_avg(t) = (1/10) * TP_avg(t-1) + (9/10) * TP(t) MBps*/\nstatic void collect_sta_traffic_statistics(_adapter *adapter)\n{\n\tstruct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;\n\tstruct sta_info *sta;\n\tu64 curr_tx_bytes = 0, curr_rx_bytes = 0;\n\tu32 curr_tx_mbytes = 0, curr_rx_mbytes = 0;\n\tint i;\n\n\tfor (i = 0; i < MACID_NUM_SW_LIMIT; i++) {\n\t\tsta = macid_ctl->sta[i];\n\t\tif (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr)) {\n\t\t\tif (sta->sta_stats.last_tx_bytes > sta->sta_stats.tx_bytes)\n\t\t\t\tsta->sta_stats.last_tx_bytes =  sta->sta_stats.tx_bytes;\n\t\t\tif (sta->sta_stats.last_rx_bytes > sta->sta_stats.rx_bytes)\n\t\t\t\tsta->sta_stats.last_rx_bytes = sta->sta_stats.rx_bytes;\n\t\t\tif (sta->sta_stats.last_rx_bc_bytes > sta->sta_stats.rx_bc_bytes)\n\t\t\t\tsta->sta_stats.last_rx_bc_bytes = sta->sta_stats.rx_bc_bytes;\n\t\t\tif (sta->sta_stats.last_rx_mc_bytes > sta->sta_stats.rx_mc_bytes)\n\t\t\t\tsta->sta_stats.last_rx_mc_bytes = sta->sta_stats.rx_mc_bytes;\n\n\t\t\tcurr_tx_bytes = sta->sta_stats.tx_bytes - sta->sta_stats.last_tx_bytes;\n\t\t\tcurr_rx_bytes = sta->sta_stats.rx_bytes - sta->sta_stats.last_rx_bytes;\n\t\t\tsta->sta_stats.tx_tp_kbits = (curr_tx_bytes * 8 / 2) >> 10;/*Kbps*/\n\t\t\tsta->sta_stats.rx_tp_kbits = (curr_rx_bytes * 8 / 2) >> 10;/*Kbps*/\n\n\t\t\tsta->sta_stats.smooth_tx_tp_kbits = (sta->sta_stats.smooth_tx_tp_kbits * 6 / 10) + (sta->sta_stats.tx_tp_kbits * 4 / 10);/*Kbps*/\n\t\t\tsta->sta_stats.smooth_rx_tp_kbits = (sta->sta_stats.smooth_rx_tp_kbits * 6 / 10) + (sta->sta_stats.rx_tp_kbits * 4 / 10);/*Kbps*/\n\n\t\t\tcurr_tx_mbytes = (curr_tx_bytes / 2) >> 20;/*MBps*/\n\t\t\tcurr_rx_mbytes = (curr_rx_bytes / 2) >> 20;/*MBps*/\n\n\t\t\tsta->cmn.tx_moving_average_tp =\n\t\t\t\t(sta->cmn.tx_moving_average_tp / 10) + (curr_tx_mbytes * 9 / 10); /*MBps*/\n\n\t\t\tsta->cmn.rx_moving_average_tp =\n\t\t\t\t(sta->cmn.rx_moving_average_tp / 10) + (curr_rx_mbytes * 9 /10); /*MBps*/\n\n\t\t\trtw_collect_bcn_info(sta->padapter);\n\n\t\t\tif (adapter->bsta_tp_dump)\n\t\t\t\tdump_sta_traffic(RTW_DBGDUMP, adapter, sta);\n\n\t\t\tsta->sta_stats.last_tx_bytes = sta->sta_stats.tx_bytes;\n\t\t\tsta->sta_stats.last_rx_bytes = sta->sta_stats.rx_bytes;\n\t\t\tsta->sta_stats.last_rx_bc_bytes = sta->sta_stats.rx_bc_bytes;\n\t\t\tsta->sta_stats.last_rx_mc_bytes = sta->sta_stats.rx_mc_bytes;\n\t\t}\n\t}\n}\n\nvoid rtw_sta_traffic_info(void *sel, _adapter *adapter)\n{\n\tstruct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;\n\tstruct sta_info *sta;\n\tint i;\n\n\tfor (i = 0; i < MACID_NUM_SW_LIMIT; i++) {\n\t\tsta = macid_ctl->sta[i];\n\t\tif (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr))\n\t\t\tdump_sta_traffic(sel, adapter, sta);\n\t}\n}\n\n/*#define DBG_TRAFFIC_STATISTIC*/\nstatic void collect_traffic_statistics(_adapter *padapter)\n{\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\n\t/*_rtw_memset(&pdvobjpriv->traffic_stat, 0, sizeof(struct rtw_traffic_statistics));*/\n\n\t/* Tx bytes reset*/\n\tpdvobjpriv->traffic_stat.tx_bytes = 0;\n\tpdvobjpriv->traffic_stat.tx_pkts = 0;\n\tpdvobjpriv->traffic_stat.tx_drop = 0;\n\n\t/* Rx bytes reset*/\n\tpdvobjpriv->traffic_stat.rx_bytes = 0;\n\tpdvobjpriv->traffic_stat.rx_pkts = 0;\n\tpdvobjpriv->traffic_stat.rx_drop = 0;\n\n\trtw_mi_traffic_statistics(padapter);\n\n\t/* Calculate throughput in last interval */\n\tpdvobjpriv->traffic_stat.cur_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes - pdvobjpriv->traffic_stat.last_tx_bytes;\n\tpdvobjpriv->traffic_stat.cur_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes - pdvobjpriv->traffic_stat.last_rx_bytes;\n\tpdvobjpriv->traffic_stat.last_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes;\n\tpdvobjpriv->traffic_stat.last_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes;\n\n\tpdvobjpriv->traffic_stat.cur_tx_tp = (u32)(pdvobjpriv->traffic_stat.cur_tx_bytes * 8 / 2 / 1024 / 1024);/*Mbps*/\n\tpdvobjpriv->traffic_stat.cur_rx_tp = (u32)(pdvobjpriv->traffic_stat.cur_rx_bytes * 8 / 2 / 1024 / 1024);/*Mbps*/\n\n\t#ifdef DBG_TRAFFIC_STATISTIC\n\tRTW_INFO(\"\\n========================\\n\");\n\tRTW_INFO(\"cur_tx_bytes:%lld\\n\", pdvobjpriv->traffic_stat.cur_tx_bytes);\n\tRTW_INFO(\"cur_rx_bytes:%lld\\n\", pdvobjpriv->traffic_stat.cur_rx_bytes);\n\n\tRTW_INFO(\"last_tx_bytes:%lld\\n\", pdvobjpriv->traffic_stat.last_tx_bytes);\n\tRTW_INFO(\"last_rx_bytes:%lld\\n\", pdvobjpriv->traffic_stat.last_rx_bytes);\n\n\tRTW_INFO(\"cur_tx_tp:%d (Mbps)\\n\", pdvobjpriv->traffic_stat.cur_tx_tp);\n\tRTW_INFO(\"cur_rx_tp:%d (Mbps)\\n\", pdvobjpriv->traffic_stat.cur_rx_tp);\n\t#endif\n\n#ifdef CONFIG_RTW_NAPI\n#ifdef CONFIG_RTW_NAPI_DYNAMIC\n\tdynamic_napi_th_chk (padapter);\n#endif /* CONFIG_RTW_NAPI_DYNAMIC */\n#endif\n\t\n}\n\nvoid rtw_dynamic_check_timer_handlder(void *ctx)\n{\n\tstruct dvobj_priv *pdvobj = (struct dvobj_priv *)ctx;\n\t_adapter *adapter = dvobj_get_primary_adapter(pdvobj);\n\n#if (MP_DRIVER == 1)\n\tif (adapter->registrypriv.mp_mode == 1 && adapter->mppriv.mp_dm == 0) { /* for MP ODM dynamic Tx power tracking */\n\t\t/* RTW_INFO(\"%s mp_dm =0 return\\n\", __func__); */\n\t\tgoto exit;\n\t}\n#endif\n\n\tif (!adapter)\n\t\tgoto exit;\n\n\tif (!rtw_is_hw_init_completed(adapter))\n\t\tgoto exit;\n\n\tif (RTW_CANNOT_RUN(adapter))\n\t\tgoto exit;\n\n\tcollect_traffic_statistics(adapter);\n\tcollect_sta_traffic_statistics(adapter);\n\trtw_mi_dynamic_check_timer_handlder(adapter);\n\n\tif (!is_drv_in_lps(adapter))\n\t\trtw_dynamic_chk_wk_cmd(adapter);\n\nexit:\n\t_set_timer(&pdvobj->dynamic_chk_timer, 2000);\n}\n\n\n#ifdef CONFIG_SET_SCAN_DENY_TIMER\ninline bool rtw_is_scan_deny(_adapter *adapter)\n{\n\tstruct mlme_priv *mlmepriv = &adapter->mlmepriv;\n\treturn (ATOMIC_READ(&mlmepriv->set_scan_deny) != 0) ? _TRUE : _FALSE;\n}\n\ninline void rtw_clear_scan_deny(_adapter *adapter)\n{\n\tstruct mlme_priv *mlmepriv = &adapter->mlmepriv;\n\tATOMIC_SET(&mlmepriv->set_scan_deny, 0);\n\tif (0)\n\t\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(adapter));\n}\n\nvoid rtw_set_scan_deny_timer_hdl(void *ctx)\n{\n\t_adapter *adapter = (_adapter *)ctx;\n\n\trtw_clear_scan_deny(adapter);\n}\nvoid rtw_set_scan_deny(_adapter *adapter, u32 ms)\n{\n\tstruct mlme_priv *mlmepriv = &adapter->mlmepriv;\n\tif (0)\n\t\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(adapter));\n\tATOMIC_SET(&mlmepriv->set_scan_deny, 1);\n\t_set_timer(&mlmepriv->set_scan_deny_timer, ms);\n}\n#endif\n\n#ifdef CONFIG_LAYER2_ROAMING\n/*\n* Select a new roaming candidate from the original @param candidate and @param competitor\n* @return _TRUE: candidate is updated\n* @return _FALSE: candidate is not updated\n*/\nstatic int rtw_check_roaming_candidate(struct mlme_priv *mlme\n\t, struct wlan_network **candidate, struct wlan_network *competitor)\n{\n\tint updated = _FALSE;\n\t_adapter *adapter = container_of(mlme, _adapter, mlmepriv);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tRT_CHANNEL_INFO *chset = rfctl->channel_set;\n\tu8 ch = competitor->network.Configuration.DSConfig;\n\n\tif (rtw_chset_search_ch(chset, ch) < 0)\n\t\tgoto exit;\n\tif (IS_DFS_SLAVE_WITH_RD(rfctl)\n\t\t&& !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))\n\t\t&& rtw_chset_is_ch_non_ocp(chset, ch))\n\t\tgoto exit;\n\n#if defined(CONFIG_RTW_REPEATER_SON) &&  (!defined(CONFIG_RTW_REPEATER_SON_ROOT))\n\tif (rtw_rson_isupdate_roamcan(mlme, candidate, competitor))\n\t\tgoto  update;\n\tgoto exit;\n#endif\n\n\tif (is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE)\n\t\tgoto exit;\n\n\tif (rtw_is_desired_network(adapter, competitor) == _FALSE)\n\t\tgoto exit;\n\n#ifdef CONFIG_LAYER2_ROAMING\n\tif (mlme->need_to_roam == _FALSE)\n\t\tgoto exit;\n#endif\n\n#ifdef CONFIG_RTW_80211R\n\tif (rtw_ft_chk_flags(adapter, RTW_FT_PEER_EN)) {\n\t\tif (rtw_ft_chk_roaming_candidate(adapter, competitor) == _FALSE)\n\t\tgoto exit;\n\t}\n#endif\n\n\tRTW_INFO(\"roam candidate:%s %s(\"MAC_FMT\", ch%3u) rssi:%d, age:%5d\\n\",\n\t\t (competitor == mlme->cur_network_scanned) ? \"*\" : \" \" ,\n\t\t competitor->network.Ssid.Ssid,\n\t\t MAC_ARG(competitor->network.MacAddress),\n\t\t competitor->network.Configuration.DSConfig,\n\t\t (int)competitor->network.Rssi,\n\t\t rtw_get_passing_time_ms(competitor->last_scanned)\n\t\t);\n\n\t/* got specific addr to roam */\n\tif (!is_zero_mac_addr(mlme->roam_tgt_addr)) {\n\t\tif (_rtw_memcmp(mlme->roam_tgt_addr, competitor->network.MacAddress, ETH_ALEN) == _TRUE)\n\t\t\tgoto update;\n\t\telse\n\t\t\tgoto exit;\n\t}\n#if 1\n\tif (rtw_get_passing_time_ms(competitor->last_scanned) >= mlme->roam_scanr_exp_ms)\n\t\tgoto exit;\n\n#if defined(CONFIG_RTW_80211R) && defined(CONFIG_RTW_WNM)\n\tif (rtw_wnm_btm_diff_bss(adapter) && \n\t\trtw_wnm_btm_roam_candidate(adapter, competitor)) {\n\t\tgoto update;\n\t}\t\n#endif\n\n\tif (competitor->network.Rssi - mlme->cur_network_scanned->network.Rssi < mlme->roam_rssi_diff_th)\n\t\tgoto exit;\n\n\tif (*candidate != NULL && (*candidate)->network.Rssi >= competitor->network.Rssi)\n\t\tgoto exit;\n#else\n\tgoto exit;\n#endif\n\nupdate:\n\t*candidate = competitor;\n\tupdated = _TRUE;\n\nexit:\n\treturn updated;\n}\n\nint rtw_select_roaming_candidate(struct mlme_priv *mlme)\n{\n\t_irqL\tirqL;\n\tint ret = _FAIL;\n\t_list\t*phead;\n\t_adapter *adapter;\n\t_queue\t*queue\t= &(mlme->scanned_queue);\n\tstruct\twlan_network\t*pnetwork = NULL;\n\tstruct\twlan_network\t*candidate = NULL;\n\n\tif (mlme->cur_network_scanned == NULL) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\t_enter_critical_bh(&(mlme->scanned_queue.lock), &irqL);\n\tphead = get_list_head(queue);\n\tadapter = (_adapter *)mlme->nic_hdl;\n\n\tmlme->pscanned = get_next(phead);\n\n\twhile (!rtw_end_of_queue_search(phead, mlme->pscanned)) {\n\n\t\tpnetwork = LIST_CONTAINOR(mlme->pscanned, struct wlan_network, list);\n\t\tif (pnetwork == NULL) {\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tmlme->pscanned = get_next(mlme->pscanned);\n\n\t\tif (0)\n\t\t\tRTW_INFO(\"%s(\"MAC_FMT\", ch%u) rssi:%d\\n\"\n\t\t\t\t , pnetwork->network.Ssid.Ssid\n\t\t\t\t , MAC_ARG(pnetwork->network.MacAddress)\n\t\t\t\t , pnetwork->network.Configuration.DSConfig\n\t\t\t\t , (int)pnetwork->network.Rssi);\n\n\t\trtw_check_roaming_candidate(mlme, &candidate, pnetwork);\n\n\t}\n\n\tif (candidate == NULL) {\n\t/*\tif parent note lost the path to root and there is no other cadidate, report disconnection\t*/\n#if defined(CONFIG_RTW_REPEATER_SON) &&  (!defined(CONFIG_RTW_REPEATER_SON_ROOT))\n\t\tstruct rtw_rson_struct  rson_curr;\n\t\tu8 rson_score;\n\n\t\trtw_get_rson_struct(&(mlme->cur_network_scanned->network), &rson_curr);\n\t\trson_score = rtw_cal_rson_score(&rson_curr, mlme->cur_network_scanned->network.Rssi);\n\t\tif (check_fwstate(mlme, _FW_LINKED)\n\t\t\t&& ((rson_score == RTW_RSON_SCORE_NOTCNNT)\n\t\t\t|| (rson_score == RTW_RSON_SCORE_NOTSUP)))\n\t\t\treceive_disconnect(adapter, mlme->cur_network_scanned->network.MacAddress\n\t\t\t\t\t\t\t\t, WLAN_REASON_EXPIRATION_CHK, _FALSE);\n#endif\n\t\tRTW_INFO(\"%s: return _FAIL(candidate == NULL)\\n\", __FUNCTION__);\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t} else {\n#if defined(CONFIG_RTW_REPEATER_SON) &&  (!defined(CONFIG_RTW_REPEATER_SON_ROOT))\n\t\tstruct rtw_rson_struct  rson_curr;\n\t\tu8 rson_score;\n\n\t\trtw_get_rson_struct(&(candidate->network), &rson_curr);\n\t\trson_score = rtw_cal_rson_score(&rson_curr, candidate->network.Rssi);\n\t\tRTW_INFO(\"%s: candidate: %s(\"MAC_FMT\", ch:%u) rson_score:%d\\n\", __FUNCTION__,\n\t\t\tcandidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress),\n\t\t\t candidate->network.Configuration.DSConfig, rson_score);\n#else\n\t\tRTW_INFO(\"%s: candidate: %s(\"MAC_FMT\", ch:%u)\\n\", __FUNCTION__,\n\t\t\tcandidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress),\n\t\t\t candidate->network.Configuration.DSConfig);\n#endif\n\t\tmlme->roam_network = candidate;\n\n\t\tif (_rtw_memcmp(candidate->network.MacAddress, mlme->roam_tgt_addr, ETH_ALEN) == _TRUE)\n\t\t\t_rtw_memset(mlme->roam_tgt_addr, 0, ETH_ALEN);\n\t}\n\n\tret = _SUCCESS;\nexit:\n\t_exit_critical_bh(&(mlme->scanned_queue.lock), &irqL);\n\n\treturn ret;\n}\n#endif /* CONFIG_LAYER2_ROAMING */\n\n/*\n* Select a new join candidate from the original @param candidate and @param competitor\n* @return _TRUE: candidate is updated\n* @return _FALSE: candidate is not updated\n*/\nstatic int rtw_check_join_candidate(struct mlme_priv *mlme\n\t    , struct wlan_network **candidate, struct wlan_network *competitor)\n{\n\tint updated = _FALSE;\n\t_adapter *adapter = container_of(mlme, _adapter, mlmepriv);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tRT_CHANNEL_INFO *chset = rfctl->channel_set;\n\tu8 ch = competitor->network.Configuration.DSConfig;\n\n\tif (rtw_chset_search_ch(chset, ch) < 0)\n\t\tgoto exit;\n\tif (IS_DFS_SLAVE_WITH_RD(rfctl)\n\t\t&& !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))\n\t\t&& rtw_chset_is_ch_non_ocp(chset, ch))\n\t\tgoto exit;\n\n#if defined(CONFIG_RTW_REPEATER_SON) &&  (!defined(CONFIG_RTW_REPEATER_SON_ROOT))\n\ts16 rson_score;\n\tstruct rtw_rson_struct  rson_data;\n\n\tif (rtw_rson_choose(candidate, competitor)) {\n\t\t*candidate = competitor;\n\t\trtw_get_rson_struct(&((*candidate)->network), &rson_data);\n\t\trson_score = rtw_cal_rson_score(&rson_data, (*candidate)->network.Rssi);\n\t\tRTW_INFO(\"[assoc_ssid:%s] new candidate: %s(\"MAC_FMT\", ch%u) rson_score:%d\\n\",\n\t\t\t mlme->assoc_ssid.Ssid,\n\t\t\t (*candidate)->network.Ssid.Ssid,\n\t\t\t MAC_ARG((*candidate)->network.MacAddress),\n\t\t\t (*candidate)->network.Configuration.DSConfig,\n\t\t\t rson_score);\n\t\treturn _TRUE;\n\t}\n\treturn _FALSE;\n#endif\n\n\t/* check bssid, if needed */\n\tif (mlme->assoc_by_bssid == _TRUE) {\n\t\tif (_rtw_memcmp(competitor->network.MacAddress, mlme->assoc_bssid, ETH_ALEN) == _FALSE)\n\t\t\tgoto exit;\n\t}\n\n\t/* check ssid, if needed */\n\tif (mlme->assoc_ssid.Ssid[0] && mlme->assoc_ssid.SsidLength) {\n\t\tif (competitor->network.Ssid.SsidLength != mlme->assoc_ssid.SsidLength\n\t\t    || _rtw_memcmp(competitor->network.Ssid.Ssid, mlme->assoc_ssid.Ssid, mlme->assoc_ssid.SsidLength) == _FALSE\n\t\t   )\n\t\t\tgoto exit;\n\t}\n\n\tif (rtw_is_desired_network(adapter, competitor)  == _FALSE)\n\t\tgoto exit;\n\n#ifdef CONFIG_LAYER2_ROAMING\n\tif (rtw_to_roam(adapter) > 0) {\n\t\tif (rtw_get_passing_time_ms(competitor->last_scanned) >= mlme->roam_scanr_exp_ms\n\t\t    || is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE\n\t\t   )\n\t\t\tgoto exit;\n\t}\n#endif\n\n\tif (*candidate == NULL || (*candidate)->network.Rssi < competitor->network.Rssi) {\n\t\t*candidate = competitor;\n\t\tupdated = _TRUE;\n\t}\n\n\tif (updated) {\n\t\tRTW_INFO(\"[by_bssid:%u][assoc_ssid:%s][to_roam:%u] \"\n\t\t\t \"new candidate: %s(\"MAC_FMT\", ch%u) rssi:%d\\n\",\n\t\t\t mlme->assoc_by_bssid,\n\t\t\t mlme->assoc_ssid.Ssid,\n\t\t\t rtw_to_roam(adapter),\n\t\t\t (*candidate)->network.Ssid.Ssid,\n\t\t\t MAC_ARG((*candidate)->network.MacAddress),\n\t\t\t (*candidate)->network.Configuration.DSConfig,\n\t\t\t (int)(*candidate)->network.Rssi\n\t\t\t);\n\t}\n\nexit:\n\treturn updated;\n}\n\n/*\nCalling context:\nThe caller of the sub-routine will be in critical section...\n\nThe caller must hold the following spinlock\n\npmlmepriv->lock\n\n\n*/\n\nint rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv)\n{\n\t_irqL\tirqL;\n\tint ret;\n\t_list\t*phead;\n\t_adapter *adapter;\n\t_queue\t*queue\t= &(pmlmepriv->scanned_queue);\n\tstruct\twlan_network\t*pnetwork = NULL;\n\tstruct\twlan_network\t*candidate = NULL;\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\tu8\t\tbSupportAntDiv = _FALSE;\n#endif\n\n\tadapter = (_adapter *)pmlmepriv->nic_hdl;\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n#ifdef CONFIG_LAYER2_ROAMING\n\tif (pmlmepriv->roam_network) {\n\t\tcandidate = pmlmepriv->roam_network;\n\t\tpmlmepriv->roam_network = NULL;\n\t\tgoto candidate_exist;\n\t}\n#endif\n\n\tphead = get_list_head(queue);\n\tpmlmepriv->pscanned = get_next(phead);\n\n\twhile (!rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) {\n\n\t\tpnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);\n\t\tif (pnetwork == NULL) {\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpmlmepriv->pscanned = get_next(pmlmepriv->pscanned);\n\n\t\tif (0)\n\t\t\tRTW_INFO(\"%s(\"MAC_FMT\", ch%u) rssi:%d\\n\"\n\t\t\t\t , pnetwork->network.Ssid.Ssid\n\t\t\t\t , MAC_ARG(pnetwork->network.MacAddress)\n\t\t\t\t , pnetwork->network.Configuration.DSConfig\n\t\t\t\t , (int)pnetwork->network.Rssi);\n\n\t\trtw_check_join_candidate(pmlmepriv, &candidate, pnetwork);\n\n\t}\n\n\tif (candidate == NULL) {\n\t\tRTW_INFO(\"%s: return _FAIL(candidate == NULL)\\n\", __FUNCTION__);\n#ifdef CONFIG_WOWLAN\n\t\t_clr_fwstate_(pmlmepriv, _FW_LINKED | _FW_UNDER_LINKING);\n#endif\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t} else {\n\t\tRTW_INFO(\"%s: candidate: %s(\"MAC_FMT\", ch:%u)\\n\", __FUNCTION__,\n\t\t\tcandidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress),\n\t\t\t candidate->network.Configuration.DSConfig);\n\t\tgoto candidate_exist;\n\t}\n\ncandidate_exist:\n\n\t/* check for situation of  _FW_LINKED */\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {\n\t\tRTW_INFO(\"%s: _FW_LINKED while ask_for_joinbss!!!\\n\", __FUNCTION__);\n\n#if 0 /* for WPA/WPA2 authentication, wpa_supplicant will expect authentication from AP, it is needed to reconnect AP... */\n\t\tif (is_same_network(&pmlmepriv->cur_network.network, &candidate->network)) {\n\t\t\tRTW_INFO(\"%s: _FW_LINKED and is same network, it needn't join again\\n\", __FUNCTION__);\n\n\t\t\trtw_indicate_connect(adapter);/* rtw_indicate_connect again */\n\n\t\t\tret = 2;\n\t\t\tgoto exit;\n\t\t} else\n#endif\n\t\t{\n\t\t\trtw_disassoc_cmd(adapter, 0, 0);\n\t\t\trtw_indicate_disconnect(adapter, 0, _FALSE);\n\t\t\trtw_free_assoc_resources_cmd(adapter, _TRUE, 0);\n\t\t}\n\t}\n\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\trtw_hal_get_def_var(adapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv));\n\tif (_TRUE == bSupportAntDiv) {\n\t\tu8 CurrentAntenna;\n\t\trtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(CurrentAntenna), NULL);\n\t\tRTW_INFO(\"#### Opt_Ant_(%s) , cur_Ant(%s)\\n\",\n\t\t\t(MAIN_ANT == candidate->network.PhyInfo.Optimum_antenna) ? \"MAIN_ANT\" : \"AUX_ANT\",\n\t\t\t (MAIN_ANT == CurrentAntenna) ? \"MAIN_ANT\" : \"AUX_ANT\"\n\t\t\t);\n\t}\n#endif\n\tset_fwstate(pmlmepriv, _FW_UNDER_LINKING);\n\tret = rtw_joinbss_cmd(adapter, candidate);\n\nexit:\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\n\treturn ret;\n}\n\nsint rtw_set_auth(_adapter *adapter, struct security_priv *psecuritypriv)\n{\n\tstruct\tcmd_obj *pcmd;\n\tstruct\tsetauth_parm *psetauthparm;\n\tstruct\tcmd_priv\t*pcmdpriv = &(adapter->cmdpriv);\n\tsint\t\tres = _SUCCESS;\n\n\n\tpcmd = (struct\tcmd_obj *)rtw_zmalloc(sizeof(struct\tcmd_obj));\n\tif (pcmd == NULL) {\n\t\tres = _FAIL; /* try again */\n\t\tgoto exit;\n\t}\n\n\tpsetauthparm = (struct setauth_parm *)rtw_zmalloc(sizeof(struct setauth_parm));\n\tif (psetauthparm == NULL) {\n\t\trtw_mfree((unsigned char *)pcmd, sizeof(struct\tcmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t_rtw_memset(psetauthparm, 0, sizeof(struct setauth_parm));\n\tpsetauthparm->mode = (unsigned char)psecuritypriv->dot11AuthAlgrthm;\n\n\tpcmd->cmdcode = _SetAuth_CMD_;\n\tpcmd->parmbuf = (unsigned char *)psetauthparm;\n\tpcmd->cmdsz = (sizeof(struct setauth_parm));\n\tpcmd->rsp = NULL;\n\tpcmd->rspsz = 0;\n\n\n\t_rtw_init_listhead(&pcmd->list);\n\n\n\tres = rtw_enqueue_cmd(pcmdpriv, pcmd);\n\nexit:\n\n\n\treturn res;\n\n}\n\n\nsint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint keyid, u8 set_tx, bool enqueue)\n{\n\tu8\tkeylen;\n\tstruct cmd_obj\t\t*pcmd;\n\tstruct setkey_parm\t*psetkeyparm;\n\tstruct cmd_priv\t\t*pcmdpriv = &(adapter->cmdpriv);\n\tsint\tres = _SUCCESS;\n\n\n\tpsetkeyparm = (struct setkey_parm *)rtw_zmalloc(sizeof(struct setkey_parm));\n\tif (psetkeyparm == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\t_rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm));\n\n\tif (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) {\n\t\tpsetkeyparm->algorithm = (unsigned char)psecuritypriv->dot118021XGrpPrivacy;\n\t} else {\n\t\tpsetkeyparm->algorithm = (u8)psecuritypriv->dot11PrivacyAlgrthm;\n\n\t}\n\tpsetkeyparm->keyid = (u8)keyid;/* 0~3 */\n\tpsetkeyparm->set_tx = set_tx;\n\tif (is_wep_enc(psetkeyparm->algorithm))\n\t\tadapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid);\n\n\tRTW_INFO(\"==> rtw_set_key algorithm(%x),keyid(%x),key_mask(%x)\\n\", psetkeyparm->algorithm, psetkeyparm->keyid, adapter->securitypriv.key_mask);\n\n\tswitch (psetkeyparm->algorithm) {\n\n\tcase _WEP40_:\n\t\tkeylen = 5;\n\t\t_rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen);\n\t\tbreak;\n\tcase _WEP104_:\n\t\tkeylen = 13;\n\t\t_rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen);\n\t\tbreak;\n\tcase _TKIP_:\n\t\tkeylen = 16;\n\t\t_rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen);\n\t\tbreak;\n\tcase _AES_:\n\t\tkeylen = 16;\n\t\t_rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen);\n\t\tbreak;\n\tdefault:\n\t\tres = _FAIL;\n\t\trtw_mfree((unsigned char *)psetkeyparm, sizeof(struct setkey_parm));\n\t\tgoto exit;\n\t}\n\n\n\tif (enqueue) {\n\t\tpcmd = (struct\tcmd_obj *)rtw_zmalloc(sizeof(struct\tcmd_obj));\n\t\tif (pcmd == NULL) {\n\t\t\trtw_mfree((unsigned char *)psetkeyparm, sizeof(struct setkey_parm));\n\t\t\tres = _FAIL; /* try again */\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpcmd->cmdcode = _SetKey_CMD_;\n\t\tpcmd->parmbuf = (u8 *)psetkeyparm;\n\t\tpcmd->cmdsz = (sizeof(struct setkey_parm));\n\t\tpcmd->rsp = NULL;\n\t\tpcmd->rspsz = 0;\n\n\t\t_rtw_init_listhead(&pcmd->list);\n\n\t\t/* _rtw_init_sema(&(pcmd->cmd_sem), 0); */\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, pcmd);\n\t} else {\n\t\tsetkey_hdl(adapter, (u8 *)psetkeyparm);\n\t\trtw_mfree((u8 *) psetkeyparm, sizeof(struct setkey_parm));\n\t}\nexit:\n\treturn res;\n\n}\n\n#ifdef CONFIG_WMMPS_STA\n/*\n * rtw_uapsd_use_default_setting\n * This function is used for setting default uapsd max sp length to uapsd_max_sp_len\n * in qos_priv data structure from registry. In additional, it will also map default uapsd \n * ac to each uapsd TID, delivery-enabled and trigger-enabled of corresponding TID. \n * \n * Arguments:\n * @padapter: _adapter pointer.\n *\n * Auther: Arvin Liu\n * Date: 2017/05/03\n */\nvoid\trtw_uapsd_use_default_setting(_adapter *padapter)\n{\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct qos_priv\t\t*pqospriv = &pmlmepriv->qospriv;\n\tstruct registry_priv\t\t*pregistrypriv = &padapter->registrypriv;\n\n\tif (pregistrypriv->uapsd_ac_enable != 0) {\n\t\tpqospriv->uapsd_max_sp_len = pregistrypriv->uapsd_max_sp_len;\n\t\t\n\t\tCLEAR_FLAGS(pqospriv->uapsd_tid);\n\t\tCLEAR_FLAGS(pqospriv->uapsd_tid_delivery_enabled);\n\t\tCLEAR_FLAGS(pqospriv->uapsd_tid_trigger_enabled);\n\n\t\t/* check the uapsd setting of AC_VO from registry then map these setting to each TID if necessary  */\n\t\tif(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_VO)) {\n\t\t\tSET_FLAG(pqospriv->uapsd_tid, WMM_TID7);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID7);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID7);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid, WMM_TID6);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID6);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID6);\n\t\t}\n\n\t\t/* check the uapsd setting of AC_VI from registry then map these setting to each TID if necessary  */\n\t\tif(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_VI)) {\t\n\t\t\tSET_FLAG(pqospriv->uapsd_tid, WMM_TID5);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID5);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID5);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid, WMM_TID4);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID4);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID4);\n\t\t}\n\n\t\t/* check the uapsd setting of AC_BK from registry then map these setting to each TID if necessary  */\n\t\tif(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_BK)) {\n\t\t\tSET_FLAG(pqospriv->uapsd_tid, WMM_TID2);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID2);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID2);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid, WMM_TID1);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID1);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID1);\n\t\t}\n\n\t\t/* check the uapsd setting of AC_BE from registry then map these setting to each TID if necessary  */\n\t\tif(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_BE)) {\n\t\t\tSET_FLAG(pqospriv->uapsd_tid, WMM_TID3);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID3);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID3);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid, WMM_TID0);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID0);\n\t\t\tSET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID0);\n\t\t}\n\n\t\tRTW_INFO(\"[WMMPS] UAPSD MAX SP Len = 0x%02x, UAPSD TID enabled = 0x%02x\\n\", \n\t\t\tpqospriv->uapsd_max_sp_len, (u8)pqospriv->uapsd_tid);\n\t}\n\n}\n\n/*\n * rtw_is_wmmps_mode\n * This function is used for checking whether Driver and an AP support uapsd function or not.\n * If both of them support uapsd function, it will return true. Otherwise returns false.\n * \n * Arguments:\n * @padapter: _adapter pointer.\n *\n * Auther: Arvin Liu\n * Date: 2017/06/12\n */\nbool rtw_is_wmmps_mode(_adapter *padapter) \n{\n\tstruct mlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tstruct qos_priv\t*pqospriv = &pmlmepriv->qospriv;\n\t\t\n\tif ((pqospriv->uapsd_ap_supported) && ((pqospriv->uapsd_tid & BIT_MASK_TID_TC)  != 0))\n\t\treturn _TRUE;\n\n\treturn _FALSE;\n}\n#endif /* CONFIG_WMMPS_STA */\n\n/* adjust IEs for rtw_joinbss_cmd in WMM */\nint rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len)\n{\n#ifdef CONFIG_WMMPS_STA\n\tstruct mlme_priv\t\t*pmlmepriv = &adapter->mlmepriv;\n\tstruct qos_priv\t\t*pqospriv = &pmlmepriv->qospriv;\n#endif /* CONFIG_WMMPS_STA */\n\tunsigned\tint ielength = 0;\n\tunsigned int i, j;\n\tu8 qos_info = 0;\n\n\ti = 12; /* after the fixed IE */\n\twhile (i < in_len) {\n\t\tielength = initial_out_len;\n\n\t\tif (in_ie[i] == 0xDD && in_ie[i + 2] == 0x00 && in_ie[i + 3] == 0x50  && in_ie[i + 4] == 0xF2 && in_ie[i + 5] == 0x02 && i + 5 < in_len) { /* WMM element ID and OUI */\n\n\t\t\t/* Append WMM IE to the last index of out_ie */\n#if 0\n\t\t\tfor (j = i; j < i + (in_ie[i + 1] + 2); j++) {\n\t\t\t\tout_ie[ielength] = in_ie[j];\n\t\t\t\tielength++;\n\t\t\t}\n\t\t\tout_ie[initial_out_len + 8] = 0x00; /* force the QoS Info Field to be zero */\n#endif\n\n\t\t\tfor (j = i; j < i + 9; j++) {\n\t\t\t\tout_ie[ielength] = in_ie[j];\n\t\t\t\tielength++;\n\t\t\t}\n\t\t\tout_ie[initial_out_len + 1] = 0x07;\n\t\t\tout_ie[initial_out_len + 6] = 0x00;\n\n#ifdef CONFIG_WMMPS_STA\n\t\t\tswitch(pqospriv->uapsd_max_sp_len) {\n\t\t\t\tcase NO_LIMIT: \n\t\t\t\t\t/* do nothing */\n\t\t\t\t\tbreak;\n\t\t\t\tcase TWO_MSDU: \n\t\t\t\t\tSET_FLAG(qos_info, BIT5);\n\t\t\t\t\tbreak;\n\t\t\t\tcase FOUR_MSDU: \n\t\t\t\t\tSET_FLAG(qos_info, BIT6);\n\t\t\t\t\tbreak;\t\n\t\t\t\tcase SIX_MSDU: \n\t\t\t\t\tSET_FLAG(qos_info, BIT5);\n\t\t\t\t\tSET_FLAG(qos_info, BIT6);\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\t/* do nothing */\n\t\t\t\t\tbreak;\n\t\t\t};\n\n\t\t\t/* check TID7 and TID6 for AC_VO to set corresponding Qos_info bit in WMM IE  */\n\t\t\tif((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID7)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID6)))\n\t\t\t\tSET_FLAG(qos_info, WMM_IE_UAPSD_VO);\n\t\t\t/* check TID5 and TID4 for AC_VI to set corresponding Qos_info bit in WMM IE  */\n\t\t\tif((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID5)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID4)))\n\t\t\t\tSET_FLAG(qos_info, WMM_IE_UAPSD_VI);\n\t\t\t/* check TID2 and TID1 for AC_BK to set corresponding Qos_info bit in WMM IE  */\n\t\t\tif((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID2)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID1)))\n\t\t\t\tSET_FLAG(qos_info, WMM_IE_UAPSD_BK);\n\t\t\t/* check TID3 and TID0 for AC_BE to set corresponding Qos_info bit in WMM IE  */\n\t\t\tif((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID3)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID0)))\n\t\t\t\tSET_FLAG(qos_info, WMM_IE_UAPSD_BE);\n#endif /* CONFIG_WMMPS_STA */\n\t\t\t\n\t\t\tout_ie[initial_out_len + 8] = qos_info;\n\n\t\t\tbreak;\n\t\t}\n\n\t\ti += (in_ie[i + 1] + 2); /* to the next IE element */\n\t}\n\n\treturn ielength;\n\n}\n\n\n/*\n * Ported from 8185: IsInPreAuthKeyList(). (Renamed from SecIsInPreAuthKeyList(), 2006-10-13.)\n * Added by Annie, 2006-05-07.\n *\n * Search by BSSID,\n * Return Value:\n *\t\t-1\t\t:if there is no pre-auth key in the  table\n *\t\t>=0\t\t:if there is pre-auth key, and   return the entry id\n *\n *   */\n\nstatic int SecIsInPMKIDList(_adapter *Adapter, u8 *bssid)\n{\n\tstruct security_priv *psecuritypriv = &Adapter->securitypriv;\n\tint i = 0;\n\n\tdo {\n\t\tif ((psecuritypriv->PMKIDList[i].bUsed) &&\n\t\t    (_rtw_memcmp(psecuritypriv->PMKIDList[i].Bssid, bssid, ETH_ALEN) == _TRUE))\n\t\t\tbreak;\n\t\telse {\n\t\t\ti++;\n\t\t\t/* continue; */\n\t\t}\n\n\t} while (i < NUM_PMKID_CACHE);\n\n\tif (i == NUM_PMKID_CACHE) {\n\t\ti = -1;/* Could not find. */\n\t} else {\n\t\t/* There is one Pre-Authentication Key for the specific BSSID. */\n\t}\n\n\treturn i;\n\n}\n\nint rtw_cached_pmkid(_adapter *Adapter, u8 *bssid)\n{\n\treturn SecIsInPMKIDList(Adapter, bssid);\n}\n\nint rtw_rsn_sync_pmkid(_adapter *adapter, u8 *ie, uint ie_len, int i_ent)\n{\n\tstruct security_priv *sec = &adapter->securitypriv;\n\tstruct rsne_info info;\n\tu8 gm_cs[4];\n\tint i;\n\n\trtw_rsne_info_parse(ie, ie_len, &info);\n\n\tif (info.err) {\n\t\tRTW_WARN(FUNC_ADPT_FMT\" rtw_rsne_info_parse error\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter));\n\t\treturn 0;\n\t}\n\n\tif (i_ent < 0 && info.pmkid_cnt == 0)\n\t\tgoto exit;\n\n\tif (i_ent >= 0 && info.pmkid_cnt == 1 && _rtw_memcmp(info.pmkid_list, sec->PMKIDList[i_ent].PMKID, 16)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" has carried the same PMKID:\"KEY_FMT\"\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), KEY_ARG(&sec->PMKIDList[i_ent].PMKID));\n\t\tgoto exit;\n\t}\n\n\t/* bakcup group mgmt cs */\n\tif (info.gmcs)\n\t\t_rtw_memcpy(gm_cs, info.gmcs, 4);\n\n\tif (info.pmkid_cnt) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" remove original PMKID, count:%u\\n\"\n\t\t\t , FUNC_ADPT_ARG(adapter), info.pmkid_cnt);\n\t\tfor (i = 0; i < info.pmkid_cnt; i++)\n\t\t\tRTW_INFO(\"    \"KEY_FMT\"\\n\", KEY_ARG(info.pmkid_list + i * 16));\n\t}\n\n\tif (i_ent >= 0) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" append PMKID:\"KEY_FMT\"\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), KEY_ARG(sec->PMKIDList[i_ent].PMKID));\n\n\t\tinfo.pmkid_cnt = 1; /* update new pmkid_cnt */\n\t\t_rtw_memcpy(info.pmkid_list, sec->PMKIDList[i_ent].PMKID, 16);\n\t} else\n\t\tinfo.pmkid_cnt = 0; /* update new pmkid_cnt */\n\n\tRTW_PUT_LE16(info.pmkid_list - 2, info.pmkid_cnt);\n\tif (info.gmcs)\n\t\t_rtw_memcpy(info.pmkid_list + 16 * info.pmkid_cnt, gm_cs, 4);\n\n\tie_len = 1 + 1 + 2 + 4\n\t\t+ 2 + 4 * info.pcs_cnt\n\t\t+ 2 + 4 * info.akm_cnt\n\t\t+ 2\n\t\t+ 2 + 16 * info.pmkid_cnt\n\t\t+ (info.gmcs ? 4 : 0)\n\t\t;\n\t\n\tie[1] = (u8)(ie_len - 2);\n\nexit:\n\treturn ie_len;\n}\n\nsint rtw_restruct_sec_ie(_adapter *adapter, u8 *out_ie)\n{\n\tu8 authmode = 0x0;\n\tuint\tielength = 0;\n\tint iEntry;\n\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tstruct security_priv *psecuritypriv = &adapter->securitypriv;\n\tuint\tndisauthmode = psecuritypriv->ndisauthtype;\n\n\tif ((ndisauthmode == Ndis802_11AuthModeWPA) || (ndisauthmode == Ndis802_11AuthModeWPAPSK))\n\t\tauthmode = _WPA_IE_ID_;\n\tif ((ndisauthmode == Ndis802_11AuthModeWPA2) || (ndisauthmode == Ndis802_11AuthModeWPA2PSK))\n\t\tauthmode = _WPA2_IE_ID_;\n\n\tif (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {\n\t\t_rtw_memcpy(out_ie, psecuritypriv->wps_ie, psecuritypriv->wps_ie_len);\n\t\tielength = psecuritypriv->wps_ie_len;\n\n\t} else if ((authmode == _WPA_IE_ID_) || (authmode == _WPA2_IE_ID_)) {\n\t\t/* copy RSN or SSN\t\t */\n\t\t_rtw_memcpy(out_ie, psecuritypriv->supplicant_ie, psecuritypriv->supplicant_ie[1] + 2);\n\t\t/* debug for CONFIG_IEEE80211W\n\t\t{\n\t\t\tint jj;\n\t\t\tprintk(\"supplicant_ie_length=%d &&&&&&&&&&&&&&&&&&&\\n\", psecuritypriv->supplicant_ie[1]+2);\n\t\t\tfor(jj=0; jj < psecuritypriv->supplicant_ie[1]+2; jj++)\n\t\t\t\tprintk(\" %02x \", psecuritypriv->supplicant_ie[jj]);\n\t\t\tprintk(\"\\n\");\n\t\t}*/\n\t\tielength = psecuritypriv->supplicant_ie[1] + 2;\n\t\trtw_report_sec_ie(adapter, authmode, psecuritypriv->supplicant_ie);\n\t}\n\n\tif (authmode == WLAN_EID_RSN) {\n\t\tiEntry = SecIsInPMKIDList(adapter, pmlmepriv->assoc_bssid);\n\t\tielength = rtw_rsn_sync_pmkid(adapter, out_ie, ielength, iEntry);\n\t}\n\n\treturn ielength;\n}\n\nvoid rtw_init_registrypriv_dev_network(_adapter *adapter)\n{\n\tstruct registry_priv *pregistrypriv = &adapter->registrypriv;\n\tWLAN_BSSID_EX    *pdev_network = &pregistrypriv->dev_network;\n\tu8 *myhwaddr = adapter_mac_addr(adapter);\n\n\n\t_rtw_memcpy(pdev_network->MacAddress, myhwaddr, ETH_ALEN);\n\n\t_rtw_memcpy(&pdev_network->Ssid, &pregistrypriv->ssid, sizeof(NDIS_802_11_SSID));\n\n\tpdev_network->Configuration.Length = sizeof(NDIS_802_11_CONFIGURATION);\n\tpdev_network->Configuration.BeaconPeriod = 100;\n}\n\nvoid rtw_update_registrypriv_dev_network(_adapter *adapter)\n{\n\tint sz = 0;\n\tstruct registry_priv *pregistrypriv = &adapter->registrypriv;\n\tWLAN_BSSID_EX    *pdev_network = &pregistrypriv->dev_network;\n\tstruct\tsecurity_priv\t*psecuritypriv = &adapter->securitypriv;\n\tstruct\twlan_network\t*cur_network = &adapter->mlmepriv.cur_network;\n\t/* struct\txmit_priv\t*pxmitpriv = &adapter->xmitpriv; */\n\tstruct mlme_ext_priv\t*pmlmeext = &adapter->mlmeextpriv;\n\n\n#if 0\n\tpxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense;\n\tpxmitpriv->vcs = pregistrypriv->vcs_type;\n\tpxmitpriv->vcs_type = pregistrypriv->vcs_type;\n\t/* pxmitpriv->rts_thresh = pregistrypriv->rts_thresh; */\n\tpxmitpriv->frag_len = pregistrypriv->frag_thresh;\n\n\tadapter->qospriv.qos_option = pregistrypriv->wmm_enable;\n#endif\n\n\tpdev_network->Privacy = (psecuritypriv->dot11PrivacyAlgrthm > 0 ? 1 : 0) ; /* adhoc no 802.1x */\n\n\tpdev_network->Rssi = 0;\n\n\tpdev_network->Configuration.DSConfig = (pregistrypriv->channel);\n\n\tif (cur_network->network.InfrastructureMode == Ndis802_11IBSS) {\n\t\tpdev_network->Configuration.ATIMWindow = (0);\n\n\t\tif (pmlmeext->cur_channel != 0)\n\t\t\tpdev_network->Configuration.DSConfig = pmlmeext->cur_channel;\n\t\telse\n\t\t\tpdev_network->Configuration.DSConfig = 1;\n\t}\n\n\tpdev_network->InfrastructureMode = (cur_network->network.InfrastructureMode);\n\n\t/* 1. Supported rates */\n\t/* 2. IE */\n\n\t/* rtw_set_supported_rate(pdev_network->SupportedRates, pregistrypriv->wireless_mode) ; */ /* will be called in rtw_generate_ie */\n\tsz = rtw_generate_ie(pregistrypriv);\n\n\tpdev_network->IELength = sz;\n\n\tpdev_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pdev_network);\n\n\t/* notes: translate IELength & Length after assign the Length to cmdsz in createbss_cmd(); */\n\t/* pdev_network->IELength = cpu_to_le32(sz); */\n\n\n}\n\nvoid rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter)\n{\n\n\n\n}\n\n/* the fucntion is at passive_level */\nvoid rtw_joinbss_reset(_adapter *padapter)\n{\n\tu8\tthreshold;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\t/* todo: if you want to do something io/reg/hw setting before join_bss, please add code here */\n\n#ifdef CONFIG_80211N_HT\n\tstruct ht_priv\t\t*phtpriv = &pmlmepriv->htpriv;\n\n\tpmlmepriv->num_FortyMHzIntolerant = 0;\n\n\tpmlmepriv->num_sta_no_ht = 0;\n\n\tphtpriv->ampdu_enable = _FALSE;/* reset to disabled */\n\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)\n\t/* TH=1 => means that invalidate usb rx aggregation */\n\t/* TH=0 => means that validate usb rx aggregation, use init value. */\n\tif (phtpriv->ht_option) {\n\t\tif (padapter->registrypriv.wifi_spec == 1)\n\t\t\tthreshold = 1;\n\t\telse\n\t\t\tthreshold = 0;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));\n\t} else {\n\t\tthreshold = 1;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));\n\t}\n#endif/* #if defined( CONFIG_USB_HCI) || defined (CONFIG_SDIO_HCI) */\n\n#endif/* #ifdef CONFIG_80211N_HT */\n\n}\n\n\n#ifdef CONFIG_80211N_HT\nvoid\trtw_ht_use_default_setting(_adapter *padapter)\n{\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct ht_priv\t\t*phtpriv = &pmlmepriv->htpriv;\n\tstruct registry_priv\t*pregistrypriv = &padapter->registrypriv;\n\tBOOLEAN\t\tbHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE;\n#ifdef CONFIG_BEAMFORMING\n\tBOOLEAN\t\tbHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE;\n#endif /* CONFIG_BEAMFORMING */\n\n\tif (pregistrypriv->wifi_spec)\n\t\tphtpriv->bss_coexist = 1;\n\telse\n\t\tphtpriv->bss_coexist = 0;\n\n\tphtpriv->sgi_40m = TEST_FLAG(pregistrypriv->short_gi, BIT1) ? _TRUE : _FALSE;\n\tphtpriv->sgi_20m = TEST_FLAG(pregistrypriv->short_gi, BIT0) ? _TRUE : _FALSE;\n\n\t/* LDPC support */\n\trtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport);\n\tCLEAR_FLAGS(phtpriv->ldpc_cap);\n\tif (bHwLDPCSupport) {\n\t\tif (TEST_FLAG(pregistrypriv->ldpc_cap, BIT4))\n\t\t\tSET_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX);\n\t}\n\trtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport);\n\tif (bHwLDPCSupport) {\n\t\tif (TEST_FLAG(pregistrypriv->ldpc_cap, BIT5))\n\t\t\tSET_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX);\n\t}\n\tif (phtpriv->ldpc_cap)\n\t\tRTW_INFO(\"[HT] HAL Support LDPC = 0x%02X\\n\", phtpriv->ldpc_cap);\n\n\t/* STBC */\n\trtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport);\n\tCLEAR_FLAGS(phtpriv->stbc_cap);\n\tif (bHwSTBCSupport) {\n\t\tif (TEST_FLAG(pregistrypriv->stbc_cap, BIT5))\n\t\t\tSET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX);\n\t}\n\trtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport);\n\tif (bHwSTBCSupport) {\n\t\tif (TEST_FLAG(pregistrypriv->stbc_cap, BIT4))\n\t\t\tSET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX);\n\t}\n\tif (phtpriv->stbc_cap)\n\t\tRTW_INFO(\"[HT] HAL Support STBC = 0x%02X\\n\", phtpriv->stbc_cap);\n\n\t/* Beamforming setting */\n\tCLEAR_FLAGS(phtpriv->beamform_cap);\n#ifdef CONFIG_BEAMFORMING\n#ifdef RTW_BEAMFORMING_VERSION_2\n\t/* only enable beamforming in STA client mode */\n\tif (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter)\n\t\t\t\t  && !MLME_IS_ADHOC(padapter)\n\t\t\t\t  && !MLME_IS_MESH(padapter))\n#endif\n\t{\n\t\trtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer);\n\t\trtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee);\n\t\tif (TEST_FLAG(pregistrypriv->beamform_cap, BIT4) && bHwSupportBeamformer) {\n\t\t\tSET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);\n\t\t\tRTW_INFO(\"[HT] HAL Support Beamformer\\n\");\n\t\t}\n\t\tif (TEST_FLAG(pregistrypriv->beamform_cap, BIT5) && bHwSupportBeamformee) {\n\t\t\tSET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);\n\t\t\tRTW_INFO(\"[HT] HAL Support Beamformee\\n\");\n\t\t}\n\t}\n#endif /* CONFIG_BEAMFORMING */\n}\nvoid rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len)\n{\n\tunsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00};\n\tint out_len;\n\tu8 *pframe;\n\n\tif (padapter->mlmepriv.qospriv.qos_option == 0) {\n\t\tout_len = *pout_len;\n\t\tpframe = rtw_set_ie(out_ie + out_len, _VENDOR_SPECIFIC_IE_,\n\t\t\t\t    _WMM_IE_Length_, WMM_IE, pout_len);\n\n\t\tpadapter->mlmepriv.qospriv.qos_option = 1;\n\t}\n}\n#if defined(CONFIG_80211N_HT)\n/* the fucntion is >= passive_level */\nunsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel)\n{\n\tu32 ielen, out_len;\n\tu32 rx_packet_offset, max_recvbuf_sz;\n\tHT_CAP_AMPDU_FACTOR max_rx_ampdu_factor;\n\tHT_CAP_AMPDU_DENSITY best_ampdu_density;\n\tunsigned char *p, *pframe;\n\tstruct rtw_ieee80211_ht_cap ht_capie;\n\tu8\tcbw40_enable = 0, rf_type = 0, rf_num = 0, rx_stbc_nss = 0, rx_nss = 0;\n\tstruct registry_priv *pregistrypriv = &padapter->registrypriv;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct ht_priv\t\t*phtpriv = &pmlmepriv->htpriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);\n#ifdef CONFIG_80211AC_VHT\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct vht_priv\t*pvhtpriv = &pmlmepriv->vhtpriv;\n#endif /* CONFIG_80211AC_VHT */\n\n\tphtpriv->ht_option = _FALSE;\n\n\tout_len = *pout_len;\n\n\t_rtw_memset(&ht_capie, 0, sizeof(struct rtw_ieee80211_ht_cap));\n\n\tht_capie.cap_info = IEEE80211_HT_CAP_DSSSCCK40;\n\n\tif (phtpriv->sgi_20m)\n\t\tht_capie.cap_info |= IEEE80211_HT_CAP_SGI_20;\n\n\t/* check if 40MHz is allowed according to hal cap and registry */\n\tif (hal_chk_bw_cap(padapter, BW_CAP_40M)) {\n\t\tif (channel > 14) {\n\t\t\tif (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))\n\t\t\t\tcbw40_enable = 1;\n\t\t} else {\n\t\t\tif (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))\n\t\t\t\tcbw40_enable = 1;\n\t\t}\n\t}\n\n\tif (cbw40_enable) {\n\t\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\t\tRT_CHANNEL_INFO *chset = rfctl->channel_set;\n\t\tu8 oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\n\t\tif (in_ie == NULL) {\n\t\t\t/* TDLS: TODO 20/40 issue */\n\t\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {\n\t\t\t\toper_bw = padapter->mlmeextpriv.cur_bwmode;\n\t\t\t\tif (oper_bw > CHANNEL_WIDTH_40)\n\t\t\t\t\toper_bw = CHANNEL_WIDTH_40;\n\t\t\t} else\n\t\t\t\t/* TDLS: TODO 40? */\n\t\t\t\toper_bw = CHANNEL_WIDTH_40;\n\t\t} else {\n\t\t\tp = rtw_get_ie(in_ie, WLAN_EID_HT_OPERATION, &ielen, in_len);\n\t\t\tif (p && ielen == HT_OP_IE_LEN) {\n\t\t\t\tif (GET_HT_OP_ELE_STA_CHL_WIDTH(p + 2)) {\n\t\t\t\t\tswitch (GET_HT_OP_ELE_2ND_CHL_OFFSET(p + 2)) {\n\t\t\t\t\tcase SCA:\n\t\t\t\t\t\toper_bw = CHANNEL_WIDTH_40;\n\t\t\t\t\t\toper_offset = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase SCB:\n\t\t\t\t\t\toper_bw = CHANNEL_WIDTH_40;\n\t\t\t\t\t\toper_offset = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n            // IOT issue : AP TP-Link WDR6500\n            if(oper_bw == CHANNEL_WIDTH_40){\n                p = rtw_get_ie(in_ie, WLAN_EID_HT_CAP, &ielen, in_len);\n                if (p && ielen == HT_CAP_IE_LEN) {\n                    oper_bw = GET_HT_CAP_ELE_CHL_WIDTH(p + 2)  ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20;\n                    if(oper_bw == CHANNEL_WIDTH_20)\n                        oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n                }\n            }\n\t\t}\n\n\t\t/* adjust bw to fit in channel plan setting */\n\t\tif (oper_bw == CHANNEL_WIDTH_40\n\t\t\t&& oper_offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE /* check this because TDLS has no info to set offset */\n\t\t\t&& (!rtw_chset_is_chbw_valid(chset, channel, oper_bw, oper_offset)\n\t\t\t\t|| (IS_DFS_SLAVE_WITH_RD(rfctl)\n\t\t\t\t\t&& !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))\n\t\t\t\t\t&& rtw_chset_is_chbw_non_ocp(chset, channel, oper_bw, oper_offset))\n\t\t\t\t)\n\t\t) {\n\t\t\toper_bw = CHANNEL_WIDTH_20;\n\t\t\toper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t\trtw_warn_on(!rtw_chset_is_chbw_valid(chset, channel, oper_bw, oper_offset));\n\t\t\tif (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl)))\n\t\t\t\trtw_warn_on(rtw_chset_is_chbw_non_ocp(chset, channel, oper_bw, oper_offset));\n\t\t}\n\n\t\tif (oper_bw == CHANNEL_WIDTH_40) {\n\t\t\tht_capie.cap_info |= IEEE80211_HT_CAP_SUP_WIDTH;\n\t\t\tif (phtpriv->sgi_40m)\n\t\t\t\tht_capie.cap_info |= IEEE80211_HT_CAP_SGI_40;\n\t\t}\n\n\t\tcbw40_enable = oper_bw == CHANNEL_WIDTH_40 ? 1 : 0;\n\t}\n\n\t/* todo: disable SM power save mode */\n\tht_capie.cap_info |= IEEE80211_HT_CAP_SM_PS;\n\n\t/* RX LDPC */\n\tif (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX)) {\n\t\tht_capie.cap_info |= IEEE80211_HT_CAP_LDPC_CODING;\n\t\tRTW_INFO(\"[HT] Declare supporting RX LDPC\\n\");\n\t}\n\n\t/* TX STBC */\n\tif (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX)) {\n\t\tht_capie.cap_info |= IEEE80211_HT_CAP_TX_STBC;\n\t\tRTW_INFO(\"[HT] Declare supporting TX STBC\\n\");\n\t}\n\n\t/* RX STBC */\n\tif (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) {\n\t\tif ((pregistrypriv->rx_stbc == 0x3) ||\t\t\t\t\t\t\t/* enable for 2.4/5 GHz */\n\t\t    ((channel <= 14) && (pregistrypriv->rx_stbc == 0x1)) ||\t\t/* enable for 2.4GHz */\n\t\t    ((channel > 14) && (pregistrypriv->rx_stbc == 0x2)) ||\t\t/* enable for 5GHz */\n\t\t    (pregistrypriv->wifi_spec == 1)) {\n\t\t\t/* HAL_DEF_RX_STBC means STBC RX spatial stream, todo: VHT 4 streams */\n\t\t\trtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss));\n\t\t\tSET_HT_CAP_ELE_RX_STBC(&ht_capie, rx_stbc_nss);\n\t\t\tRTW_INFO(\"[HT] Declare supporting RX STBC = %d\\n\", rx_stbc_nss);\n\t\t}\n\t}\n\n\t/* fill default supported_mcs_set */\n\t_rtw_memcpy(ht_capie.supp_mcs_set, pmlmeext->default_supported_mcs_set, 16);\n\n\t/* update default supported_mcs_set */\n\trtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));\n\trx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num);\n\n\tswitch (rx_nss) {\n\tcase 1:\n\t\tset_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_1R);\n\t\tbreak;\n\tcase 2:\n\t\t#ifdef CONFIG_DISABLE_MCS13TO15\n\t\tif (cbw40_enable && pregistrypriv->wifi_spec != 1)\n\t\t\tset_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R_13TO15_OFF);\n\t\telse\n\t\t#endif\n\t\t\tset_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R);\n\t\tbreak;\n\tcase 3:\n\t\tset_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_3R);\n\t\tbreak;\n\tcase 4:\n\t\tset_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_4R);\n\t\tbreak;\n\tdefault:\n\t\tRTW_WARN(\"rf_type:%d or rx_nss:%u is not expected\\n\", rf_type, hal_spec->rx_nss_num);\n\t}\n\n\t{\n\t\trtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset);\n\t\trtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz);\n\t\tif (max_recvbuf_sz - rx_packet_offset >= (8191 - 256)) {\n\t\t\tRTW_INFO(\"%s IEEE80211_HT_CAP_MAX_AMSDU is set\\n\", __FUNCTION__);\n\t\t\tht_capie.cap_info = ht_capie.cap_info | IEEE80211_HT_CAP_MAX_AMSDU;\n\t\t}\n\t}\n\t/*\n\tAMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k\n\tAMPDU_para [4:2]:Min MPDU Start Spacing\n\t*/\n\n\t/*\n\t#if defined(CONFIG_RTL8188E) && defined(CONFIG_SDIO_HCI)\n\tht_capie.ampdu_params_info = 2;\n\t#else\n\tht_capie.ampdu_params_info = (IEEE80211_HT_CAP_AMPDU_FACTOR&0x03);\n\t#endif\n\t*/\n\n\tif (padapter->driver_rx_ampdu_factor != 0xFF)\n\t\tmax_rx_ampdu_factor = (HT_CAP_AMPDU_FACTOR)padapter->driver_rx_ampdu_factor;\n\telse\n\t\trtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor);\n\n\t/* rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); */\n\tht_capie.ampdu_params_info = (max_rx_ampdu_factor & 0x03);\n\n\tif (padapter->driver_rx_ampdu_spacing != 0xFF)\n\t\tht_capie.ampdu_params_info |= ((padapter->driver_rx_ampdu_spacing & 0x07) << 2);\n\telse {\n\t\tif (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_) {\n\t\t\t/*\n\t\t\t*\tTodo : Each chip must to ask DD , this chip best ampdu_density setting\n\t\t\t*\tBy yiwei.sun\n\t\t\t*/\n\t\t\trtw_hal_get_def_var(padapter, HW_VAR_BEST_AMPDU_DENSITY, &best_ampdu_density);\n\n\t\t\tht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & (best_ampdu_density << 2));\n\n\t\t} else\n\t\t\tht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & 0x00);\n\t}\n#ifdef CONFIG_BEAMFORMING\n\tht_capie.tx_BF_cap_info = 0;\n\n\t/* HT Beamformer*/\n\tif (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {\n\t\t/* Transmit NDP Capable */\n\t\tSET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(&ht_capie, 1);\n\t\t/* Explicit Compressed Steering Capable */\n\t\tSET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(&ht_capie, 1);\n\t\t/* Compressed Steering Number Antennas */\n\t\tSET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(&ht_capie, 1);\n\t\trtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num);\n\t\tSET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(&ht_capie, rf_num);\n\t}\n\n\t/* HT Beamformee */\n\tif (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) {\n\t\t/* Receive NDP Capable */\n\t\tSET_HT_CAP_TXBF_RECEIVE_NDP_CAP(&ht_capie, 1);\n\t\t/* Explicit Compressed Beamforming Feedback Capable */\n\t\tSET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(&ht_capie, 2);\n\n\t\trtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);\n#ifdef CONFIG_80211AC_VHT\n\t\t/* IOT action suggested by Yu Chen 2017/3/3 */\n\t\tif ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) &&\n\t\t\t!pvhtpriv->ap_is_mu_bfer)\n\t\t\trf_num = (rf_num >= 2 ? 2 : rf_num);\n#endif\n\t\tSET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(&ht_capie, rf_num);\n\t}\n#endif/*CONFIG_BEAMFORMING*/\n\n\tpframe = rtw_set_ie(out_ie + out_len, _HT_CAPABILITY_IE_,\n\t\tsizeof(struct rtw_ieee80211_ht_cap), (unsigned char *)&ht_capie, pout_len);\n\n\tphtpriv->ht_option = _TRUE;\n\n\tif (in_ie != NULL) {\n\t\tp = rtw_get_ie(in_ie, _HT_ADD_INFO_IE_, &ielen, in_len);\n\t\tif (p && (ielen == sizeof(struct ieee80211_ht_addt_info))) {\n\t\t\tout_len = *pout_len;\n\t\t\tpframe = rtw_set_ie(out_ie + out_len, _HT_ADD_INFO_IE_, ielen, p + 2 , pout_len);\n\t\t}\n\t}\n\n\treturn phtpriv->ht_option;\n\n}\n\n/* the fucntion is > passive_level (in critical_section) */\nvoid rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel)\n{\n\tu8 *p, max_ampdu_sz;\n\tint len;\n\t/* struct sta_info *bmc_sta, *psta; */\n\tstruct rtw_ieee80211_ht_cap *pht_capie;\n\tstruct ieee80211_ht_addt_info *pht_addtinfo;\n\t/* struct recv_reorder_ctrl *preorder_ctrl; */\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct ht_priv\t\t*phtpriv = &pmlmepriv->htpriv;\n\t/* struct recv_priv *precvpriv = &padapter->recvpriv; */\n\tstruct registry_priv *pregistrypriv = &padapter->registrypriv;\n\t/* struct wlan_network *pcur_network = &(pmlmepriv->cur_network);; */\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8 cbw40_enable = 0;\n\n\n\tif (!phtpriv->ht_option)\n\t\treturn;\n\n\tif ((!pmlmeinfo->HT_info_enable) || (!pmlmeinfo->HT_caps_enable))\n\t\treturn;\n\n\tRTW_INFO(\"+rtw_update_ht_cap()\\n\");\n\n\t/* maybe needs check if ap supports rx ampdu. */\n\tif ((phtpriv->ampdu_enable == _FALSE) && (pregistrypriv->ampdu_enable == 1)) {\n\t\tif (pregistrypriv->wifi_spec == 1) {\n\t\t\t/* remove this part because testbed AP should disable RX AMPDU */\n\t\t\t/* phtpriv->ampdu_enable = _FALSE; */\n\t\t\tphtpriv->ampdu_enable = _TRUE;\n\t\t} else\n\t\t\tphtpriv->ampdu_enable = _TRUE;\n\t} \n\n\n\t/* check Max Rx A-MPDU Size */\n\tlen = 0;\n\tp = rtw_get_ie(pie + sizeof(NDIS_802_11_FIXED_IEs), _HT_CAPABILITY_IE_, &len, ie_len - sizeof(NDIS_802_11_FIXED_IEs));\n\tif (p && len > 0) {\n\t\tpht_capie = (struct rtw_ieee80211_ht_cap *)(p + 2);\n\t\tmax_ampdu_sz = (pht_capie->ampdu_params_info & IEEE80211_HT_CAP_AMPDU_FACTOR);\n\t\tmax_ampdu_sz = 1 << (max_ampdu_sz + 3); /* max_ampdu_sz (kbytes); */\n\n\t\t/* RTW_INFO(\"rtw_update_ht_cap(): max_ampdu_sz=%d\\n\", max_ampdu_sz); */\n\t\tphtpriv->rx_ampdu_maxlen = max_ampdu_sz;\n\n\t}\n\n\n\tlen = 0;\n\tp = rtw_get_ie(pie + sizeof(NDIS_802_11_FIXED_IEs), _HT_ADD_INFO_IE_, &len, ie_len - sizeof(NDIS_802_11_FIXED_IEs));\n\tif (p && len > 0) {\n\t\tpht_addtinfo = (struct ieee80211_ht_addt_info *)(p + 2);\n\t\t/* todo: */\n\t}\n\n\tif (hal_chk_bw_cap(padapter, BW_CAP_40M)) {\n\t\tif (channel > 14) {\n\t\t\tif (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))\n\t\t\t\tcbw40_enable = 1;\n\t\t} else {\n\t\t\tif (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))\n\t\t\t\tcbw40_enable = 1;\n\t\t}\n\t}\n\n\t/* update cur_bwmode & cur_ch_offset */\n\tif ((cbw40_enable) &&\n\t    (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) &&\n\t    (pmlmeinfo->HT_info.infos[0] & BIT(2))) {\n\t\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);\n\t\tint i;\n\t\tu8\trf_type = RF_1T1R;\n\t\tu8 tx_nss = 0;\n\n\t\trtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));\n\t\ttx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);\n\n\t\t/* update the MCS set */\n\t\tfor (i = 0; i < 16; i++)\n\t\t\tpmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i];\n\n\t\t/* update the MCS rates */\n\t\tswitch (tx_nss) {\n\t\tcase 1:\n\t\t\tset_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R);\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\t#ifdef CONFIG_DISABLE_MCS13TO15\n\t\t\tif (pmlmeext->cur_bwmode == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1)\n\t\t\t\tset_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R_13TO15_OFF);\n\t\t\telse\n\t\t\t#endif\n\t\t\t\tset_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R);\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\tset_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R);\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\tset_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_4R);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tRTW_WARN(\"rf_type:%d or tx_nss_num:%u is not expected\\n\", rf_type, hal_spec->tx_nss_num);\n\t\t}\n\n\t\t/* switch to the 40M Hz mode accoring to the AP */\n\t\t/* pmlmeext->cur_bwmode = CHANNEL_WIDTH_40; */\n\t\tswitch ((pmlmeinfo->HT_info.infos[0] & 0x3)) {\n\t\tcase EXTCHNL_OFFSET_UPPER:\n\t\t\tpmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\t\tbreak;\n\n\t\tcase EXTCHNL_OFFSET_LOWER:\n\t\t\tpmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tpmlmeext->cur_bwmode = CHANNEL_WIDTH_20;\n\t\t\tpmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t\tRTW_INFO(\"%s : ch offset is not assigned for HT40 mod , update cur_bwmode=%u, cur_ch_offset=%u\\n\", \n\t\t\t\t\t__func__, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/*  */\n\t/* Config SM Power Save setting */\n\t/*  */\n\tpmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2;\n\tif (pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) {\n#if 0\n\t\tu8 i;\n\t\t/* update the MCS rates */\n\t\tfor (i = 0; i < 16; i++)\n\t\t\tpmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];\n#endif\n\t\tRTW_INFO(\"%s(): WLAN_HT_CAP_SM_PS_STATIC\\n\", __FUNCTION__);\n\t}\n\n\t/*  */\n\t/* Config current HT Protection mode. */\n\t/*  */\n\tpmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3;\n}\n#endif\n\n#ifdef CONFIG_TDLS\nvoid rtw_issue_addbareq_cmd_tdls(_adapter *padapter, struct xmit_frame *pxmitframe)\n{\n\tstruct pkt_attrib *pattrib = &pxmitframe->attrib;\n\tstruct sta_info *ptdls_sta = NULL;\n\tu8 issued;\n\tint priority;\n\tstruct ht_priv\t*phtpriv;\n\n\tpriority = pattrib->priority;\n\n\tif (pattrib->direct_link == _TRUE) {\n\t\tptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst);\n\t\tif ((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) {\n\t\t\tphtpriv = &ptdls_sta->htpriv;\n\n\t\t\tif ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) {\n\t\t\t\tissued = (phtpriv->agg_enable_bitmap >> priority) & 0x1;\n\t\t\t\tissued |= (phtpriv->candidate_tid_bitmap >> priority) & 0x1;\n\n\t\t\t\tif (0 == issued) {\n\t\t\t\t\tRTW_INFO(\"[%s], p=%d\\n\", __FUNCTION__, priority);\n\t\t\t\t\tptdls_sta->htpriv.candidate_tid_bitmap |= BIT((u8)priority);\n\t\t\t\t\trtw_addbareq_cmd(padapter, (u8)priority, pattrib->dst);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n#endif /* CONFIG_TDLS */\n\n#ifdef CONFIG_80211N_HT\nstatic u8 rtw_issue_addbareq_check(_adapter *padapter, struct xmit_frame *pxmitframe, u8 issue_when_busy)\n{\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct registry_priv *pregistry = &padapter->registrypriv;\n\tstruct pkt_attrib *pattrib = &pxmitframe->attrib;\n\ts32 bmcst = IS_MCAST(pattrib->ra);\n\n\tif (bmcst)\n\t\treturn _FALSE;\n\n\tif (pregistry->tx_quick_addba_req == 0) {\n\t\tif ((issue_when_busy == _TRUE) && (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE))\n\t\t\treturn _FALSE;\n\n\t\tif (pmlmepriv->LinkDetectInfo.NumTxOkInPeriod < 100)\n\t\t\treturn _FALSE;\n\t}\n\n\treturn _TRUE;\n}\n\nvoid rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe, u8 issue_when_busy)\n{\n\tu8 issued;\n\tint priority;\n\tstruct sta_info *psta = NULL;\n\tstruct ht_priv\t*phtpriv;\n\tstruct pkt_attrib *pattrib = &pxmitframe->attrib;\n\n\tif (rtw_issue_addbareq_check(padapter,pxmitframe, issue_when_busy) == _FALSE)\n\t\treturn;\n\n\tpriority = pattrib->priority;\n\n#ifdef CONFIG_TDLS\n\trtw_issue_addbareq_cmd_tdls(padapter, pxmitframe);\n#endif /* CONFIG_TDLS */\n\n\tpsta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);\n\tif (pattrib->psta != psta) {\n\t\tRTW_INFO(\"%s, pattrib->psta(%p) != psta(%p)\\n\", __func__, pattrib->psta, psta);\n\t\treturn;\n\t}\n\n\tif (psta == NULL) {\n\t\tRTW_INFO(\"%s, psta==NUL\\n\", __func__);\n\t\treturn;\n\t}\n\n\tif (!(psta->state & _FW_LINKED)) {\n\t\tRTW_INFO(\"%s, psta->state(0x%x) != _FW_LINKED\\n\", __func__, psta->state);\n\t\treturn;\n\t}\n\n\n\tphtpriv = &psta->htpriv;\n\n\tif ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) {\n\t\tissued = (phtpriv->agg_enable_bitmap >> priority) & 0x1;\n\t\tissued |= (phtpriv->candidate_tid_bitmap >> priority) & 0x1;\n\n\t\tif (0 == issued) {\n\t\t\tRTW_INFO(\"rtw_issue_addbareq_cmd, p=%d\\n\", priority);\n\t\t\tpsta->htpriv.candidate_tid_bitmap |= BIT((u8)priority);\n\t\t\trtw_addbareq_cmd(padapter, (u8) priority, pattrib->ra);\n\t\t}\n\t}\n\n}\n#endif /* CONFIG_80211N_HT */\nvoid rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len)\n{\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct ht_priv\t\t*phtpriv = &pmlmepriv->htpriv;\n#ifdef CONFIG_80211AC_VHT\n\tstruct vht_priv\t*pvhtpriv = &pmlmepriv->vhtpriv;\n#endif /* CONFIG_80211AC_VHT */\n\tu8\tcap_content[8] = { 0 };\n\tu8\t*pframe;\n\tu8   null_content[8] = {0};\n\n\tif (phtpriv->bss_coexist)\n\t\tSET_EXT_CAPABILITY_ELE_BSS_COEXIST(cap_content, 1);\n\n#ifdef CONFIG_80211AC_VHT\n\tif (pvhtpriv->vht_option)\n\t\tSET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(cap_content, 1);\n#endif /* CONFIG_80211AC_VHT */\n#ifdef CONFIG_RTW_WNM\n\trtw_wnm_set_ext_cap_btm(cap_content, 1);\n#endif\n\t/*\n\t\tFrom 802.11 specification,if a STA does not support any of capabilities defined\n\t\tin the Extended Capabilities element, then the STA is not required to\n\t\ttransmit the Extended Capabilities element.\n\t*/\n\tif (_FALSE == _rtw_memcmp(cap_content, null_content, 8))\n\t\tpframe = rtw_set_ie(out_ie + *pout_len, EID_EXTCapability, 8, cap_content , pout_len);\n}\n#endif\n\n#ifdef CONFIG_LAYER2_ROAMING\ninline void rtw_set_to_roam(_adapter *adapter, u8 to_roam)\n{\n\tif (to_roam == 0)\n\t\tadapter->mlmepriv.to_join = _FALSE;\n\tadapter->mlmepriv.to_roam = to_roam;\n}\n\ninline u8 rtw_dec_to_roam(_adapter *adapter)\n{\n\tadapter->mlmepriv.to_roam--;\n\treturn adapter->mlmepriv.to_roam;\n}\n\ninline u8 rtw_to_roam(_adapter *adapter)\n{\n\treturn adapter->mlmepriv.to_roam;\n}\n\nvoid rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network)\n{\n\t_irqL irqL;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\t_rtw_roaming(padapter, tgt_network);\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n}\nvoid _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network)\n{\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wlan_network *cur_network = &pmlmepriv->cur_network;\n\tint do_join_r;\n\n\tif (0 < rtw_to_roam(padapter)) {\n\t\tRTW_INFO(\"roaming from %s(\"MAC_FMT\"), length:%d\\n\",\n\t\t\tcur_network->network.Ssid.Ssid, MAC_ARG(cur_network->network.MacAddress),\n\t\t\t cur_network->network.Ssid.SsidLength);\n\t\t_rtw_memcpy(&pmlmepriv->assoc_ssid, &cur_network->network.Ssid, sizeof(NDIS_802_11_SSID));\n\t\tpmlmepriv->assoc_ch = 0;\n\t\tpmlmepriv->assoc_by_bssid = _FALSE;\n\n#ifdef CONFIG_WAPI_SUPPORT\n\t\trtw_wapi_return_all_sta_info(padapter);\n#endif\n\n\t\twhile (1) {\n\t\t\tdo_join_r = rtw_do_join(padapter);\n\t\t\tif (_SUCCESS == do_join_r)\n\t\t\t\tbreak;\n\t\t\telse {\n\t\t\t\tRTW_INFO(\"roaming do_join return %d\\n\", do_join_r);\n\t\t\t\trtw_dec_to_roam(padapter);\n\n\t\t\t\tif (rtw_to_roam(padapter) > 0)\n\t\t\t\t\tcontinue;\n\t\t\t\telse {\n\t\t\t\t\tRTW_INFO(\"%s(%d) -to roaming fail, indicate_disconnect\\n\", __FUNCTION__, __LINE__);\n#ifdef CONFIG_RTW_80211R\n\t\t\t\t\trtw_ft_clr_flags(padapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN);\n\t\t\t\t\trtw_ft_reset_status(padapter);\n#endif\n\t\t\t\t\trtw_indicate_disconnect(padapter, 0, _FALSE);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n}\n#endif /* CONFIG_LAYER2_ROAMING */\n\nbool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset)\n{\n\tstruct registry_priv *regsty = adapter_to_regsty(adapter);\n\tu8 allowed_bw;\n\n\tif (req_ch < 14)\n\t\tallowed_bw = REGSTY_BW_2G(regsty);\n\telse if (req_ch == 14)\n\t\tallowed_bw = CHANNEL_WIDTH_20;\n\telse\n\t\tallowed_bw = REGSTY_BW_5G(regsty);\n\n\tallowed_bw = hal_largest_bw(adapter, allowed_bw);\n\n\tif (allowed_bw == CHANNEL_WIDTH_80 && *req_bw > CHANNEL_WIDTH_80)\n\t\t*req_bw = CHANNEL_WIDTH_80;\n\telse if (allowed_bw == CHANNEL_WIDTH_40 && *req_bw > CHANNEL_WIDTH_40)\n\t\t*req_bw = CHANNEL_WIDTH_40;\n\telse if (allowed_bw == CHANNEL_WIDTH_20 && *req_bw > CHANNEL_WIDTH_20) {\n\t\t*req_bw = CHANNEL_WIDTH_20;\n\t\t*req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t} else\n\t\treturn _FALSE;\n\n\treturn _TRUE;\n}\n\nsint rtw_linked_check(_adapter *padapter)\n{\n\tif (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)\n\t\t|| MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter)\n\t) {\n\t\tif (padapter->stapriv.asoc_sta_count > 2)\n\t\t\treturn _TRUE;\n\t} else {\n\t\t/* Station mode */\n\t\tif (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE)\n\t\t\treturn _TRUE;\n\t}\n\treturn _FALSE;\n}\n/*#define DBG_ADAPTER_STATE_CHK*/\nu8 rtw_is_adapter_up(_adapter *padapter)\n{\n\tif (padapter == NULL)\n\t\treturn _FALSE;\n\n\tif (RTW_CANNOT_RUN(padapter)) {\n\t\t#ifdef DBG_ADAPTER_STATE_CHK\n\t\tRTW_INFO(FUNC_ADPT_FMT \" FALSE -bDriverStopped(%s) bSurpriseRemoved(%s)\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter)\n\t\t\t, rtw_is_drv_stopped(padapter) ? \"True\" : \"False\"\n\t\t\t, rtw_is_surprise_removed(padapter) ? \"True\" : \"False\");\n\t\t#endif\n\t\treturn _FALSE;\n\t}\n\n\tif (!rtw_is_hw_init_completed(padapter)) {\n\t\t#ifdef DBG_ADAPTER_STATE_CHK\n\t\tRTW_INFO(FUNC_ADPT_FMT \" FALSE -(hw_init_completed == _FALSE)\\n\", FUNC_ADPT_ARG(padapter));\n\t\t#endif\n\t\treturn _FALSE;\n\t}\n\n\tif (padapter->bup == _FALSE) {\n\t\t#ifdef DBG_ADAPTER_STATE_CHK\n\t\tRTW_INFO(FUNC_ADPT_FMT \" FALSE -(bup == _FALSE)\\n\", FUNC_ADPT_ARG(padapter));\n\t\t#endif\n\t\treturn _FALSE;\n\t}\n\n\treturn _TRUE;\n}\n\nbool is_miracast_enabled(_adapter *adapter)\n{\n\tbool enabled = 0;\n#ifdef CONFIG_WFD\n\tstruct wifi_display_info *wfdinfo = &adapter->wfd_info;\n\n\tenabled = (wfdinfo->stack_wfd_mode & (MIRACAST_SOURCE | MIRACAST_SINK))\n\t\t  || (wfdinfo->op_wfd_mode & (MIRACAST_SOURCE | MIRACAST_SINK));\n#endif\n\n\treturn enabled;\n}\n\nbool rtw_chk_miracast_mode(_adapter *adapter, u8 mode)\n{\n\tbool ret = 0;\n#ifdef CONFIG_WFD\n\tstruct wifi_display_info *wfdinfo = &adapter->wfd_info;\n\n\tret = (wfdinfo->stack_wfd_mode & mode) || (wfdinfo->op_wfd_mode & mode);\n#endif\n\n\treturn ret;\n}\n\nconst char *get_miracast_mode_str(int mode)\n{\n\tif (mode == MIRACAST_SOURCE)\n\t\treturn \"SOURCE\";\n\telse if (mode == MIRACAST_SINK)\n\t\treturn \"SINK\";\n\telse if (mode == (MIRACAST_SOURCE | MIRACAST_SINK))\n\t\treturn \"SOURCE&SINK\";\n\telse if (mode == MIRACAST_DISABLED)\n\t\treturn \"DISABLED\";\n\telse\n\t\treturn \"INVALID\";\n}\n\n#ifdef CONFIG_WFD\nstatic bool wfd_st_match_rule(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)\n{\n\tstruct wifi_display_info *wfdinfo = &adapter->wfd_info;\n\n\tif (ntohs(*((u16 *)local_port)) == wfdinfo->rtsp_ctrlport\n\t    || ntohs(*((u16 *)local_port)) == wfdinfo->tdls_rtsp_ctrlport\n\t    || ntohs(*((u16 *)remote_port)) == wfdinfo->peer_rtsp_ctrlport)\n\t\treturn _TRUE;\n\treturn _FALSE;\n}\n\nstatic struct st_register wfd_st_reg = {\n\t.s_proto = 0x06,\n\t.rule = wfd_st_match_rule,\n};\n#endif /* CONFIG_WFD */\n\ninline void rtw_wfd_st_switch(struct sta_info *sta, bool on)\n{\n#ifdef CONFIG_WFD\n\tif (on)\n\t\trtw_st_ctl_register(&sta->st_ctl, SESSION_TRACKER_REG_ID_WFD, &wfd_st_reg);\n\telse\n\t\trtw_st_ctl_unregister(&sta->st_ctl, SESSION_TRACKER_REG_ID_WFD);\n#endif\n}\n\nvoid dump_arp_pkt(void *sel, u8 *da, u8 *sa, u8 *arp, bool tx)\n{\n\tRTW_PRINT_SEL(sel, \"%s ARP da=\"MAC_FMT\", sa=\"MAC_FMT\"\\n\"\n\t\t, tx ? \"send\" : \"recv\", MAC_ARG(da), MAC_ARG(sa));\n\tRTW_PRINT_SEL(sel, \"htype=%u, ptype=0x%04x, hlen=%u, plen=%u, oper=%u\\n\"\n\t\t, GET_ARP_HTYPE(arp), GET_ARP_PTYPE(arp), GET_ARP_HLEN(arp)\n\t\t, GET_ARP_PLEN(arp), GET_ARP_OPER(arp));\n\tRTW_PRINT_SEL(sel, \"sha=\"MAC_FMT\", spa=\"IP_FMT\"\\n\"\n\t\t, MAC_ARG(ARP_SENDER_MAC_ADDR(arp)), IP_ARG(ARP_SENDER_IP_ADDR(arp)));\n\tRTW_PRINT_SEL(sel, \"tha=\"MAC_FMT\", tpa=\"IP_FMT\"\\n\"\n\t\t, MAC_ARG(ARP_TARGET_MAC_ADDR(arp)), IP_ARG(ARP_TARGET_IP_ADDR(arp)));\n}\n\n"
  },
  {
    "path": "core/rtw_mlme_ext.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2019 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_MLME_EXT_C_\n\n#include <drv_types.h>\n#ifdef CONFIG_IOCTL_CFG80211\n\t#include <rtw_wifi_regd.h>\n#endif /* CONFIG_IOCTL_CFG80211 */\n#include <hal_data.h>\n\n\nstruct mlme_handler mlme_sta_tbl[] = {\n\t{WIFI_ASSOCREQ,\t\t\"OnAssocReq\",\t&OnAssocReq},\n\t{WIFI_ASSOCRSP,\t\t\"OnAssocRsp\",\t&OnAssocRsp},\n\t{WIFI_REASSOCREQ,\t\"OnReAssocReq\",\t&OnAssocReq},\n\t{WIFI_REASSOCRSP,\t\"OnReAssocRsp\",\t&OnAssocRsp},\n\t{WIFI_PROBEREQ,\t\t\"OnProbeReq\",\t&OnProbeReq},\n\t{WIFI_PROBERSP,\t\t\"OnProbeRsp\",\t\t&OnProbeRsp},\n\n\t/*----------------------------------------------------------\n\t\t\t\t\tbelow 2 are reserved\n\t-----------------------------------------------------------*/\n\t{0,\t\t\t\t\t\"DoReserved\",\t\t&DoReserved},\n\t{0,\t\t\t\t\t\"DoReserved\",\t\t&DoReserved},\n\t{WIFI_BEACON,\t\t\"OnBeacon\",\t\t&OnBeacon},\n\t{WIFI_ATIM,\t\t\t\"OnATIM\",\t\t&OnAtim},\n\t{WIFI_DISASSOC,\t\t\"OnDisassoc\",\t\t&OnDisassoc},\n\t{WIFI_AUTH,\t\t\t\"OnAuth\",\t\t&OnAuthClient},\n\t{WIFI_DEAUTH,\t\t\"OnDeAuth\",\t\t&OnDeAuth},\n\t{WIFI_ACTION,\t\t\"OnAction\",\t\t&OnAction},\n\t{WIFI_ACTION_NOACK, \"OnActionNoAck\",\t&OnAction},\n};\n\n#ifdef _CONFIG_NATIVEAP_MLME_\nstruct mlme_handler mlme_ap_tbl[] = {\n\t{WIFI_ASSOCREQ,\t\t\"OnAssocReq\",\t&OnAssocReq},\n\t{WIFI_ASSOCRSP,\t\t\"OnAssocRsp\",\t&OnAssocRsp},\n\t{WIFI_REASSOCREQ,\t\"OnReAssocReq\",\t&OnAssocReq},\n\t{WIFI_REASSOCRSP,\t\"OnReAssocRsp\",\t&OnAssocRsp},\n\t{WIFI_PROBEREQ,\t\t\"OnProbeReq\",\t&OnProbeReq},\n\t{WIFI_PROBERSP,\t\t\"OnProbeRsp\",\t\t&OnProbeRsp},\n\n\t/*----------------------------------------------------------\n\t\t\t\t\tbelow 2 are reserved\n\t-----------------------------------------------------------*/\n\t{0,\t\t\t\t\t\"DoReserved\",\t\t&DoReserved},\n\t{0,\t\t\t\t\t\"DoReserved\",\t\t&DoReserved},\n\t{WIFI_BEACON,\t\t\"OnBeacon\",\t\t&OnBeacon},\n\t{WIFI_ATIM,\t\t\t\"OnATIM\",\t\t&OnAtim},\n\t{WIFI_DISASSOC,\t\t\"OnDisassoc\",\t\t&OnDisassoc},\n\t{WIFI_AUTH,\t\t\t\"OnAuth\",\t\t&OnAuth},\n\t{WIFI_DEAUTH,\t\t\"OnDeAuth\",\t\t&OnDeAuth},\n\t{WIFI_ACTION,\t\t\"OnAction\",\t\t&OnAction},\n\t{WIFI_ACTION_NOACK, \"OnActionNoAck\",\t&OnAction},\n};\n#endif\n\nstruct action_handler OnAction_tbl[] = {\n\t{RTW_WLAN_CATEGORY_SPECTRUM_MGMT,\t \"ACTION_SPECTRUM_MGMT\", on_action_spct},\n\t{RTW_WLAN_CATEGORY_QOS, \"ACTION_QOS\", &OnAction_qos},\n\t{RTW_WLAN_CATEGORY_DLS, \"ACTION_DLS\", &OnAction_dls},\n\t{RTW_WLAN_CATEGORY_BACK, \"ACTION_BACK\", &OnAction_back},\n\t{RTW_WLAN_CATEGORY_PUBLIC, \"ACTION_PUBLIC\", on_action_public},\n\t{RTW_WLAN_CATEGORY_RADIO_MEAS, \"ACTION_RADIO_MEAS\", &on_action_rm},\n\t{RTW_WLAN_CATEGORY_FT, \"ACTION_FT\",\t&OnAction_ft},\n\t{RTW_WLAN_CATEGORY_HT,\t\"ACTION_HT\",\t&OnAction_ht},\n#ifdef CONFIG_IEEE80211W\n\t{RTW_WLAN_CATEGORY_SA_QUERY, \"ACTION_SA_QUERY\", &OnAction_sa_query},\n#else\n\t{RTW_WLAN_CATEGORY_SA_QUERY, \"ACTION_SA_QUERY\", &DoReserved},\n#endif /* CONFIG_IEEE80211W */\n#ifdef CONFIG_RTW_WNM\n\t{RTW_WLAN_CATEGORY_WNM, \"ACTION_WNM\", &on_action_wnm},\n#endif\n\t{RTW_WLAN_CATEGORY_UNPROTECTED_WNM, \"ACTION_UNPROTECTED_WNM\", &DoReserved},\n#ifdef CONFIG_RTW_MESH\n\t{RTW_WLAN_CATEGORY_MESH, \"ACTION_MESH\", &on_action_mesh},\n\t{RTW_WLAN_CATEGORY_SELF_PROTECTED, \"ACTION_SELF_PROTECTED\", &on_action_self_protected},\n#endif\n\t{RTW_WLAN_CATEGORY_WMM, \"ACTION_WMM\", &OnAction_wmm},\n\t{RTW_WLAN_CATEGORY_VHT, \"ACTION_VHT\", &OnAction_vht},\n\t{RTW_WLAN_CATEGORY_P2P, \"ACTION_P2P\", &OnAction_p2p},\n};\n\n\nu8\tnull_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};\n\n/**************************************************\nOUI definitions for the vendor specific IE\n***************************************************/\nunsigned char\tRTW_WPA_OUI[] = {0x00, 0x50, 0xf2, 0x01};\nunsigned char WMM_OUI[] = {0x00, 0x50, 0xf2, 0x02};\nunsigned char\tWPS_OUI[] = {0x00, 0x50, 0xf2, 0x04};\nunsigned char\tP2P_OUI[] = {0x50, 0x6F, 0x9A, 0x09};\nunsigned char\tWFD_OUI[] = {0x50, 0x6F, 0x9A, 0x0A};\n\nunsigned char\tWMM_INFO_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01};\nunsigned char\tWMM_PARA_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01};\n\nunsigned char WPA_TKIP_CIPHER[4] = {0x00, 0x50, 0xf2, 0x02};\nunsigned char RSN_TKIP_CIPHER[4] = {0x00, 0x0f, 0xac, 0x02};\n\nextern unsigned char REALTEK_96B_IE[];\n\nstatic void init_channel_list(_adapter *padapter, RT_CHANNEL_INFO *channel_set\n\t, struct p2p_channels *channel_list)\n{\n\tstruct registry_priv *regsty = adapter_to_regsty(padapter);\n\n\tstruct p2p_oper_class_map op_class[] = {\n\t\t{ IEEE80211G,  81,   1,  13,  1, BW20 },\n\t\t{ IEEE80211G,  82,  14,  14,  1, BW20 },\n#if 0 /* Do not enable HT40 on 2 GHz */\n\t\t{ IEEE80211G,  83,   1,   9,  1, BW40PLUS },\n\t\t{ IEEE80211G,  84,   5,  13,  1, BW40MINUS },\n#endif\n\t\t{ IEEE80211A, 115,  36,  48,  4, BW20 },\n\t\t{ IEEE80211A, 116,  36,  44,  8, BW40PLUS },\n\t\t{ IEEE80211A, 117,  40,  48,  8, BW40MINUS },\n\t\t{ IEEE80211A, 124, 149, 161,  4, BW20 },\n\t\t{ IEEE80211A, 125, 149, 169,  4, BW20 },\n\t\t{ IEEE80211A, 126, 149, 157,  8, BW40PLUS },\n\t\t{ IEEE80211A, 127, 153, 161,  8, BW40MINUS },\n\t\t{ -1, 0, 0, 0, 0, BW20 }\n\t};\n\n\tint cla, op;\n\n\tcla = 0;\n\n\tfor (op = 0; op_class[op].op_class; op++) {\n\t\tu8 ch;\n\t\tstruct p2p_oper_class_map *o = &op_class[op];\n\t\tstruct p2p_reg_class *reg = NULL;\n\n\t\tfor (ch = o->min_chan; ch <= o->max_chan; ch += o->inc) {\n\t\t\tif (rtw_chset_search_ch(channel_set, ch) == -1)\n\t\t\t\tcontinue;\n#if defined(CONFIG_80211N_HT) || defined(CONFIG_80211AC_VHT)\n\t\t\tif ((padapter->registrypriv.ht_enable == 0) && (o->inc == 8))\n\t\t\t\tcontinue;\n\n\t\t\tif ((REGSTY_IS_BW_5G_SUPPORT(regsty, CHANNEL_WIDTH_40)) &&\n\t\t\t    ((o->bw == BW40MINUS) || (o->bw == BW40PLUS)))\n\t\t\t\tcontinue;\n#endif\n\t\t\tif (reg == NULL) {\n\t\t\t\treg = &channel_list->reg_class[cla];\n\t\t\t\tcla++;\n\t\t\t\treg->reg_class = o->op_class;\n\t\t\t\treg->channels = 0;\n\t\t\t}\n\t\t\treg->channel[reg->channels] = ch;\n\t\t\treg->channels++;\n\t\t}\n\t}\n\tchannel_list->reg_classes = cla;\n\n}\n\n#if CONFIG_TXPWR_LIMIT\nvoid rtw_txpwr_init_regd(struct rf_ctl_t *rfctl)\n{\n\tu8 regd;\n\tstruct regd_exc_ent *exc;\n\tstruct txpwr_lmt_ent *ent;\n\t_irqL irqL;\n\n\t_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\n\trfctl->regd_name = NULL;\n\n\tif (rfctl->txpwr_regd_num == 0) {\n\t\tRTW_PRINT(\"there is no any txpwr_regd\\n\");\n\t\tgoto release_lock;\n\t}\n\n\t/* search from exception mapping */\n\texc = _rtw_regd_exc_search(rfctl\n\t\t, rfctl->country_ent ? rfctl->country_ent->alpha2 : NULL\n\t\t, rfctl->ChannelPlan);\n\tif (exc) {\n\t\tu8 has_country = (exc->country[0] == '\\0' && exc->country[1] == '\\0') ? 0 : 1;\n\n\t\tif (strcmp(exc->regd_name, regd_str(TXPWR_LMT_NONE)) == 0)\n\t\t\trfctl->regd_name = regd_str(TXPWR_LMT_NONE);\n\t\telse if (strcmp(exc->regd_name, regd_str(TXPWR_LMT_WW)) == 0)\n\t\t\trfctl->regd_name = regd_str(TXPWR_LMT_WW);\n\t\telse {\n\t\t\tent = _rtw_txpwr_lmt_get_by_name(rfctl, exc->regd_name);\n\t\t\tif (ent)\n\t\t\t\trfctl->regd_name = ent->regd_name;\n\t\t}\n\n\t\tRTW_PRINT(\"exception mapping country:%c%c domain:0x%02x to%s regd_name:%s\\n\"\n\t\t\t, has_country ? exc->country[0] : '0'\n\t\t\t, has_country ? exc->country[1] : '0'\n\t\t\t, exc->domain\n\t\t\t, rfctl->regd_name ? \"\" : \" unknown\"\n\t\t\t, exc->regd_name\n\t\t);\n\t\tif (rfctl->regd_name)\n\t\t\tgoto release_lock;\n\t}\n\n\t/* follow default channel plan mapping */\n\tregd = rtw_chplan_get_default_regd(rfctl->ChannelPlan);\n\tif (regd == TXPWR_LMT_NONE)\n\t\trfctl->regd_name = regd_str(TXPWR_LMT_NONE);\n\telse if (regd == TXPWR_LMT_WW)\n\t\trfctl->regd_name = regd_str(TXPWR_LMT_WW);\n\telse {\n\t\tent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_str(regd));\n\t\tif (ent)\n\t\t\trfctl->regd_name = ent->regd_name;\n\t}\n\n\tRTW_PRINT(\"default mapping domain:0x%02x to%s regd_name:%s\\n\"\n\t\t, rfctl->ChannelPlan\n\t\t, rfctl->regd_name ? \"\" : \" unknown\"\n\t\t, regd_str(regd)\n\t);\n\tif (rfctl->regd_name)\n\t\tgoto release_lock;\n\n\tswitch (regd) {\n\t/*\n\t* To support older chips without new predefined regd:\n\t* - use FCC if IC or CHILE or MEXICO not found\n\t* - use ETSI if KCC or ACMA not found\n\t*/\n\tcase TXPWR_LMT_IC:\n\tcase TXPWR_LMT_KCC:\n\tcase TXPWR_LMT_ACMA:\n\tcase TXPWR_LMT_CHILE:\n\tcase TXPWR_LMT_MEXICO:\n\t\tif (regd == TXPWR_LMT_IC || regd == TXPWR_LMT_CHILE || regd == TXPWR_LMT_MEXICO)\n\t\t\tregd = TXPWR_LMT_FCC;\n\t\telse if (regd == TXPWR_LMT_KCC || regd == TXPWR_LMT_ACMA)\n\t\t\tregd = TXPWR_LMT_ETSI;\n\t\tent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_str(regd));\n\t\tif (ent)\n\t\t\trfctl->regd_name = ent->regd_name;\n\t\tRTW_PRINT(\"alternate regd_name:%s %s\\n\"\n\t\t\t, regd_str(regd)\n\t\t\t, rfctl->regd_name ? \"is used\" : \"not found\"\n\t\t);\n\t\tif (rfctl->regd_name)\n\t\t\tbreak;\n\tdefault:\n\t\trfctl->regd_name = regd_str(TXPWR_LMT_WW);\n\t\tRTW_PRINT(\"assign %s for default case\\n\", regd_str(TXPWR_LMT_WW));\n\t\tbreak;\n\t};\n\nrelease_lock:\n\t_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n}\n#endif /* CONFIG_TXPWR_LIMIT */\n\nvoid rtw_rfctl_init(_adapter *adapter)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\n\trfctl->max_chan_nums = init_channel_set(adapter, rfctl->ChannelPlan, rfctl->channel_set);\n\tinit_channel_list(adapter, rfctl->channel_set, &rfctl->channel_list);\n\n\t_rtw_mutex_init(&rfctl->offch_mutex);\n\n#if CONFIG_TXPWR_LIMIT\n\t_rtw_mutex_init(&rfctl->txpwr_lmt_mutex);\n\t_rtw_init_listhead(&rfctl->reg_exc_list);\n\t_rtw_init_listhead(&rfctl->txpwr_lmt_list);\n#endif\n\n\trfctl->ch_sel_same_band_prefer = 1;\n\n#ifdef CONFIG_DFS_MASTER\n\trfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;\n\trtw_init_timer(&(rfctl->radar_detect_timer), adapter, rtw_dfs_rd_timer_hdl, rfctl);\n#endif\n#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT\n\trfctl->dfs_slave_with_rd = 1;\n#endif\n}\n\nvoid rtw_rfctl_deinit(_adapter *adapter)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\n\t_rtw_mutex_free(&rfctl->offch_mutex);\n\n#if CONFIG_TXPWR_LIMIT\n\trtw_regd_exc_list_free(rfctl);\n\trtw_txpwr_lmt_list_free(rfctl);\n\t_rtw_mutex_free(&rfctl->txpwr_lmt_mutex);\n#endif\n}\n\n#ifdef CONFIG_DFS_MASTER\n/*\n* called in rtw_dfs_rd_enable()\n* assume the request channel coverage is DFS range\n* base on the current status and the request channel coverage to check if need to reset complete CAC time\n*/\nbool rtw_is_cac_reset_needed(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset)\n{\n\tbool needed = _FALSE;\n\tu32 cur_hi, cur_lo, hi, lo;\n\n\tif (rfctl->radar_detected == 1) {\n\t\tneeded = _TRUE;\n\t\tgoto exit;\n\t}\n\n\tif (rfctl->radar_detect_ch == 0) {\n\t\tneeded = _TRUE;\n\t\tgoto exit;\n\t}\n\n\tif (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) {\n\t\tRTW_ERR(\"request detection range ch:%u, bw:%u, offset:%u\\n\", ch, bw, offset);\n\t\trtw_warn_on(1);\n\t}\n\n\tif (rtw_chbw_to_freq_range(rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset, &cur_hi, &cur_lo) == _FALSE) {\n\t\tRTW_ERR(\"cur detection range ch:%u, bw:%u, offset:%u\\n\", rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset);\n\t\trtw_warn_on(1);\n\t}\n\n\tif (hi <= lo || cur_hi <= cur_lo) {\n\t\tRTW_ERR(\"hi:%u, lo:%u, cur_hi:%u, cur_lo:%u\\n\", hi, lo, cur_hi, cur_lo);\n\t\trtw_warn_on(1);\n\t}\n\n\tif (rtw_is_range_a_in_b(hi, lo, cur_hi, cur_lo)) {\n\t\t/* request is in current detect range */\n\t\tgoto exit;\n\t}\n\n\t/* check if request channel coverage has new range and the new range is in DFS range */\n\tif (!rtw_is_range_overlap(hi, lo, cur_hi, cur_lo)) {\n\t\t/* request has no overlap with current */\n\t\tneeded = _TRUE;\n\t} else if (rtw_is_range_a_in_b(cur_hi, cur_lo, hi, lo)) {\n\t\t/* request is supper set of current */\n\t\tif ((hi != cur_hi && rtw_is_dfs_range(hi, cur_hi)) || (lo != cur_lo && rtw_is_dfs_range(cur_lo, lo)))\n\t\t\tneeded = _TRUE;\n\t} else {\n\t\t/* request is not supper set of current, but has overlap */\n\t\tif ((lo < cur_lo && rtw_is_dfs_range(cur_lo, lo)) || (hi > cur_hi && rtw_is_dfs_range(hi, cur_hi)))\n\t\t\tneeded = _TRUE;\n\t}\n\nexit:\n\treturn needed;\n}\n\nbool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset)\n{\n\tbool ret = _FALSE;\n\tu32 hi = 0, lo = 0;\n\tu32 r_hi = 0, r_lo = 0;\n\tint i;\n\n\tif (rfctl->radar_detect_by_others)\n\t\tgoto exit;\n\n\tif (rfctl->radar_detect_ch == 0)\n\t\tgoto exit;\n\n\tif (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (rtw_chbw_to_freq_range(rfctl->radar_detect_ch\n\t\t\t, rfctl->radar_detect_bw, rfctl->radar_detect_offset\n\t\t\t, &r_hi, &r_lo) == _FALSE) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (rtw_is_range_overlap(hi, lo, r_hi, r_lo))\n\t\tret = _TRUE;\n\nexit:\n\treturn ret;\n}\n\nbool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl)\n{\n\treturn _rtw_rfctl_overlap_radar_detect_ch(rfctl\n\t\t\t\t, rfctl_to_dvobj(rfctl)->oper_channel\n\t\t\t\t, rfctl_to_dvobj(rfctl)->oper_bwmode\n\t\t\t\t, rfctl_to_dvobj(rfctl)->oper_ch_offset);\n}\n\nbool rtw_rfctl_is_tx_blocked_by_ch_waiting(struct rf_ctl_t *rfctl)\n{\n\treturn rtw_rfctl_overlap_radar_detect_ch(rfctl) && IS_CH_WAITING(rfctl);\n}\n\nbool rtw_chset_is_chbw_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)\n{\n\tbool ret = _FALSE;\n\tu32 hi = 0, lo = 0;\n\tint i;\n\n\tif (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)\n\t\tgoto exit;\n\n\tfor (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {\n\t\tif (!rtw_ch2freq(ch_set[i].ChannelNum)) {\n\t\t\trtw_warn_on(1);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (!CH_IS_NON_OCP(&ch_set[i]))\n\t\t\tcontinue;\n\n\t\tif (lo <= rtw_ch2freq(ch_set[i].ChannelNum)\n\t\t\t&& rtw_ch2freq(ch_set[i].ChannelNum) <= hi\n\t\t) {\n\t\t\tret = _TRUE;\n\t\t\tbreak;\n\t\t}\n\t}\n\nexit:\n\treturn ret;\n}\n\nbool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch)\n{\n\treturn rtw_chset_is_chbw_non_ocp(ch_set, ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE);\n}\n\nu32 rtw_chset_get_ch_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)\n{\n\tint ms = 0;\n\tsystime current_time;\n\tu32 hi = 0, lo = 0;\n\tint i;\n\n\tif (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)\n\t\tgoto exit;\n\n\tcurrent_time = rtw_get_current_time();\n\n\tfor (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {\n\t\tif (!rtw_ch2freq(ch_set[i].ChannelNum)) {\n\t\t\trtw_warn_on(1);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (!CH_IS_NON_OCP(&ch_set[i]))\n\t\t\tcontinue;\n\n\t\tif (lo <= rtw_ch2freq(ch_set[i].ChannelNum)\n\t\t\t&& rtw_ch2freq(ch_set[i].ChannelNum) <= hi\n\t\t) {\n\t\t\tif (rtw_systime_to_ms(ch_set[i].non_ocp_end_time - current_time) > ms)\n\t\t\t\tms = rtw_systime_to_ms(ch_set[i].non_ocp_end_time - current_time);\n\t\t}\n\t}\n\nexit:\n\treturn ms;\n}\n\n/**\n * rtw_chset_update_non_ocp - update non_ocp_end_time according to the given @ch, @bw, @offset into @ch_set\n * @ch_set: the given channel set\n * @ch: channel number on which radar is detected\n * @bw: bandwidth on which radar is detected\n * @offset: bandwidth offset on which radar is detected\n * @ms: ms to add from now to update non_ocp_end_time, ms < 0 means use NON_OCP_TIME_MS\n */\nstatic void _rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms)\n{\n\tu32 hi = 0, lo = 0;\n\tint i;\n\n\tif (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)\n\t\tgoto exit;\n\n\tfor (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {\n\t\tif (!rtw_ch2freq(ch_set[i].ChannelNum)) {\n\t\t\trtw_warn_on(1);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (lo <= rtw_ch2freq(ch_set[i].ChannelNum)\n\t\t\t&& rtw_ch2freq(ch_set[i].ChannelNum) <= hi\n\t\t) {\n\t\t\tif (ms >= 0)\n\t\t\t\tch_set[i].non_ocp_end_time = rtw_get_current_time() + rtw_ms_to_systime(ms);\n\t\t\telse\n\t\t\t\tch_set[i].non_ocp_end_time = rtw_get_current_time() + rtw_ms_to_systime(NON_OCP_TIME_MS);\n\t\t}\n\t}\n\nexit:\n\treturn;\n}\n\ninline void rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)\n{\n\t_rtw_chset_update_non_ocp(ch_set, ch, bw, offset, -1);\n}\n\ninline void rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms)\n{\n\t_rtw_chset_update_non_ocp(ch_set, ch, bw, offset, ms);\n}\n\nu32 rtw_get_ch_waiting_ms(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms)\n{\n\tstruct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);\n\tu32 non_ocp_ms;\n\tu32 cac_ms;\n\tu8 in_rd_range = 0; /* if in current radar detection range*/\n\n\tif (rtw_chset_is_chbw_non_ocp(rfctl->channel_set, ch, bw, offset))\n\t\tnon_ocp_ms = rtw_chset_get_ch_non_ocp_ms(rfctl->channel_set, ch, bw, offset);\n\telse\n\t\tnon_ocp_ms = 0;\n\n\tif (rfctl->radar_detect_enabled) {\n\t\tu32 cur_hi, cur_lo, hi, lo;\n\n\t\tif (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) {\n\t\t\tRTW_ERR(\"input range ch:%u, bw:%u, offset:%u\\n\", ch, bw, offset);\n\t\t\trtw_warn_on(1);\n\t\t}\n\n\t\tif (rtw_chbw_to_freq_range(rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset, &cur_hi, &cur_lo) == _FALSE) {\n\t\t\tRTW_ERR(\"cur detection range ch:%u, bw:%u, offset:%u\\n\", rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset);\n\t\t\trtw_warn_on(1);\n\t\t}\n\n\t\tif (rtw_is_range_a_in_b(hi, lo, cur_hi, cur_lo))\n\t\t\tin_rd_range = 1;\n\t}\n\n\tif (!rtw_is_dfs_chbw(ch, bw, offset))\n\t\tcac_ms = 0;\n\telse if (in_rd_range && !non_ocp_ms) {\n\t\tif (IS_CH_WAITING(rfctl))\n\t\t\tcac_ms = rtw_systime_to_ms(rfctl->cac_end_time - rtw_get_current_time());\n\t\telse\n\t\t\tcac_ms = 0;\n\t} else if (rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(dvobj)))\n\t\tcac_ms = CAC_TIME_CE_MS;\n\telse\n\t\tcac_ms = CAC_TIME_MS;\n\n\tif (r_non_ocp_ms)\n\t\t*r_non_ocp_ms = non_ocp_ms;\n\tif (r_cac_ms)\n\t\t*r_cac_ms = cac_ms;\n\n\treturn non_ocp_ms + cac_ms;\n}\n\nvoid rtw_reset_cac(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset)\n{\n\tu32 non_ocp_ms;\n\tu32 cac_ms;\n\n\trtw_get_ch_waiting_ms(rfctl\n\t\t, ch\n\t\t, bw\n\t\t, offset\n\t\t, &non_ocp_ms\n\t\t, &cac_ms\n\t);\n\n\trfctl->cac_start_time = rtw_get_current_time() + rtw_ms_to_systime(non_ocp_ms);\n\trfctl->cac_end_time = rfctl->cac_start_time + rtw_ms_to_systime(cac_ms);\n\n\t/* skip special value */\n\tif (rfctl->cac_start_time == RTW_CAC_STOPPED) {\n\t\trfctl->cac_start_time++;\n\t\trfctl->cac_end_time++;\n\t}\n\tif (rfctl->cac_end_time == RTW_CAC_STOPPED)\n\t\trfctl->cac_end_time++;\n}\n\nu32 rtw_force_stop_cac(struct rf_ctl_t *rfctl, u32 timeout_ms)\n{\n\tstruct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);\n\tsystime start;\n\tu32 pass_ms;\n\n\tstart = rtw_get_current_time();\n\n\trfctl->cac_force_stop = 1;\n\n\twhile (rtw_get_passing_time_ms(start) <= timeout_ms\n\t\t&& IS_UNDER_CAC(rfctl)\n\t) {\n\t\tif (dev_is_surprise_removed(dvobj) || dev_is_drv_stopped(dvobj))\n\t\t\tbreak;\n\t\trtw_msleep_os(20);\n\t}\n\n\tif (IS_UNDER_CAC(rfctl)) {\n\t\tif (!dev_is_surprise_removed(dvobj) && !dev_is_drv_stopped(dvobj))\n\t\t\tRTW_INFO(\"%s waiting for cac stop timeout!\\n\", __func__);\n\t}\n\n\trfctl->cac_force_stop = 0;\n\n\tpass_ms = rtw_get_passing_time_ms(start);\n\n\treturn pass_ms;\n}\n#endif /* CONFIG_DFS_MASTER */\n\n/* choose channel with shortest waiting (non ocp + cac) time */\nbool rtw_choose_shortest_waiting_ch(struct rf_ctl_t *rfctl, u8 sel_ch, u8 max_bw\n\t, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset\n\t, u8 d_flags, u8 cur_ch, u8 same_band_prefer, u8 mesh_only)\n{\n#ifndef DBG_CHOOSE_SHORTEST_WAITING_CH\n#define DBG_CHOOSE_SHORTEST_WAITING_CH 0\n#endif\n\tstruct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);\n\tstruct registry_priv *regsty = dvobj_to_regsty(dvobj);\n\tu8 ch, bw, offset;\n\tu8 ch_c = 0, bw_c = 0, offset_c = 0;\n\tint i;\n\tu32 min_waiting_ms = 0;\n\n\tif (!dec_ch || !dec_bw || !dec_offset) {\n\t\trtw_warn_on(1);\n\t\treturn _FALSE;\n\t}\n\n\t/* full search and narrow bw judegement first to avoid potetial judegement timing issue */\n\tfor (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) {\n\t\tif (!hal_is_bw_support(dvobj_get_primary_adapter(dvobj), bw))\n\t\t\tcontinue;\n\n\t\tfor (i = 0; i < rfctl->max_chan_nums; i++) {\n\t\t\tu32 non_ocp_ms = 0;\n\t\t\tu32 cac_ms = 0;\n\t\t\tu32 waiting_ms = 0;\n\n\t\t\tch = rfctl->channel_set[i].ChannelNum;\n\t\t\tif (sel_ch > 0 && ch != sel_ch)\n\t\t\t\tcontinue;\n\n\t\t\tif ((d_flags & RTW_CHF_2G) && ch <= 14)\n\t\t\t\tcontinue;\n\n\t\t\tif ((d_flags & RTW_CHF_5G) && ch > 14)\n\t\t\t\tcontinue;\n\n\t\t\tif (ch > 14) {\n\t\t\t\tif (bw > REGSTY_BW_5G(regsty))\n\t\t\t\t\tcontinue;\n\t\t\t} else {\n\t\t\t\tif (bw > REGSTY_BW_2G(regsty))\n\t\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (mesh_only && ch >= 5 && ch <= 9 && bw > CHANNEL_WIDTH_20)\n\t\t\t\tcontinue;\n\n\t\t\tif (!rtw_get_offset_by_chbw(ch, bw, &offset))\n\t\t\t\tcontinue;\n\n\t\t\tif (!rtw_chset_is_chbw_valid(rfctl->channel_set, ch, bw, offset))\n\t\t\t\tcontinue;\n\n\t\t\tif ((d_flags & RTW_CHF_NON_OCP) && rtw_chset_is_chbw_non_ocp(rfctl->channel_set, ch, bw, offset))\n\t\t\t\tcontinue;\n\n\t\t\tif ((d_flags & RTW_CHF_DFS) && rtw_is_dfs_chbw(ch, bw, offset))\n\t\t\t\tcontinue;\n\n\t\t\tif ((d_flags & RTW_CHF_LONG_CAC) && rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(dvobj)))\n\t\t\t\tcontinue;\n\n\t\t\tif ((d_flags & RTW_CHF_NON_DFS) && !rtw_is_dfs_chbw(ch, bw, offset))\n\t\t\t\tcontinue;\n\n\t\t\tif ((d_flags & RTW_CHF_NON_LONG_CAC) && !rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(dvobj)))\n\t\t\t\tcontinue;\n\n\t\t\t#ifdef CONFIG_DFS_MASTER\n\t\t\twaiting_ms = rtw_get_ch_waiting_ms(rfctl, ch, bw, offset, &non_ocp_ms, &cac_ms);\n\t\t\t#endif\n\n\t\t\tif (DBG_CHOOSE_SHORTEST_WAITING_CH)\n\t\t\t\tRTW_INFO(\"%s:%u,%u,%u %u(non_ocp:%u, cac:%u)\\n\"\n\t\t\t\t\t, __func__, ch, bw, offset, waiting_ms, non_ocp_ms, cac_ms);\n\n\t\t\tif (ch_c == 0\n\t\t\t\t/* first: smaller wating time */\n\t\t\t\t|| min_waiting_ms > waiting_ms\n\t\t\t\t/* then: wider bw */\n\t\t\t\t|| (min_waiting_ms == waiting_ms && bw > bw_c)\n\t\t\t\t/* then: same band if requested */\n\t\t\t\t|| (same_band_prefer && min_waiting_ms == waiting_ms && bw == bw_c\n\t\t\t\t\t&& !rtw_is_same_band(cur_ch, ch_c) && rtw_is_same_band(cur_ch, ch))\n\t\t\t) {\n\t\t\t\tch_c = ch;\n\t\t\t\tbw_c = bw;\n\t\t\t\toffset_c = offset;\n\t\t\t\tmin_waiting_ms = waiting_ms;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (ch_c != 0) {\n\t\tRTW_INFO(\"%s: d_flags:0x%02x cur_ch:%u sb_prefer:%u%s %u,%u,%u waiting_ms:%u\\n\"\n\t\t\t, __func__, d_flags, cur_ch, same_band_prefer\n\t\t\t, mesh_only ? \" mesh_only\" : \"\"\n\t\t\t, ch_c, bw_c, offset_c, min_waiting_ms);\n\n\t\t*dec_ch = ch_c;\n\t\t*dec_bw = bw_c;\n\t\t*dec_offset = offset_c;\n\t\treturn _TRUE;\n\t}\n\n\tif (d_flags == 0) {\n\t\tRTW_INFO(\"%s: sel_ch:%u max_bw:%u d_flags:0x%02x cur_ch:%u sb_prefer:%u%s\\n\"\n\t\t\t, __func__, sel_ch, max_bw, d_flags, cur_ch, same_band_prefer\n\t\t\t, mesh_only ? \" mesh_only\" : \"\");\n\t\trtw_warn_on(1);\n\t}\n\n\treturn _FALSE;\n}\n\nvoid dump_chset(void *sel, RT_CHANNEL_INFO *ch_set)\n{\n\tu8\ti;\n\n\tfor (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {\n\t\tRTW_PRINT_SEL(sel, \"ch:%3u, freq:%u, scan_type:%d\"\n\t\t\t, ch_set[i].ChannelNum, rtw_ch2freq(ch_set[i].ChannelNum), ch_set[i].ScanType);\n\n#ifdef CONFIG_FIND_BEST_CHANNEL\n\t\t_RTW_PRINT_SEL(sel, \", rx_count:%u\", ch_set[i].rx_count);\n#endif\n\n#ifdef CONFIG_DFS_MASTER\n\t\tif (rtw_is_dfs_ch(ch_set[i].ChannelNum)) {\n\t\t\tif (CH_IS_NON_OCP(&ch_set[i]))\n\t\t\t\t_RTW_PRINT_SEL(sel, \", non_ocp:%d\"\n\t\t\t\t\t, rtw_systime_to_ms(ch_set[i].non_ocp_end_time - rtw_get_current_time()));\n\t\t\telse\n\t\t\t\t_RTW_PRINT_SEL(sel, \", non_ocp:N/A\");\n\t\t}\n#endif\n\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\n\tRTW_PRINT_SEL(sel, \"total ch number:%d\\n\", i);\n}\n\nvoid dump_cur_chset(void *sel, struct rf_ctl_t *rfctl)\n{\n\tstruct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);\n\tstruct registry_priv *regsty = dvobj_to_regsty(dvobj);\n\tint i;\n\n\tif (rfctl->country_ent)\n\t\tdump_country_chplan(sel, rfctl->country_ent);\n\telse\n\t\tRTW_PRINT_SEL(sel, \"chplan:0x%02X\\n\", rfctl->ChannelPlan);\n\n#if CONFIG_TXPWR_LIMIT\n\tRTW_PRINT_SEL(sel, \"PLS regd:%s\\n\", rfctl->regd_name);\n#endif\n\n#ifdef CONFIG_DFS_MASTER\n\tRTW_PRINT_SEL(sel, \"dfs_domain:%u\\n\", rtw_odm_get_dfs_domain(dvobj));\n#endif\n\n\tfor (i = 0; i < MAX_CHANNEL_NUM; i++)\n\t\tif (regsty->excl_chs[i] != 0)\n\t\t\tbreak;\n\n\tif (i < MAX_CHANNEL_NUM) {\n\t\tRTW_PRINT_SEL(sel, \"excl_chs:\");\n\t\tfor (i = 0; i < MAX_CHANNEL_NUM; i++) {\n\t\t\tif (regsty->excl_chs[i] == 0)\n\t\t\t\tbreak;\n\t\t\t_RTW_PRINT_SEL(sel, \"%u \", regsty->excl_chs[i]);\n\t\t}\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\n\tdump_chset(sel, rfctl->channel_set);\n}\n\n/*\n * Search the @param ch in given @param ch_set\n * @ch_set: the given channel set\n * @ch: the given channel number\n *\n * return the index of channel_num in channel_set, -1 if not found\n */\nint rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch)\n{\n\tint i;\n\n\tif (ch == 0)\n\t\treturn -1;\n\n\tfor (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {\n\t\tif (ch == ch_set[i].ChannelNum)\n\t\t\treturn i;\n\t}\n\n\treturn -1;\n}\n\n/*\n * Check if the @param ch, bw, offset is valid for the given @param ch_set\n * @ch_set: the given channel set\n * @ch: the given channel number\n * @bw: the given bandwidth\n * @offset: the given channel offset\n *\n * return valid (1) or not (0)\n */\nu8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)\n{\n\tu8 cch;\n\tu8 *op_chs;\n\tu8 op_ch_num;\n\tu8 valid = 0;\n\tint i;\n\n\tcch = rtw_get_center_ch(ch, bw, offset);\n\n\tif (!rtw_get_op_chs_by_cch_bw(cch, bw, &op_chs, &op_ch_num))\n\t\tgoto exit;\n\n\tfor (i = 0; i < op_ch_num; i++) {\n\t\tif (0)\n\t\t\tRTW_INFO(\"%u,%u,%u - cch:%u, bw:%u, op_ch:%u\\n\", ch, bw, offset, cch, bw, *(op_chs + i));\n\t\tif (rtw_chset_search_ch(ch_set, *(op_chs + i)) == -1)\n\t\t\tbreak;\n\t}\n\n\tif (op_ch_num != 0 && i == op_ch_num)\n\t\tvalid = 1;\n\nexit:\n\treturn valid;\n}\n\n/**\n * rtw_chset_sync_chbw - obey g_ch, adjust g_bw, g_offset, bw, offset to fit in channel plan\n * @ch_set: channel plan to check\n * @req_ch: pointer of the request ch, may be modified further\n * @req_bw: pointer of the request bw, may be modified further\n * @req_offset: pointer of the request offset, may be modified further\n * @g_ch: pointer of the ongoing group ch\n * @g_bw: pointer of the ongoing group bw, may be modified further\n * @g_offset: pointer of the ongoing group offset, may be modified further\n */\nvoid rtw_chset_sync_chbw(RT_CHANNEL_INFO *ch_set, u8 *req_ch, u8 *req_bw, u8 *req_offset\n\t, u8 *g_ch, u8 *g_bw, u8 *g_offset)\n{\n\tu8 r_ch, r_bw, r_offset;\n\tu8 u_ch, u_bw, u_offset;\n\tu8 cur_bw = *req_bw;\n\n\twhile (1) {\n\t\tr_ch = *req_ch;\n\t\tr_bw = cur_bw;\n\t\tr_offset = *req_offset;\n\t\tu_ch = *g_ch;\n\t\tu_bw = *g_bw;\n\t\tu_offset = *g_offset;\n\n\t\trtw_sync_chbw(&r_ch, &r_bw, &r_offset, &u_ch, &u_bw, &u_offset);\n\n\t\tif (rtw_chset_is_chbw_valid(ch_set, r_ch, r_bw, r_offset))\n\t\t\tbreak;\n\t\tif (cur_bw == CHANNEL_WIDTH_20) {\n\t\t\trtw_warn_on(1);\n\t\t\tbreak;\n\t\t}\n\t\tcur_bw--;\n\t};\n\n\t*req_ch = r_ch;\n\t*req_bw = r_bw;\n\t*req_offset = r_offset;\n\t*g_ch = u_ch;\n\t*g_bw = u_bw;\n\t*g_offset = u_offset;\n}\n\n/*\n * Check the @param ch is fit with setband setting of @param adapter\n * @adapter: the given adapter\n * @ch: the given channel number\n *\n * return _TRUE when check valid, _FALSE not valid\n */\nbool rtw_mlme_band_check(_adapter *adapter, const u32 ch)\n{\n\tif (adapter->setband == WIFI_FREQUENCY_BAND_AUTO /* 2.4G and 5G */\n\t\t|| (adapter->setband == WIFI_FREQUENCY_BAND_2GHZ && ch < 35) /* 2.4G only */\n\t\t|| (adapter->setband == WIFI_FREQUENCY_BAND_5GHZ && ch > 35) /* 5G only */\n\t)\n\t\treturn _TRUE;\n\treturn _FALSE;\n}\ninline void RTW_SET_SCAN_BAND_SKIP(_adapter *padapter, int skip_band)\n{\n\tint bs = ATOMIC_READ(&padapter->bandskip);\n\n\tbs |= skip_band;\n\tATOMIC_SET(&padapter->bandskip, bs);\n}\n\ninline void RTW_CLR_SCAN_BAND_SKIP(_adapter *padapter, int skip_band)\n{\n\tint bs = ATOMIC_READ(&padapter->bandskip);\n\n\tbs &= ~(skip_band);\n\tATOMIC_SET(&padapter->bandskip, bs);\n}\ninline int RTW_GET_SCAN_BAND_SKIP(_adapter *padapter)\n{\n\treturn ATOMIC_READ(&padapter->bandskip);\n}\n\n#define RTW_IS_SCAN_BAND_SKIP(padapter, skip_band) (ATOMIC_READ(&padapter->bandskip) & (skip_band))\n\nbool rtw_mlme_ignore_chan(_adapter *adapter, const u32 ch)\n{\n\tif (RTW_IS_SCAN_BAND_SKIP(adapter, BAND_24G) && ch < 35) /* SKIP 2.4G Band channel */\n\t\treturn _TRUE;\n\tif (RTW_IS_SCAN_BAND_SKIP(adapter, BAND_5G)  && ch > 35) /* SKIP 5G Band channel */\n\t\treturn _TRUE;\n\n\treturn _FALSE;\n}\n\n\n/****************************************************************************\n\nFollowing are the initialization functions for WiFi MLME\n\n*****************************************************************************/\n\nint init_hw_mlme_ext(_adapter *padapter)\n{\n\tstruct\tmlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\tu8 rx_bar_enble = _TRUE;\n\n\t/*\n\t * Sync driver status and hardware setting\n\t */\n\n\t/* Modify to make sure first time change channel(band) would be done properly */\n\tpHalData->current_channel = 0;\n\tpHalData->current_channel_bw = CHANNEL_WIDTH_MAX;\n\tpHalData->current_band_type = BAND_MAX;\n\n\t/* set_opmode_cmd(padapter, infra_client_with_mlme); */ /* removed */\n\trtw_hal_set_hwreg(padapter, HW_VAR_ENABLE_RX_BAR, &rx_bar_enble);\n\tset_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);\n\n\treturn _SUCCESS;\n}\n\nvoid init_mlme_default_rate_set(_adapter *padapter)\n{\n\tstruct\tmlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tunsigned\tchar end_set[1] = {0xff};\n\tu8\toffset_datarate = 0;\n\tu8\toffset_basicrate = 0;\n#ifdef CONFIG_80211N_HT\n\tunsigned char\tsupported_mcs_set[16] = {0xff, 0xff, 0xff, 0x00, 0x00, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};\n#endif\n\n\tif (IsSupportedTxCCK(padapter->registrypriv.wireless_mode)) {\n\n\t\tunsigned char\tdatarate_b[B_MODE_RATE_NUM] ={_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_};\n\t\t_rtw_memcpy(pmlmeext->datarate, datarate_b, B_MODE_RATE_NUM);\n\t\t_rtw_memcpy(pmlmeext->basicrate, datarate_b, B_MODE_RATE_NUM);\n\t\toffset_datarate += B_MODE_RATE_NUM;\n\t\toffset_basicrate += B_MODE_RATE_NUM;\n\t\tRTW_INFO(\"%s: support CCK\\n\", __func__);\n\t}\n\tif(IsSupportedTxOFDM(padapter->registrypriv.wireless_mode)) {\n\t\tunsigned char\tdatarate_g[G_MODE_RATE_NUM] ={_6M_RATE_, _9M_RATE_, _12M_RATE_, _18M_RATE_,_24M_RATE_, _36M_RATE_, _48M_RATE_, _54M_RATE_};\n\t\tunsigned char\tbasicrate_g[G_MODE_BASIC_RATE_NUM] = {_6M_RATE_, _12M_RATE_, _24M_RATE_};\n\t\t_rtw_memcpy(pmlmeext->datarate + offset_datarate, datarate_g, G_MODE_RATE_NUM);\n\t\t_rtw_memcpy(pmlmeext->basicrate + offset_basicrate,basicrate_g, G_MODE_BASIC_RATE_NUM);\n\t\toffset_datarate += G_MODE_RATE_NUM;\n\t\toffset_basicrate += G_MODE_BASIC_RATE_NUM;\n\t\tRTW_INFO(\"%s: support OFDM\\n\", __func__);\n\n\t}\n\t_rtw_memcpy(pmlmeext->datarate + offset_datarate, end_set, 1);\n\t_rtw_memcpy(pmlmeext->basicrate + offset_basicrate, end_set, 1);\n\n#ifdef CONFIG_80211N_HT\n\tif( padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode))\n\t\t_rtw_memcpy(pmlmeext->default_supported_mcs_set, supported_mcs_set, sizeof(pmlmeext->default_supported_mcs_set));\n#endif\n}\n\nstatic void init_mlme_ext_priv_value(_adapter *padapter)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tATOMIC_SET(&pmlmeext->event_seq, 0);\n\tpmlmeext->mgnt_seq = 0;/* reset to zero when disconnect at client mode */\n#ifdef CONFIG_IEEE80211W\n\tpmlmeext->sa_query_seq = 0;\n#endif\n\tpmlmeext->cur_channel = padapter->registrypriv.channel;\n\tpmlmeext->cur_bwmode = CHANNEL_WIDTH_20;\n\tpmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\n\tpmlmeext->retry = 0;\n\n\tpmlmeext->cur_wireless_mode = padapter->registrypriv.wireless_mode;\n\tinit_mlme_default_rate_set(padapter);\n\n\tif ((pmlmeext->cur_channel > 14) || ((padapter->registrypriv.wireless_mode & WIRELESS_11B) == 0))\n\t\tpmlmeext->tx_rate = IEEE80211_OFDM_RATE_6MB;\n\telse\n\t\tpmlmeext->tx_rate = IEEE80211_CCK_RATE_1MB;\n\n\tmlmeext_set_scan_state(pmlmeext, SCAN_DISABLE);\n\tpmlmeext->sitesurvey_res.channel_idx = 0;\n\tpmlmeext->sitesurvey_res.bss_cnt = 0;\n\tpmlmeext->sitesurvey_res.scan_ch_ms = SURVEY_TO;\n\tpmlmeext->sitesurvey_res.rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID;\n\tpmlmeext->sitesurvey_res.rx_ampdu_size = RX_AMPDU_SIZE_INVALID;\n#ifdef CONFIG_SCAN_BACKOP\n\tmlmeext_assign_scan_backop_flags_sta(pmlmeext, /*SS_BACKOP_EN|*/SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME);\n\t#ifdef CONFIG_AP_MODE\n\tmlmeext_assign_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN | SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME);\n\t#endif\n\t#ifdef CONFIG_RTW_MESH\n\tmlmeext_assign_scan_backop_flags_mesh(pmlmeext, /*SS_BACKOP_EN | */SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME);\n\t#endif\n\tpmlmeext->sitesurvey_res.scan_cnt = 0;\n\tpmlmeext->sitesurvey_res.scan_cnt_max = RTW_SCAN_NUM_OF_CH;\n\tpmlmeext->sitesurvey_res.backop_ms = RTW_BACK_OP_CH_MS;\n#endif\n#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)\n\tpmlmeext->sitesurvey_res.is_sw_antdiv_bl_scan = 0;\n#endif\n\tpmlmeext->scan_abort = _FALSE;\n\n\tpmlmeinfo->state = WIFI_FW_NULL_STATE;\n\tpmlmeinfo->reauth_count = 0;\n\tpmlmeinfo->reassoc_count = 0;\n\tpmlmeinfo->link_count = 0;\n\tpmlmeinfo->auth_seq = 0;\n\tpmlmeinfo->auth_algo = dot11AuthAlgrthm_Open;\n\tpmlmeinfo->key_index = 0;\n\tpmlmeinfo->iv = 0;\n\n\tpmlmeinfo->enc_algo = _NO_PRIVACY_;\n\tpmlmeinfo->authModeToggle = 0;\n\n\t_rtw_memset(pmlmeinfo->chg_txt, 0, 128);\n\n\tpmlmeinfo->slotTime = SHORT_SLOT_TIME;\n\tpmlmeinfo->preamble_mode = PREAMBLE_AUTO;\n\n\tpmlmeinfo->dialogToken = 0;\n\n\tpmlmeext->action_public_rxseq = 0xffff;\n\tpmlmeext->action_public_dialog_token = 0xff;\n#ifdef ROKU_PRIVATE\n/*infra mode, used to store AP's info*/\n\t_rtw_memset(pmlmeinfo->SupportedRates_infra_ap, 0, NDIS_802_11_LENGTH_RATES_EX);\n\tpmlmeinfo->ht_vht_received = 0;\n#endif /* ROKU_PRIVATE */\n}\n\nvoid init_mlme_ext_timer(_adapter *padapter)\n{\n\tstruct\tmlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\n\trtw_init_timer(&pmlmeext->survey_timer, padapter, survey_timer_hdl, padapter);\n\trtw_init_timer(&pmlmeext->link_timer, padapter, link_timer_hdl, padapter);\n#ifdef CONFIG_RTW_80211R\n\trtw_init_timer(&pmlmeext->ft_link_timer, padapter, rtw_ft_link_timer_hdl, padapter);\n\trtw_init_timer(&pmlmeext->ft_roam_timer, padapter, rtw_ft_roam_timer_hdl, padapter);\n#endif\n\n#ifdef CONFIG_RTW_REPEATER_SON\n\trtw_init_timer(&pmlmeext->rson_scan_timer, padapter, rson_timer_hdl, padapter);\n#endif\n}\n\nint\tinit_mlme_ext_priv(_adapter *padapter)\n{\n\tint\tres = _SUCCESS;\n\tstruct registry_priv *pregistrypriv = &padapter->registrypriv;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\t/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */\n\t/* _rtw_memset((u8 *)pmlmeext, 0, sizeof(struct mlme_ext_priv)); */\n\n\tpmlmeext->padapter = padapter;\n\n\t/* fill_fwpriv(padapter, &(pmlmeext->fwpriv)); */\n\n\tinit_mlme_ext_priv_value(padapter);\n\tpmlmeinfo->bAcceptAddbaReq = pregistrypriv->bAcceptAddbaReq;\n\n\tinit_mlme_ext_timer(padapter);\n\n#ifdef CONFIG_AP_MODE\n\tinit_mlme_ap_info(padapter);\n#endif\n\n\tpmlmeext->last_scan_time = 0;\n\tpmlmeext->mlmeext_init = _TRUE;\n\n\n#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK\n\tpmlmeext->active_keep_alive_check = _TRUE;\n#else\n\tpmlmeext->active_keep_alive_check = _FALSE;\n#endif\n\n#ifdef DBG_FIXED_CHAN\n\tpmlmeext->fixed_chan = 0xFF;\n#endif\n\n\tpmlmeext->tsf_update_pause_factor = pregistrypriv->tsf_update_pause_factor;\n\tpmlmeext->tsf_update_restore_factor = pregistrypriv->tsf_update_restore_factor;\n\n#ifdef CONFIG_SUPPORT_STATIC_SMPS\n\tpmlmeext->ssmps_en = _FALSE;\n\tpmlmeext->ssmps_tx_tp_th = SSMPS_TX_TP_TH;/*Mbps*/\n\tpmlmeext->ssmps_rx_tp_th = SSMPS_RX_TP_TH;/*Mbps*/\n\t#ifdef DBG_STATIC_SMPS\n\tpmlmeext->ssmps_test = _FALSE;\n\t#endif\n#endif\n\n#ifdef CONFIG_CTRL_TXSS_BY_TP\n\tpmlmeext->txss_ctrl_en = _TRUE;\n\tpmlmeext->txss_tp_th = TXSS_TP_TH;\n\tpmlmeext->txss_tp_chk_cnt = TXSS_TP_CHK_CNT;\n#endif\n\n\treturn res;\n\n}\n\nvoid free_mlme_ext_priv(struct mlme_ext_priv *pmlmeext)\n{\n\t_adapter *padapter = pmlmeext->padapter;\n\n\tif (!padapter)\n\t\treturn;\n\n\tif (rtw_is_drv_stopped(padapter)) {\n\t\t_cancel_timer_ex(&pmlmeext->survey_timer);\n\t\t_cancel_timer_ex(&pmlmeext->link_timer);\n\t}\n}\n\n#ifdef CONFIG_PATCH_JOIN_WRONG_CHANNEL\nstatic u8 cmp_pkt_chnl_diff(_adapter *padapter, u8 *pframe, uint packet_len)\n{\n\t/* if the channel is same, return 0. else return channel differential\t */\n\tuint len;\n\tu8 channel;\n\tu8 *p;\n\n\tp = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_, _DSSET_IE_, &len, packet_len - _BEACON_IE_OFFSET_);\n\tif (p) {\n\t\tchannel = *(p + 2);\n\t\tif (padapter->mlmeextpriv.cur_channel >= channel)\n\t\t\treturn padapter->mlmeextpriv.cur_channel - channel;\n\t\telse\n\t\t\treturn channel - padapter->mlmeextpriv.cur_channel;\n\t} else\n\t\treturn 0;\n}\n#endif /* CONFIG_PATCH_JOIN_WRONG_CHANNEL */\n\nstatic void _mgt_dispatcher(_adapter *padapter, struct mlme_handler *ptable, union recv_frame *precv_frame)\n{\n\tu8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\n\tif (ptable->func) {\n\t\t/* receive the frames that ra(a1) is my address or ra(a1) is bc address. */\n\t\tif (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN) &&\n\t\t    !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN))\n#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI\n\t\t{\n\t\t\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n\n\t\t\tif (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) != _TRUE)\n\t\t\t\treturn;\n\n\t\t    if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE)\n\t\t\t\treturn;\n\n\t\t    if ( pwdev_priv->pno_mac_addr[0] == 0xFF)\n\t\t\t\treturn;\n\n\t\t    if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_pno_mac_addr(padapter), ETH_ALEN))\n\t\t\t\treturn;\n\t\t}\n#else\n\t\t\treturn;\n#endif\n\n\t\tptable->func(padapter, precv_frame);\n\t}\n\n}\n\nvoid mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tint index;\n\tstruct mlme_handler *ptable;\n\tu8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tstruct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(pframe));\n\tstruct recv_priv  *precvpriv = &padapter->recvpriv;\n\n\n#if 0\n\t{\n\t\tu8 *pbuf;\n\t\tpbuf = GetAddr1Ptr(pframe);\n\t\tRTW_INFO(\"A1-%x:%x:%x:%x:%x:%x\\n\", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5));\n\t\tpbuf = get_addr2_ptr(pframe);\n\t\tRTW_INFO(\"A2-%x:%x:%x:%x:%x:%x\\n\", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5));\n\t\tpbuf = GetAddr3Ptr(pframe);\n\t\tRTW_INFO(\"A3-%x:%x:%x:%x:%x:%x\\n\", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5));\n\t}\n#endif\n\n\tif (GetFrameType(pframe) != WIFI_MGT_TYPE) {\n\t\treturn;\n\t}\n\n\t/* receive the frames that ra(a1) is my address or ra(a1) is bc address. */\n\tif (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN) &&\n\t    !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN))\n#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI\n\t\t{\n\t\t\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n\n\t\t\tif (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) != _TRUE)\n\t\t\t\treturn;\n\n\t\t\tif (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE)\n\t\t\t\treturn;\n\n\t\t\tif ( pwdev_priv->pno_mac_addr[0] == 0xFF)\n\t\t\t\treturn;\n\n\t\t\tif (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_pno_mac_addr(padapter), ETH_ALEN))\n\t\t\t\treturn;\n\t\t}\n#else\n\t\treturn;\n#endif\n\n\tptable = mlme_sta_tbl;\n\n\tindex = get_frame_sub_type(pframe) >> 4;\n\n#ifdef CONFIG_TDLS\n\tif ((index << 4) == WIFI_ACTION) {\n\t\t/* category==public (4), action==TDLS_DISCOVERY_RESPONSE */\n\t\tif (*(pframe + 24) == RTW_WLAN_CATEGORY_PUBLIC && *(pframe + 25) == TDLS_DISCOVERY_RESPONSE) {\n\t\t\tRTW_INFO(\"[TDLS] Recv %s from \"MAC_FMT\"\\n\", rtw_tdls_action_txt(TDLS_DISCOVERY_RESPONSE), MAC_ARG(get_addr2_ptr(pframe)));\n\t\t\tOn_TDLS_Dis_Rsp(padapter, precv_frame);\n\t\t}\n\t}\n#endif /* CONFIG_TDLS */\n\n\tif (index >= (sizeof(mlme_sta_tbl) / sizeof(struct mlme_handler))) {\n\t\treturn;\n\t}\n\tptable += index;\n\n#if 1\n\tif (psta != NULL) {\n\t\tif (GetRetry(pframe)) {\n\t\t\tif (precv_frame->u.hdr.attrib.seq_num == psta->RxMgmtFrameSeqNum) {\n\t\t\t\t/* drop the duplicate management frame */\n\t\t\t\tprecvpriv->dbg_rx_dup_mgt_frame_drop_count++;\n\t\t\t\tRTW_INFO(\"Drop duplicate management frame with seq_num = %d.\\n\", precv_frame->u.hdr.attrib.seq_num);\n\t\t\t\treturn;\n\t\t\t}\n\t\t}\n\t\tpsta->RxMgmtFrameSeqNum = precv_frame->u.hdr.attrib.seq_num;\n\t}\n#else\n\n\tif (GetRetry(pframe)) {\n\t\t/* return; */\n\t}\n#endif\n\n#ifdef CONFIG_AP_MODE\n\tswitch (get_frame_sub_type(pframe)) {\n\tcase WIFI_AUTH:\n\t\tif (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter))\n\t\t\tptable->func = &OnAuth;\n\t\telse\n\t\t\tptable->func = &OnAuthClient;\n\t/* pass through */\n\tcase WIFI_ASSOCREQ:\n\tcase WIFI_REASSOCREQ:\n\t\t_mgt_dispatcher(padapter, ptable, precv_frame);\n\t\t#ifdef CONFIG_HOSTAPD_MLME\n\t\tif (MLME_IS_AP(padapter))\n\t\t\trtw_hostapd_mlme_rx(padapter, precv_frame);\n\t\t#endif\n\t\tbreak;\n\tcase WIFI_PROBEREQ:\n\t\t_mgt_dispatcher(padapter, ptable, precv_frame);\n\t\t#ifdef CONFIG_HOSTAPD_MLME\n\t\tif (MLME_IS_AP(padapter))\n\t\t\trtw_hostapd_mlme_rx(padapter, precv_frame);\n\t\t#endif\n\t\tbreak;\n\tcase WIFI_BEACON:\n\t\t_mgt_dispatcher(padapter, ptable, precv_frame);\n\t\tbreak;\n\tcase WIFI_ACTION:\n\t\t_mgt_dispatcher(padapter, ptable, precv_frame);\n\t\tbreak;\n\tdefault:\n\t\t_mgt_dispatcher(padapter, ptable, precv_frame);\n\t\t#ifdef CONFIG_HOSTAPD_MLME\n\t\tif (MLME_IS_AP(padapter))\n\t\t\trtw_hostapd_mlme_rx(padapter, precv_frame);\n\t\t#endif\n\t\tbreak;\n\t}\n#else\n\n\t_mgt_dispatcher(padapter, ptable, precv_frame);\n\n#endif\n\n}\n\n#ifdef CONFIG_P2P\nu32 p2p_listen_state_process(_adapter *padapter, unsigned char *da)\n{\n\tbool response = _TRUE;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (padapter->wdinfo.driver_interface == DRIVER_CFG80211) {\n\t\tif (rtw_cfg80211_get_is_roch(padapter) == _FALSE\n\t\t\t|| rtw_get_oper_ch(padapter) != padapter->wdinfo.listen_channel\n\t\t\t|| adapter_wdev_data(padapter)->p2p_enabled == _FALSE\n\t\t\t|| padapter->mlmepriv.wps_probe_resp_ie == NULL\n\t\t\t|| padapter->mlmepriv.p2p_probe_resp_ie == NULL\n\t\t) {\n#ifdef CONFIG_DEBUG_CFG80211\n\t\t\tRTW_INFO(ADPT_FMT\" DON'T issue_probersp_p2p: p2p_enabled:%d, wps_probe_resp_ie:%p, p2p_probe_resp_ie:%p\\n\"\n\t\t\t\t, ADPT_ARG(padapter)\n\t\t\t\t, adapter_wdev_data(padapter)->p2p_enabled\n\t\t\t\t, padapter->mlmepriv.wps_probe_resp_ie\n\t\t\t\t, padapter->mlmepriv.p2p_probe_resp_ie);\n\t\t\tRTW_INFO(ADPT_FMT\" DON'T issue_probersp_p2p: is_ro_ch:%d, op_ch:%d, p2p_listen_channel:%d\\n\"\n\t\t\t\t, ADPT_ARG(padapter)\n\t\t\t\t, rtw_cfg80211_get_is_roch(padapter)\n\t\t\t\t, rtw_get_oper_ch(padapter)\n\t\t\t\t, padapter->wdinfo.listen_channel);\n#endif\n\t\t\tresponse = _FALSE;\n\t\t}\n\t} else\n#endif /* CONFIG_IOCTL_CFG80211 */\n\t\tif (padapter->wdinfo.driver_interface == DRIVER_WEXT) {\n\t\t\t/*\tdo nothing if the device name is empty */\n\t\t\tif (!padapter->wdinfo.device_name_len)\n\t\t\t\tresponse\t= _FALSE;\n\t\t}\n\n\tif (response == _TRUE)\n\t\tissue_probersp_p2p(padapter, da);\n\n\treturn _SUCCESS;\n}\n#endif /* CONFIG_P2P */\n\n\n/****************************************************************************\n\nFollowing are the callback functions for each subtype of the management frames\n\n*****************************************************************************/\n\nunsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tunsigned int\tielen;\n\tunsigned char\t*p;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t*cur = &(pmlmeinfo->network);\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tuint len = precv_frame->u.hdr.len;\n\tu8 is_valid_p2p_probereq = _FALSE;\n\n#ifdef CONFIG_ATMEL_RC_PATCH\n\tu8 *target_ie = NULL, *wps_ie = NULL;\n\tu8 *start;\n\tuint search_len = 0, wps_ielen = 0, target_ielen = 0;\n\tstruct sta_info\t*psta;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n#endif\n\n\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\tstruct rx_pkt_attrib\t*pattrib = &precv_frame->u.hdr.attrib;\n\tu8 wifi_test_chk_rate = 1;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif ((pwdinfo->driver_interface == DRIVER_CFG80211)\n\t    && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)\n\t    && (GET_CFG80211_REPORT_MGMT(adapter_wdev_data(padapter), IEEE80211_STYPE_PROBE_REQ) == _TRUE)\n\t) {\n\t\trtw_cfg80211_rx_probe_request(padapter, precv_frame);\n\t\treturn _SUCCESS;\n\t}\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) &&\n\t    !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) &&\n\t    !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) &&\n\t    !rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) &&\n\t    !rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN)\n\t   ) {\n\t\t/*\tCommented by Albert 2011/03/17 */\n\t\t/*\tmcs_rate = 0->CCK 1M rate */\n\t\t/*\tmcs_rate = 1->CCK 2M rate */\n\t\t/*\tmcs_rate = 2->CCK 5.5M rate */\n\t\t/*\tmcs_rate = 3->CCK 11M rate */\n\t\t/*\tIn the P2P mode, the driver should not support the CCK rate */\n\n\t\t/*\tCommented by Kurt 2012/10/16 */\n\t\t/*\tIOT issue: Google Nexus7 use 1M rate to send p2p_probe_req after GO nego completed and Nexus7 is client */\n\t\tif (padapter->registrypriv.wifi_spec == 1) {\n\t\t\tif (pattrib->data_rate <= DESC_RATE11M)\n\t\t\t\twifi_test_chk_rate = 0;\n\t\t}\n\n\t\tif (wifi_test_chk_rate == 1) {\n\t\t\tis_valid_p2p_probereq = process_probe_req_p2p_ie(pwdinfo, pframe, len);\n\t\t\tif (is_valid_p2p_probereq == _TRUE) {\n\t\t\t\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) {\n\t\t\t\t\t/* FIXME */\n\t\t\t\t\tif (padapter->wdinfo.driver_interface == DRIVER_WEXT)\n\t\t\t\t\t\treport_survey_event(padapter, precv_frame);\n\n\t\t\t\t\tp2p_listen_state_process(padapter,  get_sa(pframe));\n\n\t\t\t\t\treturn _SUCCESS;\n\t\t\t\t}\n\n\t\t\t\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))\n\t\t\t\t\tgoto _continue;\n\t\t\t}\n\t\t}\n\t}\n\n_continue:\n#endif /* CONFIG_P2P */\n\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE))\n\t\treturn _SUCCESS;\n\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE &&\n\t    check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE | WIFI_MESH_STATE) == _FALSE)\n\t\treturn _SUCCESS;\n\n\n\t/* RTW_INFO(\"+OnProbeReq\\n\"); */\n\n\n#ifdef CONFIG_ATMEL_RC_PATCH\n\twps_ie = rtw_get_wps_ie(\n\t\t\t      pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_,\n\t\t\t      len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_,\n\t\t\t      NULL, &wps_ielen);\n\tif (wps_ie)\n\t\ttarget_ie = rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_MANUFACTURER, NULL, &target_ielen);\n\tif ((target_ie && (target_ielen == 4)) && (_TRUE == _rtw_memcmp((void *)target_ie, \"Ozmo\", 4))) {\n\t\t/* psta->flag_atmel_rc = 1; */\n\t\tunsigned char *sa_addr = get_sa(pframe);\n\t\tprintk(\"%s: Find Ozmo RC -- %02x:%02x:%02x:%02x:%02x:%02x  \\n\\n\",\n\t\t       __func__, *sa_addr, *(sa_addr + 1), *(sa_addr + 2), *(sa_addr + 3), *(sa_addr + 4), *(sa_addr + 5));\n\t\t_rtw_memcpy(pstapriv->atmel_rc_pattern, get_sa(pframe), ETH_ALEN);\n\t}\n#endif\n\n\n#ifdef CONFIG_AUTO_AP_MODE\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE &&\n\t    pmlmepriv->cur_network.join_res == _TRUE) {\n\t\t_irqL\tirqL;\n\t\tstruct sta_info\t*psta;\n\t\tu8 *mac_addr, *peer_addr;\n\t\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\t\tu8 RC_OUI[4] = {0x00, 0xE0, 0x4C, 0x0A};\n\t\t/* EID[1] + EID_LEN[1] + RC_OUI[4] + MAC[6] + PairingID[2] + ChannelNum[2] */\n\n\t\tp = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, (int *)&ielen,\n\t\t\t       len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);\n\n\t\tif (!p || ielen != 14)\n\t\t\tgoto _non_rc_device;\n\n\t\tif (!_rtw_memcmp(p + 2, RC_OUI, sizeof(RC_OUI)))\n\t\t\tgoto _non_rc_device;\n\n\t\tif (!_rtw_memcmp(p + 6, get_sa(pframe), ETH_ALEN)) {\n\t\t\tRTW_INFO(\"%s, do rc pairing (\"MAC_FMT\"), but mac addr mismatch!(\"MAC_FMT\")\\n\", __FUNCTION__,\n\t\t\t\t MAC_ARG(get_sa(pframe)), MAC_ARG(p + 6));\n\n\t\t\tgoto _non_rc_device;\n\t\t}\n\n\t\tRTW_INFO(\"%s, got the pairing device(\"MAC_FMT\")\\n\", __FUNCTION__,  MAC_ARG(get_sa(pframe)));\n\n\t\t/* new a station */\n\t\tpsta = rtw_get_stainfo(pstapriv, get_sa(pframe));\n\t\tif (psta == NULL) {\n\t\t\t/* allocate a new one */\n\t\t\tRTW_INFO(\"going to alloc stainfo for rc=\"MAC_FMT\"\\n\",  MAC_ARG(get_sa(pframe)));\n\t\t\tpsta = rtw_alloc_stainfo(pstapriv, get_sa(pframe));\n\t\t\tif (psta == NULL) {\n\t\t\t\t/* TODO: */\n\t\t\t\tRTW_INFO(\" Exceed the upper limit of supported clients...\\n\");\n\t\t\t\treturn _SUCCESS;\n\t\t\t}\n\n\t\t\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\t\t\tif (rtw_is_list_empty(&psta->asoc_list)) {\n\t\t\t\tpsta->expire_to = pstapriv->expire_to;\n\t\t\t\trtw_list_insert_tail(&psta->asoc_list, &pstapriv->asoc_list);\n\t\t\t\tpstapriv->asoc_list_cnt++;\n\t\t\t}\n\t\t\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\t\t\t/* generate pairing ID */\n\t\t\tmac_addr = adapter_mac_addr(padapter);\n\t\t\tpeer_addr = psta->cmn.mac_addr;\n\t\t\tpsta->pid = (u16)(((mac_addr[4] << 8) + mac_addr[5]) + ((peer_addr[4] << 8) + peer_addr[5]));\n\n\t\t\t/* update peer stainfo */\n\t\t\tpsta->isrc = _TRUE;\n\n\t\t\t/* AID assignment */\n\t\t\tif (psta->cmn.aid > 0)\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" old AID=%d\\n\", FUNC_ADPT_ARG(padapter), psta->cmn.aid);\n\t\t\telse {\n\t\t\t\tif (!rtw_aid_alloc(padapter, psta)) {\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" no room for more AIDs\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\t\t\treturn _SUCCESS;\n\t\t\t\t}\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" allocate new AID=%d\\n\", FUNC_ADPT_ARG(padapter), psta->cmn.aid);\n\t\t\t}\n\n\t\t\tpsta->qos_option = 1;\n\t\t\tpsta->cmn.bw_mode = CHANNEL_WIDTH_20;\n\t\t\tpsta->ieee8021x_blocked = _FALSE;\n#ifdef CONFIG_80211N_HT\n\t\t\tif(padapter->registrypriv.ht_enable &&\n\t\t\t\tis_supported_ht(padapter->registrypriv.wireless_mode)) {\n\t\t\t\tpsta->htpriv.ht_option = _TRUE;\n\t\t\t\tpsta->htpriv.ampdu_enable = _FALSE;\n\t\t\t\tpsta->htpriv.sgi_20m = _FALSE;\n\t\t\t\tpsta->htpriv.sgi_40m = _FALSE;\n\t\t\t\tpsta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t\t\tpsta->htpriv.agg_enable_bitmap = 0x0;/* reset */\n\t\t\t\tpsta->htpriv.candidate_tid_bitmap = 0x0;/* reset */\n\t\t\t}\n#endif\n\n\t\t\trtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);\n\n\t\t\t_rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats));\n\n\t\t\t_enter_critical_bh(&psta->lock, &irqL);\n\t\t\tpsta->state |= _FW_LINKED;\n\t\t\t_exit_critical_bh(&psta->lock, &irqL);\n\n\t\t\treport_add_sta_event(padapter, psta->cmn.mac_addr);\n\n\t\t}\n\n\t\tissue_probersp(padapter, get_sa(pframe), _FALSE);\n\n\t\treturn _SUCCESS;\n\n\t}\n\n_non_rc_device:\n\n\treturn _SUCCESS;\n\n#endif /* CONFIG_AUTO_AP_MODE */\n\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) &&\n\t    rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_LINKING | _FW_UNDER_SURVEY)) {\n\t\t/* don't process probe req */\n\t\treturn _SUCCESS;\n\t}\n#endif\n\n\tp = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ielen,\n\t\t       len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);\n\n\n\t/* check (wildcard) SSID */\n\tif (p != NULL) {\n\t\tif (is_valid_p2p_probereq == _TRUE)\n\t\t\tgoto _issue_probersp;\n\n\t\tif ((ielen != 0 && _FALSE == _rtw_memcmp((void *)(p + 2), (void *)cur->Ssid.Ssid, cur->Ssid.SsidLength))\n\t\t\t|| (ielen == 0 && pmlmeinfo->hidden_ssid_mode))\n\t\t\tgoto exit;\n\n\t\t#ifdef CONFIG_RTW_MESH\n\t\tif (MLME_IS_MESH(padapter)) {\n\t\t\tp = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, WLAN_EID_MESH_ID, (int *)&ielen,\n\t\t\t\t\tlen - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);\n\n\t\t\tif (!p)\n\t\t\t\tgoto exit;\n\t\t\tif (ielen != 0 && _rtw_memcmp((void *)(p + 2), (void *)cur->mesh_id.Ssid, cur->mesh_id.SsidLength) == _FALSE)\n\t\t\t\tgoto exit;\n\t\t}\n\t\t#endif\n\n_issue_probersp:\n\t\tif (((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE &&\n\t\t      pmlmepriv->cur_network.join_res == _TRUE)) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) {\n\t\t\t/* RTW_INFO(\"+issue_probersp during ap mode\\n\"); */\n\t\t\tissue_probersp(padapter, get_sa(pframe), is_valid_p2p_probereq);\n\t\t}\n\n\t}\n\nexit:\n\treturn _SUCCESS;\n\n}\n\nunsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tu8\t*pframe = precv_frame->u.hdr.rx_data;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info\t*pwdinfo = &padapter->wdinfo;\n#endif\n\n\n#ifdef CONFIG_P2P\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) {\n\t\tif (_TRUE == pwdinfo->tx_prov_disc_info.benable) {\n\t\t\tif (_rtw_memcmp(pwdinfo->tx_prov_disc_info.peerIFAddr, get_addr2_ptr(pframe), ETH_ALEN)) {\n\t\t\t\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {\n\t\t\t\t\tpwdinfo->tx_prov_disc_info.benable = _FALSE;\n\t\t\t\t\tissue_p2p_provision_request(padapter,\n\t\t\t\t\t\tpwdinfo->tx_prov_disc_info.ssid.Ssid,\n\t\t\t\t\t\tpwdinfo->tx_prov_disc_info.ssid.SsidLength,\n\t\t\t\t\t\tpwdinfo->tx_prov_disc_info.peerDevAddr);\n\t\t\t\t} else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\t\t\t\tpwdinfo->tx_prov_disc_info.benable = _FALSE;\n\t\t\t\t\tissue_p2p_provision_request(padapter,\n\t\t\t\t\t\t\t\t    NULL,\n\t\t\t\t\t\t\t\t    0,\n\t\t\t\t\t\tpwdinfo->tx_prov_disc_info.peerDevAddr);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\treturn _SUCCESS;\n\t} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) {\n\t\tif (_TRUE == pwdinfo->nego_req_info.benable) {\n\t\t\tRTW_INFO(\"[%s] P2P State is GONEGO ING!\\n\", __FUNCTION__);\n\t\t\tif (_rtw_memcmp(pwdinfo->nego_req_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN)) {\n\t\t\t\tpwdinfo->nego_req_info.benable = _FALSE;\n\t\t\t\tissue_p2p_GO_request(padapter, pwdinfo->nego_req_info.peerDevAddr);\n\t\t\t}\n\t\t}\n\t} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ)) {\n\t\tif (_TRUE == pwdinfo->invitereq_info.benable) {\n\t\t\tRTW_INFO(\"[%s] P2P_STATE_TX_INVITE_REQ!\\n\", __FUNCTION__);\n\t\t\tif (_rtw_memcmp(pwdinfo->invitereq_info.peer_macaddr, get_addr2_ptr(pframe), ETH_ALEN)) {\n\t\t\t\tpwdinfo->invitereq_info.benable = _FALSE;\n\t\t\t\tissue_p2p_invitation_request(padapter, pwdinfo->invitereq_info.peer_macaddr);\n\t\t\t}\n\t\t}\n\t}\n#endif\n\n\n\tif ((mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS))\n\t\t|| (MLME_IS_MESH(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE))\n\t\t#ifdef CONFIG_RTW_REPEATER_SON\n\t\t|| (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS)\n\t\t#endif\n\t) {\n\t\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\t\tif (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)\n\t\t\t&& (pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)\n\t\t) {\n\t\t\tif (!rtw_check_bcn_info(padapter, pframe, precv_frame->u.hdr.len)) {\n\t\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" ap has changed, disconnect now\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\t\treceive_disconnect(padapter, pmlmeinfo->network.MacAddress , 0, _FALSE);\n\t\t\t}\n\t\t}\n\n\t\trtw_mi_report_survey_event(padapter, precv_frame);\n\t\treturn _SUCCESS;\n\t}\n\n#if 0 /* move to validate_recv_mgnt_frame */\n\tif (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) {\n\t\tif (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) {\n\t\t\tpsta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));\n\t\t\tif (psta != NULL)\n\t\t\t\tpsta->sta_stats.rx_mgnt_pkts++;\n\t\t}\n\t}\n#endif\n\n\treturn _SUCCESS;\n\n}\n\n/* for 11n Logo 4.2.31/4.2.32 */\nstatic void rtw_check_legacy_ap(_adapter *padapter, u8 *pframe, u32 len)\n{\n\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n\tif (!padapter->registrypriv.wifi_spec)\n\t\treturn;\n\t\n\tif(!MLME_IS_AP(padapter))\n\t\treturn;\n\t\n\n\tif (pmlmeext->bstart_bss == _TRUE) {\n\t\tint left;\n\t\tunsigned char *pos;\n\t\tstruct rtw_ieee802_11_elems elems;\n#ifdef CONFIG_80211N_HT\n\t\tu16 cur_op_mode; \n#endif\n\t\t/* checking IEs */\n\t\tleft = len - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_;\n\t\tpos = pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_;\n\t\tif (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) {\n\t\t\tRTW_INFO(\"%s: parse fail for \"MAC_FMT\"\\n\", __func__, MAC_ARG(GetAddr3Ptr(pframe)));\n\t\t\treturn;\n\t\t}\n#ifdef CONFIG_80211N_HT\n\t\tcur_op_mode = pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_OP_MODE_MASK;\n#endif\n\t\t/* for legacy ap */\n\t\tif (elems.ht_capabilities == NULL && elems.ht_capabilities_len == 0) {\n\n\t\t\tif (0)\n\t\t\t\tRTW_INFO(\"%s: \"MAC_FMT\" is legacy ap\\n\", __func__, MAC_ARG(GetAddr3Ptr(pframe)));\n\n\t\t\tATOMIC_SET(&pmlmepriv->olbc, _TRUE);\n\t\t\tATOMIC_SET(&pmlmepriv->olbc_ht, _TRUE);\n\t\t}\n\t\t\t\n\t}\n}\n\nunsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tstruct sta_info\t*psta;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct sta_priv\t*pstapriv = &padapter->stapriv;\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tuint len = precv_frame->u.hdr.len;\n\tWLAN_BSSID_EX *pbss;\n\tint ret = _SUCCESS;\n#ifdef CONFIG_TDLS\n\tstruct sta_info *ptdls_sta;\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n#ifdef CONFIG_TDLS_CH_SW\n\tstruct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;\n#endif\n#endif /* CONFIG_TDLS */\n\n\tif (validate_beacon_len(pframe, len) == _FALSE)\n\t\treturn _SUCCESS;\n\n\tif (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)\n\t\t|| (MLME_IS_MESH(padapter) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE))\n\t) {\n\t\tif (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)\n\t\t\t&& (pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)\n\t\t) {\n\t\t\tif (!rtw_check_bcn_info(padapter, pframe, len)) {\n\t\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" ap has changed, disconnect now\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\t\treceive_disconnect(padapter, pmlmeinfo->network.MacAddress , 0, _FALSE);\n\t\t\t}\n\t\t}\n\n\t\trtw_mi_report_survey_event(padapter, precv_frame);\n\t\treturn _SUCCESS;\n\t}\n#ifdef CONFIG_RTW_REPEATER_SON\n\tif (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS)\n\t\trtw_mi_report_survey_event(padapter, precv_frame);\n#endif\n\n\trtw_check_legacy_ap(padapter, pframe, len);\n\n\tif (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) {\n\t\tif ((pmlmeinfo->state & WIFI_FW_AUTH_NULL)\n\t\t\t&& (rtw_sta_linking_test_wait_done() || pmlmeext->join_abort)\n\t\t) {\n\t\t\tif (rtw_sta_linking_test_force_fail() || pmlmeext->join_abort) {\n\t\t\t\tset_link_timer(pmlmeext, 1);\n\t\t\t\treturn _SUCCESS;\n\t\t\t}\n\n\t\t\t/* we should update current network before auth, or some IE is wrong */\n\t\t\tpbss = (WLAN_BSSID_EX *)rtw_malloc(sizeof(WLAN_BSSID_EX));\n\t\t\tif (pbss) {\n\t\t\t\tif (collect_bss_info(padapter, precv_frame, pbss) == _SUCCESS) {\n\t\t\t\t\tstruct beacon_keys recv_beacon;\n\n\t\t\t\t\tupdate_network(&(pmlmepriv->cur_network.network), pbss, padapter, _TRUE);\n\n\t\t\t\t\t/* update bcn keys */\n\t\t\t\t\tif (rtw_get_bcn_keys(padapter, pframe, len, &recv_beacon) == _TRUE) {\n\t\t\t\t\t\tRTW_INFO(\"%s: beacon keys ready\\n\", __func__);\n\t\t\t\t\t\t_rtw_memcpy(&pmlmepriv->cur_beacon_keys,\n\t\t\t\t\t\t\t&recv_beacon, sizeof(recv_beacon));\n\t\t\t\t\t\tif (is_hidden_ssid(recv_beacon.ssid, recv_beacon.ssid_len)) {\n\t\t\t\t\t\t\t_rtw_memcpy(pmlmepriv->cur_beacon_keys.ssid, pmlmeinfo->network.Ssid.Ssid, IW_ESSID_MAX_SIZE);\n\t\t\t\t\t\t\tpmlmepriv->cur_beacon_keys.ssid_len = pmlmeinfo->network.Ssid.SsidLength;\n\t\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\tRTW_ERR(\"%s: get beacon keys failed\\n\", __func__);\n\t\t\t\t\t\t_rtw_memset(&pmlmepriv->cur_beacon_keys, 0, sizeof(recv_beacon));\n\t\t\t\t\t}\n\t\t\t\t\t#ifdef CONFIG_BCN_CNT_CONFIRM_HDL\n\t\t\t\t\tpmlmepriv->new_beacon_cnts = 0;\n\t\t\t\t\t#endif\n\t\t\t\t}\n\t\t\t\trtw_mfree((u8 *)pbss, sizeof(WLAN_BSSID_EX));\n\t\t\t}\n\n\t\t\t/* check the vendor of the assoc AP */\n\t\t\tpmlmeinfo->assoc_AP_vendor = check_assoc_AP(pframe + sizeof(struct rtw_ieee80211_hdr_3addr), len - sizeof(struct rtw_ieee80211_hdr_3addr));\n\n\t\t\t/* update TSF Value */\n\t\t\tupdate_TSF(pmlmeext, pframe, len);\n\t\t\tpmlmeext->bcn_cnt = 0;\n\t\t\tpmlmeext->last_bcn_cnt = 0;\n\n#ifdef CONFIG_P2P_PS\n\t\t\t/* Comment by YiWei , in wifi p2p spec the \"3.3 P2P Power Management\" , \"These mechanisms are available in a P2P Group in which only P2P Devices are associated.\" */\n\t\t\t/* process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)); */\n#endif /* CONFIG_P2P_PS */\n\n#if defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)\n\t\t\tif (padapter->registrypriv.wifi_spec) {\n\t\t\t\tif (process_p2p_cross_connect_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)) == _FALSE) {\n\t\t\t\t\tif (rtw_mi_buddy_check_mlmeinfo_state(padapter, WIFI_FW_AP_STATE)) {\n\t\t\t\t\t\tRTW_PRINT(\"no issue auth, P2P cross-connect does not permit\\n \");\n\t\t\t\t\t\treturn _SUCCESS;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n#endif /* CONFIG_P2P CONFIG_P2P and CONFIG_CONCURRENT_MODE */\n\n\t\t\t/* start auth */\n\t\t\tstart_clnt_auth(padapter);\n\n\t\t\treturn _SUCCESS;\n\t\t}\n\n\t\tif (((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) {\n\t\t\tpsta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));\n\t\t\tif (psta != NULL) {\n#ifdef CONFIG_PATCH_JOIN_WRONG_CHANNEL\n\t\t\t\t/* Merge from 8712 FW code */\n\t\t\t\tif (cmp_pkt_chnl_diff(padapter, pframe, len) != 0) {\n\t\t\t\t\t/* join wrong channel, deauth and reconnect           */\n\t\t\t\t\tissue_deauth(padapter, (&(pmlmeinfo->network))->MacAddress, WLAN_REASON_DEAUTH_LEAVING);\n\n\t\t\t\t\treport_del_sta_event(padapter, (&(pmlmeinfo->network))->MacAddress, WLAN_REASON_JOIN_WRONG_CHANNEL, _TRUE, _FALSE);\n\t\t\t\t\tpmlmeinfo->state &= (~WIFI_FW_ASSOC_SUCCESS);\n\t\t\t\t\treturn _SUCCESS;\n\t\t\t\t}\n#endif /* CONFIG_PATCH_JOIN_WRONG_CHANNEL */\n#ifdef CONFIG_RTW_80211R\n\t\t\t\trtw_ft_update_bcn(padapter, precv_frame);\n#endif\n\t\t\t\tret = rtw_check_bcn_info(padapter, pframe, len);\n\t\t\t\tif (!ret) {\n\t\t\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" ap has changed, disconnect now\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\t\t\treceive_disconnect(padapter, pmlmeinfo->network.MacAddress , 0, _FALSE);\n\t\t\t\t\treturn _SUCCESS;\n\t\t\t\t}\n\t\t\t\t/* update WMM, ERP in the beacon */\n\t\t\t\t/* todo: the timer is used instead of the number of the beacon received */\n\t\t\t\tif ((sta_rx_pkts(psta) & 0xf) == 0) {\n\t\t\t\t\t/* RTW_INFO(\"update_bcn_info\\n\"); */\n\t\t\t\t\tupdate_beacon_info(padapter, pframe, len, psta);\n\t\t\t\t}\n\n\t\t\t\tpmlmepriv->cur_network_scanned->network.Rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power;\n\t\t\t\tpmlmeext->bcn_cnt++;\n#ifdef CONFIG_BCN_RECV_TIME\n\t\t\t\trtw_rx_bcn_time_update(padapter, len, precv_frame->u.hdr.attrib.data_rate);\n#endif\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\n\t\t\t\tif (rtw_tdls_is_chsw_allowed(padapter) == _TRUE) {\n\t\t\t\t\t/* Send TDLS Channel Switch Request when receiving Beacon */\n\t\t\t\t\tif ((padapter->tdlsinfo.chsw_info.ch_sw_state & TDLS_CH_SW_INITIATOR_STATE) && (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE)\n\t\t\t\t\t    && (pmlmeext->cur_channel == rtw_get_oper_ch(padapter))) {\n\t\t\t\t\t\tptdls_sta = rtw_get_stainfo(&padapter->stapriv, padapter->tdlsinfo.chsw_info.addr);\n\t\t\t\t\t\tif (ptdls_sta != NULL) {\n\t\t\t\t\t\t\tif (ptdls_sta->tdls_sta_state | TDLS_LINKED_STATE)\n\t\t\t\t\t\t\t\t_set_timer(&ptdls_sta->stay_on_base_chnl_timer, TDLS_CH_SW_STAY_ON_BASE_CHNL_TIMEOUT);\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n#endif\n#endif /* CONFIG_TDLS */\n\n\t\t\t\t#ifdef CONFIG_DFS\n\t\t\t\tprocess_csa_ie(padapter\n\t\t\t\t\t, pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_\n\t\t\t\t\t, len - (WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_));\n\t\t\t\t#endif\n\n#ifdef CONFIG_P2P_PS\n\t\t\t\tprocess_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN));\n#endif /* CONFIG_P2P_PS */\n\n\t\t\t\tif (pmlmeext->tsf_update_required && pmlmeext->en_hw_update_tsf)\n\t\t\t\t\trtw_enable_hw_update_tsf_cmd(padapter);\n\n#if 0 /* move to validate_recv_mgnt_frame */\n\t\t\t\tpsta->sta_stats.rx_mgnt_pkts++;\n#endif\n\t\t\t}\n\n\t\t} else if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {\n\t\t\tu8 rate_set[16];\n\t\t\tu8 rate_num = 0;\n\n\t\t\tpsta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));\n\t\t\tif (psta != NULL) {\n\t\t\t\t/*\n\t\t\t\t* update WMM, ERP in the beacon\n\t\t\t\t* todo: the timer is used instead of the number of the beacon received\n\t\t\t\t*/\n\t\t\t\tif ((sta_rx_pkts(psta) & 0xf) == 0)\n\t\t\t\t\tupdate_beacon_info(padapter, pframe, len, psta);\n\n\t\t\t\tif (pmlmeext->tsf_update_required && pmlmeext->en_hw_update_tsf)\n\t\t\t\t\trtw_enable_hw_update_tsf_cmd(padapter);\n\t\t\t} else {\n\t\t\t\trtw_ies_get_supported_rate(pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_, len - WLAN_HDR_A3_LEN - _BEACON_IE_OFFSET_, rate_set, &rate_num);\n\t\t\t\tif (rate_num == 0) {\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" RX beacon with no supported rate\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\t\t\tgoto _END_ONBEACON_;\n\t\t\t\t}\n\n\t\t\t\tpsta = rtw_alloc_stainfo(pstapriv, get_addr2_ptr(pframe));\n\t\t\t\tif (psta == NULL) {\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" Exceed the upper limit of supported clients\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\t\t\tgoto _END_ONBEACON_;\n\t\t\t\t}\n\n\t\t\t\tpsta->expire_to = pstapriv->adhoc_expire_to;\n\n\t\t\t\t_rtw_memcpy(psta->bssrateset, rate_set, rate_num);\n\t\t\t\tpsta->bssratelen = rate_num;\n\n\t\t\t\t/* update TSF Value */\n\t\t\t\tupdate_TSF(pmlmeext, pframe, len);\n\n\t\t\t\t/* report sta add event */\n\t\t\t\treport_add_sta_event(padapter, get_addr2_ptr(pframe));\n\t\t\t}\n\t\t}\n\t}\n\n_END_ONBEACON_:\n\n\treturn _SUCCESS;\n\n}\n\nunsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame)\n{\n#ifdef CONFIG_AP_MODE\n\t_irqL irqL;\n\tunsigned int\tauth_mode, seq, ie_len;\n\tunsigned char\t*sa, *p;\n\tu16\talgorithm;\n\tint\tstatus;\n\tstatic struct sta_info stat;\n\tstruct\tsta_info\t*pstat = NULL;\n\tstruct\tsta_priv *pstapriv = &padapter->stapriv;\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tuint len = precv_frame->u.hdr.len;\n\tu8\toffset = 0;\n\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) &&\n\t    rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_LINKING | _FW_UNDER_SURVEY)) {\n\t\t/* don't process auth request; */\n\t\treturn _SUCCESS;\n\t}\n#endif /* CONFIG_CONCURRENT_MODE */\n\n\tif ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)\n\t\treturn _FAIL;\n\n\tif (!MLME_IS_ASOC(padapter))\n\t\treturn _SUCCESS;\n\n#if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_RTW_MESH)\n\tif (MLME_IS_MESH(padapter))\n\t\treturn rtw_mesh_on_auth(padapter, precv_frame);\n#endif\n\n\tRTW_INFO(\"+OnAuth\\n\");\n\n\tsa = get_addr2_ptr(pframe);\n\n\tauth_mode = psecuritypriv->dot11AuthAlgrthm;\n\n\tif (GetPrivacy(pframe)) {\n\t\tu8\t*iv;\n\t\tstruct rx_pkt_attrib\t*prxattrib = &(precv_frame->u.hdr.attrib);\n\n\t\tprxattrib->hdrlen = WLAN_HDR_A3_LEN;\n\t\tprxattrib->encrypt = _WEP40_;\n\n\t\tiv = pframe + prxattrib->hdrlen;\n\t\tprxattrib->key_index = ((iv[3] >> 6) & 0x3);\n\n\t\tprxattrib->iv_len = 4;\n\t\tprxattrib->icv_len = 4;\n\n\t\trtw_wep_decrypt(padapter, (u8 *)precv_frame);\n\n\t\toffset = 4;\n\t}\n\n\talgorithm = le16_to_cpu(*(u16 *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset));\n\tseq\t= le16_to_cpu(*(u16 *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2));\n\n\tRTW_INFO(\"auth alg=%x, seq=%X\\n\", algorithm, seq);\n\n\tif (rtw_ap_linking_test_force_auth_fail()) {\n\t\tstatus = rtw_ap_linking_test_force_auth_fail();\n\t\tRTW_INFO(FUNC_ADPT_FMT\" force auth fail with status:%u\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), status);\n\t\tgoto auth_fail;\n\t}\n\n\tif ((auth_mode == 2) && (algorithm != WLAN_AUTH_SAE) &&\n\t    (psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) &&\n\t    (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_))\n\t\tauth_mode = 0;\n\n\tif ((algorithm > 0 && auth_mode == 0) ||\t/* rx a shared-key auth but shared not enabled */\n\t    (algorithm == 0 && auth_mode == 1)) {\t/* rx a open-system auth but shared-key is enabled */\n\t\tRTW_INFO(\"auth rejected due to bad alg [alg=%d, auth_mib=%d] %02X%02X%02X%02X%02X%02X\\n\",\n\t\t\talgorithm, auth_mode, sa[0], sa[1], sa[2], sa[3], sa[4], sa[5]);\n\n\t\tstatus = _STATS_NO_SUPP_ALG_;\n\n\t\tgoto auth_fail;\n\t}\n\n#if CONFIG_RTW_MACADDR_ACL\n\tif (rtw_access_ctrl(padapter, sa) == _FALSE) {\n\t\tstatus = _STATS_UNABLE_HANDLE_STA_;\n\t\tgoto auth_fail;\n\t}\n#endif\n\n\tpstat = rtw_get_stainfo(pstapriv, sa);\n\tif (pstat == NULL) {\n\n\t\t/* allocate a new one */\n\t\tRTW_INFO(\"going to alloc stainfo for sa=\"MAC_FMT\"\\n\",  MAC_ARG(sa));\n\t\tpstat = rtw_alloc_stainfo(pstapriv, sa);\n\t\tif (pstat == NULL) {\n\t\t\tRTW_INFO(\" Exceed the upper limit of supported clients...\\n\");\n\t\t\tstatus = _STATS_UNABLE_HANDLE_STA_;\n\t\t\tgoto auth_fail;\n\t\t}\n\n\t\tpstat->state = WIFI_FW_AUTH_NULL;\n\t\tpstat->auth_seq = 0;\n\n\t\t/* pstat->flags = 0; */\n\t\t/* pstat->capability = 0; */\n\t} else {\n#ifdef CONFIG_IEEE80211W\n\t\tif (pstat->bpairwise_key_installed != _TRUE && !(pstat->state & WIFI_FW_ASSOC_SUCCESS))\n#endif /* CONFIG_IEEE80211W */\n\t\t{\n\n\t\t\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\t\t\tif (rtw_is_list_empty(&pstat->asoc_list) == _FALSE) {\n\t\t\t\trtw_list_delete(&pstat->asoc_list);\n\t\t\t\tpstapriv->asoc_list_cnt--;\n\t\t\t\tif (pstat->expire_to > 0)\n\t\t\t\t\t;/* TODO: STA re_auth within expire_to */\n\t\t\t}\n\t\t\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\t\t\tif (seq == 1)\n\t\t\t\t; /* TODO: STA re_auth and auth timeout */\n\n\t\t}\n\t}\n\n#ifdef CONFIG_IEEE80211W\n\tif (pstat->bpairwise_key_installed != _TRUE && !(pstat->state & WIFI_FW_ASSOC_SUCCESS))\n#endif /* CONFIG_IEEE80211W */\n\t{\n\t\t_enter_critical_bh(&pstapriv->auth_list_lock, &irqL);\n\t\tif (rtw_is_list_empty(&pstat->auth_list)) {\n\n\t\t\trtw_list_insert_tail(&pstat->auth_list, &pstapriv->auth_list);\n\t\t\tpstapriv->auth_list_cnt++;\n\t\t}\n\t\t_exit_critical_bh(&pstapriv->auth_list_lock, &irqL);\n\t}\n\n\tif (pstat->auth_seq == 0)\n\t\tpstat->expire_to = pstapriv->auth_to;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (GET_CFG80211_REPORT_MGMT(adapter_wdev_data(padapter), IEEE80211_STYPE_AUTH) == _TRUE) {\n\t\tif ((algorithm == WLAN_AUTH_SAE) &&\n\t\t\t(auth_mode == dot11AuthAlgrthm_8021X)) {\n\t\t\tpstat->authalg = algorithm;\n\n\t\t\trtw_cfg80211_rx_mframe(padapter, precv_frame, NULL);\n\t\t\treturn _SUCCESS;\n\t\t}\n\t}\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n\tif ((pstat->auth_seq + 1) != seq) {\n\t\tRTW_INFO(\"(1)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\\n\",\n\t\t\t seq, pstat->auth_seq + 1);\n\t\tstatus = _STATS_OUT_OF_AUTH_SEQ_;\n\t\tgoto auth_fail;\n\t}\n\n\tif (algorithm == 0 && (auth_mode == 0 || auth_mode == 2 || auth_mode == 3)) {\n\t\tif (seq == 1) {\n#ifdef CONFIG_IEEE80211W\n\t\t\tif (pstat->bpairwise_key_installed != _TRUE && !(pstat->state & WIFI_FW_ASSOC_SUCCESS))\n#endif /* CONFIG_IEEE80211W */\n\t\t\t{\n\t\t\t\tpstat->state &= ~WIFI_FW_AUTH_NULL;\n\t\t\t\tpstat->state |= WIFI_FW_AUTH_SUCCESS;\n\t\t\t\tpstat->expire_to = pstapriv->assoc_to;\n\t\t\t}\n\t\t\tpstat->authalg = algorithm;\n\t\t} else {\n\t\t\tRTW_INFO(\"(2)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\\n\",\n\t\t\t\t seq, pstat->auth_seq + 1);\n\t\t\tstatus = _STATS_OUT_OF_AUTH_SEQ_;\n\t\t\tgoto auth_fail;\n\t\t}\n\t} else { /* shared system or auto authentication */\n\t\tif (seq == 1) {\n\t\t\t/* prepare for the challenging txt... */\n\n\t\t\t/* get_random_bytes((void *)pstat->chg_txt, 128); */ /* TODO: */\n\t\t\t_rtw_memset((void *)pstat->chg_txt, 78, 128);\n#ifdef CONFIG_IEEE80211W\n\t\t\tif (pstat->bpairwise_key_installed != _TRUE && !(pstat->state & WIFI_FW_ASSOC_SUCCESS))\n#endif /* CONFIG_IEEE80211W */\n\t\t\t{\n\t\t\t\tpstat->state &= ~WIFI_FW_AUTH_NULL;\n\t\t\t\tpstat->state |= WIFI_FW_AUTH_STATE;\n\t\t\t}\n\t\t\tpstat->authalg = algorithm;\n\t\t\tpstat->auth_seq = 2;\n\t\t} else if (seq == 3) {\n\t\t\t/* checking for challenging txt... */\n\t\t\tRTW_INFO(\"checking for challenging txt...\\n\");\n\n\t\t\tp = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + 4 + _AUTH_IE_OFFSET_ , _CHLGETXT_IE_, (int *)&ie_len,\n\t\t\t\tlen - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_ - 4);\n\n\t\t\tif ((p == NULL) || (ie_len <= 0)) {\n\t\t\t\tRTW_INFO(\"auth rejected because challenge failure!(1)\\n\");\n\t\t\t\tstatus = _STATS_CHALLENGE_FAIL_;\n\t\t\t\tgoto auth_fail;\n\t\t\t}\n\n\t\t\tif (_rtw_memcmp((void *)(p + 2), pstat->chg_txt, 128)) {\n#ifdef CONFIG_IEEE80211W\n\t\t\t\tif (pstat->bpairwise_key_installed != _TRUE && !(pstat->state & WIFI_FW_ASSOC_SUCCESS))\n#endif /* CONFIG_IEEE80211W */\n\t\t\t\t{\n\t\t\t\t\tpstat->state &= (~WIFI_FW_AUTH_STATE);\n\t\t\t\t\tpstat->state |= WIFI_FW_AUTH_SUCCESS;\n\t\t\t\t\t/* challenging txt is correct... */\n\t\t\t\t\tpstat->expire_to =  pstapriv->assoc_to;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tRTW_INFO(\"auth rejected because challenge failure!\\n\");\n\t\t\t\tstatus = _STATS_CHALLENGE_FAIL_;\n\t\t\t\tgoto auth_fail;\n\t\t\t}\n\t\t} else {\n\t\t\tRTW_INFO(\"(3)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\\n\",\n\t\t\t\t seq, pstat->auth_seq + 1);\n\t\t\tstatus = _STATS_OUT_OF_AUTH_SEQ_;\n\t\t\tgoto auth_fail;\n\t\t}\n\t}\n\n\n\t/* Now, we are going to issue_auth... */\n\tpstat->auth_seq = seq + 1;\n\n#ifdef CONFIG_NATIVEAP_MLME\n\tissue_auth(padapter, pstat, (unsigned short)(_STATS_SUCCESSFUL_));\n#endif\n\n\tif ((pstat->state & WIFI_FW_AUTH_SUCCESS) || (pstat->state & WIFI_FW_ASSOC_SUCCESS))\n\t\tpstat->auth_seq = 0;\n\n\n\treturn _SUCCESS;\n\nauth_fail:\n\n\tif (pstat)\n\t\trtw_free_stainfo(padapter , pstat);\n\n\tpstat = &stat;\n\t_rtw_memset((char *)pstat, '\\0', sizeof(stat));\n\tpstat->auth_seq = 2;\n\t_rtw_memcpy(pstat->cmn.mac_addr, sa, ETH_ALEN);\n\n#ifdef CONFIG_NATIVEAP_MLME\n\tissue_auth(padapter, pstat, (unsigned short)status);\n#endif\n\n#endif\n\treturn _FAIL;\n\n}\n\nunsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tunsigned int\tseq, len, status, algthm, offset;\n\tunsigned char\t*p;\n\tunsigned int\tgo2asoc = 0;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tuint pkt_len = precv_frame->u.hdr.len;\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (GET_CFG80211_REPORT_MGMT(adapter_wdev_data(padapter), IEEE80211_STYPE_AUTH) == _TRUE) {\n\t\tif (rtw_sec_chk_auth_type(padapter, NL80211_AUTHTYPE_SAE)) {\n\t\t\tif (rtw_cached_pmkid(padapter, get_my_bssid(&pmlmeinfo->network)) != -1) {\n\t\t\t\tRTW_INFO(\"SAE: PMKSA cache entry found\\n\");\n\t\t\t\tgoto normal;\n\t\t\t}\n\t\t\trtw_cfg80211_rx_mframe(padapter, precv_frame, NULL);\n\t\t\treturn _SUCCESS;\n\t\t}\n\t}\n\nnormal:\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n\t/* check A1 matches or not */\n\tif (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN))\n\t\treturn _SUCCESS;\n\n\tif (!(pmlmeinfo->state & WIFI_FW_AUTH_STATE) || pmlmeext->join_abort)\n\t\treturn _SUCCESS;\n\n\toffset = (GetPrivacy(pframe)) ? 4 : 0;\n\n\talgthm\t= le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset));\n\tseq\t= le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2));\n\tstatus\t= le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 4));\n\n\tif (status != 0) {\n\t\tRTW_INFO(\"clnt auth fail, status: %d\\n\", status);\n\t\tif (status == 13) { /* && pmlmeinfo->auth_algo == dot11AuthAlgrthm_Auto) */\n\t\t\tif (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared)\n\t\t\t\tpmlmeinfo->auth_algo = dot11AuthAlgrthm_Open;\n\t\t\telse\n\t\t\t\tpmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared;\n\t\t\t/* pmlmeinfo->reauth_count = 0; */\n\t\t}\n\n\t\tpmlmeinfo->auth_status = status;\n\t\tset_link_timer(pmlmeext, 1);\n\t\tgoto authclnt_fail;\n\t}\n\n\tif (seq == 2) {\n\t\tif (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) {\n\t\t\t/* legendary shared system */\n\t\t\tp = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _AUTH_IE_OFFSET_, _CHLGETXT_IE_, (int *)&len,\n\t\t\t\tpkt_len - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_);\n\n\t\t\tif (p == NULL) {\n\t\t\t\t/* RTW_INFO(\"marc: no challenge text?\\n\"); */\n\t\t\t\tgoto authclnt_fail;\n\t\t\t}\n\n\t\t\t_rtw_memcpy((void *)(pmlmeinfo->chg_txt), (void *)(p + 2), len);\n\t\t\tpmlmeinfo->auth_seq = 3;\n\t\t\tissue_auth(padapter, NULL, 0);\n\t\t\tset_link_timer(pmlmeext, REAUTH_TO);\n\n\t\t\treturn _SUCCESS;\n\t\t} else {\n\t\t\t/* open, or 802.11r FTAA system */\n\t\t\tgo2asoc = 1;\n\t\t}\n\t} else if (seq == 4) {\n\t\tif (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared)\n\t\t\tgo2asoc = 1;\n\t\telse\n\t\t\tgoto authclnt_fail;\n\t} else {\n\t\t/* this is also illegal */\n\t\t/* RTW_INFO(\"marc: clnt auth failed due to illegal seq=%x\\n\", seq); */\n\t\tgoto authclnt_fail;\n\t}\n\n\tif (go2asoc) {\n#ifdef CONFIG_RTW_80211R\n\t\tif (rtw_ft_update_auth_rsp_ies(padapter, pframe, pkt_len))\n\t\t\treturn _SUCCESS;\n#endif\n\t\tRTW_PRINT(\"auth success, start assoc\\n\");\n\t\tstart_clnt_assoc(padapter);\n\t\treturn _SUCCESS;\n\t}\n\nauthclnt_fail:\n\n\t/* pmlmeinfo->state &= ~(WIFI_FW_AUTH_STATE); */\n\n\treturn _FAIL;\n\n}\n\nunsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)\n{\n#ifdef CONFIG_AP_MODE\n\t_irqL irqL;\n\tu16 listen_interval;\n\tstruct rtw_ieee802_11_elems elems;\n\tstruct sta_info\t*pstat;\n\tunsigned char\t\treassoc, *pos;\n\tint\t\tleft;\n\tunsigned short\t\tstatus = _STATS_SUCCESSFUL_;\n\tunsigned short\t\tframe_type, ie_offset = 0;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t*cur = &(pmlmeinfo->network);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tuint pkt_len = precv_frame->u.hdr.len;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\tu8 p2p_status_code = P2P_STATUS_SUCCESS;\n\tu8 *p2pie;\n\tu32 p2pielen = 0;\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) &&\n\t    rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_LINKING | _FW_UNDER_SURVEY)) {\n\t\t/* don't process assoc request; */\n\t\treturn _SUCCESS;\n\t}\n#endif /* CONFIG_CONCURRENT_MODE */\n\n\tif ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)\n\t\treturn _FAIL;\n\n\tframe_type = get_frame_sub_type(pframe);\n\tif (frame_type == WIFI_ASSOCREQ) {\n\t\treassoc = 0;\n\t\tie_offset = _ASOCREQ_IE_OFFSET_;\n\t} else { /* WIFI_REASSOCREQ */\n\t\treassoc = 1;\n\t\tie_offset = _REASOCREQ_IE_OFFSET_;\n\t}\n\n\n\tif (pkt_len < IEEE80211_3ADDR_LEN + ie_offset) {\n\t\tRTW_INFO(\"handle_assoc(reassoc=%d) - too short payload (len=%lu)\"\n\t\t\t \"\\n\", reassoc, (unsigned long)pkt_len);\n\t\treturn _FAIL;\n\t}\n\n\tpstat = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));\n\tif (pstat == (struct sta_info *)NULL) {\n\t\tstatus = _RSON_CLS2_;\n\t\tgoto asoc_class2_error;\n\t}\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\tif (pstat->authalg == WLAN_AUTH_SAE) {\n\t\t/* WPA3-SAE */\n\t\tif (((pstat->state) & WIFI_FW_AUTH_NULL)) {\n\t\t\t/* TODO:\n\t\t\t   Queue AssocReq and Proccess\n\t\t\t   by external auth trigger. */\n\t\t\tRTW_INFO(\"%s: wait external auth trigger\\n\", __func__);\n\t\t\treturn _SUCCESS;\n\t\t}\n\t}\n\n\t/* check if this stat has been successfully authenticated/assocated */\n\tif (!((pstat->state) & WIFI_FW_AUTH_SUCCESS)) {\n\t\tif (!((pstat->state) & WIFI_FW_ASSOC_SUCCESS)) {\n\t\t\tstatus = _RSON_CLS2_;\n\t\t\tgoto asoc_class2_error;\n\t\t} else {\n\t\t\tpstat->state &= (~WIFI_FW_ASSOC_SUCCESS);\n\t\t\tpstat->state |= WIFI_FW_ASSOC_STATE;\n\t\t}\n\t} else {\n\t\tpstat->state &= (~WIFI_FW_AUTH_SUCCESS);\n\t\tpstat->state |= WIFI_FW_ASSOC_STATE;\n\t}\n\n#if 0/* todo:tkip_countermeasures */\n\tif (hapd->tkip_countermeasures) {\n\t\tresp = WLAN_REASON_MICHAEL_MIC_FAILURE;\n\t\tgoto fail;\n\t}\n#endif\n\n\tif (rtw_ap_linking_test_force_asoc_fail()) {\n\t\tstatus = rtw_ap_linking_test_force_asoc_fail();\n\t\tRTW_INFO(FUNC_ADPT_FMT\" force asoc fail with status:%u\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), status);\n\t\tgoto OnAssocReqFail;\n\t}\n\n\t/* now parse all ieee802_11 ie to point to elems */\n\tleft = pkt_len - (IEEE80211_3ADDR_LEN + ie_offset);\n\tpos = pframe + (IEEE80211_3ADDR_LEN + ie_offset);\n\tif (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) {\n\t\tRTW_INFO(\"STA \" MAC_FMT \" sent invalid association request\\n\",\n\t\t\t MAC_ARG(pstat->cmn.mac_addr));\n\t\tstatus = _STATS_FAILURE_;\n\t\tgoto OnAssocReqFail;\n\t}\n\n\trtw_ap_parse_sta_capability(padapter, pstat, pframe + WLAN_HDR_A3_LEN);\n\n\tlisten_interval = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN + 2);\n#if 0/* todo: */\n\t/* check listen_interval */\n\tif (listen_interval > hapd->conf->max_listen_interval) {\n\t\thostapd_logger(hapd, mgmt->sa, HOSTAPD_MODULE_IEEE80211,\n\t\t\t       HOSTAPD_LEVEL_DEBUG,\n\t\t\t       \"Too large Listen Interval (%d)\",\n\t\t\t       listen_interval);\n\t\tresp = WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE;\n\t\tgoto fail;\n\t}\n\n\tpstat->listen_interval = listen_interval;\n#endif\n\n\t/* now we should check all the fields... */\n\t/* checking SSID */\n\tif (elems.ssid == NULL\n\t\t|| elems.ssid_len == 0\n\t\t|| elems.ssid_len != cur->Ssid.SsidLength\n\t\t|| _rtw_memcmp(elems.ssid, cur->Ssid.Ssid, cur->Ssid.SsidLength) == _FALSE\n\t) {\n\t\tstatus = _STATS_FAILURE_;\n\t\tgoto OnAssocReqFail;\n\t}\n\n\t/* (Extended) Supported rates */\n\tstatus = rtw_ap_parse_sta_supported_rates(padapter, pstat\n\t\t, pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset);\n\tif (status != _STATS_SUCCESSFUL_)\n\t\tgoto OnAssocReqFail;\n\n\t/* check RSN/WPA/WPS */\n\tstatus = rtw_ap_parse_sta_security_ie(padapter, pstat, &elems);\n\tif (status != _STATS_SUCCESSFUL_)\n\t\tgoto OnAssocReqFail;\n\n\t/* check if there is WMM IE & support WWM-PS */\n\trtw_ap_parse_sta_wmm_ie(padapter, pstat\n\t\t, pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset);\n\n#ifdef CONFIG_RTS_FULL_BW\n\t/*check vendor IE*/\n\trtw_parse_sta_vendor_ie_8812(padapter, pstat\n\t\t, pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset);\n#endif/*CONFIG_RTS_FULL_BW*/\n\n\trtw_ap_parse_sta_ht_ie(padapter, pstat, &elems);\n\trtw_ap_parse_sta_vht_ie(padapter, pstat, &elems);\n\n\tif (((pstat->flags & WLAN_STA_HT) || (pstat->flags & WLAN_STA_VHT)) &&\n\t    ((pstat->wpa2_pairwise_cipher & WPA_CIPHER_TKIP) ||\n\t     (pstat->wpa_pairwise_cipher & WPA_CIPHER_TKIP))) {\n\n\t\tRTW_INFO(\"(V)HT: \" MAC_FMT \" tried to use TKIP with (V)HT association\\n\", MAC_ARG(pstat->cmn.mac_addr));\n\n\t\tpstat->flags &= ~WLAN_STA_HT;\n\t\tpstat->flags &= ~WLAN_STA_VHT;\n\t\t/*status = WLAN_STATUS_CIPHER_REJECTED_PER_POLICY;\n\t\t  * goto OnAssocReqFail;\n\t\t*/\n\t}\n\n\tif (status != _STATS_SUCCESSFUL_)\n\t\tgoto OnAssocReqFail;\n\n#ifdef CONFIG_P2P\n\tpstat->is_p2p_device = _FALSE;\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\tp2pie = rtw_get_p2p_ie(pframe + WLAN_HDR_A3_LEN + ie_offset , pkt_len - WLAN_HDR_A3_LEN - ie_offset , NULL, &p2pielen);\n\t\tif (p2pie) {\n\t\t\tpstat->is_p2p_device = _TRUE;\n\t\t\tp2p_status_code = (u8)process_assoc_req_p2p_ie(pwdinfo, pframe, pkt_len, pstat);\n\t\t\tif (p2p_status_code > 0) {\n\t\t\t\tpstat->p2p_status_code = p2p_status_code;\n\t\t\t\tstatus = _STATS_CAP_FAIL_;\n\t\t\t\tgoto OnAssocReqFail;\n\t\t\t}\n\t\t}\n#ifdef CONFIG_WFD\n\t\trtw_process_wfd_ies(padapter, pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset, __func__);\n#endif\n\t}\n\tpstat->p2p_status_code = p2p_status_code;\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_RTW_REPEATER_SON\n\tif (rtw_rson_ap_check_sta(padapter, pframe, pkt_len, ie_offset))\n\t\tgoto OnAssocReqFail;\n#endif\n\n\t/* TODO: identify_proprietary_vendor_ie(); */\n\t/* Realtek proprietary IE */\n\t/* identify if this is Broadcom sta */\n\t/* identify if this is ralink sta */\n\t/* Customer proprietary IE */\n\n#ifdef CONFIG_RTW_80211K\n\trtw_ap_parse_sta_rm_en_cap(padapter, pstat, &elems);\n#endif\n\n\t/* AID assignment */\n\tif (pstat->cmn.aid > 0)\n\t\tRTW_INFO(FUNC_ADPT_FMT\" old AID=%d\\n\", FUNC_ADPT_ARG(padapter), pstat->cmn.aid);\n\telse {\n\t\tif (!rtw_aid_alloc(padapter, pstat)) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" no room for more AIDs\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\tstatus = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA;\n\t\t\tgoto OnAssocReqFail;\n\t\t}\n\t\tRTW_INFO(FUNC_ADPT_FMT\" allocate new AID=%d\\n\", FUNC_ADPT_ARG(padapter), pstat->cmn.aid);\n\t}\n\n\tpstat->state &= (~WIFI_FW_ASSOC_STATE);\n\tpstat->state |= WIFI_FW_ASSOC_SUCCESS;\n\t/* RTW_INFO(\"==================%s, %d,  (%x), bpairwise_key_installed=%d, MAC:\"MAC_FMT\"\\n\"\n\t, __func__, __LINE__, pstat->state, pstat->bpairwise_key_installed, MAC_ARG(pstat->cmn.mac_addr)); */\n#ifdef CONFIG_IEEE80211W\n\tif (pstat->bpairwise_key_installed != _TRUE)\n#endif /* CONFIG_IEEE80211W */\n\t{\n\t\t_enter_critical_bh(&pstapriv->auth_list_lock, &irqL);\n\t\tif (!rtw_is_list_empty(&pstat->auth_list)) {\n\t\t\trtw_list_delete(&pstat->auth_list);\n\t\t\tpstapriv->auth_list_cnt--;\n\t\t}\n\t\t_exit_critical_bh(&pstapriv->auth_list_lock, &irqL);\n\n\t\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\t\tif (rtw_is_list_empty(&pstat->asoc_list)) {\n\t\t\tpstat->expire_to = pstapriv->expire_to;\n\t\t\trtw_list_insert_tail(&pstat->asoc_list, &pstapriv->asoc_list);\n\t\t\tpstapriv->asoc_list_cnt++;\n\t\t}\n\t\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\t}\n\n\t/* now the station is qualified to join our BSS...\t */\n\tif (pstat && (pstat->state & WIFI_FW_ASSOC_SUCCESS) && (_STATS_SUCCESSFUL_ == status)) {\n#ifdef CONFIG_NATIVEAP_MLME\n#ifdef CONFIG_IEEE80211W\n\t\tif (pstat->bpairwise_key_installed != _TRUE)\n#endif /* CONFIG_IEEE80211W */\n\t\t{\n\t\t\t/* .1 bss_cap_update & sta_info_update */\n\t\t\tbss_cap_update_on_sta_join(padapter, pstat);\n\t\t\tsta_info_update(padapter, pstat);\n\t\t}\n#ifdef CONFIG_IEEE80211W\n\t\tif (pstat->bpairwise_key_installed == _TRUE)\n\t\t\tstatus = _STATS_REFUSED_TEMPORARILY_;\n#endif /* CONFIG_IEEE80211W */\n\t\t/* .2 issue assoc rsp before notify station join event. */\n\t\tif (frame_type == WIFI_ASSOCREQ)\n\t\t\tissue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP);\n\t\telse\n\t\t\tissue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP);\n\n#ifdef CONFIG_IOCTL_CFG80211\n\t\t_enter_critical_bh(&pstat->lock, &irqL);\n\t\tif (pstat->passoc_req) {\n\t\t\trtw_mfree(pstat->passoc_req, pstat->assoc_req_len);\n\t\t\tpstat->passoc_req = NULL;\n\t\t\tpstat->assoc_req_len = 0;\n\t\t}\n\n\t\tpstat->passoc_req =  rtw_zmalloc(pkt_len);\n\t\tif (pstat->passoc_req) {\n\t\t\t_rtw_memcpy(pstat->passoc_req, pframe, pkt_len);\n\t\t\tpstat->assoc_req_len = pkt_len;\n\t\t}\n\t\t_exit_critical_bh(&pstat->lock, &irqL);\n#endif /* CONFIG_IOCTL_CFG80211 */\n#ifdef CONFIG_IEEE80211W\n\t\tif (pstat->bpairwise_key_installed != _TRUE)\n#endif /* CONFIG_IEEE80211W */\n\t\t{\n\t\t\t/* .3-(1) report sta add event */\n\t\t\treport_add_sta_event(padapter, pstat->cmn.mac_addr);\n\t\t}\n#ifdef CONFIG_IEEE80211W\n\t\tif (pstat->bpairwise_key_installed == _TRUE && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) {\n\t\t\tRTW_INFO(MAC_FMT\"\\n\", MAC_ARG(pstat->cmn.mac_addr));\n\t\t\tissue_action_SA_Query(padapter, pstat->cmn.mac_addr, 0, 0, IEEE80211W_RIGHT_KEY);\n\t\t}\n#endif /* CONFIG_IEEE80211W */\n#endif /* CONFIG_NATIVEAP_MLME */\n\t}\n\n\treturn _SUCCESS;\n\nasoc_class2_error:\n\n#ifdef CONFIG_NATIVEAP_MLME\n\tissue_deauth(padapter, (void *)get_addr2_ptr(pframe), status);\n#endif\n\n\treturn _FAIL;\n\nOnAssocReqFail:\n\n\n#ifdef CONFIG_NATIVEAP_MLME\n\tpstat->cmn.aid = 0;\n\tif (frame_type == WIFI_ASSOCREQ)\n\t\tissue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP);\n\telse\n\t\tissue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP);\n#endif\n\n\n#endif /* CONFIG_AP_MODE */\n\n\treturn _FAIL;\n\n}\n\n#if defined(CONFIG_LAYER2_ROAMING) && defined(CONFIG_RTW_80211K)\nvoid rtw_roam_nb_discover(_adapter *padapter, u8 bfroce)\n{\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\t\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct sta_info *psta;\n\tu8 nb_req_issue = _FALSE;\n\n\tif (!check_fwstate(pmlmepriv, _FW_LINKED))\n\t\treturn;\n\n\tif (!rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE))\n\t\treturn;\n\n\tpsta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);\n\tif (!psta)\n\t\treturn;\n\t\n\tif (bfroce || (!pmlmepriv->nb_info.nb_rpt_is_same))\n\t\tnb_req_issue = _TRUE;\n\t\n\tif (nb_req_issue && (psta->rm_en_cap[0] & RTW_RRM_NB_RPT_EN)) \n\t\trm_add_nb_req(padapter, psta);\n}\n#endif\n\nunsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tuint i;\n\tint res;\n\tunsigned short\tstatus;\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\t/* WLAN_BSSID_EX \t\t*cur_network = &(pmlmeinfo->network); */\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tuint pkt_len = precv_frame->u.hdr.len;\n#ifdef CONFIG_WAPI_SUPPORT\n\tPNDIS_802_11_VARIABLE_IEs\tpWapiIE = NULL;\n#endif\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\t/* check A1 matches or not */\n\tif (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN))\n\t\treturn _SUCCESS;\n\n\tif (!(pmlmeinfo->state & (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE)) || pmlmeext->join_abort)\n\t\treturn _SUCCESS;\n\n\tif (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)\n\t\treturn _SUCCESS;\n\n\t_cancel_timer_ex(&pmlmeext->link_timer);\n\n\t/* status */\n\tstatus = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 2));\n\tif (status > 0) {\n\t\tRTW_INFO(\"assoc reject, status code: %d\\n\", status);\n\t\tpmlmeinfo->state = WIFI_FW_NULL_STATE;\n\t\tres = -4;\n\t\tgoto report_assoc_result;\n\t}\n\n\t/* get capabilities */\n\tpmlmeinfo->capability = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));\n\n\t/* set slot time */\n\tpmlmeinfo->slotTime = (pmlmeinfo->capability & BIT(10)) ? 9 : 20;\n\n\t/* AID */\n\tres = pmlmeinfo->aid = (int)(le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 4)) & 0x3fff);\n\t\n\t/* check aid value */\n\tif (res < 1 || res > 2007) {\n\t\tRTW_INFO(\"assoc reject, aid: %d\\n\", res);\n\t\tpmlmeinfo->state = WIFI_FW_NULL_STATE;\n\t\tres = -4;\n\t\tgoto report_assoc_result;\n\t}\n\n\t/* following are moved to join event callback function */\n\t/* to handle HT, WMM, rate adaptive, update MAC reg */\n\t/* for not to handle the synchronous IO in the tasklet */\n\tfor (i = (6 + WLAN_HDR_A3_LEN); i < pkt_len;) {\n\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i);\n\n\t\tswitch (pIE->ElementID) {\n\t\tcase _VENDOR_SPECIFIC_IE_:\n\t\t\tif (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6))\t/* WMM */\n\t\t\t\tWMM_param_handler(padapter, pIE);\n#if defined(CONFIG_P2P) && defined(CONFIG_WFD)\n\t\t\telse if (_rtw_memcmp(pIE->data, WFD_OUI, 4))\t\t/* WFD */\n\t\t\t\trtw_process_wfd_ie(padapter, (u8 *)pIE, pIE->Length, __func__);\n#endif\n\t\t\tbreak;\n\n#ifdef CONFIG_WAPI_SUPPORT\n\t\tcase _WAPI_IE_:\n\t\t\tpWapiIE = pIE;\n\t\t\tbreak;\n#endif\n\n\t\tcase _HT_CAPABILITY_IE_:\t/* HT caps */\n\t\t\tHT_caps_handler(padapter, pIE);\n#ifdef ROKU_PRIVATE\n\t\t\tHT_caps_handler_infra_ap(padapter, pIE);\n#endif /* ROKU_PRIVATE */\n\t\t\tbreak;\n\n\t\tcase _HT_EXTRA_INFO_IE_:\t/* HT info */\n\t\t\tHT_info_handler(padapter, pIE);\n\t\t\tbreak;\n\n#ifdef CONFIG_80211AC_VHT\n\t\tcase EID_VHTCapability:\n\t\t\tVHT_caps_handler(padapter, pIE);\n#ifdef ROKU_PRIVATE\n\t\t\tVHT_caps_handler_infra_ap(padapter, pIE);\n#endif /* ROKU_PRIVATE */\n\t\t\tbreak;\n\n\t\tcase EID_VHTOperation:\n\t\t\tVHT_operation_handler(padapter, pIE);\n\t\t\tbreak;\n#endif\n\n\t\tcase _ERPINFO_IE_:\n\t\t\tERP_IE_handler(padapter, pIE);\n\t\t\tbreak;\n#ifdef CONFIG_TDLS\n\t\tcase _EXT_CAP_IE_:\n\t\t\tif (check_ap_tdls_prohibited(pIE->data, pIE->Length) == _TRUE)\n\t\t\t\tpadapter->tdlsinfo.ap_prohibited = _TRUE;\n\t\t\tif (check_ap_tdls_ch_switching_prohibited(pIE->data, pIE->Length) == _TRUE)\n\t\t\t\tpadapter->tdlsinfo.ch_switch_prohibited = _TRUE;\n\t\t\tbreak;\n#endif /* CONFIG_TDLS */\n\n#ifdef CONFIG_RTW_80211K\n\t\tcase _EID_RRM_EN_CAP_IE_:\n\t\t\tRM_IE_handler(padapter, pIE);\n\t\t\tbreak;\n#endif\n\n#ifdef ROKU_PRIVATE\n\t\t/* Infra mode, used to store AP's info , Parse the supported rates from AssocRsp */\n\t\tcase _SUPPORTEDRATES_IE_:\n\t\t\tSupported_rate_infra_ap(padapter, pIE);\n\t\t\tbreak;\n\n\t\tcase _EXT_SUPPORTEDRATES_IE_:\n\t\t\tExtended_Supported_rate_infra_ap(padapter, pIE);\n\t\t\tbreak;\n#endif /* ROKU_PRIVATE */\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\ti += (pIE->Length + 2);\n\t}\n\n#ifdef CONFIG_WAPI_SUPPORT\n\trtw_wapi_on_assoc_ok(padapter, pIE);\n#endif\n\n\tpmlmeinfo->state &= (~WIFI_FW_ASSOC_STATE);\n\tpmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;\n\n\t/* Update Basic Rate Table for spec, 2010-12-28 , by thomas */\n\tUpdateBrateTbl(padapter, pmlmeinfo->network.SupportedRates);\n\nreport_assoc_result:\n\tif (res > 0)\n\t\trtw_buf_update(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len, pframe, pkt_len);\n\telse\n\t\trtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len);\n\n\treport_join_res(padapter, res, status);\n\n#if defined(CONFIG_LAYER2_ROAMING) && defined(CONFIG_RTW_80211K)\n\trtw_roam_nb_discover(padapter, _TRUE);\n#endif\n\treturn _SUCCESS;\n}\n\nunsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tunsigned short\treason;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n#endif /* CONFIG_P2P */\n\n\t/* check A3 */\n\tif (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)))\n\t\treturn _SUCCESS;\n\n\tRTW_INFO(FUNC_ADPT_FMT\" - Start to Disconnect\\n\", FUNC_ADPT_ARG(padapter));\n\n#ifdef CONFIG_P2P\n\tif (pwdinfo->rx_invitereq_info.scan_op_ch_only) {\n\t\t_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);\n\t\t_set_timer(&pwdinfo->reset_ch_sitesurvey, 10);\n\t}\n#endif /* CONFIG_P2P */\n\n\treason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));\n\n#ifdef CONFIG_AP_MODE\n\tif (MLME_IS_AP(padapter)) {\n\t\t_irqL irqL;\n\t\tstruct sta_info *psta;\n\t\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\t\t/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\t\t */\n\t\t/* rtw_free_stainfo(padapter, psta); */\n\t\t/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\t\t */\n\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" reason=%u, ta=%pM\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe));\n\n\t\tpsta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));\n\t\tif (psta) {\n\t\t\tu8 updated = _FALSE;\n\n\t\t\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\t\t\tif (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {\n\t\t\t\trtw_list_delete(&psta->asoc_list);\n\t\t\t\tpstapriv->asoc_list_cnt--;\n\t\t\t\tupdated = ap_free_sta(padapter, psta, _FALSE, reason, _TRUE);\n\n\t\t\t}\n\t\t\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\t\t\tassociated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);\n\t\t}\n\n\n\t\treturn _SUCCESS;\n\t} else\n#endif\n\tif (!MLME_IS_MESH(padapter)) {\n\t\tint\tignore_received_deauth = 0;\n\n\t\t/*\tCommented by Albert 20130604 */\n\t\t/*\tBefore sending the auth frame to start the STA/GC mode connection with AP/GO,  */\n\t\t/*\twe will send the deauth first. */\n\t\t/*\tHowever, the Win8.1 with BRCM Wi-Fi will send the deauth with reason code 6 to us after receieving our deauth. */\n\t\t/*\tAdded the following code to avoid this case. */\n\t\tif ((pmlmeinfo->state & WIFI_FW_AUTH_STATE) ||\n\t\t    (pmlmeinfo->state & WIFI_FW_ASSOC_STATE)) {\n\t\t\tif (reason == WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA)\n\t\t\t\tignore_received_deauth = 1;\n\t\t\telse if (WLAN_REASON_PREV_AUTH_NOT_VALID == reason) {\n\t\t\t\t/* TODO: 802.11r */\n\t\t\t\tignore_received_deauth = 1;\n\t\t\t}\n\t\t}\n\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" reason=%u, ta=%pM, ignore=%d\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe), ignore_received_deauth);\n\n\t\tif (0 == ignore_received_deauth)\n\t\t\treceive_disconnect(padapter, get_addr2_ptr(pframe), reason, _FALSE);\n\t}\n\tpmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;\n\treturn _SUCCESS;\n\n}\n\nunsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tunsigned short\treason;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n#endif /* CONFIG_P2P */\n\n\t/* check A3 */\n\tif (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)))\n\t\treturn _SUCCESS;\n\n\tRTW_INFO(FUNC_ADPT_FMT\" - Start to Disconnect\\n\", FUNC_ADPT_ARG(padapter));\n\n#ifdef CONFIG_P2P\n\tif (pwdinfo->rx_invitereq_info.scan_op_ch_only) {\n\t\t_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);\n\t\t_set_timer(&pwdinfo->reset_ch_sitesurvey, 10);\n\t}\n#endif /* CONFIG_P2P */\n\n\treason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));\n\n#ifdef CONFIG_AP_MODE\n\tif (MLME_IS_AP(padapter)) {\n\t\t_irqL irqL;\n\t\tstruct sta_info *psta;\n\t\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\t\t/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\t */\n\t\t/* rtw_free_stainfo(padapter, psta); */\n\t\t/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\t\t */\n\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" reason=%u, ta=%pM\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe));\n\n\t\tpsta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));\n\t\tif (psta) {\n\t\t\tu8 updated = _FALSE;\n\n\t\t\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\t\t\tif (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {\n\t\t\t\trtw_list_delete(&psta->asoc_list);\n\t\t\t\tpstapriv->asoc_list_cnt--;\n\t\t\t\tupdated = ap_free_sta(padapter, psta, _FALSE, reason, _TRUE);\n\n\t\t\t}\n\t\t\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\t\t\tassociated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);\n\t\t}\n\n\t\treturn _SUCCESS;\n\t} else\n#endif\n\tif (!MLME_IS_MESH(padapter)) {\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" reason=%u, ta=%pM\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe));\n\n\t\treceive_disconnect(padapter, get_addr2_ptr(pframe), reason, _FALSE);\n\t}\n\tpmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;\n\treturn _SUCCESS;\n\n}\n\nunsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\treturn _SUCCESS;\n}\n\nunsigned int on_action_spct_ch_switch(_adapter *padapter, struct sta_info *psta, u8 *ies, uint ies_len)\n{\n\tunsigned int ret = _FAIL;\n\tstruct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(mlmeext->mlmext_info);\n\n\tif (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) {\n\t\tret = _SUCCESS;\n\t\tgoto exit;\n\t}\n\n\tif ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) {\n\n\t\tint ch_switch_mode = -1, ch = -1, ch_switch_cnt = -1;\n\t\tint ch_offset = -1;\n\t\tu8 bwmode;\n\t\tstruct ieee80211_info_element *ie;\n\n\t\tRTW_INFO(FUNC_NDEV_FMT\" from \"MAC_FMT\"\\n\",\n\t\t\tFUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(psta->cmn.mac_addr));\n\n\t\tfor_each_ie(ie, ies, ies_len) {\n\t\t\tif (ie->id == WLAN_EID_CHANNEL_SWITCH) {\n\t\t\t\tch_switch_mode = ie->data[0];\n\t\t\t\tch = ie->data[1];\n\t\t\t\tch_switch_cnt = ie->data[2];\n\t\t\t\tRTW_INFO(\"ch_switch_mode:%d, ch:%d, ch_switch_cnt:%d\\n\",\n\t\t\t\t\t ch_switch_mode, ch, ch_switch_cnt);\n\t\t\t} else if (ie->id == WLAN_EID_SECONDARY_CHANNEL_OFFSET) {\n\t\t\t\tch_offset = secondary_ch_offset_to_hal_ch_offset(ie->data[0]);\n\t\t\t\tRTW_INFO(\"ch_offset:%d\\n\", ch_offset);\n\t\t\t}\n\t\t}\n\n\t\tif (ch == -1)\n\t\t\treturn _SUCCESS;\n\n\t\tif (ch_offset == -1)\n\t\t\tbwmode = mlmeext->cur_bwmode;\n\t\telse\n\t\t\tbwmode = (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) ?\n\t\t\t\t CHANNEL_WIDTH_20 : CHANNEL_WIDTH_40;\n\n\t\tch_offset = (ch_offset == -1) ? mlmeext->cur_ch_offset : ch_offset;\n\n\t\t/* todo:\n\t\t * 1. the decision of channel switching\n\t\t * 2. things after channel switching\n\t\t */\n\n\t\tret = rtw_set_chbw_cmd(padapter, ch, bwmode, ch_offset, 0);\n\t}\n\nexit:\n\treturn ret;\n}\n\nunsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tunsigned int ret = _FAIL;\n\tstruct sta_info *psta = NULL;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tuint frame_len = precv_frame->u.hdr.len;\n\tu8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));\n\tu8 category;\n\tu8 action;\n\n\tpsta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));\n\n\tif (!psta)\n\t\tgoto exit;\n\n\tcategory = frame_body[0];\n\tif (category != RTW_WLAN_CATEGORY_SPECTRUM_MGMT)\n\t\tgoto exit;\n\n\taction = frame_body[1];\n\n\tRTW_INFO(FUNC_ADPT_FMT\" action:%u\\n\", FUNC_ADPT_ARG(padapter), action);\n\n\tswitch (action) {\n\tcase RTW_WLAN_ACTION_SPCT_MSR_REQ:\n\tcase RTW_WLAN_ACTION_SPCT_MSR_RPRT:\n\tcase RTW_WLAN_ACTION_SPCT_TPC_REQ:\n\tcase RTW_WLAN_ACTION_SPCT_TPC_RPRT:\n\t\tbreak;\n\tcase RTW_WLAN_ACTION_SPCT_CHL_SWITCH:\n#ifdef CONFIG_SPCT_CH_SWITCH\n\t\tret = on_action_spct_ch_switch(padapter, psta\n\t\t\t\t, frame_body + 2, frame_len - (frame_body - pframe) - 2);\n#elif defined(CONFIG_DFS)\n\t\tif (MLME_IS_STA(padapter) && MLME_IS_ASOC(padapter)) {\n\t\t\tprocess_csa_ie(padapter\n\t\t\t\t, frame_body + 2, frame_len - (frame_body - pframe) - 2);\n\t\t}\n#endif\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\nexit:\n\treturn ret;\n}\n\nunsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame)\n{\n\treturn _SUCCESS;\n}\n\nunsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame)\n{\n\treturn _SUCCESS;\n}\n\n#ifdef CONFIG_RTW_WNM\nunsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe)\n{\n\tunsigned int ret = _FAIL;\n\tstruct sta_info *sta = NULL;\n\tstruct mlme_priv *pmlmepriv = &(adapter->mlmepriv);\n\tstruct sta_priv *stapriv = &(adapter->stapriv);\n\tu8 *frame = rframe->u.hdr.rx_data;\n\tu32 frame_len = rframe->u.hdr.len;\n\tu8 *frame_body = (u8 *)(frame + sizeof(struct rtw_ieee80211_hdr_3addr));\n\tu32 frame_body_len = frame_len - sizeof(struct rtw_ieee80211_hdr_3addr);\t\n\tu8 category, action;\n\tint cnt = 0;\n\tchar msg[16];\n\n\tsta = rtw_get_stainfo(stapriv, get_addr2_ptr(frame));\n\tif (!sta)\n\t\tgoto exit;\n\n\tcategory = frame_body[0];\n\tif (category != RTW_WLAN_CATEGORY_WNM)\n\t\tgoto exit;\n\n\taction = frame_body[1];\n\n\tswitch (action) {\n#ifdef CONFIG_RTW_80211R\n\tcase RTW_WLAN_ACTION_WNM_BTM_REQ:\n\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {\n\t\t\tRTW_INFO(\"WNM: RTW_WLAN_ACTION_WNM_BTM_REQ recv.\\n\");\n\t\t\trtw_wnm_process_btm_req(adapter, frame_body, frame_body_len);\n\t\t}\n\t\tret = _SUCCESS;\n\t\tbreak;\n#endif\t\t\n\tdefault:\n\t\t#ifdef CONFIG_IOCTL_CFG80211\n\t\tcnt += sprintf((msg + cnt), \"ACT_WNM %u\", action);\n\t\trtw_cfg80211_rx_action(adapter, rframe, msg);\n\t\t#endif\n\t\tret = _SUCCESS;\n\t\tbreak;\n\t}\n\nexit:\n\treturn ret;\n}\n#endif /* CONFIG_RTW_WNM */\n\n/**\n * rtw_rx_ampdu_size - Get the target RX AMPDU buffer size for the specific @adapter\n * @adapter: the adapter to get target RX AMPDU buffer size\n *\n * Returns: the target RX AMPDU buffer size\n */\nu8 rtw_rx_ampdu_size(_adapter *adapter)\n{\n\tu8 size;\n\tHT_CAP_AMPDU_FACTOR max_rx_ampdu_factor;\n\n#ifdef CONFIG_BT_COEXIST\n\tif (rtw_btcoex_IsBTCoexCtrlAMPDUSize(adapter) == _TRUE) {\n\t\tsize = rtw_btcoex_GetAMPDUSize(adapter);\n\t\tgoto exit;\n\t}\n#endif\n\n\t/* for scan */\n\tif (!mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_DISABLE)\n\t    && !mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_COMPLETE)\n\t    && adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_size != RX_AMPDU_SIZE_INVALID\n\t   ) {\n\t\tsize = adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_size;\n\t\tgoto exit;\n\t}\n\n\t/* default value based on max_rx_ampdu_factor */\n\tif (adapter->driver_rx_ampdu_factor != 0xFF)\n\t\tmax_rx_ampdu_factor = (HT_CAP_AMPDU_FACTOR)adapter->driver_rx_ampdu_factor;\n\telse\n\t\trtw_hal_get_def_var(adapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor);\n\t\n\t/* In Maximum A-MPDU Length Exponent subfield of A-MPDU Parameters field of HT Capabilities element,\n\t\tthe unit of max_rx_ampdu_factor are octets. 8K, 16K, 32K, 64K is right.\n\t\tBut the buffer size subfield of Block Ack Parameter Set field in ADDBA action frame indicates\n\t\tthe number of buffers available for this particular TID. Each buffer is equal to max. size of \n\t\tMSDU or AMSDU. \n\t\tThe size variable means how many MSDUs or AMSDUs, it's not Kbytes.\n\t*/\n\tif (MAX_AMPDU_FACTOR_64K == max_rx_ampdu_factor)\n\t\tsize = 64;\n\telse if (MAX_AMPDU_FACTOR_32K == max_rx_ampdu_factor)\n\t\tsize = 32;\n\telse if (MAX_AMPDU_FACTOR_16K == max_rx_ampdu_factor)\n\t\tsize = 16;\n\telse if (MAX_AMPDU_FACTOR_8K == max_rx_ampdu_factor)\n\t\tsize = 8;\n\telse\n\t\tsize = 64;\n\nexit:\n\n\tif (size > 127)\n\t\tsize = 127;\n\n\treturn size;\n}\n\n/**\n * rtw_rx_ampdu_is_accept - Get the permission if RX AMPDU should be set up for the specific @adapter\n * @adapter: the adapter to get the permission if RX AMPDU should be set up\n *\n * Returns: accept or not\n */\nbool rtw_rx_ampdu_is_accept(_adapter *adapter)\n{\n\tbool accept;\n\n\tif (adapter->fix_rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID) {\n\t\taccept = adapter->fix_rx_ampdu_accept;\n\t\tgoto exit;\n\t}\n\n#ifdef CONFIG_BT_COEXIST\n\tif (rtw_btcoex_IsBTCoexRejectAMPDU(adapter) == _TRUE) {\n\t\taccept = _FALSE;\n\t\tgoto exit;\n\t}\n#endif\n\n\t/* for scan */\n\tif (!mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_DISABLE)\n\t    && !mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_COMPLETE)\n\t    && adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID\n\t   ) {\n\t\taccept = adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept;\n\t\tgoto exit;\n\t}\n\n\t/* default value for other cases */\n\taccept = adapter->mlmeextpriv.mlmext_info.bAcceptAddbaReq;\n\nexit:\n\treturn accept;\n}\n\n/**\n * rtw_rx_ampdu_set_size - Set the target RX AMPDU buffer size for the specific @adapter and specific @reason\n * @adapter: the adapter to set target RX AMPDU buffer size\n * @size: the target RX AMPDU buffer size to set\n * @reason: reason for the target RX AMPDU buffer size setting\n *\n * Returns: whether the target RX AMPDU buffer size is changed\n */\nbool rtw_rx_ampdu_set_size(_adapter *adapter, u8 size, u8 reason)\n{\n\tbool is_adj = _FALSE;\n\tstruct mlme_ext_priv *mlmeext;\n\tstruct mlme_ext_info *mlmeinfo;\n\n\tmlmeext = &adapter->mlmeextpriv;\n\tmlmeinfo = &mlmeext->mlmext_info;\n\n\tif (reason == RX_AMPDU_DRV_FIXED) {\n\t\tif (adapter->fix_rx_ampdu_size != size) {\n\t\t\tadapter->fix_rx_ampdu_size = size;\n\t\t\tis_adj = _TRUE;\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" fix_rx_ampdu_size:%u\\n\", FUNC_ADPT_ARG(adapter), size);\n\t\t}\n\t} else if (reason == RX_AMPDU_DRV_SCAN) {\n\t\tstruct ss_res *ss = &adapter->mlmeextpriv.sitesurvey_res;\n\n\t\tif (ss->rx_ampdu_size != size) {\n\t\t\tss->rx_ampdu_size = size;\n\t\t\tis_adj = _TRUE;\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" ss.rx_ampdu_size:%u\\n\", FUNC_ADPT_ARG(adapter), size);\n\t\t}\n\t}\n\n\treturn is_adj;\n}\n\n/**\n * rtw_rx_ampdu_set_accept - Set the permission if RX AMPDU should be set up for the specific @adapter and specific @reason\n * @adapter: the adapter to set if RX AMPDU should be set up\n * @accept: if RX AMPDU should be set up\n * @reason: reason for the permission if RX AMPDU should be set up\n *\n * Returns: whether the permission if RX AMPDU should be set up is changed\n */\nbool rtw_rx_ampdu_set_accept(_adapter *adapter, u8 accept, u8 reason)\n{\n\tbool is_adj = _FALSE;\n\tstruct mlme_ext_priv *mlmeext;\n\tstruct mlme_ext_info *mlmeinfo;\n\n\tmlmeext = &adapter->mlmeextpriv;\n\tmlmeinfo = &mlmeext->mlmext_info;\n\n\tif (reason == RX_AMPDU_DRV_FIXED) {\n\t\tif (adapter->fix_rx_ampdu_accept != accept) {\n\t\t\tadapter->fix_rx_ampdu_accept = accept;\n\t\t\tis_adj = _TRUE;\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" fix_rx_ampdu_accept:%u\\n\", FUNC_ADPT_ARG(adapter), accept);\n\t\t}\n\t} else if (reason == RX_AMPDU_DRV_SCAN) {\n\t\tif (adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept != accept) {\n\t\t\tadapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept = accept;\n\t\t\tis_adj = _TRUE;\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" ss.rx_ampdu_accept:%u\\n\", FUNC_ADPT_ARG(adapter), accept);\n\t\t}\n\t}\n\n\treturn is_adj;\n}\n\n/**\n * rx_ampdu_apply_sta_tid - Apply RX AMPDU setting to the specific @sta and @tid\n * @adapter: the adapter to which @sta belongs\n * @sta: the sta to be checked\n * @tid: the tid to be checked\n * @accept: the target permission if RX AMPDU should be set up\n * @size: the target RX AMPDU buffer size\n *\n * Returns:\n * 0: no canceled\n * 1: canceled by no permission\n * 2: canceled by different buffer size\n * 3: canceled by potential mismatched status\n *\n * Blocking function, may sleep\n */\nu8 rx_ampdu_apply_sta_tid(_adapter *adapter, struct sta_info *sta, u8 tid, u8 accept, u8 size)\n{\n\tu8 ret = 0;\n\tstruct recv_reorder_ctrl *reorder_ctl = &sta->recvreorder_ctrl[tid];\n\n\tif (reorder_ctl->enable == _FALSE) {\n\t\tif (reorder_ctl->ampdu_size != RX_AMPDU_SIZE_INVALID) {\n\t\t\tsend_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 1);\n\t\t\tret = 3;\n\t\t}\n\t\tgoto exit;\n\t}\n\n\tif (accept == _FALSE) {\n\t\tsend_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 0);\n\t\tret = 1;\n\t} else if (reorder_ctl->ampdu_size != size) {\n\t\tsend_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 0);\n\t\tret = 2;\n\t}\n\nexit:\n\treturn ret;\n}\n\nu8 rx_ampdu_size_sta_limit(_adapter *adapter, struct sta_info *sta)\n{\n\tu8 sz_limit = 0xFF;\n\n#ifdef CONFIG_80211N_HT\n\tstruct registry_priv *regsty = adapter_to_regsty(adapter);\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\tstruct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info;\n\ts8 nss = -1;\n\tu8 bw = rtw_min(sta->cmn.bw_mode, adapter->mlmeextpriv.cur_bwmode);\n\n\t#ifdef CONFIG_80211AC_VHT\n\tif (is_supported_vht(sta->wireless_mode)) {\n\t\tnss = rtw_min(rtw_vht_mcsmap_to_nss(mlme->vhtpriv.vht_mcs_map)\n\t\t\t\t, rtw_vht_mcsmap_to_nss(sta->vhtpriv.vht_mcs_map));\n\t} else\n\t#endif\n\tif (is_supported_ht(sta->wireless_mode)) {\n\t\tnss = rtw_min(rtw_ht_mcsset_to_nss(mlmeinfo->HT_caps.u.HT_cap_element.MCS_rate)\n\t\t\t\t, rtw_ht_mcsset_to_nss(sta->htpriv.ht_cap.supp_mcs_set));\n\t}\n\n\tif (nss >= 1)\n\t\tsz_limit = regsty->rx_ampdu_sz_limit_by_nss_bw[nss - 1][bw];\n#endif /* CONFIG_80211N_HT */\n\n\treturn sz_limit;\n}\n\n/**\n * rx_ampdu_apply_sta - Apply RX AMPDU setting to the specific @sta\n * @adapter: the adapter to which @sta belongs\n * @sta: the sta to be checked\n * @accept: the target permission if RX AMPDU should be set up\n * @size: the target RX AMPDU buffer size\n *\n * Returns: number of the RX AMPDU assciation canceled for applying current target setting\n *\n * Blocking function, may sleep\n */\nu8 rx_ampdu_apply_sta(_adapter *adapter, struct sta_info *sta, u8 accept, u8 size)\n{\n\tu8 change_cnt = 0;\n\tint i;\n\n\tfor (i = 0; i < TID_NUM; i++) {\n\t\tif (rx_ampdu_apply_sta_tid(adapter, sta, i, accept, size) != 0)\n\t\t\tchange_cnt++;\n\t}\n\n\treturn change_cnt;\n}\n\n/**\n * rtw_rx_ampdu_apply - Apply the current target RX AMPDU setting for the specific @adapter\n * @adapter: the adapter to be applied\n *\n * Returns: number of the RX AMPDU assciation canceled for applying current target setting\n */\nu16 rtw_rx_ampdu_apply(_adapter *adapter)\n{\n\tu16 adj_cnt = 0;\n\tstruct sta_info *sta;\n\tu8 accept = rtw_rx_ampdu_is_accept(adapter);\n\tu8 size;\n\n\tif (adapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID)\n\t\tsize = adapter->fix_rx_ampdu_size;\n\telse\n\t\tsize = rtw_rx_ampdu_size(adapter);\n\n\tif (MLME_IS_STA(adapter)) {\n\t\tsta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv));\n\t\tif (sta) {\n\t\t\tu8 sta_size = size;\n\n\t\t\tif (adapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID)\n\t\t\t\tsta_size = rtw_min(size, rx_ampdu_size_sta_limit(adapter, sta));\n\t\t\tadj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size);\n\t\t}\n\t\t/* TODO: TDLS peer */\n\n\t} else if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {\n\t\t_irqL irqL;\n\t\t_list *phead, *plist;\n\t\tu8 peer_num = 0;\n\t\tchar peers[NUM_STA];\n\t\tstruct sta_priv *pstapriv = &adapter->stapriv;\n\t\tint i;\n\n\t\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\t\tphead = &pstapriv->asoc_list;\n\t\tplist = get_next(phead);\n\n\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\tint stainfo_offset;\n\n\t\t\tsta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);\n\t\t\tplist = get_next(plist);\n\n\t\t\tstainfo_offset = rtw_stainfo_offset(pstapriv, sta);\n\t\t\tif (stainfo_offset_valid(stainfo_offset))\n\t\t\t\tpeers[peer_num++] = stainfo_offset;\n\t\t}\n\n\t\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\t\tfor (i = 0; i < peer_num; i++) {\n\t\t\tsta = rtw_get_stainfo_by_offset(pstapriv, peers[i]);\n\t\t\tif (sta) {\n\t\t\t\tu8 sta_size = size;\n\n\t\t\t\tif (adapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID)\n\t\t\t\t\tsta_size = rtw_min(size, rx_ampdu_size_sta_limit(adapter, sta));\n\t\t\t\tadj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size);\n\t\t\t}\n\t\t}\n\t}\n\n\t/* TODO: ADHOC */\n\n\treturn adj_cnt;\n}\n\nunsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tu8 *addr;\n\tstruct sta_info *psta = NULL;\n\tstruct recv_reorder_ctrl *preorder_ctrl;\n\tunsigned char\t\t*frame_body;\n\tunsigned char\t\tcategory, action;\n\tunsigned short\ttid, status, reason_code = 0;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct registry_priv *pregpriv = &padapter->registrypriv;\n\n#ifdef CONFIG_80211N_HT\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\t/* check RA matches or not\t */\n\tif (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))\n\t\treturn _SUCCESS;\n\n#if 0\n\t/* check A1 matches or not */\n\tif (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN))\n\t\treturn _SUCCESS;\n#endif\n\n\tif ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)\n\t\tif (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS))\n\t\t\treturn _SUCCESS;\n\n\taddr = get_addr2_ptr(pframe);\n\tpsta = rtw_get_stainfo(pstapriv, addr);\n\n\tif (psta == NULL)\n\t\treturn _SUCCESS;\n\n\tframe_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));\n\n\tcategory = frame_body[0];\n\tif (category == RTW_WLAN_CATEGORY_BACK) { /* representing Block Ack */\n#ifdef CONFIG_TDLS\n\t\tif ((psta->tdls_sta_state & TDLS_LINKED_STATE) &&\n\t\t    (psta->htpriv.ht_option == _TRUE) &&\n\t\t    (psta->htpriv.ampdu_enable == _TRUE))\n\t\t\tRTW_INFO(\"Recv [%s] from direc link\\n\", __FUNCTION__);\n\t\telse\n#endif /* CONFIG_TDLS */\n\t\t\tif (!pmlmeinfo->HT_enable)\n\t\t\t\treturn _SUCCESS;\n\n\t\taction = frame_body[1];\n\t\tRTW_INFO(\"%s, action=%d\\n\", __FUNCTION__, action);\n\t\tswitch (action) {\n\t\tcase RTW_WLAN_ACTION_ADDBA_REQ: /* ADDBA request */\n\n\t\t\t_rtw_memcpy(&(pmlmeinfo->ADDBA_req), &(frame_body[2]), sizeof(struct ADDBA_request));\n\t\t\t/* process_addba_req(padapter, (u8*)&(pmlmeinfo->ADDBA_req), GetAddr3Ptr(pframe)); */\n\t\t\tprocess_addba_req(padapter, (u8 *)&(pmlmeinfo->ADDBA_req), addr);\n\n\t\t\tbreak;\n\n\t\tcase RTW_WLAN_ACTION_ADDBA_RESP: /* ADDBA response */\n\n\t\t\t/* status = frame_body[3] | (frame_body[4] << 8); */ /* endian issue */\n\t\t\tstatus = RTW_GET_LE16(&frame_body[3]);\n\t\t\ttid = ((frame_body[5] >> 2) & 0x7);\n\t\t\tif (status == 0) {\n\t\t\t\t/* successful\t\t\t\t\t */\n\t\t\t\tRTW_INFO(\"agg_enable for TID=%d\\n\", tid);\n\t\t\t\tpsta->htpriv.agg_enable_bitmap |= 1 << tid;\n\t\t\t\tpsta->htpriv.candidate_tid_bitmap &= ~BIT(tid);\n\t\t\t\t/* amsdu in ampdu */\n\t\t\t\tif (pregpriv->tx_ampdu_amsdu == 0)\n\t\t\t\t\tpsta->htpriv.tx_amsdu_enable = _FALSE;\n\t\t\t\telse if (pregpriv->tx_ampdu_amsdu == 1)\n\t\t\t\t\tpsta->htpriv.tx_amsdu_enable = _TRUE;\n\t\t\t\telse {\n\t\t\t\t\tif (frame_body[5] & 1)\n\t\t\t\t\t\tpsta->htpriv.tx_amsdu_enable = _TRUE;\n\t\t\t\t}\n\t\t\t} else\n\t\t\t\tpsta->htpriv.agg_enable_bitmap &= ~BIT(tid);\n\n\t\t\tif (psta->state & WIFI_STA_ALIVE_CHK_STATE) {\n\t\t\t\tRTW_INFO(\"%s alive check - rx ADDBA response\\n\", __func__);\n\t\t\t\tpsta->htpriv.agg_enable_bitmap &= ~BIT(tid);\n\t\t\t\tpsta->expire_to = pstapriv->expire_to;\n\t\t\t\tpsta->state ^= WIFI_STA_ALIVE_CHK_STATE;\n\t\t\t}\n\n\t\t\t/* RTW_INFO(\"marc: ADDBA RSP: %x\\n\", pmlmeinfo->agg_enable_bitmap); */\n\t\t\tbreak;\n\n\t\tcase RTW_WLAN_ACTION_DELBA: /* DELBA */\n\t\t\tif ((frame_body[3] & BIT(3)) == 0) {\n\t\t\t\tpsta->htpriv.agg_enable_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf));\n\t\t\t\tpsta->htpriv.candidate_tid_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf));\n\n\t\t\t\t/* reason_code = frame_body[4] | (frame_body[5] << 8); */\n\t\t\t\treason_code = RTW_GET_LE16(&frame_body[4]);\n\t\t\t} else if ((frame_body[3] & BIT(3)) == BIT(3)) {\n\t\t\t\ttid = (frame_body[3] >> 4) & 0x0F;\n\n\t\t\t\tpreorder_ctrl = &psta->recvreorder_ctrl[tid];\n\t\t\t\tpreorder_ctrl->enable = _FALSE;\n\t\t\t\tpreorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID;\n\t\t\t}\n\n\t\t\tRTW_INFO(\"%s(): DELBA: %x(%x)\\n\", __FUNCTION__, pmlmeinfo->agg_enable_bitmap, reason_code);\n\t\t\t/* todo: how to notify the host while receiving DELETE BA */\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n#endif /* CONFIG_80211N_HT */\n\treturn _SUCCESS;\n}\n\n#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE\nu32 rtw_build_vendor_ie(_adapter *padapter , unsigned char **pframe , u8 mgmt_frame_tyte)\n{\n\tint vendor_ie_num = 0;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tu32 len = 0;\n\n\tfor (vendor_ie_num = 0 ; vendor_ie_num < WLAN_MAX_VENDOR_IE_NUM ; vendor_ie_num++) {\n\t\tif (pmlmepriv->vendor_ielen[vendor_ie_num] > 0 && pmlmepriv->vendor_ie_mask[vendor_ie_num] & mgmt_frame_tyte) {\n\t\t\t_rtw_memcpy(*pframe , pmlmepriv->vendor_ie[vendor_ie_num] , pmlmepriv->vendor_ielen[vendor_ie_num]);\n\t\t\t*pframe +=  pmlmepriv->vendor_ielen[vendor_ie_num];\n\t\t\tlen += pmlmepriv->vendor_ielen[vendor_ie_num];\n\t\t}\n\t}\n\n\treturn len;\n}\n#endif\n\n#ifdef CONFIG_P2P\nint get_reg_classes_full_count(struct p2p_channels *channel_list)\n{\n\tint cnt = 0;\n\tint i;\n\n\tfor (i = 0; i < channel_list->reg_classes; i++)\n\t\tcnt += channel_list->reg_class[i].channels;\n\n\treturn cnt;\n}\n\nvoid issue_p2p_GO_request(_adapter *padapter, u8 *raddr)\n{\n\tstruct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);\n\tunsigned char category = RTW_WLAN_CATEGORY_PUBLIC;\n\tu8\t\t\taction = P2P_PUB_ACTION_ACTION;\n\tu32\t\t\tp2poui = cpu_to_be32(P2POUI);\n\tu8\t\t\toui_subtype = P2P_GO_NEGO_REQ;\n\tu8\t\t\twpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };\n\tu8\t\t\twpsielen = 0, p2pielen = 0;\n\tu16\t\t\tlen_channellist_attr = 0;\n#ifdef CONFIG_WFD\n\tu32\t\t\t\t\twfdielen = 0;\n#endif\n\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn;\n\n\tRTW_INFO(\"[%s] In\\n\", __FUNCTION__);\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));\n\tpwdinfo->negotiation_dialog_token = 1;\t/*\tInitialize the dialog value */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &pwdinfo->negotiation_dialog_token, &(pattrib->pktlen));\n\n\n\n\t/*\tWPS Section */\n\twpsielen = 0;\n\t/*\tWPS OUI */\n\t*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);\n\twpsielen += 4;\n\n\t/*\tWPS version */\n\t/*\tType: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);\n\twpsielen += 2;\n\n\t/*\tLength: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);\n\twpsielen += 2;\n\n\t/*\tValue: */\n\twpsie[wpsielen++] = WPS_VERSION_1;\t/*\tVersion 1.0 */\n\n\t/*\tDevice Password ID */\n\t/*\tType: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);\n\twpsielen += 2;\n\n\t/*\tLength: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);\n\twpsielen += 2;\n\n\t/*\tValue: */\n\n\tif (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN)\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC);\n\telse if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN)\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);\n\telse if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC)\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC);\n\n\twpsielen += 2;\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);\n\n\n\t/*\tP2P IE Section. */\n\n\t/*\tP2P OUI */\n\tp2pielen = 0;\n\tp2pie[p2pielen++] = 0x50;\n\tp2pie[p2pielen++] = 0x6F;\n\tp2pie[p2pielen++] = 0x9A;\n\tp2pie[p2pielen++] = 0x09;\t/*\tWFA P2P v1.0 */\n\n\t/*\tCommented by Albert 20110306 */\n\t/*\tAccording to the P2P Specification, the group negoitation request frame should contain 9 P2P attributes */\n\t/*\t1. P2P Capability */\n\t/*\t2. Group Owner Intent */\n\t/*\t3. Configuration Timeout */\n\t/*\t4. Listen Channel */\n\t/*\t5. Extended Listen Timing */\n\t/*\t6. Intended P2P Interface Address */\n\t/*\t7. Channel List */\n\t/*\t8. P2P Device Info */\n\t/*\t9. Operating Channel */\n\n\n\t/*\tP2P Capability */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CAPABILITY;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tDevice Capability Bitmap, 1 byte */\n\tp2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;\n\n\t/*\tGroup Capability Bitmap, 1 byte */\n\tif (pwdinfo->persistent_supported)\n\t\tp2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;\n\telse\n\t\tp2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;\n\n\n\t/*\tGroup Owner Intent */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_GO_INTENT;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tTodo the tie breaker bit. */\n\tp2pie[p2pielen++] = ((pwdinfo->intent << 1) &  0xFE);\n\n\t/*\tConfiguration Timeout */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\tp2pie[p2pielen++] = 200;\t/*\t2 seconds needed to be the P2P GO */\n\tp2pie[p2pielen++] = 200;\t/*\t2 seconds needed to be the P2P Client */\n\n\n\t/*\tListen Channel */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_LISTEN_CH;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tCountry String */\n\tp2pie[p2pielen++] = 'X';\n\tp2pie[p2pielen++] = 'X';\n\n\t/*\tThe third byte should be set to 0x04. */\n\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\tp2pie[p2pielen++] = 0x04;\n\n\t/*\tOperating Class */\n\tp2pie[p2pielen++] = 0x51;\t/*\tCopy from SD7 */\n\n\t/*\tChannel Number */\n\tp2pie[p2pielen++] = pwdinfo->listen_channel;\t/*\tlistening channel number */\n\n\n\t/*\tExtended Listen Timing ATTR */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tAvailability Period */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);\n\tp2pielen += 2;\n\n\t/*\tAvailability Interval */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);\n\tp2pielen += 2;\n\n\n\t/*\tIntended P2P Interface Address */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);\n\tp2pielen += ETH_ALEN;\n\n\n\t/*\tChannel List */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CH_LIST;\n\n\t/* Length: */\n\t/* Country String(3) */\n\t/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */\n\t/* + number of channels in all classes */\n\tlen_channellist_attr = 3\n\t\t       + (1 + 1) * (u16)(ch_list->reg_classes)\n\t\t       + get_reg_classes_full_count(ch_list);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);\n\telse\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);\n#else\n\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);\n\n#endif\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tCountry String */\n\tp2pie[p2pielen++] = 'X';\n\tp2pie[p2pielen++] = 'X';\n\n\t/*\tThe third byte should be set to 0x04. */\n\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\tp2pie[p2pielen++] = 0x04;\n\n\t/*\tChannel Entry List */\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {\n\t\tu8 union_ch = rtw_mi_get_union_chan(padapter);\n\n\t\t/*\tOperating Class */\n\t\tif (union_ch > 14) {\n\t\t\tif (union_ch >= 149)\n\t\t\t\tp2pie[p2pielen++] = 0x7c;\n\t\t\telse\n\t\t\t\tp2pie[p2pielen++] = 0x73;\n\t\t} else\n\t\t\tp2pie[p2pielen++] = 0x51;\n\n\n\t\t/*\tNumber of Channels */\n\t\t/*\tJust support 1 channel and this channel is AP's channel */\n\t\tp2pie[p2pielen++] = 1;\n\n\t\t/*\tChannel List */\n\t\tp2pie[p2pielen++] = union_ch;\n\t} else\n#endif /* CONFIG_CONCURRENT_MODE */\n\t{\n\t\tint i, j;\n\t\tfor (j = 0; j < ch_list->reg_classes; j++) {\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].reg_class;\n\n\t\t\t/*\tNumber of Channels */\n\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].channels;\n\n\t\t\t/*\tChannel List */\n\t\t\tfor (i = 0; i < ch_list->reg_class[j].channels; i++)\n\t\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].channel[i];\n\t\t}\n\t}\n\n\t/*\tDevice Info */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\t21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */\n\t/*\t+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tP2P Device Address */\n\t_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);\n\tp2pielen += ETH_ALEN;\n\n\t/*\tConfig Method */\n\t/*\tThis field should be big endian. Noted by P2P specification. */\n\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm);\n\n\tp2pielen += 2;\n\n\t/*\tPrimary Device Type */\n\t/*\tCategory ID */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);\n\tp2pielen += 2;\n\n\t/*\tOUI */\n\t*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);\n\tp2pielen += 4;\n\n\t/*\tSub Category ID */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);\n\tp2pielen += 2;\n\n\t/*\tNumber of Secondary Device Types */\n\tp2pie[p2pielen++] = 0x00;\t/*\tNo Secondary Device Type List */\n\n\t/*\tDevice Name */\n\t/*\tType: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);\n\tp2pielen += 2;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len);\n\tp2pielen += pwdinfo->device_name_len;\n\n\n\t/*\tOperating Channel */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tCountry String */\n\tp2pie[p2pielen++] = 'X';\n\tp2pie[p2pielen++] = 'X';\n\n\t/*\tThe third byte should be set to 0x04. */\n\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\tp2pie[p2pielen++] = 0x04;\n\n\t/*\tOperating Class */\n\tif (pwdinfo->operating_channel <= 14) {\n\t\t/*\tOperating Class */\n\t\tp2pie[p2pielen++] = 0x51;\n\t} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {\n\t\t/*\tOperating Class */\n\t\tp2pie[p2pielen++] = 0x73;\n\t} else {\n\t\t/*\tOperating Class */\n\t\tp2pie[p2pielen++] = 0x7c;\n\t}\n\n\t/*\tChannel Number */\n\tp2pie[p2pielen++] = pwdinfo->operating_channel;\t/*\toperating channel number */\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);\n\n#ifdef CONFIG_WFD\n\twfdielen = build_nego_req_wfd_ie(pwdinfo, pframe);\n\tpframe += wfdielen;\n\tpattrib->pktlen += wfdielen;\n#endif\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(padapter, pmgntframe);\n\n\treturn;\n\n}\n\n\nvoid issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint len, u8 result)\n{\n\tstruct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);\n\tunsigned char category = RTW_WLAN_CATEGORY_PUBLIC;\n\tu8\t\t\taction = P2P_PUB_ACTION_ACTION;\n\tu32\t\t\tp2poui = cpu_to_be32(P2POUI);\n\tu8\t\t\toui_subtype = P2P_GO_NEGO_RESP;\n\tu8\t\t\twpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };\n\tu8\t\t\tp2pielen = 0;\n\tuint\t\t\twpsielen = 0;\n\tu16\t\t\twps_devicepassword_id = 0x0000;\n\tuint\t\t\twps_devicepassword_id_len = 0;\n\tu16\t\t\tlen_channellist_attr = 0;\n\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n#ifdef CONFIG_WFD\n\tu32\t\t\t\t\twfdielen = 0;\n#endif\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn;\n\n\tRTW_INFO(\"[%s] In, result = %d\\n\", __FUNCTION__,  result);\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));\n\tpwdinfo->negotiation_dialog_token = frame_body[7];\t/*\tThe Dialog Token of provisioning discovery request frame. */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen));\n\n\t/*\tCommented by Albert 20110328 */\n\t/*\tTry to get the device password ID from the WPS IE of group negotiation request frame */\n\t/*\tWiFi Direct test plan 5.1.15 */\n\trtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen);\n\trtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8 *) &wps_devicepassword_id, &wps_devicepassword_id_len);\n\twps_devicepassword_id = be16_to_cpu(wps_devicepassword_id);\n\n\t_rtw_memset(wpsie, 0x00, 255);\n\twpsielen = 0;\n\n\t/*\tWPS Section */\n\twpsielen = 0;\n\t/*\tWPS OUI */\n\t*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);\n\twpsielen += 4;\n\n\t/*\tWPS version */\n\t/*\tType: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);\n\twpsielen += 2;\n\n\t/*\tLength: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);\n\twpsielen += 2;\n\n\t/*\tValue: */\n\twpsie[wpsielen++] = WPS_VERSION_1;\t/*\tVersion 1.0 */\n\n\t/*\tDevice Password ID */\n\t/*\tType: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);\n\twpsielen += 2;\n\n\t/*\tLength: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);\n\twpsielen += 2;\n\n\t/*\tValue: */\n\tif (wps_devicepassword_id == WPS_DPID_USER_SPEC)\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);\n\telse if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC);\n\telse\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC);\n\twpsielen += 2;\n\n\t/*\tCommented by Kurt 20120113 */\n\t/*\tIf some device wants to do p2p handshake without sending prov_disc_req */\n\t/*\tWe have to get peer_req_cm from here. */\n\tif (_rtw_memcmp(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, \"000\", 3)) {\n\t\tif (wps_devicepassword_id == WPS_DPID_USER_SPEC)\n\t\t\t_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, \"dis\", 3);\n\t\telse if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)\n\t\t\t_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, \"pad\", 3);\n\t\telse\n\t\t\t_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, \"pbc\", 3);\n\t}\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);\n\n\n\t/*\tP2P IE Section. */\n\n\t/*\tP2P OUI */\n\tp2pielen = 0;\n\tp2pie[p2pielen++] = 0x50;\n\tp2pie[p2pielen++] = 0x6F;\n\tp2pie[p2pielen++] = 0x9A;\n\tp2pie[p2pielen++] = 0x09;\t/*\tWFA P2P v1.0 */\n\n\t/*\tCommented by Albert 20100908 */\n\t/*\tAccording to the P2P Specification, the group negoitation response frame should contain 9 P2P attributes */\n\t/*\t1. Status */\n\t/*\t2. P2P Capability */\n\t/*\t3. Group Owner Intent */\n\t/*\t4. Configuration Timeout */\n\t/*\t5. Operating Channel */\n\t/*\t6. Intended P2P Interface Address */\n\t/*\t7. Channel List */\n\t/*\t8. Device Info */\n\t/*\t9. Group ID\t( Only GO ) */\n\n\n\t/*\tToDo: */\n\n\t/*\tP2P Status */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_STATUS;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\tp2pie[p2pielen++] = result;\n\n\t/*\tP2P Capability */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CAPABILITY;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tDevice Capability Bitmap, 1 byte */\n\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {\n\t\t/*\tCommented by Albert 2011/03/08 */\n\t\t/*\tAccording to the P2P specification */\n\t\t/*\tif the sending device will be client, the P2P Capability should be reserved of group negotation response frame */\n\t\tp2pie[p2pielen++] = 0;\n\t} else {\n\t\t/*\tBe group owner or meet the error case */\n\t\tp2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;\n\t}\n\n\t/*\tGroup Capability Bitmap, 1 byte */\n\tif (pwdinfo->persistent_supported)\n\t\tp2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;\n\telse\n\t\tp2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;\n\n\t/*\tGroup Owner Intent */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_GO_INTENT;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\tif (pwdinfo->peer_intent & 0x01) {\n\t\t/*\tPeer's tie breaker bit is 1, our tie breaker bit should be 0 */\n\t\tp2pie[p2pielen++] = (pwdinfo->intent << 1);\n\t} else {\n\t\t/*\tPeer's tie breaker bit is 0, our tie breaker bit should be 1 */\n\t\tp2pie[p2pielen++] = ((pwdinfo->intent << 1) | BIT(0));\n\t}\n\n\n\t/*\tConfiguration Timeout */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\tp2pie[p2pielen++] = 200;\t/*\t2 seconds needed to be the P2P GO */\n\tp2pie[p2pielen++] = 200;\t/*\t2 seconds needed to be the P2P Client */\n\n\t/*\tOperating Channel */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tCountry String */\n\tp2pie[p2pielen++] = 'X';\n\tp2pie[p2pielen++] = 'X';\n\n\t/*\tThe third byte should be set to 0x04. */\n\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\tp2pie[p2pielen++] = 0x04;\n\n\t/*\tOperating Class */\n\tif (pwdinfo->operating_channel <= 14) {\n\t\t/*\tOperating Class */\n\t\tp2pie[p2pielen++] = 0x51;\n\t} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {\n\t\t/*\tOperating Class */\n\t\tp2pie[p2pielen++] = 0x73;\n\t} else {\n\t\t/*\tOperating Class */\n\t\tp2pie[p2pielen++] = 0x7c;\n\t}\n\n\t/*\tChannel Number */\n\tp2pie[p2pielen++] = pwdinfo->operating_channel;\t/*\toperating channel number */\n\n\t/*\tIntended P2P Interface Address\t */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);\n\tp2pielen += ETH_ALEN;\n\n\t/*\tChannel List */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CH_LIST;\n\n\t/* Country String(3) */\n\t/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */\n\t/* + number of channels in all classes */\n\tlen_channellist_attr = 3\n\t\t       + (1 + 1) * (u16)ch_list->reg_classes\n\t\t       + get_reg_classes_full_count(ch_list);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);\n\telse\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);\n#else\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);\n\n#endif\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tCountry String */\n\tp2pie[p2pielen++] = 'X';\n\tp2pie[p2pielen++] = 'X';\n\n\t/*\tThe third byte should be set to 0x04. */\n\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\tp2pie[p2pielen++] = 0x04;\n\n\t/*\tChannel Entry List */\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {\n\n\t\tu8 union_chan = rtw_mi_get_union_chan(padapter);\n\n\t\t/*Operating Class*/\n\t\tif (union_chan > 14) {\n\t\t\tif (union_chan >= 149)\n\t\t\t\tp2pie[p2pielen++] = 0x7c;\n\t\t\telse\n\t\t\t\tp2pie[p2pielen++] = 0x73;\n\n\t\t} else\n\t\t\tp2pie[p2pielen++] = 0x51;\n\n\t\t/*\tNumber of Channels\n\t\t\tJust support 1 channel and this channel is AP's channel*/\n\t\tp2pie[p2pielen++] = 1;\n\n\t\t/*Channel List*/\n\t\tp2pie[p2pielen++] = union_chan;\n\t} else\n#endif /* CONFIG_CONCURRENT_MODE */\n\t{\n\t\tint i, j;\n\t\tfor (j = 0; j < ch_list->reg_classes; j++) {\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].reg_class;\n\n\t\t\t/*\tNumber of Channels */\n\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].channels;\n\n\t\t\t/*\tChannel List */\n\t\t\tfor (i = 0; i < ch_list->reg_class[j].channels; i++)\n\t\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].channel[i];\n\t\t}\n\t}\n\n\t/*\tDevice Info */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\t21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */\n\t/*\t+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tP2P Device Address */\n\t_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);\n\tp2pielen += ETH_ALEN;\n\n\t/*\tConfig Method */\n\t/*\tThis field should be big endian. Noted by P2P specification. */\n\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm);\n\n\tp2pielen += 2;\n\n\t/*\tPrimary Device Type */\n\t/*\tCategory ID */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);\n\tp2pielen += 2;\n\n\t/*\tOUI */\n\t*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);\n\tp2pielen += 4;\n\n\t/*\tSub Category ID */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);\n\tp2pielen += 2;\n\n\t/*\tNumber of Secondary Device Types */\n\tp2pie[p2pielen++] = 0x00;\t/*\tNo Secondary Device Type List */\n\n\t/*\tDevice Name */\n\t/*\tType: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);\n\tp2pielen += 2;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len);\n\tp2pielen += pwdinfo->device_name_len;\n\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\t/*\tGroup ID Attribute */\n\t\t/*\tType: */\n\t\tp2pie[p2pielen++] = P2P_ATTR_GROUP_ID;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen);\n\t\tp2pielen += 2;\n\n\t\t/*\tValue: */\n\t\t/*\tp2P Device Address */\n\t\t_rtw_memcpy(p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN);\n\t\tp2pielen += ETH_ALEN;\n\n\t\t/*\tSSID */\n\t\t_rtw_memcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);\n\t\tp2pielen += pwdinfo->nego_ssidlen;\n\n\t}\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);\n\n#ifdef CONFIG_WFD\n\twfdielen = build_nego_resp_wfd_ie(pwdinfo, pframe);\n\tpframe += wfdielen;\n\tpattrib->pktlen += wfdielen;\n#endif\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(padapter, pmgntframe);\n\n\treturn;\n\n}\n\nvoid issue_p2p_GO_confirm(_adapter *padapter, u8 *raddr, u8 result)\n{\n\n\tunsigned char category = RTW_WLAN_CATEGORY_PUBLIC;\n\tu8\t\t\taction = P2P_PUB_ACTION_ACTION;\n\tu32\t\t\tp2poui = cpu_to_be32(P2POUI);\n\tu8\t\t\toui_subtype = P2P_GO_NEGO_CONF;\n\tu8\t\t\tp2pie[255] = { 0x00 };\n\tu8\t\t\tp2pielen = 0;\n\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n#ifdef CONFIG_WFD\n\tu32\t\t\t\t\twfdielen = 0;\n#endif\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn;\n\n\tRTW_INFO(\"[%s] In\\n\", __FUNCTION__);\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen));\n\n\n\n\t/*\tP2P IE Section. */\n\n\t/*\tP2P OUI */\n\tp2pielen = 0;\n\tp2pie[p2pielen++] = 0x50;\n\tp2pie[p2pielen++] = 0x6F;\n\tp2pie[p2pielen++] = 0x9A;\n\tp2pie[p2pielen++] = 0x09;\t/*\tWFA P2P v1.0 */\n\n\t/*\tCommented by Albert 20110306 */\n\t/*\tAccording to the P2P Specification, the group negoitation request frame should contain 5 P2P attributes */\n\t/*\t1. Status */\n\t/*\t2. P2P Capability */\n\t/*\t3. Operating Channel */\n\t/*\t4. Channel List */\n\t/*\t5. Group ID\t( if this WiFi is GO ) */\n\n\t/*\tP2P Status */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_STATUS;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\tp2pie[p2pielen++] = result;\n\n\t/*\tP2P Capability */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CAPABILITY;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tDevice Capability Bitmap, 1 byte */\n\tp2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;\n\n\t/*\tGroup Capability Bitmap, 1 byte */\n\tif (pwdinfo->persistent_supported)\n\t\tp2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;\n\telse\n\t\tp2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;\n\n\n\t/*\tOperating Channel */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tCountry String */\n\tp2pie[p2pielen++] = 'X';\n\tp2pie[p2pielen++] = 'X';\n\n\t/*\tThe third byte should be set to 0x04. */\n\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\tp2pie[p2pielen++] = 0x04;\n\n\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {\n\t\tif (pwdinfo->peer_operating_ch <= 14) {\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = 0x51;\n\t\t} else if ((pwdinfo->peer_operating_ch >= 36) && (pwdinfo->peer_operating_ch <= 48)) {\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = 0x73;\n\t\t} else {\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = 0x7c;\n\t\t}\n\n\t\tp2pie[p2pielen++] = pwdinfo->peer_operating_ch;\n\t} else {\n\t\tif (pwdinfo->operating_channel <= 14) {\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = 0x51;\n\t\t} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = 0x73;\n\t\t} else {\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = 0x7c;\n\t\t}\n\n\t\t/*\tChannel Number */\n\t\tp2pie[p2pielen++] = pwdinfo->operating_channel;\t\t/*\tUse the listen channel as the operating channel */\n\t}\n\n\n\t/*\tChannel List */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CH_LIST;\n\n\t*(u16 *)(p2pie + p2pielen) = 6;\n\tp2pielen += 2;\n\n\t/*\tCountry String */\n\tp2pie[p2pielen++] = 'X';\n\tp2pie[p2pielen++] = 'X';\n\n\t/*\tThe third byte should be set to 0x04. */\n\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\tp2pie[p2pielen++] = 0x04;\n\n\t/*\tValue: */\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {\n\t\tif (pwdinfo->peer_operating_ch <= 14) {\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = 0x51;\n\t\t} else if ((pwdinfo->peer_operating_ch >= 36) && (pwdinfo->peer_operating_ch <= 48)) {\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = 0x73;\n\t\t} else {\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = 0x7c;\n\t\t}\n\t\tp2pie[p2pielen++] = 1;\n\t\tp2pie[p2pielen++] = pwdinfo->peer_operating_ch;\n\t} else {\n\t\tif (pwdinfo->operating_channel <= 14) {\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = 0x51;\n\t\t} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = 0x73;\n\t\t} else {\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = 0x7c;\n\t\t}\n\n\t\t/*\tChannel Number */\n\t\tp2pie[p2pielen++] = 1;\n\t\tp2pie[p2pielen++] = pwdinfo->operating_channel;\t\t/*\tUse the listen channel as the operating channel */\n\t}\n\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\t/*\tGroup ID Attribute */\n\t\t/*\tType: */\n\t\tp2pie[p2pielen++] = P2P_ATTR_GROUP_ID;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen);\n\t\tp2pielen += 2;\n\n\t\t/*\tValue: */\n\t\t/*\tp2P Device Address */\n\t\t_rtw_memcpy(p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN);\n\t\tp2pielen += ETH_ALEN;\n\n\t\t/*\tSSID */\n\t\t_rtw_memcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);\n\t\tp2pielen += pwdinfo->nego_ssidlen;\n\t}\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);\n\n#ifdef CONFIG_WFD\n\twfdielen = build_nego_confirm_wfd_ie(pwdinfo, pframe);\n\tpframe += wfdielen;\n\tpattrib->pktlen += wfdielen;\n#endif\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(padapter, pmgntframe);\n\n\treturn;\n\n}\n\nvoid issue_p2p_invitation_request(_adapter *padapter, u8 *raddr)\n{\n\tstruct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);\n\tunsigned char category = RTW_WLAN_CATEGORY_PUBLIC;\n\tu8\t\t\taction = P2P_PUB_ACTION_ACTION;\n\tu32\t\t\tp2poui = cpu_to_be32(P2POUI);\n\tu8\t\t\toui_subtype = P2P_INVIT_REQ;\n\tu8\t\t\tp2pie[255] = { 0x00 };\n\tu8\t\t\tp2pielen = 0;\n\tu8\t\t\tdialogToken = 3;\n\tu16\t\t\tlen_channellist_attr = 0;\n#ifdef CONFIG_WFD\n\tu32\t\t\t\t\twfdielen = 0;\n#endif\n\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, raddr,  ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));\n\n\t/*\tP2P IE Section. */\n\n\t/*\tP2P OUI */\n\tp2pielen = 0;\n\tp2pie[p2pielen++] = 0x50;\n\tp2pie[p2pielen++] = 0x6F;\n\tp2pie[p2pielen++] = 0x9A;\n\tp2pie[p2pielen++] = 0x09;\t/*\tWFA P2P v1.0 */\n\n\t/*\tCommented by Albert 20101011 */\n\t/*\tAccording to the P2P Specification, the P2P Invitation request frame should contain 7 P2P attributes */\n\t/*\t1. Configuration Timeout */\n\t/*\t2. Invitation Flags */\n\t/*\t3. Operating Channel\t( Only GO ) */\n\t/*\t4. P2P Group BSSID\t( Should be included if I am the GO ) */\n\t/*\t5. Channel List */\n\t/*\t6. P2P Group ID */\n\t/*\t7. P2P Device Info */\n\n\t/*\tConfiguration Timeout */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\tp2pie[p2pielen++] = 200;\t/*\t2 seconds needed to be the P2P GO */\n\tp2pie[p2pielen++] = 200;\t/*\t2 seconds needed to be the P2P Client */\n\n\t/*\tInvitation Flags */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_INVITATION_FLAGS;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\tp2pie[p2pielen++] = P2P_INVITATION_FLAGS_PERSISTENT;\n\n\n\t/*\tOperating Channel */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tCountry String */\n\tp2pie[p2pielen++] = 'X';\n\tp2pie[p2pielen++] = 'X';\n\n\t/*\tThe third byte should be set to 0x04. */\n\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\tp2pie[p2pielen++] = 0x04;\n\n\t/*\tOperating Class */\n\tif (pwdinfo->invitereq_info.operating_ch <= 14)\n\t\tp2pie[p2pielen++] = 0x51;\n\telse if ((pwdinfo->invitereq_info.operating_ch >= 36) && (pwdinfo->invitereq_info.operating_ch <= 48))\n\t\tp2pie[p2pielen++] = 0x73;\n\telse\n\t\tp2pie[p2pielen++] = 0x7c;\n\n\t/*\tChannel Number */\n\tp2pie[p2pielen++] = pwdinfo->invitereq_info.operating_ch;\t/*\toperating channel number */\n\n\tif (_rtw_memcmp(adapter_mac_addr(padapter), pwdinfo->invitereq_info.go_bssid, ETH_ALEN)) {\n\t\t/*\tP2P Group BSSID */\n\t\t/*\tType: */\n\t\tp2pie[p2pielen++] = P2P_ATTR_GROUP_BSSID;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);\n\t\tp2pielen += 2;\n\n\t\t/*\tValue: */\n\t\t/*\tP2P Device Address for GO */\n\t\t_rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN);\n\t\tp2pielen += ETH_ALEN;\n\t}\n\n\t/*\tChannel List */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CH_LIST;\n\n\n\t/*\tLength: */\n\t/* Country String(3) */\n\t/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */\n\t/* + number of channels in all classes */\n\tlen_channellist_attr = 3\n\t\t       + (1 + 1) * (u16)ch_list->reg_classes\n\t\t       + get_reg_classes_full_count(ch_list);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);\n\telse\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);\n#else\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);\n#endif\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tCountry String */\n\tp2pie[p2pielen++] = 'X';\n\tp2pie[p2pielen++] = 'X';\n\n\t/*\tThe third byte should be set to 0x04. */\n\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\tp2pie[p2pielen++] = 0x04;\n\n\t/*\tChannel Entry List */\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {\n\t\tu8 union_ch =  rtw_mi_get_union_chan(padapter);\n\n\t\t/*\tOperating Class */\n\t\tif (union_ch > 14) {\n\t\t\tif (union_ch >= 149)\n\t\t\t\tp2pie[p2pielen++] = 0x7c;\n\t\t\telse\n\t\t\t\tp2pie[p2pielen++] = 0x73;\n\t\t} else\n\t\t\tp2pie[p2pielen++] = 0x51;\n\n\n\t\t/*\tNumber of Channels */\n\t\t/*\tJust support 1 channel and this channel is AP's channel */\n\t\tp2pie[p2pielen++] = 1;\n\n\t\t/*\tChannel List */\n\t\tp2pie[p2pielen++] = union_ch;\n\t} else\n#endif /* CONFIG_CONCURRENT_MODE */\n\t{\n\t\tint i, j;\n\t\tfor (j = 0; j < ch_list->reg_classes; j++) {\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].reg_class;\n\n\t\t\t/*\tNumber of Channels */\n\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].channels;\n\n\t\t\t/*\tChannel List */\n\t\t\tfor (i = 0; i < ch_list->reg_class[j].channels; i++)\n\t\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].channel[i];\n\t\t}\n\t}\n\n\n\t/*\tP2P Group ID */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_GROUP_ID;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(6 + pwdinfo->invitereq_info.ssidlen);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tP2P Device Address for GO */\n\t_rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN);\n\tp2pielen += ETH_ALEN;\n\n\t/*\tSSID */\n\t_rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_ssid, pwdinfo->invitereq_info.ssidlen);\n\tp2pielen += pwdinfo->invitereq_info.ssidlen;\n\n\n\t/*\tDevice Info */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\t21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */\n\t/*\t+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tP2P Device Address */\n\t_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);\n\tp2pielen += ETH_ALEN;\n\n\t/*\tConfig Method */\n\t/*\tThis field should be big endian. Noted by P2P specification. */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_DISPLAY);\n\tp2pielen += 2;\n\n\t/*\tPrimary Device Type */\n\t/*\tCategory ID */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);\n\tp2pielen += 2;\n\n\t/*\tOUI */\n\t*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);\n\tp2pielen += 4;\n\n\t/*\tSub Category ID */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);\n\tp2pielen += 2;\n\n\t/*\tNumber of Secondary Device Types */\n\tp2pie[p2pielen++] = 0x00;\t/*\tNo Secondary Device Type List */\n\n\t/*\tDevice Name */\n\t/*\tType: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);\n\tp2pielen += 2;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len);\n\tp2pielen += pwdinfo->device_name_len;\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);\n\n#ifdef CONFIG_WFD\n\twfdielen = build_invitation_req_wfd_ie(pwdinfo, pframe);\n\tpframe += wfdielen;\n\tpattrib->pktlen += wfdielen;\n#endif\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(padapter, pmgntframe);\n\n\treturn;\n\n}\n\nvoid issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken, u8 status_code)\n{\n\tstruct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);\n\tunsigned char category = RTW_WLAN_CATEGORY_PUBLIC;\n\tu8\t\t\taction = P2P_PUB_ACTION_ACTION;\n\tu32\t\t\tp2poui = cpu_to_be32(P2POUI);\n\tu8\t\t\toui_subtype = P2P_INVIT_RESP;\n\tu8\t\t\tp2pie[255] = { 0x00 };\n\tu8\t\t\tp2pielen = 0;\n\tu16\t\t\tlen_channellist_attr = 0;\n#ifdef CONFIG_WFD\n\tu32\t\t\t\t\twfdielen = 0;\n#endif\n\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, raddr,  ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));\n\n\t/*\tP2P IE Section. */\n\n\t/*\tP2P OUI */\n\tp2pielen = 0;\n\tp2pie[p2pielen++] = 0x50;\n\tp2pie[p2pielen++] = 0x6F;\n\tp2pie[p2pielen++] = 0x9A;\n\tp2pie[p2pielen++] = 0x09;\t/*\tWFA P2P v1.0 */\n\n\t/*\tCommented by Albert 20101005 */\n\t/*\tAccording to the P2P Specification, the P2P Invitation response frame should contain 5 P2P attributes */\n\t/*\t1. Status */\n\t/*\t2. Configuration Timeout */\n\t/*\t3. Operating Channel\t( Only GO ) */\n\t/*\t4. P2P Group BSSID\t( Only GO ) */\n\t/*\t5. Channel List */\n\n\t/*\tP2P Status */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_STATUS;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tWhen status code is P2P_STATUS_FAIL_INFO_UNAVAILABLE. */\n\t/*\tSent the event receiving the P2P Invitation Req frame to DMP UI. */\n\t/*\tDMP had to compare the MAC address to find out the profile. */\n\t/*\tSo, the WiFi driver will send the P2P_STATUS_FAIL_INFO_UNAVAILABLE to NB. */\n\t/*\tIf the UI found the corresponding profile, the WiFi driver sends the P2P Invitation Req */\n\t/*\tto NB to rebuild the persistent group. */\n\tp2pie[p2pielen++] = status_code;\n\n\t/*\tConfiguration Timeout */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\tp2pie[p2pielen++] = 200;\t/*\t2 seconds needed to be the P2P GO */\n\tp2pie[p2pielen++] = 200;\t/*\t2 seconds needed to be the P2P Client */\n\n\tif (status_code == P2P_STATUS_SUCCESS) {\n\t\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\t\t/*\tThe P2P Invitation request frame asks this Wi-Fi device to be the P2P GO */\n\t\t\t/*\tIn this case, the P2P Invitation response frame should carry the two more P2P attributes. */\n\t\t\t/*\tFirst one is operating channel attribute. */\n\t\t\t/*\tSecond one is P2P Group BSSID attribute. */\n\n\t\t\t/*\tOperating Channel */\n\t\t\t/*\tType: */\n\t\t\tp2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;\n\n\t\t\t/*\tLength: */\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);\n\t\t\tp2pielen += 2;\n\n\t\t\t/*\tValue: */\n\t\t\t/*\tCountry String */\n\t\t\tp2pie[p2pielen++] = 'X';\n\t\t\tp2pie[p2pielen++] = 'X';\n\n\t\t\t/*\tThe third byte should be set to 0x04. */\n\t\t\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\t\t\tp2pie[p2pielen++] = 0x04;\n\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = 0x51;\t/*\tCopy from SD7 */\n\n\t\t\t/*\tChannel Number */\n\t\t\tp2pie[p2pielen++] = pwdinfo->operating_channel;\t/*\toperating channel number */\n\n\n\t\t\t/*\tP2P Group BSSID */\n\t\t\t/*\tType: */\n\t\t\tp2pie[p2pielen++] = P2P_ATTR_GROUP_BSSID;\n\n\t\t\t/*\tLength: */\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);\n\t\t\tp2pielen += 2;\n\n\t\t\t/*\tValue: */\n\t\t\t/*\tP2P Device Address for GO */\n\t\t\t_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);\n\t\t\tp2pielen += ETH_ALEN;\n\n\t\t}\n\n\t\t/*\tChannel List */\n\t\t/*\tType: */\n\t\tp2pie[p2pielen++] = P2P_ATTR_CH_LIST;\n\n\t\t/*\tLength: */\n\t\t/* Country String(3) */\n\t\t/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */\n\t\t/* + number of channels in all classes */\n\t\tlen_channellist_attr = 3\n\t\t\t+ (1 + 1) * (u16)ch_list->reg_classes\n\t\t\t+ get_reg_classes_full_count(ch_list);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);\n\t\telse\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);\n#else\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);\n#endif\n\t\tp2pielen += 2;\n\n\t\t/*\tValue: */\n\t\t/*\tCountry String */\n\t\tp2pie[p2pielen++] = 'X';\n\t\tp2pie[p2pielen++] = 'X';\n\n\t\t/*\tThe third byte should be set to 0x04. */\n\t\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\t\tp2pie[p2pielen++] = 0x04;\n\n\t\t/*\tChannel Entry List */\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {\n\t\t\tu8 union_ch = rtw_mi_get_union_chan(padapter);\n\n\t\t\t/*\tOperating Class */\n\t\t\tif (union_ch > 14) {\n\t\t\t\tif (union_ch >= 149)\n\t\t\t\t\tp2pie[p2pielen++]  = 0x7c;\n\t\t\t\telse\n\t\t\t\t\tp2pie[p2pielen++] = 0x73;\n\t\t\t} else\n\t\t\t\tp2pie[p2pielen++] = 0x51;\n\n\n\t\t\t/*\tNumber of Channels */\n\t\t\t/*\tJust support 1 channel and this channel is AP's channel */\n\t\t\tp2pie[p2pielen++] = 1;\n\n\t\t\t/*\tChannel List */\n\t\t\tp2pie[p2pielen++] = union_ch;\n\t\t} else\n#endif /* CONFIG_CONCURRENT_MODE */\n\t\t{\n\t\t\tint i, j;\n\t\t\tfor (j = 0; j < ch_list->reg_classes; j++) {\n\t\t\t\t/*\tOperating Class */\n\t\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].reg_class;\n\n\t\t\t\t/*\tNumber of Channels */\n\t\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].channels;\n\n\t\t\t\t/*\tChannel List */\n\t\t\t\tfor (i = 0; i < ch_list->reg_class[j].channels; i++)\n\t\t\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].channel[i];\n\t\t\t}\n\t\t}\n\t}\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);\n\n#ifdef CONFIG_WFD\n\twfdielen = build_invitation_resp_wfd_ie(pwdinfo, pframe);\n\tpframe += wfdielen;\n\tpattrib->pktlen += wfdielen;\n#endif\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(padapter, pmgntframe);\n\n\treturn;\n\n}\n\nvoid issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8 *pdev_raddr)\n{\n\tunsigned char category = RTW_WLAN_CATEGORY_PUBLIC;\n\tu8\t\t\taction = P2P_PUB_ACTION_ACTION;\n\tu8\t\t\tdialogToken = 1;\n\tu32\t\t\tp2poui = cpu_to_be32(P2POUI);\n\tu8\t\t\toui_subtype = P2P_PROVISION_DISC_REQ;\n\tu8\t\t\twpsie[100] = { 0x00 };\n\tu8\t\t\twpsielen = 0;\n\tu32\t\t\tp2pielen = 0;\n#ifdef CONFIG_WFD\n\tu32\t\t\t\t\twfdielen = 0;\n#endif\n\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn;\n\n\tRTW_INFO(\"[%s] In\\n\", __FUNCTION__);\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, pdev_raddr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, pdev_raddr, ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));\n\n\tp2pielen = build_prov_disc_request_p2p_ie(pwdinfo, pframe, pssid, ussidlen, pdev_raddr);\n\n\tpframe += p2pielen;\n\tpattrib->pktlen += p2pielen;\n\n\twpsielen = 0;\n\t/*\tWPS OUI */\n\t*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);\n\twpsielen += 4;\n\n\t/*\tWPS version */\n\t/*\tType: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);\n\twpsielen += 2;\n\n\t/*\tLength: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);\n\twpsielen += 2;\n\n\t/*\tValue: */\n\twpsie[wpsielen++] = WPS_VERSION_1;\t/*\tVersion 1.0 */\n\n\t/*\tConfig Method */\n\t/*\tType: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);\n\twpsielen += 2;\n\n\t/*\tLength: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);\n\twpsielen += 2;\n\n\t/*\tValue: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->tx_prov_disc_info.wps_config_method_request);\n\twpsielen += 2;\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);\n\n\n#ifdef CONFIG_WFD\n\twfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe);\n\tpframe += wfdielen;\n\tpattrib->pktlen += wfdielen;\n#endif\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(padapter, pmgntframe);\n\n\treturn;\n\n}\n\n\nu8 is_matched_in_profilelist(u8 *peermacaddr, struct profile_info *profileinfo)\n{\n\tu8 i, match_result = 0;\n\n\tRTW_INFO(\"[%s] peermac = %.2X %.2X %.2X %.2X %.2X %.2X\\n\", __FUNCTION__,\n\t\tpeermacaddr[0], peermacaddr[1], peermacaddr[2], peermacaddr[3], peermacaddr[4], peermacaddr[5]);\n\n\tfor (i = 0; i < P2P_MAX_PERSISTENT_GROUP_NUM; i++, profileinfo++) {\n\t\tRTW_INFO(\"[%s] profileinfo_mac = %.2X %.2X %.2X %.2X %.2X %.2X\\n\", __FUNCTION__,\n\t\t\tprofileinfo->peermac[0], profileinfo->peermac[1], profileinfo->peermac[2], profileinfo->peermac[3], profileinfo->peermac[4], profileinfo->peermac[5]);\n\t\tif (_rtw_memcmp(peermacaddr, profileinfo->peermac, ETH_ALEN)) {\n\t\t\tmatch_result = 1;\n\t\t\tRTW_INFO(\"[%s] Match!\\n\", __FUNCTION__);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn match_result ;\n}\n\nvoid issue_probersp_p2p(_adapter *padapter, unsigned char *da)\n{\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tunsigned char\t\t\t\t\t*mac;\n\tstruct xmit_priv\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\t/* WLAN_BSSID_EX \t\t*cur_network = &(pmlmeinfo->network); */\n\tu16\t\t\t\t\tbeacon_interval = 100;\n\tu16\t\t\t\t\tcapInfo = 0;\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\tu8\t\t\t\t\twpsie[255] = { 0x00 };\n\tu32\t\t\t\t\twpsielen = 0, p2pielen = 0;\n#ifdef CONFIG_WFD\n\tu32\t\t\t\t\twfdielen = 0;\n#endif\n\n\t/* RTW_INFO(\"%s\\n\", __FUNCTION__); */\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\tif (IS_CCK_RATE(pattrib->rate)) {\n\t\t/* force OFDM 6M rate */\n\t\tpattrib->rate = MGN_6M;\n\t\tpattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G);\n\t}\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tmac = adapter_mac_addr(padapter);\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\t_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);\n\n\t/*\tUse the device address for BSSID field.\t */\n\t_rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(fctrl, WIFI_PROBERSP);\n\n\tpattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = pattrib->hdrlen;\n\tpframe += pattrib->hdrlen;\n\n\t/* timestamp will be inserted by hardware */\n\tpframe += 8;\n\tpattrib->pktlen += 8;\n\n\t/* beacon interval: 2 bytes */\n\t_rtw_memcpy(pframe, (unsigned char *) &beacon_interval, 2);\n\tpframe += 2;\n\tpattrib->pktlen += 2;\n\n\t/*\tcapability info: 2 bytes */\n\t/*\tESS and IBSS bits must be 0 (defined in the 3.1.2.1.1 of WiFi Direct Spec) */\n\tcapInfo |= cap_ShortPremble;\n\tcapInfo |= cap_ShortSlot;\n\n\t_rtw_memcpy(pframe, (unsigned char *) &capInfo, 2);\n\tpframe += 2;\n\tpattrib->pktlen += 2;\n\n\n\t/* SSID */\n\tpframe = rtw_set_ie(pframe, _SSID_IE_, 7, pwdinfo->p2p_wildcard_ssid, &pattrib->pktlen);\n\n\t/* supported rates... */\n\t/*\tUse the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) */\n\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen);\n\n\t/* DS parameter set */\n\tpframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&pwdinfo->listen_channel, &pattrib->pktlen);\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {\n\t\tif (pmlmepriv->wps_probe_resp_ie != NULL && pmlmepriv->p2p_probe_resp_ie != NULL) {\n\t\t\t/* WPS IE */\n\t\t\t_rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len);\n\t\t\tpattrib->pktlen += pmlmepriv->wps_probe_resp_ie_len;\n\t\t\tpframe += pmlmepriv->wps_probe_resp_ie_len;\n\n\t\t\t/* P2P IE */\n\t\t\t_rtw_memcpy(pframe, pmlmepriv->p2p_probe_resp_ie, pmlmepriv->p2p_probe_resp_ie_len);\n\t\t\tpattrib->pktlen += pmlmepriv->p2p_probe_resp_ie_len;\n\t\t\tpframe += pmlmepriv->p2p_probe_resp_ie_len;\n\t\t}\n\t} else\n#endif /* CONFIG_IOCTL_CFG80211\t\t */\n\t{\n\n\t\t/*\tTodo: WPS IE */\n\t\t/*\tNoted by Albert 20100907 */\n\t\t/*\tAccording to the WPS specification, all the WPS attribute is presented by Big Endian. */\n\n\t\twpsielen = 0;\n\t\t/*\tWPS OUI */\n\t\t*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);\n\t\twpsielen += 4;\n\n\t\t/*\tWPS version */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\twpsie[wpsielen++] = WPS_VERSION_1;\t/*\tVersion 1.0 */\n\n\t\t/*\tWiFi Simple Config State */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SIMPLE_CONF_STATE);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\twpsie[wpsielen++] = WPS_WSC_STATE_NOT_CONFIG;\t/*\tNot Configured. */\n\n\t\t/*\tResponse Type */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_RESP_TYPE);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\twpsie[wpsielen++] = WPS_RESPONSE_TYPE_8021X;\n\n\t\t/*\tUUID-E */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_UUID_E);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0010);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\tif (pwdinfo->external_uuid == 0) {\n\t\t\t_rtw_memset(wpsie + wpsielen, 0x0, 16);\n\t\t\t_rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN);\n\t\t} else\n\t\t\t_rtw_memcpy(wpsie + wpsielen, pwdinfo->uuid, 0x10);\n\t\twpsielen += 0x10;\n\n\t\t/*\tManufacturer */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MANUFACTURER);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0007);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\t_rtw_memcpy(wpsie + wpsielen, \"Realtek\", 7);\n\t\twpsielen += 7;\n\n\t\t/*\tModel Name */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NAME);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0006);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\t_rtw_memcpy(wpsie + wpsielen, \"8192CU\", 6);\n\t\twpsielen += 6;\n\n\t\t/*\tModel Number */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NUMBER);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\twpsie[wpsielen++] = 0x31;\t\t/*\tcharacter 1 */\n\n\t\t/*\tSerial Number */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SERIAL_NUMBER);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(ETH_ALEN);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\t_rtw_memcpy(wpsie + wpsielen, \"123456\" , ETH_ALEN);\n\t\twpsielen += ETH_ALEN;\n\n\t\t/*\tPrimary Device Type */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\t/*\tCategory ID */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);\n\t\twpsielen += 2;\n\n\t\t/*\tOUI */\n\t\t*(u32 *)(wpsie + wpsielen) = cpu_to_be32(WPSOUI);\n\t\twpsielen += 4;\n\n\t\t/*\tSub Category ID */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);\n\t\twpsielen += 2;\n\n\t\t/*\tDevice Name */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->device_name_len);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\t_rtw_memcpy(wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len);\n\t\twpsielen += pwdinfo->device_name_len;\n\n\t\t/*\tConfig Method */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->supported_wps_cm);\n\t\twpsielen += 2;\n\n\n\t\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);\n\n\n\t\tp2pielen = build_probe_resp_p2p_ie(pwdinfo, pframe);\n\t\tpframe += p2pielen;\n\t\tpattrib->pktlen += p2pielen;\n\t}\n\n#ifdef CONFIG_WFD\n\twfdielen = rtw_append_probe_resp_wfd_ie(padapter, pframe);\n\tpframe += wfdielen;\n\tpattrib->pktlen += wfdielen;\n#endif\n\n/* Vendor Specific IE */\n#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE\n\tpattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_P2P_PROBERESP_VENDOR_IE_BIT);\n#endif\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\n\tdump_mgntframe(padapter, pmgntframe);\n\n\treturn;\n\n}\n\nint _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack)\n{\n\tint ret = _FAIL;\n\tstruct xmit_frame\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t*pattrib;\n\tunsigned char\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t*fctrl;\n\tunsigned char\t\t\t*mac;\n\tstruct xmit_priv\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tu8\tbc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\tu8\t\t\t\t\twpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };\n\tu16\t\t\t\t\twpsielen = 0, p2pielen = 0;\n#ifdef CONFIG_WFD\n\tu32\t\t\t\t\twfdielen = 0;\n#endif\n\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\tif (IS_CCK_RATE(pattrib->rate)) {\n\t\t/* force OFDM 6M rate */\n\t\tpattrib->rate = MGN_6M;\n\t\tpattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G);\n\t}\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tmac = adapter_mac_addr(padapter);\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\tif (da) {\n\t\t_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);\n\t} else {\n\t\tif ((pwdinfo->p2p_info.scan_op_ch_only) || (pwdinfo->rx_invitereq_info.scan_op_ch_only)) {\n\t\t\t/*\tThis two flags will be set when this is only the P2P client mode. */\n\t\t\t_rtw_memcpy(pwlanhdr->addr1, pwdinfo->p2p_peer_interface_addr, ETH_ALEN);\n\t\t\t_rtw_memcpy(pwlanhdr->addr3, pwdinfo->p2p_peer_interface_addr, ETH_ALEN);\n\t\t} else {\n\t\t\t/*\tbroadcast probe request frame */\n\t\t\t_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);\n\t\t\t_rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN);\n\t\t}\n\t}\n\t_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_PROBEREQ);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ))\n\t\tpframe = rtw_set_ie(pframe, _SSID_IE_, pwdinfo->tx_prov_disc_info.ssid.SsidLength, pwdinfo->tx_prov_disc_info.ssid.Ssid, &(pattrib->pktlen));\n\telse\n\t\tpframe = rtw_set_ie(pframe, _SSID_IE_, P2P_WILDCARD_SSID_LEN, pwdinfo->p2p_wildcard_ssid, &(pattrib->pktlen));\n\t/*\tUse the OFDM rate in the P2P probe request frame. ( 6(B), 9(B), 12(B), 24(B), 36, 48, 54 ) */\n\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen);\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {\n\t\tif (pmlmepriv->wps_probe_req_ie != NULL && pmlmepriv->p2p_probe_req_ie != NULL) {\n\t\t\t/* WPS IE */\n\t\t\t_rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len);\n\t\t\tpattrib->pktlen += pmlmepriv->wps_probe_req_ie_len;\n\t\t\tpframe += pmlmepriv->wps_probe_req_ie_len;\n\n\t\t\t/* P2P IE */\n\t\t\t_rtw_memcpy(pframe, pmlmepriv->p2p_probe_req_ie, pmlmepriv->p2p_probe_req_ie_len);\n\t\t\tpattrib->pktlen += pmlmepriv->p2p_probe_req_ie_len;\n\t\t\tpframe += pmlmepriv->p2p_probe_req_ie_len;\n\t\t}\n\t} else\n#endif /* CONFIG_IOCTL_CFG80211 */\n\t{\n\n\t\t/*\tWPS IE */\n\t\t/*\tNoted by Albert 20110221 */\n\t\t/*\tAccording to the WPS specification, all the WPS attribute is presented by Big Endian. */\n\n\t\twpsielen = 0;\n\t\t/*\tWPS OUI */\n\t\t*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);\n\t\twpsielen += 4;\n\n\t\t/*\tWPS version */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\twpsie[wpsielen++] = WPS_VERSION_1;\t/*\tVersion 1.0 */\n\n\t\tif (pmlmepriv->wps_probe_req_ie == NULL) {\n\t\t\t/*\tUUID-E */\n\t\t\t/*\tType: */\n\t\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_UUID_E);\n\t\t\twpsielen += 2;\n\n\t\t\t/*\tLength: */\n\t\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0010);\n\t\t\twpsielen += 2;\n\n\t\t\t/*\tValue: */\n\t\t\tif (pwdinfo->external_uuid == 0) {\n\t\t\t\t_rtw_memset(wpsie + wpsielen, 0x0, 16);\n\t\t\t\t_rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN);\n\t\t\t} else\n\t\t\t\t_rtw_memcpy(wpsie + wpsielen, pwdinfo->uuid, 0x10);\n\t\t\twpsielen += 0x10;\n\n\t\t\t/*\tConfig Method */\n\t\t\t/*\tType: */\n\t\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);\n\t\t\twpsielen += 2;\n\n\t\t\t/*\tLength: */\n\t\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);\n\t\t\twpsielen += 2;\n\n\t\t\t/*\tValue: */\n\t\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->supported_wps_cm);\n\t\t\twpsielen += 2;\n\t\t}\n\n\t\t/*\tDevice Name */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->device_name_len);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\t_rtw_memcpy(wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len);\n\t\twpsielen += pwdinfo->device_name_len;\n\n\t\t/*\tPrimary Device Type */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\t/*\tCategory ID */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_RTK_WIDI);\n\t\twpsielen += 2;\n\n\t\t/*\tOUI */\n\t\t*(u32 *)(wpsie + wpsielen) = cpu_to_be32(WPSOUI);\n\t\twpsielen += 4;\n\n\t\t/*\tSub Category ID */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_RTK_DMP);\n\t\twpsielen += 2;\n\n\t\t/*\tDevice Password ID */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);\t/*\tRegistrar-specified */\n\t\twpsielen += 2;\n\n\t\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);\n\n\t\t/*\tP2P OUI */\n\t\tp2pielen = 0;\n\t\tp2pie[p2pielen++] = 0x50;\n\t\tp2pie[p2pielen++] = 0x6F;\n\t\tp2pie[p2pielen++] = 0x9A;\n\t\tp2pie[p2pielen++] = 0x09;\t/*\tWFA P2P v1.0 */\n\n\t\t/*\tCommented by Albert 20110221 */\n\t\t/*\tAccording to the P2P Specification, the probe request frame should contain 5 P2P attributes */\n\t\t/*\t1. P2P Capability */\n\t\t/*\t2. P2P Device ID if this probe request wants to find the specific P2P device */\n\t\t/*\t3. Listen Channel */\n\t\t/*\t4. Extended Listen Timing */\n\t\t/*\t5. Operating Channel if this WiFi is working as the group owner now */\n\n\t\t/*\tP2P Capability */\n\t\t/*\tType: */\n\t\tp2pie[p2pielen++] = P2P_ATTR_CAPABILITY;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);\n\t\tp2pielen += 2;\n\n\t\t/*\tValue: */\n\t\t/*\tDevice Capability Bitmap, 1 byte */\n\t\tp2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;\n\n\t\t/*\tGroup Capability Bitmap, 1 byte */\n\t\tif (pwdinfo->persistent_supported)\n\t\t\tp2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;\n\t\telse\n\t\t\tp2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT;\n\n\t\t/*\tListen Channel */\n\t\t/*\tType: */\n\t\tp2pie[p2pielen++] = P2P_ATTR_LISTEN_CH;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);\n\t\tp2pielen += 2;\n\n\t\t/*\tValue: */\n\t\t/*\tCountry String */\n\t\tp2pie[p2pielen++] = 'X';\n\t\tp2pie[p2pielen++] = 'X';\n\n\t\t/*\tThe third byte should be set to 0x04. */\n\t\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\t\tp2pie[p2pielen++] = 0x04;\n\n\t\t/*\tOperating Class */\n\t\tp2pie[p2pielen++] = 0x51;\t/*\tCopy from SD7 */\n\n\t\t/*\tChannel Number */\n\t\tp2pie[p2pielen++] = pwdinfo->listen_channel;\t/*\tlisten channel */\n\n\n\t\t/*\tExtended Listen Timing */\n\t\t/*\tType: */\n\t\tp2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004);\n\t\tp2pielen += 2;\n\n\t\t/*\tValue: */\n\t\t/*\tAvailability Period */\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);\n\t\tp2pielen += 2;\n\n\t\t/*\tAvailability Interval */\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);\n\t\tp2pielen += 2;\n\n\t\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\t\t/*\tOperating Channel (if this WiFi is working as the group owner now) */\n\t\t\t/*\tType: */\n\t\t\tp2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;\n\n\t\t\t/*\tLength: */\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);\n\t\t\tp2pielen += 2;\n\n\t\t\t/*\tValue: */\n\t\t\t/*\tCountry String */\n\t\t\tp2pie[p2pielen++] = 'X';\n\t\t\tp2pie[p2pielen++] = 'X';\n\n\t\t\t/*\tThe third byte should be set to 0x04. */\n\t\t\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\t\t\tp2pie[p2pielen++] = 0x04;\n\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = 0x51;\t/*\tCopy from SD7 */\n\n\t\t\t/*\tChannel Number */\n\t\t\tp2pie[p2pielen++] = pwdinfo->operating_channel;\t/*\toperating channel number */\n\n\t\t}\n\n\t\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);\n\n\t}\n\n#ifdef CONFIG_WFD\n\twfdielen = rtw_append_probe_req_wfd_ie(padapter, pframe);\n\tpframe += wfdielen;\n\tpattrib->pktlen += wfdielen;\n#endif\n\n/* Vendor Specific IE */\n#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE\n\tpattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_P2P_PROBEREQ_VENDOR_IE_BIT);\n#endif\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\n\tif (wait_ack)\n\t\tret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);\n\telse {\n\t\tdump_mgntframe(padapter, pmgntframe);\n\t\tret = _SUCCESS;\n\t}\n\nexit:\n\treturn ret;\n}\n\ninline void issue_probereq_p2p(_adapter *adapter, u8 *da)\n{\n\t_issue_probereq_p2p(adapter, da, _FALSE);\n}\n\n/*\n * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT\n * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX\n * try_cnt means the maximal TX count to try\n */\nint issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms)\n{\n\tint ret;\n\tint i = 0;\n\tsystime start = rtw_get_current_time();\n\n\tdo {\n\t\tret = _issue_probereq_p2p(adapter, da, wait_ms > 0 ? _TRUE : _FALSE);\n\n\t\ti++;\n\n\t\tif (RTW_CANNOT_RUN(adapter))\n\t\t\tbreak;\n\n\t\tif (i < try_cnt && wait_ms > 0 && ret == _FAIL)\n\t\t\trtw_msleep_os(wait_ms);\n\n\t} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));\n\n\tif (ret != _FAIL) {\n\t\tret = _SUCCESS;\n#ifndef DBG_XMIT_ACK\n\t\tgoto exit;\n#endif\n\t}\n\n\tif (try_cnt && wait_ms) {\n\t\tif (da)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" to \"MAC_FMT\", ch:%u%s, %d/%d in %u ms\\n\",\n\t\t\t\tFUNC_ADPT_ARG(adapter), MAC_ARG(da), rtw_get_oper_ch(adapter),\n\t\t\t\tret == _SUCCESS ? \", acked\" : \"\", i, try_cnt, rtw_get_passing_time_ms(start));\n\t\telse\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\", ch:%u%s, %d/%d in %u ms\\n\",\n\t\t\t\tFUNC_ADPT_ARG(adapter), rtw_get_oper_ch(adapter),\n\t\t\t\tret == _SUCCESS ? \", acked\" : \"\", i, try_cnt, rtw_get_passing_time_ms(start));\n\t}\nexit:\n\treturn ret;\n}\n\n#endif /* CONFIG_P2P */\n\ns32 rtw_action_public_decache(union recv_frame *rframe, u8 token_offset)\n{\n\t_adapter *adapter = rframe->u.hdr.adapter;\n\tstruct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv);\n\tu8 *frame = rframe->u.hdr.rx_data;\n\tu16 seq_ctrl = ((rframe->u.hdr.attrib.seq_num & 0xffff) << 4) | (rframe->u.hdr.attrib.frag_num & 0xf);\n\tu8 token = *(rframe->u.hdr.rx_data + sizeof(struct rtw_ieee80211_hdr_3addr) + token_offset);\n\n\tif (GetRetry(frame)) {\n\t\tif ((seq_ctrl == mlmeext->action_public_rxseq)\n\t\t    && (token == mlmeext->action_public_dialog_token)\n\t\t   ) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" seq_ctrl=0x%x, rxseq=0x%x, token:%d\\n\",\n\t\t\t\tFUNC_ADPT_ARG(adapter), seq_ctrl, mlmeext->action_public_rxseq, token);\n\t\t\treturn _FAIL;\n\t\t}\n\t}\n\n\t/* TODO: per sta seq & token */\n\tmlmeext->action_public_rxseq = seq_ctrl;\n\tmlmeext->action_public_dialog_token = token;\n\n\treturn _SUCCESS;\n}\n\nunsigned int on_action_public_p2p(union recv_frame *precv_frame)\n{\n\t_adapter *padapter = precv_frame->u.hdr.adapter;\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tuint len = precv_frame->u.hdr.len;\n\tu8 *frame_body;\n#ifdef CONFIG_P2P\n\tu8 *p2p_ie;\n\tu32\tp2p_ielen;\n\tstruct\twifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\tu8\tresult = P2P_STATUS_SUCCESS;\n\tu8\tempty_addr[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };\n\tu8 *merged_p2pie = NULL;\n\tu32 merged_p2p_ielen = 0;\n#endif /* CONFIG_P2P */\n\n\tframe_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));\n\n#ifdef CONFIG_P2P\n\t_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211)\n\t\trtw_cfg80211_rx_p2p_action_public(padapter, precv_frame);\n\telse\n#endif /* CONFIG_IOCTL_CFG80211 */\n\t{\n\t\t/*\tDo nothing if the driver doesn't enable the P2P function. */\n\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE))\n\t\t\treturn _SUCCESS;\n\n\t\tlen -= sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\t\tswitch (frame_body[6]) { /* OUI Subtype */\n\t\tcase P2P_GO_NEGO_REQ: {\n\t\t\tRTW_INFO(\"[%s] Got GO Nego Req Frame\\n\", __FUNCTION__);\n\t\t\t_rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info));\n\n\t\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ))\n\t\t\t\trtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));\n\n\t\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) {\n\t\t\t\t/*\tCommented by Albert 20110526 */\n\t\t\t\t/*\tIn this case, this means the previous nego fail doesn't be reset yet. */\n\t\t\t\t_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);\n\t\t\t\t/*\tRestore the previous p2p state */\n\t\t\t\trtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));\n\t\t\t\tRTW_INFO(\"[%s] Restore the previous p2p state to %d\\n\", __FUNCTION__, rtw_p2p_state(pwdinfo));\n\t\t\t}\n#ifdef CONFIG_CONCURRENT_MODE\n\t\t\tif (rtw_mi_buddy_check_fwstate(padapter, _FW_LINKED))\n\t\t\t\t_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);\n#endif /* CONFIG_CONCURRENT_MODE */\n\n\t\t\t/*\tCommented by Kurt 20110902 */\n\t\t\t/* Add if statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. */\n\t\t\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING))\n\t\t\t\trtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));\n\n\t\t\t/*\tCommented by Kurt 20120113 */\n\t\t\t/*\tGet peer_dev_addr here if peer doesn't issue prov_disc frame. */\n\t\t\tif (_rtw_memcmp(pwdinfo->rx_prov_disc_info.peerDevAddr, empty_addr, ETH_ALEN))\n\t\t\t\t_rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN);\n\n\t\t\tresult = process_p2p_group_negotation_req(pwdinfo, frame_body, len);\n\t\t\tissue_p2p_GO_response(padapter, get_addr2_ptr(pframe), frame_body, len, result);\n\n\t\t\t/*\tCommented by Albert 20110718 */\n\t\t\t/*\tNo matter negotiating or negotiation failure, the driver should set up the restore P2P state timer. */\n#ifdef CONFIG_CONCURRENT_MODE\n\t\t\t/*\tCommented by Albert 20120107 */\n\t\t\t_set_timer(&pwdinfo->restore_p2p_state_timer, 3000);\n#else /* CONFIG_CONCURRENT_MODE */\n\t\t\t_set_timer(&pwdinfo->restore_p2p_state_timer, 5000);\n#endif /* CONFIG_CONCURRENT_MODE */\n\t\t\tbreak;\n\t\t}\n\t\tcase P2P_GO_NEGO_RESP: {\n\t\t\tRTW_INFO(\"[%s] Got GO Nego Resp Frame\\n\", __FUNCTION__);\n\n\t\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) {\n\t\t\t\t/*\tCommented by Albert 20110425 */\n\t\t\t\t/*\tThe restore timer is enabled when issuing the nego request frame of rtw_p2p_connect function. */\n\t\t\t\t_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);\n\t\t\t\tpwdinfo->nego_req_info.benable = _FALSE;\n\t\t\t\tresult = process_p2p_group_negotation_resp(pwdinfo, frame_body, len);\n\t\t\t\tissue_p2p_GO_confirm(pwdinfo->padapter, get_addr2_ptr(pframe), result);\n\t\t\t\tif (P2P_STATUS_SUCCESS == result) {\n\t\t\t\t\tif (rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT) {\n\t\t\t\t\t\tpwdinfo->p2p_info.operation_ch[0] = pwdinfo->peer_operating_ch;\n#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH\n\t\t\t\t\t\tpwdinfo->p2p_info.operation_ch[1] = 1;\t/* Check whether GO is operating in channel 1; */\n\t\t\t\t\t\tpwdinfo->p2p_info.operation_ch[2] = 6;\t/* Check whether GO is operating in channel 6; */\n\t\t\t\t\t\tpwdinfo->p2p_info.operation_ch[3] = 11;\t/* Check whether GO is operating in channel 11; */\n#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */\n\t\t\t\t\t\tpwdinfo->p2p_info.scan_op_ch_only = 1;\n\t\t\t\t\t\t_set_timer(&pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH);\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\t/*\tReset the dialog token for group negotiation frames. */\n\t\t\t\tpwdinfo->negotiation_dialog_token = 1;\n\n\t\t\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL))\n\t\t\t\t\t_set_timer(&pwdinfo->restore_p2p_state_timer, 5000);\n\t\t\t} else\n\t\t\t\tRTW_INFO(\"[%s] Skipped GO Nego Resp Frame (p2p_state != P2P_STATE_GONEGO_ING)\\n\", __FUNCTION__);\n\n\t\t\tbreak;\n\t\t}\n\t\tcase P2P_GO_NEGO_CONF: {\n\t\t\tRTW_INFO(\"[%s] Got GO Nego Confirm Frame\\n\", __FUNCTION__);\n\t\t\tresult = process_p2p_group_negotation_confirm(pwdinfo, frame_body, len);\n\t\t\tif (P2P_STATUS_SUCCESS == result) {\n\t\t\t\tif (rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT) {\n\t\t\t\t\tpwdinfo->p2p_info.operation_ch[0] = pwdinfo->peer_operating_ch;\n#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH\n\t\t\t\t\tpwdinfo->p2p_info.operation_ch[1] = 1;\t/* Check whether GO is operating in channel 1; */\n\t\t\t\t\tpwdinfo->p2p_info.operation_ch[2] = 6;\t/* Check whether GO is operating in channel 6; */\n\t\t\t\t\tpwdinfo->p2p_info.operation_ch[3] = 11;\t/* Check whether GO is operating in channel 11; */\n#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */\n\t\t\t\t\tpwdinfo->p2p_info.scan_op_ch_only = 1;\n\t\t\t\t\t_set_timer(&pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH);\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t\tcase P2P_INVIT_REQ: {\n\t\t\t/*\tAdded by Albert 2010/10/05 */\n\t\t\t/*\tReceived the P2P Invite Request frame. */\n\n\t\t\tRTW_INFO(\"[%s] Got invite request frame!\\n\", __FUNCTION__);\n\t\t\tp2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen);\n\t\t\tif (p2p_ie) {\n\t\t\t\t/*\tParse the necessary information from the P2P Invitation Request frame. */\n\t\t\t\t/*\tFor example: The MAC address of sending this P2P Invitation Request frame. */\n\t\t\t\tu32\tattr_contentlen = 0;\n\t\t\t\tu8\tstatus_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;\n\t\t\t\tstruct group_id_info group_id;\n\t\t\t\tu8\tinvitation_flag = 0;\n\n\t\t\t\tmerged_p2p_ielen = rtw_get_p2p_merged_ies_len(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_);\n\n\t\t\t\tmerged_p2pie = rtw_zmalloc(merged_p2p_ielen + 2);\t/* 2 is for EID and Length */\n\t\t\t\tif (merged_p2pie == NULL) {\n\t\t\t\t\tRTW_INFO(\"[%s] Malloc p2p ie fail\\n\", __FUNCTION__);\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t\t_rtw_memset(merged_p2pie, 0x00, merged_p2p_ielen);\n\n\t\t\t\tmerged_p2p_ielen = rtw_p2p_merge_ies(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, merged_p2pie);\n\n\t\t\t\trtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_INVITATION_FLAGS, &invitation_flag, &attr_contentlen);\n\t\t\t\tif (attr_contentlen) {\n\n\t\t\t\t\trtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_BSSID, pwdinfo->p2p_peer_interface_addr, &attr_contentlen);\n\t\t\t\t\t/*\tCommented by Albert 20120510 */\n\t\t\t\t\t/*\tCopy to the pwdinfo->p2p_peer_interface_addr. */\n\t\t\t\t\t/*\tSo that the WFD UI ( or Sigma ) can get the peer interface address by using the following command. */\n\t\t\t\t\t/*\t#> iwpriv wlan0 p2p_get peer_ifa */\n\t\t\t\t\t/*\tAfter having the peer interface address, the sigma can find the correct conf file for wpa_supplicant. */\n\n\t\t\t\t\tif (attr_contentlen) {\n\t\t\t\t\t\tRTW_INFO(\"[%s] GO's BSSID = %.2X %.2X %.2X %.2X %.2X %.2X\\n\", __FUNCTION__,\n\t\t\t\t\t\t\tpwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1],\n\t\t\t\t\t\t\tpwdinfo->p2p_peer_interface_addr[2], pwdinfo->p2p_peer_interface_addr[3],\n\t\t\t\t\t\t\tpwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);\n\t\t\t\t\t}\n\n\t\t\t\t\tif (invitation_flag & P2P_INVITATION_FLAGS_PERSISTENT) {\n\t\t\t\t\t\t/*\tRe-invoke the persistent group. */\n\n\t\t\t\t\t\t_rtw_memset(&group_id, 0x00, sizeof(struct group_id_info));\n\t\t\t\t\t\trtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, (u8 *) &group_id, &attr_contentlen);\n\t\t\t\t\t\tif (attr_contentlen) {\n\t\t\t\t\t\t\tif (_rtw_memcmp(group_id.go_device_addr, adapter_mac_addr(padapter), ETH_ALEN)) {\n\t\t\t\t\t\t\t\t/*\tThe p2p device sending this p2p invitation request wants this Wi-Fi device to be the persistent GO. */\n\t\t\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_GO);\n\t\t\t\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);\n\t\t\t\t\t\t\t\tstatus_code = P2P_STATUS_SUCCESS;\n\t\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t\t/*\tThe p2p device sending this p2p invitation request wants to be the persistent GO. */\n\t\t\t\t\t\t\t\tif (is_matched_in_profilelist(pwdinfo->p2p_peer_interface_addr, &pwdinfo->profileinfo[0])) {\n\t\t\t\t\t\t\t\t\tu8 operatingch_info[5] = { 0x00 };\n\t\t\t\t\t\t\t\t\tif (rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info,\n\t\t\t\t\t\t\t\t\t\t&attr_contentlen)) {\n\t\t\t\t\t\t\t\t\t\tif (rtw_chset_search_ch(adapter_to_chset(padapter), (u32)operatingch_info[4]) >= 0) {\n\t\t\t\t\t\t\t\t\t\t\t/*\tThe operating channel is acceptable for this device. */\n\t\t\t\t\t\t\t\t\t\t\tpwdinfo->rx_invitereq_info.operation_ch[0] = operatingch_info[4];\n#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH\n\t\t\t\t\t\t\t\t\t\t\tpwdinfo->rx_invitereq_info.operation_ch[1] = 1;\t\t/* Check whether GO is operating in channel 1; */\n\t\t\t\t\t\t\t\t\t\t\tpwdinfo->rx_invitereq_info.operation_ch[2] = 6;\t\t/* Check whether GO is operating in channel 6; */\n\t\t\t\t\t\t\t\t\t\t\tpwdinfo->rx_invitereq_info.operation_ch[3] = 11;\t\t/* Check whether GO is operating in channel 11; */\n#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */\n\t\t\t\t\t\t\t\t\t\t\tpwdinfo->rx_invitereq_info.scan_op_ch_only = 1;\n\t\t\t\t\t\t\t\t\t\t\t_set_timer(&pwdinfo->reset_ch_sitesurvey, P2P_RESET_SCAN_CH);\n\t\t\t\t\t\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH);\n\t\t\t\t\t\t\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);\n\t\t\t\t\t\t\t\t\t\t\tstatus_code = P2P_STATUS_SUCCESS;\n\t\t\t\t\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t\t\t\t\t/*\tThe operating channel isn't supported by this device. */\n\t\t\t\t\t\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH);\n\t\t\t\t\t\t\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);\n\t\t\t\t\t\t\t\t\t\t\tstatus_code = P2P_STATUS_FAIL_NO_COMMON_CH;\n\t\t\t\t\t\t\t\t\t\t\t_set_timer(&pwdinfo->restore_p2p_state_timer, 3000);\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t\t\t\t/*\tCommented by Albert 20121130 */\n\t\t\t\t\t\t\t\t\t\t/*\tIntel will use the different P2P IE to store the operating channel information */\n\t\t\t\t\t\t\t\t\t\t/*\tWorkaround for Intel WiDi 3.5 */\n\t\t\t\t\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH);\n\t\t\t\t\t\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);\n\t\t\t\t\t\t\t\t\t\tstatus_code = P2P_STATUS_SUCCESS;\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH);\n\t\t\t\t\t\t\t\t\tstatus_code = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP;\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tRTW_INFO(\"[%s] P2P Group ID Attribute NOT FOUND!\\n\", __FUNCTION__);\n\t\t\t\t\t\t\tstatus_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;\n\t\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\t/*\tReceived the invitation to join a P2P group. */\n\n\t\t\t\t\t\t_rtw_memset(&group_id, 0x00, sizeof(struct group_id_info));\n\t\t\t\t\t\trtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, (u8 *) &group_id, &attr_contentlen);\n\t\t\t\t\t\tif (attr_contentlen) {\n\t\t\t\t\t\t\tif (_rtw_memcmp(group_id.go_device_addr, adapter_mac_addr(padapter), ETH_ALEN)) {\n\t\t\t\t\t\t\t\t/*\tIn this case, the GO can't be myself. */\n\t\t\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH);\n\t\t\t\t\t\t\t\tstatus_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;\n\t\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t\t/*\tThe p2p device sending this p2p invitation request wants to join an existing P2P group */\n\t\t\t\t\t\t\t\t/*\tCommented by Albert 2012/06/28 */\n\t\t\t\t\t\t\t\t/*\tIn this case, this Wi-Fi device should use the iwpriv command to get the peer device address. */\n\t\t\t\t\t\t\t\t/*\tThe peer device address should be the destination address for the provisioning discovery request. */\n\t\t\t\t\t\t\t\t/*\tThen, this Wi-Fi device should use the iwpriv command to get the peer interface address. */\n\t\t\t\t\t\t\t\t/*\tThe peer interface address should be the address for WPS mac address */\n\t\t\t\t\t\t\t\t_rtw_memcpy(pwdinfo->p2p_peer_device_addr, group_id.go_device_addr , ETH_ALEN);\n\t\t\t\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);\n\t\t\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_JOIN);\n\t\t\t\t\t\t\t\tstatus_code = P2P_STATUS_SUCCESS;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tRTW_INFO(\"[%s] P2P Group ID Attribute NOT FOUND!\\n\", __FUNCTION__);\n\t\t\t\t\t\t\tstatus_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tRTW_INFO(\"[%s] P2P Invitation Flags Attribute NOT FOUND!\\n\", __FUNCTION__);\n\t\t\t\t\tstatus_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;\n\t\t\t\t}\n\n\t\t\t\tRTW_INFO(\"[%s] status_code = %d\\n\", __FUNCTION__, status_code);\n\n\t\t\t\tpwdinfo->inviteresp_info.token = frame_body[7];\n\t\t\t\tissue_p2p_invitation_response(padapter, get_addr2_ptr(pframe), pwdinfo->inviteresp_info.token, status_code);\n\t\t\t\t_set_timer(&pwdinfo->restore_p2p_state_timer, 3000);\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t\tcase P2P_INVIT_RESP: {\n\t\t\tu8\tattr_content = 0x00;\n\t\t\tu32\tattr_contentlen = 0;\n\n\t\t\tRTW_INFO(\"[%s] Got invite response frame!\\n\", __FUNCTION__);\n\t\t\t_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);\n\t\t\tp2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen);\n\t\t\tif (p2p_ie) {\n\t\t\t\trtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen);\n\n\t\t\t\tif (attr_contentlen == 1) {\n\t\t\t\t\tRTW_INFO(\"[%s] Status = %d\\n\", __FUNCTION__, attr_content);\n\t\t\t\t\tpwdinfo->invitereq_info.benable = _FALSE;\n\n\t\t\t\t\tif (attr_content == P2P_STATUS_SUCCESS) {\n\t\t\t\t\t\tif (_rtw_memcmp(pwdinfo->invitereq_info.go_bssid, adapter_mac_addr(padapter), ETH_ALEN))\n\t\t\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);\n\n\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_OK);\n\t\t\t\t\t} else {\n\t\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);\n\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL);\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);\n\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL);\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);\n\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL);\n\t\t\t}\n\n\t\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL))\n\t\t\t\t_set_timer(&pwdinfo->restore_p2p_state_timer, 5000);\n\t\t\tbreak;\n\t\t}\n\t\tcase P2P_DEVDISC_REQ:\n\n\t\t\tprocess_p2p_devdisc_req(pwdinfo, pframe, len);\n\n\t\t\tbreak;\n\n\t\tcase P2P_DEVDISC_RESP:\n\n\t\t\tprocess_p2p_devdisc_resp(pwdinfo, pframe, len);\n\n\t\t\tbreak;\n\n\t\tcase P2P_PROVISION_DISC_REQ:\n\t\t\tRTW_INFO(\"[%s] Got Provisioning Discovery Request Frame\\n\", __FUNCTION__);\n\t\t\tprocess_p2p_provdisc_req(pwdinfo, pframe, len);\n\t\t\t_rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN);\n\n\t\t\t/* 20110902 Kurt */\n\t\t\t/* Add the following statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. */\n\t\t\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ))\n\t\t\t\trtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));\n\n\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ);\n\t\t\t_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT);\n\t\t\tbreak;\n\n\t\tcase P2P_PROVISION_DISC_RESP:\n\t\t\t/*\tCommented by Albert 20110707 */\n\t\t\t/*\tShould we check the pwdinfo->tx_prov_disc_info.bsent flag here?? */\n\t\t\tRTW_INFO(\"[%s] Got Provisioning Discovery Response Frame\\n\", __FUNCTION__);\n\t\t\t/*\tCommented by Albert 20110426 */\n\t\t\t/*\tThe restore timer is enabled when issuing the provisioing request frame in rtw_p2p_prov_disc function. */\n\t\t\t_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);\n\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP);\n\t\t\tprocess_p2p_provdisc_resp(pwdinfo, pframe);\n\t\t\t_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT);\n\t\t\tbreak;\n\n\t\t}\n\t}\n\n\nexit:\n\n\tif (merged_p2pie)\n\t\trtw_mfree(merged_p2pie, merged_p2p_ielen + 2);\n#endif /* CONFIG_P2P */\n\treturn _SUCCESS;\n}\n\nunsigned int on_action_public_vendor(union recv_frame *precv_frame)\n{\n\tunsigned int ret = _FAIL;\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tu8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tif (_rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE) {\n\t\tif (rtw_action_public_decache(precv_frame, 7) == _FAIL)\n\t\t\tgoto exit;\n\n\t\tif (!hal_chk_wl_func(precv_frame->u.hdr.adapter, WL_FUNC_MIRACAST))\n\t\t\trtw_rframe_del_wfd_ie(precv_frame, 8);\n\n\t\tret = on_action_public_p2p(precv_frame);\n\t}\n\nexit:\n\treturn ret;\n}\n\nunsigned int on_action_public_default(union recv_frame *precv_frame, u8 action)\n{\n\tunsigned int ret = _FAIL;\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tu8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);\n\tu8 token;\n\t_adapter *adapter = precv_frame->u.hdr.adapter;\n\tint cnt = 0;\n\tchar msg[64];\n\n\ttoken = frame_body[2];\n\n\tif (rtw_action_public_decache(precv_frame, 2) == _FAIL)\n\t\tgoto exit;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tcnt += sprintf((msg + cnt), \"%s(token:%u)\", action_public_str(action), token);\n\trtw_cfg80211_rx_action(adapter, precv_frame, msg);\n#endif\n\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n\nunsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tunsigned int ret = _FAIL;\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tuint frame_len = precv_frame->u.hdr.len;\n\tu8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);\n\tu8 category, action;\n\n\t/* check RA matches or not */\n\tif (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))\n\t\tgoto exit;\n\n\tcategory = frame_body[0];\n\tif (category != RTW_WLAN_CATEGORY_PUBLIC)\n\t\tgoto exit;\n\n\taction = frame_body[1];\n\tswitch (action) {\n\tcase ACT_PUBLIC_BSSCOEXIST:\n#ifdef CONFIG_80211N_HT\n#ifdef CONFIG_AP_MODE\n\t\t/*20/40 BSS Coexistence Management frame is a Public Action frame*/\n\t\tif (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)\n\t\t\trtw_process_public_act_bsscoex(padapter, pframe, frame_len);\n#endif /*CONFIG_AP_MODE*/\n#endif /*CONFIG_80211N_HT*/\n\t\tbreak;\n\tcase ACT_PUBLIC_VENDOR:\n\t\tret = on_action_public_vendor(precv_frame);\n\t\tbreak;\n\tdefault:\n\t\tret = on_action_public_default(precv_frame, action);\n\t\tbreak;\n\t}\n\nexit:\n\treturn ret;\n}\n\n#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)\nstatic u8 rtw_wnm_nb_elem_parsing(\n\tu8* pdata, u32 data_len, u8 from_btm, \n\tu32 *nb_rpt_num, u8 *nb_rpt_is_same,\n\tstruct roam_nb_info *pnb, struct wnm_btm_cant *pcandidates)\n{\n\tu8 bfound = _FALSE, ret = _SUCCESS;\n\tu8 *ptr, *pend, *op;\n\tu32 elem_len, subelem_len, op_len;\n\tu32 i, nb_rpt_entries = 0;\n\tstruct nb_rpt_hdr *pie;\n\tstruct wnm_btm_cant *pcandidate;\n\n\tif ((!pdata) || (!pnb))\n\t\treturn _FAIL;\n\n\tif ((from_btm) && (!pcandidates))\n\t\treturn _FAIL;\n\n\tptr = pdata;\n\tpend = ptr + data_len;\n\telem_len = data_len;\n\tsubelem_len = (u32)*(pdata+1);\n\n\tfor (i=0; i < RTW_MAX_NB_RPT_NUM; i++) {\n\t\tif (((ptr + 7) > pend) || (elem_len < subelem_len)) \n\t\t\tbreak;\n\n\t\tif (*ptr != 0x34) {\n\t\t\tRTW_ERR(\"WNM: invalid data(0x%2x)!\\n\", *ptr);\n\t\t\tret = _FAIL;\n\t\t\tbreak;\n\t\t}\n\n\t\tpie = (struct nb_rpt_hdr *)ptr;\t\t\n\t\tif (from_btm) {\n\t\t\top = rtw_get_ie((u8 *)(ptr+15), \n\t\t\t\tWNM_BTM_CAND_PREF_SUBEID, \n\t\t\t\t&op_len, (subelem_len - 15));\n\t\t}\n\n\t\tptr = (u8 *)(ptr + subelem_len + 2);\n\t\telem_len -= (subelem_len +2);\n\t\tsubelem_len = *(ptr+1);\n\t\tif (from_btm) {\n\t\t\tpcandidate = (pcandidates + i);\n\t\t\t_rtw_memcpy(&pcandidate->nb_rpt, pie, sizeof(struct nb_rpt_hdr));\n\t\t\tif (op && (op_len !=0)) {\n\t\t\t\tpcandidate->preference = *(op + 2);\n\t\t\t\tbfound = _TRUE;\n\t\t\t} else\n\t\t\t\tpcandidate->preference = 0;\n\n\t\t\tRTW_DBG(\"WNM: preference check bssid(\"MAC_FMT\n\t\t\t\t\") ,bss_info(0x%04X), reg_class(0x%02X), ch(%d),\"\n\t\t\t\t\" phy_type(0x%02X), preference(0x%02X)\\n\",\n\t\t\t\tMAC_ARG(pcandidate->nb_rpt.bssid), pcandidate->nb_rpt.bss_info, \n\t\t\t\tpcandidate->nb_rpt.reg_class, pcandidate->nb_rpt.ch_num, \n\t\t\t\tpcandidate->nb_rpt.phy_type, pcandidate->preference);\n\t\t} else {\n\t\t\tif (_rtw_memcmp(&pnb->nb_rpt[i], pie, sizeof(struct nb_rpt_hdr)) == _FALSE)\n\t\t\t\t*nb_rpt_is_same = _FALSE;\n\t\t\t_rtw_memcpy(&pnb->nb_rpt[i], pie, sizeof(struct nb_rpt_hdr));\n\t\t}\n\t\tnb_rpt_entries++;\t\t\t\n\t} \n\n\tif (from_btm) \n\t\tpnb->preference_en = (bfound)?_TRUE:_FALSE; \n\n\t*nb_rpt_num = nb_rpt_entries;\n\treturn ret;\n}\t\n\n/* selection sorting based on preference value\n *  : \t\tnb_rpt_entries - candidate num\n * / :\tpcandidates\t- candidate list\n * return : TRUE - means pcandidates is updated.  \n */\nstatic u8 rtw_wnm_candidates_sorting(\n\tu32 nb_rpt_entries, struct wnm_btm_cant *pcandidates)\n{\n\tu8 updated = _FALSE;\n\tu32 i, j, pos;\n\tstruct wnm_btm_cant swap;\n\tstruct wnm_btm_cant *pcant_1, *pcant_2;\n\n\tif ((!nb_rpt_entries) || (!pcandidates))\n\t\treturn updated;\n\n\tfor (i=0; i < (nb_rpt_entries - 1); i++) {\n\t\tpos = i;\n\t\tfor (j=(i + 1); j < nb_rpt_entries; j++) {\n\t\t\tpcant_1 = pcandidates+pos;\n\t\t\tpcant_2 = pcandidates+j;\n\t\t\tif ((pcant_1->preference) < (pcant_2->preference))\n\t\t\t\tpos = j;\n\t\t}\n\n\t\tif (pos != i) {\n\t\t\tupdated = _TRUE;\n\t\t\t_rtw_memcpy(&swap, (pcandidates+i), sizeof(struct wnm_btm_cant));\n\t\t\t_rtw_memcpy((pcandidates+i), (pcandidates+pos), sizeof(struct wnm_btm_cant));\n\t\t\t_rtw_memcpy((pcandidates+pos), &swap, sizeof(struct wnm_btm_cant));\n\t\t}\n\t}\t\n\treturn updated;\n}\t\n\nstatic void rtw_wnm_nb_info_update(\n\tu32 nb_rpt_entries, u8 from_btm, \n\tstruct roam_nb_info *pnb, struct wnm_btm_cant *pcandidates, \n\tu8 *nb_rpt_is_same)\n{\n\tu8 is_found;\n\tu32 i, j;\n\tstruct wnm_btm_cant *pcand;\n\n\tif (!pnb)\n\t\treturn;\n\n\tpnb->nb_rpt_ch_list_num = 0;\n\tfor (i=0; i<nb_rpt_entries; i++) {\n\t\tis_found = _FALSE;\n\t\tif (from_btm) {\n\t\t\tpcand = (pcandidates+i);\n\t\t\tif (_rtw_memcmp(&pnb->nb_rpt[i], &pcand->nb_rpt,\n\t\t\t\t\tsizeof(struct nb_rpt_hdr)) == _FALSE)\n\t\t\t\t*nb_rpt_is_same = _FALSE;\n\t\t\t_rtw_memcpy(&pnb->nb_rpt[i], &pcand->nb_rpt, sizeof(struct nb_rpt_hdr));\n\t\t}\n\n\t\tRTW_DBG(\"WNM: bssid(\" MAC_FMT \n\t\t\t\") , bss_info(0x%04X), reg_class(0x%02X), ch_num(%d), phy_type(0x%02X)\\n\",\n\t\t\tMAC_ARG(pnb->nb_rpt[i].bssid), pnb->nb_rpt[i].bss_info, \n\t\t\tpnb->nb_rpt[i].reg_class, pnb->nb_rpt[i].ch_num, \n\t\t\tpnb->nb_rpt[i].phy_type);\n\n\t\tif (pnb->nb_rpt[i].ch_num == 0)\n\t\t\tcontinue;\n\n\t\tfor (j=0; j<nb_rpt_entries; j++) {\n\t\t\tif (pnb->nb_rpt[i].ch_num == pnb->nb_rpt_ch_list[j].hw_value) {\n\t\t\t\tis_found = _TRUE;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t\t\t\t\t\t\n\t\tif (!is_found) {\n\t\t\tpnb->nb_rpt_ch_list[pnb->nb_rpt_ch_list_num].hw_value = pnb->nb_rpt[i].ch_num;\n\t\t\t\tpnb->nb_rpt_ch_list_num++;\n\t\t}\n\t}\n}\n\nstatic void rtw_wnm_btm_candidate_select(_adapter *padapter)\n{\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);\n\tstruct wlan_network *pnetwork;\n\tu8 bfound = _FALSE;\n\tu32 i;\n\n\tfor (i = 0; i < pnb->last_nb_rpt_entries; i++) {\n\t\tpnetwork = rtw_find_network(\n\t\t\t\t&(pmlmepriv->scanned_queue), \n\t\t\t\tpnb->nb_rpt[i].bssid);\n\n\t\tif (pnetwork) {\n\t\t\tbfound = _TRUE;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (bfound) {\n\t\t_rtw_memcpy(pnb->roam_target_addr, pnb->nb_rpt[i].bssid, ETH_ALEN);\n\t\tRTW_INFO(\"WNM : select btm entry(%d) - %s(\"MAC_FMT\", ch%u) rssi:%d\\n\"\n\t\t\t, i\n\t\t\t, pnetwork->network.Ssid.Ssid\n\t\t\t, MAC_ARG(pnetwork->network.MacAddress)\n\t\t\t, pnetwork->network.Configuration.DSConfig\n\t\t\t, (int)pnetwork->network.Rssi);\n\t} else \n\t\t_rtw_memset(pnb->roam_target_addr,0, ETH_ALEN);\n}\n\nu32 rtw_wnm_btm_candidates_survey(\n\t_adapter *padapter, u8* pframe, u32 elem_len, u8 from_btm)\n{\n\tstruct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);\n\tstruct wnm_btm_cant *pcandidate_list = NULL;\n\tu8 nb_rpt_is_same = _TRUE;\n\tu32\tret = _FAIL;\n\tu32 nb_rpt_entries = 0;\t\n\n\tif (from_btm) {\n\t\tu32 mlen = sizeof(struct wnm_btm_cant) * RTW_MAX_NB_RPT_NUM;\n\t\tpcandidate_list = (struct wnm_btm_cant *)rtw_malloc(mlen);\n\t\tif (pcandidate_list == NULL) \n\t\t\tgoto exit;\t\t\t\t\n\t}\n\n\t/*clean the status set last time*/\n\t_rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list));\n\tpnb->nb_rpt_valid = _FALSE;\n\tif (!rtw_wnm_nb_elem_parsing(\n\t\t\tpframe, elem_len, from_btm, \n\t\t\t&nb_rpt_entries, &nb_rpt_is_same,\n\t\t\tpnb, pcandidate_list))\n\t\tgoto exit;\n\n\tif (nb_rpt_entries != 0) {\n\t\tif ((from_btm) && (rtw_wnm_btm_preference_cap(padapter)))\n\t\t\trtw_wnm_candidates_sorting(nb_rpt_entries, pcandidate_list);\n\n\t\trtw_wnm_nb_info_update(\n\t\t\tnb_rpt_entries, from_btm, \n\t\t\tpnb, pcandidate_list, &nb_rpt_is_same);\n\t}\n\n\tRTW_INFO(\"nb_rpt_is_same = %d, nb_rpt_entries = %d, last_nb_rpt_entries = %d\\n\", \n\t\tnb_rpt_is_same, nb_rpt_entries, pnb->last_nb_rpt_entries);\n\tif ((nb_rpt_is_same == _TRUE) && (nb_rpt_entries == pnb->last_nb_rpt_entries))\n\t\tpnb->nb_rpt_is_same = _TRUE;\n\telse {\n\t\tpnb->nb_rpt_is_same = _FALSE;\n\t\tpnb->last_nb_rpt_entries = nb_rpt_entries;\n\t}\n\n\tif ((from_btm) && (nb_rpt_entries != 0))\n\t\trtw_wnm_btm_candidate_select(padapter);\n\t\n\tpnb->nb_rpt_valid = _TRUE;\n\tret = _SUCCESS;\n\nexit:\n\tif (from_btm && pcandidate_list)\n\t\trtw_mfree((u8 *)pcandidate_list, sizeof(struct wnm_btm_cant) * RTW_MAX_NB_RPT_NUM);\n\t\n\treturn ret;\n}\n#endif\n\nunsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame)\n{\n#ifdef CONFIG_RTW_80211R\n\tu32\tret = _FAIL;\n\tu32\tframe_len = 0;\n\tu8\taction_code = 0;\n\tu8\tcategory = 0;\n\tu8\t*pframe = NULL;\n\tu8\t*pframe_body = NULL;\n\tu8\tsta_addr[ETH_ALEN] = {0};\n\tu8\t*pie = NULL;\n\tu32\tft_ie_len = 0;\n\tu32 status_code = 0;\n\tstruct mlme_ext_priv *pmlmeext = NULL;\n\tstruct mlme_ext_info *pmlmeinfo = NULL;\n\tstruct mlme_priv *pmlmepriv = NULL;\n\tstruct wlan_network *proam_target = NULL;\n\tstruct ft_roam_info *pft_roam = NULL;\n\t_irqL  irqL;\n\n\tpmlmeext = &(padapter->mlmeextpriv);\n\tpmlmeinfo = &(pmlmeext->mlmext_info);\n\tpmlmepriv = &(padapter->mlmepriv);\n\tpft_roam = &(pmlmepriv->ft_roam);\n\tpframe = precv_frame->u.hdr.rx_data;\n\tframe_len = precv_frame->u.hdr.len;\n\tpframe_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);\n\tcategory = pframe_body[0];\n\n\tif (category != RTW_WLAN_CATEGORY_FT)\n\t\tgoto exit;\n\n\taction_code = pframe_body[1];\n\tswitch (action_code) {\n\tcase RTW_WLAN_ACTION_FT_RSP:\n\t\tRTW_INFO(\"FT: RTW_WLAN_ACTION_FT_RSP recv.\\n\");\n\t\tif (!_rtw_memcmp(adapter_mac_addr(padapter), &pframe_body[2], ETH_ALEN)) {\n\t\t\tRTW_ERR(\"FT: Unmatched STA MAC Address \"MAC_FMT\"\\n\", MAC_ARG(&pframe_body[2]));\n\t\t\tgoto exit;\n\t\t}\n\n\t\tstatus_code = le16_to_cpu(*(u16 *)((SIZE_PTR)pframe +  sizeof(struct rtw_ieee80211_hdr_3addr) + 14));\n\t\tif (status_code != 0) {\n\t\t\tRTW_ERR(\"FT: WLAN ACTION FT RESPONSE fail, status: %d\\n\", status_code);\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (is_zero_mac_addr(&pframe_body[8]) || is_broadcast_mac_addr(&pframe_body[8])) {\n\t\t\tRTW_ERR(\"FT: Invalid Target MAC Address \"MAC_FMT\"\\n\", MAC_ARG(padapter->mlmepriv.roam_tgt_addr));\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpie = rtw_get_ie(pframe_body, _MDIE_, &ft_ie_len, frame_len);\n\t\tif (pie) {\n\t\t\tif (!_rtw_memcmp(&pft_roam->mdid, pie+2, 2)) {\n\t\t\t\tRTW_ERR(\"FT: Invalid MDID\\n\");\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\n\t\trtw_ft_set_status(padapter, RTW_FT_REQUESTED_STA);\n\t\t_cancel_timer_ex(&pmlmeext->ft_link_timer);\n\n\t\t/*Disconnect current AP*/\n\t\treceive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress, WLAN_REASON_ACTIVE_ROAM, _FALSE);\n\n\t\tpft_roam->ft_action_len = frame_len;\n\t\t_rtw_memcpy(pft_roam->ft_action, pframe, rtw_min(frame_len, RTW_FT_MAX_IE_SZ));\n\t\tret = _SUCCESS;\n\t\tbreak;\n\tcase RTW_WLAN_ACTION_FT_REQ:\n\tcase RTW_WLAN_ACTION_FT_CONF:\n\tcase RTW_WLAN_ACTION_FT_ACK:\n\tdefault:\n\t\tRTW_ERR(\"FT: Unsupported FT Action!\\n\");\n\t\tbreak;\n\t}\n\nexit:\n\treturn ret;\n#else\n\treturn _SUCCESS;\n#endif\n}\n\n#ifdef CONFIG_RTW_WNM\nu8 rtw_wmn_btm_rsp_reason_decision(_adapter *padapter, u8* req_mode)\n{\n\tstruct recv_priv *precvpriv = &padapter->recvpriv;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tu8 reason = 0;\n\n\tif (!rtw_wnm_btm_diff_bss(padapter)) {\n\t\t/* Reject - No suitable BSS transition candidates */\n\t\treason = 7;\n\t\tgoto candidate_remove;\n\t}\n\n#ifdef CONFIG_RTW_80211R\n\tif (rtw_ft_chk_flags(padapter, RTW_FT_BTM_ROAM)) {\n\t\t/* Accept */\n\t\treason = 0;\n\t\tgoto under_survey;\n\t}\t\n#endif\n\n\tif (((*req_mode) & DISASSOC_IMMINENT) == 0) {\n\t\t/* Reject - Unspecified reject reason */\n\t\treason = 1;\n\t\tgoto candidate_remove;\n\t}\t\n\n\tif (precvpriv->signal_strength_data.avg_val >= pmlmepriv->roam_rssi_threshold) {\n\t\treason = 1;\n\t\tgoto candidate_remove;\n\t}\n\nunder_survey:\t\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) {\n\t\tRTW_INFO(\"%s reject due to _FW_UNDER_SURVEY\\n\", __func__);\n\t\treason = 1;\n\t}\n\ncandidate_remove:\n\tif (reason !=0)\n\t\trtw_wnm_reset_btm_candidate(&padapter->mlmepriv.nb_info);\n\n\treturn reason;\n}\n\nstatic u32 rtw_wnm_btm_candidates_offset_get(u8* pframe)\n{\n\tu8 *pos = pframe;\n\tu32 offset = 0;\n\n\tif (!pframe)\n\t\treturn 0;\n\n\toffset += 7;\n\tpos += offset;\n\n\t/* BSS Termination Duration check */\n\tif (wnm_btm_bss_term_inc(pframe)) {\n\t\toffset += 12;\n\t\tpos += offset;\t\n\t}\t\n\n\t/* Session Information URL check*/\n\tif (wnm_btm_ess_disassoc_im(pframe)) {\n\t\t/*URL length field + URL variable length*/\n\t\toffset = 1 + *(pframe + offset);\n\t\tpos += offset;\t\n\t}\n\n\toffset = (pos - pframe);\n\treturn offset;\n}\n\nstatic void rtw_wnm_btm_req_hdr_parsing(u8* pframe, struct btm_req_hdr *phdr)\n{\n\tu8 *pos = pframe;\n\tu32 offset = 0;\n\n\tif (!pframe || !phdr)\n\t\treturn;\n\n\t_rtw_memset(phdr, 0, sizeof(struct btm_req_hdr));\n\tphdr->req_mode  = wnm_btm_req_mode(pframe);\n\tphdr->disassoc_timer = wnm_btm_disassoc_timer(pframe);\n\tphdr->validity_interval = wnm_btm_valid_interval(pframe);\n\tif (wnm_btm_bss_term_inc(pframe)) {\n\t\t_rtw_memcpy(&phdr->term_duration, \n\t\t\twnm_btm_term_duration_offset(pframe), \n\t\t\tsizeof(struct btm_term_duration));\n\t}\n\n\tRTW_DBG(\"WNM: req_mode(%1x), disassoc_timer(%02x), interval(%x)\\n\",\n\t\tphdr->req_mode, phdr->disassoc_timer, phdr->validity_interval);\n\tif (wnm_btm_bss_term_inc(pframe))\n\t\tRTW_INFO(\"WNM: tsf(%llx), duration(%2x)\\n\",\n\t\t\tphdr->term_duration.tsf, phdr->term_duration.duration);\n}\n\nvoid rtw_wnm_roam_scan_hdl(void *ctx)\n{\n\t_adapter *padapter = (_adapter *)ctx;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\tif (rtw_is_scan_deny(padapter)) \n\t\tRTW_INFO(\"WNM: roam scan would abort by scan_deny!\\n\");\n\t\t\n\tpmlmepriv->need_to_roam = _TRUE;\n\trtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM);\n}\n\nstatic void rtw_wnm_roam_scan(_adapter *padapter)\n{\n\tstruct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);\n\n\tif (rtw_is_scan_deny(padapter)) {\n\t\t_cancel_timer_ex(&pnb->roam_scan_timer);\n\t\t_set_timer(&pnb->roam_scan_timer, 1000);\n\t} else\n\t\trtw_wnm_roam_scan_hdl((void *)padapter);\n}\n\nvoid rtw_wnm_process_btm_req(_adapter *padapter, u8* pframe, u32 frame_len)\n{\n\tstruct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);\n\tstruct btm_req_hdr req_hdr;\n\tu8 *ptr, reason;\n\tu32 elem_len, offset;\n\n\trtw_wnm_btm_req_hdr_parsing(pframe, &req_hdr);\n\toffset = rtw_wnm_btm_candidates_offset_get(pframe);\n\tif ((offset == 0) || ((frame_len - offset) <= 15))\n\t\treturn;\n\n\tptr = (pframe + offset);\n\telem_len = (frame_len - offset);\n\trtw_wnm_btm_candidates_survey(padapter, ptr, elem_len, _TRUE);\n\treason = rtw_wmn_btm_rsp_reason_decision(padapter, &pframe[3]);\n\trtw_wnm_issue_action(padapter, \n\t\tRTW_WLAN_ACTION_WNM_BTM_RSP, reason);\n\n\tif (reason == 0) \n\t\trtw_wnm_roam_scan(padapter);\n}\n\nvoid rtw_wnm_reset_btm_candidate(struct roam_nb_info *pnb)\n{\n\tpnb->preference_en = _FALSE;\n\t_rtw_memset(pnb->roam_target_addr, 0, ETH_ALEN);\n}\n\nvoid rtw_wnm_reset_btm_state(_adapter *padapter)\n{\n\tstruct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);\n\n\tpnb->last_nb_rpt_entries = 0;\n\tpnb->nb_rpt_is_same = _TRUE;\n\tpnb->nb_rpt_valid = _FALSE;\n\tpnb->nb_rpt_ch_list_num = 0;\n\trtw_wnm_reset_btm_candidate(pnb);\n\t_rtw_memset(&pnb->nb_rpt, 0, sizeof(pnb->nb_rpt));\n\t_rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list));\n}\n\nvoid rtw_wnm_issue_action(_adapter *padapter, u8 action, u8 reason)\n{\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct xmit_priv *pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct xmit_frame *pmgntframe;\n\tstruct rtw_ieee80211_hdr *pwlanhdr;\n\tstruct pkt_attrib *pattrib;\n\tu8 category, dialog_token, termination_delay, *pframe;\n\tu16 *fctrl;\n\n\tif ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)\n\t\treturn ;\n\t\n\tpattrib = &(pmgntframe->attrib);\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\t_rtw_memset(pmgntframe->buf_addr, 0, (WLANHDR_OFFSET + TXDESC_OFFSET));\n\n\tpframe = (u8 *)(pmgntframe->buf_addr + TXDESC_OFFSET);\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tcategory = RTW_WLAN_CATEGORY_WNM;\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));\n\n\tswitch (action) {\n\t\tcase RTW_WLAN_ACTION_WNM_BTM_QUERY:\n\t\t\tpframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen));\n\t\t\tpframe = rtw_set_fixed_ie(pframe, 1, &(reason), &(pattrib->pktlen));\n\t\t\tRTW_INFO(\"WNM: RTW_WLAN_ACTION_WNM_BTM_QUERY sent.\\n\");\n\t\t\tbreak;\n\t\tcase RTW_WLAN_ACTION_WNM_BTM_RSP:\n\t\t\ttermination_delay = 0;\n\t\t\tpframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen));\n\t\t\tpframe = rtw_set_fixed_ie(pframe, 1, &(reason), &(pattrib->pktlen));\n\t\t\tpframe = rtw_set_fixed_ie(pframe, 1, &(termination_delay), &(pattrib->pktlen));\n\t\t\tif (!is_zero_mac_addr(pmlmepriv->nb_info.roam_target_addr)) {\n\t\t\t\tpframe = rtw_set_fixed_ie(pframe, 6, \n\t\t\t\t\tpmlmepriv->nb_info.roam_target_addr, &(pattrib->pktlen));\n\t\t\t}\n\t\t\tRTW_INFO(\"WNM: RTW_WLAN_ACTION_WNM_BTM_RSP sent. reason = %d\\n\", reason);\t\t\t\n\t\t\tbreak;\t\t\n\t\tdefault:\n\t\t\tgoto exit;\n\t}\t\n\t\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\tdump_mgntframe(padapter, pmgntframe);\n\nexit:\t\n\treturn;\n}\n#endif\n\nunsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tu8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);\n\tu8 category, action;\n\n\t/* check RA matches or not */\n\tif (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))\n\t\tgoto exit;\n\n\tcategory = frame_body[0];\n\tif (category != RTW_WLAN_CATEGORY_HT)\n\t\tgoto exit;\n\n\taction = frame_body[1];\n\tswitch (action) {\n\tcase RTW_WLAN_ACTION_HT_SM_PS:\n#ifdef CONFIG_80211N_HT\n#ifdef CONFIG_AP_MODE\n\t\tif (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)\n\t\t\trtw_process_ht_action_smps(padapter, get_addr2_ptr(pframe), frame_body[2]);\n#endif /*CONFIG_AP_MODE*/\n#endif /*CONFIG_80211N_HT*/\n\t\tbreak;\n\tcase RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING:\n#ifdef CONFIG_BEAMFORMING\n\t\t/*RTW_INFO(\"RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING\\n\");*/\n\t\trtw_beamforming_get_report_frame(padapter, precv_frame);\n#endif /*CONFIG_BEAMFORMING*/\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\nexit:\n\n\treturn _SUCCESS;\n}\n\n#ifdef CONFIG_IEEE80211W\nunsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tstruct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct sta_info\t\t*psta;\n\tstruct sta_priv\t\t*pstapriv = &padapter->stapriv;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tu16 tid;\n\t/* Baron */\n\n\tRTW_INFO(\"OnAction_sa_query\\n\");\n\n\tswitch (pframe[WLAN_HDR_A3_LEN + 1]) {\n\tcase 0: /* SA Query req */\n\t\t_rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN + 2], sizeof(u16));\n\t\tRTW_INFO(\"OnAction_sa_query request,action=%d, tid=%04x, pframe=%02x-%02x\\n\"\n\t\t\t, pframe[WLAN_HDR_A3_LEN + 1], tid, pframe[WLAN_HDR_A3_LEN + 2], pframe[WLAN_HDR_A3_LEN + 3]);\n\t\tissue_action_SA_Query(padapter, get_addr2_ptr(pframe), 1, tid, IEEE80211W_RIGHT_KEY);\n\t\tbreak;\n\n\tcase 1: /* SA Query rsp */\n\t\tpsta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));\n\t\tif (psta != NULL)\n\t\t\t_cancel_timer_ex(&psta->dot11w_expire_timer);\n\n\t\t_rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN + 2], sizeof(u16));\n\t\tRTW_INFO(\"OnAction_sa_query response,action=%d, tid=%04x, cancel timer\\n\", pframe[WLAN_HDR_A3_LEN + 1], tid);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\tif (0) {\n\t\tint pp;\n\t\tprintk(\"pattrib->pktlen = %d =>\", pattrib->pkt_len);\n\t\tfor (pp = 0; pp < pattrib->pkt_len; pp++)\n\t\t\tprintk(\" %02x \", pframe[pp]);\n\t\tprintk(\"\\n\");\n\t}\n\n\treturn _SUCCESS;\n}\n#endif /* CONFIG_IEEE80211W */\n\nunsigned int on_action_rm(_adapter *padapter, union recv_frame *precv_frame)\n{\n#ifdef CONFIG_RTW_80211K\n\treturn rm_on_action(padapter, precv_frame);\n#else\n\treturn _SUCCESS;\n#endif  /* CONFIG_RTW_80211K */\n}\n\nunsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame)\n{\n\treturn _SUCCESS;\n}\n\nunsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame)\n{\n#ifdef CONFIG_80211AC_VHT\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tstruct rtw_ieee80211_hdr_3addr *whdr = (struct rtw_ieee80211_hdr_3addr *)pframe;\n\tu8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);\n\tu8 category, action;\n\tstruct sta_info *psta = NULL;\n\n\t/* check RA matches or not */\n\tif (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))\n\t\tgoto exit;\n\n\tcategory = frame_body[0];\n\tif (category != RTW_WLAN_CATEGORY_VHT)\n\t\tgoto exit;\n\n\taction = frame_body[1];\n\tswitch (action) {\n\tcase RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING:\n#ifdef CONFIG_BEAMFORMING\n\t\t/*RTW_INFO(\"RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING\\n\");*/\n\t\trtw_beamforming_get_report_frame(padapter, precv_frame);\n#endif /*CONFIG_BEAMFORMING*/\n\t\tbreak;\n\tcase RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION:\n\t\t/* CategoryCode(1) + ActionCode(1) + OpModeNotification(1) */\n\t\t/* RTW_INFO(\"RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION\\n\"); */\n\t\tpsta = rtw_get_stainfo(&padapter->stapriv, whdr->addr2);\n\t\tif (psta)\n\t\t\trtw_process_vht_op_mode_notify(padapter, &frame_body[2], psta);\n\t\tbreak;\n\tcase RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT:\n#ifdef CONFIG_BEAMFORMING\n#ifdef RTW_BEAMFORMING_VERSION_2\n\t\trtw_beamforming_get_vht_gid_mgnt_frame(padapter, precv_frame);\n#endif /* RTW_BEAMFORMING_VERSION_2 */\n#endif /* CONFIG_BEAMFORMING */\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\nexit:\n#endif /* CONFIG_80211AC_VHT */\n\n\treturn _SUCCESS;\n}\n\nunsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame)\n{\n#ifdef CONFIG_P2P\n\tu8 *frame_body;\n\tu8 category, OUI_Subtype, dialogToken = 0;\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tuint len = precv_frame->u.hdr.len;\n\tstruct\twifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\t/* check RA matches or not */\n\tif (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))\n\t\treturn _SUCCESS;\n\n\tframe_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));\n\n\tcategory = frame_body[0];\n\tif (category != RTW_WLAN_CATEGORY_P2P)\n\t\treturn _SUCCESS;\n\n\tif (cpu_to_be32(*((u32 *)(frame_body + 1))) != P2POUI)\n\t\treturn _SUCCESS;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (adapter_wdev_data(padapter)->p2p_enabled\n\t\t&& pwdinfo->driver_interface == DRIVER_CFG80211\n\t) {\n\t\trtw_cfg80211_rx_action_p2p(padapter, precv_frame);\n\t\treturn _SUCCESS;\n\t} else\n#endif /* CONFIG_IOCTL_CFG80211 */\n\t{\n\t\tlen -= sizeof(struct rtw_ieee80211_hdr_3addr);\n\t\tOUI_Subtype = frame_body[5];\n\t\tdialogToken = frame_body[6];\n\n\t\tswitch (OUI_Subtype) {\n\t\tcase P2P_NOTICE_OF_ABSENCE:\n\n\t\t\tbreak;\n\n\t\tcase P2P_PRESENCE_REQUEST:\n\n\t\t\tprocess_p2p_presence_req(pwdinfo, pframe, len);\n\n\t\t\tbreak;\n\n\t\tcase P2P_PRESENCE_RESPONSE:\n\n\t\t\tbreak;\n\n\t\tcase P2P_GO_DISC_REQUEST:\n\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tbreak;\n\n\t\t}\n\t}\n#endif /* CONFIG_P2P */\n\n\treturn _SUCCESS;\n\n}\n\nunsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tint i;\n\tunsigned char\tcategory;\n\tstruct action_handler *ptable;\n\tunsigned char\t*frame_body;\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\n\tframe_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));\n\n\tcategory = frame_body[0];\n\n\tfor (i = 0; i < sizeof(OnAction_tbl) / sizeof(struct action_handler); i++) {\n\t\tptable = &OnAction_tbl[i];\n\n\t\tif (category == ptable->num)\n\t\t\tptable->func(padapter, precv_frame);\n\n\t}\n\n\treturn _SUCCESS;\n\n}\n\nunsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame)\n{\n\n\t/* RTW_INFO(\"rcvd mgt frame(%x, %x)\\n\", (get_frame_sub_type(pframe) >> 4), *(unsigned int *)GetAddr1Ptr(pframe)); */\n\treturn _SUCCESS;\n}\n\nstruct xmit_frame *_alloc_mgtxmitframe(struct xmit_priv *pxmitpriv, bool once)\n{\n\tstruct xmit_frame *pmgntframe;\n\tstruct xmit_buf *pxmitbuf;\n\n\tif (once)\n\t\tpmgntframe = rtw_alloc_xmitframe_once(pxmitpriv);\n\telse\n\t\tpmgntframe = rtw_alloc_xmitframe_ext(pxmitpriv);\n\n\tif (pmgntframe == NULL) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" alloc xmitframe fail, once:%d\\n\", FUNC_ADPT_ARG(pxmitpriv->adapter), once);\n\t\tgoto exit;\n\t}\n\n\tpxmitbuf = rtw_alloc_xmitbuf_ext(pxmitpriv);\n\tif (pxmitbuf == NULL) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" alloc xmitbuf fail\\n\", FUNC_ADPT_ARG(pxmitpriv->adapter));\n\t\trtw_free_xmitframe(pxmitpriv, pmgntframe);\n\t\tpmgntframe = NULL;\n\t\tgoto exit;\n\t}\n\n\tpmgntframe->frame_tag = MGNT_FRAMETAG;\n\tpmgntframe->pxmitbuf = pxmitbuf;\n\tpmgntframe->buf_addr = pxmitbuf->pbuf;\n\tpxmitbuf->priv_data = pmgntframe;\n\nexit:\n\treturn pmgntframe;\n\n}\n\ninline struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv)\n{\n\treturn _alloc_mgtxmitframe(pxmitpriv, _FALSE);\n}\n\ninline struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv)\n{\n\treturn _alloc_mgtxmitframe(pxmitpriv, _TRUE);\n}\n\n\n/****************************************************************************\n\nFollowing are some TX fuctions for WiFi MLME\n\n*****************************************************************************/\n\nvoid update_mgnt_tx_rate(_adapter *padapter, u8 rate)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\n\tpmlmeext->tx_rate = rate;\n\t/* RTW_INFO(\"%s(): rate = %x\\n\",__FUNCTION__, rate); */\n}\n\n\nvoid update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tu8\twireless_mode;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct xmit_priv\t\t*pxmitpriv = &padapter->xmitpriv;\n\tstruct sta_info\t\t*psta = NULL;\n\tstruct sta_priv\t\t*pstapriv = &padapter->stapriv;\n\n\tpsta = rtw_get_stainfo(pstapriv, pattrib->ra);\n\n\tpattrib->hdrlen = 24;\n\tpattrib->nr_frags = 1;\n\tpattrib->priority = 7;\n\tpattrib->mac_id = RTW_DEFAULT_MGMT_MACID;\n\tpattrib->qsel = QSLT_MGNT;\n\n\tpattrib->pktlen = 0;\n\n\tif (pmlmeext->tx_rate == IEEE80211_CCK_RATE_1MB)\n\t\twireless_mode = WIRELESS_11B;\n\telse\n\t\twireless_mode = WIRELESS_11G;\n\n\tpattrib->raid = rtw_get_mgntframe_raid(padapter, wireless_mode);\n#ifdef CONFIG_80211AC_VHT\n\tif (pHalData->rf_type == RF_1T1R)\n\t\tpattrib->raid = RATEID_IDX_VHT_1SS;\n\telse if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)\n\t\tpattrib->raid = RATEID_IDX_VHT_2SS;\n\telse if (pHalData->rf_type == RF_3T3R)\n\t\tpattrib->raid = RATEID_IDX_VHT_3SS;\n\telse\n\t\tpattrib->raid = RATEID_IDX_BGN_40M_1SS;\n#endif\n\n#ifdef CONFIG_80211AC_VHT\n\tpattrib->rate = MGN_VHT1SS_MCS9;\n#else\n\tpattrib->rate = MGN_MCS7;\n#endif\n\n\tpattrib->encrypt = _NO_PRIVACY_;\n\tpattrib->bswenc = _FALSE;\n\n\tpattrib->qos_en = _FALSE;\n\tpattrib->ht_en = 1;\n\tpattrib->bwmode = CHANNEL_WIDTH_20;\n\tpattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\tpattrib->sgi = _FALSE;\n\n\tpattrib->seqnum = pmlmeext->mgnt_seq;\n\n\tpattrib->retry_ctrl = _TRUE;\n\n\tpattrib->mbssid = 0;\n\tpattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no;\n\n}\n\n\nvoid update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib)\n{\n\tu8\twireless_mode;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct xmit_priv\t\t*pxmitpriv = &padapter->xmitpriv;\n\n#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n#endif /* CONFIG_P2P_PS_NOA_USE_MACID_SLEEP */\n\n\t/* _rtw_memset((u8 *)(pattrib), 0, sizeof(struct pkt_attrib)); */\n\n\tpattrib->hdrlen = 24;\n\tpattrib->nr_frags = 1;\n\tpattrib->priority = 7;\n\tpattrib->mac_id = RTW_DEFAULT_MGMT_MACID;\n\tpattrib->qsel = QSLT_MGNT;\n\n#ifdef CONFIG_MCC_MODE\n\tupdate_mcc_mgntframe_attrib(padapter, pattrib);\n#endif\n\n\n#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_buddy_check_fwstate(padapter, WIFI_ASOC_STATE))\n#endif /* CONFIG_CONCURRENT_MODE */\n\t\tif (MLME_IS_GC(padapter)) {\n\t\t\tif (pwdinfo->p2p_ps_mode > P2P_PS_NONE) {\n\t\t\t\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\t\t\t\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\t\t\t\tWLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);\n\t\t\t\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\t\t\t\tstruct sta_info *psta;\n\n\t\t\t\tpsta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);\n\t\t\t\tif (psta) {\n\t\t\t\t\t/* use macid sleep during NoA, mgmt frame use ac queue & ap macid */\n\t\t\t\t\tpattrib->mac_id = psta->cmn.mac_id;\n\t\t\t\t\tpattrib->qsel = QSLT_VO;\n\t\t\t\t} else {\n\t\t\t\t\tif (pwdinfo->p2p_ps_state != P2P_PS_DISABLE)\n\t\t\t\t\t\tRTW_ERR(\"%s , psta was NULL\\n\", __func__);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n#endif /* CONFIG_P2P_PS_NOA_USE_MACID_SLEEP */\n\n\n\tpattrib->pktlen = 0;\n\n\tif (IS_CCK_RATE(pmlmeext->tx_rate))\n\t\twireless_mode = WIRELESS_11B;\n\telse\n\t\twireless_mode = WIRELESS_11G;\n\tpattrib->raid =  rtw_get_mgntframe_raid(padapter, wireless_mode);\n\tpattrib->rate = pmlmeext->tx_rate;\n\n\tpattrib->encrypt = _NO_PRIVACY_;\n\tpattrib->bswenc = _FALSE;\n\n\tpattrib->qos_en = _FALSE;\n\tpattrib->ht_en = _FALSE;\n\tpattrib->bwmode = CHANNEL_WIDTH_20;\n\tpattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\tpattrib->sgi = _FALSE;\n\n\tpattrib->seqnum = pmlmeext->mgnt_seq;\n\n\tpattrib->retry_ctrl = _TRUE;\n\n\tpattrib->mbssid = 0;\n\tpattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no;\n}\n\nvoid update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntframe)\n{\n\tu8\t*pframe;\n\tstruct pkt_attrib\t*pattrib = &pmgntframe->attrib;\n#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY)\n\tstruct sta_info\t\t*sta = NULL;\n#endif\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\n\t_rtw_memcpy(pattrib->ra, GetAddr1Ptr(pframe), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ta, get_addr2_ptr(pframe), ETH_ALEN);\n\n#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY)\n\tsta = pattrib->psta;\n\tif (!sta) {\n\t\tsta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);\n\t\tpattrib->psta = sta;\n\t}\n\t#ifdef CONFIG_BEAMFORMING\n\tif (sta)\n\t\tupdate_attrib_txbf_info(padapter, pattrib, sta);\n\t#endif\n#endif /* defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) */\n}\n\nvoid dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe)\n{\n\tif (RTW_CANNOT_RUN(padapter)) {\n\t\trtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf);\n\t\trtw_free_xmitframe(&padapter->xmitpriv, pmgntframe);\n\t\treturn;\n\t}\n\n\trtw_hal_mgnt_xmit(padapter, pmgntframe);\n}\n\ns32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms)\n{\n\ts32 ret = _FAIL;\n\t_irqL irqL;\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tstruct xmit_buf *pxmitbuf = pmgntframe->pxmitbuf;\n\tstruct submit_ctx sctx;\n\n\tif (RTW_CANNOT_RUN(padapter)) {\n\t\trtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf);\n\t\trtw_free_xmitframe(&padapter->xmitpriv, pmgntframe);\n\t\treturn ret;\n\t}\n\n\trtw_sctx_init(&sctx, timeout_ms);\n\tpxmitbuf->sctx = &sctx;\n\n\tret = rtw_hal_mgnt_xmit(padapter, pmgntframe);\n\n\tif (ret == _SUCCESS)\n\t\tret = rtw_sctx_wait(&sctx, __func__);\n\n\t_enter_critical(&pxmitpriv->lock_sctx, &irqL);\n\tpxmitbuf->sctx = NULL;\n\t_exit_critical(&pxmitpriv->lock_sctx, &irqL);\n\n\treturn ret;\n}\n\ns32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms)\n{\n#ifdef CONFIG_XMIT_ACK\n\tstatic u8 seq_no = 0;\n\ts32 ret = _FAIL;\n\tstruct xmit_priv\t*pxmitpriv = &(GET_PRIMARY_ADAPTER(padapter))->xmitpriv;\n\n\tif (RTW_CANNOT_RUN(padapter)) {\n\t\trtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf);\n\t\trtw_free_xmitframe(&padapter->xmitpriv, pmgntframe);\n\t\treturn -1;\n\t}\n\n\t_enter_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL);\n\tpxmitpriv->ack_tx = _TRUE;\n\tpxmitpriv->seq_no = seq_no++;\n\tpmgntframe->ack_report = 1;\n\trtw_sctx_init(&(pxmitpriv->ack_tx_ops), timeout_ms);\n\tif (rtw_hal_mgnt_xmit(padapter, pmgntframe) == _SUCCESS)\n\t\tret = rtw_sctx_wait(&(pxmitpriv->ack_tx_ops), __func__);\n\n\tpxmitpriv->ack_tx = _FALSE;\n\t_exit_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL);\n\n\treturn ret;\n#else /* !CONFIG_XMIT_ACK */\n\tdump_mgntframe(padapter, pmgntframe);\n\trtw_msleep_os(50);\n\treturn _SUCCESS;\n#endif /* !CONFIG_XMIT_ACK */\n}\n\ns32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntframe)\n{\n\t/* In this case, use 500 ms as the default wait_ack timeout */\n\treturn dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, 500);\n}\n\n\nint update_hidden_ssid(u8 *ies, u32 ies_len, u8 hidden_ssid_mode)\n{\n\tu8 *ssid_ie;\n\tsint ssid_len_ori;\n\tint len_diff = 0;\n\n\tssid_ie = rtw_get_ie(ies,  WLAN_EID_SSID, &ssid_len_ori, ies_len);\n\n\t/* RTW_INFO(\"%s hidden_ssid_mode:%u, ssid_ie:%p, ssid_len_ori:%d\\n\", __FUNCTION__, hidden_ssid_mode, ssid_ie, ssid_len_ori); */\n\n\tif (ssid_ie && ssid_len_ori > 0) {\n\t\tswitch (hidden_ssid_mode) {\n\t\tcase 1: {\n\t\t\tu8 *next_ie = ssid_ie + 2 + ssid_len_ori;\n\t\t\tu32 remain_len = 0;\n\n\t\t\tremain_len = ies_len - (next_ie - ies);\n\n\t\t\tssid_ie[1] = 0;\n\t\t\t_rtw_memcpy(ssid_ie + 2, next_ie, remain_len);\n\t\t\tlen_diff -= ssid_len_ori;\n\n\t\t\tbreak;\n\t\t}\n\t\tcase 2:\n\t\t\t_rtw_memset(&ssid_ie[2], 0, ssid_len_ori);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn len_diff;\n}\n\nvoid issue_beacon(_adapter *padapter, int timeout_ms)\n{\n\tstruct xmit_frame\t*pmgntframe;\n\tstruct pkt_attrib\t*pattrib;\n\tunsigned char\t*pframe;\n\tstruct rtw_ieee80211_hdr *pwlanhdr;\n\tunsigned short *fctrl;\n\tunsigned int\trate_len;\n\tstruct xmit_priv\t*pxmitpriv = &(padapter->xmitpriv);\n#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)\n\t_irqL irqL;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t\t*cur_network = &(pmlmeinfo->network);\n\tu8\tbc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n#endif /* CONFIG_P2P */\n\n\n\t/* RTW_INFO(\"%s\\n\", __FUNCTION__); */\n\n#ifdef CONFIG_BCN_ICF\n\tpmgntframe = rtw_alloc_bcnxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n#else\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n#endif\n\t{\n\t\tRTW_INFO(\"%s, alloc mgnt frame fail\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)\n\t_enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);\n#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\tpattrib->qsel = QSLT_BEACON;\n\n#if defined(CONFIG_CONCURRENT_MODE) && (!defined(CONFIG_SWTIMER_BASED_TXBCN))\n\tif (padapter->hw_port == HW_PORT1)\n\t\tpattrib->mbssid = 1;\n#endif\n#ifdef CONFIG_FW_HANDLE_TXBCN\n\tif (padapter->vap_id != CONFIG_LIMITED_AP_NUM)\n\t\tpattrib->mbssid = padapter->vap_id;\n#endif\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);\n\t/* pmlmeext->mgnt_seq++; */\n\tset_frame_sub_type(pframe, WIFI_BEACON);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tif (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {\n\t\t/* RTW_INFO(\"ie len=%d\\n\", cur_network->IELength); */\n#ifdef CONFIG_P2P\n\t\t/* for P2P : Primary Device Type & Device Name */\n\t\tu32 wpsielen = 0, insert_len = 0;\n\t\tu8 *wpsie = NULL;\n\t\twpsie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen);\n\n\t\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && wpsie && wpsielen > 0) {\n\t\t\tuint wps_offset, remainder_ielen;\n\t\t\tu8 *premainder_ie, *pframe_wscie;\n\n\t\t\twps_offset = (uint)(wpsie - cur_network->IEs);\n\n\t\t\tpremainder_ie = wpsie + wpsielen;\n\n\t\t\tremainder_ielen = cur_network->IELength - wps_offset - wpsielen;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\t\t\tif (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {\n\t\t\t\tif (pmlmepriv->wps_beacon_ie && pmlmepriv->wps_beacon_ie_len > 0) {\n\t\t\t\t\t_rtw_memcpy(pframe, cur_network->IEs, wps_offset);\n\t\t\t\t\tpframe += wps_offset;\n\t\t\t\t\tpattrib->pktlen += wps_offset;\n\n\t\t\t\t\t_rtw_memcpy(pframe, pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len);\n\t\t\t\t\tpframe += pmlmepriv->wps_beacon_ie_len;\n\t\t\t\t\tpattrib->pktlen += pmlmepriv->wps_beacon_ie_len;\n\n\t\t\t\t\t/* copy remainder_ie to pframe */\n\t\t\t\t\t_rtw_memcpy(pframe, premainder_ie, remainder_ielen);\n\t\t\t\t\tpframe += remainder_ielen;\n\t\t\t\t\tpattrib->pktlen += remainder_ielen;\n\t\t\t\t} else {\n\t\t\t\t\t_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);\n\t\t\t\t\tpframe += cur_network->IELength;\n\t\t\t\t\tpattrib->pktlen += cur_network->IELength;\n\t\t\t\t}\n\t\t\t} else\n#endif /* CONFIG_IOCTL_CFG80211 */\n\t\t\t{\n\t\t\t\tpframe_wscie = pframe + wps_offset;\n\t\t\t\t_rtw_memcpy(pframe, cur_network->IEs, wps_offset + wpsielen);\n\t\t\t\tpframe += (wps_offset + wpsielen);\n\t\t\t\tpattrib->pktlen += (wps_offset + wpsielen);\n\n\t\t\t\t/* now pframe is end of wsc ie, insert Primary Device Type & Device Name */\n\t\t\t\t/*\tPrimary Device Type */\n\t\t\t\t/*\tType: */\n\t\t\t\t*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);\n\t\t\t\tinsert_len += 2;\n\n\t\t\t\t/*\tLength: */\n\t\t\t\t*(u16 *)(pframe + insert_len) = cpu_to_be16(0x0008);\n\t\t\t\tinsert_len += 2;\n\n\t\t\t\t/*\tValue: */\n\t\t\t\t/*\tCategory ID */\n\t\t\t\t*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);\n\t\t\t\tinsert_len += 2;\n\n\t\t\t\t/*\tOUI */\n\t\t\t\t*(u32 *)(pframe + insert_len) = cpu_to_be32(WPSOUI);\n\t\t\t\tinsert_len += 4;\n\n\t\t\t\t/*\tSub Category ID */\n\t\t\t\t*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);\n\t\t\t\tinsert_len += 2;\n\n\n\t\t\t\t/*\tDevice Name */\n\t\t\t\t/*\tType: */\n\t\t\t\t*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);\n\t\t\t\tinsert_len += 2;\n\n\t\t\t\t/*\tLength: */\n\t\t\t\t*(u16 *)(pframe + insert_len) = cpu_to_be16(pwdinfo->device_name_len);\n\t\t\t\tinsert_len += 2;\n\n\t\t\t\t/*\tValue: */\n\t\t\t\t_rtw_memcpy(pframe + insert_len, pwdinfo->device_name, pwdinfo->device_name_len);\n\t\t\t\tinsert_len += pwdinfo->device_name_len;\n\n\n\t\t\t\t/* update wsc ie length */\n\t\t\t\t*(pframe_wscie + 1) = (wpsielen - 2) + insert_len;\n\n\t\t\t\t/* pframe move to end */\n\t\t\t\tpframe += insert_len;\n\t\t\t\tpattrib->pktlen += insert_len;\n\n\t\t\t\t/* copy remainder_ie to pframe */\n\t\t\t\t_rtw_memcpy(pframe, premainder_ie, remainder_ielen);\n\t\t\t\tpframe += remainder_ielen;\n\t\t\t\tpattrib->pktlen += remainder_ielen;\n\t\t\t}\n\t\t} else\n#endif /* CONFIG_P2P */\n\t\t{\n\t\t\tint len_diff;\n\t\t\t_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);\n\t\t\tlen_diff = update_hidden_ssid(\n\t\t\t\t\t   pframe + _BEACON_IE_OFFSET_\n\t\t\t\t   , cur_network->IELength - _BEACON_IE_OFFSET_\n\t\t\t\t\t   , pmlmeinfo->hidden_ssid_mode\n\t\t\t\t   );\n\t\t\tpframe += (cur_network->IELength + len_diff);\n\t\t\tpattrib->pktlen += (cur_network->IELength + len_diff);\n\t\t}\n\n\t\t{\n\t\t\tu8 *wps_ie;\n\t\t\tuint wps_ielen;\n\t\t\tu8 sr = 0;\n\t\t\twps_ie = rtw_get_wps_ie(pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_,\n\t\t\t\tpattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_, NULL, &wps_ielen);\n\t\t\tif (wps_ie && wps_ielen > 0)\n\t\t\t\trtw_get_wps_attr_content(wps_ie,  wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);\n\t\t\tif (sr != 0)\n\t\t\t\tset_fwstate(pmlmepriv, WIFI_UNDER_WPS);\n\t\t\telse\n\t\t\t\t_clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS);\n\t\t}\n\n#ifdef CONFIG_RTW_80211K\n\t\tpframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_,\n\t\t\tsizeof(padapter->rmpriv.rm_en_cap_def),\n\t\t\tpadapter->rmpriv.rm_en_cap_def, &pattrib->pktlen);\n#endif\n\n#ifdef CONFIG_P2P\n\t\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\t\tu32 len;\n#ifdef CONFIG_IOCTL_CFG80211\n\t\t\tif (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {\n\t\t\t\tlen = pmlmepriv->p2p_beacon_ie_len;\n\t\t\t\tif (pmlmepriv->p2p_beacon_ie && len > 0)\n\t\t\t\t\t_rtw_memcpy(pframe, pmlmepriv->p2p_beacon_ie, len);\n\t\t\t} else\n#endif /* CONFIG_IOCTL_CFG80211 */\n\t\t\t{\n\t\t\t\tlen = build_beacon_p2p_ie(pwdinfo, pframe);\n\t\t\t}\n\n\t\t\tpframe += len;\n\t\t\tpattrib->pktlen += len;\n\n#ifdef CONFIG_MCC_MODE\n\t\t\tpframe = rtw_hal_mcc_append_go_p2p_ie(padapter, pframe, &pattrib->pktlen);\n#endif /* CONFIG_MCC_MODE*/\n\n#ifdef CONFIG_WFD\n\t\t\tlen = rtw_append_beacon_wfd_ie(padapter, pframe);\n\t\t\tpframe += len;\n\t\t\tpattrib->pktlen += len;\n#endif\n\t\t}\n#endif /* CONFIG_P2P */\n#ifdef CONFIG_RTW_REPEATER_SON\n\t\trtw_rson_append_ie(padapter, pframe, &pattrib->pktlen);\n#endif\n#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE\n\t\tpattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_BEACON_VENDOR_IE_BIT);\n#endif\n\n#ifdef CONFIG_RTL8812A \n\t\tpframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen );\n#endif/*CONFIG_RTL8812A*/\n\n\t\tgoto _issue_bcn;\n\n\t}\n\n\t/* below for ad-hoc mode */\n\n\t/* timestamp will be inserted by hardware */\n\tpframe += 8;\n\tpattrib->pktlen += 8;\n\n\t/* beacon interval: 2 bytes */\n\n\t_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);\n\n\tpframe += 2;\n\tpattrib->pktlen += 2;\n\n\t/* capability info: 2 bytes */\n\n\t_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);\n\n\tpframe += 2;\n\tpattrib->pktlen += 2;\n\n\t/* SSID */\n\tpframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen);\n\n\t/* supported rates... */\n\trate_len = rtw_get_rateset_len(cur_network->SupportedRates);\n\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pattrib->pktlen);\n\n\t/* DS parameter set */\n\tpframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen);\n\n\t/* if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) */\n\t{\n\t\tu8 erpinfo = 0;\n\t\tu32 ATIMWindow;\n\t\t/* IBSS Parameter Set... */\n\t\t/* ATIMWindow = cur->Configuration.ATIMWindow; */\n\t\tATIMWindow = 0;\n\t\tpframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen);\n\n\t\t/* ERP IE */\n\t\tpframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen);\n\t}\n\n\n\t/* EXTERNDED SUPPORTED RATE */\n\tif (rate_len > 8)\n\t\tpframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen);\n\n\n\t/* todo:HT for adhoc */\n\n_issue_bcn:\n\n#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)\n\tpmlmepriv->update_bcn = _FALSE;\n\n\t_exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);\n#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */\n\n\tif ((pattrib->pktlen + TXDESC_SIZE) > MAX_BEACON_LEN) {\n\t\tRTW_ERR(\"beacon frame too large ,len(%d,%d)\\n\",\n\t\t\t(pattrib->pktlen + TXDESC_SIZE), MAX_BEACON_LEN);\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\t/* RTW_INFO(\"issue bcn_sz=%d\\n\", pattrib->last_txcmdsz); */\n\tif (timeout_ms > 0)\n\t\tdump_mgntframe_and_wait(padapter, pmgntframe, timeout_ms);\n\telse\n\t\tdump_mgntframe(padapter, pmgntframe);\n\n}\n\nvoid issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq)\n{\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tunsigned char\t\t\t\t\t*mac, *bssid;\n\tstruct xmit_priv\t*pxmitpriv = &(padapter->xmitpriv);\n#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)\n\tu8 *pwps_ie;\n\tuint wps_ielen;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t\t*cur_network = &(pmlmeinfo->network);\n\tunsigned int\trate_len;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n#endif /* CONFIG_P2P */\n\n\t/* RTW_INFO(\"%s\\n\", __FUNCTION__); */\n\n\tif (da == NULL)\n\t\treturn;\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\treturn;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL) {\n\t\tRTW_INFO(\"%s, alloc mgnt frame fail\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tmac = adapter_mac_addr(padapter);\n\tbssid = cur_network->MacAddress;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\t_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(fctrl, WIFI_PROBERSP);\n\n\tpattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = pattrib->hdrlen;\n\tpframe += pattrib->hdrlen;\n\n\n\tif (cur_network->IELength > MAX_IE_SZ)\n\t\treturn;\n\n#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)\n\tif ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {\n\t\tpwps_ie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wps_ielen);\n\n\t\t/* inerset & update wps_probe_resp_ie */\n\t\tif ((pmlmepriv->wps_probe_resp_ie != NULL) && pwps_ie && (wps_ielen > 0)) {\n\t\t\tuint wps_offset, remainder_ielen;\n\t\t\tu8 *premainder_ie;\n\n\t\t\twps_offset = (uint)(pwps_ie - cur_network->IEs);\n\n\t\t\tpremainder_ie = pwps_ie + wps_ielen;\n\n\t\t\tremainder_ielen = cur_network->IELength - wps_offset - wps_ielen;\n\n\t\t\t_rtw_memcpy(pframe, cur_network->IEs, wps_offset);\n\t\t\tpframe += wps_offset;\n\t\t\tpattrib->pktlen += wps_offset;\n\n\t\t\twps_ielen = (uint)pmlmepriv->wps_probe_resp_ie[1];/* to get ie data len */\n\t\t\tif ((wps_offset + wps_ielen + 2) <= MAX_IE_SZ) {\n\t\t\t\t_rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, wps_ielen + 2);\n\t\t\t\tpframe += wps_ielen + 2;\n\t\t\t\tpattrib->pktlen += wps_ielen + 2;\n\t\t\t}\n\n\t\t\tif ((wps_offset + wps_ielen + 2 + remainder_ielen) <= MAX_IE_SZ) {\n\t\t\t\t_rtw_memcpy(pframe, premainder_ie, remainder_ielen);\n\t\t\t\tpframe += remainder_ielen;\n\t\t\t\tpattrib->pktlen += remainder_ielen;\n\t\t\t}\n\t\t} else {\n\t\t\t_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);\n\t\t\tpframe += cur_network->IELength;\n\t\t\tpattrib->pktlen += cur_network->IELength;\n\t\t}\n\n\t\t/* retrieve SSID IE from cur_network->Ssid */\n\t\t{\n\t\t\tu8 *ssid_ie;\n\t\t\tsint ssid_ielen;\n\t\t\tsint ssid_ielen_diff;\n\t\t\tu8 buf[MAX_IE_SZ];\n\t\t\tu8 *ies = pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\t\t\tssid_ie = rtw_get_ie(ies + _FIXED_IE_LENGTH_, _SSID_IE_, &ssid_ielen,\n\t\t\t\t     (pframe - ies) - _FIXED_IE_LENGTH_);\n\n\t\t\tssid_ielen_diff = cur_network->Ssid.SsidLength - ssid_ielen;\n\n\t\t\tif (ssid_ie &&  cur_network->Ssid.SsidLength) {\n\t\t\t\tuint remainder_ielen;\n\t\t\t\tu8 *remainder_ie;\n\t\t\t\tremainder_ie = ssid_ie + 2;\n\t\t\t\tremainder_ielen = (pframe - remainder_ie);\n\n\t\t\t\tif (remainder_ielen > MAX_IE_SZ) {\n\t\t\t\t\tRTW_WARN(FUNC_ADPT_FMT\" remainder_ielen > MAX_IE_SZ\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\t\t\tremainder_ielen = MAX_IE_SZ;\n\t\t\t\t}\n\n\t\t\t\t_rtw_memcpy(buf, remainder_ie, remainder_ielen);\n\t\t\t\t_rtw_memcpy(remainder_ie + ssid_ielen_diff, buf, remainder_ielen);\n\t\t\t\t*(ssid_ie + 1) = cur_network->Ssid.SsidLength;\n\t\t\t\t_rtw_memcpy(ssid_ie + 2, cur_network->Ssid.Ssid, cur_network->Ssid.SsidLength);\n\n\t\t\t\tpframe += ssid_ielen_diff;\n\t\t\t\tpattrib->pktlen += ssid_ielen_diff;\n\t\t\t}\n\t\t}\n#ifdef CONFIG_RTW_REPEATER_SON\n\t\trtw_rson_append_ie(padapter, pframe, &pattrib->pktlen);\n#endif\n#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE\n\t\tpattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_PROBERESP_VENDOR_IE_BIT);\n#endif\n\t} else\n#endif\n\t{\n\n\t\t/* timestamp will be inserted by hardware */\n\t\tpframe += 8;\n\t\tpattrib->pktlen += 8;\n\n\t\t/* beacon interval: 2 bytes */\n\n\t\t_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);\n\n\t\tpframe += 2;\n\t\tpattrib->pktlen += 2;\n\n\t\t/* capability info: 2 bytes */\n\n\t\t_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);\n\n\t\tpframe += 2;\n\t\tpattrib->pktlen += 2;\n\n\t\t/* below for ad-hoc mode */\n\n\t\t/* SSID */\n\t\tpframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen);\n\n\t\t/* supported rates... */\n\t\trate_len = rtw_get_rateset_len(cur_network->SupportedRates);\n\t\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pattrib->pktlen);\n\n\t\t/* DS parameter set */\n\t\tpframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen);\n\n\t\tif ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {\n\t\t\tu8 erpinfo = 0;\n\t\t\tu32 ATIMWindow;\n\t\t\t/* IBSS Parameter Set... */\n\t\t\t/* ATIMWindow = cur->Configuration.ATIMWindow; */\n\t\t\tATIMWindow = 0;\n\t\t\tpframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen);\n\n\t\t\t/* ERP IE */\n\t\t\tpframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen);\n\t\t}\n\n\n\t\t/* EXTERNDED SUPPORTED RATE */\n\t\tif (rate_len > 8)\n\t\t\tpframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen);\n\n\n\t\t/* todo:HT for adhoc */\n\n\t}\n\n#ifdef CONFIG_RTW_80211K\n\tpframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_,\n\t\tsizeof(padapter->rmpriv.rm_en_cap_def),\n\t\tpadapter->rmpriv.rm_en_cap_def, &pattrib->pktlen);\n#endif\n\n#ifdef CONFIG_P2P\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)\n\t    /* IOT issue, When wifi_spec is not set, send probe_resp with P2P IE even if probe_req has no P2P IE */\n\t    && (is_valid_p2p_probereq || !padapter->registrypriv.wifi_spec)) {\n\t\tu32 len;\n#ifdef CONFIG_IOCTL_CFG80211\n\t\tif (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {\n\t\t\t/* if pwdinfo->role == P2P_ROLE_DEVICE will call issue_probersp_p2p() */\n\t\t\tlen = pmlmepriv->p2p_go_probe_resp_ie_len;\n\t\t\tif (pmlmepriv->p2p_go_probe_resp_ie && len > 0)\n\t\t\t\t_rtw_memcpy(pframe, pmlmepriv->p2p_go_probe_resp_ie, len);\n\t\t} else\n#endif /* CONFIG_IOCTL_CFG80211 */\n\t\t{\n\t\t\tlen = build_probe_resp_p2p_ie(pwdinfo, pframe);\n\t\t}\n\n\t\tpframe += len;\n\t\tpattrib->pktlen += len;\n\n#ifdef CONFIG_MCC_MODE\n\t\tpframe = rtw_hal_mcc_append_go_p2p_ie(padapter, pframe, &pattrib->pktlen);\n#endif /* CONFIG_MCC_MODE*/\n\n#ifdef CONFIG_WFD\n\t\tlen = rtw_append_probe_resp_wfd_ie(padapter, pframe);\n\t\tpframe += len;\n\t\tpattrib->pktlen += len;\n#endif\n\t}\n#endif /* CONFIG_P2P */\n\n\n#ifdef CONFIG_AUTO_AP_MODE\n\t{\n\t\tstruct sta_info\t*psta;\n\t\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\t\tRTW_INFO(\"(%s)\\n\", __FUNCTION__);\n\n\t\t/* check rc station */\n\t\tpsta = rtw_get_stainfo(pstapriv, da);\n\t\tif (psta && psta->isrc && psta->pid > 0) {\n\t\t\tu8 RC_OUI[4] = {0x00, 0xE0, 0x4C, 0x0A};\n\t\t\tu8 RC_INFO[14] = {0};\n\t\t\t/* EID[1] + EID_LEN[1] + RC_OUI[4] + MAC[6] + PairingID[2] + ChannelNum[2] */\n\t\t\tu16 cu_ch = (u16)cur_network->Configuration.DSConfig;\n\n\t\t\tRTW_INFO(\"%s, reply rc(pid=0x%x) device \"MAC_FMT\" in ch=%d\\n\", __FUNCTION__,\n\t\t\t\t psta->pid, MAC_ARG(psta->cmn.mac_addr), cu_ch);\n\n\t\t\t/* append vendor specific ie */\n\t\t\t_rtw_memcpy(RC_INFO, RC_OUI, sizeof(RC_OUI));\n\t\t\t_rtw_memcpy(&RC_INFO[4], mac, ETH_ALEN);\n\t\t\t_rtw_memcpy(&RC_INFO[10], (u8 *)&psta->pid, 2);\n\t\t\t_rtw_memcpy(&RC_INFO[12], (u8 *)&cu_ch, 2);\n\n\t\t\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, sizeof(RC_INFO), RC_INFO, &pattrib->pktlen);\n\t\t}\n\t}\n#endif /* CONFIG_AUTO_AP_MODE */\n\n#ifdef CONFIG_RTL8812A \n\tpframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen);\n#endif/*CONFIG_RTL8812A*/\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\n\tdump_mgntframe(padapter, pmgntframe);\n\n\treturn;\n\n}\n\nint _issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int wait_ack)\n{\n\tint ret = _FAIL;\n\tstruct xmit_frame\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t*pattrib;\n\tunsigned char\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t*fctrl;\n\tunsigned char\t\t\t*mac;\n\tunsigned char\t\t\tbssrate[NumRates];\n\tstruct xmit_priv\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tint\tbssrate_len = 0;\n\tu8\tbc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n#endif\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\tgoto exit;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI\n\tif ((pwdev_priv->pno_mac_addr[0] != 0xFF)\n\t    && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE)\n\t    && (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _FALSE))\n\t\tmac = pwdev_priv->pno_mac_addr;\n\telse\n#endif\n\tmac = adapter_mac_addr(padapter);\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\tif (da) {\n\t\t/*\tunicast probe request frame */\n\t\t_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);\n\t} else {\n\t\t/*\tbroadcast probe request frame */\n\t\t_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN);\n\t}\n\n\t_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);\n\n#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI\n\tif ((pwdev_priv->pno_mac_addr[0] != 0xFF)\n\t    && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE)\n\t    && (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _FALSE)) {\n#ifdef CONFIG_RTW_DEBUG\n\t\tRTW_DBG(\"%s pno_scan_seq_num: %d\\n\", __func__,\n\t\t\t pwdev_priv->pno_scan_seq_num);\n#endif\n\t\tSetSeqNum(pwlanhdr, pwdev_priv->pno_scan_seq_num);\n\t\tpattrib->seqnum = pwdev_priv->pno_scan_seq_num;\n\t\tpattrib->qos_en = 1;\n\t\tpwdev_priv->pno_scan_seq_num++;\n\t} else\n#endif\n\t{\n\t\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\t\tpmlmeext->mgnt_seq++;\n\t}\n\tset_frame_sub_type(pframe, WIFI_PROBEREQ);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tif (pssid && !MLME_IS_MESH(padapter))\n\t\tpframe = rtw_set_ie(pframe, _SSID_IE_, pssid->SsidLength, pssid->Ssid, &(pattrib->pktlen));\n\telse\n\t\tpframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &(pattrib->pktlen));\n\n\tget_rate_set(padapter, bssrate, &bssrate_len);\n\n\tif (bssrate_len > 8) {\n\t\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen));\n\t\tpframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen));\n\t} else\n\t\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));\n\n\tif (ch)\n\t\tpframe = rtw_set_ie(pframe, _DSSET_IE_, 1, &ch, &pattrib->pktlen);\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(padapter)) {\n\t\tif (pssid)\n\t\t\tpframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, pssid->Ssid, pssid->SsidLength);\n\t\telse\n\t\t\tpframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, NULL, 0);\n\t}\n#endif\n\n\tif (append_wps) {\n\t\t/* add wps_ie for wps2.0 */\n\t\tif (pmlmepriv->wps_probe_req_ie_len > 0 && pmlmepriv->wps_probe_req_ie) {\n\t\t\t_rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len);\n\t\t\tpframe += pmlmepriv->wps_probe_req_ie_len;\n\t\t\tpattrib->pktlen += pmlmepriv->wps_probe_req_ie_len;\n\t\t\t/* pmlmepriv->wps_probe_req_ie_len = 0 ; */ /* reset to zero */\n\t\t}\n\t}\n#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE\n\tpattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_PROBEREQ_VENDOR_IE_BIT);\n#endif\n\n#ifdef CONFIG_RTL8812A \n\tpframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen );\n#endif/*CONFIG_RTL8812A*/\n\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\n\tif (wait_ack)\n\t\tret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);\n\telse {\n\t\tdump_mgntframe(padapter, pmgntframe);\n\t\tret = _SUCCESS;\n\t}\n\nexit:\n\treturn ret;\n}\n\ninline void issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da)\n{\n\t_issue_probereq(padapter, pssid, da, 0, 1, _FALSE);\n}\n\n/*\n * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT\n * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX\n * try_cnt means the maximal TX count to try\n */\nint issue_probereq_ex(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps,\n\t\t      int try_cnt, int wait_ms)\n{\n\tint ret = _FAIL;\n\tint i = 0;\n\tsystime start = rtw_get_current_time();\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\tgoto exit;\n\n\tdo {\n\t\tret = _issue_probereq(padapter, pssid, da, ch, append_wps, wait_ms > 0 ? _TRUE : _FALSE);\n\n\t\ti++;\n\n\t\tif (RTW_CANNOT_RUN(padapter))\n\t\t\tbreak;\n\n\t\tif (i < try_cnt && wait_ms > 0 && ret == _FAIL)\n\t\t\trtw_msleep_os(wait_ms);\n\n\t} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));\n\n\tif (ret != _FAIL) {\n\t\tret = _SUCCESS;\n#ifndef DBG_XMIT_ACK\n\t\tgoto exit;\n#endif\n\t}\n\n\tif (try_cnt && wait_ms) {\n\t\tif (da)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" to \"MAC_FMT\", ch:%u%s, %d/%d in %u ms\\n\",\n\t\t\t\tFUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),\n\t\t\t\tret == _SUCCESS ? \", acked\" : \"\", i, try_cnt, rtw_get_passing_time_ms(start));\n\t\telse\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\", ch:%u%s, %d/%d in %u ms\\n\",\n\t\t\t\tFUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),\n\t\t\t\tret == _SUCCESS ? \", acked\" : \"\", i, try_cnt, rtw_get_passing_time_ms(start));\n\t}\nexit:\n\treturn ret;\n}\n\n/* if psta == NULL, indiate we are station(client) now... */\nvoid issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status)\n{\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tunsigned int\t\t\t\t\tval32;\n\tunsigned short\t\t\t\tval16;\n\tint use_shared_key = 0;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\treturn;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_AUTH);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\n\tif (psta) { /* for AP mode */\n#ifdef CONFIG_NATIVEAP_MLME\n\n\t\t_rtw_memcpy(pwlanhdr->addr1, psta->cmn.mac_addr, ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);\n\n\n\t\t/* setting auth algo number */\n\t\tval16 = (u16)psta->authalg;\n\n\t\tif (status != _STATS_SUCCESSFUL_)\n\t\t\tval16 = 0;\n\n\t\tif (val16)\t{\n\t\t\tval16 = cpu_to_le16(val16);\n\t\t\tuse_shared_key = 1;\n\t\t}\n\n\t\tpframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));\n\n\t\t/* setting auth seq number */\n\t\tval16 = (u16)psta->auth_seq;\n\t\tval16 = cpu_to_le16(val16);\n\t\tpframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));\n\n\t\t/* setting status code... */\n\t\tval16 = status;\n\t\tval16 = cpu_to_le16(val16);\n\t\tpframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen));\n\n\t\t/* added challenging text... */\n\t\tif ((psta->auth_seq == 2) && (psta->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1))\n\t\t\tpframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, psta->chg_txt, &(pattrib->pktlen));\n#endif\n\t} else {\n\t\t_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);\n\n#ifdef CONFIG_RTW_80211R\n\t\tif (rtw_ft_roam(padapter)) {\n\t\t\t/* 2: 802.11R FTAA */\n\t\t\tval16 = cpu_to_le16(2);\n\t\t} else\n#endif\n\t\t{\n\t\t\t/* setting auth algo number */\n\t\t\tval16 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) ? 1 : 0;\t/* 0:OPEN System, 1:Shared key */\n\t\t\tif (val16) {\n\t\t\t\tval16 = cpu_to_le16(val16);\n\t\t\t\tuse_shared_key = 1;\n\t\t\t}\n\t\t}\n\n\t\t/* RTW_INFO(\"%s auth_algo= %s auth_seq=%d\\n\",__FUNCTION__,(pmlmeinfo->auth_algo==0)?\"OPEN\":\"SHARED\",pmlmeinfo->auth_seq); */\n\n\t\t/* setting IV for auth seq #3 */\n\t\tif ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) {\n\t\t\t/* RTW_INFO(\"==> iv(%d),key_index(%d)\\n\",pmlmeinfo->iv,pmlmeinfo->key_index); */\n\t\t\tval32 = ((pmlmeinfo->iv++) | (pmlmeinfo->key_index << 30));\n\t\t\tval32 = cpu_to_le32(val32);\n\t\t\tpframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *)&val32, &(pattrib->pktlen));\n\n\t\t\tpattrib->iv_len = 4;\n\t\t}\n\n\t\tpframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));\n\n\t\t/* setting auth seq number */\n\t\tval16 = pmlmeinfo->auth_seq;\n\t\tval16 = cpu_to_le16(val16);\n\t\tpframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));\n\n\n\t\t/* setting status code... */\n\t\tval16 = status;\n\t\tval16 = cpu_to_le16(val16);\n\t\tpframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen));\n\n#ifdef CONFIG_RTW_80211R\n\t\trtw_ft_build_auth_req_ies(padapter, pattrib, &pframe);\n#endif\n\n\t\t/* then checking to see if sending challenging text... */\n\t\tif ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) {\n\t\t\tpframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, pmlmeinfo->chg_txt, &(pattrib->pktlen));\n\n\t\t\tSetPrivacy(fctrl);\n\n\t\t\tpattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\t\t\tpattrib->encrypt = _WEP40_;\n\n\t\t\tpattrib->icv_len = 4;\n\n\t\t\tpattrib->pktlen += pattrib->icv_len;\n\n\t\t}\n\n\t}\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\trtw_wep_encrypt(padapter, (u8 *)pmgntframe);\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\tdump_mgntframe(padapter, pmgntframe);\n\n\treturn;\n}\n\n\nvoid issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type)\n{\n#ifdef CONFIG_AP_MODE\n\tstruct xmit_frame\t*pmgntframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tstruct pkt_attrib *pattrib;\n\tunsigned char\t*pbuf, *pframe;\n\tunsigned short val, ie_status;\n\tunsigned short *fctrl;\n\tstruct xmit_priv *pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);\n\tu8 *ie = pnetwork->IEs;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n#ifdef CONFIG_WFD\n\tu32\t\t\t\t\twfdielen = 0;\n#endif\n\n#endif /* CONFIG_P2P */\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\treturn;\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->cmn.mac_addr, ETH_ALEN);\n\t_rtw_memcpy((void *)get_addr2_ptr(pwlanhdr), adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tif ((pkt_type == WIFI_ASSOCRSP) || (pkt_type == WIFI_REASSOCRSP))\n\t\tset_frame_sub_type(pwlanhdr, pkt_type);\n\telse\n\t\treturn;\n\n\tpattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen += pattrib->hdrlen;\n\tpframe += pattrib->hdrlen;\n\n\t/* capability */\n\tval = *(unsigned short *)rtw_get_capability_from_ie(ie);\n\n\tpframe = rtw_set_fixed_ie(pframe, _CAPABILITY_ , (unsigned char *)&val, &(pattrib->pktlen));\n\n\tie_status = cpu_to_le16(status);\n\tpframe = rtw_set_fixed_ie(pframe , _STATUS_CODE_ , (unsigned char *)&ie_status, &(pattrib->pktlen));\n\n\tval = cpu_to_le16(pstat->cmn.aid | BIT(14) | BIT(15));\n\tpframe = rtw_set_fixed_ie(pframe, _ASOC_ID_ , (unsigned char *)&val, &(pattrib->pktlen));\n\n\tif (pstat->bssratelen <= 8)\n\t\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, pstat->bssratelen, pstat->bssrateset, &(pattrib->pktlen));\n\telse {\n\t\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pstat->bssrateset, &(pattrib->pktlen));\n\t\tpframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (pstat->bssratelen - 8), pstat->bssrateset + 8, &(pattrib->pktlen));\n\t}\n\n#ifdef CONFIG_IEEE80211W\n\tif (status == _STATS_REFUSED_TEMPORARILY_) {\n\t\tu8 timeout_itvl[5];\n\t\tu32 timeout_interval = 3000;\n\t\t/* Association Comeback time */\n\t\ttimeout_itvl[0] = 0x03;\n\t\ttimeout_interval = cpu_to_le32(timeout_interval);\n\t\t_rtw_memcpy(timeout_itvl + 1, &timeout_interval, 4);\n\t\tpframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen));\n\t}\n#endif /* CONFIG_IEEE80211W */\n\n#ifdef CONFIG_80211N_HT\n\tif ((pstat->flags & WLAN_STA_HT) && (pmlmepriv->htpriv.ht_option)) {\n\t\tuint ie_len = 0;\n\n\t\t/* FILL HT CAP INFO IE */\n\t\t/* p = hostapd_eid_ht_capabilities_info(hapd, p); */\n\t\tpbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));\n\t\tif (pbuf && ie_len > 0) {\n\t\t\t_rtw_memcpy(pframe, pbuf, ie_len + 2);\n\t\t\tpframe += (ie_len + 2);\n\t\t\tpattrib->pktlen += (ie_len + 2);\n\t\t}\n\n\t\t/* FILL HT ADD INFO IE */\n\t\t/* p = hostapd_eid_ht_operation(hapd, p); */\n\t\tpbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));\n\t\tif (pbuf && ie_len > 0) {\n\t\t\t_rtw_memcpy(pframe, pbuf, ie_len + 2);\n\t\t\tpframe += (ie_len + 2);\n\t\t\tpattrib->pktlen += (ie_len + 2);\n\t\t}\n\n\t}\n#endif\n\n\t/*adding EXT_CAPAB_IE */\n\tif (pmlmepriv->ext_capab_ie_len > 0) {\n\t\tuint ie_len = 0;\n\n\t\tpbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_CAP_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));\n\t\tif (pbuf && ie_len > 0) {\n\t\t\t_rtw_memcpy(pframe, pbuf, ie_len + 2);\n\t\t\tpframe += (ie_len + 2);\n\t\t\tpattrib->pktlen += (ie_len + 2);\n\t\t}\n\t}\n\n#ifdef CONFIG_80211AC_VHT\n\tif ((pstat->flags & WLAN_STA_VHT) && (pmlmepriv->vhtpriv.vht_option)\n\t    && (pstat->wpa_pairwise_cipher != WPA_CIPHER_TKIP)\n\t    && (pstat->wpa2_pairwise_cipher != WPA_CIPHER_TKIP)) {\n\t\tu32 ie_len = 0;\n\n\t\t/* FILL VHT CAP IE */\n\t\tpbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));\n\t\tif (pbuf && ie_len > 0) {\n\t\t\t_rtw_memcpy(pframe, pbuf, ie_len + 2);\n\t\t\tpframe += (ie_len + 2);\n\t\t\tpattrib->pktlen += (ie_len + 2);\n\t\t}\n\n\t\t/* FILL VHT OPERATION IE */\n\t\tpbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTOperation, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));\n\t\tif (pbuf && ie_len > 0) {\n\t\t\t_rtw_memcpy(pframe, pbuf, ie_len + 2);\n\t\t\tpframe += (ie_len + 2);\n\t\t\tpattrib->pktlen += (ie_len + 2);\n\t\t}\n\t}\n#endif /* CONFIG_80211AC_VHT */\n\n\t/* FILL WMM IE */\n\tif ((pstat->flags & WLAN_STA_WME) && (pmlmepriv->qospriv.qos_option)) {\n\t\tuint ie_len = 0;\n\t\tunsigned char WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01};\n\n\t\tfor (pbuf = ie + _BEACON_IE_OFFSET_; ; pbuf += (ie_len + 2)) {\n\t\t\tpbuf = rtw_get_ie(pbuf, _VENDOR_SPECIFIC_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2)));\n\t\t\tif (pbuf && _rtw_memcmp(pbuf + 2, WMM_PARA_IE, 6)) {\n\t\t\t\t_rtw_memcpy(pframe, pbuf, ie_len + 2);\n\t\t\t\tpframe += (ie_len + 2);\n\t\t\t\tpattrib->pktlen += (ie_len + 2);\n\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif ((pbuf == NULL) || (ie_len == 0))\n\t\t\t\tbreak;\n\t\t}\n\n\t}\n\n\n\tif (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK)\n\t\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen));\n\n\t/* add WPS IE ie for wps 2.0 */\n\tif (pmlmepriv->wps_assoc_resp_ie && pmlmepriv->wps_assoc_resp_ie_len > 0) {\n\t\t_rtw_memcpy(pframe, pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len);\n\n\t\tpframe += pmlmepriv->wps_assoc_resp_ie_len;\n\t\tpattrib->pktlen += pmlmepriv->wps_assoc_resp_ie_len;\n\t}\n\n#ifdef CONFIG_P2P\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && (pstat->is_p2p_device == _TRUE)) {\n\t\tu32 len;\n\n\t\tif (padapter->wdinfo.driver_interface == DRIVER_CFG80211) {\n\t\t\tlen = 0;\n\t\t\tif (pmlmepriv->p2p_assoc_resp_ie && pmlmepriv->p2p_assoc_resp_ie_len > 0) {\n\t\t\t\tlen = pmlmepriv->p2p_assoc_resp_ie_len;\n\t\t\t\t_rtw_memcpy(pframe, pmlmepriv->p2p_assoc_resp_ie, len);\n\t\t\t}\n\t\t} else\n\t\t\tlen = build_assoc_resp_p2p_ie(pwdinfo, pframe, pstat->p2p_status_code);\n\t\tpframe += len;\n\t\tpattrib->pktlen += len;\n\t}\n\n#ifdef CONFIG_WFD\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\twfdielen = rtw_append_assoc_resp_wfd_ie(padapter, pframe);\n\t\tpframe += wfdielen;\n\t\tpattrib->pktlen += wfdielen;\n\t}\n#endif\n\n#endif /* CONFIG_P2P */\n#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE\n\tpattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_ASSOCRESP_VENDOR_IE_BIT);\n#endif\n\n#ifdef CONFIG_RTL8812A \n\tpframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen );\n#endif/*CONFIG_RTL8812A*/\n\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(padapter, pmgntframe);\n\n#endif\n}\n\nvoid _issue_assocreq(_adapter *padapter, u8 is_reassoc)\n{\n\tint ret = _FAIL;\n\tstruct xmit_frame\t\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t\t\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tunsigned short\t\t\t\tval16;\n\tunsigned int\t\t\t\t\ti, j, index = 0;\n\tunsigned char\t\t\t\t\tbssrate[NumRates], sta_bssrate[NumRates];\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\tstruct xmit_priv\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tint\tbssrate_len = 0, sta_bssrate_len = 0;\n\tu8\tvs_ie_length = 0;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\tu8\t\t\t\t\tp2pie[255] = { 0x00 };\n\tu16\t\t\t\t\tp2pielen = 0;\n#ifdef CONFIG_WFD\n\tu32\t\t\t\t\twfdielen = 0;\n#endif\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_DFS\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tu16\tcap;\n\n\t/* Dot H */\n\tu8 pow_cap_ele[2] = { 0x00 };\n\tu8 sup_ch[30 * 2] = {0x00 }, sup_ch_idx = 0, idx_5g = 2;\t/* For supported channel */\n#endif /* CONFIG_DFS */\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\tgoto exit;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\t_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tif (is_reassoc == _TRUE)\n\t\tset_frame_sub_type(pframe, WIFI_REASSOCREQ);\n\telse\n\t\tset_frame_sub_type(pframe, WIFI_ASSOCREQ);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\t/* caps */\n\n#ifdef CONFIG_DFS\n\t_rtw_memcpy(&cap, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2);\n\tcap |= cap_SpecMgmt;\n\t_rtw_memcpy(pframe, &cap, 2);\n#else\n\t_rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2);\n#endif /* CONFIG_DFS */\n\n\tpframe += 2;\n\tpattrib->pktlen += 2;\n\n\t/* listen interval */\n\t/* todo: listen interval for power saving */\n\tval16 = cpu_to_le16(3);\n\t_rtw_memcpy(pframe , (unsigned char *)&val16, 2);\n\tpframe += 2;\n\tpattrib->pktlen += 2;\n\n\t/*Construct Current AP Field for Reassoc-Req only*/\n\tif (is_reassoc == _TRUE) {\n\t\t_rtw_memcpy(pframe, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\t\tpframe += ETH_ALEN;\n\t\tpattrib->pktlen += ETH_ALEN;\n\t}\n\n\t/* SSID */\n\tpframe = rtw_set_ie(pframe, _SSID_IE_,  pmlmeinfo->network.Ssid.SsidLength, pmlmeinfo->network.Ssid.Ssid, &(pattrib->pktlen));\n\n#ifdef CONFIG_DFS\n\t/* Dot H */\n\tif (pmlmeext->cur_channel > 14) {\n\t\tpow_cap_ele[0] = 13;\t/* Minimum transmit power capability */\n\t\tpow_cap_ele[1] = 21;\t/* Maximum transmit power capability */\n\t\tpframe = rtw_set_ie(pframe, EID_PowerCap, 2, pow_cap_ele, &(pattrib->pktlen));\n\n\t\t/* supported channels */\n\t\twhile (sup_ch_idx < rfctl->max_chan_nums && rfctl->channel_set[sup_ch_idx].ChannelNum != 0) {\n\t\t\tif (rfctl->channel_set[sup_ch_idx].ChannelNum <= 14) {\n\t\t\t\t/* TODO: fix 2.4G supported channel when channel doesn't start from 1 and continuous */\n\t\t\t\tsup_ch[0] = 1;\t/* First channel number */\n\t\t\t\tsup_ch[1] = rfctl->channel_set[sup_ch_idx].ChannelNum;\t/* Number of channel */\n\t\t\t} else {\n\t\t\t\tsup_ch[idx_5g++] = rfctl->channel_set[sup_ch_idx].ChannelNum;\n\t\t\t\tsup_ch[idx_5g++] = 1;\n\t\t\t}\n\t\t\tsup_ch_idx++;\n\t\t}\n\t\tpframe = rtw_set_ie(pframe, EID_SupportedChannels, idx_5g, sup_ch, &(pattrib->pktlen));\n\t}\n#endif /* CONFIG_DFS */\n\n\t/* supported rate & extended supported rate */\n\n#if 1\t/* Check if the AP's supported rates are also supported by STA. */\n\tget_rate_set(padapter, sta_bssrate, &sta_bssrate_len);\n\t/* RTW_INFO(\"sta_bssrate_len=%d\\n\", sta_bssrate_len); */\n\n\tif (pmlmeext->cur_channel == 14) /* for JAPAN, channel 14 can only uses B Mode(CCK) */\n\t\tsta_bssrate_len = 4;\n\n\n\t/* for (i = 0; i < sta_bssrate_len; i++) { */\n\t/*\tRTW_INFO(\"sta_bssrate[%d]=%02X\\n\", i, sta_bssrate[i]); */\n\t/* } */\n\n\tfor (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {\n\t\tif (pmlmeinfo->network.SupportedRates[i] == 0)\n\t\t\tbreak;\n\t\tRTW_INFO(\"network.SupportedRates[%d]=%02X\\n\", i, pmlmeinfo->network.SupportedRates[i]);\n\t}\n\n\n\tfor (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {\n\t\tif (pmlmeinfo->network.SupportedRates[i] == 0)\n\t\t\tbreak;\n\n\n\t\t/* Check if the AP's supported rates are also supported by STA. */\n\t\tfor (j = 0; j < sta_bssrate_len; j++) {\n\t\t\t/* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */\n\t\t\tif ((pmlmeinfo->network.SupportedRates[i] | IEEE80211_BASIC_RATE_MASK)\n\t\t\t    == (sta_bssrate[j] | IEEE80211_BASIC_RATE_MASK)) {\n\t\t\t\t/* RTW_INFO(\"match i = %d, j=%d\\n\", i, j); */\n\t\t\t\tbreak;\n\t\t\t} else {\n\t\t\t\t/* RTW_INFO(\"not match: %02X != %02X\\n\", (pmlmeinfo->network.SupportedRates[i]|IEEE80211_BASIC_RATE_MASK), (sta_bssrate[j]|IEEE80211_BASIC_RATE_MASK)); */\n\t\t\t}\n\t\t}\n\n\t\tif (j == sta_bssrate_len) {\n\t\t\t/* the rate is not supported by STA */\n\t\t\tRTW_INFO(\"%s(): the rate[%d]=%02X is not supported by STA!\\n\", __FUNCTION__, i, pmlmeinfo->network.SupportedRates[i]);\n\t\t} else {\n\t\t\t/* the rate is supported by STA */\n\t\t\tbssrate[index++] = pmlmeinfo->network.SupportedRates[i];\n\t\t}\n\t}\n\n\tbssrate_len = index;\n\tRTW_INFO(\"bssrate_len = %d\\n\", bssrate_len);\n\n#else\t/* Check if the AP's supported rates are also supported by STA. */\n#if 0\n\tget_rate_set(padapter, bssrate, &bssrate_len);\n#else\n\tfor (bssrate_len = 0; bssrate_len < NumRates; bssrate_len++) {\n\t\tif (pmlmeinfo->network.SupportedRates[bssrate_len] == 0)\n\t\t\tbreak;\n\n\t\tif (pmlmeinfo->network.SupportedRates[bssrate_len] == 0x2C) /* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */\n\t\t\tbreak;\n\n\t\tbssrate[bssrate_len] = pmlmeinfo->network.SupportedRates[bssrate_len];\n\t}\n#endif\n#endif /* Check if the AP's supported rates are also supported by STA. */\n\n\tif ((bssrate_len == 0) && (pmlmeinfo->network.SupportedRates[0] != 0)) {\n\t\trtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);\n\t\trtw_free_xmitframe(pxmitpriv, pmgntframe);\n\t\tgoto exit; /* don't connect to AP if no joint supported rate */\n\t}\n\n\n\tif (bssrate_len > 8) {\n\t\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen));\n\t\tpframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen));\n\t} else if (bssrate_len > 0)\n\t\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));\n\telse\n\t\tRTW_INFO(\"%s: Connect to AP without 11b and 11g data rate!\\n\", __FUNCTION__);\n\n#ifdef CONFIG_RTW_80211K\n\tif (pmlmeinfo->network.PhyInfo.rm_en_cap[0] /* RM Enabled Capabilities */\n\t\t| pmlmeinfo->network.PhyInfo.rm_en_cap[1]\n\t\t| pmlmeinfo->network.PhyInfo.rm_en_cap[2]\n\t\t| pmlmeinfo->network.PhyInfo.rm_en_cap[3]\n\t\t| pmlmeinfo->network.PhyInfo.rm_en_cap[4])\n\t\tpframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_, 5,\n\t\t\t\t(u8 *)padapter->rmpriv.rm_en_cap_def, &(pattrib->pktlen));\n#endif /* CONFIG_RTW_80211K */\n\n\t/* vendor specific IE, such as WPA, WMM, WPS */\n\tfor (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) {\n\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i);\n\n\t\tswitch (pIE->ElementID) {\n\t\tcase _VENDOR_SPECIFIC_IE_:\n\t\t\tif ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) ||\n\t\t\t    (_rtw_memcmp(pIE->data, WMM_OUI, 4)) ||\n\t\t\t    (_rtw_memcmp(pIE->data, WPS_OUI, 4))) {\n\t\t\t\tvs_ie_length = pIE->Length;\n\t\t\t\tif ((!padapter->registrypriv.wifi_spec) && (_rtw_memcmp(pIE->data, WPS_OUI, 4))) {\n\t\t\t\t\t/* Commented by Kurt 20110629 */\n\t\t\t\t\t/* In some older APs, WPS handshake */\n\t\t\t\t\t/* would be fail if we append vender extensions informations to AP */\n\n\t\t\t\t\tvs_ie_length = 14;\n\t\t\t\t}\n\n\t\t\t\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, vs_ie_length, pIE->data, &(pattrib->pktlen));\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase EID_WPA2:\n#ifdef CONFIG_RTW_80211R\n\t\t\tif ((is_reassoc) && (rtw_ft_roam(padapter))) {\n\t\t\t\trtw_ft_update_rsnie(padapter, _TRUE, pattrib, &pframe);\n\t\t\t} else\n#endif\n\t\t\t{\n#ifdef CONFIG_IOCTL_CFG80211\n\t\t\t\tif (rtw_sec_chk_auth_alg(padapter, WLAN_AUTH_OPEN) &&\n\t\t\t\t\trtw_sec_chk_auth_type(padapter, NL80211_AUTHTYPE_SAE)) {\n\t\t\t\t\ts32 entry = rtw_cached_pmkid(padapter, pmlmepriv->assoc_bssid);\n\n\t\t\t\t\trtw_rsn_sync_pmkid(padapter, (u8 *)pIE, (pIE->Length + 2), entry);\n\t\t\t\t}\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n\t\t\t\tpframe = rtw_set_ie(pframe, EID_WPA2, pIE->Length, pIE->data, &(pattrib->pktlen));\n\t\t\t}\n\t\t\tbreak;\n#ifdef CONFIG_80211N_HT\n\t\tcase EID_HTCapability:\n\t\t\tif (padapter->mlmepriv.htpriv.ht_option == _TRUE) {\n\t\t\t\tif (!(is_ap_in_tkip(padapter))) {\n\t\t\t\t\t_rtw_memcpy(&(pmlmeinfo->HT_caps), pIE->data, sizeof(struct HT_caps_element));\n\n\t\t\t\t\tpmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = cpu_to_le16(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info);\n\n\t\t\t\t\tpframe = rtw_set_ie(pframe, EID_HTCapability, pIE->Length , (u8 *)(&(pmlmeinfo->HT_caps)), &(pattrib->pktlen));\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase EID_EXTCapability:\n\t\t\tif (padapter->mlmepriv.htpriv.ht_option == _TRUE)\n\t\t\t\tpframe = rtw_set_ie(pframe, EID_EXTCapability, pIE->Length, pIE->data, &(pattrib->pktlen));\n\t\t\tbreak;\n#endif /* CONFIG_80211N_HT */\n#ifdef CONFIG_80211AC_VHT\n\t\tcase EID_VHTCapability:\n\t\t\tif (padapter->mlmepriv.vhtpriv.vht_option == _TRUE)\n\t\t\t\tpframe = rtw_set_ie(pframe, EID_VHTCapability, pIE->Length, pIE->data, &(pattrib->pktlen));\n\t\t\tbreak;\n\n\t\tcase EID_OpModeNotification:\n\t\t\tif (padapter->mlmepriv.vhtpriv.vht_option == _TRUE)\n\t\t\t\tpframe = rtw_set_ie(pframe, EID_OpModeNotification, pIE->Length, pIE->data, &(pattrib->pktlen));\n\t\t\tbreak;\n#endif /* CONFIG_80211AC_VHT */\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\ti += (pIE->Length + 2);\n\t}\n\n\tif (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK)\n\t\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen));\n\n\n#ifdef CONFIG_WAPI_SUPPORT\n\trtw_build_assoc_req_wapi_ie(padapter, pframe, pattrib);\n#endif\n\n\n#ifdef CONFIG_P2P\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {\n\t\tif (pmlmepriv->p2p_assoc_req_ie && pmlmepriv->p2p_assoc_req_ie_len > 0) {\n\t\t\t_rtw_memcpy(pframe, pmlmepriv->p2p_assoc_req_ie, pmlmepriv->p2p_assoc_req_ie_len);\n\t\t\tpframe += pmlmepriv->p2p_assoc_req_ie_len;\n\t\t\tpattrib->pktlen += pmlmepriv->p2p_assoc_req_ie_len;\n\t\t}\n\t} else\n#endif /* CONFIG_IOCTL_CFG80211 */\n\t{\n\t\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) {\n\t\t\t/*\tShould add the P2P IE in the association request frame.\t */\n\t\t\t/*\tP2P OUI */\n\n\t\t\tp2pielen = 0;\n\t\t\tp2pie[p2pielen++] = 0x50;\n\t\t\tp2pie[p2pielen++] = 0x6F;\n\t\t\tp2pie[p2pielen++] = 0x9A;\n\t\t\tp2pie[p2pielen++] = 0x09;\t/*\tWFA P2P v1.0 */\n\n\t\t\t/*\tCommented by Albert 20101109 */\n\t\t\t/*\tAccording to the P2P Specification, the association request frame should contain 3 P2P attributes */\n\t\t\t/*\t1. P2P Capability */\n\t\t\t/*\t2. Extended Listen Timing */\n\t\t\t/*\t3. Device Info */\n\t\t\t/*\tCommented by Albert 20110516 */\n\t\t\t/*\t4. P2P Interface */\n\n\t\t\t/*\tP2P Capability */\n\t\t\t/*\tType: */\n\t\t\tp2pie[p2pielen++] = P2P_ATTR_CAPABILITY;\n\n\t\t\t/*\tLength: */\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);\n\t\t\tp2pielen += 2;\n\n\t\t\t/*\tValue: */\n\t\t\t/*\tDevice Capability Bitmap, 1 byte */\n\t\t\tp2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;\n\n\t\t\t/*\tGroup Capability Bitmap, 1 byte */\n\t\t\tif (pwdinfo->persistent_supported)\n\t\t\t\tp2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;\n\t\t\telse\n\t\t\t\tp2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT;\n\n\t\t\t/*\tExtended Listen Timing */\n\t\t\t/*\tType: */\n\t\t\tp2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING;\n\n\t\t\t/*\tLength: */\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004);\n\t\t\tp2pielen += 2;\n\n\t\t\t/*\tValue: */\n\t\t\t/*\tAvailability Period */\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);\n\t\t\tp2pielen += 2;\n\n\t\t\t/*\tAvailability Interval */\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);\n\t\t\tp2pielen += 2;\n\n\t\t\t/*\tDevice Info */\n\t\t\t/*\tType: */\n\t\t\tp2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;\n\n\t\t\t/*\tLength: */\n\t\t\t/*\t21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */\n\t\t\t/*\t+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);\n\t\t\tp2pielen += 2;\n\n\t\t\t/*\tValue: */\n\t\t\t/*\tP2P Device Address */\n\t\t\t_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);\n\t\t\tp2pielen += ETH_ALEN;\n\n\t\t\t/*\tConfig Method */\n\t\t\t/*\tThis field should be big endian. Noted by P2P specification. */\n\t\t\tif ((pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN) ||\n\t\t\t    (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN))\n\t\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_DISPLAY);\n\t\t\telse\n\t\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_PBC);\n\n\t\t\tp2pielen += 2;\n\n\t\t\t/*\tPrimary Device Type */\n\t\t\t/*\tCategory ID */\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);\n\t\t\tp2pielen += 2;\n\n\t\t\t/*\tOUI */\n\t\t\t*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);\n\t\t\tp2pielen += 4;\n\n\t\t\t/*\tSub Category ID */\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);\n\t\t\tp2pielen += 2;\n\n\t\t\t/*\tNumber of Secondary Device Types */\n\t\t\tp2pie[p2pielen++] = 0x00;\t/*\tNo Secondary Device Type List */\n\n\t\t\t/*\tDevice Name */\n\t\t\t/*\tType: */\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);\n\t\t\tp2pielen += 2;\n\n\t\t\t/*\tLength: */\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);\n\t\t\tp2pielen += 2;\n\n\t\t\t/*\tValue: */\n\t\t\t_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len);\n\t\t\tp2pielen += pwdinfo->device_name_len;\n\n\t\t\t/*\tP2P Interface */\n\t\t\t/*\tType: */\n\t\t\tp2pie[p2pielen++] = P2P_ATTR_INTERFACE;\n\n\t\t\t/*\tLength: */\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x000D);\n\t\t\tp2pielen += 2;\n\n\t\t\t/*\tValue: */\n\t\t\t_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN);\t/*\tP2P Device Address */\n\t\t\tp2pielen += ETH_ALEN;\n\n\t\t\tp2pie[p2pielen++] = 1;\t/*\tP2P Interface Address Count */\n\n\t\t\t_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN);\t/*\tP2P Interface Address List */\n\t\t\tp2pielen += ETH_ALEN;\n\n\t\t\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);\n\t\t}\n\t}\n\n#ifdef CONFIG_WFD\n\twfdielen = rtw_append_assoc_req_wfd_ie(padapter, pframe);\n\tpframe += wfdielen;\n\tpattrib->pktlen += wfdielen;\n#endif\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_RTW_REPEATER_SON\n\trtw_rson_append_ie(padapter, pframe, &pattrib->pktlen);\n#endif\n#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE\n\tpattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_ASSOCREQ_VENDOR_IE_BIT);\n#endif\n\n#ifdef CONFIG_RTL8812A \n\tpframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen );\n#endif/*CONFIG_RTL8812A*/\n\n#ifdef CONFIG_RTW_80211R\n\trtw_ft_build_assoc_req_ies(padapter, is_reassoc, pattrib, &pframe);\n#endif\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\tdump_mgntframe(padapter, pmgntframe);\n\n\tret = _SUCCESS;\n\nexit:\n\tif (ret == _SUCCESS)\n\t\trtw_buf_update(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len, (u8 *)pwlanhdr, pattrib->pktlen);\n\telse\n\t\trtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len);\n\n\treturn;\n}\n\nvoid issue_assocreq(_adapter *padapter)\n{\n\t_issue_assocreq(padapter, _FALSE);\n}\n\nvoid issue_reassocreq(_adapter *padapter)\n{\n\t_issue_assocreq(padapter, _TRUE);\n}\n\n/* when wait_ack is ture, this function shoule be called at process context */\nstatic int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ack)\n{\n\tint ret = _FAIL;\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tstruct xmit_priv\t*pxmitpriv;\n\tstruct mlme_ext_priv\t*pmlmeext;\n\tstruct mlme_ext_info\t*pmlmeinfo;\n\tu8 a4_shift;\n\n\t/* RTW_INFO(\"%s:%d\\n\", __FUNCTION__, power_mode); */\n\n\tif (!padapter)\n\t\tgoto exit;\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\tgoto exit;\n\n\tpxmitpriv = &(padapter->xmitpriv);\n\tpmlmeext = &(padapter->mlmeextpriv);\n\tpmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\tpattrib->retry_ctrl = _FALSE;\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\tif (MLME_IS_AP(padapter))\n\t\tSetFrDs(fctrl);\n\telse if (MLME_IS_STA(padapter))\n\t\tSetToDs(fctrl);\n\telse if (MLME_IS_MESH(padapter)) {\n\t\tSetToDs(fctrl);\n\t\tSetFrDs(fctrl);\n\t}\n\n\tif (power_mode)\n\t\tSetPwrMgt(fctrl);\n\n\tif (get_tofr_ds(fctrl) == 3) {\n\t\t_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN);\n\t\ta4_shift = ETH_ALEN;\n\t\tpattrib->hdrlen += ETH_ALEN;\n\t} else {\n\t\t_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\t\ta4_shift = 0;\n\t}\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_DATA_NULL);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift;\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift;\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tif (wait_ack)\n\t\tret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);\n\telse {\n\t\tdump_mgntframe(padapter, pmgntframe);\n\t\tret = _SUCCESS;\n\t}\n\nexit:\n\treturn ret;\n}\n\n/*\n * When wait_ms > 0, this function should be called at process context\n * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT\n * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX\n * try_cnt means the maximal TX count to try\n * da == NULL for station mode\n */\nint issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms)\n{\n\tint ret = _FAIL;\n\tint i = 0;\n\tsystime start = rtw_get_current_time();\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\tgoto exit;\n\n\t/* da == NULL, assum it's null data for sta to ap */\n\tif (da == NULL)\n\t\tda = get_my_bssid(&(pmlmeinfo->network));\n\n\tdo {\n\t\tret = _issue_nulldata(padapter, da, power_mode, wait_ms > 0 ? _TRUE : _FALSE);\n\n\t\ti++;\n\n\t\tif (RTW_CANNOT_RUN(padapter))\n\t\t\tbreak;\n\n\t\tif (i < try_cnt && wait_ms > 0 && ret == _FAIL)\n\t\t\trtw_msleep_os(wait_ms);\n\n\t} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));\n\n\tif (ret != _FAIL) {\n\t\tret = _SUCCESS;\n#ifndef DBG_XMIT_ACK\n\t\tgoto exit;\n#endif\n\t}\n\n\tif (try_cnt && wait_ms) {\n\t\tif (da)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" to \"MAC_FMT\", ch:%u%s, %d/%d in %u ms\\n\",\n\t\t\t\tFUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),\n\t\t\t\tret == _SUCCESS ? \", acked\" : \"\", i, try_cnt, rtw_get_passing_time_ms(start));\n\t\telse\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\", ch:%u%s, %d/%d in %u ms\\n\",\n\t\t\t\tFUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),\n\t\t\t\tret == _SUCCESS ? \", acked\" : \"\", i, try_cnt, rtw_get_passing_time_ms(start));\n\t}\nexit:\n\treturn ret;\n}\n\n/* when wait_ack is ture, this function shoule be called at process context */\nstatic int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int wait_ack)\n{\n\tint ret = _FAIL;\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl, *qc;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8 a4_shift;\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\tgoto exit;\n\n\t/* RTW_INFO(\"%s\\n\", __FUNCTION__); */\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\tpattrib->hdrlen += 2;\n\tpattrib->qos_en = _TRUE;\n\tpattrib->eosp = 1;\n\tpattrib->ack_policy = 0;\n\tpattrib->mdata = 0;\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\tif (MLME_IS_AP(padapter))\n\t\tSetFrDs(fctrl);\n\telse if (MLME_IS_STA(padapter))\n\t\tSetToDs(fctrl);\n\telse if (MLME_IS_MESH(padapter)) {\n\t\tSetToDs(fctrl);\n\t\tSetFrDs(fctrl);\n\t}\n\n\tif (ps)\n\t\tSetPwrMgt(fctrl);\n\n\tif (pattrib->mdata)\n\t\tSetMData(fctrl);\n\n\tif (get_tofr_ds(fctrl) == 3) {\n\t\t_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN);\n\t\ta4_shift = ETH_ALEN;\n\t\tpattrib->hdrlen += ETH_ALEN;\n\t} else {\n\t\t_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\t\ta4_shift = 0;\n\t}\n\n\tqc = (unsigned short *)(pframe + pattrib->hdrlen - 2);\n\n\tSetPriority(qc, tid);\n\n\tSetEOSP(qc, pattrib->eosp);\n\n\tSetAckpolicy(qc, pattrib->ack_policy);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_QOS_DATA_NULL);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift;\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift;\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tif (wait_ack)\n\t\tret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);\n\telse {\n\t\tdump_mgntframe(padapter, pmgntframe);\n\t\tret = _SUCCESS;\n\t}\n\nexit:\n\treturn ret;\n}\n\n/*\n * when wait_ms >0 , this function should be called at process context\n * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT\n * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX\n * try_cnt means the maximal TX count to try\n * da == NULL for station mode\n */\nint issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int try_cnt, int wait_ms)\n{\n\tint ret = _FAIL;\n\tint i = 0;\n\tsystime start = rtw_get_current_time();\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\tgoto exit;\n\n\t/* da == NULL, assum it's null data for sta to ap*/\n\tif (da == NULL)\n\t\tda = get_my_bssid(&(pmlmeinfo->network));\n\n\tdo {\n\t\tret = _issue_qos_nulldata(padapter, da, tid, ps, wait_ms > 0 ? _TRUE : _FALSE);\n\n\t\ti++;\n\n\t\tif (RTW_CANNOT_RUN(padapter))\n\t\t\tbreak;\n\n\t\tif (i < try_cnt && wait_ms > 0 && ret == _FAIL)\n\t\t\trtw_msleep_os(wait_ms);\n\n\t} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));\n\n\tif (ret != _FAIL) {\n\t\tret = _SUCCESS;\n#ifndef DBG_XMIT_ACK\n\t\tgoto exit;\n#endif\n\t}\n\n\tif (try_cnt && wait_ms) {\n\t\tif (da)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" to \"MAC_FMT\", ch:%u%s, %d/%d in %u ms\\n\",\n\t\t\t\tFUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),\n\t\t\t\tret == _SUCCESS ? \", acked\" : \"\", i, try_cnt, rtw_get_passing_time_ms(start));\n\t\telse\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\", ch:%u%s, %d/%d in %u ms\\n\",\n\t\t\t\tFUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),\n\t\t\t\tret == _SUCCESS ? \", acked\" : \"\", i, try_cnt, rtw_get_passing_time_ms(start));\n\t}\nexit:\n\treturn ret;\n}\n\nstatic int _issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason, u8 wait_ack, u8 key_type)\n{\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tint ret = _FAIL;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n#endif /* CONFIG_P2P\t */\n\n\t/* RTW_INFO(\"%s to \"MAC_FMT\"\\n\", __func__, MAC_ARG(da)); */\n\n#ifdef CONFIG_P2P\n\tif (!(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) && (pwdinfo->rx_invitereq_info.scan_op_ch_only)) {\n\t\t_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);\n\t\t_set_timer(&pwdinfo->reset_ch_sitesurvey, 10);\n\t}\n#endif /* CONFIG_P2P */\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\tgoto exit;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\tpattrib->retry_ctrl = _FALSE;\n\tpattrib->key_type = key_type;\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_DEAUTH);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\treason = cpu_to_le16(reason);\n\tpframe = rtw_set_fixed_ie(pframe, _RSON_CODE_ , (unsigned char *)&reason, &(pattrib->pktlen));\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\n\tif (wait_ack)\n\t\tret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);\n\telse {\n\t\tdump_mgntframe(padapter, pmgntframe);\n\t\tret = _SUCCESS;\n\t}\n\nexit:\n\treturn ret;\n}\n\nint issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason)\n{\n\tRTW_INFO(\"%s to \"MAC_FMT\"\\n\", __func__, MAC_ARG(da));\n\treturn _issue_deauth(padapter, da, reason, _FALSE, IEEE80211W_RIGHT_KEY);\n}\n\n#ifdef CONFIG_IEEE80211W\nint issue_deauth_11w(_adapter *padapter, unsigned char *da, unsigned short reason, u8 key_type)\n{\n\tRTW_INFO(\"%s to \"MAC_FMT\"\\n\", __func__, MAC_ARG(da));\n\treturn _issue_deauth(padapter, da, reason, _FALSE, key_type);\n}\n#endif /* CONFIG_IEEE80211W */\n\n/*\n * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT\n * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX\n * try_cnt means the maximal TX count to try\n */\nint issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt,\n\t\t    int wait_ms)\n{\n\tint ret = _FAIL;\n\tint i = 0;\n\tsystime start = rtw_get_current_time();\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\tgoto exit;\n\n\tdo {\n\t\tret = _issue_deauth(padapter, da, reason, wait_ms > 0 ? _TRUE : _FALSE, IEEE80211W_RIGHT_KEY);\n\n\t\ti++;\n\n\t\tif (RTW_CANNOT_RUN(padapter))\n\t\t\tbreak;\n\n\t\tif (i < try_cnt && wait_ms > 0 && ret == _FAIL)\n\t\t\trtw_msleep_os(wait_ms);\n\n\t} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));\n\n\tif (ret != _FAIL) {\n\t\tret = _SUCCESS;\n#ifndef DBG_XMIT_ACK\n\t\tgoto exit;\n#endif\n\t}\n\n\tif (try_cnt && wait_ms) {\n\t\tif (da)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" to \"MAC_FMT\", ch:%u%s, %d/%d in %u ms\\n\",\n\t\t\t\tFUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),\n\t\t\t\tret == _SUCCESS ? \", acked\" : \"\", i, try_cnt, rtw_get_passing_time_ms(start));\n\t\telse\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\", ch:%u%s, %d/%d in %u ms\\n\",\n\t\t\t\tFUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),\n\t\t\t\tret == _SUCCESS ? \", acked\" : \"\", i, try_cnt, rtw_get_passing_time_ms(start));\n\t}\nexit:\n\treturn ret;\n}\n\nvoid issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset)\n{\n\tstruct xmit_frame *pmgntframe;\n\tstruct pkt_attrib *pattrib;\n\tunsigned char\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t*fctrl;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\treturn;\n\n\tRTW_INFO(FUNC_NDEV_FMT\" ra=\"MAC_FMT\", ch:%u, offset:%u\\n\",\n\t\tFUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(ra), new_ch, ch_offset);\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); /* RA */\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); /* TA */\n\t_rtw_memcpy(pwlanhdr->addr3, ra, ETH_ALEN); /* DA = RA */\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\t/* category, action */\n\t{\n\t\tu8 category, action;\n\t\tcategory = RTW_WLAN_CATEGORY_SPECTRUM_MGMT;\n\t\taction = RTW_WLAN_ACTION_SPCT_CHL_SWITCH;\n\n\t\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\t\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));\n\t}\n\n\tpframe = rtw_set_ie_ch_switch(pframe, &(pattrib->pktlen), 0, new_ch, 0);\n\tpframe = rtw_set_ie_secondary_ch_offset(pframe, &(pattrib->pktlen),\n\t\t\thal_ch_offset_to_secondary_ch_offset(ch_offset));\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(padapter, pmgntframe);\n\n}\n\n#ifdef CONFIG_IEEE80211W\nvoid issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid, u8 key_type)\n{\n\tu8\tcategory = RTW_WLAN_CATEGORY_SA_QUERY;\n\tu16\treason_code;\n\tstruct xmit_frame\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t*pattrib;\n\tu8\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tu16\t\t\t\t\t*fctrl;\n\tstruct xmit_priv\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct sta_info\t\t*psta;\n\tstruct sta_priv\t\t*pstapriv = &padapter->stapriv;\n\tstruct registry_priv\t\t*pregpriv = &padapter->registrypriv;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\treturn;\n\n\tRTW_INFO(\"%s, %04x\\n\", __FUNCTION__, tid);\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL) {\n\t\tRTW_INFO(\"%s: alloc_mgtxmitframe fail\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\tpattrib->key_type = key_type;\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\tif (raddr)\n\t\t_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);\n\telse\n\t\t_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &category, &pattrib->pktlen);\n\tpframe = rtw_set_fixed_ie(pframe, 1, &action, &pattrib->pktlen);\n\n\tswitch (action) {\n\tcase 0: /* SA Query req */\n\t\tpframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&pmlmeext->sa_query_seq, &pattrib->pktlen);\n\t\tpmlmeext->sa_query_seq++;\n\t\t/* send sa query request to AP, AP should reply sa query response in 1 second */\n\t\tif (pattrib->key_type == IEEE80211W_RIGHT_KEY) {\n\t\t\tpsta = rtw_get_stainfo(pstapriv, pwlanhdr->addr1);\n\t\t\tif (psta != NULL) {\n\t\t\t\t/* RTW_INFO(\"%s, %d, set dot11w_expire_timer\\n\", __func__, __LINE__); */\n\t\t\t\t_set_timer(&psta->dot11w_expire_timer, 1000);\n\t\t\t}\n\t\t}\n\t\tbreak;\n\n\tcase 1: /* SA Query rsp */\n\t\ttid = cpu_to_le16(tid);\n\t\t/* RTW_INFO(\"rtw_set_fixed_ie, %04x\\n\", tid); */\n\t\tpframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&tid, &pattrib->pktlen);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(padapter, pmgntframe);\n}\n#endif /* CONFIG_IEEE80211W */\n\n/**\n * issue_action_ba - internal function to TX Block Ack action frame\n * @padapter: the adapter to TX\n * @raddr: receiver address\n * @action: Block Ack Action\n * @tid: tid\n * @size: the announced AMPDU buffer size. used by ADDBA_RESP\n * @status: status/reason code. used by ADDBA_RESP, DELBA\n * @initiator: if we are the initiator of AMPDU association. used by DELBA\n * @wait_ack: used xmit ack\n *\n * Returns:\n * _SUCCESS: No xmit ack is used or acked\n * _FAIL: not acked when using xmit ack\n */\nstatic int issue_action_ba(_adapter *padapter, unsigned char *raddr, unsigned char action\n\t\t   , u8 tid, u8 size, u16 status, u8 initiator, int wait_ack)\n{\n\tint ret = _FAIL;\n\tu8\tcategory = RTW_WLAN_CATEGORY_BACK;\n\tu16\tstart_seq;\n\tu16\tBA_para_set;\n\tu16\tBA_timeout_value;\n\tu16\tBA_starting_seqctrl;\n\tstruct xmit_frame\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t*pattrib;\n\tu8\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tu16\t\t\t\t\t*fctrl;\n\tstruct xmit_priv\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct sta_info\t\t*psta;\n\tstruct sta_priv\t\t*pstapriv = &padapter->stapriv;\n\tstruct registry_priv\t\t*pregpriv = &padapter->registrypriv;\n\n#ifdef CONFIG_80211N_HT\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\tgoto exit;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t/* _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); */\n\t_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));\n\n\tif (category == 3) {\n\t\tswitch (action) {\n\t\tcase RTW_WLAN_ACTION_ADDBA_REQ:\n\t\t\tdo {\n\t\t\t\tpmlmeinfo->dialogToken++;\n\t\t\t} while (pmlmeinfo->dialogToken == 0);\n\t\t\tpframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->dialogToken), &(pattrib->pktlen));\n\n#if defined(CONFIG_RTL8188E) && defined(CONFIG_SDIO_HCI)\n\t\t\tBA_para_set = (0x0802 | ((tid & 0xf) << 2)); /* immediate ack & 16 buffer size */\n#else\n\t\t\tBA_para_set = (0x1002 | ((tid & 0xf) << 2)); /* immediate ack & 64 buffer size */\n#endif\n\n#ifdef CONFIG_TX_AMSDU\n\t\t\tif (padapter->tx_amsdu >= 1) /* TX AMSDU  enabled */\n\t\t\t\tBA_para_set |= BIT(0);\n\t\t\telse /* TX AMSDU disabled */\n\t\t\t\tBA_para_set &= ~BIT(0);\n#endif\n\t\t\tBA_para_set = cpu_to_le16(BA_para_set);\n\t\t\tpframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen));\n\n\t\t\t/* BA_timeout_value = 0xffff; */ /* max: 65535 TUs(~ 65 ms) */\n\t\t\tBA_timeout_value = 5000;/* ~ 5ms */\n\t\t\tBA_timeout_value = cpu_to_le16(BA_timeout_value);\n\t\t\tpframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_timeout_value)), &(pattrib->pktlen));\n\n\t\t\t/* if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL) */\n\t\t\tpsta = rtw_get_stainfo(pstapriv, raddr);\n\t\t\tif (psta != NULL) {\n\t\t\t\tstart_seq = (psta->sta_xmitpriv.txseq_tid[tid & 0x07] & 0xfff) + 1;\n\n\t\t\t\tRTW_INFO(\"BA_starting_seqctrl = %d for TID=%d\\n\", start_seq, tid & 0x07);\n\n\t\t\t\tpsta->BA_starting_seqctrl[tid & 0x07] = start_seq;\n\n\t\t\t\tBA_starting_seqctrl = start_seq << 4;\n\t\t\t}\n\n\t\t\tBA_starting_seqctrl = cpu_to_le16(BA_starting_seqctrl);\n\t\t\tpframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_starting_seqctrl)), &(pattrib->pktlen));\n\t\t\tbreak;\n\n\t\tcase RTW_WLAN_ACTION_ADDBA_RESP:\n\t\t\tpframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->ADDBA_req.dialog_token), &(pattrib->pktlen));\n\t\t\tstatus = cpu_to_le16(status);\n\t\t\tpframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&status), &(pattrib->pktlen));\n\n\t\t\tBA_para_set = le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set);\n\n\t\t\tBA_para_set &= ~IEEE80211_ADDBA_PARAM_TID_MASK;\n\t\t\tBA_para_set |= (tid << 2) & IEEE80211_ADDBA_PARAM_TID_MASK;\n\n\t\t\tBA_para_set &= ~RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK;\n\t\t\tBA_para_set |= (size << 6) & RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK;\n\n\t\t\tif (!padapter->registrypriv.wifi_spec) {\n\t\t\t\tif (pregpriv->rx_ampdu_amsdu == 0) /* disabled */\n\t\t\t\t\tBA_para_set &= ~BIT(0);\n\t\t\t\telse if (pregpriv->rx_ampdu_amsdu == 1) /* enabled */\n\t\t\t\t\tBA_para_set |= BIT(0);\n\t\t\t}\n\n\t\t\tBA_para_set = cpu_to_le16(BA_para_set);\n\n\t\t\tpframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen));\n\t\t\tpframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(pmlmeinfo->ADDBA_req.BA_timeout_value)), &(pattrib->pktlen));\n\t\t\tbreak;\n\n\t\tcase RTW_WLAN_ACTION_DELBA:\n\t\t\tBA_para_set = 0;\n\t\t\tBA_para_set |= (tid << 12) & IEEE80211_DELBA_PARAM_TID_MASK;\n\t\t\tBA_para_set |= (initiator << 11) & IEEE80211_DELBA_PARAM_INITIATOR_MASK;\n\n\t\t\tBA_para_set = cpu_to_le16(BA_para_set);\n\t\t\tpframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen));\n\t\t\tstatus = cpu_to_le16(status);\n\t\t\tpframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(status)), &(pattrib->pktlen));\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tif (wait_ack)\n\t\tret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);\n\telse {\n\t\tdump_mgntframe(padapter, pmgntframe);\n\t\tret = _SUCCESS;\n\t}\n\nexit:\n#endif /* CONFIG_80211N_HT */\n\treturn ret;\n}\n\n/**\n * issue_addba_req - TX ADDBA_REQ\n * @adapter: the adapter to TX\n * @ra: receiver address\n * @tid: tid\n */\ninline void issue_addba_req(_adapter *adapter, unsigned char *ra, u8 tid)\n{\n\tissue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_REQ\n\t\t\t, tid\n\t\t\t, 0 /* unused */\n\t\t\t, 0 /* unused */\n\t\t\t, 0 /* unused */\n\t\t\t, _FALSE\n\t\t       );\n\tRTW_INFO(FUNC_ADPT_FMT\" ra=\"MAC_FMT\" tid=%u\\n\"\n\t\t , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), tid);\n\n}\n\n/**\n * issue_addba_rsp - TX ADDBA_RESP\n * @adapter: the adapter to TX\n * @ra: receiver address\n * @tid: tid\n * @status: status code\n * @size: the announced AMPDU buffer size\n */\ninline void issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size)\n{\n\tissue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_RESP\n\t\t\t, tid\n\t\t\t, size\n\t\t\t, status\n\t\t\t, 0 /* unused */\n\t\t\t, _FALSE\n\t\t       );\n\tRTW_INFO(FUNC_ADPT_FMT\" ra=\"MAC_FMT\" status=%u, tid=%u, size=%u\\n\"\n\t\t , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), status, tid, size);\n}\n\n/**\n * issue_addba_rsp_wait_ack - TX ADDBA_RESP and wait ack\n * @adapter: the adapter to TX\n * @ra: receiver address\n * @tid: tid\n * @status: status code\n * @size: the announced AMPDU buffer size\n * @try_cnt: the maximal TX count to try\n * @wait_ms: == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT\n *           > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX\n */\ninline u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size, int try_cnt, int wait_ms)\n{\n\tint ret = _FAIL;\n\tint i = 0;\n\tsystime start = rtw_get_current_time();\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter)))\n\t\tgoto exit;\n\n\tdo {\n\t\tret = issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_RESP\n\t\t\t\t      , tid\n\t\t\t\t      , size\n\t\t\t\t      , status\n\t\t\t\t      , 0 /* unused */\n\t\t\t\t      , _TRUE\n\t\t\t\t     );\n\n\t\ti++;\n\n\t\tif (RTW_CANNOT_RUN(adapter))\n\t\t\tbreak;\n\n\t\tif (i < try_cnt && wait_ms > 0 && ret == _FAIL)\n\t\t\trtw_msleep_os(wait_ms);\n\n\t} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));\n\n\tif (ret != _FAIL) {\n\t\tret = _SUCCESS;\n#ifndef DBG_XMIT_ACK\n\t\t/* goto exit; */\n#endif\n\t}\n\n\tif (try_cnt && wait_ms) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" ra=\"MAC_FMT\" status:=%u tid=%u size:%u%s, %d/%d in %u ms\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(ra), status, tid, size\n\t\t\t, ret == _SUCCESS ? \", acked\" : \"\", i, try_cnt, rtw_get_passing_time_ms(start));\n\t}\n\nexit:\n\treturn ret;\n}\n\n/**\n * issue_del_ba - TX DELBA\n * @adapter: the adapter to TX\n * @ra: receiver address\n * @tid: tid\n * @reason: reason code\n * @initiator: if we are the initiator of AMPDU association. used by DELBA\n */\ninline void issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator)\n{\n\tissue_action_ba(adapter, ra, RTW_WLAN_ACTION_DELBA\n\t\t\t, tid\n\t\t\t, 0 /* unused */\n\t\t\t, reason\n\t\t\t, initiator\n\t\t\t, _FALSE\n\t\t       );\n\tRTW_INFO(FUNC_ADPT_FMT\" ra=\"MAC_FMT\" reason=%u, tid=%u, initiator=%u\\n\"\n\t\t , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), reason, tid, initiator);\n}\n\n/**\n * issue_del_ba_ex - TX DELBA with xmit ack options\n * @adapter: the adapter to TX\n * @ra: receiver address\n * @tid: tid\n * @reason: reason code\n * @initiator: if we are the initiator of AMPDU association. used by DELBA\n * @try_cnt: the maximal TX count to try\n * @wait_ms: == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT\n *           > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX\n */\nint issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator\n\t\t    , int try_cnt, int wait_ms)\n{\n\tint ret = _FAIL;\n\tint i = 0;\n\tsystime start = rtw_get_current_time();\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter)))\n\t\tgoto exit;\n\n\tdo {\n\t\tret = issue_action_ba(adapter, ra, RTW_WLAN_ACTION_DELBA\n\t\t\t\t      , tid\n\t\t\t\t      , 0 /* unused */\n\t\t\t\t      , reason\n\t\t\t\t      , initiator\n\t\t\t\t      , wait_ms > 0 ? _TRUE : _FALSE\n\t\t\t\t     );\n\n\t\ti++;\n\n\t\tif (RTW_CANNOT_RUN(adapter))\n\t\t\tbreak;\n\n\t\tif (i < try_cnt && wait_ms > 0 && ret == _FAIL)\n\t\t\trtw_msleep_os(wait_ms);\n\n\t} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));\n\n\tif (ret != _FAIL) {\n\t\tret = _SUCCESS;\n#ifndef DBG_XMIT_ACK\n\t\t/* goto exit; */\n#endif\n\t}\n\n\tif (try_cnt && wait_ms) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" ra=\"MAC_FMT\" reason=%u, tid=%u, initiator=%u%s, %d/%d in %u ms\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(ra), reason, tid, initiator\n\t\t\t, ret == _SUCCESS ? \", acked\" : \"\", i, try_cnt, rtw_get_passing_time_ms(start));\n\t}\nexit:\n\treturn ret;\n}\n\nvoid issue_action_BSSCoexistPacket(_adapter *padapter)\n{\n\t_irqL\tirqL;\n\t_list\t\t*plist, *phead;\n\tunsigned char category, action;\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t*fctrl;\n\tstruct\twlan_network\t*pnetwork = NULL;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\t_queue\t\t*queue\t= &(pmlmepriv->scanned_queue);\n\tu8 InfoContent[16] = {0};\n\tu8 ICS[8][15];\n#ifdef CONFIG_80211N_HT\n\tif ((pmlmepriv->num_FortyMHzIntolerant == 0) && (pmlmepriv->num_sta_no_ht == 0))\n\t\treturn;\n\n\tif (_TRUE == pmlmeinfo->bwmode_updated)\n\t\treturn;\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\treturn;\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\n\tcategory = RTW_WLAN_CATEGORY_PUBLIC;\n\taction = ACT_PUBLIC_BSSCOEXIST;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));\n\n\t/* TODO calculate 40Mhz intolerant via ch and ch offset */\n\t/* if (pmlmepriv->num_FortyMHzIntolerant > 0) */\n\t{\n\t\tu8 iedata = 0;\n\n\t\tiedata |= BIT(2);/* 20 MHz BSS Width Request */\n\t\tpframe = rtw_set_ie(pframe, EID_BSSCoexistence,  1, &iedata, &(pattrib->pktlen));\n\t}\n\n\t/*  */\n\t_rtw_memset(ICS, 0, sizeof(ICS));\n\tif (pmlmepriv->num_sta_no_ht > 0) {\n\t\tint i;\n\n\t\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\t\tphead = get_list_head(queue);\n\t\tplist = get_next(phead);\n\n\t\twhile (1) {\n\t\t\tint len;\n\t\t\tu8 *p;\n\t\t\tWLAN_BSSID_EX *pbss_network;\n\n\t\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\t\tbreak;\n\n\t\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\n\t\t\tplist = get_next(plist);\n\n\t\t\tpbss_network = (WLAN_BSSID_EX *)&pnetwork->network;\n\n\t\t\tp = rtw_get_ie(pbss_network->IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, pbss_network->IELength - _FIXED_IE_LENGTH_);\n\t\t\tif ((p == NULL) || (len == 0)) { /* non-HT */\n\t\t\t\tif ((pbss_network->Configuration.DSConfig <= 0) || (pbss_network->Configuration.DSConfig > 14))\n\t\t\t\t\tcontinue;\n\n\t\t\t\tICS[0][pbss_network->Configuration.DSConfig] = 1;\n\n\t\t\t\tif (ICS[0][0] == 0)\n\t\t\t\t\tICS[0][0] = 1;\n\t\t\t}\n\n\t\t}\n\n\t\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\n\t\tfor (i = 0; i < 8; i++) {\n\t\t\tif (ICS[i][0] == 1) {\n\t\t\t\tint j, k = 0;\n\n\t\t\t\tInfoContent[k] = i;\n\t\t\t\t/* SET_BSS_INTOLERANT_ELE_REG_CLASS(InfoContent,i); */\n\t\t\t\tk++;\n\n\t\t\t\tfor (j = 1; j <= 14; j++) {\n\t\t\t\t\tif (ICS[i][j] == 1) {\n\t\t\t\t\t\tif (k < 16) {\n\t\t\t\t\t\t\tInfoContent[k] = j; /* channel number */\n\t\t\t\t\t\t\t/* SET_BSS_INTOLERANT_ELE_CHANNEL(InfoContent+k, j); */\n\t\t\t\t\t\t\tk++;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tpframe = rtw_set_ie(pframe, EID_BSSIntolerantChlReport, k, InfoContent, &(pattrib->pktlen));\n\n\t\t\t}\n\n\t\t}\n\n\n\t}\n\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(padapter, pmgntframe);\n#endif /* CONFIG_80211N_HT */\n}\n\n/* Spatial Multiplexing Powersave (SMPS) action frame */\nint _issue_action_SM_PS(_adapter *padapter ,  unsigned char *raddr , u8 NewMimoPsMode ,  u8 wait_ack)\n{\n\n\tint ret = _FAIL;\n\tunsigned char category = RTW_WLAN_CATEGORY_HT;\n\tu8 action = RTW_WLAN_ACTION_HT_SM_PS;\n\tu8 sm_power_control = 0;\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\n\tif (NewMimoPsMode == WLAN_HT_CAP_SM_PS_DISABLED) {\n\t\tsm_power_control = sm_power_control  & ~(BIT(0)); /* SM Power Save Enable = 0 SM Power Save Disable */\n\t} else if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_STATIC) {\n\t\tsm_power_control = sm_power_control | BIT(0);    /* SM Power Save Enable = 1 SM Power Save Enable  */\n\t\tsm_power_control = sm_power_control & ~(BIT(1)); /* SM Mode = 0 Static Mode */\n\t} else if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_DYNAMIC) {\n\t\tsm_power_control = sm_power_control | BIT(0); /* SM Power Save Enable = 1 SM Power Save Enable  */\n\t\tsm_power_control = sm_power_control | BIT(1); /* SM Mode = 1 Dynamic Mode */\n\t} else\n\t\treturn ret;\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\treturn ret;\n\n\tRTW_INFO(\"%s, sm_power_control=%u, NewMimoPsMode=%u\\n\", __FUNCTION__ , sm_power_control , NewMimoPsMode);\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn ret;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); /* RA */\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); /* TA */\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); /* DA = RA */\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\t/* category, action */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(sm_power_control), &(pattrib->pktlen));\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tif (wait_ack)\n\t\tret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);\n\telse {\n\t\tdump_mgntframe(padapter, pmgntframe);\n\t\tret = _SUCCESS;\n\t}\n\n\tif (ret != _SUCCESS)\n\t\tRTW_INFO(\"%s, ack to\\n\", __func__);\n\n\treturn ret;\n}\n\n/*\n * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT\n * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX\n * try_cnt means the maximal TX count to try\n */\nint issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 NewMimoPsMode, int try_cnt, int wait_ms)\n{\n\tint ret = _FAIL;\n\tint i = 0;\n\tsystime start = rtw_get_current_time();\n\n\tif (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))\n\t\tgoto exit;\n\n\tdo {\n\t\tret = _issue_action_SM_PS(padapter, raddr, NewMimoPsMode , wait_ms > 0 ? _TRUE : _FALSE);\n\n\t\ti++;\n\n\t\tif (RTW_CANNOT_RUN(padapter))\n\t\t\tbreak;\n\n\t\tif (i < try_cnt && wait_ms > 0 && ret == _FAIL)\n\t\t\trtw_msleep_os(wait_ms);\n\n\t} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));\n\n\tif (ret != _FAIL) {\n\t\tret = _SUCCESS;\n#ifndef DBG_XMIT_ACK\n\t\tgoto exit;\n#endif\n\t}\n\n\tif (try_cnt && wait_ms) {\n\t\tif (raddr)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" to \"MAC_FMT\", %s , %d/%d in %u ms\\n\",\n\t\t\t\t FUNC_ADPT_ARG(padapter), MAC_ARG(raddr),\n\t\t\t\tret == _SUCCESS ? \", acked\" : \"\", i, try_cnt, rtw_get_passing_time_ms(start));\n\t\telse\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\", %s , %d/%d in %u ms\\n\",\n\t\t\t\t FUNC_ADPT_ARG(padapter),\n\t\t\t\tret == _SUCCESS ? \", acked\" : \"\", i, try_cnt, rtw_get_passing_time_ms(start));\n\t}\nexit:\n\n\treturn ret;\n}\n\nint issue_action_SM_PS(_adapter *padapter ,  unsigned char *raddr , u8 NewMimoPsMode)\n{\n\tRTW_INFO(\"%s to \"MAC_FMT\"\\n\", __func__, MAC_ARG(raddr));\n\treturn _issue_action_SM_PS(padapter, raddr, NewMimoPsMode , _FALSE);\n}\n\n/**\n * _send_delba_sta_tid - Cancel the AMPDU association for the specific @sta, @tid\n * @adapter: the adapter to which @sta belongs\n * @initiator: if we are the initiator of AMPDU association\n * @sta: the sta to be checked\n * @tid: the tid to be checked\n * @force: cancel and send DELBA even when no AMPDU association is setup\n * @wait_ack: send delba with xmit ack (valid when initiator == 0)\n *\n * Returns:\n * _FAIL if sta is NULL\n * when initiator is 1, always _SUCCESS\n * when initiator is 0, _SUCCESS if DELBA is acked\n */\nstatic unsigned int _send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid\n\t\t\t\t\t, u8 force, int wait_ack)\n{\n\tint ret = _SUCCESS;\n\n\tif (sta == NULL) {\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tif (initiator == 0) {\n\t\t/* recipient */\n\t\tif (force || sta->recvreorder_ctrl[tid].enable == _TRUE) {\n\t\t\tu8 ampdu_size_bak = sta->recvreorder_ctrl[tid].ampdu_size;\n\n\t\t\tsta->recvreorder_ctrl[tid].enable = _FALSE;\n\t\t\tsta->recvreorder_ctrl[tid].ampdu_size = RX_AMPDU_SIZE_INVALID;\n\n\t\t\tif (rtw_del_rx_ampdu_test_trigger_no_tx_fail())\n\t\t\t\tret = _FAIL;\n\t\t\telse if (wait_ack)\n\t\t\t\tret = issue_del_ba_ex(adapter, sta->cmn.mac_addr, tid, 37, initiator, 3, 1);\n\t\t\telse\n\t\t\t\tissue_del_ba(adapter, sta->cmn.mac_addr, tid, 37, initiator);\n\n\t\t\tif (ret == _FAIL && sta->recvreorder_ctrl[tid].enable == _FALSE)\n\t\t\t\tsta->recvreorder_ctrl[tid].ampdu_size = ampdu_size_bak;\n\t\t}\n\t} else if (initiator == 1) {\n\t\t/* originator */\n#ifdef CONFIG_80211N_HT\n\t\tif (force || sta->htpriv.agg_enable_bitmap & BIT(tid)) {\n\t\t\tsta->htpriv.agg_enable_bitmap &= ~BIT(tid);\n\t\t\tsta->htpriv.candidate_tid_bitmap &= ~BIT(tid);\n\t\t\tissue_del_ba(adapter, sta->cmn.mac_addr, tid, 37, initiator);\n\t\t}\n#endif\n\t}\n\nexit:\n\treturn ret;\n}\n\ninline unsigned int send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid\n\t\t\t\t       , u8 force)\n{\n\treturn _send_delba_sta_tid(adapter, initiator, sta, tid, force, 0);\n}\n\ninline unsigned int send_delba_sta_tid_wait_ack(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid\n\t\t, u8 force)\n{\n\treturn _send_delba_sta_tid(adapter, initiator, sta, tid, force, 1);\n}\n\nunsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr)\n{\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct sta_info *psta = NULL;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu16 tid;\n\n\tif ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)\n\t\tif (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS))\n\t\t\treturn _SUCCESS;\n\n\tpsta = rtw_get_stainfo(pstapriv, addr);\n\tif (psta == NULL)\n\t\treturn _SUCCESS;\n\n#if 0\n\tRTW_INFO(\"%s:%s\\n\", __func__, (initiator == 0) ? \"RX_DIR\" : \"TX_DIR\");\n\tif (initiator == 1) /* originator */\n\t\tRTW_INFO(\"tx agg_enable_bitmap(0x%08x)\\n\", psta->htpriv.agg_enable_bitmap);\n#endif\n\n\tfor (tid = 0; tid < TID_NUM; tid++)\n\t\tsend_delba_sta_tid(padapter, initiator, psta, tid, 0);\n\n\treturn _SUCCESS;\n}\n\nunsigned int send_beacon(_adapter *padapter)\n{\n#if defined(CONFIG_PCI_HCI) && !defined(CONFIG_PCI_BCN_POLLING)\n\t#ifdef CONFIG_FW_HANDLE_TXBCN\n\tu8 vap_id = padapter->vap_id;\n\n\t/* bypass TX BCN because vap_id is invalid*/\n\tif (vap_id == CONFIG_LIMITED_AP_NUM)\n\t\treturn _SUCCESS;\n\t#endif\n\n\t/* bypass TX BCN queue because op ch is switching/waiting */\n\tif (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING)\n\t\t|| IS_CH_WAITING(adapter_to_rfctl(padapter))\n\t)\n\t\treturn _SUCCESS;\n\n\t/* RTW_INFO(\"%s\\n\", __FUNCTION__); */\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);\n\n\t/* 8192EE Port select for Beacon DL */\n\trtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);\n\t#ifdef CONFIG_FW_HANDLE_TXBCN\n\trtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id);\n\t#endif\n\n\tissue_beacon(padapter, 0);\n\n\t#ifdef CONFIG_FW_HANDLE_TXBCN\n\tvap_id = 0xFF;\n\trtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id);\n\t#endif\n\n\t#ifdef RTL8814AE_SW_BCN\n\tif (GET_HAL_DATA(padapter)->bCorrectBCN != 0)\n\t\tRTW_INFO(\"%s, line%d, Warnning, pHalData->bCorrectBCN != 0\\n\", __func__, __LINE__);\n\tGET_HAL_DATA(padapter)->bCorrectBCN = 1;\n\t#endif\n\n\treturn _SUCCESS;\n#endif\n\n/* CONFIG_PCI_BCN_POLLING is for pci interface beacon polling mode */\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)|| defined(CONFIG_PCI_BCN_POLLING) \n\tu8 bxmitok = _FALSE;\n\tint issue = 0;\n\tint poll = 0;\n\tsystime start = rtw_get_current_time();\n\t#ifdef CONFIG_FW_HANDLE_TXBCN\n\tu8 vap_id = padapter->vap_id;\n\n\t/* bypass TX BCN because vap_id is invalid*/\n\tif (vap_id == CONFIG_LIMITED_AP_NUM)\n\t\treturn _SUCCESS;\n\t#endif\n\n\t/* bypass TX BCN queue because op ch is switching/waiting */\n\tif (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING)\n\t\t|| IS_CH_WAITING(adapter_to_rfctl(padapter))\n\t)\n\t\treturn _SUCCESS;\n\n\t#if defined(CONFIG_USB_HCI)\n\t#if defined(CONFIG_RTL8812A)\n\tif (IS_FULL_SPEED_USB(padapter)) {\n\t\tissue_beacon(padapter, 300);\n\t\tbxmitok = _TRUE;\n\t} else\n\t#endif\n\t#endif\n\t{\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);\n\t\t#ifdef CONFIG_FW_HANDLE_TXBCN\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id);\n\t\t#endif\n\t\tdo {\n\t\t\t#if defined(CONFIG_PCI_BCN_POLLING) \n\t\t\tissue_beacon(padapter, 0);\n\t\t\t#else\n\t\t\tissue_beacon(padapter, 100);\n\t\t\t#endif\n\t\t\tissue++;\n\t\t\tdo {\n\t\t\t\t#if defined(CONFIG_PCI_BCN_POLLING) \n\t\t\t\trtw_msleep_os(1);\n\t\t\t\t#else\n\t\t\t\trtw_yield_os();\n\t\t\t\t#endif\n\t\t\t\trtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8 *)(&bxmitok));\n\t\t\t\tpoll++;\n\t\t\t} while ((poll % 10) != 0 && _FALSE == bxmitok && !RTW_CANNOT_RUN(padapter));\n\t\t\t#if defined(CONFIG_PCI_BCN_POLLING) \n\t\t\trtw_hal_unmap_beacon_icf(padapter);\n\t\t\t#endif\n\t\t} while (bxmitok == _FALSE && (issue < 100) && !RTW_CANNOT_RUN(padapter));\n\t\t#ifdef CONFIG_FW_HANDLE_TXBCN\n\t\tvap_id = 0xFF;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id);\n\t\t#endif\n\t}\n\tif (RTW_CANNOT_RUN(padapter))\n\t\treturn _FAIL;\n\n\n\tif (_FALSE == bxmitok) {\n\t\tRTW_INFO(\"%s fail! %u ms\\n\", __FUNCTION__, rtw_get_passing_time_ms(start));\n\t\t#ifdef CONFIG_BCN_RECOVERY\n\t\tGET_HAL_DATA(padapter)->issue_bcn_fail++;\n\t\t#endif  /*CONFIG_BCN_RECOVERY*/\n\t\treturn _FAIL;\n\t} else {\n\t\tu32 passing_time = rtw_get_passing_time_ms(start);\n\n\t\tif (passing_time > 100 || issue > 3)\n\t\t\tRTW_INFO(\"%s success, issue:%d, poll:%d, %u ms\\n\", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start));\n\t\telse if (0)\n\t\t\tRTW_INFO(\"%s success, issue:%d, poll:%d, %u ms\\n\", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start));\n\n\t\t#ifdef CONFIG_FW_CORRECT_BCN\n\t\trtw_hal_fw_correct_bcn(padapter);\n\t\t#endif\n\t\treturn _SUCCESS;\n\t}\n\n#endif /*defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)*/\n\n}\n\n/****************************************************************************\n\nFollowing are some utitity fuctions for WiFi MLME\n\n*****************************************************************************/\n\nBOOLEAN IsLegal5GChannel(\n\tPADAPTER\t\t\tAdapter,\n\tu8\t\t\tchannel)\n{\n\n\tint i = 0;\n\tu8 Channel_5G[45] = {36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,\n\t\t60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122,\n\t\t124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159,\n\t\t\t     161, 163, 165\n\t\t\t    };\n\tfor (i = 0; i < sizeof(Channel_5G); i++)\n\t\tif (channel == Channel_5G[i])\n\t\t\treturn _TRUE;\n\treturn _FALSE;\n}\n\n/* collect bss info from Beacon and Probe request/response frames. */\nu8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid)\n{\n\tint\ti;\n\tsint len;\n\tu8\t*p;\n\tu8\trf_path;\n\tu16\tval16, subtype;\n\tu8\t*pframe = precv_frame->u.hdr.rx_data;\n\tu32\tpacket_len = precv_frame->u.hdr.len;\n\tu8 ie_offset;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct registry_priv\t*pregistrypriv = &padapter->registrypriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\n\tlen = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tif (len > MAX_IE_SZ) {\n\t\t/* RTW_INFO(\"IE too long for survey event\\n\"); */\n\t\treturn _FAIL;\n\t}\n\n\t_rtw_memset(bssid, 0, sizeof(WLAN_BSSID_EX));\n\n\tsubtype = get_frame_sub_type(pframe);\n\n\tif (subtype == WIFI_BEACON) {\n\t\tbssid->Reserved[0] = BSS_TYPE_BCN;\n\t\tie_offset = _BEACON_IE_OFFSET_;\n\t} else {\n\t\t/* FIXME : more type */\n\t\tif (subtype == WIFI_PROBERSP) {\n\t\t\tie_offset = _PROBERSP_IE_OFFSET_;\n\t\t\tbssid->Reserved[0] = BSS_TYPE_PROB_RSP;\n\t\t} else if (subtype == WIFI_PROBEREQ) {\n\t\t\tie_offset = _PROBEREQ_IE_OFFSET_;\n\t\t\tbssid->Reserved[0] = BSS_TYPE_PROB_REQ;\n\t\t} else {\n\t\t\tbssid->Reserved[0] = BSS_TYPE_UNDEF;\n\t\t\tie_offset = _FIXED_IE_LENGTH_;\n\t\t}\n\t}\n\n\tbssid->Length = sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + len;\n\n\t/* below is to copy the information element */\n\tbssid->IELength = len;\n\t_rtw_memcpy(bssid->IEs, (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)), bssid->IELength);\n\n\t/* get the signal strength */\n\t/* bssid->Rssi = precv_frame->u.hdr.attrib.SignalStrength; */ /* 0-100 index. */\n\tbssid->Rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power; /* in dBM.raw data */\n\tbssid->PhyInfo.SignalQuality = precv_frame->u.hdr.attrib.phy_info.signal_quality;/* in percentage */\n\tbssid->PhyInfo.SignalStrength = precv_frame->u.hdr.attrib.phy_info.signal_strength;/* in percentage */\n\n\t/* get rx_snr */\n\tif (precv_frame->u.hdr.attrib.data_rate >= DESC_RATE11M) {\n\t\tbssid->PhyInfo.is_cck_rate = 0;\n\t\tfor (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++)\n\t\t\tbssid->PhyInfo.rx_snr[rf_path] =\n\t\t\t\tprecv_frame->u.hdr.attrib.phy_info.rx_snr[rf_path];\n\t} else\n\t\tbssid->PhyInfo.is_cck_rate = 1;\n\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\trtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &(bssid->PhyInfo.Optimum_antenna), NULL);\n#endif\n\n\t/* checking SSID */\n\tp = rtw_get_ie(bssid->IEs + ie_offset, _SSID_IE_, &len, bssid->IELength - ie_offset);\n\tif (p == NULL) {\n\t\tRTW_INFO(\"marc: cannot find SSID for survey event\\n\");\n\t\treturn _FAIL;\n\t}\n\n\tif (*(p + 1)) {\n\t\tif (len > NDIS_802_11_LENGTH_SSID) {\n\t\t\tRTW_INFO(\"%s()-%d: IE too long (%d) for survey event\\n\", __FUNCTION__, __LINE__, len);\n\t\t\treturn _FAIL;\n\t\t}\n\t\t_rtw_memcpy(bssid->Ssid.Ssid, (p + 2), *(p + 1));\n\t\tbssid->Ssid.SsidLength = *(p + 1);\n\t} else\n\t\tbssid->Ssid.SsidLength = 0;\n\n\t_rtw_memset(bssid->SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX);\n\n\t/* checking rate info... */\n\ti = 0;\n\tp = rtw_get_ie(bssid->IEs + ie_offset, _SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset);\n\tif (p != NULL) {\n\t\tif (len > NDIS_802_11_LENGTH_RATES_EX) {\n\t\t\tRTW_INFO(\"%s()-%d: IE too long (%d) for survey event\\n\", __FUNCTION__, __LINE__, len);\n\t\t\treturn _FAIL;\n\t\t}\n\t\tif (rtw_validate_value(_SUPPORTEDRATES_IE_, p+2, len) == _FALSE) {\n\t\t\trtw_absorb_ssid_ifneed(padapter, bssid, pframe);\n\t\t\tRTW_DBG_DUMP(\"Invalidated Support Rate IE --\", p, len+2);\n\t\t\treturn _FAIL;\n\t\t}\n\t\t_rtw_memcpy(bssid->SupportedRates, (p + 2), len);\n\t\ti = len;\n\t}\n\n\tp = rtw_get_ie(bssid->IEs + ie_offset, _EXT_SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset);\n\tif (p != NULL) {\n\t\tif (len > (NDIS_802_11_LENGTH_RATES_EX - i)) {\n\t\t\tRTW_INFO(\"%s()-%d: IE too long (%d) for survey event\\n\", __FUNCTION__, __LINE__, len);\n\t\t\treturn _FAIL;\n\t\t}\n\t\tif (rtw_validate_value(_EXT_SUPPORTEDRATES_IE_, p+2, len) == _FALSE) {\n\t\t\trtw_absorb_ssid_ifneed(padapter, bssid, pframe);\n\t\t\tRTW_DBG_DUMP(\"Invalidated EXT Support Rate IE --\", p, len+2);\n\t\t\treturn _FAIL;\n\t\t}\n\t\t_rtw_memcpy(bssid->SupportedRates + i, (p + 2), len);\n\t}\n\n#ifdef CONFIG_P2P\n\tif (subtype == WIFI_PROBEREQ) {\n\t\tu8 *p2p_ie;\n\t\tu32\tp2p_ielen;\n\t\t/* Set Listion Channel */\n\t\tp2p_ie = rtw_get_p2p_ie(bssid->IEs, bssid->IELength, NULL, &p2p_ielen);\n\t\tif (p2p_ie) {\n\t\t\tu32\tattr_contentlen = 0;\n\t\t\tu8 listen_ch[5] = { 0x00 };\n\n\t\t\trtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, listen_ch, &attr_contentlen);\n\t\t\tbssid->Configuration.DSConfig = listen_ch[4];\n\t\t} else {\n\t\t\t/* use current channel */\n\t\t\tbssid->Configuration.DSConfig = padapter->mlmeextpriv.cur_channel;\n\t\t\tRTW_INFO(\"%s()-%d: Cannot get p2p_ie. set DSconfig to op_ch(%d)\\n\", __FUNCTION__, __LINE__, bssid->Configuration.DSConfig);\n\t\t}\n\n\t\t/* FIXME */\n\t\tbssid->InfrastructureMode = Ndis802_11Infrastructure;\n\t\t_rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN);\n\t\tbssid->Privacy = 1;\n\t\treturn _SUCCESS;\n\t}\n#endif /* CONFIG_P2P */\n\n\tif (bssid->IELength < 12)\n\t\treturn _FAIL;\n\n\t/* Checking for DSConfig */\n\tp = rtw_get_ie(bssid->IEs + ie_offset, _DSSET_IE_, &len, bssid->IELength - ie_offset);\n\n\tbssid->Configuration.DSConfig = 0;\n\tbssid->Configuration.Length = 0;\n\n\tif (p)\n\t\tbssid->Configuration.DSConfig = *(p + 2);\n\telse {\n\t\t/* In 5G, some ap do not have DSSET IE */\n\t\t/* checking HT info for channel */\n\t\tp = rtw_get_ie(bssid->IEs + ie_offset, _HT_ADD_INFO_IE_, &len, bssid->IELength - ie_offset);\n\t\tif (p) {\n\t\t\tstruct HT_info_element *HT_info = (struct HT_info_element *)(p + 2);\n\t\t\tbssid->Configuration.DSConfig = HT_info->primary_channel;\n\t\t} else {\n\t\t\t/* use current channel */\n\t\t\tbssid->Configuration.DSConfig = rtw_get_oper_ch(padapter);\n\t\t}\n\t}\n\n\t_rtw_memcpy(&bssid->Configuration.BeaconPeriod, rtw_get_beacon_interval_from_ie(bssid->IEs), 2);\n\tbssid->Configuration.BeaconPeriod = le32_to_cpu(bssid->Configuration.BeaconPeriod);\n\n\tval16 = rtw_get_capability((WLAN_BSSID_EX *)bssid);\n\n\tif ((val16 & 0x03) == cap_ESS) {\n\t\tbssid->InfrastructureMode = Ndis802_11Infrastructure;\n\t\t_rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN);\n\t} else if ((val16 & 0x03) == cap_IBSS){\n\t\tbssid->InfrastructureMode = Ndis802_11IBSS;\n\t\t_rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN);\n\t} else if ((val16 & 0x03) == 0x00){\n\t\tu8 *mesh_id_ie, *mesh_conf_ie;\n\t\tsint mesh_id_ie_len, mesh_conf_ie_len;\n\n\t\tmesh_id_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_ID, &mesh_id_ie_len, bssid->IELength - ie_offset);\n\t\tmesh_conf_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_CONFIG, &mesh_conf_ie_len, bssid->IELength - ie_offset);\n\t\tif (mesh_id_ie || mesh_conf_ie) {\n\t\t\tif (!mesh_id_ie) {\n\t\t\t\tRTW_INFO(\"cannot find Mesh ID for survey event\\n\");\n\t\t\t\treturn _FAIL;\n\t\t\t}\n\t\t\tif (mesh_id_ie_len) {\n\t\t\t\tif (mesh_id_ie_len > NDIS_802_11_LENGTH_SSID) {\n\t\t\t\t\tRTW_INFO(\"Mesh ID too long (%d) for survey event\\n\", mesh_id_ie_len);\n\t\t\t\t\treturn _FAIL;\n\t\t\t\t}\n\t\t\t\t_rtw_memcpy(bssid->mesh_id.Ssid, (mesh_id_ie + 2), mesh_id_ie_len);\n\t\t\t\tbssid->mesh_id.SsidLength = mesh_id_ie_len;\n\t\t\t} else\n\t\t\t\tbssid->mesh_id.SsidLength = 0;\n\n\t\t\tif (!mesh_conf_ie) {\n\t\t\t\tRTW_INFO(\"cannot find Mesh config for survey event\\n\");\n\t\t\t\treturn _FAIL;\n\t\t\t}\n\t\t\tif (mesh_conf_ie_len != 7) {\n\t\t\t\tRTW_INFO(\"invalid Mesh conf IE len (%d) for survey event\\n\", mesh_conf_ie_len);\n\t\t\t\treturn _FAIL;\n\t\t\t}\n\n\t\t\tbssid->InfrastructureMode = Ndis802_11_mesh;\n\t\t\t_rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN);\n\t\t} else {\n\t\t\t/* default cases */\n\t\t\tbssid->InfrastructureMode = Ndis802_11IBSS;\n\t\t\t_rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN);\n\t\t}\n\t}\n\n\tif (val16 & BIT(4))\n\t\tbssid->Privacy = 1;\n\telse\n\t\tbssid->Privacy = 0;\n\n\tbssid->Configuration.ATIMWindow = 0;\n\n\t/* 20/40 BSS Coexistence check */\n\tif ((pregistrypriv->wifi_spec == 1) && (_FALSE == pmlmeinfo->bwmode_updated)) {\n\t\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n#ifdef CONFIG_80211N_HT\n\t\tp = rtw_get_ie(bssid->IEs + ie_offset, _HT_CAPABILITY_IE_, &len, bssid->IELength - ie_offset);\n\t\tif (p && len > 0) {\n\t\t\tstruct HT_caps_element\t*pHT_caps;\n\t\t\tpHT_caps = (struct HT_caps_element *)(p + 2);\n\n\t\t\tif (pHT_caps->u.HT_cap_element.HT_caps_info & BIT(14))\n\t\t\t\tpmlmepriv->num_FortyMHzIntolerant++;\n\t\t} else\n\t\t\tpmlmepriv->num_sta_no_ht++;\n#endif /* CONFIG_80211N_HT */\n\n\t}\n\n#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) & 1\n\tif (strcmp(bssid->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) {\n\t\tRTW_INFO(\"Receiving %s(\"MAC_FMT\", DSConfig:%u) from ch%u with ss:%3u, sq:%3u, RawRSSI:%3ld\\n\"\n\t\t\t, bssid->Ssid.Ssid, MAC_ARG(bssid->MacAddress), bssid->Configuration.DSConfig\n\t\t\t , rtw_get_oper_ch(padapter)\n\t\t\t, bssid->PhyInfo.SignalStrength, bssid->PhyInfo.SignalQuality, bssid->Rssi\n\t\t\t);\n\t}\n#endif\n\n\t/* mark bss info receving from nearby channel as SignalQuality 101 */\n\tif (bssid->Configuration.DSConfig != rtw_get_oper_ch(padapter))\n\t\tbssid->PhyInfo.SignalQuality = 101;\n\n#ifdef CONFIG_RTW_80211K\n\tp = rtw_get_ie(bssid->IEs + ie_offset, _EID_RRM_EN_CAP_IE_, &len, bssid->IELength - ie_offset);\n\tif (p)\n\t\t_rtw_memcpy(bssid->PhyInfo.rm_en_cap, (p + 2), *(p + 1));\n\n\t/* save freerun counter */\n\tbssid->PhyInfo.free_cnt = precv_frame->u.hdr.attrib.free_cnt;\n#endif\n\treturn _SUCCESS;\n}\n\nvoid start_create_ibss(_adapter *padapter)\n{\n\tunsigned short\tcaps;\n\tu8\tval8;\n\tu8\tjoin_type;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t\t*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));\n\tu8 doiqk = _FALSE;\n\tpmlmeext->cur_channel = (u8)pnetwork->Configuration.DSConfig;\n\tpmlmeinfo->bcn_interval = get_beacon_interval(pnetwork);\n\n\t/* update wireless mode */\n\tupdate_wireless_mode(padapter);\n\n\t/* udpate capability */\n\tcaps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork);\n\tupdate_capinfo(padapter, caps);\n\tif (caps & cap_IBSS) { /* adhoc master */\n\t\t/* set_opmode_cmd(padapter, adhoc); */ /* removed */\n\n\t\tval8 = 0xcf;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));\n\n\t\tdoiqk = _TRUE;\n\t\trtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);\n\n\t\t/* switch channel */\n\t\tset_channel_bwmode(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n\n\t\tdoiqk = _FALSE;\n\t\trtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);\n\n\t\tbeacon_timing_control(padapter);\n\n\t\t/* set msr to WIFI_FW_ADHOC_STATE */\n\t\tpmlmeinfo->state = WIFI_FW_ADHOC_STATE;\n\t\tSet_MSR(padapter, (pmlmeinfo->state & 0x3));\n\n\t\t/* issue beacon */\n\t\tif (send_beacon(padapter) == _FAIL) {\n\n\t\t\treport_join_res(padapter, -1, WLAN_STATUS_UNSPECIFIED_FAILURE);\n\t\t\tpmlmeinfo->state = WIFI_FW_NULL_STATE;\n\t\t} else {\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress);\n\t\t\trtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);\n\t\t\tjoin_type = 0;\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));\n\n\t\t\treport_join_res(padapter, 1, WLAN_STATUS_SUCCESS);\n\t\t\tpmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;\n\t\t\trtw_indicate_connect(padapter);\n\t\t}\n\t} else {\n\t\tRTW_INFO(\"start_create_ibss, invalid cap:%x\\n\", caps);\n\t\treturn;\n\t}\n\t/* update bc/mc sta_info */\n\tupdate_bmc_sta(padapter);\n\n}\n\nvoid start_clnt_join(_adapter *padapter)\n{\n\tunsigned short\tcaps;\n\tu8\tval8;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t\t*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));\n\tint beacon_timeout;\n\tu8 ASIX_ID[] = {0x00, 0x0E, 0xC6};\n\n\t/* update wireless mode */\n\tupdate_wireless_mode(padapter);\n\n\t/* udpate capability */\n\tcaps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork);\n\tupdate_capinfo(padapter, caps);\n\n\t/* check if sta is ASIX peer and fix IOT issue if it is. */\n\tif (_rtw_memcmp(get_my_bssid(&pmlmeinfo->network) , ASIX_ID , 3)) {\n\t\tu8 iot_flag = _TRUE;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_ASIX_IOT, (u8 *)(&iot_flag));\n\t}\n\n\tif (caps & cap_ESS) {\n\t\tSet_MSR(padapter, WIFI_FW_STATION_STATE);\n\n\t\tval8 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) ? 0xcc : 0xcf;\n\n#ifdef CONFIG_WAPI_SUPPORT\n\t\tif (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) {\n\t\t\t/* Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey. */\n\t\t\tval8 = 0x4c;\n\t\t}\n#endif\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));\n\n#ifdef CONFIG_DEAUTH_BEFORE_CONNECT\n\t\t/* Because of AP's not receiving deauth before */\n\t\t/* AP may: 1)not response auth or 2)deauth us after link is complete */\n\t\t/* issue deauth before issuing auth to deal with the situation */\n\n\t\t/*\tCommented by Albert 2012/07/21 */\n\t\t/*\tFor the Win8 P2P connection, it will be hard to have a successful connection if this Wi-Fi doesn't connect to it. */\n\t\t{\n#ifdef CONFIG_P2P\n\t\t\t_queue *queue = &(padapter->mlmepriv.scanned_queue);\n\t\t\t_list\t*head = get_list_head(queue);\n\t\t\t_list *pos = get_next(head);\n\t\t\tstruct wlan_network *scanned = NULL;\n\t\t\tu8 ie_offset = 0;\n\t\t\t_irqL irqL;\n\t\t\tbool has_p2p_ie = _FALSE;\n\n\t\t\t_enter_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL);\n\n\t\t\tfor (pos = get_next(head); !rtw_end_of_queue_search(head, pos); pos = get_next(pos)) {\n\n\t\t\t\tscanned = LIST_CONTAINOR(pos, struct wlan_network, list);\n\n\t\t\t\tif (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE\n\t\t\t\t    && _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE\n\t\t\t\t   ) {\n\t\t\t\t\tie_offset = (scanned->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12);\n\t\t\t\t\tif (rtw_get_p2p_ie(scanned->network.IEs + ie_offset, scanned->network.IELength - ie_offset, NULL, NULL))\n\t\t\t\t\t\thas_p2p_ie = _TRUE;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t_exit_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL);\n\n\t\t\tif (scanned == NULL || rtw_end_of_queue_search(head, pos) || has_p2p_ie == _FALSE)\n#endif /* CONFIG_P2P */\n\t\t\t\t/* To avoid connecting to AP fail during resume process, change retry count from 5 to 1 */\n\t\t\t\tissue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100);\n\t\t}\n#endif /* CONFIG_DEAUTH_BEFORE_CONNECT */\n\n\t\t/* here wait for receiving the beacon to start auth */\n\t\t/* and enable a timer */\n\t\tbeacon_timeout = decide_wait_for_beacon_timeout(pmlmeinfo->bcn_interval);\n\t\tset_link_timer(pmlmeext, beacon_timeout);\n\t\t_set_timer(&padapter->mlmepriv.assoc_timer,\n\t\t\t(REAUTH_TO * REAUTH_LIMIT) + (REASSOC_TO * REASSOC_LIMIT) + beacon_timeout);\n\n#ifdef CONFIG_RTW_80211R\n\t\tif (rtw_ft_roam(padapter)) {\n\t\t\trtw_ft_start_clnt_join(padapter);\n\t\t} else\n#endif\n\t\t{\n\t\t\trtw_sta_linking_test_set_start();\n\t\t\tpmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE;\n\t\t}\n\t} else if (caps & cap_IBSS) { /* adhoc client */\n\t\tSet_MSR(padapter, WIFI_FW_ADHOC_STATE);\n\n\t\tval8 = 0xcf;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));\n\n\t\tbeacon_timing_control(padapter);\n\n\t\tpmlmeinfo->state = WIFI_FW_ADHOC_STATE;\n\n\t\treport_join_res(padapter, 1, WLAN_STATUS_SUCCESS);\n\t} else {\n\t\t/* RTW_INFO(\"marc: invalid cap:%x\\n\", caps); */\n\t\treturn;\n\t}\n\n}\n\nvoid start_clnt_auth(_adapter *padapter)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n\n\t_cancel_timer_ex(&pmlmeext->link_timer);\n\n\tpmlmeinfo->state &= (~WIFI_FW_AUTH_NULL);\n\tpmlmeinfo->state |= WIFI_FW_AUTH_STATE;\n\n\tpmlmeinfo->auth_seq = 1;\n\tpmlmeinfo->reauth_count = 0;\n\tpmlmeinfo->reassoc_count = 0;\n\tpmlmeinfo->link_count = 0;\n\tpmlmeext->retry = 0;\n\n#ifdef CONFIG_RTW_80211R\n\tif (rtw_ft_roam(padapter)) {\n\t\trtw_ft_set_status(padapter, RTW_FT_AUTHENTICATING_STA);\n\t\tRTW_PRINT(\"start ft auth\\n\");\n\t} else\n#endif\n\t\tRTW_PRINT(\"start auth\\n\");\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (rtw_sec_chk_auth_type(padapter, NL80211_AUTHTYPE_SAE)) {\n\t\tif (rtw_cached_pmkid(padapter, get_my_bssid(&pmlmeinfo->network)) != -1) {\n\t\t\tRTW_INFO(\"SAE: PMKSA cache entry found\\n\");\n\t\t\tpadapter->securitypriv.auth_alg = WLAN_AUTH_OPEN;\n\t\t\tgoto no_external_auth;\n\t\t}\n\n\t\tRTW_PRINT(\"SAE: start external auth\\n\");\n\t\trtw_cfg80211_external_auth_request(padapter, NULL);\n\t\treturn;\n\t}\nno_external_auth:\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n\tissue_auth(padapter, NULL, 0);\n\n\tset_link_timer(pmlmeext, REAUTH_TO);\n\n}\n\n\nvoid start_clnt_assoc(_adapter *padapter)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\t_cancel_timer_ex(&pmlmeext->link_timer);\n\n\tpmlmeinfo->state &= (~(WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE));\n\tpmlmeinfo->state |= (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE);\n\n#ifdef CONFIG_RTW_80211R\n\tif (rtw_ft_roam(padapter))\n\t\tissue_reassocreq(padapter);\n\telse\n#endif\n\t\tissue_assocreq(padapter);\n\n\tset_link_timer(pmlmeext, REASSOC_TO);\n}\n\nunsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, u8 locally_generated)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tif (!(_rtw_memcmp(MacAddr, get_my_bssid(&pmlmeinfo->network), ETH_ALEN)))\n\t\treturn _SUCCESS;\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n#ifdef CONFIG_RTW_REPEATER_SON\n\trtw_rson_do_disconnect(padapter);\n#endif\n\tif ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) {\n\t\tif (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) {\n\t\t\tif (report_del_sta_event(padapter, MacAddr, reason, _TRUE, locally_generated) != _FAIL)\n\t\t\t\tpmlmeinfo->state = WIFI_FW_NULL_STATE;\n\t\t} else if (pmlmeinfo->state & WIFI_FW_LINKING_STATE) {\n\t\t\tif (report_join_res(padapter, -2, reason) != _FAIL)\n\t\t\t\tpmlmeinfo->state = WIFI_FW_NULL_STATE;\n\t\t} else\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" - End to Disconnect\\n\", FUNC_ADPT_ARG(padapter));\n#ifdef CONFIG_RTW_80211R\n\t\trtw_ft_roam_status_reset(padapter);\n#endif\n#ifdef CONFIG_RTW_WNM\n\t\trtw_wnm_reset_btm_state(padapter);\n#endif\n\t}\n\n\treturn _SUCCESS;\n}\n\n#ifdef CONFIG_80211D\nstatic void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tstruct registry_priv *pregistrypriv;\n\tstruct mlme_ext_priv *pmlmeext;\n\tRT_CHANNEL_INFO *chplan_new;\n\tu8 channel;\n\tu8 i;\n\n\n\tpregistrypriv = &padapter->registrypriv;\n\tpmlmeext = &padapter->mlmeextpriv;\n\n\t/* Adjust channel plan by AP Country IE */\n\tif (pregistrypriv->enable80211d\n\t    && (!pmlmeext->update_channel_plan_by_ap_done)) {\n\t\tu8 *ie, *p;\n\t\tu32 len;\n\t\tRT_CHANNEL_PLAN chplan_ap;\n\t\tRT_CHANNEL_INFO *chplan_sta = NULL;\n\t\tu8 country[4];\n\t\tu8 fcn; /* first channel number */\n\t\tu8 noc; /* number of channel */\n\t\tu8 j, k;\n\n\t\tie = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _COUNTRY_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_);\n\t\tif (!ie)\n\t\t\treturn;\n\t\tif (len < 6)\n\t\t\treturn;\n\n\t\tie += 2;\n\t\tp = ie;\n\t\tie += len;\n\n\t\t_rtw_memset(country, 0, 4);\n\t\t_rtw_memcpy(country, p, 3);\n\t\tp += 3;\n\t\tRTW_INFO(\"%s: 802.11d country=%s\\n\", __FUNCTION__, country);\n\n\t\ti = 0;\n\t\twhile ((ie - p) >= 3) {\n\t\t\tfcn = *(p++);\n\t\t\tnoc = *(p++);\n\t\t\tp++;\n\n\t\t\tfor (j = 0; j < noc; j++) {\n\t\t\t\tif (fcn <= 14)\n\t\t\t\t\tchannel = fcn + j; /* 2.4 GHz */\n\t\t\t\telse\n\t\t\t\t\tchannel = fcn + j * 4; /* 5 GHz */\n\n\t\t\t\tchplan_ap.Channel[i++] = channel;\n\t\t\t}\n\t\t}\n\t\tchplan_ap.Len = i;\n\n#ifdef CONFIG_RTW_DEBUG\n\t\ti = 0;\n\t\tRTW_INFO(\"%s: AP[%s] channel plan {\", __FUNCTION__, bssid->Ssid.Ssid);\n\t\twhile ((i < chplan_ap.Len) && (chplan_ap.Channel[i] != 0)) {\n\t\t\t_RTW_INFO(\"%02d,\", chplan_ap.Channel[i]);\n\t\t\ti++;\n\t\t}\n\t\t_RTW_INFO(\"}\\n\");\n#endif\n\n\t\tchplan_sta = rtw_malloc(sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);\n\t\tif (!chplan_sta)\n\t\t\tgoto done_update_chplan_from_ap;\n\n\t\t_rtw_memcpy(chplan_sta, rfctl->channel_set, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);\n#ifdef CONFIG_RTW_DEBUG\n\t\ti = 0;\n\t\tRTW_INFO(\"%s: STA channel plan {\", __FUNCTION__);\n\t\twhile ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) {\n\t\t\t_RTW_INFO(\"%02d(%c),\", chplan_sta[i].ChannelNum, chplan_sta[i].ScanType == SCAN_PASSIVE ? 'p' : 'a');\n\t\t\ti++;\n\t\t}\n\t\t_RTW_INFO(\"}\\n\");\n#endif\n\n\t\t_rtw_memset(rfctl->channel_set, 0, sizeof(rfctl->channel_set));\n\t\tchplan_new = rfctl->channel_set;\n\n\t\ti = j = k = 0;\n\t\tif (pregistrypriv->wireless_mode & WIRELESS_11G) {\n\t\t\tdo {\n\t\t\t\tif ((i == MAX_CHANNEL_NUM)\n\t\t\t\t    || (chplan_sta[i].ChannelNum == 0)\n\t\t\t\t    || (chplan_sta[i].ChannelNum > 14))\n\t\t\t\t\tbreak;\n\n\t\t\t\tif ((j == chplan_ap.Len) || (chplan_ap.Channel[j] > 14))\n\t\t\t\t\tbreak;\n\n\t\t\t\tif (chplan_sta[i].ChannelNum == chplan_ap.Channel[j]) {\n\t\t\t\t\tchplan_new[k].ChannelNum = chplan_ap.Channel[j];\n\t\t\t\t\tchplan_new[k].ScanType = SCAN_ACTIVE;\n\t\t\t\t\ti++;\n\t\t\t\t\tj++;\n\t\t\t\t\tk++;\n\t\t\t\t} else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j]) {\n\t\t\t\t\tchplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;\n#if 0\n\t\t\t\t\tchplan_new[k].ScanType = chplan_sta[i].ScanType;\n#else\n\t\t\t\t\tchplan_new[k].ScanType = SCAN_PASSIVE;\n#endif\n\t\t\t\t\ti++;\n\t\t\t\t\tk++;\n\t\t\t\t} else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j]) {\n\t\t\t\t\tchplan_new[k].ChannelNum = chplan_ap.Channel[j];\n\t\t\t\t\tchplan_new[k].ScanType = SCAN_ACTIVE;\n\t\t\t\t\tj++;\n\t\t\t\t\tk++;\n\t\t\t\t}\n\t\t\t} while (1);\n\n\t\t\t/* change AP not support channel to Passive scan */\n\t\t\twhile ((i < MAX_CHANNEL_NUM)\n\t\t\t       && (chplan_sta[i].ChannelNum != 0)\n\t\t\t       && (chplan_sta[i].ChannelNum <= 14)) {\n\t\t\t\tchplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;\n#if 0\n\t\t\t\tchplan_new[k].ScanType = chplan_sta[i].ScanType;\n#else\n\t\t\t\tchplan_new[k].ScanType = SCAN_PASSIVE;\n#endif\n\t\t\t\ti++;\n\t\t\t\tk++;\n\t\t\t}\n\n\t\t\t/* add channel AP supported */\n\t\t\twhile ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14)) {\n\t\t\t\tchplan_new[k].ChannelNum = chplan_ap.Channel[j];\n\t\t\t\tchplan_new[k].ScanType = SCAN_ACTIVE;\n\t\t\t\tj++;\n\t\t\t\tk++;\n\t\t\t}\n\t\t} else {\n\t\t\t/* keep original STA 2.4G channel plan */\n\t\t\twhile ((i < MAX_CHANNEL_NUM)\n\t\t\t       && (chplan_sta[i].ChannelNum != 0)\n\t\t\t       && (chplan_sta[i].ChannelNum <= 14)) {\n\t\t\t\tchplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;\n\t\t\t\tchplan_new[k].ScanType = chplan_sta[i].ScanType;\n\t\t\t\ti++;\n\t\t\t\tk++;\n\t\t\t}\n\n\t\t\t/* skip AP 2.4G channel plan */\n\t\t\twhile ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14))\n\t\t\t\tj++;\n\t\t}\n\n\t\tif (pregistrypriv->wireless_mode & WIRELESS_11A) {\n\t\t\tdo {\n\t\t\t\tif ((i >= MAX_CHANNEL_NUM)\n\t\t\t\t    || (chplan_sta[i].ChannelNum == 0))\n\t\t\t\t\tbreak;\n\n\t\t\t\tif ((j == chplan_ap.Len) || (chplan_ap.Channel[j] == 0))\n\t\t\t\t\tbreak;\n\n\t\t\t\tif (chplan_sta[i].ChannelNum == chplan_ap.Channel[j]) {\n\t\t\t\t\tchplan_new[k].ChannelNum = chplan_ap.Channel[j];\n\t\t\t\t\tchplan_new[k].ScanType = SCAN_ACTIVE;\n\t\t\t\t\ti++;\n\t\t\t\t\tj++;\n\t\t\t\t\tk++;\n\t\t\t\t} else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j]) {\n\t\t\t\t\tchplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;\n#if 0\n\t\t\t\t\tchplan_new[k].ScanType = chplan_sta[i].ScanType;\n#else\n\t\t\t\t\tchplan_new[k].ScanType = SCAN_PASSIVE;\n#endif\n\t\t\t\t\ti++;\n\t\t\t\t\tk++;\n\t\t\t\t} else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j]) {\n\t\t\t\t\tchplan_new[k].ChannelNum = chplan_ap.Channel[j];\n\t\t\t\t\tchplan_new[k].ScanType = SCAN_ACTIVE;\n\t\t\t\t\tj++;\n\t\t\t\t\tk++;\n\t\t\t\t}\n\t\t\t} while (1);\n\n\t\t\t/* change AP not support channel to Passive scan */\n\t\t\twhile ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) {\n\t\t\t\tchplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;\n#if 0\n\t\t\t\tchplan_new[k].ScanType = chplan_sta[i].ScanType;\n#else\n\t\t\t\tchplan_new[k].ScanType = SCAN_PASSIVE;\n#endif\n\t\t\t\ti++;\n\t\t\t\tk++;\n\t\t\t}\n\n\t\t\t/* add channel AP supported */\n\t\t\twhile ((j < chplan_ap.Len) && (chplan_ap.Channel[j] != 0)) {\n\t\t\t\tchplan_new[k].ChannelNum = chplan_ap.Channel[j];\n\t\t\t\tchplan_new[k].ScanType = SCAN_ACTIVE;\n\t\t\t\tj++;\n\t\t\t\tk++;\n\t\t\t}\n\t\t} else {\n\t\t\t/* keep original STA 5G channel plan */\n\t\t\twhile ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) {\n\t\t\t\tchplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;\n\t\t\t\tchplan_new[k].ScanType = chplan_sta[i].ScanType;\n\t\t\t\ti++;\n\t\t\t\tk++;\n\t\t\t}\n\t\t}\n\n\t\tpmlmeext->update_channel_plan_by_ap_done = 1;\n\n#ifdef CONFIG_RTW_DEBUG\n\t\tk = 0;\n\t\tRTW_INFO(\"%s: new STA channel plan {\", __FUNCTION__);\n\t\twhile ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0)) {\n\t\t\t_RTW_INFO(\"%02d(%c),\", chplan_new[k].ChannelNum, chplan_new[k].ScanType == SCAN_PASSIVE ? 'p' : 'c');\n\t\t\tk++;\n\t\t}\n\t\t_RTW_INFO(\"}\\n\");\n#endif\n\n#if 0\n\t\t/* recover the right channel index */\n\t\tchannel = chplan_sta[pmlmeext->sitesurvey_res.channel_idx].ChannelNum;\n\t\tk = 0;\n\t\twhile ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0)) {\n\t\t\tif (chplan_new[k].ChannelNum == channel) {\n\t\t\t\tRTW_INFO(\"%s: change mlme_ext sitesurvey channel index from %d to %d\\n\",\n\t\t\t\t\t__FUNCTION__, pmlmeext->sitesurvey_res.channel_idx, k);\n\t\t\t\tpmlmeext->sitesurvey_res.channel_idx = k;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tk++;\n\t\t}\n#endif\n\ndone_update_chplan_from_ap:\n\t\tif (chplan_sta)\n\t\t\trtw_mfree(chplan_sta, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);\n\t}\n}\n#endif\n\n/****************************************************************************\n\nFollowing are the functions to report events\n\n*****************************************************************************/\n\nvoid report_survey_event(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tstruct cmd_obj *pcmd_obj;\n\tu8\t*pevtcmd;\n\tu32 cmdsz;\n\tstruct survey_event\t*psurvey_evt;\n\tstruct C2HEvent_Header *pc2h_evt_hdr;\n\tstruct mlme_ext_priv *pmlmeext;\n\tstruct cmd_priv *pcmdpriv;\n\t/* u8 *pframe = precv_frame->u.hdr.rx_data; */\n\t/* uint len = precv_frame->u.hdr.len; */\n\tRT_CHANNEL_INFO *chset = adapter_to_chset(padapter);\n\tint ch_set_idx = -1;\n\n\tif (!padapter)\n\t\treturn;\n\n\tpmlmeext = &padapter->mlmeextpriv;\n\tpcmdpriv = &padapter->cmdpriv;\n\n\n\tpcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (pcmd_obj == NULL)\n\t\treturn;\n\n\tcmdsz = (sizeof(struct survey_event) + sizeof(struct C2HEvent_Header));\n\tpevtcmd = (u8 *)rtw_zmalloc(cmdsz);\n\tif (pevtcmd == NULL) {\n\t\trtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));\n\t\treturn;\n\t}\n\n\t_rtw_init_listhead(&pcmd_obj->list);\n\n\tpcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);\n\tpcmd_obj->cmdsz = cmdsz;\n\tpcmd_obj->parmbuf = pevtcmd;\n\n\tpcmd_obj->rsp = NULL;\n\tpcmd_obj->rspsz  = 0;\n\n\tpc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd);\n\tpc2h_evt_hdr->len = sizeof(struct survey_event);\n\tpc2h_evt_hdr->ID = GEN_EVT_CODE(_Survey);\n\tpc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);\n\n\tpsurvey_evt = (struct survey_event *)(pevtcmd + sizeof(struct C2HEvent_Header));\n\n\tif (collect_bss_info(padapter, precv_frame, (WLAN_BSSID_EX *)&psurvey_evt->bss) == _FAIL) {\n\t\trtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));\n\t\trtw_mfree((u8 *)pevtcmd, cmdsz);\n\t\treturn;\n\t}\n\n#ifdef CONFIG_80211D\n\tprocess_80211d(padapter, &psurvey_evt->bss);\n#endif\n\n\tch_set_idx = rtw_chset_search_ch(chset, psurvey_evt->bss.Configuration.DSConfig);\n\tif (ch_set_idx >= 0) {\n\t\tif (psurvey_evt->bss.InfrastructureMode == Ndis802_11Infrastructure) {\n\t\t\tif (chset[ch_set_idx].ScanType == SCAN_PASSIVE\n\t\t\t\t&& !rtw_is_dfs_ch(psurvey_evt->bss.Configuration.DSConfig)\n\t\t\t) {\n\t\t\t\tRTW_INFO(\"%s: change ch:%d to active\\n\", __func__, psurvey_evt->bss.Configuration.DSConfig);\n\t\t\t\tchset[ch_set_idx].ScanType = SCAN_ACTIVE;\n\t\t\t}\n\t\t\t#ifdef CONFIG_DFS\n\t\t\tif (hidden_ssid_ap(&psurvey_evt->bss))\n\t\t\t\tchset[ch_set_idx].hidden_bss_cnt++;\n\t\t\t#endif\n\t\t}\n\t}\n\n\trtw_enqueue_cmd(pcmdpriv, pcmd_obj);\n\n\tpmlmeext->sitesurvey_res.bss_cnt++;\n\n\treturn;\n\n}\n\nvoid report_surveydone_event(_adapter *padapter)\n{\n\tstruct cmd_obj *pcmd_obj;\n\tu8\t*pevtcmd;\n\tu32 cmdsz;\n\tstruct surveydone_event *psurveydone_evt;\n\tstruct C2HEvent_Header\t*pc2h_evt_hdr;\n\tstruct mlme_ext_priv\t\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct cmd_priv *pcmdpriv = &padapter->cmdpriv;\n\n\tpcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (pcmd_obj == NULL)\n\t\treturn;\n\n\tcmdsz = (sizeof(struct surveydone_event) + sizeof(struct C2HEvent_Header));\n\tpevtcmd = (u8 *)rtw_zmalloc(cmdsz);\n\tif (pevtcmd == NULL) {\n\t\trtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));\n\t\treturn;\n\t}\n\n\t_rtw_init_listhead(&pcmd_obj->list);\n\n\tpcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);\n\tpcmd_obj->cmdsz = cmdsz;\n\tpcmd_obj->parmbuf = pevtcmd;\n\n\tpcmd_obj->rsp = NULL;\n\tpcmd_obj->rspsz  = 0;\n\n\tpc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd);\n\tpc2h_evt_hdr->len = sizeof(struct surveydone_event);\n\tpc2h_evt_hdr->ID = GEN_EVT_CODE(_SurveyDone);\n\tpc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);\n\n\tpsurveydone_evt = (struct surveydone_event *)(pevtcmd + sizeof(struct C2HEvent_Header));\n\tpsurveydone_evt->bss_cnt = pmlmeext->sitesurvey_res.bss_cnt;\n\n\tRTW_INFO(\"survey done event(%x) band:%d for \"ADPT_FMT\"\\n\", psurveydone_evt->bss_cnt, padapter->setband, ADPT_ARG(padapter));\n\n\trtw_enqueue_cmd(pcmdpriv, pcmd_obj);\n\n\treturn;\n\n}\n\nu32 report_join_res(_adapter *padapter, int aid_res, u16 status)\n{\n\tstruct cmd_obj *pcmd_obj;\n\tu8\t*pevtcmd;\n\tu32 cmdsz;\n\tstruct joinbss_event\t\t*pjoinbss_evt;\n\tstruct C2HEvent_Header\t*pc2h_evt_hdr;\n\tstruct mlme_ext_priv\t\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct cmd_priv *pcmdpriv = &padapter->cmdpriv;\n\tu32 ret = _FAIL;\n\n\tpcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (pcmd_obj == NULL)\n\t\tgoto exit;\n\n\tcmdsz = (sizeof(struct joinbss_event) + sizeof(struct C2HEvent_Header));\n\tpevtcmd = (u8 *)rtw_zmalloc(cmdsz);\n\tif (pevtcmd == NULL) {\n\t\trtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));\n\t\tgoto exit;\n\t}\n\n\t_rtw_init_listhead(&pcmd_obj->list);\n\n\tpcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);\n\tpcmd_obj->cmdsz = cmdsz;\n\tpcmd_obj->parmbuf = pevtcmd;\n\n\tpcmd_obj->rsp = NULL;\n\tpcmd_obj->rspsz  = 0;\n\n\tpc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd);\n\tpc2h_evt_hdr->len = sizeof(struct joinbss_event);\n\tpc2h_evt_hdr->ID = GEN_EVT_CODE(_JoinBss);\n\tpc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);\n\n\tpjoinbss_evt = (struct joinbss_event *)(pevtcmd + sizeof(struct C2HEvent_Header));\n\t_rtw_memcpy((unsigned char *)(&(pjoinbss_evt->network.network)), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX));\n\tpjoinbss_evt->network.join_res\t= pjoinbss_evt->network.aid = aid_res;\n\n\tRTW_INFO(\"report_join_res(%d, %u)\\n\", aid_res, status);\n\n\n\trtw_joinbss_event_prehandle(padapter, (u8 *)&pjoinbss_evt->network, status);\n\n\n\tret = rtw_enqueue_cmd(pcmdpriv, pcmd_obj);\n\nexit:\n\treturn ret;\n}\n\nvoid report_wmm_edca_update(_adapter *padapter)\n{\n\tstruct cmd_obj *pcmd_obj;\n\tu8\t*pevtcmd;\n\tu32 cmdsz;\n\tstruct wmm_event\t\t*pwmm_event;\n\tstruct C2HEvent_Header\t*pc2h_evt_hdr;\n\tstruct mlme_ext_priv\t\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct cmd_priv *pcmdpriv = &padapter->cmdpriv;\n\n\tpcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (pcmd_obj == NULL)\n\t\treturn;\n\n\tcmdsz = (sizeof(struct wmm_event) + sizeof(struct C2HEvent_Header));\n\tpevtcmd = (u8 *)rtw_zmalloc(cmdsz);\n\tif (pevtcmd == NULL) {\n\t\trtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));\n\t\treturn;\n\t}\n\n\t_rtw_init_listhead(&pcmd_obj->list);\n\n\tpcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);\n\tpcmd_obj->cmdsz = cmdsz;\n\tpcmd_obj->parmbuf = pevtcmd;\n\n\tpcmd_obj->rsp = NULL;\n\tpcmd_obj->rspsz  = 0;\n\n\tpc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd);\n\tpc2h_evt_hdr->len = sizeof(struct wmm_event);\n\tpc2h_evt_hdr->ID = GEN_EVT_CODE(_WMM);\n\tpc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);\n\n\tpwmm_event = (struct wmm_event *)(pevtcmd + sizeof(struct C2HEvent_Header));\n\tpwmm_event->wmm = 0;\n\n\trtw_enqueue_cmd(pcmdpriv, pcmd_obj);\n\n\treturn;\n\n}\n\nu32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, bool enqueue, u8 locally_generated)\n{\n\tstruct cmd_obj *pcmd_obj;\n\tu8\t*pevtcmd;\n\tu32 cmdsz;\n\tstruct sta_info *psta;\n\tint\tmac_id = -1;\n\tstruct stadel_event\t\t\t*pdel_sta_evt;\n\tstruct C2HEvent_Header\t*pc2h_evt_hdr;\n\tstruct mlme_ext_priv\t\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct cmd_priv *pcmdpriv = &padapter->cmdpriv;\n\tu8 res = _SUCCESS;\n\n\t/* prepare cmd parameter */\n\tcmdsz = (sizeof(struct stadel_event) + sizeof(struct C2HEvent_Header));\n\tpevtcmd = (u8 *)rtw_zmalloc(cmdsz);\n\tif (pevtcmd == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd);\n\tpc2h_evt_hdr->len = sizeof(struct stadel_event);\n\tpc2h_evt_hdr->ID = GEN_EVT_CODE(_DelSTA);\n\tpc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);\n\n\tpdel_sta_evt = (struct stadel_event *)(pevtcmd + sizeof(struct C2HEvent_Header));\n\t_rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN);\n\t_rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd), (unsigned char *)(&reason), 2);\n\tpsta = rtw_get_stainfo(&padapter->stapriv, MacAddr);\n\tif (psta)\n\t\tmac_id = (int)psta->cmn.mac_id;\n\telse\n\t\tmac_id = (-1);\n\tpdel_sta_evt->mac_id = mac_id;\n\tpdel_sta_evt->locally_generated = locally_generated;\n\n\tif (!enqueue) {\n\t\t/* do directly */\n\t\trtw_stadel_event_callback(padapter, (u8 *)pdel_sta_evt);\n\t\trtw_mfree(pevtcmd, cmdsz);\n\t} else {\n\t\tpcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\t\tif (pcmd_obj == NULL) {\n\t\t\trtw_mfree(pevtcmd, cmdsz);\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t_rtw_init_listhead(&pcmd_obj->list);\n\t\tpcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);\n\t\tpcmd_obj->cmdsz = cmdsz;\n\t\tpcmd_obj->parmbuf = pevtcmd;\n\n\t\tpcmd_obj->rsp = NULL;\n\t\tpcmd_obj->rspsz  = 0;\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, pcmd_obj);\n\t}\n\nexit:\n\n\tRTW_INFO(FUNC_ADPT_FMT\" \"MAC_FMT\" mac_id=%d, enqueue:%d, res:%u\\n\"\n\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(MacAddr), mac_id, enqueue, res);\n\n\treturn res;\n}\n\nvoid report_add_sta_event(_adapter *padapter, unsigned char *MacAddr)\n{\n\tstruct cmd_obj *pcmd_obj;\n\tu8\t*pevtcmd;\n\tu32 cmdsz;\n\tstruct stassoc_event\t\t*padd_sta_evt;\n\tstruct C2HEvent_Header\t*pc2h_evt_hdr;\n\tstruct mlme_ext_priv\t\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct cmd_priv *pcmdpriv = &padapter->cmdpriv;\n\n\tpcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (pcmd_obj == NULL)\n\t\treturn;\n\n\tcmdsz = (sizeof(struct stassoc_event) + sizeof(struct C2HEvent_Header));\n\tpevtcmd = (u8 *)rtw_zmalloc(cmdsz);\n\tif (pevtcmd == NULL) {\n\t\trtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));\n\t\treturn;\n\t}\n\n\t_rtw_init_listhead(&pcmd_obj->list);\n\n\tpcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);\n\tpcmd_obj->cmdsz = cmdsz;\n\tpcmd_obj->parmbuf = pevtcmd;\n\n\tpcmd_obj->rsp = NULL;\n\tpcmd_obj->rspsz  = 0;\n\n\tpc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd);\n\tpc2h_evt_hdr->len = sizeof(struct stassoc_event);\n\tpc2h_evt_hdr->ID = GEN_EVT_CODE(_AddSTA);\n\tpc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);\n\n\tpadd_sta_evt = (struct stassoc_event *)(pevtcmd + sizeof(struct C2HEvent_Header));\n\t_rtw_memcpy((unsigned char *)(&(padd_sta_evt->macaddr)), MacAddr, ETH_ALEN);\n\n\tRTW_INFO(\"report_add_sta_event: add STA\\n\");\n\n\trtw_enqueue_cmd(pcmdpriv, pcmd_obj);\n\n\treturn;\n}\n\n\nbool rtw_port_switch_chk(_adapter *adapter)\n{\n\tbool switch_needed = _FALSE;\n#ifdef CONFIG_CONCURRENT_MODE\n#ifdef CONFIG_RUNTIME_PORT_SWITCH\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct pwrctrl_priv *pwrctl = dvobj_to_pwrctl(dvobj);\n\t_adapter *if_port0 = NULL;\n\t_adapter *if_port1 = NULL;\n\tstruct mlme_ext_info *if_port0_mlmeinfo = NULL;\n\tstruct mlme_ext_info *if_port1_mlmeinfo = NULL;\n\tint i;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tif (get_hw_port(dvobj->padapters[i]) == HW_PORT0) {\n\t\t\tif_port0 = dvobj->padapters[i];\n\t\t\tif_port0_mlmeinfo = &(if_port0->mlmeextpriv.mlmext_info);\n\t\t} else if (get_hw_port(dvobj->padapters[i]) == HW_PORT1) {\n\t\t\tif_port1 = dvobj->padapters[i];\n\t\t\tif_port1_mlmeinfo = &(if_port1->mlmeextpriv.mlmext_info);\n\t\t}\n\t}\n\n\tif (if_port0 == NULL) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (if_port1 == NULL) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n#ifdef DBG_RUNTIME_PORT_SWITCH\n\tRTW_INFO(FUNC_ADPT_FMT\" wowlan_mode:%u\\n\"\n\t\t ADPT_FMT\", port0, mlmeinfo->state:0x%08x, p2p_state:%d, %d\\n\"\n\t\t ADPT_FMT\", port1, mlmeinfo->state:0x%08x, p2p_state:%d, %d\\n\",\n\t\t FUNC_ADPT_ARG(adapter), pwrctl->wowlan_mode,\n\t\tADPT_ARG(if_port0), if_port0_mlmeinfo->state, rtw_p2p_state(&if_port0->wdinfo), rtw_p2p_chk_state(&if_port0->wdinfo, P2P_STATE_NONE),\n\t\tADPT_ARG(if_port1), if_port1_mlmeinfo->state, rtw_p2p_state(&if_port1->wdinfo), rtw_p2p_chk_state(&if_port1->wdinfo, P2P_STATE_NONE));\n#endif /* DBG_RUNTIME_PORT_SWITCH */\n\n#ifdef CONFIG_WOWLAN\n\t/* WOWLAN interface(primary, for now) should be port0 */\n\tif (pwrctl->wowlan_mode == _TRUE) {\n\t\tif (!is_primary_adapter(if_port0)) {\n\t\t\tRTW_INFO(\"%s \"ADPT_FMT\" enable WOWLAN\\n\", __func__, ADPT_ARG(if_port1));\n\t\t\tswitch_needed = _TRUE;\n\t\t}\n\t\tgoto exit;\n\t}\n#endif /* CONFIG_WOWLAN */\n\n\t/* AP/Mesh should use port0 for ctl frame's ack */\n\tif ((if_port1_mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {\n\t\tRTW_INFO(\"%s \"ADPT_FMT\" is AP/GO/Mesh\\n\", __func__, ADPT_ARG(if_port1));\n\t\tswitch_needed = _TRUE;\n\t\tgoto exit;\n\t}\n\n\t/* GC should use port0 for p2p ps */\n\tif (((if_port1_mlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE)\n\t    && (if_port1_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)\n#ifdef CONFIG_P2P\n\t    && !rtw_p2p_chk_state(&if_port1->wdinfo, P2P_STATE_NONE)\n#endif\n\t    && !check_fwstate(&if_port1->mlmepriv, WIFI_UNDER_WPS)\n\t   ) {\n\t\tRTW_INFO(\"%s \"ADPT_FMT\" is GC\\n\", __func__, ADPT_ARG(if_port1));\n\t\tswitch_needed = _TRUE;\n\t\tgoto exit;\n\t}\n\n\t/* port1 linked, but port0 not linked */\n\tif ((if_port1_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)\n\t    && !(if_port0_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)\n\t    && ((if_port0_mlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)\n\t   ) {\n\t\tRTW_INFO(\"%s \"ADPT_FMT\" is SINGLE_LINK\\n\", __func__, ADPT_ARG(if_port1));\n\t\tswitch_needed = _TRUE;\n\t\tgoto exit;\n\t}\n\nexit:\n#ifdef DBG_RUNTIME_PORT_SWITCH\n\tRTW_INFO(FUNC_ADPT_FMT\" ret:%d\\n\", FUNC_ADPT_ARG(adapter), switch_needed);\n#endif /* DBG_RUNTIME_PORT_SWITCH */\n#endif /* CONFIG_RUNTIME_PORT_SWITCH */\n#endif /* CONFIG_CONCURRENT_MODE */\n\treturn switch_needed;\n}\n\n/****************************************************************************\n\nFollowing are the event callback functions\n\n*****************************************************************************/\n\n/* for sta/adhoc mode */\nvoid update_sta_info(_adapter *padapter, struct sta_info *psta)\n{\n\t_irqL\tirqL;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\t/* ERP */\n\tVCS_update(padapter, psta);\n\n#ifdef CONFIG_80211N_HT\n\t/* HT */\n\tif (pmlmepriv->htpriv.ht_option) {\n\t\tpsta->htpriv.ht_option = _TRUE;\n\n\t\tpsta->htpriv.ampdu_enable = pmlmepriv->htpriv.ampdu_enable;\n\n\t\tpsta->htpriv.rx_ampdu_min_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & IEEE80211_HT_CAP_AMPDU_DENSITY) >> 2;\n\n\t\tif (support_short_GI(padapter, &(pmlmeinfo->HT_caps), CHANNEL_WIDTH_20))\n\t\t\tpsta->htpriv.sgi_20m = _TRUE;\n\n\t\tif (support_short_GI(padapter, &(pmlmeinfo->HT_caps), CHANNEL_WIDTH_40))\n\t\t\tpsta->htpriv.sgi_40m = _TRUE;\n\n\t\tpsta->qos_option = _TRUE;\n\n\t\tpsta->htpriv.ldpc_cap = pmlmepriv->htpriv.ldpc_cap;\n\t\tpsta->htpriv.stbc_cap = pmlmepriv->htpriv.stbc_cap;\n\t\tpsta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap;\n\n\t\t_rtw_memcpy(&psta->htpriv.ht_cap, &pmlmeinfo->HT_caps, sizeof(struct rtw_ieee80211_ht_cap));\n\t\t#ifdef CONFIG_BEAMFORMING\n\t\tpsta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap;\n\t\tpsta->cmn.bf_info.ht_beamform_cap = pmlmepriv->htpriv.beamform_cap;\n\t\t#endif\n\t} else\n#endif /* CONFIG_80211N_HT */\n\t{\n#ifdef CONFIG_80211N_HT\n\t\tpsta->htpriv.ht_option = _FALSE;\n\t\tpsta->htpriv.ampdu_enable = _FALSE;\n\t\tpsta->htpriv.tx_amsdu_enable = _FALSE;\n\t\tpsta->htpriv.sgi_20m = _FALSE;\n\t\tpsta->htpriv.sgi_40m = _FALSE;\n#endif /* CONFIG_80211N_HT */\n\t\tpsta->qos_option = _FALSE;\n\n\t}\n\n#ifdef CONFIG_80211N_HT\n\tpsta->htpriv.ch_offset = pmlmeext->cur_ch_offset;\n\n\tpsta->htpriv.agg_enable_bitmap = 0x0;/* reset */\n\tpsta->htpriv.candidate_tid_bitmap = 0x0;/* reset */\n#endif /* CONFIG_80211N_HT */\n\n\tpsta->cmn.bw_mode = pmlmeext->cur_bwmode;\n\n\t/* QoS */\n\tif (pmlmepriv->qospriv.qos_option)\n\t\tpsta->qos_option = _TRUE;\n\n#ifdef CONFIG_80211AC_VHT\n\t_rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv));\n\tif (psta->vhtpriv.vht_option) {\n\t\tpsta->cmn.ra_info.is_vht_enable = _TRUE;\n\t\t#ifdef CONFIG_BEAMFORMING\n\t\tpsta->vhtpriv.beamform_cap = pmlmepriv->vhtpriv.beamform_cap;\n\t\tpsta->cmn.bf_info.vht_beamform_cap = pmlmepriv->vhtpriv.beamform_cap;\n\t\t#endif /*CONFIG_BEAMFORMING*/\n\t}\n#endif /* CONFIG_80211AC_VHT */\n\tpsta->cmn.ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta));\n\tupdate_ldpc_stbc_cap(psta);\n\n\t_enter_critical_bh(&psta->lock, &irqL);\n\tpsta->state = _FW_LINKED;\n\t_exit_critical_bh(&psta->lock, &irqL);\n\n}\n\nstatic void rtw_mlmeext_disconnect(_adapter *padapter)\n{\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8 self_action = MLME_ACTION_UNKNOWN;\n\tu8 state_backup = (pmlmeinfo->state & 0x03);\n\tu8 ASIX_ID[] = {0x00, 0x0E, 0xC6};\n\n\tif (MLME_IS_AP(padapter))\n\t\tself_action = MLME_AP_STOPPED;\n\telse if (MLME_IS_MESH(padapter))\n\t\tself_action = MLME_MESH_STOPPED;\n\telse if (MLME_IS_STA(padapter))\n\t\tself_action = MLME_STA_DISCONNECTED;\n\telse if (MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter))\n\t\tself_action = MLME_ADHOC_STOPPED;\n\telse {\n\t\tRTW_INFO(\"state:0x%x\\n\", MLME_STATE(padapter));\n\t\trtw_warn_on(1);\n\t}\n\n\t/* set_opmode_cmd(padapter, infra_client_with_mlme); */\n#ifdef CONFIG_HW_P0_TSF_SYNC\n\tif (self_action == MLME_STA_DISCONNECTED)\n\t\tcorrect_TSF(padapter, self_action);\n#endif\n\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0);\n\trtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr);\n\tif (self_action == MLME_STA_DISCONNECTED)\n\t\trtw_hal_rcr_set_chk_bssid(padapter, self_action);\n\n\t/* set MSR to no link state->infra. mode */\n\tSet_MSR(padapter, _HW_STATE_STATION_);\n\n\t/* check if sta is ASIX peer and fix IOT issue if it is. */\n\tif (_rtw_memcmp(get_my_bssid(&pmlmeinfo->network) , ASIX_ID , 3)) {\n\t\tu8 iot_flag = _FALSE;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_ASIX_IOT, (u8 *)(&iot_flag));\n\t}\n\tpmlmeinfo->state = WIFI_FW_NULL_STATE;\n\n#ifdef CONFIG_MCC_MODE\n\t/* mcc disconnect setting before download LPS rsvd page */\n\trtw_hal_set_mcc_setting_disconnect(padapter);\n#endif /* CONFIG_MCC_MODE */\n\n\tif (state_backup == WIFI_FW_STATION_STATE) {\n\t\tif (rtw_port_switch_chk(padapter) == _TRUE) {\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);\n#ifdef CONFIG_LPS\n\t\t\t{\n\t\t\t\t_adapter *port0_iface = dvobj_get_port0_adapter(adapter_to_dvobj(padapter));\n\t\t\t\tif (port0_iface)\n\t\t\t\t\trtw_lps_ctrl_wk_cmd(port0_iface, LPS_CTRL_CONNECT, RTW_CMDF_DIRECTLY);\n\t\t\t}\n#endif\n\t\t}\n\t}\n\n\t/* switch to the 20M Hz mode after disconnect */\n\tpmlmeext->cur_bwmode = CHANNEL_WIDTH_20;\n\tpmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n#ifdef CONFIG_CTRL_TXSS_BY_TP\n\tpmlmeext->txss_1ss = _FALSE;\n#endif\n\n#ifdef CONFIG_FCS_MODE\n\tif (EN_FCS(padapter))\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_STOP_FCS_MODE, NULL);\n#endif\n\n\tif (!(MLME_IS_STA(padapter) && MLME_IS_OPCH_SW(padapter))) {\n\t\t/* DFS and channel status no need to check here for STA under OPCH_SW */\n\t\tu8 ch, bw, offset;\n\n\t\t#ifdef CONFIG_DFS_MASTER\n\t\trtw_dfs_rd_en_decision(padapter, self_action, 0);\n\t\t#endif\n\n\t\tif (rtw_mi_get_ch_setting_union_no_self(padapter, &ch, &bw, &offset) != 0) {\n\t\t\tset_channel_bwmode(padapter, ch, offset, bw);\n\t\t\trtw_mi_update_union_chan_inf(padapter, ch, offset, bw);\n\t\t}\n\t}\n\n\tflush_all_cam_entry(padapter);\n\n\t_cancel_timer_ex(&pmlmeext->link_timer);\n\n\t/* pmlmepriv->LinkDetectInfo.TrafficBusyState = _FALSE; */\n\tpmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0;\n\tpmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0;\n\n#ifdef CONFIG_TDLS\n\tpadapter->tdlsinfo.ap_prohibited = _FALSE;\n\n\t/* For TDLS channel switch, currently we only allow it to work in wifi logo test mode */\n\tif (padapter->registrypriv.wifi_spec == 1)\n\t\tpadapter->tdlsinfo.ch_switch_prohibited = _FALSE;\n#endif /* CONFIG_TDLS */\n\n#ifdef CONFIG_WMMPS_STA\n\t if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {\n\t\t/* reset currently related uapsd setting when the connection has broken */\n\t\tpmlmepriv->qospriv.uapsd_max_sp_len = 0;\n\t\tpmlmepriv->qospriv.uapsd_tid = 0;\n\t\tpmlmepriv->qospriv.uapsd_tid_delivery_enabled = 0;\n\t\tpmlmepriv->qospriv.uapsd_tid_trigger_enabled = 0;\n\t\tpmlmepriv->qospriv.uapsd_ap_supported = 0;\n\t}\n#endif /* CONFIG_WMMPS_STA */\n#ifdef CONFIG_RTS_FULL_BW\n\trtw_set_rts_bw(padapter);\n#endif/*CONFIG_RTS_FULL_BW*/\n\n}\n\nvoid mlmeext_joinbss_event_callback(_adapter *padapter, int join_res)\n{\n\tstruct sta_info\t\t*psta;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t\t*cur_network = &(pmlmeinfo->network);\n\tstruct sta_priv\t\t*pstapriv = &padapter->stapriv;\n\tu8\tjoin_type;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\n#ifndef CONFIG_IOCTL_CFG80211\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n#endif\n\n\tif (pmlmepriv->wpa_phase == _TRUE)\n\t\tpmlmepriv->wpa_phase = _FALSE;\n\n\tif (join_res < 0) {\n\t\tjoin_type = 1;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr);\n\t\tif ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE)\n\t\t\trtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_DISCONNECTED);\n\n\t\tgoto exit_mlmeext_joinbss_event_callback;\n\t}\n\n#ifdef CONFIG_ARP_KEEP_ALIVE\n\tpmlmepriv->bGetGateway = 1;\n\tpmlmepriv->GetGatewayTryCnt = 0;\n#endif\n\n\tif ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {\n\t\t/* update bc/mc sta_info */\n\t\tupdate_bmc_sta(padapter);\n\t}\n\n\n\t/* turn on dynamic functions */\n\t/* Switch_DM_Func(padapter, DYNAMIC_ALL_FUNC_ENABLE, _TRUE); */\n\n\t/* update IOT-releated issue */\n\tupdate_IOT_info(padapter);\n\n\t#ifdef CONFIG_RTS_FULL_BW\n\trtw_set_rts_bw(padapter);\n\t#endif/*CONFIG_RTS_FULL_BW*/\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, cur_network->SupportedRates);\n\n\t/* BCN interval */\n\trtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pmlmeinfo->bcn_interval));\n\n\t/* udpate capability */\n\tupdate_capinfo(padapter, pmlmeinfo->capability);\n\n\t/* WMM, Update EDCA param */\n\tWMMOnAssocRsp(padapter);\n#ifdef CONFIG_80211N_HT\n\t/* HT */\n\tHTOnAssocRsp(padapter);\n#endif /* CONFIG_80211N_HT */\n#ifdef CONFIG_80211AC_VHT\n\t/* VHT */\n\tVHTOnAssocRsp(padapter);\n#endif\n\n\tpsta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);\n\tif (psta) { /* only for infra. mode */\n\t\tpsta->wireless_mode = pmlmeext->cur_wireless_mode;\n\n\t\t/* set per sta rate after updating HT cap. */\n\t\tset_sta_rate(padapter, psta);\n\n\t\trtw_sta_media_status_rpt(padapter, psta, 1);\n\n\t\t/* wakeup macid after join bss successfully to ensure\n\t\t\tthe subsequent data frames can be sent out normally */\n\t\trtw_hal_macid_wakeup(padapter, psta->cmn.mac_id);\n\n\t\trtw_xmit_queue_clear(psta);\n\t}\n\n#ifndef CONFIG_IOCTL_CFG80211\n\tif (is_wep_enc(psecuritypriv->dot11PrivacyAlgrthm))\n\t\trtw_sec_restore_wep_key(padapter);\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n\tif (rtw_port_switch_chk(padapter) == _TRUE)\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);\n\n\tjoin_type = 2;\n\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));\n\n\tif ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) {\n\t\trtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTED);\n\n\t\t/* correcting TSF */\n\t\tcorrect_TSF(padapter, MLME_STA_CONNECTED);\n\n\t\t/* set_link_timer(pmlmeext, DISCONNECT_TO); */\n\t}\n\n#ifdef CONFIG_LPS\n\t#ifndef CONFIG_FW_MULTI_PORT_SUPPORT\n\tif (get_hw_port(padapter) == HW_PORT0)\n\t#endif\n\t\trtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_CONNECT, RTW_CMDF_DIRECTLY);\n#endif\n\n#ifdef CONFIG_BEAMFORMING\n\tif (psta)\n\t\tbeamforming_wk_cmd(padapter, BEAMFORMING_CTRL_ENTER, (u8 *)psta, sizeof(struct sta_info), 0);\n#endif/*CONFIG_BEAMFORMING*/\n\nexit_mlmeext_joinbss_event_callback:\n\n\trtw_join_done_chk_ch(padapter, join_res);\n#ifdef CONFIG_RTW_REPEATER_SON\n\trtw_rson_join_done(padapter);\n#endif\n\tRTW_INFO(\"=>%s - End to Connection without 4-way\\n\", __FUNCTION__);\n}\n\n/* currently only adhoc mode will go here */\nvoid mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8\tjoin_type;\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\tif ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {\n\t\tif (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { /* adhoc master or sta_count>1 */\n\t\t\t/* nothing to do */\n\t\t} else { /* adhoc client */\n\t\t\t/* update TSF Value */\n\t\t\t/* update_TSF(pmlmeext, pframe, len);\t\t\t */\n\n\t\t\t/* correcting TSF */\n\t\t\tcorrect_TSF(padapter, MLME_ADHOC_STARTED);\n\n\t\t\t/* start beacon */\n\t\t\tif (send_beacon(padapter) == _FAIL)\n\t\t\t\trtw_warn_on(1);\n\n\t\t\tpmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;\n\t\t}\n\n\t\tjoin_type = 2;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));\n\t}\n\n\t/* update adhoc sta_info */\n\tupdate_sta_info(padapter, psta);\n\n\trtw_hal_update_sta_ra_info(padapter, psta);\n\n\t/* ToDo: HT for Ad-hoc */\n\tpsta->wireless_mode = rtw_check_network_type(psta->bssrateset, psta->bssratelen, pmlmeext->cur_channel);\n\trtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);\n\n\t/* rate radaptive */\n\tUpdate_RA_Entry(padapter, psta);\n}\n\nvoid mlmeext_sta_del_event_callback(_adapter *padapter)\n{\n\tif (is_client_associated_to_ap(padapter) || is_IBSS_empty(padapter))\n\t\trtw_mlmeext_disconnect(padapter);\n}\n\n/****************************************************************************\n\nFollowing are the functions for the timer handlers\n\n*****************************************************************************/\nvoid _linked_info_dump(_adapter *padapter)\n{\n\tif (padapter->bLinkInfoDump) {\n\t\trtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, RTW_DBGDUMP);\n\t\trtw_hal_set_odm_var(padapter, HAL_ODM_RX_INFO_DUMP, RTW_DBGDUMP, _FALSE);\n\t}\n}\n/********************************************************************\n\nWhen station does not receive any packet in MAX_CONTINUAL_NORXPACKET_COUNT*2 seconds,\nrecipient station will teardown the block ack by issuing DELBA frame.\n\n*********************************************************************/\nvoid rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer)\n{\n\tint\ti = 0;\n\tint ret = _SUCCESS;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\t/*\n\t\tIOT issue,occur Broadcom ap(Buffalo WZR-D1800H,Netgear R6300).\n\t\tAP is originator.AP does not transmit unicast packets when STA response its BAR.\n\t\tThis case probably occur ap issue BAR after AP builds BA.\n\n\t\tFollow 802.11 spec, STA shall maintain an inactivity timer for every negotiated Block Ack setup.\n\t\tThe inactivity timer is not reset when MPDUs corresponding to other TIDs are received.\n\t*/\n\tif (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) {\n\t\tfor (i = 0; i < TID_NUM ; i++) {\n\t\t\tif ((psta->recvreorder_ctrl[i].enable) && \n                        (sta_rx_data_qos_pkts(psta, i) == sta_last_rx_data_qos_pkts(psta, i)) ) {\t\t\t\n\t\t\t\t\tif (_TRUE == rtw_inc_and_chk_continual_no_rx_packet(psta, i)) {\t\t\t\t\t\n\t\t\t\t\t\t/* send a DELBA frame to the peer STA with the Reason Code field set to TIMEOUT */\n\t\t\t\t\t\tif (!from_timer)\n\t\t\t\t\t\t\tret = issue_del_ba_ex(padapter, psta->cmn.mac_addr, i, 39, 0, 3, 1);\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tissue_del_ba(padapter,  psta->cmn.mac_addr, i, 39, 0);\n\t\t\t\t\t\tpsta->recvreorder_ctrl[i].enable = _FALSE;\n\t\t\t\t\t\tif (ret != _FAIL)\n\t\t\t\t\t\t\tpsta->recvreorder_ctrl[i].ampdu_size = RX_AMPDU_SIZE_INVALID;\n\t\t\t\t\t\trtw_reset_continual_no_rx_packet(psta, i);\n\t\t\t\t\t}\t\t\t\t\n\t\t\t} else {\n\t\t\t\t/* The inactivity timer is reset when MPDUs to the TID is received. */\n\t\t\t\trtw_reset_continual_no_rx_packet(psta, i);\n\t\t\t}\n\t\t}\n\t}\n}\n\nu8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta)\n{\n\tu8 ret = _FALSE;\n#ifdef DBG_EXPIRATION_CHK\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tRTW_INFO(FUNC_ADPT_FMT\" rx:\"STA_PKTS_FMT\", beacon:%llu, probersp_to_self:%llu\"\n\t\t/*\", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u\"*/\n\t\t \", retry:%u\\n\"\n\t\t , FUNC_ADPT_ARG(padapter)\n\t\t , STA_RX_PKTS_DIFF_ARG(psta)\n\t\t, psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts\n\t\t, psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts\n\t\t/*, psta->sta_stats.rx_probersp_bm_pkts - psta->sta_stats.last_rx_probersp_bm_pkts\n\t\t, psta->sta_stats.rx_probersp_uo_pkts - psta->sta_stats.last_rx_probersp_uo_pkts\n\t\t, psta->sta_stats.rx_probereq_pkts - psta->sta_stats.last_rx_probereq_pkts\n\t\t , pmlmeinfo->bcn_interval*/\n\t\t , pmlmeext->retry\n\t\t);\n\n\tRTW_INFO(FUNC_ADPT_FMT\" tx_pkts:%llu, link_count:%u\\n\", FUNC_ADPT_ARG(padapter)\n\t\t , sta_tx_pkts(psta)\n\t\t , pmlmeinfo->link_count\n\t\t);\n#endif\n\n\tif ((sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta))\n\t    && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta)\n\t    && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta)\n\t   )\n\t\tret = _FALSE;\n\telse\n\t\tret = _TRUE;\n\n\tsta_update_last_rx_pkts(psta);\n\n\treturn ret;\n}\n\nu8 chk_adhoc_peer_is_alive(struct sta_info *psta)\n{\n\tu8 ret = _TRUE;\n\n#ifdef DBG_EXPIRATION_CHK\n\tRTW_INFO(\"sta:\"MAC_FMT\", rssi:%d, rx:\"STA_PKTS_FMT\", beacon:%llu, probersp_to_self:%llu\"\n\t\t/*\", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u\"*/\n\t\t \", expire_to:%u\\n\"\n\t\t , MAC_ARG(psta->cmn.mac_addr)\n\t\t , psta->cmn.rssi_stat.rssi\n\t\t , STA_RX_PKTS_DIFF_ARG(psta)\n\t\t, psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts\n\t\t, psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts\n\t\t/*, psta->sta_stats.rx_probersp_bm_pkts - psta->sta_stats.last_rx_probersp_bm_pkts\n\t\t, psta->sta_stats.rx_probersp_uo_pkts - psta->sta_stats.last_rx_probersp_uo_pkts\n\t\t, psta->sta_stats.rx_probereq_pkts - psta->sta_stats.last_rx_probereq_pkts\n\t\t , pmlmeinfo->bcn_interval*/\n\t\t , psta->expire_to\n\t\t);\n#endif\n\n\tif (sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta)\n\t    && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta)\n\t    && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta))\n\t\tret = _FALSE;\n\n\tsta_update_last_rx_pkts(psta);\n\n\treturn ret;\n}\n\n#ifdef CONFIG_TDLS\nu8 chk_tdls_peer_sta_is_alive(_adapter *padapter, struct sta_info *psta)\n{\n\tif ((psta->sta_stats.rx_data_pkts == psta->sta_stats.last_rx_data_pkts)\n\t    && (psta->sta_stats.rx_tdls_disc_rsp_pkts == psta->sta_stats.last_rx_tdls_disc_rsp_pkts))\n\t\treturn _FALSE;\n\n\treturn _TRUE;\n}\n\nvoid linked_status_chk_tdls(_adapter *padapter)\n{\n\tstruct candidate_pool {\n\t\tstruct sta_info *psta;\n\t\tu8 addr[ETH_ALEN];\n\t};\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\t_irqL irqL;\n\tu8 ack_chk;\n\tstruct sta_info *psta;\n\tint i, num_teardown = 0, num_checkalive = 0;\n\t_list\t*plist, *phead;\n\tstruct tdls_txmgmt txmgmt;\n\tstruct candidate_pool checkalive[MAX_ALLOWED_TDLS_STA_NUM];\n\tstruct candidate_pool teardown[MAX_ALLOWED_TDLS_STA_NUM];\n\tu8 tdls_sta_max = _FALSE;\n\n#define ALIVE_MIN 2\n#define ALIVE_MAX 5\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\t_rtw_memset(checkalive, 0x00, sizeof(checkalive));\n\t_rtw_memset(teardown, 0x00, sizeof(teardown));\n\n\tif ((padapter->tdlsinfo.link_established == _TRUE)) {\n\t\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\t\tfor (i = 0; i < NUM_STA; i++) {\n\t\t\tphead = &(pstapriv->sta_hash[i]);\n\t\t\tplist = get_next(phead);\n\n\t\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\t\t\t\tplist = get_next(plist);\n\n\t\t\t\tif (psta->tdls_sta_state & TDLS_LINKED_STATE) {\n\t\t\t\t\tpsta->alive_count++;\n\t\t\t\t\tif (psta->alive_count >= ALIVE_MIN) {\n\t\t\t\t\t\tif (chk_tdls_peer_sta_is_alive(padapter, psta) == _FALSE) {\n\t\t\t\t\t\t\tif (psta->alive_count < ALIVE_MAX) {\n\t\t\t\t\t\t\t\t_rtw_memcpy(checkalive[num_checkalive].addr, psta->cmn.mac_addr, ETH_ALEN);\n\t\t\t\t\t\t\t\tcheckalive[num_checkalive].psta = psta;\n\t\t\t\t\t\t\t\tnum_checkalive++;\n\t\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t\t_rtw_memcpy(teardown[num_teardown].addr, psta->cmn.mac_addr, ETH_ALEN);\n\t\t\t\t\t\t\t\tteardown[num_teardown].psta = psta;\n\t\t\t\t\t\t\t\tnum_teardown++;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t} else\n\t\t\t\t\t\t\tpsta->alive_count = 0;\n\t\t\t\t\t}\n\t\t\t\t\tpsta->sta_stats.last_rx_data_pkts = psta->sta_stats.rx_data_pkts;\n\t\t\t\t\tpsta->sta_stats.last_rx_tdls_disc_rsp_pkts = psta->sta_stats.rx_tdls_disc_rsp_pkts;\n\n\t\t\t\t\tif ((num_checkalive >= MAX_ALLOWED_TDLS_STA_NUM) || (num_teardown >= MAX_ALLOWED_TDLS_STA_NUM)) {\n\t\t\t\t\t\ttdls_sta_max = _TRUE;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (tdls_sta_max == _TRUE)\n\t\t\t\tbreak;\n\t\t}\n\t\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\t\tif (num_checkalive > 0) {\n\t\t\tfor (i = 0; i < num_checkalive; i++) {\n\t\t\t\t_rtw_memcpy(txmgmt.peer, checkalive[i].addr, ETH_ALEN);\n\t\t\t\tissue_tdls_dis_req(padapter, &txmgmt);\n\t\t\t\tissue_tdls_dis_req(padapter, &txmgmt);\n\t\t\t\tissue_tdls_dis_req(padapter, &txmgmt);\n\t\t\t}\n\t\t}\n\n\t\tif (num_teardown > 0) {\n\t\t\tfor (i = 0; i < num_teardown; i++) {\n\t\t\t\tRTW_INFO(\"[%s %d] Send teardown to \"MAC_FMT\"\\n\", __FUNCTION__, __LINE__, MAC_ARG(teardown[i].addr));\n\t\t\t\ttxmgmt.status_code = _RSON_TDLS_TEAR_TOOFAR_;\n\t\t\t\t_rtw_memcpy(txmgmt.peer, teardown[i].addr, ETH_ALEN);\n\t\t\t\tissue_tdls_teardown(padapter, &txmgmt, _FALSE);\n\t\t\t}\n\t\t}\n\t}\n\n}\n#endif /* CONFIG_TDLS */\n\ninline int rtw_get_rx_chk_limit(_adapter *adapter)\n{\n\treturn adapter->stapriv.rx_chk_limit;\n}\n\ninline void rtw_set_rx_chk_limit(_adapter *adapter, int limit)\n{\n\tadapter->stapriv.rx_chk_limit = limit;\n}\n\n/* from_timer == 1 means driver is in LPS */\nvoid linked_status_chk(_adapter *padapter, u8 from_timer)\n{\n\tu32\ti;\n\tstruct sta_info\t\t*psta;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct sta_priv\t\t*pstapriv = &padapter->stapriv;\n#if defined(CONFIG_ARP_KEEP_ALIVE) || defined(CONFIG_LAYER2_ROAMING)\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n#endif\n#ifdef CONFIG_LAYER2_ROAMING\n\tstruct recv_priv\t*precvpriv = &padapter->recvpriv;\n#endif\n\n\tif (padapter->registrypriv.mp_mode == _TRUE)\n\t\treturn;\n\n\tif (is_client_associated_to_ap(padapter)) {\n\t\t/* linked infrastructure client mode */\n\n\t\tint tx_chk = _SUCCESS, rx_chk = _SUCCESS;\n\t\tint rx_chk_limit;\n\t\tint link_count_limit;\n\n#if defined(CONFIG_RTW_REPEATER_SON)\n\trtw_rson_scan_wk_cmd(padapter, RSON_SCAN_PROCESS);\n#elif defined(CONFIG_LAYER2_ROAMING)\n\t\tif (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) {\n\t\t\tRTW_INFO(\"signal_strength_data.avg_val = %d\\n\", precvpriv->signal_strength_data.avg_val);\n\t\t\tif ((precvpriv->signal_strength_data.avg_val < pmlmepriv->roam_rssi_threshold)\n\t\t\t\t&& (rtw_get_passing_time_ms(pmlmepriv->last_roaming) >= pmlmepriv->roam_scan_int*2000)) {\n#ifdef CONFIG_RTW_80211K\n\t\t\t\trtw_roam_nb_discover(padapter, _FALSE);\n#endif\n\t\t\t\tpmlmepriv->need_to_roam = _TRUE;\n\t\t\t\trtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM);\n\t\t\t\tpmlmepriv->last_roaming = rtw_get_current_time();\n\t\t\t} else\n\t\t\t\tpmlmepriv->need_to_roam = _FALSE;\n\t\t}\n#endif\n#ifdef CONFIG_MCC_MODE\n\t\t/*\n\t\t * due to tx ps null date to ao, so ap doest not tx pkt to driver\n\t\t * we may check chk_ap_is_alive fail, and may issue_probereq to wrong channel under sitesurvey\n\t\t * don't keep alive check under MCC\n\t\t */\n\t\tif (rtw_hal_mcc_link_status_chk(padapter, __func__) == _FALSE)\n\t\t\treturn;\n#endif\n\n\t\trx_chk_limit = rtw_get_rx_chk_limit(padapter);\n\n#ifdef CONFIG_ARP_KEEP_ALIVE\n\t\tif (!from_timer && pmlmepriv->bGetGateway == 1 && pmlmepriv->GetGatewayTryCnt < 3) {\n\t\t\tRTW_INFO(\"do rtw_gw_addr_query() : %d\\n\", pmlmepriv->GetGatewayTryCnt);\n\t\t\tpmlmepriv->GetGatewayTryCnt++;\n\t\t\tif (rtw_gw_addr_query(padapter) == 0)\n\t\t\t\tpmlmepriv->bGetGateway = 0;\n\t\t\telse {\n\t\t\t\t_rtw_memset(pmlmepriv->gw_ip, 0, 4);\n\t\t\t\t_rtw_memset(pmlmepriv->gw_mac_addr, 0, ETH_ALEN);\n\t\t\t}\n\t\t}\n#endif\n#ifdef CONFIG_P2P\n\t\tif (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) {\n\t\t\tif (!from_timer)\n\t\t\t\tlink_count_limit = 3; /* 8 sec */\n\t\t\telse\n\t\t\t\tlink_count_limit = 15; /* 32 sec */\n\t\t} else\n#endif /* CONFIG_P2P */\n\t\t{\n\t\t\tif (!from_timer)\n\t\t\t\tlink_count_limit = 7; /* 16 sec */\n\t\t\telse\n\t\t\t\tlink_count_limit = 29; /* 60 sec */\n\t\t}\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\n\t\tif (ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on) == _TRUE)\n\t\t\treturn;\n#endif /* CONFIG_TDLS_CH_SW */\n\n#ifdef CONFIG_TDLS_AUTOCHECKALIVE\n\t\tlinked_status_chk_tdls(padapter);\n#endif /* CONFIG_TDLS_AUTOCHECKALIVE */\n#endif /* CONFIG_TDLS */\n\n\t\tpsta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);\n\t\tif (psta != NULL) {\n\t\t\tbool is_p2p_enable = _FALSE;\n#ifdef CONFIG_P2P\n\t\t\tis_p2p_enable = !rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE);\n#endif\n\n#ifdef CONFIG_ISSUE_DELBA_WHEN_NO_TRAFFIC \n\t\t\t/*issue delba when ap does not tx data packet that is Broadcom ap */\n\t\t\trtw_delba_check(padapter, psta, from_timer);\n#endif\n\t\t\tif (chk_ap_is_alive(padapter, psta) == _FALSE)\n\t\t\t\trx_chk = _FAIL;\n\n\t\t\tif (sta_last_tx_pkts(psta) == sta_tx_pkts(psta))\n\t\t\t\ttx_chk = _FAIL;\n\n#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK\n\t\t\tif (!from_timer && pmlmeext->active_keep_alive_check && (rx_chk == _FAIL || tx_chk == _FAIL)\n\t\t\t) {\n\t\t\t\tu8 backup_ch = 0, backup_bw = 0, backup_offset = 0;\n\t\t\t\tu8 union_ch = 0, union_bw = 0, union_offset = 0;\n\t\t\t\tu8 switch_channel_by_drv = _TRUE;\n\n\t\t\t\t\n#ifdef CONFIG_MCC_MODE\n\t\t\t\tif (MCC_EN(padapter)) {\n\t\t\t\t\t/* driver doesn't switch channel under MCC */\n\t\t\t\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))\n\t\t\t\t\t\tswitch_channel_by_drv = _FALSE;\n\t\t\t\t}\n#endif\n\t\t\t\tif (switch_channel_by_drv) {\n\t\t\t\t\tif (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset)\n\t\t\t\t\t\t|| pmlmeext->cur_channel != union_ch)\n\t\t\t\t\t\t\tgoto bypass_active_keep_alive;\n\n\t\t\t\t\t/* switch to correct channel of current network  before issue keep-alive frames */\n\t\t\t\t\tif (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) {\n\t\t\t\t\t\tbackup_ch = rtw_get_oper_ch(padapter);\n\t\t\t\t\t\tbackup_bw = rtw_get_oper_bw(padapter);\n\t\t\t\t\t\tbackup_offset = rtw_get_oper_choffset(padapter);\n\t\t\t\t\t\tset_channel_bwmode(padapter, union_ch, union_offset, union_bw);\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif (rx_chk != _SUCCESS)\n\t\t\t\t\tissue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, psta->cmn.mac_addr, 0, 0, 3, 1);\n\n\t\t\t\tif ((tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit) || rx_chk != _SUCCESS) {\n\t\t\t\t\tif (rtw_mi_check_fwstate(padapter, _FW_UNDER_SURVEY))\n\t\t\t\t\t\ttx_chk = issue_nulldata(padapter, psta->cmn.mac_addr, 1, 3, 1);\n\t\t\t\t\telse\n\t\t\t\t\t\ttx_chk = issue_nulldata(padapter, psta->cmn.mac_addr, 0, 3, 1);\n\t\t\t\t\t/* if tx acked and p2p disabled, set rx_chk _SUCCESS to reset retry count */\n\t\t\t\t\tif (tx_chk == _SUCCESS && !is_p2p_enable)\n\t\t\t\t\t\trx_chk = _SUCCESS;\n\t\t\t\t}\n\n\t\t\t\t/* back to the original operation channel */\n\t\t\t\tif (backup_ch > 0 && switch_channel_by_drv)\n\t\t\t\t\tset_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw);\n\nbypass_active_keep_alive:\n\t\t\t\t;\n\t\t\t} else\n#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */\n\t\t\t{\n\t\t\t\tif (rx_chk != _SUCCESS) {\n\t\t\t\t\tif (pmlmeext->retry == 0) {\n#ifdef DBG_EXPIRATION_CHK\n\t\t\t\t\t\tRTW_INFO(\"issue_probereq to trigger probersp, retry=%d\\n\", pmlmeext->retry);\n#endif\n\t\t\t\t\t\tissue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1));\n\t\t\t\t\t\tissue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1));\n\t\t\t\t\t\tissue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1));\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif (tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit\n#ifdef CONFIG_MCC_MODE\n\t\t\t\t    /* FW tx nulldata under MCC mode, we just check  ap is alive */\n\t\t\t\t    && (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC))\n#endif /* CONFIG_MCC_MODE */\n\t\t\t\t) {\n\t\t\t\t\t#ifdef DBG_EXPIRATION_CHK\n\t\t\t\t\tRTW_INFO(\"%s issue_nulldata(%d)\\n\", __FUNCTION__, from_timer ? 1 : 0);\n\t\t\t\t\t#endif\n\t\t\t\t\tif (from_timer || rtw_mi_check_fwstate(padapter, _FW_UNDER_SURVEY))\n\t\t\t\t\t\ttx_chk = issue_nulldata(padapter, NULL, 1, 0, 0);\n\t\t\t\t\telse\n\t\t\t\t\t\ttx_chk = issue_nulldata(padapter, NULL, 0, 1, 1);\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (rx_chk == _FAIL) {\n\t\t\t\tpmlmeext->retry++;\n\t\t\t\tif (pmlmeext->retry > rx_chk_limit) {\n\t\t\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" disconnect or roaming\\n\",\n\t\t\t\t\t\t  FUNC_ADPT_ARG(padapter));\n\t\t\t\t\treceive_disconnect(padapter, pmlmeinfo->network.MacAddress\n\t\t\t\t\t\t, WLAN_REASON_EXPIRATION_CHK, _FALSE);\n\t\t\t\t\treturn;\n\t\t\t\t}\n\t\t\t} else\n\t\t\t\tpmlmeext->retry = 0;\n\n\t\t\tif (tx_chk == _FAIL)\n\t\t\t\tpmlmeinfo->link_count %= (link_count_limit + 1);\n\t\t\telse {\n\t\t\t\tpsta->sta_stats.last_tx_pkts = psta->sta_stats.tx_pkts;\n\t\t\t\tpmlmeinfo->link_count = 0;\n\t\t\t}\n\n\t\t} /* end of if ((psta = rtw_get_stainfo(pstapriv, passoc_res->network.MacAddress)) != NULL) */\n\n\t} else if (is_client_associated_to_ibss(padapter)) {\n\t\t_irqL irqL;\n\t\t_list *phead, *plist, dlist;\n\n\t\t_rtw_init_listhead(&dlist);\n\n\t\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\t\tfor (i = 0; i < NUM_STA; i++) {\n\n\t\t\tphead = &(pstapriv->sta_hash[i]);\n\t\t\tplist = get_next(phead);\n\t\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\t\t\t\tplist = get_next(plist);\n\n\t\t\t\tif (is_broadcast_mac_addr(psta->cmn.mac_addr))\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (chk_adhoc_peer_is_alive(psta) || !psta->expire_to)\n\t\t\t\t\tpsta->expire_to = pstapriv->adhoc_expire_to;\n\t\t\t\telse\n\t\t\t\t\tpsta->expire_to--;\n\n\t\t\t\tif (psta->expire_to <= 0) {\n\t\t\t\t\trtw_list_delete(&psta->list);\n\t\t\t\t\trtw_list_insert_tail(&psta->list, &dlist);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\t\tplist = get_next(&dlist);\n\t\twhile (rtw_end_of_queue_search(&dlist, plist) == _FALSE) {\n\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, list);\n\t\t\tplist = get_next(plist);\n\t\t\trtw_list_delete(&psta->list);\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" ibss expire \"MAC_FMT\"\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));\n\t\t\treport_del_sta_event(padapter, psta->cmn.mac_addr, WLAN_REASON_EXPIRATION_CHK, from_timer ? _TRUE : _FALSE, _FALSE);\n\t\t}\n\t}\n\n}\n\nvoid survey_timer_hdl(void *ctx)\n{\n\t_adapter *padapter = (_adapter *)ctx;\n\tstruct cmd_obj *cmd;\n\tstruct sitesurvey_parm *psurveyPara;\n\tstruct cmd_priv *pcmdpriv = &padapter->cmdpriv;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\n\tif (mlmeext_scan_state(pmlmeext) > SCAN_DISABLE) {\n\t\tcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\t\tif (cmd == NULL) {\n\t\t\trtw_warn_on(1);\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpsurveyPara = (struct sitesurvey_parm *)rtw_zmalloc(sizeof(struct sitesurvey_parm));\n\t\tif (psurveyPara == NULL) {\n\t\t\trtw_warn_on(1);\n\t\t\trtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj));\n\t\t\tgoto exit;\n\t\t}\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(cmd, psurveyPara, GEN_CMD_CODE(_SiteSurvey));\n\t\trtw_enqueue_cmd(pcmdpriv, cmd);\n\t}\n\nexit:\n\treturn;\n}\n\n#ifdef CONFIG_RTW_REPEATER_SON\n/*\t 100ms pass, stop rson_scan\t*/\nvoid rson_timer_hdl(void *ctx)\n{\n\t_adapter *padapter = (_adapter *)ctx;\n\n\trtw_rson_scan_wk_cmd(padapter, RSON_SCAN_DISABLE);\n}\n\n#endif\n\nvoid link_timer_hdl(void *ctx)\n{\n\t_adapter *padapter = (_adapter *)ctx;\n\t/* static unsigned int\t\trx_pkt = 0; */\n\t/* static u64\t\t\t\ttx_cnt = 0; */\n\t/* struct xmit_priv\t\t*pxmitpriv = &(padapter->xmitpriv); */\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\t/* struct sta_priv\t\t*pstapriv = &padapter->stapriv; */\n#ifdef CONFIG_RTW_80211R\n\tstruct\tsta_priv\t\t*pstapriv = &padapter->stapriv;\n\tstruct\tsta_info\t\t*psta = NULL;\n\tWLAN_BSSID_EX\t\t*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));\n#endif\n\n\tif (rtw_sta_linking_test_force_fail())\n\t\tRTW_INFO(\"rtw_sta_linking_test_force_fail\\n\");\n\n\tif (pmlmeext->join_abort && pmlmeinfo->state != WIFI_FW_NULL_STATE) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" join abort\\n\", FUNC_ADPT_ARG(padapter));\n\t\tpmlmeinfo->state = WIFI_FW_NULL_STATE;\n\t\treport_join_res(padapter, -4, WLAN_STATUS_UNSPECIFIED_FAILURE);\n\t\tgoto exit;\n\t}\n\n\tif (pmlmeinfo->state & WIFI_FW_AUTH_NULL) {\n\t\tRTW_INFO(\"link_timer_hdl:no beacon while connecting\\n\");\n\t\tpmlmeinfo->state = WIFI_FW_NULL_STATE;\n\t\treport_join_res(padapter, -3, WLAN_STATUS_UNSPECIFIED_FAILURE);\n\t} else if (pmlmeinfo->state & WIFI_FW_AUTH_STATE) {\n\n#ifdef CONFIG_IOCTL_CFG80211\n\t\tif (rtw_sec_chk_auth_type(padapter, NL80211_AUTHTYPE_SAE))\n\t\t\treturn;\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n\t\t/* re-auth timer */\n\t\tif (++pmlmeinfo->reauth_count > REAUTH_LIMIT) {\n\t\t\t/* if (pmlmeinfo->auth_algo != dot11AuthAlgrthm_Auto) */\n\t\t\t/* { */\n\t\t\tpmlmeinfo->state = 0;\n\t\t\tif (pmlmeinfo->auth_status) {\n\t\t\t\treport_join_res(padapter, -1, pmlmeinfo->auth_status);\n\t\t\t\tpmlmeinfo->auth_status = 0; /* reset */\n\t\t\t} else\n\t\t\t\treport_join_res(padapter, -1, WLAN_STATUS_UNSPECIFIED_FAILURE);\n\t\t\treturn;\n\t\t\t/* } */\n\t\t\t/* else */\n\t\t\t/* { */\n\t\t\t/*\tpmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared; */\n\t\t\t/*\tpmlmeinfo->reauth_count = 0; */\n\t\t\t/* } */\n\t\t}\n\n\t\tRTW_INFO(\"link_timer_hdl: auth timeout and try again\\n\");\n\t\tpmlmeinfo->auth_seq = 1;\n\t\tissue_auth(padapter, NULL, 0);\n\t\tset_link_timer(pmlmeext, REAUTH_TO);\n\t} else if (pmlmeinfo->state & WIFI_FW_ASSOC_STATE) {\n\t\t/* re-assoc timer */\n\t\tif (++pmlmeinfo->reassoc_count > REASSOC_LIMIT) {\n\t\t\tpmlmeinfo->state = WIFI_FW_NULL_STATE;\n#ifdef CONFIG_RTW_80211R\n\t\t\tif (rtw_ft_roam(padapter)) {\n\t\t\t\tpsta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);\n\t\t\t\tif (psta)\n\t\t\t\t\trtw_free_stainfo(padapter,  psta);\n\t\t\t}\n#endif\n\t\t\treport_join_res(padapter, -2, WLAN_STATUS_UNSPECIFIED_FAILURE);\n\t\t\treturn;\n\t\t}\n\n#ifdef CONFIG_RTW_80211R\n\t\tif (rtw_ft_roam(padapter)) {\n\t\t\tRTW_INFO(\"link_timer_hdl: reassoc timeout and try again\\n\");\n\t\t\tissue_reassocreq(padapter);\n\t\t} else\n#endif\n\t\t{\n\t\t\tRTW_INFO(\"link_timer_hdl: assoc timeout and try again\\n\");\n\t\t\tissue_assocreq(padapter);\n\t\t}\n\n\t\tset_link_timer(pmlmeext, REASSOC_TO);\n\t}\n\nexit:\n\treturn;\n}\n\nvoid addba_timer_hdl(void *ctx)\n{\n\tstruct sta_info *psta = (struct sta_info *)ctx;\n\n#ifdef CONFIG_80211N_HT\n\tstruct ht_priv\t*phtpriv;\n\n\tif (!psta)\n\t\treturn;\n\n\tphtpriv = &psta->htpriv;\n\n\tif ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) {\n\t\tif (phtpriv->candidate_tid_bitmap)\n\t\t\tphtpriv->candidate_tid_bitmap = 0x0;\n\n\t}\n#endif /* CONFIG_80211N_HT */\n}\n\n#ifdef CONFIG_IEEE80211W\nvoid report_sta_timeout_event(_adapter *padapter, u8 *MacAddr, unsigned short reason)\n{\n\tstruct cmd_obj *pcmd_obj;\n\tu8\t*pevtcmd;\n\tu32 cmdsz;\n\tstruct sta_info *psta;\n\tint\tmac_id;\n\tstruct stadel_event\t\t\t*pdel_sta_evt;\n\tstruct C2HEvent_Header\t*pc2h_evt_hdr;\n\tstruct mlme_ext_priv\t\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct cmd_priv *pcmdpriv = &padapter->cmdpriv;\n\n\tpcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (pcmd_obj == NULL)\n\t\treturn;\n\n\tcmdsz = (sizeof(struct stadel_event) + sizeof(struct C2HEvent_Header));\n\tpevtcmd = (u8 *)rtw_zmalloc(cmdsz);\n\tif (pevtcmd == NULL) {\n\t\trtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));\n\t\treturn;\n\t}\n\n\t_rtw_init_listhead(&pcmd_obj->list);\n\n\tpcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);\n\tpcmd_obj->cmdsz = cmdsz;\n\tpcmd_obj->parmbuf = pevtcmd;\n\n\tpcmd_obj->rsp = NULL;\n\tpcmd_obj->rspsz  = 0;\n\n\tpc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd);\n\tpc2h_evt_hdr->len = sizeof(struct stadel_event);\n\tpc2h_evt_hdr->ID = GEN_EVT_CODE(_TimeoutSTA);\n\tpc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);\n\n\tpdel_sta_evt = (struct stadel_event *)(pevtcmd + sizeof(struct C2HEvent_Header));\n\t_rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN);\n\t_rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd), (unsigned char *)(&reason), 2);\n\n\n\tpsta = rtw_get_stainfo(&padapter->stapriv, MacAddr);\n\tif (psta)\n\t\tmac_id = (int)psta->cmn.mac_id;\n\telse\n\t\tmac_id = (-1);\n\n\tpdel_sta_evt->mac_id = mac_id;\n\n\tRTW_INFO(\"report_del_sta_event: delete STA, mac_id=%d\\n\", mac_id);\n\n\trtw_enqueue_cmd(pcmdpriv, pcmd_obj);\n\n\treturn;\n}\n\nvoid clnt_sa_query_timeout(_adapter *padapter)\n{\n\tstruct mlme_ext_priv *mlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info);\n\n\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n\treceive_disconnect(padapter, get_my_bssid(&(mlmeinfo->network)), WLAN_REASON_SA_QUERY_TIMEOUT, _FALSE);\n}\n\nvoid sa_query_timer_hdl(void *ctx)\n{\n\tstruct sta_info *psta = (struct sta_info *)ctx;\n\t_adapter *padapter = psta->padapter;\n\t_irqL irqL;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE &&\n\t    check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\tclnt_sa_query_timeout(padapter);\n\telse if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)\n\t\treport_sta_timeout_event(padapter, psta->cmn.mac_addr, WLAN_REASON_PREV_AUTH_NOT_VALID);\n}\n\n#endif /* CONFIG_IEEE80211W */\n\n#ifdef CONFIG_RTW_80211R\nvoid rtw_ft_update_bcn(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tuint len = precv_frame->u.hdr.len;\n\tWLAN_BSSID_EX *pbss;\n\n\tif (rtw_ft_chk_status(padapter,RTW_FT_ASSOCIATED_STA) \n\t\t&& (pmlmepriv->ft_roam.ft_updated_bcn == _FALSE)) {\n\t\tpbss = (WLAN_BSSID_EX*)rtw_malloc(sizeof(WLAN_BSSID_EX));\n\t\tif (pbss) {\n\t\t\tif (collect_bss_info(padapter, precv_frame, pbss) == _SUCCESS) {\n\t\t\t\tstruct beacon_keys recv_beacon;\n\n\t\t\t\tupdate_network(&(pmlmepriv->cur_network.network), pbss, padapter, _TRUE);\n\t\t\t\t\n\t\t\t\t/* update bcn keys */\n\t\t\t\tif (rtw_get_bcn_keys(padapter, pframe, len, &recv_beacon) == _TRUE) {\n\t\t\t\t\tRTW_INFO(\"%s: beacon keys ready\\n\", __func__);\n\t\t\t\t\t_rtw_memcpy(&pmlmepriv->cur_beacon_keys,\n\t\t\t\t\t\t&recv_beacon, sizeof(recv_beacon));\n\t\t\t\t\tif (is_hidden_ssid(recv_beacon.ssid, recv_beacon.ssid_len)) {\n\t\t\t\t\t\t_rtw_memcpy(pmlmepriv->cur_beacon_keys.ssid, pmlmeinfo->network.Ssid.Ssid, IW_ESSID_MAX_SIZE);\n\t\t\t\t\t\tpmlmepriv->cur_beacon_keys.ssid_len = pmlmeinfo->network.Ssid.SsidLength;\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tRTW_ERR(\"%s: get beacon keys failed\\n\", __func__);\n\t\t\t\t\t_rtw_memset(&pmlmepriv->cur_beacon_keys, 0, sizeof(recv_beacon));\n\t\t\t\t}\n\t\t\t\t#ifdef CONFIG_BCN_CNT_CONFIRM_HDL\n\t\t\t\tpmlmepriv->new_beacon_cnts = 0;\n\t\t\t\t#endif\n\t\t\t}\n\t\t\trtw_mfree((u8*)pbss, sizeof(WLAN_BSSID_EX));\n\t\t}\n\n\t\t/* check the vendor of the assoc AP */\n\t\tpmlmeinfo->assoc_AP_vendor = \t\n\t\t\tcheck_assoc_AP(pframe+sizeof(struct rtw_ieee80211_hdr_3addr),\n\t\t\t\t(len - sizeof(struct rtw_ieee80211_hdr_3addr)));\n\n\t\t/* update TSF Value */\n\t\tupdate_TSF(pmlmeext, pframe, len);\n\t\tpmlmeext->bcn_cnt = 0;\n\t\tpmlmeext->last_bcn_cnt = 0;\n\t\tpmlmepriv->ft_roam.ft_updated_bcn = _TRUE;\n\t}\n}\n\nvoid rtw_ft_start_clnt_join(_adapter *padapter)\n{\n\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct\tmlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);\n\n\tif (rtw_ft_otd_roam(padapter)) {\n\t\tpmlmeinfo->state = WIFI_FW_AUTH_SUCCESS | WIFI_FW_STATION_STATE;\n\t\tpft_roam->ft_event.ies =\n\t\t\t(pft_roam->ft_action + sizeof(struct rtw_ieee80211_hdr_3addr) + 16);\n\t\tpft_roam->ft_event.ies_len =\n\t\t\t(pft_roam->ft_action_len - sizeof(struct rtw_ieee80211_hdr_3addr));\n\n\t\t/*Not support RIC*/\n\t\tpft_roam->ft_event.ric_ies =  NULL;\n\t\tpft_roam->ft_event.ric_ies_len = 0;\n\t\trtw_ft_report_evt(padapter);\n\t\treturn;\n\t}\n\n\tpmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE;\n\tstart_clnt_auth(padapter);\n}\n\nu8 rtw_ft_update_rsnie(\n\t_adapter *padapter, u8 bwrite, \n\tstruct pkt_attrib *pattrib, u8 **pframe)\n{\n\tstruct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);\n\tu8 *pie;\n\tu32 len;\n\n\tpie = rtw_get_ie(pft_roam->updated_ft_ies, EID_WPA2, &len, \n\t\t\tpft_roam->updated_ft_ies_len);\n\n\tif (!bwrite)\n\t\treturn (pie)?_SUCCESS:_FAIL;\n\t\n\tif (pie) {\n\t\t*pframe = rtw_set_ie(((u8 *)*pframe), EID_WPA2, len, \n\t\t\t\t\t\tpie+2, &(pattrib->pktlen));\n\t} else\n\t\treturn _FAIL;\n\n\treturn _SUCCESS;\t\n}\n\nstatic u8 rtw_ft_update_mdie(\n\t_adapter *padapter, struct pkt_attrib *pattrib, u8 **pframe)\n{\n\tstruct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);\n\tu8 *pie, mdie[3];\n\tu32 len = 3;\n\n\tif (rtw_ft_roam(padapter)) {\n\t\tif ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _MDIE_, \n\t\t\t\t&len, pft_roam->updated_ft_ies_len))) {\n\t\t\tpie = (pie + 2); /* ignore md-id & length */\n\t\t} else \n\t\t\treturn _FAIL;\n\t} else {\n\t\t*((u16 *)&mdie[0]) = pft_roam->mdid;\n\t\tmdie[2] = pft_roam->ft_cap;\n\t\tpie = &mdie[0];\n\t}\n\n\t*pframe = rtw_set_ie(((u8 *)*pframe), _MDIE_, len , pie, &(pattrib->pktlen));\n\treturn _SUCCESS;\t\n}\n\nstatic u8 rtw_ft_update_ftie(\n\t_adapter *padapter, struct pkt_attrib *pattrib, u8 **pframe)\n{\n\tstruct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);\n\tu8 *pie;\n\tu32 len;\n\n\tif ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _FTIE_, &len, \n\t\t\t\tpft_roam->updated_ft_ies_len)) != NULL) {\n\t\t*pframe = rtw_set_ie(*pframe, _FTIE_, len , \n\t\t\t\t\t(pie+2), &(pattrib->pktlen));\n\t} else\n\t\treturn _FAIL;\n\n\treturn _SUCCESS;\t\n}\n\nvoid rtw_ft_build_auth_req_ies(_adapter *padapter, \n\tstruct pkt_attrib *pattrib, u8 **pframe)\n{\n\tu8 ftie_append = _TRUE;\n\n\tif (!pattrib || !(*pframe))\n\t\treturn;\n\n\tif (!rtw_ft_roam(padapter))\n\t\treturn;\n\n\tftie_append = rtw_ft_update_rsnie(padapter, _TRUE, pattrib, pframe);\n\trtw_ft_update_mdie(padapter, pattrib, pframe);\n\tif (ftie_append)\n\t\trtw_ft_update_ftie(padapter, pattrib, pframe);\n}\n\nvoid rtw_ft_build_assoc_req_ies(_adapter *padapter, \n\tu8 is_reassoc, struct pkt_attrib *pattrib, u8 **pframe)\n{\n\tif (!pattrib || !(*pframe))\n\t\treturn;\n\n\tif (rtw_ft_chk_flags(padapter, RTW_FT_PEER_EN))\n\t\trtw_ft_update_mdie(padapter, pattrib, pframe);\n\n\tif ((!is_reassoc) || (!rtw_ft_roam(padapter)))\n\t\treturn;\n\n\tif (rtw_ft_update_rsnie(padapter, _FALSE, pattrib, pframe))\n\t\trtw_ft_update_ftie(padapter, pattrib, pframe);\t\n}\n\nu8 rtw_ft_update_auth_rsp_ies(_adapter *padapter, u8 *pframe, u32 len)\n{\n\tu8 ret = _SUCCESS;\n\tu8 target_ap_addr[ETH_ALEN] = {0};\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);\n\n\tif (!rtw_ft_roam(padapter))\n\t\treturn _FAIL;\n\n\t/*rtw_ft_report_reassoc_evt already,\n\t * and waiting for cfg80211_rtw_update_ft_ies */\n\tif (rtw_ft_authed_sta(padapter))\n\t\treturn ret;\n\n\tif (!pframe || !len)\n\t\treturn _FAIL;\n\t\n\trtw_buf_update(&pmlmepriv->auth_rsp, \n\t\t&pmlmepriv->auth_rsp_len, pframe, len);\n\tpft_roam->ft_event.ies =\n\t\t(pmlmepriv->auth_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6);\n\tpft_roam->ft_event.ies_len =\n\t\t(pmlmepriv->auth_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6);\n\n\t/*Not support RIC*/\n\tpft_roam->ft_event.ric_ies =  NULL;\n\tpft_roam->ft_event.ric_ies_len =  0;\n\t_rtw_memcpy(target_ap_addr, pmlmepriv->assoc_bssid, ETH_ALEN);\n\trtw_ft_report_reassoc_evt(padapter, target_ap_addr);\n\n\treturn ret;\t\n}\n\nstatic void rtw_ft_start_clnt_action(_adapter *padapter, u8 *pTargetAddr)\n{\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\n\trtw_ft_set_status(padapter, RTW_FT_REQUESTING_STA);\n\trtw_ft_issue_action_req(padapter, pTargetAddr);\n\t_set_timer(&pmlmeext->ft_link_timer, REASSOC_TO);\n}\n\nvoid rtw_ft_start_roam(_adapter *padapter, u8 *pTargetAddr)\n{\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\n\tif (rtw_ft_otd_roam(padapter)) {\n\t\trtw_ft_start_clnt_action(padapter, pTargetAddr);\n\t} else {\n\t\t/*wait a little time to retrieve packets buffered in the current ap while scan*/\n\t\t_set_timer(&pmlmeext->ft_roam_timer, 30);\n\t}\n}\n\nvoid rtw_ft_issue_action_req(_adapter *padapter, u8 *pTargetAddr)\n{\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct xmit_priv *pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct xmit_frame *pmgntframe;\n\tstruct rtw_ieee80211_hdr *pwlanhdr;\n\tstruct pkt_attrib *pattrib;\n\tu8 *pframe;\n\tu8 category = RTW_WLAN_CATEGORY_FT;\n\tu8 action = RTW_WLAN_ACTION_FT_REQ;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn;\n\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\tpwlanhdr->frame_ctl = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));\n\n\t_rtw_memcpy(pframe, adapter_mac_addr(padapter), ETH_ALEN);\n\tpframe += ETH_ALEN;\n\tpattrib->pktlen += ETH_ALEN;\n\n\t_rtw_memcpy(pframe, pTargetAddr, ETH_ALEN);\n\tpframe += ETH_ALEN;\n\tpattrib->pktlen += ETH_ALEN;\n\n\trtw_ft_update_mdie(padapter, pattrib, &pframe);\n\tif (rtw_ft_update_rsnie(padapter, _TRUE, pattrib, &pframe))\n\t\trtw_ft_update_ftie(padapter, pattrib, &pframe);\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\tdump_mgntframe(padapter, pmgntframe);\n}\n\nvoid rtw_ft_report_evt(_adapter *padapter)\n{\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);\n\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&(pmlmeinfo->network);\n\tstruct cfg80211_ft_event_params ft_evt_parms;\n\t_irqL irqL;\n\n\t_rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms));\n\trtw_ft_update_stainfo(padapter, pnetwork);\n\n\tif (!pnetwork)\n\t\tgoto err_2;\n\n\tft_evt_parms.ies_len = pft_roam->ft_event.ies_len;\n\tft_evt_parms.ies =  rtw_zmalloc(ft_evt_parms.ies_len);\n\tif (ft_evt_parms.ies)\n\t\t_rtw_memcpy((void *)ft_evt_parms.ies, pft_roam->ft_event.ies, ft_evt_parms.ies_len);\n\t else\n\t\tgoto err_2;\n\n\tft_evt_parms.target_ap = rtw_zmalloc(ETH_ALEN);\n\tif (ft_evt_parms.target_ap)\n\t\t_rtw_memcpy((void *)ft_evt_parms.target_ap, pnetwork->MacAddress, ETH_ALEN);\n\telse\n\t\tgoto err_1;\n\n\tft_evt_parms.ric_ies = pft_roam->ft_event.ric_ies;\n\tft_evt_parms.ric_ies_len = pft_roam->ft_event.ric_ies_len;\n\n\trtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA, &irqL);\n\trtw_cfg80211_ft_event(padapter, &ft_evt_parms);\n\tRTW_INFO(\"FT: rtw_ft_report_evt\\n\");\n\trtw_mfree((u8 *)pft_roam->ft_event.target_ap, ETH_ALEN);\nerr_1:\n\trtw_mfree((u8 *)ft_evt_parms.ies, ft_evt_parms.ies_len);\nerr_2:\n\treturn;\n}\n\nvoid rtw_ft_report_reassoc_evt(_adapter *padapter, u8 *pMacAddr)\n{\n\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n\tstruct cmd_priv *pcmdpriv = &(padapter->cmdpriv);\n\tstruct cmd_obj *pcmd_obj = NULL;\n\tstruct stassoc_event *passoc_sta_evt = NULL;\n\tstruct C2HEvent_Header *pc2h_evt_hdr = NULL;\n\tu8 *pevtcmd = NULL;\n\tu32 cmdsz = 0;\n\n\tpcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (pcmd_obj == NULL)\n\t\treturn;\n\n\tcmdsz = (sizeof(struct stassoc_event) + sizeof(struct C2HEvent_Header));\n\tpevtcmd = (u8 *)rtw_zmalloc(cmdsz);\n\tif (pevtcmd == NULL) {\n\t\trtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));\n\t\treturn;\n\t}\n\n\t_rtw_init_listhead(&pcmd_obj->list);\n\tpcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);\n\tpcmd_obj->cmdsz = cmdsz;\n\tpcmd_obj->parmbuf = pevtcmd;\n\tpcmd_obj->rsp = NULL;\n\tpcmd_obj->rspsz  = 0;\n\n\tpc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd);\n\tpc2h_evt_hdr->len = sizeof(struct stassoc_event);\n\tpc2h_evt_hdr->ID = GEN_EVT_CODE(_FT_REASSOC);\n\tpc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);\n\n\tpassoc_sta_evt = (struct stassoc_event *)(pevtcmd + sizeof(struct C2HEvent_Header));\n\t_rtw_memcpy((unsigned char *)(&(passoc_sta_evt->macaddr)), pMacAddr, ETH_ALEN);\n\trtw_enqueue_cmd(pcmdpriv, pcmd_obj);\n}\n\nvoid rtw_ft_link_timer_hdl(void *ctx)\n{\n\t_adapter *padapter = (_adapter *)ctx;\n\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);\n\n\tif (rtw_ft_chk_status(padapter, RTW_FT_REQUESTING_STA)) {\n\t\tif (pft_roam->ft_req_retry_cnt < RTW_FT_ACTION_REQ_LMT) {\n\t\t\tpft_roam->ft_req_retry_cnt++;\n\t\t\trtw_ft_issue_action_req(padapter, (u8 *)pmlmepriv->roam_network->network.MacAddress);\n\t\t\t_set_timer(&pmlmeext->ft_link_timer, REASSOC_TO);\n\t\t} else {\n\t\t\tpft_roam->ft_req_retry_cnt = 0;\t\n\t\t\tif (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)\n\t\t\t\trtw_ft_set_status(padapter, RTW_FT_ASSOCIATED_STA);\n\t\t\telse\n\t\t\t\trtw_ft_reset_status(padapter);\n\t\t}\n\t}\n}\n\nvoid rtw_ft_roam_timer_hdl(void *ctx)\n{\n\t_adapter *padapter = (_adapter *)ctx;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\treceive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress\n\t\t\t\t, WLAN_REASON_ACTIVE_ROAM, _FALSE);\n}\n\nvoid rtw_ft_roam_status_reset(_adapter *padapter)\n{\n\tstruct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);\n\n\tif ((rtw_to_roam(padapter) > 0) && \n\t\t(!rtw_ft_chk_status(padapter, RTW_FT_REQUESTED_STA))) {\n\t\trtw_ft_reset_status(padapter);\n\t}\t\n\t\n\tpadapter->mlmepriv.ft_roam.ft_updated_bcn = _FALSE;\n}\n#endif\n\nu8 NULL_hdl(_adapter *padapter, u8 *pbuf)\n{\n\treturn H2C_SUCCESS;\n}\n\n#ifdef CONFIG_AUTO_AP_MODE\nvoid rtw_auto_ap_rx_msg_dump(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_pos)\n{\n\tstruct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;\n\tstruct sta_info *psta = precv_frame->u.hdr.psta;\n\tstruct ethhdr *ehdr = (struct ethhdr *)ehdr_pos;\n\n\tRTW_INFO(\"eth rx: got eth_type=0x%x\\n\", ntohs(ehdr->h_proto));\n\n\tif (psta && psta->isrc && psta->pid > 0) {\n\t\tu16 rx_pid;\n\n\t\trx_pid = *(u16 *)(ehdr_pos + ETH_HLEN);\n\n\t\tRTW_INFO(\"eth rx(pid=0x%x): sta(\"MAC_FMT\") pid=0x%x\\n\",\n\t\t\t rx_pid, MAC_ARG(psta->cmn.mac_addr), psta->pid);\n\n\t\tif (rx_pid == psta->pid) {\n\t\t\tint i;\n\t\t\tu16 len = *(u16 *)(ehdr_pos + ETH_HLEN + 2);\n\t\t\t/* u16 ctrl_type = *(u16 *)(ehdr_pos + ETH_HLEN + 4); */\n\n\t\t\t/* RTW_INFO(\"eth, RC: len=0x%x, ctrl_type=0x%x\\n\", len, ctrl_type);  */\n\t\t\tRTW_INFO(\"eth, RC: len=0x%x\\n\", len);\n\n\t\t\tfor (i = 0; i < len; i++)\n\t\t\t\tRTW_INFO(\"0x%x\\n\", *(ehdr_pos + ETH_HLEN + 4 + i));\n\t\t\t/* RTW_INFO(\"0x%x\\n\", *(ehdr_pos + ETH_HLEN + 6 + i)); */\n\n\t\t\tRTW_INFO(\"eth, RC-end\\n\");\n\t\t}\n\t}\n\n}\n\nvoid rtw_start_auto_ap(_adapter *adapter)\n{\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\trtw_set_802_11_infrastructure_mode(adapter, Ndis802_11APMode);\n\n\trtw_setopmode_cmd(adapter, Ndis802_11APMode, RTW_CMDF_WAIT_ACK);\n}\n\nstatic int rtw_auto_ap_start_beacon(_adapter *adapter)\n{\n\tint ret = 0;\n\tu8 *pbuf = NULL;\n\tuint len;\n\tu8\tsupportRate[16];\n\tint\tsz = 0, rateLen;\n\tu8\t*ie;\n\tu8\twireless_mode, oper_channel;\n\tu8 ssid[3] = {0}; /* hidden ssid */\n\tu32 ssid_len = sizeof(ssid);\n\tstruct mlme_priv *pmlmepriv = &(adapter->mlmepriv);\n\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)\n\t\treturn -EINVAL;\n\n\n\tlen = 128;\n\tpbuf = rtw_zmalloc(len);\n\tif (!pbuf)\n\t\treturn -ENOMEM;\n\n\n\t/* generate beacon */\n\tie = pbuf;\n\n\t/* timestamp will be inserted by hardware */\n\tsz += 8;\n\tie += sz;\n\n\t/* beacon interval : 2bytes */\n\t*(u16 *)ie = cpu_to_le16((u16)100); /* BCN_INTERVAL=100; */\n\tsz += 2;\n\tie += 2;\n\n\t/* capability info */\n\t*(u16 *)ie = 0;\n\t*(u16 *)ie |= cpu_to_le16(cap_ESS);\n\t*(u16 *)ie |= cpu_to_le16(cap_ShortPremble);\n\t/* *(u16*)ie |= cpu_to_le16(cap_Privacy); */\n\tsz += 2;\n\tie += 2;\n\n\t/* SSID */\n\tie = rtw_set_ie(ie, _SSID_IE_, ssid_len, ssid, &sz);\n\n\t/* supported rates */\n\twireless_mode = (WIRELESS_11BG_24N & padapter->registrypriv.wireless_mode);\n\trtw_set_supported_rate(supportRate, wireless_mode);\n\trateLen = rtw_get_rateset_len(supportRate);\n\tif (rateLen > 8)\n\t\tie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, 8, supportRate, &sz);\n\telse\n\t\tie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, rateLen, supportRate, &sz);\n\n\n\t/* DS parameter set */\n\tif (rtw_mi_check_status(adapter, MI_LINKED))\n\t\toper_channel = rtw_mi_get_union_chan(adapter);\n\telse\n\t\toper_channel = adapter_to_dvobj(adapter)->oper_channel;\n\n\tie = rtw_set_ie(ie, _DSSET_IE_, 1, &oper_channel, &sz);\n\n\t/* ext supported rates */\n\tif (rateLen > 8)\n\t\tie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (supportRate + 8), &sz);\n\n\tRTW_INFO(\"%s, start auto ap beacon sz=%d\\n\", __FUNCTION__, sz);\n\n\t/* lunch ap mode & start to issue beacon */\n\tif (rtw_check_beacon_data(adapter, pbuf,  sz) == _SUCCESS) {\n\n\t} else\n\t\tret = -EINVAL;\n\n\n\trtw_mfree(pbuf, len);\n\n\treturn ret;\n\n}\n#endif/* CONFIG_AUTO_AP_MODE */\n\nu8 setopmode_hdl(_adapter *padapter, u8 *pbuf)\n{\n\tu8\ttype;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct setopmode_parm *psetop = (struct setopmode_parm *)pbuf;\n\n\tif (psetop->mode == Ndis802_11APMode\n\t\t|| psetop->mode == Ndis802_11_mesh\n\t) {\n\t\tpmlmeinfo->state = WIFI_FW_AP_STATE;\n\t\ttype = _HW_STATE_AP_;\n\t} else if (psetop->mode == Ndis802_11Infrastructure) {\n\t\tpmlmeinfo->state &= ~(BIT(0) | BIT(1)); /* clear state */\n\t\tpmlmeinfo->state |= WIFI_FW_STATION_STATE;/* set to \tSTATION_STATE */\n\t\ttype = _HW_STATE_STATION_;\n\t} else if (psetop->mode == Ndis802_11IBSS)\n\t\ttype = _HW_STATE_ADHOC_;\n\telse if (psetop->mode == Ndis802_11Monitor)\n\t\ttype = _HW_STATE_MONITOR_;\n\telse\n\t\ttype = _HW_STATE_NOLINK_;\n\n#ifdef CONFIG_AP_PORT_SWAP\n\trtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, (u8 *)(&type));\n#endif\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_SET_OPMODE, (u8 *)(&type));\n\n#ifdef CONFIG_AUTO_AP_MODE\n\tif (psetop->mode == Ndis802_11APMode)\n\t\trtw_auto_ap_start_beacon(padapter);\n#endif\n\n\tif (rtw_port_switch_chk(padapter) == _TRUE) {\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);\n\n\t\tif (psetop->mode == Ndis802_11APMode)\n\t\t\tadapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff; /* ap mode won't dowload rsvd pages */\n\t\telse if (psetop->mode == Ndis802_11Infrastructure) {\n#ifdef CONFIG_LPS\n\t\t\t_adapter *port0_iface = dvobj_get_port0_adapter(adapter_to_dvobj(padapter));\n\t\t\tif (port0_iface)\n\t\t\t\trtw_lps_ctrl_wk_cmd(port0_iface, LPS_CTRL_CONNECT, RTW_CMDF_DIRECTLY);\n#endif\n\t\t}\n\t}\n\n#ifdef CONFIG_BT_COEXIST\n\tif (psetop->mode == Ndis802_11APMode\n\t\t|| psetop->mode == Ndis802_11_mesh\n\t\t|| psetop->mode == Ndis802_11Monitor\n\t) {\n\t\t/* Do this after port switch to */\n\t\t/* prevent from downloading rsvd page to wrong port */\n\t\trtw_btcoex_MediaStatusNotify(padapter, 1); /* connect */\n\t}\n#endif /* CONFIG_BT_COEXIST */\n\n\treturn H2C_SUCCESS;\n\n}\n\nu8 createbss_hdl(_adapter *padapter, u8 *pbuf)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));\n\tWLAN_BSSID_EX\t*pdev_network = &padapter->registrypriv.dev_network;\n\tstruct createbss_parm *parm = (struct createbss_parm *)pbuf;\n\tu8 ret = H2C_SUCCESS;\n\t/* u8\tinitialgain; */\n\n#ifdef CONFIG_AP_MODE\n\tif ((parm->req_ch == 0 && pmlmeinfo->state == WIFI_FW_AP_STATE)\n\t\t|| parm->req_ch != 0\n\t) {\n\t\tstart_bss_network(padapter, parm);\n\t\tgoto exit;\n\t}\n#endif\n\n\t/* below is for ad-hoc master */\n\tif (parm->adhoc) {\n\t\trtw_warn_on(pdev_network->InfrastructureMode != Ndis802_11IBSS);\n\t\trtw_joinbss_reset(padapter);\n\n\t\tpmlmeext->cur_bwmode = CHANNEL_WIDTH_20;\n\t\tpmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tpmlmeinfo->ERP_enable = 0;\n\t\tpmlmeinfo->WMM_enable = 0;\n\t\tpmlmeinfo->HT_enable = 0;\n\t\tpmlmeinfo->HT_caps_enable = 0;\n\t\tpmlmeinfo->HT_info_enable = 0;\n\t\tpmlmeinfo->agg_enable_bitmap = 0;\n\t\tpmlmeinfo->candidate_tid_bitmap = 0;\n\n\t\t/* cancel link timer */\n\t\t_cancel_timer_ex(&pmlmeext->link_timer);\n\n\t\t/* clear CAM */\n\t\tflush_all_cam_entry(padapter);\n\n\t\tpdev_network->Length = get_WLAN_BSSID_EX_sz(pdev_network);\n\t\t_rtw_memcpy(pnetwork, pdev_network, FIELD_OFFSET(WLAN_BSSID_EX, IELength));\n\t\tpnetwork->IELength = pdev_network->IELength;\n\n\t\tif (pnetwork->IELength > MAX_IE_SZ) {\n\t\t\tret = H2C_PARAMETERS_ERROR;\n\t\t\tgoto ibss_post_hdl;\n\t\t}\n\n\t\t_rtw_memcpy(pnetwork->IEs, pdev_network->IEs, pnetwork->IELength);\n\t\tstart_create_ibss(padapter);\n\t} else {\n\t\trtw_warn_on(1);\n\t\tret = H2C_PARAMETERS_ERROR;\n\t}\n\nibss_post_hdl:\n\trtw_create_ibss_post_hdl(padapter, ret);\n\nexit:\n\treturn ret;\n}\n\nu8 join_cmd_hdl(_adapter *padapter, u8 *pbuf)\n{\n\tu8\tjoin_type;\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t\t*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\tstruct joinbss_parm\t*pparm = (struct joinbss_parm *)pbuf;\n#endif /* CONFIG_ANTENNA_DIVERSITY */\n\tu32 i;\n\t/* u8\tinitialgain; */\n\t/* u32\tacparm; */\n\tu8 u_ch, u_bw, u_offset;\n\tu8 doiqk = _FALSE;\n\n\t/* check already connecting to AP or not */\n\tif (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) {\n\t\tif (pmlmeinfo->state & WIFI_FW_STATION_STATE)\n\t\t\tissue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100);\n\t\tpmlmeinfo->state = WIFI_FW_NULL_STATE;\n\n\t\t/* clear CAM */\n\t\tflush_all_cam_entry(padapter);\n\n\t\t_cancel_timer_ex(&pmlmeext->link_timer);\n\n\t\t/* set MSR to nolink->infra. mode\t\t */\n\t\t/* Set_MSR(padapter, _HW_STATE_NOLINK_); */\n\t\tSet_MSR(padapter, _HW_STATE_STATION_);\n\n\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0);\n\t\tif (pmlmeinfo->state & WIFI_FW_STATION_STATE)\n\t\t\trtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_DISCONNECTED);\n\t}\n\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\trtw_antenna_select_cmd(padapter, pparm->network.PhyInfo.Optimum_antenna, _FALSE);\n#endif\n\n#ifdef CONFIG_WAPI_SUPPORT\n\trtw_wapi_clear_all_cam_entry(padapter);\n#endif\n\n\trtw_joinbss_reset(padapter);\n\n\tpmlmeinfo->ERP_enable = 0;\n\tpmlmeinfo->WMM_enable = 0;\n\tpmlmeinfo->HT_enable = 0;\n\tpmlmeinfo->HT_caps_enable = 0;\n\tpmlmeinfo->HT_info_enable = 0;\n\tpmlmeinfo->agg_enable_bitmap = 0;\n\tpmlmeinfo->candidate_tid_bitmap = 0;\n\tpmlmeinfo->bwmode_updated = _FALSE;\n\t/* pmlmeinfo->assoc_AP_vendor = HT_IOT_PEER_MAX; */\n\tpmlmeinfo->VHT_enable = 0;\n#ifdef ROKU_PRIVATE\n\tpmlmeinfo->ht_vht_received = 0;\n\t_rtw_memset(pmlmeinfo->SupportedRates_infra_ap, 0, NDIS_802_11_LENGTH_RATES_EX);\n#endif /* ROKU_PRIVATE */\n\t_rtw_memcpy(pnetwork, pbuf, FIELD_OFFSET(WLAN_BSSID_EX, IELength));\n\tpnetwork->IELength = ((WLAN_BSSID_EX *)pbuf)->IELength;\n\n\tif (pnetwork->IELength > MAX_IE_SZ) /* Check pbuf->IELength */\n\t\treturn H2C_PARAMETERS_ERROR;\n\n\tif (pnetwork->IELength < 2) {\n\t\treport_join_res(padapter, (-4), WLAN_STATUS_UNSPECIFIED_FAILURE);\n\t\treturn H2C_SUCCESS;\n\t}\n\t_rtw_memcpy(pnetwork->IEs, ((WLAN_BSSID_EX *)pbuf)->IEs, pnetwork->IELength);\n\n\tpmlmeinfo->bcn_interval = get_beacon_interval(pnetwork);\n\n\t/* Check AP vendor to move rtw_joinbss_cmd() */\n\t/* pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->IEs, pnetwork->IELength); */\n\n\t/* sizeof(NDIS_802_11_FIXED_IEs)\t */\n\tfor (i = _FIXED_IE_LENGTH_ ; i < pnetwork->IELength - 2 ;) {\n\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i);\n\n\t\tswitch (pIE->ElementID) {\n\t\tcase _VENDOR_SPECIFIC_IE_: /* Get WMM IE. */\n\t\t\tif (_rtw_memcmp(pIE->data, WMM_OUI, 4))\n\t\t\t\tWMM_param_handler(padapter, pIE);\n\t\t\tbreak;\n\n#ifdef CONFIG_80211N_HT\n\t\tcase _HT_CAPABILITY_IE_:\t/* Get HT Cap IE. */\n\t\t\tpmlmeinfo->HT_caps_enable = 1;\n\t\t\tbreak;\n\n\t\tcase _HT_EXTRA_INFO_IE_:\t/* Get HT Info IE. */\n\t\t\tpmlmeinfo->HT_info_enable = 1;\n\t\t\tbreak;\n#endif /* CONFIG_80211N_HT */\n\n#ifdef CONFIG_80211AC_VHT\n\t\tcase EID_VHTCapability: /* Get VHT Cap IE. */\n\t\t\tpmlmeinfo->VHT_enable = 1;\n\t\t\tbreak;\n\n\t\tcase EID_VHTOperation: /* Get VHT Operation IE. */\n\t\t\tbreak;\n#endif /* CONFIG_80211AC_VHT */\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\ti += (pIE->Length + 2);\n\t}\n\n\trtw_bss_get_chbw(pnetwork\n\t\t, &pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset, 1, 1);\n\n\trtw_adjust_chbw(padapter, pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset);\n\n#if 0\n\tif (padapter->registrypriv.wifi_spec) {\n\t\t/* for WiFi test, follow WMM test plan spec */\n\t\tacparm = 0x002F431C; /* VO */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm));\n\t\tacparm = 0x005E541C; /* VI */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm));\n\t\tacparm = 0x0000A525; /* BE */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));\n\t\tacparm = 0x0000A549; /* BK */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm));\n\n\t\t/* for WiFi test, mixed mode with intel STA under bg mode throughput issue */\n\t\tif (padapter->mlmepriv.htpriv.ht_option == _FALSE) {\n\t\t\tacparm = 0x00004320;\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));\n\t\t}\n\t} else {\n\t\tacparm = 0x002F3217; /* VO */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm));\n\t\tacparm = 0x005E4317; /* VI */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm));\n\t\tacparm = 0x00105320; /* BE */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));\n\t\tacparm = 0x0000A444; /* BK */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm));\n\t}\n#endif\n\n\t/* check channel, bandwidth, offset and switch */\n\tif (rtw_chk_start_clnt_join(padapter, &u_ch, &u_bw, &u_offset) == _FAIL) {\n\t\treport_join_res(padapter, (-4), WLAN_STATUS_UNSPECIFIED_FAILURE);\n\t\treturn H2C_SUCCESS;\n\t}\n\n\t/* disable dynamic functions, such as high power, DIG */\n\t/*rtw_phydm_func_disable_all(padapter);*/\n\n\t/* config the initial gain under linking, need to write the BB registers */\n\t/* initialgain = 0x1E; */\n\t/*rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);*/\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);\n\tif (MLME_IS_STA(padapter))\n\t\trtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTING);\n\telse\n\t\trtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);\n\n\tjoin_type = 0;\n\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));\n\n\tdoiqk = _TRUE;\n\trtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);\n\n\tset_channel_bwmode(padapter, u_ch, u_offset, u_bw);\n\trtw_mi_update_union_chan_inf(padapter, u_ch, u_offset, u_bw);\n\n\tdoiqk = _FALSE;\n\trtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);\n\n\t/* cancel link timer */\n\t_cancel_timer_ex(&pmlmeext->link_timer);\n\n\tstart_clnt_join(padapter);\n\n\treturn H2C_SUCCESS;\n\n}\n\nu8 disconnect_hdl(_adapter *padapter, unsigned char *pbuf)\n{\n#ifdef CONFIG_DFS\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n#endif\n\tstruct disconnect_parm *param = (struct disconnect_parm *)pbuf;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t\t*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));\n\tu8 val8;\n\n\tif (is_client_associated_to_ap(padapter)\n\t\t#ifdef CONFIG_DFS\n\t\t&& !IS_RADAR_DETECTED(rfctl) && !rfctl->csa_ch\n\t\t#endif\n\t) {\n\t\t#ifdef CONFIG_PLATFORM_ROCKCHIPS\n\t\t/* To avoid connecting to AP fail during resume process, change retry count from 5 to 1 */\n\t\tissue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100);\n\t\t#else\n\t\tissue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, param->deauth_timeout_ms / 100, 100);\n\t\t#endif /* CONFIG_PLATFORM_ROCKCHIPS */\n\t}\n\n#ifndef CONFIG_SUPPORT_MULTI_BCN\n\tif (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {\n\t\t/* Stop BCN */\n\t\tval8 = 0;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_BCN_FUNC, (u8 *)(&val8));\n\t}\n#endif\n\n\trtw_mlmeext_disconnect(padapter);\n\n\trtw_free_uc_swdec_pending_queue(padapter);\n\n\trtw_sta_mstatus_report(padapter);\n\n\treturn\tH2C_SUCCESS;\n}\n\nstatic const char *const _scan_state_str[] = {\n\t\"SCAN_DISABLE\",\n\t\"SCAN_START\",\n\t\"SCAN_PS_ANNC_WAIT\",\n\t\"SCAN_ENTER\",\n\t\"SCAN_PROCESS\",\n\t\"SCAN_BACKING_OP\",\n\t\"SCAN_BACK_OP\",\n\t\"SCAN_LEAVING_OP\",\n\t\"SCAN_LEAVE_OP\",\n\t\"SCAN_SW_ANTDIV_BL\",\n\t\"SCAN_TO_P2P_LISTEN\",\n\t\"SCAN_P2P_LISTEN\",\n\t\"SCAN_COMPLETE\",\n\t\"SCAN_STATE_MAX\",\n};\n\nconst char *scan_state_str(u8 state)\n{\n\tstate = (state >= SCAN_STATE_MAX) ? SCAN_STATE_MAX : state;\n\treturn _scan_state_str[state];\n}\n\nstatic bool scan_abort_hdl(_adapter *adapter)\n{\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct ss_res *ss = &pmlmeext->sitesurvey_res;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *pwdinfo = &adapter->wdinfo;\n#endif\n\tbool ret = _FALSE;\n\n\tif (pmlmeext->scan_abort == _TRUE) {\n#ifdef CONFIG_P2P\n\t\tif (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) {\n\t\t\trtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_MAX);\n\t\t\tss->channel_idx = 3;\n\t\t\tRTW_INFO(\"%s idx:%d, cnt:%u\\n\", __FUNCTION__\n\t\t\t\t , ss->channel_idx\n\t\t\t\t , pwdinfo->find_phase_state_exchange_cnt\n\t\t\t\t);\n\t\t} else\n#endif\n\t\t{\n\t\t\tss->channel_idx = ss->ch_num;\n\t\t\tRTW_INFO(\"%s idx:%d\\n\", __FUNCTION__\n\t\t\t\t , ss->channel_idx\n\t\t\t\t);\n\t\t}\n\t\tpmlmeext->scan_abort = _FALSE;\n\t\tret = _TRUE;\n\t}\n\n\treturn ret;\n}\n\nu8 rtw_scan_sparse(_adapter *adapter, struct rtw_ieee80211_channel *ch, u8 ch_num)\n{\n\t/* interval larger than this is treated as backgroud scan */\n#ifndef RTW_SCAN_SPARSE_BG_INTERVAL_MS\n#define RTW_SCAN_SPARSE_BG_INTERVAL_MS 12000\n#endif\n\n#ifndef RTW_SCAN_SPARSE_CH_NUM_MIRACAST\n#define RTW_SCAN_SPARSE_CH_NUM_MIRACAST 1\n#endif\n#ifndef RTW_SCAN_SPARSE_CH_NUM_BG\n#define RTW_SCAN_SPARSE_CH_NUM_BG 4\n#endif\n#ifdef CONFIG_LAYER2_ROAMING\n#ifndef RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE\n#define RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE 1\n#endif\n#endif\n\n#define SCAN_SPARSE_CH_NUM_INVALID 255\n\n\tstatic u8 token = 255;\n\tu32 interval;\n\tbool busy_traffic = _FALSE;\n\tbool miracast_enabled = _FALSE;\n\tbool bg_scan = _FALSE;\n\tu8 max_allow_ch = SCAN_SPARSE_CH_NUM_INVALID;\n\tu8 scan_division_num;\n\tu8 ret_num = ch_num;\n\tstruct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));\n\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\n\tif (regsty->wifi_spec)\n\t\tgoto exit;\n\n\t/* assume ch_num > 6 is normal scan */\n\tif (ch_num <= 6)\n\t\tgoto exit;\n\n\tif (mlmeext->last_scan_time == 0)\n\t\tmlmeext->last_scan_time = rtw_get_current_time();\n\n\tinterval = rtw_get_passing_time_ms(mlmeext->last_scan_time);\n\n\n\tif (rtw_mi_busy_traffic_check(adapter, _FALSE))\n\t\tbusy_traffic = _TRUE;\n\n\tif (rtw_mi_check_miracast_enabled(adapter))\n\t\tmiracast_enabled = _TRUE;\n\n\tif (interval > RTW_SCAN_SPARSE_BG_INTERVAL_MS)\n\t\tbg_scan = _TRUE;\n\n\t/* max_allow_ch by conditions*/\n\n#if RTW_SCAN_SPARSE_MIRACAST\n\tif (miracast_enabled == _TRUE && busy_traffic == _TRUE)\n\t\tmax_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_MIRACAST);\n#endif\n\n#if RTW_SCAN_SPARSE_BG\n\tif (bg_scan == _TRUE)\n\t\tmax_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_BG);\n#endif\n\n#if  defined(CONFIG_LAYER2_ROAMING) && defined(RTW_SCAN_SPARSE_ROAMING_ACTIVE)\n\tif (rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) {\n\t\tif (busy_traffic == _TRUE && adapter->mlmepriv.need_to_roam == _TRUE)\n\t\t\tmax_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE);\n\t}\n#endif\n\n\n\tif (max_allow_ch != SCAN_SPARSE_CH_NUM_INVALID) {\n\t\tint i;\n\t\tint k = 0;\n\n\t\tscan_division_num = (ch_num / max_allow_ch) + ((ch_num % max_allow_ch) ? 1 : 0);\n\t\ttoken = (token + 1) % scan_division_num;\n\n\t\tif (0)\n\t\t\tRTW_INFO(\"scan_division_num:%u, token:%u\\n\", scan_division_num, token);\n\n\t\tfor (i = 0; i < ch_num; i++) {\n\t\t\tif (ch[i].hw_value && (i % scan_division_num) == token\n\t\t\t   ) {\n\t\t\t\tif (i != k)\n\t\t\t\t\t_rtw_memcpy(&ch[k], &ch[i], sizeof(struct rtw_ieee80211_channel));\n\t\t\t\tk++;\n\t\t\t}\n\t\t}\n\n\t\t_rtw_memset(&ch[k], 0, sizeof(struct rtw_ieee80211_channel));\n\n\t\tret_num = k;\n\t\tmlmeext->last_scan_time = rtw_get_current_time();\n\t}\n\nexit:\n\treturn ret_num;\n}\n\n#ifdef CONFIG_SCAN_BACKOP\nu8 rtw_scan_backop_decision(_adapter *adapter)\n{\n\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\tstruct mi_state mstate;\n\tu8 backop_flags = 0;\n\n\trtw_mi_status(adapter, &mstate);\n\n\tif ((MSTATE_STA_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(mlmeext, SS_BACKOP_EN))\n\t\t|| (MSTATE_STA_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(mlmeext, SS_BACKOP_EN_NL)))\n\t\tbackop_flags |= mlmeext_scan_backop_flags_sta(mlmeext);\n\n#ifdef CONFIG_AP_MODE\n\tif ((MSTATE_AP_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(mlmeext, SS_BACKOP_EN))\n\t\t|| (MSTATE_AP_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(mlmeext, SS_BACKOP_EN_NL)))\n\t\tbackop_flags |= mlmeext_scan_backop_flags_ap(mlmeext);\n#endif\n\n#ifdef CONFIG_RTW_MESH\n\tif ((MSTATE_MESH_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_mesh(mlmeext, SS_BACKOP_EN))\n\t\t|| (MSTATE_MESH_NUM(&mstate) && mlmeext_chk_scan_backop_flags_mesh(mlmeext, SS_BACKOP_EN_NL)))\n\t\tbackop_flags |= mlmeext_scan_backop_flags_mesh(mlmeext);\n#endif\n\n\treturn backop_flags;\n}\n#endif\n\n#define SCANNING_TIMEOUT_EX\t2000\nu32 rtw_scan_timeout_decision(_adapter *padapter)\n{\n\tu32 back_op_times= 0;\n\tu8 max_chan_num;\n\tu16 scan_ms;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct ss_res *ss = &pmlmeext->sitesurvey_res;\n\n\tif (is_supported_5g(padapter->registrypriv.wireless_mode)\n\t\t&& IsSupported24G(padapter->registrypriv.wireless_mode)) \n\t\tmax_chan_num = MAX_CHANNEL_NUM;/* dual band */\n\telse\n\t\tmax_chan_num = MAX_CHANNEL_NUM_2G;/*single band*/\n\n\t#ifdef CONFIG_SCAN_BACKOP\n\tif (rtw_scan_backop_decision(padapter))\n\t\tback_op_times = (max_chan_num / ss->scan_cnt_max) * ss->backop_ms;\n\t#endif\n\n\tif (ss->duration)\n\t\tscan_ms = ss->duration;\n\telse\n\t#if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)\n\tif (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter))\n\t\tscan_ms = rtw_acs_get_adv_st(padapter);\n\telse\n\t#endif /*CONFIG_RTW_ACS*/\n\t\tscan_ms = ss->scan_ch_ms;\n\n\tss->scan_timeout_ms = (scan_ms * max_chan_num) + back_op_times + SCANNING_TIMEOUT_EX;\n\t#ifdef DBG_SITESURVEY\n\tRTW_INFO(\"%s , scan_timeout_ms = %d (ms)\\n\", __func__, ss->scan_timeout_ms);\n\t#endif /*DBG_SITESURVEY*/\n\treturn ss->scan_timeout_ms;\n}\n\nstatic int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel *out,\n\t\tu32 out_num, struct rtw_ieee80211_channel *in, u32 in_num)\n{\n\tint i, j;\n\tint set_idx;\n\tu8 chan;\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\n\t/* clear first */\n\t_rtw_memset(out, 0, sizeof(struct rtw_ieee80211_channel) * out_num);\n\n\t/* acquire channels from in */\n\tj = 0;\n\tfor (i = 0; i < in_num; i++) {\n\n\t\tif (0)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" \"CHAN_FMT\"\\n\", FUNC_ADPT_ARG(padapter), CHAN_ARG(&in[i]));\n\n\t\tif (!in[i].hw_value || (in[i].flags & RTW_IEEE80211_CHAN_DISABLED))\n\t\t\tcontinue;\n\t\tif (rtw_mlme_band_check(padapter, in[i].hw_value) == _FALSE)\n\t\t\tcontinue;\n\n\t\tset_idx = rtw_chset_search_ch(rfctl->channel_set, in[i].hw_value);\n\t\tif (set_idx >= 0) {\n\t\t\tif (j >= out_num) {\n\t\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" out_num:%u not enough\\n\",\n\t\t\t\t\t  FUNC_ADPT_ARG(padapter), out_num);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t_rtw_memcpy(&out[j], &in[i], sizeof(struct rtw_ieee80211_channel));\n\n\t\t\tif (rfctl->channel_set[set_idx].ScanType == SCAN_PASSIVE)\n\t\t\t\tout[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN;\n\n\t\t\tj++;\n\t\t}\n\t\tif (j >= out_num)\n\t\t\tbreak;\n\t}\n\n\t/* if out is empty, use channel_set as default */\n\tif (j == 0) {\n\t\tfor (i = 0; i < rfctl->max_chan_nums; i++) {\n\t\t\tchan = rfctl->channel_set[i].ChannelNum;\n\t\t\tif (rtw_mlme_band_check(padapter, chan) == _TRUE) {\n\t\t\t\tif (rtw_mlme_ignore_chan(padapter, chan) == _TRUE)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (0)\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" ch:%u\\n\", FUNC_ADPT_ARG(padapter), chan);\n\n\t\t\t\tif (j >= out_num) {\n\t\t\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" out_num:%u not enough\\n\",\n\t\t\t\t\t\tFUNC_ADPT_ARG(padapter), out_num);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\tout[j].hw_value = chan;\n\n\t\t\t\tif (rfctl->channel_set[i].ScanType == SCAN_PASSIVE)\n\t\t\t\t\tout[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN;\n\n\t\t\t\tj++;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* scan_sparse */\n\tj = rtw_scan_sparse(padapter, out, j);\n\n\treturn j;\n}\n\nstatic void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm)\n{\n\tstruct ss_res *ss = &adapter->mlmeextpriv.sitesurvey_res;\n\tRT_CHANNEL_INFO *chset = adapter_to_chset(adapter);\n\tint i;\n\n\tss->bss_cnt = 0;\n\tss->channel_idx = 0;\n#ifdef CONFIG_DFS\n\tss->dfs_ch_ssid_scan = 0;\n#endif\n\tss->igi_scan = 0;\n\tss->igi_before_scan = 0;\n#ifdef CONFIG_SCAN_BACKOP\n\tss->scan_cnt = 0;\n#endif\n#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)\n\tss->is_sw_antdiv_bl_scan = 0;\n#endif\n\tss->ssid_num = 0;\n\tfor (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) {\n\t\tif (parm->ssid[i].SsidLength) {\n\t\t\t_rtw_memcpy(ss->ssid[i].Ssid, parm->ssid[i].Ssid, IW_ESSID_MAX_SIZE);\n\t\t\tss->ssid[i].SsidLength = parm->ssid[i].SsidLength;\n\t\t\tss->ssid_num++;\n\t\t} else\n\t\t\tss->ssid[i].SsidLength = 0;\n\t}\n\n\tss->ch_num = rtw_scan_ch_decision(adapter\n\t\t\t\t\t  , ss->ch, RTW_CHANNEL_SCAN_AMOUNT\n\t\t\t\t\t  , parm->ch, parm->ch_num\n\t\t\t\t\t );\n\n#ifdef CONFIG_DFS\n\tfor (i = 0; i < MAX_CHANNEL_NUM; i++)\n\t\tchset[i].hidden_bss_cnt = 0;\n#endif\n\n\tss->bw = parm->bw;\n\tss->igi = parm->igi;\n\tss->token = parm->token;\n\tss->duration = parm->duration;\n\tss->scan_mode = parm->scan_mode;\n\tss->token = parm->token;\n}\n\nstatic u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE *type)\n{\n\tu8 next_state;\n\tu8 scan_ch = 0;\n\tRT_SCAN_TYPE scan_type = SCAN_PASSIVE;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct ss_res *ss = &pmlmeext->sitesurvey_res;\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tint ch_set_idx;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *pwdinfo = &padapter->wdinfo;\n#endif\n#ifdef CONFIG_SCAN_BACKOP\n\tu8 backop_flags = 0;\n#endif\n\n\t/* handle scan abort request */\n\tscan_abort_hdl(padapter);\n\n#ifdef CONFIG_P2P\n\tif (pwdinfo->rx_invitereq_info.scan_op_ch_only || pwdinfo->p2p_info.scan_op_ch_only) {\n\t\tif (pwdinfo->rx_invitereq_info.scan_op_ch_only)\n\t\t\tscan_ch = pwdinfo->rx_invitereq_info.operation_ch[ss->channel_idx];\n\t\telse\n\t\t\tscan_ch = pwdinfo->p2p_info.operation_ch[ss->channel_idx];\n\t\tscan_type = SCAN_ACTIVE;\n\t} else if (rtw_p2p_findphase_ex_is_social(pwdinfo)) {\n\t\t/*\n\t\t* Commented by Albert 2011/06/03\n\t\t* The driver is in the find phase, it should go through the social channel.\n\t\t*/\n\t\tscan_ch = pwdinfo->social_chan[ss->channel_idx];\n\t\tch_set_idx = rtw_chset_search_ch(rfctl->channel_set, scan_ch);\n\t\tif (ch_set_idx >= 0)\n\t\t\tscan_type = rfctl->channel_set[ch_set_idx].ScanType;\n\t\telse\n\t\t\tscan_type = SCAN_ACTIVE;\n\t} else\n#endif /* CONFIG_P2P */\n\t{\n\t\tstruct rtw_ieee80211_channel *ch;\n\n\t\t#ifdef CONFIG_SCAN_BACKOP\n\t\tbackop_flags = rtw_scan_backop_decision(padapter);\n\t\t#endif\n\n#ifdef CONFIG_DFS\n\t\t#ifdef CONFIG_SCAN_BACKOP\n\t\tif (!(backop_flags && ss->scan_cnt >= ss->scan_cnt_max))\n\t\t#endif\n\t\t{\n\t\t\t#ifdef CONFIG_RTW_WIFI_HAL\n\t\t\tif (adapter_to_dvobj(padapter)->nodfs) {\n\t\t\t\twhile ( ss->channel_idx < ss->ch_num && rtw_is_dfs_ch(ss->ch[ss->channel_idx].hw_value))\n\t\t\t\t\tss->channel_idx++;\n\t\t\t} else\n\t\t\t#endif\n\t\t\tif (ss->channel_idx != 0 && ss->dfs_ch_ssid_scan == 0\n\t\t\t\t&& pmlmeext->sitesurvey_res.ssid_num\n\t\t\t\t&& rtw_is_dfs_ch(ss->ch[ss->channel_idx - 1].hw_value)\n\t\t\t) {\n\t\t\t\tch_set_idx = rtw_chset_search_ch(rfctl->channel_set, ss->ch[ss->channel_idx - 1].hw_value);\n\t\t\t\tif (ch_set_idx != -1 && rfctl->channel_set[ch_set_idx].hidden_bss_cnt\n\t\t\t\t\t&& (!IS_DFS_SLAVE_WITH_RD(rfctl)\n\t\t\t\t\t\t|| rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))\n\t\t\t\t\t\t|| !CH_IS_NON_OCP(&rfctl->channel_set[ch_set_idx]))\n\t\t\t\t) {\n\t\t\t\t\tss->channel_idx--;\n\t\t\t\t\tss->dfs_ch_ssid_scan = 1;\n\t\t\t\t}\n\t\t\t} else\n\t\t\t\tss->dfs_ch_ssid_scan = 0;\n\t\t}\n#endif /* CONFIG_DFS */\n\n\t\tif (ss->channel_idx < ss->ch_num) {\n\t\t\tch = &ss->ch[ss->channel_idx];\n\t\t\tscan_ch = ch->hw_value;\n\n\t\t\t#if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)\n\t\t\tif (IS_ACS_ENABLE(padapter) && rtw_is_acs_passiv_scan(padapter))\n\t\t\t\tscan_type = SCAN_PASSIVE;\n\t\t\telse\n\t\t\t#endif /*CONFIG_RTW_ACS*/\n\t\t\t\tscan_type = (ch->flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) ? SCAN_PASSIVE : SCAN_ACTIVE;\n\t\t}\n\t}\n\n\tif (scan_ch != 0) {\n\t\tnext_state = SCAN_PROCESS;\n\n\t\t#ifdef CONFIG_SCAN_BACKOP\n\t\tif (backop_flags) {\n\t\t\tif (ss->scan_cnt < ss->scan_cnt_max)\n\t\t\t\tss->scan_cnt++;\n\t\t\telse {\n\t\t\t\tmlmeext_assign_scan_backop_flags(pmlmeext, backop_flags);\n\t\t\t\tnext_state = SCAN_BACKING_OP;\n\t\t\t}\n\t\t}\n\t\t#endif\n\n\t} else if (rtw_p2p_findphase_ex_is_needed(pwdinfo)) {\n\t\t/* go p2p listen */\n\t\tnext_state = SCAN_TO_P2P_LISTEN;\n\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\t} else if (rtw_hal_antdiv_before_linked(padapter)) {\n\t\t/* go sw antdiv before link */\n\t\tnext_state = SCAN_SW_ANTDIV_BL;\n#endif\n\t} else {\n\t\tnext_state = SCAN_COMPLETE;\n\n#if defined(DBG_SCAN_SW_ANTDIV_BL)\n\t\t{\n\t\t\t/* for SCAN_SW_ANTDIV_BL state testing */\n\t\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\t\t\tint i;\n\t\t\tbool is_linked = _FALSE;\n\n\t\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\t\tif (rtw_linked_check(dvobj->padapters[i]))\n\t\t\t\t\tis_linked = _TRUE;\n\t\t\t}\n\n\t\t\tif (!is_linked) {\n\t\t\t\tstatic bool fake_sw_antdiv_bl_state = 0;\n\n\t\t\t\tif (fake_sw_antdiv_bl_state == 0) {\n\t\t\t\t\tnext_state = SCAN_SW_ANTDIV_BL;\n\t\t\t\t\tfake_sw_antdiv_bl_state = 1;\n\t\t\t\t} else\n\t\t\t\t\tfake_sw_antdiv_bl_state = 0;\n\t\t\t}\n\t\t}\n#endif /* defined(DBG_SCAN_SW_ANTDIV_BL) */\n\t}\n\n#ifdef CONFIG_SCAN_BACKOP\n\tif (next_state != SCAN_PROCESS)\n\t\tss->scan_cnt = 0;\n#endif\n\n\n#ifdef DBG_FIXED_CHAN\n\tif (pmlmeext->fixed_chan != 0xff && next_state == SCAN_PROCESS)\n\t\tscan_ch = pmlmeext->fixed_chan;\n#endif\n\n\tif (ch)\n\t\t*ch = scan_ch;\n\tif (type)\n\t\t*type = scan_type;\n\n\treturn next_state;\n}\n\nvoid site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType)\n{\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct ss_res *ss = &pmlmeext->sitesurvey_res;\n\tu8 ssid_scan = 0;\n\n#ifdef CONFIG_P2P\n#ifndef CONFIG_IOCTL_CFG80211\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n#endif\n#endif\n\n\tif (survey_channel != 0) {\n\t\tset_channel_bwmode(padapter, survey_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n\n#ifdef CONFIG_DFS\n\t\tif (ScanType == SCAN_PASSIVE && ss->dfs_ch_ssid_scan)\n\t\t\tssid_scan = 1;\n\t\telse\n#endif\n\t\tif (ScanType == SCAN_ACTIVE) {\n#ifdef CONFIG_P2P\n\t\t\t#ifdef CONFIG_IOCTL_CFG80211\n\t\t\tif (rtw_cfg80211_is_p2p_scan(padapter))\n\t\t\t#else\n\t\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN)\n\t\t\t\t|| rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH))\n\t\t\t#endif\n\t\t\t{\n\t\t\t\tissue_probereq_p2p(padapter, NULL);\n\t\t\t\tissue_probereq_p2p(padapter, NULL);\n\t\t\t\tissue_probereq_p2p(padapter, NULL);\n\t\t\t} else\n#endif /* CONFIG_P2P */\n\t\t\t{\n\t\t\t\tif (pmlmeext->sitesurvey_res.scan_mode == SCAN_ACTIVE) {\n\t\t\t\t\t/* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */\n\t\t\t\t\tif (padapter->registrypriv.wifi_spec)\n\t\t\t\t\t\tissue_probereq(padapter, NULL, NULL);\n\t\t\t\t\telse\n\t\t\t\t\t\tissue_probereq_ex(padapter, NULL, NULL, 0, 0, 0, 0);\n\t\t\t\t\tissue_probereq(padapter, NULL, NULL);\n\t\t\t\t}\n\n\t\t\t\tssid_scan = 1;\n\t\t\t}\n\t\t}\n\n\t\tif (ssid_scan) {\n\t\t\tint i;\n\n\t\t\tfor (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) {\n\t\t\t\tif (pmlmeext->sitesurvey_res.ssid[i].SsidLength) {\n\t\t\t\t\t/* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */\n\t\t\t\t\tif (padapter->registrypriv.wifi_spec)\n\t\t\t\t\t\tissue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL);\n\t\t\t\t\telse\n\t\t\t\t\t\tissue_probereq_ex(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL, 0, 0, 0, 0);\n\t\t\t\t\tissue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else {\n\t\t/* channel number is 0 or this channel is not valid. */\n\t\trtw_warn_on(1);\n\t}\n\n\treturn;\n}\n\nvoid survey_done_set_ch_bw(_adapter *padapter)\n{\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tu8 cur_channel = 0;\n\tu8 cur_bwmode;\n\tu8 cur_ch_offset;\n\n#ifdef CONFIG_MCC_MODE\n\tif (!rtw_hal_mcc_change_scan_flag(padapter, &cur_channel, &cur_bwmode, &cur_ch_offset)) {\n\t\tif (0)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" back to AP channel - ch:%u, bw:%u, offset:%u\\n\",\n\t\t\t\tFUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset);\n\t\tgoto exit;\n\t}\n#endif\n\n\tif (rtw_mi_get_ch_setting_union(padapter, &cur_channel, &cur_bwmode, &cur_ch_offset) != 0) {\n\t\tif (0)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" back to linked/linking union - ch:%u, bw:%u, offset:%u\\n\",\n\t\t\t\tFUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset);\n\t} else {\n#ifdef CONFIG_P2P\n\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\t\t_adapter *iface;\n\t\tint i;\n\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tif (!iface)\n\t\t\t\tcontinue;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\t\t\tif (iface->wdinfo.driver_interface == DRIVER_CFG80211 && !adapter_wdev_data(iface)->p2p_enabled)\n\t\t\t\tcontinue;\n#endif\n\n\t\t\tif (rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_LISTEN)) {\n\t\t\t\tcur_channel = iface->wdinfo.listen_channel;\n\t\t\t\tcur_bwmode = CHANNEL_WIDTH_20;\n\t\t\t\tcur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t\t\tif (0)\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" back to \"ADPT_FMT\"'s listen ch - ch:%u, bw:%u, offset:%u\\n\",\n\t\t\t\t\t\tFUNC_ADPT_ARG(padapter), ADPT_ARG(iface), cur_channel, cur_bwmode, cur_ch_offset);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n#endif /* CONFIG_P2P */\n\n\t\tif (cur_channel == 0) {\n\t\t\tcur_channel = pmlmeext->cur_channel;\n\t\t\tcur_bwmode = pmlmeext->cur_bwmode;\n\t\t\tcur_ch_offset = pmlmeext->cur_ch_offset;\n\t\t\tif (0)\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" back to ch:%u, bw:%u, offset:%u\\n\",\n\t\t\t\t\tFUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset);\n\t\t}\n\t}\n#ifdef CONFIG_MCC_MODE\nexit:\n#endif\n\tset_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode);\n}\n\n/**\n * rtw_ps_annc - check and doing ps announcement for all the adapters\n * @adapter: the requesting adapter\n * @ps: power saving or not\n *\n * Returns: 0: no ps announcement is doing. 1: ps announcement is doing\n */\nu8 rtw_ps_annc(_adapter *adapter, bool ps)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\t_adapter *iface;\n\tint i;\n\tu8 ps_anc = 0;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (!iface)\n\t\t\tcontinue;\n\n\t\tif (MLME_IS_STA(iface)) {\n\t\t\tif (is_client_associated_to_ap(iface) == _TRUE) {\n\t\t\t\t/* TODO: TDLS peers */\n\t\t\t\t#ifdef CONFIG_MCC_MODE\n\t\t\t\t/* for two station case */\n\t\t\t\tif (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_NEED_MCC)) {\n\t\t\t\t\tu8 ch = iface->mlmeextpriv.cur_channel;\n\t\t\t\t\tu8 offset = iface->mlmeextpriv.cur_ch_offset;\n\t\t\t\t\tu8 bw = iface->mlmeextpriv.cur_bwmode;\n\n\t\t\t\t\tset_channel_bwmode(iface, ch, offset, bw);\n\t\t\t\t}\n\t\t\t\t#endif /* CONFIG_MCC_MODE */\n\t\t\t\tissue_nulldata(iface, NULL, ps, 3, 500);\n\t\t\t\tps_anc = 1;\n\t\t\t}\n\t\t#ifdef CONFIG_RTW_MESH\n\t\t} else if (MLME_IS_MESH(iface)) {\n\t\t\tif (rtw_mesh_ps_annc(iface, ps))\n\t\t\t\tps_anc = 1;\n\t\t#endif\n\t\t}\n\t}\n\treturn ps_anc;\n}\n\nvoid rtw_leave_opch(_adapter *adapter)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\n#ifdef CONFIG_MCC_MODE\n\tif (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))\n\t\treturn;\n#endif\n\n\t_enter_critical_mutex(&rfctl->offch_mutex, NULL);\n\n\tif (rfctl->offch_state == OFFCHS_NONE) {\n\t\t/* prepare to leave operating channel */\n\t\trfctl->offch_state = OFFCHS_LEAVING_OP;\n\n\t\t/* clear HW TX queue */\n\t\trtw_hal_set_hwreg(adapter, HW_VAR_CHECK_TXBUF, 0);\n\n\t\trtw_hal_macid_sleep_all_used(adapter);\n\n\t\trtw_ps_annc(adapter, 1);\n\n\t\trfctl->offch_state = OFFCHS_LEAVE_OP;\n\t}\n\n\t_exit_critical_mutex(&rfctl->offch_mutex, NULL);\n}\n\nvoid rtw_back_opch(_adapter *adapter)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\n#ifdef CONFIG_MCC_MODE\n\tif (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))\n\t\treturn;\n#endif\n\n\t_enter_critical_mutex(&rfctl->offch_mutex, NULL);\n\n\tif (rfctl->offch_state != OFFCHS_NONE) {\n\t\trfctl->offch_state = OFFCHS_BACKING_OP;\n\t\trtw_hal_macid_wakeup_all_used(adapter);\n\t\trtw_ps_annc(adapter, 0);\n\n\t\trfctl->offch_state = OFFCHS_NONE;\n\t\trtw_mi_os_xmit_schedule(adapter);\n\t}\n\n\t_exit_critical_mutex(&rfctl->offch_mutex, NULL);\n}\n\nvoid sitesurvey_set_igi(_adapter *adapter)\n{\n\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\tstruct ss_res *ss = &mlmeext->sitesurvey_res;\n\tu8 igi;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *pwdinfo = &adapter->wdinfo;\n#endif\n\n\tswitch (mlmeext_scan_state(mlmeext)) {\n\tcase SCAN_ENTER:\n\t\t#ifdef CONFIG_P2P\n\t\t#ifdef CONFIG_IOCTL_CFG80211\n\t\tif (pwdinfo->driver_interface == DRIVER_CFG80211 && rtw_cfg80211_is_p2p_scan(adapter))\n\t\t\tigi = 0x30;\n\t\telse\n\t\t#endif /* CONFIG_IOCTL_CFG80211 */\n\t\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))\n\t\t\tigi = 0x28;\n\t\telse\n\t\t#endif /* CONFIG_P2P */\n\n\t\tif (ss->igi)\n\t\t\tigi = ss->igi;\n\t\telse\n\t\t#if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)\n\t\tif (IS_ACS_ENABLE(adapter) && rtw_is_acs_igi_valid(adapter))\n\t\t\tigi = rtw_acs_get_adv_igi(adapter);\n\t\telse\n\t\t#endif /*CONFIG_RTW_ACS*/\n\t\t\tigi = 0x1e;\n\n\t\t/* record IGI status */\n\t\tss->igi_scan = igi;\n\t\trtw_hal_get_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &ss->igi_before_scan, NULL);\n\n\t\t/* disable DIG and set IGI for scan */\n\t\trtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE);\n\t\tbreak;\n\tcase SCAN_COMPLETE:\n\tcase SCAN_TO_P2P_LISTEN:\n\t\t/* enable DIG and restore IGI */\n\t\tigi = 0xff;\n\t\trtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE);\n\t\tbreak;\n#ifdef CONFIG_SCAN_BACKOP\n\tcase SCAN_BACKING_OP:\n\t\t/* write IGI for op channel when DIG is not enabled */\n\t\todm_write_dig(adapter_to_phydm(adapter), ss->igi_before_scan);\n\t\tbreak;\n\tcase SCAN_LEAVE_OP:\n\t\t/* write IGI for scan when DIG is not enabled */\n\t\todm_write_dig(adapter_to_phydm(adapter), ss->igi_scan);\n\t\tbreak;\n#endif /* CONFIG_SCAN_BACKOP */\n\tdefault:\n\t\trtw_warn_on(1);\n\t\tbreak;\n\t}\n}\nvoid sitesurvey_set_msr(_adapter *adapter, bool enter)\n{\n\tu8 network_type;\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tif (enter) {\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\t\trtw_hal_get_hwreg(adapter, HW_VAR_MEDIA_STATUS, (u8 *)(&pmlmeinfo->hw_media_state));\n#endif\n\t\t/* set MSR to no link state */\n\t\tnetwork_type = _HW_STATE_NOLINK_;\n\t} else {\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\t\tnetwork_type = pmlmeinfo->hw_media_state;\n#else\n\t\tnetwork_type = pmlmeinfo->state & 0x3;\n#endif\n\t}\n\tSet_MSR(adapter, network_type);\n}\n\nvoid sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\n\t_enter_critical_mutex(&rfctl->offch_mutex, NULL);\n\n\tswitch (scan_state) {\n\tcase SCAN_DISABLE:\n\tcase SCAN_BACK_OP:\n\t\trfctl->offch_state = OFFCHS_NONE;\n\t\tbreak;\n\tcase SCAN_START:\n\tcase SCAN_LEAVING_OP:\n\t\trfctl->offch_state = OFFCHS_LEAVING_OP;\n\t\tbreak;\n\tcase SCAN_ENTER:\n\tcase SCAN_LEAVE_OP:\n\t\trfctl->offch_state = OFFCHS_LEAVE_OP;\n\t\tbreak;\n\tcase SCAN_COMPLETE:\n\tcase SCAN_BACKING_OP:\n\t\trfctl->offch_state = OFFCHS_BACKING_OP;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t_exit_critical_mutex(&rfctl->offch_mutex, NULL);\n}\n\nu8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)\n{\n\tstruct sitesurvey_parm\t*pparm = (struct sitesurvey_parm *)pbuf;\n#ifdef DBG_CHECK_FW_PS_STATE\n\tstruct dvobj_priv *dvobj = padapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &dvobj->drv_dbg;\n#endif\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct ss_res *ss = &pmlmeext->sitesurvey_res;\n#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI\n\t\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n#endif\n\tu8 val8;\n\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *pwdinfo = &padapter->wdinfo;\n#endif\n\n#ifdef DBG_CHECK_FW_PS_STATE\n\tif (rtw_fw_ps_state(padapter) == _FAIL) {\n\t\tRTW_INFO(\"scan without leave 32k\\n\");\n\t\tpdbgpriv->dbg_scan_pwr_state_cnt++;\n\t}\n#endif /* DBG_CHECK_FW_PS_STATE */\n\n\t/* increase channel idx */\n\tif (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS))\n\t\tss->channel_idx++;\n\n\t/* update scan state to next state (assigned by previous cmd hdl) */\n\tif (mlmeext_scan_state(pmlmeext) != mlmeext_scan_next_state(pmlmeext))\n\t\tmlmeext_set_scan_state(pmlmeext, mlmeext_scan_next_state(pmlmeext));\n\noperation_by_state:\n\tswitch (mlmeext_scan_state(pmlmeext)) {\n\n\tcase SCAN_DISABLE:\n\t\t/*\n\t\t* SW parameter initialization\n\t\t*/\n\n\t\tsitesurvey_res_reset(padapter, pparm);\n\t\tmlmeext_set_scan_state(pmlmeext, SCAN_START);\n\t\tgoto operation_by_state;\n\n\tcase SCAN_START:\n#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI\n\t\tif ((pwdev_priv->pno_mac_addr[0] != 0xFF)\n\t\t\t    && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE)\n\t    \t    && (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _FALSE)) {\n\t\t\tu16 seq_num;\n\n\t\t\trtw_hal_pno_random_gen_mac_addr(padapter);\n\t\t\trtw_hal_set_hw_mac_addr(padapter, pwdev_priv->pno_mac_addr);\n\t\t\tget_random_bytes(&seq_num, 2);\n\t\t\tpwdev_priv->pno_scan_seq_num = seq_num & 0xFFF;\n\t\t\tRTW_INFO(\"%s pno_scan_seq_num %d\\n\", __func__,\n\t\t\t\t pwdev_priv->pno_scan_seq_num);\n\t\t}\n#endif\n\n\t\t/*\n\t\t* prepare to leave operating channel\n\t\t*/\n\n#ifdef CONFIG_MCC_MODE\n\t\trtw_hal_set_mcc_setting_scan_start(padapter);\n#endif /* CONFIG_MCC_MODE */\n\n\t\t/* apply rx ampdu setting */\n\t\tif (ss->rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID\n\t\t\t|| ss->rx_ampdu_size != RX_AMPDU_SIZE_INVALID)\n\t\t\trtw_rx_ampdu_apply(padapter);\n\n\t\t/* clear HW TX queue before scan */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);\n\n\t\trtw_hal_macid_sleep_all_used(padapter);\n\n\t\t/* power save state announcement */\n\t\tif (rtw_ps_annc(padapter, 1)) {\n\t\t\tmlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT);\n\t\t\tmlmeext_set_scan_next_state(pmlmeext, SCAN_ENTER);\n\t\t\tset_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */\n\t\t} else {\n\t\t\tmlmeext_set_scan_state(pmlmeext, SCAN_ENTER);\n\t\t\tgoto operation_by_state;\n\t\t}\n\n\t\tbreak;\n\n\tcase SCAN_ENTER:\n\t\t/*\n\t\t* HW register and DM setting for enter scan\n\t\t*/\n\n\t\trtw_phydm_ability_backup(padapter);\n\n\t\tsitesurvey_set_igi(padapter);\n\n\t\t/* config dynamic functions for off channel */\n\t\trtw_phydm_func_for_offchannel(padapter);\n\t\t/* set MSR to no link state */\n\t\tsitesurvey_set_msr(padapter, _TRUE);\n\n\t\tval8 = 1; /* under site survey */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));\n\n\t\tmlmeext_set_scan_state(pmlmeext, SCAN_PROCESS);\n\t\tgoto operation_by_state;\n\n\tcase SCAN_PROCESS: {\n\t\tu8 scan_ch;\n\t\tRT_SCAN_TYPE scan_type;\n\t\tu8 next_state;\n\t\tu32 scan_ms;\n\n#ifdef CONFIG_RTW_ACS\n\t\tif (IS_ACS_ENABLE(padapter))\n\t\t\trtw_acs_get_rst(padapter);\n#endif\n\n\t\tnext_state = sitesurvey_pick_ch_behavior(padapter, &scan_ch, &scan_type);\n\n\t\tif (next_state != SCAN_PROCESS) {\n\t\t\tmlmeext_set_scan_state(pmlmeext, next_state);\n\t\t\tgoto operation_by_state;\n\t\t}\n\n\t\t/* still SCAN_PROCESS state */\n\t\t#ifdef DBG_SITESURVEY\n\t\t\t#ifdef CONFIG_P2P\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" %s ch:%u (cnt:%u,idx:%d) at %dms, %c%c%c%c\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter)\n\t\t\t\t, mlmeext_scan_state_str(pmlmeext)\n\t\t\t\t, scan_ch\n\t\t\t\t, pwdinfo->find_phase_state_exchange_cnt, ss->channel_idx\n\t\t\t\t, rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time)\n\t\t\t\t, scan_type ? 'A' : 'P', ss->scan_mode ? 'A' : 'P'\n\t\t\t\t, ss->ssid[0].SsidLength ? 'S' : ' '\n\t\t\t\t, ss->dfs_ch_ssid_scan ? 'D' : ' '\n\t\t\t);\n\t\t\t#else\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" %s ch:%u (idx:%d) at %dms, %c%c%c%c\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter)\n\t\t\t\t, mlmeext_scan_state_str(pmlmeext)\n\t\t\t\t, scan_ch\n\t\t\t\t, ss->channel_idx\n\t\t\t\t, rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time)\n\t\t\t\t, scan_type ? 'A' : 'P', ss->scan_mode ? 'A' : 'P'\n\t\t\t\t, ss->ssid[0].SsidLength ? 'S' : ' '\n\t\t\t\t, ss->dfs_ch_ssid_scan ? 'D' : ' '\n\t\t\t);\n\t\t\t#endif /* CONFIG_P2P */\n\t\t#endif /*DBG_SITESURVEY*/\n#ifdef DBG_FIXED_CHAN\n\t\tif (pmlmeext->fixed_chan != 0xff)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" fixed_chan:%u\\n\", pmlmeext->fixed_chan);\n#endif\n\n\t\tsite_survey(padapter, scan_ch, scan_type);\n\n#if defined(CONFIG_ATMEL_RC_PATCH)\n\t\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t\tscan_ms = 20;\n\t\telse\n\t\t\tscan_ms = 40;\n#else\n\t\t#if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)\n\t\tif (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter))\n\t\t\tscan_ms = rtw_acs_get_adv_st(padapter);\n\t\telse\n\t\t#endif /*CONFIG_RTW_ACS*/\n\t\t\tscan_ms = ss->scan_ch_ms;\n#endif\n\n#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)\n\t\tif (ss->is_sw_antdiv_bl_scan)\n\t\t\tscan_ms = scan_ms / 2;\n#endif\n\n#ifdef CONFIG_RTW_ACS\n\t\tif (IS_ACS_ENABLE(padapter)) {\n\t\t\tif (pparm->token)\n\t\t\t\trtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_IEEE_11K_HIGH);\n\t\t\telse\n\t\t\t\trtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_ACS);\n\t\t}\n#endif\n\n#ifdef CONFIG_BACKGROUND_NOISE_MONITOR\n\t\tif (IS_NM_ENABLE(padapter))\n\t\t\trtw_noise_measure(padapter, scan_ch, _FALSE, 0, scan_ms / 2);\n#endif\n\t\tset_survey_timer(pmlmeext, scan_ms);\n\t\tbreak;\n\t}\n\n#ifdef CONFIG_SCAN_BACKOP\n\tcase SCAN_BACKING_OP: {\n\t\tu8 back_ch, back_bw, back_ch_offset;\n\t\tu8 need_ch_setting_union = _TRUE;\n\n#ifdef CONFIG_MCC_MODE\n\t\tneed_ch_setting_union = rtw_hal_mcc_change_scan_flag(padapter,\n\t\t\t\t&back_ch, &back_bw, &back_ch_offset);\n#endif /* CONFIG_MCC_MODE */\n\n\t\tif (need_ch_setting_union) {\n\t\t\tif (rtw_mi_get_ch_setting_union(padapter, &back_ch, &back_bw, &back_ch_offset) == 0)\n\t\t\t\trtw_warn_on(1);\n\t\t}\n\n\t\t#ifdef DBG_SITESURVEY\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" %s ch:%u, bw:%u, offset:%u at %dms\\n\"\n\t\t\t\t , FUNC_ADPT_ARG(padapter)\n\t\t\t\t , mlmeext_scan_state_str(pmlmeext)\n\t\t\t\t , back_ch, back_bw, back_ch_offset\n\t\t\t\t, rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time)\n\t\t\t\t);\n\t\t#endif /*DBG_SITESURVEY*/\n\t\tset_channel_bwmode(padapter, back_ch, back_ch_offset, back_bw);\n\n\t\tsitesurvey_set_msr(padapter, _FALSE);\n\n\t\tval8 = 0; /* survey done */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));\n\n\t\tif (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) {\n\t\t\tsitesurvey_set_igi(padapter);\n\t\t\trtw_hal_macid_wakeup_all_used(padapter);\n\t\t\trtw_ps_annc(padapter, 0);\n\t\t}\n\n\t\tmlmeext_set_scan_state(pmlmeext, SCAN_BACK_OP);\n\t\tss->backop_time = rtw_get_current_time();\n\n\t\tif (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_TX_RESUME))\n\t\t\trtw_mi_os_xmit_schedule(padapter);\n\n\n\t\tgoto operation_by_state;\n\t}\n\n\tcase SCAN_BACK_OP:\n\t\tif (rtw_get_passing_time_ms(ss->backop_time) >= ss->backop_ms\n\t\t    || pmlmeext->scan_abort\n\t\t   ) {\n\t\t\tmlmeext_set_scan_state(pmlmeext, SCAN_LEAVING_OP);\n\t\t\tgoto operation_by_state;\n\t\t}\n\t\tset_survey_timer(pmlmeext, 50);\n\t\tbreak;\n\n\tcase SCAN_LEAVING_OP:\n\t\t/*\n\t\t * prepare to leave operating channel\n\t\t */\n\n\t\t/* clear HW TX queue before scan */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);\n\n\t\trtw_hal_macid_sleep_all_used(padapter);\n\t\tif (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)\n\t\t\t&& rtw_ps_annc(padapter, 1)\n\t\t) {\n\t\t\tmlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT);\n\t\t\tmlmeext_set_scan_next_state(pmlmeext, SCAN_LEAVE_OP);\n\t\t\tset_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */\n\t\t} else {\n\t\t\tmlmeext_set_scan_state(pmlmeext, SCAN_LEAVE_OP);\n\t\t\tgoto operation_by_state;\n\t\t}\n\n\t\tbreak;\n\n\tcase SCAN_LEAVE_OP:\n\t\t/*\n\t\t* HW register and DM setting for enter scan\n\t\t*/\n\n\t\tif (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC))\n\t\t\tsitesurvey_set_igi(padapter);\n\n\t\tsitesurvey_set_msr(padapter, _TRUE);\n\n\t\tval8 = 1; /* under site survey */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));\n\n\t\tmlmeext_set_scan_state(pmlmeext, SCAN_PROCESS);\n\t\tgoto operation_by_state;\n\n#endif /* CONFIG_SCAN_BACKOP */\n\n#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)\n\tcase SCAN_SW_ANTDIV_BL:\n\t\t/*\n\t\t* 20100721\n\t\t* For SW antenna diversity before link, it needs to switch to another antenna and scan again.\n\t\t* It compares the scan result and select better one to do connection.\n\t\t*/\n\t\tss->bss_cnt = 0;\n\t\tss->channel_idx = 0;\n\t\tss->is_sw_antdiv_bl_scan = 1;\n\n\t\tmlmeext_set_scan_next_state(pmlmeext, SCAN_PROCESS);\n\t\tset_survey_timer(pmlmeext, ss->scan_ch_ms);\n\t\tbreak;\n#endif\n\n#ifdef CONFIG_P2P\n\tcase SCAN_TO_P2P_LISTEN:\n\t\t/*\n\t\t* Set the P2P State to the listen state of find phase\n\t\t* and set the current channel to the listen channel\n\t\t*/\n\t\tset_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_LISTEN);\n\n\t\t/* turn on phy-dynamic functions */\n\t\trtw_phydm_ability_restore(padapter);\n\n\t\tsitesurvey_set_igi(padapter);\n\n\t\tmlmeext_set_scan_state(pmlmeext, SCAN_P2P_LISTEN);\n\t\t_set_timer(&pwdinfo->find_phase_timer, (u32)((u32)pwdinfo->listen_dwell * 100));\n\t\tbreak;\n\n\tcase SCAN_P2P_LISTEN:\n\t\tmlmeext_set_scan_state(pmlmeext, SCAN_PROCESS);\n\t\tss->channel_idx = 0;\n\t\tgoto operation_by_state;\n#endif /* CONFIG_P2P */\n\n\tcase SCAN_COMPLETE:\n#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI\n\t\trtw_hal_set_hw_mac_addr(padapter, adapter_mac_addr(padapter));\n#endif\n#ifdef CONFIG_P2P\n\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN)\n\t\t    || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH)\n\t\t   ) {\n#ifdef CONFIG_CONCURRENT_MODE\n\t\t\tif (pwdinfo->driver_interface == DRIVER_WEXT) {\n\t\t\t\tif (rtw_mi_check_status(padapter, MI_LINKED))\n\t\t\t\t\t_set_timer(&pwdinfo->ap_p2p_switch_timer, 500);\n\t\t\t}\n#endif\n\n\t\t\trtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));\n\t\t}\n\t\trtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);\n#endif /* CONFIG_P2P */\n\n\t\t/* switch channel */\n\t\tsurvey_done_set_ch_bw(padapter);\n\n\t\tsitesurvey_set_msr(padapter, _FALSE);\n\n\t\tval8 = 0; /* survey done */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));\n\n\t\t/* turn on phy-dynamic functions */\n\t\trtw_phydm_ability_restore(padapter);\n\n\t\tsitesurvey_set_igi(padapter);\n\n#ifdef CONFIG_MCC_MODE\n\t\t/* start MCC fail, then tx null data */\n\t\tif (!rtw_hal_set_mcc_setting_scan_complete(padapter))\n#endif\n\t\t{\n\t\t\trtw_hal_macid_wakeup_all_used(padapter);\n\t\t\trtw_ps_annc(padapter, 0);\n\t\t}\n\n\t\t/* apply rx ampdu setting */\n\t\trtw_rx_ampdu_apply(padapter);\n\n\t\tmlmeext_set_scan_state(pmlmeext, SCAN_DISABLE);\n\n\t\treport_surveydone_event(padapter);\n#ifdef CONFIG_RTW_ACS\n\t\tif (IS_ACS_ENABLE(padapter))\n\t\t\trtw_acs_select_best_chan(padapter);\n#endif\n\n#if defined(CONFIG_BACKGROUND_NOISE_MONITOR) && defined(DBG_NOISE_MONITOR)\n\t\tif (IS_NM_ENABLE(padapter))\n\t\t\trtw_noise_info_dump(RTW_DBGDUMP, padapter);\n#endif\n\t\tissue_action_BSSCoexistPacket(padapter);\n\t\tissue_action_BSSCoexistPacket(padapter);\n\t\tissue_action_BSSCoexistPacket(padapter);\n\n#ifdef CONFIG_RTW_80211K\n\t\tif (ss->token)\n\t\t\trm_post_event(padapter, ss->token, RM_EV_survey_done);\n#endif /* CONFIG_RTW_80211K */\n\n\t\tbreak;\n\t}\n\n\treturn H2C_SUCCESS;\n}\n\nu8 setauth_hdl(_adapter *padapter, unsigned char *pbuf)\n{\n\tstruct setauth_parm\t\t*pparm = (struct setauth_parm *)pbuf;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tif (pparm->mode < 4)\n\t\tpmlmeinfo->auth_algo = pparm->mode;\n\n\treturn\tH2C_SUCCESS;\n}\n\n/*\nSEC CAM Entry format (32 bytes)\nDW0 - MAC_ADDR[15:0] | Valid[15] | MFB[14:8] | RSVD[7]  | GK[6] | MIC_KEY[5] | SEC_TYPE[4:2] | KID[1:0]\nDW0 - MAC_ADDR[15:0] | Valid[15] |RSVD[14:9] | RPT_MODE[8] | SPP_MODE[7]  | GK[6] | MIC_KEY[5] | SEC_TYPE[4:2] | KID[1:0] (92E/8812A/8814A)\nDW1 - MAC_ADDR[47:16]\nDW2 - KEY[31:0]\nDW3 - KEY[63:32]\nDW4 - KEY[95:64]\nDW5 - KEY[127:96]\nDW6 - RSVD\nDW7 - RSVD\n*/\n\n/*Set WEP key or Group Key*/\nu8 setkey_hdl(_adapter *padapter, u8 *pbuf)\n{\n\tu16\tctrl = 0;\n\ts16 cam_id = 0;\n\tstruct setkey_parm\t\t*pparm = (struct setkey_parm *)pbuf;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tunsigned char null_addr[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};\n\tu8 *addr;\n\tbool used = _FALSE;\n\n\t/* main tx key for wep. */\n\tif (pparm->set_tx)\n\t\tpmlmeinfo->key_index = pparm->keyid;\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE))\n\t\tcam_id = rtw_iface_bcmc_id_get(padapter);\n\telse\n#endif\n\t\tcam_id = rtw_camid_alloc(padapter, NULL, pparm->keyid, 1, &used);\n\n\tif (cam_id < 0)\n\t\tgoto enable_mc;\n\n#ifndef CONFIG_CONCURRENT_MODE\n\tif (cam_id >= 0 && cam_id <= 3) {\n\t\t/* default key camid */\n\t\taddr = null_addr;\n\t} else\n#endif\n\t{\n\t\t/* not default key camid */\n\t\tif (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) {\n\t\t\t/* group TX, force sec cam entry_id */\n\t\t\taddr = adapter_mac_addr(padapter);\n\t\t} else {\n\t\t\t/* group RX, searched by A2 (TA) */\n\t\t\taddr = get_bssid(&padapter->mlmepriv);\n\t\t}\n\t}\n\n#ifdef CONFIG_LPS_PG\n\tif (adapter_to_pwrctl(padapter)->lps_level == LPS_PG)\n\t\tLPS_Leave(padapter, \"SET_KEY\");\n#endif\n\n\t/* cam entry searched is pairwise key */\n\tif (used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _FALSE) {\n\t\ts16 camid_clr;\n\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" group key with \"MAC_FMT\" id:%u the same key id as pairwise key\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(addr), pparm->keyid);\n\n\t\t/* HW has problem to distinguish this group key with existing pairwise key, stop HW enc and dec for BMC */\n\t\trtw_camctl_set_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL);\n\n\t\t/* clear group key */\n\t\twhile ((camid_clr = rtw_camid_search(padapter, addr, -1, 1)) >= 0) {\n\t\t\tRTW_PRINT(\"clear group key for addr:\"MAC_FMT\", camid:%d\\n\", MAC_ARG(addr), camid_clr);\n\t\t\tclear_cam_entry(padapter, camid_clr);\n\t\t\trtw_camid_free(padapter, camid_clr);\n\t\t}\n\n\t\tgoto enable_mc;\n\t}\n\n\tctrl = BIT(15) | BIT(6) | ((pparm->algorithm) << 2) | pparm->keyid;\n\n\tRTW_PRINT(\"set group key camid:%d, addr:\"MAC_FMT\", kid:%d, type:%s\\n\"\n\t\t, cam_id, MAC_ARG(addr), pparm->keyid, security_type_str(pparm->algorithm));\n\n\twrite_cam(padapter, cam_id, ctrl, addr, pparm->key);\n\n\t/* if ((cam_id > 3) && (((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)))*/\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) {\n\t\tif (is_wep_enc(pparm->algorithm)) {\n\t\t\tpadapter->securitypriv.dot11Def_camid[pparm->keyid] = cam_id;\n\t\t\tpadapter->securitypriv.dot118021x_bmc_cam_id =\n\t\t\t\tpadapter->securitypriv.dot11Def_camid[padapter->securitypriv.dot11PrivacyKeyIndex];\n\t\t\tRTW_PRINT(\"wep group key - force camid:%d\\n\", padapter->securitypriv.dot118021x_bmc_cam_id);\n\t\t} else {\n\t\t\t/*u8 org_cam_id = padapter->securitypriv.dot118021x_bmc_cam_id;*/\n\n\t\t\t/*force GK's cam id*/\n\t\t\tpadapter->securitypriv.dot118021x_bmc_cam_id = cam_id;\n\n\t\t\t/* for GTK rekey\n\t\t\tif ((org_cam_id != INVALID_SEC_MAC_CAM_ID) &&\n\t\t\t\t(org_cam_id != cam_id)) {\n\t\t\t\tRTW_PRINT(\"clear group key for addr:\"MAC_FMT\", org_camid:%d new_camid:%d\\n\", MAC_ARG(addr), org_cam_id, cam_id);\n\t\t\t\tclear_cam_entry(padapter, org_cam_id);\n\t\t\t\trtw_camid_free(padapter, org_cam_id);\n\t\t\t}*/\n\t\t}\n\t}\n#endif\n\n\n#ifndef CONFIG_CONCURRENT_MODE\n\tif (cam_id >= 0 && cam_id <= 3)\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8 *)_TRUE);\n#endif\n\n\t/* 8814au should set both broadcast and unicast CAM entry for WEP key in STA mode */\n\tif (is_wep_enc(pparm->algorithm) && check_mlmeinfo_state(pmlmeext, WIFI_FW_STATION_STATE) &&\n\t    _rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_BMC)) {\n\t\tstruct set_stakey_parm\tsta_pparm;\n\n\t\t_rtw_memset(&sta_pparm, 0, sizeof(struct set_stakey_parm));\n\t\tsta_pparm.algorithm = pparm->algorithm;\n\t\tsta_pparm.keyid = pparm->keyid;\n\t\t_rtw_memcpy(sta_pparm.key, pparm->key, 16);\n\t\t_rtw_memcpy(sta_pparm.addr, get_bssid(&padapter->mlmepriv), ETH_ALEN);\n\t\tset_stakey_hdl(padapter, (u8 *)&sta_pparm);\n\t}\n\nenable_mc:\n\t/* allow multicast packets to driver */\n\trtw_hal_set_hwreg(padapter, HW_VAR_ON_RCR_AM, null_addr);\n\n\treturn H2C_SUCCESS;\n}\n\nvoid rtw_ap_wep_pk_setting(_adapter *adapter, struct sta_info *psta)\n{\n\tstruct security_priv *psecuritypriv = &(adapter->securitypriv);\n\tstruct set_stakey_parm\tsta_pparm;\n\tsint keyid;\n\n\tif (!is_wep_enc(psecuritypriv->dot11PrivacyAlgrthm))\n\t\treturn;\n\n\tfor (keyid = 0; keyid < 4; keyid++) {\n\t\tif ((psecuritypriv->key_mask & BIT(keyid)) && (keyid == psecuritypriv->dot11PrivacyKeyIndex)) {\n\t\t\tsta_pparm.algorithm = psecuritypriv->dot11PrivacyAlgrthm;\n\t\t\tsta_pparm.keyid = keyid;\n\t\t\tsta_pparm.gk = 0;\n\t\t\t_rtw_memcpy(sta_pparm.key, &(psecuritypriv->dot11DefKey[keyid].skey[0]), 16);\n\t\t\t_rtw_memcpy(sta_pparm.addr, psta->cmn.mac_addr, ETH_ALEN);\n\n\t\t\tRTW_PRINT(FUNC_ADPT_FMT\"set WEP - PK with \"MAC_FMT\" keyid:%u\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr), keyid);\n\n\t\t\tset_stakey_hdl(adapter, (u8 *)&sta_pparm);\n\t\t}\n\t}\n}\n\nu8 set_stakey_hdl(_adapter *padapter, u8 *pbuf)\n{\n\tu16 ctrl = 0;\n\ts16 cam_id = 0;\n\tbool used;\n\tu8 ret = H2C_SUCCESS;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct set_stakey_parm\t*pparm = (struct set_stakey_parm *)pbuf;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct sta_info *psta;\n\n\tif (pparm->algorithm == _NO_PRIVACY_)\n\t\tgoto write_to_cam;\n\n\tpsta = rtw_get_stainfo(pstapriv, pparm->addr);\n\tif (!psta) {\n\t\tRTW_PRINT(\"%s sta:\"MAC_FMT\" not found\\n\", __func__, MAC_ARG(pparm->addr));\n\t\tret = H2C_REJECTED;\n\t\tgoto exit;\n\t}\n\n\tpmlmeinfo->enc_algo = pparm->algorithm;\n\n\tcam_id = rtw_camid_alloc(padapter, psta, pparm->keyid, pparm->gk, &used);\n\tif (cam_id < 0)\n\t\tgoto exit;\n\n#ifdef CONFIG_LPS_PG\n\tif (adapter_to_pwrctl(padapter)->lps_level == LPS_PG)\n\t\tLPS_Leave(padapter, \"SET_KEY\");\n#endif\n\n\t/* cam entry searched is group key when setting pariwise key */\n\tif (!pparm->gk && used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _TRUE) {\n\t\ts16 camid_clr;\n\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" pairwise key with \"MAC_FMT\" id:%u the same key id as group key\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(pparm->addr), pparm->keyid);\n\n\t\t/* HW has problem to distinguish this pairwise key with existing group key, stop HW enc and dec for BMC */\n\t\trtw_camctl_set_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL);\n\n\t\t/* clear group key */\n\t\twhile ((camid_clr = rtw_camid_search(padapter, pparm->addr, -1, 1)) >= 0) {\n\t\t\tRTW_PRINT(\"clear group key for addr:\"MAC_FMT\", camid:%d\\n\", MAC_ARG(pparm->addr), camid_clr);\n\t\t\tclear_cam_entry(padapter, camid_clr);\n\t\t\trtw_camid_free(padapter, camid_clr);\n\t\t}\n\t}\n\nwrite_to_cam:\n\tif (pparm->algorithm == _NO_PRIVACY_) {\n\t\twhile ((cam_id = rtw_camid_search(padapter, pparm->addr, -1, -1)) >= 0) {\n\t\t\tRTW_PRINT(\"clear key for addr:\"MAC_FMT\", camid:%d\\n\", MAC_ARG(pparm->addr), cam_id);\n\t\t\tclear_cam_entry(padapter, cam_id);\n\t\t\trtw_camid_free(padapter, cam_id);\n\t\t}\n\t} else {\n\t\tRTW_PRINT(\"set %s key camid:%d, addr:\"MAC_FMT\", kid:%d, type:%s\\n\"\n\t\t\t, pparm->gk ? \"group\" : \"pairwise\"\n\t\t\t, cam_id, MAC_ARG(pparm->addr), pparm->keyid, security_type_str(pparm->algorithm));\n\t\tctrl = BIT(15) | ((pparm->algorithm) << 2) | pparm->keyid;\n\t\tif (pparm->gk)\n\t\t\tctrl |= BIT(6);\n\t\twrite_cam(padapter, cam_id, ctrl, pparm->addr, pparm->key);\n\t}\n\tret = H2C_SUCCESS_RSP;\n\nexit:\n\treturn ret;\n}\n\nu8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf)\n{\n\tstruct addBaReq_parm\t*pparm = (struct addBaReq_parm *)pbuf;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tstruct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, pparm->addr);\n\n\tif (!psta)\n\t\treturn\tH2C_SUCCESS;\n\n#ifdef CONFIG_80211N_HT\n\tif (((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && (pmlmeinfo->HT_enable)) ||\n\t    ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {\n\t\t/* pmlmeinfo->ADDBA_retry_count = 0; */\n\t\t/* pmlmeinfo->candidate_tid_bitmap |= (0x1 << pparm->tid);\t\t */\n\t\t/* psta->htpriv.candidate_tid_bitmap |= BIT(pparm->tid); */\n\t\tissue_addba_req(padapter, pparm->addr, (u8)pparm->tid);\n\t\t_set_timer(&psta->addba_retry_timer, ADDBA_TO);\n\t}\n#ifdef CONFIG_TDLS\n\telse if ((psta->tdls_sta_state & TDLS_LINKED_STATE) &&\n\t\t (psta->htpriv.ht_option == _TRUE) &&\n\t\t (psta->htpriv.ampdu_enable == _TRUE)) {\n\t\tissue_addba_req(padapter, pparm->addr, (u8)pparm->tid);\n\t\t_set_timer(&psta->addba_retry_timer, ADDBA_TO);\n\t}\n#endif /* CONFIG */\n\telse\n\t\tpsta->htpriv.candidate_tid_bitmap &= ~BIT(pparm->tid);\n#endif /* CONFIG_80211N_HT */\n\treturn\tH2C_SUCCESS;\n}\n\n\nu8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf)\n{\n\tstruct addBaRsp_parm *pparm = (struct addBaRsp_parm *)pbuf;\n\tstruct recv_reorder_ctrl *preorder_ctrl;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct sta_info *psta;\n\tu8 ret = _TRUE;\n\n\tpsta = rtw_get_stainfo(pstapriv, pparm->addr);\n\tif (!psta)\n\t\tgoto exit;\n\n\tpreorder_ctrl = &psta->recvreorder_ctrl[pparm->tid];\n\tret = issue_addba_rsp_wait_ack(padapter, pparm->addr, pparm->tid, pparm->status, pparm->size, 3, 50);\n\n#ifdef CONFIG_UPDATE_INDICATE_SEQ_WHILE_PROCESS_ADDBA_REQ\n\t/* status = 0 means accept this addba req, so update indicate seq = start_seq under this compile flag */\n\tif (pparm->status == 0) {\n\t\tpreorder_ctrl->indicate_seq = pparm->start_seq;\n\t\t#ifdef DBG_RX_SEQ\n\t\tRTW_INFO(\"DBG_RX_SEQ \"FUNC_ADPT_FMT\" tid:%u SN_UPDATE indicate_seq:%d, start_seq:%d\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pparm->start_seq);\n\t\t#endif\n\t}\n#else\n\trtw_set_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack);\n\t#ifdef DBG_RX_SEQ\n\tRTW_INFO(\"DBG_RX_SEQ \"FUNC_ADPT_FMT\" tid:%u SN_CLEAR indicate_seq:%d, start_seq:%d preorder_ctrl->rec_abba_rsp_ack =%lu \\n\"\n\t\t, FUNC_ADPT_ARG(padapter)\n\t\t, preorder_ctrl->tid\n\t\t, preorder_ctrl->indicate_seq\n\t\t, pparm->start_seq\n\t\t,preorder_ctrl->rec_abba_rsp_ack\n\t\t);\n\t#endif\n#endif\n\n\t/*\n\t  * status = 0 means accept this addba req\n\t  * status = 37 means reject this addba req\n\t  */\n\tif (pparm->status == 0) {\n\t\tpreorder_ctrl->enable = _TRUE;\n\t\tpreorder_ctrl->ampdu_size = pparm->size;\n\t} else if (pparm->status == 37)\n\t\tpreorder_ctrl->enable = _FALSE;\n\nexit:\n\treturn H2C_SUCCESS;\n}\n\nu8 chk_bmc_sleepq_cmd(_adapter *padapter)\n{\n\tstruct cmd_obj *ph2c;\n\tstruct cmd_priv *pcmdpriv = &(padapter->cmdpriv);\n\tu8 res = _SUCCESS;\n\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tinit_h2fwcmd_w_parm_no_parm_rsp(ph2c, GEN_CMD_CODE(_ChkBMCSleepq));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\n\n\treturn res;\n}\n\nu8 set_tx_beacon_cmd(_adapter *padapter, u8 flags)\n{\n\tstruct cmd_obj\t*ph2c;\n\tstruct Tx_Beacon_param\t*ptxBeacon_parm;\n\tstruct cmd_priv\t*pcmdpriv = &(padapter->cmdpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct submit_ctx sctx;\n\tu8\tres = _SUCCESS;\n\tint len_diff = 0;\n\n\t/*prepare cmd parameter*/\n\tptxBeacon_parm = (struct Tx_Beacon_param *)rtw_zmalloc(sizeof(struct Tx_Beacon_param));\n\tif (ptxBeacon_parm == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t_rtw_memcpy(&(ptxBeacon_parm->network), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX));\n\n\tlen_diff = update_hidden_ssid(\n\t\t\t   ptxBeacon_parm->network.IEs + _BEACON_IE_OFFSET_\n\t\t   , ptxBeacon_parm->network.IELength - _BEACON_IE_OFFSET_\n\t\t\t   , pmlmeinfo->hidden_ssid_mode\n\t\t   );\n\tptxBeacon_parm->network.IELength += len_diff;\n\n\n\t/* need enqueue, prepare cmd_obj and enqueue */\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\trtw_mfree((u8 *)ptxBeacon_parm, sizeof(*ptxBeacon_parm));\n\t\tgoto exit;\n\t}\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, ptxBeacon_parm, GEN_CMD_CODE(_TX_Beacon));\n\n\tif (flags & RTW_CMDF_WAIT_ACK) {\n\t\tph2c->sctx = &sctx;\n\t\trtw_sctx_init(&sctx, 10 * 1000);\n\t}\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\n\tif (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {\n\t\trtw_sctx_wait(&sctx, __func__);\n\t\t_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t\tif (sctx.status == RTW_SCTX_SUBMITTED)\n\t\t\tph2c->sctx = NULL;\n\t\t_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);\n\t}\n\t\n\nexit:\n\n\n\treturn res;\n}\n\n\nu8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf)\n{\n\tu8 evt_code, evt_seq;\n\tu16 evt_sz;\n\tuint\t*peventbuf;\n\tvoid (*event_callback)(_adapter *dev, u8 *pbuf);\n\tstruct evt_priv *pevt_priv = &(padapter->evtpriv);\n\n\tif (pbuf == NULL)\n\t\tgoto _abort_event_;\n\n\tpeventbuf = (uint *)pbuf;\n\tevt_sz = (u16)(*peventbuf & 0xffff);\n\tevt_seq = (u8)((*peventbuf >> 24) & 0x7f);\n\tevt_code = (u8)((*peventbuf >> 16) & 0xff);\n\n\n#ifdef CHECK_EVENT_SEQ\n\t/* checking event sequence...\t\t */\n\tif (evt_seq != (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f)) {\n\n\t\tpevt_priv->event_seq = (evt_seq + 1) & 0x7f;\n\n\t\tgoto _abort_event_;\n\t}\n#endif\n\n\t/* checking if event code is valid */\n\tif (evt_code >= MAX_C2HEVT) {\n\t\tgoto _abort_event_;\n\t}\n\n\t/* checking if event size match the event parm size\t */\n\tif ((wlanevents[evt_code].parmsize != 0) &&\n\t    (wlanevents[evt_code].parmsize != evt_sz)) {\n\n\t\tgoto _abort_event_;\n\n\t}\n\n\tATOMIC_INC(&pevt_priv->event_seq);\n\n\tpeventbuf += 2;\n\n\tif (peventbuf) {\n\t\tevent_callback = wlanevents[evt_code].event_callback;\n\t\tevent_callback(padapter, (u8 *)peventbuf);\n\n\t\tpevt_priv->evt_done_cnt++;\n\t}\n\n\n_abort_event_:\n\n\n\treturn H2C_SUCCESS;\n\n}\n\nu8 h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf)\n{\n\tif (!pbuf)\n\t\treturn H2C_PARAMETERS_ERROR;\n\n\treturn H2C_SUCCESS;\n}\n\nu8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf)\n{\n#ifdef CONFIG_AP_MODE\n\t_irqL irqL;\n\tstruct sta_info *psta_bmc;\n\t_list\t*xmitframe_plist, *xmitframe_phead;\n\tstruct xmit_frame *pxmitframe = NULL;\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tstruct sta_priv  *pstapriv = &padapter->stapriv;\n\n\t/* for BC/MC Frames */\n\tpsta_bmc = rtw_get_bcmc_stainfo(padapter);\n\tif (!psta_bmc)\n\t\treturn H2C_SUCCESS;\n\n\tif ((rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) && (psta_bmc->sleepq_len > 0)) {\n#ifndef CONFIG_PCI_HCI\n\t\trtw_msleep_os(10);/* 10ms, ATIM(HIQ) Windows */\n#endif\n\t\t/* _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); */\n\t\t_enter_critical_bh(&pxmitpriv->lock, &irqL);\n\n\t\txmitframe_phead = get_list_head(&psta_bmc->sleep_q);\n\t\txmitframe_plist = get_next(xmitframe_phead);\n\n\t\twhile ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {\n\t\t\tpxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);\n\n\t\t\txmitframe_plist = get_next(xmitframe_plist);\n\n\t\t\trtw_list_delete(&pxmitframe->list);\n\n\t\t\tpsta_bmc->sleepq_len--;\n\t\t\tif (psta_bmc->sleepq_len > 0)\n\t\t\t\tpxmitframe->attrib.mdata = 1;\n\t\t\telse\n\t\t\t\tpxmitframe->attrib.mdata = 0;\n\n\t\t\tpxmitframe->attrib.triggered = 1;\n\n\t\t\tif (xmitframe_hiq_filter(pxmitframe) == _TRUE)\n\t\t\t\tpxmitframe->attrib.qsel = QSLT_HIGH;/* HIQ */\n\n#if 0\n\t\t\t_exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);\n\t\t\tif (rtw_hal_xmit(padapter, pxmitframe) == _TRUE)\n\t\t\t\trtw_os_xmit_complete(padapter, pxmitframe);\n\t\t\t_enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL);\n#endif\n\t\t\trtw_hal_xmitframe_enqueue(padapter, pxmitframe);\n\t\t}\n\n\t\t/* _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); */\n\t\t_exit_critical_bh(&pxmitpriv->lock, &irqL);\n\n\t\tif (rtw_get_intf_type(padapter) != RTW_PCIE) {\n\t\t\t/* check hi queue and bmc_sleepq */\n\t\t\trtw_chk_hi_queue_cmd(padapter);\n\t\t}\n\t}\n#endif\n\n\treturn H2C_SUCCESS;\n}\n\nu8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf)\n{\n\t/*RTW_INFO(FUNC_ADPT_FMT, FUNC_ADPT_ARG(padapter));*/\n#ifdef CONFIG_SWTIMER_BASED_TXBCN\n\n\ttx_beacon_handlder(padapter->dvobj);\n\n#else\n\n\tif (send_beacon(padapter) == _FAIL) {\n\t\tRTW_INFO(\"issue_beacon, fail!\\n\");\n\t\treturn H2C_PARAMETERS_ERROR;\n\t}\n\n\t/* tx bc/mc frames after update TIM */\n\tchk_bmc_sleepq_hdl(padapter, NULL);\n#endif\n\n\treturn H2C_SUCCESS;\n}\n\n/*\n* according to channel\n* add/remove WLAN_BSSID_EX.IEs's ERP ie\n* set WLAN_BSSID_EX.SupportedRates\n* update WLAN_BSSID_EX.IEs's Supported Rate and Extended Supported Rate ie\n*/\nvoid change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch)\n{\n\tu8\tnetwork_type, rate_len, total_rate_len, remainder_rate_len;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tu8\terpinfo = 0x4;\n\n\tif (ch >= 36) {\n\t\tnetwork_type = WIRELESS_11A;\n\t\ttotal_rate_len = IEEE80211_NUM_OFDM_RATESLEN;\n\t\trtw_remove_bcn_ie(padapter, pnetwork, _ERPINFO_IE_);\n\t\t#ifdef CONFIG_80211AC_VHT\n\t\t/* if channel in 5G band, then add vht ie . */\n\t\tif ((pmlmepriv->htpriv.ht_option == _TRUE)\n\t\t\t&& REGSTY_IS_11AC_ENABLE(&padapter->registrypriv)\n\t\t\t&& is_supported_vht(padapter->registrypriv.wireless_mode)\n\t\t\t&& (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))\n\t\t) {\n\t\t\tif (REGSTY_IS_11AC_AUTO(&padapter->registrypriv)\n\t\t\t\t|| pmlmepriv->ori_vht_en)\n\t\t\t\trtw_vht_ies_attach(padapter, pnetwork);\n\t\t}\n\t\t#endif\n\t} else {\n\t\tnetwork_type = 0;\n\t\ttotal_rate_len = 0;\n\t\tif (padapter->registrypriv.wireless_mode & WIRELESS_11B) {\n\t\t\tnetwork_type |= WIRELESS_11B;\n\t\t\ttotal_rate_len += IEEE80211_CCK_RATE_LEN;\n\t\t}\n\t\tif (padapter->registrypriv.wireless_mode & WIRELESS_11G) {\n\t\t\tnetwork_type |= WIRELESS_11G;\n\t\t\ttotal_rate_len += IEEE80211_NUM_OFDM_RATESLEN;\n\t\t}\n\t\trtw_add_bcn_ie(padapter, pnetwork, _ERPINFO_IE_, &erpinfo, 1);\n\t\t#ifdef CONFIG_80211AC_VHT\n\t\trtw_vht_ies_detach(padapter, pnetwork);\n\t\t#endif\n\t}\n\n\trtw_set_supported_rate(pnetwork->SupportedRates, network_type);\n\n\tUpdateBrateTbl(padapter, pnetwork->SupportedRates);\n\n\tif (total_rate_len > 8) {\n\t\trate_len = 8;\n\t\tremainder_rate_len = total_rate_len - 8;\n\t} else {\n\t\trate_len = total_rate_len;\n\t\tremainder_rate_len = 0;\n\t}\n\n\trtw_add_bcn_ie(padapter, pnetwork, _SUPPORTEDRATES_IE_, pnetwork->SupportedRates, rate_len);\n\n\tif (remainder_rate_len)\n\t\trtw_add_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_, (pnetwork->SupportedRates + 8), remainder_rate_len);\n\telse\n\t\trtw_remove_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_);\n\n\tpnetwork->Length = get_WLAN_BSSID_EX_sz(pnetwork);\n}\n\nvoid rtw_join_done_chk_ch(_adapter *adapter, int join_res)\n{\n#define DUMP_ADAPTERS_STATUS 0\n\n\tstruct dvobj_priv *dvobj;\n\t_adapter *iface;\n\tstruct mlme_priv *mlme;\n\tstruct mlme_ext_priv *mlmeext;\n\tu8 u_ch, u_offset, u_bw;\n\tint i;\n\n\tdvobj = adapter_to_dvobj(adapter);\n\n\tif (DUMP_ADAPTERS_STATUS) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" enter\\n\", FUNC_ADPT_ARG(adapter));\n\t\tdump_adapters_status(RTW_DBGDUMP , dvobj);\n\t}\n\n\tif (join_res >= 0) {\n\n#ifdef CONFIG_MCC_MODE\n\t\t/* MCC setting success, don't go to ch union process */\n\t\tif (rtw_hal_set_mcc_setting_join_done_chk_ch(adapter))\n\t\t\treturn;\n#endif /* CONFIG_MCC_MODE */\n\n\t\tif (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset) <= 0) {\n\t\t\tdump_adapters_status(RTW_DBGDUMP , dvobj);\n\t\t\trtw_warn_on(1);\n\t\t}\n\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tmlme = &iface->mlmepriv;\n\t\t\tmlmeext = &iface->mlmeextpriv;\n\n\t\t\tif (!iface || iface == adapter)\n\t\t\t\tcontinue;\n\n\t\t\tif ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))\n\t\t\t\t&& check_fwstate(mlme, WIFI_ASOC_STATE)\n\t\t\t) {\n\t\t\t\tu8 ori_ch, ori_bw, ori_offset;\n\t\t\t\tbool is_grouped = rtw_is_chbw_grouped(u_ch, u_bw, u_offset\n\t\t\t\t\t, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);\n\n\t\t\t\tif (is_grouped == _FALSE) {\n\t\t\t\t\t/* handle AP which need to switch ch setting */\n\n\t\t\t\t\tori_ch = mlmeext->cur_channel;\n\t\t\t\t\tori_bw = mlmeext->cur_bwmode;\n\t\t\t\t\tori_offset = mlmeext->cur_ch_offset;\n\n\t\t\t\t\t/* restore original bw, adjust bw by registry setting on target ch */\n\t\t\t\t\tmlmeext->cur_bwmode = mlme->ori_bw;\n\t\t\t\t\tmlmeext->cur_channel = u_ch;\n\t\t\t\t\trtw_adjust_chbw(iface, mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset);\n\t\t\t\t\t#ifdef CONFIG_RTW_MESH\n\t\t\t\t\tif (MLME_IS_MESH(iface))\n\t\t\t\t\t\trtw_mesh_adjust_chbw(mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset);\n\t\t\t\t\t#endif\n\n\t\t\t\t\trtw_chset_sync_chbw(adapter_to_chset(adapter)\n\t\t\t\t\t\t, &mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset\n\t\t\t\t\t\t, &u_ch, &u_bw, &u_offset);\n\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" %u,%u,%u => %u,%u,%u\\n\", FUNC_ADPT_ARG(iface)\n\t\t\t\t\t\t, ori_ch, ori_bw, ori_offset\n\t\t\t\t\t\t, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);\n\n\t\t\t\t\trtw_ap_update_bss_chbw(iface, &(mlmeext->mlmext_info.network)\n\t\t\t\t\t\t, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);\n\n\t\t\t\t\t_rtw_memcpy(&(mlme->cur_network.network), &(mlmeext->mlmext_info.network), sizeof(WLAN_BSSID_EX));\n\n\t\t\t\t\trtw_start_bss_hdl_after_chbw_decided(iface);\n\n\t\t\t\t\t{\n\t\t\t\t\t\t#if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))\n\t\t\t\t\t\tu8 ht_option = 0;\n\n\t\t\t\t\t\t#ifdef CONFIG_80211N_HT\n\t\t\t\t\t\tht_option = mlme->htpriv.ht_option;\n\t\t\t\t\t\t#endif\n\n\t\t\t\t\t\trtw_cfg80211_ch_switch_notify(iface\n\t\t\t\t\t\t\t, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset\n\t\t\t\t\t\t\t, ht_option);\n\t\t\t\t\t\t#endif\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tclr_fwstate(mlme, WIFI_OP_CH_SWITCHING);\n\t\t\t\tupdate_beacon(iface, 0xFF, NULL, _TRUE, 0);\n\t\t\t}\n\t\t}\n\n#ifdef CONFIG_DFS_MASTER\n\t\trtw_dfs_rd_en_decision(adapter, MLME_STA_CONNECTED, 0);\n#endif\n\t} else {\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tmlme = &iface->mlmepriv;\n\t\t\tmlmeext = &iface->mlmeextpriv;\n\n\t\t\tif (!iface || iface == adapter)\n\t\t\t\tcontinue;\n\n\t\t\tif ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))\n\t\t\t\t&& check_fwstate(mlme, WIFI_ASOC_STATE)\n\t\t\t) {\n\t\t\t\tclr_fwstate(mlme, WIFI_OP_CH_SWITCHING);\n\t\t\t\tupdate_beacon(iface, 0xFF, NULL, _TRUE, 0);\n\t\t\t}\n\t\t}\n#ifdef CONFIG_DFS_MASTER\n\t\trtw_dfs_rd_en_decision(adapter, MLME_STA_DISCONNECTED, 0);\n#endif\n\t}\n\n\tif (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" union:%u,%u,%u\\n\", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset);\n\t\tset_channel_bwmode(adapter, u_ch, u_offset, u_bw);\n\t\trtw_mi_update_union_chan_inf(adapter, u_ch, u_offset, u_bw);\n\t}\n\n\tif (DUMP_ADAPTERS_STATUS) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" exit\\n\", FUNC_ADPT_ARG(adapter));\n\t\tdump_adapters_status(RTW_DBGDUMP , dvobj);\n\t}\n}\n\nint rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset)\n{\n#ifdef CONFIG_CONCURRENT_MODE\n\tbool chbw_allow = _TRUE;\n#endif\n\tbool connect_allow = _TRUE;\n\tstruct mlme_ext_priv\t*pmlmeext = &adapter->mlmeextpriv;\n\tu8 cur_ch, cur_bw, cur_ch_offset;\n\tu8 u_ch, u_offset, u_bw;\n\n\tu_ch = cur_ch = pmlmeext->cur_channel;\n\tu_bw = cur_bw = pmlmeext->cur_bwmode;\n\tu_offset = cur_ch_offset = pmlmeext->cur_ch_offset;\n\n\tif (!ch || !bw || !offset) {\n\t\tconnect_allow = _FALSE;\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (cur_ch == 0) {\n\t\tconnect_allow = _FALSE;\n\t\tRTW_ERR(FUNC_ADPT_FMT\" cur_ch:%u\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), cur_ch);\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\tRTW_INFO(FUNC_ADPT_FMT\" req: %u,%u,%u\\n\", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t{\n\t\tstruct dvobj_priv *dvobj;\n\t\t_adapter *iface;\n\t\tstruct mlme_priv *mlme;\n\t\tstruct mlme_ext_priv *mlmeext;\n\t\tstruct mi_state mstate;\n\t\tint i;\n\n\t\tdvobj = adapter_to_dvobj(adapter);\n\n\t\trtw_mi_status_no_self(adapter, &mstate);\n\t\tRTW_INFO(FUNC_ADPT_FMT\" others ld_sta_num:%u, ap_num:%u, mesh_num:%u\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate)\n\t\t\t, MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate));\n\n\t\tif (!MSTATE_STA_LD_NUM(&mstate) && !MSTATE_AP_NUM(&mstate) && !MSTATE_MESH_NUM(&mstate)) {\n\t\t\t/* consider linking STA? */\n\t\t\tgoto connect_allow_hdl;\n\t\t}\n\n\t\tif (rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset) <= 0) {\n\t\t\tdump_adapters_status(RTW_DBGDUMP , dvobj);\n\t\t\trtw_warn_on(1);\n\t\t}\n\t\tRTW_INFO(FUNC_ADPT_FMT\" others union:%u,%u,%u\\n\"\n\t\t\t , FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset);\n\n\t\t/* chbw_allow? */\n\t\tchbw_allow = rtw_is_chbw_grouped(pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset\n\t\t\t\t\t\t , u_ch, u_bw, u_offset);\n\n\t\tRTW_INFO(FUNC_ADPT_FMT\" chbw_allow:%d\\n\"\n\t\t\t , FUNC_ADPT_ARG(adapter), chbw_allow);\n\n#ifdef CONFIG_MCC_MODE\n\t\t/* check setting success, don't go to ch union process */\n\t\tif (rtw_hal_set_mcc_setting_chk_start_clnt_join(adapter, &u_ch, &u_bw, &u_offset, chbw_allow))\n\t\t\tgoto exit;\n#endif\n\n\t\tif (chbw_allow == _TRUE) {\n\t\t\trtw_sync_chbw(&cur_ch, &cur_bw, &cur_ch_offset, &u_ch, &u_bw, &u_offset);\n\t\t\trtw_warn_on(cur_ch != pmlmeext->cur_channel);\n\t\t\trtw_warn_on(cur_bw != pmlmeext->cur_bwmode);\n\t\t\trtw_warn_on(cur_ch_offset != pmlmeext->cur_ch_offset);\n\t\t\tgoto connect_allow_hdl;\n\t\t}\n\n#ifdef CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT\n\t\t/* chbw_allow is _FALSE, connect allow? */\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tmlme = &iface->mlmepriv;\n\t\t\tmlmeext = &iface->mlmeextpriv;\n\n\t\t\tif (check_fwstate(mlme, WIFI_STATION_STATE)\n\t\t\t    && check_fwstate(mlme, WIFI_ASOC_STATE)\n#if defined(CONFIG_P2P)\n\t\t\t    && rtw_p2p_chk_state(&(iface->wdinfo), P2P_STATE_NONE)\n#endif\n\t\t\t   ) {\n\t\t\t\tconnect_allow = _FALSE;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n#endif /* CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT */\n\n\t\tif (MSTATE_STA_LD_NUM(&mstate) + MSTATE_AP_LD_NUM(&mstate) + MSTATE_MESH_LD_NUM(&mstate) >= 4)\n\t\t\tconnect_allow = _FALSE;\n\n\t\tRTW_INFO(FUNC_ADPT_FMT\" connect_allow:%d\\n\"\n\t\t\t , FUNC_ADPT_ARG(adapter), connect_allow);\n\n\t\tif (connect_allow == _FALSE)\n\t\t\tgoto exit;\n\nconnect_allow_hdl:\n\t\t/* connect_allow == _TRUE */\n\n\t\tif (chbw_allow == _FALSE) {\n\t\t\tu_ch = cur_ch;\n\t\t\tu_bw = cur_bw;\n\t\t\tu_offset = cur_ch_offset;\n\n\t\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\t\tiface = dvobj->padapters[i];\n\t\t\t\tmlme = &iface->mlmepriv;\n\t\t\t\tmlmeext = &iface->mlmeextpriv;\n\n\t\t\t\tif (!iface || iface == adapter)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))\n\t\t\t\t\t&& check_fwstate(mlme, WIFI_ASOC_STATE)\n\t\t\t\t) {\n\t\t\t\t\t#ifdef CONFIG_SPCT_CH_SWITCH\n\t\t\t\t\tif (1)\n\t\t\t\t\t\trtw_ap_inform_ch_switch(iface, pmlmeext->cur_channel , pmlmeext->cur_ch_offset);\n\t\t\t\t\telse\n\t\t\t\t\t#endif\n\t\t\t\t\t\trtw_sta_flush(iface, _FALSE);\n\n\t\t\t\t\trtw_hal_set_hwreg(iface, HW_VAR_CHECK_TXBUF, 0);\n\t\t\t\t\tset_fwstate(mlme, WIFI_OP_CH_SWITCHING);\n\n\t\t\t\t} else if (check_fwstate(mlme, WIFI_STATION_STATE)\n\t\t\t\t\t&& check_fwstate(mlme, WIFI_ASOC_STATE)\n\t\t\t\t) {\n\t\t\t\t\trtw_disassoc_cmd(iface, 500, RTW_CMDF_DIRECTLY);\n\t\t\t\t\trtw_indicate_disconnect(iface, 0, _FALSE);\n\t\t\t\t\trtw_free_assoc_resources(iface, _TRUE);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t#ifdef CONFIG_DFS_MASTER\n\t\trtw_dfs_rd_en_decision(adapter, MLME_STA_CONNECTING, 0);\n\t\t#endif\n\t}\n#endif /* CONFIG_CONCURRENT_MODE */\n\nexit:\n\n\tif (connect_allow == _TRUE) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" union: %u,%u,%u\\n\", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset);\n\t\t*ch = u_ch;\n\t\t*bw = u_bw;\n\t\t*offset = u_offset;\n\n#if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))\n\t\t{\n\t\t\tu8 ht_option = 0;\n\n#ifdef CONFIG_80211N_HT\n\t\t\tht_option = adapter->mlmepriv.htpriv.ht_option;\n#endif /* CONFIG_80211N_HT */\n\n\t\t\t/* \n\t\t\t\twhen supplicant send the mlme frame,\n\t\t\t\tthe bss freq is updated by channel switch event.\n\t\t\t*/\n\t\t\trtw_cfg80211_ch_switch_notify(adapter,\n\t\t\t\tcur_ch, cur_bw, cur_ch_offset, ht_option);\n\t\t}\n#endif\n\t}\n\n\treturn connect_allow == _TRUE ? _SUCCESS : _FAIL;\n}\n\nvoid rtw_set_external_auth_status(_adapter *padapter,\n\tconst void *data, int len)\n{\n#ifdef CONFIG_IOCTL_CFG80211\n\tstruct net_device *dev = padapter->pnetdev;\n\tstruct wiphy *wiphy = adapter_to_wiphy(padapter);\n\tstruct rtw_external_auth_params params;\n\n\t/* convert data to external_auth_params */\n\tparams.action = RTW_GET_BE32((u8 *)data);\n\t_rtw_memcpy(&params.bssid, (u8 *)data + 4, ETH_ALEN);\n\t_rtw_memcpy(&params.ssid.ssid, (u8 *)data + 10, WLAN_SSID_MAXLEN);\n\tparams.ssid.ssid_len = RTW_GET_BE64((u8 *)data + 42);\n\tparams.key_mgmt_suite = RTW_GET_BE32((u8 *)data + 58);\n\tparams.status = RTW_GET_BE16((u8 *)data + 62);\n\t_rtw_memcpy(&params.pmkid, (u8 *)data + 64, PMKID_LEN);\n\n\trtw_cfg80211_external_auth_status(wiphy, dev, &params);\n#endif /* CONFIG_IOCTL_CFG80211 */\n}\n\nu8 rtw_set_chbw_hdl(_adapter *padapter, u8 *pbuf)\n{\n\tstruct set_ch_parm *set_ch_parm;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\n\tif (!pbuf)\n\t\treturn H2C_PARAMETERS_ERROR;\n\n\tset_ch_parm = (struct set_ch_parm *)pbuf;\n\n\tRTW_INFO(FUNC_NDEV_FMT\" ch:%u, bw:%u, ch_offset:%u\\n\",\n\t\t FUNC_NDEV_ARG(padapter->pnetdev),\n\t\t set_ch_parm->ch, set_ch_parm->bw, set_ch_parm->ch_offset);\n\n\tpmlmeext->cur_channel = set_ch_parm->ch;\n\tpmlmeext->cur_ch_offset = set_ch_parm->ch_offset;\n\tpmlmeext->cur_bwmode = set_ch_parm->bw;\n\n\tset_channel_bwmode(padapter, set_ch_parm->ch, set_ch_parm->ch_offset, set_ch_parm->bw);\n\n\treturn\tH2C_SUCCESS;\n}\n\nu8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf)\n{\n\tstruct SetChannelPlan_param *setChannelPlan_param;\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\n\tif (!pbuf)\n\t\treturn H2C_PARAMETERS_ERROR;\n\n\tsetChannelPlan_param = (struct SetChannelPlan_param *)pbuf;\n\n\tif (!rtw_is_channel_plan_valid(setChannelPlan_param->channel_plan))\n\t\treturn H2C_PARAMETERS_ERROR;\n\n\trfctl->country_ent = setChannelPlan_param->country_ent;\n\trfctl->ChannelPlan = setChannelPlan_param->channel_plan;\n\n\trfctl->max_chan_nums = init_channel_set(padapter, rfctl->ChannelPlan, rfctl->channel_set);\n\tinit_channel_list(padapter, rfctl->channel_set, &rfctl->channel_list);\n#if CONFIG_TXPWR_LIMIT\n\trtw_txpwr_init_regd(rfctl);\n#endif\n\n\trtw_hal_set_odm_var(padapter, HAL_ODM_REGULATION, NULL, _TRUE);\n\n#ifdef CONFIG_IOCTL_CFG80211\n\trtw_regd_apply_flags(adapter_to_wiphy(padapter));\n#endif\n\n\treturn\tH2C_SUCCESS;\n}\n\nu8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf)\n{\n\tstruct LedBlink_param *ledBlink_param;\n\n\tif (!pbuf)\n\t\treturn H2C_PARAMETERS_ERROR;\n\n\tledBlink_param = (struct LedBlink_param *)pbuf;\n\n#ifdef CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD\n\tBlinkHandler((PLED_DATA)ledBlink_param->pLed);\n#endif\n\n\treturn\tH2C_SUCCESS;\n}\n\nu8 set_csa_hdl(_adapter *adapter, unsigned char *pbuf)\n{\n#ifdef CONFIG_DFS\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\n\tif (rfctl->csa_ch)\n\t\trtw_dfs_ch_switch_hdl(adapter_to_dvobj(adapter));\n#endif\n\treturn\tH2C_SUCCESS;\n}\n\nu8 tdls_hdl(_adapter *padapter, unsigned char *pbuf)\n{\n#ifdef CONFIG_TDLS\n\t_irqL irqL;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n#ifdef CONFIG_TDLS_CH_SW\n\tstruct tdls_ch_switch *pchsw_info = &ptdlsinfo->chsw_info;\n#endif\n\tstruct TDLSoption_param *TDLSoption;\n\tstruct sta_info *ptdls_sta = NULL;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;\n\tstruct sta_info *ap_sta = rtw_get_stainfo(&padapter->stapriv, get_my_bssid(&(pmlmeinfo->network)));\n\tu8 survey_channel, i, min, option;\n\tstruct tdls_txmgmt txmgmt;\n\tu32 setchtime, resp_sleep = 0, wait_time;\n\tu8 zaddr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};\n\tu8 ret;\n\tu8 doiqk;\n\tu64 tx_ra_bitmap = 0;\n\n\tif (!pbuf)\n\t\treturn H2C_PARAMETERS_ERROR;\n\n\tTDLSoption = (struct TDLSoption_param *)pbuf;\n\toption = TDLSoption->option;\n\n\tif (!_rtw_memcmp(TDLSoption->addr, zaddr, ETH_ALEN)) {\n\t\tptdls_sta = rtw_get_stainfo(&(padapter->stapriv), TDLSoption->addr);\n\t\tif (ptdls_sta == NULL)\n\t\t\treturn H2C_REJECTED;\n\t} else {\n\t\tif (!(option == TDLS_RS_RCR))\n\t\t\treturn H2C_REJECTED;\n\t}\n\n\t/* _enter_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); */\n\t/* RTW_INFO(\"[%s] option:%d\\n\", __FUNCTION__, option); */\n\n\tswitch (option) {\n\tcase TDLS_ESTABLISHED: {\n\t\t/* As long as TDLS handshake success, we should set RCR_CBSSID_DATA bit to 0 */\n\t\t/* So we can receive all kinds of data frames. */\n\t\tu8 sta_band = 0;\n\n\t\t/* leave ALL PS when TDLS is established */\n\t\trtw_pwr_wakeup(padapter);\n\n\t\trtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_LINKED);\n\t\tRTW_INFO(\"Created Direct Link with \"MAC_FMT\"\\n\", MAC_ARG(ptdls_sta->cmn.mac_addr));\n\n\t\t/* Set TDLS sta rate. */\n\t\t/* Update station supportRate */\n\t\trtw_hal_update_sta_ra_info(padapter, ptdls_sta);\n\t\ttx_ra_bitmap = ptdls_sta->cmn.ra_info.ramask;\n\n\t\tif (pmlmeext->cur_channel > 14) {\n\t\t\tif (tx_ra_bitmap & 0xffff000)\n\t\t\t\tsta_band |= WIRELESS_11_5N ;\n\n\t\t\tif (tx_ra_bitmap & 0xff0)\n\t\t\t\tsta_band |= WIRELESS_11A;\n\n\t\t\t/* 5G band */\n#ifdef CONFIG_80211AC_VHT\n\t\t\tif (ptdls_sta->vhtpriv.vht_option)\n\t\t\t\tsta_band = WIRELESS_11_5AC;\n#endif\n\n\t\t} else {\n\t\t\tif (tx_ra_bitmap & 0xffff000)\n\t\t\t\tsta_band |= WIRELESS_11_24N;\n\n\t\t\tif (tx_ra_bitmap & 0xff0)\n\t\t\t\tsta_band |= WIRELESS_11G;\n\n\t\t\tif (tx_ra_bitmap & 0x0f)\n\t\t\t\tsta_band |= WIRELESS_11B;\n\t\t}\n\t\tptdls_sta->wireless_mode = sta_band;\n\t\trtw_hal_update_sta_wset(padapter, ptdls_sta);\n\t\t/* Sta mode */\n\t\trtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, ptdls_sta, _TRUE);\n\n\t\tset_sta_rate(padapter, ptdls_sta);\n\t\trtw_sta_media_status_rpt(padapter, ptdls_sta, 1);\n\t\tbreak;\n\t}\n\tcase TDLS_ISSUE_PTI:\n\t\tptdls_sta->tdls_sta_state |= TDLS_WAIT_PTR_STATE;\n\t\tissue_tdls_peer_traffic_indication(padapter, ptdls_sta);\n\t\t_set_timer(&ptdls_sta->pti_timer, TDLS_PTI_TIME);\n\t\tbreak;\n#ifdef CONFIG_TDLS_CH_SW\n\tcase TDLS_CH_SW_RESP:\n\t\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\t\ttxmgmt.status_code = 0;\n\t\t_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);\n\n\t\tif (ap_sta)\n\t\t\trtw_hal_macid_sleep(padapter, ap_sta->cmn.mac_id);\n\t\tissue_nulldata(padapter, NULL, 1, 3, 3);\n\n\t\tRTW_INFO(\"[TDLS ] issue tdls channel switch response\\n\");\n\t\tret = issue_tdls_ch_switch_rsp(padapter, &txmgmt, _TRUE);\n\n\t\t/* If we receive TDLS_CH_SW_REQ at off channel which it's target is AP's channel */\n\t\t/* then we just switch to AP's channel*/\n\t\tif (padapter->mlmeextpriv.cur_channel == pchsw_info->off_ch_num) {\n\t\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL);\n\t\t\tbreak;\n\t\t}\n\n\t\tif (ret == _SUCCESS)\n\t\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_OFF_CHNL);\n\t\telse\n\t\t\tRTW_INFO(\"[TDLS] issue_tdls_ch_switch_rsp wait ack fail !!!!!!!!!!\\n\");\n\n\t\tbreak;\n\tcase TDLS_CH_SW_PREPARE:\n\t\tpchsw_info->ch_sw_state |= TDLS_CH_SWITCH_PREPARE_STATE;\n\n\t\t/* to collect IQK info of off-chnl */\n\t\tdoiqk = _TRUE;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk);\n\t\tset_channel_bwmode(padapter, pchsw_info->off_ch_num, pchsw_info->ch_offset, (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20);\n\t\tdoiqk = _FALSE;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk);\n\n\t\t/* switch back to base-chnl */\n\t\tset_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);\n\n\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);\n\n\t\tpchsw_info->ch_sw_state &= ~(TDLS_CH_SWITCH_PREPARE_STATE);\n\n\t\tbreak;\n\tcase TDLS_CH_SW_START:\n\t\trtw_tdls_set_ch_sw_oper_control(padapter, _TRUE);\n\t\tbreak;\n\tcase TDLS_CH_SW_TO_OFF_CHNL:\n\t\tif (ap_sta)\n\t\t\trtw_hal_macid_sleep(padapter, ap_sta->cmn.mac_id);\n\t\tissue_nulldata(padapter, NULL, 1, 3, 3);\n\n\t\tif (padapter->registrypriv.wifi_spec == 0) {\n\t\tif (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))\n\t\t\t_set_timer(&ptdls_sta->ch_sw_timer, (u32)(ptdls_sta->ch_switch_timeout) / 1000);\n\t\t}\n\n\t\tif (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_OFF_CHNL, pchsw_info->off_ch_num,\n\t\t\tpchsw_info->ch_offset, (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20, ptdls_sta->ch_switch_time) == _SUCCESS) {\n\t\t\tpchsw_info->ch_sw_state &= ~(TDLS_PEER_AT_OFF_STATE);\n\t\t\tif (pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE) {\n\t\t\t\tif (issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta->cmn.mac_addr, 0, 1, \n\t\t\t\t\t(padapter->registrypriv.wifi_spec == 0) ? 3 : 0) == _FAIL)\n\t\t\t\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL);\n\t\t\t}\n\t\t} else {\n\t\t\tif (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))\n\t\t\t\t_cancel_timer_ex(&ptdls_sta->ch_sw_timer);\n\t\t}\n\n\n\t\tbreak;\n\tcase TDLS_CH_SW_END:\n\tcase TDLS_CH_SW_END_TO_BASE_CHNL:\n\t\trtw_tdls_set_ch_sw_oper_control(padapter, _FALSE);\n\t\t_cancel_timer_ex(&ptdls_sta->ch_sw_timer);\n\t\t_cancel_timer_ex(&ptdls_sta->stay_on_base_chnl_timer);\n\t\t_cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer);\n#if 0\n\t\t_rtw_memset(pHalData->tdls_ch_sw_iqk_info_base_chnl, 0x00, sizeof(pHalData->tdls_ch_sw_iqk_info_base_chnl));\n\t\t_rtw_memset(pHalData->tdls_ch_sw_iqk_info_off_chnl, 0x00, sizeof(pHalData->tdls_ch_sw_iqk_info_off_chnl));\n#endif\n\n\t\tif (option == TDLS_CH_SW_END_TO_BASE_CHNL)\n\t\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL);\n\n\t\tbreak;\n\tcase TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED:\n\tcase TDLS_CH_SW_TO_BASE_CHNL:\n\t\tpchsw_info->ch_sw_state &= ~(TDLS_PEER_AT_OFF_STATE | TDLS_WAIT_CH_RSP_STATE);\n\n\t\tif (option == TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED) {\n\t\t\tif (ptdls_sta != NULL) {\n\t\t\t\t/* Send unsolicited channel switch rsp. to peer */\n\t\t\t\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\t\t\t\ttxmgmt.status_code = 0;\n\t\t\t\t_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);\n\t\t\t\tissue_tdls_ch_switch_rsp(padapter, &txmgmt, _FALSE);\n\t\t\t}\n\t\t}\n\n\t\tif (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_BASE_CHNL, pmlmeext->cur_channel,\n\t\t\tpmlmeext->cur_ch_offset, pmlmeext->cur_bwmode, ptdls_sta->ch_switch_time) == _SUCCESS) {\n\t\t\tif (ap_sta)\n\t\t\t\trtw_hal_macid_wakeup(padapter, ap_sta->cmn.mac_id);\n\t\t\tissue_nulldata(padapter, NULL, 0, 3, 3);\n\t\t\t/* set ch sw monitor timer for responder */\n\t\t\tif (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))\n\t\t\t\t_set_timer(&ptdls_sta->ch_sw_monitor_timer, TDLS_CH_SW_MONITOR_TIMEOUT);\n\t\t}\n\n\t\tbreak;\n#endif\n\tcase TDLS_RS_RCR:\n\t\trtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_NOLINK);\n\t\tbreak;\n\tcase TDLS_TEARDOWN_STA:\n\tcase TDLS_TEARDOWN_STA_NO_WAIT:\n\t\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\t\ttxmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;\n\t\t_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);\n\n\t\tissue_tdls_teardown(padapter, &txmgmt, (option == TDLS_TEARDOWN_STA) ? _TRUE : _FALSE);\n\n\t\tbreak;\n\tcase TDLS_TEARDOWN_STA_LOCALLY:\n\tcase TDLS_TEARDOWN_STA_LOCALLY_POST:\n#ifdef CONFIG_TDLS_CH_SW\n\t\tif (_rtw_memcmp(TDLSoption->addr, pchsw_info->addr, ETH_ALEN) == _TRUE) {\n\t\t\tpchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE |\n\t\t\t\t\t\t     TDLS_CH_SWITCH_ON_STATE |\n\t\t\t\t\t\t     TDLS_PEER_AT_OFF_STATE);\n\t\t\trtw_tdls_set_ch_sw_oper_control(padapter, _FALSE);\n\t\t\t_rtw_memset(pchsw_info->addr, 0x00, ETH_ALEN);\n\t\t}\n#endif\n\n\t\tif (option == TDLS_TEARDOWN_STA_LOCALLY)\n\t\t\trtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);\n\n\t\trtw_tdls_teardown_post_hdl(padapter, ptdls_sta, _FALSE);\n\n\t\tif (ptdlsinfo->tdls_sctx != NULL)\n\t\t\trtw_sctx_done(&(ptdlsinfo->tdls_sctx));\n\n\t\tbreak;\n\t}\n\n\t/* _exit_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); */\n\n\treturn H2C_SUCCESS;\n#else\n\treturn H2C_REJECTED;\n#endif /* CONFIG_TDLS */\n\n}\n\nu8 run_in_thread_hdl(_adapter *padapter, u8 *pbuf)\n{\n\tstruct RunInThread_param *p;\n\n\n\tif (NULL == pbuf)\n\t\treturn H2C_PARAMETERS_ERROR;\n\tp = (struct RunInThread_param *)pbuf;\n\n\tif (p->func)\n\t\tp->func(p->context);\n\n\treturn H2C_SUCCESS;\n}\n\nu8 rtw_getmacreg_hdl(_adapter *padapter, u8 *pbuf)\n{\n\n\tstruct readMAC_parm *preadmacparm = NULL;\n\tu8 sz = 0;\n\tu32\taddr = 0;\n\tu32\tvalue = 0;\n\n\tif (!pbuf)\n\t\treturn H2C_PARAMETERS_ERROR;\n\n\tpreadmacparm = (struct readMAC_parm *) pbuf;\n\tsz = preadmacparm->len;\n\taddr = preadmacparm->addr;\n\tvalue = 0;\n\n\tswitch (sz) {\n\tcase 1:\n\t\tvalue = rtw_read8(padapter, addr);\n\t\tbreak;\n\tcase 2:\n\t\tvalue = rtw_read16(padapter, addr);\n\t\tbreak;\n\tcase 4:\n\t\tvalue = rtw_read32(padapter, addr);\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(\"%s: Unknown size\\n\", __func__);\n\t\tbreak;\n\t}\n\tRTW_INFO(\"%s: addr:0x%02x valeu:0x%02x\\n\", __func__, addr, value);\n\n\treturn H2C_SUCCESS;\n}\n\nint rtw_sae_preprocess(_adapter *adapter, const u8 *buf, u32 len, u8 tx)\n{\n#ifdef CONFIG_IOCTL_CFG80211\n\tconst u8 *frame_body = buf + sizeof(struct rtw_ieee80211_hdr_3addr);\n\tu16 alg;\n\tu16 seq;\n\tu16 status;\n\tint ret = _FAIL;\n\n\talg = RTW_GET_LE16(frame_body);\n\tif (alg != WLAN_AUTH_SAE)\n\t\tgoto exit;\n\n\tseq = RTW_GET_LE16(frame_body + 2);\n\tstatus = RTW_GET_LE16(frame_body + 4);\n\n\tRTW_INFO(\"RTW_%s:AUTH alg:0x%04x, seq:0x%04x, status:0x%04x, mesg:%s\\n\",\n\t\t(tx == _TRUE) ? \"Tx\" : \"Rx\", alg, seq, status,\n\t\t(seq == 1) ? \"Commit\" : \"Confirm\");\n\n\tret = _SUCCESS;\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(adapter)) {\n\t\trtw_mesh_sae_check_frames(adapter, buf, len, tx, alg, seq, status);\n\t\tgoto exit;\n\t}\n#endif\n\n\tif (tx && (seq == 2) && (status == 0)) {\n\t\t/* quere commit frame until external auth statue update */\n\t\tstruct sta_priv *pstapriv = &adapter->stapriv;\n\t\tstruct sta_info\t*psta = NULL;\n\t\t_irqL irqL;\n\n\t\tpsta = rtw_get_stainfo(pstapriv, GetAddr1Ptr(buf));\n\t\tif (psta) {\n\t\t\t_enter_critical_bh(&psta->lock, &irqL);\n\t\t\tif (psta->pauth_frame) {\n\t\t\t\trtw_mfree(psta->pauth_frame, psta->auth_len);\n\t\t\t\tpsta->pauth_frame = NULL;\n\t\t\t\tpsta->auth_len = 0;\n\t\t\t}\n\n\t\t\tpsta->pauth_frame =  rtw_zmalloc(len);\n\t\t\tif (psta->pauth_frame) {\n\t\t\t\t_rtw_memcpy(psta->pauth_frame, buf, len);\n\t\t\t\tpsta->auth_len = len;\n\t\t\t}\n\t\t\t_exit_critical_bh(&psta->lock, &irqL);\n\n\t\t\tret = 2;\n\t\t}\n\t}\nexit:\n\treturn ret;\n#else\n\treturn _SUCCESS;\n#endif /* CONFIG_IOCTL_CFG80211 */\n}\n\n"
  },
  {
    "path": "core/rtw_mp.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_MP_C_\n#include <drv_types.h>\n#ifdef PLATFORM_FREEBSD\n\t#include <sys/unistd.h>\t\t/* for RFHIGHPID */\n#endif\n\n#include \"../hal/phydm/phydm_precomp.h\"\n#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A)\n\t#include <rtw_bt_mp.h>\n#endif\n\n#ifdef CONFIG_MP_VHT_HW_TX_MODE\n#define CEILING_POS(X) ((X - (int)(X)) > 0 ? (int)(X + 1) : (int)(X))\n#define CEILING_NEG(X) ((X - (int)(X)) < 0 ? (int)(X - 1) : (int)(X))\n#define ceil(X) (((X) > 0) ? CEILING_POS(X) : CEILING_NEG(X))\n\nint rtfloor(float x)\n{\n\tint i = x - 2;\n\twhile\n\t(++i <= x - 1)\n\t\t;\n\treturn i;\n}\n#endif\n\n#ifdef CONFIG_MP_INCLUDED\nu32 read_macreg(_adapter *padapter, u32 addr, u32 sz)\n{\n\tu32 val = 0;\n\n\tswitch (sz) {\n\tcase 1:\n\t\tval = rtw_read8(padapter, addr);\n\t\tbreak;\n\tcase 2:\n\t\tval = rtw_read16(padapter, addr);\n\t\tbreak;\n\tcase 4:\n\t\tval = rtw_read32(padapter, addr);\n\t\tbreak;\n\tdefault:\n\t\tval = 0xffffffff;\n\t\tbreak;\n\t}\n\n\treturn val;\n\n}\n\nvoid write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz)\n{\n\tswitch (sz) {\n\tcase 1:\n\t\trtw_write8(padapter, addr, (u8)val);\n\t\tbreak;\n\tcase 2:\n\t\trtw_write16(padapter, addr, (u16)val);\n\t\tbreak;\n\tcase 4:\n\t\trtw_write32(padapter, addr, val);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n}\n\nu32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask)\n{\n\treturn rtw_hal_read_bbreg(padapter, addr, bitmask);\n}\n\nvoid write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val)\n{\n\trtw_hal_write_bbreg(padapter, addr, bitmask, val);\n}\n\nu32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask)\n{\n\treturn rtw_hal_read_rfreg(padapter, rfpath, addr, bitmask);\n}\n\nvoid _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val)\n{\n\trtw_hal_write_rfreg(padapter, rfpath, addr, bitmask, val);\n}\n\nu32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr)\n{\n\treturn _read_rfreg(padapter, rfpath, addr, bRFRegOffsetMask);\n}\n\nvoid write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val)\n{\n\t_write_rfreg(padapter, rfpath, addr, bRFRegOffsetMask, val);\n}\n\nstatic void _init_mp_priv_(struct mp_priv *pmp_priv)\n{\n\tWLAN_BSSID_EX *pnetwork;\n\n\t_rtw_memset(pmp_priv, 0, sizeof(struct mp_priv));\n\n\tpmp_priv->mode = MP_OFF;\n\n\tpmp_priv->channel = 1;\n\tpmp_priv->bandwidth = CHANNEL_WIDTH_20;\n\tpmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\tpmp_priv->rateidx = RATE_1M;\n\tpmp_priv->txpoweridx = 0x2A;\n\n\tpmp_priv->antenna_tx = ANTENNA_A;\n\tpmp_priv->antenna_rx = ANTENNA_AB;\n\n\tpmp_priv->check_mp_pkt = 0;\n\n\tpmp_priv->tx_pktcount = 0;\n\n\tpmp_priv->rx_bssidpktcount = 0;\n\tpmp_priv->rx_pktcount = 0;\n\tpmp_priv->rx_crcerrpktcount = 0;\n\n\tpmp_priv->network_macaddr[0] = 0x00;\n\tpmp_priv->network_macaddr[1] = 0xE0;\n\tpmp_priv->network_macaddr[2] = 0x4C;\n\tpmp_priv->network_macaddr[3] = 0x87;\n\tpmp_priv->network_macaddr[4] = 0x66;\n\tpmp_priv->network_macaddr[5] = 0x55;\n\n\tpmp_priv->bSetRxBssid = _FALSE;\n\tpmp_priv->bRTWSmbCfg = _FALSE;\n\tpmp_priv->bloopback = _FALSE;\n\n\tpmp_priv->bloadefusemap = _FALSE;\n\tpmp_priv->brx_filter_beacon = _FALSE;\n\tpmp_priv->mplink_brx = _FALSE;\n\n\tpnetwork = &pmp_priv->mp_network.network;\n\t_rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN);\n\n\tpnetwork->Ssid.SsidLength = 8;\n\t_rtw_memcpy(pnetwork->Ssid.Ssid, \"mp_871x\", pnetwork->Ssid.SsidLength);\n\n\tpmp_priv->tx.payload = 2;\n#ifdef CONFIG_80211N_HT\n\tpmp_priv->tx.attrib.ht_en = 1;\n#endif\n\n\tpmp_priv->mpt_ctx.mpt_rate_index = 1;\n\n}\n\n\nstatic void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n\tstruct pkt_attrib *pattrib;\n\n\t/* init xmitframe attribute */\n\tpattrib = &pmptx->attrib;\n\t_rtw_memset(pattrib, 0, sizeof(struct pkt_attrib));\n\t_rtw_memset(pmptx->desc, 0, TXDESC_SIZE);\n\n\tpattrib->ether_type = 0x8712;\n#if 0\n\t_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);\n#endif\n\t_rtw_memset(pattrib->dst, 0xFF, ETH_ALEN);\n\n\t/*\tpattrib->dhcp_pkt = 0;\n\t *\tpattrib->pktlen = 0; */\n\tpattrib->ack_policy = 0;\n\t/*\tpattrib->pkt_hdrlen = ETH_HLEN; */\n\tpattrib->hdrlen = WLAN_HDR_A3_LEN;\n\tpattrib->subtype = WIFI_DATA;\n\tpattrib->priority = 0;\n\tpattrib->qsel = pattrib->priority;\n\t/*\tdo_queue_select(padapter, pattrib); */\n\tpattrib->nr_frags = 1;\n\tpattrib->encrypt = 0;\n\tpattrib->bswenc = _FALSE;\n\tpattrib->qos_en = _FALSE;\n\n\tpattrib->pktlen = 1500;\n\n\tif (pHalData->rf_type == RF_2T2R)\n\t\tpattrib->raid = RATEID_IDX_BGN_40M_2SS;\n\telse\n\t\tpattrib->raid = RATEID_IDX_BGN_40M_1SS;\n\n#ifdef CONFIG_80211AC_VHT\n\tif (pHalData->rf_type == RF_1T1R)\n\t\tpattrib->raid = RATEID_IDX_VHT_1SS;\n\telse if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)\n\t\tpattrib->raid = RATEID_IDX_VHT_2SS;\n\telse if (pHalData->rf_type == RF_3T3R)\n\t\tpattrib->raid = RATEID_IDX_VHT_3SS;\n\telse\n\t\tpattrib->raid = RATEID_IDX_BGN_40M_1SS;\n#endif\n}\n\ns32 init_mp_priv(PADAPTER padapter)\n{\n\tstruct mp_priv *pmppriv = &padapter->mppriv;\n\tPHAL_DATA_TYPE pHalData;\n\n\tpHalData = GET_HAL_DATA(padapter);\n\n\t_init_mp_priv_(pmppriv);\n\tpmppriv->papdater = padapter;\n\tif (IS_HARDWARE_TYPE_8822C(padapter))\n\t\tpmppriv->mp_dm = 1;/* default enable dpk tracking */\n\telse\n\t\tpmppriv->mp_dm = 0;\n\n\tpmppriv->tx.stop = 1;\n\tpmppriv->bSetTxPower = 0;\t\t/*for  manually set tx power*/\n\tpmppriv->bTxBufCkFail = _FALSE;\n\tpmppriv->pktInterval = 0;\n\tpmppriv->pktLength = 1000;\n\tpmppriv->bprocess_mp_mode = _FALSE;\n\n\tmp_init_xmit_attrib(&pmppriv->tx, padapter);\n\n\tswitch (padapter->registrypriv.rf_config) {\n\tcase RF_1T1R:\n\t\tpmppriv->antenna_tx = ANTENNA_A;\n\t\tpmppriv->antenna_rx = ANTENNA_A;\n\t\tbreak;\n\tcase RF_1T2R:\n\tdefault:\n\t\tpmppriv->antenna_tx = ANTENNA_A;\n\t\tpmppriv->antenna_rx = ANTENNA_AB;\n\t\tbreak;\n\tcase RF_2T2R:\n\t\tpmppriv->antenna_tx = ANTENNA_AB;\n\t\tpmppriv->antenna_rx = ANTENNA_AB;\n\t\tbreak;\n\tcase RF_2T4R:\n\t\tpmppriv->antenna_tx = ANTENNA_BC;\n\t\tpmppriv->antenna_rx = ANTENNA_ABCD;\n\t\tbreak;\n\t}\n\n\tpHalData->AntennaRxPath = pmppriv->antenna_rx;\n\tpHalData->antenna_tx_path = pmppriv->antenna_tx;\n\n\treturn _SUCCESS;\n}\n\nvoid free_mp_priv(struct mp_priv *pmp_priv)\n{\n\tif (pmp_priv->pallocated_mp_xmitframe_buf) {\n\t\trtw_mfree(pmp_priv->pallocated_mp_xmitframe_buf, 0);\n\t\tpmp_priv->pallocated_mp_xmitframe_buf = NULL;\n\t}\n\tpmp_priv->pmp_xmtframe_buf = NULL;\n}\n\n#if 0\nstatic void PHY_IQCalibrate_default(\n\t\tPADAPTER\tpAdapter,\n\t\tBOOLEAN\tbReCovery\n)\n{\n\tRTW_INFO(\"%s\\n\", __func__);\n}\n\nstatic void PHY_LCCalibrate_default(\n\t\tPADAPTER\tpAdapter\n)\n{\n\tRTW_INFO(\"%s\\n\", __func__);\n}\n\nstatic void PHY_SetRFPathSwitch_default(\n\t\tPADAPTER\tpAdapter,\n\t\tBOOLEAN\t\tbMain\n)\n{\n\tRTW_INFO(\"%s\\n\", __func__);\n}\n#endif\n\nvoid mpt_InitHWConfig(PADAPTER Adapter)\n{\n\tPHAL_DATA_TYPE hal;\n\n\thal = GET_HAL_DATA(Adapter);\n\n\tif (IS_HARDWARE_TYPE_8723B(Adapter)) {\n\t\t/* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */\n\t\t/* TODO:  A better solution is configure it according EFUSE during the run-time. */\n\n\t\tphy_set_mac_reg(Adapter, 0x64, BIT20, 0x0);\t\t/* 0x66[4]=0\t\t */\n\t\tphy_set_mac_reg(Adapter, 0x64, BIT24, 0x0);\t\t/* 0x66[8]=0 */\n\t\tphy_set_mac_reg(Adapter, 0x40, BIT4, 0x0);\t\t/* 0x40[4]=0\t\t */\n\t\tphy_set_mac_reg(Adapter, 0x40, BIT3, 0x1);\t\t/* 0x40[3]=1\t\t */\n\t\tphy_set_mac_reg(Adapter, 0x4C, BIT24, 0x1);\t\t/* 0x4C[24:23]=10 */\n\t\tphy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0);\t\t/* 0x4C[24:23]=10 */\n\t\tphy_set_bb_reg(Adapter, 0x944, BIT1 | BIT0, 0x3);\t/* 0x944[1:0]=11\t */\n\t\tphy_set_bb_reg(Adapter, 0x930, bMaskByte0, 0x77);/* 0x930[7:0]=77\t  */\n\t\tphy_set_mac_reg(Adapter, 0x38, BIT11, 0x1);/* 0x38[11]=1 */\n\n\t\t/* TODO: <20130206, Kordan> The default setting is wrong, hard-coded here. */\n\t\tphy_set_mac_reg(Adapter, 0x778, 0x3, 0x3);\t\t\t\t\t/* Turn off hardware PTA control (Asked by Scott) */\n\t\tphy_set_mac_reg(Adapter, 0x64, bMaskDWord, 0x36000000);/* Fix BT S0/S1 */\n\t\tphy_set_mac_reg(Adapter, 0x948, bMaskDWord, 0x0);\t\t/* Fix BT can't Tx */\n\n\t\t/* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou) */\n\t\tphy_set_bb_reg(Adapter, 0xA00, BIT8, 0x0);\t\t\t/*0xA01[0] = 0*/\n\t} else if (IS_HARDWARE_TYPE_8821(Adapter)) {\n\t\t/* <20131121, VincentL> Add for 8821AU DPDT setting and fix switching antenna issue (Asked by Rock)\n\t\t<20131122, VincentL> Enable for all 8821A/8811AU  (Asked by Alex)*/\n\t\tphy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0);\t\t/*0x4C[23:22]=01*/\n\t\tphy_set_mac_reg(Adapter, 0x4C, BIT22, 0x1);\t\t/*0x4C[23:22]=01*/\n\t} else if (IS_HARDWARE_TYPE_8188ES(Adapter))\n\t\tphy_set_mac_reg(Adapter, 0x4C , BIT23, 0);\t\t/*select DPDT_P and DPDT_N as output pin*/\n#ifdef CONFIG_RTL8814A\n\telse if (IS_HARDWARE_TYPE_8814A(Adapter))\n\t\tPlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814A, 0x2000);\n#endif\n\n#ifdef CONFIG_RTL8812A\n\telse if (IS_HARDWARE_TYPE_8812(Adapter)) {\n\t\trtw_write32(Adapter, 0x520, rtw_read32(Adapter, 0x520) | 0x8000);\n\t\trtw_write32(Adapter, 0x524, rtw_read32(Adapter, 0x524) & (~0x800));\n\t}\n#endif\n\n\n#ifdef CONFIG_RTL8822B\n\telse if (IS_HARDWARE_TYPE_8822B(Adapter)) {\n\t\tu32 tmp_reg = 0;\n\n\t\tPlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8822B, 0x2000);\n\t\t/* fixed wifi can't 2.4g tx suggest by Szuyitasi 20160504 */\n\t\tphy_set_bb_reg(Adapter, 0x70, bMaskByte3, 0x0e);\n\t\tRTW_INFO(\" 0x73 = 0x%x\\n\", phy_query_bb_reg(Adapter, 0x70, bMaskByte3));\n\t\tphy_set_bb_reg(Adapter, 0x1704, bMaskDWord, 0x0000ff00);\n\t\tRTW_INFO(\" 0x1704 = 0x%x\\n\", phy_query_bb_reg(Adapter, 0x1704, bMaskDWord));\n\t\tphy_set_bb_reg(Adapter, 0x1700, bMaskDWord, 0xc00f0038);\n\t\tRTW_INFO(\" 0x1700 = 0x%x\\n\", phy_query_bb_reg(Adapter, 0x1700, bMaskDWord));\n\t}\n#endif /* CONFIG_RTL8822B */\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(Adapter))\n\t\tPlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8821C, 0x2000);\n#endif /* CONFIG_RTL8821C */\n#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)\n\telse if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {\n\t\tif (IS_A_CUT(hal->version_id) || IS_B_CUT(hal->version_id)) {\n\t\t\tRTW_INFO(\"%s() Active large power detection\\n\", __func__);\n\t\t\tphy_active_large_power_detection_8188f(&(GET_HAL_DATA(Adapter)->odmpriv));\n\t\t}\n\t}\n#endif\n#if defined(CONFIG_RTL8822C)\n\telse if( IS_HARDWARE_TYPE_8822C(Adapter)) {\n\t\trtw_write16(Adapter, REG_RXFLTMAP1_8822C, 0x2000);\n\t\t/* 0x7D8[31] : time out enable when cca is not assert\n\t\t\t0x60D[7:0] : time out value (Unit : us)*/\n\t\trtw_write8(Adapter, 0x7db, 0xc0);\n\t\tRTW_INFO(\" 0x7d8 = 0x%x\\n\", rtw_read8(Adapter, 0x7d8));\n\t\trtw_write8(Adapter, 0x60d, 0x0c);\n\t\tRTW_INFO(\" 0x60d = 0x%x\\n\", rtw_read8(Adapter, 0x60d));\n\t\tphy_set_bb_reg(Adapter, 0x1c44, BIT10, 0x1);\n\t\tRTW_INFO(\" 0x1c44 = 0x%x\\n\", phy_query_bb_reg(Adapter, 0x1c44, bMaskDWord));\n\t}\n#endif\n\n}\n\nstatic void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery)\n{\n\thalrf_iqk_trigger(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery);\n}\n\nstatic void PHY_LCCalibrate(PADAPTER padapter)\n{\n\thalrf_lck_trigger(&(GET_HAL_DATA(padapter)->odmpriv));\n}\n\nstatic u8 PHY_QueryRFPathSwitch(PADAPTER padapter)\n{\n\tu8 bmain = 0;\n/*\n\tif (IS_HARDWARE_TYPE_8723B(padapter)) {\n#ifdef CONFIG_RTL8723B\n\t\tbmain = PHY_QueryRFPathSwitch_8723B(padapter);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8188E(padapter)) {\n#ifdef CONFIG_RTL8188E\n\t\tbmain = PHY_QueryRFPathSwitch_8188E(padapter);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8814A(padapter)) {\n#ifdef CONFIG_RTL8814A\n\t\tbmain = PHY_QueryRFPathSwitch_8814A(padapter);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\n\t\tbmain = PHY_QueryRFPathSwitch_8812A(padapter);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8192E(padapter)) {\n#ifdef CONFIG_RTL8192E\n\t\tbmain = PHY_QueryRFPathSwitch_8192E(padapter);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8703B(padapter)) {\n#ifdef CONFIG_RTL8703B\n\t\tbmain = PHY_QueryRFPathSwitch_8703B(padapter);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8188F(padapter)) {\n#ifdef CONFIG_RTL8188F\n\t\tbmain = PHY_QueryRFPathSwitch_8188F(padapter);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8188GTV(padapter)) {\n#ifdef CONFIG_RTL8188GTV\n\t\tbmain = PHY_QueryRFPathSwitch_8188GTV(padapter);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8822B(padapter)) {\n#ifdef CONFIG_RTL8822B\n\t\tbmain = PHY_QueryRFPathSwitch_8822B(padapter);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8723D(padapter)) {\n#ifdef CONFIG_RTL8723D\n\t\tbmain = PHY_QueryRFPathSwitch_8723D(padapter);\n#endif\n\t} else\n*/\n\n\tif (IS_HARDWARE_TYPE_8821C(padapter)) {\n#ifdef CONFIG_RTL8821C\n\t\tbmain = phy_query_rf_path_switch_8821c(padapter);\n#endif\n\t}\n\n\treturn bmain;\n}\n\nstatic void  PHY_SetRFPathSwitch(PADAPTER padapter , BOOLEAN bMain) {\n\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);\n\tstruct dm_struct *phydm = &hal->odmpriv;\n\n\tif (IS_HARDWARE_TYPE_8723B(padapter)) {\n#ifdef CONFIG_RTL8723B\n\t\tphy_set_rf_path_switch_8723b(phydm, bMain);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8188E(padapter)) {\n#ifdef CONFIG_RTL8188E\n\t\tphy_set_rf_path_switch_8188e(phydm, bMain);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8814A(padapter)) {\n#ifdef CONFIG_RTL8814A\n\t\tphy_set_rf_path_switch_8814a(phydm, bMain);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\n\t\tphy_set_rf_path_switch_8812a(phydm, bMain);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8192E(padapter)) {\n#ifdef CONFIG_RTL8192E\n\t\tphy_set_rf_path_switch_8192e(phydm, bMain);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8703B(padapter)) {\n#ifdef CONFIG_RTL8703B\n\t\tphy_set_rf_path_switch_8703b(phydm, bMain);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8188F(padapter) || IS_HARDWARE_TYPE_8188GTV(padapter)) {\n#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)\n\t\tphy_set_rf_path_switch_8188f(phydm, bMain);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8192F(padapter)) {\n#ifdef CONFIG_RTL8192F\n\t\tphy_set_rf_path_switch_8192f(padapter, bMain);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8822B(padapter)) {\n#ifdef CONFIG_RTL8822B\n\t\tphy_set_rf_path_switch_8822b(phydm, bMain);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8723D(padapter)) {\n#ifdef CONFIG_RTL8723D\n\t\tphy_set_rf_path_switch_8723d(phydm, bMain);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8821C(padapter)) {\n#ifdef CONFIG_RTL8821C\n\t\tphy_set_rf_path_switch_8821c(phydm, bMain);\n#endif\n\t} else if (IS_HARDWARE_TYPE_8822C(padapter)) {\n#ifdef CONFIG_RTL8822C\n\t\tphy_set_rf_path_switch_8822c(phydm, bMain);\n#endif\n\t}\n}\n\n\nstatic void phy_switch_rf_path_set(PADAPTER padapter , u8 *prf_set_State) {\n#ifdef CONFIG_RTL8821C\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\tstruct dm_struct *p_dm = &pHalData->odmpriv;\n\n\tif (IS_HARDWARE_TYPE_8821C(padapter)) {\n\t\tconfig_phydm_set_ant_path(p_dm, *prf_set_State, p_dm->current_ant_num_8821c);\n\t\t/* Do IQK when switching to BTG/WLG, requested by RF Binson */\n\t\tif (*prf_set_State == SWITCH_TO_BTG || *prf_set_State == SWITCH_TO_WLG)\n\t\t\tPHY_IQCalibrate(padapter, FALSE);\n\t}\n#endif\n\n}\n\n\n#ifdef CONFIG_ANTENNA_DIVERSITY\nu8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\tu8 cur_ant, change_ant;\n\n\tif (!pHalData->AntDivCfg)\n\t\treturn _FALSE;\n\t/*rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL);*/\n\tchange_ant = (bMain == MAIN_ANT) ? MAIN_ANT : AUX_ANT;\n\n\tRTW_INFO(\"%s: config %s\\n\", __func__, (bMain == MAIN_ANT) ? \"MAIN_ANT\" : \"AUX_ANT\");\n\trtw_antenna_select_cmd(padapter, change_ant, _FALSE);\n\n\treturn _TRUE;\n}\n#endif\n\ns32\nMPT_InitializeAdapter(\n\t\tPADAPTER\t\t\tpAdapter,\n\t\tu8\t\t\t\tChannel\n)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\ts32\t\trtStatus = _SUCCESS;\n\tPMPT_CONTEXT\tpMptCtx = &pAdapter->mppriv.mpt_ctx;\n\tu32\t\tledsetting;\n\n\tpMptCtx->bMptDrvUnload = _FALSE;\n\tpMptCtx->bMassProdTest = _FALSE;\n\tpMptCtx->bMptIndexEven = _TRUE;\t/* default gain index is -6.0db */\n\tpMptCtx->h2cReqNum = 0x0;\n\t/* init for BT MP */\n#if defined(CONFIG_RTL8723B)\n\tpMptCtx->bMPh2c_timeout = _FALSE;\n\tpMptCtx->MptH2cRspEvent = _FALSE;\n\tpMptCtx->MptBtC2hEvent = _FALSE;\n\t_rtw_init_sema(&pMptCtx->MPh2c_Sema, 0);\n\trtw_init_timer(&pMptCtx->MPh2c_timeout_timer, pAdapter, MPh2c_timeout_handle, pAdapter);\n#endif\n\n\tmpt_InitHWConfig(pAdapter);\n\n#ifdef CONFIG_RTL8723B\n\trtl8723b_InitAntenna_Selection(pAdapter);\n\tif (IS_HARDWARE_TYPE_8723B(pAdapter)) {\n\n\t\t/* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou)*/\n\t\tphy_set_bb_reg(pAdapter, 0xA00, BIT8, 0x0);\n\t\tPHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /*default use Main*/\n\n\t\tif (pHalData->PackageType == PACKAGE_DEFAULT)\n\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);\n\t\telse\n\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6F10E);\n\n\t}\n\t/*set ant to wifi side in mp mode*/\n\trtw_write16(pAdapter, 0x870, 0x300);\n\trtw_write16(pAdapter, 0x860, 0x110);\n#endif\n\n\tpMptCtx->bMptWorkItemInProgress = _FALSE;\n\tpMptCtx->CurrMptAct = NULL;\n\tpMptCtx->mpt_rf_path = RF_PATH_A;\n\t/* ------------------------------------------------------------------------- */\n\t/* Don't accept any packets */\n\trtw_write32(pAdapter, REG_RCR, 0);\n\n\t/* ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); */\n\t/* rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS); */\n\n\t/* rtw_write32(pAdapter, REG_LEDCFG0, 0x08080); */\n\tledsetting = rtw_read32(pAdapter, REG_LEDCFG0);\n\n\n\tPHY_LCCalibrate(pAdapter);\n\tPHY_IQCalibrate(pAdapter, _FALSE);\n\t/* dm_check_txpowertracking(&pHalData->odmpriv);\t*/ /* trigger thermal meter */\n\n\tPHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /* default use Main */\n\n\tpMptCtx->backup0xc50 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);\n\tpMptCtx->backup0xc58 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);\n\tpMptCtx->backup0xc30 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);\n\tpMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);\n\tpMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);\n#ifdef CONFIG_RTL8188E\n\trtw_write32(pAdapter, REG_MACID_NO_LINK_0, 0x0);\n\trtw_write32(pAdapter, REG_MACID_NO_LINK_1, 0x0);\n#endif\n#ifdef CONFIG_RTL8814A\n\tif (IS_HARDWARE_TYPE_8814A(pAdapter)) {\n\t\tpHalData->BackUp_IG_REG_4_Chnl_Section[0] = (u8)phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);\n\t\tpHalData->BackUp_IG_REG_4_Chnl_Section[1] = (u8)phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);\n\t\tpHalData->BackUp_IG_REG_4_Chnl_Section[2] = (u8)phy_query_bb_reg(pAdapter, rC_IGI_Jaguar2, bMaskByte0);\n\t\tpHalData->BackUp_IG_REG_4_Chnl_Section[3] = (u8)phy_query_bb_reg(pAdapter, rD_IGI_Jaguar2, bMaskByte0);\n\t}\n#endif\n\treturn\trtStatus;\n}\n\n/*-----------------------------------------------------------------------------\n * Function:\tMPT_DeInitAdapter()\n *\n * Overview:\tExtra DeInitialization for Mass Production Test.\n *\n * Input:\t\tPADAPTER\tpAdapter\n *\n * Output:\t\tNONE\n *\n * Return:\t\tNONE\n *\n * Revised History:\n *\tWhen\t\tWho\t\tRemark\n *\t05/08/2007\tMHC\t\tCreate Version 0.\n *\t05/18/2007\tMHC\t\tAdd normal driver MPHalt code.\n *\n *---------------------------------------------------------------------------*/\nvoid\nMPT_DeInitAdapter(\n\t\tPADAPTER\tpAdapter\n)\n{\n\tPMPT_CONTEXT\t\tpMptCtx = &pAdapter->mppriv.mpt_ctx;\n\n\tpMptCtx->bMptDrvUnload = _TRUE;\n#if defined(CONFIG_RTL8723B)\n\t_rtw_free_sema(&(pMptCtx->MPh2c_Sema));\n\t_cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);\n#endif\n#if\tdefined(CONFIG_RTL8723B)\n\tphy_set_bb_reg(pAdapter, 0xA01, BIT0, 1); /* /suggestion  by jerry for MP Rx. */\n#endif\n#if 0 /* for Windows */\n\tPlatformFreeWorkItem(&(pMptCtx->MptWorkItem));\n\n\twhile (pMptCtx->bMptWorkItemInProgress) {\n\t\tif (NdisWaitEvent(&(pMptCtx->MptWorkItemEvent), 50))\n\t\t\tbreak;\n\t}\n\tNdisFreeSpinLock(&(pMptCtx->MptWorkItemSpinLock));\n#endif\n}\n\nstatic u8 mpt_ProStartTest(PADAPTER padapter)\n{\n\tPMPT_CONTEXT pMptCtx = &padapter->mppriv.mpt_ctx;\n\n\tpMptCtx->bMassProdTest = _TRUE;\n\tpMptCtx->is_start_cont_tx = _FALSE;\n\tpMptCtx->bCckContTx = _FALSE;\n\tpMptCtx->bOfdmContTx = _FALSE;\n\tpMptCtx->bSingleCarrier = _FALSE;\n\tpMptCtx->is_carrier_suppression = _FALSE;\n\tpMptCtx->is_single_tone = _FALSE;\n\tpMptCtx->HWTxmode = PACKETS_TX;\n\n\treturn _SUCCESS;\n}\n\n/*\n * General use\n */\ns32 SetPowerTracking(PADAPTER padapter, u8 enable)\n{\n\n\thal_mpt_SetPowerTracking(padapter, enable);\n\treturn 0;\n}\n\nvoid GetPowerTracking(PADAPTER padapter, u8 *enable)\n{\n\thal_mpt_GetPowerTracking(padapter, enable);\n}\n\nvoid rtw_mp_trigger_iqk(PADAPTER padapter)\n{\n\tPHY_IQCalibrate(padapter, _FALSE);\n}\n\nvoid rtw_mp_trigger_lck(PADAPTER padapter)\n{\n\tPHY_LCCalibrate(padapter);\n}\n\nvoid rtw_mp_trigger_dpk(PADAPTER padapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct dm_struct\t\t*pDM_Odm = &pHalData->odmpriv;\n\n\thalrf_dpk_trigger(pDM_Odm);\n}\n\nstatic void init_mp_data(PADAPTER padapter)\n{\n\tu8 v8;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct dm_struct\t\t*pDM_Odm = &pHalData->odmpriv;\n\n\t/*disable BCN*/\n\tv8 = rtw_read8(padapter, REG_BCN_CTRL);\n\tv8 &= ~EN_BCN_FUNCTION;\n\trtw_write8(padapter, REG_BCN_CTRL, v8);\n\n\tpDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;\n}\n\nvoid MPT_PwrCtlDM(PADAPTER padapter, u32 bstart)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct dm_struct\t\t*pDM_Odm = &pHalData->odmpriv;\n\tu32\trf_ability;\n\n\tif (bstart == 1) {\n\t\tRTW_INFO(\"in MPT_PwrCtlDM start\\n\");\n\n\t\trf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) | HAL_RF_TX_PWR_TRACK;\n\t\thalrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);\n\t\thalrf_set_pwr_track(pDM_Odm, true);\n\t\tpDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;\n\t\tpadapter->mppriv.mp_dm = 1;\n\n\t} else {\n\t\tRTW_INFO(\"in MPT_PwrCtlDM stop\\n\");\n\t\trf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) & ~HAL_RF_TX_PWR_TRACK;\n\t\thalrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);\n\t\thalrf_set_pwr_track(pDM_Odm, false);\n\t\tpDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;\n\t\tif (IS_HARDWARE_TYPE_8822C(padapter))\n\t\t\tpadapter->mppriv.mp_dm = 1; /* default enable dpk tracking */\n\t\telse\n\t\t\tpadapter->mppriv.mp_dm = 0;\n\t\t{\n\t\t\tstruct txpwrtrack_cfg c;\n\t\t\tu8\tchnl = 0 ;\n\t\t\t_rtw_memset(&c, 0, sizeof(struct txpwrtrack_cfg));\n\t\t\tconfigure_txpower_track(pDM_Odm, &c);\n\t\t\todm_clear_txpowertracking_state(pDM_Odm);\n\t\t\tif (*c.odm_tx_pwr_track_set_pwr) {\n\t\t\t\tif (pDM_Odm->support_ic_type == ODM_RTL8188F)\n\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl);\n\t\t\t\telse if (pDM_Odm->support_ic_type == ODM_RTL8723D) {\n\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);\n\t\t\t\t\tSetTxPower(padapter);\n\t\t\t\t} else if (pDM_Odm->support_ic_type == ODM_RTL8192F) {\n\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl);\n\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_B, chnl);\n\t\t\t\t} else {\n\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);\n\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_B, chnl);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n}\n\n\nu32 mp_join(PADAPTER padapter, u8 mode)\n{\n\tWLAN_BSSID_EX bssid;\n\tstruct sta_info *psta;\n\tu32 length;\n\t_irqL irqL;\n\ts32 res = _SUCCESS;\n\n\tstruct mp_priv *pmppriv = &padapter->mppriv;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct wlan_network *tgt_network = &pmlmepriv->cur_network;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t\t*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));\n\n\t/* 1. initialize a new WLAN_BSSID_EX */\n\t_rtw_memset(&bssid, 0, sizeof(WLAN_BSSID_EX));\n\tRTW_INFO(\"%s ,pmppriv->network_macaddr=%x %x %x %x %x %x\\n\", __func__,\n\t\tpmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],\n\t\t pmppriv->network_macaddr[5]);\n\t_rtw_memcpy(bssid.MacAddress, pmppriv->network_macaddr, ETH_ALEN);\n\n\tif (mode == WIFI_FW_ADHOC_STATE) {\n\t\tbssid.Ssid.SsidLength = strlen(\"mp_pseudo_adhoc\");\n\t\t_rtw_memcpy(bssid.Ssid.Ssid, (u8 *)\"mp_pseudo_adhoc\", bssid.Ssid.SsidLength);\n\t\tbssid.InfrastructureMode = Ndis802_11IBSS;\n\t\tbssid.IELength = 0;\n\t\tbssid.Configuration.DSConfig = pmppriv->channel;\n\n\t} else if (mode == WIFI_FW_STATION_STATE) {\n\t\tbssid.Ssid.SsidLength = strlen(\"mp_pseudo_STATION\");\n\t\t_rtw_memcpy(bssid.Ssid.Ssid, (u8 *)\"mp_pseudo_STATION\", bssid.Ssid.SsidLength);\n\t\tbssid.InfrastructureMode = Ndis802_11Infrastructure;\n\t\tbssid.IELength = 0;\n\t}\n\n\tlength = get_WLAN_BSSID_EX_sz(&bssid);\n\tif (length % 4)\n\t\tbssid.Length = ((length >> 2) + 1) << 2; /* round up to multiple of 4 bytes. */\n\telse\n\t\tbssid.Length = length;\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\n\tif (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)\n\t\tgoto end_of_mp_start_test;\n\n\t/* init mp_start_test status */\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {\n\t\trtw_disassoc_cmd(padapter, 500, 0);\n\t\trtw_indicate_disconnect(padapter, 0, _FALSE);\n\t\trtw_free_assoc_resources_cmd(padapter, _TRUE, 0);\n\t}\n\tpmppriv->prev_fw_state = get_fwstate(pmlmepriv);\n\t/*pmlmepriv->fw_state = WIFI_MP_STATE;*/\n\tinit_fwstate(pmlmepriv, WIFI_MP_STATE);\n\n\tset_fwstate(pmlmepriv, _FW_UNDER_LINKING);\n\n\t/* 3 2. create a new psta for mp driver */\n\t/* clear psta in the cur_network, if any */\n\tpsta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);\n\tif (psta)\n\t\trtw_free_stainfo(padapter, psta);\n\n\tpsta = rtw_alloc_stainfo(&padapter->stapriv, bssid.MacAddress);\n\tif (psta == NULL) {\n\t\t/*pmlmepriv->fw_state = pmppriv->prev_fw_state;*/\n\t\tinit_fwstate(pmlmepriv, pmppriv->prev_fw_state);\n\t\tres = _FAIL;\n\t\tgoto end_of_mp_start_test;\n\t}\n\tif (mode == WIFI_FW_ADHOC_STATE)\n\tset_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);\n\telse\n\t\tset_fwstate(pmlmepriv, WIFI_STATION_STATE);\n\t/* 3 3. join psudo AdHoc */\n\ttgt_network->join_res = 1;\n\ttgt_network->aid = psta->cmn.aid = 1;\n\n\t_rtw_memcpy(&padapter->registrypriv.dev_network, &bssid, length);\n\trtw_update_registrypriv_dev_network(padapter);\n\t_rtw_memcpy(&tgt_network->network, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);\n\t_rtw_memcpy(pnetwork, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);\n\n\trtw_indicate_connect(padapter);\n\t_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);\n\tset_fwstate(pmlmepriv, _FW_LINKED);\n\nend_of_mp_start_test:\n\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\n\tif (1) { /* (res == _SUCCESS) */\n\t\t/* set MSR to WIFI_FW_ADHOC_STATE */\n\t\tif (mode == WIFI_FW_ADHOC_STATE) {\n\t\t\t/* set msr to WIFI_FW_ADHOC_STATE */\n\t\t\tpmlmeinfo->state = WIFI_FW_ADHOC_STATE;\n\t\t\tSet_MSR(padapter, (pmlmeinfo->state & 0x3));\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress);\n\t\t\trtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);\n\t\t\tpmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;\n\t\t} else {\n\t\t\tSet_MSR(padapter, WIFI_FW_STATION_STATE);\n\n\t\t\tRTW_INFO(\"%s , pmppriv->network_macaddr =%x %x %x %x %x %x\\n\", __func__,\n\t\t\t\tpmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],\n\t\t\t\t pmppriv->network_macaddr[5]);\n\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmppriv->network_macaddr);\n\t\t}\n\t}\n\n\treturn res;\n}\n/* This function initializes the DUT to the MP test mode */\ns32 mp_start_test(PADAPTER padapter)\n{\n\tstruct mp_priv *pmppriv = &padapter->mppriv;\n#ifdef CONFIG_PCI_HCI\n\tPHAL_DATA_TYPE hal;\n#endif\n\ts32 res = _SUCCESS;\n\n\tpadapter->registrypriv.mp_mode = 1;\n\n\tinit_mp_data(padapter);\n#ifdef CONFIG_RTL8814A\n\trtl8814_InitHalDm(padapter);\n#endif /* CONFIG_RTL8814A */\n#ifdef CONFIG_RTL8812A\n\trtl8812_InitHalDm(padapter);\n#endif /* CONFIG_RTL8812A */\n#ifdef CONFIG_RTL8723B\n\trtl8723b_InitHalDm(padapter);\n#endif /* CONFIG_RTL8723B */\n#ifdef CONFIG_RTL8703B\n\trtl8703b_InitHalDm(padapter);\n#endif /* CONFIG_RTL8703B */\n#ifdef CONFIG_RTL8192E\n\trtl8192e_InitHalDm(padapter);\n#endif\n#ifdef CONFIG_RTL8188F\n\trtl8188f_InitHalDm(padapter);\n#endif\n#ifdef CONFIG_RTL8188GTV\n\trtl8188gtv_InitHalDm(padapter);\n#endif\n#ifdef CONFIG_RTL8188E\n\trtl8188e_InitHalDm(padapter);\n#endif\n#ifdef CONFIG_RTL8723D\n\trtl8723d_InitHalDm(padapter);\n#endif /* CONFIG_RTL8723D */\n\n#ifdef CONFIG_PCI_HCI\n\thal = GET_HAL_DATA(padapter);\n\thal->pci_backdoor_ctrl = 0;\n\trtw_pci_aspm_config(padapter);\n#endif\n\n\n\t/* 3 0. update mp_priv */\n\n\tif (!RF_TYPE_VALID(padapter->registrypriv.rf_config)) {\n\t\t/*\t\tswitch (phal->rf_type) { */\n\t\tswitch (GET_RF_TYPE(padapter)) {\n\t\tcase RF_1T1R:\n\t\t\tpmppriv->antenna_tx = ANTENNA_A;\n\t\t\tpmppriv->antenna_rx = ANTENNA_A;\n\t\t\tbreak;\n\t\tcase RF_1T2R:\n\t\tdefault:\n\t\t\tpmppriv->antenna_tx = ANTENNA_A;\n\t\t\tpmppriv->antenna_rx = ANTENNA_AB;\n\t\t\tbreak;\n\t\tcase RF_2T2R:\n\t\t\tpmppriv->antenna_tx = ANTENNA_AB;\n\t\t\tpmppriv->antenna_rx = ANTENNA_AB;\n\t\t\tbreak;\n\t\tcase RF_2T4R:\n\t\t\tpmppriv->antenna_tx = ANTENNA_AB;\n\t\t\tpmppriv->antenna_rx = ANTENNA_ABCD;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tmpt_ProStartTest(padapter);\n\n\tmp_join(padapter, WIFI_FW_ADHOC_STATE);\n\n\treturn res;\n}\n/* ------------------------------------------------------------------------------\n * This function change the DUT from the MP test mode into normal mode */\nvoid mp_stop_test(PADAPTER padapter)\n{\n\tstruct mp_priv *pmppriv = &padapter->mppriv;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct wlan_network *tgt_network = &pmlmepriv->cur_network;\n\tstruct sta_info *psta;\n#ifdef CONFIG_PCI_HCI\n\tstruct registry_priv  *registry_par = &padapter->registrypriv;\n\tPHAL_DATA_TYPE hal;\n#endif\n\n\t_irqL irqL;\n\n\tif (pmppriv->mode == MP_ON) {\n\t\tpmppriv->bSetTxPower = 0;\n\t\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\t\tif (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)\n\t\t\tgoto end_of_mp_stop_test;\n\n\t\t/* 3 1. disconnect psudo AdHoc */\n\t\trtw_indicate_disconnect(padapter, 0, _FALSE);\n\n\t\t/* 3 2. clear psta used in mp test mode.\n\t\t*\trtw_free_assoc_resources(padapter, _TRUE); */\n\t\tpsta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);\n\t\tif (psta)\n\t\t\trtw_free_stainfo(padapter, psta);\n\n\t\t/* 3 3. return to normal state (default:station mode) */\n\t\t/*pmlmepriv->fw_state = pmppriv->prev_fw_state; */ /* WIFI_STATION_STATE;*/\n\t\tinit_fwstate(pmlmepriv, pmppriv->prev_fw_state);\n\n\t\t/* flush the cur_network */\n\t\t_rtw_memset(tgt_network, 0, sizeof(struct wlan_network));\n\n\t\t_clr_fwstate_(pmlmepriv, WIFI_MP_STATE);\n\nend_of_mp_stop_test:\n\n\t\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\n#ifdef CONFIG_PCI_HCI\n\t\thal = GET_HAL_DATA(padapter);\n\t\thal->pci_backdoor_ctrl = registry_par->pci_aspm_config;\n\t\trtw_pci_aspm_config(padapter);\n#endif\n\n#ifdef CONFIG_RTL8812A\n\t\trtl8812_InitHalDm(padapter);\n#endif\n#ifdef CONFIG_RTL8723B\n\t\trtl8723b_InitHalDm(padapter);\n#endif\n#ifdef CONFIG_RTL8703B\n\t\trtl8703b_InitHalDm(padapter);\n#endif\n#ifdef CONFIG_RTL8192E\n\t\trtl8192e_InitHalDm(padapter);\n#endif\n#ifdef CONFIG_RTL8188F\n\t\trtl8188f_InitHalDm(padapter);\n#endif\n#ifdef CONFIG_RTL8188GTV\n\t\trtl8188gtv_InitHalDm(padapter);\n#endif\n#ifdef CONFIG_RTL8723D\n\t\trtl8723d_InitHalDm(padapter);\n#endif\n\t}\n}\n/*---------------------------hal\\rtl8192c\\MPT_Phy.c---------------------------*/\n#if 0\n/* #ifdef CONFIG_USB_HCI */\nstatic void mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Channel, u8 BandWidthID)\n{\n\tu8\t\teRFPath;\n\tu32\t\trfReg0x26;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\n\n\tif (RateIdx < MPT_RATE_6M) \t/* CCK rate,for 88cu */\n\t\trfReg0x26 = 0xf400;\n\telse if ((RateIdx >= MPT_RATE_6M) && (RateIdx <= MPT_RATE_54M)) {/* OFDM rate,for 88cu */\n\t\tif ((4 == Channel) || (8 == Channel) || (12 == Channel))\n\t\t\trfReg0x26 = 0xf000;\n\t\telse if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))\n\t\t\trfReg0x26 = 0xf400;\n\t\telse\n\t\t\trfReg0x26 = 0x4f200;\n\t} else if ((RateIdx >= MPT_RATE_MCS0) && (RateIdx <= MPT_RATE_MCS15)) {\n\t\t/* MCS 20M ,for 88cu */ /* MCS40M rate,for 88cu */\n\n\t\tif (CHANNEL_WIDTH_20 == BandWidthID) {\n\t\t\tif ((4 == Channel) || (8 == Channel))\n\t\t\t\trfReg0x26 = 0xf000;\n\t\t\telse if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))\n\t\t\t\trfReg0x26 = 0xf400;\n\t\t\telse\n\t\t\t\trfReg0x26 = 0x4f200;\n\t\t} else {\n\t\t\tif ((4 == Channel) || (8 == Channel))\n\t\t\t\trfReg0x26 = 0xf000;\n\t\t\telse if ((5 == Channel) || (7 == Channel))\n\t\t\t\trfReg0x26 = 0xf400;\n\t\t\telse\n\t\t\t\trfReg0x26 = 0x4f200;\n\t\t}\n\t}\n\n\tfor (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)\n\t\twrite_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26);\n}\n#endif\n/*-----------------------------------------------------------------------------\n * Function:\tmpt_SwitchRfSetting\n *\n * Overview:\tChange RF Setting when we siwthc channel/rate/BW for MP.\n *\n * Input:       \tPADAPTER\t\t\t\tpAdapter\n *\n * Output:      NONE\n *\n * Return:      NONE\n *\n * Revised History:\n * When\t\t\tWho\t\tRemark\n * 01/08/2009\tMHC\t\tSuggestion from SD3 Willis for 92S series.\n * 01/09/2009\tMHC\t\tAdd CCK modification for 40MHZ. Suggestion from SD3.\n *\n *---------------------------------------------------------------------------*/\n#if 0\nstatic void mpt_SwitchRfSetting(PADAPTER pAdapter)\n{\n\thal_mpt_SwitchRfSetting(pAdapter);\n}\n\n/*---------------------------hal\\rtl8192c\\MPT_Phy.c---------------------------*/\n/*---------------------------hal\\rtl8192c\\MPT_HelperFunc.c---------------------------*/\nstatic void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)\n{\n\thal_mpt_CCKTxPowerAdjust(Adapter, bInCH14);\n}\n#endif\n\n/*---------------------------hal\\rtl8192c\\MPT_HelperFunc.c---------------------------*/\n\n/*\n * SetChannel\n * Description\n *\tUse H2C command to change channel,\n *\tnot only modify rf register, but also other setting need to be done.\n */\nvoid SetChannel(PADAPTER pAdapter)\n{\n\thal_mpt_SetChannel(pAdapter);\n}\n\n/*\n * Notice\n *\tSwitch bandwitdth may change center frequency(channel)\n */\nvoid SetBandwidth(PADAPTER pAdapter)\n{\n\thal_mpt_SetBandwidth(pAdapter);\n\n}\n\nvoid SetAntenna(PADAPTER pAdapter)\n{\n\thal_mpt_SetAntenna(pAdapter);\n}\n\nint SetTxPower(PADAPTER pAdapter)\n{\n\n\thal_mpt_SetTxPower(pAdapter);\n\treturn _TRUE;\n}\n\nvoid SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)\n{\n\tu32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;\n\n\tTxAGCOffset_B = (ulTxAGCOffset & 0x000000ff);\n\tTxAGCOffset_C = ((ulTxAGCOffset & 0x0000ff00) >> 8);\n\tTxAGCOffset_D = ((ulTxAGCOffset & 0x00ff0000) >> 16);\n\n\ttmpAGC = (TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B);\n\twrite_bbreg(pAdapter, rFPGA0_TxGainStage,\n\t\t    (bXBTxAGC | bXCTxAGC | bXDTxAGC), tmpAGC);\n}\n\nvoid SetDataRate(PADAPTER pAdapter)\n{\n\thal_mpt_SetDataRate(pAdapter);\n}\n\nvoid MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain)\n{\n\n\tPHY_SetRFPathSwitch(pAdapter, bMain);\n\n}\n\nvoid mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate)\n{\n\n\tphy_switch_rf_path_set(pAdapter, pstate);\n\n}\n\nu8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter)\n{\n\treturn PHY_QueryRFPathSwitch(pAdapter);\n}\n\ns32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther)\n{\n\treturn hal_mpt_SetThermalMeter(pAdapter, target_ther);\n}\n\n#if 0\nstatic void TriggerRFThermalMeter(PADAPTER pAdapter)\n{\n\thal_mpt_TriggerRFThermalMeter(pAdapter);\n}\n\nstatic u8 ReadRFThermalMeter(PADAPTER pAdapter)\n{\n\treturn hal_mpt_ReadRFThermalMeter(pAdapter);\n}\n#endif\n\nvoid GetThermalMeter(PADAPTER pAdapter, u8 rfpath ,u8 *value)\n{\n\thal_mpt_GetThermalMeter(pAdapter, rfpath, value);\n}\n\nvoid SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)\n{\n\tPhySetTxPowerLevel(pAdapter);\n\thal_mpt_SetSingleCarrierTx(pAdapter, bStart);\n}\n\nvoid SetSingleToneTx(PADAPTER pAdapter, u8 bStart)\n{\n\tPhySetTxPowerLevel(pAdapter);\n\thal_mpt_SetSingleToneTx(pAdapter, bStart);\n}\n\nvoid SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)\n{\n\tPhySetTxPowerLevel(pAdapter);\n\thal_mpt_SetCarrierSuppressionTx(pAdapter, bStart);\n}\n\nvoid SetContinuousTx(PADAPTER pAdapter, u8 bStart)\n{\n\tPhySetTxPowerLevel(pAdapter);\n\thal_mpt_SetContinuousTx(pAdapter, bStart);\n}\n\n\nvoid PhySetTxPowerLevel(PADAPTER pAdapter)\n{\n\tstruct mp_priv *pmp_priv = &pAdapter->mppriv;\n\n\n\tif (pmp_priv->bSetTxPower == 0) /* for NO manually set power index */\n\t\trtw_hal_set_tx_power_level(pAdapter, pmp_priv->channel);\n}\n\n/* ------------------------------------------------------------------------------ */\nstatic void dump_mpframe(PADAPTER padapter, struct xmit_frame *pmpframe)\n{\n\trtw_hal_mgnt_xmit(padapter, pmpframe);\n}\n\nstatic struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv)\n{\n\tstruct xmit_frame\t*pmpframe;\n\tstruct xmit_buf\t*pxmitbuf;\n\n\tpmpframe = rtw_alloc_xmitframe(pxmitpriv);\n\tif (pmpframe == NULL)\n\t\treturn NULL;\n\n\tpxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);\n\tif (pxmitbuf == NULL) {\n\t\trtw_free_xmitframe(pxmitpriv, pmpframe);\n\t\treturn NULL;\n\t}\n\n\tpmpframe->frame_tag = MP_FRAMETAG;\n\n\tpmpframe->pxmitbuf = pxmitbuf;\n\n\tpmpframe->buf_addr = pxmitbuf->pbuf;\n\n\tpxmitbuf->priv_data = pmpframe;\n\n\treturn pmpframe;\n\n}\n\n#ifdef CONFIG_PCI_HCI\nstatic u8 check_nic_enough_desc(_adapter *padapter, struct pkt_attrib *pattrib)\n{\n\tu32 prio;\n\tstruct xmit_priv\t*pxmitpriv = &padapter->xmitpriv;\n\tstruct rtw_tx_ring\t*ring;\n\n\tswitch (pattrib->qsel) {\n\tcase 0:\n\tcase 3:\n\t\tprio = BE_QUEUE_INX;\n\t\tbreak;\n\tcase 1:\n\tcase 2:\n\t\tprio = BK_QUEUE_INX;\n\t\tbreak;\n\tcase 4:\n\tcase 5:\n\t\tprio = VI_QUEUE_INX;\n\t\tbreak;\n\tcase 6:\n\tcase 7:\n\t\tprio = VO_QUEUE_INX;\n\t\tbreak;\n\tdefault:\n\t\tprio = BE_QUEUE_INX;\n\t\tbreak;\n\t}\n\n\tring = &pxmitpriv->tx_ring[prio];\n\n\t/*\n\t * for now we reserve two free descriptor as a safety boundary\n\t * between the tail and the head\n\t */\n\tif ((ring->entries - ring->qlen) >= 2)\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\n#endif\n\nstatic thread_return mp_xmit_packet_thread(thread_context context)\n{\n\tstruct xmit_frame\t*pxmitframe;\n\tstruct mp_tx\t\t*pmptx;\n\tstruct mp_priv\t*pmp_priv;\n\tstruct xmit_priv\t*pxmitpriv;\n\tPADAPTER padapter;\n\n\tpmp_priv = (struct mp_priv *)context;\n\tpmptx = &pmp_priv->tx;\n\tpadapter = pmp_priv->papdater;\n\tpxmitpriv = &(padapter->xmitpriv);\n\n\tthread_enter(\"RTW_MP_THREAD\");\n\n\tRTW_INFO(\"%s:pkTx Start\\n\", __func__);\n\twhile (1) {\n\t\tpxmitframe = alloc_mp_xmitframe(pxmitpriv);\n#ifdef CONFIG_PCI_HCI\n\t\tif(check_nic_enough_desc(padapter, &pmptx->attrib) == _FALSE) {\n\t\t\trtw_usleep_os(1000);\n\t\t\tcontinue;\n\t\t}\n#endif\n\t\tif (pxmitframe == NULL) {\n\t\t\tif (pmptx->stop ||\n\t\t\t    RTW_CANNOT_RUN(padapter))\n\t\t\t\tgoto exit;\n\t\t\telse {\n\t\t\t\trtw_usleep_os(10);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t}\n\t\t_rtw_memcpy((u8 *)(pxmitframe->buf_addr + TXDESC_OFFSET), pmptx->buf, pmptx->write_size);\n\t\t_rtw_memcpy(&(pxmitframe->attrib), &(pmptx->attrib), sizeof(struct pkt_attrib));\n\n\n\t\trtw_usleep_os(padapter->mppriv.pktInterval);\n\t\tdump_mpframe(padapter, pxmitframe);\n\n\t\tpmptx->sended++;\n\t\tpmp_priv->tx_pktcount++;\n\n\t\tif (pmptx->stop ||\n\t\t    RTW_CANNOT_RUN(padapter))\n\t\t\tgoto exit;\n\t\tif ((pmptx->count != 0) &&\n\t\t    (pmptx->count == pmptx->sended))\n\t\t\tgoto exit;\n\n\t\tflush_signals_thread();\n\t}\n\nexit:\n\t/* RTW_INFO(\"%s:pkTx Exit\\n\", __func__); */\n\trtw_mfree(pmptx->pallocated_buf, pmptx->buf_size);\n\tpmptx->pallocated_buf = NULL;\n\tpmptx->stop = 1;\n\n\tthread_exit(NULL);\n\treturn 0;\n}\n\nvoid fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc)\n{\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\t_rtw_memcpy(ptxdesc, pmp_priv->tx.desc, TXDESC_SIZE);\n}\n\n#if defined(CONFIG_RTL8188E)\nvoid fill_tx_desc_8188e(PADAPTER padapter)\n{\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\tstruct tx_desc *desc   = (struct tx_desc *)&(pmp_priv->tx.desc);\n\tstruct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);\n\tu32\tpkt_size = pattrib->last_txcmdsz;\n\ts32 bmcast = IS_MCAST(pattrib->ra);\n\t/* offset 0 */\n#if !defined(CONFIG_RTL8188E_SDIO) && !defined(CONFIG_PCI_HCI)\n\tdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);\n\tdesc->txdw0 |= cpu_to_le32(pkt_size & 0x0000FFFF); /* packet size */\n\tdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00FF0000); /* 32 bytes for TX Desc */\n\tif (bmcast)\n\t\tdesc->txdw0 |= cpu_to_le32(BMC); /* broadcast packet */\n\n\tdesc->txdw1 |= cpu_to_le32((0x01 << 26) & 0xff000000);\n#endif\n\n\tdesc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x3F); /* CAM_ID(MAC_ID) */\n\tdesc->txdw1 |= cpu_to_le32((pattrib->qsel << QSEL_SHT) & 0x00001F00); /* Queue Select, TID */\n\tdesc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000); /* Rate Adaptive ID */\n\t/* offset 8 */\n\t/* desc->txdw2 |= cpu_to_le32(AGG_BK); */ /* AGG BK */\n\n\tdesc->txdw3 |= cpu_to_le32((pattrib->seqnum << 16) & 0x0fff0000);\n\tdesc->txdw4 |= cpu_to_le32(HW_SSN);\n\n\tdesc->txdw4 |= cpu_to_le32(USERATE);\n\tdesc->txdw4 |= cpu_to_le32(DISDATAFB);\n\n\tif (pmp_priv->preamble) {\n\t\tif (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)\n\t\t\tdesc->txdw4 |= cpu_to_le32(DATA_SHORT); /* CCK Short Preamble */\n\t}\n\n\tif (pmp_priv->bandwidth == CHANNEL_WIDTH_40)\n\t\tdesc->txdw4 |= cpu_to_le32(DATA_BW);\n\n\t/* offset 20 */\n\tdesc->txdw5 |= cpu_to_le32(pmp_priv->rateidx & 0x0000001F);\n\n\tif (pmp_priv->preamble) {\n\t\tif (HwRateToMPTRate(pmp_priv->rateidx) > MPT_RATE_54M)\n\t\t\tdesc->txdw5 |= cpu_to_le32(SGI); /* MCS Short Guard Interval */\n\t}\n\n\tdesc->txdw5 |= cpu_to_le32(RTY_LMT_EN); /* retry limit enable */\n\tdesc->txdw5 |= cpu_to_le32(0x00180000); /* DATA/RTS Rate Fallback Limit\t */\n\n\n}\n#endif\n\n#if defined(CONFIG_RTL8814A)\nvoid fill_tx_desc_8814a(PADAPTER padapter)\n{\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\tu8 *pDesc   = (u8 *)&(pmp_priv->tx.desc);\n\tstruct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);\n\n\tu32\tpkt_size = pattrib->last_txcmdsz;\n\ts32 bmcast = IS_MCAST(pattrib->ra);\n\tu8 offset;\n\n\t/* SET_TX_DESC_FIRST_SEG_8814A(pDesc, 1); */\n\tSET_TX_DESC_LAST_SEG_8814A(pDesc, 1);\n\t/* SET_TX_DESC_OWN_(pDesc, 1); */\n\n\tSET_TX_DESC_PKT_SIZE_8814A(pDesc, pkt_size);\n\n\toffset = TXDESC_SIZE + OFFSET_SZ;\n\n\tSET_TX_DESC_OFFSET_8814A(pDesc, offset);\n#if defined(CONFIG_PCI_HCI)\n\tSET_TX_DESC_PKT_OFFSET_8814A(pDesc, 0); /* 8814AE pkt_offset is 0 */\n#else\n\tSET_TX_DESC_PKT_OFFSET_8814A(pDesc, 1);\n#endif\n\n\tif (bmcast)\n\t\tSET_TX_DESC_BMC_8814A(pDesc, 1);\n\n\tSET_TX_DESC_MACID_8814A(pDesc, pattrib->mac_id);\n\tSET_TX_DESC_RATE_ID_8814A(pDesc, pattrib->raid);\n\n\t/* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */\n\tSET_TX_DESC_QUEUE_SEL_8814A(pDesc,  pattrib->qsel);\n\t/* SET_TX_DESC_QUEUE_SEL_8812(pDesc,  QSLT_MGNT); */\n\n\tif (pmp_priv->preamble)\n\t\tSET_TX_DESC_DATA_SHORT_8814A(pDesc, 1);\n\n\tif (!pattrib->qos_en) {\n\t\tSET_TX_DESC_HWSEQ_EN_8814A(pDesc, 1); /* Hw set sequence number */\n\t} else\n\t\tSET_TX_DESC_SEQ_8814A(pDesc, pattrib->seqnum);\n\n\tif (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)\n\t\tSET_TX_DESC_DATA_BW_8814A(pDesc, pmp_priv->bandwidth);\n\telse {\n\t\tRTW_INFO(\"%s:Err: unknown bandwidth %d, use 20M\\n\", __func__, pmp_priv->bandwidth);\n\t\tSET_TX_DESC_DATA_BW_8814A(pDesc, CHANNEL_WIDTH_20);\n\t}\n\n\tSET_TX_DESC_DISABLE_FB_8814A(pDesc, 1);\n\tSET_TX_DESC_USE_RATE_8814A(pDesc, 1);\n\tSET_TX_DESC_TX_RATE_8814A(pDesc, pmp_priv->rateidx);\n\n}\n#endif\n\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\nvoid fill_tx_desc_8812a(PADAPTER padapter)\n{\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\tu8 *pDesc   = (u8 *)&(pmp_priv->tx.desc);\n\tstruct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);\n\n\tu32\tpkt_size = pattrib->last_txcmdsz;\n\ts32 bmcast = IS_MCAST(pattrib->ra);\n\tu8 data_rate, pwr_status, offset;\n\n\tSET_TX_DESC_FIRST_SEG_8812(pDesc, 1);\n\tSET_TX_DESC_LAST_SEG_8812(pDesc, 1);\n\tSET_TX_DESC_OWN_8812(pDesc, 1);\n\n\tSET_TX_DESC_PKT_SIZE_8812(pDesc, pkt_size);\n\n\toffset = TXDESC_SIZE + OFFSET_SZ;\n\n\tSET_TX_DESC_OFFSET_8812(pDesc, offset);\n\n#if defined(CONFIG_PCI_HCI)\n\tSET_TX_DESC_PKT_OFFSET_8812(pDesc, 0);\n#else\n\tSET_TX_DESC_PKT_OFFSET_8812(pDesc, 1);\n#endif\n\tif (bmcast)\n\t\tSET_TX_DESC_BMC_8812(pDesc, 1);\n\n\tSET_TX_DESC_MACID_8812(pDesc, pattrib->mac_id);\n\tSET_TX_DESC_RATE_ID_8812(pDesc, pattrib->raid);\n\n\t/* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */\n\tSET_TX_DESC_QUEUE_SEL_8812(pDesc,  pattrib->qsel);\n\t/* SET_TX_DESC_QUEUE_SEL_8812(pDesc,  QSLT_MGNT); */\n\n\tif (!pattrib->qos_en) {\n\t\tSET_TX_DESC_HWSEQ_EN_8812(pDesc, 1); /* Hw set sequence number */\n\t} else\n\t\tSET_TX_DESC_SEQ_8812(pDesc, pattrib->seqnum);\n\n\tif (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)\n\t\tSET_TX_DESC_DATA_BW_8812(pDesc, pmp_priv->bandwidth);\n\telse {\n\t\tRTW_INFO(\"%s:Err: unknown bandwidth %d, use 20M\\n\", __func__, pmp_priv->bandwidth);\n\t\tSET_TX_DESC_DATA_BW_8812(pDesc, CHANNEL_WIDTH_20);\n\t}\n\n\tSET_TX_DESC_DISABLE_FB_8812(pDesc, 1);\n\tSET_TX_DESC_USE_RATE_8812(pDesc, 1);\n\tSET_TX_DESC_TX_RATE_8812(pDesc, pmp_priv->rateidx);\n\n}\n#endif\n#if defined(CONFIG_RTL8192E)\nvoid fill_tx_desc_8192e(PADAPTER padapter)\n{\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\tu8 *pDesc\t= (u8 *)&(pmp_priv->tx.desc);\n\tstruct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);\n\n\tu32 pkt_size = pattrib->last_txcmdsz;\n\ts32 bmcast = IS_MCAST(pattrib->ra);\n\tu8 data_rate, pwr_status, offset;\n\n\n\tSET_TX_DESC_PKT_SIZE_92E(pDesc, pkt_size);\n\n\toffset = TXDESC_SIZE + OFFSET_SZ;\n\n\tSET_TX_DESC_OFFSET_92E(pDesc, offset);\n#if defined(CONFIG_PCI_HCI) /* 8192EE */\n\n\tSET_TX_DESC_PKT_OFFSET_92E(pDesc, 0); /* 8192EE pkt_offset is 0 */\n#else /* 8192EU 8192ES */\n\tSET_TX_DESC_PKT_OFFSET_92E(pDesc, 1);\n#endif\n\n\tif (bmcast)\n\t\tSET_TX_DESC_BMC_92E(pDesc, 1);\n\n\tSET_TX_DESC_MACID_92E(pDesc, pattrib->mac_id);\n\tSET_TX_DESC_RATE_ID_92E(pDesc, pattrib->raid);\n\n\n\tSET_TX_DESC_QUEUE_SEL_92E(pDesc,  pattrib->qsel);\n\t/* SET_TX_DESC_QUEUE_SEL_8812(pDesc,  QSLT_MGNT); */\n\n\tif (!pattrib->qos_en) {\n\t\tSET_TX_DESC_EN_HWSEQ_92E(pDesc, 1);/* Hw set sequence number */\n\t\tSET_TX_DESC_HWSEQ_SEL_92E(pDesc, pattrib->hw_ssn_sel);\n\t} else\n\t\tSET_TX_DESC_SEQ_92E(pDesc, pattrib->seqnum);\n\n\tif ((pmp_priv->bandwidth == CHANNEL_WIDTH_20) || (pmp_priv->bandwidth == CHANNEL_WIDTH_40))\n\t\tSET_TX_DESC_DATA_BW_92E(pDesc, pmp_priv->bandwidth);\n\telse {\n\t\tRTW_INFO(\"%s:Err: unknown bandwidth %d, use 20M\\n\", __func__, pmp_priv->bandwidth);\n\t\tSET_TX_DESC_DATA_BW_92E(pDesc, CHANNEL_WIDTH_20);\n\t}\n\n\t/* SET_TX_DESC_DATA_SC_92E(pDesc, SCMapping_92E(padapter,pattrib)); */\n\n\tSET_TX_DESC_DISABLE_FB_92E(pDesc, 1);\n\tSET_TX_DESC_USE_RATE_92E(pDesc, 1);\n\tSET_TX_DESC_TX_RATE_92E(pDesc, pmp_priv->rateidx);\n\n}\n#endif\n\n#if defined(CONFIG_RTL8723B)\nvoid fill_tx_desc_8723b(PADAPTER padapter)\n{\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\tstruct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);\n\tu8 *ptxdesc = pmp_priv->tx.desc;\n\n\tSET_TX_DESC_AGG_BREAK_8723B(ptxdesc, 1);\n\tSET_TX_DESC_MACID_8723B(ptxdesc, pattrib->mac_id);\n\tSET_TX_DESC_QUEUE_SEL_8723B(ptxdesc, pattrib->qsel);\n\n\tSET_TX_DESC_RATE_ID_8723B(ptxdesc, pattrib->raid);\n\tSET_TX_DESC_SEQ_8723B(ptxdesc, pattrib->seqnum);\n\tSET_TX_DESC_HWSEQ_EN_8723B(ptxdesc, 1);\n\tSET_TX_DESC_USE_RATE_8723B(ptxdesc, 1);\n\tSET_TX_DESC_DISABLE_FB_8723B(ptxdesc, 1);\n\n\tif (pmp_priv->preamble) {\n\t\tif (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)\n\t\t\tSET_TX_DESC_DATA_SHORT_8723B(ptxdesc, 1);\n\t}\n\n\tif (pmp_priv->bandwidth == CHANNEL_WIDTH_40)\n\t\tSET_TX_DESC_DATA_BW_8723B(ptxdesc, 1);\n\n\tSET_TX_DESC_TX_RATE_8723B(ptxdesc, pmp_priv->rateidx);\n\n\tSET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(ptxdesc, 0x1F);\n\tSET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(ptxdesc, 0xF);\n}\n#endif\n\n#if defined(CONFIG_RTL8703B)\nvoid fill_tx_desc_8703b(PADAPTER padapter)\n{\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\tstruct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);\n\tu8 *ptxdesc = pmp_priv->tx.desc;\n\n\tSET_TX_DESC_AGG_BREAK_8703B(ptxdesc, 1);\n\tSET_TX_DESC_MACID_8703B(ptxdesc, pattrib->mac_id);\n\tSET_TX_DESC_QUEUE_SEL_8703B(ptxdesc, pattrib->qsel);\n\n\tSET_TX_DESC_RATE_ID_8703B(ptxdesc, pattrib->raid);\n\tSET_TX_DESC_SEQ_8703B(ptxdesc, pattrib->seqnum);\n\tSET_TX_DESC_HWSEQ_EN_8703B(ptxdesc, 1);\n\tSET_TX_DESC_USE_RATE_8703B(ptxdesc, 1);\n\tSET_TX_DESC_DISABLE_FB_8703B(ptxdesc, 1);\n\n\tif (pmp_priv->preamble) {\n\t\tif (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)\n\t\t\tSET_TX_DESC_DATA_SHORT_8703B(ptxdesc, 1);\n\t}\n\n\tif (pmp_priv->bandwidth == CHANNEL_WIDTH_40)\n\t\tSET_TX_DESC_DATA_BW_8703B(ptxdesc, 1);\n\n\tSET_TX_DESC_TX_RATE_8703B(ptxdesc, pmp_priv->rateidx);\n\n\tSET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(ptxdesc, 0x1F);\n\tSET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(ptxdesc, 0xF);\n}\n#endif\n\n#if defined(CONFIG_RTL8188F)\nvoid fill_tx_desc_8188f(PADAPTER padapter)\n{\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\tstruct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);\n\tu8 *ptxdesc = pmp_priv->tx.desc;\n\n\tSET_TX_DESC_AGG_BREAK_8188F(ptxdesc, 1);\n\tSET_TX_DESC_MACID_8188F(ptxdesc, pattrib->mac_id);\n\tSET_TX_DESC_QUEUE_SEL_8188F(ptxdesc, pattrib->qsel);\n\n\tSET_TX_DESC_RATE_ID_8188F(ptxdesc, pattrib->raid);\n\tSET_TX_DESC_SEQ_8188F(ptxdesc, pattrib->seqnum);\n\tSET_TX_DESC_HWSEQ_EN_8188F(ptxdesc, 1);\n\tSET_TX_DESC_USE_RATE_8188F(ptxdesc, 1);\n\tSET_TX_DESC_DISABLE_FB_8188F(ptxdesc, 1);\n\n\tif (pmp_priv->preamble)\n\t\tif (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)\n\t\t\tSET_TX_DESC_DATA_SHORT_8188F(ptxdesc, 1);\n\n\tif (pmp_priv->bandwidth == CHANNEL_WIDTH_40)\n\t\tSET_TX_DESC_DATA_BW_8188F(ptxdesc, 1);\n\n\tSET_TX_DESC_TX_RATE_8188F(ptxdesc, pmp_priv->rateidx);\n\n\tSET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(ptxdesc, 0x1F);\n\tSET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(ptxdesc, 0xF);\n}\n#endif\n\n#if defined(CONFIG_RTL8188GTV)\nvoid fill_tx_desc_8188gtv(PADAPTER padapter)\n{\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\tstruct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);\n\tu8 *ptxdesc = pmp_priv->tx.desc;\n\n\tSET_TX_DESC_AGG_BREAK_8188GTV(ptxdesc, 1);\n\tSET_TX_DESC_MACID_8188GTV(ptxdesc, pattrib->mac_id);\n\tSET_TX_DESC_QUEUE_SEL_8188GTV(ptxdesc, pattrib->qsel);\n\n\tSET_TX_DESC_RATE_ID_8188GTV(ptxdesc, pattrib->raid);\n\tSET_TX_DESC_SEQ_8188GTV(ptxdesc, pattrib->seqnum);\n\tSET_TX_DESC_HWSEQ_EN_8188GTV(ptxdesc, 1);\n\tSET_TX_DESC_USE_RATE_8188GTV(ptxdesc, 1);\n\tSET_TX_DESC_DISABLE_FB_8188GTV(ptxdesc, 1);\n\n\tif (pmp_priv->preamble)\n\t\tif (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)\n\t\t\tSET_TX_DESC_DATA_SHORT_8188GTV(ptxdesc, 1);\n\n\tif (pmp_priv->bandwidth == CHANNEL_WIDTH_40)\n\t\tSET_TX_DESC_DATA_BW_8188GTV(ptxdesc, 1);\n\n\tSET_TX_DESC_TX_RATE_8188GTV(ptxdesc, pmp_priv->rateidx);\n\n\tSET_TX_DESC_DATA_RATE_FB_LIMIT_8188GTV(ptxdesc, 0x1F);\n\tSET_TX_DESC_RTS_RATE_FB_LIMIT_8188GTV(ptxdesc, 0xF);\n}\n#endif\n\n#if defined(CONFIG_RTL8723D)\nvoid fill_tx_desc_8723d(PADAPTER padapter)\n{\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\tstruct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);\n\tu8 *ptxdesc = pmp_priv->tx.desc;\n\n\tSET_TX_DESC_BK_8723D(ptxdesc, 1);\n\tSET_TX_DESC_MACID_8723D(ptxdesc, pattrib->mac_id);\n\tSET_TX_DESC_QUEUE_SEL_8723D(ptxdesc, pattrib->qsel);\n\n\tSET_TX_DESC_RATE_ID_8723D(ptxdesc, pattrib->raid);\n\tSET_TX_DESC_SEQ_8723D(ptxdesc, pattrib->seqnum);\n\tSET_TX_DESC_HWSEQ_EN_8723D(ptxdesc, 1);\n\tSET_TX_DESC_USE_RATE_8723D(ptxdesc, 1);\n\tSET_TX_DESC_DISABLE_FB_8723D(ptxdesc, 1);\n\n\tif (pmp_priv->preamble) {\n\t\tif (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)\n\t\t\tSET_TX_DESC_DATA_SHORT_8723D(ptxdesc, 1);\n\t}\n\n\tif (pmp_priv->bandwidth == CHANNEL_WIDTH_40)\n\t\tSET_TX_DESC_DATA_BW_8723D(ptxdesc, 1);\n\n\tSET_TX_DESC_TX_RATE_8723D(ptxdesc, pmp_priv->rateidx);\n\n\tSET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(ptxdesc, 0x1F);\n\tSET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(ptxdesc, 0xF);\n}\n#endif\n\n#if defined(CONFIG_RTL8710B)\nvoid fill_tx_desc_8710b(PADAPTER padapter)\n{\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\tstruct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);\n\tu8 *ptxdesc = pmp_priv->tx.desc;\n\n\tSET_TX_DESC_BK_8710B(ptxdesc, 1);\n\tSET_TX_DESC_MACID_8710B(ptxdesc, pattrib->mac_id);\n\tSET_TX_DESC_QUEUE_SEL_8710B(ptxdesc, pattrib->qsel);\n\n\tSET_TX_DESC_RATE_ID_8710B(ptxdesc, pattrib->raid);\n\tSET_TX_DESC_SEQ_8710B(ptxdesc, pattrib->seqnum);\n\tSET_TX_DESC_HWSEQ_EN_8710B(ptxdesc, 1);\n\tSET_TX_DESC_USE_RATE_8710B(ptxdesc, 1);\n\tSET_TX_DESC_DISABLE_FB_8710B(ptxdesc, 1);\n\n\tif (pmp_priv->preamble) {\n\t\tif (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)\n\t\t\tSET_TX_DESC_DATA_SHORT_8710B(ptxdesc, 1);\n\t}\n\n\tif (pmp_priv->bandwidth == CHANNEL_WIDTH_40)\n\t\tSET_TX_DESC_DATA_BW_8710B(ptxdesc, 1);\n\n\tSET_TX_DESC_TX_RATE_8710B(ptxdesc, pmp_priv->rateidx);\n\n\tSET_TX_DESC_DATA_RATE_FB_LIMIT_8710B(ptxdesc, 0x1F);\n\tSET_TX_DESC_RTS_RATE_FB_LIMIT_8710B(ptxdesc, 0xF);\n}\n#endif\n\n#if defined(CONFIG_RTL8192F)\nvoid fill_tx_desc_8192f(PADAPTER padapter)\n{\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\tstruct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);\n\tu8 *ptxdesc = pmp_priv->tx.desc;\n\n\tSET_TX_DESC_BK_8192F(ptxdesc, 1);\n\tSET_TX_DESC_MACID_8192F(ptxdesc, pattrib->mac_id);\n\tSET_TX_DESC_QUEUE_SEL_8192F(ptxdesc, pattrib->qsel);\n\n\tSET_TX_DESC_RATE_ID_8192F(ptxdesc, pattrib->raid);\n\tSET_TX_DESC_SEQ_8192F(ptxdesc, pattrib->seqnum);\n\tSET_TX_DESC_HWSEQ_EN_8192F(ptxdesc, 1);\n\tSET_TX_DESC_USE_RATE_8192F(ptxdesc, 1);\n\tSET_TX_DESC_DISABLE_FB_8192F(ptxdesc, 1);\n\n\tif (pmp_priv->preamble) {\n\t\tif (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)\n\t\t\tSET_TX_DESC_DATA_SHORT_8192F(ptxdesc, 1);\n\t}\n\n\tif (pmp_priv->bandwidth == CHANNEL_WIDTH_40)\n\t\tSET_TX_DESC_DATA_BW_8192F(ptxdesc, 1);\n\n\tSET_TX_DESC_TX_RATE_8192F(ptxdesc, pmp_priv->rateidx);\n\n\tSET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(ptxdesc, 0x1F);\n\tSET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(ptxdesc, 0xF);\n}\n\n#endif\nstatic void Rtw_MPSetMacTxEDCA(PADAPTER padapter)\n{\n\n\trtw_write32(padapter, 0x508 , 0x00a422); /* Disable EDCA BE Txop for MP pkt tx adjust Packet interval */\n\t/* RTW_INFO(\"%s:write 0x508~~~~~~ 0x%x\\n\", __func__,rtw_read32(padapter, 0x508)); */\n\tphy_set_mac_reg(padapter, 0x458 , bMaskDWord , 0x0);\n\t/*RTW_INFO(\"%s()!!!!! 0x460 = 0x%x\\n\" ,__func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));*/\n\tphy_set_mac_reg(padapter, 0x460 , bMaskLWord , 0x0); /* fast EDCA queue packet interval & time out value*/\n\t/*phy_set_mac_reg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C);*/\n\t/*phy_set_mac_reg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C);*/\n\t/*phy_set_mac_reg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C);*/\n\tRTW_INFO(\"%s()!!!!! 0x460 = 0x%x\\n\" , __func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));\n\n}\n\nvoid SetPacketTx(PADAPTER padapter)\n{\n\tu8 *ptr, *pkt_start, *pkt_end;\n\tu32 pkt_size, i;\n\tstruct rtw_ieee80211_hdr *hdr;\n\tu8 payload;\n\ts32 bmcast;\n\tstruct pkt_attrib *pattrib;\n\tstruct mp_priv *pmp_priv;\n\n\tpmp_priv = &padapter->mppriv;\n\n\tif (pmp_priv->tx.stop)\n\t\treturn;\n\tpmp_priv->tx.sended = 0;\n\tpmp_priv->tx.stop = 0;\n\tpmp_priv->tx_pktcount = 0;\n\n\t/* 3 1. update_attrib() */\n\tpattrib = &pmp_priv->tx.attrib;\n\t_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);\n\t_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);\n\tbmcast = IS_MCAST(pattrib->ra);\n\tif (bmcast)\n\t\tpattrib->psta = rtw_get_bcmc_stainfo(padapter);\n\telse\n\t\tpattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));\n\n\tpattrib->mac_id = pattrib->psta->cmn.mac_id;\n\tpattrib->mbssid = 0;\n\n\tpattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen;\n\n\t/* 3 2. allocate xmit buffer */\n\tpkt_size = pattrib->last_txcmdsz;\n\n\tif (pmp_priv->tx.pallocated_buf)\n\t\trtw_mfree(pmp_priv->tx.pallocated_buf, pmp_priv->tx.buf_size);\n\tpmp_priv->tx.write_size = pkt_size;\n\tpmp_priv->tx.buf_size = pkt_size + XMITBUF_ALIGN_SZ;\n\tpmp_priv->tx.pallocated_buf = rtw_zmalloc(pmp_priv->tx.buf_size);\n\tif (pmp_priv->tx.pallocated_buf == NULL) {\n\t\tRTW_INFO(\"%s: malloc(%d) fail!!\\n\", __func__, pmp_priv->tx.buf_size);\n\t\treturn;\n\t}\n\tpmp_priv->tx.buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pmp_priv->tx.pallocated_buf), XMITBUF_ALIGN_SZ);\n\tptr = pmp_priv->tx.buf;\n\n\t_rtw_memset(pmp_priv->tx.desc, 0, TXDESC_SIZE);\n\tpkt_start = ptr;\n\tpkt_end = pkt_start + pkt_size;\n\n\t/* 3 3. init TX descriptor */\n#if defined(CONFIG_RTL8188E)\n\tif (IS_HARDWARE_TYPE_8188E(padapter))\n\t\tfill_tx_desc_8188e(padapter);\n#endif\n\n#if defined(CONFIG_RTL8814A)\n\tif (IS_HARDWARE_TYPE_8814A(padapter))\n\t\tfill_tx_desc_8814a(padapter);\n#endif /* defined(CONFIG_RTL8814A) */\n\n#if defined(CONFIG_RTL8822B)\n\tif (IS_HARDWARE_TYPE_8822B(padapter))\n\t\trtl8822b_prepare_mp_txdesc(padapter, pmp_priv);\n#endif /* CONFIG_RTL8822B */\n\n#if defined(CONFIG_RTL8822C)\n\tif (IS_HARDWARE_TYPE_8822C(padapter))\n\t\trtl8822c_prepare_mp_txdesc(padapter, pmp_priv);\n#endif /* CONFIG_RTL8822C */\n\n#if defined(CONFIG_RTL8821C)\n\tif (IS_HARDWARE_TYPE_8821C(padapter))\n\t\trtl8821c_prepare_mp_txdesc(padapter, pmp_priv);\n#endif /* CONFIG_RTL8821C */\n\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\n\tif (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter))\n\t\tfill_tx_desc_8812a(padapter);\n#endif\n\n#if defined(CONFIG_RTL8192E)\n\tif (IS_HARDWARE_TYPE_8192E(padapter))\n\t\tfill_tx_desc_8192e(padapter);\n#endif\n#if defined(CONFIG_RTL8723B)\n\tif (IS_HARDWARE_TYPE_8723B(padapter))\n\t\tfill_tx_desc_8723b(padapter);\n#endif\n#if defined(CONFIG_RTL8703B)\n\tif (IS_HARDWARE_TYPE_8703B(padapter))\n\t\tfill_tx_desc_8703b(padapter);\n#endif\n\n#if defined(CONFIG_RTL8188F)\n\tif (IS_HARDWARE_TYPE_8188F(padapter))\n\t\tfill_tx_desc_8188f(padapter);\n#endif\n\n#if defined(CONFIG_RTL8188GTV)\n\tif (IS_HARDWARE_TYPE_8188GTV(padapter))\n\t\tfill_tx_desc_8188gtv(padapter);\n#endif\n\n#if defined(CONFIG_RTL8723D)\n\tif (IS_HARDWARE_TYPE_8723D(padapter))\n\t\tfill_tx_desc_8723d(padapter);\n#endif\n#if defined(CONFIG_RTL8192F)\n\t\tif (IS_HARDWARE_TYPE_8192F(padapter))\n\t\t\tfill_tx_desc_8192f(padapter);\n#endif\n\n#if defined(CONFIG_RTL8710B)\n\tif (IS_HARDWARE_TYPE_8710B(padapter))\n\t\tfill_tx_desc_8710b(padapter);\n#endif\n\n\t/* 3 4. make wlan header, make_wlanhdr() */\n\thdr = (struct rtw_ieee80211_hdr *)pkt_start;\n\tset_frame_sub_type(&hdr->frame_ctl, pattrib->subtype);\n\n\t_rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); /* DA */\n\t_rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); /* SA */\n\t_rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); /* RA, BSSID */\n\n\t/* 3 5. make payload */\n\tptr = pkt_start + pattrib->hdrlen;\n\n\tswitch (pmp_priv->tx.payload) {\n\tcase 0:\n\t\tpayload = 0x00;\n\t\tbreak;\n\tcase 1:\n\t\tpayload = 0x5a;\n\t\tbreak;\n\tcase 2:\n\t\tpayload = 0xa5;\n\t\tbreak;\n\tcase 3:\n\t\tpayload = 0xff;\n\t\tbreak;\n\tdefault:\n\t\tpayload = 0x00;\n\t\tbreak;\n\t}\n\tpmp_priv->TXradomBuffer = rtw_zmalloc(4096);\n\tif (pmp_priv->TXradomBuffer == NULL) {\n\t\tRTW_INFO(\"mp create random buffer fail!\\n\");\n\t\tgoto exit;\n\t}\n\n\n\tfor (i = 0; i < 4096; i++)\n\t\tpmp_priv->TXradomBuffer[i] = rtw_random32() % 0xFF;\n\n\t/* startPlace = (u32)(rtw_random32() % 3450); */\n\tif (pmp_priv->mplink_btx == _TRUE)\n\t\t_rtw_memcpy(ptr, pmp_priv->mplink_buf, pkt_end - ptr);\n\telse\n\t\t_rtw_memcpy(ptr, pmp_priv->TXradomBuffer, pkt_end - ptr);\n\t/* _rtw_memset(ptr, payload, pkt_end - ptr); */\n\trtw_mfree(pmp_priv->TXradomBuffer, 4096);\n\n\t/* 3 6. start thread */\n#ifdef PLATFORM_LINUX\n\tpmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, \"RTW_MP_THREAD\");\n\tif (IS_ERR(pmp_priv->tx.PktTxThread)) {\n\t\tRTW_ERR(\"Create PktTx Thread Fail !!!!!\\n\");\n\t\tpmp_priv->tx.PktTxThread = NULL;\n\t}\n#endif\n#ifdef PLATFORM_FREEBSD\n\t{\n\t\tstruct proc *p;\n\t\tstruct thread *td;\n\t\tpmp_priv->tx.PktTxThread = kproc_kthread_add(mp_xmit_packet_thread, pmp_priv,\n\t\t\t&p, &td, RFHIGHPID, 0, \"MPXmitThread\", \"MPXmitThread\");\n\n\t\tif (pmp_priv->tx.PktTxThread < 0)\n\t\t\tRTW_INFO(\"Create PktTx Thread Fail !!!!!\\n\");\n\t}\n#endif\n\n\tRtw_MPSetMacTxEDCA(padapter);\nexit:\n\treturn;\n}\n\nvoid SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB)\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);\n\tstruct mp_priv *pmppriv = &pAdapter->mppriv;\n\n\n\tif (bStartRx) {\n#ifdef CONFIG_RTL8723B\n\t\tphy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x3); /* Power on adc  (in RX_WAIT_CCA state) */\n\t\twrite_bbreg(pAdapter, 0xa01, BIT0, bDisable);/* improve Rx performance by jerry\t */\n#endif\n\t\tpHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AMF | RCR_HTC_LOC_CTRL;\n\t\tpHalData->ReceiveConfig |= RCR_ACRC32;\n\t\tpHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;\n\n\t\tif (pmppriv->bSetRxBssid == _TRUE) {\n\t\t\tRTW_INFO(\"%s: pmppriv->network_macaddr=\" MAC_FMT \"\\n\", __func__,\n\t\t\t\t MAC_ARG(pmppriv->network_macaddr));\n\t\t\tpHalData->ReceiveConfig = 0;\n\t\t\tpHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN |RCR_APM | RCR_AM | RCR_AB |RCR_AMF;\n\t\t\tpHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF;\n\n#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)\n\t\t\twrite_bbreg(pAdapter, 0x550, BIT3, bEnable);\n#endif\n\t\t\trtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFEF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */\n\t\t\tpmppriv->brx_filter_beacon = _TRUE;\n\n\t\t} else {\n\t\t\tpHalData->ReceiveConfig |= RCR_ADF;\n\t\t\t/* Accept all data frames */\n\t\t\trtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF);\n\t\t}\n\n\t\tif (bAB)\n\t\t\tpHalData->ReceiveConfig |= RCR_AB;\n\t} else {\n#ifdef CONFIG_RTL8723B\n\t\tphy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x00); /* Power off adc  (in RX_WAIT_CCA state)*/\n\t\twrite_bbreg(pAdapter, 0xa01, BIT0, bEnable);/* improve Rx performance by jerry\t */\n#endif\n\t\tpHalData->ReceiveConfig = 0;\n\t\trtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFFF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */\n\t}\n\n\trtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig);\n}\n\nvoid ResetPhyRxPktCount(PADAPTER pAdapter)\n{\n\tu32 i, phyrx_set = 0;\n\n\tfor (i = 0; i <= 0xF; i++) {\n\t\tphyrx_set = 0;\n\t\tphyrx_set |= _RXERR_RPT_SEL(i);\t/* select */\n\t\tphyrx_set |= RXERR_RPT_RST;\t/* set counter to zero */\n\t\trtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);\n\t}\n}\n\nstatic u32 GetPhyRxPktCounts(PADAPTER pAdapter, u32 selbit)\n{\n\t/* selection */\n\tu32 phyrx_set = 0, count = 0;\n\n\tphyrx_set = _RXERR_RPT_SEL(selbit & 0xF);\n\trtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);\n\n\t/* Read packet count */\n\tcount = rtw_read32(pAdapter, REG_RXERR_RPT) & RXERR_COUNTER_MASK;\n\n\treturn count;\n}\n\nu32 GetPhyRxPktReceived(PADAPTER pAdapter)\n{\n\tu32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;\n\n\tOFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_OK);\n\tCCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_OK);\n\tHT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_OK);\n\n\treturn OFDM_cnt + CCK_cnt + HT_cnt;\n}\n\nu32 GetPhyRxPktCRC32Error(PADAPTER pAdapter)\n{\n\tu32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;\n\n\tOFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_FAIL);\n\tCCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_FAIL);\n\tHT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_FAIL);\n\n\treturn OFDM_cnt + CCK_cnt + HT_cnt;\n}\n\nstruct psd_init_regs {\n\t/* 3 wire */\n\tint reg_88c;\n\tint reg_c00;\n\tint reg_e00;\n\tint reg_1800;\n\tint reg_1a00;\n\t/* cck */\n\tint reg_800;\n\tint reg_808;\n};\n\nstatic int rtw_mp_psd_init(PADAPTER padapter, struct psd_init_regs *regs)\n{\n\tHAL_DATA_TYPE\t*phal_data\t= GET_HAL_DATA(padapter);\n\n\tswitch (phal_data->rf_type) {\n\t/* 1R */\n\tcase RF_1T1R:\n\t\tif (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {\n\t\t\t/* 11AC 1R PSD Setting 3wire & cck off */\n\t\t\tregs->reg_c00 = rtw_read32(padapter, 0xC00);\n\t\t\tphy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);\n\t\t\tregs->reg_808 = rtw_read32(padapter, 0x808);\n\t\t\tphy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);\n\t\t} else {\n\t\t\t/* 11N 3-wire off 1 */\n\t\t\tregs->reg_88c = rtw_read32(padapter, 0x88C);\n\t\t\tphy_set_bb_reg(padapter, 0x88C, 0x300000, 0x3);\n\t\t\t/* 11N CCK off */\n\t\t\tregs->reg_800 = rtw_read32(padapter, 0x800);\n\t\t\tphy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0);\n\t\t}\n\tbreak;\n\n\t/* 2R */\n\tcase RF_1T2R:\n\tcase RF_2T2R:\n\t\tif (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {\n\t\t\t/* 11AC 2R PSD Setting 3wire & cck off */\n\t\t\tregs->reg_c00 = rtw_read32(padapter, 0xC00);\n\t\t\tregs->reg_e00 = rtw_read32(padapter, 0xE00);\n\t\t\tphy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);\n\t\t\tphy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);\n\t\t\tregs->reg_808 = rtw_read32(padapter, 0x808);\n\t\t\tphy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);\n\t\t} else {\n\t\t\t/* 11N 3-wire off 2 */\n\t\t\tregs->reg_88c = rtw_read32(padapter, 0x88C);\n\t\t\tphy_set_bb_reg(padapter, 0x88C, 0xF00000, 0xF);\n\t\t\t/* 11N CCK off */\n\t\t\tregs->reg_800 = rtw_read32(padapter, 0x800);\n\t\t\tphy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0);\n\t\t}\n\tbreak;\n\n\t/* 3R */\n\tcase RF_2T3R:\n\tcase RF_3T3R:\n\t\tif (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {\n\t\t\t/* 11AC 3R PSD Setting 3wire & cck off */\n\t\t\tregs->reg_c00 = rtw_read32(padapter, 0xC00);\n\t\t\tregs->reg_e00 = rtw_read32(padapter, 0xE00);\n\t\t\tregs->reg_1800 = rtw_read32(padapter, 0x1800);\n\t\t\tphy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);\n\t\t\tphy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);\n\t\t\tphy_set_bb_reg(padapter, 0x1800, 0x3, 0x00);\n\t\t\tregs->reg_808 = rtw_read32(padapter, 0x808);\n\t\t\tphy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);\n\t\t} else {\n\t\t\tRTW_ERR(\"%s: 11n don't support 3R\\n\", __func__);\n\t\t\treturn -1;\n\t\t}\n\t\tbreak;\n\n\t/* 4R */\n\tcase RF_2T4R:\n\tcase RF_3T4R:\n\tcase RF_4T4R:\n\t\tif (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {\n\t\t\t/* 11AC 4R PSD Setting 3wire & cck off */\n\t\t\tregs->reg_c00 = rtw_read32(padapter, 0xC00);\n\t\t\tregs->reg_e00 = rtw_read32(padapter, 0xE00);\n\t\t\tregs->reg_1800 = rtw_read32(padapter, 0x1800);\n\t\t\tregs->reg_1a00 = rtw_read32(padapter, 0x1A00);\n\t\t\tphy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);\n\t\t\tphy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);\n\t\t\tphy_set_bb_reg(padapter, 0x1800, 0x3, 0x00);\n\t\t\tphy_set_bb_reg(padapter, 0x1A00, 0x3, 0x00);\n\t\t\tregs->reg_808 = rtw_read32(padapter, 0x808);\n\t\t\tphy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);\n\t\t} else {\n\t\t\tRTW_ERR(\"%s: 11n don't support 4R\\n\", __func__);\n\t\t\treturn -1;\n\t\t}\n\t\tbreak;\n\n\tdefault:\n\t\tRTW_ERR(\"%s: unknown %d rf type\\n\", __func__, phal_data->rf_type);\n\t\treturn -1;\n\t}\n\n\t/* Set PSD points, 0=128, 1=256, 2=512, 3=1024 */\n\tif (hal_chk_proto_cap(padapter, PROTO_CAP_11AC))\n\t\tphy_set_bb_reg(padapter, 0x910, 0xC000, 3);\n\telse\n\t\tphy_set_bb_reg(padapter, 0x808, 0xC000, 3);\n\n\tRTW_INFO(\"%s: set %d rf type done\\n\", __func__, phal_data->rf_type);\n\treturn 0;\n}\n\nstatic int rtw_mp_psd_close(PADAPTER padapter, struct psd_init_regs *regs)\n{\n\tHAL_DATA_TYPE\t*phal_data\t= GET_HAL_DATA(padapter);\n\n\n\tif (!hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {\n\t\t/* 11n 3wire restore */\n\t\trtw_write32(padapter, 0x88C, regs->reg_88c);\n\t\t/* 11n cck restore */\n\t\trtw_write32(padapter, 0x800, regs->reg_800);\n\t\tRTW_INFO(\"%s: restore %d rf type\\n\", __func__, phal_data->rf_type);\n\t\treturn 0;\n\t}\n\n\t/* 11ac 3wire restore */\n\tswitch (phal_data->rf_type) {\n\tcase RF_1T1R:\n\t\trtw_write32(padapter, 0xC00, regs->reg_c00);\n\t\tbreak;\n\tcase RF_1T2R:\n\tcase RF_2T2R:\n\t\trtw_write32(padapter, 0xC00, regs->reg_c00);\n\t\trtw_write32(padapter, 0xE00, regs->reg_e00);\n\t\tbreak;\n\tcase RF_2T3R:\n\tcase RF_3T3R:\n\t\trtw_write32(padapter, 0xC00, regs->reg_c00);\n\t\trtw_write32(padapter, 0xE00, regs->reg_e00);\n\t\trtw_write32(padapter, 0x1800, regs->reg_1800);\n\t\tbreak;\n\tcase RF_2T4R:\n\tcase RF_3T4R:\n\tcase RF_4T4R:\n\t\trtw_write32(padapter, 0xC00, regs->reg_c00);\n\t\trtw_write32(padapter, 0xE00, regs->reg_e00);\n\t\trtw_write32(padapter, 0x1800, regs->reg_1800);\n\t\trtw_write32(padapter, 0x1A00, regs->reg_1a00);\n\t\tbreak;\n\tdefault:\n\t\tRTW_WARN(\"%s: unknown %d rf type\\n\", __func__, phal_data->rf_type);\n\t\tbreak;\n\t}\n\n\t/* 11ac cck restore */\n\trtw_write32(padapter, 0x808, regs->reg_808);\n\tRTW_INFO(\"%s: restore %d rf type done\\n\", __func__, phal_data->rf_type);\n\treturn 0;\n}\n\n/* reg 0x808[9:0]: FFT data x\n * reg 0x808[22]:  0  -->  1  to get 1 FFT data y\n * reg 0x8B4[15:0]: FFT data y report */\nstatic u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point)\n{\n\tu32 psd_val = 0;\n\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)\n\tu16 psd_reg = 0x910;\n\tu16 psd_regL = 0xF44;\n#else\n\tu16 psd_reg = 0x808;\n\tu16 psd_regL = 0x8B4;\n#endif\n\n\tpsd_val = rtw_read32(pAdapter, psd_reg);\n\n\tpsd_val &= 0xFFBFFC00;\n\tpsd_val |= point;\n\n\trtw_write32(pAdapter, psd_reg, psd_val);\n\trtw_mdelay_os(1);\n\tpsd_val |= 0x00400000;\n\n\trtw_write32(pAdapter, psd_reg, psd_val);\n\trtw_mdelay_os(1);\n\n\tpsd_val = rtw_read32(pAdapter, psd_regL);\n#if defined(CONFIG_RTL8821C)\n\tpsd_val = (psd_val & 0x00FFFFFF) / 32;\n#else\n\tpsd_val &= 0x0000FFFF;\n#endif\n\n\treturn psd_val;\n}\n\n/*\n * pts\tstart_point_min\t\tstop_point_max\n * 128\t64\t\t\t64 + 128 = 192\n * 256\t128\t\t\t128 + 256 = 384\n * 512\t256\t\t\t256 + 512 = 768\n * 1024\t512\t\t\t512 + 1024 = 1536\n *\n */\nu32 mp_query_psd(PADAPTER pAdapter, u8 *data)\n{\n\tHAL_DATA_TYPE\t*pHalData\t= GET_HAL_DATA(pAdapter);\n\tstruct dm_struct *p_dm = adapter_to_phydm(pAdapter);\n\n\tu32 i, psd_pts = 0, psd_start = 0, psd_stop = 0;\n\tu32 psd_data = 0;\n\tstruct psd_init_regs regs = {};\n\tint psd_analysis = 0;\n\n\n#ifdef PLATFORM_LINUX\n\tif (!netif_running(pAdapter->pnetdev)) {\n\t\treturn 0;\n\t}\n#endif\n\n\tif (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {\n\t\treturn 0;\n\t}\n\n\tif (strlen(data) == 0) { /* default value */\n\t\tpsd_pts = 128;\n\t\tpsd_start = 64;\n\t\tpsd_stop = 128;\n\t} else if (strncmp(data, \"analysis,\", 9) == 0) {\n\t\tif (rtw_mp_psd_init(pAdapter, &regs) != 0)\n\t\t\treturn 0;\n\t\tpsd_analysis = 1;\n\t\tsscanf(data + 9, \"pts=%d,start=%d,stop=%d\", &psd_pts, &psd_start, &psd_stop);\n\t} else\n\t\tsscanf(data, \"pts=%d,start=%d,stop=%d\", &psd_pts, &psd_start, &psd_stop);\n\n\tdata[0] = '\\0';\n\n\tif (IS_HARDWARE_TYPE_8822C(pAdapter)) {\n\t\t\tu32 *psdbuf = rtw_zmalloc(sizeof(u32)*256);\n\n\t\t\tif (psdbuf == NULL) {\n\t\t\t\tRTW_INFO(\"%s: psd buf malloc fail!!\\n\", __func__);\n\t\t\t\treturn 0;\n\t\t\t}\n\n\t\t\thalrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_POINT, psd_pts);\n\t\t\thalrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_START_POINT, psd_start);\n\t\t\thalrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_STOP_POINT, psd_stop);\n\t\t\thalrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_AVERAGE, 0x20000);\n\n\t\t\thalrf_psd_init(p_dm);\n#ifdef CONFIG_LONG_DELAY_ISSUE\n\t\trtw_msleep_os(100);\n#else\n\t\trtw_mdelay_os(100);\n#endif\n\t\t\thalrf_psd_query(p_dm, psdbuf, 256);\n\n\t\t\ti = 0;\n\t\t\twhile (i < 256) {\n\t\t\t\tsprintf(data, \"%s%x \", data, (psdbuf[i]));\n\t\t\t\ti++;\n\t\t\t}\n\n\t\tif (psdbuf)\n\t\t\trtw_mfree(psdbuf, sizeof(u32)*256);\n\n\t} else {\n\ti = psd_start;\n\twhile (i < psd_stop) {\n\t\tif (i >= psd_pts)\n\t\t\tpsd_data = rtw_GetPSDData(pAdapter, i - psd_pts);\n\t\telse\n\t\t\tpsd_data = rtw_GetPSDData(pAdapter, i);\n\n\t\tsprintf(data, \"%s%x \", data, psd_data);\n\t\ti++;\n\t}\n\n\t}\n\n#ifdef CONFIG_LONG_DELAY_ISSUE\n\trtw_msleep_os(100);\n#else\n\trtw_mdelay_os(100);\n#endif\n\n\tif (psd_analysis)\n\t\trtw_mp_psd_close(pAdapter, &regs);\n\n\treturn strlen(data) + 1;\n}\n\n\n#if 0\nvoid _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv)\n{\n\tint i, res;\n\t_adapter *padapter = pxmitpriv->adapter;\n\tstruct xmit_frame\t*pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;\n\tstruct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;\n\n\tu32 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;\n\tu32 num_xmit_extbuf = NR_XMIT_EXTBUFF;\n\tif (padapter->registrypriv.mp_mode == 0) {\n\t\tmax_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;\n\t\tnum_xmit_extbuf = NR_XMIT_EXTBUFF;\n\t} else {\n\t\tmax_xmit_extbuf_size = 6000;\n\t\tnum_xmit_extbuf = 8;\n\t}\n\n\tpxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;\n\tfor (i = 0; i < num_xmit_extbuf; i++) {\n\t\trtw_os_xmit_resource_free(padapter, pxmitbuf, (max_xmit_extbuf_size + XMITBUF_ALIGN_SZ), _FALSE);\n\n\t\tpxmitbuf++;\n\t}\n\n\tif (pxmitpriv->pallocated_xmit_extbuf)\n\t\trtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, num_xmit_extbuf * sizeof(struct xmit_buf) + 4);\n\n\tif (padapter->registrypriv.mp_mode == 0) {\n\t\tmax_xmit_extbuf_size = 6000;\n\t\tnum_xmit_extbuf = 8;\n\t} else {\n\t\tmax_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;\n\t\tnum_xmit_extbuf = NR_XMIT_EXTBUFF;\n\t}\n\n\t/* Init xmit extension buff */\n\t_rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue);\n\n\tpxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(num_xmit_extbuf * sizeof(struct xmit_buf) + 4);\n\n\tif (pxmitpriv->pallocated_xmit_extbuf  == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4);\n\n\tpxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;\n\n\tfor (i = 0; i < num_xmit_extbuf; i++) {\n\t\t_rtw_init_listhead(&pxmitbuf->list);\n\n\t\tpxmitbuf->priv_data = NULL;\n\t\tpxmitbuf->padapter = padapter;\n\t\tpxmitbuf->buf_tag = XMITBUF_MGNT;\n\n\t\tres = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, max_xmit_extbuf_size + XMITBUF_ALIGN_SZ, _TRUE);\n\t\tif (res == _FAIL) {\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t\tpxmitbuf->phead = pxmitbuf->pbuf;\n\t\tpxmitbuf->pend = pxmitbuf->pbuf + max_xmit_extbuf_size;\n\t\tpxmitbuf->len = 0;\n\t\tpxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;\n#endif\n\n\t\trtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue));\n#ifdef DBG_XMIT_BUF_EXT\n\t\tpxmitbuf->no = i;\n#endif\n\t\tpxmitbuf++;\n\n\t}\n\n\tpxmitpriv->free_xmit_extbuf_cnt = num_xmit_extbuf;\n\nexit:\n\t;\n}\n#endif\n\nu8\nmpt_to_mgnt_rate(\n\t\tu32\tMptRateIdx\n)\n{\n\t/* Mapped to MGN_XXX defined in MgntGen.h */\n\tswitch (MptRateIdx) {\n\t/* CCK rate. */\n\tcase\tMPT_RATE_1M:\n\t\treturn MGN_1M;\n\tcase\tMPT_RATE_2M:\n\t\treturn MGN_2M;\n\tcase\tMPT_RATE_55M:\n\t\treturn MGN_5_5M;\n\tcase\tMPT_RATE_11M:\n\t\treturn MGN_11M;\n\n\t/* OFDM rate. */\n\tcase\tMPT_RATE_6M:\n\t\treturn MGN_6M;\n\tcase\tMPT_RATE_9M:\n\t\treturn MGN_9M;\n\tcase\tMPT_RATE_12M:\n\t\treturn MGN_12M;\n\tcase\tMPT_RATE_18M:\n\t\treturn MGN_18M;\n\tcase\tMPT_RATE_24M:\n\t\treturn MGN_24M;\n\tcase\tMPT_RATE_36M:\n\t\treturn MGN_36M;\n\tcase\tMPT_RATE_48M:\n\t\treturn MGN_48M;\n\tcase\tMPT_RATE_54M:\n\t\treturn MGN_54M;\n\n\t/* HT rate. */\n\tcase\tMPT_RATE_MCS0:\n\t\treturn MGN_MCS0;\n\tcase\tMPT_RATE_MCS1:\n\t\treturn MGN_MCS1;\n\tcase\tMPT_RATE_MCS2:\n\t\treturn MGN_MCS2;\n\tcase\tMPT_RATE_MCS3:\n\t\treturn MGN_MCS3;\n\tcase\tMPT_RATE_MCS4:\n\t\treturn MGN_MCS4;\n\tcase\tMPT_RATE_MCS5:\n\t\treturn MGN_MCS5;\n\tcase\tMPT_RATE_MCS6:\n\t\treturn MGN_MCS6;\n\tcase\tMPT_RATE_MCS7:\n\t\treturn MGN_MCS7;\n\tcase\tMPT_RATE_MCS8:\n\t\treturn MGN_MCS8;\n\tcase\tMPT_RATE_MCS9:\n\t\treturn MGN_MCS9;\n\tcase\tMPT_RATE_MCS10:\n\t\treturn MGN_MCS10;\n\tcase\tMPT_RATE_MCS11:\n\t\treturn MGN_MCS11;\n\tcase\tMPT_RATE_MCS12:\n\t\treturn MGN_MCS12;\n\tcase\tMPT_RATE_MCS13:\n\t\treturn MGN_MCS13;\n\tcase\tMPT_RATE_MCS14:\n\t\treturn MGN_MCS14;\n\tcase\tMPT_RATE_MCS15:\n\t\treturn MGN_MCS15;\n\tcase\tMPT_RATE_MCS16:\n\t\treturn MGN_MCS16;\n\tcase\tMPT_RATE_MCS17:\n\t\treturn MGN_MCS17;\n\tcase\tMPT_RATE_MCS18:\n\t\treturn MGN_MCS18;\n\tcase\tMPT_RATE_MCS19:\n\t\treturn MGN_MCS19;\n\tcase\tMPT_RATE_MCS20:\n\t\treturn MGN_MCS20;\n\tcase\tMPT_RATE_MCS21:\n\t\treturn MGN_MCS21;\n\tcase\tMPT_RATE_MCS22:\n\t\treturn MGN_MCS22;\n\tcase\tMPT_RATE_MCS23:\n\t\treturn MGN_MCS23;\n\tcase\tMPT_RATE_MCS24:\n\t\treturn MGN_MCS24;\n\tcase\tMPT_RATE_MCS25:\n\t\treturn MGN_MCS25;\n\tcase\tMPT_RATE_MCS26:\n\t\treturn MGN_MCS26;\n\tcase\tMPT_RATE_MCS27:\n\t\treturn MGN_MCS27;\n\tcase\tMPT_RATE_MCS28:\n\t\treturn MGN_MCS28;\n\tcase\tMPT_RATE_MCS29:\n\t\treturn MGN_MCS29;\n\tcase\tMPT_RATE_MCS30:\n\t\treturn MGN_MCS30;\n\tcase\tMPT_RATE_MCS31:\n\t\treturn MGN_MCS31;\n\n\t/* VHT rate. */\n\tcase\tMPT_RATE_VHT1SS_MCS0:\n\t\treturn MGN_VHT1SS_MCS0;\n\tcase\tMPT_RATE_VHT1SS_MCS1:\n\t\treturn MGN_VHT1SS_MCS1;\n\tcase\tMPT_RATE_VHT1SS_MCS2:\n\t\treturn MGN_VHT1SS_MCS2;\n\tcase\tMPT_RATE_VHT1SS_MCS3:\n\t\treturn MGN_VHT1SS_MCS3;\n\tcase\tMPT_RATE_VHT1SS_MCS4:\n\t\treturn MGN_VHT1SS_MCS4;\n\tcase\tMPT_RATE_VHT1SS_MCS5:\n\t\treturn MGN_VHT1SS_MCS5;\n\tcase\tMPT_RATE_VHT1SS_MCS6:\n\t\treturn MGN_VHT1SS_MCS6;\n\tcase\tMPT_RATE_VHT1SS_MCS7:\n\t\treturn MGN_VHT1SS_MCS7;\n\tcase\tMPT_RATE_VHT1SS_MCS8:\n\t\treturn MGN_VHT1SS_MCS8;\n\tcase\tMPT_RATE_VHT1SS_MCS9:\n\t\treturn MGN_VHT1SS_MCS9;\n\tcase\tMPT_RATE_VHT2SS_MCS0:\n\t\treturn MGN_VHT2SS_MCS0;\n\tcase\tMPT_RATE_VHT2SS_MCS1:\n\t\treturn MGN_VHT2SS_MCS1;\n\tcase\tMPT_RATE_VHT2SS_MCS2:\n\t\treturn MGN_VHT2SS_MCS2;\n\tcase\tMPT_RATE_VHT2SS_MCS3:\n\t\treturn MGN_VHT2SS_MCS3;\n\tcase\tMPT_RATE_VHT2SS_MCS4:\n\t\treturn MGN_VHT2SS_MCS4;\n\tcase\tMPT_RATE_VHT2SS_MCS5:\n\t\treturn MGN_VHT2SS_MCS5;\n\tcase\tMPT_RATE_VHT2SS_MCS6:\n\t\treturn MGN_VHT2SS_MCS6;\n\tcase\tMPT_RATE_VHT2SS_MCS7:\n\t\treturn MGN_VHT2SS_MCS7;\n\tcase\tMPT_RATE_VHT2SS_MCS8:\n\t\treturn MGN_VHT2SS_MCS8;\n\tcase\tMPT_RATE_VHT2SS_MCS9:\n\t\treturn MGN_VHT2SS_MCS9;\n\tcase\tMPT_RATE_VHT3SS_MCS0:\n\t\treturn MGN_VHT3SS_MCS0;\n\tcase\tMPT_RATE_VHT3SS_MCS1:\n\t\treturn MGN_VHT3SS_MCS1;\n\tcase\tMPT_RATE_VHT3SS_MCS2:\n\t\treturn MGN_VHT3SS_MCS2;\n\tcase\tMPT_RATE_VHT3SS_MCS3:\n\t\treturn MGN_VHT3SS_MCS3;\n\tcase\tMPT_RATE_VHT3SS_MCS4:\n\t\treturn MGN_VHT3SS_MCS4;\n\tcase\tMPT_RATE_VHT3SS_MCS5:\n\t\treturn MGN_VHT3SS_MCS5;\n\tcase\tMPT_RATE_VHT3SS_MCS6:\n\t\treturn MGN_VHT3SS_MCS6;\n\tcase\tMPT_RATE_VHT3SS_MCS7:\n\t\treturn MGN_VHT3SS_MCS7;\n\tcase\tMPT_RATE_VHT3SS_MCS8:\n\t\treturn MGN_VHT3SS_MCS8;\n\tcase\tMPT_RATE_VHT3SS_MCS9:\n\t\treturn MGN_VHT3SS_MCS9;\n\tcase\tMPT_RATE_VHT4SS_MCS0:\n\t\treturn MGN_VHT4SS_MCS0;\n\tcase\tMPT_RATE_VHT4SS_MCS1:\n\t\treturn MGN_VHT4SS_MCS1;\n\tcase\tMPT_RATE_VHT4SS_MCS2:\n\t\treturn MGN_VHT4SS_MCS2;\n\tcase\tMPT_RATE_VHT4SS_MCS3:\n\t\treturn MGN_VHT4SS_MCS3;\n\tcase\tMPT_RATE_VHT4SS_MCS4:\n\t\treturn MGN_VHT4SS_MCS4;\n\tcase\tMPT_RATE_VHT4SS_MCS5:\n\t\treturn MGN_VHT4SS_MCS5;\n\tcase\tMPT_RATE_VHT4SS_MCS6:\n\t\treturn MGN_VHT4SS_MCS6;\n\tcase\tMPT_RATE_VHT4SS_MCS7:\n\t\treturn MGN_VHT4SS_MCS7;\n\tcase\tMPT_RATE_VHT4SS_MCS8:\n\t\treturn MGN_VHT4SS_MCS8;\n\tcase\tMPT_RATE_VHT4SS_MCS9:\n\t\treturn MGN_VHT4SS_MCS9;\n\n\tcase\tMPT_RATE_LAST:\t/* fully automatiMGN_VHT2SS_MCS1;\t */\n\tdefault:\n\t\tRTW_INFO(\"<===mpt_to_mgnt_rate(), Invalid Rate: %d!!\\n\", MptRateIdx);\n\t\treturn 0x0;\n\t}\n}\n\n\nu8 HwRateToMPTRate(u8 rate)\n{\n\tu8\tret_rate = MGN_1M;\n\n\tswitch (rate) {\n\tcase DESC_RATE1M:\n\t\tret_rate = MPT_RATE_1M;\n\t\tbreak;\n\tcase DESC_RATE2M:\n\t\tret_rate = MPT_RATE_2M;\n\t\tbreak;\n\tcase DESC_RATE5_5M:\n\t\tret_rate = MPT_RATE_55M;\n\t\tbreak;\n\tcase DESC_RATE11M:\n\t\tret_rate = MPT_RATE_11M;\n\t\tbreak;\n\tcase DESC_RATE6M:\n\t\tret_rate = MPT_RATE_6M;\n\t\tbreak;\n\tcase DESC_RATE9M:\n\t\tret_rate = MPT_RATE_9M;\n\t\tbreak;\n\tcase DESC_RATE12M:\n\t\tret_rate = MPT_RATE_12M;\n\t\tbreak;\n\tcase DESC_RATE18M:\n\t\tret_rate = MPT_RATE_18M;\n\t\tbreak;\n\tcase DESC_RATE24M:\n\t\tret_rate = MPT_RATE_24M;\n\t\tbreak;\n\tcase DESC_RATE36M:\n\t\tret_rate = MPT_RATE_36M;\n\t\tbreak;\n\tcase DESC_RATE48M:\n\t\tret_rate = MPT_RATE_48M;\n\t\tbreak;\n\tcase DESC_RATE54M:\n\t\tret_rate = MPT_RATE_54M;\n\t\tbreak;\n\tcase DESC_RATEMCS0:\n\t\tret_rate = MPT_RATE_MCS0;\n\t\tbreak;\n\tcase DESC_RATEMCS1:\n\t\tret_rate = MPT_RATE_MCS1;\n\t\tbreak;\n\tcase DESC_RATEMCS2:\n\t\tret_rate = MPT_RATE_MCS2;\n\t\tbreak;\n\tcase DESC_RATEMCS3:\n\t\tret_rate = MPT_RATE_MCS3;\n\t\tbreak;\n\tcase DESC_RATEMCS4:\n\t\tret_rate = MPT_RATE_MCS4;\n\t\tbreak;\n\tcase DESC_RATEMCS5:\n\t\tret_rate = MPT_RATE_MCS5;\n\t\tbreak;\n\tcase DESC_RATEMCS6:\n\t\tret_rate = MPT_RATE_MCS6;\n\t\tbreak;\n\tcase DESC_RATEMCS7:\n\t\tret_rate = MPT_RATE_MCS7;\n\t\tbreak;\n\tcase DESC_RATEMCS8:\n\t\tret_rate = MPT_RATE_MCS8;\n\t\tbreak;\n\tcase DESC_RATEMCS9:\n\t\tret_rate = MPT_RATE_MCS9;\n\t\tbreak;\n\tcase DESC_RATEMCS10:\n\t\tret_rate = MPT_RATE_MCS10;\n\t\tbreak;\n\tcase DESC_RATEMCS11:\n\t\tret_rate = MPT_RATE_MCS11;\n\t\tbreak;\n\tcase DESC_RATEMCS12:\n\t\tret_rate = MPT_RATE_MCS12;\n\t\tbreak;\n\tcase DESC_RATEMCS13:\n\t\tret_rate = MPT_RATE_MCS13;\n\t\tbreak;\n\tcase DESC_RATEMCS14:\n\t\tret_rate = MPT_RATE_MCS14;\n\t\tbreak;\n\tcase DESC_RATEMCS15:\n\t\tret_rate = MPT_RATE_MCS15;\n\t\tbreak;\n\tcase DESC_RATEMCS16:\n\t\tret_rate = MPT_RATE_MCS16;\n\t\tbreak;\n\tcase DESC_RATEMCS17:\n\t\tret_rate = MPT_RATE_MCS17;\n\t\tbreak;\n\tcase DESC_RATEMCS18:\n\t\tret_rate = MPT_RATE_MCS18;\n\t\tbreak;\n\tcase DESC_RATEMCS19:\n\t\tret_rate = MPT_RATE_MCS19;\n\t\tbreak;\n\tcase DESC_RATEMCS20:\n\t\tret_rate = MPT_RATE_MCS20;\n\t\tbreak;\n\tcase DESC_RATEMCS21:\n\t\tret_rate = MPT_RATE_MCS21;\n\t\tbreak;\n\tcase DESC_RATEMCS22:\n\t\tret_rate = MPT_RATE_MCS22;\n\t\tbreak;\n\tcase DESC_RATEMCS23:\n\t\tret_rate = MPT_RATE_MCS23;\n\t\tbreak;\n\tcase DESC_RATEMCS24:\n\t\tret_rate = MPT_RATE_MCS24;\n\t\tbreak;\n\tcase DESC_RATEMCS25:\n\t\tret_rate = MPT_RATE_MCS25;\n\t\tbreak;\n\tcase DESC_RATEMCS26:\n\t\tret_rate = MPT_RATE_MCS26;\n\t\tbreak;\n\tcase DESC_RATEMCS27:\n\t\tret_rate = MPT_RATE_MCS27;\n\t\tbreak;\n\tcase DESC_RATEMCS28:\n\t\tret_rate = MPT_RATE_MCS28;\n\t\tbreak;\n\tcase DESC_RATEMCS29:\n\t\tret_rate = MPT_RATE_MCS29;\n\t\tbreak;\n\tcase DESC_RATEMCS30:\n\t\tret_rate = MPT_RATE_MCS30;\n\t\tbreak;\n\tcase DESC_RATEMCS31:\n\t\tret_rate = MPT_RATE_MCS31;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS0:\n\t\tret_rate = MPT_RATE_VHT1SS_MCS0;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS1:\n\t\tret_rate = MPT_RATE_VHT1SS_MCS1;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS2:\n\t\tret_rate = MPT_RATE_VHT1SS_MCS2;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS3:\n\t\tret_rate = MPT_RATE_VHT1SS_MCS3;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS4:\n\t\tret_rate = MPT_RATE_VHT1SS_MCS4;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS5:\n\t\tret_rate = MPT_RATE_VHT1SS_MCS5;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS6:\n\t\tret_rate = MPT_RATE_VHT1SS_MCS6;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS7:\n\t\tret_rate = MPT_RATE_VHT1SS_MCS7;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS8:\n\t\tret_rate = MPT_RATE_VHT1SS_MCS8;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS9:\n\t\tret_rate = MPT_RATE_VHT1SS_MCS9;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS0:\n\t\tret_rate = MPT_RATE_VHT2SS_MCS0;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS1:\n\t\tret_rate = MPT_RATE_VHT2SS_MCS1;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS2:\n\t\tret_rate = MPT_RATE_VHT2SS_MCS2;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS3:\n\t\tret_rate = MPT_RATE_VHT2SS_MCS3;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS4:\n\t\tret_rate = MPT_RATE_VHT2SS_MCS4;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS5:\n\t\tret_rate = MPT_RATE_VHT2SS_MCS5;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS6:\n\t\tret_rate = MPT_RATE_VHT2SS_MCS6;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS7:\n\t\tret_rate = MPT_RATE_VHT2SS_MCS7;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS8:\n\t\tret_rate = MPT_RATE_VHT2SS_MCS8;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS9:\n\t\tret_rate = MPT_RATE_VHT2SS_MCS9;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS0:\n\t\tret_rate = MPT_RATE_VHT3SS_MCS0;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS1:\n\t\tret_rate = MPT_RATE_VHT3SS_MCS1;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS2:\n\t\tret_rate = MPT_RATE_VHT3SS_MCS2;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS3:\n\t\tret_rate = MPT_RATE_VHT3SS_MCS3;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS4:\n\t\tret_rate = MPT_RATE_VHT3SS_MCS4;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS5:\n\t\tret_rate = MPT_RATE_VHT3SS_MCS5;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS6:\n\t\tret_rate = MPT_RATE_VHT3SS_MCS6;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS7:\n\t\tret_rate = MPT_RATE_VHT3SS_MCS7;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS8:\n\t\tret_rate = MPT_RATE_VHT3SS_MCS8;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS9:\n\t\tret_rate = MPT_RATE_VHT3SS_MCS9;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS0:\n\t\tret_rate = MPT_RATE_VHT4SS_MCS0;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS1:\n\t\tret_rate = MPT_RATE_VHT4SS_MCS1;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS2:\n\t\tret_rate = MPT_RATE_VHT4SS_MCS2;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS3:\n\t\tret_rate = MPT_RATE_VHT4SS_MCS3;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS4:\n\t\tret_rate = MPT_RATE_VHT4SS_MCS4;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS5:\n\t\tret_rate = MPT_RATE_VHT4SS_MCS5;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS6:\n\t\tret_rate = MPT_RATE_VHT4SS_MCS6;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS7:\n\t\tret_rate = MPT_RATE_VHT4SS_MCS7;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS8:\n\t\tret_rate = MPT_RATE_VHT4SS_MCS8;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS9:\n\t\tret_rate = MPT_RATE_VHT4SS_MCS9;\n\t\tbreak;\n\n\tdefault:\n\t\tRTW_INFO(\"hw_rate_to_m_rate(): Non supported Rate [%x]!!!\\n\", rate);\n\t\tbreak;\n\t}\n\treturn ret_rate;\n}\n\nu8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr)\n{\n\tu16 i = 0;\n\tu8 *rateindex_Array[] = { \"1M\", \"2M\", \"5.5M\", \"11M\", \"6M\", \"9M\", \"12M\", \"18M\", \"24M\", \"36M\", \"48M\", \"54M\",\n\t\t\"HTMCS0\", \"HTMCS1\", \"HTMCS2\", \"HTMCS3\", \"HTMCS4\", \"HTMCS5\", \"HTMCS6\", \"HTMCS7\",\n\t\t\"HTMCS8\", \"HTMCS9\", \"HTMCS10\", \"HTMCS11\", \"HTMCS12\", \"HTMCS13\", \"HTMCS14\", \"HTMCS15\",\n\t\t\"HTMCS16\", \"HTMCS17\", \"HTMCS18\", \"HTMCS19\", \"HTMCS20\", \"HTMCS21\", \"HTMCS22\", \"HTMCS23\",\n\t\t\"HTMCS24\", \"HTMCS25\", \"HTMCS26\", \"HTMCS27\", \"HTMCS28\", \"HTMCS29\", \"HTMCS30\", \"HTMCS31\",\n\t\t\"VHT1MCS0\", \"VHT1MCS1\", \"VHT1MCS2\", \"VHT1MCS3\", \"VHT1MCS4\", \"VHT1MCS5\", \"VHT1MCS6\", \"VHT1MCS7\", \"VHT1MCS8\", \"VHT1MCS9\",\n\t\t\"VHT2MCS0\", \"VHT2MCS1\", \"VHT2MCS2\", \"VHT2MCS3\", \"VHT2MCS4\", \"VHT2MCS5\", \"VHT2MCS6\", \"VHT2MCS7\", \"VHT2MCS8\", \"VHT2MCS9\",\n\t\t\"VHT3MCS0\", \"VHT3MCS1\", \"VHT3MCS2\", \"VHT3MCS3\", \"VHT3MCS4\", \"VHT3MCS5\", \"VHT3MCS6\", \"VHT3MCS7\", \"VHT3MCS8\", \"VHT3MCS9\",\n\t\t\"VHT4MCS0\", \"VHT4MCS1\", \"VHT4MCS2\", \"VHT4MCS3\", \"VHT4MCS4\", \"VHT4MCS5\", \"VHT4MCS6\", \"VHT4MCS7\", \"VHT4MCS8\", \"VHT4MCS9\"\n\t\t\t\t};\n\n\tfor (i = 0; i <= 83; i++) {\n\t\tif (strcmp(targetStr, rateindex_Array[i]) == 0) {\n\t\t\tRTW_INFO(\"%s , index = %d\\n\", __func__ , i);\n\t\t\treturn i;\n\t\t}\n\t}\n\n\tprintk(\"%s ,please input a Data RATE String as:\", __func__);\n\tfor (i = 0; i <= 83; i++) {\n\t\tprintk(\"%s \", rateindex_Array[i]);\n\t\tif (i % 10 == 0)\n\t\t\tprintk(\"\\n\");\n\t}\n\treturn _FAIL;\n}\n\nu8 rtw_mp_mode_check(PADAPTER pAdapter)\n{\n\tPADAPTER primary_adapter = GET_PRIMARY_ADAPTER(pAdapter);\n\n\tif (primary_adapter->registrypriv.mp_mode == 1 || primary_adapter->mppriv.bprocess_mp_mode == _TRUE)\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\n\n\nu32 mpt_ProQueryCalTxPower(\n\tPADAPTER\tpAdapter,\n\tu8\t\tRfPath\n)\n{\n\n\tHAL_DATA_TYPE\t*pHalData\t= GET_HAL_DATA(pAdapter);\n\tPMPT_CONTEXT\t\tpMptCtx = &(pAdapter->mppriv.mpt_ctx);\n\n\tu32\t\t\tTxPower = 1;\n\tstruct txpwr_idx_comp tic;\n\tu8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);\n\n\tTxPower = rtw_hal_get_tx_power_index(pAdapter, RfPath, mgn_rate, pHalData->current_channel_bw, pHalData->current_channel, &tic);\n\n\tRTW_INFO(\"TXPWR: [%c][%s]ch:%u, %s %uT, pwr_idx:%u(0x%02x) = %u + (%d=%d:%d) + (%d) + (%d) + (%d) + (%d)\\n\"\n\t\t, rf_path_char(RfPath), ch_width_str(pHalData->current_channel_bw), pHalData->current_channel, MGN_RATE_STR(mgn_rate), tic.ntx_idx + 1\n\t\t, TxPower, TxPower, tic.pg, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt\n\t\t, tic.ebias, tic.btc, tic.dpd);\n\n\tpAdapter->mppriv.txpoweridx = (u8)TxPower;\n\tif (RfPath == RF_PATH_A)\n\t\tpMptCtx->TxPwrLevel[RF_PATH_A] = (u8)TxPower;\n\telse if (RfPath == RF_PATH_B)\n\t\tpMptCtx->TxPwrLevel[RF_PATH_B] = (u8)TxPower;\n\telse if (RfPath == RF_PATH_C)\n\t\tpMptCtx->TxPwrLevel[RF_PATH_C] = (u8)TxPower;\n\telse if (RfPath == RF_PATH_D)\n\t\tpMptCtx->TxPwrLevel[RF_PATH_D] = (u8)TxPower;\n\thal_mpt_SetTxPower(pAdapter);\n\n\treturn TxPower;\n}\n\n#ifdef CONFIG_MP_VHT_HW_TX_MODE\nstatic inline void dump_buf(u8 *buf, u32 len)\n{\n\tu32 i;\n\n\tRTW_INFO(\"-----------------Len %d----------------\\n\", len);\n\tfor (i = 0; i < len; i++)\n\t\tRTW_INFO(\"%2.2x-\", *(buf + i));\n\tRTW_INFO(\"\\n\");\n}\n\nvoid ByteToBit(\n\tu8\t*out,\n\tbool\t*in,\n\tu8\tin_size)\n{\n\tu8 i = 0, j = 0;\n\n\tfor (i = 0; i < in_size; i++) {\n\t\tfor (j = 0; j < 8; j++) {\n\t\t\tif (in[8 * i + j])\n\t\t\t\tout[i] |= (1 << j);\n\t\t}\n\t}\n}\n\n\nvoid CRC16_generator(\n\tbool *out,\n\tbool *in,\n\tu8 in_size\n)\n{\n\tu8 i = 0;\n\tbool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};\n\n\tfor (i = 0; i < in_size; i++) {/* take one's complement and bit reverse*/\n\t\ttemp = in[i] ^ reg[15];\n\t\treg[15]\t= reg[14];\n\t\treg[14]\t= reg[13];\n\t\treg[13]\t= reg[12];\n\t\treg[12]\t= reg[11];\n\t\treg[11]\t= reg[10];\n\t\treg[10]\t= reg[9];\n\t\treg[9]\t= reg[8];\n\t\treg[8]\t= reg[7];\n\n\t\treg[7]\t= reg[6];\n\t\treg[6]\t= reg[5];\n\t\treg[5]\t= reg[4];\n\t\treg[4]\t= reg[3];\n\t\treg[3]\t= reg[2];\n\t\treg[2]\t= reg[1];\n\t\treg[1]\t= reg[0];\n\t\treg[12]\t= reg[12] ^ temp;\n\t\treg[5]\t= reg[5] ^ temp;\n\t\treg[0]\t= temp;\n\t}\n\tfor (i = 0; i < 16; i++)\t/* take one's complement and bit reverse*/\n\t\tout[i] = 1 - reg[15 - i];\n}\n\n\n\n/*========================================\n\tSFD\t\tSIGNAL\tSERVICE\tLENGTH\tCRC\n\t16 bit\t8 bit\t8 bit\t16 bit\t16 bit\n========================================*/\nvoid CCK_generator(\n\tPRT_PMAC_TX_INFO\tpPMacTxInfo,\n\tPRT_PMAC_PKT_INFO\tpPMacPktInfo\n)\n{\n\tdouble\tratio = 0;\n\tbool\tcrc16_in[32] = {0}, crc16_out[16] = {0};\n\tbool LengthExtBit;\n\tdouble LengthExact;\n\tdouble LengthPSDU;\n\tu8 i;\n\tu32 PacketLength = pPMacTxInfo->PacketLength;\n\n\tif (pPMacTxInfo->bSPreamble)\n\t\tpPMacTxInfo->SFD = 0x05CF;\n\telse\n\t\tpPMacTxInfo->SFD = 0xF3A0;\n\n\tswitch (pPMacPktInfo->MCS) {\n\tcase 0:\n\t\tpPMacTxInfo->SignalField = 0xA;\n\t\tratio = 8;\n\t\t/*CRC16_in(1,0:7)=[0 1 0 1 0 0 0 0]*/\n\t\tcrc16_in[1] = crc16_in[3] = 1;\n\t\tbreak;\n\tcase 1:\n\t\tpPMacTxInfo->SignalField = 0x14;\n\t\tratio = 4;\n\t\t/*CRC16_in(1,0:7)=[0 0 1 0 1 0 0 0];*/\n\t\tcrc16_in[2] = crc16_in[4] = 1;\n\t\tbreak;\n\tcase 2:\n\t\tpPMacTxInfo->SignalField = 0x37;\n\t\tratio = 8.0 / 5.5;\n\t\t/*CRC16_in(1,0:7)=[1 1 1 0 1 1 0 0];*/\n\t\tcrc16_in[0] = crc16_in[1] = crc16_in[2] = crc16_in[4] = crc16_in[5] = 1;\n\t\tbreak;\n\tcase 3:\n\t\tpPMacTxInfo->SignalField = 0x6E;\n\t\tratio = 8.0 / 11.0;\n\t\t/*CRC16_in(1,0:7)=[0 1 1 1 0 1 1 0];*/\n\t\tcrc16_in[1] = crc16_in[2] = crc16_in[3] = crc16_in[5] = crc16_in[6] = 1;\n\t\tbreak;\n\t}\n\n\tLengthExact = PacketLength * ratio;\n\tLengthPSDU = ceil(LengthExact);\n\n\tif ((pPMacPktInfo->MCS == 3) &&\n\t    ((LengthPSDU - LengthExact) >= 0.727 || (LengthPSDU - LengthExact) <= -0.727))\n\t\tLengthExtBit = 1;\n\telse\n\t\tLengthExtBit = 0;\n\n\n\tpPMacTxInfo->LENGTH = (u32)LengthPSDU;\n\t/* CRC16_in(1,16:31) = LengthPSDU[0:15]*/\n\tfor (i = 0; i < 16; i++)\n\t\tcrc16_in[i + 16] = (pPMacTxInfo->LENGTH >> i) & 0x1;\n\n\tif (LengthExtBit == 0) {\n\t\tpPMacTxInfo->ServiceField = 0x0;\n\t\t/* CRC16_in(1,8:15) = [0 0 0 0 0 0 0 0];*/\n\t} else {\n\t\tpPMacTxInfo->ServiceField = 0x80;\n\t\t/*CRC16_in(1,8:15)=[0 0 0 0 0 0 0 1];*/\n\t\tcrc16_in[15] = 1;\n\t}\n\n\tCRC16_generator(crc16_out, crc16_in, 32);\n\n\t_rtw_memset(pPMacTxInfo->CRC16, 0, 2);\n\tByteToBit(pPMacTxInfo->CRC16, crc16_out, 2);\n\n}\n\n\nvoid PMAC_Get_Pkt_Param(\n\tPRT_PMAC_TX_INFO\tpPMacTxInfo,\n\tPRT_PMAC_PKT_INFO\tpPMacPktInfo)\n{\n\n\tu8\t\tTX_RATE_HEX = 0, MCS = 0;\n\tu8\t\tTX_RATE = pPMacTxInfo->TX_RATE;\n\n\t/*\tTX_RATE & Nss\t*/\n\tif (MPT_IS_2SS_RATE(TX_RATE))\n\t\tpPMacPktInfo->Nss = 2;\n\telse if (MPT_IS_3SS_RATE(TX_RATE))\n\t\tpPMacPktInfo->Nss = 3;\n\telse if (MPT_IS_4SS_RATE(TX_RATE))\n\t\tpPMacPktInfo->Nss = 4;\n\telse\n\t\tpPMacPktInfo->Nss = 1;\n\n\tRTW_INFO(\"PMacTxInfo.Nss =%d\\n\", pPMacPktInfo->Nss);\n\n\t/*\tMCS & TX_RATE_HEX*/\n\tif (MPT_IS_CCK_RATE(TX_RATE)) {\n\t\tswitch (TX_RATE) {\n\t\tcase MPT_RATE_1M:\n\t\t\tTX_RATE_HEX = MCS = 0;\n\t\t\tbreak;\n\t\tcase MPT_RATE_2M:\n\t\t\tTX_RATE_HEX = MCS = 1;\n\t\t\tbreak;\n\t\tcase MPT_RATE_55M:\n\t\t\tTX_RATE_HEX = MCS = 2;\n\t\t\tbreak;\n\t\tcase MPT_RATE_11M:\n\t\t\tTX_RATE_HEX = MCS = 3;\n\t\t\tbreak;\n\t\t}\n\t} else if (MPT_IS_OFDM_RATE(TX_RATE)) {\n\t\tMCS = TX_RATE - MPT_RATE_6M;\n\t\tTX_RATE_HEX = MCS + 4;\n\t} else if (MPT_IS_HT_RATE(TX_RATE)) {\n\t\tMCS = TX_RATE - MPT_RATE_MCS0;\n\t\tTX_RATE_HEX = MCS + 12;\n\t} else if (MPT_IS_VHT_RATE(TX_RATE)) {\n\t\tTX_RATE_HEX = TX_RATE - MPT_RATE_VHT1SS_MCS0 + 44;\n\n\t\tif (MPT_IS_VHT_2S_RATE(TX_RATE))\n\t\t\tMCS = TX_RATE - MPT_RATE_VHT2SS_MCS0;\n\t\telse if (MPT_IS_VHT_3S_RATE(TX_RATE))\n\t\t\tMCS = TX_RATE - MPT_RATE_VHT3SS_MCS0;\n\t\telse if (MPT_IS_VHT_4S_RATE(TX_RATE))\n\t\t\tMCS = TX_RATE - MPT_RATE_VHT4SS_MCS0;\n\t\telse\n\t\t\tMCS = TX_RATE - MPT_RATE_VHT1SS_MCS0;\n\t}\n\n\tpPMacPktInfo->MCS = MCS;\n\tpPMacTxInfo->TX_RATE_HEX = TX_RATE_HEX;\n\n\tRTW_INFO(\" MCS=%d, TX_RATE_HEX =0x%x\\n\", MCS, pPMacTxInfo->TX_RATE_HEX);\n\t/*\tmSTBC & Nsts*/\n\tpPMacPktInfo->Nsts = pPMacPktInfo->Nss;\n\tif (pPMacTxInfo->bSTBC) {\n\t\tif (pPMacPktInfo->Nss == 1) {\n\t\t\tpPMacTxInfo->m_STBC = 2;\n\t\t\tpPMacPktInfo->Nsts = pPMacPktInfo->Nss * 2;\n\t\t} else\n\t\t\tpPMacTxInfo->m_STBC = 1;\n\t} else\n\t\tpPMacTxInfo->m_STBC = 1;\n}\n\n\nu32 LDPC_parameter_generator(\n\tu32 N_pld_int,\n\tu32 N_CBPSS,\n\tu32 N_SS,\n\tu32 R,\n\tu32 m_STBC,\n\tu32 N_TCB_int\n)\n{\n\tdouble\tCR = 0.;\n\tdouble\tN_pld = (double)N_pld_int;\n\tdouble\tN_TCB = (double)N_TCB_int;\n\tdouble\tN_CW = 0., N_shrt = 0., N_spcw = 0., N_fshrt = 0.;\n\tdouble\tL_LDPC = 0., K_LDPC = 0., L_LDPC_info = 0.;\n\tdouble\tN_punc = 0., N_ppcw = 0., N_fpunc = 0., N_rep = 0., N_rpcw = 0., N_frep = 0.;\n\tdouble\tR_eff = 0.;\n\tu32\tVHTSIGA2B3  = 0;/* extra symbol from VHT-SIG-A2 Bit 3*/\n\n\tif (R == 0)\n\t\tCR\t= 0.5;\n\telse if (R == 1)\n\t\tCR = 2. / 3.;\n\telse if (R == 2)\n\t\tCR = 3. / 4.;\n\telse if (R == 3)\n\t\tCR = 5. / 6.;\n\n\tif (N_TCB <= 648.) {\n\t\tN_CW\t= 1.;\n\t\tif (N_TCB >= N_pld + 912.*(1. - CR))\n\t\t\tL_LDPC\t= 1296.;\n\t\telse\n\t\t\tL_LDPC\t= 648.;\n\t} else if (N_TCB <= 1296.) {\n\t\tN_CW\t= 1.;\n\t\tif (N_TCB >= (double)N_pld + 1464.*(1. - CR))\n\t\t\tL_LDPC\t= 1944.;\n\t\telse\n\t\t\tL_LDPC\t= 1296.;\n\t} else if\t(N_TCB <= 1944.) {\n\t\tN_CW\t= 1.;\n\t\tL_LDPC\t= 1944.;\n\t} else if (N_TCB <= 2592.) {\n\t\tN_CW\t= 2.;\n\t\tif (N_TCB >= N_pld + 2916.*(1. - CR))\n\t\t\tL_LDPC\t= 1944.;\n\t\telse\n\t\t\tL_LDPC\t= 1296.;\n\t} else {\n\t\tN_CW = ceil(N_pld / 1944. / CR);\n\t\tL_LDPC\t= 1944.;\n\t}\n\t/*\tNumber of information bits per CW*/\n\tK_LDPC = L_LDPC * CR;\n\t/*\tNumber of shortening bits\t\t\t\t\tmax(0, (N_CW * L_LDPC * R) - N_pld)*/\n\tN_shrt = (N_CW * K_LDPC - N_pld) > 0. ? (N_CW * K_LDPC - N_pld) : 0.;\n\t/*\tNumber of shortening bits per CW\t\t\tN_spcw = rtfloor(N_shrt/N_CW)*/\n\tN_spcw = rtfloor(N_shrt / N_CW);\n\t/*\tThe first N_fshrt CWs shorten 1 bit more*/\n\tN_fshrt = (double)((int)N_shrt % (int)N_CW);\n\t/*\tNumber of data bits for the last N_CW-N_fshrt CWs*/\n\tL_LDPC_info = K_LDPC - N_spcw;\n\t/*\tNumber of puncturing bits*/\n\tN_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;\n\tif (((N_punc > .1 * N_CW * L_LDPC * (1. - CR)) && (N_shrt < 1.2 * N_punc * CR / (1. - CR))) ||\n\t    (N_punc > 0.3 * N_CW * L_LDPC * (1. - CR))) {\n\t\t/*cout << \"*** N_TCB and N_punc are Recomputed ***\" << endl;*/\n\t\tVHTSIGA2B3 = 1;\n\t\tN_TCB += (double)N_CBPSS * N_SS * m_STBC;\n\t\tN_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;\n\t} else\n\t\tVHTSIGA2B3 = 0;\n\n\treturn VHTSIGA2B3;\n}\t/* function end of LDPC_parameter_generator */\n\n/*========================================\n\tData field of PPDU\n\tGet N_sym and SIGA2BB3\n========================================*/\nvoid PMAC_Nsym_generator(\n\tPRT_PMAC_TX_INFO\tpPMacTxInfo,\n\tPRT_PMAC_PKT_INFO\tpPMacPktInfo)\n{\n\tu32\tSIGA2B3 = 0;\n\tu8\tTX_RATE = pPMacTxInfo->TX_RATE;\n\n\tu32 R, R_list[10] = {0, 0, 2, 0, 2, 1, 2, 3, 2, 3};\n\tdouble CR = 0;\n\tu32 N_SD, N_BPSC_list[10] = {1, 2, 2, 4, 4, 6, 6, 6, 8, 8};\n\tu32 N_BPSC = 0, N_CBPS = 0, N_DBPS = 0, N_ES = 0, N_SYM = 0, N_pld = 0, N_TCB = 0;\n\tint D_R = 0;\n\n\tRTW_INFO(\"TX_RATE = %d\\n\", TX_RATE);\n\t/*\tN_SD*/\n\tif (pPMacTxInfo->BandWidth == 0)\n\t\tN_SD = 52;\n\telse if (pPMacTxInfo->BandWidth == 1)\n\t\tN_SD = 108;\n\telse\n\t\tN_SD = 234;\n\n\tif (MPT_IS_HT_RATE(TX_RATE)) {\n\t\tu8 MCS_temp;\n\n\t\tif (pPMacPktInfo->MCS > 23)\n\t\t\tMCS_temp = pPMacPktInfo->MCS - 24;\n\t\telse if (pPMacPktInfo->MCS > 15)\n\t\t\tMCS_temp = pPMacPktInfo->MCS - 16;\n\t\telse if (pPMacPktInfo->MCS > 7)\n\t\t\tMCS_temp = pPMacPktInfo->MCS - 8;\n\t\telse\n\t\t\tMCS_temp = pPMacPktInfo->MCS;\n\n\t\tR = R_list[MCS_temp];\n\n\t\tswitch (R) {\n\t\tcase 0:\n\t\t\tCR = .5;\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tCR = 2. / 3.;\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tCR = 3. / 4.;\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\tCR = 5. / 6.;\n\t\t\tbreak;\n\t\t}\n\n\t\tN_BPSC = N_BPSC_list[MCS_temp];\n\t\tN_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;\n\t\tN_DBPS = (u32)((double)N_CBPS * CR);\n\n\t\tif (pPMacTxInfo->bLDPC == FALSE) {\n\t\t\tN_ES = (u32)ceil((double)(N_DBPS * pPMacPktInfo->Nss) / 4. / 300.);\n\t\t\tRTW_INFO(\"N_ES = %d\\n\", N_ES);\n\n\t\t\t/*\tN_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/\n\t\t\tN_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) /\n\t\t\t\t\t(double)(N_DBPS * pPMacTxInfo->m_STBC));\n\n\t\t} else {\n\t\t\tN_ES = 1;\n\t\t\t/*\tN_pld = length * 8 + 16*/\n\t\t\tN_pld = pPMacTxInfo->PacketLength * 8 + 16;\n\t\t\tRTW_INFO(\"N_pld = %d\\n\", N_pld);\n\t\t\tN_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(N_pld) /\n\t\t\t\t\t(double)(N_DBPS * pPMacTxInfo->m_STBC));\n\t\t\tRTW_INFO(\"N_SYM = %d\\n\", N_SYM);\n\t\t\t/*\tN_avbits = N_CBPS *m_STBC *(N_pld/N_CBPS*R*m_STBC)*/\n\t\t\tN_TCB = N_CBPS * N_SYM;\n\t\t\tRTW_INFO(\"N_TCB = %d\\n\", N_TCB);\n\t\t\tSIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);\n\t\t\tRTW_INFO(\"SIGA2B3 = %d\\n\", SIGA2B3);\n\t\t\tN_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;\n\t\t\tRTW_INFO(\"N_SYM = %d\\n\", N_SYM);\n\t\t}\n\t} else if (MPT_IS_VHT_RATE(TX_RATE)) {\n\t\tR = R_list[pPMacPktInfo->MCS];\n\n\t\tswitch (R) {\n\t\tcase 0:\n\t\t\tCR = .5;\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tCR = 2. / 3.;\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tCR = 3. / 4.;\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\tCR = 5. / 6.;\n\t\t\tbreak;\n\t\t}\n\t\tN_BPSC = N_BPSC_list[pPMacPktInfo->MCS];\n\t\tN_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;\n\t\tN_DBPS = (u32)((double)N_CBPS * CR);\n\t\tif (pPMacTxInfo->bLDPC == FALSE) {\n\t\t\tif (pPMacTxInfo->bSGI)\n\t\t\t\tN_ES = (u32)ceil((double)(N_DBPS) / 3.6 / 600.);\n\t\t\telse\n\t\t\t\tN_ES = (u32)ceil((double)(N_DBPS) / 4. / 600.);\n\t\t\t/*\tN_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/\n\t\t\tN_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) / (double)(N_DBPS * pPMacTxInfo->m_STBC));\n\t\t\tSIGA2B3 = 0;\n\t\t} else {\n\t\t\tN_ES = 1;\n\t\t\t/*\tN_SYM = m_STBC* (8*length+N_service) / (m_STBC*N_DBPS)*/\n\t\t\tN_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16) / (double)(N_DBPS * pPMacTxInfo->m_STBC));\n\t\t\t/*\tN_avbits = N_sys_init * N_CBPS*/\n\t\t\tN_TCB = N_CBPS * N_SYM;\n\t\t\t/*\tN_pld = N_sys_init * N_DBPS*/\n\t\t\tN_pld = N_SYM * N_DBPS;\n\t\t\tSIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);\n\t\t\tN_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;\n\t\t}\n\n\t\tswitch (R) {\n\t\tcase 0:\n\t\t\tD_R = 2;\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tD_R = 3;\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tD_R = 4;\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\tD_R = 6;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (((N_CBPS / N_ES) % D_R) != 0) {\n\t\t\tRTW_INFO(\"MCS= %d is not supported when Nss=%d and BW= %d !!\\n\",  pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);\n\t\t\treturn;\n\t\t}\n\n\t\tRTW_INFO(\"MCS= %d Nss=%d and BW= %d !!\\n\",  pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);\n\t}\n\n\tpPMacPktInfo->N_sym = N_SYM;\n\tpPMacPktInfo->SIGA2B3 = SIGA2B3;\n}\n\n/*========================================\n\tL-SIG\tRate\tR\tLength\tP\tTail\n\t\t\t4b\t\t1b\t12b\t\t1b\t6b\n========================================*/\n\nvoid L_SIG_generator(\n\tu32\tN_SYM,\t\t/* Max: 750*/\n\tPRT_PMAC_TX_INFO\tpPMacTxInfo,\n\tPRT_PMAC_PKT_INFO\tpPMacPktInfo)\n{\n\tu8\tsig_bi[24] = {0};\t/* 24 BIT*/\n\tu32\tmode, LENGTH;\n\tint i;\n\n\tif (MPT_IS_OFDM_RATE(pPMacTxInfo->TX_RATE)) {\n\t\tmode = pPMacPktInfo->MCS;\n\t\tLENGTH = pPMacTxInfo->PacketLength;\n\t} else {\n\t\tu8\tN_LTF;\n\t\tdouble\tT_data;\n\t\tu32\tOFDM_symbol;\n\n\t\tmode = 0;\n\n\t\t/*\tTable 20-13 Num of HT-DLTFs request*/\n\t\tif (pPMacPktInfo->Nsts <= 2)\n\t\t\tN_LTF = pPMacPktInfo->Nsts;\n\t\telse\n\t\t\tN_LTF = 4;\n\n\t\tif (pPMacTxInfo->bSGI)\n\t\t\tT_data = 3.6;\n\t\telse\n\t\t\tT_data = 4.0;\n\n\t\t/*(L-SIG, HT-SIG, HT-STF, HT-LTF....HT-LTF, Data)*/\n\t\tif (MPT_IS_VHT_RATE(pPMacTxInfo->TX_RATE))\n\t\t\tOFDM_symbol = (u32)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data + 4) / 4.);\n\t\telse\n\t\t\tOFDM_symbol = (u32)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data) / 4.);\n\n\t\tRTW_INFO(\"%s , OFDM_symbol =%d\\n\", __func__, OFDM_symbol);\n\t\tLENGTH = OFDM_symbol * 3 - 3;\n\t\tRTW_INFO(\"%s , LENGTH =%d\\n\", __func__, LENGTH);\n\n\t}\n\t/*\tRate Field*/\n\tswitch (mode) {\n\tcase\t0:\n\t\tsig_bi[0] = 1;\n\t\tsig_bi[1] = 1;\n\t\tsig_bi[2] = 0;\n\t\tsig_bi[3] = 1;\n\t\tbreak;\n\tcase\t1:\n\t\tsig_bi[0] = 1;\n\t\tsig_bi[1] = 1;\n\t\tsig_bi[2] = 1;\n\t\tsig_bi[3] = 1;\n\t\tbreak;\n\tcase\t2:\n\t\tsig_bi[0] = 0;\n\t\tsig_bi[1] = 1;\n\t\tsig_bi[2] = 0;\n\t\tsig_bi[3] = 1;\n\t\tbreak;\n\tcase\t3:\n\t\tsig_bi[0] = 0;\n\t\tsig_bi[1] = 1;\n\t\tsig_bi[2] = 1;\n\t\tsig_bi[3] = 1;\n\t\tbreak;\n\tcase\t4:\n\t\tsig_bi[0] = 1;\n\t\tsig_bi[1] = 0;\n\t\tsig_bi[2] = 0;\n\t\tsig_bi[3] = 1;\n\t\tbreak;\n\tcase\t5:\n\t\tsig_bi[0] = 1;\n\t\tsig_bi[1] = 0;\n\t\tsig_bi[2] = 1;\n\t\tsig_bi[3] = 1;\n\t\tbreak;\n\tcase\t6:\n\t\tsig_bi[0] = 0;\n\t\tsig_bi[1] = 0;\n\t\tsig_bi[2] = 0;\n\t\tsig_bi[3] = 1;\n\t\tbreak;\n\tcase\t7:\n\t\tsig_bi[0] = 0;\n\t\tsig_bi[1] = 0;\n\t\tsig_bi[2] = 1;\n\t\tsig_bi[3] = 1;\n\t\tbreak;\n\t}\n\t/*Reserved bit*/\n\tsig_bi[4] = 0;\n\n\t/*\tLength Field*/\n\tfor (i = 0; i < 12; i++)\n\t\tsig_bi[i + 5] = (LENGTH >> i) & 1;\n\n\t/* Parity Bit*/\n\tsig_bi[17] = 0;\n\tfor (i = 0; i < 17; i++)\n\t\tsig_bi[17] = sig_bi[17] + sig_bi[i];\n\n\tsig_bi[17] %= 2;\n\n\t/*\tTail Field*/\n\tfor (i = 18; i < 24; i++)\n\t\tsig_bi[i] = 0;\n\n\t/* dump_buf(sig_bi,24);*/\n\t_rtw_memset(pPMacTxInfo->LSIG, 0, 3);\n\tByteToBit(pPMacTxInfo->LSIG, (bool *)sig_bi, 3);\n}\n\n\nvoid CRC8_generator(\n\tbool\t*out,\n\tbool\t*in,\n\tu8\tin_size\n)\n{\n\tu8 i = 0;\n\tbool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1};\n\n\tfor (i = 0; i < in_size; i++) { /* take one's complement and bit reverse*/\n\t\ttemp = in[i] ^ reg[7];\n\t\treg[7]\t= reg[6];\n\t\treg[6]\t= reg[5];\n\t\treg[5]\t= reg[4];\n\t\treg[4]\t= reg[3];\n\t\treg[3]\t= reg[2];\n\t\treg[2]\t= reg[1] ^ temp;\n\t\treg[1]\t= reg[0] ^ temp;\n\t\treg[0]\t= temp;\n\t}\n\tfor (i = 0; i < 8; i++)/* take one's complement and bit reverse*/\n\t\tout[i] = reg[7 - i] ^ 1;\n}\n\n/*/================================================================================\n\tHT-SIG1\tMCS\tCW\tLength\t\t24BIT + 24BIT\n\t\t\t7b\t1b\t16b\n\tHT-SIG2\tSmoothing\tNot sounding\tRsvd\t\tAGG\tSTBC\tFEC\tSGI\tN_ELTF\tCRC\tTail\n\t\t\t1b\t\t\t1b\t\t\t1b\t\t1b\t2b\t\t1b\t1b\t2b\t\t8b\t6b\n================================================================================*/\nvoid HT_SIG_generator(\n\tPRT_PMAC_TX_INFO\tpPMacTxInfo,\n\tPRT_PMAC_PKT_INFO\tpPMacPktInfo\n)\n{\n\tu32 i;\n\tbool sig_bi[48] = {0}, crc8[8] = {0};\n\t/*\tMCS Field*/\n\tfor (i = 0; i < 7; i++)\n\t\tsig_bi[i] = (pPMacPktInfo->MCS >> i) & 0x1;\n\t/*\tPacket BW Setting*/\n\tsig_bi[7] = pPMacTxInfo->BandWidth;\n\t/*\tHT-Length Field*/\n\tfor (i = 0; i < 16; i++)\n\t\tsig_bi[i + 8] = (pPMacTxInfo->PacketLength >> i) & 0x1;\n\t/*\tSmoothing;\t1->allow smoothing*/\n\tsig_bi[24] = 1;\n\t/*Not Sounding*/\n\tsig_bi[25] = 1 - pPMacTxInfo->NDP_sound;\n\t/*Reserved bit*/\n\tsig_bi[26] = 1;\n\t/*/Aggregate*/\n\tsig_bi[27] = 0;\n\t/*STBC Field*/\n\tif (pPMacTxInfo->bSTBC) {\n\t\tsig_bi[28] = 1;\n\t\tsig_bi[29] = 0;\n\t} else {\n\t\tsig_bi[28] = 0;\n\t\tsig_bi[29] = 0;\n\t}\n\t/*Advance Coding,\t0: BCC, 1: LDPC*/\n\tsig_bi[30] = pPMacTxInfo->bLDPC;\n\t/* Short GI*/\n\tsig_bi[31] = pPMacTxInfo->bSGI;\n\t/* N_ELTFs*/\n\tif (pPMacTxInfo->NDP_sound == FALSE) {\n\t\tsig_bi[32]\t= 0;\n\t\tsig_bi[33]\t= 0;\n\t} else {\n\t\tint\tN_ELTF = pPMacTxInfo->Ntx - pPMacPktInfo->Nss;\n\n\t\tfor (i = 0; i < 2; i++)\n\t\t\tsig_bi[32 + i] = (N_ELTF >> i) % 2;\n\t}\n\t/*\tCRC-8*/\n\tCRC8_generator(crc8, sig_bi, 34);\n\n\tfor (i = 0; i < 8; i++)\n\t\tsig_bi[34 + i] = crc8[i];\n\n\t/*Tail*/\n\tfor (i = 42; i < 48; i++)\n\t\tsig_bi[i] = 0;\n\n\t_rtw_memset(pPMacTxInfo->HT_SIG, 0, 6);\n\tByteToBit(pPMacTxInfo->HT_SIG, sig_bi, 6);\n}\n\n\n/*======================================================================================\n\tVHT-SIG-A1\n\tBW\tReserved\tSTBC\tG_ID\tSU_Nsts\tP_AID\tTXOP_PS_NOT_ALLOW\tReserved\n\t2b\t1b\t\t\t1b\t\t6b\t3b\t9b\t\t1b\t\t2b\t\t\t\t\t1b\n\tVHT-SIG-A2\n\tSGI\tSGI_Nsym\tSU/MU coding\tLDPC_Extra\tSU_NCS\tBeamformed\tReserved\tCRC\tTail\n\t1b\t1b\t\t\t1b\t\t\t\t1b\t\t\t4b\t\t1b\t\t\t1b\t\t\t8b\t6b\n======================================================================================*/\nvoid VHT_SIG_A_generator(\n\tPRT_PMAC_TX_INFO\tpPMacTxInfo,\n\tPRT_PMAC_PKT_INFO\tpPMacPktInfo)\n{\n\tu32 i;\n\tbool sig_bi[48], crc8[8];\n\n\t_rtw_memset(sig_bi, 0, 48);\n\t_rtw_memset(crc8, 0, 8);\n\n\t/*\tBW Setting*/\n\tfor (i = 0; i < 2; i++)\n\t\tsig_bi[i] = (pPMacTxInfo->BandWidth >> i) & 0x1;\n\t/* Reserved Bit*/\n\tsig_bi[2] = 1;\n\t/*STBC Field*/\n\tsig_bi[3] = pPMacTxInfo->bSTBC;\n\t/*Group ID: Single User->A value of 0 or 63 indicates an SU PPDU. */\n\tfor (i = 0; i < 6; i++)\n\t\tsig_bi[4 + i] = 0;\n\t/*\tN_STS/Partial AID*/\n\tfor (i = 0; i < 12; i++) {\n\t\tif (i < 3)\n\t\t\tsig_bi[10 + i] = ((pPMacPktInfo->Nsts - 1) >> i) & 0x1;\n\t\telse\n\t\t\tsig_bi[10 + i] = 0;\n\t}\n\t/*TXOP_PS_NOT_ALLPWED*/\n\tsig_bi[22]\t= 0;\n\t/*Reserved Bits*/\n\tsig_bi[23]\t= 1;\n\t/*Short GI*/\n\tsig_bi[24] = pPMacTxInfo->bSGI;\n\tif (pPMacTxInfo->bSGI > 0 && (pPMacPktInfo->N_sym % 10) == 9)\n\t\tsig_bi[25] = 1;\n\telse\n\t\tsig_bi[25] = 0;\n\t/* SU/MU[0] Coding*/\n\tsig_bi[26] = pPMacTxInfo->bLDPC;\t/*\t0:BCC, 1:LDPC\t\t*/\n\tsig_bi[27] = pPMacPktInfo->SIGA2B3;\t/*/\tRecord Extra OFDM Symols is added or not when LDPC is used*/\n\t/*SU MCS/MU[1-3] Coding*/\n\tfor (i = 0; i < 4; i++)\n\t\tsig_bi[28 + i] = (pPMacPktInfo->MCS >> i) & 0x1;\n\t/*SU Beamform */\n\tsig_bi[32] = 0;\t/*packet.TXBF_en;*/\n\t/*Reserved Bit*/\n\tsig_bi[33] = 1;\n\t/*CRC-8*/\n\tCRC8_generator(crc8, sig_bi, 34);\n\tfor (i = 0; i < 8; i++)\n\t\tsig_bi[34 + i]\t= crc8[i];\n\t/*Tail*/\n\tfor (i = 42; i < 48; i++)\n\t\tsig_bi[i] = 0;\n\n\t_rtw_memset(pPMacTxInfo->VHT_SIG_A, 0, 6);\n\tByteToBit(pPMacTxInfo->VHT_SIG_A, sig_bi, 6);\n}\n\n/*======================================================================================\n\tVHT-SIG-B\n\tLength\t\t\t\tResesrved\tTrail\n\t17/19/21 BIT\t\t3/2/2 BIT\t6b\n======================================================================================*/\nvoid VHT_SIG_B_generator(\n\tPRT_PMAC_TX_INFO\tpPMacTxInfo)\n{\n\tbool sig_bi[32], crc8_bi[8];\n\tu32 i, len, res, tail = 6, total_len, crc8_in_len;\n\tu32 sigb_len;\n\n\t_rtw_memset(sig_bi, 0, 32);\n\t_rtw_memset(crc8_bi, 0, 8);\n\n\t/*Sounding Packet*/\n\tif (pPMacTxInfo->NDP_sound == 1) {\n\t\tif (pPMacTxInfo->BandWidth == 0) {\n\t\t\tbool sigb_temp[26] = {0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};\n\n\t\t\t_rtw_memcpy(sig_bi, sigb_temp, 26);\n\t\t} else if (pPMacTxInfo->BandWidth == 1) {\n\t\t\tbool sigb_temp[27] = {1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0};\n\n\t\t\t_rtw_memcpy(sig_bi, sigb_temp, 27);\n\t\t} else if (pPMacTxInfo->BandWidth == 2) {\n\t\t\tbool sigb_temp[29] = {0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};\n\n\t\t\t_rtw_memcpy(sig_bi, sigb_temp, 29);\n\t\t}\n\t} else {\t/* Not NDP Sounding*/\n\t\tbool *sigb_temp[29] = {0};\n\n\t\tif (pPMacTxInfo->BandWidth == 0) {\n\t\t\tlen = 17;\n\t\t\tres = 3;\n\t\t} else if (pPMacTxInfo->BandWidth == 1) {\n\t\t\tlen = 19;\n\t\t\tres = 2;\n\t\t} else if (pPMacTxInfo->BandWidth == 2) {\n\t\t\tlen\t= 21;\n\t\t\tres\t= 2;\n\t\t} else {\n\t\t\tlen\t= 21;\n\t\t\tres\t= 2;\n\t\t}\n\t\ttotal_len = len + res + tail;\n\t\tcrc8_in_len = len + res;\n\n\t\t/*Length Field*/\n\t\tsigb_len = (pPMacTxInfo->PacketLength + 3) >> 2;\n\n\t\tfor (i = 0; i < len; i++)\n\t\t\tsig_bi[i] = (sigb_len >> i) & 0x1;\n\t\t/*Reserved Field*/\n\t\tfor (i = 0; i < res; i++)\n\t\t\tsig_bi[len + i] = 1;\n\t\t/* CRC-8*/\n\t\tCRC8_generator(crc8_bi, sig_bi, crc8_in_len);\n\n\t\t/* Tail */\n\t\tfor (i = 0; i < tail; i++)\n\t\t\tsig_bi[len + res + i] = 0;\n\t}\n\n\t_rtw_memset(pPMacTxInfo->VHT_SIG_B, 0, 4);\n\tByteToBit(pPMacTxInfo->VHT_SIG_B, sig_bi, 4);\n\n\tpPMacTxInfo->VHT_SIG_B_CRC = 0;\n\tByteToBit(&(pPMacTxInfo->VHT_SIG_B_CRC), crc8_bi, 1);\n}\n\n/*=======================\n VHT Delimiter\n=======================*/\nvoid VHT_Delimiter_generator(\n\tPRT_PMAC_TX_INFO\tpPMacTxInfo\n)\n{\n\tbool sig_bi[32] = {0}, crc8[8] = {0};\n\tu32 crc8_in_len = 16;\n\tu32 PacketLength = pPMacTxInfo->PacketLength;\n\tint j;\n\n\t/* Delimiter[0]: EOF*/\n\tsig_bi[0] = 1;\n\t/* Delimiter[1]: Reserved*/\n\tsig_bi[1] = 0;\n\t/* Delimiter[3:2]: MPDU Length High*/\n\tsig_bi[2] = ((PacketLength - 4) >> 12) % 2;\n\tsig_bi[3] = ((PacketLength - 4) >> 13) % 2;\n\t/* Delimiter[15:4]: MPDU Length Low*/\n\tfor (j = 4; j < 16; j++)\n\t\tsig_bi[j] = ((PacketLength - 4) >> (j - 4)) % 2;\n\tCRC8_generator(crc8, sig_bi, crc8_in_len);\n\tfor (j = 16; j < 24; j++) /* Delimiter[23:16]: CRC 8*/\n\t\tsig_bi[j] = crc8[j - 16];\n\tfor (j = 24; j < 32; j++) /* Delimiter[31:24]: Signature ('4E' in Hex, 78 in Dec)*/\n\t\tsig_bi[j]\t= (78 >> (j - 24)) % 2;\n\n\t_rtw_memset(pPMacTxInfo->VHT_Delimiter, 0, 4);\n\tByteToBit(pPMacTxInfo->VHT_Delimiter, sig_bi, 4);\n}\n\n#endif\n#endif\n"
  },
  {
    "path": "core/rtw_odm.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include <rtw_odm.h>\n#include <hal_data.h>\n\nu32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);\n\tstruct dm_struct *podmpriv = &pHalData->odmpriv;\n\tu32 result = 0;\n\n\tswitch (ops) {\n\tcase HAL_PHYDM_DIS_ALL_FUNC:\n\t\tpodmpriv->support_ability = DYNAMIC_FUNC_DISABLE;\n\t\thalrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, DYNAMIC_FUNC_DISABLE);\n\t\tbreak;\n\tcase HAL_PHYDM_FUNC_SET:\n\t\tpodmpriv->support_ability |= ability;\n\t\tbreak;\n\tcase HAL_PHYDM_FUNC_CLR:\n\t\tpodmpriv->support_ability &= ~(ability);\n\t\tbreak;\n\tcase HAL_PHYDM_ABILITY_BK:\n\t\t/* dm flag backup*/\n\t\tpodmpriv->bk_support_ability = podmpriv->support_ability;\n\t\tpHalData->bk_rf_ability = halrf_cmn_info_get(podmpriv, HALRF_CMNINFO_ABILITY);\n\t\tbreak;\n\tcase HAL_PHYDM_ABILITY_RESTORE:\n\t\t/* restore dm flag */\n\t\tpodmpriv->support_ability = podmpriv->bk_support_ability;\n\t\thalrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, pHalData->bk_rf_ability);\n\t\tbreak;\n\tcase HAL_PHYDM_ABILITY_SET:\n\t\tpodmpriv->support_ability = ability;\n\t\tbreak;\n\tcase HAL_PHYDM_ABILITY_GET:\n\t\tresult = podmpriv->support_ability;\n\t\tbreak;\n\t}\n\treturn result;\n}\n\n/* set ODM_CMNINFO_IC_TYPE based on chip_type */\nvoid rtw_odm_init_ic_type(_adapter *adapter)\n{\n\tstruct dm_struct *odm = adapter_to_phydm(adapter);\n\tu32 ic_type = chip_type_to_odm_ic_type(rtw_get_chip_type(adapter));\n\n\trtw_warn_on(!ic_type);\n\n\todm_cmn_info_init(odm, ODM_CMNINFO_IC_TYPE, ic_type);\n}\n\nvoid rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)\n{\n\tRTW_PRINT_SEL(sel, \"ADAPTIVITY_VERSION \"ADAPTIVITY_VERSION\"\\n\");\n}\n\n#define RTW_ADAPTIVITY_EN_DISABLE 0\n#define RTW_ADAPTIVITY_EN_ENABLE 1\n\nvoid rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter)\n{\n\tstruct registry_priv *regsty = &adapter->registrypriv;\n\n\tRTW_PRINT_SEL(sel, \"RTW_ADAPTIVITY_EN_\");\n\n\tif (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_DISABLE)\n\t\t_RTW_PRINT_SEL(sel, \"DISABLE\\n\");\n\telse if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)\n\t\t_RTW_PRINT_SEL(sel, \"ENABLE\\n\");\n\telse\n\t\t_RTW_PRINT_SEL(sel, \"INVALID\\n\");\n}\n\n#define RTW_ADAPTIVITY_MODE_NORMAL 0\n#define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1\n\nvoid rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter)\n{\n\tstruct registry_priv *regsty = &adapter->registrypriv;\n\n\tRTW_PRINT_SEL(sel, \"RTW_ADAPTIVITY_MODE_\");\n\n\tif (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_NORMAL)\n\t\t_RTW_PRINT_SEL(sel, \"NORMAL\\n\");\n\telse if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_CARRIER_SENSE)\n\t\t_RTW_PRINT_SEL(sel, \"CARRIER_SENSE\\n\");\n\telse\n\t\t_RTW_PRINT_SEL(sel, \"INVALID\\n\");\n}\n\nvoid rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter)\n{\n\trtw_odm_adaptivity_ver_msg(sel, adapter);\n\trtw_odm_adaptivity_en_msg(sel, adapter);\n\trtw_odm_adaptivity_mode_msg(sel, adapter);\n}\n\nbool rtw_odm_adaptivity_needed(_adapter *adapter)\n{\n\tstruct registry_priv *regsty = &adapter->registrypriv;\n\tbool ret = _FALSE;\n\n\tif (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)\n\t\tret = _TRUE;\n\n\treturn ret;\n}\n\nvoid rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter)\n{\n\tstruct dm_struct *odm = adapter_to_phydm(adapter);\n\n\trtw_odm_adaptivity_config_msg(sel, adapter);\n\n\tRTW_PRINT_SEL(sel, \"%10s %16s\\n\"\n\t\t, \"th_l2h_ini\", \"th_edcca_hl_diff\");\n\tRTW_PRINT_SEL(sel, \"0x%-8x %-16d\\n\"\n\t\t, (u8)odm->th_l2h_ini\n\t\t, odm->th_edcca_hl_diff\n\t);\n}\n\nvoid rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff)\n{\n\tstruct dm_struct *odm = adapter_to_phydm(adapter);\n\n\todm->th_l2h_ini = th_l2h_ini;\n\todm->th_edcca_hl_diff = th_edcca_hl_diff;\n}\n\nvoid rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter)\n{\n\tstruct dm_struct *odm = adapter_to_phydm(adapter);\n\n\tRTW_PRINT_SEL(sel, \"rx_rate = %s, rssi_a = %d(%%), rssi_b = %d(%%)\\n\",\n\t\t      HDATA_RATE(odm->rx_rate), odm->rssi_a, odm->rssi_b);\n}\n\n\nvoid rtw_odm_acquirespinlock(_adapter *adapter,\tenum rt_spinlock_type type)\n{\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(adapter);\n\t_irqL irqL;\n\n\tswitch (type) {\n\tcase RT_IQK_SPINLOCK:\n\t\t_enter_critical_bh(&pHalData->IQKSpinLock, &irqL);\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid rtw_odm_releasespinlock(_adapter *adapter,\tenum rt_spinlock_type type)\n{\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(adapter);\n\t_irqL irqL;\n\n\tswitch (type) {\n\tcase RT_IQK_SPINLOCK:\n\t\t_exit_critical_bh(&pHalData->IQKSpinLock, &irqL);\n\tdefault:\n\t\tbreak;\n\t}\n}\n\ninline u8 rtw_odm_get_dfs_domain(struct dvobj_priv *dvobj)\n{\n#ifdef CONFIG_DFS_MASTER\n\tstruct dm_struct *pDM_Odm = dvobj_to_phydm(dvobj);\n\n\treturn pDM_Odm->dfs_region_domain;\n#else\n\treturn PHYDM_DFS_DOMAIN_UNKNOWN;\n#endif\n}\n\ninline u8 rtw_odm_dfs_domain_unknown(struct dvobj_priv *dvobj)\n{\n#ifdef CONFIG_DFS_MASTER\n\treturn rtw_odm_get_dfs_domain(dvobj) == PHYDM_DFS_DOMAIN_UNKNOWN;\n#else\n\treturn 1;\n#endif\n}\n\n#ifdef CONFIG_DFS_MASTER\ninline void rtw_odm_radar_detect_reset(_adapter *adapter)\n{\n\tphydm_radar_detect_reset(adapter_to_phydm(adapter));\n}\n\ninline void rtw_odm_radar_detect_disable(_adapter *adapter)\n{\n\tphydm_radar_detect_disable(adapter_to_phydm(adapter));\n}\n\n/* called after ch, bw is set */\ninline void rtw_odm_radar_detect_enable(_adapter *adapter)\n{\n\tphydm_radar_detect_enable(adapter_to_phydm(adapter));\n}\n\ninline BOOLEAN rtw_odm_radar_detect(_adapter *adapter)\n{\n\treturn phydm_radar_detect(adapter_to_phydm(adapter));\n}\n\ninline u8 rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv *dvobj)\n{\n\treturn phydm_dfs_polling_time(dvobj_to_phydm(dvobj));\n}\n#endif /* CONFIG_DFS_MASTER */\n\nvoid rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys)\n{\n#ifndef DBG_RX_PHYSTATUS_CHINFO\n#define DBG_RX_PHYSTATUS_CHINFO 0\n#endif\n\n#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)\n\t_adapter *adapter = rframe->u.hdr.adapter;\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n\tstruct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib;\n\tu8 *wlanhdr = get_recvframe_data(rframe);\n\n\tif (phydm->support_ic_type & PHYSTS_2ND_TYPE_IC) {\n\t\t/*\n\t\t* 8723D:\n\t\t* type_0(CCK)\n\t\t*     l_rxsc\n\t\t*         is filled with primary channel SC, not real rxsc.\n\t\t*         0:LSC, 1:USC\n\t\t* type_1(OFDM)\n\t\t*     rf_mode\n\t\t*         RF bandwidth when RX\n\t\t*     l_rxsc(legacy), ht_rxsc\n\t\t*         see below RXSC N-series\n\t\t* type_2(Not used)\n\t\t*/\n\t\t/*\n\t\t* 8821C, 8822B:\n\t\t* type_0(CCK)\n\t\t*     l_rxsc\n\t\t*         is filled with primary channel SC, not real rxsc.\n\t\t*         0:LSC, 1:USC\n\t\t* type_1(OFDM)\n\t\t*     rf_mode\n\t\t*         RF bandwidth when RX\n\t\t*     l_rxsc(legacy), ht_rxsc\n\t\t*         see below RXSC AC-series\n\t\t* type_2(Not used)\n\t\t*/\n\n\t\tif ((*phys & 0xf) == 0) {\n\t\t\tstruct phy_sts_rpt_jgr2_type0 *phys_t0 = (struct phy_sts_rpt_jgr2_type0 *)phys;\n\n\t\t\tif (DBG_RX_PHYSTATUS_CHINFO) {\n\t\t\t\tRTW_PRINT(\"phys_t%u ta=\"MAC_FMT\" %s, %s(band:%u, ch:%u, l_rxsc:%u)\\n\"\n\t\t\t\t\t, *phys & 0xf\n\t\t\t\t\t, MAC_ARG(get_ta(wlanhdr))\n\t\t\t\t\t, is_broadcast_mac_addr(get_ra(wlanhdr)) ? \"BC\" : is_multicast_mac_addr(get_ra(wlanhdr)) ? \"MC\" : \"UC\"\n\t\t\t\t\t, HDATA_RATE(attrib->data_rate)\n\t\t\t\t\t, phys_t0->band, phys_t0->channel, phys_t0->rxsc\n\t\t\t\t);\n\t\t\t}\n\n\t\t} else if ((*phys & 0xf) == 1) {\n\t\t\tstruct phy_sts_rpt_jgr2_type1 *phys_t1 = (struct phy_sts_rpt_jgr2_type1 *)phys;\n\t\t\tu8 rxsc = (attrib->data_rate > DESC_RATE11M && attrib->data_rate < DESC_RATEMCS0) ? phys_t1->l_rxsc : phys_t1->ht_rxsc;\n\t\t\tu8 pkt_cch = 0;\n\t\t\tu8 pkt_bw = CHANNEL_WIDTH_20;\n\n\t\t\t#if\tODM_IC_11N_SERIES_SUPPORT\n\t\t\tif (phydm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\t\t\t/* RXSC N-series */\n\t\t\t\t#define RXSC_DUP\t0\n\t\t\t\t#define RXSC_LSC\t1\n\t\t\t\t#define RXSC_USC\t2\n\t\t\t\t#define RXSC_40M\t3\n\n\t\t\t\tstatic const s8 cch_offset_by_rxsc[4] = {0, -2, 2, 0};\n\n\t\t\t\tif (phys_t1->rf_mode == 0) {\n\t\t\t\t\tpkt_cch = phys_t1->channel;\n\t\t\t\t\tpkt_bw = CHANNEL_WIDTH_20;\n\t\t\t\t} else if (phys_t1->rf_mode == 1) {\n\t\t\t\t\tif (rxsc == RXSC_LSC || rxsc == RXSC_USC) {\n\t\t\t\t\t\tpkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];\n\t\t\t\t\t\tpkt_bw = CHANNEL_WIDTH_20;\n\t\t\t\t\t} else if (rxsc == RXSC_40M) {\n\t\t\t\t\t\tpkt_cch = phys_t1->channel;\n\t\t\t\t\t\tpkt_bw = CHANNEL_WIDTH_40;\n\t\t\t\t\t}\n\t\t\t\t} else\n\t\t\t\t\trtw_warn_on(1);\n\n\t\t\t\tgoto type1_end;\n\t\t\t}\n\t\t\t#endif /* ODM_IC_11N_SERIES_SUPPORT */\n\n\t\t\t#if\tODM_IC_11AC_SERIES_SUPPORT\n\t\t\tif (phydm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\t\t\t/* RXSC AC-series */\n\t\t\t\t#define RXSC_DUP\t\t\t0 /* 0: RX from all SC of current rf_mode */\n\n\t\t\t\t#define RXSC_LL20M_OF_160M\t8 /* 1~8: RX from 20MHz SC */\n\t\t\t\t#define RXSC_L20M_OF_160M\t6\n\t\t\t\t#define RXSC_L20M_OF_80M\t4\n\t\t\t\t#define RXSC_L20M_OF_40M\t2\n\t\t\t\t#define RXSC_U20M_OF_40M\t1\n\t\t\t\t#define RXSC_U20M_OF_80M\t3\n\t\t\t\t#define RXSC_U20M_OF_160M\t5\n\t\t\t\t#define RXSC_UU20M_OF_160M\t7\n\n\t\t\t\t#define RXSC_L40M_OF_160M\t12 /* 9~12: RX from 40MHz SC */\n\t\t\t\t#define RXSC_L40M_OF_80M\t10\n\t\t\t\t#define RXSC_U40M_OF_80M\t9\n\t\t\t\t#define RXSC_U40M_OF_160M\t11\n\n\t\t\t\t#define RXSC_L80M_OF_160M\t14 /* 13~14: RX from 80MHz SC */\n\t\t\t\t#define RXSC_U80M_OF_160M\t13\n\n\t\t\t\tstatic const s8 cch_offset_by_rxsc[15] = {0, 2, -2, 6, -6, 10, -10, 14, -14, 4, -4, 12, -12, 8, -8};\n\n\t\t\t\tif (phys_t1->rf_mode > 3) {\n\t\t\t\t\t/* invalid rf_mode */\n\t\t\t\t\trtw_warn_on(1);\n\t\t\t\t\tgoto type1_end;\n\t\t\t\t}\n\n\t\t\t\tif (phys_t1->rf_mode == 0) {\n\t\t\t\t\t/* RF 20MHz */\n\t\t\t\t\tpkt_cch = phys_t1->channel;\n\t\t\t\t\tpkt_bw = CHANNEL_WIDTH_20;\n\t\t\t\t\tgoto type1_end;\n\t\t\t\t}\n\n\t\t\t\tif (rxsc == 0) {\n\t\t\t\t\t/* RF and RX with same BW */\n\t\t\t\t\tif (attrib->data_rate >= DESC_RATEMCS0) {\n\t\t\t\t\t\tpkt_cch = phys_t1->channel;\n\t\t\t\t\t\tpkt_bw = phys_t1->rf_mode;\n\t\t\t\t\t}\n\t\t\t\t\tgoto type1_end;\n\t\t\t\t}\n\n\t\t\t\tif ((phys_t1->rf_mode == 1 && rxsc >= 1 && rxsc <= 2) /* RF 40MHz, RX 20MHz */\n\t\t\t\t\t|| (phys_t1->rf_mode == 2 && rxsc >= 1 && rxsc <= 4) /* RF 80MHz, RX 20MHz */\n\t\t\t\t\t|| (phys_t1->rf_mode == 3 && rxsc >= 1 && rxsc <= 8) /* RF 160MHz, RX 20MHz */\n\t\t\t\t) {\n\t\t\t\t\tpkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];\n\t\t\t\t\tpkt_bw = CHANNEL_WIDTH_20;\n\t\t\t\t} else if ((phys_t1->rf_mode == 2 && rxsc >= 9 && rxsc <= 10) /* RF 80MHz, RX 40MHz */\n\t\t\t\t\t|| (phys_t1->rf_mode == 3 && rxsc >= 9 && rxsc <= 12) /* RF 160MHz, RX 40MHz */\n\t\t\t\t) {\n\t\t\t\t\tif (attrib->data_rate >= DESC_RATEMCS0) {\n\t\t\t\t\t\tpkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];\n\t\t\t\t\t\tpkt_bw = CHANNEL_WIDTH_40;\n\t\t\t\t\t}\n\t\t\t\t} else if ((phys_t1->rf_mode == 3 && rxsc >= 13 && rxsc <= 14) /* RF 160MHz, RX 80MHz */\n\t\t\t\t) {\n\t\t\t\t\tif (attrib->data_rate >= DESC_RATEMCS0) {\n\t\t\t\t\t\tpkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];\n\t\t\t\t\t\tpkt_bw = CHANNEL_WIDTH_80;\n\t\t\t\t\t}\n\t\t\t\t} else\n\t\t\t\t\trtw_warn_on(1);\n\n\t\t\t}\n\t\t\t#endif /* ODM_IC_11AC_SERIES_SUPPORT */\n\ntype1_end:\n\t\t\tif (DBG_RX_PHYSTATUS_CHINFO) {\n\t\t\t\tRTW_PRINT(\"phys_t%u ta=\"MAC_FMT\" %s, %s(band:%u, ch:%u, rf_mode:%u, l_rxsc:%u, ht_rxsc:%u) => %u,%u\\n\"\n\t\t\t\t\t, *phys & 0xf\n\t\t\t\t\t, MAC_ARG(get_ta(wlanhdr))\n\t\t\t\t\t, is_broadcast_mac_addr(get_ra(wlanhdr)) ? \"BC\" : is_multicast_mac_addr(get_ra(wlanhdr)) ? \"MC\" : \"UC\"\n\t\t\t\t\t, HDATA_RATE(attrib->data_rate)\n\t\t\t\t\t, phys_t1->band, phys_t1->channel, phys_t1->rf_mode, phys_t1->l_rxsc, phys_t1->ht_rxsc\n\t\t\t\t\t, pkt_cch, pkt_bw\n\t\t\t\t);\n\t\t\t}\n\n\t\t\t/* for now, only return cneter channel of 20MHz packet */\n\t\t\tif (pkt_cch && pkt_bw == CHANNEL_WIDTH_20)\n\t\t\t\tattrib->ch = pkt_cch;\n\n\t\t} else {\n\t\t\tstruct phy_sts_rpt_jgr2_type2 *phys_t2 = (struct phy_sts_rpt_jgr2_type2 *)phys;\n\n\t\t\tif (DBG_RX_PHYSTATUS_CHINFO) {\n\t\t\t\tRTW_PRINT(\"phys_t%u ta=\"MAC_FMT\" %s, %s(band:%u, ch:%u, l_rxsc:%u, ht_rxsc:%u)\\n\"\n\t\t\t\t\t, *phys & 0xf\n\t\t\t\t\t, MAC_ARG(get_ta(wlanhdr))\n\t\t\t\t\t, is_broadcast_mac_addr(get_ra(wlanhdr)) ? \"BC\" : is_multicast_mac_addr(get_ra(wlanhdr)) ? \"MC\" : \"UC\"\n\t\t\t\t\t, HDATA_RATE(attrib->data_rate)\n\t\t\t\t\t, phys_t2->band, phys_t2->channel, phys_t2->l_rxsc, phys_t2->ht_rxsc\n\t\t\t\t);\n\t\t\t}\n\t\t}\n\t}\n#endif /* (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) */\n\n}\n\n#if defined(CONFIG_RTL8822C) && defined(CONFIG_LPS_PG)\nvoid\ndebug_DACK(\n\tstruct dm_struct *dm\n)\n{\n\t//P_PHYDM_FUNC dm;\n\t//dm = &(SysMib.ODM.Phydm);\n\t//PIQK_OFFLOAD_PARM pIQK_info;\n\t//pIQK_info= &(SysMib.ODM.IQKParm);\n\tu8 i;\n\tu32 temp1, temp2, temp3;\n\n\ttemp1 = odm_get_bb_reg(dm, 0x1860, bMaskDWord);\n\ttemp2 = odm_get_bb_reg(dm, 0x4160, bMaskDWord);\n\ttemp3 = odm_get_bb_reg(dm, 0x9b4, bMaskDWord);\n\n\todm_set_bb_reg(dm, 0x9b4, bMaskDWord, 0xdb66db00);\n\n\t//pathA\n\todm_set_bb_reg(dm, 0x1830, BIT(30), 0x0);\n\todm_set_bb_reg(dm, 0x1860, 0xfc000000, 0x3c);\n\n\tRTW_INFO(\"path A i\\n\");\n\t//i\n\tfor (i = 0; i < 0xf; i++) {\n\t\todm_set_bb_reg(dm, 0x18b0, 0xf0000000, i);\n\t\tRTW_INFO(\"[0][0][%d] = 0x%08x\\n\", i, (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000));\n\t\t//pIQK_info->msbk_d[0][0][i] = (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000);\n\t}\n\tRTW_INFO(\"path A q\\n\");\n\t//q\n\tfor (i = 0; i < 0xf; i++) {\n\t\todm_set_bb_reg(dm, 0x18cc, 0xf0000000, i);\n\t\tRTW_INFO(\"[0][1][%d] = 0x%08x\\n\", i, (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000));\n\t\t//pIQK_info->msbk_d[0][1][i] = (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000);\n\t}\n\t//pathB\n\todm_set_bb_reg(dm, 0x4130, BIT(30), 0x0);\n\todm_set_bb_reg(dm, 0x4160, 0xfc000000, 0x3c);\n\n\tRTW_INFO(\"\\npath B i\\n\");\n\t//i\n\tfor (i = 0; i < 0xf; i++) {\n\t\todm_set_bb_reg(dm, 0x41b0, 0xf0000000, i);\n\t\tRTW_INFO(\"[1][0][%d] = 0x%08x\\n\", i, (u16)odm_get_bb_reg(dm,0x4510,0x7fc0000));\n\t\t//pIQK_info->msbk_d[1][0][i] = (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000);\n\t}\n\tRTW_INFO(\"path B q\\n\");\n\t//q\n\tfor (i = 0; i < 0xf; i++) {\n\t\todm_set_bb_reg(dm, 0x41cc, 0xf0000000, i);\n\t\tRTW_INFO(\"[1][1][%d] = 0x%08x\\n\", i, (u16)odm_get_bb_reg(dm,0x453c,0x7fc0000));\n\t\t//pIQK_info->msbk_d[1][1][i] = (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000);\n\t}\n\n\t//restore to normal\n\todm_set_bb_reg(dm, 0x1830, BIT(30), 0x1);\n\todm_set_bb_reg(dm, 0x4130, BIT(30), 0x1);\n\todm_set_bb_reg(dm, 0x1860, bMaskDWord, temp1);\n\todm_set_bb_reg(dm, 0x4160, bMaskDWord, temp2);\n\todm_set_bb_reg(dm, 0x9b4, bMaskDWord, temp3);\n\n\n}\n\nvoid\ndebug_IQK(\n\tstruct dm_struct *dm,\n\tIN\tu8 idx,\n\tIN\tu8 path\n)\n{\n\tu8 i, ch;\n\tu32 tmp;\n\tu32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);\n\n\tRTW_INFO(\"idx = %d, path = %d\\n\", idx, path);\n\n\todm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0x8 | path << 1);\n\n\tif (idx == TX_IQK) {//TXCFIR\n\t\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x3);\n\t} else {//RXCFIR\n\t\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);\t\t\n\t}\n\todm_set_bb_reg(dm, R_0x1bd4, BIT(21), 0x1);\n\todm_set_bb_reg(dm, R_0x1bd4, bit_mask_20_16, 0x10);\n\tfor (i = 0; i <= 16; i++) {\n\t\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001 | i << 2);\n\t\ttmp = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);\n\t\tRTW_INFO(\"iqk_cfir_real[%d][%d][%d] = 0x%x\\n\", path, idx, i, ((tmp & 0x0fff0000) >> 16));\n\t\t//iqk_info->iqk_cfir_real[ch][path][idx][i] =\n\t\t//\t\t\t\t(tmp & 0x0fff0000) >> 16;\n\t\tRTW_INFO(\"iqk_cfir_imag[%d][%d][%d] = 0x%x\\n\", path, idx, i, (tmp & 0x0fff));\n\t\t//iqk_info->iqk_cfir_imag[ch][path][idx][i] = tmp & 0x0fff;\t\t\n\t}\n\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);\n\t//odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);\n}\n\n__odm_func__ void\ndebug_information_8822c(\n\tstruct dm_struct *dm)\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu32  reg_rf18;\n\n\tif (odm_get_bb_reg(dm, R_0x1e7c, BIT(30)))\n\t\tdpk_info->is_tssi_mode = true;\n\telse\n\t\tdpk_info->is_tssi_mode = false;\n\n\treg_rf18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK);\n\n\tdpk_info->dpk_band = (u8)((reg_rf18 & BIT(16)) >> 16); /*0/1:G/A*/\n\tdpk_info->dpk_ch = (u8)reg_rf18 & 0xff;\n\tdpk_info->dpk_bw = (u8)((reg_rf18 & 0x3000) >> 12); /*3/2/1:20/40/80*/\n\n\tRTW_INFO(\"[DPK] TSSI/ Band/ CH/ BW = %d / %s / %d / %s\\n\",\n\t       dpk_info->is_tssi_mode, dpk_info->dpk_band == 0 ? \"2G\" : \"5G\",\n\t       dpk_info->dpk_ch,\n\t       dpk_info->dpk_bw == 3 ? \"20M\" : (dpk_info->dpk_bw == 2 ? \"40M\" : \"80M\"));\n}\n\nextern void _dpk_get_coef_8822c(void *dm_void, u8 path);\n\n__odm_func__ void\ndebug_reload_data_8822c(\n\tvoid *dm_void)\n{\t\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu8 path;\n\tu32 u32tmp;\n\n\tdebug_information_8822c(dm);\n\n\tfor (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {\n\n\t\tRTW_INFO(\"[DPK] Reload path: 0x%x\\n\", path);\n\n\t\todm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | (path << 1));\n\n\t\t /*txagc bnd*/\n\t\tif (dpk_info->dpk_band == 0x0)\n\t\t\tu32tmp = odm_get_bb_reg(dm, R_0x1b60, MASKDWORD);\n\t\telse\n\t\t\tu32tmp = odm_get_bb_reg(dm, R_0x1b60, MASKDWORD);\n\n \t\tRTW_INFO(\"[DPK] txagc bnd = 0x%08x\\n\", u32tmp);\n\n\t\tu32tmp = odm_get_bb_reg(dm, R_0x1b64, MASKBYTE3);\n\t\tRTW_INFO(\"[DPK] dpk_txagc = 0x%08x\\n\", u32tmp);\n\t\t\n\t\t//debug_coef_write_8822c(dm, path, dpk_info->dpk_path_ok & BIT(path) >> path);\n\t\t_dpk_get_coef_8822c(dm, path);\n\n\t\t//debug_one_shot_8822c(dm, path, DPK_ON);\n\n\t\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc);\n\n\t\tif (path == RF_PATH_A)\n\t\t\tu32tmp = odm_get_bb_reg(dm, R_0x1b04, 0x0fffffff);\n\t\telse \n\t\t\tu32tmp = odm_get_bb_reg(dm, R_0x1b5c, 0x0fffffff);\n\n\t\tRTW_INFO(\"[DPK] dpk_gs = 0x%08x\\n\", u32tmp);\n\t\t\n\t}\n}\n\nvoid odm_lps_pg_debug_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tdebug_DACK(dm);\n\tdebug_IQK(dm, TX_IQK, RF_PATH_A);\n\tdebug_IQK(dm, RX_IQK, RF_PATH_A);\n\tdebug_IQK(dm, TX_IQK, RF_PATH_B);\n\tdebug_IQK(dm, RX_IQK, RF_PATH_B);\t\n\tdebug_reload_data_8822c(dm);\n}\n#endif /* defined(CONFIG_RTL8822C) && defined(CONFIG_LPS_PG) */\n\n"
  },
  {
    "path": "core/rtw_p2p.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_P2P_C_\n\n#include <drv_types.h>\n\n#ifdef CONFIG_P2P\n\nint rtw_p2p_is_channel_list_ok(u8 desired_ch, u8 *ch_list, u8 ch_cnt)\n{\n\tint found = 0, i = 0;\n\n\tfor (i = 0; i < ch_cnt; i++) {\n\t\tif (ch_list[i] == desired_ch) {\n\t\t\tfound = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn found ;\n}\n\nint is_any_client_associated(_adapter *padapter)\n{\n\treturn padapter->stapriv.asoc_list_cnt ? _TRUE : _FALSE;\n}\n\nstatic u32 go_add_group_info_attr(struct wifidirect_info *pwdinfo, u8 *pbuf)\n{\n\t_irqL irqL;\n\t_list\t*phead, *plist;\n\tu32 len = 0;\n\tu16 attr_len = 0;\n\tu8 tmplen, *pdata_attr, *pstart, *pcur;\n\tstruct sta_info *psta = NULL;\n\t_adapter *padapter = pwdinfo->padapter;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n\n\tpdata_attr = rtw_zmalloc(MAX_P2P_IE_LEN);\n\n\tif (NULL == pdata_attr) {\n\t\tRTW_INFO(\"%s pdata_attr malloc failed\\n\", __FUNCTION__);\n\t\tgoto _exit;\n\t}\n\n\tpstart = pdata_attr;\n\tpcur = pdata_attr;\n\n\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\tphead = &pstapriv->asoc_list;\n\tplist = get_next(phead);\n\n\t/* look up sta asoc_queue */\n\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);\n\n\t\tplist = get_next(plist);\n\n\n\t\tif (psta->is_p2p_device) {\n\t\t\ttmplen = 0;\n\n\t\t\tpcur++;\n\n\t\t\t/* P2P device address */\n\t\t\t_rtw_memcpy(pcur, psta->dev_addr, ETH_ALEN);\n\t\t\tpcur += ETH_ALEN;\n\n\t\t\t/* P2P interface address */\n\t\t\t_rtw_memcpy(pcur, psta->cmn.mac_addr, ETH_ALEN);\n\t\t\tpcur += ETH_ALEN;\n\n\t\t\t*pcur = psta->dev_cap;\n\t\t\tpcur++;\n\n\t\t\t/* *(u16*)(pcur) = cpu_to_be16(psta->config_methods); */\n\t\t\tRTW_PUT_BE16(pcur, psta->config_methods);\n\t\t\tpcur += 2;\n\n\t\t\t_rtw_memcpy(pcur, psta->primary_dev_type, 8);\n\t\t\tpcur += 8;\n\n\t\t\t*pcur = psta->num_of_secdev_type;\n\t\t\tpcur++;\n\n\t\t\t_rtw_memcpy(pcur, psta->secdev_types_list, psta->num_of_secdev_type * 8);\n\t\t\tpcur += psta->num_of_secdev_type * 8;\n\n\t\t\tif (psta->dev_name_len > 0) {\n\t\t\t\t/* *(u16*)(pcur) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */\n\t\t\t\tRTW_PUT_BE16(pcur, WPS_ATTR_DEVICE_NAME);\n\t\t\t\tpcur += 2;\n\n\t\t\t\t/* *(u16*)(pcur) = cpu_to_be16( psta->dev_name_len ); */\n\t\t\t\tRTW_PUT_BE16(pcur, psta->dev_name_len);\n\t\t\t\tpcur += 2;\n\n\t\t\t\t_rtw_memcpy(pcur, psta->dev_name, psta->dev_name_len);\n\t\t\t\tpcur += psta->dev_name_len;\n\t\t\t}\n\n\n\t\t\ttmplen = (u8)(pcur - pstart);\n\n\t\t\t*pstart = (tmplen - 1);\n\n\t\t\tattr_len += tmplen;\n\n\t\t\t/* pstart += tmplen; */\n\t\t\tpstart = pcur;\n\n\t\t}\n\n\n\t}\n\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\tif (attr_len > 0)\n\t\tlen = rtw_set_p2p_attr_content(pbuf, P2P_ATTR_GROUP_INFO, attr_len, pdata_attr);\n\n\trtw_mfree(pdata_attr, MAX_P2P_IE_LEN);\n\n_exit:\n\treturn len;\n\n}\n\nstatic void issue_group_disc_req(struct wifidirect_info *pwdinfo, u8 *da)\n{\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\t_adapter *padapter = pwdinfo->padapter;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tunsigned char category = RTW_WLAN_CATEGORY_P2P;/* P2P action frame\t */\n\tu32\tp2poui = cpu_to_be32(P2POUI);\n\tu8\toui_subtype = P2P_GO_DISC_REQUEST;\n\tu8\tdialogToken = 0;\n\n\tRTW_INFO(\"[%s]\\n\", __FUNCTION__);\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\t/* Build P2P action frame header */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));\n\n\t/* there is no IE in this P2P action frame */\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(padapter, pmgntframe);\n\n}\n\nstatic void issue_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken)\n{\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\t_adapter *padapter = pwdinfo->padapter;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tunsigned char category = RTW_WLAN_CATEGORY_PUBLIC;\n\tu8\t\t\taction = P2P_PUB_ACTION_ACTION;\n\tu32\t\t\tp2poui = cpu_to_be32(P2POUI);\n\tu8\t\t\toui_subtype = P2P_DEVDISC_RESP;\n\tu8 p2pie[8] = { 0x00 };\n\tu32 p2pielen = 0;\n\n\tRTW_INFO(\"[%s]\\n\", __FUNCTION__);\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, pwdinfo->device_addr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, pwdinfo->device_addr, ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\t/* Build P2P public action frame header */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));\n\n\n\t/* Build P2P IE */\n\t/*\tP2P OUI */\n\tp2pielen = 0;\n\tp2pie[p2pielen++] = 0x50;\n\tp2pie[p2pielen++] = 0x6F;\n\tp2pie[p2pielen++] = 0x9A;\n\tp2pie[p2pielen++] = 0x09;\t/*\tWFA P2P v1.0 */\n\n\t/* P2P_ATTR_STATUS */\n\tp2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status);\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &pattrib->pktlen);\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(padapter, pmgntframe);\n\n}\n\nstatic void issue_p2p_provision_resp(struct wifidirect_info *pwdinfo, u8 *raddr, u8 *frame_body, u16 config_method)\n{\n\t_adapter *padapter = pwdinfo->padapter;\n\tunsigned char category = RTW_WLAN_CATEGORY_PUBLIC;\n\tu8\t\t\taction = P2P_PUB_ACTION_ACTION;\n\tu8\t\t\tdialogToken = frame_body[7];\t/*\tThe Dialog Token of provisioning discovery request frame. */\n\tu32\t\t\tp2poui = cpu_to_be32(P2POUI);\n\tu8\t\t\toui_subtype = P2P_PROVISION_DISC_RESP;\n\tu8\t\t\twpsie[100] = { 0x00 };\n\tu8\t\t\twpsielen = 0;\n#ifdef CONFIG_WFD\n\tu32\t\t\t\t\twfdielen = 0;\n#endif\n\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));\n\n\twpsielen = 0;\n\t/*\tWPS OUI */\n\t/* *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); */\n\tRTW_PUT_BE32(wpsie, WPSOUI);\n\twpsielen += 4;\n\n#if 0\n\t/*\tWPS version */\n\t/*\tType: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);\n\twpsielen += 2;\n\n\t/*\tLength: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);\n\twpsielen += 2;\n\n\t/*\tValue: */\n\twpsie[wpsielen++] = WPS_VERSION_1;\t/*\tVersion 1.0 */\n#endif\n\n\t/*\tConfig Method */\n\t/*\tType: */\n\t/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); */\n\tRTW_PUT_BE16(wpsie + wpsielen, WPS_ATTR_CONF_METHOD);\n\twpsielen += 2;\n\n\t/*\tLength: */\n\t/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); */\n\tRTW_PUT_BE16(wpsie + wpsielen, 0x0002);\n\twpsielen += 2;\n\n\t/*\tValue: */\n\t/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( config_method ); */\n\tRTW_PUT_BE16(wpsie + wpsielen, config_method);\n\twpsielen += 2;\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);\n\n#ifdef CONFIG_WFD\n\twfdielen = build_provdisc_resp_wfd_ie(pwdinfo, pframe);\n\tpframe += wfdielen;\n\tpattrib->pktlen += wfdielen;\n#endif\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(padapter, pmgntframe);\n\n\treturn;\n\n}\n\nstatic void issue_p2p_presence_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken)\n{\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\t_adapter *padapter = pwdinfo->padapter;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tunsigned char category = RTW_WLAN_CATEGORY_P2P;/* P2P action frame\t */\n\tu32\tp2poui = cpu_to_be32(P2POUI);\n\tu8\toui_subtype = P2P_PRESENCE_RESPONSE;\n\tu8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };\n\tu8 noa_attr_content[32] = { 0x00 };\n\tu32 p2pielen = 0;\n\n\tRTW_INFO(\"[%s]\\n\", __FUNCTION__);\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\t/* Build P2P action frame header */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));\n\n\n\t/* Add P2P IE header */\n\t/*\tP2P OUI */\n\tp2pielen = 0;\n\tp2pie[p2pielen++] = 0x50;\n\tp2pie[p2pielen++] = 0x6F;\n\tp2pie[p2pielen++] = 0x9A;\n\tp2pie[p2pielen++] = 0x09;\t/*\tWFA P2P v1.0 */\n\n\t/* Add Status attribute in P2P IE */\n\tp2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status);\n\n\t/* Add NoA attribute in P2P IE */\n\tnoa_attr_content[0] = 0x1;/* index */\n\tnoa_attr_content[1] = 0x0;/* CTWindow and OppPS Parameters */\n\n\t/* todo: Notice of Absence Descriptor(s) */\n\n\tp2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_NOA, 2, noa_attr_content);\n\n\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &(pattrib->pktlen));\n\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(padapter, pmgntframe);\n\n}\n\nu32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)\n{\n\tu8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };\n\tu16 capability = 0;\n\tu32 len = 0, p2pielen = 0;\n\n\n\t/*\tP2P OUI */\n\tp2pielen = 0;\n\tp2pie[p2pielen++] = 0x50;\n\tp2pie[p2pielen++] = 0x6F;\n\tp2pie[p2pielen++] = 0x9A;\n\tp2pie[p2pielen++] = 0x09;\t/*\tWFA P2P v1.0 */\n\n\n\t/*\tAccording to the P2P Specification, the beacon frame should contain 3 P2P attributes */\n\t/*\t1. P2P Capability */\n\t/*\t2. P2P Device ID */\n\t/*\t3. Notice of Absence ( NOA )\t */\n\n\t/*\tP2P Capability ATTR */\n\t/*\tType: */\n\t/*\tLength: */\n\t/*\tValue: */\n\t/*\tDevice Capability Bitmap, 1 byte */\n\t/*\tBe able to participate in additional P2P Groups and */\n\t/*\tsupport the P2P Invitation Procedure\t */\n\t/*\tGroup Capability Bitmap, 1 byte\t */\n\tcapability = P2P_DEVCAP_INVITATION_PROC | P2P_DEVCAP_CLIENT_DISCOVERABILITY;\n\tcapability |= ((P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS) << 8);\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))\n\t\tcapability |= (P2P_GRPCAP_GROUP_FORMATION << 8);\n\n\tcapability = cpu_to_le16(capability);\n\n\tp2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_CAPABILITY, 2, (u8 *)&capability);\n\n\n\t/* P2P Device ID ATTR */\n\tp2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_DEVICE_ID, ETH_ALEN, pwdinfo->device_addr);\n\n\n\t/* Notice of Absence ATTR */\n\t/*\tType:  */\n\t/*\tLength: */\n\t/*\tValue: */\n\n\t/* go_add_noa_attr(pwdinfo); */\n\n\n\tpbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);\n\n\n\treturn len;\n\n}\n\n#ifdef CONFIG_WFD\nu32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)\n{\n\tu8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };\n\tu16 val16 = 0;\n\tu32 len = 0, wfdielen = 0;\n\t_adapter *padapter = pwdinfo->padapter;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wifi_display_info\t*pwfd_info = padapter->wdinfo.wfd_info;\n\n\tif (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))\n\t\tgoto exit;\n\n\t/*\tWFD OUI */\n\twfdielen = 0;\n\twfdie[wfdielen++] = 0x50;\n\twfdie[wfdielen++] = 0x6F;\n\twfdie[wfdielen++] = 0x9A;\n\twfdie[wfdielen++] = 0x0A;\t/*\tWFA WFD v1.0 */\n\n\t/*\tCommented by Albert 20110812 */\n\t/*\tAccording to the WFD Specification, the beacon frame should contain 4 WFD attributes */\n\t/*\t1. WFD Device Information */\n\t/*\t2. Associated BSSID */\n\t/*\t3. Coupled Sink Information */\n\n\n\t/*\tWFD Device Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue1: */\n\t/*\tWFD device information */\n\n\tif (P2P_ROLE_GO == pwdinfo->role) {\n\t\tif (is_any_client_associated(pwdinfo->padapter)) {\n\t\t\t/*\tWFD primary sink + WiFi Direct mode + WSD (WFD Service Discovery) */\n\t\t\tval16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD;\n\t\t\tRTW_PUT_BE16(wfdie + wfdielen, val16);\n\t\t} else {\n\t\t\t/*\tWFD primary sink + available for WFD session + WiFi Direct mode + WSD (WFD Service Discovery) */\n\t\t\tval16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;\n\t\t\tRTW_PUT_BE16(wfdie + wfdielen, val16);\n\t\t}\n\n\t} else {\n\t\t/*\tWFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */\n\t\tval16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;\n\t\tRTW_PUT_BE16(wfdie + wfdielen, val16);\n\t}\n\n\twfdielen += 2;\n\n\t/*\tValue2: */\n\t/*\tSession Management Control Port */\n\t/*\tDefault TCP port for RTSP messages is 554 */\n\tRTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);\n\twfdielen += 2;\n\n\t/*\tValue3: */\n\t/*\tWFD Device Maximum Throughput */\n\t/*\t300Mbps is the maximum throughput */\n\tRTW_PUT_BE16(wfdie + wfdielen, 300);\n\twfdielen += 2;\n\n\t/*\tAssociated BSSID ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tAssociated BSSID */\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);\n\telse\n\t\t_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);\n\n\twfdielen += ETH_ALEN;\n\n\t/*\tCoupled Sink Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0007);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tCoupled Sink Status bitmap */\n\t/*\tNot coupled/available for Coupling */\n\twfdie[wfdielen++] = 0;\n\t/* MAC Addr. */\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\n\trtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);\n\nexit:\n\treturn len;\n}\n\nu32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)\n{\n\tu8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };\n\tu16 val16 = 0;\n\tu32 len = 0, wfdielen = 0;\n\t_adapter *padapter = pwdinfo->padapter;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wifi_display_info\t*pwfd_info = padapter->wdinfo.wfd_info;\n\n\tif (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))\n\t\tgoto exit;\n\n\t/*\tWFD OUI */\n\twfdielen = 0;\n\twfdie[wfdielen++] = 0x50;\n\twfdie[wfdielen++] = 0x6F;\n\twfdie[wfdielen++] = 0x9A;\n\twfdie[wfdielen++] = 0x0A;\t/*\tWFA WFD v1.0 */\n\n\t/*\tCommented by Albert 20110812 */\n\t/*\tAccording to the WFD Specification, the probe request frame should contain 4 WFD attributes */\n\t/*\t1. WFD Device Information */\n\t/*\t2. Associated BSSID */\n\t/*\t3. Coupled Sink Information */\n\n\n\t/*\tWFD Device Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue1: */\n\t/*\tWFD device information */\n\n\tif (1 == pwdinfo->wfd_tdls_enable) {\n\t\t/*\tWFD primary sink + available for WFD session + WiFi TDLS mode + WSC ( WFD Service Discovery )\t */\n\t\tval16 = pwfd_info->wfd_device_type |\n\t\t\tWFD_DEVINFO_SESSION_AVAIL |\n\t\t\tWFD_DEVINFO_WSD |\n\t\t\tWFD_DEVINFO_PC_TDLS;\n\t\tRTW_PUT_BE16(wfdie + wfdielen, val16);\n\t} else {\n\t\t/*\tWFD primary sink + available for WFD session + WiFi Direct mode + WSC ( WFD Service Discovery )\t */\n\t\tval16 = pwfd_info->wfd_device_type |\n\t\t\tWFD_DEVINFO_SESSION_AVAIL |\n\t\t\tWFD_DEVINFO_WSD;\n\t\tRTW_PUT_BE16(wfdie + wfdielen, val16);\n\t}\n\n\twfdielen += 2;\n\n\t/*\tValue2: */\n\t/*\tSession Management Control Port */\n\t/*\tDefault TCP port for RTSP messages is 554 */\n\tRTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);\n\twfdielen += 2;\n\n\t/*\tValue3: */\n\t/*\tWFD Device Maximum Throughput */\n\t/*\t300Mbps is the maximum throughput */\n\tRTW_PUT_BE16(wfdie + wfdielen, 300);\n\twfdielen += 2;\n\n\t/*\tAssociated BSSID ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tAssociated BSSID */\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);\n\telse\n\t\t_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);\n\n\twfdielen += ETH_ALEN;\n\n\t/*\tCoupled Sink Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0007);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tCoupled Sink Status bitmap */\n\t/*\tNot coupled/available for Coupling */\n\twfdie[wfdielen++] = 0;\n\t/* MAC Addr. */\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\n\trtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);\n\nexit:\n\treturn len;\n}\n\nu32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled)\n{\n\tu8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };\n\tu32 len = 0, wfdielen = 0;\n\t_adapter *padapter = pwdinfo->padapter;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wifi_display_info\t*pwfd_info = padapter->wdinfo.wfd_info;\n\tu16 v16 = 0;\n\n\tif (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))\n\t\tgoto exit;\n\n\t/*\tWFD OUI */\n\twfdielen = 0;\n\twfdie[wfdielen++] = 0x50;\n\twfdie[wfdielen++] = 0x6F;\n\twfdie[wfdielen++] = 0x9A;\n\twfdie[wfdielen++] = 0x0A;\t/*\tWFA WFD v1.0 */\n\n\t/*\tCommented by Albert 20110812 */\n\t/*\tAccording to the WFD Specification, the probe response frame should contain 4 WFD attributes */\n\t/*\t1. WFD Device Information */\n\t/*\t2. Associated BSSID */\n\t/*\t3. Coupled Sink Information */\n\t/*\t4. WFD Session Information */\n\n\n\t/*\tWFD Device Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue1: */\n\t/*\tWFD device information */\n\t/*\tWFD primary sink + available for WFD session + WiFi Direct mode */\n\n\tif (_TRUE == pwdinfo->session_available) {\n\t\tif (P2P_ROLE_GO == pwdinfo->role) {\n\t\t\tif (is_any_client_associated(pwdinfo->padapter)) {\n\t\t\t\tif (pwdinfo->wfd_tdls_enable) {\n\t\t\t\t\t/*\tTDLS mode + WSD ( WFD Service Discovery ) */\n\t\t\t\t\tv16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;\n\t\t\t\t\tRTW_PUT_BE16(wfdie + wfdielen, v16);\n\t\t\t\t} else {\n\t\t\t\t\t/*\tWiFi Direct mode + WSD ( WFD Service Discovery ) */\n\t\t\t\t\tv16 =  pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;\n\t\t\t\t\tRTW_PUT_BE16(wfdie + wfdielen, v16);\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif (pwdinfo->wfd_tdls_enable) {\n\t\t\t\t\t/*\tavailable for WFD session + TDLS mode + WSD ( WFD Service Discovery ) */\n\t\t\t\t\tv16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;\n\t\t\t\t\tRTW_PUT_BE16(wfdie + wfdielen, v16);\n\t\t\t\t} else {\n\t\t\t\t\t/*\tavailable for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */\n\t\t\t\t\tv16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;\n\t\t\t\t\tRTW_PUT_BE16(wfdie + wfdielen, v16);\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tif (pwdinfo->wfd_tdls_enable) {\n\t\t\t\t/*\tavailable for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */\n\t\t\t\tv16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;\n\t\t\t\tRTW_PUT_BE16(wfdie + wfdielen, v16);\n\t\t\t} else {\n\t\t\t\t/*\tavailable for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */\n\t\t\t\tv16 =  pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;\n\t\t\t\tRTW_PUT_BE16(wfdie + wfdielen, v16);\n\t\t\t}\n\t\t}\n\t} else {\n\t\tif (pwdinfo->wfd_tdls_enable) {\n\t\t\tv16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;\n\t\t\tRTW_PUT_BE16(wfdie + wfdielen, v16);\n\t\t} else {\n\t\t\tv16 =  pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;\n\t\t\tRTW_PUT_BE16(wfdie + wfdielen, v16);\n\t\t}\n\t}\n\n\twfdielen += 2;\n\n\t/*\tValue2: */\n\t/*\tSession Management Control Port */\n\t/*\tDefault TCP port for RTSP messages is 554 */\n\tRTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);\n\twfdielen += 2;\n\n\t/*\tValue3: */\n\t/*\tWFD Device Maximum Throughput */\n\t/*\t300Mbps is the maximum throughput */\n\tRTW_PUT_BE16(wfdie + wfdielen, 300);\n\twfdielen += 2;\n\n\t/*\tAssociated BSSID ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tAssociated BSSID */\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);\n\telse\n\t\t_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);\n\n\twfdielen += ETH_ALEN;\n\n\t/*\tCoupled Sink Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0007);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tCoupled Sink Status bitmap */\n\t/*\tNot coupled/available for Coupling */\n\twfdie[wfdielen++] = 0;\n\t/* MAC Addr. */\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\t/*\tWFD Session Information ATTR */\n\t\t/*\tType: */\n\t\twfdie[wfdielen++] = WFD_ATTR_SESSION_INFO;\n\n\t\t/*\tLength: */\n\t\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\t\tRTW_PUT_BE16(wfdie + wfdielen, 0x0000);\n\t\twfdielen += 2;\n\n\t\t/*\tTodo: to add the list of WFD device info descriptor in WFD group. */\n\n\t}\n#ifdef CONFIG_CONCURRENT_MODE\n#ifdef CONFIG_TDLS\n\t{\n\t\tint i;\n\t\t_adapter *iface = NULL;\n\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tif ((iface) && rtw_is_adapter_up(iface)) {\n\t\t\t\tif (iface == padapter)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif ((tunneled == 0) && (iface->wdinfo.wfd_tdls_enable == 1)) {\n\t\t\t\t\t/*\tAlternative MAC Address ATTR\n\t\t\t\t\t\tType:\t\t\t\t\t*/\n\t\t\t\t\twfdie[wfdielen++] = WFD_ATTR_ALTER_MAC;\n\n\t\t\t\t\t/*\tLength:\n\t\t\t\t\t\tNote: In the WFD specification, the size of length field is 2.*/\n\t\t\t\t\tRTW_PUT_BE16(wfdie + wfdielen,  ETH_ALEN);\n\t\t\t\t\twfdielen += 2;\n\n\t\t\t\t\t/*\tValue:\n\t\t\t\t\t\tAlternative MAC Address*/\n\t\t\t\t\t_rtw_memcpy(wfdie + wfdielen, adapter_mac_addr(iface), ETH_ALEN);\n\t\t\t\t\twfdielen += ETH_ALEN;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n#endif /* CONFIG_TDLS*/\n#endif /* CONFIG_CONCURRENT_MODE */\n\n\tpbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);\n\nexit:\n\treturn len;\n}\n\nu32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)\n{\n\tu8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };\n\tu16 val16 = 0;\n\tu32 len = 0, wfdielen = 0;\n\t_adapter\t\t\t\t\t*padapter = NULL;\n\tstruct mlme_priv\t\t\t*pmlmepriv = NULL;\n\tstruct wifi_display_info\t\t*pwfd_info = NULL;\n\n\tpadapter = pwdinfo->padapter;\n\tpmlmepriv = &padapter->mlmepriv;\n\tpwfd_info = padapter->wdinfo.wfd_info;\n\n\tif (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))\n\t\tgoto exit;\n\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE))\n\t\tgoto exit;\n\n\t/* WFD OUI */\n\twfdielen = 0;\n\twfdie[wfdielen++] = 0x50;\n\twfdie[wfdielen++] = 0x6F;\n\twfdie[wfdielen++] = 0x9A;\n\twfdie[wfdielen++] = 0x0A;\t/*\tWFA WFD v1.0 */\n\n\t/*\tCommented by Albert 20110812 */\n\t/*\tAccording to the WFD Specification, the probe request frame should contain 4 WFD attributes */\n\t/*\t1. WFD Device Information */\n\t/*\t2. Associated BSSID */\n\t/*\t3. Coupled Sink Information */\n\n\n\t/*\tWFD Device Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue1: */\n\t/*\tWFD device information */\n\t/*\tWFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */\n\tval16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;\n\tRTW_PUT_BE16(wfdie + wfdielen, val16);\n\twfdielen += 2;\n\n\t/*\tValue2: */\n\t/*\tSession Management Control Port */\n\t/*\tDefault TCP port for RTSP messages is 554 */\n\tRTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);\n\twfdielen += 2;\n\n\t/*\tValue3: */\n\t/*\tWFD Device Maximum Throughput */\n\t/*\t300Mbps is the maximum throughput */\n\tRTW_PUT_BE16(wfdie + wfdielen, 300);\n\twfdielen += 2;\n\n\t/*\tAssociated BSSID ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tAssociated BSSID */\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);\n\telse\n\t\t_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);\n\n\twfdielen += ETH_ALEN;\n\n\t/*\tCoupled Sink Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0007);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tCoupled Sink Status bitmap */\n\t/*\tNot coupled/available for Coupling */\n\twfdie[wfdielen++] = 0;\n\t/* MAC Addr. */\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\n\trtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);\n\nexit:\n\treturn len;\n}\n\nu32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)\n{\n\tu8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };\n\tu32 len = 0, wfdielen = 0;\n\tu16 val16 = 0;\n\t_adapter *padapter = pwdinfo->padapter;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wifi_display_info\t*pwfd_info = padapter->wdinfo.wfd_info;\n\n\tif (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))\n\t\tgoto exit;\n\n\t/*\tWFD OUI */\n\twfdielen = 0;\n\twfdie[wfdielen++] = 0x50;\n\twfdie[wfdielen++] = 0x6F;\n\twfdie[wfdielen++] = 0x9A;\n\twfdie[wfdielen++] = 0x0A;\t/*\tWFA WFD v1.0 */\n\n\t/*\tCommented by Albert 20110812 */\n\t/*\tAccording to the WFD Specification, the probe request frame should contain 4 WFD attributes */\n\t/*\t1. WFD Device Information */\n\t/*\t2. Associated BSSID */\n\t/*\t3. Coupled Sink Information */\n\n\n\t/*\tWFD Device Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue1: */\n\t/*\tWFD device information */\n\t/*\tWFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */\n\tval16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;\n\tRTW_PUT_BE16(wfdie + wfdielen, val16);\n\twfdielen += 2;\n\n\t/*\tValue2: */\n\t/*\tSession Management Control Port */\n\t/*\tDefault TCP port for RTSP messages is 554 */\n\tRTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);\n\twfdielen += 2;\n\n\t/*\tValue3: */\n\t/*\tWFD Device Maximum Throughput */\n\t/*\t300Mbps is the maximum throughput */\n\tRTW_PUT_BE16(wfdie + wfdielen, 300);\n\twfdielen += 2;\n\n\t/*\tAssociated BSSID ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tAssociated BSSID */\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);\n\telse\n\t\t_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);\n\n\twfdielen += ETH_ALEN;\n\n\t/*\tCoupled Sink Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0007);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tCoupled Sink Status bitmap */\n\t/*\tNot coupled/available for Coupling */\n\twfdie[wfdielen++] = 0;\n\t/* MAC Addr. */\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\n\trtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);\n\nexit:\n\treturn len;\n}\n\nu32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)\n{\n\tu8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };\n\tu32 len = 0, wfdielen = 0;\n\tu16 val16 = 0;\n\t_adapter *padapter = pwdinfo->padapter;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wifi_display_info\t*pwfd_info = padapter->wdinfo.wfd_info;\n\n\tif (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))\n\t\tgoto exit;\n\n\t/*\tWFD OUI */\n\twfdielen = 0;\n\twfdie[wfdielen++] = 0x50;\n\twfdie[wfdielen++] = 0x6F;\n\twfdie[wfdielen++] = 0x9A;\n\twfdie[wfdielen++] = 0x0A;\t/*\tWFA WFD v1.0 */\n\n\t/*\tCommented by Albert 20110825 */\n\t/*\tAccording to the WFD Specification, the negotiation request frame should contain 3 WFD attributes */\n\t/*\t1. WFD Device Information */\n\t/*\t2. Associated BSSID ( Optional ) */\n\t/*\t3. Local IP Adress ( Optional ) */\n\n\n\t/*\tWFD Device Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue1: */\n\t/*\tWFD device information */\n\t/*\tWFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available */\n\tval16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL;\n\tRTW_PUT_BE16(wfdie + wfdielen, val16);\n\twfdielen += 2;\n\n\t/*\tValue2: */\n\t/*\tSession Management Control Port */\n\t/*\tDefault TCP port for RTSP messages is 554 */\n\tRTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);\n\twfdielen += 2;\n\n\t/*\tValue3: */\n\t/*\tWFD Device Maximum Throughput */\n\t/*\t300Mbps is the maximum throughput */\n\tRTW_PUT_BE16(wfdie + wfdielen, 300);\n\twfdielen += 2;\n\n\t/*\tAssociated BSSID ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tAssociated BSSID */\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);\n\telse\n\t\t_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);\n\n\twfdielen += ETH_ALEN;\n\n\t/*\tCoupled Sink Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0007);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tCoupled Sink Status bitmap */\n\t/*\tNot coupled/available for Coupling */\n\twfdie[wfdielen++] = 0;\n\t/* MAC Addr. */\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\n\trtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);\n\nexit:\n\treturn len;\n}\n\nu32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)\n{\n\tu8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };\n\tu32 len = 0, wfdielen = 0;\n\tu16 val16 = 0;\n\t_adapter *padapter = pwdinfo->padapter;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wifi_display_info\t*pwfd_info = padapter->wdinfo.wfd_info;\n\n\tif (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))\n\t\tgoto exit;\n\n\t/*\tWFD OUI */\n\twfdielen = 0;\n\twfdie[wfdielen++] = 0x50;\n\twfdie[wfdielen++] = 0x6F;\n\twfdie[wfdielen++] = 0x9A;\n\twfdie[wfdielen++] = 0x0A;\t/*\tWFA WFD v1.0 */\n\n\t/*\tCommented by Albert 20110825 */\n\t/*\tAccording to the WFD Specification, the negotiation request frame should contain 3 WFD attributes */\n\t/*\t1. WFD Device Information */\n\t/*\t2. Associated BSSID ( Optional ) */\n\t/*\t3. Local IP Adress ( Optional ) */\n\n\n\t/*\tWFD Device Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue1: */\n\t/*\tWFD device information */\n\t/*\tWFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available */\n\tval16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL;\n\tRTW_PUT_BE16(wfdie + wfdielen, val16);\n\twfdielen += 2;\n\n\t/*\tValue2: */\n\t/*\tSession Management Control Port */\n\t/*\tDefault TCP port for RTSP messages is 554 */\n\tRTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);\n\twfdielen += 2;\n\n\t/*\tValue3: */\n\t/*\tWFD Device Maximum Throughput */\n\t/*\t300Mbps is the maximum throughput */\n\tRTW_PUT_BE16(wfdie + wfdielen, 300);\n\twfdielen += 2;\n\n\t/*\tAssociated BSSID ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tAssociated BSSID */\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);\n\telse\n\t\t_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);\n\n\twfdielen += ETH_ALEN;\n\n\t/*\tCoupled Sink Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0007);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tCoupled Sink Status bitmap */\n\t/*\tNot coupled/available for Coupling */\n\twfdie[wfdielen++] = 0;\n\t/* MAC Addr. */\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\n\n\trtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);\n\nexit:\n\treturn len;\n}\n\nu32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)\n{\n\tu8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };\n\tu32 len = 0, wfdielen = 0;\n\tu16 val16 = 0;\n\t_adapter *padapter = pwdinfo->padapter;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wifi_display_info\t*pwfd_info = padapter->wdinfo.wfd_info;\n\n\tif (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))\n\t\tgoto exit;\n\n\t/*\tWFD OUI */\n\twfdielen = 0;\n\twfdie[wfdielen++] = 0x50;\n\twfdie[wfdielen++] = 0x6F;\n\twfdie[wfdielen++] = 0x9A;\n\twfdie[wfdielen++] = 0x0A;\t/*\tWFA WFD v1.0 */\n\n\t/*\tCommented by Albert 20110825 */\n\t/*\tAccording to the WFD Specification, the negotiation request frame should contain 3 WFD attributes */\n\t/*\t1. WFD Device Information */\n\t/*\t2. Associated BSSID ( Optional ) */\n\t/*\t3. Local IP Adress ( Optional ) */\n\n\n\t/*\tWFD Device Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue1: */\n\t/*\tWFD device information */\n\t/*\tWFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available */\n\tval16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL;\n\tRTW_PUT_BE16(wfdie + wfdielen, val16);\n\twfdielen += 2;\n\n\t/*\tValue2: */\n\t/*\tSession Management Control Port */\n\t/*\tDefault TCP port for RTSP messages is 554 */\n\tRTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);\n\twfdielen += 2;\n\n\t/*\tValue3: */\n\t/*\tWFD Device Maximum Throughput */\n\t/*\t300Mbps is the maximum throughput */\n\tRTW_PUT_BE16(wfdie + wfdielen, 300);\n\twfdielen += 2;\n\n\t/*\tAssociated BSSID ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tAssociated BSSID */\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);\n\telse\n\t\t_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);\n\n\twfdielen += ETH_ALEN;\n\n\t/*\tCoupled Sink Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0007);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tCoupled Sink Status bitmap */\n\t/*\tNot coupled/available for Coupling */\n\twfdie[wfdielen++] = 0;\n\t/* MAC Addr. */\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\n\n\tpbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);\n\nexit:\n\treturn len;\n}\n\nu32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)\n{\n\tu8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };\n\tu32 len = 0, wfdielen = 0;\n\tu16 val16 = 0;\n\t_adapter *padapter = pwdinfo->padapter;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wifi_display_info\t*pwfd_info = padapter->wdinfo.wfd_info;\n\n\tif (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))\n\t\tgoto exit;\n\n\t/*\tWFD OUI */\n\twfdielen = 0;\n\twfdie[wfdielen++] = 0x50;\n\twfdie[wfdielen++] = 0x6F;\n\twfdie[wfdielen++] = 0x9A;\n\twfdie[wfdielen++] = 0x0A;\t/*\tWFA WFD v1.0 */\n\n\t/*\tCommented by Albert 20110825 */\n\t/*\tAccording to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes */\n\t/*\t1. WFD Device Information */\n\t/*\t2. Associated BSSID ( Optional ) */\n\t/*\t3. Local IP Adress ( Optional ) */\n\n\n\t/*\tWFD Device Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue1: */\n\t/*\tWFD device information */\n\t/*\tWFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */\n\tval16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;\n\tRTW_PUT_BE16(wfdie + wfdielen, val16);\n\twfdielen += 2;\n\n\t/*\tValue2: */\n\t/*\tSession Management Control Port */\n\t/*\tDefault TCP port for RTSP messages is 554 */\n\tRTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);\n\twfdielen += 2;\n\n\t/*\tValue3: */\n\t/*\tWFD Device Maximum Throughput */\n\t/*\t300Mbps is the maximum throughput */\n\tRTW_PUT_BE16(wfdie + wfdielen, 300);\n\twfdielen += 2;\n\n\t/*\tAssociated BSSID ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tAssociated BSSID */\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);\n\telse\n\t\t_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);\n\n\twfdielen += ETH_ALEN;\n\n\t/*\tCoupled Sink Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0007);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tCoupled Sink Status bitmap */\n\t/*\tNot coupled/available for Coupling */\n\twfdie[wfdielen++] = 0;\n\t/* MAC Addr. */\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\n\tif (P2P_ROLE_GO == pwdinfo->role) {\n\t\t/*\tWFD Session Information ATTR */\n\t\t/*\tType: */\n\t\twfdie[wfdielen++] = WFD_ATTR_SESSION_INFO;\n\n\t\t/*\tLength: */\n\t\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\t\tRTW_PUT_BE16(wfdie + wfdielen, 0x0000);\n\t\twfdielen += 2;\n\n\t\t/*\tTodo: to add the list of WFD device info descriptor in WFD group. */\n\n\t}\n\n\trtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);\n\nexit:\n\treturn len;\n}\n\nu32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)\n{\n\tu8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };\n\tu16 val16 = 0;\n\tu32 len = 0, wfdielen = 0;\n\t_adapter *padapter = pwdinfo->padapter;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wifi_display_info\t*pwfd_info = padapter->wdinfo.wfd_info;\n\n\tif (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))\n\t\tgoto exit;\n\n\t/*\tWFD OUI */\n\twfdielen = 0;\n\twfdie[wfdielen++] = 0x50;\n\twfdie[wfdielen++] = 0x6F;\n\twfdie[wfdielen++] = 0x9A;\n\twfdie[wfdielen++] = 0x0A;\t/*\tWFA WFD v1.0 */\n\n\t/*\tCommented by Albert 20110825 */\n\t/*\tAccording to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes */\n\t/*\t1. WFD Device Information */\n\t/*\t2. Associated BSSID ( Optional ) */\n\t/*\t3. Local IP Adress ( Optional ) */\n\n\n\t/*\tWFD Device Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue1: */\n\t/*\tWFD device information */\n\t/*\tWFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */\n\tval16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;\n\tRTW_PUT_BE16(wfdie + wfdielen, val16);\n\twfdielen += 2;\n\n\t/*\tValue2: */\n\t/*\tSession Management Control Port */\n\t/*\tDefault TCP port for RTSP messages is 554 */\n\tRTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);\n\twfdielen += 2;\n\n\t/*\tValue3: */\n\t/*\tWFD Device Maximum Throughput */\n\t/*\t300Mbps is the maximum throughput */\n\tRTW_PUT_BE16(wfdie + wfdielen, 300);\n\twfdielen += 2;\n\n\t/*\tAssociated BSSID ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tAssociated BSSID */\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);\n\telse\n\t\t_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);\n\n\twfdielen += ETH_ALEN;\n\n\t/*\tCoupled Sink Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0007);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tCoupled Sink Status bitmap */\n\t/*\tNot coupled/available for Coupling */\n\twfdie[wfdielen++] = 0;\n\t/* MAC Addr. */\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\n\tif (P2P_ROLE_GO == pwdinfo->role) {\n\t\t/*\tWFD Session Information ATTR */\n\t\t/*\tType: */\n\t\twfdie[wfdielen++] = WFD_ATTR_SESSION_INFO;\n\n\t\t/*\tLength: */\n\t\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\t\tRTW_PUT_BE16(wfdie + wfdielen, 0x0000);\n\t\twfdielen += 2;\n\n\t\t/*\tTodo: to add the list of WFD device info descriptor in WFD group. */\n\n\t}\n\n\trtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);\n\nexit:\n\treturn len;\n}\n\nu32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)\n{\n\tu8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };\n\tu32 len = 0, wfdielen = 0;\n\tu16 val16 = 0;\n\t_adapter *padapter = pwdinfo->padapter;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wifi_display_info\t*pwfd_info = padapter->wdinfo.wfd_info;\n\n\tif (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))\n\t\tgoto exit;\n\n\t/*\tWFD OUI */\n\twfdielen = 0;\n\twfdie[wfdielen++] = 0x50;\n\twfdie[wfdielen++] = 0x6F;\n\twfdie[wfdielen++] = 0x9A;\n\twfdie[wfdielen++] = 0x0A;\t/*\tWFA WFD v1.0 */\n\n\t/*\tCommented by Albert 20110825 */\n\t/*\tAccording to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes */\n\t/*\t1. WFD Device Information */\n\t/*\t2. Associated BSSID ( Optional ) */\n\t/*\t3. Local IP Adress ( Optional ) */\n\n\n\t/*\tWFD Device Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue1: */\n\t/*\tWFD device information */\n\t/*\tWFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */\n\tval16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;\n\tRTW_PUT_BE16(wfdie + wfdielen, val16);\n\twfdielen += 2;\n\n\t/*\tValue2: */\n\t/*\tSession Management Control Port */\n\t/*\tDefault TCP port for RTSP messages is 554 */\n\tRTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);\n\twfdielen += 2;\n\n\t/*\tValue3: */\n\t/*\tWFD Device Maximum Throughput */\n\t/*\t300Mbps is the maximum throughput */\n\tRTW_PUT_BE16(wfdie + wfdielen, 300);\n\twfdielen += 2;\n\n\t/*\tAssociated BSSID ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tAssociated BSSID */\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);\n\telse\n\t\t_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);\n\n\twfdielen += ETH_ALEN;\n\n\t/*\tCoupled Sink Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0007);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tCoupled Sink Status bitmap */\n\t/*\tNot coupled/available for Coupling */\n\twfdie[wfdielen++] = 0;\n\t/* MAC Addr. */\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\n\n\trtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);\n\nexit:\n\treturn len;\n}\n\nu32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)\n{\n\tu8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };\n\tu32 len = 0, wfdielen = 0;\n\tu16 val16 = 0;\n\t_adapter *padapter = pwdinfo->padapter;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wifi_display_info\t*pwfd_info = padapter->wdinfo.wfd_info;\n\n\tif (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))\n\t\tgoto exit;\n\n\t/*\tWFD OUI */\n\twfdielen = 0;\n\twfdie[wfdielen++] = 0x50;\n\twfdie[wfdielen++] = 0x6F;\n\twfdie[wfdielen++] = 0x9A;\n\twfdie[wfdielen++] = 0x0A;\t/*\tWFA WFD v1.0 */\n\n\t/*\tCommented by Albert 20110825 */\n\t/*\tAccording to the WFD Specification, the provision discovery response frame should contain 3 WFD attributes */\n\t/*\t1. WFD Device Information */\n\t/*\t2. Associated BSSID ( Optional ) */\n\t/*\t3. Local IP Adress ( Optional ) */\n\n\n\t/*\tWFD Device Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue1: */\n\t/*\tWFD device information */\n\t/*\tWFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */\n\tval16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;\n\tRTW_PUT_BE16(wfdie + wfdielen, val16);\n\twfdielen += 2;\n\n\t/*\tValue2: */\n\t/*\tSession Management Control Port */\n\t/*\tDefault TCP port for RTSP messages is 554 */\n\tRTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);\n\twfdielen += 2;\n\n\t/*\tValue3: */\n\t/*\tWFD Device Maximum Throughput */\n\t/*\t300Mbps is the maximum throughput */\n\tRTW_PUT_BE16(wfdie + wfdielen, 300);\n\twfdielen += 2;\n\n\t/*\tAssociated BSSID ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tAssociated BSSID */\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);\n\telse\n\t\t_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);\n\n\twfdielen += ETH_ALEN;\n\n\t/*\tCoupled Sink Information ATTR */\n\t/*\tType: */\n\twfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;\n\n\t/*\tLength: */\n\t/*\tNote: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0007);\n\twfdielen += 2;\n\n\t/*\tValue: */\n\t/*\tCoupled Sink Status bitmap */\n\t/*\tNot coupled/available for Coupling */\n\twfdie[wfdielen++] = 0;\n\t/* MAC Addr. */\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\twfdie[wfdielen++] = 0;\n\n\trtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);\n\nexit:\n\treturn len;\n}\n#endif /* CONFIG_WFD */\n\nu32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)\n{\n\tu8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };\n\tu32 len = 0, p2pielen = 0;\n\n\t/*\tP2P OUI */\n\tp2pielen = 0;\n\tp2pie[p2pielen++] = 0x50;\n\tp2pie[p2pielen++] = 0x6F;\n\tp2pie[p2pielen++] = 0x9A;\n\tp2pie[p2pielen++] = 0x09;\t/*\tWFA P2P v1.0 */\n\n\t/*\tCommented by Albert 20100907 */\n\t/*\tAccording to the P2P Specification, the probe response frame should contain 5 P2P attributes */\n\t/*\t1. P2P Capability */\n\t/*\t2. Extended Listen Timing */\n\t/*\t3. Notice of Absence ( NOA )\t( Only GO needs this ) */\n\t/*\t4. Device Info */\n\t/*\t5. Group Info\t( Only GO need this ) */\n\n\t/*\tP2P Capability ATTR */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CAPABILITY;\n\n\t/*\tLength: */\n\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); */\n\tRTW_PUT_LE16(p2pie + p2pielen, 0x0002);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tDevice Capability Bitmap, 1 byte */\n\tp2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;\n\n\t/*\tGroup Capability Bitmap, 1 byte */\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\tp2pie[p2pielen] = (P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS);\n\n\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))\n\t\t\tp2pie[p2pielen] |= P2P_GRPCAP_GROUP_FORMATION;\n\n\t\tp2pielen++;\n\t} else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) {\n\t\t/*\tGroup Capability Bitmap, 1 byte */\n\t\tif (pwdinfo->persistent_supported)\n\t\t\tp2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;\n\t\telse\n\t\t\tp2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT;\n\t}\n\n\t/*\tExtended Listen Timing ATTR */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING;\n\n\t/*\tLength: */\n\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); */\n\tRTW_PUT_LE16(p2pie + p2pielen, 0x0004);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tAvailability Period */\n\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); */\n\tRTW_PUT_LE16(p2pie + p2pielen, 0xFFFF);\n\tp2pielen += 2;\n\n\t/*\tAvailability Interval */\n\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); */\n\tRTW_PUT_LE16(p2pie + p2pielen, 0xFFFF);\n\tp2pielen += 2;\n\n\n\t/* Notice of Absence ATTR */\n\t/*\tType:  */\n\t/*\tLength: */\n\t/*\tValue: */\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\t/* go_add_noa_attr(pwdinfo); */\n\t}\n\n\t/*\tDevice Info ATTR */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\t21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */\n\t/*\t+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */\n\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); */\n\tRTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tP2P Device Address */\n\t_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN);\n\tp2pielen += ETH_ALEN;\n\n\t/*\tConfig Method */\n\t/*\tThis field should be big endian. Noted by P2P specification. */\n\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); */\n\tRTW_PUT_BE16(p2pie + p2pielen, pwdinfo->supported_wps_cm);\n\tp2pielen += 2;\n\n\t{\n\t\t/*\tPrimary Device Type */\n\t\t/*\tCategory ID */\n\t\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); */\n\t\tRTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA);\n\t\tp2pielen += 2;\n\n\t\t/*\tOUI */\n\t\t/* *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); */\n\t\tRTW_PUT_BE32(p2pie + p2pielen, WPSOUI);\n\t\tp2pielen += 4;\n\n\t\t/*\tSub Category ID */\n\t\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); */\n\t\tRTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER);\n\t\tp2pielen += 2;\n\t}\n\n\t/*\tNumber of Secondary Device Types */\n\tp2pie[p2pielen++] = 0x00;\t/*\tNo Secondary Device Type List */\n\n\t/*\tDevice Name */\n\t/*\tType: */\n\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */\n\tRTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME);\n\tp2pielen += 2;\n\n\t/*\tLength: */\n\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); */\n\tRTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len);\n\tp2pielen += pwdinfo->device_name_len;\n\n\t/* Group Info ATTR */\n\t/*\tType: */\n\t/*\tLength: */\n\t/*\tValue: */\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))\n\t\tp2pielen += go_add_group_info_attr(pwdinfo, p2pie + p2pielen);\n\n\n\tpbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);\n\n\n\treturn len;\n\n}\n\nu32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 *pssid, u8 ussidlen, u8 *pdev_raddr)\n{\n\tu8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };\n\tu32 len = 0, p2pielen = 0;\n\n\t/*\tP2P OUI */\n\tp2pielen = 0;\n\tp2pie[p2pielen++] = 0x50;\n\tp2pie[p2pielen++] = 0x6F;\n\tp2pie[p2pielen++] = 0x9A;\n\tp2pie[p2pielen++] = 0x09;\t/*\tWFA P2P v1.0 */\n\n\t/*\tCommented by Albert 20110301 */\n\t/*\tAccording to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes */\n\t/*\t1. P2P Capability */\n\t/*\t2. Device Info */\n\t/*\t3. Group ID ( When joining an operating P2P Group ) */\n\n\t/*\tP2P Capability ATTR */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CAPABILITY;\n\n\t/*\tLength: */\n\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); */\n\tRTW_PUT_LE16(p2pie + p2pielen, 0x0002);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tDevice Capability Bitmap, 1 byte */\n\tp2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;\n\n\t/*\tGroup Capability Bitmap, 1 byte */\n\tif (pwdinfo->persistent_supported)\n\t\tp2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;\n\telse\n\t\tp2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT;\n\n\n\t/*\tDevice Info ATTR */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\t21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */\n\t/*\t+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */\n\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); */\n\tRTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tP2P Device Address */\n\t_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN);\n\tp2pielen += ETH_ALEN;\n\n\t/*\tConfig Method */\n\t/*\tThis field should be big endian. Noted by P2P specification. */\n\tif (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC) {\n\t\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_PBC ); */\n\t\tRTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_PBC);\n\t} else {\n\t\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY ); */\n\t\tRTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_DISPLAY);\n\t}\n\n\tp2pielen += 2;\n\n\t/*\tPrimary Device Type */\n\t/*\tCategory ID */\n\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); */\n\tRTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA);\n\tp2pielen += 2;\n\n\t/*\tOUI */\n\t/* *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); */\n\tRTW_PUT_BE32(p2pie + p2pielen, WPSOUI);\n\tp2pielen += 4;\n\n\t/*\tSub Category ID */\n\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); */\n\tRTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER);\n\tp2pielen += 2;\n\n\t/*\tNumber of Secondary Device Types */\n\tp2pie[p2pielen++] = 0x00;\t/*\tNo Secondary Device Type List */\n\n\t/*\tDevice Name */\n\t/*\tType: */\n\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */\n\tRTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME);\n\tp2pielen += 2;\n\n\t/*\tLength: */\n\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); */\n\tRTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len);\n\tp2pielen += pwdinfo->device_name_len;\n\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {\n\t\t/*\tAdded by Albert 2011/05/19 */\n\t\t/*\tIn this case, the pdev_raddr is the device address of the group owner. */\n\n\t\t/*\tP2P Group ID ATTR */\n\t\t/*\tType: */\n\t\tp2pie[p2pielen++] = P2P_ATTR_GROUP_ID;\n\n\t\t/*\tLength: */\n\t\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + ussidlen ); */\n\t\tRTW_PUT_LE16(p2pie + p2pielen, ETH_ALEN + ussidlen);\n\t\tp2pielen += 2;\n\n\t\t/*\tValue: */\n\t\t_rtw_memcpy(p2pie + p2pielen, pdev_raddr, ETH_ALEN);\n\t\tp2pielen += ETH_ALEN;\n\n\t\t_rtw_memcpy(p2pie + p2pielen, pssid, ussidlen);\n\t\tp2pielen += ussidlen;\n\n\t}\n\n\tpbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);\n\n\n\treturn len;\n\n}\n\n\nu32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code)\n{\n\tu8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };\n\tu32 len = 0, p2pielen = 0;\n\n\t/*\tP2P OUI */\n\tp2pielen = 0;\n\tp2pie[p2pielen++] = 0x50;\n\tp2pie[p2pielen++] = 0x6F;\n\tp2pie[p2pielen++] = 0x9A;\n\tp2pie[p2pielen++] = 0x09;\t/*\tWFA P2P v1.0 */\n\n\t/* According to the P2P Specification, the Association response frame should contain 2 P2P attributes */\n\t/*\t1. Status */\n\t/*\t2. Extended Listen Timing (optional) */\n\n\n\t/*\tStatus ATTR */\n\tp2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status_code);\n\n\n\t/* Extended Listen Timing ATTR */\n\t/*\tType: */\n\t/*\tLength: */\n\t/*\tValue: */\n\n\n\tpbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);\n\n\treturn len;\n\n}\n\nu32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)\n{\n\tu32 len = 0;\n\n\treturn len;\n}\n\nu32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)\n{\n\tu8 *p;\n\tu32 ret = _FALSE;\n\tu8 *p2pie;\n\tu32\tp2pielen = 0;\n\tint ssid_len = 0, rate_cnt = 0;\n\n\tp = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SUPPORTEDRATES_IE_, (int *)&rate_cnt,\n\t\t       len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);\n\n\tif (rate_cnt <= 4) {\n\t\tint i, g_rate = 0;\n\n\t\tfor (i = 0; i < rate_cnt; i++) {\n\t\t\tif (((*(p + 2 + i) & 0xff) != 0x02) &&\n\t\t\t    ((*(p + 2 + i) & 0xff) != 0x04) &&\n\t\t\t    ((*(p + 2 + i) & 0xff) != 0x0B) &&\n\t\t\t    ((*(p + 2 + i) & 0xff) != 0x16))\n\t\t\t\tg_rate = 1;\n\t\t}\n\n\t\tif (g_rate == 0) {\n\t\t\t/*\tThere is no OFDM rate included in SupportedRates IE of this probe request frame */\n\t\t\t/*\tThe driver should response this probe request. */\n\t\t\treturn ret;\n\t\t}\n\t} else {\n\t\t/*\trate_cnt > 4 means the SupportRates IE contains the OFDM rate because the count of CCK rates are 4. */\n\t\t/*\tWe should proceed the following check for this probe request. */\n\t}\n\n\t/*\tAdded comments by Albert 20100906 */\n\t/*\tThere are several items we should check here. */\n\t/*\t1. This probe request frame must contain the P2P IE. (Done) */\n\t/*\t2. This probe request frame must contain the wildcard SSID. (Done) */\n\t/*\t3. Wildcard BSSID. (Todo) */\n\t/*\t4. Destination Address. ( Done in mgt_dispatcher function ) */\n\t/*\t5. Requested Device Type in WSC IE. (Todo) */\n\t/*\t6. Device ID attribute in P2P IE. (Todo) */\n\n\tp = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ssid_len,\n\t\t       len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);\n\n\tssid_len &= 0xff;\t/*\tJust last 1 byte is valid for ssid len of the probe request */\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\tp2pie = rtw_get_p2p_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_ , len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_ , NULL, &p2pielen);\n\t\tif (p2pie) {\n\t\t\tif ((p != NULL) && _rtw_memcmp((void *)(p + 2), (void *) pwdinfo->p2p_wildcard_ssid , 7)) {\n\t\t\t\t/* todo: */\n\t\t\t\t/* Check Requested Device Type attributes in WSC IE. */\n\t\t\t\t/* Check Device ID attribute in P2P IE */\n\n\t\t\t\tret = _TRUE;\n\t\t\t} else if ((p != NULL) && (ssid_len == 0))\n\t\t\t\tret = _TRUE;\n\t\t} else {\n\t\t\t/* non -p2p device */\n\t\t}\n\n\t}\n\n\n\treturn ret;\n\n}\n\nu32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta)\n{\n\tu8 status_code = P2P_STATUS_SUCCESS;\n\tu8 *pbuf, *pattr_content = NULL;\n\tu32 attr_contentlen = 0;\n\tu16 cap_attr = 0;\n\tunsigned short\tframe_type, ie_offset = 0;\n\tu8 *ies;\n\tu32 ies_len;\n\tu8 *p2p_ie;\n\tu32\tp2p_ielen = 0;\n\n\tif (!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))\n\t\treturn P2P_STATUS_FAIL_REQUEST_UNABLE;\n\n\tframe_type = get_frame_sub_type(pframe);\n\tif (frame_type == WIFI_ASSOCREQ)\n\t\tie_offset = _ASOCREQ_IE_OFFSET_;\n\telse /* WIFI_REASSOCREQ */\n\t\tie_offset = _REASOCREQ_IE_OFFSET_;\n\n\ties = pframe + WLAN_HDR_A3_LEN + ie_offset;\n\ties_len = len - WLAN_HDR_A3_LEN - ie_offset;\n\n\tp2p_ie = rtw_get_p2p_ie(ies , ies_len , NULL, &p2p_ielen);\n\n\tif (!p2p_ie) {\n\t\tRTW_INFO(\"[%s] P2P IE not Found!!\\n\", __FUNCTION__);\n\t\tstatus_code =  P2P_STATUS_FAIL_INVALID_PARAM;\n\t} else\n\t\tRTW_INFO(\"[%s] P2P IE Found!!\\n\", __FUNCTION__);\n\n\twhile (p2p_ie) {\n\t\t/* Check P2P Capability ATTR */\n\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *) &attr_contentlen)) {\n\t\t\tRTW_INFO(\"[%s] Got P2P Capability Attr!!\\n\", __FUNCTION__);\n\t\t\tcap_attr = le16_to_cpu(cap_attr);\n\t\t\tpsta->dev_cap = cap_attr & 0xff;\n\t\t}\n\n\t\t/* Check Extended Listen Timing ATTR */\n\n\n\t\t/* Check P2P Device Info ATTR */\n\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, NULL, (uint *)&attr_contentlen)) {\n\t\t\tRTW_INFO(\"[%s] Got P2P DEVICE INFO Attr!!\\n\", __FUNCTION__);\n\t\t\tpattr_content = pbuf = rtw_zmalloc(attr_contentlen);\n\t\t\tif (pattr_content) {\n\t\t\t\tu8 num_of_secdev_type;\n\t\t\t\tu16 dev_name_len;\n\n\n\t\t\t\trtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO , pattr_content, (uint *)&attr_contentlen);\n\n\t\t\t\t_rtw_memcpy(psta->dev_addr, \tpattr_content, ETH_ALEN);/* P2P Device Address */\n\n\t\t\t\tpattr_content += ETH_ALEN;\n\n\t\t\t\t_rtw_memcpy(&psta->config_methods, pattr_content, 2);/* Config Methods */\n\t\t\t\tpsta->config_methods = be16_to_cpu(psta->config_methods);\n\n\t\t\t\tpattr_content += 2;\n\n\t\t\t\t_rtw_memcpy(psta->primary_dev_type, pattr_content, 8);\n\n\t\t\t\tpattr_content += 8;\n\n\t\t\t\tnum_of_secdev_type = *pattr_content;\n\t\t\t\tpattr_content += 1;\n\n\t\t\t\tif (num_of_secdev_type == 0)\n\t\t\t\t\tpsta->num_of_secdev_type = 0;\n\t\t\t\telse {\n\t\t\t\t\tu32 len;\n\n\t\t\t\t\tpsta->num_of_secdev_type = num_of_secdev_type;\n\n\t\t\t\t\tlen = (sizeof(psta->secdev_types_list) < (num_of_secdev_type * 8)) ? (sizeof(psta->secdev_types_list)) : (num_of_secdev_type * 8);\n\n\t\t\t\t\t_rtw_memcpy(psta->secdev_types_list, pattr_content, len);\n\n\t\t\t\t\tpattr_content += (num_of_secdev_type * 8);\n\t\t\t\t}\n\n\n\t\t\t\t/* dev_name_len = attr_contentlen - ETH_ALEN - 2 - 8 - 1 - (num_of_secdev_type*8); */\n\t\t\t\tpsta->dev_name_len = 0;\n\t\t\t\tif (WPS_ATTR_DEVICE_NAME == be16_to_cpu(*(u16 *)pattr_content)) {\n\t\t\t\t\tdev_name_len = be16_to_cpu(*(u16 *)(pattr_content + 2));\n\n\t\t\t\t\tpsta->dev_name_len = (sizeof(psta->dev_name) < dev_name_len) ? sizeof(psta->dev_name) : dev_name_len;\n\n\t\t\t\t\t_rtw_memcpy(psta->dev_name, pattr_content + 4, psta->dev_name_len);\n\t\t\t\t}\n\n\t\t\t\trtw_mfree(pbuf, attr_contentlen);\n\n\t\t\t}\n\n\t\t}\n\n\t\t/* Get the next P2P IE */\n\t\tp2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);\n\n\t}\n\n\treturn status_code;\n\n}\n\nu32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)\n{\n\tu8 *frame_body;\n\tu8 status, dialogToken;\n\tstruct sta_info *psta = NULL;\n\t_adapter *padapter = pwdinfo->padapter;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tu8 *p2p_ie;\n\tu32\tp2p_ielen = 0;\n\n\tframe_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));\n\n\tdialogToken = frame_body[7];\n\tstatus = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP;\n\n\tp2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen);\n\tif (p2p_ie) {\n\t\tu8 groupid[38] = { 0x00 };\n\t\tu8 dev_addr[ETH_ALEN] = { 0x00 };\n\t\tu32\tattr_contentlen = 0;\n\n\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) {\n\t\t\tif (_rtw_memcmp(pwdinfo->device_addr, groupid, ETH_ALEN) &&\n\t\t\t    _rtw_memcmp(pwdinfo->p2p_group_ssid, groupid + ETH_ALEN, pwdinfo->p2p_group_ssid_len)) {\n\t\t\t\tattr_contentlen = 0;\n\t\t\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_ID, dev_addr, &attr_contentlen)) {\n\t\t\t\t\t_irqL irqL;\n\t\t\t\t\t_list\t*phead, *plist;\n\n\t\t\t\t\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\t\t\t\t\tphead = &pstapriv->asoc_list;\n\t\t\t\t\tplist = get_next(phead);\n\n\t\t\t\t\t/* look up sta asoc_queue */\n\t\t\t\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\t\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);\n\n\t\t\t\t\t\tplist = get_next(plist);\n\n\t\t\t\t\t\tif (psta->is_p2p_device && (psta->dev_cap & P2P_DEVCAP_CLIENT_DISCOVERABILITY) &&\n\t\t\t\t\t\t    _rtw_memcmp(psta->dev_addr, dev_addr, ETH_ALEN)) {\n\n\t\t\t\t\t\t\t/* _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); */\n\t\t\t\t\t\t\t/* issue GO Discoverability Request */\n\t\t\t\t\t\t\tissue_group_disc_req(pwdinfo, psta->cmn.mac_addr);\n\t\t\t\t\t\t\t/* _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); */\n\n\t\t\t\t\t\t\tstatus = P2P_STATUS_SUCCESS;\n\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t} else\n\t\t\t\t\t\t\tstatus = P2P_STATUS_FAIL_INFO_UNAVAILABLE;\n\n\t\t\t\t\t}\n\t\t\t\t\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\t\t\t\t} else\n\t\t\t\t\tstatus = P2P_STATUS_FAIL_INVALID_PARAM;\n\n\t\t\t} else\n\t\t\t\tstatus = P2P_STATUS_FAIL_INVALID_PARAM;\n\n\t\t}\n\n\t}\n\n\n\t/* issue Device Discoverability Response */\n\tissue_p2p_devdisc_resp(pwdinfo, get_addr2_ptr(pframe), status, dialogToken);\n\n\n\treturn (status == P2P_STATUS_SUCCESS) ? _TRUE : _FALSE;\n\n}\n\nu32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)\n{\n\treturn _TRUE;\n}\n\nu8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo,  u8 *pframe, uint len)\n{\n\tu8 *frame_body;\n\tu8 *wpsie;\n\tuint\twps_ielen = 0, attr_contentlen = 0;\n\tu16\tuconfig_method = 0;\n\n\n\tframe_body = (pframe + sizeof(struct rtw_ieee80211_hdr_3addr));\n\n\twpsie = rtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen);\n\tif (wpsie) {\n\t\tif (rtw_get_wps_attr_content(wpsie, wps_ielen, WPS_ATTR_CONF_METHOD , (u8 *) &uconfig_method, &attr_contentlen)) {\n\t\t\tuconfig_method = be16_to_cpu(uconfig_method);\n\t\t\tswitch (uconfig_method) {\n\t\t\tcase WPS_CM_DISPLYA: {\n\t\t\t\t_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, \"dis\", 3);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tcase WPS_CM_LABEL: {\n\t\t\t\t_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, \"lab\", 3);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tcase WPS_CM_PUSH_BUTTON: {\n\t\t\t\t_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, \"pbc\", 3);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tcase WPS_CM_KEYPAD: {\n\t\t\t\t_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, \"pad\", 3);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\t}\n\t\t\tissue_p2p_provision_resp(pwdinfo, get_addr2_ptr(pframe), frame_body, uconfig_method);\n\t\t}\n\t}\n\tRTW_INFO(\"[%s] config method = %s\\n\", __FUNCTION__, pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req);\n\treturn _TRUE;\n\n}\n\nu8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo,  u8 *pframe)\n{\n\n\treturn _TRUE;\n}\n\nu8 rtw_p2p_get_peer_ch_list(struct wifidirect_info *pwdinfo, u8 *ch_content, u8 ch_cnt, u8 *peer_ch_list)\n{\n\tu8 i = 0, j = 0;\n\tu8 temp = 0;\n\tu8 ch_no = 0;\n\tch_content += 3;\n\tch_cnt -= 3;\n\n\twhile (ch_cnt > 0) {\n\t\tch_content += 1;\n\t\tch_cnt -= 1;\n\t\ttemp = *ch_content;\n\t\tfor (i = 0 ; i < temp ; i++, j++)\n\t\t\tpeer_ch_list[j] = *(ch_content + 1 + i);\n\t\tch_content += (temp + 1);\n\t\tch_cnt -= (temp + 1);\n\t\tch_no += temp ;\n\t}\n\n\treturn ch_no;\n}\n\nu8 rtw_p2p_ch_inclusion(_adapter *adapter, u8 *peer_ch_list, u8 peer_ch_num, u8 *ch_list_inclusioned)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tint\ti = 0, j = 0, temp = 0;\n\tu8 ch_no = 0;\n\n\tfor (i = 0; i < peer_ch_num; i++) {\n\t\tfor (j = temp; j < rfctl->max_chan_nums; j++) {\n\t\t\tif (*(peer_ch_list + i) == rfctl->channel_set[j].ChannelNum) {\n\t\t\t\tch_list_inclusioned[ch_no++] = *(peer_ch_list + i);\n\t\t\t\ttemp = j;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn ch_no;\n}\n\nu8 process_p2p_group_negotation_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)\n{\n\t_adapter *padapter = pwdinfo->padapter;\n\tu8\tresult = P2P_STATUS_SUCCESS;\n\tu32\tp2p_ielen = 0, wps_ielen = 0;\n\tu8 *ies;\n\tu32 ies_len;\n\tu8 *p2p_ie;\n\tu8 *wpsie;\n\tu16\t\twps_devicepassword_id = 0x0000;\n\tuint\twps_devicepassword_id_len = 0;\n#ifdef CONFIG_WFD\n#ifdef CONFIG_TDLS\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n#endif /* CONFIG_TDLS\t */\n#endif /* CONFIG_WFD */\n\twpsie = rtw_get_wps_ie(pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen);\n\tif (wpsie) {\n\t\t/*\tCommented by Kurt 20120113 */\n\t\t/*\tIf some device wants to do p2p handshake without sending prov_disc_req */\n\t\t/*\tWe have to get peer_req_cm from here. */\n\t\tif (_rtw_memcmp(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, \"000\", 3)) {\n\t\t\trtw_get_wps_attr_content(wpsie, wps_ielen, WPS_ATTR_DEVICE_PWID, (u8 *) &wps_devicepassword_id, &wps_devicepassword_id_len);\n\t\t\twps_devicepassword_id = be16_to_cpu(wps_devicepassword_id);\n\n\t\t\tif (wps_devicepassword_id == WPS_DPID_USER_SPEC)\n\t\t\t\t_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, \"dis\", 3);\n\t\t\telse if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)\n\t\t\t\t_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, \"pad\", 3);\n\t\t\telse\n\t\t\t\t_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, \"pbc\", 3);\n\t\t}\n\t} else {\n\t\tRTW_INFO(\"[%s] WPS IE not Found!!\\n\", __FUNCTION__);\n\t\tresult = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;\n\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);\n\t\treturn result ;\n\t}\n\n\ties = pframe + _PUBLIC_ACTION_IE_OFFSET_;\n\ties_len = len - _PUBLIC_ACTION_IE_OFFSET_;\n\n\tp2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);\n\n\tif (!p2p_ie) {\n\t\tRTW_INFO(\"[%s] P2P IE not Found!!\\n\", __FUNCTION__);\n\t\tresult = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;\n\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);\n\t}\n\n\twhile (p2p_ie) {\n\t\tu8\tattr_content = 0x00;\n\t\tu32\tattr_contentlen = 0;\n\t\tu8\tch_content[100] = { 0x00 };\n\t\tuint\tch_cnt = 0;\n\t\tu8\tpeer_ch_list[100] = { 0x00 };\n\t\tu8\tpeer_ch_num = 0;\n\t\tu8\tch_list_inclusioned[100] = { 0x00 };\n\t\tu8\tch_num_inclusioned = 0;\n\t\tu16\tcap_attr;\n\t\tu8 listen_ch_attr[5] = { 0x00 };\n\n\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING);\n\n\t\t/* Check P2P Capability ATTR */\n\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *)&attr_contentlen)) {\n\t\t\tcap_attr = le16_to_cpu(cap_attr);\n\n#if defined(CONFIG_WFD) && defined(CONFIG_TDLS)\n\t\t\tif (!(cap_attr & P2P_GRPCAP_INTRABSS))\n\t\t\t\tptdlsinfo->ap_prohibited = _TRUE;\n#endif /* defined(CONFIG_WFD) && defined(CONFIG_TDLS) */\n\t\t}\n\n\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen)) {\n\t\t\tRTW_INFO(\"[%s] GO Intent = %d, tie = %d\\n\", __FUNCTION__, attr_content >> 1, attr_content & 0x01);\n\t\t\tpwdinfo->peer_intent = attr_content;\t/*\tinclude both intent and tie breaker values. */\n\n\t\t\tif (pwdinfo->intent == (pwdinfo->peer_intent >> 1)) {\n\t\t\t\t/*\tTry to match the tie breaker value */\n\t\t\t\tif (pwdinfo->intent == P2P_MAX_INTENT) {\n\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);\n\t\t\t\t\tresult = P2P_STATUS_FAIL_BOTH_GOINTENT_15;\n\t\t\t\t} else {\n\t\t\t\t\tif (attr_content & 0x01)\n\t\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);\n\t\t\t\t\telse\n\t\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);\n\t\t\t\t}\n\t\t\t} else if (pwdinfo->intent > (pwdinfo->peer_intent >> 1))\n\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);\n\t\t\telse\n\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);\n\n\t\t\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\t\t\t/*\tStore the group id information. */\n\t\t\t\t_rtw_memcpy(pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN);\n\t\t\t\t_rtw_memcpy(pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);\n\t\t\t}\n\t\t}\n\n\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, (u8 *)listen_ch_attr, (uint *) &attr_contentlen) && attr_contentlen == 5)\n\t\t\tpwdinfo->nego_req_info.peer_ch = listen_ch_attr[4];\n\n\t\tRTW_INFO(FUNC_ADPT_FMT\" listen channel :%u\\n\", FUNC_ADPT_ARG(padapter), pwdinfo->nego_req_info.peer_ch);\n\n\t\tattr_contentlen = 0;\n\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) {\n\t\t\tif (attr_contentlen != ETH_ALEN)\n\t\t\t\t_rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN);\n\t\t}\n\n\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, ch_content, &ch_cnt)) {\n\t\t\tpeer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, ch_content, ch_cnt, peer_ch_list);\n\t\t\tch_num_inclusioned = rtw_p2p_ch_inclusion(padapter, peer_ch_list, peer_ch_num, ch_list_inclusioned);\n\n\t\t\tif (ch_num_inclusioned == 0) {\n\t\t\t\tRTW_INFO(\"[%s] No common channel in channel list!\\n\", __FUNCTION__);\n\t\t\t\tresult = P2P_STATUS_FAIL_NO_COMMON_CH;\n\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\t\t\tif (!rtw_p2p_is_channel_list_ok(pwdinfo->operating_channel,\n\t\t\t\t\tch_list_inclusioned, ch_num_inclusioned)) {\n#ifdef CONFIG_CONCURRENT_MODE\n\t\t\t\t\tif (rtw_mi_check_status(padapter, MI_LINKED)\n\t\t\t\t\t    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {\n\t\t\t\t\t\tRTW_INFO(\"[%s] desired channel NOT Found!\\n\", __FUNCTION__);\n\t\t\t\t\t\tresult = P2P_STATUS_FAIL_NO_COMMON_CH;\n\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t} else\n#endif /* CONFIG_CONCURRENT_MODE */\n\t\t\t\t\t{\n\t\t\t\t\t\tu8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0;\n\t\t\t\t\t\tattr_contentlen = 0;\n\n\t\t\t\t\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen))\n\t\t\t\t\t\t\tpeer_operating_ch = operatingch_info[4];\n\n\t\t\t\t\t\tif (rtw_p2p_is_channel_list_ok(peer_operating_ch,\n\t\t\t\t\t\t\tch_list_inclusioned, ch_num_inclusioned)) {\n\t\t\t\t\t\t\t/**\n\t\t\t\t\t\t\t *\tChange our operating channel as peer's for compatibility.\n\t\t\t\t\t\t\t */\n\t\t\t\t\t\t\tpwdinfo->operating_channel = peer_operating_ch;\n\t\t\t\t\t\t\tRTW_INFO(\"[%s] Change op ch to %02x as peer's\\n\", __FUNCTION__, pwdinfo->operating_channel);\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t/* Take first channel of ch_list_inclusioned as operating channel */\n\t\t\t\t\t\t\tpwdinfo->operating_channel = ch_list_inclusioned[0];\n\t\t\t\t\t\t\tRTW_INFO(\"[%s] Change op ch to %02x\\n\", __FUNCTION__, pwdinfo->operating_channel);\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/* Get the next P2P IE */\n\t\tp2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);\n\t}\n\n\tif (pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO) {\n\t\tresult = P2P_STATUS_FAIL_INFO_UNAVAILABLE;\n\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INFOR_NOREADY);\n\t\treturn result;\n\t}\n\n#ifdef CONFIG_WFD\n\trtw_process_wfd_ies(padapter, pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, __func__);\n#endif\n\n\treturn result ;\n}\n\nu8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)\n{\n\t_adapter *padapter = pwdinfo->padapter;\n\tu8\tresult = P2P_STATUS_SUCCESS;\n\tu32\tp2p_ielen, wps_ielen;\n\tu8 *ies;\n\tu32 ies_len;\n\tu8 *p2p_ie;\n#ifdef CONFIG_WFD\n#ifdef CONFIG_TDLS\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n#endif /* CONFIG_TDLS\t */\n#endif /* CONFIG_WFD */\n\n\ties = pframe + _PUBLIC_ACTION_IE_OFFSET_;\n\ties_len = len - _PUBLIC_ACTION_IE_OFFSET_;\n\n\t/*\tBe able to know which one is the P2P GO and which one is P2P client. */\n\n\tif (rtw_get_wps_ie(ies, ies_len, NULL, &wps_ielen)) {\n\n\t} else {\n\t\tRTW_INFO(\"[%s] WPS IE not Found!!\\n\", __FUNCTION__);\n\t\tresult = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;\n\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);\n\t}\n\n\tp2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);\n\tif (!p2p_ie) {\n\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);\n\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);\n\t\tresult = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;\n\t} else {\n\n\t\tu8\tattr_content = 0x00;\n\t\tu32\tattr_contentlen = 0;\n\t\tu8\toperatingch_info[5] = { 0x00 };\n\t\tu8\tgroupid[38];\n\t\tu16\tcap_attr;\n\t\tu8\tpeer_ch_list[100] = { 0x00 };\n\t\tu8\tpeer_ch_num = 0;\n\t\tu8\tch_list_inclusioned[100] = { 0x00 };\n\t\tu8\tch_num_inclusioned = 0;\n\n\t\twhile (p2p_ie) {\t/*\tFound the P2P IE. */\n\n\t\t\t/* Check P2P Capability ATTR */\n\t\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *)&attr_contentlen)) {\n\t\t\t\tcap_attr = le16_to_cpu(cap_attr);\n#ifdef CONFIG_TDLS\n\t\t\t\tif (!(cap_attr & P2P_GRPCAP_INTRABSS))\n\t\t\t\t\tptdlsinfo->ap_prohibited = _TRUE;\n#endif /* CONFIG_TDLS */\n\t\t\t}\n\n\t\t\trtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen);\n\t\t\tif (attr_contentlen == 1) {\n\t\t\t\tRTW_INFO(\"[%s] Status = %d\\n\", __FUNCTION__, attr_content);\n\t\t\t\tif (attr_content == P2P_STATUS_SUCCESS) {\n\t\t\t\t\t/*\tDo nothing. */\n\t\t\t\t} else {\n\t\t\t\t\tif (P2P_STATUS_FAIL_INFO_UNAVAILABLE == attr_content)\n\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INFOR_NOREADY);\n\t\t\t\t\telse\n\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);\n\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);\n\t\t\t\t\tresult = attr_content;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/*\tTry to get the peer's interface address */\n\t\t\tattr_contentlen = 0;\n\t\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) {\n\t\t\t\tif (attr_contentlen != ETH_ALEN)\n\t\t\t\t\t_rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN);\n\t\t\t}\n\n\t\t\t/*\tTry to get the peer's intent and tie breaker value. */\n\t\t\tattr_content = 0x00;\n\t\t\tattr_contentlen = 0;\n\t\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen)) {\n\t\t\t\tRTW_INFO(\"[%s] GO Intent = %d, tie = %d\\n\", __FUNCTION__, attr_content >> 1, attr_content & 0x01);\n\t\t\t\tpwdinfo->peer_intent = attr_content;\t/*\tinclude both intent and tie breaker values. */\n\n\t\t\t\tif (pwdinfo->intent == (pwdinfo->peer_intent >> 1)) {\n\t\t\t\t\t/*\tTry to match the tie breaker value */\n\t\t\t\t\tif (pwdinfo->intent == P2P_MAX_INTENT) {\n\t\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);\n\t\t\t\t\t\tresult = P2P_STATUS_FAIL_BOTH_GOINTENT_15;\n\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);\n\t\t\t\t\t} else {\n\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);\n\t\t\t\t\t\trtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);\n\t\t\t\t\t\tif (attr_content & 0x01)\n\t\t\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);\n\t\t\t\t\t}\n\t\t\t\t} else if (pwdinfo->intent > (pwdinfo->peer_intent >> 1)) {\n\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);\n\t\t\t\t\trtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);\n\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);\n\t\t\t\t} else {\n\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);\n\t\t\t\t\trtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);\n\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);\n\t\t\t\t}\n\n\t\t\t\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\t\t\t\t/*\tStore the group id information. */\n\t\t\t\t\t_rtw_memcpy(pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN);\n\t\t\t\t\t_rtw_memcpy(pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);\n\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/*\tTry to get the operation channel information */\n\n\t\t\tattr_contentlen = 0;\n\t\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) {\n\t\t\t\tRTW_INFO(\"[%s] Peer's operating channel = %d\\n\", __FUNCTION__, operatingch_info[4]);\n\t\t\t\tpwdinfo->peer_operating_ch = operatingch_info[4];\n\t\t\t}\n\n\t\t\t/*\tTry to get the channel list information */\n\t\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, pwdinfo->channel_list_attr, &pwdinfo->channel_list_attr_len)) {\n\t\t\t\tRTW_INFO(\"[%s] channel list attribute found, len = %d\\n\", __FUNCTION__,  pwdinfo->channel_list_attr_len);\n\n\t\t\t\tpeer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, pwdinfo->channel_list_attr, pwdinfo->channel_list_attr_len, peer_ch_list);\n\t\t\t\tch_num_inclusioned = rtw_p2p_ch_inclusion(padapter, peer_ch_list, peer_ch_num, ch_list_inclusioned);\n\n\t\t\t\tif (ch_num_inclusioned == 0) {\n\t\t\t\t\tRTW_INFO(\"[%s] No common channel in channel list!\\n\", __FUNCTION__);\n\t\t\t\t\tresult = P2P_STATUS_FAIL_NO_COMMON_CH;\n\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\t\t\t\tif (!rtw_p2p_is_channel_list_ok(pwdinfo->operating_channel,\n\t\t\t\t\t\tch_list_inclusioned, ch_num_inclusioned)) {\n#ifdef CONFIG_CONCURRENT_MODE\n\t\t\t\t\t\tif (rtw_mi_check_status(padapter, MI_LINKED)\n\t\t\t\t\t\t    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {\n\t\t\t\t\t\t\tRTW_INFO(\"[%s] desired channel NOT Found!\\n\", __FUNCTION__);\n\t\t\t\t\t\t\tresult = P2P_STATUS_FAIL_NO_COMMON_CH;\n\t\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t} else\n#endif /* CONFIG_CONCURRENT_MODE */\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tu8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0;\n\t\t\t\t\t\t\tattr_contentlen = 0;\n\n\t\t\t\t\t\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen))\n\t\t\t\t\t\t\t\tpeer_operating_ch = operatingch_info[4];\n\n\t\t\t\t\t\t\tif (rtw_p2p_is_channel_list_ok(peer_operating_ch,\n\t\t\t\t\t\t\t\tch_list_inclusioned, ch_num_inclusioned)) {\n\t\t\t\t\t\t\t\t/**\n\t\t\t\t\t\t\t\t *\tChange our operating channel as peer's for compatibility.\n\t\t\t\t\t\t\t\t */\n\t\t\t\t\t\t\t\tpwdinfo->operating_channel = peer_operating_ch;\n\t\t\t\t\t\t\t\tRTW_INFO(\"[%s] Change op ch to %02x as peer's\\n\", __FUNCTION__, pwdinfo->operating_channel);\n\t\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t\t/* Take first channel of ch_list_inclusioned as operating channel */\n\t\t\t\t\t\t\t\tpwdinfo->operating_channel = ch_list_inclusioned[0];\n\t\t\t\t\t\t\t\tRTW_INFO(\"[%s] Change op ch to %02x\\n\", __FUNCTION__, pwdinfo->operating_channel);\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t} else\n\t\t\t\tRTW_INFO(\"[%s] channel list attribute not found!\\n\", __FUNCTION__);\n\n\t\t\t/*\tTry to get the group id information if peer is GO */\n\t\t\tattr_contentlen = 0;\n\t\t\t_rtw_memset(groupid, 0x00, 38);\n\t\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) {\n\t\t\t\t_rtw_memcpy(pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN);\n\t\t\t\t_rtw_memcpy(pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN);\n\t\t\t}\n\n\t\t\t/* Get the next P2P IE */\n\t\t\tp2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);\n\t\t}\n\n\t}\n\n#ifdef CONFIG_WFD\n\trtw_process_wfd_ies(padapter, pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, __func__);\n#endif\n\n\treturn result ;\n\n}\n\nu8 process_p2p_group_negotation_confirm(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)\n{\n#ifdef CONFIG_CONCURRENT_MODE\n\t_adapter *padapter = pwdinfo->padapter;\n#endif\n\tu8 *ies;\n\tu32 ies_len;\n\tu8 *p2p_ie;\n\tu32\tp2p_ielen = 0;\n\tu8\tresult = P2P_STATUS_SUCCESS;\n\ties = pframe + _PUBLIC_ACTION_IE_OFFSET_;\n\ties_len = len - _PUBLIC_ACTION_IE_OFFSET_;\n\n\tp2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);\n\twhile (p2p_ie) {\t/*\tFound the P2P IE. */\n\t\tu8\tattr_content = 0x00, operatingch_info[5] = { 0x00 };\n\t\tu8\tgroupid[38] = { 0x00 };\n\t\tu32\tattr_contentlen = 0;\n\n\t\tpwdinfo->negotiation_dialog_token = 1;\n\t\trtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen);\n\t\tif (attr_contentlen == 1) {\n\t\t\tRTW_INFO(\"[%s] Status = %d\\n\", __FUNCTION__, attr_content);\n\t\t\tresult = attr_content;\n\n\t\t\tif (attr_content == P2P_STATUS_SUCCESS) {\n\n\t\t\t\t_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);\n\n\t\t\t\t/*\tCommented by Albert 20100911 */\n\t\t\t\t/*\tTodo: Need to handle the case which both Intents are the same. */\n\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);\n\t\t\t\trtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);\n\t\t\t\tif ((pwdinfo->intent) > (pwdinfo->peer_intent >> 1))\n\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);\n\t\t\t\telse if ((pwdinfo->intent) < (pwdinfo->peer_intent >> 1))\n\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);\n\t\t\t\telse {\n\t\t\t\t\t/*\tHave to compare the Tie Breaker */\n\t\t\t\t\tif (pwdinfo->peer_intent & 0x01)\n\t\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);\n\t\t\t\t\telse\n\t\t\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);\n\t\t\t\t}\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t\t\t\tif (rtw_mi_check_status(padapter, MI_LINKED)\n\t\t\t\t    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {\n\t\t\t\t\t/*\tSwitch back to the AP channel soon. */\n\t\t\t\t\t_set_timer(&pwdinfo->ap_p2p_switch_timer, 100);\n\t\t\t\t}\n#endif\n\t\t\t} else {\n\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);\n\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\t/*\tTry to get the group id information */\n\t\tattr_contentlen = 0;\n\t\t_rtw_memset(groupid, 0x00, 38);\n\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) {\n\t\t\tRTW_INFO(\"[%s] Ssid = %s, ssidlen = %zu\\n\", __FUNCTION__, &groupid[ETH_ALEN], strlen(&groupid[ETH_ALEN]));\n\t\t\t_rtw_memcpy(pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN);\n\t\t\t_rtw_memcpy(pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN);\n\t\t}\n\n\t\tattr_contentlen = 0;\n\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) {\n\t\t\tRTW_INFO(\"[%s] Peer's operating channel = %d\\n\", __FUNCTION__, operatingch_info[4]);\n\t\t\tpwdinfo->peer_operating_ch = operatingch_info[4];\n\t\t}\n\n\t\t/* Get the next P2P IE */\n\t\tp2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);\n\n\t}\n\n\treturn result ;\n}\n\nu8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)\n{\n\tu8 *frame_body;\n\tu8 dialogToken = 0;\n\tu8 status = P2P_STATUS_SUCCESS;\n\n\tframe_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));\n\n\tdialogToken = frame_body[6];\n\n\t/* todo: check NoA attribute */\n\n\tissue_p2p_presence_resp(pwdinfo, get_addr2_ptr(pframe), status, dialogToken);\n\n\treturn _TRUE;\n}\n\nvoid find_phase_handler(_adapter\t*padapter)\n{\n\tstruct wifidirect_info  *pwdinfo = &padapter->wdinfo;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct sitesurvey_parm parm;\n\t_irqL\t\t\t\tirqL;\n\tu8\t\t\t\t\t_status = 0;\n\n\n\trtw_init_sitesurvey_parm(padapter, &parm);\n\t_rtw_memcpy(&parm.ssid[0].Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN);\n\tparm.ssid[0].SsidLength = P2P_WILDCARD_SSID_LEN;\n\tparm.ssid_num = 1;\n\n\trtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\t_status = rtw_sitesurvey_cmd(padapter, &parm);\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\n\n}\n\nvoid p2p_concurrent_handler(_adapter *padapter);\n\nvoid restore_p2p_state_handler(_adapter\t*padapter)\n{\n\tstruct wifidirect_info  *pwdinfo = &padapter->wdinfo;\n\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL))\n\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_check_status(padapter, MI_LINKED)) {\n\t\tu8 union_ch = rtw_mi_get_union_chan(padapter);\n\t\tu8 union_bw = rtw_mi_get_union_bw(padapter);\n\t\tu8 union_offset = rtw_mi_get_union_offset(padapter);\n\n\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP)) {\n\t\t\tset_channel_bwmode(padapter, union_ch, union_offset, union_bw);\n\t\t\trtw_back_opch(padapter);\n\t\t}\n\t}\n#endif\n\n\trtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));\n\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) {\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tp2p_concurrent_handler(padapter);\n#else\n\t\t/*\tIn the P2P client mode, the driver should not switch back to its listen channel */\n\t\t/*\tbecause this P2P client should stay at the operating channel of P2P GO. */\n\t\tset_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n#endif\n\t}\n}\n\nvoid pre_tx_invitereq_handler(_adapter\t*padapter)\n{\n\tstruct wifidirect_info  *pwdinfo = &padapter->wdinfo;\n\tu8\tval8 = 1;\n\n\tset_channel_bwmode(padapter, pwdinfo->invitereq_info.peer_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));\n\tissue_probereq_p2p(padapter, NULL);\n\t_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);\n\n}\n\nvoid pre_tx_provdisc_handler(_adapter\t*padapter)\n{\n\tstruct wifidirect_info  *pwdinfo = &padapter->wdinfo;\n\tu8\tval8 = 1;\n\n\tset_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));\n\tissue_probereq_p2p(padapter, NULL);\n\t_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);\n\n}\n\nvoid pre_tx_negoreq_handler(_adapter\t*padapter)\n{\n\tstruct wifidirect_info  *pwdinfo = &padapter->wdinfo;\n\tu8\tval8 = 1;\n\n\tset_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));\n\tissue_probereq_p2p(padapter , NULL);\n\t/* WIN Phone only accept unicast probe request when nego back */\n\tissue_probereq_p2p(padapter , pwdinfo->nego_req_info.peerDevAddr);\n\t_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);\n\n}\n\n#ifdef CONFIG_CONCURRENT_MODE\nvoid p2p_concurrent_handler(_adapter\t*padapter)\n{\n\tstruct wifidirect_info\t*pwdinfo = &padapter->wdinfo;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8\t\t\t\t\tval8;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (pwdinfo->driver_interface == DRIVER_CFG80211\n\t\t&& !rtw_cfg80211_get_is_roch(padapter))\n\t\treturn;\n#endif\n\n\tif (rtw_mi_check_status(padapter, MI_LINKED)) {\n\t\tu8 union_ch = rtw_mi_get_union_chan(padapter);\n\t\tu8 union_bw = rtw_mi_get_union_bw(padapter);\n\t\tu8 union_offset = rtw_mi_get_union_offset(padapter);\n\n\t\tpwdinfo->operating_channel = union_ch;\n\n\t\tif (pwdinfo->driver_interface == DRIVER_CFG80211) {\n\t\t\tRTW_INFO(\"%s, switch ch back to union=%u,%u, %u\\n\"\n\t\t\t\t, __func__, union_ch, union_bw, union_offset);\n\t\t\tset_channel_bwmode(padapter, union_ch, union_offset, union_bw);\n\t\t\trtw_back_opch(padapter);\n\n\t\t} else if (pwdinfo->driver_interface == DRIVER_WEXT) {\n\t\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) {\n\t\t\t\t/*\tNow, the driver stays on the AP's channel. */\n\t\t\t\t/*\tIf the pwdinfo->ext_listen_period = 0, that means the P2P listen state is not available on listen channel. */\n\t\t\t\tif (pwdinfo->ext_listen_period > 0) {\n\t\t\t\t\tRTW_INFO(\"[%s] P2P_STATE_IDLE, ext_listen_period = %d\\n\", __FUNCTION__, pwdinfo->ext_listen_period);\n\n\t\t\t\t\tif (union_ch != pwdinfo->listen_channel) {\n\t\t\t\t\t\trtw_leave_opch(padapter);\n\t\t\t\t\t\tset_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n\t\t\t\t\t}\n\n\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);\n\n\t\t\t\t\tif (!rtw_mi_check_mlmeinfo_state(padapter, WIFI_FW_AP_STATE)) {\n\t\t\t\t\t\tval8 = 1;\n\t\t\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));\n\t\t\t\t\t}\n\t\t\t\t\t/*\tTodo: To check the value of pwdinfo->ext_listen_period is equal to 0 or not. */\n\t\t\t\t\t_set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_period);\n\t\t\t\t}\n\n\t\t\t} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) ||\n\t\t\t\trtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL) ||\n\t\t\t\t(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) && pwdinfo->nego_req_info.benable == _FALSE) ||\n\t\t\t\trtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ)) {\n\t\t\t\t/*\tNow, the driver is in the listen state of P2P mode. */\n\t\t\t\tRTW_INFO(\"[%s] P2P_STATE_IDLE, ext_listen_interval = %d\\n\", __FUNCTION__, pwdinfo->ext_listen_interval);\n\n\t\t\t\t/*\tCommented by Albert 2012/11/01 */\n\t\t\t\t/*\tIf the AP's channel is the same as the listen channel, we should still be in the listen state */\n\t\t\t\t/*\tOther P2P device is still able to find this device out even this device is in the AP's channel. */\n\t\t\t\t/*\tSo, configure this device to be able to receive the probe request frame and set it to listen state. */\n\t\t\t\tif (union_ch != pwdinfo->listen_channel) {\n\n\t\t\t\t\tset_channel_bwmode(padapter, union_ch, union_offset, union_bw);\n\t\t\t\t\tif (!rtw_mi_check_status(padapter, MI_AP_MODE)) {\n\t\t\t\t\t\tval8 = 0;\n\t\t\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));\n\t\t\t\t\t}\n\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE);\n\t\t\t\t\trtw_back_opch(padapter);\n\t\t\t\t}\n\n\t\t\t\t/*\tTodo: To check the value of pwdinfo->ext_listen_interval is equal to 0 or not. */\n\t\t\t\t_set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_interval);\n\n\t\t\t} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK)) {\n\t\t\t\t/*\tThe driver had finished the P2P handshake successfully. */\n\t\t\t\tval8 = 0;\n\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));\n\t\t\t\tset_channel_bwmode(padapter, union_ch, union_offset, union_bw);\n\t\t\t\trtw_back_opch(padapter);\n\n\t\t\t} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) {\n\t\t\t\tval8 = 1;\n\t\t\t\tset_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));\n\t\t\t\tissue_probereq_p2p(padapter, NULL);\n\t\t\t\t_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);\n\t\t\t} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) && pwdinfo->nego_req_info.benable == _TRUE) {\n\t\t\t\tval8 = 1;\n\t\t\t\tset_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));\n\t\t\t\tissue_probereq_p2p(padapter, NULL);\n\t\t\t\t_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);\n\t\t\t} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ) && pwdinfo->invitereq_info.benable == _TRUE) {\n\t\t\t\t/*\n\t\t\t\tval8 = 1;\n\t\t\t\tset_channel_bwmode(padapter, , HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));\n\t\t\t\tissue_probereq_p2p(padapter, NULL);\n\t\t\t\t_set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT );\n\t\t\t\t*/\n\t\t\t}\n\t\t}\n\t} else {\n\t\t/* In p2p+softap. When in P2P_STATE_GONEGO_OK, not back to listen channel.*/\n\t\tif (!rtw_p2p_chk_state(pwdinfo , P2P_STATE_GONEGO_OK) || padapter->registrypriv.full_ch_in_p2p_handshake == 0)\n\t\t\tset_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n\t\telse\n\t\t\tRTW_INFO(\"%s, buddy not linked, go nego ok, not back to listen channel\\n\", __func__);\n\t}\n\n}\n#endif\n\n#ifdef CONFIG_IOCTL_CFG80211\nu8 roch_stay_in_cur_chan(_adapter *padapter)\n{\n\tint i;\n\t_adapter *iface;\n\tstruct mlme_priv *pmlmepriv;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tu8 rst = _FALSE;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface) {\n\t\t\tpmlmepriv = &iface->mlmepriv;\n\n\t\t\tif (check_fwstate(pmlmepriv, _FW_UNDER_LINKING | WIFI_UNDER_WPS | WIFI_UNDER_KEY_HANDSHAKE) == _TRUE) {\n\t\t\t\tRTW_INFO(ADPT_FMT\"- _FW_UNDER_LINKING |WIFI_UNDER_WPS | WIFI_UNDER_KEY_HANDSHAKE (mlme state:0x%x)\\n\",\n\t\t\t\t\t\tADPT_ARG(iface), get_fwstate(&iface->mlmepriv));\n\t\t\t\trst = _TRUE;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\t#ifdef CONFIG_AP_MODE\n\t\t\tif (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) {\n\t\t\t\tif (rtw_ap_sta_states_check(iface) == _TRUE) {\n\t\t\t\t\trst = _TRUE;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\t#endif\n\t\t}\n\t}\n\n\treturn rst;\n}\n\nstatic int ro_ch_handler(_adapter *adapter, u8 *buf)\n{\n\tint ret = H2C_SUCCESS;\n\tstruct p2p_roch_parm *roch_parm = (struct p2p_roch_parm *)buf;\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);\n\tstruct cfg80211_wifidirect_info *pcfg80211_wdinfo = &adapter->cfg80211_wdinfo;\n#ifdef CONFIG_CONCURRENT_MODE\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n#ifdef RTW_ROCH_BACK_OP\n\tstruct wifidirect_info *pwdinfo = &adapter->wdinfo;\n#endif\n#endif\n\tu8 ready_on_channel = _FALSE;\n\tu8 remain_ch;\n\tunsigned int duration;\n\n\t_enter_critical_mutex(&pwdev_priv->roch_mutex, NULL);\n\n\tif (rtw_cfg80211_get_is_roch(adapter) != _TRUE)\n\t\tgoto exit;\n\n\tremain_ch = (u8)ieee80211_frequency_to_channel(roch_parm->ch.center_freq);\n\tduration = roch_parm->duration;\n\n\tRTW_INFO(FUNC_ADPT_FMT\" ch:%u duration:%d, cookie:0x%llx\\n\"\n\t\t, FUNC_ADPT_ARG(adapter), remain_ch, roch_parm->duration, roch_parm->cookie);\n\n\tif (roch_parm->wdev && roch_parm->cookie) {\n\t\tif (pcfg80211_wdinfo->ro_ch_wdev != roch_parm->wdev) {\n\t\t\tRTW_WARN(FUNC_ADPT_FMT\" ongoing wdev:%p, wdev:%p\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), pcfg80211_wdinfo->ro_ch_wdev, roch_parm->wdev);\n\t\t\trtw_warn_on(1);\n\t\t}\n\n\t\tif (pcfg80211_wdinfo->remain_on_ch_cookie != roch_parm->cookie) {\n\t\t\tRTW_WARN(FUNC_ADPT_FMT\" ongoing cookie:0x%llx, cookie:0x%llx\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), pcfg80211_wdinfo->remain_on_ch_cookie, roch_parm->cookie);\n\t\t\trtw_warn_on(1);\n\t\t}\n\t}\n\n\tif (roch_stay_in_cur_chan(adapter) == _TRUE) {\n\t\tremain_ch = rtw_mi_get_union_chan(adapter);\n\t\tRTW_INFO(FUNC_ADPT_FMT\" stay in union ch:%d\\n\", FUNC_ADPT_ARG(adapter), remain_ch);\n\t}\n\n\t#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_check_status(adapter, MI_LINKED) && (0 != rtw_mi_get_union_chan(adapter))) {\n\t\tif ((remain_ch != rtw_mi_get_union_chan(adapter)) && !check_fwstate(&adapter->mlmepriv, _FW_LINKED)) {\n\t\t\tif (remain_ch != pmlmeext->cur_channel\n\t\t\t\t#ifdef RTW_ROCH_BACK_OP\n\t\t\t\t|| ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1\n\t\t\t\t#endif\n\t\t\t) {\n\t\t\t\trtw_leave_opch(adapter);\n\n\t\t\t\t#ifdef RTW_ROCH_BACK_OP\n\t\t\t\tRTW_INFO(\"%s, set switch ch timer, duration=%d\\n\", __func__, duration - pwdinfo->ext_listen_interval);\n\t\t\t\tATOMIC_SET(&pwdev_priv->switch_ch_to, 0);\n\t\t\t\t_set_timer(&pwdinfo->ap_p2p_switch_timer, duration - pwdinfo->ext_listen_interval);\n\t\t\t\t#endif\n\t\t\t}\n\t\t}\n\t\tready_on_channel = _TRUE;\n\t} else\n\t#endif /* CONFIG_CONCURRENT_MODE */\n\t{\n\t\tif (remain_ch != rtw_get_oper_ch(adapter))\n\t\t\tready_on_channel = _TRUE;\n\t}\n\n\tif (ready_on_channel == _TRUE) {\n\t\t#ifndef RTW_SINGLE_WIPHY\n\t\tif (!check_fwstate(&adapter->mlmepriv, _FW_LINKED))\n\t\t#endif\n\t\t{\n\t\t\t#ifdef CONFIG_CONCURRENT_MODE\n\t\t\tif (rtw_get_oper_ch(adapter) != remain_ch)\n\t\t\t#endif\n\t\t\t{\n\t\t\t\t/* if (!padapter->mlmepriv.LinkDetectInfo.bBusyTraffic) */\n\t\t\t\tset_channel_bwmode(adapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n\t\t\t}\n\t\t}\n\t}\n\n\t#ifdef CONFIG_BT_COEXIST\n\trtw_btcoex_ScanNotify(adapter, _TRUE);\n\t#endif\n\n\tRTW_INFO(\"%s, set ro ch timer, duration=%d\\n\", __func__, duration);\n\t_set_timer(&pcfg80211_wdinfo->remain_on_ch_timer, duration);\n\nexit:\n\t_exit_critical_mutex(&pwdev_priv->roch_mutex, NULL);\n\n\treturn ret;\n}\n\nstatic int cancel_ro_ch_handler(_adapter *padapter, u8 *buf)\n{\n\tint ret = H2C_SUCCESS;\n\tstruct p2p_roch_parm *roch_parm = (struct p2p_roch_parm *)buf;\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n\tstruct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;\n\tstruct wireless_dev *wdev;\n\tstruct wifidirect_info *pwdinfo = &padapter->wdinfo;\n\tu8 ch, bw, offset;\n\n\t_enter_critical_mutex(&pwdev_priv->roch_mutex, NULL);\n\n\tif (rtw_cfg80211_get_is_roch(padapter) != _TRUE)\n\t\tgoto exit;\n\n\tif (roch_parm->wdev && roch_parm->cookie) {\n\t\tif (pcfg80211_wdinfo->ro_ch_wdev != roch_parm->wdev) {\n\t\t\tRTW_WARN(FUNC_ADPT_FMT\" ongoing wdev:%p, wdev:%p\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter), pcfg80211_wdinfo->ro_ch_wdev, roch_parm->wdev);\n\t\t\trtw_warn_on(1);\n\t\t}\n\n\t\tif (pcfg80211_wdinfo->remain_on_ch_cookie != roch_parm->cookie) {\n\t\t\tRTW_WARN(FUNC_ADPT_FMT\" ongoing cookie:0x%llx, cookie:0x%llx\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter), pcfg80211_wdinfo->remain_on_ch_cookie, roch_parm->cookie);\n\t\t\trtw_warn_on(1);\n\t\t}\n\t}\n\n#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE)\n\t_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);\n\tATOMIC_SET(&pwdev_priv->switch_ch_to, 1);\n#endif\n\n\tif (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) {\n\t\tif (0)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" back to linked/linking union - ch:%u, bw:%u, offset:%u\\n\",\n\t\t\t\t FUNC_ADPT_ARG(padapter), ch, bw, offset);\n\t} else if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->listen_channel) {\n\t\tch = pwdinfo->listen_channel;\n\t\tbw = CHANNEL_WIDTH_20;\n\t\toffset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tif (0)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" back to listen ch - ch:%u, bw:%u, offset:%u\\n\",\n\t\t\t\t FUNC_ADPT_ARG(padapter), ch, bw, offset);\n\t} else {\n\t\tch = pcfg80211_wdinfo->restore_channel;\n\t\tbw = CHANNEL_WIDTH_20;\n\t\toffset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tif (0)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" back to restore ch - ch:%u, bw:%u, offset:%u\\n\",\n\t\t\t\t FUNC_ADPT_ARG(padapter), ch, bw, offset);\n\t}\n\n\tset_channel_bwmode(padapter, ch, offset, bw);\n\trtw_back_opch(padapter);\n\n\trtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));\n#ifdef CONFIG_DEBUG_CFG80211\n\tRTW_INFO(\"%s, role=%d, p2p_state=%d\\n\", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));\n#endif\n\n\twdev = pcfg80211_wdinfo->ro_ch_wdev;\n\n\trtw_cfg80211_set_is_roch(padapter, _FALSE);\n\tpcfg80211_wdinfo->ro_ch_wdev = NULL;\n\trtw_cfg80211_set_last_ro_ch_time(padapter);\n\n\trtw_cfg80211_remain_on_channel_expired(wdev\n\t\t, pcfg80211_wdinfo->remain_on_ch_cookie\n\t\t, &pcfg80211_wdinfo->remain_on_ch_channel\n\t\t, pcfg80211_wdinfo->remain_on_ch_type, GFP_KERNEL);\n\n\tRTW_INFO(\"cfg80211_remain_on_channel_expired cookie:0x%llx\\n\"\n\t\t, pcfg80211_wdinfo->remain_on_ch_cookie);\n\n#ifdef CONFIG_BT_COEXIST\n\trtw_btcoex_ScanNotify(padapter, _FALSE);\n#endif\n\nexit:\n\t_exit_critical_mutex(&pwdev_priv->roch_mutex, NULL);\n\n\treturn ret;\n}\n\nstatic void ro_ch_timer_process(void *FunctionContext)\n{\n\t_adapter *adapter = (_adapter *)FunctionContext;\n\n\tp2p_cancel_roch_cmd(adapter, 0, NULL, 0);\n}\n\n#if 0\nstatic void rtw_change_p2pie_op_ch(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch)\n{\n\tu8 *ies, *p2p_ie;\n\tu32 ies_len, p2p_ielen;\n\n#ifdef CONFIG_MCC_MODE\n\tif (MCC_EN(padapter))\n\t\treturn;\n#endif /* CONFIG_MCC_MODE */\n\n\ties = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);\n\ties_len = len - _PUBLIC_ACTION_IE_OFFSET_;\n\n\tp2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);\n\n\twhile (p2p_ie) {\n\t\tu32\tattr_contentlen = 0;\n\t\tu8 *pattr = NULL;\n\n\t\t/* Check P2P_ATTR_OPERATING_CH */\n\t\tattr_contentlen = 0;\n\t\tpattr = NULL;\n\t\tpattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint *)&attr_contentlen);\n\t\tif (pattr != NULL)\n\t\t\t*(pattr + 4) = ch;\n\n\t\t/* Get the next P2P IE */\n\t\tp2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);\n\t}\n}\n#endif\n\n#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)\nstatic void rtw_change_p2pie_ch_list(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch)\n{\n\tu8 *ies, *p2p_ie;\n\tu32 ies_len, p2p_ielen;\n\n#ifdef CONFIG_MCC_MODE\n\tif (MCC_EN(padapter))\n\t\treturn;\n#endif /* CONFIG_MCC_MODE */\n\n\ties = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);\n\ties_len = len - _PUBLIC_ACTION_IE_OFFSET_;\n\n\tp2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);\n\n\twhile (p2p_ie) {\n\t\tu32\tattr_contentlen = 0;\n\t\tu8 *pattr = NULL;\n\n\t\t/* Check P2P_ATTR_CH_LIST */\n\t\tpattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint *)&attr_contentlen);\n\t\tif (pattr != NULL) {\n\t\t\tint i;\n\t\t\tu32 num_of_ch;\n\t\t\tu8 *pattr_temp = pattr + 3 ;\n\n\t\t\tattr_contentlen -= 3;\n\n\t\t\twhile (attr_contentlen > 0) {\n\t\t\t\tnum_of_ch = *(pattr_temp + 1);\n\n\t\t\t\tfor (i = 0; i < num_of_ch; i++)\n\t\t\t\t\t*(pattr_temp + 2 + i) = ch;\n\n\t\t\t\tpattr_temp += (2 + num_of_ch);\n\t\t\t\tattr_contentlen -= (2 + num_of_ch);\n\t\t\t}\n\t\t}\n\n\t\t/* Get the next P2P IE */\n\t\tp2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);\n\t}\n}\n#endif\n\n#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)\nstatic bool rtw_chk_p2pie_ch_list_with_buddy(_adapter *padapter, const u8 *frame_body, u32 len)\n{\n\tbool fit = _FALSE;\n\tu8 *ies, *p2p_ie;\n\tu32 ies_len, p2p_ielen;\n\tu8 union_ch = rtw_mi_get_union_chan(padapter);\n\n\ties = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);\n\ties_len = len - _PUBLIC_ACTION_IE_OFFSET_;\n\n\tp2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);\n\n\twhile (p2p_ie) {\n\t\tu32\tattr_contentlen = 0;\n\t\tu8 *pattr = NULL;\n\n\t\t/* Check P2P_ATTR_CH_LIST */\n\t\tpattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint *)&attr_contentlen);\n\t\tif (pattr != NULL) {\n\t\t\tint i;\n\t\t\tu32 num_of_ch;\n\t\t\tu8 *pattr_temp = pattr + 3 ;\n\n\t\t\tattr_contentlen -= 3;\n\n\t\t\twhile (attr_contentlen > 0) {\n\t\t\t\tnum_of_ch = *(pattr_temp + 1);\n\n\t\t\t\tfor (i = 0; i < num_of_ch; i++) {\n\t\t\t\t\tif (*(pattr_temp + 2 + i) == union_ch) {\n\t\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" ch_list fit buddy_ch:%u\\n\", FUNC_ADPT_ARG(padapter), union_ch);\n\t\t\t\t\t\tfit = _TRUE;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tpattr_temp += (2 + num_of_ch);\n\t\t\t\tattr_contentlen -= (2 + num_of_ch);\n\t\t\t}\n\t\t}\n\n\t\t/* Get the next P2P IE */\n\t\tp2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);\n\t}\n\n\treturn fit;\n}\n\n#if defined(CONFIG_P2P_INVITE_IOT)\nstatic bool rtw_chk_p2pie_op_ch_with_buddy(_adapter *padapter, const u8 *frame_body, u32 len)\n{\n\tbool fit = _FALSE;\n\tu8 *ies, *p2p_ie;\n\tu32 ies_len, p2p_ielen;\n\tu8 union_ch = rtw_mi_get_union_chan(padapter);\n\n\ties = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);\n\ties_len = len - _PUBLIC_ACTION_IE_OFFSET_;\n\n\tp2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);\n\n\twhile (p2p_ie) {\n\t\tu32\tattr_contentlen = 0;\n\t\tu8 *pattr = NULL;\n\n\t\t/* Check P2P_ATTR_OPERATING_CH */\n\t\tattr_contentlen = 0;\n\t\tpattr = NULL;\n\t\tpattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint *)&attr_contentlen);\n\t\tif (pattr != NULL) {\n\t\t\tif (*(pattr + 4) == union_ch) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" op_ch fit buddy_ch:%u\\n\", FUNC_ADPT_ARG(padapter), union_ch);\n\t\t\t\tfit = _TRUE;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\t/* Get the next P2P IE */\n\t\tp2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);\n\t}\n\n\treturn fit;\n}\n#endif\n\nstatic void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *frame_body, u32 len)\n{\n\tu8 *ies, *p2p_ie;\n\tu32 ies_len, p2p_ielen;\n\tu8 union_ch = rtw_mi_get_union_chan(padapter);\n\n#ifdef CONFIG_MCC_MODE\n\tif (MCC_EN(padapter))\n\t\treturn;\n#endif /* CONFIG_MCC_MODE */\n\n\ties = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);\n\ties_len = len - _PUBLIC_ACTION_IE_OFFSET_;\n\n\tp2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);\n\n\twhile (p2p_ie) {\n\t\tu32\tattr_contentlen = 0;\n\t\tu8 *pattr = NULL;\n\n\t\t/* Check P2P_ATTR_CH_LIST */\n\t\tpattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint *)&attr_contentlen);\n\t\tif (pattr != NULL) {\n\t\t\tint i;\n\t\t\tu32 num_of_ch;\n\t\t\tu8 *pattr_temp = pattr + 3 ;\n\n\t\t\tattr_contentlen -= 3;\n\n\t\t\twhile (attr_contentlen > 0) {\n\t\t\t\tnum_of_ch = *(pattr_temp + 1);\n\n\t\t\t\tfor (i = 0; i < num_of_ch; i++) {\n\t\t\t\t\tif (*(pattr_temp + 2 + i) && *(pattr_temp + 2 + i) != union_ch) {\n\t\t\t\t\t\t#ifdef RTW_SINGLE_WIPHY\n\t\t\t\t\t\tRTW_ERR(\"replace ch_list:%u with:%u\\n\", *(pattr_temp + 2 + i), union_ch);\n\t\t\t\t\t\t#endif\n\t\t\t\t\t\t*(pattr_temp + 2 + i) = union_ch; /*forcing to the same channel*/\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tpattr_temp += (2 + num_of_ch);\n\t\t\t\tattr_contentlen -= (2 + num_of_ch);\n\t\t\t}\n\t\t}\n\n\t\t/* Check P2P_ATTR_OPERATING_CH */\n\t\tattr_contentlen = 0;\n\t\tpattr = NULL;\n\t\tpattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint *)&attr_contentlen);\n\t\tif (pattr != NULL) {\n\t\t\tif (*(pattr + 4) && *(pattr + 4) != union_ch) {\n\t\t\t\t#ifdef RTW_SINGLE_WIPHY\n\t\t\t\tRTW_ERR(\"replace op_ch:%u with:%u\\n\", *(pattr + 4), union_ch);\n\t\t\t\t#endif\n\t\t\t\t*(pattr + 4) = union_ch; /*forcing to the same channel\t*/\n\t\t\t}\n\t\t}\n\n\t\t/* Get the next P2P IE */\n\t\tp2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);\n\n\t}\n\n}\n#endif\n\n#ifdef CONFIG_WFD\nu32 rtw_xframe_build_wfd_ie(struct xmit_frame *xframe)\n{\n\t_adapter *adapter = xframe->padapter;\n\tstruct wifidirect_info *wdinfo = &adapter->wdinfo;\n\tu8 *frame = xframe->buf_addr + TXDESC_OFFSET;\n\tu8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr);\n\tu8 *frame_tail = frame + xframe->attrib.pktlen;\n\tu8 category, action, OUI_Subtype, dialogToken = 0;\n\tu32\twfdielen = 0;\n\n\tcategory = frame_body[0];\n\tif (category == RTW_WLAN_CATEGORY_PUBLIC) {\n\t\taction = frame_body[1];\n\t\tif (action == ACT_PUBLIC_VENDOR\n\t\t    && _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE\n\t\t   ) {\n\t\t\tOUI_Subtype = frame_body[6];\n\t\t\tdialogToken = frame_body[7];\n\n\t\t\tswitch (OUI_Subtype) {\n\t\t\tcase P2P_GO_NEGO_REQ:\n\t\t\t\twfdielen = build_nego_req_wfd_ie(wdinfo, frame_tail);\n\t\t\t\tbreak;\n\t\t\tcase P2P_GO_NEGO_RESP:\n\t\t\t\twfdielen = build_nego_resp_wfd_ie(wdinfo, frame_tail);\n\t\t\t\tbreak;\n\t\t\tcase P2P_GO_NEGO_CONF:\n\t\t\t\twfdielen = build_nego_confirm_wfd_ie(wdinfo, frame_tail);\n\t\t\t\tbreak;\n\t\t\tcase P2P_INVIT_REQ:\n\t\t\t\twfdielen = build_invitation_req_wfd_ie(wdinfo, frame_tail);\n\t\t\t\tbreak;\n\t\t\tcase P2P_INVIT_RESP:\n\t\t\t\twfdielen = build_invitation_resp_wfd_ie(wdinfo, frame_tail);\n\t\t\t\tbreak;\n\t\t\tcase P2P_PROVISION_DISC_REQ:\n\t\t\t\twfdielen = build_provdisc_req_wfd_ie(wdinfo, frame_tail);\n\t\t\t\tbreak;\n\t\t\tcase P2P_PROVISION_DISC_RESP:\n\t\t\t\twfdielen = build_provdisc_resp_wfd_ie(wdinfo, frame_tail);\n\t\t\t\tbreak;\n\t\t\tcase P2P_DEVDISC_REQ:\n\t\t\tcase P2P_DEVDISC_RESP:\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t}\n\t} else if (category == RTW_WLAN_CATEGORY_P2P) {\n\t\tOUI_Subtype = frame_body[5];\n\t\tdialogToken = frame_body[6];\n\n#ifdef CONFIG_DEBUG_CFG80211\n\t\tRTW_INFO(\"ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\\n\"\n\t\t\t, cpu_to_be32(*((u32 *)(frame_body + 1))), OUI_Subtype, dialogToken);\n#endif\n\n\t\tswitch (OUI_Subtype) {\n\t\tcase P2P_NOTICE_OF_ABSENCE:\n\t\t\tbreak;\n\t\tcase P2P_PRESENCE_REQUEST:\n\t\t\tbreak;\n\t\tcase P2P_PRESENCE_RESPONSE:\n\t\t\tbreak;\n\t\tcase P2P_GO_DISC_REQUEST:\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t} else\n\t\tRTW_INFO(\"%s, action frame category=%d\\n\", __func__, category);\n\n\txframe->attrib.pktlen += wfdielen;\n\n\treturn wfdielen;\n}\n#endif /* CONFIG_WFD */\n\nbool rtw_xframe_del_wfd_ie(struct xmit_frame *xframe)\n{\n#define DBG_XFRAME_DEL_WFD_IE 0\n\tu8 *frame = xframe->buf_addr + TXDESC_OFFSET;\n\tu8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr);\n\tu8 *frame_tail = frame + xframe->attrib.pktlen;\n\tu8 category, action, OUI_Subtype;\n\tu8 *ies = NULL;\n\tuint ies_len_ori = 0;\n\tuint ies_len = 0;\n\n\tcategory = frame_body[0];\n\tif (category == RTW_WLAN_CATEGORY_PUBLIC) {\n\t\taction = frame_body[1];\n\t\tif (action == ACT_PUBLIC_VENDOR\n\t\t    && _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE\n\t\t   ) {\n\t\t\tOUI_Subtype = frame_body[6];\n\n\t\t\tswitch (OUI_Subtype) {\n\t\t\tcase P2P_GO_NEGO_REQ:\n\t\t\tcase P2P_GO_NEGO_RESP:\n\t\t\tcase P2P_GO_NEGO_CONF:\n\t\t\tcase P2P_INVIT_REQ:\n\t\t\tcase P2P_INVIT_RESP:\n\t\t\tcase P2P_PROVISION_DISC_REQ:\n\t\t\tcase P2P_PROVISION_DISC_RESP:\n\t\t\t\ties = frame_body + 8;\n\t\t\t\ties_len_ori = frame_tail - (frame_body + 8);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (ies && ies_len_ori) {\n\t\ties_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_XFRAME_DEL_WFD_IE ? __func__ : NULL);\n\t\txframe->attrib.pktlen -= (ies_len_ori - ies_len);\n\t}\n\n\treturn ies_len_ori != ies_len;\n}\n\n/*\n* rtw_xframe_chk_wfd_ie -\n*\n*/\nvoid rtw_xframe_chk_wfd_ie(struct xmit_frame *xframe)\n{\n\t_adapter *adapter = xframe->padapter;\n#ifdef CONFIG_IOCTL_CFG80211\n\tstruct wifidirect_info *wdinfo = &adapter->wdinfo;\n#endif\n\tu8 build = 0;\n\tu8 del = 0;\n\n\tif (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))\n\t\tdel = 1;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (wdinfo->wfd_info->wfd_enable == _TRUE)\n#endif\n\t\tdel = build = 1;\n\n\tif (del)\n\t\trtw_xframe_del_wfd_ie(xframe);\n\n#ifdef CONFIG_WFD\n\tif (build)\n\t\trtw_xframe_build_wfd_ie(xframe);\n#endif\n}\n\nu8 *dump_p2p_attr_ch_list(u8 *p2p_ie, uint p2p_ielen, u8 *buf, u32 buf_len)\n{\n\tuint attr_contentlen = 0;\n\tu8 *pattr = NULL;\n\tint w_sz = 0;\n\tu8 ch_cnt = 0;\n\tu8 ch_list[40];\n\n\tpattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, &attr_contentlen);\n\tif (pattr != NULL) {\n\t\tint i, j;\n\t\tu32 num_of_ch;\n\t\tu8 *pattr_temp = pattr + 3 ;\n\n\t\tattr_contentlen -= 3;\n\n\t\t_rtw_memset(ch_list, 0, 40);\n\n\t\twhile (attr_contentlen > 0) {\n\t\t\tnum_of_ch = *(pattr_temp + 1);\n\n\t\t\tfor (i = 0; i < num_of_ch; i++) {\n\t\t\t\tfor (j = 0; j < ch_cnt; j++) {\n\t\t\t\t\tif (ch_list[j] == *(pattr_temp + 2 + i))\n\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tif (j >= ch_cnt)\n\t\t\t\t\tch_list[ch_cnt++] = *(pattr_temp + 2 + i);\n\n\t\t\t}\n\n\t\t\tpattr_temp += (2 + num_of_ch);\n\t\t\tattr_contentlen -= (2 + num_of_ch);\n\t\t}\n\n\t\tfor (j = 0; j < ch_cnt; j++) {\n\t\t\tif (j == 0)\n\t\t\t\tw_sz += snprintf(buf + w_sz, buf_len - w_sz, \"%u\", ch_list[j]);\n\t\t\telse if (ch_list[j] - ch_list[j - 1] != 1)\n\t\t\t\tw_sz += snprintf(buf + w_sz, buf_len - w_sz, \", %u\", ch_list[j]);\n\t\t\telse if (j != ch_cnt - 1 && ch_list[j + 1] - ch_list[j] == 1) {\n\t\t\t\t/* empty */\n\t\t\t} else\n\t\t\t\tw_sz += snprintf(buf + w_sz, buf_len - w_sz, \"-%u\", ch_list[j]);\n\t\t}\n\t}\n\treturn buf;\n}\n\n/*\n * return _TRUE if requester is GO, _FALSE if responder is GO\n */\nbool rtw_p2p_nego_intent_compare(u8 req, u8 resp)\n{\n\tif (req >> 1 == resp >> 1)\n\t\treturn  req & 0x01 ? _TRUE : _FALSE;\n\telse if (req >> 1 > resp >> 1)\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\n\nint rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)\n{\n\tint is_p2p_frame = (-1);\n\tunsigned char\t*frame_body;\n\tu8 category, action, OUI_Subtype, dialogToken = 0;\n\tu8 *p2p_ie = NULL;\n\tuint p2p_ielen = 0;\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n\tint status = -1;\n\tu8 ch_list_buf[128] = {'\\0'};\n\tint op_ch = -1;\n\tint listen_ch = -1;\n\tu8 intent = 0;\n\tu8 *iaddr = NULL;\n\tu8 *gbssid = NULL;\n\n\tframe_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr));\n\tcategory = frame_body[0];\n\t/* just for check */\n\tif (category == RTW_WLAN_CATEGORY_PUBLIC) {\n\t\taction = frame_body[1];\n\t\tif (action == ACT_PUBLIC_VENDOR\n\t\t\t&& _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE\n\t\t) {\n\t\t\tOUI_Subtype = frame_body[6];\n\t\t\tdialogToken = frame_body[7];\n\t\t\tis_p2p_frame = OUI_Subtype;\n\n\t\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\t\tRTW_INFO(\"ACTION_CATEGORY_PUBLIC: ACT_PUBLIC_VENDOR, OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\\n\",\n\t\t\t\tcpu_to_be32(*((u32 *)(frame_body + 2))), OUI_Subtype, dialogToken);\n\t\t\t#endif\n\n\t\t\tp2p_ie = rtw_get_p2p_ie(\n\t\t\t\t(u8 *)buf + sizeof(struct rtw_ieee80211_hdr_3addr) + _PUBLIC_ACTION_IE_OFFSET_\n\t\t\t\t, len - sizeof(struct rtw_ieee80211_hdr_3addr) - _PUBLIC_ACTION_IE_OFFSET_\n\t\t\t\t, NULL, &p2p_ielen);\n\n\t\t\tswitch (OUI_Subtype) { /* OUI Subtype */\n\t\t\t\tu8 *cont;\n\t\t\t\tuint cont_len;\n\t\t\tcase P2P_GO_NEGO_REQ: {\n\t\t\t\tstruct rtw_wdev_nego_info *nego_info = &pwdev_priv->nego_info;\n\n\t\t\t\tif (tx) {\n\t\t\t\t\t#ifdef CONFIG_DRV_ISSUE_PROV_REQ /* IOT FOR S2 */\n\t\t\t\t\tif (pwdev_priv->provdisc_req_issued == _FALSE)\n\t\t\t\t\t\trtw_cfg80211_issue_p2p_provision_request(padapter, buf, len);\n\t\t\t\t\t#endif /* CONFIG_DRV_ISSUE_PROV_REQ */\n\n\t\t\t\t\t/* pwdev_priv->provdisc_req_issued = _FALSE; */\n\n\t\t\t\t\t#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)\n\t\t\t\t\tif (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)\n\t\t\t\t\t\trtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));\n\t\t\t\t\t#endif\n\t\t\t\t}\n\n\t\t\t\tcont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);\n\t\t\t\tif (cont)\n\t\t\t\t\top_ch = *(cont + 4);\n\t\t\t\tcont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, NULL, &cont_len);\n\t\t\t\tif (cont)\n\t\t\t\t\tlisten_ch = *(cont + 4);\n\t\t\t\tcont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT, NULL, &cont_len);\n\t\t\t\tif (cont)\n\t\t\t\t\tintent = *cont;\n\t\t\t\tcont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, NULL, &cont_len);\n\t\t\t\tif (cont && cont_len == 6)\n\t\t\t\t\tiaddr = cont;\n\n\t\t\t\tif (nego_info->token != dialogToken)\n\t\t\t\t\trtw_wdev_nego_info_init(nego_info);\n\n\t\t\t\t_rtw_memcpy(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN);\n\t\t\t\tif (iaddr)\n\t\t\t\t\t_rtw_memcpy(tx ? nego_info->iface_addr : nego_info->peer_iface_addr, iaddr, ETH_ALEN);\n\t\t\t\tnego_info->active = tx ? 1 : 0;\n\t\t\t\tnego_info->token = dialogToken;\n\t\t\t\tnego_info->req_op_ch = op_ch;\n\t\t\t\tnego_info->req_listen_ch = listen_ch;\n\t\t\t\tnego_info->req_intent = intent;\n\t\t\t\tnego_info->state = 0;\n\n\t\t\t\tdump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);\n\t\t\t\tRTW_INFO(\"RTW_%s:P2P_GO_NEGO_REQ, dialogToken=%d, intent:%u%s, listen_ch:%d, op_ch:%d, ch_list:%s\"\n\t\t\t\t\t, (tx == _TRUE) ? \"Tx\" : \"Rx\" , dialogToken , (intent >> 1) , intent & 0x1 ? \"+\" : \"-\" , listen_ch , op_ch , ch_list_buf);\n\t\t\t\tif (iaddr)\n\t\t\t\t\t_RTW_INFO(\", iaddr:\"MAC_FMT, MAC_ARG(iaddr));\n\t\t\t\t_RTW_INFO(\"\\n\");\n\n\t\t\t\tif (!tx) {\n\t\t\t\t\t#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)\n\t\t\t\t\tif (rtw_mi_check_status(padapter, MI_LINKED)\n\t\t\t\t\t    && rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE\n\t\t\t\t\t    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {\n\t\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" ch_list has no intersect with buddy\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\t\t\t\trtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);\n\t\t\t\t\t}\n\t\t\t\t\t#endif\n\t\t\t\t}\n\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tcase P2P_GO_NEGO_RESP: {\n\t\t\t\tstruct rtw_wdev_nego_info *nego_info = &pwdev_priv->nego_info;\n\n\t\t\t\tif (tx) {\n\t\t\t\t\t#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)\n\t\t\t\t\tif (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)\n\t\t\t\t\t\trtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));\n\t\t\t\t\t#endif\n\t\t\t\t}\n\n\t\t\t\tcont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);\n\t\t\t\tif (cont)\n\t\t\t\t\top_ch = *(cont + 4);\n\t\t\t\tcont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT, NULL, &cont_len);\n\t\t\t\tif (cont)\n\t\t\t\t\tintent = *cont;\n\t\t\t\tcont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);\n\t\t\t\tif (cont)\n\t\t\t\t\tstatus = *cont;\n\t\t\t\tcont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, NULL, &cont_len);\n\t\t\t\tif (cont && cont_len == 6)\n\t\t\t\t\tiaddr = cont;\n\n\t\t\t\tif (nego_info->token == dialogToken && nego_info->state == 0\n\t\t\t\t\t&& _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE\n\t\t\t\t) {\n\t\t\t\t\tif (iaddr)\n\t\t\t\t\t\t_rtw_memcpy(tx ? nego_info->iface_addr : nego_info->peer_iface_addr, iaddr, ETH_ALEN);\n\t\t\t\t\tnego_info->status = (status == -1) ? 0xff : status;\n\t\t\t\t\tnego_info->rsp_op_ch = op_ch;\n\t\t\t\t\tnego_info->rsp_intent = intent;\n\t\t\t\t\tnego_info->state = 1;\n\t\t\t\t\tif (status != 0)\n\t\t\t\t\t\tnego_info->token = 0; /* init */\n\t\t\t\t}\n\n\t\t\t\tdump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);\n\t\t\t\tRTW_INFO(\"RTW_%s:P2P_GO_NEGO_RESP, dialogToken=%d, intent:%u%s, status:%d, op_ch:%d, ch_list:%s\"\n\t\t\t\t\t, (tx == _TRUE) ? \"Tx\" : \"Rx\", dialogToken, (intent >> 1), intent & 0x1 ? \"+\" : \"-\", status, op_ch, ch_list_buf);\n\t\t\t\tif (iaddr)\n\t\t\t\t\t_RTW_INFO(\", iaddr:\"MAC_FMT, MAC_ARG(iaddr));\n\t\t\t\t_RTW_INFO(\"\\n\");\n\n\t\t\t\tif (!tx) {\n\t\t\t\t\tpwdev_priv->provdisc_req_issued = _FALSE;\n\t\t\t\t\t#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)\n\t\t\t\t\tif (rtw_mi_check_status(padapter, MI_LINKED)\n\t\t\t\t\t    && rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE\n\t\t\t\t\t    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {\n\t\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" ch_list has no intersect with buddy\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\t\t\t\trtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);\n\t\t\t\t\t}\n\t\t\t\t\t#endif\n\t\t\t\t}\n\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tcase P2P_GO_NEGO_CONF: {\n\t\t\t\tstruct rtw_wdev_nego_info *nego_info = &pwdev_priv->nego_info;\n\t\t\t\tbool is_go = _FALSE;\n\n\t\t\t\tif (tx) {\n\t\t\t\t\t#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)\n\t\t\t\t\tif (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)\n\t\t\t\t\t\trtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));\n\t\t\t\t\t#endif\n\t\t\t\t}\n\n\t\t\t\tcont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);\n\t\t\t\tif (cont)\n\t\t\t\t\top_ch = *(cont + 4);\n\t\t\t\tcont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);\n\t\t\t\tif (cont)\n\t\t\t\t\tstatus = *cont;\n\n\t\t\t\tif (nego_info->token == dialogToken && nego_info->state == 1\n\t\t\t\t    && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE\n\t\t\t\t   ) {\n\t\t\t\t\tnego_info->status = (status == -1) ? 0xff : status;\n\t\t\t\t\tnego_info->conf_op_ch = (op_ch == -1) ? 0 : op_ch;\n\t\t\t\t\tnego_info->state = 2;\n\n\t\t\t\t\tif (status == 0) {\n\t\t\t\t\t\tif (rtw_p2p_nego_intent_compare(nego_info->req_intent, nego_info->rsp_intent) ^ !tx)\n\t\t\t\t\t\t\tis_go = _TRUE;\n\t\t\t\t\t}\n\n\t\t\t\t\tnego_info->token = 0; /* init */\n\t\t\t\t}\n\n\t\t\t\tdump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);\n\t\t\t\tRTW_INFO(\"RTW_%s:P2P_GO_NEGO_CONF, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s\\n\"\n\t\t\t\t\t, (tx == _TRUE) ? \"Tx\" : \"Rx\", dialogToken, status, op_ch, ch_list_buf);\n\n\t\t\t\tif (!tx) {\n\t\t\t\t}\n\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tcase P2P_INVIT_REQ: {\n\t\t\t\tstruct rtw_wdev_invit_info *invit_info = &pwdev_priv->invit_info;\n\t\t\t\tint flags = -1;\n\n\t\t\t\tif (tx) {\n\t\t\t\t\t#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)\n\t\t\t\t\tif (rtw_mi_check_status(padapter, MI_LINKED)\n\t\t\t\t\t    && padapter->registrypriv.full_ch_in_p2p_handshake == 0)\n\t\t\t\t\t\trtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));\n\t\t\t\t\t#endif\n\t\t\t\t}\n\n\t\t\t\tcont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INVITATION_FLAGS, NULL, &cont_len);\n\t\t\t\tif (cont)\n\t\t\t\t\tflags = *cont;\n\t\t\t\tcont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);\n\t\t\t\tif (cont)\n\t\t\t\t\top_ch = *(cont + 4);\n\t\t\t\tcont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_BSSID, NULL, &cont_len);\n\t\t\t\tif (cont && cont_len == 6)\n\t\t\t\t\tgbssid = cont;\n\n\t\t\t\tif (invit_info->token != dialogToken)\n\t\t\t\t\trtw_wdev_invit_info_init(invit_info);\n\n\t\t\t\t_rtw_memcpy(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN);\n\t\t\t\tif (gbssid)\n\t\t\t\t\t_rtw_memcpy(invit_info->group_bssid, gbssid, ETH_ALEN);\n\t\t\t\tinvit_info->active = tx ? 1 : 0;\n\t\t\t\tinvit_info->token = dialogToken;\n\t\t\t\tinvit_info->flags = (flags == -1) ? 0x0 : flags;\n\t\t\t\tinvit_info->req_op_ch = op_ch;\n\t\t\t\tinvit_info->state = 0;\n\n\t\t\t\tdump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);\n\t\t\t\tRTW_INFO(\"RTW_%s:P2P_INVIT_REQ, dialogToken=%d, flags:0x%02x, op_ch:%d, ch_list:%s\"\n\t\t\t\t\t, (tx == _TRUE) ? \"Tx\" : \"Rx\", dialogToken, flags, op_ch, ch_list_buf);\n\t\t\t\tif (gbssid)\n\t\t\t\t\t_RTW_INFO(\", gbssid:\"MAC_FMT, MAC_ARG(gbssid));\n\t\t\t\t_RTW_INFO(\"\\n\");\n\n\t\t\t\tif (!tx) {\n\t\t\t\t\t#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)\n\t\t\t\t\tif (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {\n\t\t\t\t\t\t#if defined(CONFIG_P2P_INVITE_IOT)\n\t\t\t\t\t\tif (op_ch != -1 && rtw_chk_p2pie_op_ch_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) {\n\t\t\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" op_ch:%u has no intersect with buddy\\n\", FUNC_ADPT_ARG(padapter), op_ch);\n\t\t\t\t\t\t\trtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);\n\t\t\t\t\t\t} else\n\t\t\t\t\t\t#endif\n\t\t\t\t\t\tif (rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) {\n\t\t\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" ch_list has no intersect with buddy\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\t\t\t\t\trtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\t#endif\n\t\t\t\t}\n\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tcase P2P_INVIT_RESP: {\n\t\t\t\tstruct rtw_wdev_invit_info *invit_info = &pwdev_priv->invit_info;\n\n\t\t\t\tif (tx) {\n\t\t\t\t\t#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)\n\t\t\t\t\tif (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)\n\t\t\t\t\t\trtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));\n\t\t\t\t\t#endif\n\t\t\t\t}\n\n\t\t\t\tcont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);\n\t\t\t\tif (cont) {\n\t\t\t\t\t#ifdef CONFIG_P2P_INVITE_IOT\n\t\t\t\t\tif (tx && *cont == 7) {\n\t\t\t\t\t\tRTW_INFO(\"TX_P2P_INVITE_RESP, status is no common channel, change to unknown group\\n\");\n\t\t\t\t\t\t*cont = 8; /* unknow group status */\n\t\t\t\t\t}\n\t\t\t\t\t#endif /* CONFIG_P2P_INVITE_IOT */\n\t\t\t\t\tstatus = *cont;\n\t\t\t\t}\n\t\t\t\tcont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);\n\t\t\t\tif (cont)\n\t\t\t\t\top_ch = *(cont + 4);\n\t\t\t\tcont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_BSSID, NULL, &cont_len);\n\t\t\t\tif (cont && cont_len == 6)\n\t\t\t\t\tgbssid = cont;\n\n\t\t\t\tif (invit_info->token == dialogToken && invit_info->state == 0\n\t\t\t\t    && _rtw_memcmp(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE\n\t\t\t\t   ) {\n\t\t\t\t\tinvit_info->status = (status == -1) ? 0xff : status;\n\t\t\t\t\tinvit_info->rsp_op_ch = op_ch;\n\t\t\t\t\tinvit_info->state = 1;\n\t\t\t\t\tinvit_info->token = 0; /* init */\n\t\t\t\t}\n\n\t\t\t\tdump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);\n\t\t\t\tRTW_INFO(\"RTW_%s:P2P_INVIT_RESP, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s\"\n\t\t\t\t\t, (tx == _TRUE) ? \"Tx\" : \"Rx\", dialogToken, status, op_ch, ch_list_buf);\n\t\t\t\tif (gbssid)\n\t\t\t\t\t_RTW_INFO(\", gbssid:\"MAC_FMT, MAC_ARG(gbssid));\n\t\t\t\t_RTW_INFO(\"\\n\");\n\n\t\t\t\tif (!tx) {\n\t\t\t\t}\n\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tcase P2P_DEVDISC_REQ:\n\t\t\t\tRTW_INFO(\"RTW_%s:P2P_DEVDISC_REQ, dialogToken=%d\\n\", (tx == _TRUE) ? \"Tx\" : \"Rx\", dialogToken);\n\t\t\t\tbreak;\n\t\t\tcase P2P_DEVDISC_RESP:\n\t\t\t\tcont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);\n\t\t\t\tRTW_INFO(\"RTW_%s:P2P_DEVDISC_RESP, dialogToken=%d, status:%d\\n\", (tx == _TRUE) ? \"Tx\" : \"Rx\", dialogToken, cont ? *cont : -1);\n\t\t\t\tbreak;\n\t\t\tcase P2P_PROVISION_DISC_REQ: {\n\t\t\t\tsize_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr);\n\t\t\t\tu8 *p2p_ie;\n\t\t\t\tuint p2p_ielen = 0;\n\t\t\t\tuint contentlen = 0;\n\n\t\t\t\tRTW_INFO(\"RTW_%s:P2P_PROVISION_DISC_REQ, dialogToken=%d\\n\", (tx == _TRUE) ? \"Tx\" : \"Rx\", dialogToken);\n\n\t\t\t\t/* if(tx) */\n\t\t\t\t{\n\t\t\t\t\tpwdev_priv->provdisc_req_issued = _FALSE;\n\n\t\t\t\t\tp2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen);\n\t\t\t\t\tif (p2p_ie) {\n\n\t\t\t\t\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, NULL, &contentlen)) {\n\t\t\t\t\t\t\tpwdev_priv->provdisc_req_issued = _FALSE;/* case: p2p_client join p2p GO */\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\t\t\t\t\t\tRTW_INFO(\"provdisc_req_issued is _TRUE\\n\");\n\t\t\t\t\t\t\t#endif /*CONFIG_DEBUG_CFG80211*/\n\t\t\t\t\t\t\tpwdev_priv->provdisc_req_issued = _TRUE;/* case: p2p_devices connection before Nego req. */\n\t\t\t\t\t\t}\n\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\t\tcase P2P_PROVISION_DISC_RESP:\n\t\t\t\tRTW_INFO(\"RTW_%s:P2P_PROVISION_DISC_RESP, dialogToken=%d\\n\", (tx == _TRUE) ? \"Tx\" : \"Rx\", dialogToken);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tRTW_INFO(\"RTW_%s:OUI_Subtype=%d, dialogToken=%d\\n\", (tx == _TRUE) ? \"Tx\" : \"Rx\", OUI_Subtype, dialogToken);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t}\n\n\t} else if (category == RTW_WLAN_CATEGORY_P2P) {\n\t\tOUI_Subtype = frame_body[5];\n\t\tdialogToken = frame_body[6];\n\n\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\tRTW_INFO(\"ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\\n\",\n\t\t\tcpu_to_be32(*((u32 *)(frame_body + 1))), OUI_Subtype, dialogToken);\n\t\t#endif\n\n\t\tis_p2p_frame = OUI_Subtype;\n\n\t\tswitch (OUI_Subtype) {\n\t\tcase P2P_NOTICE_OF_ABSENCE:\n\t\t\tRTW_INFO(\"RTW_%s:P2P_NOTICE_OF_ABSENCE, dialogToken=%d\\n\", (tx == _TRUE) ? \"Tx\" : \"Rx\", dialogToken);\n\t\t\tbreak;\n\t\tcase P2P_PRESENCE_REQUEST:\n\t\t\tRTW_INFO(\"RTW_%s:P2P_PRESENCE_REQUEST, dialogToken=%d\\n\", (tx == _TRUE) ? \"Tx\" : \"Rx\", dialogToken);\n\t\t\tbreak;\n\t\tcase P2P_PRESENCE_RESPONSE:\n\t\t\tRTW_INFO(\"RTW_%s:P2P_PRESENCE_RESPONSE, dialogToken=%d\\n\", (tx == _TRUE) ? \"Tx\" : \"Rx\", dialogToken);\n\t\t\tbreak;\n\t\tcase P2P_GO_DISC_REQUEST:\n\t\t\tRTW_INFO(\"RTW_%s:P2P_GO_DISC_REQUEST, dialogToken=%d\\n\", (tx == _TRUE) ? \"Tx\" : \"Rx\", dialogToken);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tRTW_INFO(\"RTW_%s:OUI_Subtype=%d, dialogToken=%d\\n\", (tx == _TRUE) ? \"Tx\" : \"Rx\", OUI_Subtype, dialogToken);\n\t\t\tbreak;\n\t\t}\n\n\t}\n\n\treturn is_p2p_frame;\n}\n\nvoid rtw_init_cfg80211_wifidirect_info(_adapter\t*padapter)\n{\n\tstruct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;\n\n\t_rtw_memset(pcfg80211_wdinfo, 0x00, sizeof(struct cfg80211_wifidirect_info));\n\n\trtw_init_timer(&pcfg80211_wdinfo->remain_on_ch_timer, padapter, ro_ch_timer_process, padapter);\n}\n#endif /* CONFIG_IOCTL_CFG80211\t */\n\ns32 p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf)\n{\n\tint ret = H2C_SUCCESS;\n\n\tswitch (intCmdType) {\n\tcase P2P_FIND_PHASE_WK:\n\t\tfind_phase_handler(padapter);\n\t\tbreak;\n\n\tcase P2P_RESTORE_STATE_WK:\n\t\trestore_p2p_state_handler(padapter);\n\t\tbreak;\n\n\tcase P2P_PRE_TX_PROVDISC_PROCESS_WK:\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED))\n\t\t\tp2p_concurrent_handler(padapter);\n\t\telse\n\t\t\tpre_tx_provdisc_handler(padapter);\n#else\n\t\tpre_tx_provdisc_handler(padapter);\n#endif\n\t\tbreak;\n\n\tcase P2P_PRE_TX_INVITEREQ_PROCESS_WK:\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED))\n\t\t\tp2p_concurrent_handler(padapter);\n\t\telse\n\t\t\tpre_tx_invitereq_handler(padapter);\n#else\n\t\tpre_tx_invitereq_handler(padapter);\n#endif\n\t\tbreak;\n\n\tcase P2P_PRE_TX_NEGOREQ_PROCESS_WK:\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED))\n\t\t\tp2p_concurrent_handler(padapter);\n\t\telse\n\t\t\tpre_tx_negoreq_handler(padapter);\n#else\n\t\tpre_tx_negoreq_handler(padapter);\n#endif\n\t\tbreak;\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tcase P2P_AP_P2P_CH_SWITCH_PROCESS_WK:\n\t\tp2p_concurrent_handler(padapter);\n\t\tbreak;\n#endif\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tcase P2P_RO_CH_WK:\n\t\tret = ro_ch_handler(padapter, buf);\n\t\tbreak;\n\tcase P2P_CANCEL_RO_CH_WK:\n\t\tret = cancel_ro_ch_handler(padapter, buf);\n\t\tbreak;\n#endif\n\n\tdefault:\n\t\trtw_warn_on(1);\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nint process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength)\n{\n\tint ret = _TRUE;\n\tu8 *ies;\n\tu32 ies_len;\n\tu8 *p2p_ie;\n\tu32\tp2p_ielen = 0;\n\tu8\tp2p_attr[MAX_P2P_IE_LEN] = { 0x00 };/* NoA length should be n*(13) + 2 */\n\tu32\tattr_contentlen = 0;\n\n\n\n\tif (IELength <= _BEACON_IE_OFFSET_)\n\t\treturn ret;\n\n\ties = IEs + _BEACON_IE_OFFSET_;\n\ties_len = IELength - _BEACON_IE_OFFSET_;\n\n\tp2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);\n\n\twhile (p2p_ie) {\n\t\t/* Get P2P Manageability IE. */\n\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_MANAGEABILITY, p2p_attr, &attr_contentlen)) {\n\t\t\tif ((p2p_attr[0] & (BIT(0) | BIT(1))) == 0x01)\n\t\t\t\tret = _FALSE;\n\t\t\tbreak;\n\t\t}\n\t\t/* Get the next P2P IE */\n\t\tp2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);\n\t}\n\n\treturn ret;\n}\n\n#ifdef CONFIG_P2P_PS\nvoid process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength)\n{\n\tu8 *ies;\n\tu32 ies_len;\n\tu8 *p2p_ie;\n\tu32\tp2p_ielen = 0;\n\tu8 *noa_attr; /* NoA length should be n*(13) + 2 */\n\tu32\tattr_contentlen = 0;\n\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\tu8\tfind_p2p = _FALSE, find_p2p_ps = _FALSE;\n\tu8\tnoa_offset, noa_num, noa_index;\n\n\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))\n\t\treturn;\n#ifdef CONFIG_CONCURRENT_MODE\n#ifndef CONFIG_FW_MULTI_PORT_SUPPORT\n\tif (padapter->hw_port != HW_PORT0)\n\t\treturn;\n#endif\n#endif\n\tif (IELength <= _BEACON_IE_OFFSET_)\n\t\treturn;\n\n\ties = IEs + _BEACON_IE_OFFSET_;\n\ties_len = IELength - _BEACON_IE_OFFSET_;\n\n\tp2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);\n\n\twhile (p2p_ie) {\n\t\tfind_p2p = _TRUE;\n\t\t/* Get Notice of Absence IE. */\n\t\tnoa_attr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_NOA, NULL, &attr_contentlen);\n\t\tif (noa_attr) {\n\t\t\tfind_p2p_ps = _TRUE;\n\t\t\tnoa_index = noa_attr[0];\n\n\t\t\tif ((pwdinfo->p2p_ps_mode == P2P_PS_NONE) ||\n\t\t\t    (noa_index != pwdinfo->noa_index)) { /* if index change, driver should reconfigure related setting. */\n\t\t\t\tpwdinfo->noa_index = noa_index;\n\t\t\t\tpwdinfo->opp_ps = noa_attr[1] >> 7;\n\t\t\t\tpwdinfo->ctwindow = noa_attr[1] & 0x7F;\n\n\t\t\t\tnoa_offset = 2;\n\t\t\t\tnoa_num = 0;\n\t\t\t\t/* NoA length should be n*(13) + 2 */\n\t\t\t\tif (attr_contentlen > 2 && (attr_contentlen - 2) % 13 == 0) {\n\t\t\t\t\twhile (noa_offset < attr_contentlen && noa_num < P2P_MAX_NOA_NUM) {\n\t\t\t\t\t\t/* _rtw_memcpy(&wifidirect_info->noa_count[noa_num], &noa_attr[noa_offset], 1); */\n\t\t\t\t\t\tpwdinfo->noa_count[noa_num] = noa_attr[noa_offset];\n\t\t\t\t\t\tnoa_offset += 1;\n\n\t\t\t\t\t\t_rtw_memcpy(&pwdinfo->noa_duration[noa_num], &noa_attr[noa_offset], 4);\n\t\t\t\t\t\tnoa_offset += 4;\n\n\t\t\t\t\t\t_rtw_memcpy(&pwdinfo->noa_interval[noa_num], &noa_attr[noa_offset], 4);\n\t\t\t\t\t\tnoa_offset += 4;\n\n\t\t\t\t\t\t_rtw_memcpy(&pwdinfo->noa_start_time[noa_num], &noa_attr[noa_offset], 4);\n\t\t\t\t\t\tnoa_offset += 4;\n\n\t\t\t\t\t\tnoa_num++;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tpwdinfo->noa_num = noa_num;\n\n\t\t\t\tif (pwdinfo->opp_ps == 1) {\n\t\t\t\t\tpwdinfo->p2p_ps_mode = P2P_PS_CTWINDOW;\n\t\t\t\t\t/* driver should wait LPS for entering CTWindow */\n\t\t\t\t\tif (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE)\n\t\t\t\t\t\tp2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1);\n\t\t\t\t} else if (pwdinfo->noa_num > 0) {\n\t\t\t\t\tpwdinfo->p2p_ps_mode = P2P_PS_NOA;\n\t\t\t\t\tp2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1);\n\t\t\t\t} else if (pwdinfo->p2p_ps_mode > P2P_PS_NONE)\n\t\t\t\t\tp2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1);\n\t\t\t}\n\n\t\t\tbreak; /* find target, just break. */\n\t\t}\n\n\t\t/* Get the next P2P IE */\n\t\tp2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);\n\n\t}\n\n\tif (find_p2p == _TRUE) {\n\t\tif ((pwdinfo->p2p_ps_mode > P2P_PS_NONE) && (find_p2p_ps == _FALSE))\n\t\t\tp2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1);\n\t}\n\n}\n\nvoid p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state)\n{\n\tstruct pwrctrl_priv\t\t*pwrpriv = adapter_to_pwrctl(padapter);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\tu32 ps_deny = 0;\n\n\t/* Pre action for p2p state */\n\tswitch (p2p_ps_state) {\n\tcase P2P_PS_DISABLE:\n\t\tpwdinfo->p2p_ps_state = p2p_ps_state;\n\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state));\n\n\t\tpwdinfo->noa_index = 0;\n\t\tpwdinfo->ctwindow = 0;\n\t\tpwdinfo->opp_ps = 0;\n\t\tpwdinfo->noa_num = 0;\n\t\tpwdinfo->p2p_ps_mode = P2P_PS_NONE;\n\t\tif (pwrpriv->bFwCurrentInPSMode == _TRUE) {\n\t\t\tif (pwrpriv->smart_ps == 0) {\n\t\t\t\tpwrpriv->smart_ps = 2;\n\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&(pwrpriv->pwr_mode)));\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tcase P2P_PS_ENABLE:\n\t\t_enter_pwrlock(&adapter_to_pwrctl(padapter)->lock);\n\t\tps_deny = rtw_ps_deny_get(padapter);\n\t\t_exit_pwrlock(&adapter_to_pwrctl(padapter)->lock);\n\n\t\tif ((ps_deny & (PS_DENY_SCAN | PS_DENY_JOIN))\n\t\t\t|| rtw_mi_check_fwstate(padapter, (_FW_UNDER_SURVEY | _FW_UNDER_LINKING))) {\n\t\t\tpwdinfo->p2p_ps_mode = P2P_PS_NONE;\n\t\t\tRTW_DBG(FUNC_ADPT_FMT\" Block P2P PS under site survey or LINKING\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\treturn;\n\t\t}\n\t\tif (pwdinfo->p2p_ps_mode > P2P_PS_NONE) {\n#ifdef CONFIG_MCC_MODE\n\t\t\tif (MCC_EN(padapter)) {\n\t\t\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {\n\t\t\t\t\tRTW_INFO(\"P2P PS enble under MCC\\n\");\n\t\t\t\t\trtw_warn_on(1);\n\t\t\t\t}\n\n\t\t\t}\n#endif /* CONFIG_MCC_MODE */\n\t\t\tpwdinfo->p2p_ps_state = p2p_ps_state;\n\n\t\t\tif (pwdinfo->ctwindow > 0) {\n\t\t\t\tif (pwrpriv->smart_ps != 0) {\n\t\t\t\t\tpwrpriv->smart_ps = 0;\n\t\t\t\t\tRTW_INFO(\"%s(): Enter CTW, change SmartPS\\n\", __FUNCTION__);\n\t\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&(pwrpriv->pwr_mode)));\n\t\t\t\t}\n\t\t\t}\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state));\n\t\t}\n\t\tbreak;\n\tcase P2P_PS_SCAN:\n\tcase P2P_PS_SCAN_DONE:\n\tcase P2P_PS_ALLSTASLEEP:\n\t\tif (pwdinfo->p2p_ps_mode > P2P_PS_NONE) {\n\t\t\tpwdinfo->p2p_ps_state = p2p_ps_state;\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state));\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n#ifdef CONFIG_MCC_MODE\n\trtw_hal_mcc_process_noa(padapter);\n#endif /* CONFIG_MCC_MODE */\n}\n\nu8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue)\n{\n\tstruct cmd_obj\t*ph2c;\n\tstruct drvextra_cmd_parm\t*pdrvextra_cmd_parm;\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\tstruct cmd_priv\t*pcmdpriv = &padapter->cmdpriv;\n\tu8\tres = _SUCCESS;\n\n\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)\n#ifdef CONFIG_CONCURRENT_MODE\n#ifndef CONFIG_FW_MULTI_PORT_SUPPORT\n\t    || (padapter->hw_port != HW_PORT0)\n#endif\n#endif\n\t   )\n\t\treturn res;\n\n\tif (enqueue) {\n\t\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\t\tif (ph2c == NULL) {\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\t\tif (pdrvextra_cmd_parm == NULL) {\n\t\t\trtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpdrvextra_cmd_parm->ec_id = P2P_PS_WK_CID;\n\t\tpdrvextra_cmd_parm->type = p2p_ps_state;\n\t\tpdrvextra_cmd_parm->size = 0;\n\t\tpdrvextra_cmd_parm->pbuf = NULL;\n\n\t\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\t\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\t} else\n\t\tp2p_ps_wk_hdl(padapter, p2p_ps_state);\n\nexit:\n\n\n\treturn res;\n\n}\n#endif /* CONFIG_P2P_PS */\n\nstatic void reset_ch_sitesurvey_timer_process(void *FunctionContext)\n{\n\t_adapter *adapter = (_adapter *)FunctionContext;\n\tstruct\twifidirect_info\t\t*pwdinfo = &adapter->wdinfo;\n\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))\n\t\treturn;\n\n\tRTW_INFO(\"[%s] In\\n\", __FUNCTION__);\n\t/*\tReset the operation channel information */\n\tpwdinfo->rx_invitereq_info.operation_ch[0] = 0;\n#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH\n\tpwdinfo->rx_invitereq_info.operation_ch[1] = 0;\n\tpwdinfo->rx_invitereq_info.operation_ch[2] = 0;\n\tpwdinfo->rx_invitereq_info.operation_ch[3] = 0;\n#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */\n\tpwdinfo->rx_invitereq_info.scan_op_ch_only = 0;\n}\n\nstatic void reset_ch_sitesurvey_timer_process2(void *FunctionContext)\n{\n\t_adapter *adapter = (_adapter *)FunctionContext;\n\tstruct\twifidirect_info\t\t*pwdinfo = &adapter->wdinfo;\n\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))\n\t\treturn;\n\n\tRTW_INFO(\"[%s] In\\n\", __FUNCTION__);\n\t/*\tReset the operation channel information */\n\tpwdinfo->p2p_info.operation_ch[0] = 0;\n#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH\n\tpwdinfo->p2p_info.operation_ch[1] = 0;\n\tpwdinfo->p2p_info.operation_ch[2] = 0;\n\tpwdinfo->p2p_info.operation_ch[3] = 0;\n#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */\n\tpwdinfo->p2p_info.scan_op_ch_only = 0;\n}\n\nstatic void restore_p2p_state_timer_process(void *FunctionContext)\n{\n\t_adapter *adapter = (_adapter *)FunctionContext;\n\tstruct\twifidirect_info\t\t*pwdinfo = &adapter->wdinfo;\n\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))\n\t\treturn;\n\n\tp2p_protocol_wk_cmd(adapter, P2P_RESTORE_STATE_WK);\n}\n\nstatic void pre_tx_scan_timer_process(void *FunctionContext)\n{\n\t_adapter\t\t\t\t\t\t\t*adapter = (_adapter *) FunctionContext;\n\tstruct\twifidirect_info\t\t\t\t*pwdinfo = &adapter->wdinfo;\n\t_irqL\t\t\t\t\t\t\tirqL;\n\tstruct mlme_priv\t\t\t\t\t*pmlmepriv = &adapter->mlmepriv;\n\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))\n\t\treturn;\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\n\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) {\n\t\tif (_TRUE == pwdinfo->tx_prov_disc_info.benable) {\t/*\tthe provision discovery request frame is trigger to send or not */\n\t\t\tp2p_protocol_wk_cmd(adapter, P2P_PRE_TX_PROVDISC_PROCESS_WK);\n\t\t\t/* issue_probereq_p2p(adapter, NULL); */\n\t\t\t/* _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); */\n\t\t}\n\t} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) {\n\t\tif (_TRUE == pwdinfo->nego_req_info.benable)\n\t\t\tp2p_protocol_wk_cmd(adapter, P2P_PRE_TX_NEGOREQ_PROCESS_WK);\n\t} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ)) {\n\t\tif (_TRUE == pwdinfo->invitereq_info.benable)\n\t\t\tp2p_protocol_wk_cmd(adapter, P2P_PRE_TX_INVITEREQ_PROCESS_WK);\n\t} else\n\t\tRTW_INFO(\"[%s] p2p_state is %d, ignore!!\\n\", __FUNCTION__, rtw_p2p_state(pwdinfo));\n\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n}\n\nstatic void find_phase_timer_process(void *FunctionContext)\n{\n\t_adapter *adapter = (_adapter *)FunctionContext;\n\tstruct\twifidirect_info\t\t*pwdinfo = &adapter->wdinfo;\n\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))\n\t\treturn;\n\n\tadapter->wdinfo.find_phase_state_exchange_cnt++;\n\n\tp2p_protocol_wk_cmd(adapter, P2P_FIND_PHASE_WK);\n}\n\n#ifdef CONFIG_CONCURRENT_MODE\nvoid ap_p2p_switch_timer_process(void *FunctionContext)\n{\n\t_adapter *adapter = (_adapter *)FunctionContext;\n\tstruct\twifidirect_info\t\t*pwdinfo = &adapter->wdinfo;\n#ifdef CONFIG_IOCTL_CFG80211\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);\n#endif\n\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))\n\t\treturn;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tATOMIC_SET(&pwdev_priv->switch_ch_to, 1);\n#endif\n\n\tp2p_protocol_wk_cmd(adapter, P2P_AP_P2P_CH_SWITCH_PROCESS_WK);\n}\n#endif\n\nvoid reset_global_wifidirect_info(_adapter *padapter)\n{\n\tstruct wifidirect_info\t*pwdinfo;\n\n\tpwdinfo = &padapter->wdinfo;\n\tpwdinfo->persistent_supported = 0;\n\tpwdinfo->session_available = _TRUE;\n\trtw_tdls_wfd_enable(padapter, 0);\n\tpwdinfo->wfd_tdls_weaksec = _TRUE;\n}\n\n#ifdef CONFIG_WFD\nint rtw_init_wifi_display_info(_adapter *padapter)\n{\n\tint\tres = _SUCCESS;\n\tstruct wifi_display_info *pwfd_info = &padapter->wfd_info;\n\n\t/* Used in P2P and TDLS */\n\tpwfd_info->init_rtsp_ctrlport = 554;\n#ifdef CONFIG_IOCTL_CFG80211\n\tpwfd_info->rtsp_ctrlport = 0;\n#else\n\tpwfd_info->rtsp_ctrlport = pwfd_info->init_rtsp_ctrlport; /* set non-zero value for legacy wfd */\n#endif\n\tpwfd_info->tdls_rtsp_ctrlport = 0;\n\tpwfd_info->peer_rtsp_ctrlport = 0;\t/*\tReset to 0 */\n\tpwfd_info->wfd_enable = _FALSE;\n\tpwfd_info->wfd_device_type = WFD_DEVINFO_PSINK;\n\tpwfd_info->scan_result_type = SCAN_RESULT_P2P_ONLY;\n\n\t/* Used in P2P */\n\tpwfd_info->peer_session_avail = _TRUE;\n\tpwfd_info->wfd_pc = _FALSE;\n\n\t/* Used in TDLS */\n\t_rtw_memset(pwfd_info->ip_address, 0x00, 4);\n\t_rtw_memset(pwfd_info->peer_ip_address, 0x00, 4);\n\treturn res;\n\n}\n\ninline void rtw_wfd_enable(_adapter *adapter, bool on)\n{\n\tstruct wifi_display_info *wfdinfo = &adapter->wfd_info;\n\n\tif (on) {\n\t\twfdinfo->rtsp_ctrlport = wfdinfo->init_rtsp_ctrlport;\n\t\twfdinfo->wfd_enable = _TRUE;\n\n\t} else {\n\t\twfdinfo->wfd_enable = _FALSE;\n\t\twfdinfo->rtsp_ctrlport = 0;\n\t}\n}\n\ninline void rtw_wfd_set_ctrl_port(_adapter *adapter, u16 port)\n{\n\tstruct wifi_display_info *wfdinfo = &adapter->wfd_info;\n\n\twfdinfo->init_rtsp_ctrlport = port;\n\tif (wfdinfo->wfd_enable == _TRUE)\n\t\twfdinfo->rtsp_ctrlport = port;\n\tif (adapter->wdinfo.wfd_tdls_enable == 1)\n\t\twfdinfo->tdls_rtsp_ctrlport = port;\n}\n\ninline void rtw_tdls_wfd_enable(_adapter *adapter, bool on)\n{\n\tstruct wifi_display_info *wfdinfo = &adapter->wfd_info;\n\n\tif (on) {\n\t\twfdinfo->tdls_rtsp_ctrlport = wfdinfo->init_rtsp_ctrlport;\n\t\tadapter->wdinfo.wfd_tdls_enable = 1;\n\n\t} else {\n\t\tadapter->wdinfo.wfd_tdls_enable = 0;\n\t\twfdinfo->tdls_rtsp_ctrlport = 0;\n\t}\n}\n\nu32 rtw_append_beacon_wfd_ie(_adapter *adapter, u8 *pbuf)\n{\n\tstruct wifidirect_info *wdinfo = &adapter->wdinfo;\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\tu8 build_ie_by_self = 0;\n\tu32 len = 0;\n\n\tif (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))\n\t\tgoto exit;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (_TRUE == wdinfo->wfd_info->wfd_enable)\n#endif\n\t\tbuild_ie_by_self = 1;\n\n\tif (build_ie_by_self)\n\t\tlen = build_beacon_wfd_ie(wdinfo, pbuf);\n#ifdef CONFIG_IOCTL_CFG80211\n\telse if (mlme->wfd_beacon_ie && mlme->wfd_beacon_ie_len > 0) {\n\t\tlen = mlme->wfd_beacon_ie_len;\n\t\t_rtw_memcpy(pbuf, mlme->wfd_beacon_ie, len);\n\t}\n#endif\n\nexit:\n\treturn len;\n}\n\nu32 rtw_append_probe_req_wfd_ie(_adapter *adapter, u8 *pbuf)\n{\n\tstruct wifidirect_info *wdinfo = &adapter->wdinfo;\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\tu8 build_ie_by_self = 0;\n\tu32 len = 0;\n\n\tif (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))\n\t\tgoto exit;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (_TRUE == wdinfo->wfd_info->wfd_enable)\n#endif\n\t\tbuild_ie_by_self = 1;\n\n\tif (build_ie_by_self)\n\t\tlen = build_probe_req_wfd_ie(wdinfo, pbuf);\n#ifdef CONFIG_IOCTL_CFG80211\n\telse if (mlme->wfd_probe_req_ie && mlme->wfd_probe_req_ie_len > 0) {\n\t\tlen = mlme->wfd_probe_req_ie_len;\n\t\t_rtw_memcpy(pbuf, mlme->wfd_probe_req_ie, len);\n\t}\n#endif\n\nexit:\n\treturn len;\n}\n\nu32 rtw_append_probe_resp_wfd_ie(_adapter *adapter, u8 *pbuf)\n{\n\tstruct wifidirect_info *wdinfo = &adapter->wdinfo;\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\tu8 build_ie_by_self = 0;\n\tu32 len = 0;\n\n\tif (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))\n\t\tgoto exit;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (_TRUE == wdinfo->wfd_info->wfd_enable)\n#endif\n\t\tbuild_ie_by_self = 1;\n\n\tif (build_ie_by_self)\n\t\tlen = build_probe_resp_wfd_ie(wdinfo, pbuf, 0);\n#ifdef CONFIG_IOCTL_CFG80211\n\telse if (mlme->wfd_probe_resp_ie && mlme->wfd_probe_resp_ie_len > 0) {\n\t\tlen = mlme->wfd_probe_resp_ie_len;\n\t\t_rtw_memcpy(pbuf, mlme->wfd_probe_resp_ie, len);\n\t}\n#endif\n\nexit:\n\treturn len;\n}\n\nu32 rtw_append_assoc_req_wfd_ie(_adapter *adapter, u8 *pbuf)\n{\n\tstruct wifidirect_info *wdinfo = &adapter->wdinfo;\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\tu8 build_ie_by_self = 0;\n\tu32 len = 0;\n\n\tif (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))\n\t\tgoto exit;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (_TRUE == wdinfo->wfd_info->wfd_enable)\n#endif\n\t\tbuild_ie_by_self = 1;\n\n\tif (build_ie_by_self)\n\t\tlen = build_assoc_req_wfd_ie(wdinfo, pbuf);\n#ifdef CONFIG_IOCTL_CFG80211\n\telse if (mlme->wfd_assoc_req_ie && mlme->wfd_assoc_req_ie_len > 0) {\n\t\tlen = mlme->wfd_assoc_req_ie_len;\n\t\t_rtw_memcpy(pbuf, mlme->wfd_assoc_req_ie, len);\n\t}\n#endif\n\nexit:\n\treturn len;\n}\n\nu32 rtw_append_assoc_resp_wfd_ie(_adapter *adapter, u8 *pbuf)\n{\n\tstruct wifidirect_info *wdinfo = &adapter->wdinfo;\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\tu8 build_ie_by_self = 0;\n\tu32 len = 0;\n\n\tif (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))\n\t\tgoto exit;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (_TRUE == wdinfo->wfd_info->wfd_enable)\n#endif\n\t\tbuild_ie_by_self = 1;\n\n\tif (build_ie_by_self)\n\t\tlen = build_assoc_resp_wfd_ie(wdinfo, pbuf);\n#ifdef CONFIG_IOCTL_CFG80211\n\telse if (mlme->wfd_assoc_resp_ie && mlme->wfd_assoc_resp_ie_len > 0) {\n\t\tlen = mlme->wfd_assoc_resp_ie_len;\n\t\t_rtw_memcpy(pbuf, mlme->wfd_assoc_resp_ie, len);\n\t}\n#endif\n\nexit:\n\treturn len;\n}\n\n#endif /* CONFIG_WFD */\n\nvoid rtw_init_wifidirect_timers(_adapter *padapter)\n{\n\tstruct wifidirect_info *pwdinfo = &padapter->wdinfo;\n\n\trtw_init_timer(&pwdinfo->find_phase_timer, padapter, find_phase_timer_process, padapter);\n\trtw_init_timer(&pwdinfo->restore_p2p_state_timer, padapter, restore_p2p_state_timer_process, padapter);\n\trtw_init_timer(&pwdinfo->pre_tx_scan_timer, padapter, pre_tx_scan_timer_process, padapter);\n\trtw_init_timer(&pwdinfo->reset_ch_sitesurvey, padapter, reset_ch_sitesurvey_timer_process, padapter);\n\trtw_init_timer(&pwdinfo->reset_ch_sitesurvey2, padapter, reset_ch_sitesurvey_timer_process2, padapter);\n#ifdef CONFIG_CONCURRENT_MODE\n\trtw_init_timer(&pwdinfo->ap_p2p_switch_timer, padapter, ap_p2p_switch_timer_process, padapter);\n#endif\n}\n\nvoid rtw_init_wifidirect_addrs(_adapter *padapter, u8 *dev_addr, u8 *iface_addr)\n{\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *pwdinfo = &padapter->wdinfo;\n\n\t/*init device&interface address */\n\tif (dev_addr)\n\t\t_rtw_memcpy(pwdinfo->device_addr, dev_addr, ETH_ALEN);\n\tif (iface_addr)\n\t\t_rtw_memcpy(pwdinfo->interface_addr, iface_addr, ETH_ALEN);\n#endif\n}\n\nvoid init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role)\n{\n\tstruct wifidirect_info\t*pwdinfo;\n#ifdef CONFIG_WFD\n\tstruct wifi_display_info\t*pwfd_info = &padapter->wfd_info;\n#endif\n\tpwdinfo = &padapter->wdinfo;\n\n\tpwdinfo->padapter = padapter;\n\n\t/*\t1, 6, 11 are the social channel defined in the WiFi Direct specification. */\n\tpwdinfo->social_chan[0] = 1;\n\tpwdinfo->social_chan[1] = 6;\n\tpwdinfo->social_chan[2] = 11;\n\tpwdinfo->social_chan[3] = 0;\t/*\tchannel 0 for scanning ending in site survey function. */\n\n\tif (role != P2P_ROLE_DISABLE\n\t\t&& pwdinfo->driver_interface != DRIVER_CFG80211\n\t) {\n\t\t#ifdef CONFIG_CONCURRENT_MODE\n\t\tu8 union_ch = 0;\n\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED))\n\t\t\tunion_ch = rtw_mi_get_union_chan(padapter);\n\n\t\tif (union_ch != 0 &&\n\t\t\t(union_ch == 1 || union_ch == 6 || union_ch == 11)\n\t\t) {\n\t\t\t/* Use the AP's channel as the listen channel */\n\t\t\t/* This will avoid the channel switch between AP's channel and listen channel */\n\t\t\tpwdinfo->listen_channel = union_ch;\n\t\t} else\n\t\t#endif /* CONFIG_CONCURRENT_MODE */\n\t\t{\n\t\t\t/* Use the channel 11 as the listen channel */\n\t\t\tpwdinfo->listen_channel = 11;\n\t\t}\n\t}\n\n\tif (role == P2P_ROLE_DEVICE) {\n\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED))\n\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE);\n\t\telse\n#endif\n\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);\n\n\t\tpwdinfo->intent = 1;\n\t\trtw_p2p_set_pre_state(pwdinfo, P2P_STATE_LISTEN);\n\t} else if (role == P2P_ROLE_CLIENT) {\n\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);\n\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);\n\t\tpwdinfo->intent = 1;\n\t\trtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);\n\t} else if (role == P2P_ROLE_GO) {\n\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);\n\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);\n\t\tpwdinfo->intent = 15;\n\t\trtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);\n\t}\n\n\t/*\tUse the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 )\t */\n\tpwdinfo->support_rate[0] = 0x8c;\t/*\t6(B) */\n\tpwdinfo->support_rate[1] = 0x92;\t/*\t9(B) */\n\tpwdinfo->support_rate[2] = 0x18;\t/*\t12 */\n\tpwdinfo->support_rate[3] = 0x24;\t/*\t18 */\n\tpwdinfo->support_rate[4] = 0x30;\t/*\t24 */\n\tpwdinfo->support_rate[5] = 0x48;\t/*\t36 */\n\tpwdinfo->support_rate[6] = 0x60;\t/*\t48 */\n\tpwdinfo->support_rate[7] = 0x6c;\t/*\t54 */\n\n\t_rtw_memcpy((void *) pwdinfo->p2p_wildcard_ssid, \"DIRECT-\", 7);\n\n\t_rtw_memset(pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN);\n\tpwdinfo->device_name_len = 0;\n\n\t_rtw_memset(&pwdinfo->invitereq_info, 0x00, sizeof(struct tx_invite_req_info));\n\tpwdinfo->invitereq_info.token = 3;\t/*\tToken used for P2P invitation request frame. */\n\n\t_rtw_memset(&pwdinfo->inviteresp_info, 0x00, sizeof(struct tx_invite_resp_info));\n\tpwdinfo->inviteresp_info.token = 0;\n\n\tpwdinfo->profileindex = 0;\n\t_rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM);\n\n\trtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);\n\n\tpwdinfo->listen_dwell = (u8)((rtw_get_current_time() % 3) + 1);\n\t/* RTW_INFO( \"[%s] listen_dwell time is %d00ms\\n\", __FUNCTION__, pwdinfo->listen_dwell ); */\n\n\t_rtw_memset(&pwdinfo->tx_prov_disc_info, 0x00, sizeof(struct tx_provdisc_req_info));\n\tpwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_NONE;\n\n\t_rtw_memset(&pwdinfo->nego_req_info, 0x00, sizeof(struct tx_nego_req_info));\n\n\tpwdinfo->device_password_id_for_nego = WPS_DPID_PBC;\n\tpwdinfo->negotiation_dialog_token = 1;\n\n\t_rtw_memset(pwdinfo->nego_ssid, 0x00, WLAN_SSID_MAXLEN);\n\tpwdinfo->nego_ssidlen = 0;\n\n\tpwdinfo->ui_got_wps_info = P2P_NO_WPSINFO;\n#ifdef CONFIG_WFD\n\tpwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY  | WPS_CONFIG_METHOD_PBC;\n\tpwdinfo->wfd_info = pwfd_info;\n#else\n\tpwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY | WPS_CONFIG_METHOD_PBC | WPS_CONFIG_METHOD_KEYPAD;\n#endif /* CONFIG_WFD */\n\tpwdinfo->channel_list_attr_len = 0;\n\t_rtw_memset(pwdinfo->channel_list_attr, 0x00, 100);\n\n\t_rtw_memset(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, 0x00, 4);\n\t_rtw_memset(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, '0', 3);\n\t_rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info));\n#ifdef CONFIG_CONCURRENT_MODE\n#ifdef CONFIG_IOCTL_CFG80211\n\tpwdinfo->ext_listen_interval = 1000; /* The interval to be available with legacy AP during p2p0-find/scan */\n\tpwdinfo->ext_listen_period = 3000; /* The time period to be available for P2P during nego */\n#else /* !CONFIG_IOCTL_CFG80211 */\n\t/* pwdinfo->ext_listen_interval = 3000; */\n\t/* pwdinfo->ext_listen_period = 400; */\n\tpwdinfo->ext_listen_interval = 1000;\n\tpwdinfo->ext_listen_period = 1000;\n#endif /* !CONFIG_IOCTL_CFG80211 */\n#endif\n\n\t/* Commented by Kurt 20130319\n\t * For WiDi purpose: Use CFG80211 interface but controled WFD/RDS frame by driver itself. */\n#ifdef CONFIG_IOCTL_CFG80211\n\tpwdinfo->driver_interface = DRIVER_CFG80211;\n#else\n\tpwdinfo->driver_interface = DRIVER_WEXT;\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n\tpwdinfo->wfd_tdls_enable = 0;\n\t_rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN);\n\t_rtw_memset(pwdinfo->p2p_peer_device_addr, 0x00, ETH_ALEN);\n\n\tpwdinfo->rx_invitereq_info.operation_ch[0] = 0;\n\tpwdinfo->rx_invitereq_info.operation_ch[1] = 0;\t/*\tUsed to indicate the scan end in site survey function */\n#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH\n\tpwdinfo->rx_invitereq_info.operation_ch[2] = 0;\n\tpwdinfo->rx_invitereq_info.operation_ch[3] = 0;\n\tpwdinfo->rx_invitereq_info.operation_ch[4] = 0;\n#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */\n\tpwdinfo->rx_invitereq_info.scan_op_ch_only = 0;\n\tpwdinfo->p2p_info.operation_ch[0] = 0;\n\tpwdinfo->p2p_info.operation_ch[1] = 0;\t\t\t/*\tUsed to indicate the scan end in site survey function */\n#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH\n\tpwdinfo->p2p_info.operation_ch[2] = 0;\n\tpwdinfo->p2p_info.operation_ch[3] = 0;\n\tpwdinfo->p2p_info.operation_ch[4] = 0;\n#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */\n\tpwdinfo->p2p_info.scan_op_ch_only = 0;\n}\n\nvoid _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role)\n{\n\tif (wdinfo->role != role) {\n\t\twdinfo->role = role;\n\t\trtw_mi_update_iface_status(&(wdinfo->padapter->mlmepriv), 0);\n\t}\n}\n\n#ifdef CONFIG_DBG_P2P\n\n/**\n * rtw_p2p_role_txt - Get the p2p role name as a text string\n * @role: P2P role\n * Returns: The state name as a printable text string\n */\nconst char *rtw_p2p_role_txt(enum P2P_ROLE role)\n{\n\tswitch (role) {\n\tcase P2P_ROLE_DISABLE:\n\t\treturn \"P2P_ROLE_DISABLE\";\n\tcase P2P_ROLE_DEVICE:\n\t\treturn \"P2P_ROLE_DEVICE\";\n\tcase P2P_ROLE_CLIENT:\n\t\treturn \"P2P_ROLE_CLIENT\";\n\tcase P2P_ROLE_GO:\n\t\treturn \"P2P_ROLE_GO\";\n\tdefault:\n\t\treturn \"UNKNOWN\";\n\t}\n}\n\n/**\n * rtw_p2p_state_txt - Get the p2p state name as a text string\n * @state: P2P state\n * Returns: The state name as a printable text string\n */\nconst char *rtw_p2p_state_txt(enum P2P_STATE state)\n{\n\tswitch (state) {\n\tcase P2P_STATE_NONE:\n\t\treturn \"P2P_STATE_NONE\";\n\tcase P2P_STATE_IDLE:\n\t\treturn \"P2P_STATE_IDLE\";\n\tcase P2P_STATE_LISTEN:\n\t\treturn \"P2P_STATE_LISTEN\";\n\tcase P2P_STATE_SCAN:\n\t\treturn \"P2P_STATE_SCAN\";\n\tcase P2P_STATE_FIND_PHASE_LISTEN:\n\t\treturn \"P2P_STATE_FIND_PHASE_LISTEN\";\n\tcase P2P_STATE_FIND_PHASE_SEARCH:\n\t\treturn \"P2P_STATE_FIND_PHASE_SEARCH\";\n\tcase P2P_STATE_TX_PROVISION_DIS_REQ:\n\t\treturn \"P2P_STATE_TX_PROVISION_DIS_REQ\";\n\tcase P2P_STATE_RX_PROVISION_DIS_RSP:\n\t\treturn \"P2P_STATE_RX_PROVISION_DIS_RSP\";\n\tcase P2P_STATE_RX_PROVISION_DIS_REQ:\n\t\treturn \"P2P_STATE_RX_PROVISION_DIS_REQ\";\n\tcase P2P_STATE_GONEGO_ING:\n\t\treturn \"P2P_STATE_GONEGO_ING\";\n\tcase P2P_STATE_GONEGO_OK:\n\t\treturn \"P2P_STATE_GONEGO_OK\";\n\tcase P2P_STATE_GONEGO_FAIL:\n\t\treturn \"P2P_STATE_GONEGO_FAIL\";\n\tcase P2P_STATE_RECV_INVITE_REQ_MATCH:\n\t\treturn \"P2P_STATE_RECV_INVITE_REQ_MATCH\";\n\tcase P2P_STATE_PROVISIONING_ING:\n\t\treturn \"P2P_STATE_PROVISIONING_ING\";\n\tcase P2P_STATE_PROVISIONING_DONE:\n\t\treturn \"P2P_STATE_PROVISIONING_DONE\";\n\tcase P2P_STATE_TX_INVITE_REQ:\n\t\treturn \"P2P_STATE_TX_INVITE_REQ\";\n\tcase P2P_STATE_RX_INVITE_RESP_OK:\n\t\treturn \"P2P_STATE_RX_INVITE_RESP_OK\";\n\tcase P2P_STATE_RECV_INVITE_REQ_DISMATCH:\n\t\treturn \"P2P_STATE_RECV_INVITE_REQ_DISMATCH\";\n\tcase P2P_STATE_RECV_INVITE_REQ_GO:\n\t\treturn \"P2P_STATE_RECV_INVITE_REQ_GO\";\n\tcase P2P_STATE_RECV_INVITE_REQ_JOIN:\n\t\treturn \"P2P_STATE_RECV_INVITE_REQ_JOIN\";\n\tcase P2P_STATE_RX_INVITE_RESP_FAIL:\n\t\treturn \"P2P_STATE_RX_INVITE_RESP_FAIL\";\n\tcase P2P_STATE_RX_INFOR_NOREADY:\n\t\treturn \"P2P_STATE_RX_INFOR_NOREADY\";\n\tcase P2P_STATE_TX_INFOR_NOREADY:\n\t\treturn \"P2P_STATE_TX_INFOR_NOREADY\";\n\tdefault:\n\t\treturn \"UNKNOWN\";\n\t}\n}\n\nvoid dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line)\n{\n\tif (!_rtw_p2p_chk_state(wdinfo, state)) {\n\t\tenum P2P_STATE old_state = _rtw_p2p_state(wdinfo);\n\t\t_rtw_p2p_set_state(wdinfo, state);\n\t\tRTW_INFO(\"[CONFIG_DBG_P2P]%s:%d set_state from %s to %s\\n\", caller, line\n\t\t\t, rtw_p2p_state_txt(old_state), rtw_p2p_state_txt(_rtw_p2p_state(wdinfo))\n\t\t\t);\n\t} else {\n\t\tRTW_INFO(\"[CONFIG_DBG_P2P]%s:%d set_state to same state %s\\n\", caller, line\n\t\t\t , rtw_p2p_state_txt(_rtw_p2p_state(wdinfo))\n\t\t\t);\n\t}\n}\nvoid dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line)\n{\n\tif (_rtw_p2p_pre_state(wdinfo) != state) {\n\t\tenum P2P_STATE old_state = _rtw_p2p_pre_state(wdinfo);\n\t\t_rtw_p2p_set_pre_state(wdinfo, state);\n\t\tRTW_INFO(\"[CONFIG_DBG_P2P]%s:%d set_pre_state from %s to %s\\n\", caller, line\n\t\t\t, rtw_p2p_state_txt(old_state), rtw_p2p_state_txt(_rtw_p2p_pre_state(wdinfo))\n\t\t\t);\n\t} else {\n\t\tRTW_INFO(\"[CONFIG_DBG_P2P]%s:%d set_pre_state to same state %s\\n\", caller, line\n\t\t\t , rtw_p2p_state_txt(_rtw_p2p_pre_state(wdinfo))\n\t\t\t);\n\t}\n}\n#if 0\nvoid dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line)\n{\n\tif (wdinfo->pre_p2p_state != -1) {\n\t\tRTW_INFO(\"[CONFIG_DBG_P2P]%s:%d restore from %s to %s\\n\", caller, line\n\t\t\t, p2p_state_str[wdinfo->p2p_state], p2p_state_str[wdinfo->pre_p2p_state]\n\t\t\t);\n\t\t_rtw_p2p_restore_state(wdinfo);\n\t} else {\n\t\tRTW_INFO(\"[CONFIG_DBG_P2P]%s:%d restore no pre state, cur state %s\\n\", caller, line\n\t\t\t , p2p_state_str[wdinfo->p2p_state]\n\t\t\t);\n\t}\n}\n#endif\nvoid dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line)\n{\n\tif (wdinfo->role != role) {\n\t\tenum P2P_ROLE old_role = wdinfo->role;\n\t\t_rtw_p2p_set_role(wdinfo, role);\n\t\tRTW_INFO(\"[CONFIG_DBG_P2P]%s:%d set_role from %s to %s\\n\", caller, line\n\t\t\t, rtw_p2p_role_txt(old_role), rtw_p2p_role_txt(wdinfo->role)\n\t\t\t);\n\t} else {\n\t\tRTW_INFO(\"[CONFIG_DBG_P2P]%s:%d set_role to same role %s\\n\", caller, line\n\t\t\t , rtw_p2p_role_txt(wdinfo->role)\n\t\t\t);\n\t}\n}\n#endif /* CONFIG_DBG_P2P */\n\n\nint rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role)\n{\n\tint ret = _SUCCESS;\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n\n\tif (role == P2P_ROLE_DEVICE || role == P2P_ROLE_CLIENT || role == P2P_ROLE_GO) {\n#if defined(CONFIG_CONCURRENT_MODE) && (!defined(RTW_P2P_GROUP_INTERFACE) || !RTW_P2P_GROUP_INTERFACE)\n\t\t/*\tCommented by Albert 2011/12/30 */\n\t\t/*\tThe driver just supports 1 P2P group operation. */\n\t\t/*\tSo, this function will do nothing if the buddy adapter had enabled the P2P function. */\n\t\t/*if(!rtw_p2p_chk_state(pbuddy_wdinfo, P2P_STATE_NONE))\n\t\t\treturn ret;*/\n\t\t/*The buddy adapter had enabled the P2P function.*/\n\t\tif (rtw_mi_buddy_stay_in_p2p_mode(padapter))\n\t\t\treturn ret;\n#endif /* CONFIG_CONCURRENT_MODE */\n\n\t\t/* leave IPS/Autosuspend */\n\t\tif (_FAIL == rtw_pwr_wakeup(padapter)) {\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/*\tAdded by Albert 2011/03/22 */\n\t\t/*\tIn the P2P mode, the driver should not support the b mode. */\n\t\t/*\tSo, the Tx packet shouldn't use the CCK rate */\n\t\t#ifdef CONFIG_IOCTL_CFG80211\n\t\tif (rtw_cfg80211_iface_has_p2p_group_cap(padapter))\n\t\t#endif\n\t\t\tupdate_tx_basic_rate(padapter, WIRELESS_11AGN);\n\n\t\t/* Enable P2P function */\n\t\tinit_wifidirect_info(padapter, role);\n\n\t\t#ifdef CONFIG_IOCTL_CFG80211\n\t\tif (padapter->wdinfo.driver_interface == DRIVER_CFG80211)\n\t\t\tadapter_wdev_data(padapter)->p2p_enabled = _TRUE;\n\t\t#endif\n\n\t\trtw_hal_set_odm_var(padapter, HAL_ODM_P2P_STATE, NULL, _TRUE);\n#ifdef CONFIG_WFD\n\t\tif (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))\n\t\t\trtw_hal_set_odm_var(padapter, HAL_ODM_WIFI_DISPLAY_STATE, NULL, _TRUE);\n#endif\n\n\t} else if (role == P2P_ROLE_DISABLE) {\n\n\t\t#ifdef CONFIG_IOCTL_CFG80211\n\t\tif (padapter->wdinfo.driver_interface == DRIVER_CFG80211)\n\t\t\tadapter_wdev_data(padapter)->p2p_enabled = _FALSE;\n\t\t#endif\n\n\t\tpwdinfo->listen_channel = 0;\n\n\t\t/* Disable P2P function */\n\t\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {\n\t\t\t_cancel_timer_ex(&pwdinfo->find_phase_timer);\n\t\t\t_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);\n\t\t\t_cancel_timer_ex(&pwdinfo->pre_tx_scan_timer);\n\t\t\t_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);\n\t\t\t_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey2);\n\t\t\treset_ch_sitesurvey_timer_process(padapter);\n\t\t\treset_ch_sitesurvey_timer_process2(padapter);\n#ifdef CONFIG_CONCURRENT_MODE\n\t\t\t_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);\n#endif\n\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_NONE);\n\t\t\trtw_p2p_set_pre_state(pwdinfo, P2P_STATE_NONE);\n\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_DISABLE);\n\t\t\t_rtw_memset(&pwdinfo->rx_prov_disc_info, 0x00, sizeof(struct rx_provdisc_req_info));\n\n\t\t\t/* Remove profiles in wifidirect_info structure. */\n\t\t\t_rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM);\n\t\t\tpwdinfo->profileindex = 0;\n\t\t}\n\n\t\trtw_hal_set_odm_var(padapter, HAL_ODM_P2P_STATE, NULL, _FALSE);\n#ifdef CONFIG_WFD\n\t\tif (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))\n\t\t\trtw_hal_set_odm_var(padapter, HAL_ODM_WIFI_DISPLAY_STATE, NULL, _FALSE);\n#endif\n\n\t\tif (_FAIL == rtw_pwr_wakeup(padapter)) {\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* Restore to initial setting. */\n\t\tupdate_tx_basic_rate(padapter, padapter->registrypriv.wireless_mode);\n\n\t\t/* For WiDi purpose. */\n#ifdef CONFIG_IOCTL_CFG80211\n\t\tpwdinfo->driver_interface = DRIVER_CFG80211;\n#else\n\t\tpwdinfo->driver_interface = DRIVER_WEXT;\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n\t}\n\nexit:\n\treturn ret;\n}\n\n#endif /* CONFIG_P2P */\n"
  },
  {
    "path": "core/rtw_pwrctrl.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_PWRCTRL_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n#include <hal_com_h2c.h>\n\n#ifdef DBG_CHECK_FW_PS_STATE\nint rtw_fw_ps_state(PADAPTER padapter)\n{\n\tstruct dvobj_priv *psdpriv = padapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &psdpriv->drv_dbg;\n\tint ret = _FAIL, dont_care = 0;\n\tu16 fw_ps_state = 0;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tstruct registry_priv  *registry_par = &padapter->registrypriv;\n\n\tif (registry_par->check_fw_ps != 1)\n\t\treturn _SUCCESS;\n\n\t_enter_pwrlock(&pwrpriv->check_32k_lock);\n\n\tif (RTW_CANNOT_RUN(padapter)) {\n\t\tRTW_INFO(\"%s: bSurpriseRemoved=%s , hw_init_completed=%d, bDriverStopped=%s\\n\", __func__\n\t\t\t , rtw_is_surprise_removed(padapter) ? \"True\" : \"False\"\n\t\t\t , rtw_get_hw_init_completed(padapter)\n\t\t\t , rtw_is_drv_stopped(padapter) ? \"True\" : \"False\");\n\t\tgoto exit_fw_ps_state;\n\t}\n\t#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)\n\trtw_hal_get_hwreg(padapter, HW_VAR_FW_PS_STATE, (u8 *)&fw_ps_state);\n\tif ((fw_ps_state & BIT_LPS_STATUS) == 0)\n\t\tret = _SUCCESS;\n\telse {\n\t\tpdbgpriv->dbg_poll_fail_cnt++;\n\t\tRTW_INFO(\"%s: fw_ps_state=%04x\\n\", __FUNCTION__, fw_ps_state);\n\t}\n\t#else\n\trtw_hal_set_hwreg(padapter, HW_VAR_SET_REQ_FW_PS, (u8 *)&dont_care);\n\t{\n\t\t/* 4. if 0x88[7]=1, driver set cmd to leave LPS/IPS. */\n\t\t/* Else, hw will keep in active mode. */\n\t\t/* debug info: */\n\t\t/* 0x88[7] = 32kpermission, */\n\t\t/* 0x88[6:0] = current_ps_state */\n\t\t/* 0x89[7:0] = last_rpwm */\n\n\t\trtw_hal_get_hwreg(padapter, HW_VAR_FW_PS_STATE, (u8 *)&fw_ps_state);\n\n\t\tif ((fw_ps_state & 0x80) == 0)\n\t\t\tret = _SUCCESS;\n\t\telse {\n\t\t\tpdbgpriv->dbg_poll_fail_cnt++;\n\t\t\tRTW_INFO(\"%s: fw_ps_state=%04x\\n\", __FUNCTION__, fw_ps_state);\n\t\t}\n\t}\n\t#endif\n\nexit_fw_ps_state:\n\t_exit_pwrlock(&pwrpriv->check_32k_lock);\n\treturn ret;\n}\n#endif /*DBG_CHECK_FW_PS_STATE*/\n#ifdef CONFIG_IPS\nvoid _ips_enter(_adapter *padapter)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\n\tpwrpriv->bips_processing = _TRUE;\n\n\t/* syn ips_mode with request */\n\tpwrpriv->ips_mode = pwrpriv->ips_mode_req;\n\n\tpwrpriv->ips_enter_cnts++;\n\tRTW_INFO(\"==>ips_enter cnts:%d\\n\", pwrpriv->ips_enter_cnts);\n\n\tif (rf_off == pwrpriv->change_rfpwrstate) {\n\t\tpwrpriv->bpower_saving = _TRUE;\n\t\tRTW_PRINT(\"nolinked power save enter\\n\");\n\n\t\tif (pwrpriv->ips_mode == IPS_LEVEL_2)\n\t\t\tpwrpriv->bkeepfwalive = _TRUE;\n\n#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS\t\t\n\t\tpwrpriv->pwr_saving_start_time = rtw_get_current_time();\n#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */\n\n\t\trtw_ips_pwr_down(padapter);\n\t\tpwrpriv->rf_pwrstate = rf_off;\n\t}\n\tpwrpriv->bips_processing = _FALSE;\n\n}\n\nvoid ips_enter(_adapter *padapter)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\n\n#ifdef CONFIG_BT_COEXIST\n\trtw_btcoex_IpsNotify(padapter, pwrpriv->ips_mode_req);\n#endif /* CONFIG_BT_COEXIST */\n\n\t_enter_pwrlock(&pwrpriv->lock);\n\t_ips_enter(padapter);\n\t_exit_pwrlock(&pwrpriv->lock);\n}\n\nint _ips_leave(_adapter *padapter)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tint result = _SUCCESS;\n\n\tif ((pwrpriv->rf_pwrstate == rf_off) && (!pwrpriv->bips_processing)) {\n\t\tpwrpriv->bips_processing = _TRUE;\n\t\tpwrpriv->change_rfpwrstate = rf_on;\n\t\tpwrpriv->ips_leave_cnts++;\n\t\tRTW_INFO(\"==>ips_leave cnts:%d\\n\", pwrpriv->ips_leave_cnts);\n\n\t\tresult = rtw_ips_pwr_up(padapter);\n\t\tif (result == _SUCCESS)\n\t\t\tpwrpriv->rf_pwrstate = rf_on;\n\t\t\n#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS\t\n\t\tpwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);\n#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */\n\n\t\tRTW_PRINT(\"nolinked power save leave\\n\");\n\n\t\tRTW_INFO(\"==> ips_leave.....LED(0x%08x)...\\n\", rtw_read32(padapter, 0x4c));\n\t\tpwrpriv->bips_processing = _FALSE;\n\n\t\tpwrpriv->bkeepfwalive = _FALSE;\n\t\tpwrpriv->bpower_saving = _FALSE;\n\t}\n\n\treturn result;\n}\n\nint ips_leave(_adapter *padapter)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n#ifdef DBG_CHECK_FW_PS_STATE\n\tstruct dvobj_priv *psdpriv = padapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &psdpriv->drv_dbg;\n#endif\n\tint ret;\n\n\tif (!is_primary_adapter(padapter))\n\t\treturn _SUCCESS;\n\n\t_enter_pwrlock(&pwrpriv->lock);\n\tret = _ips_leave(padapter);\n#ifdef DBG_CHECK_FW_PS_STATE\n\tif (rtw_fw_ps_state(padapter) == _FAIL) {\n\t\tRTW_INFO(\"ips leave doesn't leave 32k\\n\");\n\t\tpdbgpriv->dbg_leave_ips_fail_cnt++;\n\t}\n#endif /* DBG_CHECK_FW_PS_STATE */\n\t_exit_pwrlock(&pwrpriv->lock);\n\n\tif (_SUCCESS == ret)\n\t\todm_dm_reset(&GET_HAL_DATA(padapter)->odmpriv);\n\n#ifdef CONFIG_BT_COEXIST\n\tif (_SUCCESS == ret)\n\t\trtw_btcoex_IpsNotify(padapter, IPS_NONE);\n#endif /* CONFIG_BT_COEXIST */\n\n\treturn ret;\n}\n#endif /* CONFIG_IPS */\n\n#ifdef CONFIG_AUTOSUSPEND\n\textern void autosuspend_enter(_adapter *padapter);\n\textern int autoresume_enter(_adapter *padapter);\n#endif\n\n#ifdef SUPPORT_HW_RFOFF_DETECTED\n\tint rtw_hw_suspend(_adapter *padapter);\n\tint rtw_hw_resume(_adapter *padapter);\n#endif\n\nbool rtw_pwr_unassociated_idle(_adapter *adapter)\n{\n\tu8 i;\n\t_adapter *iface;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct xmit_priv *pxmit_priv = &adapter->xmitpriv;\n\tstruct mlme_priv *pmlmepriv;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info\t*pwdinfo;\n#endif\n\n\tbool ret = _FALSE;\n\n\tif (adapter_to_pwrctl(adapter)->bpower_saving == _TRUE) {\n\t\t/* RTW_INFO(\"%s: already in LPS or IPS mode\\n\", __func__); */\n\t\tgoto exit;\n\t}\n\n\tif (rtw_time_after(adapter_to_pwrctl(adapter)->ips_deny_time, rtw_get_current_time())) {\n\t\t/* RTW_INFO(\"%s ips_deny_time\\n\", __func__); */\n\t\tgoto exit;\n\t}\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif ((iface) && rtw_is_adapter_up(iface)) {\n\t\t\tpmlmepriv = &(iface->mlmepriv);\n#ifdef CONFIG_P2P\n\t\t\tpwdinfo = &(iface->wdinfo);\n#endif\n\t\t\tif (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_SITE_MONITOR)\n\t\t\t\t|| check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)\n\t\t\t\t|| MLME_IS_AP(iface)\n\t\t\t\t|| MLME_IS_MESH(iface)\n\t\t\t\t|| check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE)\n\t\t\t\t#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211)\n\t\t\t\t|| rtw_cfg80211_get_is_roch(iface) == _TRUE\n\t\t\t\t|| (rtw_cfg80211_is_ro_ch_once(adapter)\n\t\t\t\t\t&& rtw_cfg80211_get_last_ro_ch_passing_ms(adapter) < 3000)\n\t\t\t\t#elif defined(CONFIG_P2P)\n\t\t\t\t|| rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)\n\t\t\t\t|| rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN)\n\t\t\t\t#endif\n\t\t\t)\n\t\t\t\tgoto exit;\n\n\t\t}\n\t}\n\n#if (MP_DRIVER == 1)\n\tif (adapter->registrypriv.mp_mode == 1)\n\t\tgoto exit;\n#endif\n\n\tif (pxmit_priv->free_xmitbuf_cnt != NR_XMITBUFF ||\n\t    pxmit_priv->free_xmit_extbuf_cnt != NR_XMIT_EXTBUFF) {\n\t\tRTW_PRINT(\"There are some pkts to transmit\\n\");\n\t\tRTW_PRINT(\"free_xmitbuf_cnt: %d, free_xmit_extbuf_cnt: %d\\n\",\n\t\t\tpxmit_priv->free_xmitbuf_cnt, pxmit_priv->free_xmit_extbuf_cnt);\n\t\tgoto exit;\n\t}\n\n\tret = _TRUE;\n\nexit:\n\treturn ret;\n}\n\n\n/*\n * ATTENTION:\n *\trtw_ps_processor() doesn't handle LPS.\n */\nvoid rtw_ps_processor(_adapter *padapter)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct dvobj_priv *psdpriv = padapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &psdpriv->drv_dbg;\n#ifdef SUPPORT_HW_RFOFF_DETECTED\n\trt_rf_power_state rfpwrstate;\n#endif /* SUPPORT_HW_RFOFF_DETECTED */\n\tu32 ps_deny = 0;\n\n\t_enter_pwrlock(&adapter_to_pwrctl(padapter)->lock);\n\tps_deny = rtw_ps_deny_get(padapter);\n\t_exit_pwrlock(&adapter_to_pwrctl(padapter)->lock);\n\tif (ps_deny != 0) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": ps_deny=0x%08X, skip power save!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter), ps_deny);\n\t\tgoto exit;\n\t}\n\n\tif (pwrpriv->bInSuspend == _TRUE) { /* system suspend or autosuspend */\n\t\tpdbgpriv->dbg_ps_insuspend_cnt++;\n\t\tRTW_INFO(\"%s, pwrpriv->bInSuspend == _TRUE ignore this process\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tpwrpriv->ps_processing = _TRUE;\n\n#ifdef SUPPORT_HW_RFOFF_DETECTED\n\tif (pwrpriv->bips_processing == _TRUE)\n\t\tgoto exit;\n\n\t/* RTW_INFO(\"==> fw report state(0x%x)\\n\",rtw_read8(padapter,0x1ca));\t */\n\tif (pwrpriv->bHWPwrPindetect) {\n#ifdef CONFIG_AUTOSUSPEND\n\t\tif (padapter->registrypriv.usbss_enable) {\n\t\t\tif (pwrpriv->rf_pwrstate == rf_on) {\n\t\t\t\tif (padapter->net_closed == _TRUE)\n\t\t\t\t\tpwrpriv->ps_flag = _TRUE;\n\n\t\t\t\trfpwrstate = RfOnOffDetect(padapter);\n\t\t\t\tRTW_INFO(\"@@@@- #1  %s==> rfstate:%s\\n\", __FUNCTION__, (rfpwrstate == rf_on) ? \"rf_on\" : \"rf_off\");\n\t\t\t\tif (rfpwrstate != pwrpriv->rf_pwrstate) {\n\t\t\t\t\tif (rfpwrstate == rf_off) {\n\t\t\t\t\t\tpwrpriv->change_rfpwrstate = rf_off;\n\n\t\t\t\t\t\tpwrpriv->bkeepfwalive = _TRUE;\n\t\t\t\t\t\tpwrpriv->brfoffbyhw = _TRUE;\n\n\t\t\t\t\t\tautosuspend_enter(padapter);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else\n#endif /* CONFIG_AUTOSUSPEND */\n\t\t{\n\t\t\trfpwrstate = RfOnOffDetect(padapter);\n\t\t\tRTW_INFO(\"@@@@- #2  %s==> rfstate:%s\\n\", __FUNCTION__, (rfpwrstate == rf_on) ? \"rf_on\" : \"rf_off\");\n\n\t\t\tif (rfpwrstate != pwrpriv->rf_pwrstate) {\n\t\t\t\tif (rfpwrstate == rf_off) {\n\t\t\t\t\tpwrpriv->change_rfpwrstate = rf_off;\n\t\t\t\t\tpwrpriv->brfoffbyhw = _TRUE;\n\t\t\t\t\trtw_hw_suspend(padapter);\n\t\t\t\t} else {\n\t\t\t\t\tpwrpriv->change_rfpwrstate = rf_on;\n\t\t\t\t\trtw_hw_resume(padapter);\n\t\t\t\t}\n\t\t\t\tRTW_INFO(\"current rf_pwrstate(%s)\\n\", (pwrpriv->rf_pwrstate == rf_off) ? \"rf_off\" : \"rf_on\");\n\t\t\t}\n\t\t}\n\t\tpwrpriv->pwr_state_check_cnts++;\n\t}\n#endif /* SUPPORT_HW_RFOFF_DETECTED */\n\n\tif (pwrpriv->ips_mode_req == IPS_NONE)\n\t\tgoto exit;\n\n\tif (rtw_pwr_unassociated_idle(padapter) == _FALSE)\n\t\tgoto exit;\n\n\tif ((pwrpriv->rf_pwrstate == rf_on) && ((pwrpriv->pwr_state_check_cnts % 4) == 0)) {\n\t\tRTW_INFO(\"==>%s .fw_state(%x)\\n\", __FUNCTION__, get_fwstate(pmlmepriv));\n#if defined(CONFIG_BT_COEXIST) && defined (CONFIG_AUTOSUSPEND)\n#else\n\t\tpwrpriv->change_rfpwrstate = rf_off;\n#endif\n#ifdef CONFIG_AUTOSUSPEND\n\t\tif (padapter->registrypriv.usbss_enable) {\n\t\t\tif (pwrpriv->bHWPwrPindetect)\n\t\t\t\tpwrpriv->bkeepfwalive = _TRUE;\n\n\t\t\tif (padapter->net_closed == _TRUE)\n\t\t\t\tpwrpriv->ps_flag = _TRUE;\n\n#if defined(CONFIG_BT_COEXIST) && defined (CONFIG_AUTOSUSPEND)\n\t\t\tif (_TRUE == pwrpriv->bInternalAutoSuspend)\n\t\t\t\tRTW_INFO(\"<==%s .pwrpriv->bInternalAutoSuspend)(%x)\\n\", __FUNCTION__, pwrpriv->bInternalAutoSuspend);\n\t\t\telse {\n\t\t\t\tpwrpriv->change_rfpwrstate = rf_off;\n\t\t\t\tRTW_INFO(\"<==%s .pwrpriv->bInternalAutoSuspend)(%x) call autosuspend_enter\\n\", __FUNCTION__, pwrpriv->bInternalAutoSuspend);\n\t\t\t\tautosuspend_enter(padapter);\n\t\t\t}\n#else\n\t\t\tautosuspend_enter(padapter);\n#endif\t/* if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) */\n\t\t} else if (pwrpriv->bHWPwrPindetect) {\n\t\t} else\n#endif /* CONFIG_AUTOSUSPEND */\n\t\t{\n#if defined(CONFIG_BT_COEXIST) && defined (CONFIG_AUTOSUSPEND)\n\t\t\tpwrpriv->change_rfpwrstate = rf_off;\n#endif\t/* defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) */\n\n#ifdef CONFIG_IPS\n\t\t\tips_enter(padapter);\n#endif\n\t\t}\n\t}\nexit:\n#ifndef CONFIG_IPS_CHECK_IN_WD\n\trtw_set_pwr_state_check_timer(pwrpriv);\n#endif\n\tpwrpriv->ps_processing = _FALSE;\n\treturn;\n}\n\nvoid pwr_state_check_handler(void *ctx)\n{\n\t_adapter *padapter = (_adapter *)ctx;\n\trtw_ps_cmd(padapter);\n}\n\n#ifdef CONFIG_LPS\n#ifdef CONFIG_CHECK_LEAVE_LPS\n#ifdef CONFIG_LPS_CHK_BY_TP\nvoid traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info *sta)\n{\n\tstruct stainfo_stats *pstats = &sta->sta_stats;\n\tu64 cur_acc_tx_bytes = 0, cur_acc_rx_bytes = 0;\n\tu32 tx_tp_kbyte = 0, rx_tp_kbyte = 0;\n\tu32 tx_tp_th = 0, rx_tp_th = 0;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tu8\tleave_lps = _FALSE;\n\n\tif (tx) { /* from tx */\n\t\tcur_acc_tx_bytes = pstats->tx_bytes - pstats->acc_tx_bytes;\n\t\ttx_tp_kbyte = cur_acc_tx_bytes >> 10;\n\t\ttx_tp_th = pwrpriv->lps_tx_tp_th * 1024 / 8 * 2; /*KBytes @2s*/\n\n\t\tif (tx_tp_kbyte >= tx_tp_th ||\n\t\t\tpadapter->mlmepriv.LinkDetectInfo.NumTxOkInPeriod >= pwrpriv->lps_tx_pkts){\n\t\t\tif (pwrpriv->bLeisurePs\n\t\t\t\t&& (pwrpriv->pwr_mode != PS_MODE_ACTIVE)\n\t\t\t\t#ifdef CONFIG_BT_COEXIST\n\t\t\t\t&& (rtw_btcoex_IsBtControlLps(padapter) == _FALSE)\n\t\t\t\t#endif\n\t\t\t) {\n\t\t\t\tleave_lps = _TRUE;\n\t\t\t}\n\t\t}\n\n\t} else { /* from rx path */\n\t\tcur_acc_rx_bytes = pstats->rx_bytes - pstats->acc_rx_bytes;\n\t\trx_tp_kbyte = cur_acc_rx_bytes >> 10;\n\t\trx_tp_th = pwrpriv->lps_rx_tp_th * 1024 / 8 * 2;\n\n\t\tif (rx_tp_kbyte>= rx_tp_th ||\n\t\t\tpadapter->mlmepriv.LinkDetectInfo.NumRxUnicastOkInPeriod >= pwrpriv->lps_rx_pkts) {\n\t\t\tif (pwrpriv->bLeisurePs\n\t\t\t\t&& (pwrpriv->pwr_mode != PS_MODE_ACTIVE)\n\t\t\t\t#ifdef CONFIG_BT_COEXIST\n\t\t\t\t&& (rtw_btcoex_IsBtControlLps(padapter) == _FALSE)\n\t\t\t\t#endif\n\t\t\t) {\n\t\t\t\tleave_lps = _TRUE;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (leave_lps) {\n\t\t#ifdef DBG_LPS_CHK_BY_TP\n\t\tRTW_INFO(\"leave lps via %s, \", tx ? \"Tx\" : \"Rx\");\n\t\tif (tx)\n\t\t\tRTW_INFO(\"Tx = %d [%d] (KB)\\n\", tx_tp_kbyte, tx_tp_th);\n\t\telse\n\t\t\tRTW_INFO(\"Rx = %d [%d] (KB)\\n\", rx_tp_kbyte, rx_tp_th);\n\t\t#endif\n\t\tpwrpriv->lps_chk_cnt = pwrpriv->lps_chk_cnt_th;\n\t\t/* rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0); */\n\t\trtw_lps_ctrl_wk_cmd(padapter, tx ? LPS_CTRL_TX_TRAFFIC_LEAVE : LPS_CTRL_RX_TRAFFIC_LEAVE, 0);\n\t}\n}\n#endif /*CONFIG_LPS_CHK_BY_TP*/\n\nvoid\ttraffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets)\n{\n\tstatic systime start_time = 0;\n\tstatic u32 xmit_cnt = 0;\n\tu8\tbLeaveLPS = _FALSE;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\n\n\n\tif (tx) { /* from tx */\n\t\txmit_cnt += tx_packets;\n\n\t\tif (start_time == 0)\n\t\t\tstart_time = rtw_get_current_time();\n\n\t\tif (rtw_get_passing_time_ms(start_time) > 2000) { /* 2 sec == watch dog timer */\n\t\t\tif (xmit_cnt > 8) {\n\t\t\t\tif ((adapter_to_pwrctl(padapter)->bLeisurePs)\n\t\t\t\t    && (adapter_to_pwrctl(padapter)->pwr_mode != PS_MODE_ACTIVE)\n#ifdef CONFIG_BT_COEXIST\n\t\t\t\t    && (rtw_btcoex_IsBtControlLps(padapter) == _FALSE)\n#endif\n\t\t\t\t   ) {\n\t\t\t\t\t/* RTW_INFO(\"leave lps via Tx = %d\\n\", xmit_cnt);\t\t\t */\n\t\t\t\t\tbLeaveLPS = _TRUE;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tstart_time = rtw_get_current_time();\n\t\t\txmit_cnt = 0;\n\t\t}\n\n\t} else { /* from rx path */\n\t\tif (pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 4/*2*/) {\n\t\t\tif ((adapter_to_pwrctl(padapter)->bLeisurePs)\n\t\t\t    && (adapter_to_pwrctl(padapter)->pwr_mode != PS_MODE_ACTIVE)\n#ifdef CONFIG_BT_COEXIST\n\t\t\t    && (rtw_btcoex_IsBtControlLps(padapter) == _FALSE)\n#endif\n\t\t\t   ) {\n\t\t\t\t/* RTW_INFO(\"leave lps via Rx = %d\\n\", pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod);\t */\n\t\t\t\tbLeaveLPS = _TRUE;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (bLeaveLPS) {\n\t\t/* RTW_INFO(\"leave lps via %s, Tx = %d, Rx = %d\\n\", tx?\"Tx\":\"Rx\", pmlmepriv->LinkDetectInfo.NumTxOkInPeriod,pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod);\t */\n\t\t/* rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0); */\n\t\trtw_lps_ctrl_wk_cmd(padapter, tx ? LPS_CTRL_TX_TRAFFIC_LEAVE : LPS_CTRL_RX_TRAFFIC_LEAVE, tx ? RTW_CMDF_DIRECTLY : 0);\n\t}\n}\n#endif /* CONFIG_CHECK_LEAVE_LPS */\n\n#ifdef CONFIG_LPS_LCLK\n#define LPS_CPWM_TIMEOUT_MS\t10 /*ms*/\n#define LPS_RPWM_RETRY_CNT\t\t3\n\nu8 rtw_cpwm_polling(_adapter *adapter, u8 rpwm, u8 cpwm_orig)\n{\n\tu8 rst = _FAIL;\n\tu8 cpwm_now = 0;\n\tsystime start_time;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\t#ifdef DBG_CHECK_FW_PS_STATE\n\tstruct debug_priv *pdbgpriv = &(adapter_to_dvobj(adapter)->drv_dbg);\n\t#endif\n\n\tpwrpriv->rpwm_retry = 0;\n\n\tdo {\n\t\tstart_time = rtw_get_current_time();\n\t\tdo {\n\t\t\trtw_msleep_os(1);\n\t\t\trtw_hal_get_hwreg(adapter, HW_VAR_CPWM, &cpwm_now);\n\n\t\t\tif ((cpwm_orig ^ cpwm_now) & 0x80) {\n\t\t\t\tpwrpriv->cpwm = PS_STATE_S4;\n\t\t\t\tpwrpriv->cpwm_tog = cpwm_now & PS_TOGGLE;\n\t\t\t\trst = _SUCCESS;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} while (rtw_get_passing_time_ms(start_time) < LPS_CPWM_TIMEOUT_MS && !RTW_CANNOT_RUN(adapter));\n\n\t\tif (rst == _SUCCESS)\n\t\t\tbreak;\n\t\telse {\n\t\t\t/* rpwm retry */\n\t\t\tcpwm_orig = cpwm_now;\n\t\t\trpwm &= ~PS_TOGGLE;\n\t\t\trpwm |= pwrpriv->tog;\n\t\t\trtw_hal_set_hwreg(adapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));\n\t\t\tpwrpriv->tog += 0x80;\n\t\t}\n\t} while (pwrpriv->rpwm_retry++ < LPS_RPWM_RETRY_CNT && !RTW_CANNOT_RUN(adapter));\n\n\tif (rst == _SUCCESS) {\n\t\t#ifdef DBG_CHECK_FW_PS_STATE\n\t\tRTW_INFO(\"%s: polling cpwm OK! rpwm_retry=%d, cpwm_orig=%02x, cpwm_now=%02x , 0x100=0x%x\\n\"\n\t\t\t, __func__, pwrpriv->rpwm_retry, cpwm_orig, cpwm_now, rtw_read8(adapter, REG_CR));\n\t\tif (rtw_fw_ps_state(adapter) == _FAIL) {\n\t\t\tRTW_INFO(\"leave 32k but fw state in 32k\\n\");\n\t\t\tpdbgpriv->dbg_rpwm_toogle_cnt++;\n\t\t}\n\t\t#endif /* DBG_CHECK_FW_PS_STATE */\n\t} else {\n\t\tRTW_ERR(\"%s: polling cpwm timeout! rpwm_retry=%d, cpwm_orig=%02x, cpwm_now=%02x\\n\"\n\t\t\t\t, __func__, pwrpriv->rpwm_retry, cpwm_orig, cpwm_now);\n\t\t#ifdef DBG_CHECK_FW_PS_STATE\n\t\tif (rtw_fw_ps_state(adapter) == _FAIL) {\n\t\t\tRTW_INFO(\"rpwm timeout and fw ps state in 32k\\n\");\n\t\t\tpdbgpriv->dbg_rpwm_timeout_fail_cnt++;\n\t\t}\n\t\t#endif /* DBG_CHECK_FW_PS_STATE */\n\n\t\t#ifdef CONFIG_LPS_RPWM_TIMER\n\t\t_set_timer(&pwrpriv->pwr_rpwm_timer, 1);\n\t\t#endif /* CONFIG_LPS_RPWM_TIMER */\n\t}\n\n\treturn rst;\n}\n#endif\n/*\n * Description:\n *\tThis function MUST be called under power lock protect\n *\n * Parameters\n *\tpadapter\n *\tpslv\t\t\tpower state level, only could be PS_STATE_S0 ~ PS_STATE_S4\n *\n */\nu8 rtw_set_rpwm(PADAPTER padapter, u8 pslv)\n{\n\tu8\trpwm = 0xFF;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n#ifdef CONFIG_LPS_LCLK\n\tu8 cpwm_orig;\n#endif\n\n\tpslv = PS_STATE(pslv);\n\n#ifdef CONFIG_LPS_RPWM_TIMER\n\tif (pwrpriv->brpwmtimeout == _TRUE)\n\t\tRTW_INFO(\"%s: RPWM timeout, force to set RPWM(0x%02X) again!\\n\", __FUNCTION__, pslv);\n\telse\n#endif /* CONFIG_LPS_RPWM_TIMER */\n\t{\n\t\tif ((pwrpriv->rpwm == pslv)\n#ifdef CONFIG_LPS_LCLK\n\t\t    || ((pwrpriv->rpwm >= PS_STATE_S2) && (pslv >= PS_STATE_S2))\n#endif\n\t\t\t|| (pwrpriv->lps_level == LPS_NORMAL)\n\t\t   ) {\n\t\t\treturn rpwm;\n\t\t}\n\t}\n\n\tif (rtw_is_surprise_removed(padapter) ||\n\t    (!rtw_is_hw_init_completed(padapter))) {\n\n\t\tpwrpriv->cpwm = PS_STATE_S4;\n\n\t\treturn rpwm;\n\t}\n\n\tif (rtw_is_drv_stopped(padapter))\n\t\tif (pslv < PS_STATE_S2)\n\t\t\treturn rpwm;\n\n\trpwm = pslv | pwrpriv->tog;\n#ifdef CONFIG_LPS_LCLK\n\t/* only when from PS_STATE S0/S1 to S2 and higher needs ACK */\n\tif ((pwrpriv->cpwm < PS_STATE_S2) && (pslv >= PS_STATE_S2))\n\t\trpwm |= PS_ACK;\n#endif\n\n\tpwrpriv->rpwm = pslv;\n\n#ifdef CONFIG_LPS_LCLK\n\tcpwm_orig = 0;\n\tif (rpwm & PS_ACK)\n\t\trtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);\n#endif\n\n#if defined(CONFIG_LPS_RPWM_TIMER) && !defined(CONFIG_DETECT_CPWM_BY_POLLING)\n\tif (rpwm & PS_ACK) {\n\t\t#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)\n\t\tif (pwrpriv->wowlan_mode != _TRUE &&\n\t\t\tpwrpriv->wowlan_ap_mode != _TRUE &&\n\t\t\tpwrpriv->wowlan_p2p_mode != _TRUE)\n\t\t#endif\n\t\t_set_timer(&pwrpriv->pwr_rpwm_timer, LPS_CPWM_TIMEOUT_MS);\n\t}\n#endif /* CONFIG_LPS_RPWM_TIMER & !CONFIG_DETECT_CPWM_BY_POLLING */\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));\n\n\tpwrpriv->tog += 0x80;\n\n#ifdef CONFIG_LPS_LCLK\n\t/* No LPS 32K, No Ack */\n\tif (rpwm & PS_ACK) {\n\t\t#ifdef CONFIG_DETECT_CPWM_BY_POLLING\n\t\trtw_cpwm_polling(padapter, rpwm, cpwm_orig);\n\t\t#else\n\t\t#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)\n\t\tif (pwrpriv->wowlan_mode == _TRUE ||\n\t\t\tpwrpriv->wowlan_ap_mode == _TRUE ||\n\t\t\tpwrpriv->wowlan_p2p_mode == _TRUE)\n\t\t\t\trtw_cpwm_polling(padapter, rpwm, cpwm_orig);\n\t\t#endif /*#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)*/\n\t\t#endif /*#ifdef CONFIG_DETECT_CPWM_BY_POLLING*/\n\t} else\n#endif /* CONFIG_LPS_LCLK */\n\t{\n\t\tpwrpriv->cpwm = pslv;\n\t}\n\n\treturn rpwm;\n}\n\nu8 PS_RDY_CHECK(_adapter *padapter)\n{\n\tstruct pwrctrl_priv\t*pwrpriv = adapter_to_pwrctl(padapter);\n\tstruct mlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\n\tif (_TRUE == pwrpriv->bInSuspend && pwrpriv->wowlan_mode)\n\t\treturn _TRUE;\n\telse if (_TRUE == pwrpriv->bInSuspend && pwrpriv->wowlan_ap_mode)\n\t\treturn _TRUE;\n\telse if (_TRUE == pwrpriv->bInSuspend)\n\t\treturn _FALSE;\n#else\n\tif (_TRUE == pwrpriv->bInSuspend)\n\t\treturn _FALSE;\n#endif\n\n\tif (rtw_time_after(pwrpriv->lps_deny_time, rtw_get_current_time()))\n\t\treturn _FALSE;\n\n\tif (check_fwstate(pmlmepriv, WIFI_SITE_MONITOR)\n\t\t|| check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)\n\t\t|| MLME_IS_AP(padapter)\n\t\t|| MLME_IS_MESH(padapter)\n\t\t|| check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE)\n\t\t#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211)\n\t\t|| rtw_cfg80211_get_is_roch(padapter) == _TRUE\n\t\t#endif\n\t\t|| rtw_is_scan_deny(padapter)\n\t\t#ifdef CONFIG_TDLS\n\t\t/* TDLS link is established. */\n\t\t|| (padapter->tdlsinfo.link_established == _TRUE)\n\t\t#endif /* CONFIG_TDLS\t\t */\n\t\t#ifdef CONFIG_DFS_MASTER\n\t\t|| adapter_to_rfctl(padapter)->radar_detect_enabled\n\t\t#endif\n\t)\n\t\treturn _FALSE;\n\n\tif ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) && (padapter->securitypriv.binstallGrpkey == _FALSE)) {\n\t\tRTW_INFO(\"Group handshake still in progress !!!\\n\");\n\t\treturn _FALSE;\n\t}\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (!rtw_cfg80211_pwr_mgmt(padapter))\n\t\treturn _FALSE;\n#endif\n\n\treturn _TRUE;\n}\n\n#if defined(CONFIG_FWLPS_IN_IPS)\nvoid rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tint cnt = 0;\n\tsystime start_time;\n\tu8 val8 = 0;\n\tu8 cpwm_orig = 0, cpwm_now = 0;\n\tu8 parm[H2C_INACTIVE_PS_LEN] = {0};\n\n\tif (padapter->netif_up == _FALSE) {\n\t\tRTW_INFO(\"%s: ERROR, netif is down\\n\", __func__);\n\t\treturn;\n\t}\n\n\t/* u8 cmd_param; */ /* BIT0:enable, BIT1:NoConnect32k */\n\tif (enable) {\n#ifdef CONFIG_BT_COEXIST\n\t\trtw_btcoex_IpsNotify(padapter, pwrpriv->ips_mode_req);\n#endif\n\t\t/* Enter IPS */\n\t\tRTW_INFO(\"%s: issue H2C to FW when entering IPS\\n\", __func__);\n\n\t\tparm[0] = 0x1;/* suggest by Isaac.Hsu*/\n#ifdef CONFIG_PNO_SUPPORT\n\t\tif (pwrpriv->pno_inited) {\n\t\t\tparm[1] = pwrpriv->pnlo_info->fast_scan_iterations;\n\t\t\tparm[2] = pwrpriv->pnlo_info->slow_scan_period;\n\t\t}\n#endif\n\n\t\trtw_hal_fill_h2c_cmd(padapter, /* H2C_FWLPS_IN_IPS_, */\n\t\t\t\t     H2C_INACTIVE_PS_,\n\t\t\t\t     H2C_INACTIVE_PS_LEN, parm);\n\t\t/* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW. */\n\t\tdo {\n\t\t\tval8 = rtw_read8(padapter, REG_HMETFR);\n\t\t\tcnt++;\n\t\t\tRTW_INFO(\"%s  polling REG_HMETFR=0x%x, cnt=%d\\n\",\n\t\t\t\t __func__, val8, cnt);\n\t\t\trtw_mdelay_os(10);\n\t\t} while (cnt < 100 && (val8 != 0));\n\n#ifdef CONFIG_LPS_LCLK\n\t\t/* H2C done, enter 32k */\n\t\tif (val8 == 0) {\n\t\t\t/* ser rpwm to enter 32k */\n\t\t\trtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &val8);\n\t\t\tRTW_INFO(\"%s: read rpwm=%02x\\n\", __FUNCTION__, val8);\n\t\t\tval8 += 0x80;\n\t\t\tval8 |= BIT(0);\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&val8));\n\t\t\tRTW_INFO(\"%s: write rpwm=%02x\\n\", __FUNCTION__, val8);\n\t\t\tadapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;\n\t\t\tcnt = val8 = 0;\n\t\t\tif (parm[1] == 0 || parm[2] == 0) {\n\t\t\t\tdo {\n\t\t\t\t\tval8 = rtw_read8(padapter, REG_CR);\n\t\t\t\t\tcnt++;\n\t\t\t\t\tRTW_INFO(\"%s  polling 0x100=0x%x, cnt=%d\\n\",\n\t\t\t\t\t\t __func__, val8, cnt);\n\t\t\t\t\tRTW_INFO(\"%s 0x08:%02x, 0x03:%02x\\n\",\n\t\t\t\t\t\t __func__,\n\t\t\t\t\t\t rtw_read8(padapter, 0x08),\n\t\t\t\t\t\t rtw_read8(padapter, 0x03));\n\t\t\t\t\trtw_mdelay_os(10);\n\t\t\t\t} while (cnt < 20 && (val8 != 0xEA));\n\t\t\t}\n\t\t}\n#endif\n\t} else {\n\t\t/* Leave IPS */\n\t\tRTW_INFO(\"%s: Leaving IPS in FWLPS state\\n\", __func__);\n\n#ifdef CONFIG_LPS_LCLK\n\t\t/* for polling cpwm */\n\t\tcpwm_orig = 0;\n\t\trtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);\n\n\t\t/* ser rpwm */\n\t\trtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &val8);\n\t\tval8 += 0x80;\n\t\tval8 |= BIT(6);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&val8));\n\t\tRTW_INFO(\"%s: write rpwm=%02x\\n\", __FUNCTION__, val8);\n\t\tadapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;\n\n\t\t/* do polling cpwm */\n\t\tstart_time = rtw_get_current_time();\n\t\tdo {\n\n\t\t\trtw_mdelay_os(1);\n\n\t\t\trtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);\n\t\t\tif ((cpwm_orig ^ cpwm_now) & 0x80)\n\t\t\t\tbreak;\n\n\t\t\tif (rtw_get_passing_time_ms(start_time) > 100) {\n\t\t\t\tRTW_INFO(\"%s: polling cpwm timeout when leaving IPS in FWLPS state\\n\", __FUNCTION__);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} while (1);\n\n#endif\n\t\tparm[0] = 0x0;\n\t\tparm[1] = 0x0;\n\t\tparm[2] = 0x0;\n\t\trtw_hal_fill_h2c_cmd(padapter, H2C_INACTIVE_PS_,\n\t\t\t\t     H2C_INACTIVE_PS_LEN, parm);\n#ifdef CONFIG_BT_COEXIST\n\t\trtw_btcoex_IpsNotify(padapter, IPS_NONE);\n#endif\n\t}\n}\n#endif /* CONFIG_PNO_SUPPORT */\n\nvoid rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tstruct mlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)\n\tstruct dvobj_priv *psdpriv = padapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &psdpriv->drv_dbg;\n#endif\n#ifdef CONFIG_WMMPS_STA\t\n\tstruct registry_priv *pregistrypriv = &padapter->registrypriv;\n#endif\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n#endif /* CONFIG_P2P */\n#ifdef CONFIG_TDLS\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\t_irqL irqL;\n\tint i, j;\n\t_list\t*plist, *phead;\n\tstruct sta_info *ptdls_sta;\n#endif /* CONFIG_TDLS */\n#ifdef CONFIG_LPS_PG\n\tu8 lps_pg_hdl_id = 0;\n#endif\n\n\n\n\tif (ps_mode > PM_Card_Disable) {\n\t\treturn;\n\t}\n\n\tif (pwrpriv->pwr_mode == ps_mode) {\n\t\tif (PS_MODE_ACTIVE == ps_mode)\n\t\t\treturn;\n\n#ifndef CONFIG_BT_COEXIST\n#ifdef CONFIG_WMMPS_STA\t\n\t\tif (!rtw_is_wmmps_mode(padapter))\n#endif /* CONFIG_WMMPS_STA */\n\t\t\tif ((pwrpriv->smart_ps == smart_ps) &&\n\t\t\t    (pwrpriv->bcn_ant_mode == bcn_ant_mode))\n\t\t\t\treturn;\n#endif /* !CONFIG_BT_COEXIST */\n\t}\n\n#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\tif (PS_MODE_ACTIVE != ps_mode) {\n\t\trtw_set_ps_rsvd_page(padapter);\n\t\trtw_set_default_port_id(padapter);\n\t}\n#endif\n\n#ifdef CONFIG_LPS_PG\n\tif ((PS_MODE_ACTIVE != ps_mode) && (pwrpriv->lps_level == LPS_PG)) {\n\t\tif (pwrpriv->wowlan_mode != _TRUE) {\n\t\t\t\t/*rtw_hal_set_lps_pg_info(padapter);*/\n\t\t\t\tlps_pg_hdl_id = LPS_PG_INFO_CFG;\n\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));\n\t\t}\n\t}\n#endif\n\n#ifdef CONFIG_LPS_LCLK\n\t_enter_pwrlock(&pwrpriv->lock);\n#endif\n\n\t/* if(pwrpriv->pwr_mode == PS_MODE_ACTIVE) */\n\tif (ps_mode == PS_MODE_ACTIVE) {\n\t\tif (1\n#ifdef CONFIG_BT_COEXIST\n\t\t    && (((rtw_btcoex_IsBtControlLps(padapter) == _FALSE)\n#ifdef CONFIG_P2P_PS\n\t\t\t && (pwdinfo->opp_ps == 0)\n#endif /* CONFIG_P2P_PS */\n\t\t\t)\n\t\t\t|| ((rtw_btcoex_IsBtControlLps(padapter) == _TRUE)\n\t\t\t    && (rtw_btcoex_IsLpsOn(padapter) == _FALSE))\n\t\t       )\n#else /* !CONFIG_BT_COEXIST */\n#ifdef CONFIG_P2P_PS\n\t\t    && (pwdinfo->opp_ps == 0)\n#endif /* CONFIG_P2P_PS */\n#endif /* !CONFIG_BT_COEXIST */\n\t\t   ) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" Leave 802.11 power save - %s\\n\",\n\t\t\t\t FUNC_ADPT_ARG(padapter), msg);\n\n\t\t\tif (pwrpriv->lps_leave_cnts < UINT_MAX)\n\t\t\t\tpwrpriv->lps_leave_cnts++;\n\t\t\telse\n\t\t\t\tpwrpriv->lps_leave_cnts = 0;\n#ifdef CONFIG_TDLS\n\t\t\tfor (i = 0; i < NUM_STA; i++) {\n\t\t\t\tphead = &(pstapriv->sta_hash[i]);\n\t\t\t\tplist = get_next(phead);\n\n\t\t\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\t\t\tptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\n\t\t\t\t\tif (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)\n\t\t\t\t\t\tissue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 0, 0);\n\t\t\t\t\tplist = get_next(plist);\n\t\t\t\t}\n\t\t\t}\n#endif /* CONFIG_TDLS */\n\n\t\t\tpwrpriv->pwr_mode = ps_mode;\n\t\t\trtw_set_rpwm(padapter, PS_STATE_S4);\n\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)\n\t\t\tif (pwrpriv->wowlan_mode == _TRUE ||\n\t\t\t    pwrpriv->wowlan_ap_mode == _TRUE ||\n\t\t\t    pwrpriv->wowlan_p2p_mode == _TRUE) {\n\t\t\t\tsystime start_time;\n\t\t\t\tu32 delay_ms;\n\t\t\t\tu8 val8;\n\t\t\t\tdelay_ms = 20;\n\t\t\t\tstart_time = rtw_get_current_time();\n\t\t\t\tdo {\n\t\t\t\t\trtw_hal_get_hwreg(padapter, HW_VAR_SYS_CLKR, &val8);\n\t\t\t\t\tif (!(val8 & BIT(4))) { /* 0x08 bit4 =1 --> in 32k, bit4 = 0 --> leave 32k */\n\t\t\t\t\t\tpwrpriv->cpwm = PS_STATE_S4;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t\tif (rtw_get_passing_time_ms(start_time) > delay_ms) {\n\t\t\t\t\t\tRTW_INFO(\"%s: Wait for FW 32K leave more than %u ms!!!\\n\",\n\t\t\t\t\t\t\t__FUNCTION__, delay_ms);\n\t\t\t\t\t\tpdbgpriv->dbg_wow_leave_ps_fail_cnt++;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t\trtw_usleep_os(100);\n\t\t\t\t} while (1);\n\t\t\t}\n#endif\n#ifdef CONFIG_LPS_PG\n\t\t\tif (pwrpriv->lps_level == LPS_PG) {\n\t\t\t\tlps_pg_hdl_id = LPS_PG_REDLEMEM;\n\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));\n\t\t\t}\n#endif\n#ifdef CONFIG_WOWLAN\n\t\t\tif (pwrpriv->wowlan_mode == _TRUE)\n\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_H2C_INACTIVE_IPS, (u8 *)(&ps_mode));\n#endif /* CONFIG_WOWLAN */\n\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode));\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_LPS_STATE_CHK, (u8 *)(&ps_mode));\n\n\n#ifdef CONFIG_LPS_PG\n\t\t\tif (pwrpriv->lps_level == LPS_PG) {\n\t\t\t\tlps_pg_hdl_id = LPS_PG_PHYDM_EN;\n\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));\n\t\t\t}\n#endif\n\n#ifdef CONFIG_LPS_POFF\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_SET_MODE,\n\t\t\t\t\t  (u8 *)(&ps_mode));\n#endif /*CONFIG_LPS_POFF*/\n\n\t\t\tpwrpriv->bFwCurrentInPSMode = _FALSE;\n\n#ifdef CONFIG_BT_COEXIST\n\t\t\trtw_btcoex_LpsNotify(padapter, ps_mode);\n#endif /* CONFIG_BT_COEXIST */\n\t\t}\n\t} else {\n\t\tif ((PS_RDY_CHECK(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE))\n#ifdef CONFIG_BT_COEXIST\n\t\t    || ((rtw_btcoex_IsBtControlLps(padapter) == _TRUE)\n\t\t\t&& (rtw_btcoex_IsLpsOn(padapter) == _TRUE))\n#endif\n#ifdef CONFIG_P2P_WOWLAN\n\t\t    || (_TRUE == pwrpriv->wowlan_p2p_mode)\n#endif /* CONFIG_P2P_WOWLAN */\n#ifdef CONFIG_WOWLAN\n\t\t\t|| WOWLAN_IS_STA_MIX_MODE(padapter)\n#endif /* CONFIG_WOWLAN */\n\t\t   ) {\n\t\t\tu8 pslv;\n\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" Enter 802.11 power save - %s\\n\",\n\t\t\t\t FUNC_ADPT_ARG(padapter), msg);\n\n\t\t\tif (pwrpriv->lps_enter_cnts < UINT_MAX)\n\t\t\t\tpwrpriv->lps_enter_cnts++;\n\t\t\telse\n\t\t\t\tpwrpriv->lps_enter_cnts = 0;\n#ifdef CONFIG_TDLS\n\t\t\tfor (i = 0; i < NUM_STA; i++) {\n\t\t\t\tphead = &(pstapriv->sta_hash[i]);\n\t\t\t\tplist = get_next(phead);\n\n\t\t\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\t\t\tptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\n\t\t\t\t\tif (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)\n\t\t\t\t\t\tissue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 1, 0, 0);\n\t\t\t\t\tplist = get_next(plist);\n\t\t\t\t}\n\t\t\t}\n#endif /* CONFIG_TDLS */\n\n#ifdef CONFIG_BT_COEXIST\n\t\t\trtw_btcoex_LpsNotify(padapter, ps_mode);\n#endif /* CONFIG_BT_COEXIST */\n\n#ifdef CONFIG_LPS_POFF\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_SET_MODE,\n\t\t\t\t\t  (u8 *)(&ps_mode));\n#endif /*CONFIG_LPS_POFF*/\n\n\t\t\tpwrpriv->bFwCurrentInPSMode = _TRUE;\n\t\t\tpwrpriv->pwr_mode = ps_mode;\n\t\t\tpwrpriv->smart_ps = smart_ps;\n\t\t\tpwrpriv->bcn_ant_mode = bcn_ant_mode;\n#ifdef CONFIG_LPS_PG\n\t\t\tif (pwrpriv->lps_level == LPS_PG) {\n\t\t\t\tlps_pg_hdl_id = LPS_PG_PHYDM_DIS;\n\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));\n\t\t\t}\n#endif\n\n#ifdef CONFIG_WMMPS_STA\t\n\t\t\tpwrpriv->wmm_smart_ps = pregistrypriv->wmm_smart_ps;\n#endif /* CONFIG_WMMPS_STA */\n\t\t\t\n\t\t\t\n\t\t\tif (check_fwstate(pmlmepriv, _FW_LINKED))\n\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode));\n#ifdef CONFIG_WOWLAN\n\t\t\tif (pwrpriv->wowlan_mode == _TRUE)\n\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_H2C_INACTIVE_IPS, (u8 *)(&ps_mode));\n#endif /* CONFIG_WOWLAN */\n\n#ifdef CONFIG_P2P_PS\n\t\t\t/* Set CTWindow after LPS */\n\t\t\tif (pwdinfo->opp_ps == 1)\n\t\t\t\tp2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 0);\n#endif /* CONFIG_P2P_PS */\n\n\t\t\tpslv = PS_STATE_S2;\n#ifdef CONFIG_LPS_LCLK\n\t\t\tif (pwrpriv->alives == 0)\n\t\t\t\tpslv = PS_STATE_S0;\n#endif /* CONFIG_LPS_LCLK */\n\n#ifdef CONFIG_BT_COEXIST\n\t\t\tif ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE)\n\t\t\t    && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) {\n\t\t\t\tu8 val8;\n\n\t\t\t\tval8 = rtw_btcoex_LpsVal(padapter);\n\t\t\t\tif (val8 & BIT(4))\n\t\t\t\t\tpslv = PS_STATE_S2;\n\n\t\t\t}\n#endif /* CONFIG_BT_COEXIST */\n\n\t\t\trtw_set_rpwm(padapter, pslv);\n\t\t}\n\t}\n\n#ifdef CONFIG_LPS_LCLK\n\t_exit_pwrlock(&pwrpriv->lock);\n#endif\n\n}\n\n/*\n *\tDescription:\n *\t\tEnter the leisure power save mode.\n *   */\nvoid LPS_Enter(PADAPTER padapter, const char *msg)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct pwrctrl_priv\t*pwrpriv = dvobj_to_pwrctl(dvobj);\n\tint i;\n\tchar buf[32] = {0};\n#ifdef DBG_LA_MODE\n\tstruct registry_priv *registry_par = &(padapter->registrypriv);\n#endif\n\n\t/*\tRTW_INFO(\"+LeisurePSEnter\\n\"); */\n\tif (GET_HAL_DATA(padapter)->bFWReady == _FALSE)\n\t\treturn;\n\n#ifdef CONFIG_BT_COEXIST\n\tif (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)\n\t\treturn;\n#endif\n\n#ifdef DBG_LA_MODE\n\tif(registry_par->la_mode_en == 1) {\n\t\tRTW_INFO(\"%s LA debug mode lps_leave \\n\", __func__);\n\t\treturn;\n\t}\n#endif\n\t/* Skip lps enter request if number of assocated adapters is not 1 */\n\tif (rtw_mi_get_assoc_if_num(padapter) != 1)\n\t\treturn;\n\n#ifndef CONFIG_FW_MULTI_PORT_SUPPORT\n\t/* Skip lps enter request for adapter not port0 */\n\tif (get_hw_port(padapter) != HW_PORT0)\n\t\treturn;\n#endif\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tif (PS_RDY_CHECK(dvobj->padapters[i]) == _FALSE)\n\t\t\treturn;\n\t}\n\n#ifdef CONFIG_CLIENT_PORT_CFG\n\tif ((rtw_hal_get_port(padapter) == CLT_PORT_INVALID) ||\n\t\tget_clt_num(padapter) > MAX_CLIENT_PORT_NUM){\n\t\tRTW_ERR(ADPT_FMT\" cannot get client port or clt num(%d) over than 4\\n\", ADPT_ARG(padapter), get_clt_num(padapter));\n\t\treturn;\n\t}\n#endif\n\n#ifdef CONFIG_P2P_PS\n\tif (padapter->wdinfo.p2p_ps_mode == P2P_PS_NOA) {\n\t\treturn;/* supporting p2p client ps NOA via H2C_8723B_P2P_PS_OFFLOAD */\n\t}\n#endif /* CONFIG_P2P_PS */\n\n\tif (pwrpriv->bLeisurePs) {\n\t\t/* Idle for a while if we connect to AP a while ago. */\n\t\tif (pwrpriv->LpsIdleCount >= 2) { /* 4 Sec */\n\t\t\tif (pwrpriv->pwr_mode == PS_MODE_ACTIVE) {\n\n#ifdef CONFIG_WMMPS_STA\n\t\t\t\tif (rtw_is_wmmps_mode(padapter))\n\t\t\t\t\tmsg = \"WMMPS_IDLE\";\n#endif /* CONFIG_WMMPS_STA */\n\t\t\t\t\n\t\t\t\tsprintf(buf, \"WIFI-%s\", msg);\n\t\t\t\tpwrpriv->bpower_saving = _TRUE;\n\t\t\t\t\n#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS\n\t\t\t\tpwrpriv->pwr_saving_start_time = rtw_get_current_time();\n#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */\n\n\t\t\t\trtw_set_ps_mode(padapter, pwrpriv->power_mgnt, padapter->registrypriv.smart_ps, 0, buf);\n\t\t\t}\n\t\t} else\n\t\t\tpwrpriv->LpsIdleCount++;\n\t}\n\n\t/*\tRTW_INFO(\"-LeisurePSEnter\\n\"); */\n\n}\n\n/*\n *\tDescription:\n *\t\tLeave the leisure power save mode.\n *   */\nvoid LPS_Leave(PADAPTER padapter, const char *msg)\n{\n#define LPS_LEAVE_TIMEOUT_MS 100\n\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct pwrctrl_priv\t*pwrpriv = dvobj_to_pwrctl(dvobj);\n\tchar buf[32] = {0};\n#ifdef DBG_CHECK_FW_PS_STATE\n\tstruct debug_priv *pdbgpriv = &dvobj->drv_dbg;\n#endif\n\n\n\t/*\tRTW_INFO(\"+LeisurePSLeave\\n\"); */\n\n#ifdef CONFIG_BT_COEXIST\n\tif (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)\n\t\treturn;\n#endif\n\n\tif (pwrpriv->bLeisurePs) {\n\t\tif (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {\n\n#ifdef CONFIG_WMMPS_STA\n\t\t\tif (rtw_is_wmmps_mode(padapter))\n\t\t\t\tmsg = \"WMMPS_BUSY\";\n#endif /* CONFIG_WMMPS_STA */\n\t\t\t\n\t\t\tsprintf(buf, \"WIFI-%s\", msg);\n\t\t\trtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, buf);\n\n#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS\t\n\t\t\tpwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);\n#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */\n\t\t}\n\t}\n\n\tpwrpriv->bpower_saving = _FALSE;\n#ifdef DBG_CHECK_FW_PS_STATE\n\tif (rtw_fw_ps_state(padapter) == _FAIL) {\n\t\tRTW_INFO(\"leave lps, fw in 32k\\n\");\n\t\tpdbgpriv->dbg_leave_lps_fail_cnt++;\n\t}\n#endif /* DBG_CHECK_FW_PS_STATE\n * \tRTW_INFO(\"-LeisurePSLeave\\n\"); */\n\n}\n\n#ifdef CONFIG_WOWLAN\nvoid rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);\n\n\tif (wow_en) {\n\t\tpwrpriv->lps_level_bk = pwrpriv->lps_level;\n\t\tpwrpriv->lps_level = pwrpriv->wowlan_lps_level;\n\t\t#ifdef CONFIG_LPS_1T1R\n\t\tpwrpriv->lps_1t1r_bk = pwrpriv->lps_1t1r;\n\t\tpwrpriv->lps_1t1r = pwrpriv->wowlan_lps_1t1r;\n\t\t#endif\n\t} else {\n\t\tpwrpriv->lps_level = pwrpriv->lps_level_bk;\n\t\t#ifdef CONFIG_LPS_1T1R\n\t\tpwrpriv->lps_1t1r = pwrpriv->lps_1t1r_bk;\n\t\t#endif\n\t}\n}\n#endif /* CONFIG_WOWLAN */\n#endif /* CONFIG_LPS */\n\nvoid LeaveAllPowerSaveModeDirect(PADAPTER Adapter)\n{\n\tPADAPTER pri_padapter = GET_PRIMARY_ADAPTER(Adapter);\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter);\n#ifdef CONFIG_LPS_LCLK\n#ifndef CONFIG_DETECT_CPWM_BY_POLLING\n\tu8 cpwm_orig;\n#endif /* CONFIG_DETECT_CPWM_BY_POLLING */\n\tu8 rpwm;\n#endif\n\n\tRTW_INFO(\"%s.....\\n\", __FUNCTION__);\n\n\tif (rtw_is_surprise_removed(Adapter)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": bSurpriseRemoved=_TRUE Skip!\\n\", FUNC_ADPT_ARG(Adapter));\n\t\treturn;\n\t}\n\n\tif (rtw_mi_check_status(Adapter, MI_LINKED)) { /*connect*/\n\n\t\tif (pwrpriv->pwr_mode == PS_MODE_ACTIVE) {\n\t\t\tRTW_INFO(\"%s: Driver Already Leave LPS\\n\", __FUNCTION__);\n\t\t\treturn;\n\t\t}\n\n#ifdef CONFIG_LPS_LCLK\n\t\t_enter_pwrlock(&pwrpriv->lock);\n\n#ifndef CONFIG_DETECT_CPWM_BY_POLLING\n\t\tcpwm_orig = 0;\n\t\trtw_hal_get_hwreg(Adapter, HW_VAR_CPWM, &cpwm_orig);\n#endif /* CONFIG_DETECT_CPWM_BY_POLLING */\n\t\trpwm = rtw_set_rpwm(Adapter, PS_STATE_S4);\n\n#ifndef CONFIG_DETECT_CPWM_BY_POLLING\n\t\tif (rpwm != 0xFF && rpwm & PS_ACK)\n\t\t\trtw_cpwm_polling(Adapter, rpwm, cpwm_orig);\n#endif /* CONFIG_DETECT_CPWM_BY_POLLING */\n\n\t\t_exit_pwrlock(&pwrpriv->lock);\n#endif/*CONFIG_LPS_LCLK*/\n\n#ifdef CONFIG_P2P_PS\n\t\tp2p_ps_wk_cmd(pri_padapter, P2P_PS_DISABLE, 0);\n#endif /* CONFIG_P2P_PS */\n\n#ifdef CONFIG_LPS\n\t\trtw_lps_ctrl_wk_cmd(pri_padapter, LPS_CTRL_LEAVE, RTW_CMDF_DIRECTLY);\n#endif\n\t} else {\n\t\tif (pwrpriv->rf_pwrstate == rf_off) {\n#ifdef CONFIG_AUTOSUSPEND\n\t\t\tif (Adapter->registrypriv.usbss_enable) {\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\t\t\t\tusb_disable_autosuspend(adapter_to_dvobj(Adapter)->pusbdev);\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 34))\n\t\t\t\tadapter_to_dvobj(Adapter)->pusbdev->autosuspend_disabled = Adapter->bDisableAutosuspend;/* autosuspend disabled by the user */\n#endif\n\t\t\t} else\n#endif\n\t\t\t{\n#if defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_RTL8188E)\n#ifdef CONFIG_IPS\n\t\t\t\tif (_FALSE == ips_leave(pri_padapter))\n\t\t\t\t\tRTW_INFO(\"======> ips_leave fail.............\\n\");\n#endif\n#endif /* CONFIG_SWLPS_IN_IPS || (CONFIG_PLATFORM_SPRD && CONFIG_RTL8188E) */\n\t\t\t}\n\t\t}\n\t}\n\n}\n\n/*\n * Description: Leave all power save mode: LPS, FwLPS, IPS if needed.\n * Move code to function by tynli. 2010.03.26.\n *   */\nvoid LeaveAllPowerSaveMode(PADAPTER Adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);\n\tu8\tenqueue = 0;\n\tint i;\n\n\t#ifndef CONFIG_NEW_NETDEV_HDL\n\tif (_FALSE == Adapter->bup) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": bup=%d Skip!\\n\",\n\t\t\t FUNC_ADPT_ARG(Adapter), Adapter->bup);\n\t\treturn;\n\t}\n\t#endif\n\n/*\tRTW_INFO(FUNC_ADPT_FMT \"\\n\", FUNC_ADPT_ARG(Adapter));*/\n\n\tif (rtw_is_surprise_removed(Adapter)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": bSurpriseRemoved=_TRUE Skip!\\n\", FUNC_ADPT_ARG(Adapter));\n\t\treturn;\n\t}\n\n\tif (rtw_mi_get_assoc_if_num(Adapter)) {\n\t\t/* connect */\n#ifdef CONFIG_LPS_LCLK\n\t\tenqueue = 1;\n#endif\n\n#ifdef CONFIG_P2P_PS\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\t_adapter *iface = dvobj->padapters[i];\n\t\t\tstruct wifidirect_info *pwdinfo = &(iface->wdinfo);\n\n\t\t\tif (pwdinfo->p2p_ps_mode > P2P_PS_NONE)\n\t\t\t\tp2p_ps_wk_cmd(iface, P2P_PS_DISABLE, enqueue);\n\t\t}\n#endif /* CONFIG_P2P_PS */\n\n#ifdef CONFIG_LPS\n\t\trtw_lps_ctrl_wk_cmd(Adapter, LPS_CTRL_LEAVE, enqueue ? 0 : RTW_CMDF_DIRECTLY);\n#endif\n\n#ifdef CONFIG_LPS_LCLK\n\t\tLPS_Leave_check(Adapter);\n#endif\n\t} else {\n\t\tif (adapter_to_pwrctl(Adapter)->rf_pwrstate == rf_off) {\n#ifdef CONFIG_AUTOSUSPEND\n\t\t\tif (Adapter->registrypriv.usbss_enable) {\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\t\t\t\tusb_disable_autosuspend(adapter_to_dvobj(Adapter)->pusbdev);\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 34))\n\t\t\t\tadapter_to_dvobj(Adapter)->pusbdev->autosuspend_disabled = Adapter->bDisableAutosuspend;/* autosuspend disabled by the user */\n#endif\n\t\t\t} else\n#endif\n\t\t\t{\n#if defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) || (defined(CONFIG_PLATFORM_SPRD) && defined(CONFIG_RTL8188E))\n#ifdef CONFIG_IPS\n\t\t\t\tif (_FALSE == ips_leave(Adapter))\n\t\t\t\t\tRTW_INFO(\"======> ips_leave fail.............\\n\");\n#endif\n#endif /* CONFIG_SWLPS_IN_IPS || (CONFIG_PLATFORM_SPRD && CONFIG_RTL8188E) */\n\t\t\t}\n\t\t}\n\t}\n\n}\n\n#ifdef CONFIG_LPS_LCLK\nvoid LPS_Leave_check(\n\tPADAPTER padapter)\n{\n\tstruct pwrctrl_priv *pwrpriv;\n\tsystime\tstart_time;\n\tu8\tbReady;\n\n\n\tpwrpriv = adapter_to_pwrctl(padapter);\n\n\tbReady = _FALSE;\n\tstart_time = rtw_get_current_time();\n\n\trtw_yield_os();\n\n\twhile (1) {\n\t\t_enter_pwrlock(&pwrpriv->lock);\n\n\t\tif (rtw_is_surprise_removed(padapter)\n\t\t    || (!rtw_is_hw_init_completed(padapter))\n#ifdef CONFIG_USB_HCI\n\t\t    || rtw_is_drv_stopped(padapter)\n#endif\n\t\t    || (pwrpriv->pwr_mode == PS_MODE_ACTIVE)\n\t\t   )\n\t\t\tbReady = _TRUE;\n\n\t\t_exit_pwrlock(&pwrpriv->lock);\n\n\t\tif (_TRUE == bReady)\n\t\t\tbreak;\n\n\t\tif (rtw_get_passing_time_ms(start_time) > 100) {\n\t\t\tRTW_ERR(\"Wait for cpwm event  than 100 ms!!!\\n\");\n\t\t\tbreak;\n\t\t}\n\t\trtw_msleep_os(1);\n\t}\n\n}\n\n/*\n * Caller:ISR handler...\n *\n * This will be called when CPWM interrupt is up.\n *\n * using to update cpwn of drv; and drv willl make a decision to up or down pwr level\n */\nvoid cpwm_int_hdl(\n\tPADAPTER padapter,\n\tstruct reportpwrstate_parm *preportpwrstate)\n{\n\tstruct pwrctrl_priv *pwrpriv;\n\n\tif (!padapter)\n\t\tgoto exit;\n\n\tif (RTW_CANNOT_RUN(padapter))\n\t\tgoto exit;\n\n\tpwrpriv = adapter_to_pwrctl(padapter);\n#if 0\n\tif (pwrpriv->cpwm_tog == (preportpwrstate->state & PS_TOGGLE)) {\n\t\tgoto exit;\n\t}\n#endif\n\n\t_enter_pwrlock(&pwrpriv->lock);\n\n#ifdef CONFIG_LPS_RPWM_TIMER\n\tif (pwrpriv->rpwm < PS_STATE_S2) {\n\t\tRTW_INFO(\"%s: Redundant CPWM Int. RPWM=0x%02X CPWM=0x%02x\\n\", __func__, pwrpriv->rpwm, pwrpriv->cpwm);\n\t\t_exit_pwrlock(&pwrpriv->lock);\n\t\tgoto exit;\n\t}\n#endif /* CONFIG_LPS_RPWM_TIMER */\n\n\tpwrpriv->cpwm = PS_STATE(preportpwrstate->state);\n\tpwrpriv->cpwm_tog = preportpwrstate->state & PS_TOGGLE;\n\n\tif (pwrpriv->cpwm >= PS_STATE_S2) {\n\t\tif (pwrpriv->alives & CMD_ALIVE)\n\t\t\t_rtw_up_sema(&padapter->cmdpriv.cmd_queue_sema);\n\n\t\tif (pwrpriv->alives & XMIT_ALIVE)\n\t\t\t_rtw_up_sema(&padapter->xmitpriv.xmit_sema);\n\t}\n\n\t_exit_pwrlock(&pwrpriv->lock);\n\nexit:\n\treturn;\n}\n\nstatic void cpwm_event_callback(struct work_struct *work)\n{\n\tstruct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, cpwm_event);\n\tstruct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);\n\t_adapter *adapter = dvobj_get_primary_adapter(dvobj);\n\tstruct reportpwrstate_parm report;\n\n\t/* RTW_INFO(\"%s\\n\",__FUNCTION__); */\n\n\treport.state = PS_STATE_S2;\n\tcpwm_int_hdl(adapter, &report);\n}\n\nstatic void dma_event_callback(struct work_struct *work)\n{\n\tstruct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, dma_event);\n\tstruct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);\n\t_adapter *adapter = dvobj_get_primary_adapter(dvobj);\n\n\trtw_unregister_tx_alive(adapter);\n}\n\n#ifdef CONFIG_LPS_RPWM_TIMER\n\n#define DBG_CPWM_CHK_FAIL\n#if defined(DBG_CPWM_CHK_FAIL) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)) \n#define CPU_EXCEPTION_CODE 0xFAFAFAFA\nstatic void rtw_cpwm_chk_fail_debug(_adapter *padapter)\n{\n\tu32 cpu_state;\n\n\tcpu_state = rtw_read32(padapter, 0x10FC);\n\n\tRTW_INFO(\"[PS-DBG] Reg_10FC =0x%08x\\n\", cpu_state);\n\tRTW_INFO(\"[PS-DBG] Reg_10F8 =0x%08x\\n\", rtw_read32(padapter, 0x10F8));\n\tRTW_INFO(\"[PS-DBG] Reg_11F8 =0x%08x\\n\", rtw_read32(padapter, 0x11F8));\n\tRTW_INFO(\"[PS-DBG] Reg_4A4 =0x%08x\\n\", rtw_read32(padapter, 0x4A4));\n\tRTW_INFO(\"[PS-DBG] Reg_4A8 =0x%08x\\n\", rtw_read32(padapter, 0x4A8));\n\n\tif (cpu_state == CPU_EXCEPTION_CODE) {\n\t\tRTW_INFO(\"[PS-DBG] Reg_48C =0x%08x\\n\", rtw_read32(padapter, 0x48C));\n\t\tRTW_INFO(\"[PS-DBG] Reg_490 =0x%08x\\n\", rtw_read32(padapter, 0x490));\n\t\tRTW_INFO(\"[PS-DBG] Reg_494 =0x%08x\\n\", rtw_read32(padapter, 0x494));\n\t\tRTW_INFO(\"[PS-DBG] Reg_498 =0x%08x\\n\", rtw_read32(padapter, 0x498));\n\t\tRTW_INFO(\"[PS-DBG] Reg_49C =0x%08x\\n\", rtw_read32(padapter, 0x49C));\n\t\tRTW_INFO(\"[PS-DBG] Reg_4A0 =0x%08x\\n\", rtw_read32(padapter, 0x4A0));\n\t\tRTW_INFO(\"[PS-DBG] Reg_1BC =0x%08x\\n\", rtw_read32(padapter, 0x1BC));\n\n\t\tRTW_INFO(\"[PS-DBG] Reg_008 =0x%08x\\n\", rtw_read32(padapter, 0x08));\n\t\tRTW_INFO(\"[PS-DBG] Reg_2F0 =0x%08x\\n\", rtw_read32(padapter, 0x2F0));\n\t\tRTW_INFO(\"[PS-DBG] Reg_2F4 =0x%08x\\n\", rtw_read32(padapter, 0x2F4));\n\t\tRTW_INFO(\"[PS-DBG] Reg_2F8 =0x%08x\\n\", rtw_read32(padapter, 0x2F8));\n\t\tRTW_INFO(\"[PS-DBG] Reg_2FC =0x%08x\\n\", rtw_read32(padapter, 0x2FC));\n\n\t\trtw_dump_fifo(RTW_DBGDUMP, padapter, 5, 0, 3072);\n\t}\n}\n#endif\nstatic void rpwmtimeout_workitem_callback(struct work_struct *work)\n{\n\tPADAPTER padapter;\n\tstruct dvobj_priv *dvobj;\n\tstruct pwrctrl_priv *pwrpriv;\n\n\n\tpwrpriv = container_of(work, struct pwrctrl_priv, rpwmtimeoutwi);\n\tdvobj = pwrctl_to_dvobj(pwrpriv);\n\tpadapter = dvobj_get_primary_adapter(dvobj);\n\n\tif (!padapter)\n\t\treturn;\n\n\tif (RTW_CANNOT_RUN(padapter))\n\t\treturn;\n\n\t_enter_pwrlock(&pwrpriv->lock);\n\tif ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) {\n\t\tRTW_INFO(\"%s: rpwm=0x%02X cpwm=0x%02X CPWM done!\\n\", __func__, pwrpriv->rpwm, pwrpriv->cpwm);\n\t\tgoto exit;\n\t}\n\n\tif (pwrpriv->rpwm_retry++ < LPS_RPWM_RETRY_CNT) {\n\t\tu8 rpwm = (pwrpriv->rpwm | pwrpriv->tog | PS_ACK);\n\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));\n\n\t\tpwrpriv->tog += 0x80;\n\t\t_set_timer(&pwrpriv->pwr_rpwm_timer, LPS_CPWM_TIMEOUT_MS);\n\t\tgoto exit;\n\t}\n\n\tpwrpriv->rpwm_retry = 0;\n\t_exit_pwrlock(&pwrpriv->lock);\n\n#if defined(DBG_CPWM_CHK_FAIL) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C))\n\tRTW_INFO(\"+%s: rpwm=0x%02X cpwm=0x%02X\\n\", __func__, pwrpriv->rpwm, pwrpriv->cpwm);\n\trtw_cpwm_chk_fail_debug(padapter);\n#endif\n\n\tif (rtw_read8(padapter, 0x100) != 0xEA) {\n#if 1\n\t\tstruct reportpwrstate_parm report;\n\n\t\treport.state = PS_STATE_S2;\n\t\tRTW_INFO(\"\\n%s: FW already leave 32K!\\n\\n\", __func__);\n\t\tcpwm_int_hdl(padapter, &report);\n#else\n\t\tRTW_INFO(\"\\n%s: FW already leave 32K!\\n\\n\", __func__);\n\t\tcpwm_event_callback(&pwrpriv->cpwm_event);\n#endif\n\t\treturn;\n\t}\n\n\t_enter_pwrlock(&pwrpriv->lock);\n\n\tif ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) {\n\t\tRTW_INFO(\"%s: cpwm=%d, nothing to do!\\n\", __func__, pwrpriv->cpwm);\n\t\tgoto exit;\n\t}\n\tpwrpriv->brpwmtimeout = _TRUE;\n\trtw_set_rpwm(padapter, pwrpriv->rpwm);\n\tpwrpriv->brpwmtimeout = _FALSE;\n\nexit:\n\t_exit_pwrlock(&pwrpriv->lock);\n}\n\n/*\n * This function is a timer handler, can't do any IO in it.\n */\nstatic void pwr_rpwm_timeout_handler(void *FunctionContext)\n{\n\tPADAPTER padapter;\n\tstruct pwrctrl_priv *pwrpriv;\n\n\n\tpadapter = (PADAPTER)FunctionContext;\n\tpwrpriv = adapter_to_pwrctl(padapter);\n\tif (!padapter)\n\t\treturn;\n\n\tif (RTW_CANNOT_RUN(padapter))\n\t\treturn;\n\n\tRTW_INFO(\"+%s: rpwm=0x%02X cpwm=0x%02X\\n\", __func__, pwrpriv->rpwm, pwrpriv->cpwm);\n\n\tif ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) {\n\t\tRTW_INFO(\"+%s: cpwm=%d, nothing to do!\\n\", __func__, pwrpriv->cpwm);\n\t\treturn;\n\t}\n\n\t_set_workitem(&pwrpriv->rpwmtimeoutwi);\n}\n#endif /* CONFIG_LPS_RPWM_TIMER */\n\n__inline static void register_task_alive(struct pwrctrl_priv *pwrctrl, u32 tag)\n{\n\tpwrctrl->alives |= tag;\n}\n\n__inline static void unregister_task_alive(struct pwrctrl_priv *pwrctrl, u32 tag)\n{\n\tpwrctrl->alives &= ~tag;\n}\n\n\n/*\n * Description:\n *\tCheck if the fw_pwrstate is okay for I/O.\n *\tIf not (cpwm is less than S2), then the sub-routine\n *\twill raise the cpwm to be greater than or equal to S2.\n *\n *\tCalling Context: Passive\n *\n *\tConstraint:\n *\t\t1. this function will request pwrctrl->lock\n *\n * Return Value:\n *\t_SUCCESS\thardware is ready for I/O\n *\t_FAIL\t\tcan't I/O right now\n */\ns32 rtw_register_task_alive(PADAPTER padapter, u32 task)\n{\n\ts32 res;\n\tstruct pwrctrl_priv *pwrctrl;\n\tu8 pslv;\n\n\n\tres = _SUCCESS;\n\tpwrctrl = adapter_to_pwrctl(padapter);\n\tpslv = PS_STATE_S2;\n\n\t_enter_pwrlock(&pwrctrl->lock);\n\n\tregister_task_alive(pwrctrl, task);\n\n\tif (pwrctrl->bFwCurrentInPSMode == _TRUE) {\n\n\t\tif (pwrctrl->cpwm < pslv) {\n\t\t\tif (pwrctrl->cpwm < PS_STATE_S2)\n\t\t\t\tres = _FAIL;\n\t\t\tif (pwrctrl->rpwm < pslv)\n\t\t\t\trtw_set_rpwm(padapter, pslv);\n\t\t}\n\t}\n\n\t_exit_pwrlock(&pwrctrl->lock);\n\n#ifdef CONFIG_DETECT_CPWM_BY_POLLING\n\tif (_FAIL == res) {\n\t\tif (pwrctrl->cpwm >= PS_STATE_S2)\n\t\t\tres = _SUCCESS;\n\t}\n#endif /* CONFIG_DETECT_CPWM_BY_POLLING */\n\n\n\treturn res;\n}\n\n/*\n * Description:\n *\tIf task is done, call this func. to power down firmware again.\n *\n *\tConstraint:\n *\t\t1. this function will request pwrctrl->lock\n *\n * Return Value:\n *\tnone\n */\nvoid rtw_unregister_task_alive(PADAPTER padapter, u32 task)\n{\n\tstruct pwrctrl_priv *pwrctrl;\n\tu8 pslv;\n\n\n\tpwrctrl = adapter_to_pwrctl(padapter);\n\tpslv = PS_STATE_S0;\n\n#ifdef CONFIG_BT_COEXIST\n\tif ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE)\n\t    && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) {\n\t\tu8 val8;\n\n\t\tval8 = rtw_btcoex_LpsVal(padapter);\n\t\tif (val8 & BIT(4))\n\t\t\tpslv = PS_STATE_S2;\n\n\t}\n#endif /* CONFIG_BT_COEXIST */\n\n\t_enter_pwrlock(&pwrctrl->lock);\n\n\tunregister_task_alive(pwrctrl, task);\n\n\tif ((pwrctrl->pwr_mode != PS_MODE_ACTIVE)\n\t    && (pwrctrl->bFwCurrentInPSMode == _TRUE)) {\n\n\t\tif (pwrctrl->cpwm > pslv) {\n\t\t\tif ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0))\n\t\t\t\trtw_set_rpwm(padapter, pslv);\n\t\t}\n\t}\n\n\t_exit_pwrlock(&pwrctrl->lock);\n\n}\n\n/*\n * Caller: rtw_xmit_thread\n *\n * Check if the fw_pwrstate is okay for xmit.\n * If not (cpwm is less than S3), then the sub-routine\n * will raise the cpwm to be greater than or equal to S3.\n *\n * Calling Context: Passive\n *\n * Return Value:\n *\t _SUCCESS\trtw_xmit_thread can write fifo/txcmd afterwards.\n *\t _FAIL\t\trtw_xmit_thread can not do anything.\n */\ns32 rtw_register_tx_alive(PADAPTER padapter)\n{\n\ts32 res;\n\tstruct pwrctrl_priv *pwrctrl;\n\tu8 pslv;\n\n\n\tres = _SUCCESS;\n\tpwrctrl = adapter_to_pwrctl(padapter);\n\tpslv = PS_STATE_S2;\n\n\t_enter_pwrlock(&pwrctrl->lock);\n\n\tregister_task_alive(pwrctrl, XMIT_ALIVE);\n\n\tif (pwrctrl->bFwCurrentInPSMode == _TRUE) {\n\n\t\tif (pwrctrl->cpwm < pslv) {\n\t\t\tif (pwrctrl->cpwm < PS_STATE_S2)\n\t\t\t\tres = _FAIL;\n\t\t\tif (pwrctrl->rpwm < pslv)\n\t\t\t\trtw_set_rpwm(padapter, pslv);\n\t\t}\n\t}\n\n\t_exit_pwrlock(&pwrctrl->lock);\n\n#ifdef CONFIG_DETECT_CPWM_BY_POLLING\n\tif (_FAIL == res) {\n\t\tif (pwrctrl->cpwm >= PS_STATE_S2)\n\t\t\tres = _SUCCESS;\n\t}\n#endif /* CONFIG_DETECT_CPWM_BY_POLLING */\n\n\n\treturn res;\n}\n\n/*\n * Caller: rtw_cmd_thread\n *\n * Check if the fw_pwrstate is okay for issuing cmd.\n * If not (cpwm should be is less than S2), then the sub-routine\n * will raise the cpwm to be greater than or equal to S2.\n *\n * Calling Context: Passive\n *\n * Return Value:\n *\t_SUCCESS\trtw_cmd_thread can issue cmds to firmware afterwards.\n *\t_FAIL\t\trtw_cmd_thread can not do anything.\n */\ns32 rtw_register_cmd_alive(PADAPTER padapter)\n{\n\ts32 res;\n\tstruct pwrctrl_priv *pwrctrl;\n\tu8 pslv;\n\n\n\tres = _SUCCESS;\n\tpwrctrl = adapter_to_pwrctl(padapter);\n\tpslv = PS_STATE_S2;\n\n\t_enter_pwrlock(&pwrctrl->lock);\n\n\tregister_task_alive(pwrctrl, CMD_ALIVE);\n\n\tif (pwrctrl->bFwCurrentInPSMode == _TRUE) {\n\n\t\tif (pwrctrl->cpwm < pslv) {\n\t\t\tif (pwrctrl->cpwm < PS_STATE_S2)\n\t\t\t\tres = _FAIL;\n\t\t\tif (pwrctrl->rpwm < pslv)\n\t\t\t\trtw_set_rpwm(padapter, pslv);\n\t\t}\n\t}\n\n\t_exit_pwrlock(&pwrctrl->lock);\n\n#ifdef CONFIG_DETECT_CPWM_BY_POLLING\n\tif (_FAIL == res) {\n\t\tif (pwrctrl->cpwm >= PS_STATE_S2)\n\t\t\tres = _SUCCESS;\n\t}\n#endif /* CONFIG_DETECT_CPWM_BY_POLLING */\n\n\n\treturn res;\n}\n\n/*\n * Caller: rx_isr\n *\n * Calling Context: Dispatch/ISR\n *\n * Return Value:\n *\t_SUCCESS\n *\t_FAIL\n */\ns32 rtw_register_rx_alive(PADAPTER padapter)\n{\n\tstruct pwrctrl_priv *pwrctrl;\n\n\n\tpwrctrl = adapter_to_pwrctl(padapter);\n\n\t_enter_pwrlock(&pwrctrl->lock);\n\n\tregister_task_alive(pwrctrl, RECV_ALIVE);\n\n\t_exit_pwrlock(&pwrctrl->lock);\n\n\n\treturn _SUCCESS;\n}\n\n/*\n * Caller: evt_isr or evt_thread\n *\n * Calling Context: Dispatch/ISR or Passive\n *\n * Return Value:\n *\t_SUCCESS\n *\t_FAIL\n */\ns32 rtw_register_evt_alive(PADAPTER padapter)\n{\n\tstruct pwrctrl_priv *pwrctrl;\n\n\n\tpwrctrl = adapter_to_pwrctl(padapter);\n\n\t_enter_pwrlock(&pwrctrl->lock);\n\n\tregister_task_alive(pwrctrl, EVT_ALIVE);\n\n\t_exit_pwrlock(&pwrctrl->lock);\n\n\n\treturn _SUCCESS;\n}\n\n/*\n * Caller: ISR\n *\n * If ISR's txdone,\n * No more pkts for TX,\n * Then driver shall call this fun. to power down firmware again.\n */\nvoid rtw_unregister_tx_alive(PADAPTER padapter)\n{\n\tstruct pwrctrl_priv *pwrctrl;\n\t_adapter *iface;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tu8 pslv, i;\n\n\n\tpwrctrl = adapter_to_pwrctl(padapter);\n\tpslv = PS_STATE_S0;\n\n#ifdef CONFIG_BT_COEXIST\n\tif ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE)\n\t    && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) {\n\t\tu8 val8;\n\n\t\tval8 = rtw_btcoex_LpsVal(padapter);\n\t\tif (val8 & BIT(4))\n\t\t\tpslv = PS_STATE_S2;\n\n\t}\n#endif /* CONFIG_BT_COEXIST */\n\n#ifdef CONFIG_P2P_PS\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif ((iface) && rtw_is_adapter_up(iface)) {\n\t\t\tif (iface->wdinfo.p2p_ps_mode > P2P_PS_NONE) {\n\t\t\t\tpslv = PS_STATE_S2;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n#endif\n\t_enter_pwrlock(&pwrctrl->lock);\n\n\tunregister_task_alive(pwrctrl, XMIT_ALIVE);\n\n\tif ((pwrctrl->pwr_mode != PS_MODE_ACTIVE)\n\t    && (pwrctrl->bFwCurrentInPSMode == _TRUE)) {\n\n\t\tif (pwrctrl->cpwm > pslv) {\n\t\t\tif ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0))\n\t\t\t\trtw_set_rpwm(padapter, pslv);\n\t\t}\n\t}\n\n\t_exit_pwrlock(&pwrctrl->lock);\n\n}\n\n/*\n * Caller: ISR\n *\n * If all commands have been done,\n * and no more command to do,\n * then driver shall call this fun. to power down firmware again.\n */\nvoid rtw_unregister_cmd_alive(PADAPTER padapter)\n{\n\t_adapter *iface;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct pwrctrl_priv *pwrctrl;\n\tu8 pslv, i;\n\n\n\tpwrctrl = adapter_to_pwrctl(padapter);\n\tpslv = PS_STATE_S0;\n\n#ifdef CONFIG_BT_COEXIST\n\tif ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE)\n\t    && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) {\n\t\tu8 val8;\n\n\t\tval8 = rtw_btcoex_LpsVal(padapter);\n\t\tif (val8 & BIT(4))\n\t\t\tpslv = PS_STATE_S2;\n\n\t}\n#endif /* CONFIG_BT_COEXIST */\n\n#ifdef CONFIG_P2P_PS\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif ((iface) && rtw_is_adapter_up(iface)) {\n\t\t\tif (iface->wdinfo.p2p_ps_mode > P2P_PS_NONE) {\n\t\t\t\tpslv = PS_STATE_S2;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n#endif\n\n\t_enter_pwrlock(&pwrctrl->lock);\n\n\tunregister_task_alive(pwrctrl, CMD_ALIVE);\n\n\tif ((pwrctrl->pwr_mode != PS_MODE_ACTIVE)\n\t    && (pwrctrl->bFwCurrentInPSMode == _TRUE)) {\n\n\t\tif (pwrctrl->cpwm > pslv) {\n\t\t\tif ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0))\n\t\t\t\trtw_set_rpwm(padapter, pslv);\n\t\t}\n\t}\n\n\t_exit_pwrlock(&pwrctrl->lock);\n\n}\n\n/*\n * Caller: ISR\n */\nvoid rtw_unregister_rx_alive(PADAPTER padapter)\n{\n\tstruct pwrctrl_priv *pwrctrl;\n\n\n\tpwrctrl = adapter_to_pwrctl(padapter);\n\n\t_enter_pwrlock(&pwrctrl->lock);\n\n\tunregister_task_alive(pwrctrl, RECV_ALIVE);\n\n\n\t_exit_pwrlock(&pwrctrl->lock);\n\n}\n\nvoid rtw_unregister_evt_alive(PADAPTER padapter)\n{\n\tstruct pwrctrl_priv *pwrctrl;\n\n\n\tpwrctrl = adapter_to_pwrctl(padapter);\n\n\tunregister_task_alive(pwrctrl, EVT_ALIVE);\n\n\n\t_exit_pwrlock(&pwrctrl->lock);\n\n}\n#endif\t/* CONFIG_LPS_LCLK */\n\n#ifdef CONFIG_RESUME_IN_WORKQUEUE\n\tstatic void resume_workitem_callback(struct work_struct *work);\n#endif /* CONFIG_RESUME_IN_WORKQUEUE */\n\nvoid rtw_init_pwrctrl_priv(PADAPTER padapter)\n{\n#ifdef CONFIG_LPS_1T1R\n#define LPS_1T1R_FMT \", LPS_1T1R=%d\"\n#define LPS_1T1R_ARG , pwrctrlpriv->lps_1t1r\n#else\n#define LPS_1T1R_FMT \"\"\n#define LPS_1T1R_ARG\n#endif\n\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n#ifdef CONFIG_WOWLAN\n\tstruct registry_priv  *registry_par = &padapter->registrypriv;\n#endif\n#ifdef CONFIG_GPIO_WAKEUP\n\tu8 val8 = 0;\n#endif\n\n#if defined(CONFIG_CONCURRENT_MODE)\n\tif (!is_primary_adapter(padapter))\n\t\treturn;\n#endif\n\n\t_init_pwrlock(&pwrctrlpriv->lock);\n\t_init_pwrlock(&pwrctrlpriv->check_32k_lock);\n\tpwrctrlpriv->rf_pwrstate = rf_on;\n\tpwrctrlpriv->ips_enter_cnts = 0;\n\tpwrctrlpriv->ips_leave_cnts = 0;\n\tpwrctrlpriv->lps_enter_cnts = 0;\n\tpwrctrlpriv->lps_leave_cnts = 0;\n\tpwrctrlpriv->bips_processing = _FALSE;\n#ifdef CONFIG_LPS_CHK_BY_TP\n\tpwrctrlpriv->lps_chk_by_tp = padapter->registrypriv.lps_chk_by_tp;\n\tpwrctrlpriv->lps_tx_tp_th = LPS_TX_TP_TH;\n\tpwrctrlpriv->lps_rx_tp_th = LPS_RX_TP_TH;\n\tpwrctrlpriv->lps_bi_tp_th = LPS_BI_TP_TH;\n\tpwrctrlpriv->lps_chk_cnt = pwrctrlpriv->lps_chk_cnt_th = LPS_TP_CHK_CNT;\n\tpwrctrlpriv->lps_tx_pkts = LPS_CHK_PKTS_TX;\n\tpwrctrlpriv->lps_rx_pkts = LPS_CHK_PKTS_RX;\n#endif\n\n\tpwrctrlpriv->ips_mode = padapter->registrypriv.ips_mode;\n\tpwrctrlpriv->ips_mode_req = padapter->registrypriv.ips_mode;\n\tpwrctrlpriv->ips_deny_time = rtw_get_current_time();\n\tpwrctrlpriv->lps_level = padapter->registrypriv.lps_level;\n#ifdef CONFIG_LPS_1T1R\n\tpwrctrlpriv->lps_1t1r = padapter->registrypriv.lps_1t1r;\n#endif\n\n\tpwrctrlpriv->pwr_state_check_interval = RTW_PWR_STATE_CHK_INTERVAL;\n\tpwrctrlpriv->pwr_state_check_cnts = 0;\n\t#ifdef CONFIG_AUTOSUSPEND\n\tpwrctrlpriv->bInternalAutoSuspend = _FALSE;\n\t#endif\n\tpwrctrlpriv->bInSuspend = _FALSE;\n\tpwrctrlpriv->bkeepfwalive = _FALSE;\n\n#ifdef CONFIG_AUTOSUSPEND\n#ifdef SUPPORT_HW_RFOFF_DETECTED\n\tpwrctrlpriv->pwr_state_check_interval = (pwrctrlpriv->bHWPwrPindetect) ? 1000 : 2000;\n#endif\n#endif\n\n\tpwrctrlpriv->LpsIdleCount = 0;\n\n\t/* pwrctrlpriv->FWCtrlPSMode =padapter->registrypriv.power_mgnt; */ /* PS_MODE_MIN; */\n\tif (padapter->registrypriv.mp_mode == 1)\n\t\tpwrctrlpriv->power_mgnt = PS_MODE_ACTIVE ;\n\telse\n\t\tpwrctrlpriv->power_mgnt = padapter->registrypriv.power_mgnt; /* PS_MODE_MIN; */\n\tpwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt) ? _TRUE : _FALSE;\n\n\tpwrctrlpriv->bFwCurrentInPSMode = _FALSE;\n\tpwrctrlpriv->lps_deny_time = rtw_get_current_time();\n\n\tpwrctrlpriv->rpwm = 0;\n\tpwrctrlpriv->cpwm = PS_STATE_S4;\n\n\tpwrctrlpriv->pwr_mode = PS_MODE_ACTIVE;\n\tpwrctrlpriv->smart_ps = padapter->registrypriv.smart_ps;\n\tpwrctrlpriv->bcn_ant_mode = 0;\n\tpwrctrlpriv->dtim = 0;\n\n\tpwrctrlpriv->tog = 0x80;\n\tpwrctrlpriv->rpwm_retry = 0;\n\n\tRTW_INFO(\"%s: IPS_mode=%d, LPS_mode=%d, LPS_level=%d\"LPS_1T1R_FMT\"\\n\", \n\t\t__func__, pwrctrlpriv->ips_mode, pwrctrlpriv->power_mgnt, pwrctrlpriv->lps_level\n\t\tLPS_1T1R_ARG\n\t);\n\n#ifdef CONFIG_LPS_LCLK\n\trtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&pwrctrlpriv->rpwm));\n\n\t_init_workitem(&pwrctrlpriv->cpwm_event, cpwm_event_callback, NULL);\n\n\t_init_workitem(&pwrctrlpriv->dma_event, dma_event_callback, NULL);\n\n#ifdef CONFIG_LPS_RPWM_TIMER\n\tpwrctrlpriv->brpwmtimeout = _FALSE;\n\t_init_workitem(&pwrctrlpriv->rpwmtimeoutwi, rpwmtimeout_workitem_callback, NULL);\n\trtw_init_timer(&pwrctrlpriv->pwr_rpwm_timer, padapter, pwr_rpwm_timeout_handler, padapter);\n#endif /* CONFIG_LPS_RPWM_TIMER */\n#endif /* CONFIG_LPS_LCLK */\n\n#ifdef CONFIG_LPS_PG\n\tpwrctrlpriv->lpspg_info.name = \"LPSPG_INFO\";\n\t#ifdef CONFIG_RTL8822C\n\tpwrctrlpriv->lpspg_dpk_info.name = \"LPSPG_DPK_INFO\";\n\tpwrctrlpriv->lpspg_iqk_info.name = \"LPSPG_IQK_INFO\";\n\t#endif\n#endif\n\n\trtw_init_timer(&pwrctrlpriv->pwr_state_check_timer, padapter, pwr_state_check_handler, padapter);\n\n\tpwrctrlpriv->wowlan_mode = _FALSE;\n\tpwrctrlpriv->wowlan_ap_mode = _FALSE;\n\tpwrctrlpriv->wowlan_p2p_mode = _FALSE;\n\tpwrctrlpriv->wowlan_in_resume = _FALSE;\n\tpwrctrlpriv->wowlan_last_wake_reason = 0;\n\n#ifdef CONFIG_RESUME_IN_WORKQUEUE\n\t_init_workitem(&pwrctrlpriv->resume_work, resume_workitem_callback, NULL);\n\tpwrctrlpriv->rtw_workqueue = create_singlethread_workqueue(\"rtw_workqueue\");\n#endif /* CONFIG_RESUME_IN_WORKQUEUE */\n\n#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)\n\tpwrctrlpriv->early_suspend.suspend = NULL;\n\trtw_register_early_suspend(pwrctrlpriv);\n#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */\n\n#ifdef CONFIG_GPIO_WAKEUP\n\t/*default low active*/\n\tpwrctrlpriv->is_high_active = HIGH_ACTIVE_DEV2HST;\n\tpwrctrlpriv->hst2dev_high_active = HIGH_ACTIVE_HST2DEV;\n#ifdef CONFIG_RTW_ONE_PIN_GPIO\n\trtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _TRUE);\n\trtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX);\n#else\n\t#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE\n\tif (pwrctrlpriv->is_high_active == 0)\n\t\trtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX);\n\telse\n\t\trtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, 0);\n\t#else\n\tval8 = (pwrctrlpriv->is_high_active == 0) ? 1 : 0;\n\trtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8);\n\tRTW_INFO(\"%s: set GPIO_%d %d as default.\\n\",\n\t\t __func__, WAKEUP_GPIO_IDX, val8);\n\t#endif /*CONFIG_WAKEUP_GPIO_INPUT_MODE*/\n#endif /* CONFIG_RTW_ONE_PIN_GPIO */\n#endif /* CONFIG_GPIO_WAKEUP */\n\n#ifdef CONFIG_WOWLAN\n#ifdef CONFIG_LPS_1T1R\n#define WOW_LPS_1T1R_FMT \", WOW_LPS_1T1R=%d\"\n#define WOW_LPS_1T1R_ARG , pwrctrlpriv->wowlan_lps_1t1r\n#else\n#define WOW_LPS_1T1R_FMT \"\"\n#define WOW_LPS_1T1R_ARG\n#endif\n\n\tpwrctrlpriv->wowlan_power_mgmt = padapter->registrypriv.wow_power_mgnt;\n\tpwrctrlpriv->wowlan_lps_level = padapter->registrypriv.wow_lps_level;\n#ifdef CONFIG_LPS_1T1R\n\tpwrctrlpriv->wowlan_lps_1t1r = padapter->registrypriv.wow_lps_1t1r;\n#endif\n\n\tRTW_INFO(\"%s: WOW_LPS_mode=%d, WOW_LPS_level=%d\"WOW_LPS_1T1R_FMT\"\\n\",\n\t\t__func__, pwrctrlpriv->wowlan_power_mgmt, pwrctrlpriv->wowlan_lps_level\n\t\tWOW_LPS_1T1R_ARG\n\t);\n\n\tif (registry_par->wakeup_event & BIT(1))\n\t\tpwrctrlpriv->default_patterns_en = _TRUE;\n\telse\n\t\tpwrctrlpriv->default_patterns_en = _FALSE;\n\n\trtw_wow_pattern_sw_reset(padapter);\n#ifdef CONFIG_PNO_SUPPORT\n\tpwrctrlpriv->pno_inited = _FALSE;\n\tpwrctrlpriv->pnlo_info = NULL;\n\tpwrctrlpriv->pscan_info = NULL;\n\tpwrctrlpriv->pno_ssid_list = NULL;\n#endif /* CONFIG_PNO_SUPPORT */\n#ifdef CONFIG_WOW_PATTERN_HW_CAM\n\t_rtw_mutex_init(&pwrctrlpriv->wowlan_pattern_cam_mutex);\n#endif\n\tpwrctrlpriv->wowlan_aoac_rpt_loc = 0;\n#endif /* CONFIG_WOWLAN */\n\n#ifdef CONFIG_LPS_POFF\n\trtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_INIT, 0);\n#endif\n\n\n}\n\n\nvoid rtw_free_pwrctrl_priv(PADAPTER adapter)\n{\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter);\n\n#if defined(CONFIG_CONCURRENT_MODE)\n\tif (!is_primary_adapter(adapter))\n\t\treturn;\n#endif\n\n\n\t/* _rtw_memset((unsigned char *)pwrctrlpriv, 0, sizeof(struct pwrctrl_priv)); */\n\n\n#ifdef CONFIG_RESUME_IN_WORKQUEUE\n\tif (pwrctrlpriv->rtw_workqueue) {\n\t\tflush_workqueue(pwrctrlpriv->rtw_workqueue);\n\t\tdestroy_workqueue(pwrctrlpriv->rtw_workqueue);\n\t}\n#endif\n\n#ifdef CONFIG_LPS_POFF\n\trtw_hal_set_hwreg(adapter, HW_VAR_LPS_POFF_DEINIT, 0);\n#endif\n\n#ifdef CONFIG_LPS_LCLK\n\t_cancel_workitem_sync(&pwrctrlpriv->cpwm_event);\n\t_cancel_workitem_sync(&pwrctrlpriv->dma_event);\n\t#ifdef CONFIG_LPS_RPWM_TIMER\n\t_cancel_workitem_sync(&pwrctrlpriv->rpwmtimeoutwi);\n\t#endif\n#endif /* CONFIG_LPS_LCLK */\n\n#ifdef CONFIG_LPS_PG\n\trsvd_page_cache_free(&pwrctrlpriv->lpspg_info);\n\t#ifdef CONFIG_RTL8822C\n\trsvd_page_cache_free(&pwrctrlpriv->lpspg_dpk_info);\n\trsvd_page_cache_free(&pwrctrlpriv->lpspg_iqk_info);\n\t#endif\n#endif\n\n#ifdef CONFIG_WOWLAN\n#ifdef CONFIG_PNO_SUPPORT\n\tif (pwrctrlpriv->pnlo_info != NULL)\n\t\tprintk(\"****** pnlo_info memory leak********\\n\");\n\n\tif (pwrctrlpriv->pscan_info != NULL)\n\t\tprintk(\"****** pscan_info memory leak********\\n\");\n\n\tif (pwrctrlpriv->pno_ssid_list != NULL)\n\t\tprintk(\"****** pno_ssid_list memory leak********\\n\");\n#endif\n#ifdef CONFIG_WOW_PATTERN_HW_CAM\n\t_rtw_mutex_free(&pwrctrlpriv->wowlan_pattern_cam_mutex);\n#endif\n\n#endif /* CONFIG_WOWLAN */\n\n#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)\n\trtw_unregister_early_suspend(pwrctrlpriv);\n#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */\n\n\t_free_pwrlock(&pwrctrlpriv->lock);\n\t_free_pwrlock(&pwrctrlpriv->check_32k_lock);\n\n}\n\n#ifdef CONFIG_RESUME_IN_WORKQUEUE\nextern int rtw_resume_process(_adapter *padapter);\n\nstatic void resume_workitem_callback(struct work_struct *work)\n{\n\tstruct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, resume_work);\n\tstruct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);\n\t_adapter *adapter = dvobj_get_primary_adapter(dvobj);\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\trtw_resume_process(adapter);\n\n\trtw_resume_unlock_suspend();\n}\n\nvoid rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv)\n{\n\t/* accquire system's suspend lock preventing from falliing asleep while resume in workqueue */\n\t/* rtw_lock_suspend(); */\n\n\trtw_resume_lock_suspend();\n\n#if 1\n\tqueue_work(pwrpriv->rtw_workqueue, &pwrpriv->resume_work);\n#else\n\t_set_workitem(&pwrpriv->resume_work);\n#endif\n}\n#endif /* CONFIG_RESUME_IN_WORKQUEUE */\n\n#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)\ninline bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv)\n{\n\treturn (pwrpriv->early_suspend.suspend) ? _TRUE : _FALSE;\n}\n\ninline bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv)\n{\n\treturn (pwrpriv->do_late_resume) ? _TRUE : _FALSE;\n}\n\ninline void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable)\n{\n\tpwrpriv->do_late_resume = enable;\n}\n#endif\n\n#ifdef CONFIG_HAS_EARLYSUSPEND\nextern int rtw_resume_process(_adapter *padapter);\nstatic void rtw_early_suspend(struct early_suspend *h)\n{\n\tstruct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\trtw_set_do_late_resume(pwrpriv, _FALSE);\n}\n\nstatic void rtw_late_resume(struct early_suspend *h)\n{\n\tstruct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);\n\tstruct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);\n\t_adapter *adapter = dvobj_get_primary_adapter(dvobj);\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\tif (pwrpriv->do_late_resume) {\n\t\trtw_set_do_late_resume(pwrpriv, _FALSE);\n\t\trtw_resume_process(adapter);\n\t}\n}\n\nvoid rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv)\n{\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\t/* jeff: set the early suspend level before blank screen, so we wll do late resume after scree is lit */\n\tpwrpriv->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20;\n\tpwrpriv->early_suspend.suspend = rtw_early_suspend;\n\tpwrpriv->early_suspend.resume = rtw_late_resume;\n\tregister_early_suspend(&pwrpriv->early_suspend);\n\n\n}\n\nvoid rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv)\n{\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\trtw_set_do_late_resume(pwrpriv, _FALSE);\n\n\tif (pwrpriv->early_suspend.suspend)\n\t\tunregister_early_suspend(&pwrpriv->early_suspend);\n\n\tpwrpriv->early_suspend.suspend = NULL;\n\tpwrpriv->early_suspend.resume = NULL;\n}\n#endif /* CONFIG_HAS_EARLYSUSPEND */\n\n#ifdef CONFIG_ANDROID_POWER\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\textern int rtw_resume_process(PADAPTER padapter);\n#endif\nstatic void rtw_early_suspend(android_early_suspend_t *h)\n{\n\tstruct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\trtw_set_do_late_resume(pwrpriv, _FALSE);\n}\n\nstatic void rtw_late_resume(android_early_suspend_t *h)\n{\n\tstruct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);\n\tstruct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);\n\t_adapter *adapter = dvobj_get_primary_adapter(dvobj);\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\tif (pwrpriv->do_late_resume) {\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t\trtw_set_do_late_resume(pwrpriv, _FALSE);\n\t\trtw_resume_process(adapter);\n#endif\n\t}\n}\n\nvoid rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv)\n{\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\t/* jeff: set the early suspend level before blank screen, so we wll do late resume after scree is lit */\n\tpwrpriv->early_suspend.level = ANDROID_EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20;\n\tpwrpriv->early_suspend.suspend = rtw_early_suspend;\n\tpwrpriv->early_suspend.resume = rtw_late_resume;\n\tandroid_register_early_suspend(&pwrpriv->early_suspend);\n}\n\nvoid rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv)\n{\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\trtw_set_do_late_resume(pwrpriv, _FALSE);\n\n\tif (pwrpriv->early_suspend.suspend)\n\t\tandroid_unregister_early_suspend(&pwrpriv->early_suspend);\n\n\tpwrpriv->early_suspend.suspend = NULL;\n\tpwrpriv->early_suspend.resume = NULL;\n}\n#endif /* CONFIG_ANDROID_POWER */\n\nu8 rtw_interface_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val)\n{\n\tu8 bResult = _TRUE;\n\trtw_hal_intf_ps_func(padapter, efunc_id, val);\n\n\treturn bResult;\n}\n\n\ninline void rtw_set_ips_deny(_adapter *padapter, u32 ms)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tpwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ms);\n}\n\n/*\n* rtw_pwr_wakeup - Wake the NIC up from: 1)IPS. 2)USB autosuspend\n* @adapter: pointer to _adapter structure\n* @ips_deffer_ms: the ms wiil prevent from falling into IPS after wakeup\n* Return _SUCCESS or _FAIL\n*/\n\nint _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);\n\tstruct mlme_priv *pmlmepriv;\n\tint ret = _SUCCESS;\n\tsystime start = rtw_get_current_time();\n\n\t/*RTW_INFO(FUNC_ADPT_FMT \"===>\\n\", FUNC_ADPT_ARG(padapter));*/\n\t/* for LPS */\n\tLeaveAllPowerSaveMode(padapter);\n\n\t/* IPS still bound with primary adapter */\n\tpadapter = GET_PRIMARY_ADAPTER(padapter);\n\tpmlmepriv = &padapter->mlmepriv;\n\n\tif (rtw_time_after(rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms), pwrpriv->ips_deny_time))\n\t\tpwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms);\n\n\n\tif (pwrpriv->ps_processing) {\n\t\tRTW_INFO(\"%s wait ps_processing...\\n\", __func__);\n\t\twhile (pwrpriv->ps_processing && rtw_get_passing_time_ms(start) <= 3000)\n\t\t\trtw_msleep_os(10);\n\t\tif (pwrpriv->ps_processing)\n\t\t\tRTW_INFO(\"%s wait ps_processing timeout\\n\", __func__);\n\t\telse\n\t\t\tRTW_INFO(\"%s wait ps_processing done\\n\", __func__);\n\t}\n\n#ifdef DBG_CONFIG_ERROR_DETECT\n\tif (rtw_hal_sreset_inprogress(padapter)) {\n\t\tRTW_INFO(\"%s wait sreset_inprogress...\\n\", __func__);\n\t\twhile (rtw_hal_sreset_inprogress(padapter) && rtw_get_passing_time_ms(start) <= 4000)\n\t\t\trtw_msleep_os(10);\n\t\tif (rtw_hal_sreset_inprogress(padapter))\n\t\t\tRTW_INFO(\"%s wait sreset_inprogress timeout\\n\", __func__);\n\t\telse\n\t\t\tRTW_INFO(\"%s wait sreset_inprogress done\\n\", __func__);\n\t}\n#endif\n\n\tif (pwrpriv->bInSuspend\n\t\t#ifdef CONFIG_AUTOSUSPEND\n\t\t&& pwrpriv->bInternalAutoSuspend == _FALSE\n\t\t#endif\n\t\t) {\n\t\tRTW_INFO(\"%s wait bInSuspend...\\n\", __func__);\n\t\twhile (pwrpriv->bInSuspend\n\t\t       && ((rtw_get_passing_time_ms(start) <= 3000 && !rtw_is_do_late_resume(pwrpriv))\n\t\t\t|| (rtw_get_passing_time_ms(start) <= 500 && rtw_is_do_late_resume(pwrpriv)))\n\t\t      )\n\t\t\trtw_msleep_os(10);\n\t\tif (pwrpriv->bInSuspend)\n\t\t\tRTW_INFO(\"%s wait bInSuspend timeout\\n\", __func__);\n\t\telse\n\t\t\tRTW_INFO(\"%s wait bInSuspend done\\n\", __func__);\n\t}\n\n\t/* System suspend is not allowed to wakeup */\n\tif ((_TRUE == pwrpriv->bInSuspend)\n\t\t#ifdef CONFIG_AUTOSUSPEND\n\t\t&& (pwrpriv->bInternalAutoSuspend == _FALSE)\n\t\t#endif\n\t) {\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n#ifdef CONFIG_AUTOSUSPEND\n\t/* usb autosuspend block??? */\n\tif ((pwrpriv->bInternalAutoSuspend == _TRUE)  && (padapter->net_closed == _TRUE)) {\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n#endif\n\t/* I think this should be check in IPS, LPS, autosuspend functions... */\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {\n#if defined(CONFIG_BT_COEXIST) && defined (CONFIG_AUTOSUSPEND)\n\t\tif (_TRUE == pwrpriv->bInternalAutoSuspend) {\n\t\t\tif (0 == pwrpriv->autopm_cnt) {\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33))\n\t\t\t\tif (usb_autopm_get_interface(adapter_to_dvobj(padapter)->pusbintf) < 0)\n\t\t\t\t\tRTW_INFO(\"can't get autopm:\\n\");\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20))\n\t\t\t\tusb_autopm_disable(adapter_to_dvobj(padapter)->pusbintf);\n#else\n\t\t\t\tusb_autoresume_device(adapter_to_dvobj(padapter)->pusbdev, 1);\n#endif\n\t\t\t\tpwrpriv->autopm_cnt++;\n\t\t\t}\n#endif\t/* #if defined (CONFIG_BT_COEXIST) && defined (CONFIG_AUTOSUSPEND) */\n\t\t\tret = _SUCCESS;\n\t\t\tgoto exit;\n#if defined(CONFIG_BT_COEXIST) && defined (CONFIG_AUTOSUSPEND)\n\t\t}\n#endif\t/* #if defined (CONFIG_BT_COEXIST) && defined (CONFIG_AUTOSUSPEND) */\n\t}\n\n\tif (rf_off == pwrpriv->rf_pwrstate) {\n#ifdef CONFIG_USB_HCI\n#ifdef CONFIG_AUTOSUSPEND\n\t\tif (pwrpriv->brfoffbyhw == _TRUE) {\n\t\t\tRTW_INFO(\"hw still in rf_off state ...........\\n\");\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t} else if (padapter->registrypriv.usbss_enable) {\n\t\t\tRTW_INFO(\"%s call autoresume_enter....\\n\", __FUNCTION__);\n\t\t\tif (_FAIL ==  autoresume_enter(padapter)) {\n\t\t\t\tRTW_INFO(\"======> autoresume fail.............\\n\");\n\t\t\t\tret = _FAIL;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t} else\n#endif\n#endif\n\t\t{\n#ifdef CONFIG_IPS\n\t\t\tRTW_INFO(\"%s call ips_leave....\\n\", __FUNCTION__);\n\t\t\tif (_FAIL ==  ips_leave(padapter)) {\n\t\t\t\tRTW_INFO(\"======> ips_leave fail.............\\n\");\n\t\t\t\tret = _FAIL;\n\t\t\t\tgoto exit;\n\t\t\t}\n#endif\n\t\t}\n\t}\n\n\t/* TODO: the following checking need to be merged... */\n\tif (rtw_is_drv_stopped(padapter)\n\t    || !padapter->bup\n\t    || !rtw_is_hw_init_completed(padapter)\n\t   ) {\n\t\tRTW_INFO(\"%s: bDriverStopped=%s, bup=%d, hw_init_completed=%u\\n\"\n\t\t\t , caller\n\t\t\t , rtw_is_drv_stopped(padapter) ? \"True\" : \"False\"\n\t\t\t , padapter->bup\n\t\t\t , rtw_get_hw_init_completed(padapter));\n\t\tret = _FALSE;\n\t\tgoto exit;\n\t}\n\nexit:\n\tif (rtw_time_after(rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms), pwrpriv->ips_deny_time))\n\t\tpwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms);\n\t/*RTW_INFO(FUNC_ADPT_FMT \"<===\\n\", FUNC_ADPT_ARG(padapter));*/\n\treturn ret;\n\n}\n\nint rtw_pm_set_lps(_adapter *padapter, u8 mode)\n{\n\tint\tret = 0;\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n\n\tif (mode < PS_MODE_NUM) {\n\t\tif (pwrctrlpriv->power_mgnt != mode) {\n\t\t\tif (PS_MODE_ACTIVE == mode)\n\t\t\t\tLeaveAllPowerSaveMode(padapter);\n\t\t\telse\n\t\t\t\tpwrctrlpriv->LpsIdleCount = 2;\n\t\t\tpwrctrlpriv->power_mgnt = mode;\n\t\t\tpwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt) ? _TRUE : _FALSE;\n\t\t}\n\t} else\n\t\tret = -EINVAL;\n\n\treturn ret;\n}\n\nint rtw_pm_set_lps_level(_adapter *padapter, u8 level)\n{\n\tint\tret = 0;\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n\n\tif (level < LPS_LEVEL_MAX) {\n\t\tif (pwrctrlpriv->lps_level != level) {\n\t\t\t#ifdef CONFIG_LPS\n\t\t\tif (rtw_lps_ctrl_leave_set_level_cmd(padapter, level, RTW_CMDF_WAIT_ACK) != _SUCCESS)\n\t\t\t#endif\n\t\t\t\tpwrctrlpriv->lps_level = level;\n\t\t}\n\t} else\n\t\tret = -EINVAL;\n\n\treturn ret;\n}\n\n#ifdef CONFIG_LPS_1T1R\nint rtw_pm_set_lps_1t1r(_adapter *padapter, u8 en)\n{\n\tint\tret = 0;\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n\n\ten = en ? 1 : 0;\n\tif (pwrctrlpriv->lps_1t1r != en) {\n\t\tif (rtw_lps_ctrl_leave_set_1t1r_cmd(padapter, en, RTW_CMDF_WAIT_ACK) != _SUCCESS)\n\t\t\tpwrctrlpriv->lps_1t1r = en;\n\t}\n\n\treturn ret;\n}\n#endif\n\ninline void rtw_set_lps_deny(_adapter *adapter, u32 ms)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\tpwrpriv->lps_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ms);\n}\n\n#ifdef CONFIG_WOWLAN\nint rtw_pm_set_wow_lps(_adapter *padapter, u8 mode)\n{\n\tint\tret = 0;\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n\n\tif (mode < PS_MODE_NUM) {\n\t\tif (pwrctrlpriv->wowlan_power_mgmt != mode) \n\t\t\tpwrctrlpriv->wowlan_power_mgmt = mode;\n\t} else\n\t\tret = -EINVAL;\n\n\treturn ret;\n}\nint rtw_pm_set_wow_lps_level(_adapter *padapter, u8 level)\n{\n\tint\tret = 0;\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n\n\tif (level < LPS_LEVEL_MAX)\n\t\tpwrctrlpriv->wowlan_lps_level = level;\n\telse\n\t\tret = -EINVAL;\n\n\treturn ret;\n}\n\n#ifdef CONFIG_LPS_1T1R\nint rtw_pm_set_wow_lps_1t1r(_adapter *padapter, u8 en)\n{\n\tint\tret = 0;\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n\n\ten = en ? 1 : 0;\n\tpwrctrlpriv->wowlan_lps_1t1r = en;\n\n\treturn ret;\n}\n#endif /* CONFIG_LPS_1T1R */\n#endif /* CONFIG_WOWLAN */\n\nint rtw_pm_set_ips(_adapter *padapter, u8 mode)\n{\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n\n\tif (mode == IPS_NORMAL || mode == IPS_LEVEL_2) {\n\t\trtw_ips_mode_req(pwrctrlpriv, mode);\n\t\tRTW_INFO(\"%s %s\\n\", __FUNCTION__, mode == IPS_NORMAL ? \"IPS_NORMAL\" : \"IPS_LEVEL_2\");\n\t\treturn 0;\n\t} else if (mode == IPS_NONE) {\n\t\trtw_ips_mode_req(pwrctrlpriv, mode);\n\t\tRTW_INFO(\"%s %s\\n\", __FUNCTION__, \"IPS_NONE\");\n\t\tif (!rtw_is_surprise_removed(padapter) && (_FAIL == rtw_pwr_wakeup(padapter)))\n\t\t\treturn -EFAULT;\n\t} else\n\t\treturn -EINVAL;\n\treturn 0;\n}\n\n/*\n * ATTENTION:\n *\tThis function will request pwrctrl LOCK!\n */\nvoid rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason)\n{\n\tstruct pwrctrl_priv *pwrpriv;\n\n\t/* \tRTW_INFO(\"+\" FUNC_ADPT_FMT \": Request PS deny for %d (0x%08X)\\n\",\n\t *\t\tFUNC_ADPT_ARG(padapter), reason, BIT(reason)); */\n\n\tpwrpriv = adapter_to_pwrctl(padapter);\n\n\t_enter_pwrlock(&pwrpriv->lock);\n\tif (pwrpriv->ps_deny & BIT(reason)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": [WARNING] Reason %d had been set before!!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter), reason);\n\t}\n\tpwrpriv->ps_deny |= BIT(reason);\n\t_exit_pwrlock(&pwrpriv->lock);\n\n\t/* \tRTW_INFO(\"-\" FUNC_ADPT_FMT \": Now PS deny for 0x%08X\\n\",\n\t *\t\tFUNC_ADPT_ARG(padapter), pwrpriv->ps_deny); */\n}\n\n/*\n * ATTENTION:\n *\tThis function will request pwrctrl LOCK!\n */\nvoid rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason)\n{\n\tstruct pwrctrl_priv *pwrpriv;\n\n\n\t/* \tRTW_INFO(\"+\" FUNC_ADPT_FMT \": Cancel PS deny for %d(0x%08X)\\n\",\n\t *\t\tFUNC_ADPT_ARG(padapter), reason, BIT(reason)); */\n\n\tpwrpriv = adapter_to_pwrctl(padapter);\n\n\t_enter_pwrlock(&pwrpriv->lock);\n\tif ((pwrpriv->ps_deny & BIT(reason)) == 0) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": [ERROR] Reason %d had been canceled before!!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter), reason);\n\t}\n\tpwrpriv->ps_deny &= ~BIT(reason);\n\t_exit_pwrlock(&pwrpriv->lock);\n\n\t/* \tRTW_INFO(\"-\" FUNC_ADPT_FMT \": Now PS deny for 0x%08X\\n\",\n\t *\t\tFUNC_ADPT_ARG(padapter), pwrpriv->ps_deny); */\n}\n\n/*\n * ATTENTION:\n *\tBefore calling this function pwrctrl lock should be occupied already,\n *\totherwise it may return incorrect value.\n */\nu32 rtw_ps_deny_get(PADAPTER padapter)\n{\n\tu32 deny;\n\n\n\tdeny = adapter_to_pwrctl(padapter)->ps_deny;\n\n\treturn deny;\n}\n\nstatic void _rtw_ssmps(_adapter *adapter, struct sta_info *sta)\n{\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tif (MLME_IS_STA(adapter)) {\n\t\tissue_action_SM_PS_wait_ack(adapter , get_my_bssid(&(pmlmeinfo->network)),\n\t\t\tsta->cmn.sm_ps, 3 , 1);\n\t}\n\telse if (MLME_IS_AP(adapter)) {\n\n\t}\n\trtw_phydm_ra_registed(adapter, sta);\n}\nvoid rtw_ssmps_enter(_adapter *adapter, struct sta_info *sta)\n{\n\tif (sta->cmn.sm_ps == SM_PS_STATIC)\n\t\treturn;\n\n\tRTW_INFO(ADPT_FMT\" STA [\" MAC_FMT \"]\\n\", ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));\n\n\tsta->cmn.sm_ps = SM_PS_STATIC;\n\t_rtw_ssmps(adapter, sta);\n}\nvoid rtw_ssmps_leave(_adapter *adapter, struct sta_info *sta)\n{\n\tif (sta->cmn.sm_ps == SM_PS_DISABLE)\n\t\treturn;\n\n\tRTW_INFO(ADPT_FMT\" STA [\" MAC_FMT \"] \\n\", ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));\n\tsta->cmn.sm_ps = SM_PS_DISABLE;\n\t_rtw_ssmps(adapter, sta);\n}\n\n"
  },
  {
    "path": "core/rtw_recv.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_RECV_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\n#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS\nstatic void rtw_signal_stat_timer_hdl(void *ctx);\n\nenum {\n\tSIGNAL_STAT_CALC_PROFILE_0 = 0,\n\tSIGNAL_STAT_CALC_PROFILE_1,\n\tSIGNAL_STAT_CALC_PROFILE_MAX\n};\n\nu8 signal_stat_calc_profile[SIGNAL_STAT_CALC_PROFILE_MAX][2] = {\n\t{4, 1},\t/* Profile 0 => pre_stat : curr_stat = 4 : 1 */\n\t{3, 7}\t/* Profile 1 => pre_stat : curr_stat = 3 : 7 */\n};\n\n#ifndef RTW_SIGNAL_STATE_CALC_PROFILE\n\t#define RTW_SIGNAL_STATE_CALC_PROFILE SIGNAL_STAT_CALC_PROFILE_1\n#endif\n\n#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */\n\nu8 rtw_bridge_tunnel_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 };\nu8 rtw_rfc1042_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 };\nstatic u8 SNAP_ETH_TYPE_IPX[2] = {0x81, 0x37};\nstatic u8 SNAP_ETH_TYPE_APPLETALK_AARP[2] = {0x80, 0xf3};\n#ifdef CONFIG_TDLS\nstatic u8 SNAP_ETH_TYPE_TDLS[2] = {0x89, 0x0d};\n#endif\n\n#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL\nint recv_frame_monitor(_adapter *padapter, union recv_frame *rframe);\n#endif\nvoid _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv)\n{\n\n\n\n\t_rtw_memset((u8 *)psta_recvpriv, 0, sizeof(struct sta_recv_priv));\n\n\t_rtw_spinlock_init(&psta_recvpriv->lock);\n\n\t/* for(i=0; i<MAX_RX_NUMBLKS; i++) */\n\t/*\t_rtw_init_queue(&psta_recvpriv->blk_strms[i]); */\n\n\t_rtw_init_queue(&psta_recvpriv->defrag_q);\n\n\n}\n\nsint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter)\n{\n\tsint i;\n\n\tunion recv_frame *precvframe;\n\tsint\tres = _SUCCESS;\n\n\n\t/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */\n\t/* _rtw_memset((unsigned char *)precvpriv, 0, sizeof (struct  recv_priv)); */\n\n\t_rtw_spinlock_init(&precvpriv->lock);\n\n#ifdef CONFIG_RECV_THREAD_MODE\n\t_rtw_init_sema(&precvpriv->recv_sema, 0);\n\n#endif\n\n\t_rtw_init_queue(&precvpriv->free_recv_queue);\n\t_rtw_init_queue(&precvpriv->recv_pending_queue);\n\t_rtw_init_queue(&precvpriv->uc_swdec_pending_queue);\n\n\tprecvpriv->adapter = padapter;\n\n\tprecvpriv->free_recvframe_cnt = NR_RECVFRAME;\n\n\tprecvpriv->sink_udpport = 0;\n\tprecvpriv->pre_rtp_rxseq = 0;\n\tprecvpriv->cur_rtp_rxseq = 0;\n\n#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA\n\tprecvpriv->store_law_data_flag = 1;\n#else\n\tprecvpriv->store_law_data_flag = 0;\n#endif\n\n\trtw_os_recv_resource_init(precvpriv, padapter);\n\n\tprecvpriv->pallocated_frame_buf = rtw_zvmalloc(NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ);\n\n\tif (precvpriv->pallocated_frame_buf == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\t/* _rtw_memset(precvpriv->pallocated_frame_buf, 0, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); */\n\n\tprecvpriv->precv_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_frame_buf), RXFRAME_ALIGN_SZ);\n\t/* precvpriv->precv_frame_buf = precvpriv->pallocated_frame_buf + RXFRAME_ALIGN_SZ - */\n\t/*\t\t\t\t\t\t((SIZE_PTR) (precvpriv->pallocated_frame_buf) &(RXFRAME_ALIGN_SZ-1)); */\n\n\tprecvframe = (union recv_frame *) precvpriv->precv_frame_buf;\n\n\n\tfor (i = 0; i < NR_RECVFRAME ; i++) {\n\t\t_rtw_init_listhead(&(precvframe->u.list));\n\n\t\trtw_list_insert_tail(&(precvframe->u.list), &(precvpriv->free_recv_queue.queue));\n\n\t\tres = rtw_os_recv_resource_alloc(padapter, precvframe);\n\n\t\tprecvframe->u.hdr.len = 0;\n\n\t\tprecvframe->u.hdr.adapter = padapter;\n\t\tprecvframe++;\n\n\t}\n\n#ifdef CONFIG_USB_HCI\n\n\tATOMIC_SET(&(precvpriv->rx_pending_cnt), 1);\n\n\t_rtw_init_sema(&precvpriv->allrxreturnevt, 0);\n\n#endif\n\n\tres = rtw_hal_init_recv_priv(padapter);\n\n#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS\n\trtw_init_timer(&precvpriv->signal_stat_timer, padapter, rtw_signal_stat_timer_hdl, padapter);\n\n\tprecvpriv->signal_stat_sampling_interval = 2000; /* ms */\n\t/* precvpriv->signal_stat_converging_constant = 5000; */ /* ms */\n\n\trtw_set_signal_stat_timer(precvpriv);\n#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */\n\nexit:\n\n\n\treturn res;\n\n}\n\nvoid rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv);\nvoid rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv)\n{\n\t_rtw_spinlock_free(&precvpriv->lock);\n#ifdef CONFIG_RECV_THREAD_MODE\n\t_rtw_free_sema(&precvpriv->recv_sema);\n#endif\n\n\t_rtw_spinlock_free(&precvpriv->free_recv_queue.lock);\n\t_rtw_spinlock_free(&precvpriv->recv_pending_queue.lock);\n\n\t_rtw_spinlock_free(&precvpriv->free_recv_buf_queue.lock);\n\n#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX\n\t_rtw_spinlock_free(&precvpriv->recv_buf_pending_queue.lock);\n#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */\n}\n\nvoid _rtw_free_recv_priv(struct recv_priv *precvpriv)\n{\n\t_adapter\t*padapter = precvpriv->adapter;\n\n\n\trtw_free_uc_swdec_pending_queue(padapter);\n\n\trtw_mfree_recv_priv_lock(precvpriv);\n\n\trtw_os_recv_resource_free(precvpriv);\n\n\tif (precvpriv->pallocated_frame_buf)\n\t\trtw_vmfree(precvpriv->pallocated_frame_buf, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ);\n\n\trtw_hal_free_recv_priv(padapter);\n\n\n}\n\nbool rtw_rframe_del_wfd_ie(union recv_frame *rframe, u8 ies_offset)\n{\n#define DBG_RFRAME_DEL_WFD_IE 0\n\tu8 *ies = rframe->u.hdr.rx_data + sizeof(struct rtw_ieee80211_hdr_3addr) + ies_offset;\n\tuint ies_len_ori = rframe->u.hdr.len - (ies - rframe->u.hdr.rx_data);\n\tuint ies_len;\n\n\ties_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_RFRAME_DEL_WFD_IE ? __func__ : NULL);\n\trframe->u.hdr.len -= ies_len_ori - ies_len;\n\n\treturn ies_len_ori != ies_len;\n}\n\nunion recv_frame *_rtw_alloc_recvframe(_queue *pfree_recv_queue)\n{\n\n\tunion recv_frame  *precvframe;\n\t_list\t*plist, *phead;\n\t_adapter *padapter;\n\tstruct recv_priv *precvpriv;\n\n\tif (_rtw_queue_empty(pfree_recv_queue) == _TRUE)\n\t\tprecvframe = NULL;\n\telse {\n\t\tphead = get_list_head(pfree_recv_queue);\n\n\t\tplist = get_next(phead);\n\n\t\tprecvframe = LIST_CONTAINOR(plist, union recv_frame, u);\n\n\t\trtw_list_delete(&precvframe->u.hdr.list);\n\t\tpadapter = precvframe->u.hdr.adapter;\n\t\tif (padapter != NULL) {\n\t\t\tprecvpriv = &padapter->recvpriv;\n\t\t\tif (pfree_recv_queue == &precvpriv->free_recv_queue)\n\t\t\t\tprecvpriv->free_recvframe_cnt--;\n\t\t}\n\t}\n\n\n\treturn precvframe;\n\n}\n\nunion recv_frame *rtw_alloc_recvframe(_queue *pfree_recv_queue)\n{\n\t_irqL irqL;\n\tunion recv_frame  *precvframe;\n\n\t_enter_critical_bh(&pfree_recv_queue->lock, &irqL);\n\n\tprecvframe = _rtw_alloc_recvframe(pfree_recv_queue);\n\n\t_exit_critical_bh(&pfree_recv_queue->lock, &irqL);\n\n\treturn precvframe;\n}\n\nvoid rtw_init_recvframe(union recv_frame *precvframe, struct recv_priv *precvpriv)\n{\n\t/* Perry: This can be removed */\n\t_rtw_init_listhead(&precvframe->u.hdr.list);\n\n\tprecvframe->u.hdr.len = 0;\n}\n\nint rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue)\n{\n\t_irqL irqL;\n\t_adapter *padapter = precvframe->u.hdr.adapter;\n\tstruct recv_priv *precvpriv = &padapter->recvpriv;\n\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tpadapter = GET_PRIMARY_ADAPTER(padapter);\n\tprecvpriv = &padapter->recvpriv;\n\tpfree_recv_queue = &precvpriv->free_recv_queue;\n\tprecvframe->u.hdr.adapter = padapter;\n#endif\n\n\n\trtw_os_free_recvframe(precvframe);\n\n\n\t_enter_critical_bh(&pfree_recv_queue->lock, &irqL);\n\n\trtw_list_delete(&(precvframe->u.hdr.list));\n\n\tprecvframe->u.hdr.len = 0;\n\n\trtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(pfree_recv_queue));\n\n\tif (padapter != NULL) {\n\t\tif (pfree_recv_queue == &precvpriv->free_recv_queue)\n\t\t\tprecvpriv->free_recvframe_cnt++;\n\t}\n\n\t_exit_critical_bh(&pfree_recv_queue->lock, &irqL);\n\n\n\treturn _SUCCESS;\n\n}\n\n\n\n\nsint _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue)\n{\n\n\t_adapter *padapter = precvframe->u.hdr.adapter;\n\tstruct recv_priv *precvpriv = &padapter->recvpriv;\n\n\n\t/* _rtw_init_listhead(&(precvframe->u.hdr.list)); */\n\trtw_list_delete(&(precvframe->u.hdr.list));\n\n\n\trtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(queue));\n\n\tif (padapter != NULL) {\n\t\tif (queue == &precvpriv->free_recv_queue)\n\t\t\tprecvpriv->free_recvframe_cnt++;\n\t}\n\n\n\treturn _SUCCESS;\n}\n\nsint rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue)\n{\n\tsint ret;\n\t_irqL irqL;\n\n\t/* _spinlock(&pfree_recv_queue->lock); */\n\t_enter_critical_bh(&queue->lock, &irqL);\n\tret = _rtw_enqueue_recvframe(precvframe, queue);\n\t/* _rtw_spinunlock(&pfree_recv_queue->lock); */\n\t_exit_critical_bh(&queue->lock, &irqL);\n\n\treturn ret;\n}\n\n/*\nsint\trtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue)\n{\n\treturn rtw_free_recvframe(precvframe, queue);\n}\n*/\n\n\n\n\n/*\ncaller : defrag ; recvframe_chk_defrag in recv_thread  (passive)\npframequeue: defrag_queue : will be accessed in recv_thread  (passive)\n\nusing spinlock to protect\n\n*/\n\nvoid rtw_free_recvframe_queue(_queue *pframequeue,  _queue *pfree_recv_queue)\n{\n\tunion\trecv_frame\t*precvframe;\n\t_list\t*plist, *phead;\n\n\t_rtw_spinlock(&pframequeue->lock);\n\n\tphead = get_list_head(pframequeue);\n\tplist = get_next(phead);\n\n\twhile (rtw_end_of_queue_search(phead, plist) == _FALSE) {\n\t\tprecvframe = LIST_CONTAINOR(plist, union recv_frame, u);\n\n\t\tplist = get_next(plist);\n\n\t\t/* rtw_list_delete(&precvframe->u.hdr.list); */ /* will do this in rtw_free_recvframe() */\n\n\t\trtw_free_recvframe(precvframe, pfree_recv_queue);\n\t}\n\n\t_rtw_spinunlock(&pframequeue->lock);\n\n\n}\n\nu32 rtw_free_uc_swdec_pending_queue(_adapter *adapter)\n{\n\tu32 cnt = 0;\n\tunion recv_frame *pending_frame;\n\twhile ((pending_frame = rtw_alloc_recvframe(&adapter->recvpriv.uc_swdec_pending_queue))) {\n\t\trtw_free_recvframe(pending_frame, &adapter->recvpriv.free_recv_queue);\n\t\tcnt++;\n\t}\n\n\tif (cnt)\n\t\tRTW_INFO(FUNC_ADPT_FMT\" dequeue %d\\n\", FUNC_ADPT_ARG(adapter), cnt);\n\n\treturn cnt;\n}\n\n\nsint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue)\n{\n\t_irqL irqL;\n\n\t_enter_critical_bh(&queue->lock, &irqL);\n\n\trtw_list_delete(&precvbuf->list);\n\trtw_list_insert_head(&precvbuf->list, get_list_head(queue));\n\n\t_exit_critical_bh(&queue->lock, &irqL);\n\n\treturn _SUCCESS;\n}\n\nsint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue)\n{\n\t_irqL irqL;\n#ifdef CONFIG_SDIO_HCI\n\t_enter_critical_bh(&queue->lock, &irqL);\n#else\n\t_enter_critical_ex(&queue->lock, &irqL);\n#endif/*#ifdef CONFIG_SDIO_HCI*/\n\n\trtw_list_delete(&precvbuf->list);\n\n\trtw_list_insert_tail(&precvbuf->list, get_list_head(queue));\n#ifdef CONFIG_SDIO_HCI\n\t_exit_critical_bh(&queue->lock, &irqL);\n#else\n\t_exit_critical_ex(&queue->lock, &irqL);\n#endif/*#ifdef CONFIG_SDIO_HCI*/\n\treturn _SUCCESS;\n\n}\n\nstruct recv_buf *rtw_dequeue_recvbuf(_queue *queue)\n{\n\t_irqL irqL;\n\tstruct recv_buf *precvbuf;\n\t_list\t*plist, *phead;\n\n#ifdef CONFIG_SDIO_HCI\n\t_enter_critical_bh(&queue->lock, &irqL);\n#else\n\t_enter_critical_ex(&queue->lock, &irqL);\n#endif/*#ifdef CONFIG_SDIO_HCI*/\n\n\tif (_rtw_queue_empty(queue) == _TRUE)\n\t\tprecvbuf = NULL;\n\telse {\n\t\tphead = get_list_head(queue);\n\n\t\tplist = get_next(phead);\n\n\t\tprecvbuf = LIST_CONTAINOR(plist, struct recv_buf, list);\n\n\t\trtw_list_delete(&precvbuf->list);\n\n\t}\n\n#ifdef CONFIG_SDIO_HCI\n\t_exit_critical_bh(&queue->lock, &irqL);\n#else\n\t_exit_critical_ex(&queue->lock, &irqL);\n#endif/*#ifdef CONFIG_SDIO_HCI*/\n\n\treturn precvbuf;\n\n}\n\nsint recvframe_chkmic(_adapter *adapter,  union recv_frame *precvframe);\nsint recvframe_chkmic(_adapter *adapter,  union recv_frame *precvframe)\n{\n\n\tsint\ti, res = _SUCCESS;\n\tu32\tdatalen;\n\tu8\tmiccode[8];\n\tu8\tbmic_err = _FALSE, brpt_micerror = _TRUE;\n\tu8\t*pframe, *payload, *pframemic;\n\tu8\t*mickey;\n\t/* u8\t*iv,rxdata_key_idx=0; */\n\tstruct\tsta_info\t\t*stainfo;\n\tstruct\trx_pkt_attrib\t*prxattrib = &precvframe->u.hdr.attrib;\n\tstruct\tsecurity_priv\t*psecuritypriv = &adapter->securitypriv;\n\n\tstruct mlme_ext_priv\t*pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tstainfo = rtw_get_stainfo(&adapter->stapriv , &prxattrib->ta[0]);\n\n\tif (prxattrib->encrypt == _TKIP_) {\n\n\t\t/* calculate mic code */\n\t\tif (stainfo != NULL) {\n\t\t\tif (IS_MCAST(prxattrib->ra)) {\n\t\t\t\t/* mickey=&psecuritypriv->dot118021XGrprxmickey.skey[0]; */\n\t\t\t\t/* iv = precvframe->u.hdr.rx_data+prxattrib->hdrlen; */\n\t\t\t\t/* rxdata_key_idx =( ((iv[3])>>6)&0x3) ; */\n\t\t\t\tmickey = &psecuritypriv->dot118021XGrprxmickey[prxattrib->key_index].skey[0];\n\n\t\t\t\t/* RTW_INFO(\"\\n recvframe_chkmic: bcmc key psecuritypriv->dot118021XGrpKeyid(%d),pmlmeinfo->key_index(%d) ,recv key_id(%d)\\n\", */\n\t\t\t\t/*\t\t\t\t\t\t\t\tpsecuritypriv->dot118021XGrpKeyid,pmlmeinfo->key_index,rxdata_key_idx); */\n\n\t\t\t\tif (psecuritypriv->binstallGrpkey == _FALSE) {\n\t\t\t\t\tres = _FAIL;\n\t\t\t\t\tRTW_INFO(\"\\n recvframe_chkmic:didn't install group key!!!!!!!!!!\\n\");\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tmickey = &stainfo->dot11tkiprxmickey.skey[0];\n\t\t\t}\n\n\t\t\tdatalen = precvframe->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len - prxattrib->icv_len - 8; /* icv_len included the mic code */\n\t\t\tpframe = precvframe->u.hdr.rx_data;\n\t\t\tpayload = pframe + prxattrib->hdrlen + prxattrib->iv_len;\n\n\n\t\t\t/* rtw_seccalctkipmic(&stainfo->dot11tkiprxmickey.skey[0],pframe,payload, datalen ,&miccode[0],(unsigned char)prxattrib->priority); */ /* care the length of the data */\n\n\t\t\trtw_seccalctkipmic(mickey, pframe, payload, datalen , &miccode[0], (unsigned char)prxattrib->priority); /* care the length of the data */\n\n\t\t\tpframemic = payload + datalen;\n\n\t\t\tbmic_err = _FALSE;\n\n\t\t\tfor (i = 0; i < 8; i++) {\n\t\t\t\tif (miccode[i] != *(pframemic + i)) {\n\t\t\t\t\tbmic_err = _TRUE;\n\t\t\t\t}\n\t\t\t}\n\n\n\t\t\tif (bmic_err == _TRUE) {\n\n\n\n\t\t\t\t/* double check key_index for some timing issue , */\n\t\t\t\t/* cannot compare with psecuritypriv->dot118021XGrpKeyid also cause timing issue */\n\t\t\t\tif ((IS_MCAST(prxattrib->ra) == _TRUE)  && (prxattrib->key_index != pmlmeinfo->key_index))\n\t\t\t\t\tbrpt_micerror = _FALSE;\n\n\t\t\t\tif ((prxattrib->bdecrypted == _TRUE) && (brpt_micerror == _TRUE)) {\n\t\t\t\t\trtw_handle_tkip_mic_err(adapter, stainfo, (u8)IS_MCAST(prxattrib->ra));\n\t\t\t\t\tRTW_INFO(\" mic error :prxattrib->bdecrypted=%d\\n\", prxattrib->bdecrypted);\n\t\t\t\t} else {\n\t\t\t\t\tRTW_INFO(\" mic error :prxattrib->bdecrypted=%d\\n\", prxattrib->bdecrypted);\n\t\t\t\t}\n\n\t\t\t\tres = _FAIL;\n\n\t\t\t} else {\n\t\t\t\t/* mic checked ok */\n\t\t\t\tif ((psecuritypriv->bcheck_grpkey == _FALSE) && (IS_MCAST(prxattrib->ra) == _TRUE)) {\n\t\t\t\t\tpsecuritypriv->bcheck_grpkey = _TRUE;\n\t\t\t\t}\n\t\t\t}\n\n\t\t}\n\n\t\trecvframe_pull_tail(precvframe, 8);\n\n\t}\n\nexit:\n\n\n\treturn res;\n\n}\n\n/*#define DBG_RX_SW_DECRYPTOR*/\n\n/* decrypt and set the ivlen,icvlen of the recv_frame */\nunion recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame);\nunion recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame)\n{\n\n\tstruct rx_pkt_attrib *prxattrib = &precv_frame->u.hdr.attrib;\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tunion recv_frame *return_packet = precv_frame;\n\tu32\t res = _SUCCESS;\n\n\n\tDBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt);\n\n\n\tif (prxattrib->encrypt > 0) {\n\t\tu8 *iv = precv_frame->u.hdr.rx_data + prxattrib->hdrlen;\n\t\tprxattrib->key_index = (((iv[3]) >> 6) & 0x3) ;\n\n\t\tif (prxattrib->key_index > WEP_KEYS) {\n\t\t\tRTW_INFO(\"prxattrib->key_index(%d) > WEP_KEYS\\n\", prxattrib->key_index);\n\n\t\t\tswitch (prxattrib->encrypt) {\n\t\t\tcase _WEP40_:\n\t\t\tcase _WEP104_:\n\t\t\t\tprxattrib->key_index = psecuritypriv->dot11PrivacyKeyIndex;\n\t\t\t\tbreak;\n\t\t\tcase _TKIP_:\n\t\t\tcase _AES_:\n\t\t\tdefault:\n\t\t\t\tprxattrib->key_index = psecuritypriv->dot118021XGrpKeyid;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (prxattrib->encrypt && !prxattrib->bdecrypted) {\n\t\tif (GetFrameType(get_recvframe_data(precv_frame)) == WIFI_DATA\n\t\t\t#ifdef CONFIG_CONCURRENT_MODE\n\t\t\t&& !IS_MCAST(prxattrib->ra) /* bc/mc packets may use sw decryption for concurrent mode */\n\t\t\t#endif\n\t\t)\n\t\t\tpsecuritypriv->hw_decrypted = _FALSE;\n\n#ifdef DBG_RX_SW_DECRYPTOR\n\t\tRTW_INFO(ADPT_FMT\" - sec_type:%s DO SW decryption\\n\",\n\t\t\tADPT_ARG(padapter), security_type_str(prxattrib->encrypt));\n#endif\n\n#ifdef DBG_RX_DECRYPTOR\n\t\tRTW_INFO(\"[%s] %d:prxstat->bdecrypted:%d,  prxattrib->encrypt:%d,  Setting psecuritypriv->hw_decrypted = %d\\n\",\n\t\t\t __FUNCTION__,\n\t\t\t __LINE__,\n\t\t\t prxattrib->bdecrypted,\n\t\t\t prxattrib->encrypt,\n\t\t\t psecuritypriv->hw_decrypted);\n#endif\n\n\t\tswitch (prxattrib->encrypt) {\n\t\tcase _WEP40_:\n\t\tcase _WEP104_:\n\t\t\tDBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_wep);\n\t\t\trtw_wep_decrypt(padapter, (u8 *)precv_frame);\n\t\t\tbreak;\n\t\tcase _TKIP_:\n\t\t\tDBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_tkip);\n\t\t\tres = rtw_tkip_decrypt(padapter, (u8 *)precv_frame);\n\t\t\tbreak;\n\t\tcase _AES_:\n\t\t\tDBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_aes);\n\t\t\tres = rtw_aes_decrypt(padapter, (u8 *)precv_frame);\n\t\t\tbreak;\n#ifdef CONFIG_WAPI_SUPPORT\n\t\tcase _SMS4_:\n\t\t\tDBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_wapi);\n\t\t\trtw_sms4_decrypt(padapter, (u8 *)precv_frame);\n\t\t\tbreak;\n#endif\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t} else if (prxattrib->bdecrypted == 1\n\t\t   && prxattrib->encrypt > 0\n\t\t&& (psecuritypriv->busetkipkey == 1 || prxattrib->encrypt != _TKIP_)\n\t\t  ) {\n#if 0\n\t\tif ((prxstat->icv == 1) && (prxattrib->encrypt != _AES_)) {\n\t\t\tpsecuritypriv->hw_decrypted = _FALSE;\n\n\n\t\t\trtw_free_recvframe(precv_frame, &padapter->recvpriv.free_recv_queue);\n\n\t\t\treturn_packet = NULL;\n\n\t\t} else\n#endif\n\t\t{\n\t\t\tDBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_hw);\n\n\t\t\tpsecuritypriv->hw_decrypted = _TRUE;\n#ifdef DBG_RX_DECRYPTOR\n\t\t\tRTW_INFO(\"[%s] %d:prxstat->bdecrypted:%d,  prxattrib->encrypt:%d,  Setting psecuritypriv->hw_decrypted = %d\\n\",\n\t\t\t\t __FUNCTION__,\n\t\t\t\t __LINE__,\n\t\t\t\t prxattrib->bdecrypted,\n\t\t\t\t prxattrib->encrypt,\n\t\t\t\t psecuritypriv->hw_decrypted);\n\n#endif\n\t\t}\n\t} else {\n\t\tDBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_unknown);\n#ifdef DBG_RX_DECRYPTOR\n\t\tRTW_INFO(\"[%s] %d:prxstat->bdecrypted:%d,  prxattrib->encrypt:%d,  Setting psecuritypriv->hw_decrypted = %d\\n\",\n\t\t\t __FUNCTION__,\n\t\t\t __LINE__,\n\t\t\t prxattrib->bdecrypted,\n\t\t\t prxattrib->encrypt,\n\t\t\t psecuritypriv->hw_decrypted);\n#endif\n\t}\n\n\t#ifdef CONFIG_RTW_MESH\n\tif (res != _FAIL\n\t\t&& !prxattrib->amsdu\n\t\t&& prxattrib->mesh_ctrl_present)\n\t\tres = rtw_mesh_rx_validate_mctrl_non_amsdu(padapter, precv_frame);\n\t#endif\n\n\tif (res == _FAIL) {\n\t\trtw_free_recvframe(return_packet, &padapter->recvpriv.free_recv_queue);\n\t\treturn_packet = NULL;\n\t} else\n\t\tprxattrib->bdecrypted = _TRUE;\n\t/* recvframe_chkmic(adapter, precv_frame);   */ /* move to recvframme_defrag function */\n\n\n\treturn return_packet;\n\n}\n/* ###set the security information in the recv_frame */\nunion recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame);\nunion recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame)\n{\n\tu8 *psta_addr = NULL;\n\tu8 *ptr;\n\tuint  auth_alg;\n\tstruct recv_frame_hdr *pfhdr;\n\tstruct sta_info *psta;\n\tstruct sta_priv *pstapriv ;\n\tunion recv_frame *prtnframe;\n\tu16\tether_type = 0;\n\tu16  eapol_type = 0x888e;/* for Funia BD's WPA issue  */\n\tstruct rx_pkt_attrib *pattrib;\n\n\n\tpstapriv = &adapter->stapriv;\n\n\tauth_alg = adapter->securitypriv.dot11AuthAlgrthm;\n\n\tptr = get_recvframe_data(precv_frame);\n\tpfhdr = &precv_frame->u.hdr;\n\tpattrib = &pfhdr->attrib;\n\tpsta_addr = pattrib->ta;\n\n\tprtnframe = NULL;\n\n\tpsta = rtw_get_stainfo(pstapriv, psta_addr);\n\n\n\tif (auth_alg == dot11AuthAlgrthm_8021X) {\n\t\tif ((psta != NULL) && (psta->ieee8021x_blocked)) {\n\t\t\t/* blocked */\n\t\t\t/* only accept EAPOL frame */\n\n\t\t\tprtnframe = precv_frame;\n\n\t\t\t/* get ether_type */\n\t\t\tptr = ptr + pfhdr->attrib.hdrlen + pfhdr->attrib.iv_len + LLC_HEADER_SIZE;\n\t\t\t_rtw_memcpy(&ether_type, ptr, 2);\n\t\t\tether_type = ntohs((unsigned short)ether_type);\n\n\t\t\tif (ether_type == eapol_type)\n\t\t\t\tprtnframe = precv_frame;\n\t\t\telse {\n\t\t\t\t/* free this frame */\n\t\t\t\trtw_free_recvframe(precv_frame, &adapter->recvpriv.free_recv_queue);\n\t\t\t\tprtnframe = NULL;\n\t\t\t}\n\t\t} else {\n\t\t\t/* allowed */\n\t\t\t/* check decryption status, and decrypt the frame if needed */\n\n\n\t\t\tprtnframe = precv_frame;\n\t\t\t/* check is the EAPOL frame or not (Rekey) */\n\t\t\t/* if(ether_type == eapol_type){ */\n\t\t\t/* check Rekey */\n\n\t\t\t/*\tprtnframe=precv_frame; */\n\t\t\t/* } */\n\t\t}\n\t} else\n\t\tprtnframe = precv_frame;\n\n\n\treturn prtnframe;\n\n}\n\n/* VALID_PN_CHK\n * Return true when PN is legal, otherwise false.\n * Legal PN:\n *\t1. If old PN is 0, any PN is legal\n *\t2. PN > old PN\n */\n#define PN_LESS_CHK(a, b)\t(((a-b) & 0x800000000000) != 0)\n#define VALID_PN_CHK(new, old)\t(((old) == 0) || PN_LESS_CHK(old, new))\n#define CCMPH_2_KEYID(ch)\t(((ch) & 0x00000000c0000000) >> 30)\nsint recv_ucast_pn_decache(union recv_frame *precv_frame);\nsint recv_ucast_pn_decache(union recv_frame *precv_frame)\n{\n\tstruct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;\n\tstruct sta_info *sta = precv_frame->u.hdr.psta;\n\tstruct stainfo_rxcache *prxcache = &sta->sta_recvpriv.rxcache;\n\tu8 *pdata = precv_frame->u.hdr.rx_data;\n\tsint tid = precv_frame->u.hdr.attrib.priority;\n\tu64 tmp_iv_hdr = 0;\n\tu64 curr_pn = 0, pkt_pn = 0;\n\n\tif (tid > 15)\n\t\treturn _FAIL;\n\n\tif (pattrib->encrypt == _AES_) {\n\t\ttmp_iv_hdr = le64_to_cpu(*(u64*)(pdata + pattrib->hdrlen));\n\t\tpkt_pn = CCMPH_2_PN(tmp_iv_hdr);\n\t\ttmp_iv_hdr = le64_to_cpu(*(u64*)prxcache->iv[tid]);\n\t\tcurr_pn = CCMPH_2_PN(tmp_iv_hdr);\n\n\t\tif (!VALID_PN_CHK(pkt_pn, curr_pn)) {\n\t\t\t/* return _FAIL; */\n\t\t} else {\n\t\t\tprxcache->last_tid = tid;\n\t\t\t_rtw_memcpy(prxcache->iv[tid],\n\t\t\t\t    (pdata + pattrib->hdrlen),\n\t\t\t\t    sizeof(prxcache->iv[tid]));\n\t\t}\n\t}\n\n\treturn _SUCCESS;\n}\n\nsint recv_bcast_pn_decache(union recv_frame *precv_frame);\nsint recv_bcast_pn_decache(union recv_frame *precv_frame)\n{\n\t_adapter *padapter = precv_frame->u.hdr.adapter;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tstruct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;\n\tu8 *pdata = precv_frame->u.hdr.rx_data;\n\tu64 tmp_iv_hdr = 0;\n\tu64 curr_pn = 0, pkt_pn = 0;\n\tu8 key_id;\n\n\tif ((pattrib->encrypt == _AES_) &&\n\t\t(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) {\n\n\t\ttmp_iv_hdr = le64_to_cpu(*(u64*)(pdata + pattrib->hdrlen));\n\t\tkey_id = CCMPH_2_KEYID(tmp_iv_hdr);\n\t\tpkt_pn = CCMPH_2_PN(tmp_iv_hdr);\n\n\t\tcurr_pn = le64_to_cpu(*(u64*)psecuritypriv->iv_seq[key_id]);\n\t\tcurr_pn &= 0x0000ffffffffffff;\n\n\t\tif (!VALID_PN_CHK(pkt_pn, curr_pn))\n\t\t\treturn _FAIL;\n\n\t\t*(u64*)psecuritypriv->iv_seq[key_id] = cpu_to_le64(pkt_pn);\n\t}\n\n\treturn _SUCCESS;\n}\n\nsint recv_decache(union recv_frame *precv_frame)\n{\n\tstruct sta_info *psta = precv_frame->u.hdr.psta;\n\tstruct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;\n\t_adapter *adapter = psta->padapter;\n\tsint tid = pattrib->priority;\n\tu16 seq_ctrl = ((precv_frame->u.hdr.attrib.seq_num & 0xffff) << 4) |\n\t\t       (precv_frame->u.hdr.attrib.frag_num & 0xf);\n\tu16 *prxseq;\n\n\tif (tid > 15)\n\t\treturn _FAIL;\n\n\tif (pattrib->qos) {\n\t\tif (IS_MCAST(pattrib->ra))\n\t\t\tprxseq = &psta->sta_recvpriv.bmc_tid_rxseq[tid];\n\t\telse\n\t\t\tprxseq = &psta->sta_recvpriv.rxcache.tid_rxseq[tid];\n\t} else {\n\t\tif (IS_MCAST(pattrib->ra)) {\n\t\t\tprxseq = &psta->sta_recvpriv.nonqos_bmc_rxseq;\n\t\t\t#ifdef DBG_RX_SEQ\n\t\t\tRTW_INFO(\"DBG_RX_SEQ \"FUNC_ADPT_FMT\" nonqos bmc seq_num:%d\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), pattrib->seq_num);\n\t\t\t#endif\n\n\t\t} else {\n\t\t\tprxseq = &psta->sta_recvpriv.nonqos_rxseq;\n\t\t\t#ifdef DBG_RX_SEQ\n\t\t\tRTW_INFO(\"DBG_RX_SEQ \"FUNC_ADPT_FMT\" nonqos seq_num:%d\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), pattrib->seq_num);\n\t\t\t#endif\n\t\t}\n\t}\n\n\tif (seq_ctrl == *prxseq) {\n\t\t/* for non-AMPDU case\t*/\n\t\tpsta->sta_stats.duplicate_cnt++;\n\n\t\tif (psta->sta_stats.duplicate_cnt % 100 == 0)\n\t\t\tRTW_INFO(\"%s: tid=%u seq=%d frag=%d\\n\", __func__\n\t\t\t\t, tid, precv_frame->u.hdr.attrib.seq_num\n\t\t\t\t, precv_frame->u.hdr.attrib.frag_num);\n\n\t\t#ifdef DBG_RX_DROP_FRAME\n\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" recv_decache _FAIL for sta=\"MAC_FMT\"\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr));\n\t\t#endif\n\t\treturn _FAIL;\n\t}\n\t*prxseq = seq_ctrl;\n\n\treturn _SUCCESS;\n}\n\nvoid process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta)\n{\n#ifdef CONFIG_AP_MODE\n\tunsigned char pwrbit;\n\tu8 *ptr = precv_frame->u.hdr.rx_data;\n\n\tpwrbit = GetPwrMgt(ptr);\n\n\tif (pwrbit) {\n\t\tif (!(psta->state & WIFI_SLEEP_STATE)) {\n\t\t\t/* psta->state |= WIFI_SLEEP_STATE; */\n\t\t\t/* rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, BIT(psta->cmn.aid)); */\n\n\t\t\tstop_sta_xmit(padapter, psta);\n\t\t\t/* RTW_INFO_DUMP(\"to sleep, sta_dz_bitmap=\", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); */\n\t\t}\n\t} else {\n\t\tif (psta->state & WIFI_SLEEP_STATE) {\n\t\t\t/* psta->state ^= WIFI_SLEEP_STATE; */\n\t\t\t/* rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, BIT(psta->cmn.aid)); */\n\n\t\t\twakeup_sta_to_xmit(padapter, psta);\n\t\t\t/* RTW_INFO_DUMP(\"to wakeup, sta_dz_bitmap=\", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); */\n\t\t}\n\t}\n#endif\n}\n\nvoid process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta)\n{\n#ifdef CONFIG_AP_MODE\n\tstruct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;\n\n#ifdef CONFIG_TDLS\n\tif (!(psta->tdls_sta_state & TDLS_LINKED_STATE)) {\n#endif /* CONFIG_TDLS */\n\n\t\tif (!psta->qos_option)\n\t\t\treturn;\n\n\t\tif (!(psta->qos_info & 0xf))\n\t\t\treturn;\n\n#ifdef CONFIG_TDLS\n\t}\n#endif /* CONFIG_TDLS\t\t */\n\n\tif (psta->state & WIFI_SLEEP_STATE) {\n\t\tu8 wmmps_ac = 0;\n\n\t\tswitch (pattrib->priority) {\n\t\tcase 1:\n\t\tcase 2:\n\t\t\twmmps_ac = psta->uapsd_bk & BIT(1);\n\t\t\tbreak;\n\t\tcase 4:\n\t\tcase 5:\n\t\t\twmmps_ac = psta->uapsd_vi & BIT(1);\n\t\t\tbreak;\n\t\tcase 6:\n\t\tcase 7:\n\t\t\twmmps_ac = psta->uapsd_vo & BIT(1);\n\t\t\tbreak;\n\t\tcase 0:\n\t\tcase 3:\n\t\tdefault:\n\t\t\twmmps_ac = psta->uapsd_be & BIT(1);\n\t\t\tbreak;\n\t\t}\n\n\t\tif (wmmps_ac) {\n\t\t\tif (psta->sleepq_ac_len > 0) {\n\t\t\t\t/* process received triggered frame */\n\t\t\t\txmit_delivery_enabled_frames(padapter, psta);\n\t\t\t} else {\n\t\t\t\t/* issue one qos null frame with More data bit = 0 and the EOSP bit set (=1) */\n\t\t\t\tissue_qos_nulldata(padapter, psta->cmn.mac_addr, (u16)pattrib->priority, 0, 0, 0);\n\t\t\t}\n\t\t}\n\n\t}\n\n\n#endif\n\n}\n\n#ifdef CONFIG_TDLS\nsint OnTDLS(_adapter *adapter, union recv_frame *precv_frame)\n{\n\tstruct rx_pkt_attrib\t*pattrib = &precv_frame->u.hdr.attrib;\n\tsint ret = _SUCCESS;\n\tu8 *paction = get_recvframe_data(precv_frame);\n\tu8 category_field = 1;\n#ifdef CONFIG_WFD\n\tu8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a };\n#endif /* CONFIG_WFD */\n\tstruct tdls_info *ptdlsinfo = &(adapter->tdlsinfo);\n\tu8 *ptr = precv_frame->u.hdr.rx_data;\n\tstruct sta_priv *pstapriv = &(adapter->stapriv);\n\tstruct sta_info *ptdls_sta = NULL;\n\n\t/* point to action field */\n\tpaction += pattrib->hdrlen\n\t\t   + pattrib->iv_len\n\t\t   + SNAP_SIZE\n\t\t   + ETH_TYPE_LEN\n\t\t   + PAYLOAD_TYPE_LEN\n\t\t   + category_field;\n\n\tRTW_INFO(\"[TDLS] Recv %s from \"MAC_FMT\" with SeqNum = %d\\n\", rtw_tdls_action_txt(*paction), MAC_ARG(pattrib->src), GetSequence(get_recvframe_data(precv_frame)));\n\n\tif (hal_chk_wl_func(adapter, WL_FUNC_TDLS) == _FALSE) {\n\t\tRTW_INFO(\"Ignore tdls frame since hal doesn't support tdls\\n\");\n\t\tret = _FAIL;\n\t\treturn ret;\n\t}\n\n\tif (rtw_is_tdls_enabled(adapter) == _FALSE) {\n\t\tRTW_INFO(\"recv tdls frame, \"\n\t\t\t \"but tdls haven't enabled\\n\");\n\t\tret = _FAIL;\n\t\treturn ret;\n\t}\n\n\tptdls_sta = rtw_get_stainfo(pstapriv, get_sa(ptr));\n\tif (ptdls_sta == NULL) {\n\t\tswitch (*paction) {\n\t\tcase TDLS_SETUP_REQUEST:\n\t\tcase TDLS_DISCOVERY_REQUEST:\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tRTW_INFO(\"[TDLS] %s - Direct Link Peer = \"MAC_FMT\" not found for action = %d\\n\", __func__, MAC_ARG(get_sa(ptr)), *paction);\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\tswitch (*paction) {\n\tcase TDLS_SETUP_REQUEST:\n\t\tret = On_TDLS_Setup_Req(adapter, precv_frame, ptdls_sta);\n\t\tbreak;\n\tcase TDLS_SETUP_RESPONSE:\n\t\tret = On_TDLS_Setup_Rsp(adapter, precv_frame, ptdls_sta);\n\t\tbreak;\n\tcase TDLS_SETUP_CONFIRM:\n\t\tret = On_TDLS_Setup_Cfm(adapter, precv_frame, ptdls_sta);\n\t\tbreak;\n\tcase TDLS_TEARDOWN:\n\t\tret = On_TDLS_Teardown(adapter, precv_frame, ptdls_sta);\n\t\tbreak;\n\tcase TDLS_DISCOVERY_REQUEST:\n\t\tret = On_TDLS_Dis_Req(adapter, precv_frame);\n\t\tbreak;\n\tcase TDLS_PEER_TRAFFIC_INDICATION:\n\t\tret = On_TDLS_Peer_Traffic_Indication(adapter, precv_frame, ptdls_sta);\n\t\tbreak;\n\tcase TDLS_PEER_TRAFFIC_RESPONSE:\n\t\tret = On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame, ptdls_sta);\n\t\tbreak;\n#ifdef CONFIG_TDLS_CH_SW\n\tcase TDLS_CHANNEL_SWITCH_REQUEST:\n\t\tret = On_TDLS_Ch_Switch_Req(adapter, precv_frame, ptdls_sta);\n\t\tbreak;\n\tcase TDLS_CHANNEL_SWITCH_RESPONSE:\n\t\tret = On_TDLS_Ch_Switch_Rsp(adapter, precv_frame, ptdls_sta);\n\t\tbreak;\n#endif\n#ifdef CONFIG_WFD\n\t/* First byte of WFA OUI */\n\tcase 0x50:\n\t\tif (_rtw_memcmp(WFA_OUI, paction, 3)) {\n\t\t\t/* Probe request frame */\n\t\t\tif (*(paction + 3) == 0x04) {\n\t\t\t\t/* WFDTDLS: for sigma test, do not setup direct link automatically */\n\t\t\t\tptdlsinfo->dev_discovered = _TRUE;\n\t\t\t\tRTW_INFO(\"recv tunneled probe request frame\\n\");\n\t\t\t\tissue_tunneled_probe_rsp(adapter, precv_frame);\n\t\t\t}\n\t\t\t/* Probe response frame */\n\t\t\tif (*(paction + 3) == 0x05) {\n\t\t\t\t/* WFDTDLS: for sigma test, do not setup direct link automatically */\n\t\t\t\tptdlsinfo->dev_discovered = _TRUE;\n\t\t\t\tRTW_INFO(\"recv tunneled probe response frame\\n\");\n\t\t\t}\n\t\t}\n\t\tbreak;\n#endif /* CONFIG_WFD */\n\tdefault:\n\t\tRTW_INFO(\"receive TDLS frame %d but not support\\n\", *paction);\n\t\tret = _FAIL;\n\t\tbreak;\n\t}\n\nexit:\n\treturn ret;\n\n}\n#endif /* CONFIG_TDLS */\n\nvoid count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta)\n{\n\tint\tsz;\n\tstruct sta_info\t\t*psta = NULL;\n\tstruct stainfo_stats\t*pstats = NULL;\n\tstruct rx_pkt_attrib\t*pattrib = &prframe->u.hdr.attrib;\n\tstruct recv_priv\t\t*precvpriv = &padapter->recvpriv;\n\n\tsz = get_recvframe_len(prframe);\n\tprecvpriv->rx_bytes += sz;\n\n\tpadapter->mlmepriv.LinkDetectInfo.NumRxOkInPeriod++;\n\n\tif ((!MacAddr_isBcst(pattrib->dst)) && (!IS_MCAST(pattrib->dst)))\n\t\tpadapter->mlmepriv.LinkDetectInfo.NumRxUnicastOkInPeriod++;\n\n\tif (sta)\n\t\tpsta = sta;\n\telse\n\t\tpsta = prframe->u.hdr.psta;\n\n\tif (psta) {\n\t\tu8 is_ra_bmc = IS_MCAST(pattrib->ra);\n\n\t\tpstats = &psta->sta_stats;\n\n\t\tpstats->last_rx_time = rtw_get_current_time();\n\t\tpstats->rx_data_pkts++;\n\t\tpstats->rx_bytes += sz;\n\t\tif (is_broadcast_mac_addr(pattrib->ra)) {\n\t\t\tpstats->rx_data_bc_pkts++;\n\t\t\tpstats->rx_bc_bytes += sz;\n\t\t} else if (is_ra_bmc) {\n\t\t\tpstats->rx_data_mc_pkts++;\n\t\t\tpstats->rx_mc_bytes += sz;\n\t\t}\n\n\t\tif (!is_ra_bmc) {\n\t\t\tpstats->rxratecnt[pattrib->data_rate]++;\n\t\t\t/*record rx packets for every tid*/\n\t\t\tpstats->rx_data_qos_pkts[pattrib->priority]++;\n\t\t}\n#ifdef CONFIG_DYNAMIC_SOML\n\t\trtw_dyn_soml_byte_update(padapter, pattrib->data_rate, sz);\n#endif\n#if defined(CONFIG_CHECK_LEAVE_LPS) && defined(CONFIG_LPS_CHK_BY_TP)\n\t\tif (adapter_to_pwrctl(padapter)->lps_chk_by_tp)\n\t\t\ttraffic_check_for_leave_lps_by_tp(padapter, _FALSE, psta);\n#endif /* CONFIG_LPS */\n\n\t}\n\n#ifdef CONFIG_CHECK_LEAVE_LPS\n#ifdef CONFIG_LPS_CHK_BY_TP\n\tif (!adapter_to_pwrctl(padapter)->lps_chk_by_tp)\n#endif\n\t\ttraffic_check_for_leave_lps(padapter, _FALSE, 0);\n#endif /* CONFIG_CHECK_LEAVE_LPS */\n\n}\n\nsint sta2sta_data_frame(\n\t_adapter *adapter,\n\tunion recv_frame *precv_frame,\n\tstruct sta_info **psta\n)\n{\n\tu8 *ptr = precv_frame->u.hdr.rx_data;\n\tsint ret = _SUCCESS;\n\tstruct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;\n\tstruct\tsta_priv\t\t*pstapriv = &adapter->stapriv;\n\tstruct\tmlme_priv\t*pmlmepriv = &adapter->mlmepriv;\n\tu8 *mybssid  = get_bssid(pmlmepriv);\n\tu8 *myhwaddr = adapter_mac_addr(adapter);\n\tu8 *sta_addr = pattrib->ta;\n\tsint bmcast = IS_MCAST(pattrib->dst);\n\n#ifdef CONFIG_TDLS\n\tstruct tdls_info *ptdlsinfo = &adapter->tdlsinfo;\n#ifdef CONFIG_TDLS_CH_SW\n\tstruct tdls_ch_switch *pchsw_info = &ptdlsinfo->chsw_info;\n#endif\n\tstruct sta_info *ptdls_sta = NULL;\n\tu8 *psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE;\n\t/* frame body located after [+2]: ether-type, [+1]: payload type */\n\tu8 *pframe_body = psnap_type + 2 + 1;\n#endif\n\n\n\t/* RTW_INFO(\"[%s] %d, seqnum:%d\\n\", __FUNCTION__, __LINE__, pattrib->seq_num); */\n\n\tif ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ||\n\t    (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {\n\n\t\t/* filter packets that SA is myself or multicast or broadcast */\n\t\tif (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) {\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN))\t&& (!bmcast)) {\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (_rtw_memcmp(pattrib->bssid, \"\\x0\\x0\\x0\\x0\\x0\\x0\", ETH_ALEN) ||\n\t\t    _rtw_memcmp(mybssid, \"\\x0\\x0\\x0\\x0\\x0\\x0\", ETH_ALEN) ||\n\t\t    (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))) {\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t} else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {\n#ifdef CONFIG_TDLS\n\n\t\t/* direct link data transfer */\n\t\tif (ptdlsinfo->link_established == _TRUE) {\n\t\t\t*psta = ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->ta);\n\t\t\tif (ptdls_sta == NULL) {\n\t\t\t\tret = _FAIL;\n\t\t\t\tgoto exit;\n\t\t\t} else if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {\n\t\t\t\t/* filter packets that SA is myself or multicast or broadcast */\n\t\t\t\tif (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) {\n\t\t\t\t\tret = _FAIL;\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t\t/* da should be for me */\n\t\t\t\tif ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast)) {\n\t\t\t\t\tret = _FAIL;\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t\t/* check BSSID */\n\t\t\t\tif (_rtw_memcmp(pattrib->bssid, \"\\x0\\x0\\x0\\x0\\x0\\x0\", ETH_ALEN) ||\n\t\t\t\t    _rtw_memcmp(mybssid, \"\\x0\\x0\\x0\\x0\\x0\\x0\", ETH_ALEN) ||\n\t\t\t\t    (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))) {\n\t\t\t\t\tret = _FAIL;\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\n#ifdef CONFIG_TDLS_CH_SW\n\t\t\t\tif (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) {\n\t\t\t\t\tif (adapter->mlmeextpriv.cur_channel != rtw_get_oper_ch(adapter)) {\n\t\t\t\t\t\tpchsw_info->ch_sw_state |= TDLS_PEER_AT_OFF_STATE;\n\t\t\t\t\t\tif (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))\n\t\t\t\t\t\t\t_cancel_timer_ex(&ptdls_sta->ch_sw_timer);\n\t\t\t\t\t\t/* On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame); */\n\t\t\t\t\t}\n\t\t\t\t}\n#endif\n\n\t\t\t\t/* process UAPSD tdls sta */\n\t\t\t\tprocess_pwrbit_data(adapter, precv_frame, ptdls_sta);\n\n\t\t\t\t/* if NULL-frame, check pwrbit */\n\t\t\t\tif ((get_frame_sub_type(ptr) & WIFI_DATA_NULL) == WIFI_DATA_NULL) {\n\t\t\t\t\t/* NULL-frame with pwrbit=1, buffer_STA should buffer frames for sleep_STA */\n\t\t\t\t\tif (GetPwrMgt(ptr)) {\n\t\t\t\t\t\t/* it would be triggered when we are off channel and receiving NULL DATA */\n\t\t\t\t\t\t/* we can confirm that peer STA is at off channel */\n\t\t\t\t\t\tRTW_INFO(\"TDLS: recv peer null frame with pwr bit 1\\n\");\n\t\t\t\t\t\t/* ptdls_sta->tdls_sta_state|=TDLS_PEER_SLEEP_STATE; */\n\t\t\t\t\t}\n\n\t\t\t\t\t/* TODO: Updated BSSID's seq. */\n\t\t\t\t\t/* RTW_INFO(\"drop Null Data\\n\"); */\n\t\t\t\t\tptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE);\n\t\t\t\t\tret = _FAIL;\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\n\t\t\t\t/* receive some of all TDLS management frames, process it at ON_TDLS */\n\t\t\t\tif (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_TDLS, 2)) {\n\t\t\t\t\tret = OnTDLS(adapter, precv_frame);\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\n\t\t\t\tif ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE)\n\t\t\t\t\tprocess_wmmps_data(adapter, precv_frame, ptdls_sta);\n\n\t\t\t\tptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE);\n\n\t\t\t}\n\t\t} else\n#endif /* CONFIG_TDLS */\n\t\t{\n\t\t\t/* For Station mode, sa and bssid should always be BSSID, and DA is my mac-address */\n\t\t\tif (!_rtw_memcmp(pattrib->bssid, pattrib->src, ETH_ALEN)) {\n\t\t\t\tret = _FAIL;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\n\t} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {\n\t\tif (bmcast) {\n\t\t\t/* For AP mode, if DA == MCAST, then BSSID should be also MCAST */\n\t\t\tif (!IS_MCAST(pattrib->bssid)) {\n\t\t\t\tret = _FAIL;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t} else { /* not mc-frame */\n\t\t\t/* For AP mode, if DA is non-MCAST, then it must be BSSID, and bssid == BSSID */\n\t\t\tif (!_rtw_memcmp(pattrib->bssid, pattrib->dst, ETH_ALEN)) {\n\t\t\t\tret = _FAIL;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\n\t} else if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) {\n\t\t_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);\n\n\t\tsta_addr = mybssid;\n\t} else\n\t\tret  = _FAIL;\n\n#ifdef CONFIG_TDLS\n\tif (ptdls_sta == NULL)\n#endif\n\t\t*psta = rtw_get_stainfo(pstapriv, sta_addr);\n\n\tif (*psta == NULL) {\n#ifdef CONFIG_MP_INCLUDED\n\t\tif (adapter->registrypriv.mp_mode == 1) {\n\t\t\tif (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)\n\t\t\t\tadapter->mppriv.rx_pktloss++;\n\t\t}\n#endif\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\nexit:\n\treturn ret;\n\n}\n\nsint ap2sta_data_frame(\n\t_adapter *adapter,\n\tunion recv_frame *precv_frame,\n\tstruct sta_info **psta)\n{\n\tu8 *ptr = precv_frame->u.hdr.rx_data;\n\tstruct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;\n\tsint ret = _SUCCESS;\n\tstruct\tsta_priv\t\t*pstapriv = &adapter->stapriv;\n\tstruct\tmlme_priv\t*pmlmepriv = &adapter->mlmepriv;\n\tu8 *mybssid  = get_bssid(pmlmepriv);\n\tu8 *myhwaddr = adapter_mac_addr(adapter);\n\tsint bmcast = IS_MCAST(pattrib->dst);\n\n\n\tif ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)\n\t    && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE\n\t\t|| check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE)\n\t   ) {\n\n\t\t/* filter packets that SA is myself or multicast or broadcast */\n\t\tif (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) {\n\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" SA=\"MAC_FMT\", myhwaddr=\"MAC_FMT\"\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(pattrib->src), MAC_ARG(myhwaddr));\n\t\t\t#endif\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* da should be for me */\n\t\tif ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast)) {\n\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" DA=\"MAC_FMT\"\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(pattrib->dst));\n\t\t\t#endif\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\n\t\t/* check BSSID */\n\t\tif (_rtw_memcmp(pattrib->bssid, \"\\x0\\x0\\x0\\x0\\x0\\x0\", ETH_ALEN) ||\n\t\t    _rtw_memcmp(mybssid, \"\\x0\\x0\\x0\\x0\\x0\\x0\", ETH_ALEN) ||\n\t\t    (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))) {\n\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" BSSID=\"MAC_FMT\", mybssid=\"MAC_FMT\"\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(pattrib->bssid), MAC_ARG(mybssid));\n\t\t\t#endif\n#ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL\n\t\t\tif (!bmcast\n\t\t\t\t&& !IS_RADAR_DETECTED(adapter_to_rfctl(adapter))\n\t\t\t) {\n\t\t\t\tRTW_INFO(ADPT_FMT\" -issue_deauth to the nonassociated ap=\" MAC_FMT \" for the reason(7)\\n\", ADPT_ARG(adapter), MAC_ARG(pattrib->bssid));\n\t\t\t\tissue_deauth(adapter, pattrib->bssid, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);\n\t\t\t}\n#endif\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t*psta = rtw_get_stainfo(pstapriv, pattrib->ta);\n\t\tif (*psta == NULL) {\n\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" can't get psta under STATION_MODE ; drop pkt\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter));\n\t\t\t#endif\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/*if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) {\n\t\t}\n\t\t*/\n\n\t\tif (get_frame_sub_type(ptr) & BIT(6)) {\n\t\t\t/* No data, will not indicate to upper layer, temporily count it here */\n\t\t\tcount_rx_stats(adapter, precv_frame, *psta);\n\t\t\tret = RTW_RX_HANDLED;\n\t\t\tgoto exit;\n\t\t}\n\n\t} else if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) &&\n\t\t   (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {\n\t\t_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);\n\n\n\t\t*psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */\n\t\tif (*psta == NULL) {\n\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" can't get psta under WIFI_MP_STATE ; drop pkt\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter));\n\t\t\t#endif\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\n\t} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {\n\t\t/* Special case */\n\t\tret = RTW_RX_HANDLED;\n\t\tgoto exit;\n\t} else {\n\t\tif (_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN) && (!bmcast)) {\n\t\t\t*psta = rtw_get_stainfo(pstapriv, pattrib->ta);\n\t\t\tif (*psta == NULL) {\n\n\t\t\t\t/* for AP multicast issue , modify by yiwei */\n\t\t\t\tstatic systime send_issue_deauth_time = 0;\n\n\t\t\t\t/* RTW_INFO(\"After send deauth , %u ms has elapsed.\\n\", rtw_get_passing_time_ms(send_issue_deauth_time)); */\n\n\t\t\t\tif (rtw_get_passing_time_ms(send_issue_deauth_time) > 10000 || send_issue_deauth_time == 0) {\n\t\t\t\t\tsend_issue_deauth_time = rtw_get_current_time();\n\n\t\t\t\t\tRTW_INFO(\"issue_deauth to the ap=\" MAC_FMT \" for the reason(7)\\n\", MAC_ARG(pattrib->bssid));\n\n\t\t\t\t\tissue_deauth(adapter, pattrib->bssid, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tret = _FAIL;\n\t\t#ifdef DBG_RX_DROP_FRAME\n\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" fw_state:0x%x\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv));\n\t\t#endif\n\t}\n\nexit:\n\n\n\treturn ret;\n\n}\n\nsint sta2ap_data_frame(\n\t_adapter *adapter,\n\tunion recv_frame *precv_frame,\n\tstruct sta_info **psta)\n{\n\tu8 *ptr = precv_frame->u.hdr.rx_data;\n\tstruct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;\n\tstruct\tsta_priv\t\t*pstapriv = &adapter->stapriv;\n\tstruct\tmlme_priv\t*pmlmepriv = &adapter->mlmepriv;\n\tunsigned char *mybssid  = get_bssid(pmlmepriv);\n\tsint ret = _SUCCESS;\n\n\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {\n\t\t/* For AP mode, RA=BSSID, TX=STA(SRC_ADDR), A3=DST_ADDR */\n\t\tif (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN)) {\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t*psta = rtw_get_stainfo(pstapriv, pattrib->ta);\n\t\tif (*psta == NULL) {\n\t\t\tif (!IS_RADAR_DETECTED(adapter_to_rfctl(adapter))) {\n#ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL\n\t\t\t\tRTW_INFO(\"issue_deauth to sta=\" MAC_FMT \" for the reason(7)\\n\", MAC_ARG(pattrib->src));\n\t\t\t\tissue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);\n#endif\n\t\t\t}\n\n\t\t\tret = RTW_RX_HANDLED;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tprocess_pwrbit_data(adapter, precv_frame, *psta);\n\n\t\tif ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE)\n\t\t\tprocess_wmmps_data(adapter, precv_frame, *psta);\n\n\t\tif (get_frame_sub_type(ptr) & BIT(6)) {\n\t\t\t/* No data, will not indicate to upper layer, temporily count it here */\n\t\t\tcount_rx_stats(adapter, precv_frame, *psta);\n\t\t\tret = RTW_RX_HANDLED;\n\t\t\tgoto exit;\n\t\t}\n\t} else if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) &&\n\t\t   (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {\n\t\t/* RTW_INFO(\"%s ,in WIFI_MP_STATE\\n\",__func__); */\n\t\t_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);\n\n\n\t\t*psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */\n\t\tif (*psta == NULL) {\n\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" can't get psta under WIFI_MP_STATE ; drop pkt\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter));\n\t\t\t#endif\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t} else {\n\t\tu8 *myhwaddr = adapter_mac_addr(adapter);\n\t\tif (!_rtw_memcmp(pattrib->ra, myhwaddr, ETH_ALEN)) {\n\t\t\tret = RTW_RX_HANDLED;\n\t\t\tgoto exit;\n\t\t}\n#ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL\n\t\tRTW_INFO(\"issue_deauth to sta=\" MAC_FMT \" for the reason(7)\\n\", MAC_ARG(pattrib->src));\n\t\tissue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);\n#endif\n\t\tret = RTW_RX_HANDLED;\n\t\tgoto exit;\n\t}\n\nexit:\n\n\n\treturn ret;\n\n}\n\nsint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame);\nsint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tstruct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tstruct sta_info *psta = NULL;\n\t/* uint len = precv_frame->u.hdr.len; */\n\n\t/* RTW_INFO(\"+validate_recv_ctrl_frame\\n\"); */\n\n\tif (GetFrameType(pframe) != WIFI_CTRL_TYPE)\n\t\treturn _FAIL;\n\n\t/* receive the frames that ra(a1) is my address */\n\tif (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN))\n\t\treturn _FAIL;\n\n\tpsta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));\n\tif (psta == NULL)\n\t\treturn _FAIL;\n\n\t/* for rx pkt statistics */\n\tpsta->sta_stats.last_rx_time = rtw_get_current_time();\n\tpsta->sta_stats.rx_ctrl_pkts++;\n\n\t/* only handle ps-poll */\n\tif (get_frame_sub_type(pframe) == WIFI_PSPOLL) {\n#ifdef CONFIG_AP_MODE\n\t\tu16 aid;\n\t\tu8 wmmps_ac = 0;\n\n\t\taid = GetAid(pframe);\n\t\tif (psta->cmn.aid != aid)\n\t\t\treturn _FAIL;\n\n\t\tswitch (pattrib->priority) {\n\t\tcase 1:\n\t\tcase 2:\n\t\t\twmmps_ac = psta->uapsd_bk & BIT(0);\n\t\t\tbreak;\n\t\tcase 4:\n\t\tcase 5:\n\t\t\twmmps_ac = psta->uapsd_vi & BIT(0);\n\t\t\tbreak;\n\t\tcase 6:\n\t\tcase 7:\n\t\t\twmmps_ac = psta->uapsd_vo & BIT(0);\n\t\t\tbreak;\n\t\tcase 0:\n\t\tcase 3:\n\t\tdefault:\n\t\t\twmmps_ac = psta->uapsd_be & BIT(0);\n\t\t\tbreak;\n\t\t}\n\n\t\tif (wmmps_ac)\n\t\t\treturn _FAIL;\n\n\t\tif (psta->state & WIFI_STA_ALIVE_CHK_STATE) {\n\t\t\tRTW_INFO(\"%s alive check-rx ps-poll\\n\", __func__);\n\t\t\tpsta->expire_to = pstapriv->expire_to;\n\t\t\tpsta->state ^= WIFI_STA_ALIVE_CHK_STATE;\n\t\t}\n\n\t\tif ((psta->state & WIFI_SLEEP_STATE) && (rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid))) {\n\t\t\t_irqL irqL;\n\t\t\t_list\t*xmitframe_plist, *xmitframe_phead;\n\t\t\tstruct xmit_frame *pxmitframe = NULL;\n\t\t\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\n\t\t\t/* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */\n\t\t\t_enter_critical_bh(&pxmitpriv->lock, &irqL);\n\n\t\t\txmitframe_phead = get_list_head(&psta->sleep_q);\n\t\t\txmitframe_plist = get_next(xmitframe_phead);\n\n\t\t\tif ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {\n\t\t\t\tpxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);\n\n\t\t\t\txmitframe_plist = get_next(xmitframe_plist);\n\n\t\t\t\trtw_list_delete(&pxmitframe->list);\n\n\t\t\t\tpsta->sleepq_len--;\n\n\t\t\t\tif (psta->sleepq_len > 0)\n\t\t\t\t\tpxmitframe->attrib.mdata = 1;\n\t\t\t\telse\n\t\t\t\t\tpxmitframe->attrib.mdata = 0;\n\n\t\t\t\tpxmitframe->attrib.triggered = 1;\n\n\t\t\t\t/* RTW_INFO(\"handling ps-poll, q_len=%d\\n\", psta->sleepq_len); */\n\t\t\t\t/* RTW_INFO_DUMP(\"handling, tim=\", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */\n\n#if 0\n\t\t\t\t_exit_critical_bh(&psta->sleep_q.lock, &irqL);\n\t\t\t\tif (rtw_hal_xmit(padapter, pxmitframe) == _TRUE)\n\t\t\t\t\trtw_os_xmit_complete(padapter, pxmitframe);\n\t\t\t\t_enter_critical_bh(&psta->sleep_q.lock, &irqL);\n#endif\n\t\t\t\trtw_hal_xmitframe_enqueue(padapter, pxmitframe);\n\n\t\t\t\tif (psta->sleepq_len == 0) {\n\t\t\t\t\trtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);\n\n\t\t\t\t\t/* RTW_INFO(\"after handling ps-poll\\n\"); */\n\t\t\t\t\t/* RTW_INFO_DUMP(\"after handling, tim=\", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */\n\n\t\t\t\t\t/* upate BCN for TIM IE */\n\t\t\t\t\t/* update_BCNTIM(padapter);\t\t */\n\t\t\t\t\tupdate_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0);\n\t\t\t\t}\n\n\t\t\t\t/* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */\n\t\t\t\t_exit_critical_bh(&pxmitpriv->lock, &irqL);\n\n\t\t\t} else {\n\t\t\t\t/* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */\n\t\t\t\t_exit_critical_bh(&pxmitpriv->lock, &irqL);\n\n\t\t\t\t/* RTW_INFO(\"no buffered packets to xmit\\n\"); */\n\t\t\t\tif (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) {\n\t\t\t\t\tif (psta->sleepq_len == 0) {\n\t\t\t\t\t\tRTW_INFO(\"no buffered packets to xmit\\n\");\n\n\t\t\t\t\t\t/* issue nulldata with More data bit = 0 to indicate we have no buffered packets */\n\t\t\t\t\t\tissue_nulldata(padapter, psta->cmn.mac_addr, 0, 0, 0);\n\t\t\t\t\t} else {\n\t\t\t\t\t\tRTW_INFO(\"error!psta->sleepq_len=%d\\n\", psta->sleepq_len);\n\t\t\t\t\t\tpsta->sleepq_len = 0;\n\t\t\t\t\t}\n\n\t\t\t\t\trtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);\n\n\t\t\t\t\t/* upate BCN for TIM IE */\n\t\t\t\t\t/* update_BCNTIM(padapter); */\n\t\t\t\t\tupdate_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n#endif /* CONFIG_AP_MODE */\n\t} else if (get_frame_sub_type(pframe) == WIFI_NDPA) {\n#ifdef CONFIG_BEAMFORMING\n\t\trtw_beamforming_get_ndpa_frame(padapter, precv_frame);\n#endif/*CONFIG_BEAMFORMING*/\n\t} else if (get_frame_sub_type(pframe) == WIFI_BAR) {\n\t\trtw_process_bar_frame(padapter, precv_frame);\n\t}\n\n\treturn _FAIL;\n\n}\n\n#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)\nstatic sint validate_mgmt_protect(_adapter *adapter, union recv_frame *precv_frame)\n{\n#define DBG_VALIDATE_MGMT_PROTECT 0\n#define DBG_VALIDATE_MGMT_DEC 0\n\n\tstruct security_priv *sec = &adapter->securitypriv;\n\tstruct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;\n\tstruct sta_info\t*psta = precv_frame->u.hdr.psta;\n\tu8 *ptr;\n\tu8 type;\n\tu8 subtype;\n\tu8 is_bmc;\n\tu8 category = 0xFF;\n\n#ifdef CONFIG_IEEE80211W\n\tconst u8 *igtk;\n\tu16 igtk_id;\n\tu64* ipn;\n#endif\n\n\tu8 *mgmt_DATA;\n\tu32 data_len = 0;\n\n\tsint ret;\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(adapter)) {\n\t\tif (!adapter->mesh_info.mesh_auth_id)\n\t\t\treturn pattrib->privacy ? _FAIL : _SUCCESS;\n\t} else\n#endif\n\tif (SEC_IS_BIP_KEY_INSTALLED(sec) == _FALSE)\n\t\treturn _SUCCESS;\n\n\tptr = precv_frame->u.hdr.rx_data;\n\ttype = GetFrameType(ptr);\n\tsubtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */\n\tis_bmc = IS_MCAST(GetAddr1Ptr(ptr));\n\n#if DBG_VALIDATE_MGMT_PROTECT\n\tif (subtype == WIFI_DEAUTH) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" bmc:%u, deauth, privacy:%u, encrypt:%u, bdecrypted:%u\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter)\n\t\t\t, is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);\n\t} else if (subtype == WIFI_DISASSOC) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" bmc:%u, disassoc, privacy:%u, encrypt:%u, bdecrypted:%u\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter)\n\t\t\t, is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);\n\t} if (subtype == WIFI_ACTION) {\n\t\tif (pattrib->privacy) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" bmc:%u, action(?), privacy:%u, encrypt:%u, bdecrypted:%u\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter)\n\t\t\t\t, is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);\n\t\t} else {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" bmc:%u, action(%u), privacy:%u, encrypt:%u, bdecrypted:%u\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), is_bmc\n\t\t\t\t, *(ptr + sizeof(struct rtw_ieee80211_hdr_3addr))\n\t\t\t\t, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);\n\t\t}\n\t}\n#endif\n\n\tif (!pattrib->privacy) {\n\t\tif (!psta || !(psta->flags & WLAN_STA_MFP)) {\n\t\t\t/* peer is not MFP capable, no need to check */\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (subtype == WIFI_ACTION)\n\t\t\tcategory = *(ptr + sizeof(struct rtw_ieee80211_hdr_3addr));\n\n\t\tif (is_bmc) {\n\t\t\t/* broadcast cases */\n\t\t\tif (subtype == WIFI_ACTION) {\n\t\t\t\tif (CATEGORY_IS_GROUP_PRIVACY(category)) {\n\t\t\t\t\t/* drop broadcast group privacy action frame without encryption */\n\t\t\t\t\t#if DBG_VALIDATE_MGMT_PROTECT\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" broadcast gp action(%u) w/o encrypt\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(adapter), category);\n\t\t\t\t\t#endif\n\t\t\t\t\tgoto fail;\n\t\t\t\t}\n\t\t\t\tif (CATEGORY_IS_ROBUST(category)) {\n\t\t\t\t\t/* broadcast robust action frame need BIP check */\n\t\t\t\t\tgoto bip_verify;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) {\n\t\t\t\t/* broadcast deauth or disassoc frame need BIP check */\n\t\t\t\tgoto bip_verify;\n\t\t\t}\n\t\t\tgoto exit;\n\n\t\t} else {\n\t\t\t/* unicast cases */\n\t\t\t#ifdef CONFIG_IEEE80211W\n\t\t\tif (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) {\n\t\t\t\tif (!MLME_IS_MESH(adapter)) {\n\t\t\t\t\tunsigned short reason = le16_to_cpu(*(unsigned short *)(ptr + WLAN_HDR_A3_LEN));\n\n\t\t\t\t\t#if DBG_VALIDATE_MGMT_PROTECT\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" unicast %s, reason=%d w/o encrypt\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(adapter), subtype == WIFI_DEAUTH ? \"deauth\" : \"disassoc\", reason);\n\t\t\t\t\t#endif\n\t\t\t\t\tif (reason == 6 || reason == 7) {\n\t\t\t\t\t\t/* issue sa query request */\n\t\t\t\t\t\tissue_action_SA_Query(adapter, psta->cmn.mac_addr, 0, 0, IEEE80211W_RIGHT_KEY);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tgoto fail;\n\t\t\t}\n\t\t\t#endif\n\n\t\t\tif (subtype == WIFI_ACTION && CATEGORY_IS_ROBUST(category)) {\n\t\t\t\tif (psta->bpairwise_key_installed == _TRUE) {\n\t\t\t\t\t#if DBG_VALIDATE_MGMT_PROTECT\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" unicast robust action(%d) w/o encrypt\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(adapter), category);\n\t\t\t\t\t#endif\n\t\t\t\t\tgoto fail;\n\t\t\t\t}\n\t\t\t}\n\t\t\tgoto exit;\n\t\t}\n\nbip_verify:\n#ifdef CONFIG_IEEE80211W\n\t\t#ifdef CONFIG_RTW_MESH\n\t\tif (MLME_IS_MESH(adapter)) {\n\t\t\tif (psta->igtk_bmp) {\n\t\t\t\tigtk = psta->igtk.skey;\n\t\t\t\tigtk_id = psta->igtk_id;\n\t\t\t\tipn = &psta->igtk_pn.val;\n\t\t\t} else {\n\t\t\t\t/* mesh MFP without IGTK */\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t} else\n\t\t#endif\n\t\t{\n\t\t\tigtk = sec->dot11wBIPKey[sec->dot11wBIPKeyid].skey;\n\t\t\tigtk_id = sec->dot11wBIPKeyid;\n\t\t\tipn = &sec->dot11wBIPrxpn.val;\n\t\t}\n\n\t\t/* verify BIP MME IE */\n\t\tret = rtw_BIP_verify(adapter\n\t\t\t, get_recvframe_data(precv_frame)\n\t\t\t, get_recvframe_len(precv_frame)\n\t\t\t, igtk, igtk_id, ipn);\n\t\tif (ret == _FAIL) {\n\t\t\t/* RTW_INFO(\"802.11w BIP verify fail\\n\"); */\n\t\t\tgoto fail;\n\n\t\t} else if (ret == RTW_RX_HANDLED) {\n\t\t\t#if DBG_VALIDATE_MGMT_PROTECT\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" none protected packet\\n\", FUNC_ADPT_ARG(adapter));\n\t\t\t#endif\n\t\t\tgoto fail;\n\t\t}\n#endif /* CONFIG_IEEE80211W */\n\t\tgoto exit;\n\t}\n\n\t/* cases to decrypt mgmt frame */\n\tpattrib->bdecrypted = 0;\n\tpattrib->encrypt = _AES_;\n\tpattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\t/* set iv and icv length */\n\tSET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt);\n\t_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);\n\n\t/* actual management data frame body */\n\tdata_len = pattrib->pkt_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;\n\tmgmt_DATA = rtw_zmalloc(data_len);\n\tif (mgmt_DATA == NULL) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" mgmt allocate fail  !!!!!!!!!\\n\", FUNC_ADPT_ARG(adapter));\n\t\tgoto fail;\n\t}\n\n#if DBG_VALIDATE_MGMT_DEC\n\t/* dump the packet content before decrypt */\n\t{\n\t\tint pp;\n\n\t\tprintk(\"pattrib->pktlen = %d =>\", pattrib->pkt_len);\n\t\tfor (pp = 0; pp < pattrib->pkt_len; pp++)\n\t\tprintk(\" %02x \", ptr[pp]);\n\t\tprintk(\"\\n\");\n\t}\n#endif\n\n\tprecv_frame = decryptor(adapter, precv_frame);\n\t/* save actual management data frame body */\n\t_rtw_memcpy(mgmt_DATA, ptr + pattrib->hdrlen + pattrib->iv_len, data_len);\n\t/* overwrite the iv field */\n\t_rtw_memcpy(ptr + pattrib->hdrlen, mgmt_DATA, data_len);\n\t/* remove the iv and icv length */\n\tpattrib->pkt_len = pattrib->pkt_len - pattrib->iv_len - pattrib->icv_len;\n\trtw_mfree(mgmt_DATA, data_len);\n\n#if DBG_VALIDATE_MGMT_DEC\n\t/* print packet content after decryption */\n\t{\n\t\tint pp;\n\n\t\tprintk(\"after decryption pattrib->pktlen = %d @@=>\", pattrib->pkt_len);\n\t\tfor (pp = 0; pp < pattrib->pkt_len; pp++)\n\t\tprintk(\" %02x \", ptr[pp]);\n\t\tprintk(\"\\n\");\n\t}\n#endif\n\n\tif (!precv_frame) {\n\t\t#if DBG_VALIDATE_MGMT_PROTECT\n\t\tRTW_INFO(FUNC_ADPT_FMT\" mgmt descrypt fail  !!!!!!!!!\\n\", FUNC_ADPT_ARG(adapter));\n\t\t#endif\n\t\tgoto fail;\n\t}\n\nexit:\n\treturn _SUCCESS;\n\nfail:\n\treturn _FAIL;\n\n}\n#endif /* defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) */\n\nunion recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame);\n\nsint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame)\n{\n\tstruct sta_info *psta = precv_frame->u.hdr.psta\n\t\t= rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(precv_frame->u.hdr.rx_data));\n\n#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)\n\tif (validate_mgmt_protect(padapter, precv_frame) == _FAIL) {\n\t\tDBG_COUNTER(padapter->rx_logs.core_rx_pre_mgmt_err_80211w);\n\t\tgoto exit;\n\t}\n#endif\n\n\tprecv_frame = recvframe_chk_defrag(padapter, precv_frame);\n\tif (precv_frame == NULL)\n\t\treturn _SUCCESS;\n\n\t/* for rx pkt statistics */\n\tif (psta) {\n\t\tpsta->sta_stats.last_rx_time = rtw_get_current_time();\n\t\tpsta->sta_stats.rx_mgnt_pkts++;\n\t\tif (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_BEACON)\n\t\t\tpsta->sta_stats.rx_beacon_pkts++;\n\t\telse if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBEREQ)\n\t\t\tpsta->sta_stats.rx_probereq_pkts++;\n\t\telse if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBERSP) {\n\t\t\tif (_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(precv_frame->u.hdr.rx_data), ETH_ALEN) == _TRUE)\n\t\t\t\tpsta->sta_stats.rx_probersp_pkts++;\n\t\t\telse if (is_broadcast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data))\n\t\t\t\t|| is_multicast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data)))\n\t\t\t\tpsta->sta_stats.rx_probersp_bm_pkts++;\n\t\t\telse\n\t\t\t\tpsta->sta_stats.rx_probersp_uo_pkts++;\n\t\t}\n\t}\n\n\tmgt_dispatcher(padapter, precv_frame);\n\n#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)\nexit:\n#endif\n\treturn _SUCCESS;\n\n}\n\nsint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame)\n{\n\tu8 bretry, a4_shift;\n\tstruct sta_info *psta = NULL;\n\tu8 *ptr = precv_frame->u.hdr.rx_data;\n\tstruct rx_pkt_attrib\t*pattrib = &precv_frame->u.hdr.attrib;\n\tstruct security_priv\t*psecuritypriv = &adapter->securitypriv;\n\tsint ret = _SUCCESS;\n\n\tbretry = GetRetry(ptr);\n\ta4_shift = (pattrib->to_fr_ds == 3) ? ETH_ALEN : 0;\n\n\t/* some address fields are different when using AMSDU */\n\tif (pattrib->qos)\n\t\tpattrib->amsdu = GetAMsdu(ptr + WLAN_HDR_A3_LEN + a4_shift);\n\telse\n\t\tpattrib->amsdu = 0;\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(adapter)) {\n\t\tret = rtw_mesh_rx_data_validate_hdr(adapter, precv_frame, &psta);\n\t\tgoto pre_validate_status_chk;\n\t}\n#endif\n\n\tswitch (pattrib->to_fr_ds) {\n\tcase 0:\n\t\t_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);\n\t\tret = sta2sta_data_frame(adapter, precv_frame, &psta);\n\t\tbreak;\n\n\tcase 1:\n\t\t_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->src, GetAddr3Ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->bssid, get_addr2_ptr(ptr), ETH_ALEN);\n\t\tret = ap2sta_data_frame(adapter, precv_frame, &psta);\n\t\tbreak;\n\n\tcase 2:\n\t\t_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->dst, GetAddr3Ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->bssid, GetAddr1Ptr(ptr), ETH_ALEN);\n\t\tret = sta2ap_data_frame(adapter, precv_frame, &psta);\n\t\tbreak;\n\n\tcase 3:\n\tdefault:\n\t\t/* WDS is not supported */\n\t\tret = _FAIL;\n\t\tbreak;\n\t}\n\n#ifdef CONFIG_RTW_MESH\npre_validate_status_chk:\n#endif\n\tif (ret == _FAIL) {\n\t\t#ifdef DBG_RX_DROP_FRAME\n\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" case:%d, res:%d, ra=\"MAC_FMT\", ta=\"MAC_FMT\"\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), pattrib->to_fr_ds, ret, MAC_ARG(GetAddr1Ptr(ptr)), MAC_ARG(get_addr2_ptr(ptr)));\n\t\t#endif\n\t\tgoto exit;\n\t} else if (ret == RTW_RX_HANDLED)\n\t\tgoto exit;\n\n\n\tif (psta == NULL) {\n\t\t#ifdef DBG_RX_DROP_FRAME\n\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" psta == NULL, ra=\"MAC_FMT\", ta=\"MAC_FMT\"\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(GetAddr1Ptr(ptr)), MAC_ARG(get_addr2_ptr(ptr)));\n\t\t#endif\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tprecv_frame->u.hdr.psta = psta;\n\tprecv_frame->u.hdr.preorder_ctrl = NULL;\n\tpattrib->ack_policy = 0;\n\n\t/* parsing QC field */\n\tif (pattrib->qos == 1) {\n\t\tpattrib->priority = GetPriority((ptr + WLAN_HDR_A3_LEN + a4_shift)); /* point to Qos field*/\n\t\tpattrib->ack_policy = GetAckpolicy((ptr + WLAN_HDR_A3_LEN + a4_shift));\n\t\tpattrib->hdrlen = WLAN_HDR_A3_QOS_LEN + a4_shift;\n\t\tif (pattrib->priority != 0 && pattrib->priority != 3)\n\t\t\tadapter->recvpriv.is_any_non_be_pkts = _TRUE;\n\t\telse\n\t\t\tadapter->recvpriv.is_any_non_be_pkts = _FALSE;\n\t} else {\n\t\tpattrib->priority = 0;\n\t\tpattrib->hdrlen = WLAN_HDR_A3_LEN + a4_shift;\n\t}\n\n\tif (pattrib->order) /* HT-CTRL 11n */\n\t\tpattrib->hdrlen += 4;\n\n\t/* decache, drop duplicate recv packets */\n\tret = recv_decache(precv_frame);\n\tif (ret  == _FAIL)\n\t\tgoto exit;\n\n\tif (!IS_MCAST(pattrib->ra)) {\n\n\t\tif (pattrib->qos)\n\t\t\tprecv_frame->u.hdr.preorder_ctrl = &psta->recvreorder_ctrl[pattrib->priority];\n\n\t\tif (recv_ucast_pn_decache(precv_frame) == _FAIL) {\n\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" recv_ucast_pn_decache return _FAIL for sta=\"MAC_FMT\"\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr));\n\t\t\t#endif\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\t} else {\n\t\tif (recv_bcast_pn_decache(precv_frame) == _FAIL) {\n\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" recv_bcast_pn_decache return _FAIL for sta=\"MAC_FMT\"\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr));\n\t\t\t#endif\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\tif (pattrib->privacy) {\n#ifdef CONFIG_TDLS\n\t\tif ((psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta->dot118021XPrivacy == _AES_))\n\t\t\tpattrib->encrypt = psta->dot118021XPrivacy;\n\t\telse\n#endif /* CONFIG_TDLS */\n\t\t\tGET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, IS_MCAST(pattrib->ra));\n\n\n\t\tSET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt);\n\t} else {\n\t\tpattrib->encrypt = 0;\n\t\tpattrib->iv_len = pattrib->icv_len = 0;\n\t}\n\n#ifdef CONFIG_RTW_MESH\n\tif (!pattrib->amsdu\n\t\t&& pattrib->mesh_ctrl_present\n\t\t&& (!pattrib->encrypt || pattrib->bdecrypted))\n\t\tret = rtw_mesh_rx_validate_mctrl_non_amsdu(adapter, precv_frame);\n#endif\n\nexit:\n\treturn ret;\n}\n\nstatic inline void dump_rx_packet(u8 *ptr)\n{\n\tint i;\n\n\tRTW_INFO(\"#############################\\n\");\n\tfor (i = 0; i < 64; i = i + 8)\n\t\tRTW_INFO(\"%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\\n\", *(ptr + i),\n\t\t\t*(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7));\n\tRTW_INFO(\"#############################\\n\");\n}\n\nsint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame);\nsint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame)\n{\n\t/* shall check frame subtype, to / from ds, da, bssid */\n\n\t/* then call check if rx seq/frag. duplicated. */\n\n\tu8 type;\n\tu8 subtype;\n\tsint retval = _SUCCESS;\n\n\tstruct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;\n\tstruct recv_priv  *precvpriv = &adapter->recvpriv;\n\n\tu8 *ptr = precv_frame->u.hdr.rx_data;\n\tu8  ver = (unsigned char)(*ptr) & 0x3 ;\n#ifdef CONFIG_FIND_BEST_CHANNEL\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n#endif\n\n#ifdef CONFIG_TDLS\n\tstruct tdls_info *ptdlsinfo = &adapter->tdlsinfo;\n#endif /* CONFIG_TDLS */\n#ifdef CONFIG_WAPI_SUPPORT\n\tPRT_WAPI_T\tpWapiInfo = &adapter->wapiInfo;\n\tstruct recv_frame_hdr *phdr = &precv_frame->u.hdr;\n\tu8 wai_pkt = 0;\n\tu16 sc;\n\tu8\texternal_len = 0;\n#endif\n\n\n#ifdef CONFIG_FIND_BEST_CHANNEL\n\tif (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {\n\t\tint ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, rtw_get_oper_ch(adapter));\n\t\tif (ch_set_idx >= 0)\n\t\t\trfctl->channel_set[ch_set_idx].rx_count++;\n\t}\n#endif\n\n#ifdef CONFIG_TDLS\n\tif (ptdlsinfo->ch_sensing == 1 && ptdlsinfo->cur_channel != 0)\n\t\tptdlsinfo->collect_pkt_num[ptdlsinfo->cur_channel - 1]++;\n#endif /* CONFIG_TDLS */\n\n#ifdef RTK_DMP_PLATFORM\n\tif (0) {\n\t\tRTW_INFO(\"++\\n\");\n\t\t{\n\t\t\tint i;\n\t\t\tfor (i = 0; i < 64; i = i + 8)\n\t\t\t\tRTW_INFO(\"%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\", *(ptr + i),\n\t\t\t\t\t*(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7));\n\n\t\t}\n\t\tRTW_INFO(\"--\\n\");\n\t}\n#endif /* RTK_DMP_PLATFORM */\n\n\t/* add version chk */\n\tif (ver != 0) {\n\t\tretval = _FAIL;\n\t\tDBG_COUNTER(adapter->rx_logs.core_rx_pre_ver_err);\n\t\tgoto exit;\n\t}\n\n\ttype =  GetFrameType(ptr);\n\tsubtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */\n\n\tpattrib->to_fr_ds = get_tofr_ds(ptr);\n\n\tpattrib->frag_num = GetFragNum(ptr);\n\tpattrib->seq_num = GetSequence(ptr);\n\n\tpattrib->pw_save = GetPwrMgt(ptr);\n\tpattrib->mfrag = GetMFrag(ptr);\n\tpattrib->mdata = GetMData(ptr);\n\tpattrib->privacy = GetPrivacy(ptr);\n\tpattrib->order = GetOrder(ptr);\n#ifdef CONFIG_WAPI_SUPPORT\n\tsc = (pattrib->seq_num << 4) | pattrib->frag_num;\n#endif\n\n#if 1 /* Dump rx packets */\n\t{\n\t\tu8 bDumpRxPkt = 0;\n\n\t\trtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt));\n\t\tif (bDumpRxPkt == 1) /* dump all rx packets */\n\t\t\tdump_rx_packet(ptr);\n\t\telse if ((bDumpRxPkt == 2) && (type == WIFI_MGT_TYPE))\n\t\t\tdump_rx_packet(ptr);\n\t\telse if ((bDumpRxPkt == 3) && (type == WIFI_DATA_TYPE))\n\t\t\tdump_rx_packet(ptr);\n\t}\n#endif\n\tswitch (type) {\n\tcase WIFI_MGT_TYPE: /* mgnt */\n\t\tDBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt);\n\t\tretval = validate_recv_mgnt_frame(adapter, precv_frame);\n\t\tif (retval == _FAIL) {\n\t\t\tDBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt_err);\n\t\t}\n\t\tretval = _FAIL; /* only data frame return _SUCCESS */\n\t\tbreak;\n\tcase WIFI_CTRL_TYPE: /* ctrl */\n\t\tDBG_COUNTER(adapter->rx_logs.core_rx_pre_ctrl);\n\t\tretval = validate_recv_ctrl_frame(adapter, precv_frame);\n\t\tif (retval == _FAIL) {\n\t\t\tDBG_COUNTER(adapter->rx_logs.core_rx_pre_ctrl_err);\n\t\t}\n\t\tretval = _FAIL; /* only data frame return _SUCCESS */\n\t\tbreak;\n\tcase WIFI_DATA_TYPE: /* data */\n\t\tDBG_COUNTER(adapter->rx_logs.core_rx_pre_data);\n#ifdef CONFIG_WAPI_SUPPORT\n\t\tif (pattrib->qos)\n\t\t\texternal_len = 2;\n\t\telse\n\t\t\texternal_len = 0;\n\n\t\twai_pkt = rtw_wapi_is_wai_packet(adapter, ptr);\n\n\t\tphdr->bIsWaiPacket = wai_pkt;\n\n\t\tif (wai_pkt != 0) {\n\t\t\tif (sc != adapter->wapiInfo.wapiSeqnumAndFragNum)\n\t\t\t\tadapter->wapiInfo.wapiSeqnumAndFragNum = sc;\n\t\t\telse {\n\t\t\t\tretval = _FAIL;\n\t\t\t\tDBG_COUNTER(adapter->rx_logs.core_rx_pre_data_wapi_seq_err);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} else {\n\n\t\t\tif (rtw_wapi_drop_for_key_absent(adapter, get_addr2_ptr(ptr))) {\n\t\t\t\tretval = _FAIL;\n\t\t\t\tWAPI_TRACE(WAPI_RX, \"drop for key absent for rx\\n\");\n\t\t\t\tDBG_COUNTER(adapter->rx_logs.core_rx_pre_data_wapi_key_err);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n#endif\n\n\t\tpattrib->qos = (subtype & BIT(7)) ? 1 : 0;\n\t\tretval = validate_recv_data_frame(adapter, precv_frame);\n\t\tif (retval == _FAIL) {\n\t\t\tprecvpriv->dbg_rx_drop_count++;\n\t\t\tDBG_COUNTER(adapter->rx_logs.core_rx_pre_data_err);\n\t\t} else if (retval == _SUCCESS) {\n\t\t\t#ifdef DBG_RX_DUMP_EAP\n\t\t\tif (!pattrib->encrypt || pattrib->bdecrypted) {\n\t\t\t\tu8 bDumpRxPkt;\n\t\t\t\tu16 eth_type;\n\n\t\t\t\t/* dump eapol */\n\t\t\t\trtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt));\n\t\t\t\t/* get ether_type */\n\t\t\t\t_rtw_memcpy(&eth_type, ptr + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + LLC_HEADER_SIZE, 2);\n\t\t\t\teth_type = ntohs((unsigned short) eth_type);\n\t\t\t\tif ((bDumpRxPkt == 4) && (eth_type == 0x888e))\n\t\t\t\t\tdump_rx_packet(ptr);\n\t\t\t}\n\t\t\t#endif\n\t\t} else\n\t\t\tDBG_COUNTER(adapter->rx_logs.core_rx_pre_data_handled);\n\t\tbreak;\n\tdefault:\n\t\tDBG_COUNTER(adapter->rx_logs.core_rx_pre_unknown);\n\t\t#ifdef DBG_RX_DROP_FRAME\n\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" fail! type=0x%x\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), type);\n\t\t#endif\n\t\tretval = _FAIL;\n\t\tbreak;\n\t}\n\nexit:\n\n\n\treturn retval;\n}\n\n\n/* remove the wlanhdr and add the eth_hdr */\nsint wlanhdr_to_ethhdr(union recv_frame *precvframe)\n{\n\tsint\trmv_len;\n\tu16\teth_type, len;\n\tu8\tbsnaphdr;\n\tu8\t*psnap_type;\n\tstruct ieee80211_snap_hdr\t*psnap;\n\n\tsint ret = _SUCCESS;\n\t_adapter\t\t\t*adapter = precvframe->u.hdr.adapter;\n\tstruct mlme_priv\t*pmlmepriv = &adapter->mlmepriv;\n\n\tu8\t*ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */\n\tstruct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;\n\n\n\tif (pattrib->encrypt)\n\t\trecvframe_pull_tail(precvframe, pattrib->icv_len);\n\n\tpsnap = (struct ieee80211_snap_hdr *)(ptr + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib));\n\tpsnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + SNAP_SIZE;\n\t/* convert hdr + possible LLC headers into Ethernet header */\n\t/* eth_type = (psnap_type[0] << 8) | psnap_type[1]; */\n\tif ((_rtw_memcmp(psnap, rtw_rfc1042_header, SNAP_SIZE) &&\n\t     (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_IPX, 2) == _FALSE) &&\n\t     (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_AARP, 2) == _FALSE)) ||\n\t    /* eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || */\n\t    _rtw_memcmp(psnap, rtw_bridge_tunnel_header, SNAP_SIZE)) {\n\t\t/* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */\n\t\tbsnaphdr = _TRUE;\n\t} else {\n\t\t/* Leave Ethernet header part of hdr and full payload */\n\t\tbsnaphdr = _FALSE;\n\t}\n\n\trmv_len = pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + (bsnaphdr ? SNAP_SIZE : 0);\n\tlen = precvframe->u.hdr.len - rmv_len;\n\n\n\t_rtw_memcpy(&eth_type, ptr + rmv_len, 2);\n\teth_type = ntohs((unsigned short)eth_type); /* pattrib->ether_type */\n\tpattrib->eth_type = eth_type;\n\n\n\tif ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)) {\n\t\tptr += rmv_len ;\n\t\t*ptr = 0x87;\n\t\t*(ptr + 1) = 0x12;\n\n\t\teth_type = 0x8712;\n\t\t/* append rx status for mp test packets */\n\t\tptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + 2) - 24);\n\t\tif (!ptr) {\n\t\t\tret = _FAIL;\n\t\t\tgoto exiting;\n\t\t}\n\t\t_rtw_memcpy(ptr, get_rxmem(precvframe), 24);\n\t\tptr += 24;\n\t} else {\n\t\tptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + (bsnaphdr ? 2 : 0)));\n\t\tif (!ptr) {\n\t\t\tret = _FAIL;\n\t\t\tgoto exiting;\n\t\t}\n\t}\n\n\tif (ptr) {\n\t\t_rtw_memcpy(ptr, pattrib->dst, ETH_ALEN);\n\t\t_rtw_memcpy(ptr + ETH_ALEN, pattrib->src, ETH_ALEN);\n\n\t\tif (!bsnaphdr) {\n\t\t\tlen = htons(len);\n\t\t\t_rtw_memcpy(ptr + 12, &len, 2);\n\t\t}\n\n\t\trtw_rframe_set_os_pkt(precvframe);\n\t}\n\nexiting:\n\treturn ret;\n\n}\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n#ifndef CONFIG_SDIO_RX_COPY\n#ifdef PLATFORM_LINUX\nstatic void recvframe_expand_pkt(\n\tPADAPTER padapter,\n\tunion recv_frame *prframe)\n{\n\tstruct recv_frame_hdr *pfhdr;\n\t_pkt *ppkt;\n\tu8 shift_sz;\n\tu32 alloc_sz;\n\tu8 *ptr;\n\n\n\tpfhdr = &prframe->u.hdr;\n\n\t/*\t6 is for IP header 8 bytes alignment in QoS packet case. */\n\tif (pfhdr->attrib.qos)\n\t\tshift_sz = 6;\n\telse\n\t\tshift_sz = 0;\n\n\t/* for first fragment packet, need to allocate */\n\t/* (1536 + RXDESC_SIZE + drvinfo_sz) to reassemble packet */\n\t/*\t8 is for skb->data 8 bytes alignment.\n\t*\talloc_sz = _RND(1536 + RXDESC_SIZE + pfhdr->attrib.drvinfosize + shift_sz + 8, 128); */\n\talloc_sz = 1664; /* round (1536 + 24 + 32 + shift_sz + 8) to 128 bytes alignment */\n\n\t/* 3 1. alloc new skb */\n\t/* prepare extra space for 4 bytes alignment */\n\tppkt = rtw_skb_alloc(alloc_sz);\n\n\tif (!ppkt)\n\t\treturn; /* no way to expand */\n\n\t/* 3 2. Prepare new skb to replace & release old skb */\n\t/* force ppkt->data at 8-byte alignment address */\n\tskb_reserve(ppkt, 8 - ((SIZE_PTR)ppkt->data & 7));\n\t/* force ip_hdr at 8-byte alignment address according to shift_sz */\n\tskb_reserve(ppkt, shift_sz);\n\n\t/* copy data to new pkt */\n\tptr = skb_put(ppkt, pfhdr->len);\n\tif (ptr)\n\t\t_rtw_memcpy(ptr, pfhdr->rx_data, pfhdr->len);\n\n\trtw_skb_free(pfhdr->pkt);\n\n\t/* attach new pkt to recvframe */\n\tpfhdr->pkt = ppkt;\n\tpfhdr->rx_head = ppkt->head;\n\tpfhdr->rx_data = ppkt->data;\n\tpfhdr->rx_tail = skb_tail_pointer(ppkt);\n\tpfhdr->rx_end = skb_end_pointer(ppkt);\n}\n#else /*!= PLATFORM_LINUX*/\n#warning \"recvframe_expand_pkt not implement, defrag may crash system\"\n#endif\n#endif /*#ifndef CONFIG_SDIO_RX_COPY*/\n#endif\n\n/* perform defrag */\nunion recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q);\nunion recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q)\n{\n\t_list\t*plist, *phead;\n\tu8\t*data, wlanhdr_offset;\n\tu8\tcurfragnum;\n\tstruct recv_frame_hdr *pfhdr, *pnfhdr;\n\tunion recv_frame *prframe, *pnextrframe;\n\t_queue\t*pfree_recv_queue;\n\n\n\tcurfragnum = 0;\n\tpfree_recv_queue = &adapter->recvpriv.free_recv_queue;\n\n\tphead = get_list_head(defrag_q);\n\tplist = get_next(phead);\n\tprframe = LIST_CONTAINOR(plist, union recv_frame, u);\n\tpfhdr = &prframe->u.hdr;\n\trtw_list_delete(&(prframe->u.list));\n\n\tif (curfragnum != pfhdr->attrib.frag_num) {\n\t\t/* the first fragment number must be 0 */\n\t\t/* free the whole queue */\n\t\trtw_free_recvframe(prframe, pfree_recv_queue);\n\t\trtw_free_recvframe_queue(defrag_q, pfree_recv_queue);\n\n\t\treturn NULL;\n\t}\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n#ifndef CONFIG_SDIO_RX_COPY\n\trecvframe_expand_pkt(adapter, prframe);\n#endif\n#endif\n\n\tcurfragnum++;\n\n\tplist = get_list_head(defrag_q);\n\n\tplist = get_next(plist);\n\n\tdata = get_recvframe_data(prframe);\n\n\twhile (rtw_end_of_queue_search(phead, plist) == _FALSE) {\n\t\tpnextrframe = LIST_CONTAINOR(plist, union recv_frame , u);\n\t\tpnfhdr = &pnextrframe->u.hdr;\n\n\n\t\t/* check the fragment sequence  (2nd ~n fragment frame) */\n\n\t\tif (curfragnum != pnfhdr->attrib.frag_num) {\n\t\t\t/* the fragment number must be increasing  (after decache) */\n\t\t\t/* release the defrag_q & prframe */\n\t\t\trtw_free_recvframe(prframe, pfree_recv_queue);\n\t\t\trtw_free_recvframe_queue(defrag_q, pfree_recv_queue);\n\t\t\treturn NULL;\n\t\t}\n\n\t\tcurfragnum++;\n\n\t\t/* copy the 2nd~n fragment frame's payload to the first fragment */\n\t\t/* get the 2nd~last fragment frame's payload */\n\n\t\twlanhdr_offset = pnfhdr->attrib.hdrlen + pnfhdr->attrib.iv_len;\n\n\t\trecvframe_pull(pnextrframe, wlanhdr_offset);\n\n\t\t/* append  to first fragment frame's tail (if privacy frame, pull the ICV) */\n\t\trecvframe_pull_tail(prframe, pfhdr->attrib.icv_len);\n\n\t\t/* memcpy */\n\t\t_rtw_memcpy(pfhdr->rx_tail, pnfhdr->rx_data, pnfhdr->len);\n\n\t\trecvframe_put(prframe, pnfhdr->len);\n\n\t\tpfhdr->attrib.icv_len = pnfhdr->attrib.icv_len;\n\t\tplist = get_next(plist);\n\n\t};\n\n\t/* free the defrag_q queue and return the prframe */\n\trtw_free_recvframe_queue(defrag_q, pfree_recv_queue);\n\n\n\n\treturn prframe;\n}\n\n/* check if need to defrag, if needed queue the frame to defrag_q */\nunion recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame)\n{\n\tu8\tismfrag;\n\tu8\tfragnum;\n\tu8\t*psta_addr;\n\tstruct recv_frame_hdr *pfhdr;\n\tstruct sta_info *psta;\n\tstruct sta_priv *pstapriv;\n\t_list *phead;\n\tunion recv_frame *prtnframe = NULL;\n\t_queue *pfree_recv_queue, *pdefrag_q = NULL;\n\n\n\tpstapriv = &padapter->stapriv;\n\n\tpfhdr = &precv_frame->u.hdr;\n\n\tpfree_recv_queue = &padapter->recvpriv.free_recv_queue;\n\n\t/* need to define struct of wlan header frame ctrl */\n\tismfrag = pfhdr->attrib.mfrag;\n\tfragnum = pfhdr->attrib.frag_num;\n\n\tpsta_addr = pfhdr->attrib.ta;\n\tpsta = rtw_get_stainfo(pstapriv, psta_addr);\n\tif (psta == NULL) {\n\t\tu8 type = GetFrameType(pfhdr->rx_data);\n\t\tif (type != WIFI_DATA_TYPE) {\n\t\t\tpsta = rtw_get_bcmc_stainfo(padapter);\n\t\t\tif (psta)\n\t\t\t\tpdefrag_q = &psta->sta_recvpriv.defrag_q;\n\t\t} else\n\t\t\tpdefrag_q = NULL;\n\t} else\n\t\tpdefrag_q = &psta->sta_recvpriv.defrag_q;\n\n\tif ((ismfrag == 0) && (fragnum == 0)) {\n\t\tprtnframe = precv_frame;/* isn't a fragment frame */\n\t}\n\n\tif (ismfrag == 1) {\n\t\t/* 0~(n-1) fragment frame */\n\t\t/* enqueue to defraf_g */\n\t\tif (pdefrag_q != NULL) {\n\t\t\tif (fragnum == 0) {\n\t\t\t\t/* the first fragment */\n\t\t\t\tif (_rtw_queue_empty(pdefrag_q) == _FALSE) {\n\t\t\t\t\t/* free current defrag_q */\n\t\t\t\t\trtw_free_recvframe_queue(pdefrag_q, pfree_recv_queue);\n\t\t\t\t}\n\t\t\t}\n\n\n\t\t\t/* Then enqueue the 0~(n-1) fragment into the defrag_q */\n\n\t\t\t/* _rtw_spinlock(&pdefrag_q->lock); */\n\t\t\tphead = get_list_head(pdefrag_q);\n\t\t\trtw_list_insert_tail(&pfhdr->list, phead);\n\t\t\t/* _rtw_spinunlock(&pdefrag_q->lock); */\n\n\n\t\t\tprtnframe = NULL;\n\n\t\t} else {\n\t\t\t/* can't find this ta's defrag_queue, so free this recv_frame */\n\t\t\trtw_free_recvframe(precv_frame, pfree_recv_queue);\n\t\t\tprtnframe = NULL;\n\t\t}\n\n\t}\n\n\tif ((ismfrag == 0) && (fragnum != 0)) {\n\t\t/* the last fragment frame */\n\t\t/* enqueue the last fragment */\n\t\tif (pdefrag_q != NULL) {\n\t\t\t/* _rtw_spinlock(&pdefrag_q->lock); */\n\t\t\tphead = get_list_head(pdefrag_q);\n\t\t\trtw_list_insert_tail(&pfhdr->list, phead);\n\t\t\t/* _rtw_spinunlock(&pdefrag_q->lock); */\n\n\t\t\t/* call recvframe_defrag to defrag */\n\t\t\tprecv_frame = recvframe_defrag(padapter, pdefrag_q);\n\t\t\tprtnframe = precv_frame;\n\n\t\t} else {\n\t\t\t/* can't find this ta's defrag_queue, so free this recv_frame */\n\t\t\trtw_free_recvframe(precv_frame, pfree_recv_queue);\n\t\t\tprtnframe = NULL;\n\t\t}\n\n\t}\n\n\n\tif ((prtnframe != NULL) && (prtnframe->u.hdr.attrib.privacy)) {\n\t\t/* after defrag we must check tkip mic code */\n\t\tif (recvframe_chkmic(padapter,  prtnframe) == _FAIL) {\n\t\t\trtw_free_recvframe(prtnframe, pfree_recv_queue);\n\t\t\tprtnframe = NULL;\n\t\t}\n\t}\n\n\n\treturn prtnframe;\n\n}\n\nstatic int rtw_recv_indicatepkt_check(union recv_frame *rframe, u8 *ehdr_pos, u32 pkt_len)\n{\n\t_adapter *adapter = rframe->u.hdr.adapter;\n\tstruct recv_priv *recvpriv = &adapter->recvpriv;\n\tstruct ethhdr *ehdr = (struct ethhdr *)ehdr_pos;\n#ifdef DBG_IP_R_MONITOR\n\tint i;\n\tstruct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib;\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_priv\t*pmlmepriv = &adapter->mlmepriv;\n\tstruct wlan_network *cur_network = &(pmlmepriv->cur_network);\n#endif/*DBG_IP_R_MONITOR*/\n\tint ret = _FAIL;\n\n#ifdef CONFIG_WAPI_SUPPORT\n\tif (rtw_wapi_check_for_drop(adapter, rframe, ehdr_pos)) {\n\t\t#ifdef DBG_RX_DROP_FRAME\n\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" rtw_wapi_check_for_drop\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter));\n\t\t#endif\n\t\tgoto exit;\n\t}\n#endif\n\n\tif (rframe->u.hdr.psta)\n\t\trtw_st_ctl_rx(rframe->u.hdr.psta, ehdr_pos);\n\n\tif (ntohs(ehdr->h_proto) == 0x888e)\n\t\tparsing_eapol_packet(adapter, ehdr_pos + ETH_HLEN, rframe->u.hdr.psta, 0);\n#ifdef DBG_ARP_DUMP\n\telse if (ntohs(ehdr->h_proto) == ETH_P_ARP)\n\t\tdump_arp_pkt(RTW_DBGDUMP, ehdr->h_dest, ehdr->h_source, ehdr_pos + ETH_HLEN, 0);\n#endif\n\n\tif (recvpriv->sink_udpport > 0)\n\t\trtw_sink_rtp_seq_dbg(adapter, ehdr_pos);\n\n#ifdef DBG_UDP_PKT_LOSE_11AC\n\t#define PAYLOAD_LEN_LOC_OF_IP_HDR 0x10 /*ethernet payload length location of ip header (DA + SA+eth_type+(version&hdr_len)) */\n\n\tif (ntohs(ehdr->h_proto) == ETH_P_ARP) {\n\t\t/* ARP Payload length will be 42bytes or 42+18(tailer)=60bytes*/\n\t\tif (pkt_len != 42 && pkt_len != 60)\n\t\t\tRTW_INFO(\"Error !!%s,ARP Payload length %u not correct\\n\" , __func__ , pkt_len);\n\t} else if (ntohs(ehdr->h_proto) == ETH_P_IP) {\n\t\tif (be16_to_cpu(*((u16 *)(ehdr_pos + PAYLOAD_LEN_LOC_OF_IP_HDR))) != (pkt_len) - ETH_HLEN) {\n\t\t\tRTW_INFO(\"Error !!%s,Payload length not correct\\n\" , __func__);\n\t\t\tRTW_INFO(\"%s, IP header describe Total length=%u\\n\" , __func__ , be16_to_cpu(*((u16 *)(ehdr_pos + PAYLOAD_LEN_LOC_OF_IP_HDR))));\n\t\t\tRTW_INFO(\"%s, Pkt real length=%u\\n\" , __func__ , (pkt_len) - ETH_HLEN);\n\t\t}\n\t}\n#endif\n\n#ifdef DBG_IP_R_MONITOR\n\t#define LEN_ARP_OP_HDR 7 /*ARP OERATION */\n\tif (ntohs(ehdr->h_proto) == ETH_P_ARP) {\n\n\t\tif(check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE){\n\t\t\tif(ehdr_pos[ETHERNET_HEADER_SIZE+LEN_ARP_OP_HDR] == 2) {\n\n\t\t\t\tRTW_INFO(\"%s,[DBG_ARP] Rx ARP RSP Packet;SeqNum = %d !\\n\",\n\t\t\t\t\t__FUNCTION__, pattrib->seq_num);\n\n\t\t\t\tdump_arp_pkt(RTW_DBGDUMP, ehdr->h_dest, ehdr->h_source, ehdr_pos + ETH_HLEN, 0);\n\n\t\t\t}\n\t\t}\n\t}\n#endif/*DBG_IP_R_MONITOR*/\n\n#ifdef CONFIG_AUTO_AP_MODE\n\tif (ntohs(ehdr->h_proto) == 0x8899)\n\t\trtw_auto_ap_rx_msg_dump(adapter, rframe, ehdr_pos);\n#endif\n\n\tret = _SUCCESS;\n\n#ifdef CONFIG_WAPI_SUPPORT\nexit:\n#endif\n\treturn ret;\n}\n\nstatic void recv_free_fwd_resource(_adapter *adapter, struct xmit_frame *fwd_frame, _list *b2u_list)\n{\n\tstruct xmit_priv *xmitpriv = &adapter->xmitpriv;\n\n\tif (fwd_frame)\n\t\trtw_free_xmitframe(xmitpriv, fwd_frame);\n\n#ifdef CONFIG_RTW_MESH\n#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\tif (!rtw_is_list_empty(b2u_list)) {\n\t\tstruct xmit_frame *b2uframe;\n\t\t_list *list;\n\n\t\tlist = get_next(b2u_list);\n\t\twhile (rtw_end_of_queue_search(b2u_list, list) == _FALSE) {\n\t\t\tb2uframe = LIST_CONTAINOR(list, struct xmit_frame, list);\n\t\t\tlist = get_next(list);\n\t\t\trtw_list_delete(&b2uframe->list);\n\t\t\trtw_free_xmitframe(xmitpriv, b2uframe);\n\t\t}\n\t}\n#endif\n#endif /* CONFIG_RTW_MESH */\n}\n\n#ifdef CONFIG_RTW_MESH\nstatic void recv_fwd_pkt_hdl(_adapter *adapter, _pkt *pkt\n\t, u8 act, struct xmit_frame *fwd_frame, _list *b2u_list)\n{\n\tstruct xmit_priv *xmitpriv = &adapter->xmitpriv;\n\t_pkt *fwd_pkt = pkt;\n\n\tif (act & RTW_RX_MSDU_ACT_INDICATE) {\n\t\tfwd_pkt = rtw_os_pkt_copy(pkt);\n\t\tif (!fwd_pkt) {\n\t\t\t#ifdef DBG_TX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_TX_DROP_FRAME %s rtw_os_pkt_copy fail\\n\", __func__);\n\t\t\t#endif\n\t\t\trecv_free_fwd_resource(adapter, fwd_frame, b2u_list);\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\tif (!rtw_is_list_empty(b2u_list)) {\n\t\t_list *list = get_next(b2u_list);\n\t\tstruct xmit_frame *b2uframe;\n\n\t\twhile (rtw_end_of_queue_search(b2u_list, list) == _FALSE) {\n\t\t\tb2uframe = LIST_CONTAINOR(list, struct xmit_frame, list);\n\t\t\tlist = get_next(list);\n\t\t\trtw_list_delete(&b2uframe->list);\n\n\t\t\tif (!fwd_frame && rtw_is_list_empty(b2u_list)) /* the last fwd_pkt */\n\t\t\t\tb2uframe->pkt = fwd_pkt;\n\t\t\telse\n\t\t\t\tb2uframe->pkt = rtw_os_pkt_copy(fwd_pkt);\n\t\t\tif (!b2uframe->pkt) {\n\t\t\t\trtw_free_xmitframe(xmitpriv, b2uframe);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\trtw_xmit_posthandle(adapter, b2uframe, b2uframe->pkt);\n\t\t}\n\t}\n#endif\n\n\tif (fwd_frame) {\n\t\tfwd_frame->pkt = fwd_pkt;\n\t\tif (rtw_xmit_posthandle(adapter, fwd_frame, fwd_pkt) < 0) {\n\t\t\t#ifdef DBG_TX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_TX_DROP_FRAME %s rtw_xmit_posthandle fail\\n\", __func__);\n\t\t\t#endif\n\t\t\txmitpriv->tx_drop++;\n\t\t}\n\t}\n\nexit:\n\treturn;\n}\n#endif /* CONFIG_RTW_MESH */\n\nint amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe)\n{\n\tstruct rx_pkt_attrib *rattrib = &prframe->u.hdr.attrib;\n\tint\ta_len, padding_len;\n\tu16\tnSubframe_Length;\n\tu8\tnr_subframes, i;\n\tu8\t*pdata;\n\t_pkt *sub_pkt, *subframes[MAX_SUBFRAME_COUNT];\n\tstruct recv_priv *precvpriv = &padapter->recvpriv;\n\t_queue *pfree_recv_queue = &(precvpriv->free_recv_queue);\n\tconst u8 *da, *sa;\n\tint act;\n\tstruct xmit_frame *fwd_frame;\n\t_list b2u_list;\n\tu8 mctrl_len = 0;\n\tint\tret = _SUCCESS;\n\n\tnr_subframes = 0;\n\n\trecvframe_pull(prframe, rattrib->hdrlen);\n\n\tif (rattrib->iv_len > 0)\n\t\trecvframe_pull(prframe, rattrib->iv_len);\n\n\ta_len = prframe->u.hdr.len;\n\tpdata = prframe->u.hdr.rx_data;\n\n\twhile (a_len > ETH_HLEN) {\n\t\t/* Offset 12 denote 2 mac address */\n\t\tnSubframe_Length = RTW_GET_BE16(pdata + 12);\n\t\tif (a_len < (ETHERNET_HEADER_SIZE + nSubframe_Length)) {\n\t\t\tRTW_INFO(\"nRemain_Length is %d and nSubframe_Length is : %d\\n\", a_len, nSubframe_Length);\n\t\t\tbreak;\n\t\t}\n\n\t\tact = RTW_RX_MSDU_ACT_INDICATE;\n\t\tfwd_frame = NULL;\n\n\t\t#ifdef CONFIG_RTW_MESH\n\t\tif (MLME_IS_MESH(padapter)) {\n\t\t\tu8 *mda = pdata, *msa = pdata + ETH_ALEN;\n\t\t\tstruct rtw_ieee80211s_hdr *mctrl = (struct rtw_ieee80211s_hdr *)(pdata + ETH_HLEN);\n\t\t\tint v_ret;\n\n\t\t\tv_ret = rtw_mesh_rx_data_validate_mctrl(padapter, prframe\n\t\t\t\t, mctrl, mda, msa, &mctrl_len, &da, &sa);\n\t\t\tif (v_ret != _SUCCESS)\n\t\t\t\tgoto move_to_next;\n\n\t\t\tact = rtw_mesh_rx_msdu_act_check(prframe\n\t\t\t\t, mda, msa, da, sa, mctrl, &fwd_frame, &b2u_list);\n\t\t} else\n\t\t#endif\n\t\t{\n\t\t\tda = pdata;\n\t\t\tsa = pdata + ETH_ALEN;\n\t\t}\n\n\t\tif (!act)\n\t\t\tgoto move_to_next;\n\n\t\trtw_led_rx_control(padapter, da);\n\n\t\tsub_pkt = rtw_os_alloc_msdu_pkt(prframe, da, sa\n\t\t\t, pdata + ETH_HLEN + mctrl_len, nSubframe_Length - mctrl_len);\n\t\tif (sub_pkt == NULL) {\n\t\t\tif (act & RTW_RX_MSDU_ACT_INDICATE) {\n\t\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME %s rtw_os_alloc_msdu_pkt fail\\n\", __func__);\n\t\t\t\t#endif\n\t\t\t}\n\t\t\tif (act & RTW_RX_MSDU_ACT_FORWARD) {\n\t\t\t\t#ifdef DBG_TX_DROP_FRAME\n\t\t\t\tRTW_INFO(\"DBG_TX_DROP_FRAME %s rtw_os_alloc_msdu_pkt fail\\n\", __func__);\n\t\t\t\t#endif\n\t\t\t\trecv_free_fwd_resource(padapter, fwd_frame, &b2u_list);\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\n\t\t#ifdef CONFIG_RTW_MESH\n\t\tif (act & RTW_RX_MSDU_ACT_FORWARD) {\n\t\t\trecv_fwd_pkt_hdl(padapter, sub_pkt, act, fwd_frame, &b2u_list);\n\t\t\tif (!(act & RTW_RX_MSDU_ACT_INDICATE))\n\t\t\t\tgoto move_to_next;\n\t\t}\n\t\t#endif\n\n\t\tif (rtw_recv_indicatepkt_check(prframe, rtw_os_pkt_data(sub_pkt), rtw_os_pkt_len(sub_pkt)) == _SUCCESS)\n\t\t\tsubframes[nr_subframes++] = sub_pkt;\n\t\telse\n\t\t\trtw_os_pkt_free(sub_pkt);\n\nmove_to_next:\n\t\t/* move the data point to data content */\n\t\tpdata += ETH_HLEN;\n\t\ta_len -= ETH_HLEN;\n\n\t\tif (nr_subframes >= MAX_SUBFRAME_COUNT) {\n\t\t\tRTW_WARN(\"ParseSubframe(): Too many Subframes! Packets dropped!\\n\");\n\t\t\tbreak;\n\t\t}\n\n\t\tpdata += nSubframe_Length;\n\t\ta_len -= nSubframe_Length;\n\t\tif (a_len != 0) {\n\t\t\tpadding_len = 4 - ((nSubframe_Length + ETH_HLEN) & (4 - 1));\n\t\t\tif (padding_len == 4)\n\t\t\t\tpadding_len = 0;\n\n\t\t\tif (a_len < padding_len) {\n\t\t\t\tRTW_INFO(\"ParseSubframe(): a_len < padding_len !\\n\");\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tpdata += padding_len;\n\t\t\ta_len -= padding_len;\n\t\t}\n\t}\n\n\tfor (i = 0; i < nr_subframes; i++) {\n\t\tsub_pkt = subframes[i];\n\n\t\t/* Indicat the packets to upper layer */\n\t\tif (sub_pkt)\n\t\t\trtw_os_recv_indicate_pkt(padapter, sub_pkt, prframe);\n\t}\n\n\tprframe->u.hdr.len = 0;\n\trtw_free_recvframe(prframe, pfree_recv_queue);/* free this recv_frame */\n\n\treturn ret;\n}\n\nstatic int recv_process_mpdu(_adapter *padapter, union recv_frame *prframe)\n{\n\t_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;\n\tstruct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;\n\tint ret;\n\n\tif (pattrib->amsdu) {\n\t\tret = amsdu_to_msdu(padapter, prframe);\n\t\tif (ret != _SUCCESS) {\n\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" amsdu_to_msdu fail\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter));\n\t\t\t#endif\n\t\t\trtw_free_recvframe(prframe, pfree_recv_queue);\n\t\t\tgoto exit;\n\t\t}\n\t} else {\n\t\tint act = RTW_RX_MSDU_ACT_INDICATE;\n\t\tstruct xmit_frame *fwd_frame = NULL;\n\t\t_list b2u_list;\n\n\t\t#ifdef CONFIG_RTW_MESH\n\t\tif (MLME_IS_MESH(padapter) && pattrib->mesh_ctrl_present) {\n\t\t\tact = rtw_mesh_rx_msdu_act_check(prframe\n\t\t\t\t, pattrib->mda, pattrib->msa\n\t\t\t\t, pattrib->dst, pattrib->src\n\t\t\t\t, (struct rtw_ieee80211s_hdr *)(get_recvframe_data(prframe) + pattrib->hdrlen + pattrib->iv_len)\n\t\t\t\t, &fwd_frame, &b2u_list);\n\t\t}\n\t\t#endif\n\n\t\tif (!act) {\n\t\t\trtw_free_recvframe(prframe, pfree_recv_queue);\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\trtw_led_rx_control(padapter, pattrib->dst);\n\n\t\tret = wlanhdr_to_ethhdr(prframe);\n\t\tif (ret != _SUCCESS) {\n\t\t\tif (act & RTW_RX_MSDU_ACT_INDICATE) {\n\t\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" wlanhdr_to_ethhdr: drop pkt\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter));\n\t\t\t\t#endif\n\t\t\t}\n\t\t\tif (act & RTW_RX_MSDU_ACT_FORWARD) {\n\t\t\t\t#ifdef DBG_TX_DROP_FRAME\n\t\t\t\tRTW_INFO(\"DBG_TX_DROP_FRAME %s wlanhdr_to_ethhdr fail\\n\", __func__);\n\t\t\t\t#endif\n\t\t\t\trecv_free_fwd_resource(padapter, fwd_frame, &b2u_list);\n\t\t\t}\n\t\t\trtw_free_recvframe(prframe, pfree_recv_queue);\n\t\t\tgoto exit;\n\t\t}\n\n\t\t#ifdef CONFIG_RTW_MESH\n\t\tif (act & RTW_RX_MSDU_ACT_FORWARD) {\n\t\t\trecv_fwd_pkt_hdl(padapter, prframe->u.hdr.pkt, act, fwd_frame, &b2u_list);\n\t\t\tif (!(act & RTW_RX_MSDU_ACT_INDICATE)) {\n\t\t\t\tprframe->u.hdr.pkt = NULL;\n\t\t\t\trtw_free_recvframe(prframe, pfree_recv_queue);\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\t\t#endif\n\n\t\tif (!RTW_CANNOT_RUN(padapter)) {\n\t\t\tret = rtw_recv_indicatepkt_check(prframe\n\t\t\t\t, get_recvframe_data(prframe), get_recvframe_len(prframe));\n\t\t\tif (ret != _SUCCESS) {\n\t\t\t\trtw_free_recvframe(prframe, pfree_recv_queue);\n\t\t\t\tgoto exit;\n\t\t\t}\n\n\t\t\t/* indicate this recv_frame */\n\t\t\tret = rtw_recv_indicatepkt(padapter, prframe);\n\t\t\tif (ret != _SUCCESS) {\n\t\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" rtw_recv_indicatepkt fail!\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter));\n\t\t\t\t#endif\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t} else {\n\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" DS:%u SR:%u\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter)\n\t\t\t\t, rtw_is_drv_stopped(padapter)\n\t\t\t\t, rtw_is_surprise_removed(padapter));\n\t\t\t#endif\n\t\t\tret = _SUCCESS; /* don't count as packet drop */\n\t\t\trtw_free_recvframe(prframe, pfree_recv_queue);\n\t\t}\n\t}\n\nexit:\n\treturn ret;\n}\n\n#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)\nstatic int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num)\n{\n\tPADAPTER padapter = preorder_ctrl->padapter;\n\tstruct recv_priv  *precvpriv = &padapter->recvpriv;\n\tu8\twsize = preorder_ctrl->wsize_b;\n\tu16\twend;\n\n\t/* Rx Reorder initialize condition. */\n\tif (preorder_ctrl->indicate_seq == 0xFFFF) {\n\t\tpreorder_ctrl->indicate_seq = seq_num;\n\t\t#ifdef DBG_RX_SEQ\n\t\tRTW_INFO(\"DBG_RX_SEQ \"FUNC_ADPT_FMT\" tid:%u SN_INIT indicate_seq:%d, seq_num:%d\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);\n\t\t#endif\n\t}\n\twend = (preorder_ctrl->indicate_seq + wsize - 1) & 0xFFF; /* % 4096; */\n\n\t/* Drop out the packet which SeqNum is smaller than WinStart */\n\tif (SN_LESS(seq_num, preorder_ctrl->indicate_seq)) {\n\t\t#ifdef DBG_RX_DROP_FRAME\n\t\tRTW_INFO(FUNC_ADPT_FMT\" tid:%u indicate_seq:%d > seq_num:%d\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);\n\t\t#endif\n\t\treturn _FALSE;\n\t}\n\n\t/*\n\t* Sliding window manipulation. Conditions includes:\n\t* 1. Incoming SeqNum is equal to WinStart =>Window shift 1\n\t* 2. Incoming SeqNum is larger than the WinEnd => Window shift N\n\t*/\n\tif (SN_EQUAL(seq_num, preorder_ctrl->indicate_seq)) {\n\t\tpreorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF;\n\t\t#ifdef DBG_RX_SEQ\n\t\tRTW_INFO(\"DBG_RX_SEQ \"FUNC_ADPT_FMT\" tid:%u SN_EQUAL indicate_seq:%d, seq_num:%d\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);\n\t\t#endif\n\n\t} else if (SN_LESS(wend, seq_num)) {\n\t\t/* boundary situation, when seq_num cross 0xFFF */\n\t\tif (seq_num >= (wsize - 1))\n\t\t\tpreorder_ctrl->indicate_seq = seq_num + 1 - wsize;\n\t\telse\n\t\t\tpreorder_ctrl->indicate_seq = 0xFFF - (wsize - (seq_num + 1)) + 1;\n\n\t\tprecvpriv->dbg_rx_ampdu_window_shift_cnt++;\n\t\t#ifdef DBG_RX_SEQ\n\t\tRTW_INFO(\"DBG_RX_SEQ \"FUNC_ADPT_FMT\" tid:%u SN_LESS(wend, seq_num) indicate_seq:%d, seq_num:%d\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);\n\t\t#endif\n\t}\n\n\treturn _TRUE;\n}\n\nstatic int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe)\n{\n\tstruct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;\n\t_queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;\n\t_list\t*phead, *plist;\n\tunion recv_frame *pnextrframe;\n\tstruct rx_pkt_attrib *pnextattrib;\n\n\t/* DbgPrint(\"+enqueue_reorder_recvframe()\\n\"); */\n\n\t/* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */\n\t/* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */\n\n\n\tphead = get_list_head(ppending_recvframe_queue);\n\tplist = get_next(phead);\n\n\twhile (rtw_end_of_queue_search(phead, plist) == _FALSE) {\n\t\tpnextrframe = LIST_CONTAINOR(plist, union recv_frame, u);\n\t\tpnextattrib = &pnextrframe->u.hdr.attrib;\n\n\t\tif (SN_LESS(pnextattrib->seq_num, pattrib->seq_num))\n\t\t\tplist = get_next(plist);\n\t\telse if (SN_EQUAL(pnextattrib->seq_num, pattrib->seq_num)) {\n\t\t\t/* Duplicate entry is found!! Do not insert current entry. */\n\n\t\t\t/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */\n\n\t\t\treturn _FALSE;\n\t\t} else\n\t\t\tbreak;\n\n\t\t/* DbgPrint(\"enqueue_reorder_recvframe():while\\n\"); */\n\n\t}\n\n\n\t/* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */\n\t/* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */\n\n\trtw_list_delete(&(prframe->u.hdr.list));\n\n\trtw_list_insert_tail(&(prframe->u.hdr.list), plist);\n\n\t/* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */\n\t/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */\n\n\n\treturn _TRUE;\n\n}\n\nstatic void recv_indicatepkts_pkt_loss_cnt(_adapter *padapter, u64 prev_seq, u64 current_seq)\n{\n\tstruct recv_priv *precvpriv = &padapter->recvpriv;\n\n\tif (current_seq < prev_seq) {\n\t\tprecvpriv->dbg_rx_ampdu_loss_count += (4096 + current_seq - prev_seq);\n\t\tprecvpriv->rx_drop += (4096 + current_seq - prev_seq);\n\t} else {\n\t\tprecvpriv->dbg_rx_ampdu_loss_count += (current_seq - prev_seq);\n\t\tprecvpriv->rx_drop += (current_seq - prev_seq);\n\t}\n}\n\nstatic int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced)\n{\n\t/* _irqL irql; */\n\t_list\t*phead, *plist;\n\tunion recv_frame *prframe;\n\tstruct rx_pkt_attrib *pattrib;\n\t/* u8 index = 0; */\n\tint bPktInBuf = _FALSE;\n\tstruct recv_priv *precvpriv = &padapter->recvpriv;\n\t_queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;\n\n\tDBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_in_oder);\n\n\t/* DbgPrint(\"+recv_indicatepkts_in_order\\n\"); */\n\n\t/* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */\n\t/* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */\n\n\tphead =\tget_list_head(ppending_recvframe_queue);\n\tplist = get_next(phead);\n\n#if 0\n\t/* Check if there is any other indication thread running. */\n\tif (pTS->RxIndicateState == RXTS_INDICATE_PROCESSING)\n\t\treturn;\n#endif\n\n\t/* Handling some condition for forced indicate case. */\n\tif (bforced == _TRUE) {\n\t\tprecvpriv->dbg_rx_ampdu_forced_indicate_count++;\n\t\tif (rtw_is_list_empty(phead)) {\n\t\t\t/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */\n\t\t\t/* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */\n\t\t\treturn _TRUE;\n\t\t}\n\n\t\tprframe = LIST_CONTAINOR(plist, union recv_frame, u);\n\t\tpattrib = &prframe->u.hdr.attrib;\n\n\t\t#ifdef DBG_RX_SEQ\n\t\tRTW_INFO(\"DBG_RX_SEQ \"FUNC_ADPT_FMT\" tid:%u FORCE indicate_seq:%d, seq_num:%d\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pattrib->seq_num);\n\t\t#endif\n\t\trecv_indicatepkts_pkt_loss_cnt(padapter, preorder_ctrl->indicate_seq, pattrib->seq_num);\n\t\tpreorder_ctrl->indicate_seq = pattrib->seq_num;\n\t}\n\n\t/* Prepare indication list and indication. */\n\t/* Check if there is any packet need indicate. */\n\twhile (!rtw_is_list_empty(phead)) {\n\n\t\tprframe = LIST_CONTAINOR(plist, union recv_frame, u);\n\t\tpattrib = &prframe->u.hdr.attrib;\n\n\t\tif (!SN_LESS(preorder_ctrl->indicate_seq, pattrib->seq_num)) {\n\n#if 0\n\t\t\t/* This protect buffer from overflow. */\n\t\t\tif (index >= REORDER_WIN_SIZE) {\n\t\t\t\tRT_ASSERT(FALSE, (\"IndicateRxReorderList(): Buffer overflow!!\\n\"));\n\t\t\t\tbPktInBuf = TRUE;\n\t\t\t\tbreak;\n\t\t\t}\n#endif\n\n\t\t\tplist = get_next(plist);\n\t\t\trtw_list_delete(&(prframe->u.hdr.list));\n\n\t\t\tif (SN_EQUAL(preorder_ctrl->indicate_seq, pattrib->seq_num)) {\n\t\t\t\tpreorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF;\n\t\t\t\t#ifdef DBG_RX_SEQ\n\t\t\t\tRTW_INFO(\"DBG_RX_SEQ \"FUNC_ADPT_FMT\" tid:%u SN_EQUAL indicate_seq:%d, seq_num:%d\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pattrib->seq_num);\n\t\t\t\t#endif\n\t\t\t}\n\n#if 0\n\t\t\tindex++;\n\t\t\tif (index == 1) {\n\t\t\t\t/* Cancel previous pending timer. */\n\t\t\t\t/* PlatformCancelTimer(Adapter, &pTS->RxPktPendingTimer); */\n\t\t\t\tif (bforced != _TRUE) {\n\t\t\t\t\t/* RTW_INFO(\"_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);\\n\"); */\n\t\t\t\t\t_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);\n\t\t\t\t}\n\t\t\t}\n#endif\n\n\t\t\t/* Set this as a lock to make sure that only one thread is indicating packet. */\n\t\t\t/* pTS->RxIndicateState = RXTS_INDICATE_PROCESSING; */\n\n\t\t\t/* Indicate packets */\n\t\t\t/* RT_ASSERT((index<=REORDER_WIN_SIZE), (\"RxReorderIndicatePacket(): Rx Reorder buffer full!!\\n\")); */\n\n\n\t\t\t/* indicate this recv_frame */\n\t\t\t/* DbgPrint(\"recv_indicatepkts_in_order, indicate_seq=%d, seq_num=%d\\n\", precvpriv->indicate_seq, pattrib->seq_num); */\n\t\t\tif (recv_process_mpdu(padapter, prframe) != _SUCCESS)\n\t\t\t\tprecvpriv->dbg_rx_drop_count++;\n\n\t\t\t/* Update local variables. */\n\t\t\tbPktInBuf = _FALSE;\n\n\t\t} else {\n\t\t\tbPktInBuf = _TRUE;\n\t\t\tbreak;\n\t\t}\n\n\t\t/* DbgPrint(\"recv_indicatepkts_in_order():while\\n\"); */\n\n\t}\n\n\t/* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */\n\t/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */\n\n#if 0\n\t/* Release the indication lock and set to new indication step. */\n\tif (bPktInBuf) {\n\t\t/*  Set new pending timer. */\n\t\t/* pTS->RxIndicateState = RXTS_INDICATE_REORDER; */\n\t\t/* PlatformSetTimer(Adapter, &pTS->RxPktPendingTimer, pHTInfo->RxReorderPendingTime); */\n\n\t\t_set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME);\n\t} else {\n\t\t/* pTS->RxIndicateState = RXTS_INDICATE_IDLE; */\n\t}\n#endif\n\t/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */\n\n\t/* return _TRUE; */\n\treturn bPktInBuf;\n\n}\n\nstatic int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe)\n{\n\t_irqL irql;\n\tstruct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;\n\tstruct recv_reorder_ctrl *preorder_ctrl = prframe->u.hdr.preorder_ctrl;\n\t_queue *ppending_recvframe_queue = preorder_ctrl ? &preorder_ctrl->pending_recvframe_queue : NULL;\n\tstruct recv_priv  *precvpriv = &padapter->recvpriv;\n\n\tif (!pattrib->qos || !preorder_ctrl || preorder_ctrl->enable == _FALSE)\n\t\tgoto _success_exit;\n\n\n\tDBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_reoder);\n\n\t_enter_critical_bh(&ppending_recvframe_queue->lock, &irql);\n\n\n\tif(rtw_test_and_clear_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack))\n\t\tpreorder_ctrl->indicate_seq = 0xFFFF;\n\t#ifdef DBG_RX_SEQ\n\tRTW_INFO(\"DBG_RX_SEQ %s:preorder_ctrl->rec_abba_rsp_ack = %u,indicate_seq = %d\\n\"\n\t\t, __func__\n\t\t, preorder_ctrl->rec_abba_rsp_ack\n\t\t, preorder_ctrl->indicate_seq);\n\t#endif\n\n\t/* s2. check if winstart_b(indicate_seq) needs to been updated */\n\tif (!check_indicate_seq(preorder_ctrl, pattrib->seq_num)) {\n\t\tprecvpriv->dbg_rx_ampdu_drop_count++;\n\t\t/* pHTInfo->RxReorderDropCounter++; */\n\t\t/* ReturnRFDList(Adapter, pRfd); */\n\t\t/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */\n\t\t/* return _FAIL; */\n\n\t\t#ifdef DBG_RX_DROP_FRAME\n\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" check_indicate_seq fail\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter));\n\t\t#endif\n#if 0\n\t\trtw_recv_indicatepkt(padapter, prframe);\n\n\t\t_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);\n\n\t\tgoto _success_exit;\n#else\n\t\tgoto _err_exit;\n#endif\n\t}\n\n\n\t/* s3. Insert all packet into Reorder Queue to maintain its ordering. */\n\tif (!enqueue_reorder_recvframe(preorder_ctrl, prframe)) {\n\t\t/* DbgPrint(\"recv_indicatepkt_reorder, enqueue_reorder_recvframe fail!\\n\"); */\n\t\t/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */\n\t\t/* return _FAIL; */\n\t\t#ifdef DBG_RX_DROP_FRAME\n\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" enqueue_reorder_recvframe fail\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter));\n\t\t#endif\n\t\tgoto _err_exit;\n\t}\n\n\n\t/* s4. */\n\t/* Indication process. */\n\t/* After Packet dropping and Sliding Window shifting as above, we can now just indicate the packets */\n\t/* with the SeqNum smaller than latest WinStart and buffer other packets. */\n\t/*  */\n\t/* For Rx Reorder condition: */\n\t/* 1. All packets with SeqNum smaller than WinStart => Indicate */\n\t/* 2. All packets with SeqNum larger than or equal to WinStart => Buffer it. */\n\t/*  */\n\n\t/* recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE); */\n\tif (recv_indicatepkts_in_order(padapter, preorder_ctrl, _FALSE) == _TRUE) {\n\t\tif (!preorder_ctrl->bReorderWaiting) {\n\t\t\tpreorder_ctrl->bReorderWaiting = _TRUE;\n\t\t\t_set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME);\n\t\t}\n\t\t_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);\n\t} else {\n\t\tpreorder_ctrl->bReorderWaiting = _FALSE;\n\t\t_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);\n\t\t_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);\n\t}\n\n\treturn RTW_RX_HANDLED;\n\n_success_exit:\n\n\treturn _SUCCESS;\n\n_err_exit:\n\n\t_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);\n\n\treturn _FAIL;\n}\n\n\nvoid rtw_reordering_ctrl_timeout_handler(void *pcontext)\n{\n\t_irqL irql;\n\tstruct recv_reorder_ctrl *preorder_ctrl = (struct recv_reorder_ctrl *)pcontext;\n\t_adapter *padapter = preorder_ctrl->padapter;\n\t_queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;\n\n\n\tif (RTW_CANNOT_RUN(padapter))\n\t\treturn;\n\n\t/* RTW_INFO(\"+rtw_reordering_ctrl_timeout_handler()=>\\n\"); */\n\n\t_enter_critical_bh(&ppending_recvframe_queue->lock, &irql);\n\n\tif (preorder_ctrl)\n\t\tpreorder_ctrl->bReorderWaiting = _FALSE;\n\n\tif (recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE) == _TRUE)\n\t\t_set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME);\n\n\t_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);\n\n}\n#endif /* defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) */\n\nstatic void recv_set_iseq_before_mpdu_process(union recv_frame *rframe, u16 seq_num, const char *caller)\n{\n#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)\n\tstruct recv_reorder_ctrl *reorder_ctrl = rframe->u.hdr.preorder_ctrl;\n\n\tif (reorder_ctrl) {\n\t\treorder_ctrl->indicate_seq = seq_num;\n\t\t#ifdef DBG_RX_SEQ\n\t\tRTW_INFO(\"DBG_RX_SEQ %s(\"ADPT_FMT\")-B tid:%u indicate_seq:%d, seq_num:%d\\n\"\n\t\t\t, caller, ADPT_ARG(reorder_ctrl->padapter)\n\t\t\t, reorder_ctrl->tid, reorder_ctrl->indicate_seq, seq_num);\n\t\t#endif\n\t}\n#endif\n}\n\nstatic void recv_set_iseq_after_mpdu_process(union recv_frame *rframe, u16 seq_num, const char *caller)\n{\n#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)\n\tstruct recv_reorder_ctrl *reorder_ctrl = rframe->u.hdr.preorder_ctrl;\n\n\tif (reorder_ctrl) {\n\t\treorder_ctrl->indicate_seq = (reorder_ctrl->indicate_seq + 1) % 4096;\n\t\t#ifdef DBG_RX_SEQ\n\t\tRTW_INFO(\"DBG_RX_SEQ %s(\"ADPT_FMT\")-A tid:%u indicate_seq:%d, seq_num:%d\\n\"\n\t\t\t, caller, ADPT_ARG(reorder_ctrl->padapter)\n\t\t\t, reorder_ctrl->tid, reorder_ctrl->indicate_seq, seq_num);\n\t\t#endif\n\t}\n#endif\n}\n\n#ifdef CONFIG_MP_INCLUDED\nint validate_mp_recv_frame(_adapter *adapter, union recv_frame *precv_frame)\n{\n\tint ret = _SUCCESS;\n\tu8 *ptr = precv_frame->u.hdr.rx_data;\n\tu8 type, subtype;\n\tstruct mp_priv *pmppriv = &adapter->mppriv;\n\tstruct mp_tx\t\t*pmptx;\n\tunsigned char\t*sa , *da, *bs;\n\tstruct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;\n\tu32 i = 0;\n\tu8 rtk_prefix[]={0x52, 0x65, 0x61, 0x6C, 0x4C, 0x6F, 0x76, 0x65, 0x54, 0x65, 0x6B};\n\tu8 *prx_data;\n\tpmptx = &pmppriv->tx;\n\n\n\tif (pmppriv->mplink_brx == _FALSE) {\n\n\t\tu8 bDumpRxPkt = 0;\n\t\ttype =  GetFrameType(ptr);\n\t\tsubtype = get_frame_sub_type(ptr); /* bit(7)~bit(2)\t */\n\n\t\tRTW_INFO(\"hdr len = %d iv_len=%d \\n\", pattrib->hdrlen , pattrib->iv_len);\n\t\tprx_data = ptr + pattrib->hdrlen + pattrib->iv_len;\n\n\t\tfor (i = 0; i < precv_frame->u.hdr.len; i++) {\n\t\t\tif (precv_frame->u.hdr.len < (11 + i))\n\t\t\t\tbreak;\n\n\t\t\tif (_rtw_memcmp(prx_data + i, (void *)&rtk_prefix, 11) == _FALSE) {\n\t\t\t\tbDumpRxPkt = 0;\n\t\t\t\tRTW_DBG(\"prx_data = %02X != rtk_prefix[%d] = %02X \\n\", *(prx_data + i), i , rtk_prefix[i]);\n\t\t\t\t} else {\n\t\t\t\tbDumpRxPkt = 1;\n\t\t\t\tRTW_DBG(\"prx_data = %02X = rtk_prefix[%d] = %02X \\n\", *(prx_data + i), i , rtk_prefix[i]);\n\t\t\t\tbreak;\n\t\t\t\t}\n\t\t}\n\n\t\tif (bDumpRxPkt == 1) { /* dump all rx packets */\n\t\t\tint i;\n\t\t\tRTW_INFO(\"############ type:0x%02x subtype:0x%02x #################\\n\", type, subtype);\n\n\t\t\tfor (i = 0; i < precv_frame->u.hdr.len; i = i + 8)\n\t\t\t\tRTW_INFO(\"%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\\n\", *(ptr + i),\n\t\t\t\t\t*(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7));\n\t\t\t\tRTW_INFO(\"#############################\\n\");\n\t\t\t\t_rtw_memset(pmppriv->mplink_buf, '\\0' , sizeof(pmppriv->mplink_buf));\n\t\t\t\t_rtw_memcpy(pmppriv->mplink_buf, ptr, precv_frame->u.hdr.len);\n\t\t\t\tpmppriv->mplink_rx_len = precv_frame->u.hdr.len;\n\t\t\t\tpmppriv->mplink_brx =_TRUE;\n\t\t}\n\t}\n\tif (pmppriv->bloopback) {\n\t\tif (_rtw_memcmp(ptr + 24, pmptx->buf + 24, precv_frame->u.hdr.len - 24) == _FALSE) {\n\t\t\tRTW_INFO(\"Compare payload content Fail !!!\\n\");\n\t\t\tret = _FAIL;\n\t\t}\n\t}\n \tif (pmppriv->bSetRxBssid == _TRUE) {\n\n\t\tsa = get_addr2_ptr(ptr);\n\t\tda = GetAddr1Ptr(ptr);\n\t\tbs = GetAddr3Ptr(ptr);\n\t\ttype =\tGetFrameType(ptr);\n\t\tsubtype = get_frame_sub_type(ptr); /* bit(7)~bit(2)  */\n\n\t\tif (_rtw_memcmp(bs, adapter->mppriv.network_macaddr, ETH_ALEN) == _FALSE)\n\t\t\tret = _FAIL;\n\n\t\tRTW_DBG(\"############ type:0x%02x subtype:0x%02x #################\\n\", type, subtype);\n\t\tRTW_DBG(\"A2 sa %02X:%02X:%02X:%02X:%02X:%02X \\n\", *(sa) , *(sa + 1), *(sa+ 2), *(sa + 3), *(sa + 4), *(sa + 5));\n\t\tRTW_DBG(\"A1 da %02X:%02X:%02X:%02X:%02X:%02X \\n\", *(da) , *(da + 1), *(da+ 2), *(da + 3), *(da + 4), *(da + 5));\n\t\tRTW_DBG(\"A3 bs %02X:%02X:%02X:%02X:%02X:%02X \\n --------------------------\\n\", *(bs) , *(bs + 1), *(bs+ 2), *(bs + 3), *(bs + 4), *(bs + 5));\n\t}\n\n\tif (!adapter->mppriv.bmac_filter)\n\t\treturn ret;\n\n\tif (_rtw_memcmp(get_addr2_ptr(ptr), adapter->mppriv.mac_filter, ETH_ALEN) == _FALSE)\n\t\tret = _FAIL;\n\n\treturn ret;\n}\n\nstatic sint MPwlanhdr_to_ethhdr(union recv_frame *precvframe)\n{\n\tsint\trmv_len;\n\tu16 eth_type, len;\n\tu8\tbsnaphdr;\n\tu8\t*psnap_type;\n\tu8 mcastheadermac[] = {0x01, 0x00, 0x5e};\n\n\tstruct ieee80211_snap_hdr\t*psnap;\n\n\tsint ret = _SUCCESS;\n\t_adapter\t\t\t*adapter = precvframe->u.hdr.adapter;\n\n\tu8\t*ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */\n\tstruct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;\n\n\n\tif (pattrib->encrypt)\n\t\trecvframe_pull_tail(precvframe, pattrib->icv_len);\n\n\tpsnap = (struct ieee80211_snap_hdr *)(ptr + pattrib->hdrlen + pattrib->iv_len);\n\tpsnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE;\n\t/* convert hdr + possible LLC headers into Ethernet header */\n\t/* eth_type = (psnap_type[0] << 8) | psnap_type[1]; */\n\tif ((_rtw_memcmp(psnap, rtw_rfc1042_header, SNAP_SIZE) &&\n\t     (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_IPX, 2) == _FALSE) &&\n\t     (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_AARP, 2) == _FALSE)) ||\n\t    /* eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || */\n\t    _rtw_memcmp(psnap, rtw_bridge_tunnel_header, SNAP_SIZE)) {\n\t\t/* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */\n\t\tbsnaphdr = _TRUE;\n\t} else {\n\t\t/* Leave Ethernet header part of hdr and full payload */\n\t\tbsnaphdr = _FALSE;\n\t}\n\n\trmv_len = pattrib->hdrlen + pattrib->iv_len + (bsnaphdr ? SNAP_SIZE : 0);\n\tlen = precvframe->u.hdr.len - rmv_len;\n\n\n\t_rtw_memcpy(&eth_type, ptr + rmv_len, 2);\n\teth_type = ntohs((unsigned short)eth_type); /* pattrib->ether_type */\n\tpattrib->eth_type = eth_type;\n\n\t{\n\t\tptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + (bsnaphdr ? 2 : 0)));\n\t}\n\n\t_rtw_memcpy(ptr, pattrib->dst, ETH_ALEN);\n\t_rtw_memcpy(ptr + ETH_ALEN, pattrib->src, ETH_ALEN);\n\n\tif (!bsnaphdr) {\n\t\tlen = htons(len);\n\t\t_rtw_memcpy(ptr + 12, &len, 2);\n\t}\n\n\n\tlen = htons(pattrib->seq_num);\n\t/* RTW_INFO(\"wlan seq = %d ,seq_num =%x\\n\",len,pattrib->seq_num); */\n\t_rtw_memcpy(ptr + 12, &len, 2);\n\tif (adapter->mppriv.bRTWSmbCfg == _TRUE) {\n\t\t/* if(_rtw_memcmp(mcastheadermac, pattrib->dst, 3) == _TRUE) */ /* SimpleConfig Dest. */\n\t\t/*\t\t\t_rtw_memcpy(ptr+ETH_ALEN, pattrib->bssid, ETH_ALEN); */\n\n\t\tif (_rtw_memcmp(mcastheadermac, pattrib->bssid, 3) == _TRUE) /* SimpleConfig Dest. */\n\t\t\t_rtw_memcpy(ptr, pattrib->bssid, ETH_ALEN);\n\n\t}\n\n\n\treturn ret;\n\n}\n\n\nint mp_recv_frame(_adapter *padapter, union recv_frame *rframe)\n{\n\tint ret = _SUCCESS;\n\tstruct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib;\n\t_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;\n#ifdef CONFIG_MP_INCLUDED\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct mp_priv *pmppriv = &padapter->mppriv;\n#endif /* CONFIG_MP_INCLUDED */\n\tu8 type;\n\tu8 *ptr = rframe->u.hdr.rx_data;\n\tu8 *psa, *pda, *pbssid;\n\tstruct sta_info *psta = NULL;\n\tDBG_COUNTER(padapter->rx_logs.core_rx_pre);\n\n\tif ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) { /* &&(padapter->mppriv.check_mp_pkt == 0)) */\n\t\tif (pattrib->crc_err == 1)\n\t\t\tpadapter->mppriv.rx_crcerrpktcount++;\n\t\telse {\n\t\t\tif (_SUCCESS == validate_mp_recv_frame(padapter, rframe))\n\t\t\t\tpadapter->mppriv.rx_pktcount++;\n\t\t\telse\n\t\t\t\tpadapter->mppriv.rx_pktcount_filter_out++;\n\t\t}\n\n\t\tif (pmppriv->rx_bindicatePkt == _FALSE) {\n\t\t\tret = _FAIL;\n\t\t\trtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */\n\t\t\tgoto exit;\n\t\t} else {\n\t\t\ttype =\tGetFrameType(ptr);\n\t\t\tpattrib->to_fr_ds = get_tofr_ds(ptr);\n\t\t\tpattrib->frag_num = GetFragNum(ptr);\n\t\t\tpattrib->seq_num = GetSequence(ptr);\n\t\t\tpattrib->pw_save = GetPwrMgt(ptr);\n\t\t\tpattrib->mfrag = GetMFrag(ptr);\n\t\t\tpattrib->mdata = GetMData(ptr);\n\t\t\tpattrib->privacy = GetPrivacy(ptr);\n\t\t\tpattrib->order = GetOrder(ptr);\n\n\t\t\tif (type == WIFI_DATA_TYPE) {\n\t\t\t\tpda = get_da(ptr);\n\t\t\t\tpsa = get_sa(ptr);\n\t\t\t\tpbssid = get_hdr_bssid(ptr);\n\n\t\t\t\t_rtw_memcpy(pattrib->dst, pda, ETH_ALEN);\n\t\t\t\t_rtw_memcpy(pattrib->src, psa, ETH_ALEN);\n\t\t\t\t_rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN);\n\n\t\t\t\tswitch (pattrib->to_fr_ds) {\n\t\t\t\tcase 0:\n\t\t\t\t\t_rtw_memcpy(pattrib->ra, pda, ETH_ALEN);\n\t\t\t\t\t_rtw_memcpy(pattrib->ta, psa, ETH_ALEN);\n\t\t\t\t\tret = sta2sta_data_frame(padapter, rframe, &psta);\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase 1:\n\n\t\t\t\t\t_rtw_memcpy(pattrib->ra, pda, ETH_ALEN);\n\t\t\t\t\t_rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN);\n\t\t\t\t\tret = ap2sta_data_frame(padapter, rframe, &psta);\n\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase 2:\n\t\t\t\t\t_rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN);\n\t\t\t\t\t_rtw_memcpy(pattrib->ta, psa, ETH_ALEN);\n\t\t\t\t\tret = sta2ap_data_frame(padapter, rframe, &psta);\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase 3:\n\t\t\t\t\t_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);\n\t\t\t\t\t_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);\n\t\t\t\t\tret = _FAIL;\n\t\t\t\t\tbreak;\n\n\t\t\t\tdefault:\n\t\t\t\t\tret = _FAIL;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\tret = MPwlanhdr_to_ethhdr(rframe);\n\n\t\t\t\tif (ret != _SUCCESS) {\n\t\t\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" wlanhdr_to_ethhdr: drop pkt\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter));\n\t\t\t\t\t#endif\n\t\t\t\t\trtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */\n\t\t\t\t\tret = _FAIL;\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t\tif (!RTW_CANNOT_RUN(padapter)) {\n\t\t\t\t\t/* indicate this recv_frame */\n\t\t\t\t\tret = rtw_recv_indicatepkt(padapter, rframe);\n\t\t\t\t\tif (ret != _SUCCESS) {\n\t\t\t\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\t\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" rtw_recv_indicatepkt fail!\\n\"\n\t\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter));\n\t\t\t\t\t\t#endif\n\t\t\t\t\t\trtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */\n\t\t\t\t\t\tret = _FAIL;\n\n\t\t\t\t\t\tgoto exit;\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\t#ifdef DBG_RX_DROP_FRAME\n\t\t\t\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" bDriverStopped(%s) OR bSurpriseRemoved(%s)\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter)\n\t\t\t\t\t\t, rtw_is_drv_stopped(padapter) ? \"True\" : \"False\"\n\t\t\t\t\t\t, rtw_is_surprise_removed(padapter) ? \"True\" : \"False\");\n\t\t\t\t\t#endif\n\t\t\t\t\tret = _FAIL;\n\t\t\t\t\trtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\n\t\t\t}\n\t\t}\n\n\t}\n\n\trtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */\n\tret = _FAIL;\n\nexit:\n\treturn ret;\n\n}\n#endif\n\nstatic sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, u8 *buf)\n{\n#define CHAN2FREQ(a) ((a < 14) ? (2407+5*a) : (5000+5*a))\n\n#if 0\n#define RTW_RX_RADIOTAP_PRESENT (\\\n\t\t\t\t (1 << IEEE80211_RADIOTAP_TSFT)              | \\\n\t\t\t\t (1 << IEEE80211_RADIOTAP_FLAGS)             | \\\n\t\t\t\t (1 << IEEE80211_RADIOTAP_RATE)              | \\\n\t\t\t\t (1 << IEEE80211_RADIOTAP_CHANNEL)           | \\\n\t\t\t\t (0 << IEEE80211_RADIOTAP_FHSS)              | \\\n\t\t\t\t (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)     | \\\n\t\t\t\t (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE)      | \\\n\t\t\t\t (0 << IEEE80211_RADIOTAP_LOCK_QUALITY)      | \\\n\t\t\t\t (0 << IEEE80211_RADIOTAP_TX_ATTENUATION)    | \\\n\t\t\t\t (0 << IEEE80211_RADIOTAP_DB_TX_ATTENUATION) | \\\n\t\t\t\t (0 << IEEE80211_RADIOTAP_DBM_TX_POWER)      | \\\n\t\t\t\t (1 << IEEE80211_RADIOTAP_ANTENNA)           | \\\n\t\t\t\t (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL)      | \\\n\t\t\t\t (0 << IEEE80211_RADIOTAP_DB_ANTNOISE)       | \\\n\t\t\t\t (0 << IEEE80211_RADIOTAP_RX_FLAGS)          | \\\n\t\t\t\t (0 << IEEE80211_RADIOTAP_TX_FLAGS)          | \\\n\t\t\t\t (0 << IEEE80211_RADIOTAP_RTS_RETRIES)       | \\\n\t\t\t\t (0 << IEEE80211_RADIOTAP_DATA_RETRIES)      | \\\n\t\t\t\t (0 << IEEE80211_RADIOTAP_MCS)               | \\\n\t\t\t\t (0 << IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE)| \\\n\t\t\t\t (0 << IEEE80211_RADIOTAP_VENDOR_NAMESPACE)  | \\\n\t\t\t\t (0 << IEEE80211_RADIOTAP_EXT)               | \\\n\t\t\t\t 0)\n\n\t/* (0 << IEEE80211_RADIOTAP_AMPDU_STATUS)      | \\ */\n\t/* (0 << IEEE80211_RADIOTAP_VHT)               | \\ */\n#endif\n\n#ifndef IEEE80211_RADIOTAP_RX_FLAGS\n#define IEEE80211_RADIOTAP_RX_FLAGS 14\n#endif\n\n#ifndef IEEE80211_RADIOTAP_MCS\n#define IEEE80211_RADIOTAP_MCS 19\n#endif\n#ifndef IEEE80211_RADIOTAP_VHT\n#define IEEE80211_RADIOTAP_VHT 21\n#endif\n\n#ifndef IEEE80211_RADIOTAP_F_BADFCS\n#define IEEE80211_RADIOTAP_F_BADFCS 0x40 /* bad FCS */\n#endif\n\n\tsint ret = _SUCCESS;\n\tstruct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;\n\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\n\tu16 tmp_16bit = 0;\n\n\tu8 data_rate[] = {\n\t\t2, 4, 11, 22, /* CCK */\n\t\t12, 18, 24, 36, 48, 72, 93, 108, /* OFDM */\n\t\t0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, /* HT MCS index */\n\t\t16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n\t\t0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 1 */\n\t\t0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 2 */\n\t\t0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 3 */\n\t\t0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 4 */\n\t};\n\n\t_pkt *pskb = NULL;\n\n\tstruct ieee80211_radiotap_header *rtap_hdr = NULL;\n\tu8 *ptr = NULL;\n\n\tu8 hdr_buf[64] = {0};\n\tu16 rt_len = 8;\n\n\t/* create header */\n\trtap_hdr = (struct ieee80211_radiotap_header *)&hdr_buf[0];\n\trtap_hdr->it_version = PKTHDR_RADIOTAP_VERSION;\n\n\t/* tsft */\n\tif (pattrib->tsfl) {\n\t\tu64 tmp_64bit;\n\n\t\trtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_TSFT);\n\t\ttmp_64bit = cpu_to_le64(pattrib->tsfl);\n\t\tmemcpy(&hdr_buf[rt_len], &tmp_64bit, 8);\n\t\trt_len += 8;\n\t}\n\n\t/* flags */\n\trtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_FLAGS);\n\tif (0)\n\t\thdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_CFP;\n\n\tif (0)\n\t\thdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_SHORTPRE;\n\n\tif ((pattrib->encrypt == 1) || (pattrib->encrypt == 5))\n\t\thdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_WEP;\n\n\tif (pattrib->mfrag)\n\t\thdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_FRAG;\n\n\t/* always append FCS */\n\thdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_FCS;\n\n\n\tif (0)\n\t\thdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_DATAPAD;\n\n\tif (pattrib->crc_err)\n\t\thdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_BADFCS;\n\n\tif (pattrib->sgi) {\n\t\t/* Currently unspecified but used */\n\t\thdr_buf[rt_len] |= 0x80;\n\t}\n\trt_len += 1;\n\n\t/* rate */\n\tif (pattrib->data_rate <= DESC_RATE54M) {\n\t\trtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_RATE);\n\t\tif (pattrib->data_rate <= DESC_RATE11M) {\n\t\t\t/* CCK */\n\t\t\thdr_buf[rt_len] = data_rate[pattrib->data_rate];\n\t\t} else {\n\t\t\t/* OFDM */\n\t\t\thdr_buf[rt_len] = data_rate[pattrib->data_rate];\n\t\t}\n\t}\n\trt_len += 1; /* force padding 1 byte for aligned */\n\n\t/* channel */\n\ttmp_16bit = 0;\n\trtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_CHANNEL);\n\ttmp_16bit = CHAN2FREQ(rtw_get_oper_ch(padapter));\n\t/*tmp_16bit = CHAN2FREQ(pHalData->current_channel);*/\n\tmemcpy(&hdr_buf[rt_len], &tmp_16bit, 2);\n\trt_len += 2;\n\n\t/* channel flags */\n\ttmp_16bit = 0;\n\tif (pHalData->current_band_type == 0)\n\t\ttmp_16bit |= cpu_to_le16(IEEE80211_CHAN_2GHZ);\n\telse\n\t\ttmp_16bit |= cpu_to_le16(IEEE80211_CHAN_5GHZ);\n\n\tif (pattrib->data_rate <= DESC_RATE54M) {\n\t\tif (pattrib->data_rate <= DESC_RATE11M) {\n\t\t\t/* CCK */\n\t\t\ttmp_16bit |= cpu_to_le16(IEEE80211_CHAN_CCK);\n\t\t} else {\n\t\t\t/* OFDM */\n\t\t\ttmp_16bit |= cpu_to_le16(IEEE80211_CHAN_OFDM);\n\t\t}\n\t} else\n\t\ttmp_16bit |= cpu_to_le16(IEEE80211_CHAN_DYN);\n\tmemcpy(&hdr_buf[rt_len], &tmp_16bit, 2);\n\trt_len += 2;\n\n\t/* dBm Antenna Signal */\n\trtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL);\n\thdr_buf[rt_len] = pattrib->phy_info.recv_signal_power;\n\trt_len += 1;\n\n#if 0\n\t/* dBm Antenna Noise */\n\trtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE);\n\thdr_buf[rt_len] = 0;\n\trt_len += 1;\n\n\t/* Signal Quality */\n\trtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_LOCK_QUALITY);\n\thdr_buf[rt_len] = pattrib->phy_info.signal_quality;\n\trt_len += 1;\n#endif\n\n\t/* Antenna */\n\trtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_ANTENNA);\n\thdr_buf[rt_len] = 0; /* pHalData->rf_type; */\n\trt_len += 1;\n\n\t/* RX flags */\n\trtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_RX_FLAGS);\n#if 0\n\ttmp_16bit = cpu_to_le16(0);\n\tmemcpy(ptr, &tmp_16bit, 1);\n#endif\n\trt_len += 2;\n\n\t/* MCS information */\n\tif (pattrib->data_rate >= DESC_RATEMCS0 && pattrib->data_rate <= DESC_RATEMCS31) {\n\t\trtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_MCS);\n\t\t/* known, flag */\n\t\thdr_buf[rt_len] |= BIT1; /* MCS index known */\n\n\t\t/* bandwidth */\n\t\thdr_buf[rt_len] |= BIT0;\n\t\thdr_buf[rt_len + 1] |= (pattrib->bw & 0x03);\n\n\t\t/* guard interval */\n\t\thdr_buf[rt_len] |= BIT2;\n\t\thdr_buf[rt_len + 1] |= (pattrib->sgi & 0x01) << 2;\n\n\t\t/* STBC */\n\t\thdr_buf[rt_len] |= BIT5;\n\t\thdr_buf[rt_len + 1] |= (pattrib->stbc & 0x03) << 5;\n\n\t\trt_len += 2;\n\n\t\t/* MCS rate index */\n\t\thdr_buf[rt_len] = data_rate[pattrib->data_rate];\n\t\trt_len += 1;\n\t}\n\n\t/* VHT */\n\tif (pattrib->data_rate >= DESC_RATEVHTSS1MCS0 && pattrib->data_rate <= DESC_RATEVHTSS4MCS9) {\n\t\trtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_VHT);\n\n\t\t/* known 16 bit, flag 8 bit */\n\t\ttmp_16bit = 0;\n\n\t\t/* Bandwidth */\n\t\ttmp_16bit |= BIT6;\n\n\t\t/* Group ID */\n\t\ttmp_16bit |= BIT7;\n\n\t\t/* Partial AID */\n\t\ttmp_16bit |= BIT8;\n\n\t\t/* STBC */\n\t\ttmp_16bit |= BIT0;\n\t\thdr_buf[rt_len + 2] |= (pattrib->stbc & 0x01);\n\n\t\t/* Guard interval */\n\t\ttmp_16bit |= BIT2;\n\t\thdr_buf[rt_len + 2] |= (pattrib->sgi & 0x01) << 2;\n\n\t\t/* LDPC extra OFDM symbol */\n\t\ttmp_16bit |= BIT4;\n\t\thdr_buf[rt_len + 2] |= (pattrib->ldpc & 0x01) << 4;\n\n\t\tmemcpy(&hdr_buf[rt_len], &tmp_16bit, 2);\n\t\trt_len += 3;\n\n\t\t/* bandwidth */\n\t\tif (pattrib->bw == 0)\n\t\t\thdr_buf[rt_len] |= 0;\n\t\telse if (pattrib->bw == 1)\n\t\t\thdr_buf[rt_len] |= 1;\n\t\telse if (pattrib->bw == 2)\n\t\t\thdr_buf[rt_len] |= 4;\n\t\telse if (pattrib->bw == 3)\n\t\t\thdr_buf[rt_len] |= 11;\n\t\trt_len += 1;\n\n\t\t/* mcs_nss */\n\t\tif (pattrib->data_rate >= DESC_RATEVHTSS1MCS0 && pattrib->data_rate <= DESC_RATEVHTSS1MCS9) {\n\t\t\thdr_buf[rt_len] |= 1;\n\t\t\thdr_buf[rt_len] |= data_rate[pattrib->data_rate] << 4;\n\t\t} else if (pattrib->data_rate >= DESC_RATEVHTSS2MCS0 && pattrib->data_rate <= DESC_RATEVHTSS2MCS9) {\n\t\t\thdr_buf[rt_len + 1] |= 2;\n\t\t\thdr_buf[rt_len + 1] |= data_rate[pattrib->data_rate] << 4;\n\t\t} else if (pattrib->data_rate >= DESC_RATEVHTSS3MCS0 && pattrib->data_rate <= DESC_RATEVHTSS3MCS9) {\n\t\t\thdr_buf[rt_len + 2] |= 3;\n\t\t\thdr_buf[rt_len + 2] |= data_rate[pattrib->data_rate] << 4;\n\t\t} else if (pattrib->data_rate >= DESC_RATEVHTSS4MCS0 && pattrib->data_rate <= DESC_RATEVHTSS4MCS9) {\n\t\t\thdr_buf[rt_len + 3] |= 4;\n\t\t\thdr_buf[rt_len + 3] |= data_rate[pattrib->data_rate] << 4;\n\t\t}\n\t\trt_len += 4;\n\n\t\t/* coding */\n\t\thdr_buf[rt_len] = 0;\n\t\trt_len += 1;\n\n\t\t/* group_id */\n\t\thdr_buf[rt_len] = 0;\n\t\trt_len += 1;\n\n\t\t/* partial_aid */\n\t\ttmp_16bit = 0;\n\t\tmemcpy(&hdr_buf[rt_len], &tmp_16bit, 2);\n\t\trt_len += 2;\n\t}\n\n\t/* push to skb */\n\tpskb = (_pkt *)buf;\n\tif (skb_headroom(pskb) < rt_len) {\n\t\tRTW_INFO(\"%s:%d %s headroom is too small.\\n\", __FILE__, __LINE__, __func__);\n\t\tret = _FAIL;\n\t\treturn ret;\n\t}\n\n\tptr = skb_push(pskb, rt_len);\n\tif (ptr) {\n\t\trtap_hdr->it_len = cpu_to_le16(rt_len);\n\t\trtap_hdr->it_present = cpu_to_le32(rtap_hdr->it_present);\n\t\tmemcpy(ptr, rtap_hdr, rt_len);\n\t} else\n\t\tret = _FAIL;\n\n\treturn ret;\n\n}\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))\nint recv_frame_monitor(_adapter *padapter, union recv_frame *rframe)\n{\n\tint ret = _SUCCESS;\n\t_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;\n\t_pkt *pskb = NULL;\n\n\t/* read skb information from recv frame */\n\tpskb = rframe->u.hdr.pkt;\n\tpskb->len = rframe->u.hdr.len;\n\tpskb->data = rframe->u.hdr.rx_data;\n\tskb_set_tail_pointer(pskb, rframe->u.hdr.len);\n\n#ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL\n\t/* fill radiotap header */\n\tif (fill_radiotap_hdr(padapter, rframe, (u8 *)pskb) == _FAIL) {\n\t\tret = _FAIL;\n\t\trtw_free_recvframe(rframe, pfree_recv_queue); /* free this recv_frame */\n\t\tgoto exit;\n\t}\n#endif\n\t/* write skb information to recv frame */\n\tskb_reset_mac_header(pskb);\n\trframe->u.hdr.len = pskb->len;\n\trframe->u.hdr.rx_data = pskb->data;\n\trframe->u.hdr.rx_head = pskb->head;\n\trframe->u.hdr.rx_tail = skb_tail_pointer(pskb);\n\trframe->u.hdr.rx_end = skb_end_pointer(pskb);\n\n\tif (!RTW_CANNOT_RUN(padapter)) {\n\t\t/* indicate this recv_frame */\n\t\tret = rtw_recv_monitor(padapter, rframe);\n\t\tif (ret != _SUCCESS) {\n\t\t\tret = _FAIL;\n\t\t\trtw_free_recvframe(rframe, pfree_recv_queue); /* free this recv_frame */\n\t\t\tgoto exit;\n\t\t}\n\t} else {\n\t\tret = _FAIL;\n\t\trtw_free_recvframe(rframe, pfree_recv_queue); /* free this recv_frame */\n\t\tgoto exit;\n\t}\n\nexit:\n\treturn ret;\n}\n#endif\nint recv_func_prehandle(_adapter *padapter, union recv_frame *rframe)\n{\n\tint ret = _SUCCESS;\n#ifdef DBG_RX_COUNTER_DUMP\n\tstruct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib;\n#endif\n\t_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;\n\n#ifdef DBG_RX_COUNTER_DUMP\n\tif (padapter->dump_rx_cnt_mode & DUMP_DRV_RX_COUNTER) {\n\t\tif (pattrib->crc_err == 1)\n\t\t\tpadapter->drv_rx_cnt_crcerror++;\n\t\telse\n\t\t\tpadapter->drv_rx_cnt_ok++;\n\t}\n#endif\n\n#ifdef CONFIG_MP_INCLUDED\n\tif (padapter->registrypriv.mp_mode == 1 || padapter->mppriv.bRTWSmbCfg == _TRUE) {\n\t\tmp_recv_frame(padapter, rframe);\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t} else\n#endif\n\t{\n\t\t/* check the frame crtl field and decache */\n\t\tret = validate_recv_frame(padapter, rframe);\n\t\tif (ret != _SUCCESS) {\n\t\t\trtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */\n\t\t\tgoto exit;\n\t\t}\n\t}\nexit:\n\treturn ret;\n}\n\n/*#define DBG_RX_BMC_FRAME*/\nint recv_func_posthandle(_adapter *padapter, union recv_frame *prframe)\n{\n\tint ret = _SUCCESS;\n\tunion recv_frame *orig_prframe = prframe;\n\tstruct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;\n\tstruct recv_priv *precvpriv = &padapter->recvpriv;\n\t_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;\n#ifdef CONFIG_TDLS\n\tu8 *psnap_type, *pcategory;\n#endif /* CONFIG_TDLS */\n\n\tDBG_COUNTER(padapter->rx_logs.core_rx_post);\n\n\tprframe = decryptor(padapter, prframe);\n\tif (prframe == NULL) {\n\t\t#ifdef DBG_RX_DROP_FRAME\n\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" decryptor: drop pkt\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter));\n\t\t#endif\n\t\tret = _FAIL;\n\t\tDBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_err);\n\t\tgoto _recv_data_drop;\n\t}\n\n#ifdef DBG_RX_BMC_FRAME\n\tif (IS_MCAST(pattrib->ra))\n\t\tRTW_INFO(\"%s =>\"ADPT_FMT\" Rx BC/MC from \"MAC_FMT\"\\n\", __func__, ADPT_ARG(padapter), MAC_ARG(pattrib->ta));\n#endif\n\n#if 0\n\tif (is_primary_adapter(padapter)) {\n\t\tRTW_INFO(\"+++\\n\");\n\t\t{\n\t\t\tint i;\n\t\t\tu8\t*ptr = get_recvframe_data(prframe);\n\t\t\tfor (i = 0; i < 140; i = i + 8)\n\t\t\t\tRTW_INFO(\"%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\", *(ptr + i),\n\t\t\t\t\t*(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7));\n\n\t\t}\n\t\tRTW_INFO(\"---\\n\");\n\t}\n#endif\n\n#ifdef CONFIG_TDLS\n\t/* check TDLS frame */\n\tpsnap_type = get_recvframe_data(orig_prframe) + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE;\n\tpcategory = psnap_type + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;\n\n\tif ((_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_TDLS, ETH_TYPE_LEN)) &&\n\t    ((*pcategory == RTW_WLAN_CATEGORY_TDLS) || (*pcategory == RTW_WLAN_CATEGORY_P2P))) {\n\t\tret = OnTDLS(padapter, prframe);\n\t\tif (ret == _FAIL)\n\t\t\tgoto _exit_recv_func;\n\t}\n#endif /* CONFIG_TDLS */\n\n\tprframe = recvframe_chk_defrag(padapter, prframe);\n\tif (prframe == NULL)\t{\n\t\t#ifdef DBG_RX_DROP_FRAME\n\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" recvframe_chk_defrag: drop pkt\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter));\n\t\t#endif\n\t\tDBG_COUNTER(padapter->rx_logs.core_rx_post_defrag_err);\n\t\tgoto _recv_data_drop;\n\t}\n\n\tprframe = portctrl(padapter, prframe);\n\tif (prframe == NULL) {\n\t\t#ifdef DBG_RX_DROP_FRAME\n\t\tRTW_INFO(\"DBG_RX_DROP_FRAME \"FUNC_ADPT_FMT\" portctrl: drop pkt\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter));\n\t\t#endif\n\t\tret = _FAIL;\n\t\tDBG_COUNTER(padapter->rx_logs.core_rx_post_portctrl_err);\n\t\tgoto _recv_data_drop;\n\t}\n\n\tcount_rx_stats(padapter, prframe, NULL);\n\n#ifdef CONFIG_WAPI_SUPPORT\n\trtw_wapi_update_info(padapter, prframe);\n#endif\n\n#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)\n\t/* including perform A-MPDU Rx Ordering Buffer Control */\n\tret = recv_indicatepkt_reorder(padapter, prframe);\n\tif (ret == _FAIL) {\n\t\trtw_free_recvframe(orig_prframe, pfree_recv_queue);\n\t\tgoto _recv_data_drop;\n\t} else if (ret == RTW_RX_HANDLED) /* queued OR indicated in order */\n\t\tgoto _exit_recv_func;\n#endif\n\n\trecv_set_iseq_before_mpdu_process(prframe, pattrib->seq_num, __func__);\n\tret = recv_process_mpdu(padapter, prframe);\n\trecv_set_iseq_after_mpdu_process(prframe, pattrib->seq_num, __func__);\n\tif (ret == _FAIL)\n\t\tgoto _recv_data_drop;\n\n_exit_recv_func:\n\treturn ret;\n\n_recv_data_drop:\n\tprecvpriv->dbg_rx_drop_count++;\n\treturn ret;\n}\n\nint recv_func(_adapter *padapter, union recv_frame *rframe)\n{\n\tint ret;\n\tstruct rx_pkt_attrib *prxattrib = &rframe->u.hdr.attrib;\n\tstruct recv_priv *recvpriv = &padapter->recvpriv;\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tstruct mlme_priv *mlmepriv = &padapter->mlmepriv;\n#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL\n\tu8 type;\n\tu8 *ptr = rframe->u.hdr.rx_data;\n#endif\n\tif (check_fwstate(mlmepriv, WIFI_MONITOR_STATE)) {\n\t\t/* monitor mode */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))\n\t\trecv_frame_monitor(padapter, rframe);\n#endif\n\t\tret = _SUCCESS;\n\t\tgoto exit;\n\t} else\n\t\t{}\n#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL\n\ttype = GetFrameType(ptr);\n\tif ((type == WIFI_DATA_TYPE)&& check_fwstate(mlmepriv, WIFI_STATION_STATE)) {\n\t\tstruct wlan_network *cur_network = &(mlmepriv->cur_network);\n\t\tif ( _rtw_memcmp(get_addr2_ptr(ptr), cur_network->network.MacAddress, ETH_ALEN)==0) {\n\t\t\trecv_frame_monitor(padapter, rframe);\n\t\t\tret = _SUCCESS;\n\t\t\tgoto exit;\n\t\t}\n\t}\n#endif\n\t\t/* check if need to handle uc_swdec_pending_queue*/\n\t\tif (check_fwstate(mlmepriv, WIFI_STATION_STATE) && psecuritypriv->busetkipkey) {\n\t\t\tunion recv_frame *pending_frame;\n\t\t\tint cnt = 0;\n\n\t\t\twhile ((pending_frame = rtw_alloc_recvframe(&padapter->recvpriv.uc_swdec_pending_queue))) {\n\t\t\t\tcnt++;\n\t\t\t\tDBG_COUNTER(padapter->rx_logs.core_rx_dequeue);\n\t\t\t\trecv_func_posthandle(padapter, pending_frame);\n\t\t\t}\n\n\t\t\tif (cnt)\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" dequeue %d from uc_swdec_pending_queue\\n\",\n\t\t\t\t\t FUNC_ADPT_ARG(padapter), cnt);\n\t\t}\n\n\tDBG_COUNTER(padapter->rx_logs.core_rx);\n\tret = recv_func_prehandle(padapter, rframe);\n\n\tif (ret == _SUCCESS) {\n\n\t\t/* check if need to enqueue into uc_swdec_pending_queue*/\n\t\tif (check_fwstate(mlmepriv, WIFI_STATION_STATE) &&\n\t\t    !IS_MCAST(prxattrib->ra) && prxattrib->encrypt > 0 &&\n\t\t    (prxattrib->bdecrypted == 0 || psecuritypriv->sw_decrypt == _TRUE) &&\n\t\t    psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPAPSK &&\n\t\t    !psecuritypriv->busetkipkey) {\n\t\t\tDBG_COUNTER(padapter->rx_logs.core_rx_enqueue);\n\t\t\trtw_enqueue_recvframe(rframe, &padapter->recvpriv.uc_swdec_pending_queue);\n\t\t\t/* RTW_INFO(\"%s: no key, enqueue uc_swdec_pending_queue\\n\", __func__); */\n\n\t\t\tif (recvpriv->free_recvframe_cnt < NR_RECVFRAME / 4) {\n\t\t\t\t/* to prevent from recvframe starvation, get recvframe from uc_swdec_pending_queue to free_recvframe_cnt */\n\t\t\t\trframe = rtw_alloc_recvframe(&padapter->recvpriv.uc_swdec_pending_queue);\n\t\t\t\tif (rframe)\n\t\t\t\t\tgoto do_posthandle;\n\t\t\t}\n\t\t\tgoto exit;\n\t\t}\n\ndo_posthandle:\n\t\tret = recv_func_posthandle(padapter, rframe);\n\t}\n\nexit:\n\treturn ret;\n}\n\n\ns32 rtw_recv_entry(union recv_frame *precvframe)\n{\n\t_adapter *padapter;\n\tstruct recv_priv *precvpriv;\n\ts32 ret = _SUCCESS;\n\n\n\n\tpadapter = precvframe->u.hdr.adapter;\n\n\tprecvpriv = &padapter->recvpriv;\n\n\n\tret = recv_func(padapter, precvframe);\n\tif (ret == _FAIL) {\n\t\tgoto _recv_entry_drop;\n\t}\n\n\n\tprecvpriv->rx_pkts++;\n\n\n\treturn ret;\n\n_recv_entry_drop:\n\n#ifdef CONFIG_MP_INCLUDED\n\tif (padapter->registrypriv.mp_mode == 1)\n\t\tpadapter->mppriv.rx_pktloss = precvpriv->rx_drop;\n#endif\n\n\n\n\treturn ret;\n}\n\n#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS\nstatic void rtw_signal_stat_timer_hdl(void *ctx)\n{\n\t_adapter *adapter = (_adapter *)ctx;\n\tstruct recv_priv *recvpriv = &adapter->recvpriv;\n\n\tu32 tmp_s, tmp_q;\n\tu8 avg_signal_strength = 0;\n\tu8 avg_signal_qual = 0;\n\tu32 num_signal_strength = 0;\n\tu32 num_signal_qual = 0;\n\tu8 ratio_pre_stat = 0, ratio_curr_stat = 0, ratio_total = 0, ratio_profile = SIGNAL_STAT_CALC_PROFILE_0;\n\n\tif (adapter->recvpriv.is_signal_dbg) {\n\t\t/* update the user specific value, signal_strength_dbg, to signal_strength, rssi */\n\t\tadapter->recvpriv.signal_strength = adapter->recvpriv.signal_strength_dbg;\n\t\tadapter->recvpriv.rssi = (s8)translate_percentage_to_dbm((u8)adapter->recvpriv.signal_strength_dbg);\n\t} else {\n\n\t\tif (recvpriv->signal_strength_data.update_req == 0) { /* update_req is clear, means we got rx */\n\t\t\tavg_signal_strength = recvpriv->signal_strength_data.avg_val;\n\t\t\tnum_signal_strength = recvpriv->signal_strength_data.total_num;\n\t\t\t/* after avg_vals are accquired, we can re-stat the signal values */\n\t\t\trecvpriv->signal_strength_data.update_req = 1;\n\t\t}\n\n\t\tif (recvpriv->signal_qual_data.update_req == 0) { /* update_req is clear, means we got rx */\n\t\t\tavg_signal_qual = recvpriv->signal_qual_data.avg_val;\n\t\t\tnum_signal_qual = recvpriv->signal_qual_data.total_num;\n\t\t\t/* after avg_vals are accquired, we can re-stat the signal values */\n\t\t\trecvpriv->signal_qual_data.update_req = 1;\n\t\t}\n\n\t\tif (num_signal_strength == 0) {\n\t\t\tif (rtw_get_on_cur_ch_time(adapter) == 0\n\t\t\t    || rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) < 2 * adapter->mlmeextpriv.mlmext_info.bcn_interval\n\t\t\t   )\n\t\t\t\tgoto set_timer;\n\t\t}\n\n\t\tif (check_fwstate(&adapter->mlmepriv, _FW_UNDER_SURVEY) == _TRUE\n\t\t    || check_fwstate(&adapter->mlmepriv, _FW_LINKED) == _FALSE\n\t\t   )\n\t\t\tgoto set_timer;\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_buddy_check_fwstate(adapter, _FW_UNDER_SURVEY) == _TRUE)\n\t\t\tgoto set_timer;\n#endif\n\n\t\tif (RTW_SIGNAL_STATE_CALC_PROFILE < SIGNAL_STAT_CALC_PROFILE_MAX)\n\t\t\tratio_profile = RTW_SIGNAL_STATE_CALC_PROFILE;\n\n\t\tratio_pre_stat = signal_stat_calc_profile[ratio_profile][0];\n\t\tratio_curr_stat = signal_stat_calc_profile[ratio_profile][1];\n\t\tratio_total = ratio_pre_stat + ratio_curr_stat;\n\n\t\t/* update value of signal_strength, rssi, signal_qual */\n\t\ttmp_s = (ratio_curr_stat * avg_signal_strength + ratio_pre_stat * recvpriv->signal_strength);\n\t\tif (tmp_s % ratio_total)\n\t\t\ttmp_s = tmp_s / ratio_total + 1;\n\t\telse\n\t\t\ttmp_s = tmp_s / ratio_total;\n\t\tif (tmp_s > 100)\n\t\t\ttmp_s = 100;\n\n\t\ttmp_q = (ratio_curr_stat * avg_signal_qual + ratio_pre_stat * recvpriv->signal_qual);\n\t\tif (tmp_q % ratio_total)\n\t\t\ttmp_q = tmp_q / ratio_total + 1;\n\t\telse\n\t\t\ttmp_q = tmp_q / ratio_total;\n\t\tif (tmp_q > 100)\n\t\t\ttmp_q = 100;\n\n\t\trecvpriv->signal_strength = tmp_s;\n\t\trecvpriv->rssi = (s8)translate_percentage_to_dbm(tmp_s);\n\t\trecvpriv->signal_qual = tmp_q;\n\n#if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1\n\t\tRTW_INFO(FUNC_ADPT_FMT\" signal_strength:%3u, rssi:%3d, signal_qual:%3u\"\n\t\t\t \", num_signal_strength:%u, num_signal_qual:%u\"\n\t\t\t \", on_cur_ch_ms:%d\"\n\t\t\t \"\\n\"\n\t\t\t , FUNC_ADPT_ARG(adapter)\n\t\t\t , recvpriv->signal_strength\n\t\t\t , recvpriv->rssi\n\t\t\t , recvpriv->signal_qual\n\t\t\t , num_signal_strength, num_signal_qual\n\t\t\t, rtw_get_on_cur_ch_time(adapter) ? rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) : 0\n\t\t\t);\n#endif\n\t}\n\nset_timer:\n\trtw_set_signal_stat_timer(recvpriv);\n\n}\n#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */\n\nstatic void rx_process_rssi(_adapter *padapter, union recv_frame *prframe)\n{\n\tstruct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;\n#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS\n\tstruct signal_stat *signal_stat = &padapter->recvpriv.signal_strength_data;\n#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */\n\tu32 last_rssi, tmp_val;\n#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */\n\n\t/* RTW_INFO(\"process_rssi=> pattrib->rssil(%d) signal_strength(%d)\\n \",pattrib->recv_signal_power,pattrib->signal_strength); */\n\t/* if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon) */\n\t{\n#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS\n\t\tif (signal_stat->update_req) {\n\t\t\tsignal_stat->total_num = 0;\n\t\t\tsignal_stat->total_val = 0;\n\t\t\tsignal_stat->update_req = 0;\n\t\t}\n\n\t\tsignal_stat->total_num++;\n\t\tsignal_stat->total_val  += pattrib->phy_info.signal_strength;\n\t\tsignal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;\n#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */\n\n\t\t/* Adapter->RxStats.RssiCalculateCnt++;\t */ /* For antenna Test */\n\t\tif (padapter->recvpriv.signal_strength_data.total_num++ >= PHY_RSSI_SLID_WIN_MAX) {\n\t\t\tpadapter->recvpriv.signal_strength_data.total_num = PHY_RSSI_SLID_WIN_MAX;\n\t\t\tlast_rssi = padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index];\n\t\t\tpadapter->recvpriv.signal_strength_data.total_val -= last_rssi;\n\t\t}\n\t\tpadapter->recvpriv.signal_strength_data.total_val  += pattrib->phy_info.signal_strength;\n\n\t\tpadapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->phy_info.signal_strength;\n\t\tif (padapter->recvpriv.signal_strength_data.index >= PHY_RSSI_SLID_WIN_MAX)\n\t\t\tpadapter->recvpriv.signal_strength_data.index = 0;\n\n\n\t\ttmp_val = padapter->recvpriv.signal_strength_data.total_val / padapter->recvpriv.signal_strength_data.total_num;\n\n\t\tif (padapter->recvpriv.is_signal_dbg) {\n\t\t\tpadapter->recvpriv.signal_strength = padapter->recvpriv.signal_strength_dbg;\n\t\t\tpadapter->recvpriv.rssi = (s8)translate_percentage_to_dbm(padapter->recvpriv.signal_strength_dbg);\n\t\t} else {\n\t\t\tpadapter->recvpriv.signal_strength = tmp_val;\n\t\t\tpadapter->recvpriv.rssi = (s8)translate_percentage_to_dbm(tmp_val);\n\t\t}\n\n#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */\n\t}\n}\n\nstatic void rx_process_link_qual(_adapter *padapter, union recv_frame *prframe)\n{\n\tstruct rx_pkt_attrib *pattrib;\n#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS\n\tstruct signal_stat *signal_stat;\n#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */\n\tu32 last_evm = 0, tmpVal;\n#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */\n\n\tif (prframe == NULL || padapter == NULL)\n\t\treturn;\n\n\tpattrib = &prframe->u.hdr.attrib;\n#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS\n\tsignal_stat = &padapter->recvpriv.signal_qual_data;\n#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */\n\n\t/* RTW_INFO(\"process_link_qual=> pattrib->signal_qual(%d)\\n \",pattrib->signal_qual); */\n\n#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS\n\tif (signal_stat->update_req) {\n\t\tsignal_stat->total_num = 0;\n\t\tsignal_stat->total_val = 0;\n\t\tsignal_stat->update_req = 0;\n\t}\n\n\tsignal_stat->total_num++;\n\tsignal_stat->total_val  += pattrib->phy_info.signal_quality;\n\tsignal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;\n\n#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */\n\tif (pattrib->phy_info.signal_quality != 0) {\n\t\t/*  */\n\t\t/* 1. Record the general EVM to the sliding window. */\n\t\t/*  */\n\t\tif (padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) {\n\t\t\tpadapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX;\n\t\t\tlast_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index];\n\t\t\tpadapter->recvpriv.signal_qual_data.total_val -= last_evm;\n\t\t}\n\t\tpadapter->recvpriv.signal_qual_data.total_val += pattrib->phy_info.signal_quality;\n\n\t\tpadapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->phy_info.signal_quality;\n\t\tif (padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX)\n\t\t\tpadapter->recvpriv.signal_qual_data.index = 0;\n\n\n\t\t/* <1> Showed on UI for user, in percentage. */\n\t\ttmpVal = padapter->recvpriv.signal_qual_data.total_val / padapter->recvpriv.signal_qual_data.total_num;\n\t\tpadapter->recvpriv.signal_qual = (u8)tmpVal;\n\n\t}\n#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */\n}\n\nvoid rx_process_phy_info(_adapter *padapter, union recv_frame *rframe)\n{\n\t/* Check RSSI */\n\trx_process_rssi(padapter, rframe);\n\n\t/* Check PWDB */\n\t/* process_PWDB(padapter, rframe); */\n\n\t/* UpdateRxSignalStatistics8192C(Adapter, pRfd); */\n\n\t/* Check EVM */\n\trx_process_link_qual(padapter, rframe);\n\trtw_store_phy_info(padapter, rframe);\n}\n\nvoid rx_query_phy_status(\n\tunion recv_frame\t*precvframe,\n\tu8 *pphy_status)\n{\n\tPADAPTER\t\t\tpadapter = precvframe->u.hdr.adapter;\n\tstruct rx_pkt_attrib\t*pattrib = &precvframe->u.hdr.attrib;\n\tHAL_DATA_TYPE\t\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct phydm_phyinfo_struct *p_phy_info = &pattrib->phy_info;\n\tu8\t\t\t\t\t*wlanhdr;\n\tstruct phydm_perpkt_info_struct pkt_info;\n\tu8 *ta, *ra;\n\tu8 is_ra_bmc;\n\tstruct sta_priv *pstapriv;\n\tstruct sta_info *psta = NULL;\n\tstruct recv_priv  *precvpriv = &padapter->recvpriv;\n\t/* _irqL\t\tirqL; */\n\n\tpkt_info.is_packet_match_bssid = _FALSE;\n\tpkt_info.is_packet_to_self = _FALSE;\n\tpkt_info.is_packet_beacon = _FALSE;\n\tpkt_info.ppdu_cnt = pattrib->ppdu_cnt;\n\tpkt_info.station_id = 0xFF;\n\n\twlanhdr = get_recvframe_data(precvframe);\n\n\tta = get_ta(wlanhdr);\n\tra = get_ra(wlanhdr);\n\tis_ra_bmc = IS_MCAST(ra);\n\n\tif (_rtw_memcmp(adapter_mac_addr(padapter), ta, ETH_ALEN) == _TRUE) {\n\t\tstatic systime start_time = 0;\n\n#if 0 /*For debug */\n\t\tif (IsFrameTypeCtrl(wlanhdr)) {\n\t\t\tRTW_INFO(\"-->Control frame: Y\\n\");\n\t\t\tRTW_INFO(\"-->pkt_len: %d\\n\", pattrib->pkt_len);\n\t\t\tRTW_INFO(\"-->Sub Type = 0x%X\\n\", get_frame_sub_type(wlanhdr));\n\t\t}\n\n\t\t/* Dump first 40 bytes of header */\n\t\tint i = 0;\n\n\t\tfor (i = 0; i < 40; i++)\n\t\t\tRTW_INFO(\"%d: %X\\n\", i, *((u8 *)wlanhdr + i));\n\n\t\tRTW_INFO(\"\\n\");\n#endif\n\n\t\tif ((start_time == 0) || (rtw_get_passing_time_ms(start_time) > 5000)) {\n\t\t\tRTW_PRINT(\"Warning!!! %s: Confilc mac addr!!\\n\", __func__);\n\t\t\tstart_time = rtw_get_current_time();\n\t\t}\n\t\tprecvpriv->dbg_rx_conflic_mac_addr_cnt++;\n\t} else {\n\t\tpstapriv = &padapter->stapriv;\n\t\tpsta = rtw_get_stainfo(pstapriv, ta);\n\t\tif (psta)\n\t\t\tpkt_info.station_id = psta->cmn.mac_id;\n\t}\n\n\tpkt_info.is_packet_match_bssid = (!IsFrameTypeCtrl(wlanhdr))\n\t\t&& (!pattrib->icv_err) && (!pattrib->crc_err)\n\t\t&& ((!MLME_IS_MESH(padapter) && _rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN))\n\t\t\t|| (MLME_IS_MESH(padapter) && psta));\n\n\tpkt_info.is_to_self = (!pattrib->icv_err) && (!pattrib->crc_err)\n\t\t&& _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN);\n\n\tpkt_info.is_packet_to_self = pkt_info.is_packet_match_bssid\n\t\t&& _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN);\n\n\tpkt_info.is_packet_beacon = pkt_info.is_packet_match_bssid\n\t\t\t\t && (get_frame_sub_type(wlanhdr) == WIFI_BEACON);\n\n\tif (psta && IsFrameTypeData(wlanhdr)) {\n\t\tif (is_ra_bmc)\n\t\t\tpsta->curr_rx_rate_bmc = pattrib->data_rate;\n\t\telse\n\t\t\tpsta->curr_rx_rate = pattrib->data_rate;\n\t}\n\tpkt_info.data_rate = pattrib->data_rate;\n\n\todm_phy_status_query(&pHalData->odmpriv, p_phy_info, pphy_status, &pkt_info);\n\n\t/* If bw is initial value, get from phy status */\n\tif (pattrib->bw == CHANNEL_WIDTH_MAX)\n\t\tpattrib->bw = p_phy_info->band_width;\n\n\t{\n\t\tprecvframe->u.hdr.psta = NULL;\n\t\tif (padapter->registrypriv.mp_mode != 1) {\n\t\t\tif ((!MLME_IS_MESH(padapter) && pkt_info.is_packet_match_bssid)\n\t\t\t\t|| (MLME_IS_MESH(padapter) && psta)) {\n\t\t\t\tif (psta) {\n\t\t\t\t\tprecvframe->u.hdr.psta = psta;\n\t\t\t\t\trx_process_phy_info(padapter, precvframe);\n\t\t\t\t}\n\t\t\t} else if (pkt_info.is_packet_to_self || pkt_info.is_packet_beacon) {\n\t\t\t\tif (psta)\n\t\t\t\t\tprecvframe->u.hdr.psta = psta;\n\t\t\t\trx_process_phy_info(padapter, precvframe);\n\t\t\t}\n\t\t} else {\n#ifdef CONFIG_MP_INCLUDED\n\t\t\tif (padapter->mppriv.brx_filter_beacon == _TRUE) {\n\t\t\t\tif (pkt_info.is_packet_beacon) {\n\t\t\t\t\tRTW_INFO(\"in MP Rx is_packet_beacon\\n\");\n\t\t\t\t\tif (psta)\n\t\t\t\t\t\tprecvframe->u.hdr.psta = psta;\n\t\t\t\t\trx_process_phy_info(padapter, precvframe);\n\t\t\t\t}\n\t\t\t} else \n#endif\n\t\t\t{\n\t\t\t\t\tif (psta)\n\t\t\t\t\t\tprecvframe->u.hdr.psta = psta;\n\t\t\t\t\trx_process_phy_info(padapter, precvframe);\n\t\t\t}\n\t\t}\n\t}\n\n\trtw_odm_parse_rx_phy_status_chinfo(precvframe, pphy_status);\n}\n/*\n* Increase and check if the continual_no_rx_packet of this @param pmlmepriv is larger than MAX_CONTINUAL_NORXPACKET_COUNT\n* @return _TRUE:\n* @return _FALSE:\n*/\nint rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index)\n{\n\n\tint ret = _FALSE;\n\tint value = ATOMIC_INC_RETURN(&sta->continual_no_rx_packet[tid_index]);\n\n\tif (value >= MAX_CONTINUAL_NORXPACKET_COUNT)\n\t\tret = _TRUE;\n\n\treturn ret;\n}\n\n/*\n* Set the continual_no_rx_packet of this @param pmlmepriv to 0\n*/\nvoid rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index)\n{\n\tATOMIC_SET(&sta->continual_no_rx_packet[tid_index], 0);\n}\n\nu8 adapter_allow_bmc_data_rx(_adapter *adapter)\n{\n\tif (check_fwstate(&adapter->mlmepriv, WIFI_MONITOR_STATE | WIFI_MP_STATE) == _TRUE)\n\t\treturn 1;\n\n\tif (MLME_IS_AP(adapter))\n\t\treturn 0;\n\n\tif (rtw_linked_check(adapter) == _FALSE)\n\t\treturn 0;\n\n\treturn 1;\n}\n\ns32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status)\n{\n\ts32 ret = _SUCCESS;\n\tu8 *pbuf = precvframe->u.hdr.rx_data;\n\tu8 *pda = get_ra(pbuf);\n\tu8 ra_is_bmc = IS_MCAST(pda);\n\t_adapter *primary_padapter = precvframe->u.hdr.adapter;\n#ifdef CONFIG_CONCURRENT_MODE\n\t_adapter *iface = NULL;\n\n\t#ifdef CONFIG_MP_INCLUDED\n\tif (rtw_mp_mode_check(primary_padapter))\n\t\tgoto bypass_concurrent_hdl;\n\t#endif\n\n\tif (ra_is_bmc == _FALSE) { /*unicast packets*/\n\t\tiface = rtw_get_iface_by_macddr(primary_padapter , pda);\n\t\tif (NULL == iface) {\n\t\t#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI\n\t\t\tif (_rtw_memcmp(pda, adapter_pno_mac_addr(primary_padapter),\n\t\t\t\t\tETH_ALEN) != _TRUE)\n\t\t#endif\n\t\t\tRTW_INFO(\"%s [WARN] Cannot find appropriate adapter - mac_addr : \"MAC_FMT\"\\n\", __func__, MAC_ARG(pda));\n\t\t\t/*rtw_warn_on(1);*/\n\t\t} else\n\t\t\tprecvframe->u.hdr.adapter = iface;\n\t} else   /* Handle BC/MC Packets\t*/\n\t\trtw_mi_buddy_clone_bcmc_packet(primary_padapter, precvframe, pphy_status);\nbypass_concurrent_hdl:\n#endif /* CONFIG_CONCURRENT_MODE */\n\tif (primary_padapter->registrypriv.mp_mode != 1) {\n\t\t/* skip unnecessary bmc data frame for primary adapter */\n\t\tif (ra_is_bmc == _TRUE && GetFrameType(pbuf) == WIFI_DATA_TYPE\n\t\t\t&& !adapter_allow_bmc_data_rx(precvframe->u.hdr.adapter)\n\t\t) {\n\t\t\trtw_free_recvframe(precvframe, &precvframe->u.hdr.adapter->recvpriv.free_recv_queue);\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\tif (pphy_status)\n\t\trx_query_phy_status(precvframe, pphy_status);\n\tret = rtw_recv_entry(precvframe);\n\nexit:\n\treturn ret;\n}\n\n#ifdef CONFIG_RECV_THREAD_MODE\nthread_return rtw_recv_thread(thread_context context)\n{\n\t_adapter *adapter = (_adapter *)context;\n\tstruct recv_priv *recvpriv = &adapter->recvpriv;\n\ts32 err = _SUCCESS;\n#ifdef RTW_RECV_THREAD_HIGH_PRIORITY\n#ifdef PLATFORM_LINUX\n\tstruct sched_param param = { .sched_priority = 1 };\n\n\tsched_setscheduler(current, SCHED_FIFO, &param);\n#endif /* PLATFORM_LINUX */\n#endif /*RTW_RECV_THREAD_HIGH_PRIORITY*/\n\tthread_enter(\"RTW_RECV_THREAD\");\n\n\tRTW_INFO(FUNC_ADPT_FMT\" enter\\n\", FUNC_ADPT_ARG(adapter));\n\n\tdo {\n\t\terr = _rtw_down_sema(&recvpriv->recv_sema);\n\t\tif (_FAIL == err) {\n\t\t\tRTW_ERR(FUNC_ADPT_FMT\" down recv_sema fail!\\n\", FUNC_ADPT_ARG(adapter));\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (RTW_CANNOT_RUN(adapter)) {\n\t\t\tRTW_DBG(FUNC_ADPT_FMT \"- bDriverStopped(%s) bSurpriseRemoved(%s)\\n\",\n\t\t\t\tFUNC_ADPT_ARG(adapter),\n\t\t\t\trtw_is_drv_stopped(adapter) ? \"True\" : \"False\",\n\t\t\t\trtw_is_surprise_removed(adapter) ? \"True\" : \"False\");\n\t\t\tgoto exit;\n\t\t}\n\n\t\terr = rtw_hal_recv_hdl(adapter);\n\n\t\tif (err == RTW_RFRAME_UNAVAIL\n\t\t\t|| err == RTW_RFRAME_PKT_UNAVAIL\n\t\t) {\n\t\t\trtw_msleep_os(1);\n\t\t\t_rtw_up_sema(&recvpriv->recv_sema);\n\t\t}\n\n\t\tflush_signals_thread();\n\n\t} while (err != _FAIL);\n\nexit:\n\n\tRTW_INFO(FUNC_ADPT_FMT \" Exit\\n\", FUNC_ADPT_ARG(adapter));\n\n\trtw_thread_wait_stop();\n\n\treturn 0;\n}\n#endif /* CONFIG_RECV_THREAD_MODE */\n\n#if DBG_RX_BH_TRACKING\nvoid rx_bh_tk_set_stage(struct recv_priv *recv, u32 s)\n{\n\trecv->rx_bh_stage = s;\n}\n\nvoid rx_bh_tk_set_buf(struct recv_priv *recv, void *buf, void *data, u32 dlen)\n{\n\tif (recv->rx_bh_cbuf)\n\t\trecv->rx_bh_lbuf = recv->rx_bh_cbuf;\n\trecv->rx_bh_cbuf = buf;\n\tif (buf) {\n\t\trecv->rx_bh_cbuf_data = data;\n\t\trecv->rx_bh_cbuf_dlen = dlen;\n\t\trecv->rx_bh_buf_dq_cnt++;\n\t} else {\n\t\trecv->rx_bh_cbuf_data = NULL;\n\t\trecv->rx_bh_cbuf_dlen = 0;\n\t}\n}\n\nvoid rx_bh_tk_set_buf_pos(struct recv_priv *recv, void *pos)\n{\n\tif (recv->rx_bh_cbuf) {\n\t\trecv->rx_bh_cbuf_pos = pos - recv->rx_bh_cbuf_data;\n\t} else {\n\t\trtw_warn_on(1);\n\t\trecv->rx_bh_cbuf_pos = 0;\n\t}\n}\n\nvoid rx_bh_tk_set_frame(struct recv_priv *recv, void *frame)\n{\n\trecv->rx_bh_cframe = frame;\n}\n\nvoid dump_rx_bh_tk(void *sel, struct recv_priv *recv)\n{\n\tRTW_PRINT_SEL(sel, \"[RXBHTK]s:%u, buf_dqc:%u, lbuf:%p, cbuf:%p, dlen:%u, pos:%u, cframe:%p\\n\"\n\t\t, recv->rx_bh_stage\n\t\t, recv->rx_bh_buf_dq_cnt\n\t\t, recv->rx_bh_lbuf\n\t\t, recv->rx_bh_cbuf\n\t\t, recv->rx_bh_cbuf_dlen\n\t\t, recv->rx_bh_cbuf_pos\n\t\t, recv->rx_bh_cframe\n\t);\n}\n#endif /* DBG_RX_BH_TRACKING */\n\n"
  },
  {
    "path": "core/rtw_rf.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_RF_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\nu8 center_ch_2g[CENTER_CH_2G_NUM] = {\n/* G00 */1, 2,\n/* G01 */3, 4, 5,\n/* G02 */6, 7, 8,\n/* G03 */9, 10, 11,\n/* G04 */12, 13,\n/* G05 */14\n};\n\nu8 center_ch_2g_40m[CENTER_CH_2G_40M_NUM] = {\n\t3,\n\t4,\n\t5,\n\t6,\n\t7,\n\t8,\n\t9,\n\t10,\n\t11,\n};\n\nu8 op_chs_of_cch_2g_40m[CENTER_CH_2G_40M_NUM][2] = {\n\t{1, 5}, /* 3 */\n\t{2, 6}, /* 4 */\n\t{3, 7}, /* 5 */\n\t{4, 8}, /* 6 */\n\t{5, 9}, /* 7 */\n\t{6, 10}, /* 8 */\n\t{7, 11}, /* 9 */\n\t{8, 12}, /* 10 */\n\t{9, 13}, /* 11 */\n};\n\nu8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM] = {\n/* G00 */36, 38, 40,\n\t42,\n/* G01 */44, 46, 48,\n\t/* 50, */\n/* G02 */52, 54, 56,\n\t58,\n/* G03 */60, 62, 64,\n/* G04 */100, 102, 104,\n\t106,\n/* G05 */108, 110, 112,\n\t/* 114, */\n/* G06 */116, 118, 120,\n\t122,\n/* G07 */124, 126, 128,\n/* G08 */132, 134, 136,\n\t138,\n/* G09 */140, 142, 144,\n/* G10 */149, 151, 153,\n\t155,\n/* G11 */157, 159, 161,\n\t/* 163, */\n/* G12 */165, 167, 169,\n\t171,\n/* G13 */173, 175, 177\n};\n\nu8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM] = {\n/* G00 */36, 40,\n/* G01 */44, 48,\n/* G02 */52, 56,\n/* G03 */60, 64,\n/* G04 */100, 104,\n/* G05 */108, 112,\n/* G06 */116, 120,\n/* G07 */124, 128,\n/* G08 */132, 136,\n/* G09 */140, 144,\n/* G10 */149, 153,\n/* G11 */157, 161,\n/* G12 */165, 169,\n/* G13 */173, 177\n};\n\nu8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM] = {\n/* G00 */38,\n/* G01 */46,\n/* G02 */54,\n/* G03 */62,\n/* G04 */102,\n/* G05 */110,\n/* G06 */118,\n/* G07 */126,\n/* G08 */134,\n/* G09 */142,\n/* G10 */151,\n/* G11 */159,\n/* G12 */167,\n/* G13 */175\n};\n\nu8 center_ch_5g_20m_40m[CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM] = {\n/* G00 */36, 38, 40,\n/* G01 */44, 46, 48,\n/* G02 */52, 54, 56,\n/* G03 */60, 62, 64,\n/* G04 */100, 102, 104,\n/* G05 */108, 110, 112,\n/* G06 */116, 118, 120,\n/* G07 */124, 126, 128,\n/* G08 */132, 134, 136,\n/* G09 */140, 142, 144,\n/* G10 */149, 151, 153,\n/* G11 */157, 159, 161,\n/* G12 */165, 167, 169,\n/* G13 */173, 175, 177\n};\n\nu8 op_chs_of_cch_5g_40m[CENTER_CH_5G_40M_NUM][2] = {\n\t{36, 40}, /* 38 */\n\t{44, 48}, /* 46 */\n\t{52, 56}, /* 54 */\n\t{60, 64}, /* 62 */\n\t{100, 104}, /* 102 */\n\t{108, 112}, /* 110 */\n\t{116, 120}, /* 118 */\n\t{124, 128}, /* 126 */\n\t{132, 136}, /* 134 */\n\t{140, 144}, /* 142 */\n\t{149, 153}, /* 151 */\n\t{157, 161}, /* 159 */\n\t{165, 169}, /* 167 */\n\t{173, 177}, /* 175 */\n};\n\nu8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM] = {\n/* G00 ~ G01*/42,\n/* G02 ~ G03*/58,\n/* G04 ~ G05*/106,\n/* G06 ~ G07*/122,\n/* G08 ~ G09*/138,\n/* G10 ~ G11*/155,\n/* G12 ~ G13*/171\n};\n\nu8 op_chs_of_cch_5g_80m[CENTER_CH_5G_80M_NUM][4] = {\n\t{36, 40, 44, 48}, /* 42 */\n\t{52, 56, 60, 64}, /* 58 */\n\t{100, 104, 108, 112}, /* 106 */\n\t{116, 120, 124, 128}, /* 122 */\n\t{132, 136, 140, 144}, /* 138 */\n\t{149, 153, 157, 161}, /* 155 */\n\t{165, 169, 173, 177}, /* 171 */\n};\n\nu8 center_ch_5g_160m[CENTER_CH_5G_160M_NUM] = {\n/* G00 ~ G03*/50,\n/* G04 ~ G07*/114,\n/* G10 ~ G13*/163\n};\n\nu8 op_chs_of_cch_5g_160m[CENTER_CH_5G_160M_NUM][8] = {\n\t{36, 40, 44, 48, 52, 56, 60, 64}, /* 50 */\n\t{100, 104, 108, 112, 116, 120, 124, 128}, /* 114 */\n\t{149, 153, 157, 161, 165, 169, 173, 177}, /* 163 */\n};\n\nstruct center_chs_ent_t {\n\tu8 ch_num;\n\tu8 *chs;\n};\n\nstruct center_chs_ent_t center_chs_2g_by_bw[] = {\n\t{CENTER_CH_2G_NUM, center_ch_2g},\n\t{CENTER_CH_2G_40M_NUM, center_ch_2g_40m},\n};\n\nstruct center_chs_ent_t center_chs_5g_by_bw[] = {\n\t{CENTER_CH_5G_20M_NUM, center_ch_5g_20m},\n\t{CENTER_CH_5G_40M_NUM, center_ch_5g_40m},\n\t{CENTER_CH_5G_80M_NUM, center_ch_5g_80m},\n\t{CENTER_CH_5G_160M_NUM, center_ch_5g_160m},\n};\n\n/*\n * Get center channel of smaller bandwidth by @param cch, @param bw, @param offset\n * @cch: the given center channel\n * @bw: the given bandwidth\n * @offset: the given primary SC offset of the given bandwidth\n *\n * return center channel of smaller bandiwdth if valid, or 0\n */\nu8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset)\n{\n\tu8 t_cch = 0;\n\n\tif (bw == CHANNEL_WIDTH_20) {\n\t\tt_cch = cch;\n\t\tgoto exit;\n\t}\n\n\tif (offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\t/* 2.4G, 40MHz */\n\tif (cch >= 3 && cch <= 11 && bw == CHANNEL_WIDTH_40) {\n\t\tt_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2;\n\t\tgoto exit;\n\t}\n\n\t/* 5G, 160MHz */\n\tif (cch >= 50 && cch <= 163 && bw == CHANNEL_WIDTH_160) {\n\t\tt_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 8 : cch - 8;\n\t\tgoto exit;\n\n\t/* 5G, 80MHz */\n\t} else if (cch >= 42 && cch <= 171 && bw == CHANNEL_WIDTH_80) {\n\t\tt_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 4 : cch - 4;\n\t\tgoto exit;\n\n\t/* 5G, 40MHz */\n\t} else if (cch >= 38 && cch <= 175 && bw == CHANNEL_WIDTH_40) {\n\t\tt_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2;\n\t\tgoto exit;\n\n\t} else {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\nexit:\n\treturn t_cch;\n}\n\nstruct op_chs_ent_t {\n\tu8 ch_num;\n\tu8 *chs;\n};\n\nstruct op_chs_ent_t op_chs_of_cch_2g_by_bw[] = {\n\t{1, center_ch_2g},\n\t{2, (u8 *)op_chs_of_cch_2g_40m},\n};\n\nstruct op_chs_ent_t op_chs_of_cch_5g_by_bw[] = {\n\t{1, center_ch_5g_20m},\n\t{2, (u8 *)op_chs_of_cch_5g_40m},\n\t{4, (u8 *)op_chs_of_cch_5g_80m},\n\t{8, (u8 *)op_chs_of_cch_5g_160m},\n};\n\ninline u8 center_chs_2g_num(u8 bw)\n{\n\tif (bw > CHANNEL_WIDTH_40)\n\t\treturn 0;\n\n\treturn center_chs_2g_by_bw[bw].ch_num;\n}\n\ninline u8 center_chs_2g(u8 bw, u8 id)\n{\n\tif (bw > CHANNEL_WIDTH_40)\n\t\treturn 0;\n\n\tif (id >= center_chs_2g_num(bw))\n\t\treturn 0;\n\n\treturn center_chs_2g_by_bw[bw].chs[id];\n}\n\ninline u8 center_chs_5g_num(u8 bw)\n{\n\tif (bw > CHANNEL_WIDTH_80)\n\t\treturn 0;\n\n\treturn center_chs_5g_by_bw[bw].ch_num;\n}\n\ninline u8 center_chs_5g(u8 bw, u8 id)\n{\n\tif (bw > CHANNEL_WIDTH_80)\n\t\treturn 0;\n\n\tif (id >= center_chs_5g_num(bw))\n\t\treturn 0;\n\n\treturn center_chs_5g_by_bw[bw].chs[id];\n}\n\n/*\n * Get available op channels by @param cch, @param bw\n * @cch: the given center channel\n * @bw: the given bandwidth\n * @op_chs: the pointer to return pointer of op channel array\n * @op_ch_num: the pointer to return pointer of op channel number\n *\n * return valid (1) or not (0)\n */\nu8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num)\n{\n\tint i;\n\tstruct center_chs_ent_t *c_chs_ent = NULL;\n\tstruct op_chs_ent_t *op_chs_ent = NULL;\n\tu8 valid = 1;\n\n\tif (cch <= 14\n\t\t&& bw >= CHANNEL_WIDTH_20 && bw <= CHANNEL_WIDTH_40\n\t) {\n\t\tc_chs_ent = &center_chs_2g_by_bw[bw];\n\t\top_chs_ent = &op_chs_of_cch_2g_by_bw[bw];\n\t} else if (cch >= 36 && cch <= 177\n\t\t&& bw >= CHANNEL_WIDTH_20 && bw <= CHANNEL_WIDTH_160\n\t) {\n\t\tc_chs_ent = &center_chs_5g_by_bw[bw];\n\t\top_chs_ent = &op_chs_of_cch_5g_by_bw[bw];\n\t} else {\n\t\tvalid = 0;\n\t\tgoto exit;\n\t}\n\n\tfor (i = 0; i < c_chs_ent->ch_num; i++)\n\t\tif (cch == *(c_chs_ent->chs + i))\n\t\t\tbreak;\n\n\tif (i == c_chs_ent->ch_num) {\n\t\tvalid = 0;\n\t\tgoto exit;\n\t}\n\n\t*op_chs = op_chs_ent->chs + op_chs_ent->ch_num * i;\n\t*op_ch_num = op_chs_ent->ch_num;\n\nexit:\n\treturn valid;\n}\n\nu8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group)\n{\n\tBAND_TYPE band = BAND_MAX;\n\ts8 gp = -1, cck_gp = -1;\n\n\tif (ch <= 14) {\n\t\tband = BAND_ON_2_4G;\n\n\t\tif (1 <= ch && ch <= 2)\n\t\t\tgp = 0;\n\t\telse if (3  <= ch && ch <= 5)\n\t\t\tgp = 1;\n\t\telse if (6  <= ch && ch <= 8)\n\t\t\tgp = 2;\n\t\telse if (9  <= ch && ch <= 11)\n\t\t\tgp = 3;\n\t\telse if (12 <= ch && ch <= 14)\n\t\t\tgp = 4;\n\t\telse\n\t\t\tband = BAND_MAX;\n\n\t\tif (ch == 14)\n\t\t\tcck_gp = 5;\n\t\telse\n\t\t\tcck_gp = gp;\n\t} else {\n\t\tband = BAND_ON_5G;\n\n\t\tif (36 <= ch && ch <= 42)\n\t\t\tgp = 0;\n\t\telse if (44   <= ch && ch <=  48)\n\t\t\tgp = 1;\n\t\telse if (50   <= ch && ch <=  58)\n\t\t\tgp = 2;\n\t\telse if (60   <= ch && ch <=  64)\n\t\t\tgp = 3;\n\t\telse if (100  <= ch && ch <= 106)\n\t\t\tgp = 4;\n\t\telse if (108  <= ch && ch <= 114)\n\t\t\tgp = 5;\n\t\telse if (116  <= ch && ch <= 122)\n\t\t\tgp = 6;\n\t\telse if (124  <= ch && ch <= 130)\n\t\t\tgp = 7;\n\t\telse if (132  <= ch && ch <= 138)\n\t\t\tgp = 8;\n\t\telse if (140  <= ch && ch <= 144)\n\t\t\tgp = 9;\n\t\telse if (149  <= ch && ch <= 155)\n\t\t\tgp = 10;\n\t\telse if (157  <= ch && ch <= 161)\n\t\t\tgp = 11;\n\t\telse if (165  <= ch && ch <= 171)\n\t\t\tgp = 12;\n\t\telse if (173  <= ch && ch <= 177)\n\t\t\tgp = 13;\n\t\telse\n\t\t\tband = BAND_MAX;\n\t}\n\n\tif (band == BAND_MAX\n\t\t|| (band == BAND_ON_2_4G && cck_gp == -1)\n\t\t|| gp == -1\n\t) {\n\t\tRTW_WARN(\"%s invalid channel:%u\", __func__, ch);\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (group)\n\t\t*group = gp;\n\tif (cck_group && band == BAND_ON_2_4G)\n\t\t*cck_group = cck_gp;\n\nexit:\n\treturn band;\n}\n\nint rtw_ch2freq(int chan)\n{\n\t/* see 802.11 17.3.8.3.2 and Annex J\n\t* there are overlapping channel numbers in 5GHz and 2GHz bands */\n\n\t/*\n\t* RTK: don't consider the overlapping channel numbers: 5G channel <= 14,\n\t* because we don't support it. simply judge from channel number\n\t*/\n\n\tif (chan >= 1 && chan <= 14) {\n\t\tif (chan == 14)\n\t\t\treturn 2484;\n\t\telse if (chan < 14)\n\t\t\treturn 2407 + chan * 5;\n\t} else if (chan >= 36 && chan <= 177)\n\t\treturn 5000 + chan * 5;\n\n\treturn 0; /* not supported */\n}\n\nint rtw_freq2ch(int freq)\n{\n\t/* see 802.11 17.3.8.3.2 and Annex J */\n\tif (freq == 2484)\n\t\treturn 14;\n\telse if (freq < 2484)\n\t\treturn (freq - 2407) / 5;\n\telse if (freq >= 4910 && freq <= 4980)\n\t\treturn (freq - 4000) / 5;\n\telse if (freq <= 45000) /* DMG band lower limit */\n\t\treturn (freq - 5000) / 5;\n\telse if (freq >= 58320 && freq <= 64800)\n\t\treturn (freq - 56160) / 2160;\n\telse\n\t\treturn 0;\n}\n\nbool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo)\n{\n\tu8 c_ch;\n\tu32 freq;\n\tu32 hi_ret = 0, lo_ret = 0;\n\tbool valid = _FALSE;\n\n\tif (hi)\n\t\t*hi = 0;\n\tif (lo)\n\t\t*lo = 0;\n\n\tc_ch = rtw_get_center_ch(ch, bw, offset);\n\tfreq = rtw_ch2freq(c_ch);\n\n\tif (!freq) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (bw == CHANNEL_WIDTH_80) {\n\t\thi_ret = freq + 40;\n\t\tlo_ret = freq - 40;\n\t} else if (bw == CHANNEL_WIDTH_40) {\n\t\thi_ret = freq + 20;\n\t\tlo_ret = freq - 20;\n\t} else if (bw == CHANNEL_WIDTH_20) {\n\t\thi_ret = freq + 10;\n\t\tlo_ret = freq - 10;\n\t} else\n\t\trtw_warn_on(1);\n\n\tif (hi)\n\t\t*hi = hi_ret;\n\tif (lo)\n\t\t*lo = lo_ret;\n\n\tvalid = _TRUE;\n\nexit:\n\treturn valid;\n}\n\nconst char *const _ch_width_str[CHANNEL_WIDTH_MAX] = {\n\t\"20MHz\",\n\t\"40MHz\",\n\t\"80MHz\",\n\t\"160MHz\",\n\t\"80_80MHz\",\n\t\"5MHz\",\n\t\"10MHz\",\n};\n\nconst u8 _ch_width_to_bw_cap[CHANNEL_WIDTH_MAX] = {\n\tBW_CAP_20M,\n\tBW_CAP_40M,\n\tBW_CAP_80M,\n\tBW_CAP_160M,\n\tBW_CAP_80_80M,\n\tBW_CAP_5M,\n\tBW_CAP_10M,\n};\n\nconst char *const _band_str[] = {\n\t\"2.4G\",\n\t\"5G\",\n\t\"BOTH\",\n\t\"BAND_MAX\",\n};\n\nconst u8 _band_to_band_cap[] = {\n\tBAND_CAP_2G,\n\tBAND_CAP_5G,\n\t0,\n\t0,\n};\n\nconst u8 _rf_type_to_rf_tx_cnt[] = {\n\t1, /*RF_1T1R*/\n\t1, /*RF_1T2R*/\n\t2, /*RF_2T2R*/\n\t2, /*RF_2T3R*/\n\t2, /*RF_2T4R*/\n\t3, /*RF_3T3R*/\n\t3, /*RF_3T4R*/\n\t4, /*RF_4T4R*/\n\t1, /*RF_TYPE_MAX*/\n};\n\nconst u8 _rf_type_to_rf_rx_cnt[] = {\n\t1, /*RF_1T1R*/\n\t2, /*RF_1T2R*/\n\t2, /*RF_2T2R*/\n\t3, /*RF_2T3R*/\n\t4, /*RF_2T4R*/\n\t3, /*RF_3T3R*/\n\t4, /*RF_3T4R*/\n\t4, /*RF_4T4R*/\n\t1, /*RF_TYPE_MAX*/\n};\n\nconst char *const _regd_str[] = {\n\t\"NONE\",\n\t\"FCC\",\n\t\"MKK\",\n\t\"ETSI\",\n\t\"IC\",\n\t\"KCC\",\n\t\"ACMA\",\n\t\"CHILE\",\n\t\"MEXICO\",\n\t\"WW\",\n};\n\n#if CONFIG_TXPWR_LIMIT\nvoid _dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl)\n{\n\tstruct regd_exc_ent *ent;\n\t_list *cur, *head;\n\n\tRTW_PRINT_SEL(sel, \"regd_exc_num:%u\\n\", rfctl->regd_exc_num);\n\n\tif (!rfctl->regd_exc_num)\n\t\tgoto exit;\n\n\tRTW_PRINT_SEL(sel, \"%-7s %-6s %-9s\\n\", \"country\", \"domain\", \"regd_name\");\n\n\thead = &rfctl->reg_exc_list;\n\tcur = get_next(head);\n\n\twhile ((rtw_end_of_queue_search(head, cur)) == _FALSE) {\n\t\tu8 has_country;\n\n\t\tent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);\n\t\tcur = get_next(cur);\n\t\thas_country = (ent->country[0] == '\\0' && ent->country[1] == '\\0') ? 0 : 1;\n\n\t\tRTW_PRINT_SEL(sel, \"     %c%c   0x%02x %s\\n\"\n\t\t\t, has_country ? ent->country[0] : '0'\n\t\t\t, has_country ? ent->country[1] : '0'\n\t\t\t, ent->domain\n\t\t\t, ent->regd_name\n\t\t);\n\t}\n\nexit:\n\treturn;\n}\n\ninline void dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl)\n{\n\t_irqL irqL;\n\n\t_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\t_dump_regd_exc_list(sel, rfctl);\n\t_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n}\n\nvoid rtw_regd_exc_add_with_nlen(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name, u32 nlen)\n{\n\tstruct regd_exc_ent *ent;\n\t_irqL irqL;\n\n\tif (!regd_name || !nlen) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tent = (struct regd_exc_ent *)rtw_zmalloc(sizeof(struct regd_exc_ent) + nlen + 1);\n\tif (!ent)\n\t\tgoto exit;\n\n\t_rtw_init_listhead(&ent->list);\n\tif (country)\n\t\t_rtw_memcpy(ent->country, country, 2);\n\tent->domain = domain;\n\t_rtw_memcpy(ent->regd_name, regd_name, nlen);\n\n\t_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\n\trtw_list_insert_tail(&ent->list, &rfctl->reg_exc_list);\n\trfctl->regd_exc_num++;\n\n\t_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\nexit:\n\treturn;\n}\n\ninline void rtw_regd_exc_add(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name)\n{\n\trtw_regd_exc_add_with_nlen(rfctl, country, domain, regd_name, strlen(regd_name));\n}\n\nstruct regd_exc_ent *_rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain)\n{\n\tstruct regd_exc_ent *ent;\n\t_list *cur, *head;\n\tu8 match = 0;\n\n\thead = &rfctl->reg_exc_list;\n\tcur = get_next(head);\n\n\twhile ((rtw_end_of_queue_search(head, cur)) == _FALSE) {\n\t\tu8 has_country;\n\n\t\tent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);\n\t\tcur = get_next(cur);\n\t\thas_country = (ent->country[0] == '\\0' && ent->country[1] == '\\0') ? 0 : 1;\n\n\t\t/* entry has country condition to match */\n\t\tif (has_country) {\n\t\t\tif (!country)\n\t\t\t\tcontinue;\n\t\t\tif (ent->country[0] != country[0]\n\t\t\t\t|| ent->country[1] != country[1])\n\t\t\t\tcontinue;\n\t\t}\n\n\t\t/* entry has domain condition to match */\n\t\tif (ent->domain != 0xFF) {\n\t\t\tif (domain == 0xFF)\n\t\t\t\tcontinue;\n\t\t\tif (ent->domain != domain)\n\t\t\t\tcontinue;\n\t\t}\n\n\t\tmatch = 1;\n\t\tbreak;\n\t}\n\n\tif (match)\n\t\treturn ent;\n\telse\n\t\treturn NULL;\n}\n\ninline struct regd_exc_ent *rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain)\n{\n\tstruct regd_exc_ent *ent;\n\t_irqL irqL;\n\n\t_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\tent = _rtw_regd_exc_search(rfctl, country, domain);\n\t_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\n\treturn ent;\n}\n\nvoid rtw_regd_exc_list_free(struct rf_ctl_t *rfctl)\n{\n\tstruct regd_exc_ent *ent;\n\t_irqL irqL;\n\t_list *cur, *head;\n\n\t_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\n\thead = &rfctl->reg_exc_list;\n\tcur = get_next(head);\n\n\twhile ((rtw_end_of_queue_search(head, cur)) == _FALSE) {\n\t\tent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);\n\t\tcur = get_next(cur);\n\t\trtw_list_delete(&ent->list);\n\t\trtw_mfree((u8 *)ent, sizeof(struct regd_exc_ent) + strlen(ent->regd_name) + 1);\n\t}\n\trfctl->regd_exc_num = 0;\n\n\t_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n}\n\nvoid dump_txpwr_lmt(void *sel, _adapter *adapter)\n{\n#define TMP_STR_LEN 16\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\t_irqL irqL;\n\tchar fmt[16];\n\tchar tmp_str[TMP_STR_LEN];\n\ts8 *lmt_idx = NULL;\n\tint bw, band, ch_num, tlrs, ntx_idx, rs, i, path;\n\tu8 ch, n, rfpath_num;\n\n\t_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\n\t_dump_regd_exc_list(sel, rfctl);\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tif (!rfctl->txpwr_regd_num)\n\t\tgoto release_lock;\n\n\tlmt_idx = rtw_malloc(sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num);\n\tif (!lmt_idx) {\n\t\tRTW_ERR(\"%s alloc fail\\n\", __func__);\n\t\tgoto release_lock;\n\t}\n\n\tRTW_PRINT_SEL(sel, \"txpwr_lmt_2g_cck_ofdm_state:0x%02x\\n\", rfctl->txpwr_lmt_2g_cck_ofdm_state);\n\t#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\tif (IS_HARDWARE_TYPE_JAGUAR_ALL(adapter)) {\n\t\tRTW_PRINT_SEL(sel, \"txpwr_lmt_5g_cck_ofdm_state:0x%02x\\n\", rfctl->txpwr_lmt_5g_cck_ofdm_state);\n\t\tRTW_PRINT_SEL(sel, \"txpwr_lmt_5g_20_40_ref:0x%02x\\n\", rfctl->txpwr_lmt_5g_20_40_ref);\n\t}\n\t#endif\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tfor (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {\n\t\tif (!hal_is_band_support(adapter, band))\n\t\t\tcontinue;\n\n\t\trfpath_num = (band == BAND_ON_2_4G ? hal_spec->rfpath_num_2g : hal_spec->rfpath_num_5g);\n\n\t\tfor (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; bw++) {\n\n\t\t\tif (bw >= CHANNEL_WIDTH_160)\n\t\t\t\tbreak;\n\t\t\tif (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80)\n\t\t\t\tbreak;\n\n\t\t\tif (band == BAND_ON_2_4G)\n\t\t\t\tch_num = CENTER_CH_2G_NUM;\n\t\t\telse\n\t\t\t\tch_num = center_chs_5g_num(bw);\n\n\t\t\tif (ch_num == 0) {\n\t\t\t\trtw_warn_on(1);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tfor (tlrs = TXPWR_LMT_RS_CCK; tlrs < TXPWR_LMT_RS_NUM; tlrs++) {\n\n\t\t\t\tif (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT)\n\t\t\t\t\tcontinue;\n\t\t\t\tif (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK)\n\t\t\t\t\tcontinue;\n\t\t\t\tif (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM))\n\t\t\t\t\tcontinue;\n\t\t\t\tif (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT)\n\t\t\t\t\tcontinue;\n\t\t\t\tif (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))\n\t\t\t\t\tcontinue;\n\n\t\t\t\tfor (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {\n\t\t\t\t\tstruct txpwr_lmt_ent *ent;\n\t\t\t\t\t_list *cur, *head;\n\n\t\t\t\t\tif (ntx_idx >= hal_spec->tx_nss_num)\n\t\t\t\t\t\tcontinue;\n\n\t\t\t\t\t/* bypass CCK multi-TX is not defined */\n\t\t\t\t\tif (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) {\n\t\t\t\t\t\tif (band == BAND_ON_2_4G\n\t\t\t\t\t\t\t&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx)))\n\t\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\n\n\t\t\t\t\t/* bypass OFDM multi-TX is not defined */\n\t\t\t\t\tif (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) {\n\t\t\t\t\t\tif (band == BAND_ON_2_4G\n\t\t\t\t\t\t\t&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))\n\t\t\t\t\t\t\tcontinue;\n\t\t\t\t\t\t#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\t\t\t\t\t\tif (band == BAND_ON_5G\n\t\t\t\t\t\t\t&& !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))\n\t\t\t\t\t\t\tcontinue;\n\t\t\t\t\t\t#endif\n\t\t\t\t\t}\n\n\t\t\t\t\t/* bypass 5G 20M, 40M pure reference */\n\t\t\t\t\t#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\t\t\t\t\tif (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) {\n\t\t\t\t\t\tif (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) {\n\t\t\t\t\t\t\tif (tlrs == TXPWR_LMT_RS_HT)\n\t\t\t\t\t\t\t\tcontinue;\n\t\t\t\t\t\t} else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) {\n\t\t\t\t\t\t\tif (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40)\n\t\t\t\t\t\t\t\tcontinue;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\t#endif\n\n\t\t\t\t\t/* choose n-SS mapping rate section to get lmt diff value */\n\t\t\t\t\tif (tlrs == TXPWR_LMT_RS_CCK)\n\t\t\t\t\t\trs = CCK;\n\t\t\t\t\telse if (tlrs == TXPWR_LMT_RS_OFDM)\n\t\t\t\t\t\trs = OFDM;\n\t\t\t\t\telse if (tlrs == TXPWR_LMT_RS_HT)\n\t\t\t\t\t\trs = HT_1SS + ntx_idx;\n\t\t\t\t\telse if (tlrs == TXPWR_LMT_RS_VHT)\n\t\t\t\t\t\trs = VHT_1SS + ntx_idx;\n\t\t\t\t\telse {\n\t\t\t\t\t\tRTW_ERR(\"%s invalid tlrs %u\\n\", __func__, tlrs);\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\n\n\t\t\t\t\tRTW_PRINT_SEL(sel, \"[%s][%s][%s][%uT]\\n\"\n\t\t\t\t\t\t, band_str(band)\n\t\t\t\t\t\t, ch_width_str(bw)\n\t\t\t\t\t\t, txpwr_lmt_rs_str(tlrs)\n\t\t\t\t\t\t, ntx_idx + 1\n\t\t\t\t\t);\n\n\t\t\t\t\t/* header for limit in db */\n\t\t\t\t\tRTW_PRINT_SEL(sel, \"%3s \", \"ch\");\n\n\t\t\t\t\thead = &rfctl->txpwr_lmt_list;\n\t\t\t\t\tcur = get_next(head);\n\t\t\t\t\twhile ((rtw_end_of_queue_search(head, cur)) == _FALSE) {\n\t\t\t\t\t\tent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);\n\t\t\t\t\t\tcur = get_next(cur);\n\n\t\t\t\t\t\tsprintf(fmt, \"%%%zus%%s \", strlen(ent->regd_name) >= 6 ? 1 : 6 - strlen(ent->regd_name));\n\t\t\t\t\t\tsnprintf(tmp_str, TMP_STR_LEN, fmt\n\t\t\t\t\t\t\t, strcmp(ent->regd_name, rfctl->regd_name) == 0 ? \"*\" : \"\"\n\t\t\t\t\t\t\t, ent->regd_name);\n\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%s\", tmp_str);\n\t\t\t\t\t}\n\t\t\t\t\tsprintf(fmt, \"%%%zus%%s \", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? 1 : 6 - strlen(regd_str(TXPWR_LMT_WW)));\n\t\t\t\t\tsnprintf(tmp_str, TMP_STR_LEN, fmt\n\t\t\t\t\t\t, strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? \"*\" : \"\"\n\t\t\t\t\t\t, regd_str(TXPWR_LMT_WW));\n\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%s\", tmp_str);\n\n\t\t\t\t\t/* header for limit offset */\n\t\t\t\t\tfor (path = 0; path < RF_PATH_MAX; path++) {\n\t\t\t\t\t\tif (path >= rfpath_num)\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"|\");\n\t\t\t\t\t\thead = &rfctl->txpwr_lmt_list;\n\t\t\t\t\t\tcur = get_next(head);\n\t\t\t\t\t\twhile ((rtw_end_of_queue_search(head, cur)) == _FALSE) {\n\t\t\t\t\t\t\tent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);\n\t\t\t\t\t\t\tcur = get_next(cur);\n\t\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%3c \"\n\t\t\t\t\t\t\t\t, strcmp(ent->regd_name, rfctl->regd_name) == 0 ? rf_path_char(path) : ' ');\n\t\t\t\t\t\t}\n\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%3c \"\n\t\t\t\t\t\t\t\t, strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? rf_path_char(path) : ' ');\n\t\t\t\t\t}\n\t\t\t\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\n\t\t\t\t\tfor (n = 0; n < ch_num; n++) {\n\t\t\t\t\t\ts8 lmt;\n\t\t\t\t\t\ts8 lmt_offset;\n\t\t\t\t\t\tu8 base;\n\n\t\t\t\t\t\tif (band == BAND_ON_2_4G)\n\t\t\t\t\t\t\tch = n + 1;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tch = center_chs_5g(bw, n);\n\n\t\t\t\t\t\tif (ch == 0) {\n\t\t\t\t\t\t\trtw_warn_on(1);\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t}\n\n\t\t\t\t\t\t/* dump limit in db */\n\t\t\t\t\t\tRTW_PRINT_SEL(sel, \"%3u \", ch);\n\t\t\t\t\t\thead = &rfctl->txpwr_lmt_list;\n\t\t\t\t\t\tcur = get_next(head);\n\t\t\t\t\t\twhile ((rtw_end_of_queue_search(head, cur)) == _FALSE) {\n\t\t\t\t\t\t\tent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);\n\t\t\t\t\t\t\tcur = get_next(cur);\n\t\t\t\t\t\t\tlmt = phy_get_txpwr_lmt_abs(adapter, ent->regd_name, band, bw, tlrs, ntx_idx, ch, 0);\n\t\t\t\t\t\t\tif (lmt == hal_spec->txgi_max) {\n\t\t\t\t\t\t\t\tsprintf(fmt, \"%%%zus \", strlen(ent->regd_name) >= 6 ? strlen(ent->regd_name) + 1 : 6);\n\t\t\t\t\t\t\t\tsnprintf(tmp_str, TMP_STR_LEN, fmt, \"NA\");\n\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%s\", tmp_str);\n\t\t\t\t\t\t\t} else if (lmt > -hal_spec->txgi_pdbm && lmt < 0) { /* -0.xx */\n\t\t\t\t\t\t\t\tsprintf(fmt, \"%%%zus-0.%%d \", strlen(ent->regd_name) >= 6 ? strlen(ent->regd_name) - 4 : 1);\n\t\t\t\t\t\t\t\tsnprintf(tmp_str, TMP_STR_LEN, fmt, \"\", (rtw_abs(lmt) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);\n\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%s\", tmp_str);\n\t\t\t\t\t\t\t} else if (lmt % hal_spec->txgi_pdbm) { /* d.xx */\n\t\t\t\t\t\t\t\tsprintf(fmt, \"%%%zud.%%d \", strlen(ent->regd_name) >= 6 ? strlen(ent->regd_name) - 2 : 3);\n\t\t\t\t\t\t\t\tsnprintf(tmp_str, TMP_STR_LEN, fmt, lmt / hal_spec->txgi_pdbm, (rtw_abs(lmt) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);\n\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%s\", tmp_str);\n\t\t\t\t\t\t\t} else { /* d */\n\t\t\t\t\t\t\t\tsprintf(fmt, \"%%%zud \", strlen(ent->regd_name) >= 6 ? strlen(ent->regd_name) + 1 : 6);\n\t\t\t\t\t\t\t\tsnprintf(tmp_str, TMP_STR_LEN, fmt, lmt / hal_spec->txgi_pdbm);\n\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%s\", tmp_str);\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tlmt = phy_get_txpwr_lmt_abs(adapter, regd_str(TXPWR_LMT_WW), band, bw, tlrs, ntx_idx, ch, 0);\n\t\t\t\t\t\tif (lmt == hal_spec->txgi_max) {\n\t\t\t\t\t\t\tsprintf(fmt, \"%%%zus \", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? strlen(regd_str(TXPWR_LMT_WW)) + 1 : 6);\n\t\t\t\t\t\t\tsnprintf(tmp_str, TMP_STR_LEN, fmt, \"NA\");\n\t\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%s\", tmp_str);\n\t\t\t\t\t\t} else if (lmt > -hal_spec->txgi_pdbm && lmt < 0) { /* -0.xx */\n\t\t\t\t\t\t\tsprintf(fmt, \"%%%zus-0.%%d \", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? strlen(regd_str(TXPWR_LMT_WW)) - 4 : 1);\n\t\t\t\t\t\t\tsnprintf(tmp_str, TMP_STR_LEN, fmt, \"\", (rtw_abs(lmt) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);\n\t\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%s\", tmp_str);\n\t\t\t\t\t\t} else if (lmt % hal_spec->txgi_pdbm) { /* d.xx */\n\t\t\t\t\t\t\tsprintf(fmt, \"%%%zud.%%d \", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? strlen(regd_str(TXPWR_LMT_WW)) - 2 : 3);\n\t\t\t\t\t\t\tsnprintf(tmp_str, TMP_STR_LEN, fmt, lmt / hal_spec->txgi_pdbm, (rtw_abs(lmt) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);\n\t\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%s\", tmp_str);\n\t\t\t\t\t\t} else { /* d */\n\t\t\t\t\t\t\tsprintf(fmt, \"%%%zud \", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? strlen(regd_str(TXPWR_LMT_WW)) + 1 : 6);\n\t\t\t\t\t\t\tsnprintf(tmp_str, TMP_STR_LEN, fmt, lmt / hal_spec->txgi_pdbm);\n\t\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%s\", tmp_str);\n\t\t\t\t\t\t}\n\n\t\t\t\t\t\t/* dump limit offset of each path */\n\t\t\t\t\t\tfor (path = RF_PATH_A; path < RF_PATH_MAX; path++) {\n\t\t\t\t\t\t\tif (path >= rfpath_num)\n\t\t\t\t\t\t\t\tbreak;\n\n\t\t\t\t\t\t\tbase = PHY_GetTxPowerByRateBase(adapter, band, path, rs);\n\n\t\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"|\");\n\t\t\t\t\t\t\thead = &rfctl->txpwr_lmt_list;\n\t\t\t\t\t\t\tcur = get_next(head);\n\t\t\t\t\t\t\ti = 0;\n\t\t\t\t\t\t\twhile ((rtw_end_of_queue_search(head, cur)) == _FALSE) {\n\t\t\t\t\t\t\t\tent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);\n\t\t\t\t\t\t\t\tcur = get_next(cur);\n\t\t\t\t\t\t\t\tlmt_offset = phy_get_txpwr_lmt(adapter, ent->regd_name, band, bw, path, rs, ntx_idx, ch, 0);\n\t\t\t\t\t\t\t\tif (lmt_offset == hal_spec->txgi_max) {\n\t\t\t\t\t\t\t\t\t*(lmt_idx + i * RF_PATH_MAX + path) = hal_spec->txgi_max;\n\t\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%3s \", \"NA\");\n\t\t\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t\t\t*(lmt_idx + i * RF_PATH_MAX + path) = lmt_offset + base;\n\t\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%3d \", lmt_offset);\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\ti++;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tlmt_offset = phy_get_txpwr_lmt(adapter, regd_str(TXPWR_LMT_WW), band, bw, path, rs, ntx_idx, ch, 0);\n\t\t\t\t\t\t\tif (lmt_offset == hal_spec->txgi_max)\n\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%3s \", \"NA\");\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%3d \", lmt_offset);\n\n\t\t\t\t\t\t}\n\n\t\t\t\t\t\t/* compare limit_idx of each path, print 'x' when mismatch */\n\t\t\t\t\t\tif (rfpath_num > 1) {\n\t\t\t\t\t\t\tfor (i = 0; i < rfctl->txpwr_regd_num; i++) {\n\t\t\t\t\t\t\t\tfor (path = 0; path < RF_PATH_MAX; path++) {\n\t\t\t\t\t\t\t\t\tif (path >= rfpath_num)\n\t\t\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t\t\tif (*(lmt_idx + i * RF_PATH_MAX + path) != *(lmt_idx + i * RF_PATH_MAX + ((path + 1) % rfpath_num)))\n\t\t\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\tif (path >= rfpath_num)\n\t\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \" \");\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"x\");\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\n\t\t\t\t\t}\n\t\t\t\t\tRTW_PRINT_SEL(sel, \"\\n\");\n\t\t\t\t}\n\t\t\t} /* loop for rate sections */\n\t\t} /* loop for bandwidths */\n\t} /* loop for bands */\n\n\tif (lmt_idx)\n\t\trtw_mfree(lmt_idx, sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num);\n\nrelease_lock:\n\t_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n}\n\n/* search matcing first, if not found, alloc one */\nvoid rtw_txpwr_lmt_add_with_nlen(struct rf_ctl_t *rfctl, const char *regd_name, u32 nlen\n\t, u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(dvobj_get_primary_adapter(rfctl_to_dvobj(rfctl)));\n\tstruct txpwr_lmt_ent *ent;\n\t_irqL irqL;\n\t_list *cur, *head;\n\ts8 pre_lmt;\n\n\tif (!regd_name || !nlen) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\t_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\n\t/* search for existed entry */\n\thead = &rfctl->txpwr_lmt_list;\n\tcur = get_next(head);\n\twhile ((rtw_end_of_queue_search(head, cur)) == _FALSE) {\n\t\tent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);\n\t\tcur = get_next(cur);\n\n\t\tif (strlen(ent->regd_name) == nlen\n\t\t\t&& _rtw_memcmp(ent->regd_name, regd_name, nlen) == _TRUE)\n\t\t\tgoto chk_lmt_val;\n\t}\n\n\t/* alloc new one */\n\tent = (struct txpwr_lmt_ent *)rtw_zvmalloc(sizeof(struct txpwr_lmt_ent) + nlen + 1);\n\tif (!ent)\n\t\tgoto release_lock;\n\n\t_rtw_init_listhead(&ent->list);\n\t_rtw_memcpy(ent->regd_name, regd_name, nlen);\n\t{\n\t\tu8 j, k, l, m;\n\n\t\tfor (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j)\n\t\t\tfor (k = 0; k < TXPWR_LMT_RS_NUM_2G; ++k)\n\t\t\t\tfor (m = 0; m < CENTER_CH_2G_NUM; ++m)\n\t\t\t\t\tfor (l = 0; l < MAX_TX_COUNT; ++l)\n\t\t\t\t\t\tent->lmt_2g[j][k][m][l] = hal_spec->txgi_max;\n\t\t#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\t\tfor (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j)\n\t\t\tfor (k = 0; k < TXPWR_LMT_RS_NUM_5G; ++k)\n\t\t\t\tfor (m = 0; m < CENTER_CH_5G_ALL_NUM; ++m)\n\t\t\t\t\tfor (l = 0; l < MAX_TX_COUNT; ++l)\n\t\t\t\t\t\tent->lmt_5g[j][k][m][l] = hal_spec->txgi_max;\n\t\t#endif\n\t}\n\n\trtw_list_insert_tail(&ent->list, &rfctl->txpwr_lmt_list);\n\trfctl->txpwr_regd_num++;\n\nchk_lmt_val:\n\tif (band == BAND_ON_2_4G)\n\t\tpre_lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx];\n\t#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\telse if (band == BAND_ON_5G)\n\t\tpre_lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx];\n\t#endif\n\telse\n\t\tgoto release_lock;\n\n\tif (pre_lmt != hal_spec->txgi_max)\n\t\tRTW_PRINT(\"duplicate txpwr_lmt for [%s][%s][%s][%s][%uT][%d]\\n\"\n\t\t\t, regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1\n\t\t\t, band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx]);\n\n\tlmt = rtw_min(pre_lmt, lmt);\n\tif (band == BAND_ON_2_4G)\n\t\tent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] = lmt;\n\t#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\telse if (band == BAND_ON_5G)\n\t\tent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] = lmt;\n\t#endif\n\n\tif (0)\n\t\tRTW_PRINT(\"%s, %4s, %6s, %7s, %uT, ch%3d = %d\\n\"\n\t\t\t, regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1\n\t\t\t, band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx]\n\t\t\t, lmt);\n\nrelease_lock:\n\t_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\nexit:\n\treturn;\n}\n\ninline void rtw_txpwr_lmt_add(struct rf_ctl_t *rfctl, const char *regd_name\n\t, u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt)\n{\n\trtw_txpwr_lmt_add_with_nlen(rfctl, regd_name, strlen(regd_name)\n\t\t, band, bw, tlrs, ntx_idx, ch_idx, lmt);\n}\n\nstruct txpwr_lmt_ent *_rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name)\n{\n\tstruct txpwr_lmt_ent *ent;\n\t_list *cur, *head;\n\tu8 found = 0;\n\n\thead = &rfctl->txpwr_lmt_list;\n\tcur = get_next(head);\n\n\twhile ((rtw_end_of_queue_search(head, cur)) == _FALSE) {\n\t\tent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);\n\t\tcur = get_next(cur);\n\n\t\tif (strcmp(ent->regd_name, regd_name) == 0) {\n\t\t\tfound = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (found)\n\t\treturn ent;\n\treturn NULL;\n}\n\ninline struct txpwr_lmt_ent *rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name)\n{\n\tstruct txpwr_lmt_ent *ent;\n\t_irqL irqL;\n\n\t_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\tent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name);\n\t_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\n\treturn ent;\n}\n\nvoid rtw_txpwr_lmt_list_free(struct rf_ctl_t *rfctl)\n{\n\tstruct txpwr_lmt_ent *ent;\n\t_irqL irqL;\n\t_list *cur, *head;\n\n\t_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\n\thead = &rfctl->txpwr_lmt_list;\n\tcur = get_next(head);\n\n\twhile ((rtw_end_of_queue_search(head, cur)) == _FALSE) {\n\t\tent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);\n\t\tcur = get_next(cur);\n\t\tif (ent->regd_name == rfctl->regd_name)\n\t\t\trfctl->regd_name = regd_str(TXPWR_LMT_NONE);\n\t\trtw_list_delete(&ent->list);\n\t\trtw_vmfree((u8 *)ent, sizeof(struct txpwr_lmt_ent) + strlen(ent->regd_name) + 1);\n\t}\n\trfctl->txpwr_regd_num = 0;\n\n\t_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n}\n#endif /* CONFIG_TXPWR_LIMIT */\n\nint rtw_ch_to_bb_gain_sel(int ch)\n{\n\tint sel = -1;\n\n\tif (ch >= 1 && ch <= 14)\n\t\tsel = BB_GAIN_2G;\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\telse if (ch >= 36 && ch < 48)\n\t\tsel = BB_GAIN_5GLB1;\n\telse if (ch >= 52 && ch <= 64)\n\t\tsel = BB_GAIN_5GLB2;\n\telse if (ch >= 100 && ch <= 120)\n\t\tsel = BB_GAIN_5GMB1;\n\telse if (ch >= 124 && ch <= 144)\n\t\tsel = BB_GAIN_5GMB2;\n\telse if (ch >= 149 && ch <= 177)\n\t\tsel = BB_GAIN_5GHB;\n#endif\n\n\treturn sel;\n}\n\ns8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch)\n{\n\ts8 kfree_offset = 0;\n\n#ifdef CONFIG_RF_POWER_TRIM\n\tstruct kfree_data_t *kfree_data = GET_KFREE_DATA(padapter);\n\ts8 bb_gain_sel = rtw_ch_to_bb_gain_sel(ch);\n\n\tif (bb_gain_sel < BB_GAIN_2G || bb_gain_sel >= BB_GAIN_NUM) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (kfree_data->flag & KFREE_FLAG_ON) {\n\t\tkfree_offset = kfree_data->bb_gain[bb_gain_sel][path];\n\t\tif (IS_HARDWARE_TYPE_8723D(padapter))\n\t\t\tRTW_INFO(\"%s path:%s, ch:%u, bb_gain_sel:%d, kfree_offset:%d\\n\"\n\t\t\t\t, __func__, (path == 0)?\"S1\":\"S0\", \n\t\t\t\tch, bb_gain_sel, kfree_offset);\n\t\telse\n\t\t\tRTW_INFO(\"%s path:%u, ch:%u, bb_gain_sel:%d, kfree_offset:%d\\n\"\n\t\t\t\t, __func__, path, ch, bb_gain_sel, kfree_offset);\n\t}\nexit:\n#endif /* CONFIG_RF_POWER_TRIM */\n\treturn kfree_offset;\n}\n\nvoid rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset)\n{\n#if !defined(CONFIG_RTL8814A) && !defined(CONFIG_RTL8822B) && !defined(CONFIG_RTL8821C) && !defined(CONFIG_RTL8822C)\n\tu8 write_value;\n#endif\n\tu8 target_path = 0;\n\tu32 val32 = 0;\n\n\tif (IS_HARDWARE_TYPE_8723D(adapter)) {\n\t\ttarget_path = RF_PATH_A; /*in 8723D case path means S0/S1*/\n\t\tif (path == PPG_8723D_S1)\n\t\t\tRTW_INFO(\"kfree gain_offset 0x55:0x%x \",\n\t\t\trtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff));\n\t\telse if (path == PPG_8723D_S0)\n\t\t\tRTW_INFO(\"kfree gain_offset 0x65:0x%x \",\n\t\t\trtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff));\n\t} else {\n\t\ttarget_path = path;\n\t\tRTW_INFO(\"kfree gain_offset 0x55:0x%x \", rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff));\n\t}\n\t\n\tswitch (rtw_get_chip_type(adapter)) {\n#ifdef CONFIG_RTL8723D\n\tcase RTL8723D:\n\t\twrite_value = RF_TX_GAIN_OFFSET_8723D(offset);\n\t\tif (path == PPG_8723D_S1)\n\t\t\trtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);\n\t\telse if (path == PPG_8723D_S0)\n\t\t\trtw_hal_write_rfreg(adapter, target_path, 0x65, 0x0f8000, write_value);\n\t\tbreak;\n#endif /* CONFIG_RTL8723D */\n#ifdef CONFIG_RTL8703B\n\tcase RTL8703B:\n\t\twrite_value = RF_TX_GAIN_OFFSET_8703B(offset);\n\t\trtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value);\n\t\tbreak;\n#endif /* CONFIG_RTL8703B */\n#ifdef CONFIG_RTL8188F\n\tcase RTL8188F:\n\t\twrite_value = RF_TX_GAIN_OFFSET_8188F(offset);\n\t\trtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value);\n\t\tbreak;\n#endif /* CONFIG_RTL8188F */\n#ifdef CONFIG_RTL8188GTV\n\tcase RTL8188GTV:\n\t\twrite_value = RF_TX_GAIN_OFFSET_8188GTV(offset);\n\t\trtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value);\n\t\tbreak;\n#endif /* CONFIG_RTL8188GTV */\n#ifdef CONFIG_RTL8192E\n\tcase RTL8192E:\n\t\twrite_value = RF_TX_GAIN_OFFSET_8192E(offset);\n\t\trtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);\n\t\tbreak;\n#endif /* CONFIG_RTL8188F */\n\n#ifdef CONFIG_RTL8821A\n\tcase RTL8821:\n\t\twrite_value = RF_TX_GAIN_OFFSET_8821A(offset);\n\t\trtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);\n\t\tbreak;\n#endif /* CONFIG_RTL8821A */\n#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822C)\n\tcase RTL8814A:\n\tcase RTL8822B:\n\tcase RTL8822C:\t\n\tcase RTL8821C:\n\tcase RTL8192F:\n\t\tRTW_INFO(\"\\nkfree by PhyDM on the sw CH. path %d\\n\", path);\n\t\tbreak;\n#endif /* CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */\n\n\tdefault:\n\t\trtw_warn_on(1);\n\t\tbreak;\n\t}\n\t\n\tif (IS_HARDWARE_TYPE_8723D(adapter)) {\n\t\tif (path == PPG_8723D_S1)\n\t\t\tval32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff);\n\t\telse if (path == PPG_8723D_S0)\n\t\t\tval32 = rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff);\n\t} else {\n\t\tval32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff);\n\t}\n\tRTW_INFO(\" after :0x%x\\n\", val32);\n}\n\nvoid rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\ts8 kfree_offset = 0;\n\ts8 tx_pwr_track_offset = 0; /* TODO: 8814A should consider tx pwr track when setting tx gain offset */\n\ts8 total_offset;\n\tint i, total = 0;\n\n\tif (IS_HARDWARE_TYPE_8723D(adapter))\n\t\ttotal = 2; /* S1 and S0 */\n\telse\n\t\ttotal = hal_data->NumTotalRFPath;\n\n\tfor (i = 0; i < total; i++) {\n\t\tkfree_offset = rtw_rf_get_kfree_tx_gain_offset(adapter, i, ch);\n\t\ttotal_offset = kfree_offset + tx_pwr_track_offset;\n\t\trtw_rf_set_tx_gain_offset(adapter, i, total_offset);\n\t}\n}\n\ninline u8 rtw_is_dfs_range(u32 hi, u32 lo)\n{\n\treturn rtw_is_range_overlap(hi, lo, 5720 + 10, 5260 - 10);\n}\n\nu8 rtw_is_dfs_ch(u8 ch)\n{\n\tu32 hi, lo;\n\n\tif (!rtw_chbw_to_freq_range(ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, &hi, &lo))\n\t\treturn 0;\n\n\treturn rtw_is_dfs_range(hi, lo);\n}\n\nu8 rtw_is_dfs_chbw(u8 ch, u8 bw, u8 offset)\n{\n\tu32 hi, lo;\n\n\tif (!rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo))\n\t\treturn 0;\n\n\treturn rtw_is_dfs_range(hi, lo);\n}\n\nbool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region)\n{\n\treturn (dfs_region == PHYDM_DFS_DOMAIN_ETSI && rtw_is_range_overlap(hi, lo, 5650, 5600)) ? _TRUE : _FALSE;\n}\n\nbool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region)\n{\n\tu32 hi, lo;\n\n\tif (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)\n\t\treturn _FALSE;\n\n\treturn rtw_is_long_cac_range(hi, lo, dfs_region) ? _TRUE : _FALSE;\n}\n"
  },
  {
    "path": "core/rtw_rm.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include <drv_types.h>\n#include <hal_data.h>\n#include \"rtw_rm_fsm.h\"\n\n#define pstr(s) s+strlen(s)\n\nu8 rm_post_event_hdl(_adapter *padapter, u8 *pbuf)\n{\n#ifdef CONFIG_RTW_80211K\n\tstruct rm_event *pev = (struct rm_event *)pbuf;\n\n\t_rm_post_event(padapter, pev->rmid, pev->evid);\n\trm_handler(padapter, pev);\n#endif\n\treturn H2C_SUCCESS;\n}\n\n#ifdef CONFIG_RTW_80211K\n\n/* 802.11-2012 Table E-1 Operationg classes in United States */\nstatic RT_OPERATING_CLASS RTW_OP_CLASS_US[] = {\n\t/* 0, OP_CLASS_NULL */\t{  0,  0, {}},\n\t/* 1, OP_CLASS_1 */\t{115,  4, {36, 40, 44, 48}},\n\t/* 2, OP_CLASS_2 */\t{118,  4, {52, 56, 60, 64}},\n\t/* 3, OP_CLASS_3 */\t{124,  4, {149, 153, 157, 161}},\n\t/* 4, OP_CLASS_4 */\t{121, 11, {100, 104, 108, 112, 116, 120, 124,\n\t\t\t\t\t\t128, 132, 136, 140}},\n\t/* 5, OP_CLASS_5 */\t{125,  5, {149, 153, 157, 161, 165}},\n\t/* 6, OP_CLASS_12 */\t{ 81, 11, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}}\n};\n\nstruct cmd_meas_type_ {\n\tu8 id;\n\tchar *name;\n};\n\nchar *rm_type_req_name(u8 meas_type) {\n\n\tswitch (meas_type) {\n\tcase basic_req:\n\t\treturn \"basic_req\";\n\tcase cca_req:\n\t\treturn \"cca_req\";\n\tcase rpi_histo_req:\n\t\treturn \"rpi_histo_req\";\n\tcase ch_load_req:\n\t\treturn \"ch_load_req\";\n\tcase noise_histo_req:\n\t\treturn \"noise_histo_req\";\n\tcase bcn_req:\n\t\treturn \"bcn_req\";\n\tcase frame_req:\n\t\treturn \"frame_req\";\n\tcase sta_statis_req:\n\t\treturn \"sta_statis_req\";\n\t}\n\treturn \"unknown_req\";\n};\n\nchar *rm_type_rep_name(u8 meas_type) {\n\n\tswitch (meas_type) {\n\tcase basic_rep:\n\t\treturn \"basic_rep\";\n\tcase cca_rep:\n\t\treturn \"cca_rep\";\n\tcase rpi_histo_rep:\n\t\treturn \"rpi_histo_rep\";\n\tcase ch_load_rep:\n\t\treturn \"ch_load_rep\";\n\tcase noise_histo_rep:\n\t\treturn \"noise_histo_rep\";\n\tcase bcn_rep:\n\t\treturn \"bcn_rep\";\n\tcase frame_rep:\n\t\treturn \"frame_rep\";\n\tcase sta_statis_rep:\n\t\treturn \"sta_statis_rep\";\n\t}\n\treturn \"unknown_rep\";\n};\n\nchar *rm_en_cap_name(enum rm_cap_en en)\n{\n\tswitch (en) {\n\tcase RM_LINK_MEAS_CAP_EN:\n\t\treturn \"RM_LINK_MEAS_CAP_EN\";\n\tcase RM_NB_REP_CAP_EN:\n\t\treturn \"RM_NB_REP_CAP_EN\";\n\tcase RM_PARAL_MEAS_CAP_EN:\n\t\treturn \"RM_PARAL_MEAS_CAP_EN\";\n\tcase RM_REPEAT_MEAS_CAP_EN:\n\t\treturn \"RM_REPEAT_MEAS_CAP_EN\";\n\tcase RM_BCN_PASSIVE_MEAS_CAP_EN:\n\t\treturn \"RM_BCN_PASSIVE_MEAS_CAP_EN\";\n\tcase RM_BCN_ACTIVE_MEAS_CAP_EN:\n\t\treturn \"RM_BCN_ACTIVE_MEAS_CAP_EN\";\n\tcase RM_BCN_TABLE_MEAS_CAP_EN:\n\t\treturn \"RM_BCN_TABLE_MEAS_CAP_EN\";\n\tcase RM_BCN_MEAS_REP_COND_CAP_EN:\n\t\treturn \"RM_BCN_MEAS_REP_COND_CAP_EN\";\n\n\tcase RM_FRAME_MEAS_CAP_EN:\n\t\treturn \"RM_FRAME_MEAS_CAP_EN\";\n\tcase RM_CH_LOAD_CAP_EN:\n\t\treturn \"RM_CH_LOAD_CAP_EN\";\n\tcase RM_NOISE_HISTO_CAP_EN:\n\t\treturn \"RM_NOISE_HISTO_CAP_EN\";\n\tcase RM_STATIS_MEAS_CAP_EN:\n\t\treturn \"RM_STATIS_MEAS_CAP_EN\";\n\tcase RM_LCI_MEAS_CAP_EN:\n\t\treturn \"RM_LCI_MEAS_CAP_EN\";\n\tcase RM_LCI_AMIMUTH_CAP_EN:\n\t\treturn \"RM_LCI_AMIMUTH_CAP_EN\";\n\tcase RM_TRANS_STREAM_CAT_MEAS_CAP_EN:\n\t\treturn \"RM_TRANS_STREAM_CAT_MEAS_CAP_EN\";\n\tcase RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN:\n\t\treturn \"RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN\";\n\n\tcase RM_AP_CH_REP_CAP_EN:\n\t\treturn \"RM_AP_CH_REP_CAP_EN\";\n\tcase RM_RM_MIB_CAP_EN:\n\t\treturn \"RM_RM_MIB_CAP_EN\";\n\tcase RM_OP_CH_MAX_MEAS_DUR0:\n\t\treturn \"RM_OP_CH_MAX_MEAS_DUR0\";\n\tcase RM_OP_CH_MAX_MEAS_DUR1:\n\t\treturn \"RM_OP_CH_MAX_MEAS_DUR1\";\n\tcase RM_OP_CH_MAX_MEAS_DUR2:\n\t\treturn \"RM_OP_CH_MAX_MEAS_DUR2\";\n\tcase RM_NONOP_CH_MAX_MEAS_DUR0:\n\t\treturn \"RM_NONOP_CH_MAX_MEAS_DUR0\";\n\tcase RM_NONOP_CH_MAX_MEAS_DUR1:\n\t\treturn \"RM_NONOP_CH_MAX_MEAS_DUR1\";\n\tcase RM_NONOP_CH_MAX_MEAS_DUR2:\n\t\treturn \"RM_NONOP_CH_MAX_MEAS_DUR2\";\n\n\tcase RM_MEAS_PILOT_CAP0:\n\t\treturn \"RM_MEAS_PILOT_CAP0\";\t\t/* 24-26 */\n\tcase RM_MEAS_PILOT_CAP1:\n\t\treturn \"RM_MEAS_PILOT_CAP1\";\n\tcase RM_MEAS_PILOT_CAP2:\n\t\treturn \"RM_MEAS_PILOT_CAP2\";\n\tcase RM_MEAS_PILOT_TRANS_INFO_CAP_EN:\n\t\treturn \"RM_MEAS_PILOT_TRANS_INFO_CAP_EN\";\n\tcase RM_NB_REP_TSF_OFFSET_CAP_EN:\n\t\treturn \"RM_NB_REP_TSF_OFFSET_CAP_EN\";\n\tcase RM_RCPI_MEAS_CAP_EN:\n\t\treturn \"RM_RCPI_MEAS_CAP_EN\";\t\t/* 29 */\n\tcase RM_RSNI_MEAS_CAP_EN:\n\t\treturn \"RM_RSNI_MEAS_CAP_EN\";\n\tcase RM_BSS_AVG_ACCESS_DELAY_CAP_EN:\n\t\treturn \"RM_BSS_AVG_ACCESS_DELAY_CAP_EN\";\n\n\tcase RM_AVALB_ADMIS_CAPACITY_CAP_EN:\n\t\treturn \"RM_AVALB_ADMIS_CAPACITY_CAP_EN\";\n\tcase RM_ANT_CAP_EN:\n\t\treturn \"RM_ANT_CAP_EN\";\n\tcase RM_RSVD:\n\tcase RM_MAX:\n\tdefault:\n\t\tbreak;\n\t}\n\treturn \"unknown\";\n}\n\nint rm_en_cap_chk_and_set(struct rm_obj *prm, enum rm_cap_en en)\n{\n\tint idx;\n\tu8 cap;\n\n\n\tif (en >= RM_MAX)\n\t\treturn _FALSE;\n\n\tidx = en / 8;\n\tcap = prm->psta->padapter->rmpriv.rm_en_cap_def[idx];\n\n\tif (!(cap & BIT(en - (idx*8)))) {\n\t\tRTW_INFO(\"RM: %s incapable\\n\",rm_en_cap_name(en));\n\t\trm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);\n\t\treturn _FALSE;\n\t}\n\treturn _SUCCESS;\n}\n\nstatic u8 rm_get_oper_class_via_ch(u8 ch)\n{\n\tint i,j,sz;\n\n\n\tsz = sizeof(RTW_OP_CLASS_US)/sizeof(struct _RT_OPERATING_CLASS);\n\n\tfor (i = 0; i < sz; i++) {\n\t\tfor (j = 0; j < RTW_OP_CLASS_US[i].Len; j++) {\n\t\t\tif ( ch == RTW_OP_CLASS_US[i].Channel[j]) {\n\t\t\t\tRTW_INFO(\"RM: ch %u in oper_calss %u\\n\",\n\t\t\t\t\tch, RTW_OP_CLASS_US[i].global_op_class);\n\t\t\t\treturn RTW_OP_CLASS_US[i].global_op_class;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic u8 rm_get_ch_set(\n\tstruct rtw_ieee80211_channel *pch_set, u8 op_class, u8 ch_num)\n{\n\tint i,j,sz;\n\tu8 ch_amount = 0;\n\n\n\tsz = sizeof(RTW_OP_CLASS_US)/sizeof(struct _RT_OPERATING_CLASS);\n\n\tif (ch_num != 0) {\n\t\tpch_set[0].hw_value = ch_num;\n\t\tch_amount = 1;\n\t\tRTW_INFO(\"RM: meas_ch->hw_value = %u\\n\", pch_set->hw_value);\n\t\tgoto done;\n\t}\n\n\tfor (i = 0; i < sz; i++) {\n\n\t\tif (RTW_OP_CLASS_US[i].global_op_class == op_class) {\n\n\t\t\tfor (j = 0; j < RTW_OP_CLASS_US[i].Len; j++) {\n\t\t\t\tpch_set[j].hw_value =\n\t\t\t\t\tRTW_OP_CLASS_US[i].Channel[j];\n\t\t\t\tRTW_INFO(\"RM: meas_ch[%d].hw_value = %u\\n\",\n\t\t\t\t\tj, pch_set[j].hw_value);\n\t\t\t}\n\t\t\tch_amount = RTW_OP_CLASS_US[i].Len;\n\t\t\tbreak;\n\t\t}\n\t}\ndone:\n\treturn ch_amount;\n}\n\nstatic int is_wildcard_bssid(u8 *bssid)\n{\n\tint i;\n\tu8 val8 = 0xff;\n\n\n\tfor (i=0;i<6;i++)\n\t\tval8 &= bssid[i];\n\n\tif (val8 == 0xff)\n\t\treturn _SUCCESS;\n\treturn _FALSE;\n}\n\n/* for caller outside rm */\nu8 rm_add_nb_req(_adapter *padapter, struct sta_info *psta)\n{\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;\n\tstruct rm_obj *prm;\n\n\n\tprm = rm_alloc_rmobj(padapter);\n\n\tif (prm == NULL) {\n\t\tRTW_ERR(\"RM: unable to alloc rm obj for requeset\\n\");\n\t\treturn _FALSE;\n\t}\n\n\tprm->psta = psta;\n\tprm->q.category = RTW_WLAN_CATEGORY_RADIO_MEAS;\n\tprm->q.diag_token = pmlmeinfo->dialogToken++;\n\tprm->q.m_token = 1;\n\n\tprm->rmid = psta->cmn.aid << 16\n\t\t| prm->q.diag_token << 8\n\t\t| RM_MASTER;\n\n\tprm->q.action_code = RM_ACT_NB_REP_REQ;\n\n\t#if 0\n\tif (pmac) { /* find sta_info according to bssid */\n\t\tpmac += 4; /* skip mac= */\n\t\tif (hwaddr_parse(pmac, bssid) == NULL) {\n\t\t\tsprintf(pstr(s), \"Err: \\nincorrect mac format\\n\");\n\t\t\treturn _FAIL;\n\t\t}\n\t\tpsta = rm_get_sta(padapter, 0xff, bssid);\n\t}\n\t#endif\n\n\t/* enquee rmobj */\n\trm_enqueue_rmobj(padapter, prm, _FALSE);\n\n\tRTW_INFO(\"RM: rmid=%x add req to \" MAC_FMT \"\\n\",\n\t\tprm->rmid, MAC_ARG(psta->cmn.mac_addr));\n\n\treturn _SUCCESS;\n}\n\n\nstatic u8 *build_wlan_hdr(_adapter *padapter, struct xmit_frame *pmgntframe,\n\tstruct sta_info *psta, u16 frame_type)\n{\n\tu8 *pframe;\n\tu16 *fctrl;\n\tstruct pkt_attrib *pattr;\n\tstruct rtw_ieee80211_hdr *pwlanhdr;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;\n\n\n\t/* update attribute */\n\tpattr = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattr);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, psta->cmn.mac_addr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3,\n\t\tget_my_bssid(&(pmlmeinfo->network)),ETH_ALEN);\n\n\tRTW_INFO(\"RM: dst = \" MAC_FMT \"\\n\", MAC_ARG(pwlanhdr->addr1));\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tSetFragNum(pframe, 0);\n\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattr->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\treturn pframe;\n}\n\nvoid rm_set_rep_mode(struct rm_obj *prm, u8 mode)\n{\n\n\tRTW_INFO(\"RM: rmid=%x set %s\\n\",\n\t\tprm->rmid,\n\t\tmode|MEAS_REP_MOD_INCAP?\"INCAP\":\n\t\tmode|MEAS_REP_MOD_REFUSE?\"REFUSE\":\n\t\tmode|MEAS_REP_MOD_LATE?\"LATE\":\"\");\n\n\tprm->p.m_mode |= mode;\n}\n\nint issue_null_reply(struct rm_obj *prm)\n{\n\tint len=0, my_len;\n\tu8 *pframe, m_mode;\n\t_adapter *padapter = prm->psta->padapter;\n\tstruct pkt_attrib *pattr;\n\tstruct xmit_frame *pmgntframe;\n\tstruct xmit_priv *pxmitpriv = &(padapter->xmitpriv);\n\n\n\tm_mode = prm->p.m_mode;\n\tif (m_mode || prm->p.rpt == 0) {\n\t\tRTW_INFO(\"RM: rmid=%x reply (%s repeat=%d)\\n\",\n\t\t\tprm->rmid,\n\t\t\tm_mode&MEAS_REP_MOD_INCAP?\"INCAP\":\n\t\t\tm_mode&MEAS_REP_MOD_REFUSE?\"REFUSE\":\n\t\t\tm_mode&MEAS_REP_MOD_LATE?\"LATE\":\"no content\",\n\t\t\tprm->p.rpt);\n\t}\n\n\tswitch (prm->p.action_code) {\n\tcase RM_ACT_RADIO_MEAS_REQ:\n\t\tlen = 8;\n\t\tbreak;\n\tcase RM_ACT_NB_REP_REQ:\n\t\tlen = 3;\n\t\tbreak;\n\tcase RM_ACT_LINK_MEAS_REQ:\n\t\tlen = 3;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (len==0)\n\t\treturn _FALSE;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL) {\n\t\tRTW_ERR(\"RM: %s alloc xmit_frame fail\\n\",__func__);\n\t\treturn _FALSE;\n\t}\n\tpattr = &pmgntframe->attrib;\n\tpframe = build_wlan_hdr(padapter, pmgntframe, prm->psta, WIFI_ACTION);\n\tpframe = rtw_set_fixed_ie(pframe, 3, &prm->p.category, &pattr->pktlen);\n\n\tmy_len = 0;\n\tif (len>5) {\n\t\tprm->p.len = len - 3 - 2;\n\t\tpframe = rtw_set_fixed_ie(pframe, len - 3,\n\t\t\t&prm->p.e_id, &my_len);\n\t}\n\n\tpattr->pktlen += my_len;\n\tpattr->last_txcmdsz = pattr->pktlen;\n\tdump_mgntframe(padapter, pmgntframe);\n\n\treturn _SUCCESS;\n}\n\nint ready_for_scan(struct rm_obj *prm)\n{\n\t_adapter *padapter = prm->psta->padapter;\n\tu8 ssc_chk;\n\n\tif (!rtw_is_adapter_up(padapter))\n\t\treturn _FALSE;\n\n\tssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);\n\n\tif (ssc_chk == SS_ALLOW)\n\t\treturn _SUCCESS;\n\n\treturn _FALSE;\n}\n\nint rm_sitesurvey(struct rm_obj *prm)\n{\n\tint meas_ch_num=0;\n\tu8 ch_num=0, op_class=0, val8;\n\tstruct rtw_ieee80211_channel *pch_set;\n\tstruct sitesurvey_parm parm;\n\n\n\tRTW_INFO(\"RM: rmid=%x %s\\n\",prm->rmid, __func__);\n\n\tpch_set = &prm->q.ch_set[0];\n\n\t_rtw_memset(pch_set, 0,\n\t\tsizeof(struct rtw_ieee80211_channel) * MAX_OP_CHANNEL_SET_NUM);\n\n\tif (prm->q.ch_num == 0) {\n\t\t/* ch_num=0   : scan all ch in operating class */\n\t\top_class = prm->q.op_class;\n\n\t} else if (prm->q.ch_num == 255) {\n\t\t/* 802.11 p.499 */\n\t\t/* ch_num=255 : scan all ch in current operating class */\n\t\top_class = rm_get_oper_class_via_ch(\n\t\t\t(u8)prm->psta->padapter->mlmeextpriv.cur_channel);\n\t} else\n\t\tch_num = prm->q.ch_num;\n\n\t/* get means channel */\n\tmeas_ch_num = rm_get_ch_set(pch_set, op_class, ch_num);\n\tprm->q.ch_set_ch_amount = meas_ch_num;\n\n\t_rtw_memset(&parm, 0, sizeof(struct sitesurvey_parm));\n\t_rtw_memcpy(parm.ch, pch_set,\n\t\tsizeof(struct rtw_ieee80211_channel) * MAX_OP_CHANNEL_SET_NUM);\n\n\t_rtw_memcpy(&parm.ssid[0], &prm->q.opt.bcn.ssid, IW_ESSID_MAX_SIZE);\n\n\tparm.ssid_num = 1;\n\tparm.scan_mode = prm->q.m_mode;\n\tparm.ch_num = meas_ch_num;\n\tparm.igi = 0;\n\tparm.token = prm->rmid;\n\tparm.duration = prm->q.meas_dur;\n\t/* parm.bw = BW_20M; */\n\n\trtw_sitesurvey_cmd(prm->psta->padapter, &parm);\n\n\treturn _SUCCESS;\n}\n\nstatic u8 translate_percentage_to_rcpi(u32 SignalStrengthIndex)\n{\n\ts32 SignalPower; /* in dBm. */\n\tu8 rcpi;\n\n\t/* Translate to dBm (x=y-100) */\n\tSignalPower = SignalStrengthIndex - 100;\n\n\t/* RCPI = Int{(Power in dBm + 110)*2} for 0dBm > Power > -110dBm\n\t *    0\t: power <= -110.0 dBm\n\t *    1\t: power =  -109.5 dBm\n\t *    2\t: power =  -109.0 dBm\n\t */\n\n\trcpi = (SignalPower + 110)*2;\n\treturn rcpi;\n}\n\nstatic int rm_parse_ch_load_s_elem(struct rm_obj *prm, u8 *pbody, int req_len)\n{\n\tu8 *popt_id;\n\tint i, p=0; /* position */\n\tint len = req_len;\n\n\n\tprm->q.opt_s_elem_len = len;\n#if (RM_MORE_DBG_MSG)\n\tRTW_INFO(\"RM: opt_s_elem_len=%d\\n\", len);\n#endif\n\twhile (len) {\n\n\t\tswitch (pbody[p]) {\n\t\tcase ch_load_rep_info:\n\t\t\t/* check RM_EN */\n\t\t\trm_en_cap_chk_and_set(prm, RM_CH_LOAD_CAP_EN);\n\n\t\t\t_rtw_memcpy(&(prm->q.opt.clm.rep_cond),\n\t\t\t\t&pbody[p+2], sizeof(prm->q.opt.clm.rep_cond));\n\n\t\t\tRTW_INFO(\"RM: ch_load_rep_info=%u:%u\\n\",\n\t\t\t\tprm->q.opt.clm.rep_cond.cond,\n\t\t\t\tprm->q.opt.clm.rep_cond.threshold);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\n\t\t}\n\t\tlen = len - (int)pbody[p+1] - 2;\n\t\tp = p + (int)pbody[p+1] + 2;\n#if (RM_MORE_DBG_MSG)\n\t\tRTW_INFO(\"RM: opt_s_elem_len=%d\\n\",len);\n#endif\n\t}\n\treturn _SUCCESS;\n}\n\nstatic int rm_parse_noise_histo_s_elem(struct rm_obj *prm,\n\tu8 *pbody, int req_len)\n{\n\tu8 *popt_id;\n\tint i, p=0; /* position */\n\tint len = req_len;\n\n\n\tprm->q.opt_s_elem_len = len;\n#if (RM_MORE_DBG_MSG)\n\tRTW_INFO(\"RM: opt_s_elem_len=%d\\n\", len);\n#endif\n\n\twhile (len) {\n\n\t\tswitch (pbody[p]) {\n\t\tcase noise_histo_rep_info:\n\t\t\t/* check RM_EN */\n\t\t\trm_en_cap_chk_and_set(prm, RM_NOISE_HISTO_CAP_EN);\n\n\t\t\t_rtw_memcpy(&(prm->q.opt.nhm.rep_cond),\n\t\t\t\t&pbody[p+2], sizeof(prm->q.opt.nhm.rep_cond));\n\n\t\t\tRTW_INFO(\"RM: noise_histo_rep_info=%u:%u\\n\",\n\t\t\t\tprm->q.opt.nhm.rep_cond.cond,\n\t\t\t\tprm->q.opt.nhm.rep_cond.threshold);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\n       \t\t}\n\t\tlen = len - (int)pbody[p+1] - 2;\n\t\tp = p + (int)pbody[p+1] + 2;\n#if (RM_MORE_DBG_MSG)\n\t\tRTW_INFO(\"RM: opt_s_elem_len=%d\\n\",len);\n#endif\n\t}\n\treturn _SUCCESS;\n}\n\nstatic int rm_parse_bcn_req_s_elem(struct rm_obj *prm, u8 *pbody, int req_len)\n{\n\tu8 *popt_id;\n\tint i, p=0; /* position */\n\tint len = req_len;\n\n\n\t/* opt length,2:pbody[0]+ pbody[1] */\n\t/* first opt id : pbody[18] */\n\n\tprm->q.opt_s_elem_len = len;\n#if (RM_MORE_DBG_MSG)\n\tRTW_INFO(\"RM: opt_s_elem_len=%d\\n\", len);\n#endif\n\n\tpopt_id = prm->q.opt.bcn.opt_id;\n\twhile (len && prm->q.opt.bcn.opt_id_num < BCN_REQ_OPT_MAX_NUM) {\n\n\t\tswitch (pbody[p]) {\n\t\tcase bcn_req_ssid:\n\t\t\tRTW_INFO(\"bcn_req_ssid\\n\");\n\n#if (DBG_BCN_REQ_WILDCARD)\n\t\t\tRTW_INFO(\"DBG set ssid to WILDCARD\\n\");\n#else\n#if (DBG_BCN_REQ_SSID)\n\t\t\tRTW_INFO(\"DBG set ssid to %s\\n\",DBG_BCN_REQ_SSID_NAME);\n\t\t\ti = strlen(DBG_BCN_REQ_SSID_NAME);\n\t\t\tprm->q.opt.bcn.ssid.SsidLength = i;\n\t\t\t_rtw_memcpy(&(prm->q.opt.bcn.ssid.Ssid),\n\t\t\t\tDBG_BCN_REQ_SSID_NAME, i);\n\n#else /* original */\n\t\t\tprm->q.opt.bcn.ssid.SsidLength = pbody[p+1];\n\t\t\t_rtw_memcpy(&(prm->q.opt.bcn.ssid.Ssid),\n\t\t\t\t&pbody[p+2], pbody[p+1]);\n#endif\n#endif\n\n\t\t\tRTW_INFO(\"RM: bcn_req_ssid=%s\\n\",\n\t\t\t\tprm->q.opt.bcn.ssid.Ssid);\n\n\t\t\tpopt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];\n\t\t\tbreak;\n\n\t\tcase bcn_req_rep_info:\n\t\t\t/* check RM_EN */\n\t\t\trm_en_cap_chk_and_set(prm, RM_BCN_MEAS_REP_COND_CAP_EN);\n\n\t\t\t_rtw_memcpy(&(prm->q.opt.bcn.rep_cond),\n\t\t\t\t&pbody[p+2], sizeof(prm->q.opt.bcn.rep_cond));\n\n\t\t\tRTW_INFO(\"bcn_req_rep_info=%u:%u\\n\",\n\t\t\t\tprm->q.opt.bcn.rep_cond.cond,\n\t\t\t\tprm->q.opt.bcn.rep_cond.threshold);\n\n\t\t\t/*popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];*/\n\t\t\tbreak;\n\n\t\tcase bcn_req_rep_detail:\n#if DBG_BCN_REQ_DETAIL\n\t\t\tprm->q.opt.bcn.rep_detail = 2; /* all IE in beacon */\n#else\n\t\t\tprm->q.opt.bcn.rep_detail = pbody[p+2];\n#endif\n\t\t\tpopt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];\n\n#if (RM_MORE_DBG_MSG)\n\t\t\tRTW_INFO(\"RM: report_detail=%d\\n\",\n\t\t\t\tprm->q.opt.bcn.rep_detail);\n#endif\n\t\t\tbreak;\n\n\t\tcase bcn_req_req:\n\t\t\tRTW_INFO(\"RM: bcn_req_req\\n\");\n\n\t\t\tprm->q.opt.bcn.req_start = rtw_malloc(pbody[p+1]);\n\n\t\t\tif (prm->q.opt.bcn.req_start == NULL) {\n\t\t\t\tRTW_ERR(\"RM: req_start malloc fail!!\\n\");\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tfor (i = 0; i < pbody[p+1]; i++)\n\t\t\t\t*((prm->q.opt.bcn.req_start)+i) =\n\t\t\t\t\tpbody[p+2+i];\n\n\t\t\tprm->q.opt.bcn.req_len = pbody[p+1];\n\t\t\tpopt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];\n\t\t\tbreak;\n\n\t\tcase bcn_req_ac_ch_rep:\n#if (RM_MORE_DBG_MSG)\n\t\t\tRTW_INFO(\"RM: bcn_req_ac_ch_rep\\n\");\n#endif\n\t\t\tpopt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tbreak;\n\n       \t\t}\n\t\tlen = len - (int)pbody[p+1] - 2;\n\t\tp = p + (int)pbody[p+1] + 2;\n#if (RM_MORE_DBG_MSG)\n\t\tRTW_INFO(\"RM: opt_s_elem_len=%d\\n\",len);\n#endif\n\t}\n\n\treturn _SUCCESS;\n}\n\nstatic int rm_parse_meas_req(struct rm_obj *prm, u8 *pbody)\n{\n\tint p; /* position */\n\tint req_len;\n\n\n\treq_len = (int)pbody[1];\n\tp = 5;\n\n\tprm->q.op_class = pbody[p++];\n\tprm->q.ch_num = pbody[p++];\n\tprm->q.rand_intvl = le16_to_cpu(*(u16*)(&pbody[p]));\n\tp+=2;\n\tprm->q.meas_dur = le16_to_cpu(*(u16*)(&pbody[p]));\n\tp+=2;\n\n\tif (prm->q.m_type == bcn_req) {\n\t\t/*\n\t\t * 0: passive\n\t\t * 1: active\n\t\t * 2: bcn_table\n\t\t */\n\t\tprm->q.m_mode = pbody[p++];\n\n\t\t/* BSSID */\n\t\t_rtw_memcpy(&(prm->q.bssid), &pbody[p], 6);\n\t\tp+=6;\n\n\t\t/*\n\t\t * default, used when Reporting detail subelement\n\t\t * is not included in Beacon Request\n\t\t */\n\t\tprm->q.opt.bcn.rep_detail = 2;\n\t}\n\n\tif (req_len-(p-2) <= 0) /* without sub-element */\n\t\treturn _SUCCESS;\n\n\tswitch (prm->q.m_type) {\n\tcase bcn_req:\n\t\trm_parse_bcn_req_s_elem(prm, &pbody[p], req_len-(p-2));\n\t\tbreak;\n\tcase ch_load_req:\n\t\trm_parse_ch_load_s_elem(prm, &pbody[p], req_len-(p-2));\n\t\tbreak;\n\tcase noise_histo_req:\n\t\trm_parse_noise_histo_s_elem(prm, &pbody[p], req_len-(p-2));\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn _SUCCESS;\n}\n\n/* receive measurement request */\nint rm_recv_radio_mens_req(_adapter *padapter,\n\tunion recv_frame *precv_frame, struct sta_info *psta)\n{\n\tstruct rm_obj *prm;\n\tstruct rm_priv *prmpriv = &padapter->rmpriv;\n\tu8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +\n\t\tsizeof(struct rtw_ieee80211_hdr_3addr));\n\tu8 *pmeas_body = &pdiag_body[5];\n\tu8 rmid, update = 0;\n\n\n#if 0\n\t/* search existing rm_obj */\n\trmid = psta->cmn.aid << 16\n\t\t| pdiag_body[2] << 8\n\t\t| RM_SLAVE;\n\n\tprm = rm_get_rmobj(padapter, rmid);\n\tif (prm) {\n\t\tRTW_INFO(\"RM: Found an exist meas rmid=%u\\n\", rmid);\n\t\tupdate = 1;\n\t} else\n#endif\n\tprm = rm_alloc_rmobj(padapter);\n\n\tif (prm == NULL) {\n\t\tRTW_ERR(\"RM: unable to alloc rm obj for requeset\\n\");\n\t\treturn _FALSE;\n\t}\n\n\tprm->psta = psta;\n\tprm->q.diag_token = pdiag_body[2];\n\tprm->q.rpt = le16_to_cpu(*(u16*)(&pdiag_body[3]));\n\n\t/* Figure 8-104 Measurement Requested format */\n\tprm->q.e_id = pmeas_body[0];\n\tprm->q.m_token = pmeas_body[2];\n\tprm->q.m_mode = pmeas_body[3];\n\tprm->q.m_type = pmeas_body[4];\n\n\tprm->rmid = psta->cmn.aid << 16\n\t\t| prm->q.diag_token << 8\n\t\t| RM_SLAVE;\n\n\tRTW_INFO(\"RM: rmid=%x, bssid \" MAC_FMT \"\\n\", prm->rmid,\n\t\tMAC_ARG(prm->psta->cmn.mac_addr));\n\n#if (RM_MORE_DBG_MSG)\n\tRTW_INFO(\"RM: element_id = %d\\n\", prm->q.e_id);\n\tRTW_INFO(\"RM: length = %d\\n\", (int)pmeas_body[1]);\n\tRTW_INFO(\"RM: meas_token = %d\\n\", prm->q.m_token);\n\tRTW_INFO(\"RM: meas_mode = %d\\n\", prm->q.m_mode);\n\tRTW_INFO(\"RM: meas_type = %d\\n\", prm->q.m_type);\n#endif\n\n\tif (prm->q.e_id != _MEAS_REQ_IE_) /* 38 */\n\t\treturn _FALSE;\n\n\tswitch (prm->q.m_type) {\n\tcase bcn_req:\n\t\tRTW_INFO(\"RM: recv beacon_request\\n\");\n\t\tswitch (prm->q.m_mode) {\n\t\tcase bcn_req_passive:\n\t\t\trm_en_cap_chk_and_set(prm, RM_BCN_PASSIVE_MEAS_CAP_EN);\n\t\t\tbreak;\n\t\tcase bcn_req_active:\n\t\t\trm_en_cap_chk_and_set(prm, RM_BCN_ACTIVE_MEAS_CAP_EN);\n\t\t\tbreak;\n\t\tcase bcn_req_bcn_table:\n\t\t\trm_en_cap_chk_and_set(prm, RM_BCN_TABLE_MEAS_CAP_EN);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\trm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase ch_load_req:\n\t\tRTW_INFO(\"RM: recv ch_load_request\\n\");\n\t\trm_en_cap_chk_and_set(prm, RM_CH_LOAD_CAP_EN);\n\t\tbreak;\n\tcase noise_histo_req:\n\t\tRTW_INFO(\"RM: recv noise_histogram_request\\n\");\n\t\trm_en_cap_chk_and_set(prm, RM_NOISE_HISTO_CAP_EN);\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(\"RM: recv unknown request type 0x%02x\\n\",\n\t\t\tprm->q.m_type);\n\t\trm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);\n\t\tgoto done;\n       }\n\trm_parse_meas_req(prm, pmeas_body);\ndone:\n\tif (!update)\n\t\trm_enqueue_rmobj(padapter, prm, _FALSE);\n\n\treturn _SUCCESS;\n}\n\n/* receive measurement report */\nint rm_recv_radio_mens_rep(_adapter *padapter,\n\tunion recv_frame *precv_frame, struct sta_info *psta)\n{\n\tint ret = _FALSE;\n\tstruct rm_obj *prm;\n\tu32 rmid;\n\tu8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +\n\t\tsizeof(struct rtw_ieee80211_hdr_3addr));\n\tu8 *pmeas_body = &pdiag_body[3];\n\n\n\trmid = psta->cmn.aid << 16\n\t\t| pdiag_body[2] << 8\n\t\t| RM_MASTER;\n\n\tprm = rm_get_rmobj(padapter, rmid);\n\tif (prm == NULL)\n\t\treturn _FALSE;\n\n\tprm->p.action_code = pdiag_body[1];\n\tprm->p.diag_token = pdiag_body[2];\n\n\t/* Figure 8-140 Measuremnt Report format */\n\tprm->p.e_id = pmeas_body[0];\n\tprm->p.m_token = pmeas_body[2];\n\tprm->p.m_mode = pmeas_body[3];\n\tprm->p.m_type = pmeas_body[4];\n\n\tRTW_INFO(\"RM: rmid=%x, bssid \" MAC_FMT \"\\n\", prm->rmid,\n\t\tMAC_ARG(prm->psta->cmn.mac_addr));\n\n#if (RM_MORE_DBG_MSG)\n\tRTW_INFO(\"RM: element_id = %d\\n\", prm->p.e_id);\n\tRTW_INFO(\"RM: length = %d\\n\", (int)pmeas_body[1]);\n\tRTW_INFO(\"RM: meas_token = %d\\n\", prm->p.m_token);\n\tRTW_INFO(\"RM: meas_mode = %d\\n\", prm->p.m_mode);\n\tRTW_INFO(\"RM: meas_type = %d\\n\", prm->p.m_type);\n#endif\n\tif (prm->p.e_id != _MEAS_RSP_IE_) /* 39 */\n\t\treturn _FALSE;\n\n\tRTW_INFO(\"RM: recv %s\\n\", rm_type_rep_name(prm->p.m_type));\n\trm_post_event(padapter, prm->rmid, RM_EV_recv_rep);\n\n\treturn ret;\n}\n\nint rm_radio_mens_nb_rep(_adapter *padapter,\n\tunion recv_frame *precv_frame, struct sta_info *psta)\n{\n\tu8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +\n\t\tsizeof(struct rtw_ieee80211_hdr_3addr));\n\tu8 *pmeas_body = &pdiag_body[3];\n\tu32 len = precv_frame->u.hdr.len;\n\tu32 rmid;\n\tstruct rm_obj *prm;\n\n\n\trmid = psta->cmn.aid << 16\n\t\t| pdiag_body[2] << 8\n\t\t| RM_MASTER;\n\n\tprm = rm_get_rmobj(padapter, rmid);\n\tif (prm == NULL)\n\t\treturn _FALSE;\n\n\tprm->p.action_code = pdiag_body[1];\n\tprm->p.diag_token = pdiag_body[2];\n\tprm->p.e_id = pmeas_body[0];\n\n\tRTW_INFO(\"RM: rmid=%x, bssid \" MAC_FMT \"\\n\", prm->rmid,\n\t\tMAC_ARG(prm->psta->cmn.mac_addr));\n\n#if (RM_MORE_DBG_MSG)\n\tRTW_INFO(\"RM: element_id = %d\\n\", prm->p.e_id);\n\tRTW_INFO(\"RM: length = %d\\n\", (int)pmeas_body[1]);\n#endif\n\trm_post_event(padapter, prm->rmid, RM_EV_recv_rep);\n\n#ifdef CONFIG_LAYER2_ROAMING\n\tif (rtw_wnm_btm_candidates_survey(padapter\n\t\t\t,(pdiag_body + 3)\n\t\t\t,(len - sizeof(struct rtw_ieee80211_hdr_3addr))\n\t\t\t,_FALSE) == _FAIL)\n\t\treturn _FALSE;\n#endif\n\trtw_cfg80211_rx_rrm_action(padapter, precv_frame);\n\n\treturn _TRUE;\n}\n\nunsigned int rm_on_action(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tu32 ret = _FAIL;\n\tu8 *pframe = NULL;\n\tu8 *pframe_body = NULL;\n\tu8 action_code = 0;\n\tu8 diag_token = 0;\n\tstruct rtw_ieee80211_hdr_3addr *whdr;\n\tstruct sta_info *psta;\n\n\n\tpframe = precv_frame->u.hdr.rx_data;\n\n\t/* check RA matches or not */\n\tif (!_rtw_memcmp(adapter_mac_addr(padapter),\n\t\tGetAddr1Ptr(pframe), ETH_ALEN))\n\t\tgoto exit;\n\n\twhdr = (struct rtw_ieee80211_hdr_3addr *)pframe;\n\tRTW_INFO(\"RM: %s bssid = \" MAC_FMT \"\\n\",\n\t\t__func__, MAC_ARG(whdr->addr2));\n\n\tpsta = rtw_get_stainfo(&padapter->stapriv, whdr->addr2);\n\n        if (!psta) {\n\t\tRTW_ERR(\"RM: psta not found\\n\");\n                goto exit;\n        }\n\n\tpframe_body = (unsigned char *)(pframe +\n\t\tsizeof(struct rtw_ieee80211_hdr_3addr));\n\n\t/* Figure 8-438 radio measurement request frame Action field format */\n\t/* Category = pframe_body[0] = 5 (Radio Measurement) */\n\taction_code = pframe_body[1];\n\tdiag_token = pframe_body[2];\n\n#if (RM_MORE_DBG_MSG)\n\tRTW_INFO(\"RM: %s radio_action=%x, diag_token=%x\\n\", __func__,\n\t\taction_code, diag_token);\n#endif\n\n\tswitch (action_code) {\n\n\tcase RM_ACT_RADIO_MEAS_REQ:\n\t\tRTW_INFO(\"RM: RM_ACT_RADIO_MEAS_REQ\\n\");\n\t\tret = rm_recv_radio_mens_req(padapter, precv_frame, psta);\n\t\tbreak;\n\n\tcase RM_ACT_RADIO_MEAS_REP:\n\t\tRTW_INFO(\"RM: RM_ACT_RADIO_MEAS_REP\\n\");\n\t\tret = rm_recv_radio_mens_rep(padapter, precv_frame, psta);\n\t\tbreak;\n\n\tcase RM_ACT_LINK_MEAS_REQ:\n\t\tRTW_INFO(\"RM: RM_ACT_LINK_MEAS_REQ\\n\");\n\t\tbreak;\n\n\tcase RM_ACT_LINK_MEAS_REP:\n\t\tRTW_INFO(\"RM: RM_ACT_LINK_MEAS_REP\\n\");\n\t\tbreak;\n\n\tcase RM_ACT_NB_REP_REQ:\n\t\tRTW_INFO(\"RM: RM_ACT_NB_REP_REQ\\n\");\n\t\tbreak;\n\n\tcase RM_ACT_NB_REP_RESP:\n\t\tRTW_INFO(\"RM: RM_ACT_NB_REP_RESP\\n\");\n\t\tret = rm_radio_mens_nb_rep(padapter, precv_frame, psta);\n\t\tbreak;\n\n\tdefault:\n\t\t/* TODO reply incabable */\n\t\tRTW_ERR(\"RM: unknown specturm management action %2x\\n\",\n\t\t\taction_code);\n\t\tbreak;\n\t}\nexit:\n\treturn ret;\n}\n\nstatic u8 *rm_gen_bcn_detail_elem(_adapter *padapter, u8 *pframe,\n\tstruct rm_obj *prm, struct wlan_network *pnetwork,\n\tunsigned int *fr_len)\n{\n\tWLAN_BSSID_EX *pbss = &pnetwork->network;\n\tunsigned int my_len;\n\tint j, k, len;\n\tu8 *plen;\n\tu8 *ptr;\n\tu8 val8, eid;\n\n\n\tmy_len = 0;\n\t/* Reporting Detail values\n\t * 0: No fixed length fields or elements\n\t * 1: All fixed length fields and any requested elements\n\t *    in the Request info element if present\n\t * 2: All fixed length fields and elements\n\t * 3-255: Reserved\n\t */\n\n\t/* report_detail = 0 */\n\tif (prm->q.opt.bcn.rep_detail == 0\n\t\t|| prm->q.opt.bcn.rep_detail > 2) {\n\t\treturn pframe;\n\t}\n\n\t/* ID */\n\tval8 = 1; /* 1:reported frame body */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\tplen = pframe;\n\tval8 = 0;\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\t/* report_detail = 2 */\n\tif (prm->q.opt.bcn.rep_detail == 2) {\n\t\tpframe = rtw_set_fixed_ie(pframe, pbss->IELength - 4,\n\t\t\tpbss->IEs, &my_len); /* -4 remove FCS */\n\t\tgoto done;\n\t}\n\n\t/* report_detail = 1 */\n\t/* all fixed lenght fields */\n\tpframe = rtw_set_fixed_ie(pframe,\n\t\t_FIXED_IE_LENGTH_, pbss->IEs, &my_len);\n\n\tfor (j = 0; j < prm->q.opt.bcn.opt_id_num; j++) {\n\t\tswitch (prm->q.opt.bcn.opt_id[j]) {\n\t\tcase bcn_req_ssid:\n\t\t\t/* SSID */\n#if (RM_MORE_DBG_MSG)\n\t\t\tRTW_INFO(\"RM: bcn_req_ssid\\n\");\n#endif\n\t\t\tpframe = rtw_set_ie(pframe, _SSID_IE_,\n\t\t\t\tpbss->Ssid.SsidLength,\n\t\t\t\tpbss->Ssid.Ssid, &my_len);\n\t\t\tbreak;\n\t\tcase bcn_req_req:\n\t\t\tif (prm->q.opt.bcn.req_start == NULL)\n\t\t\t\tbreak;\n#if (RM_MORE_DBG_MSG)\n\t\t\tRTW_INFO(\"RM: bcn_req_req\");\n#endif\n\t\t\tfor (k=0; k<prm->q.opt.bcn.req_len; k++) {\n\t\t\t\teid = prm->q.opt.bcn.req_start[k];\n\n\t\t\t\tval8 = pbss->IELength - _FIXED_IE_LENGTH_;\n\t\t\t\tptr = rtw_get_ie(pbss->IEs + _FIXED_IE_LENGTH_,\n\t\t\t\t\teid, &len, val8);\n\n\t\t\t\tif (!ptr)\n\t\t\t\t\tcontinue;\n#if (RM_MORE_DBG_MSG)\n\t\t\t\tswitch (eid) {\n\t\t\t\tcase EID_QBSSLoad:\n\t\t\t\t\tRTW_INFO(\"RM: EID_QBSSLoad\\n\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase EID_HTCapability:\n\t\t\t\t\tRTW_INFO(\"RM: EID_HTCapability\\n\");\n\t\t\t\t\tbreak;\n\t\t\t\tcase _MDIE_:\n\t\t\t\t\tRTW_INFO(\"RM: EID_MobilityDomain\\n\");\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tRTW_INFO(\"RM: EID %d todo\\n\",eid);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n#endif\n\t\t\t\tpframe = rtw_set_ie(pframe, eid,\n\t\t\t\t\tlen,ptr+2, &my_len);\n\t\t\t} /* for() */\n\t\t\tbreak;\n\t\tcase bcn_req_ac_ch_rep:\n\t\tdefault:\n\t\t\tRTW_INFO(\"RM: OPT %d TODO\\n\",prm->q.opt.bcn.opt_id[j]);\n\t\t\tbreak;\n\t\t}\n\t}\ndone:\n\t/*\n\t * update my length\n\t * content length does NOT include ID and LEN\n\t */\n\tval8 = my_len - 2;\n\trtw_set_fixed_ie(plen, 1, &val8, &j);\n\n\t/* update length to caller */\n\t*fr_len += my_len;\n\n\treturn pframe;\n}\n\nstatic u8 rm_get_rcpi(struct rm_obj *prm, struct wlan_network *pnetwork)\n{\n\treturn translate_percentage_to_rcpi(\n\t\tpnetwork->network.PhyInfo.SignalStrength);\n}\n\nstatic u8 rm_get_rsni(struct rm_obj *prm, struct wlan_network *pnetwork)\n{\n\tint i;\n\tu8 val8, snr;\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(prm->psta->padapter);\n\n\n\tif (pnetwork->network.PhyInfo.is_cck_rate) {\n\t\t/* current HW doesn't have CCK RSNI */\n\t\t/* 255 indicates RSNI is unavailable */\n\t\tval8 = 255;\n\t} else {\n\t\tsnr = 0;\n\t\tfor (i = 0; i < pHalData->NumTotalRFPath; i++) {\n\t\t\tsnr += pnetwork->network.PhyInfo.rx_snr[i];\n\t\t}\n\t\tsnr = snr / pHalData->NumTotalRFPath;\n\t\tval8 = (u8)(snr + 10)*2;\n\t}\n\treturn val8;\n}\n\nu8 rm_bcn_req_cond_mach(struct rm_obj *prm, struct wlan_network *pnetwork)\n{\n\tu8 val8;\n\n\n\tswitch(prm->q.opt.bcn.rep_cond.cond) {\n\tcase bcn_rep_cond_immediately:\n\t\treturn _SUCCESS;\n\tcase bcn_req_cond_rcpi_greater:\n\t\tval8 = rm_get_rcpi(prm, pnetwork);\n\t\tif (val8 > prm->q.opt.bcn.rep_cond.threshold)\n\t\t\treturn _SUCCESS;\n\t\tbreak;\n\tcase bcn_req_cond_rcpi_less:\n\t\tval8 = rm_get_rcpi(prm, pnetwork);\n\t\tif (val8 < prm->q.opt.bcn.rep_cond.threshold)\n\t\t\treturn _SUCCESS;\n\t\tbreak;\n\tcase bcn_req_cond_rsni_greater:\n\t\tval8 = rm_get_rsni(prm, pnetwork);\n\t\tif (val8 != 255 && val8 > prm->q.opt.bcn.rep_cond.threshold)\n\t\t\treturn _SUCCESS;\n\t\tbreak;\n\tcase bcn_req_cond_rsni_less:\n\t\tval8 = rm_get_rsni(prm, pnetwork);\n\t\tif (val8 != 255 && val8 < prm->q.opt.bcn.rep_cond.threshold)\n\t\t\treturn _SUCCESS;\n\t\tbreak;\n\tdefault:\n\t\tRTW_ERR(\"RM: bcn_req cond %u not support\\n\",\n\t\t\tprm->q.opt.bcn.rep_cond.cond);\n\t\tbreak;\n\t}\n\treturn _FALSE;\n}\n\nstatic u8 *rm_bcn_rep_fill_scan_resule (struct rm_obj *prm,\n\tu8 *pframe, struct wlan_network *pnetwork, unsigned int *fr_len)\n{\n\tint snr, i;\n\tu8 val8, *plen;\n\tu16 val16;\n\tu32 val32;\n\tu64 val64;\n\tPWLAN_BSSID_EX pbss;\n\tunsigned int my_len;\n\t_adapter *padapter = prm->psta->padapter;\n\n\n\tmy_len = 0;\n\t/* meas ID */\n\tval8 = EID_MeasureReport;\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\t/* remember position form elelment length */\n\tplen = pframe;\n\n\t/* meas_rpt_len */\n\t/* default 3 = mode + token + type but no beacon content */\n\tval8 = 3;\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\t/* meas_token */\n\tval8 = prm->q.m_token;\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\t/* meas_rpt_mode F8-141 */\n\tval8 = prm->p.m_mode;\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\t/* meas_type T8-81 */\n\tval8 = bcn_rep;\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\tif (pnetwork == NULL)\n\t\tgoto done;\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &prm->q.op_class, &my_len);\n\n\t/* channel */\n\tpbss = &pnetwork->network;\n\tval8 = pbss->Configuration.DSConfig;\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\t/* Actual Measurement StartTime */\n\tval64 = cpu_to_le64(prm->meas_start_time);\n\tpframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len);\n\n\t/* Measurement Duration */\n\tval16 = prm->meas_end_time - prm->meas_start_time;\n\tval16 = cpu_to_le16(val16);\n\tpframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);\n\n\t/* TODO\n\t * ReportedFrameInformation:\n\t * 0 :beacon or probe rsp\n\t * 1 :pilot frame\n\t */\n\tval8 = 0; /* report frame info */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\t/* RCPI */\n\tval8 = rm_get_rcpi(prm, pnetwork);\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\t/* RSNI */\n\tval8 = rm_get_rsni(prm, pnetwork);\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\t/* BSSID */\n\tpframe = rtw_set_fixed_ie(pframe, 6, (u8 *)&pbss->MacAddress, &my_len);\n\n\t/*\n\t * AntennaID\n\t * 0: unknown\n\t * 255: multiple antenna (Diversity)\n\t */\n\tval8 = 0;\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\t/* ParentTSF */\n\tval32 = prm->meas_start_time + pnetwork->network.PhyInfo.free_cnt;\n\tpframe = rtw_set_fixed_ie(pframe, 4, (u8 *)&val32, &my_len);\n\n\t/*\n\t * Generate Beacon detail\n\t */\n\tpframe = rm_gen_bcn_detail_elem(padapter, pframe,\n\t\tprm, pnetwork, &my_len);\ndone:\n\t/*\n\t * update my length\n\t * content length does NOT include ID and LEN\n\t */\n\tval8 = my_len - 2;\n\trtw_set_fixed_ie(plen, 1, &val8, &i);\n\n\t/* update length to caller */\n\t*fr_len += my_len;\n\n\treturn pframe;\n}\n\nstatic u8 *rm_gen_bcn_rep_ie (struct rm_obj *prm,\n\tu8 *pframe, struct wlan_network *pnetwork, unsigned int *fr_len)\n{\n\tint snr, i;\n\tu8 val8, *plen;\n\tu16 val16;\n\tu32 val32;\n\tu64 val64;\n\tunsigned int my_len;\n\t_adapter *padapter = prm->psta->padapter;\n\n\n\tmy_len = 0;\n\tplen = pframe + 1;\n\tpframe = rtw_set_fixed_ie(pframe, 7, &prm->p.e_id, &my_len);\n\n\t/* Actual Measurement StartTime */\n\tval64 = cpu_to_le64(prm->meas_start_time);\n\tpframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len);\n\n\t/* Measurement Duration */\n\tval16 = prm->meas_end_time - prm->meas_start_time;\n\tval16 = cpu_to_le16(val16);\n\tpframe = rtw_set_fixed_ie(pframe, 2, (u8*)&val16, &my_len);\n\n\t/* TODO\n\t* ReportedFrameInformation:\n\t* 0 :beacon or probe rsp\n\t* 1 :pilot frame\n\t*/\n\tval8 = 0; /* report frame info */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\t/* RCPI */\n\tval8 = rm_get_rcpi(prm, pnetwork);\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\t/* RSNI */\n\tval8 = rm_get_rsni(prm, pnetwork);\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\t/* BSSID */\n\tpframe = rtw_set_fixed_ie(pframe, 6,\n\t\t(u8 *)&pnetwork->network.MacAddress, &my_len);\n\n\t/*\n\t * AntennaID\n\t * 0: unknown\n\t * 255: multiple antenna (Diversity)\n\t */\n\tval8 = 0;\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\t/* ParentTSF */\n\tval32 = prm->meas_start_time + pnetwork->network.PhyInfo.free_cnt;\n\tpframe = rtw_set_fixed_ie(pframe, 4, (u8 *)&val32, &my_len);\n\n\t/* Generate Beacon detail */\n\tpframe = rm_gen_bcn_detail_elem(padapter, pframe,\n\t\tprm, pnetwork, &my_len);\ndone:\n\t/*\n\t* update my length\n\t* content length does NOT include ID and LEN\n\t*/\n\tval8 = my_len - 2;\n\trtw_set_fixed_ie(plen, 1, &val8, &i);\n\n\t/* update length to caller */\n\t*fr_len += my_len;\n\n\treturn pframe;\n}\n\nstatic int retrieve_scan_result(struct rm_obj *prm)\n{\n\t_irqL irqL;\n\t_list *plist, *phead;\n\t_queue *queue;\n\t_adapter *padapter = prm->psta->padapter;\n\tstruct rtw_ieee80211_channel *pch_set;\n\tstruct wlan_network *pnetwork = NULL;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tint i, meas_ch_num=0;\n\tPWLAN_BSSID_EX pbss;\n\tunsigned int matched_network;\n\tint len, my_len;\n\tu8 buf_idx, *pbuf = NULL, *tmp_buf = NULL;\n\n\n\ttmp_buf = rtw_malloc(MAX_XMIT_EXTBUF_SZ);\n\tif (tmp_buf == NULL)\n\t\treturn 0;\n\n\tmy_len = 0;\n\tbuf_idx = 0;\n\tmatched_network = 0;\n\tqueue = &(pmlmepriv->scanned_queue);\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\n\t/* get requested measurement channel set */\n\tpch_set = prm->q.ch_set;\n\tmeas_ch_num = prm->q.ch_set_ch_amount;\n\n\t/* search scan queue to find requested SSID */\n\twhile (1) {\n\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\t\tpbss = &pnetwork->network;\n\n\t\t/*\n\t\t* report network if requested channel set contains\n\t\t* the channel matchs selected network\n\t\t*/\n\t\tif (rtw_chset_search_ch(adapter_to_chset(padapter),\n\t\t\tpbss->Configuration.DSConfig) == 0)\n\t\t\tgoto next;\n\n\t\tif (rtw_mlme_band_check(padapter, pbss->Configuration.DSConfig)\n\t\t\t== _FALSE)\n\t\t\tgoto next;\n\n\t\tif (rtw_validate_ssid(&(pbss->Ssid)) == _FALSE)\n\t\t\tgoto next;\n\n\t\t/* go through measurement requested channels */\n\t\tfor (i = 0; i < meas_ch_num; i++) {\n\n\t\t\t/* match channel */\n\t\t\tif (pch_set[i].hw_value != pbss->Configuration.DSConfig)\n\t\t\t\tcontinue;\n\n\t\t\t/* match bssid */\n\t\t\tif (is_wildcard_bssid(prm->q.bssid) == FALSE)\n\t\t\t\tif (_rtw_memcmp(prm->q.bssid,\n\t\t\t\t\tpbss->MacAddress, 6) == _FALSE) {\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t/*\n\t\t\t * default wildcard SSID. wildcard SSID:\n\t\t\t * A SSID value (null) used to represent all SSIDs\n\t\t\t */\n\n\t\t\t/* match ssid */\n\t\t\tif ((prm->q.opt.bcn.ssid.SsidLength > 0) &&\n\t\t\t\t_rtw_memcmp(prm->q.opt.bcn.ssid.Ssid,\n\t\t\t\tpbss->Ssid.Ssid,\n\t\t\t\tprm->q.opt.bcn.ssid.SsidLength) == _FALSE)\n\t\t\t\tcontinue;\n\n\t\t\t/* match condition */\n\t\t\tif (rm_bcn_req_cond_mach(prm, pnetwork) == _FALSE) {\n\t\t\t\tRTW_INFO(\"RM: condition mismatch ch %u ssid %s bssid \"MAC_FMT\"\\n\",\n\t\t\t\t\tpch_set[i].hw_value, pbss->Ssid.Ssid,\n\t\t\t\t\tMAC_ARG(pbss->MacAddress));\n\t\t\t\tRTW_INFO(\"RM: condition %u:%u\\n\",\n\t\t\t\t\tprm->q.opt.bcn.rep_cond.cond,\n\t\t\t\t\tprm->q.opt.bcn.rep_cond.threshold);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\t/* Found a matched SSID */\n\t\t\tmatched_network++;\n\n\t\t\tRTW_INFO(\"RM: ch %u Found %s bssid \"MAC_FMT\"\\n\",\n\t\t\t\tpch_set[i].hw_value, pbss->Ssid.Ssid,\n\t\t\t\tMAC_ARG(pbss->MacAddress));\n\n\t\t\tlen = 0;\n\t\t\t_rtw_memset(tmp_buf, 0, MAX_XMIT_EXTBUF_SZ);\n\t\t\trm_gen_bcn_rep_ie(prm, tmp_buf, pnetwork, &len);\nnew_packet:\n\t\t\tif (my_len == 0) {\n\t\t\t\tpbuf = rtw_malloc(MAX_XMIT_EXTBUF_SZ);\n\t\t\t\tif (pbuf == NULL)\n\t\t\t\t\tgoto fail;\n\t\t\t\tprm->buf[buf_idx].pbuf = pbuf;\n\t\t\t}\n\n\t\t\tif ((MAX_XMIT_EXTBUF_SZ - (my_len+len+24+4)) > 0) {\n\t\t\t\tpbuf = rtw_set_fixed_ie(pbuf,\n\t\t\t\t\tlen, tmp_buf, &my_len);\n\t\t\t\tprm->buf[buf_idx].len = my_len;\n\t\t\t} else {\n\t\t\t\tif (my_len == 0) /* not enough space */\n\t\t\t\t\tgoto fail;\n\n\t\t\t\tmy_len = 0;\n\t\t\t\tbuf_idx++;\n\t\t\t\tgoto new_packet;\n\t\t\t}\n\t\t} /* for() */\nnext:\n\t\tplist = get_next(plist);\n\t} /* while() */\nfail:\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tif (tmp_buf)\n\t\trtw_mfree(tmp_buf, MAX_XMIT_EXTBUF_SZ);\n\n\tRTW_INFO(\"RM: Found %d matched %s\\n\", matched_network,\n\t\tprm->q.opt.bcn.ssid.Ssid);\n\n\tif (prm->buf[buf_idx].pbuf)\n\t\treturn buf_idx+1;\n\n\treturn 0;\n}\n\nint issue_beacon_rep(struct rm_obj *prm)\n{\n\tint i, my_len;\n\tu8 *pframe;\n\t_adapter *padapter = prm->psta->padapter;\n\tstruct pkt_attrib *pattr;\n\tstruct xmit_frame *pmgntframe;\n\tstruct xmit_priv *pxmitpriv = &(padapter->xmitpriv);\n\tint pkt_num;\n\n\n\tpkt_num = retrieve_scan_result(prm);\n\n\tif (pkt_num == 0) {\n\t\tissue_null_reply(prm);\n\t\treturn _SUCCESS;\n\t}\n\n\tfor (i=0;i<pkt_num;i++) {\n\n\t\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\t\tif (pmgntframe == NULL) {\n\t\t\tRTW_ERR(\"RM: %s alloc xmit_frame fail\\n\",__func__);\n\t\t\tgoto fail;\n\t\t}\n\t\tpattr = &pmgntframe->attrib;\n\t\tpframe = build_wlan_hdr(padapter,\n\t\t\tpmgntframe, prm->psta, WIFI_ACTION);\n\t\tpframe = rtw_set_fixed_ie(pframe,\n\t\t\t3, &prm->p.category, &pattr->pktlen);\n\n\t\tmy_len = 0;\n\t\tpframe = rtw_set_fixed_ie(pframe,\n\t\t\tprm->buf[i].len, prm->buf[i].pbuf, &my_len);\n\n\t\tpattr->pktlen += my_len;\n\t\tpattr->last_txcmdsz = pattr->pktlen;\n\t\tdump_mgntframe(padapter, pmgntframe);\n\t}\nfail:\n\tfor (i=0;i<pkt_num;i++) {\n\t\tif (prm->buf[i].pbuf) {\n\t\t\trtw_mfree(prm->buf[i].pbuf, MAX_XMIT_EXTBUF_SZ);\n\t\t\tprm->buf[i].pbuf = NULL;\n\t\t\tprm->buf[i].len = 0;\n\t\t}\n\t}\n\treturn _SUCCESS;\n}\n\n/* neighbor request */\nint issue_nb_req(struct rm_obj *prm)\n{\n\t_adapter *padapter = prm->psta->padapter;\n\tstruct sta_info *psta = prm->psta;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tstruct xmit_frame *pmgntframe = NULL;\n\tstruct pkt_attrib *pattr = NULL;\n\tu8 val8;\n\tu8 *pframe = NULL;\n\n\n\tRTW_INFO(\"RM: %s\\n\", __func__);\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL) {\n\t\tRTW_ERR(\"RM: %s alloc xmit_frame fail\\n\",__func__);\n\t\treturn _FALSE;\n\t}\n\tpattr = &pmgntframe->attrib;\n\tpframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION);\n\tpframe = rtw_set_fixed_ie(pframe,\n\t\t3, &prm->q.category, &pattr->pktlen);\n\n\tif (prm->q.pssid) {\n\n\t\tu8 sub_ie[64] = {0};\n\t\tu8 *pie = &sub_ie[2];\n\n\t\tRTW_INFO(\"RM: Send NB Req to \"MAC_FMT\" for(SSID) %s searching\\n\",\n\t\t\tMAC_ARG(pmlmepriv->cur_network.network.MacAddress),\n\t\t\tpmlmepriv->cur_network.network.Ssid.Ssid);\n\n\t\tval8 = strlen(prm->q.pssid);\n\t\tsub_ie[0] = 0; /*SSID*/\n\t\tsub_ie[1] = val8;\n\n\t\t_rtw_memcpy(pie, prm->q.pssid, val8);\n\n\t\tpframe = rtw_set_fixed_ie(pframe, val8 + 2,\n\t\t\tsub_ie, &pattr->pktlen);\n\t} else {\n\n\t\tif (!pmlmepriv->cur_network.network.Ssid.SsidLength)\n\t\t\tRTW_INFO(\"RM: Send NB Req to \"MAC_FMT\"\\n\",\n\t\t\t\tMAC_ARG(pmlmepriv->cur_network.network.MacAddress));\n\t\telse {\n\t\t\tu8 sub_ie[64] = {0};\n\t\t\tu8 *pie = &sub_ie[2];\n\n\t\t\tRTW_INFO(\"RM: Send NB Req to \"MAC_FMT\" for(SSID) %s searching\\n\",\n\t\t\t\tMAC_ARG(pmlmepriv->cur_network.network.MacAddress),\n\t\t\t\tpmlmepriv->cur_network.network.Ssid.Ssid);\n\n\t\t\tsub_ie[0] = 0; /*SSID*/\n\t\t\tsub_ie[1] = pmlmepriv->cur_network.network.Ssid.SsidLength;\n\n\t\t\t_rtw_memcpy(pie, pmlmepriv->cur_network.network.Ssid.Ssid,\n\t\t\t\tpmlmepriv->cur_network.network.Ssid.SsidLength);\n\n\t\t\tpframe = rtw_set_fixed_ie(pframe,\n\t\t\t\tpmlmepriv->cur_network.network.Ssid.SsidLength + 2,\n\t\t\t\tsub_ie, &pattr->pktlen);\n\t\t}\n\t}\n\n\tpattr->last_txcmdsz = pattr->pktlen;\n\tdump_mgntframe(padapter, pmgntframe);\n\n\treturn _SUCCESS;\n}\n\nstatic u8 *rm_gen_bcn_req_s_elem(_adapter *padapter,\n\tu8 *pframe, unsigned int *fr_len)\n{\n\tu8 val8;\n\tunsigned int my_len = 0;\n\tu8 bssid[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\n\n\tval8 = bcn_req_active; /* measurement mode T8-64 */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\tpframe = rtw_set_fixed_ie(pframe, 6, bssid, &my_len);\n\n\t/* update length to caller */\n\t*fr_len += my_len;\n\n\t/* optional subelements */\n\treturn pframe;\n}\n\nstatic u8 *rm_gen_ch_load_req_s_elem(_adapter *padapter,\n\tu8 *pframe, unsigned int *fr_len)\n{\n\tu8 val8;\n\tunsigned int my_len = 0;\n\n\n\tval8 = 1; /* 1: channel load T8-60 */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\tval8 = 2; /* channel load length = 2 (extensible)  */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\tval8 = 0; /* channel load condition : 0 (issue when meas done) T8-61 */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\tval8 = 0; /* channel load reference value : 0 */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\t/* update length to caller */\n\t*fr_len += my_len;\n\n\treturn pframe;\n}\n\nstatic u8 *rm_gen_noise_histo_req_s_elem(_adapter *padapter,\n\tu8 *pframe, unsigned int *fr_len)\n{\n\tu8 val8;\n\tunsigned int my_len = 0;\n\n\n\tval8 = 1; /* 1: noise histogram T8-62 */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\tval8 = 2; /* noise histogram length = 2 (extensible)  */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\tval8 = 0; /* noise histogram condition : 0 (issue when meas done) T8-63 */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\tval8 = 0; /* noise histogram reference value : 0 */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\n\t/* update length to caller */\n\t*fr_len += my_len;\n\n\treturn pframe;\n}\n\nint issue_radio_meas_req(struct rm_obj *prm)\n{\n\tu8 val8;\n\tu8 *pframe;\n\tu8 *plen;\n\tu16 val16;\n\tint my_len, i;\n\tstruct xmit_frame *pmgntframe;\n\tstruct pkt_attrib *pattr;\n\t_adapter *padapter = prm->psta->padapter;\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\n\n\tRTW_INFO(\"RM: %s - %s\\n\", __func__, rm_type_req_name(prm->q.m_type));\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL) {\n\t\tRTW_ERR(\"RM: %s alloc xmit_frame fail\\n\",__func__);\n\t\treturn _FALSE;\n\t}\n\tpattr = &pmgntframe->attrib;\n\tpframe = build_wlan_hdr(padapter, pmgntframe, prm->psta, WIFI_ACTION);\n\tpframe = rtw_set_fixed_ie(pframe, 3, &prm->q.category, &pattr->pktlen);\n\n\t/* repeat */\n\tval16 = cpu_to_le16(prm->q.rpt);\n\tpframe = rtw_set_fixed_ie(pframe, 2,\n\t\t(unsigned char *)&(val16), &pattr->pktlen);\n\n\tmy_len = 0;\n\tplen = pframe + 1;\n\tpframe = rtw_set_fixed_ie(pframe, 7, &prm->q.e_id, &my_len);\n\n\t/* random interval */\n\tval16 = 100; /* 100 TU */\n\tval16 = cpu_to_le16(val16);\n\tpframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);\n\n\t/* measurement duration */\n\tval16 = 100;\n\tval16 = cpu_to_le16(val16);\n\tpframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);\n\n\t/* optional subelement */\n\tswitch (prm->q.m_type) {\n\tcase bcn_req:\n\t\tpframe = rm_gen_bcn_req_s_elem(padapter, pframe, &my_len);\n\t\tbreak;\n\tcase ch_load_req:\n\t\tpframe = rm_gen_ch_load_req_s_elem(padapter, pframe, &my_len);\n\t\tbreak;\n\tcase noise_histo_req:\n\t\tpframe = rm_gen_noise_histo_req_s_elem(padapter,\n\t\t\tpframe, &my_len);\n\t\tbreak;\n\tcase basic_req:\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* length */\n\tval8 = (u8)my_len - 2;\n\trtw_set_fixed_ie(plen, 1, &val8, &i);\n\n\tpattr->pktlen += my_len;\n\n\tpattr->last_txcmdsz = pattr->pktlen;\n\tdump_mgntframe(padapter, pmgntframe);\n\n\treturn _SUCCESS;\n}\n\n/* noise histogram */\nstatic u8 rm_get_anpi(struct rm_obj *prm, struct wlan_network *pnetwork)\n{\n\treturn translate_percentage_to_rcpi(\n\t\tpnetwork->network.PhyInfo.SignalStrength);\n}\n\nint rm_radio_meas_report_cond(struct rm_obj *prm)\n{\n\tu8 val8;\n\tint i;\n\n\n\tswitch (prm->q.m_type) {\n\tcase ch_load_req:\n\n\t\tval8 = prm->p.ch_load;\n\t\tswitch (prm->q.opt.clm.rep_cond.cond) {\n\t\tcase ch_load_cond_immediately:\n\t\t\treturn _SUCCESS;\n\t\tcase ch_load_cond_anpi_equal_greater:\n\t\t\tif (val8 >= prm->q.opt.clm.rep_cond.threshold)\n\t\t\t\treturn _SUCCESS;\n\t\tcase ch_load_cond_anpi_equal_less:\n\t\t\tif (val8 <= prm->q.opt.clm.rep_cond.threshold)\n\t\t\t\treturn _SUCCESS;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase noise_histo_req:\n\t\tval8 = prm->p.anpi;\n\t\tswitch (prm->q.opt.nhm.rep_cond.cond) {\n\t\tcase noise_histo_cond_immediately:\n\t\t\treturn _SUCCESS;\n\t\tcase noise_histo_cond_anpi_equal_greater:\n\t\t\tif (val8 >= prm->q.opt.nhm.rep_cond.threshold)\n\t\t\t\treturn _SUCCESS;\n\t\t\tbreak;\n\t\tcase noise_histo_cond_anpi_equal_less:\n\t\t\tif (val8 <= prm->q.opt.nhm.rep_cond.threshold)\n\t\t\t\treturn _SUCCESS;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn _FAIL;\n}\n\nint retrieve_radio_meas_result(struct rm_obj *prm)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(prm->psta->padapter);\n\tint i, ch = -1;\n\tu8 val8;\n\n\n\tch = rtw_chset_search_ch(adapter_to_chset(prm->psta->padapter),\n\t\tprm->q.ch_num);\n\n\tif ((ch == -1) || (ch >= MAX_CHANNEL_NUM)) {\n\t\tRTW_ERR(\"RM: get ch(CH:%d) fail\\n\", prm->q.ch_num);\n\t\tch = 0;\n\t}\n\n\tswitch (prm->q.m_type) {\n\tcase ch_load_req:\n#ifdef CONFIG_RTW_ACS\n\t\tval8 = hal_data->acs.clm_ratio[ch];\n#else\n\t\tval8 = 0;\n#endif\n\t\tprm->p.ch_load = val8;\n\t\tbreak;\n\tcase noise_histo_req:\n#ifdef CONFIG_RTW_ACS\n\t\t/* ANPI */\n\t\tprm->p.anpi = hal_data->acs.nhm_ratio[ch];\n\n\t\t/* IPI 0~10 */\n\t\tfor (i=0;i<11;i++)\n\t\t\tprm->p.ipi[i] = hal_data->acs.nhm[ch][i];\n\t\t\n#else\n\t\tval8 = 0;\n\t\tprm->p.anpi = val8;\n\t\tfor (i=0;i<11;i++)\n\t\t\tprm->p.ipi[i] = val8;\n#endif\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn _SUCCESS;\n}\n\nint issue_radio_meas_rep(struct rm_obj *prm)\n{\n\tu8 val8;\n\tu8 *pframe;\n\tu8 *plen;\n\tu16 val16;\n\tu64 val64;\n\tunsigned int my_len;\n\t_adapter *padapter = prm->psta->padapter;\n\tstruct xmit_frame *pmgntframe;\n\tstruct pkt_attrib *pattr;\n\tstruct xmit_priv *pxmitpriv = &(padapter->xmitpriv);\n\tstruct sta_info *psta = prm->psta;\n\tint i;\n\n\n\tRTW_INFO(\"RM: %s\\n\", __func__);\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL) {\n\t\tRTW_ERR(\"RM: ERR %s alloc xmit_frame fail\\n\",__func__);\n\t\treturn _FALSE;\n\t}\n\tpattr = &pmgntframe->attrib;\n\tpframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION);\n\tpframe = rtw_set_fixed_ie(pframe, 3,\n\t\t&prm->p.category, &pattr->pktlen);\n\n\tmy_len = 0;\n\tplen = pframe + 1;\n\tpframe = rtw_set_fixed_ie(pframe, 7, &prm->p.e_id, &my_len);\n\n\t/* Actual Meas start time - 8 bytes */\n\tval64 = cpu_to_le64(prm->meas_start_time);\n\tpframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len);\n\n\t/* measurement duration */\n\tval16 = prm->meas_end_time - prm->meas_start_time;\n\tval16 = cpu_to_le16(val16);\n\tpframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);\n\n\t/* optional subelement */\n\tswitch (prm->q.m_type) {\n\tcase ch_load_req:\n\t\tval8 = prm->p.ch_load;\n\t\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\t\tbreak;\n\tcase noise_histo_req:\n\t\t/*\n\t\t * AntennaID\n\t\t * 0: unknown\n\t\t * 255: multiple antenna (Diversity)\n\t\t */\n\t\tval8 = 0;\n\t\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\t\t/* ANPI */\n\t\tval8 = prm->p.anpi;\n\t\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\t\t/* IPI 0~10 */\n\t\tfor (i=0;i<11;i++) {\n\t\t\tval8 = prm->p.ipi[i];\n\t\t\tpframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\ndone:\n\t/* length */\n\tval8 = (u8)my_len-2;\n\trtw_set_fixed_ie(plen, 1, &val8, &i); /* use variable i to ignore it */\n\n\tpattr->pktlen += my_len;\n\tpattr->last_txcmdsz = pattr->pktlen;\n\tdump_mgntframe(padapter, pmgntframe);\n\n\treturn _SUCCESS;\n}\n\nvoid rtw_ap_parse_sta_rm_en_cap(_adapter *padapter,\n\tstruct sta_info *psta, struct rtw_ieee802_11_elems *elem)\n{\n\tif (elem->rm_en_cap) {\n\t\tRTW_INFO(\"assoc.rm_en_cap=\"RM_CAP_FMT\"\\n\",\n\t\t\tRM_CAP_ARG(elem->rm_en_cap));\n\t\t_rtw_memcpy(psta->rm_en_cap,\n\t\t\t(elem->rm_en_cap), elem->rm_en_cap_len);\n\t}\n}\n\nvoid RM_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)\n{\n\tint i;\n\n\t_rtw_memcpy(&padapter->rmpriv.rm_en_cap_assoc, pIE->data, pIE->Length);\n\tRTW_INFO(\"assoc.rm_en_cap=\"RM_CAP_FMT\"\\n\", RM_CAP_ARG(pIE->data));\n}\n\n/* Debug command */\n\n#if (RM_SUPPORT_IWPRIV_DBG)\nstatic int hex2num(char c)\n{\n\tif (c >= '0' && c <= '9')\n\t\treturn c - '0';\n\tif (c >= 'a' && c <= 'f')\n\t\treturn c - 'a' + 10;\n\tif (c >= 'A' && c <= 'F')\n\t\treturn c - 'A' + 10;\n\treturn -1;\n}\n\nint hex2byte(const char *hex)\n{\n\tint a, b;\n\ta = hex2num(*hex++);\n\tif (a < 0)\n\t\treturn -1;\n\tb = hex2num(*hex++);\n\tif (b < 0)\n\t\treturn -1;\n\treturn (a << 4) | b;\n}\n\nstatic char * hwaddr_parse(char *txt, u8 *addr)\n{\n\tsize_t i;\n\n\tfor (i = 0; i < ETH_ALEN; i++) {\n\t\tint a;\n\n\t\ta = hex2byte(txt);\n\t\tif (a < 0)\n\t\t\treturn NULL;\n\t\ttxt += 2;\n\t\taddr[i] = a;\n\t\tif (i < ETH_ALEN - 1 && *txt++ != ':')\n\t\t\treturn NULL;\n\t}\n\treturn txt;\n}\n\nvoid rm_dbg_list_sta(_adapter *padapter, char *s)\n{\n\tint i;\n\t_irqL irqL;\n\tstruct sta_info *psta;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\t_list *plist, *phead;\n\n\n\tsprintf(pstr(s), \"\\n\");\n\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\tfor (i = 0; i < NUM_STA; i++) {\n\t\tphead = &(pstapriv->sta_hash[i]);\n\t\tplist = get_next(phead);\n\n\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\tpsta = LIST_CONTAINOR(plist,\n\t\t\t\tstruct sta_info, hash_list);\n\n\t\t\tplist = get_next(plist);\n\n\t\t\tsprintf(pstr(s), \"=========================================\\n\");\n\t\t\tsprintf(pstr(s), \"mac=\" MAC_FMT \"\\n\",\n\t\t\t\tMAC_ARG(psta->cmn.mac_addr));\n\t\t\tsprintf(pstr(s), \"state=0x%x, aid=%d, macid=%d\\n\",\n\t\t\t\tpsta->state, psta->cmn.aid, psta->cmn.mac_id);\n\t\t\tsprintf(pstr(s), \"rm_cap=\"RM_CAP_FMT\"\\n\",\n\t\t\t\tRM_CAP_ARG(psta->rm_en_cap));\n\t\t}\n\n\t}\n\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\tsprintf(pstr(s), \"=========================================\\n\");\n}\n\nvoid rm_dbg_help(_adapter *padapter, char *s)\n{\n\tint i;\n\n\n\tsprintf(pstr(s), \"\\n\");\n\tsprintf(pstr(s), \"rrm list_sta\\n\");\n\tsprintf(pstr(s), \"rrm list_meas\\n\");\n\n\tsprintf(pstr(s), \"rrm add_meas <aid=1|mac=>,m=<bcn|clm|nhm|nb>,rpt=\\n\");\n\tsprintf(pstr(s), \"rrm run_meas <aid=1|evid=>\\n\");\n\tsprintf(pstr(s), \"rrm del_meas\\n\");\n\n\tsprintf(pstr(s), \"rrm run_meas rmid=xxxx,ev=xx\\n\");\n\tsprintf(pstr(s), \"rrm activate\\n\");\n\n\tfor (i=0;i<RM_EV_max;i++)\n\t\tsprintf(pstr(s), \"\\t%2d %s\\n\",i, rm_event_name(i) );\n\tsprintf(pstr(s), \"\\n\");\n}\n\nstruct sta_info *rm_get_sta(_adapter *padapter, u16 aid, u8* pbssid)\n{\n\tint i;\n\t_irqL irqL;\n\tstruct sta_info *psta = NULL;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\t_list *plist, *phead;\n\n\n\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\tfor (i = 0; i < NUM_STA; i++) {\n\t\tphead = &(pstapriv->sta_hash[i]);\n\t\tplist = get_next(phead);\n\n\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\tpsta = LIST_CONTAINOR(plist,\n\t\t\t\tstruct sta_info, hash_list);\n\n\t\t\tplist = get_next(plist);\n\n\t\t\tif (psta->cmn.aid == aid)\n\t\t\t\tgoto done;\n\n\t\t\tif (pbssid && _rtw_memcmp(psta->cmn.mac_addr,\n\t\t\t\tpbssid, 6))\n\t\t\t\tgoto done;\n\t\t}\n\n\t}\n\tpsta = NULL;\ndone:\n\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\treturn psta;\n}\n\nstatic int rm_dbg_modify_meas(_adapter *padapter, char *s)\n{\n\tstruct rm_priv *prmpriv = &padapter->rmpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;\n\tstruct rm_obj *prm;\n\tstruct sta_info *psta;\n\tchar *pmac, *ptr, *paid, *prpt, *pnbp, *pclm, *pnhm, *pbcn;\n\tunsigned val;\n\tu8 bssid[ETH_ALEN];\n\n\n\t/* example :\n\t* rrm add_meas <aid=1|mac=>,m=<nb|clm|nhm|bcn>,<rept=>\n\t* rrm run_meas <aid=1|evid=>\n\t*/\n\tpaid = strstr(s, \"aid=\");\n\tpmac = strstr(s, \"mac=\");\n\tpbcn = strstr(s, \"m=bcn\");\n\tpclm = strstr(s, \"m=clm\");\n\tpnhm = strstr(s, \"m=nhm\");\n\tpnbp = strstr(s, \"m=nb\");\n\tprpt = strstr(s, \"rpt=\");\n\n\t/* set all ',' to NULL (end of line) */\n\tptr = s;\n\twhile (ptr) {\n\t\tptr = strchr(ptr, ',');\n\t\tif (ptr) {\n\t\t\t*(ptr) = 0x0;\n\t\t\tptr++;\n\t\t}\n\t}\n\tprm = (struct rm_obj *)prmpriv->prm_sel;\n\tprm->q.m_token = 1;\n\tpsta = prm->psta;\n\n\tif (paid) { /* find sta_info according to aid */\n\t\tpaid += 4; /* skip aid= */\n\t\tsscanf(paid, \"%u\", &val); /* aid=x */\n\t\tpsta = rm_get_sta(padapter, val, NULL);\n\n\t} else if (pmac) { /* find sta_info according to bssid */\n\t\tpmac += 4; /* skip mac= */\n\t\tif (hwaddr_parse(pmac, bssid) == NULL) {\n\t\t\tsprintf(pstr(s), \"Err: \\nincorrect mac format\\n\");\n\t\t\treturn _FAIL;\n\t\t}\n\t\tpsta = rm_get_sta(padapter, 0xff, bssid);\n\t}\n\n\tif (psta) {\n\t\tprm->psta = psta;\n\n#if 0\n\t\tprm->q.diag_token = psta->rm_diag_token++;\n#else\n\t\t/* TODO dialog should base on sta_info */\n\t\tprm->q.diag_token = pmlmeinfo->dialogToken++;\n#endif\n\t\tprm->rmid = psta->cmn.aid << 16\n\t\t\t| prm->q.diag_token << 8\n\t\t\t| RM_MASTER;\n\t} else\n\t\treturn _FAIL;\n\n\tprm->q.action_code = RM_ACT_RADIO_MEAS_REQ;\n\tif (pbcn) {\n\t\tprm->q.m_type = bcn_req;\n\t} else if (pnhm) {\n\t\tprm->q.m_type = noise_histo_req;\n\t} else if (pclm) {\n\t\tprm->q.m_type = ch_load_req;\n\t} else if (pnbp) {\n\t\tprm->q.action_code = RM_ACT_NB_REP_REQ;\n\t} else\n\t\treturn _FAIL;\n\n\tif (prpt) {\n\t\tprpt += 4; /* skip rpt= */\n\t\tsscanf(prpt, \"%u\", &val);\n\t\tprm->q.rpt = (u8)val;\n\t}\n\n\treturn _SUCCESS;\n}\n\nstatic void rm_dbg_activate_meas(_adapter *padapter, char *s)\n{\n\tstruct rm_priv *prmpriv = &(padapter->rmpriv);\n\tstruct rm_obj *prm;\n\n\n\tif (prmpriv->prm_sel == NULL) {\n\t\tsprintf(pstr(s), \"\\nErr: No inActivate measurement\\n\");\n\t\treturn;\n\t}\n\tprm = (struct rm_obj *)prmpriv->prm_sel;\n\n\t/* verify attributes */\n\tif (prm->psta == NULL) {\n\t\tsprintf(pstr(s), \"\\nErr: inActivate meas has no psta\\n\");\n\t\treturn;\n\t}\n\n\t/* measure current channel */\n\tprm->q.ch_num = padapter->mlmeextpriv.cur_channel;\n\tprm->q.op_class = rm_get_oper_class_via_ch(prm->q.ch_num);\n\n\t/* enquee rmobj */\n\trm_enqueue_rmobj(padapter, prm, _FALSE);\n\n\tsprintf(pstr(s), \"\\nActivate rmid=%x, state=%s, meas_type=%s\\n\",\n\t\tprm->rmid, rm_state_name(prm->state),\n\t\trm_type_req_name(prm->q.m_type));\n\n\tsprintf(pstr(s), \"aid=%d, mac=\" MAC_FMT \"\\n\",\n\t\tprm->psta->cmn.aid, MAC_ARG(prm->psta->cmn.mac_addr));\n\n\t/* clearn inActivate prm info */\n\tprmpriv->prm_sel = NULL;\n}\n\nstatic void rm_dbg_add_meas(_adapter *padapter, char *s)\n{\n\tstruct rm_priv *prmpriv = &(padapter->rmpriv);\n\tstruct rm_obj *prm;\n\tchar *pact;\n\n\n\t/* example :\n\t* rrm add_meas <aid=1|mac=>,m=<nb_req|clm_req|nhm_req>\n\t* rrm run_meas <aid=1|evid=>\n\t*/\n\tprm = (struct rm_obj *)prmpriv->prm_sel;\n\tif (prm == NULL)\n\t\tprm = rm_alloc_rmobj(padapter);\n\n\tif (prm == NULL) {\n\t\tsprintf(pstr(s), \"\\nErr: alloc meas fail\\n\");\n\t\treturn;\n\t}\n\n        prmpriv->prm_sel = prm;\n\n\tpact = strstr(s, \"act\");\n\tif (rm_dbg_modify_meas(padapter, s) == _FAIL) {\n\n\t\tsprintf(pstr(s), \"\\nErr: add meas fail\\n\");\n\t\trm_free_rmobj(prm);\n\t\tprmpriv->prm_sel = NULL;\n\t\treturn;\n\t}\n\tprm->q.category = RTW_WLAN_CATEGORY_RADIO_MEAS;\n\tprm->q.e_id = _MEAS_REQ_IE_; /* 38 */\n\n\tif (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ)\n\t\tsprintf(pstr(s), \"\\nAdd rmid=%x, meas_type=%s ok\\n\",\n\t\t\tprm->rmid, rm_type_req_name(prm->q.m_type));\n\telse  if (prm->q.action_code == RM_ACT_NB_REP_REQ) \n\t\tsprintf(pstr(s), \"\\nAdd rmid=%x, meas_type=bcn_req ok\\n\",\n\t\t\tprm->rmid);\n\n\tif (prm->psta)\n\t\tsprintf(pstr(s), \"mac=\"MAC_FMT\"\\n\",\n\t\t\tMAC_ARG(prm->psta->cmn.mac_addr));\n\n\tif (pact)\n\t\trm_dbg_activate_meas(padapter, pstr(s));\n}\n\nstatic void rm_dbg_del_meas(_adapter *padapter, char *s)\n{\n\tstruct rm_priv *prmpriv = &padapter->rmpriv;\n\tstruct rm_obj *prm = (struct rm_obj *)prmpriv->prm_sel;\n\n\n\tif (prm) {\n\t\tsprintf(pstr(s), \"\\ndelete rmid=%x\\n\",prm->rmid);\n\n\t\t/* free inActivate meas - enqueue yet  */\n\t\tprmpriv->prm_sel = NULL;\n\t\trtw_mfree(prmpriv->prm_sel, sizeof(struct rm_obj));\n\t} else\n\t\tsprintf(pstr(s), \"Err: no inActivate measurement\\n\");\n}\n\nstatic void rm_dbg_run_meas(_adapter *padapter, char *s)\n{\n\tstruct rm_obj *prm;\n\tchar *pevid, *prmid;\n\tu32 rmid, evid;\n\n\n\tprmid = strstr(s, \"rmid=\"); /* hex */\n\tpevid = strstr(s, \"evid=\"); /* dec */\n\n\tif (prmid && pevid) {\n\t\tprmid += 5; /* rmid= */\n\t\tsscanf(prmid, \"%x\", &rmid);\n\n\t\tpevid += 5; /* evid= */\n\t\tsscanf(pevid, \"%u\", &evid);\n\t} else {\n\t\tsprintf(pstr(s), \"\\nErr: incorrect attribute\\n\");\n\t\treturn;\n\t}\n\n\tprm = rm_get_rmobj(padapter, rmid);\n\n\tif (!prm) {\n\t\tsprintf(pstr(s), \"\\nErr: measurement not found\\n\");\n\t\treturn;\n\t}\n\n\tif (evid >= RM_EV_max) {\n\t\tsprintf(pstr(s), \"\\nErr: wrong event id\\n\");\n\t\treturn;\n\t}\n\n\trm_post_event(padapter, prm->rmid, evid);\n\tsprintf(pstr(s), \"\\npost %s to rmid=%x\\n\",rm_event_name(evid), rmid);\n}\n\nstatic void rm_dbg_show_meas(struct rm_obj *prm, char *s)\n{\n\tstruct sta_info *psta;\n\n\tpsta = prm->psta;\n\n\tif (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {\n\n\t\tsprintf(pstr(s), \"\\nrmid=%x, meas_type=%s\\n\",\n\t\t\tprm->rmid, rm_type_req_name(prm->q.m_type));\n\n\t} else  if (prm->q.action_code == RM_ACT_NB_REP_REQ) {\n\n\t\tsprintf(pstr(s), \"\\nrmid=%x, action=neighbor_req\\n\",\n\t\t\tprm->rmid);\n\t} else\n\t\tsprintf(pstr(s), \"\\nrmid=%x, action=unknown\\n\",\n\t\t\tprm->rmid);\n\n\tif (psta)\n\t\tsprintf(pstr(s), \"aid=%d, mac=\"MAC_FMT\"\\n\",\n\t\t\tpsta->cmn.aid, MAC_ARG(psta->cmn.mac_addr));\n\n\tsprintf(pstr(s), \"clock=%d, state=%s, rpt=%u/%u\\n\",\n\t\t(int)ATOMIC_READ(&prm->pclock->counter),\n\t\trm_state_name(prm->state), prm->p.rpt, prm->q.rpt);\n}\n\nstatic void rm_dbg_list_meas(_adapter *padapter, char *s)\n{\n\tint meas_amount;\n\t_irqL irqL;\n\tstruct rm_obj *prm;\n\tstruct sta_info *psta;\n\tstruct rm_priv *prmpriv = &padapter->rmpriv;\n\t_queue *queue = &prmpriv->rm_queue;\n\t_list *plist, *phead;\n\n\n\tsprintf(pstr(s), \"\\n\");\n\t_enter_critical(&queue->lock, &irqL);\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\tmeas_amount = 0;\n\n\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\tprm = LIST_CONTAINOR(plist, struct rm_obj, list);\n\t\tmeas_amount++;\n\t\tplist = get_next(plist);\n\t\tpsta = prm->psta;\n\t\tsprintf(pstr(s), \"=========================================\\n\");\n\n\t\trm_dbg_show_meas(prm, s);\n\t}\n\t_exit_critical(&queue->lock, &irqL);\n\n\tsprintf(pstr(s), \"=========================================\\n\");\n\n\tif (meas_amount==0) {\n\t\tsprintf(pstr(s), \"No Activate measurement\\n\");\n\t\tsprintf(pstr(s), \"=========================================\\n\");\n\t}\n\n\tif (prmpriv->prm_sel == NULL)\n\t\tsprintf(pstr(s), \"\\nNo inActivate measurement\\n\");\n\telse {\n\t\tsprintf(pstr(s), \"\\ninActivate measurement\\n\");\n\t\trm_dbg_show_meas((struct rm_obj *)prmpriv->prm_sel, s);\n\t}\n}\n#endif /* RM_SUPPORT_IWPRIV_DBG */\n\nvoid rm_dbg_cmd(_adapter *padapter, char *s)\n{\n\tunsigned val;\n\tchar *paid;\n\tstruct sta_info *psta=NULL;\n\n#if (RM_SUPPORT_IWPRIV_DBG)\n\tif (_rtw_memcmp(s, \"help\", 4)) {\n\t\trm_dbg_help(padapter, s);\n\n\t} else if (_rtw_memcmp(s, \"list_sta\", 8)) {\n\t\trm_dbg_list_sta(padapter, s);\n\n\t} else if (_rtw_memcmp(s, \"list_meas\", 9)) {\n\t\trm_dbg_list_meas(padapter, s);\n\n\t} else if (_rtw_memcmp(s, \"add_meas\", 8)) {\n\t\trm_dbg_add_meas(padapter, s);\n\n\t} else if (_rtw_memcmp(s, \"del_meas\", 8)) {\n\t\trm_dbg_del_meas(padapter, s);\n\n\t} else if (_rtw_memcmp(s, \"activate\", 8)) {\n\t\trm_dbg_activate_meas(padapter, s);\n\n\t} else if (_rtw_memcmp(s, \"run_meas\", 8)) {\n\t\trm_dbg_run_meas(padapter, s);\n\t} else if (_rtw_memcmp(s, \"nb\", 2)) {\n\n\t\tpaid = strstr(s, \"aid=\");\n\n\t\tif (paid) { /* find sta_info according to aid */\n\t\t\tpaid += 4; /* skip aid= */\n\t\t\tsscanf(paid, \"%u\", &val); /* aid=x */\n\t\t\tpsta = rm_get_sta(padapter, val, NULL);\n\n\t\t\tif (psta)\n\t\t\t\trm_add_nb_req(padapter, psta);\n\t\t}\n\t}\n#else\n\tsprintf(pstr(s), \"\\n\");\n\tsprintf(pstr(s), \"rrm debug command was disabled\\n\");\n#endif\n}\n#endif /* CONFIG_RTW_80211K */\n"
  },
  {
    "path": "core/rtw_rm_fsm.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include <drv_types.h>\n#include <hal_data.h>\n#include \"rtw_rm_fsm.h\"\n\n#ifdef CONFIG_RTW_80211K\n\nstruct fsm_state {\n\tu8 *name;\n\tint(*fsm_func)(struct rm_obj *prm, enum RM_EV_ID evid);\n};\n\nstatic void rm_state_initial(struct rm_obj *prm);\nstatic void rm_state_goto(struct rm_obj *prm, enum RM_STATE rm_state);\nstatic void rm_state_run(struct rm_obj *prm, enum RM_EV_ID evid);\nstatic struct rm_event *rm_dequeue_ev(_queue *queue);\nstatic struct rm_obj *rm_dequeue_rm(_queue *queue);\n\nvoid rm_timer_callback(void *data)\n{\n\tint i;\n\t_adapter *padapter = (_adapter *)data;\n\tstruct rm_priv *prmpriv = &padapter->rmpriv;\n\tstruct rm_clock *pclock;\n\n\n\t/* deal with clock */\n\tfor (i=0;i<RM_TIMER_NUM;i++) {\n\t\tpclock = &prmpriv->clock[i];\n\t\tif (pclock->prm == NULL\n\t\t\t||(ATOMIC_READ(&(pclock->counter)) == 0))\n\t\t\tcontinue;\n\n\t\tATOMIC_DEC(&(pclock->counter));\n\n\t\tif (ATOMIC_READ(&(pclock->counter)) == 0)\n\t\t\trm_post_event(pclock->prm->psta->padapter,\n\t\t\t\tpclock->prm->rmid, prmpriv->clock[i].evid);\n\t}\n\t_set_timer(&prmpriv->rm_timer, CLOCK_UNIT);\n}\n\nint rtw_init_rm(_adapter *padapter)\n{\n\tstruct rm_priv *prmpriv = &padapter->rmpriv;\n\n\n\tRTW_INFO(\"RM: %s\\n\",__func__);\n\t_rtw_init_queue(&(prmpriv->rm_queue));\n\t_rtw_init_queue(&(prmpriv->ev_queue));\n\n\t/* bit 0-7 */\n\tprmpriv->rm_en_cap_def[0] = 0\n\t\t/*| BIT(RM_LINK_MEAS_CAP_EN)*/\n\t\t| BIT(RM_NB_REP_CAP_EN)\n\t\t/*| BIT(RM_PARAL_MEAS_CAP_EN)*/\n\t\t| BIT(RM_REPEAT_MEAS_CAP_EN)\n\t\t| BIT(RM_BCN_PASSIVE_MEAS_CAP_EN)\n\t\t| BIT(RM_BCN_ACTIVE_MEAS_CAP_EN)\n\t\t| BIT(RM_BCN_TABLE_MEAS_CAP_EN)\n\t\t/*| BIT(RM_BCN_MEAS_REP_COND_CAP_EN)*/;\n\n\t/* bit  8-15 */\n\tprmpriv->rm_en_cap_def[1] = 0\n\t\t/*| BIT(RM_FRAME_MEAS_CAP_EN - 8)*/\n#ifdef CONFIG_RTW_ACS\n\t\t| BIT(RM_CH_LOAD_CAP_EN - 8)\n\t\t| BIT(RM_NOISE_HISTO_CAP_EN - 8)\n#endif\n\t\t/*| BIT(RM_STATIS_MEAS_CAP_EN - 8)*/\n\t\t/*| BIT(RM_LCI_MEAS_CAP_EN - 8)*/\n\t\t/*| BIT(RM_LCI_AMIMUTH_CAP_EN - 8)*/\n\t\t/*| BIT(RM_TRANS_STREAM_CAT_MEAS_CAP_EN - 8)*/\n\t\t/*| BIT(RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN - 8)*/;\n\n\t/* bit 16-23 */\n\tprmpriv->rm_en_cap_def[2] = 0\n\t\t/*| BIT(RM_AP_CH_REP_CAP_EN - 16)*/\n\t\t/*| BIT(RM_RM_MIB_CAP_EN - 16)*/\n\t\t/*| BIT(RM_OP_CH_MAX_MEAS_DUR0 - 16)*/\n\t\t/*| BIT(RM_OP_CH_MAX_MEAS_DUR1 - 16)*/\n\t\t/*| BIT(RM_OP_CH_MAX_MEAS_DUR2 - 16)*/\n\t\t/*| BIT(RM_NONOP_CH_MAX_MEAS_DUR0 - 16)*/\n\t\t/*| BIT(RM_NONOP_CH_MAX_MEAS_DUR1 - 16)*/\n\t\t/*| BIT(RM_NONOP_CH_MAX_MEAS_DUR2 - 16)*/;\n\n\t/* bit 24-31 */\n\tprmpriv->rm_en_cap_def[3] = 0\n\t\t/*| BIT(RM_MEAS_PILOT_CAP0 - 24)*/\n\t\t/*| BIT(RM_MEAS_PILOT_CAP1 - 24)*/\n\t\t/*| BIT(RM_MEAS_PILOT_CAP2 - 24)*/\n\t\t/*| BIT(RM_MEAS_PILOT_TRANS_INFO_CAP_EN - 24)*/\n\t\t/*| BIT(RM_NB_REP_TSF_OFFSET_CAP_EN - 24)*/\n\t\t| BIT(RM_RCPI_MEAS_CAP_EN - 24)\n\t\t| BIT(RM_RSNI_MEAS_CAP_EN - 24)\n\t\t/*| BIT(RM_BSS_AVG_ACCESS_DELAY_CAP_EN - 24)*/;\n\n\t/* bit 32-39 */\n\tprmpriv->rm_en_cap_def[4] = 0\n\t\t/*| BIT(RM_BSS_AVG_ACCESS_DELAY_CAP_EN - 32)*/\n\t\t/*| BIT(RM_AVALB_ADMIS_CAPACITY_CAP_EN - 32)*/\n\t\t/*| BIT(RM_ANT_CAP_EN - 32)*/;\n\n\tprmpriv->enable = _TRUE;\n\n\t/* clock timer */\n\trtw_init_timer(&prmpriv->rm_timer,\n\t\tpadapter, rm_timer_callback, padapter);\n\t_set_timer(&prmpriv->rm_timer, CLOCK_UNIT);\n\n\treturn _SUCCESS;\n}\n\nint rtw_deinit_rm(_adapter *padapter)\n{\n\tstruct rm_priv *prmpriv = &padapter->rmpriv;\n\tstruct rm_obj *prm;\n\tstruct rm_event *pev;\n\n\n\tRTW_INFO(\"RM: %s\\n\",__func__);\n\tprmpriv->enable = _FALSE;\n\t_cancel_timer_ex(&prmpriv->rm_timer);\n\n\t/* free all events and measurements */\n\twhile((pev = rm_dequeue_ev(&prmpriv->ev_queue)) != NULL)\n\t\trtw_mfree((void *)pev, sizeof(struct rm_event));\n\n\twhile((prm = rm_dequeue_rm(&prmpriv->rm_queue)) != NULL)\n\t\trm_state_run(prm, RM_EV_cancel);\n\n\t_rtw_deinit_queue(&(prmpriv->rm_queue));\n\t_rtw_deinit_queue(&(prmpriv->ev_queue));\n\n\treturn _SUCCESS;\n}\n\nint rtw_free_rm_priv(_adapter *padapter)\n{\n\treturn rtw_deinit_rm(padapter);\n}\n\nstatic int rm_enqueue_ev(_queue *queue, struct rm_event *obj, bool to_head)\n{\n\t_irqL irqL;\n\n\n\tif (obj == NULL)\n\t\treturn _FAIL;\n\n\t_enter_critical(&queue->lock, &irqL);\n\n\tif (to_head)\n\t\trtw_list_insert_head(&obj->list, &queue->queue);\n\telse\n\t\trtw_list_insert_tail(&obj->list, &queue->queue);\n\n\t_exit_critical(&queue->lock, &irqL);\n\n\treturn _SUCCESS;\n}\n\nstatic void rm_set_clock(struct rm_obj *prm, u32 ms, enum RM_EV_ID evid)\n{\n\tATOMIC_SET(&(prm->pclock->counter), (ms/CLOCK_UNIT));\n\tprm->pclock->evid = evid;\n}\n\nstatic struct rm_clock *rm_alloc_clock(_adapter *padapter, struct rm_obj *prm)\n{\n\tint i;\n\tstruct rm_priv *prmpriv = &padapter->rmpriv;\n\tstruct rm_clock *pclock = NULL;\n\n\n\tfor (i=0;i<RM_TIMER_NUM;i++) {\n\t\tpclock = &prmpriv->clock[i];\n\n\t\tif (pclock->prm == NULL) {\n\t\t\tpclock->prm = prm;\n\t\t\tATOMIC_SET(&(pclock->counter), 0);\n\t\t\tpclock->evid = RM_EV_max;\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn pclock;\n}\n\nstatic void rm_cancel_clock(struct rm_obj *prm)\n{\n\tATOMIC_SET(&(prm->pclock->counter), 0);\n\tprm->pclock->evid = RM_EV_max;\n}\n\nstatic void rm_free_clock(struct rm_clock *pclock)\n{\n\tpclock->prm = NULL;\n\tATOMIC_SET(&(pclock->counter), 0);\n\tpclock->evid = RM_EV_max;\n}\n\nstatic int is_list_linked(const struct list_head *head)\n{\n\treturn head->prev != NULL;\n}\n\nvoid rm_free_rmobj(struct rm_obj *prm)\n{\n\tif (is_list_linked(&prm->list))\n\t\trtw_list_delete(&prm->list);\n\n\tif (prm->q.pssid)\n\t\trtw_mfree(prm->q.pssid, strlen(prm->q.pssid)+1);\n\n\tif (prm->q.opt.bcn.req_start)\n\t\trtw_mfree(prm->q.opt.bcn.req_start,\n\t\t\tprm->q.opt.bcn.req_len);\n\n\tif (prm->pclock)\n\t\trm_free_clock(prm->pclock);\n\n\trtw_mfree((void *)prm, sizeof(struct rm_obj));\n}\n\nstruct rm_obj *rm_alloc_rmobj(_adapter *padapter)\n{\n\tstruct rm_obj *prm;\n\n\n\tprm = (struct rm_obj *)rtw_malloc(sizeof(struct rm_obj));\n\tif (prm == NULL)\n\t\treturn NULL;\n\n\t_rtw_memset(prm, 0, sizeof(struct rm_obj));\n\n\t/* alloc timer */\n\tif ((prm->pclock = rm_alloc_clock(padapter, prm)) == NULL) {\n\t\trm_free_rmobj(prm);\n\t\treturn NULL;\n\t}\n\treturn prm;\n}\n\nint rm_enqueue_rmobj(_adapter *padapter, struct rm_obj *prm, bool to_head)\n{\n\t_irqL irqL;\n\tstruct rm_priv *prmpriv = &padapter->rmpriv;\n\t_queue *queue = &prmpriv->rm_queue;\n\n\n\tif (prm == NULL)\n\t\treturn _FAIL;\n\n\t_enter_critical(&queue->lock, &irqL);\n\tif (to_head)\n\t\trtw_list_insert_head(&prm->list, &queue->queue);\n\telse\n\t\trtw_list_insert_tail(&prm->list, &queue->queue);\n\t_exit_critical(&queue->lock, &irqL);\n\n\trm_state_initial(prm);\n\n\treturn _SUCCESS;\n}\n\nstatic struct rm_obj *rm_dequeue_rm(_queue *queue)\n{\n\t_irqL irqL;\n\tstruct rm_obj *prm;\n\n\n\t_enter_critical(&queue->lock, &irqL);\n\tif (rtw_is_list_empty(&(queue->queue)))\n\t\tprm = NULL;\n\telse {\n\t\tprm = LIST_CONTAINOR(get_next(&(queue->queue)),\n\t\t\tstruct rm_obj, list);\n\t\t/* rtw_list_delete(&prm->list); */\n\t}\n\t_exit_critical(&queue->lock, &irqL);\n\n\treturn prm;\n}\n\nstatic struct rm_event *rm_dequeue_ev(_queue *queue)\n{\n\t_irqL irqL;\n\tstruct rm_event *ev;\n\n\n\t_enter_critical(&queue->lock, &irqL);\n\tif (rtw_is_list_empty(&(queue->queue)))\n\t\tev = NULL;\n\telse {\n\t\tev = LIST_CONTAINOR(get_next(&(queue->queue)),\n\t\t\tstruct rm_event, list);\n\t\trtw_list_delete(&ev->list);\n\t}\n\t_exit_critical(&queue->lock, &irqL);\n\n\treturn ev;\n}\n\nstatic struct rm_obj *_rm_get_rmobj(_queue *queue, u32 rmid)\n{\n\t_irqL irqL;\n\t_list *phead, *plist;\n\tstruct rm_obj *prm = NULL;\n\n\n\tif (rmid == 0)\n\t\treturn NULL;\n\n\t_enter_critical(&queue->lock, &irqL);\n\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\n\t\tprm = LIST_CONTAINOR(plist, struct rm_obj, list);\n\t\tif (rmid == (prm->rmid)) {\n\t\t\t_exit_critical(&queue->lock, &irqL);\n\t\t\treturn prm;\n\t\t}\n\t\tplist = get_next(plist);\n\t}\n\t_exit_critical(&queue->lock, &irqL);\n\n\treturn NULL;\n}\n\nstruct sta_info *rm_get_psta(_adapter *padapter, u32 rmid)\n{\n\tstruct rm_priv *prmpriv = &padapter->rmpriv;\n\tstruct rm_obj *prm;\n\n\n\tprm = _rm_get_rmobj(&prmpriv->rm_queue, rmid);\n\n\tif (prm)\n\t\treturn prm->psta;\n\n\treturn NULL;\n}\n\nstruct rm_obj *rm_get_rmobj(_adapter *padapter, u32 rmid)\n{\n\tstruct rm_priv *prmpriv = &padapter->rmpriv;\n\n\treturn _rm_get_rmobj(&prmpriv->rm_queue, rmid);\n}\n\nu8 rtw_rm_post_envent_cmd(_adapter *padapter, u32 rmid, u8 evid)\n{\n\tstruct cmd_obj *pcmd;\n\tstruct rm_event *pev;\n\tstruct cmd_priv *pcmdpriv = &padapter->cmdpriv;\n\tu8 res = _SUCCESS;\n\n\n\tpcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (pcmd == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tpev = (struct rm_event*)rtw_zmalloc(sizeof(struct rm_event));\n\n\tif (pev == NULL) {\n\t\trtw_mfree((u8 *) pcmd, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tpev->rmid = rmid;\n\tpev->evid = evid;\n\n\tinit_h2fwcmd_w_parm_no_rsp(pcmd, pev, GEN_CMD_CODE(_RM_POST_EVENT));\n\tres = rtw_enqueue_cmd(pcmdpriv, pcmd);\nexit:\n\treturn res;\n}\n\nint rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid)\n{\n\tif (padapter->rmpriv.enable == _FALSE)\n\t\treturn _FALSE;\n\n\tRTW_INFO(\"RM: post asyn %s to rmid=%x\\n\", rm_event_name(evid), rmid);\n\trtw_rm_post_envent_cmd(padapter, rmid, evid);\n\treturn _SUCCESS;\n}\n\nint _rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid)\n{\n\tstruct rm_priv *prmpriv = &padapter->rmpriv;\n\tstruct rm_event *pev;\n\n\tif (evid >= RM_EV_max || rmid == 0)\n\t\treturn _FALSE;\n\n\tpev = (struct rm_event *)rtw_malloc(sizeof(struct rm_event));\n\tif (pev == NULL)\n\t\treturn _FALSE;\n\n\tpev->rmid = rmid;\n\tpev->evid = evid;\n\n\tRTW_INFO(\"RM: post sync %s to rmid=%x\\n\", rm_event_name(evid), rmid);\n\trm_enqueue_ev(&prmpriv->ev_queue, pev, FALSE);\n\n\treturn _SUCCESS;\n}\n\nstatic void rm_bcast_aid_handler(_adapter *padapter, struct rm_event *pev)\n{\n\t_irqL irqL;\n\t_list *phead, *plist;\n\t_queue *queue = &padapter->rmpriv.rm_queue;\n\tstruct rm_obj *prm;\n\n\n\t_enter_critical(&queue->lock, &irqL);\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\n\t\tprm = LIST_CONTAINOR(plist, struct rm_obj, list);\n\t\tplist = get_next(plist);\n\t\tif (RM_GET_AID(pev->rmid) == RM_GET_AID(prm->rmid)) {\n\t\t\t_exit_critical(&queue->lock, &irqL);\n\t\t\trm_state_run(prm, pev->evid);\n\t\t\t_enter_critical(&queue->lock, &irqL);\n\t\t}\n\t}\n\t_exit_critical(&queue->lock, &irqL);\n\treturn;\n}\n\n/* main handler of RM (Resource Management) */\nvoid rm_handler(_adapter *padapter, struct rm_event *pe)\n{\n\tint i;\n\tstruct rm_priv *prmpriv = &padapter->rmpriv;\n\tstruct rm_obj *prm;\n\tstruct rm_event *pev;\n\n\n\t/* dequeue event */\n\twhile((pev = rm_dequeue_ev(&prmpriv->ev_queue)) != NULL)\n\t{\n\t\tif (RM_IS_ID_FOR_ALL(pev->rmid)) {\n\t\t\t/* apply to all aid mateched measurement */\n\t\t\trm_bcast_aid_handler(padapter, pev);\n\t\t\trtw_mfree((void *)pev, sizeof(struct rm_event));\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* retrieve rmobj */\n\t\tprm = _rm_get_rmobj(&prmpriv->rm_queue, pev->rmid);\n\t\tif (prm == NULL) {\n\t\t\tRTW_ERR(\"RM: rmid=%x event=%s doesn't find rm obj\\n\",\n\t\t\t\tpev->rmid, rm_event_name(pev->evid));\n\t\t\trtw_mfree((void *)pev, sizeof(struct rm_event));\n\t\t\treturn;\n\t\t}\n\t\t/* run state machine */\n\t\trm_state_run(prm, pev->evid);\n\t\trtw_mfree((void *)pev, sizeof(struct rm_event));\n\t}\n}\n\nstatic int rm_issue_meas_req(struct rm_obj *prm)\n{\n\tswitch (prm->q.action_code) {\n\tcase RM_ACT_RADIO_MEAS_REQ:\n\t\tswitch (prm->q.m_type) {\n\t\tcase bcn_req:\n\t\tcase ch_load_req:\n\t\tcase noise_histo_req:\n\t\t\tissue_radio_meas_req(prm);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t} /* meas_type */\n\t\tbreak;\n\tcase RM_ACT_NB_REP_REQ:\n\t\t/* issue neighbor request */\n\t\tissue_nb_req(prm);\n\t\tbreak;\n\tcase RM_ACT_LINK_MEAS_REQ:\n\tdefault:\n\t\treturn _FALSE;\n\t} /* action_code */\n\n\treturn _SUCCESS;\n}\n\n/*\n* RM state machine\n*/\n\nstatic int rm_state_idle(struct rm_obj *prm, enum RM_EV_ID evid)\n{\n\t_adapter *padapter = prm->psta->padapter;\n\tu8 val8;\n\tu32 val32;\n\n\n\tprm->p.category = RTW_WLAN_CATEGORY_RADIO_MEAS;\n\n\tswitch (evid) {\n\tcase RM_EV_state_in:\n\t\tswitch (prm->q.action_code) {\n\t\tcase RM_ACT_RADIO_MEAS_REQ:\n\t\t\t/* copy attrib from meas_req to meas_rep */\n\t\t\tprm->p.action_code = RM_ACT_RADIO_MEAS_REP;\n\t\t\tprm->p.diag_token = prm->q.diag_token;\n\t\t\tprm->p.e_id = _MEAS_RSP_IE_;\n\t\t\tprm->p.m_token = prm->q.m_token;\n\t\t\tprm->p.m_type = prm->q.m_type;\n\t\t\tprm->p.rpt = prm->q.rpt;\n\t\t\tprm->p.ch_num = prm->q.ch_num;\n\t\t\tprm->p.op_class = prm->q.op_class;\n\n\t\t\tif (prm->q.m_type == ch_load_req\n\t\t\t\t|| prm->q.m_type == noise_histo_req) {\n\t\t\t\t/*\n\t\t\t\t * phydm measure current ch periodically\n\t\t\t\t * scan current ch is not necessary\n\t\t\t\t */\n\t\t\t\tval8 = padapter->mlmeextpriv.cur_channel;\n\t\t\t\tif (prm->q.ch_num == val8)\n\t\t\t\t\tprm->poll_mode = 1;\n\t\t\t}\n\t\t\tRTW_INFO(\"RM: rmid=%x %s switch in repeat=%u\\n\",\n\t\t\t\tprm->rmid, rm_type_req_name(prm->q.m_type),\n\t\t\t\tprm->q.rpt);\n\t\t\tbreak;\n\t\tcase RM_ACT_NB_REP_REQ:\n\t\t\tprm->p.action_code = RM_ACT_NB_REP_RESP;\n\t\t\tRTW_INFO(\"RM: rmid=%x Neighbor request switch in\\n\",\n\t\t\t\tprm->rmid);\n\t\t\tbreak;\n\t\tcase RM_ACT_LINK_MEAS_REQ:\n\t\t\tprm->p.action_code = RM_ACT_LINK_MEAS_REP;\n\t\t\trm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);\n\t\t\tRTW_INFO(\"RM: rmid=%x Link meas switch in\\n\",\n\t\t\t\tprm->rmid);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprm->p.action_code = prm->q.action_code;\n\t\t\trm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);\n\t\t\tRTW_INFO(\"RM: rmid=%x recv unknown action %d\\n\",\n\t\t\t\tprm->rmid,prm->p.action_code);\n\t\t\tbreak;\n\t\t} /* switch() */\n\n\t\tif (prm->rmid & RM_MASTER) {\n\t\t\tif (rm_issue_meas_req(prm) == _SUCCESS)\n\t\t\t\trm_state_goto(prm, RM_ST_WAIT_MEAS);\n\t\t\telse\n\t\t\t\trm_state_goto(prm, RM_ST_END);\n\t\t\treturn _SUCCESS;\n\t\t} else {\n\t\t\trm_state_goto(prm, RM_ST_DO_MEAS);\n\t\t\treturn _SUCCESS;\n\t\t}\n\n\t\tif (prm->p.m_mode) {\n\t\t\tissue_null_reply(prm);\n\t\t\trm_state_goto(prm, RM_ST_END);\n\t\t\treturn _SUCCESS;\n\t\t}\n\t\tif (prm->q.rand_intvl) {\n\t\t\t/* get low tsf to generate random interval */\n\t\t\tval32 = rtw_read32(padapter, REG_TSFTR);\n\t\t\tval32 = val32 % prm->q.rand_intvl;\n\t\t\tRTW_INFO(\"RM: rmid=%x rand_intval=%d, rand=%d\\n\",\n\t\t\t\tprm->rmid, (int)prm->q.rand_intvl,val32);\n\t\t\trm_set_clock(prm, prm->q.rand_intvl,\n\t\t\t\tRM_EV_delay_timer_expire);\n\t\t\treturn _SUCCESS;\n\t\t}\n\t\tbreak;\n\tcase RM_EV_delay_timer_expire:\n\t\trm_state_goto(prm, RM_ST_DO_MEAS);\n\t\tbreak;\n\tcase RM_EV_cancel:\n\t\trm_state_goto(prm, RM_ST_END);\n\t\tbreak;\n\tcase RM_EV_state_out:\n\t\trm_cancel_clock(prm);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn _SUCCESS;\n}\n\n/* we do the measuring */\nstatic int rm_state_do_meas(struct rm_obj *prm, enum RM_EV_ID evid)\n{\n\t_adapter *padapter = prm->psta->padapter;\n\tu8 val8;\n\tu64 val64;\n\n\n\tswitch (evid) {\n\tcase RM_EV_state_in:\n\t\tif (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {\n\t\t\tswitch (prm->q.m_type) {\n\t\t\tcase bcn_req:\n\t\t\t\tif (prm->q.m_mode == bcn_req_bcn_table) {\n\t\t\t\t\tRTW_INFO(\"RM: rmid=%x Beacon table\\n\",\n\t\t\t\t\t\tprm->rmid);\n\t\t\t\t\t_rm_post_event(padapter, prm->rmid,\n\t\t\t\t\t\tRM_EV_survey_done);\n\t\t\t\t\treturn _SUCCESS;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase ch_load_req:\n\t\t\tcase noise_histo_req:\n\t\t\t\tif (prm->poll_mode)\n\t\t\t\t\t_rm_post_event(padapter, prm->rmid,\n\t\t\t\t\t\tRM_EV_survey_done);\n\t\t\t\treturn _SUCCESS;\n\t\t\tdefault:\n\t\t\t\trm_state_goto(prm, RM_ST_END);\n\t\t\t\treturn _SUCCESS;\n\t\t\t}\n\n\t\t\tif (!ready_for_scan(prm)) {\n\t\t\t\tprm->wait_busy = RM_BUSY_TRAFFIC_TIMES;\n\t\t\t\tRTW_INFO(\"RM: wait busy traffic - %d\\n\",\n\t\t\t\t\tprm->wait_busy);\n\t\t\t\trm_set_clock(prm, RM_WAIT_BUSY_TIMEOUT,\n\t\t\t\t\tRM_EV_busy_timer_expire);\n\t\t\t\treturn _SUCCESS;\n\t\t\t}\n\t\t}\n\t\t_rm_post_event(padapter, prm->rmid, RM_EV_start_meas);\n\t\tbreak;\n\tcase RM_EV_start_meas:\n\t\tif (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {\n\t\t\t/* resotre measurement start time */\n\t\t\tprm->meas_start_time = rtw_hal_get_tsftr_by_port(padapter\n\t\t\t\t\t\t\t\t\t, rtw_hal_get_port(padapter));\n\n\t\t\tswitch (prm->q.m_type) {\n\t\t\tcase bcn_req:\n\t\t\t\tval8 = 1; /* Enable free run counter */\n\t\t\t\trtw_hal_set_hwreg(padapter,\n\t\t\t\t\tHW_VAR_FREECNT, &val8);\n\t\t\t\trm_sitesurvey(prm);\n\t\t\t\tbreak;\n\t\t\tcase ch_load_req:\n\t\t\tcase noise_histo_req:\n\t\t\t\trm_sitesurvey(prm);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\trm_state_goto(prm, RM_ST_END);\n\t\t\t\treturn _SUCCESS;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* handle measurement timeout */\n\t\trm_set_clock(prm, RM_MEAS_TIMEOUT, RM_EV_meas_timer_expire);\n\t\tbreak;\n\tcase RM_EV_survey_done:\n\t\tif (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {\n\t\t\tswitch (prm->q.m_type) {\n\t\t\tcase bcn_req:\n\t\t\t\trm_cancel_clock(prm);\n\t\t\t\trm_state_goto(prm, RM_ST_SEND_REPORT);\n\t\t\t\treturn _SUCCESS;\n\t\t\tcase ch_load_req:\n\t\t\tcase noise_histo_req:\n\t\t\t\tretrieve_radio_meas_result(prm);\n\n\t\t\t\tif (rm_radio_meas_report_cond(prm) == _SUCCESS)\n\t\t\t\t\trm_state_goto(prm, RM_ST_SEND_REPORT);\n\t\t\t\telse\n\t\t\t\t\trm_set_clock(prm, RM_COND_INTVL,\n\t\t\t\t\t\tRM_EV_retry_timer_expire);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\trm_state_goto(prm, RM_ST_END);\n\t\t\t\treturn _SUCCESS;\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tcase RM_EV_meas_timer_expire:\n\t\tRTW_INFO(\"RM: rmid=%x measurement timeount\\n\",prm->rmid);\n\t\trm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);\n\t\tissue_null_reply(prm);\n\t\trm_state_goto(prm, RM_ST_END);\n\t\tbreak;\n\tcase RM_EV_busy_timer_expire:\n\t\tif (!ready_for_scan(prm) && prm->wait_busy--) {\n\t\t\tRTW_INFO(\"RM: wait busy - %d\\n\",prm->wait_busy);\n\t\t\trm_set_clock(prm, RM_WAIT_BUSY_TIMEOUT,\n\t\t\t\tRM_EV_busy_timer_expire);\n\t\t\tbreak;\n\t\t}\n\t\telse if (prm->wait_busy <= 0) {\n\t\t\tRTW_INFO(\"RM: wait busy timeout\\n\");\n\t\t\trm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);\n\t\t\tissue_null_reply(prm);\n\t\t\trm_state_goto(prm, RM_ST_END);\n\t\t\treturn _SUCCESS;\n\t\t}\n\t\t_rm_post_event(padapter, prm->rmid, RM_EV_start_meas);\n\t\tbreak;\n\tcase RM_EV_request_timer_expire:\n\t\trm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);\n\t\tissue_null_reply(prm);\n\t\trm_state_goto(prm, RM_ST_END);\n\t\tbreak;\n\tcase RM_EV_retry_timer_expire:\n\t\t/* expired due to meas condition mismatch, meas again */\n\t\t_rm_post_event(padapter, prm->rmid, RM_EV_start_meas);\n\t\tbreak;\n\tcase RM_EV_cancel:\n\t\trm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);\n\t\tissue_null_reply(prm);\n\t\trm_state_goto(prm, RM_ST_END);\n\t\tbreak;\n\tcase RM_EV_state_out:\n\t\trm_cancel_clock(prm);\n\t\t/* resotre measurement end time */\n\t\tprm->meas_end_time = rtw_hal_get_tsftr_by_port(padapter\n\t\t\t\t\t\t\t\t, rtw_hal_get_port(padapter));\n\n\t\tval8 = 0; /* Disable free run counter */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_FREECNT, &val8);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn _SUCCESS;\n}\n\nstatic int rm_state_wait_meas(struct rm_obj *prm, enum RM_EV_ID evid)\n{\n\tu8 val8;\n\tu64 val64;\n\n\n\tswitch (evid) {\n\tcase RM_EV_state_in:\n\t\t/* we create meas_req, waiting for peer report */\n\t\trm_set_clock(prm, RM_REQ_TIMEOUT,\n\t\t\tRM_EV_request_timer_expire);\n\t\tbreak;\n\tcase RM_EV_recv_rep:\n\t\trm_state_goto(prm, RM_ST_RECV_REPORT);\n\t\tbreak;\n\tcase RM_EV_request_timer_expire:\n\tcase RM_EV_cancel:\n\t\trm_state_goto(prm, RM_ST_END);\n\t\tbreak;\n\tcase RM_EV_state_out:\n\t\trm_cancel_clock(prm);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn _SUCCESS;\n}\n\nstatic int rm_state_send_report(struct rm_obj *prm, enum RM_EV_ID evid)\n{\n\tu8 val8;\n\n\n\tswitch (evid) {\n\tcase RM_EV_state_in:\n\t\t/* we have to issue report */\n\t\tswitch (prm->q.m_type) {\n\t\tcase bcn_req:\n\t\t\tissue_beacon_rep(prm);\n\t\t\tbreak;\n\t\tcase ch_load_req:\n\t\tcase noise_histo_req:\n\t\t\tissue_radio_meas_rep(prm);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\trm_state_goto(prm, RM_ST_END);\n\t\t\treturn _SUCCESS;\n\t\t}\n\n\t\t/* check repeat */\n\t\tif (prm->p.rpt) {\n\t\t\tRTW_INFO(\"RM: rmid=%x repeat=%u/%u\\n\",\n\t\t\t\tprm->rmid, prm->p.rpt,\n\t\t\t\tprm->q.rpt);\n\t\t\tprm->p.rpt--;\n\t\t\t/*\n\t\t\t* we recv meas_req,\n\t\t\t* delay for a wihile and than meas again\n\t\t\t*/\n\t\t\tif (prm->poll_mode)\n\t\t\t\trm_set_clock(prm, RM_REPT_POLL_INTVL,\n\t\t\t\t\tRM_EV_repeat_delay_expire);\n\t\t\telse\n\t\t\t\trm_set_clock(prm, RM_REPT_SCAN_INTVL,\n\t\t\t\t\tRM_EV_repeat_delay_expire);\n\t\t\treturn _SUCCESS;\n\t\t}\n\t\t/* we are done */\n\t\trm_state_goto(prm, RM_ST_END);\n\t\tbreak;\n\tcase RM_EV_repeat_delay_expire:\n\t\trm_state_goto(prm, RM_ST_DO_MEAS);\n\t\tbreak;\n\tcase RM_EV_cancel:\n\t\trm_state_goto(prm, RM_ST_END);\n\t\tbreak;\n\tcase RM_EV_state_out:\n\t\trm_cancel_clock(prm);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn _SUCCESS;\n}\n\nstatic int rm_state_recv_report(struct rm_obj *prm, enum RM_EV_ID evid)\n{\n\tu8 val8;\n\n\n\tswitch (evid) {\n\tcase RM_EV_state_in:\n\t\t/* we issue meas_req, got peer's meas report */\n\t\tswitch (prm->p.action_code) {\n\t\tcase RM_ACT_RADIO_MEAS_REP:\n\t\t\t/* check refuse, incapable and repeat */\n\t\t\tval8 = prm->p.m_mode;\n\t\t\tif (val8) {\n\t\t\t\tRTW_INFO(\"RM: rmid=%x peer reject (%s repeat=%d)\\n\",\n\t\t\t\t\tprm->rmid,\n\t\t\t\t\tval8|MEAS_REP_MOD_INCAP?\"INCAP\":\n\t\t\t\t\tval8|MEAS_REP_MOD_REFUSE?\"REFUSE\":\n\t\t\t\t\tval8|MEAS_REP_MOD_LATE?\"LATE\":\"\",\n\t\t\t\t\tprm->p.rpt);\n\t\t\t\trm_state_goto(prm, RM_ST_END);\n\t\t\t\treturn _SUCCESS;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase RM_ACT_NB_REP_RESP:\n\t\t\t/* report to upper layer if needing */\n\t\t\trm_state_goto(prm, RM_ST_END);\n\t\t\treturn _SUCCESS;\n\t\tdefault:\n\t\t\trm_state_goto(prm, RM_ST_END);\n\t\t\treturn _SUCCESS;\n\t\t}\n\t\t/* check repeat */\n\t\tif (prm->p.rpt) {\n\t\t\tRTW_INFO(\"RM: rmid=%x repeat=%u/%u\\n\",\n\t\t\t\tprm->rmid, prm->p.rpt,\n\t\t\t\tprm->q.rpt);\n\t\t\tprm->p.rpt--;\n\t\t\t/* waitting more report */\n\t\t\trm_state_goto(prm, RM_ST_WAIT_MEAS);\n\t\t\tbreak;\n\t\t}\n\t\t/* we are done */\n\t\trm_state_goto(prm, RM_ST_END);\n\t\tbreak;\n\tcase RM_EV_cancel:\n\t\trm_state_goto(prm, RM_ST_END);\n\t\tbreak;\n\tcase RM_EV_state_out:\n\t\trm_cancel_clock(prm);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn _SUCCESS;\n}\n\nstatic int rm_state_end(struct rm_obj *prm, enum RM_EV_ID evid)\n{\n\tswitch (evid) {\n\tcase RM_EV_state_in:\n\t\t_rm_post_event(prm->psta->padapter, prm->rmid, RM_EV_state_out);\n\t\tbreak;\n\n\tcase RM_EV_cancel:\n\tcase RM_EV_state_out:\n\tdefault:\n\t\trm_free_rmobj(prm);\n\t\tbreak;\n\t}\n\treturn _SUCCESS;\n}\n\nstruct fsm_state rm_fsm[] = {\n\t{\"RM_ST_IDLE\",\t\trm_state_idle},\n\t{\"RM_ST_DO_MEAS\",\trm_state_do_meas},\n\t{\"RM_ST_WAIT_MEAS\", \trm_state_wait_meas},\n\t{\"RM_ST_SEND_REPORT\", \trm_state_send_report},\n\t{\"RM_ST_RECV_REPORT\", \trm_state_recv_report},\n\t{\"RM_ST_END\", \t\trm_state_end}\n};\n\nchar *rm_state_name(enum RM_STATE state)\n{\n\treturn rm_fsm[state].name;\n}\n\nchar *rm_event_name(enum RM_EV_ID evid)\n{\n\tswitch(evid) {\n\tcase RM_EV_state_in:\n\t\treturn \"RM_EV_state_in\";\n\tcase RM_EV_busy_timer_expire:\n\t\treturn \"RM_EV_busy_timer_expire\";\n\tcase RM_EV_delay_timer_expire:\n\t\treturn \"RM_EV_delay_timer_expire\";\n\tcase RM_EV_meas_timer_expire:\n\t\treturn \"RM_EV_meas_timer_expire\";\n\tcase RM_EV_repeat_delay_expire:\n\t\treturn \"RM_EV_repeat_delay_expire\";\n\tcase RM_EV_retry_timer_expire:\n\t\treturn \"RM_EV_retry_timer_expire\";\n\tcase RM_EV_request_timer_expire:\n\t\treturn \"RM_EV_request_timer_expire\";\n\tcase RM_EV_wait_report:\n\t\treturn \"RM_EV_wait_report\";\n\tcase RM_EV_start_meas:\n\t\treturn \"RM_EV_start_meas\";\n\tcase RM_EV_survey_done:\n\t\treturn \"RM_EV_survey_done\";\n\tcase RM_EV_recv_rep:\n\t\treturn \"RM_EV_recv_report\";\n\tcase RM_EV_cancel:\n\t\treturn \"RM_EV_cancel\";\n\tcase RM_EV_state_out:\n\t\treturn \"RM_EV_state_out\";\n\tcase RM_EV_max:\n\t\treturn \"RM_EV_max\";\n\tdefault:\n\t\treturn \"RM_EV_unknown\";\n\t}\n\treturn \"UNKNOWN\";\n}\n\nstatic void rm_state_initial(struct rm_obj *prm)\n{\n\tprm->state = RM_ST_IDLE;\n\n\tRTW_INFO(\"\\n\");\n\tRTW_INFO(\"RM: rmid=%x %-18s -> %s\\n\",prm->rmid,\n\t\t\"new measurement\", rm_fsm[prm->state].name);\n\n\trm_post_event(prm->psta->padapter, prm->rmid, RM_EV_state_in);\n}\n\nstatic void rm_state_run(struct rm_obj *prm, enum RM_EV_ID evid)\n{\n\tRTW_INFO(\"RM: rmid=%x %-18s    %s\\n\",prm->rmid,\n\t\trm_fsm[prm->state].name,rm_event_name(evid));\n\n\trm_fsm[prm->state].fsm_func(prm, evid);\n}\n\nstatic void rm_state_goto(struct rm_obj *prm, enum RM_STATE rm_state)\n{\n\tif (prm->state == rm_state)\n\t\treturn;\n\n\trm_state_run(prm, RM_EV_state_out);\n\n\tRTW_INFO(\"\\n\");\n\tRTW_INFO(\"RM: rmid=%x %-18s -> %s\\n\",prm->rmid,\n\t\trm_fsm[prm->state].name, rm_fsm[rm_state].name);\n\n\tprm->state = rm_state;\n\trm_state_run(prm, RM_EV_state_in);\n}\n#endif /* CONFIG_RTW_80211K */\n"
  },
  {
    "path": "core/rtw_rson.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along with\n * this program; if not, write to the Free Software Foundation, Inc.,\n * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\n *\n *\n ******************************************************************************/\n#define _RTW_RSON_C_\n\n#include <drv_types.h>\n\n#ifdef CONFIG_RTW_REPEATER_SON\n\n/********\tCustommize Part\t***********************/\n\nunsigned char\tRTW_RSON_OUI[] = {0xFA, 0xFA, 0xFA};\n#define RSON_SCORE_DIFF_TH\t\t\t\t8\n\n/*\n\tCalculate the corresponding score.\n*/\ninline u8 rtw_cal_rson_score(struct rtw_rson_struct *cand_rson_data, NDIS_802_11_RSSI  Rssi)\n{\n\tif ((cand_rson_data->hopcnt == RTW_RSON_HC_NOTREADY)\n\t\t|| (cand_rson_data->connectible == RTW_RSON_DENYCONNECT))\n\t\treturn RTW_RSON_SCORE_NOTCNNT;\n\n\treturn RTW_RSON_SCORE_MAX - (cand_rson_data->hopcnt * 10) + (Rssi/10);\n}\n\n/*************************************************/\n\n\nstatic u8 rtw_rson_block_bssid_idx = 0;\nu8 rtw_rson_block_bssid[10][6] = {\n\t\t\t/*{0x02, 0xE0, 0x4C, 0x07, 0xC3, 0xF6}*/\n};\n\n/* fake root, regard a real AP as a SO root */\nstatic u8 rtw_rson_root_bssid_idx = 0;\nu8 rtw_rson_root_bssid[10][6] = {\n\t\t\t/*{0x1c, 0x5f, 0x2b, 0x5a, 0x60, 0x24}*/\n};\n\nint is_match_bssid(u8 *mac, u8 bssid_array[][6], int num)\n{\n\tint i;\n\n\tfor (i = 0; i < num; i++)\n\t\tif (_rtw_memcmp(mac, bssid_array[i], 6) == _TRUE)\n\t\t\treturn _TRUE;\n\treturn _FALSE;\n}\n\nvoid init_rtw_rson_data(struct dvobj_priv *dvobj)\n{\n\t/*Aries  todo.  if pdvobj->rson_data.ver == 1 */\n\tdvobj->rson_data.ver = RTW_RSON_VER;\n\tdvobj->rson_data.id = CONFIG_RTW_REPEATER_SON_ID;\n#ifdef CONFIG_RTW_REPEATER_SON_ROOT\n\tdvobj->rson_data.hopcnt = RTW_RSON_HC_ROOT;\n\tdvobj->rson_data.connectible = RTW_RSON_ALLOWCONNECT;\n#else\n\tdvobj->rson_data.hopcnt = RTW_RSON_HC_NOTREADY;\n\tdvobj->rson_data.connectible = RTW_RSON_DENYCONNECT;\n#endif\n\tdvobj->rson_data.loading = 0;\n\t_rtw_memset(dvobj->rson_data.res, 0xAA, sizeof(dvobj->rson_data.res));\n}\n\nvoid\trtw_rson_get_property_str(_adapter *padapter, char *rson_data_str)\n{\n\tstruct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);\n\n\tsprintf(rson_data_str, \"version : \\t%d\\nid : \\t\\t%08x\\nhop count : \\t%d\\nconnectible : \\t%s\\nloading : \\t%d\\nreserve : \\t%16ph\\n\",\n\t\tpdvobj->rson_data.ver,\n\t\tpdvobj->rson_data.id,\n\t\tpdvobj->rson_data.hopcnt,\n\t\tpdvobj->rson_data.connectible ? \"connectable\":\"unconnectable\",\n\t\tpdvobj->rson_data.loading,\n\t\tpdvobj->rson_data.res);\n}\n\nint str2hexbuf(char *str, u8 *hexbuf, int len)\n{\n\tu8 *p;\n\tint i, slen, idx = 0;\n\n\tp = (unsigned char *)str;\n\tif ((*p != '0') || (*(p+1) != 'x'))\n\t\treturn _FALSE;\n\tslen = strlen(str);\n\tif (slen > (len*2) + 2)\n\t\treturn _FALSE;\n\tp += 2;\n\tfor (i = 0 ; i < len; i++, idx = idx+2) {\n\t\thexbuf[i] = key_2char2num(p[idx], p[idx + 1]);\n\t\tif (slen <= idx+2)\n\t\t\tbreak;\n\t}\n\treturn _TRUE;\n}\n\nint rtw_rson_set_property(_adapter *padapter, char *field, char *value)\n{\n\tstruct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);\n\tint num = 0;\n\n\tif (_rtw_memcmp(field, (u8 *)\"ver\", 3) == _TRUE)\n\t\tpdvobj->rson_data.ver = rtw_atoi(value);\n\telse if (_rtw_memcmp(field, (u8 *)\"id\", 2) == _TRUE)\n\t\tnum = sscanf(value, \"%08x\",   &(pdvobj->rson_data.id));\n\telse if (_rtw_memcmp(field, (u8 *)\"hc\", 2) == _TRUE)\n\t\tnum = sscanf(value, \"%hhu\", &(pdvobj->rson_data.hopcnt));\n\telse if (_rtw_memcmp(field, (u8 *)\"cnt\", 3) == _TRUE)\n\t\tnum = sscanf(value, \"%hhu\", &(pdvobj->rson_data.connectible));\n\telse if (_rtw_memcmp(field, (u8 *)\"loading\", 2) == _TRUE)\n\t\tnum = sscanf(value, \"%hhu\", &(pdvobj->rson_data.loading));\n\telse if (_rtw_memcmp(field, (u8 *)\"res\", 2) == _TRUE) {\n\t\tstr2hexbuf(value, pdvobj->rson_data.res, 16);\n\t\treturn 1;\n\t} else\n\t\treturn _FALSE;\n\treturn num;\n}\n\n/*\n\treturn :\tTRUE  -- competitor is taking advantage than condidate\n\t\t\tFALSE -- we should continue keeping candidate\n*/\nint rtw_rson_choose(struct wlan_network **candidate, struct wlan_network *competitor)\n{\n\ts16 comp_score = 0, cand_score = 0;\n\tstruct rtw_rson_struct rson_cand, rson_comp;\n\n\tif (is_match_bssid(competitor->network.MacAddress, rtw_rson_block_bssid, rtw_rson_block_bssid_idx) == _TRUE)\n\t\treturn _FALSE;\n\n\tif ((competitor == NULL)\n\t\t|| (rtw_get_rson_struct(&(competitor->network), &rson_comp) != _TRUE)\n\t\t|| (rson_comp.id != CONFIG_RTW_REPEATER_SON_ID))\n\t\treturn _FALSE;\n\n\tcomp_score = rtw_cal_rson_score(&rson_comp, competitor->network.Rssi);\n\tif (comp_score == RTW_RSON_SCORE_NOTCNNT)\n\t\treturn _FALSE;\n\n\tif (*candidate == NULL)\n\t\treturn _TRUE;\n\tif (rtw_get_rson_struct(&((*candidate)->network), &rson_cand) != _TRUE)\n\t\treturn _FALSE;\n\n\tcand_score = rtw_cal_rson_score(&rson_cand, (*candidate)->network.Rssi);\n\tRTW_INFO(\"%s: competitor_score=%d,  candidate_score=%d\\n\", __func__, comp_score, cand_score);\n\tif (comp_score - cand_score > RSON_SCORE_DIFF_TH)\n\t\treturn _TRUE;\n\n\treturn _FALSE;\n}\n\ninline u8 rtw_rson_varify_ie(u8 *p)\n{\n\tu8 *ptr = NULL;\n\tu8 ver;\n\tu32 id;\n\tu8 hopcnt;\n\tu8 allcnnt;\n\n\tptr = p + 2 + sizeof(RTW_RSON_OUI);\n\tver = *ptr;\n\n\t/*\tfor (ver == 1)\t*/\n\tif (ver != 1)\n\t\treturn _FALSE;\n\n\treturn _TRUE;\n}\n\n/*\n\tParsing RTK self-organization vendor IE\n*/\nint rtw_get_rson_struct(WLAN_BSSID_EX *bssid, struct  rtw_rson_struct *rson_data)\n{\n\tsint  limit = 0;\n\tu32\tlen;\n\tu8\t*p;\n\n\tif ((rson_data == NULL) || (bssid == NULL))\n\t\treturn -EINVAL;\n\n\t/*\tDefault\t\t*/\n\trson_data->id = 0;\n\trson_data->ver = 0;\n\trson_data->hopcnt = 0;\n\trson_data->connectible = 0;\n\trson_data->loading = 0;\n\t/*\tfake root\t\t*/\n\tif (is_match_bssid(bssid->MacAddress, rtw_rson_root_bssid, rtw_rson_root_bssid_idx) == _TRUE) {\n\t\trson_data->id = CONFIG_RTW_REPEATER_SON_ID;\n\t\trson_data->ver = RTW_RSON_VER;\n\t\trson_data->hopcnt = RTW_RSON_HC_ROOT;\n\t\trson_data->connectible = RTW_RSON_ALLOWCONNECT;\n\t\trson_data->loading = 0;\n\t\treturn _TRUE;\n\t}\n\tlimit = bssid->IELength - _BEACON_IE_OFFSET_;\n\n\tfor (p = bssid->IEs + _BEACON_IE_OFFSET_; ; p += (len + 2)) {\n\t\tp = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &len, limit);\n\t\tlimit -= len;\n\t\tif ((p == NULL) || (len == 0))\n\t\t\tbreak;\n\t\tif (p && (_rtw_memcmp(p + 2, RTW_RSON_OUI, sizeof(RTW_RSON_OUI)) == _TRUE)\n\t\t\t&& rtw_rson_varify_ie(p)) {\n\t\t\tp = p + 2 + sizeof(RTW_RSON_OUI);\n\t\t\trson_data->ver = *p;\n\t\t\t/*\tfor (ver == 1)\t\t*/\n\t\t\tp = p + 1;\n\t\t\trson_data->id = le32_to_cpup((__le32 *)p);\n\t\t\tp = p + 4;\n\t\t\trson_data->hopcnt = *p;\n\t\t\tp = p + 1;\n\t\t\trson_data->connectible = *p;\n\t\t\tp = p + 1;\n\t\t\trson_data->loading = *p;\n\n\t\t\treturn _TRUE;\n\t\t}\n\t}\n\treturn -EBADMSG;\n}\n\nu32 rtw_rson_append_ie(_adapter *padapter, unsigned char *pframe, u32 *len)\n{\n\tu8 *ptr, *ori, ie_len = 0;\n\tstruct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n/*\tstatic int iii = 0;*/\n\n\tif ((!pdvobj) || (!pframe))\n\t\treturn 0;\n\tptr = ori = pframe;\n\t*ptr++ = _VENDOR_SPECIFIC_IE_;\n\t*ptr++ = ie_len = sizeof(RTW_RSON_OUI)+sizeof(pdvobj->rson_data);\n\t_rtw_memcpy(ptr, RTW_RSON_OUI, sizeof(RTW_RSON_OUI));\n\tptr = ptr + sizeof(RTW_RSON_OUI);\n\t*ptr++ = pdvobj->rson_data.ver;\n\t*(s32 *)ptr = cpu_to_le32(pdvobj->rson_data.id);\n\tptr = ptr + sizeof(pdvobj->rson_data.id);\n\t*ptr++ = pdvobj->rson_data.hopcnt;\n\t*ptr++ = pdvobj->rson_data.connectible;\n\t*ptr++ = pdvobj->rson_data.loading;\n\t_rtw_memcpy(ptr, pdvobj->rson_data.res, sizeof(pdvobj->rson_data.res));\n\tpframe = ptr;\n/*\n\tiii = iii % 20;\n\tif (iii++ == 0)\n\t\tRTW_INFO(\"%s : RTW RSON IE : %20ph\\n\", __func__, ori);\n*/\n\t*len += (ie_len+2);\n\treturn ie_len;\n\n}\n\nvoid rtw_rson_do_disconnect(_adapter *padapter)\n{\n\tstruct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);\n\n\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n#ifndef CONFIG_RTW_REPEATER_SON_ROOT\n\tpdvobj->rson_data.ver = RTW_RSON_VER;\n\tpdvobj->rson_data.id = CONFIG_RTW_REPEATER_SON_ID;\n\tpdvobj->rson_data.hopcnt = RTW_RSON_HC_NOTREADY;\n\tpdvobj->rson_data.connectible = RTW_RSON_DENYCONNECT;\n\tpdvobj->rson_data.loading = 0;\n\trtw_mi_tx_beacon_hdl(padapter);\n#endif\n}\n\nvoid rtw_rson_join_done(_adapter *padapter)\n{\n\tstruct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);\n\tWLAN_BSSID_EX\t*cur_network = NULL;\n\tstruct rtw_rson_struct  rson_data;\n\n\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n\tif (!padapter->mlmepriv.cur_network_scanned)\n\t\treturn;\n\tcur_network = &(padapter->mlmepriv.cur_network_scanned->network);\n\tif (rtw_get_rson_struct(cur_network, &rson_data) != _TRUE) {\n\t\tRTW_ERR(\"%s: try to join a improper network(%s)\\n\", __func__, cur_network->Ssid.Ssid);\n\t\treturn;\n\t}\n\n#ifndef CONFIG_RTW_REPEATER_SON_ROOT\n\t/* update rson_data */\n\tpdvobj->rson_data.ver = RTW_RSON_VER;\n\tpdvobj->rson_data.id = rson_data.id;\n\tpdvobj->rson_data.hopcnt = rson_data.hopcnt + 1;\n\tpdvobj->rson_data.connectible = RTW_RSON_ALLOWCONNECT;\n\tpdvobj->rson_data.loading = 0;\n\trtw_mi_tx_beacon_hdl(padapter);\n#endif\n}\n\nint rtw_rson_isupdate_roamcan(struct mlme_priv *mlme\n\t, struct wlan_network **candidate, struct wlan_network *competitor)\n{\n\tstruct rtw_rson_struct  rson_cand, rson_comp, rson_curr;\n\ts16 comp_score, cand_score, curr_score;\n\n\tif ((competitor == NULL)\n\t\t|| (rtw_get_rson_struct(&(competitor->network), &rson_comp) != _TRUE)\n\t\t|| (rson_comp.id != CONFIG_RTW_REPEATER_SON_ID))\n\t\treturn _FALSE;\n\n\tif (is_match_bssid(competitor->network.MacAddress, rtw_rson_block_bssid, rtw_rson_block_bssid_idx) == _TRUE)\n\t\treturn _FALSE;\n\n\tif ((!mlme->cur_network_scanned)\n\t\t|| (mlme->cur_network_scanned == competitor)\n\t\t|| (rtw_get_rson_struct(&(mlme->cur_network_scanned->network), &rson_curr)) != _TRUE)\n\t\treturn _FALSE;\n\n\tif (rtw_get_passing_time_ms((u32)competitor->last_scanned) >= mlme->roam_scanr_exp_ms)\n\t\treturn _FALSE;\n\n\tcomp_score = rtw_cal_rson_score(&rson_comp, competitor->network.Rssi);\n\tcurr_score = rtw_cal_rson_score(&rson_curr, mlme->cur_network_scanned->network.Rssi);\n\tif (comp_score - curr_score < RSON_SCORE_DIFF_TH)\n\t\treturn _FALSE;\n\n\tif (*candidate == NULL)\n\t\treturn _TRUE;\n\n\tif (rtw_get_rson_struct(&((*candidate)->network), &rson_cand) != _TRUE) {\n\t\tRTW_ERR(\"%s : Unable to get rson_struct from candidate(%s -- \" MAC_FMT\")\\n\",\n\t\t\t\t__func__, (*candidate)->network.Ssid.Ssid, MAC_ARG((*candidate)->network.MacAddress));\n\t\treturn _FALSE;\n\t}\n\tcand_score = rtw_cal_rson_score(&rson_cand, (*candidate)->network.Rssi);\n\tRTW_DBG(\"comp_score=%d , cand_score=%d , curr_score=%d\\n\", comp_score, cand_score, curr_score);\n\tif (cand_score < comp_score)\n\t\treturn _TRUE;\n\n#if 0\t\t/*\tHandle 11R protocol\t*/\n#ifdef CONFIG_RTW_80211R\n\tif (rtw_chk_ft_flags(adapter, RTW_FT_SUPPORTED)) {\n\t\tptmp = rtw_get_ie(&competitor->network.IEs[12], _MDIE_, &mdie_len, competitor->network.IELength-12);\n\t\tif (ptmp) {\n\t\t\tif (!_rtw_memcmp(&pftpriv->mdid, ptmp+2, 2))\n\t\t\t\tgoto exit;\n\n\t\t\t/*The candidate don't support over-the-DS*/\n\t\t\tif (rtw_chk_ft_flags(adapter, RTW_FT_STA_OVER_DS_SUPPORTED)) {\n\t\t\t\tif ((rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && !(*(ptmp+4) & 0x01)) ||\n\t\t\t\t\t(!rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && (*(ptmp+4) & 0x01))) {\n\t\t\t\t\tRTW_INFO(\"FT: ignore the candidate(\" MAC_FMT \") for over-the-DS\\n\", MAC_ARG(competitor->network.MacAddress));\n\t\t\t\t\trtw_clr_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED);\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t}\n\t\t} else\n\t\t\tgoto exit;\n\t}\n#endif\n#endif\n\treturn _FALSE;\n}\n\nvoid rtw_rson_show_survey_info(struct seq_file *m, _list *plist, _list *phead)\n{\n\tstruct wlan_network\t*pnetwork = NULL;\n\tstruct rtw_rson_struct  rson_data;\n\ts16 rson_score;\n\tu16  index = 0;\n\n\tRTW_PRINT_SEL(m, \"%5s  %-17s  %3s  %5s %14s  %10s  %-3s  %5s %32s\\n\", \"index\", \"bssid\", \"ch\", \"id\", \"hop_cnt\", \"loading\", \"RSSI\", \"score\", \"ssid\");\n\twhile (1) {\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\t\tif (!pnetwork)\n\t\t\tbreak;\n\n\t\t_rtw_memset(&rson_data, 0, sizeof(rson_data));\n\t\trson_score = 0;\n\t\tif (rtw_get_rson_struct(&(pnetwork->network), &rson_data) == _TRUE)\n\t\t\trson_score = rtw_cal_rson_score(&rson_data, pnetwork->network.Rssi);\n\t\tRTW_PRINT_SEL(m, \"%5d  \"MAC_FMT\" %3d  0x%08x %6d %10d   %6d %6d   %32s\\n\",\n\t\t\t      ++index,\n\t\t\t      MAC_ARG(pnetwork->network.MacAddress),\n\t\t\t      pnetwork->network.Configuration.DSConfig,\n\t\t\t      rson_data.id,\n\t\t\t      rson_data.hopcnt,\n\t\t\t      rson_data.loading,\n\t\t\t      (int)pnetwork->network.Rssi,\n\t\t\t      rson_score,\n\t\t\t      pnetwork->network.Ssid.Ssid);\n\t\tplist = get_next(plist);\n\t\t}\n\n}\n\n/*\n\tDescription :\tAs a AP role, We need to check the qualify of associating STA.\n\t\t\t\t\tWe also need to check if we are ready to be associated.\n\n\treturn :\tTRUE  -- AP REJECT this STA\n\t\t\t\tFALSE -- AP ACCEPT this STA\n*/\nu8 rtw_rson_ap_check_sta(_adapter *padapter, u8 *pframe, uint pkt_len, unsigned short ie_offset)\n{\n\tstruct wlan_network\t*pnetwork = NULL;\n\tstruct rtw_rson_struct  rson_target;\n\tstruct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);\n\tint len = 0;\n\tu8 ret = _FALSE;\n\tu8 *p;\n\n#ifndef CONFIG_RTW_REPEATER_SON_ROOT\n\t_rtw_memset(&rson_target, 0, sizeof(rson_target));\n\tfor (p = pframe + WLAN_HDR_A3_LEN + ie_offset; ; p += (len + 2)) {\n\t\tp = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &len, pkt_len - WLAN_HDR_A3_LEN - ie_offset);\n\n\t\tif ((p == NULL) || (len == 0))\n\t\t\tbreak;\n\n\t\tif (p && (_rtw_memcmp(p + 2, RTW_RSON_OUI, sizeof(RTW_RSON_OUI)) == _TRUE)\n\t\t\t&& rtw_rson_varify_ie(p)) {\n\t\t\tp = p + 2 + sizeof(RTW_RSON_OUI);\n\t\t\trson_target.ver = *p;\n\t\t\t/*\tfor (ver == 1)\t\t*/\n\t\t\tp = p + 1;\n\t\t\trson_target.id = le32_to_cpup((__le32 *)p);\n\t\t\tp = p + 4;\n\t\t\trson_target.hopcnt = *p;\n\t\t\tp = p + 1;\n\t\t\trson_target.connectible = *p;\n\t\t\tp = p + 1;\n\t\t\trson_target.loading = *p;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (rson_target.id == 0)\t\t/*\tNormal STA, not a RSON STA\t*/\n\t\tret = _FALSE;\n\telse if (rson_target.id != pdvobj->rson_data.id) {\n\t\tret = _TRUE;\n\t\tRTW_INFO(\"%s : Reject AssoReq because RSON ID not match, STA=%08x, our=%08x\\n\",\n\t\t\t\t__func__, rson_target.id, pdvobj->rson_data.id);\n\t} else if ((pdvobj->rson_data.hopcnt == RTW_RSON_HC_NOTREADY)\n\t\t|| (pdvobj->rson_data.connectible == RTW_RSON_DENYCONNECT)) {\n\t\tret = _TRUE;\n\t\tRTW_INFO(\"%s : Reject AssoReq becuase our hopcnt=%d or connectbile=%d\\n\",\n\t\t\t\t__func__, pdvobj->rson_data.hopcnt, pdvobj->rson_data.connectible);\n\t}\n#endif\n\treturn ret;\n}\n\nu8 rtw_rson_scan_wk_cmd(_adapter *padapter, int op)\n{\n\tstruct cmd_obj *ph2c;\n\tstruct drvextra_cmd_parm *pdrvextra_cmd_parm;\n\tstruct cmd_priv *pcmdpriv = &padapter->cmdpriv;\n\tu8 *extra_cmd_buf;\n\tu8 res = _SUCCESS;\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tpdrvextra_cmd_parm->ec_id = RSON_SCAN_WK_CID;\n\tpdrvextra_cmd_parm->type = op;\n\tpdrvextra_cmd_parm->size = 0;\n\tpdrvextra_cmd_parm->pbuf = NULL;\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\n\tres = rtw_enqueue_cmd(pcmdpriv, ph2c);\n\nexit:\n\treturn res;\n\n}\n\nvoid rtw_rson_scan_cmd_hdl(_adapter *padapter, int op)\n{\n\tstruct cmd_priv *pcmdpriv = &padapter->cmdpriv;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tu8 val8;\n\n\tif (mlmeext_chk_scan_state(pmlmeext, SCAN_DISABLE) != _TRUE)\n\t\treturn;\n\tif (op == RSON_SCAN_PROCESS) {\n\t\tpadapter->rtw_rson_scanstage = RSON_SCAN_PROCESS;\n\t\tval8 = 0x1e;\n\t\trtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &val8, _FALSE);\n\t\tval8 = 1;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));\n\t\tissue_probereq(padapter, NULL, NULL);\n\t\t/*\tstop rson_scan after 100ms\t*/\n\t\t_set_timer(&(pmlmeext->rson_scan_timer), 100);\n\t} else if  (op == RSON_SCAN_DISABLE) {\n\t\tpadapter->rtw_rson_scanstage = RSON_SCAN_DISABLE;\n\t\tval8 = 0;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));\n\t\tval8 = 0xff;\n\t\trtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &val8, _FALSE);\n\t\t/*\treport_surveydone_event(padapter);*/\n\t\tif (pmlmepriv->to_join == _TRUE) {\n\t\t\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) != _TRUE) {\n\t\t\t\tint s_ret;\n\n\t\t\t\tset_fwstate(pmlmepriv, _FW_UNDER_LINKING);\n\t\t\t\tpmlmepriv->to_join = _FALSE;\n\t\t\t\ts_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv);\n\t\t\t\tif (s_ret == _SUCCESS)\n\t\t\t\t\t_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);\n\t\t\t\telse if (s_ret == 2) {\n\t\t\t\t\t_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);\n\t\t\t\t\trtw_indicate_connect(padapter);\n\t\t\t\t} else {\n\t\t\t\t\tRTW_INFO(\"try_to_join, but select scanning queue fail, to_roam:%d\\n\", rtw_to_roam(padapter));\n\t\t\t\t\tif (rtw_to_roam(padapter) != 0) {\n\t\t\t\t\t\tif (rtw_dec_to_roam(padapter) == 0) {\n\t\t\t\t\t\t\trtw_set_to_roam(padapter, 0);\n\t\t\t\t\t\t\trtw_free_assoc_resources(padapter, _TRUE);\n\t\t\t\t\t\t\trtw_indicate_disconnect(padapter, 0, _FALSE);\n\t\t\t\t\t\t} else\n\t\t\t\t\t\t\tpmlmepriv->to_join = _TRUE;\n\t\t\t\t\t} else\n\t\t\t\t\t\trtw_indicate_disconnect(padapter, 0, _FALSE);\n\t\t\t\t\t_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tif (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) {\n\t\t\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE)\n\t\t\t\t    && check_fwstate(pmlmepriv, _FW_LINKED)) {\n\t\t\t\t\tif (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) {\n#ifdef CONFIG_RTW_80211R\n\t\t\t\t\t\tif (rtw_chk_ft_flags(padapter, RTW_FT_OVER_DS_SUPPORTED)) {\n\t\t\t\t\t\t\tstart_clnt_ft_action(adapter, (u8 *)pmlmepriv->roam_network->network.MacAddress);\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t/*wait a little time to retrieve packets buffered in the current ap while scan*/\n\t\t\t\t\t\t\t_set_timer(&pmlmeext->ft_roam_timer, 30);\n\t\t\t\t\t\t}\n#else\n\t\t\t\t\t\treceive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress\n\t\t\t\t\t\t\t, WLAN_REASON_ACTIVE_ROAM, _FALSE);\n#endif\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tissue_action_BSSCoexistPacket(padapter);\n\t\t\tissue_action_BSSCoexistPacket(padapter);\n\t\t\tissue_action_BSSCoexistPacket(padapter);\n\t\t}\n\t} else {\n\t\tRTW_ERR(\"%s : improper parameter -- op = %d\\n\", __func__, op);\n\t}\n}\n\n#endif\t/* CONFIG_RTW_REPEATER_SON */\n"
  },
  {
    "path": "core/rtw_sdio.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_SDIO_C_\n\n#include <drv_types.h>\t\t/* struct dvobj_priv and etc. */\n#include <drv_types_sdio.h>\t/* RTW_SDIO_ADDR_CMD52_GEN */\n\n/*\n * Description:\n *\tUse SDIO cmd52 or cmd53 to read/write data\n *\n * Parameters:\n *\td\tpointer of device object(struct dvobj_priv)\n *\taddr\tSDIO address, 17 bits\n *\tbuf\tbuffer for I/O\n *\tlen\tlength\n *\twrite\t0:read, 1:write\n *\tcmd52\t0:cmd52, 1:cmd53\n *\n * Return:\n *\t_SUCCESS\tI/O ok.\n *\t_FAIL\t\tI/O fail.\n */\nstatic u8 sdio_io(struct dvobj_priv *d, u32 addr, void *buf, size_t len, u8 write, u8 cmd52)\n{\n#ifdef DBG_SDIO\n#if (DBG_SDIO >= 3)\n\tstruct sdio_data *sdio;\n#endif /* DBG_SDIO >= 3 */\n#endif /* DBG_SDIO */\n\tu32 addr_drv;\t/* address with driver defined bit */\n\tint err;\n\tu8 retry = 0;\n\tu8 stop_retry = _FALSE;\t/* flag for stopping retry or not */\n\n\n#ifdef DBG_SDIO\n#if (DBG_SDIO >= 3)\n\tsdio = &d->intf_data;\n#endif /* DBG_SDIO >= 3 */\n#endif /* DBG_SDIO */\n\n\tif (rtw_is_surprise_removed(dvobj_get_primary_adapter(d))) {\n\t\tRTW_ERR(\"%s: bSurpriseRemoved, skip %s 0x%05x, %zu bytes\\n\",\n\t\t\t__FUNCTION__, write?\"write\":\"read\", addr, len);\n\t\treturn _FAIL;\n\t}\n\n\taddr_drv = addr;\n\tif (cmd52)\n\t\taddr_drv = RTW_SDIO_ADDR_CMD52_GEN(addr_drv);\n\n\tdo {\n\t\tif (write)\n\t\t\terr = d->intf_ops->write(d, addr_drv, buf, len, 0);\n\t\telse\n\t\t\terr = d->intf_ops->read(d, addr_drv, buf, len, 0);\n\t\tif (!err) {\n\t\t\tif (retry) {\n\t\t\t\tRTW_INFO(\"%s: Retry %s OK! addr=0x%05x %zu bytes, retry=%u,%u\\n\",\n\t\t\t\t\t __FUNCTION__, write?\"write\":\"read\",\n\t\t\t\t\t addr, len, retry, ATOMIC_READ(&d->continual_io_error));\n\t\t\t\tRTW_INFO_DUMP(\"Data: \", buf, len);\n\t\t\t}\n\t\t\trtw_reset_continual_io_error(d);\n\t\t\tbreak;\n\t\t}\n\t\tRTW_ERR(\"%s: %s FAIL! error(%d) addr=0x%05x %zu bytes, retry=%u,%u\\n\",\n\t\t\t__FUNCTION__, write?\"write\":\"read\", err, addr, len,\n\t\t\tretry, ATOMIC_READ(&d->continual_io_error));\n\n#ifdef DBG_SDIO\n#if (DBG_SDIO >= 3)\n\t\tif (sdio->dbg_enable) {\n\t\t\tif (sdio->err_test && sdio->err_test_triggered)\n\t\t\t\tsdio->err_test = 0;\n\n\t\t\tif (sdio->err_stop) {\n\t\t\t\tRTW_ERR(\"%s: I/O error! Set surprise remove flag ON!\\n\",\n\t\t\t\t\t__FUNCTION__);\n\t\t\t\trtw_set_surprise_removed(dvobj_get_primary_adapter(d));\n\t\t\t\treturn _FAIL;\n\t\t\t}\n\t\t}\n#endif /* DBG_SDIO >= 3 */\n#endif /* DBG_SDIO */\n\n\t\tretry++;\n\t\tstop_retry = rtw_inc_and_chk_continual_io_error(d);\n\t\tif ((err == -1) || (stop_retry == _TRUE) || (retry > SD_IO_TRY_CNT)) {\n\t\t\t/* critical error, unrecoverable */\n\t\t\tRTW_ERR(\"%s: Fatal error! Set surprise remove flag ON! (retry=%u,%u)\\n\",\n\t\t\t\t__FUNCTION__, retry, ATOMIC_READ(&d->continual_io_error));\n\t\t\trtw_set_surprise_removed(dvobj_get_primary_adapter(d));\n\t\t\treturn _FAIL;\n\t\t}\n\n\t\t/* WLAN IOREG or SDIO Local */\n\t\tif ((addr & 0x10000) || !(addr & 0xE000)) {\n\t\t\tRTW_WARN(\"%s: Retry %s addr=0x%05x %zu bytes, retry=%u,%u\\n\",\n\t\t\t\t __FUNCTION__, write?\"write\":\"read\", addr, len,\n\t\t\t\t retry, ATOMIC_READ(&d->continual_io_error));\n\t\t\tcontinue;\n\t\t}\n\t\treturn _FAIL;\n\t} while (1);\n\n\treturn _SUCCESS;\n}\n\nu8 rtw_sdio_read_cmd52(struct dvobj_priv *d, u32 addr, void *buf, size_t len)\n{\n\treturn sdio_io(d, addr, buf, len, 0, 1);\n}\n\nu8 rtw_sdio_read_cmd53(struct dvobj_priv *d, u32 addr, void *buf, size_t len)\n{\n\treturn sdio_io(d, addr, buf, len, 0, 0);\n}\n\nu8 rtw_sdio_write_cmd52(struct dvobj_priv *d, u32 addr, void *buf, size_t len)\n{\n\treturn sdio_io(d, addr, buf, len, 1, 1);\n}\n\nu8 rtw_sdio_write_cmd53(struct dvobj_priv *d, u32 addr, void *buf, size_t len)\n{\n\treturn sdio_io(d, addr, buf, len, 1, 0);\n}\n\nu8 rtw_sdio_f0_read(struct dvobj_priv *d, u32 addr, void *buf, size_t len)\n{\n\tint err;\n\tu8 ret;\n\n\n\tret = _SUCCESS;\n\taddr = RTW_SDIO_ADDR_F0_GEN(addr);\n\n\terr = d->intf_ops->read(d, addr, buf, len, 0);\n\tif (err)\n\t\tret = _FAIL;\n\n\treturn ret;\n}\n"
  },
  {
    "path": "core/rtw_security.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define  _RTW_SECURITY_C_\n\n#include <drv_types.h>\n\nstatic const char *_security_type_str[] = {\n\t\"N/A\",\n\t\"WEP40\",\n\t\"TKIP\",\n\t\"TKIP_WM\",\n\t\"AES\",\n\t\"WEP104\",\n\t\"SMS4\",\n\t\"WEP_WPA\",\n\t\"BIP\",\n};\n\nconst char *security_type_str(u8 value)\n{\n#ifdef CONFIG_IEEE80211W\n\tif (value <= _BIP_)\n#else\n\tif (value <= _WEP_WPA_MIXED_)\n#endif\n\t\treturn _security_type_str[value];\n\treturn NULL;\n}\n\n#ifdef DBG_SW_SEC_CNT\n#define WEP_SW_ENC_CNT_INC(sec, ra) do {\\\n\tif (is_broadcast_mac_addr(ra)) \\\n\t\tsec->wep_sw_enc_cnt_bc++; \\\n\telse if (is_multicast_mac_addr(ra)) \\\n\t\tsec->wep_sw_enc_cnt_mc++; \\\n\telse \\\n\t\tsec->wep_sw_enc_cnt_uc++; \\\n\t} while (0)\n\n#define WEP_SW_DEC_CNT_INC(sec, ra) do {\\\n\tif (is_broadcast_mac_addr(ra)) \\\n\t\tsec->wep_sw_dec_cnt_bc++; \\\n\telse if (is_multicast_mac_addr(ra)) \\\n\t\tsec->wep_sw_dec_cnt_mc++; \\\n\telse \\\n\t\tsec->wep_sw_dec_cnt_uc++; \\\n\t} while (0)\n\n#define TKIP_SW_ENC_CNT_INC(sec, ra) do {\\\n\tif (is_broadcast_mac_addr(ra)) \\\n\t\tsec->tkip_sw_enc_cnt_bc++; \\\n\telse if (is_multicast_mac_addr(ra)) \\\n\t\tsec->tkip_sw_enc_cnt_mc++; \\\n\telse \\\n\t\tsec->tkip_sw_enc_cnt_uc++; \\\n\t} while (0)\n\n#define TKIP_SW_DEC_CNT_INC(sec, ra) do {\\\n\tif (is_broadcast_mac_addr(ra)) \\\n\t\tsec->tkip_sw_dec_cnt_bc++; \\\n\telse if (is_multicast_mac_addr(ra)) \\\n\t\tsec->tkip_sw_dec_cnt_mc++; \\\n\telse \\\n\t\tsec->tkip_sw_dec_cnt_uc++; \\\n\t} while (0)\n\n#define AES_SW_ENC_CNT_INC(sec, ra) do {\\\n\tif (is_broadcast_mac_addr(ra)) \\\n\t\tsec->aes_sw_enc_cnt_bc++; \\\n\telse if (is_multicast_mac_addr(ra)) \\\n\t\tsec->aes_sw_enc_cnt_mc++; \\\n\telse \\\n\t\tsec->aes_sw_enc_cnt_uc++; \\\n\t} while (0)\n\n#define AES_SW_DEC_CNT_INC(sec, ra) do {\\\n\tif (is_broadcast_mac_addr(ra)) \\\n\t\tsec->aes_sw_dec_cnt_bc++; \\\n\telse if (is_multicast_mac_addr(ra)) \\\n\t\tsec->aes_sw_dec_cnt_mc++; \\\n\telse \\\n\t\tsec->aes_sw_dec_cnt_uc++; \\\n\t} while (0)\n#else\n#define WEP_SW_ENC_CNT_INC(sec, ra)\n#define WEP_SW_DEC_CNT_INC(sec, ra)\n#define TKIP_SW_ENC_CNT_INC(sec, ra)\n#define TKIP_SW_DEC_CNT_INC(sec, ra)\n#define AES_SW_ENC_CNT_INC(sec, ra)\n#define AES_SW_DEC_CNT_INC(sec, ra)\n#endif /* DBG_SW_SEC_CNT */\n\n/* *****WEP related***** */\n\n#define CRC32_POLY 0x04c11db7\n\nstruct arc4context {\n\tu32 x;\n\tu32 y;\n\tu8 state[256];\n};\n\n\nstatic void arcfour_init(struct arc4context\t*parc4ctx, u8 *key, u32\tkey_len)\n{\n\tu32\tt, u;\n\tu32\tkeyindex;\n\tu32\tstateindex;\n\tu8 *state;\n\tu32\tcounter;\n\tstate = parc4ctx->state;\n\tparc4ctx->x = 0;\n\tparc4ctx->y = 0;\n\tfor (counter = 0; counter < 256; counter++)\n\t\tstate[counter] = (u8)counter;\n\tkeyindex = 0;\n\tstateindex = 0;\n\tfor (counter = 0; counter < 256; counter++) {\n\t\tt = state[counter];\n\t\tstateindex = (stateindex + key[keyindex] + t) & 0xff;\n\t\tu = state[stateindex];\n\t\tstate[stateindex] = (u8)t;\n\t\tstate[counter] = (u8)u;\n\t\tif (++keyindex >= key_len)\n\t\t\tkeyindex = 0;\n\t}\n}\nstatic u32 arcfour_byte(struct arc4context\t*parc4ctx)\n{\n\tu32 x;\n\tu32 y;\n\tu32 sx, sy;\n\tu8 *state;\n\tstate = parc4ctx->state;\n\tx = (parc4ctx->x + 1) & 0xff;\n\tsx = state[x];\n\ty = (sx + parc4ctx->y) & 0xff;\n\tsy = state[y];\n\tparc4ctx->x = x;\n\tparc4ctx->y = y;\n\tstate[y] = (u8)sx;\n\tstate[x] = (u8)sy;\n\treturn state[(sx + sy) & 0xff];\n}\n\n\nstatic void arcfour_encrypt(struct arc4context\t*parc4ctx,\n\t\t\t    u8 *dest,\n\t\t\t    u8 *src,\n\t\t\t    u32 len)\n{\n\tu32\ti;\n\tfor (i = 0; i < len; i++)\n\t\tdest[i] = src[i] ^ (unsigned char)arcfour_byte(parc4ctx);\n}\n\nstatic sint bcrc32initialized = 0;\nstatic u32 crc32_table[256];\n\n\nstatic u8 crc32_reverseBit(u8 data)\n{\n\treturn (u8)((data << 7) & 0x80) | ((data << 5) & 0x40) | ((data << 3) & 0x20) | ((data << 1) & 0x10) | ((data >> 1) & 0x08) | ((data >> 3) & 0x04) | ((data >> 5) & 0x02) | ((\n\t\t\t\tdata >> 7) & 0x01) ;\n}\n\nstatic void crc32_init(void)\n{\n\tif (bcrc32initialized == 1)\n\t\tgoto exit;\n\telse {\n\t\tsint i, j;\n\t\tu32 c;\n\t\tu8 *p = (u8 *)&c, *p1;\n\t\tu8 k;\n\n\t\tc = 0x12340000;\n\n\t\tfor (i = 0; i < 256; ++i) {\n\t\t\tk = crc32_reverseBit((u8)i);\n\t\t\tfor (c = ((u32)k) << 24, j = 8; j > 0; --j)\n\t\t\t\tc = c & 0x80000000 ? (c << 1) ^ CRC32_POLY : (c << 1);\n\t\t\tp1 = (u8 *)&crc32_table[i];\n\n\t\t\tp1[0] = crc32_reverseBit(p[3]);\n\t\t\tp1[1] = crc32_reverseBit(p[2]);\n\t\t\tp1[2] = crc32_reverseBit(p[1]);\n\t\t\tp1[3] = crc32_reverseBit(p[0]);\n\t\t}\n\t\tbcrc32initialized = 1;\n\t}\nexit:\n\treturn;\n}\n\nstatic u32 getcrc32(u8 *buf, sint len)\n{\n\tu8 *p;\n\tu32  crc;\n\tif (bcrc32initialized == 0)\n\t\tcrc32_init();\n\n\tcrc = 0xffffffff;       /* preload shift register, per CRC-32 spec */\n\n\tfor (p = buf; len > 0; ++p, --len)\n\t\tcrc = crc32_table[(crc ^ *p) & 0xff] ^ (crc >> 8);\n\treturn ~crc;    /* transmit complement, per CRC-32 spec */\n}\n\n\n/*\n\tNeed to consider the fragment  situation\n*/\nvoid rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe)\n{\n\t/* exclude ICV */\n\n\tunsigned char\tcrc[4];\n\tstruct arc4context\t mycontext;\n\n\tsint\tcurfragnum, length;\n\tu32\tkeylength;\n\n\tu8\t*pframe, *payload, *iv;   /* ,*wepkey */\n\tu8\twepkey[16];\n\tu8   hw_hdr_offset = 0;\n\tstruct\tpkt_attrib\t*pattrib = &((struct xmit_frame *)pxmitframe)->attrib;\n\tstruct\tsecurity_priv\t*psecuritypriv = &padapter->securitypriv;\n\tstruct\txmit_priv\t\t*pxmitpriv = &padapter->xmitpriv;\n\n\n\n\tif (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)\n\t\treturn;\n\n#ifdef CONFIG_USB_TX_AGGREGATION\n\thw_hdr_offset = TXDESC_SIZE +\n\t\t(((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);\n#else\n#ifdef CONFIG_TX_EARLY_MODE\n\thw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;\n#else\n\thw_hdr_offset = TXDESC_OFFSET;\n#endif\n#endif\n\n\tpframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset;\n\n\t/* start to encrypt each fragment */\n\tif ((pattrib->encrypt == _WEP40_) || (pattrib->encrypt == _WEP104_)) {\n\t\tkeylength = psecuritypriv->dot11DefKeylen[psecuritypriv->dot11PrivacyKeyIndex];\n\n\t\tfor (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {\n\t\t\tiv = pframe + pattrib->hdrlen;\n\t\t\t_rtw_memcpy(&wepkey[0], iv, 3);\n\t\t\t_rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0], keylength);\n\t\t\tpayload = pframe + pattrib->iv_len + pattrib->hdrlen;\n\n\t\t\tif ((curfragnum + 1) == pattrib->nr_frags) {\n\t\t\t\t/* the last fragment */\n\n\t\t\t\tlength = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;\n\n\t\t\t\t*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length));\n\n\t\t\t\tarcfour_init(&mycontext, wepkey, 3 + keylength);\n\t\t\t\tarcfour_encrypt(&mycontext, payload, payload, length);\n\t\t\t\tarcfour_encrypt(&mycontext, payload + length, crc, 4);\n\n\t\t\t} else {\n\t\t\t\tlength = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ;\n\t\t\t\t*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length));\n\t\t\t\tarcfour_init(&mycontext, wepkey, 3 + keylength);\n\t\t\t\tarcfour_encrypt(&mycontext, payload, payload, length);\n\t\t\t\tarcfour_encrypt(&mycontext, payload + length, crc, 4);\n\n\t\t\t\tpframe += pxmitpriv->frag_len;\n\t\t\t\tpframe = (u8 *)RND4((SIZE_PTR)(pframe));\n\n\t\t\t}\n\n\t\t}\n\n\t\tWEP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra);\n\t}\n\n\n}\n\nvoid rtw_wep_decrypt(_adapter  *padapter, u8 *precvframe)\n{\n\t/* exclude ICV */\n\tu8\tcrc[4];\n\tstruct arc4context\t mycontext;\n\tsint\tlength;\n\tu32\tkeylength;\n\tu8\t*pframe, *payload, *iv, wepkey[16];\n\tu8\t keyindex;\n\tstruct\trx_pkt_attrib\t*prxattrib = &(((union recv_frame *)precvframe)->u.hdr.attrib);\n\tstruct\tsecurity_priv\t*psecuritypriv = &padapter->securitypriv;\n\n\n\tpframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;\n\n\t/* start to decrypt recvframe */\n\tif ((prxattrib->encrypt == _WEP40_) || (prxattrib->encrypt == _WEP104_)) {\n\t\tiv = pframe + prxattrib->hdrlen;\n\t\t/* keyindex=(iv[3]&0x3); */\n\t\tkeyindex = prxattrib->key_index;\n\t\tkeylength = psecuritypriv->dot11DefKeylen[keyindex];\n\t\t_rtw_memcpy(&wepkey[0], iv, 3);\n\t\t/* _rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0],keylength); */\n\t\t_rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[keyindex].skey[0], keylength);\n\t\tlength = ((union recv_frame *)precvframe)->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len;\n\n\t\tpayload = pframe + prxattrib->iv_len + prxattrib->hdrlen;\n\n\t\t/* decrypt payload include icv */\n\t\tarcfour_init(&mycontext, wepkey, 3 + keylength);\n\t\tarcfour_encrypt(&mycontext, payload, payload,  length);\n\n\t\t/* calculate icv and compare the icv */\n\t\t*((u32 *)crc) = le32_to_cpu(getcrc32(payload, length - 4));\n\n\n\t\tWEP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);\n\t}\n\n\n\treturn;\n\n}\n\n/* 3\t\t=====TKIP related===== */\n\nstatic u32 secmicgetuint32(u8 *p)\n/* Convert from Byte[] to Us4Byte32 in a portable way */\n{\n\ts32 i;\n\tu32 res = 0;\n\tfor (i = 0; i < 4; i++)\n\t\tres |= ((u32)(*p++)) << (8 * i);\n\treturn res;\n}\n\nstatic void secmicputuint32(u8 *p, u32 val)\n/* Convert from Us4Byte32 to Byte[] in a portable way */\n{\n\tlong i;\n\tfor (i = 0; i < 4; i++) {\n\t\t*p++ = (u8)(val & 0xff);\n\t\tval >>= 8;\n\t}\n}\n\nstatic void secmicclear(struct mic_data *pmicdata)\n{\n\t/* Reset the state to the empty message. */\n\tpmicdata->L = pmicdata->K0;\n\tpmicdata->R = pmicdata->K1;\n\tpmicdata->nBytesInM = 0;\n\tpmicdata->M = 0;\n}\n\nvoid rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key)\n{\n\t/* Set the key */\n\tpmicdata->K0 = secmicgetuint32(key);\n\tpmicdata->K1 = secmicgetuint32(key + 4);\n\t/* and reset the message */\n\tsecmicclear(pmicdata);\n}\n\nvoid rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b)\n{\n\t/* Append the byte to our word-sized buffer */\n\tpmicdata->M |= ((unsigned long)b) << (8 * pmicdata->nBytesInM);\n\tpmicdata->nBytesInM++;\n\t/* Process the word if it is full. */\n\tif (pmicdata->nBytesInM >= 4) {\n\t\tpmicdata->L ^= pmicdata->M;\n\t\tpmicdata->R ^= ROL32(pmicdata->L, 17);\n\t\tpmicdata->L += pmicdata->R;\n\t\tpmicdata->R ^= ((pmicdata->L & 0xff00ff00) >> 8) | ((pmicdata->L & 0x00ff00ff) << 8);\n\t\tpmicdata->L += pmicdata->R;\n\t\tpmicdata->R ^= ROL32(pmicdata->L, 3);\n\t\tpmicdata->L += pmicdata->R;\n\t\tpmicdata->R ^= ROR32(pmicdata->L, 2);\n\t\tpmicdata->L += pmicdata->R;\n\t\t/* Clear the buffer */\n\t\tpmicdata->M = 0;\n\t\tpmicdata->nBytesInM = 0;\n\t}\n}\n\nvoid rtw_secmicappend(struct mic_data *pmicdata, u8 *src, u32 nbytes)\n{\n\t/* This is simple */\n\twhile (nbytes > 0) {\n\t\trtw_secmicappendbyte(pmicdata, *src++);\n\t\tnbytes--;\n\t}\n}\n\nvoid rtw_secgetmic(struct mic_data *pmicdata, u8 *dst)\n{\n\t/* Append the minimum padding */\n\trtw_secmicappendbyte(pmicdata, 0x5a);\n\trtw_secmicappendbyte(pmicdata, 0);\n\trtw_secmicappendbyte(pmicdata, 0);\n\trtw_secmicappendbyte(pmicdata, 0);\n\trtw_secmicappendbyte(pmicdata, 0);\n\t/* and then zeroes until the length is a multiple of 4 */\n\twhile (pmicdata->nBytesInM != 0)\n\t\trtw_secmicappendbyte(pmicdata, 0);\n\t/* The appendByte function has already computed the result. */\n\tsecmicputuint32(dst, pmicdata->L);\n\tsecmicputuint32(dst + 4, pmicdata->R);\n\t/* Reset to the empty message. */\n\tsecmicclear(pmicdata);\n}\n\n\nvoid rtw_seccalctkipmic(u8 *key, u8 *header, u8 *data, u32 data_len, u8 *mic_code, u8 pri)\n{\n\n\tstruct mic_data\tmicdata;\n\tu8 priority[4] = {0x0, 0x0, 0x0, 0x0};\n\trtw_secmicsetkey(&micdata, key);\n\tpriority[0] = pri;\n\n\t/* Michael MIC pseudo header: DA, SA, 3 x 0, Priority */\n\tif (header[1] & 1) { /* ToDS==1 */\n\t\trtw_secmicappend(&micdata, &header[16], 6);  /* DA */\n\t\tif (header[1] & 2) /* From Ds==1 */\n\t\t\trtw_secmicappend(&micdata, &header[24], 6);\n\t\telse\n\t\t\trtw_secmicappend(&micdata, &header[10], 6);\n\t} else {\t/* ToDS==0 */\n\t\trtw_secmicappend(&micdata, &header[4], 6);   /* DA */\n\t\tif (header[1] & 2) /* From Ds==1 */\n\t\t\trtw_secmicappend(&micdata, &header[16], 6);\n\t\telse\n\t\t\trtw_secmicappend(&micdata, &header[10], 6);\n\n\t}\n\trtw_secmicappend(&micdata, &priority[0], 4);\n\n\n\trtw_secmicappend(&micdata, data, data_len);\n\n\trtw_secgetmic(&micdata, mic_code);\n}\n\n\n\n\n/* macros for extraction/creation of unsigned char/unsigned short values */\n#define RotR1(v16)   ((((v16) >> 1) & 0x7FFF) ^ (((v16) & 1) << 15))\n#define   Lo8(v16)   ((u8)((v16)       & 0x00FF))\n#define   Hi8(v16)   ((u8)(((v16) >> 8) & 0x00FF))\n#define  Lo16(v32)   ((u16)((v32)       & 0xFFFF))\n#define  Hi16(v32)   ((u16)(((v32) >> 16) & 0xFFFF))\n#define  Mk16(hi, lo) ((lo) ^ (((u16)(hi)) << 8))\n\n/* select the Nth 16-bit word of the temporal key unsigned char array TK[]  */\n#define  TK16(N)     Mk16(tk[2*(N)+1], tk[2*(N)])\n\n/* S-box lookup: 16 bits --> 16 bits */\n#define _S_(v16)     (Sbox1[0][Lo8(v16)] ^ Sbox1[1][Hi8(v16)])\n\n/* fixed algorithm \"parameters\" */\n#define PHASE1_LOOP_CNT   8    /* this needs to be \"big enough\"     */\n#define TA_SIZE           6    /*  48-bit transmitter address      */\n#define TK_SIZE          16    /* 128-bit temporal key             */\n#define P1K_SIZE         10    /*  80-bit Phase1 key               */\n#define RC4_KEY_SIZE     16    /* 128-bit RC4KEY (104 bits unknown) */\n\n\n/* 2-unsigned char by 2-unsigned char subset of the full AES S-box table */\nstatic const unsigned short Sbox1[2][256] =      /* Sbox for hash (can be in ROM)    */\n{ {\n\t\t0xC6A5, 0xF884, 0xEE99, 0xF68D, 0xFF0D, 0xD6BD, 0xDEB1, 0x9154,\n\t\t0x6050, 0x0203, 0xCEA9, 0x567D, 0xE719, 0xB562, 0x4DE6, 0xEC9A,\n\t\t0x8F45, 0x1F9D, 0x8940, 0xFA87, 0xEF15, 0xB2EB, 0x8EC9, 0xFB0B,\n\t\t0x41EC, 0xB367, 0x5FFD, 0x45EA, 0x23BF, 0x53F7, 0xE496, 0x9B5B,\n\t\t0x75C2, 0xE11C, 0x3DAE, 0x4C6A, 0x6C5A, 0x7E41, 0xF502, 0x834F,\n\t\t0x685C, 0x51F4, 0xD134, 0xF908, 0xE293, 0xAB73, 0x6253, 0x2A3F,\n\t\t0x080C, 0x9552, 0x4665, 0x9D5E, 0x3028, 0x37A1, 0x0A0F, 0x2FB5,\n\t\t0x0E09, 0x2436, 0x1B9B, 0xDF3D, 0xCD26, 0x4E69, 0x7FCD, 0xEA9F,\n\t\t0x121B, 0x1D9E, 0x5874, 0x342E, 0x362D, 0xDCB2, 0xB4EE, 0x5BFB,\n\t\t0xA4F6, 0x764D, 0xB761, 0x7DCE, 0x527B, 0xDD3E, 0x5E71, 0x1397,\n\t\t0xA6F5, 0xB968, 0x0000, 0xC12C, 0x4060, 0xE31F, 0x79C8, 0xB6ED,\n\t\t0xD4BE, 0x8D46, 0x67D9, 0x724B, 0x94DE, 0x98D4, 0xB0E8, 0x854A,\n\t\t0xBB6B, 0xC52A, 0x4FE5, 0xED16, 0x86C5, 0x9AD7, 0x6655, 0x1194,\n\t\t0x8ACF, 0xE910, 0x0406, 0xFE81, 0xA0F0, 0x7844, 0x25BA, 0x4BE3,\n\t\t0xA2F3, 0x5DFE, 0x80C0, 0x058A, 0x3FAD, 0x21BC, 0x7048, 0xF104,\n\t\t0x63DF, 0x77C1, 0xAF75, 0x4263, 0x2030, 0xE51A, 0xFD0E, 0xBF6D,\n\t\t0x814C, 0x1814, 0x2635, 0xC32F, 0xBEE1, 0x35A2, 0x88CC, 0x2E39,\n\t\t0x9357, 0x55F2, 0xFC82, 0x7A47, 0xC8AC, 0xBAE7, 0x322B, 0xE695,\n\t\t0xC0A0, 0x1998, 0x9ED1, 0xA37F, 0x4466, 0x547E, 0x3BAB, 0x0B83,\n\t\t0x8CCA, 0xC729, 0x6BD3, 0x283C, 0xA779, 0xBCE2, 0x161D, 0xAD76,\n\t\t0xDB3B, 0x6456, 0x744E, 0x141E, 0x92DB, 0x0C0A, 0x486C, 0xB8E4,\n\t\t0x9F5D, 0xBD6E, 0x43EF, 0xC4A6, 0x39A8, 0x31A4, 0xD337, 0xF28B,\n\t\t0xD532, 0x8B43, 0x6E59, 0xDAB7, 0x018C, 0xB164, 0x9CD2, 0x49E0,\n\t\t0xD8B4, 0xACFA, 0xF307, 0xCF25, 0xCAAF, 0xF48E, 0x47E9, 0x1018,\n\t\t0x6FD5, 0xF088, 0x4A6F, 0x5C72, 0x3824, 0x57F1, 0x73C7, 0x9751,\n\t\t0xCB23, 0xA17C, 0xE89C, 0x3E21, 0x96DD, 0x61DC, 0x0D86, 0x0F85,\n\t\t0xE090, 0x7C42, 0x71C4, 0xCCAA, 0x90D8, 0x0605, 0xF701, 0x1C12,\n\t\t0xC2A3, 0x6A5F, 0xAEF9, 0x69D0, 0x1791, 0x9958, 0x3A27, 0x27B9,\n\t\t0xD938, 0xEB13, 0x2BB3, 0x2233, 0xD2BB, 0xA970, 0x0789, 0x33A7,\n\t\t0x2DB6, 0x3C22, 0x1592, 0xC920, 0x8749, 0xAAFF, 0x5078, 0xA57A,\n\t\t0x038F, 0x59F8, 0x0980, 0x1A17, 0x65DA, 0xD731, 0x84C6, 0xD0B8,\n\t\t0x82C3, 0x29B0, 0x5A77, 0x1E11, 0x7BCB, 0xA8FC, 0x6DD6, 0x2C3A,\n\t},\n\n\n\t{  /* second half of table is unsigned char-reversed version of first! */\n\t\t0xA5C6, 0x84F8, 0x99EE, 0x8DF6, 0x0DFF, 0xBDD6, 0xB1DE, 0x5491,\n\t\t0x5060, 0x0302, 0xA9CE, 0x7D56, 0x19E7, 0x62B5, 0xE64D, 0x9AEC,\n\t\t0x458F, 0x9D1F, 0x4089, 0x87FA, 0x15EF, 0xEBB2, 0xC98E, 0x0BFB,\n\t\t0xEC41, 0x67B3, 0xFD5F, 0xEA45, 0xBF23, 0xF753, 0x96E4, 0x5B9B,\n\t\t0xC275, 0x1CE1, 0xAE3D, 0x6A4C, 0x5A6C, 0x417E, 0x02F5, 0x4F83,\n\t\t0x5C68, 0xF451, 0x34D1, 0x08F9, 0x93E2, 0x73AB, 0x5362, 0x3F2A,\n\t\t0x0C08, 0x5295, 0x6546, 0x5E9D, 0x2830, 0xA137, 0x0F0A, 0xB52F,\n\t\t0x090E, 0x3624, 0x9B1B, 0x3DDF, 0x26CD, 0x694E, 0xCD7F, 0x9FEA,\n\t\t0x1B12, 0x9E1D, 0x7458, 0x2E34, 0x2D36, 0xB2DC, 0xEEB4, 0xFB5B,\n\t\t0xF6A4, 0x4D76, 0x61B7, 0xCE7D, 0x7B52, 0x3EDD, 0x715E, 0x9713,\n\t\t0xF5A6, 0x68B9, 0x0000, 0x2CC1, 0x6040, 0x1FE3, 0xC879, 0xEDB6,\n\t\t0xBED4, 0x468D, 0xD967, 0x4B72, 0xDE94, 0xD498, 0xE8B0, 0x4A85,\n\t\t0x6BBB, 0x2AC5, 0xE54F, 0x16ED, 0xC586, 0xD79A, 0x5566, 0x9411,\n\t\t0xCF8A, 0x10E9, 0x0604, 0x81FE, 0xF0A0, 0x4478, 0xBA25, 0xE34B,\n\t\t0xF3A2, 0xFE5D, 0xC080, 0x8A05, 0xAD3F, 0xBC21, 0x4870, 0x04F1,\n\t\t0xDF63, 0xC177, 0x75AF, 0x6342, 0x3020, 0x1AE5, 0x0EFD, 0x6DBF,\n\t\t0x4C81, 0x1418, 0x3526, 0x2FC3, 0xE1BE, 0xA235, 0xCC88, 0x392E,\n\t\t0x5793, 0xF255, 0x82FC, 0x477A, 0xACC8, 0xE7BA, 0x2B32, 0x95E6,\n\t\t0xA0C0, 0x9819, 0xD19E, 0x7FA3, 0x6644, 0x7E54, 0xAB3B, 0x830B,\n\t\t0xCA8C, 0x29C7, 0xD36B, 0x3C28, 0x79A7, 0xE2BC, 0x1D16, 0x76AD,\n\t\t0x3BDB, 0x5664, 0x4E74, 0x1E14, 0xDB92, 0x0A0C, 0x6C48, 0xE4B8,\n\t\t0x5D9F, 0x6EBD, 0xEF43, 0xA6C4, 0xA839, 0xA431, 0x37D3, 0x8BF2,\n\t\t0x32D5, 0x438B, 0x596E, 0xB7DA, 0x8C01, 0x64B1, 0xD29C, 0xE049,\n\t\t0xB4D8, 0xFAAC, 0x07F3, 0x25CF, 0xAFCA, 0x8EF4, 0xE947, 0x1810,\n\t\t0xD56F, 0x88F0, 0x6F4A, 0x725C, 0x2438, 0xF157, 0xC773, 0x5197,\n\t\t0x23CB, 0x7CA1, 0x9CE8, 0x213E, 0xDD96, 0xDC61, 0x860D, 0x850F,\n\t\t0x90E0, 0x427C, 0xC471, 0xAACC, 0xD890, 0x0506, 0x01F7, 0x121C,\n\t\t0xA3C2, 0x5F6A, 0xF9AE, 0xD069, 0x9117, 0x5899, 0x273A, 0xB927,\n\t\t0x38D9, 0x13EB, 0xB32B, 0x3322, 0xBBD2, 0x70A9, 0x8907, 0xA733,\n\t\t0xB62D, 0x223C, 0x9215, 0x20C9, 0x4987, 0xFFAA, 0x7850, 0x7AA5,\n\t\t0x8F03, 0xF859, 0x8009, 0x171A, 0xDA65, 0x31D7, 0xC684, 0xB8D0,\n\t\t0xC382, 0xB029, 0x775A, 0x111E, 0xCB7B, 0xFCA8, 0xD66D, 0x3A2C,\n\t}\n};\n\n/*\n**********************************************************************\n* Routine: Phase 1 -- generate P1K, given TA, TK, IV32\n*\n* Inputs:\n*     tk[]      = temporal key                         [128 bits]\n*     ta[]      = transmitter's MAC address            [ 48 bits]\n*     iv32      = upper 32 bits of IV                  [ 32 bits]\n* Output:\n*     p1k[]     = Phase 1 key                          [ 80 bits]\n*\n* Note:\n*     This function only needs to be called every 2**16 packets,\n*     although in theory it could be called every packet.\n*\n**********************************************************************\n*/\nstatic void phase1(u16 *p1k, const u8 *tk, const u8 *ta, u32 iv32)\n{\n\tsint  i;\n\t/* Initialize the 80 bits of P1K[] from IV32 and TA[0..5]    */\n\tp1k[0]      = Lo16(iv32);\n\tp1k[1]      = Hi16(iv32);\n\tp1k[2]      = Mk16(ta[1], ta[0]); /* use TA[] as little-endian */\n\tp1k[3]      = Mk16(ta[3], ta[2]);\n\tp1k[4]      = Mk16(ta[5], ta[4]);\n\n\t/* Now compute an unbalanced Feistel cipher with 80-bit block */\n\t/* size on the 80-bit block P1K[], using the 128-bit key TK[] */\n\tfor (i = 0; i < PHASE1_LOOP_CNT ; i++) {\n\t\t/* Each add operation here is mod 2**16 */\n\t\tp1k[0] += _S_(p1k[4] ^ TK16((i & 1) + 0));\n\t\tp1k[1] += _S_(p1k[0] ^ TK16((i & 1) + 2));\n\t\tp1k[2] += _S_(p1k[1] ^ TK16((i & 1) + 4));\n\t\tp1k[3] += _S_(p1k[2] ^ TK16((i & 1) + 6));\n\t\tp1k[4] += _S_(p1k[3] ^ TK16((i & 1) + 0));\n\t\tp1k[4] += (unsigned short)i;                     /* avoid \"slide attacks\" */\n\t}\n}\n\n\n/*\n**********************************************************************\n* Routine: Phase 2 -- generate RC4KEY, given TK, P1K, IV16\n*\n* Inputs:\n*     tk[]      = Temporal key                         [128 bits]\n*     p1k[]     = Phase 1 output key                   [ 80 bits]\n*     iv16      = low 16 bits of IV counter            [ 16 bits]\n* Output:\n*     rc4key[]  = the key used to encrypt the packet   [128 bits]\n*\n* Note:\n*     The value {TA,IV32,IV16} for Phase1/Phase2 must be unique\n*     across all packets using the same key TK value. Then, for a\n*     given value of TK[], this TKIP48 construction guarantees that\n*     the final RC4KEY value is unique across all packets.\n*\n* Suggested implementation optimization: if PPK[] is \"overlaid\"\n*     appropriately on RC4KEY[], there is no need for the final\n*     for loop below that copies the PPK[] result into RC4KEY[].\n*\n**********************************************************************\n*/\nstatic void phase2(u8 *rc4key, const u8 *tk, const u16 *p1k, u16 iv16)\n{\n\tsint  i;\n\tu16 PPK[6];                          /* temporary key for mixing   */\n\t/* Note: all adds in the PPK[] equations below are mod 2**16        */\n\tfor (i = 0; i < 5; i++)\n\t\tPPK[i] = p1k[i];    /* first, copy P1K to PPK     */\n\tPPK[5]  =  p1k[4] + iv16;            /* next,  add in IV16         */\n\n\t/* Bijective non-linear mixing of the 96 bits of PPK[0..5]          */\n\tPPK[0] +=    _S_(PPK[5] ^ TK16(0));   /* Mix key in each \"round\"     */\n\tPPK[1] +=    _S_(PPK[0] ^ TK16(1));\n\tPPK[2] +=    _S_(PPK[1] ^ TK16(2));\n\tPPK[3] +=    _S_(PPK[2] ^ TK16(3));\n\tPPK[4] +=    _S_(PPK[3] ^ TK16(4));\n\tPPK[5] +=    _S_(PPK[4] ^ TK16(5));   /* Total # S-box lookups == 6 */\n\n\t/* Final sweep: bijective, \"linear\". Rotates kill LSB correlations   */\n\tPPK[0] +=  RotR1(PPK[5] ^ TK16(6));\n\tPPK[1] +=  RotR1(PPK[0] ^ TK16(7));   /* Use all of TK[] in Phase2  */\n\tPPK[2] +=  RotR1(PPK[1]);\n\tPPK[3] +=  RotR1(PPK[2]);\n\tPPK[4] +=  RotR1(PPK[3]);\n\tPPK[5] +=  RotR1(PPK[4]);\n\t/* Note: At this point, for a given key TK[0..15], the 96-bit output */\n\t/*       value PPK[0..5] is guaranteed to be unique, as a function  */\n\t/*       of the 96-bit \"input\" value   {TA,IV32,IV16}. That is, P1K  */\n\t/*       is now a keyed permutation of {TA,IV32,IV16}.              */\n\n\t/* Set RC4KEY[0..3], which includes \"cleartext\" portion of RC4 key   */\n\trc4key[0] = Hi8(iv16);                /* RC4KEY[0..2] is the WEP IV */\n\trc4key[1] = (Hi8(iv16) | 0x20) & 0x7F; /* Help avoid weak (FMS) keys */\n\trc4key[2] = Lo8(iv16);\n\trc4key[3] = Lo8((PPK[5] ^ TK16(0)) >> 1);\n\n\n\t/* Copy 96 bits of PPK[0..5] to RC4KEY[4..15]  (little-endian)      */\n\tfor (i = 0; i < 6; i++) {\n\t\trc4key[4 + 2 * i] = Lo8(PPK[i]);\n\t\trc4key[5 + 2 * i] = Hi8(PPK[i]);\n\t}\n}\n\n\n/* The hlen isn't include the IV */\nu32\trtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe)\n{\n\t/* exclude ICV */\n\tu16\tpnl;\n\tu32\tpnh;\n\tu8\trc4key[16];\n\tu8   ttkey[16];\n\tu8\tcrc[4];\n\tu8   hw_hdr_offset = 0;\n\tstruct arc4context mycontext;\n\tsint\t\t\tcurfragnum, length;\n\tu32\tprwskeylen;\n\n\tu8\t*pframe, *payload, *iv, *prwskey;\n\tunion pn48 dot11txpn;\n\t/* struct\tsta_info\t\t*stainfo; */\n\tstruct\tpkt_attrib\t*pattrib = &((struct xmit_frame *)pxmitframe)->attrib;\n\tstruct\tsecurity_priv\t*psecuritypriv = &padapter->securitypriv;\n\tstruct\txmit_priv\t\t*pxmitpriv = &padapter->xmitpriv;\n\tu32\tres = _SUCCESS;\n\n\tif (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)\n\t\treturn _FAIL;\n\n#ifdef CONFIG_USB_TX_AGGREGATION\n\thw_hdr_offset = TXDESC_SIZE +\n\t\t(((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);\n#else\n#ifdef CONFIG_TX_EARLY_MODE\n\thw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;\n#else\n\thw_hdr_offset = TXDESC_OFFSET;\n#endif\n#endif\n\n\tpframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset;\n\t/* 4 start to encrypt each fragment */\n\tif (pattrib->encrypt == _TKIP_) {\n\n\t\t/*\n\t\t\t\tif(pattrib->psta)\n\t\t\t\t{\n\t\t\t\t\tstainfo = pattrib->psta;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tRTW_INFO(\"%s, call rtw_get_stainfo()\\n\", __func__);\n\t\t\t\t\tstainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] );\n\t\t\t\t}\n\t\t*/\n\t\t/* if (stainfo!=NULL) */\n\t\t{\n\t\t\t/*\n\t\t\t\t\t\tif(!(stainfo->state &_FW_LINKED))\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tRTW_INFO(\"%s, psta->state(0x%x) != _FW_LINKED\\n\", __func__, stainfo->state);\n\t\t\t\t\t\t\treturn _FAIL;\n\t\t\t\t\t\t}\n\t\t\t*/\n\n\t\t\tif (IS_MCAST(pattrib->ra))\n\t\t\t\tprwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;\n\t\t\telse {\n\t\t\t\t/* prwskey=&stainfo->dot118021x_UncstKey.skey[0]; */\n\t\t\t\tprwskey = pattrib->dot118021x_UncstKey.skey;\n\t\t\t}\n\n\t\t\tprwskeylen = 16;\n\n\t\t\tfor (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {\n\t\t\t\tiv = pframe + pattrib->hdrlen;\n\t\t\t\tpayload = pframe + pattrib->iv_len + pattrib->hdrlen;\n\n\t\t\t\tGET_TKIP_PN(iv, dot11txpn);\n\n\t\t\t\tpnl = (u16)(dot11txpn.val);\n\t\t\t\tpnh = (u32)(dot11txpn.val >> 16);\n\n\t\t\t\tphase1((u16 *)&ttkey[0], prwskey, &pattrib->ta[0], pnh);\n\n\t\t\t\tphase2(&rc4key[0], prwskey, (u16 *)&ttkey[0], pnl);\n\n\t\t\t\tif ((curfragnum + 1) == pattrib->nr_frags) {\t/* 4 the last fragment */\n\t\t\t\t\tlength = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;\n\t\t\t\t\t*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); /* modified by Amy*/\n\n\t\t\t\t\tarcfour_init(&mycontext, rc4key, 16);\n\t\t\t\t\tarcfour_encrypt(&mycontext, payload, payload, length);\n\t\t\t\t\tarcfour_encrypt(&mycontext, payload + length, crc, 4);\n\n\t\t\t\t} else {\n\t\t\t\t\tlength = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ;\n\t\t\t\t\t*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); /* modified by Amy*/\n\t\t\t\t\tarcfour_init(&mycontext, rc4key, 16);\n\t\t\t\t\tarcfour_encrypt(&mycontext, payload, payload, length);\n\t\t\t\t\tarcfour_encrypt(&mycontext, payload + length, crc, 4);\n\n\t\t\t\t\tpframe += pxmitpriv->frag_len;\n\t\t\t\t\tpframe = (u8 *)RND4((SIZE_PTR)(pframe));\n\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tTKIP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra);\n\t\t}\n\t\t/*\n\t\t\t\telse{\n\t\t\t\t\tRTW_INFO(\"%s, psta==NUL\\n\", __func__);\n\t\t\t\t\tres=_FAIL;\n\t\t\t\t}\n\t\t*/\n\n\t}\n\treturn res;\n\n}\n\n\n/* The hlen isn't include the IV */\nu32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe)\n{\n\t/* exclude ICV */\n\tu16 pnl;\n\tu32 pnh;\n\tu8   rc4key[16];\n\tu8   ttkey[16];\n\tu8\tcrc[4];\n\tstruct arc4context mycontext;\n\tsint\t\t\tlength;\n\tu32\tprwskeylen;\n\n\tu8\t*pframe, *payload, *iv, *prwskey;\n\tunion pn48 dot11txpn;\n\tstruct\tsta_info\t\t*stainfo;\n\tstruct\trx_pkt_attrib\t*prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;\n\tstruct\tsecurity_priv\t*psecuritypriv = &padapter->securitypriv;\n\t/*\tstruct\trecv_priv\t\t*precvpriv=&padapter->recvpriv; */\n\tu32\t\tres = _SUCCESS;\n\n\n\tpframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;\n\n\t/* 4 start to decrypt recvframe */\n\tif (prxattrib->encrypt == _TKIP_) {\n\n\t\tstainfo = rtw_get_stainfo(&padapter->stapriv , &prxattrib->ta[0]);\n\t\tif (stainfo != NULL) {\n\n\t\t\tif (IS_MCAST(prxattrib->ra)) {\n\t\t\t\tstatic systime start = 0;\n\t\t\t\tstatic u32 no_gkey_bc_cnt = 0;\n\t\t\t\tstatic u32 no_gkey_mc_cnt = 0;\n\n\t\t\t\tif (psecuritypriv->binstallGrpkey == _FALSE) {\n\t\t\t\t\tres = _FAIL;\n\n\t\t\t\t\tif (start == 0)\n\t\t\t\t\t\tstart = rtw_get_current_time();\n\n\t\t\t\t\tif (is_broadcast_mac_addr(prxattrib->ra))\n\t\t\t\t\t\tno_gkey_bc_cnt++;\n\t\t\t\t\telse\n\t\t\t\t\t\tno_gkey_mc_cnt++;\n\n\t\t\t\t\tif (rtw_get_passing_time_ms(start) > 1000) {\n\t\t\t\t\t\tif (no_gkey_bc_cnt || no_gkey_mc_cnt) {\n\t\t\t\t\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\\n\",\n\t\t\t\t\t\t\t\tFUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);\n\t\t\t\t\t\t}\n\t\t\t\t\t\tstart = rtw_get_current_time();\n\t\t\t\t\t\tno_gkey_bc_cnt = 0;\n\t\t\t\t\t\tno_gkey_mc_cnt = 0;\n\t\t\t\t\t}\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\n\t\t\t\tif (no_gkey_bc_cnt || no_gkey_mc_cnt) {\n\t\t\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\\n\",\n\t\t\t\t\t\tFUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);\n\t\t\t\t}\n\t\t\t\tstart = 0;\n\t\t\t\tno_gkey_bc_cnt = 0;\n\t\t\t\tno_gkey_mc_cnt = 0;\n\n\t\t\t\t/* RTW_INFO(\"rx bc/mc packets, to perform sw rtw_tkip_decrypt\\n\"); */\n\t\t\t\t/* prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; */\n\t\t\t\tprwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey;\n\t\t\t\tprwskeylen = 16;\n\t\t\t} else {\n\t\t\t\tprwskey = &stainfo->dot118021x_UncstKey.skey[0];\n\t\t\t\tprwskeylen = 16;\n\t\t\t}\n\n\t\t\tiv = pframe + prxattrib->hdrlen;\n\t\t\tpayload = pframe + prxattrib->iv_len + prxattrib->hdrlen;\n\t\t\tlength = ((union recv_frame *)precvframe)->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len;\n\n\t\t\tGET_TKIP_PN(iv, dot11txpn);\n\n\t\t\tpnl = (u16)(dot11txpn.val);\n\t\t\tpnh = (u32)(dot11txpn.val >> 16);\n\n\t\t\tphase1((u16 *)&ttkey[0], prwskey, &prxattrib->ta[0], pnh);\n\t\t\tphase2(&rc4key[0], prwskey, (unsigned short *)&ttkey[0], pnl);\n\n\t\t\t/* 4 decrypt payload include icv */\n\n\t\t\tarcfour_init(&mycontext, rc4key, 16);\n\t\t\tarcfour_encrypt(&mycontext, payload, payload, length);\n\n\t\t\t*((u32 *)crc) = le32_to_cpu(getcrc32(payload, length - 4));\n\n\t\t\tif (crc[3] != payload[length - 1] || crc[2] != payload[length - 2] || crc[1] != payload[length - 3] || crc[0] != payload[length - 4]) {\n\t\t\t\tres = _FAIL;\n\t\t\t}\n\n\t\t\tTKIP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);\n\t\t} else {\n\t\t\tres = _FAIL;\n\t\t}\n\n\t}\nexit:\n\treturn res;\n\n}\n\n\n/* 3\t\t\t=====AES related===== */\n\n\n\n#define MAX_MSG_SIZE\t2048\n/*****************************/\n/******** SBOX Table *********/\n/*****************************/\n\nstatic  u8 sbox_table[256] = {\n\t0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5,\n\t0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,\n\t0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0,\n\t0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,\n\t0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc,\n\t0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,\n\t0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a,\n\t0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,\n\t0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0,\n\t0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,\n\t0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b,\n\t0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,\n\t0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85,\n\t0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,\n\t0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5,\n\t0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,\n\t0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17,\n\t0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,\n\t0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88,\n\t0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,\n\t0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c,\n\t0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,\n\t0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9,\n\t0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,\n\t0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6,\n\t0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,\n\t0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e,\n\t0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,\n\t0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94,\n\t0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,\n\t0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68,\n\t0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16\n};\n\n/*****************************/\n/**** Function Prototypes ****/\n/*****************************/\n\nstatic void bitwise_xor(u8 *ina, u8 *inb, u8 *out);\nstatic void construct_mic_iv(\n\tu8 *mic_header1,\n\tsint qc_exists,\n\tsint a4_exists,\n\tu8 *mpdu,\n\tuint payload_length,\n\tu8 *pn_vector,\n\tuint frtype);/* add for CONFIG_IEEE80211W, none 11w also can use */\nstatic void construct_mic_header1(\n\tu8 *mic_header1,\n\tsint header_length,\n\tu8 *mpdu,\n\tuint frtype);/* add for CONFIG_IEEE80211W, none 11w also can use */\nstatic void construct_mic_header2(\n\tu8 *mic_header2,\n\tu8 *mpdu,\n\tsint a4_exists,\n\tsint qc_exists);\nstatic void construct_ctr_preload(\n\tu8 *ctr_preload,\n\tsint a4_exists,\n\tsint qc_exists,\n\tu8 *mpdu,\n\tu8 *pn_vector,\n\tsint c,\n\tuint frtype);/* add for CONFIG_IEEE80211W, none 11w also can use */\nstatic void xor_128(u8 *a, u8 *b, u8 *out);\nstatic void xor_32(u8 *a, u8 *b, u8 *out);\nstatic u8 sbox(u8 a);\nstatic void next_key(u8 *key, sint round);\nstatic void byte_sub(u8 *in, u8 *out);\nstatic void shift_row(u8 *in, u8 *out);\nstatic void mix_column(u8 *in, u8 *out);\nstatic void aes128k128d(u8 *key, u8 *data, u8 *ciphertext);\n\n\n/****************************************/\n/* aes128k128d()                       */\n/* Performs a 128 bit AES encrypt with */\n/* 128 bit data.                       */\n/****************************************/\nstatic void xor_128(u8 *a, u8 *b, u8 *out)\n{\n\tsint i;\n\tfor (i = 0; i < 16; i++)\n\t\tout[i] = a[i] ^ b[i];\n}\n\n\nstatic void xor_32(u8 *a, u8 *b, u8 *out)\n{\n\tsint i;\n\tfor (i = 0; i < 4; i++)\n\t\tout[i] = a[i] ^ b[i];\n}\n\n\nstatic u8 sbox(u8 a)\n{\n\treturn sbox_table[(sint)a];\n}\n\n\nstatic void next_key(u8 *key, sint round)\n{\n\tu8 rcon;\n\tu8 sbox_key[4];\n\tu8 rcon_table[12] = {\n\t\t0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80,\n\t\t0x1b, 0x36, 0x36, 0x36\n\t};\n\tsbox_key[0] = sbox(key[13]);\n\tsbox_key[1] = sbox(key[14]);\n\tsbox_key[2] = sbox(key[15]);\n\tsbox_key[3] = sbox(key[12]);\n\n\trcon = rcon_table[round];\n\n\txor_32(&key[0], sbox_key, &key[0]);\n\tkey[0] = key[0] ^ rcon;\n\n\txor_32(&key[4], &key[0], &key[4]);\n\txor_32(&key[8], &key[4], &key[8]);\n\txor_32(&key[12], &key[8], &key[12]);\n}\n\n\nstatic void byte_sub(u8 *in, u8 *out)\n{\n\tsint i;\n\tfor (i = 0; i < 16; i++)\n\t\tout[i] = sbox(in[i]);\n}\n\n\nstatic void shift_row(u8 *in, u8 *out)\n{\n\tout[0] =  in[0];\n\tout[1] =  in[5];\n\tout[2] =  in[10];\n\tout[3] =  in[15];\n\tout[4] =  in[4];\n\tout[5] =  in[9];\n\tout[6] =  in[14];\n\tout[7] =  in[3];\n\tout[8] =  in[8];\n\tout[9] =  in[13];\n\tout[10] = in[2];\n\tout[11] = in[7];\n\tout[12] = in[12];\n\tout[13] = in[1];\n\tout[14] = in[6];\n\tout[15] = in[11];\n}\n\n\nstatic void mix_column(u8 *in, u8 *out)\n{\n\tsint i;\n\tu8 add1b[4];\n\tu8 add1bf7[4];\n\tu8 rotl[4];\n\tu8 swap_halfs[4];\n\tu8 andf7[4];\n\tu8 rotr[4];\n\tu8 temp[4];\n\tu8 tempb[4];\n\tfor (i = 0 ; i < 4; i++) {\n\t\tif ((in[i] & 0x80) == 0x80)\n\t\t\tadd1b[i] = 0x1b;\n\t\telse\n\t\t\tadd1b[i] = 0x00;\n\t}\n\n\tswap_halfs[0] = in[2];    /* Swap halfs */\n\tswap_halfs[1] = in[3];\n\tswap_halfs[2] = in[0];\n\tswap_halfs[3] = in[1];\n\n\trotl[0] = in[3];        /* Rotate left 8 bits */\n\trotl[1] = in[0];\n\trotl[2] = in[1];\n\trotl[3] = in[2];\n\n\tandf7[0] = in[0] & 0x7f;\n\tandf7[1] = in[1] & 0x7f;\n\tandf7[2] = in[2] & 0x7f;\n\tandf7[3] = in[3] & 0x7f;\n\n\tfor (i = 3; i > 0; i--) { /* logical shift left 1 bit */\n\t\tandf7[i] = andf7[i] << 1;\n\t\tif ((andf7[i - 1] & 0x80) == 0x80)\n\t\t\tandf7[i] = (andf7[i] | 0x01);\n\t}\n\tandf7[0] = andf7[0] << 1;\n\tandf7[0] = andf7[0] & 0xfe;\n\n\txor_32(add1b, andf7, add1bf7);\n\n\txor_32(in, add1bf7, rotr);\n\n\ttemp[0] = rotr[0];         /* Rotate right 8 bits */\n\trotr[0] = rotr[1];\n\trotr[1] = rotr[2];\n\trotr[2] = rotr[3];\n\trotr[3] = temp[0];\n\n\txor_32(add1bf7, rotr, temp);\n\txor_32(swap_halfs, rotl, tempb);\n\txor_32(temp, tempb, out);\n}\n\n\nstatic void aes128k128d(u8 *key, u8 *data, u8 *ciphertext)\n{\n\tsint round;\n\tsint i;\n\tu8 intermediatea[16];\n\tu8 intermediateb[16];\n\tu8 round_key[16];\n\tfor (i = 0; i < 16; i++)\n\t\tround_key[i] = key[i];\n\n\tfor (round = 0; round < 11; round++) {\n\t\tif (round == 0) {\n\t\t\txor_128(round_key, data, ciphertext);\n\t\t\tnext_key(round_key, round);\n\t\t} else if (round == 10) {\n\t\t\tbyte_sub(ciphertext, intermediatea);\n\t\t\tshift_row(intermediatea, intermediateb);\n\t\t\txor_128(intermediateb, round_key, ciphertext);\n\t\t} else { /* 1 - 9 */\n\t\t\tbyte_sub(ciphertext, intermediatea);\n\t\t\tshift_row(intermediatea, intermediateb);\n\t\t\tmix_column(&intermediateb[0], &intermediatea[0]);\n\t\t\tmix_column(&intermediateb[4], &intermediatea[4]);\n\t\t\tmix_column(&intermediateb[8], &intermediatea[8]);\n\t\t\tmix_column(&intermediateb[12], &intermediatea[12]);\n\t\t\txor_128(intermediatea, round_key, ciphertext);\n\t\t\tnext_key(round_key, round);\n\t\t}\n\t}\n}\n\n\n/************************************************/\n/* construct_mic_iv()                          */\n/* Builds the MIC IV from header fields and PN */\n/* Baron think the function is construct CCM   */\n/* nonce                                       */\n/************************************************/\nstatic void construct_mic_iv(\n\tu8 *mic_iv,\n\tsint qc_exists,\n\tsint a4_exists,\n\tu8 *mpdu,\n\tuint payload_length,\n\tu8 *pn_vector,\n\tuint frtype/* add for CONFIG_IEEE80211W, none 11w also can use */\n)\n{\n\tsint i;\n\tmic_iv[0] = 0x59;\n\tif (qc_exists && a4_exists)\n\t\tmic_iv[1] = mpdu[30] & 0x0f;    /* QoS_TC          */\n\tif (qc_exists && !a4_exists)\n\t\tmic_iv[1] = mpdu[24] & 0x0f;   /* mute bits 7-4   */\n\tif (!qc_exists)\n\t\tmic_iv[1] = 0x00;\n#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)\n\t/* 802.11w management frame should set management bit(4) */\n\tif (frtype == WIFI_MGT_TYPE)\n\t\tmic_iv[1] |= BIT(4);\n#endif\n\tfor (i = 2; i < 8; i++)\n\t\tmic_iv[i] = mpdu[i + 8];                    /* mic_iv[2:7] = A2[0:5] = mpdu[10:15] */\n#ifdef CONSISTENT_PN_ORDER\n\tfor (i = 8; i < 14; i++)\n\t\tmic_iv[i] = pn_vector[i - 8];           /* mic_iv[8:13] = PN[0:5] */\n#else\n\tfor (i = 8; i < 14; i++)\n\t\tmic_iv[i] = pn_vector[13 - i];          /* mic_iv[8:13] = PN[5:0] */\n#endif\n\tmic_iv[14] = (unsigned char)(payload_length / 256);\n\tmic_iv[15] = (unsigned char)(payload_length % 256);\n}\n\n\n/************************************************/\n/* construct_mic_header1()                     */\n/* Builds the first MIC header block from      */\n/* header fields.                              */\n/* Build AAD SC,A1,A2                          */\n/************************************************/\nstatic void construct_mic_header1(\n\tu8 *mic_header1,\n\tsint header_length,\n\tu8 *mpdu,\n\tuint frtype/* add for CONFIG_IEEE80211W, none 11w also can use */\n)\n{\n\tmic_header1[0] = (u8)((header_length - 2) / 256);\n\tmic_header1[1] = (u8)((header_length - 2) % 256);\n#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)\n\t/* 802.11w management frame don't AND subtype bits 4,5,6 of frame control field */\n\tif (frtype == WIFI_MGT_TYPE)\n\t\tmic_header1[2] = mpdu[0];\n\telse\n#endif\n\t\tmic_header1[2] = mpdu[0] & 0xcf;    /* Mute CF poll & CF ack bits */\n\n\tmic_header1[3] = mpdu[1] & 0xc7;    /* Mute retry, more data and pwr mgt bits */\n\tmic_header1[4] = mpdu[4];       /* A1 */\n\tmic_header1[5] = mpdu[5];\n\tmic_header1[6] = mpdu[6];\n\tmic_header1[7] = mpdu[7];\n\tmic_header1[8] = mpdu[8];\n\tmic_header1[9] = mpdu[9];\n\tmic_header1[10] = mpdu[10];     /* A2 */\n\tmic_header1[11] = mpdu[11];\n\tmic_header1[12] = mpdu[12];\n\tmic_header1[13] = mpdu[13];\n\tmic_header1[14] = mpdu[14];\n\tmic_header1[15] = mpdu[15];\n}\n\n\n/************************************************/\n/* construct_mic_header2()                     */\n/* Builds the last MIC header block from       */\n/* header fields.                              */\n/************************************************/\nstatic void construct_mic_header2(\n\tu8 *mic_header2,\n\tu8 *mpdu,\n\tsint a4_exists,\n\tsint qc_exists\n)\n{\n\tsint i;\n\tfor (i = 0; i < 16; i++)\n\t\tmic_header2[i] = 0x00;\n\n\tmic_header2[0] = mpdu[16];    /* A3 */\n\tmic_header2[1] = mpdu[17];\n\tmic_header2[2] = mpdu[18];\n\tmic_header2[3] = mpdu[19];\n\tmic_header2[4] = mpdu[20];\n\tmic_header2[5] = mpdu[21];\n\n\t/* mic_header2[6] = mpdu[22] & 0xf0;    SC */\n\tmic_header2[6] = 0x00;\n\tmic_header2[7] = 0x00; /* mpdu[23]; */\n\n\n\tif (!qc_exists && a4_exists) {\n\t\tfor (i = 0; i < 6; i++)\n\t\t\tmic_header2[8 + i] = mpdu[24 + i]; /* A4 */\n\n\t}\n\n\tif (qc_exists && !a4_exists) {\n\t\tmic_header2[8] = mpdu[24] & 0x0f; /* mute bits 15 - 4 */\n\t\tmic_header2[9] = mpdu[25] & 0x00;\n\t}\n\n\tif (qc_exists && a4_exists) {\n\t\tfor (i = 0; i < 6; i++)\n\t\t\tmic_header2[8 + i] = mpdu[24 + i]; /* A4 */\n\n\t\tmic_header2[14] = mpdu[30] & 0x0f;\n\t\tmic_header2[15] = mpdu[31] & 0x00;\n\t}\n\n}\n\n\n/************************************************/\n/* construct_mic_header2()                     */\n/* Builds the last MIC header block from       */\n/* header fields.                              */\n/* Baron think the function is construct CCM   */\n/* nonce                                       */\n/************************************************/\nstatic void construct_ctr_preload(\n\tu8 *ctr_preload,\n\tsint a4_exists,\n\tsint qc_exists,\n\tu8 *mpdu,\n\tu8 *pn_vector,\n\tsint c,\n\tuint frtype /* add for CONFIG_IEEE80211W, none 11w also can use */\n)\n{\n\tsint i = 0;\n\tfor (i = 0; i < 16; i++)\n\t\tctr_preload[i] = 0x00;\n\ti = 0;\n\n\tctr_preload[0] = 0x01;                                  /* flag */\n\tif (qc_exists && a4_exists)\n\t\tctr_preload[1] = mpdu[30] & 0x0f;   /* QoC_Control */\n\tif (qc_exists && !a4_exists)\n\t\tctr_preload[1] = mpdu[24] & 0x0f;\n#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)\n\t/* 802.11w management frame should set management bit(4) */\n\tif (frtype == WIFI_MGT_TYPE)\n\t\tctr_preload[1] |= BIT(4);\n#endif\n\tfor (i = 2; i < 8; i++)\n\t\tctr_preload[i] = mpdu[i + 8];                       /* ctr_preload[2:7] = A2[0:5] = mpdu[10:15] */\n#ifdef CONSISTENT_PN_ORDER\n\tfor (i = 8; i < 14; i++)\n\t\tctr_preload[i] =    pn_vector[i - 8];           /* ctr_preload[8:13] = PN[0:5] */\n#else\n\tfor (i = 8; i < 14; i++)\n\t\tctr_preload[i] =    pn_vector[13 - i];          /* ctr_preload[8:13] = PN[5:0] */\n#endif\n\tctr_preload[14] = (unsigned char)(c / 256);   /* Ctr */\n\tctr_preload[15] = (unsigned char)(c % 256);\n}\n\n\n/************************************/\n/* bitwise_xor()                   */\n/* A 128 bit, bitwise exclusive or */\n/************************************/\nstatic void bitwise_xor(u8 *ina, u8 *inb, u8 *out)\n{\n\tsint i;\n\tfor (i = 0; i < 16; i++)\n\t\tout[i] = ina[i] ^ inb[i];\n}\n\n\nstatic sint aes_cipher(u8 *key, uint\thdrlen,\n\t\t       u8 *pframe, uint plen)\n{\n\t/*\tstatic unsigned char\tmessage[MAX_MSG_SIZE]; */\n\tuint\tqc_exists, a4_exists, i, j, payload_remainder,\n\t\tnum_blocks, payload_index;\n\n\tu8 pn_vector[6];\n\tu8 mic_iv[16];\n\tu8 mic_header1[16];\n\tu8 mic_header2[16];\n\tu8 ctr_preload[16];\n\n\t/* Intermediate Buffers */\n\tu8 chain_buffer[16];\n\tu8 aes_out[16];\n\tu8 padded_buffer[16];\n\tu8 mic[8];\n\t/*\tuint\toffset = 0; */\n\tuint\tfrtype  = GetFrameType(pframe);\n\tuint\tfrsubtype  = get_frame_sub_type(pframe);\n\n\tfrsubtype = frsubtype >> 4;\n\n\n\t_rtw_memset((void *)mic_iv, 0, 16);\n\t_rtw_memset((void *)mic_header1, 0, 16);\n\t_rtw_memset((void *)mic_header2, 0, 16);\n\t_rtw_memset((void *)ctr_preload, 0, 16);\n\t_rtw_memset((void *)chain_buffer, 0, 16);\n\t_rtw_memset((void *)aes_out, 0, 16);\n\t_rtw_memset((void *)padded_buffer, 0, 16);\n\n\tif ((hdrlen == WLAN_HDR_A3_LEN) || (hdrlen ==  WLAN_HDR_A3_QOS_LEN))\n\t\ta4_exists = 0;\n\telse\n\t\ta4_exists = 1;\n\n\tif (\n\t\t((frtype | frsubtype) == WIFI_DATA_CFACK) ||\n\t\t((frtype | frsubtype) == WIFI_DATA_CFPOLL) ||\n\t\t((frtype | frsubtype) == WIFI_DATA_CFACKPOLL)) {\n\t\tqc_exists = 1;\n\t\tif (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)\n\t\t\thdrlen += 2;\n\t}\n\t/* add for CONFIG_IEEE80211W, none 11w also can use */\n\telse if ((frtype == WIFI_DATA) &&\n\t\t ((frsubtype == 0x08) ||\n\t\t  (frsubtype == 0x09) ||\n\t\t  (frsubtype == 0x0a) ||\n\t\t  (frsubtype == 0x0b))) {\n\t\tif (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)\n\t\t\thdrlen += 2;\n\t\tqc_exists = 1;\n\t} else\n\t\tqc_exists = 0;\n\n\tpn_vector[0] = pframe[hdrlen];\n\tpn_vector[1] = pframe[hdrlen + 1];\n\tpn_vector[2] = pframe[hdrlen + 4];\n\tpn_vector[3] = pframe[hdrlen + 5];\n\tpn_vector[4] = pframe[hdrlen + 6];\n\tpn_vector[5] = pframe[hdrlen + 7];\n\n\tconstruct_mic_iv(\n\t\tmic_iv,\n\t\tqc_exists,\n\t\ta4_exists,\n\t\tpframe,\t /* message, */\n\t\tplen,\n\t\tpn_vector,\n\t\tfrtype /* add for CONFIG_IEEE80211W, none 11w also can use */\n\t);\n\n\tconstruct_mic_header1(\n\t\tmic_header1,\n\t\thdrlen,\n\t\tpframe,\t/* message */\n\t\tfrtype /* add for CONFIG_IEEE80211W, none 11w also can use */\n\t);\n\tconstruct_mic_header2(\n\t\tmic_header2,\n\t\tpframe,\t/* message, */\n\t\ta4_exists,\n\t\tqc_exists\n\t);\n\n\n\tpayload_remainder = plen % 16;\n\tnum_blocks = plen / 16;\n\n\t/* Find start of payload */\n\tpayload_index = (hdrlen + 8);\n\n\t/* Calculate MIC */\n\taes128k128d(key, mic_iv, aes_out);\n\tbitwise_xor(aes_out, mic_header1, chain_buffer);\n\taes128k128d(key, chain_buffer, aes_out);\n\tbitwise_xor(aes_out, mic_header2, chain_buffer);\n\taes128k128d(key, chain_buffer, aes_out);\n\n\tfor (i = 0; i < num_blocks; i++) {\n\t\tbitwise_xor(aes_out, &pframe[payload_index], chain_buffer);/* bitwise_xor(aes_out, &message[payload_index], chain_buffer); */\n\n\t\tpayload_index += 16;\n\t\taes128k128d(key, chain_buffer, aes_out);\n\t}\n\n\t/* Add on the final payload block if it needs padding */\n\tif (payload_remainder > 0) {\n\t\tfor (j = 0; j < 16; j++)\n\t\t\tpadded_buffer[j] = 0x00;\n\t\tfor (j = 0; j < payload_remainder; j++) {\n\t\t\tpadded_buffer[j] = pframe[payload_index++];/* padded_buffer[j] = message[payload_index++]; */\n\t\t}\n\t\tbitwise_xor(aes_out, padded_buffer, chain_buffer);\n\t\taes128k128d(key, chain_buffer, aes_out);\n\n\t}\n\n\tfor (j = 0 ; j < 8; j++)\n\t\tmic[j] = aes_out[j];\n\n\t/* Insert MIC into payload */\n\tfor (j = 0; j < 8; j++)\n\t\tpframe[payload_index + j] = mic[j];\t/* message[payload_index+j] = mic[j]; */\n\n\tpayload_index = hdrlen + 8;\n\tfor (i = 0; i < num_blocks; i++) {\n\t\tconstruct_ctr_preload(\n\t\t\tctr_preload,\n\t\t\ta4_exists,\n\t\t\tqc_exists,\n\t\t\tpframe,\t/* message, */\n\t\t\tpn_vector,\n\t\t\ti + 1,\n\t\t\tfrtype); /* add for CONFIG_IEEE80211W, none 11w also can use */\n\t\taes128k128d(key, ctr_preload, aes_out);\n\t\tbitwise_xor(aes_out, &pframe[payload_index], chain_buffer);/* bitwise_xor(aes_out, &message[payload_index], chain_buffer); */\n\t\tfor (j = 0; j < 16; j++)\n\t\t\tpframe[payload_index++] = chain_buffer[j];/* for (j=0; j<16;j++) message[payload_index++] = chain_buffer[j]; */\n\t}\n\n\tif (payload_remainder > 0) {        /* If there is a short final block, then pad it,*/\n\t\t/* encrypt it and copy the unpadded part back  */\n\t\tconstruct_ctr_preload(\n\t\t\tctr_preload,\n\t\t\ta4_exists,\n\t\t\tqc_exists,\n\t\t\tpframe,\t/* message, */\n\t\t\tpn_vector,\n\t\t\tnum_blocks + 1,\n\t\t\tfrtype); /* add for CONFIG_IEEE80211W, none 11w also can use */\n\n\t\tfor (j = 0; j < 16; j++)\n\t\t\tpadded_buffer[j] = 0x00;\n\t\tfor (j = 0; j < payload_remainder; j++) {\n\t\t\tpadded_buffer[j] = pframe[payload_index + j]; /* padded_buffer[j] = message[payload_index+j]; */\n\t\t}\n\t\taes128k128d(key, ctr_preload, aes_out);\n\t\tbitwise_xor(aes_out, padded_buffer, chain_buffer);\n\t\tfor (j = 0; j < payload_remainder; j++)\n\t\t\tpframe[payload_index++] = chain_buffer[j];/* for (j=0; j<payload_remainder;j++) message[payload_index++] = chain_buffer[j]; */\n\t}\n\n\t/* Encrypt the MIC */\n\tconstruct_ctr_preload(\n\t\tctr_preload,\n\t\ta4_exists,\n\t\tqc_exists,\n\t\tpframe,\t/* message, */\n\t\tpn_vector,\n\t\t0,\n\t\tfrtype); /* add for CONFIG_IEEE80211W, none 11w also can use */\n\n\tfor (j = 0; j < 16; j++)\n\t\tpadded_buffer[j] = 0x00;\n\tfor (j = 0; j < 8; j++) {\n\t\tpadded_buffer[j] = pframe[j + hdrlen + 8 + plen]; /* padded_buffer[j] = message[j+hdrlen+8+plen]; */\n\t}\n\n\taes128k128d(key, ctr_preload, aes_out);\n\tbitwise_xor(aes_out, padded_buffer, chain_buffer);\n\tfor (j = 0; j < 8; j++)\n\t\tpframe[payload_index++] = chain_buffer[j];/* for (j=0; j<8;j++) message[payload_index++] = chain_buffer[j]; */\n\treturn _SUCCESS;\n}\n\n\n\n\n\nu32\trtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe)\n{\n\t/* exclude ICV */\n\n\n\t/*static*/\n\t/*\tunsigned char\tmessage[MAX_MSG_SIZE]; */\n\n\t/* Intermediate Buffers */\n\tsint\tcurfragnum, length;\n\tu32\tprwskeylen;\n\tu8\t*pframe, *prwskey;\t/* , *payload,*iv */\n\tu8   hw_hdr_offset = 0;\n\t/* struct\tsta_info\t\t*stainfo=NULL; */\n\tstruct\tpkt_attrib\t*pattrib = &((struct xmit_frame *)pxmitframe)->attrib;\n\tstruct\tsecurity_priv\t*psecuritypriv = &padapter->securitypriv;\n\tstruct\txmit_priv\t\t*pxmitpriv = &padapter->xmitpriv;\n\n\t/*\tuint\toffset = 0; */\n\tu32 res = _SUCCESS;\n\n\tif (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)\n\t\treturn _FAIL;\n\n#ifdef CONFIG_USB_TX_AGGREGATION\n\thw_hdr_offset = TXDESC_SIZE +\n\t\t(((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);\n#else\n#ifdef CONFIG_TX_EARLY_MODE\n\thw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;\n#else\n\thw_hdr_offset = TXDESC_OFFSET;\n#endif\n#endif\n\n\tpframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset;\n\n\t/* 4 start to encrypt each fragment */\n\tif ((pattrib->encrypt == _AES_)) {\n\t\t/*\n\t\t\t\tif(pattrib->psta)\n\t\t\t\t{\n\t\t\t\t\tstainfo = pattrib->psta;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tRTW_INFO(\"%s, call rtw_get_stainfo()\\n\", __func__);\n\t\t\t\t\tstainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] );\n\t\t\t\t}\n\t\t*/\n\t\t/* if (stainfo!=NULL) */\n\t\t{\n\t\t\t/*\n\t\t\t\t\t\tif(!(stainfo->state &_FW_LINKED))\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tRTW_INFO(\"%s, psta->state(0x%x) != _FW_LINKED\\n\", __func__, stainfo->state);\n\t\t\t\t\t\t\treturn _FAIL;\n\t\t\t\t\t\t}\n\t\t\t*/\n\n\t\t\tif (IS_MCAST(pattrib->ra))\n\t\t\t\tprwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;\n\t\t\telse {\n\t\t\t\t/* prwskey=&stainfo->dot118021x_UncstKey.skey[0]; */\n\t\t\t\tprwskey = pattrib->dot118021x_UncstKey.skey;\n\t\t\t}\n\n#ifdef CONFIG_TDLS\n\t\t\t{\n\t\t\t\t/* Swencryption */\n\t\t\t\tstruct\tsta_info\t\t*ptdls_sta;\n\t\t\t\tptdls_sta = rtw_get_stainfo(&padapter->stapriv , &pattrib->dst[0]);\n\t\t\t\tif ((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) {\n\t\t\t\t\tRTW_INFO(\"[%s] for tdls link\\n\", __FUNCTION__);\n\t\t\t\t\tprwskey = &ptdls_sta->tpk.tk[0];\n\t\t\t\t}\n\t\t\t}\n#endif /* CONFIG_TDLS */\n\n\t\t\tprwskeylen = 16;\n\n\t\t\tfor (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {\n\n\t\t\t\tif ((curfragnum + 1) == pattrib->nr_frags) {\t/* 4 the last fragment */\n\t\t\t\t\tlength = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;\n\n\t\t\t\t\taes_cipher(prwskey, pattrib->hdrlen, pframe, length);\n\t\t\t\t} else {\n\t\t\t\t\tlength = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ;\n\n\t\t\t\t\taes_cipher(prwskey, pattrib->hdrlen, pframe, length);\n\t\t\t\t\tpframe += pxmitpriv->frag_len;\n\t\t\t\t\tpframe = (u8 *)RND4((SIZE_PTR)(pframe));\n\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tAES_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra);\n\t\t}\n\t\t/*\n\t\t\t\telse{\n\t\t\t\t\tRTW_INFO(\"%s, psta==NUL\\n\", __func__);\n\t\t\t\t\tres=_FAIL;\n\t\t\t\t}\n\t\t*/\n\t}\n\n\n\n\treturn res;\n}\n\nstatic sint aes_decipher(u8 *key, uint\thdrlen,\n\t\t\t u8 *pframe, uint plen)\n{\n\tstatic u8\tmessage[MAX_MSG_SIZE];\n\tuint\tqc_exists, a4_exists, i, j, payload_remainder,\n\t\tnum_blocks, payload_index;\n\tsint res = _SUCCESS;\n\tu8 pn_vector[6];\n\tu8 mic_iv[16];\n\tu8 mic_header1[16];\n\tu8 mic_header2[16];\n\tu8 ctr_preload[16];\n\n\t/* Intermediate Buffers */\n\tu8 chain_buffer[16];\n\tu8 aes_out[16];\n\tu8 padded_buffer[16];\n\tu8 mic[8];\n\n\n\t/*\tuint\toffset = 0; */\n\tuint\tfrtype  = GetFrameType(pframe);\n\tuint\tfrsubtype  = get_frame_sub_type(pframe);\n\tfrsubtype = frsubtype >> 4;\n\n\n\t_rtw_memset((void *)mic_iv, 0, 16);\n\t_rtw_memset((void *)mic_header1, 0, 16);\n\t_rtw_memset((void *)mic_header2, 0, 16);\n\t_rtw_memset((void *)ctr_preload, 0, 16);\n\t_rtw_memset((void *)chain_buffer, 0, 16);\n\t_rtw_memset((void *)aes_out, 0, 16);\n\t_rtw_memset((void *)padded_buffer, 0, 16);\n\n\t/* start to decrypt the payload */\n\n\tnum_blocks = (plen - 8) / 16; /* (plen including LLC, payload_length and mic ) */\n\n\tpayload_remainder = (plen - 8) % 16;\n\n\tpn_vector[0]  = pframe[hdrlen];\n\tpn_vector[1]  = pframe[hdrlen + 1];\n\tpn_vector[2]  = pframe[hdrlen + 4];\n\tpn_vector[3]  = pframe[hdrlen + 5];\n\tpn_vector[4]  = pframe[hdrlen + 6];\n\tpn_vector[5]  = pframe[hdrlen + 7];\n\n\tif ((hdrlen == WLAN_HDR_A3_LEN) || (hdrlen ==  WLAN_HDR_A3_QOS_LEN))\n\t\ta4_exists = 0;\n\telse\n\t\ta4_exists = 1;\n\n\tif (\n\t\t((frtype | frsubtype) == WIFI_DATA_CFACK) ||\n\t\t((frtype | frsubtype) == WIFI_DATA_CFPOLL) ||\n\t\t((frtype | frsubtype) == WIFI_DATA_CFACKPOLL)) {\n\t\tqc_exists = 1;\n\t\tif (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)\n\t\t\thdrlen += 2;\n\t} /* only for data packet . add for CONFIG_IEEE80211W, none 11w also can use */\n\telse if ((frtype == WIFI_DATA) &&\n\t\t ((frsubtype == 0x08) ||\n\t\t  (frsubtype == 0x09) ||\n\t\t  (frsubtype == 0x0a) ||\n\t\t  (frsubtype == 0x0b))) {\n\t\tif (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)\n\t\t\thdrlen += 2;\n\t\tqc_exists = 1;\n\t} else\n\t\tqc_exists = 0;\n\n\n\t/* now, decrypt pframe with hdrlen offset and plen long */\n\n\tpayload_index = hdrlen + 8; /* 8 is for extiv */\n\n\tfor (i = 0; i < num_blocks; i++) {\n\t\tconstruct_ctr_preload(\n\t\t\tctr_preload,\n\t\t\ta4_exists,\n\t\t\tqc_exists,\n\t\t\tpframe,\n\t\t\tpn_vector,\n\t\t\ti + 1,\n\t\t\tfrtype /* add for CONFIG_IEEE80211W, none 11w also can use */\n\t\t);\n\n\t\taes128k128d(key, ctr_preload, aes_out);\n\t\tbitwise_xor(aes_out, &pframe[payload_index], chain_buffer);\n\n\t\tfor (j = 0; j < 16; j++)\n\t\t\tpframe[payload_index++] = chain_buffer[j];\n\t}\n\n\tif (payload_remainder > 0) {        /* If there is a short final block, then pad it,*/\n\t\t/* encrypt it and copy the unpadded part back  */\n\t\tconstruct_ctr_preload(\n\t\t\tctr_preload,\n\t\t\ta4_exists,\n\t\t\tqc_exists,\n\t\t\tpframe,\n\t\t\tpn_vector,\n\t\t\tnum_blocks + 1,\n\t\t\tfrtype /* add for CONFIG_IEEE80211W, none 11w also can use */\n\t\t);\n\n\t\tfor (j = 0; j < 16; j++)\n\t\t\tpadded_buffer[j] = 0x00;\n\t\tfor (j = 0; j < payload_remainder; j++)\n\t\t\tpadded_buffer[j] = pframe[payload_index + j];\n\t\taes128k128d(key, ctr_preload, aes_out);\n\t\tbitwise_xor(aes_out, padded_buffer, chain_buffer);\n\t\tfor (j = 0; j < payload_remainder; j++)\n\t\t\tpframe[payload_index++] = chain_buffer[j];\n\t}\n\n\t/* start to calculate the mic\t */\n\tif ((hdrlen + plen + 8) <= MAX_MSG_SIZE)\n\t\t_rtw_memcpy((void *)message, pframe, (hdrlen + plen + 8)); /* 8 is for ext iv len */\n\n\n\tpn_vector[0] = pframe[hdrlen];\n\tpn_vector[1] = pframe[hdrlen + 1];\n\tpn_vector[2] = pframe[hdrlen + 4];\n\tpn_vector[3] = pframe[hdrlen + 5];\n\tpn_vector[4] = pframe[hdrlen + 6];\n\tpn_vector[5] = pframe[hdrlen + 7];\n\n\n\n\tconstruct_mic_iv(\n\t\tmic_iv,\n\t\tqc_exists,\n\t\ta4_exists,\n\t\tmessage,\n\t\tplen - 8,\n\t\tpn_vector,\n\t\tfrtype /* add for CONFIG_IEEE80211W, none 11w also can use */\n\t);\n\n\tconstruct_mic_header1(\n\t\tmic_header1,\n\t\thdrlen,\n\t\tmessage,\n\t\tfrtype /* add for CONFIG_IEEE80211W, none 11w also can use */\n\t);\n\tconstruct_mic_header2(\n\t\tmic_header2,\n\t\tmessage,\n\t\ta4_exists,\n\t\tqc_exists\n\t);\n\n\n\tpayload_remainder = (plen - 8) % 16;\n\tnum_blocks = (plen - 8) / 16;\n\n\t/* Find start of payload */\n\tpayload_index = (hdrlen + 8);\n\n\t/* Calculate MIC */\n\taes128k128d(key, mic_iv, aes_out);\n\tbitwise_xor(aes_out, mic_header1, chain_buffer);\n\taes128k128d(key, chain_buffer, aes_out);\n\tbitwise_xor(aes_out, mic_header2, chain_buffer);\n\taes128k128d(key, chain_buffer, aes_out);\n\n\tfor (i = 0; i < num_blocks; i++) {\n\t\tbitwise_xor(aes_out, &message[payload_index], chain_buffer);\n\n\t\tpayload_index += 16;\n\t\taes128k128d(key, chain_buffer, aes_out);\n\t}\n\n\t/* Add on the final payload block if it needs padding */\n\tif (payload_remainder > 0) {\n\t\tfor (j = 0; j < 16; j++)\n\t\t\tpadded_buffer[j] = 0x00;\n\t\tfor (j = 0; j < payload_remainder; j++)\n\t\t\tpadded_buffer[j] = message[payload_index++];\n\t\tbitwise_xor(aes_out, padded_buffer, chain_buffer);\n\t\taes128k128d(key, chain_buffer, aes_out);\n\n\t}\n\n\tfor (j = 0 ; j < 8; j++)\n\t\tmic[j] = aes_out[j];\n\n\t/* Insert MIC into payload */\n\tfor (j = 0; j < 8; j++)\n\t\tmessage[payload_index + j] = mic[j];\n\n\tpayload_index = hdrlen + 8;\n\tfor (i = 0; i < num_blocks; i++) {\n\t\tconstruct_ctr_preload(\n\t\t\tctr_preload,\n\t\t\ta4_exists,\n\t\t\tqc_exists,\n\t\t\tmessage,\n\t\t\tpn_vector,\n\t\t\ti + 1,\n\t\t\tfrtype); /* add for CONFIG_IEEE80211W, none 11w also can use */\n\t\taes128k128d(key, ctr_preload, aes_out);\n\t\tbitwise_xor(aes_out, &message[payload_index], chain_buffer);\n\t\tfor (j = 0; j < 16; j++)\n\t\t\tmessage[payload_index++] = chain_buffer[j];\n\t}\n\n\tif (payload_remainder > 0) {        /* If there is a short final block, then pad it,*/\n\t\t/* encrypt it and copy the unpadded part back  */\n\t\tconstruct_ctr_preload(\n\t\t\tctr_preload,\n\t\t\ta4_exists,\n\t\t\tqc_exists,\n\t\t\tmessage,\n\t\t\tpn_vector,\n\t\t\tnum_blocks + 1,\n\t\t\tfrtype); /* add for CONFIG_IEEE80211W, none 11w also can use */\n\n\t\tfor (j = 0; j < 16; j++)\n\t\t\tpadded_buffer[j] = 0x00;\n\t\tfor (j = 0; j < payload_remainder; j++)\n\t\t\tpadded_buffer[j] = message[payload_index + j];\n\t\taes128k128d(key, ctr_preload, aes_out);\n\t\tbitwise_xor(aes_out, padded_buffer, chain_buffer);\n\t\tfor (j = 0; j < payload_remainder; j++)\n\t\t\tmessage[payload_index++] = chain_buffer[j];\n\t}\n\n\t/* Encrypt the MIC */\n\tconstruct_ctr_preload(\n\t\tctr_preload,\n\t\ta4_exists,\n\t\tqc_exists,\n\t\tmessage,\n\t\tpn_vector,\n\t\t0,\n\t\tfrtype); /* add for CONFIG_IEEE80211W, none 11w also can use */\n\n\tfor (j = 0; j < 16; j++)\n\t\tpadded_buffer[j] = 0x00;\n\tfor (j = 0; j < 8; j++)\n\t\tpadded_buffer[j] = message[j + hdrlen + 8 + plen - 8];\n\n\taes128k128d(key, ctr_preload, aes_out);\n\tbitwise_xor(aes_out, padded_buffer, chain_buffer);\n\tfor (j = 0; j < 8; j++)\n\t\tmessage[payload_index++] = chain_buffer[j];\n\n\t/* compare the mic */\n\tfor (i = 0; i < 8; i++) {\n\t\tif (pframe[hdrlen + 8 + plen - 8 + i] != message[hdrlen + 8 + plen - 8 + i]) {\n\t\t\tRTW_INFO(\"aes_decipher:mic check error mic[%d]: pframe(%x) != message(%x)\\n\",\n\t\t\t\ti, pframe[hdrlen + 8 + plen - 8 + i], message[hdrlen + 8 + plen - 8 + i]);\n\t\t\tres = _FAIL;\n\t\t}\n\t}\n\treturn res;\n}\n\nu32\trtw_aes_decrypt(_adapter *padapter, u8 *precvframe)\n{\n\t/* exclude ICV */\n\n\n\t/*static*/\n\t/*\tunsigned char\tmessage[MAX_MSG_SIZE]; */\n\n\n\t/* Intermediate Buffers */\n\n\n\tsint\t\tlength;\n\tu8\t*pframe, *prwskey;\t/* , *payload,*iv */\n\tstruct\tsta_info\t\t*stainfo;\n\tstruct\trx_pkt_attrib\t*prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;\n\tstruct\tsecurity_priv\t*psecuritypriv = &padapter->securitypriv;\n\t/*\tstruct\trecv_priv\t\t*precvpriv=&padapter->recvpriv; */\n\tu32\tres = _SUCCESS;\n\tpframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;\n\t/* 4 start to encrypt each fragment */\n\tif ((prxattrib->encrypt == _AES_)) {\n\n\t\tstainfo = rtw_get_stainfo(&padapter->stapriv , &prxattrib->ta[0]);\n\t\tif (stainfo != NULL) {\n\n\t\t\tif (IS_MCAST(prxattrib->ra)) {\n\t\t\t\tstatic systime start = 0;\n\t\t\t\tstatic u32 no_gkey_bc_cnt = 0;\n\t\t\t\tstatic u32 no_gkey_mc_cnt = 0;\n\n\t\t\t\t/* RTW_INFO(\"rx bc/mc packets, to perform sw rtw_aes_decrypt\\n\"); */\n\t\t\t\t/* prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; */\n\t\t\t\tif ((!MLME_IS_MESH(padapter) && psecuritypriv->binstallGrpkey == _FALSE)\n\t\t\t\t\t#ifdef CONFIG_RTW_MESH\n\t\t\t\t\t|| !(stainfo->gtk_bmp | BIT(prxattrib->key_index))\n\t\t\t\t\t#endif\n\t\t\t\t) {\n\t\t\t\t\tres = _FAIL;\n\n\t\t\t\t\tif (start == 0)\n\t\t\t\t\t\tstart = rtw_get_current_time();\n\n\t\t\t\t\tif (is_broadcast_mac_addr(prxattrib->ra))\n\t\t\t\t\t\tno_gkey_bc_cnt++;\n\t\t\t\t\telse\n\t\t\t\t\t\tno_gkey_mc_cnt++;\n\n\t\t\t\t\tif (rtw_get_passing_time_ms(start) > 1000) {\n\t\t\t\t\t\tif (no_gkey_bc_cnt || no_gkey_mc_cnt) {\n\t\t\t\t\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\\n\",\n\t\t\t\t\t\t\t\tFUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);\n\t\t\t\t\t\t}\n\t\t\t\t\t\tstart = rtw_get_current_time();\n\t\t\t\t\t\tno_gkey_bc_cnt = 0;\n\t\t\t\t\t\tno_gkey_mc_cnt = 0;\n\t\t\t\t\t}\n\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\n\t\t\t\tif (no_gkey_bc_cnt || no_gkey_mc_cnt) {\n\t\t\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\\n\",\n\t\t\t\t\t\tFUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);\n\t\t\t\t}\n\t\t\t\tstart = 0;\n\t\t\t\tno_gkey_bc_cnt = 0;\n\t\t\t\tno_gkey_mc_cnt = 0;\n\n\t\t\t\t#ifdef CONFIG_RTW_MESH\n\t\t\t\tif (MLME_IS_MESH(padapter)) {\n\t\t\t\t\t/* TODO: multiple GK? */\n\t\t\t\t\tprwskey = &stainfo->gtk.skey[0];\n\t\t\t\t} else\n\t\t\t\t#endif\n\t\t\t\t{\n\t\t\t\t\tprwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey;\n\t\t\t\t\tif (psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) {\n\t\t\t\t\t\tRTW_DBG(\"not match packet_index=%d, install_index=%d\\n\"\n\t\t\t\t\t\t\t, prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid);\n\t\t\t\t\t\tres = _FAIL;\n\t\t\t\t\t\tgoto exit;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else\n\t\t\t\tprwskey = &stainfo->dot118021x_UncstKey.skey[0];\n\n\t\t\tlength = ((union recv_frame *)precvframe)->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len;\n#if 0\n\t\t\t/*  add for CONFIG_IEEE80211W, debug */\n\t\t\tif (0)\n\t\t\t\tprintk(\"@@@@@@@@@@@@@@@@@@ length=%d, prxattrib->hdrlen=%d, prxattrib->pkt_len=%d\\n\"\n\t\t\t\t       , length, prxattrib->hdrlen, prxattrib->pkt_len);\n\t\t\tif (0) {\n\t\t\t\tint no;\n\t\t\t\t/* test print PSK */\n\t\t\t\tprintk(\"PSK key below:\\n\");\n\t\t\t\tfor (no = 0; no < 16; no++)\n\t\t\t\t\tprintk(\" %02x \", prwskey[no]);\n\t\t\t\tprintk(\"\\n\");\n\t\t\t}\n\t\t\tif (0) {\n\t\t\t\tint no;\n\t\t\t\t/* test print PSK */\n\t\t\t\tprintk(\"frame:\\n\");\n\t\t\t\tfor (no = 0; no < prxattrib->pkt_len; no++)\n\t\t\t\t\tprintk(\" %02x \", pframe[no]);\n\t\t\t\tprintk(\"\\n\");\n\t\t\t}\n#endif\n\n\t\t\tres = aes_decipher(prwskey, prxattrib->hdrlen, pframe, length);\n\n\t\t\tAES_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);\n\t\t} else {\n\t\t\tres = _FAIL;\n\t\t}\n\n\t}\nexit:\n\treturn res;\n}\n\n#ifdef CONFIG_IEEE80211W\nu32\trtw_BIP_verify(_adapter *padapter, u8 *whdr_pos, sint flen\n\t, const u8 *key, u16 keyid, u64* ipn)\n{\n\tu8 *BIP_AAD, *mme;\n\tu32\tres = _FAIL;\n\tuint len, ori_len;\n\tu16 pkt_keyid = 0;\n\tu64 pkt_ipn = 0;\n\tstruct rtw_ieee80211_hdr *pwlanhdr;\n\tu8 mic[16];\n\n\tmme = whdr_pos + flen - 18;\n\tif (*mme != _MME_IE_)\n\t\treturn RTW_RX_HANDLED;\n\n\t/* copy key index */\n\t_rtw_memcpy(&pkt_keyid, mme + 2, 2);\n\tpkt_keyid = le16_to_cpu(pkt_keyid);\n\tif (pkt_keyid != keyid) {\n\t\tRTW_INFO(\"BIP key index error!\\n\");\n\t\treturn _FAIL;\n\t}\n\n\t/* save packet number */\n\t_rtw_memcpy(&pkt_ipn, mme + 4, 6);\n\tpkt_ipn = le64_to_cpu(pkt_ipn);\n\t/* BIP packet number should bigger than previous BIP packet */\n\tif (pkt_ipn <= *ipn) { /* wrap around? */\n\t\tRTW_INFO(\"replay BIP packet\\n\");\n\t\treturn _FAIL;\n\t}\n\n\tori_len = flen - WLAN_HDR_A3_LEN + BIP_AAD_SIZE;\n\tBIP_AAD = rtw_zmalloc(ori_len);\n\tif (BIP_AAD == NULL) {\n\t\tRTW_INFO(\"BIP AAD allocate fail\\n\");\n\t\treturn _FAIL;\n\t}\n\n\t/* mapping to wlan header */\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)whdr_pos;\n\n\t/* save the frame body + MME */\n\t_rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, whdr_pos + WLAN_HDR_A3_LEN, flen - WLAN_HDR_A3_LEN);\n\n\t/* point mme to the copy */\n\tmme = BIP_AAD + ori_len - 18;\n\n\t/* clear the MIC field of MME to zero */\n\t_rtw_memset(mme + 10, 0, 8);\n\n\t/* conscruct AAD, copy frame control field */\n\t_rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2);\n\tClearRetry(BIP_AAD);\n\tClearPwrMgt(BIP_AAD);\n\tClearMData(BIP_AAD);\n\t/* conscruct AAD, copy address 1 to address 3 */\n\t_rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18);\n\n\tif (omac1_aes_128(key, BIP_AAD, ori_len, mic))\n\t\tgoto BIP_exit;\n\n#if 0\n\t/* management packet content */\n\t{\n\t\tint pp;\n\t\tRTW_INFO(\"pkt: \");\n\t\tfor (pp = 0; pp < flen; pp++)\n\t\t\tprintk(\" %02x \", whdr_pos[pp]);\n\t\tRTW_INFO(\"\\n\");\n\t\t/* BIP AAD + management frame body + MME(MIC is zero) */\n\t\tRTW_INFO(\"AAD+PKT: \");\n\t\tfor (pp = 0; pp < ori_len; pp++)\n\t\t\tRTW_INFO(\" %02x \", BIP_AAD[pp]);\n\t\tRTW_INFO(\"\\n\");\n\t\t/* show the MIC result */\n\t\tRTW_INFO(\"mic: \");\n\t\tfor (pp = 0; pp < 16; pp++)\n\t\t\tRTW_INFO(\" %02x \", mic[pp]);\n\t\tRTW_INFO(\"\\n\");\n\t}\n#endif\n\n\t/* MIC field should be last 8 bytes of packet (packet without FCS) */\n\tif (_rtw_memcmp(mic, whdr_pos + flen - 8, 8)) {\n\t\t*ipn = pkt_ipn;\n\t\tres = _SUCCESS;\n\t} else\n\t\tRTW_INFO(\"BIP MIC error!\\n\");\n\nBIP_exit:\n\n\trtw_mfree(BIP_AAD, ori_len);\n\treturn res;\n}\n#endif /* CONFIG_IEEE80211W */\n\n#ifndef PLATFORM_FREEBSD\n#if defined(CONFIG_TDLS)\n/* compress 512-bits */\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))\nstatic int sha256_compress(struct sha256_state *md, unsigned char *buf)\n{\n\tu32 S[8], W[64], t0, t1;\n\tu32 t;\n\tint i;\n\n\t/* copy state into S */\n\tfor (i = 0; i < 8; i++)\n\t\tS[i] = md->state[i];\n\n\t/* copy the state into 512-bits into W[0..15] */\n\tfor (i = 0; i < 16; i++)\n\t\tW[i] = WPA_GET_BE32(buf + (4 * i));\n\n\t/* fill W[16..63] */\n\tfor (i = 16; i < 64; i++) {\n\t\tW[i] = Gamma1(W[i - 2]) + W[i - 7] + Gamma0(W[i - 15]) +\n\t\t       W[i - 16];\n\t}\n\n\t/* Compress */\n#define RND(a, b, c, d, e, f, g, h, i)                          do {\\\n\tt0 = h + Sigma1(e) + Ch(e, f, g) + K[i] + W[i];\t\\\n\tt1 = Sigma0(a) + Maj(a, b, c);\t\t\t\\\n\td += t0;\t\t\t\t\t\\\n\th  = t0 + t1;\t\\\n\t} while (0)\n\n\tfor (i = 0; i < 64; ++i) {\n\t\tRND(S[0], S[1], S[2], S[3], S[4], S[5], S[6], S[7], i);\n\t\tt = S[7];\n\t\tS[7] = S[6];\n\t\tS[6] = S[5];\n\t\tS[5] = S[4];\n\t\tS[4] = S[3];\n\t\tS[3] = S[2];\n\t\tS[2] = S[1];\n\t\tS[1] = S[0];\n\t\tS[0] = t;\n\t}\n\n\t/* feedback */\n\tfor (i = 0; i < 8; i++)\n\t\tmd->state[i] = md->state[i] + S[i];\n\treturn 0;\n}\n#endif\n\n/* Initialize the hash state */\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))\nstatic void sha256_init(struct sha256_state *md)\n{\n\tmd->curlen = 0;\n\tmd->length = 0;\n\tmd->state[0] = 0x6A09E667UL;\n\tmd->state[1] = 0xBB67AE85UL;\n\tmd->state[2] = 0x3C6EF372UL;\n\tmd->state[3] = 0xA54FF53AUL;\n\tmd->state[4] = 0x510E527FUL;\n\tmd->state[5] = 0x9B05688CUL;\n\tmd->state[6] = 0x1F83D9ABUL;\n\tmd->state[7] = 0x5BE0CD19UL;\n}\n#endif\n\n/**\n   Process a block of memory though the hash\n   @param md     The hash state\n   @param in     The data to hash\n   @param inlen  The length of the data (octets)\n   @return CRYPT_OK if successful\n*/\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))\nstatic int sha256_process(struct sha256_state *md, unsigned char *in,\n\t\t\t  unsigned long inlen)\n{\n\tunsigned long n;\n#define block_size 64\n\n\tif (md->curlen >= sizeof(md->buf))\n\t\treturn -1;\n\n\twhile (inlen > 0) {\n\t\tif (md->curlen == 0 && inlen >= block_size) {\n\t\t\tif (sha256_compress(md, (unsigned char *) in) < 0)\n\t\t\t\treturn -1;\n\t\t\tmd->length += block_size * 8;\n\t\t\tin += block_size;\n\t\t\tinlen -= block_size;\n\t\t} else {\n\t\t\tn = MIN(inlen, (block_size - md->curlen));\n\t\t\t_rtw_memcpy(md->buf + md->curlen, in, n);\n\t\t\tmd->curlen += n;\n\t\t\tin += n;\n\t\t\tinlen -= n;\n\t\t\tif (md->curlen == block_size) {\n\t\t\t\tif (sha256_compress(md, md->buf) < 0)\n\t\t\t\t\treturn -1;\n\t\t\t\tmd->length += 8 * block_size;\n\t\t\t\tmd->curlen = 0;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n#endif\n\n/**\n   Terminate the hash to get the digest\n   @param md  The hash state\n   @param out [out] The destination of the hash (32 bytes)\n   @return CRYPT_OK if successful\n*/\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))\nstatic int sha256_done(struct sha256_state *md, unsigned char *out)\n{\n\tint i;\n\n\tif (md->curlen >= sizeof(md->buf))\n\t\treturn -1;\n\n\t/* increase the length of the message */\n\tmd->length += md->curlen * 8;\n\n\t/* append the '1' bit */\n\tmd->buf[md->curlen++] = (unsigned char) 0x80;\n\n\t/* if the length is currently above 56 bytes we append zeros\n\t * then compress.  Then we can fall back to padding zeros and length\n\t * encoding like normal.\n\t */\n\tif (md->curlen > 56) {\n\t\twhile (md->curlen < 64)\n\t\t\tmd->buf[md->curlen++] = (unsigned char) 0;\n\t\tsha256_compress(md, md->buf);\n\t\tmd->curlen = 0;\n\t}\n\n\t/* pad upto 56 bytes of zeroes */\n\twhile (md->curlen < 56)\n\t\tmd->buf[md->curlen++] = (unsigned char) 0;\n\n\t/* store length */\n\tWPA_PUT_BE64(md->buf + 56, md->length);\n\tsha256_compress(md, md->buf);\n\n\t/* copy output */\n\tfor (i = 0; i < 8; i++)\n\t\tWPA_PUT_BE32(out + (4 * i), md->state[i]);\n\n\treturn 0;\n}\n#endif\n\n/**\n * sha256_vector - SHA256 hash for data vector\n * @num_elem: Number of elements in the data vector\n * @addr: Pointers to the data areas\n * @len: Lengths of the data blocks\n * @mac: Buffer for the hash\n * Returns: 0 on success, -1 of failure\n */\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))\nstatic int sha256_vector(size_t num_elem, u8 *addr[], size_t *len,\n\t\t\t u8 *mac)\n{\n\tstruct sha256_state ctx;\n\tsize_t i;\n\n\tsha256_init(&ctx);\n\tfor (i = 0; i < num_elem; i++)\n\t\tif (sha256_process(&ctx, addr[i], len[i]))\n\t\t\treturn -1;\n\tif (sha256_done(&ctx, mac))\n\t\treturn -1;\n\treturn 0;\n}\n#endif\n\nstatic u8 os_strlen(const char *s)\n{\n\tconst char *p = s;\n\twhile (*p)\n\t\tp++;\n\treturn p - s;\n}\n#endif\n\n#if defined(CONFIG_TDLS) || defined(CONFIG_RTW_MESH_AEK)\nstatic int os_memcmp(const void *s1, const void *s2, u8 n)\n{\n\tconst unsigned char *p1 = s1, *p2 = s2;\n\n\tif (n == 0)\n\t\treturn 0;\n\n\twhile (*p1 == *p2) {\n\t\tp1++;\n\t\tp2++;\n\t\tn--;\n\t\tif (n == 0)\n\t\t\treturn 0;\n\t}\n\n\treturn *p1 - *p2;\n}\n#endif\n\n/**\n * hmac_sha256_vector - HMAC-SHA256 over data vector (RFC 2104)\n * @key: Key for HMAC operations\n * @key_len: Length of the key in bytes\n * @num_elem: Number of elements in the data vector\n * @addr: Pointers to the data areas\n * @len: Lengths of the data blocks\n * @mac: Buffer for the hash (32 bytes)\n */\n#if defined(CONFIG_TDLS)\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))\nstatic void hmac_sha256_vector(u8 *key, size_t key_len, size_t num_elem,\n\t\t\t       u8 *addr[], size_t *len, u8 *mac)\n{\n\tunsigned char k_pad[64]; /* padding - key XORd with ipad/opad */\n\tunsigned char tk[32];\n\tu8 *_addr[6];\n\tsize_t _len[6], i;\n\n\tif (num_elem > 5) {\n\t\t/*\n\t\t * Fixed limit on the number of fragments to avoid having to\n\t\t * allocate memory (which could fail).\n\t\t */\n\t\treturn;\n\t}\n\n\t/* if key is longer than 64 bytes reset it to key = SHA256(key) */\n\tif (key_len > 64) {\n\t\tsha256_vector(1, &key, &key_len, tk);\n\t\tkey = tk;\n\t\tkey_len = 32;\n\t}\n\n\t/* the HMAC_SHA256 transform looks like:\n\t *\n\t * SHA256(K XOR opad, SHA256(K XOR ipad, text))\n\t *\n\t * where K is an n byte key\n\t * ipad is the byte 0x36 repeated 64 times\n\t * opad is the byte 0x5c repeated 64 times\n\t * and text is the data being protected */\n\n\t/* start out by storing key in ipad */\n\t_rtw_memset(k_pad, 0, sizeof(k_pad));\n\t_rtw_memcpy(k_pad, key, key_len);\n\t/* XOR key with ipad values */\n\tfor (i = 0; i < 64; i++)\n\t\tk_pad[i] ^= 0x36;\n\n\t/* perform inner SHA256 */\n\t_addr[0] = k_pad;\n\t_len[0] = 64;\n\tfor (i = 0; i < num_elem; i++) {\n\t\t_addr[i + 1] = addr[i];\n\t\t_len[i + 1] = len[i];\n\t}\n\tsha256_vector(1 + num_elem, _addr, _len, mac);\n\n\t_rtw_memset(k_pad, 0, sizeof(k_pad));\n\t_rtw_memcpy(k_pad, key, key_len);\n\t/* XOR key with opad values */\n\tfor (i = 0; i < 64; i++)\n\t\tk_pad[i] ^= 0x5c;\n\n\t/* perform outer SHA256 */\n\t_addr[0] = k_pad;\n\t_len[0] = 64;\n\t_addr[1] = mac;\n\t_len[1] = 32;\n\tsha256_vector(2, _addr, _len, mac);\n}\n#endif\n#endif /* CONFIG_TDLS */\n#endif /* PLATFORM_FREEBSD */\n/**\n * sha256_prf - SHA256-based Pseudo-Random Function (IEEE 802.11r, 8.5.1.5.2)\n * @key: Key for PRF\n * @key_len: Length of the key in bytes\n * @label: A unique label for each purpose of the PRF\n * @data: Extra data to bind into the key\n * @data_len: Length of the data\n * @buf: Buffer for the generated pseudo-random key\n * @buf_len: Number of bytes of key to generate\n *\n * This function is used to derive new, cryptographically separate keys from a\n * given key.\n */\n#ifndef PLATFORM_FREEBSD /* Baron */\n#if defined(CONFIG_TDLS)\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))\nstatic void sha256_prf(u8 *key, size_t key_len, char *label,\n\t\t       u8 *data, size_t data_len, u8 *buf, size_t buf_len)\n{\n\tu16 counter = 1;\n\tsize_t pos, plen;\n\tu8 hash[SHA256_MAC_LEN];\n\tu8 *addr[4];\n\tsize_t len[4];\n\tu8 counter_le[2], length_le[2];\n\n\taddr[0] = counter_le;\n\tlen[0] = 2;\n\taddr[1] = (u8 *) label;\n\tlen[1] = os_strlen(label);\n\taddr[2] = data;\n\tlen[2] = data_len;\n\taddr[3] = length_le;\n\tlen[3] = sizeof(length_le);\n\n\tWPA_PUT_LE16(length_le, buf_len * 8);\n\tpos = 0;\n\twhile (pos < buf_len) {\n\t\tplen = buf_len - pos;\n\t\tWPA_PUT_LE16(counter_le, counter);\n\t\tif (plen >= SHA256_MAC_LEN) {\n\t\t\thmac_sha256_vector(key, key_len, 4, addr, len,\n\t\t\t\t\t   &buf[pos]);\n\t\t\tpos += SHA256_MAC_LEN;\n\t\t} else {\n\t\t\thmac_sha256_vector(key, key_len, 4, addr, len, hash);\n\t\t\t_rtw_memcpy(&buf[pos], hash, plen);\n\t\t\tbreak;\n\t\t}\n\t\tcounter++;\n\t}\n}\n#endif\n#endif\n#endif /* PLATFORM_FREEBSD Baron */\n\n/* AES tables*/\nconst u32 Te0[256] = {\n\t0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU,\n\t0xfff2f20dU, 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U,\n\t0x60303050U, 0x02010103U, 0xce6767a9U, 0x562b2b7dU,\n\t0xe7fefe19U, 0xb5d7d762U, 0x4dababe6U, 0xec76769aU,\n\t0x8fcaca45U, 0x1f82829dU, 0x89c9c940U, 0xfa7d7d87U,\n\t0xeffafa15U, 0xb25959ebU, 0x8e4747c9U, 0xfbf0f00bU,\n\t0x41adadecU, 0xb3d4d467U, 0x5fa2a2fdU, 0x45afafeaU,\n\t0x239c9cbfU, 0x53a4a4f7U, 0xe4727296U, 0x9bc0c05bU,\n\t0x75b7b7c2U, 0xe1fdfd1cU, 0x3d9393aeU, 0x4c26266aU,\n\t0x6c36365aU, 0x7e3f3f41U, 0xf5f7f702U, 0x83cccc4fU,\n\t0x6834345cU, 0x51a5a5f4U, 0xd1e5e534U, 0xf9f1f108U,\n\t0xe2717193U, 0xabd8d873U, 0x62313153U, 0x2a15153fU,\n\t0x0804040cU, 0x95c7c752U, 0x46232365U, 0x9dc3c35eU,\n\t0x30181828U, 0x379696a1U, 0x0a05050fU, 0x2f9a9ab5U,\n\t0x0e070709U, 0x24121236U, 0x1b80809bU, 0xdfe2e23dU,\n\t0xcdebeb26U, 0x4e272769U, 0x7fb2b2cdU, 0xea75759fU,\n\t0x1209091bU, 0x1d83839eU, 0x582c2c74U, 0x341a1a2eU,\n\t0x361b1b2dU, 0xdc6e6eb2U, 0xb45a5aeeU, 0x5ba0a0fbU,\n\t0xa45252f6U, 0x763b3b4dU, 0xb7d6d661U, 0x7db3b3ceU,\n\t0x5229297bU, 0xdde3e33eU, 0x5e2f2f71U, 0x13848497U,\n\t0xa65353f5U, 0xb9d1d168U, 0x00000000U, 0xc1eded2cU,\n\t0x40202060U, 0xe3fcfc1fU, 0x79b1b1c8U, 0xb65b5bedU,\n\t0xd46a6abeU, 0x8dcbcb46U, 0x67bebed9U, 0x7239394bU,\n\t0x944a4adeU, 0x984c4cd4U, 0xb05858e8U, 0x85cfcf4aU,\n\t0xbbd0d06bU, 0xc5efef2aU, 0x4faaaae5U, 0xedfbfb16U,\n\t0x864343c5U, 0x9a4d4dd7U, 0x66333355U, 0x11858594U,\n\t0x8a4545cfU, 0xe9f9f910U, 0x04020206U, 0xfe7f7f81U,\n\t0xa05050f0U, 0x783c3c44U, 0x259f9fbaU, 0x4ba8a8e3U,\n\t0xa25151f3U, 0x5da3a3feU, 0x804040c0U, 0x058f8f8aU,\n\t0x3f9292adU, 0x219d9dbcU, 0x70383848U, 0xf1f5f504U,\n\t0x63bcbcdfU, 0x77b6b6c1U, 0xafdada75U, 0x42212163U,\n\t0x20101030U, 0xe5ffff1aU, 0xfdf3f30eU, 0xbfd2d26dU,\n\t0x81cdcd4cU, 0x180c0c14U, 0x26131335U, 0xc3ecec2fU,\n\t0xbe5f5fe1U, 0x359797a2U, 0x884444ccU, 0x2e171739U,\n\t0x93c4c457U, 0x55a7a7f2U, 0xfc7e7e82U, 0x7a3d3d47U,\n\t0xc86464acU, 0xba5d5de7U, 0x3219192bU, 0xe6737395U,\n\t0xc06060a0U, 0x19818198U, 0x9e4f4fd1U, 0xa3dcdc7fU,\n\t0x44222266U, 0x542a2a7eU, 0x3b9090abU, 0x0b888883U,\n\t0x8c4646caU, 0xc7eeee29U, 0x6bb8b8d3U, 0x2814143cU,\n\t0xa7dede79U, 0xbc5e5ee2U, 0x160b0b1dU, 0xaddbdb76U,\n\t0xdbe0e03bU, 0x64323256U, 0x743a3a4eU, 0x140a0a1eU,\n\t0x924949dbU, 0x0c06060aU, 0x4824246cU, 0xb85c5ce4U,\n\t0x9fc2c25dU, 0xbdd3d36eU, 0x43acacefU, 0xc46262a6U,\n\t0x399191a8U, 0x319595a4U, 0xd3e4e437U, 0xf279798bU,\n\t0xd5e7e732U, 0x8bc8c843U, 0x6e373759U, 0xda6d6db7U,\n\t0x018d8d8cU, 0xb1d5d564U, 0x9c4e4ed2U, 0x49a9a9e0U,\n\t0xd86c6cb4U, 0xac5656faU, 0xf3f4f407U, 0xcfeaea25U,\n\t0xca6565afU, 0xf47a7a8eU, 0x47aeaee9U, 0x10080818U,\n\t0x6fbabad5U, 0xf0787888U, 0x4a25256fU, 0x5c2e2e72U,\n\t0x381c1c24U, 0x57a6a6f1U, 0x73b4b4c7U, 0x97c6c651U,\n\t0xcbe8e823U, 0xa1dddd7cU, 0xe874749cU, 0x3e1f1f21U,\n\t0x964b4bddU, 0x61bdbddcU, 0x0d8b8b86U, 0x0f8a8a85U,\n\t0xe0707090U, 0x7c3e3e42U, 0x71b5b5c4U, 0xcc6666aaU,\n\t0x904848d8U, 0x06030305U, 0xf7f6f601U, 0x1c0e0e12U,\n\t0xc26161a3U, 0x6a35355fU, 0xae5757f9U, 0x69b9b9d0U,\n\t0x17868691U, 0x99c1c158U, 0x3a1d1d27U, 0x279e9eb9U,\n\t0xd9e1e138U, 0xebf8f813U, 0x2b9898b3U, 0x22111133U,\n\t0xd26969bbU, 0xa9d9d970U, 0x078e8e89U, 0x339494a7U,\n\t0x2d9b9bb6U, 0x3c1e1e22U, 0x15878792U, 0xc9e9e920U,\n\t0x87cece49U, 0xaa5555ffU, 0x50282878U, 0xa5dfdf7aU,\n\t0x038c8c8fU, 0x59a1a1f8U, 0x09898980U, 0x1a0d0d17U,\n\t0x65bfbfdaU, 0xd7e6e631U, 0x844242c6U, 0xd06868b8U,\n\t0x824141c3U, 0x299999b0U, 0x5a2d2d77U, 0x1e0f0f11U,\n\t0x7bb0b0cbU, 0xa85454fcU, 0x6dbbbbd6U, 0x2c16163aU,\n};\nconst u32 Td0[256] = {\n\t0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U,\n\t0x3bab6bcbU, 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U,\n\t0x2030fa55U, 0xad766df6U, 0x88cc7691U, 0xf5024c25U,\n\t0x4fe5d7fcU, 0xc52acbd7U, 0x26354480U, 0xb562a38fU,\n\t0xdeb15a49U, 0x25ba1b67U, 0x45ea0e98U, 0x5dfec0e1U,\n\t0xc32f7502U, 0x814cf012U, 0x8d4697a3U, 0x6bd3f9c6U,\n\t0x038f5fe7U, 0x15929c95U, 0xbf6d7aebU, 0x955259daU,\n\t0xd4be832dU, 0x587421d3U, 0x49e06929U, 0x8ec9c844U,\n\t0x75c2896aU, 0xf48e7978U, 0x99583e6bU, 0x27b971ddU,\n\t0xbee14fb6U, 0xf088ad17U, 0xc920ac66U, 0x7dce3ab4U,\n\t0x63df4a18U, 0xe51a3182U, 0x97513360U, 0x62537f45U,\n\t0xb16477e0U, 0xbb6bae84U, 0xfe81a01cU, 0xf9082b94U,\n\t0x70486858U, 0x8f45fd19U, 0x94de6c87U, 0x527bf8b7U,\n\t0xab73d323U, 0x724b02e2U, 0xe31f8f57U, 0x6655ab2aU,\n\t0xb2eb2807U, 0x2fb5c203U, 0x86c57b9aU, 0xd33708a5U,\n\t0x302887f2U, 0x23bfa5b2U, 0x02036abaU, 0xed16825cU,\n\t0x8acf1c2bU, 0xa779b492U, 0xf307f2f0U, 0x4e69e2a1U,\n\t0x65daf4cdU, 0x0605bed5U, 0xd134621fU, 0xc4a6fe8aU,\n\t0x342e539dU, 0xa2f355a0U, 0x058ae132U, 0xa4f6eb75U,\n\t0x0b83ec39U, 0x4060efaaU, 0x5e719f06U, 0xbd6e1051U,\n\t0x3e218af9U, 0x96dd063dU, 0xdd3e05aeU, 0x4de6bd46U,\n\t0x91548db5U, 0x71c45d05U, 0x0406d46fU, 0x605015ffU,\n\t0x1998fb24U, 0xd6bde997U, 0x894043ccU, 0x67d99e77U,\n\t0xb0e842bdU, 0x07898b88U, 0xe7195b38U, 0x79c8eedbU,\n\t0xa17c0a47U, 0x7c420fe9U, 0xf8841ec9U, 0x00000000U,\n\t0x09808683U, 0x322bed48U, 0x1e1170acU, 0x6c5a724eU,\n\t0xfd0efffbU, 0x0f853856U, 0x3daed51eU, 0x362d3927U,\n\t0x0a0fd964U, 0x685ca621U, 0x9b5b54d1U, 0x24362e3aU,\n\t0x0c0a67b1U, 0x9357e70fU, 0xb4ee96d2U, 0x1b9b919eU,\n\t0x80c0c54fU, 0x61dc20a2U, 0x5a774b69U, 0x1c121a16U,\n\t0xe293ba0aU, 0xc0a02ae5U, 0x3c22e043U, 0x121b171dU,\n\t0x0e090d0bU, 0xf28bc7adU, 0x2db6a8b9U, 0x141ea9c8U,\n\t0x57f11985U, 0xaf75074cU, 0xee99ddbbU, 0xa37f60fdU,\n\t0xf701269fU, 0x5c72f5bcU, 0x44663bc5U, 0x5bfb7e34U,\n\t0x8b432976U, 0xcb23c6dcU, 0xb6edfc68U, 0xb8e4f163U,\n\t0xd731dccaU, 0x42638510U, 0x13972240U, 0x84c61120U,\n\t0x854a247dU, 0xd2bb3df8U, 0xaef93211U, 0xc729a16dU,\n\t0x1d9e2f4bU, 0xdcb230f3U, 0x0d8652ecU, 0x77c1e3d0U,\n\t0x2bb3166cU, 0xa970b999U, 0x119448faU, 0x47e96422U,\n\t0xa8fc8cc4U, 0xa0f03f1aU, 0x567d2cd8U, 0x223390efU,\n\t0x87494ec7U, 0xd938d1c1U, 0x8ccaa2feU, 0x98d40b36U,\n\t0xa6f581cfU, 0xa57ade28U, 0xdab78e26U, 0x3fadbfa4U,\n\t0x2c3a9de4U, 0x5078920dU, 0x6a5fcc9bU, 0x547e4662U,\n\t0xf68d13c2U, 0x90d8b8e8U, 0x2e39f75eU, 0x82c3aff5U,\n\t0x9f5d80beU, 0x69d0937cU, 0x6fd52da9U, 0xcf2512b3U,\n\t0xc8ac993bU, 0x10187da7U, 0xe89c636eU, 0xdb3bbb7bU,\n\t0xcd267809U, 0x6e5918f4U, 0xec9ab701U, 0x834f9aa8U,\n\t0xe6956e65U, 0xaaffe67eU, 0x21bccf08U, 0xef15e8e6U,\n\t0xbae79bd9U, 0x4a6f36ceU, 0xea9f09d4U, 0x29b07cd6U,\n\t0x31a4b2afU, 0x2a3f2331U, 0xc6a59430U, 0x35a266c0U,\n\t0x744ebc37U, 0xfc82caa6U, 0xe090d0b0U, 0x33a7d815U,\n\t0xf104984aU, 0x41ecdaf7U, 0x7fcd500eU, 0x1791f62fU,\n\t0x764dd68dU, 0x43efb04dU, 0xccaa4d54U, 0xe49604dfU,\n\t0x9ed1b5e3U, 0x4c6a881bU, 0xc12c1fb8U, 0x4665517fU,\n\t0x9d5eea04U, 0x018c355dU, 0xfa877473U, 0xfb0b412eU,\n\t0xb3671d5aU, 0x92dbd252U, 0xe9105633U, 0x6dd64713U,\n\t0x9ad7618cU, 0x37a10c7aU, 0x59f8148eU, 0xeb133c89U,\n\t0xcea927eeU, 0xb761c935U, 0xe11ce5edU, 0x7a47b13cU,\n\t0x9cd2df59U, 0x55f2733fU, 0x1814ce79U, 0x73c737bfU,\n\t0x53f7cdeaU, 0x5ffdaa5bU, 0xdf3d6f14U, 0x7844db86U,\n\t0xcaaff381U, 0xb968c43eU, 0x3824342cU, 0xc2a3405fU,\n\t0x161dc372U, 0xbce2250cU, 0x283c498bU, 0xff0d9541U,\n\t0x39a80171U, 0x080cb3deU, 0xd8b4e49cU, 0x6456c190U,\n\t0x7bcb8461U, 0xd532b670U, 0x486c5c74U, 0xd0b85742U,\n};\nconst u8 Td4s[256] = {\n\t0x52U, 0x09U, 0x6aU, 0xd5U, 0x30U, 0x36U, 0xa5U, 0x38U,\n\t0xbfU, 0x40U, 0xa3U, 0x9eU, 0x81U, 0xf3U, 0xd7U, 0xfbU,\n\t0x7cU, 0xe3U, 0x39U, 0x82U, 0x9bU, 0x2fU, 0xffU, 0x87U,\n\t0x34U, 0x8eU, 0x43U, 0x44U, 0xc4U, 0xdeU, 0xe9U, 0xcbU,\n\t0x54U, 0x7bU, 0x94U, 0x32U, 0xa6U, 0xc2U, 0x23U, 0x3dU,\n\t0xeeU, 0x4cU, 0x95U, 0x0bU, 0x42U, 0xfaU, 0xc3U, 0x4eU,\n\t0x08U, 0x2eU, 0xa1U, 0x66U, 0x28U, 0xd9U, 0x24U, 0xb2U,\n\t0x76U, 0x5bU, 0xa2U, 0x49U, 0x6dU, 0x8bU, 0xd1U, 0x25U,\n\t0x72U, 0xf8U, 0xf6U, 0x64U, 0x86U, 0x68U, 0x98U, 0x16U,\n\t0xd4U, 0xa4U, 0x5cU, 0xccU, 0x5dU, 0x65U, 0xb6U, 0x92U,\n\t0x6cU, 0x70U, 0x48U, 0x50U, 0xfdU, 0xedU, 0xb9U, 0xdaU,\n\t0x5eU, 0x15U, 0x46U, 0x57U, 0xa7U, 0x8dU, 0x9dU, 0x84U,\n\t0x90U, 0xd8U, 0xabU, 0x00U, 0x8cU, 0xbcU, 0xd3U, 0x0aU,\n\t0xf7U, 0xe4U, 0x58U, 0x05U, 0xb8U, 0xb3U, 0x45U, 0x06U,\n\t0xd0U, 0x2cU, 0x1eU, 0x8fU, 0xcaU, 0x3fU, 0x0fU, 0x02U,\n\t0xc1U, 0xafU, 0xbdU, 0x03U, 0x01U, 0x13U, 0x8aU, 0x6bU,\n\t0x3aU, 0x91U, 0x11U, 0x41U, 0x4fU, 0x67U, 0xdcU, 0xeaU,\n\t0x97U, 0xf2U, 0xcfU, 0xceU, 0xf0U, 0xb4U, 0xe6U, 0x73U,\n\t0x96U, 0xacU, 0x74U, 0x22U, 0xe7U, 0xadU, 0x35U, 0x85U,\n\t0xe2U, 0xf9U, 0x37U, 0xe8U, 0x1cU, 0x75U, 0xdfU, 0x6eU,\n\t0x47U, 0xf1U, 0x1aU, 0x71U, 0x1dU, 0x29U, 0xc5U, 0x89U,\n\t0x6fU, 0xb7U, 0x62U, 0x0eU, 0xaaU, 0x18U, 0xbeU, 0x1bU,\n\t0xfcU, 0x56U, 0x3eU, 0x4bU, 0xc6U, 0xd2U, 0x79U, 0x20U,\n\t0x9aU, 0xdbU, 0xc0U, 0xfeU, 0x78U, 0xcdU, 0x5aU, 0xf4U,\n\t0x1fU, 0xddU, 0xa8U, 0x33U, 0x88U, 0x07U, 0xc7U, 0x31U,\n\t0xb1U, 0x12U, 0x10U, 0x59U, 0x27U, 0x80U, 0xecU, 0x5fU,\n\t0x60U, 0x51U, 0x7fU, 0xa9U, 0x19U, 0xb5U, 0x4aU, 0x0dU,\n\t0x2dU, 0xe5U, 0x7aU, 0x9fU, 0x93U, 0xc9U, 0x9cU, 0xefU,\n\t0xa0U, 0xe0U, 0x3bU, 0x4dU, 0xaeU, 0x2aU, 0xf5U, 0xb0U,\n\t0xc8U, 0xebU, 0xbbU, 0x3cU, 0x83U, 0x53U, 0x99U, 0x61U,\n\t0x17U, 0x2bU, 0x04U, 0x7eU, 0xbaU, 0x77U, 0xd6U, 0x26U,\n\t0xe1U, 0x69U, 0x14U, 0x63U, 0x55U, 0x21U, 0x0cU, 0x7dU,\n};\nconst u8 rcons[] = {\n\t0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1B, 0x36\n\t/* for 128-bit blocks, Rijndael never uses more than 10 rcon values */\n};\n\n/**\n * Expand the cipher key into the encryption key schedule.\n *\n * @return\tthe number of rounds for the given cipher key size.\n */\n#ifndef PLATFORM_FREEBSD /* Baron */\nstatic void rijndaelKeySetupEnc(u32 rk[/*44*/], const u8 cipherKey[])\n{\n\tint i;\n\tu32 temp;\n\n\trk[0] = GETU32(cipherKey);\n\trk[1] = GETU32(cipherKey +  4);\n\trk[2] = GETU32(cipherKey +  8);\n\trk[3] = GETU32(cipherKey + 12);\n\tfor (i = 0; i < 10; i++) {\n\t\ttemp  = rk[3];\n\t\trk[4] = rk[0] ^\n\t\t\tTE421(temp) ^ TE432(temp) ^ TE443(temp) ^ TE414(temp) ^\n\t\t\tRCON(i);\n\t\trk[5] = rk[1] ^ rk[4];\n\t\trk[6] = rk[2] ^ rk[5];\n\t\trk[7] = rk[3] ^ rk[6];\n\t\trk += 4;\n\t}\n}\n\nstatic void rijndaelEncrypt(u32 rk[/*44*/], u8 pt[16], u8 ct[16])\n{\n\tu32 s0, s1, s2, s3, t0, t1, t2, t3;\n\tint Nr = 10;\n#ifndef FULL_UNROLL\n\tint r;\n#endif /* ?FULL_UNROLL */\n\n\t/*\n\t * map byte array block to cipher state\n\t * and add initial round key:\n\t */\n\ts0 = GETU32(pt) ^ rk[0];\n\ts1 = GETU32(pt +  4) ^ rk[1];\n\ts2 = GETU32(pt +  8) ^ rk[2];\n\ts3 = GETU32(pt + 12) ^ rk[3];\n\n#define ROUND(i, d, s) do {\\\n\td##0 = TE0(s##0) ^ TE1(s##1) ^ TE2(s##2) ^ TE3(s##3) ^ rk[4 * i]; \\\n\td##1 = TE0(s##1) ^ TE1(s##2) ^ TE2(s##3) ^ TE3(s##0) ^ rk[4 * i + 1]; \\\n\td##2 = TE0(s##2) ^ TE1(s##3) ^ TE2(s##0) ^ TE3(s##1) ^ rk[4 * i + 2]; \\\n\td##3 = TE0(s##3) ^ TE1(s##0) ^ TE2(s##1) ^ TE3(s##2) ^ rk[4 * i + 3]; \\\n\t} while (0)\n\n#ifdef FULL_UNROLL\n\n\tROUND(1, t, s);\n\tROUND(2, s, t);\n\tROUND(3, t, s);\n\tROUND(4, s, t);\n\tROUND(5, t, s);\n\tROUND(6, s, t);\n\tROUND(7, t, s);\n\tROUND(8, s, t);\n\tROUND(9, t, s);\n\n\trk += Nr << 2;\n\n#else  /* !FULL_UNROLL */\n\n\t/* Nr - 1 full rounds: */\n\tr = Nr >> 1;\n\tfor (;;) {\n\t\tROUND(1, t, s);\n\t\trk += 8;\n\t\tif (--r == 0)\n\t\t\tbreak;\n\t\tROUND(0, s, t);\n\t}\n\n#endif /* ?FULL_UNROLL */\n\n#undef ROUND\n\n\t/*\n\t * apply last round and\n\t * map cipher state to byte array block:\n\t */\n\ts0 = TE41(t0) ^ TE42(t1) ^ TE43(t2) ^ TE44(t3) ^ rk[0];\n\tPUTU32(ct     , s0);\n\ts1 = TE41(t1) ^ TE42(t2) ^ TE43(t3) ^ TE44(t0) ^ rk[1];\n\tPUTU32(ct +  4, s1);\n\ts2 = TE41(t2) ^ TE42(t3) ^ TE43(t0) ^ TE44(t1) ^ rk[2];\n\tPUTU32(ct +  8, s2);\n\ts3 = TE41(t3) ^ TE42(t0) ^ TE43(t1) ^ TE44(t2) ^ rk[3];\n\tPUTU32(ct + 12, s3);\n}\n\nstatic void *aes_encrypt_init(const u8 *key, size_t len)\n{\n\tu32 *rk;\n\tif (len != 16)\n\t\treturn NULL;\n\trk = (u32 *)rtw_malloc(AES_PRIV_SIZE);\n\tif (rk == NULL)\n\t\treturn NULL;\n\trijndaelKeySetupEnc(rk, key);\n\treturn rk;\n}\n\nstatic void aes_128_encrypt(void *ctx, u8 *plain, u8 *crypt)\n{\n\trijndaelEncrypt(ctx, plain, crypt);\n}\n\n\nstatic void gf_mulx(u8 *pad)\n{\n\tint i, carry;\n\n\tcarry = pad[0] & 0x80;\n\tfor (i = 0; i < AES_BLOCK_SIZE - 1; i++)\n\t\tpad[i] = (pad[i] << 1) | (pad[i + 1] >> 7);\n\tpad[AES_BLOCK_SIZE - 1] <<= 1;\n\tif (carry)\n\t\tpad[AES_BLOCK_SIZE - 1] ^= 0x87;\n}\n\nstatic void aes_encrypt_deinit(void *ctx)\n{\n\t_rtw_memset(ctx, 0, AES_PRIV_SIZE);\n\trtw_mfree(ctx, AES_PRIV_SIZE);\n}\n\n\n/**\n * omac1_aes_128_vector - One-Key CBC MAC (OMAC1) hash with AES-128\n * @key: 128-bit key for the hash operation\n * @num_elem: Number of elements in the data vector\n * @addr: Pointers to the data areas\n * @len: Lengths of the data blocks\n * @mac: Buffer for MAC (128 bits, i.e., 16 bytes)\n * Returns: 0 on success, -1 on failure\n *\n * This is a mode for using block cipher (AES in this case) for authentication.\n * OMAC1 was standardized with the name CMAC by NIST in a Special Publication\n * (SP) 800-38B.\n */\nstatic int omac1_aes_128_vector(const u8 *key, size_t num_elem,\n\t\t\t const u8 *addr[], const size_t *len, u8 *mac)\n{\n\tvoid *ctx;\n\tu8 cbc[AES_BLOCK_SIZE], pad[AES_BLOCK_SIZE];\n\tconst u8 *pos, *end;\n\tsize_t i, e, left, total_len;\n\n\tctx = aes_encrypt_init(key, 16);\n\tif (ctx == NULL)\n\t\treturn -1;\n\t_rtw_memset(cbc, 0, AES_BLOCK_SIZE);\n\n\ttotal_len = 0;\n\tfor (e = 0; e < num_elem; e++)\n\t\ttotal_len += len[e];\n\tleft = total_len;\n\n\te = 0;\n\tpos = addr[0];\n\tend = pos + len[0];\n\n\twhile (left >= AES_BLOCK_SIZE) {\n\t\tfor (i = 0; i < AES_BLOCK_SIZE; i++) {\n\t\t\tcbc[i] ^= *pos++;\n\t\t\tif (pos >= end) {\n\t\t\t\te++;\n\t\t\t\tpos = addr[e];\n\t\t\t\tend = pos + len[e];\n\t\t\t}\n\t\t}\n\t\tif (left > AES_BLOCK_SIZE)\n\t\t\taes_128_encrypt(ctx, cbc, cbc);\n\t\tleft -= AES_BLOCK_SIZE;\n\t}\n\n\t_rtw_memset(pad, 0, AES_BLOCK_SIZE);\n\taes_128_encrypt(ctx, pad, pad);\n\tgf_mulx(pad);\n\n\tif (left || total_len == 0) {\n\t\tfor (i = 0; i < left; i++) {\n\t\t\tcbc[i] ^= *pos++;\n\t\t\tif (pos >= end) {\n\t\t\t\te++;\n\t\t\t\tpos = addr[e];\n\t\t\t\tend = pos + len[e];\n\t\t\t}\n\t\t}\n\t\tcbc[left] ^= 0x80;\n\t\tgf_mulx(pad);\n\t}\n\n\tfor (i = 0; i < AES_BLOCK_SIZE; i++)\n\t\tpad[i] ^= cbc[i];\n\taes_128_encrypt(ctx, pad, mac);\n\taes_encrypt_deinit(ctx);\n\treturn 0;\n}\n\n\n/**\n * omac1_aes_128 - One-Key CBC MAC (OMAC1) hash with AES-128 (aka AES-CMAC)\n * @key: 128-bit key for the hash operation\n * @data: Data buffer for which a MAC is determined\n * @data_len: Length of data buffer in bytes\n * @mac: Buffer for MAC (128 bits, i.e., 16 bytes)\n * Returns: 0 on success, -1 on failure\n *\n * This is a mode for using block cipher (AES in this case) for authentication.\n * OMAC1 was standardized with the name CMAC by NIST in a Special Publication\n * (SP) 800-38B.\n */ /* modify for CONFIG_IEEE80211W */\nint omac1_aes_128(const u8 *key, const u8 *data, size_t data_len, u8 *mac)\n{\n\treturn omac1_aes_128_vector(key, 1, &data, &data_len, mac);\n}\n#endif /* PLATFORM_FREEBSD Baron */\n\n#ifdef CONFIG_RTW_MESH_AEK\n/* for AES-SIV */\n#define os_memset _rtw_memset\n#define os_memcpy _rtw_memcpy\n#define os_malloc rtw_malloc\n#define bin_clear_free(bin, len) \\\n\tdo { \\\n\t\tif (bin) { \\\n\t\t\tos_memset(bin, 0, len); \\\n\t\t\trtw_mfree(bin, len); \\\n\t\t} \\\n\t} while (0)\n\nstatic const u8 zero[AES_BLOCK_SIZE];\n\nstatic void dbl(u8 *pad)\n{\n\tint i, carry;\n\n\tcarry = pad[0] & 0x80;\n\tfor (i = 0; i < AES_BLOCK_SIZE - 1; i++)\n\t\tpad[i] = (pad[i] << 1) | (pad[i + 1] >> 7);\n\tpad[AES_BLOCK_SIZE - 1] <<= 1;\n\tif (carry)\n\t\tpad[AES_BLOCK_SIZE - 1] ^= 0x87;\n}\n\nstatic void xor(u8 *a, const u8 *b)\n{\n\tint i;\n\n\tfor (i = 0; i < AES_BLOCK_SIZE; i++)\n\t\t*a++ ^= *b++;\n}\n\nstatic void xorend(u8 *a, int alen, const u8 *b, int blen)\n{\n\tint i;\n\n\tif (alen < blen)\n\t\treturn;\n\n\tfor (i = 0; i < blen; i++)\n\t\ta[alen - blen + i] ^= b[i];\n}\n\nstatic void pad_block(u8 *pad, const u8 *addr, size_t len)\n{\n\tos_memset(pad, 0, AES_BLOCK_SIZE);\n\tos_memcpy(pad, addr, len);\n\n\tif (len < AES_BLOCK_SIZE)\n\t\tpad[len] = 0x80;\n}\n\nstatic int aes_s2v(const u8 *key, size_t num_elem, const u8 *addr[],\n\t\t   size_t *len, u8 *mac)\n{\n\tu8 tmp[AES_BLOCK_SIZE], tmp2[AES_BLOCK_SIZE];\n\tu8 *buf = NULL;\n\tint ret;\n\tsize_t i;\n\n\tif (!num_elem) {\n\t\tos_memcpy(tmp, zero, sizeof(zero));\n\t\ttmp[AES_BLOCK_SIZE - 1] = 1;\n\t\treturn omac1_aes_128(key, tmp, sizeof(tmp), mac);\n\t}\n\n\tret = omac1_aes_128(key, zero, sizeof(zero), tmp);\n\tif (ret)\n\t\treturn ret;\n\n\tfor (i = 0; i < num_elem - 1; i++) {\n\t\tret = omac1_aes_128(key, addr[i], len[i], tmp2);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tdbl(tmp);\n\t\txor(tmp, tmp2);\n\t}\n\tif (len[i] >= AES_BLOCK_SIZE) {\n\t\tbuf = os_malloc(len[i]);\n\t\tif (!buf)\n\t\t\treturn -ENOMEM;\n\n\t\tos_memcpy(buf, addr[i], len[i]);\n\t\txorend(buf, len[i], tmp, AES_BLOCK_SIZE);\n\t\tret = omac1_aes_128(key, buf, len[i], mac);\n\t\tbin_clear_free(buf, len[i]);\n\t\treturn ret;\n\t}\n\n\tdbl(tmp);\n\tpad_block(tmp2, addr[i], len[i]);\n\txor(tmp, tmp2);\n\n\treturn omac1_aes_128(key, tmp, sizeof(tmp), mac);\n}\n\n/**\n * aes_128_ctr_encrypt - AES-128 CTR mode encryption\n * @key: Key for encryption (16 bytes)\n * @nonce: Nonce for counter mode (16 bytes)\n * @data: Data to encrypt in-place\n * @data_len: Length of data in bytes\n * Returns: 0 on success, -1 on failure\n */\nint aes_128_ctr_encrypt(const u8 *key, const u8 *nonce,\n\t\t\tu8 *data, size_t data_len)\n{\n\tvoid *ctx;\n\tsize_t j, len, left = data_len;\n\tint i;\n\tu8 *pos = data;\n\tu8 counter[AES_BLOCK_SIZE], buf[AES_BLOCK_SIZE];\n\n\tctx = aes_encrypt_init(key, 16);\n\tif (ctx == NULL)\n\t\treturn -1;\n\tos_memcpy(counter, nonce, AES_BLOCK_SIZE);\n\n\twhile (left > 0) {\n\t\t#if 0\n\t\taes_encrypt(ctx, counter, buf);\n\t\t#else\n\t\taes_128_encrypt(ctx, counter, buf);\n\t\t#endif\n\n\t\tlen = (left < AES_BLOCK_SIZE) ? left : AES_BLOCK_SIZE;\n\t\tfor (j = 0; j < len; j++)\n\t\t\tpos[j] ^= buf[j];\n\t\tpos += len;\n\t\tleft -= len;\n\n\t\tfor (i = AES_BLOCK_SIZE - 1; i >= 0; i--) {\n\t\t\tcounter[i]++;\n\t\t\tif (counter[i])\n\t\t\t\tbreak;\n\t\t}\n\t}\n\taes_encrypt_deinit(ctx);\n\treturn 0;\n}\n\nint aes_siv_encrypt(const u8 *key, const u8 *pw,\n\t\t    size_t pwlen, size_t num_elem,\n\t\t    const u8 *addr[], const size_t *len, u8 *out)\n{\n\tconst u8 *_addr[6];\n\tsize_t _len[6];\n\tconst u8 *k1 = key, *k2 = key + 16;\n\tu8 v[AES_BLOCK_SIZE];\n\tsize_t i;\n\tu8 *iv, *crypt_pw;\n\n\tif (num_elem > ARRAY_SIZE(_addr) - 1)\n\t\treturn -1;\n\n\tfor (i = 0; i < num_elem; i++) {\n\t\t_addr[i] = addr[i];\n\t\t_len[i] = len[i];\n\t}\n\t_addr[num_elem] = pw;\n\t_len[num_elem] = pwlen;\n\n\tif (aes_s2v(k1, num_elem + 1, _addr, _len, v))\n\t\treturn -1;\n\n\tiv = out;\n\tcrypt_pw = out + AES_BLOCK_SIZE;\n\n\tos_memcpy(iv, v, AES_BLOCK_SIZE);\n\tos_memcpy(crypt_pw, pw, pwlen);\n\n\t/* zero out 63rd and 31st bits of ctr (from right) */\n\tv[8] &= 0x7f;\n\tv[12] &= 0x7f;\n\treturn aes_128_ctr_encrypt(k2, v, crypt_pw, pwlen);\n}\n\nint aes_siv_decrypt(const u8 *key, const u8 *iv_crypt, size_t iv_c_len,\n\t\t    size_t num_elem, const u8 *addr[], const size_t *len,\n\t\t    u8 *out)\n{\n\tconst u8 *_addr[6];\n\tsize_t _len[6];\n\tconst u8 *k1 = key, *k2 = key + 16;\n\tsize_t crypt_len;\n\tsize_t i;\n\tint ret;\n\tu8 iv[AES_BLOCK_SIZE];\n\tu8 check[AES_BLOCK_SIZE];\n\n\tif (iv_c_len < AES_BLOCK_SIZE || num_elem > ARRAY_SIZE(_addr) - 1)\n\t\treturn -1;\n\tcrypt_len = iv_c_len - AES_BLOCK_SIZE;\n\n\tfor (i = 0; i < num_elem; i++) {\n\t\t_addr[i] = addr[i];\n\t\t_len[i] = len[i];\n\t}\n\t_addr[num_elem] = out;\n\t_len[num_elem] = crypt_len;\n\n\tos_memcpy(iv, iv_crypt, AES_BLOCK_SIZE);\n\tos_memcpy(out, iv_crypt + AES_BLOCK_SIZE, crypt_len);\n\n\tiv[8] &= 0x7f;\n\tiv[12] &= 0x7f;\n\n\tret = aes_128_ctr_encrypt(k2, iv, out, crypt_len);\n\tif (ret)\n\t\treturn ret;\n\n\tret = aes_s2v(k1, num_elem + 1, _addr, _len, check);\n\tif (ret)\n\t\treturn ret;\n\tif (os_memcmp(check, iv_crypt, AES_BLOCK_SIZE) == 0)\n\t\treturn 0;\n\n\treturn -1;\n}\n#endif /* CONFIG_RTW_MESH_AEK */\n\n#ifdef CONFIG_TDLS\nvoid wpa_tdls_generate_tpk(_adapter *padapter, void *sta)\n{\n\tstruct sta_info *psta = (struct sta_info *)sta;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tu8 *SNonce = psta->SNonce;\n\tu8 *ANonce = psta->ANonce;\n\n\tu8 key_input[SHA256_MAC_LEN];\n\tu8 *nonce[2];\n\tsize_t len[2];\n\tu8 data[3 * ETH_ALEN];\n\n\t/* IEEE Std 802.11z-2010 8.5.9.1:\n\t * TPK-Key-Input = SHA-256(min(SNonce, ANonce) || max(SNonce, ANonce))\n\t */\n\tlen[0] = 32;\n\tlen[1] = 32;\n\tif (os_memcmp(SNonce, ANonce, 32) < 0) {\n\t\tnonce[0] = SNonce;\n\t\tnonce[1] = ANonce;\n\t} else {\n\t\tnonce[0] = ANonce;\n\t\tnonce[1] = SNonce;\n\t}\n\n\tsha256_vector(2, nonce, len, key_input);\n\n\t/*\n\t * TPK-Key-Data = KDF-N_KEY(TPK-Key-Input, \"TDLS PMK\",\n\t *\tmin(MAC_I, MAC_R) || max(MAC_I, MAC_R) || BSSID || N_KEY)\n\t * TODO: is N_KEY really included in KDF Context and if so, in which\n\t * presentation format (little endian 16-bit?) is it used? It gets\n\t * added by the KDF anyway..\n\t */\n\n\tif (os_memcmp(adapter_mac_addr(padapter), psta->cmn.mac_addr, ETH_ALEN) < 0) {\n\t\t_rtw_memcpy(data, adapter_mac_addr(padapter), ETH_ALEN);\n\t\t_rtw_memcpy(data + ETH_ALEN, psta->cmn.mac_addr, ETH_ALEN);\n\t} else {\n\t\t_rtw_memcpy(data, psta->cmn.mac_addr, ETH_ALEN);\n\t\t_rtw_memcpy(data + ETH_ALEN, adapter_mac_addr(padapter), ETH_ALEN);\n\t}\n\t_rtw_memcpy(data + 2 * ETH_ALEN, get_bssid(pmlmepriv), ETH_ALEN);\n\n\tsha256_prf(key_input, SHA256_MAC_LEN, \"TDLS PMK\", data, sizeof(data), (u8 *) &psta->tpk, sizeof(psta->tpk));\n\n\n}\n\n/**\n * wpa_tdls_ftie_mic - Calculate TDLS FTIE MIC\n * @kck: TPK-KCK\n * @lnkid: Pointer to the beginning of Link Identifier IE\n * @rsnie: Pointer to the beginning of RSN IE used for handshake\n * @timeoutie: Pointer to the beginning of Timeout IE used for handshake\n * @ftie: Pointer to the beginning of FT IE\n * @mic: Pointer for writing MIC\n *\n * Calculate MIC for TDLS frame.\n */\nint wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq,\n\t\t      u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie,\n\t\t      u8 *mic)\n{\n\tu8 *buf, *pos;\n\tstruct wpa_tdls_ftie *_ftie;\n\tstruct wpa_tdls_lnkid *_lnkid;\n\tint ret;\n\tint len = 2 * ETH_ALEN + 1 + 2 + lnkid[1] + 2 + rsnie[1] +\n\t\t  2 + timeoutie[1] + 2 + ftie[1];\n\tbuf = rtw_zmalloc(len);\n\tif (!buf) {\n\t\tRTW_INFO(\"TDLS: No memory for MIC calculation\\n\");\n\t\treturn -1;\n\t}\n\n\tpos = buf;\n\t_lnkid = (struct wpa_tdls_lnkid *) lnkid;\n\t/* 1) TDLS initiator STA MAC address */\n\t_rtw_memcpy(pos, _lnkid->init_sta, ETH_ALEN);\n\tpos += ETH_ALEN;\n\t/* 2) TDLS responder STA MAC address */\n\t_rtw_memcpy(pos, _lnkid->resp_sta, ETH_ALEN);\n\tpos += ETH_ALEN;\n\t/* 3) Transaction Sequence number */\n\t*pos++ = trans_seq;\n\t/* 4) Link Identifier IE */\n\t_rtw_memcpy(pos, lnkid, 2 + lnkid[1]);\n\tpos += 2 + lnkid[1];\n\t/* 5) RSN IE */\n\t_rtw_memcpy(pos, rsnie, 2 + rsnie[1]);\n\tpos += 2 + rsnie[1];\n\t/* 6) Timeout Interval IE */\n\t_rtw_memcpy(pos, timeoutie, 2 + timeoutie[1]);\n\tpos += 2 + timeoutie[1];\n\t/* 7) FTIE, with the MIC field of the FTIE set to 0 */\n\t_rtw_memcpy(pos, ftie, 2 + ftie[1]);\n\t_ftie = (struct wpa_tdls_ftie *) pos;\n\t_rtw_memset(_ftie->mic, 0, TDLS_MIC_LEN);\n\tpos += 2 + ftie[1];\n\n\tret = omac1_aes_128(kck, buf, pos - buf, mic);\n\trtw_mfree(buf, len);\n\treturn ret;\n\n}\n\n/**\n * wpa_tdls_teardown_ftie_mic - Calculate TDLS TEARDOWN FTIE MIC\n * @kck: TPK-KCK\n * @lnkid: Pointer to the beginning of Link Identifier IE\n * @reason: Reason code of TDLS Teardown\n * @dialog_token: Dialog token that was used in the MIC calculation for TPK Handshake Message 3\n * @trans_seq: Transaction Sequence number (1 octet) which shall be set to the value 4\n * @ftie: Pointer to the beginning of FT IE\n * @mic: Pointer for writing MIC\n *\n * Calculate MIC for TDLS TEARDOWN frame according to Section 10.22.5 in IEEE 802.11 - 2012.\n */\nint wpa_tdls_teardown_ftie_mic(u8 *kck, u8 *lnkid, u16 reason,\n\t\t\t       u8 dialog_token, u8 trans_seq, u8 *ftie, u8 *mic)\n{\n\tu8 *buf, *pos;\n\tstruct wpa_tdls_ftie *_ftie;\n\tint ret;\n\tint len = 2 + lnkid[1] + 2 + 1 + 1 + 2 + ftie[1];\n\n\tbuf = rtw_zmalloc(len);\n\tif (!buf) {\n\t\tRTW_INFO(\"TDLS: No memory for MIC calculation\\n\");\n\t\treturn -1;\n\t}\n\n\tpos = buf;\n\t/* 1) Link Identifier IE */\n\t_rtw_memcpy(pos, lnkid, 2 + lnkid[1]);\n\tpos += 2 + lnkid[1];\n\t/* 2) Reason Code */\n\t_rtw_memcpy(pos, (u8 *)&reason, 2);\n\tpos += 2;\n\t/* 3) Dialog Token */\n\t*pos++ = dialog_token;\n\t/* 4) Transaction Sequence number */\n\t*pos++ = trans_seq;\n\t/* 5) FTIE, with the MIC field of the FTIE set to 0 */\n\t_rtw_memcpy(pos, ftie, 2 + ftie[1]);\n\t_ftie = (struct wpa_tdls_ftie *) pos;\n\t_rtw_memset(_ftie->mic, 0, TDLS_MIC_LEN);\n\tpos += 2 + ftie[1];\n\n\tret = omac1_aes_128(kck, buf, pos - buf, mic);\n\trtw_mfree(buf, len);\n\treturn ret;\n\n}\n\nint tdls_verify_mic(u8 *kck, u8 trans_seq,\n\t\t    u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie)\n{\n\tu8 *buf, *pos;\n\tint len;\n\tu8 mic[16];\n\tint ret;\n\tu8 *rx_ftie, *tmp_ftie;\n\n\tif (lnkid == NULL || rsnie == NULL ||\n\t    timeoutie == NULL || ftie == NULL)\n\t\treturn _FAIL;\n\n\tlen = 2 * ETH_ALEN + 1 + 2 + 18 + 2 + *(rsnie + 1) + 2 + *(timeoutie + 1) + 2 + *(ftie + 1);\n\n\tbuf = rtw_zmalloc(len);\n\tif (buf == NULL)\n\t\treturn _FAIL;\n\n\tpos = buf;\n\t/* 1) TDLS initiator STA MAC address */\n\t_rtw_memcpy(pos, lnkid + ETH_ALEN + 2, ETH_ALEN);\n\tpos += ETH_ALEN;\n\t/* 2) TDLS responder STA MAC address */\n\t_rtw_memcpy(pos, lnkid + 2 * ETH_ALEN + 2, ETH_ALEN);\n\tpos += ETH_ALEN;\n\t/* 3) Transaction Sequence number */\n\t*pos++ = trans_seq;\n\t/* 4) Link Identifier IE */\n\t_rtw_memcpy(pos, lnkid, 2 + 18);\n\tpos += 2 + 18;\n\t/* 5) RSN IE */\n\t_rtw_memcpy(pos, rsnie, 2 + *(rsnie + 1));\n\tpos += 2 + *(rsnie + 1);\n\t/* 6) Timeout Interval IE */\n\t_rtw_memcpy(pos, timeoutie, 2 + *(timeoutie + 1));\n\tpos += 2 + *(timeoutie + 1);\n\t/* 7) FTIE, with the MIC field of the FTIE set to 0 */\n\t_rtw_memcpy(pos, ftie, 2 + *(ftie + 1));\n\tpos += 2;\n\ttmp_ftie = (u8 *)(pos + 2);\n\t_rtw_memset(tmp_ftie, 0, 16);\n\tpos += *(ftie + 1);\n\n\tret = omac1_aes_128(kck, buf, pos - buf, mic);\n\trtw_mfree(buf, len);\n\tif (ret)\n\t\treturn _FAIL;\n\trx_ftie = ftie + 4;\n\n\tif (os_memcmp(mic, rx_ftie, 16) == 0) {\n\t\t/* Valid MIC */\n\t\treturn _SUCCESS;\n\t}\n\n\t/* Invalid MIC */\n\tRTW_INFO(\"[%s] Invalid MIC\\n\", __FUNCTION__);\n\treturn _FAIL;\n\n}\n#endif /* CONFIG_TDLS */\n\n/* Restore HW wep key setting according to key_mask */\nvoid rtw_sec_restore_wep_key(_adapter *adapter)\n{\n\tstruct security_priv *securitypriv = &(adapter->securitypriv);\n\tsint keyid;\n\n\tif ((_WEP40_ == securitypriv->dot11PrivacyAlgrthm) || (_WEP104_ == securitypriv->dot11PrivacyAlgrthm)) {\n\t\tfor (keyid = 0; keyid < 4; keyid++) {\n\t\t\tif (securitypriv->key_mask & BIT(keyid)) {\n\t\t\t\tif (keyid == securitypriv->dot11PrivacyKeyIndex)\n\t\t\t\t\trtw_set_key(adapter, securitypriv, keyid, 1, _FALSE);\n\t\t\t\telse\n\t\t\t\t\trtw_set_key(adapter, securitypriv, keyid, 0, _FALSE);\n\t\t\t}\n\t\t}\n\t}\n}\n\nu8 rtw_handle_tkip_countermeasure(_adapter *adapter, const char *caller)\n{\n\tstruct security_priv *securitypriv = &(adapter->securitypriv);\n\tu8 status = _SUCCESS;\n\n\tif (securitypriv->btkip_countermeasure == _TRUE) {\n\t\tu32 passing_ms = rtw_get_passing_time_ms(securitypriv->btkip_countermeasure_time);\n\t\tif (passing_ms > 60 * 1000) {\n\t\t\tRTW_PRINT(\"%s(\"ADPT_FMT\") countermeasure time:%ds > 60s\\n\",\n\t\t\t\t  caller, ADPT_ARG(adapter), passing_ms / 1000);\n\t\t\tsecuritypriv->btkip_countermeasure = _FALSE;\n\t\t\tsecuritypriv->btkip_countermeasure_time = 0;\n\t\t} else {\n\t\t\tRTW_PRINT(\"%s(\"ADPT_FMT\") countermeasure time:%ds < 60s\\n\",\n\t\t\t\t  caller, ADPT_ARG(adapter), passing_ms / 1000);\n\t\t\tstatus = _FAIL;\n\t\t}\n\t}\n\n\treturn status;\n}\n\n#ifdef CONFIG_WOWLAN\nu16 rtw_cal_crc16(u8 data, u16 crc)\n{\n\tu8 shift_in, data_bit;\n\tu8 crc_bit4, crc_bit11, crc_bit15;\n\tu16 crc_result;\n\tint index;\n\n\tfor (index = 0; index < 8; index++) {\n\t\tcrc_bit15 = ((crc & BIT15) ? 1 : 0);\n\t\tdata_bit = (data & (BIT0 << index) ? 1 : 0);\n\t\tshift_in = crc_bit15 ^ data_bit;\n\t\t/*printf(\"crc_bit15=%d, DataBit=%d, shift_in=%d\\n\",\n\t\t * crc_bit15, data_bit, shift_in);*/\n\n\t\tcrc_result = crc << 1;\n\n\t\tif (shift_in == 0)\n\t\t\tcrc_result &= (~BIT0);\n\t\telse\n\t\t\tcrc_result |= BIT0;\n\t\t/*printf(\"CRC =%x\\n\",CRC_Result);*/\n\n\t\tcrc_bit11 = ((crc & BIT11) ? 1 : 0) ^ shift_in;\n\n\t\tif (crc_bit11 == 0)\n\t\t\tcrc_result &= (~BIT12);\n\t\telse\n\t\t\tcrc_result |= BIT12;\n\n\t\t/*printf(\"bit12 CRC =%x\\n\",CRC_Result);*/\n\n\t\tcrc_bit4 = ((crc & BIT4) ? 1 : 0) ^ shift_in;\n\n\t\tif (crc_bit4 == 0)\n\t\t\tcrc_result &= (~BIT5);\n\t\telse\n\t\t\tcrc_result |= BIT5;\n\n\t\t/* printf(\"bit5 CRC =%x\\n\",CRC_Result); */\n\t\t/* repeat using the last result*/\n\t\tcrc = crc_result;\n\t}\n\treturn crc;\n}\n\n/*\n * function name :rtw_calc_crc\n *\n * input: char* pattern , pattern size\n *\n */\nu16 rtw_calc_crc(u8  *pdata, int length)\n{\n\tu16 crc = 0xffff;\n\tint i;\n\n\tfor (i = 0; i < length; i++)\n\t\tcrc = rtw_cal_crc16(pdata[i], crc);\n\t/* get 1' complement */\n\tcrc = ~crc;\n\n\treturn crc;\n}\n#endif /*CONFIG_WOWLAN*/\n"
  },
  {
    "path": "core/rtw_sreset.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include <drv_types.h>\n#include <hal_data.h>\n#include <rtw_sreset.h>\n\nvoid sreset_init_value(_adapter *padapter)\n{\n#if defined(DBG_CONFIG_ERROR_DETECT)\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct sreset_priv *psrtpriv = &pHalData->srestpriv;\n\n\t_rtw_mutex_init(&psrtpriv->silentreset_mutex);\n\tpsrtpriv->silent_reset_inprogress = _FALSE;\n\tpsrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;\n\tpsrtpriv->last_tx_time = 0;\n\tpsrtpriv->last_tx_complete_time = 0;\n#endif\n}\nvoid sreset_reset_value(_adapter *padapter)\n{\n#if defined(DBG_CONFIG_ERROR_DETECT)\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct sreset_priv *psrtpriv = &pHalData->srestpriv;\n\n\tpsrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;\n\tpsrtpriv->last_tx_time = 0;\n\tpsrtpriv->last_tx_complete_time = 0;\n#endif\n}\n\nu8 sreset_get_wifi_status(_adapter *padapter)\n{\n#if defined(DBG_CONFIG_ERROR_DETECT)\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct sreset_priv *psrtpriv = &pHalData->srestpriv;\n\tu8 status = WIFI_STATUS_SUCCESS;\n\tu32 val32 = 0;\n\n\tif (psrtpriv->silent_reset_inprogress == _TRUE)\n\t\treturn status;\n\tval32 = rtw_read32(padapter, REG_TXDMA_STATUS);\n\tif (val32 == 0xeaeaeaea)\n\t\tpsrtpriv->Wifi_Error_Status = WIFI_IF_NOT_EXIST;\n\telse if (val32 != 0) {\n\t\tRTW_INFO(\"txdmastatu(%x)\\n\", val32);\n\t\tpsrtpriv->Wifi_Error_Status = WIFI_MAC_TXDMA_ERROR;\n\t}\n\n\tif (WIFI_STATUS_SUCCESS != psrtpriv->Wifi_Error_Status) {\n\t\tRTW_INFO(\"==>%s error_status(0x%x)\\n\", __FUNCTION__, psrtpriv->Wifi_Error_Status);\n\t\tstatus = (psrtpriv->Wifi_Error_Status & (~(USB_READ_PORT_FAIL | USB_WRITE_PORT_FAIL)));\n\t}\n\tRTW_INFO(\"==> %s wifi_status(0x%x)\\n\", __FUNCTION__, status);\n\n\t/* status restore */\n\tpsrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;\n\n\treturn status;\n#else\n\treturn WIFI_STATUS_SUCCESS;\n#endif\n}\n\nvoid sreset_set_wifi_error_status(_adapter *padapter, u32 status)\n{\n#if defined(DBG_CONFIG_ERROR_DETECT)\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tpHalData->srestpriv.Wifi_Error_Status = status;\n#endif\n}\n\nvoid sreset_set_trigger_point(_adapter *padapter, s32 tgp)\n{\n#if defined(DBG_CONFIG_ERROR_DETECT)\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tpHalData->srestpriv.dbg_trigger_point = tgp;\n#endif\n}\n\nbool sreset_inprogress(_adapter *padapter)\n{\n#if defined(DBG_CONFIG_ERROR_RESET)\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\treturn pHalData->srestpriv.silent_reset_inprogress;\n#else\n\treturn _FALSE;\n#endif\n}\n\nvoid sreset_restore_security_station(_adapter *padapter)\n{\n\tstruct mlme_priv *mlmepriv = &padapter->mlmepriv;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct sta_info *psta;\n\tstruct mlme_ext_info\t*pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;\n\n\t{\n\t\tu8 val8;\n\n\t\tif (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) {\n\t\t\tval8 = 0xcc;\n#ifdef CONFIG_WAPI_SUPPORT\n\t\t} else if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) {\n\t\t\t/* Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey. */\n\t\t\tval8 = 0x4c;\n#endif\n\t\t} else\n\t\t\tval8 = 0xcf;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));\n\t}\n\n\tif ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||\n\t    (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) {\n\t\tpsta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv));\n\t\tif (psta == NULL) {\n\t\t\t/* DEBUG_ERR( (\"Set wpa_set_encryption: Obtain Sta_info fail\\n\")); */\n\t\t} else {\n\t\t\t/* pairwise key */\n\t\t\trtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _FALSE);\n\t\t\t/* group key */\n\t\t\trtw_set_key(padapter, &padapter->securitypriv, padapter->securitypriv.dot118021XGrpKeyid, 0, _FALSE);\n\t\t}\n\t}\n}\n\nvoid sreset_restore_network_station(_adapter *padapter)\n{\n\tstruct mlme_priv *mlmepriv = &padapter->mlmepriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8 doiqk = _FALSE;\n\n\trtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, RTW_CMDF_DIRECTLY);\n\n\t{\n\t\tu8 threshold;\n#ifdef CONFIG_USB_HCI\n\t\t/* TH=1 => means that invalidate usb rx aggregation */\n\t\t/* TH=0 => means that validate usb rx aggregation, use init value. */\n#ifdef CONFIG_80211N_HT\n\t\tif (mlmepriv->htpriv.ht_option) {\n\t\t\tif (padapter->registrypriv.wifi_spec == 1)\n\t\t\t\tthreshold = 1;\n\t\t\telse\n\t\t\t\tthreshold = 0;\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));\n\t\t} else {\n\t\t\tthreshold = 1;\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));\n\t\t}\n#endif /* CONFIG_80211N_HT */\n#endif\n\t}\n\n\tdoiqk = _TRUE;\n\trtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK , &doiqk);\n\n\tset_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);\n\n\tdoiqk = _FALSE;\n\trtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);\n\t/* disable dynamic functions, such as high power, DIG */\n\t/*rtw_phydm_func_disable_all(padapter);*/\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);\n\n\t{\n\t\tu8\tjoin_type = 0;\n\n\t\trtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTING);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));\n\t}\n\n\tSet_MSR(padapter, (pmlmeinfo->state & 0x3));\n\n\tmlmeext_joinbss_event_callback(padapter, 1);\n\t/* restore Sequence No. */\n\trtw_hal_set_hwreg(padapter, HW_VAR_RESTORE_HW_SEQ, 0);\n\n\tsreset_restore_security_station(padapter);\n}\n\n\nvoid sreset_restore_network_status(_adapter *padapter)\n{\n\tstruct mlme_priv *mlmepriv = &padapter->mlmepriv;\n\n\tif (check_fwstate(mlmepriv, WIFI_STATION_STATE)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" fwstate:0x%08x - WIFI_STATION_STATE\\n\", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));\n\t\tsreset_restore_network_station(padapter);\n\t} else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" %s\\n\", FUNC_ADPT_ARG(padapter), MLME_IS_AP(padapter) ? \"AP\" : \"MESH\");\n\t\trtw_ap_restore_network(padapter);\n\t} else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE))\n\t\tRTW_INFO(FUNC_ADPT_FMT\" fwstate:0x%08x - WIFI_ADHOC_STATE\\n\", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));\n\telse\n\t\tRTW_INFO(FUNC_ADPT_FMT\" fwstate:0x%08x - ???\\n\", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));\n}\n\nvoid sreset_stop_adapter(_adapter *padapter)\n{\n\tstruct mlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tstruct xmit_priv\t*pxmitpriv = &padapter->xmitpriv;\n\n\tif (padapter == NULL)\n\t\treturn;\n\n\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n\n\trtw_netif_stop_queue(padapter->pnetdev);\n\n\trtw_cancel_all_timer(padapter);\n\n\t/* TODO: OS and HCI independent */\n#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)\n\ttasklet_kill(&pxmitpriv->xmit_tasklet);\n#endif\n\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))\n\t\trtw_scan_abort(padapter);\n\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) {\n\t\trtw_set_to_roam(padapter, 0);\n\t\trtw_join_timeout_handler(padapter);\n\t}\n\n}\n\nvoid sreset_start_adapter(_adapter *padapter)\n{\n\tstruct mlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tstruct xmit_priv\t*pxmitpriv = &padapter->xmitpriv;\n\n\tif (padapter == NULL)\n\t\treturn;\n\n\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n\n\tif (check_fwstate(pmlmepriv, _FW_LINKED))\n\t\tsreset_restore_network_status(padapter);\n\n\t/* TODO: OS and HCI independent */\n#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)\n\ttasklet_hi_schedule(&pxmitpriv->xmit_tasklet);\n#endif\n\n\tif (is_primary_adapter(padapter))\n\t\t_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);\n\n\trtw_netif_wake_queue(padapter->pnetdev);\n}\n\nvoid sreset_reset(_adapter *padapter)\n{\n#ifdef DBG_CONFIG_ERROR_RESET\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct sreset_priv *psrtpriv = &pHalData->srestpriv;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tstruct mlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tstruct xmit_priv\t*pxmitpriv = &padapter->xmitpriv;\n\t_irqL irqL;\n\tsystime start = rtw_get_current_time();\n\tstruct dvobj_priv *psdpriv = padapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &psdpriv->drv_dbg;\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\tpsrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;\n\n\n#ifdef CONFIG_LPS\n\trtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, \"SRESET\");\n#endif/* #ifdef CONFIG_LPS */\n\n\t_enter_pwrlock(&pwrpriv->lock);\n\n\tpsrtpriv->silent_reset_inprogress = _TRUE;\n\tpwrpriv->change_rfpwrstate = rf_off;\n\n\trtw_mi_sreset_adapter_hdl(padapter, _FALSE);/*sreset_stop_adapter*/\n#ifdef CONFIG_IPS\n\t_ips_enter(padapter);\n\t_ips_leave(padapter);\n#endif\n\trtw_mi_sreset_adapter_hdl(padapter, _TRUE);/*sreset_start_adapter*/\n\n\tpsrtpriv->silent_reset_inprogress = _FALSE;\n\n\t_exit_pwrlock(&pwrpriv->lock);\n\n\tRTW_INFO(\"%s done in %d ms\\n\", __FUNCTION__, rtw_get_passing_time_ms(start));\n\tpdbgpriv->dbg_sreset_cnt++;\n\n\tpsrtpriv->self_dect_fw = _FALSE;\n\tpsrtpriv->rx_cnt = 0;\n#endif\n}\n"
  },
  {
    "path": "core/rtw_sta_mgt.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2019 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_STA_MGT_C_\n\n#include <drv_types.h>\n\nbool test_st_match_rule(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)\n{\n\tif (ntohs(*((u16 *)local_port)) == 5001 || ntohs(*((u16 *)remote_port)) == 5001)\n\t\treturn _TRUE;\n\treturn _FALSE;\n}\n\nstruct st_register test_st_reg = {\n\t.s_proto = 0x06,\n\t.rule = test_st_match_rule,\n};\n\ninline void rtw_st_ctl_init(struct st_ctl_t *st_ctl)\n{\n\t_rtw_memset(st_ctl->reg, 0 , sizeof(struct st_register) * SESSION_TRACKER_REG_ID_NUM);\n\t_rtw_init_queue(&st_ctl->tracker_q);\n}\n\ninline void rtw_st_ctl_clear_tracker_q(struct st_ctl_t *st_ctl)\n{\n\t_irqL irqL;\n\t_list *plist, *phead;\n\tstruct session_tracker *st;\n\n\t_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);\n\tphead = &st_ctl->tracker_q.queue;\n\tplist = get_next(phead);\n\twhile (rtw_end_of_queue_search(phead, plist) == _FALSE) {\n\t\tst = LIST_CONTAINOR(plist, struct session_tracker, list);\n\t\tplist = get_next(plist);\n\t\trtw_list_delete(&st->list);\n\t\trtw_mfree((u8 *)st, sizeof(struct session_tracker));\n\t}\n\t_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);\n}\n\ninline void rtw_st_ctl_deinit(struct st_ctl_t *st_ctl)\n{\n\trtw_st_ctl_clear_tracker_q(st_ctl);\n\t_rtw_deinit_queue(&st_ctl->tracker_q);\n}\n\ninline void rtw_st_ctl_register(struct st_ctl_t *st_ctl, u8 st_reg_id, struct st_register *reg)\n{\n\tif (st_reg_id >= SESSION_TRACKER_REG_ID_NUM) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tst_ctl->reg[st_reg_id].s_proto = reg->s_proto;\n\tst_ctl->reg[st_reg_id].rule = reg->rule;\n}\n\ninline void rtw_st_ctl_unregister(struct st_ctl_t *st_ctl, u8 st_reg_id)\n{\n\tint i;\n\n\tif (st_reg_id >= SESSION_TRACKER_REG_ID_NUM) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tst_ctl->reg[st_reg_id].s_proto = 0;\n\tst_ctl->reg[st_reg_id].rule = NULL;\n\n\t/* clear tracker queue if no session trecker registered */\n\tfor (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++)\n\t\tif (st_ctl->reg[i].s_proto != 0)\n\t\t\tbreak;\n\tif (i >= SESSION_TRACKER_REG_ID_NUM)\n\t\trtw_st_ctl_clear_tracker_q(st_ctl);\n}\n\ninline bool rtw_st_ctl_chk_reg_s_proto(struct st_ctl_t *st_ctl, u8 s_proto)\n{\n\tbool ret = _FALSE;\n\tint i;\n\n\tfor (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) {\n\t\tif (st_ctl->reg[i].s_proto == s_proto) {\n\t\t\tret = _TRUE;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn ret;\n}\n\ninline bool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)\n{\n\tbool ret = _FALSE;\n\tint i;\n\tst_match_rule rule;\n\n\tfor (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) {\n\t\trule = st_ctl->reg[i].rule;\n\t\tif (rule && rule(adapter, local_naddr, local_port, remote_naddr, remote_port) == _TRUE) {\n\t\t\tret = _TRUE;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn ret;\n}\n\nvoid rtw_st_ctl_rx(struct sta_info *sta, u8 *ehdr_pos)\n{\n\t_adapter *adapter = sta->padapter;\n\tstruct ethhdr *etherhdr = (struct ethhdr *)ehdr_pos;\n\n\tif (ntohs(etherhdr->h_proto) == ETH_P_IP) {\n\t\tu8 *ip = ehdr_pos + ETH_HLEN;\n\n\t\tif (GET_IPV4_PROTOCOL(ip) == 0x06  /* TCP */\n\t\t\t&& rtw_st_ctl_chk_reg_s_proto(&sta->st_ctl, 0x06) == _TRUE\n\t\t) {\n\t\t\tu8 *tcp = ip + GET_IPV4_IHL(ip) * 4;\n\n\t\t\tif (rtw_st_ctl_chk_reg_rule(&sta->st_ctl, adapter, IPV4_DST(ip), TCP_DST(tcp), IPV4_SRC(ip), TCP_SRC(tcp)) == _TRUE) {\n\t\t\t\tif (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) {\n\t\t\t\t\tsession_tracker_add_cmd(adapter, sta\n\t\t\t\t\t\t, IPV4_DST(ip), TCP_DST(tcp)\n\t\t\t\t\t\t, IPV4_SRC(ip), TCP_SRC(tcp));\n\t\t\t\t\tif (DBG_SESSION_TRACKER)\n\t\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" local:\"IP_FMT\":\"PORT_FMT\", remote:\"IP_FMT\":\"PORT_FMT\" SYN-ACK\\n\"\n\t\t\t\t\t\t\t, FUNC_ADPT_ARG(adapter)\n\t\t\t\t\t\t\t, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp))\n\t\t\t\t\t\t\t, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp)));\n\t\t\t\t}\n\t\t\t\tif (GET_TCP_FIN(tcp)) {\n\t\t\t\t\tsession_tracker_del_cmd(adapter, sta\n\t\t\t\t\t\t, IPV4_DST(ip), TCP_DST(tcp)\n\t\t\t\t\t\t, IPV4_SRC(ip), TCP_SRC(tcp));\n\t\t\t\t\tif (DBG_SESSION_TRACKER)\n\t\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" local:\"IP_FMT\":\"PORT_FMT\", remote:\"IP_FMT\":\"PORT_FMT\" FIN\\n\"\n\t\t\t\t\t\t\t, FUNC_ADPT_ARG(adapter)\n\t\t\t\t\t\t\t, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp))\n\t\t\t\t\t\t\t, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp)));\n\t\t\t\t}\n\t\t\t}\n\n\t\t}\n\t}\n}\n\n#define SESSION_TRACKER_FMT IP_FMT\":\"PORT_FMT\" \"IP_FMT\":\"PORT_FMT\" %u %d\"\n#define SESSION_TRACKER_ARG(st) IP_ARG(&(st)->local_naddr), PORT_ARG(&(st)->local_port), IP_ARG(&(st)->remote_naddr), PORT_ARG(&(st)->remote_port), (st)->status, rtw_get_passing_time_ms((st)->set_time)\n\nvoid dump_st_ctl(void *sel, struct st_ctl_t *st_ctl)\n{\n\tint i;\n\t_irqL irqL;\n\t_list *plist, *phead;\n\tstruct session_tracker *st;\n\n\tif (!DBG_SESSION_TRACKER)\n\t\treturn;\n\n\tfor (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++)\n\t\tRTW_PRINT_SEL(sel, \"reg%d: %u %p\\n\", i, st_ctl->reg[i].s_proto, st_ctl->reg[i].rule);\n\n\t_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);\n\tphead = &st_ctl->tracker_q.queue;\n\tplist = get_next(phead);\n\twhile (rtw_end_of_queue_search(phead, plist) == _FALSE) {\n\t\tst = LIST_CONTAINOR(plist, struct session_tracker, list);\n\t\tplist = get_next(plist);\n\n\t\tRTW_PRINT_SEL(sel, SESSION_TRACKER_FMT\"\\n\", SESSION_TRACKER_ARG(st));\n\t}\n\t_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);\n\n}\n\nvoid _rtw_init_stainfo(struct sta_info *psta);\nvoid _rtw_init_stainfo(struct sta_info *psta)\n{\n\t_rtw_memset((u8 *)psta, 0, sizeof(struct sta_info));\n\n\t_rtw_spinlock_init(&psta->lock);\n\t_rtw_init_listhead(&psta->list);\n\t_rtw_init_listhead(&psta->hash_list);\n\t/* _rtw_init_listhead(&psta->asoc_list); */\n\t/* _rtw_init_listhead(&psta->sleep_list); */\n\t/* _rtw_init_listhead(&psta->wakeup_list);\t */\n\n\t_rtw_init_queue(&psta->sleep_q);\n\n\t_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);\n\t_rtw_init_sta_recv_priv(&psta->sta_recvpriv);\n\n#ifdef CONFIG_AP_MODE\n\t_rtw_init_listhead(&psta->asoc_list);\n\t_rtw_init_listhead(&psta->auth_list);\n\tpsta->bpairwise_key_installed = _FALSE;\n\n#ifdef CONFIG_RTW_80211R\n\tpsta->ft_pairwise_key_installed = _FALSE;\n#endif\n#endif /* CONFIG_AP_MODE\t */\n\n\trtw_st_ctl_init(&psta->st_ctl);\n}\n\nu32\t_rtw_init_sta_priv(struct\tsta_priv *pstapriv)\n{\n\t_adapter *adapter = container_of(pstapriv, _adapter, stapriv);\n\tstruct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);\n\tstruct sta_info *psta;\n\ts32 i;\n\tu32 ret = _FAIL;\n\n\tpstapriv->padapter = adapter;\n\n\tpstapriv->pallocated_stainfo_buf = rtw_zvmalloc(\n\t\tsizeof(struct sta_info) * NUM_STA + MEM_ALIGNMENT_OFFSET);\n\tif (!pstapriv->pallocated_stainfo_buf)\n\t\tgoto exit;\n\n\tpstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf;\n\tif ((SIZE_PTR)pstapriv->pstainfo_buf & MEM_ALIGNMENT_PADDING)\n\t\tpstapriv->pstainfo_buf += MEM_ALIGNMENT_OFFSET -\n\t\t\t((SIZE_PTR)pstapriv->pstainfo_buf & MEM_ALIGNMENT_PADDING);\n\n\t_rtw_init_queue(&pstapriv->free_sta_queue);\n\n\t_rtw_spinlock_init(&pstapriv->sta_hash_lock);\n\n\t/* _rtw_init_queue(&pstapriv->asoc_q); */\n\tpstapriv->asoc_sta_count = 0;\n\t_rtw_init_queue(&pstapriv->sleep_q);\n\t_rtw_init_queue(&pstapriv->wakeup_q);\n\n\tpsta = (struct sta_info *)(pstapriv->pstainfo_buf);\n\n\n\tfor (i = 0; i < NUM_STA; i++) {\n\t\t_rtw_init_stainfo(psta);\n\n\t\t_rtw_init_listhead(&(pstapriv->sta_hash[i]));\n\n\t\trtw_list_insert_tail(&psta->list, get_list_head(&pstapriv->free_sta_queue));\n\n\t\tpsta++;\n\t}\n\n\tpstapriv->adhoc_expire_to = 4; /* 4 * 2 = 8 sec */\n\n#ifdef CONFIG_AP_MODE\n\tpstapriv->max_aid = macid_ctl->num;\n\tpstapriv->rr_aid = 0;\n\tpstapriv->started_aid = 1;\n\tpstapriv->sta_aid = rtw_zmalloc(pstapriv->max_aid * sizeof(struct sta_info *));\n\tif (!pstapriv->sta_aid)\n\t\tgoto exit;\n\tpstapriv->aid_bmp_len = AID_BMP_LEN(pstapriv->max_aid);\n\tpstapriv->sta_dz_bitmap = rtw_zmalloc(pstapriv->aid_bmp_len);\n\tif (!pstapriv->sta_dz_bitmap)\n\t\tgoto exit;\n\tpstapriv->tim_bitmap = rtw_zmalloc(pstapriv->aid_bmp_len);\n\tif (!pstapriv->tim_bitmap)\n\t\tgoto exit;\n\n\t_rtw_init_listhead(&pstapriv->asoc_list);\n\t_rtw_init_listhead(&pstapriv->auth_list);\n\t_rtw_spinlock_init(&pstapriv->asoc_list_lock);\n\t_rtw_spinlock_init(&pstapriv->auth_list_lock);\n\tpstapriv->asoc_list_cnt = 0;\n\tpstapriv->auth_list_cnt = 0;\n\n\tpstapriv->auth_to = 3; /* 3*2 = 6 sec */\n\tpstapriv->assoc_to = 3;\n\t/* pstapriv->expire_to = 900; */ /* 900*2 = 1800 sec = 30 min, expire after no any traffic. */\n\t/* pstapriv->expire_to = 30; */ /* 30*2 = 60 sec = 1 min, expire after no any traffic. */\n#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK\n\tpstapriv->expire_to = 3; /* 3*2 = 6 sec */\n#else\n\tpstapriv->expire_to = 60;/* 60*2 = 120 sec = 2 min, expire after no any traffic. */\n#endif\n#ifdef CONFIG_ATMEL_RC_PATCH\n\t_rtw_memset(pstapriv->atmel_rc_pattern, 0, ETH_ALEN);\n#endif\n\tpstapriv->max_num_sta = NUM_STA;\n\n#endif\n\n#if CONFIG_RTW_MACADDR_ACL\n\tfor (i = 0; i < RTW_ACL_PERIOD_NUM; i++)\n\t\trtw_macaddr_acl_init(adapter, i);\n#endif\n\n#if CONFIG_RTW_PRE_LINK_STA\n\trtw_pre_link_sta_ctl_init(pstapriv);\n#endif\n\n#if defined(DBG_ROAMING_TEST) || defined(CONFIG_RTW_REPEATER_SON)\n\trtw_set_rx_chk_limit(adapter,1);\n#elif defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && !defined(CONFIG_LPS_LCLK_WD_TIMER)\n\trtw_set_rx_chk_limit(adapter,4);\n#else\n\trtw_set_rx_chk_limit(adapter,8);\n#endif\n\n\tret = _SUCCESS;\n\nexit:\n\tif (ret != _SUCCESS) {\n\t\tif (pstapriv->pallocated_stainfo_buf)\n\t\t\trtw_vmfree(pstapriv->pallocated_stainfo_buf,\n\t\t\t\tsizeof(struct sta_info) * NUM_STA + MEM_ALIGNMENT_OFFSET);\n\t\t#ifdef CONFIG_AP_MODE\n\t\tif (pstapriv->sta_aid)\n\t\t\trtw_mfree(pstapriv->sta_aid, pstapriv->max_aid * sizeof(struct sta_info *));\n\t\tif (pstapriv->sta_dz_bitmap)\n\t\t\trtw_mfree(pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);\n\t\t#endif\n\t}\n\n\treturn ret;\n}\n\ninline int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta)\n{\n\tint offset = (((u8 *)sta) - stapriv->pstainfo_buf) / sizeof(struct sta_info);\n\n\tif (!stainfo_offset_valid(offset))\n\t\tRTW_INFO(\"%s invalid offset(%d), out of range!!!\", __func__, offset);\n\n\treturn offset;\n}\n\ninline struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset)\n{\n\tif (!stainfo_offset_valid(offset))\n\t\tRTW_INFO(\"%s invalid offset(%d), out of range!!!\", __func__, offset);\n\n\treturn (struct sta_info *)(stapriv->pstainfo_buf + offset * sizeof(struct sta_info));\n}\n\nvoid\t_rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv);\nvoid\t_rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv)\n{\n\n\t_rtw_spinlock_free(&psta_xmitpriv->lock);\n\n\t_rtw_spinlock_free(&(psta_xmitpriv->be_q.sta_pending.lock));\n\t_rtw_spinlock_free(&(psta_xmitpriv->bk_q.sta_pending.lock));\n\t_rtw_spinlock_free(&(psta_xmitpriv->vi_q.sta_pending.lock));\n\t_rtw_spinlock_free(&(psta_xmitpriv->vo_q.sta_pending.lock));\n}\n\nstatic void\t_rtw_free_sta_recv_priv_lock(struct sta_recv_priv *psta_recvpriv)\n{\n\n\t_rtw_spinlock_free(&psta_recvpriv->lock);\n\n\t_rtw_spinlock_free(&(psta_recvpriv->defrag_q.lock));\n\n\n}\n\nvoid rtw_mfree_stainfo(struct sta_info *psta);\nvoid rtw_mfree_stainfo(struct sta_info *psta)\n{\n\n\tif (&psta->lock != NULL)\n\t\t_rtw_spinlock_free(&psta->lock);\n\n\t_rtw_free_sta_xmit_priv_lock(&psta->sta_xmitpriv);\n\t_rtw_free_sta_recv_priv_lock(&psta->sta_recvpriv);\n\n}\n\n\n/* this function is used to free the memory of lock || sema for all stainfos */\nvoid rtw_mfree_all_stainfo(struct sta_priv *pstapriv);\nvoid rtw_mfree_all_stainfo(struct sta_priv *pstapriv)\n{\n\t_irqL\t irqL;\n\t_list\t*plist, *phead;\n\tstruct sta_info *psta = NULL;\n\n\n\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\tphead = get_list_head(&pstapriv->free_sta_queue);\n\tplist = get_next(phead);\n\n\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\tpsta = LIST_CONTAINOR(plist, struct sta_info , list);\n\t\tplist = get_next(plist);\n\n\t\trtw_mfree_stainfo(psta);\n\t}\n\n\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\n}\n\nvoid rtw_mfree_sta_priv_lock(struct\tsta_priv *pstapriv);\nvoid rtw_mfree_sta_priv_lock(struct\tsta_priv *pstapriv)\n{\n\trtw_mfree_all_stainfo(pstapriv); /* be done before free sta_hash_lock */\n\n\t_rtw_spinlock_free(&pstapriv->free_sta_queue.lock);\n\n\t_rtw_spinlock_free(&pstapriv->sta_hash_lock);\n\t_rtw_spinlock_free(&pstapriv->wakeup_q.lock);\n\t_rtw_spinlock_free(&pstapriv->sleep_q.lock);\n\n#ifdef CONFIG_AP_MODE\n\t_rtw_spinlock_free(&pstapriv->asoc_list_lock);\n\t_rtw_spinlock_free(&pstapriv->auth_list_lock);\n#endif\n\n}\n\nu32\t_rtw_free_sta_priv(struct\tsta_priv *pstapriv)\n{\n\t_irqL\tirqL;\n\t_list\t*phead, *plist;\n\tstruct sta_info *psta = NULL;\n\tstruct recv_reorder_ctrl *preorder_ctrl;\n\tint\tindex;\n\n\tif (pstapriv) {\n\n\t\t/*\tdelete all reordering_ctrl_timer\t\t*/\n\t\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\t\tfor (index = 0; index < NUM_STA; index++) {\n\t\t\tphead = &(pstapriv->sta_hash[index]);\n\t\t\tplist = get_next(phead);\n\n\t\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\t\tint i;\n\t\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info , hash_list);\n\t\t\t\tplist = get_next(plist);\n\n\t\t\t\tfor (i = 0; i < 16 ; i++) {\n\t\t\t\t\tpreorder_ctrl = &psta->recvreorder_ctrl[i];\n\t\t\t\t\t_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\t\t/*===============================*/\n\n\t\trtw_mfree_sta_priv_lock(pstapriv);\n\n#if CONFIG_RTW_MACADDR_ACL\n\t\tfor (index = 0; index < RTW_ACL_PERIOD_NUM; index++)\n\t\t\trtw_macaddr_acl_deinit(pstapriv->padapter, index);\n#endif\n\n#if CONFIG_RTW_PRE_LINK_STA\n\t\trtw_pre_link_sta_ctl_deinit(pstapriv);\n#endif\n\n\t\tif (pstapriv->pallocated_stainfo_buf)\n\t\t\trtw_vmfree(pstapriv->pallocated_stainfo_buf,\n\t\t\t\tsizeof(struct sta_info) * NUM_STA + MEM_ALIGNMENT_OFFSET);\n\t\t#ifdef CONFIG_AP_MODE\n\t\tif (pstapriv->sta_aid)\n\t\t\trtw_mfree(pstapriv->sta_aid, pstapriv->max_aid * sizeof(struct sta_info *));\n\t\tif (pstapriv->sta_dz_bitmap)\n\t\t\trtw_mfree(pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);\n\t\tif (pstapriv->tim_bitmap)\n\t\t\trtw_mfree(pstapriv->tim_bitmap, pstapriv->aid_bmp_len);\n\t\t#endif\n\t}\n\n\treturn _SUCCESS;\n}\n\n\nstatic void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl)\n{\n\t_adapter *padapter = preorder_ctrl->padapter;\n\n#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)\n\trtw_init_timer(&(preorder_ctrl->reordering_ctrl_timer), padapter, rtw_reordering_ctrl_timeout_handler, preorder_ctrl);\n#endif\n}\n\n/* struct\tsta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr) */\nstruct\tsta_info *rtw_alloc_stainfo(struct\tsta_priv *pstapriv, const u8 *hwaddr)\n{\n\t_irqL irqL2;\n\ts32\tindex;\n\t_list\t*phash_list;\n\tstruct sta_info\t*psta;\n\t_queue *pfree_sta_queue;\n\tstruct recv_reorder_ctrl *preorder_ctrl;\n\tint i = 0;\n\tu16  wRxSeqInitialValue = 0xffff;\n\n\n\tpfree_sta_queue = &pstapriv->free_sta_queue;\n\n\t/* _enter_critical_bh(&(pfree_sta_queue->lock), &irqL); */\n\t_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);\n\tif (_rtw_queue_empty(pfree_sta_queue) == _TRUE) {\n\t\t/* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL); */\n\t\t_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);\n\t\tpsta = NULL;\n\t} else {\n\t\tpsta = LIST_CONTAINOR(get_next(&pfree_sta_queue->queue), struct sta_info, list);\n\n\t\trtw_list_delete(&(psta->list));\n\n\t\t/* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL); */\n\t\t_rtw_init_stainfo(psta);\n\n\t\tpsta->padapter = pstapriv->padapter;\n\n\t\t_rtw_memcpy(psta->cmn.mac_addr, hwaddr, ETH_ALEN);\n\n\t\tindex = wifi_mac_hash(hwaddr);\n\n\n\t\tif (index >= NUM_STA) {\n\t\t\tpsta = NULL;\n\t\t\tgoto exit;\n\t\t}\n\t\tphash_list = &(pstapriv->sta_hash[index]);\n\n\t\t/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */\n\n\t\trtw_list_insert_tail(&psta->hash_list, phash_list);\n\n\t\tpstapriv->asoc_sta_count++;\n\n\t\t/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */\n\n\t\t/* Commented by Albert 2009/08/13\n\t\t * For the SMC router, the sequence number of first packet of WPS handshake will be 0.\n\t\t * In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable.\n\t\t * So, we initialize the tid_rxseq variable as the 0xffff. */\n\n\t\tfor (i = 0; i < 16; i++) {\n\t\t\t_rtw_memcpy(&psta->sta_recvpriv.rxcache.tid_rxseq[i], &wRxSeqInitialValue, 2);\n\t\t\t_rtw_memcpy(&psta->sta_recvpriv.bmc_tid_rxseq[i], &wRxSeqInitialValue, 2);\n\t\t\t_rtw_memset(&psta->sta_recvpriv.rxcache.iv[i], 0, sizeof(psta->sta_recvpriv.rxcache.iv[i]));\n\t\t}\n\n\t\trtw_init_timer(&psta->addba_retry_timer, psta->padapter, addba_timer_hdl, psta);\n#ifdef CONFIG_IEEE80211W\n\t\trtw_init_timer(&psta->dot11w_expire_timer, psta->padapter, sa_query_timer_hdl, psta);\n#endif /* CONFIG_IEEE80211W */\n#ifdef CONFIG_TDLS\n\t\trtw_init_tdls_timer(pstapriv->padapter, psta);\n#endif /* CONFIG_TDLS */\n\n\t\t/* for A-MPDU Rx reordering buffer control */\n\t\tfor (i = 0; i < 16 ; i++) {\n\t\t\tpreorder_ctrl = &psta->recvreorder_ctrl[i];\n\t\t\tpreorder_ctrl->padapter = pstapriv->padapter;\n\t\t\tpreorder_ctrl->tid = i;\n\t\t\tpreorder_ctrl->enable = _FALSE;\n\t\t\tpreorder_ctrl->indicate_seq = 0xffff;\n\t\t\t#ifdef DBG_RX_SEQ\n\t\t\tRTW_INFO(\"DBG_RX_SEQ \"FUNC_ADPT_FMT\" tid:%u SN_CLEAR indicate_seq:%d\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(pstapriv->padapter), i, preorder_ctrl->indicate_seq);\n\t\t\t#endif\n\t\t\tpreorder_ctrl->wend_b = 0xffff;\n\t\t\t/* preorder_ctrl->wsize_b = (NR_RECVBUFF-2); */\n\t\t\tpreorder_ctrl->wsize_b = 64;/* 64; */\n\t\t\tpreorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID;\n\n\t\t\t_rtw_init_queue(&preorder_ctrl->pending_recvframe_queue);\n\n\t\t\trtw_init_recv_timer(preorder_ctrl);\n\t\t\trtw_clear_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack);\n\n\t\t}\n\n\n\t\t/* init for DM */\n\t\tpsta->cmn.rssi_stat.rssi = (-1);\n\t\tpsta->cmn.rssi_stat.rssi_cck = (-1);\n\t\tpsta->cmn.rssi_stat.rssi_ofdm = (-1);\n#ifdef CONFIG_ATMEL_RC_PATCH\n\t\tpsta->flag_atmel_rc = 0;\n#endif\n\t\t/* init for the sequence number of received management frame */\n\t\tpsta->RxMgmtFrameSeqNum = 0xffff;\n\t\t_rtw_memset(&psta->sta_stats, 0, sizeof(struct stainfo_stats));\n\n\t\trtw_alloc_macid(pstapriv->padapter, psta);\n\n\t\tpsta->tx_q_enable = 0;\n\t\t_rtw_init_queue(&psta->tx_queue);\n\t\t_init_workitem(&psta->tx_q_work, rtw_xmit_dequeue_callback, NULL);\n\t}\n\nexit:\n\n\t_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);\n\n\n\tif (psta)\n\t\trtw_mi_update_iface_status(&(pstapriv->padapter->mlmepriv), 0);\n\n\treturn psta;\n}\n\n\n/* using pstapriv->sta_hash_lock to protect */\nu32\trtw_free_stainfo(_adapter *padapter , struct sta_info *psta)\n{\n\tint i;\n\t_irqL irqL0;\n\t_queue *pfree_sta_queue;\n\tstruct recv_reorder_ctrl *preorder_ctrl;\n\tstruct\tsta_xmit_priv\t*pstaxmitpriv;\n\tstruct\txmit_priv\t*pxmitpriv = &padapter->xmitpriv;\n\tstruct\tsta_priv *pstapriv = &padapter->stapriv;\n\tstruct hw_xmit *phwxmit;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tint pending_qcnt[4];\n\tu8 is_pre_link_sta = _FALSE;\n\n\tif (psta == NULL)\n\t\tgoto exit;\n\n#ifdef CONFIG_RTW_80211K\n\trm_post_event(padapter, RM_ID_FOR_ALL(psta->cmn.aid), RM_EV_cancel);\n#endif\n\n\tis_pre_link_sta = rtw_is_pre_link_sta(pstapriv, psta->cmn.mac_addr);\n\n\tif (is_pre_link_sta == _FALSE) {\n\t\t_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);\n\t\trtw_list_delete(&psta->hash_list);\n\t\tpstapriv->asoc_sta_count--;\n\t\t_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);\n\t\trtw_mi_update_iface_status(&(padapter->mlmepriv), 0);\n\t} else {\n\t\t_enter_critical_bh(&psta->lock, &irqL0);\n\t\tpsta->state = WIFI_FW_PRE_LINK;\n\t\t_exit_critical_bh(&psta->lock, &irqL0);\n\t}\n\n\t_enter_critical_bh(&psta->lock, &irqL0);\n\tpsta->state &= ~_FW_LINKED;\n\t_exit_critical_bh(&psta->lock, &irqL0);\n\n\tpfree_sta_queue = &pstapriv->free_sta_queue;\n\n\n\tpstaxmitpriv = &psta->sta_xmitpriv;\n\n\t/* rtw_list_delete(&psta->sleep_list); */\n\n\t/* rtw_list_delete(&psta->wakeup_list); */\n\n\trtw_free_xmitframe_queue(pxmitpriv, &psta->tx_queue);\n\t_rtw_deinit_queue(&psta->tx_queue);\n\n\t_enter_critical_bh(&pxmitpriv->lock, &irqL0);\n\n\trtw_free_xmitframe_queue(pxmitpriv, &psta->sleep_q);\n\tpsta->sleepq_len = 0;\n\n\t/* vo */\n\t/* _enter_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); */\n\trtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->vo_q.sta_pending);\n\trtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));\n\tphwxmit = pxmitpriv->hwxmits;\n\tphwxmit->accnt -= pstaxmitpriv->vo_q.qcnt;\n\tpending_qcnt[0] = pstaxmitpriv->vo_q.qcnt;\n\tpstaxmitpriv->vo_q.qcnt = 0;\n\t/* _exit_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); */\n\n\t/* vi */\n\t/* _enter_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); */\n\trtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->vi_q.sta_pending);\n\trtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));\n\tphwxmit = pxmitpriv->hwxmits + 1;\n\tphwxmit->accnt -= pstaxmitpriv->vi_q.qcnt;\n\tpending_qcnt[1] = pstaxmitpriv->vi_q.qcnt;\n\tpstaxmitpriv->vi_q.qcnt = 0;\n\t/* _exit_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); */\n\n\t/* be */\n\t/* _enter_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); */\n\trtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->be_q.sta_pending);\n\trtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));\n\tphwxmit = pxmitpriv->hwxmits + 2;\n\tphwxmit->accnt -= pstaxmitpriv->be_q.qcnt;\n\tpending_qcnt[2] = pstaxmitpriv->be_q.qcnt;\n\tpstaxmitpriv->be_q.qcnt = 0;\n\t/* _exit_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); */\n\n\t/* bk */\n\t/* _enter_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); */\n\trtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->bk_q.sta_pending);\n\trtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));\n\tphwxmit = pxmitpriv->hwxmits + 3;\n\tphwxmit->accnt -= pstaxmitpriv->bk_q.qcnt;\n\tpending_qcnt[3] = pstaxmitpriv->bk_q.qcnt;\n\tpstaxmitpriv->bk_q.qcnt = 0;\n\t/* _exit_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); */\n\n\trtw_os_wake_queue_at_free_stainfo(padapter, pending_qcnt);\n\n\t_exit_critical_bh(&pxmitpriv->lock, &irqL0);\n\n\n\t/* re-init sta_info; 20061114 */ /* will be init in alloc_stainfo */\n\t/* _rtw_init_sta_xmit_priv(&psta->sta_xmitpriv); */\n\t/* _rtw_init_sta_recv_priv(&psta->sta_recvpriv); */\n#ifdef CONFIG_IEEE80211W\n\t_cancel_timer_ex(&psta->dot11w_expire_timer);\n#endif /* CONFIG_IEEE80211W */\n\t_cancel_timer_ex(&psta->addba_retry_timer);\n\n#ifdef CONFIG_TDLS\n\tpsta->tdls_sta_state = TDLS_STATE_NONE;\n#endif /* CONFIG_TDLS */\n\n\t/* for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer */\n\tfor (i = 0; i < 16 ; i++) {\n\t\t_irqL irqL;\n\t\t_list\t*phead, *plist;\n\t\tunion recv_frame *prframe;\n\t\t_queue *ppending_recvframe_queue;\n\t\t_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;\n\n\t\tpreorder_ctrl = &psta->recvreorder_ctrl[i];\n\t\trtw_clear_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack);\n\t\t\n\t\t_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);\n\n\n\t\tppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;\n\n\t\t_enter_critical_bh(&ppending_recvframe_queue->lock, &irqL);\n\n\t\tphead =\tget_list_head(ppending_recvframe_queue);\n\t\tplist = get_next(phead);\n\n\t\twhile (!rtw_is_list_empty(phead)) {\n\t\t\tprframe = LIST_CONTAINOR(plist, union recv_frame, u);\n\n\t\t\tplist = get_next(plist);\n\n\t\t\trtw_list_delete(&(prframe->u.hdr.list));\n\n\t\t\trtw_free_recvframe(prframe, pfree_recv_queue);\n\t\t}\n\n\t\t_exit_critical_bh(&ppending_recvframe_queue->lock, &irqL);\n\n\t}\n\n\tif (!((psta->state & WIFI_AP_STATE) || MacAddr_isBcst(psta->cmn.mac_addr)) && is_pre_link_sta == _FALSE)\n\t\trtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _FALSE);\n\n\n\t/* release mac id for non-bc/mc station, */\n\tif (is_pre_link_sta == _FALSE)\n\t\trtw_release_macid(pstapriv->padapter, psta);\n\n#ifdef CONFIG_AP_MODE\n\n\t/*\n\t\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL0);\n\t\trtw_list_delete(&psta->asoc_list);\n\t\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL0);\n\t*/\n\t_enter_critical_bh(&pstapriv->auth_list_lock, &irqL0);\n\tif (!rtw_is_list_empty(&psta->auth_list)) {\n\t\trtw_list_delete(&psta->auth_list);\n\t\tpstapriv->auth_list_cnt--;\n\t}\n\t_exit_critical_bh(&pstapriv->auth_list_lock, &irqL0);\n\n\tpsta->expire_to = 0;\n#ifdef CONFIG_ATMEL_RC_PATCH\n\tpsta->flag_atmel_rc = 0;\n#endif\n\tpsta->sleepq_ac_len = 0;\n\tpsta->qos_info = 0;\n\n\tpsta->max_sp_len = 0;\n\tpsta->uapsd_bk = 0;\n\tpsta->uapsd_be = 0;\n\tpsta->uapsd_vi = 0;\n\tpsta->uapsd_vo = 0;\n\n\tpsta->has_legacy_ac = 0;\n\n#ifdef CONFIG_NATIVEAP_MLME\n\n\tif (pmlmeinfo->state == _HW_STATE_AP_) {\n\t\trtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid);\n\t\trtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);\n\n\t\t/* rtw_indicate_sta_disassoc_event(padapter, psta); */\n\n\t\tif ((psta->cmn.aid > 0) && (pstapriv->sta_aid[psta->cmn.aid - 1] == psta)) {\n\t\t\tpstapriv->sta_aid[psta->cmn.aid - 1] = NULL;\n\t\t\tpsta->cmn.aid = 0;\n\t\t}\n\t}\n\n#endif /* CONFIG_NATIVEAP_MLME\t */\n\n#ifdef CONFIG_TX_MCAST2UNI\n\tpsta->under_exist_checking = 0;\n#endif /* CONFIG_TX_MCAST2UNI */\n\n#endif /* CONFIG_AP_MODE\t */\n\n\trtw_st_ctl_deinit(&psta->st_ctl);\n\n\tif (is_pre_link_sta == _FALSE) {\n\t\t_rtw_spinlock_free(&psta->lock);\n\n\t\t/* _enter_critical_bh(&(pfree_sta_queue->lock), &irqL0); */\n\t\t_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);\n\t\trtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue));\n\t\t_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);\n\t\t/* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL0); */\n\t}\n\nexit:\n\treturn _SUCCESS;\n}\n\n/* free all stainfo which in sta_hash[all] */\nvoid rtw_free_all_stainfo(_adapter *padapter)\n{\n\t_irqL\t irqL;\n\t_list\t*plist, *phead;\n\ts32\tindex;\n\tstruct sta_info *psta = NULL;\n\tstruct\tsta_priv *pstapriv = &padapter->stapriv;\n\tstruct sta_info *pbcmc_stainfo = rtw_get_bcmc_stainfo(padapter);\n\tu8 free_sta_num = 0;\n\tchar free_sta_list[NUM_STA];\n\tint stainfo_offset;\n\n\n\tif (pstapriv->asoc_sta_count == 1)\n\t\tgoto exit;\n\n\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\tfor (index = 0; index < NUM_STA; index++) {\n\t\tphead = &(pstapriv->sta_hash[index]);\n\t\tplist = get_next(phead);\n\n\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info , hash_list);\n\n\t\t\tplist = get_next(plist);\n\n\t\t\tif (pbcmc_stainfo != psta) {\n\t\t\t\tif (rtw_is_pre_link_sta(pstapriv, psta->cmn.mac_addr) == _FALSE)\n\t\t\t\t\trtw_list_delete(&psta->hash_list);\n\n\t\t\t\tstainfo_offset = rtw_stainfo_offset(pstapriv, psta);\n\t\t\t\tif (stainfo_offset_valid(stainfo_offset))\n\t\t\t\t\tfree_sta_list[free_sta_num++] = stainfo_offset;\n\t\t\t}\n\n\t\t}\n\t}\n\n\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\n\tfor (index = 0; index < free_sta_num; index++) {\n\t\tpsta = rtw_get_stainfo_by_offset(pstapriv, free_sta_list[index]);\n\t\trtw_free_stainfo(padapter , psta);\n\t}\n\nexit:\n\treturn;\n}\n\n/* any station allocated can be searched by hash list */\nstruct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr)\n{\n\n\t_irqL\t irqL;\n\n\t_list\t*plist, *phead;\n\n\tstruct sta_info *psta = NULL;\n\n\tu32\tindex;\n\n\tconst u8 *addr;\n\n\tu8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\n\n\tif (hwaddr == NULL)\n\t\treturn NULL;\n\n\tif (IS_MCAST(hwaddr))\n\t\taddr = bc_addr;\n\telse\n\t\taddr = hwaddr;\n\n\tindex = wifi_mac_hash(addr);\n\n\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\tphead = &(pstapriv->sta_hash[index]);\n\tplist = get_next(phead);\n\n\n\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\n\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\n\t\tif ((_rtw_memcmp(psta->cmn.mac_addr, addr, ETH_ALEN)) == _TRUE) {\n\t\t\t/* if found the matched address */\n\t\t\tbreak;\n\t\t}\n\t\tpsta = NULL;\n\t\tplist = get_next(plist);\n\t}\n\n\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\treturn psta;\n\n}\n\nu32 rtw_init_bcmc_stainfo(_adapter *padapter)\n{\n\n\tstruct sta_info\t*psta;\n\tstruct tx_servq\t*ptxservq;\n\tu32 res = _SUCCESS;\n\tNDIS_802_11_MAC_ADDRESS\tbcast_addr = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\n\tstruct\tsta_priv *pstapriv = &padapter->stapriv;\n\t/* _queue\t*pstapending = &padapter->xmitpriv.bm_pending; */\n\n\n\tpsta = rtw_alloc_stainfo(pstapriv, bcast_addr);\n\n\tif (psta == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n#ifdef CONFIG_BEAMFORMING\n\tpsta->cmn.bf_info.g_id = 63;\n\tpsta->cmn.bf_info.p_aid = 0;\n#endif\n\n\tptxservq = &(psta->sta_xmitpriv.be_q);\n\n\t/*\n\t\t_enter_critical(&pstapending->lock, &irqL0);\n\n\t\tif (rtw_is_list_empty(&ptxservq->tx_pending))\n\t\t\trtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(pstapending));\n\n\t\t_exit_critical(&pstapending->lock, &irqL0);\n\t*/\n\nexit:\n\treturn _SUCCESS;\n\n}\n\n\nstruct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter)\n{\n\tstruct sta_info\t*psta;\n\tstruct sta_priv\t*pstapriv = &padapter->stapriv;\n\tu8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tpsta = rtw_get_stainfo(pstapriv, bc_addr);\n\treturn psta;\n\n}\n\n#ifdef CONFIG_AP_MODE\nu16 rtw_aid_alloc(_adapter *adapter, struct sta_info *sta)\n{\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tu16 aid, i, used_cnt = 0;\n\n\tfor (i = 0; i < stapriv->max_aid; i++) {\n\t\taid = ((i + stapriv->started_aid - 1) % stapriv->max_aid) + 1;\n\t\tif (stapriv->sta_aid[aid - 1] == NULL)\n\t\t\tbreak;\n\t\tif (++used_cnt >= stapriv->max_num_sta)\n\t\t\tbreak;\n\t}\n\n\t/* check for aid limit and assoc limit  */\n\tif (i >= stapriv->max_aid || used_cnt >= stapriv->max_num_sta)\n\t\taid = 0;\n\n\tsta->cmn.aid = aid;\n\tif (aid) {\n\t\tstapriv->sta_aid[aid - 1] = sta;\n\t\tif (stapriv->rr_aid)\n\t\t\tstapriv->started_aid = (aid % stapriv->max_aid) + 1;\n\t}\n\n\treturn aid;\n}\n\nvoid dump_aid_status(void *sel, _adapter *adapter)\n{\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tu8 *aid_bmp;\n\tu16 i, used_cnt = 0;\n\n\taid_bmp = rtw_zmalloc(stapriv->aid_bmp_len);\n\tif (!aid_bmp)\n\t\treturn;\n\n\tfor (i = 1; i <= stapriv->max_aid; i++) {\n\t\tif (stapriv->sta_aid[i - 1]) {\n\t\t\taid_bmp[i / 8] |= BIT(i % 8);\n\t\t\t++used_cnt;\n\t\t}\n\t}\n\n\tRTW_PRINT_SEL(sel, \"used_cnt:%u/%u\\n\", used_cnt, stapriv->max_aid);\n\tRTW_MAP_DUMP_SEL(sel, \"aid_map:\", aid_bmp, stapriv->aid_bmp_len);\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"%-2s %-11s\\n\", \"rr\", \"started_aid\");\n\tRTW_PRINT_SEL(sel, \"%2d %11d\\n\", stapriv->rr_aid, stapriv->started_aid);\n\n\trtw_mfree(aid_bmp, stapriv->aid_bmp_len);\n}\n#endif /* CONFIG_AP_MODE */\n\n#if CONFIG_RTW_MACADDR_ACL\nconst char *const _acl_period_str[RTW_ACL_PERIOD_NUM] = {\n\t\"DEV\",\n\t\"BSS\",\n};\n\nconst char *const _acl_mode_str[RTW_ACL_MODE_MAX] = {\n\t\"DISABLED\",\n\t\"ACCEPT_UNLESS_LISTED\",\n\t\"DENY_UNLESS_LISTED\",\n};\n\nu8 _rtw_access_ctrl(_adapter *adapter, u8 period, const u8 *mac_addr)\n{\n\tu8 res = _TRUE;\n\t_irqL irqL;\n\t_list *list, *head;\n\tstruct rtw_wlan_acl_node *acl_node;\n\tu8 match = _FALSE;\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct wlan_acl_pool *acl;\n\t_queue\t*acl_node_q;\n\n\tif (period >= RTW_ACL_PERIOD_NUM) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tacl = &stapriv->acl_list[period];\n\tacl_node_q = &acl->acl_node_q;\n\n\tif (acl->mode != RTW_ACL_MODE_ACCEPT_UNLESS_LISTED\n\t\t&& acl->mode != RTW_ACL_MODE_DENY_UNLESS_LISTED)\n\t\tgoto exit;\n\n\t_enter_critical_bh(&(acl_node_q->lock), &irqL);\n\thead = get_list_head(acl_node_q);\n\tlist = get_next(head);\n\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\tacl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list);\n\t\tlist = get_next(list);\n\n\t\tif (_rtw_memcmp(acl_node->addr, mac_addr, ETH_ALEN)) {\n\t\t\tif (acl_node->valid == _TRUE) {\n\t\t\t\tmatch = _TRUE;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\t_exit_critical_bh(&(acl_node_q->lock), &irqL);\n\n\tif (acl->mode == RTW_ACL_MODE_ACCEPT_UNLESS_LISTED)\n\t\tres = (match == _TRUE) ?  _FALSE : _TRUE;\n\telse /* RTW_ACL_MODE_DENY_UNLESS_LISTED */\n\t\tres = (match == _TRUE) ?  _TRUE : _FALSE;\n\nexit:\n\treturn res;\n}\n\nu8 rtw_access_ctrl(_adapter *adapter, const u8 *mac_addr)\n{\n\tint i;\n\n\tfor (i = 0; i < RTW_ACL_PERIOD_NUM; i++)\n\t\tif (_rtw_access_ctrl(adapter, i, mac_addr) == _FALSE)\n\t\t\treturn _FALSE;\n\n\treturn _TRUE;\n}\n\nvoid dump_macaddr_acl(void *sel, _adapter *adapter)\n{\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct wlan_acl_pool *acl;\n\tint i, j;\n\n\tfor (j = 0; j < RTW_ACL_PERIOD_NUM; j++) {\n\t\tRTW_PRINT_SEL(sel, \"period:%s(%d)\\n\", acl_period_str(j), j);\n\n\t\tacl = &stapriv->acl_list[j];\n\t\tRTW_PRINT_SEL(sel, \"mode:%s(%d)\\n\", acl_mode_str(acl->mode), acl->mode);\n\t\tRTW_PRINT_SEL(sel, \"num:%d/%d\\n\", acl->num, NUM_ACL);\n\t\tfor (i = 0; i < NUM_ACL; i++) {\n\t\t\tif (acl->aclnode[i].valid == _FALSE)\n\t\t\t\tcontinue;\n\t\t\tRTW_PRINT_SEL(sel, MAC_FMT\"\\n\", MAC_ARG(acl->aclnode[i].addr));\n\t\t}\n\t\tRTW_PRINT_SEL(sel, \"\\n\");\n\t}\n}\n#endif /* CONFIG_RTW_MACADDR_ACL */\n\nbool rtw_is_pre_link_sta(struct sta_priv *stapriv, u8 *addr)\n{\n#if CONFIG_RTW_PRE_LINK_STA\n\tstruct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;\n\tstruct sta_info *sta = NULL;\n\tu8 exist = _FALSE;\n\tint i;\n\t_irqL irqL;\n\n\t_enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);\n\tfor (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {\n\t\tif (pre_link_sta_ctl->node[i].valid == _TRUE\n\t\t\t&& _rtw_memcmp(pre_link_sta_ctl->node[i].addr, addr, ETH_ALEN) == _TRUE\n\t\t) {\n\t\t\texist = _TRUE;\n\t\t\tbreak;\n\t\t}\n\t}\n\t_exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);\n\n\treturn exist;\n#else\n\treturn _FALSE;\n#endif\n}\n\n#if CONFIG_RTW_PRE_LINK_STA\nstruct sta_info *rtw_pre_link_sta_add(struct sta_priv *stapriv, u8 *hwaddr)\n{\n\tstruct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;\n\tstruct pre_link_sta_node_t *node = NULL;\n\tstruct sta_info *sta = NULL;\n\tu8 exist = _FALSE;\n\tint i;\n\t_irqL irqL;\n\n\tif (rtw_check_invalid_mac_address(hwaddr, _FALSE) == _TRUE)\n\t\tgoto exit;\n\n\t_enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);\n\tfor (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {\n\t\tif (pre_link_sta_ctl->node[i].valid == _TRUE\n\t\t\t&& _rtw_memcmp(pre_link_sta_ctl->node[i].addr, hwaddr, ETH_ALEN) == _TRUE\n\t\t) {\n\t\t\tnode = &pre_link_sta_ctl->node[i];\n\t\t\texist = _TRUE;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (node == NULL && pre_link_sta_ctl->node[i].valid == _FALSE)\n\t\t\tnode = &pre_link_sta_ctl->node[i];\n\t}\n\n\tif (exist == _FALSE && node) {\n\t\t_rtw_memcpy(node->addr, hwaddr, ETH_ALEN);\n\t\tnode->valid = _TRUE;\n\t\tpre_link_sta_ctl->num++;\n\t}\n\t_exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);\n\n\tif (node == NULL)\n\t\tgoto exit;\n\n\tsta = rtw_get_stainfo(stapriv, hwaddr);\n\tif (sta)\n\t\tgoto odm_hook;\n\n\tsta = rtw_alloc_stainfo(stapriv, hwaddr);\n\tif (!sta)\n\t\tgoto exit;\n\n\tsta->state = WIFI_FW_PRE_LINK;\n\nodm_hook:\n\trtw_hal_set_odm_var(stapriv->padapter, HAL_ODM_STA_INFO, sta, _TRUE);\n\nexit:\n\treturn sta;\n}\n\nvoid rtw_pre_link_sta_del(struct sta_priv *stapriv, u8 *hwaddr)\n{\n\tstruct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;\n\tstruct pre_link_sta_node_t *node = NULL;\n\tstruct sta_info *sta = NULL;\n\tu8 exist = _FALSE;\n\tint i;\n\t_irqL irqL;\n\n\tif (rtw_check_invalid_mac_address(hwaddr, _FALSE) == _TRUE)\n\t\tgoto exit;\n\n\t_enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);\n\tfor (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {\n\t\tif (pre_link_sta_ctl->node[i].valid == _TRUE\n\t\t\t&& _rtw_memcmp(pre_link_sta_ctl->node[i].addr, hwaddr, ETH_ALEN) == _TRUE\n\t\t) {\n\t\t\tnode = &pre_link_sta_ctl->node[i];\n\t\t\texist = _TRUE;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (exist == _TRUE && node) {\n\t\tnode->valid = _FALSE;\n\t\tpre_link_sta_ctl->num--;\n\t}\n\t_exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);\n\n\tif (exist == _FALSE)\n\t\tgoto exit;\n\n\tsta = rtw_get_stainfo(stapriv, hwaddr);\n\tif (!sta)\n\t\tgoto exit;\n\n\tif (sta->state == WIFI_FW_PRE_LINK)\n\t\trtw_free_stainfo(stapriv->padapter, sta);\n\nexit:\n\treturn;\n}\n\nvoid rtw_pre_link_sta_ctl_reset(struct sta_priv *stapriv)\n{\n\tstruct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;\n\tstruct pre_link_sta_node_t *node = NULL;\n\tstruct sta_info *sta = NULL;\n\tint i, j = 0;\n\t_irqL irqL;\n\n\tu8 addrs[RTW_PRE_LINK_STA_NUM][ETH_ALEN];\n\n\t_rtw_memset(addrs, 0, RTW_PRE_LINK_STA_NUM * ETH_ALEN);\n\n\t_enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);\n\tfor (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {\n\t\tif (pre_link_sta_ctl->node[i].valid == _FALSE)\n\t\t\tcontinue;\n\t\t_rtw_memcpy(&(addrs[j][0]), pre_link_sta_ctl->node[i].addr, ETH_ALEN);\n\t\tpre_link_sta_ctl->node[i].valid = _FALSE;\n\t\tpre_link_sta_ctl->num--;\n\t\tj++;\n\t}\n\t_exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);\n\n\tfor (i = 0; i < j; i++) {\n\t\tsta = rtw_get_stainfo(stapriv, &(addrs[i][0]));\n\t\tif (!sta)\n\t\t\tcontinue;\n\n\t\tif (sta->state == WIFI_FW_PRE_LINK)\n\t\t\trtw_free_stainfo(stapriv->padapter, sta);\n\t}\n}\n\nvoid rtw_pre_link_sta_ctl_init(struct sta_priv *stapriv)\n{\n\tstruct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;\n\tint i;\n\n\t_rtw_spinlock_init(&pre_link_sta_ctl->lock);\n\tpre_link_sta_ctl->num = 0;\n\tfor (i = 0; i < RTW_PRE_LINK_STA_NUM; i++)\n\t\tpre_link_sta_ctl->node[i].valid = _FALSE;\n}\n\nvoid rtw_pre_link_sta_ctl_deinit(struct sta_priv *stapriv)\n{\n\tstruct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;\n\tint i;\n\n\trtw_pre_link_sta_ctl_reset(stapriv);\n\n\t_rtw_spinlock_free(&pre_link_sta_ctl->lock);\n}\n\nvoid dump_pre_link_sta_ctl(void *sel, struct sta_priv *stapriv)\n{\n\tstruct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;\n\tint i;\n\n\tRTW_PRINT_SEL(sel, \"num:%d/%d\\n\", pre_link_sta_ctl->num, RTW_PRE_LINK_STA_NUM);\n\n\tfor (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {\n\t\tif (pre_link_sta_ctl->node[i].valid == _FALSE)\n\t\t\tcontinue;\n\t\tRTW_PRINT_SEL(sel, MAC_FMT\"\\n\", MAC_ARG(pre_link_sta_ctl->node[i].addr));\n\t}\n}\n#endif /* CONFIG_RTW_PRE_LINK_STA */\n\n"
  },
  {
    "path": "core/rtw_tdls.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_TDLS_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\n#ifdef CONFIG_TDLS\n#define ONE_SEC \t1000 /* 1000 ms */\n\nextern unsigned char MCS_rate_2R[16];\nextern unsigned char MCS_rate_1R[16];\n\ninline void rtw_tdls_set_link_established(_adapter *adapter, bool en)\n{\n\tadapter->tdlsinfo.link_established = en;\n\trtw_mi_update_iface_status(&(adapter->mlmepriv), 0);\n}\n\nvoid rtw_reset_tdls_info(_adapter *padapter)\n{\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\n\tptdlsinfo->ap_prohibited = _FALSE;\n\n\t/* For TDLS channel switch, currently we only allow it to work in wifi logo test mode */\n\tif (padapter->registrypriv.wifi_spec == 1)\n\t\tptdlsinfo->ch_switch_prohibited = _FALSE;\n\telse\n\t\tptdlsinfo->ch_switch_prohibited = _TRUE;\n\n\trtw_tdls_set_link_established(padapter, _FALSE);\n\tptdlsinfo->sta_cnt = 0;\n\tptdlsinfo->sta_maximum = _FALSE;\n\n#ifdef CONFIG_TDLS_CH_SW\n\tptdlsinfo->chsw_info.ch_sw_state = TDLS_STATE_NONE;\n\tATOMIC_SET(&ptdlsinfo->chsw_info.chsw_on, _FALSE);\n\tptdlsinfo->chsw_info.off_ch_num = 0;\n\tptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\tptdlsinfo->chsw_info.cur_time = 0;\n\tptdlsinfo->chsw_info.delay_switch_back = _FALSE;\n\tptdlsinfo->chsw_info.dump_stack = _FALSE;\n#endif\n\n\tptdlsinfo->ch_sensing = 0;\n\tptdlsinfo->watchdog_count = 0;\n\tptdlsinfo->dev_discovered = _FALSE;\n\n#ifdef CONFIG_WFD\n\tptdlsinfo->wfd_info = &padapter->wfd_info;\n#endif\n\n\tptdlsinfo->tdls_sctx = NULL;\n}\n\nint rtw_init_tdls_info(_adapter *padapter)\n{\n\tint\tres = _SUCCESS;\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\n\trtw_reset_tdls_info(padapter);\n\n#ifdef CONFIG_TDLS_DRIVER_SETUP\n\tptdlsinfo->driver_setup = _TRUE;\n#else\n\tptdlsinfo->driver_setup = _FALSE;\n#endif /* CONFIG_TDLS_DRIVER_SETUP */\n\n\t_rtw_spinlock_init(&ptdlsinfo->cmd_lock);\n\t_rtw_spinlock_init(&ptdlsinfo->hdl_lock);\n\n\treturn res;\n\n}\n\nvoid rtw_free_tdls_info(struct tdls_info *ptdlsinfo)\n{\n\t_rtw_spinlock_free(&ptdlsinfo->cmd_lock);\n\t_rtw_spinlock_free(&ptdlsinfo->hdl_lock);\n\n\t_rtw_memset(ptdlsinfo, 0, sizeof(struct tdls_info));\n\n}\n\nvoid rtw_free_all_tdls_sta(_adapter *padapter, u8 enqueue_cmd)\n{\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\t_irqL\t irqL;\n\t_list\t*plist, *phead;\n\ts32\tindex;\n\tstruct sta_info *psta = NULL;\n\tstruct sta_info *ptdls_sta[NUM_STA];\n\tu8 empty_hwaddr[ETH_ALEN] = { 0x00 };\n\n\t_rtw_memset(ptdls_sta, 0x00, sizeof(ptdls_sta));\n\n\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\tfor (index = 0; index < NUM_STA; index++) {\n\t\tphead = &(pstapriv->sta_hash[index]);\n\t\tplist = get_next(phead);\n\n\t\twhile (rtw_end_of_queue_search(phead, plist) == _FALSE) {\n\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\n\t\t\tplist = get_next(plist);\n\n\t\t\tif (psta->tdls_sta_state != TDLS_STATE_NONE)\n\t\t\t\tptdls_sta[index] = psta;\n\t\t}\n\t}\n\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\tfor (index = 0; index < NUM_STA; index++) {\n\t\tif (ptdls_sta[index]) {\n\t\t\tstruct TDLSoption_param tdls_param;\n\n\t\t\tpsta = ptdls_sta[index];\n\n\t\t\tRTW_INFO(\"Do tear down to \"MAC_FMT\" by enqueue_cmd = %d\\n\", MAC_ARG(psta->cmn.mac_addr), enqueue_cmd);\n\n\t\t\t_rtw_memcpy(&(tdls_param.addr), psta->cmn.mac_addr, ETH_ALEN);\n\t\t\ttdls_param.option = TDLS_TEARDOWN_STA_NO_WAIT;\n\t\t\ttdls_hdl(padapter, (unsigned char *)&(tdls_param));\n\n\t\t\trtw_tdls_teardown_pre_hdl(padapter, psta);\n\n\t\t\tif (enqueue_cmd == _TRUE)\n\t\t\t\trtw_tdls_cmd(padapter, psta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);\n\t\t\telse\n\t\t\t {\n\t\t\t\ttdls_param.option = TDLS_TEARDOWN_STA_LOCALLY_POST;\n\t\t\t\ttdls_hdl(padapter, (unsigned char *)&(tdls_param));\n\t\t\t}\n\t\t}\n\t}\n}\n\nint check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len)\n{\n\tu8 tdls_prohibited_bit = 0x40; /* bit(38); TDLS_prohibited */\n\n\tif (pkt_len < 5)\n\t\treturn _FALSE;\n\n\tpframe += 4;\n\tif ((*pframe) & tdls_prohibited_bit)\n\t\treturn _TRUE;\n\n\treturn _FALSE;\n}\n\nint check_ap_tdls_ch_switching_prohibited(u8 *pframe, u8 pkt_len)\n{\n\tu8 tdls_ch_swithcing_prohibited_bit = 0x80; /* bit(39); TDLS_channel_switching prohibited */\n\n\tif (pkt_len < 5)\n\t\treturn _FALSE;\n\n\tpframe += 4;\n\tif ((*pframe) & tdls_ch_swithcing_prohibited_bit)\n\t\treturn _TRUE;\n\n\treturn _FALSE;\n}\n\nu8 rtw_is_tdls_enabled(_adapter *padapter)\n{\n\treturn padapter->registrypriv.en_tdls;\n}\n\nvoid rtw_set_tdls_enable(_adapter *padapter, u8 enable)\n{\n\tpadapter->registrypriv.en_tdls = enable;\n\tRTW_INFO(\"%s: en_tdls = %d\\n\", __func__, rtw_is_tdls_enabled(padapter));\n}\n\nvoid rtw_enable_tdls_func(_adapter *padapter)\n{\n\tif (rtw_is_tdls_enabled(padapter) == _TRUE)\n\t\treturn;\n\n#if 0\n#ifdef CONFIG_MCC_MODE\n\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC) == _TRUE) {\n\t\tRTW_INFO(\"[TDLS] MCC is running, can't enable TDLS !\\n\");\n\t\treturn;\n\t}\n#endif\n#endif\n\trtw_set_tdls_enable(padapter, _TRUE);\n}\n\nvoid rtw_disable_tdls_func(_adapter *padapter, u8 enqueue_cmd)\n{\n\tif (rtw_is_tdls_enabled(padapter) == _FALSE)\n\t\treturn;\n\n\trtw_free_all_tdls_sta(padapter, enqueue_cmd);\n\trtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR);\n\trtw_reset_tdls_info(padapter);\n\n\trtw_set_tdls_enable(padapter, _FALSE);\n}\n\nu8 rtw_is_tdls_sta_existed(_adapter *padapter)\n{\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct sta_info *psta;\n\tint i = 0;\n\t_irqL irqL;\n\t_list\t*plist, *phead;\n\tu8 ret = _FALSE;\n\n\tif (rtw_is_tdls_enabled(padapter) == _FALSE)\n\t\treturn _FALSE;\n\n\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\tfor (i = 0; i < NUM_STA; i++) {\n\t\tphead = &(pstapriv->sta_hash[i]);\n\t\tplist = get_next(phead);\n\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\t\t\tplist = get_next(plist);\n\t\t\tif (psta->tdls_sta_state != TDLS_STATE_NONE) {\n\t\t\t\tret = _TRUE;\n\t\t\t\tgoto Exit;\n\t\t\t}\n\t\t}\n\t}\n\nExit:\n\n\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\treturn ret;\n}\n\nu8 rtw_tdls_is_setup_allowed(_adapter *padapter)\n{\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\n\tif (is_client_associated_to_ap(padapter) == _FALSE)\n\t\treturn _FALSE;\n\n\tif (ptdlsinfo->ap_prohibited == _TRUE)\n\t\treturn _FALSE;\n\n\treturn _TRUE;\n}\n\n#ifdef CONFIG_TDLS_CH_SW\nu8 rtw_tdls_is_chsw_allowed(_adapter *padapter)\n{\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\n\tif (ptdlsinfo->ch_switch_prohibited == _TRUE)\n\t\treturn _FALSE;\n\n\tif (padapter->registrypriv.wifi_spec == 0)\n\t\treturn _FALSE;\n\n\treturn _TRUE;\n}\n#endif\n\nint _issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ms)\n{\n\tint ret = _FAIL;\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl, *qc;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\tpattrib->hdrlen += 2;\n\tpattrib->qos_en = _TRUE;\n\tpattrib->eosp = 1;\n\tpattrib->ack_policy = 0;\n\tpattrib->mdata = 0;\n\tpattrib->retry_ctrl = _FALSE;\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\tif (power_mode)\n\t\tSetPwrMgt(fctrl);\n\n\tqc = (unsigned short *)(pframe + pattrib->hdrlen - 2);\n\n\tSetPriority(qc, 7);\t/* Set priority to VO */\n\n\tSetEOSP(qc, pattrib->eosp);\n\n\tSetAckpolicy(qc, pattrib->ack_policy);\n\n\t_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_QOS_DATA_NULL);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos);\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tif (wait_ms)\n\t\tret = dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, wait_ms);\n\telse {\n\t\tdump_mgntframe(padapter, pmgntframe);\n\t\tret = _SUCCESS;\n\t}\n\nexit:\n\treturn ret;\n\n}\n\n/*\n *wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT\n *wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX\n *try_cnt means the maximal TX count to try\n */\nint issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms)\n{\n\tint ret;\n\tint i = 0;\n\tsystime start = rtw_get_current_time();\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n#if 0\n\tpsta = rtw_get_stainfo(&padapter->stapriv, da);\n\tif (psta) {\n\t\tif (power_mode)\n\t\t\trtw_hal_macid_sleep(padapter, psta->cmn.mac_id);\n\t\telse\n\t\t\trtw_hal_macid_wakeup(padapter, psta->cmn.mac_id);\n\t} else {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": Can't find sta info for \" MAC_FMT \", skip macid %s!!\\n\",\n\t\t\tFUNC_ADPT_ARG(padapter), MAC_ARG(da), power_mode ? \"sleep\" : \"wakeup\");\n\t\trtw_warn_on(1);\n\t}\n#endif\n\n\tdo {\n\t\tret = _issue_nulldata_to_TDLS_peer_STA(padapter, da, power_mode, wait_ms);\n\n\t\ti++;\n\n\t\tif (RTW_CANNOT_RUN(padapter))\n\t\t\tbreak;\n\n\t\tif (i < try_cnt && wait_ms > 0 && ret == _FAIL)\n\t\t\trtw_msleep_os(wait_ms);\n\n\t} while ((i < try_cnt) && (ret == _FAIL || wait_ms == 0));\n\n\tif (ret != _FAIL) {\n\t\tret = _SUCCESS;\n#ifndef DBG_XMIT_ACK\n\t\tgoto exit;\n#endif\n\t}\n\n\tif (try_cnt && wait_ms) {\n\t\tif (da)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" to \"MAC_FMT\", ch:%u%s, %d/%d in %u ms\\n\",\n\t\t\t\tFUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),\n\t\t\t\tret == _SUCCESS ? \", acked\" : \"\", i, try_cnt, rtw_get_passing_time_ms(start));\n\t\telse\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\", ch:%u%s, %d/%d in %u ms\\n\",\n\t\t\t\tFUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),\n\t\t\t\tret == _SUCCESS ? \", acked\" : \"\", i, try_cnt, rtw_get_passing_time_ms(start));\n\t}\nexit:\n\treturn ret;\n}\n\n/* TDLS encryption(if needed) will always be CCMP */\nvoid rtw_tdls_set_key(_adapter *padapter, struct sta_info *ptdls_sta)\n{\n\tptdls_sta->dot118021XPrivacy = _AES_;\n\trtw_setstakey_cmd(padapter, ptdls_sta, TDLS_KEY, _TRUE);\n}\n\n#ifdef CONFIG_80211N_HT\nvoid rtw_tdls_process_ht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct ht_priv\t\t\t*phtpriv = &pmlmepriv->htpriv;\n\tu8\tmax_AMPDU_len, min_MPDU_spacing;\n\tu8\tcur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0;\n\n\t/* Save HT capabilities in the sta object */\n\t_rtw_memset(&ptdls_sta->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap));\n\tif (data && Length >= sizeof(struct rtw_ieee80211_ht_cap)) {\n\t\tptdls_sta->flags |= WLAN_STA_HT;\n\t\tptdls_sta->flags |= WLAN_STA_WME;\n\n\t\t_rtw_memcpy(&ptdls_sta->htpriv.ht_cap, data, sizeof(struct rtw_ieee80211_ht_cap));\n\t} else {\n\t\tptdls_sta->flags &= ~WLAN_STA_HT;\n\t\treturn;\n\t}\n\n\tif (ptdls_sta->flags & WLAN_STA_HT) {\n\t\tif (padapter->registrypriv.ht_enable == _TRUE && is_supported_ht(padapter->registrypriv.wireless_mode) ) {\n\t\t\tptdls_sta->htpriv.ht_option = _TRUE;\n\t\t\tptdls_sta->qos_option = _TRUE;\n\t\t} else {\n\t\t\tptdls_sta->htpriv.ht_option = _FALSE;\n\t\t\tptdls_sta->qos_option = _FALSE;\n\t\t}\n\t}\n\n\t/* HT related cap */\n\tif (ptdls_sta->htpriv.ht_option) {\n\t\t/* Check if sta supports rx ampdu */\n\t\tif (padapter->registrypriv.ampdu_enable == 1)\n\t\t\tptdls_sta->htpriv.ampdu_enable = _TRUE;\n\n\t\t/* AMPDU Parameters field */\n\t\t/* Get MIN of MAX AMPDU Length Exp */\n\t\tif ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3) > (data[2] & 0x3))\n\t\t\tmax_AMPDU_len = (data[2] & 0x3);\n\t\telse\n\t\t\tmax_AMPDU_len = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3);\n\t\t/* Get MAX of MIN MPDU Start Spacing */\n\t\tif ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) > (data[2] & 0x1c))\n\t\t\tmin_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c);\n\t\telse\n\t\t\tmin_MPDU_spacing = (data[2] & 0x1c);\n\t\tptdls_sta->htpriv.rx_ampdu_min_spacing = max_AMPDU_len | min_MPDU_spacing;\n\n\t\t/* Check if sta support s Short GI 20M */\n\t\tif ((phtpriv->sgi_20m == _TRUE) && (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_20)))\n\t\t\tptdls_sta->htpriv.sgi_20m = _TRUE;\n\n\t\t/* Check if sta support s Short GI 40M */\n\t\tif ((phtpriv->sgi_40m == _TRUE) && (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)))\n\t\t\tptdls_sta->htpriv.sgi_40m = _TRUE;\n\n\t\t/* Bwmode would still followed AP's setting */\n\t\tif (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH)) {\n\t\t\tif (padapter->mlmeextpriv.cur_bwmode >= CHANNEL_WIDTH_40)\n\t\t\t\tptdls_sta->cmn.bw_mode = CHANNEL_WIDTH_40;\n\t\t\tptdls_sta->htpriv.ch_offset = padapter->mlmeextpriv.cur_ch_offset;\n\t\t}\n\n\t\t/* Config LDPC Coding Capability */\n\t\tif (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX) && GET_HT_CAP_ELE_LDPC_CAP(data)) {\n\t\t\tSET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX));\n\t\t\tRTW_INFO(\"Enable HT Tx LDPC!\\n\");\n\t\t}\n\t\tptdls_sta->htpriv.ldpc_cap = cur_ldpc_cap;\n\n\t\t/* Config STBC setting */\n\t\tif (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(data)) {\n\t\t\tSET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX));\n\t\t\tRTW_INFO(\"Enable HT Tx STBC!\\n\");\n\t\t}\n\t\tptdls_sta->htpriv.stbc_cap = cur_stbc_cap;\n\n#ifdef CONFIG_BEAMFORMING\n\t\t/* Config Tx beamforming setting */\n\t\tif (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&\n\t\t    GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(data))\n\t\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);\n\n\t\tif (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&\n\t\t    GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(data))\n\t\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);\n\t\tptdls_sta->htpriv.beamform_cap = cur_beamform_cap;\n\t\tif (cur_beamform_cap)\n\t\t\tRTW_INFO(\"Client HT Beamforming Cap = 0x%02X\\n\", cur_beamform_cap);\n#endif /* CONFIG_BEAMFORMING */\n\t}\n\n}\n\nu8 *rtw_tdls_set_ht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)\n{\n\trtw_ht_use_default_setting(padapter);\n\n\tif (padapter->registrypriv.wifi_spec == 1) {\n\t\tpadapter->mlmepriv.htpriv.sgi_20m = _FALSE;\n\t\tpadapter->mlmepriv.htpriv.sgi_40m = _FALSE;\n\t}\n\n\trtw_restructure_ht_ie(padapter, NULL, pframe, 0, &(pattrib->pktlen), padapter->mlmeextpriv.cur_channel);\n\n\treturn pframe + pattrib->pktlen;\n}\n#endif\n\n#ifdef CONFIG_80211AC_VHT\nvoid rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct vht_priv\t\t\t*pvhtpriv = &pmlmepriv->vhtpriv;\n\tu8\tcur_ldpc_cap = 0, cur_stbc_cap = 0, rf_type = RF_1T1R, tx_nss = 0;\n\tu16 cur_beamform_cap = 0;\n\tu8\t*pcap_mcs;\n\n\t_rtw_memset(&ptdls_sta->vhtpriv, 0, sizeof(struct vht_priv));\n\tif (data && Length == 12) {\n\t\tptdls_sta->flags |= WLAN_STA_VHT;\n\n\t\t_rtw_memcpy(ptdls_sta->vhtpriv.vht_cap, data, 12);\n\n#if 0\n\t\tif (elems.vht_op_mode_notify && elems.vht_op_mode_notify_len == 1)\n\t\t\t_rtw_memcpy(&pstat->vhtpriv.vht_op_mode_notify, elems.vht_op_mode_notify, 1);\n\t\telse /* for Frame without Operating Mode notify ie; default: 80M */\n\t\t\tpstat->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80;\n#else\n\t\tptdls_sta->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80;\n#endif\n\t} else {\n\t\tptdls_sta->flags &= ~WLAN_STA_VHT;\n\t\treturn;\n\t}\n\n\tif (ptdls_sta->flags & WLAN_STA_VHT) {\n\t\tif (REGSTY_IS_11AC_ENABLE(&padapter->registrypriv)\n\t\t    && is_supported_vht(padapter->registrypriv.wireless_mode)\n\t\t    && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))) {\n\t\t\tptdls_sta->vhtpriv.vht_option = _TRUE;\n\t\t\tptdls_sta->cmn.ra_info.is_vht_enable = _TRUE;\n\t\t}\n\t\telse\n\t\t\tptdls_sta->vhtpriv.vht_option = _FALSE;\n\t}\n\n\t/* B4 Rx LDPC */\n\tif (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX) &&\n\t    GET_VHT_CAPABILITY_ELE_RX_LDPC(data)) {\n\t\tSET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));\n\t\tRTW_INFO(\"Current VHT LDPC Setting = %02X\\n\", cur_ldpc_cap);\n\t}\n\tptdls_sta->vhtpriv.ldpc_cap = cur_ldpc_cap;\n\n\t/* B5 Short GI for 80 MHz */\n\tptdls_sta->vhtpriv.sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(data) & pvhtpriv->sgi_80m) ? _TRUE : _FALSE;\n\n\t/* B8 B9 B10 Rx STBC */\n\tif (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX) &&\n\t    GET_VHT_CAPABILITY_ELE_RX_STBC(data)) {\n\t\tSET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));\n\t\tRTW_INFO(\"Current VHT STBC Setting = %02X\\n\", cur_stbc_cap);\n\t}\n\tptdls_sta->vhtpriv.stbc_cap = cur_stbc_cap;\n\n\t#ifdef CONFIG_BEAMFORMING\n\t/* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */\n\tif (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&\n\t    GET_VHT_CAPABILITY_ELE_SU_BFEE(data))\n\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);\n\n\t/* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */\n\tif (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&\n\t    GET_VHT_CAPABILITY_ELE_SU_BFER(data))\n\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);\n\tptdls_sta->vhtpriv.beamform_cap = cur_beamform_cap;\n\tptdls_sta->cmn.bf_info.vht_beamform_cap = cur_beamform_cap;\n\tif (cur_beamform_cap)\n\t\tRTW_INFO(\"Current VHT Beamforming Setting = %02X\\n\", cur_beamform_cap);\n\t#endif /*CONFIG_BEAMFORMING*/\n\n\t/* B23 B24 B25 Maximum A-MPDU Length Exponent */\n\tptdls_sta->vhtpriv.ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(data);\n\n\tpcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(data);\n\trtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));\n\ttx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);\n\trtw_vht_nss_to_mcsmap(tx_nss, ptdls_sta->vhtpriv.vht_mcs_map, pcap_mcs);\n\tptdls_sta->vhtpriv.vht_highest_rate = rtw_get_vht_highest_rate(ptdls_sta->vhtpriv.vht_mcs_map);\n}\n\nvoid rtw_tdls_process_vht_operation(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)\n{\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct registry_priv *regsty = adapter_to_regsty(padapter);\n\tu8 operation_bw = 0;\n\n\tif (GET_VHT_OPERATION_ELE_CHL_WIDTH(data) >= 1) {\n\n\t\toperation_bw = CHANNEL_WIDTH_80;\n\n\t\tif (hal_is_bw_support(padapter, operation_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, operation_bw)\n\t\t\t&& (operation_bw <= pmlmeext->cur_bwmode))\n\t\t\tptdls_sta->cmn.bw_mode = operation_bw;\n\t\telse\n\t\t\tptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode;\n\t} else\n\t\tptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode;\n}\n\nvoid rtw_tdls_process_vht_op_mode_notify(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)\n{\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct vht_priv\t\t*pvhtpriv = &pmlmepriv->vhtpriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct registry_priv *regsty = adapter_to_regsty(padapter);\n\tu8\ttarget_bw;\n\tu8\ttarget_rxss, current_rxss;\n\n\tif (pvhtpriv->vht_option == _FALSE)\n\t\treturn;\n\n\ttarget_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(data);\n\ttarget_rxss = (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(data) + 1);\n\n\tif (hal_is_bw_support(padapter, target_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw)\n\t\t&& (target_bw <= pmlmeext->cur_bwmode))\n\t\tptdls_sta->cmn.bw_mode = target_bw;\n\telse\n\t\tptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode;\n\n\tcurrent_rxss = rtw_vht_mcsmap_to_nss(ptdls_sta->vhtpriv.vht_mcs_map);\n\tif (target_rxss != current_rxss) {\n\t\tu8\tvht_mcs_map[2] = {};\n\n\t\trtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, ptdls_sta->vhtpriv.vht_mcs_map);\n\t\t_rtw_memcpy(ptdls_sta->vhtpriv.vht_mcs_map, vht_mcs_map, 2);\n\t}\n}\n\nu8 *rtw_tdls_set_aid(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)\n{\n\treturn rtw_set_ie(pframe, EID_AID, 2, (u8 *)&(padapter->mlmepriv.cur_network.aid), &(pattrib->pktlen));\n}\n\nu8 *rtw_tdls_set_vht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)\n{\n\tu32 ie_len = 0;\n\n\trtw_vht_use_default_setting(padapter);\n\n\tie_len = rtw_build_vht_cap_ie(padapter, pframe);\n\tpattrib->pktlen += ie_len;\n\n\treturn pframe + ie_len;\n}\n\nu8 *rtw_tdls_set_vht_operation(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib, u8 channel)\n{\n\tu32 ie_len = 0;\n\n\tie_len = rtw_build_vht_operation_ie(padapter, pframe, channel);\n\tpattrib->pktlen += ie_len;\n\n\treturn pframe + ie_len;\n}\n\nu8 *rtw_tdls_set_vht_op_mode_notify(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib, u8 bw)\n{\n\tu32 ie_len = 0;\n\n\tie_len = rtw_build_vht_op_mode_notify_ie(padapter, pframe, bw);\n\tpattrib->pktlen += ie_len;\n\n\treturn pframe + ie_len;\n}\n#endif\n\n\nu8 *rtw_tdls_set_sup_ch(_adapter *adapter, u8 *pframe, struct pkt_attrib *pattrib)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tu8 sup_ch[30 * 2] = {0x00}, ch_set_idx = 0, sup_ch_idx = 2;\n\n\twhile (ch_set_idx < rfctl->max_chan_nums && rfctl->channel_set[ch_set_idx].ChannelNum != 0) {\n\t\tif (rfctl->channel_set[ch_set_idx].ChannelNum <= 14) {\n\t\t\t/* TODO: fix 2.4G supported channel when channel doesn't start from 1 and continuous */\n\t\t\tsup_ch[0] = 1;\t/* First channel number */\n\t\t\tsup_ch[1] = rfctl->channel_set[ch_set_idx].ChannelNum;\t/* Number of channel */\n\t\t} else {\n\t\t\tsup_ch[sup_ch_idx++] = rfctl->channel_set[ch_set_idx].ChannelNum;\n\t\t\tsup_ch[sup_ch_idx++] = 1;\n\t\t}\n\t\tch_set_idx++;\n\t}\n\n\treturn rtw_set_ie(pframe, _SUPPORTED_CH_IE_, sup_ch_idx, sup_ch, &(pattrib->pktlen));\n}\n\nu8 *rtw_tdls_set_rsnie(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib *pattrib,  int init, struct sta_info *ptdls_sta)\n{\n\tu8 *p = NULL;\n\tint len = 0;\n\n\tif (ptxmgmt->len > 0)\n\t\tp = rtw_get_ie(ptxmgmt->buf, _RSN_IE_2_, &len, ptxmgmt->len);\n\n\tif (p != NULL)\n\t\treturn rtw_set_ie(pframe, _RSN_IE_2_, len, p + 2, &(pattrib->pktlen));\n\telse if (init == _TRUE)\n\t\treturn rtw_set_ie(pframe, _RSN_IE_2_, sizeof(TDLS_RSNIE), TDLS_RSNIE, &(pattrib->pktlen));\n\telse\n\t\treturn rtw_set_ie(pframe, _RSN_IE_2_, sizeof(ptdls_sta->TDLS_RSNIE), ptdls_sta->TDLS_RSNIE, &(pattrib->pktlen));\n}\n\nu8 *rtw_tdls_set_ext_cap(u8 *pframe, struct pkt_attrib *pattrib)\n{\n\treturn rtw_set_ie(pframe, _EXT_CAP_IE_ , sizeof(TDLS_EXT_CAPIE), TDLS_EXT_CAPIE, &(pattrib->pktlen));\n}\n\nu8 *rtw_tdls_set_qos_cap(u8 *pframe, struct pkt_attrib *pattrib)\n{\n\treturn rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, sizeof(TDLS_WMMIE), TDLS_WMMIE,  &(pattrib->pktlen));\n}\n\nu8 *rtw_tdls_set_ftie(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib *pattrib, u8 *ANonce, u8 *SNonce)\n{\n\tstruct wpa_tdls_ftie FTIE = {0};\n\tu8 *p = NULL;\n\tint len = 0;\n\n\tif (ptxmgmt->len > 0)\n\t\tp = rtw_get_ie(ptxmgmt->buf, _FTIE_, &len, ptxmgmt->len);\n\n\tif (p != NULL)\n\t\treturn rtw_set_ie(pframe, _FTIE_, len, p + 2, &(pattrib->pktlen));\n\telse {\n\t\tif (ANonce != NULL)\n\t\t\t_rtw_memcpy(FTIE.Anonce, ANonce, WPA_NONCE_LEN);\n\t\tif (SNonce != NULL)\n\t\t\t_rtw_memcpy(FTIE.Snonce, SNonce, WPA_NONCE_LEN);\n\n\t\treturn rtw_set_ie(pframe, _FTIE_, TDLS_FTIE_DATA_LEN,\n\t\t\t\t\t\t  (u8 *)FTIE.data, &(pattrib->pktlen));\n\t}\n}\n\nu8 *rtw_tdls_set_timeout_interval(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib *pattrib, int init, struct sta_info *ptdls_sta)\n{\n\tu8 timeout_itvl[5];\t/* set timeout interval to maximum value */\n\tu32 timeout_interval = TDLS_TPK_RESEND_COUNT;\n\tu8 *p = NULL;\n\tint len = 0;\n\n\tif (ptxmgmt->len > 0)\n\t\tp = rtw_get_ie(ptxmgmt->buf, _TIMEOUT_ITVL_IE_, &len, ptxmgmt->len);\n\n\tif (p != NULL)\n\t\treturn rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, len, p + 2, &(pattrib->pktlen));\n\telse {\n\t\t/* Timeout interval */\n\t\ttimeout_itvl[0] = 0x02;\n\t\tif (init == _TRUE)\n\t\t\t_rtw_memcpy(timeout_itvl + 1, &timeout_interval, 4);\n\t\telse\n\t\t\t_rtw_memcpy(timeout_itvl + 1, (u8 *)(&ptdls_sta->TDLS_PeerKey_Lifetime), 4);\n\n\t\treturn rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen));\n\t}\n}\n\nu8 *rtw_tdls_set_bss_coexist(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)\n{\n\tu8 iedata = 0;\n\n\tif (padapter->mlmepriv.num_FortyMHzIntolerant > 0)\n\t\tiedata |= BIT(2);\t/* 20 MHz BSS Width Request */\n\n\t/* Information Bit should be set by TDLS test plan 5.9 */\n\tiedata |= BIT(0);\n\treturn rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen));\n}\n\nu8 *rtw_tdls_set_payload_type(u8 *pframe, struct pkt_attrib *pattrib)\n{\n\tu8 payload_type = 0x02;\n\treturn rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen));\n}\n\nu8 *rtw_tdls_set_category(u8 *pframe, struct pkt_attrib *pattrib, u8 category)\n{\n\treturn rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n}\n\nu8 *rtw_tdls_set_action(u8 *pframe, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt)\n{\n\treturn rtw_set_fixed_ie(pframe, 1, &(ptxmgmt->action_code), &(pattrib->pktlen));\n}\n\nu8 *rtw_tdls_set_status_code(u8 *pframe, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt)\n{\n\treturn rtw_set_fixed_ie(pframe, 2, (u8 *)&(ptxmgmt->status_code), &(pattrib->pktlen));\n}\n\nu8 *rtw_tdls_set_dialog(u8 *pframe, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt)\n{\n\tu8 dialogtoken = 1;\n\tif (ptxmgmt->dialog_token)\n\t\treturn rtw_set_fixed_ie(pframe, 1, &(ptxmgmt->dialog_token), &(pattrib->pktlen));\n\telse\n\t\treturn rtw_set_fixed_ie(pframe, 1, &(dialogtoken), &(pattrib->pktlen));\n}\n\nu8 *rtw_tdls_set_reg_class(u8 *pframe, struct pkt_attrib *pattrib, struct sta_info *ptdls_sta)\n{\n\tu8 reg_class = 22;\n\treturn rtw_set_fixed_ie(pframe, 1, &(reg_class), &(pattrib->pktlen));\n}\n\nu8 *rtw_tdls_set_second_channel_offset(u8 *pframe, struct pkt_attrib *pattrib, u8 ch_offset)\n{\n\treturn rtw_set_ie(pframe, EID_SecondaryChnlOffset , 1, &ch_offset, &(pattrib->pktlen));\n}\n\nu8 *rtw_tdls_set_capability(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &pmlmeext->mlmext_info;\n\tu8 cap_from_ie[2] = {0};\n\n\t_rtw_memcpy(cap_from_ie, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2);\n\n\treturn rtw_set_fixed_ie(pframe, 2, cap_from_ie, &(pattrib->pktlen));\n}\n\nu8 *rtw_tdls_set_supported_rate(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)\n{\n\tu8 bssrate[NDIS_802_11_LENGTH_RATES_EX];\n\tint bssrate_len = 0;\n\tu8 more_supportedrates = 0;\n\n\trtw_set_supported_rate(bssrate, (padapter->registrypriv.wireless_mode == WIRELESS_MODE_MAX) ? padapter->mlmeextpriv.cur_wireless_mode : padapter->registrypriv.wireless_mode);\n\tbssrate_len = rtw_get_rateset_len(bssrate);\n\n\tif (bssrate_len > 8) {\n\t\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen));\n\t\tmore_supportedrates = 1;\n\t} else\n\t\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));\n\n\t/* extended supported rates */\n\tif (more_supportedrates == 1)\n\t\tpframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen));\n\n\treturn pframe;\n}\n\nu8 *rtw_tdls_set_sup_reg_class(u8 *pframe, struct pkt_attrib *pattrib)\n{\n\treturn rtw_set_ie(pframe, _SRC_IE_ , sizeof(TDLS_SRC), TDLS_SRC, &(pattrib->pktlen));\n}\n\nu8 *rtw_tdls_set_linkid(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib, u8 init)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tu8 link_id_addr[18] = {0};\n\n\t_rtw_memcpy(link_id_addr, get_my_bssid(&(pmlmeinfo->network)), 6);\n\n\tif (init == _TRUE) {\n\t\t_rtw_memcpy((link_id_addr + 6), pattrib->src, 6);\n\t\t_rtw_memcpy((link_id_addr + 12), pattrib->dst, 6);\n\t} else {\n\t\t_rtw_memcpy((link_id_addr + 6), pattrib->dst, 6);\n\t\t_rtw_memcpy((link_id_addr + 12), pattrib->src, 6);\n\t}\n\treturn rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen));\n}\n\n#ifdef CONFIG_TDLS_CH_SW\nu8 *rtw_tdls_set_target_ch(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)\n{\n\tu8 target_ch = 1;\n\tif (padapter->tdlsinfo.chsw_info.off_ch_num)\n\t\treturn rtw_set_fixed_ie(pframe, 1, &(padapter->tdlsinfo.chsw_info.off_ch_num), &(pattrib->pktlen));\n\telse\n\t\treturn rtw_set_fixed_ie(pframe, 1, &(target_ch), &(pattrib->pktlen));\n}\n\nu8 *rtw_tdls_set_ch_sw(u8 *pframe, struct pkt_attrib *pattrib, struct sta_info *ptdls_sta)\n{\n\tu8 ch_switch_timing[4] = {0};\n\tu16 switch_time = (ptdls_sta->ch_switch_time >= TDLS_CH_SWITCH_TIME * 1000) ?\n\t\t\t  ptdls_sta->ch_switch_time : TDLS_CH_SWITCH_TIME;\n\tu16 switch_timeout = (ptdls_sta->ch_switch_timeout >= TDLS_CH_SWITCH_TIMEOUT * 1000) ?\n\t\t     ptdls_sta->ch_switch_timeout : TDLS_CH_SWITCH_TIMEOUT;\n\n\t_rtw_memcpy(ch_switch_timing, &switch_time, 2);\n\t_rtw_memcpy(ch_switch_timing + 2, &switch_timeout, 2);\n\n\treturn rtw_set_ie(pframe, _CH_SWITCH_TIMING_,  4, ch_switch_timing, &(pattrib->pktlen));\n}\n\nvoid rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\n\tif (enable == _TRUE) {\n#ifdef CONFIG_TDLS_CH_SW_V2\n\t\tpHalData->ch_switch_offload = _TRUE;\n#endif\n\n#ifdef CONFIG_TDLS_CH_SW_BY_DRV\n\t\tpHalData->ch_switch_offload = _FALSE;\n#endif\n\t}\n\telse\n\t\tpHalData->ch_switch_offload = _FALSE;\n\t\n\tif (ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on) != enable)\n\t\tATOMIC_SET(&padapter->tdlsinfo.chsw_info.chsw_on, enable);\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_TDLS_BCN_EARLY_C2H_RPT, &enable);\n\tRTW_INFO(\"[TDLS] %s Bcn Early C2H Report\\n\", (enable == _TRUE) ? \"Start\" : \"Stop\");\n}\n\nvoid rtw_tdls_ch_sw_back_to_base_chnl(_adapter *padapter)\n{\n\tstruct mlme_priv *pmlmepriv;\n\tstruct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;\n\n\tpmlmepriv = &padapter->mlmepriv;\n\n\tif ((ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) &&\n\t    (padapter->mlmeextpriv.cur_channel != rtw_get_oper_ch(padapter)))\n\t\trtw_tdls_cmd(padapter, pchsw_info->addr, TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED);\n}\n\nstatic void rtw_tdls_chsw_oper_init(_adapter *padapter, u32 timeout_ms)\n{\n\tstruct submit_ctx\t*chsw_sctx = &padapter->tdlsinfo.chsw_info.chsw_sctx;\n\n\trtw_sctx_init(chsw_sctx, timeout_ms);\n}\n\nstatic int rtw_tdls_chsw_oper_wait(_adapter *padapter)\n{\n\tstruct submit_ctx\t*chsw_sctx = &padapter->tdlsinfo.chsw_info.chsw_sctx;\n\n\treturn rtw_sctx_wait(chsw_sctx, __func__);\n}\n\nvoid rtw_tdls_chsw_oper_done(_adapter *padapter)\n{\n\tstruct submit_ctx\t*chsw_sctx = &padapter->tdlsinfo.chsw_info.chsw_sctx;\n\n\trtw_sctx_done(&chsw_sctx);\n}\n\ns32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_type, u8 channel, u8 channel_offset, u16 bwmode, u16 ch_switch_time)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\tu8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\tu32 ch_sw_time_start, ch_sw_time_spent, wait_time;\n\tu8 take_care_iqk;\n\ts32 ret = _FAIL;\n\n\tch_sw_time_start = rtw_systime_to_ms(rtw_get_current_time());\n\n\t/* set mac_id sleep before channel switch */\n\trtw_hal_macid_sleep(padapter, ptdls_sta->cmn.mac_id);\n\n#if defined(CONFIG_TDLS_CH_SW_BY_DRV) || defined(CONFIG_TDLS_CH_SW_V2)\n\tset_channel_bwmode(padapter, channel, channel_offset, bwmode);\n\tret = _SUCCESS;\n#else\n\trtw_tdls_chsw_oper_init(padapter, TDLS_CH_SWITCH_OPER_OFFLOAD_TIMEOUT);\n\n\t/* channel switch IOs offload to FW */\n\tif (rtw_hal_ch_sw_oper_offload(padapter, channel, channel_offset, bwmode) == _SUCCESS) {\n\t\tif (rtw_tdls_chsw_oper_wait(padapter) == _SUCCESS) {\n\t\t\t/* set channel and bw related variables in driver */\n\t\t\t_enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);\n\n\t\t\trtw_set_oper_ch(padapter, channel);\n\t\t\trtw_set_oper_choffset(padapter, channel_offset);\n\t\t\trtw_set_oper_bw(padapter, bwmode);\n\n\t\t\tcenter_ch = rtw_get_center_ch(channel, bwmode, channel_offset);\n\t\t\tpHalData->current_channel = center_ch;\n\t\t\tpHalData->CurrentCenterFrequencyIndex1 = center_ch;\n\t\t\tpHalData->current_channel_bw = bwmode;\n\t\t\tpHalData->nCur40MhzPrimeSC = channel_offset;\n\n\t\t\tif (bwmode == CHANNEL_WIDTH_80) {\n\t\t\t\tif (center_ch > channel)\n\t\t\t\t\tchnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\t\t\telse if (center_ch < channel)\n\t\t\t\t\tchnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\t\t\telse\n\t\t\t\t\tchnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t\t}\n\t\t\tpHalData->nCur80MhzPrimeSC = chnl_offset80;\n\n\t\t\tpHalData->CurrentCenterFrequencyIndex1 = center_ch;\n\n\t\t\t_exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);\n\n\t\t\trtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);\n\t\t\tif (take_care_iqk == _TRUE)\n\t\t\t\trtw_hal_ch_sw_iqk_info_restore(padapter, CH_SW_USE_CASE_TDLS);\n\n\t\t\tret = _SUCCESS;\n\t\t} else\n\t\t\tRTW_INFO(\"[TDLS] chsw oper wait fail !!\\n\");\n\t}\n#endif\n\n\tif (ret == _SUCCESS) {\n\t\tch_sw_time_spent = rtw_systime_to_ms(rtw_get_current_time()) - ch_sw_time_start;\n\t\tif (chnl_type == TDLS_CH_SW_OFF_CHNL) {\n\t\t\tif ((u32)ch_switch_time / 1000 > ch_sw_time_spent)\n\t\t\t\twait_time = (u32)ch_switch_time / 1000 - ch_sw_time_spent;\n\t\t\telse\n\t\t\t\twait_time = 0;\n\n\t\t\tif (wait_time > 0)\n\t\t\t\trtw_msleep_os(wait_time);\n\t\t}\n\t}\n\n\t/* set mac_id wakeup after channel switch */\n\trtw_hal_macid_wakeup(padapter, ptdls_sta->cmn.mac_id);\n\n\treturn ret;\n}\n#endif\n\nu8 *rtw_tdls_set_wmm_params(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8 wmm_param_ele[24] = {0};\n\n\tif (&pmlmeinfo->WMM_param) {\n\t\t_rtw_memcpy(wmm_param_ele, WMM_PARA_OUI, 6);\n\t\tif (_rtw_memcmp(&pmlmeinfo->WMM_param, &wmm_param_ele[6], 18) == _TRUE)\n\t\t\t/* Use default WMM Param */\n\t\t\t_rtw_memcpy(wmm_param_ele + 6, (u8 *)&TDLS_WMM_PARAM_IE, sizeof(TDLS_WMM_PARAM_IE));\n\t\telse\n\t\t\t_rtw_memcpy(wmm_param_ele + 6, (u8 *)&pmlmeinfo->WMM_param, sizeof(pmlmeinfo->WMM_param));\n\t\treturn rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_,  24, wmm_param_ele, &(pattrib->pktlen));\n\t} else\n\t\treturn pframe;\n}\n\n#ifdef CONFIG_WFD\nvoid rtw_tdls_process_wfd_ie(struct tdls_info *ptdlsinfo, u8 *ptr, u8 length)\n{\n\tu8 *wfd_ie;\n\tu32\twfd_ielen = 0;\n\n\tif (!hal_chk_wl_func(tdls_info_to_adapter(ptdlsinfo), WL_FUNC_MIRACAST))\n\t\treturn;\n\n\t/* Try to get the TCP port information when receiving the negotiation response. */\n\n\twfd_ie = rtw_get_wfd_ie(ptr, length, NULL, &wfd_ielen);\n\twhile (wfd_ie) {\n\t\tu8 *attr_content;\n\t\tu32\tattr_contentlen = 0;\n\t\tint\ti;\n\n\t\tRTW_INFO(\"[%s] WFD IE Found!!\\n\", __FUNCTION__);\n\t\tattr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen);\n\t\tif (attr_content && attr_contentlen) {\n\t\t\tptdlsinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16(attr_content + 2);\n\t\t\tRTW_INFO(\"[%s] Peer PORT NUM = %d\\n\", __FUNCTION__, ptdlsinfo->wfd_info->peer_rtsp_ctrlport);\n\t\t}\n\n\t\tattr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_LOCAL_IP_ADDR, NULL, &attr_contentlen);\n\t\tif (attr_content && attr_contentlen) {\n\t\t\t_rtw_memcpy(ptdlsinfo->wfd_info->peer_ip_address, (attr_content + 1), 4);\n\t\t\tRTW_INFO(\"[%s] Peer IP = %02u.%02u.%02u.%02u\\n\", __FUNCTION__,\n\t\t\t\tptdlsinfo->wfd_info->peer_ip_address[0], ptdlsinfo->wfd_info->peer_ip_address[1],\n\t\t\t\tptdlsinfo->wfd_info->peer_ip_address[2], ptdlsinfo->wfd_info->peer_ip_address[3]);\n\t\t}\n\n\t\twfd_ie = rtw_get_wfd_ie(wfd_ie + wfd_ielen, (ptr + length) - (wfd_ie + wfd_ielen), NULL, &wfd_ielen);\n\t}\n}\n\nint issue_tunneled_probe_req(_adapter *padapter)\n{\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tu8 baddr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tstruct tdls_txmgmt txmgmt;\n\tint ret = _FAIL;\n\n\tRTW_INFO(\"[%s]\\n\", __FUNCTION__);\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\ttxmgmt.action_code = TUNNELED_PROBE_REQ;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\tpattrib = &pmgntframe->attrib;\n\n\tpmgntframe->frame_tag = DATA_FRAMETAG;\n\tpattrib->ether_type = 0x890d;\n\n\t_rtw_memcpy(pattrib->dst, baddr, ETH_ALEN);\n\t_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);\n\n\tupdate_tdls_attrib(padapter, pattrib);\n\tpattrib->qsel = pattrib->priority;\n\tif (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) {\n\t\trtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);\n\t\trtw_free_xmitframe(pxmitpriv, pmgntframe);\n\t\tgoto exit;\n\t}\n\tdump_mgntframe(padapter, pmgntframe);\n\tret = _SUCCESS;\nexit:\n\n\treturn ret;\n}\n\nint issue_tunneled_probe_rsp(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct tdls_txmgmt txmgmt;\n\tint ret = _FAIL;\n\n\tRTW_INFO(\"[%s]\\n\", __FUNCTION__);\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\ttxmgmt.action_code = TUNNELED_PROBE_RSP;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\tpattrib = &pmgntframe->attrib;\n\n\tpmgntframe->frame_tag = DATA_FRAMETAG;\n\tpattrib->ether_type = 0x890d;\n\n\t_rtw_memcpy(pattrib->dst, precv_frame->u.hdr.attrib.src, ETH_ALEN);\n\t_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);\n\n\tupdate_tdls_attrib(padapter, pattrib);\n\tpattrib->qsel = pattrib->priority;\n\tif (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) {\n\t\trtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);\n\t\trtw_free_xmitframe(pxmitpriv, pmgntframe);\n\t\tgoto exit;\n\t}\n\tdump_mgntframe(padapter, pmgntframe);\n\tret = _SUCCESS;\nexit:\n\n\treturn ret;\n}\n#endif /* CONFIG_WFD */\n\nint issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack)\n{\n\tstruct tdls_info\t*ptdlsinfo = &padapter->tdlsinfo;\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct sta_info *ptdls_sta = NULL;\n\t_irqL irqL;\n\tint ret = _FAIL;\n\t/* Retry timer should be set at least 301 sec, using TPK_count counting 301 times. */\n\tu32 timeout_interval = TDLS_TPK_RESEND_COUNT;\n\n\tRTW_INFO(\"[TDLS] %s\\n\", __FUNCTION__);\n\n\tif (rtw_tdls_is_setup_allowed(padapter) == _FALSE)\n\t\tgoto exit;\n\n\tif (IS_MCAST(ptxmgmt->peer))\n\t\tgoto exit;\n\n\tptdls_sta = rtw_get_stainfo(pstapriv, ptxmgmt->peer);\n\tif (ptdlsinfo->sta_maximum == _TRUE) {\n\t\tif (ptdls_sta == NULL)\n\t\t\tgoto exit;\n\t\telse if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE))\n\t\t\tgoto exit;\n\t}\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\tif (ptdls_sta == NULL) {\n\t\tptdls_sta = rtw_alloc_stainfo(pstapriv, ptxmgmt->peer);\n\t\tif (ptdls_sta == NULL) {\n\t\t\tRTW_INFO(\"[%s] rtw_alloc_stainfo fail\\n\", __FUNCTION__);\n\t\t\trtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);\n\t\t\trtw_free_xmitframe(pxmitpriv, pmgntframe);\n\t\t\tgoto exit;\n\t\t}\n\t\tptdlsinfo->sta_cnt++;\n\t}\n\n\tptxmgmt->action_code = TDLS_SETUP_REQUEST;\n\n\tpattrib = &pmgntframe->attrib;\n\tpmgntframe->frame_tag = DATA_FRAMETAG;\n\tpattrib->ether_type = 0x890d;\n\n\t_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);\n\t_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);\n\n\tupdate_tdls_attrib(padapter, pattrib);\n\n\tif (ptdlsinfo->sta_cnt == MAX_ALLOWED_TDLS_STA_NUM)\n\t\tptdlsinfo->sta_maximum  = _TRUE;\n\n\tptdls_sta->tdls_sta_state |= TDLS_RESPONDER_STATE;\n\n\tif (rtw_tdls_is_driver_setup(padapter) == _TRUE) {\n\t\tptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval;\n\t\t_set_timer(&ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME);\n\t}\n\n\tpattrib->qsel = pattrib->priority;\n\n\tif (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {\n\t\trtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);\n\t\trtw_free_xmitframe(pxmitpriv, pmgntframe);\n\t\tgoto exit;\n\t}\n\n\tif (wait_ack)\n\t\tret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);\n\telse {\n\t\tdump_mgntframe(padapter, pmgntframe);\n\t\tret = _SUCCESS;\n\t}\n\nexit:\n\n\treturn ret;\n}\n\nint _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta, u8 wait_ack)\n{\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\t_irqL irqL;\n\tint ret = _FAIL;\n\n\tRTW_INFO(\"[TDLS] %s\\n\", __FUNCTION__);\n\n\tptxmgmt->action_code = TDLS_TEARDOWN;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\trtw_mi_set_scan_deny(padapter, 550);\n\trtw_mi_scan_abort(padapter, _TRUE);\n\n\tpattrib = &pmgntframe->attrib;\n\n\tpmgntframe->frame_tag = DATA_FRAMETAG;\n\tpattrib->ether_type = 0x890d;\n\n\t_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);\n\t_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);\n\n\tif (ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_)\n\t\t_rtw_memcpy(pattrib->ra, ptxmgmt->peer, ETH_ALEN);\n\telse\n\t\t_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);\n\n\t_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);\n\n\tupdate_tdls_attrib(padapter, pattrib);\n\tpattrib->qsel = pattrib->priority;\n\tif (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {\n\t\trtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);\n\t\trtw_free_xmitframe(pxmitpriv, pmgntframe);\n\t\tgoto exit;\n\t}\n\n\tif (rtw_tdls_is_driver_setup(padapter) == _TRUE)\n\t\tif (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)\n\t\t\tif (pattrib->encrypt)\n\t\t\t\t_cancel_timer_ex(&ptdls_sta->TPK_timer);\n\n\tif (wait_ack)\n\t\tret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);\n\telse {\n\t\tdump_mgntframe(padapter, pmgntframe);\n\t\tret = _SUCCESS;\n\t}\n\nexit:\n\n\treturn ret;\n}\n\nint issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait_ack)\n{\n\tstruct sta_info *ptdls_sta = NULL;\n\tint ret = _FAIL;\n\n\tptdls_sta = rtw_get_stainfo(&(padapter->stapriv), ptxmgmt->peer);\n\tif (ptdls_sta == NULL) {\n\t\tRTW_INFO(\"No tdls_sta for tearing down\\n\");\n\t\tgoto exit;\n\t}\n\n\tret = _issue_tdls_teardown(padapter, ptxmgmt, ptdls_sta, wait_ack);\n\tif ((ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_) && (ret == _FAIL)) {\n\t\t/* Change status code and send teardown again via AP */\n\t\tptxmgmt->status_code = _RSON_TDLS_TEAR_TOOFAR_;\n\t\tret = _issue_tdls_teardown(padapter, ptxmgmt, ptdls_sta, wait_ack);\n\t}\n\n\tif (rtw_tdls_is_driver_setup(padapter)) {\n\t\trtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);\n\t\trtw_tdls_cmd(padapter, ptxmgmt->peer, TDLS_TEARDOWN_STA_LOCALLY_POST);\n\t}\n\nexit:\n\treturn ret;\n}\n\nint issue_tdls_dis_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt)\n{\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tint ret = _FAIL;\n\n\tRTW_INFO(\"[TDLS] %s\\n\", __FUNCTION__);\n\n\tptxmgmt->action_code = TDLS_DISCOVERY_REQUEST;\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\tpattrib = &pmgntframe->attrib;\n\tpmgntframe->frame_tag = DATA_FRAMETAG;\n\tpattrib->ether_type = 0x890d;\n\n\t_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);\n\t_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);\n\n\tupdate_tdls_attrib(padapter, pattrib);\n\tpattrib->qsel = pattrib->priority;\n\tif (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {\n\t\trtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);\n\t\trtw_free_xmitframe(pxmitpriv, pmgntframe);\n\t\tgoto exit;\n\t}\n\tdump_mgntframe(padapter, pmgntframe);\n\tRTW_INFO(\"issue tdls dis req\\n\");\n\n\tret = _SUCCESS;\nexit:\n\n\treturn ret;\n}\n\nint issue_tdls_setup_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt)\n{\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tint ret = _FAIL;\n\n\tRTW_INFO(\"[TDLS] %s\\n\", __FUNCTION__);\n\n\tptxmgmt->action_code = TDLS_SETUP_RESPONSE;\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\tpattrib = &pmgntframe->attrib;\n\tpmgntframe->frame_tag = DATA_FRAMETAG;\n\tpattrib->ether_type = 0x890d;\n\n\t_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);\n\t_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ra, get_bssid(&(padapter->mlmepriv)), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);\n\n\tupdate_tdls_attrib(padapter, pattrib);\n\tpattrib->qsel = pattrib->priority;\n\tif (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {\n\t\trtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);\n\t\trtw_free_xmitframe(pxmitpriv, pmgntframe);\n\t\tgoto exit;\n\t}\n\n\tdump_mgntframe(padapter, pmgntframe);\n\n\tret = _SUCCESS;\nexit:\n\n\treturn ret;\n\n}\n\nint issue_tdls_setup_cfm(_adapter *padapter, struct tdls_txmgmt *ptxmgmt)\n{\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tint ret = _FAIL;\n\n\tRTW_INFO(\"[TDLS] %s\\n\", __FUNCTION__);\n\n\tptxmgmt->action_code = TDLS_SETUP_CONFIRM;\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\tpattrib = &pmgntframe->attrib;\n\tpmgntframe->frame_tag = DATA_FRAMETAG;\n\tpattrib->ether_type = 0x890d;\n\n\t_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);\n\t_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ra, get_bssid(&padapter->mlmepriv), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);\n\n\tupdate_tdls_attrib(padapter, pattrib);\n\tpattrib->qsel = pattrib->priority;\n\tif (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {\n\t\trtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);\n\t\trtw_free_xmitframe(pxmitpriv, pmgntframe);\n\t\tgoto exit;\n\t}\n\n\tdump_mgntframe(padapter, pmgntframe);\n\n\tret = _SUCCESS;\nexit:\n\n\treturn ret;\n\n}\n\n/* TDLS Discovery Response frame is a management action frame */\nint issue_tdls_dis_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 privacy)\n{\n\tstruct xmit_frame\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t*pattrib;\n\tunsigned char\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t*fctrl;\n\tstruct xmit_priv\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tint ret = _FAIL;\n\n\tRTW_INFO(\"[TDLS] %s\\n\", __FUNCTION__);\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t/* unicast probe request frame */\n\t_rtw_memcpy(pwlanhdr->addr1, ptxmgmt->peer, ETH_ALEN);\n\t_rtw_memcpy(pattrib->dst, pwlanhdr->addr1, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pattrib->src, pwlanhdr->addr2, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ra, pwlanhdr->addr3, ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\trtw_build_tdls_dis_rsp_ies(padapter, pmgntframe, pframe, ptxmgmt, privacy);\n\n\tpattrib->nr_frags = 1;\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(padapter, pmgntframe);\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n\nint issue_tdls_peer_traffic_rsp(_adapter *padapter, struct sta_info *ptdls_sta, struct tdls_txmgmt *ptxmgmt)\n{\n\tstruct xmit_frame\t*pmgntframe;\n\tstruct pkt_attrib\t*pattrib;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct xmit_priv\t*pxmitpriv = &(padapter->xmitpriv);\n\tint ret = _FAIL;\n\n\tRTW_INFO(\"[TDLS] %s\\n\", __FUNCTION__);\n\n\tptxmgmt->action_code = TDLS_PEER_TRAFFIC_RESPONSE;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\tpattrib = &pmgntframe->attrib;\n\n\tpmgntframe->frame_tag = DATA_FRAMETAG;\n\tpattrib->ether_type = 0x890d;\n\n\t_rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN);\n\t_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ra, ptdls_sta->cmn.mac_addr, ETH_ALEN);\n\t_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);\n\n\tupdate_tdls_attrib(padapter, pattrib);\n\tpattrib->qsel = pattrib->priority;\n\n\tif (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {\n\t\trtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);\n\t\trtw_free_xmitframe(pxmitpriv, pmgntframe);\n\t\tgoto exit;\n\t}\n\n\tdump_mgntframe(padapter, pmgntframe);\n\tret = _SUCCESS;\n\nexit:\n\n\treturn ret;\n}\n\nint issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *ptdls_sta)\n{\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct tdls_txmgmt txmgmt;\n\tint ret = _FAIL;\n\n\tRTW_INFO(\"[TDLS] %s\\n\", __FUNCTION__);\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\ttxmgmt.action_code = TDLS_PEER_TRAFFIC_INDICATION;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\tpattrib = &pmgntframe->attrib;\n\n\tpmgntframe->frame_tag = DATA_FRAMETAG;\n\tpattrib->ether_type = 0x890d;\n\n\t_rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN);\n\t_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);\n\n\t/* PTI frame's priority should be AC_VO */\n\tpattrib->priority = 7;\n\n\tupdate_tdls_attrib(padapter, pattrib);\n\tpattrib->qsel = pattrib->priority;\n\tif (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) {\n\t\trtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);\n\t\trtw_free_xmitframe(pxmitpriv, pmgntframe);\n\t\tgoto exit;\n\t}\n\n\tdump_mgntframe(padapter, pmgntframe);\n\tret = _SUCCESS;\n\nexit:\n\n\treturn ret;\n}\n\n#ifdef CONFIG_TDLS_CH_SW\nint issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta)\n{\n\tstruct xmit_frame\t*pmgntframe;\n\tstruct pkt_attrib\t*pattrib;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct xmit_priv\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct tdls_txmgmt txmgmt;\n\tint ret = _FAIL;\n\n\tRTW_INFO(\"[TDLS] %s\\n\", __FUNCTION__);\n\n\tif (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {\n\t\tRTW_INFO(\"[TDLS] Ignore %s since channel switch is not allowed\\n\", __func__);\n\t\tgoto exit;\n\t}\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\ttxmgmt.action_code = TDLS_CHANNEL_SWITCH_REQUEST;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\tpattrib = &pmgntframe->attrib;\n\n\tpmgntframe->frame_tag = DATA_FRAMETAG;\n\tpattrib->ether_type = 0x890d;\n\n\t_rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN);\n\t_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ra, ptdls_sta->cmn.mac_addr, ETH_ALEN);\n\t_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);\n\n\tupdate_tdls_attrib(padapter, pattrib);\n\tpattrib->qsel = pattrib->priority;\n\tif (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) {\n\t\trtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);\n\t\trtw_free_xmitframe(pxmitpriv, pmgntframe);\n\t\tgoto exit;\n\t}\n\n\tdump_mgntframe(padapter, pmgntframe);\n\tret = _SUCCESS;\nexit:\n\n\treturn ret;\n}\n\nint issue_tdls_ch_switch_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack)\n{\n\tstruct xmit_frame\t*pmgntframe;\n\tstruct pkt_attrib\t*pattrib;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct xmit_priv\t*pxmitpriv = &(padapter->xmitpriv);\n\tint ret = _FAIL;\n\n\tRTW_INFO(\"[TDLS] %s\\n\", __FUNCTION__);\n\n\tif (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {\n\t\tRTW_INFO(\"[TDLS] Ignore %s since channel switch is not allowed\\n\", __func__);\n\t\tgoto exit;\n\t}\n\n\tptxmgmt->action_code = TDLS_CHANNEL_SWITCH_RESPONSE;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\tgoto exit;\n\n\tpattrib = &pmgntframe->attrib;\n\n\tpmgntframe->frame_tag = DATA_FRAMETAG;\n\tpattrib->ether_type = 0x890d;\n\n\t_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);\n\t_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ra, ptxmgmt->peer, ETH_ALEN);\n\t_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);\n\n\tupdate_tdls_attrib(padapter, pattrib);\n\tpattrib->qsel = pattrib->priority;\n\t/*\n\t\t_enter_critical_bh(&pxmitpriv->lock, &irqL);\n\t\tif(xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pmgntframe)==_TRUE){\n\t\t\t_exit_critical_bh(&pxmitpriv->lock, &irqL);\n\t\t\treturn _FALSE;\n\t\t}\n\t*/\n\tif (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {\n\t\trtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);\n\t\trtw_free_xmitframe(pxmitpriv, pmgntframe);\n\t\tgoto exit;\n\t}\n\n\tif (wait_ack)\n\t\tret = dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, 10);\n\telse {\n\t\tdump_mgntframe(padapter, pmgntframe);\n\t\tret = _SUCCESS;\n\t}\nexit:\n\n\treturn ret;\n}\n#endif\n\nint On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tstruct sta_info *ptdls_sta = NULL, *psta = rtw_get_stainfo(&(padapter->stapriv), get_bssid(&(padapter->mlmepriv)));\n\tstruct recv_priv *precvpriv = &(padapter->recvpriv);\n\tu8 *ptr = precv_frame->u.hdr.rx_data, *psa;\n\tstruct rx_pkt_attrib *pattrib = &(precv_frame->u.hdr.attrib);\n\tstruct tdls_info *ptdlsinfo = &(padapter->tdlsinfo);\n\tu8 empty_addr[ETH_ALEN] = { 0x00 };\n\tint rssi = 0;\n\tstruct tdls_txmgmt txmgmt;\n\tint ret = _SUCCESS;\n\n\tif (psta)\n\t\trssi = psta->cmn.rssi_stat.rssi;\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\t/* WFDTDLS: for sigma test, not to setup direct link automatically */\n\tptdlsinfo->dev_discovered = _TRUE;\n\n\tpsa = get_sa(ptr);\n\tptdls_sta = rtw_get_stainfo(&(padapter->stapriv), psa);\n\tif (ptdls_sta != NULL)\n\t\tptdls_sta->sta_stats.rx_tdls_disc_rsp_pkts++;\n\n#ifdef CONFIG_TDLS_AUTOSETUP\n\tif (ptdls_sta != NULL) {\n\t\t/* Record the tdls sta with lowest signal strength */\n\t\tif (ptdlsinfo->sta_maximum == _TRUE && ptdls_sta->alive_count >= 1) {\n\t\t\tif (_rtw_memcmp(ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN)) {\n\t\t\t\t_rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN);\n\t\t\t\tptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.rx_pwdb_all;\n\t\t\t} else {\n\t\t\t\tif (ptdlsinfo->ss_record.RxPWDBAll < pattrib->phy_info.rx_pwdb_all) {\n\t\t\t\t\t_rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN);\n\t\t\t\t\tptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.rx_pwdb_all;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else {\n\t\tif (ptdlsinfo->sta_maximum == _TRUE) {\n\t\t\tif (_rtw_memcmp(ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN)) {\n\t\t\t\t/* All traffics are busy, do not set up another direct link. */\n\t\t\t\tret = _FAIL;\n\t\t\t\tgoto exit;\n\t\t\t} else {\n\t\t\t\tif (pattrib->phy_info.rx_pwdb_all > ptdlsinfo->ss_record.RxPWDBAll) {\n\t\t\t\t\t_rtw_memcpy(txmgmt.peer, ptdlsinfo->ss_record.macaddr, ETH_ALEN);\n\t\t\t\t\t/* issue_tdls_teardown(padapter, ptdlsinfo->ss_record.macaddr, _FALSE); */\n\t\t\t\t} else {\n\t\t\t\t\tret = _FAIL;\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\n\t\tif (pattrib->phy_info.rx_pwdb_all + TDLS_SIGNAL_THRESH >= rssi) {\n\t\t\tRTW_INFO(\"pattrib->RxPWDBAll=%d, pdmpriv->undecorated_smoothed_pwdb=%d\\n\", pattrib->phy_info.rx_pwdb_all, rssi);\n\t\t\t_rtw_memcpy(txmgmt.peer, psa, ETH_ALEN);\n\t\t\tissue_tdls_setup_req(padapter, &txmgmt, _FALSE);\n\t\t}\n\t}\n#endif /* CONFIG_TDLS_AUTOSETUP */\n\nexit:\n\treturn ret;\n\n}\n\nsint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)\n{\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\tu8 *psa, *pmyid;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tu8 *ptr = precv_frame->u.hdr.rx_data;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\t_irqL irqL;\n\tstruct rx_pkt_attrib\t*prx_pkt_attrib = &precv_frame->u.hdr.attrib;\n\tu8 *prsnie, *ppairwise_cipher;\n\tu8 i, k;\n\tu8 ccmp_included = 0, rsnie_included = 0;\n\tu16 j, pairwise_count;\n\tu8 SNonce[32];\n\tu32 timeout_interval = TDLS_TPK_RESEND_COUNT;\n\tsint parsing_length;\t/* Frame body length, without icv_len */\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\tu8 FIXED_IE = 5;\n\tunsigned char\t\tsupportRate[16];\n\tint\t\t\t\tsupportRateNum = 0;\n\tstruct tdls_txmgmt txmgmt;\n\n\tif (rtw_tdls_is_setup_allowed(padapter) == _FALSE)\n\t\tgoto exit;\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\tpsa = get_sa(ptr);\n\n\tif (ptdlsinfo->sta_maximum == _TRUE) {\n\t\tif (ptdls_sta == NULL)\n\t\t\tgoto exit;\n\t\telse if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE))\n\t\t\tgoto exit;\n\t}\n\n\tpmyid = adapter_mac_addr(padapter);\n\tptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;\n\tparsing_length = ((union recv_frame *)precv_frame)->u.hdr.len\n\t\t\t - prx_pkt_attrib->hdrlen\n\t\t\t - prx_pkt_attrib->iv_len\n\t\t\t - prx_pkt_attrib->icv_len\n\t\t\t - LLC_HEADER_SIZE\n\t\t\t - ETH_TYPE_LEN\n\t\t\t - PAYLOAD_TYPE_LEN;\n\n\tif (ptdls_sta == NULL) {\n\t\tptdls_sta = rtw_alloc_stainfo(pstapriv, psa);\n\t\tif (ptdls_sta == NULL)\n\t\t\tgoto exit;\n\t\t\n\t\tptdlsinfo->sta_cnt++;\n\t}\n\telse {\n\t\tif (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {\n\t\t\t/* If the direct link is already set up */\n\t\t\t/* Process as re-setup after tear down */\n\t\t\tRTW_INFO(\"re-setup a direct link\\n\");\n\t\t}\n\t\t/* Already receiving TDLS setup request */\n\t\telse if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) {\n\t\t\tRTW_INFO(\"receive duplicated TDLS setup request frame in handshaking\\n\");\n\t\t\tgoto exit;\n\t\t}\n\t\t/* When receiving and sending setup_req to the same link at the same time */\n\t\t/* STA with higher MAC_addr would be initiator */\n\t\telse if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) {\n\t\t\tRTW_INFO(\"receive setup_req after sending setup_req\\n\");\n\t\t\tfor (i = 0; i < 6; i++) {\n\t\t\t\tif (*(pmyid + i) == *(psa + i)) {\n\t\t\t\t} else if (*(pmyid + i) > *(psa + i)) {\n\t\t\t\t\tptdls_sta->tdls_sta_state = TDLS_INITIATOR_STATE;\n\t\t\t\t\tbreak;\n\t\t\t\t} else if (*(pmyid + i) < *(psa + i))\n\t\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (ptdls_sta) {\n\t\ttxmgmt.dialog_token = *(ptr + 2);\t/* Copy dialog token */\n\t\ttxmgmt.status_code = _STATS_SUCCESSFUL_;\n\n\t\t/* Parsing information element */\n\t\tfor (j = FIXED_IE; j < parsing_length;) {\n\n\t\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);\n\n\t\t\tswitch (pIE->ElementID) {\n\t\t\tcase _SUPPORTEDRATES_IE_:\n\t\t\t\t_rtw_memcpy(supportRate, pIE->data, pIE->Length);\n\t\t\t\tsupportRateNum = pIE->Length;\n\t\t\t\tbreak;\n\t\t\tcase _COUNTRY_IE_:\n\t\t\t\tbreak;\n\t\t\tcase _EXT_SUPPORTEDRATES_IE_:\n\t\t\t\tif (supportRateNum < sizeof(supportRate)) {\n\t\t\t\t\t_rtw_memcpy(supportRate + supportRateNum, pIE->data, pIE->Length);\n\t\t\t\t\tsupportRateNum += pIE->Length;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase _SUPPORTED_CH_IE_:\n\t\t\t\tbreak;\n\t\t\tcase _RSN_IE_2_:\n\t\t\t\trsnie_included = 1;\n\t\t\t\tif (prx_pkt_attrib->encrypt) {\n\t\t\t\t\tprsnie = (u8 *)pIE;\n\t\t\t\t\t/* Check CCMP pairwise_cipher presence. */\n\t\t\t\t\tppairwise_cipher = prsnie + 10;\n\t\t\t\t\t_rtw_memcpy(ptdls_sta->TDLS_RSNIE, pIE->data, pIE->Length);\n\t\t\t\t\tpairwise_count = *(u16 *)(ppairwise_cipher - 2);\n\t\t\t\t\tfor (k = 0; k < pairwise_count; k++) {\n\t\t\t\t\t\tif (_rtw_memcmp(ppairwise_cipher + 4 * k, RSN_CIPHER_SUITE_CCMP, 4) == _TRUE)\n\t\t\t\t\t\t\tccmp_included = 1;\n\t\t\t\t\t}\n\n\t\t\t\t\tif (ccmp_included == 0)\n\t\t\t\t\t\ttxmgmt.status_code = _STATS_INVALID_RSNIE_;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase _EXT_CAP_IE_:\n\t\t\t\tbreak;\n\t\t\tcase _VENDOR_SPECIFIC_IE_:\n\t\t\t\tbreak;\n\t\t\tcase _FTIE_:\n\t\t\t\tif (prx_pkt_attrib->encrypt)\n\t\t\t\t\t_rtw_memcpy(SNonce, (ptr + j + 52), 32);\n\t\t\t\tbreak;\n\t\t\tcase _TIMEOUT_ITVL_IE_:\n\t\t\t\tif (prx_pkt_attrib->encrypt)\n\t\t\t\t\ttimeout_interval = cpu_to_le32(*(u32 *)(ptr + j + 3));\n\t\t\t\tbreak;\n\t\t\tcase _RIC_Descriptor_IE_:\n\t\t\t\tbreak;\n#ifdef CONFIG_80211N_HT\n\t\t\tcase _HT_CAPABILITY_IE_:\n\t\t\t\trtw_tdls_process_ht_cap(padapter, ptdls_sta, pIE->data, pIE->Length);\n\t\t\t\tbreak;\n#endif\n#ifdef CONFIG_80211AC_VHT\n\t\t\tcase EID_AID:\n\t\t\t\tbreak;\n\t\t\tcase EID_VHTCapability:\n\t\t\t\trtw_tdls_process_vht_cap(padapter, ptdls_sta, pIE->data, pIE->Length);\n\t\t\t\tbreak;\n#endif\n\t\t\tcase EID_BSSCoexistence:\n\t\t\t\tbreak;\n\t\t\tcase _LINK_ID_IE_:\n\t\t\t\tif (_rtw_memcmp(get_bssid(pmlmepriv), pIE->data, 6) == _FALSE)\n\t\t\t\t\ttxmgmt.status_code = _STATS_NOT_IN_SAME_BSS_;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tj += (pIE->Length + 2);\n\n\t\t}\n\n\t\t/* Check status code */\n\t\t/* If responder STA has/hasn't security on AP, but request hasn't/has RSNIE, it should reject */\n\t\tif (txmgmt.status_code == _STATS_SUCCESSFUL_) {\n\t\t\tif (rsnie_included && prx_pkt_attrib->encrypt == 0)\n\t\t\t\ttxmgmt.status_code = _STATS_SEC_DISABLED_;\n\t\t\telse if (rsnie_included == 0 && prx_pkt_attrib->encrypt)\n\t\t\t\ttxmgmt.status_code = _STATS_INVALID_PARAMETERS_;\n\n#ifdef CONFIG_WFD\n\t\t\t/* WFD test plan version 0.18.2 test item 5.1.5 */\n\t\t\t/* SoUT does not use TDLS if AP uses weak security */\n\t\t\tif (padapter->wdinfo.wfd_tdls_enable && (rsnie_included && prx_pkt_attrib->encrypt != _AES_))\n\t\t\t\ttxmgmt.status_code = _STATS_SEC_DISABLED_;\n#endif /* CONFIG_WFD */\n\t\t}\n\n\t\tptdls_sta->tdls_sta_state |= TDLS_INITIATOR_STATE;\n\t\tif (prx_pkt_attrib->encrypt) {\n\t\t\t_rtw_memcpy(ptdls_sta->SNonce, SNonce, 32);\n\n\t\t\tif (timeout_interval <= 300)\n\t\t\t\tptdls_sta->TDLS_PeerKey_Lifetime = TDLS_TPK_RESEND_COUNT;\n\t\t\telse\n\t\t\t\tptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval;\n\t\t}\n\n\t\t/* Update station supportRate */\n\t\tptdls_sta->bssratelen = supportRateNum;\n\t\t_rtw_memcpy(ptdls_sta->bssrateset, supportRate, supportRateNum);\n\n\t\t/* -2: AP + BC/MC sta, -4: default key */\n\t\tif (ptdlsinfo->sta_cnt == MAX_ALLOWED_TDLS_STA_NUM)\n\t\t\tptdlsinfo->sta_maximum = _TRUE;\n\n#ifdef CONFIG_WFD\n\t\trtw_tdls_process_wfd_ie(ptdlsinfo, ptr + FIXED_IE, parsing_length);\n#endif\n\n\t} else\n\t\tgoto exit;\n\n\t_rtw_memcpy(txmgmt.peer, prx_pkt_attrib->src, ETH_ALEN);\n\n\tif (rtw_tdls_is_driver_setup(padapter)) {\n\t\tissue_tdls_setup_rsp(padapter, &txmgmt);\n\n\t\tif (txmgmt.status_code == _STATS_SUCCESSFUL_)\n\t\t\t_set_timer(&ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME);\n\t\telse {\n\t\t\trtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);\n\t\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);\n\t\t}\n\t}\n\nexit:\n\n\treturn _SUCCESS;\n}\n\nint On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)\n{\n\tstruct registry_priv\t*pregistrypriv = &padapter->registrypriv;\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tu8 *ptr = precv_frame->u.hdr.rx_data;\n\t_irqL irqL;\n\tstruct rx_pkt_attrib\t*prx_pkt_attrib = &precv_frame->u.hdr.attrib;\n\tu8 *psa;\n\tu16 status_code = 0;\n\tsint parsing_length;\t/* Frame body length, without icv_len */\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\tu8 FIXED_IE = 7;\n\tu8 ANonce[32];\n\tu8  *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL, *ppairwise_cipher = NULL;\n\tu16 pairwise_count, j, k;\n\tu8 verify_ccmp = 0;\n\tunsigned char\t\tsupportRate[16];\n\tint\t\t\t\tsupportRateNum = 0;\n\tstruct tdls_txmgmt txmgmt;\n\tint ret = _SUCCESS;\n\tu32 timeout_interval = TDLS_TPK_RESEND_COUNT;\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\tpsa = get_sa(ptr);\n\n\tptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;\n\tparsing_length = ((union recv_frame *)precv_frame)->u.hdr.len\n\t\t\t - prx_pkt_attrib->hdrlen\n\t\t\t - prx_pkt_attrib->iv_len\n\t\t\t - prx_pkt_attrib->icv_len\n\t\t\t - LLC_HEADER_SIZE\n\t\t\t - ETH_TYPE_LEN\n\t\t\t - PAYLOAD_TYPE_LEN;\n\n\t_rtw_memcpy(&status_code, ptr + 2, 2);\n\n\tif (status_code != 0) {\n\t\tRTW_INFO(\"[TDLS] %s status_code = %d, free_tdls_sta\\n\", __FUNCTION__, status_code);\n\t\trtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);\n\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tstatus_code = 0;\n\n\t/* parsing information element */\n\tfor (j = FIXED_IE; j < parsing_length;) {\n\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);\n\n\t\tswitch (pIE->ElementID) {\n\t\tcase _SUPPORTEDRATES_IE_:\n\t\t\t_rtw_memcpy(supportRate, pIE->data, pIE->Length);\n\t\t\tsupportRateNum = pIE->Length;\n\t\t\tbreak;\n\t\tcase _COUNTRY_IE_:\n\t\t\tbreak;\n\t\tcase _EXT_SUPPORTEDRATES_IE_:\n\t\t\tif (supportRateNum < sizeof(supportRate)) {\n\t\t\t\t_rtw_memcpy(supportRate + supportRateNum, pIE->data, pIE->Length);\n\t\t\t\tsupportRateNum += pIE->Length;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase _SUPPORTED_CH_IE_:\n\t\t\tbreak;\n\t\tcase _RSN_IE_2_:\n\t\t\tprsnie = (u8 *)pIE;\n\t\t\t/* Check CCMP pairwise_cipher presence. */\n\t\t\tppairwise_cipher = prsnie + 10;\n\t\t\t_rtw_memcpy(&pairwise_count, (u16 *)(ppairwise_cipher - 2), 2);\n\t\t\tfor (k = 0; k < pairwise_count; k++) {\n\t\t\t\tif (_rtw_memcmp(ppairwise_cipher + 4 * k, RSN_CIPHER_SUITE_CCMP, 4) == _TRUE)\n\t\t\t\t\tverify_ccmp = 1;\n\t\t\t}\n\t\tcase _EXT_CAP_IE_:\n\t\t\tbreak;\n\t\tcase _VENDOR_SPECIFIC_IE_:\n\t\t\tif (_rtw_memcmp((u8 *)pIE + 2, WMM_INFO_OUI, 6) == _TRUE) {\n\t\t\t\t/* WMM Info ID and OUI */\n\t\t\t\tif ((pregistrypriv->wmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE))\n\t\t\t\t\tptdls_sta->qos_option = _TRUE;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase _FTIE_:\n\t\t\tpftie = (u8 *)pIE;\n\t\t\t_rtw_memcpy(ANonce, (ptr + j + 20), 32);\n\t\t\tbreak;\n\t\tcase _TIMEOUT_ITVL_IE_:\n\t\t\tptimeout_ie = (u8 *)pIE;\n\t\t\ttimeout_interval = cpu_to_le32(*(u32 *)(ptimeout_ie + 3));\n\t\t\tbreak;\n\t\tcase _RIC_Descriptor_IE_:\n\t\t\tbreak;\n#ifdef CONFIG_80211N_HT\n\t\tcase _HT_CAPABILITY_IE_:\n\t\t\trtw_tdls_process_ht_cap(padapter, ptdls_sta, pIE->data, pIE->Length);\n\t\t\tbreak;\n#endif\n#ifdef CONFIG_80211AC_VHT\n\t\tcase EID_AID:\n\t\t\t/* todo in the future if necessary */\n\t\t\tbreak;\n\t\tcase EID_VHTCapability:\n\t\t\trtw_tdls_process_vht_cap(padapter, ptdls_sta, pIE->data, pIE->Length);\n\t\t\tbreak;\n\t\tcase EID_OpModeNotification:\n\t\t\trtw_tdls_process_vht_op_mode_notify(padapter, ptdls_sta, pIE->data, pIE->Length);\n\t\t\tbreak;\n#endif\n\t\tcase EID_BSSCoexistence:\n\t\t\tbreak;\n\t\tcase _LINK_ID_IE_:\n\t\t\tplinkid_ie = (u8 *)pIE;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tj += (pIE->Length + 2);\n\n\t}\n\n\tptdls_sta->bssratelen = supportRateNum;\n\t_rtw_memcpy(ptdls_sta->bssrateset, supportRate, supportRateNum);\n\t_rtw_memcpy(ptdls_sta->ANonce, ANonce, 32);\n\n#ifdef CONFIG_WFD\n\trtw_tdls_process_wfd_ie(ptdlsinfo, ptr + FIXED_IE, parsing_length);\n#endif\n\n\tif (prx_pkt_attrib->encrypt) {\n\t\tif (verify_ccmp == 1) {\n\t\t\ttxmgmt.status_code = _STATS_SUCCESSFUL_;\n\t\t\tif (rtw_tdls_is_driver_setup(padapter) == _TRUE) {\n\t\t\t\twpa_tdls_generate_tpk(padapter, ptdls_sta);\n\t\t\t\tif (tdls_verify_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL) {\n\t\t\t\t\tRTW_INFO(\"[TDLS] %s tdls_verify_mic fail, free_tdls_sta\\n\", __FUNCTION__);\n\t\t\t\t\trtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);\n\t\t\t\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);\n\t\t\t\t\tret = _FAIL;\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t\tptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval;\n\t\t\t}\n\t\t} else\n\t\t\ttxmgmt.status_code = _STATS_INVALID_RSNIE_;\n\t} else\n\t\ttxmgmt.status_code = _STATS_SUCCESSFUL_;\n\n\tif (rtw_tdls_is_driver_setup(padapter) == _TRUE) {\n\t\t_rtw_memcpy(txmgmt.peer, prx_pkt_attrib->src, ETH_ALEN);\n\t\tissue_tdls_setup_cfm(padapter, &txmgmt);\n\n\t\tif (txmgmt.status_code == _STATS_SUCCESSFUL_) {\n\t\t\trtw_tdls_set_link_established(padapter, _TRUE);\n\n\t\t\tif (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) {\n\t\t\t\tptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE;\n\t\t\t\tptdls_sta->state |= _FW_LINKED;\n\t\t\t\t_cancel_timer_ex(&ptdls_sta->handshake_timer);\n\t\t\t}\n\n\t\t\tif (prx_pkt_attrib->encrypt)\n\t\t\t\trtw_tdls_set_key(padapter, ptdls_sta);\n\n\t\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ESTABLISHED);\n\n\t\t}\n\t}\n\nexit:\n\tif (rtw_tdls_is_driver_setup(padapter) == _TRUE)\n\t\treturn ret;\n\telse\n\t\treturn _SUCCESS;\n\n}\n\nint On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)\n{\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tu8 *ptr = precv_frame->u.hdr.rx_data;\n\t_irqL irqL;\n\tstruct rx_pkt_attrib\t*prx_pkt_attrib = &precv_frame->u.hdr.attrib;\n\tu8 *psa;\n\tu16 status_code = 0;\n\tsint parsing_length;\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\tu8 FIXED_IE = 5;\n\tu8  *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL, *ppairwise_cipher = NULL;\n\tu16 j, pairwise_count;\n\tint ret = _SUCCESS;\n\n\tpsa = get_sa(ptr);\n\n\tptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;\n\tparsing_length = ((union recv_frame *)precv_frame)->u.hdr.len\n\t\t\t - prx_pkt_attrib->hdrlen\n\t\t\t - prx_pkt_attrib->iv_len\n\t\t\t - prx_pkt_attrib->icv_len\n\t\t\t - LLC_HEADER_SIZE\n\t\t\t - ETH_TYPE_LEN\n\t\t\t - PAYLOAD_TYPE_LEN;\n\n\t_rtw_memcpy(&status_code, ptr + 2, 2);\n\n\tif (status_code != 0) {\n\t\tRTW_INFO(\"[%s] status_code = %d\\n, free_tdls_sta\", __FUNCTION__, status_code);\n\t\trtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);\n\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t/* Parsing information element */\n\tfor (j = FIXED_IE; j < parsing_length;) {\n\n\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);\n\n\t\tswitch (pIE->ElementID) {\n\t\tcase _RSN_IE_2_:\n\t\t\tprsnie = (u8 *)pIE;\n\t\t\tbreak;\n\t\tcase _VENDOR_SPECIFIC_IE_:\n\t\t\tif (_rtw_memcmp((u8 *)pIE + 2, WMM_PARA_OUI, 6) == _TRUE) {\n\t\t\t\t/* WMM Parameter ID and OUI */\n\t\t\t\tptdls_sta->qos_option = _TRUE;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase _FTIE_:\n\t\t\tpftie = (u8 *)pIE;\n\t\t\tbreak;\n\t\tcase _TIMEOUT_ITVL_IE_:\n\t\t\tptimeout_ie = (u8 *)pIE;\n\t\t\tbreak;\n#ifdef CONFIG_80211N_HT\n\t\tcase _HT_EXTRA_INFO_IE_:\n\t\t\tbreak;\n#endif\n#ifdef CONFIG_80211AC_VHT\n\t\tcase EID_VHTOperation:\n\t\t\trtw_tdls_process_vht_operation(padapter, ptdls_sta, pIE->data, pIE->Length);\n\t\t\tbreak;\n\t\tcase EID_OpModeNotification:\n\t\t\trtw_tdls_process_vht_op_mode_notify(padapter, ptdls_sta, pIE->data, pIE->Length);\n\t\t\tbreak;\n#endif\n\t\tcase _LINK_ID_IE_:\n\t\t\tplinkid_ie = (u8 *)pIE;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tj += (pIE->Length + 2);\n\n\t}\n\n\tif (prx_pkt_attrib->encrypt) {\n\t\t/* Verify mic in FTIE MIC field */\n\t\tif (rtw_tdls_is_driver_setup(padapter) &&\n\t\t    (tdls_verify_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL)) {\n\t\t\trtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);\n\t\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);\n\t\t\tret = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\tif (rtw_tdls_is_driver_setup(padapter)) {\n\t\trtw_tdls_set_link_established(padapter, _TRUE);\n\n\t\tif (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) {\n\t\t\tptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE;\n\t\t\tptdls_sta->state |= _FW_LINKED;\n\t\t\t_cancel_timer_ex(&ptdls_sta->handshake_timer);\n\t\t}\n\n\t\tif (prx_pkt_attrib->encrypt) {\n\t\t\trtw_tdls_set_key(padapter, ptdls_sta);\n\n\t\t\t/* Start  TPK timer */\n\t\t\tptdls_sta->TPK_count = 0;\n\t\t\t_set_timer(&ptdls_sta->TPK_timer, ONE_SEC);\n\t\t}\n\n\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ESTABLISHED);\n\t}\n\nexit:\n\treturn ret;\n\n}\n\nint On_TDLS_Dis_Req(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tstruct rx_pkt_attrib\t*prx_pkt_attrib = &precv_frame->u.hdr.attrib;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct sta_info *psta_ap;\n\tu8 *ptr = precv_frame->u.hdr.rx_data;\n\tsint parsing_length;\t/* Frame body length, without icv_len */\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\tu8 FIXED_IE = 3, *dst;\n\tu16 j;\n\tstruct tdls_txmgmt txmgmt;\n\tint ret = _SUCCESS;\n\n\tif (rtw_tdls_is_driver_setup(padapter) == _FALSE)\n\t\tgoto exit;\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\tptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;\n\ttxmgmt.dialog_token = *(ptr + 2);\n\t_rtw_memcpy(&txmgmt.peer, precv_frame->u.hdr.attrib.src, ETH_ALEN);\n\ttxmgmt.action_code = TDLS_DISCOVERY_RESPONSE;\n\tparsing_length = ((union recv_frame *)precv_frame)->u.hdr.len\n\t\t\t - prx_pkt_attrib->hdrlen\n\t\t\t - prx_pkt_attrib->iv_len\n\t\t\t - prx_pkt_attrib->icv_len\n\t\t\t - LLC_HEADER_SIZE\n\t\t\t - ETH_TYPE_LEN\n\t\t\t - PAYLOAD_TYPE_LEN;\n\n\t/* Parsing information element */\n\tfor (j = FIXED_IE; j < parsing_length;) {\n\n\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);\n\n\t\tswitch (pIE->ElementID) {\n\t\tcase _LINK_ID_IE_:\n\t\t\tpsta_ap = rtw_get_stainfo(pstapriv, pIE->data);\n\t\t\tif (psta_ap == NULL)\n\t\t\t\tgoto exit;\n\t\t\tdst = pIE->data + 12;\n\t\t\tif (MacAddr_isBcst(dst) == _FALSE && (_rtw_memcmp(adapter_mac_addr(padapter), dst, ETH_ALEN) == _FALSE))\n\t\t\t\tgoto exit;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tj += (pIE->Length + 2);\n\n\t}\n\n\tissue_tdls_dis_rsp(padapter, &txmgmt, prx_pkt_attrib->privacy);\n\nexit:\n\treturn ret;\n\n}\n\nint On_TDLS_Teardown(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)\n{\n\tu8 *ptr = precv_frame->u.hdr.rx_data;\n\tstruct rx_pkt_attrib\t*prx_pkt_attrib = &precv_frame->u.hdr.attrib;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct sta_priv\t*pstapriv = &padapter->stapriv;\n\t_irqL irqL;\n\tu8 reason;\n\n\treason = *(ptr + prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN + 2);\n\tRTW_INFO(\"[TDLS] %s Reason code(%d)\\n\", __FUNCTION__, reason);\n\n\tif (rtw_tdls_is_driver_setup(padapter)) {\n\t\trtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);\n\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);\n\t}\n\n\treturn _SUCCESS;\n\n}\n\n#if 0\nu8 TDLS_check_ch_state(uint state)\n{\n\tif (state & TDLS_CH_SWITCH_ON_STATE &&\n\t    state & TDLS_PEER_AT_OFF_STATE) {\n\t\tif (state & TDLS_PEER_SLEEP_STATE)\n\t\t\treturn 2;\t/* U-APSD + ch. switch */\n\t\telse\n\t\t\treturn 1;\t/* ch. switch */\n\t} else\n\t\treturn 0;\n}\n#endif\n\nint On_TDLS_Peer_Traffic_Indication(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)\n{\n\tstruct rx_pkt_attrib\t*pattrib = &precv_frame->u.hdr.attrib;\n\tu8 *ptr = precv_frame->u.hdr.rx_data;\n\tstruct tdls_txmgmt txmgmt;\n\n\tptr += pattrib->hdrlen + pattrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\n\t\ttxmgmt.dialog_token = *(ptr + 2);\n\t\tissue_tdls_peer_traffic_rsp(padapter, ptdls_sta, &txmgmt);\n\t\t/* issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 0, 0); */\n\n\treturn _SUCCESS;\n}\n\n/* We process buffered data for 1. U-APSD, 2. ch. switch, 3. U-APSD + ch. switch here */\nint On_TDLS_Peer_Traffic_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)\n{\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct rx_pkt_attrib\t*pattrib = &precv_frame->u.hdr.attrib;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tu8 wmmps_ac = 0;\n\t/* u8 state=TDLS_check_ch_state(ptdls_sta->tdls_sta_state); */\n\tint i;\n\n\tptdls_sta->sta_stats.rx_data_pkts++;\n\n\tptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE);\n\n\t/* Check 4-AC queue bit */\n\tif (ptdls_sta->uapsd_vo || ptdls_sta->uapsd_vi || ptdls_sta->uapsd_be || ptdls_sta->uapsd_bk)\n\t\twmmps_ac = 1;\n\n\t/* If it's a direct link and have buffered frame */\n\tif (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {\n\t\tif (wmmps_ac) {\n\t\t\t_irqL irqL;\n\t\t\t_list\t*xmitframe_plist, *xmitframe_phead;\n\t\t\tstruct xmit_frame *pxmitframe = NULL;\n\n\t\t\t_enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);\n\n\t\t\txmitframe_phead = get_list_head(&ptdls_sta->sleep_q);\n\t\t\txmitframe_plist = get_next(xmitframe_phead);\n\n\t\t\t/* transmit buffered frames */\n\t\t\twhile (rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist) == _FALSE) {\n\t\t\t\tpxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);\n\t\t\t\txmitframe_plist = get_next(xmitframe_plist);\n\t\t\t\trtw_list_delete(&pxmitframe->list);\n\n\t\t\t\tptdls_sta->sleepq_len--;\n\t\t\t\tptdls_sta->sleepq_ac_len--;\n\t\t\t\tif (ptdls_sta->sleepq_len > 0) {\n\t\t\t\t\tpxmitframe->attrib.mdata = 1;\n\t\t\t\t\tpxmitframe->attrib.eosp = 0;\n\t\t\t\t} else {\n\t\t\t\t\tpxmitframe->attrib.mdata = 0;\n\t\t\t\t\tpxmitframe->attrib.eosp = 1;\n\t\t\t\t}\n\t\t\t\tpxmitframe->attrib.triggered = 1;\n\n\t\t\t\trtw_hal_xmitframe_enqueue(padapter, pxmitframe);\n\t\t\t}\n\n\t\t\tif (ptdls_sta->sleepq_len == 0)\n\t\t\t\tRTW_INFO(\"no buffered packets for tdls to xmit\\n\");\n\t\t\telse {\n\t\t\t\tRTW_INFO(\"error!psta->sleepq_len=%d\\n\", ptdls_sta->sleepq_len);\n\t\t\t\tptdls_sta->sleepq_len = 0;\n\t\t\t}\n\n\t\t\t_exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);\n\n\t\t}\n\n\t}\n\n\treturn _SUCCESS;\n}\n\n#ifdef CONFIG_TDLS_CH_SW\nsint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)\n{\n\tstruct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tu8 *ptr = precv_frame->u.hdr.rx_data;\n\tstruct rx_pkt_attrib\t*prx_pkt_attrib = &precv_frame->u.hdr.attrib;\n\tsint parsing_length;\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\tu8 FIXED_IE = 4;\n\tu16 j;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tu8 zaddr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};\n\tu16 switch_time = TDLS_CH_SWITCH_TIME * 1000, switch_timeout = TDLS_CH_SWITCH_TIMEOUT * 1000;\n\tu8 take_care_iqk;\n\n\tif (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {\n\t\tRTW_INFO(\"[TDLS] Ignore %s since channel switch is not allowed\\n\", __func__);\n\t\treturn _FAIL;\n\t}\n\n\tptdls_sta->ch_switch_time = switch_time;\n\tptdls_sta->ch_switch_timeout = switch_timeout;\n\n\tptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;\n\tparsing_length = ((union recv_frame *)precv_frame)->u.hdr.len\n\t\t\t - prx_pkt_attrib->hdrlen\n\t\t\t - prx_pkt_attrib->iv_len\n\t\t\t - prx_pkt_attrib->icv_len\n\t\t\t - LLC_HEADER_SIZE\n\t\t\t - ETH_TYPE_LEN\n\t\t\t - PAYLOAD_TYPE_LEN;\n\n\tpchsw_info->off_ch_num = *(ptr + 2);\n\n\tif ((*(ptr + 2) == 2) && (hal_is_band_support(padapter, BAND_ON_5G)))\n\t\tpchsw_info->off_ch_num = 44;\n\n\tif (pchsw_info->off_ch_num != pmlmeext->cur_channel)\n\t\tpchsw_info->delay_switch_back = _FALSE;\n\n\t/* Parsing information element */\n\tfor (j = FIXED_IE; j < parsing_length;) {\n\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);\n\n\t\tswitch (pIE->ElementID) {\n\t\tcase EID_SecondaryChnlOffset:\n\t\t\tswitch (*(pIE->data)) {\n\t\t\tcase EXTCHNL_OFFSET_UPPER:\n\t\t\t\tpchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\t\t\tbreak;\n\n\t\t\tcase EXTCHNL_OFFSET_LOWER:\n\t\t\t\tpchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\t\t\tbreak;\n\n\t\t\tdefault:\n\t\t\t\tpchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase _LINK_ID_IE_:\n\t\t\tbreak;\n\t\tcase _CH_SWITCH_TIMING_:\n\t\t\tptdls_sta->ch_switch_time = (RTW_GET_LE16(pIE->data) >= TDLS_CH_SWITCH_TIME * 1000) ?\n\t\t\t\tRTW_GET_LE16(pIE->data) : TDLS_CH_SWITCH_TIME * 1000;\n\t\t\tptdls_sta->ch_switch_timeout = (RTW_GET_LE16(pIE->data + 2) >= TDLS_CH_SWITCH_TIMEOUT * 1000) ?\n\t\t\t\tRTW_GET_LE16(pIE->data + 2) : TDLS_CH_SWITCH_TIMEOUT * 1000;\n\t\t\tRTW_INFO(\"[TDLS] %s ch_switch_time:%d, ch_switch_timeout:%d\\n\"\n\t\t\t\t, __FUNCTION__, RTW_GET_LE16(pIE->data), RTW_GET_LE16(pIE->data + 2));\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tj += (pIE->Length + 2);\n\t}\n\n\trtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);\n\tif (take_care_iqk == _TRUE) {\n\t\tu8 central_chnl;\n\t\tu8 bw_mode;\n\n\t\tbw_mode = (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20;\n\t\tcentral_chnl = rtw_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset);\n\t\tif (rtw_hal_ch_sw_iqk_info_search(padapter, central_chnl, bw_mode) < 0) {\n\t\t\tif (!(pchsw_info->ch_sw_state & TDLS_CH_SWITCH_PREPARE_STATE))\n\t\t\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_PREPARE);\n\n\t\t\treturn _FAIL;\n\t\t}\n\t}\n\n\t/* cancel ch sw monitor timer for responder */\n\tif (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))\n\t\t_cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer);\n\n\tif (_rtw_memcmp(pchsw_info->addr, zaddr, ETH_ALEN) == _TRUE)\n\t\t_rtw_memcpy(pchsw_info->addr, ptdls_sta->cmn.mac_addr, ETH_ALEN);\n\n\tif (ATOMIC_READ(&pchsw_info->chsw_on) == _FALSE)\n\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);\n\n\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_RESP);\n\n\treturn _SUCCESS;\n}\n\nsint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)\n{\n\tstruct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tu8 *ptr = precv_frame->u.hdr.rx_data;\n\tstruct rx_pkt_attrib\t*prx_pkt_attrib = &precv_frame->u.hdr.attrib;\n\tsint parsing_length;\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\tu8 FIXED_IE = 4;\n\tu16 status_code, j, switch_time, switch_timeout;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tint ret = _SUCCESS;\n\n\tif (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {\n\t\tRTW_INFO(\"[TDLS] Ignore %s since channel switch is not allowed\\n\", __func__);\n\t\treturn _SUCCESS;\n\t}\n\n\t/* If we receive Unsolicited TDLS Channel Switch Response when channel switch is running, */\n\t/* we will go back to base channel and terminate this channel switch procedure */\n\tif (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) {\n\t\tif (pmlmeext->cur_channel != rtw_get_oper_ch(padapter)) {\n\t\t\tRTW_INFO(\"[TDLS] Rx unsolicited channel switch response\\n\");\n\t\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL);\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\tptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;\n\tparsing_length = ((union recv_frame *)precv_frame)->u.hdr.len\n\t\t\t - prx_pkt_attrib->hdrlen\n\t\t\t - prx_pkt_attrib->iv_len\n\t\t\t - prx_pkt_attrib->icv_len\n\t\t\t - LLC_HEADER_SIZE\n\t\t\t - ETH_TYPE_LEN\n\t\t\t - PAYLOAD_TYPE_LEN;\n\n\t_rtw_memcpy(&status_code, ptr + 2, 2);\n\n\tif (status_code != 0) {\n\t\tRTW_INFO(\"[TDLS] %s status_code:%d\\n\", __func__, status_code);\n\t\tpchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE);\n\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END);\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t/* Parsing information element */\n\tfor (j = FIXED_IE; j < parsing_length;) {\n\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);\n\n\t\tswitch (pIE->ElementID) {\n\t\tcase _LINK_ID_IE_:\n\t\t\tbreak;\n\t\tcase _CH_SWITCH_TIMING_:\n\t\t\t_rtw_memcpy(&switch_time, pIE->data, 2);\n\t\t\tif (switch_time > ptdls_sta->ch_switch_time)\n\t\t\t\t_rtw_memcpy(&ptdls_sta->ch_switch_time, &switch_time, 2);\n\n\t\t\t_rtw_memcpy(&switch_timeout, pIE->data + 2, 2);\n\t\t\tif (switch_timeout > ptdls_sta->ch_switch_timeout)\n\t\t\t\t_rtw_memcpy(&ptdls_sta->ch_switch_timeout, &switch_timeout, 2);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tj += (pIE->Length + 2);\n\t}\n\n\tif ((pmlmeext->cur_channel == rtw_get_oper_ch(padapter)) &&\n\t    (pchsw_info->ch_sw_state & TDLS_WAIT_CH_RSP_STATE)) {\n\t\tif (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE)\n\t\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_OFF_CHNL);\n\t}\n\nexit:\n\treturn ret;\n}\n#endif /* CONFIG_TDLS_CH_SW */\n\n#ifdef CONFIG_WFD\nvoid wfd_ie_tdls(_adapter *padapter, u8 *pframe, u32 *pktlen)\n{\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wifi_display_info\t*pwfd_info = padapter->tdlsinfo.wfd_info;\n\tu8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };\n\tu32 wfdielen = 0;\n\tu16 v16 = 0;\n\n\tif (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))\n\t\treturn;\n\n\t/* WFD OUI */\n\twfdielen = 0;\n\twfdie[wfdielen++] = 0x50;\n\twfdie[wfdielen++] = 0x6F;\n\twfdie[wfdielen++] = 0x9A;\n\twfdie[wfdielen++] = 0x0A;\t/* WFA WFD v1.0 */\n\n\t/*\n\t *\tCommented by Albert 20110825\n\t *\tAccording to the WFD Specification, the negotiation request frame should contain 3 WFD attributes\n\t *\t1. WFD Device Information\n\t *\t2. Associated BSSID ( Optional )\n\t *\t3. Local IP Adress ( Optional )\n\t */\n\n\t/* WFD Device Information ATTR */\n\t/* Type: */\n\twfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;\n\n\t/* Length: */\n\t/* Note: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/* Value1: */\n\t/* WFD device information */\n\t/* available for WFD session + Preferred TDLS + WSD ( WFD Service Discovery ) */\n\tv16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL\n\t\t| WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_WSD;\n\tRTW_PUT_BE16(wfdie + wfdielen, v16);\n\twfdielen += 2;\n\n\t/* Value2: */\n\t/* Session Management Control Port */\n\t/* Default TCP port for RTSP messages is 554 */\n\tRTW_PUT_BE16(wfdie + wfdielen, pwfd_info->tdls_rtsp_ctrlport);\n\twfdielen += 2;\n\n\t/* Value3: */\n\t/* WFD Device Maximum Throughput */\n\t/* 300Mbps is the maximum throughput */\n\tRTW_PUT_BE16(wfdie + wfdielen, 300);\n\twfdielen += 2;\n\n\t/* Associated BSSID ATTR */\n\t/* Type: */\n\twfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;\n\n\t/* Length: */\n\t/* Note: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0006);\n\twfdielen += 2;\n\n\t/* Value: */\n\t/* Associated BSSID */\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);\n\telse\n\t\t_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);\n\n\t/* Local IP Address ATTR */\n\twfdie[wfdielen++] = WFD_ATTR_LOCAL_IP_ADDR;\n\n\t/* Length: */\n\t/* Note: In the WFD specification, the size of length field is 2. */\n\tRTW_PUT_BE16(wfdie + wfdielen, 0x0005);\n\twfdielen += 2;\n\n\t/* Version: */\n\t/* 0x01: Version1;IPv4 */\n\twfdie[wfdielen++] = 0x01;\n\n\t/* IPv4 Address */\n\t_rtw_memcpy(wfdie + wfdielen, pwfd_info->ip_address, 4);\n\twfdielen += 4;\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, pktlen);\n\n}\n#endif /* CONFIG_WFD */\n\nvoid rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tstruct registry_priv\t*pregistrypriv = &padapter->registrypriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct pkt_attrib\t*pattrib = &pxmitframe->attrib;\n\tint i = 0 ;\n\tu32 time;\n\tu8 *pframe_head;\n\n\t/* SNonce */\n\tif (pattrib->encrypt) {\n\t\tfor (i = 0; i < 8; i++) {\n\t\t\ttime = rtw_get_current_time();\n\t\t\t_rtw_memcpy(&ptdls_sta->SNonce[4 * i], (u8 *)&time, 4);\n\t\t}\n\t}\n\n\tpframe_head = pframe;\t/* For rtw_tdls_set_ht_cap() */\n\n\tpframe = rtw_tdls_set_payload_type(pframe, pattrib);\n\tpframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);\n\tpframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);\n\tpframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);\n\n\tpframe = rtw_tdls_set_capability(padapter, pframe, pattrib);\n\tpframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib);\n\tpframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib);\n\tpframe = rtw_tdls_set_sup_reg_class(pframe, pattrib);\n\n\tif (pattrib->encrypt)\n\t\tpframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib,  _TRUE, ptdls_sta);\n\n\tpframe = rtw_tdls_set_ext_cap(pframe, pattrib);\n\n\tif (pattrib->encrypt) {\n\t\tpframe = rtw_tdls_set_ftie(ptxmgmt\n\t\t\t\t\t   , pframe\n\t\t\t\t\t   , pattrib\n\t\t\t\t\t   , NULL\n\t\t\t\t\t   , ptdls_sta->SNonce);\n\n\t\tpframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib, _TRUE, ptdls_sta);\n\t}\n\n#ifdef CONFIG_80211N_HT\n\t/* Sup_reg_classes(optional) */\n\tif (pregistrypriv->ht_enable == _TRUE)\n\t\tpframe = rtw_tdls_set_ht_cap(padapter, pframe_head, pattrib);\n#endif\n\n\tpframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib);\n\n\tpframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);\n\n\tif ((pregistrypriv->wmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE))\n\t\tpframe = rtw_tdls_set_qos_cap(pframe, pattrib);\n\n#ifdef CONFIG_80211AC_VHT\n\tif ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14)\n\t    && REGSTY_IS_11AC_ENABLE(pregistrypriv)\n\t    && is_supported_vht(pregistrypriv->wireless_mode)\n\t    && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))\n\t   ) {\n\t\tpframe = rtw_tdls_set_aid(padapter, pframe, pattrib);\n\t\tpframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib);\n\t}\n#endif\n\n#ifdef CONFIG_WFD\n\tif (padapter->wdinfo.wfd_tdls_enable == 1)\n\t\twfd_ie_tdls(padapter, pframe, &(pattrib->pktlen));\n#endif\n\n}\n\nvoid rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tstruct registry_priv\t*pregistrypriv = &padapter->registrypriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct pkt_attrib\t*pattrib = &pxmitframe->attrib;\n\tu8 k; /* for random ANonce */\n\tu8  *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL;\n\tu32 time;\n\tu8 *pframe_head;\n\n\tif (pattrib->encrypt) {\n\t\tfor (k = 0; k < 8; k++) {\n\t\t\ttime = rtw_get_current_time();\n\t\t\t_rtw_memcpy(&ptdls_sta->ANonce[4 * k], (u8 *)&time, 4);\n\t\t}\n\t}\n\n\tpframe_head = pframe;\n\n\tpframe = rtw_tdls_set_payload_type(pframe, pattrib);\n\tpframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);\n\tpframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);\n\tpframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt);\n\n\tif (ptxmgmt->status_code != 0) {\n\t\tRTW_INFO(\"[%s] status_code:%04x\\n\", __FUNCTION__, ptxmgmt->status_code);\n\t\treturn;\n\t}\n\n\tpframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);\n\tpframe = rtw_tdls_set_capability(padapter, pframe, pattrib);\n\tpframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib);\n\tpframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib);\n\tpframe = rtw_tdls_set_sup_reg_class(pframe, pattrib);\n\n\tif (pattrib->encrypt) {\n\t\tprsnie = pframe;\n\t\tpframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib,  _FALSE, ptdls_sta);\n\t}\n\n\tpframe = rtw_tdls_set_ext_cap(pframe, pattrib);\n\n\tif (pattrib->encrypt) {\n\t\tif (rtw_tdls_is_driver_setup(padapter) == _TRUE)\n\t\t\twpa_tdls_generate_tpk(padapter, ptdls_sta);\n\n\t\tpftie = pframe;\n\t\tpftie_mic = pframe + 4;\n\t\tpframe = rtw_tdls_set_ftie(ptxmgmt\n\t\t\t\t\t   , pframe\n\t\t\t\t\t   , pattrib\n\t\t\t\t\t   , ptdls_sta->ANonce\n\t\t\t\t\t   , ptdls_sta->SNonce);\n\n\t\tptimeout_ie = pframe;\n\t\tpframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib, _FALSE, ptdls_sta);\n\t}\n\n#ifdef CONFIG_80211N_HT\n\t/* Sup_reg_classes(optional) */\n\tif (pregistrypriv->ht_enable == _TRUE)\n\t\tpframe = rtw_tdls_set_ht_cap(padapter, pframe_head, pattrib);\n#endif\n\n\tpframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib);\n\n\tplinkid_ie = pframe;\n\tpframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);\n\n\t/* Fill FTIE mic */\n\tif (pattrib->encrypt && rtw_tdls_is_driver_setup(padapter) == _TRUE)\n\t\twpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic);\n\n\tif ((pregistrypriv->wmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE))\n\t\tpframe = rtw_tdls_set_qos_cap(pframe, pattrib);\n\n#ifdef CONFIG_80211AC_VHT\n\tif ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14)\n\t    && REGSTY_IS_11AC_ENABLE(pregistrypriv)\n\t    && is_supported_vht(pregistrypriv->wireless_mode)\n\t    && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))\n\t   ) {\n\t\tpframe = rtw_tdls_set_aid(padapter, pframe, pattrib);\n\t\tpframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib);\n\t\tpframe = rtw_tdls_set_vht_op_mode_notify(padapter, pframe, pattrib, pmlmeext->cur_bwmode);\n\t}\n#endif\n\n#ifdef CONFIG_WFD\n\tif (padapter->wdinfo.wfd_tdls_enable)\n\t\twfd_ie_tdls(padapter, pframe, &(pattrib->pktlen));\n#endif\n\n}\n\nvoid rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tstruct registry_priv\t*pregistrypriv = &padapter->registrypriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct pkt_attrib\t*pattrib = &pxmitframe->attrib;\n\n\tunsigned int ie_len;\n\tunsigned char *p;\n\tu8 wmm_param_ele[24] = {0};\n\tu8  *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL;\n\n\tpframe = rtw_tdls_set_payload_type(pframe, pattrib);\n\tpframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);\n\tpframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);\n\tpframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt);\n\tpframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);\n\n\tif (ptxmgmt->status_code != 0)\n\t\treturn;\n\n\tif (pattrib->encrypt) {\n\t\tprsnie = pframe;\n\t\tpframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib, _TRUE, ptdls_sta);\n\t}\n\n\tif (pattrib->encrypt) {\n\t\tpftie = pframe;\n\t\tpftie_mic = pframe + 4;\n\t\tpframe = rtw_tdls_set_ftie(ptxmgmt\n\t\t\t\t\t   , pframe\n\t\t\t\t\t   , pattrib\n\t\t\t\t\t   , ptdls_sta->ANonce\n\t\t\t\t\t   , ptdls_sta->SNonce);\n\n\t\tptimeout_ie = pframe;\n\t\tpframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib, _TRUE, ptdls_sta);\n\n\t\tif (rtw_tdls_is_driver_setup(padapter) == _TRUE) {\n\t\t\t/* Start TPK timer */\n\t\t\tptdls_sta->TPK_count = 0;\n\t\t\t_set_timer(&ptdls_sta->TPK_timer, ONE_SEC);\n\t\t}\n\t}\n\n\t/* HT operation; todo */\n\n\tplinkid_ie = pframe;\n\tpframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);\n\n\tif (pattrib->encrypt && (rtw_tdls_is_driver_setup(padapter) == _TRUE))\n\t\twpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic);\n\n\tif (ptdls_sta->qos_option == _TRUE)\n\t\tpframe = rtw_tdls_set_wmm_params(padapter, pframe, pattrib);\n\n#ifdef CONFIG_80211AC_VHT\n\tif ((padapter->mlmepriv.htpriv.ht_option == _TRUE)\n\t    && (ptdls_sta->vhtpriv.vht_option == _TRUE) && (pmlmeext->cur_channel > 14)\n\t    && REGSTY_IS_11AC_ENABLE(pregistrypriv)\n\t    && is_supported_vht(pregistrypriv->wireless_mode)\n\t    && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))\n\t   ) {\n\t\tpframe = rtw_tdls_set_vht_operation(padapter, pframe, pattrib, pmlmeext->cur_channel);\n\t\tpframe = rtw_tdls_set_vht_op_mode_notify(padapter, pframe, pattrib, pmlmeext->cur_bwmode);\n\t}\n#endif\n}\n\nvoid rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)\n{\n\tstruct pkt_attrib\t*pattrib = &pxmitframe->attrib;\n\tu8  *pftie = NULL, *pftie_mic = NULL, *plinkid_ie = NULL;\n\n\tpframe = rtw_tdls_set_payload_type(pframe, pattrib);\n\tpframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);\n\tpframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);\n\tpframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt);\n\n\tif (pattrib->encrypt) {\n\t\tpftie = pframe;\n\t\tpftie_mic = pframe + 4;\n\t\tpframe = rtw_tdls_set_ftie(ptxmgmt\n\t\t\t\t\t   , pframe\n\t\t\t\t\t   , pattrib\n\t\t\t\t\t   , ptdls_sta->ANonce\n\t\t\t\t\t   , ptdls_sta->SNonce);\n\t}\n\n\tplinkid_ie = pframe;\n\tif (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)\n\t\tpframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);\n\telse if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)\n\t\tpframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);\n\n\tif (pattrib->encrypt && (rtw_tdls_is_driver_setup(padapter) == _TRUE))\n\t\twpa_tdls_teardown_ftie_mic(ptdls_sta->tpk.kck, plinkid_ie, ptxmgmt->status_code, 1, 4, pftie, pftie_mic);\n}\n\nvoid rtw_build_tdls_dis_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt)\n{\n\tstruct pkt_attrib *pattrib = &pxmitframe->attrib;\n\n\tpframe = rtw_tdls_set_payload_type(pframe, pattrib);\n\tpframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);\n\tpframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);\n\tpframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);\n\tpframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);\n\n}\n\nvoid rtw_build_tdls_dis_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, u8 privacy)\n{\n\tstruct registry_priv\t*pregistrypriv = &padapter->registrypriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct pkt_attrib\t*pattrib = &pxmitframe->attrib;\n\tu8 *pframe_head, pktlen_index;\n\n\tpktlen_index = pattrib->pktlen;\n\tpframe_head = pframe;\n\n\tpframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_PUBLIC);\n\tpframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);\n\tpframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);\n\tpframe = rtw_tdls_set_capability(padapter, pframe, pattrib);\n\n\tpframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib);\n\n\tpframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib);\n\n\tif (privacy)\n\t\tpframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib, _TRUE, NULL);\n\n\tpframe = rtw_tdls_set_ext_cap(pframe, pattrib);\n\n\tif (privacy) {\n\t\tpframe = rtw_tdls_set_ftie(ptxmgmt, pframe, pattrib, NULL, NULL);\n\t\tpframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib,  _TRUE, NULL);\n\t}\n\n#ifdef CONFIG_80211N_HT\n\tif (pregistrypriv->ht_enable == _TRUE)\n\t\tpframe = rtw_tdls_set_ht_cap(padapter, pframe_head - pktlen_index, pattrib);\n#endif\n\n\tpframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib);\n\tpframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);\n\n}\n\n\nvoid rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)\n{\n\n\tstruct pkt_attrib\t*pattrib = &pxmitframe->attrib;\n\tu8 AC_queue = 0;\n\n\tpframe = rtw_tdls_set_payload_type(pframe, pattrib);\n\tpframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);\n\tpframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);\n\tpframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);\n\n\tif (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)\n\t\tpframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);\n\telse if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)\n\t\tpframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);\n\n\t/* PTI control */\n\t/* PU buffer status */\n\tif (ptdls_sta->uapsd_bk & BIT(1))\n\t\tAC_queue = BIT(0);\n\tif (ptdls_sta->uapsd_be & BIT(1))\n\t\tAC_queue = BIT(1);\n\tif (ptdls_sta->uapsd_vi & BIT(1))\n\t\tAC_queue = BIT(2);\n\tif (ptdls_sta->uapsd_vo & BIT(1))\n\t\tAC_queue = BIT(3);\n\tpframe = rtw_set_ie(pframe, _PTI_BUFFER_STATUS_, 1, &AC_queue, &(pattrib->pktlen));\n\n}\n\nvoid rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)\n{\n\n\tstruct pkt_attrib\t*pattrib = &pxmitframe->attrib;\n\n\tpframe = rtw_tdls_set_payload_type(pframe, pattrib);\n\tpframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);\n\tpframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);\n\tpframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);\n\n\tif (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)\n\t\tpframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);\n\telse if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)\n\t\tpframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);\n}\n\n#ifdef CONFIG_TDLS_CH_SW\nvoid rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)\n{\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\tstruct pkt_attrib\t*pattrib = &pxmitframe->attrib;\n\tstruct sta_priv\t*pstapriv = &padapter->stapriv;\n\tu16 switch_time = TDLS_CH_SWITCH_TIME * 1000, switch_timeout = TDLS_CH_SWITCH_TIMEOUT * 1000;\n\n\tptdls_sta->ch_switch_time = switch_time;\n\tptdls_sta->ch_switch_timeout = switch_timeout;\n\n\tpframe = rtw_tdls_set_payload_type(pframe, pattrib);\n\tpframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);\n\tpframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);\n\tpframe = rtw_tdls_set_target_ch(padapter, pframe, pattrib);\n\tpframe = rtw_tdls_set_reg_class(pframe, pattrib, ptdls_sta);\n\n\tif (ptdlsinfo->chsw_info.ch_offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE) {\n\t\tswitch (ptdlsinfo->chsw_info.ch_offset) {\n\t\tcase HAL_PRIME_CHNL_OFFSET_LOWER:\n\t\t\tpframe = rtw_tdls_set_second_channel_offset(pframe, pattrib, SCA);\n\t\t\tbreak;\n\t\tcase HAL_PRIME_CHNL_OFFSET_UPPER:\n\t\t\tpframe = rtw_tdls_set_second_channel_offset(pframe, pattrib, SCB);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)\n\t\tpframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);\n\telse if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)\n\t\tpframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);\n\n\tpframe = rtw_tdls_set_ch_sw(pframe, pattrib, ptdls_sta);\n\n}\n\nvoid rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)\n{\n\n\tstruct pkt_attrib\t*pattrib = &pxmitframe->attrib;\n\tstruct sta_priv\t*pstapriv = &padapter->stapriv;\n\n\tpframe = rtw_tdls_set_payload_type(pframe, pattrib);\n\tpframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);\n\tpframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);\n\tpframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt);\n\n\tif (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)\n\t\tpframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);\n\telse if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)\n\t\tpframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);\n\n\tpframe = rtw_tdls_set_ch_sw(pframe, pattrib, ptdls_sta);\n}\n#endif\n\n#ifdef CONFIG_WFD\nvoid rtw_build_tunneled_probe_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe)\n{\n\tu8 i;\n\t_adapter *iface = NULL;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct pkt_attrib *pattrib = &pxmitframe->attrib;\n\tstruct wifidirect_info *pwdinfo;\n\n\tu8 category = RTW_WLAN_CATEGORY_P2P;\n\tu8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a};\n\tu8 probe_req = 4;\n\tu8 wfdielen = 0;\n\n\tpframe = rtw_tdls_set_payload_type(pframe, pattrib);\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 3, WFA_OUI, &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(probe_req), &(pattrib->pktlen));\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif ((iface) && rtw_is_adapter_up(iface)) {\n\t\t\tpwdinfo = &iface->wdinfo;\n\t\t\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {\n\t\t\t\twfdielen = build_probe_req_wfd_ie(pwdinfo, pframe);\n\t\t\t\tpframe += wfdielen;\n\t\t\t\tpattrib->pktlen += wfdielen;\n\t\t\t}\n\t\t}\n\t}\n}\n\nvoid rtw_build_tunneled_probe_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe)\n{\n\tu8 i;\n\t_adapter *iface = NULL;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct pkt_attrib\t*pattrib = &pxmitframe->attrib;\n\tstruct wifidirect_info *pwdinfo;\n\tu8 category = RTW_WLAN_CATEGORY_P2P;\n\tu8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a};\n\tu8 probe_rsp = 5;\n\tu8 wfdielen = 0;\n\n\tpframe = rtw_tdls_set_payload_type(pframe, pattrib);\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 3, WFA_OUI, &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(probe_rsp), &(pattrib->pktlen));\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif ((iface) && rtw_is_adapter_up(iface)) {\n\t\t\tpwdinfo = &iface->wdinfo;\n\t\t\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {\n\t\t\t\twfdielen = build_probe_resp_wfd_ie(pwdinfo, pframe, 1);\n\t\t\t\tpframe += wfdielen;\n\t\t\t\tpattrib->pktlen += wfdielen;\n\t\t\t}\n\t\t}\n\t}\n}\n#endif /* CONFIG_WFD */\n\nvoid _tdls_tpk_timer_hdl(void *FunctionContext)\n{\n\tstruct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;\n\tstruct tdls_txmgmt txmgmt;\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\tptdls_sta->TPK_count++;\n\t/* TPK_timer expired in a second */\n\t/* Retry timer should set at least 301 sec. */\n\tif (ptdls_sta->TPK_count >= (ptdls_sta->TDLS_PeerKey_Lifetime - 3)) {\n\t\tRTW_INFO(\"[TDLS] %s, Re-Setup TDLS link with \"MAC_FMT\" since TPK lifetime expires!\\n\",\n\t\t\t__FUNCTION__, MAC_ARG(ptdls_sta->cmn.mac_addr));\n\t\tptdls_sta->TPK_count = 0;\n\t\t_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);\n\t\tissue_tdls_setup_req(ptdls_sta->padapter, &txmgmt, _FALSE);\n\t}\n\n\t_set_timer(&ptdls_sta->TPK_timer, ONE_SEC);\n}\n\n#ifdef CONFIG_TDLS_CH_SW\nvoid _tdls_ch_switch_timer_hdl(void *FunctionContext)\n{\n\tstruct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;\n\t_adapter *padapter = ptdls_sta->padapter;\n\tstruct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;\n\n\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL);\n\tRTW_INFO(\"[TDLS] %s, can't get traffic from op_ch:%d\\n\", __func__, rtw_get_oper_ch(padapter));\n}\n\nvoid _tdls_delay_timer_hdl(void *FunctionContext)\n{\n\tstruct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;\n\t_adapter *padapter = ptdls_sta->padapter;\n\tstruct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;\n\n\tRTW_INFO(\"[TDLS] %s, op_ch:%d, tdls_state:0x%08x\\n\", __func__, rtw_get_oper_ch(padapter), ptdls_sta->tdls_sta_state);\n\tpchsw_info->delay_switch_back = _TRUE;\n}\n\nvoid _tdls_stay_on_base_chnl_timer_hdl(void *FunctionContext)\n{\n\tstruct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;\n\t_adapter *padapter = ptdls_sta->padapter;\n\tstruct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;\n\n\tif (ptdls_sta != NULL) {\n\t\tissue_tdls_ch_switch_req(padapter, ptdls_sta);\n\t\tpchsw_info->ch_sw_state |= TDLS_WAIT_CH_RSP_STATE;\n\t}\n}\n\nvoid _tdls_ch_switch_monitor_timer_hdl(void *FunctionContext)\n{\n\tstruct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;\n\t_adapter *padapter = ptdls_sta->padapter;\n\tstruct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;\n\n\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END);\n\tRTW_INFO(\"[TDLS] %s, does not receive ch sw req\\n\", __func__);\n}\n\n#endif\n\nvoid _tdls_handshake_timer_hdl(void *FunctionContext)\n{\n\tstruct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;\n\t_adapter *padapter = NULL;\n\tstruct tdls_txmgmt txmgmt;\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\t_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);\n\ttxmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;\n\n\tif (ptdls_sta != NULL) {\n\t\tpadapter = ptdls_sta->padapter;\n\n\t\tRTW_INFO(\"[TDLS] Handshake time out\\n\");\n\t\tif (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)\n\t\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA);\n\t\telse\n\t\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY);\n\t}\n}\n\nvoid _tdls_pti_timer_hdl(void *FunctionContext)\n{\n\tstruct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;\n\t_adapter *padapter = NULL;\n\tstruct tdls_txmgmt txmgmt;\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\t_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);\n\ttxmgmt.status_code = _RSON_TDLS_TEAR_TOOFAR_;\n\n\tif (ptdls_sta != NULL) {\n\t\tpadapter = ptdls_sta->padapter;\n\n\t\tif (ptdls_sta->tdls_sta_state & TDLS_WAIT_PTR_STATE) {\n\t\t\tRTW_INFO(\"[TDLS] Doesn't receive PTR from peer dev:\"MAC_FMT\"; \"\n\t\t\t\t\"Send TDLS Tear Down\\n\", MAC_ARG(ptdls_sta->cmn.mac_addr));\n\t\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA);\n\t\t}\n\t}\n}\n\nvoid rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta)\n{\n\tpsta->padapter = padapter;\n\trtw_init_timer(&psta->TPK_timer, padapter, _tdls_tpk_timer_hdl, psta);\n#ifdef CONFIG_TDLS_CH_SW\n\trtw_init_timer(&psta->ch_sw_timer, padapter, _tdls_ch_switch_timer_hdl, psta);\n\trtw_init_timer(&psta->delay_timer, padapter, _tdls_delay_timer_hdl, psta);\n\trtw_init_timer(&psta->stay_on_base_chnl_timer, padapter, _tdls_stay_on_base_chnl_timer_hdl, psta);\n\trtw_init_timer(&psta->ch_sw_monitor_timer, padapter, _tdls_ch_switch_monitor_timer_hdl, psta);\n#endif\n\trtw_init_timer(&psta->handshake_timer, padapter, _tdls_handshake_timer_hdl, psta);\n\trtw_init_timer(&psta->pti_timer, padapter, _tdls_pti_timer_hdl, psta);\n}\n\nvoid rtw_cancel_tdls_timer(struct sta_info *psta)\n{\n\t_cancel_timer_ex(&psta->TPK_timer);\n#ifdef CONFIG_TDLS_CH_SW\n\t_cancel_timer_ex(&psta->ch_sw_timer);\n\t_cancel_timer_ex(&psta->delay_timer);\n\t_cancel_timer_ex(&psta->stay_on_base_chnl_timer);\n\t_cancel_timer_ex(&psta->ch_sw_monitor_timer);\n#endif\n\t_cancel_timer_ex(&psta->handshake_timer);\n\t_cancel_timer_ex(&psta->pti_timer);\n}\n\nvoid rtw_tdls_teardown_pre_hdl(_adapter *padapter, struct sta_info *psta)\n{\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\t_irqL irqL;\n\n\trtw_cancel_tdls_timer(psta);\n\n\t_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\n\tif (ptdlsinfo->sta_cnt != 0)\n\t\tptdlsinfo->sta_cnt--;\n\t_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\n\n\tif (ptdlsinfo->sta_cnt < MAX_ALLOWED_TDLS_STA_NUM) {\n\t\tptdlsinfo->sta_maximum = _FALSE;\n\t\t_rtw_memset(&ptdlsinfo->ss_record, 0x00, sizeof(struct tdls_ss_record));\n\t}\n\n\tif (ptdlsinfo->sta_cnt == 0)\n\t\trtw_tdls_set_link_established(padapter, _FALSE);\n\telse\n\t\tRTW_INFO(\"Remain tdls sta:%02x\\n\", ptdlsinfo->sta_cnt);\n}\n\nvoid rtw_tdls_teardown_post_hdl(_adapter *padapter, struct sta_info *psta, u8 enqueue_cmd)\n{\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\n\t/* Clear cam */\n\trtw_clearstakey_cmd(padapter, psta, enqueue_cmd);\n\n\t/* Update sta media status */\n\tif (enqueue_cmd)\n\t\trtw_sta_media_status_rpt_cmd(padapter, psta, 0);\n\telse\n\t\trtw_sta_media_status_rpt(padapter, psta, 0);\n\n\t/* Set RCR if necessary */\n\tif (ptdlsinfo->sta_cnt == 0) {\n\t\tif (enqueue_cmd)\n\t\t\trtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR);\n\t\telse\n\t\t\trtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_NOLINK);\n\t}\n\n\t/* Free tdls sta info */\n\trtw_free_stainfo(padapter,  psta);\n}\n\nint rtw_tdls_is_driver_setup(_adapter *padapter)\n{\n\treturn padapter->tdlsinfo.driver_setup;\n}\n\nconst char *rtw_tdls_action_txt(enum TDLS_ACTION_FIELD action)\n{\n\tswitch (action) {\n\tcase TDLS_SETUP_REQUEST:\n\t\treturn \"TDLS_SETUP_REQUEST\";\n\tcase TDLS_SETUP_RESPONSE:\n\t\treturn \"TDLS_SETUP_RESPONSE\";\n\tcase TDLS_SETUP_CONFIRM:\n\t\treturn \"TDLS_SETUP_CONFIRM\";\n\tcase TDLS_TEARDOWN:\n\t\treturn \"TDLS_TEARDOWN\";\n\tcase TDLS_PEER_TRAFFIC_INDICATION:\n\t\treturn \"TDLS_PEER_TRAFFIC_INDICATION\";\n\tcase TDLS_CHANNEL_SWITCH_REQUEST:\n\t\treturn \"TDLS_CHANNEL_SWITCH_REQUEST\";\n\tcase TDLS_CHANNEL_SWITCH_RESPONSE:\n\t\treturn \"TDLS_CHANNEL_SWITCH_RESPONSE\";\n\tcase TDLS_PEER_PSM_REQUEST:\n\t\treturn \"TDLS_PEER_PSM_REQUEST\";\n\tcase TDLS_PEER_PSM_RESPONSE:\n\t\treturn \"TDLS_PEER_PSM_RESPONSE\";\n\tcase TDLS_PEER_TRAFFIC_RESPONSE:\n\t\treturn \"TDLS_PEER_TRAFFIC_RESPONSE\";\n\tcase TDLS_DISCOVERY_REQUEST:\n\t\treturn \"TDLS_DISCOVERY_REQUEST\";\n\tcase TDLS_DISCOVERY_RESPONSE:\n\t\treturn \"TDLS_DISCOVERY_RESPONSE\";\n\tdefault:\n\t\treturn \"UNKNOWN\";\n\t}\n}\n\n#endif /* CONFIG_TDLS */\n"
  },
  {
    "path": "core/rtw_vht.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_VHT_C\n\n#include <drv_types.h>\n#include <hal_data.h>\n\n#ifdef CONFIG_80211AC_VHT\nconst u16 _vht_max_mpdu_len[] = {\n\t3895,\n\t7991,\n\t11454,\n\t0,\n};\n\nconst u8 _vht_sup_ch_width_set_to_bw_cap[] = {\n\tBW_CAP_80M,\n\tBW_CAP_80M | BW_CAP_160M,\n\tBW_CAP_80M | BW_CAP_160M | BW_CAP_80_80M,\n\t0,\n};\n\nconst char *const _vht_sup_ch_width_set_str[] = {\n\t\"80MHz\",\n\t\"160MHz\",\n\t\"160MHz & 80+80MHz\",\n\t\"BW-RSVD\",\n};\n\nvoid dump_vht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len)\n{\n\tif (buf_len != VHT_CAP_IE_LEN) {\n\t\tRTW_PRINT_SEL(sel, \"Invalid VHT capability IE len:%d != %d\\n\", buf_len, VHT_CAP_IE_LEN);\n\t\treturn;\n\t}\n\n\tRTW_PRINT_SEL(sel, \"cap_info:%02x %02x %02x %02x: MAX_MPDU_LEN:%u %s%s%s%s%s RX-STBC:%u MAX_AMPDU_LEN:%u\\n\"\n\t\t, *(buf), *(buf + 1), *(buf + 2), *(buf + 3)\n\t\t, vht_max_mpdu_len(GET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(buf))\n\t\t, vht_sup_ch_width_set_str(GET_VHT_CAPABILITY_ELE_CHL_WIDTH(buf))\n\t\t, GET_VHT_CAPABILITY_ELE_RX_LDPC(buf) ? \" RX-LDPC\" : \"\"\n\t\t, GET_VHT_CAPABILITY_ELE_SHORT_GI80M(buf) ? \" SGI-80\" : \"\"\n\t\t, GET_VHT_CAPABILITY_ELE_SHORT_GI160M(buf) ? \" SGI-160\" : \"\"\n\t\t, GET_VHT_CAPABILITY_ELE_TX_STBC(buf) ? \" TX-STBC\" : \"\"\n\t\t, GET_VHT_CAPABILITY_ELE_RX_STBC(buf)\n\t\t, VHT_MAX_AMPDU_LEN(GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(buf))\n\t);\n}\n\nvoid dump_vht_cap_ie(void *sel, const u8 *ie, u32 ie_len)\n{\n\tconst u8 *vht_cap_ie;\n\tsint vht_cap_ielen;\n\n\tvht_cap_ie = rtw_get_ie(ie, WLAN_EID_VHT_CAPABILITY, &vht_cap_ielen, ie_len);\n\tif (!ie || vht_cap_ie != ie)\n\t\treturn;\n\n\tdump_vht_cap_ie_content(sel, vht_cap_ie + 2, vht_cap_ielen);\n}\n\nconst char *const _vht_op_ch_width_str[] = {\n\t\"20 or 40MHz\",\n\t\"80MHz\",\n\t\"160MHz\",\n\t\"80+80MHz\",\n\t\"BW-RSVD\",\n};\n\nvoid dump_vht_op_ie_content(void *sel, const u8 *buf, u32 buf_len)\n{\n\tif (buf_len != VHT_OP_IE_LEN) {\n\t\tRTW_PRINT_SEL(sel, \"Invalid VHT operation IE len:%d != %d\\n\", buf_len, VHT_OP_IE_LEN);\n\t\treturn;\n\t}\n\n\tRTW_PRINT_SEL(sel, \"%s, ch0:%u, ch1:%u\\n\"\n\t\t, vht_op_ch_width_str(GET_VHT_OPERATION_ELE_CHL_WIDTH(buf))\n\t\t, GET_VHT_OPERATION_ELE_CENTER_FREQ1(buf)\n\t\t, GET_VHT_OPERATION_ELE_CENTER_FREQ2(buf)\n\t);\n}\n\nvoid dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len)\n{\n\tconst u8 *vht_op_ie;\n\tsint vht_op_ielen;\n\n\tvht_op_ie = rtw_get_ie(ie, WLAN_EID_VHT_OPERATION, &vht_op_ielen, ie_len);\n\tif (!ie || vht_op_ie != ie)\n\t\treturn;\n\n\tdump_vht_op_ie_content(sel, vht_op_ie + 2, vht_op_ielen);\n}\n\n/*\t\t\t\t20/40/80,\tShortGI,\tMCS Rate  */\nconst u16 VHT_MCS_DATA_RATE[3][2][30] = {\n\t{\t{\n\t\t\t13, 26, 39, 52, 78, 104, 117, 130, 156, 156,\n\t\t\t26, 52, 78, 104, 156, 208, 234, 260, 312, 312,\n\t\t\t39, 78, 117, 156, 234, 312, 351, 390, 468, 520\n\t\t},\t\t\t/* Long GI, 20MHz */\n\t\t{\n\t\t\t14, 29, 43, 58, 87, 116, 130, 144, 173, 173,\n\t\t\t29, 58, 87, 116, 173, 231, 260, 289, 347, 347,\n\t\t\t43,\t87, 130, 173, 260, 347, 390,\t433,\t520, 578\n\t\t}\n\t},\t\t/* Short GI, 20MHz */\n\t{\t{\n\t\t\t27, 54, 81, 108, 162, 216, 243, 270, 324, 360,\n\t\t\t54, 108, 162, 216, 324, 432, 486, 540, 648, 720,\n\t\t\t81, 162, 243, 324, 486, 648, 729, 810, 972, 1080\n\t\t}, \t\t/* Long GI, 40MHz */\n\t\t{\n\t\t\t30, 60, 90, 120, 180, 240, 270, 300, 360, 400,\n\t\t\t60, 120, 180, 240, 360, 480, 540, 600, 720, 800,\n\t\t\t90, 180, 270, 360, 540, 720, 810, 900, 1080, 1200\n\t\t}\n\t},\t\t/* Short GI, 40MHz */\n\t{\t{\n\t\t\t59, 117,  176, 234, 351, 468, 527, 585, 702, 780,\n\t\t\t117, 234, 351, 468, 702, 936, 1053, 1170, 1404, 1560,\n\t\t\t176, 351, 527, 702, 1053, 1404, 1580, 1755, 2106, 2340\n\t\t},\t/* Long GI, 80MHz */\n\t\t{\n\t\t\t65, 130, 195, 260, 390, 520, 585, 650, 780, 867,\n\t\t\t130, 260, 390, 520, 780, 1040, 1170, 1300, 1560, 1734,\n\t\t\t195, 390, 585, 780, 1170, 1560, 1755, 1950, 2340, 2600\n\t\t}\n\t}\t/* Short GI, 80MHz */\n};\n\nu8\trtw_get_vht_highest_rate(u8 *pvht_mcs_map)\n{\n\tu8\ti, j;\n\tu8\tbit_map;\n\tu8\tvht_mcs_rate = 0;\n\n\tfor (i = 0; i < 2; i++) {\n\t\tif (pvht_mcs_map[i] != 0xff) {\n\t\t\tfor (j = 0; j < 8; j += 2) {\n\t\t\t\tbit_map = (pvht_mcs_map[i] >> j) & 3;\n\n\t\t\t\tif (bit_map != 3)\n\t\t\t\t\tvht_mcs_rate = MGN_VHT1SS_MCS7 + 10 * j / 2 + i * 40 + bit_map; /* VHT rate indications begin from 0x90 */\n\t\t\t}\n\t\t}\n\t}\n\n\t/* RTW_INFO(\"HighestVHTMCSRate is %x\\n\", vht_mcs_rate); */\n\treturn vht_mcs_rate;\n}\n\nu8\trtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map)\n{\n\tu8\ti, j;\n\tu8\tbit_map;\n\tu8\tnss = 0;\n\n\tfor (i = 0; i < 2; i++) {\n\t\tif (pvht_mcs_map[i] != 0xff) {\n\t\t\tfor (j = 0; j < 8; j += 2) {\n\t\t\t\tbit_map = (pvht_mcs_map[i] >> j) & 3;\n\n\t\t\t\tif (bit_map != 3)\n\t\t\t\t\tnss++;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* RTW_INFO(\"%s : %dSS\\n\", __FUNCTION__, nss); */\n\treturn nss;\n}\n\nvoid rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map)\n{\n\tu8\ti, j;\n\tu8\tcur_rate, target_rate;\n\n\tfor (i = 0; i < 2; i++) {\n\t\ttarget_mcs_map[i] = 0;\n\t\tfor (j = 0; j < 8; j += 2) {\n\t\t\tcur_rate = (cur_mcs_map[i] >> j) & 3;\n\t\t\tif (cur_rate == 3) /* 0x3 indicates not supported that num of SS */\n\t\t\t\ttarget_rate = 3;\n\t\t\telse if (nss <= ((j / 2) + i * 4))\n\t\t\t\ttarget_rate = 3;\n\t\t\telse\n\t\t\t\ttarget_rate = cur_rate;\n\n\t\t\ttarget_mcs_map[i] |= (target_rate << j);\n\t\t}\n\t}\n\n\t/* RTW_INFO(\"%s : %dSS\\n\", __FUNCTION__, nss); */\n}\n\nu16\trtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate)\n{\n\tif (vht_mcs_rate > MGN_VHT3SS_MCS9)\n\t\tvht_mcs_rate = MGN_VHT3SS_MCS9;\n\t/* RTW_INFO(\"bw=%d, short_GI=%d, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)=%d\\n\", bw, short_GI, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)); */\n\treturn VHT_MCS_DATA_RATE[bw][short_GI][((vht_mcs_rate - MGN_VHT1SS_MCS0) & 0x3f)];\n}\n\nvoid\trtw_vht_use_default_setting(_adapter *padapter)\n{\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct vht_priv\t\t*pvhtpriv = &pmlmepriv->vhtpriv;\n\tstruct registry_priv\t*pregistrypriv = &padapter->registrypriv;\n\tBOOLEAN\t\tbHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE;\n#ifdef CONFIG_BEAMFORMING\n\tBOOLEAN\t\tbHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE;\n\tu8\tmu_bfer, mu_bfee;\n#endif /* CONFIG_BEAMFORMING */\n\tu8\trf_type = 0;\n\tu8 tx_nss, rx_nss;\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tpvhtpriv->sgi_80m = TEST_FLAG(pregistrypriv->short_gi, BIT2) ? _TRUE : _FALSE;\n\n\t/* LDPC support */\n\trtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport);\n\tCLEAR_FLAGS(pvhtpriv->ldpc_cap);\n\tif (bHwLDPCSupport) {\n\t\tif (TEST_FLAG(pregistrypriv->ldpc_cap, BIT0))\n\t\t\tSET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX);\n\t}\n\trtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport);\n\tif (bHwLDPCSupport) {\n\t\tif (TEST_FLAG(pregistrypriv->ldpc_cap, BIT1))\n\t\t\tSET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX);\n\t}\n\tif (pvhtpriv->ldpc_cap)\n\t\tRTW_INFO(\"[VHT] Support LDPC = 0x%02X\\n\", pvhtpriv->ldpc_cap);\n\n\t/* STBC */\n\trtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport);\n\tCLEAR_FLAGS(pvhtpriv->stbc_cap);\n\tif (bHwSTBCSupport) {\n\t\tif (TEST_FLAG(pregistrypriv->stbc_cap, BIT1))\n\t\t\tSET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX);\n\t}\n\trtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport);\n\tif (bHwSTBCSupport) {\n\t\tif (TEST_FLAG(pregistrypriv->stbc_cap, BIT0))\n\t\t\tSET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX);\n\t}\n\tif (pvhtpriv->stbc_cap)\n\t\tRTW_INFO(\"[VHT] Support STBC = 0x%02X\\n\", pvhtpriv->stbc_cap);\n\n\t/* Beamforming setting */\n\tCLEAR_FLAGS(pvhtpriv->beamform_cap);\n#ifdef CONFIG_BEAMFORMING\n#ifdef RTW_BEAMFORMING_VERSION_2\n\t/* only enable beamforming in STA client mode */\n\tif (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter)\n\t\t\t\t  && !MLME_IS_ADHOC(padapter)\n\t\t\t\t  && !MLME_IS_MESH(padapter))\n#endif\n\t{\n\t\trtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER,\n\t\t\t(u8 *)&bHwSupportBeamformer);\n\t\trtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE,\n\t\t\t(u8 *)&bHwSupportBeamformee);\n\t\tmu_bfer = _FALSE;\n\t\tmu_bfee = _FALSE;\n\t\trtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMER, &mu_bfer);\n\t\trtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMEE, &mu_bfee);\n\t\tif (TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer) {\n#ifdef CONFIG_CONCURRENT_MODE\n\t\t\tif ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {\n\t\t\t\tSET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);\n\t\t\t\tRTW_INFO(\"[VHT] CONCURRENT AP Support Beamformer\\n\");\n\t\t\t\tif (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2))\n\t\t\t\t    && (_TRUE == mu_bfer)) {\n\t\t\t\t\tSET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);\n\t\t\t\t\tRTW_INFO(\"[VHT] Support MU-MIMO AP\\n\");\n\t\t\t\t}\n\t\t\t} else\n\t\t\t\tRTW_INFO(\"[VHT] CONCURRENT not AP ;not allow  Support Beamformer\\n\");\n#else\n\t\t\tSET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);\n\t\t\tRTW_INFO(\"[VHT] Support Beamformer\\n\");\n\t\t\tif (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2))\n\t\t\t    && (_TRUE == mu_bfer)\n\t\t\t    && ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {\n\t\t\t\tSET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);\n\t\t\t\tRTW_INFO(\"[VHT] Support MU-MIMO AP\\n\");\n\t\t\t}\n#endif\n\t\t}\n\t\tif (TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee) {\n\t\t\tSET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);\n\t\t\tRTW_INFO(\"[VHT] Support Beamformee\\n\");\n\t\t\tif (TEST_FLAG(pregistrypriv->beamform_cap, BIT(3))\n\t\t\t    && (_TRUE == mu_bfee)\n\t\t\t    && ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)) {\n\t\t\t\tSET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);\n\t\t\t\tRTW_INFO(\"[VHT] Support MU-MIMO STA\\n\");\n\t\t\t}\n\t\t}\n\t}\n#endif /* CONFIG_BEAMFORMING */\n\n\tpvhtpriv->ampdu_len = pregistrypriv->ampdu_factor;\n\n\trtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));\n\ttx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);\n\trx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num);\n\n\t/* for now, vhtpriv.vht_mcs_map comes from RX NSS */\n\trtw_vht_nss_to_mcsmap(rx_nss, pvhtpriv->vht_mcs_map, pregistrypriv->vht_rx_mcs_map);\n\tpvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map);\n}\n\nu64\trtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss)\n{\n\tu8 i, j, tmp;\n\tu64 bitmap = 0;\n\tu8 bits_nss = nss * 2;\n\n\tfor (i = j = 0; i < bits_nss; i += 2, j += 10) {\n\t\t/* every two bits means single sptial stream */\n\t\ttmp = (mcs_map[i / 8] >> i) & 3;\n\n\t\tswitch (tmp) {\n\t\tcase 2:\n\t\t\tbitmap = bitmap | (0x03ff << j);\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tbitmap = bitmap | (0x01ff << j);\n\t\t\tbreak;\n\t\tcase 0:\n\t\t\tbitmap = bitmap | (0x00ff << j);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tRTW_INFO(\"vht_mcs_map=%02x %02x, nss=%u => bitmap=%016llx\\n\"\n\t\t, mcs_map[0], mcs_map[1], nss, bitmap);\n\n\treturn bitmap;\n}\n\n#ifdef CONFIG_BEAMFORMING\nvoid update_sta_vht_info_apmode_bf_cap(_adapter *padapter, struct sta_info *psta)\n{\n\tstruct mlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tstruct vht_priv\t*pvhtpriv_ap = &pmlmepriv->vhtpriv;\n\tstruct vht_priv\t*pvhtpriv_sta = &psta->vhtpriv;\n\tu16\tcur_beamform_cap = 0;\n\n\t/* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */\n\tif (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&\n\t    GET_VHT_CAPABILITY_ELE_SU_BFEE(pvhtpriv_sta->vht_cap)) {\n\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);\n\t\t/*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/\n\t\tSET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pvhtpriv_sta->vht_cap) << 8);\n\t}\n\n\t/* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */\n\tif (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&\n\t    GET_VHT_CAPABILITY_ELE_SU_BFER(pvhtpriv_sta->vht_cap)) {\n\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);\n\t\t/*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/\n\t\tSET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pvhtpriv_sta->vht_cap) << 12);\n\t}\n\n\tif (cur_beamform_cap)\n\t\tRTW_INFO(\"Current STA(%d) VHT Beamforming Setting = %02X\\n\", psta->cmn.aid, cur_beamform_cap);\n\n\tpvhtpriv_sta->beamform_cap = cur_beamform_cap;\n\tpsta->cmn.bf_info.vht_beamform_cap = cur_beamform_cap;\n}\n#endif\n\nvoid\tupdate_sta_vht_info_apmode(_adapter *padapter, void *sta)\n{\n\tstruct sta_info\t*psta = (struct sta_info *)sta;\n\tstruct mlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct vht_priv\t*pvhtpriv_ap = &pmlmepriv->vhtpriv;\n\tstruct vht_priv\t*pvhtpriv_sta = &psta->vhtpriv;\n\tu8\tcur_ldpc_cap = 0, cur_stbc_cap = 0;\n\ts8 bw_mode = -1;\n\tu8\t*pcap_mcs;\n\n\tif (pvhtpriv_sta->vht_option == _FALSE)\n\t\treturn;\n\n\tif (pvhtpriv_sta->op_present) {\n\t\tswitch (GET_VHT_OPERATION_ELE_CHL_WIDTH(pvhtpriv_sta->vht_op)) {\n\t\tcase 1: /* 80MHz */\n\t\tcase 2: /* 160MHz */\n\t\tcase 3: /* 80+80 */\n\t\t\tbw_mode = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (pvhtpriv_sta->notify_present)\n\t\tbw_mode = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&pvhtpriv_sta->vht_op_mode_notify);\n\telse if (MLME_IS_AP(padapter)) {\n\t\t/* for VHT client without Operating Mode Notify IE; minimal 80MHz */\n\t\tif (bw_mode < CHANNEL_WIDTH_80)\n\t\t\tbw_mode = CHANNEL_WIDTH_80;\n\t}\n\n\tif (bw_mode != -1)\n\t\tpsta->cmn.bw_mode = bw_mode; /* update bw_mode only if get value from VHT IEs */\n\n\tpsta->cmn.ra_info.is_vht_enable = _TRUE;\n\n\t/* B4 Rx LDPC */\n\tif (TEST_FLAG(pvhtpriv_ap->ldpc_cap, LDPC_VHT_ENABLE_TX) &&\n\t    GET_VHT_CAPABILITY_ELE_RX_LDPC(pvhtpriv_sta->vht_cap)) {\n\t\tSET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));\n\t\tRTW_INFO(\"Current STA(%d) VHT LDPC = %02X\\n\", psta->cmn.aid, cur_ldpc_cap);\n\t}\n\tpvhtpriv_sta->ldpc_cap = cur_ldpc_cap;\n\n\tif (psta->cmn.bw_mode > pmlmeext->cur_bwmode)\n\t\tpsta->cmn.bw_mode = pmlmeext->cur_bwmode;\n\n\tif (psta->cmn.bw_mode == CHANNEL_WIDTH_80) {\n\t\t/* B5 Short GI for 80 MHz */\n\t\tpvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;\n\t\t/* RTW_INFO(\"Current STA ShortGI80MHz = %d\\n\", pvhtpriv_sta->sgi_80m); */\n\t} else if (psta->cmn.bw_mode >= CHANNEL_WIDTH_160) {\n\t\t/* B5 Short GI for 80 MHz */\n\t\tpvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;\n\t\t/* RTW_INFO(\"Current STA ShortGI160MHz = %d\\n\", pvhtpriv_sta->sgi_80m); */\n\t}\n\n\t/* B8 B9 B10 Rx STBC */\n\tif (TEST_FLAG(pvhtpriv_ap->stbc_cap, STBC_VHT_ENABLE_TX) &&\n\t    GET_VHT_CAPABILITY_ELE_RX_STBC(pvhtpriv_sta->vht_cap)) {\n\t\tSET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));\n\t\tRTW_INFO(\"Current STA(%d) VHT STBC = %02X\\n\", psta->cmn.aid, cur_stbc_cap);\n\t}\n\tpvhtpriv_sta->stbc_cap = cur_stbc_cap;\n\n#ifdef CONFIG_BEAMFORMING\n\tupdate_sta_vht_info_apmode_bf_cap(padapter, psta);\n#endif\n\n\t/* B23 B24 B25 Maximum A-MPDU Length Exponent */\n\tpvhtpriv_sta->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pvhtpriv_sta->vht_cap);\n\n\tpcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pvhtpriv_sta->vht_cap);\n\t_rtw_memcpy(pvhtpriv_sta->vht_mcs_map, pcap_mcs, 2);\n\tpvhtpriv_sta->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv_sta->vht_mcs_map);\n}\n\nvoid\tupdate_hw_vht_param(_adapter *padapter)\n{\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct vht_priv\t\t*pvhtpriv = &pmlmepriv->vhtpriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8\tht_AMPDU_len;\n\n\tht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;\n\n\tif (pvhtpriv->ampdu_len > ht_AMPDU_len)\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len));\n}\n\n#ifdef ROKU_PRIVATE\nu8 VHT_get_ss_from_map(u8 *vht_mcs_map)\n{\n\tu8 i, j;\n\tu8 ss = 0;\n\n\tfor (i = 0; i < 2; i++) {\n\t\tif (vht_mcs_map[i] != 0xff) {\n\t\t\tfor (j = 0; j < 8; j += 2) {\n\t\t\t\tif (((vht_mcs_map[i] >> j) & 0x03) == 0x03)\n\t\t\t\t\tbreak;\n\t\t\t\tss++;\n\t\t\t}\n\t\t}\n\n\t}\n\nreturn ss;\n}\n\nvoid VHT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)\n{\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct vht_priv_infra_ap\t*pvhtpriv = &pmlmepriv->vhtpriv_infra_ap;\n\tu8      cur_stbc_cap_infra_ap = 0;\n\tu16\tcur_beamform_cap_infra_ap = 0;\n\tu8\t*pcap_mcs;\n\tu8\t*pcap_mcs_tx;\n\tu8\tRx_ss = 0, Tx_ss = 0;\n\n\tstruct mlme_ext_priv\t\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tif (pIE == NULL)\n\t\treturn;\n\n\tpmlmeinfo->ht_vht_received |= BIT(1);\n\n\tpvhtpriv->ldpc_cap_infra_ap = GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data);\n\n\tif (GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data))\n\t\tSET_FLAG(cur_stbc_cap_infra_ap, STBC_VHT_ENABLE_RX);\n\tif (GET_VHT_CAPABILITY_ELE_TX_STBC(pIE->data))\n\t\tSET_FLAG(cur_stbc_cap_infra_ap, STBC_VHT_ENABLE_TX);\n\tpvhtpriv->stbc_cap_infra_ap = cur_stbc_cap_infra_ap;\n\n\t/*store ap info for channel bandwidth*/\n\tpvhtpriv->channel_width_infra_ap = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(pIE->data);\n\n\t/*check B11: SU Beamformer Capable and B12: SU Beamformee B19: MU Beamformer B20:MU Beamformee*/\n\tif (GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data))\n\t\tSET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);\n\tif (GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data))\n\t\tSET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);\n\tif (GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data))\n\t\tSET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);\n\tif (GET_VHT_CAPABILITY_ELE_MU_BFEE(pIE->data))\n\t\tSET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);\n\tpvhtpriv->beamform_cap_infra_ap = cur_beamform_cap_infra_ap;\n\n\t/*store information about vht_mcs_set*/\n\tpcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data);\n\tpcap_mcs_tx = GET_VHT_CAPABILITY_ELE_TX_MCS(pIE->data);\n\t_rtw_memcpy(pvhtpriv->vht_mcs_map_infra_ap, pcap_mcs, 2);\n\t_rtw_memcpy(pvhtpriv->vht_mcs_map_tx_infra_ap, pcap_mcs_tx, 2);\n\n\tRx_ss = VHT_get_ss_from_map(pvhtpriv->vht_mcs_map_infra_ap);\n\tTx_ss = VHT_get_ss_from_map(pvhtpriv->vht_mcs_map_tx_infra_ap);\n\tif (Rx_ss >= Tx_ss) {\n\t\tpvhtpriv->number_of_streams_infra_ap = Rx_ss;\n\t} else{\n\t\tpvhtpriv->number_of_streams_infra_ap = Tx_ss;\n\t}\n\n}\n#endif /* ROKU_PRIVATE */\n\nvoid VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct vht_priv\t\t*pvhtpriv = &pmlmepriv->vhtpriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8\tcur_ldpc_cap = 0, cur_stbc_cap = 0, rf_type = RF_1T1R, tx_nss = 0;\n\tu16\tcur_beamform_cap = 0;\n\tu8\t*pcap_mcs;\n\n\tif (pIE == NULL)\n\t\treturn;\n\n\tif (pvhtpriv->vht_option == _FALSE)\n\t\treturn;\n\n\tpmlmeinfo->VHT_enable = 1;\n\n\t/* B4 Rx LDPC */\n\tif (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX) &&\n\t    GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data)) {\n\t\tSET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));\n\t\tRTW_INFO(\"Current VHT LDPC Setting = %02X\\n\", cur_ldpc_cap);\n\t}\n\tpvhtpriv->ldpc_cap = cur_ldpc_cap;\n\n\t/* B5 Short GI for 80 MHz */\n\tpvhtpriv->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pIE->data) & pvhtpriv->sgi_80m) ? _TRUE : _FALSE;\n\t/* RTW_INFO(\"Current ShortGI80MHz = %d\\n\", pvhtpriv->sgi_80m); */\n\n\t/* B8 B9 B10 Rx STBC */\n\tif (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX) &&\n\t    GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data)) {\n\t\tSET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));\n\t\tRTW_INFO(\"Current VHT STBC Setting = %02X\\n\", cur_stbc_cap);\n\t}\n\tpvhtpriv->stbc_cap = cur_stbc_cap;\n#ifdef CONFIG_BEAMFORMING\n#ifdef RTW_BEAMFORMING_VERSION_2\n\t/*\n\t * B11 SU Beamformer Capable,\n\t * the target supports Beamformer and we are Beamformee\n\t */\n\tif (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)\n\t    && GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data)) {\n\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);\n\n\t\t/* Shift to BEAMFORMING_VHT_BEAMFORMEE_STS_CAP */\n\t\tSET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pIE->data) << 8);\n\n\t\t/*\n\t\t * B19 MU Beamformer Capable,\n\t\t * the target supports Beamformer and we are Beamformee\n\t\t */\n\t\tif (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)\n\t\t    && GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data))\n\t\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);\n\t}\n\n\t/*\n\t * B12 SU Beamformee Capable,\n\t * the target supports Beamformee and we are Beamformer\n\t */\n\tif (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)\n\t    && GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data)) {\n\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);\n\n\t\t/* Shit to BEAMFORMING_VHT_BEAMFORMER_SOUND_DIM */\n\t\tSET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data) << 12);\n\n\t\t/*\n\t\t * B20 MU Beamformee Capable,\n\t\t * the target supports Beamformee and we are Beamformer\n\t\t */\n\t\tif (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)\n\t\t    && GET_VHT_CAPABILITY_ELE_MU_BFEE(pIE->data))\n\t\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);\n\t}\n\n\tpvhtpriv->beamform_cap = cur_beamform_cap;\n\tRTW_INFO(\"Current VHT Beamforming Setting=0x%04X\\n\", cur_beamform_cap);\n#else /* !RTW_BEAMFORMING_VERSION_2 */\n\t/* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */\n\tif (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&\n\t    GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data)) {\n\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);\n\t\t/*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/\n\t\tSET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pIE->data) << 8);\n\t}\n\n\t/* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */\n\tif (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&\n\t    GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data)) {\n\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);\n\t\t/*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/\n\t\tSET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data) << 12);\n\n\t}\n\tpvhtpriv->beamform_cap = cur_beamform_cap;\n\tif (cur_beamform_cap)\n\t\tRTW_INFO(\"Current VHT Beamforming Setting = %02X\\n\", cur_beamform_cap);\n#endif /* !RTW_BEAMFORMING_VERSION_2 */\n#endif /* CONFIG_BEAMFORMING */\n\t/* B23 B24 B25 Maximum A-MPDU Length Exponent */\n\tpvhtpriv->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pIE->data);\n\n\tpcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data);\n\trtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));\n\ttx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);\n\trtw_vht_nss_to_mcsmap(tx_nss, pvhtpriv->vht_mcs_map, pcap_mcs);\n\tpvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map);\n}\n\nvoid VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)\n{\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct vht_priv\t\t*pvhtpriv = &pmlmepriv->vhtpriv;\n\n\tif (pIE == NULL)\n\t\treturn;\n\n\tif (pvhtpriv->vht_option == _FALSE)\n\t\treturn;\n}\n\nvoid rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, void *sta)\n{\n\tstruct sta_info\t\t*psta = (struct sta_info *)sta;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct vht_priv\t\t*pvhtpriv = &pmlmepriv->vhtpriv;\n\tstruct registry_priv *regsty = adapter_to_regsty(padapter);\n\tu8\ttarget_bw;\n\tu8\ttarget_rxss, current_rxss;\n\tu8\tupdate_ra = _FALSE;\n\tu8 tx_nss = 0, rf_type = RF_1T1R;\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);\n\n\tif (pvhtpriv->vht_option == _FALSE)\n\t\treturn;\n\n\ttarget_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(pframe);\n\n\trtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));\n\ttx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);\n\ttarget_rxss = rtw_min(tx_nss, (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(pframe) + 1));\n\n\tif (target_bw != psta->cmn.bw_mode) {\n\t\tif (hal_is_bw_support(padapter, target_bw)\n\t\t    && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw)\n\t\t   ) {\n\t\t\tupdate_ra = _TRUE;\n\t\t\tpsta->cmn.bw_mode = target_bw;\n\t\t}\n\t}\n\n\tcurrent_rxss = rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map);\n\tif (target_rxss != current_rxss) {\n\t\tu8\tvht_mcs_map[2] = {};\n\n\t\tupdate_ra = _TRUE;\n\n\t\trtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, psta->vhtpriv.vht_mcs_map);\n\t\t_rtw_memcpy(psta->vhtpriv.vht_mcs_map, vht_mcs_map, 2);\n\n\t\trtw_hal_update_sta_ra_info(padapter, psta);\n\t}\n\n\tif (update_ra)\n\t\trtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta);\n}\n\nu32\trtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel)\n{\n\tstruct registry_priv\t*pregistrypriv = &padapter->registrypriv;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct vht_priv\t\t*pvhtpriv = &pmlmepriv->vhtpriv;\n\t/* struct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv; */\n\tu8\tChnlWidth, center_freq, bw_mode;\n\tu32\tlen = 0;\n\tu8\toperation[5];\n\n\t_rtw_memset(operation, 0, 5);\n\n\tbw_mode = REGSTY_BW_5G(pregistrypriv); /* TODO: control op bw with other info */\n\n\tif (hal_chk_bw_cap(padapter, BW_CAP_80M | BW_CAP_160M)\n\t    && REGSTY_BW_5G(pregistrypriv) >= CHANNEL_WIDTH_80\n\t   ) {\n\t\tcenter_freq = rtw_get_center_ch(channel, bw_mode, HAL_PRIME_CHNL_OFFSET_LOWER);\n\t\tChnlWidth = 1;\n\t} else {\n\t\tcenter_freq = 0;\n\t\tChnlWidth = 0;\n\t}\n\n\n\tSET_VHT_OPERATION_ELE_CHL_WIDTH(operation, ChnlWidth);\n\t/* center frequency */\n\tSET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(operation, center_freq);/* Todo: need to set correct center channel */\n\tSET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(operation, 0);\n\n\t_rtw_memcpy(operation + 3, pvhtpriv->vht_mcs_map, 2);\n\n\trtw_set_ie(pbuf, EID_VHTOperation, 5, operation, &len);\n\n\treturn len;\n}\n\nu32\trtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw)\n{\n\t/* struct registry_priv *pregistrypriv = &padapter->registrypriv; */\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct vht_priv\t*pvhtpriv = &pmlmepriv->vhtpriv;\n\tu32\tlen = 0;\n\tu8\topmode = 0;\n\tu8\tchnl_width, rx_nss;\n\n\tchnl_width = bw;\n\trx_nss = rtw_vht_mcsmap_to_nss(pvhtpriv->vht_mcs_map);\n\n\tSET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&opmode, chnl_width);\n\tSET_VHT_OPERATING_MODE_FIELD_RX_NSS(&opmode, (rx_nss - 1));\n\tSET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(&opmode, 0); /* Todo */\n\n\tpvhtpriv->vht_op_mode_notify = opmode;\n\n\tpbuf = rtw_set_ie(pbuf, EID_OpModeNotification, 1, &opmode, &len);\n\n\treturn len;\n}\n\nu32\trtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)\n{\n\tu8\tbw, rf_num, rx_stbc_nss = 0;\n\tu16\tHighestRate;\n\tu8\t*pcap, *pcap_mcs;\n\tu32\tlen = 0;\n\tu32 rx_packet_offset, max_recvbuf_sz;\n\tstruct registry_priv *pregistrypriv = &padapter->registrypriv;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct vht_priv\t*pvhtpriv = &pmlmepriv->vhtpriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tpcap = pvhtpriv->vht_cap;\n\t_rtw_memset(pcap, 0, 32);\n\n\t/* B0 B1 Maximum MPDU Length */\n\trtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset);\n\trtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz);\n\n\tRTW_DBG(\"%s, line%d, Available RX buf size = %d bytes\\n\", __FUNCTION__, __LINE__, max_recvbuf_sz - rx_packet_offset);\n\n\tif ((max_recvbuf_sz - rx_packet_offset) >= 11454) {\n\t\tSET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 2);\n\t\tRTW_INFO(\"%s, line%d, Set MAX MPDU len = 11454 bytes\\n\", __FUNCTION__, __LINE__);\n\t} else if ((max_recvbuf_sz - rx_packet_offset) >= 7991) {\n\t\tSET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 1);\n\t\tRTW_INFO(\"%s, line%d, Set MAX MPDU len = 7991 bytes\\n\", __FUNCTION__, __LINE__);\n\t} else if ((max_recvbuf_sz - rx_packet_offset) >= 3895) {\n\t\tSET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 0);\n\t\tRTW_INFO(\"%s, line%d, Set MAX MPDU len = 3895 bytes\\n\", __FUNCTION__, __LINE__);\n\t} else\n\t\tRTW_ERR(\"%s, line%d, Error!! Available RX buf size < 3895 bytes\\n\", __FUNCTION__, __LINE__);\n\n\t/* B2 B3 Supported Channel Width Set */\n\tif (hal_chk_bw_cap(padapter, BW_CAP_160M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_160)) {\n\t\tif (hal_chk_bw_cap(padapter, BW_CAP_80_80M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_80_80))\n\t\t\tSET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 2);\n\t\telse\n\t\t\tSET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 1);\n\t} else\n\t\tSET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 0);\n\n\t/* B4 Rx LDPC */\n\tif (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) {\n\t\tSET_VHT_CAPABILITY_ELE_RX_LDPC(pcap, 1);\n\t\tRTW_INFO(\"[VHT] Declare supporting RX LDPC\\n\");\n\t}\n\n\t/* B5 ShortGI for 80MHz */\n\tSET_VHT_CAPABILITY_ELE_SHORT_GI80M(pcap, pvhtpriv->sgi_80m ? 1 : 0); /* We can receive Short GI of 80M */\n\tif (pvhtpriv->sgi_80m)\n\t\tRTW_INFO(\"[VHT] Declare supporting SGI 80MHz\\n\");\n\n\t/* B6 ShortGI for 160MHz */\n\t/* SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pcap, pvhtpriv->sgi_80m? 1 : 0); */\n\n\t/* B7 Tx STBC */\n\tif (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) {\n\t\tSET_VHT_CAPABILITY_ELE_TX_STBC(pcap, 1);\n\t\tRTW_INFO(\"[VHT] Declare supporting TX STBC\\n\");\n\t}\n\n\t/* B8 B9 B10 Rx STBC */\n\tif (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) {\n\t\trtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss));\n\n\t\tSET_VHT_CAPABILITY_ELE_RX_STBC(pcap, rx_stbc_nss);\n\t\tRTW_INFO(\"[VHT] Declare supporting RX STBC = %d\\n\", rx_stbc_nss);\n\t}\n\t#ifdef CONFIG_BEAMFORMING\n\t/* B11 SU Beamformer Capable */\n\tif (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {\n\t\tSET_VHT_CAPABILITY_ELE_SU_BFER(pcap, 1);\n\t\tRTW_INFO(\"[VHT] Declare supporting SU Bfer\\n\");\n\t\t/* B16 17 18 Number of Sounding Dimensions */\n\t\trtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num);\n\t\tSET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(pcap, rf_num);\n\t\t/* B19 MU Beamformer Capable */\n\t\tif (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) {\n\t\t\tSET_VHT_CAPABILITY_ELE_MU_BFER(pcap, 1);\n\t\t\tRTW_INFO(\"[VHT] Declare supporting MU Bfer\\n\");\n\t\t}\n\t}\n\n\t/* B12 SU Beamformee Capable */\n\tif (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {\n\t\tSET_VHT_CAPABILITY_ELE_SU_BFEE(pcap, 1);\n\t\tRTW_INFO(\"[VHT] Declare supporting SU Bfee\\n\");\n\n\t\trtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);\n\n\t\t/* IOT action suggested by Yu Chen 2017/3/3 */\n#ifdef CONFIG_80211AC_VHT\n\t\tif ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) &&\n\t\t\t!pvhtpriv->ap_is_mu_bfer)\n\t\t\trf_num = (rf_num >= 2 ? 2 : rf_num);\n#endif\n\t\t/* B13 14 15 Compressed Steering Number of Beamformer Antennas Supported */\n\t\tSET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(pcap, rf_num);\n\t\t/* B20 SU Beamformee Capable */\n\t\tif (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) {\n\t\t\tSET_VHT_CAPABILITY_ELE_MU_BFEE(pcap, 1);\n\t\t\tRTW_INFO(\"[VHT] Declare supporting MU Bfee\\n\");\n\t\t}\n\t}\n\t#endif/*CONFIG_BEAMFORMING*/\n\n\t/* B21 VHT TXOP PS */\n\tSET_VHT_CAPABILITY_ELE_TXOP_PS(pcap, 0);\n\t/* B22 +HTC-VHT Capable */\n\tSET_VHT_CAPABILITY_ELE_HTC_VHT(pcap, 1);\n\t/* B23 24 25 Maximum A-MPDU Length Exponent */\n\tif (pregistrypriv->ampdu_factor != 0xFE)\n\t\tSET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, pregistrypriv->ampdu_factor);\n\telse\n\t\tSET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, 7);\n\t/* B26 27 VHT Link Adaptation Capable */\n\tSET_VHT_CAPABILITY_ELE_LINK_ADAPTION(pcap, 0);\n\n\tpcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pcap);\n\t_rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2);\n\n\tpcap_mcs = GET_VHT_CAPABILITY_ELE_TX_MCS(pcap);\n\t_rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2);\n\n\t/* find the largest bw supported by both registry and hal */\n\tbw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv));\n\n\tHighestRate = VHT_MCS_DATA_RATE[bw][pvhtpriv->sgi_80m][((pvhtpriv->vht_highest_rate - MGN_VHT1SS_MCS0) & 0x3f)];\n\tHighestRate = (HighestRate + 1) >> 1;\n\n\tSET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(pcap, HighestRate); /* indicate we support highest rx rate is 600Mbps. */\n\tSET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(pcap, HighestRate); /* indicate we support highest tx rate is 600Mbps. */\n\n\tpbuf = rtw_set_ie(pbuf, EID_VHTCapability, 12, pcap, &len);\n\n\treturn len;\n}\n\nu32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tRT_CHANNEL_INFO *chset = rfctl->channel_set;\n\tu32\tielen;\n\tu8 max_bw;\n\tu8 oper_ch, oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\tu8 *out_vht_op_ie, *ht_op_ie, *vht_cap_ie, *vht_op_ie;\n\tstruct registry_priv *pregistrypriv = &padapter->registrypriv;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct vht_priv\t*pvhtpriv = &pmlmepriv->vhtpriv;\n\n\trtw_vht_use_default_setting(padapter);\n\n\tht_op_ie = rtw_get_ie(in_ie + 12, WLAN_EID_HT_OPERATION, &ielen, in_len - 12);\n\tif (!ht_op_ie || ielen != HT_OP_IE_LEN)\n\t\tgoto exit;\n\tvht_cap_ie = rtw_get_ie(in_ie + 12, EID_VHTCapability, &ielen, in_len - 12);\n\tif (!vht_cap_ie || ielen != VHT_CAP_IE_LEN)\n\t\tgoto exit;\n\tvht_op_ie = rtw_get_ie(in_ie + 12, EID_VHTOperation, &ielen, in_len - 12);\n\tif (!vht_op_ie || ielen != VHT_OP_IE_LEN)\n\t\tgoto exit;\n\n\t/* VHT Capabilities element */\n\t*pout_len += rtw_build_vht_cap_ie(padapter, out_ie + *pout_len);\n\n\n\t/* VHT Operation element */\n\tout_vht_op_ie = out_ie + *pout_len;\n\trtw_set_ie(out_vht_op_ie, EID_VHTOperation, VHT_OP_IE_LEN, vht_op_ie + 2 , pout_len);\n\n\t/* get primary channel from HT_OP_IE */\n\toper_ch = GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2);\n\n\t/* find the largest bw supported by both registry and hal */\n\tmax_bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv));\n\n\tif (max_bw >= CHANNEL_WIDTH_40) {\n\t\t/* get bw offset form HT_OP_IE */\n\t\tif (GET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2)) {\n\t\t\tswitch (GET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2)) {\n\t\t\tcase SCA:\n\t\t\t\toper_bw = CHANNEL_WIDTH_40;\n\t\t\t\toper_offset = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\t\t\tbreak;\n\t\t\tcase SCB:\n\t\t\t\toper_bw = CHANNEL_WIDTH_40;\n\t\t\t\toper_offset = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tif (oper_bw == CHANNEL_WIDTH_40) {\n\t\t\tswitch (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2)) {\n\t\t\tcase 1: /* 80MHz */\n\t\t\tcase 2: /* 160MHz */\n\t\t\tcase 3: /* 80+80 */\n\t\t\t\toper_bw = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\toper_bw = rtw_min(oper_bw, max_bw);\n\n\t\t\t/* try downgrage bw to fit in channel plan setting */\n\t\t\twhile (!rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset)\n\t\t\t\t|| (IS_DFS_SLAVE_WITH_RD(rfctl)\n\t\t\t\t\t&& !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))\n\t\t\t\t\t&& rtw_chset_is_chbw_non_ocp(chset, oper_ch, oper_bw, oper_offset))\n\t\t\t) {\n\t\t\t\toper_bw--;\n\t\t\t\tif (oper_bw == CHANNEL_WIDTH_20) {\n\t\t\t\t\toper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\trtw_warn_on(!rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset));\n\tif (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl)))\n\t\trtw_warn_on(rtw_chset_is_chbw_non_ocp(chset, oper_ch, oper_bw, oper_offset));\n\n\t/* update VHT_OP_IE */\n\tif (oper_bw < CHANNEL_WIDTH_80) {\n\t\tSET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 0);\n\t\tSET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, 0);\n\t\tSET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0);\n\t} else if (oper_bw == CHANNEL_WIDTH_80) {\n\t\tu8 cch = rtw_get_center_ch(oper_ch, oper_bw, oper_offset);\n\n\t\tSET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 1);\n\t\tSET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, cch);\n\t\tSET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0);\n\t} else {\n\t\tRTW_ERR(FUNC_ADPT_FMT\" unsupported BW:%u\\n\", FUNC_ADPT_ARG(padapter), oper_bw);\n\t\trtw_warn_on(1);\n\t}\n\n\t/* Operating Mode Notification element */\n\t*pout_len += rtw_build_vht_op_mode_notify_ie(padapter, out_ie + *pout_len, oper_bw);\n\n\tpvhtpriv->vht_option = _TRUE;\n\nexit:\n\treturn pvhtpriv->vht_option;\n\n}\n\nvoid VHTOnAssocRsp(_adapter *padapter)\n{\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct vht_priv\t\t*pvhtpriv = &pmlmepriv->vhtpriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8\tht_AMPDU_len;\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\tif (!pmlmeinfo->HT_enable)\n\t\treturn;\n\n\tif (!pmlmeinfo->VHT_enable)\n\t\treturn;\n\n\tht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;\n\n\tif (pvhtpriv->ampdu_len > ht_AMPDU_len)\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len));\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MAX_TIME, (u8 *)(&pvhtpriv->vht_highest_rate));\n}\n\nvoid rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pnetwork)\n{\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tu8 cap_len, operation_len;\n\tuint len = 0;\n\tsint ie_len = 0;\n\tu8 *p = NULL;\n\n\tp = rtw_get_ie(pnetwork->IEs + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len,\n\t\t\t(pnetwork->IELength - _BEACON_IE_OFFSET_));\n\tif (p && ie_len > 0)\n\t\treturn;\n\n\trtw_vht_use_default_setting(padapter);\n\n\t/* VHT Operation mode notifiy bit in Extended IE (127) */\n\tSET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(pmlmepriv->ext_capab_ie_data, 1);\n\tpmlmepriv->ext_capab_ie_len = 10;\n\trtw_set_ie(pnetwork->IEs + pnetwork->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len);\n\tpnetwork->IELength += pmlmepriv->ext_capab_ie_len;\n\n\t/* VHT Capabilities element */\n\tcap_len = rtw_build_vht_cap_ie(padapter, pnetwork->IEs + pnetwork->IELength);\n\tpnetwork->IELength += cap_len;\n\n\t/* VHT Operation element */\n\toperation_len = rtw_build_vht_operation_ie(padapter, pnetwork->IEs + pnetwork->IELength,\n\t\t\t\t\t\t\t\t\t\tpnetwork->Configuration.DSConfig);\n\tpnetwork->IELength += operation_len;\n\n\trtw_check_for_vht20(padapter, pnetwork->IEs + _BEACON_IE_OFFSET_, pnetwork->IELength - _BEACON_IE_OFFSET_);\n\n\tpmlmepriv->vhtpriv.vht_option = _TRUE;\n}\n\nvoid rtw_vht_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pnetwork)\n{\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\trtw_remove_bcn_ie(padapter, pnetwork, EID_EXTCapability);\n\trtw_remove_bcn_ie(padapter, pnetwork, EID_VHTCapability);\n\trtw_remove_bcn_ie(padapter, pnetwork, EID_VHTOperation);\n\n\tpmlmepriv->vhtpriv.vht_option = _FALSE;\n}\n\nvoid rtw_check_for_vht20(_adapter *adapter, u8 *ies, int ies_len)\n{\n\tu8 ht_ch, ht_bw, ht_offset;\n\tu8 vht_ch, vht_bw, vht_offset;\n\n\trtw_ies_get_chbw(ies, ies_len, &ht_ch, &ht_bw, &ht_offset, 1, 0);\n\trtw_ies_get_chbw(ies, ies_len, &vht_ch, &vht_bw, &vht_offset, 1, 1);\n\n\tif (ht_bw == CHANNEL_WIDTH_20 && vht_bw >= CHANNEL_WIDTH_80) {\n\t\tu8 *vht_op_ie;\n\t\tint vht_op_ielen;\n\n\t\tRTW_INFO(FUNC_ADPT_FMT\" vht80 is not allowed without ht40\\n\", FUNC_ADPT_ARG(adapter));\n\t\tvht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len);\n\t\tif (vht_op_ie && vht_op_ielen) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" switch to vht20\\n\", FUNC_ADPT_ARG(adapter));\n\t\t\tSET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0);\n\t\t\tSET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0);\n\t\t\tSET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0);\n\t\t}\n\t}\n}\n#endif /* CONFIG_80211AC_VHT */\n"
  },
  {
    "path": "core/rtw_wapi.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifdef CONFIG_WAPI_SUPPORT\n\n#include <linux/unistd.h>\n#include <linux/etherdevice.h>\n#include <drv_types.h>\n#include <rtw_wapi.h>\n\n\nu32 wapi_debug_component =\n\t/*\t\t\t\tWAPI_INIT\t|\n\t *\t\t\t\tWAPI_API\t|\n\t *\t\t\t\tWAPI_TX\t|\n\t *\t\t\t\tWAPI_RX\t| */\n\tWAPI_ERR ; /* always open err flags on */\n\nvoid WapiFreeAllStaInfo(_adapter *padapter)\n{\n\tPRT_WAPI_T\t\t\t\tpWapiInfo;\n\tPRT_WAPI_STA_INFO\t\tpWapiStaInfo;\n\tPRT_WAPI_BKID\t\t\tpWapiBkid;\n\n\tWAPI_TRACE(WAPI_INIT, \"===========> %s\\n\", __FUNCTION__);\n\tpWapiInfo = &padapter->wapiInfo;\n\n\t/* Pust to Idle List */\n\trtw_wapi_return_all_sta_info(padapter);\n\n\t/* Sta Info List */\n\twhile (!list_empty(&(pWapiInfo->wapiSTAIdleList))) {\n\t\tpWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAIdleList.next, RT_WAPI_STA_INFO, list);\n\t\tlist_del_init(&pWapiStaInfo->list);\n\t}\n\n\t/* BKID List */\n\twhile (!list_empty(&(pWapiInfo->wapiBKIDIdleList))) {\n\t\tpWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDIdleList.next, RT_WAPI_BKID, list);\n\t\tlist_del_init(&pWapiBkid->list);\n\t}\n\tWAPI_TRACE(WAPI_INIT, \"<=========== %s\\n\", __FUNCTION__);\n\treturn;\n}\n\nvoid WapiSetIE(_adapter *padapter)\n{\n\tPRT_WAPI_T\t\tpWapiInfo = &(padapter->wapiInfo);\n\t/* PRT_WAPI_BKID\tpWapiBkid; */\n\tu16\t\tprotocolVer = 1;\n\tu16\t\takmCnt = 1;\n\tu16\t\tsuiteCnt = 1;\n\tu16\t\tcapability = 0;\n\tu8\t\tOUI[3];\n\n\tOUI[0] = 0x00;\n\tOUI[1] = 0x14;\n\tOUI[2] = 0x72;\n\n\tpWapiInfo->wapiIELength = 0;\n\t/* protocol version */\n\tmemcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &protocolVer, 2);\n\tpWapiInfo->wapiIELength += 2;\n\t/* akm */\n\tmemcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &akmCnt, 2);\n\tpWapiInfo->wapiIELength += 2;\n\n\tif (pWapiInfo->bWapiPSK) {\n\t\tmemcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3);\n\t\tpWapiInfo->wapiIELength += 3;\n\t\tpWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x2;\n\t\tpWapiInfo->wapiIELength += 1;\n\t} else {\n\t\tmemcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3);\n\t\tpWapiInfo->wapiIELength += 3;\n\t\tpWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1;\n\t\tpWapiInfo->wapiIELength += 1;\n\t}\n\n\t/* usk */\n\tmemcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &suiteCnt, 2);\n\tpWapiInfo->wapiIELength += 2;\n\tmemcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3);\n\tpWapiInfo->wapiIELength += 3;\n\tpWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1;\n\tpWapiInfo->wapiIELength += 1;\n\n\t/* msk */\n\tmemcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3);\n\tpWapiInfo->wapiIELength += 3;\n\tpWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1;\n\tpWapiInfo->wapiIELength += 1;\n\n\t/* Capbility */\n\tmemcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &capability, 2);\n\tpWapiInfo->wapiIELength += 2;\n}\n\n\n/*  PN1 > PN2, return 1,\n *  else return 0.\n */\nu32 WapiComparePN(u8 *PN1, u8 *PN2)\n{\n\tchar i;\n\n\tif ((NULL == PN1) || (NULL == PN2))\n\t\treturn 1;\n\n\t/* overflow case */\n\tif ((PN2[15] - PN1[15]) & 0x80)\n\t\treturn 1;\n\n\tfor (i = 16; i > 0; i--) {\n\t\tif (PN1[i - 1] == PN2[i - 1])\n\t\t\tcontinue;\n\t\telse if (PN1[i - 1] > PN2[i - 1])\n\t\t\treturn 1;\n\t\telse\n\t\t\treturn 0;\n\t}\n\n\treturn 0;\n}\n\nu8\nWapiGetEntryForCamWrite(_adapter *padapter, u8 *pMacAddr, u8 KID, BOOLEAN IsMsk)\n{\n\tPRT_WAPI_T\t\tpWapiInfo = NULL;\n\t/* PRT_WAPI_CAM_ENTRY\tpEntry=NULL; */\n\tu8 i = 0;\n\tu8 ret = 0xff;\n\n\tWAPI_TRACE(WAPI_API, \"===========> %s\\n\", __FUNCTION__);\n\n\tpWapiInfo =  &padapter->wapiInfo;\n\n\t/* exist? */\n\tfor (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {\n\t\tif (pWapiInfo->wapiCamEntry[i].IsUsed\n\t\t    && (_rtw_memcmp(pMacAddr, pWapiInfo->wapiCamEntry[i].PeerMacAddr, ETH_ALEN) == _TRUE)\n\t\t    && pWapiInfo->wapiCamEntry[i].keyidx == KID\n\t\t    && pWapiInfo->wapiCamEntry[i].type == IsMsk) {\n\t\t\tret = pWapiInfo->wapiCamEntry[i].entry_idx; /* cover it */\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (i == WAPI_CAM_ENTRY_NUM) { /* not found */\n\t\tfor (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {\n\t\t\tif (pWapiInfo->wapiCamEntry[i].IsUsed == 0) {\n\t\t\t\tpWapiInfo->wapiCamEntry[i].IsUsed = 1;\n\t\t\t\tpWapiInfo->wapiCamEntry[i].type = IsMsk;\n\t\t\t\tpWapiInfo->wapiCamEntry[i].keyidx = KID;\n\t\t\t\t_rtw_memcpy(pWapiInfo->wapiCamEntry[i].PeerMacAddr, pMacAddr, ETH_ALEN);\n\t\t\t\tret = pWapiInfo->wapiCamEntry[i].entry_idx;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tWAPI_TRACE(WAPI_API, \"<========== %s\\n\", __FUNCTION__);\n\treturn ret;\n\n\t/*\n\t\tif(RTIsListEmpty(&pWapiInfo->wapiCamIdleList)) {\n\t\t\treturn 0;\n\t\t}\n\n\t\tpEntry = (PRT_WAPI_CAM_ENTRY)RTRemoveHeadList(&pWapiInfo->wapiCamIdleList);\n\t\tRTInsertTailList(&pWapiInfo->wapiCamUsedList, &pEntry->list);\n\n\n\t\treturn pEntry->entry_idx;*/\n}\n\nu8 WapiGetEntryForCamClear(_adapter *padapter, u8 *pPeerMac, u8 keyid, u8 IsMsk)\n{\n\tPRT_WAPI_T\t\tpWapiInfo = NULL;\n\tu8\t\ti = 0;\n\n\tWAPI_TRACE(WAPI_API, \"===========> %s\\n\", __FUNCTION__);\n\n\tpWapiInfo =  &padapter->wapiInfo;\n\n\tfor (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {\n\t\tif (pWapiInfo->wapiCamEntry[i].IsUsed\n\t\t    && (_rtw_memcmp(pPeerMac, pWapiInfo->wapiCamEntry[i].PeerMacAddr, ETH_ALEN) == _TRUE)\n\t\t    && pWapiInfo->wapiCamEntry[i].keyidx == keyid\n\t\t    && pWapiInfo->wapiCamEntry[i].type == IsMsk) {\n\t\t\tpWapiInfo->wapiCamEntry[i].IsUsed = 0;\n\t\t\tpWapiInfo->wapiCamEntry[i].keyidx = 2;\n\t\t\t_rtw_memset(pWapiInfo->wapiCamEntry[i].PeerMacAddr, 0, ETH_ALEN);\n\n\t\t\tWAPI_TRACE(WAPI_API, \"<========== %s\\n\", __FUNCTION__);\n\t\t\treturn pWapiInfo->wapiCamEntry[i].entry_idx;\n\t\t}\n\t}\n\n\tWAPI_TRACE(WAPI_API, \"<====WapiGetReturnCamEntry(), No this cam entry.\\n\");\n\treturn 0xff;\n\t/*\n\t\tif(RTIsListEmpty(&pWapiInfo->wapiCamUsedList)) {\n\t\t\treturn FALSE;\n\t\t}\n\n\t\tpList = &pWapiInfo->wapiCamUsedList;\n\t\twhile(pList->Flink != &pWapiInfo->wapiCamUsedList)\n\t\t{\n\t\t\tpEntry = (PRT_WAPI_CAM_ENTRY)pList->Flink;\n\t\t\tif(PlatformCompareMemory(pPeerMac,pEntry->PeerMacAddr, ETHER_ADDRLEN)== 0\n\t\t\t\t&& keyid == pEntry->keyidx)\n\t\t\t{\n\t\t\t\tRTRemoveEntryList(pList);\n\t\t\t\tRTInsertHeadList(&pWapiInfo->wapiCamIdleList, pList);\n\t\t\t\treturn pEntry->entry_idx;\n\t\t\t}\n\t\t\tpList = pList->Flink;\n\t\t}\n\n\t\treturn 0;\n\t*/\n}\n\nvoid\nWapiResetAllCamEntry(_adapter *padapter)\n{\n\tPRT_WAPI_T\t\tpWapiInfo;\n\tint\t\t\t\ti;\n\n\tWAPI_TRACE(WAPI_API, \"===========> %s\\n\", __FUNCTION__);\n\n\tpWapiInfo =  &padapter->wapiInfo;\n\n\tfor (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {\n\t\t_rtw_memset(pWapiInfo->wapiCamEntry[i].PeerMacAddr, 0, ETH_ALEN);\n\t\tpWapiInfo->wapiCamEntry[i].IsUsed = 0;\n\t\tpWapiInfo->wapiCamEntry[i].keyidx = 2; /* invalid */\n\t\tpWapiInfo->wapiCamEntry[i].entry_idx = 4 + i * 2;\n\t}\n\n\tWAPI_TRACE(WAPI_API, \"<========== %s\\n\", __FUNCTION__);\n\n\treturn;\n}\n\nu8 WapiWriteOneCamEntry(\n\t_adapter\t*padapter,\n\tu8\t\t\t*pMacAddr,\n\tu8\t\t\tKeyId,\n\tu8\t\t\tEntryId,\n\tu8\t\t\tEncAlg,\n\tu8\t\t\tbGroupKey,\n\tu8\t\t\t*pKey\n)\n{\n\tu8 retVal = 0;\n\tu16 usConfig = 0;\n\n\tWAPI_TRACE(WAPI_API, \"===========> %s\\n\", __FUNCTION__);\n\n\tif (EntryId >= 32) {\n\t\tWAPI_TRACE(WAPI_ERR, \"<=== CamAddOneEntry(): ulKeyId exceed!\\n\");\n\t\treturn retVal;\n\t}\n\n\tusConfig = usConfig | (0x01 << 15) | ((u16)(EncAlg) << 2) | (KeyId);\n\n\tif (EncAlg == _SMS4_) {\n\t\tif (bGroupKey == 1)\n\t\t\tusConfig |= (0x01 << 6);\n\t\tif ((EntryId % 2) == 1) /* ==0 sec key; == 1mic key */\n\t\t\tusConfig |= (0x01 << 5);\n\t}\n\n\twrite_cam(padapter, EntryId, usConfig, pMacAddr, pKey);\n\n\tWAPI_TRACE(WAPI_API, \"===========> %s\\n\", __FUNCTION__);\n\treturn 1;\n}\n\nvoid rtw_wapi_init(_adapter *padapter)\n{\n\tPRT_WAPI_T\t\tpWapiInfo;\n\tint\t\t\t\ti;\n\n\tWAPI_TRACE(WAPI_INIT, \"===========> %s\\n\", __FUNCTION__);\n\tRT_ASSERT_RET(padapter);\n\n\tif (!padapter->WapiSupport) {\n\t\tWAPI_TRACE(WAPI_INIT, \"<========== %s, WAPI not supported!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tpWapiInfo =  &padapter->wapiInfo;\n\tpWapiInfo->bWapiEnable = false;\n\n\t/* Init BKID List */\n\tINIT_LIST_HEAD(&pWapiInfo->wapiBKIDIdleList);\n\tINIT_LIST_HEAD(&pWapiInfo->wapiBKIDStoreList);\n\tfor (i = 0; i < WAPI_MAX_BKID_NUM; i++)\n\t\tlist_add_tail(&pWapiInfo->wapiBKID[i].list, &pWapiInfo->wapiBKIDIdleList);\n\n\t/* Init STA List */\n\tINIT_LIST_HEAD(&pWapiInfo->wapiSTAIdleList);\n\tINIT_LIST_HEAD(&pWapiInfo->wapiSTAUsedList);\n\tfor (i = 0; i < WAPI_MAX_STAINFO_NUM; i++)\n\t\tlist_add_tail(&pWapiInfo->wapiSta[i].list, &pWapiInfo->wapiSTAIdleList);\n\n\tfor (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {\n\t\tpWapiInfo->wapiCamEntry[i].IsUsed = 0;\n\t\tpWapiInfo->wapiCamEntry[i].keyidx = 2; /* invalid */\n\t\tpWapiInfo->wapiCamEntry[i].entry_idx = 4 + i * 2;\n\t}\n\n\tWAPI_TRACE(WAPI_INIT, \"<========== %s\\n\", __FUNCTION__);\n}\n\nvoid rtw_wapi_free(_adapter *padapter)\n{\n\tWAPI_TRACE(WAPI_INIT, \"===========> %s\\n\", __FUNCTION__);\n\tRT_ASSERT_RET(padapter);\n\n\tif (!padapter->WapiSupport) {\n\t\tWAPI_TRACE(WAPI_INIT, \"<========== %s, WAPI not supported!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tWapiFreeAllStaInfo(padapter);\n\n\tWAPI_TRACE(WAPI_INIT, \"<========== %s\\n\", __FUNCTION__);\n}\n\nvoid rtw_wapi_disable_tx(_adapter *padapter)\n{\n\tWAPI_TRACE(WAPI_INIT, \"===========> %s\\n\", __FUNCTION__);\n\tRT_ASSERT_RET(padapter);\n\n\tif (!padapter->WapiSupport) {\n\t\tWAPI_TRACE(WAPI_INIT, \"<========== %s, WAPI not supported!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tpadapter->wapiInfo.wapiTxMsk.bTxEnable = false;\n\tpadapter->wapiInfo.wapiTxMsk.bSet = false;\n\n\tWAPI_TRACE(WAPI_INIT, \"<========== %s\\n\", __FUNCTION__);\n}\n\nu8 rtw_wapi_is_wai_packet(_adapter *padapter, u8 *pkt_data)\n{\n\tPRT_WAPI_T pWapiInfo = &(padapter->wapiInfo);\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct security_priv   *psecuritypriv = &padapter->securitypriv;\n\tPRT_WAPI_STA_INFO pWapiSta = NULL;\n\tu8 WaiPkt = 0, *pTaddr, bFind = false;\n\tu8 Offset_TypeWAI = 0 ;\t/* (mac header len + llc length) */\n\n\tWAPI_TRACE(WAPI_TX | WAPI_RX, \"===========> %s\\n\", __FUNCTION__);\n\n\tif ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {\n\t\tWAPI_TRACE(WAPI_MLME, \"<========== %s, WAPI not supported or not enabled!\\n\", __FUNCTION__);\n\t\treturn 0;\n\t}\n\n\tOffset_TypeWAI = 24 + 6 ;\n\n\t/* YJ,add,091103. Data frame may also have skb->data[30]=0x88 and skb->data[31]=0xb4. */\n\tif ((pkt_data[1] & 0x40) != 0) {\n\t\t/* RTW_INFO(\"data is privacy\\n\"); */\n\t\treturn 0;\n\t}\n\n\tpTaddr = get_addr2_ptr(pkt_data);\n\tif (list_empty(&pWapiInfo->wapiSTAUsedList))\n\t\tbFind = false;\n\telse {\n\t\tlist_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {\n\t\t\tif (_rtw_memcmp(pTaddr, pWapiSta->PeerMacAddr, 6) == _TRUE) {\n\t\t\t\tbFind = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tWAPI_TRACE(WAPI_TX | WAPI_RX, \"%s: bFind=%d pTaddr=\"MAC_FMT\"\\n\", __FUNCTION__, bFind, MAC_ARG(pTaddr));\n\n\tif (pkt_data[0] == WIFI_QOS_DATA_TYPE)\n\t\tOffset_TypeWAI += 2;\n\n\t/* 88b4? */\n\tif ((pkt_data[Offset_TypeWAI] == 0x88) && (pkt_data[Offset_TypeWAI + 1] == 0xb4)) {\n\t\tWaiPkt = pkt_data[Offset_TypeWAI + 5];\n\n\t\tpsecuritypriv->hw_decrypted = _TRUE;\n\t} else\n\t\tWAPI_TRACE(WAPI_TX | WAPI_RX, \"%s(): non wai packet\\n\", __FUNCTION__);\n\n\tWAPI_TRACE(WAPI_TX | WAPI_RX, \"%s(): Recvd WAI frame. IsWAIPkt(%d)\\n\", __FUNCTION__, WaiPkt);\n\n\treturn\tWaiPkt;\n}\n\n\nvoid rtw_wapi_update_info(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tPRT_WAPI_T     pWapiInfo = &(padapter->wapiInfo);\n\tstruct recv_frame_hdr *precv_hdr;\n\tu8\t*ptr;\n\tu8\t*pTA;\n\tu8\t*pRecvPN;\n\n\n\tWAPI_TRACE(WAPI_RX, \"===========> %s\\n\", __FUNCTION__);\n\n\tif ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {\n\t\tWAPI_TRACE(WAPI_RX, \"<========== %s, WAPI not supported or not enabled!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tprecv_hdr = &precv_frame->u.hdr;\n\tptr = precv_hdr->rx_data;\n\n\tif (precv_hdr->attrib.qos == 1)\n\t\tprecv_hdr->UserPriority = GetTid(ptr);\n\telse\n\t\tprecv_hdr->UserPriority = 0;\n\n\tpTA = get_addr2_ptr(ptr);\n\t_rtw_memcpy((u8 *)precv_hdr->WapiSrcAddr, pTA, 6);\n\tpRecvPN = ptr + precv_hdr->attrib.hdrlen + 2;\n\t_rtw_memcpy((u8 *)precv_hdr->WapiTempPN, pRecvPN, 16);\n\n\tWAPI_TRACE(WAPI_RX, \"<========== %s\\n\", __FUNCTION__);\n}\n\n/****************************************************************************\nTRUE-----------------Drop\nFALSE---------------- handle\nadd to support WAPI to N-mode\n*****************************************************************************/\nu8 rtw_wapi_check_for_drop(\n\t_adapter *padapter,\n\tunion recv_frame *precv_frame,\n\tu8 *ehdr_ops\n)\n{\n\tPRT_WAPI_T     pWapiInfo = &(padapter->wapiInfo);\n\tu8\t\t\t*pLastRecvPN = NULL;\n\tu8\t\t\tbFind = false;\n\tPRT_WAPI_STA_INFO\tpWapiSta = NULL;\n\tu8\t\t\tbDrop = false;\n\tstruct recv_frame_hdr *precv_hdr = &precv_frame->u.hdr;\n\tu8\t\t\t\t\tWapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;\n\tu8\t\t\t\t\tWapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;\n\tu8\t\t\t\t\t*ptr = ehdr_ops;\n\tint\t\t\t\t\ti;\n\n\tWAPI_TRACE(WAPI_RX, \"===========> %s\\n\", __FUNCTION__);\n\n\tif ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {\n\t\tWAPI_TRACE(WAPI_RX, \"<========== %s, WAPI not supported or not enabled!\\n\", __FUNCTION__);\n\t\treturn false;\n\t}\n\n\tif (precv_hdr->bIsWaiPacket != 0) {\n\t\tif (precv_hdr->bIsWaiPacket == 0x8) {\n\n\t\t\tRTW_INFO(\"rtw_wapi_check_for_drop: dump packet\\n\");\n\t\t\tfor (i = 0; i < 50; i++) {\n\t\t\t\tRTW_INFO(\"%02X  \", ptr[i]);\n\t\t\t\tif ((i + 1) % 8 == 0)\n\t\t\t\t\tRTW_INFO(\"\\n\");\n\t\t\t}\n\t\t\tRTW_INFO(\"\\n rtw_wapi_check_for_drop: dump packet\\n\");\n\n\t\t\tfor (i = 0; i < 16; i++) {\n\t\t\t\tif (ptr[i + 27] != 0)\n\t\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif (i == 16) {\n\t\t\t\tWAPI_TRACE(WAPI_RX, \"rtw_wapi_check_for_drop: drop with zero BKID\\n\");\n\t\t\t\treturn true;\n\t\t\t} else\n\t\t\t\treturn false;\n\t\t} else\n\t\t\treturn false;\n\t}\n\n\tif (list_empty(&pWapiInfo->wapiSTAUsedList))\n\t\tbFind = false;\n\telse {\n\t\tlist_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {\n\t\t\tif (_rtw_memcmp(precv_hdr->WapiSrcAddr, pWapiSta->PeerMacAddr, ETH_ALEN) == _TRUE) {\n\t\t\t\tbFind = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\tWAPI_TRACE(WAPI_RX, \"%s: bFind=%d prxb->WapiSrcAddr=\"MAC_FMT\"\\n\", __FUNCTION__, bFind, MAC_ARG(precv_hdr->WapiSrcAddr));\n\n\tif (bFind) {\n\t\tif (IS_MCAST(precv_hdr->attrib.ra)) {\n\t\t\tWAPI_TRACE(WAPI_RX, \"rtw_wapi_check_for_drop: multicast case\\n\");\n\t\t\tpLastRecvPN = pWapiSta->lastRxMulticastPN;\n\t\t} else {\n\t\t\tWAPI_TRACE(WAPI_RX, \"rtw_wapi_check_for_drop: unicast case\\n\");\n\t\t\tswitch (precv_hdr->UserPriority) {\n\t\t\tcase 0:\n\t\t\tcase 3:\n\t\t\t\tpLastRecvPN = pWapiSta->lastRxUnicastPNBEQueue;\n\t\t\t\tbreak;\n\t\t\tcase 1:\n\t\t\tcase 2:\n\t\t\t\tpLastRecvPN = pWapiSta->lastRxUnicastPNBKQueue;\n\t\t\t\tbreak;\n\t\t\tcase 4:\n\t\t\tcase 5:\n\t\t\t\tpLastRecvPN = pWapiSta->lastRxUnicastPNVIQueue;\n\t\t\t\tbreak;\n\t\t\tcase 6:\n\t\t\tcase 7:\n\t\t\t\tpLastRecvPN = pWapiSta->lastRxUnicastPNVOQueue;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tWAPI_TRACE(WAPI_ERR, \"%s: Unknown TID\\n\", __FUNCTION__);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tif (!WapiComparePN(precv_hdr->WapiTempPN, pLastRecvPN)) {\n\t\t\tWAPI_TRACE(WAPI_RX, \"%s: Equal PN!!\\n\", __FUNCTION__);\n\t\t\tif (IS_MCAST(precv_hdr->attrib.ra))\n\t\t\t\t_rtw_memcpy(pLastRecvPN, WapiAEMultiCastPNInitialValueSrc, 16);\n\t\t\telse\n\t\t\t\t_rtw_memcpy(pLastRecvPN, WapiAEPNInitialValueSrc, 16);\n\t\t\tbDrop = true;\n\t\t} else\n\t\t\t_rtw_memcpy(pLastRecvPN, precv_hdr->WapiTempPN, 16);\n\t}\n\n\tWAPI_TRACE(WAPI_RX, \"<========== %s\\n\", __FUNCTION__);\n\treturn bDrop;\n}\n\nvoid rtw_build_probe_resp_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib)\n{\n\tPRT_WAPI_T pWapiInfo = &(padapter->wapiInfo);\n\tu8 WapiIELength = 0;\n\n\tWAPI_TRACE(WAPI_MLME, \"===========> %s\\n\", __FUNCTION__);\n\n\tif ((!padapter->WapiSupport)  || (!pWapiInfo->bWapiEnable)) {\n\t\tWAPI_TRACE(WAPI_MLME, \"<========== %s, WAPI not supported!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tWapiSetIE(padapter);\n\tWapiIELength = pWapiInfo->wapiIELength;\n\tpframe[0] = _WAPI_IE_;\n\tpframe[1] = WapiIELength;\n\t_rtw_memcpy(pframe + 2, pWapiInfo->wapiIE, WapiIELength);\n\tpframe += WapiIELength + 2;\n\tpattrib->pktlen += WapiIELength + 2;\n\n\tWAPI_TRACE(WAPI_MLME, \"<========== %s\\n\", __FUNCTION__);\n}\n\nvoid rtw_build_beacon_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib)\n{\n\tPRT_WAPI_T pWapiInfo = &(padapter->wapiInfo);\n\tu8 WapiIELength = 0;\n\tWAPI_TRACE(WAPI_MLME, \"===========> %s\\n\", __FUNCTION__);\n\n\tif ((!padapter->WapiSupport)  || (!pWapiInfo->bWapiEnable)) {\n\t\tWAPI_TRACE(WAPI_MLME, \"<========== %s, WAPI not supported!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tWapiSetIE(padapter);\n\tWapiIELength = pWapiInfo->wapiIELength;\n\tpframe[0] = _WAPI_IE_;\n\tpframe[1] = WapiIELength;\n\t_rtw_memcpy(pframe + 2, pWapiInfo->wapiIE, WapiIELength);\n\tpframe += WapiIELength + 2;\n\tpattrib->pktlen += WapiIELength + 2;\n\n\tWAPI_TRACE(WAPI_MLME, \"<========== %s\\n\", __FUNCTION__);\n}\n\nvoid rtw_build_assoc_req_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib)\n{\n\tPRT_WAPI_BKID\t\tpWapiBKID;\n\tu16\t\t\t\t\tbkidNum;\n\tPRT_WAPI_T\t\t\tpWapiInfo = &(padapter->wapiInfo);\n\tu8\t\t\t\t\tWapiIELength = 0;\n\n\tWAPI_TRACE(WAPI_MLME, \"===========> %s\\n\", __FUNCTION__);\n\n\tif ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {\n\t\tWAPI_TRACE(WAPI_MLME, \"<========== %s, WAPI not supported!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tWapiSetIE(padapter);\n\tWapiIELength = pWapiInfo->wapiIELength;\n\tbkidNum = 0;\n\tif (!list_empty(&(pWapiInfo->wapiBKIDStoreList))) {\n\t\tlist_for_each_entry(pWapiBKID, &pWapiInfo->wapiBKIDStoreList, list) {\n\t\t\tbkidNum++;\n\t\t\t_rtw_memcpy(pWapiInfo->wapiIE + WapiIELength + 2, pWapiBKID->bkid, 16);\n\t\t\tWapiIELength += 16;\n\t\t}\n\t}\n\t_rtw_memcpy(pWapiInfo->wapiIE + WapiIELength, &bkidNum, 2);\n\tWapiIELength += 2;\n\n\tpframe[0] = _WAPI_IE_;\n\tpframe[1] = WapiIELength;\n\t_rtw_memcpy(pframe + 2, pWapiInfo->wapiIE, WapiIELength);\n\tpframe += WapiIELength + 2;\n\tpattrib->pktlen += WapiIELength + 2;\n\tWAPI_TRACE(WAPI_MLME, \"<========== %s\\n\", __FUNCTION__);\n}\n\nvoid rtw_wapi_on_assoc_ok(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)\n{\n\tPRT_WAPI_T pWapiInfo = &(padapter->wapiInfo);\n\tPRT_WAPI_STA_INFO pWapiSta;\n\tu8 WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;\n\t/* u8 WapiASUEPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; */\n\tu8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;\n\n\tWAPI_TRACE(WAPI_MLME, \"===========> %s\\n\", __FUNCTION__);\n\n\tif ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {\n\t\tWAPI_TRACE(WAPI_MLME, \"<========== %s, WAPI not supported or not enabled!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tpWapiSta = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAIdleList.next, RT_WAPI_STA_INFO, list);\n\tlist_del_init(&pWapiSta->list);\n\tlist_add_tail(&pWapiSta->list, &pWapiInfo->wapiSTAUsedList);\n\t_rtw_memcpy(pWapiSta->PeerMacAddr, padapter->mlmeextpriv.mlmext_info.network.MacAddress, 6);\n\t_rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16);\n\t_rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiAEPNInitialValueSrc, 16);\n\n\t/* For chenk PN error with Qos Data after s3: add by ylb 20111114 */\n\t_rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiAEPNInitialValueSrc, 16);\n\t_rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiAEPNInitialValueSrc, 16);\n\t_rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiAEPNInitialValueSrc, 16);\n\t_rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiAEPNInitialValueSrc, 16);\n\n\tWAPI_TRACE(WAPI_MLME, \"<========== %s\\n\", __FUNCTION__);\n}\n\n\nvoid rtw_wapi_return_one_sta_info(_adapter *padapter, u8 *MacAddr)\n{\n\tPRT_WAPI_T\t\t\t\tpWapiInfo;\n\tPRT_WAPI_STA_INFO\t\tpWapiStaInfo = NULL;\n\tPRT_WAPI_BKID\t\t\tpWapiBkid = NULL;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\n\tpWapiInfo = &padapter->wapiInfo;\n\n\tWAPI_TRACE(WAPI_API, \"==========> %s\\n\", __FUNCTION__);\n\n\tif ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {\n\t\tWAPI_TRACE(WAPI_MLME, \"<========== %s, WAPI not supported or not enabled!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {\n\t\twhile (!list_empty(&(pWapiInfo->wapiBKIDStoreList))) {\n\t\t\tpWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDStoreList.next, RT_WAPI_BKID, list);\n\t\t\tlist_del_init(&pWapiBkid->list);\n\t\t\t_rtw_memset(pWapiBkid->bkid, 0, 16);\n\t\t\tlist_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDIdleList);\n\t\t}\n\t}\n\n\n\tWAPI_TRACE(WAPI_API, \" %s: after clear bkid\\n\", __FUNCTION__);\n\n\n\t/* Remove STA info */\n\tif (list_empty(&(pWapiInfo->wapiSTAUsedList))) {\n\t\tWAPI_TRACE(WAPI_API, \" %s: wapiSTAUsedList is null\\n\", __FUNCTION__);\n\t\treturn;\n\t} else {\n\n\t\tWAPI_TRACE(WAPI_API, \" %s: wapiSTAUsedList is not null\\n\", __FUNCTION__);\n#if 0\n\t\tpWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry((pWapiInfo->wapiSTAUsedList.next), RT_WAPI_STA_INFO, list);\n\n\t\tlist_for_each_entry(pWapiStaInfo, &(pWapiInfo->wapiSTAUsedList), list) {\n\n\t\t\tRTW_INFO(\"MAC Addr %02x-%02x-%02x-%02x-%02x-%02x\\n\", MacAddr[0], MacAddr[1], MacAddr[2], MacAddr[3], MacAddr[4], MacAddr[5]);\n\n\n\t\t\tRTW_INFO(\"peer Addr %02x-%02x-%02x-%02x-%02x-%02x\\n\", pWapiStaInfo->PeerMacAddr[0], pWapiStaInfo->PeerMacAddr[1], pWapiStaInfo->PeerMacAddr[2], pWapiStaInfo->PeerMacAddr[3],\n\t\t\t\tpWapiStaInfo->PeerMacAddr[4], pWapiStaInfo->PeerMacAddr[5]);\n\n\t\t\tif (pWapiStaInfo == NULL) {\n\t\t\t\tWAPI_TRACE(WAPI_API, \" %s: pWapiStaInfo == NULL Case\\n\", __FUNCTION__);\n\t\t\t\treturn;\n\t\t\t}\n\n\t\t\tif (pWapiStaInfo->PeerMacAddr == NULL) {\n\t\t\t\tWAPI_TRACE(WAPI_API, \" %s: pWapiStaInfo->PeerMacAddr == NULL Case\\n\", __FUNCTION__);\n\t\t\t\treturn;\n\t\t\t}\n\n\t\t\tif (MacAddr == NULL) {\n\t\t\t\tWAPI_TRACE(WAPI_API, \" %s: MacAddr == NULL Case\\n\", __FUNCTION__);\n\t\t\t\treturn;\n\t\t\t}\n\n\t\t\tif (_rtw_memcmp(pWapiStaInfo->PeerMacAddr, MacAddr, ETH_ALEN) == _TRUE) {\n\t\t\t\tpWapiStaInfo->bAuthenticateInProgress = false;\n\t\t\t\tpWapiStaInfo->bSetkeyOk = false;\n\t\t\t\t_rtw_memset(pWapiStaInfo->PeerMacAddr, 0, ETH_ALEN);\n\t\t\t\tlist_del_init(&pWapiStaInfo->list);\n\t\t\t\tlist_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t}\n#endif\n\n\t\twhile (!list_empty(&(pWapiInfo->wapiSTAUsedList))) {\n\t\t\tpWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAUsedList.next, RT_WAPI_STA_INFO, list);\n\n\t\t\tRTW_INFO(\"peer Addr %02x-%02x-%02x-%02x-%02x-%02x\\n\", pWapiStaInfo->PeerMacAddr[0], pWapiStaInfo->PeerMacAddr[1], pWapiStaInfo->PeerMacAddr[2], pWapiStaInfo->PeerMacAddr[3],\n\t\t\t\tpWapiStaInfo->PeerMacAddr[4], pWapiStaInfo->PeerMacAddr[5]);\n\n\t\t\tlist_del_init(&pWapiStaInfo->list);\n\t\t\tmemset(pWapiStaInfo->PeerMacAddr, 0, ETH_ALEN);\n\t\t\tpWapiStaInfo->bSetkeyOk = 0;\n\t\t\tlist_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList);\n\t\t}\n\n\t}\n\n\tWAPI_TRACE(WAPI_API, \"<========== %s\\n\", __FUNCTION__);\n\treturn;\n}\n\nvoid rtw_wapi_return_all_sta_info(_adapter *padapter)\n{\n\tPRT_WAPI_T\t\t\t\tpWapiInfo;\n\tPRT_WAPI_STA_INFO\t\tpWapiStaInfo;\n\tPRT_WAPI_BKID\t\t\tpWapiBkid;\n\tWAPI_TRACE(WAPI_API, \"===========> %s\\n\", __FUNCTION__);\n\n\tpWapiInfo = &padapter->wapiInfo;\n\n\tif ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {\n\t\tWAPI_TRACE(WAPI_MLME, \"<========== %s, WAPI not supported or not enabled!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\t/* Sta Info List */\n\twhile (!list_empty(&(pWapiInfo->wapiSTAUsedList))) {\n\t\tpWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAUsedList.next, RT_WAPI_STA_INFO, list);\n\t\tlist_del_init(&pWapiStaInfo->list);\n\t\tmemset(pWapiStaInfo->PeerMacAddr, 0, ETH_ALEN);\n\t\tpWapiStaInfo->bSetkeyOk = 0;\n\t\tlist_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList);\n\t}\n\n\t/* BKID List */\n\twhile (!list_empty(&(pWapiInfo->wapiBKIDStoreList))) {\n\t\tpWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDStoreList.next, RT_WAPI_BKID, list);\n\t\tlist_del_init(&pWapiBkid->list);\n\t\tmemset(pWapiBkid->bkid, 0, 16);\n\t\tlist_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDIdleList);\n\t}\n\tWAPI_TRACE(WAPI_API, \"<========== %s\\n\", __FUNCTION__);\n}\n\nvoid CAM_empty_entry(\n\tPADAPTER\tAdapter,\n\tu8\t\t\tucIndex\n)\n{\n\trtw_hal_set_hwreg(Adapter, HW_VAR_CAM_EMPTY_ENTRY, (u8 *)(&ucIndex));\n}\n\nvoid rtw_wapi_clear_cam_entry(_adapter *padapter, u8 *pMacAddr)\n{\n\tu8 UcIndex = 0;\n\n\tWAPI_TRACE(WAPI_API, \"===========> %s\\n\", __FUNCTION__);\n\n\tif ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {\n\t\tWAPI_TRACE(WAPI_MLME, \"<========== %s, WAPI not supported or not enabled!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tUcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 0, 0);\n\tif (UcIndex != 0xff) {\n\t\t/* CAM_mark_invalid(Adapter, UcIndex); */\n\t\tCAM_empty_entry(padapter, UcIndex);\n\t}\n\n\tUcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 1, 0);\n\tif (UcIndex != 0xff) {\n\t\t/* CAM_mark_invalid(Adapter, UcIndex); */\n\t\tCAM_empty_entry(padapter, UcIndex);\n\t}\n\n\tUcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 0, 1);\n\tif (UcIndex != 0xff) {\n\t\t/* CAM_mark_invalid(Adapter, UcIndex); */\n\t\tCAM_empty_entry(padapter, UcIndex);\n\t}\n\n\tUcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 1, 1);\n\tif (UcIndex != 0xff) {\n\t\t/* CAM_mark_invalid(padapter, UcIndex); */\n\t\tCAM_empty_entry(padapter, UcIndex);\n\t}\n\n\tWAPI_TRACE(WAPI_API, \"<========== %s\\n\", __FUNCTION__);\n}\n\nvoid rtw_wapi_clear_all_cam_entry(_adapter *padapter)\n{\n\tWAPI_TRACE(WAPI_API, \"===========> %s\\n\", __FUNCTION__);\n\n\tif ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {\n\t\tWAPI_TRACE(WAPI_MLME, \"<========== %s, WAPI not supported or not enabled!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tinvalidate_cam_all(padapter); /* is this ok? */\n\tWapiResetAllCamEntry(padapter);\n\n\tWAPI_TRACE(WAPI_API, \"===========> %s\\n\", __FUNCTION__);\n}\n\nvoid rtw_wapi_set_key(_adapter *padapter, RT_WAPI_KEY *pWapiKey, RT_WAPI_STA_INFO *pWapiSta, u8 bGroupKey, u8 bUseDefaultKey)\n{\n\tPRT_WAPI_T\t\tpWapiInfo =  &padapter->wapiInfo;\n\tu8\t\t\t\t*pMacAddr = pWapiSta->PeerMacAddr;\n\tu32 EntryId = 0;\n\tBOOLEAN IsPairWise = false ;\n\tu8 EncAlgo;\n\n\tWAPI_TRACE(WAPI_API, \"===========> %s\\n\", __FUNCTION__);\n\n\tif ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {\n\t\tWAPI_TRACE(WAPI_API, \"<========== %s, WAPI not supported or not enabled!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tEncAlgo = _SMS4_;\n\n\t/* For Tx bc/mc pkt,use defualt key entry */\n\tif (bUseDefaultKey) {\n\t\t/* when WAPI update key, keyid will be 0 or 1 by turns. */\n\t\tif (pWapiKey->keyId == 0)\n\t\t\tEntryId = 0;\n\t\telse\n\t\t\tEntryId = 2;\n\t} else {\n\t\t/* tx/rx unicast pkt, or rx broadcast, find the key entry by peer's MacAddr */\n\t\tEntryId = WapiGetEntryForCamWrite(padapter, pMacAddr, pWapiKey->keyId, bGroupKey);\n\t}\n\n\tif (EntryId == 0xff) {\n\t\tWAPI_TRACE(WAPI_API, \"===>No entry for WAPI setkey! !!\\n\");\n\t\treturn;\n\t}\n\n\t/* EntryId is also used to diff Sec key and Mic key */\n\t/* Sec Key */\n\tWapiWriteOneCamEntry(padapter,\n\t\t\t     pMacAddr,\n\t\t\t     pWapiKey->keyId, /* keyid */\n\t\t\t     EntryId,\t/* entry */\n\t\t\t     EncAlgo, /* type */\n\t\t\t     bGroupKey, /* pairwise or group key */\n\t\t\t     pWapiKey->dataKey);\n\t/* MIC key */\n\tWapiWriteOneCamEntry(padapter,\n\t\t\t     pMacAddr,\n\t\t\t     pWapiKey->keyId, /* keyid */\n\t\t\t     EntryId + 1,\t/* entry */\n\t\t\t     EncAlgo, /* type */\n\t\t\t     bGroupKey, /* pairwise or group key */\n\t\t\t     pWapiKey->micKey);\n\n\tWAPI_TRACE(WAPI_API, \"Set Wapi Key :KeyId:%d,EntryId:%d,PairwiseKey:%d.\\n\", pWapiKey->keyId, EntryId, !bGroupKey);\n\tWAPI_TRACE(WAPI_API, \"===========> %s\\n\", __FUNCTION__);\n\n}\n\n#if 0\n/* YJ,test,091013 */\nvoid wapi_test_set_key(struct _adapter *padapter, u8 *buf)\n{\n\t/*Data: keyType(1) + bTxEnable(1) + bAuthenticator(1) + bUpdate(1) + PeerAddr(6) + DataKey(16) + MicKey(16) + KeyId(1)*/\n\tPRT_WAPI_T\t\t\tpWapiInfo = &padapter->wapiInfo;\n\tPRT_WAPI_BKID\t\tpWapiBkid;\n\tPRT_WAPI_STA_INFO\tpWapiSta;\n\tu8\t\t\t\t\tdata[43];\n\tbool\t\t\t\t\tbTxEnable;\n\tbool\t\t\t\t\tbUpdate;\n\tbool\t\t\t\t\tbAuthenticator;\n\tu8\t\t\t\t\tPeerAddr[6];\n\tu8\t\t\t\t\tWapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;\n\tu8\t\t\t\t\tWapiASUEPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;\n\tu8\t\t\t\t\tWapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;\n\n\tWAPI_TRACE(WAPI_INIT, \"===========>%s\\n\", __FUNCTION__);\n\n\tif (!padapter->WapiSupport)\n\t\treturn;\n\n\tcopy_from_user(data, buf, 43);\n\tbTxEnable = data[1];\n\tbAuthenticator = data[2];\n\tbUpdate = data[3];\n\tmemcpy(PeerAddr, data + 4, 6);\n\n\tif (data[0] == 0x3) {\n\t\tif (!list_empty(&(pWapiInfo->wapiBKIDIdleList))) {\n\t\t\tpWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDIdleList.next, RT_WAPI_BKID, list);\n\t\t\tlist_del_init(&pWapiBkid->list);\n\t\t\tmemcpy(pWapiBkid->bkid, data + 10, 16);\n\t\t\tWAPI_DATA(WAPI_INIT, \"SetKey - BKID\", pWapiBkid->bkid, 16);\n\t\t\tlist_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDStoreList);\n\t\t}\n\t} else {\n\t\tlist_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {\n\t\t\tif (!memcmp(pWapiSta->PeerMacAddr, PeerAddr, 6)) {\n\t\t\t\tpWapiSta->bAuthenticatorInUpdata = false;\n\t\t\t\tswitch (data[0]) {\n\t\t\t\tcase 1:              /* usk */\n\t\t\t\t\tif (bAuthenticator) {       /* authenticator */\n\t\t\t\t\t\tmemcpy(pWapiSta->lastTxUnicastPN, WapiAEPNInitialValueSrc, 16);\n\t\t\t\t\t\tif (!bUpdate) {    /* first */\n\t\t\t\t\t\t\tWAPI_TRACE(WAPI_INIT, \"AE fisrt set usk\\n\");\n\t\t\t\t\t\t\tpWapiSta->wapiUsk.bSet = true;\n\t\t\t\t\t\t\tmemcpy(pWapiSta->wapiUsk.dataKey, data + 10, 16);\n\t\t\t\t\t\t\tmemcpy(pWapiSta->wapiUsk.micKey, data + 26, 16);\n\t\t\t\t\t\t\tpWapiSta->wapiUsk.keyId = *(data + 42);\n\t\t\t\t\t\t\tpWapiSta->wapiUsk.bTxEnable = true;\n\t\t\t\t\t\t\tWAPI_DATA(WAPI_INIT, \"SetKey - AE USK Data Key\", pWapiSta->wapiUsk.dataKey, 16);\n\t\t\t\t\t\t\tWAPI_DATA(WAPI_INIT, \"SetKey - AE USK Mic Key\", pWapiSta->wapiUsk.micKey, 16);\n\t\t\t\t\t\t} else {           /* update */\n\t\t\t\t\t\t\tWAPI_TRACE(WAPI_INIT, \"AE update usk\\n\");\n\t\t\t\t\t\t\tpWapiSta->wapiUskUpdate.bSet = true;\n\t\t\t\t\t\t\tpWapiSta->bAuthenticatorInUpdata = true;\n\t\t\t\t\t\t\tmemcpy(pWapiSta->wapiUskUpdate.dataKey, data + 10, 16);\n\t\t\t\t\t\t\tmemcpy(pWapiSta->wapiUskUpdate.micKey, data + 26, 16);\n\t\t\t\t\t\t\tmemcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiASUEPNInitialValueSrc, 16);\n\t\t\t\t\t\t\tmemcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiASUEPNInitialValueSrc, 16);\n\t\t\t\t\t\t\tmemcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiASUEPNInitialValueSrc, 16);\n\t\t\t\t\t\t\tmemcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiASUEPNInitialValueSrc, 16);\n\t\t\t\t\t\t\tmemcpy(pWapiSta->lastRxUnicastPN, WapiASUEPNInitialValueSrc, 16);\n\t\t\t\t\t\t\tpWapiSta->wapiUskUpdate.keyId = *(data + 42);\n\t\t\t\t\t\t\tpWapiSta->wapiUskUpdate.bTxEnable = true;\n\t\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\tif (!bUpdate) {\n\t\t\t\t\t\t\tWAPI_TRACE(WAPI_INIT, \"ASUE fisrt set usk\\n\");\n\t\t\t\t\t\t\tif (bTxEnable) {\n\t\t\t\t\t\t\t\tpWapiSta->wapiUsk.bTxEnable = true;\n\t\t\t\t\t\t\t\tmemcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16);\n\t\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t\tpWapiSta->wapiUsk.bSet = true;\n\t\t\t\t\t\t\t\tmemcpy(pWapiSta->wapiUsk.dataKey, data + 10, 16);\n\t\t\t\t\t\t\t\tmemcpy(pWapiSta->wapiUsk.micKey, data + 26, 16);\n\t\t\t\t\t\t\t\tpWapiSta->wapiUsk.keyId = *(data + 42);\n\t\t\t\t\t\t\t\tpWapiSta->wapiUsk.bTxEnable = false;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tWAPI_TRACE(WAPI_INIT, \"ASUE update usk\\n\");\n\t\t\t\t\t\t\tif (bTxEnable) {\n\t\t\t\t\t\t\t\tpWapiSta->wapiUskUpdate.bTxEnable = true;\n\t\t\t\t\t\t\t\tif (pWapiSta->wapiUskUpdate.bSet) {\n\t\t\t\t\t\t\t\t\tmemcpy(pWapiSta->wapiUsk.dataKey, pWapiSta->wapiUskUpdate.dataKey, 16);\n\t\t\t\t\t\t\t\t\tmemcpy(pWapiSta->wapiUsk.micKey, pWapiSta->wapiUskUpdate.micKey, 16);\n\t\t\t\t\t\t\t\t\tpWapiSta->wapiUsk.keyId = pWapiSta->wapiUskUpdate.keyId;\n\t\t\t\t\t\t\t\t\tmemcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiASUEPNInitialValueSrc, 16);\n\t\t\t\t\t\t\t\t\tmemcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiASUEPNInitialValueSrc, 16);\n\t\t\t\t\t\t\t\t\tmemcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiASUEPNInitialValueSrc, 16);\n\t\t\t\t\t\t\t\t\tmemcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiASUEPNInitialValueSrc, 16);\n\t\t\t\t\t\t\t\t\tmemcpy(pWapiSta->lastRxUnicastPN, WapiASUEPNInitialValueSrc, 16);\n\t\t\t\t\t\t\t\t\tpWapiSta->wapiUskUpdate.bTxEnable = false;\n\t\t\t\t\t\t\t\t\tpWapiSta->wapiUskUpdate.bSet = false;\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\tmemcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16);\n\t\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t\tpWapiSta->wapiUskUpdate.bSet = true;\n\t\t\t\t\t\t\t\tmemcpy(pWapiSta->wapiUskUpdate.dataKey, data + 10, 16);\n\t\t\t\t\t\t\t\tmemcpy(pWapiSta->wapiUskUpdate.micKey, data + 26, 16);\n\t\t\t\t\t\t\t\tpWapiSta->wapiUskUpdate.keyId = *(data + 42);\n\t\t\t\t\t\t\t\tpWapiSta->wapiUskUpdate.bTxEnable = false;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\tcase 2:\t\t/* msk */\n\t\t\t\t\tif (bAuthenticator) {        /* authenticator */\n\t\t\t\t\t\tpWapiInfo->wapiTxMsk.bSet = true;\n\t\t\t\t\t\tmemcpy(pWapiInfo->wapiTxMsk.dataKey, data + 10, 16);\n\t\t\t\t\t\tmemcpy(pWapiInfo->wapiTxMsk.micKey, data + 26, 16);\n\t\t\t\t\t\tpWapiInfo->wapiTxMsk.keyId = *(data + 42);\n\t\t\t\t\t\tpWapiInfo->wapiTxMsk.bTxEnable = true;\n\t\t\t\t\t\tmemcpy(pWapiInfo->lastTxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16);\n\n\t\t\t\t\t\tif (!bUpdate) {    /* first */\n\t\t\t\t\t\t\tWAPI_TRACE(WAPI_INIT, \"AE fisrt set msk\\n\");\n\t\t\t\t\t\t\tif (!pWapiSta->bSetkeyOk)\n\t\t\t\t\t\t\t\tpWapiSta->bSetkeyOk = true;\n\t\t\t\t\t\t\tpWapiInfo->bFirstAuthentiateInProgress = false;\n\t\t\t\t\t\t} else                /* update */\n\t\t\t\t\t\t\tWAPI_TRACE(WAPI_INIT, \"AE update msk\\n\");\n\n\t\t\t\t\t\tWAPI_DATA(WAPI_INIT, \"SetKey - AE MSK Data Key\", pWapiInfo->wapiTxMsk.dataKey, 16);\n\t\t\t\t\t\tWAPI_DATA(WAPI_INIT, \"SetKey - AE MSK Mic Key\", pWapiInfo->wapiTxMsk.micKey, 16);\n\t\t\t\t\t} else {\n\t\t\t\t\t\tif (!bUpdate) {\n\t\t\t\t\t\t\tWAPI_TRACE(WAPI_INIT, \"ASUE fisrt set msk\\n\");\n\t\t\t\t\t\t\tpWapiSta->wapiMsk.bSet = true;\n\t\t\t\t\t\t\tmemcpy(pWapiSta->wapiMsk.dataKey, data + 10, 16);\n\t\t\t\t\t\t\tmemcpy(pWapiSta->wapiMsk.micKey, data + 26, 16);\n\t\t\t\t\t\t\tpWapiSta->wapiMsk.keyId = *(data + 42);\n\t\t\t\t\t\t\tpWapiSta->wapiMsk.bTxEnable = false;\n\t\t\t\t\t\t\tif (!pWapiSta->bSetkeyOk)\n\t\t\t\t\t\t\t\tpWapiSta->bSetkeyOk = true;\n\t\t\t\t\t\t\tpWapiInfo->bFirstAuthentiateInProgress = false;\n\t\t\t\t\t\t\tWAPI_DATA(WAPI_INIT, \"SetKey - ASUE MSK Data Key\", pWapiSta->wapiMsk.dataKey, 16);\n\t\t\t\t\t\t\tWAPI_DATA(WAPI_INIT, \"SetKey - ASUE MSK Mic Key\", pWapiSta->wapiMsk.micKey, 16);\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tWAPI_TRACE(WAPI_INIT, \"ASUE update msk\\n\");\n\t\t\t\t\t\t\tpWapiSta->wapiMskUpdate.bSet = true;\n\t\t\t\t\t\t\tmemcpy(pWapiSta->wapiMskUpdate.dataKey, data + 10, 16);\n\t\t\t\t\t\t\tmemcpy(pWapiSta->wapiMskUpdate.micKey, data + 26, 16);\n\t\t\t\t\t\t\tpWapiSta->wapiMskUpdate.keyId = *(data + 42);\n\t\t\t\t\t\t\tpWapiSta->wapiMskUpdate.bTxEnable = false;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tWAPI_TRACE(WAPI_ERR, \"Unknown Flag\\n\");\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\tWAPI_TRACE(WAPI_INIT, \"<===========%s\\n\", __FUNCTION__);\n}\n\n\nvoid wapi_test_init(struct _adapter *padapter)\n{\n\tu8 keybuf[100];\n\tu8 mac_addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x72, 0x04, 0x70};\n\tu8 UskDataKey[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f};\n\tu8 UskMicKey[16] = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f};\n\tu8 UskId = 0;\n\tu8 MskDataKey[16] = {0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f};\n\tu8 MskMicKey[16] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f};\n\tu8 MskId = 0;\n\n\tWAPI_TRACE(WAPI_INIT, \"===========>%s\\n\", __FUNCTION__);\n\n\t/* Enable Wapi */\n\tWAPI_TRACE(WAPI_INIT, \"%s: Enable wapi!!!!\\n\", __FUNCTION__);\n\tpadapter->wapiInfo.bWapiEnable = true;\n\tpadapter->pairwise_key_type = KEY_TYPE_SMS4;\n\tieee->group_key_type = KEY_TYPE_SMS4;\n\tpadapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN;\n\tpadapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN;\n\n\t/* set usk */\n\tWAPI_TRACE(WAPI_INIT, \"%s: Set USK!!!!\\n\", __FUNCTION__);\n\tmemset(keybuf, 0, 100);\n\tkeybuf[0] = 1;                           /* set usk */\n\tkeybuf[1] = 1; \t\t\t\t/* enable tx */\n\tkeybuf[2] = 1; \t\t\t\t/* AE */\n\tkeybuf[3] = 0; \t\t\t\t/* not update */\n\n\tmemcpy(keybuf + 4, mac_addr, ETH_ALEN);\n\tmemcpy(keybuf + 10, UskDataKey, 16);\n\tmemcpy(keybuf + 26, UskMicKey, 16);\n\tkeybuf[42] = UskId;\n\twapi_test_set_key(padapter, keybuf);\n\n\tmemset(keybuf, 0, 100);\n\tkeybuf[0] = 1;                           /* set usk */\n\tkeybuf[1] = 1; \t\t\t\t/* enable tx */\n\tkeybuf[2] = 0; \t\t\t\t/* AE */\n\tkeybuf[3] = 0; \t\t\t\t/* not update */\n\n\tmemcpy(keybuf + 4, mac_addr, ETH_ALEN);\n\tmemcpy(keybuf + 10, UskDataKey, 16);\n\tmemcpy(keybuf + 26, UskMicKey, 16);\n\tkeybuf[42] = UskId;\n\twapi_test_set_key(padapter, keybuf);\n\n\t/* set msk */\n\tWAPI_TRACE(WAPI_INIT, \"%s: Set MSK!!!!\\n\", __FUNCTION__);\n\tmemset(keybuf, 0, 100);\n\tkeybuf[0] = 2;                                /* set msk */\n\tkeybuf[1] = 1;                               /* Enable TX */\n\tkeybuf[2] = 1; \t\t\t\t/* AE */\n\tkeybuf[3] = 0;                              /* not update */\n\tmemcpy(keybuf + 4, mac_addr, ETH_ALEN);\n\tmemcpy(keybuf + 10, MskDataKey, 16);\n\tmemcpy(keybuf + 26, MskMicKey, 16);\n\tkeybuf[42] = MskId;\n\twapi_test_set_key(padapter, keybuf);\n\n\tmemset(keybuf, 0, 100);\n\tkeybuf[0] = 2;                                /* set msk */\n\tkeybuf[1] = 1;                               /* Enable TX */\n\tkeybuf[2] = 0; \t\t\t\t/* AE */\n\tkeybuf[3] = 0;                              /* not update */\n\tmemcpy(keybuf + 4, mac_addr, ETH_ALEN);\n\tmemcpy(keybuf + 10, MskDataKey, 16);\n\tmemcpy(keybuf + 26, MskMicKey, 16);\n\tkeybuf[42] = MskId;\n\twapi_test_set_key(padapter, keybuf);\n\tWAPI_TRACE(WAPI_INIT, \"<===========%s\\n\", __FUNCTION__);\n}\n#endif\n\nvoid rtw_wapi_get_iv(_adapter *padapter, u8 *pRA, u8 *IV)\n{\n\tPWLAN_HEADER_WAPI_EXTENSION pWapiExt = NULL;\n\tPRT_WAPI_T         pWapiInfo = &padapter->wapiInfo;\n\tbool\tbPNOverflow = false;\n\tbool\tbFindMatchPeer = false;\n\tPRT_WAPI_STA_INFO  pWapiSta = NULL;\n\n\tpWapiExt = (PWLAN_HEADER_WAPI_EXTENSION)IV;\n\n\tWAPI_DATA(WAPI_RX, \"wapi_get_iv: pra\", pRA, 6);\n\n\tif (IS_MCAST(pRA)) {\n\t\tif (!pWapiInfo->wapiTxMsk.bTxEnable) {\n\t\t\tWAPI_TRACE(WAPI_ERR, \"%s: bTxEnable = 0!!\\n\", __FUNCTION__);\n\t\t\treturn;\n\t\t}\n\n\t\tif (pWapiInfo->wapiTxMsk.keyId <= 1) {\n\t\t\tpWapiExt->KeyIdx = pWapiInfo->wapiTxMsk.keyId;\n\t\t\tpWapiExt->Reserved = 0;\n\t\t\tbPNOverflow = WapiIncreasePN(pWapiInfo->lastTxMulticastPN, 1);\n\t\t\tmemcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16);\n\t\t}\n\t} else {\n\t\tif (list_empty(&pWapiInfo->wapiSTAUsedList)) {\n\t\t\tWAPI_TRACE(WAPI_RX, \"rtw_wapi_get_iv: list is empty\\n\");\n\t\t\t_rtw_memset(IV, 10, 18);\n\t\t\treturn;\n\t\t} else {\n\t\t\tlist_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {\n\t\t\t\tWAPI_DATA(WAPI_RX, \"rtw_wapi_get_iv: peermacaddr \", pWapiSta->PeerMacAddr, 6);\n\t\t\t\tif (_rtw_memcmp((u8 *)pWapiSta->PeerMacAddr, pRA, 6) == _TRUE) {\n\t\t\t\t\tbFindMatchPeer = true;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tWAPI_TRACE(WAPI_RX, \"bFindMatchPeer: %d\\n\", bFindMatchPeer);\n\t\t\tWAPI_DATA(WAPI_RX, \"Addr\", pRA, 6);\n\n\t\t\tif (bFindMatchPeer) {\n\t\t\t\tif ((!pWapiSta->wapiUskUpdate.bTxEnable) && (!pWapiSta->wapiUsk.bTxEnable))\n\t\t\t\t\treturn;\n\n\t\t\t\tif (pWapiSta->wapiUsk.keyId <= 1) {\n\t\t\t\t\tif (pWapiSta->wapiUskUpdate.bTxEnable)\n\t\t\t\t\t\tpWapiExt->KeyIdx = pWapiSta->wapiUskUpdate.keyId;\n\t\t\t\t\telse\n\t\t\t\t\t\tpWapiExt->KeyIdx = pWapiSta->wapiUsk.keyId;\n\n\t\t\t\t\tpWapiExt->Reserved = 0;\n\t\t\t\t\tbPNOverflow = WapiIncreasePN(pWapiSta->lastTxUnicastPN, 2);\n\t\t\t\t\t_rtw_memcpy(pWapiExt->PN, pWapiSta->lastTxUnicastPN, 16);\n\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t}\n\n}\n\nbool rtw_wapi_drop_for_key_absent(_adapter *padapter, u8 *pRA)\n{\n\tPRT_WAPI_T         pWapiInfo = &padapter->wapiInfo;\n\tbool\t\t\t\tbFindMatchPeer = false;\n\tbool\t\t\t\tbDrop = false;\n\tPRT_WAPI_STA_INFO  pWapiSta = NULL;\n\tstruct security_priv\t\t*psecuritypriv = &padapter->securitypriv;\n\n\tWAPI_DATA(WAPI_RX, \"rtw_wapi_drop_for_key_absent: ra \", pRA, 6);\n\n\tif (psecuritypriv->dot11PrivacyAlgrthm == _SMS4_) {\n\t\tif ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable))\n\t\t\treturn true;\n\n\t\tif (IS_MCAST(pRA)) {\n\t\t\tif (!pWapiInfo->wapiTxMsk.bTxEnable) {\n\t\t\t\tbDrop = true;\n\t\t\t\tWAPI_TRACE(WAPI_RX, \"rtw_wapi_drop_for_key_absent: multicast key is absent\\n\");\n\t\t\t\treturn bDrop;\n\t\t\t}\n\t\t} else {\n\t\t\tif (!list_empty(&pWapiInfo->wapiSTAUsedList)) {\n\t\t\t\tlist_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {\n\t\t\t\t\tWAPI_DATA(WAPI_RX, \"rtw_wapi_drop_for_key_absent: pWapiSta->PeerMacAddr \", pWapiSta->PeerMacAddr, 6);\n\t\t\t\t\tif (_rtw_memcmp(pRA, pWapiSta->PeerMacAddr, 6) == _TRUE) {\n\t\t\t\t\t\tbFindMatchPeer = true;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif (bFindMatchPeer)\t{\n\t\t\t\t\tif (!pWapiSta->wapiUsk.bTxEnable) {\n\t\t\t\t\t\tbDrop = true;\n\t\t\t\t\t\tWAPI_TRACE(WAPI_RX, \"rtw_wapi_drop_for_key_absent: unicast key is absent\\n\");\n\t\t\t\t\t\treturn bDrop;\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tbDrop = true;\n\t\t\t\t\tWAPI_TRACE(WAPI_RX, \"rtw_wapi_drop_for_key_absent: no peer find\\n\");\n\t\t\t\t\treturn bDrop;\n\t\t\t\t}\n\n\t\t\t} else {\n\t\t\t\tbDrop = true;\n\t\t\t\tWAPI_TRACE(WAPI_RX, \"rtw_wapi_drop_for_key_absent: no sta  exist\\n\");\n\t\t\t\treturn bDrop;\n\t\t\t}\n\t\t}\n\t} else\n\t\treturn bDrop;\n\n\treturn bDrop;\n}\n\nvoid rtw_wapi_set_set_encryption(_adapter *padapter, struct ieee_param *param)\n{\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tPRT_WAPI_T\t\t\tpWapiInfo = &padapter->wapiInfo;\n\tPRT_WAPI_STA_INFO\tpWapiSta;\n\tu8\t\t\t\t\tWapiASUEPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;\n\tu8\t\t\t\t\tWapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;\n\tu8\t\t\t\t\tWapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;\n\n\tif (param->u.crypt.set_tx == 1) {\n\t\tlist_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {\n\t\t\tif (_rtw_memcmp(pWapiSta->PeerMacAddr, param->sta_addr, 6)) {\n\t\t\t\t_rtw_memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16);\n\n\t\t\t\tpWapiSta->wapiUsk.bSet = true;\n\t\t\t\t_rtw_memcpy(pWapiSta->wapiUsk.dataKey, param->u.crypt.key, 16);\n\t\t\t\t_rtw_memcpy(pWapiSta->wapiUsk.micKey, param->u.crypt.key + 16, 16);\n\t\t\t\tpWapiSta->wapiUsk.keyId = param->u.crypt.idx ;\n\t\t\t\tpWapiSta->wapiUsk.bTxEnable = true;\n\n\t\t\t\t_rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiAEPNInitialValueSrc, 16);\n\t\t\t\t_rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiAEPNInitialValueSrc, 16);\n\t\t\t\t_rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiAEPNInitialValueSrc, 16);\n\t\t\t\t_rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiAEPNInitialValueSrc, 16);\n\t\t\t\t_rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiAEPNInitialValueSrc, 16);\n\t\t\t\tpWapiSta->wapiUskUpdate.bTxEnable = false;\n\t\t\t\tpWapiSta->wapiUskUpdate.bSet = false;\n\n\t\t\t\tif (psecuritypriv->sw_encrypt == false || psecuritypriv->sw_decrypt == false) {\n\t\t\t\t\t/* set unicast key for ASUE */\n\t\t\t\t\trtw_wapi_set_key(padapter, &pWapiSta->wapiUsk, pWapiSta, false, false);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else {\n\t\tlist_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {\n\t\t\tif (_rtw_memcmp(pWapiSta->PeerMacAddr, get_bssid(pmlmepriv), 6)) {\n\t\t\t\tpWapiSta->wapiMsk.bSet = true;\n\t\t\t\t_rtw_memcpy(pWapiSta->wapiMsk.dataKey, param->u.crypt.key, 16);\n\t\t\t\t_rtw_memcpy(pWapiSta->wapiMsk.micKey, param->u.crypt.key + 16, 16);\n\t\t\t\tpWapiSta->wapiMsk.keyId = param->u.crypt.idx ;\n\t\t\t\tpWapiSta->wapiMsk.bTxEnable = false;\n\t\t\t\tif (!pWapiSta->bSetkeyOk)\n\t\t\t\t\tpWapiSta->bSetkeyOk = true;\n\t\t\t\tpWapiSta->bAuthenticateInProgress = false;\n\n\t\t\t\t_rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16);\n\n\t\t\t\tif (psecuritypriv->sw_decrypt == false) {\n\t\t\t\t\t/* set rx broadcast key for ASUE */\n\t\t\t\t\trtw_wapi_set_key(padapter, &pWapiSta->wapiMsk, pWapiSta, true, false);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n#endif\n"
  },
  {
    "path": "core/rtw_wapi_sms4.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifdef CONFIG_WAPI_SUPPORT\n\n#include <linux/unistd.h>\n#include <linux/etherdevice.h>\n#include <drv_types.h>\n#include <rtw_wapi.h>\n\n\n#ifdef CONFIG_WAPI_SW_SMS4\n\n#define WAPI_LITTLE_ENDIAN\n/* #define BIG_ENDIAN */\n#define ENCRYPT  0\n#define DECRYPT  1\n\n\n/**********************************************************\n **********************************************************/\nconst u8 Sbox[256] = {\n\t0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7, 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,\n\t0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3, 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,\n\t0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a, 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,\n\t0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95, 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,\n\t0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba, 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,\n\t0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b, 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,\n\t0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2, 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,\n\t0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52, 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,\n\t0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5, 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,\n\t0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55, 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,\n\t0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60, 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,\n\t0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f, 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,\n\t0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f, 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,\n\t0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd, 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,\n\t0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e, 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,\n\t0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20, 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48\n};\n\nconst u32 CK[32] = {\n\t0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269,\n\t0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9,\n\t0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249,\n\t0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9,\n\t0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229,\n\t0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299,\n\t0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209,\n\t0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279\n};\n\n#define Rotl(_x, _y) (((_x) << (_y)) | ((_x) >> (32 - (_y))))\n\n#define ByteSub(_A) (Sbox[(_A) >> 24 & 0xFF] << 24 | \\\n\t\t     Sbox[(_A) >> 16 & 0xFF] << 16 | \\\n\t\t     Sbox[(_A) >>  8 & 0xFF] <<  8 | \\\n\t\t     Sbox[(_A) & 0xFF])\n\n#define L1(_B) ((_B) ^ Rotl(_B, 2) ^ Rotl(_B, 10) ^ Rotl(_B, 18) ^ Rotl(_B, 24))\n#define L2(_B) ((_B) ^ Rotl(_B, 13) ^ Rotl(_B, 23))\n\nstatic void\nxor_block(void *dst, void *src1, void *src2)\n/* 128-bit xor: *dst = *src1 xor *src2. Pointers must be 32-bit aligned */\n{\n\t((u32 *)dst)[0] = ((u32 *)src1)[0] ^ ((u32 *)src2)[0];\n\t((u32 *)dst)[1] = ((u32 *)src1)[1] ^ ((u32 *)src2)[1];\n\t((u32 *)dst)[2] = ((u32 *)src1)[2] ^ ((u32 *)src2)[2];\n\t((u32 *)dst)[3] = ((u32 *)src1)[3] ^ ((u32 *)src2)[3];\n}\n\n\nvoid SMS4Crypt(u8 *Input, u8 *Output, u32 *rk)\n{\n\tu32 r, mid, x0, x1, x2, x3, *p;\n\tp = (u32 *)Input;\n\tx0 = p[0];\n\tx1 = p[1];\n\tx2 = p[2];\n\tx3 = p[3];\n#ifdef WAPI_LITTLE_ENDIAN\n\tx0 = Rotl(x0, 16);\n\tx0 = ((x0 & 0x00FF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);\n\tx1 = Rotl(x1, 16);\n\tx1 = ((x1 & 0x00FF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);\n\tx2 = Rotl(x2, 16);\n\tx2 = ((x2 & 0x00FF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);\n\tx3 = Rotl(x3, 16);\n\tx3 = ((x3 & 0x00FF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);\n#endif\n\tfor (r = 0; r < 32; r += 4) {\n\t\tmid = x1 ^ x2 ^ x3 ^ rk[r + 0];\n\t\tmid = ByteSub(mid);\n\t\tx0 ^= L1(mid);\n\t\tmid = x2 ^ x3 ^ x0 ^ rk[r + 1];\n\t\tmid = ByteSub(mid);\n\t\tx1 ^= L1(mid);\n\t\tmid = x3 ^ x0 ^ x1 ^ rk[r + 2];\n\t\tmid = ByteSub(mid);\n\t\tx2 ^= L1(mid);\n\t\tmid = x0 ^ x1 ^ x2 ^ rk[r + 3];\n\t\tmid = ByteSub(mid);\n\t\tx3 ^= L1(mid);\n\t}\n#ifdef WAPI_LITTLE_ENDIAN\n\tx0 = Rotl(x0, 16);\n\tx0 = ((x0 & 0x00FF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);\n\tx1 = Rotl(x1, 16);\n\tx1 = ((x1 & 0x00FF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);\n\tx2 = Rotl(x2, 16);\n\tx2 = ((x2 & 0x00FF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);\n\tx3 = Rotl(x3, 16);\n\tx3 = ((x3 & 0x00FF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);\n#endif\n\tp = (u32 *)Output;\n\tp[0] = x3;\n\tp[1] = x2;\n\tp[2] = x1;\n\tp[3] = x0;\n}\n\n\n\nvoid SMS4KeyExt(u8 *Key, u32 *rk, u32 CryptFlag)\n{\n\tu32 r, mid, x0, x1, x2, x3, *p;\n\n\tp = (u32 *)Key;\n\tx0 = p[0];\n\tx1 = p[1];\n\tx2 = p[2];\n\tx3 = p[3];\n#ifdef WAPI_LITTLE_ENDIAN\n\tx0 = Rotl(x0, 16);\n\tx0 = ((x0 & 0xFF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);\n\tx1 = Rotl(x1, 16);\n\tx1 = ((x1 & 0xFF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);\n\tx2 = Rotl(x2, 16);\n\tx2 = ((x2 & 0xFF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);\n\tx3 = Rotl(x3, 16);\n\tx3 = ((x3 & 0xFF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);\n#endif\n\n\tx0 ^= 0xa3b1bac6;\n\tx1 ^= 0x56aa3350;\n\tx2 ^= 0x677d9197;\n\tx3 ^= 0xb27022dc;\n\tfor (r = 0; r < 32; r += 4) {\n\t\tmid = x1 ^ x2 ^ x3 ^ CK[r + 0];\n\t\tmid = ByteSub(mid);\n\t\trk[r + 0] = x0 ^= L2(mid);\n\t\tmid = x2 ^ x3 ^ x0 ^ CK[r + 1];\n\t\tmid = ByteSub(mid);\n\t\trk[r + 1] = x1 ^= L2(mid);\n\t\tmid = x3 ^ x0 ^ x1 ^ CK[r + 2];\n\t\tmid = ByteSub(mid);\n\t\trk[r + 2] = x2 ^= L2(mid);\n\t\tmid = x0 ^ x1 ^ x2 ^ CK[r + 3];\n\t\tmid = ByteSub(mid);\n\t\trk[r + 3] = x3 ^= L2(mid);\n\t}\n\tif (CryptFlag == DECRYPT) {\n\t\tfor (r = 0; r < 16; r++)\n\t\t\tmid = rk[r], rk[r] = rk[31 - r], rk[31 - r] = mid;\n\t}\n}\n\n\nvoid WapiSMS4Cryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,\n\t\t      u8 *Output, u16 *OutputLength, u32 CryptFlag)\n{\n\tu32 blockNum, i, j, rk[32];\n\tu16 remainder;\n\tu8 blockIn[16], blockOut[16], tempIV[16], k;\n\n\t*OutputLength = 0;\n\tremainder = InputLength & 0x0F;\n\tblockNum = InputLength >> 4;\n\tif (remainder != 0)\n\t\tblockNum++;\n\telse\n\t\tremainder = 16;\n\n\tfor (k = 0; k < 16; k++)\n\t\ttempIV[k] = IV[15 - k];\n\n\tmemcpy(blockIn, tempIV, 16);\n\n\tSMS4KeyExt((u8 *)Key, rk, CryptFlag);\n\n\tfor (i = 0; i < blockNum - 1; i++) {\n\t\tSMS4Crypt((u8 *)blockIn, blockOut, rk);\n\t\txor_block(&Output[i * 16], &Input[i * 16], blockOut);\n\t\tmemcpy(blockIn, blockOut, 16);\n\t}\n\n\t*OutputLength = i * 16;\n\n\tSMS4Crypt((u8 *)blockIn, blockOut, rk);\n\n\tfor (j = 0; j < remainder; j++)\n\t\tOutput[i * 16 + j] = Input[i * 16 + j] ^ blockOut[j];\n\t*OutputLength += remainder;\n\n}\n\nvoid WapiSMS4Encryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,\n\t\t\tu8 *Output, u16 *OutputLength)\n{\n\n\tWapiSMS4Cryption(Key, IV, Input, InputLength, Output, OutputLength, ENCRYPT);\n}\n\nvoid WapiSMS4Decryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,\n\t\t\tu8 *Output, u16 *OutputLength)\n{\n\t/* OFB mode: is also ENCRYPT flag */\n\tWapiSMS4Cryption(Key, IV, Input, InputLength, Output, OutputLength, ENCRYPT);\n}\n\nvoid WapiSMS4CalculateMic(u8 *Key, u8 *IV, u8 *Input1, u8 Input1Length,\n\t\t  u8 *Input2, u16 Input2Length, u8 *Output, u8 *OutputLength)\n{\n\tu32 blockNum, i, remainder, rk[32];\n\tu8 BlockIn[16], BlockOut[16], TempBlock[16], tempIV[16], k;\n\n\t*OutputLength = 0;\n\tremainder = Input1Length & 0x0F;\n\tblockNum = Input1Length >> 4;\n\n\tfor (k = 0; k < 16; k++)\n\t\ttempIV[k] = IV[15 - k];\n\n\tmemcpy(BlockIn, tempIV, 16);\n\n\tSMS4KeyExt((u8 *)Key, rk, ENCRYPT);\n\n\tSMS4Crypt((u8 *)BlockIn, BlockOut, rk);\n\n\tfor (i = 0; i < blockNum; i++) {\n\t\txor_block(BlockIn, (Input1 + i * 16), BlockOut);\n\t\tSMS4Crypt((u8 *)BlockIn, BlockOut, rk);\n\t}\n\n\tif (remainder != 0) {\n\t\tmemset(TempBlock, 0, 16);\n\t\tmemcpy(TempBlock, (Input1 + blockNum * 16), remainder);\n\n\t\txor_block(BlockIn, TempBlock, BlockOut);\n\t\tSMS4Crypt((u8 *)BlockIn, BlockOut, rk);\n\t}\n\n\tremainder = Input2Length & 0x0F;\n\tblockNum = Input2Length >> 4;\n\n\tfor (i = 0; i < blockNum; i++) {\n\t\txor_block(BlockIn, (Input2 + i * 16), BlockOut);\n\t\tSMS4Crypt((u8 *)BlockIn, BlockOut, rk);\n\t}\n\n\tif (remainder != 0) {\n\t\tmemset(TempBlock, 0, 16);\n\t\tmemcpy(TempBlock, (Input2 + blockNum * 16), remainder);\n\n\t\txor_block(BlockIn, TempBlock, BlockOut);\n\t\tSMS4Crypt((u8 *)BlockIn, BlockOut, rk);\n\t}\n\n\tmemcpy(Output, BlockOut, 16);\n\t*OutputLength = 16;\n}\n\nvoid SecCalculateMicSMS4(\n\tu8\t\tKeyIdx,\n\tu8        *MicKey,\n\tu8        *pHeader,\n\tu8        *pData,\n\tu16       DataLen,\n\tu8        *MicBuffer\n)\n{\n#if 0\n\tstruct ieee80211_hdr_3addr_qos *header;\n\tu8 TempBuf[34], TempLen = 32, MicLen, QosOffset, *IV;\n\tu16 *pTemp, fc;\n\n\tWAPI_TRACE(WAPI_TX | WAPI_RX, \"=========>%s\\n\", __FUNCTION__);\n\n\theader = (struct ieee80211_hdr_3addr_qos *)pHeader;\n\tmemset(TempBuf, 0, 34);\n\tmemcpy(TempBuf, pHeader, 2); /* FrameCtrl */\n\tpTemp = (u16 *)TempBuf;\n\t*pTemp &= 0xc78f;       /* bit4,5,6,11,12,13 */\n\n\tmemcpy((TempBuf + 2), (pHeader + 4), 12); /* Addr1, Addr2 */\n\tmemcpy((TempBuf + 14), (pHeader + 22), 2); /* SeqCtrl */\n\tpTemp = (u16 *)(TempBuf + 14);\n\t*pTemp &= 0x000f;\n\n\tmemcpy((TempBuf + 16), (pHeader + 16), 6); /* Addr3 */\n\n\tfc = le16_to_cpu(header->frame_ctl);\n\n\n\n\tif (GetFrDs((u16 *)&fc) && GetToDs((u16 *)&fc)) {\n\t\tmemcpy((TempBuf + 22), (pHeader + 24), 6);\n\t\tQosOffset = 30;\n\t} else {\n\t\tmemset((TempBuf + 22), 0, 6);\n\t\tQosOffset = 24;\n\t}\n\n\tif ((fc & 0x0088) == 0x0088) {\n\t\tmemcpy((TempBuf + 28), (pHeader + QosOffset), 2);\n\t\tTempLen += 2;\n\t\t/* IV = pHeader + QosOffset + 2 + SNAP_SIZE + sizeof(u16) + 2; */\n\t\tIV = pHeader + QosOffset + 2 + 2;\n\t} else {\n\t\tIV = pHeader + QosOffset + 2;\n\t\t/* IV = pHeader + QosOffset + SNAP_SIZE + sizeof(u16) + 2; */\n\t}\n\n\tTempBuf[TempLen - 1] = (u8)(DataLen & 0xff);\n\tTempBuf[TempLen - 2] = (u8)((DataLen & 0xff00) >> 8);\n\tTempBuf[TempLen - 4] = KeyIdx;\n\n\tWAPI_DATA(WAPI_TX, \"CalculateMic - KEY\", MicKey, 16);\n\tWAPI_DATA(WAPI_TX, \"CalculateMic - IV\", IV, 16);\n\tWAPI_DATA(WAPI_TX, \"CalculateMic - TempBuf\", TempBuf, TempLen);\n\tWAPI_DATA(WAPI_TX, \"CalculateMic - pData\", pData, DataLen);\n\n\tWapiSMS4CalculateMic(MicKey, IV, TempBuf, TempLen,\n\t\t\t     pData, DataLen, MicBuffer, &MicLen);\n\n\tif (MicLen != 16)\n\t\tWAPI_TRACE(WAPI_ERR, \"%s: MIC Length Error!!\\n\", __FUNCTION__);\n\n\tWAPI_TRACE(WAPI_TX | WAPI_RX, \"<=========%s\\n\", __FUNCTION__);\n#endif\n}\n\n/* AddCount: 1 or 2.\n *  If overflow, return 1,\n *  else return 0.\n */\nu8 WapiIncreasePN(u8 *PN, u8 AddCount)\n{\n\tu8  i;\n\n\tif (NULL == PN)\n\t\treturn 1;\n\t/* YJ,test,091102 */\n\t/*\n\tif(AddCount == 2){\n\t\tRTW_INFO(\"############################%s(): PN[0]=0x%x\\n\", __FUNCTION__, PN[0]);\n\t\tif(PN[0] == 0x48){\n\t\t\tPN[0] += AddCount;\n\t\t\treturn 1;\n\t\t}else{\n\t\t\tPN[0] += AddCount;\n\t\t\treturn 0;\n\t\t}\n\t}\n\t*/\n\t/* YJ,test,091102,end */\n\n\tfor (i = 0; i < 16; i++) {\n\t\tif (PN[i] + AddCount <= 0xff) {\n\t\t\tPN[i] += AddCount;\n\t\t\treturn 0;\n\t\t} else {\n\t\t\tPN[i] += AddCount;\n\t\t\tAddCount = 1;\n\t\t}\n\t}\n\treturn 1;\n}\n\n\nvoid WapiGetLastRxUnicastPNForQoSData(\n\tu8\t\t\tUserPriority,\n\tPRT_WAPI_STA_INFO    pWapiStaInfo,\n\tu8 *PNOut\n)\n{\n\tWAPI_TRACE(WAPI_RX, \"===========> %s\\n\", __FUNCTION__);\n\tswitch (UserPriority) {\n\tcase 0:\n\tcase 3:\n\t\tmemcpy(PNOut, pWapiStaInfo->lastRxUnicastPNBEQueue, 16);\n\t\tbreak;\n\tcase 1:\n\tcase 2:\n\t\tmemcpy(PNOut, pWapiStaInfo->lastRxUnicastPNBKQueue, 16);\n\t\tbreak;\n\tcase 4:\n\tcase 5:\n\t\tmemcpy(PNOut, pWapiStaInfo->lastRxUnicastPNVIQueue, 16);\n\t\tbreak;\n\tcase 6:\n\tcase 7:\n\t\tmemcpy(PNOut, pWapiStaInfo->lastRxUnicastPNVOQueue, 16);\n\t\tbreak;\n\tdefault:\n\t\tWAPI_TRACE(WAPI_ERR, \"%s: Unknown TID\\n\", __FUNCTION__);\n\t\tbreak;\n\t}\n\tWAPI_TRACE(WAPI_RX, \"<=========== %s\\n\", __FUNCTION__);\n}\n\n\nvoid WapiSetLastRxUnicastPNForQoSData(\n\tu8\t\tUserPriority,\n\tu8           *PNIn,\n\tPRT_WAPI_STA_INFO    pWapiStaInfo\n)\n{\n\tWAPI_TRACE(WAPI_RX, \"===========> %s\\n\", __FUNCTION__);\n\tswitch (UserPriority) {\n\tcase 0:\n\tcase 3:\n\t\tmemcpy(pWapiStaInfo->lastRxUnicastPNBEQueue, PNIn, 16);\n\t\tbreak;\n\tcase 1:\n\tcase 2:\n\t\tmemcpy(pWapiStaInfo->lastRxUnicastPNBKQueue, PNIn, 16);\n\t\tbreak;\n\tcase 4:\n\tcase 5:\n\t\tmemcpy(pWapiStaInfo->lastRxUnicastPNVIQueue, PNIn, 16);\n\t\tbreak;\n\tcase 6:\n\tcase 7:\n\t\tmemcpy(pWapiStaInfo->lastRxUnicastPNVOQueue, PNIn, 16);\n\t\tbreak;\n\tdefault:\n\t\tWAPI_TRACE(WAPI_ERR, \"%s: Unknown TID\\n\", __FUNCTION__);\n\t\tbreak;\n\t}\n\tWAPI_TRACE(WAPI_RX, \"<=========== %s\\n\", __FUNCTION__);\n}\n\n\n/****************************************************************************\n FALSE not RX-Reorder\n TRUE do RX Reorder\nadd to support WAPI to N-mode\n*****************************************************************************/\nu8 WapiCheckPnInSwDecrypt(\n\t_adapter *padapter,\n\tstruct sk_buff *pskb\n)\n{\n\tu8\t\t\t\tret = false;\n\n#if 0\n\tstruct ieee80211_hdr_3addr_qos *header;\n\tu16\t\t\t\tfc;\n\tu8\t\t\t\t*pDaddr, *pTaddr, *pRaddr;\n\n\theader = (struct ieee80211_hdr_3addr_qos *)pskb->data;\n\tpTaddr = header->addr2;\n\tpRaddr = header->addr1;\n\tfc = le16_to_cpu(header->frame_ctl);\n\n\tif (GetToDs(&fc))\n\t\tpDaddr = header->addr3;\n\telse\n\t\tpDaddr = header->addr1;\n\n\tif ((_rtw_memcmp(pRaddr, padapter->pnetdev->dev_addr, ETH_ALEN) == 0)\n\t    &&\t!(pDaddr)\n\t    && (GetFrameType(&fc) == WIFI_QOS_DATA_TYPE))\n\t\t/* && ieee->pHTInfo->bCurrentHTSupport && */\n\t\t/* ieee->pHTInfo->bCurRxReorderEnable) */\n\t\tret = false;\n\telse\n\t\tret = true;\n#endif\n\tWAPI_TRACE(WAPI_RX, \"%s: return %d\\n\", __FUNCTION__, ret);\n\treturn ret;\n}\n\nint SecSMS4HeaderFillIV(_adapter *padapter, u8 *pxmitframe)\n{\n\tstruct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib;\n\tu8 *frame = ((struct xmit_frame *)pxmitframe)->buf_addr + TXDESC_OFFSET;\n\tu8 *pSecHeader = NULL, *pos = NULL, *pRA = NULL;\n\tu8 bPNOverflow = false, bFindMatchPeer = false, hdr_len = 0;\n\tPWLAN_HEADER_WAPI_EXTENSION pWapiExt = NULL;\n\tPRT_WAPI_T         pWapiInfo = &padapter->wapiInfo;\n\tPRT_WAPI_STA_INFO  pWapiSta = NULL;\n\tint ret = 0;\n\n\tWAPI_TRACE(WAPI_TX, \"=========>%s\\n\", __FUNCTION__);\n\n\treturn ret;\n#if 0\n\thdr_len = sMacHdrLng;\n\tif (GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE)\n\t\thdr_len += 2;\n\t/* hdr_len += SNAP_SIZE + sizeof(u16); */\n\n\tpos = skb_push(pskb, padapter->wapiInfo.extra_prefix_len);\n\tmemmove(pos, pos + padapter->wapiInfo.extra_prefix_len, hdr_len);\n\n\tpSecHeader = pskb->data + hdr_len;\n\tpWapiExt = (PWLAN_HEADER_WAPI_EXTENSION)pSecHeader;\n\tpRA = pskb->data + 4;\n\n\tWAPI_DATA(WAPI_TX, \"FillIV - Before Fill IV\", pskb->data, pskb->len);\n\n\t/* Address 1 is always receiver's address */\n\tif (IS_MCAST(pRA)) {\n\t\tif (!pWapiInfo->wapiTxMsk.bTxEnable) {\n\t\t\tWAPI_TRACE(WAPI_ERR, \"%s: bTxEnable = 0!!\\n\", __FUNCTION__);\n\t\t\treturn -2;\n\t\t}\n\t\tif (pWapiInfo->wapiTxMsk.keyId <= 1) {\n\t\t\tpWapiExt->KeyIdx = pWapiInfo->wapiTxMsk.keyId;\n\t\t\tpWapiExt->Reserved = 0;\n\t\t\tbPNOverflow = WapiIncreasePN(pWapiInfo->lastTxMulticastPN, 1);\n\t\t\tmemcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16);\n\t\t\tif (bPNOverflow) {\n\t\t\t\t/* Update MSK Notification. */\n\t\t\t\tWAPI_TRACE(WAPI_ERR, \"===============>%s():multicast PN overflow\\n\", __FUNCTION__);\n\t\t\t\trtw_wapi_app_event_handler(padapter, NULL, 0, pRA, false, false, true, 0, false);\n\t\t\t}\n\t\t} else {\n\t\t\tWAPI_TRACE(WAPI_ERR, \"%s: Invalid Wapi Multicast KeyIdx!!\\n\", __FUNCTION__);\n\t\t\tret = -3;\n\t\t}\n\t} else {\n\t\tlist_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {\n\t\t\tif (!memcmp(pWapiSta->PeerMacAddr, pRA, 6)) {\n\t\t\t\tbFindMatchPeer = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (bFindMatchPeer) {\n\t\t\tif ((!pWapiSta->wapiUskUpdate.bTxEnable) && (!pWapiSta->wapiUsk.bTxEnable)) {\n\t\t\t\tWAPI_TRACE(WAPI_ERR, \"%s: bTxEnable = 0!!\\n\", __FUNCTION__);\n\t\t\t\treturn -4;\n\t\t\t}\n\t\t\tif (pWapiSta->wapiUsk.keyId <= 1) {\n\t\t\t\tif (pWapiSta->wapiUskUpdate.bTxEnable)\n\t\t\t\t\tpWapiExt->KeyIdx = pWapiSta->wapiUskUpdate.keyId;\n\t\t\t\telse\n\t\t\t\t\tpWapiExt->KeyIdx = pWapiSta->wapiUsk.keyId;\n\n\t\t\t\tpWapiExt->Reserved = 0;\n\t\t\t\tbPNOverflow = WapiIncreasePN(pWapiSta->lastTxUnicastPN, 2);\n\t\t\t\tmemcpy(pWapiExt->PN, pWapiSta->lastTxUnicastPN, 16);\n\t\t\t\tif (bPNOverflow) {\n\t\t\t\t\t/* Update USK Notification. */\n\t\t\t\t\tWAPI_TRACE(WAPI_ERR, \"===============>%s():unicast PN overflow\\n\", __FUNCTION__);\n\t\t\t\t\trtw_wapi_app_event_handler(padapter, NULL, 0, pWapiSta->PeerMacAddr, false, true, false, 0, false);\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tWAPI_TRACE(WAPI_ERR, \"%s: Invalid Wapi Unicast KeyIdx!!\\n\", __FUNCTION__);\n\t\t\t\tret = -5;\n\t\t\t}\n\t\t} else {\n\t\t\tWAPI_TRACE(WAPI_ERR, \"%s: Can not find Peer Sta \"MAC_FMT\"!!\\n\", __FUNCTION__, MAC_ARG(pRA));\n\t\t\tret = -6;\n\t\t}\n\t}\n\n\tWAPI_DATA(WAPI_TX, \"FillIV - After Fill IV\", pskb->data, pskb->len);\n\tWAPI_TRACE(WAPI_TX, \"<=========%s\\n\", __FUNCTION__);\n\treturn ret;\n#endif\n}\n\n/* WAPI SW Enc: must have done Coalesce! */\nvoid SecSWSMS4Encryption(\n\t_adapter *padapter,\n\tu8 *pxmitframe\n)\n{\n\tPRT_WAPI_T\t\tpWapiInfo = &padapter->wapiInfo;\n\tPRT_WAPI_STA_INFO   pWapiSta = NULL;\n\tu8 *pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + TXDESC_SIZE;\n\tstruct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib;\n\n\tu8 *SecPtr = NULL, *pRA, *pMicKey = NULL, *pDataKey = NULL, *pIV = NULL;\n\tu8 IVOffset, DataOffset, bFindMatchPeer = false, KeyIdx = 0, MicBuffer[16];\n\tu16 OutputLength;\n\n\tWAPI_TRACE(WAPI_TX, \"=========>%s\\n\", __FUNCTION__);\n\n\tWAPI_TRACE(WAPI_TX, \"hdrlen: %d\\n\", pattrib->hdrlen);\n\n\treturn;\n\n\tDataOffset = pattrib->hdrlen + pattrib->iv_len;\n\n\tpRA = pframe + 4;\n\n\n\tif (IS_MCAST(pRA)) {\n\t\tKeyIdx = pWapiInfo->wapiTxMsk.keyId;\n\t\tpIV = pWapiInfo->lastTxMulticastPN;\n\t\tpMicKey = pWapiInfo->wapiTxMsk.micKey;\n\t\tpDataKey = pWapiInfo->wapiTxMsk.dataKey;\n\t} else {\n\t\tif (!list_empty(&(pWapiInfo->wapiSTAUsedList))) {\n\t\t\tlist_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {\n\t\t\t\tif (0 == memcmp(pWapiSta->PeerMacAddr, pRA, 6)) {\n\t\t\t\t\tbFindMatchPeer = true;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (bFindMatchPeer) {\n\t\t\t\tif (pWapiSta->wapiUskUpdate.bTxEnable) {\n\t\t\t\t\tKeyIdx = pWapiSta->wapiUskUpdate.keyId;\n\t\t\t\t\tWAPI_TRACE(WAPI_TX, \"%s(): Use update USK!! KeyIdx=%d\\n\", __FUNCTION__, KeyIdx);\n\t\t\t\t\tpIV = pWapiSta->lastTxUnicastPN;\n\t\t\t\t\tpMicKey = pWapiSta->wapiUskUpdate.micKey;\n\t\t\t\t\tpDataKey = pWapiSta->wapiUskUpdate.dataKey;\n\t\t\t\t} else {\n\t\t\t\t\tKeyIdx = pWapiSta->wapiUsk.keyId;\n\t\t\t\t\tWAPI_TRACE(WAPI_TX, \"%s(): Use USK!! KeyIdx=%d\\n\", __FUNCTION__, KeyIdx);\n\t\t\t\t\tpIV = pWapiSta->lastTxUnicastPN;\n\t\t\t\t\tpMicKey = pWapiSta->wapiUsk.micKey;\n\t\t\t\t\tpDataKey = pWapiSta->wapiUsk.dataKey;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tWAPI_TRACE(WAPI_ERR, \"%s: Can not find Peer Sta!!\\n\", __FUNCTION__);\n\t\t\t\treturn;\n\t\t\t}\n\t\t} else {\n\t\t\tWAPI_TRACE(WAPI_ERR, \"%s: wapiSTAUsedList is empty!!\\n\", __FUNCTION__);\n\t\t\treturn;\n\t\t}\n\t}\n\n\tSecPtr = pframe;\n\tSecCalculateMicSMS4(KeyIdx, pMicKey, SecPtr, (SecPtr + DataOffset), pattrib->pktlen, MicBuffer);\n\n\tWAPI_DATA(WAPI_TX, \"Encryption - MIC\", MicBuffer, padapter->wapiInfo.extra_postfix_len);\n\n\tmemcpy(pframe + pattrib->hdrlen + pattrib->iv_len + pattrib->pktlen - pattrib->icv_len,\n\t       (u8 *)MicBuffer,\n\t       padapter->wapiInfo.extra_postfix_len\n\t      );\n\n\n\tWapiSMS4Encryption(pDataKey, pIV, (SecPtr + DataOffset), pattrib->pktlen + pattrib->icv_len, (SecPtr + DataOffset), &OutputLength);\n\n\tWAPI_DATA(WAPI_TX, \"Encryption - After SMS4 encryption\", pframe, pattrib->hdrlen + pattrib->iv_len + pattrib->pktlen);\n\n\tWAPI_TRACE(WAPI_TX, \"<=========%s\\n\", __FUNCTION__);\n}\n\nu8 SecSWSMS4Decryption(\n\t_adapter *padapter,\n\tu8\t\t*precv_frame,\n\tstruct recv_priv *precv_priv\n)\n{\n\tPRT_WAPI_T pWapiInfo = &padapter->wapiInfo;\n\tstruct recv_frame_hdr *precv_hdr;\n\tPRT_WAPI_STA_INFO   pWapiSta = NULL;\n\tu8 IVOffset, DataOffset, bFindMatchPeer = false, bUseUpdatedKey = false;\n\tu8 KeyIdx, MicBuffer[16], lastRxPNforQoS[16];\n\tu8 *pRA, *pTA, *pMicKey, *pDataKey, *pLastRxPN, *pRecvPN, *pSecData, *pRecvMic, *pos;\n\tu8 TID = 0;\n\tu16 OutputLength, DataLen;\n\tu8   bQosData;\n\tstruct sk_buff\t*pskb;\n\n\tWAPI_TRACE(WAPI_RX, \"=========>%s\\n\", __FUNCTION__);\n\n\treturn 0;\n\n\tprecv_hdr = &((union recv_frame *)precv_frame)->u.hdr;\n\tpskb = (struct sk_buff *)(precv_hdr->rx_data);\n\tprecv_hdr->bWapiCheckPNInDecrypt = WapiCheckPnInSwDecrypt(padapter, pskb);\n\tWAPI_TRACE(WAPI_RX, \"=========>%s: check PN  %d\\n\", __FUNCTION__, precv_hdr->bWapiCheckPNInDecrypt);\n\tWAPI_DATA(WAPI_RX, \"Decryption - Before decryption\", pskb->data, pskb->len);\n\n\tIVOffset = sMacHdrLng;\n\tbQosData = GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE;\n\tif (bQosData)\n\t\tIVOffset += 2;\n\n\t/* if(GetHTC()) */\n\t/*\tIVOffset += 4; */\n\n\t/* IVOffset += SNAP_SIZE + sizeof(u16); */\n\n\tDataOffset = IVOffset + padapter->wapiInfo.extra_prefix_len;\n\n\tpRA = pskb->data + 4;\n\tpTA = pskb->data + 10;\n\tKeyIdx = *(pskb->data + IVOffset);\n\tpRecvPN = pskb->data + IVOffset + 2;\n\tpSecData = pskb->data + DataOffset;\n\tDataLen = pskb->len - DataOffset;\n\tpRecvMic = pskb->data + pskb->len - padapter->wapiInfo.extra_postfix_len;\n\tTID = GetTid(pskb->data);\n\n\tif (!list_empty(&(pWapiInfo->wapiSTAUsedList))) {\n\t\tlist_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {\n\t\t\tif (0 == memcmp(pWapiSta->PeerMacAddr, pTA, 6)) {\n\t\t\t\tbFindMatchPeer = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (!bFindMatchPeer) {\n\t\tWAPI_TRACE(WAPI_ERR, \"%s: Can not find Peer Sta \"MAC_FMT\" for Key Info!!!\\n\", __FUNCTION__, MAC_ARG(pTA));\n\t\treturn false;\n\t}\n\n\tif (IS_MCAST(pRA)) {\n\t\tWAPI_TRACE(WAPI_RX, \"%s: Multicast decryption !!!\\n\", __FUNCTION__);\n\t\tif (pWapiSta->wapiMsk.keyId == KeyIdx && pWapiSta->wapiMsk.bSet) {\n\t\t\tpLastRxPN = pWapiSta->lastRxMulticastPN;\n\t\t\tif (!WapiComparePN(pRecvPN, pLastRxPN)) {\n\t\t\t\tWAPI_TRACE(WAPI_ERR, \"%s: MSK PN is not larger than last, Dropped!!!\\n\", __FUNCTION__);\n\t\t\t\tWAPI_DATA(WAPI_ERR, \"pRecvPN:\", pRecvPN, 16);\n\t\t\t\tWAPI_DATA(WAPI_ERR, \"pLastRxPN:\", pLastRxPN, 16);\n\t\t\t\treturn false;\n\t\t\t}\n\n\t\t\tmemcpy(pLastRxPN, pRecvPN, 16);\n\t\t\tpMicKey = pWapiSta->wapiMsk.micKey;\n\t\t\tpDataKey = pWapiSta->wapiMsk.dataKey;\n\t\t} else if (pWapiSta->wapiMskUpdate.keyId == KeyIdx && pWapiSta->wapiMskUpdate.bSet) {\n\t\t\tWAPI_TRACE(WAPI_RX, \"%s: Use Updated MSK for Decryption !!!\\n\", __FUNCTION__);\n\t\t\tbUseUpdatedKey = true;\n\t\t\tmemcpy(pWapiSta->lastRxMulticastPN, pRecvPN, 16);\n\t\t\tpMicKey = pWapiSta->wapiMskUpdate.micKey;\n\t\t\tpDataKey = pWapiSta->wapiMskUpdate.dataKey;\n\t\t} else {\n\t\t\tWAPI_TRACE(WAPI_ERR, \"%s: Can not find MSK with matched KeyIdx(%d), Dropped !!!\\n\", __FUNCTION__, KeyIdx);\n\t\t\treturn false;\n\t\t}\n\t} else {\n\t\tWAPI_TRACE(WAPI_RX, \"%s: Unicast decryption !!!\\n\", __FUNCTION__);\n\t\tif (pWapiSta->wapiUsk.keyId == KeyIdx && pWapiSta->wapiUsk.bSet) {\n\t\t\tWAPI_TRACE(WAPI_RX, \"%s: Use USK for Decryption!!!\\n\", __FUNCTION__);\n\t\t\tif (precv_hdr->bWapiCheckPNInDecrypt) {\n\t\t\t\tif (GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE) {\n\t\t\t\t\tWapiGetLastRxUnicastPNForQoSData(TID, pWapiSta, lastRxPNforQoS);\n\t\t\t\t\tpLastRxPN = lastRxPNforQoS;\n\t\t\t\t} else\n\t\t\t\t\tpLastRxPN = pWapiSta->lastRxUnicastPN;\n\t\t\t\tif (!WapiComparePN(pRecvPN, pLastRxPN))\n\t\t\t\t\treturn false;\n\t\t\t\tif (bQosData)\n\t\t\t\t\tWapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta);\n\t\t\t\telse\n\t\t\t\t\tmemcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16);\n\t\t\t} else\n\t\t\t\tmemcpy(precv_hdr->WapiTempPN, pRecvPN, 16);\n\n\t\t\tif (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE)) {\n\t\t\t\tif ((pRecvPN[0] & 0x1) == 0) {\n\t\t\t\t\tWAPI_TRACE(WAPI_ERR, \"%s: Rx USK PN is not odd when Infra STA mode, Dropped !!!\\n\", __FUNCTION__);\n\t\t\t\t\treturn false;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tpMicKey = pWapiSta->wapiUsk.micKey;\n\t\t\tpDataKey = pWapiSta->wapiUsk.dataKey;\n\t\t} else if (pWapiSta->wapiUskUpdate.keyId == KeyIdx && pWapiSta->wapiUskUpdate.bSet) {\n\t\t\tWAPI_TRACE(WAPI_RX, \"%s: Use Updated USK for Decryption!!!\\n\", __FUNCTION__);\n\t\t\tif (pWapiSta->bAuthenticatorInUpdata)\n\t\t\t\tbUseUpdatedKey = true;\n\t\t\telse\n\t\t\t\tbUseUpdatedKey = false;\n\n\t\t\tif (bQosData)\n\t\t\t\tWapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta);\n\t\t\telse\n\t\t\t\tmemcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16);\n\t\t\tpMicKey = pWapiSta->wapiUskUpdate.micKey;\n\t\t\tpDataKey = pWapiSta->wapiUskUpdate.dataKey;\n\t\t} else {\n\t\t\tWAPI_TRACE(WAPI_ERR, \"%s: No valid USK!!!KeyIdx=%d pWapiSta->wapiUsk.keyId=%d pWapiSta->wapiUskUpdate.keyId=%d\\n\", __FUNCTION__, KeyIdx, pWapiSta->wapiUsk.keyId,\n\t\t\t\t   pWapiSta->wapiUskUpdate.keyId);\n\t\t\t/* dump_buf(pskb->data,pskb->len); */\n\t\t\treturn false;\n\t\t}\n\t}\n\n\tWAPI_DATA(WAPI_RX, \"Decryption - DataKey\", pDataKey, 16);\n\tWAPI_DATA(WAPI_RX, \"Decryption - IV\", pRecvPN, 16);\n\tWapiSMS4Decryption(pDataKey, pRecvPN, pSecData, DataLen, pSecData, &OutputLength);\n\n\tif (OutputLength != DataLen)\n\t\tWAPI_TRACE(WAPI_ERR, \"%s:  Output Length Error!!!!\\n\", __FUNCTION__);\n\n\tWAPI_DATA(WAPI_RX, \"Decryption - After decryption\", pskb->data, pskb->len);\n\n\tDataLen -= padapter->wapiInfo.extra_postfix_len;\n\n\tSecCalculateMicSMS4(KeyIdx, pMicKey, pskb->data, pSecData, DataLen, MicBuffer);\n\n\tWAPI_DATA(WAPI_RX, \"Decryption - MIC received\", pRecvMic, SMS4_MIC_LEN);\n\tWAPI_DATA(WAPI_RX, \"Decryption - MIC calculated\", MicBuffer, SMS4_MIC_LEN);\n\n\tif (0 == memcmp(MicBuffer, pRecvMic, padapter->wapiInfo.extra_postfix_len)) {\n\t\tWAPI_TRACE(WAPI_RX, \"%s: Check MIC OK!!\\n\", __FUNCTION__);\n\t\tif (bUseUpdatedKey) {\n\t\t\t/* delete the old key */\n\t\t\tif (IS_MCAST(pRA)) {\n\t\t\t\tWAPI_TRACE(WAPI_API, \"%s(): AE use new update MSK!!\\n\", __FUNCTION__);\n\t\t\t\tpWapiSta->wapiMsk.keyId = pWapiSta->wapiMskUpdate.keyId;\n\t\t\t\tmemcpy(pWapiSta->wapiMsk.dataKey, pWapiSta->wapiMskUpdate.dataKey, 16);\n\t\t\t\tmemcpy(pWapiSta->wapiMsk.micKey, pWapiSta->wapiMskUpdate.micKey, 16);\n\t\t\t\tpWapiSta->wapiMskUpdate.bTxEnable = pWapiSta->wapiMskUpdate.bSet = false;\n\t\t\t} else {\n\t\t\t\tWAPI_TRACE(WAPI_API, \"%s(): AE use new update USK!!\\n\", __FUNCTION__);\n\t\t\t\tpWapiSta->wapiUsk.keyId = pWapiSta->wapiUskUpdate.keyId;\n\t\t\t\tmemcpy(pWapiSta->wapiUsk.dataKey, pWapiSta->wapiUskUpdate.dataKey, 16);\n\t\t\t\tmemcpy(pWapiSta->wapiUsk.micKey, pWapiSta->wapiUskUpdate.micKey, 16);\n\t\t\t\tpWapiSta->wapiUskUpdate.bTxEnable = pWapiSta->wapiUskUpdate.bSet = false;\n\t\t\t}\n\t\t}\n\t} else {\n\t\tWAPI_TRACE(WAPI_ERR, \"%s:  Check MIC Error, Dropped !!!!\\n\", __FUNCTION__);\n\t\treturn false;\n\t}\n\n\tpos = pskb->data;\n\tmemmove(pos + padapter->wapiInfo.extra_prefix_len, pos, IVOffset);\n\tskb_pull(pskb, padapter->wapiInfo.extra_prefix_len);\n\n\tWAPI_TRACE(WAPI_RX, \"<=========%s\\n\", __FUNCTION__);\n\n\treturn true;\n}\n\nu32\trtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe)\n{\n\n\tu8\t*pframe;\n\tu32 res = _SUCCESS;\n\n\tWAPI_TRACE(WAPI_TX, \"=========>%s\\n\", __FUNCTION__);\n\n\tif ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {\n\t\tWAPI_TRACE(WAPI_TX, \"<========== %s, WAPI not supported or enabled!\\n\", __FUNCTION__);\n\t\treturn _FAIL;\n\t}\n\n\tif (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)\n\t\treturn _FAIL;\n\n\tpframe = ((struct xmit_frame *)pxmitframe)->buf_addr + TXDESC_OFFSET;\n\n\tSecSWSMS4Encryption(padapter, pxmitframe);\n\n\tWAPI_TRACE(WAPI_TX, \"<=========%s\\n\", __FUNCTION__);\n\treturn res;\n}\n\nu32\trtw_sms4_decrypt(_adapter *padapter, u8 *precvframe)\n{\n\tu8\t*pframe;\n\tu32 res = _SUCCESS;\n\n\tWAPI_TRACE(WAPI_RX, \"=========>%s\\n\", __FUNCTION__);\n\n\tif ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {\n\t\tWAPI_TRACE(WAPI_RX, \"<========== %s, WAPI not supported or enabled!\\n\", __FUNCTION__);\n\t\treturn _FAIL;\n\t}\n\n\n\t/* drop packet when hw decrypt fail\n\t* return tempraily */\n\treturn _FAIL;\n\n\t/* pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; */\n\n\tif (false == SecSWSMS4Decryption(padapter, precvframe, &padapter->recvpriv)) {\n\t\tWAPI_TRACE(WAPI_ERR, \"%s():SMS4 decrypt frame error\\n\", __FUNCTION__);\n\t\treturn _FAIL;\n\t}\n\n\tWAPI_TRACE(WAPI_RX, \"<=========%s\\n\", __FUNCTION__);\n\treturn res;\n}\n\n#else\n\nu32\trtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe)\n{\n\tWAPI_TRACE(WAPI_TX, \"=========>Dummy %s\\n\", __FUNCTION__);\n\tWAPI_TRACE(WAPI_TX, \"<=========Dummy %s\\n\", __FUNCTION__);\n\treturn _SUCCESS;\n}\n\nu32\trtw_sms4_decrypt(_adapter *padapter, u8 *precvframe)\n{\n\tWAPI_TRACE(WAPI_RX, \"=========>Dummy %s\\n\", __FUNCTION__);\n\tWAPI_TRACE(WAPI_RX, \"<=========Dummy %s\\n\", __FUNCTION__);\n\treturn _SUCCESS;\n}\n\n#endif\n\n#endif\n"
  },
  {
    "path": "core/rtw_wlan_util.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_WLAN_UTIL_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\n\t#include <linux/inetdevice.h>\n\t#define ETH_TYPE_OFFSET\t12\n\t#define PROTOCOL_OFFSET\t23\n\t#define IP_OFFSET\t30\n\t#define IPv6_OFFSET\t38\n\t#define IPv6_PROTOCOL_OFFSET\t20\n#endif\n\nunsigned char ARTHEROS_OUI1[] = {0x00, 0x03, 0x7f};\nunsigned char ARTHEROS_OUI2[] = {0x00, 0x13, 0x74};\n\nunsigned char BROADCOM_OUI1[] = {0x00, 0x10, 0x18};\nunsigned char BROADCOM_OUI2[] = {0x00, 0x0a, 0xf7};\nunsigned char BROADCOM_OUI3[] = {0x00, 0x05, 0xb5};\n\n\nunsigned char CISCO_OUI[] = {0x00, 0x40, 0x96};\nunsigned char MARVELL_OUI[] = {0x00, 0x50, 0x43};\nunsigned char RALINK_OUI[] = {0x00, 0x0c, 0x43};\nunsigned char REALTEK_OUI[] = {0x00, 0xe0, 0x4c};\nunsigned char AIRGOCAP_OUI[] = {0x00, 0x0a, 0xf5};\n\nunsigned char REALTEK_96B_IE[] = {0x00, 0xe0, 0x4c, 0x02, 0x01, 0x20};\n\nextern unsigned char RTW_WPA_OUI[];\nextern unsigned char WPA_TKIP_CIPHER[4];\nextern unsigned char RSN_TKIP_CIPHER[4];\n\n#define R2T_PHY_DELAY\t(0)\n\n/* #define WAIT_FOR_BCN_TO_MIN\t(3000) */\n#define WAIT_FOR_BCN_TO_MIN\t(6000)\n#define WAIT_FOR_BCN_TO_MAX\t(20000)\n\nstatic u8 rtw_basic_rate_cck[4] = {\n\tIEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK,\n\tIEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK\n};\n\nstatic u8 rtw_basic_rate_ofdm[3] = {\n\tIEEE80211_OFDM_RATE_6MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_12MB | IEEE80211_BASIC_RATE_MASK,\n\tIEEE80211_OFDM_RATE_24MB | IEEE80211_BASIC_RATE_MASK\n};\n\nstatic u8 rtw_basic_rate_mix[7] = {\n\tIEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK,\n\tIEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK,\n\tIEEE80211_OFDM_RATE_6MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_12MB | IEEE80211_BASIC_RATE_MASK,\n\tIEEE80211_OFDM_RATE_24MB | IEEE80211_BASIC_RATE_MASK\n};\n\nextern u8\tWIFI_CCKRATES[];\nbool rtw_is_cck_rate(u8 rate)\n{\n\tint i;\n\n\tfor (i = 0; i < 4; i++)\n\t\tif ((WIFI_CCKRATES[i] & 0x7F) == (rate & 0x7F))\n\t\t\treturn 1;\n\treturn 0;\n}\n\nextern u8\tWIFI_OFDMRATES[];\nbool rtw_is_ofdm_rate(u8 rate)\n{\n\tint i;\n\n\tfor (i = 0; i < 8; i++)\n\t\tif ((WIFI_OFDMRATES[i] & 0x7F) == (rate & 0x7F))\n\t\t\treturn 1;\n\treturn 0;\n}\n\n/* test if rate is defined in rtw_basic_rate_cck */\nbool rtw_is_basic_rate_cck(u8 rate)\n{\n\tint i;\n\n\tfor (i = 0; i < 4; i++)\n\t\tif ((rtw_basic_rate_cck[i] & 0x7F) == (rate & 0x7F))\n\t\t\treturn 1;\n\treturn 0;\n}\n\n/* test if rate is defined in rtw_basic_rate_ofdm */\nbool rtw_is_basic_rate_ofdm(u8 rate)\n{\n\tint i;\n\n\tfor (i = 0; i < 3; i++)\n\t\tif ((rtw_basic_rate_ofdm[i] & 0x7F) == (rate & 0x7F))\n\t\t\treturn 1;\n\treturn 0;\n}\n\n/* test if rate is defined in rtw_basic_rate_mix */\nbool rtw_is_basic_rate_mix(u8 rate)\n{\n\tint i;\n\n\tfor (i = 0; i < 7; i++)\n\t\tif ((rtw_basic_rate_mix[i] & 0x7F) == (rate & 0x7F))\n\t\t\treturn 1;\n\treturn 0;\n}\n#ifdef CONFIG_BCN_CNT_CONFIRM_HDL\nint new_bcn_max = 3;\n#endif\nint cckrates_included(unsigned char *rate, int ratelen)\n{\n\tint\ti;\n\n\tfor (i = 0; i < ratelen; i++) {\n\t\tif ((((rate[i]) & 0x7f) == 2)\t|| (((rate[i]) & 0x7f) == 4) ||\n\t\t    (((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) == 22))\n\t\t\treturn _TRUE;\n\t}\n\n\treturn _FALSE;\n\n}\n\nint cckratesonly_included(unsigned char *rate, int ratelen)\n{\n\tint\ti;\n\n\tfor (i = 0; i < ratelen; i++) {\n\t\tif ((((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) &&\n\t\t    (((rate[i]) & 0x7f) != 11)  && (((rate[i]) & 0x7f) != 22))\n\t\t\treturn _FALSE;\n\t}\n\n\treturn _TRUE;\n}\n\ns8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tu8 rf_type = RF_1T1R, custom_rf_type;\n\ts8 nss = 1;\n\n\tif (!psta)\n\t\treturn nss;\n\n\tcustom_rf_type = adapter->registrypriv.rf_config;\n\trtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));\n\tif (RF_TYPE_VALID(custom_rf_type))\n\t\trf_type = custom_rf_type;\n\n\tnss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num);\n\n#ifdef CONFIG_80211N_HT\n\t#ifdef CONFIG_80211AC_VHT\n\tif (psta->vhtpriv.vht_option)\n\t\tnss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map));\n\telse\n\t#endif /* CONFIG_80211AC_VHT */\n\tif (psta->htpriv.ht_option)\n\t\tnss = rtw_min(nss, rtw_ht_mcsset_to_nss(psta->htpriv.ht_cap.supp_mcs_set));\n#endif /*CONFIG_80211N_HT*/\n\tRTW_INFO(\"%s: %d SS\\n\", __func__, nss);\n\treturn nss;\n}\n\ns8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tu8 rf_type = RF_1T1R, custom_rf_type;\n\ts8 nss = 1;\n\n\tif (!psta)\n\t\treturn nss;\n\n\tcustom_rf_type = adapter->registrypriv.rf_config;\n\trtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));\n\tif (RF_TYPE_VALID(custom_rf_type))\n\t\trf_type = custom_rf_type;\n\n\tnss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);\n\n#ifdef CONFIG_80211N_HT\n\t#ifdef CONFIG_80211AC_VHT\n\tif (psta->vhtpriv.vht_option)\n\t\tnss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map));\n\telse\n\t#endif /* CONFIG_80211AC_VHT */\n\tif (psta->htpriv.ht_option)\n\t\tnss = rtw_min(nss, rtw_ht_mcsset_to_nss(psta->htpriv.ht_cap.supp_mcs_set));\n#endif /*CONFIG_80211N_HT*/\n\tRTW_INFO(\"%s: %d SS\\n\", __func__, nss);\n\treturn nss;\n}\n\nu8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen)\n{\n\tu8 network_type = 0;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\n\tif (pmlmeext->cur_channel > 14) {\n\t\tif (pmlmeinfo->VHT_enable)\n\t\t\tnetwork_type = WIRELESS_11AC;\n\t\telse if (pmlmeinfo->HT_enable)\n\t\t\tnetwork_type = WIRELESS_11_5N;\n\n\t\tnetwork_type |= WIRELESS_11A;\n\t} else {\n\t\tif (pmlmeinfo->HT_enable)\n\t\t\tnetwork_type = WIRELESS_11_24N;\n\n\t\tif ((cckratesonly_included(rate, ratelen)) == _TRUE)\n\t\t\tnetwork_type |= WIRELESS_11B;\n\t\telse if ((cckrates_included(rate, ratelen)) == _TRUE)\n\t\t\tnetwork_type |= WIRELESS_11BG;\n\t\telse\n\t\t\tnetwork_type |= WIRELESS_11G;\n\t}\n\n\treturn\tnetwork_type;\n}\n\nunsigned char ratetbl_val_2wifirate(unsigned char rate);\nunsigned char ratetbl_val_2wifirate(unsigned char rate)\n{\n\tunsigned char val = 0;\n\n\tswitch (rate & 0x7f) {\n\tcase 0:\n\t\tval = IEEE80211_CCK_RATE_1MB;\n\t\tbreak;\n\n\tcase 1:\n\t\tval = IEEE80211_CCK_RATE_2MB;\n\t\tbreak;\n\n\tcase 2:\n\t\tval = IEEE80211_CCK_RATE_5MB;\n\t\tbreak;\n\n\tcase 3:\n\t\tval = IEEE80211_CCK_RATE_11MB;\n\t\tbreak;\n\n\tcase 4:\n\t\tval = IEEE80211_OFDM_RATE_6MB;\n\t\tbreak;\n\n\tcase 5:\n\t\tval = IEEE80211_OFDM_RATE_9MB;\n\t\tbreak;\n\n\tcase 6:\n\t\tval = IEEE80211_OFDM_RATE_12MB;\n\t\tbreak;\n\n\tcase 7:\n\t\tval = IEEE80211_OFDM_RATE_18MB;\n\t\tbreak;\n\n\tcase 8:\n\t\tval = IEEE80211_OFDM_RATE_24MB;\n\t\tbreak;\n\n\tcase 9:\n\t\tval = IEEE80211_OFDM_RATE_36MB;\n\t\tbreak;\n\n\tcase 10:\n\t\tval = IEEE80211_OFDM_RATE_48MB;\n\t\tbreak;\n\n\tcase 11:\n\t\tval = IEEE80211_OFDM_RATE_54MB;\n\t\tbreak;\n\n\t}\n\n\treturn val;\n\n}\n\nint is_basicrate(_adapter *padapter, unsigned char rate);\nint is_basicrate(_adapter *padapter, unsigned char rate)\n{\n\tint i;\n\tunsigned char val;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\n\tfor (i = 0; i < NumRates; i++) {\n\t\tval = pmlmeext->basicrate[i];\n\n\t\tif ((val != 0xff) && (val != 0xfe)) {\n\t\t\tif (rate == ratetbl_val_2wifirate(val))\n\t\t\t\treturn _TRUE;\n\t\t}\n\t}\n\n\treturn _FALSE;\n}\n\nunsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset);\nunsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset)\n{\n\tint i;\n\tunsigned char rate;\n\tunsigned int\tlen = 0;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\n\tfor (i = 0; i < NumRates; i++) {\n\t\trate = pmlmeext->datarate[i];\n\n\t\tif (rtw_get_oper_ch(padapter) > 14 && rate < _6M_RATE_) /*5G no support CCK rate*/\n\t\t\tcontinue;\n\n\t\tswitch (rate) {\n\t\tcase 0xff:\n\t\t\treturn len;\n\n\t\tcase 0xfe:\n\t\t\tcontinue;\n\n\t\tdefault:\n\t\t\trate = ratetbl_val_2wifirate(rate);\n\n\t\t\tif (is_basicrate(padapter, rate) == _TRUE)\n\t\t\t\trate |= IEEE80211_BASIC_RATE_MASK;\n\n\t\t\trateset[len] = rate;\n\t\t\tlen++;\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn len;\n}\n\nvoid get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len)\n{\n\tunsigned char supportedrates[NumRates];\n\n\t_rtw_memset(supportedrates, 0, NumRates);\n\t*bssrate_len = ratetbl2rateset(padapter, supportedrates);\n\t_rtw_memcpy(pbssrate, supportedrates, *bssrate_len);\n}\n\nvoid set_mcs_rate_by_mask(u8 *mcs_set, u32 mask)\n{\n\tu8 mcs_rate_1r = (u8)(mask & 0xff);\n\tu8 mcs_rate_2r = (u8)((mask >> 8) & 0xff);\n\tu8 mcs_rate_3r = (u8)((mask >> 16) & 0xff);\n\tu8 mcs_rate_4r = (u8)((mask >> 24) & 0xff);\n\n\tmcs_set[0] &= mcs_rate_1r;\n\tmcs_set[1] &= mcs_rate_2r;\n\tmcs_set[2] &= mcs_rate_3r;\n\tmcs_set[3] &= mcs_rate_4r;\n}\n\nvoid UpdateBrateTbl(\n\tPADAPTER\t\tAdapter,\n\tu8\t\t\t*mBratesOS\n)\n{\n\tu8\ti;\n\tu8\trate;\n\n\t/* 1M, 2M, 5.5M, 11M, 6M, 12M, 24M are mandatory. */\n\tfor (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {\n\t\trate = mBratesOS[i] & 0x7f;\n\t\tswitch (rate) {\n\t\tcase IEEE80211_CCK_RATE_1MB:\n\t\tcase IEEE80211_CCK_RATE_2MB:\n\t\tcase IEEE80211_CCK_RATE_5MB:\n\t\tcase IEEE80211_CCK_RATE_11MB:\n\t\tcase IEEE80211_OFDM_RATE_6MB:\n\t\tcase IEEE80211_OFDM_RATE_12MB:\n\t\tcase IEEE80211_OFDM_RATE_24MB:\n\t\t\tmBratesOS[i] |= IEEE80211_BASIC_RATE_MASK;\n\t\t\tbreak;\n\t\t}\n\t}\n\n}\n\nvoid UpdateBrateTblForSoftAP(u8 *bssrateset, u32 bssratelen)\n{\n\tu8\ti;\n\tu8\trate;\n\n\tfor (i = 0; i < bssratelen; i++) {\n\t\trate = bssrateset[i] & 0x7f;\n\t\tswitch (rate) {\n\t\tcase IEEE80211_CCK_RATE_1MB:\n\t\tcase IEEE80211_CCK_RATE_2MB:\n\t\tcase IEEE80211_CCK_RATE_5MB:\n\t\tcase IEEE80211_CCK_RATE_11MB:\n\t\t\tbssrateset[i] |= IEEE80211_BASIC_RATE_MASK;\n\t\t\tbreak;\n\t\t}\n\t}\n\n}\nvoid Set_MSR(_adapter *padapter, u8 type)\n{\n\trtw_hal_set_hwreg(padapter, HW_VAR_MEDIA_STATUS, (u8 *)(&type));\n}\n\ninline u8 rtw_get_oper_ch(_adapter *adapter)\n{\n\treturn adapter_to_dvobj(adapter)->oper_channel;\n}\n\ninline void rtw_set_oper_ch(_adapter *adapter, u8 ch)\n{\n#ifdef DBG_CH_SWITCH\n\tconst int len = 128;\n\tchar msg[128] = {0};\n\tint cnt = 0;\n\tint i = 0;\n#endif  /* DBG_CH_SWITCH */\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\n\tif (dvobj->oper_channel != ch) {\n\t\tdvobj->on_oper_ch_time = rtw_get_current_time();\n\n#ifdef DBG_CH_SWITCH\n\t\tcnt += snprintf(msg + cnt, len - cnt, \"switch to ch %3u\", ch);\n\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\t_adapter *iface = dvobj->padapters[i];\n\t\t\tcnt += snprintf(msg + cnt, len - cnt, \" [\"ADPT_FMT\":\", ADPT_ARG(iface));\n\t\t\tif (iface->mlmeextpriv.cur_channel == ch)\n\t\t\t\tcnt += snprintf(msg + cnt, len - cnt, \"C\");\n\t\t\telse\n\t\t\t\tcnt += snprintf(msg + cnt, len - cnt, \"_\");\n\t\t\tif (iface->wdinfo.listen_channel == ch && !rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_NONE))\n\t\t\t\tcnt += snprintf(msg + cnt, len - cnt, \"L\");\n\t\t\telse\n\t\t\t\tcnt += snprintf(msg + cnt, len - cnt, \"_\");\n\t\t\tcnt += snprintf(msg + cnt, len - cnt, \"]\");\n\t\t}\n\n\t\tRTW_INFO(FUNC_ADPT_FMT\" %s\\n\", FUNC_ADPT_ARG(adapter), msg);\n#endif /* DBG_CH_SWITCH */\n\t}\n\n\tdvobj->oper_channel = ch;\n}\n\ninline u8 rtw_get_oper_bw(_adapter *adapter)\n{\n\treturn adapter_to_dvobj(adapter)->oper_bwmode;\n}\n\ninline void rtw_set_oper_bw(_adapter *adapter, u8 bw)\n{\n\tadapter_to_dvobj(adapter)->oper_bwmode = bw;\n}\n\ninline u8 rtw_get_oper_choffset(_adapter *adapter)\n{\n\treturn adapter_to_dvobj(adapter)->oper_ch_offset;\n}\n\ninline void rtw_set_oper_choffset(_adapter *adapter, u8 offset)\n{\n\tadapter_to_dvobj(adapter)->oper_ch_offset = offset;\n}\n\nu8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset)\n{\n\tu8 valid = 1;\n\tu8 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\n\tif (bw == CHANNEL_WIDTH_20)\n\t\tgoto exit;\n\n\tif (bw >= CHANNEL_WIDTH_80 && ch <= 14) {\n\t\tvalid = 0;\n\t\tgoto exit;\n\t}\n\n\tif (ch >= 1 && ch <= 4)\n\t\toffset = HAL_PRIME_CHNL_OFFSET_LOWER;\n\telse if (ch >= 5 && ch <= 9) {\n\t\tif (*r_offset == HAL_PRIME_CHNL_OFFSET_LOWER || *r_offset == HAL_PRIME_CHNL_OFFSET_UPPER)\n\t\t\toffset = *r_offset; /* both lower and upper is valid, obey input value */\n\t\telse\n\t\t\toffset = HAL_PRIME_CHNL_OFFSET_UPPER; /* default use upper */\n\t} else if (ch >= 10 && ch <= 13)\n\t\toffset = HAL_PRIME_CHNL_OFFSET_UPPER;\n\telse if (ch == 14) {\n\t\tvalid = 0; /* ch14 doesn't support 40MHz bandwidth */\n\t\tgoto exit;\n\t} else if (ch >= 36 && ch <= 177) {\n\t\tswitch (ch) {\n\t\tcase 36:\n\t\tcase 44:\n\t\tcase 52:\n\t\tcase 60:\n\t\tcase 100:\n\t\tcase 108:\n\t\tcase 116:\n\t\tcase 124:\n\t\tcase 132:\n\t\tcase 140:\n\t\tcase 149:\n\t\tcase 157:\n\t\tcase 165:\n\t\tcase 173:\n\t\t\toffset = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\t\tbreak;\n\t\tcase 40:\n\t\tcase 48:\n\t\tcase 56:\n\t\tcase 64:\n\t\tcase 104:\n\t\tcase 112:\n\t\tcase 120:\n\t\tcase 128:\n\t\tcase 136:\n\t\tcase 144:\n\t\tcase 153:\n\t\tcase 161:\n\t\tcase 169:\n\t\tcase 177:\n\t\t\toffset = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tvalid = 0;\n\t\t\tbreak;\n\t\t}\n\t} else\n\t\tvalid = 0;\n\nexit:\n\tif (valid && r_offset)\n\t\t*r_offset = offset;\n\treturn valid;\n}\n\nu8 rtw_get_center_ch(u8 channel, u8 chnl_bw, u8 chnl_offset)\n{\n\tu8 center_ch = channel;\n\n\tif (chnl_bw == CHANNEL_WIDTH_80) {\n\t\tif (channel == 36 || channel == 40 || channel == 44 || channel == 48)\n\t\t\tcenter_ch = 42;\n\t\telse if (channel == 52 || channel == 56 || channel == 60 || channel == 64)\n\t\t\tcenter_ch = 58;\n\t\telse if (channel == 100 || channel == 104 || channel == 108 || channel == 112)\n\t\t\tcenter_ch = 106;\n\t\telse if (channel == 116 || channel == 120 || channel == 124 || channel == 128)\n\t\t\tcenter_ch = 122;\n\t\telse if (channel == 132 || channel == 136 || channel == 140 || channel == 144)\n\t\t\tcenter_ch = 138;\n\t\telse if (channel == 149 || channel == 153 || channel == 157 || channel == 161)\n\t\t\tcenter_ch = 155;\n\t\telse if (channel == 165 || channel == 169 || channel == 173 || channel == 177)\n\t\t\tcenter_ch = 171;\n\t\telse if (channel <= 14)\n\t\t\tcenter_ch = 7;\n\t} else if (chnl_bw == CHANNEL_WIDTH_40) {\n\t\tif (chnl_offset == HAL_PRIME_CHNL_OFFSET_LOWER)\n\t\t\tcenter_ch = channel + 2;\n\t\telse\n\t\t\tcenter_ch = channel - 2;\n\t} else if (chnl_bw == CHANNEL_WIDTH_20)\n\t\tcenter_ch = channel;\n\telse\n\t\trtw_warn_on(1);\n\n\treturn center_ch;\n}\n\ninline systime rtw_get_on_oper_ch_time(_adapter *adapter)\n{\n\treturn adapter_to_dvobj(adapter)->on_oper_ch_time;\n}\n\ninline systime rtw_get_on_cur_ch_time(_adapter *adapter)\n{\n\tif (adapter->mlmeextpriv.cur_channel == adapter_to_dvobj(adapter)->oper_channel)\n\t\treturn adapter_to_dvobj(adapter)->on_oper_ch_time;\n\telse\n\t\treturn 0;\n}\n\nvoid set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode)\n{\n\tu8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE)\n\tu8 iqk_info_backup = _FALSE;\n#endif\n\n\tif (padapter->bNotifyChannelChange)\n\t\tRTW_INFO(\"[%s] ch = %d, offset = %d, bwmode = %d\\n\", __FUNCTION__, channel, channel_offset, bwmode);\n\n\tcenter_ch = rtw_get_center_ch(channel, bwmode, channel_offset);\n\n\tif (bwmode == CHANNEL_WIDTH_80) {\n\t\tif (center_ch > channel)\n\t\t\tchnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\telse if (center_ch < channel)\n\t\t\tchnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\telse\n\t\t\tchnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t}\n\t_enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);\n\n#ifdef CONFIG_MCC_MODE\n\tif (MCC_EN(padapter)) {\n\t\t/* driver doesn't set channel setting reg under MCC */\n\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))\n\t\t\tRTW_INFO(\"Warning: Do not set channel setting reg MCC mode\\n\");\n\t}\n#endif\n\n#ifdef CONFIG_DFS_MASTER\n\t{\n\t\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\t\tbool ori_overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl);\n\t\tbool new_overlap_radar_detect_ch = _rtw_rfctl_overlap_radar_detect_ch(rfctl, channel, bwmode, channel_offset);\n\n\t\tif (new_overlap_radar_detect_ch && IS_CH_WAITING(rfctl)) {\n\t\t\tu8 pause = 0xFF;\n\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause);\n\t\t}\n#endif /* CONFIG_DFS_MASTER */\n\n\t\t/* set Channel */\n\t\t/* saved channel/bw info */\n\t\trtw_set_oper_ch(padapter, channel);\n\t\trtw_set_oper_bw(padapter, bwmode);\n\t\trtw_set_oper_choffset(padapter, channel_offset);\n\n#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE)\n\t\t/* To check if we need to backup iqk info after switch chnl & bw */\n\t\t{\n\t\t\tu8 take_care_iqk, do_iqk;\n\n\t\t\trtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);\n\t\t\trtw_hal_get_hwreg(padapter, HW_VAR_DO_IQK, &do_iqk);\n\t\t\tif ((take_care_iqk == _TRUE) && (do_iqk == _TRUE))\n\t\t\t\tiqk_info_backup = _TRUE;\n\t\t}\n#endif\n\n\t\trtw_hal_set_chnl_bw(padapter, center_ch, bwmode, channel_offset, chnl_offset80); /* set center channel */\n\n#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE)\n\t\tif (iqk_info_backup == _TRUE)\n\t\t\trtw_hal_ch_sw_iqk_info_backup(padapter);\n#endif\n\n#ifdef CONFIG_DFS_MASTER\n\t\tif (new_overlap_radar_detect_ch)\n\t\t\trtw_odm_radar_detect_enable(padapter);\n\t\telse if (ori_overlap_radar_detect_ch) {\n\t\t\tu8 pause = 0x00;\n\n\t\t\trtw_odm_radar_detect_disable(padapter);\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause);\n\t\t}\n\t}\n#endif /* CONFIG_DFS_MASTER */\n\n\t_exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);\n}\n\n__inline u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork)\n{\n\treturn pnetwork->MacAddress;\n}\n\nu16 get_beacon_interval(WLAN_BSSID_EX *bss)\n{\n\tunsigned short val;\n\t_rtw_memcpy((unsigned char *)&val, rtw_get_beacon_interval_from_ie(bss->IEs), 2);\n\n\treturn le16_to_cpu(val);\n\n}\n\nint is_client_associated_to_ap(_adapter *padapter)\n{\n\tstruct mlme_ext_priv\t*pmlmeext;\n\tstruct mlme_ext_info\t*pmlmeinfo;\n\n\tif (!padapter)\n\t\treturn _FAIL;\n\n\tpmlmeext = &padapter->mlmeextpriv;\n\tpmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tif ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE))\n\t\treturn _TRUE;\n\telse\n\t\treturn _FAIL;\n}\n\nint is_client_associated_to_ibss(_adapter *padapter)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tif ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE))\n\t\treturn _TRUE;\n\telse\n\t\treturn _FAIL;\n}\n\nint is_IBSS_empty(_adapter *padapter)\n{\n\tint i;\n\tstruct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl;\n\n\tfor (i = 0; i < macid_ctl->num; i++) {\n\t\tif (!rtw_macid_is_used(macid_ctl, i))\n\t\t\tcontinue;\n\t\tif (!rtw_macid_is_iface_specific(macid_ctl, i, padapter))\n\t\t\tcontinue;\n\t\tif (!GET_H2CCMD_MSRRPT_PARM_OPMODE(&macid_ctl->h2c_msr[i]))\n\t\t\tcontinue;\n\t\tif (GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]) == H2C_MSR_ROLE_ADHOC)\n\t\t\treturn _FAIL;\n\t}\n\n\treturn _TRUE;\n}\n\nunsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval)\n{\n\tif ((bcn_interval << 2) < WAIT_FOR_BCN_TO_MIN)\n\t\treturn WAIT_FOR_BCN_TO_MIN;\n\telse if ((bcn_interval << 2) > WAIT_FOR_BCN_TO_MAX)\n\t\treturn WAIT_FOR_BCN_TO_MAX;\n\telse\n\t\treturn bcn_interval << 2;\n}\n\nvoid invalidate_cam_all(_adapter *padapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\t_irqL irqL;\n\tu8 val8 = 0;\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_CAM_INVALID_ALL, &val8);\n\n\t_enter_critical_bh(&cam_ctl->lock, &irqL);\n\trtw_sec_cam_map_clr_all(&cam_ctl->used);\n\t_rtw_memset(dvobj->cam_cache, 0, sizeof(struct sec_cam_ent) * SEC_CAM_ENT_NUM_SW_LIMIT);\n\t_exit_critical_bh(&cam_ctl->lock, &irqL);\n}\n\nvoid _clear_cam_entry(_adapter *padapter, u8 entry)\n{\n\tunsigned char null_sta[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};\n\tunsigned char null_key[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};\n\n\trtw_sec_write_cam_ent(padapter, entry, 0, null_sta, null_key);\n}\n\ninline void write_cam(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)\n{\n#ifdef CONFIG_WRITE_CACHE_ONLY\n\twrite_cam_cache(adapter, id , ctrl, mac, key);\n#else\n\trtw_sec_write_cam_ent(adapter, id, ctrl, mac, key);\n\twrite_cam_cache(adapter, id , ctrl, mac, key);\n#endif\n}\n\ninline void clear_cam_entry(_adapter *adapter, u8 id)\n{\n\t_clear_cam_entry(adapter, id);\n\tclear_cam_cache(adapter, id);\n}\n\ninline void write_cam_from_cache(_adapter *adapter, u8 id)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\t_irqL irqL;\n\tstruct sec_cam_ent cache;\n\n\t_enter_critical_bh(&cam_ctl->lock, &irqL);\n\t_rtw_memcpy(&cache, &dvobj->cam_cache[id], sizeof(struct sec_cam_ent));\n\t_exit_critical_bh(&cam_ctl->lock, &irqL);\n\n\trtw_sec_write_cam_ent(adapter, id, cache.ctrl, cache.mac, cache.key);\n}\nvoid write_cam_cache(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\t_irqL irqL;\n\n\t_enter_critical_bh(&cam_ctl->lock, &irqL);\n\n\tdvobj->cam_cache[id].ctrl = ctrl;\n\t_rtw_memcpy(dvobj->cam_cache[id].mac, mac, ETH_ALEN);\n\t_rtw_memcpy(dvobj->cam_cache[id].key, key, 16);\n\n\t_exit_critical_bh(&cam_ctl->lock, &irqL);\n}\n\nvoid clear_cam_cache(_adapter *adapter, u8 id)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\t_irqL irqL;\n\n\t_enter_critical_bh(&cam_ctl->lock, &irqL);\n\n\t_rtw_memset(&(dvobj->cam_cache[id]), 0, sizeof(struct sec_cam_ent));\n\n\t_exit_critical_bh(&cam_ctl->lock, &irqL);\n}\n\ninline bool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\n\tif (cam_ctl->sec_cap & cap)\n\t\treturn _TRUE;\n\treturn _FALSE;\n}\n\ninline void _rtw_camctl_set_flags(_adapter *adapter, u32 flags)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\n\tcam_ctl->flags |= flags;\n}\n\ninline void rtw_camctl_set_flags(_adapter *adapter, u32 flags)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\t_irqL irqL;\n\n\t_enter_critical_bh(&cam_ctl->lock, &irqL);\n\t_rtw_camctl_set_flags(adapter, flags);\n\t_exit_critical_bh(&cam_ctl->lock, &irqL);\n}\n\ninline void _rtw_camctl_clr_flags(_adapter *adapter, u32 flags)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\n\tcam_ctl->flags &= ~flags;\n}\n\ninline void rtw_camctl_clr_flags(_adapter *adapter, u32 flags)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\t_irqL irqL;\n\n\t_enter_critical_bh(&cam_ctl->lock, &irqL);\n\t_rtw_camctl_clr_flags(adapter, flags);\n\t_exit_critical_bh(&cam_ctl->lock, &irqL);\n}\n\ninline bool _rtw_camctl_chk_flags(_adapter *adapter, u32 flags)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\n\tif (cam_ctl->flags & flags)\n\t\treturn _TRUE;\n\treturn _FALSE;\n}\n\nvoid dump_sec_cam_map(void *sel, struct sec_cam_bmp *map, u8 max_num)\n{\n\tRTW_PRINT_SEL(sel, \"0x%08x\\n\", map->m0);\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)\n\tif (max_num && max_num > 32)\n\t\tRTW_PRINT_SEL(sel, \"0x%08x\\n\", map->m1);\n#endif\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)\n\tif (max_num && max_num > 64)\n\t\tRTW_PRINT_SEL(sel, \"0x%08x\\n\", map->m2);\n#endif\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)\n\tif (max_num && max_num > 96)\n\t\tRTW_PRINT_SEL(sel, \"0x%08x\\n\", map->m3);\n#endif\n}\n\ninline bool rtw_sec_camid_is_set(struct sec_cam_bmp *map, u8 id)\n{\n\tif (id < 32)\n\t\treturn map->m0 & BIT(id);\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)\n\telse if (id < 64)\n\t\treturn map->m1 & BIT(id - 32);\n#endif\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)\n\telse if (id < 96)\n\t\treturn map->m2 & BIT(id - 64);\n#endif\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)\n\telse if (id < 128)\n\t\treturn map->m3 & BIT(id - 96);\n#endif\n\telse\n\t\trtw_warn_on(1);\n\n\treturn 0;\n}\n\ninline void rtw_sec_cam_map_set(struct sec_cam_bmp *map, u8 id)\n{\n\tif (id < 32)\n\t\tmap->m0 |= BIT(id);\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)\n\telse if (id < 64)\n\t\tmap->m1 |= BIT(id - 32);\n#endif\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)\n\telse if (id < 96)\n\t\tmap->m2 |= BIT(id - 64);\n#endif\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)\n\telse if (id < 128)\n\t\tmap->m3 |= BIT(id - 96);\n#endif\n\telse\n\t\trtw_warn_on(1);\n}\n\ninline void rtw_sec_cam_map_clr(struct sec_cam_bmp *map, u8 id)\n{\n\tif (id < 32)\n\t\tmap->m0 &= ~BIT(id);\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)\n\telse if (id < 64)\n\t\tmap->m1 &= ~BIT(id - 32);\n#endif\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)\n\telse if (id < 96)\n\t\tmap->m2 &= ~BIT(id - 64);\n#endif\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)\n\telse if (id < 128)\n\t\tmap->m3 &= ~BIT(id - 96);\n#endif\n\telse\n\t\trtw_warn_on(1);\n}\n\ninline void rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map)\n{\n\tmap->m0 = 0;\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)\n\tmap->m1 = 0;\n#endif\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)\n\tmap->m2 = 0;\n#endif\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)\n\tmap->m3 = 0;\n#endif\n}\n\ninline bool rtw_sec_camid_is_drv_forbid(struct cam_ctl_t *cam_ctl, u8 id)\n{\n\tstruct sec_cam_bmp forbid_map;\n\n\tforbid_map.m0 = 0x00000ff0;\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)\n\tforbid_map.m1 = 0x00000000;\n#endif\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)\n\tforbid_map.m2 = 0x00000000;\n#endif\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)\n\tforbid_map.m3 = 0x00000000;\n#endif\n\n\tif (id < 32)\n\t\treturn forbid_map.m0 & BIT(id);\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)\n\telse if (id < 64)\n\t\treturn forbid_map.m1 & BIT(id - 32);\n#endif\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)\n\telse if (id < 96)\n\t\treturn forbid_map.m2 & BIT(id - 64);\n#endif\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)\n\telse if (id < 128)\n\t\treturn forbid_map.m3 & BIT(id - 96);\n#endif\n\telse\n\t\trtw_warn_on(1);\n\n\treturn 1;\n}\n\nbool _rtw_sec_camid_is_used(struct cam_ctl_t *cam_ctl, u8 id)\n{\n\tbool ret = _FALSE;\n\n\tif (id >= cam_ctl->num) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n#if 0 /* for testing */\n\tif (rtw_sec_camid_is_drv_forbid(cam_ctl, id)) {\n\t\tret = _TRUE;\n\t\tgoto exit;\n\t}\n#endif\n\n\tret = rtw_sec_camid_is_set(&cam_ctl->used, id);\n\nexit:\n\treturn ret;\n}\n\ninline bool rtw_sec_camid_is_used(struct cam_ctl_t *cam_ctl, u8 id)\n{\n\t_irqL irqL;\n\tbool ret;\n\n\t_enter_critical_bh(&cam_ctl->lock, &irqL);\n\tret = _rtw_sec_camid_is_used(cam_ctl, id);\n\t_exit_critical_bh(&cam_ctl->lock, &irqL);\n\n\treturn ret;\n}\nu8 rtw_get_sec_camid(_adapter *adapter, u8 max_bk_key_num, u8 *sec_key_id)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\tint i;\n\t_irqL irqL;\n\tu8 sec_cam_num = 0;\n\n\t_enter_critical_bh(&cam_ctl->lock, &irqL);\n\tfor (i = 0; i < cam_ctl->num; i++) {\n\t\tif (_rtw_sec_camid_is_used(cam_ctl, i)) {\n\t\t\tsec_key_id[sec_cam_num++] = i;\n\t\t\tif (sec_cam_num == max_bk_key_num)\n\t\t\t\tbreak;\n\t\t}\n\t}\n\t_exit_critical_bh(&cam_ctl->lock, &irqL);\n\n\treturn sec_cam_num;\n}\n\ninline bool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\tbool ret = _FALSE;\n\n\tif (cam_id >= cam_ctl->num) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (_rtw_sec_camid_is_used(cam_ctl, cam_id) == _FALSE)\n\t\tgoto exit;\n\n\tret = (dvobj->cam_cache[cam_id].ctrl & BIT6) ? _TRUE : _FALSE;\n\nexit:\n\treturn ret;\n}\n\ninline bool rtw_camid_is_gk(_adapter *adapter, u8 cam_id)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\t_irqL irqL;\n\tbool ret;\n\n\t_enter_critical_bh(&cam_ctl->lock, &irqL);\n\tret = _rtw_camid_is_gk(adapter, cam_id);\n\t_exit_critical_bh(&cam_ctl->lock, &irqL);\n\n\treturn ret;\n}\n\nbool cam_cache_chk(_adapter *adapter, u8 id, u8 *addr, s16 kid, s8 gk)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tbool ret = _FALSE;\n\n\tif (addr && _rtw_memcmp(dvobj->cam_cache[id].mac, addr, ETH_ALEN) == _FALSE)\n\t\tgoto exit;\n\tif (kid >= 0 && kid != (dvobj->cam_cache[id].ctrl & 0x03))\n\t\tgoto exit;\n\tif (gk != -1 && (gk ? _TRUE : _FALSE) != _rtw_camid_is_gk(adapter, id))\n\t\tgoto exit;\n\n\tret = _TRUE;\n\nexit:\n\treturn ret;\n}\n\ns16 _rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\tint i;\n\ts16 cam_id = -1;\n\n\tfor (i = 0; i < cam_ctl->num; i++) {\n\t\tif (cam_cache_chk(adapter, i, addr, kid, gk)) {\n\t\t\tcam_id = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (0) {\n\t\tif (addr)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" addr:\"MAC_FMT\" kid:%d, gk:%d, return cam_id:%d\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid, gk, cam_id);\n\t\telse\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" addr:%p kid:%d, gk:%d, return cam_id:%d\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), addr, kid, gk, cam_id);\n\t}\n\n\treturn cam_id;\n}\n\ns16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\t_irqL irqL;\n\ts16 cam_id = -1;\n\n\t_enter_critical_bh(&cam_ctl->lock, &irqL);\n\tcam_id = _rtw_camid_search(adapter, addr, kid, gk);\n\t_exit_critical_bh(&cam_ctl->lock, &irqL);\n\n\treturn cam_id;\n}\n\ns16 rtw_get_camid(_adapter *adapter, u8 *addr, s16 kid, u8 gk)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\tint i;\n#if 0 /* for testing */\n\tstatic u8 start_id = 0;\n#else\n\tu8 start_id = 0;\n#endif\n\ts16 cam_id = -1;\n\n\tif (addr == NULL) {\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" mac_address is NULL\\n\"\n\t\t\t  , FUNC_ADPT_ARG(adapter));\n\t\trtw_warn_on(1);\n\t\tgoto _exit;\n\t}\n\n\t/* find cam entry which has the same addr, kid (, gk bit) */\n\tif (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC) == _TRUE)\n\t\ti = _rtw_camid_search(adapter, addr, kid, gk);\n\telse\n\t\ti = _rtw_camid_search(adapter, addr, kid, -1);\n\n\tif (i >= 0) {\n\t\tcam_id = i;\n\t\tgoto _exit;\n\t}\n\n\tfor (i = 0; i < cam_ctl->num; i++) {\n\t\t/* bypass default key which is allocated statically */\n#ifndef CONFIG_CONCURRENT_MODE\n\t\tif (((i + start_id) % cam_ctl->num) < 4)\n\t\t\tcontinue;\n#endif\n\t\tif (_rtw_sec_camid_is_used(cam_ctl, ((i + start_id) % cam_ctl->num)) == _FALSE)\n\t\t\tbreak;\n\t}\n\n\tif (i == cam_ctl->num) {\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" %s key with \"MAC_FMT\" id:%u no room\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), gk ? \"group\" : \"pairwise\", MAC_ARG(addr), kid);\n\t\trtw_warn_on(1);\n\t\tgoto _exit;\n\t}\n\n\tcam_id = ((i + start_id) % cam_ctl->num);\n\tstart_id = ((i + start_id + 1) % cam_ctl->num);\n\n_exit:\n\treturn cam_id;\n}\n\ns16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, u8 gk, bool *used)\n{\n\tstruct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\t_irqL irqL;\n\ts16 cam_id = -1;\n\n\t*used = _FALSE;\n\n\t_enter_critical_bh(&cam_ctl->lock, &irqL);\n\n\tif ((((mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE))\n\t    && !sta) {\n\t\t/*\n\t\t* 1. non-STA mode WEP key\n\t\t* 2. group TX key\n\t\t*/\n#ifndef CONFIG_CONCURRENT_MODE\n\t\t/* static alloction to default key by key ID when concurrent is not defined */\n\t\tif (kid > 3) {\n\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" group key with invalid key id:%u\\n\"\n\t\t\t\t  , FUNC_ADPT_ARG(adapter), kid);\n\t\t\trtw_warn_on(1);\n\t\t\tgoto bitmap_handle;\n\t\t}\n\t\tcam_id = kid;\n#else\n\t\tu8 *addr = adapter_mac_addr(adapter);\n\n\t\tcam_id = rtw_get_camid(adapter, addr, kid, gk);\n\t\tif (1)\n\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" group key with \"MAC_FMT\" assigned cam_id:%u\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(addr), cam_id);\n#endif\n\t} else {\n\t\t/*\n\t\t* 1. STA mode WEP key\n\t\t* 2. STA mode group RX key\n\t\t* 3. sta key (pairwise, group RX)\n\t\t*/\n\t\tu8 *addr = sta ? sta->cmn.mac_addr : NULL;\n\n\t\tif (!sta) {\n\t\t\tif (!(mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) {\n\t\t\t\t/* bypass STA mode group key setting before connected(ex:WEP) because bssid is not ready */\n\t\t\t\tgoto bitmap_handle;\n\t\t\t}\n\t\t\taddr = get_bssid(&adapter->mlmepriv);/*A2*/\n\t\t}\n\t\tcam_id = rtw_get_camid(adapter, addr, kid, gk);\n\t}\n\n\nbitmap_handle:\n\tif (cam_id >= 0) {\n\t\t*used = _rtw_sec_camid_is_used(cam_ctl, cam_id);\n\t\trtw_sec_cam_map_set(&cam_ctl->used, cam_id);\n\t}\n\n\t_exit_critical_bh(&cam_ctl->lock, &irqL);\n\n\treturn cam_id;\n}\n\nvoid rtw_camid_set(_adapter *adapter, u8 cam_id)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\t_irqL irqL;\n\n\t_enter_critical_bh(&cam_ctl->lock, &irqL);\n\n\tif (cam_id < cam_ctl->num)\n\t\trtw_sec_cam_map_set(&cam_ctl->used, cam_id);\n\n\t_exit_critical_bh(&cam_ctl->lock, &irqL);\n}\n\nvoid rtw_camid_free(_adapter *adapter, u8 cam_id)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\t_irqL irqL;\n\n\t_enter_critical_bh(&cam_ctl->lock, &irqL);\n\n\tif (cam_id < cam_ctl->num)\n\t\trtw_sec_cam_map_clr(&cam_ctl->used, cam_id);\n\n\t_exit_critical_bh(&cam_ctl->lock, &irqL);\n}\n\n/*Must pause TX/RX before use this API*/\ninline void rtw_sec_cam_swap(_adapter *adapter, u8 cam_id_a, u8 cam_id_b)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\tstruct sec_cam_ent cache_a, cache_b;\n\t_irqL irqL;\n\tbool cam_a_used, cam_b_used;\n\n\tif (1)\n\t\tRTW_INFO(ADPT_FMT\" - sec_cam %d,%d swap\\n\", ADPT_ARG(adapter), cam_id_a, cam_id_b);\n\n\tif (cam_id_a == cam_id_b)\n\t\treturn;\n\n#ifdef CONFIG_CONCURRENT_MODE\n\trtw_mi_update_ap_bmc_camid(adapter, cam_id_a, cam_id_b);\n#endif\n\n\t/*setp-1. backup org cam_info*/\n\t_enter_critical_bh(&cam_ctl->lock, &irqL);\n\n\tcam_a_used = _rtw_sec_camid_is_used(cam_ctl, cam_id_a);\n\tcam_b_used = _rtw_sec_camid_is_used(cam_ctl, cam_id_b);\n\n\tif (cam_a_used)\n\t\t_rtw_memcpy(&cache_a, &dvobj->cam_cache[cam_id_a], sizeof(struct sec_cam_ent));\n\n\tif (cam_b_used)\n\t\t_rtw_memcpy(&cache_b, &dvobj->cam_cache[cam_id_b], sizeof(struct sec_cam_ent));\n\n\t_exit_critical_bh(&cam_ctl->lock, &irqL);\n\n\t/*setp-2. clean cam_info*/\n\tif (cam_a_used) {\n\t\trtw_camid_free(adapter, cam_id_a);\n\t\tclear_cam_entry(adapter, cam_id_a);\n\t}\n\tif (cam_b_used) {\n\t\trtw_camid_free(adapter, cam_id_b);\n\t\tclear_cam_entry(adapter, cam_id_b);\n\t}\n\n\t/*setp-3. set cam_info*/\n\tif (cam_a_used) {\n\t\twrite_cam(adapter, cam_id_b, cache_a.ctrl, cache_a.mac, cache_a.key);\n\t\trtw_camid_set(adapter, cam_id_b);\n\t}\n\n\tif (cam_b_used) {\n\t\twrite_cam(adapter, cam_id_a, cache_b.ctrl, cache_b.mac, cache_b.key);\n\t\trtw_camid_set(adapter, cam_id_a);\n\t}\n}\n\ns16 rtw_get_empty_cam_entry(_adapter *adapter, u8 start_camid)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\t_irqL irqL;\n\tint i;\n\ts16 cam_id = -1;\n\n\t_enter_critical_bh(&cam_ctl->lock, &irqL);\n\tfor (i = start_camid; i < cam_ctl->num; i++) {\n\t\tif (_FALSE == _rtw_sec_camid_is_used(cam_ctl, i)) {\n\t\t\tcam_id = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\t_exit_critical_bh(&cam_ctl->lock, &irqL);\n\n\treturn cam_id;\n}\nvoid rtw_clean_dk_section(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);\n\ts16 ept_cam_id;\n\tint i;\n\n\tfor (i = 0; i < 4; i++) {\n\t\tif (rtw_sec_camid_is_used(cam_ctl, i)) {\n\t\t\tept_cam_id = rtw_get_empty_cam_entry(adapter, 4);\n\t\t\tif (ept_cam_id > 0)\n\t\t\t\trtw_sec_cam_swap(adapter, i, ept_cam_id);\n\t\t}\n\t}\n}\nvoid rtw_clean_hw_dk_cam(_adapter *adapter)\n{\n\tint i;\n\n\tfor (i = 0; i < 4; i++)\n\t\trtw_sec_clr_cam_ent(adapter, i);\n\t\t/*_clear_cam_entry(adapter, i);*/\n}\n\nvoid flush_all_cam_entry(_adapter *padapter)\n{\n#ifdef CONFIG_CONCURRENT_MODE\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct security_priv *psecpriv = &padapter->securitypriv;\n\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {\n\t\tstruct sta_priv\t*pstapriv = &padapter->stapriv;\n\t\tstruct sta_info\t\t*psta;\n\n\t\tpsta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);\n\t\tif (psta) {\n\t\t\tif (psta->state & WIFI_AP_STATE) {\n\t\t\t\t/*clear cam when ap free per sta_info*/\n\t\t\t} else\n\t\t\t\trtw_clearstakey_cmd(padapter, psta, _FALSE);\n\t\t}\n\t} else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {\n#if 1\n\t\tint cam_id = -1;\n\t\tu8 *addr = adapter_mac_addr(padapter);\n\n\t\twhile ((cam_id = rtw_camid_search(padapter, addr, -1, -1)) >= 0) {\n\t\t\tRTW_PRINT(\"clear wep or group key for addr:\"MAC_FMT\", camid:%d\\n\", MAC_ARG(addr), cam_id);\n\t\t\tclear_cam_entry(padapter, cam_id);\n\t\t\trtw_camid_free(padapter, cam_id);\n\t\t}\n#else\n\t\t/* clear default key */\n\t\tint i, cam_id;\n\t\tu8 null_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};\n\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\tcam_id = rtw_camid_search(padapter, null_addr, i, -1);\n\t\t\tif (cam_id >= 0) {\n\t\t\t\tclear_cam_entry(padapter, cam_id);\n\t\t\t\trtw_camid_free(padapter, cam_id);\n\t\t\t}\n\t\t}\n\t\t/* clear default key related key search setting */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8 *)_FALSE);\n#endif\n\t}\n\n#else /*NON CONFIG_CONCURRENT_MODE*/\n\n\tinvalidate_cam_all(padapter);\n\t/* clear default key related key search setting */\n\trtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8 *)_FALSE);\n#endif\n}\n\n#if defined(CONFIG_P2P) && defined(CONFIG_WFD)\nvoid rtw_process_wfd_ie(_adapter *adapter, u8 *wfd_ie, u8 wfd_ielen, const char *tag)\n{\n\tstruct wifidirect_info *wdinfo = &adapter->wdinfo;\n\n\tu8 *attr_content;\n\tu32 attr_contentlen = 0;\n\n\tif (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))\n\t\treturn;\n\n\tRTW_INFO(\"[%s] Found WFD IE\\n\", tag);\n\tattr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen);\n\tif (attr_content && attr_contentlen) {\n\t\twdinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16(attr_content + 2);\n\t\tRTW_INFO(\"[%s] Peer PORT NUM = %d\\n\", tag, wdinfo->wfd_info->peer_rtsp_ctrlport);\n\t}\n}\n\nvoid rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag)\n{\n\tu8 *wfd_ie;\n\tu32\twfd_ielen;\n\n\tif (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))\n\t\treturn;\n\n\twfd_ie = rtw_get_wfd_ie(ies, ies_len, NULL, &wfd_ielen);\n\twhile (wfd_ie) {\n\t\trtw_process_wfd_ie(adapter, wfd_ie, wfd_ielen, tag);\n\t\twfd_ie = rtw_get_wfd_ie(wfd_ie + wfd_ielen, (ies + ies_len) - (wfd_ie + wfd_ielen), NULL, &wfd_ielen);\n\t}\n}\n#endif /* defined(CONFIG_P2P) && defined(CONFIG_WFD) */\n\nint WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs\tpIE)\n{\n\t/* struct registry_priv\t*pregpriv = &padapter->registrypriv; */\n\tstruct mlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tif (pmlmepriv->qospriv.qos_option == 0) {\n\t\tpmlmeinfo->WMM_enable = 0;\n\t\treturn _FALSE;\n\t}\n\n\tif (_rtw_memcmp(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element)))\n\t\treturn _FALSE;\n\telse\n\t\t_rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element));\n\tpmlmeinfo->WMM_enable = 1;\n\treturn _TRUE;\n\n#if 0\n\tif (pregpriv->wifi_spec == 1) {\n\t\tif (pmlmeinfo->WMM_enable == 1) {\n\t\t\t/* todo: compare the parameter set count & decide wheher to update or not */\n\t\t\treturn _FAIL;\n\t\t} else {\n\t\t\tpmlmeinfo->WMM_enable = 1;\n\t\t\t_rtw_rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element));\n\t\t\treturn _TRUE;\n\t\t}\n\t} else {\n\t\tpmlmeinfo->WMM_enable = 0;\n\t\treturn _FAIL;\n\t}\n#endif\n\n}\n\nvoid WMMOnAssocRsp(_adapter *padapter)\n{\n\tu8\tACI, ACM, AIFS, ECWMin, ECWMax, aSifsTime;\n\tu8\tacm_mask;\n\tu16\tTXOP;\n\tu32\tacParm, i;\n\tu32\tedca[4], inx[4];\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct xmit_priv\t\t*pxmitpriv = &padapter->xmitpriv;\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n#ifdef CONFIG_WMMPS_STA\n\tstruct mlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tstruct qos_priv\t*pqospriv = &pmlmepriv->qospriv;\n#endif /* CONFIG_WMMPS_STA */\t\n\n\tacm_mask = 0;\n\n\tif (is_supported_5g(pmlmeext->cur_wireless_mode) ||\n\t    (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))\n\t\taSifsTime = 16;\n\telse\n\t\taSifsTime = 10;\n\n\tif (pmlmeinfo->WMM_enable == 0) {\n\t\tpadapter->mlmepriv.acm_mask = 0;\n\n\t\tAIFS = aSifsTime + (2 * pmlmeinfo->slotTime);\n\n\t\tif (pmlmeext->cur_wireless_mode & (WIRELESS_11G | WIRELESS_11A)) {\n\t\t\tECWMin = 4;\n\t\t\tECWMax = 10;\n\t\t} else if (pmlmeext->cur_wireless_mode & WIRELESS_11B) {\n\t\t\tECWMin = 5;\n\t\t\tECWMax = 10;\n\t\t} else {\n\t\t\tECWMin = 4;\n\t\t\tECWMax = 10;\n\t\t}\n\n\t\tTXOP = 0;\n\t\tacParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));\n\n\t\tECWMin = 2;\n\t\tECWMax = 3;\n\t\tTXOP = 0x2f;\n\t\tacParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));\n\t} else {\n\t\tedca[0] = edca[1] = edca[2] = edca[3] = 0;\n\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\tACI = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 5) & 0x03;\n\t\t\tACM = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 4) & 0x01;\n\n\t\t\t/* AIFS = AIFSN * slot time + SIFS - r2t phy delay */\n\t\t\tAIFS = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN & 0x0f) * pmlmeinfo->slotTime + aSifsTime;\n\n\t\t\tECWMin = (pmlmeinfo->WMM_param.ac_param[i].CW & 0x0f);\n\t\t\tECWMax = (pmlmeinfo->WMM_param.ac_param[i].CW & 0xf0) >> 4;\n\t\t\tTXOP = le16_to_cpu(pmlmeinfo->WMM_param.ac_param[i].TXOP_limit);\n\n\t\t\tacParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);\n\n\t\t\tswitch (ACI) {\n\t\t\tcase 0x0:\n\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));\n\t\t\t\tacm_mask |= (ACM ? BIT(1) : 0);\n\t\t\t\tedca[XMIT_BE_QUEUE] = acParm;\n\t\t\t\tbreak;\n\n\t\t\tcase 0x1:\n\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));\n\t\t\t\t/* acm_mask |= (ACM? BIT(0):0); */\n\t\t\t\tedca[XMIT_BK_QUEUE] = acParm;\n\t\t\t\tbreak;\n\n\t\t\tcase 0x2:\n\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));\n\t\t\t\tacm_mask |= (ACM ? BIT(2) : 0);\n\t\t\t\tedca[XMIT_VI_QUEUE] = acParm;\n\t\t\t\tbreak;\n\n\t\t\tcase 0x3:\n\t\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));\n\t\t\t\tacm_mask |= (ACM ? BIT(3) : 0);\n\t\t\t\tedca[XMIT_VO_QUEUE] = acParm;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tRTW_INFO(\"WMM(%x): %x, %x\\n\", ACI, ACM, acParm);\n\t\t}\n\n\t\tif (padapter->registrypriv.acm_method == 1)\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_ACM_CTRL, (u8 *)(&acm_mask));\n\t\telse\n\t\t\tpadapter->mlmepriv.acm_mask = acm_mask;\n\n\t\tinx[0] = 0;\n\t\tinx[1] = 1;\n\t\tinx[2] = 2;\n\t\tinx[3] = 3;\n\n\t\tif (pregpriv->wifi_spec == 1) {\n\t\t\tu32\tj, tmp, change_inx = _FALSE;\n\n\t\t\t/* entry indx: 0->vo, 1->vi, 2->be, 3->bk. */\n\t\t\tfor (i = 0; i < 4; i++) {\n\t\t\t\tfor (j = i + 1; j < 4; j++) {\n\t\t\t\t\t/* compare CW and AIFS */\n\t\t\t\t\tif ((edca[j] & 0xFFFF) < (edca[i] & 0xFFFF))\n\t\t\t\t\t\tchange_inx = _TRUE;\n\t\t\t\t\telse if ((edca[j] & 0xFFFF) == (edca[i] & 0xFFFF)) {\n\t\t\t\t\t\t/* compare TXOP */\n\t\t\t\t\t\tif ((edca[j] >> 16) > (edca[i] >> 16))\n\t\t\t\t\t\t\tchange_inx = _TRUE;\n\t\t\t\t\t}\n\n\t\t\t\t\tif (change_inx) {\n\t\t\t\t\t\ttmp = edca[i];\n\t\t\t\t\t\tedca[i] = edca[j];\n\t\t\t\t\t\tedca[j] = tmp;\n\n\t\t\t\t\t\ttmp = inx[i];\n\t\t\t\t\t\tinx[i] = inx[j];\n\t\t\t\t\t\tinx[j] = tmp;\n\n\t\t\t\t\t\tchange_inx = _FALSE;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\tpxmitpriv->wmm_para_seq[i] = inx[i];\n\t\t\tRTW_INFO(\"wmm_para_seq(%d): %d\\n\", i, pxmitpriv->wmm_para_seq[i]);\n\t\t}\n\t\t\n#ifdef CONFIG_WMMPS_STA\n\t\t/* if AP supports UAPSD function, driver must set each uapsd TID to coresponding mac register 0x693 */\n\t\tif (pmlmeinfo->WMM_param.QoS_info & AP_SUPPORTED_UAPSD) {\n\t\t\tpqospriv->uapsd_ap_supported = 1;\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_UAPSD_TID, NULL);\n\t\t}\n#endif /* CONFIG_WMMPS_STA */\n\t}\n}\n\nstatic void bwmode_update_check(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)\n{\n#ifdef CONFIG_80211N_HT\n\tunsigned char\t new_bwmode;\n\tunsigned char  new_ch_offset;\n\tstruct HT_info_element\t*pHT_info;\n\tstruct mlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct registry_priv *pregistrypriv = &padapter->registrypriv;\n\tstruct ht_priv\t\t\t*phtpriv = &pmlmepriv->htpriv;\n\tu8\tcbw40_enable = 0;\n\n\tif (!pIE)\n\t\treturn;\n\n\tif (phtpriv->ht_option == _FALSE)\n\t\treturn;\n\n\tif (pmlmeext->cur_bwmode >= CHANNEL_WIDTH_80)\n\t\treturn;\n\n\tif (pIE->Length > sizeof(struct HT_info_element))\n\t\treturn;\n\n\tpHT_info = (struct HT_info_element *)pIE->data;\n\n\tif (hal_chk_bw_cap(padapter, BW_CAP_40M)) {\n\t\tif (pmlmeext->cur_channel > 14) {\n\t\t\tif (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))\n\t\t\t\tcbw40_enable = 1;\n\t\t} else {\n\t\t\tif (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))\n\t\t\t\tcbw40_enable = 1;\n\t\t}\n\t}\n\n\tif ((pHT_info->infos[0] & BIT(2)) && cbw40_enable) {\n\t\tnew_bwmode = CHANNEL_WIDTH_40;\n\n\t\tswitch (pHT_info->infos[0] & 0x3) {\n\t\tcase 1:\n\t\t\tnew_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\t\tbreak;\n\n\t\tcase 3:\n\t\t\tnew_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tnew_bwmode = CHANNEL_WIDTH_20;\n\t\t\tnew_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t\tbreak;\n\t\t}\n\t} else {\n\t\tnew_bwmode = CHANNEL_WIDTH_20;\n\t\tnew_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t}\n\n\n\tif ((new_bwmode != pmlmeext->cur_bwmode || new_ch_offset != pmlmeext->cur_ch_offset)\n\t    && new_bwmode < pmlmeext->cur_bwmode\n\t   ) {\n\t\tpmlmeinfo->bwmode_updated = _TRUE;\n\n\t\tpmlmeext->cur_bwmode = new_bwmode;\n\t\tpmlmeext->cur_ch_offset = new_ch_offset;\n\n\t\t/* update HT info also */\n\t\tHT_info_handler(padapter, pIE);\n\t} else\n\t\tpmlmeinfo->bwmode_updated = _FALSE;\n\n\n\tif (_TRUE == pmlmeinfo->bwmode_updated) {\n\t\tstruct sta_info *psta;\n\t\tWLAN_BSSID_EX\t*cur_network = &(pmlmeinfo->network);\n\t\tstruct sta_priv\t*pstapriv = &padapter->stapriv;\n\n\t\t/* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */\n\n\n\t\t/* update ap's stainfo */\n\t\tpsta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);\n\t\tif (psta) {\n\t\t\tstruct ht_priv\t*phtpriv_sta = &psta->htpriv;\n\n\t\t\tif (phtpriv_sta->ht_option) {\n\t\t\t\t/* bwmode\t\t\t\t */\n\t\t\t\tpsta->cmn.bw_mode = pmlmeext->cur_bwmode;\n\t\t\t\tphtpriv_sta->ch_offset = pmlmeext->cur_ch_offset;\n\t\t\t} else {\n\t\t\t\tpsta->cmn.bw_mode = CHANNEL_WIDTH_20;\n\t\t\t\tphtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t\t}\n\n\t\t\trtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta);\n\t\t}\n\n\t\t/* pmlmeinfo->bwmode_updated = _FALSE; */ /* bwmode_updated done, reset it! */\n\t}\n#endif /* CONFIG_80211N_HT */\n}\n\n#ifdef ROKU_PRIVATE\nvoid Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)\n{\n\tunsigned int\ti;\n\tstruct mlme_ext_priv\t\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tif (pIE == NULL)\n\t\treturn;\n\n\tfor (i = 0 ; i < pIE->Length; i++)\n\t\tpmlmeinfo->SupportedRates_infra_ap[i] = (pIE->data[i]);\n\n}\n\nvoid Extended_Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)\n{\n\tunsigned int i, j;\n\tstruct mlme_ext_priv\t\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tif (pIE == NULL)\n\t\treturn;\n\n\tif (pIE->Length > 0) {\n\t\tfor (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {\n\t\t\tif (pmlmeinfo->SupportedRates_infra_ap[i] == 0)\n\t\t\t\tbreak;\n\t\t}\n\t\tfor (j = 0; j < pIE->Length; j++)\n\t\t\tpmlmeinfo->SupportedRates_infra_ap[i+j] = (pIE->data[j]);\n\t}\n\n}\n\nvoid HT_get_ss_from_mcs_set(u8 *mcs_set, u8 *Rx_ss)\n{\n\tu8 i, j;\n\tu8 r_ss = 0, t_ss = 0;\n\n\tfor (i = 0; i < 4; i++) {\n\t\tif ((mcs_set[3-i] & 0xff) != 0x00) {\n\t\t\tr_ss = 4-i;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t*Rx_ss = r_ss;\n}\n\nvoid HT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)\n{\n\tunsigned int\ti;\n\tu8\tcur_stbc_cap_infra_ap = 0;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct ht_priv_infra_ap\t\t*phtpriv = &pmlmepriv->htpriv_infra_ap;\n\n\tstruct mlme_ext_priv\t\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tif (pIE == NULL)\n\t\treturn;\n\n\tpmlmeinfo->ht_vht_received |= BIT(0);\n\n\t/*copy MCS_SET*/\n\tfor (i = 3; i < 19; i++)\n\t\tphtpriv->MCS_set_infra_ap[i-3] = (pIE->data[i]);\n\n\t/*get number of stream from mcs set*/\n\tHT_get_ss_from_mcs_set(phtpriv->MCS_set_infra_ap, &phtpriv->Rx_ss_infra_ap);\n\n\tphtpriv->rx_highest_data_rate_infra_ap = le16_to_cpu(GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(pIE->data));\n\n\tphtpriv->ldpc_cap_infra_ap = GET_HT_CAP_ELE_LDPC_CAP(pIE->data);\n\n\tif (GET_HT_CAP_ELE_RX_STBC(pIE->data))\n\t\tSET_FLAG(cur_stbc_cap_infra_ap, STBC_HT_ENABLE_RX);\n\tif (GET_HT_CAP_ELE_TX_STBC(pIE->data))\n\t\tSET_FLAG(cur_stbc_cap_infra_ap, STBC_HT_ENABLE_TX);\n\tphtpriv->stbc_cap_infra_ap = cur_stbc_cap_infra_ap;\n\n\t/*store ap info SGI 20m 40m*/\n\tphtpriv->sgi_20m_infra_ap = GET_HT_CAP_ELE_SHORT_GI20M(pIE->data);\n\tphtpriv->sgi_40m_infra_ap = GET_HT_CAP_ELE_SHORT_GI40M(pIE->data);\n\n\t/*store ap info for supported channel bandwidth*/\n\tphtpriv->channel_width_infra_ap = GET_HT_CAP_ELE_CHL_WIDTH(pIE->data);\n}\n#endif /* ROKU_PRIVATE */\n\nvoid HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)\n{\n#ifdef CONFIG_80211N_HT\n\tunsigned int\ti;\n\tu8\trf_type = RF_1T1R;\n\tu8\tmax_AMPDU_len, min_MPDU_spacing;\n\tu8\tcur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0, tx_nss = 0;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct ht_priv\t\t\t*phtpriv = &pmlmepriv->htpriv;\n#ifdef CONFIG_DISABLE_MCS13TO15\n\tstruct registry_priv\t*pregistrypriv = &padapter->registrypriv;\n#endif\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);\n\n\tif (pIE == NULL)\n\t\treturn;\n\n\tif (phtpriv->ht_option == _FALSE)\n\t\treturn;\n\n\tpmlmeinfo->HT_caps_enable = 1;\n\n\tfor (i = 0; i < (pIE->Length); i++) {\n\t\tif (i != 2) {\n\t\t\t/*\tCommented by Albert 2010/07/12 */\n\t\t\t/*\tGot the endian issue here. */\n\t\t\tpmlmeinfo->HT_caps.u.HT_cap[i] &= (pIE->data[i]);\n\t\t} else {\n\t\t\t/* AMPDU Parameters field */\n\n\t\t\t/* Get MIN of MAX AMPDU Length Exp */\n\t\t\tif ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3) > (pIE->data[i] & 0x3))\n\t\t\t\tmax_AMPDU_len = (pIE->data[i] & 0x3);\n\t\t\telse\n\t\t\t\tmax_AMPDU_len = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3);\n\n\t\t\t/* Get MAX of MIN MPDU Start Spacing */\n\t\t\tif ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) > (pIE->data[i] & 0x1c))\n\t\t\t\tmin_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c);\n\t\t\telse\n\t\t\t\tmin_MPDU_spacing = (pIE->data[i] & 0x1c);\n\n\t\t\tpmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para = max_AMPDU_len | min_MPDU_spacing;\n\t\t}\n\t}\n\n\t/*\tCommented by Albert 2010/07/12 */\n\t/*\tHave to handle the endian issue after copying. */\n\t/*\tHT_ext_caps didn't be used yet.\t */\n\tpmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info);\n\tpmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps);\n\n\t/* update the MCS set */\n\tfor (i = 0; i < 16; i++)\n\t\tpmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i];\n\n\trtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));\n\ttx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);\n\n\tswitch (tx_nss) {\n\tcase 1:\n\t\tset_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R);\n\t\tbreak;\n\tcase 2:\n\t\t#ifdef CONFIG_DISABLE_MCS13TO15\n\t\tif (pmlmeext->cur_bwmode == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1)\n\t\t\tset_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R_13TO15_OFF);\n\t\telse\n\t\t#endif\n\t\t\tset_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R);\n\t\tbreak;\n\tcase 3:\n\t\tset_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R);\n\t\tbreak;\n\tcase 4:\n\t\tset_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_4R);\n\t\tbreak;\n\tdefault:\n\t\tRTW_WARN(\"rf_type:%d or tx_nss:%u is not expected\\n\", rf_type, hal_spec->tx_nss_num);\n\t}\n\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {\n\t\t/* Config STBC setting */\n\t\tif (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(pIE->data)) {\n\t\t\tSET_FLAG(cur_stbc_cap, STBC_HT_ENABLE_TX);\n\t\t\tRTW_INFO(\"Enable HT Tx STBC !\\n\");\n\t\t}\n\t\tphtpriv->stbc_cap = cur_stbc_cap;\n\n#ifdef CONFIG_BEAMFORMING\n\t\t/* Config Tx beamforming setting */\n\t\tif (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&\n\t\t    GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) {\n\t\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);\n\t\t\t/* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/\n\t\t\tSET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6);\n\t\t}\n\n\t\tif (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&\n\t\t    GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) {\n\t\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);\n\t\t\t/* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/\n\t\t\tSET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4);\n\t\t}\n\t\tphtpriv->beamform_cap = cur_beamform_cap;\n\t\tif (cur_beamform_cap)\n\t\t\tRTW_INFO(\"AP HT Beamforming Cap = 0x%02X\\n\", cur_beamform_cap);\n#endif /*CONFIG_BEAMFORMING*/\n\t} else {\n\t\t/*WIFI_STATION_STATEorI_ADHOC_STATE or WIFI_ADHOC_MASTER_STATE*/\n\t\t/* Config LDPC Coding Capability */\n\t\tif (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX) && GET_HT_CAP_ELE_LDPC_CAP(pIE->data)) {\n\t\t\tSET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX));\n\t\t\tRTW_INFO(\"Enable HT Tx LDPC!\\n\");\n\t\t}\n\t\tphtpriv->ldpc_cap = cur_ldpc_cap;\n\n\t\t/* Config STBC setting */\n\t\tif (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(pIE->data)) {\n\t\t\tSET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX));\n\t\t\tRTW_INFO(\"Enable HT Tx STBC!\\n\");\n\t\t}\n\t\tphtpriv->stbc_cap = cur_stbc_cap;\n\n#ifdef CONFIG_BEAMFORMING\n#ifdef RTW_BEAMFORMING_VERSION_2\n\t\t/* Config beamforming setting */\n\t\tif (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&\n\t\t    GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) {\n\t\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);\n\t\t\t/* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/\n\t\t\tSET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6);\n\t\t}\n\n\t\tif (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&\n\t\t    GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) {\n\t\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);\n\t\t\t/* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/\n\t\t\tSET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4);\n\t\t}\n#else /* !RTW_BEAMFORMING_VERSION_2 */\n\t\t/* Config Tx beamforming setting */\n\t\tif (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&\n\t\t    GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) {\n\t\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);\n\t\t\t/* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/\n\t\t\tSET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6);\n\t\t}\n\n\t\tif (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&\n\t\t    GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) {\n\t\t\tSET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);\n\t\t\t/* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/\n\t\t\tSET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4);\n\t\t}\n#endif /* !RTW_BEAMFORMING_VERSION_2 */\n\t\tphtpriv->beamform_cap = cur_beamform_cap;\n\t\tif (cur_beamform_cap)\n\t\t\tRTW_INFO(\"Client HT Beamforming Cap = 0x%02X\\n\", cur_beamform_cap);\n#endif /*CONFIG_BEAMFORMING*/\n\t}\n\n#endif /* CONFIG_80211N_HT */\n}\n\nvoid HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)\n{\n#ifdef CONFIG_80211N_HT\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct ht_priv\t\t\t*phtpriv = &pmlmepriv->htpriv;\n\n\tif (pIE == NULL)\n\t\treturn;\n\n\tif (phtpriv->ht_option == _FALSE)\n\t\treturn;\n\n\n\tif (pIE->Length > sizeof(struct HT_info_element))\n\t\treturn;\n\n\tpmlmeinfo->HT_info_enable = 1;\n\t_rtw_memcpy(&(pmlmeinfo->HT_info), pIE->data, pIE->Length);\n#endif /* CONFIG_80211N_HT */\n\treturn;\n}\n\nvoid HTOnAssocRsp(_adapter *padapter)\n{\n\tunsigned char\t\tmax_AMPDU_len;\n\tunsigned char\t\tmin_MPDU_spacing;\n\t/* struct registry_priv\t *pregpriv = &padapter->registrypriv; */\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\tif ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable))\n\t\tpmlmeinfo->HT_enable = 1;\n\telse {\n\t\tpmlmeinfo->HT_enable = 0;\n\t\t/* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */\n\t\treturn;\n\t}\n\n\t/* handle A-MPDU parameter field */\n\t/*\n\t\tAMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k\n\t\tAMPDU_para [4:2]:Min MPDU Start Spacing\n\t*/\n\tmax_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;\n\n\tmin_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2;\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing));\n#ifdef CONFIG_80211N_HT\n\trtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len));\n#endif /* CONFIG_80211N_HT */\n#if 0 /* move to rtw_update_ht_cap() */\n\tif ((pregpriv->bw_mode > 0) &&\n\t    (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) &&\n\t    (pmlmeinfo->HT_info.infos[0] & BIT(2))) {\n\t\t/* switch to the 40M Hz mode accoring to the AP */\n\t\tpmlmeext->cur_bwmode = CHANNEL_WIDTH_40;\n\t\tswitch ((pmlmeinfo->HT_info.infos[0] & 0x3)) {\n\t\tcase EXTCHNL_OFFSET_UPPER:\n\t\t\tpmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\t\tbreak;\n\n\t\tcase EXTCHNL_OFFSET_LOWER:\n\t\t\tpmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tpmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t\tbreak;\n\t\t}\n\t}\n#endif\n\n\t/* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */\n\n#if 0 /* move to rtw_update_ht_cap() */\n\t/*  */\n\t/* Config SM Power Save setting */\n\t/*  */\n\tpmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2;\n\tif (pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) {\n#if 0\n\t\tu8 i;\n\t\t/* update the MCS rates */\n\t\tfor (i = 0; i < 16; i++)\n\t\t\tpmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];\n#endif\n\t\tRTW_INFO(\"%s(): WLAN_HT_CAP_SM_PS_STATIC\\n\", __FUNCTION__);\n\t}\n\n\t/*  */\n\t/* Config current HT Protection mode. */\n\t/*  */\n\tpmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3;\n#endif\n\n}\n\nvoid ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tif (pIE->Length > 1)\n\t\treturn;\n\n\tpmlmeinfo->ERP_enable = 1;\n\t_rtw_memcpy(&(pmlmeinfo->ERP_IE), pIE->data, pIE->Length);\n}\n\nvoid VCS_update(_adapter *padapter, struct sta_info *psta)\n{\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tswitch (pregpriv->vrtl_carrier_sense) { /* 0:off 1:on 2:auto */\n\tcase 0: /* off */\n\t\tpsta->rtsen = 0;\n\t\tpsta->cts2self = 0;\n\t\tbreak;\n\n\tcase 1: /* on */\n\t\tif (pregpriv->vcs_type == 1) { /* 1:RTS/CTS 2:CTS to self */\n\t\t\tpsta->rtsen = 1;\n\t\t\tpsta->cts2self = 0;\n\t\t} else {\n\t\t\tpsta->rtsen = 0;\n\t\t\tpsta->cts2self = 1;\n\t\t}\n\t\tbreak;\n\n\tcase 2: /* auto */\n\tdefault:\n\t\tif (((pmlmeinfo->ERP_enable) && (pmlmeinfo->ERP_IE & BIT(1)))\n\t\t\t/*||(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/\n\t\t) {\n\t\t\tif (pregpriv->vcs_type == 1) {\n\t\t\t\tpsta->rtsen = 1;\n\t\t\t\tpsta->cts2self = 0;\n\t\t\t} else {\n\t\t\t\tpsta->rtsen = 0;\n\t\t\t\tpsta->cts2self = 1;\n\t\t\t}\n\t\t} else {\n\t\t\tpsta->rtsen = 0;\n\t\t\tpsta->cts2self = 0;\n\t\t}\n\t\tbreak;\n\t}\n}\n\nvoid\tupdate_ldpc_stbc_cap(struct sta_info *psta)\n{\n#ifdef CONFIG_80211N_HT\n\n#ifdef CONFIG_80211AC_VHT\n\tif (psta->vhtpriv.vht_option) {\n\t\tif (TEST_FLAG(psta->vhtpriv.ldpc_cap, LDPC_VHT_ENABLE_TX))\n\t\t\tpsta->cmn.ldpc_en = VHT_LDPC_EN;\n\t\telse\n\t\t\tpsta->cmn.ldpc_en = 0;\n\n\t\tif (TEST_FLAG(psta->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX))\n\t\t\tpsta->cmn.stbc_en = VHT_STBC_EN;\n\t\telse\n\t\t\tpsta->cmn.stbc_en = 0;\n\t} else\n#endif /* CONFIG_80211AC_VHT */\n\t\tif (psta->htpriv.ht_option) {\n\t\t\tif (TEST_FLAG(psta->htpriv.ldpc_cap, LDPC_HT_ENABLE_TX))\n\t\t\t\tpsta->cmn.ldpc_en = HT_LDPC_EN;\n\t\t\telse\n\t\t\t\tpsta->cmn.ldpc_en = 0;\n\n\t\t\tif (TEST_FLAG(psta->htpriv.stbc_cap, STBC_HT_ENABLE_TX))\n\t\t\t\tpsta->cmn.stbc_en = HT_STBC_EN;\n\t\t\telse\n\t\t\t\tpsta->cmn.stbc_en = 0;\n\t\t} else {\n\t\t\tpsta->cmn.ldpc_en = 0;\n\t\t\tpsta->cmn.stbc_en = 0;\n\t\t}\n\n#endif /* CONFIG_80211N_HT */\n}\n\nint check_ielen(u8 *start, uint len)\n{\n\tint left = len;\n\tu8 *pos = start;\n\tu8 id, elen;\n\n\twhile (left >= 2) {\n\t\tid = *pos++;\n\t\telen = *pos++;\n\t\tleft -= 2;\n\n\t\tif (elen > left) {\n\t\t\tRTW_INFO(\"IEEE 802.11 element parse failed (id=%d elen=%d left=%lu)\\n\",\n\t\t\t\t\tid, elen, (unsigned long) left);\n\t\t\treturn _FALSE;\n\t\t}\n\t\tif ((id == WLAN_EID_VENDOR_SPECIFIC) && (elen < 3))\n\t\t\t\treturn _FALSE;\n\n\t\tleft -= elen;\n\t\tpos += elen;\n\t}\n\tif (left)\n\t\treturn _FALSE;\n\n\treturn _TRUE;\n}\n\nint validate_beacon_len(u8 *pframe, u32 len)\n{\n\tu8 ie_offset = _BEACON_IE_OFFSET_ + sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tif (len < ie_offset) {\n\t\tRTW_INFO(\"%s: incorrect beacon length(%d)\\n\", __func__, len);\n\t\treturn _FALSE;\n\t}\n\n\tif (check_ielen(pframe + ie_offset, len - ie_offset) == _FALSE)\n\t\treturn _FALSE;\n\n\treturn _TRUE;\n}\n\n\nu8 support_rate_ranges[] = {\n\tIEEE80211_CCK_RATE_1MB,\n\tIEEE80211_CCK_RATE_2MB,\n\tIEEE80211_CCK_RATE_5MB,\n\tIEEE80211_CCK_RATE_11MB,\n\tIEEE80211_OFDM_RATE_6MB,\n\tIEEE80211_OFDM_RATE_9MB,\n\tIEEE80211_OFDM_RATE_12MB,\n\tIEEE80211_OFDM_RATE_18MB,\n\tIEEE80211_OFDM_RATE_24MB,\n\tIEEE80211_OFDM_RATE_36MB,\n\tIEEE80211_OFDM_RATE_48MB,\n\tIEEE80211_OFDM_RATE_54MB,\n\tIEEE80211_PBCC_RATE_22MB,\n    IEEE80211_PBCC_RATE_33MB,\n};\n\ninline bool match_ranges(u16 EID, u32 value)\n{\n\tint i;\n\tint nr_range;\n\n\tswitch (EID) {\n\tcase _EXT_SUPPORTEDRATES_IE_:\n\tcase _SUPPORTEDRATES_IE_:\n\t\tnr_range = sizeof(support_rate_ranges)/sizeof(u8);\n\t\tfor (i = 0; i < nr_range; i++) {\n\t\t\t/*\tclear bit7 before searching.\t*/\n\t\t\tvalue &= ~BIT(7);\n\t\t\tif (value == support_rate_ranges[i])\n\t\t\t\treturn _TRUE;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t};\n\treturn _FALSE;\n}\n\n/*\n * rtw_validate_value: validate the IE contain.\n *\n *\tInput : \n *\t\tEID : Element ID\n *\t\tp\t: IE buffer (without EID & length)\n *\t\tlen\t: IE length\n *\treturn: \n * \t\t_TRUE\t: All Values are validated.\n *\t\t_FALSE\t: At least one value is NOT validated.\n */\nbool rtw_validate_value(u16 EID, u8 *p, u16 len)\n{\n\tu8 rate;\n\tu32 i, nr_val;\n\n\tswitch (EID) {\n\tcase _EXT_SUPPORTEDRATES_IE_:\n\tcase _SUPPORTEDRATES_IE_:\n\t\tnr_val = len;\n\t\tfor (i=0; i<nr_val; i++) {\n\t\t\trate = *(p+i);\n\t\t\tif (match_ranges(EID, rate) == _FALSE)\n\t\t\t\treturn _FALSE;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t};\n\treturn _TRUE;\n}\n\nbool is_hidden_ssid(char *ssid, int len)\n{\n\treturn len == 0 || is_all_null(ssid, len) == _TRUE;\n}\n\ninline bool hidden_ssid_ap(WLAN_BSSID_EX *snetwork)\n{\n\treturn is_hidden_ssid(snetwork->Ssid.Ssid, snetwork->Ssid.SsidLength);\n}\n\n/*\n\tGet SSID if this ilegal frame(probe resp) comes from a hidden SSID AP.\n\tUpdate the SSID to the corresponding pnetwork in scan queue.\n*/\nvoid rtw_absorb_ssid_ifneed(_adapter *padapter, WLAN_BSSID_EX *bssid, u8 *pframe)\n{\n\tstruct wlan_network *scanned = NULL;\n\tWLAN_BSSID_EX\t*snetwork;\n\tu8 ie_offset, *p=NULL, *next_ie=NULL, *mac = get_addr2_ptr(pframe);\n\tsint len, ssid_len_ori;\n\tu32 remain_len = 0;\n\tu8 backupIE[MAX_IE_SZ];\n\tu16 subtype = get_frame_sub_type(pframe);\n\t_irqL irqL;\n\n\tif ((!bssid) || (!pframe))\n\t\treturn;\n\n\tif (subtype == WIFI_BEACON) {\n\t\tbssid->Reserved[0] = BSS_TYPE_BCN;\n\t\tie_offset = _BEACON_IE_OFFSET_;\n\t} else {\n\t\t/* FIXME : more type */\n\t\tif (subtype == WIFI_PROBERSP) {\n\t\t\tie_offset = _PROBERSP_IE_OFFSET_;\n\t\t\tbssid->Reserved[0] = BSS_TYPE_PROB_RSP;\n\t\t} else if (subtype == WIFI_PROBEREQ) {\n\t\t\tie_offset = _PROBEREQ_IE_OFFSET_;\n\t\t\tbssid->Reserved[0] = BSS_TYPE_PROB_REQ;\n\t\t} else {\n\t\t\tbssid->Reserved[0] = BSS_TYPE_UNDEF;\n\t\t\tie_offset = _FIXED_IE_LENGTH_;\n\t\t}\n\t}\n\t\n\t_enter_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL);\n\tscanned = _rtw_find_network(&padapter->mlmepriv.scanned_queue, mac);\n\tif (!scanned) {\n\t\t_exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL);\n\t\treturn;\n\t}\n\n\tsnetwork = &(scanned->network);\n\t/* scan queue records as Hidden SSID && Input frame is NOT Hidden SSID\t*/\n\tif (hidden_ssid_ap(snetwork) && !hidden_ssid_ap(bssid)) {\n\t\tp = rtw_get_ie(snetwork->IEs+ie_offset, _SSID_IE_, &ssid_len_ori, snetwork->IELength-ie_offset);\n\t\tif (!p) {\n\t\t\t_exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL);\n\t\t\treturn;\n\t\t}\n\t\tnext_ie = p + 2 + ssid_len_ori;\n\t\tremain_len = snetwork->IELength - (next_ie - snetwork->IEs);\n\t\tscanned->network.Ssid.SsidLength = bssid->Ssid.SsidLength;\n\t\t_rtw_memcpy(scanned->network.Ssid.Ssid, bssid->Ssid.Ssid, bssid->Ssid.SsidLength);\n\n\t\t//update pnetwork->ssid, pnetwork->ssidlen\n\t\t_rtw_memcpy(backupIE, next_ie, remain_len);\n\t\t*(p+1) = bssid->Ssid.SsidLength;\n\t\t_rtw_memcpy(p+2, bssid->Ssid.Ssid, bssid->Ssid.SsidLength);\n\t\t_rtw_memcpy(p+2+bssid->Ssid.SsidLength, backupIE, remain_len);\n\t\tsnetwork->IELength += bssid->Ssid.SsidLength;\n\t}\n\t_exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL);\n}\n\n#ifdef DBG_RX_BCN\nvoid rtw_debug_rx_bcn(_adapter *adapter, u8 *pframe, u32 packet_len)\n{\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info *mlmeinfo = &(pmlmeext->mlmext_info);\n\tu16 sn = ((struct rtw_ieee80211_hdr_3addr *)pframe)->seq_ctl >> 4;\n\tu64 tsf, tsf_offset;\n\tu8 dtim_cnt, dtim_period, tim_bmap, tim_pvbit;\n\n\tupdate_TSF(pmlmeext, pframe, packet_len);\n\ttsf = pmlmeext->TSFValue;\n\ttsf_offset = rtw_modular64(pmlmeext->TSFValue, (mlmeinfo->bcn_interval * 1024));\n\n\t/*get TIM IE*/\n\t/*DTIM Count*/\n\tdtim_cnt = pmlmeext->tim[0];\n\t/*DTIM Period*/\n\tdtim_period = pmlmeext->tim[1];\n\t/*Bitmap*/\n\ttim_bmap = pmlmeext->tim[2];\n\t/*Partial VBitmap AID 0 ~ 7*/\n\ttim_pvbit = pmlmeext->tim[3];\n\n\tRTW_INFO(\"[BCN] SN-%d, TSF-%lld(us), offset-%lld, bcn_interval-%d DTIM-%d[%d] bitmap-0x%02x-0x%02x\\n\",\n\t\tsn, tsf, tsf_offset, mlmeinfo->bcn_interval, dtim_period, dtim_cnt, tim_bmap, tim_pvbit);\n}\n#endif\n\n/*\n * rtw_get_bcn_keys: get beacon keys from recv frame\n *\n * TODO:\n *\tWLAN_EID_COUNTRY\n *\tWLAN_EID_ERP_INFO\n *\tWLAN_EID_CHANNEL_SWITCH\n *\tWLAN_EID_PWR_CONSTRAINT\n */\nint rtw_get_bcn_keys(ADAPTER *Adapter, u8 *pframe, u32 packet_len,\n\t\t     struct beacon_keys *recv_beacon)\n{\n\tint left;\n\tu16 capability;\n\tunsigned char *pos;\n\tstruct rtw_ieee802_11_elems elems;\n\n\t_rtw_memset(recv_beacon, 0, sizeof(*recv_beacon));\n\n\t/* checking capabilities */\n\tcapability = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 10));\n\n\t/* checking IEs */\n\tleft = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_;\n\tpos = pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_;\n\tif (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed)\n\t\treturn _FALSE;\n\n\tif (elems.ht_capabilities) {\n\t\tif (elems.ht_capabilities_len != 26)\n\t\t\treturn _FALSE;\n\t}\n\n\tif (elems.ht_operation) {\n\t\tif (elems.ht_operation_len != 22)\n\t\t\treturn _FALSE;\n\t}\n\n\tif (elems.vht_capabilities) {\n\t\tif (elems.vht_capabilities_len != 12)\n\t\t\treturn _FALSE;\n\t}\n\n\tif (elems.vht_operation) {\n\t\tif (elems.vht_operation_len != 5)\n\t\t\treturn _FALSE;\n\t}\n\n\tif (rtw_ies_get_supported_rate(pos, left, recv_beacon->rate_set, &recv_beacon->rate_num) == _FAIL)\n\t\treturn _FALSE;\n\n\tif (cckratesonly_included(recv_beacon->rate_set, recv_beacon->rate_num) == _TRUE)\n\t\trecv_beacon->proto_cap |= PROTO_CAP_11B;\n\telse if (cckrates_included(recv_beacon->rate_set, recv_beacon->rate_num) == _TRUE)\n\t\trecv_beacon->proto_cap |= PROTO_CAP_11B | PROTO_CAP_11G;\n\telse\n\t\trecv_beacon->proto_cap |= PROTO_CAP_11G;\n\n\tif (elems.ht_capabilities && elems.ht_operation)\n\t\trecv_beacon->proto_cap |= PROTO_CAP_11N;\n\n\tif (elems.vht_capabilities && elems.vht_operation)\n\t\trecv_beacon->proto_cap |= PROTO_CAP_11AC;\n\n\t/* check bw and channel offset */\n\trtw_ies_get_chbw(pos, left, &recv_beacon->ch, &recv_beacon->bw, &recv_beacon->offset, 1, 1);\n\tif (!recv_beacon->ch) {\n\t\t/* we don't find channel IE, so don't check it */\n\t\t/* RTW_INFO(\"Oops: %s we don't find channel IE, so don't check it\\n\", __func__); */\n\t\trecv_beacon->ch = Adapter->mlmeextpriv.cur_channel;\n\t}\n\n\t/* checking SSID */\n\tif (elems.ssid) {\n\t\tif (elems.ssid_len > sizeof(recv_beacon->ssid))\n\t\t\treturn _FALSE;\n\n\t\t_rtw_memcpy(recv_beacon->ssid, elems.ssid, elems.ssid_len);\n\t\trecv_beacon->ssid_len = elems.ssid_len;\n\t}\n\n\t/* checking RSN first */\n\tif (elems.rsn_ie && elems.rsn_ie_len) {\n\t\trecv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA2;\n\t\trtw_parse_wpa2_ie(elems.rsn_ie - 2, elems.rsn_ie_len + 2,\n\t\t\t&recv_beacon->group_cipher, &recv_beacon->pairwise_cipher,\n\t\t\t\t  &recv_beacon->akm, NULL);\n\t}\n\t/* checking WPA secon */\n\telse if (elems.wpa_ie && elems.wpa_ie_len) {\n\t\trecv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA;\n\t\trtw_parse_wpa_ie(elems.wpa_ie - 2, elems.wpa_ie_len + 2,\n\t\t\t&recv_beacon->group_cipher, &recv_beacon->pairwise_cipher,\n\t\t\t\t &recv_beacon->akm);\n\t} else if (capability & BIT(4))\n\t\trecv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WEP;\n\n\tif (elems.tim && elems.tim_len) {\n\t\tstruct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;\n\n\t\t#ifdef DBG_RX_BCN\n\t\t_rtw_memcpy(pmlmeext->tim, elems.tim, 4);\n\t\t#endif\n\t\tpmlmeext->dtim = elems.tim[1];\n\t}\n\n\treturn _TRUE;\n}\n\nvoid rtw_dump_bcn_keys(void *sel, struct beacon_keys *recv_beacon)\n{\n\tu8 ssid[IW_ESSID_MAX_SIZE + 1];\n\n\t_rtw_memcpy(ssid, recv_beacon->ssid, recv_beacon->ssid_len);\n\tssid[recv_beacon->ssid_len] = '\\0';\n\n\tRTW_PRINT_SEL(sel, \"ssid = %s (len = %u)\\n\", ssid, recv_beacon->ssid_len);\n\tRTW_PRINT_SEL(sel, \"ch = %u,%u,%u\\n\"\n\t\t, recv_beacon->ch, recv_beacon->bw, recv_beacon->offset);\n\tRTW_PRINT_SEL(sel, \"proto_cap = 0x%02x\\n\", recv_beacon->proto_cap);\n\tRTW_MAP_DUMP_SEL(sel, \"rate_set = \"\n\t\t, recv_beacon->rate_set, recv_beacon->rate_num);\n\tRTW_PRINT_SEL(sel, \"sec = %d, group = 0x%x, pair = 0x%x, akm = 0x%08x\\n\"\n\t\t, recv_beacon->encryp_protocol, recv_beacon->group_cipher\n\t\t, recv_beacon->pairwise_cipher, recv_beacon->akm);\n}\n\nint rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len)\n{\n#define BCNKEY_VERIFY_PROTO_CAP 0\n#define BCNKEY_VERIFY_WHOLE_RATE_SET 0\n\n\tu8 *pbssid = GetAddr3Ptr(pframe);\n\tstruct mlme_priv *pmlmepriv = &Adapter->mlmepriv;\n\tstruct wlan_network *cur_network = &(Adapter->mlmepriv.cur_network);\n\tstruct beacon_keys *cur_beacon = &pmlmepriv->cur_beacon_keys;\n\tstruct beacon_keys recv_beacon;\n\tint ret = 0;\n\n\tif (is_client_associated_to_ap(Adapter) == _FALSE)\n\t\tgoto exit_success;\n\n\tif (rtw_get_bcn_keys(Adapter, pframe, packet_len, &recv_beacon) == _FALSE)\n\t\tgoto exit_success; /* parsing failed => broken IE */\n\n#ifdef DBG_RX_BCN\n\trtw_debug_bcn(Adapter, pframe, packet_len);\n#endif\n\n\t/* hidden ssid, replace with current beacon ssid directly */\n\tif (is_hidden_ssid(recv_beacon.ssid, recv_beacon.ssid_len)) {\n\t\t_rtw_memcpy(recv_beacon.ssid, pmlmepriv->cur_beacon_keys.ssid,\n\t\t\t    pmlmepriv->cur_beacon_keys.ssid_len);\n\t\trecv_beacon.ssid_len = pmlmepriv->cur_beacon_keys.ssid_len;\n\t}\n\n#ifdef CONFIG_BCN_CNT_CONFIRM_HDL\n\tif (_rtw_memcmp(&recv_beacon, cur_beacon, sizeof(recv_beacon)) == _TRUE)\n\t\tpmlmepriv->new_beacon_cnts = 0;\n\telse if ((pmlmepriv->new_beacon_cnts == 0) ||\n\t\t_rtw_memcmp(&recv_beacon, &pmlmepriv->new_beacon_keys, sizeof(recv_beacon)) == _FALSE) {\n\t\tRTW_DBG(\"%s: start new beacon (seq=%d)\\n\", __func__, GetSequence(pframe));\n\n\t\tif (pmlmepriv->new_beacon_cnts == 0) {\n\t\t\tRTW_ERR(\"%s: cur beacon key\\n\", __func__);\n\t\t\tRTW_DBG_EXPR(rtw_dump_bcn_keys(RTW_DBGDUMP, cur_beacon));\n\t\t}\n\n\t\tRTW_DBG(\"%s: new beacon key\\n\", __func__);\n\t\tRTW_DBG_EXPR(rtw_dump_bcn_keys(RTW_DBGDUMP, &recv_beacon));\n\n\t\t_rtw_memcpy(&pmlmepriv->new_beacon_keys, &recv_beacon, sizeof(recv_beacon));\n\t\tpmlmepriv->new_beacon_cnts = 1;\n\t} else {\n\t\tRTW_DBG(\"%s: new beacon again (seq=%d)\\n\", __func__, GetSequence(pframe));\n\t\tpmlmepriv->new_beacon_cnts++;\n\t}\n\n\t/* if counter >= max, it means beacon is changed really */\n\tif (pmlmepriv->new_beacon_cnts >= new_bcn_max)\n#else\n\tif (_rtw_memcmp(&recv_beacon, cur_beacon, sizeof(recv_beacon)) == _FALSE)\n#endif\n\t{\n\t\tstruct beacon_keys tmp_beacon;\n\n\t\tRTW_INFO(FUNC_ADPT_FMT\" new beacon occur!!\\n\", FUNC_ADPT_ARG(Adapter));\n\t\tRTW_INFO(FUNC_ADPT_FMT\" cur beacon key:\\n\", FUNC_ADPT_ARG(Adapter));\n\t\trtw_dump_bcn_keys(RTW_DBGDUMP, cur_beacon);\n\t\tRTW_INFO(FUNC_ADPT_FMT\" new beacon key:\\n\", FUNC_ADPT_ARG(Adapter));\n\t\trtw_dump_bcn_keys(RTW_DBGDUMP, &recv_beacon);\n\n\t\tif (!rtw_is_chbw_grouped(cur_beacon->ch, cur_beacon->bw, cur_beacon->offset\n\t\t\t\t, recv_beacon.ch, recv_beacon.bw, recv_beacon.offset))\n\t\t\tgoto exit;\n\n\t\t_rtw_memcpy(&tmp_beacon, cur_beacon, sizeof(tmp_beacon));\n\n\t\t/* check fields excluding below */\n\t\ttmp_beacon.ch = recv_beacon.ch;\n\t\ttmp_beacon.bw = recv_beacon.bw;\n\t\ttmp_beacon.offset = recv_beacon.offset;\n\t\tif (!BCNKEY_VERIFY_PROTO_CAP)\n\t\t\ttmp_beacon.proto_cap = recv_beacon.proto_cap;\n\t\tif (!BCNKEY_VERIFY_WHOLE_RATE_SET) {\n\t\t\ttmp_beacon.rate_num = recv_beacon.rate_num;\n\t\t\t_rtw_memcpy(tmp_beacon.rate_set, recv_beacon.rate_set, 12);\n\t\t}\n\t\tif (_rtw_memcmp(&tmp_beacon, &recv_beacon, sizeof(recv_beacon)) == _FALSE)\n\t\t\tgoto exit;\n\n\t\t_rtw_memcpy(cur_beacon, &recv_beacon, sizeof(recv_beacon));\n\t\t#ifdef CONFIG_BCN_CNT_CONFIRM_HDL\n\t\tpmlmepriv->new_beacon_cnts = 0;\n\t\t#endif\n\t}\n\nexit_success:\n\tret = 1;\n\nexit:\n\treturn ret;\n}\n\nvoid update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta_info *psta)\n{\n\tunsigned int i;\n\tunsigned int len;\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\n#ifdef CONFIG_TDLS\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\tu8 tdls_prohibited[] = { 0x00, 0x00, 0x00, 0x00, 0x10 }; /* bit(38): TDLS_prohibited */\n#endif /* CONFIG_TDLS */\n\n\tlen = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN);\n\n\tfor (i = 0; i < len;) {\n\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i);\n\n\t\tswitch (pIE->ElementID) {\n\t\tcase _VENDOR_SPECIFIC_IE_:\n\t\t\t/* to update WMM paramter set while receiving beacon */\n\t\t\tif (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6) && pIE->Length == WLAN_WMM_LEN)\t/* WMM */\n\t\t\t\t(WMM_param_handler(padapter, pIE)) ? report_wmm_edca_update(padapter) : 0;\n\n\t\t\tbreak;\n\n\t\tcase _HT_EXTRA_INFO_IE_:\t/* HT info */\n\t\t\t/* HT_info_handler(padapter, pIE); */\n\t\t\tbwmode_update_check(padapter, pIE);\n\t\t\tbreak;\n#ifdef CONFIG_80211AC_VHT\n\t\tcase EID_OpModeNotification:\n\t\t\trtw_process_vht_op_mode_notify(padapter, pIE->data, psta);\n\t\t\tbreak;\n#endif /* CONFIG_80211AC_VHT */\n\t\tcase _ERPINFO_IE_:\n\t\t\tERP_IE_handler(padapter, pIE);\n\t\t\tVCS_update(padapter, psta);\n\t\t\tbreak;\n\n#ifdef CONFIG_TDLS\n\t\tcase _EXT_CAP_IE_:\n\t\t\tif (check_ap_tdls_prohibited(pIE->data, pIE->Length) == _TRUE)\n\t\t\t\tptdlsinfo->ap_prohibited = _TRUE;\n\t\t\tif (check_ap_tdls_ch_switching_prohibited(pIE->data, pIE->Length) == _TRUE)\n\t\t\t\tptdlsinfo->ch_switch_prohibited = _TRUE;\n\t\t\tbreak;\n#endif /* CONFIG_TDLS */\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\ti += (pIE->Length + 2);\n\t}\n}\n\n#ifdef CONFIG_DFS\nvoid process_csa_ie(_adapter *padapter, u8 *ies, uint ies_len)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tunsigned int i;\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\tu8 ch = 0;\n\n\t/* TODO: compare with scheduling CSA */\n\tif (rfctl->csa_ch)\n\t\treturn;\n\n\tfor (i = 0; i + 1 < ies_len;) {\n\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(ies + i);\n\n\t\tswitch (pIE->ElementID) {\n\t\tcase _CH_SWTICH_ANNOUNCE_:\n\t\t\tch = *(pIE->data + 1);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\ti += (pIE->Length + 2);\n\t}\n\n\tif (ch != 0) {\n\t\trfctl->csa_ch = ch;\n\t\tif (rtw_set_csa_cmd(padapter) != _SUCCESS)\n\t\t\trfctl->csa_ch = 0;\n\t}\n}\n#endif /* CONFIG_DFS */\n\nvoid parsing_eapol_packet(_adapter *padapter, u8 *key_payload, struct sta_info *psta, u8 trx_type)\n{\n\tstruct security_priv *psecuritypriv = &(padapter->securitypriv);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct sta_priv *pstapriv = &(padapter->stapriv);\n\tstruct ieee802_1x_hdr *hdr;\n\tstruct wpa_eapol_key *key;\n\tu16 key_info, key_data_length;\n\tchar *trx_msg = trx_type ? \"send\" : \"recv\";\n\n\thdr = (struct ieee802_1x_hdr *) key_payload;\n\n\t /* WPS - eapol start packet */\n\tif (hdr->type == 1 && hdr->length == 0) {\n\t\tRTW_INFO(\"%s eapol start packet\\n\", trx_msg);\n\t\treturn;\n\t}\n\n\tif (hdr->type == 0) { /* WPS - eapol packet */\n\t\tRTW_INFO(\"%s eapol packet\\n\", trx_msg);\n\t\treturn;\n\t}\n\n\tkey = (struct wpa_eapol_key *) (hdr + 1);\n\tkey_info = be16_to_cpu(*((u16 *)(key->key_info)));\n\tkey_data_length = be16_to_cpu(*((u16 *)(key->key_data_length)));\n\n\tif (!(key_info & WPA_KEY_INFO_KEY_TYPE)) { /* WPA group key handshake */\n\t\tif (key_info & WPA_KEY_INFO_ACK) {\n\t\t\tRTW_PRINT(\"%s eapol packet - WPA Group Key 1/2\\n\", trx_msg);\n\t\t} else {\n\t\t\tRTW_PRINT(\"%s eapol packet - WPA Group Key 2/2\\n\", trx_msg);\n\n\t\t\t/* WPA key-handshake has completed */\n\t\t\tif (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPAPSK)\n\t\t\t\tpsta->state &= (~WIFI_UNDER_KEY_HANDSHAKE);\n\t\t}\n\t} else if (key_info & WPA_KEY_INFO_MIC) {\n\t\tif (key_data_length == 0)\n\t\t\tRTW_PRINT(\"%s eapol packet 4/4\\n\", trx_msg);\n\t\telse if (key_info & WPA_KEY_INFO_ACK)\n\t\t\tRTW_PRINT(\"%s eapol packet 3/4\\n\", trx_msg);\n\t\telse\n\t\t\tRTW_PRINT(\"%s eapol packet 2/4\\n\", trx_msg);\n\t} else {\n\t\tRTW_PRINT(\"%s eapol packet 1/4\\n\", trx_msg);\n\t}\n\n}\n\nunsigned int is_ap_in_tkip(_adapter *padapter)\n{\n\tu32 i;\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t\t*cur_network = &(pmlmeinfo->network);\n\n\tif (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) {\n\t\tfor (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) {\n\t\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i);\n\n\t\t\tswitch (pIE->ElementID) {\n\t\t\tcase _VENDOR_SPECIFIC_IE_:\n\t\t\t\tif ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) && (_rtw_memcmp((pIE->data + 12), WPA_TKIP_CIPHER, 4)))\n\t\t\t\t\treturn _TRUE;\n\t\t\t\tbreak;\n\n\t\t\tcase _RSN_IE_2_:\n\t\t\t\tif (_rtw_memcmp((pIE->data + 8), RSN_TKIP_CIPHER, 4))\n\t\t\t\t\treturn _TRUE;\n\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\ti += (pIE->Length + 2);\n\t\t}\n\n\t\treturn _FALSE;\n\t} else\n\t\treturn _FALSE;\n\n}\n\nunsigned int should_forbid_n_rate(_adapter *padapter)\n{\n\tu32 i;\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tWLAN_BSSID_EX  *cur_network = &pmlmepriv->cur_network.network;\n\n\tif (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) {\n\t\tfor (i = sizeof(NDIS_802_11_FIXED_IEs); i < cur_network->IELength;) {\n\t\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(cur_network->IEs + i);\n\n\t\t\tswitch (pIE->ElementID) {\n\t\t\tcase _VENDOR_SPECIFIC_IE_:\n\t\t\t\tif (_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4) &&\n\t\t\t\t    ((_rtw_memcmp((pIE->data + 12), WPA_CIPHER_SUITE_CCMP, 4)) ||\n\t\t\t\t     (_rtw_memcmp((pIE->data + 16), WPA_CIPHER_SUITE_CCMP, 4))))\n\t\t\t\t\treturn _FALSE;\n\t\t\t\tbreak;\n\n\t\t\tcase _RSN_IE_2_:\n\t\t\t\tif ((_rtw_memcmp((pIE->data + 8), RSN_CIPHER_SUITE_CCMP, 4))  ||\n\t\t\t\t    (_rtw_memcmp((pIE->data + 12), RSN_CIPHER_SUITE_CCMP, 4)))\n\t\t\t\t\treturn _FALSE;\n\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\ti += (pIE->Length + 2);\n\t\t}\n\n\t\treturn _TRUE;\n\t} else\n\t\treturn _FALSE;\n\n}\n\n\nunsigned int is_ap_in_wep(_adapter *padapter)\n{\n\tu32 i;\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t\t*cur_network = &(pmlmeinfo->network);\n\n\tif (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) {\n\t\tfor (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) {\n\t\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i);\n\n\t\t\tswitch (pIE->ElementID) {\n\t\t\tcase _VENDOR_SPECIFIC_IE_:\n\t\t\t\tif (_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4))\n\t\t\t\t\treturn _FALSE;\n\t\t\t\tbreak;\n\n\t\t\tcase _RSN_IE_2_:\n\t\t\t\treturn _FALSE;\n\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\ti += (pIE->Length + 2);\n\t\t}\n\n\t\treturn _TRUE;\n\t} else\n\t\treturn _FALSE;\n\n}\n\nint wifirate2_ratetbl_inx(unsigned char rate);\nint wifirate2_ratetbl_inx(unsigned char rate)\n{\n\tint\tinx = 0;\n\trate = rate & 0x7f;\n\n\tswitch (rate) {\n\tcase 54*2:\n\t\tinx = 11;\n\t\tbreak;\n\n\tcase 48*2:\n\t\tinx = 10;\n\t\tbreak;\n\n\tcase 36*2:\n\t\tinx = 9;\n\t\tbreak;\n\n\tcase 24*2:\n\t\tinx = 8;\n\t\tbreak;\n\n\tcase 18*2:\n\t\tinx = 7;\n\t\tbreak;\n\n\tcase 12*2:\n\t\tinx = 6;\n\t\tbreak;\n\n\tcase 9*2:\n\t\tinx = 5;\n\t\tbreak;\n\n\tcase 6*2:\n\t\tinx = 4;\n\t\tbreak;\n\n\tcase 11*2:\n\t\tinx = 3;\n\t\tbreak;\n\tcase 11:\n\t\tinx = 2;\n\t\tbreak;\n\n\tcase 2*2:\n\t\tinx = 1;\n\t\tbreak;\n\n\tcase 1*2:\n\t\tinx = 0;\n\t\tbreak;\n\n\t}\n\treturn inx;\n}\n\nunsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz)\n{\n\tunsigned int i, num_of_rate;\n\tunsigned int mask = 0;\n\n\tnum_of_rate = (ptn_sz > NumRates) ? NumRates : ptn_sz;\n\n\tfor (i = 0; i < num_of_rate; i++) {\n\t\tif ((*(ptn + i)) & 0x80)\n\t\t\tmask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i));\n\t}\n\treturn mask;\n}\n\nunsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz)\n{\n\tunsigned int i, num_of_rate;\n\tunsigned int mask = 0;\n\n\tnum_of_rate = (ptn_sz > NumRates) ? NumRates : ptn_sz;\n\n\tfor (i = 0; i < num_of_rate; i++)\n\t\tmask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i));\n\n\treturn mask;\n}\n\nint support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode)\n{\n\tunsigned char\t\t\t\t\tbit_offset;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tif (!(pmlmeinfo->HT_enable))\n\t\treturn _FAIL;\n\n\tbit_offset = (bwmode & CHANNEL_WIDTH_40) ? 6 : 5;\n\n\tif (pHT_caps->u.HT_cap_element.HT_caps_info & (0x1 << bit_offset))\n\t\treturn _SUCCESS;\n\telse\n\t\treturn _FAIL;\n}\n\nunsigned char get_highest_rate_idx(u64 mask)\n{\n\tint i;\n\tunsigned char rate_idx = 0;\n\n\tfor (i = 63; i >= 0; i--) {\n\t\tif ((mask >> i) & 0x01) {\n\t\t\trate_idx = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn rate_idx;\n}\nunsigned char get_lowest_rate_idx_ex(u64 mask, int start_bit)\n{\n\tint i;\n\tunsigned char rate_idx = 0;\n\n\tfor (i = start_bit; i < 64; i++) {\n\t\tif ((mask >> i) & 0x01) {\n\t\t\trate_idx = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn rate_idx;\n}\n\nvoid Update_RA_Entry(_adapter *padapter, struct sta_info *psta)\n{\n\trtw_hal_update_ra_mask(psta);\n}\n\nvoid set_sta_rate(_adapter *padapter, struct sta_info *psta)\n{\n\t/* rate adaptive\t */\n\trtw_hal_update_ra_mask(psta);\n}\n\n/* Update RRSR and Rate for USERATE */\nvoid update_tx_basic_rate(_adapter *padapter, u8 wirelessmode)\n{\n\tNDIS_802_11_RATES_EX\tsupported_rates;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info\t*pwdinfo = &padapter->wdinfo;\n\n\t/*\tAdded by Albert 2011/03/22 */\n\t/*\tIn the P2P mode, the driver should not support the b mode. */\n\t/*\tSo, the Tx packet shouldn't use the CCK rate */\n\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))\n\t\treturn;\n#endif /* CONFIG_P2P */\n\n\t_rtw_memset(supported_rates, 0, NDIS_802_11_LENGTH_RATES_EX);\n\n\t/* clear B mod if current channel is in 5G band, avoid tx cck rate in 5G band. */\n\tif (pmlmeext->cur_channel > 14)\n\t\twirelessmode &= ~(WIRELESS_11B);\n\n\tif ((wirelessmode & WIRELESS_11B) && (wirelessmode == WIRELESS_11B))\n\t\t_rtw_memcpy(supported_rates, rtw_basic_rate_cck, 4);\n\telse if (wirelessmode & WIRELESS_11B)\n\t\t_rtw_memcpy(supported_rates, rtw_basic_rate_mix, 7);\n\telse\n\t\t_rtw_memcpy(supported_rates, rtw_basic_rate_ofdm, 3);\n\n\tif (wirelessmode & WIRELESS_11B)\n\t\tupdate_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB);\n\telse\n\t\tupdate_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB);\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, supported_rates);\n}\n\nunsigned char check_assoc_AP(u8 *pframe, uint len)\n{\n\tunsigned int\ti;\n\tPNDIS_802_11_VARIABLE_IEs\tpIE;\n\n\tfor (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;) {\n\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i);\n\n\t\tswitch (pIE->ElementID) {\n\t\tcase _VENDOR_SPECIFIC_IE_:\n\t\t\tif ((_rtw_memcmp(pIE->data, ARTHEROS_OUI1, 3)) || (_rtw_memcmp(pIE->data, ARTHEROS_OUI2, 3))) {\n\t\t\t\tRTW_INFO(\"link to Artheros AP\\n\");\n\t\t\t\treturn HT_IOT_PEER_ATHEROS;\n\t\t\t} else if ((_rtw_memcmp(pIE->data, BROADCOM_OUI1, 3))\n\t\t\t\t   || (_rtw_memcmp(pIE->data, BROADCOM_OUI2, 3))\n\t\t\t\t|| (_rtw_memcmp(pIE->data, BROADCOM_OUI3, 3))) {\n\t\t\t\tRTW_INFO(\"link to Broadcom AP\\n\");\n\t\t\t\treturn HT_IOT_PEER_BROADCOM;\n\t\t\t} else if (_rtw_memcmp(pIE->data, MARVELL_OUI, 3)) {\n\t\t\t\tRTW_INFO(\"link to Marvell AP\\n\");\n\t\t\t\treturn HT_IOT_PEER_MARVELL;\n\t\t\t} else if (_rtw_memcmp(pIE->data, RALINK_OUI, 3)) {\n\t\t\t\tRTW_INFO(\"link to Ralink AP\\n\");\n\t\t\t\treturn HT_IOT_PEER_RALINK;\n\t\t\t} else if (_rtw_memcmp(pIE->data, CISCO_OUI, 3)) {\n\t\t\t\tRTW_INFO(\"link to Cisco AP\\n\");\n\t\t\t\treturn HT_IOT_PEER_CISCO;\n\t\t\t} else if (_rtw_memcmp(pIE->data, REALTEK_OUI, 3)) {\n\t\t\t\tu32\tVender = HT_IOT_PEER_REALTEK;\n\n\t\t\t\tif (pIE->Length >= 5) {\n\t\t\t\t\tif (pIE->data[4] == 1) {\n\t\t\t\t\t\t/* if(pIE->data[5] & RT_HT_CAP_USE_LONG_PREAMBLE) */\n\t\t\t\t\t\t/*\tbssDesc->BssHT.RT2RT_HT_Mode |= RT_HT_CAP_USE_LONG_PREAMBLE; */\n\n\t\t\t\t\t\tif (pIE->data[5] & RT_HT_CAP_USE_92SE) {\n\t\t\t\t\t\t\t/* bssDesc->BssHT.RT2RT_HT_Mode |= RT_HT_CAP_USE_92SE; */\n\t\t\t\t\t\t\tVender = HT_IOT_PEER_REALTEK_92SE;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t\tif (pIE->data[5] & RT_HT_CAP_USE_SOFTAP)\n\t\t\t\t\t\tVender = HT_IOT_PEER_REALTEK_SOFTAP;\n\n\t\t\t\t\tif (pIE->data[4] == 2) {\n\t\t\t\t\t\tif (pIE->data[6] & RT_HT_CAP_USE_JAGUAR_BCUT) {\n\t\t\t\t\t\t\tVender = HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP;\n\t\t\t\t\t\t\tRTW_INFO(\"link to Realtek JAGUAR_BCUTAP\\n\");\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif (pIE->data[6] & RT_HT_CAP_USE_JAGUAR_CCUT) {\n\t\t\t\t\t\t\tVender = HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP;\n\t\t\t\t\t\t\tRTW_INFO(\"link to Realtek JAGUAR_CCUTAP\\n\");\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tRTW_INFO(\"link to Realtek AP\\n\");\n\t\t\t\treturn Vender;\n\t\t\t} else if (_rtw_memcmp(pIE->data, AIRGOCAP_OUI, 3)) {\n\t\t\t\tRTW_INFO(\"link to Airgo Cap\\n\");\n\t\t\t\treturn HT_IOT_PEER_AIRGO;\n\t\t\t} else\n\t\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\ti += (pIE->Length + 2);\n\t}\n\n\tRTW_INFO(\"link to new AP\\n\");\n\treturn HT_IOT_PEER_UNKNOWN;\n}\n\nvoid get_assoc_AP_Vendor(char *vendor, u8 assoc_AP_vendor)\n{\n\tswitch (assoc_AP_vendor) {\n\t\n\tcase HT_IOT_PEER_UNKNOWN:\n\tsprintf(vendor, \"%s\", \"unknown\");\n\tbreak;\n\n\tcase HT_IOT_PEER_REALTEK:\n\tcase HT_IOT_PEER_REALTEK_92SE:\n\tcase HT_IOT_PEER_REALTEK_SOFTAP:\n\tcase HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP:\n\tcase HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP:\n\n\tsprintf(vendor, \"%s\", \"Realtek\");\n\tbreak;\n\n\tcase HT_IOT_PEER_BROADCOM:\n\tsprintf(vendor, \"%s\", \"Broadcom\");\n\tbreak;\n\n\tcase HT_IOT_PEER_MARVELL:\n\tsprintf(vendor, \"%s\", \"Marvell\");\n\tbreak;\n\n\tcase HT_IOT_PEER_RALINK:\n\tsprintf(vendor, \"%s\", \"Ralink\");\n\tbreak;\n\n\tcase HT_IOT_PEER_CISCO:\n\tsprintf(vendor, \"%s\", \"Cisco\");\n\tbreak;\n\n\tcase HT_IOT_PEER_AIRGO:\n\tsprintf(vendor, \"%s\", \"Airgo\");\n\tbreak;\n\n\tcase HT_IOT_PEER_ATHEROS:\n\tsprintf(vendor, \"%s\", \"Atheros\");\n\tbreak;\n\n\tdefault:\n\tsprintf(vendor, \"%s\", \"unkown\");\n\tbreak;\n\t}\n\n}\n#ifdef CONFIG_RTS_FULL_BW\nvoid rtw_parse_sta_vendor_ie_8812(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len)\n{\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\tunsigned char REALTEK_OUI[] = {0x00,0xe0, 0x4c};\n\tu8 *p;\n\tint i;\n\n\tp = rtw_get_ie_ex(tlv_ies, tlv_ies_len, WLAN_EID_VENDOR_SPECIFIC, REALTEK_OUI, 3, NULL, NULL);\n\tif (!p)\n\t\tgoto exit;\n\telse {\n\t\tif(*(p+1) > 6 ) {\n\n\t\t\tif(*(p+6) != 2)\n\t\t\t\tgoto exit;\n\t\t\t\n\t\t\tif(*(p+8) == RT_HT_CAP_USE_JAGUAR_BCUT)\n\t\t\t\tsta->vendor_8812 = TRUE;\n\t\t\telse if (*(p+8) == RT_HT_CAP_USE_JAGUAR_CCUT)\n\t\t\t\tsta->vendor_8812 = TRUE;\n\t\t}\n\t}\nexit:\n\treturn;\n}\n#endif/*CONFIG_RTS_FULL_BW*/\n\n#ifdef CONFIG_80211AC_VHT\nunsigned char get_vht_mu_bfer_cap(u8 *pframe, uint len)\n{\n\tunsigned int i;\n\tunsigned int mu_bfer=0;\n\tPNDIS_802_11_VARIABLE_IEs pIE;\n\n\tfor (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;) {\n\t\tpIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i);\n\n\t\tswitch (pIE->ElementID) {\n\n\t\tcase EID_VHTCapability:\n\t\t\tmu_bfer = GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t\ti += (pIE->Length + 2);\n\t}\n\treturn mu_bfer;\n}\n#endif\n\nvoid update_capinfo(PADAPTER Adapter, u16 updateCap)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &Adapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tBOOLEAN\t\tShortPreamble;\n\n\t/* Check preamble mode, 2005.01.06, by rcnjko. */\n\t/* Mark to update preamble value forever, 2008.03.18 by lanhsin */\n\t/* if( pMgntInfo->RegPreambleMode == PREAMBLE_AUTO ) */\n\t{\n\n\t\tif (updateCap & cShortPreamble) {\n\t\t\t/* Short Preamble */\n\t\t\tif (pmlmeinfo->preamble_mode != PREAMBLE_SHORT) { /* PREAMBLE_LONG or PREAMBLE_AUTO */\n\t\t\t\tShortPreamble = _TRUE;\n\t\t\t\tpmlmeinfo->preamble_mode = PREAMBLE_SHORT;\n\t\t\t\trtw_hal_set_hwreg(Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble);\n\t\t\t}\n\t\t} else {\n\t\t\t/* Long Preamble */\n\t\t\tif (pmlmeinfo->preamble_mode != PREAMBLE_LONG) { /* PREAMBLE_SHORT or PREAMBLE_AUTO */\n\t\t\t\tShortPreamble = _FALSE;\n\t\t\t\tpmlmeinfo->preamble_mode = PREAMBLE_LONG;\n\t\t\t\trtw_hal_set_hwreg(Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble);\n\t\t\t}\n\t\t}\n\t}\n\n\tif (updateCap & cIBSS) {\n\t\t/* Filen: See 802.11-2007 p.91 */\n\t\tpmlmeinfo->slotTime = NON_SHORT_SLOT_TIME;\n\t} else {\n\t\t/* Filen: See 802.11-2007 p.90 */\n\t\tif (pmlmeext->cur_wireless_mode & (WIRELESS_11_24N | WIRELESS_11A | WIRELESS_11_5N | WIRELESS_11AC))\n\t\t\tpmlmeinfo->slotTime = SHORT_SLOT_TIME;\n\t\telse if (pmlmeext->cur_wireless_mode & (WIRELESS_11G)) {\n\t\t\tif ((updateCap & cShortSlotTime) /* && (!(pMgntInfo->pHTInfo->RT2RT_HT_Mode & RT_HT_CAP_USE_LONG_PREAMBLE)) */) {\n\t\t\t\t/* Short Slot Time */\n\t\t\t\tpmlmeinfo->slotTime = SHORT_SLOT_TIME;\n\t\t\t} else {\n\t\t\t\t/* Long Slot Time */\n\t\t\t\tpmlmeinfo->slotTime = NON_SHORT_SLOT_TIME;\n\t\t\t}\n\t\t} else {\n\t\t\t/* B Mode */\n\t\t\tpmlmeinfo->slotTime = NON_SHORT_SLOT_TIME;\n\t\t}\n\t}\n\n\trtw_hal_set_hwreg(Adapter, HW_VAR_SLOT_TIME, &pmlmeinfo->slotTime);\n\n}\n\n/*\n* set adapter.mlmeextpriv.mlmext_info.HT_enable\n* set adapter.mlmeextpriv.cur_wireless_mode\n* set SIFS register\n* set mgmt tx rate\n*/\nvoid update_wireless_mode(_adapter *padapter)\n{\n\tint ratelen, network_type = 0;\n\tu32 SIFS_Timer;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t\t*cur_network = &(pmlmeinfo->network);\n\tunsigned char\t\t\t*rate = cur_network->SupportedRates;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n#endif /* CONFIG_P2P */\n\n\tratelen = rtw_get_rateset_len(cur_network->SupportedRates);\n\n\tif ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable))\n\t\tpmlmeinfo->HT_enable = 1;\n\n\tif (pmlmeext->cur_channel > 14) {\n\t\tif (pmlmeinfo->VHT_enable)\n\t\t\tnetwork_type = WIRELESS_11AC;\n\t\telse if (pmlmeinfo->HT_enable)\n\t\t\tnetwork_type = WIRELESS_11_5N;\n\n\t\tnetwork_type |= WIRELESS_11A;\n\t} else {\n\t\tif (pmlmeinfo->VHT_enable)\n\t\t\tnetwork_type = WIRELESS_11AC;\n\t\telse if (pmlmeinfo->HT_enable)\n\t\t\tnetwork_type = WIRELESS_11_24N;\n\n\t\tif ((cckratesonly_included(rate, ratelen)) == _TRUE)\n\t\t\tnetwork_type |= WIRELESS_11B;\n\t\telse if ((cckrates_included(rate, ratelen)) == _TRUE)\n\t\t\tnetwork_type |= WIRELESS_11BG;\n\t\telse\n\t\t\tnetwork_type |= WIRELESS_11G;\n\t}\n\n\tpmlmeext->cur_wireless_mode = network_type & padapter->registrypriv.wireless_mode;\n\t/* RTW_INFO(\"network_type=%02x, padapter->registrypriv.wireless_mode=%02x\\n\", network_type, padapter->registrypriv.wireless_mode); */\n\n#ifndef RTW_HALMAC\n\t/* HALMAC IC do not set HW_VAR_RESP_SIFS here */\n#if 0\n\tif ((pmlmeext->cur_wireless_mode == WIRELESS_11G) ||\n\t    (pmlmeext->cur_wireless_mode == WIRELESS_11BG)) /* WIRELESS_MODE_G) */\n\t\tSIFS_Timer = 0x0a0a;/* CCK */\n\telse\n\t\tSIFS_Timer = 0x0e0e;/* pHalData->SifsTime; //OFDM */\n#endif\n\n\tSIFS_Timer = 0x0a0a0808; /* 0x0808->for CCK, 0x0a0a->for OFDM\n                              * change this value if having IOT issues. */\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_RESP_SIFS, (u8 *)&SIFS_Timer);\n#endif\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_WIRELESS_MODE, (u8 *)&(pmlmeext->cur_wireless_mode));\n\n\tif ((pmlmeext->cur_wireless_mode & WIRELESS_11B)\n\t\t#ifdef CONFIG_P2P\n\t\t&& (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)\n\t\t\t#ifdef CONFIG_IOCTL_CFG80211\n\t\t\t|| !rtw_cfg80211_iface_has_p2p_group_cap(padapter)\n\t\t\t#endif\n\t\t\t)\n\t\t#endif\n\t)\n\t\tupdate_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB);\n\telse\n\t\tupdate_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB);\n}\n\nvoid fire_write_MAC_cmd(_adapter *padapter, unsigned int addr, unsigned int value);\nvoid fire_write_MAC_cmd(_adapter *padapter, unsigned int addr, unsigned int value)\n{\n#if 0\n\tstruct cmd_obj\t\t\t\t\t*ph2c;\n\tstruct reg_rw_parm\t\t\t*pwriteMacPara;\n\tstruct cmd_priv\t\t\t\t\t*pcmdpriv = &(padapter->cmdpriv);\n\n\tph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (ph2c == NULL)\n\t\treturn;\n\n\tpwriteMacPara = (struct reg_rw_parm *)rtw_malloc(sizeof(struct reg_rw_parm));\n\tif (pwriteMacPara == NULL) {\n\t\trtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));\n\t\treturn;\n\t}\n\n\tpwriteMacPara->rw = 1;\n\tpwriteMacPara->addr = addr;\n\tpwriteMacPara->value = value;\n\n\tinit_h2fwcmd_w_parm_no_rsp(ph2c, pwriteMacPara, GEN_CMD_CODE(_Write_MACREG));\n\trtw_enqueue_cmd(pcmdpriv, ph2c);\n#endif\n}\n\nvoid update_sta_basic_rate(struct sta_info *psta, u8 wireless_mode)\n{\n\tif (IsSupportedTxCCK(wireless_mode)) {\n\t\t/* Only B, B/G, and B/G/N AP could use CCK rate */\n\t\t_rtw_memcpy(psta->bssrateset, rtw_basic_rate_cck, 4);\n\t\tpsta->bssratelen = 4;\n\t} else {\n\t\t_rtw_memcpy(psta->bssrateset, rtw_basic_rate_ofdm, 3);\n\t\tpsta->bssratelen = 3;\n\t}\n}\n\nint rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num)\n{\n\tu8 *ie, *p;\n\tunsigned int ie_len;\n\tint i, j;\n\n\tstruct support_rate_handler support_rate_tbl[] = {\n\t\t{IEEE80211_CCK_RATE_1MB, \t\t_FALSE,\t\t_FALSE},\n\t\t{IEEE80211_CCK_RATE_2MB, \t\t_FALSE,\t\t_FALSE},\n\t\t{IEEE80211_CCK_RATE_5MB, \t\t_FALSE,\t\t_FALSE},\n\t\t{IEEE80211_CCK_RATE_11MB,\t\t_FALSE,\t\t_FALSE},\n\t\t{IEEE80211_OFDM_RATE_6MB,\t\t_FALSE,\t\t_FALSE},\n\t\t{IEEE80211_OFDM_RATE_9MB,\t\t_FALSE,\t\t_FALSE},\n\t\t{IEEE80211_OFDM_RATE_12MB,\t\t_FALSE,\t\t_FALSE},\n\t\t{IEEE80211_OFDM_RATE_18MB,\t\t_FALSE,\t\t_FALSE},\n\t\t{IEEE80211_OFDM_RATE_24MB,\t\t_FALSE,\t\t_FALSE},\n\t\t{IEEE80211_OFDM_RATE_36MB,\t\t_FALSE,\t\t_FALSE},\n\t\t{IEEE80211_OFDM_RATE_48MB,\t\t_FALSE,\t\t_FALSE},\n\t\t{IEEE80211_OFDM_RATE_54MB,\t\t_FALSE,\t\t_FALSE},\n\t};\n\t\t\n\tif (!rate_set || !rate_num)\n\t\treturn _FALSE;\n\n\t*rate_num = 0;\n\tie = rtw_get_ie(ies, _SUPPORTEDRATES_IE_, &ie_len, ies_len);\n\tif (ie == NULL)\n\t\tgoto ext_rate;\n\n\t/* get valid supported rates */\n\tfor (i = 0; i < 12; i++) {\n\t\tp = ie + 2;\n\t\tfor (j = 0; j < ie_len; j++) {\n\t\t\tif ((*p & ~BIT(7)) == support_rate_tbl[i].rate){\n\t\t\t\tsupport_rate_tbl[i].existence = _TRUE;\n\t\t\t\tif ((*p) & BIT(7))\n\t\t\t\t\tsupport_rate_tbl[i].basic = _TRUE;\n\t\t\t}\n\t\t\tp++;\n\t\t}\n\t}\n\next_rate:\n\tie = rtw_get_ie(ies, _EXT_SUPPORTEDRATES_IE_, &ie_len, ies_len);\n\tif (ie) {\n\t\t/* get valid extended supported rates */\n\t\tfor (i = 0; i < 12; i++) {\n\t\t\tp = ie + 2;\n\t\t\tfor (j = 0; j < ie_len; j++) {\n\t\t\t\tif ((*p & ~BIT(7)) == support_rate_tbl[i].rate){\n\t\t\t\t\tsupport_rate_tbl[i].existence = _TRUE;\n\t\t\t\t\tif ((*p) & BIT(7))\n\t\t\t\t\t\tsupport_rate_tbl[i].basic = _TRUE;\n\t\t\t\t}\n\t\t\t\tp++;\n\t\t\t}\n\t\t}\n\t}\n\n\tfor (i = 0; i < 12; i++){\n\t\tif (support_rate_tbl[i].existence){\n\t\t\tif (support_rate_tbl[i].basic)\n\t\t\t\trate_set[*rate_num] = support_rate_tbl[i].rate | IEEE80211_BASIC_RATE_MASK;\n\t\t\telse\n\t\t\t\trate_set[*rate_num] = support_rate_tbl[i].rate;\n\t\t\t*rate_num += 1;\n\t\t}\n\t}\n\n\tif (*rate_num == 0)\n\t\treturn _FAIL;\n\n\tif (0) {\n\t\tint i;\n\n\t\tfor (i = 0; i < *rate_num; i++)\n\t\t\tRTW_INFO(\"rate:0x%02x\\n\", *(rate_set + i));\n\t}\n\n\treturn _SUCCESS;\n}\n\nvoid process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr)\n{\n\tstruct sta_info *psta;\n\tu16 tid, start_seq, param;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct ADDBA_request\t*preq = (struct ADDBA_request *)paddba_req;\n\tu8 size, accept = _FALSE;\n\n\tpsta = rtw_get_stainfo(pstapriv, addr);\n\tif (!psta)\n\t\tgoto exit;\n\n\tstart_seq = le16_to_cpu(preq->BA_starting_seqctrl) >> 4;\n\n\tparam = le16_to_cpu(preq->BA_para_set);\n\ttid = (param >> 2) & 0x0f;\n\n\n\taccept = rtw_rx_ampdu_is_accept(padapter);\n\tif (padapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID)\n\t\tsize = padapter->fix_rx_ampdu_size;\n\telse {\n\t\tsize = rtw_rx_ampdu_size(padapter);\n\t\tsize = rtw_min(size, rx_ampdu_size_sta_limit(padapter, psta));\n\t}\n\n\tif (accept == _TRUE)\n\t\trtw_addbarsp_cmd(padapter, addr, tid, 0, size, start_seq);\n\telse\n\t\trtw_addbarsp_cmd(padapter, addr, tid, 37, size, start_seq); /* reject ADDBA Req */\n\nexit:\n\treturn;\n}\n\nvoid rtw_process_bar_frame(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tstruct sta_info *psta = NULL;\n\tstruct recv_reorder_ctrl *preorder_ctrl = NULL;\n\tu8 tid = 0;\n\tu16 start_seq=0;\n\n\tpsta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));\n\tif (psta == NULL)\n\t\tgoto exit;\n\n\ttid = ((cpu_to_le16((*(u16 *)(pframe + 16))) & 0xf000) >> 12);\n\tpreorder_ctrl = &psta->recvreorder_ctrl[tid];\n\tstart_seq = ((cpu_to_le16(*(u16 *)(pframe + 18))) >> 4);\n\tpreorder_ctrl->indicate_seq = start_seq;\n\n\t/* for Debug use */\n\tif (0)\n\t\tRTW_INFO(FUNC_ADPT_FMT\" tid=%d, start_seq=%d\\n\", FUNC_ADPT_ARG(padapter),  tid, start_seq);\n\nexit:\n\treturn;\n}\n\nvoid update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len)\n{\n\tu8 *pIE;\n\tu32 *pbuf;\n\n\tpIE = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpbuf = (u32 *)pIE;\n\n\tpmlmeext->TSFValue = le32_to_cpu(*(pbuf + 1));\n\n\tpmlmeext->TSFValue = pmlmeext->TSFValue << 32;\n\n\tpmlmeext->TSFValue |= le32_to_cpu(*pbuf);\n}\n\nvoid correct_TSF(_adapter *padapter, u8 mlme_state)\n{\n\tu8 m_state = mlme_state;\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_CORRECT_TSF, (u8 *)&m_state);\n}\n\n#ifdef CONFIG_BCN_RECV_TIME\n/*\tcalculate beacon receiving time\n\t1.RxBCNTime(CCK_1M) = [192us(preamble)] + [length of beacon(byte)*8us] + [10us]\n\t2.RxBCNTime(OFDM_6M) = [8us(S) + 8us(L) + 4us(L-SIG)] + [(length of beacon(byte)/3 + 1] *4us] + [10us]\n*/\ninline u16 _rx_bcn_time_calculate(uint bcn_len, u8 data_rate)\n{\n\tu16 rx_bcn_time = 0;/*us*/\n\n\tif (data_rate == DESC_RATE1M)\n\t\trx_bcn_time = 192 + bcn_len * 8 + 10;\n\telse if(data_rate == DESC_RATE6M)\n\t\trx_bcn_time = 8 + 8 + 4 + (bcn_len /3 + 1) * 4 + 10;\n/*\n\telse\n\t\tRTW_ERR(\"%s invalid data rate(0x%02x)\\n\", __func__, data_rate);\n*/\n\treturn rx_bcn_time;\n}\nvoid rtw_rx_bcn_time_update(_adapter *adapter, uint bcn_len, u8 data_rate)\n{\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\n\tpmlmeext->bcn_rx_time = _rx_bcn_time_calculate(bcn_len, data_rate);\n}\n#endif\n\nvoid beacon_timing_control(_adapter *padapter)\n{\n\trtw_hal_bcn_related_reg_setting(padapter);\n}\n\nvoid dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num)\n{\n\tRTW_PRINT_SEL(sel, \"0x%08x\\n\", map->m0);\n#if (MACID_NUM_SW_LIMIT > 32)\n\tif (max_num && max_num > 32)\n\t\tRTW_PRINT_SEL(sel, \"0x%08x\\n\", map->m1);\n#endif\n#if (MACID_NUM_SW_LIMIT > 64)\n\tif (max_num && max_num > 64)\n\t\tRTW_PRINT_SEL(sel, \"0x%08x\\n\", map->m2);\n#endif\n#if (MACID_NUM_SW_LIMIT > 96)\n\tif (max_num && max_num > 96)\n\t\tRTW_PRINT_SEL(sel, \"0x%08x\\n\", map->m3);\n#endif\n}\n\ninline bool rtw_macid_is_set(struct macid_bmp *map, u8 id)\n{\n\tif (id < 32)\n\t\treturn map->m0 & BIT(id);\n#if (MACID_NUM_SW_LIMIT > 32)\n\telse if (id < 64)\n\t\treturn map->m1 & BIT(id - 32);\n#endif\n#if (MACID_NUM_SW_LIMIT > 64)\n\telse if (id < 96)\n\t\treturn map->m2 & BIT(id - 64);\n#endif\n#if (MACID_NUM_SW_LIMIT > 96)\n\telse if (id < 128)\n\t\treturn map->m3 & BIT(id - 96);\n#endif\n\telse\n\t\trtw_warn_on(1);\n\n\treturn 0;\n}\n\ninline void rtw_macid_map_set(struct macid_bmp *map, u8 id)\n{\n\tif (id < 32)\n\t\tmap->m0 |= BIT(id);\n#if (MACID_NUM_SW_LIMIT > 32)\n\telse if (id < 64)\n\t\tmap->m1 |= BIT(id - 32);\n#endif\n#if (MACID_NUM_SW_LIMIT > 64)\n\telse if (id < 96)\n\t\tmap->m2 |= BIT(id - 64);\n#endif\n#if (MACID_NUM_SW_LIMIT > 96)\n\telse if (id < 128)\n\t\tmap->m3 |= BIT(id - 96);\n#endif\n\telse\n\t\trtw_warn_on(1);\n}\n\ninline void rtw_macid_map_clr(struct macid_bmp *map, u8 id)\n{\n\tif (id < 32)\n\t\tmap->m0 &= ~BIT(id);\n#if (MACID_NUM_SW_LIMIT > 32)\n\telse if (id < 64)\n\t\tmap->m1 &= ~BIT(id - 32);\n#endif\n#if (MACID_NUM_SW_LIMIT > 64)\n\telse if (id < 96)\n\t\tmap->m2 &= ~BIT(id - 64);\n#endif\n#if (MACID_NUM_SW_LIMIT > 96)\n\telse if (id < 128)\n\t\tmap->m3 &= ~BIT(id - 96);\n#endif\n\telse\n\t\trtw_warn_on(1);\n}\n\ninline bool rtw_macid_is_used(struct macid_ctl_t *macid_ctl, u8 id)\n{\n\treturn rtw_macid_is_set(&macid_ctl->used, id);\n}\n\ninline bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id)\n{\n\treturn rtw_macid_is_set(&macid_ctl->bmc, id);\n}\n\ninline u8 rtw_macid_get_iface_bmp(struct macid_ctl_t *macid_ctl, u8 id)\n{\n\tint i;\n\tu8 iface_bmp = 0;\n\n\tfor (i = 0; i < CONFIG_IFACE_NUMBER; i++) {\n\t\tif (rtw_macid_is_set(&macid_ctl->if_g[i], id))\n\t\t\tiface_bmp |= BIT(i);\n\t}\n\treturn iface_bmp;\n}\n\ninline bool rtw_macid_is_iface_shared(struct macid_ctl_t *macid_ctl, u8 id)\n{\n\tint i;\n\tu8 iface_bmp = 0;\n\n\tfor (i = 0; i < CONFIG_IFACE_NUMBER; i++) {\n\t\tif (rtw_macid_is_set(&macid_ctl->if_g[i], id)) {\n\t\t\tif (iface_bmp)\n\t\t\t\treturn 1;\n\t\t\tiface_bmp |= BIT(i);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\ninline bool rtw_macid_is_iface_specific(struct macid_ctl_t *macid_ctl, u8 id, _adapter *adapter)\n{\n\tint i;\n\tu8 iface_bmp = 0;\n\n\tfor (i = 0; i < CONFIG_IFACE_NUMBER; i++) {\n\t\tif (rtw_macid_is_set(&macid_ctl->if_g[i], id)) {\n\t\t\tif (iface_bmp || i != adapter->iface_id)\n\t\t\t\treturn 0;\n\t\t\tiface_bmp |= BIT(i);\n\t\t}\n\t}\n\n\treturn iface_bmp ? 1 : 0;\n}\n\ninline s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id)\n{\n\tint i;\n\n\tfor (i = 0; i < 2; i++) {\n\t\tif (rtw_macid_is_set(&macid_ctl->ch_g[i], id))\n\t\t\treturn i;\n\t}\n\treturn -1;\n}\n\n/*Record bc's mac-id and sec-cam-id*/\ninline void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\n\tmacid_ctl->iface_bmc[padapter->iface_id] = mac_id;\n}\ninline u8 rtw_iface_bcmc_id_get(_adapter *padapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\n\treturn macid_ctl->iface_bmc[padapter->iface_id];\n}\n\nvoid rtw_alloc_macid(_adapter *padapter, struct sta_info *psta)\n{\n\tint i;\n\t_irqL irqL;\n\tu8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\tstruct macid_bmp *used_map = &macid_ctl->used;\n\t/* static u8 last_id = 0;  for testing */\n\tu8 last_id = 0;\n\tu8 is_bc_sta = _FALSE;\n\n\tif (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN)) {\n\t\tpsta->cmn.mac_id = macid_ctl->num;\n\t\treturn;\n\t}\n\n\tif (_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)) {\n\t\tis_bc_sta = _TRUE;\n\t\trtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID);\t/*init default value*/\n\t}\n\n\tif (is_bc_sta\n\t\t#ifdef CONFIG_CONCURRENT_MODE\n\t\t&& (MLME_IS_STA(padapter) || MLME_IS_NULL(padapter))\n\t\t#endif\n\t) {\n\t\t/* STA mode have no BMC data TX, shared with this macid */\n\t\t/* When non-concurrent, only one BMC data TX is used, shared with this macid */\n\t\t/* TODO: When concurrent, non-security BMC data TX may use this, but will not control by specific macid sleep */\n\t\ti = RTW_DEFAULT_MGMT_MACID;\n\t\tgoto assigned;\n\t}\n\n\t_enter_critical_bh(&macid_ctl->lock, &irqL);\n\n\tfor (i = last_id; i < macid_ctl->num; i++) {\n#ifdef CONFIG_MCC_MODE\n\t\t/* macid 0/1 reserve for mcc for mgnt queue macid */\n\t\tif (MCC_EN(padapter)) {\n\t\t\tif (i == MCC_ROLE_STA_GC_MGMT_QUEUE_MACID)\n\t\t\t\tcontinue;\n\t\t\tif (i == MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID)\n\t\t\t\tcontinue;\n\t\t}\n#endif /* CONFIG_MCC_MODE */\n\n\t\tif (is_bc_sta) {\n\t\t\tstruct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);\n\n\t\t\tif ((!rtw_macid_is_used(macid_ctl, i)) && (!rtw_sec_camid_is_used(cam_ctl, i)))\n\t\t\t\tbreak;\n\t\t} else {\n\t\t\tif (!rtw_macid_is_used(macid_ctl, i))\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (i < macid_ctl->num) {\n\n\t\trtw_macid_map_set(used_map, i);\n\n\t\tif (is_bc_sta) {\n\t\t\tstruct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);\n\n\t\t\trtw_macid_map_set(&macid_ctl->bmc, i);\n\t\t\trtw_iface_bcmc_id_set(padapter, i);\n\t\t\trtw_sec_cam_map_set(&cam_ctl->used, i);\n\t\t}\n\n\t\trtw_macid_map_set(&macid_ctl->if_g[padapter->iface_id], i);\n\t\tmacid_ctl->sta[i] = psta;\n\n\t\t/* TODO ch_g? */\n\n\t\tlast_id++;\n\t\tlast_id %= macid_ctl->num;\n\t}\n\n\t_exit_critical_bh(&macid_ctl->lock, &irqL);\n\n\tif (i >= macid_ctl->num) {\n\t\tpsta->cmn.mac_id = macid_ctl->num;\n\t\tRTW_ERR(FUNC_ADPT_FMT\" if%u, mac_addr:\"MAC_FMT\" no available macid\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->cmn.mac_addr));\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t} else\n\t\tgoto assigned;\n\nassigned:\n\tpsta->cmn.mac_id = i;\n\tRTW_INFO(FUNC_ADPT_FMT\" if%u, mac_addr:\"MAC_FMT\" macid:%u\\n\"\n\t\t, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);\n\nexit:\n\treturn;\n}\n\nvoid rtw_release_macid(_adapter *padapter, struct sta_info *psta)\n{\n\t_irqL irqL;\n\tu8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\tu8 ifbmp;\n\tint i;\n\n\tif (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN))\n\t\tgoto exit;\n\n\tif (psta->cmn.mac_id >= macid_ctl->num) {\n\t\tRTW_WARN(FUNC_ADPT_FMT\" if%u, mac_addr:\"MAC_FMT\" macid:%u not valid\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1\n\t\t\t, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (psta->cmn.mac_id == RTW_DEFAULT_MGMT_MACID)\n\t\tgoto msg;\n\n\t_enter_critical_bh(&macid_ctl->lock, &irqL);\n\n\tif (!rtw_macid_is_used(macid_ctl, psta->cmn.mac_id)) {\n\t\tRTW_WARN(FUNC_ADPT_FMT\" if%u, mac_addr:\"MAC_FMT\" macid:%u not used\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1\n\t\t\t, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);\n\t\t_exit_critical_bh(&macid_ctl->lock, &irqL);\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tifbmp = rtw_macid_get_iface_bmp(macid_ctl, psta->cmn.mac_id);\n\tif (!(ifbmp & BIT(padapter->iface_id))) {\n\t\tRTW_WARN(FUNC_ADPT_FMT\" if%u, mac_addr:\"MAC_FMT\" macid:%u not used by self\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1\n\t\t\t, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);\n\t\t_exit_critical_bh(&macid_ctl->lock, &irqL);\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)) {\n\t\tstruct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);\n\t\tu8 id = rtw_iface_bcmc_id_get(padapter);\n\n\t\tif ((id != INVALID_SEC_MAC_CAM_ID) && (id < cam_ctl->num))\n\t\t\trtw_sec_cam_map_clr(&cam_ctl->used, id);\n\n\t\trtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID);\n\t}\n\n\trtw_macid_map_clr(&macid_ctl->if_g[padapter->iface_id], psta->cmn.mac_id);\n\n\tifbmp &= ~BIT(padapter->iface_id);\n\tif (!ifbmp) { /* only used by self */\n\t\trtw_macid_map_clr(&macid_ctl->used, psta->cmn.mac_id);\n\t\trtw_macid_map_clr(&macid_ctl->bmc, psta->cmn.mac_id);\n\t\tfor (i = 0; i < 2; i++)\n\t\t\trtw_macid_map_clr(&macid_ctl->ch_g[i], psta->cmn.mac_id);\n\t\tmacid_ctl->sta[psta->cmn.mac_id] = NULL;\n\t}\n\n\t_exit_critical_bh(&macid_ctl->lock, &irqL);\n\nmsg:\n\tRTW_INFO(FUNC_ADPT_FMT\" if%u, mac_addr:\"MAC_FMT\" macid:%u\\n\"\n\t\t, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1\n\t\t, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id\n\t);\n\nexit:\n\tpsta->cmn.mac_id = macid_ctl->num;\n}\n\n/* For 8188E RA */\nu8 rtw_search_max_mac_id(_adapter *padapter)\n{\n\tu8 max_mac_id = 0;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\tint i;\n\t_irqL irqL;\n\n\t/* TODO: Only search for connected macid? */\n\n\t_enter_critical_bh(&macid_ctl->lock, &irqL);\n\tfor (i = (macid_ctl->num - 1); i > 0 ; i--) {\n\t\tif (rtw_macid_is_used(macid_ctl, i))\n\t\t\tbreak;\n\t}\n\t_exit_critical_bh(&macid_ctl->lock, &irqL);\n\tmax_mac_id = i;\n\n\treturn max_mac_id;\n}\n\ninline u8 rtw_macid_ctl_set_h2c_msr(struct macid_ctl_t *macid_ctl, u8 id, u8 h2c_msr)\n{\n\tu8 op_num_change_bmp = 0;\n\n\tif (id >= macid_ctl->num) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (GET_H2CCMD_MSRRPT_PARM_OPMODE(&macid_ctl->h2c_msr[id])\n\t\t&& !GET_H2CCMD_MSRRPT_PARM_OPMODE(&h2c_msr)\n\t) {\n\t\tu8 role = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[id]);\n\n\t\tif (role < H2C_MSR_ROLE_MAX) {\n\t\t\tmacid_ctl->op_num[role]--;\n\t\t\top_num_change_bmp |= BIT(role);\n\t\t}\n\t} else if (!GET_H2CCMD_MSRRPT_PARM_OPMODE(&macid_ctl->h2c_msr[id])\n\t\t&& GET_H2CCMD_MSRRPT_PARM_OPMODE(&h2c_msr)\n\t) {\n\t\tu8 role = GET_H2CCMD_MSRRPT_PARM_ROLE(&h2c_msr);\n\n\t\tif (role < H2C_MSR_ROLE_MAX) {\n\t\t\tmacid_ctl->op_num[role]++;\n\t\t\top_num_change_bmp |= BIT(role);\n\t\t}\n\t}\n\n\tmacid_ctl->h2c_msr[id] = h2c_msr;\n\tif (0)\n\t\tRTW_INFO(\"macid:%u, h2c_msr:\"H2C_MSR_FMT\"\\n\", id, H2C_MSR_ARG(&macid_ctl->h2c_msr[id]));\n\nexit:\n\treturn op_num_change_bmp;\n}\n\ninline void rtw_macid_ctl_set_bw(struct macid_ctl_t *macid_ctl, u8 id, u8 bw)\n{\n\tif (id >= macid_ctl->num) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tmacid_ctl->bw[id] = bw;\n\tif (0)\n\t\tRTW_INFO(\"macid:%u, bw:%s\\n\", id, ch_width_str(macid_ctl->bw[id]));\n}\n\ninline void rtw_macid_ctl_set_vht_en(struct macid_ctl_t *macid_ctl, u8 id, u8 en)\n{\n\tif (id >= macid_ctl->num) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tmacid_ctl->vht_en[id] = en;\n\tif (0)\n\t\tRTW_INFO(\"macid:%u, vht_en:%u\\n\", id, macid_ctl->vht_en[id]);\n}\n\ninline void rtw_macid_ctl_set_rate_bmp0(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp)\n{\n\tif (id >= macid_ctl->num) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tmacid_ctl->rate_bmp0[id] = bmp;\n\tif (0)\n\t\tRTW_INFO(\"macid:%u, rate_bmp0:0x%08X\\n\", id, macid_ctl->rate_bmp0[id]);\n}\n\ninline void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp)\n{\n\tif (id >= macid_ctl->num) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tmacid_ctl->rate_bmp1[id] = bmp;\n\tif (0)\n\t\tRTW_INFO(\"macid:%u, rate_bmp1:0x%08X\\n\", id, macid_ctl->rate_bmp1[id]);\n}\n\ninline void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3)\n{\n\tmacid_ctl->reg_sleep_m0 = m0;\n#if (MACID_NUM_SW_LIMIT > 32)\n\tmacid_ctl->reg_sleep_m1 = m1;\n#endif\n#if (MACID_NUM_SW_LIMIT > 64)\n\tmacid_ctl->reg_sleep_m2 = m2;\n#endif\n#if (MACID_NUM_SW_LIMIT > 96)\n\tmacid_ctl->reg_sleep_m3 = m3;\n#endif\n}\n\ninline void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl)\n{\n\tint i;\n\tu8 id = RTW_DEFAULT_MGMT_MACID;\n\n\trtw_macid_map_set(&macid_ctl->used, id);\n\trtw_macid_map_set(&macid_ctl->bmc, id);\n\tfor (i = 0; i < CONFIG_IFACE_NUMBER; i++)\n\t\trtw_macid_map_set(&macid_ctl->if_g[i], id);\n\tmacid_ctl->sta[id] = NULL;\n\n\t_rtw_spinlock_init(&macid_ctl->lock);\n}\n\ninline void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl)\n{\n\t_rtw_spinlock_free(&macid_ctl->lock);\n}\n\ninline bool rtw_bmp_is_set(const u8 *bmp, u8 bmp_len, u8 id)\n{\n\tif (id / 8 >= bmp_len)\n\t\treturn 0;\n\n\treturn bmp[id / 8] & BIT(id % 8);\n}\n\ninline void rtw_bmp_set(u8 *bmp, u8 bmp_len, u8 id)\n{\n\tif (id / 8 < bmp_len)\n\t\tbmp[id / 8] |= BIT(id % 8);\n}\n\ninline void rtw_bmp_clear(u8 *bmp, u8 bmp_len, u8 id)\n{\n\tif (id / 8 < bmp_len)\n\t\tbmp[id / 8] &= ~BIT(id % 8);\n}\n\ninline bool rtw_bmp_not_empty(const u8 *bmp, u8 bmp_len)\n{\n\tint i;\n\n\tfor (i = 0; i < bmp_len; i++) {\n\t\tif (bmp[i])\n\t\t\treturn 1;\n\t}\n\n\treturn 0;\n}\n\ninline bool rtw_bmp_not_empty_exclude_bit0(const u8 *bmp, u8 bmp_len)\n{\n\tint i;\n\n\tfor (i = 0; i < bmp_len; i++) {\n\t\tif (i == 0) {\n\t\t\tif (bmp[i] & 0xFE)\n\t\t\t\treturn 1;\n\t\t} else {\n\t\t\tif (bmp[i])\n\t\t\t\treturn 1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n#ifdef CONFIG_AP_MODE\n/* Check the id be set or not in map , if yes , return a none zero value*/\nbool rtw_tim_map_is_set(_adapter *padapter, const u8 *map, u8 id)\n{\n\treturn rtw_bmp_is_set(map, padapter->stapriv.aid_bmp_len, id);\n}\n\n/* Set the id into map array*/\nvoid rtw_tim_map_set(_adapter *padapter, u8 *map, u8 id)\n{\n\trtw_bmp_set(map, padapter->stapriv.aid_bmp_len, id);\n}\n\n/* Clear the id from map array*/\nvoid rtw_tim_map_clear(_adapter *padapter, u8 *map, u8 id)\n{\n\trtw_bmp_clear(map, padapter->stapriv.aid_bmp_len, id);\n}\n\n/* Check have anyone bit be set , if yes return true*/\nbool rtw_tim_map_anyone_be_set(_adapter *padapter, const u8 *map)\n{\n\treturn rtw_bmp_not_empty(map, padapter->stapriv.aid_bmp_len);\n}\n\n/* Check have anyone bit be set exclude bit0 , if yes return true*/\nbool rtw_tim_map_anyone_be_set_exclude_aid0(_adapter *padapter, const u8 *map)\n{\n\treturn rtw_bmp_not_empty_exclude_bit0(map, padapter->stapriv.aid_bmp_len);\n}\n#endif /* CONFIG_AP_MODE */\n\n#if 0\nunsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame)\n{\n\tunsigned short\t\t\t\tATIMWindow;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct tx_desc\t\t\t\t*ptxdesc;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tunsigned int\t\t\t\t\trate_len, len = 0;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t\t*cur_network = &(pmlmeinfo->network);\n\tu8\tbc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\n\t_rtw_memset(beacon_frame, 0, 256);\n\n\tpframe = beacon_frame + TXDESC_SIZE;\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);\n\n\tset_frame_sub_type(pframe, WIFI_BEACON);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\t/* timestamp will be inserted by hardware */\n\tpframe += 8;\n\tlen += 8;\n\n\t/* beacon interval: 2 bytes */\n\t_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);\n\n\tpframe += 2;\n\tlen += 2;\n\n\t/* capability info: 2 bytes */\n\t_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);\n\n\tpframe += 2;\n\tlen += 2;\n\n\t/* SSID */\n\tpframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &len);\n\n\t/* supported rates... */\n\trate_len = rtw_get_rateset_len(cur_network->SupportedRates);\n\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &len);\n\n\t/* DS parameter set */\n\tpframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &len);\n\n\t/* IBSS Parameter Set... */\n\t/* ATIMWindow = cur->Configuration.ATIMWindow; */\n\tATIMWindow = 0;\n\tpframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &len);\n\n\t/* todo: ERP IE */\n\n\t/* EXTERNDED SUPPORTED RATE */\n\tif (rate_len > 8)\n\t\tpframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &len);\n\n\tif ((len + TXDESC_SIZE) > 256) {\n\t\t/* RTW_INFO(\"marc: beacon frame too large\\n\"); */\n\t\treturn 0;\n\t}\n\n\t/* fill the tx descriptor */\n\tptxdesc = (struct tx_desc *)beacon_frame;\n\n\t/* offset 0\t */\n\tptxdesc->txdw0 |= cpu_to_le32(len & 0x0000ffff);\n\tptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00ff0000); /* default = 32 bytes for TX Desc */\n\n\t/* offset 4\t */\n\tptxdesc->txdw1 |= cpu_to_le32((0x10 << QSEL_SHT) & 0x00001f00);\n\n\t/* offset 8\t\t */\n\tptxdesc->txdw2 |= cpu_to_le32(BMC);\n\tptxdesc->txdw2 |= cpu_to_le32(BK);\n\n\t/* offset 16\t\t */\n\tptxdesc->txdw4 = 0x80000000;\n\n\t/* offset 20 */\n\tptxdesc->txdw5 = 0x00000000; /* 1M\t */\n\n\treturn len + TXDESC_SIZE;\n}\n#endif\n\n_adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj)\n{\n\t_adapter *port0_iface = NULL;\n\tint i;\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tif (get_hw_port(dvobj->padapters[i]) == HW_PORT0)\n\t\t\tbreak;\n\t}\n\n\tif (i < 0 || i >= dvobj->iface_nums)\n\t\trtw_warn_on(1);\n\telse\n\t\tport0_iface = dvobj->padapters[i];\n\n\treturn port0_iface;\n}\n\n_adapter *dvobj_get_unregisterd_adapter(struct dvobj_priv *dvobj)\n{\n\t_adapter *adapter = NULL;\n\tint i;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tif (dvobj->padapters[i]->registered == 0)\n\t\t\tbreak;\n\t}\n\n\tif (i < dvobj->iface_nums)\n\t\tadapter = dvobj->padapters[i];\n\n\treturn adapter;\n}\n\n_adapter *dvobj_get_adapter_by_addr(struct dvobj_priv *dvobj, u8 *addr)\n{\n\t_adapter *adapter = NULL;\n\tint i;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tif (_rtw_memcmp(dvobj->padapters[i]->mac_addr, addr, ETH_ALEN) == _TRUE)\n\t\t\tbreak;\n\t}\n\n\tif (i < dvobj->iface_nums)\n\t\tadapter = dvobj->padapters[i];\n\n\treturn adapter;\n}\n\n#ifdef CONFIG_WOWLAN\nbool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern,\n\t\t\t\t   int *pattern_len, char *bit_mask)\n{\n\tchar *cp = NULL, *end = NULL;\n\tsize_t len = 0;\n\tint pos = 0, mask_pos = 0, res = 0;\n\tu8 member[2] = {0};\n\n\tcp = strchr(input, '=');\n\tif (cp) {\n\t\t*cp = 0;\n\t\tcp++;\n\t\tinput = cp;\n\t}\n\n\twhile (1) {\n\t\tcp = strchr(input, ':');\n\n\t\tif (cp) {\n\t\t\tlen = strlen(input) - strlen(cp);\n\t\t\t*cp = 0;\n\t\t\tcp++;\n\t\t} else\n\t\t\tlen = 2;\n\n\t\tif (bit_mask && (strcmp(input, \"-\") == 0 ||\n\t\t\t\t strcmp(input, \"xx\") == 0 ||\n\t\t\t\t strcmp(input, \"--\") == 0)) {\n\t\t\t/* skip this byte and leave mask bit unset */\n\t\t} else {\n\t\t\tu8 hex;\n\n\t\t\tstrncpy(member, input, len);\n\t\t\tif (!rtw_check_pattern_valid(member, sizeof(member))) {\n\t\t\t\tRTW_INFO(\"%s:[ERROR] pattern is invalid!!\\n\",\n\t\t\t\t\t __func__);\n\t\t\t\tgoto error;\n\t\t\t}\n\n\t\t\tres = sscanf(member, \"%02hhx\", &hex);\n\t\t\tpattern[pos] = hex;\n\t\t\tmask_pos = pos / 8;\n\t\t\tif (bit_mask)\n\t\t\t\tbit_mask[mask_pos] |= 1 << (pos % 8);\n\t\t}\n\n\t\tpos++;\n\t\tif (!cp)\n\t\t\tbreak;\n\t\tinput = cp;\n\t}\n\n\t(*pattern_len) = pos;\n\n\treturn _TRUE;\nerror:\n\treturn _FALSE;\n}\n\nbool rtw_check_pattern_valid(u8 *input, u8 len)\n{\n\tint i = 0;\n\tbool res = _FALSE;\n\n\tif (len != 2)\n\t\tgoto exit;\n\n\tfor (i = 0 ; i < len ; i++)\n\t\tif (IsHexDigit(input[i]) == _FALSE)\n\t\t\tgoto exit;\n\n\tres = _SUCCESS;\n\nexit:\n\treturn res;\n}\nvoid rtw_wow_pattern_sw_reset(_adapter *adapter)\n{\n\tint i;\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter);\n\n\tif (pwrctrlpriv->default_patterns_en == _TRUE)\n\t\tpwrctrlpriv->wowlan_pattern_idx = DEFAULT_PATTERN_NUM;\n\telse\n\t\tpwrctrlpriv->wowlan_pattern_idx = 0;\n\n\tfor (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) {\n\t\t_rtw_memset(pwrctrlpriv->patterns[i].content, '\\0', sizeof(pwrctrlpriv->patterns[i].content));\n\t\t_rtw_memset(pwrctrlpriv->patterns[i].mask, '\\0', sizeof(pwrctrlpriv->patterns[i].mask));\n\t\tpwrctrlpriv->patterns[i].len = 0;\n\t}\n}\n\nu8 rtw_set_default_pattern(_adapter *adapter)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;\n\tu8 index = 0;\n\tu8 multicast_addr[3] = {0x01, 0x00, 0x5e};\n\tu8 multicast_ip[4] = {0xe0, 0x28, 0x28, 0x2a};\n\n\tu8 unicast_mask[5] = {0x3f, 0x70, 0x80, 0xc0, 0x03};\n\tu8 icmpv6_mask[7] = {0x00, 0x70, 0x10, 0x00, 0xc0, 0xc0, 0x3f};\n\tu8 multicast_mask[5] = {0x07, 0x70, 0x80, 0xc0, 0x03};\n\n\tu8 ip_protocol[3] = {0x08, 0x00, 0x45};\n\tu8 ipv6_protocol[3] = {0x86, 0xdd, 0x60};\n\n\tu8 *target = NULL;\n\n\tif (pwrpriv->default_patterns_en == _FALSE)\n\t\treturn 0;\n\n\tfor (index = 0 ; index < DEFAULT_PATTERN_NUM ; index++) {\n\t\t_rtw_memset(pwrpriv->patterns[index].content, 0,\n\t\t\t    sizeof(pwrpriv->patterns[index].content));\n\t\t_rtw_memset(pwrpriv->patterns[index].mask, 0,\n\t\t\t    sizeof(pwrpriv->patterns[index].mask));\n\t\tpwrpriv->patterns[index].len = 0;\n\t}\n\n\t/*TCP/ICMP unicast*/\n\tfor (index = 0 ; index < DEFAULT_PATTERN_NUM ; index++) {\n\t\tswitch (index) {\n\t\tcase 0:\n\t\t\ttarget = pwrpriv->patterns[index].content;\n\t\t\t_rtw_memcpy(target, adapter_mac_addr(adapter),\n\t\t\t\t    ETH_ALEN);\n\n\t\t\ttarget += ETH_TYPE_OFFSET;\n\t\t\t_rtw_memcpy(target, &ip_protocol,\n\t\t\t\t    sizeof(ip_protocol));\n\n\t\t\t/* TCP */\n\t\t\ttarget += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET);\n\t\t\t_rtw_memset(target, 0x06, 1);\n\n\t\t\ttarget += (IP_OFFSET - PROTOCOL_OFFSET);\n\n\t\t\t_rtw_memcpy(target, pmlmeinfo->ip_addr,\n\t\t\t\t    RTW_IP_ADDR_LEN);\n\n\t\t\t_rtw_memcpy(pwrpriv->patterns[index].mask,\n\t\t\t\t    &unicast_mask, sizeof(unicast_mask));\n\n\t\t\tpwrpriv->patterns[index].len =\n\t\t\t\tIP_OFFSET + RTW_IP_ADDR_LEN;\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\ttarget = pwrpriv->patterns[index].content;\n\t\t\t_rtw_memcpy(target, adapter_mac_addr(adapter),\n\t\t\t\t    ETH_ALEN);\n\n\t\t\ttarget += ETH_TYPE_OFFSET;\n\t\t\t_rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol));\n\n\t\t\t/* ICMP */\n\t\t\ttarget += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET);\n\t\t\t_rtw_memset(target, 0x01, 1);\n\n\t\t\ttarget += (IP_OFFSET - PROTOCOL_OFFSET);\n\t\t\t_rtw_memcpy(target, pmlmeinfo->ip_addr,\n\t\t\t\t    RTW_IP_ADDR_LEN);\n\n\t\t\t_rtw_memcpy(pwrpriv->patterns[index].mask,\n\t\t\t\t    &unicast_mask, sizeof(unicast_mask));\n\t\t\tpwrpriv->patterns[index].len =\n\n\t\t\t\tIP_OFFSET + RTW_IP_ADDR_LEN;\n\t\t\tbreak;\n#ifdef CONFIG_IPV6\n\t\tcase 2:\n\t\t\tif (pwrpriv->wowlan_ns_offload_en == _TRUE) {\n\t\t\t\ttarget = pwrpriv->patterns[index].content;\n\t\t\t\ttarget += ETH_TYPE_OFFSET;\n\n\t\t\t\t_rtw_memcpy(target, &ipv6_protocol,\n\t\t\t\t\t    sizeof(ipv6_protocol));\n\n\t\t\t\t/* ICMPv6 */\n\t\t\t\ttarget += (IPv6_PROTOCOL_OFFSET -\n\t\t\t\t\t   ETH_TYPE_OFFSET);\n\t\t\t\t_rtw_memset(target, 0x3a, 1);\n\n\t\t\t\ttarget += (IPv6_OFFSET - IPv6_PROTOCOL_OFFSET);\n\t\t\t\t_rtw_memcpy(target, pmlmeinfo->ip6_addr,\n\t\t\t\t\t    RTW_IPv6_ADDR_LEN);\n\n\t\t\t\t_rtw_memcpy(pwrpriv->patterns[index].mask,\n\t\t\t\t\t    &icmpv6_mask, sizeof(icmpv6_mask));\n\t\t\t\tpwrpriv->patterns[index].len =\n\t\t\t\t\tIPv6_OFFSET + RTW_IPv6_ADDR_LEN;\n\t\t\t}\n\t\t\tbreak;\n#endif /*CONFIG_IPV6*/\n\t\tcase 3:\n\t\t\ttarget = pwrpriv->patterns[index].content;\n\t\t\t_rtw_memcpy(target, &multicast_addr,\n\t\t\t\t    sizeof(multicast_addr));\n\n\t\t\ttarget += ETH_TYPE_OFFSET;\n\t\t\t_rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol));\n\n\t\t\t/* UDP */\n\t\t\ttarget += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET);\n\t\t\t_rtw_memset(target, 0x11, 1);\n\n\t\t\ttarget += (IP_OFFSET - PROTOCOL_OFFSET);\n\t\t\t_rtw_memcpy(target, &multicast_ip,\n\t\t\t\t    sizeof(multicast_ip));\n\n\t\t\t_rtw_memcpy(pwrpriv->patterns[index].mask,\n\t\t\t\t    &multicast_mask, sizeof(multicast_mask));\n\n\t\t\tpwrpriv->patterns[index].len =\n\t\t\t\tIP_OFFSET + sizeof(multicast_ip);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn index;\n}\n\nvoid rtw_dump_priv_pattern(_adapter *adapter, u8 idx)\n{\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);\n\tchar str_1[128];\n\tchar *p_str;\n\tu8 val8 = 0;\n\tint i = 0, j = 0, len = 0, max_len = 0;\n\n\tRTW_INFO(\"=========[%d]========\\n\", idx);\n\n\tRTW_INFO(\">>>priv_pattern_content:\\n\");\n\tp_str = str_1;\n\tmax_len = sizeof(str_1);\n\tfor (i = 0 ; i < MAX_WKFM_PATTERN_SIZE / 8 ; i++) {\n\t\t_rtw_memset(p_str, 0, max_len);\n\t\tlen = 0;\n\t\tfor (j = 0 ; j < 8 ; j++) {\n\t\t\tval8 = pwrctl->patterns[idx].content[i * 8 + j];\n\t\t\tlen += snprintf(p_str + len, max_len - len,\n\t\t\t\t\t\"%02x \", val8);\n\t\t}\n\t\tRTW_INFO(\"%s\\n\", p_str);\n\t}\n\n\tRTW_INFO(\">>>priv_pattern_mask:\\n\");\n\tfor (i = 0 ; i < MAX_WKFM_SIZE / 8 ; i++) {\n\t\t_rtw_memset(p_str, 0, max_len);\n\t\tlen = 0;\n\t\tfor (j = 0 ; j < 8 ; j++) {\n\t\t\tval8 = pwrctl->patterns[idx].mask[i * 8 + j];\n\t\t\tlen += snprintf(p_str + len, max_len - len,\n\t\t\t\t\t\"%02x \", val8);\n\t\t}\n\t\tRTW_INFO(\"%s\\n\", p_str);\n\t}\n\n\tRTW_INFO(\">>>priv_pattern_len:\\n\");\n\tRTW_INFO(\"%s: len: %d\\n\", __func__, pwrctl->patterns[idx].len);\n}\n\nvoid rtw_wow_pattern_sw_dump(_adapter *adapter)\n{\n\tint i;\n\n\tRTW_INFO(\"********[RTK priv-patterns]*********\\n\");\n\tfor (i = 0 ; i < MAX_WKFM_CAM_NUM; i++)\n\t\trtw_dump_priv_pattern(adapter, i);\n}\n\nvoid rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr)\n{\n\tstruct sta_info\t\t*psta;\n\tstruct security_priv *psecpriv = &padapter->securitypriv;\n\n\t_rtw_memset(pcur_dot11txpn, 0, 8);\n\tif (NULL == StaAddr)\n\t\treturn;\n\tpsta = rtw_get_stainfo(&padapter->stapriv, StaAddr);\n\tRTW_INFO(\"%s(): StaAddr: %02x %02x %02x %02x %02x %02x\\n\",\n\t\t __func__, StaAddr[0], StaAddr[1], StaAddr[2],\n\t\t StaAddr[3], StaAddr[4], StaAddr[5]);\n\n\tif (psta) {\n\t\tif (psecpriv->dot11PrivacyAlgrthm == _AES_)\n\t\t\tAES_IV(pcur_dot11txpn, psta->dot11txpn, 0);\n\t\telse if (psecpriv->dot11PrivacyAlgrthm == _TKIP_)\n\t\t\tTKIP_IV(pcur_dot11txpn, psta->dot11txpn, 0);\n\n\t\tRTW_INFO(\"%s(): CurrentIV: %02x %02x %02x %02x %02x %02x %02x %02x\\n\"\n\t\t\t , __func__, pcur_dot11txpn[0], pcur_dot11txpn[1],\n\t\t\tpcur_dot11txpn[2], pcur_dot11txpn[3], pcur_dot11txpn[4],\n\t\t\tpcur_dot11txpn[5], pcur_dot11txpn[6], pcur_dot11txpn[7]);\n\t}\n}\n#endif /* CONFIG_WOWLAN */\n\n#ifdef CONFIG_PNO_SUPPORT\n#define\tCSCAN_TLV_TYPE_SSID_IE\t'S'\n#define CIPHER_IE \"key_mgmt=\"\n#define CIPHER_NONE \"NONE\"\n#define CIPHER_WPA_PSK \"WPA-PSK\"\n#define CIPHER_WPA_EAP \"WPA-EAP IEEE8021X\"\n/*\n *  SSIDs list parsing from cscan tlv list\n */\nint rtw_parse_ssid_list_tlv(char **list_str, pno_ssid_t *ssid,\n\t\t\t    int max, int *bytes_left)\n{\n\tchar *str;\n\n\tint idx = 0;\n\n\tif ((list_str == NULL) || (*list_str == NULL) || (*bytes_left < 0)) {\n\t\tRTW_INFO(\"%s error paramters\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\tstr = *list_str;\n\twhile (*bytes_left > 0) {\n\n\t\tif (str[0] != CSCAN_TLV_TYPE_SSID_IE) {\n\t\t\t*list_str = str;\n\t\t\tRTW_INFO(\"nssid=%d left_parse=%d %d\\n\", idx, *bytes_left, str[0]);\n\t\t\treturn idx;\n\t\t}\n\n\t\t/* Get proper CSCAN_TLV_TYPE_SSID_IE */\n\t\t*bytes_left -= 1;\n\t\tstr += 1;\n\n\t\tif (str[0] == 0) {\n\t\t\t/* Broadcast SSID */\n\t\t\tssid[idx].SSID_len = 0;\n\t\t\tmemset((char *)ssid[idx].SSID, 0x0, WLAN_SSID_MAXLEN);\n\t\t\t*bytes_left -= 1;\n\t\t\tstr += 1;\n\n\t\t\tRTW_INFO(\"BROADCAST SCAN  left=%d\\n\", *bytes_left);\n\t\t} else if (str[0] <= WLAN_SSID_MAXLEN) {\n\t\t\t/* Get proper SSID size */\n\t\t\tssid[idx].SSID_len = str[0];\n\t\t\t*bytes_left -= 1;\n\t\t\tstr += 1;\n\n\t\t\t/* Get SSID */\n\t\t\tif (ssid[idx].SSID_len > *bytes_left) {\n\t\t\t\tRTW_INFO(\"%s out of memory range len=%d but left=%d\\n\",\n\t\t\t\t\t__func__, ssid[idx].SSID_len, *bytes_left);\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\tmemcpy((char *)ssid[idx].SSID, str, ssid[idx].SSID_len);\n\n\t\t\t*bytes_left -= ssid[idx].SSID_len;\n\t\t\tstr += ssid[idx].SSID_len;\n\n\t\t\tRTW_INFO(\"%s :size=%d left=%d\\n\",\n\t\t\t\t(char *)ssid[idx].SSID, ssid[idx].SSID_len, *bytes_left);\n\t\t} else {\n\t\t\tRTW_INFO(\"### SSID size more that %d\\n\", str[0]);\n\t\t\treturn -1;\n\t\t}\n\n\t\tif (idx++ >  max) {\n\t\t\tRTW_INFO(\"%s number of SSIDs more that %d\\n\", __func__, idx);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t*list_str = str;\n\treturn idx;\n}\n\nint rtw_parse_cipher_list(struct pno_nlo_info *nlo_info, char *list_str)\n{\n\n\tchar *pch, *pnext, *pend;\n\tu8 key_len = 0, index = 0;\n\n\tpch = list_str;\n\n\tif (nlo_info == NULL || list_str == NULL) {\n\t\tRTW_INFO(\"%s error paramters\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\twhile (strlen(pch) != 0) {\n\t\tpnext = strstr(pch, \"key_mgmt=\");\n\t\tif (pnext != NULL) {\n\t\t\tpch = pnext + strlen(CIPHER_IE);\n\t\t\tpend = strstr(pch, \"}\");\n\t\t\tif (strncmp(pch, CIPHER_NONE,\n\t\t\t\t    strlen(CIPHER_NONE)) == 0)\n\t\t\t\tnlo_info->ssid_cipher_info[index] = 0x00;\n\t\t\telse if (strncmp(pch, CIPHER_WPA_PSK,\n\t\t\t\t\t strlen(CIPHER_WPA_PSK)) == 0)\n\t\t\t\tnlo_info->ssid_cipher_info[index] = 0x66;\n\t\t\telse if (strncmp(pch, CIPHER_WPA_EAP,\n\t\t\t\t\t strlen(CIPHER_WPA_EAP)) == 0)\n\t\t\t\tnlo_info->ssid_cipher_info[index] = 0x01;\n\t\t\tindex++;\n\t\t\tpch = pend + 1;\n\t\t} else\n\t\t\tbreak;\n\t}\n\treturn 0;\n}\n\nint rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid,\n\t\t int num, int pno_time, int pno_repeat, int pno_freq_expo_max)\n{\n\n\tint i = 0;\n\tstruct file *fp;\n\tmm_segment_t fs;\n\tloff_t pos = 0;\n\tu8 *source = NULL;\n\tlong len = 0;\n\n\tRTW_INFO(\"+%s+\\n\", __func__);\n\n\tnlo_info->fast_scan_period = pno_time;\n\tnlo_info->ssid_num = num & BIT_LEN_MASK_32(8);\n\tnlo_info->hidden_ssid_num = num & BIT_LEN_MASK_32(8);\n\tnlo_info->slow_scan_period = (pno_time * 2);\n\tnlo_info->fast_scan_iterations = 5;\n\n\tif (nlo_info->hidden_ssid_num > 8)\n\t\tnlo_info->hidden_ssid_num = 8;\n\n\t/* TODO: channel list and probe index is all empty. */\n\tfor (i = 0 ; i < num ; i++) {\n\t\tnlo_info->ssid_length[i]\n\t\t\t= ssid[i].SSID_len;\n\t}\n\n\t/* cipher array */\n\tfp = filp_open(\"/data/misc/wifi/wpa_supplicant.conf\", O_RDONLY,  0644);\n\tif (IS_ERR(fp)) {\n\t\tRTW_INFO(\"Error, wpa_supplicant.conf doesn't exist.\\n\");\n\t\tRTW_INFO(\"Error, cipher array using default value.\\n\");\n\t\treturn 0;\n\t}\n\n\tlen = i_size_read(fp->f_path.dentry->d_inode);\n\tif (len < 0 || len > 2048) {\n\t\tRTW_INFO(\"Error, file size is bigger than 2048.\\n\");\n\t\tRTW_INFO(\"Error, cipher array using default value.\\n\");\n\t\treturn 0;\n\t}\n\n\tfs = get_fs();\n\tset_fs(KERNEL_DS);\n\n\tsource = rtw_zmalloc(2048);\n\n\tif (source != NULL) {\n\t\tlen = vfs_read(fp, source, len, &pos);\n\t\trtw_parse_cipher_list(nlo_info, source);\n\t\trtw_mfree(source, 2048);\n\t}\n\n\tset_fs(fs);\n\tfilp_close(fp, NULL);\n\n\tRTW_INFO(\"-%s-\\n\", __func__);\n\treturn 0;\n}\n\nint rtw_dev_ssid_list_set(struct pno_ssid_list *pno_ssid_list,\n\t\t\t  pno_ssid_t *ssid, u8 num)\n{\n\n\tint i = 0;\n\tif (num > MAX_PNO_LIST_COUNT)\n\t\tnum = MAX_PNO_LIST_COUNT;\n\n\tfor (i = 0 ; i < num ; i++) {\n\t\t_rtw_memcpy(&pno_ssid_list->node[i].SSID,\n\t\t\t    ssid[i].SSID, ssid[i].SSID_len);\n\t\tpno_ssid_list->node[i].SSID_len = ssid[i].SSID_len;\n\t}\n\treturn 0;\n}\n\nint rtw_dev_scan_info_set(_adapter *padapter, pno_ssid_t *ssid,\n\t  unsigned char ch, unsigned char ch_offset, unsigned short bw_mode)\n{\n\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);\n\tstruct pno_scan_info *scan_info = pwrctl->pscan_info;\n\tint i;\n\n\tscan_info->channel_num = MAX_SCAN_LIST_COUNT;\n\tscan_info->orig_ch = ch;\n\tscan_info->orig_bw = bw_mode;\n\tscan_info->orig_40_offset = ch_offset;\n\n\tfor (i = 0 ; i < scan_info->channel_num ; i++) {\n\t\tif (i < 11)\n\t\t\tscan_info->ssid_channel_info[i].active = 1;\n\t\telse\n\t\t\tscan_info->ssid_channel_info[i].active = 0;\n\n\t\tscan_info->ssid_channel_info[i].timeout = 100;\n\n\t\tscan_info->ssid_channel_info[i].tx_power =\n\t\t\tphy_get_tx_power_index(padapter, 0, 0x02, bw_mode, i + 1);\n\n\t\tscan_info->ssid_channel_info[i].channel = i + 1;\n\t}\n\n\tRTW_INFO(\"%s, channel_num: %d, orig_ch: %d, orig_bw: %d orig_40_offset: %d\\n\",\n\t\t __func__, scan_info->channel_num, scan_info->orig_ch,\n\t\t scan_info->orig_bw, scan_info->orig_40_offset);\n\treturn 0;\n}\n\nint rtw_dev_pno_set(struct net_device *net, pno_ssid_t *ssid, int num,\n\t\t    int pno_time, int pno_repeat, int pno_freq_expo_max)\n{\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(net);\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\n\tint ret = -1;\n\n\tif (num == 0) {\n\t\tRTW_INFO(\"%s, nssid is zero, no need to setup pno ssid list\\n\", __func__);\n\t\treturn 0;\n\t}\n\n\tif (pwrctl == NULL) {\n\t\tRTW_INFO(\"%s, ERROR: pwrctl is NULL\\n\", __func__);\n\t\treturn -1;\n\t} else {\n\t\tpwrctl->pnlo_info =\n\t\t\t(pno_nlo_info_t *)rtw_zmalloc(sizeof(pno_nlo_info_t));\n\t\tpwrctl->pno_ssid_list =\n\t\t\t(pno_ssid_list_t *)rtw_zmalloc(sizeof(pno_ssid_list_t));\n\t\tpwrctl->pscan_info =\n\t\t\t(pno_scan_info_t *)rtw_zmalloc(sizeof(pno_scan_info_t));\n\t}\n\n\tif (pwrctl->pnlo_info == NULL ||\n\t    pwrctl->pscan_info == NULL ||\n\t    pwrctl->pno_ssid_list == NULL) {\n\t\tRTW_INFO(\"%s, ERROR: alloc nlo_info, ssid_list, scan_info fail\\n\", __func__);\n\t\tgoto failing;\n\t}\n\n\tpwrctl->wowlan_in_resume = _FALSE;\n\n\tpwrctl->pno_inited = _TRUE;\n\t/* NLO Info */\n\tret = rtw_dev_nlo_info_set(pwrctl->pnlo_info, ssid, num,\n\t\t\t\t   pno_time, pno_repeat, pno_freq_expo_max);\n\n\t/* SSID Info */\n\tret = rtw_dev_ssid_list_set(pwrctl->pno_ssid_list, ssid, num);\n\n\t/* SCAN Info */\n\tret = rtw_dev_scan_info_set(padapter, ssid, pmlmeext->cur_channel,\n\t\t\t    pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);\n\n\tRTW_INFO(\"+%s num: %d, pno_time: %d, pno_repeat:%d, pno_freq_expo_max:%d+\\n\",\n\t\t __func__, num, pno_time, pno_repeat, pno_freq_expo_max);\n\n\treturn 0;\n\nfailing:\n\tif (pwrctl->pnlo_info) {\n\t\trtw_mfree((u8 *)pwrctl->pnlo_info, sizeof(pno_nlo_info_t));\n\t\tpwrctl->pnlo_info = NULL;\n\t}\n\tif (pwrctl->pno_ssid_list) {\n\t\trtw_mfree((u8 *)pwrctl->pno_ssid_list, sizeof(pno_ssid_list_t));\n\t\tpwrctl->pno_ssid_list = NULL;\n\t}\n\tif (pwrctl->pscan_info) {\n\t\trtw_mfree((u8 *)pwrctl->pscan_info, sizeof(pno_scan_info_t));\n\t\tpwrctl->pscan_info = NULL;\n\t}\n\n\treturn -1;\n}\n\n#ifdef CONFIG_PNO_SET_DEBUG\nvoid rtw_dev_pno_debug(struct net_device *net)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(net);\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);\n\tint i = 0, j = 0;\n\n\tRTW_INFO(\"*******NLO_INFO********\\n\");\n\tRTW_INFO(\"ssid_num: %d\\n\", pwrctl->pnlo_info->ssid_num);\n\tRTW_INFO(\"fast_scan_iterations: %d\\n\",\n\t\t pwrctl->pnlo_info->fast_scan_iterations);\n\tRTW_INFO(\"fast_scan_period: %d\\n\", pwrctl->pnlo_info->fast_scan_period);\n\tRTW_INFO(\"slow_scan_period: %d\\n\", pwrctl->pnlo_info->slow_scan_period);\n\n\n\n\tfor (i = 0 ; i < MAX_PNO_LIST_COUNT ; i++) {\n\t\tRTW_INFO(\"%d SSID (%s) length (%d) cipher(%x) channel(%d)\\n\",\n\t\t\ti, pwrctl->pno_ssid_list->node[i].SSID, pwrctl->pnlo_info->ssid_length[i],\n\t\t\tpwrctl->pnlo_info->ssid_cipher_info[i], pwrctl->pnlo_info->ssid_channel_info[i]);\n\t}\n\n\tRTW_INFO(\"******SCAN_INFO******\\n\");\n\tRTW_INFO(\"ch_num: %d\\n\", pwrctl->pscan_info->channel_num);\n\tRTW_INFO(\"orig_ch: %d\\n\", pwrctl->pscan_info->orig_ch);\n\tRTW_INFO(\"orig bw: %d\\n\", pwrctl->pscan_info->orig_bw);\n\tRTW_INFO(\"orig 40 offset: %d\\n\", pwrctl->pscan_info->orig_40_offset);\n\tfor (i = 0 ; i < MAX_SCAN_LIST_COUNT ; i++) {\n\t\tRTW_INFO(\"[%02d] avtive:%d, timeout:%d, tx_power:%d, ch:%02d\\n\",\n\t\t\t i, pwrctl->pscan_info->ssid_channel_info[i].active,\n\t\t\t pwrctl->pscan_info->ssid_channel_info[i].timeout,\n\t\t\t pwrctl->pscan_info->ssid_channel_info[i].tx_power,\n\t\t\t pwrctl->pscan_info->ssid_channel_info[i].channel);\n\t}\n\tRTW_INFO(\"*****************\\n\");\n}\n#endif /* CONFIG_PNO_SET_DEBUG */\n#endif /* CONFIG_PNO_SUPPORT */\n\ninline void rtw_collect_bcn_info(_adapter *adapter)\n{\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\n\tif (!is_client_associated_to_ap(adapter))\n\t\treturn;\n\n\tpmlmeext->cur_bcn_cnt = pmlmeext->bcn_cnt - pmlmeext->last_bcn_cnt;\n\tpmlmeext->last_bcn_cnt = pmlmeext->bcn_cnt;\n\t/*TODO get offset of bcn's timestamp*/\n\t/*pmlmeext->bcn_timestamp;*/\n}\n"
  },
  {
    "path": "core/rtw_xmit.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2019 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTW_XMIT_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\nstatic u8 P802_1H_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0xf8 };\nstatic u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 };\n\nstatic void _init_txservq(struct tx_servq *ptxservq)\n{\n\t_rtw_init_listhead(&ptxservq->tx_pending);\n\t_rtw_init_queue(&ptxservq->sta_pending);\n\tptxservq->qcnt = 0;\n}\n\n\nvoid\t_rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv)\n{\n\n\n\t_rtw_memset((unsigned char *)psta_xmitpriv, 0, sizeof(struct sta_xmit_priv));\n\n\t_rtw_spinlock_init(&psta_xmitpriv->lock);\n\n\t/* for(i = 0 ; i < MAX_NUMBLKS; i++) */\n\t/*\t_init_txservq(&(psta_xmitpriv->blk_q[i])); */\n\n\t_init_txservq(&psta_xmitpriv->be_q);\n\t_init_txservq(&psta_xmitpriv->bk_q);\n\t_init_txservq(&psta_xmitpriv->vi_q);\n\t_init_txservq(&psta_xmitpriv->vo_q);\n\t_rtw_init_listhead(&psta_xmitpriv->legacy_dz);\n\t_rtw_init_listhead(&psta_xmitpriv->apsd);\n\n\n}\n\nvoid rtw_init_xmit_block(_adapter *padapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\t_rtw_spinlock_init(&dvobj->xmit_block_lock);\n\tdvobj->xmit_block = XMIT_BLOCK_NONE;\n\n}\nvoid rtw_free_xmit_block(_adapter *padapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\t_rtw_spinlock_free(&dvobj->xmit_block_lock);\n}\n\ns32\t_rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter)\n{\n\tint i;\n\tstruct xmit_buf *pxmitbuf;\n\tstruct xmit_frame *pxframe;\n\tsint\tres = _SUCCESS;\n\n\n\t/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */\n\t/* _rtw_memset((unsigned char *)pxmitpriv, 0, sizeof(struct xmit_priv)); */\n\n\t_rtw_spinlock_init(&pxmitpriv->lock);\n\t_rtw_spinlock_init(&pxmitpriv->lock_sctx);\n\t_rtw_init_sema(&pxmitpriv->xmit_sema, 0);\n\n\t/*\n\tPlease insert all the queue initializaiton using _rtw_init_queue below\n\t*/\n\n\tpxmitpriv->adapter = padapter;\n\n\t/* for(i = 0 ; i < MAX_NUMBLKS; i++) */\n\t/*\t_rtw_init_queue(&pxmitpriv->blk_strms[i]); */\n\n\t_rtw_init_queue(&pxmitpriv->be_pending);\n\t_rtw_init_queue(&pxmitpriv->bk_pending);\n\t_rtw_init_queue(&pxmitpriv->vi_pending);\n\t_rtw_init_queue(&pxmitpriv->vo_pending);\n\t_rtw_init_queue(&pxmitpriv->bm_pending);\n\n\t/* _rtw_init_queue(&pxmitpriv->legacy_dz_queue); */\n\t/* _rtw_init_queue(&pxmitpriv->apsd_queue); */\n\n\t_rtw_init_queue(&pxmitpriv->free_xmit_queue);\n\n\t/*\n\tPlease allocate memory with the sz = (struct xmit_frame) * NR_XMITFRAME,\n\tand initialize free_xmit_frame below.\n\tPlease also apply  free_txobj to link_up all the xmit_frames...\n\t*/\n\n\tpxmitpriv->pallocated_frame_buf = rtw_zvmalloc(NR_XMITFRAME * sizeof(struct xmit_frame) + 4);\n\n\tif (pxmitpriv->pallocated_frame_buf  == NULL) {\n\t\tpxmitpriv->pxmit_frame_buf = NULL;\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tpxmitpriv->pxmit_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_frame_buf), 4);\n\t/* pxmitpriv->pxmit_frame_buf = pxmitpriv->pallocated_frame_buf + 4 - */\n\t/*\t\t\t\t\t\t((SIZE_PTR) (pxmitpriv->pallocated_frame_buf) &3); */\n\n\tpxframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;\n\n\tfor (i = 0; i < NR_XMITFRAME; i++) {\n\t\t_rtw_init_listhead(&(pxframe->list));\n\n\t\tpxframe->padapter = padapter;\n\t\tpxframe->frame_tag = NULL_FRAMETAG;\n\n\t\tpxframe->pkt = NULL;\n\n\t\tpxframe->buf_addr = NULL;\n\t\tpxframe->pxmitbuf = NULL;\n\n\t\trtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xmit_queue.queue));\n\n\t\tpxframe++;\n\t}\n\n\tpxmitpriv->free_xmitframe_cnt = NR_XMITFRAME;\n\n\tpxmitpriv->frag_len = MAX_FRAG_THRESHOLD;\n\n\n\t/* init xmit_buf */\n\t_rtw_init_queue(&pxmitpriv->free_xmitbuf_queue);\n\t_rtw_init_queue(&pxmitpriv->pending_xmitbuf_queue);\n\n\tpxmitpriv->pallocated_xmitbuf = rtw_zvmalloc(NR_XMITBUFF * sizeof(struct xmit_buf) + 4);\n\n\tif (pxmitpriv->pallocated_xmitbuf  == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpxmitpriv->pxmitbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmitbuf), 4);\n\t/* pxmitpriv->pxmitbuf = pxmitpriv->pallocated_xmitbuf + 4 - */\n\t/*\t\t\t\t\t\t((SIZE_PTR) (pxmitpriv->pallocated_xmitbuf) &3); */\n\n\tpxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;\n\n\tfor (i = 0; i < NR_XMITBUFF; i++) {\n\t\t_rtw_init_listhead(&pxmitbuf->list);\n\n\t\tpxmitbuf->priv_data = NULL;\n\t\tpxmitbuf->padapter = padapter;\n\t\tpxmitbuf->buf_tag = XMITBUF_DATA;\n\n\t\t/* Tx buf allocation may fail sometimes, so sleep and retry. */\n\t\tres = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE);\n\t\tif (res == _FAIL) {\n\t\t\trtw_msleep_os(10);\n\t\t\tres = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE);\n\t\t\tif (res == _FAIL)\n\t\t\t\tgoto exit;\n\t\t}\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t\tpxmitbuf->phead = pxmitbuf->pbuf;\n\t\tpxmitbuf->pend = pxmitbuf->pbuf + MAX_XMITBUF_SZ;\n\t\tpxmitbuf->len = 0;\n\t\tpxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;\n#endif\n\n\t\tpxmitbuf->flags = XMIT_VO_QUEUE;\n\n\t\trtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmitbuf_queue.queue));\n#ifdef DBG_XMIT_BUF\n\t\tpxmitbuf->no = i;\n#endif\n\n\t\tpxmitbuf++;\n\n\t}\n\n\tpxmitpriv->free_xmitbuf_cnt = NR_XMITBUFF;\n\n\t/* init xframe_ext queue,  the same count as extbuf */\n\t_rtw_init_queue(&pxmitpriv->free_xframe_ext_queue);\n\n\tpxmitpriv->xframe_ext_alloc_addr = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_frame) + 4);\n\n\tif (pxmitpriv->xframe_ext_alloc_addr  == NULL) {\n\t\tpxmitpriv->xframe_ext = NULL;\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\tpxmitpriv->xframe_ext = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->xframe_ext_alloc_addr), 4);\n\tpxframe = (struct xmit_frame *)pxmitpriv->xframe_ext;\n\n\tfor (i = 0; i < NR_XMIT_EXTBUFF; i++) {\n\t\t_rtw_init_listhead(&(pxframe->list));\n\n\t\tpxframe->padapter = padapter;\n\t\tpxframe->frame_tag = NULL_FRAMETAG;\n\n\t\tpxframe->pkt = NULL;\n\n\t\tpxframe->buf_addr = NULL;\n\t\tpxframe->pxmitbuf = NULL;\n\n\t\tpxframe->ext_tag = 1;\n\n\t\trtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xframe_ext_queue.queue));\n\n\t\tpxframe++;\n\t}\n\tpxmitpriv->free_xframe_ext_cnt = NR_XMIT_EXTBUFF;\n\n\t/* Init xmit extension buff */\n\t_rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue);\n\n\tpxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4);\n\n\tif (pxmitpriv->pallocated_xmit_extbuf  == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4);\n\n\tpxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;\n\n\tfor (i = 0; i < NR_XMIT_EXTBUFF; i++) {\n\t\t_rtw_init_listhead(&pxmitbuf->list);\n\n\t\tpxmitbuf->priv_data = NULL;\n\t\tpxmitbuf->padapter = padapter;\n\t\tpxmitbuf->buf_tag = XMITBUF_MGNT;\n\n\t\tres = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, MAX_XMIT_EXTBUF_SZ + XMITBUF_ALIGN_SZ, _TRUE);\n\t\tif (res == _FAIL) {\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t\tpxmitbuf->phead = pxmitbuf->pbuf;\n\t\tpxmitbuf->pend = pxmitbuf->pbuf + MAX_XMIT_EXTBUF_SZ;\n\t\tpxmitbuf->len = 0;\n\t\tpxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;\n#endif\n\n\t\trtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue));\n#ifdef DBG_XMIT_BUF_EXT\n\t\tpxmitbuf->no = i;\n#endif\n\t\tpxmitbuf++;\n\n\t}\n\n\tpxmitpriv->free_xmit_extbuf_cnt = NR_XMIT_EXTBUFF;\n\n\tfor (i = 0; i < CMDBUF_MAX; i++) {\n\t\tpxmitbuf = &pxmitpriv->pcmd_xmitbuf[i];\n\t\tif (pxmitbuf) {\n\t\t\t_rtw_init_listhead(&pxmitbuf->list);\n\n\t\t\tpxmitbuf->priv_data = NULL;\n\t\t\tpxmitbuf->padapter = padapter;\n\t\t\tpxmitbuf->buf_tag = XMITBUF_CMD;\n\n\t\t\tres = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ, _TRUE);\n\t\t\tif (res == _FAIL) {\n\t\t\t\tres = _FAIL;\n\t\t\t\tgoto exit;\n\t\t\t}\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t\t\tpxmitbuf->phead = pxmitbuf->pbuf;\n\t\t\tpxmitbuf->pend = pxmitbuf->pbuf + MAX_CMDBUF_SZ;\n\t\t\tpxmitbuf->len = 0;\n\t\t\tpxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;\n#endif\n\t\t\tpxmitbuf->alloc_sz = MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ;\n\t\t}\n\t}\n\n\trtw_alloc_hwxmits(padapter);\n\trtw_init_hwxmits(pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);\n\n\tfor (i = 0; i < 4; i++)\n\t\tpxmitpriv->wmm_para_seq[i] = i;\n\n#ifdef CONFIG_USB_HCI\n\tpxmitpriv->txirp_cnt = 1;\n\n\t_rtw_init_sema(&(pxmitpriv->tx_retevt), 0);\n\n\t/* per AC pending irp */\n\tpxmitpriv->beq_cnt = 0;\n\tpxmitpriv->bkq_cnt = 0;\n\tpxmitpriv->viq_cnt = 0;\n\tpxmitpriv->voq_cnt = 0;\n#endif\n\n\n#ifdef CONFIG_XMIT_ACK\n\tpxmitpriv->ack_tx = _FALSE;\n\t_rtw_mutex_init(&pxmitpriv->ack_tx_mutex);\n\trtw_sctx_init(&pxmitpriv->ack_tx_ops, 0);\n#endif\n\n#ifdef CONFIG_TX_AMSDU\n\trtw_init_timer(&(pxmitpriv->amsdu_vo_timer), padapter,\n\t\trtw_amsdu_vo_timeout_handler, padapter);\n\tpxmitpriv->amsdu_vo_timeout = RTW_AMSDU_TIMER_UNSET;\n\n\trtw_init_timer(&(pxmitpriv->amsdu_vi_timer), padapter,\n\t\trtw_amsdu_vi_timeout_handler, padapter);\n\tpxmitpriv->amsdu_vi_timeout = RTW_AMSDU_TIMER_UNSET;\n\n\trtw_init_timer(&(pxmitpriv->amsdu_be_timer), padapter,\n\t\trtw_amsdu_be_timeout_handler, padapter);\n\tpxmitpriv->amsdu_be_timeout = RTW_AMSDU_TIMER_UNSET;\n\n\trtw_init_timer(&(pxmitpriv->amsdu_bk_timer), padapter,\n\t\trtw_amsdu_bk_timeout_handler, padapter);\n\tpxmitpriv->amsdu_bk_timeout = RTW_AMSDU_TIMER_UNSET;\n\n\tpxmitpriv->amsdu_debug_set_timer = 0;\n\tpxmitpriv->amsdu_debug_timeout = 0;\n\tpxmitpriv->amsdu_debug_coalesce_one = 0;\n\tpxmitpriv->amsdu_debug_coalesce_two = 0;\n#endif\n#ifdef DBG_TXBD_DESC_DUMP\n\tpxmitpriv->dump_txbd_desc = 0;\n#endif\n\trtw_init_xmit_block(padapter);\n\trtw_hal_init_xmit_priv(padapter);\n\nexit:\n\n\n\treturn res;\n}\n\nvoid  rtw_mfree_xmit_priv_lock(struct xmit_priv *pxmitpriv);\nvoid  rtw_mfree_xmit_priv_lock(struct xmit_priv *pxmitpriv)\n{\n\t_rtw_spinlock_free(&pxmitpriv->lock);\n\t_rtw_free_sema(&pxmitpriv->xmit_sema);\n\n\t_rtw_spinlock_free(&pxmitpriv->be_pending.lock);\n\t_rtw_spinlock_free(&pxmitpriv->bk_pending.lock);\n\t_rtw_spinlock_free(&pxmitpriv->vi_pending.lock);\n\t_rtw_spinlock_free(&pxmitpriv->vo_pending.lock);\n\t_rtw_spinlock_free(&pxmitpriv->bm_pending.lock);\n\n\t/* _rtw_spinlock_free(&pxmitpriv->legacy_dz_queue.lock); */\n\t/* _rtw_spinlock_free(&pxmitpriv->apsd_queue.lock); */\n\n\t_rtw_spinlock_free(&pxmitpriv->free_xmit_queue.lock);\n\t_rtw_spinlock_free(&pxmitpriv->free_xmitbuf_queue.lock);\n\t_rtw_spinlock_free(&pxmitpriv->pending_xmitbuf_queue.lock);\n}\n\n\nvoid _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv)\n{\n\tint i;\n\t_adapter *padapter = pxmitpriv->adapter;\n\tstruct xmit_frame\t*pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;\n\tstruct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;\n\n\n\trtw_hal_free_xmit_priv(padapter);\n\n\trtw_mfree_xmit_priv_lock(pxmitpriv);\n\n\tif (pxmitpriv->pxmit_frame_buf == NULL)\n\t\tgoto out;\n\n\tfor (i = 0; i < NR_XMITFRAME; i++) {\n\t\trtw_os_xmit_complete(padapter, pxmitframe);\n\n\t\tpxmitframe++;\n\t}\n\n\tfor (i = 0; i < NR_XMITBUFF; i++) {\n\t\trtw_os_xmit_resource_free(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE);\n\n\t\tpxmitbuf++;\n\t}\n\n\tif (pxmitpriv->pallocated_frame_buf)\n\t\trtw_vmfree(pxmitpriv->pallocated_frame_buf, NR_XMITFRAME * sizeof(struct xmit_frame) + 4);\n\n\n\tif (pxmitpriv->pallocated_xmitbuf)\n\t\trtw_vmfree(pxmitpriv->pallocated_xmitbuf, NR_XMITBUFF * sizeof(struct xmit_buf) + 4);\n\n\t/* free xframe_ext queue,  the same count as extbuf */\n\tif ((pxmitframe = (struct xmit_frame *)pxmitpriv->xframe_ext)) {\n\t\tfor (i = 0; i < NR_XMIT_EXTBUFF; i++) {\n\t\t\trtw_os_xmit_complete(padapter, pxmitframe);\n\t\t\tpxmitframe++;\n\t\t}\n\t}\n\tif (pxmitpriv->xframe_ext_alloc_addr)\n\t\trtw_vmfree(pxmitpriv->xframe_ext_alloc_addr, NR_XMIT_EXTBUFF * sizeof(struct xmit_frame) + 4);\n\t_rtw_spinlock_free(&pxmitpriv->free_xframe_ext_queue.lock);\n\n\t/* free xmit extension buff */\n\t_rtw_spinlock_free(&pxmitpriv->free_xmit_extbuf_queue.lock);\n\n\tpxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;\n\tfor (i = 0; i < NR_XMIT_EXTBUFF; i++) {\n\t\trtw_os_xmit_resource_free(padapter, pxmitbuf, (MAX_XMIT_EXTBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE);\n\n\t\tpxmitbuf++;\n\t}\n\n\tif (pxmitpriv->pallocated_xmit_extbuf)\n\t\trtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4);\n\n\tfor (i = 0; i < CMDBUF_MAX; i++) {\n\t\tpxmitbuf = &pxmitpriv->pcmd_xmitbuf[i];\n\t\tif (pxmitbuf != NULL)\n\t\t\trtw_os_xmit_resource_free(padapter, pxmitbuf, MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ , _TRUE);\n\t}\n\n\trtw_free_hwxmits(padapter);\n\n#ifdef CONFIG_XMIT_ACK\n\t_rtw_mutex_free(&pxmitpriv->ack_tx_mutex);\n#endif\n\trtw_free_xmit_block(padapter);\nout:\n\treturn;\n}\n\nu8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta)\n{\n\tu8 bw;\n\n\tbw = sta->cmn.bw_mode;\n\tif (MLME_STATE(adapter) & WIFI_ASOC_STATE) {\n\t\tif (adapter->mlmeextpriv.cur_channel <= 14)\n\t\t\tbw = rtw_min(bw, ADAPTER_TX_BW_2G(adapter));\n\t\telse\n\t\t\tbw = rtw_min(bw, ADAPTER_TX_BW_5G(adapter));\n\t}\n\n\treturn bw;\n}\n\nvoid rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u32 *r_bmp_vht)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\tu8 fix_bw = 0xFF;\n\tu16 bmp_cck_ofdm = 0;\n\tu32 bmp_ht = 0;\n\tu32 bmp_vht = 0;\n\tint i;\n\n\tif (adapter->fix_rate != 0xFF && adapter->fix_bw != 0xFF)\n\t\tfix_bw = adapter->fix_bw;\n\n\t/* TODO: adapter->fix_rate */\n\n\tfor (i = 0; i < macid_ctl->num; i++) {\n\t\tif (!rtw_macid_is_used(macid_ctl, i))\n\t\t\tcontinue;\n\t\tif (!rtw_macid_is_iface_specific(macid_ctl, i, adapter))\n\t\t\tcontinue;\n\n\t\tif (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */\n\t\t\tbmp_cck_ofdm |= macid_ctl->rate_bmp0[i] & 0x00000FFF;\n\n\t\t/* bypass mismatch bandwidth for HT, VHT */\n\t\tif ((fix_bw != 0xFF && fix_bw != bw) || (fix_bw == 0xFF && macid_ctl->bw[i] != bw))\n\t\t\tcontinue;\n\n\t\tif (macid_ctl->vht_en[i])\n\t\t\tbmp_vht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);\n\t\telse\n\t\t\tbmp_ht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);\n\t}\n\n\t/* TODO: mlmeext->tx_rate*/\n\n\tif (r_bmp_cck_ofdm)\n\t\t*r_bmp_cck_ofdm = bmp_cck_ofdm;\n\tif (r_bmp_ht)\n\t\t*r_bmp_ht = bmp_ht;\n\tif (r_bmp_vht)\n\t\t*r_bmp_vht = bmp_vht;\n}\n\nvoid rtw_get_shared_macid_tx_rate_bmp_by_bw(struct dvobj_priv *dvobj, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u32 *r_bmp_vht)\n{\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\tu16 bmp_cck_ofdm = 0;\n\tu32 bmp_ht = 0;\n\tu32 bmp_vht = 0;\n\tint i;\n\n\tfor (i = 0; i < macid_ctl->num; i++) {\n\t\tif (!rtw_macid_is_used(macid_ctl, i))\n\t\t\tcontinue;\n\t\tif (!rtw_macid_is_iface_shared(macid_ctl, i))\n\t\t\tcontinue;\n\n\t\tif (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */\n\t\t\tbmp_cck_ofdm |= macid_ctl->rate_bmp0[i] & 0x00000FFF;\n\n\t\t/* bypass mismatch bandwidth for HT, VHT */\n\t\tif (macid_ctl->bw[i] != bw)\n\t\t\tcontinue;\n\n\t\tif (macid_ctl->vht_en[i])\n\t\t\tbmp_vht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);\n\t\telse\n\t\t\tbmp_ht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);\n\t}\n\n\tif (r_bmp_cck_ofdm)\n\t\t*r_bmp_cck_ofdm = bmp_cck_ofdm;\n\tif (r_bmp_ht)\n\t\t*r_bmp_ht = bmp_ht;\n\tif (r_bmp_vht)\n\t\t*r_bmp_vht = bmp_vht;\n}\n\nvoid rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj)\n{\n\tstruct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);\n\t_adapter *adapter = dvobj_get_primary_adapter(dvobj);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tu8 bw;\n\tu16 bmp_cck_ofdm, tmp_cck_ofdm;\n\tu32 bmp_ht, tmp_ht, ori_bmp_ht[2];\n\tu8 ori_highest_ht_rate_bw_bmp;\n\tu32 bmp_vht, tmp_vht, ori_bmp_vht[4];\n\tu8 ori_highest_vht_rate_bw_bmp;\n\tint i;\n\n\t/* backup the original ht & vht highest bw bmp */\n\tori_highest_ht_rate_bw_bmp = rf_ctl->highest_ht_rate_bw_bmp;\n\tori_highest_vht_rate_bw_bmp = rf_ctl->highest_vht_rate_bw_bmp;\n\n\tfor (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) {\n\t\t/* backup the original ht & vht bmp */\n\t\tif (bw <= CHANNEL_WIDTH_40)\n\t\t\tori_bmp_ht[bw] = rf_ctl->rate_bmp_ht_by_bw[bw];\n\t\tif (bw <= CHANNEL_WIDTH_160)\n\t\t\tori_bmp_vht[bw] = rf_ctl->rate_bmp_vht_by_bw[bw];\n\n\t\tbmp_cck_ofdm = bmp_ht = bmp_vht = 0;\n\t\tif (hal_is_bw_support(dvobj_get_primary_adapter(dvobj), bw)) {\n\t\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\t\tif (!dvobj->padapters[i])\n\t\t\t\t\tcontinue;\n\t\t\t\trtw_get_adapter_tx_rate_bmp_by_bw(dvobj->padapters[i], bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht);\n\t\t\t\tbmp_cck_ofdm |= tmp_cck_ofdm;\n\t\t\t\tbmp_ht |= tmp_ht;\n\t\t\t\tbmp_vht |= tmp_vht;\n\t\t\t}\n\t\t\trtw_get_shared_macid_tx_rate_bmp_by_bw(dvobj, bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht);\n\t\t\tbmp_cck_ofdm |= tmp_cck_ofdm;\n\t\t\tbmp_ht |= tmp_ht;\n\t\t\tbmp_vht |= tmp_vht;\n\t\t}\n\t\tif (bw == CHANNEL_WIDTH_20)\n\t\t\trf_ctl->rate_bmp_cck_ofdm = bmp_cck_ofdm;\n\t\tif (bw <= CHANNEL_WIDTH_40)\n\t\t\trf_ctl->rate_bmp_ht_by_bw[bw] = bmp_ht;\n\t\tif (bw <= CHANNEL_WIDTH_160)\n\t\t\trf_ctl->rate_bmp_vht_by_bw[bw] = bmp_vht;\n\t}\n\n#ifndef DBG_HIGHEST_RATE_BMP_BW_CHANGE\n#define DBG_HIGHEST_RATE_BMP_BW_CHANGE 0\n#endif\n\n\t{\n\t\tu8 highest_rate_bw;\n\t\tu8 highest_rate_bw_bmp;\n\t\tu8 update_ht_rs = _FALSE;\n\t\tu8 update_vht_rs = _FALSE;\n\n\t\thighest_rate_bw_bmp = BW_CAP_20M;\n\t\thighest_rate_bw = CHANNEL_WIDTH_20;\n\t\tfor (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_40; bw++) {\n\t\t\tif (rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw] < rf_ctl->rate_bmp_ht_by_bw[bw]) {\n\t\t\t\thighest_rate_bw_bmp = ch_width_to_bw_cap(bw);\n\t\t\t\thighest_rate_bw = bw;\n\t\t\t} else if (rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw] == rf_ctl->rate_bmp_ht_by_bw[bw])\n\t\t\t\thighest_rate_bw_bmp |= ch_width_to_bw_cap(bw);\n\t\t}\n\t\trf_ctl->highest_ht_rate_bw_bmp = highest_rate_bw_bmp;\n\n\t\tif (ori_highest_ht_rate_bw_bmp != rf_ctl->highest_ht_rate_bw_bmp\n\t\t\t|| largest_bit(ori_bmp_ht[highest_rate_bw]) != largest_bit(rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw])\n\t\t) {\n\t\t\tif (DBG_HIGHEST_RATE_BMP_BW_CHANGE) {\n\t\t\t\tRTW_INFO(\"highest_ht_rate_bw_bmp:0x%02x=>0x%02x\\n\", ori_highest_ht_rate_bw_bmp, rf_ctl->highest_ht_rate_bw_bmp);\n\t\t\t\tRTW_INFO(\"rate_bmp_ht_by_bw[%u]:0x%08x=>0x%08x\\n\", highest_rate_bw, ori_bmp_ht[highest_rate_bw], rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw]);\n\t\t\t}\n\t\t\tupdate_ht_rs = _TRUE;\n\t\t}\n\n\t\thighest_rate_bw_bmp = BW_CAP_20M;\n\t\thighest_rate_bw = CHANNEL_WIDTH_20;\n\t\tfor (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) {\n\t\t\tif (rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw] < rf_ctl->rate_bmp_vht_by_bw[bw]) {\n\t\t\t\thighest_rate_bw_bmp = ch_width_to_bw_cap(bw);\n\t\t\t\thighest_rate_bw = bw;\n\t\t\t} else if (rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw] == rf_ctl->rate_bmp_vht_by_bw[bw])\n\t\t\t\thighest_rate_bw_bmp |= ch_width_to_bw_cap(bw);\n\t\t}\n\t\trf_ctl->highest_vht_rate_bw_bmp = highest_rate_bw_bmp;\n\n\t\tif (ori_highest_vht_rate_bw_bmp != rf_ctl->highest_vht_rate_bw_bmp\n\t\t\t|| largest_bit(ori_bmp_vht[highest_rate_bw]) != largest_bit(rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw])\n\t\t) {\n\t\t\tif (DBG_HIGHEST_RATE_BMP_BW_CHANGE) {\n\t\t\t\tRTW_INFO(\"highest_vht_rate_bw_bmp:0x%02x=>0x%02x\\n\", ori_highest_vht_rate_bw_bmp, rf_ctl->highest_vht_rate_bw_bmp);\n\t\t\t\tRTW_INFO(\"rate_bmp_vht_by_bw[%u]:0x%08x=>0x%08x\\n\", highest_rate_bw, ori_bmp_vht[highest_rate_bw], rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw]);\n\t\t\t}\n\t\t\tupdate_vht_rs = _TRUE;\n\t\t}\n\n\t\t/* TODO: per rfpath and rate section handling? */\n\t\tif (update_ht_rs == _TRUE || update_vht_rs == _TRUE)\n\t\t\trtw_hal_set_tx_power_level(dvobj_get_primary_adapter(dvobj), hal_data->current_channel);\n\t}\n}\n\ninline u16 rtw_get_tx_rate_bmp_cck_ofdm(struct dvobj_priv *dvobj)\n{\n\tstruct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);\n\n\treturn rf_ctl->rate_bmp_cck_ofdm;\n}\n\ninline u32 rtw_get_tx_rate_bmp_ht_by_bw(struct dvobj_priv *dvobj, u8 bw)\n{\n\tstruct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);\n\n\treturn rf_ctl->rate_bmp_ht_by_bw[bw];\n}\n\ninline u32 rtw_get_tx_rate_bmp_vht_by_bw(struct dvobj_priv *dvobj, u8 bw)\n{\n\tstruct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);\n\n\treturn rf_ctl->rate_bmp_vht_by_bw[bw];\n}\n\nu8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw)\n{\n\tstruct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);\n\tu8 bw;\n\tu8 bw_bmp = 0;\n\tu32 rate_bmp;\n\n\tif (!IS_HT_RATE(rate)) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\trate_bmp = 1 << (rate - MGN_MCS0);\n\n\tif (max_bw > CHANNEL_WIDTH_40)\n\t\tmax_bw = CHANNEL_WIDTH_40;\n\n\tfor (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) {\n\t\t/* RA may use lower rate for retry */\n\t\tif (rf_ctl->rate_bmp_ht_by_bw[bw] >= rate_bmp)\n\t\t\tbw_bmp |= ch_width_to_bw_cap(bw);\n\t}\n\nexit:\n\treturn bw_bmp;\n}\n\nu8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw)\n{\n\tstruct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);\n\tu8 bw;\n\tu8 bw_bmp = 0;\n\tu32 rate_bmp;\n\n\tif (!IS_VHT_RATE(rate)) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\trate_bmp = 1 << (rate - MGN_VHT1SS_MCS0);\n\n\tif (max_bw > CHANNEL_WIDTH_160)\n\t\tmax_bw = CHANNEL_WIDTH_160;\n\n\tfor (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) {\n\t\t/* RA may use lower rate for retry */\n\t\tif (rf_ctl->rate_bmp_vht_by_bw[bw] >= rate_bmp)\n\t\t\tbw_bmp |= ch_width_to_bw_cap(bw);\n\t}\n\nexit:\n\treturn bw_bmp;\n}\n\nu8 query_ra_short_GI(struct sta_info *psta, u8 bw)\n{\n\tu8\tsgi = _FALSE, sgi_20m = _FALSE, sgi_40m = _FALSE, sgi_80m = _FALSE;\n\n#ifdef CONFIG_80211N_HT\n#ifdef CONFIG_80211AC_VHT\n\tif (psta->vhtpriv.vht_option)\n\t\tsgi_80m = psta->vhtpriv.sgi_80m;\n#endif\n\tsgi_20m = psta->htpriv.sgi_20m;\n\tsgi_40m = psta->htpriv.sgi_40m;\n#endif\n\n\tswitch (bw) {\n\tcase CHANNEL_WIDTH_80:\n\t\tsgi = sgi_80m;\n\t\tbreak;\n\tcase CHANNEL_WIDTH_40:\n\t\tsgi = sgi_40m;\n\t\tbreak;\n\tcase CHANNEL_WIDTH_20:\n\tdefault:\n\t\tsgi = sgi_20m;\n\t\tbreak;\n\t}\n\n\treturn sgi;\n}\n\nstatic void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitframe)\n{\n\tu32\tsz;\n\tstruct pkt_attrib\t*pattrib = &pxmitframe->attrib;\n\t/* struct sta_info\t*psta = pattrib->psta; */\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\t/*\n\t\tif(pattrib->psta)\n\t\t{\n\t\t\tpsta = pattrib->psta;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tRTW_INFO(\"%s, call rtw_get_stainfo()\\n\", __func__);\n\t\t\tpsta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] );\n\t\t}\n\n\t\tif(psta==NULL)\n\t\t{\n\t\t\tRTW_INFO(\"%s, psta==NUL\\n\", __func__);\n\t\t\treturn;\n\t\t}\n\n\t\tif(!(psta->state &_FW_LINKED))\n\t\t{\n\t\t\tRTW_INFO(\"%s, psta->state(0x%x) != _FW_LINKED\\n\", __func__, psta->state);\n\t\t\treturn;\n\t\t}\n\t*/\n\n\tif (pattrib->nr_frags != 1)\n\t\tsz = padapter->xmitpriv.frag_len;\n\telse /* no frag */\n\t\tsz = pattrib->last_txcmdsz;\n\n\t/* (1) RTS_Threshold is compared to the MPDU, not MSDU. */\n\t/* (2) If there are more than one frag in  this MSDU, only the first frag uses protection frame. */\n\t/*\t\tOther fragments are protected by previous fragment. */\n\t/*\t\tSo we only need to check the length of first fragment. */\n\tif (pmlmeext->cur_wireless_mode < WIRELESS_11_24N  || padapter->registrypriv.wifi_spec) {\n\t\tif (sz > padapter->registrypriv.rts_thresh)\n\t\t\tpattrib->vcs_mode = RTS_CTS;\n\t\telse {\n\t\t\tif (pattrib->rtsen)\n\t\t\t\tpattrib->vcs_mode = RTS_CTS;\n\t\t\telse if (pattrib->cts2self)\n\t\t\t\tpattrib->vcs_mode = CTS_TO_SELF;\n\t\t\telse\n\t\t\t\tpattrib->vcs_mode = NONE_VCS;\n\t\t}\n\t} else {\n\t\twhile (_TRUE) {\n#if 0 /* Todo */\n\t\t\t/* check IOT action */\n\t\t\tif (pHTInfo->IOTAction & HT_IOT_ACT_FORCED_CTS2SELF) {\n\t\t\t\tpattrib->vcs_mode = CTS_TO_SELF;\n\t\t\t\tpattrib->rts_rate = MGN_24M;\n\t\t\t\tbreak;\n\t\t\t} else if (pHTInfo->IOTAction & (HT_IOT_ACT_FORCED_RTS | HT_IOT_ACT_PURE_N_MODE)) {\n\t\t\t\tpattrib->vcs_mode = RTS_CTS;\n\t\t\t\tpattrib->rts_rate = MGN_24M;\n\t\t\t\tbreak;\n\t\t\t}\n#endif\n\n\t\t\t/* IOT action */\n\t\t\tif ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS) && (pattrib->ampdu_en == _TRUE) &&\n\t\t\t    (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) {\n\t\t\t\tpattrib->vcs_mode = CTS_TO_SELF;\n\t\t\t\tbreak;\n\t\t\t}\n\n\n\t\t\t/* check ERP protection */\n\t\t\tif (pattrib->rtsen || pattrib->cts2self) {\n\t\t\t\tif (pattrib->rtsen)\n\t\t\t\t\tpattrib->vcs_mode = RTS_CTS;\n\t\t\t\telse if (pattrib->cts2self)\n\t\t\t\t\tpattrib->vcs_mode = CTS_TO_SELF;\n\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* check HT op mode */\n\t\t\tif (pattrib->ht_en) {\n\t\t\t\tu8 HTOpMode = pmlmeinfo->HT_protection;\n\t\t\t\tif ((pmlmeext->cur_bwmode && (HTOpMode == 2 || HTOpMode == 3)) ||\n\t\t\t\t    (!pmlmeext->cur_bwmode && HTOpMode == 3)) {\n\t\t\t\t\tpattrib->vcs_mode = RTS_CTS;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* check rts */\n\t\t\tif (sz > padapter->registrypriv.rts_thresh) {\n\t\t\t\tpattrib->vcs_mode = RTS_CTS;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* to do list: check MIMO power save condition. */\n\n\t\t\t/* check AMPDU aggregation for TXOP */\n\t\t\tif ((pattrib->ampdu_en == _TRUE) && (!IS_HARDWARE_TYPE_8812(padapter))) {\n\t\t\t\tpattrib->vcs_mode = RTS_CTS;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tpattrib->vcs_mode = NONE_VCS;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* for debug : force driver control vrtl_carrier_sense. */\n\tif (padapter->driver_vcs_en == 1) {\n\t\t/* u8 driver_vcs_en; */ /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */\n\t\t/* u8 driver_vcs_type; */ /* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */\n\t\tpattrib->vcs_mode = padapter->driver_vcs_type;\n\t}\n\n}\n\n#ifdef CONFIG_WMMPS_STA\n/*\n * update_attrib_trigger_frame_info\n * For Station mode, if a specific TID of driver setting and an AP support uapsd function, the data \n * frame with corresponding TID will be a trigger frame when driver is in wmm power saving mode.\n * \n * Arguments:\n * @padapter: _adapter pointer.\n * @pattrib: pkt_attrib pointer.\n *\n * Auther: Arvin Liu\n * Date: 2017/06/05\n */\nstatic void update_attrib_trigger_frame_info(_adapter *padapter, struct pkt_attrib *pattrib) {\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct pwrctrl_priv \t*pwrpriv = adapter_to_pwrctl(padapter); \n\tstruct qos_priv \t*pqospriv = &pmlmepriv->qospriv;\n\tu8 trigger_frame_en = 0;\n\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {\n\t\tif ((pwrpriv->pwr_mode == PS_MODE_MIN) || (pwrpriv->pwr_mode == PS_MODE_MAX)) {\n\t\t\tif((pqospriv->uapsd_ap_supported) && ((pqospriv->uapsd_tid & BIT(pattrib->priority)) == _TRUE)) {\n\t\t\t\ttrigger_frame_en = 1;\n\t\t\t\tRTW_INFO(\"[WMMPS]\"FUNC_ADPT_FMT\": This is a Trigger Frame\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\t}\n\t\t}\n\t}\n\n\tpattrib->trigger_frame = trigger_frame_en;\n}\n#endif /* CONFIG_WMMPS_STA */\n\nstatic void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta)\n{\n\tstruct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv;\n\tu8 bw;\n\n\tpattrib->rtsen = psta->rtsen;\n\tpattrib->cts2self = psta->cts2self;\n\n\tpattrib->mdata = 0;\n\tpattrib->eosp = 0;\n\tpattrib->triggered = 0;\n\tpattrib->ampdu_spacing = 0;\n\n\t/* ht_en, init rate, ,bw, ch_offset, sgi */\n\n\tpattrib->raid = psta->cmn.ra_info.rate_id;\n\n\tbw = rtw_get_tx_bw_mode(padapter, psta);\n\tpattrib->bwmode = rtw_min(bw, mlmeext->cur_bwmode);\n\tpattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode);\n\n\tpattrib->ldpc = psta->cmn.ldpc_en;\n\tpattrib->stbc = psta->cmn.stbc_en;\n\n#ifdef CONFIG_80211N_HT\n\tif(padapter->registrypriv.ht_enable &&\n\t\tis_supported_ht(padapter->registrypriv.wireless_mode)) {\n\t\tpattrib->ht_en = psta->htpriv.ht_option;\n\t\tpattrib->ch_offset = psta->htpriv.ch_offset;\n\t\tpattrib->ampdu_en = _FALSE;\n\n\t\tif (padapter->driver_ampdu_spacing != 0xFF) /* driver control AMPDU Density for peer sta's rx */\n\t\t\tpattrib->ampdu_spacing = padapter->driver_ampdu_spacing;\n\t\telse\n\t\t\tpattrib->ampdu_spacing = psta->htpriv.rx_ampdu_min_spacing;\n\n\t\t/* check if enable ampdu */\n\t\tif (pattrib->ht_en && psta->htpriv.ampdu_enable) {\n\t\t\tif (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) {\n\t\t\t\tpattrib->ampdu_en = _TRUE;\n\t\t\t\tif (psta->htpriv.tx_amsdu_enable == _TRUE)\n\t\t\t\t\tpattrib->amsdu_ampdu_en = _TRUE;\n\t\t\t\telse\n\t\t\t\t\tpattrib->amsdu_ampdu_en = _FALSE;\n\t\t\t}\n\t\t}\n\t}\n#endif /* CONFIG_80211N_HT */\n\t/* if(pattrib->ht_en && psta->htpriv.ampdu_enable) */\n\t/* { */\n\t/*\tif(psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) */\n\t/*\t\tpattrib->ampdu_en = _TRUE; */\n\t/* }\t */\n\n#ifdef CONFIG_TDLS\n\tif (pattrib->direct_link == _TRUE) {\n\t\tpsta = pattrib->ptdls_sta;\n\n\t\tpattrib->raid = psta->cmn.ra_info.rate_id;\n#ifdef CONFIG_80211N_HT\n\tif(padapter->registrypriv.ht_enable &&\n\t\tis_supported_ht(padapter->registrypriv.wireless_mode)) {\n\t\t\tpattrib->bwmode = rtw_get_tx_bw_mode(padapter, psta);\n\t\t\tpattrib->ht_en = psta->htpriv.ht_option;\n\t\t\tpattrib->ch_offset = psta->htpriv.ch_offset;\n\t\t\tpattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode);\n\t}\n#endif /* CONFIG_80211N_HT */\n\t}\n#endif /* CONFIG_TDLS */\n\n\tpattrib->retry_ctrl = _FALSE;\n}\n\nstatic s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta)\n{\n\tsint res = _SUCCESS;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tsint bmcast = IS_MCAST(pattrib->ra);\n\n\t_rtw_memset(pattrib->dot118021x_UncstKey.skey,  0, 16);\n\t_rtw_memset(pattrib->dot11tkiptxmickey.skey,  0, 16);\n\tpattrib->mac_id = psta->cmn.mac_id;\n\n\tif (psta->ieee8021x_blocked == _TRUE) {\n\n\t\tpattrib->encrypt = 0;\n\n\t\tif ((pattrib->ether_type != 0x888e) && (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)) {\n#ifdef DBG_TX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_TX_DROP_FRAME %s psta->ieee8021x_blocked == _TRUE,  pattrib->ether_type(%04x) != 0x888e\\n\", __FUNCTION__, pattrib->ether_type);\n#endif\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\t} else {\n\t\tGET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, bmcast);\n\n#ifdef CONFIG_WAPI_SUPPORT\n\t\tif (pattrib->ether_type == 0x88B4)\n\t\t\tpattrib->encrypt = _NO_PRIVACY_;\n#endif\n\n\t\tswitch (psecuritypriv->dot11AuthAlgrthm) {\n\t\tcase dot11AuthAlgrthm_Open:\n\t\tcase dot11AuthAlgrthm_Shared:\n\t\tcase dot11AuthAlgrthm_Auto:\n\t\t\tpattrib->key_idx = (u8)psecuritypriv->dot11PrivacyKeyIndex;\n\t\t\tbreak;\n\t\tcase dot11AuthAlgrthm_8021X:\n\t\t\tif (bmcast)\n\t\t\t\tpattrib->key_idx = (u8)psecuritypriv->dot118021XGrpKeyid;\n\t\t\telse\n\t\t\t\tpattrib->key_idx = 0;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tpattrib->key_idx = 0;\n\t\t\tbreak;\n\t\t}\n\n\t\t/* For WPS 1.0 WEP, driver should not encrypt EAPOL Packet for WPS handshake. */\n\t\tif (((pattrib->encrypt == _WEP40_) || (pattrib->encrypt == _WEP104_)) && (pattrib->ether_type == 0x888e))\n\t\t\tpattrib->encrypt = _NO_PRIVACY_;\n\n\t}\n\n#ifdef CONFIG_TDLS\n\tif (pattrib->direct_link == _TRUE) {\n\t\tif (pattrib->encrypt > 0)\n\t\t\tpattrib->encrypt = _AES_;\n\t}\n#endif\n\n\tswitch (pattrib->encrypt) {\n\tcase _WEP40_:\n\tcase _WEP104_:\n\t\tpattrib->iv_len = 4;\n\t\tpattrib->icv_len = 4;\n\t\tWEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);\n\t\tbreak;\n\n\tcase _TKIP_:\n\t\tpattrib->iv_len = 8;\n\t\tpattrib->icv_len = 4;\n\n\t\tif (psecuritypriv->busetkipkey == _FAIL) {\n#ifdef DBG_TX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_TX_DROP_FRAME %s psecuritypriv->busetkipkey(%d)==_FAIL drop packet\\n\", __FUNCTION__, psecuritypriv->busetkipkey);\n#endif\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (bmcast)\n\t\t\tTKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);\n\t\telse\n\t\t\tTKIP_IV(pattrib->iv, psta->dot11txpn, 0);\n\n\n\t\t_rtw_memcpy(pattrib->dot11tkiptxmickey.skey, psta->dot11tkiptxmickey.skey, 16);\n\n\t\tbreak;\n\n\tcase _AES_:\n\n\t\tpattrib->iv_len = 8;\n\t\tpattrib->icv_len = 8;\n\n\t\tif (bmcast)\n\t\t\tAES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);\n\t\telse\n\t\t\tAES_IV(pattrib->iv, psta->dot11txpn, 0);\n\n\t\tbreak;\n\n#ifdef CONFIG_WAPI_SUPPORT\n\tcase _SMS4_:\n\t\tpattrib->iv_len = 18;\n\t\tpattrib->icv_len = 16;\n\t\trtw_wapi_get_iv(padapter, pattrib->ra, pattrib->iv);\n\t\tbreak;\n#endif\n\tdefault:\n\t\tpattrib->iv_len = 0;\n\t\tpattrib->icv_len = 0;\n\t\tbreak;\n\t}\n\n\tif (pattrib->encrypt > 0)\n\t\t_rtw_memcpy(pattrib->dot118021x_UncstKey.skey, psta->dot118021x_UncstKey.skey, 16);\n\n\n\tif (pattrib->encrypt &&\n\t    ((padapter->securitypriv.sw_encrypt == _TRUE) || (psecuritypriv->hw_decrypted == _FALSE))) {\n\t\tpattrib->bswenc = _TRUE;\n\t} else {\n\t\tpattrib->bswenc = _FALSE;\n\t}\n\n#if defined(CONFIG_CONCURRENT_MODE)\n\tpattrib->bmc_camid = padapter->securitypriv.dot118021x_bmc_cam_id;\n#endif\n\n\tif (pattrib->encrypt && bmcast && _rtw_camctl_chk_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH))\n\t\tpattrib->bswenc = _TRUE;\n\n#ifdef CONFIG_WAPI_SUPPORT\n\tif (pattrib->encrypt == _SMS4_)\n\t\tpattrib->bswenc = _FALSE;\n#endif\n\nexit:\n\n\treturn res;\n\n}\n\nu8\tqos_acm(u8 acm_mask, u8 priority)\n{\n\tu8\tchange_priority = priority;\n\n\tswitch (priority) {\n\tcase 0:\n\tcase 3:\n\t\tif (acm_mask & BIT(1))\n\t\t\tchange_priority = 1;\n\t\tbreak;\n\tcase 1:\n\tcase 2:\n\t\tbreak;\n\tcase 4:\n\tcase 5:\n\t\tif (acm_mask & BIT(2))\n\t\t\tchange_priority = 0;\n\t\tbreak;\n\tcase 6:\n\tcase 7:\n\t\tif (acm_mask & BIT(3))\n\t\t\tchange_priority = 5;\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(\"qos_acm(): invalid pattrib->priority: %d!!!\\n\", priority);\n\t\tbreak;\n\t}\n\n\treturn change_priority;\n}\n\n#ifdef CONFIG_USER_PRIORITY_COMPLY_RFC4594_DSCP\n/* refer to IEEE802.11-2016 Table R-3; Comply with Table R-2 (IETF RFC4594) */\nstatic u8 dscp_to_up_ac(u8 tos)\n{\n\tu8 up = 0;\n\tu8 dscp;\n\n\tdscp = (tos >> 2);\n\n\tif ( dscp == 0 )\n\t\tup = 0;\n\telse if ( dscp >= 1 && dscp <= 9)\n\t\tup = 1;\n\telse if ( dscp >= 10 && dscp <= 16)\n\t\tup = 2;\n\telse if ( dscp >= 17 && dscp <= 23)\n\t\tup = 3;\n\telse if ( dscp >= 24 && dscp <= 31)\n\t\tup = 4;\n\telse if ( dscp >= 33 && dscp <= 40)\n\t\tup = 5;\n\telse if ((dscp >= 41 && dscp <= 47) || (dscp == 32))\n\t\tup = 6;\n\telse if ( dscp >= 48 && dscp <= 63)\n\t\tup = 7;\n\n\treturn up;\n}\n#endif\n\nstatic void set_qos(struct pkt_file *ppktfile, struct pkt_attrib *pattrib)\n{\n\tstruct ethhdr etherhdr;\n\tstruct iphdr ip_hdr;\n\ts32 UserPriority = 0;\n\n\n\t_rtw_open_pktfile(ppktfile->pkt, ppktfile);\n\t_rtw_pktfile_read(ppktfile, (unsigned char *)&etherhdr, ETH_HLEN);\n\n\t/* get UserPriority from IP hdr */\n\tif (pattrib->ether_type == 0x0800) {\n\t\t_rtw_pktfile_read(ppktfile, (u8 *)&ip_hdr, sizeof(ip_hdr));\n\t\t/*\t\tUserPriority = (ntohs(ip_hdr.tos) >> 5) & 0x3; */\n#ifdef CONFIG_USER_PRIORITY_COMPLY_RFC4594_DSCP\n\t\tUserPriority = dscp_to_up_ac(ip_hdr.tos);\n#else\n\t\tUserPriority = ip_hdr.tos >> 5;\n#endif\n\t}\n\t/*\n\t\telse if (pattrib->ether_type == 0x888e) {\n\n\n\t\t\tUserPriority = 7;\n\t\t}\n\t*/\n\n\t#ifdef CONFIG_ICMP_VOQ\n\tif(pattrib->icmp_pkt==1)/*use VO queue to send icmp packet*/\n\t\tUserPriority = 7;\n\t#endif\n\t#ifdef CONFIG_IP_R_MONITOR\n\tif (pattrib->ether_type == ETH_P_ARP)\n\t\tUserPriority = 7;\n\t#endif/*CONFIG_IP_R_MONITOR*/\n\tpattrib->priority = UserPriority;\n\tpattrib->hdrlen = WLAN_HDR_A3_QOS_LEN;\n\tpattrib->subtype = WIFI_QOS_DATA_TYPE;\n}\n\n#ifdef CONFIG_TDLS\nu8 rtw_check_tdls_established(_adapter *padapter, struct pkt_attrib *pattrib)\n{\n\tpattrib->ptdls_sta = NULL;\n\n\tpattrib->direct_link = _FALSE;\n\tif (padapter->tdlsinfo.link_established == _TRUE) {\n\t\tpattrib->ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst);\n#if 1\n\t\tif ((pattrib->ptdls_sta != NULL) &&\n\t\t    (pattrib->ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) &&\n\t\t    (pattrib->ether_type != 0x0806)) {\n\t\t\tpattrib->direct_link = _TRUE;\n\t\t\t/* RTW_INFO(\"send ptk to \"MAC_FMT\" using direct link\\n\", MAC_ARG(pattrib->dst)); */\n\t\t}\n#else\n\t\tif (pattrib->ptdls_sta != NULL &&\n\t\t    pattrib->ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {\n\t\t\tpattrib->direct_link = _TRUE;\n#if 0\n\t\t\tRTW_INFO(\"send ptk to \"MAC_FMT\" using direct link\\n\", MAC_ARG(pattrib->dst));\n#endif\n\t\t}\n\n\t\t/* ARP frame may be helped by AP*/\n\t\tif (pattrib->ether_type != 0x0806)\n\t\t\tpattrib->direct_link = _FALSE;\n#endif\n\t}\n\n\treturn pattrib->direct_link;\n}\n\ns32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib)\n{\n\n\tstruct sta_info *psta = NULL;\n\tstruct sta_priv\t\t*pstapriv = &padapter->stapriv;\n\tstruct security_priv\t*psecuritypriv = &padapter->securitypriv;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct qos_priv\t\t*pqospriv = &pmlmepriv->qospriv;\n\n\ts32 res = _SUCCESS;\n\n\tpsta = rtw_get_stainfo(pstapriv, pattrib->ra);\n\tif (psta == NULL)\t{\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpattrib->mac_id = psta->cmn.mac_id;\n\tpattrib->psta = psta;\n\tpattrib->ack_policy = 0;\n\t/* get ether_hdr_len */\n\tpattrib->pkt_hdrlen = ETH_HLEN;\n\n\tpattrib->qos_en = psta->qos_option;\n\n\t/* [TDLS] TODO: setup req/rsp should be AC_BK */\n\tif (pqospriv->qos_option &&  psta->qos_option) {\n\t\tpattrib->priority = 4;\t/* tdls management frame should be AC_VI */\n\t\tpattrib->hdrlen = WLAN_HDR_A3_QOS_LEN;\n\t\tpattrib->subtype = WIFI_QOS_DATA_TYPE;\n\t} else {\n\t\tpattrib->priority = 0;\n\t\tpattrib->hdrlen = WLAN_HDR_A3_LEN;\n\t\tpattrib->subtype = WIFI_DATA_TYPE;\n\t}\n\n\t/* TODO:_lock */\n\tif (update_attrib_sec_info(padapter, pattrib, psta) == _FAIL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tupdate_attrib_phy_info(padapter, pattrib, psta);\n\n\nexit:\n\n\treturn res;\n}\n\n#endif /* CONFIG_TDLS */\n\n/*get non-qos hw_ssn control register,mapping to REG_HW_SEQ 0,1,2,3*/\ninline u8 rtw_get_hwseq_no(_adapter *padapter)\n{\n\tu8 hwseq_num = 0;\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)\n\thwseq_num = padapter->iface_id;\n\tif (hwseq_num > 3)\n\t\thwseq_num = 3;\n\t#else\n\tif (!is_primary_adapter(padapter))\n\t\thwseq_num = 1;\n\t#endif\n#endif /* CONFIG_CONCURRENT_MODE */\n\treturn hwseq_num;\n}\n#ifdef CONFIG_LPS\n#define LPS_PT_NORMAL\t0\n#define LPS_PT_SP\t\t1/* only DHCP packets is as SPECIAL_PACKET*/\n#define LPS_PT_ICMP\t\t2\n\n/*If EAPOL , ARP , OR DHCP packet, driver must be in active mode.*/\nstatic u8 _rtw_lps_chk_packet_type(struct pkt_attrib *pattrib)\n{\n\tu8 pkt_type = LPS_PT_NORMAL; /*normal data frame*/\n\n\t#ifdef CONFIG_WAPI_SUPPORT\n\tif ((pattrib->ether_type == 0x88B4) || (pattrib->ether_type == 0x0806) || (pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1))\n\t\tpkt_type = LPS_PT_SP;\n\t#else /* !CONFIG_WAPI_SUPPORT */\n\n\t#ifndef CONFIG_LPS_NOT_LEAVE_FOR_ICMP\n\tif (pattrib->icmp_pkt == 1)\n\t\tpkt_type = LPS_PT_ICMP;\n\telse\n\t#endif\n\t\tif (pattrib->dhcp_pkt == 1)\n\t\t\tpkt_type = LPS_PT_SP;\n\t#endif\n\treturn pkt_type;\n}\n#endif\nstatic s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattrib)\n{\n\tuint i;\n\tstruct pkt_file pktfile;\n\tstruct sta_info *psta = NULL;\n\tstruct ethhdr etherhdr;\n\n\tsint bmcast;\n\tstruct sta_priv\t\t*pstapriv = &padapter->stapriv;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct qos_priv\t\t*pqospriv = &pmlmepriv->qospriv;\n\tstruct xmit_priv\t\t*pxmitpriv = &padapter->xmitpriv;\n\tsint res = _SUCCESS;\n#ifdef CONFIG_LPS\n\tu8 pkt_type = 0;\n#endif\n\n\tDBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib);\n\n\t_rtw_open_pktfile(pkt, &pktfile);\n\ti = _rtw_pktfile_read(&pktfile, (u8 *)&etherhdr, ETH_HLEN);\n\n\tpattrib->ether_type = ntohs(etherhdr.h_proto);\n\n\tif (MLME_IS_MESH(padapter)) /* address resolve is done for mesh */\n\t\tgoto get_sta_info;\n\n\t_rtw_memcpy(pattrib->dst, &etherhdr.h_dest, ETH_ALEN);\n\t_rtw_memcpy(pattrib->src, &etherhdr.h_source, ETH_ALEN);\n\n\tif ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ||\n\t    (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {\n\t\t_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->ta, adapter_mac_addr(padapter), ETH_ALEN);\n\t\tDBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_adhoc);\n\t} else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {\n#ifdef CONFIG_TDLS\n\t\tif (rtw_check_tdls_established(padapter, pattrib) == _TRUE)\n\t\t\t_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);\t/* For TDLS direct link Tx, set ra to be same to dst */\n\t\telse\n#endif\n\t\t\t_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->ta, adapter_mac_addr(padapter), ETH_ALEN);\n\t\tDBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_sta);\n\t} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {\n\t\t_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);\n\t\t_rtw_memcpy(pattrib->ta, get_bssid(pmlmepriv), ETH_ALEN);\n\t\tDBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_ap);\n\t} else\n\t\tDBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_unknown);\n\nget_sta_info:\n\tbmcast = IS_MCAST(pattrib->ra);\n\tif (bmcast) {\n\t\tpsta = rtw_get_bcmc_stainfo(padapter);\n\t\tif (psta == NULL) { /* if we cannot get psta => drop the pkt */\n\t\t\tDBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sta);\n\t\t\t#ifdef DBG_TX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_TX_DROP_FRAME %s get sta_info fail, ra:\" MAC_FMT\"\\n\", __func__, MAC_ARG(pattrib->ra));\n\t\t\t#endif\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\t} else {\n\t\tpsta = rtw_get_stainfo(pstapriv, pattrib->ra);\n\t\tif (psta == NULL) { /* if we cannot get psta => drop the pkt */\n\t\t\tDBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_sta);\n\t\t\t#ifdef DBG_TX_DROP_FRAME\n\t\t\tRTW_INFO(\"DBG_TX_DROP_FRAME %s get sta_info fail, ra:\" MAC_FMT\"\\n\", __func__, MAC_ARG(pattrib->ra));\n\t\t\t#endif\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && !(psta->state & _FW_LINKED)) {\n\t\t\tDBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_ap_link);\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\tif (!(psta->state & _FW_LINKED)) {\n\t\tDBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_link);\n\t\tRTW_INFO(\"%s-\"ADPT_FMT\" psta(\"MAC_FMT\")->state(0x%x) != _FW_LINKED\\n\",\n\t\t\t__func__, ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr), psta->state);\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpattrib->pktlen = pktfile.pkt_len;\n\n\t/* TODO: 802.1Q VLAN header */\n\t/* TODO: IPV6 */\n\n\tif (ETH_P_IP == pattrib->ether_type) {\n\t\tu8 ip[20];\n\n\t\t_rtw_pktfile_read(&pktfile, ip, 20);\n\n\t\tif (GET_IPV4_IHL(ip) * 4 > 20)\n\t\t\t_rtw_pktfile_read(&pktfile, NULL, GET_IPV4_IHL(ip) - 20);\n\n\t\tpattrib->icmp_pkt = 0;\n\t\tpattrib->dhcp_pkt = 0;\n\n\t\tif (GET_IPV4_PROTOCOL(ip) == 0x01) { /* ICMP */\n\t\t\tpattrib->icmp_pkt = 1;\n\t\t\tDBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_icmp);\n\n\t\t} else if (GET_IPV4_PROTOCOL(ip) == 0x11) { /* UDP */\n\t\t\tu8 udp[8];\n\n\t\t\t_rtw_pktfile_read(&pktfile, udp, 8);\n\n\t\t\tif ((GET_UDP_SRC(udp) == 68 && GET_UDP_DST(udp) == 67)\n\t\t\t\t|| (GET_UDP_SRC(udp) == 67 && GET_UDP_DST(udp) == 68)\n\t\t\t) {\n\t\t\t\t/* 67 : UDP BOOTP server, 68 : UDP BOOTP client */\n\t\t\t\tif (pattrib->pktlen > 282) { /* MINIMUM_DHCP_PACKET_SIZE */\n\t\t\t\t\tpattrib->dhcp_pkt = 1;\n\t\t\t\t\tDBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_dhcp);\n\t\t\t\t\tif (0)\n\t\t\t\t\t\tRTW_INFO(\"send DHCP packet\\n\");\n\t\t\t\t}\n\t\t\t}\n\n\t\t} else if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */\n\t\t\t&& rtw_st_ctl_chk_reg_s_proto(&psta->st_ctl, 0x06) == _TRUE\n\t\t) {\n\t\t\tu8 tcp[20];\n\n\t\t\t_rtw_pktfile_read(&pktfile, tcp, 20);\n\n\t\t\tif (rtw_st_ctl_chk_reg_rule(&psta->st_ctl, padapter, IPV4_SRC(ip), TCP_SRC(tcp), IPV4_DST(ip), TCP_DST(tcp)) == _TRUE) {\n\t\t\t\tif (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) {\n\t\t\t\t\tsession_tracker_add_cmd(padapter, psta\n\t\t\t\t\t\t, IPV4_SRC(ip), TCP_SRC(tcp)\n\t\t\t\t\t\t, IPV4_SRC(ip), TCP_DST(tcp));\n\t\t\t\t\tif (DBG_SESSION_TRACKER)\n\t\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" local:\"IP_FMT\":\"PORT_FMT\", remote:\"IP_FMT\":\"PORT_FMT\" SYN-ACK\\n\"\n\t\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter)\n\t\t\t\t\t\t\t, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))\n\t\t\t\t\t\t\t, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)));\n\t\t\t\t}\n\t\t\t\tif (GET_TCP_FIN(tcp)) {\n\t\t\t\t\tsession_tracker_del_cmd(padapter, psta\n\t\t\t\t\t\t, IPV4_SRC(ip), TCP_SRC(tcp)\n\t\t\t\t\t\t, IPV4_SRC(ip), TCP_DST(tcp));\n\t\t\t\t\tif (DBG_SESSION_TRACKER)\n\t\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" local:\"IP_FMT\":\"PORT_FMT\", remote:\"IP_FMT\":\"PORT_FMT\" FIN\\n\"\n\t\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter)\n\t\t\t\t\t\t\t, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))\n\t\t\t\t\t\t\t, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)));\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t} else if (0x888e == pattrib->ether_type)\n\t\tparsing_eapol_packet(padapter, pktfile.cur_addr, psta, 1);\n#if defined (DBG_ARP_DUMP) || defined (DBG_IP_R_MONITOR)\n\telse if (pattrib->ether_type == ETH_P_ARP) {\n\t\tu8 arp[28] = {0};\n\n\t\t_rtw_pktfile_read(&pktfile, arp, 28);\n\t\tdump_arp_pkt(RTW_DBGDUMP, etherhdr.h_dest, etherhdr.h_source, arp, 1);\n\t}\n#endif\n\n\tif ((pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1))\n\t\trtw_mi_set_scan_deny(padapter, 3000);\n\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) &&\n\t\tpattrib->ether_type == ETH_P_ARP &&\n\t\t!IS_MCAST(pattrib->dst)) {\n\t\trtw_mi_set_scan_deny(padapter, 1000);\n\t\trtw_mi_scan_abort(padapter, _FALSE); /*rtw_scan_abort_no_wait*/\n\t}\n\n#ifdef CONFIG_LPS\n\tpkt_type = _rtw_lps_chk_packet_type(pattrib);\n\n\tif (pkt_type == LPS_PT_SP) {/*packet is as SPECIAL_PACKET*/\n\t\tDBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_active);\n\t\trtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SPECIAL_PACKET, 0);\n\t} else if (pkt_type == LPS_PT_ICMP)\n\t\trtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0);\n#endif /* CONFIG_LPS */\n\n#ifdef CONFIG_BEAMFORMING\n\tupdate_attrib_txbf_info(padapter, pattrib, psta);\n#endif\n\n\t/* TODO:_lock */\n\tif (update_attrib_sec_info(padapter, pattrib, psta) == _FAIL) {\n\t\tDBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sec);\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t/* get ether_hdr_len */\n\tpattrib->pkt_hdrlen = ETH_HLEN;/* (pattrib->ether_type == 0x8100) ? (14 + 4 ): 14; */ /* vlan tag */\n\n\tpattrib->hdrlen = WLAN_HDR_A3_LEN;\n\tpattrib->subtype = WIFI_DATA_TYPE;\n\tpattrib->qos_en = psta->qos_option;\n\tpattrib->priority = 0;\n\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE\n\t\t| WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)\n\t) {\n\t\tif (pattrib->qos_en) {\n\t\t\tset_qos(&pktfile, pattrib);\n\t\t\t#ifdef CONFIG_RTW_MESH\n\t\t\tif (MLME_IS_MESH(padapter))\n\t\t\t\trtw_mesh_tx_set_whdr_mctrl_len(pattrib->mesh_frame_mode, pattrib);\n\t\t\t#endif\n\t\t}\n\t} else {\n#ifdef CONFIG_TDLS\n\t\tif (pattrib->direct_link == _TRUE) {\n\t\t\tif (pattrib->qos_en)\n\t\t\t\tset_qos(&pktfile, pattrib);\n\t\t} else\n#endif\n\t\t{\n\t\t\tif (pqospriv->qos_option) {\n\t\t\t\tset_qos(&pktfile, pattrib);\n\n\t\t\t\tif (pmlmepriv->acm_mask != 0)\n\t\t\t\t\tpattrib->priority = qos_acm(pmlmepriv->acm_mask, pattrib->priority);\n\t\t\t}\n\t\t}\n\t}\n\t\n\tupdate_attrib_phy_info(padapter, pattrib, psta);\n\n\t/* RTW_INFO(\"%s ==> mac_id(%d)\\n\",__FUNCTION__,pattrib->mac_id ); */\n\n\tpattrib->psta = psta;\n\t/* TODO:_unlock */\n\n#ifdef CONFIG_AUTO_AP_MODE\n\tif (psta->isrc && psta->pid > 0)\n\t\tpattrib->pctrl = _TRUE;\n\telse\n#endif\n\t\tpattrib->pctrl = 0;\n\n\tpattrib->ack_policy = 0;\n\n\tif (bmcast)\n\t\tpattrib->rate = psta->init_rate;\n\n\n#ifdef CONFIG_WMMPS_STA\n\tupdate_attrib_trigger_frame_info(padapter, pattrib);\n#endif /* CONFIG_WMMPS_STA */\t\n\n\t/* pattrib->priority = 5; */ /* force to used VI queue, for testing */\n\tpattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no;\n\trtw_set_tx_chksum_offload(pkt, pattrib);\n\nexit:\n\n\n\treturn res;\n}\n\nstatic s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe)\n{\n\tsint\t\t\tcurfragnum, length;\n\tu8\t*pframe, *payload, mic[8];\n\tstruct\tmic_data\t\tmicdata;\n\t/* struct\tsta_info\t\t*stainfo; */\n\tstruct\tpkt_attrib\t*pattrib = &pxmitframe->attrib;\n\tstruct\tsecurity_priv\t*psecuritypriv = &padapter->securitypriv;\n\tstruct\txmit_priv\t\t*pxmitpriv = &padapter->xmitpriv;\n\tu8 priority[4] = {0x0, 0x0, 0x0, 0x0};\n\tu8 hw_hdr_offset = 0;\n\tsint bmcst = IS_MCAST(pattrib->ra);\n\n\t/*\n\t\tif(pattrib->psta)\n\t\t{\n\t\t\tstainfo = pattrib->psta;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tRTW_INFO(\"%s, call rtw_get_stainfo()\\n\", __func__);\n\t\t\tstainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]);\n\t\t}\n\n\t\tif(stainfo==NULL)\n\t\t{\n\t\t\tRTW_INFO(\"%s, psta==NUL\\n\", __func__);\n\t\t\treturn _FAIL;\n\t\t}\n\n\t\tif(!(stainfo->state &_FW_LINKED))\n\t\t{\n\t\t\tRTW_INFO(\"%s, psta->state(0x%x) != _FW_LINKED\\n\", __func__, stainfo->state);\n\t\t\treturn _FAIL;\n\t\t}\n\t*/\n\n\n#ifdef CONFIG_USB_TX_AGGREGATION\n\thw_hdr_offset = TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);;\n#else\n#ifdef CONFIG_TX_EARLY_MODE\n\thw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;\n#else\n\thw_hdr_offset = TXDESC_OFFSET;\n#endif\n#endif\n\n\tif (pattrib->encrypt == _TKIP_) { /* if(psecuritypriv->dot11PrivacyAlgrthm==_TKIP_PRIVACY_) */\n\t\t/* encode mic code */\n\t\t/* if(stainfo!= NULL) */\n\t\t{\n\t\t\tu8 null_key[16] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};\n\n\t\t\tpframe = pxmitframe->buf_addr + hw_hdr_offset;\n\n\t\t\tif (bmcst) {\n\t\t\t\tif (_rtw_memcmp(psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey, null_key, 16) == _TRUE) {\n\t\t\t\t\t/* DbgPrint(\"\\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\\n\"); */\n\t\t\t\t\t/* rtw_msleep_os(10); */\n\t\t\t\t\treturn _FAIL;\n\t\t\t\t}\n\t\t\t\t/* start to calculate the mic code */\n\t\t\t\trtw_secmicsetkey(&micdata, psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey);\n\t\t\t} else {\n\t\t\t\tif (_rtw_memcmp(&pattrib->dot11tkiptxmickey.skey[0], null_key, 16) == _TRUE) {\n\t\t\t\t\t/* DbgPrint(\"\\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\\n\"); */\n\t\t\t\t\t/* rtw_msleep_os(10); */\n\t\t\t\t\treturn _FAIL;\n\t\t\t\t}\n\t\t\t\t/* start to calculate the mic code */\n\t\t\t\trtw_secmicsetkey(&micdata, &pattrib->dot11tkiptxmickey.skey[0]);\n\t\t\t}\n\n\t\t\tif (pframe[1] & 1) { /* ToDS==1 */\n\t\t\t\trtw_secmicappend(&micdata, &pframe[16], 6);  /* DA */\n\t\t\t\tif (pframe[1] & 2) /* From Ds==1 */\n\t\t\t\t\trtw_secmicappend(&micdata, &pframe[24], 6);\n\t\t\t\telse\n\t\t\t\t\trtw_secmicappend(&micdata, &pframe[10], 6);\n\t\t\t} else {\t/* ToDS==0 */\n\t\t\t\trtw_secmicappend(&micdata, &pframe[4], 6);   /* DA */\n\t\t\t\tif (pframe[1] & 2) /* From Ds==1 */\n\t\t\t\t\trtw_secmicappend(&micdata, &pframe[16], 6);\n\t\t\t\telse\n\t\t\t\t\trtw_secmicappend(&micdata, &pframe[10], 6);\n\n\t\t\t}\n\n\t\t\tif (pattrib->qos_en)\n\t\t\t\tpriority[0] = (u8)pxmitframe->attrib.priority;\n\n\n\t\t\trtw_secmicappend(&micdata, &priority[0], 4);\n\n\t\t\tpayload = pframe;\n\n\t\t\tfor (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {\n\t\t\t\tpayload = (u8 *)RND4((SIZE_PTR)(payload));\n\n\t\t\t\tpayload = payload + pattrib->hdrlen + pattrib->iv_len;\n\t\t\t\tif ((curfragnum + 1) == pattrib->nr_frags) {\n\t\t\t\t\tlength = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0);\n\t\t\t\t\trtw_secmicappend(&micdata, payload, length);\n\t\t\t\t\tpayload = payload + length;\n\t\t\t\t} else {\n\t\t\t\t\tlength = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0);\n\t\t\t\t\trtw_secmicappend(&micdata, payload, length);\n\t\t\t\t\tpayload = payload + length + pattrib->icv_len;\n\t\t\t\t}\n\t\t\t}\n\t\t\trtw_secgetmic(&micdata, &(mic[0]));\n\t\t\t/* add mic code  and add the mic code length in last_txcmdsz */\n\n\t\t\t_rtw_memcpy(payload, &(mic[0]), 8);\n\t\t\tpattrib->last_txcmdsz += 8;\n\n\t\t\tpayload = payload - pattrib->last_txcmdsz + 8;\n\t\t}\n\t}\n\n\n\treturn _SUCCESS;\n}\n\n/*#define DBG_TX_SW_ENCRYPTOR*/\n\nstatic s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe)\n{\n\n\tstruct\tpkt_attrib\t*pattrib = &pxmitframe->attrib;\n\t/* struct \tsecurity_priv\t*psecuritypriv=&padapter->securitypriv; */\n\n\n\t/* if((psecuritypriv->sw_encrypt)||(pattrib->bswenc))\t */\n\tif (pattrib->bswenc) {\n#ifdef DBG_TX_SW_ENCRYPTOR\n\t\tRTW_INFO(ADPT_FMT\" - sec_type:%s DO SW encryption\\n\",\n\t\t\tADPT_ARG(padapter), security_type_str(pattrib->encrypt));\n#endif\n\n\t\tswitch (pattrib->encrypt) {\n\t\tcase _WEP40_:\n\t\tcase _WEP104_:\n\t\t\trtw_wep_encrypt(padapter, (u8 *)pxmitframe);\n\t\t\tbreak;\n\t\tcase _TKIP_:\n\t\t\trtw_tkip_encrypt(padapter, (u8 *)pxmitframe);\n\t\t\tbreak;\n\t\tcase _AES_:\n\t\t\trtw_aes_encrypt(padapter, (u8 *)pxmitframe);\n\t\t\tbreak;\n#ifdef CONFIG_WAPI_SUPPORT\n\t\tcase _SMS4_:\n\t\t\trtw_sms4_encrypt(padapter, (u8 *)pxmitframe);\n#endif\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t}\n\n\n\treturn _SUCCESS;\n}\n\ns32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib)\n{\n\tu16 *qc;\n\n\tstruct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct qos_priv *pqospriv = &pmlmepriv->qospriv;\n\tu8 qos_option = _FALSE;\n\tsint res = _SUCCESS;\n\tu16 *fctrl = &pwlanhdr->frame_ctl;\n\n\t/* struct sta_info *psta; */\n\n\t/* sint bmcst = IS_MCAST(pattrib->ra); */\n\n\n\t/*\n\t\tpsta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);\n\t\tif(pattrib->psta != psta)\n\t\t{\n\t\t\tRTW_INFO(\"%s, pattrib->psta(%p) != psta(%p)\\n\", __func__, pattrib->psta, psta);\n\t\t\treturn;\n\t\t}\n\n\t\tif(psta==NULL)\n\t\t{\n\t\t\tRTW_INFO(\"%s, psta==NUL\\n\", __func__);\n\t\t\treturn _FAIL;\n\t\t}\n\n\t\tif(!(psta->state &_FW_LINKED))\n\t\t{\n\t\t\tRTW_INFO(\"%s, psta->state(0x%x) != _FW_LINKED\\n\", __func__, psta->state);\n\t\t\treturn _FAIL;\n\t\t}\n\t*/\n\n\t_rtw_memset(hdr, 0, WLANHDR_OFFSET);\n\n\tset_frame_sub_type(fctrl, pattrib->subtype);\n\n\tif (pattrib->subtype & WIFI_DATA_TYPE) {\n\t\tif ((check_fwstate(pmlmepriv,  WIFI_STATION_STATE) == _TRUE)) {\n#ifdef CONFIG_TDLS\n\t\t\tif (pattrib->direct_link == _TRUE) {\n\t\t\t\t/* TDLS data transfer, ToDS=0, FrDs=0 */\n\t\t\t\t_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);\n\t\t\t\t_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);\n\t\t\t\t_rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);\n\n\t\t\t\tif (pattrib->qos_en)\n\t\t\t\t\tqos_option = _TRUE;\n\t\t\t} else\n#endif /* CONFIG_TDLS */\n\t\t\t{\n\t\t\t\t/* to_ds = 1, fr_ds = 0; */\n\t\t\t\t/* 1.Data transfer to AP */\n\t\t\t\t/* 2.Arp pkt will relayed by AP */\n\t\t\t\tSetToDs(fctrl);\n\t\t\t\t_rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN);\n\t\t\t\t_rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN);\n\t\t\t\t_rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);\n\n\t\t\t\tif (pqospriv->qos_option)\n\t\t\t\t\tqos_option = _TRUE;\n\t\t\t}\n\t\t} else if ((check_fwstate(pmlmepriv,  WIFI_AP_STATE) == _TRUE)) {\n\t\t\t/* to_ds = 0, fr_ds = 1; */\n\t\t\tSetFrDs(fctrl);\n\t\t\t_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);\n\t\t\t_rtw_memcpy(pwlanhdr->addr2, get_bssid(pmlmepriv), ETH_ALEN);\n\t\t\t_rtw_memcpy(pwlanhdr->addr3, pattrib->src, ETH_ALEN);\n\n\t\t\tif (pattrib->qos_en)\n\t\t\t\tqos_option = _TRUE;\n\t\t} else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ||\n\t\t\t(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {\n\t\t\t_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);\n\t\t\t_rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN);\n\t\t\t_rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);\n\n\t\t\tif (pattrib->qos_en)\n\t\t\t\tqos_option = _TRUE;\n#ifdef CONFIG_RTW_MESH\n\t\t} else if (check_fwstate(pmlmepriv, WIFI_MESH_STATE) == _TRUE) {\n\t\t\trtw_mesh_tx_build_whdr(padapter, pattrib, fctrl, pwlanhdr);\n\t\t\tif (pattrib->qos_en)\n\t\t\t\tqos_option = _TRUE;\n\t\t\telse {\n\t\t\t\tRTW_WARN(\"[%s] !qos_en in Mesh\\n\", __FUNCTION__);\n\t\t\t\tres = _FAIL;\n\t\t\t\tgoto exit;\n\t\t\t}\n#endif\n\t\t} else {\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (pattrib->mdata)\n\t\t\tSetMData(fctrl);\n\n\t\tif (pattrib->encrypt)\n\t\t\tSetPrivacy(fctrl);\n\n\t\tif (qos_option) {\n\t\t\tqc = (unsigned short *)(hdr + pattrib->hdrlen - 2);\n\n\t\t\tif (pattrib->priority)\n\t\t\t\tSetPriority(qc, pattrib->priority);\n\n\t\t\tSetEOSP(qc, pattrib->eosp);\n\n\t\t\tSetAckpolicy(qc, pattrib->ack_policy);\n\n\t\t\tif(pattrib->amsdu)\n\t\t\t\tSetAMsdu(qc, pattrib->amsdu);\n#ifdef CONFIG_RTW_MESH\n\t\t\tif (MLME_IS_MESH(padapter)) {\n\t\t\t\t/* active: don't care, light sleep: 0, deep sleep: 1*/\n\t\t\t\tset_mps_lv(qc, 0); //TBD\n\n\t\t\t\t/* TBD: temporary set (rspi, eosp) = (0, 1) which means End MPSP */\n\t\t\t\tset_rspi(qc, 0);\n\t\t\t\tSetEOSP(qc, 1);\n\t\t\t\t\n\t\t\t\tset_mctrl_present(qc, 1);\n\t\t\t}\n#endif\n\t\t}\n\n\t\t/* TODO: fill HT Control Field */\n\n\t\t/* Update Seq Num will be handled by f/w */\n\t\t{\n\t\t\tstruct sta_info *psta;\n\t\t\tpsta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);\n\t\t\tif (pattrib->psta != psta) {\n\t\t\t\tRTW_INFO(\"%s, pattrib->psta(%p) != psta(%p)\\n\", __func__, pattrib->psta, psta);\n\t\t\t\treturn _FAIL;\n\t\t\t}\n\n\t\t\tif (psta == NULL) {\n\t\t\t\tRTW_INFO(\"%s, psta==NUL\\n\", __func__);\n\t\t\t\treturn _FAIL;\n\t\t\t}\n\n\t\t\tif (!(psta->state & _FW_LINKED)) {\n\t\t\t\tRTW_INFO(\"%s, psta->state(0x%x) != _FW_LINKED\\n\", __func__, psta->state);\n\t\t\t\treturn _FAIL;\n\t\t\t}\n\n\n\t\t\tif (psta) {\n\t\t\t\tpsta->sta_xmitpriv.txseq_tid[pattrib->priority]++;\n\t\t\t\tpsta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF;\n\t\t\t\tpattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority];\n\n\t\t\t\tSetSeqNum(hdr, pattrib->seqnum);\n\n#ifdef CONFIG_80211N_HT\n#if 0 /* move into update_attrib_phy_info(). */\n\t\t\t\t/* check if enable ampdu */\n\t\t\t\tif (pattrib->ht_en && psta->htpriv.ampdu_enable) {\n\t\t\t\t\tif (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority))\n\t\t\t\t\t\tpattrib->ampdu_en = _TRUE;\n\t\t\t\t}\n#endif\n\t\t\t\t/* re-check if enable ampdu by BA_starting_seqctrl */\n\t\t\t\tif (pattrib->ampdu_en == _TRUE) {\n\t\t\t\t\tu16 tx_seq;\n\n\t\t\t\t\ttx_seq = psta->BA_starting_seqctrl[pattrib->priority & 0x0f];\n\n\t\t\t\t\t/* check BA_starting_seqctrl */\n\t\t\t\t\tif (SN_LESS(pattrib->seqnum, tx_seq)) {\n\t\t\t\t\t\t/* RTW_INFO(\"tx ampdu seqnum(%d) < tx_seq(%d)\\n\", pattrib->seqnum, tx_seq); */\n\t\t\t\t\t\tpattrib->ampdu_en = _FALSE;/* AGG BK */\n\t\t\t\t\t} else if (SN_EQUAL(pattrib->seqnum, tx_seq)) {\n\t\t\t\t\t\tpsta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (tx_seq + 1) & 0xfff;\n\n\t\t\t\t\t\tpattrib->ampdu_en = _TRUE;/* AGG EN */\n\t\t\t\t\t} else {\n\t\t\t\t\t\t/* RTW_INFO(\"tx ampdu over run\\n\"); */\n\t\t\t\t\t\tpsta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (pattrib->seqnum + 1) & 0xfff;\n\t\t\t\t\t\tpattrib->ampdu_en = _TRUE;/* AGG EN */\n\t\t\t\t\t}\n\n\t\t\t\t}\n#endif /* CONFIG_80211N_HT */\n\t\t\t}\n\t\t}\n\n\t} else {\n\n\t}\n\nexit:\n\n\n\treturn res;\n}\n\ns32 rtw_txframes_pending(_adapter *padapter)\n{\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\n\treturn ((_rtw_queue_empty(&pxmitpriv->be_pending) == _FALSE) ||\n\t\t(_rtw_queue_empty(&pxmitpriv->bk_pending) == _FALSE) ||\n\t\t(_rtw_queue_empty(&pxmitpriv->vi_pending) == _FALSE) ||\n\t\t(_rtw_queue_empty(&pxmitpriv->vo_pending) == _FALSE));\n}\n\ns32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib)\n{\n\tstruct sta_info *psta;\n\tstruct tx_servq *ptxservq;\n\tint priority = pattrib->priority;\n\t/*\n\t\tif(pattrib->psta)\n\t\t{\n\t\t\tpsta = pattrib->psta;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tRTW_INFO(\"%s, call rtw_get_stainfo()\\n\", __func__);\n\t\t\tpsta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]);\n\t\t}\n\t*/\n\tpsta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);\n\tif (pattrib->psta != psta) {\n\t\tRTW_INFO(\"%s, pattrib->psta(%p) != psta(%p)\\n\", __func__, pattrib->psta, psta);\n\t\treturn 0;\n\t}\n\n\tif (psta == NULL) {\n\t\tRTW_INFO(\"%s, psta==NUL\\n\", __func__);\n\t\treturn 0;\n\t}\n\n\tif (!(psta->state & _FW_LINKED)) {\n\t\tRTW_INFO(\"%s, psta->state(0x%x) != _FW_LINKED\\n\", __func__, psta->state);\n\t\treturn 0;\n\t}\n\n\tswitch (priority) {\n\tcase 1:\n\tcase 2:\n\t\tptxservq = &(psta->sta_xmitpriv.bk_q);\n\t\tbreak;\n\tcase 4:\n\tcase 5:\n\t\tptxservq = &(psta->sta_xmitpriv.vi_q);\n\t\tbreak;\n\tcase 6:\n\tcase 7:\n\t\tptxservq = &(psta->sta_xmitpriv.vo_q);\n\t\tbreak;\n\tcase 0:\n\tcase 3:\n\tdefault:\n\t\tptxservq = &(psta->sta_xmitpriv.be_q);\n\t\tbreak;\n\n\t}\n\n\treturn ptxservq->qcnt;\n}\n\n#ifdef CONFIG_TDLS\n\nint rtw_build_tdls_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt)\n{\n\tstruct pkt_attrib *pattrib = &pxmitframe->attrib;\n\tstruct sta_info *ptdls_sta = NULL;\n\tint res = _SUCCESS;\n\n\tptdls_sta = rtw_get_stainfo((&padapter->stapriv), pattrib->dst);\n\tif (ptdls_sta == NULL) {\n\t\tswitch (ptxmgmt->action_code) {\n\t\tcase TDLS_DISCOVERY_REQUEST:\n\t\tcase TUNNELED_PROBE_REQ:\n\t\tcase TUNNELED_PROBE_RSP:\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tRTW_INFO(\"[TDLS] %s - Direct Link Peer = \"MAC_FMT\" not found for action = %d\\n\", __func__, MAC_ARG(pattrib->dst), ptxmgmt->action_code);\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\tswitch (ptxmgmt->action_code) {\n\tcase TDLS_SETUP_REQUEST:\n\t\trtw_build_tdls_setup_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);\n\t\tbreak;\n\tcase TDLS_SETUP_RESPONSE:\n\t\trtw_build_tdls_setup_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);\n\t\tbreak;\n\tcase TDLS_SETUP_CONFIRM:\n\t\trtw_build_tdls_setup_cfm_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);\n\t\tbreak;\n\tcase TDLS_TEARDOWN:\n\t\trtw_build_tdls_teardown_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);\n\t\tbreak;\n\tcase TDLS_DISCOVERY_REQUEST:\n\t\trtw_build_tdls_dis_req_ies(padapter, pxmitframe, pframe, ptxmgmt);\n\t\tbreak;\n\tcase TDLS_PEER_TRAFFIC_INDICATION:\n\t\trtw_build_tdls_peer_traffic_indication_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);\n\t\tbreak;\n#ifdef CONFIG_TDLS_CH_SW\n\tcase TDLS_CHANNEL_SWITCH_REQUEST:\n\t\trtw_build_tdls_ch_switch_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);\n\t\tbreak;\n\tcase TDLS_CHANNEL_SWITCH_RESPONSE:\n\t\trtw_build_tdls_ch_switch_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);\n\t\tbreak;\n#endif\n\tcase TDLS_PEER_TRAFFIC_RESPONSE:\n\t\trtw_build_tdls_peer_traffic_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);\n\t\tbreak;\n#ifdef CONFIG_WFD\n\tcase TUNNELED_PROBE_REQ:\n\t\trtw_build_tunneled_probe_req_ies(padapter, pxmitframe, pframe);\n\t\tbreak;\n\tcase TUNNELED_PROBE_RSP:\n\t\trtw_build_tunneled_probe_rsp_ies(padapter, pxmitframe, pframe);\n\t\tbreak;\n#endif /* CONFIG_WFD */\n\tdefault:\n\t\tres = _FAIL;\n\t\tbreak;\n\t}\n\nexit:\n\treturn res;\n}\n\ns32 rtw_make_tdls_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt)\n{\n\tu16 *qc;\n\tstruct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct qos_priv *pqospriv = &pmlmepriv->qospriv;\n\tstruct sta_priv\t*pstapriv = &padapter->stapriv;\n\tstruct sta_info *psta = NULL, *ptdls_sta = NULL;\n\tu8 tdls_seq = 0, baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };\n\n\tsint res = _SUCCESS;\n\tu16 *fctrl = &pwlanhdr->frame_ctl;\n\n\n\t_rtw_memset(hdr, 0, WLANHDR_OFFSET);\n\n\tset_frame_sub_type(fctrl, pattrib->subtype);\n\n\tswitch (ptxmgmt->action_code) {\n\tcase TDLS_SETUP_REQUEST:\n\tcase TDLS_SETUP_RESPONSE:\n\tcase TDLS_SETUP_CONFIRM:\n\tcase TDLS_PEER_TRAFFIC_INDICATION:\n\tcase TDLS_PEER_PSM_REQUEST:\n\tcase TUNNELED_PROBE_REQ:\n\tcase TUNNELED_PROBE_RSP:\n\tcase TDLS_DISCOVERY_REQUEST:\n\t\tSetToDs(fctrl);\n\t\t_rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);\n\t\tbreak;\n\tcase TDLS_CHANNEL_SWITCH_REQUEST:\n\tcase TDLS_CHANNEL_SWITCH_RESPONSE:\n\tcase TDLS_PEER_PSM_RESPONSE:\n\tcase TDLS_PEER_TRAFFIC_RESPONSE:\n\t\t_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);\n\t\ttdls_seq = 1;\n\t\tbreak;\n\tcase TDLS_TEARDOWN:\n\t\tif (ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_) {\n\t\t\t_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);\n\t\t\t_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);\n\t\t\t_rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);\n\t\t\ttdls_seq = 1;\n\t\t} else {\n\t\t\tSetToDs(fctrl);\n\t\t\t_rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN);\n\t\t\t_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);\n\t\t\t_rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);\n\t\t}\n\t\tbreak;\n\t}\n\n\tif (pattrib->encrypt)\n\t\tSetPrivacy(fctrl);\n\n\tif (ptxmgmt->action_code == TDLS_PEER_TRAFFIC_RESPONSE)\n\t\tSetPwrMgt(fctrl);\n\n\tif (pqospriv->qos_option) {\n\t\tqc = (unsigned short *)(hdr + pattrib->hdrlen - 2);\n\t\tif (pattrib->priority)\n\t\t\tSetPriority(qc, pattrib->priority);\n\t\tSetAckpolicy(qc, pattrib->ack_policy);\n\t}\n\n\tpsta = pattrib->psta;\n\n\t/* 1. update seq_num per link by sta_info */\n\t/* 2. rewrite encrypt to _AES_, also rewrite iv_len, icv_len */\n\tif (tdls_seq == 1) {\n\t\tptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst);\n\t\tif (ptdls_sta) {\n\t\t\tptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]++;\n\t\t\tptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF;\n\t\t\tpattrib->seqnum = ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority];\n\t\t\tSetSeqNum(hdr, pattrib->seqnum);\n\n\t\t\tif (pattrib->encrypt) {\n\t\t\t\tpattrib->encrypt = _AES_;\n\t\t\t\tpattrib->iv_len = 8;\n\t\t\t\tpattrib->icv_len = 8;\n\t\t\t\tpattrib->bswenc = _FALSE;\n\t\t\t}\n\t\t\tpattrib->mac_id = ptdls_sta->cmn.mac_id;\n\t\t} else {\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\t} else if (psta) {\n\t\tpsta->sta_xmitpriv.txseq_tid[pattrib->priority]++;\n\t\tpsta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF;\n\t\tpattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority];\n\t\tSetSeqNum(hdr, pattrib->seqnum);\n\t}\n\n\nexit:\n\n\n\treturn res;\n}\n\ns32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt)\n{\n\ts32 llc_sz;\n\n\tu8 *pframe, *mem_start;\n\n\tstruct sta_info\t\t*psta;\n\tstruct sta_priv\t\t*pstapriv = &padapter->stapriv;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct pkt_attrib\t*pattrib = &pxmitframe->attrib;\n\tu8 *pbuf_start;\n\ts32 bmcst = IS_MCAST(pattrib->ra);\n\ts32 res = _SUCCESS;\n\n\n\tif (pattrib->psta)\n\t\tpsta = pattrib->psta;\n\telse {\n\t\tif (bmcst)\n\t\t\tpsta = rtw_get_bcmc_stainfo(padapter);\n\t\telse\n\t\t\tpsta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);\n\t}\n\n\tif (psta == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tif (pxmitframe->buf_addr == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpbuf_start = pxmitframe->buf_addr;\n\tmem_start = pbuf_start + TXDESC_OFFSET;\n\n\tif (rtw_make_tdls_wlanhdr(padapter, mem_start, pattrib, ptxmgmt) == _FAIL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpframe = mem_start;\n\tpframe += pattrib->hdrlen;\n\n\t/* adding icv, if necessary... */\n\tif (pattrib->iv_len) {\n\t\tif (psta != NULL) {\n\t\t\tswitch (pattrib->encrypt) {\n\t\t\tcase _WEP40_:\n\t\t\tcase _WEP104_:\n\t\t\t\tWEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);\n\t\t\t\tbreak;\n\t\t\tcase _TKIP_:\n\t\t\t\tif (bmcst)\n\t\t\t\t\tTKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);\n\t\t\t\telse\n\t\t\t\t\tTKIP_IV(pattrib->iv, psta->dot11txpn, 0);\n\t\t\t\tbreak;\n\t\t\tcase _AES_:\n\t\t\t\tif (bmcst)\n\t\t\t\t\tAES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);\n\t\t\t\telse\n\t\t\t\t\tAES_IV(pattrib->iv, psta->dot11txpn, 0);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\t_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);\n\t\tpframe += pattrib->iv_len;\n\n\t}\n\n\tllc_sz = rtw_put_snap(pframe, pattrib->ether_type);\n\tpframe += llc_sz;\n\n\t/* pattrib->pktlen will be counted in rtw_build_tdls_ies */\n\tpattrib->pktlen = 0;\n\n\trtw_build_tdls_ies(padapter, pxmitframe, pframe, ptxmgmt);\n\n\tif ((pattrib->icv_len > 0) && (pattrib->bswenc)) {\n\t\tpframe += pattrib->pktlen;\n\t\t_rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);\n\t\tpframe += pattrib->icv_len;\n\t}\n\n\tpattrib->nr_frags = 1;\n\tpattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + llc_sz +\n\t\t((pattrib->bswenc) ? pattrib->icv_len : 0) + pattrib->pktlen;\n\n\tif (xmitframe_addmic(padapter, pxmitframe) == _FAIL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\txmitframe_swencrypt(padapter, pxmitframe);\n\n\tupdate_attrib_vcs_info(padapter, pxmitframe);\n\nexit:\n\n\n\treturn res;\n}\n#endif /* CONFIG_TDLS */\n\n/*\n * Calculate wlan 802.11 packet MAX size from pkt_attrib\n * This function doesn't consider fragment case\n */\nu32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib)\n{\n\tu32\tlen = 0;\n\n\tlen = pattrib->hdrlen /* WLAN Header */\n\t\t+ pattrib->iv_len /* IV */\n\t\t+ XATTRIB_GET_MCTRL_LEN(pattrib)\n\t\t+ SNAP_SIZE + sizeof(u16) /* LLC */\n\t\t+ pattrib->pktlen\n\t\t+ (pattrib->encrypt == _TKIP_ ? 8 : 0) /* MIC */\n\t\t+ (pattrib->bswenc ? pattrib->icv_len : 0) /* ICV */\n\t\t;\n\n\treturn len;\n}\n\n#ifdef CONFIG_TX_AMSDU\ns32 check_amsdu(struct xmit_frame *pxmitframe)\n{\n\tstruct pkt_attrib *pattrib;\n\ts32 ret = _TRUE;\n\n\tif (!pxmitframe)\n\t\tret = _FALSE;\n\n\tpattrib = &pxmitframe->attrib;\n\n\tif (IS_MCAST(pattrib->ra))\n\t\tret = _FALSE;\n\n\tif ((pattrib->ether_type == 0x888e) ||\n\t\t(pattrib->ether_type == 0x0806) ||\n\t\t(pattrib->ether_type == 0x88b4) ||\n\t\t(pattrib->dhcp_pkt == 1))\n\t\tret = _FALSE;\n\n\tif ((pattrib->encrypt == _WEP40_) ||\n\t    (pattrib->encrypt == _WEP104_) ||\n\t    (pattrib->encrypt == _TKIP_))\n\t\tret = _FALSE;\n\n\tif (!pattrib->qos_en)\n\t\tret = _FALSE;\n\n\tif (IS_AMSDU_AMPDU_NOT_VALID(pattrib))\n\t\tret = _FALSE;\n\n\treturn ret;\n}\n\ns32 check_amsdu_tx_support(_adapter *padapter)\n{\n\tstruct dvobj_priv *pdvobjpriv;\n\tint tx_amsdu;\n\tint tx_amsdu_rate;\n\tint current_tx_rate;\n\ts32 ret = _FALSE;\n\n\tpdvobjpriv = adapter_to_dvobj(padapter);\n\ttx_amsdu = padapter->tx_amsdu;\n\ttx_amsdu_rate = padapter->tx_amsdu_rate;\n\tcurrent_tx_rate = pdvobjpriv->traffic_stat.cur_tx_tp;\n\n\tif (tx_amsdu == 1)\n\t\tret = _TRUE;\n\telse if (tx_amsdu == 2 && (tx_amsdu_rate == 0 || current_tx_rate > tx_amsdu_rate))\n\t\tret = _TRUE;\n\telse\n\t\tret = _FALSE;\n\n\treturn ret;\n}\n\ns32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue)\n{\n\n\tstruct pkt_file pktfile;\n\tstruct pkt_attrib *pattrib;\n\t_pkt *pkt;\n\n\tstruct pkt_file pktfile_queue;\n\tstruct pkt_attrib *pattrib_queue;\n\t_pkt *pkt_queue;\n\n\ts32 llc_sz, mem_sz;\n\n\ts32 padding = 0;\n\n\tu8 *pframe, *mem_start;\n\tu8 hw_hdr_offset;\n\n\tu16* len;\n\tu8 *pbuf_start;\n\ts32 res = _SUCCESS;\n\n\tif (pxmitframe->buf_addr == NULL) {\n\t\tRTW_INFO(\"==> %s buf_addr==NULL\\n\", __FUNCTION__);\n\t\treturn _FAIL;\n\t}\n\n\n\tpbuf_start = pxmitframe->buf_addr;\n\n#ifdef CONFIG_USB_TX_AGGREGATION\n\thw_hdr_offset =  TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);\n#else\n#ifdef CONFIG_TX_EARLY_MODE /* for SDIO && Tx Agg */\n\thw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;\n#else\n\thw_hdr_offset = TXDESC_OFFSET;\n#endif\n#endif\n\n\tmem_start = pbuf_start + hw_hdr_offset; //for DMA\n\n\tpattrib = &pxmitframe->attrib;\n\n\tpattrib->amsdu = 1;\n\n\tif (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) {\n\t\tRTW_INFO(\"rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\\n\");\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tllc_sz = 0;\n\n\tpframe = mem_start;\n\n\t//SetMFrag(mem_start);\n\tClearMFrag(mem_start);\n\n\tpframe += pattrib->hdrlen;\n\n\t/* adding icv, if necessary... */\n\tif (pattrib->iv_len) {\n\t\t_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); // queue or new?\n\n\t\tRTW_DBG(\"rtw_xmitframe_coalesce: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\\n\",\n\t\t\tpadapter->securitypriv.dot11PrivacyKeyIndex, pattrib->iv[3], *pframe, *(pframe + 1), *(pframe + 2), *(pframe + 3));\n\n\t\tpframe += pattrib->iv_len;\n\t}\n\n\tpattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len;\n\n\tif(pxmitframe_queue)\n\t{\n\t\tpattrib_queue = &pxmitframe_queue->attrib;\n\t\tpkt_queue = pxmitframe_queue->pkt;\n\n\t\t_rtw_open_pktfile(pkt_queue, &pktfile_queue);\n\t\t_rtw_pktfile_read(&pktfile_queue, NULL, pattrib_queue->pkt_hdrlen);\n\n\t\t#ifdef CONFIG_RTW_MESH\n\t\tif (MLME_IS_MESH(padapter)) {\n\t\t\t/* mDA(6), mSA(6), len(2), mctrl */\n\t\t\t_rtw_memcpy(pframe, pattrib_queue->mda, ETH_ALEN);\n\t\t\tpframe += ETH_ALEN;\n\t\t\t_rtw_memcpy(pframe, pattrib_queue->msa, ETH_ALEN);\n\t\t\tpframe += ETH_ALEN;\n\t\t\tlen = (u16*)pframe;\n\t\t\tpframe += 2;\n\t\t\trtw_mesh_tx_build_mctrl(padapter, pattrib_queue, pframe);\n\t\t\tpframe += XATTRIB_GET_MCTRL_LEN(pattrib_queue);\n\t\t} else\n\t\t#endif\n\t\t{\n\t\t\t/* 802.3 MAC Header DA(6)  SA(6)  Len(2)*/\n\t\t\t_rtw_memcpy(pframe, pattrib_queue->dst, ETH_ALEN);\n\t\t\tpframe += ETH_ALEN;\n\t\t\t_rtw_memcpy(pframe, pattrib_queue->src, ETH_ALEN);\n\t\t\tpframe += ETH_ALEN;\n\t\t\tlen = (u16*)pframe;\n\t\t\tpframe += 2;\n\t\t}\n\n\t\tllc_sz = rtw_put_snap(pframe, pattrib_queue->ether_type);\n\t\tpframe += llc_sz;\n\n\t\tmem_sz = _rtw_pktfile_read(&pktfile_queue, pframe, pattrib_queue->pktlen);\n\t\tpframe += mem_sz;\n\n\t\t*len = htons(XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz);\n\n\t\t//calc padding\n\t\tpadding = 4 - ((ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz) & (4-1));\n\t\tif(padding == 4)\n\t\t\tpadding = 0;\n\n\t\t//_rtw_memset(pframe,0xaa, padding);\n\t\tpframe += padding;\n\n\t\tpattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz + padding ;\n\t}\n\n\t//2nd mpdu\n\n\tpkt = pxmitframe->pkt;\n\t_rtw_open_pktfile(pkt, &pktfile);\n\t_rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen);\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(padapter)) {\n\t\t/* mDA(6), mSA(6), len(2), mctrl */\n\t\t_rtw_memcpy(pframe, pattrib->mda, ETH_ALEN);\n\t\tpframe += ETH_ALEN;\n\t\t_rtw_memcpy(pframe, pattrib->msa, ETH_ALEN);\n\t\tpframe += ETH_ALEN;\n\t\tlen = (u16*)pframe;\n\t\tpframe += 2;\n\t\trtw_mesh_tx_build_mctrl(padapter, pattrib, pframe);\n\t\tpframe += XATTRIB_GET_MCTRL_LEN(pattrib);\n\t} else\n#endif\n\t{\n\t\t/* 802.3 MAC Header  DA(6)  SA(6)  Len(2) */\n\t\t_rtw_memcpy(pframe, pattrib->dst, ETH_ALEN);\n\t\tpframe += ETH_ALEN;\n\t\t_rtw_memcpy(pframe, pattrib->src, ETH_ALEN);\n\t\tpframe += ETH_ALEN;\n\t\tlen = (u16*)pframe;\n\t\tpframe += 2;\n\t}\n\n\tllc_sz = rtw_put_snap(pframe, pattrib->ether_type);\n\tpframe += llc_sz;\n\n\tmem_sz = _rtw_pktfile_read(&pktfile, pframe, pattrib->pktlen);\n\n\tpframe += mem_sz;\n\n\t*len = htons(XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz);\n\n\t//the last ampdu has no padding\n\tpadding = 0;\n\n\tpattrib->nr_frags = 1;\n\n\tpattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz + padding +\n\t\t((pattrib->bswenc) ? pattrib->icv_len : 0) ;\n\n\tif ((pattrib->icv_len > 0) && (pattrib->bswenc)) {\n\t\t_rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);\n\t\tpframe += pattrib->icv_len;\n\t}\n\n\tif (xmitframe_addmic(padapter, pxmitframe) == _FAIL) {\n\t\tRTW_INFO(\"xmitframe_addmic(padapter, pxmitframe)==_FAIL\\n\");\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\txmitframe_swencrypt(padapter, pxmitframe);\n\n\tupdate_attrib_vcs_info(padapter, pxmitframe);\n\nexit:\n\treturn res;\n}\n#endif /* CONFIG_TX_AMSDU */\n\n/*\n\nThis sub-routine will perform all the following:\n\n1. remove 802.3 header.\n2. create wlan_header, based on the info in pxmitframe\n3. append sta's iv/ext-iv\n4. append LLC\n5. move frag chunk from pframe to pxmitframe->mem\n6. apply sw-encrypt, if necessary.\n\n*/\ns32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe)\n{\n\tstruct pkt_file pktfile;\n\n\ts32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz;\n\n\tSIZE_PTR addr;\n\n\tu8 *pframe, *mem_start;\n\tu8 hw_hdr_offset;\n\n\t/* struct sta_info\t\t*psta; */\n\t/* struct sta_priv\t\t*pstapriv = &padapter->stapriv; */\n\t/* struct mlme_priv\t*pmlmepriv = &padapter->mlmepriv; */\n\tstruct xmit_priv\t*pxmitpriv = &padapter->xmitpriv;\n\n\tstruct pkt_attrib\t*pattrib = &pxmitframe->attrib;\n\n\tu8 *pbuf_start;\n\n\ts32 bmcst = IS_MCAST(pattrib->ra);\n\ts32 res = _SUCCESS;\n\n\n\t/*\n\t\tif (pattrib->psta)\n\t\t{\n\t\t\tpsta = pattrib->psta;\n\t\t} else\n\t\t{\n\t\t\tRTW_INFO(\"%s, call rtw_get_stainfo()\\n\", __func__);\n\t\t\tpsta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);\n\t\t}\n\n\t\tif(psta==NULL)\n\t\t{\n\n\t\t\tRTW_INFO(\"%s, psta==NUL\\n\", __func__);\n\t\t\treturn _FAIL;\n\t\t}\n\n\n\t\tif(!(psta->state &_FW_LINKED))\n\t\t{\n\t\t\tRTW_INFO(\"%s, psta->state(0x%x) != _FW_LINKED\\n\", __func__, psta->state);\n\t\t\treturn _FAIL;\n\t\t}\n\t*/\n\tif (pxmitframe->buf_addr == NULL) {\n\t\tRTW_INFO(\"==> %s buf_addr==NULL\\n\", __FUNCTION__);\n\t\treturn _FAIL;\n\t}\n\n\tpbuf_start = pxmitframe->buf_addr;\n\n#ifdef CONFIG_USB_TX_AGGREGATION\n\thw_hdr_offset =  TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);\n#else\n#ifdef CONFIG_TX_EARLY_MODE /* for SDIO && Tx Agg */\n\thw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;\n#else\n\thw_hdr_offset = TXDESC_OFFSET;\n#endif\n#endif\n\n\tmem_start = pbuf_start +\thw_hdr_offset;\n\n\tif (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) {\n\t\tRTW_INFO(\"rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\\n\");\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t_rtw_open_pktfile(pkt, &pktfile);\n\t_rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen);\n\n\tfrg_inx = 0;\n\tfrg_len = pxmitpriv->frag_len - 4;/* 2346-4 = 2342 */\n\n\twhile (1) {\n\t\tllc_sz = 0;\n\n\t\tmpdu_len = frg_len;\n\n\t\tpframe = mem_start;\n\n\t\tSetMFrag(mem_start);\n\n\t\tpframe += pattrib->hdrlen;\n\t\tmpdu_len -= pattrib->hdrlen;\n\n\t\t/* adding icv, if necessary... */\n\t\tif (pattrib->iv_len) {\n#if 0\n\t\t\t/* if (check_fwstate(pmlmepriv, WIFI_MP_STATE)) */\n\t\t\t/*\tpsta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); */\n\t\t\t/* else */\n\t\t\t/*\tpsta = rtw_get_stainfo(pstapriv, pattrib->ra); */\n\n\t\t\tif (psta != NULL) {\n\t\t\t\tswitch (pattrib->encrypt) {\n\t\t\t\tcase _WEP40_:\n\t\t\t\tcase _WEP104_:\n\t\t\t\t\tWEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);\n\t\t\t\t\tbreak;\n\t\t\t\tcase _TKIP_:\n\t\t\t\t\tif (bmcst)\n\t\t\t\t\t\tTKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);\n\t\t\t\t\telse\n\t\t\t\t\t\tTKIP_IV(pattrib->iv, psta->dot11txpn, 0);\n\t\t\t\t\tbreak;\n\t\t\t\tcase _AES_:\n\t\t\t\t\tif (bmcst)\n\t\t\t\t\t\tAES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);\n\t\t\t\t\telse\n\t\t\t\t\t\tAES_IV(pattrib->iv, psta->dot11txpn, 0);\n\t\t\t\t\tbreak;\n#ifdef CONFIG_WAPI_SUPPORT\n\t\t\t\tcase _SMS4_:\n\t\t\t\t\trtw_wapi_get_iv(padapter, pattrib->ra, pattrib->iv);\n\t\t\t\t\tbreak;\n#endif\n\t\t\t\t}\n\t\t\t}\n#endif\n\t\t\t_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);\n\n\n\t\t\tpframe += pattrib->iv_len;\n\n\t\t\tmpdu_len -= pattrib->iv_len;\n\t\t}\n\n\t\tif (frg_inx == 0) {\n\t\t\t#ifdef CONFIG_RTW_MESH\n\t\t\tif (MLME_IS_MESH(padapter)) {\n\t\t\t\trtw_mesh_tx_build_mctrl(padapter, pattrib, pframe);\n\t\t\t\tpframe += XATTRIB_GET_MCTRL_LEN(pattrib);\n\t\t\t\tmpdu_len -= XATTRIB_GET_MCTRL_LEN(pattrib);\n\t\t\t}\n\t\t\t#endif\n\n\t\t\tllc_sz = rtw_put_snap(pframe, pattrib->ether_type);\n\t\t\tpframe += llc_sz;\n\t\t\tmpdu_len -= llc_sz;\n\t\t}\n\n\t\tif ((pattrib->icv_len > 0) && (pattrib->bswenc))\n\t\t\tmpdu_len -= pattrib->icv_len;\n\n\n\t\tif (bmcst) {\n\t\t\t/* don't do fragment to broadcat/multicast packets */\n\t\t\tmem_sz = _rtw_pktfile_read(&pktfile, pframe, pattrib->pktlen);\n\t\t} else\n\t\t\tmem_sz = _rtw_pktfile_read(&pktfile, pframe, mpdu_len);\n\n\t\tpframe += mem_sz;\n\n\t\tif ((pattrib->icv_len > 0) && (pattrib->bswenc)) {\n\t\t\t_rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);\n\t\t\tpframe += pattrib->icv_len;\n\t\t}\n\n\t\tfrg_inx++;\n\n\t\tif (bmcst || (rtw_endofpktfile(&pktfile) == _TRUE)) {\n\t\t\tpattrib->nr_frags = frg_inx;\n\n\t\t\tpattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len +\n\t\t\t\t((pattrib->nr_frags == 1) ? (XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz) : 0) +\n\t\t\t\t((pattrib->bswenc) ? pattrib->icv_len : 0) + mem_sz;\n\n\t\t\tClearMFrag(mem_start);\n\n\t\t\tbreak;\n\t\t}\n\n\t\taddr = (SIZE_PTR)(pframe);\n\n\t\tmem_start = (unsigned char *)RND4(addr) + hw_hdr_offset;\n\t\t_rtw_memcpy(mem_start, pbuf_start + hw_hdr_offset, pattrib->hdrlen);\n\n\t}\n\n\tif (xmitframe_addmic(padapter, pxmitframe) == _FAIL) {\n\t\tRTW_INFO(\"xmitframe_addmic(padapter, pxmitframe)==_FAIL\\n\");\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\txmitframe_swencrypt(padapter, pxmitframe);\n\n\tif (bmcst == _FALSE)\n\t\tupdate_attrib_vcs_info(padapter, pxmitframe);\n\telse\n\t\tpattrib->vcs_mode = NONE_VCS;\n\nexit:\n\n\n\treturn res;\n}\n\n#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)\n/*\n * CCMP encryption for unicast robust mgmt frame and broadcast group privicy action\n * BIP for broadcast robust mgmt frame\n */\ns32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe)\n{\n#define DBG_MGMT_XMIT_COALESEC_DUMP 0\n#define DBG_MGMT_XMIT_BIP_DUMP 0\n#define DBG_MGMT_XMIT_ENC_DUMP 0\n\n\tstruct pkt_file pktfile;\n\ts32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz;\n\tSIZE_PTR addr;\n\tu8 *pframe, *mem_start = NULL, *tmp_buf = NULL;\n\tu8 hw_hdr_offset, subtype ;\n\tu8 category = 0xFF;\n\tstruct sta_info\t\t*psta = NULL;\n\tstruct xmit_priv\t*pxmitpriv = &padapter->xmitpriv;\n\tstruct pkt_attrib\t*pattrib = &pxmitframe->attrib;\n\tu8 *pbuf_start;\n\ts32 bmcst = IS_MCAST(pattrib->ra);\n\ts32 res = _FAIL;\n\tu8 *BIP_AAD = NULL;\n\tu8 *MGMT_body = NULL;\n\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tu8 MME[_MME_IE_LENGTH_];\n\n\t_irqL irqL;\n\tu32\tori_len;\n\tunion pn48 *pn = NULL;\n\tu8 kid;\n\n\tif (pxmitframe->buf_addr == NULL) {\n\t\tRTW_WARN(FUNC_ADPT_FMT\" pxmitframe->buf_addr\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter));\n\t\treturn _FAIL;\n\t}\n\n\tmem_start = pframe = (u8 *)(pxmitframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\tsubtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */\n\n\t/* check if robust mgmt frame */\n\tif (subtype != WIFI_DEAUTH && subtype != WIFI_DISASSOC && subtype != WIFI_ACTION)\n\t\treturn _SUCCESS;\n\tif (subtype == WIFI_ACTION) {\n\t\tcategory = *(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));\n\t\tif (CATEGORY_IS_NON_ROBUST(category))\n\t\t\treturn _SUCCESS;\n\t}\n\tif (!bmcst) {\n\t\tif (pattrib->psta)\n\t\t\tpsta = pattrib->psta;\n\t\telse\n\t\t\tpattrib->psta = psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);\n\t\tif (psta == NULL) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" unicast sta == NULL\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\treturn _FAIL;\n\t\t}\n\t\tif (!(psta->flags & WLAN_STA_MFP)) {\n\t\t\t/* peer is not MFP capable, no need to encrypt */\n\t\t\treturn _SUCCESS;\n\t\t}\n\t\tif (psta->bpairwise_key_installed != _TRUE) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" PTK is not installed\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter));\n\t\t\treturn _FAIL;\n\t\t}\n\t}\n\n\tori_len = BIP_AAD_SIZE + pattrib->pktlen;\n\ttmp_buf = BIP_AAD = rtw_zmalloc(ori_len);\n\tif (BIP_AAD == NULL)\n\t\treturn _FAIL;\n\n\t_enter_critical_bh(&padapter->security_key_mutex, &irqL);\n\n\tif (bmcst) {\n\t\tif (subtype == WIFI_ACTION && CATEGORY_IS_GROUP_PRIVACY(category)) {\n\t\t\t/* broadcast group privacy action frame */\n\t\t\t#if DBG_MGMT_XMIT_COALESEC_DUMP\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" broadcast gp action(%u)\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter), category);\n\t\t\t#endif\n\n\t\t\tif (pattrib->psta)\n\t\t\t\tpsta = pattrib->psta;\n\t\t\telse\n\t\t\t\tpattrib->psta = psta = rtw_get_bcmc_stainfo(padapter);\n\t\t\tif (psta == NULL) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" broadcast sta == NULL\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter));\n\t\t\t\tgoto xmitframe_coalesce_fail;\n\t\t\t}\n\t\t\tif (padapter->securitypriv.binstallGrpkey != _TRUE) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" GTK is not installed\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter));\n\t\t\t\tgoto xmitframe_coalesce_fail;\n\t\t\t}\n\n\t\t\tpn = &psta->dot11txpn;\n\t\t\tkid = padapter->securitypriv.dot118021XGrpKeyid;\n\t\t} else {\n\t\t\t#ifdef CONFIG_IEEE80211W\n\t\t\t/* broadcast robust mgmt frame, using BIP */\n\t\t\tint frame_body_len;\n\t\t\tu8 mic[16];\n\n\t\t\t/* IGTK key is not install ex: mesh MFP without IGTK */\n\t\t\tif (SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) != _TRUE)\n\t\t\t\tgoto xmitframe_coalesce_success;\n\n\t\t\t#if DBG_MGMT_XMIT_COALESEC_DUMP\n\t\t\tif (subtype == WIFI_DEAUTH)\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" braodcast deauth\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\telse if (subtype == WIFI_DISASSOC)\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" braodcast disassoc\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\telse if (subtype == WIFI_ACTION) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" braodcast action(%u)\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), category);\n\t\t\t}\n\t\t\t#endif\n\n\t\t\t_rtw_memset(MME, 0, _MME_IE_LENGTH_);\n\n\t\t\tMGMT_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);\n\t\t\tpframe += pattrib->pktlen;\n\n\t\t\t/* octent 0 and 1 is key index ,BIP keyid is 4 or 5, LSB only need octent 0 */\n\t\t\tMME[0] = padapter->securitypriv.dot11wBIPKeyid;\n\t\t\t/* increase PN and apply to packet */\n\t\t\tpadapter->securitypriv.dot11wBIPtxpn.val++;\n\t\t\tRTW_PUT_LE64(&MME[2], padapter->securitypriv.dot11wBIPtxpn.val);\n\n\t\t\t/* add MME IE with MIC all zero, MME string doesn't include element id and length */\n\t\t\tpframe = rtw_set_ie(pframe, _MME_IE_ , 16 , MME, &(pattrib->pktlen));\n\t\t\tpattrib->last_txcmdsz = pattrib->pktlen;\n\t\t\t/* total frame length - header length */\n\t\t\tframe_body_len = pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\t\t\t/* conscruct AAD, copy frame control field */\n\t\t\t_rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2);\n\t\t\tClearRetry(BIP_AAD);\n\t\t\tClearPwrMgt(BIP_AAD);\n\t\t\tClearMData(BIP_AAD);\n\t\t\t/* conscruct AAD, copy address 1 to address 3 */\n\t\t\t_rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18);\n\t\t\t/* copy management fram body */\n\t\t\t_rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, MGMT_body, frame_body_len);\n\n\t\t\t#if DBG_MGMT_XMIT_BIP_DUMP\n\t\t\t/* dump total packet include MME with zero MIC */\n\t\t\t{\n\t\t\t\tint i;\n\t\t\t\tprintk(\"Total packet: \");\n\t\t\t\tfor (i = 0; i < BIP_AAD_SIZE + frame_body_len; i++)\n\t\t\t\t\tprintk(\" %02x \", BIP_AAD[i]);\n\t\t\t\tprintk(\"\\n\");\n\t\t\t}\n\t\t\t#endif\n\n\t\t\t/* calculate mic */\n\t\t\tif (omac1_aes_128(padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey\n\t\t\t\t  , BIP_AAD, BIP_AAD_SIZE + frame_body_len, mic))\n\t\t\t\tgoto xmitframe_coalesce_fail;\n\n\t\t\t#if DBG_MGMT_XMIT_BIP_DUMP\n\t\t\t/* dump calculated mic result */\n\t\t\t{\n\t\t\t\tint i;\n\t\t\t\tprintk(\"Calculated mic result: \");\n\t\t\t\tfor (i = 0; i < 16; i++)\n\t\t\t\t\tprintk(\" %02x \", mic[i]);\n\t\t\t\tprintk(\"\\n\");\n\t\t\t}\n\t\t\t#endif\n\n\t\t\t/* copy right BIP mic value, total is 128bits, we use the 0~63 bits */\n\t\t\t_rtw_memcpy(pframe - 8, mic, 8);\n\n\t\t\t#if DBG_MGMT_XMIT_BIP_DUMP\n\t\t\t/*dump all packet after mic ok */\n\t\t\t{\n\t\t\t\tint pp;\n\t\t\t\tprintk(\"pattrib->pktlen = %d\\n\", pattrib->pktlen);\n\t\t\t\tfor(pp=0;pp< pattrib->pktlen; pp++)\n\t\t\t\t\tprintk(\" %02x \", mem_start[pp]);\n\t\t\t\tprintk(\"\\n\");\n\t\t\t}\n\t\t\t#endif\n\n\t\t\t#endif /* CONFIG_IEEE80211W */\n\n\t\t\tgoto xmitframe_coalesce_success;\n\t\t}\n\t}\n\telse {\n\t\t/* unicast robust mgmt frame */\n\t\t#if DBG_MGMT_XMIT_COALESEC_DUMP\n\t\tif (subtype == WIFI_DEAUTH) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" unicast deauth to \"MAC_FMT\"\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra));\n\t\t} else if (subtype == WIFI_DISASSOC) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" unicast disassoc to \"MAC_FMT\"\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra));\n\t\t} else if (subtype == WIFI_ACTION) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" unicast action(%u) to \"MAC_FMT\"\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter), category, MAC_ARG(pattrib->ra));\n\t\t}\n\t\t#endif\n\n\t\t_rtw_memcpy(pattrib->dot118021x_UncstKey.skey, psta->dot118021x_UncstKey.skey, 16);\n\n\t\t/* To use wrong key */\n\t\tif (pattrib->key_type == IEEE80211W_WRONG_KEY) {\n\t\t\tRTW_INFO(\"use wrong key\\n\");\n\t\t\tpattrib->dot118021x_UncstKey.skey[0] = 0xff;\n\t\t}\n\n\t\tpn = &psta->dot11txpn;\n\t\tkid = 0;\n\t}\n\n\t#if DBG_MGMT_XMIT_ENC_DUMP\n\t/* before encrypt dump the management packet content */\n\t{\n\t\tint i;\n\t\tprintk(\"Management pkt: \");\n\t\tfor(i=0; i<pattrib->pktlen; i++)\n\t\tprintk(\" %02x \", pframe[i]);\n\t\tprintk(\"=======\\n\");\n\t}\n\t#endif\n\n\t/* bakeup original management packet */\n\t_rtw_memcpy(tmp_buf, pframe, pattrib->pktlen);\n\t/* move to data portion */\n\tpframe += pattrib->hdrlen;\n\n\t/* 802.11w encrypted management packet must be _AES_ */\n\tif (pattrib->key_type != IEEE80211W_NO_KEY) {\n\t\tpattrib->encrypt = _AES_;\n\t\tpattrib->bswenc = _TRUE;\n\t}\n\n\tpattrib->iv_len = 8;\n\t/* it's MIC of AES */\n\tpattrib->icv_len = 8;\n\n\tswitch (pattrib->encrypt) {\n\tcase _AES_:\n\t\t/* set AES IV header */\n\t\tAES_IV(pattrib->iv, (*pn), kid);\n\t\tbreak;\n\tdefault:\n\t\tgoto xmitframe_coalesce_fail;\n\t}\n\n\t/* insert iv header into management frame */\n\t_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);\n\tpframe += pattrib->iv_len;\n\t/* copy mgmt data portion after CCMP header */\n\t_rtw_memcpy(pframe, tmp_buf + pattrib->hdrlen, pattrib->pktlen - pattrib->hdrlen);\n\t/* move pframe to end of mgmt pkt */\n\tpframe += pattrib->pktlen - pattrib->hdrlen;\n\t/* add 8 bytes CCMP IV header to length */\n\tpattrib->pktlen += pattrib->iv_len;\n\n\t#if DBG_MGMT_XMIT_ENC_DUMP\n\t/* dump management packet include AES IV header */\n\t{\n\t\tint i;\n\t\tprintk(\"Management pkt + IV: \");\n\t\t/* for(i=0; i<pattrib->pktlen; i++) */\n\n\t\tprintk(\"@@@@@@@@@@@@@\\n\");\n\t}\n\t#endif\n\n\tif ((pattrib->icv_len > 0) && (pattrib->bswenc)) {\n\t\t_rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);\n\t\tpframe += pattrib->icv_len;\n\t}\n\t/* add 8 bytes MIC */\n\tpattrib->pktlen += pattrib->icv_len;\n\t/* set final tx command size */\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\t/* set protected bit must be beofre SW encrypt */\n\tSetPrivacy(mem_start);\n\n\t#if DBG_MGMT_XMIT_ENC_DUMP\n\t/* dump management packet include AES header */\n\t{\n\t\tint i;\n\t\tprintk(\"prepare to enc Management pkt + IV: \");\n\t\tfor (i = 0; i < pattrib->pktlen; i++)\n\t\t\tprintk(\" %02x \", mem_start[i]);\n\t\tprintk(\"@@@@@@@@@@@@@\\n\");\n\t}\n\t#endif\n\n\t/* software encrypt */\n\txmitframe_swencrypt(padapter, pxmitframe);\n\nxmitframe_coalesce_success:\n\t_exit_critical_bh(&padapter->security_key_mutex, &irqL);\n\trtw_mfree(BIP_AAD, ori_len);\n\treturn _SUCCESS;\n\nxmitframe_coalesce_fail:\n\t_exit_critical_bh(&padapter->security_key_mutex, &irqL);\n\trtw_mfree(BIP_AAD, ori_len);\n\n\treturn _FAIL;\n}\n#endif /* defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) */\n\n/* Logical Link Control(LLC) SubNetwork Attachment Point(SNAP) header\n * IEEE LLC/SNAP header contains 8 octets\n * First 3 octets comprise the LLC portion\n * SNAP portion, 5 octets, is divided into two fields:\n *\tOrganizationally Unique Identifier(OUI), 3 octets,\n *\ttype, defined by that organization, 2 octets.\n */\ns32 rtw_put_snap(u8 *data, u16 h_proto)\n{\n\tstruct ieee80211_snap_hdr *snap;\n\tu8 *oui;\n\n\n\tsnap = (struct ieee80211_snap_hdr *)data;\n\tsnap->dsap = 0xaa;\n\tsnap->ssap = 0xaa;\n\tsnap->ctrl = 0x03;\n\n\tif (h_proto == 0x8137 || h_proto == 0x80f3)\n\t\toui = P802_1H_OUI;\n\telse\n\t\toui = RFC1042_OUI;\n\n\tsnap->oui[0] = oui[0];\n\tsnap->oui[1] = oui[1];\n\tsnap->oui[2] = oui[2];\n\n\t*(u16 *)(data + SNAP_SIZE) = htons(h_proto);\n\n\n\treturn SNAP_SIZE + sizeof(u16);\n}\n\nvoid rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len)\n{\n\n\tuint\tprotection;\n\tu8\t*perp;\n\tsint\t erp_len;\n\tstruct\txmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tstruct\tregistry_priv *pregistrypriv = &padapter->registrypriv;\n\n\n\tswitch (pxmitpriv->vcs_setting) {\n\tcase DISABLE_VCS:\n\t\tpxmitpriv->vcs = NONE_VCS;\n\t\tbreak;\n\n\tcase ENABLE_VCS:\n\t\tbreak;\n\n\tcase AUTO_VCS:\n\tdefault:\n\t\tperp = rtw_get_ie(ie, _ERPINFO_IE_, &erp_len, ie_len);\n\t\tif (perp == NULL)\n\t\t\tpxmitpriv->vcs = NONE_VCS;\n\t\telse {\n\t\t\tprotection = (*(perp + 2)) & BIT(1);\n\t\t\tif (protection) {\n\t\t\t\tif (pregistrypriv->vcs_type == RTS_CTS)\n\t\t\t\t\tpxmitpriv->vcs = RTS_CTS;\n\t\t\t\telse\n\t\t\t\t\tpxmitpriv->vcs = CTS_TO_SELF;\n\t\t\t} else\n\t\t\t\tpxmitpriv->vcs = NONE_VCS;\n\t\t}\n\n\t\tbreak;\n\n\t}\n\n\n}\n\nvoid rtw_count_tx_stats(PADAPTER padapter, struct xmit_frame *pxmitframe, int sz)\n{\n\tstruct sta_info *psta = NULL;\n\tstruct stainfo_stats *pstats = NULL;\n\tstruct xmit_priv\t*pxmitpriv = &padapter->xmitpriv;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tu8\tpkt_num = 1;\n\n\tif ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) {\n#if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t\tpkt_num = pxmitframe->agg_num;\n#endif\n\t\tpmlmepriv->LinkDetectInfo.NumTxOkInPeriod += pkt_num;\n\n\t\tpxmitpriv->tx_pkts += pkt_num;\n\n\t\tpxmitpriv->tx_bytes += sz;\n\n\t\tpsta = pxmitframe->attrib.psta;\n\t\tif (psta) {\n\t\t\tpstats = &psta->sta_stats;\n\n\t\t\tpstats->tx_pkts += pkt_num;\n\n\t\t\tpstats->tx_bytes += sz;\n\t\t\t#if defined(CONFIG_CHECK_LEAVE_LPS) && defined(CONFIG_LPS_CHK_BY_TP)\n\t\t\tif (adapter_to_pwrctl(padapter)->lps_chk_by_tp)\n\t\t\t\ttraffic_check_for_leave_lps_by_tp(padapter, _TRUE, psta);\n\t\t\t#endif /* CONFIG_LPS */\n\t\t}\n\n#ifdef CONFIG_CHECK_LEAVE_LPS\n\t\t/* traffic_check_for_leave_lps(padapter, _TRUE); */\n#endif /* CONFIG_CHECK_LEAVE_LPS */\n\n\t}\n}\n\nstatic struct xmit_buf *__rtw_alloc_cmd_xmitbuf(struct xmit_priv *pxmitpriv,\n\t\tenum cmdbuf_type buf_type)\n{\n\tstruct xmit_buf *pxmitbuf =  NULL;\n\n\n\tpxmitbuf = &pxmitpriv->pcmd_xmitbuf[buf_type];\n\tif (pxmitbuf !=  NULL) {\n\t\tpxmitbuf->priv_data = NULL;\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t\tpxmitbuf->len = 0;\n\t\tpxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;\n\t\tpxmitbuf->agg_num = 0;\n\t\tpxmitbuf->pg_num = 0;\n#endif\n#ifdef CONFIG_PCI_HCI\n\t\tpxmitbuf->len = 0;\n#ifdef CONFIG_TRX_BD_ARCH\n\t\t/*pxmitbuf->buf_desc = NULL;*/\n#else\n\t\tpxmitbuf->desc = NULL;\n#endif\n#endif\n\n\t\tif (pxmitbuf->sctx) {\n\t\t\tRTW_INFO(\"%s pxmitbuf->sctx is not NULL\\n\", __func__);\n\t\t\trtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC);\n\t\t}\n\t} else\n\t\tRTW_INFO(\"%s fail, no xmitbuf available !!!\\n\", __func__);\n\n\treturn pxmitbuf;\n}\n\nstruct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv,\n\t\tenum cmdbuf_type buf_type)\n{\n\tstruct xmit_frame\t\t*pcmdframe;\n\tstruct xmit_buf\t\t*pxmitbuf;\n\n\tpcmdframe = rtw_alloc_xmitframe(pxmitpriv);\n\tif (pcmdframe == NULL) {\n\t\tRTW_INFO(\"%s, alloc xmitframe fail\\n\", __FUNCTION__);\n\t\treturn NULL;\n\t}\n\n\tpxmitbuf = __rtw_alloc_cmd_xmitbuf(pxmitpriv, buf_type);\n\tif (pxmitbuf == NULL) {\n\t\tRTW_INFO(\"%s, alloc xmitbuf fail\\n\", __FUNCTION__);\n\t\trtw_free_xmitframe(pxmitpriv, pcmdframe);\n\t\treturn NULL;\n\t}\n\n\tpcmdframe->frame_tag = MGNT_FRAMETAG;\n\n\tpcmdframe->pxmitbuf = pxmitbuf;\n\n\tpcmdframe->buf_addr = pxmitbuf->pbuf;\n\n\t/* initial memory to zero */\n\t_rtw_memset(pcmdframe->buf_addr, 0, MAX_CMDBUF_SZ);\n\n\tpxmitbuf->priv_data = pcmdframe;\n\n\treturn pcmdframe;\n\n}\n\nstruct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv)\n{\n\t_irqL irqL;\n\tstruct xmit_buf *pxmitbuf =  NULL;\n\t_list *plist, *phead;\n\t_queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue;\n\n\n\t_enter_critical(&pfree_queue->lock, &irqL);\n\n\tif (_rtw_queue_empty(pfree_queue) == _TRUE)\n\t\tpxmitbuf = NULL;\n\telse {\n\n\t\tphead = get_list_head(pfree_queue);\n\n\t\tplist = get_next(phead);\n\n\t\tpxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);\n\n\t\trtw_list_delete(&(pxmitbuf->list));\n\t}\n\n\tif (pxmitbuf !=  NULL) {\n\t\tpxmitpriv->free_xmit_extbuf_cnt--;\n#ifdef DBG_XMIT_BUF_EXT\n\t\tRTW_INFO(\"DBG_XMIT_BUF_EXT ALLOC no=%d,  free_xmit_extbuf_cnt=%d\\n\", pxmitbuf->no, pxmitpriv->free_xmit_extbuf_cnt);\n#endif\n\n\n\t\tpxmitbuf->priv_data = NULL;\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t\tpxmitbuf->len = 0;\n\t\tpxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;\n\t\tpxmitbuf->agg_num = 1;\n#endif\n#ifdef CONFIG_PCI_HCI\n\t\tpxmitbuf->len = 0;\n#ifdef CONFIG_TRX_BD_ARCH\n\t\t/*pxmitbuf->buf_desc = NULL;*/\n#else\n\t\tpxmitbuf->desc = NULL;\n#endif\n#endif\n\n\t\tif (pxmitbuf->sctx) {\n\t\t\tRTW_INFO(\"%s pxmitbuf->sctx is not NULL\\n\", __func__);\n\t\t\trtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC);\n\t\t}\n\n\t}\n\n\t_exit_critical(&pfree_queue->lock, &irqL);\n\n\n\treturn pxmitbuf;\n}\n\ns32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)\n{\n\t_irqL irqL;\n\t_queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue;\n\n\n\tif (pxmitbuf == NULL)\n\t\treturn _FAIL;\n\n\t_enter_critical(&pfree_queue->lock, &irqL);\n\n\trtw_list_delete(&pxmitbuf->list);\n\n\trtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_queue));\n\tpxmitpriv->free_xmit_extbuf_cnt++;\n#ifdef DBG_XMIT_BUF_EXT\n\tRTW_INFO(\"DBG_XMIT_BUF_EXT FREE no=%d, free_xmit_extbuf_cnt=%d\\n\", pxmitbuf->no , pxmitpriv->free_xmit_extbuf_cnt);\n#endif\n\n\t_exit_critical(&pfree_queue->lock, &irqL);\n\n\n\treturn _SUCCESS;\n}\n\nstruct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv)\n{\n\t_irqL irqL;\n\tstruct xmit_buf *pxmitbuf =  NULL;\n\t_list *plist, *phead;\n\t_queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue;\n\n\n\t/* RTW_INFO(\"+rtw_alloc_xmitbuf\\n\"); */\n\n\t_enter_critical(&pfree_xmitbuf_queue->lock, &irqL);\n\n\tif (_rtw_queue_empty(pfree_xmitbuf_queue) == _TRUE)\n\t\tpxmitbuf = NULL;\n\telse {\n\n\t\tphead = get_list_head(pfree_xmitbuf_queue);\n\n\t\tplist = get_next(phead);\n\n\t\tpxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);\n\n\t\trtw_list_delete(&(pxmitbuf->list));\n\t}\n\n\tif (pxmitbuf !=  NULL) {\n\t\tpxmitpriv->free_xmitbuf_cnt--;\n#ifdef DBG_XMIT_BUF\n\t\tRTW_INFO(\"DBG_XMIT_BUF ALLOC no=%d,  free_xmitbuf_cnt=%d\\n\", pxmitbuf->no, pxmitpriv->free_xmitbuf_cnt);\n#endif\n\t\t/* RTW_INFO(\"alloc, free_xmitbuf_cnt=%d\\n\", pxmitpriv->free_xmitbuf_cnt); */\n\n\t\tpxmitbuf->priv_data = NULL;\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t\tpxmitbuf->len = 0;\n\t\tpxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;\n\t\tpxmitbuf->agg_num = 0;\n\t\tpxmitbuf->pg_num = 0;\n#endif\n#ifdef CONFIG_PCI_HCI\n\t\tpxmitbuf->len = 0;\n#ifdef CONFIG_TRX_BD_ARCH\n\t\t/*pxmitbuf->buf_desc = NULL;*/\n#else\n\t\tpxmitbuf->desc = NULL;\n#endif\n#endif\n\n\t\tif (pxmitbuf->sctx) {\n\t\t\tRTW_INFO(\"%s pxmitbuf->sctx is not NULL\\n\", __func__);\n\t\t\trtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC);\n\t\t}\n\t}\n#ifdef DBG_XMIT_BUF\n\telse\n\t\tRTW_INFO(\"DBG_XMIT_BUF rtw_alloc_xmitbuf return NULL\\n\");\n#endif\n\n\t_exit_critical(&pfree_xmitbuf_queue->lock, &irqL);\n\n\n\treturn pxmitbuf;\n}\n\ns32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)\n{\n\t_irqL irqL;\n\t_queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue;\n\n\n\t/* RTW_INFO(\"+rtw_free_xmitbuf\\n\"); */\n\n\tif (pxmitbuf == NULL)\n\t\treturn _FAIL;\n\n\tif (pxmitbuf->sctx) {\n\t\tRTW_INFO(\"%s pxmitbuf->sctx is not NULL\\n\", __func__);\n\t\trtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_FREE);\n\t}\n\n\tif (pxmitbuf->buf_tag == XMITBUF_CMD) {\n\t} else if (pxmitbuf->buf_tag == XMITBUF_MGNT)\n\t\trtw_free_xmitbuf_ext(pxmitpriv, pxmitbuf);\n\telse {\n\t\t_enter_critical(&pfree_xmitbuf_queue->lock, &irqL);\n\n\t\trtw_list_delete(&pxmitbuf->list);\n\n\t\trtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_xmitbuf_queue));\n\n\t\tpxmitpriv->free_xmitbuf_cnt++;\n\t\t/* RTW_INFO(\"FREE, free_xmitbuf_cnt=%d\\n\", pxmitpriv->free_xmitbuf_cnt); */\n#ifdef DBG_XMIT_BUF\n\t\tRTW_INFO(\"DBG_XMIT_BUF FREE no=%d, free_xmitbuf_cnt=%d\\n\", pxmitbuf->no , pxmitpriv->free_xmitbuf_cnt);\n#endif\n\t\t_exit_critical(&pfree_xmitbuf_queue->lock, &irqL);\n\t}\n\n\n\treturn _SUCCESS;\n}\n\nvoid rtw_init_xmitframe(struct xmit_frame *pxframe)\n{\n\tif (pxframe !=  NULL) { /* default value setting */\n\t\tpxframe->buf_addr = NULL;\n\t\tpxframe->pxmitbuf = NULL;\n\n\t\t_rtw_memset(&pxframe->attrib, 0, sizeof(struct pkt_attrib));\n\t\t/* pxframe->attrib.psta = NULL; */\n\n\t\tpxframe->frame_tag = DATA_FRAMETAG;\n\n#ifdef CONFIG_USB_HCI\n\t\tpxframe->pkt = NULL;\n#ifdef USB_PACKET_OFFSET_SZ\n\t\tpxframe->pkt_offset = (PACKET_OFFSET_SZ / 8);\n#else\n\t\tpxframe->pkt_offset = 1;/* default use pkt_offset to fill tx desc */\n#endif\n\n#ifdef CONFIG_USB_TX_AGGREGATION\n\t\tpxframe->agg_num = 1;\n#endif\n\n#endif /* #ifdef CONFIG_USB_HCI */\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t\tpxframe->pg_num = 1;\n\t\tpxframe->agg_num = 1;\n#endif\n\n#ifdef CONFIG_XMIT_ACK\n\t\tpxframe->ack_report = 0;\n#endif\n\n\t}\n}\n\n/*\nCalling context:\n1. OS_TXENTRY\n2. RXENTRY (rx_thread or RX_ISR/RX_CallBack)\n\nIf we turn on USE_RXTHREAD, then, no need for critical section.\nOtherwise, we must use _enter/_exit critical to protect free_xmit_queue...\n\nMust be very very cautious...\n\n*/\nstruct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv)/* (_queue *pfree_xmit_queue) */\n{\n\t/*\n\t\tPlease remember to use all the osdep_service api,\n\t\tand lock/unlock or _enter/_exit critical to protect\n\t\tpfree_xmit_queue\n\t*/\n\n\t_irqL irqL;\n\tstruct xmit_frame *pxframe = NULL;\n\t_list *plist, *phead;\n\t_queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue;\n\n\n\t_enter_critical_bh(&pfree_xmit_queue->lock, &irqL);\n\n\tif (_rtw_queue_empty(pfree_xmit_queue) == _TRUE) {\n\t\tpxframe =  NULL;\n\t} else {\n\t\tphead = get_list_head(pfree_xmit_queue);\n\n\t\tplist = get_next(phead);\n\n\t\tpxframe = LIST_CONTAINOR(plist, struct xmit_frame, list);\n\n\t\trtw_list_delete(&(pxframe->list));\n\t\tpxmitpriv->free_xmitframe_cnt--;\n\t}\n\n\t_exit_critical_bh(&pfree_xmit_queue->lock, &irqL);\n\n\trtw_init_xmitframe(pxframe);\n\n\n\treturn pxframe;\n}\n\nstruct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv)\n{\n\t_irqL irqL;\n\tstruct xmit_frame *pxframe = NULL;\n\t_list *plist, *phead;\n\t_queue *queue = &pxmitpriv->free_xframe_ext_queue;\n\n\n\t_enter_critical_bh(&queue->lock, &irqL);\n\n\tif (_rtw_queue_empty(queue) == _TRUE) {\n\t\tpxframe =  NULL;\n\t} else {\n\t\tphead = get_list_head(queue);\n\t\tplist = get_next(phead);\n\t\tpxframe = LIST_CONTAINOR(plist, struct xmit_frame, list);\n\n\t\trtw_list_delete(&(pxframe->list));\n\t\tpxmitpriv->free_xframe_ext_cnt--;\n\t}\n\n\t_exit_critical_bh(&queue->lock, &irqL);\n\n\trtw_init_xmitframe(pxframe);\n\n\n\treturn pxframe;\n}\n\nstruct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv)\n{\n\tstruct xmit_frame *pxframe = NULL;\n\tu8 *alloc_addr;\n\n\talloc_addr = rtw_zmalloc(sizeof(struct xmit_frame) + 4);\n\n\tif (alloc_addr == NULL)\n\t\tgoto exit;\n\n\tpxframe = (struct xmit_frame *)N_BYTE_ALIGMENT((SIZE_PTR)(alloc_addr), 4);\n\tpxframe->alloc_addr = alloc_addr;\n\n\tpxframe->padapter = pxmitpriv->adapter;\n\tpxframe->frame_tag = NULL_FRAMETAG;\n\n\tpxframe->pkt = NULL;\n\n\tpxframe->buf_addr = NULL;\n\tpxframe->pxmitbuf = NULL;\n\n\trtw_init_xmitframe(pxframe);\n\n\tRTW_INFO(\"################## %s ##################\\n\", __func__);\n\nexit:\n\treturn pxframe;\n}\n\ns32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe)\n{\n\t_irqL irqL;\n\t_queue *queue = NULL;\n\t_adapter *padapter = pxmitpriv->adapter;\n\t_pkt *pndis_pkt = NULL;\n\n\n\tif (pxmitframe == NULL) {\n\t\tgoto exit;\n\t}\n\n\tif (pxmitframe->pkt) {\n\t\tpndis_pkt = pxmitframe->pkt;\n\t\tpxmitframe->pkt = NULL;\n\t}\n\n\tif (pxmitframe->alloc_addr) {\n\t\tRTW_INFO(\"################## %s with alloc_addr ##################\\n\", __func__);\n\t\trtw_mfree(pxmitframe->alloc_addr, sizeof(struct xmit_frame) + 4);\n\t\tgoto check_pkt_complete;\n\t}\n\n\tif (pxmitframe->ext_tag == 0)\n\t\tqueue = &pxmitpriv->free_xmit_queue;\n\telse if (pxmitframe->ext_tag == 1)\n\t\tqueue = &pxmitpriv->free_xframe_ext_queue;\n\telse\n\t\trtw_warn_on(1);\n\n\t_enter_critical_bh(&queue->lock, &irqL);\n\n\trtw_list_delete(&pxmitframe->list);\n\trtw_list_insert_tail(&pxmitframe->list, get_list_head(queue));\n\tif (pxmitframe->ext_tag == 0) {\n\t\tpxmitpriv->free_xmitframe_cnt++;\n\t} else if (pxmitframe->ext_tag == 1) {\n\t\tpxmitpriv->free_xframe_ext_cnt++;\n\t} else {\n\t}\n\n\t_exit_critical_bh(&queue->lock, &irqL);\n\ncheck_pkt_complete:\n\n\tif (pndis_pkt)\n\t\trtw_os_pkt_complete(padapter, pndis_pkt);\n\nexit:\n\n\n\treturn _SUCCESS;\n}\n\nvoid rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue)\n{\n\t_irqL irqL;\n\t_list\t*plist, *phead;\n\tstruct\txmit_frame\t*pxmitframe;\n\n\n\t_enter_critical_bh(&(pframequeue->lock), &irqL);\n\n\tphead = get_list_head(pframequeue);\n\tplist = get_next(phead);\n\n\twhile (rtw_end_of_queue_search(phead, plist) == _FALSE) {\n\n\t\tpxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list);\n\n\t\tplist = get_next(plist);\n\n\t\trtw_free_xmitframe(pxmitpriv, pxmitframe);\n\n\t}\n\t_exit_critical_bh(&(pframequeue->lock), &irqL);\n\n}\n\ns32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)\n{\n\tDBG_COUNTER(padapter->tx_logs.core_tx_enqueue);\n\tif (rtw_xmit_classifier(padapter, pxmitframe) == _FAIL) {\n\t\t/*\t\tpxmitframe->pkt = NULL; */\n\t\treturn _FAIL;\n\t}\n\n\treturn _SUCCESS;\n}\n\nstatic struct xmit_frame *dequeue_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, _queue *pframe_queue)\n{\n\t_list\t*xmitframe_plist, *xmitframe_phead;\n\tstruct\txmit_frame\t*pxmitframe = NULL;\n\n\txmitframe_phead = get_list_head(pframe_queue);\n\txmitframe_plist = get_next(xmitframe_phead);\n\n\twhile ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {\n\t\tpxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);\n\n\t\t/* xmitframe_plist = get_next(xmitframe_plist); */\n\n\t\t/*#ifdef RTK_DMP_PLATFORM\n\t\t#ifdef CONFIG_USB_TX_AGGREGATION\n\t\t\t\tif((ptxservq->qcnt>0) && (ptxservq->qcnt<=2))\n\t\t\t\t{\n\t\t\t\t\tpxmitframe = NULL;\n\n\t\t\t\t\ttasklet_schedule(&pxmitpriv->xmit_tasklet);\n\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t#endif\n\t\t#endif*/\n\t\trtw_list_delete(&pxmitframe->list);\n\n\t\tptxservq->qcnt--;\n\n\t\t/* rtw_list_insert_tail(&pxmitframe->list, &phwxmit->pending); */\n\n\t\t/* ptxservq->qcnt--; */\n\n\t\tbreak;\n\n\t\t/* pxmitframe = NULL; */\n\n\t}\n\n\treturn pxmitframe;\n}\n\nstatic struct xmit_frame *get_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, _queue *pframe_queue)\n{\n\t_list\t*xmitframe_plist, *xmitframe_phead;\n\tstruct\txmit_frame\t*pxmitframe = NULL;\n\n\txmitframe_phead = get_list_head(pframe_queue);\n\txmitframe_plist = get_next(xmitframe_phead);\n\n\twhile ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {\n\t\tpxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);\n\t\tbreak;\n\t}\n\n\treturn pxmitframe;\n}\n\nstruct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame)\n{\n\t_irqL irqL0;\n\t_list *sta_plist, *sta_phead;\n\tstruct hw_xmit *phwxmit_i = pxmitpriv->hwxmits;\n\tsint entry =  pxmitpriv->hwxmit_entry;\n\n\tstruct hw_xmit *phwxmit;\n\tstruct tx_servq *ptxservq = NULL;\n\t_queue *pframe_queue = NULL;\n\tstruct xmit_frame *pxmitframe = NULL;\n\t_adapter *padapter = pxmitpriv->adapter;\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\tint i, inx[4];\n\n\tinx[0] = 0;\n\tinx[1] = 1;\n\tinx[2] = 2;\n\tinx[3] = 3;\n\n\t*num_frame = 0;\n\n\t/*No amsdu when wifi_spec on*/\n\tif (pregpriv->wifi_spec == 1) {\n\t\treturn NULL;\n\t}\n\n\t_enter_critical_bh(&pxmitpriv->lock, &irqL0);\n\n\tfor (i = 0; i < entry; i++) {\n\t\tphwxmit = phwxmit_i + inx[i];\n\n\t\tsta_phead = get_list_head(phwxmit->sta_queue);\n\t\tsta_plist = get_next(sta_phead);\n\n\t\twhile ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) {\n\n\t\t\tptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending);\n\t\t\tpframe_queue = &ptxservq->sta_pending;\n\n\t\t\tif(ptxservq->qcnt)\n\t\t\t{\n\t\t\t\t*num_frame = ptxservq->qcnt;\n\t\t\t\tpxmitframe = get_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue);\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tsta_plist = get_next(sta_plist);\n\t\t}\n\t}\n\nexit:\n\n\t_exit_critical_bh(&pxmitpriv->lock, &irqL0);\n\n\treturn pxmitframe;\n}\n\n\nstruct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry)\n{\n\t_irqL irqL0;\n\t_list *sta_plist, *sta_phead;\n\tstruct hw_xmit *phwxmit;\n\tstruct tx_servq *ptxservq = NULL;\n\t_queue *pframe_queue = NULL;\n\tstruct xmit_frame *pxmitframe = NULL;\n\t_adapter *padapter = pxmitpriv->adapter;\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\tint i, inx[4];\n\n\tinx[0] = 0;\n\tinx[1] = 1;\n\tinx[2] = 2;\n\tinx[3] = 3;\n\n\tif (pregpriv->wifi_spec == 1) {\n\t\tint j;\n#if 0\n\t\tif (flags < XMIT_QUEUE_ENTRY) {\n\t\t\t/* priority exchange according to the completed xmitbuf flags. */\n\t\t\tinx[flags] = 0;\n\t\t\tinx[0] = flags;\n\t\t}\n#endif\n\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_PCI_HCI)\n\t\tfor (j = 0; j < 4; j++)\n\t\t\tinx[j] = pxmitpriv->wmm_para_seq[j];\n#endif\n\t}\n\n\t_enter_critical_bh(&pxmitpriv->lock, &irqL0);\n\n\tfor (i = 0; i < entry; i++) {\n\t\tphwxmit = phwxmit_i + inx[i];\n\n\t\t/* _enter_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */\n\n\t\tsta_phead = get_list_head(phwxmit->sta_queue);\n\t\tsta_plist = get_next(sta_phead);\n\n\t\twhile ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) {\n\n\t\t\tptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending);\n\n\t\t\tpframe_queue = &ptxservq->sta_pending;\n\n\t\t\tpxmitframe = dequeue_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue);\n\n\t\t\tif (pxmitframe) {\n\t\t\t\tphwxmit->accnt--;\n\n\t\t\t\t/* Remove sta node when there is no pending packets. */\n\t\t\t\tif (_rtw_queue_empty(pframe_queue)) /* must be done after get_next and before break */\n\t\t\t\t\trtw_list_delete(&ptxservq->tx_pending);\n\n\t\t\t\t/* _exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */\n\n\t\t\t\tgoto exit;\n\t\t\t}\n\n\t\t\tsta_plist = get_next(sta_plist);\n\n\t\t}\n\n\t\t/* _exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */\n\n\t}\n\nexit:\n\n\t_exit_critical_bh(&pxmitpriv->lock, &irqL0);\n\n\treturn pxmitframe;\n}\n\n#if 1\nstruct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac)\n{\n\tstruct tx_servq *ptxservq = NULL;\n\n\n\tswitch (up) {\n\tcase 1:\n\tcase 2:\n\t\tptxservq = &(psta->sta_xmitpriv.bk_q);\n\t\t*(ac) = 3;\n\t\tbreak;\n\n\tcase 4:\n\tcase 5:\n\t\tptxservq = &(psta->sta_xmitpriv.vi_q);\n\t\t*(ac) = 1;\n\t\tbreak;\n\n\tcase 6:\n\tcase 7:\n\t\tptxservq = &(psta->sta_xmitpriv.vo_q);\n\t\t*(ac) = 0;\n\t\tbreak;\n\n\tcase 0:\n\tcase 3:\n\tdefault:\n\t\tptxservq = &(psta->sta_xmitpriv.be_q);\n\t\t*(ac) = 2;\n\t\tbreak;\n\n\t}\n\n\n\treturn ptxservq;\n}\n#else\n__inline static struct tx_servq *rtw_get_sta_pending\n(_adapter *padapter, _queue **ppstapending, struct sta_info *psta, sint up)\n{\n\tstruct tx_servq *ptxservq;\n\tstruct hw_xmit *phwxmits =  padapter->xmitpriv.hwxmits;\n\n\n#ifdef CONFIG_RTL8711\n\n\tif (IS_MCAST(psta->cmn.mac_addr)) {\n\t\tptxservq = &(psta->sta_xmitpriv.be_q); /* we will use be_q to queue bc/mc frames in BCMC_stainfo */\n\t\t*ppstapending = &padapter->xmitpriv.bm_pending;\n\t} else\n#endif\n\t{\n\t\tswitch (up) {\n\t\tcase 1:\n\t\tcase 2:\n\t\t\tptxservq = &(psta->sta_xmitpriv.bk_q);\n\t\t\t*ppstapending = &padapter->xmitpriv.bk_pending;\n\t\t\t(phwxmits + 3)->accnt++;\n\t\t\tbreak;\n\n\t\tcase 4:\n\t\tcase 5:\n\t\t\tptxservq = &(psta->sta_xmitpriv.vi_q);\n\t\t\t*ppstapending = &padapter->xmitpriv.vi_pending;\n\t\t\t(phwxmits + 1)->accnt++;\n\t\t\tbreak;\n\n\t\tcase 6:\n\t\tcase 7:\n\t\t\tptxservq = &(psta->sta_xmitpriv.vo_q);\n\t\t\t*ppstapending = &padapter->xmitpriv.vo_pending;\n\t\t\t(phwxmits + 0)->accnt++;\n\t\t\tbreak;\n\n\t\tcase 0:\n\t\tcase 3:\n\t\tdefault:\n\t\t\tptxservq = &(psta->sta_xmitpriv.be_q);\n\t\t\t*ppstapending = &padapter->xmitpriv.be_pending;\n\t\t\t(phwxmits + 2)->accnt++;\n\t\t\tbreak;\n\n\t\t}\n\n\t}\n\n\n\treturn ptxservq;\n}\n#endif\n\n/*\n * Will enqueue pxmitframe to the proper queue,\n * and indicate it to xx_pending list.....\n */\ns32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe)\n{\n\t/* _irqL irqL0; */\n\tu8\tac_index;\n\tstruct sta_info\t*psta;\n\tstruct tx_servq\t*ptxservq;\n\tstruct pkt_attrib\t*pattrib = &pxmitframe->attrib;\n\tstruct hw_xmit\t*phwxmits =  padapter->xmitpriv.hwxmits;\n\tsint res = _SUCCESS;\n\n\n\tDBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class);\n\n\t/*\n\t\tif (pattrib->psta) {\n\t\t\tpsta = pattrib->psta;\n\t\t} else {\n\t\t\tRTW_INFO(\"%s, call rtw_get_stainfo()\\n\", __func__);\n\t\t\tpsta = rtw_get_stainfo(pstapriv, pattrib->ra);\n\t\t}\n\t*/\n\n\tpsta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);\n\tif (pattrib->psta != psta) {\n\t\tDBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_sta);\n\t\tRTW_INFO(\"%s, pattrib->psta(%p) != psta(%p)\\n\", __func__, pattrib->psta, psta);\n\t\treturn _FAIL;\n\t}\n\n\tif (psta == NULL) {\n\t\tDBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_nosta);\n\t\tres = _FAIL;\n\t\tRTW_INFO(\"rtw_xmit_classifier: psta == NULL\\n\");\n\t\tgoto exit;\n\t}\n\n\tif (!(psta->state & _FW_LINKED)) {\n\t\tDBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_fwlink);\n\t\tRTW_INFO(\"%s, psta->state(0x%x) != _FW_LINKED\\n\", __func__, psta->state);\n\t\treturn _FAIL;\n\t}\n\n\tptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index));\n\n\t/* _enter_critical(&pstapending->lock, &irqL0); */\n\n\tif (rtw_is_list_empty(&ptxservq->tx_pending))\n\t\trtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(phwxmits[ac_index].sta_queue));\n\n\t/* _enter_critical(&ptxservq->sta_pending.lock, &irqL1); */\n\n\trtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptxservq->sta_pending));\n\tptxservq->qcnt++;\n\tphwxmits[ac_index].accnt++;\n\n\t/* _exit_critical(&ptxservq->sta_pending.lock, &irqL1); */\n\n\t/* _exit_critical(&pstapending->lock, &irqL0); */\n\nexit:\n\n\n\treturn res;\n}\n\nvoid rtw_alloc_hwxmits(_adapter *padapter)\n{\n\tstruct hw_xmit *hwxmits;\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\n\tpxmitpriv->hwxmit_entry = HWXMIT_ENTRY;\n\n\tpxmitpriv->hwxmits = NULL;\n\n\tpxmitpriv->hwxmits = (struct hw_xmit *)rtw_zmalloc(sizeof(struct hw_xmit) * pxmitpriv->hwxmit_entry);\n\n\tif (pxmitpriv->hwxmits == NULL) {\n\t\tRTW_INFO(\"alloc hwxmits fail!...\\n\");\n\t\treturn;\n\t}\n\n\thwxmits = pxmitpriv->hwxmits;\n\n\tif (pxmitpriv->hwxmit_entry == 5) {\n\t\t/* pxmitpriv->bmc_txqueue.head = 0; */\n\t\t/* hwxmits[0] .phwtxqueue = &pxmitpriv->bmc_txqueue; */\n\t\thwxmits[0] .sta_queue = &pxmitpriv->bm_pending;\n\n\t\t/* pxmitpriv->vo_txqueue.head = 0; */\n\t\t/* hwxmits[1] .phwtxqueue = &pxmitpriv->vo_txqueue; */\n\t\thwxmits[1] .sta_queue = &pxmitpriv->vo_pending;\n\n\t\t/* pxmitpriv->vi_txqueue.head = 0; */\n\t\t/* hwxmits[2] .phwtxqueue = &pxmitpriv->vi_txqueue; */\n\t\thwxmits[2] .sta_queue = &pxmitpriv->vi_pending;\n\n\t\t/* pxmitpriv->bk_txqueue.head = 0; */\n\t\t/* hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; */\n\t\thwxmits[3] .sta_queue = &pxmitpriv->bk_pending;\n\n\t\t/* pxmitpriv->be_txqueue.head = 0; */\n\t\t/* hwxmits[4] .phwtxqueue = &pxmitpriv->be_txqueue; */\n\t\thwxmits[4] .sta_queue = &pxmitpriv->be_pending;\n\n\t} else if (pxmitpriv->hwxmit_entry == 4) {\n\n\t\t/* pxmitpriv->vo_txqueue.head = 0; */\n\t\t/* hwxmits[0] .phwtxqueue = &pxmitpriv->vo_txqueue; */\n\t\thwxmits[0] .sta_queue = &pxmitpriv->vo_pending;\n\n\t\t/* pxmitpriv->vi_txqueue.head = 0; */\n\t\t/* hwxmits[1] .phwtxqueue = &pxmitpriv->vi_txqueue; */\n\t\thwxmits[1] .sta_queue = &pxmitpriv->vi_pending;\n\n\t\t/* pxmitpriv->be_txqueue.head = 0; */\n\t\t/* hwxmits[2] .phwtxqueue = &pxmitpriv->be_txqueue; */\n\t\thwxmits[2] .sta_queue = &pxmitpriv->be_pending;\n\n\t\t/* pxmitpriv->bk_txqueue.head = 0; */\n\t\t/* hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; */\n\t\thwxmits[3] .sta_queue = &pxmitpriv->bk_pending;\n\t} else {\n\n\n\t}\n\n\n}\n\nvoid rtw_free_hwxmits(_adapter *padapter)\n{\n\tstruct hw_xmit *hwxmits;\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\n\thwxmits = pxmitpriv->hwxmits;\n\tif (hwxmits)\n\t\trtw_mfree((u8 *)hwxmits, (sizeof(struct hw_xmit) * pxmitpriv->hwxmit_entry));\n}\n\nvoid rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry)\n{\n\tsint i;\n\tfor (i = 0; i < entry; i++, phwxmit++) {\n\t\t/* _rtw_spinlock_init(&phwxmit->xmit_lock); */\n\t\t/* _rtw_init_listhead(&phwxmit->pending);\t\t */\n\t\t/* phwxmit->txcmdcnt = 0; */\n\t\tphwxmit->accnt = 0;\n\t}\n}\n\n#ifdef CONFIG_BR_EXT\nint rtw_br_client_tx(_adapter *padapter, struct sk_buff **pskb)\n{\n\tstruct sk_buff *skb = *pskb;\n\t_irqL irqL;\n\t/* if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) */\n\t{\n\t\tvoid dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb);\n\t\tint res, is_vlan_tag = 0, i, do_nat25 = 1;\n\t\tunsigned short vlan_hdr = 0;\n\t\tvoid *br_port = NULL;\n\n\t\t/* mac_clone_handle_frame(priv, skb); */\n\n#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))\n\t\tbr_port = padapter->pnetdev->br_port;\n#else   /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */\n\t\trcu_read_lock();\n\t\tbr_port = rcu_dereference(padapter->pnetdev->rx_handler_data);\n\t\trcu_read_unlock();\n#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */\n\t\t_enter_critical_bh(&padapter->br_ext_lock, &irqL);\n\t\tif (!(skb->data[0] & 1) &&\n\t\t    br_port &&\n\t\t    memcmp(skb->data + MACADDRLEN, padapter->br_mac, MACADDRLEN) &&\n\t\t    *((unsigned short *)(skb->data + MACADDRLEN * 2)) != __constant_htons(ETH_P_8021Q) &&\n\t\t    *((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP) &&\n\t\t    !memcmp(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN) && padapter->scdb_entry) {\n\t\t\tmemcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);\n\t\t\tpadapter->scdb_entry->ageing_timer = jiffies;\n\t\t\t_exit_critical_bh(&padapter->br_ext_lock, &irqL);\n\t\t} else\n\t\t\t/* if (!priv->pmib->ethBrExtInfo.nat25_disable)\t\t */\n\t\t{\n\t\t\t/*\t\t\tif (priv->dev->br_port &&\n\t\t\t *\t\t\t\t !memcmp(skb->data+MACADDRLEN, priv->br_mac, MACADDRLEN)) { */\n#if 1\n\t\t\tif (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_8021Q)) {\n\t\t\t\tis_vlan_tag = 1;\n\t\t\t\tvlan_hdr = *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2));\n\t\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\t\t*((unsigned short *)(skb->data + MACADDRLEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + MACADDRLEN * 2 - 2 - i * 2));\n\t\t\t\tskb_pull(skb, 4);\n\t\t\t}\n\t\t\t/* if SA == br_mac && skb== IP  => copy SIP to br_ip ?? why */\n\t\t\tif (!memcmp(skb->data + MACADDRLEN, padapter->br_mac, MACADDRLEN) &&\n\t\t\t    (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP)))\n\t\t\t\tmemcpy(padapter->br_ip, skb->data + WLAN_ETHHDR_LEN + 12, 4);\n\n\t\t\tif (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP)) {\n\t\t\t\tif (memcmp(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN)) {\n\t\t\t\t\tvoid *scdb_findEntry(_adapter *priv, unsigned char *macAddr, unsigned char *ipAddr);\n\n\t\t\t\t\tpadapter->scdb_entry = (struct nat25_network_db_entry *)scdb_findEntry(padapter,\n\t\t\t\t\t\tskb->data + MACADDRLEN, skb->data + WLAN_ETHHDR_LEN + 12);\n\t\t\t\t\tif (padapter->scdb_entry != NULL) {\n\t\t\t\t\t\tmemcpy(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN);\n\t\t\t\t\t\tmemcpy(padapter->scdb_ip, skb->data + WLAN_ETHHDR_LEN + 12, 4);\n\t\t\t\t\t\tpadapter->scdb_entry->ageing_timer = jiffies;\n\t\t\t\t\t\tdo_nat25 = 0;\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tif (padapter->scdb_entry) {\n\t\t\t\t\t\tpadapter->scdb_entry->ageing_timer = jiffies;\n\t\t\t\t\t\tdo_nat25 = 0;\n\t\t\t\t\t} else {\n\t\t\t\t\t\tmemset(padapter->scdb_mac, 0, MACADDRLEN);\n\t\t\t\t\t\tmemset(padapter->scdb_ip, 0, 4);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\t_exit_critical_bh(&padapter->br_ext_lock, &irqL);\n#endif /* 1 */\n\t\t\tif (do_nat25) {\n\t\t\t\tint nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method);\n\t\t\t\tif (nat25_db_handle(padapter, skb, NAT25_CHECK) == 0) {\n\t\t\t\t\tstruct sk_buff *newskb;\n\n\t\t\t\t\tif (is_vlan_tag) {\n\t\t\t\t\t\tskb_push(skb, 4);\n\t\t\t\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\t\t\t\t*((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2));\n\t\t\t\t\t\t*((unsigned short *)(skb->data + MACADDRLEN * 2)) = __constant_htons(ETH_P_8021Q);\n\t\t\t\t\t\t*((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)) = vlan_hdr;\n\t\t\t\t\t}\n\n\t\t\t\t\tnewskb = rtw_skb_copy(skb);\n\t\t\t\t\tif (newskb == NULL) {\n\t\t\t\t\t\t/* priv->ext_stats.tx_drops++; */\n\t\t\t\t\t\tDEBUG_ERR(\"TX DROP: rtw_skb_copy fail!\\n\");\n\t\t\t\t\t\t/* goto stop_proc; */\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\t\t\t\t\trtw_skb_free(skb);\n\n\t\t\t\t\t*pskb = skb = newskb;\n\t\t\t\t\tif (is_vlan_tag) {\n\t\t\t\t\t\tvlan_hdr = *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2));\n\t\t\t\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\t\t\t\t*((unsigned short *)(skb->data + MACADDRLEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + MACADDRLEN * 2 - 2 - i * 2));\n\t\t\t\t\t\tskb_pull(skb, 4);\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif (skb_is_nonlinear(skb))\n\t\t\t\t\tDEBUG_ERR(\"%s(): skb_is_nonlinear!!\\n\", __FUNCTION__);\n\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))\n\t\t\t\tres = skb_linearize(skb, GFP_ATOMIC);\n#else\t/* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) */\n\t\t\t\tres = skb_linearize(skb);\n#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) */\n\t\t\t\tif (res < 0) {\n\t\t\t\t\tDEBUG_ERR(\"TX DROP: skb_linearize fail!\\n\");\n\t\t\t\t\t/* goto free_and_stop; */\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\n\t\t\t\tres = nat25_db_handle(padapter, skb, NAT25_INSERT);\n\t\t\t\tif (res < 0) {\n\t\t\t\t\tif (res == -2) {\n\t\t\t\t\t\t/* priv->ext_stats.tx_drops++; */\n\t\t\t\t\t\tDEBUG_ERR(\"TX DROP: nat25_db_handle fail!\\n\");\n\t\t\t\t\t\t/* goto free_and_stop; */\n\t\t\t\t\t\treturn -1;\n\n\t\t\t\t\t}\n\t\t\t\t\t/* we just print warning message and let it go */\n\t\t\t\t\t/* DEBUG_WARN(\"%s()-%d: nat25_db_handle INSERT Warning!\\n\", __FUNCTION__, __LINE__); */\n\t\t\t\t\t/* return -1; */ /* return -1 will cause system crash on 2011/08/30! */\n\t\t\t\t\treturn 0;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tmemcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);\n\n\t\t\tdhcp_flag_bcast(padapter, skb);\n\n\t\t\tif (is_vlan_tag) {\n\t\t\t\tskb_push(skb, 4);\n\t\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\t\t*((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2));\n\t\t\t\t*((unsigned short *)(skb->data + MACADDRLEN * 2)) = __constant_htons(ETH_P_8021Q);\n\t\t\t\t*((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)) = vlan_hdr;\n\t\t\t}\n\t\t}\n#if 0\n\t\telse {\n\t\t\tif (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_8021Q))\n\t\t\t\tis_vlan_tag = 1;\n\n\t\t\tif (is_vlan_tag) {\n\t\t\t\tif (ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A_VALN(skb->data))\n\t\t\t\t\tmemcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);\n\t\t\t} else {\n\t\t\t\tif (ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A(skb->data))\n\t\t\t\t\tmemcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);\n\t\t\t}\n\t\t}\n#endif /* 0 */\n\n\t\t/* check if SA is equal to our MAC */\n\t\tif (memcmp(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN)) {\n\t\t\t/* priv->ext_stats.tx_drops++; */\n\t\t\tDEBUG_ERR(\"TX DROP: untransformed frame SA:%02X%02X%02X%02X%02X%02X!\\n\",\n\t\t\t\tskb->data[6], skb->data[7], skb->data[8], skb->data[9], skb->data[10], skb->data[11]);\n\t\t\t/* goto free_and_stop; */\n\t\t\treturn -1;\n\t\t}\n\t}\n\treturn 0;\n}\n#endif /* CONFIG_BR_EXT */\n\nu32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe)\n{\n\tu32 addr;\n\tstruct pkt_attrib *pattrib = &pxmitframe->attrib;\n\n\tswitch (pattrib->qsel) {\n\tcase 0:\n\tcase 3:\n\t\taddr = BE_QUEUE_INX;\n\t\tbreak;\n\tcase 1:\n\tcase 2:\n\t\taddr = BK_QUEUE_INX;\n\t\tbreak;\n\tcase 4:\n\tcase 5:\n\t\taddr = VI_QUEUE_INX;\n\t\tbreak;\n\tcase 6:\n\tcase 7:\n\t\taddr = VO_QUEUE_INX;\n\t\tbreak;\n\tcase 0x10:\n\t\taddr = BCN_QUEUE_INX;\n\t\tbreak;\n\tcase 0x11: /* BC/MC in PS (HIQ) */\n\t\taddr = HIGH_QUEUE_INX;\n\t\tbreak;\n\tcase 0x13:\n\t\taddr = TXCMD_QUEUE_INX;\n\t\tbreak;\n\tcase 0x12:\n\tdefault:\n\t\taddr = MGT_QUEUE_INX;\n\t\tbreak;\n\n\t}\n\n\treturn addr;\n\n}\n\nstatic void do_queue_select(_adapter\t*padapter, struct pkt_attrib *pattrib)\n{\n\tu8 qsel;\n\n\tqsel = pattrib->priority;\n\n#ifdef CONFIG_MCC_MODE\n\tif (MCC_EN(padapter)) {\n\t\t/* Under MCC */\n\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {\n\t\t\tif (padapter->mcc_adapterpriv.role == MCC_ROLE_GO\n\t\t\t    || padapter->mcc_adapterpriv.role == MCC_ROLE_AP) {\n\t\t\t\tpattrib->qsel = QSLT_VO; /* AP interface VO queue */\n\t\t\t\tpattrib->priority  = QSLT_VO;\n\t\t\t} else {\n\t\t\t\tpattrib->qsel = QSLT_BE; /* STA interface BE queue */\n\t\t\t\tpattrib->priority  = QSLT_BE;\n\t\t\t}\n\t\t} else\n\t\t\t/* Not Under MCC */\n\t\t\tpattrib->qsel = qsel;\n\t} else\n\t\t/* Not enable MCC */\n\t\tpattrib->qsel = qsel;\n#else /* !CONFIG_MCC_MODE */\n\tpattrib->qsel = qsel;\n#endif /* CONFIG_MCC_MODE */\n}\n\n/*\n * The main transmit(tx) entry\n *\n * Return\n *\t1\tenqueue\n *\t0\tsuccess, hardware will handle this xmit frame(packet)\n *\t<0\tfail\n */\n #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))\ns32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev)\n{\n\tu16 frame_ctl;\n\tstruct ieee80211_radiotap_header rtap_hdr;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct pkt_file pktfile;\n\tstruct rtw_ieee80211_hdr *pwlanhdr;\n\tstruct pkt_attrib\t*pattrib;\n\tstruct xmit_frame\t\t*pmgntframe;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct xmit_priv\t*pxmitpriv = &(padapter->xmitpriv);\n\tunsigned char\t*pframe;\n\tu8 dummybuf[32];\n\tint len = skb->len, rtap_len;\n\n\n\trtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize);\n\n#ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL\n\tif (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header)))\n\t\tgoto fail;\n\n\t_rtw_open_pktfile((_pkt *)skb, &pktfile);\n\t_rtw_pktfile_read(&pktfile, (u8 *)(&rtap_hdr), sizeof(struct ieee80211_radiotap_header));\n\trtap_len = ieee80211_get_radiotap_len((u8 *)(&rtap_hdr));\n\tif (unlikely(rtap_hdr.it_version))\n\t\tgoto fail;\n\n\tif (unlikely(skb->len < rtap_len))\n\t\tgoto fail;\n\n\tif (rtap_len != 12) {\n\t\tRTW_INFO(\"radiotap len (should be 14): %d\\n\", rtap_len);\n\t\tgoto fail;\n\t}\n\t_rtw_pktfile_read(&pktfile, dummybuf, rtap_len-sizeof(struct ieee80211_radiotap_header));\n\tlen = len - rtap_len;\n#endif\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL) {\n\t\trtw_udelay_os(500);\n\t\tgoto fail;\n\t}\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n//\t_rtw_memcpy(pframe, (void *)checking, len);\n\t_rtw_pktfile_read(&pktfile, pframe, len);\n\n\n\t/* Check DATA/MGNT frames */\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\tframe_ctl = le16_to_cpu(pwlanhdr->frame_ctl);\n\tif ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) {\n\n\t\tpattrib = &pmgntframe->attrib;\n\t\tupdate_monitor_frame_attrib(padapter, pattrib);\n\n\t\tif (is_broadcast_mac_addr(pwlanhdr->addr3) || is_broadcast_mac_addr(pwlanhdr->addr1))\n\t\t\tpattrib->rate = MGN_24M;\n\n\t} else {\n\n\t\tpattrib = &pmgntframe->attrib;\n\t\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t}\n\tpattrib->retry_ctrl = _FALSE;\n\tpattrib->pktlen = len;\n\tpmlmeext->mgnt_seq = GetSequence(pwlanhdr);\n\tpattrib->seqnum = pmlmeext->mgnt_seq;\n\tpmlmeext->mgnt_seq++;\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(padapter, pmgntframe);\n\nfail:\n\trtw_skb_free(skb);\n\treturn 0;\n}\n#endif\n\n/*\n *\n * Return _TRUE when frame has been put to queue, otherwise return _FALSE.\n */\nstatic u8 xmit_enqueue(struct _ADAPTER *a, struct xmit_frame *frame)\n{\n\tstruct sta_info *sta = NULL;\n\tstruct pkt_attrib *attrib = NULL;\n\t_irqL irqL;\n\t_list *head;\n\tu8 ret = _TRUE;\n\n\n\tattrib = &frame->attrib;\n\tsta = attrib->psta;\n\tif (!sta)\n\t\treturn _FALSE;\n\n\t_enter_critical_bh(&sta->tx_queue.lock, &irqL);\n\n\thead = get_list_head(&sta->tx_queue);\n\n\tif ((rtw_is_list_empty(head) == _TRUE) && (!sta->tx_q_enable)) {\n\t\tret = _FALSE;\n\t\tgoto exit;\n\t}\n\n\trtw_list_insert_tail(&frame->list, head);\n\tRTW_INFO(FUNC_ADPT_FMT \": en-queue tx pkt for macid=%d\\n\",\n\t\t FUNC_ADPT_ARG(a), sta->cmn.mac_id);\n\nexit:\n\t_exit_critical_bh(&sta->tx_queue.lock, &irqL);\n\n\treturn ret;\n}\n\nstatic void xmit_dequeue(struct sta_info *sta)\n{\n\tstruct _ADAPTER *a;\n\t_irqL irqL;\n\t_list *head, *list;\n\tstruct xmit_frame *frame;\n\n\n\ta = sta->padapter;\n\n\t_enter_critical_bh(&sta->tx_queue.lock, &irqL);\n\n\thead = get_list_head(&sta->tx_queue);\n\n\tdo {\n\t\tif (rtw_is_list_empty(head) == _TRUE)\n\t\t\tbreak;\n\n\t\tlist = get_next(head);\n\t\trtw_list_delete(list);\n\t\tframe = LIST_CONTAINOR(list, struct xmit_frame, list);\n\t\tRTW_INFO(FUNC_ADPT_FMT \": de-queue tx frame of macid=%d\\n\",\n\t\t\t FUNC_ADPT_ARG(a), sta->cmn.mac_id);\n\n\t\trtw_hal_xmit(a, frame);\n\t} while (1);\n\n\t_exit_critical_bh(&sta->tx_queue.lock, &irqL);\n}\n\nvoid rtw_xmit_dequeue_callback(_workitem *work)\n{\n\tstruct sta_info *sta;\n\n\n\tsta = container_of(work, struct sta_info, tx_q_work);\n\txmit_dequeue(sta);\n}\n\nvoid rtw_xmit_queue_set(struct sta_info *sta)\n{\n\t_irqL irqL;\n\n\t_enter_critical_bh(&sta->tx_queue.lock, &irqL);\n\n\tif (sta->tx_q_enable) {\n\t\tRTW_WARN(FUNC_ADPT_FMT \": duplicated set!\\n\",\n\t\t\t FUNC_ADPT_ARG(sta->padapter));\n\t\tgoto exit;\n\t}\n\tsta->tx_q_enable = 1;\n\tRTW_INFO(FUNC_ADPT_FMT \": enable queue TX for macid=%d\\n\",\n\t\t FUNC_ADPT_ARG(sta->padapter), sta->cmn.mac_id);\n\nexit:\n\t_exit_critical_bh(&sta->tx_queue.lock, &irqL);\n}\n\nvoid rtw_xmit_queue_clear(struct sta_info *sta)\n{\n\t_irqL irqL;\n\n\t_enter_critical_bh(&sta->tx_queue.lock, &irqL);\n\n\tif (!sta->tx_q_enable) {\n\t\tRTW_WARN(FUNC_ADPT_FMT \": tx queue for macid=%d \"\n\t\t\t \"not be enabled!\\n\",\n\t\t\t FUNC_ADPT_ARG(sta->padapter), sta->cmn.mac_id);\n\t\tgoto exit;\n\t}\n\n\tsta->tx_q_enable = 0;\n\tRTW_INFO(FUNC_ADPT_FMT \": disable queue TX for macid=%d\\n\",\n\t\t FUNC_ADPT_ARG(sta->padapter), sta->cmn.mac_id);\n\n\t_set_workitem(&sta->tx_q_work);\n\nexit:\n\t_exit_critical_bh(&sta->tx_queue.lock, &irqL);\n}\n\n/*\n * The main transmit(tx) entry post handle\n *\n * Return\n *\t1\tenqueue\n *\t0\tsuccess, hardware will handle this xmit frame(packet)\n *\t<0\tfail\n */\ns32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, _pkt *pkt)\n{\n#ifdef CONFIG_AP_MODE\n\t_irqL irqL0;\n#endif\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\ts32 res;\n\n\tres = update_attrib(padapter, pkt, &pxmitframe->attrib);\n\n#ifdef CONFIG_MCC_MODE\n\t/* record data kernel TX to driver to check MCC concurrent TX */\n\trtw_hal_mcc_calc_tx_bytes_from_kernel(padapter, pxmitframe->attrib.pktlen);\n#endif /* CONFIG_MCC_MODE */\n\n#ifdef CONFIG_WAPI_SUPPORT\n\tif (pxmitframe->attrib.ether_type != 0x88B4) {\n\t\tif (rtw_wapi_drop_for_key_absent(padapter, pxmitframe->attrib.ra)) {\n\t\t\tWAPI_TRACE(WAPI_RX, \"drop for key absend when tx\\n\");\n\t\t\tres = _FAIL;\n\t\t}\n\t}\n#endif\n\tif (res == _FAIL) {\n\t\t/*RTW_INFO(\"%s-\"ADPT_FMT\" update attrib fail\\n\", __func__, ADPT_ARG(padapter));*/\n#ifdef DBG_TX_DROP_FRAME\n\t\tRTW_INFO(\"DBG_TX_DROP_FRAME %s update attrib fail\\n\", __FUNCTION__);\n#endif\n\t\trtw_free_xmitframe(pxmitpriv, pxmitframe);\n\t\treturn -1;\n\t}\n\tpxmitframe->pkt = pkt;\n\n\trtw_led_tx_control(padapter, pxmitframe->attrib.dst);\n\n\tdo_queue_select(padapter, &pxmitframe->attrib);\n\n#ifdef CONFIG_AP_MODE\n\t_enter_critical_bh(&pxmitpriv->lock, &irqL0);\n\tif (xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) {\n\t\t_exit_critical_bh(&pxmitpriv->lock, &irqL0);\n\t\tDBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue);\n\t\treturn 1;\n\t}\n\t_exit_critical_bh(&pxmitpriv->lock, &irqL0);\n#endif\n\n\tif (xmit_enqueue(padapter, pxmitframe) == _TRUE)\n\t\treturn 1;\n\n\t/* pre_xmitframe */\n\tif (rtw_hal_xmit(padapter, pxmitframe) == _FALSE)\n\t\treturn 1;\n\n\treturn 0;\n}\n\n/*\n * The main transmit(tx) entry\n *\n * Return\n *\t1\tenqueue\n *\t0\tsuccess, hardware will handle this xmit frame(packet)\n *\t<0\tfail\n */\ns32 rtw_xmit(_adapter *padapter, _pkt **ppkt)\n{\n\tstatic systime start = 0;\n\tstatic u32 drop_cnt = 0;\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tstruct xmit_frame *pxmitframe = NULL;\n\ts32 res;\n\n\tDBG_COUNTER(padapter->tx_logs.core_tx);\n\n\tif (IS_CH_WAITING(adapter_to_rfctl(padapter)))\n\t\treturn -1;\n\n\tif (rtw_linked_check(padapter) == _FALSE)\n\t\treturn -1;\n\n\tif (start == 0)\n\t\tstart = rtw_get_current_time();\n\n\tpxmitframe = rtw_alloc_xmitframe(pxmitpriv);\n\n\tif (rtw_get_passing_time_ms(start) > 2000) {\n\t\tif (drop_cnt)\n\t\t\tRTW_INFO(\"DBG_TX_DROP_FRAME %s no more pxmitframe, drop_cnt:%u\\n\", __FUNCTION__, drop_cnt);\n\t\tstart = rtw_get_current_time();\n\t\tdrop_cnt = 0;\n\t}\n\n\tif (pxmitframe == NULL) {\n\t\tdrop_cnt++;\n\t\t/*RTW_INFO(\"%s-\"ADPT_FMT\" no more xmitframe\\n\", __func__, ADPT_ARG(padapter));*/\n\t\tDBG_COUNTER(padapter->tx_logs.core_tx_err_pxmitframe);\n\t\treturn -1;\n\t}\n\n#ifdef CONFIG_BR_EXT\n\tif (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) {\n\t\tvoid *br_port = NULL;\n\n\t\t#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))\n\t\tbr_port = padapter->pnetdev->br_port;\n\t\t#else\n\t\trcu_read_lock();\n\t\tbr_port = rcu_dereference(padapter->pnetdev->rx_handler_data);\n\t\trcu_read_unlock();\n\t\t#endif\n\n\t\tif (br_port) {\n\t\t\tres = rtw_br_client_tx(padapter, ppkt);\n\t\t\tif (res == -1) {\n\t\t\t\trtw_free_xmitframe(pxmitpriv, pxmitframe);\n\t\t\t\tDBG_COUNTER(padapter->tx_logs.core_tx_err_brtx);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n#endif /* CONFIG_BR_EXT */\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(padapter)) {\n\t\t_list b2u_list;\n\n\t\tres = rtw_mesh_addr_resolve(padapter, pxmitframe, *ppkt, &b2u_list);\n\t\tif (res == RTW_RA_RESOLVING)\n\t\t\treturn 1;\n\t\tif (res == _FAIL)\n\t\t\treturn -1;\n\n\t\t#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\t\tif (!rtw_is_list_empty(&b2u_list)) {\n\t\t\t_list *list = get_next(&b2u_list);\n\t\t\tstruct xmit_frame *b2uframe;\n\n\t\t\twhile ((rtw_end_of_queue_search(&b2u_list, list)) == _FALSE) {\n\t\t\t\tb2uframe = LIST_CONTAINOR(list, struct xmit_frame, list);\n\t\t\t\tlist = get_next(list);\n\t\t\t\trtw_list_delete(&b2uframe->list);\n\n\t\t\t\tb2uframe->pkt = rtw_os_pkt_copy(*ppkt);\n\t\t\t\tif (!b2uframe->pkt) {\n\t\t\t\t\tif (res == RTW_BMC_NO_NEED)\n\t\t\t\t\t\tres = _SUCCESS;\n\t\t\t\t\trtw_free_xmitframe(pxmitpriv, b2uframe);\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\trtw_xmit_posthandle(padapter, b2uframe, b2uframe->pkt);\n\t\t\t}\n\t\t}\n\t\t#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */\n\n\t\tif (res == RTW_BMC_NO_NEED) {\n\t\t\trtw_free_xmitframe(&padapter->xmitpriv, pxmitframe);\n\t\t\treturn 0;\n\t\t}\n\t}\n#endif /* CONFIG_RTW_MESH */\n\n\tpxmitframe->pkt = NULL; /* let rtw_xmit_posthandle not to free pkt inside */\n\tres = rtw_xmit_posthandle(padapter, pxmitframe, *ppkt);\n\n\treturn res;\n}\n\n#ifdef CONFIG_TDLS\nsint xmitframe_enqueue_for_tdls_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe)\n{\n\tsint ret = _FALSE;\n\n\t_irqL irqL;\n\tstruct sta_info *ptdls_sta = NULL;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct pkt_attrib *pattrib = &pxmitframe->attrib;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tint i;\n\n\tptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst);\n\tif (ptdls_sta == NULL)\n\t\treturn ret;\n\telse if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {\n\n\t\tif (pattrib->triggered == 1) {\n\t\t\tret = _TRUE;\n\t\t\treturn ret;\n\t\t}\n\n\t\t_enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);\n\n\t\tif (ptdls_sta->state & WIFI_SLEEP_STATE) {\n\t\t\trtw_list_delete(&pxmitframe->list);\n\n\t\t\t/* _enter_critical_bh(&psta->sleep_q.lock, &irqL);\t */\n\n\t\t\trtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptdls_sta->sleep_q));\n\n\t\t\tptdls_sta->sleepq_len++;\n\t\t\tptdls_sta->sleepq_ac_len++;\n\n\t\t\t/* indicate 4-AC queue bit in TDLS peer traffic indication */\n\t\t\tswitch (pattrib->priority) {\n\t\t\tcase 1:\n\t\t\tcase 2:\n\t\t\t\tptdls_sta->uapsd_bk |= BIT(1);\n\t\t\t\tbreak;\n\t\t\tcase 4:\n\t\t\tcase 5:\n\t\t\t\tptdls_sta->uapsd_vi |= BIT(1);\n\t\t\t\tbreak;\n\t\t\tcase 6:\n\t\t\tcase 7:\n\t\t\t\tptdls_sta->uapsd_vo |= BIT(1);\n\t\t\t\tbreak;\n\t\t\tcase 0:\n\t\t\tcase 3:\n\t\t\tdefault:\n\t\t\t\tptdls_sta->uapsd_be |= BIT(1);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* Transmit TDLS PTI via AP */\n\t\t\tif (ptdls_sta->sleepq_len == 1)\n\t\t\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ISSUE_PTI);\n\n\t\t\tret = _TRUE;\n\t\t}\n\n\t\t_exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);\n\t}\n\n\treturn ret;\n\n}\n#endif /* CONFIG_TDLS */\n\n#define RTW_HIQ_FILTER_ALLOW_ALL 0\n#define RTW_HIQ_FILTER_ALLOW_SPECIAL 1\n#define RTW_HIQ_FILTER_DENY_ALL 2\n\ninline bool xmitframe_hiq_filter(struct xmit_frame *xmitframe)\n{\n\tbool allow = _FALSE;\n\t_adapter *adapter = xmitframe->padapter;\n\tstruct registry_priv *registry = &adapter->registrypriv;\n\n\tif (adapter->registrypriv.wifi_spec == 1)\n\t\tallow = _TRUE;\n\telse if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_SPECIAL) {\n\n\t\tstruct pkt_attrib *attrib = &xmitframe->attrib;\n\n\t\tif (attrib->ether_type == 0x0806\n\t\t    || attrib->ether_type == 0x888e\n#ifdef CONFIG_WAPI_SUPPORT\n\t\t    || attrib->ether_type == 0x88B4\n#endif\n\t\t    || attrib->dhcp_pkt\n\t\t   ) {\n\t\t\tif (0)\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" ether_type:0x%04x%s\\n\", FUNC_ADPT_ARG(xmitframe->padapter)\n\t\t\t\t\t, attrib->ether_type, attrib->dhcp_pkt ? \" DHCP\" : \"\");\n\t\t\tallow = _TRUE;\n\t\t}\n\t} else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_ALL)\n\t\tallow = _TRUE;\n\telse if (registry->hiq_filter == RTW_HIQ_FILTER_DENY_ALL)\n\t\tallow = _FALSE;\n\telse\n\t\trtw_warn_on(1);\n\n\treturn allow;\n}\n\n#if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS)\n\nsint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe)\n{\n\t_irqL irqL;\n\tsint ret = _FALSE;\n\tstruct sta_info *psta = NULL;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct pkt_attrib *pattrib = &pxmitframe->attrib;\n\tsint bmcst = IS_MCAST(pattrib->ra);\n\tbool update_tim = _FALSE;\n#ifdef CONFIG_TDLS\n\n\tif (padapter->tdlsinfo.link_established == _TRUE)\n\t\tret = xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pxmitframe);\n#endif /* CONFIG_TDLS */\n\n\tif (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) {\n\t\tDBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_fwstate);\n\t\treturn ret;\n\t}\n\t/*\n\t\tif(pattrib->psta)\n\t\t{\n\t\t\tpsta = pattrib->psta;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tRTW_INFO(\"%s, call rtw_get_stainfo()\\n\", __func__);\n\t\t\tpsta=rtw_get_stainfo(pstapriv, pattrib->ra);\n\t\t}\n\t*/\n\tpsta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);\n\tif (pattrib->psta != psta) {\n\t\tDBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_sta);\n\t\tRTW_INFO(\"%s, pattrib->psta(%p) != psta(%p)\\n\", __func__, pattrib->psta, psta);\n\t\treturn _FALSE;\n\t}\n\n\tif (psta == NULL) {\n\t\tDBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_nosta);\n\t\tRTW_INFO(\"%s, psta==NUL\\n\", __func__);\n\t\treturn _FALSE;\n\t}\n\n\tif (!(psta->state & _FW_LINKED)) {\n\t\tDBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_link);\n\t\tRTW_INFO(\"%s, psta->state(0x%x) != _FW_LINKED\\n\", __func__, psta->state);\n\t\treturn _FALSE;\n\t}\n\n\tif (pattrib->triggered == 1) {\n\t\tDBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_trigger);\n\t\t/* RTW_INFO(\"directly xmit pspoll_triggered packet\\n\"); */\n\n\t\t/* pattrib->triggered=0; */\n\t\tif (bmcst && xmitframe_hiq_filter(pxmitframe) == _TRUE)\n\t\t\tpattrib->qsel = QSLT_HIGH;/* HIQ */\n\n\t\treturn ret;\n\t}\n\n\n\tif (bmcst) {\n\t\t_enter_critical_bh(&psta->sleep_q.lock, &irqL);\n\n\t\tif (rtw_tim_map_anyone_be_set(padapter, pstapriv->sta_dz_bitmap)) { /* if anyone sta is in ps mode */\n\t\t\t/* pattrib->qsel = QSLT_HIGH; */ /* HIQ */\n\n\t\t\trtw_list_delete(&pxmitframe->list);\n\n\t\t\t/*_enter_critical_bh(&psta->sleep_q.lock, &irqL);*/\n\n\t\t\trtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q));\n\n\t\t\tpsta->sleepq_len++;\n\n\t\t\tif (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)))\n\t\t\t\tupdate_tim = _TRUE;\n\n\t\t\trtw_tim_map_set(padapter, pstapriv->tim_bitmap, 0);\n\t\t\trtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, 0);\n\n\t\t\t/* RTW_INFO(\"enqueue, sq_len=%d\\n\", psta->sleepq_len); */\n\t\t\t/* RTW_INFO_DUMP(\"enqueue, tim=\", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */\n\t\t\tif (update_tim == _TRUE) {\n\t\t\t\tif (is_broadcast_mac_addr(pattrib->ra))\n\t\t\t\t\t_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, \"buffer BC\");\n\t\t\t\telse\n\t\t\t\t\t_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, \"buffer MC\");\n\t\t\t} else\n\t\t\t\tchk_bmc_sleepq_cmd(padapter);\n\n\t\t\t/*_exit_critical_bh(&psta->sleep_q.lock, &irqL);*/\n\n\t\t\tret = _TRUE;\n\n\t\t\tDBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_mcast);\n\t\t}\n\n\t\t_exit_critical_bh(&psta->sleep_q.lock, &irqL);\n\n\t\treturn ret;\n\n\t}\n\n\n\t_enter_critical_bh(&psta->sleep_q.lock, &irqL);\n\n\tif (psta->state & WIFI_SLEEP_STATE) {\n\t\tu8 wmmps_ac = 0;\n\n\t\tif (rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid)) {\n\t\t\trtw_list_delete(&pxmitframe->list);\n\n\t\t\t/* _enter_critical_bh(&psta->sleep_q.lock, &irqL);\t */\n\n\t\t\trtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q));\n\n\t\t\tpsta->sleepq_len++;\n\n\t\t\tswitch (pattrib->priority) {\n\t\t\tcase 1:\n\t\t\tcase 2:\n\t\t\t\twmmps_ac = psta->uapsd_bk & BIT(0);\n\t\t\t\tbreak;\n\t\t\tcase 4:\n\t\t\tcase 5:\n\t\t\t\twmmps_ac = psta->uapsd_vi & BIT(0);\n\t\t\t\tbreak;\n\t\t\tcase 6:\n\t\t\tcase 7:\n\t\t\t\twmmps_ac = psta->uapsd_vo & BIT(0);\n\t\t\t\tbreak;\n\t\t\tcase 0:\n\t\t\tcase 3:\n\t\t\tdefault:\n\t\t\t\twmmps_ac = psta->uapsd_be & BIT(0);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif (wmmps_ac)\n\t\t\t\tpsta->sleepq_ac_len++;\n\n\t\t\tif (((psta->has_legacy_ac) && (!wmmps_ac)) || ((!psta->has_legacy_ac) && (wmmps_ac))) {\n\t\t\t\tif (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)))\n\t\t\t\t\tupdate_tim = _TRUE;\n\n\t\t\t\trtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid);\n\n\t\t\t\t/* RTW_INFO(\"enqueue, sq_len=%d\\n\", psta->sleepq_len); */\n\t\t\t\t/* RTW_INFO_DUMP(\"enqueue, tim=\", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */\n\n\t\t\t\tif (update_tim == _TRUE) {\n\t\t\t\t\t/* RTW_INFO(\"sleepq_len==1, update BCNTIM\\n\"); */\n\t\t\t\t\t/* upate BCN for TIM IE */\n\t\t\t\t\t_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, \"buffer UC\");\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* _exit_critical_bh(&psta->sleep_q.lock, &irqL);\t\t\t */\n\n\t\t\t/* if(psta->sleepq_len > (NR_XMITFRAME>>3)) */\n\t\t\t/* { */\n\t\t\t/*\twakeup_sta_to_xmit(padapter, psta); */\n\t\t\t/* }\t */\n\n\t\t\tret = _TRUE;\n\n\t\t\tDBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_ucast);\n\t\t}\n\n\t}\n\n\t_exit_critical_bh(&psta->sleep_q.lock, &irqL);\n\n\treturn ret;\n\n}\n\nstatic void dequeue_xmitframes_to_sleeping_queue(_adapter *padapter, struct sta_info *psta, _queue *pframequeue)\n{\n\tsint ret;\n\t_list\t*plist, *phead;\n\tu8\tac_index;\n\tstruct tx_servq\t*ptxservq;\n\tstruct pkt_attrib\t*pattrib;\n\tstruct xmit_frame\t*pxmitframe;\n\tstruct hw_xmit *phwxmits =  padapter->xmitpriv.hwxmits;\n\n\tphead = get_list_head(pframequeue);\n\tplist = get_next(phead);\n\n\twhile (rtw_end_of_queue_search(phead, plist) == _FALSE) {\n\t\tpxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list);\n\n\t\tplist = get_next(plist);\n\n\t\tpattrib = &pxmitframe->attrib;\n\n\t\tpattrib->triggered = 0;\n\n\t\tret = xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe);\n\n\t\tif (_TRUE == ret) {\n\t\t\tptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index));\n\n\t\t\tptxservq->qcnt--;\n\t\t\tphwxmits[ac_index].accnt--;\n\t\t} else {\n\t\t\t/* RTW_INFO(\"xmitframe_enqueue_for_sleeping_sta return _FALSE\\n\"); */\n\t\t}\n\n\t}\n\n}\n\nvoid stop_sta_xmit(_adapter *padapter, struct sta_info *psta)\n{\n\t_irqL irqL0;\n\tstruct sta_info *psta_bmc;\n\tstruct sta_xmit_priv *pstaxmitpriv;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\n\tpstaxmitpriv = &psta->sta_xmitpriv;\n\n\t/* for BC/MC Frames */\n\tpsta_bmc = rtw_get_bcmc_stainfo(padapter);\n\n\n\t_enter_critical_bh(&pxmitpriv->lock, &irqL0);\n\n\tpsta->state |= WIFI_SLEEP_STATE;\n\n#ifdef CONFIG_TDLS\n\tif (!(psta->tdls_sta_state & TDLS_LINKED_STATE))\n#endif /* CONFIG_TDLS */\n\t\trtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid);\n\n\tdequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vo_q.sta_pending);\n\trtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));\n\tdequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vi_q.sta_pending);\n\trtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));\n\tdequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->be_q.sta_pending);\n\trtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));\n\tdequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->bk_q.sta_pending);\n\trtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));\n\n#ifdef CONFIG_TDLS\n\tif (!(psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta_bmc != NULL)) {\n#endif /* CONFIG_TDLS */\n\n\t\t/* for BC/MC Frames */\n\t\tpstaxmitpriv = &psta_bmc->sta_xmitpriv;\n\t\tdequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->vo_q.sta_pending);\n\t\trtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));\n\t\tdequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->vi_q.sta_pending);\n\t\trtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));\n\t\tdequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->be_q.sta_pending);\n\t\trtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));\n\t\tdequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->bk_q.sta_pending);\n\t\trtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));\n\n#ifdef CONFIG_TDLS\n\t}\n#endif /* CONFIG_TDLS\t */\n\t_exit_critical_bh(&pxmitpriv->lock, &irqL0);\n\n\n}\n\nvoid wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta)\n{\n\t_irqL irqL;\n\tu8 update_mask = 0, wmmps_ac = 0;\n\tstruct sta_info *psta_bmc;\n\t_list\t*xmitframe_plist, *xmitframe_phead;\n\tstruct xmit_frame *pxmitframe = NULL;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\n\tpsta_bmc = rtw_get_bcmc_stainfo(padapter);\n\n\n\t/* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */\n\t_enter_critical_bh(&pxmitpriv->lock, &irqL);\n\n\txmitframe_phead = get_list_head(&psta->sleep_q);\n\txmitframe_plist = get_next(xmitframe_phead);\n\n\twhile ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {\n\t\tpxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);\n\n\t\txmitframe_plist = get_next(xmitframe_plist);\n\n\t\trtw_list_delete(&pxmitframe->list);\n\n\t\tswitch (pxmitframe->attrib.priority) {\n\t\tcase 1:\n\t\tcase 2:\n\t\t\twmmps_ac = psta->uapsd_bk & BIT(1);\n\t\t\tbreak;\n\t\tcase 4:\n\t\tcase 5:\n\t\t\twmmps_ac = psta->uapsd_vi & BIT(1);\n\t\t\tbreak;\n\t\tcase 6:\n\t\tcase 7:\n\t\t\twmmps_ac = psta->uapsd_vo & BIT(1);\n\t\t\tbreak;\n\t\tcase 0:\n\t\tcase 3:\n\t\tdefault:\n\t\t\twmmps_ac = psta->uapsd_be & BIT(1);\n\t\t\tbreak;\n\t\t}\n\n\t\tpsta->sleepq_len--;\n\t\tif (psta->sleepq_len > 0)\n\t\t\tpxmitframe->attrib.mdata = 1;\n\t\telse\n\t\t\tpxmitframe->attrib.mdata = 0;\n\n\t\tif (wmmps_ac) {\n\t\t\tpsta->sleepq_ac_len--;\n\t\t\tif (psta->sleepq_ac_len > 0) {\n\t\t\t\tpxmitframe->attrib.mdata = 1;\n\t\t\t\tpxmitframe->attrib.eosp = 0;\n\t\t\t} else {\n\t\t\t\tpxmitframe->attrib.mdata = 0;\n\t\t\t\tpxmitframe->attrib.eosp = 1;\n\t\t\t}\n\t\t}\n\n\t\tpxmitframe->attrib.triggered = 1;\n\n\t\t/*\n\t\t\t\t_exit_critical_bh(&psta->sleep_q.lock, &irqL);\n\t\t\t\tif(rtw_hal_xmit(padapter, pxmitframe) == _TRUE)\n\t\t\t\t{\n\t\t\t\t\trtw_os_xmit_complete(padapter, pxmitframe);\n\t\t\t\t}\n\t\t\t\t_enter_critical_bh(&psta->sleep_q.lock, &irqL);\n\t\t*/\n\t\trtw_hal_xmitframe_enqueue(padapter, pxmitframe);\n\n\n\t}\n\n\tif (psta->sleepq_len == 0) {\n#ifdef CONFIG_TDLS\n\t\tif (psta->tdls_sta_state & TDLS_LINKED_STATE) {\n\t\t\tif (psta->state & WIFI_SLEEP_STATE)\n\t\t\t\tpsta->state ^= WIFI_SLEEP_STATE;\n\n\t\t\t_exit_critical_bh(&pxmitpriv->lock, &irqL);\n\t\t\treturn;\n\t\t}\n#endif /* CONFIG_TDLS */\n\n\t\tif (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) {\n\t\t\t/* RTW_INFO(\"wakeup to xmit, qlen==0\\n\"); */\n\t\t\t/* RTW_INFO_DUMP(\"update_BCNTIM, tim=\", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */\n\t\t\t/* upate BCN for TIM IE */\n\t\t\t/* update_BCNTIM(padapter); */\n\t\t\tupdate_mask = BIT(0);\n\t\t}\n\n\t\trtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);\n\n\t\tif (psta->state & WIFI_SLEEP_STATE)\n\t\t\tpsta->state ^= WIFI_SLEEP_STATE;\n\n\t\tif (psta->state & WIFI_STA_ALIVE_CHK_STATE) {\n\t\t\tRTW_INFO(\"%s alive check\\n\", __func__);\n\t\t\tpsta->expire_to = pstapriv->expire_to;\n\t\t\tpsta->state ^= WIFI_STA_ALIVE_CHK_STATE;\n\t\t}\n\n\t\trtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid);\n\t}\n\n\t/* for BC/MC Frames */\n\tif (!psta_bmc)\n\t\tgoto _exit;\n\n\tif (!(rtw_tim_map_anyone_be_set_exclude_aid0(padapter, pstapriv->sta_dz_bitmap))) { /* no any sta in ps mode */\n\t\txmitframe_phead = get_list_head(&psta_bmc->sleep_q);\n\t\txmitframe_plist = get_next(xmitframe_phead);\n\n\t\twhile ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {\n\t\t\tpxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);\n\n\t\t\txmitframe_plist = get_next(xmitframe_plist);\n\n\t\t\trtw_list_delete(&pxmitframe->list);\n\n\t\t\tpsta_bmc->sleepq_len--;\n\t\t\tif (psta_bmc->sleepq_len > 0)\n\t\t\t\tpxmitframe->attrib.mdata = 1;\n\t\t\telse\n\t\t\t\tpxmitframe->attrib.mdata = 0;\n\n\n\t\t\tpxmitframe->attrib.triggered = 1;\n\t\t\t/*\n\t\t\t\t\t\t_exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);\n\t\t\t\t\t\tif(rtw_hal_xmit(padapter, pxmitframe) == _TRUE)\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\trtw_os_xmit_complete(padapter, pxmitframe);\n\t\t\t\t\t\t}\n\t\t\t\t\t\t_enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL);\n\n\t\t\t*/\n\t\t\trtw_hal_xmitframe_enqueue(padapter, pxmitframe);\n\n\t\t}\n\n\t\tif (psta_bmc->sleepq_len == 0) {\n\t\t\tif (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) {\n\t\t\t\t/* RTW_INFO(\"wakeup to xmit, qlen==0\\n\"); */\n\t\t\t\t/* RTW_INFO_DUMP(\"update_BCNTIM, tim=\", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */\n\t\t\t\t/* upate BCN for TIM IE */\n\t\t\t\t/* update_BCNTIM(padapter); */\n\t\t\t\tupdate_mask |= BIT(1);\n\t\t\t}\n\t\t\trtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0);\n\t\t\trtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0);\n\t\t}\n\n\t}\n\n_exit:\n\n\t/* _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);\t */\n\t_exit_critical_bh(&pxmitpriv->lock, &irqL);\n\n\tif (update_mask) {\n\t\t/* update_BCNTIM(padapter); */\n\t\tif ((update_mask & (BIT(0) | BIT(1))) == (BIT(0) | BIT(1)))\n\t\t\t_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, \"clear UC&BMC\");\n\t\telse if ((update_mask & BIT(1)) == BIT(1))\n\t\t\t_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, \"clear BMC\");\n\t\telse\n\t\t\t_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, \"clear UC\");\n\t}\n\n}\n\nvoid xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta)\n{\n\t_irqL irqL;\n\tu8 wmmps_ac = 0;\n\t_list\t*xmitframe_plist, *xmitframe_phead;\n\tstruct xmit_frame *pxmitframe = NULL;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\n\n\t/* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */\n\t_enter_critical_bh(&pxmitpriv->lock, &irqL);\n\n\txmitframe_phead = get_list_head(&psta->sleep_q);\n\txmitframe_plist = get_next(xmitframe_phead);\n\n\twhile ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {\n\t\tpxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);\n\n\t\txmitframe_plist = get_next(xmitframe_plist);\n\n\t\tswitch (pxmitframe->attrib.priority) {\n\t\tcase 1:\n\t\tcase 2:\n\t\t\twmmps_ac = psta->uapsd_bk & BIT(1);\n\t\t\tbreak;\n\t\tcase 4:\n\t\tcase 5:\n\t\t\twmmps_ac = psta->uapsd_vi & BIT(1);\n\t\t\tbreak;\n\t\tcase 6:\n\t\tcase 7:\n\t\t\twmmps_ac = psta->uapsd_vo & BIT(1);\n\t\t\tbreak;\n\t\tcase 0:\n\t\tcase 3:\n\t\tdefault:\n\t\t\twmmps_ac = psta->uapsd_be & BIT(1);\n\t\t\tbreak;\n\t\t}\n\n\t\tif (!wmmps_ac)\n\t\t\tcontinue;\n\n\t\trtw_list_delete(&pxmitframe->list);\n\n\t\tpsta->sleepq_len--;\n\t\tpsta->sleepq_ac_len--;\n\n\t\tif (psta->sleepq_ac_len > 0) {\n\t\t\tpxmitframe->attrib.mdata = 1;\n\t\t\tpxmitframe->attrib.eosp = 0;\n\t\t} else {\n\t\t\tpxmitframe->attrib.mdata = 0;\n\t\t\tpxmitframe->attrib.eosp = 1;\n\t\t}\n\n\t\tpxmitframe->attrib.triggered = 1;\n\t\trtw_hal_xmitframe_enqueue(padapter, pxmitframe);\n\n\t\tif ((psta->sleepq_ac_len == 0) && (!psta->has_legacy_ac) && (wmmps_ac)) {\n#ifdef CONFIG_TDLS\n\t\t\tif (psta->tdls_sta_state & TDLS_LINKED_STATE) {\n\t\t\t\t/* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */\n\t\t\t\tgoto exit;\n\t\t\t}\n#endif /* CONFIG_TDLS */\n\t\t\trtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);\n\n\t\t\t/* RTW_INFO(\"wakeup to xmit, qlen==0\\n\"); */\n\t\t\t/* RTW_INFO_DUMP(\"update_BCNTIM, tim=\", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */\n\t\t\t/* upate BCN for TIM IE */\n\t\t\t/* update_BCNTIM(padapter); */\n\t\t\tupdate_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0);\n\t\t\t/* update_mask = BIT(0); */\n\t\t}\n\n\t}\n\n#ifdef CONFIG_TDLS\nexit:\n#endif\n\t/* _exit_critical_bh(&psta->sleep_q.lock, &irqL);\t */\n\t_exit_critical_bh(&pxmitpriv->lock, &irqL);\n\n\treturn;\n}\n\n#endif /* defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) */\n\n#ifdef CONFIG_XMIT_THREAD_MODE\nvoid enqueue_pending_xmitbuf(\n\tstruct xmit_priv *pxmitpriv,\n\tstruct xmit_buf *pxmitbuf)\n{\n\t_irqL irql;\n\t_queue *pqueue;\n\t_adapter *pri_adapter = pxmitpriv->adapter;\n\n\tpqueue = &pxmitpriv->pending_xmitbuf_queue;\n\n\t_enter_critical_bh(&pqueue->lock, &irql);\n\trtw_list_delete(&pxmitbuf->list);\n\trtw_list_insert_tail(&pxmitbuf->list, get_list_head(pqueue));\n\t_exit_critical_bh(&pqueue->lock, &irql);\n\n#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_CONCURRENT_MODE)\n\tpri_adapter = GET_PRIMARY_ADAPTER(pri_adapter);\n#endif /*SDIO_HCI + CONCURRENT*/\n\t_rtw_up_sema(&(pri_adapter->xmitpriv.xmit_sema));\n}\n\nvoid enqueue_pending_xmitbuf_to_head(\n\tstruct xmit_priv *pxmitpriv,\n\tstruct xmit_buf *pxmitbuf)\n{\n\t_irqL irql;\n\t_queue *pqueue = &pxmitpriv->pending_xmitbuf_queue;\n\n\t_enter_critical_bh(&pqueue->lock, &irql);\n\trtw_list_delete(&pxmitbuf->list);\n\trtw_list_insert_head(&pxmitbuf->list, get_list_head(pqueue));\n\t_exit_critical_bh(&pqueue->lock, &irql);\n}\n\nstruct xmit_buf *dequeue_pending_xmitbuf(\n\tstruct xmit_priv *pxmitpriv)\n{\n\t_irqL irql;\n\tstruct xmit_buf *pxmitbuf;\n\t_queue *pqueue;\n\n\n\tpxmitbuf = NULL;\n\tpqueue = &pxmitpriv->pending_xmitbuf_queue;\n\n\t_enter_critical_bh(&pqueue->lock, &irql);\n\n\tif (_rtw_queue_empty(pqueue) == _FALSE) {\n\t\t_list *plist, *phead;\n\n\t\tphead = get_list_head(pqueue);\n\t\tplist = get_next(phead);\n\t\tpxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);\n\t\trtw_list_delete(&pxmitbuf->list);\n\t}\n\n\t_exit_critical_bh(&pqueue->lock, &irql);\n\n\treturn pxmitbuf;\n}\n\nstatic struct xmit_buf *dequeue_pending_xmitbuf_ext(\n\tstruct xmit_priv *pxmitpriv)\n{\n\t_irqL irql;\n\tstruct xmit_buf *pxmitbuf;\n\t_queue *pqueue;\n\n\tpxmitbuf = NULL;\n\tpqueue = &pxmitpriv->pending_xmitbuf_queue;\n\n\t_enter_critical_bh(&pqueue->lock, &irql);\n\n\tif (_rtw_queue_empty(pqueue) == _FALSE) {\n\t\t_list *plist, *phead;\n\t\tu8 type = 0;\n\n\t\tphead = get_list_head(pqueue);\n\t\tplist = phead;\n\t\tdo {\n\t\t\tplist = get_next(plist);\n\t\t\tif (plist == phead)\n\t\t\t\tbreak;\n\n\t\t\tpxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);\n\n\t\t\tif (pxmitbuf->buf_tag == XMITBUF_MGNT) {\n\t\t\t\trtw_list_delete(&pxmitbuf->list);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tpxmitbuf = NULL;\n\t\t} while (1);\n\t}\n\n\t_exit_critical_bh(&pqueue->lock, &irql);\n\n\treturn pxmitbuf;\n}\n\nstruct xmit_buf *select_and_dequeue_pending_xmitbuf(_adapter *padapter)\n{\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tstruct xmit_buf *pxmitbuf = NULL;\n\n\tif (_TRUE == rtw_is_xmit_blocked(padapter))\n\t\treturn pxmitbuf;\n\n\tpxmitbuf = dequeue_pending_xmitbuf_ext(pxmitpriv);\n\tif (pxmitbuf == NULL && rtw_xmit_ac_blocked(padapter) != _TRUE)\n\t\tpxmitbuf = dequeue_pending_xmitbuf(pxmitpriv);\n\n\treturn pxmitbuf;\n}\n\nsint check_pending_xmitbuf(\n\tstruct xmit_priv *pxmitpriv)\n{\n\t_irqL irql;\n\t_queue *pqueue;\n\tsint\tret = _FALSE;\n\n\tpqueue = &pxmitpriv->pending_xmitbuf_queue;\n\n\t_enter_critical_bh(&pqueue->lock, &irql);\n\n\tif (_rtw_queue_empty(pqueue) == _FALSE)\n\t\tret = _TRUE;\n\n\t_exit_critical_bh(&pqueue->lock, &irql);\n\n\treturn ret;\n}\n\nthread_return rtw_xmit_thread(thread_context context)\n{\n\ts32 err;\n\tPADAPTER padapter;\n#ifdef RTW_XMIT_THREAD_HIGH_PRIORITY\n#ifdef PLATFORM_LINUX\n\tstruct sched_param param = { .sched_priority = 1 };\n\n\tsched_setscheduler(current, SCHED_FIFO, &param);\n#endif /* PLATFORM_LINUX */\n#endif /* RTW_XMIT_THREAD_HIGH_PRIORITY */\n\n\terr = _SUCCESS;\n\tpadapter = (PADAPTER)context;\n\n\tthread_enter(\"RTW_XMIT_THREAD\");\n\n\tdo {\n\t\terr = rtw_hal_xmit_thread_handler(padapter);\n\t\tflush_signals_thread();\n\t} while (_SUCCESS == err);\n\n\tRTW_INFO(FUNC_ADPT_FMT \" Exit\\n\", FUNC_ADPT_ARG(padapter));\n\n\trtw_thread_wait_stop();\n\n\treturn 0;\n}\n#endif\n\n#ifdef DBG_XMIT_BLOCK\nvoid dump_xmit_block(void *sel, _adapter *padapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\tRTW_PRINT_SEL(sel, \"[XMIT-BLOCK] xmit_block :0x%02x\\n\", dvobj->xmit_block);\n\tif (dvobj->xmit_block & XMIT_BLOCK_REDLMEM)\n\t\tRTW_PRINT_SEL(sel, \"Reason:%s\\n\", \"XMIT_BLOCK_REDLMEM\");\n\tif (dvobj->xmit_block & XMIT_BLOCK_SUSPEND)\n\t\tRTW_PRINT_SEL(sel, \"Reason:%s\\n\", \"XMIT_BLOCK_SUSPEND\");\n\tif (dvobj->xmit_block == XMIT_BLOCK_NONE)\n\t\tRTW_PRINT_SEL(sel, \"Reason:%s\\n\", \"XMIT_BLOCK_NONE\");\n}\nvoid dump_xmit_block_info(void *sel, const char *fun_name, _adapter *padapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\tRTW_INFO(\"\\n\"ADPT_FMT\" call %s\\n\", ADPT_ARG(padapter), fun_name);\n\tdump_xmit_block(sel, padapter);\n}\n#define DBG_XMIT_BLOCK_DUMP(adapter)\tdump_xmit_block_info(RTW_DBGDUMP, __func__, adapter)\n#endif\n\nvoid rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason)\n{\n\t_irqL irqL;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\t_enter_critical_bh(&dvobj->xmit_block_lock, &irqL);\n\tdvobj->xmit_block |= reason;\n\t_exit_critical_bh(&dvobj->xmit_block_lock, &irqL);\n\n\t#ifdef DBG_XMIT_BLOCK\n\tDBG_XMIT_BLOCK_DUMP(padapter);\n\t#endif\n}\n\nvoid rtw_clr_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason)\n{\n\t_irqL irqL;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\t_enter_critical_bh(&dvobj->xmit_block_lock, &irqL);\n\tdvobj->xmit_block &= ~reason;\n\t_exit_critical_bh(&dvobj->xmit_block_lock, &irqL);\n\n\t#ifdef DBG_XMIT_BLOCK\n\tDBG_XMIT_BLOCK_DUMP(padapter);\n\t#endif\n}\nbool rtw_is_xmit_blocked(_adapter *padapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\t#ifdef DBG_XMIT_BLOCK\n\tDBG_XMIT_BLOCK_DUMP(padapter);\n\t#endif\n\treturn ((dvobj->xmit_block) ? _TRUE : _FALSE);\n}\n\nbool rtw_xmit_ac_blocked(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\t_adapter *iface;\n\tstruct mlme_ext_priv *mlmeext;\n\tbool blocked = _FALSE;\n\tint i;\n#ifdef DBG_CONFIG_ERROR_DETECT\n#ifdef DBG_CONFIG_ERROR_RESET\n#ifdef CONFIG_USB_HCI\n\tif (rtw_hal_sreset_inprogress(adapter) == _TRUE) {\n\t\tblocked = _TRUE;\n\t\tgoto exit;\n\t}\n#endif/* #ifdef CONFIG_USB_HCI */\n#endif/* #ifdef DBG_CONFIG_ERROR_RESET */\n#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */\n\n\tif (rfctl->offch_state != OFFCHS_NONE\n\t\t#ifdef CONFIG_DFS\n\t\t|| IS_RADAR_DETECTED(rfctl) || rfctl->csa_ch\n\t\t#endif\n\t) {\n\t\tblocked = _TRUE;\n\t\tgoto exit;\n\t}\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tmlmeext = &iface->mlmeextpriv;\n\n\t\t/* check scan state */\n\t\tif (mlmeext_scan_state(mlmeext) != SCAN_DISABLE\n\t\t\t&& mlmeext_scan_state(mlmeext) != SCAN_BACK_OP\n\t\t) {\n\t\t\tblocked = _TRUE;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (mlmeext_scan_state(mlmeext) == SCAN_BACK_OP\n\t\t\t&& !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME)\n\t\t) {\n\t\t\tblocked = _TRUE;\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n#ifdef CONFIG_MCC_MODE\n\tif (MCC_EN(adapter)) {\n\t\tif (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {\n\t\t\tif (MCC_STOP(adapter)) {\n\t\t\t\tblocked = _TRUE;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\t}\n#endif /*  CONFIG_MCC_MODE */\n\nexit:\n\treturn blocked;\n}\n\n#ifdef CONFIG_TX_AMSDU\nvoid rtw_amsdu_vo_timeout_handler(void *FunctionContext)\n{\n\t_adapter *adapter = (_adapter *)FunctionContext;\n\n\tadapter->xmitpriv.amsdu_vo_timeout = RTW_AMSDU_TIMER_TIMEOUT;\n\n\ttasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);\n}\n\nvoid rtw_amsdu_vi_timeout_handler(void *FunctionContext)\n{\n\t_adapter *adapter = (_adapter *)FunctionContext;\n\n\tadapter->xmitpriv.amsdu_vi_timeout = RTW_AMSDU_TIMER_TIMEOUT;\n\n\ttasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);\n}\n\nvoid rtw_amsdu_be_timeout_handler(void *FunctionContext)\n{\n\t_adapter *adapter = (_adapter *)FunctionContext;\n\n\tadapter->xmitpriv.amsdu_be_timeout = RTW_AMSDU_TIMER_TIMEOUT;\n\n\tif (printk_ratelimit())\n\t\tRTW_DBG(\"%s Timeout!\\n\",__FUNCTION__);\n\n\ttasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);\n}\n\nvoid rtw_amsdu_bk_timeout_handler(void *FunctionContext)\n{\n\t_adapter *adapter = (_adapter *)FunctionContext;\n\n\tadapter->xmitpriv.amsdu_bk_timeout = RTW_AMSDU_TIMER_TIMEOUT;\n\n\ttasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);\n}\n\nu8 rtw_amsdu_get_timer_status(_adapter *padapter, u8 priority)\n{\n\tstruct xmit_priv        *pxmitpriv = &padapter->xmitpriv;\n\n\tu8 status =  RTW_AMSDU_TIMER_UNSET;\n\n\tswitch(priority)\n\t{\n\t\tcase 1:\n\t\tcase 2:\n\t\t\tstatus = pxmitpriv->amsdu_bk_timeout;\n\t\t\tbreak;\n\t\tcase 4:\n\t\tcase 5:\n\t\t\tstatus = pxmitpriv->amsdu_vi_timeout;\n\t\t\tbreak;\n\t\tcase 6:\n\t\tcase 7:\n\t\t\tstatus = pxmitpriv->amsdu_vo_timeout;\n\t\t\tbreak;\n\t\tcase 0:\n\t\tcase 3:\n\t\tdefault:\n\t\t\tstatus = pxmitpriv->amsdu_be_timeout;\n\t\t\tbreak;\n\t}\n\treturn status;\n}\n\nvoid rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status)\n{\n\tstruct xmit_priv        *pxmitpriv = &padapter->xmitpriv;\n\n\tswitch(priority)\n\t{\n\t\tcase 1:\n\t\tcase 2:\n\t\t\tpxmitpriv->amsdu_bk_timeout = status;\n\t\t\tbreak;\n\t\tcase 4:\n\t\tcase 5:\n\t\t\tpxmitpriv->amsdu_vi_timeout = status;\n\t\t\tbreak;\n\t\tcase 6:\n\t\tcase 7:\n\t\t\tpxmitpriv->amsdu_vo_timeout = status;\n\t\t\tbreak;\n\t\tcase 0:\n\t\tcase 3:\n\t\tdefault:\n\t\t\tpxmitpriv->amsdu_be_timeout = status;\n\t\t\tbreak;\n\t}\n}\n\nvoid rtw_amsdu_set_timer(_adapter *padapter, u8 priority)\n{\n\tstruct xmit_priv        *pxmitpriv = &padapter->xmitpriv;\n\n\t_timer* amsdu_timer = NULL;\n\n\tswitch(priority)\n\t{\n\t\tcase 1:\n\t\tcase 2:\n\t\t\tamsdu_timer = &pxmitpriv->amsdu_bk_timer;\n\t\t\tbreak;\n\t\tcase 4:\n\t\tcase 5:\n\t\t\tamsdu_timer = &pxmitpriv->amsdu_vi_timer;\n\t\t\tbreak;\n\t\tcase 6:\n\t\tcase 7:\n\t\t\tamsdu_timer = &pxmitpriv->amsdu_vo_timer;\n\t\t\tbreak;\n\t\tcase 0:\n\t\tcase 3:\n\t\tdefault:\n\t\t\tamsdu_timer = &pxmitpriv->amsdu_be_timer;\n\t\t\tbreak;\n\t}\n\t_set_timer(amsdu_timer, 1);\n}\n\nvoid rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority)\n{\n\tstruct xmit_priv        *pxmitpriv = &padapter->xmitpriv;\n\t_timer* amsdu_timer = NULL;\n\n\tswitch(priority)\n\t{\n\t\tcase 1:\n\t\tcase 2:\n\t\t\tamsdu_timer = &pxmitpriv->amsdu_bk_timer;\n\t\t\tbreak;\n\t\tcase 4:\n\t\tcase 5:\n\t\t\tamsdu_timer = &pxmitpriv->amsdu_vi_timer;\n\t\t\tbreak;\n\t\tcase 6:\n\t\tcase 7:\n\t\t\tamsdu_timer = &pxmitpriv->amsdu_vo_timer;\n\t\t\tbreak;\n\t\tcase 0:\n\t\tcase 3:\n\t\tdefault:\n\t\t\tamsdu_timer = &pxmitpriv->amsdu_be_timer;\n\t\t\tbreak;\n\t}\n\t_cancel_timer_ex(amsdu_timer);\n}\n#endif /* CONFIG_TX_AMSDU */\n\n#ifdef DBG_TXBD_DESC_DUMP\nstatic struct rtw_tx_desc_backup tx_backup[HW_QUEUE_ENTRY][TX_BAK_FRMAE_CNT];\nstatic u8 backup_idx[HW_QUEUE_ENTRY];\n\nvoid rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 desc_size, u8 hwq)\n{\n\tu32 tmp32;\n\tu8 *pxmit_buf;\n\n\tif (rtw_get_hw_init_completed(padapter) == _FALSE)\n\t\treturn;\n\n\tpxmit_buf = pxmitframe->pxmitbuf->pbuf;\n\n\t_rtw_memcpy(tx_backup[hwq][backup_idx[hwq]].tx_bak_desc, pxmit_buf, desc_size);\n\t_rtw_memcpy(tx_backup[hwq][backup_idx[hwq]].tx_bak_data_hdr, pxmit_buf+desc_size, TX_BAK_DATA_LEN);\n\n\ttmp32 = rtw_read32(padapter, get_txbd_rw_reg(hwq));\n\n\ttx_backup[hwq][backup_idx[hwq]].tx_bak_rp = (tmp32>>16)&0xfff;\n\ttx_backup[hwq][backup_idx[hwq]].tx_bak_wp = tmp32&0xfff;\n\n\ttx_backup[hwq][backup_idx[hwq]].tx_desc_size = desc_size;\n\n\tbackup_idx[hwq] = (backup_idx[hwq] + 1) % TX_BAK_FRMAE_CNT;\n}\n\nvoid rtw_tx_desc_backup_reset(void)\n{\n\tint i, j;\n\n\tfor (i = 0; i < HW_QUEUE_ENTRY; i++) {\n\t\tfor (j = 0; j < TX_BAK_FRMAE_CNT; j++)\n\t\t\t_rtw_memset(&tx_backup[i][j], 0, sizeof(struct rtw_tx_desc_backup));\n\n\t\tbackup_idx[i] = 0;\n\t}\n}\n\nu8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup **pbak)\n{\n\t*pbak = &tx_backup[hwq][0];\n\n\treturn backup_idx[hwq];\n}\n#endif\n\n#ifdef CONFIG_PCI_TX_POLLING\nvoid rtw_tx_poll_init(_adapter *padapter)\n{\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\t_timer* timer = &pxmitpriv->tx_poll_timer;\n\n\tif (!is_primary_adapter(padapter))\n\t\treturn;\n\n\tif (timer->function != NULL) {\n\t\tRTW_INFO(\"tx polling timer has been init.\\n\");\n\t\treturn;\n\t}\n\n\trtw_init_timer(timer, padapter, rtw_tx_poll_timeout_handler, padapter);\n\trtw_tx_poll_timer_set(padapter, 1);\n\tRTW_INFO(\"Tx poll timer init!\\n\");\n}\n\nvoid rtw_tx_poll_timeout_handler(void *FunctionContext)\n{\n\t_adapter *adapter = (_adapter *)FunctionContext;\n\n\trtw_tx_poll_timer_set(adapter, 1);\n\n\tif (adapter->hal_func.tx_poll_handler)\n\t\tadapter->hal_func.tx_poll_handler(adapter);\n\telse\n\t\tRTW_WARN(\"hal ops: tx_poll_handler is NULL\\n\");\n}\n\nvoid rtw_tx_poll_timer_set(_adapter *padapter, u32 delay)\n{\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\t_timer* timer = NULL;\n\n\ttimer = &pxmitpriv->tx_poll_timer;\n\t_set_timer(timer, delay);\n}\n\nvoid rtw_tx_poll_timer_cancel(_adapter *padapter)\n{\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\t_timer* timer = NULL;\n\n\tif (!is_primary_adapter(padapter))\n\t\treturn;\n\n\ttimer = &pxmitpriv->tx_poll_timer;\n\t_cancel_timer_ex(timer);\n\ttimer->function = NULL;\n\tRTW_INFO(\"Tx poll timer cancel !\\n\");\n}\n#endif /* CONFIG_PCI_TX_POLLING */\n\nvoid rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms)\n{\n\tsctx->timeout_ms = timeout_ms;\n\tsctx->submit_time = rtw_get_current_time();\n#ifdef PLATFORM_LINUX /* TODO: add condition wating interface for other os */\n\tinit_completion(&sctx->done);\n#endif\n\tsctx->status = RTW_SCTX_SUBMITTED;\n}\n\nint rtw_sctx_wait(struct submit_ctx *sctx, const char *msg)\n{\n\tint ret = _FAIL;\n\tunsigned long expire;\n\tint status = 0;\n\n#ifdef PLATFORM_LINUX\n\texpire = sctx->timeout_ms ? msecs_to_jiffies(sctx->timeout_ms) : MAX_SCHEDULE_TIMEOUT;\n\tif (!wait_for_completion_timeout(&sctx->done, expire)) {\n\t\t/* timeout, do something?? */\n\t\tstatus = RTW_SCTX_DONE_TIMEOUT;\n\t\tRTW_INFO(\"%s timeout: %s\\n\", __func__, msg);\n\t} else\n\t\tstatus = sctx->status;\n#endif\n\n\tif (status == RTW_SCTX_DONE_SUCCESS)\n\t\tret = _SUCCESS;\n\n\treturn ret;\n}\n\nbool rtw_sctx_chk_waring_status(int status)\n{\n\tswitch (status) {\n\tcase RTW_SCTX_DONE_UNKNOWN:\n\tcase RTW_SCTX_DONE_BUF_ALLOC:\n\tcase RTW_SCTX_DONE_BUF_FREE:\n\n\tcase RTW_SCTX_DONE_DRV_STOP:\n\tcase RTW_SCTX_DONE_DEV_REMOVE:\n\t\treturn _TRUE;\n\tdefault:\n\t\treturn _FALSE;\n\t}\n}\n\nvoid rtw_sctx_done_err(struct submit_ctx **sctx, int status)\n{\n\tif (*sctx) {\n\t\tif (rtw_sctx_chk_waring_status(status))\n\t\t\tRTW_INFO(\"%s status:%d\\n\", __func__, status);\n\t\t(*sctx)->status = status;\n#ifdef PLATFORM_LINUX\n\t\tcomplete(&((*sctx)->done));\n#endif\n\t\t*sctx = NULL;\n\t}\n}\n\nvoid rtw_sctx_done(struct submit_ctx **sctx)\n{\n\trtw_sctx_done_err(sctx, RTW_SCTX_DONE_SUCCESS);\n}\n\n#ifdef CONFIG_XMIT_ACK\nint rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms)\n{\n\tstruct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops;\n\n\tpack_tx_ops->submit_time = rtw_get_current_time();\n\tpack_tx_ops->timeout_ms = timeout_ms;\n\tpack_tx_ops->status = RTW_SCTX_SUBMITTED;\n\n\treturn rtw_sctx_wait(pack_tx_ops, __func__);\n}\n\nvoid rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status)\n{\n\tstruct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops;\n\n\tif (pxmitpriv->ack_tx)\n\t\trtw_sctx_done_err(&pack_tx_ops, status);\n\telse\n\t\tRTW_INFO(\"%s ack_tx not set\\n\", __func__);\n}\n#endif /* CONFIG_XMIT_ACK */\n"
  },
  {
    "path": "dkms.conf",
    "content": "PACKAGE_NAME=\"rtl88x2ce\"\nPACKAGE_VERSION=\"5.7.3_35403_20240103\"\nPROCS_NUM=$(nproc)\n[ $PROCS_NUM -gt 16 ] && PROCS_NUM=16\nMAKE=\"'make' -j${PROCS_NUM} KVER=${kernelver} KSRC=/lib/modules/${kernelver}/build USER_EXTRA_CFLAGS+=-DCONFIG_CONCURRENT_MODE\"\nCLEAN=\"make clean\"\nBUILT_MODULE_NAME[0]=\"rtl88x2ce\"\nDEST_MODULE_LOCATION[0]=\"/kernel/drivers/net/wireless/realtek/rtl88x2ce\"\nAUTOINSTALL=\"yes\"\n"
  },
  {
    "path": "hal/HalPwrSeqCmd.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n/*++\nCopyright (c) Realtek Semiconductor Corp. All rights reserved.\n\nModule Name:\n\tHalPwrSeqCmd.c\n\nAbstract:\n\tImplement HW Power sequence configuration CMD handling routine for Realtek devices.\n\nMajor Change History:\n\tWhen       Who               What\n\t---------- ---------------   -------------------------------\n\t2011-10-26 Lucas            Modify to be compatible with SD4-CE driver.\n\t2011-07-07 Roger            Create.\n\n--*/\n#include <HalPwrSeqCmd.h>\n\n\n/*\n *\tDescription:\n *\t\tThis routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.\n *\n *\tAssumption:\n *\t\tWe should follow specific format which was released from HW SD.\n *\n *\t2011.07.07, added by Roger.\n *   */\nu8 HalPwrSeqCmdParsing(\n\tPADAPTER\t\tpadapter,\n\tu8\t\t\t\tCutVersion,\n\tu8\t\t\t\tFabVersion,\n\tu8\t\t\t\tInterfaceType,\n\tWLAN_PWR_CFG\tPwrSeqCmd[])\n{\n\tWLAN_PWR_CFG\tPwrCfgCmd = {0};\n\tu8\t\t\t\tbPollingBit = _FALSE;\n\tu8\t\t\t\tbHWICSupport = _FALSE;\n\tu32\t\t\t\tAryIdx = 0;\n\tu8\t\t\t\tvalue = 0;\n\tu32\t\t\t\toffset = 0;\n\tu8\t\t\t\tflag = 0;\n\tu32\t\t\t\tpollingCount = 0; /* polling autoload done. */\n\tu32\t\t\t\tmaxPollingCnt = 5000;\n\n\tdo {\n\t\tPwrCfgCmd = PwrSeqCmd[AryIdx];\n\n\n\t\t/* 2 Only Handle the command whose FAB, CUT, and Interface are matched */\n\t\tif ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&\n\t\t    (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&\n\t\t    (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) {\n\t\t\tswitch (GET_PWR_CFG_CMD(PwrCfgCmd)) {\n\t\t\tcase PWR_CMD_READ:\n\t\t\t\tbreak;\n\n\t\t\tcase PWR_CMD_WRITE:\n\t\t\t\toffset = GET_PWR_CFG_OFFSET(PwrCfgCmd);\n\n#ifdef CONFIG_SDIO_HCI\n\t\t\t\t/*  */\n\t\t\t\t/* <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */\n\t\t\t\t/* 2011.07.07. */\n\t\t\t\t/*  */\n\t\t\t\tif (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {\n\t\t\t\t\t/* Read Back SDIO Local value */\n\t\t\t\t\tvalue = SdioLocalCmd52Read1Byte(padapter, offset);\n\n\t\t\t\t\tvalue &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));\n\t\t\t\t\tvalue |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));\n\n\t\t\t\t\t/* Write Back SDIO Local value */\n\t\t\t\t\tSdioLocalCmd52Write1Byte(padapter, offset, value);\n\t\t\t\t} else\n#endif\n\t\t\t\t{\n#ifdef CONFIG_GSPI_HCI\n\t\t\t\t\tif (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)\n\t\t\t\t\t\toffset = SPI_LOCAL_OFFSET | offset;\n#endif\n\t\t\t\t\t/* Read the value from system register */\n\t\t\t\t\tvalue = rtw_read8(padapter, offset);\n\n\t\t\t\t\tvalue = value & (~(GET_PWR_CFG_MASK(PwrCfgCmd)));\n\t\t\t\t\tvalue = value | (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));\n\n\t\t\t\t\t/* Write the value back to sytem register */\n\t\t\t\t\trtw_write8(padapter, offset, value);\n\t\t\t\t}\n\t\t\t\tbreak;\n\n\t\t\tcase PWR_CMD_POLLING:\n\n\t\t\t\tbPollingBit = _FALSE;\n\t\t\t\toffset = GET_PWR_CFG_OFFSET(PwrCfgCmd);\n\n\t\t\t\trtw_hal_get_hwreg(padapter, HW_VAR_PWR_CMD, &bHWICSupport);\n\t\t\t\tif (bHWICSupport && offset == 0x06) {\n\t\t\t\t\tflag = 0;\n\t\t\t\t\tmaxPollingCnt = 100000;\n\t\t\t\t} else\n\t\t\t\t\tmaxPollingCnt = 5000;\n\n#ifdef CONFIG_GSPI_HCI\n\t\t\t\tif (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)\n\t\t\t\t\toffset = SPI_LOCAL_OFFSET | offset;\n#endif\n\t\t\t\tdo {\n#ifdef CONFIG_SDIO_HCI\n\t\t\t\t\tif (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)\n\t\t\t\t\t\tvalue = SdioLocalCmd52Read1Byte(padapter, offset);\n\t\t\t\t\telse\n#endif\n\t\t\t\t\t\tvalue = rtw_read8(padapter, offset);\n\n\t\t\t\t\tvalue = value & GET_PWR_CFG_MASK(PwrCfgCmd);\n\t\t\t\t\tif (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))\n\t\t\t\t\t\tbPollingBit = _TRUE;\n\t\t\t\t\telse\n\t\t\t\t\t\trtw_udelay_os(10);\n\n\t\t\t\t\tif (pollingCount++ > maxPollingCnt) {\n\t\t\t\t\t\tRTW_ERR(\"HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\\n\", offset, value);\n\n\t\t\t\t\t\t/* For PCIE + USB package poll power bit timeout issue only modify 8821AE and 8723BE */\n\t\t\t\t\t\tif (bHWICSupport && offset == 0x06  && flag == 0) {\n\n\t\t\t\t\t\t\tRTW_ERR(\"[WARNING] PCIE polling(0x%X) timeout(%d), Toggle 0x04[3] and try again.\\n\", offset, maxPollingCnt);\n\t\t\t\t\t\t\tif (IS_HARDWARE_TYPE_8723DE(padapter))\n\t\t\t\t\t\t\t\tPlatformEFIOWrite1Byte(padapter, 0x40, (PlatformEFIORead1Byte(padapter, 0x40)) & (~BIT3));\n\n\t\t\t\t\t\t\tPlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) | BIT3);\n\t\t\t\t\t\t\tPlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) & ~BIT3);\n\n\t\t\t\t\t\t\tif (IS_HARDWARE_TYPE_8723DE(padapter))\n\t\t\t\t\t\t\t\tPlatformEFIOWrite1Byte(padapter, 0x40, PlatformEFIORead1Byte(padapter, 0x40)|BIT3);\n\n\t\t\t\t\t\t\t/* Retry Polling Process one more time */\n\t\t\t\t\t\t\tpollingCount = 0;\n\t\t\t\t\t\t\tflag = 1;\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\treturn _FALSE;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t} while (!bPollingBit);\n\n\t\t\t\tbreak;\n\n\t\t\tcase PWR_CMD_DELAY:\n\t\t\t\tif (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)\n\t\t\t\t\trtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));\n\t\t\t\telse\n\t\t\t\t\trtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd) * 1000);\n\t\t\t\tbreak;\n\n\t\t\tcase PWR_CMD_END:\n\t\t\t\t/* When this command is parsed, end the process */\n\t\t\t\treturn _TRUE;\n\t\t\t\tbreak;\n\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tAryIdx++;/* Add Array Index */\n\t} while (1);\n\n\treturn _TRUE;\n}\n"
  },
  {
    "path": "hal/btc/btc_basic_types.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __BTC_BASIC_TYPES_H__\n#define __BTC_BASIC_TYPES_H__\n\n#define IN\n#define OUT\n#define VOID void\ntypedef void *PVOID;\n\n#define u1Byte\t\tu8\n#define pu1Byte\t\tu8*\n\n#define u2Byte\t\tu16\n#define pu2Byte\t\tu16*\n\n#define u4Byte\t\tu32\n#define pu4Byte\t\tu32*\n\n#define u8Byte\t\tu64\n#define pu8Byte\t\tu64*\n\n#define s1Byte\t\ts8\n#define ps1Byte\t\ts8*\n\n#define s2Byte\t\ts16\n#define ps2Byte\t\ts16*\n\n#define s4Byte\t\ts32\n#define ps4Byte\t\ts32*\n\n#define s8Byte\t\ts64\n#define ps8Byte\t\ts64*\n\n#define UCHAR u8\n#define USHORT u16\n#define UINT u32\n#define ULONG u32\n#define PULONG u32*\n\n#endif /* __BTC_BASIC_TYPES_H__ */\n"
  },
  {
    "path": "hal/btc/halbtc8822c.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include \"mp_precomp.h\"\n\n#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)\n\nstatic u8 *trace_buf = &gl_btc_trace_buf[0];\n\nstatic const u32 bt_desired_ver_8822c = 0xd;\n\n/* rssi express in percentage % (dbm = % - 100)  */\nstatic const u8 wl_rssi_step_8822c[] = {60, 50, 44, 30};\nstatic const u8 bt_rssi_step_8822c[] = {8, 15, 20, 25};\n\n/* Shared-Antenna Coex Table */\nstatic const struct btc_coex_table_para table_sant_8822c[] = {\n\t\t\t\t{0xffffffff, 0xffffffff}, /*case-0*/\n\t\t\t\t{0x55555555, 0x55555555},\n\t\t\t\t{0x66555555, 0x66555555},\n\t\t\t\t{0xaaaaaaaa, 0xaaaaaaaa},\n\t\t\t\t{0x5a5a5a5a, 0x5a5a5a5a},\n\t\t\t\t{0xfafafafa, 0xfafafafa}, /*case-5*/\n\t\t\t\t{0x6a5a6a5a, 0xaaaaaaaa},\n\t\t\t\t{0x6a5a56aa, 0x6a5a56aa},\n\t\t\t\t{0x6a5a5a5a, 0x6a5a5a5a},\n\t\t\t\t{0x66555555, 0x5a5a5a5a},\n\t\t\t\t{0x66555555, 0x6a5a5a5a}, /*case-10*/\n\t\t\t\t{0x66555555, 0xfafafafa},\n\t\t\t\t{0x66555555, 0x6a5a5aaa},\n\t\t\t\t{0x66555555, 0x5aaa5aaa},\n\t\t\t\t{0x66555555, 0xaaaa5aaa},\n\t\t\t\t{0x66555555, 0xaaaaaaaa}, /*case-15*/\n\t\t\t\t{0xffff55ff, 0xfafafafa},\n\t\t\t\t{0xffff55ff, 0x6afa5afa},\n\t\t\t\t{0xaaffffaa, 0xfafafafa},\n\t\t\t\t{0xaa5555aa, 0x5a5a5a5a},\n\t\t\t\t{0xaa5555aa, 0x6a5a5a5a}, /*case-20*/\n\t\t\t\t{0xaa5555aa, 0xaaaaaaaa},\n\t\t\t\t{0xffffffff, 0x5a5a5a5a},\n\t\t\t\t{0xffffffff, 0x6a5a5a5a},\n\t\t\t\t{0xffffffff, 0x55555555},\n\t\t\t\t{0xffffffff, 0x6a5a5aaa}, /*case-25*/\n\t\t\t\t{0x55555555, 0x5a5a5a5a},\n\t\t\t\t{0x55555555, 0xaaaaaaaa},\n\t\t\t\t{0x55555555, 0x6a5a6a5a},\n\t\t\t\t{0x66556655, 0x66556655} };\n\n/* Non-Shared-Antenna Coex Table */\nstatic const struct btc_coex_table_para table_nsant_8822c[] = {\n\t\t\t\t{0xffffffff, 0xffffffff}, /*case-100*/\n\t\t\t\t{0x55555555, 0x55555555},\n\t\t\t\t{0x66555555, 0x66555555},\n\t\t\t\t{0xaaaaaaaa, 0xaaaaaaaa},\n\t\t\t\t{0x5a5a5a5a, 0x5a5a5a5a},\n\t\t\t\t{0xfafafafa, 0xfafafafa}, /*case-105*/\n\t\t\t\t{0x5afa5afa, 0x5afa5afa},\n\t\t\t\t{0x55555555, 0xfafafafa},\n\t\t\t\t{0x66555555, 0xfafafafa},\n\t\t\t\t{0x66555555, 0x5a5a5a5a},\n\t\t\t\t{0x66555555, 0x6a5a5a5a}, /*case-110*/\n\t\t\t\t{0x66555555, 0xaaaaaaaa},\n\t\t\t\t{0xffff55ff, 0xfafafafa},\n\t\t\t\t{0xffff55ff, 0x5afa5afa},\n\t\t\t\t{0xffff55ff, 0xaaaaaaaa},\n\t\t\t\t{0xaaffffaa, 0xfafafafa}, /*case-115*/\n\t\t\t\t{0xaaffffaa, 0x5afa5afa},\n\t\t\t\t{0xaaffffaa, 0xaaaaaaaa},\n\t\t\t\t{0xffffffff, 0xfafafafa},\n\t\t\t\t{0xffffffff, 0x5afa5afa},\n\t\t\t\t{0xffffffff, 0xaaaaaaaa},/*case-120*/\n\t\t\t\t{0x55ff55ff, 0x5afa5afa},\n\t\t\t\t{0x55ff55ff, 0xaaaaaaaa},\n\t\t\t\t{0x55ff55ff, 0x55ff55ff} };\n\n/* Shared-Antenna TDMA*/\nstatic const struct btc_tdma_para tdma_sant_8822c[] = {\n\t\t\t\t{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /*case-0*/\n\t\t\t\t{ {0x61, 0x45, 0x03, 0x11, 0x11} }, /*case-1*/\n\t\t\t\t{ {0x61, 0x3a, 0x03, 0x11, 0x11} },\n\t\t\t\t{ {0x61, 0x30, 0x03, 0x11, 0x11} },\n\t\t\t\t{ {0x61, 0x20, 0x03, 0x11, 0x11} },\n\t\t\t\t{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /*case-5*/\n\t\t\t\t{ {0x61, 0x45, 0x03, 0x11, 0x10} },\n\t\t\t\t{ {0x61, 0x3a, 0x03, 0x11, 0x10} },\n\t\t\t\t{ {0x61, 0x30, 0x03, 0x11, 0x10} },\n\t\t\t\t{ {0x61, 0x20, 0x03, 0x11, 0x10} },\n\t\t\t\t{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /*case-10*/\n\t\t\t\t{ {0x61, 0x08, 0x03, 0x11, 0x14} },\n\t\t\t\t{ {0x61, 0x08, 0x03, 0x10, 0x14} },\n\t\t\t\t{ {0x51, 0x08, 0x03, 0x10, 0x54} },\n\t\t\t\t{ {0x51, 0x08, 0x03, 0x10, 0x55} },\n\t\t\t\t{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /*case-15*/\n\t\t\t\t{ {0x51, 0x45, 0x03, 0x10, 0x50} },\n\t\t\t\t{ {0x51, 0x3a, 0x03, 0x10, 0x50} },\n\t\t\t\t{ {0x51, 0x30, 0x03, 0x10, 0x50} },\n\t\t\t\t{ {0x51, 0x20, 0x03, 0x10, 0x50} },\n\t\t\t\t{ {0x51, 0x10, 0x03, 0x10, 0x50} }, /*case-20*/\n\t\t\t\t{ {0x51, 0x4a, 0x03, 0x10, 0x50} },\n\t\t\t\t{ {0x51, 0x0c, 0x03, 0x10, 0x54} },\n\t\t\t\t{ {0x55, 0x08, 0x03, 0x10, 0x54} },\n\t\t\t\t{ {0x65, 0x10, 0x03, 0x11, 0x11} },\n\t\t\t\t{ {0x51, 0x10, 0x03, 0x10, 0x51} } };\n\n/* Non-Shared-Antenna TDMA*/\nstatic const struct btc_tdma_para tdma_nsant_8822c[] = {\n\t\t\t\t{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /*case-100*/\n\t\t\t\t{ {0x61, 0x45, 0x03, 0x11, 0x11} }, /*case-101*/\n\t\t\t\t{ {0x61, 0x3a, 0x03, 0x11, 0x11} },\n\t\t\t\t{ {0x61, 0x30, 0x03, 0x11, 0x11} },\n\t\t\t\t{ {0x61, 0x20, 0x03, 0x11, 0x11} },\n\t\t\t\t{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /*case-105*/\n\t\t\t\t{ {0x61, 0x45, 0x03, 0x11, 0x10} },\n\t\t\t\t{ {0x61, 0x3a, 0x03, 0x11, 0x10} },\n\t\t\t\t{ {0x61, 0x30, 0x03, 0x11, 0x10} },\n\t\t\t\t{ {0x61, 0x20, 0x03, 0x11, 0x10} },\n\t\t\t\t{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /*case-110*/\n\t\t\t\t{ {0x61, 0x08, 0x03, 0x11, 0x14} },\n\t\t\t\t{ {0x61, 0x08, 0x03, 0x10, 0x14} },\n\t\t\t\t{ {0x51, 0x08, 0x03, 0x10, 0x54} },\n\t\t\t\t{ {0x51, 0x08, 0x03, 0x10, 0x55} },\n\t\t\t\t{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /*case-115*/\n\t\t\t\t{ {0x51, 0x45, 0x03, 0x10, 0x50} },\n\t\t\t\t{ {0x51, 0x3a, 0x03, 0x10, 0x50} },\n\t\t\t\t{ {0x51, 0x30, 0x03, 0x10, 0x50} },\n\t\t\t\t{ {0x51, 0x20, 0x03, 0x10, 0x50} },\n\t\t\t\t{ {0x51, 0x10, 0x03, 0x10, 0x50} } };\n\n/* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */\nstatic const struct btc_rf_para rf_para_tx_8822c[] = {\n\t\t\t\t{0, 0, FALSE, 7},  /* for normal */\n\t\t\t\t{0, 16, FALSE, 7}, /* for WL-CPT */\n\t\t\t\t{8, 17, TRUE, 4},\n\t\t\t\t{7, 18, TRUE, 4},\n\t\t\t\t{6, 19, TRUE, 4},\n\t\t\t\t{5, 20, TRUE, 4} };\n\nstatic const struct btc_rf_para rf_para_rx_8822c[] = {\n\t\t\t\t{0, 0, FALSE, 7},  /* for normal */\n\t\t\t\t{0, 16, FALSE, 7}, /* for WL-CPT */\n\t\t\t\t{3, 24, TRUE, 5},\n\t\t\t\t{2, 26, TRUE, 5},\n\t\t\t\t{1, 27, TRUE, 5},\n\t\t\t\t{0, 28, TRUE, 5} };\n\nconst struct btc_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} };\n\nconst struct btc_chip_para btc_chip_para_8822c = {\n\t\"8822c\",\t\t\t\t/*.chip_name */\n\t20190531,\t\t\t\t/*.para_ver_date */\n\t0xe,\t\t\t\t\t/*.para_ver */\n\t0xd,\t\t\t\t\t/* bt_desired_ver */\n\tTRUE,\t\t\t\t\t/* scbd_support */\n\tTRUE,\t\t\t\t\t/* mailbox_support*/\n\tTRUE,\t\t\t\t\t/* lte_indirect_access */\n\tTRUE,\t\t\t\t\t/* new_scbd10_def */\n\tBTC_INDIRECT_1700,\t\t\t/* indirect_type */\n\tBTC_PSTDMA_FORCE_LPSOFF,\t\t/* pstdma_type */\n\tBTC_BTRSSI_DBM,\t\t\t\t/* bt_rssi_type */\n\t15,\t\t\t\t\t/*.ant_isolation */\n\t2,\t\t\t\t\t/*.rssi_tolerance */\n\t2,\t\t\t\t\t/* rx_path_num */\n\tARRAY_SIZE(wl_rssi_step_8822c),\t\t/*.wl_rssi_step_num */\n\twl_rssi_step_8822c,\t\t\t/*.wl_rssi_step */\n\tARRAY_SIZE(bt_rssi_step_8822c),\t\t/*.bt_rssi_step_num */\n\tbt_rssi_step_8822c,\t\t\t/*.bt_rssi_step */\n\tARRAY_SIZE(table_sant_8822c),\t\t/*.table_sant_num */\n\ttable_sant_8822c,\t\t\t/*.table_sant = */ \n\tARRAY_SIZE(table_nsant_8822c),\t\t/*.table_nsant_num */\n\ttable_nsant_8822c,\t\t\t/*.table_nsant = */ \n\tARRAY_SIZE(tdma_sant_8822c),\t\t/*.tdma_sant_num */\n\ttdma_sant_8822c,\t\t\t/*.tdma_sant = */\n\tARRAY_SIZE(tdma_nsant_8822c),\t\t/*.tdma_nsant_num */\n\ttdma_nsant_8822c,\t\t\t/*.tdma_nsant */\n\tARRAY_SIZE(rf_para_tx_8822c),\t\t/* wl_rf_para_tx_num */\n\trf_para_tx_8822c,\t\t        /* wl_rf_para_tx */\n\trf_para_rx_8822c,\t\t        /* wl_rf_para_rx */\n\t0x24,\t\t\t\t\t/*.bt_afh_span_bw20 */\n\t0x36,\t\t\t\t\t/*.bt_afh_span_bw40 */\n\tARRAY_SIZE(afh_5g_8822c),\t\t/*.afh_5g_num */\n\tafh_5g_8822c,\t\t\t\t/*.afh_5g */\n\thalbtc8822c_chip_setup\t\t\t/* chip_setup function */\n};\n\nvoid halbtc8822c_cfg_init(struct btc_coexist *btc)\n{\n\tu8 u8tmp = 0;\n\n\t/* enable TBTT nterrupt */\n\tbtc->btc_write_1byte_bitmask(btc, 0x550, 0x8, 0x1);\n\n\t/* BT report packet sample rate\t */\n\t/* 0x790[5:0]=0x5 */\n\tbtc->btc_write_1byte(btc, 0x790, 0x5);\n\n\t/* Enable BT counter statistics */\n\tbtc->btc_write_1byte(btc, 0x778, 0x1);\n\n\t/* Enable PTA (3-wire function form BT side) */\n\tbtc->btc_write_1byte_bitmask(btc, 0x40, 0x20, 0x1);\n\tbtc->btc_write_1byte_bitmask(btc, 0x41, 0x02, 0x1);\n\n\t/* Enable PTA (tx/rx signal form WiFi side) */\n\tbtc->btc_write_1byte_bitmask(btc, 0x4c6, BIT(4), 0x1);\n\tbtc->btc_write_1byte_bitmask(btc, 0x4c6, BIT(5), 0x0);\n\t/*GNT_BT=1 while select both */\n\tbtc->btc_write_1byte_bitmask(btc, 0x763, BIT(4), 0x1);\n\n\t/* BT_CCA = ~GNT_WL_BB, (not or GNT_BT_BB, LTE_Rx */\n\tbtc->btc_write_1byte_bitmask(btc, 0x4fc, 0x3, 0x0);\n\n\t/* To avoid RF parameter error */\n\tbtc->btc_set_rf_reg(btc, BTC_RF_B, 0x1, 0xfffff, 0x40000);\n}\n\nvoid halbtc8822c_cfg_ant_switch(struct btc_coexist *btc)\n{}\n\nvoid halbtc8822c_cfg_gnt_fix(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\tu32 val = 0x40000;\n\n\t/* Because WL-S1 5G RF TRX mask affect by GNT_BT\n\t * Set debug mode on: GNT_BT=0, GNT_WL=1, BT at BTG\n\t */\n\tif (coex_sta->kt_ver == 0 &&\n\t    coex_sta->wl_coex_mode == BTC_WLINK_5G)\n\t\tval = 0x40021;\n\telse if (coex_sta->coex_freerun) /* WL S1 force to GNT_WL=1, GNT_BT=0 */\n\t\tval = 0x40021;\n\telse\n\t\tval = 0x40000;\n\n\tif (btc->board_info.btdm_ant_num == 1) /* BT at S1 for 2-Ant */\n\t\tval = val | BIT(13);\n\n\tbtc->btc_set_rf_reg(btc, BTC_RF_B, 0x1, 0xfffff, val);\n\n\t/* Because WL-S0 2G RF TRX can't masked by GNT_BT\n\t * enable \"WLS0 BB chage RF mode if GNT_BT = 1\" for shared-antenna type\n\t * disable:0x1860[3] = 1, enable:0x1860[3] = 0\n\t *\n\t * enable \"AFE DAC off if GNT_WL = 0\"\n\t * disable 0x1c30[22] = 0,\n\t * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1\n\t */\n\tbtc->btc_write_1byte_bitmask(btc, 0x1c32, BIT(6), 1);\n\tbtc->btc_write_1byte_bitmask(btc, 0x1c39, BIT(4), 0);\n\tbtc->btc_write_1byte_bitmask(btc, 0x1c3b, BIT(4), 1);\n\n\t/* disable WLS1 BB chage RF mode if GNT_BT\n\t * since RF TRx mask can do it\n\t */\n\tbtc->btc_write_1byte_bitmask(btc, 0x4160, BIT(3), 1);\n\n\t/* for kt_ver >= 3: 0x1860[3] = 0\n\t * always set \"WLS0 BB chage RF mode if GNT_WL = 0\"\n\t * But the BB DAC will be turned off by GNT_BT = 1\n\t * 0x1ca7[3] = 1, \"don't off BB DAC if GNT_BT = 1\"\n\t */\n\n\tif (coex_sta->wl_coex_mode == BTC_WLINK_5G ||\n\t    link_info_ext->is_all_under_5g) {\n\t\tif (coex_sta->kt_ver >= 3) {\n\t\t\tbtc->btc_write_1byte_bitmask(btc, 0x1860, BIT(3), 0);\n\t\t\tbtc->btc_write_1byte_bitmask(btc, 0x1ca7, BIT(3), 1);\n\t\t} else {\n\t\t\tbtc->btc_write_1byte_bitmask(btc, 0x1860, BIT(3), 1);\n\t\t}\n\t} else if (btc->board_info.btdm_ant_num == 2 ||\n\t\t   coex_sta->wl_coex_mode == BTC_WLINK_25GMPORT) {\n\t\t/* non-shared-antenna or MCC-2band */\n\t\tif (coex_sta->kt_ver >= 3) {\n\t\t\tbtc->btc_write_1byte_bitmask(btc, 0x1860, BIT(3), 0);\n\t\t\tbtc->btc_write_1byte_bitmask(btc, 0x1ca7, BIT(3), 1);\n\t\t} else {\n\t\t\tbtc->btc_write_1byte_bitmask(btc, 0x1860, BIT(3), 1);\n\t\t}\n\t} else { /* shared-antenna */\n\t\tbtc->btc_write_1byte_bitmask(btc, 0x1860, BIT(3), 0);\n\t\tif (coex_sta->kt_ver >= 3)\n\t\t\tbtc->btc_write_1byte_bitmask(btc, 0x1ca7, BIT(3), 0);\n\t}\n}\n\nvoid halbtc8822c_cfg_gnt_debug(struct btc_coexist *btc)\n{\n\tbtc->btc_write_1byte_bitmask(btc, 0x66, BIT(4), 0);\n\tbtc->btc_write_1byte_bitmask(btc, 0x67, BIT(0), 0);\n\tbtc->btc_write_1byte_bitmask(btc, 0x42, BIT(3), 0);\n\tbtc->btc_write_1byte_bitmask(btc, 0x65, BIT(7), 0);\n\tbtc->btc_write_1byte_bitmask(btc, 0x73, BIT(3), 0);\n}\n\nvoid halbtc8822c_cfg_rfe_type(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_rfe_type *rfe_type = &btc->rfe_type;\n\tstruct btc_board_info *board_info = &btc->board_info;\n\n\trfe_type->rfe_module_type = board_info->rfe_type;\n\trfe_type->ant_switch_polarity = 0;\n\trfe_type->ant_switch_exist = FALSE;\n\trfe_type->ant_switch_with_bt = FALSE;\n\trfe_type->ant_switch_type = BTC_SWITCH_NONE;\n\trfe_type->ant_switch_diversity = FALSE;\n\n\trfe_type->band_switch_exist = FALSE;\n\trfe_type->band_switch_type = 0;\n\trfe_type->band_switch_polarity = 0;\n\n\tif (btc->board_info.btdm_ant_num == 1)\n\t\trfe_type->wlg_at_btg = TRUE;\n\telse\n\t\trfe_type->wlg_at_btg = FALSE;\n\n\tcoex_sta->rf4ce_en = FALSE;\n\n\t/* Disable LTE Coex Function in WiFi side */\n\tbtc->btc_write_linderct(btc, 0x38, BIT(7), 0);\n\n\t/* BTC_CTT_WL_VS_LTE  */\n\tbtc->btc_write_linderct(btc, 0xa0, 0xffff, 0xffff);\n\n\t/*  BTC_CTT_BT_VS_LTE */\n\tbtc->btc_write_linderct(btc, 0xa4, 0xffff, 0xffff);\n}\n\nvoid halbtc8822c_cfg_coexinfo_hw(struct btc_coexist *btc)\n{\n\tu8 *cli_buf = btc->cli_buf, u8tmp[4];\n\tu16 u16tmp[4];\n\tu32 u32tmp[4];\n\tboolean lte_coex_on = FALSE;\n\n\tu32tmp[0] = btc->btc_read_linderct(btc, 0x38);\n\tu32tmp[1] = btc->btc_read_linderct(btc, 0x54);\n\tu8tmp[0] = btc->btc_read_1byte(btc, 0x73);\n\tlte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? TRUE : FALSE;\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %s\",\n\t\t   \"LTE Coex/Path Owner\", ((lte_coex_on) ? \"On\" : \"Off\"),\n\t\t   ((u8tmp[0] & BIT(2)) ? \"WL\" : \"BT\"));\n\tCL_PRINTF(cli_buf);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t   \"\\r\\n %-35s = RF:%s_BB:%s/ RF:%s_BB:%s/ %s\",\n\t\t   \"GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg\",\n\t\t   ((u32tmp[0] & BIT(12)) ? \"SW\" : \"HW\"),\n\t\t   ((u32tmp[0] & BIT(8)) ? \"SW\" : \"HW\"),\n\t\t   ((u32tmp[0] & BIT(14)) ? \"SW\" : \"HW\"),\n\t\t   ((u32tmp[0] & BIT(10)) ? \"SW\" : \"HW\"),\n\t\t   ((u8tmp[0] & BIT(3)) ? \"On\" : \"Off\"));\n\tCL_PRINTF(cli_buf);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d\",\n\t\t   \"GNT_WL/GNT_BT\", (int)((u32tmp[1] & BIT(2)) >> 2),\n\t\t   (int)((u32tmp[1] & BIT(3)) >> 3));\n\tCL_PRINTF(cli_buf);\n\n\tu32tmp[0] = btc->btc_read_4byte(btc, 0x1c38);\n\tu8tmp[0] = btc->btc_read_1byte(btc, 0x1860);\n\tu8tmp[1] = btc->btc_read_1byte(btc, 0x4160);\n\tu8tmp[2] = btc->btc_read_1byte(btc, 0x1c32);\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t   \"\\r\\n %-35s = %d/ %d/ %d/ %d\",\n\t\t   \"1860[3]/4160[3]/1c30[22]/1c38[28]\",\n\t\t   (int)((u8tmp[0] & BIT(3)) >> 3),\n\t\t   (int)((u8tmp[1] & BIT(3)) >> 3),\n\t\t   (int)((u8tmp[2] & BIT(6)) >> 6),\n\t\t   (int)((u32tmp[0] & BIT(28)) >> 28));\n\tCL_PRINTF(cli_buf);\n\n\tu32tmp[0] = btc->btc_read_4byte(btc, 0x430);\n\tu32tmp[1] = btc->btc_read_4byte(btc, 0x434);\n\tu16tmp[0] = btc->btc_read_2byte(btc, 0x42a);\n\tu8tmp[0] = btc->btc_read_1byte(btc, 0x426);\n\tu8tmp[1] = btc->btc_read_1byte(btc, 0x45e);\n\tu8tmp[2] = btc->btc_read_1byte(btc, 0x455);\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t   \"\\r\\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x/ 0x%x/ 0x%x\",\n\t\t   \"430/434/42a/426/45e[3]/455\",\n\t\t   u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0],\n\t\t   (int)((u8tmp[1] & BIT(3)) >> 3), u8tmp[2]);\n\tCL_PRINTF(cli_buf);\n\n\tu32tmp[0] = btc->btc_read_4byte(btc, 0x4c);\n\tu8tmp[2] = btc->btc_read_1byte(btc, 0x64);\n\tu8tmp[0] = btc->btc_read_1byte(btc, 0x4c6);\n\tu8tmp[1] = btc->btc_read_1byte(btc, 0x40);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t   \"\\r\\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x/ 0x%x\",\n\t\t   \"4c[24:23]/64[0]/4c6[4]/40[5]/RF_0x1\",\n\t\t   (int)(u32tmp[0] & (BIT(24) | BIT(23))) >> 23, u8tmp[2] & 0x1,\n\t\t   (int)((u8tmp[0] & BIT(4)) >> 4),\n\t\t   (int)((u8tmp[1] & BIT(5)) >> 5),\n\t\t   (int)(btc->btc_get_rf_reg(btc, BTC_RF_B, 0x1, 0xfffff)));\n\tCL_PRINTF(cli_buf);\n\n\tu32tmp[0] = btc->btc_read_4byte(btc, 0x550);\n\tu8tmp[0] = btc->btc_read_1byte(btc, 0x522);\n\tu8tmp[1] = btc->btc_read_1byte(btc, 0x953);\n\tu8tmp[2] = btc->btc_read_1byte(btc, 0xc50);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t   \"\\r\\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x\",\n\t\t   \"550/522/4-RxAGC/c50\", u32tmp[0], u8tmp[0],\n\t\t   (u8tmp[1] & 0x2) ? \"On\" : \"Off\", u8tmp[2]);\n\tCL_PRINTF(cli_buf);\n\n\tu8tmp[0] = btc->btc_read_1byte(btc, 0xf8e);\n\tu8tmp[1] = btc->btc_read_1byte(btc, 0xf8f);\n\tu8tmp[2] = btc->btc_read_1byte(btc, 0xd14);\n\tu8tmp[3] = btc->btc_read_1byte(btc, 0xd54);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d/ %d/ %d\",\n\t\t   \"EVM_A/ EVM_B/ SNR_A/ SNR_B\",\n\t\t   (u8tmp[0] > 127 ? u8tmp[0] - 256 : u8tmp[0]),\n\t\t   (u8tmp[1] > 127 ? u8tmp[1] - 256 : u8tmp[1]),\n\t\t   (u8tmp[2] > 127 ? u8tmp[2] - 256 : u8tmp[2]),\n\t\t   (u8tmp[3] > 127 ? u8tmp[3] - 256 : u8tmp[3]));\n\tCL_PRINTF(cli_buf);\n}\n\nvoid halbtc8822c_cfg_wl_tx_power(struct btc_coexist *btc)\n{\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\n\tbtc->btc_reduce_wl_tx_power(btc, coex_dm->cur_wl_pwr_lvl);\n}\n\nvoid halbtc8822c_cfg_wl_rx_gain(struct btc_coexist *btc)\n{\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\tu8 i;\n\n\t/* WL Rx Low gain on  */\n\tstatic const u32\twl_rx_gain_on_HT20[] = {0x00000000};\n\tstatic const u32\twl_rx_gain_on_HT40[] = {0x00000000};\n\n\t/* WL Rx Low gain off  */\n\tstatic const u32\twl_rx_gain_off_HT20[] = {0x00000000};\n\tstatic const u32\twl_rx_gain_off_HT40[] = {0x00000000};\n\n\tu32\t\t*wl_rx_gain_on, *wl_rx_gain_off;\n\n\tif (coex_dm->cur_wl_rx_low_gain_en) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], Hi-Li Table On!\\n\");\n\t\tBTC_TRACE(trace_buf);\n#if 0\n\t\tif (link_info_ext->wifi_bw == BTC_WIFI_BW_HT40)\n\t\t\twl_rx_gain_on = wl_rx_gain_on_HT40;\n\t\telse\n\t\t\twl_rx_gain_on = wl_rx_gain_on_HT20;\n\t\tfor (i = 0; i < ARRAY_SIZE(wl_rx_gain_on); i++)\n\t\t\tbtc->btc_write_4byte(btc, 0x1d90, wl_rx_gain_on[i]);\n#endif\n\n\t\t/* set Rx filter corner RCK offset */\n\t\tbtc->btc_set_rf_reg(btc, BTC_RF_A, 0xde, 0xfffff, 0x22);\n\t\tbtc->btc_set_rf_reg(btc, BTC_RF_A, 0x1d, 0xfffff, 0x36);\n\t\tbtc->btc_set_rf_reg(btc, BTC_RF_B, 0xde, 0xfffff, 0x22);\n\t\tbtc->btc_set_rf_reg(btc, BTC_RF_B, 0x1d, 0xfffff, 0x36);\n\t} else {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], Hi-Li Table Off!\\n\");\n\t\tBTC_TRACE(trace_buf);\n\n#if 0\n\t\tif (link_info_ext->wifi_bw == BTC_WIFI_BW_HT40)\n\t\t\twl_rx_gain_off = wl_rx_gain_off_HT40;\n\t\telse\n\t\t\twl_rx_gain_off = wl_rx_gain_off_HT20;\n\t\tfor (i = 0; i < ARRAY_SIZE(wl_rx_gain_off); i++)\n\t\t\tbtc->btc_write_4byte(btc, 0x1d90, wl_rx_gain_off[i]);\n#endif\n\n\t\t/* set Rx filter corner RCK offset */\n\t\tbtc->btc_set_rf_reg(btc, BTC_RF_A, 0xde, 0xfffff, 0x20);\n\t\tbtc->btc_set_rf_reg(btc, BTC_RF_A, 0x1d, 0xfffff, 0x0);\n\t\tbtc->btc_set_rf_reg(btc, BTC_RF_B, 0xde, 0xfffff, 0x20);\n\t\tbtc->btc_set_rf_reg(btc, BTC_RF_B, 0x1d, 0xfffff, 0x0);\n\t}\n}\n\nvoid halbtc8822c_cfg_wlan_act_ips(struct btc_coexist *btc)\n{}\n\nvoid halbtc8822c_chip_setup(struct btc_coexist *btc, u8 type)\n{\n\tswitch (type) {\n\tcase BTC_CSETUP_INIT_HW:\n\t\thalbtc8822c_cfg_init(btc);\n\t\tbreak;\n\tcase BTC_CSETUP_ANT_SWITCH:\n\t\thalbtc8822c_cfg_ant_switch(btc);\n\t\tbreak;\n\tcase BTC_CSETUP_GNT_FIX:\n\t\thalbtc8822c_cfg_gnt_fix(btc);\n\t\tbreak;\n\tcase BTC_CSETUP_GNT_DEBUG:\n\t\thalbtc8822c_cfg_gnt_debug(btc);\n\t\tbreak;\n\tcase BTC_CSETUP_RFE_TYPE:\n\t\thalbtc8822c_cfg_rfe_type(btc);\n\t\tbreak;\n\tcase BTC_CSETUP_COEXINFO_HW:\n\t\thalbtc8822c_cfg_coexinfo_hw(btc);\n\t\tbreak;\n\tcase BTC_CSETUP_WL_TX_POWER:\n\t\thalbtc8822c_cfg_wl_tx_power(btc);\n\t\tbreak;\n\tcase BTC_CSETUP_WL_RX_GAIN:\n\t\thalbtc8822c_cfg_wl_rx_gain(btc);\n\t\tbreak;\n\tcase BTC_CSETUP_WLAN_ACT_IPS:\n\t\thalbtc8822c_cfg_wlan_act_ips(btc);\n\t\tbreak;\n\t}\n}\n#endif\n"
  },
  {
    "path": "hal/btc/halbtc8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\nextern const struct btc_chip_para btc_chip_para_8822c;\nvoid halbtc8822c_chip_setup(struct btc_coexist *btc, u8 type);\nvoid halbtc8822c_cfg_init(struct btc_coexist *btc);\nvoid halbtc8822c_cfg_ant_switch(struct btc_coexist *btc);\nvoid halbtc8822c_cfg_gnt_debug(struct btc_coexist *btc);\nvoid halbtc8822c_cfg_fre_type(struct btc_coexist *btc);\nvoid halbtc8822c_cfg_coexinfo_hw(struct btc_coexist *btc);\nvoid halbtc8822c_cfg_wl_tx_power(struct btc_coexist *btc);\nvoid halbtc8822c_cfg_wl_rx_gain(struct btc_coexist *btc);\nvoid halbtc8822c_cfg_wlan_act_ips(struct btc_coexist *btc);\n\n\n"
  },
  {
    "path": "hal/btc/halbtc8822cwifionly.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#include \"mp_precomp.h\"\n\n\nVOID\nex_hal8822c_wifi_only_hw_config(\n\tIN struct wifi_only_cfg *pwifionlycfg\n\t)\n{\n\thalwifionly_phy_set_bb_reg(pwifionlycfg, 0x70, 0xff000000, 0x0e);\n\t/*gnt_wl=1 , gnt_bt=0*/\n\thalwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff, 0x7700);\n\thalwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff, 0xc00f0038);\n\n\thalwifionly_phy_set_bb_reg(pwifionlycfg, 0x6c0, 0xffffffff, 0xaaaaaaaa);\n\thalwifionly_phy_set_bb_reg(pwifionlycfg, 0x6c4, 0xffffffff, 0xaaaaaaaa);\n}\n\nVOID\nex_hal8822c_wifi_only_scannotify(\n\tIN struct wifi_only_cfg *pwifionlycfg,\n\tIN u1Byte  is_5g\n\t)\n{\n}\n\nVOID\nex_hal8822c_wifi_only_switchbandnotify(\n\tIN struct wifi_only_cfg *pwifionlycfg,\n\tIN u1Byte  is_5g\n\t)\n{\n}\n\nVOID\nex_hal8822c_wifi_only_connectnotify(\n\tIN struct wifi_only_cfg *pwifionlycfg,\n\tIN u1Byte  is_5g\n\t)\n{\n}\n\n\nVOID\nhal8822c_wifi_only_switch_antenna(\n\tIN struct wifi_only_cfg *pwifionlycfg,\n\tIN u1Byte  is_5g\n\t)\n{\n}\n"
  },
  {
    "path": "hal/btc/halbtc8822cwifionly.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8822CWIFIONLYHWCFG_H\n#define __INC_HAL8822CWIFIONLYHWCFG_H\n\nVOID\nex_hal8822c_wifi_only_hw_config(\n\tIN struct wifi_only_cfg *pwifionlycfg\n\t);\nVOID\nex_hal8822c_wifi_only_scannotify(\n\tIN struct wifi_only_cfg *pwifionlycfg,\n\tIN u1Byte  is_5g\n\t);\nVOID\nex_hal8822c_wifi_only_switchbandnotify(\n\tIN struct wifi_only_cfg *pwifionlycfg,\n\tIN u1Byte  is_5g\n\t);\nVOID\nex_hal8822c_wifi_only_connectnotify(\n\tIN struct wifi_only_cfg *pwifionlycfg,\n\tIN u1Byte  is_5g\n\t);\nVOID\nhal8822c_wifi_only_switch_antenna(\n\tIN struct wifi_only_cfg *pwifionlycfg,\n\tIN u1Byte  is_5g\n\t);\n#endif\n"
  },
  {
    "path": "hal/btc/halbtccommon.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include \"mp_precomp.h\"\n\n#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)\n\nstatic u8 *trace_buf = &gl_btc_trace_buf[0];\nstatic const u32 coex_ver_date = 20190531;\nstatic const u32 coex_ver = 0xe;\n/*  static const u32 bt_desired_ver = 0x9; */\n\nstatic u8\nrtw_btc_rssi_state(struct btc_coexist *btc, u8 *pre_state,\n\t\t   u8 rssi, u8 rssi_thresh)\n{\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\tu8\tnext_state, tol = chip_para->rssi_tolerance;\n\n\tif (*pre_state == BTC_RSSI_STATE_LOW ||\n\t    *pre_state == BTC_RSSI_STATE_STAY_LOW) {\n\t\tif (rssi >= (rssi_thresh + tol))\n\t\t\tnext_state = BTC_RSSI_STATE_HIGH;\n\t\telse\n\t\t\tnext_state = BTC_RSSI_STATE_STAY_LOW;\n\t} else {\n\t\tif (rssi < rssi_thresh)\n\t\t\tnext_state = BTC_RSSI_STATE_LOW;\n\t\telse\n\t\t\tnext_state = BTC_RSSI_STATE_STAY_HIGH;\n\t}\n\n\t*pre_state = next_state;\n\treturn next_state;\n}\n\nstatic void\nrtw_btc_limited_tx(struct btc_coexist *btc, boolean force_exec,\n\t\t   boolean tx_limit_en,  boolean ampdu_limit_en)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\tboolean wl_b_mode = FALSE;\n\n\tif (!chip_para->scbd_support)\n\t\treturn;\n\n\t/* Force Max Tx retry limit = 8*/\n\tif (!coex_sta->wl_tx_limit_en) {\n\t\tcoex_sta->wl_arfb1_backup = btc->btc_read_4byte(btc, 0x430);\n\t\tcoex_sta->wl_arfb2_backup = btc->btc_read_4byte(btc, 0x434);\n\t\tcoex_sta->wl_txlimit_backup = btc->btc_read_2byte(btc, 0x42a);\n\t}\n\n\tif (!coex_sta->wl_ampdu_limit_en)\n\t\tcoex_sta->wl_ampdulen_backup = btc->btc_read_1byte(btc, 0x455);\n\n\tif (!force_exec && tx_limit_en == coex_sta->wl_tx_limit_en &&\n\t    ampdu_limit_en == coex_sta->wl_ampdu_limit_en)\n\t\treturn;\n\n\tcoex_sta->wl_tx_limit_en = tx_limit_en;\n\tcoex_sta->wl_ampdu_limit_en = ampdu_limit_en;\n\n\tif (tx_limit_en) {\n\t\t/* Set BT polluted packet on for Tx rate adaptive\n\t\t * Set queue life time to avoid can't reach tx retry limit\n\t\t * if tx is always break by GNT_BT.\n\t\t */\n\t\tbtc->btc_write_1byte_bitmask(btc, 0x45e, 0x8, 0x1);\n\n\t\t/* queue life time can't on if 2-port */\n\t\tif (link_info_ext->num_of_active_port <= 1)\n\t\t\tbtc->btc_write_1byte_bitmask(btc, 0x426, 0xf, 0xf);\n\n\t\t/* Max Tx retry limit = 8*/\n\t\tbtc->btc_write_2byte(btc, 0x42a, 0x0808);\n\n\t\tbtc->btc_get(btc, BTC_GET_BL_WIFI_UNDER_B_MODE, &wl_b_mode);\n\n\t\t/* Auto rate fallback step within 8 retry*/\n\t\tif (wl_b_mode) {\n\t\t\tbtc->btc_write_4byte(btc, 0x430, 0x1000000);\n\t\t\tbtc->btc_write_4byte(btc, 0x434, 0x1010101);\n\t\t} else {\n\t\t\tbtc->btc_write_4byte(btc, 0x430, 0x1000000);\n\t\t\tbtc->btc_write_4byte(btc, 0x434, 0x4030201);\n\t\t}\n\t} else {\n\t\t/* Set BT polluted packet on for Tx rate adaptive not\n\t\t *including Tx retry break by PTA, 0x45c[19] =1\n\t\t */\n\t\tbtc->btc_write_1byte_bitmask(btc, 0x45e, 0x8, 0x0);\n\n\t\t/* Set queue life time to avoid can't reach tx retry limit\n\t\t * if tx is always break by GNT_BT.\n\t\t */\n\t\tbtc->btc_write_1byte_bitmask(btc, 0x426, 0xf, 0x0);\n\n\t\t/* Recovery Max Tx retry limit*/\n\t\tbtc->btc_write_2byte(btc, 0x42a, coex_sta->wl_txlimit_backup);\n\t\tbtc->btc_write_4byte(btc, 0x430, coex_sta->wl_arfb1_backup);\n\t\tbtc->btc_write_4byte(btc, 0x434, coex_sta->wl_arfb2_backup);\n\t}\n\n\tif (ampdu_limit_en)\n\t\tbtc->btc_write_1byte(btc, 0x455, 0x20);\n\telse\n\t\tbtc->btc_write_1byte(btc, 0x455, coex_sta->wl_ampdulen_backup);\n}\n\nstatic void\nrtw_btc_limited_rx(struct btc_coexist *btc, boolean force_exec,\n\t\t   boolean rej_ap_agg_pkt, boolean bt_ctrl_agg_buf_size,\n\t\t   u8 agg_buf_size)\n{\n#if 0\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tboolean reject_rx_agg = rej_ap_agg_pkt;\n\tboolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;\n\tu8 rx_agg_size = agg_buf_size;\n\n\tif (!force_exec &&\n\t    bt_ctrl_agg_buf_size == coex_sta->wl_rxagg_limit_en &&\n\t    agg_buf_size == coex_sta->wl_rxagg_size)\n\t\treturn;\n\n\tcoex_sta->wl_rxagg_limit_en = bt_ctrl_agg_buf_size;\n\tcoex_sta->wl_rxagg_size = agg_buf_size;\n\n\t/*btc->btc_set(btc, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &reject_rx_agg);*/\n\t/* decide BT control aggregation buf size or not */\n\tbtc->btc_set(btc, BTC_SET_BL_BT_CTRL_AGG_SIZE, &bt_ctrl_rx_agg_size);\n\t/* aggregation buf size, only work when BT control Rx aggregation size*/\n\tbtc->btc_set(btc, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);\n\t/* real update aggregation setting */\n\tbtc->btc_set(btc, BTC_SET_ACT_AGGREGATE_CTRL, NULL);\n#endif\n}\n\nstatic void\nrtw_btc_low_penalty_ra(struct btc_coexist *btc, boolean force_exec,\n\t\t       boolean low_penalty_ra, u8 thres)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\n\tif (!force_exec) {\n\t\tif (low_penalty_ra == coex_dm->cur_low_penalty_ra &&\n\t\t    thres == coex_sta->wl_ra_thres)\n\t\t\treturn;\n\t}\n\n\tif (low_penalty_ra)\n\t\tbtc->btc_phydm_modify_RA_PCR_threshold(btc, 0, thres);\n\telse\n\t\tbtc->btc_phydm_modify_RA_PCR_threshold(btc, 0, 0);\n\n\tcoex_dm->cur_low_penalty_ra = low_penalty_ra;\n\tcoex_sta->wl_ra_thres = thres;\n}\n\nstatic void\nrtw_btc_limited_wl(struct btc_coexist *btc)\n{\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\n\tif (link_info_ext->is_all_under_5g ||\n\t    link_info_ext->num_of_active_port == 0 ||\n\t    coex_dm->bt_status == BTC_BTSTATUS_NCON_IDLE) {\n\t\trtw_btc_low_penalty_ra(btc, NM_EXCU, FALSE, 0);\n\t\trtw_btc_limited_tx(btc, NM_EXCU, FALSE, FALSE);\n\t\trtw_btc_limited_rx(btc, NM_EXCU, FALSE, TRUE, 64);\n\t} else if (link_info_ext->num_of_active_port > 1) {\n\t\trtw_btc_low_penalty_ra(btc, NM_EXCU, TRUE, 30);\n\t\trtw_btc_limited_tx(btc, NM_EXCU, TRUE, TRUE);\n\t\trtw_btc_limited_rx(btc, NM_EXCU, FALSE, TRUE, 16);\n\t} else {\n\t\tif (link_info_ext->is_p2p_connected)\n\t\t\trtw_btc_low_penalty_ra(btc, NM_EXCU, TRUE, 30);\n\t\telse\n\t\t\trtw_btc_low_penalty_ra(btc, NM_EXCU, TRUE, 15);\n\n\t\tif (coex_sta->bt_hid_exist || coex_sta->bt_hid_pair_num > 0 ||\n\t\t    coex_sta->bt_hfp_exist) {\n\t\t\trtw_btc_limited_tx(btc, NM_EXCU, TRUE, TRUE);\n\t\t\trtw_btc_limited_rx(btc, NM_EXCU, FALSE, TRUE, 16);\n\t\t} else {\n\t\t\trtw_btc_limited_tx(btc, NM_EXCU, TRUE, FALSE);\n\t\t\trtw_btc_limited_rx(btc, NM_EXCU, FALSE, TRUE, 64);\n\t\t}\n\t}\n}\n\nstatic void\nrtw_btc_mailbox_operation(struct btc_coexist *btc, u8 h2c_id, u8 h2c_len,\n\t\t\t  u8 *h2c_para)\n{\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\tu8\tbuf[6] = {0};\n\n\tif (chip_para->mailbox_support) {\n\t\tbtc->btc_fill_h2c(btc, h2c_id, h2c_len, h2c_para);\n\t\treturn;\n\t}\n\n\tswitch (h2c_id) {\n\tcase 0x61:\n\t\tbuf[0] = 3;\n\t\tbuf[1] = 0x1;\t/* polling enable, 1=enable, 0=disable */\n\t\tbuf[2] = 0x2;\t/* polling time in seconds */\n\t\tbuf[3] = 0x1;\t/* auto report enable, 1=enable, 0=disable */\n\n\t\tbtc->btc_set(btc, BTC_SET_ACT_CTRL_BT_INFO, (void *)&buf[0]);\n\t\tbreak;\n\tcase 0x62:\n\t\tbuf[0] = 4;\n\t\tbuf[1] = 0x3;\t\t/* OP_Code */\n\t\tbuf[2] = 0x2;\t\t/* OP_Code_Length */\n\t\tbuf[3] = (h2c_para[0] != 0) ? 0x1 : 0x0; /* OP_Code_Content */\n\t\tbuf[4] = h2c_para[0];/* pwr_level */\n\n\t\tbtc->btc_set(btc, BTC_SET_ACT_CTRL_BT_COEX, (void *)&buf[0]);\n\t\tbreak;\n\tcase 0x63:\n\t\tbuf[0] = 3;\n\t\tbuf[1] = 0x1;\t\t/* OP_Code */\n\t\tbuf[2] = 0x1;\t\t/* OP_Code_Length */\n\t\tbuf[3] = (h2c_para[0] == 0x1) ? 0x1 : 0x0; /* OP_Code_Content */\n\n\t\tbtc->btc_set(btc, BTC_SET_ACT_CTRL_BT_COEX, (void *)&buf[0]);\n\t\tbreak;\n\tcase 0x66:\n\t\tbuf[0] = 5;\n\t\tbuf[1] = 0x5;\t\t/* OP_Code */\n\t\tbuf[2] = 0x3;\t\t/* OP_Code_Length */\n\t\tbuf[3] = h2c_para[0];\t/* OP_Code_Content */\n\t\tbuf[4] = h2c_para[1];\n\t\tbuf[5] = h2c_para[2];\n\n\t\tbtc->btc_set(btc, BTC_SET_ACT_CTRL_BT_COEX, (void *)&buf[0]);\n\t\tbreak;\n\t}\n}\n\nstatic boolean\nrtw_btc_freerun_check(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\tu8 bt_rssi;\n\n\tif (btc->board_info.btdm_ant_num == 1)\n\t\treturn FALSE;\n\n\tif (btc->board_info.ant_distance >= 40)\n\t\treturn TRUE;\n\n\tif (btc->board_info.ant_distance <= 5)\n\t\treturn FALSE;\n\n\tif (coex_sta->bt_hid_pair_num >= 2)\n\t\treturn TRUE;\n\n\tif (!coex_sta->wl_gl_busy)\n\t\treturn FALSE;\n\n\t/* ant_distance = 5 ~ 40  */\n\tif (BTC_RSSI_HIGH(coex_dm->wl_rssi_state[1]) &&\n\t    BTC_RSSI_HIGH(coex_dm->bt_rssi_state[0]))\n\t\treturn TRUE;\n\n\tif (link_info_ext->traffic_dir == BTC_WIFI_TRAFFIC_TX)\n\t\tbt_rssi = coex_dm->bt_rssi_state[0];\n\telse\n\t\tbt_rssi = coex_dm->bt_rssi_state[1];\n\n\tif (BTC_RSSI_HIGH(coex_dm->wl_rssi_state[3]) &&\n\t    BTC_RSSI_HIGH(bt_rssi) &&\n\t    coex_sta->cnt_wl[BTC_CNT_WL_SCANAP] <= 5)\n\t\treturn TRUE;\n\n\treturn FALSE;\n}\n\nstatic void\nrtw_btc_wl_ccklock_action(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu8 h2c_parameter[2] = {0};\n\n\tif (btc->manual_control || btc->stop_coex_dm)\n\t\treturn;\n\n\tif (coex_sta->tdma_timer_base == 3) {\n\t\tif (!coex_sta->is_no_wl_5ms_extend) {\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], set h2c 0x69 opcode 12 to turn off 5ms WL slot extend!!\\n\");\n\t\t\tBTC_TRACE(trace_buf);\n\n\t\t\th2c_parameter[0] = 0xc;\n\t\t\th2c_parameter[1] = 0x1;\n\t\t\tbtc->btc_fill_h2c(btc, 0x69, 2, h2c_parameter);\n\t\t\tcoex_sta->is_no_wl_5ms_extend = TRUE;\n\t\t\tcoex_sta->cnt_wl[BTC_CNT_WL_5MS_NOEXTEND] = 0;\n\t\t}\n\t\treturn;\n\t}\n\n\tif (!coex_sta->is_no_wl_5ms_extend && coex_sta->wl_force_lps_ctrl &&\n\t    !coex_sta->wl_cck_lock_ever) {\n\t\tif (coex_sta->wl_fw_dbg_info[7] <= 5)\n\t\t\tcoex_sta->cnt_wl[BTC_CNT_WL_5MS_NOEXTEND]++;\n\t\telse\n\t\t\tcoex_sta->cnt_wl[BTC_CNT_WL_5MS_NOEXTEND] = 0;\n\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], 5ms WL slot extend cnt = %d!!\\n\",\n\t\t\t    coex_sta->cnt_wl[BTC_CNT_WL_5MS_NOEXTEND]);\n\t\tBTC_TRACE(trace_buf);\n\n\t\tif (coex_sta->cnt_wl[BTC_CNT_WL_5MS_NOEXTEND] == 7) {\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], set h2c 0x69 opcode 12 to turn off 5ms WL slot extend!!\\n\");\n\t\t\tBTC_TRACE(trace_buf);\n\n\t\t\th2c_parameter[0] = 0xc;\n\t\t\th2c_parameter[1] = 0x1;\n\t\t\tbtc->btc_fill_h2c(btc, 0x69, 2, h2c_parameter);\n\t\t\tcoex_sta->is_no_wl_5ms_extend = TRUE;\n\t\t\tcoex_sta->cnt_wl[BTC_CNT_WL_5MS_NOEXTEND] = 0;\n\t\t}\n\t} else if (coex_sta->is_no_wl_5ms_extend && coex_sta->wl_cck_lock) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], set h2c 0x69 opcode 12 to turn on 5ms WL slot extend!!\\n\");\n\t\tBTC_TRACE(trace_buf);\n\n\t\th2c_parameter[0] = 0xc;\n\t\th2c_parameter[1] = 0x0;\n\t\tbtc->btc_fill_h2c(btc, 0x69, 2, h2c_parameter);\n\t\tcoex_sta->is_no_wl_5ms_extend = FALSE;\n\t}\n}\n\nstatic void\nrtw_btc_wl_ccklock_detect(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\tboolean is_cck_lock_rate = FALSE;\n\n\tif (coex_dm->bt_status == BTC_BTSTATUS_INQ_PAGE ||\n\t    coex_sta->bt_setup_link) {\n\t\tcoex_sta->wl_cck_lock = FALSE;\n\t\tcoex_sta->wl_cck_lock_pre = FALSE;\n\t\treturn;\n\t}\n\n\tif (coex_sta->wl_rx_rate <= BTC_CCK_2 ||\n\t    coex_sta->wl_rts_rx_rate <= BTC_CCK_2)\n\t\tis_cck_lock_rate = TRUE;\n\n\tif (link_info_ext->is_connected && coex_sta->wl_gl_busy &&\n\t    BTC_RSSI_HIGH(coex_dm->wl_rssi_state[3]) &&\n\t    (coex_dm->bt_status == BTC_BTSTATUS_ACL_BUSY ||\n\t     coex_dm->bt_status == BTC_BTSTATUS_ACL_SCO_BUSY ||\n\t     coex_dm->bt_status == BTC_BTSTATUS_SCO_BUSY)) {\n\t\tif (is_cck_lock_rate) {\n\t\t\tcoex_sta->wl_cck_lock = TRUE;\n\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], cck locking...\\n\");\n\t\t\tBTC_TRACE(trace_buf);\n\t\t} else {\n\t\t\tcoex_sta->wl_cck_lock = FALSE;\n\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], cck unlock...\\n\");\n\t\t\tBTC_TRACE(trace_buf);\n\t\t}\n\t} else {\n\t\tcoex_sta->wl_cck_lock = FALSE;\n\t}\n\n\t/* CCK lock identification */\n\tif (coex_sta->wl_cck_lock && !coex_sta->wl_cck_lock_pre)\n\t\tbtc->btc_set_timer(btc, BTC_TIMER_WL_CCKLOCK, 3);\n\n\tcoex_sta->wl_cck_lock_pre = coex_sta->wl_cck_lock;\n}\n\nstatic void\nrtw_btc_wl_noisy_detect(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu32 cnt_cck, ok_11b, err_11b;\n\n\tok_11b = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_CCK);\n\terr_11b = btc->btc_phydm_query_PHY_counter(btc,\n\t\t\t\t\t\t   PHYDM_INFO_CRC32_ERROR_CCK);\n\n\t/* WiFi environment noisy identification */\n\tcnt_cck = ok_11b + err_11b;\n\n\tif (!coex_sta->wl_gl_busy && !coex_sta->wl_cck_lock) {\n\t\tif (cnt_cck > 250) {\n\t\t\tif (coex_sta->cnt_wl[BTC_CNT_WL_NOISY2] < 5)\n\t\t\t\tcoex_sta->cnt_wl[BTC_CNT_WL_NOISY2]++;\n\n\t\t\tif (coex_sta->cnt_wl[BTC_CNT_WL_NOISY2] == 5) {\n\t\t\t\tcoex_sta->cnt_wl[BTC_CNT_WL_NOISY0] = 0;\n\t\t\t\tcoex_sta->cnt_wl[BTC_CNT_WL_NOISY1] = 0;\n\t\t\t}\n\t\t} else if (cnt_cck < 100) {\n\t\t\tif (coex_sta->cnt_wl[BTC_CNT_WL_NOISY0] < 5)\n\t\t\t\tcoex_sta->cnt_wl[BTC_CNT_WL_NOISY0]++;\n\n\t\t\tif (coex_sta->cnt_wl[BTC_CNT_WL_NOISY0] == 5) {\n\t\t\t\tcoex_sta->cnt_wl[BTC_CNT_WL_NOISY1] = 0;\n\t\t\t\tcoex_sta->cnt_wl[BTC_CNT_WL_NOISY2] = 0;\n\t\t\t}\n\t\t} else {\n\t\t\tif (coex_sta->cnt_wl[BTC_CNT_WL_NOISY1] < 5)\n\t\t\t\tcoex_sta->cnt_wl[BTC_CNT_WL_NOISY1]++;\n\n\t\t\tif (coex_sta->cnt_wl[BTC_CNT_WL_NOISY1] == 5) {\n\t\t\t\tcoex_sta->cnt_wl[BTC_CNT_WL_NOISY0] = 0;\n\t\t\t\tcoex_sta->cnt_wl[BTC_CNT_WL_NOISY2] = 0;\n\t\t\t}\n\t\t}\n\n\t\tif (coex_sta->cnt_wl[BTC_CNT_WL_NOISY2] == 5)\n\t\t\tcoex_sta->wl_noisy_level = 2;\n\t\telse if (coex_sta->cnt_wl[BTC_CNT_WL_NOISY1] == 5)\n\t\t\tcoex_sta->wl_noisy_level = 1;\n\t\telse\n\t\t\tcoex_sta->wl_noisy_level = 0;\n\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], wl_noisy_level = %d\\n\",\n\t\t\t    coex_sta->wl_noisy_level);\n\n\t\tBTC_TRACE(trace_buf);\n\t}\n}\n\nstatic void\nrtw_btc_set_extend_btautoslot(struct btc_coexist *btc, u8 thres)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu8 h2c_para[2] = {0x9, 0x32};\n\n\th2c_para[1] = thres; /* thres must be 50 ~ 80*/\n\n\tcoex_sta->bt_ext_autoslot_thres = h2c_para[1];\n\n\tbtc->btc_fill_h2c(btc, 0x69, 2, h2c_para);\n}\n\nstatic void\nrtw_btc_set_tdma_timer_base(struct btc_coexist *btc, u8 type)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu16 tbtt_interval = 100;\n\tu8 h2c_para[2] = {0xb, 0x1};\n\n\tbtc->btc_get(btc, BTC_GET_U2_BEACON_PERIOD, &tbtt_interval);\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], tbtt_interval = %d\\n\", tbtt_interval);\n\tBTC_TRACE(trace_buf);\n\n\t/* Add for JIRA coex-256 */\n\tif (type == 3) { /* 4-slot  */\n\t\tif (coex_sta->tdma_timer_base == 3)\n\t\t\treturn;\n\n\t\th2c_para[1] = 0xc1; /* 4-slot */\n\t\tcoex_sta->tdma_timer_base = 3;\n\t} else if (tbtt_interval < 80 && tbtt_interval > 0) {\n\t\tif (coex_sta->tdma_timer_base == 2)\n\t\t\treturn;\n\t\th2c_para[1] = (100 / tbtt_interval);\n\n\t\tif (100 % tbtt_interval != 0)\n\t\t\th2c_para[1] = h2c_para[1] + 1;\n\n\t\th2c_para[1] = h2c_para[1] & 0x3f;\n\t\tcoex_sta->tdma_timer_base = 2;\n\t} else if (tbtt_interval >= 180) {\n\t\tif (coex_sta->tdma_timer_base == 1)\n\t\t\treturn;\n\t\th2c_para[1] = (tbtt_interval / 100);\n\n\t\tif (tbtt_interval % 100 <= 80)\n\t\t\th2c_para[1] = h2c_para[1] - 1;\n\n\t\th2c_para[1] = h2c_para[1] & 0x3f;\n\t\th2c_para[1] = h2c_para[1] | 0x80;\n\t\tcoex_sta->tdma_timer_base = 1;\n\t} else {\n\t\tif (coex_sta->tdma_timer_base == 0)\n\t\t\treturn;\n\t\th2c_para[1] = 0x1;\n\t\tcoex_sta->tdma_timer_base = 0;\n\t}\n\n\tbtc->btc_fill_h2c(btc, 0x69, 2, h2c_para);\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], %s(): h2c_0x69 = 0x%x\\n\", __func__, h2c_para[1]);\n\tBTC_TRACE(trace_buf);\n\n\t/* no 5ms_wl_slot_extend for 4-slot mode  */\n\tif (coex_sta->tdma_timer_base == 3)\n\t\trtw_btc_wl_ccklock_action(btc);\n}\n\nstatic void\nrtw_btc_set_wl_pri_mask(struct btc_coexist *btc, u8 bitmap, u8 data)\n{\n\tu32 addr;\n\n\taddr = 0x6cc + (bitmap / 8);\n\tbitmap = bitmap % 8;\n\n\tbtc->btc_write_1byte_bitmask(btc, addr, BIT(bitmap), data);\n}\n\nstatic void\nrtw_btc_set_bt_golden_rx_range(struct btc_coexist *btc, boolean force_exec,\n\t\t\t       u8 profile_id, u8 shift_level)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu16 para;\n\n\tif (profile_id > 3)\n\t\treturn;\n\n\tif (!force_exec &&\n\t    shift_level == coex_sta->bt_golden_rx_shift[profile_id])\n\t\treturn;\n\n\tcoex_sta->bt_golden_rx_shift[profile_id] = shift_level;\n\n\tpara = (profile_id << 8) | ((0x100 - shift_level) & 0xff);\n\n\tbtc->btc_set(btc, BTC_SET_BL_BT_GOLDEN_RX_RANGE, &para);\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], %s(): para = 0x%04x\\n\", __func__, para);\n\tBTC_TRACE(trace_buf);\n}\n\nstatic void\nrtw_btc_query_bt_info(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu8 h2c_parameter[1] = {0x1};\n\n\tif (coex_sta->bt_disabled)\n\t\treturn;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_mailbox_operation(btc, 0x61, 1, h2c_parameter);\n}\n\nstatic void\nrtw_btc_gnt_debug(struct btc_coexist *btc, boolean isenable)\n{\n\tif (!isenable)\n\t\tbtc->btc_write_1byte_bitmask(btc, 0x73, 0x8, 0x0);\n\telse\n\t\tbtc->chip_para->chip_setup(btc, BTC_CSETUP_GNT_DEBUG);\n}\n\nstatic void\nrtw_btc_gnt_workaround(struct btc_coexist *btc, boolean force_exec, u8 mode)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\n\tif (!force_exec) {\n\t\tif (coex_sta->gnt_workaround_state == coex_sta->wl_coex_mode)\n\t\t\treturn;\n\t}\n\n\tcoex_sta->gnt_workaround_state = coex_sta->wl_coex_mode;\n\n\tbtc->chip_para->chip_setup(btc, BTC_CSETUP_GNT_FIX);\n}\n\nstatic void\nrtw_btc_monitor_bt_ctr(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu32 u32tmp;\n\n\tu32tmp = btc->btc_read_4byte(btc, 0x770);\n\tcoex_sta->hi_pri_tx = u32tmp & MASKLWORD;\n\tcoex_sta->hi_pri_rx = (u32tmp & MASKHWORD) >> 16;\n\n\tu32tmp = btc->btc_read_4byte(btc, 0x774);\n\tcoex_sta->lo_pri_tx = u32tmp & MASKLWORD;\n\tcoex_sta->lo_pri_rx = (u32tmp & MASKHWORD) >> 16;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\\n\",\n\t\t    coex_sta->hi_pri_rx, coex_sta->hi_pri_tx,\n\t\t    coex_sta->lo_pri_rx, coex_sta->lo_pri_tx);\n\tBTC_TRACE(trace_buf);\n\n\tif (coex_sta->hi_pri_rx == 0 && coex_sta->hi_pri_tx == 0 &&\n\t    coex_sta->lo_pri_rx == 0 && coex_sta->lo_pri_tx == 0) {\n\t\tcoex_sta->cnt_bt[BTC_CNT_BT_DISABLE]++;\n\n\t\tif (coex_sta->cnt_bt[BTC_CNT_BT_DISABLE] > 2)\n\t\t\tcoex_sta->cnt_bt[BTC_CNT_BT_DISABLE] = 2;\n\t} else {\n\t\tcoex_sta->cnt_bt[BTC_CNT_BT_DISABLE] = 0;\n\t}\n\n\t/* reset counter */\n\tbtc->btc_write_1byte(btc, 0x76e, 0xc);\n}\n\nstatic void\nrtw_btc_monitor_bt_enable(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\tboolean bt_disabled = FALSE;\n\tu16 u16tmp;\n\n\tif (chip_para->scbd_support) {\n\t\tbtc->btc_read_scbd(btc, &u16tmp);\n\t\tbt_disabled = (u16tmp & BTC_SCBD_BT_ONOFF) ? FALSE : TRUE;\n\t} else {\n\t\tif (coex_sta->cnt_bt[BTC_CNT_BT_DISABLE] >= 2)\n\t\t\tbt_disabled = TRUE;\n\t}\n\n\tbtc->btc_set(btc, BTC_SET_BL_BT_DISABLE, &bt_disabled);\n\n\tif (coex_sta->bt_disabled != bt_disabled) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], BT is from %s to %s!!\\n\",\n\t\t\t    (coex_sta->bt_disabled ? \"disabled\" : \"enabled\"),\n\t\t\t    (bt_disabled ? \"disabled\" : \"enabled\"));\n\t\tBTC_TRACE(trace_buf);\n\t\tcoex_sta->bt_disabled = bt_disabled;\n\n\t\tcoex_sta->bt_supported_feature = 0;\n\t\tcoex_sta->bt_supported_version = 0;\n\t\tcoex_sta->bt_ble_scan_type = 0;\n\t\tcoex_sta->bt_ble_scan_para[0] = 0;\n\t\tcoex_sta->bt_ble_scan_para[1] = 0;\n\t\tcoex_sta->bt_ble_scan_para[2] = 0;\n\t\tcoex_sta->bt_reg_vendor_ac = 0xffff;\n\t\tcoex_sta->bt_reg_vendor_ae = 0xffff;\n\t\tcoex_sta->bt_a2dp_vendor_id = 0;\n\t\tcoex_sta->bt_a2dp_device_name = 0;\n\t\tcoex_sta->bt_iqk_state = 0;\n\t\tcoex_dm->cur_bt_lna_lvl = 0;\n\t\tbtc->bt_info.bt_get_fw_ver = 0;\n\n\t\t/*for win10 BT disable->enable trigger wifi scan issue   */\n\t\tif (!coex_sta->bt_disabled) {\n\t\t\tcoex_sta->bt_reenable = TRUE;\n\t\t\tbtc->btc_set_timer(btc, BTC_TIMER_BT_REENABLE, 15);\n\t\t} else {\n\t\t\tcoex_sta->bt_reenable = FALSE;\n\t\t}\n\t}\n}\n\nstatic void\nrtw_btc_update_bt_sut_info(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu32 val = 0;\n\n\tif (coex_sta->bt_profile_num == 0) {\n\t\t/* clear golden rx range if no PAN exist */\n\t\tif (coex_sta->bt_golden_rx_shift[3] != 0)\n\t\t\trtw_btc_set_bt_golden_rx_range(btc, FC_EXCU, 3, 0);\n\t\treturn;\n\t}\n\n\tif (coex_sta->bt_a2dp_exist) {\n\t\tif (coex_sta->bt_a2dp_vendor_id == 0 &&\n\t\t    coex_sta->bt_a2dp_device_name == 0) {\n\t\t\tbtc->btc_get(btc, BTC_GET_U4_BT_DEVICE_INFO, &val);\n\n\t\t\tcoex_sta->bt_a2dp_vendor_id = (u8)(val & 0xff);\n\t\t\tcoex_sta->bt_a2dp_device_name = (val & 0xffffff00) >> 8;\n\t\t}\n\n\t\trtw_btc_set_bt_golden_rx_range(btc, FC_EXCU, 2, 0);\n\t} else {\n\t\tcoex_sta->bt_sut_pwr_lvl[2] = 0xff;\n\t}\n\n\tif (coex_sta->bt_hfp_exist)\n\t\trtw_btc_set_bt_golden_rx_range(btc, FC_EXCU, 0, 0);\n\telse\n\t\tcoex_sta->bt_sut_pwr_lvl[0] = 0xff;\n\n\tif (coex_sta->bt_hid_exist)\n\t\trtw_btc_set_bt_golden_rx_range(btc, FC_EXCU, 1, 0);\n\telse\n\t\tcoex_sta->bt_sut_pwr_lvl[1] = 0xff;\n\n\tif (coex_sta->bt_pan_exist) {\n\t\trtw_btc_set_bt_golden_rx_range(btc, FC_EXCU, 3,\n\t\t\t\t\t       coex_sta->bt_golden_rx_shift[3]);\n\t} else {\n\t\tcoex_sta->bt_golden_rx_shift[3] = 0;\n\t\tcoex_sta->bt_sut_pwr_lvl[3] = 0xff;\n\t}\n}\n\nstatic void\nrtw_btc_update_wl_link_info(struct btc_coexist *btc, u8 reason)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tstruct btc_wifi_link_info_ext *linfo_ext = &btc->wifi_link_info_ext;\n\tstruct btc_wifi_link_info linfo;\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\tu8 wifi_central_chnl = 0, num_of_wifi_link = 0, i;\n\tu32 wifi_link_status = 0, wifi_bw;\n\ts32 wl_rssi;\n\tboolean isunder5G = FALSE, ismcc25g = FALSE, is_p2p_connected = FALSE,\n\t\tplus_bt = FALSE;\n\n\tbtc->btc_get(btc, BTC_GET_BL_WIFI_SCAN, &linfo_ext->is_scan);\n\tbtc->btc_get(btc, BTC_GET_BL_WIFI_LINK, &linfo_ext->is_link);\n\tbtc->btc_get(btc, BTC_GET_BL_WIFI_ROAM, &linfo_ext->is_roam);\n\tbtc->btc_get(btc, BTC_GET_BL_WIFI_LW_PWR_STATE, &linfo_ext->is_32k);\n\tbtc->btc_get(btc, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &linfo_ext->is_4way);\n\tbtc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &linfo_ext->is_connected);\n\tbtc->btc_get(btc, BTC_GET_U4_WIFI_TRAFFIC_DIR, &linfo_ext->traffic_dir);\n\tbtc->btc_get(btc, BTC_GET_U4_WIFI_BW, &linfo_ext->wifi_bw);\n\tbtc->btc_get(btc, BTC_GET_U4_WIFI_LINK_STATUS, &wifi_link_status);\n\tlinfo_ext->port_connect_status = wifi_link_status & 0xffff;\n\n\tbtc->btc_get(btc, BTC_GET_BL_WIFI_LINK_INFO, &linfo);\n\tbtc->wifi_link_info = linfo;\n\n\tbtc->btc_get(btc, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifi_central_chnl);\n\tcoex_sta->wl_center_ch = wifi_central_chnl;\n\n\tbtc->btc_get(btc, BTC_GET_S4_WIFI_RSSI, &wl_rssi);\n\tfor (i = 0; i < 4; i++)\n\t\trtw_btc_rssi_state(btc, &coex_dm->wl_rssi_state[i],\n\t\t\t\t   (u8)(wl_rssi & 0xff),\n\t\t\t\t   chip_para->wl_rssi_step[i]);\n\n\t/* Check scan/connect/special-pkt action first  */\n\tswitch (reason) {\n\tcase BTC_RSN_5GSCANSTART:\n\tcase BTC_RSN_5GSWITCHBAND:\n\tcase BTC_RSN_5GCONSTART:\n\n\t\tisunder5G = TRUE;\n\t\tbreak;\n\tcase BTC_RSN_2GSCANSTART:\n\tcase BTC_RSN_2GSWITCHBAND:\n\tcase BTC_RSN_2GCONSTART:\n\n\t\tisunder5G = FALSE;\n\t\tbreak;\n\tcase BTC_RSN_2GCONFINISH:\n\tcase BTC_RSN_5GCONFINISH:\n\tcase BTC_RSN_2GMEDIA:\n\tcase BTC_RSN_5GMEDIA:\n\tcase BTC_RSN_BTINFO:\n\tcase BTC_RSN_PERIODICAL:\n\tcase BTC_RSN_TIMERUP:\n\tcase BTC_RSN_WLSTATUS:\n\tcase BTC_RSN_2GSPECIALPKT:\n\tcase BTC_RSN_5GSPECIALPKT:\n\tdefault:\n\t\tswitch (linfo.link_mode) {\n\t\tcase BTC_LINK_5G_MCC_GO_STA:\n\t\tcase BTC_LINK_5G_MCC_GC_STA:\n\t\tcase BTC_LINK_5G_SCC_GO_STA:\n\t\tcase BTC_LINK_5G_SCC_GC_STA:\n\n\t\t\tisunder5G = TRUE;\n\t\t\tbreak;\n\t\tcase BTC_LINK_2G_MCC_GO_STA:\n\t\tcase BTC_LINK_2G_MCC_GC_STA:\n\t\tcase BTC_LINK_2G_SCC_GO_STA:\n\t\tcase BTC_LINK_2G_SCC_GC_STA:\n\n\t\t\tisunder5G = FALSE;\n\t\t\tbreak;\n\t\tcase BTC_LINK_25G_MCC_GO_STA:\n\t\tcase BTC_LINK_25G_MCC_GC_STA:\n\n\t\t\tisunder5G = FALSE;\n\t\t\tismcc25g = TRUE;\n\t\t\tbreak;\n\t\tcase BTC_LINK_ONLY_STA:\n\t\t\tif (linfo.sta_center_channel > 14)\n\t\t\t\tisunder5G = TRUE;\n\t\t\telse\n\t\t\t\tisunder5G = FALSE;\n\t\t\tbreak;\n\t\tcase BTC_LINK_ONLY_GO:\n\t\tcase BTC_LINK_ONLY_GC:\n\t\tcase BTC_LINK_ONLY_AP:\n\t\tdefault:\n\t\t\tif (linfo.p2p_center_channel > 14)\n\t\t\t\tisunder5G = TRUE;\n\t\t\telse\n\t\t\t\tisunder5G = FALSE;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\t}\n\n\tlinfo_ext->is_all_under_5g = isunder5G;\n\tlinfo_ext->is_mcc_25g = ismcc25g;\n\n\tif (wifi_link_status & WIFI_STA_CONNECTED)\n\t\tnum_of_wifi_link++;\n\n\tif (wifi_link_status & WIFI_AP_CONNECTED)\n\t\tnum_of_wifi_link++;\n\n\tif (wifi_link_status & WIFI_P2P_GO_CONNECTED) {\n\t\tif (!(wifi_link_status & WIFI_AP_CONNECTED))\n\t\t\tnum_of_wifi_link++;\n\t\tis_p2p_connected = TRUE;\n\t}\n\n\tif (wifi_link_status & WIFI_P2P_GC_CONNECTED) {\n\t\tnum_of_wifi_link++;\n\t\tis_p2p_connected = TRUE;\n\t}\n\n\tlinfo_ext->num_of_active_port = num_of_wifi_link;\n\tlinfo_ext->is_p2p_connected = is_p2p_connected;\n\n\tif (linfo.link_mode == BTC_LINK_ONLY_GO && linfo.bhotspot)\n\t\tlinfo_ext->is_ap_mode = TRUE;\n\telse\n\t\tlinfo_ext->is_ap_mode = FALSE;\n\n\tif (linfo_ext->is_p2p_connected && coex_sta->bt_link_exist)\n\t\tplus_bt = TRUE;\n\n\tbtc->btc_set(btc, BTC_SET_BL_MIRACAST_PLUS_BT, &plus_bt);\n\n\tif (linfo_ext->is_scan || linfo_ext->is_link ||\n\t    linfo_ext->is_roam || linfo_ext->is_4way ||\n\t    reason == BTC_RSN_2GSCANSTART ||\n\t    reason == BTC_RSN_2GSWITCHBAND ||\n\t    reason == BTC_RSN_2GCONSTART ||\n\t    reason == BTC_RSN_2GSPECIALPKT)\n\t\tcoex_sta->wl_linkscan_proc = TRUE;\n\telse\n\t\tcoex_sta->wl_linkscan_proc = FALSE;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\\n\",\n\t\t    linfo_ext->is_scan, linfo_ext->is_link,\n\t\t    linfo_ext->is_roam,\n\t\t    linfo_ext->is_4way);\n\tBTC_TRACE(trace_buf);\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], wifi_link_info: link_mode=%d, STA_Ch=%d, P2P_Ch=%d, AnyClient_Join_Go=%d !\\n\",\n\t\t    linfo.link_mode,\n\t\t    linfo.sta_center_channel,\n\t\t    linfo.p2p_center_channel,\n\t\t    linfo.bany_client_join_go);\n\tBTC_TRACE(trace_buf);\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], wifi_link_info: center_ch=%d, is_all_under_5g=%d, is_mcc_25g=%d!\\n\",\n\t\t    coex_sta->wl_center_ch,\n\t\t    linfo_ext->is_all_under_5g,\n\t\t    linfo_ext->is_mcc_25g);\n\tBTC_TRACE(trace_buf);\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], wifi_link_info: port_connect_status=0x%x, active_port_cnt=%d, P2P_Connect=%d!\\n\",\n\t\t    linfo_ext->port_connect_status,\n\t\t    linfo_ext->num_of_active_port,\n\t\t    linfo_ext->is_p2p_connected);\n\tBTC_TRACE(trace_buf);\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], Update reason = %s\\n\",\n\t\t    run_reason_string[reason]);\n\tBTC_TRACE(trace_buf);\n}\n\nstatic void\nrtw_btc_update_bt_link_info(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\tboolean bt_busy = FALSE, increase_scan_dev_num = FALSE,\n\t\tscan_type_change = FALSE;\n\tu8 i, scan_type;\n\n\t/* update wl/bt rssi by btinfo */\n\tfor (i = 0; i < 4; i++)\n\t\trtw_btc_rssi_state(btc, &coex_dm->bt_rssi_state[i],\n\t\t\t\t   coex_sta->bt_rssi,\n\t\t\t\t   chip_para->bt_rssi_step[i]);\n\n\tif (coex_sta->bt_ble_scan_en) {\n\t\tscan_type = btc->btc_get_ble_scan_type_from_bt(btc);\n\n\t\tif (scan_type != coex_sta->bt_ble_scan_type)\n\t\t\tscan_type_change = TRUE;\n\n\t\tcoex_sta->bt_ble_scan_type = scan_type;\n\t}\n\n\tif (scan_type_change) {\n\t\tu32 *p = NULL;\n\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], BTinfo HiByte1[5] check, query BLE Scan type!!\\n\");\n\t\tBTC_TRACE(trace_buf);\n\n\t\tif ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) {\n\t\t\tcoex_sta->bt_init_scan = TRUE;\n\t\t\tp = &coex_sta->bt_ble_scan_para[0];\n\t\t\t*p = btc->btc_get_ble_scan_para_from_bt(btc, 0x1);\n\t\t} else {\n\t\t\tcoex_sta->bt_init_scan = FALSE;\n\t\t}\n\n\t\tif ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) {\n\t\t\tp = &coex_sta->bt_ble_scan_para[1];\n\t\t\t*p = btc->btc_get_ble_scan_para_from_bt(btc, 0x2);\n\t\t}\n\n\t\tif ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) {\n\t\t\tp = &coex_sta->bt_ble_scan_para[2];\n\t\t\t*p = btc->btc_get_ble_scan_para_from_bt(btc, 0x4);\n\t\t}\n\t}\n\n\tcoex_sta->bt_profile_num = 0;\n\n\t/* set link exist status */\n\tif (!(coex_sta->bt_info_lb2 & BTC_INFO_CONNECTION)) {\n\t\tcoex_sta->bt_link_exist = FALSE;\n\t\tcoex_sta->bt_pan_exist = FALSE;\n\t\tcoex_sta->bt_a2dp_exist = FALSE;\n\t\tcoex_sta->bt_hid_exist = FALSE;\n\t\tcoex_sta->bt_hfp_exist = FALSE;\n\t\tcoex_sta->bt_msft_mr_exist = FALSE;\n\t} else { /* connection exists */\n\t\tcoex_sta->bt_link_exist = TRUE;\n\t\tif (coex_sta->bt_info_lb2 & BTC_INFO_FTP) {\n\t\t\tcoex_sta->bt_pan_exist = TRUE;\n\t\t\tcoex_sta->bt_profile_num++;\n\t\t} else {\n\t\t\tcoex_sta->bt_pan_exist = FALSE;\n\t\t}\n\n\t\tif (coex_sta->bt_info_lb2 & BTC_INFO_A2DP) {\n\t\t\tcoex_sta->bt_a2dp_exist = TRUE;\n\t\t\tcoex_sta->bt_profile_num++;\n\t\t} else {\n\t\t\tcoex_sta->bt_a2dp_exist = FALSE;\n\t\t}\n\n\t\tif (coex_sta->bt_info_lb2 & BTC_INFO_HID) {\n\t\t\tcoex_sta->bt_hid_exist = TRUE;\n\t\t\tcoex_sta->bt_profile_num++;\n\t\t} else {\n\t\t\tcoex_sta->bt_hid_exist = FALSE;\n\t\t}\n\n\t\tif (coex_sta->bt_info_lb2 & BTC_INFO_SCO_ESCO) {\n\t\t\tcoex_sta->bt_hfp_exist = TRUE;\n\t\t\tcoex_sta->bt_profile_num++;\n\t\t} else {\n\t\t\tcoex_sta->bt_hfp_exist = FALSE;\n\t\t}\n\n\t\tif (coex_sta->bt_hid_slot == 0 &&\n\t\t    coex_sta->bt_hid_pair_num > 0 &&\n\t\t    coex_sta->lo_pri_tx > 1000 &&\n\t\t    coex_sta->lo_pri_rx > 1000 &&\n\t\t    !coex_sta->bt_inq_page)\n\t\t\tcoex_sta->bt_msft_mr_exist = TRUE;\n\t\telse\n\t\t\tcoex_sta->bt_msft_mr_exist = FALSE;\n\t}\n\n\tif (coex_sta->bt_info_lb2 & BTC_INFO_INQ_PAGE) {\n\t\tcoex_dm->bt_status = BTC_BTSTATUS_INQ_PAGE;\n\t} else if (!(coex_sta->bt_info_lb2 & BTC_INFO_CONNECTION)) {\n\t\tcoex_dm->bt_status = BTC_BTSTATUS_NCON_IDLE;\n\t} else if (coex_sta->bt_info_lb2 == BTC_INFO_CONNECTION) {\n\t\tif (coex_sta->bt_msft_mr_exist)\n\t\t\tcoex_dm->bt_status = BTC_BTSTATUS_ACL_BUSY;\n\t\telse\n\t\t\tcoex_dm->bt_status = BTC_BTSTATUS_CON_IDLE;\n\t} else if ((coex_sta->bt_info_lb2 & BTC_INFO_SCO_ESCO) ||\n\t\t   (coex_sta->bt_info_lb2 & BTC_INFO_SCO_BUSY)) {\n\t\tif (coex_sta->bt_info_lb2 & BTC_INFO_ACL_BUSY)\n\t\t\tcoex_dm->bt_status = BTC_BTSTATUS_ACL_SCO_BUSY;\n\t\telse\n\t\t\tcoex_dm->bt_status = BTC_BTSTATUS_SCO_BUSY;\n\t} else if (coex_sta->bt_info_lb2 & BTC_INFO_ACL_BUSY) {\n\t\tcoex_dm->bt_status = BTC_BTSTATUS_ACL_BUSY;\n\t} else {\n\t\tcoex_dm->bt_status = BTC_BTSTATUS_MAX;\n\t}\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s(), %s!!!\\n\",\n\t\t    __func__, bt_status_string[coex_dm->bt_status]);\n\tBTC_TRACE(trace_buf);\n\n\tif (coex_dm->bt_status == BTC_BTSTATUS_ACL_BUSY ||\n\t    coex_dm->bt_status == BTC_BTSTATUS_SCO_BUSY ||\n\t    coex_dm->bt_status == BTC_BTSTATUS_ACL_SCO_BUSY) {\n\t\tbt_busy = TRUE;\n\t\tincrease_scan_dev_num = TRUE;\n\t} else {\n\t\tbt_busy = FALSE;\n\t\tincrease_scan_dev_num = FALSE;\n\t}\n\n\tbtc->btc_set(btc, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);\n\tbtc->btc_set(btc, BTC_SET_BL_INC_SCAN_DEV_NUM, &increase_scan_dev_num);\n\n\tif (coex_sta->bt_profile_num != coex_sta->bt_profile_num_pre) {\n\t\trtw_btc_update_bt_sut_info(btc);\n\t\tcoex_sta->bt_profile_num_pre = coex_sta->bt_profile_num;\n\t}\n\n\tcoex_sta->cnt_bt[BTC_CNT_BT_INFOUPDATE]++;\n}\n\nstatic void\nrtw_btc_update_wl_ch_info(struct btc_coexist *btc, u8 type)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\tstruct btc_wifi_link_info *link_info = &btc->wifi_link_info;\n\tu8 h2c_para[3] = {0}, i, wl_center_ch = 0;\n\n\tif (btc->manual_control)\n\t\treturn;\n\n\tif (btc->stop_coex_dm || btc->wl_rf_state_off) {\n\t\twl_center_ch = 0;\n\t} else if (type != BTC_MEDIA_DISCONNECT ||\n\t\t   (type == BTC_MEDIA_DISCONNECT &&\n\t\t    link_info_ext->num_of_active_port > 0)) {\n\t\tif (link_info_ext->num_of_active_port == 1) {\n\t\t\tif (link_info_ext->is_p2p_connected)\n\t\t\t\twl_center_ch = link_info->p2p_center_channel;\n\t\t\telse\n\t\t\t\twl_center_ch = link_info->sta_center_channel;\n\t\t} else { /* port > 2 */\n\t\t\tif (link_info->p2p_center_channel > 14 &&\n\t\t\t    link_info->sta_center_channel > 14)\n\t\t\t\twl_center_ch = link_info->p2p_center_channel;\n\t\t\telse if (link_info->p2p_center_channel <= 14)\n\t\t\t\twl_center_ch = link_info->p2p_center_channel;\n\t\t\telse if (link_info->sta_center_channel <= 14)\n\t\t\t\twl_center_ch = link_info->sta_center_channel;\n\t\t}\n\t}\n\n\tif (wl_center_ch == 0 ||\n\t    (btc->board_info.btdm_ant_num == 1 && wl_center_ch <= 14)) {\n\t\th2c_para[0] = 0;\n\t\th2c_para[1] = 0;\n\t\th2c_para[2] = 0;\n\t} else if (wl_center_ch <= 14) {\n\t\th2c_para[0] = 0x1;\n\t\th2c_para[1] = wl_center_ch;\n\n\t\tif (link_info_ext->wifi_bw == BTC_WIFI_BW_HT40)\n\t\t\th2c_para[2] = chip_para->bt_afh_span_bw40;\n\t\telse\n\t\t\th2c_para[2] = chip_para->bt_afh_span_bw20;\n\t} else if (chip_para->afh_5g_num > 1) { /* for 5G  */\n\t\tfor (i = 0; i < chip_para->afh_5g_num; i++) {\n\t\t\tif (wl_center_ch == chip_para->afh_5g[i].wl_5g_ch) {\n\t\t\t\th2c_para[0] = 0x3;\n\t\t\t\th2c_para[1] = chip_para->afh_5g[i].bt_skip_ch;\n\t\t\t\th2c_para[2] = chip_para->afh_5g[i].bt_skip_span;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tcoex_dm->wl_chnl_info[0] = h2c_para[0];\n\tcoex_dm->wl_chnl_info[1] = h2c_para[1];\n\tcoex_dm->wl_chnl_info[2] = h2c_para[2];\n\trtw_btc_mailbox_operation(btc, 0x66, 3, h2c_para);\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], %s: para[0:2] = 0x%x 0x%x 0x%x\\n\",\n\t\t    __func__, h2c_para[0], h2c_para[1], h2c_para[2]);\n\tBTC_TRACE(trace_buf);\n}\n\nstatic void\nrtw_btc_set_wl_tx_power(struct btc_coexist *btc,\n\t\t\tboolean force_exec, u8 wl_pwr_dec_lvl)\n{\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tu8 i, pwr;\n\tu32 reg_addr;\n\n\tif (!force_exec && wl_pwr_dec_lvl == coex_dm->cur_wl_pwr_lvl)\n\t\treturn;\n\n\tcoex_dm->cur_wl_pwr_lvl = wl_pwr_dec_lvl;\n\n\tchip_para->chip_setup(btc, BTC_CSETUP_WL_TX_POWER);\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s(): level = %d\\n\",\n\t\t    __func__, wl_pwr_dec_lvl);\n\tBTC_TRACE(trace_buf);\n}\n\nstatic void\nrtw_btc_set_bt_tx_power(struct btc_coexist *btc,\n\t\t\tboolean force_exec, u8 bt_pwr_dec_lvl)\n{\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tu8 h2c_para[1] = {0};\n\n\tif (!force_exec && bt_pwr_dec_lvl == coex_dm->cur_bt_pwr_lvl)\n\t\treturn;\n\n\th2c_para[0] = (0x100 - bt_pwr_dec_lvl) & 0xff;\n\n\trtw_btc_mailbox_operation(btc, 0x62, 1, h2c_para);\n\n\tcoex_dm->cur_bt_pwr_lvl = bt_pwr_dec_lvl;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], %s(), bt_tx_power = 0x%x, level = %d\\n\",\n\t\t    __func__, h2c_para[0], bt_pwr_dec_lvl);\n\tBTC_TRACE(trace_buf);\n}\n\nstatic void\nrtw_btc_set_wl_rx_gain(struct btc_coexist *btc, boolean force_exec,\n\t\t       boolean low_gain_en)\n{\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\n\tif (!force_exec && low_gain_en == coex_dm->cur_wl_rx_low_gain_en)\n\t\treturn;\n\n\tcoex_dm->cur_wl_rx_low_gain_en = low_gain_en;\n\n\tif (low_gain_en)\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], Hi-L Rx!\\n\");\n\telse\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], Nm-L Rx!\\n\");\n\n\tBTC_TRACE(trace_buf);\n\n\tchip_para->chip_setup(btc, BTC_CSETUP_WL_RX_GAIN);\n}\n\nstatic void\nrtw_btc_set_bt_rx_gain(struct btc_coexist *btc, boolean force_exec, u8 lna_lvl)\n{\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\n\tif (!force_exec && lna_lvl == coex_dm->cur_bt_lna_lvl)\n\t\treturn;\n\n\tif (lna_lvl < 7) {\n\t\tbtc->btc_set(btc, BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL, &lna_lvl);\n\t\t/* use scoreboard[4] to notify BT Rx gain table change */\n\t\tbtc->btc_write_scbd(btc, BTC_SCBD_RXGAIN, TRUE);\n\t} else {\n\t\tbtc->btc_write_scbd(btc, BTC_SCBD_RXGAIN, FALSE);\n\t}\n\n\tcoex_dm->cur_bt_lna_lvl = lna_lvl;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], %s(): bt_rx_LNA_level = %d\\n\",\n\t\t    __func__, lna_lvl);\n\tBTC_TRACE(trace_buf);\n}\n\nstatic void\nrtw_btc_set_rf_para(struct btc_coexist *btc, boolean force_exec,\n\t\t    struct btc_rf_para para)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu8 tmp = 0;\n\n\tif (coex_sta->coex_freerun) {\n\t\tif (coex_sta->cnt_wl[BTC_CNT_WL_SCANAP] <= 5)\n\t\t\ttmp = 3;\n\t}\n\n\trtw_btc_set_wl_tx_power(btc, force_exec, para.wl_pwr_dec_lvl);\n\trtw_btc_set_bt_tx_power(btc, force_exec, para.bt_pwr_dec_lvl + tmp);\n\trtw_btc_set_wl_rx_gain(btc, force_exec, para.wl_low_gain_en);\n\trtw_btc_set_bt_rx_gain(btc, force_exec, para.bt_lna_lvl);\n}\n\nstatic void\nrtw_btc_coex_ctrl_owner(struct btc_coexist *btc, boolean wifi_control)\n{\n\tu8 val;\n\n\tval = (wifi_control) ? 1 : 0;\n\tbtc->btc_write_1byte_bitmask(btc, 0x73, BIT(2), val); /* 0x70[26] */\n\n\tif (!wifi_control)\n\t\tbtc->chip_para->chip_setup(btc, BTC_CSETUP_WLAN_ACT_IPS);\n}\n\nstatic void\nrtw_btc_set_gnt_bt(struct btc_coexist *btc, u8 state)\n{\n\tswitch (state) {\n\tcase BTC_GNT_SW_LOW:\n\t\tbtc->btc_write_linderct(btc, 0x38, 0xc000, 0x1);\n\t\tbtc->btc_write_linderct(btc, 0x38, 0x0c00, 0x1);\n\t\tbreak;\n\tcase BTC_GNT_SW_HIGH:\n\t\tbtc->btc_write_linderct(btc, 0x38, 0xc000, 0x3);\n\t\tbtc->btc_write_linderct(btc, 0x38, 0x0c00, 0x3);\n\t\tbreak;\n\tcase BTC_GNT_HW_PTA:\n\tdefault:\n\t\tbtc->btc_write_linderct(btc, 0x38, 0xc000, 0x0);\n\t\tbtc->btc_write_linderct(btc, 0x38, 0x0c00, 0x0);\n\t\tbreak;\n\t}\n}\n\nstatic void\nrtw_btc_set_gnt_wl(struct btc_coexist *btc, u8 state)\n{\n\tswitch (state) {\n\tcase BTC_GNT_SW_LOW:\n\t\tbtc->btc_write_linderct(btc, 0x38, 0x3000, 0x1);\n\t\tbtc->btc_write_linderct(btc, 0x38, 0x0300, 0x1);\n\t\tbreak;\n\tcase BTC_GNT_SW_HIGH:\n\t\tbtc->btc_write_linderct(btc, 0x38, 0x3000, 0x3);\n\t\tbtc->btc_write_linderct(btc, 0x38, 0x0300, 0x3);\n\t\tbreak;\n\tcase BTC_GNT_HW_PTA:\n\tdefault:\n\t\tbtc->btc_write_linderct(btc, 0x38, 0x3000, 0x0);\n\t\tbtc->btc_write_linderct(btc, 0x38, 0x0300, 0x0);\n\t\tbreak;\n\t}\n}\n\nstatic void\nrtw_btc_mimo_ps(struct btc_coexist *btc, boolean force_exec,\n\t\tu8 state)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\n\tif (!force_exec && state == coex_sta->wl_mimo_ps)\n\t\treturn;\n\n\tcoex_sta->wl_mimo_ps = state;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], %s(): state = %d\\n\", __func__, state);\n\tBTC_TRACE(trace_buf);\n\n\tbtc->btc_set(btc, BTC_SET_MIMO_PS_MODE, &state);\n}\n\nstatic void\nrtw_btc_wltoggle_tableA(IN struct btc_coexist *btc,\n\t\t\tIN boolean force_exec,  IN u32 table_case)\n{\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\tu8 h2c_para[6] = {0};\n\tu32 table_wl = 0x5a5a5a5a;\n\n\th2c_para[0] = 0xd; /* op_code, 0x7= wlan slot toggle-A*/\n\th2c_para[1] = 0x1; /* no definition */\n\n\tif (btc->board_info.btdm_ant_num == 1) {\n\t\tif (table_case < chip_para->table_sant_num)\n\t\t\ttable_wl = chip_para->table_sant[table_case].wl;\n\t} else {\n\t\tif (table_case < chip_para->table_nsant_num)\n\t\t\ttable_wl = chip_para->table_nsant[table_case].wl;\n\t}\n\n\t/* tell WL FW WL slot toggle table-A*/\n\th2c_para[2] = (u8)(table_wl & 0xff);\n\th2c_para[3] = (u8)((table_wl & 0xff00) >> 8);\n\th2c_para[4] = (u8)((table_wl & 0xff0000) >> 16);\n\th2c_para[5] = (u8)((table_wl & 0xff000000) >> 24);\n\n\tbtc->btc_fill_h2c(btc, 0x69, 6, h2c_para);\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], %s(): H2C = [%02x %02x %02x %02x %02x %02x]\\n\",\n\t\t    __func__, h2c_para[0], h2c_para[1], h2c_para[2],\n\t\t    h2c_para[3], h2c_para[4], h2c_para[5]);\n\tBTC_TRACE(trace_buf);\n}\n\nstatic void\nrtw_btc_wltoggle_tableB(IN struct btc_coexist *btc, IN boolean force_exec,\n\t\t\tIN u8 interval, IN u32 table)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu8\tcur_h2c_para[6] = {0};\n\tu8\ti, match_cnt = 0;\n\n\tcur_h2c_para[0] = 0x7;\t/* op_code, 0x7= wlan slot toggle-B*/\n\tcur_h2c_para[1] = interval;\n\tcur_h2c_para[2] = (u8)(table & 0xff);\n\tcur_h2c_para[3] = (u8)((table & 0xff00) >> 8);\n\tcur_h2c_para[4] = (u8)((table & 0xff0000) >> 16);\n\tcur_h2c_para[5] = (u8)((table & 0xff000000) >> 24);\n\n\tif (ARRAY_SIZE(coex_sta->wl_toggle_para) != 6)\n\t\treturn;\n\n\tfor (i = 0; i <= 5; i++)\n\t\tcoex_sta->wl_toggle_para[i] = cur_h2c_para[i];\n\n\tbtc->btc_fill_h2c(btc, 0x69, 6, cur_h2c_para);\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], %s(): H2C = [%02x %02x %02x %02x %02x %02x]\\n\",\n\t\t    __func__, cur_h2c_para[0], cur_h2c_para[1], cur_h2c_para[2],\n\t\t    cur_h2c_para[3], cur_h2c_para[4], cur_h2c_para[5]);\n\tBTC_TRACE(trace_buf);\n}\n\nstatic void\nrtw_btc_set_table(struct btc_coexist *btc, boolean force_exec, u32 val0x6c0,\n\t\t  u32 val0x6c4)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\n\t/* If last tdma is wl slot toggle, force write table*/\n\tif (!force_exec && coex_sta->coex_run_reason != BTC_RSN_LPS) {\n\t\tif (val0x6c0 == coex_dm->cur_val0x6c0 &&\n\t\t    val0x6c4 == coex_dm->cur_val0x6c4)\n\t\t\treturn;\n\t}\n\n\tbtc->btc_write_4byte(btc, 0x6c0, val0x6c0);\n\tbtc->btc_write_4byte(btc, 0x6c4, val0x6c4);\n\tbtc->btc_write_4byte(btc, 0x6c8, 0xf0ffffff);\n\n\tcoex_dm->cur_val0x6c0 = btc->btc_read_4byte(btc, 0x6c0);\n\tcoex_dm->cur_val0x6c4 = btc->btc_read_4byte(btc, 0x6c4);\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], %s(): 0x6c0 = %x, 0x6c4 = %x\\n\",\n\t\t    __func__, val0x6c0, val0x6c4);\n\tBTC_TRACE(trace_buf);\n}\n\nstatic void\nrtw_btc_table(struct btc_coexist *btc, boolean force_exec, u8 type)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\tu8 h2c_para[6] = {0};\n\tu32 table_wl = 0x0;\n\n\tcoex_sta->coex_table_type = type;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], ***** Coex_Table - %d *****\\n\", type);\n\tBTC_TRACE(trace_buf);\n\n\th2c_para[0] = 0xd;\n\th2c_para[1] = 0x1;\n\n\tif (btc->board_info.btdm_ant_num == 1) {\n\t\tif (type < chip_para->table_sant_num)\n\t\t\trtw_btc_set_table(btc, force_exec,\n\t\t\t\t\t  chip_para->table_sant[type].bt,\n\t\t\t\t\t  chip_para->table_sant[type].wl);\n\t} else {\n\t\ttype = type - 100;\n\t\tif (type < chip_para->table_nsant_num)\n\t\t\trtw_btc_set_table(btc, force_exec,\n\t\t\t\t\t  chip_para->table_nsant[type].bt,\n\t\t\t\t\t  chip_para->table_nsant[type].wl);\n\t}\n\n\tif (coex_sta->wl_slot_toggle_change)\n\t\trtw_btc_wltoggle_tableA(btc, FC_EXCU, type);\n}\n\nstatic void\nrtw_btc_ignore_wlan_act(struct btc_coexist *btc, boolean force_exec,\n\t\t\tboolean enable)\n{\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tu8 h2c_para[1] = {0};\n\n\tif (btc->manual_control || btc->stop_coex_dm)\n\t\treturn;\n\n\tif (!force_exec && enable == coex_dm->cur_ignore_wlan_act)\n\t\treturn;\n\n\tif (enable)\n\t\th2c_para[0] = 0x1; /* function enable */\n\n\trtw_btc_mailbox_operation(btc, 0x63, 1, h2c_para);\n\n\tcoex_dm->cur_ignore_wlan_act = enable;\n}\n\nstatic void\nrtw_btc_lps_rpwm(struct btc_coexist *btc, boolean force_exec, u8 lps_val,\n\t\t u8 rpwm_val)\n{\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\n\tif (!force_exec) {\n\t\tif (lps_val == coex_dm->cur_lps &&\n\t\t    rpwm_val == coex_dm->cur_rpwm)\n\t\t\treturn;\n\t}\n\n\tbtc->btc_set(btc, BTC_SET_U1_LPS_VAL, &lps_val);\n\tbtc->btc_set(btc, BTC_SET_U1_RPWM_VAL, &rpwm_val);\n\n\tcoex_dm->cur_lps = lps_val;\n\tcoex_dm->cur_rpwm = rpwm_val;\n}\n\nstatic boolean\nrtw_btc_power_save_state(struct btc_coexist *btc, u8 ps_type, u8 lps_val,\n\t\t\t u8 rpwm_val)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tboolean low_pwr_dis = FALSE, result = TRUE;\n\tu8 lps_mode = 0x0;\n\tu8 h2c_para[5] = {0, 0, 0, 0, 0};\n\n\tbtc->btc_get(btc, BTC_GET_U1_LPS_MODE, &lps_mode);\n\n\tswitch (ps_type) {\n\tcase BTC_PS_WIFI_NATIVE:\n\t\t/* recover to original 32k low power setting */\n\t\tcoex_sta->wl_force_lps_ctrl = FALSE;\n\t\tbtc->btc_set(btc, BTC_SET_ACT_PRE_NORMAL_LPS, NULL);\n\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): BTC_PS_WIFI_NATIVE\\n\", __func__);\n\t\tbreak;\n\tcase BTC_PS_LPS_ON:\n\t\tcoex_sta->wl_force_lps_ctrl = TRUE;\n\t\t/*set tdma off if LPS off  */\n\t\tif (!lps_mode)\n\t\t\tbtc->btc_fill_h2c(btc, 0x60, 5, h2c_para);\n\t\trtw_btc_lps_rpwm(btc, NM_EXCU, lps_val, rpwm_val);\n\t\t/* when coex force to enter LPS, do not enter 32k low power. */\n\t\tlow_pwr_dis = TRUE;\n\t\tbtc->btc_set(btc, BTC_SET_ACT_DISABLE_LOW_POWER, &low_pwr_dis);\n\t\t/* power save must executed before psTdma. */\n\t\tbtc->btc_set(btc, BTC_SET_ACT_ENTER_LPS, NULL);\n\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): BTC_PS_LPS_ON\\n\", __func__);\n\t\tbreak;\n\tcase BTC_PS_LPS_OFF:\n\t\tcoex_sta->wl_force_lps_ctrl = TRUE;\n\t\t/*set tdma off if LPS on  */\n\t\tif (lps_mode)\n\t\t\tbtc->btc_fill_h2c(btc, 0x60, 5, h2c_para);\n\t\tresult = btc->btc_set(btc, BTC_SET_ACT_LEAVE_LPS, NULL);\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): BTC_PS_LPS_OFF\\n\", __func__);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tBTC_TRACE(trace_buf);\n\treturn result;\n}\n\nstatic void\nrtw_btc_set_tdma(struct btc_coexist *btc, u8 byte1, u8 byte2, u8 byte3,\n\t\t u8 byte4, u8 byte5)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tstruct btc_wifi_link_info_ext *linfo_ext = &btc->wifi_link_info_ext;\n\tu8 ps_type = BTC_PS_WIFI_NATIVE,\n\t   real_byte1 = byte1, real_byte5 = byte5;\n\tboolean result = FALSE;\n\n\tif (byte5 & BIT(2))\n\t\tcoex_sta->tdma_bt_autoslot = TRUE;\n\telse\n\t\tcoex_sta->tdma_bt_autoslot = FALSE;\n\n\tif (linfo_ext->is_ap_mode && (byte1 & BIT(4) && !(byte1 & BIT(5)))) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): AP mode\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\treal_byte1 &= ~BIT(4);\n\t\treal_byte1 |= BIT(5);\n\n\t\treal_byte5 |= BIT(5);\n\t\treal_byte5 &= ~BIT(6);\n\n\t\tps_type = BTC_PS_WIFI_NATIVE;\n\t\trtw_btc_power_save_state(btc, ps_type, 0x0, 0x0);\n\t} else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): Force LPS (byte1 = 0x%x)\\n\",\n\t\t\t    __func__, byte1);\n\t\tBTC_TRACE(trace_buf);\n\n\t\tif (btc->chip_para->pstdma_type == BTC_PSTDMA_FORCE_LPSOFF)\n\t\t\tps_type = BTC_PS_LPS_OFF;\n\t\telse\n\t\t\tps_type = BTC_PS_LPS_ON;\n\t\tif (!rtw_btc_power_save_state(btc, ps_type, 0x50, 0x4))\n\t\t\tresult = TRUE;\n\t} else {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): native power save (byte1 = 0x%x)\\n\",\n\t\t\t    __func__, byte1);\n\t\tBTC_TRACE(trace_buf);\n\n\t\tps_type = BTC_PS_WIFI_NATIVE;\n\t\trtw_btc_power_save_state(btc, ps_type, 0x0, 0x0);\n\t}\n\n\tcoex_sta->wl_ps_state_fail = result;\n\n\tif (coex_sta->wl_ps_state_fail) {\n\t\tcoex_sta->cnt_wl[BTC_CNT_WL_PSFAIL]++;\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): Force Leave LPS Fail (cnt = %d)\\n\",\n\t\t\t    __func__, coex_sta->cnt_wl[BTC_CNT_WL_PSFAIL]);\n\t\tBTC_TRACE(trace_buf);\n\t\treturn;\n\t}\n\n\tcoex_dm->ps_tdma_para[0] = real_byte1;\n\tcoex_dm->ps_tdma_para[1] = byte2;\n\tcoex_dm->ps_tdma_para[2] = byte3;\n\tcoex_dm->ps_tdma_para[3] = byte4;\n\tcoex_dm->ps_tdma_para[4] = real_byte5;\n\n\tbtc->btc_fill_h2c(btc, 0x60, 5, coex_dm->ps_tdma_para);\n\n\t/* Always forec excute rtw_btc_set_table To avoid\n\t * coex table error if wl slot toggle mode on ->off\n\t * ex: 5508031054 next state -> rtw_btc_table + 5108031054\n\t * rtw_btc_table may be changed by 5508031054\n\t */\n\tif (real_byte1 & BIT(2)) {\n\t\tcoex_sta->wl_slot_toggle = TRUE;\n\t\tcoex_sta->wl_slot_toggle_change = FALSE;\n\t} else {\n\t\tcoex_sta->wl_slot_toggle_change = coex_sta->wl_slot_toggle;\n\t\tcoex_sta->wl_slot_toggle = FALSE;\n\t}\n\n\tif (ps_type == BTC_PS_WIFI_NATIVE)\n\t\tbtc->btc_set(btc, BTC_SET_ACT_POST_NORMAL_LPS, NULL);\n}\n\nstatic\nvoid rtw_btc_tdma(struct btc_coexist *btc, boolean force_exec, u32 tcase)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\tu8 type;\n\tboolean turn_on;\n\n\tbtc->btc_set_atomic(btc, &coex_dm->setting_tdma, TRUE);\n\t/* tcase: bit0~7 --> tdma case index\n\t *        bit8   --> for 4-slot (50ms) mode\n\t */\n\n\tif (tcase & BIT(8))/* 4-slot (50ms) mode */\n\t\trtw_btc_set_tdma_timer_base(btc, 3);\n\telse\n\t\trtw_btc_set_tdma_timer_base(btc, 0);\n\n\ttype = (u8)(tcase & 0xff);\n\tturn_on = (type == 0 || type == 100) ? FALSE : TRUE;\n\n\tif (!force_exec && turn_on == coex_dm->cur_ps_tdma_on &&\n\t    type == coex_dm->cur_ps_tdma) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], Skip TDMA because no change TDMA(%s, %d)\\n\",\n\t\t\t    (coex_dm->cur_ps_tdma_on ? \"on\" : \"off\"),\n\t\t\t    coex_dm->cur_ps_tdma);\n\t\tBTC_TRACE(trace_buf);\n\n\t\tbtc->btc_set_atomic(btc, &coex_dm->setting_tdma, FALSE);\n\t\treturn;\n\t}\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], ***** TDMA - %d *****\\n\", type);\n\tBTC_TRACE(trace_buf);\n\n\tif (turn_on) { /* enable TBTT nterrupt */\n\t\tbtc->btc_write_1byte_bitmask(btc, 0x550, BIT(3), 0x1);\n\t\tbtc->btc_write_scbd(btc, BTC_SCBD_TDMA, TRUE);\n\t} else {\n\t\tbtc->btc_write_scbd(btc, BTC_SCBD_TDMA, FALSE);\n\t}\n\n\tif (btc->board_info.btdm_ant_num == 1) {\n\t\tif (type < chip_para->tdma_sant_num)\n\t\t\trtw_btc_set_tdma(btc,\n\t\t\t\t\t chip_para->tdma_sant[type].para[0],\n\t\t\t\t\t chip_para->tdma_sant[type].para[1],\n\t\t\t\t\t chip_para->tdma_sant[type].para[2],\n\t\t\t\t\t chip_para->tdma_sant[type].para[3],\n\t\t\t\t\t chip_para->tdma_sant[type].para[4]);\n\t} else {\n\t\ttype = type - 100;\n\t\tif (type < chip_para->tdma_nsant_num)\n\t\t\trtw_btc_set_tdma(btc,\n\t\t\t\t\t chip_para->tdma_nsant[type].para[0],\n\t\t\t\t\t chip_para->tdma_nsant[type].para[1],\n\t\t\t\t\t chip_para->tdma_nsant[type].para[2],\n\t\t\t\t\t chip_para->tdma_nsant[type].para[3],\n\t\t\t\t\t chip_para->tdma_nsant[type].para[4]);\n\t}\n\n\tif (!coex_sta->wl_ps_state_fail) { /* update pre state */\n\t\tcoex_dm->cur_ps_tdma_on = turn_on;\n\t\tcoex_dm->cur_ps_tdma = type;\n\t}\n\n\tbtc->btc_set_atomic(btc, &coex_dm->setting_tdma, FALSE);\n}\n\nstatic\nvoid rtw_btc_set_ant_switch(struct btc_coexist *btc, boolean force_exec,\n\t\t\t    u8 ctrl_type, u8 pos_type)\n{\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\n\tif (!force_exec) {\n\t\tif (((ctrl_type << 8) + pos_type) == coex_dm->cur_switch_status)\n\t\t\treturn;\n\t}\n\n\tcoex_dm->cur_switch_status = (ctrl_type << 8) + pos_type;\n\n\tbtc->chip_para->chip_setup(btc, BTC_CSETUP_ANT_SWITCH);\n}\n\nstatic\nvoid rtw_btc_set_ant_path(struct btc_coexist *btc, boolean force_exec,\n\t\t\t  u8 phase)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tstruct btc_rfe_type *rfe_type = &btc->rfe_type;\n\tu8 u8tmp = 0, ctrl_type = BTC_SWITCH_CTRL_MAX,\n\t   pos_type = BTC_SWITCH_TO_MAX, cnt = 0;\n\tu32 u32tmp1 = 0;\n\tu16 u16tmp = 0;\n\n\tif (!force_exec && coex_dm->cur_ant_pos_type == phase)\n\t\treturn;\n\n\tcoex_dm->cur_ant_pos_type = phase;\n\n\t/* To avoid switch coex_ctrl_owner during BT IQK */\n\tif (rfe_type->wlg_at_btg && btc->chip_para->scbd_support &&\n\t    coex_sta->bt_iqk_state != 0xff) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], (Before Ant Setup) Delay by IQK\\n\");\n\t\tBTC_TRACE(trace_buf);\n\n\t\tbtc->btc_read_scbd(btc, &u16tmp); /* BT RFK  */\n\t\tu8tmp = btc->btc_read_1byte(btc, 0x49c); /* WL RFK */\n\t\twhile (++cnt < 12 && ((u16tmp & BIT(5)) || (u8tmp & BIT(0))))\n\t\t\tdelay_ms(50);\n\t\t/*  wait timeout */\n\t\tif (cnt >= 12)\n\t\t\tcoex_sta->bt_iqk_state = 0xff;\n\t}\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex],  coex_sta->bt_disabled = 0x%x\\n\",\n\t\t    coex_sta->bt_disabled);\n\tBTC_TRACE(trace_buf);\n\n\tswitch (phase) {\n\tcase BTC_ANT_POWERON:\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s() - PHASE_COEX_POWERON\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\t/* set Path control owner to BT at power-on step */\n\t\tif (coex_sta->bt_disabled)\n\t\t\trtw_btc_coex_ctrl_owner(btc, BTC_OWNER_WL);\n\t\telse\n\t\t\trtw_btc_coex_ctrl_owner(btc, BTC_OWNER_BT);\n\n\t\t/*Caution: Don't indirect access while power on phase   */\n\n\t\tctrl_type = BTC_SWITCH_CTRL_BY_BBSW;\n\t\tpos_type = BTC_SWITCH_TO_BT;\n\t\tbreak;\n\tcase BTC_ANT_INIT:\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s() - PHASE_COEX_INIT\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\tif (coex_sta->bt_disabled) {\n\t\t\t/* set GNT_BT to SW low */\n\t\t\trtw_btc_set_gnt_bt(btc, BTC_GNT_SW_LOW);\n\t\t\t/* set GNT_WL to SW high */\n\t\t\trtw_btc_set_gnt_wl(btc, BTC_GNT_SW_HIGH);\n\t\t} else {\n\t\t\t/* set GNT_BT to SW high */\n\t\t\trtw_btc_set_gnt_bt(btc, BTC_GNT_SW_HIGH);\n\t\t\t/* set GNT_WL to SW low */\n\t\t\trtw_btc_set_gnt_wl(btc, BTC_GNT_SW_LOW);\n\t\t}\n\n\t\t/* set Path control owner to WL at initial step */\n\t\trtw_btc_coex_ctrl_owner(btc, BTC_OWNER_WL);\n\n\t\tctrl_type = BTC_SWITCH_CTRL_BY_BBSW;\n\t\tpos_type = BTC_SWITCH_TO_BT;\n\t\tbreak;\n\tcase BTC_ANT_WONLY:\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s() - PHASE_WLANONLY_INIT\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\t/* set GNT_BT to SW Low */\n\t\trtw_btc_set_gnt_bt(btc, BTC_GNT_SW_LOW);\n\t\t/* Set GNT_WL to SW high */\n\t\trtw_btc_set_gnt_wl(btc, BTC_GNT_SW_HIGH);\n\t\t/* set Path control owner to WL at initial step */\n\t\trtw_btc_coex_ctrl_owner(btc, BTC_OWNER_WL);\n\n\t\tctrl_type = BTC_SWITCH_CTRL_BY_BBSW;\n\t\tpos_type = BTC_SWITCH_TO_WLG;\n\t\tbreak;\n\tcase BTC_ANT_WOFF:\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s() - PHASE_WLAN_OFF\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\t/* set Path control owner to BT */\n\t\trtw_btc_coex_ctrl_owner(btc, BTC_OWNER_BT);\n\n\t\tctrl_type = BTC_SWITCH_CTRL_BY_BT;\n\t\tpos_type = BTC_SWITCH_TO_NOCARE;\n\t\tbreak;\n\tcase BTC_ANT_2G:\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s() - PHASE_2G_RUNTIME\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\t/* set GNT_BT to PTA */\n\t\trtw_btc_set_gnt_bt(btc, BTC_GNT_HW_PTA);\n\t\t/* Set GNT_WL to PTA */\n\t\trtw_btc_set_gnt_wl(btc, BTC_GNT_HW_PTA);\n\n\t\t/* set Path control owner to WL at runtime step */\n\t\trtw_btc_coex_ctrl_owner(btc, BTC_OWNER_WL);\n\n\t\tctrl_type = BTC_SWITCH_CTRL_BY_PTA;\n\t\tpos_type = BTC_SWITCH_TO_NOCARE;\n\t\tbreak;\n\tcase BTC_ANT_5G:\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s() - PHASE_5G_RUNTIME\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\t/* set GNT_BT to SW Hi */\n\t\trtw_btc_set_gnt_bt(btc, BTC_GNT_HW_PTA);\n\t\t/* Set GNT_WL to SW Hi */\n\t\trtw_btc_set_gnt_wl(btc, BTC_GNT_SW_HIGH);\n\n\t\t/* set Path control owner to WL at runtime step */\n\t\trtw_btc_coex_ctrl_owner(btc, BTC_OWNER_WL);\n\n\t\tctrl_type = BTC_SWITCH_CTRL_BY_BBSW;\n\t\tpos_type = BTC_SWITCH_TO_WLA;\n\t\tbreak;\n\tcase BTC_ANT_2G_FREERUN:\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s() - PHASE_2G_FREERUN\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\t/* set GNT_BT to SW Hi */\n\t\trtw_btc_set_gnt_bt(btc, BTC_GNT_HW_PTA);\n\n\t\t/* Set GNT_WL to SW Hi */\n\t\trtw_btc_set_gnt_wl(btc, BTC_GNT_SW_HIGH);\n\n\t\t/* set Path control owner to WL at runtime step */\n\t\trtw_btc_coex_ctrl_owner(btc, BTC_OWNER_WL);\n\n\t\tctrl_type = BTC_SWITCH_CTRL_BY_BBSW;\n\t\tpos_type = BTC_SWITCH_TO_WLG_BT;\n\t\tbreak;\n\tcase BTC_ANT_2G_WLBT:\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s() - PHASE_2G_WLBT\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\t/* set GNT_BT to HW PTA */\n\t\trtw_btc_set_gnt_bt(btc, BTC_GNT_HW_PTA);\n\t\t/* Set GNT_WL to HW PTA */\n\t\trtw_btc_set_gnt_wl(btc, BTC_GNT_HW_PTA);\n\t\t/* set Path control owner to WL at runtime step */\n\t\trtw_btc_coex_ctrl_owner(btc, BTC_OWNER_WL);\n\n\t\tctrl_type = BTC_SWITCH_CTRL_BY_BBSW;\n\t\tpos_type = BTC_SWITCH_TO_WLG_BT;\n\t\tbreak;\n\tcase BTC_ANT_2G_WL:\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s() - PHASE_2G_WL\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\t/* set GNT_BT to PTA */\n\t\trtw_btc_set_gnt_bt(btc, BTC_GNT_HW_PTA);\n\t\t/* Set GNT_WL to PTA */\n\t\trtw_btc_set_gnt_wl(btc, BTC_GNT_HW_PTA);\n\t\t/* set Path control owner to WL at runtime step */\n\t\trtw_btc_coex_ctrl_owner(btc, BTC_OWNER_WL);\n\n\t\tctrl_type = BTC_SWITCH_CTRL_BY_BBSW;\n\t\tpos_type = BTC_SWITCH_TO_WLG;\n\t\tbreak;\n\tcase BTC_ANT_2G_BT:\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s() - PHASE_2G_WL\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\t/* set GNT_BT to PTA */\n\t\trtw_btc_set_gnt_bt(btc, BTC_GNT_HW_PTA);\n\t\t/* Set GNT_WL to PTA */\n\t\trtw_btc_set_gnt_wl(btc, BTC_GNT_HW_PTA);\n\t\t/* set Path control owner to WL at runtime step */\n\t\trtw_btc_coex_ctrl_owner(btc, BTC_OWNER_WL);\n\n\t\tctrl_type = BTC_SWITCH_CTRL_BY_BBSW;\n\t\tpos_type = BTC_SWITCH_TO_BT;\n\t\tbreak;\n\tcase BTC_ANT_BTMP:\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s() - PHASE_BTMP\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\t/* set GNT_BT to SW Hi */\n\t\trtw_btc_set_gnt_bt(btc, BTC_GNT_SW_HIGH);\n\t\t/* Set GNT_WL to SW Lo */\n\t\trtw_btc_set_gnt_wl(btc, BTC_GNT_SW_LOW);\n\t\t/* set Path control owner to WL */\n\t\trtw_btc_coex_ctrl_owner(btc, BTC_OWNER_WL);\n\n\t\tbtc->stop_coex_dm = TRUE;\n\n\t\tctrl_type = BTC_SWITCH_CTRL_BY_BBSW;\n\t\tpos_type = BTC_SWITCH_TO_BT;\n\t\tbreak;\n\tcase BTC_ANT_MCC:\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s() - PHASE_MCC\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\t/* set GNT_BT to PTA */\n\t\trtw_btc_set_gnt_bt(btc, BTC_GNT_HW_PTA);\n\t\t/* Set GNT_WL to PTA */\n\t\trtw_btc_set_gnt_wl(btc, BTC_GNT_HW_PTA);\n\t\t/* set Path control owner to WL at runtime step */\n\t\trtw_btc_coex_ctrl_owner(btc, BTC_OWNER_WL);\n\n\t\tctrl_type = BTC_SWITCH_CTRL_BY_FW;\n\t\tpos_type = BTC_SWITCH_TO_NOCARE;\n\t\tbreak;\n\t}\n\n\tif (ctrl_type < BTC_SWITCH_CTRL_MAX && pos_type < BTC_SWITCH_TO_MAX &&\n\t    rfe_type->ant_switch_exist)\n\t\trtw_btc_set_ant_switch(btc, force_exec, ctrl_type, pos_type);\n}\n\nstatic u8 rtw_btc_algorithm(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu8 algorithm = BTC_COEX_NOPROFILE;\n\tu8 profile_map = 0;\n\n\tif (coex_sta->bt_hfp_exist)\n\t\tprofile_map = profile_map | BTC_BTPROFILE_HFP;\n\n\tif (coex_sta->bt_hid_exist)\n\t\tprofile_map = profile_map | BTC_BTPROFILE_HID;\n\n\tif (coex_sta->bt_a2dp_exist)\n\t\tprofile_map = profile_map | BTC_BTPROFILE_A2DP;\n\n\tif (coex_sta->bt_pan_exist)\n\t\tprofile_map = profile_map | BTC_BTPROFILE_PAN;\n\n\tswitch (profile_map) {\n\tcase BTC_BTPROFILE_NONE:\n\t\talgorithm = BTC_COEX_NOPROFILE;\n\t\tbreak;\n\tcase BTC_BTPROFILE_HFP:\n\t\talgorithm = BTC_COEX_HFP;\n\t\tbreak;\n\tcase BTC_BTPROFILE_HID:\n\t\talgorithm = BTC_COEX_HID;\n\t\tbreak;\n\tcase (BTC_BTPROFILE_HID | BTC_BTPROFILE_HFP):\n\t\talgorithm = BTC_COEX_HID;\n\t\tbreak;\n\tcase BTC_BTPROFILE_A2DP:\n\t\t/* OPP may disappear during CPT_for_WiFi test */\n\t\tif (coex_sta->bt_multi_link && coex_sta->bt_hid_pair_num > 0)\n\t\t\talgorithm = BTC_COEX_A2DP_HID;\n\t\telse if (coex_sta->bt_multi_link)\n\t\t\talgorithm = BTC_COEX_A2DP_PAN;\n\t\telse\n\t\t\talgorithm = BTC_COEX_A2DP;\n\t\tbreak;\n\tcase (BTC_BTPROFILE_A2DP | BTC_BTPROFILE_HFP):\n\t\talgorithm = BTC_COEX_A2DP_HID;\n\t\tbreak;\n\tcase (BTC_BTPROFILE_A2DP | BTC_BTPROFILE_HID):\n\t\talgorithm = BTC_COEX_A2DP_HID;\n\t\tbreak;\n\tcase (BTC_BTPROFILE_A2DP | BTC_BTPROFILE_HID | BTC_BTPROFILE_HFP):\n\t\talgorithm = BTC_COEX_A2DP_HID;\n\t\tbreak;\n\tcase BTC_BTPROFILE_PAN:\n\t\talgorithm = BTC_COEX_PAN;\n\t\tbreak;\n\tcase (BTC_BTPROFILE_PAN | BTC_BTPROFILE_HFP):\n\t\talgorithm = BTC_COEX_PAN_HID;\n\t\tbreak;\n\tcase (BTC_BTPROFILE_PAN | BTC_BTPROFILE_HID):\n\t\talgorithm = BTC_COEX_PAN_HID;\n\t\tbreak;\n\tcase (BTC_BTPROFILE_PAN | BTC_BTPROFILE_HID | BTC_BTPROFILE_HFP):\n\t\talgorithm = BTC_COEX_PAN_HID;\n\t\tbreak;\n\tcase (BTC_BTPROFILE_PAN | BTC_BTPROFILE_A2DP):\n\t\talgorithm = BTC_COEX_A2DP_PAN;\n\t\tbreak;\n\tcase (BTC_BTPROFILE_PAN | BTC_BTPROFILE_A2DP | BTC_BTPROFILE_HFP):\n\t\talgorithm = BTC_COEX_A2DP_PAN_HID;\n\t\tbreak;\n\tcase (BTC_BTPROFILE_PAN | BTC_BTPROFILE_A2DP | BTC_BTPROFILE_HID):\n\t\talgorithm = BTC_COEX_A2DP_PAN_HID;\n\t\tbreak;\n\tcase BTC_BTPROFILE_MAX:\n\t\talgorithm = BTC_COEX_A2DP_PAN_HID;\n\t\tbreak;\n\t}\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], BT Profile = %s => Algorithm = %s\\n\",\n\t\t    bt_profile_string[profile_map],\n\t\t    coex_algo_string[algorithm]);\n\tBTC_TRACE(trace_buf);\n\n\treturn algorithm;\n}\n\nstatic void rtw_btc_action_coex_all_off(struct btc_coexist *btc)\n{\n\tu8 table_case, tdma_case;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\t/* To avoid  rtw_btc_set_ant_path here */\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\ttable_case = 2;\n\t\ttdma_case = 0;\n\t} else { /* Non-Shared-Ant */\n\t\ttable_case = 100;\n\t\ttdma_case = 100;\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_freerun(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tconst struct btc_chip_para *cpara = btc->chip_para;\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\tu8 level = 0, i;\n\tboolean bt_afh_loss = TRUE;\n\n\tif (btc->board_info.btdm_ant_num != 2)\n\t\treturn;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\tcoex_sta->coex_freerun = TRUE;\n\n\tfor (i = 0; i <= 8; i++) {\n\t\tif (coex_sta->bt_afh_map[i] != 0xff) {\n\t\t\tbt_afh_loss = FALSE;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (bt_afh_loss)\n\t\trtw_btc_update_wl_ch_info(btc, BTC_MEDIA_CONNECT);\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G_FREERUN);\n\n\tbtc->btc_write_scbd(btc, BTC_SCBD_FIX2M, FALSE);\n\n\t/* decrease more BT Tx power for clear case */\n\tif (BTC_RSSI_HIGH(coex_dm->wl_rssi_state[0]))\n\t\tlevel = 2;\n\telse if (BTC_RSSI_HIGH(coex_dm->wl_rssi_state[1]))\n\t\tlevel = 3;\n\telse if (BTC_RSSI_HIGH(coex_dm->wl_rssi_state[2]))\n\t\tlevel = 4;\n\telse\n\t\tlevel = 5;\n\n\tif (level > cpara->wl_rf_para_tx_num - 1)\n\t\tlevel = cpara->wl_rf_para_tx_num - 1;\n\n\tif (link_info_ext->traffic_dir == BTC_WIFI_TRAFFIC_TX)\n\t\trtw_btc_set_rf_para(btc, NM_EXCU, cpara->wl_rf_para_tx[level]);\n\telse\n\t\trtw_btc_set_rf_para(btc, NM_EXCU, cpara->wl_rf_para_rx[level]);\n\n\trtw_btc_table(btc, NM_EXCU, 100);\n\trtw_btc_tdma(btc, NM_EXCU, 100);\n}\n\nstatic void rtw_btc_action_rf4ce(struct btc_coexist *btc)\n{\n\tu8 table_case, tdma_case;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\ttable_case = 9;\n\t\ttdma_case = 16;\n\t} else { /* Non-Shared-Ant */\n\t\ttable_case = 100;\n\t\ttdma_case = 100;\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_bt_whql_test(struct btc_coexist *btc)\n{\n\tu8 table_case, tdma_case;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\ttable_case = 2;\n\t\ttdma_case = 0;\n\t} else { /* Non-Shared-Ant */\n\t\ttable_case = 100;\n\t\ttdma_case = 100;\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_bt_relink(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu8 table_case, tdma_case;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\ttable_case = 1;\n\t\ttdma_case = 0;\n\t} else { /* Non-Shared-Ant */\n\t\ttable_case = 100;\n\t\ttdma_case = 100;\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_bt_idle(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tstruct btc_rfe_type *rfe_type = &btc->rfe_type;\n\tstruct btc_wifi_link_info *link_info = &btc->wifi_link_info;\n\tu8 table_case = 0xff, tdma_case = 0xff;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tif (rfe_type->ant_switch_with_bt &&\n\t    coex_dm->bt_status == BTC_BTSTATUS_NCON_IDLE) {\n\t\tif (btc->board_info.btdm_ant_num == 1 &&\n\t\t    BTC_RSSI_HIGH(coex_dm->wl_rssi_state[1])) {\n\t\t\ttable_case = 0;\n\t\t\ttdma_case = 0;\n\t\t} else if (btc->board_info.btdm_ant_num == 2) {\n\t\t\ttable_case = 100;\n\t\t\ttdma_case = 100;\n\t\t}\n\t}\n\n\tif (table_case != 0xff && tdma_case != 0xff) {\n\t\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G_FREERUN);\n\t\trtw_btc_table(btc, NM_EXCU, table_case);\n\t\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n\t\treturn;\n\t}\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\n#ifndef PLATFORM_WINDOWS\n\tif (coex_sta->wl_noisy_level > 0) {\n\t\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\t\ttable_case = 1;\n\t\t\ttdma_case = 0;\n\t\t} else { /* Non-Shared-Ant */\n\t\t\ttable_case = 123;\n\t\t\ttdma_case = 0;\n\t\t}\n\n\t\trtw_btc_table(btc, NM_EXCU, table_case);\n\t\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n\t\treturn;\n\t}\n#endif\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\tif (!coex_sta->wl_gl_busy) {\n\t\t\ttable_case = 10;\n\t\t\ttdma_case = 3;\n\t\t} else if (coex_sta->bt_mesh) {\n\t\t\ttable_case = 26;\n\t\t\ttdma_case = 7;\n\t\t} else if (coex_dm->bt_status == BTC_BTSTATUS_NCON_IDLE) {\n\t\t\ttable_case = 6;\n\t\t\ttdma_case = 7;\n\t\t} else {\n\t\t\ttable_case = 12;\n\t\t\ttdma_case = 7;\n\t\t}\n\t} else { /* Non-Shared-Ant */\n\t\tif (!coex_sta->wl_gl_busy) {\n\t\t\ttable_case = 112;\n\t\t\ttdma_case = 104;\n\t\t} else if ((coex_sta->bt_ble_scan_type & 0x2) &&\n\t\t\t    coex_dm->bt_status == BTC_BTSTATUS_NCON_IDLE) {\n\t\t\ttable_case = 114;\n\t\t\ttdma_case = 103;\n\t\t} else {\n\t\t\ttable_case = 112;\n\t\t\ttdma_case = 103;\n\t\t}\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_bt_inquiry(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\tboolean wl_hi_pri = FALSE;\n\tu8 table_case, tdma_case;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tif (coex_sta->wl_linkscan_proc || coex_sta->wl_hi_pri_task1 ||\n\t    coex_sta->wl_hi_pri_task2 || coex_sta->wl_gl_busy)\n\t\twl_hi_pri = TRUE;\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\tif (wl_hi_pri) {\n\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], bt inq/page +  wifi hi-pri task\\n\");\n\n\t\t\ttable_case = 15;\n\n\t\t\tif (coex_sta->bt_a2dp_exist && !coex_sta->bt_pan_exist)\n\t\t\t\ttdma_case = 11;\n\t\t\telse if (coex_sta->wl_hi_pri_task1)\n\t\t\t\ttdma_case = 6;\n\t\t\telse if (!coex_sta->bt_page)\n\t\t\t\ttdma_case = 8;\n\t\t\telse\n\t\t\t\ttdma_case = 9;\n\t\t} else if (link_info_ext->is_connected) {\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], bt inq/page +  wifi connected\\n\");\n\n\t\t\ttable_case = 10;\n\t\t\ttdma_case = 10;\n\t\t} else {\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], bt inq/page +  wifi not-connected\\n\");\n\n\t\t\ttable_case = 1;\n\t\t\ttdma_case = 0;\n\t\t}\n\t} else { /* Non_Shared-Ant */\n\t\tif (wl_hi_pri) {\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], bt inq/page +  wifi hi-pri task\\n\");\n\n\t\t\ttable_case = 113;\n\n\t\t\tif (coex_sta->bt_a2dp_exist && !coex_sta->bt_pan_exist)\n\t\t\t\ttdma_case = 111;\n\t\t\telse if (coex_sta->wl_hi_pri_task1)\n\t\t\t\ttdma_case = 106;\n\t\t\telse if (!coex_sta->bt_page)\n\t\t\t\ttdma_case = 108;\n\t\t\telse\n\t\t\t\ttdma_case = 109;\n\t\t} else if (link_info_ext->is_connected) {\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], bt inq/page +  wifi connected\\n\");\n\n\t\t\ttable_case = 101;\n\t\t\ttdma_case = 100;\n\t\t} else {\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], bt inq/page +  wifi not-connected\\n\");\n\n\t\t\ttable_case = 101;\n\t\t\ttdma_case = 100;\n\t\t}\n\t}\n\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_bt_mr(struct btc_coexist *btc)\n{\n\tstruct btc_rfe_type *rfe_type = &btc->rfe_type;\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\tu8 table_case, tdma_case;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\tif (rfe_type->ant_switch_with_bt)\n\t\t\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G_FREERUN);\n\t\telse\n\t\t\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\n\t\ttable_case = 0;\n\t\ttdma_case = 0;\n\t} else { /* Non-Shared-Ant */\n\t\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\n\t\ttable_case = 100;\n\t\ttdma_case = 100;\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_bt_hfp(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu8 table_case, tdma_case;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\tif (coex_sta->bt_multi_link) {\n\t\t\ttable_case = 10;\n\t\t\ttdma_case = 17;\n\t\t} else {\n\t\t\ttable_case = 10;\n\t\t\ttdma_case = 5;\n\t\t}\n\t} else { /* Non-Shared-Ant */\n\t\tif (coex_sta->bt_multi_link) {\n\t\t\ttable_case = 112;\n\t\t\ttdma_case = 117;\n\t\t} else {\n\t\t\ttable_case = 105;\n\t\t\ttdma_case = 100;\n\t\t}\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_bt_hid(struct btc_coexist *btc)\n{\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu8 table_case, tdma_case;\n\tboolean is_toggle_table = FALSE;\n\tu32 slot_type = 0;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\tif (coex_sta->bt_ble_exist) { /* RCU */\n\t\t\tif (coex_sta->cnt_wl[BTC_CNT_WL_SCANAP] > 5) {\n\t\t\t\ttable_case = 26;\n\t\t\t\ttdma_case = 2;\n\t\t\t} else {\n\t\t\t\ttable_case = 27;\n\t\t\t\ttdma_case = 9;\n\t\t\t}\n\t\t} else { /* Legacy HID  */\n\t\t\tif (coex_sta->bt_a2dp_active) {\n\t\t\t\ttable_case = 9;\n\t\t\t\ttdma_case = 18;\n\t\t\t} else if (coex_sta->bt_418_hid_exist &&\n\t\t\t\t   coex_sta->wl_gl_busy) {\n\t\t\t\tis_toggle_table = TRUE;\n\t\t\t\tslot_type = BIT(8);\n\t\t\t\ttable_case = 9;\n\t\t\t\ttdma_case = 24;\n\t\t\t} else {\n\t\t\t\ttable_case = 9;\n\t\t\t\ttdma_case = 9;\n\t\t\t}\n\t\t}\n\t} else { /* Non-Shared-Ant */\n\t\tif (coex_sta->bt_ble_exist) { /* BLE */\n\t\t\tif (coex_sta->cnt_wl[BTC_CNT_WL_SCANAP] > 5) {\n\t\t\t\ttable_case = 121;\n\t\t\t\ttdma_case = 102;\n\t\t\t} else {\n\t\t\t\ttable_case = 122;\n\t\t\t\ttdma_case = 109;\n\t\t\t}\n\t\t} else if (coex_sta->bt_a2dp_active) {\n\t\t\ttable_case = 113;\n\t\t\ttdma_case = 118;\n\t\t} else {\n\t\t\ttable_case = 113;\n\t\t\ttdma_case = 104;\n\t\t}\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\tif (is_toggle_table) {\n\t\trtw_btc_wltoggle_tableA(btc, FC_EXCU, table_case);\n\t\trtw_btc_wltoggle_tableB(btc, NM_EXCU, 1, 0x5a5a5aaa);\n\t}\n\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case | slot_type);\n}\n\nstatic void rtw_btc_action_bt_a2dp(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tu8 table_case, tdma_case;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\tif (coex_sta->wl_gl_busy && coex_sta->wl_noisy_level == 0)\n\t\t\ttable_case = 12;\n\t\telse\n\t\t\ttable_case = 9;\n\n\t\tif (coex_sta->wl_connecting || !coex_sta->wl_gl_busy)\n\t\t\ttdma_case = 14;\n\t\telse\n\t\t\ttdma_case = 13;\n\t} else { /* Non-Shared-Ant */\n\t\ttable_case = 112;\n\n\t\tif (BTC_RSSI_HIGH(coex_dm->wl_rssi_state[1]))\n\t\t\ttdma_case = 112;\n\t\telse\n\t\t\ttdma_case = 113;\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_bt_a2dpsink(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tstruct btc_wifi_link_info_ext *linfo_ext = &btc->wifi_link_info_ext;\n\tu8 table_case, tdma_case;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\tif (linfo_ext->is_ap_mode) {\n\t\t\ttable_case = 2;\n\t\t\ttdma_case = 0;\n\t\t} else if (coex_sta->wl_gl_busy) {\n\t\t\ttable_case = 28;\n\t\t\ttdma_case = 20;\n\t\t} else {\n\t\t\ttable_case = 28;\n\t\t\ttdma_case = 26;\n\t\t}\n\t} else { /* Non-Shared-Ant */\n\t\tif (linfo_ext->is_ap_mode) {\n\t\t\ttable_case = 100;\n\t\t\ttdma_case = 100;\n\t\t} else {\n\t\t\ttable_case = 119;\n\t\t\ttdma_case = 120;\n\t\t}\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_bt_pan(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu8 table_case, tdma_case;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\tif (coex_sta->wl_gl_busy && coex_sta->wl_noisy_level == 0)\n\t\t\ttable_case = 14;\n\t\telse\n\t\t\ttable_case = 10;\n\n\t\tif (coex_sta->wl_gl_busy)\n\t\t\ttdma_case = 17;\n\t\telse\n\t\t\ttdma_case = 19;\n\t} else { /* Non-Shared-Ant */\n\t\ttable_case = 112;\n\n\t\tif (coex_sta->wl_gl_busy)\n\t\t\ttdma_case = 117;\n\t\telse\n\t\t\ttdma_case = 119;\n\t}\n\n\tif (coex_sta->bt_slave && coex_sta->wl_gl_busy)\n\t\trtw_btc_set_bt_golden_rx_range(btc, NM_EXCU, 3, 20);\n\telse\n\t\trtw_btc_set_bt_golden_rx_range(btc, NM_EXCU, 3, 0);\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_bt_a2dp_hid(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\tu8 table_case, tdma_case;\n\tboolean is_toggle_table = FALSE;\n\tu32 slot_type = 0;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\tif (coex_sta->bt_ble_exist)\n\t\t\ttable_case = 26; /* for RCU */\n\t\telse\n\t\t\ttable_case = 9;\n\n\t\tif (coex_sta->wl_connecting || !coex_sta->wl_gl_busy) {\n\t\t\ttdma_case = 14;\n\t\t} else if (coex_sta->bt_418_hid_exist && coex_sta->wl_gl_busy) {\n\t\t\tis_toggle_table = TRUE;\n\t\t\tslot_type = BIT(8);\n\t\t\ttdma_case = 23;\n\t\t} else {\n\t\t\ttdma_case = 13;\n\t\t}\n\t} else { /* Non-Shared-Ant */\n\t\tif (coex_sta->bt_ble_exist)\n\t\t\ttable_case = 121;\n\t\telse\n\t\t\ttable_case = 113;\n\n\t\tif (BTC_RSSI_HIGH(coex_dm->wl_rssi_state[1]))\n\t\t\ttdma_case = 112;\n\t\telse\n\t\t\ttdma_case = 113;\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\tif (is_toggle_table) {\n\t\trtw_btc_wltoggle_tableA(btc, FC_EXCU, table_case);\n\t\trtw_btc_wltoggle_tableB(btc, NM_EXCU, 1, 0x5a5a5aaa);\n\t}\n\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case | slot_type);\n}\n\nstatic void rtw_btc_action_bt_a2dp_pan(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\tu8 table_case, tdma_case;\n\tboolean wl_cpt_test = FALSE, bt_cpt_test = FALSE;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\tif (btc->board_info.customer_id == RT_CID_LENOVO_CHINA &&\n\t    coex_sta->cnt_wl[BTC_CNT_WL_SCANAP] <= 10 &&\n\t    coex_sta->wl_iot_peer == BTC_IOT_PEER_ATHEROS) {\n\t\tif (BTC_RSSI_LOW(coex_dm->wl_rssi_state[2]))\n\t\t\twl_cpt_test = TRUE;\n\t\telse\n\t\t\tbt_cpt_test = TRUE;\n\t}\n\n\tif (wl_cpt_test)\n\t\trtw_btc_set_rf_para(btc, NM_EXCU, chip_para->wl_rf_para_rx[1]);\n\telse\n\t\trtw_btc_set_rf_para(btc, NM_EXCU, chip_para->wl_rf_para_rx[0]);\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\tif (wl_cpt_test) {\n\t\t\tif (coex_sta->wl_gl_busy) {\n\t\t\t\ttable_case = 20;\n\t\t\t\ttdma_case = 17;\n\t\t\t} else {\n\t\t\t\ttable_case = 10;\n\t\t\t\ttdma_case = 15;\n\t\t\t}\n\t\t} else if (bt_cpt_test) {\n\t\t\ttable_case = 10;\n\t\t\ttdma_case = 15;\n\t\t} else {\n\t\t\tif (coex_sta->wl_gl_busy &&\n\t\t\t    coex_sta->wl_noisy_level == 0)\n\t\t\t\ttable_case = 14;\n\t\t\telse\n\t\t\t\ttable_case = 10;\n\n\t\t\tif (coex_sta->wl_gl_busy)\n\t\t\t\ttdma_case = 15;\n\t\t\telse\n\t\t\t\ttdma_case = 20;\n\t\t}\n\t} else { /* Non-Shared-Ant */\n\t\ttable_case = 112;\n\n\t\tif (coex_sta->wl_gl_busy)\n\t\t\ttdma_case = 115;\n\t\telse\n\t\t\ttdma_case = 120;\n\t}\n\n\tif (coex_sta->bt_slave)\n\t\trtw_btc_set_extend_btautoslot(btc, 0x3c);\n\telse\n\t\trtw_btc_set_extend_btautoslot(btc, 0x32);\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_bt_pan_hid(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu8 table_case, tdma_case;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\ttable_case = 9;\n\n\t\tif (coex_sta->wl_gl_busy)\n\t\t\ttdma_case = 18;\n\t\telse\n\t\t\ttdma_case = 19;\n\t} else { /* Non-Shared-Ant */\n\t\ttable_case = 113;\n\n\t\tif (coex_sta->wl_gl_busy)\n\t\t\ttdma_case = 117;\n\t\telse\n\t\t\ttdma_case = 119;\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_bt_a2dp_pan_hid(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu8 table_case, tdma_case;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\ttable_case = 10;\n\n\t\tif (coex_sta->wl_gl_busy)\n\t\t\ttdma_case = 15;\n\t\telse\n\t\t\ttdma_case = 20;\n\t} else { /* Non-Shared-Ant */\n\t\ttable_case = 113;\n\n\t\tif (coex_sta->wl_gl_busy)\n\t\t\ttdma_case = 115;\n\t\telse\n\t\t\ttdma_case = 120;\n\t}\n\n\tif (coex_sta->bt_slave)\n\t\trtw_btc_set_extend_btautoslot(btc, 0x3c);\n\telse\n\t\trtw_btc_set_extend_btautoslot(btc, 0x32);\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_wl_under5g(struct btc_coexist *btc)\n{\n\tu8 table_case, tdma_case;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_ant_path(btc, FC_EXCU, BTC_ANT_5G);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tbtc->btc_write_scbd(btc, BTC_SCBD_FIX2M, FALSE);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\ttable_case = 0;\n\t\ttdma_case = 0;\n\t} else { /* Non-Shared-Ant */\n\t\ttable_case = 100;\n\t\ttdma_case = 100;\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_wl_only(struct btc_coexist *btc)\n{\n\tu8 table_case, tdma_case;\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\ttable_case = 2;\n\t\ttdma_case = 0;\n\t} else { /* Non-Shared-Ant */\n\t\ttable_case = 100;\n\t\ttdma_case = 100;\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_wl_native_lps(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\tu8 table_case, tdma_case;\n\n\tif (link_info_ext->is_all_under_5g)\n\t\treturn;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\ttable_case = 28; /*0x6c0 for A2DP, 0x6c4 for non-A2DP*/\n\t\ttdma_case = 0;\n\t} else { /* Non-Shared-Ant */\n\t\ttable_case = 100;\n\t\ttdma_case = 100;\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_wl_linkscan(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu8 table_case, tdma_case;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\tif (coex_sta->bt_a2dp_exist) {\n\t\t\ttable_case = 9;\n\t\t\ttdma_case = 11;\n\t\t} else {\n\t\t\ttable_case = 9;\n\t\t\ttdma_case = 7;\n\t\t}\n\t} else { /* Non-Shared-Ant */\n\t\tif (coex_sta->bt_a2dp_exist) {\n\t\t\ttable_case = 112;\n\t\t\ttdma_case = 111;\n\t\t} else {\n\t\t\ttable_case = 112;\n\t\t\ttdma_case = 107;\n\t\t}\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_wl_not_connected(struct btc_coexist *btc)\n{\n\tu8 table_case, tdma_case;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\ttable_case = 2;\n\t\ttdma_case = 0;\n\t} else { /* Non-Shared-Ant */\n\t\ttable_case = 100;\n\t\ttdma_case = 100;\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_wl_connected(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu8 algorithm;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\talgorithm = rtw_btc_algorithm(btc);\n\n\tswitch (algorithm) {\n\tcase BTC_COEX_HFP:\n\t\trtw_btc_action_bt_hfp(btc);\n\t\tbreak;\n\tcase BTC_COEX_HID:\n\t\tif (rtw_btc_freerun_check(btc))\n\t\t\trtw_btc_action_freerun(btc);\n\t\telse\n\t\t\trtw_btc_action_bt_hid(btc);\n\t\tbreak;\n\tcase BTC_COEX_A2DP:\n\t\tif (rtw_btc_freerun_check(btc))\n\t\t\trtw_btc_action_freerun(btc);\n\t\telse if (coex_sta->bt_a2dp_sink)\n\t\t\trtw_btc_action_bt_a2dpsink(btc);\n\t\telse\n\t\t\trtw_btc_action_bt_a2dp(btc);\n\t\tbreak;\n\tcase BTC_COEX_PAN:\n\t\trtw_btc_action_bt_pan(btc);\n\t\tbreak;\n\tcase BTC_COEX_A2DP_HID:\n\t\tif (rtw_btc_freerun_check(btc))\n\t\t\trtw_btc_action_freerun(btc);\n\t\telse\n\t\t\trtw_btc_action_bt_a2dp_hid(btc);\n\t\tbreak;\n\tcase BTC_COEX_A2DP_PAN:\n\t\trtw_btc_action_bt_a2dp_pan(btc);\n\t\tbreak;\n\tcase BTC_COEX_PAN_HID:\n\t\trtw_btc_action_bt_pan_hid(btc);\n\t\tbreak;\n\tcase BTC_COEX_A2DP_PAN_HID:\n\t\trtw_btc_action_bt_a2dp_pan_hid(btc);\n\t\tbreak;\n\tdefault:\n\tcase BTC_COEX_NOPROFILE:\n\t\trtw_btc_action_bt_idle(btc);\n\t\tbreak;\n\t}\n}\n\nstatic void rtw_btc_action_wl_mcc25g(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu8 table_case, tdma_case;\n\n\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_MCC);\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\tbtc->btc_write_scbd(btc, BTC_SCBD_FIX2M, FALSE);\n\n\tif (btc->board_info.btdm_ant_num == 1) { /* Shared-Ant */\n\t\tif (coex_sta->bt_setup_link) {\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], %s(): BT Relink\\n\", __func__);\n\n\t\t\ttable_case = 24;\n\t\t\ttdma_case = 0;\n\t\t} else if (coex_sta->bt_inq_page) {\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], %s(): BT Inq-Pag\\n\", __func__);\n\n\t\t\ttable_case = 23;\n\t\t\ttdma_case = 0;\n\t\t} else {\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], %s(): BT on\\n\", __func__);\n\n\t\t\tif (coex_sta->bt_418_hid_exist)\n\t\t\t\ttable_case = 25;\n\t\t\telse\n\t\t\t\ttable_case = 23;\n\t\t\ttdma_case = 0;\n\t\t}\n\t} else { /* Non-Shared-Ant */\n\t\tif (coex_sta->bt_setup_link) {\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], %s(): BT Relink\\n\", __func__);\n\n\t\t\ttable_case = 100;\n\t\t\ttdma_case = 100;\n\t\t} else if (coex_sta->bt_inq_page) {\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], %s(): BT Inq-Pag\\n\", __func__);\n\n\t\t\ttable_case = 118;\n\t\t\ttdma_case = 100;\n\t\t} else {\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], %s(): BT on!!\\n\", __func__);\n\n\t\t\ttable_case = 118;\n\t\t\ttdma_case = 100;\n\t\t}\n\t}\n\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n}\n\nstatic void rtw_btc_action_wl_scc2g(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu8 table_case = 0xff, tdma_case = 0xff;\n\tboolean is_toggle_table = FALSE;\n\tu32 slot_type = 0;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\tif (coex_sta->bt_profile_num == 1) {\n\t\tif (coex_sta->bt_hid_exist || coex_sta->bt_hfp_exist) {\n\t\t\tif (coex_sta->bt_a2dp_active) {\n\t\t\t\ttable_case = 9;\n\t\t\t\ttdma_case = 21;\n\t\t\t} else if (coex_sta->bt_418_hid_exist) {\n\t\t\t\ttable_case = 10;\n\t\t\t\ttdma_case = 24;\n\t\t\t\tis_toggle_table = TRUE;\n\t\t\t\tslot_type = BIT(8);\n\t\t\t} else {\n\t\t\t\ttable_case = 2;\n\t\t\t\ttdma_case = 0;\n\t\t\t}\n\t\t} else if (coex_sta->bt_a2dp_exist) {\n\t\t\ttable_case = 10;\n\t\t\ttdma_case = 22;\n\t\t\tslot_type = BIT(8);\n\t\t} else { /* PAN or OPP */\n\t\t\ttable_case = 10;\n\t\t\ttdma_case = 21;\n\t\t}\n\t} else {\n\t\tif ((coex_sta->bt_hid_exist || coex_sta->bt_hfp_exist) &&\n\t\t    coex_sta->bt_a2dp_exist) {\n\t\t\ttable_case = 9;\n\t\t\ttdma_case = 22;\n\n\t\t\tslot_type = BIT(8);\n\t\t\tif (coex_sta->bt_418_hid_exist)\n\t\t\t\tis_toggle_table = TRUE;\n\t\t} else if (coex_sta->bt_pan_exist && coex_sta->bt_a2dp_exist) {\n\t\t\ttable_case = 10;\n\t\t\ttdma_case = 22;\n\t\t\tslot_type = BIT(8);\n\t\t} else { /* hid + pan */\n\t\t\ttable_case = 9;\n\t\t\ttdma_case = 21;\n\t\t}\n\t}\n\n\trtw_btc_table(btc, NM_EXCU, table_case);\n\tif (is_toggle_table) {\n\t\trtw_btc_wltoggle_tableA(btc, FC_EXCU, table_case);\n\t\trtw_btc_wltoggle_tableB(btc, NM_EXCU, 1, 0x5a5a5aaa);\n\t}\n\n\trtw_btc_tdma(btc, NM_EXCU, tdma_case | slot_type);\n}\n\nstatic void rtw_btc_action_wl_p2p2g(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_rfe_type *rfe_type = &btc->rfe_type;\n\tstruct btc_wifi_link_info *link_info = &btc->wifi_link_info;\n\tu8 table_case = 0xff, tdma_case = 0xff, ant_phase;\n\n\tif (rfe_type->ant_switch_with_bt)\n\t\tant_phase = BTC_ANT_2G_FREERUN;\n\telse\n\t\tant_phase = BTC_ANT_2G;\n\n\trtw_btc_set_rf_para(btc, NM_EXCU, btc->chip_para->wl_rf_para_rx[0]);\n\tbtc->btc_write_scbd(btc, BTC_SCBD_FIX2M, FALSE);\n\n\tif (btc->board_info.btdm_ant_num == 2) { /* Non-Shared-Ant */\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): Non_Shared_Ant!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\trtw_btc_action_freerun(btc);\n\t\treturn;\n\t}\n\n\t/* Shared-Ant */\n\tif (coex_sta->bt_disabled) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): BT Disable!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\n\t\ttable_case = 0;\n\t\ttdma_case = 0;\n\t} else if (coex_sta->bt_setup_link) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): BT Relink!!\\n\", __func__);\n\n\t\trtw_btc_set_ant_path(btc, NM_EXCU, ant_phase);\n\n\t\ttable_case = 1;\n\t\ttdma_case = 0;\n\t} else if (coex_sta->bt_inq_page) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): BT Inq-Page!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\trtw_btc_set_ant_path(btc, NM_EXCU, ant_phase);\n\n\t\ttable_case = 15;\n\t\ttdma_case = 2;\n\t} else if (coex_sta->bt_profile_num == 0) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): BT idle!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\trtw_btc_set_ant_path(btc, NM_EXCU, ant_phase);\n\n\t\ttable_case = 2;\n\t\ttdma_case = 0;\n\t} else if (coex_sta->wl_linkscan_proc) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): WL scan!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\trtw_btc_action_wl_linkscan(btc);\n\t} else {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): BT busy!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\tswitch (link_info->link_mode) {\n\t\tcase BTC_LINK_2G_SCC_GC_STA:\n\t\tcase BTC_LINK_2G_SCC_GO_STA:\n\t\t\trtw_btc_set_ant_path(btc, NM_EXCU, BTC_ANT_2G);\n\t\t\trtw_btc_action_wl_scc2g(btc);\n\t\t\tbreak;\n#if 0\n\t\tcase BTC_LINK_ONLY_GO:\n\t\t\trtw_btc_set_ant_path(btc, NM_EXCU, ant_phase);\n\t\t\ttable_case = 7;\n\t\t\ttdma_case = 0;\n\t\t\tbreak;\n\t\tcase BTC_LINK_ONLY_GC:\n\t\t\trtw_btc_set_ant_path(btc, NM_EXCU, ant_phase);\n\t\t\tif (coex_sta->bt_418_hid_exist)\n\t\t\t\ttable_case = 6;\n\t\t\telse\n\t\t\t\ttable_case = 8;\n\t\t\ttdma_case = 0;\n\t\t\tbreak;\n#endif\n\t\tdefault:\n\t\t\trtw_btc_set_ant_path(btc, NM_EXCU, ant_phase);\n\t\t\ttable_case = 2;\n\t\t\ttdma_case = 0;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (table_case != 0xff && tdma_case != 0xff) {\n\t\trtw_btc_table(btc, NM_EXCU, table_case);\n\t\trtw_btc_tdma(btc, NM_EXCU, tdma_case);\n\t}\n}\n\nstatic void rtw_btc_run_coex(struct btc_coexist *btc, u8 reason)\n{\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\tstruct btc_wifi_link_info *link_info = &btc->wifi_link_info;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], %s(): reason = %d\\n\", __func__, reason);\n\tBTC_TRACE(trace_buf);\n\n\tcoex_sta->coex_run_reason = reason;\n\n\t/* update wifi_link_info_ext variable */\n\trtw_btc_update_wl_link_info(btc, reason);\n\n\trtw_btc_monitor_bt_enable(btc);\n\n\tif (coex_sta->wl_linkscan_proc ||\n\t    coex_sta->wl_hi_pri_task1 ||\n\t    coex_sta->wl_hi_pri_task2 || coex_sta->wl_gl_busy)\n\t\tbtc->btc_write_scbd(btc, BTC_SCBD_SCAN, TRUE);\n\telse\n\t\tbtc->btc_write_scbd(btc, BTC_SCBD_SCAN, FALSE);\n\n\tif (btc->manual_control) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], return for Manual CTRL!!\\n\");\n\t\tBTC_TRACE(trace_buf);\n\t\treturn;\n\t}\n\n\tif (btc->stop_coex_dm) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], return for Stop Coex DM!!\\n\");\n\t\tBTC_TRACE(trace_buf);\n\t\treturn;\n\t}\n\n\tif (coex_sta->wl_under_ips) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], return for wifi is under IPS!!\\n\");\n\t\tBTC_TRACE(trace_buf);\n\t\treturn;\n\t}\n\n\tif (coex_sta->wl_under_lps && link_info_ext->is_32k) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], return for wifi is under LPS-32K!!\\n\");\n\t\tBTC_TRACE(trace_buf);\n\t\treturn;\n\t}\n\n\tif (coex_sta->coex_freeze && !coex_sta->bt_setup_link) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], return for coex_freeze!!\\n\");\n\t\tBTC_TRACE(trace_buf);\n\t\treturn;\n\t}\n\n\tcoex_sta->cnt_wl[BTC_CNT_WL_COEXRUN]++;\n\tcoex_sta->coex_freerun = FALSE;\n\n\t/* Pure-5G Coex Process */\n\tif (link_info_ext->is_all_under_5g) {\n\t\tcoex_sta->wl_coex_mode = BTC_WLINK_5G;\n\t\trtw_btc_action_wl_under5g(btc);\n\t\tgoto exit;\n\t}\n\n\tif (coex_sta->bt_msft_mr_exist && link_info_ext->is_connected) {\n\t\tcoex_sta->wl_coex_mode = BTC_WLINK_BTMR;\n\t\trtw_btc_action_bt_mr(btc);\n\t\tgoto exit;\n\t}\n\n\tif (link_info_ext->is_mcc_25g) {\n\t\tcoex_sta->wl_coex_mode = BTC_WLINK_25GMPORT;\n\t\trtw_btc_action_wl_mcc25g(btc);\n\t\tgoto exit;\n\t}\n\n\t/* if multi-port, P2P-GO, P2P-GC  */\n\tif (link_info_ext->num_of_active_port > 1 ||\n\t    (link_info->link_mode == BTC_LINK_ONLY_GO &&\n\t     !link_info_ext->is_ap_mode) ||\n\t     link_info->link_mode == BTC_LINK_ONLY_GC) {\n\t\tif (link_info->link_mode == BTC_LINK_ONLY_GO)\n\t\t\tcoex_sta->wl_coex_mode = BTC_WLINK_2GGO;\n\t\telse if (link_info->link_mode == BTC_LINK_ONLY_GC)\n\t\t\tcoex_sta->wl_coex_mode = BTC_WLINK_2GGC;\n\t\telse\n\t\t\tcoex_sta->wl_coex_mode = BTC_WLINK_2GMPORT;\n\t\trtw_btc_action_wl_p2p2g(btc);\n\t\tgoto exit;\n\t}\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], WiFi is single-port 2G!!\\n\");\n\tBTC_TRACE(trace_buf);\n\n\tcoex_sta->wl_coex_mode = BTC_WLINK_2G1PORT;\n\n\tbtc->btc_write_scbd(btc, BTC_SCBD_FIX2M, FALSE);\n\n\tif (coex_sta->bt_disabled) {\n\t\tif (link_info_ext->is_connected && coex_sta->rf4ce_en)\n\t\t\trtw_btc_action_rf4ce(btc);\n\t\telse if (!link_info_ext->is_connected)\n\t\t\trtw_btc_action_wl_not_connected(btc);\n\t\telse\n\t\t\trtw_btc_action_wl_only(btc);\n\t\tgoto exit;\n\t}\n\n\tif (coex_sta->wl_under_lps && !coex_sta->wl_force_lps_ctrl) {\n\t\trtw_btc_action_wl_native_lps(btc);\n\t\tgoto exit;\n\t}\n\n\tif (coex_sta->bt_whck_test) {\n\t\trtw_btc_action_bt_whql_test(btc);\n\t\tgoto exit;\n\t}\n\n\tif (coex_sta->bt_setup_link) {\n\t\trtw_btc_action_bt_relink(btc);\n\t\tgoto exit;\n\t}\n\n\tif (coex_sta->bt_inq_page) {\n\t\trtw_btc_action_bt_inquiry(btc);\n\t\tgoto exit;\n\t}\n\n\tif ((coex_dm->bt_status == BTC_BTSTATUS_NCON_IDLE ||\n\t     coex_dm->bt_status == BTC_BTSTATUS_CON_IDLE) &&\n\t     link_info_ext->is_connected) {\n\t\trtw_btc_action_bt_idle(btc);\n\t\tgoto exit;\n\t}\n\n\tif (coex_sta->wl_linkscan_proc && !coex_sta->coex_freerun) {\n\t\trtw_btc_action_wl_linkscan(btc);\n\t\tgoto exit;\n\t}\n\n\tif (link_info_ext->is_connected) {\n\t\trtw_btc_action_wl_connected(btc);\n\t\tgoto exit;\n\t} else {\n\t\trtw_btc_action_wl_not_connected(btc);\n\t\tgoto exit;\n\t}\n\nexit:\n\t/* No MIMO Power Save, 3:disable */\n\tif (coex_sta->wl_coex_mode == BTC_WLINK_BTMR)\n\t\trtw_btc_mimo_ps(btc, NM_EXCU, 3);\n\telse\n\t\trtw_btc_mimo_ps(btc, NM_EXCU, 0);\n\n\trtw_btc_gnt_workaround(btc, NM_EXCU, coex_sta->wl_coex_mode);\n\trtw_btc_limited_wl(btc);\n}\n\nstatic void rtw_btc_init_coex_var(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\tu8 i;\n\n\t/* Reset Coex variable */\n\tbtc->btc_set(btc, BTC_SET_RESET_COEX_VAR, NULL);\n\n\t/* Init Coex variables that are not zero */\n\tfor (i = 0; i < ARRAY_SIZE(coex_dm->bt_rssi_state); i++)\n\t\tcoex_dm->bt_rssi_state[i] = BTC_RSSI_STATE_LOW;\n\n\tfor (i = 0; i < ARRAY_SIZE(coex_dm->wl_rssi_state); i++)\n\t\tcoex_dm->wl_rssi_state[i] = BTC_RSSI_STATE_LOW;\n\n\tfor (i = 0; i < ARRAY_SIZE(coex_sta->bt_sut_pwr_lvl); i++)\n\t\tcoex_sta->bt_sut_pwr_lvl[i] = 0xff;\n\n\tcoex_sta->bt_reg_vendor_ac = 0xffff;\n\tcoex_sta->bt_reg_vendor_ae = 0xffff;\n\n\tcoex_sta->gnt_workaround_state = BTC_WLINK_MAX;\n\tbtc->bt_info.bt_get_fw_ver = 0;\n}\n\nstatic void rtw_btc_init_coex_dm(struct btc_coexist *btc)\n{\n}\n\nstatic void\nrtw_btc_init_hw_config(struct btc_coexist *btc, boolean wifi_only)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu32 u32tmp1 = 0, u32tmp2 = 0;\n\tu8 table_case = 1, tdma_case = 0;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\t/* init coex_dm, coex_sta variable to sync with chip status */\n\trtw_btc_init_coex_var(btc);\n\n\t/* 0xf0[15:12] --> chip kt info */\n\tcoex_sta->kt_ver = (btc->btc_read_1byte(btc, 0xf1) & 0xf0) >> 4;\n\n\trtw_btc_monitor_bt_enable(btc);\n\n\t/* Setup RF front end type */\n\tbtc->chip_para->chip_setup(btc, BTC_CSETUP_RFE_TYPE);\n\n\t/* Init coex relared register  */\n\tbtc->chip_para->chip_setup(btc, BTC_CSETUP_INIT_HW);\n\n\t/* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */\n\trtw_btc_set_wl_pri_mask(btc, BTC_WLPRI_TX_RSP, 1);\n\n\t/* set Tx beacon = Hi-Pri  */\n\trtw_btc_set_wl_pri_mask(btc, BTC_WLPRI_TX_BEACON, 1);\n\n\t/* set Tx beacon queue = Hi-Pri  */\n\trtw_btc_set_wl_pri_mask(btc, BTC_WLPRI_TX_BEACONQ, 1);\n#if 0\n\t/* coex-276  P2P-Go beacon request can't release issue\n\t * Only PCIe can set 0x454[6] = 1 to solve this issue,\n\t * WL SDIO/USB interface need driver support.\n\t */\n\tif (btc->chip_interface == BTC_INTF_PCI)\n\t\tbtc->btc_write_1byte_bitmask(btc, 0x454, BIT(6), 0x1);\n#endif\n\n\t/* Antenna config */\n\tif (btc->wl_rf_state_off) {\n\t\trtw_btc_set_ant_path(btc, FC_EXCU, BTC_ANT_WOFF);\n\t\tbtc->btc_write_scbd(btc, BTC_SCBD_ALL, FALSE);\n\t\tbtc->stop_coex_dm = TRUE;\n\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): RF Off\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t} else if (wifi_only) {\n\t\trtw_btc_set_ant_path(btc, FC_EXCU, BTC_ANT_WONLY);\n\t\tbtc->btc_write_scbd(btc, BTC_SCBD_ACTIVE | BTC_SCBD_ON, TRUE);\n\t\tbtc->stop_coex_dm = TRUE;\n\t} else {\n\t\trtw_btc_set_ant_path(btc, FC_EXCU, BTC_ANT_INIT);\n\t\tbtc->btc_write_scbd(btc, BTC_SCBD_ACTIVE | BTC_SCBD_ON, TRUE);\n\t\tbtc->stop_coex_dm = FALSE;\n\t}\n\n\t/* PTA parameter */\n\trtw_btc_table(btc, FC_EXCU, table_case);\n\trtw_btc_tdma(btc, FC_EXCU, tdma_case);\n\n\trtw_btc_query_bt_info(btc);\n}\n\nvoid rtw_btc_ex_power_on_setting(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_board_info *board_info = &btc->board_info;\n\tu8 u8tmp = 0x0, table_case = 1;\n\tu16 u16tmp = 0x0;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\tbtc->stop_coex_dm = TRUE;\n\tbtc->wl_rf_state_off = FALSE;\n\n\t/* enable BB, REG_SYS_FUNC_EN to write reg correctly. */\n\tu16tmp = btc->btc_read_2byte(btc, 0x2);\n\tbtc->btc_write_2byte(btc, 0x2, u16tmp | BIT(0) | BIT(1));\n\n\trtw_btc_monitor_bt_enable(btc);\n\n\t/* Setup RF front end type */\n\tbtc->chip_para->chip_setup(btc, BTC_CSETUP_RFE_TYPE);\n\n\t/* Set Antenna Path to BT side */\n\trtw_btc_set_ant_path(btc, FC_EXCU, BTC_ANT_POWERON);\n\n\trtw_btc_table(btc, FC_EXCU, table_case);\n\n\t/* SD1 Chunchu red x issue */\n\tbtc->btc_write_1byte(btc, 0xff1a, 0x0);\n\n\trtw_btc_gnt_debug(btc, TRUE);\n\n\tboard_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;\n}\n\nvoid rtw_btc_ex_pre_load_firmware(struct btc_coexist *btc) {}\n\nvoid rtw_btc_ex_init_hw_config(struct btc_coexist *btc, boolean wifi_only)\n{\n\trtw_btc_init_hw_config(btc, wifi_only);\n}\n\nvoid rtw_btc_ex_init_coex_dm(struct btc_coexist *btc)\n{\n\trtw_btc_init_coex_dm(btc);\n}\n\nvoid rtw_btc_ex_display_simple_coex_info(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\tstruct btc_rfe_type *rfe_type = &btc->rfe_type;\n\tstruct btc_board_info *board_info = &btc->board_info;\n\n\tu8 *cli_buf = btc->cli_buf;\n\tu32 bt_patch_ver = 0, bt_coex_ver = 0, val = 0;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n _____[BT Coexist info]____\");\n\tCL_PRINTF(cli_buf);\n\n\tif (btc->manual_control) {\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n __[Under Manual Control]_\");\n\t\tCL_PRINTF(cli_buf);\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n _________________________\");\n\t\tCL_PRINTF(cli_buf);\n\t}\n\n\tif (btc->stop_coex_dm) {\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n ____[Coex is STOPPED]____\");\n\t\tCL_PRINTF(cli_buf);\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n _________________________\");\n\t\tCL_PRINTF(cli_buf);\n\t}\n\n\tif (!coex_sta->bt_disabled &&\n\t    (coex_sta->bt_supported_version == 0 ||\n\t     coex_sta->bt_supported_version == 0xffff) &&\n\t     coex_sta->cnt_wl[BTC_CNT_WL_COEXINFO2] % 3 == 0) {\n\t\tbtc->btc_get(btc, BTC_GET_U4_SUPPORTED_FEATURE,\n\t\t\t     &coex_sta->bt_supported_feature);\n\n\t\tbtc->btc_get(btc, BTC_GET_U4_SUPPORTED_VERSION,\n\t\t\t     &coex_sta->bt_supported_version);\n\n\t\tval = btc->btc_get_bt_reg(btc, 3, 0xac);\n\n\t\tcoex_sta->bt_reg_vendor_ac = (u16)(val & 0xffff);\n\n\t\tval = btc->btc_get_bt_reg(btc, 3, 0xae);\n\n\t\tcoex_sta->bt_reg_vendor_ae = (u16)(val & 0xffff);\n\n\t\tbtc->btc_get(btc, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);\n\t\tbtc->bt_info.bt_get_fw_ver = bt_patch_ver;\n\t}\n\n\t/* BT coex. info. */\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t   \"\\r\\n %-35s = %d/ %d/ %s / %d\",\n\t\t   \"Ant PG Num/ Mech/ Pos/ RFE\", board_info->pg_ant_num,\n\t\t   board_info->btdm_ant_num,\n\t\t   (board_info->btdm_ant_pos ==\n\t\t    BTC_ANTENNA_AT_MAIN_PORT ? \"Main\" : \"Aux\"),\n\t\t   rfe_type->rfe_module_type);\n\tCL_PRINTF(cli_buf);\n\n\tbt_coex_ver = ((coex_sta->bt_supported_version & 0xff00) >> 8);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t   \"\\r\\n %-35s = %d_%02x/ %d_%02x/ 0x%02x/ 0x%02x (%s)\",\n\t\t   \"Ver Coex/ Para/ BT_Dez/ BT_Rpt\",\n\t\t   coex_ver_date, coex_ver, chip_para->para_ver_date,\n\t\t   chip_para->para_ver, chip_para->bt_desired_ver, bt_coex_ver,\n\t\t   (bt_coex_ver == 0xff ? \"Unknown\" :\n\t\t   (coex_sta->bt_disabled ? \"BT-disable\" :\n\t\t   (bt_coex_ver >= chip_para->bt_desired_ver ?\n\t\t    \"Match\" : \"Mis-Match\"))));\n\tCL_PRINTF(cli_buf);\n\n\t/* BT Status */\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s\", \"BT status\",\n\t\t   ((coex_sta->bt_disabled) ? (\"disabled\") :\n\t\t   ((coex_sta->bt_inq_page) ? (\"inquiry/page\") :\n\t\t   ((coex_dm->bt_status == BTC_BTSTATUS_NCON_IDLE) ?\n\t\t    \"non-connected idle\" :\n\t\t    ((coex_dm->bt_status == BTC_BTSTATUS_CON_IDLE) ?\n\t\t    \"connected-idle\" : \"busy\")))));\n\tCL_PRINTF(cli_buf);\n\n\t/* HW Settings */\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d\",\n\t\t   \"0x770(Hi-pri rx/tx)\", coex_sta->hi_pri_rx,\n\t\t   coex_sta->hi_pri_tx);\n\tCL_PRINTF(cli_buf);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d %s\",\n\t\t   \"0x774(Lo-pri rx/tx)\", coex_sta->lo_pri_rx,\n\t\t   coex_sta->lo_pri_tx, (coex_sta->bt_slave ?\n\t\t   \"(Slave!!)\" : \"\"));\n\tCL_PRINTF(cli_buf);\n\n\tcoex_sta->cnt_wl[BTC_CNT_WL_COEXINFO2]++;\n}\n\nvoid rtw_btc_ex_display_coex_info(struct btc_coexist *btc)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\tstruct btc_rfe_type *rfe_type = &btc->rfe_type;\n\tstruct btc_board_info *board_info = &btc->board_info;\n\n\tu8 *cli_buf = btc->cli_buf, u8tmp[4], i, ps_tdma_case = 0;\n\tu16 u16tmp[4];\n\tu32 u32tmp[4], phy_ver = 0, fw_ver = 0,\n\t    bt_coex_ver = 0, val = 0,\n\t    fa_ofdm, fa_cck, cca_ofdm, cca_cck,\n\t    ok_11b, ok_11g, ok_11n, ok_11vht,\n\t    err_11b, err_11g, err_11n, err_11vht;\n\tboolean is_bt_reply = FALSE;\n\tu8 * const p = &coex_sta->bt_afh_map[0];\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t   \"\\r\\n ============[BT Coexist info %s]============\",\n\t\t   chip_para->chip_name);\n\tCL_PRINTF(cli_buf);\n\n\tif (btc->manual_control) {\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n ============[Under Manual Control]============\");\n\t\tCL_PRINTF(cli_buf);\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n ==========================================\");\n\t\tCL_PRINTF(cli_buf);\n\t} else if (btc->stop_coex_dm) {\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n ============[Coex is STOPPED]============\");\n\t\tCL_PRINTF(cli_buf);\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n ==========================================\");\n\t\tCL_PRINTF(cli_buf);\n\t} else if (coex_sta->coex_freeze) {\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n ============[coex_freeze]============\");\n\t\tCL_PRINTF(cli_buf);\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n ==========================================\");\n\t\tCL_PRINTF(cli_buf);\n\t}\n\n\tif (!coex_sta->bt_disabled &&\n\t     coex_sta->cnt_wl[BTC_CNT_WL_COEXINFO1] % 3 == 0) {\n\t\tif (coex_sta->bt_supported_version == 0 ||\n\t\t    coex_sta->bt_supported_version == 0xffff) {\n\t\t\tbtc->btc_get(btc, BTC_GET_U4_SUPPORTED_VERSION,\n\t\t\t\t     &coex_sta->bt_supported_version);\n\n\t\t\tif (coex_sta->bt_supported_version > 0 &&\n\t\t\t    coex_sta->bt_supported_version < 0xffff)\n\t\t\t\tis_bt_reply = TRUE;\n\t\t} else {\n\t\t\tis_bt_reply = TRUE;\n\t\t}\n\n\t\tif (coex_dm->bt_status != BTC_BTSTATUS_NCON_IDLE) {\n\t\t\tbtc->btc_get_bt_afh_map_from_bt(btc, 0, p);\n\t\t\tval = btc->btc_get_bt_reg(btc, 1, 0xa);\n\t\t\tcoex_sta->bt_reg_modem_a = (u16)((val & 0x1c0) >> 6);\n\t\t\tval = btc->btc_get_bt_reg(btc, 0, 0x2);\n\t\t\tcoex_sta->bt_reg_rf_2 = (u16)val;\n\t\t}\n\t}\n\n\tif (is_bt_reply) {\n\t\tif (coex_sta->bt_supported_feature == 0) {\n\t\t\tbtc->btc_get(btc, BTC_GET_U4_SUPPORTED_FEATURE,\n\t\t\t\t     &coex_sta->bt_supported_feature);\n\n\t\t\tif (coex_sta->bt_supported_feature & BIT(11))\n\t\t\t\tcoex_sta->bt_slave_latency = TRUE;\n\t\t\telse\n\t\t\t\tcoex_sta->bt_slave_latency = FALSE;\n\t\t}\n\n\t\tif (coex_sta->bt_reg_vendor_ac == 0xffff) {\n\t\t\tval = btc->btc_get_bt_reg(btc, 3, 0xac);\n\t\t\tcoex_sta->bt_reg_vendor_ac = (u16)(val & 0xffff);\n\t\t}\n\n\t\tif (coex_sta->bt_reg_vendor_ae == 0xffff) {\n\t\t\tval = btc->btc_get_bt_reg(btc, 3, 0xae);\n\t\t\tcoex_sta->bt_reg_vendor_ae = (u16)(val & 0xffff);\n\t\t}\n\n\t\tif (btc->bt_info.bt_get_fw_ver == 0)\n\t\t\tbtc->btc_get(btc, BTC_GET_U4_BT_PATCH_VER,\n\t\t\t\t     &btc->bt_info.bt_get_fw_ver);\n\t}\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %s/ %s / %d/ %d\",\n\t\t   \"Ant PG Num/ Mech/ Pos/ RFE/ Dist\", board_info->pg_ant_num,\n\t\t   (board_info->btdm_ant_num == 1 ? \"Shared\" : \"Non-Shared\"),\n\t\t   (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT ?\n\t\t   \"Main\" : \"Aux\"), rfe_type->rfe_module_type,\n\t\t   board_info->ant_distance);\n\tCL_PRINTF(cli_buf);\n\n\tbtc->btc_get(btc, BTC_GET_U4_WIFI_FW_VER, &fw_ver);\n\tbtc->btc_get(btc, BTC_GET_U4_WIFI_PHY_VER, &phy_ver);\n\tbt_coex_ver = ((coex_sta->bt_supported_version & 0xff00) >> 8);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t   \"\\r\\n %-35s = %d_%02x/ %d_%02x/ 0x%02x/ 0x%02x (%s)\",\n\t\t   \"Ver Coex/ Para/ BT_Dez/ BT_Rpt\",\n\t\t   coex_ver_date, coex_ver, chip_para->para_ver_date,\n\t\t   chip_para->para_ver, chip_para->bt_desired_ver, bt_coex_ver,\n\t\t   (bt_coex_ver == 0xff ? \"Unknown\" :\n\t\t   (coex_sta->bt_disabled ? \"BT-disable\" :\n\t\t   (bt_coex_ver >= chip_para->bt_desired_ver ?\n\t\t    \"Match\" : \"Mis-Match\"))));\n\tCL_PRINTF(cli_buf);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t   \"\\r\\n %-35s = 0x%x/ 0x%08x/ v%d/ %c\",\n\t\t   \"W_FW/ B_FW/ Phy/ Kt\", fw_ver, btc->bt_info.bt_get_fw_ver,\n\t\t   phy_ver, coex_sta->kt_ver + 65);\n\tCL_PRINTF(cli_buf);\n\n\t/* wifi status */\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s\",\n\t\t   \"============[Wifi Status]============\");\n\tCL_PRINTF(cli_buf);\n\tbtc->btc_disp_dbg_msg(btc, BTC_DBG_DISP_WIFI_STATUS);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s\",\n\t\t   \"============[BT Status]============\");\n\tCL_PRINTF(cli_buf);\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %ddBm/ %d/ %d\",\n\t\t   \"BT status/ rssi/ retryCnt/ popCnt\",\n\t\t   ((coex_sta->bt_disabled) ? (\"disabled\") :\n\t\t    ((coex_sta->bt_inq_page) ? (\"inquiry-page\") :\n\t\t    ((coex_dm->bt_status == BTC_BTSTATUS_NCON_IDLE) ?\n\t\t    \"non-connecte-idle\" : ((coex_dm->bt_status ==\n\t\t    BTC_BTSTATUS_CON_IDLE) ? \"connected-idle\" : \"busy\")))),\n\t\t    coex_sta->bt_rssi - 100, coex_sta->cnt_bt[BTC_CNT_BT_RETRY],\n\t\t    coex_sta->cnt_bt[BTC_CNT_BT_POPEVENT]);\n\tCL_PRINTF(cli_buf);\n\n\tif (coex_sta->bt_profile_num != 0) {\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n %-35s = %s%s%s%s%s%s (multilink = %d)\",\n\t\t\t   \"Profiles\", ((coex_sta->bt_a2dp_exist) ?\n\t\t\t   ((coex_sta->bt_a2dp_sink) ? \"A2DP sink,\" :\n\t\t\t    \"A2DP,\") : \"\"),\n\t\t\t   ((coex_sta->bt_hfp_exist) ? \"HFP,\" : \"\"),\n\t\t\t   ((coex_sta->bt_hid_exist) ?\n\t\t\t   ((coex_sta->bt_ble_exist) ? \"HID(RCU)\" :\n\t\t\t   ((coex_sta->bt_hid_slot >= 2) ? \"HID(4/18),\" :\n\t\t\t   \"HID(2/18),\")) : \"\"), ((coex_sta->bt_pan_exist) ?\n\t\t\t   ((coex_sta->bt_opp_exist) ? \"OPP,\" : \"PAN,\") :\n\t\t\t   \"\"), ((coex_sta->bt_ble_voice) ? \"Voice,\" : \"\"),\n\t\t\t   ((coex_sta->bt_msft_mr_exist) ? \"MR\" : \"\"),\n\t\t\t   coex_sta->bt_multi_link);\n\t\tCL_PRINTF(cli_buf);\n\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n %-35s = %d/ %d/ %d/ %d\",\n\t\t\t   \"SUT Power[3:0]\",\n\t\t\t   coex_sta->bt_sut_pwr_lvl[3],\n\t\t\t   coex_sta->bt_sut_pwr_lvl[2],\n\t\t\t   coex_sta->bt_sut_pwr_lvl[1],\n\t\t\t   coex_sta->bt_sut_pwr_lvl[0]);\n\n\t\tCL_PRINTF(cli_buf);\n\t} else {\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s\",\n\t\t\t   \"Profiles\",\n\t\t\t   (coex_sta->bt_msft_mr_exist) ? \"MR\" : \"None\");\n\n\tCL_PRINTF(cli_buf);\n\t}\n\n\t/* for 8822b, Scoreboard[10]: 0: CQDDR off, 1: CQDDR on\n\t * for 8822c, Scoreboard[10]: 0: CQDDR on, 1:CQDDR fix 2M\n\t */\n\n\tif (coex_sta->bt_a2dp_exist) {\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n %-35s = %s/ %d/ 0x%x/ 0x%x\",\n\t\t\t   \"CQDDR/Bitpool/V_ID/D_name\",\n\t\t\t   (chip_para->new_scbd10_def ?\n\t\t\t   ((coex_sta->bt_fix_2M) ? \"fix_2M\" : \"CQDDR_On\") :\n\t\t\t   ((coex_sta->bt_fix_2M) ? \"CQDDR_On\" : \"CQDDR_Off\")),\n\t\t\t   coex_sta->bt_a2dp_bitpool,\n\t\t\t   coex_sta->bt_a2dp_vendor_id,\n\t\t\t   coex_sta->bt_a2dp_device_name);\n\n\t\tCL_PRINTF(cli_buf);\n\t}\n\n\tif (coex_sta->bt_hid_exist) {\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d\",\n\t\t\t   \"HID PairNum\", coex_sta->bt_hid_pair_num);\n\t\tCL_PRINTF(cli_buf);\n\t}\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %d/ %s/ 0x%x\",\n\t\t   \"Role/RoleSwCnt/IgnWla/Feature\",\n\t\t   ((coex_sta->bt_slave) ? \"Slave\" : \"Master\"),\n\t\t   coex_sta->cnt_bt[BTC_CNT_BT_ROLESWITCH],\n\t\t   ((coex_dm->cur_ignore_wlan_act) ? \"Yes\" : \"No\"),\n\t\t   coex_sta->bt_supported_feature);\n\tCL_PRINTF(cli_buf);\n\n\tif (coex_sta->bt_ble_scan_en) {\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x\",\n\t\t\t   \"BLEScan Type/TV/Init/Ble\",\n\t\t\t   coex_sta->bt_ble_scan_type,\n\t\t\t   (coex_sta->bt_ble_scan_type & 0x1 ?\n\t\t\t\t    coex_sta->bt_ble_scan_para[0] : 0x0),\n\t\t\t   (coex_sta->bt_ble_scan_type & 0x2 ?\n\t\t\t\t    coex_sta->bt_ble_scan_para[1] : 0x0),\n\t\t\t   (coex_sta->bt_ble_scan_type & 0x4 ?\n\t\t\t\t    coex_sta->bt_ble_scan_para[2] : 0x0));\n\t\tCL_PRINTF(cli_buf);\n\t}\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t   \"\\r\\n %-35s = %d/ %d/ %d/ %d/ %d/ %d/ %d %s\",\n\t\t   \"Init/ReLink/IgnWl/Pag/Inq/iqkO/iqkX\",\n\t\t   coex_sta->cnt_bt[BTC_CNT_BT_REINIT],\n\t\t   coex_sta->cnt_bt[BTC_CNT_BT_SETUPLINK],\n\t\t   coex_sta->cnt_bt[BTC_CNT_BT_IGNWLANACT],\n\t\t   coex_sta->cnt_bt[BTC_CNT_BT_PAGE],\n\t\t   coex_sta->cnt_bt[BTC_CNT_BT_INQ],\n\t\t   coex_sta->cnt_bt[BTC_CNT_BT_IQK],\n\t\t   coex_sta->cnt_bt[BTC_CNT_BT_IQKFAIL],\n\t\t   (coex_sta->bt_setup_link ? \"(Relink!!)\" : \"\"));\n\tCL_PRINTF(cli_buf);\n\n\tbtc->btc_read_scbd(btc, &u16tmp[0]);\n\n\tif (coex_sta->bt_reg_vendor_ae == 0xffff ||\n\t    coex_sta->bt_reg_vendor_ac == 0xffff)\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n %-35s = x/ x/ 0x%04x\",\n\t\t\t   \"0xae[4]/0xac[1:0]/ScBd(B->W)\", u16tmp[0]);\n\telse\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x/ 0x%04x/ %s\",\n\t\t\t   \"ae/ac/m_a[8:6]/rf_2/ScBd(B->W)/path\",\n\t\t\t   coex_sta->bt_reg_vendor_ae,\n\t\t\t   coex_sta->bt_reg_vendor_ac,\n\t\t\t   coex_sta->bt_reg_modem_a,\n\t\t\t   coex_sta->bt_reg_rf_2, u16tmp[0],\n\t\t\t   ((coex_sta->bt_reg_vendor_ae & BIT(4)) ? \"S1\" : \"S0\"\n\t\t\t   ));\n\tCL_PRINTF(cli_buf);\n\n\tif (coex_dm->bt_status != BTC_BTSTATUS_NCON_IDLE) {\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n %-35s = %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x\",\n\t\t\t   \"AFH MAP\", coex_sta->bt_afh_map[0],\n\t\t\t   coex_sta->bt_afh_map[1], coex_sta->bt_afh_map[2],\n\t\t\t   coex_sta->bt_afh_map[3], coex_sta->bt_afh_map[4],\n\t\t\t   coex_sta->bt_afh_map[5], coex_sta->bt_afh_map[6],\n\t\t\t   coex_sta->bt_afh_map[7], coex_sta->bt_afh_map[8],\n\t\t\t   coex_sta->bt_afh_map[9]);\n\t\tCL_PRINTF(cli_buf);\n\t}\n\n\tfor (i = 0; i < BTC_BTINFO_SRC_BT_IQK; i++) {\n\t\tif (coex_sta->cnt_bt_info_c2h[i]) {\n\t\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t   \"\\r\\n %-35s = %02x %02x %02x %02x %02x %02x %02x (%d)\",\n\t\t\t\t   glbt_info_src[i],\n\t\t\t\t   coex_sta->bt_info_c2h[i][0],\n\t\t\t\t   coex_sta->bt_info_c2h[i][1],\n\t\t\t\t   coex_sta->bt_info_c2h[i][2],\n\t\t\t\t   coex_sta->bt_info_c2h[i][3],\n\t\t\t\t   coex_sta->bt_info_c2h[i][4],\n\t\t\t\t   coex_sta->bt_info_c2h[i][5],\n\t\t\t\t   coex_sta->bt_info_c2h[i][6],\n\t\t\t\t   coex_sta->cnt_bt_info_c2h[i]);\n\t\t\tCL_PRINTF(cli_buf);\n\t\t}\n\t}\n\n\tif (btc->manual_control) {\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s\",\n\t\t\t   \"============[mechanisms] (under Manual)============\");\n\t\tCL_PRINTF(cli_buf);\n\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n %-35s = %02x %02x %02x %02x %02x\",\n\t\t\t   \"TDMA_Now\",\n\t\t\t   coex_dm->fw_tdma_para[0], coex_dm->fw_tdma_para[1],\n\t\t\t   coex_dm->fw_tdma_para[2], coex_dm->fw_tdma_para[3],\n\t\t\t   coex_dm->fw_tdma_para[4]);\n\t\tCL_PRINTF(cli_buf);\n\t} else {\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s\",\n\t\t\t   \"============[Mechanisms]============\");\n\t\tCL_PRINTF(cli_buf);\n\n\t\tps_tdma_case = coex_dm->cur_ps_tdma;\n\t\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t\t   \"\\r\\n %-35s = %02x %02x %02x %02x %02x (case-%d, TDMA-%s, Ext-%d)\",\n\t\t\t   \"TDMA\",\n\t\t\t   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],\n\t\t\t   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],\n\t\t\t   coex_dm->ps_tdma_para[4], ps_tdma_case,\n\t\t\t   (coex_dm->cur_ps_tdma_on ? \"On\" : \"Off\"),\n\t\t\t   coex_sta->bt_ext_autoslot_thres);\n\t\tCL_PRINTF(cli_buf);\n\t}\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %s/ %d\",\n\t\t   \"Coex_Mode/Free_Run/Timer_base\",\n\t\t   coex_mode_string[coex_sta->wl_coex_mode],\n\t\t   ((coex_sta->coex_freerun) ? \"Yes\" : \"No\"),\n\t\t   coex_sta->tdma_timer_base);\n\n\tCL_PRINTF(cli_buf);\n\n\tu32tmp[0] = btc->btc_read_4byte(btc, 0x6c0);\n\tu32tmp[1] = btc->btc_read_4byte(btc, 0x6c4);\n\tu32tmp[2] = btc->btc_read_4byte(btc, 0x6c8);\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t   \"\\r\\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x\",\n\t\t   \"Table/0x6c0/0x6c4/0x6c8\", coex_sta->coex_table_type,\n\t\t   u32tmp[0], u32tmp[1], u32tmp[2]);\n\tCL_PRINTF(cli_buf);\n\n\tu8tmp[0] = btc->btc_read_1byte(btc, 0x778);\n\tu32tmp[0] = btc->btc_read_4byte(btc, 0x6cc);\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t   \"\\r\\n %-35s = 0x%x/ 0x%x/ 0x%04x/ %d/ %s\",\n\t\t   \"0x778/0x6cc/ScBd(W->B)/RunCnt/Rsn\", u8tmp[0], u32tmp[0],\n\t\t   coex_sta->score_board_WB,\n\t\t   coex_sta->cnt_wl[BTC_CNT_WL_COEXRUN],\n\t\t   run_reason_string[coex_sta->coex_run_reason]);\n\tCL_PRINTF(cli_buf);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t   \"\\r\\n %-35s = %02x %02x %02x (RF-Ch = %d)\", \"AFH Map to BT\",\n\t\t   coex_dm->wl_chnl_info[0], coex_dm->wl_chnl_info[1],\n\t\t   coex_dm->wl_chnl_info[2], coex_sta->wl_center_ch);\n\tCL_PRINTF(cli_buf);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %s/ %s/ %d/ %d\",\n\t\t   \"AntDiv/BtCtrlLPS/LPRA/PsFail/g_busy\",\n\t\t   ((board_info->ant_div_cfg) ? \"On\" : \"Off\"),\n\t\t   ((coex_sta->wl_force_lps_ctrl) ? \"On\" : \"Off\"),\n\t\t   ((coex_dm->cur_low_penalty_ra) ? \"On\" : \"Off\"),\n\t\t   coex_sta->cnt_wl[BTC_CNT_WL_PSFAIL], coex_sta->wl_gl_busy);\n\tCL_PRINTF(cli_buf);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d/ %d/ %d/ %d\",\n\t\t   \"Null All/Retry/Ack/BT_Empty/BT_Late\",\n\t\t   coex_sta->wl_fw_dbg_info[1], coex_sta->wl_fw_dbg_info[2],\n\t\t   coex_sta->wl_fw_dbg_info[3], coex_sta->wl_fw_dbg_info[4],\n\t\t   coex_sta->wl_fw_dbg_info[5]);\n\tCL_PRINTF(cli_buf);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d/ %s/ %d\",\n\t\t   \"Cnt TDMA_Togg/Lk5ms/Lk5ms_off/fw\",\n\t\t   coex_sta->wl_fw_dbg_info[6],\n\t\t   coex_sta->wl_fw_dbg_info[7],\n\t\t   ((coex_sta->is_no_wl_5ms_extend) ? \"Yes\" : \"No\"),\n\t\t   coex_sta->cnt_wl[BTC_CNT_WL_FW_NOTIFY]);\n\tCL_PRINTF(cli_buf);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d/ %s/ %d\",\n\t\t   \"WL_TxPw/BT_TxPw/WL_Rx/BT_LNA_Lvl\",\n\t\t   coex_dm->cur_wl_pwr_lvl, coex_dm->cur_bt_pwr_lvl,\n\t\t   ((coex_dm->cur_wl_rx_low_gain_en) ? \"On\" : \"Off\"),\n\t\t   coex_dm->cur_bt_lna_lvl);\n\tCL_PRINTF(cli_buf);\n\n\t/* Hw setting\t\t */\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s\",\n\t\t   \"============[Hw setting]============\");\n\tCL_PRINTF(cli_buf);\n\n\tbtc->chip_para->chip_setup(btc, BTC_CSETUP_COEXINFO_HW);\n\n\tfa_ofdm = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_FA_OFDM);\n\tfa_cck = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_FA_CCK);\n\tcca_ofdm = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CCA_OFDM);\n\tcca_cck = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CCA_CCK);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t   \"\\r\\n %-35s = %d/ %d/ %d/ %d\",\n\t\t   \"CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA\", cca_cck, fa_cck, cca_ofdm,\n\t\t   fa_ofdm);\n\tCL_PRINTF(cli_buf);\n\n\tok_11b =\n\t   btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_CCK);\n\tok_11g =\n\t   btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_LEGACY);\n\tok_11n =\n\t   btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_HT);\n\tok_11vht =\n\t   btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_VHT);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d/ %d/ %d\",\n\t\t   \"CRC_OK CCK/11g/11n/11ac\", ok_11b, ok_11g, ok_11n, ok_11vht);\n\tCL_PRINTF(cli_buf);\n\n\terr_11b =\n\t   btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_CCK);\n\terr_11g =\n\t   btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_LEGACY);\n\terr_11n =\n\t    btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_HT);\n\terr_11vht =\n\t    btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_VHT);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d/ %d/ %d\",\n\t\t   \"CRC_Err CCK/11g/11n/11ac\",\n\t\t   err_11b, err_11g, err_11n, err_11vht);\n\tCL_PRINTF(cli_buf);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,\n\t\t   \"\\r\\n %-35s = %d/ %d/ %s-%d/ %d (Tx macid: %d)\",\n\t\t   \"Rate RxD/RxRTS/TxD/TxRetry_ratio\",\n\t\t   coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate,\n\t\t   (coex_sta->wl_tx_rate & 0x80 ? \"SGI\" : \"LGI\"),\n\t\t   coex_sta->wl_tx_rate & 0x7f,\n\t\t   coex_sta->wl_tx_retry_ratio,\n\t\t   coex_sta->wl_tx_macid);\n\tCL_PRINTF(cli_buf);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %s/ %s/ %d\",\n\t\t   \"HiPr/ Locking/ Locked/ Noisy\",\n\t\t   (coex_sta->wl_hi_pri_task1 ? \"Yes\" : \"No\"),\n\t\t   (coex_sta->wl_cck_lock ? \"Yes\" : \"No\"),\n\t\t   (coex_sta->wl_cck_lock_ever ? \"Yes\" : \"No\"),\n\t\t   coex_sta->wl_noisy_level);\n\tCL_PRINTF(cli_buf);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d\",\n\t\t   \"0x770(Hi-pri rx/tx)\", coex_sta->hi_pri_rx,\n\t\t   coex_sta->hi_pri_tx);\n\tCL_PRINTF(cli_buf);\n\n\tCL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d %s\",\n\t\t   \"0x774(Lo-pri rx/tx)\", coex_sta->lo_pri_rx,\n\t\t   coex_sta->lo_pri_tx, (coex_sta->bt_slave ?\n\t\t   \"(Slave!!)\" : \"\"));\n\tCL_PRINTF(cli_buf);\n\n\tbtc->btc_disp_dbg_msg(btc, BTC_DBG_DISP_COEX_STATISTICS);\n\n\tcoex_sta->cnt_wl[BTC_CNT_WL_COEXINFO1]++;\n\n\tif (coex_sta->cnt_wl[BTC_CNT_WL_COEXINFO1] % 5 == 0)\n\t\tcoex_sta->cnt_bt[BTC_CNT_BT_POPEVENT] = 0;\n}\n\nvoid rtw_btc_ex_ips_notify(struct btc_coexist *btc, u8 type)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\n\tif (btc->manual_control || btc->stop_coex_dm)\n\t\treturn;\n\n\tif (type == BTC_IPS_ENTER) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], IPS ENTER notify\\n\");\n\t\tBTC_TRACE(trace_buf);\n\t\tcoex_sta->wl_under_ips = TRUE;\n\n\t\t/* Write WL \"Active\" in Score-board for LPS off */\n\t\tbtc->btc_write_scbd(btc, BTC_SCBD_ALL, FALSE);\n\n\t\trtw_btc_set_ant_path(btc, FC_EXCU, BTC_ANT_WOFF);\n\t\trtw_btc_action_coex_all_off(btc);\n\t} else if (type == BTC_IPS_LEAVE) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], IPS LEAVE notify\\n\");\n\t\tBTC_TRACE(trace_buf);\n\t\tbtc->btc_write_scbd(btc, BTC_SCBD_ACTIVE | BTC_SCBD_ON, TRUE);\n\n\t\t/*leave IPS : run ini hw config (exclude wifi only)*/\n\t\trtw_btc_init_hw_config(btc, FALSE);\n\t\t/*sw all off*/\n\t\trtw_btc_init_coex_dm(btc);\n\n\t\trtw_btc_query_bt_info(btc);\n\n\t\tcoex_sta->wl_under_ips = FALSE;\n\t}\n}\n\nvoid rtw_btc_ex_lps_notify(struct btc_coexist *btc, u8 type)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\n\tif (btc->manual_control || btc->stop_coex_dm)\n\t\treturn;\n\n\tif (type == BTC_LPS_ENABLE) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], LPS ENABLE notify\\n\");\n\t\tBTC_TRACE(trace_buf);\n\t\tcoex_sta->wl_under_lps = TRUE;\n\n\t\tif (coex_sta->wl_force_lps_ctrl) { /* LPS No-32K */\n\t\t\t/* Write WL \"Active\" in Score-board for PS-TDMA */\n\t\t\tbtc->btc_write_scbd(btc, BTC_SCBD_ACTIVE, TRUE);\n\t\t} else {\n\t\t\t/* Write WL \"Non-Active\" in Score-board for Native-PS */\n\t\t\tbtc->btc_write_scbd(btc, BTC_SCBD_ACTIVE, FALSE);\n\n\t\t\trtw_btc_run_coex(btc, BTC_RSN_LPS);\n\t\t}\n\t} else if (type == BTC_LPS_DISABLE) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], LPS DISABLE notify\\n\");\n\t\tBTC_TRACE(trace_buf);\n\t\tcoex_sta->wl_under_lps = FALSE;\n\n\t\t/* Write WL \"Active\" in Score-board for LPS off */\n\t\tbtc->btc_write_scbd(btc, BTC_SCBD_ACTIVE, TRUE);\n\n\t\tif (!coex_sta->wl_force_lps_ctrl)\n\t\t\trtw_btc_query_bt_info(btc);\n\n\t\trtw_btc_run_coex(btc, BTC_RSN_LPS);\n\t}\n}\n\nvoid rtw_btc_ex_scan_notify(struct btc_coexist *btc, u8 type)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\n\tif (btc->manual_control || btc->stop_coex_dm)\n\t\treturn;\n\n\tcoex_sta->coex_freeze = FALSE;\n\n\tbtc->btc_write_scbd(btc, BTC_SCBD_ACTIVE | BTC_SCBD_ON, TRUE);\n\n\tif (type == BTC_SCAN_START_5G) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], SCAN START notify (5G)\\n\");\n\t\tBTC_TRACE(trace_buf);\n\n\t\trtw_btc_set_ant_path(btc, FC_EXCU, BTC_ANT_5G);\n\t\trtw_btc_run_coex(btc, BTC_RSN_5GSCANSTART);\n\t} else if (type == BTC_SCAN_START_2G || type == BTC_SCAN_START) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], SCAN START notify (2G)\\n\");\n\t\tBTC_TRACE(trace_buf);\n\n\t\tcoex_sta->wl_hi_pri_task2 = TRUE;\n\n\t\t/* Force antenna setup for no scan result issue */\n\t\trtw_btc_set_ant_path(btc, FC_EXCU, BTC_ANT_2G);\n\t\trtw_btc_run_coex(btc, BTC_RSN_2GSCANSTART);\n\t} else {\n\t\tbtc->btc_get(btc, BTC_GET_U1_AP_NUM,\n\t\t\t     &coex_sta->cnt_wl[BTC_CNT_WL_SCANAP]);\n\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], SCAN FINISH notify (Scan-AP = %d)\\n\",\n\t\t\t    coex_sta->cnt_wl[BTC_CNT_WL_SCANAP]);\n\t\tBTC_TRACE(trace_buf);\n\n\t\tcoex_sta->wl_hi_pri_task2 = FALSE;\n\n\t\trtw_btc_run_coex(btc, BTC_RSN_SCANFINISH);\n\t}\n}\n\nvoid rtw_btc_ex_scan_notify_without_bt(struct btc_coexist *btc, u8 type)\n{\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\tstruct btc_rfe_type *rfe_type = &btc->rfe_type;\n\tu8 ctrl_type = BTC_SWITCH_CTRL_BY_BBSW, pos_type = BTC_SWITCH_TO_WLG;\n\n\tif (!rfe_type->ant_switch_exist)\n\t\treturn;\n\n\tif (type == BTC_SCAN_START) {\n\t\tif (link_info_ext->is_all_under_5g)\n\t\t\tpos_type = BTC_SWITCH_TO_WLA;\n\t\telse /* under 2.4G */\n\t\t\tpos_type = BTC_SWITCH_TO_WLG;\n\t} else if (type == BTC_SCAN_START_2G) {\n\t\tpos_type = BTC_SWITCH_TO_WLG;\n\t}\n\n\trtw_btc_set_ant_switch(btc, FC_EXCU, ctrl_type, pos_type);\n}\n\nvoid rtw_btc_ex_switchband_notify(struct btc_coexist *btc, u8 type)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\n\tif (btc->manual_control || btc->stop_coex_dm)\n\t\treturn;\n\n\tif (type == BTC_SWITCH_TO_5G) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): TO_5G\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\trtw_btc_run_coex(btc, BTC_RSN_5GSWITCHBAND);\n\t} else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): TO_24G_NOFORSCAN\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\trtw_btc_run_coex(btc, BTC_RSN_2GSWITCHBAND);\n\t} else {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): TO_2G\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\trtw_btc_ex_scan_notify(btc, BTC_SCAN_START_2G);\n\t}\n}\n\nvoid rtw_btc_ex_switchband_notify_without_bt(struct btc_coexist *btc, u8 type)\n{\n\tstruct btc_rfe_type *rfe_type = &btc->rfe_type;\n\tu8 ctrl_type = BTC_SWITCH_CTRL_BY_BBSW, pos_type = BTC_SWITCH_TO_WLG;\n\n\tif (!rfe_type->ant_switch_exist)\n\t\treturn;\n\n\tif (type == BTC_SWITCH_TO_5G) {\n\t\tpos_type = BTC_SWITCH_TO_WLA;\n\t} else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) {\n\t\tpos_type = BTC_SWITCH_TO_WLG;\n\t} else {\n\t\trtw_btc_ex_scan_notify_without_bt(btc, BTC_SCAN_START_2G);\n\t\treturn;\n\t}\n\n\trtw_btc_set_ant_switch(btc, FC_EXCU, ctrl_type, pos_type);\n}\n\nvoid rtw_btc_ex_connect_notify(struct btc_coexist *btc, u8 type)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\n\tif (btc->manual_control || btc->stop_coex_dm)\n\t\treturn;\n\n\tbtc->btc_write_scbd(btc, BTC_SCBD_ACTIVE | BTC_SCBD_ON, TRUE);\n\n\tif (type == BTC_ASSOCIATE_5G_START) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): 5G start\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\trtw_btc_set_ant_path(btc, FC_EXCU, BTC_ANT_5G);\n\n\t\trtw_btc_run_coex(btc, BTC_RSN_5GCONSTART);\n\t} else if (type == BTC_ASSOCIATE_5G_FINISH) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): 5G finish\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\trtw_btc_set_ant_path(btc, FC_EXCU, BTC_ANT_5G);\n\n\t\trtw_btc_run_coex(btc, BTC_RSN_5GCONFINISH);\n\t} else if (type == BTC_ASSOCIATE_START) {\n\t\tcoex_sta->wl_hi_pri_task1 = TRUE;\n\t\tcoex_sta->cnt_wl[BTC_CNT_WL_ARP] = 0;\n\t\tcoex_sta->wl_connecting = TRUE;\n\t\tbtc->btc_set_timer(btc, BTC_TIMER_WL_CONNPKT, 2);\n\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): 2G start\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\t/* Force antenna setup for no scan result issue */\n\t\trtw_btc_set_ant_path(btc, FC_EXCU, BTC_ANT_2G);\n\n\t\trtw_btc_run_coex(btc, BTC_RSN_2GCONSTART);\n\n\t\t/* To keep TDMA case during connect process,\n\t\t * to avoid changed by Btinfo and run_coex\n\t\t */\n\t\tcoex_sta->coex_freeze = TRUE;\n\t\tbtc->btc_set_timer(btc, BTC_TIMER_WL_COEXFREEZE, 5);\n\t} else {\n\t\tcoex_sta->wl_hi_pri_task1 = FALSE;\n\t\tcoex_sta->coex_freeze = FALSE;\n\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): 2G finish\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\trtw_btc_run_coex(btc, BTC_RSN_2GCONFINISH);\n\t}\n}\n\nvoid rtw_btc_ex_media_status_notify(struct btc_coexist *btc, u8 type)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tboolean wl_b_mode = FALSE;\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\n\tif (btc->manual_control || btc->stop_coex_dm)\n\t\treturn;\n\n\tif (type == BTC_MEDIA_CONNECT_5G) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): 5G\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\tbtc->btc_write_scbd(btc, BTC_SCBD_ACTIVE, TRUE);\n\n\t\trtw_btc_set_ant_path(btc, FC_EXCU, BTC_ANT_5G);\n\n\t\trtw_btc_run_coex(btc, BTC_RSN_5GMEDIA);\n\t} else if (type == BTC_MEDIA_CONNECT) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): 2G\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\tbtc->btc_write_scbd(btc, BTC_SCBD_ACTIVE, TRUE);\n\n\t\t/* Force antenna setup for no scan result issue */\n\t\trtw_btc_set_ant_path(btc, FC_EXCU, BTC_ANT_2G);\n\n\t\tbtc->btc_get(btc, BTC_GET_BL_WIFI_UNDER_B_MODE, &wl_b_mode);\n\n\t\t/* Set CCK Tx/Rx high Pri except 11b mode */\n\t\tif (wl_b_mode)/* CCK Rx */\n\t\t\trtw_btc_set_wl_pri_mask(btc, BTC_WLPRI_RX_CCK, 0);\n\t\telse /* CCK Rx */\n\t\t\trtw_btc_set_wl_pri_mask(btc, BTC_WLPRI_RX_CCK, 1);\n\n\t\trtw_btc_run_coex(btc, BTC_RSN_2GMEDIA);\n\t} else {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): disconnect!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t\tcoex_sta->cnt_wl[BTC_CNT_WL_ARP] = 0;\n\n\t\t/* CCK Rx, Tx response, Tx beacon = low pri */\n\t\tif (link_info_ext->num_of_active_port == 0)\n\t\t\trtw_btc_set_wl_pri_mask(btc, BTC_WLPRI_RX_CCK, 0);\n\n\t\tcoex_sta->wl_cck_lock_ever = FALSE;\n\t\tcoex_sta->wl_cck_lock = FALSE;\n\n\t\trtw_btc_run_coex(btc, BTC_RSN_MEDIADISCON);\n\t}\n\n\tbtc->btc_get(btc, BTC_GET_U1_IOT_PEER, &coex_sta->wl_iot_peer);\n\trtw_btc_update_wl_ch_info(btc, type);\n}\n\nvoid rtw_btc_ex_specific_packet_notify(struct btc_coexist *btc, u8 type)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tboolean under_4way = FALSE;\n\n\tif (btc->manual_control || btc->stop_coex_dm)\n\t\treturn;\n\n\tif (type & BTC_5G_BAND) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): 5G\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\trtw_btc_run_coex(btc, BTC_RSN_5GSPECIALPKT);\n\t\treturn;\n\t}\n\n\tbtc->btc_get(btc, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way);\n\n\tif (under_4way) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): under_4way!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\tcoex_sta->wl_hi_pri_task1 = TRUE;\n\t\tbtc->btc_set_timer(btc, BTC_TIMER_WL_SPECPKT, 2);\n\t} else if (type == BTC_PACKET_ARP) {\n\t\tcoex_sta->cnt_wl[BTC_CNT_WL_ARP]++;\n\n\t\tif (coex_sta->wl_hi_pri_task1) {\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], %s(): ARP cnt = %d\\n\",\n\t\t\t\t    __func__, coex_sta->cnt_wl[BTC_CNT_WL_ARP]);\n\t\t\tBTC_TRACE(trace_buf);\n\t\t}\n\t} else {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): DHCP or EAPOL Type = %d\\n\",\n\t\t\t    __func__, type);\n\t\tBTC_TRACE(trace_buf);\n\n\t\tcoex_sta->wl_hi_pri_task1 = TRUE;\n\t\tbtc->btc_set_timer(btc, BTC_TIMER_WL_SPECPKT, 2);\n\t}\n\n\tif (coex_sta->wl_hi_pri_task1)\n\t\trtw_btc_run_coex(btc, BTC_RSN_2GSPECIALPKT);\n}\n\nvoid rtw_btc_ex_bt_info_notify(struct btc_coexist *btc, u8 *tmp_buf, u8 length)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_coex_dm *coex_dm = &btc->coex_dm;\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\tu8 i, rsp_source = 0, type;\n\n\trsp_source = tmp_buf[0] & 0xf;\n\tif (rsp_source >= BTC_BTINFO_SRC_MAX)\n\t\treturn;\n\n\tcoex_sta->cnt_bt_info_c2h[rsp_source]++;\n\n\t/* bt_iqk_state-> 1: start, 0: ok, 2:fail  */\n\tif (rsp_source == BTC_BTINFO_SRC_BT_IQK) {\n\t\tcoex_sta->bt_iqk_state = tmp_buf[1];\n\t\tif (coex_sta->bt_iqk_state == 0x0)\n\t\t\tcoex_sta->cnt_bt[BTC_CNT_BT_IQK]++;\n\t\telse if (coex_sta->bt_iqk_state == 0x2)\n\t\t\tcoex_sta->cnt_bt[BTC_CNT_BT_IQKFAIL]++;\n\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], BT IQK by bt_info, data0 = 0x%02x\\n\",\n\t\t\t    tmp_buf[1]);\n\t\tBTC_TRACE(trace_buf);\n\t\treturn;\n\t}\n\n\tif (rsp_source == BTC_BTINFO_SRC_BT_SCBD) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], BT Scoreboard change notify by WL FW c2h, 0xaa = 0x%02x, 0xab = 0x%02x\\n\",\n\t\t\t    tmp_buf[1], tmp_buf[2]);\n\t\tBTC_TRACE(trace_buf);\n\t\trtw_btc_monitor_bt_enable(btc);\n\n\t\tif (coex_sta->bt_disabled != coex_sta->bt_disabled_pre) {\n\t\t\tcoex_sta->bt_disabled_pre = coex_sta->bt_disabled;\n\t\t\trtw_btc_run_coex(btc, BTC_RSN_BTINFO);\n\t\t}\n\t\treturn;\n\t}\n\n\tif (rsp_source == BTC_BTINFO_SRC_H2C60) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], H2C 0x60 content replied by WL FW: H2C_0x60 = [%02x %02x %02x %02x %02x]\\n\",\n\t\t\t    tmp_buf[1], tmp_buf[2], tmp_buf[3], tmp_buf[4],\n\t\t\t    tmp_buf[5]);\n\t\tBTC_TRACE(trace_buf);\n\n\t\tfor (i = 1; i <= 5; i++)\n\t\t\tcoex_dm->fw_tdma_para[i - 1] = tmp_buf[i];\n\t\treturn;\n\t}\n\n\tif (rsp_source == BTC_BTINFO_SRC_WL_FW) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], bt_info reply by WL FW\\n\");\n\t\tBTC_TRACE(trace_buf);\n\t\trtw_btc_update_bt_link_info(btc);\n\t\trtw_btc_run_coex(btc, BTC_RSN_BTINFO);\n\t\treturn;\n\t}\n\n\tif (rsp_source == BTC_BTINFO_SRC_BT_RSP ||\n\t    rsp_source == BTC_BTINFO_SRC_BT_ACT) {\n\t\tif (coex_sta->bt_disabled) {\n\t\t\tcoex_sta->bt_disabled = FALSE;\n\t\t\tcoex_sta->bt_reenable = TRUE;\n\t\t\tbtc->btc_set_timer(btc, BTC_TIMER_BT_REENABLE, 15);\n\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t\t    \"[BTCoex], BT enable detected by bt_info\\n\");\n\t\t\tBTC_TRACE(trace_buf);\n\t\t}\n\t}\n\n\tif (length != 7) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], Bt_info length = %d invalid!!\\n\",\n\t\t\t    length);\n\t\tBTC_TRACE(trace_buf);\n\t\treturn;\n\t}\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], Bt_info[%d], len=%d, data=[%02x %02x %02x %02x %02x %02x]\\n\",\n\t\t    tmp_buf[0], length, tmp_buf[1], tmp_buf[2], tmp_buf[3],\n\t\t    tmp_buf[4], tmp_buf[5], tmp_buf[6]);\n\tBTC_TRACE(trace_buf);\n\n\tfor (i = 0; i < 7; i++)\n\t\tcoex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];\n\n\tif (coex_sta->bt_info_c2h[rsp_source][1] == coex_sta->bt_info_lb2 &&\n\t    coex_sta->bt_info_c2h[rsp_source][2] == coex_sta->bt_info_lb3 &&\n\t    coex_sta->bt_info_c2h[rsp_source][3] == coex_sta->bt_info_hb0 &&\n\t    coex_sta->bt_info_c2h[rsp_source][4] == coex_sta->bt_info_hb1 &&\n\t    coex_sta->bt_info_c2h[rsp_source][5] == coex_sta->bt_info_hb2 &&\n\t    coex_sta->bt_info_c2h[rsp_source][6] == coex_sta->bt_info_hb3) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], Return because Btinfo duplicate!!\\n\");\n\t\tBTC_TRACE(trace_buf);\n\t\treturn;\n\t}\n\n\tcoex_sta->bt_info_lb2 = coex_sta->bt_info_c2h[rsp_source][1];\n\tcoex_sta->bt_info_lb3 = coex_sta->bt_info_c2h[rsp_source][2];\n\tcoex_sta->bt_info_hb0 = coex_sta->bt_info_c2h[rsp_source][3];\n\tcoex_sta->bt_info_hb1 = coex_sta->bt_info_c2h[rsp_source][4];\n\tcoex_sta->bt_info_hb2 = coex_sta->bt_info_c2h[rsp_source][5];\n\tcoex_sta->bt_info_hb3 = coex_sta->bt_info_c2h[rsp_source][6];\n\n\t/* ========== BT info Low-Byte2 ========== */\n\t/* if 0xff, it means BT is under WHCK test */\n\tcoex_sta->bt_whck_test = (coex_sta->bt_info_lb2 == 0xff);\n\tcoex_sta->bt_inq_page = ((coex_sta->bt_info_lb2 & BIT(2)) == BIT(2));\n\tcoex_sta->bt_acl_busy = ((coex_sta->bt_info_lb2 & BIT(3)) == BIT(3));\n\n\t/* ==========  BT info Low-Byte3 ========== */\n\tcoex_sta->cnt_bt[BTC_CNT_BT_RETRY] = coex_sta->bt_info_lb3 & 0xf;\n\n\tif (coex_sta->cnt_bt[BTC_CNT_BT_RETRY] >= 1)\n\t\tcoex_sta->cnt_bt[BTC_CNT_BT_POPEVENT]++;\n\n\tcoex_sta->bt_fix_2M = ((coex_sta->bt_info_lb3 & BIT(4)) == BIT(4));\n\n\tcoex_sta->bt_inq = ((coex_sta->bt_info_lb3 & BIT(5)) == BIT(5));\n\n\tcoex_sta->bt_mesh = ((coex_sta->bt_info_lb3 & BIT(6)) == BIT(6));\n\n\tif (coex_sta->bt_inq)\n\t\tcoex_sta->cnt_bt[BTC_CNT_BT_INQ]++;\n\n\tcoex_sta->bt_page = ((coex_sta->bt_info_lb3 & BIT(7)) == BIT(7));\n\n\tif (coex_sta->bt_page)\n\t\tcoex_sta->cnt_bt[BTC_CNT_BT_PAGE]++;\n\n\t/* ==========  BT info High-Byte0 ========== */\n\t/* unit: %, value-100 to translate to unit: dBm */\n\tif (btc->chip_para->bt_rssi_type == BTC_BTRSSI_RATIO) {\n\t\tcoex_sta->bt_rssi = coex_sta->bt_info_hb0 * 2 + 10;\n\t} else { /* coex_sta->bt_info_hb0 is just dbm */\n\t\tif (coex_sta->bt_info_hb0 <= 127)\n\t\t\tcoex_sta->bt_rssi = 100;\n\t\telse if (256 - coex_sta->bt_info_hb0 <= 100)\n\t\t\tcoex_sta->bt_rssi = 100 - (256 - coex_sta->bt_info_hb0);\n\t\telse\n\t\t\tcoex_sta->bt_rssi = 0;\n\t}\n\n\t/* ==========  BT info High-Byte1 ========== */\n\tcoex_sta->bt_ble_exist = ((coex_sta->bt_info_hb1 & BIT(0)) == BIT(0));\n\n\tif (coex_sta->bt_info_hb1 & BIT(1))\n\t\tcoex_sta->cnt_bt[BTC_CNT_BT_REINIT]++;\n\n\tif ((coex_sta->bt_info_hb1 & BIT(2)) ||\n\t    (coex_sta->bt_page && coex_sta->wl_pnp_wakeup)) {\n\t\tcoex_sta->cnt_bt[BTC_CNT_BT_SETUPLINK]++;\n\t\tcoex_sta->bt_setup_link = TRUE;\n\n\t\tif (coex_sta->bt_reenable)\n\t\t\tbtc->btc_set_timer(btc, BTC_TIMER_BT_RELINK, 6);\n\t\telse\n\t\t\tbtc->btc_set_timer(btc, BTC_TIMER_BT_RELINK, 2);\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], Re-Link start in BT info!!\\n\");\n\t\tBTC_TRACE(trace_buf);\n\t}\n\n\tif (coex_sta->bt_info_hb1 & BIT(3))\n\t\tcoex_sta->cnt_bt[BTC_CNT_BT_IGNWLANACT]++;\n\n\tcoex_sta->bt_ble_voice = ((coex_sta->bt_info_hb1 & BIT(4)) == BIT(4));\n\tcoex_sta->bt_ble_scan_en = ((coex_sta->bt_info_hb1 & BIT(5)) == BIT(5));\n\n\tif (coex_sta->bt_info_hb1 & BIT(6))\n\t\tcoex_sta->cnt_bt[BTC_CNT_BT_ROLESWITCH]++;\n\n\tcoex_sta->bt_multi_link = ((coex_sta->bt_info_hb1 & BIT(7)) == BIT(7));\n\n\t/* Here we need to resend some wifi info to BT */\n\t/* because bt is reset and loss of the info. */\n\t/*  Re-Init */\n\tif ((coex_sta->bt_info_hb1 & BIT(1))) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], BT Re-init, send wifi BW & Chnl to BT!!\\n\");\n\t\tBTC_TRACE(trace_buf);\n\t\tif (link_info_ext->is_connected)\n\t\t\ttype = BTC_MEDIA_CONNECT;\n\t\telse\n\t\t\ttype = BTC_MEDIA_DISCONNECT;\n\t\trtw_btc_update_wl_ch_info(btc, type);\n\t}\n\n\t/* If Ignore_WLanAct && not SetUp_Link */\n\tif ((coex_sta->bt_info_hb1 & BIT(3)) &&\n\t    (!(coex_sta->bt_info_hb1 & BIT(2)))) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\\n\");\n\t\tBTC_TRACE(trace_buf);\n\t\trtw_btc_ignore_wlan_act(btc, FC_EXCU, FALSE);\n\t}\n\n\t/* ==========  BT info High-Byte2 ========== */\n\tcoex_sta->bt_opp_exist = ((coex_sta->bt_info_hb2 & BIT(0)) == BIT(0));\n\n\tif (coex_sta->bt_info_hb2 & BIT(1))\n\t\tcoex_sta->cnt_bt[BTC_CNT_BT_AFHUPDATE]++;\n\n\tcoex_sta->bt_a2dp_active = ((coex_sta->bt_info_hb2 & BIT(2)) == BIT(2));\n\tcoex_sta->bt_slave = ((coex_sta->bt_info_hb2 & BIT(3)) == BIT(3));\n\tcoex_sta->bt_hid_slot = (coex_sta->bt_info_hb2 & 0x30) >> 4;\n\tcoex_sta->bt_hid_pair_num = (coex_sta->bt_info_hb2 & 0xc0) >> 6;\n\n\tif (coex_sta->bt_hid_pair_num > 0 && coex_sta->bt_hid_slot >= 2)\n\t\tcoex_sta->bt_418_hid_exist = TRUE;\n\telse if (coex_sta->bt_hid_pair_num == 0)\n\t\tcoex_sta->bt_418_hid_exist = FALSE;\n\n\t/* ==========  BT info High-Byte3 ========== */\n\tif ((coex_sta->bt_info_lb2 & 0x49) == 0x49)\n\t\tcoex_sta->bt_a2dp_bitpool = (coex_sta->bt_info_hb3 & 0x7f);\n\telse\n\t\tcoex_sta->bt_a2dp_bitpool = 0;\n\n\tcoex_sta->bt_a2dp_sink = ((coex_sta->bt_info_hb3 & BIT(7)) == BIT(7));\n\n\trtw_btc_update_bt_link_info(btc);\n\trtw_btc_run_coex(btc, BTC_RSN_BTINFO);\n}\n\nvoid rtw_btc_ex_wl_fwdbginfo_notify(struct btc_coexist *btc, u8 *tmp_buf,\n\t\t\t\t    u8 length)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tu8 i = 0, val = 0;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], WiFi Fw Dbg info = %d %d %d %d %d %d %d %d (len = %d)\\n\",\n\t\t    tmp_buf[0], tmp_buf[1], tmp_buf[2], tmp_buf[3], tmp_buf[4],\n\t\t    tmp_buf[5], tmp_buf[6], tmp_buf[7], length);\n\tBTC_TRACE(trace_buf);\n\n\tif (tmp_buf[0] != 0x8)\n\t\treturn;\n\n\tfor (i = 1; i <= 7; i++) {\n\t\tval = coex_sta->wl_fw_dbg_info_pre[i];\n\t\tif (tmp_buf[i] >= val)\n\t\t\tcoex_sta->wl_fw_dbg_info[i] = tmp_buf[i] - val;\n\t\telse\n\t\t\tcoex_sta->wl_fw_dbg_info[i] = 255 - val + tmp_buf[i];\n\n\t\tcoex_sta->wl_fw_dbg_info_pre[i] = tmp_buf[i];\n\t}\n\n\t/* wl_fwdbginfo_notify is auto send by WL FW if TDMA slot toggle = 20\n\t * coex_sta->wl_fw_dbg_info[6] = TDMA slot toggle\n\t * For debug, TDMA slot toggle should be calculated by 2-second\n\t */\n\tcoex_sta->cnt_wl[BTC_CNT_WL_FW_NOTIFY]++;\n\trtw_btc_wl_ccklock_action(btc);\n}\n\nvoid rtw_btc_ex_rx_rate_change_notify(struct btc_coexist *btc,\n\t\t\t\t      BOOLEAN is_data_frame, u8 btc_rate_id)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\n\tif (is_data_frame)\n\t\tcoex_sta->wl_rx_rate = btc_rate_id;\n\n\telse\n\t\tcoex_sta->wl_rts_rx_rate = btc_rate_id;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], %s(): rate id = %d, RTS_Rate = %d\\n\", __func__,\n\t\t    coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_wl_ccklock_detect(btc);\n}\n\nvoid rtw_btc_ex_tx_rate_change_notify(struct btc_coexist *btc, u8 tx_rate,\n\t\t\t\t      u8 tx_retry_ratio, u8 macid)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], %s(): Tx_Rate = %d, Tx_Retry_Ratio = %d, macid =%d\\n\",\n\t\t    __func__, tx_rate, tx_retry_ratio, macid);\n\tBTC_TRACE(trace_buf);\n\n\tcoex_sta->wl_tx_rate = tx_rate;\n\tcoex_sta->wl_tx_retry_ratio = tx_retry_ratio;\n\tcoex_sta->wl_tx_macid = macid;\n}\n\nvoid rtw_btc_ex_rf_status_notify(struct btc_coexist *btc, u8 type)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\n\tif (type == BTC_RF_ON) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): RF is turned ON!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t\tbtc->stop_coex_dm = FALSE;\n\t\tbtc->wl_rf_state_off = FALSE;\n\n\t} else if (type == BTC_RF_OFF) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): RF is turned Off!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\tbtc->btc_write_scbd(btc, BTC_SCBD_ALL, FALSE);\n\n\t\trtw_btc_tdma(btc, FC_EXCU, 0);\n\n\t\trtw_btc_set_ant_path(btc, FC_EXCU, BTC_ANT_WOFF);\n\t\trtw_btc_ignore_wlan_act(btc, FC_EXCU, TRUE);\n\n\t\tbtc->stop_coex_dm = TRUE;\n\t\tbtc->wl_rf_state_off = TRUE;\n\n\t\t/* must place in the last step */\n\t\trtw_btc_update_wl_ch_info(btc, BTC_MEDIA_DISCONNECT);\n\t}\n}\n\nvoid rtw_btc_ex_halt_notify(struct btc_coexist *btc)\n{\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_ex_media_status_notify(btc, BTC_MEDIA_DISCONNECT);\n\n\trtw_btc_ignore_wlan_act(btc, FC_EXCU, TRUE);\n\n\trtw_btc_set_ant_path(btc, FC_EXCU, BTC_ANT_WOFF);\n\n\tbtc->btc_write_scbd(btc, BTC_SCBD_ALL, FALSE);\n\n\tbtc->stop_coex_dm = TRUE;\n\n\t/* must place in the last step */\n\trtw_btc_update_wl_ch_info(btc, BTC_MEDIA_DISCONNECT);\n}\n\nvoid rtw_btc_ex_pnp_notify(struct btc_coexist *btc, u8 pnp_state)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tstruct btc_wifi_link_info_ext *link_info_ext = &btc->wifi_link_info_ext;\n\tu8 phase;\n\n\tif (pnp_state == BTC_WIFI_PNP_SLEEP ||\n\t    pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT) {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): Sleep\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\n\t\tbtc->btc_write_scbd(btc, BTC_SCBD_ALL, FALSE);\n\n\t\tif (pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT) {\n\t\t\tif (link_info_ext->is_all_under_5g)\n\t\t\t\tphase = BTC_ANT_5G;\n\t\t\telse\n\t\t\t\tphase = BTC_ANT_2G;\n\t\t} else {\n\t\t\tphase = BTC_ANT_WOFF;\n\t\t}\n\t\trtw_btc_set_ant_path(btc, FC_EXCU, phase);\n\n\t\tbtc->stop_coex_dm = TRUE;\n\t} else {\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): Wake up\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t\tcoex_sta->wl_pnp_wakeup = TRUE;\n\t\tbtc->btc_set_timer(btc, BTC_TIMER_WL_PNPWAKEUP, 3);\n\n\t\t/*WoWLAN*/\n\t\tif (coex_sta->wl_pnp_state_pre == BTC_WIFI_PNP_SLEEP_KEEP_ANT ||\n\t\t    pnp_state == BTC_WIFI_PNP_WOWLAN) {\n\t\t\tbtc->stop_coex_dm = FALSE;\n\t\t\trtw_btc_run_coex(btc, BTC_RSN_PNP);\n\t\t}\n\t}\n\n\tcoex_sta->wl_pnp_state_pre = pnp_state;\n}\n\nvoid rtw_btc_ex_coex_dm_reset(struct btc_coexist *btc)\n{\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, \"[BTCoex], %s()\\n\", __func__);\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_init_hw_config(btc, FALSE);\n\trtw_btc_init_coex_dm(btc);\n}\n\nvoid rtw_btc_ex_periodical(struct btc_coexist *btc)\n{\n\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t    \"[BTCoex], ============== Periodical ==============\\n\");\n\tBTC_TRACE(trace_buf);\n\n\trtw_btc_monitor_bt_ctr(btc);\n\trtw_btc_wl_noisy_detect(btc);\n}\n\nvoid rtw_btc_ex_timerup_notify(struct btc_coexist *btc, u32 type)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tboolean is_change = FALSE;\n\n\tif (type & BIT(BTC_TIMER_WL_STAYBUSY)) {\n\t\tif (!coex_sta->wl_busy_pre) {\n\t\t\tcoex_sta->wl_gl_busy = FALSE;\n\t\t\tis_change = TRUE;\n\t\t\tbtc->btc_write_scbd(btc, BTC_SCBD_WLBUSY, FALSE);\n\t\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): WL busy -> idle!!\\n\", __func__);\n\t\t\tBTC_TRACE(trace_buf);\n\t\t}\n\t}\n\n\t /*avoid no connect finish notify */\n\tif (type & BIT(BTC_TIMER_WL_COEXFREEZE)) {\n\t\tcoex_sta->coex_freeze = FALSE;\n\t\tcoex_sta->wl_hi_pri_task1 = FALSE;\n\t\tis_change = TRUE;\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): Coex is de-freeze!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t}\n\n\tif (type & BIT(BTC_TIMER_WL_SPECPKT)) {\n\t\tif (!coex_sta->coex_freeze) {\n\t\t\tcoex_sta->wl_hi_pri_task1 = FALSE;\n\t\t\tis_change = TRUE;\n\t\t}\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): WL SPECPKT finish!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t}\n\n\t/*for A2DP glitch during connecting AP*/\n\tif (type & BIT(BTC_TIMER_WL_CONNPKT)) {\n\t\tcoex_sta->wl_connecting = FALSE;\n\t\tis_change = TRUE;\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): WL connecting stop!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t}\n\n\tif (type & BIT(BTC_TIMER_WL_PNPWAKEUP)) {\n\t\tcoex_sta->wl_pnp_wakeup = FALSE;\n\t\tis_change = TRUE;\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): WL pnp wakeup stop!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t}\n\n\tif (type & BIT(BTC_TIMER_WL_CCKLOCK)) {\n\t\tif (coex_sta->wl_cck_lock_pre) {\n\t\t\tcoex_sta->wl_cck_lock_ever = TRUE;\n\t\t\tis_change = TRUE;\n\t\t}\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): WL CCK Lock Detect!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t}\n\n\tif (type & BIT(BTC_TIMER_BT_RELINK)) {\n\t\tcoex_sta->bt_setup_link = FALSE;\n\t\tis_change = TRUE;\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): Re-Link stop!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t}\n\n\tif (type & BIT(BTC_TIMER_BT_REENABLE)) {\n\t\tcoex_sta->bt_reenable = FALSE;\n\t\tis_change = TRUE;\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): BT renable finish!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t}\n\n\tif (is_change)\n\t\trtw_btc_run_coex(btc, BTC_RSN_TIMERUP);\n}\n\nvoid rtw_btc_ex_wl_status_change_notify(struct btc_coexist *btc, u32 type)\n{\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tboolean is_change = FALSE;\n\n\tif (type & BIT(BTC_WLSTATUS_CHANGE_TOIDLE)) { /* if busy->idle */\n\t\tcoex_sta->wl_busy_pre = FALSE;\n\t\tbtc->btc_set_timer(btc, BTC_TIMER_WL_STAYBUSY, 6);\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): WL busy -> idle!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t}\n\n\tif (type & BIT(BTC_WLSTATUS_CHANGE_TOBUSY)) { /* if idle->busy */\n\t\tcoex_sta->wl_gl_busy = TRUE;\n\t\tcoex_sta->wl_busy_pre = TRUE;\n\t\tis_change = TRUE;\n\t\tbtc->btc_write_scbd(btc, BTC_SCBD_WLBUSY, TRUE);\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): WL idle -> busy!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t}\n\n\tif (type & BIT(BTC_WLSTATUS_CHANGE_RSSI)) { /* if RSSI change */\n\t\tis_change = TRUE;\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): WL RSSI change!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t}\n\n\tif (type & BIT(BTC_WLSTATUS_CHANGE_LINKINFO)) { /* if linkinfo change */\n\t\tis_change = TRUE;\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): WL LinkInfo change!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t}\n\n\tif (type & BIT(BTC_WLSTATUS_CHANGE_DIR)) { /*if WL UL-DL change*/\n\t\tis_change = TRUE;\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s(): WL UL-DL change!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t}\n\n\tif (type & BIT(BTC_WLSTATUS_CHANGE_NOISY)) { /*if noisy level change*/\n\t\tis_change = TRUE;\n\t\tBTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s():Noisy Level change!!\\n\", __func__);\n\t\tBTC_TRACE(trace_buf);\n\t}\n\n\tif (is_change)\n\t\trtw_btc_run_coex(btc, BTC_RSN_WLSTATUS);\n}\n#endif\n /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */\n"
  },
  {
    "path": "hal/btc/halbtccommon.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)\n\n/* *******************************************\n * The following is interface which will notify coex module.\n * ********************************************/\nvoid rtw_btc_ex_power_on_setting(struct btc_coexist *btc);\nvoid rtw_btc_ex_pre_load_firmware(struct btc_coexist *btc);\nvoid rtw_btc_ex_init_hw_config(struct btc_coexist *btc, boolean wifi_only);\nvoid rtw_btc_ex_init_coex_dm(struct btc_coexist *btc);\nvoid rtw_btc_ex_ips_notify(struct btc_coexist *btc, u8 type);\nvoid rtw_btc_ex_lps_notify(struct btc_coexist *btc, u8 type);\nvoid rtw_btc_ex_scan_notify(struct btc_coexist *btc, u8 type);\nvoid rtw_btc_ex_scan_notify_without_bt(struct btc_coexist *btc, u8 type);\nvoid rtw_btc_ex_switchband_notify(struct btc_coexist *btc, u8 type);\nvoid rtw_btc_ex_switchband_notify_without_bt(struct btc_coexist *btc, u8 type);\nvoid rtw_btc_ex_connect_notify(struct btc_coexist *btc, u8 type);\nvoid rtw_btc_ex_media_status_notify(struct btc_coexist *btc, u8 type);\nvoid rtw_btc_ex_specific_packet_notify(struct btc_coexist *btc, u8 type);\nvoid rtw_btc_ex_bt_info_notify(struct btc_coexist *btc, u8 *tmp_buf, u8 length);\nvoid rtw_btc_ex_wl_fwdbginfo_notify(struct btc_coexist *btc, u8 *tmp_buf,\n\t\t\t\t    u8 length);\nvoid rtw_btc_ex_rx_rate_change_notify(struct btc_coexist *btc,\n\t\t\t\t      BOOLEAN is_data_frame,\n\t\t\t\t      u8 btc_rate_id);\nvoid rtw_btc_ex_tx_rate_change_notify(struct btc_coexist *btc, u8 tx_rate,\n\t\t\t\t      u8 tx_retry_ratio, u8 macid);\nvoid rtw_btc_ex_rf_status_notify(struct btc_coexist *btc, u8 type);\nvoid rtw_btc_ex_halt_notify(struct btc_coexist *btc);\nvoid rtw_btc_ex_pnp_notify(struct btc_coexist *btc, u8 pnp_state);\nvoid rtw_btc_ex_coex_dm_reset(struct btc_coexist *btc);\nvoid rtw_btc_ex_periodical(struct btc_coexist *btc);\nvoid rtw_btc_ex_timerup_notify(struct btc_coexist *btc, u32 type);\nvoid rtw_btc_ex_wl_status_change_notify(struct btc_coexist *btc, u32 type);\nvoid rtw_btc_ex_display_simple_coex_info(struct btc_coexist *btc);\nvoid rtw_btc_ex_display_coex_info(struct btc_coexist *btc);\nvoid rtw_btc_ex_dbg_control(struct btc_coexist *btc, u8 op_code, u8 op_len,\n\t\t\t    u8 *pdata);\n\n#else\n#define rtw_btc_ex_power_on_setting(btc)\n#define rtw_btc_ex_pre_load_firmware(btc)\n#define rtw_btc_ex_init_hw_config(btc, wifi_only)\n#define rtw_btc_ex_init_coex_dm(btc)\n#define rtw_btc_ex_ips_notify(btc, type)\n#define rtw_btc_ex_lps_notify(btc, type)\n#define rtw_btc_ex_scan_notify(btc, type)\n#define rtw_btc_ex_scan_notify_without_bt(btc, type)\n#define rtw_btc_ex_switchband_notify(btc, type)\n#define rtw_btc_ex_switchband_notify_without_bt(btc, type)\n#define rtw_btc_ex_connect_notify(btc, type)\n#define rtw_btc_ex_media_status_notify(btc, type)\n#define rtw_btc_ex_specific_packet_notify(btc, type)\n#define rtw_btc_ex_bt_info_notify(btc, tmp_buf, length)\n#define rtw_btc_ex_wl_fwdbginfo_notify(btc, tmp_buf, length)\n#define rtw_btc_ex_rx_rate_change_notify(btc, is_data_frame, btc_rate_id)\n#define rtw_btc_ex_tx_rate_change_notify(btcoexist, tx_rate, tx_retry_ratio, \\\n\t\t\t\t       macid)\n#define rtw_btc_ex_rf_status_notify(btc, type)\n#define rtw_btc_ex_halt_notify(btc)\n#define rtw_btc_ex_pnp_notify(btc, pnp_state)\n#define rtw_btc_ex_coex_dm_reset(btc)\n#define rtw_btc_ex_periodical(btc)\n#define rtw_btc_ex_timerup_notify(btc, type)\n#define rtw_btc_ex_wl_status_change_notify(btc, type)\n#define rtw_btc_ex_display_coex_info(btc)\n#define rtw_btc_ex_dbg_control(btc, op_code, op_len, pdata)\n#endif\n"
  },
  {
    "path": "hal/btc/halbtcoutsrc.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef\t__HALBTC_OUT_SRC_H__\n#define __HALBTC_OUT_SRC_H__\n\nenum {\n\tBTC_CCK_1,\n\tBTC_CCK_2,\n\tBTC_CCK_5_5,\n\tBTC_CCK_11,\n\tBTC_OFDM_6,\n\tBTC_OFDM_9,\n\tBTC_OFDM_12,\n\tBTC_OFDM_18,\n\tBTC_OFDM_24,\n\tBTC_OFDM_36,\n\tBTC_OFDM_48,\n\tBTC_OFDM_54,\n\tBTC_MCS_0,\n\tBTC_MCS_1,\n\tBTC_MCS_2,\n\tBTC_MCS_3,\n\tBTC_MCS_4,\n\tBTC_MCS_5,\n\tBTC_MCS_6,\n\tBTC_MCS_7,\n\tBTC_MCS_8,\n\tBTC_MCS_9,\n\tBTC_MCS_10,\n\tBTC_MCS_11,\n\tBTC_MCS_12,\n\tBTC_MCS_13,\n\tBTC_MCS_14,\n\tBTC_MCS_15,\n\tBTC_MCS_16,\n\tBTC_MCS_17,\n\tBTC_MCS_18,\n\tBTC_MCS_19,\n\tBTC_MCS_20,\n\tBTC_MCS_21,\n\tBTC_MCS_22,\n\tBTC_MCS_23,\n\tBTC_MCS_24,\n\tBTC_MCS_25,\n\tBTC_MCS_26,\n\tBTC_MCS_27,\n\tBTC_MCS_28,\n\tBTC_MCS_29,\n\tBTC_MCS_30,\n\tBTC_MCS_31,\n\tBTC_VHT_1SS_MCS_0,\n\tBTC_VHT_1SS_MCS_1,\n\tBTC_VHT_1SS_MCS_2,\n\tBTC_VHT_1SS_MCS_3,\n\tBTC_VHT_1SS_MCS_4,\n\tBTC_VHT_1SS_MCS_5,\n\tBTC_VHT_1SS_MCS_6,\n\tBTC_VHT_1SS_MCS_7,\n\tBTC_VHT_1SS_MCS_8,\n\tBTC_VHT_1SS_MCS_9,\n\tBTC_VHT_2SS_MCS_0,\n\tBTC_VHT_2SS_MCS_1,\n\tBTC_VHT_2SS_MCS_2,\n\tBTC_VHT_2SS_MCS_3,\n\tBTC_VHT_2SS_MCS_4,\n\tBTC_VHT_2SS_MCS_5,\n\tBTC_VHT_2SS_MCS_6,\n\tBTC_VHT_2SS_MCS_7,\n\tBTC_VHT_2SS_MCS_8,\n\tBTC_VHT_2SS_MCS_9,\n\tBTC_VHT_3SS_MCS_0,\n\tBTC_VHT_3SS_MCS_1,\n\tBTC_VHT_3SS_MCS_2,\n\tBTC_VHT_3SS_MCS_3,\n\tBTC_VHT_3SS_MCS_4,\n\tBTC_VHT_3SS_MCS_5,\n\tBTC_VHT_3SS_MCS_6,\n\tBTC_VHT_3SS_MCS_7,\n\tBTC_VHT_3SS_MCS_8,\n\tBTC_VHT_3SS_MCS_9,\n\tBTC_VHT_4SS_MCS_0,\n\tBTC_VHT_4SS_MCS_1,\n\tBTC_VHT_4SS_MCS_2,\n\tBTC_VHT_4SS_MCS_3,\n\tBTC_VHT_4SS_MCS_4,\n\tBTC_VHT_4SS_MCS_5,\n\tBTC_VHT_4SS_MCS_6,\n\tBTC_VHT_4SS_MCS_7,\n\tBTC_VHT_4SS_MCS_8,\n\tBTC_VHT_4SS_MCS_9,\n\tBTC_MCS_32,\n\tBTC_UNKNOWN,\n\tBTC_PKT_MGNT,\n\tBTC_PKT_CTRL,\n\tBTC_PKT_UNKNOWN,\n\tBTC_PKT_NOT_FOR_ME,\n\tBTC_RATE_MAX\n};\n\nenum {\n\tBTC_MULTIPORT_SCC,\n\tBTC_MULTIPORT_MCC_DUAL_CHANNEL,\n\tBTC_MULTIPORT_MCC_DUAL_BAND,\n\tBTC_MULTIPORT_MAX\n};\n\n#define\t\tBTC_COEX_8822B_COMMON_CODE\t0\n#define\t\tBTC_COEX_OFFLOAD\t\t\t0\n#define\t\tBTC_TMP_BUF_SHORT\t\t20\n\nextern u1Byte\tgl_btc_trace_buf[];\n#define\t\tBTC_SPRINTF\t\t\trsprintf\n#define\t\tBTC_TRACE(_MSG_)\\\ndo {\\\n\tif (GLBtcDbgType[COMP_COEX] & BIT(DBG_LOUD)) {\\\n\t\tRTW_INFO(\"%s\", _MSG_);\\\n\t} \\\n} while (0)\n#define\t\tBT_PrintData(adapter, _MSG_, len, data)\tRTW_DBG_DUMP((_MSG_), data, len)\n\n\n#define\t\tNORMAL_EXEC\t\t\t\t\tFALSE\n#define\t\tFORCE_EXEC\t\t\t\t\t\tTRUE\n\n#define\t\tNM_EXCU\t\t\t\t\t\tFALSE\n#define\t\tFC_EXCU\t\t\t\t\t\tTRUE\n\n#define\t\tBTC_RF_OFF\t\t\t\t\t0x0\n#define\t\tBTC_RF_ON\t\t\t\t\t0x1\n\n#define\t\tBTC_RF_A\t\t\t\t\t0x0\n#define\t\tBTC_RF_B\t\t\t\t\t0x1\n#define\t\tBTC_RF_C\t\t\t\t\t0x2\n#define\t\tBTC_RF_D\t\t\t\t\t0x3\n\n#define\t\tBTC_SMSP\t\t\t\tSINGLEMAC_SINGLEPHY\n#define\t\tBTC_DMDP\t\t\t\tDUALMAC_DUALPHY\n#define\t\tBTC_DMSP\t\t\t\tDUALMAC_SINGLEPHY\n#define\t\tBTC_MP_UNKNOWN\t\t0xff\n\n#define\t\tBT_COEX_ANT_TYPE_PG\t\t\t0\n#define\t\tBT_COEX_ANT_TYPE_ANTDIV\t\t1\n#define\t\tBT_COEX_ANT_TYPE_DETECTED\t2\n\n#define\t\tBTC_MIMO_PS_STATIC\t\t\t0\t/* 1ss */\n#define\t\tBTC_MIMO_PS_DYNAMIC\t\t\t1\t/* 2ss */\n\n#define\t\tBTC_RATE_DISABLE\t\t\t0\n#define\t\tBTC_RATE_ENABLE\t\t\t\t1\n\n/* single Antenna definition */\n#define\t\tBTC_ANT_PATH_WIFI\t\t\t0\n#define\t\tBTC_ANT_PATH_BT\t\t\t\t1\n#define\t\tBTC_ANT_PATH_PTA\t\t\t2\n#define\t\tBTC_ANT_PATH_WIFI5G\t\t\t3\n#define\t\tBTC_ANT_PATH_AUTO\t\t\t4\n/* dual Antenna definition */\n#define\t\tBTC_ANT_WIFI_AT_MAIN\t\t0\n#define\t\tBTC_ANT_WIFI_AT_AUX\t\t\t1\n#define\t\tBTC_ANT_WIFI_AT_DIVERSITY\t2\n/* coupler Antenna definition */\n#define\t\tBTC_ANT_WIFI_AT_CPL_MAIN\t0\n#define\t\tBTC_ANT_WIFI_AT_CPL_AUX\t\t1\n\ntypedef enum _BTC_POWERSAVE_TYPE {\n\tBTC_PS_WIFI_NATIVE\t\t\t= 0,\t/* wifi original power save behavior */\n\tBTC_PS_LPS_ON\t\t\t\t= 1,\n\tBTC_PS_LPS_OFF\t\t\t\t= 2,\n\tBTC_PS_MAX\n} BTC_POWERSAVE_TYPE, *PBTC_POWERSAVE_TYPE;\n\ntypedef enum _BTC_BT_REG_TYPE {\n\tBTC_BT_REG_RF\t\t\t\t\t\t= 0,\n\tBTC_BT_REG_MODEM\t\t\t\t\t= 1,\n\tBTC_BT_REG_BLUEWIZE\t\t\t\t\t= 2,\n\tBTC_BT_REG_VENDOR\t\t\t\t\t= 3,\n\tBTC_BT_REG_LE\t\t\t\t\t\t= 4,\n\tBTC_BT_REG_MAX\n} BTC_BT_REG_TYPE, *PBTC_BT_REG_TYPE;\n\ntypedef enum _BTC_CHIP_INTERFACE {\n\tBTC_INTF_UNKNOWN\t= 0,\n\tBTC_INTF_PCI\t\t\t= 1,\n\tBTC_INTF_USB\t\t\t= 2,\n\tBTC_INTF_SDIO\t\t= 3,\n\tBTC_INTF_MAX\n} BTC_CHIP_INTERFACE, *PBTC_CHIP_INTERFACE;\n\ntypedef enum _BTC_CHIP_TYPE {\n\tBTC_CHIP_UNDEF\t\t= 0,\n\tBTC_CHIP_CSR_BC4\t\t= 1,\n\tBTC_CHIP_CSR_BC8\t\t= 2,\n\tBTC_CHIP_RTL8723A\t\t= 3,\n\tBTC_CHIP_RTL8821\t\t= 4,\n\tBTC_CHIP_RTL8723B\t\t= 5,\n\tBTC_CHIP_RTL8822B \t\t= 6,\n\tBTC_CHIP_RTL8822C \t\t= 7,\n\tBTC_CHIP_RTL8821C \t\t= 8,\n\tBTC_CHIP_RTL8821A \t\t= 9,\n\tBTC_CHIP_RTL8723D \t\t= 10,\n\tBTC_CHIP_RTL8703B \t\t= 11,\n\tBTC_CHIP_RTL8725A \t\t= 12,\n\tBTC_CHIP_MAX\n} BTC_CHIP_TYPE, *PBTC_CHIP_TYPE;\n\n/* following is for wifi link status */\n#define\t\tWIFI_STA_CONNECTED\t\t\t\tBIT0\n#define\t\tWIFI_AP_CONNECTED\t\t\t\tBIT1\n#define\t\tWIFI_HS_CONNECTED\t\t\t\tBIT2\n#define\t\tWIFI_P2P_GO_CONNECTED\t\t\tBIT3\n#define\t\tWIFI_P2P_GC_CONNECTED\t\t\tBIT4\n\n/* following is for command line utility */\n#define\tCL_SPRINTF\trsprintf\n#define\tCL_PRINTF\tDCMD_Printf\n#define CL_STRNCAT(dst, dst_size, src, src_size) rstrncat(dst, src, src_size)\n\nstatic const char *const glbt_info_src[] = {\n\t\"BT Info[wifi fw]\",\n\t\"BT Info[bt rsp]\",\n\t\"BT Info[bt auto report]\",\n};\n\n#define BTC_INFO_FTP\t\tBIT(7)\n#define BTC_INFO_A2DP\t\tBIT(6)\n#define BTC_INFO_HID\t\tBIT(5)\n#define BTC_INFO_SCO_BUSY\t\tBIT(4)\n#define BTC_INFO_ACL_BUSY\t\tBIT(3)\n#define BTC_INFO_INQ_PAGE\t\tBIT(2)\n#define BTC_INFO_SCO_ESCO\t\tBIT(1)\n#define BTC_INFO_CONNECTION\tBIT(0)\n\n#define BTC_BTINFO_LENGTH_MAX 10\n\nenum btc_gnt_setup_state {\n\tBTC_GNT_SET_SW_LOW\t= 0x0,\n\tBTC_GNT_SET_SW_HIGH\t= 0x1,\n\tBTC_GNT_SET_HW_PTA\t= 0x2,\n\tBTC_GNT_SET_MAX\n};\n\nenum btc_gnt_setup_state_2 {\n\tBTC_GNT_SW_LOW\t\t= 0x0,\n\tBTC_GNT_SW_HIGH\t\t= 0x1,\n\tBTC_GNT_HW_PTA\t\t= 0x2,\n\tBTC_GNT_MAX\n};\n\nenum btc_path_ctrl_owner {\n\tBTC_OWNER_BT\t\t= 0x0,\n\tBTC_OWNER_WL\t\t= 0x1,\n\tBTC_OWNER_MAX\n};\n\nenum btc_gnt_ctrl_type {\n\tBTC_GNT_CTRL_BY_PTA\t= 0x0,\n\tBTC_GNT_CTRL_BY_SW\t= 0x1,\n\tBTC_GNT_CTRL_MAX\n};\n\nenum btc_gnt_ctrl_block {\n\tBTC_GNT_BLOCK_RFC_BB\t= 0x0,\n\tBTC_GNT_BLOCK_RFC\t= 0x1,\n\tBTC_GNT_BLOCK_BB\t= 0x2,\n\tBTC_GNT_BLOCK_MAX\n};\n\nenum btc_lte_coex_table_type {\n\tBTC_CTT_WL_VS_LTE\t= 0x0,\n\tBTC_CTT_BT_VS_LTE\t= 0x1,\n\tBTC_CTT_MAX\n};\n\nenum btc_lte_break_table_type {\n\tBTC_LBTT_WL_BREAK_LTE\t= 0x0,\n\tBTC_LBTT_BT_BREAK_LTE\t= 0x1,\n\tBTC_LBTT_LTE_BREAK_WL\t= 0x2,\n\tBTC_LBTT_LTE_BREAK_BT\t= 0x3,\n\tBTC_LBTT_MAX\n};\n\nenum btc_btinfo_src {\n\tBTC_BTINFO_SRC_WL_FW\t= 0x0,\n\tBTC_BTINFO_SRC_BT_RSP\t= 0x1,\n\tBTC_BTINFO_SRC_BT_ACT\t= 0x2,\n\tBTC_BTINFO_SRC_BT_IQK\t= 0x3,\n\tBTC_BTINFO_SRC_BT_SCBD\t= 0x4,\n\tBTC_BTINFO_SRC_H2C60\t= 0x5,\n\tBTC_BTINFO_SRC_MAX\n};\n\nenum btc_bt_profile {\n\tBTC_BTPROFILE_NONE\t\t= 0,\n\tBTC_BTPROFILE_HFP\t\t= BIT(0),\n\tBTC_BTPROFILE_HID\t\t= BIT(1),\n\tBTC_BTPROFILE_A2DP\t\t= BIT(2),\n\tBTC_BTPROFILE_PAN\t\t= BIT(3),\n\tBTC_BTPROFILE_MAX\t\t= 0xf\n};\n\nstatic const char *const bt_profile_string[] = {\n\t\"None\",\n\t\"HFP\",\n\t\"HID\",\n\t\"HID + HFP\",\n\t\"A2DP\",\n\t\"A2DP + HFP\",\n\t\"A2DP + HID\",\n\t\"PAN + HID + HFP\",\n\t\"PAN\",\n\t\"PAN + HFP\",\n\t\"PAN + HID\",\n\t\"PAN + HID + HFP\",\n\t\"PAN + A2DP\",\n\t\"PAN + A2DP + HFP\",\n\t\"PAN + A2DP + HID\",\n\t\"PAN + A2DP + HID + HFP\"\n};\n\nenum btc_bt_status {\n\tBTC_BTSTATUS_NCON_IDLE\t\t= 0x0,\n\tBTC_BTSTATUS_CON_IDLE\t\t= 0x1,\n\tBTC_BTSTATUS_INQ_PAGE\t\t= 0x2,\n\tBTC_BTSTATUS_ACL_BUSY\t\t= 0x3,\n\tBTC_BTSTATUS_SCO_BUSY\t\t= 0x4,\n\tBTC_BTSTATUS_ACL_SCO_BUSY\t= 0x5,\n\tBTC_BTSTATUS_MAX\n};\n\nstatic const char *const bt_status_string[] = {\n\t\"BT Non-Connected-idle\",\n\t\"BT Connected-idle\",\n\t\"BT Inq-page\",\n\t\"BT ACL-busy\",\n\t\"BT SCO-busy\",\n\t\"BT ACL-SCO-busy\",\n\t\"BT Non-Defined-state\"\n};\n\nenum btc_coex_algo {\n\tBTC_COEX_NOPROFILE\t\t= 0x0,\n\tBTC_COEX_HFP\t\t\t= 0x1,\n\tBTC_COEX_HID\t\t\t= 0x2,\n\tBTC_COEX_A2DP\t\t\t= 0x3,\n\tBTC_COEX_PAN\t\t\t= 0x4,\n\tBTC_COEX_A2DP_HID\t\t= 0x5,\n\tBTC_COEX_A2DP_PAN\t\t= 0x6,\n\tBTC_COEX_PAN_HID\t\t= 0x7,\n\tBTC_COEX_A2DP_PAN_HID\t\t= 0x8,\n\tBTC_COEX_MAX\n};\n\nstatic const char *const coex_algo_string[] = {\n\t\"No Profile\",\n\t\"HFP\",\n\t\"HID\",\n\t\"A2DP\",\n\t\"PAN\",\n\t\"A2DP + HID\",\n\t\"A2DP + PAN\",\n\t\"PAN + HID\",\n\t\"A2DP + PAN + HID\"\n};\n\nenum btc_ext_ant_switch_type {\n\tBTC_SWITCH_NONE\t= 0x0,\n\tBTC_SWITCH_SPDT\t= 0x1,\n\tBTC_SWITCH_SP3T\t= 0x2,\n\tBTC_SWITCH_ANTMAX\n};\n\nenum btc_ext_ant_switch_ctrl_type {\n\tBTC_SWITCH_CTRL_BY_BBSW\t\t= 0x0,\n\tBTC_SWITCH_CTRL_BY_PTA\t\t= 0x1,\n\tBTC_SWITCH_CTRL_BY_ANTDIV\t= 0x2,\n\tBTC_SWITCH_CTRL_BY_MAC\t\t= 0x3,\n\tBTC_SWITCH_CTRL_BY_BT\t\t= 0x4,\n\tBTC_SWITCH_CTRL_BY_FW\t\t= 0x5,\n\tBTC_SWITCH_CTRL_MAX\n};\n\nenum btc_ext_ant_switch_pos_type {\n\tBTC_SWITCH_TO_BT\t\t= 0x0,\n\tBTC_SWITCH_TO_WLG\t\t= 0x1,\n\tBTC_SWITCH_TO_WLA\t\t= 0x2,\n\tBTC_SWITCH_TO_NOCARE\t\t= 0x3,\n\tBTC_SWITCH_TO_WLG_BT\t\t= 0x4,\n\tBTC_SWITCH_TO_MAX\n};\n\nenum btx_set_ant_phase {\n\tBTC_ANT_INIT\t\t\t= 0x0,\n\tBTC_ANT_WONLY\t\t\t= 0x1,\n\tBTC_ANT_WOFF\t\t\t= 0x2,\n\tBTC_ANT_2G\t\t\t= 0x3,\n\tBTC_ANT_5G\t\t\t= 0x4,\n\tBTC_ANT_BTMP\t\t\t= 0x5,\n\tBTC_ANT_POWERON\t\t\t= 0x6,\n\tBTC_ANT_2G_WL\t\t\t= 0x7,\n\tBTC_ANT_2G_BT\t\t\t= 0x8,\n\tBTC_ANT_MCC\t\t\t= 0x9,\n\tBTC_ANT_2G_WLBT\t\t\t= 0xa,\n\tBTC_ANT_2G_FREERUN\t\t= 0xb,\n\tBTC_ANT_MAX\n};\n\n/*ADD SCOREBOARD TO FIX BT LPS 32K ISSUE WHILE WL BUSY*/\nenum btc_wl2bt_scoreboard {\n\tBTC_SCBD_ACTIVE\t\t= BIT(0),\n\tBTC_SCBD_ON\t\t\t= BIT(1),\n\tBTC_SCBD_SCAN\t\t= BIT(2),\n\tBTC_SCBD_UNDERTEST\t= BIT(3),\n\tBTC_SCBD_RXGAIN\t\t= BIT(4),\n\tBTC_SCBD_WLBUSY\t\t= BIT(7),\n\tBTC_SCBD_EXTFEM\t\t= BIT(8),\n\tBTC_SCBD_TDMA\t\t= BIT(9),\n\tBTC_SCBD_FIX2M\t\t= BIT(10),\n\tBTC_SCBD_ALL\t\t= 0xffff\n};\n\nenum btc_bt2wl_scoreboard {\n\tBTC_SCBD_BT_ONOFF\t= BIT(1),\n\tBTC_SCBD_BT_LPS\t\t= BIT(7)\n};\n\nenum btc_runreason {\n\tBTC_RSN_2GSCANSTART\t= 0x0,\n\tBTC_RSN_5GSCANSTART\t= 0x1,\n\tBTC_RSN_SCANFINISH\t= 0x2,\n\tBTC_RSN_2GSWITCHBAND\t= 0x3,\n\tBTC_RSN_5GSWITCHBAND\t= 0x4,\n\tBTC_RSN_2GCONSTART\t= 0x5,\n\tBTC_RSN_5GCONSTART\t= 0x6,\n\tBTC_RSN_2GCONFINISH\t= 0x7,\n\tBTC_RSN_5GCONFINISH\t= 0x8,\n\tBTC_RSN_2GMEDIA\t\t= 0x9,\n\tBTC_RSN_5GMEDIA\t\t= 0xa,\n\tBTC_RSN_MEDIADISCON\t= 0xb,\n\tBTC_RSN_2GSPECIALPKT\t= 0xc,\n\tBTC_RSN_5GSPECIALPKT\t= 0xd,\n\tBTC_RSN_BTINFO\t\t= 0xe,\n\tBTC_RSN_PERIODICAL\t= 0xf,\n\tBTC_RSN_PNP\t\t= 0x10,\n\tBTC_RSN_LPS\t\t= 0x11,\n\tBTC_RSN_TIMERUP\t\t= 0x12,\n\tBTC_RSN_WLSTATUS\t= 0x13,\n\tBTC_RSN_MAX\n};\n\nstatic const char *const run_reason_string[] = {\n\t\"2G_SCAN_START\",\n\t\"5G_SCAN_START\",\n\t\"SCAN_FINISH\",\n\t\"2G_SWITCH_BAND\",\n\t\"5G_SWITCH_BAND\",\n\t\"2G_CONNECT_START\",\n\t\"5G_CONNECT_START\",\n\t\"2G_CONNECT_FINISH\",\n\t\"5G_CONNECT_FINISH\",\n\t\"2G_MEDIA_STATUS\",\n\t\"5G_MEDIA_STATUS\",\n\t\"MEDIA_DISCONNECT\",\n\t\"2G_SPECIALPKT\",\n\t\"5G_SPECIALPKT\",\n\t\"BTINFO\",\n\t\"PERIODICAL\",\n\t\"PNPNotify\",\n\t\"LPSNotify\",\n\t\"TimerUp\",\n\t\"WL_STATUS_CHANGE\",\n};\n\nenum btc_wl_link_mode {\n\tBTC_WLINK_2G1PORT\t= 0x0,\n\tBTC_WLINK_2GMPORT\t= 0x1,\n\tBTC_WLINK_25GMPORT\t= 0x2,\n\tBTC_WLINK_5G\t\t= 0x3,\n\tBTC_WLINK_2GGO\t\t= 0x4,\n\tBTC_WLINK_2GGC\t\t= 0x5,\n\tBTC_WLINK_BTMR\t\t= 0x6,\n\tBTC_WLINK_MAX\n};\n\nstatic const char *const coex_mode_string[] = {\n\t\"2G-SP\",\n\t\"2G-MP\",\n\t\"25G-MP\",\n\t\"5G\",\n\t\"2G-P2P-GO\",\n\t\"2G-P2P-GC\",\n\t\"BT-MR\"\n};\n\nenum btc_bt_state_cnt {\n\tBTC_CNT_BT_RETRY\t= 0x0,\n\tBTC_CNT_BT_REINIT\t= 0x1,\n\tBTC_CNT_BT_POPEVENT\t= 0x2,\n\tBTC_CNT_BT_SETUPLINK\t= 0x3,\n\tBTC_CNT_BT_IGNWLANACT\t= 0x4,\n\tBTC_CNT_BT_INQ\t\t= 0x5,\n\tBTC_CNT_BT_PAGE\t\t= 0x6,\n\tBTC_CNT_BT_ROLESWITCH\t= 0x7,\n\tBTC_CNT_BT_AFHUPDATE\t= 0x8,\n\tBTC_CNT_BT_DISABLE\t= 0x9,\n\tBTC_CNT_BT_INFOUPDATE\t= 0xa,\n\tBTC_CNT_BT_IQK\t\t= 0xb,\n\tBTC_CNT_BT_IQKFAIL\t= 0xc,\n\tBTC_CNT_BT_MAX\n};\n\nenum btc_wl_state_cnt {\n\tBTC_CNT_WL_SCANAP\t\t= 0x0,\n\tBTC_CNT_WL_ARP\t\t\t= 0x1,\n\tBTC_CNT_WL_GNTERR\t\t= 0x2,\n\tBTC_CNT_WL_PSFAIL\t\t= 0x3,\n\tBTC_CNT_WL_COEXRUN\t\t= 0x4,\n\tBTC_CNT_WL_COEXINFO1\t\t= 0x5,\n\tBTC_CNT_WL_COEXINFO2\t\t= 0x6,\n\tBTC_CNT_WL_AUTOSLOT_HANG\t= 0x7,\n\tBTC_CNT_WL_NOISY0\t\t= 0x8,\n\tBTC_CNT_WL_NOISY1\t\t= 0x9,\n\tBTC_CNT_WL_NOISY2\t\t= 0xa,\n\tBTC_CNT_WL_ACTIVEPORT\t\t= 0xb,\n\tBTC_CNT_WL_5MS_NOEXTEND\t\t= 0xc,\n\tBTC_CNT_WL_FW_NOTIFY\t\t= 0xd,\n\tBTC_CNT_WL_MAX\n};\n\nenum btc_wl_crc_cnt {\n\tBTC_WLCRC_11BOK\t\t= 0x0,\n\tBTC_WLCRC_11GOK\t\t= 0x1,\n\tBTC_WLCRC_11NOK\t\t= 0x2,\n\tBTC_WLCRC_11VHTOK\t= 0x3,\n\tBTC_WLCRC_11BERR\t= 0x4,\n\tBTC_WLCRC_11GERR\t= 0x5,\n\tBTC_WLCRC_11NERR\t= 0x6,\n\tBTC_WLCRC_11VHTERR\t= 0x7,\n\tBTC_WLCRC_MAX\n};\n\nenum btc_timer_cnt {\n\tBTC_TIMER_WL_STAYBUSY\t= 0x0,\n\tBTC_TIMER_WL_COEXFREEZE\t= 0x1,\n\tBTC_TIMER_WL_SPECPKT\t= 0x2,\n\tBTC_TIMER_WL_CONNPKT\t= 0x3,\n\tBTC_TIMER_WL_PNPWAKEUP\t= 0x4,\n\tBTC_TIMER_WL_CCKLOCK\t= 0x5,\n\tBTC_TIMER_WL_FWDBG\t= 0x6,\n\tBTC_TIMER_BT_RELINK\t= 0x7,\n\tBTC_TIMER_BT_REENABLE\t= 0x8,\n\tBTC_TIMER_MAX\n};\n\nenum btc_wl_status_change {\n\tBTC_WLSTATUS_CHANGE_TOIDLE\t= 0x0,\n\tBTC_WLSTATUS_CHANGE_TOBUSY\t= 0x1,\n\tBTC_WLSTATUS_CHANGE_RSSI\t= 0x2,\n\tBTC_WLSTATUS_CHANGE_LINKINFO\t= 0x3,\n\tBTC_WLSTATUS_CHANGE_DIR\t= 0x4,\n\tBTC_WLSTATUS_CHANGE_NOISY\t= 0x5,\n\tBTC_WLSTATUS_CHANGE_MAX\n};\n\nenum btc_commom_chip_setup {\n\tBTC_CSETUP_INIT_HW\t\t= 0x0,\n\tBTC_CSETUP_ANT_SWITCH\t= 0x1,\n\tBTC_CSETUP_GNT_FIX\t\t= 0x2,\n\tBTC_CSETUP_GNT_DEBUG\t= 0x3,\n\tBTC_CSETUP_RFE_TYPE\t\t= 0x4,\n\tBTC_CSETUP_COEXINFO_HW\t= 0x5,\n\tBTC_CSETUP_WL_TX_POWER\t= 0x6,\n\tBTC_CSETUP_WL_RX_GAIN\t= 0x7,\n\tBTC_CSETUP_WLAN_ACT_IPS = 0x8,\n\tBTC_CSETUP_MAX\n};\n\nenum btc_indirect_reg_type {\n\tBTC_INDIRECT_1700\t= 0x0,\n\tBTC_INDIRECT_7C0\t= 0x1,\n\tBTC_INDIRECT_MAX\n};\n\nenum btc_pstdma_type {\n\tBTC_PSTDMA_FORCE_LPSOFF\t= 0x0,\n\tBTC_PSTDMA_FORCE_LPSON\t= 0x1,\n\tBTC_PSTDMA_MAX\n};\n\nenum btc_btrssi_type {\n\tBTC_BTRSSI_RATIO\t= 0x0,\n\tBTC_BTRSSI_DBM\t\t= 0x1,\n\tBTC_BTRSSI_MAX\n};\n\nenum btc_wl_priority_mask {\n\tBTC_WLPRI_RX_RSP\t= 2,\n\tBTC_WLPRI_TX_RSP\t= 3,\n\tBTC_WLPRI_TX_BEACON\t= 4,\n\tBTC_WLPRI_TX_OFDM\t= 11,\n\tBTC_WLPRI_TX_CCK\t= 12,\n\tBTC_WLPRI_TX_BEACONQ\t= 27,\n\tBTC_WLPRI_RX_CCK\t= 28,\n\tBTC_WLPRI_RX_OFDM\t= 29,\n\tBTC_WLPRI_MAX\n};\n\nstruct btc_board_info {\n\t/* The following is some board information */\n\tu8\t\t\t\tbt_chip_type;\n\tu8\t\t\t\tpg_ant_num;\t/* pg ant number */\n\tu8\t\t\t\tbtdm_ant_num;\t/* ant number for btdm */\n\tu8\t\t\t\tbtdm_ant_num_by_ant_det;\t/* ant number for btdm after antenna detection */\n\tu8\t\t\t\tbtdm_ant_pos;\t\t/* Bryant Add to indicate Antenna Position for (pg_ant_num = 2) && (btdm_ant_num =1)  (DPDT+1Ant case) */\n\tu8\t\t\t\tsingle_ant_path;\t/* current used for 8723b only, 1=>s0,  0=>s1 */\n\tboolean\t\t\ttfbga_package;    /* for Antenna detect threshold */\n\tboolean\t\t\tbtdm_ant_det_finish;\n\tboolean\t\t\tbtdm_ant_det_already_init_phydm;\n\tu8\t\t\t\tant_type;\n\tu8\t\t\t\trfe_type;\n\tu8\t\t\t\tant_div_cfg;\n\tboolean\t\t\tbtdm_ant_det_complete_fail;\n\tu8\t\t\t\tant_det_result;\n\tboolean\t\t\tant_det_result_five_complete;\n\tu32\t\t\t\tantdetval;\n\tu8\t\t\t\tcustomerID;\n\tu8\t\t\t\tcustomer_id;\n\tu8\t\t\t\tant_distance;\t/* WL-BT antenna space for non-shared antenna  */\n};\n\nstruct btc_coex_dm {\n\tboolean cur_ignore_wlan_act;\n\tboolean cur_ps_tdma_on;\n\tboolean cur_low_penalty_ra;\n\tboolean cur_wl_rx_low_gain_en;\n\n\tu8\tbt_rssi_state[4];\n\tu8\twl_rssi_state[4];\n\tu8\tcur_ps_tdma;\n\tu8\tps_tdma_para[5];\n\tu8\tfw_tdma_para[5];\n\tu8\tcur_lps;\n\tu8\tcur_rpwm;\n\tu8\tcur_bt_pwr_lvl;\n\tu8\tcur_bt_lna_lvl;\n\tu8\tcur_wl_pwr_lvl;\n\tu8\tcur_algorithm;\n\tu8\tbt_status;\n\tu8\twl_chnl_info[3];\n\tu8\tcur_toggle_para[6];\n\tu8\tcur_val0x6cc;\n\tu32\tcur_val0x6c0;\n\tu32\tcur_val0x6c4;\n\tu32\tcur_val0x6c8;\n\tu32\tcur_ant_pos_type;\n\tu32\tcur_switch_status;\n\tu32\tsetting_tdma;\n};\n\nstruct btc_coex_sta {\n\tboolean coex_freeze;\n\tboolean coex_freerun;\n\tboolean tdma_bt_autoslot;\n\tboolean rf4ce_en;\n\tboolean is_no_wl_5ms_extend;\n\n\tboolean bt_disabled;\n\tboolean bt_disabled_pre;\n\tboolean bt_link_exist;\n\tboolean bt_whck_test;\n\tboolean bt_inq_page;\n\tboolean bt_inq;\n\tboolean bt_page;\n\tboolean bt_ble_voice;\n\tboolean bt_ble_exist;\n\tboolean bt_hfp_exist;\n\tboolean bt_a2dp_exist;\n\tboolean bt_hid_exist;\n\tboolean bt_pan_exist; // PAN or OPP\n\tboolean bt_opp_exist; //OPP only\n\tboolean bt_msft_mr_exist;\n\tboolean bt_acl_busy;\n\tboolean bt_fix_2M;\n\tboolean bt_setup_link;\n\tboolean bt_multi_link;\n\tboolean bt_a2dp_sink;\n\tboolean bt_reenable;\n\tboolean bt_ble_scan_en;\n\tboolean bt_slave;\n\tboolean bt_a2dp_active;\n\tboolean bt_slave_latency;\n\tboolean bt_init_scan;\n\tboolean bt_418_hid_exist;\n\tboolean bt_mesh;\n\n\tboolean wl_under_lps;\n\tboolean wl_under_ips;\n\tboolean wl_under_4way;\n\tboolean\twl_hi_pri_task1;\n\tboolean\twl_hi_pri_task2;\n\tboolean wl_cck_lock;\n\tboolean wl_cck_lock_pre;\n\tboolean wl_cck_lock_ever;\n\tboolean wl_force_lps_ctrl;\n\tboolean wl_busy_pre;\n\tboolean wl_gl_busy;\n\tboolean wl_gl_busy_pre;\n\tboolean wl_linkscan_proc;\n\tboolean wl_mimo_ps;\n\tboolean wl_ps_state_fail;\n\tboolean wl_cck_dead_lock_ap;\n\tboolean wl_tx_limit_en;\n\tboolean wl_ampdu_limit_en;\n\tboolean wl_rxagg_limit_en;\n\tboolean wl_connecting;\n\tboolean wl_pnp_wakeup;\n\tboolean wl_slot_toggle;\n\tboolean wl_slot_toggle_change; /* if toggle to no-toggle */\n\n\tu8\tcoex_table_type;\n\tu8 \tcoex_run_reason;\n\tu8\ttdma_byte4_modify_pre;\n\tu8\tkt_ver;\n\tu8\tgnt_workaround_state;\n\tu8\ttdma_timer_base;\n\tu8\tbt_rssi;\n\tu8\tbt_profile_num;\n\tu8\tbt_profile_num_pre;\n\tu8\tbt_info_c2h[BTC_BTINFO_SRC_MAX][BTC_BTINFO_LENGTH_MAX];\n\tu8\tbt_info_lb2;\n\tu8\tbt_info_lb3;\n\tu8\tbt_info_hb0;\n\tu8\tbt_info_hb1;\n\tu8\tbt_info_hb2;\n\tu8\tbt_info_hb3;\n\tu8\tbt_ble_scan_type;\n\tu8\tbt_afh_map[10];\n\tu8\tbt_a2dp_vendor_id;\n\tu8\tbt_hid_pair_num;\n\tu8\tbt_hid_slot;\n\tu8\tbt_a2dp_bitpool;\n\tu8\tbt_iqk_state;\n\tu8\tbt_sut_pwr_lvl[4];\n\tu8\tbt_golden_rx_shift[4];\n\tu8\tbt_ext_autoslot_thres;\n\n\tu8\twl_pnp_state_pre;\n\tu8\twl_noisy_level;\n\tu8\twl_fw_dbg_info[10];\n\tu8\twl_fw_dbg_info_pre[10];\n\tu8\twl_rx_rate;\n\tu8\twl_tx_rate;\n\tu8\twl_rts_rx_rate;\n\tu8\twl_center_ch;\n\tu8\twl_tx_macid;\n\tu8\twl_tx_retry_ratio;\n\tu8\twl_coex_mode;\n\tu8\twl_iot_peer;\n\tu8\twl_ra_thres;\n\tu8\twl_ampdulen_backup;\n\tu8\twl_rxagg_size;\n\tu8\twl_toggle_para[6];\n\n\tu16\tscore_board_BW;\n\tu16\tscore_board_WB;\n\tu16\tbt_reg_vendor_ac;\n\tu16\tbt_reg_vendor_ae;\n\tu16\tbt_reg_modem_a;\n\tu16\tbt_reg_rf_2;\n\tu16\twl_txlimit_backup;\n\n\tu32\thi_pri_tx;\n\tu32\thi_pri_rx;\n\tu32\tlo_pri_tx;\n\tu32\tlo_pri_rx;\n\tu32\tbt_supported_feature;\n\tu32\tbt_supported_version;\n\tu32\tbt_ble_scan_para[3];\n\tu32\tbt_a2dp_device_name;\n\tu32\twl_arfb1_backup;\n\tu32\twl_arfb2_backup;\n\tu32\twl_traffic_dir;\n\tu32\twl_bw;\n\tu32\tcnt_bt_info_c2h[BTC_BTINFO_SRC_MAX];\n\tu32\tcnt_bt[BTC_CNT_BT_MAX];\n\tu32\tcnt_wl[BTC_CNT_WL_MAX];\n\tu32\tcnt_timer[BTC_TIMER_MAX];\n};\n\nstruct btc_rfe_type {\n\tboolean ant_switch_exist;\n\tboolean ant_switch_diversity; /* If diversity on */\n\tboolean ant_switch_with_bt; /* If WL_2G/BT use ext-switch at shared-ant */\n\tu8\trfe_module_type;\n\tu8\tant_switch_type;\n\tu8\tant_switch_polarity;\n\t\n\tboolean band_switch_exist;\n\tu8\tband_switch_type; /* 0:DPDT, 1:SPDT */\n\tu8\tband_switch_polarity;\n\n\t/*  If TRUE:  WLG at BTG, If FALSE: WLG at WLAG */\n\tboolean wlg_at_btg;\n};\n\n\nstruct btc_wifi_link_info_ext {\n\tboolean is_all_under_5g;\n\tboolean is_mcc_25g;\n\tboolean is_p2p_connected;\n\tboolean is_ap_mode;\n\tboolean is_scan;\n\tboolean is_link;\n\tboolean is_roam;\n\tboolean is_4way;\n\tboolean is_32k;\n\tboolean is_connected;\n\tu8\tnum_of_active_port;\n\tu32\tport_connect_status;\n\tu32\ttraffic_dir;\n\tu32\twifi_bw;\n};\n\nstruct btc_coex_table_para {\n\tu32 bt;\t//0x6c0\n\tu32 wl;\t//0x6c4\n};\n\nstruct btc_tdma_para {\n\tu8 para[5];\n};\n\nstruct btc_reg_byte_modify {\n\tu32 addr;\n\tu8 bitmask;\n\tu8 val;\n};\n\nstruct btc_5g_afh_map {\n\tu32 wl_5g_ch;\n\tu8 bt_skip_ch;\n\tu8 bt_skip_span;\n};\n\nstruct btc_rf_para {\n\tu8 wl_pwr_dec_lvl;\n\tu8 bt_pwr_dec_lvl;\n\tboolean wl_low_gain_en;\n\tu8 bt_lna_lvl;\n};\n\ntypedef enum _BTC_DBG_OPCODE {\n\tBTC_DBG_SET_COEX_NORMAL\t\t\t\t= 0x0,\n\tBTC_DBG_SET_COEX_WIFI_ONLY\t\t\t\t= 0x1,\n\tBTC_DBG_SET_COEX_BT_ONLY\t\t\t\t= 0x2,\n\tBTC_DBG_SET_COEX_DEC_BT_PWR\t\t\t\t= 0x3,\n\tBTC_DBG_SET_COEX_BT_AFH_MAP\t\t\t\t= 0x4,\n\tBTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT\t\t= 0x5,\n\tBTC_DBG_SET_COEX_MANUAL_CTRL\t\t\t\t= 0x6,\n\tBTC_DBG_MAX\n} BTC_DBG_OPCODE, *PBTC_DBG_OPCODE;\n\ntypedef enum _BTC_RSSI_STATE {\n\tBTC_RSSI_STATE_HIGH\t\t\t\t\t\t= 0x0,\n\tBTC_RSSI_STATE_MEDIUM\t\t\t\t\t= 0x1,\n\tBTC_RSSI_STATE_LOW\t\t\t\t\t\t= 0x2,\n\tBTC_RSSI_STATE_STAY_HIGH\t\t\t\t\t= 0x3,\n\tBTC_RSSI_STATE_STAY_MEDIUM\t\t\t\t= 0x4,\n\tBTC_RSSI_STATE_STAY_LOW\t\t\t\t\t= 0x5,\n\tBTC_RSSI_MAX\n} BTC_RSSI_STATE, *PBTC_RSSI_STATE;\n#define\tBTC_RSSI_HIGH(_rssi_)\t((_rssi_ == BTC_RSSI_STATE_HIGH || _rssi_ == BTC_RSSI_STATE_STAY_HIGH) ? TRUE:FALSE)\n#define\tBTC_RSSI_MEDIUM(_rssi_)\t((_rssi_ == BTC_RSSI_STATE_MEDIUM || _rssi_ == BTC_RSSI_STATE_STAY_MEDIUM) ? TRUE:FALSE)\n#define\tBTC_RSSI_LOW(_rssi_)\t((_rssi_ == BTC_RSSI_STATE_LOW || _rssi_ == BTC_RSSI_STATE_STAY_LOW) ? TRUE:FALSE)\n\ntypedef enum _BTC_WIFI_ROLE {\n\tBTC_ROLE_STATION\t\t\t\t\t\t= 0x0,\n\tBTC_ROLE_AP\t\t\t\t\t\t\t\t= 0x1,\n\tBTC_ROLE_IBSS\t\t\t\t\t\t\t= 0x2,\n\tBTC_ROLE_HS_MODE\t\t\t\t\t\t= 0x3,\n\tBTC_ROLE_MAX\n} BTC_WIFI_ROLE, *PBTC_WIFI_ROLE;\n\ntypedef enum _BTC_WIRELESS_FREQ {\n\tBTC_FREQ_2_4G\t\t\t\t\t= 0x0,\n\tBTC_FREQ_5G\t\t\t\t\t\t= 0x1,\n\tBTC_FREQ_25G\t\t\t\t\t= 0x2,\n\tBTC_FREQ_MAX\n} BTC_WIRELESS_FREQ, *PBTC_WIRELESS_FREQ;\n\ntypedef enum _BTC_WIFI_BW_MODE {\n\tBTC_WIFI_BW_LEGACY\t\t\t\t\t= 0x0,\n\tBTC_WIFI_BW_HT20\t\t\t\t\t= 0x1,\n\tBTC_WIFI_BW_HT40\t\t\t\t\t= 0x2,\n\tBTC_WIFI_BW_HT80\t\t\t\t\t= 0x3,\n\tBTC_WIFI_BW_HT160\t\t\t\t\t= 0x4,\n\tBTC_WIFI_BW_MAX\n} BTC_WIFI_BW_MODE, *PBTC_WIFI_BW_MODE;\n\ntypedef enum _BTC_WIFI_TRAFFIC_DIR {\n\tBTC_WIFI_TRAFFIC_TX\t\t\t\t\t= 0x0,\n\tBTC_WIFI_TRAFFIC_RX\t\t\t\t\t= 0x1,\n\tBTC_WIFI_TRAFFIC_MAX\n} BTC_WIFI_TRAFFIC_DIR, *PBTC_WIFI_TRAFFIC_DIR;\n\ntypedef enum _BTC_WIFI_PNP {\n\tBTC_WIFI_PNP_WAKE_UP\t\t\t\t\t= 0x0,\n\tBTC_WIFI_PNP_SLEEP\t\t\t\t\t\t= 0x1,\n\tBTC_WIFI_PNP_SLEEP_KEEP_ANT\t\t\t\t= 0x2,\n\tBTC_WIFI_PNP_WOWLAN\t\t\t\t\t= 0x3,\n\tBTC_WIFI_PNP_MAX\n} BTC_WIFI_PNP, *PBTC_WIFI_PNP;\n\ntypedef enum _BTC_IOT_PEER {\n\tBTC_IOT_PEER_UNKNOWN = 0,\n\tBTC_IOT_PEER_REALTEK = 1,\n\tBTC_IOT_PEER_REALTEK_92SE = 2,\n\tBTC_IOT_PEER_BROADCOM = 3,\n\tBTC_IOT_PEER_RALINK = 4,\n\tBTC_IOT_PEER_ATHEROS = 5,\n\tBTC_IOT_PEER_CISCO = 6,\n\tBTC_IOT_PEER_MERU = 7,\n\tBTC_IOT_PEER_MARVELL = 8,\n\tBTC_IOT_PEER_REALTEK_SOFTAP = 9, /* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */\n\tBTC_IOT_PEER_SELF_SOFTAP = 10, /* Self is SoftAP */\n\tBTC_IOT_PEER_AIRGO = 11,\n\tBTC_IOT_PEER_INTEL\t\t\t\t= 12,\n\tBTC_IOT_PEER_RTK_APCLIENT\t\t= 13,\n\tBTC_IOT_PEER_REALTEK_81XX\t\t= 14,\n\tBTC_IOT_PEER_REALTEK_WOW\t\t= 15,\n\tBTC_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 16,\n\tBTC_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 17,\n\tBTC_IOT_PEER_MAX,\n} BTC_IOT_PEER, *PBTC_IOT_PEER;\n\n/* for 8723b-d cut large current issue */\ntypedef enum _BTC_WIFI_COEX_STATE {\n\tBTC_WIFI_STAT_INIT,\n\tBTC_WIFI_STAT_IQK,\n\tBTC_WIFI_STAT_NORMAL_OFF,\n\tBTC_WIFI_STAT_MP_OFF,\n\tBTC_WIFI_STAT_NORMAL,\n\tBTC_WIFI_STAT_ANT_DIV,\n\tBTC_WIFI_STAT_MAX\n} BTC_WIFI_COEX_STATE, *PBTC_WIFI_COEX_STATE;\n\ntypedef enum _BTC_ANT_TYPE {\n\tBTC_ANT_TYPE_0,\n\tBTC_ANT_TYPE_1,\n\tBTC_ANT_TYPE_2,\n\tBTC_ANT_TYPE_3,\n\tBTC_ANT_TYPE_4,\n\tBTC_ANT_TYPE_MAX\n} BTC_ANT_TYPE, *PBTC_ANT_TYPE;\n\ntypedef enum _BTC_VENDOR {\n\tBTC_VENDOR_LENOVO,\n\tBTC_VENDOR_ASUS,\n\tBTC_VENDOR_OTHER\n} BTC_VENDOR, *PBTC_VENDOR;\n\n\n/* defined for BFP_BTC_GET */\ntypedef enum _BTC_GET_TYPE {\n\t/* type BOOLEAN */\n\tBTC_GET_BL_HS_OPERATION,\n\tBTC_GET_BL_HS_CONNECTING,\n\tBTC_GET_BL_WIFI_FW_READY,\n\tBTC_GET_BL_WIFI_CONNECTED,\n\tBTC_GET_BL_WIFI_DUAL_BAND_CONNECTED,\n\tBTC_GET_BL_WIFI_LINK_INFO,\n\tBTC_GET_BL_WIFI_BUSY,\n\tBTC_GET_BL_WIFI_SCAN,\n\tBTC_GET_BL_WIFI_LINK,\n\tBTC_GET_BL_WIFI_ROAM,\n\tBTC_GET_BL_WIFI_4_WAY_PROGRESS,\n\tBTC_GET_BL_WIFI_UNDER_5G,\n\tBTC_GET_BL_WIFI_AP_MODE_ENABLE,\n\tBTC_GET_BL_WIFI_ENABLE_ENCRYPTION,\n\tBTC_GET_BL_WIFI_UNDER_B_MODE,\n\tBTC_GET_BL_EXT_SWITCH,\n\tBTC_GET_BL_WIFI_IS_IN_MP_MODE,\n\tBTC_GET_BL_IS_ASUS_8723B,\n\tBTC_GET_BL_RF4CE_CONNECTED,\n\tBTC_GET_BL_WIFI_LW_PWR_STATE,\n\n\t/* type s4Byte */\n\tBTC_GET_S4_WIFI_RSSI,\n\tBTC_GET_S4_HS_RSSI,\n\n\t/* type u4Byte */\n\tBTC_GET_U4_WIFI_BW,\n\tBTC_GET_U4_WIFI_TRAFFIC_DIRECTION,\n\tBTC_GET_U4_WIFI_TRAFFIC_DIR,\n\tBTC_GET_U4_WIFI_FW_VER,\n\tBTC_GET_U4_WIFI_PHY_VER,\n\tBTC_GET_U4_WIFI_LINK_STATUS,\n\tBTC_GET_U4_BT_PATCH_VER,\n\tBTC_GET_U4_VENDOR,\n\tBTC_GET_U4_SUPPORTED_VERSION,\n\tBTC_GET_U4_SUPPORTED_FEATURE,\n\tBTC_GET_U4_BT_DEVICE_INFO,\n\tBTC_GET_U4_BT_FORBIDDEN_SLOT_VAL,\n\tBTC_GET_U4_WIFI_IQK_TOTAL,\n\tBTC_GET_U4_WIFI_IQK_OK,\n\tBTC_GET_U4_WIFI_IQK_FAIL,\n\n\t/* type u1Byte */\n\tBTC_GET_U1_WIFI_DOT11_CHNL,\n\tBTC_GET_U1_WIFI_CENTRAL_CHNL,\n\tBTC_GET_U1_WIFI_HS_CHNL,\n\tBTC_GET_U1_WIFI_P2P_CHNL,\n\tBTC_GET_U1_MAC_PHY_MODE,\n\tBTC_GET_U1_AP_NUM,\n\tBTC_GET_U1_ANT_TYPE,\n\tBTC_GET_U1_IOT_PEER,\n\n\t/* type u2Byte */\n\tBTC_GET_U2_BEACON_PERIOD,\n\n\t/*===== for 1Ant ======*/\n\tBTC_GET_U1_LPS_MODE,\n\n\tBTC_GET_MAX\n} BTC_GET_TYPE, *PBTC_GET_TYPE;\n\n/* defined for BFP_BTC_SET */\ntypedef enum _BTC_SET_TYPE {\n\t/* type BOOLEAN */\n\tBTC_SET_BL_BT_DISABLE,\n\tBTC_SET_BL_BT_ENABLE_DISABLE_CHANGE,\n\tBTC_SET_BL_BT_TRAFFIC_BUSY,\n\tBTC_SET_BL_BT_LIMITED_DIG,\n\tBTC_SET_BL_FORCE_TO_ROAM,\n\tBTC_SET_BL_TO_REJ_AP_AGG_PKT,\n\tBTC_SET_BL_BT_CTRL_AGG_SIZE,\n\tBTC_SET_BL_INC_SCAN_DEV_NUM,\n\tBTC_SET_BL_BT_TX_RX_MASK,\n\tBTC_SET_BL_MIRACAST_PLUS_BT,\n\tBTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL,\n\tBTC_SET_BL_BT_GOLDEN_RX_RANGE,\n\n\t/* type u1Byte */\n\tBTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,\n\tBTC_SET_U1_AGG_BUF_SIZE,\n\n\t/* type trigger some action */\n\tBTC_SET_ACT_GET_BT_RSSI,\n\tBTC_SET_ACT_AGGREGATE_CTRL,\n\tBTC_SET_ACT_ANTPOSREGRISTRY_CTRL,\n\n\t// for mimo ps mode setting\n\tBTC_SET_MIMO_PS_MODE,\n\t/*===== for 1Ant ======*/\n\t/* type BOOLEAN */\n\n\t/* type u1Byte */\n\tBTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE,\n\tBTC_SET_U1_LPS_VAL,\n\tBTC_SET_U1_RPWM_VAL,\n\t/* type trigger some action */\n\tBTC_SET_ACT_LEAVE_LPS,\n\tBTC_SET_ACT_ENTER_LPS,\n\tBTC_SET_ACT_NORMAL_LPS,\n\tBTC_SET_ACT_PRE_NORMAL_LPS,\n\tBTC_SET_ACT_POST_NORMAL_LPS,\n\tBTC_SET_ACT_DISABLE_LOW_POWER,\n\tBTC_SET_ACT_UPDATE_RAMASK,\n\tBTC_SET_ACT_SEND_MIMO_PS,\n\t/* BT Coex related */\n\tBTC_SET_ACT_CTRL_BT_INFO,\n\tBTC_SET_ACT_CTRL_BT_COEX,\n\tBTC_SET_ACT_CTRL_8723B_ANT,\n\tBTC_SET_RESET_COEX_VAR,\n\t/*=================*/\n\tBTC_SET_MAX\n} BTC_SET_TYPE, *PBTC_SET_TYPE;\n\ntypedef enum _BTC_DBG_DISP_TYPE {\n\tBTC_DBG_DISP_COEX_STATISTICS\t\t\t\t= 0x0,\n\tBTC_DBG_DISP_BT_LINK_INFO\t\t\t\t= 0x1,\n\tBTC_DBG_DISP_WIFI_STATUS\t\t\t\t= 0x2,\n\tBTC_DBG_DISP_MAX\n} BTC_DBG_DISP_TYPE, *PBTC_DBG_DISP_TYPE;\n\ntypedef enum _BTC_NOTIFY_TYPE_IPS {\n\tBTC_IPS_LEAVE\t\t\t\t\t\t\t= 0x0,\n\tBTC_IPS_ENTER\t\t\t\t\t\t\t= 0x1,\n\tBTC_IPS_MAX\n} BTC_NOTIFY_TYPE_IPS, *PBTC_NOTIFY_TYPE_IPS;\ntypedef enum _BTC_NOTIFY_TYPE_LPS {\n\tBTC_LPS_DISABLE\t\t\t\t\t\t\t= 0x0,\n\tBTC_LPS_ENABLE\t\t\t\t\t\t\t= 0x1,\n\tBTC_LPS_MAX\n} BTC_NOTIFY_TYPE_LPS, *PBTC_NOTIFY_TYPE_LPS;\ntypedef enum _BTC_NOTIFY_TYPE_SCAN {\n\tBTC_SCAN_FINISH\t\t\t\t\t\t\t= 0x0,\n\tBTC_SCAN_START\t\t\t\t\t\t\t= 0x1,\n\tBTC_SCAN_START_2G\t\t\t\t\t\t= 0x2,\n\tBTC_SCAN_START_5G\t\t\t\t\t\t= 0x3,\n\tBTC_SCAN_MAX\n} BTC_NOTIFY_TYPE_SCAN, *PBTC_NOTIFY_TYPE_SCAN;\ntypedef enum _BTC_NOTIFY_TYPE_SWITCHBAND {\n\tBTC_NOT_SWITCH\t\t\t\t\t\t\t= 0x0,\n\tBTC_SWITCH_TO_24G\t\t\t\t\t\t= 0x1,\n\tBTC_SWITCH_TO_5G\t\t\t\t\t\t= 0x2,\n\tBTC_SWITCH_TO_24G_NOFORSCAN\t\t\t\t= 0x3,\n\tBTC_SWITCH_MAX\n} BTC_NOTIFY_TYPE_SWITCHBAND, *PBTC_NOTIFY_TYPE_SWITCHBAND;\ntypedef enum _BTC_NOTIFY_TYPE_ASSOCIATE {\n\tBTC_ASSOCIATE_FINISH\t\t\t\t\t\t= 0x0,\n\tBTC_ASSOCIATE_START\t\t\t\t\t\t= 0x1,\n\tBTC_ASSOCIATE_5G_FINISH\t\t\t\t\t\t= 0x2,\n\tBTC_ASSOCIATE_5G_START\t\t\t\t\t\t= 0x3,\n\tBTC_ASSOCIATE_MAX\n} BTC_NOTIFY_TYPE_ASSOCIATE, *PBTC_NOTIFY_TYPE_ASSOCIATE;\ntypedef enum _BTC_NOTIFY_TYPE_MEDIA_STATUS {\n\tBTC_MEDIA_DISCONNECT\t\t\t\t\t= 0x0,\n\tBTC_MEDIA_CONNECT\t\t\t\t\t\t= 0x1,\n\tBTC_MEDIA_CONNECT_5G\t\t\t\t\t= 0x02,\n\tBTC_MEDIA_MAX\n} BTC_NOTIFY_TYPE_MEDIA_STATUS, *PBTC_NOTIFY_TYPE_MEDIA_STATUS;\ntypedef enum _BTC_NOTIFY_TYPE_SPECIFIC_PACKET {\n\tBTC_PACKET_UNKNOWN\t\t\t\t\t= 0x0,\n\tBTC_PACKET_DHCP\t\t\t\t\t\t\t= 0x1,\n\tBTC_PACKET_ARP\t\t\t\t\t\t\t= 0x2,\n\tBTC_PACKET_EAPOL\t\t\t\t\t\t= 0x3,\n\tBTC_PACKET_MAX\n} BTC_NOTIFY_TYPE_SPECIFIC_PACKET, *PBTC_NOTIFY_TYPE_SPECIFIC_PACKET;\ntypedef enum _BTC_NOTIFY_TYPE_STACK_OPERATION {\n\tBTC_STACK_OP_NONE\t\t\t\t\t= 0x0,\n\tBTC_STACK_OP_INQ_PAGE_PAIR_START\t\t= 0x1,\n\tBTC_STACK_OP_INQ_PAGE_PAIR_FINISH\t= 0x2,\n\tBTC_STACK_OP_MAX\n} BTC_NOTIFY_TYPE_STACK_OPERATION, *PBTC_NOTIFY_TYPE_STACK_OPERATION;\n\n/* Bryant Add */\ntypedef enum _BTC_ANTENNA_POS {\n\tBTC_ANTENNA_AT_MAIN_PORT\t\t\t\t= 0x1,\n\tBTC_ANTENNA_AT_AUX_PORT\t\t\t\t= 0x2,\n} BTC_ANTENNA_POS, *PBTC_ANTENNA_POS;\n\n/* Bryant Add */\ntypedef enum _BTC_BT_OFFON {\n\tBTC_BT_OFF\t\t\t\t= 0x0,\n\tBTC_BT_ON\t\t\t\t= 0x1,\n} BTC_BTOFFON, *PBTC_BT_OFFON;\n\n#define BTC_5G_BAND 0x80\n\n/*==================================================\nFor following block is for coex offload\n==================================================*/\ntypedef struct _COL_H2C {\n\tu1Byte\topcode;\n\tu1Byte\topcode_ver:4;\n\tu1Byte\treq_num:4;\n\tu1Byte\tbuf[1];\n} COL_H2C, *PCOL_H2C;\n\n#define\tCOL_C2H_ACK_HDR_LEN\t3\ntypedef struct _COL_C2H_ACK {\n\tu1Byte\tstatus;\n\tu1Byte\topcode_ver:4;\n\tu1Byte\treq_num:4;\n\tu1Byte\tret_len;\n\tu1Byte\tbuf[1];\n} COL_C2H_ACK, *PCOL_C2H_ACK;\n\n#define\tCOL_C2H_IND_HDR_LEN\t3\ntypedef struct _COL_C2H_IND {\n\tu1Byte\ttype;\n\tu1Byte\tversion;\n\tu1Byte\tlength;\n\tu1Byte\tdata[1];\n} COL_C2H_IND, *PCOL_C2H_IND;\n\n/*============================================\nNOTE: for debug message, the following define should match\nthe strings in coexH2cResultString.\n============================================*/\ntypedef enum _COL_H2C_STATUS {\n\t/* c2h status */\n\tCOL_STATUS_C2H_OK\t\t\t\t\t\t\t\t= 0x00, /* Wifi received H2C request and check content ok. */\n\tCOL_STATUS_C2H_UNKNOWN\t\t\t\t\t\t\t= 0x01,\t/* Not handled routine */\n\tCOL_STATUS_C2H_UNKNOWN_OPCODE\t\t\t\t\t= 0x02,\t/* Invalid OP code, It means that wifi firmware received an undefiend OP code. */\n\tCOL_STATUS_C2H_OPCODE_VER_MISMATCH\t\t\t= 0x03, /* Wifi firmware and wifi driver mismatch, need to update wifi driver or wifi or. */\n\tCOL_STATUS_C2H_PARAMETER_ERROR\t\t\t\t= 0x04, /* Error paraneter.(ex: parameters = NULL but it should have values) */\n\tCOL_STATUS_C2H_PARAMETER_OUT_OF_RANGE\t\t= 0x05, /* Wifi firmware needs to check the parameters from H2C request and return the status.(ex: ch = 500, it's wrong) */\n\t/* other COL status start from here */\n\tCOL_STATUS_C2H_REQ_NUM_MISMATCH\t\t\t, /* c2h req_num mismatch, means this c2h is not we expected. */\n\tCOL_STATUS_H2C_HALMAC_FAIL\t\t\t\t\t, /* HALMAC return fail. */\n\tCOL_STATUS_H2C_TIMTOUT\t\t\t\t\t\t, /* not received the c2h response from fw */\n\tCOL_STATUS_INVALID_C2H_LEN\t\t\t\t\t, /* invalid coex offload c2h ack length, must >= 3 */\n\tCOL_STATUS_COEX_DATA_OVERFLOW\t\t\t\t, /* coex returned length over the c2h ack length. */\n\tCOL_STATUS_MAX\n} COL_H2C_STATUS, *PCOL_H2C_STATUS;\n\n#define\tCOL_MAX_H2C_REQ_NUM\t\t16\n\n#define\tCOL_H2C_BUF_LEN\t\t\t20\ntypedef enum _COL_OPCODE {\n\tCOL_OP_WIFI_STATUS_NOTIFY\t\t\t\t\t= 0x0,\n\tCOL_OP_WIFI_PROGRESS_NOTIFY\t\t\t\t\t= 0x1,\n\tCOL_OP_WIFI_INFO_NOTIFY\t\t\t\t\t\t= 0x2,\n\tCOL_OP_WIFI_POWER_STATE_NOTIFY\t\t\t\t= 0x3,\n\tCOL_OP_SET_CONTROL\t\t\t\t\t\t\t= 0x4,\n\tCOL_OP_GET_CONTROL\t\t\t\t\t\t\t= 0x5,\n\tCOL_OP_WIFI_OPCODE_MAX\n} COL_OPCODE, *PCOL_OPCODE;\n\ntypedef enum _COL_IND_TYPE {\n\tCOL_IND_BT_INFO\t\t\t\t\t\t\t\t= 0x0,\n\tCOL_IND_PSTDMA\t\t\t\t\t\t\t\t= 0x1,\n\tCOL_IND_LIMITED_TX_RX\t\t\t\t\t\t= 0x2,\n\tCOL_IND_COEX_TABLE\t\t\t\t\t\t\t= 0x3,\n\tCOL_IND_REQ\t\t\t\t\t\t\t\t\t= 0x4,\n\tCOL_IND_MAX\n} COL_IND_TYPE, *PCOL_IND_TYPE;\n\ntypedef struct _COL_SINGLE_H2C_RECORD {\n\tu1Byte\t\t\t\t\th2c_buf[COL_H2C_BUF_LEN];\t/* the latest sent h2c buffer */\n\tu4Byte\t\t\t\t\th2c_len;\n\tu1Byte\t\t\t\t\tc2h_ack_buf[COL_H2C_BUF_LEN];\t/* the latest received c2h buffer */\n\tu4Byte\t\t\t\t\tc2h_ack_len;\n\tu4Byte\t\t\t\t\tcount;\t\t\t\t\t\t\t\t\t/* the total number of the sent h2c command */\n\tu4Byte\t\t\t\t\tstatus[COL_STATUS_MAX];\t\t\t\t\t/* the c2h status for the sent h2c command */\n} COL_SINGLE_H2C_RECORD, *PCOL_SINGLE_H2C_RECORD;\n\ntypedef struct _COL_SINGLE_C2H_IND_RECORD {\n\tu1Byte\t\t\t\t\tind_buf[COL_H2C_BUF_LEN];\t/* the latest received c2h indication buffer */\n\tu4Byte\t\t\t\t\tind_len;\n\tu4Byte\t\t\t\t\tcount;\t\t\t\t\t\t\t\t\t/* the total number of the rcvd c2h indication */\n\tu4Byte\t\t\t\t\tstatus[COL_STATUS_MAX];\t\t\t\t\t/* the c2h indication verified status */\n} COL_SINGLE_C2H_IND_RECORD, *PCOL_SINGLE_C2H_IND_RECORD;\n\ntypedef struct _BTC_OFFLOAD {\n\t/* H2C command related */\n\tu1Byte\t\t\t\t\th2c_req_num;\n\tu4Byte\t\t\t\t\tcnt_h2c_sent;\n\tCOL_SINGLE_H2C_RECORD\th2c_record[COL_OP_WIFI_OPCODE_MAX];\n\n\t/* C2H Ack related */\n\tu4Byte\t\t\t\t\tcnt_c2h_ack;\n\tu4Byte\t\t\t\t\tstatus[COL_STATUS_MAX];\n\tstruct completion\t\tc2h_event[COL_MAX_H2C_REQ_NUM];\t/* for req_num = 1~COL_MAX_H2C_REQ_NUM */\n\tu1Byte\t\t\t\t\tc2h_ack_buf[COL_MAX_H2C_REQ_NUM][COL_H2C_BUF_LEN];\n\tu1Byte\t\t\t\t\tc2h_ack_len[COL_MAX_H2C_REQ_NUM];\n\n\t/* C2H Indication related */\n\tu4Byte\t\t\t\t\t\tcnt_c2h_ind;\n\tCOL_SINGLE_C2H_IND_RECORD\tc2h_ind_record[COL_IND_MAX];\n\tu4Byte\t\t\t\t\t\tc2h_ind_status[COL_STATUS_MAX];\n\tu1Byte\t\t\t\t\t\tc2h_ind_buf[COL_H2C_BUF_LEN];\n\tu1Byte\t\t\t\t\t\tc2h_ind_len;\n} BTC_OFFLOAD, *PBTC_OFFLOAD;\nextern BTC_OFFLOAD\t\t\t\tgl_coex_offload;\n/*==================================================*/\n\n/* BTC_LINK_MODE same as WIFI_LINK_MODE */\ntypedef enum _BTC_LINK_MODE{\n\tBTC_LINK_NONE=0,\n\tBTC_LINK_ONLY_GO,\n\tBTC_LINK_ONLY_GC,\n\tBTC_LINK_ONLY_STA,\n\tBTC_LINK_ONLY_AP,\n\tBTC_LINK_2G_MCC_GO_STA,\n\tBTC_LINK_5G_MCC_GO_STA,\n\tBTC_LINK_25G_MCC_GO_STA,\n\tBTC_LINK_2G_MCC_GC_STA,\n\tBTC_LINK_5G_MCC_GC_STA,\n\tBTC_LINK_25G_MCC_GC_STA,\n\tBTC_LINK_2G_SCC_GO_STA,\n\tBTC_LINK_5G_SCC_GO_STA,\n\tBTC_LINK_2G_SCC_GC_STA,\n\tBTC_LINK_5G_SCC_GC_STA,\n\tBTC_LINK_MAX=30\n}BTC_LINK_MODE, *PBTC_LINK_MODE;\n\n\nstruct btc_wifi_link_info {\n\tBTC_LINK_MODE link_mode; /* LinkMode */\n\tu1Byte sta_center_channel; /* StaCenterChannel */\n\tu1Byte p2p_center_channel; /* P2PCenterChannel\t*/\n\tBOOLEAN bany_client_join_go;\n\tBOOLEAN benable_noa;\n\tBOOLEAN bhotspot;\n};\n\ntypedef enum _BTC_MULTI_PORT_TDMA_MODE {\n\tBTC_MULTI_PORT_TDMA_MODE_NONE=0,\n\tBTC_MULTI_PORT_TDMA_MODE_2G_SCC_GO,\n\tBTC_MULTI_PORT_TDMA_MODE_2G_P2P_GO,\n\tBTC_MULTI_PORT_TDMA_MODE_2G_HOTSPOT_GO\n} BTC_MULTI_PORT_TDMA_MODE, *PBTC_MULTI_PORT_TDMA_MODE;\n\ntypedef struct btc_multi_port_tdma_info {\n\tBTC_MULTI_PORT_TDMA_MODE btc_multi_port_tdma_mode;\n\tu1Byte start_time_from_bcn;\n\tu1Byte bt_time;\n} BTC_MULTI_PORT_TDMA_INFO, *PBTC_MULTI_PORT_TDMA_INFO;\n\ntypedef u1Byte\n(*BFP_BTC_R1)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tu4Byte\t\t\tRegAddr\n\t);\ntypedef u2Byte\n(*BFP_BTC_R2)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tu4Byte\t\t\tRegAddr\n\t);\ntypedef u4Byte\n(*BFP_BTC_R4)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tu4Byte\t\t\tRegAddr\n\t);\ntypedef VOID\n(*BFP_BTC_W1)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tu4Byte\t\t\tRegAddr,\n\tIN\tu1Byte\t\t\tData\n\t);\ntypedef VOID\n(*BFP_BTC_W1_BIT_MASK)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tu4Byte\t\t\tregAddr,\n\tIN\tu1Byte\t\t\tbitMask,\n\tIN\tu1Byte\t\t\tdata1b\n\t);\ntypedef VOID\n(*BFP_BTC_W2)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tu4Byte\t\t\tRegAddr,\n\tIN\tu2Byte\t\t\tData\n\t);\ntypedef VOID\n(*BFP_BTC_W4)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tu4Byte\t\t\tRegAddr,\n\tIN\tu4Byte\t\t\tData\n\t);\ntypedef VOID\n(*BFP_BTC_LOCAL_REG_W1)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tu4Byte\t\t\tRegAddr,\n\tIN\tu1Byte\t\t\tData\n\t);\ntypedef u4Byte\n(*BFP_BTC_R_LINDIRECT)(\n\tIN \tPVOID\t\t\tpBtcContext,\n\tIN\tu2Byte\t\t\treg_addr\n\t);\ntypedef VOID\n(*BFP_BTC_R_SCBD)(\n\tIN \tPVOID\t\t\tpBtcContext,\n\tIN\tpu2Byte\t\t\tscore_board_val\n\t);\ntypedef VOID\n(*BFP_BTC_W_SCBD)(\n\tIN \tPVOID\t\t\tpBtcContext,\n\tIN\tu2Byte\t\t\tbitpos,\n\tIN\tBOOLEAN\t\t\tstate\n\t);\ntypedef VOID\n(*BFP_BTC_W_LINDIRECT)(\n\tIN \tPVOID\t\t\tpBtcContext,\n\tIN\tu2Byte\t\t\treg_addr,\n\tIN\tu4Byte\t\t\tbit_mask,\n\tIN\tu4Byte \t\t\treg_value\n\t);\ntypedef VOID\n(*BFP_BTC_SET_BB_REG)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tu4Byte\t\t\tRegAddr,\n\tIN\tu4Byte\t\t\tBitMask,\n\tIN\tu4Byte\t\t\tData\n\t);\ntypedef u4Byte\n(*BFP_BTC_GET_BB_REG)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tu4Byte\t\t\tRegAddr,\n\tIN\tu4Byte\t\t\tBitMask\n\t);\ntypedef VOID\n(*BFP_BTC_SET_RF_REG)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tenum rf_path\t\teRFPath,\n\tIN\tu4Byte\t\t\tRegAddr,\n\tIN\tu4Byte\t\t\tBitMask,\n\tIN\tu4Byte\t\t\tData\n\t);\ntypedef u4Byte\n(*BFP_BTC_GET_RF_REG)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tenum rf_path\t\teRFPath,\n\tIN\tu4Byte\t\t\tRegAddr,\n\tIN\tu4Byte\t\t\tBitMask\n\t);\ntypedef VOID\n(*BFP_BTC_FILL_H2C)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tu1Byte\t\t\telementId,\n\tIN\tu4Byte\t\t\tcmdLen,\n\tIN\tpu1Byte\t\t\tpCmdBuffer\n\t);\n\ntypedef\tBOOLEAN\n(*BFP_BTC_GET)(\n\tIN\tPVOID\t\t\tpBtCoexist,\n\tIN\tu1Byte\t\t\tgetType,\n\tOUT\tPVOID\t\t\tpOutBuf\n\t);\n\ntypedef\tBOOLEAN\n(*BFP_BTC_SET)(\n\tIN\tPVOID\t\t\tpBtCoexist,\n\tIN\tu1Byte\t\t\tsetType,\n\tOUT\tPVOID\t\t\tpInBuf\n\t);\ntypedef u2Byte\n(*BFP_BTC_SET_BT_REG)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tu1Byte\t\t\tregType,\n\tIN\tu4Byte\t\t\toffset,\n\tIN\tu4Byte\t\t\tvalue\n\t);\ntypedef BOOLEAN\n(*BFP_BTC_SET_BT_ANT_DETECTION)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tu1Byte\t\t\ttxTime,\n\tIN\tu1Byte\t\t\tbtChnl\n\t);\n\ntypedef BOOLEAN\n(*BFP_BTC_SET_BT_TRX_MASK)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tu1Byte\t\t\tbt_trx_mask\n\t);\n\ntypedef u4Byte\n(*BFP_BTC_GET_BT_REG)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tu1Byte\t\t\tregType,\n\tIN\tu4Byte\t\t\toffset\n\t);\ntypedef VOID\n(*BFP_BTC_DISP_DBG_MSG)(\n\tIN\tPVOID\t\t\tpBtCoexist,\n\tIN\tu1Byte\t\t\tdispType\n\t);\n\ntypedef COL_H2C_STATUS\n(*BFP_BTC_COEX_H2C_PROCESS)(\n\tIN\tPVOID\t\t\tpBtCoexist,\n\tIN\tu1Byte\t\t\topcode,\n\tIN\tu1Byte\t\t\topcode_ver,\n\tIN\tpu1Byte\t\t\tph2c_par,\n\tIN\tu1Byte\t\t\th2c_par_len\n\t);\n\ntypedef u4Byte\n(*BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE)(\n\tIN\tPVOID\t\t\tpBtcContext\n\t);\n\ntypedef u4Byte\n(*BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION)(\n\tIN\tPVOID\t\t\tpBtcContext\n\t);\n\ntypedef u4Byte\n(*BFP_BTC_GET_PHYDM_VERSION)(\n\tIN\tPVOID\t\t\tpBtcContext\n\t);\n\ntypedef u1Byte\n(*BFP_BTC_SET_TIMER) \t(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tu4Byte \t\t\ttype,\n\tIN\tu4Byte\t\t\tval\n\t);\n\ntypedef u4Byte\n(*BFP_BTC_SET_ATOMIC) \t(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tpu4Byte \t\ttarget,\n\tIN\tu4Byte\t\t\tval\n\t);\n\n\ntypedef VOID\n(*BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD)(\n\tIN\tPVOID\t\tpDM_Odm,\n\tIN\tu1Byte\t\tRA_offset_direction,\n\tIN\tu1Byte\t\tRA_threshold_offset\n\t);\n\ntypedef u4Byte\n(*BTC_PHYDM_CMNINFOQUERY)(\n\tIN\t\tPVOID\tpDM_Odm,\n\tIN\t\tu1Byte\tinfo_type\n\t);\n\ntypedef VOID\n(*BTC_REDUCE_WL_TX_POWER)(\n\tIN\t\tPVOID\t\tpDM_Odm,\n\tIN\t\ts1Byte\t\ttx_power\n\t);\n\ntypedef VOID\n(*BTC_PHYDM_MODIFY_ANTDIV_HWSW)(\n\tIN\t\tPVOID\tpDM_Odm,\n\tIN\t\tu1Byte\ttype\n\t);\n\ntypedef u1Byte\n(*BFP_BTC_GET_ANT_DET_VAL_FROM_BT)(\n\n\tIN\tPVOID\t\t\tpBtcContext\n\t);\n\ntypedef u1Byte\n(*BFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT)(\n\tIN\tPVOID\t\t\tpBtcContext\n\t);\n\ntypedef u4Byte\n(*BFP_BTC_GET_BLE_SCAN_PARA_FROM_BT)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN  u1Byte\t\t\tscanType\n\t);\n\ntypedef BOOLEAN\n(*BFP_BTC_GET_BT_AFH_MAP_FROM_BT)(\n\tIN\tPVOID\t\t\tpBtcContext,\n\tIN\tu1Byte\t\t\tmapType,\n\tOUT\tpu1Byte\t\t\tafhMap\n\t);\n\nstruct  btc_bt_info {\n\tboolean\t\t\t\t\tbt_disabled;\n\tboolean\t\t\t\tbt_enable_disable_change;\n\tu8\t\t\t\t\trssi_adjust_for_agc_table_on;\n\tu8\t\t\t\t\trssi_adjust_for_1ant_coex_type;\n\tboolean\t\t\t\t\tpre_bt_ctrl_agg_buf_size;\n\tboolean\t\t\t\t\tbt_ctrl_agg_buf_size;\n\tboolean\t\t\t\t\tpre_reject_agg_pkt;\n\tboolean\t\t\t\t\treject_agg_pkt;\n\tboolean\t\t\t\t\tincrease_scan_dev_num;\n\tboolean\t\t\t\t\tbt_tx_rx_mask;\n\tu8\t\t\t\t\tpre_agg_buf_size;\n\tu8\t\t\t\t\tagg_buf_size;\n\tboolean\t\t\t\t\tbt_busy;\n\tboolean\t\t\t\t\tlimited_dig;\n\tu16\t\t\t\t\tbt_hci_ver;\n\tu32\t\t\t\t\tbt_real_fw_ver;\n\tu32\t\t\t\t\tget_bt_fw_ver_cnt;\n\tu32\t\t\t\t\tbt_get_fw_ver;\n\tboolean\t\t\t\t\tmiracast_plus_bt;\n\n\tboolean\t\t\t\t\tbt_disable_low_pwr;\n\n\tboolean\t\t\t\t\tbt_ctrl_lps;\n\tboolean\t\t\t\t\tbt_lps_on;\n\tboolean\t\t\t\t\tforce_to_roam;\t/* for 1Ant solution */\n\tu8\t\t\t\t\tlps_val;\n\tu8\t\t\t\t\trpwm_val;\n\tu32\t\t\t\t\tra_mask;\n};\n\nstruct btc_stack_info {\n\tboolean\t\t\t\t\tprofile_notified;\n\tu16\t\t\t\t\thci_version;\t/* stack hci version */\n\tu8\t\t\t\t\tnum_of_link;\n\tboolean\t\t\t\t\tbt_link_exist;\n\tboolean\t\t\t\t\tsco_exist;\n\tboolean\t\t\t\t\tacl_exist;\n\tboolean\t\t\t\t\ta2dp_exist;\n\tboolean\t\t\t\t\thid_exist;\n\tu8\t\t\t\t\tnum_of_hid;\n\tboolean\t\t\t\t\tpan_exist;\n\tboolean\t\t\t\t\tunknown_acl_exist;\n\ts8\t\t\t\t\tmin_bt_rssi;\n};\n\nstruct btc_bt_link_info {\n\tboolean\t\t\t\t\tbt_link_exist;\n\tboolean\t\t\t\t\tbt_hi_pri_link_exist;\n\tboolean\t\t\t\t\tsco_exist;\n\tboolean\t\t\t\t\tsco_only;\n\tboolean\t\t\t\t\ta2dp_exist;\n\tboolean\t\t\t\t\ta2dp_only;\n\tboolean\t\t\t\t\thid_exist;\n\tboolean\t\t\t\t\thid_only;\n\tboolean\t\t\t\t\tpan_exist;\n\tboolean\t\t\t\t\tpan_only;\n\tboolean\t\t\t\t\tslave_role;\n\tboolean\t\t\t\t\tacl_busy;\n};\n\n#ifdef CONFIG_RF4CE_COEXIST\nstruct btc_rf4ce_info {\n\tu8\t\t\t\t\tlink_state;\n};\n#endif\n\nstruct btc_statistics {\n\tu32\t\t\t\t\tcnt_bind;\n\tu32\t\t\t\t\tcnt_power_on;\n\tu32\t\t\t\t\tcnt_pre_load_firmware;\n\tu32\t\t\t\t\tcnt_init_hw_config;\n\tu32\t\t\t\t\tcnt_init_coex_dm;\n\tu32\t\t\t\t\tcnt_ips_notify;\n\tu32\t\t\t\t\tcnt_lps_notify;\n\tu32\t\t\t\t\tcnt_scan_notify;\n\tu32\t\t\t\t\tcnt_connect_notify;\n\tu32\t\t\t\t\tcnt_media_status_notify;\n\tu32\t\t\t\t\tcnt_specific_packet_notify;\n\tu32\t\t\t\t\tcnt_bt_info_notify;\n\tu32\t\t\t\t\tcnt_rf_status_notify;\n\tu32\t\t\t\t\tcnt_periodical;\n\tu32\t\t\t\t\tcnt_coex_dm_switch;\n\tu32\t\t\t\t\tcnt_stack_operation_notify;\n\tu32\t\t\t\t\tcnt_dbg_ctrl;\n\tu32\t\t\t\t\tcnt_rate_id_notify;\n\tu32\t\t\t\t\tcnt_halt_notify;\n\tu32\t\t\t\t\tcnt_pnp_notify;\n};\n\nstruct btc_coexist {\n\tBOOLEAN\t\t\t\tbBinded;\t\t/*make sure only one adapter can bind the data context*/\n\tPVOID\t\t\t\tAdapter;\t\t/*default adapter*/\n\tstruct  btc_board_info\t\tboard_info;\n\tstruct  btc_bt_info\t\t\tbt_info;\t\t/*some bt info referenced by non-bt module*/\n\tstruct  btc_stack_info\t\tstack_info;\n\tstruct  btc_bt_link_info\t\tbt_link_info;\n\tstruct btc_wifi_link_info\twifi_link_info;\n\tstruct btc_wifi_link_info_ext\t\twifi_link_info_ext;\n\tstruct btc_coex_dm\t\t\tcoex_dm;\n\tstruct btc_coex_sta\t\t\tcoex_sta;\n\tstruct btc_rfe_type\t\t\trfe_type;\n\tconst struct btc_chip_para\t\t*chip_para;\n\n#ifdef CONFIG_RF4CE_COEXIST\n\tstruct  btc_rf4ce_info\t\trf4ce_info;\n#endif\n\tBTC_CHIP_INTERFACE\t\tchip_interface;\n\tPVOID\t\t\t\t\todm_priv;\n\n\tBOOLEAN\t\t\t\t\tinitilized;\n\tBOOLEAN\t\t\t\t\tstop_coex_dm;\n\tBOOLEAN\t\t\t\t\tmanual_control;\n\tBOOLEAN\t\t\t\t\tbdontenterLPS;\n\tpu1Byte\t\t\t\t\tcli_buf;\n\tstruct btc_statistics\t\tstatistics;\n\tu1Byte\t\t\t\tpwrModeVal[10];\n\tBOOLEAN dbg_mode;\n\tBOOLEAN auto_report;\n\tu8\tchip_type;\n\tBOOLEAN wl_rf_state_off;\n\n\t/* function pointers */\n\t/* io related */\n\tBFP_BTC_R1\t\t\tbtc_read_1byte;\n\tBFP_BTC_W1\t\t\tbtc_write_1byte;\n\tBFP_BTC_W1_BIT_MASK\tbtc_write_1byte_bitmask;\n\tBFP_BTC_R2\t\t\tbtc_read_2byte;\n\tBFP_BTC_W2\t\t\tbtc_write_2byte;\n\tBFP_BTC_R4\t\t\tbtc_read_4byte;\n\tBFP_BTC_W4\t\t\tbtc_write_4byte;\n\tBFP_BTC_LOCAL_REG_W1\tbtc_write_local_reg_1byte;\n\tBFP_BTC_R_LINDIRECT\t\tbtc_read_linderct;\n\tBFP_BTC_W_LINDIRECT\t\tbtc_write_linderct;\n\tBFP_BTC_R_SCBD\t\t\tbtc_read_scbd;\n\tBFP_BTC_W_SCBD\t\t\tbtc_write_scbd;\n\t/* read/write bb related */\n\tBFP_BTC_SET_BB_REG\tbtc_set_bb_reg;\n\tBFP_BTC_GET_BB_REG\tbtc_get_bb_reg;\n\n\t/* read/write rf related */\n\tBFP_BTC_SET_RF_REG\tbtc_set_rf_reg;\n\tBFP_BTC_GET_RF_REG\tbtc_get_rf_reg;\n\n\t/* fill h2c related */\n\tBFP_BTC_FILL_H2C\t\tbtc_fill_h2c;\n\t/* other */\n\tBFP_BTC_DISP_DBG_MSG\tbtc_disp_dbg_msg;\n\t/* normal get/set related */\n\tBFP_BTC_GET\t\t\tbtc_get;\n\tBFP_BTC_SET\t\t\tbtc_set;\n\n\tBFP_BTC_GET_BT_REG\tbtc_get_bt_reg;\n\tBFP_BTC_SET_BT_REG\tbtc_set_bt_reg;\n\n\tBFP_BTC_SET_BT_ANT_DETECTION\tbtc_set_bt_ant_detection;\n\n\tBFP_BTC_COEX_H2C_PROCESS\tbtc_coex_h2c_process;\n\tBFP_BTC_SET_BT_TRX_MASK\t\tbtc_set_bt_trx_mask;\n\tBFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE btc_get_bt_coex_supported_feature;\n\tBFP_BTC_GET_BT_COEX_SUPPORTED_VERSION btc_get_bt_coex_supported_version;\n\tBFP_BTC_GET_PHYDM_VERSION\t\tbtc_get_bt_phydm_version;\n\tBFP_BTC_SET_TIMER\t\t\t\tbtc_set_timer;\n\tBFP_BTC_SET_ATOMIC\t\t\tbtc_set_atomic;\n\tBTC_PHYDM_MODIFY_RA_PCR_THRESHLOD\tbtc_phydm_modify_RA_PCR_threshold;\n\tBTC_PHYDM_CMNINFOQUERY\t\t\t\tbtc_phydm_query_PHY_counter;\n\tBTC_REDUCE_WL_TX_POWER\t\t\t\tbtc_reduce_wl_tx_power;\n\tBTC_PHYDM_MODIFY_ANTDIV_HWSW\t\tbtc_phydm_modify_antdiv_hwsw;\n\tBFP_BTC_GET_ANT_DET_VAL_FROM_BT\t\tbtc_get_ant_det_val_from_bt;\n\tBFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT\tbtc_get_ble_scan_type_from_bt;\n\tBFP_BTC_GET_BLE_SCAN_PARA_FROM_BT\tbtc_get_ble_scan_para_from_bt;\n\tBFP_BTC_GET_BT_AFH_MAP_FROM_BT\t\tbtc_get_bt_afh_map_from_bt;\n\n\tunion {\n\t\t#ifdef CONFIG_RTL8822B\n\t\tstruct coex_dm_8822b_1ant\tcoex_dm_8822b_1ant;\n\t\tstruct coex_dm_8822b_2ant\tcoex_dm_8822b_2ant;\n\t\t#endif /* 8822B */\n\t\t#ifdef CONFIG_RTL8821C\n\t\tstruct coex_dm_8821c_1ant\tcoex_dm_8821c_1ant;\n\t\tstruct coex_dm_8821c_2ant\tcoex_dm_8821c_2ant;\n\t\t#endif /* 8821C */\n        #ifdef CONFIG_RTL8723D\n        struct coex_dm_8723d_1ant   coex_dm_8723d_1ant;\n        struct coex_dm_8723d_2ant   coex_dm_8723d_2ant;\n        #endif /* 8723D */\n\t};\n\n\tunion {\n\t\t#ifdef CONFIG_RTL8822B\n\t\tstruct coex_sta_8822b_1ant\tcoex_sta_8822b_1ant;\n\t\tstruct coex_sta_8822b_2ant\tcoex_sta_8822b_2ant;\n\t\t#endif /* 8822B */\n\t\t#ifdef CONFIG_RTL8821C\n\t\tstruct coex_sta_8821c_1ant\tcoex_sta_8821c_1ant;\n\t\tstruct coex_sta_8821c_2ant\tcoex_sta_8821c_2ant;\n\t\t#endif /* 8821C */\n        #ifdef CONFIG_RTL8723D\n        struct coex_sta_8723d_1ant  coex_sta_8723d_1ant;\n        struct coex_sta_8723d_2ant  coex_sta_8723d_2ant;\n        #endif /* 8723D */\n\t};\n\n\tunion {\n\t\t#ifdef CONFIG_RTL8822B\n\t\tstruct rfe_type_8822b_1ant\trfe_type_8822b_1ant;\n\t\tstruct rfe_type_8822b_2ant\trfe_type_8822b_2ant;\n\t\t#endif /* 8822B */\n\t\t#ifdef CONFIG_RTL8821C\n\t\tstruct rfe_type_8821c_1ant\trfe_type_8821c_1ant;\n\t\tstruct rfe_type_8821c_2ant\trfe_type_8821c_2ant;\n\t\t#endif /* 8821C */\n\t};\n\n\tunion {\n\t\t#ifdef CONFIG_RTL8822B\n\t\tstruct wifi_link_info_8822b_1ant\twifi_link_info_8822b_1ant;\n\t\tstruct wifi_link_info_8822b_2ant\twifi_link_info_8822b_2ant;\n\t\t#endif /* 8822B */\n\t\t#ifdef CONFIG_RTL8821C\n\t\tstruct wifi_link_info_8821c_1ant\twifi_link_info_8821c_1ant;\n\t\tstruct wifi_link_info_8821c_2ant\twifi_link_info_8821c_2ant;\n\t\t#endif /* 8821C */\n\t};\n\n};\ntypedef struct btc_coexist *PBTC_COEXIST;\n\nextern struct btc_coexist\tGLBtCoexist;\n\ntypedef\tvoid\n(*BFP_BTC_CHIP_SETUP)(\n\tIN\tPBTC_COEXIST\tpBtCoexist,\n\tIN\tu1Byte\t\t\tsetType\n\t);\n\nstruct btc_chip_para {\n\tconst char\t\t\t\t*chip_name;\n\tu32\t\t\t\tpara_ver_date;\n\tu32\t\t\t\tpara_ver;\n\tu32\t\t\t\tbt_desired_ver;\n\tboolean\t\t\tscbd_support;\n\tboolean\t\t\tmailbox_support;\n\tboolean\t\t\tlte_indirect_access;\n\tboolean\t\t\tnew_scbd10_def; /* TRUE: 1:fix 2M(8822c) */\n\tu8\t\t\t\tindirect_type;\t/* 0:17xx, 1:7cx */\n\tu8\t\t\t\tpstdma_type; /* 0: LPSoff, 1:LPSon */\n\tu8\t\t\t\tbt_rssi_type;\n\tu8\t\t\t\tant_isolation;\n\tu8\t\t\t\trssi_tolerance;\n\tu8\t\t\t\trx_path_num;\n\tu8\t\t\t\twl_rssi_step_num;\n\tconst u8\t\t\t\t*wl_rssi_step;\n\tu8\t\t\t\tbt_rssi_step_num;\n\tconst u8\t\t\t\t*bt_rssi_step;\n\tu8\t\t\t\ttable_sant_num;\n\tconst struct btc_coex_table_para \t*table_sant;\n\tu8\t\t\t\ttable_nsant_num;\n\tconst struct btc_coex_table_para \t*table_nsant;\n\tu8\t\t\t\ttdma_sant_num;\n\tconst struct btc_tdma_para \t*tdma_sant;\n\tu8\t\t\t\ttdma_nsant_num;\n\tconst struct btc_tdma_para \t*tdma_nsant;\n\tu8\t\t\t\twl_rf_para_tx_num;\n\tconst struct btc_rf_para\t\t*wl_rf_para_tx;\n\tconst struct btc_rf_para\t\t*wl_rf_para_rx;\n\tu8\t\t\t\tbt_afh_span_bw20;\n\tu8\t\t\t\tbt_afh_span_bw40;\n\tu8\t\t\t\tafh_5g_num;\n\tconst struct btc_5g_afh_map\t*afh_5g;\n\tBFP_BTC_CHIP_SETUP\t\tchip_setup;\n};\n\nBOOLEAN\nEXhalbtcoutsrc_InitlizeVariables(\n\tIN\tPVOID\t\tAdapter\n\t);\nVOID\nEXhalbtcoutsrc_PowerOnSetting(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist\n\t);\nVOID\nEXhalbtcoutsrc_PreLoadFirmware(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist\n\t);\nVOID\nEXhalbtcoutsrc_InitHwConfig(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist,\n\tIN\tBOOLEAN\t\t\t\tbWifiOnly\n\t);\nVOID\nEXhalbtcoutsrc_InitCoexDm(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist\n\t);\nVOID\nEXhalbtcoutsrc_IpsNotify(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist,\n\tIN\tu1Byte\t\t\ttype\n\t);\nVOID\nEXhalbtcoutsrc_LpsNotify(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist,\n\tIN\tu1Byte\t\t\ttype\n\t);\nVOID\nEXhalbtcoutsrc_ScanNotify(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist,\n\tIN\tu1Byte\t\t\ttype\n\t);\nVOID\nEXhalbtcoutsrc_SetAntennaPathNotify(\n\tIN\tPBTC_COEXIST\tpBtCoexist,\n\tIN\tu1Byte\t\t\ttype\n\t);\nVOID\nEXhalbtcoutsrc_ConnectNotify(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist,\n\tIN\tu1Byte\t\t\taction\n\t);\nVOID\nEXhalbtcoutsrc_MediaStatusNotify(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist,\n\tIN\tRT_MEDIA_STATUS\tmediaStatus\n\t);\nVOID\nEXhalbtcoutsrc_SpecificPacketNotify(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist,\n\tIN\tu1Byte\t\t\tpktType\n\t);\nVOID\nEXhalbtcoutsrc_BtInfoNotify(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist,\n\tIN\tpu1Byte\t\t\ttmpBuf,\n\tIN\tu1Byte\t\t\tlength\n\t);\nVOID\nEXhalbtcoutsrc_RfStatusNotify(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist,\n\tIN\tu1Byte\t\t\t\ttype\n\t);\nu4Byte\nEXhalbtcoutsrc_CoexTimerCheck(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist\n\t);\nu4Byte\nEXhalbtcoutsrc_WLStatusCheck(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist\n\t);\nVOID\nEXhalbtcoutsrc_WlFwDbgInfoNotify(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist,\n\tIN\tpu1Byte\t\t\ttmpBuf,\n\tIN\tu1Byte\t\t\tlength\n\t);\nVOID\nEXhalbtcoutsrc_rx_rate_change_notify(\n\tIN\tPBTC_COEXIST\tpBtCoexist,\n\tIN \tBOOLEAN\t\t\tis_data_frame,\n\tIN\tu1Byte\t\t\tbtc_rate_id\n\t);\nVOID\nEXhalbtcoutsrc_StackOperationNotify(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist,\n\tIN\tu1Byte\t\t\ttype\n\t);\nVOID\nEXhalbtcoutsrc_HaltNotify(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist\n\t);\nVOID\nEXhalbtcoutsrc_PnpNotify(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist,\n\tIN\tu1Byte\t\t\tpnpState\n\t);\nVOID\nEXhalbtcoutsrc_TimerNotify(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist,\n\tIN\tu4Byte timer_type\n);\nVOID\nEXhalbtcoutsrc_WLStatusChangeNotify(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist,\n\tIN\tu4Byte change_type\n);\nVOID\nEXhalbtcoutsrc_CoexDmSwitch(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist\n\t);\nVOID\nEXhalbtcoutsrc_Periodical(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist\n\t);\nVOID\nEXhalbtcoutsrc_DbgControl(\n\tIN\tPBTC_COEXIST\t\t\tpBtCoexist,\n\tIN\tu1Byte\t\t\t\topCode,\n\tIN\tu1Byte\t\t\t\topLen,\n\tIN\tpu1Byte\t\t\t\tpData\n\t);\nVOID\nEXhalbtcoutsrc_AntennaDetection(\n\tIN\tPBTC_COEXIST\t\t\tpBtCoexist,\n\tIN\tu4Byte\t\t\t\t\tcentFreq,\n\tIN\tu4Byte\t\t\t\t\toffset,\n\tIN\tu4Byte\t\t\t\t\tspan,\n\tIN\tu4Byte\t\t\t\t\tseconds\n\t);\nVOID\nEXhalbtcoutsrc_StackUpdateProfileInfo(\n\tVOID\n\t);\nVOID\nEXhalbtcoutsrc_SetHciVersion(\n\tIN\tu2Byte\thciVersion\n\t);\nVOID\nEXhalbtcoutsrc_SetBtPatchVersion(\n\tIN\tu2Byte\tbtHciVersion,\n\tIN\tu2Byte\tbtPatchVersion\n\t);\nVOID\nEXhalbtcoutsrc_UpdateMinBtRssi(\n\tIN\ts1Byte\tbtRssi\n\t);\n#if 0\nVOID\nEXhalbtcoutsrc_SetBtExist(\n\tIN\tBOOLEAN\t\tbBtExist\n\t);\n#endif\nVOID\nEXhalbtcoutsrc_SetChipType(\n\tIN\tu1Byte\t\tchipType\n\t);\nVOID\nEXhalbtcoutsrc_SetAntNum(\n\tIN\tu1Byte\t\ttype,\n\tIN\tu1Byte\t\tantNum\n\t);\nVOID\nEXhalbtcoutsrc_SetSingleAntPath(\n\tIN\tu1Byte\t\tsingleAntPath\n\t);\nVOID\nEXhalbtcoutsrc_DisplayBtCoexInfo(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist\n\t);\nVOID\nEXhalbtcoutsrc_DisplayAntDetection(\n\tIN\tPBTC_COEXIST\t\tpBtCoexist\n\t);\n\n#define\tMASKBYTE0\t\t0xff\n#define\tMASKBYTE1\t\t0xff00\n#define\tMASKBYTE2\t\t0xff0000\n#define\tMASKBYTE3\t\t0xff000000\n#define\tMASKHWORD\t0xffff0000\n#define\tMASKLWORD\t\t0x0000ffff\n#define\tMASKDWORD\t0xffffffff\n#define\tMASK12BITS\t\t0xfff\n#define\tMASKH4BITS\t\t0xf0000000\n#define\tMASKOFDM_D\t0xffc00000\n#define\tMASKCCK\t\t0x3f3f3f3f\n\n#endif\n"
  },
  {
    "path": "hal/btc/mp_precomp.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __MP_PRECOMP_H__\n#define __MP_PRECOMP_H__\n\n#include <drv_types.h>\n#include <hal_data.h>\n#include \"btc_basic_types.h\"\n\n#define BT_TMP_BUF_SIZE\t100\n\n#ifdef PLATFORM_LINUX\n#define rsprintf snprintf\n#define rstrncat(dst, src, src_size) strncat(dst, src, src_size)\n#elif defined(PLATFORM_WINDOWS)\n#define rsprintf sprintf_s\n#endif\n\n#define DCMD_Printf\t\t\tDBG_BT_INFO\n\n#define delay_ms(ms)\t\trtw_mdelay_os(ms)\n\n#ifdef bEnable\n#undef bEnable\n#endif\n\n#define WPP_SOFTWARE_TRACE 0\n\ntypedef enum _BTC_MSG_COMP_TYPE {\n\tCOMP_COEX\t\t= 0,\n\tCOMP_MAX\n} BTC_MSG_COMP_TYPE;\nextern u4Byte GLBtcDbgType[];\n\n#define DBG_OFF\t\t\t0\n#define DBG_SEC\t\t\t1\n#define DBG_SERIOUS\t\t2\n#define DBG_WARNING\t\t3\n#define DBG_LOUD\t\t4\n#define DBG_TRACE\t\t5\n\n#ifdef CONFIG_BT_COEXIST\n#define BT_SUPPORT\t\t1\n#define COEX_SUPPORT\t1\n#define HS_SUPPORT\t\t1\n#else\n#define BT_SUPPORT\t\t0\n#define COEX_SUPPORT\t0\n#define HS_SUPPORT\t\t0\n#endif\n\n/* for wifi only mode */\n#include \"hal_btcoex_wifionly.h\"\n\n#ifdef CONFIG_BT_COEXIST\n#define BTC_BTINFO_LENGTH_MAX 10\n\nstruct wifi_only_cfg;\nstruct btc_coexist;\n\n#ifdef CONFIG_RTL8192E\n#include \"halbtc8192e1ant.h\"\n#include \"halbtc8192e2ant.h\"\n#endif\n\n#ifdef CONFIG_RTL8723B\n#include \"halbtc8723bwifionly.h\"\n#include \"halbtc8723b1ant.h\"\n#include \"halbtc8723b2ant.h\"\n#endif\n\n#ifdef CONFIG_RTL8812A\n#include \"halbtc8812a1ant.h\"\n#include \"halbtc8812a2ant.h\"\n#endif\n\n#ifdef CONFIG_RTL8821A\n#include \"halbtc8821a1ant.h\"\n#include \"halbtc8821a2ant.h\"\n#endif\n\n#ifdef CONFIG_RTL8703B\n#include \"halbtc8703b1ant.h\"\n#endif\n\n#ifdef CONFIG_RTL8723D\n#include \"halbtc8723d1ant.h\"\n#include \"halbtc8723d2ant.h\"\n#endif\n\n#ifdef CONFIG_RTL8822B\n#include \"halbtc8822bwifionly.h\"\n#include \"halbtc8822b1ant.h\"\n#include \"halbtc8822b2ant.h\"\n#endif\n\n#ifdef CONFIG_RTL8821C\n#include \"halbtc8821cwifionly.h\"\n#include \"halbtc8821c1ant.h\"\n#include \"halbtc8821c2ant.h\"\n#endif\n\n#ifdef CONFIG_RTL8822C\n#include \"halbtccommon.h\"\n#include \"halbtc8822cwifionly.h\"\n#include \"halbtc8822c.h\"\n#endif\n\n#ifdef CONFIG_RTL8814A\n#include \"halbtc8814a2ant.h\"\n#endif\n\n#include \"halbtcoutsrc.h\"\n\n#else /* CONFIG_BT_COEXIST */\n\n#ifdef CONFIG_RTL8723B\n#include \"halbtc8723bwifionly.h\"\n#endif\n\n#ifdef CONFIG_RTL8822B\n#include \"halbtc8822bwifionly.h\"\n#endif\n\n#ifdef CONFIG_RTL8821C\n#include \"halbtc8821cwifionly.h\"\n#endif\n\n#ifdef CONFIG_RTL8822C\n#include \"halbtc8822cwifionly.h\"\n#endif\n\n#endif /* CONFIG_BT_COEXIST */\n\n#endif /*  __MP_PRECOMP_H__ */\n"
  },
  {
    "path": "hal/efuse/efuse_mask.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifdef CONFIG_USB_HCI\n\n\t#if defined(CONFIG_RTL8188E)\n\t\t#include \"rtl8188e/HalEfuseMask8188E_USB.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8812A)\n\t\t#include \"rtl8812a/HalEfuseMask8812A_USB.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8821A)\n\t\t#include \"rtl8812a/HalEfuseMask8821A_USB.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8192E)\n\t\t#include \"rtl8192e/HalEfuseMask8192E_USB.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8723B)\n\t\t#include \"rtl8723b/HalEfuseMask8723B_USB.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8814A)\n\t\t#include \"rtl8814a/HalEfuseMask8814A_USB.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8703B)\n\t\t#include \"rtl8703b/HalEfuseMask8703B_USB.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8723D)\n\t\t#include \"rtl8723d/HalEfuseMask8723D_USB.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8188F)\n\t\t#include \"rtl8188f/HalEfuseMask8188F_USB.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8188GTV)\n\t\t#include \"rtl8188gtv/HalEfuseMask8188GTV_USB.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8822B)\n\t\t#include \"rtl8822b/HalEfuseMask8822B_USB.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8821C)\n\t\t#include \"rtl8821c/HalEfuseMask8821C_USB.h\"\n\t#endif\n\t\n\t#if defined(CONFIG_RTL8710B)\n\t\t#include \"rtl8710b/HalEfuseMask8710B_USB.h\"\n\t#endif\n\t\n\t#if defined(CONFIG_RTL8192F)\n\t\t#include \"rtl8192f/HalEfuseMask8192F_USB.h\"\n\t#endif\n\t#if defined(CONFIG_RTL8822C)\n\t\t#include \"rtl8822c/HalEfuseMask8822C_USB.h\"\n\t#endif\n#endif /*CONFIG_USB_HCI*/\n\n#ifdef CONFIG_PCI_HCI\n\n\t#if defined(CONFIG_RTL8188E)\n\t\t#include \"rtl8188e/HalEfuseMask8188E_PCIE.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8812A)\n\t\t#include \"rtl8812a/HalEfuseMask8812A_PCIE.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8821A)\n\t\t#include \"rtl8812a/HalEfuseMask8821A_PCIE.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8192E)\n\t\t#include \"rtl8192e/HalEfuseMask8192E_PCIE.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8723B)\n\t\t#include \"rtl8723b/HalEfuseMask8723B_PCIE.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8814A)\n\t\t#include \"rtl8814a/HalEfuseMask8814A_PCIE.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8703B)\n\t\t#include \"rtl8703b/HalEfuseMask8703B_PCIE.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8822B)\n\t\t#include \"rtl8822b/HalEfuseMask8822B_PCIE.h\"\n\t#endif\n\t#if defined(CONFIG_RTL8723D)\n\t\t#include \"rtl8723d/HalEfuseMask8723D_PCIE.h\"\n\t#endif\n\t#if defined(CONFIG_RTL8821C)\n\t\t#include \"rtl8821c/HalEfuseMask8821C_PCIE.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8192F)\n\t\t#include \"rtl8192f/HalEfuseMask8192F_PCIE.h\"\n\t#endif\n\t#if defined(CONFIG_RTL8822C)\n\t\t#include \"rtl8822c/HalEfuseMask8822C_PCIE.h\"\n\t#endif\n#endif /*CONFIG_PCI_HCI*/\n#ifdef CONFIG_SDIO_HCI\n\t#if defined(CONFIG_RTL8723B)\n\t\t#include \"rtl8723b/HalEfuseMask8723B_SDIO.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8188E)\n\t\t#include \"rtl8188e/HalEfuseMask8188E_SDIO.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8703B)\n\t\t#include \"rtl8703b/HalEfuseMask8703B_SDIO.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8188F)\n\t\t#include \"rtl8188f/HalEfuseMask8188F_SDIO.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8188GTV)\n\t\t#include \"rtl8188gtv/HalEfuseMask8188GTV_SDIO.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8723D)\n\t\t#include \"rtl8723d/HalEfuseMask8723D_SDIO.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8192E)\n\t\t#include \"rtl8192e/HalEfuseMask8192E_SDIO.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8821A)\n\t\t#include \"rtl8812a/HalEfuseMask8821A_SDIO.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8821C)\n\t\t#include \"rtl8821c/HalEfuseMask8821C_SDIO.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8822B)\n\t\t#include \"rtl8822b/HalEfuseMask8822B_SDIO.h\"\n\t#endif\n\n\t#if defined(CONFIG_RTL8192F)\n\t\t#include \"rtl8192f/HalEfuseMask8192F_SDIO.h\"\n\t#endif\n\n\n\t#if defined(CONFIG_RTL8822C)\n\t\t#include \"rtl8822c/HalEfuseMask8822C_SDIO.h\"\n\t#endif\n\n#endif /*CONFIG_SDIO_HCI*/\n"
  },
  {
    "path": "hal/efuse/rtl8822c/HalEfuseMask8822C_PCIE.c",
    "content": "/******************************************************************************\n*\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n*\n* This program is free software; you can redistribute it and/or modify it\n* under the terms of version 2 of the GNU General Public License as\n* published by the Free Software Foundation.\n*\n* This program is distributed in the hope that it will be useful, but WITHOUT\n* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n* more details.\n*\n *****************************************************************************/\n#include <drv_types.h>\n\n#include \"HalEfuseMask8822C_PCIE.h\"\n\n/******************************************************************************\n*                           MPCIE.TXT\n******************************************************************************/\n\nu8 Array_MP_8822C_MPCIE_BT[] = {\n\t\t0x00,\n\t\t0x41,\n\t\t0x00,\n\t\t0x70,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x02,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x08,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0xCF,\n\t\t0xFF,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n};\n\nu8 Array_MP_8822C_MPCIE[] = {\n\t0xFF,\n\t0xF7,\n\t0xEF,\n\t0xDE,\n\t0xFC,\n\t0xFB,\n\t0x10,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x03,\n\t0xF7,\n\t0xD7,\n\t0x00,\n\t0x00,\n\t0x71,\n\t0xF1,\n\t0xFF,\n\t0xFF,\n\t0x7E,\n\t0xFC,\n\t0xFF,\n\t0xF1,\n\t0x00,\n\t0xD0,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n};\n\n/* BT  eFuse Maks */\nu16 EFUSE_GetBTArrayLen_MP_8822C_MPCIE(void)\n{\n\treturn sizeof(Array_MP_8822C_MPCIE_BT) / sizeof(u8);\n}\n\nvoid EFUSE_GetBTMaskArray_MP_8822C_MPCIE(u8 *Array)\n{\n\tu16 len = EFUSE_GetBTArrayLen_MP_8822C_MPCIE(), i = 0;\n\n\tfor (i = 0; i < len; ++i)\n\t\tArray[i] = Array_MP_8822C_MPCIE_BT[i];\n}\n\nBOOLEAN EFUSE_IsBTAddressMasked_MP_8822C_MPCIE(u16 Offset)\n{\n\tint r = Offset / 16;\n\tint c = (Offset % 16) / 2;\n\tint result = 0;\n\n\tif (c < 4) /*Upper double word*/\n\t\tresult = (Array_MP_8822C_MPCIE_BT[r] & (0x10 << c));\n\telse\n\t\tresult = (Array_MP_8822C_MPCIE_BT[r] & (0x01 << (c - 4)));\n\n\treturn (result > 0) ? 0 : 1;\n}\n\n/* WiFi eFuse Maks */\nu16 EFUSE_GetArrayLen_MP_8822C_MPCIE(void)\n{\n\treturn sizeof(Array_MP_8822C_MPCIE) / sizeof(u8);\n}\n\nvoid EFUSE_GetMaskArray_MP_8822C_MPCIE(u8 *Array)\n{\n\tu16 len = EFUSE_GetArrayLen_MP_8822C_MPCIE(), i = 0;\n\n\tfor (i = 0; i < len; ++i)\n\t\tArray[i] = Array_MP_8822C_MPCIE[i];\n}\n\nBOOLEAN EFUSE_IsAddressMasked_MP_8822C_MPCIE(u16 Offset)\n{\n\tint r = Offset / 16;\n\tint c = (Offset % 16) / 2;\n\tint result = 0;\n\n\tif (c < 4) /*Upper double word*/\n\t\tresult = (Array_MP_8822C_MPCIE[r] & (0x10 << c));\n\telse\n\t\tresult = (Array_MP_8822C_MPCIE[r] & (0x01 << (c - 4)));\n\n\treturn (result > 0) ? 0 : 1;\n}\n"
  },
  {
    "path": "hal/efuse/rtl8822c/HalEfuseMask8822C_PCIE.h",
    "content": "/******************************************************************************\n*\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n*\n* This program is free software; you can redistribute it and/or modify it\n* under the terms of version 2 of the GNU General Public License as\n* published by the Free Software Foundation.\n*\n* This program is distributed in the hope that it will be useful, but WITHOUT\n* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n* more details.\n*\n *****************************************************************************/\n\n\n/******************************************************************************\n*                           MPCIE.TXT\n******************************************************************************/\n\n\nu16 EFUSE_GetArrayLen_MP_8822C_MPCIE(void);\n\nvoid EFUSE_GetMaskArray_MP_8822C_MPCIE(u8 *Array);\n\nBOOLEAN EFUSE_IsAddressMasked_MP_8822C_MPCIE(u16 Offset);\n\nu16 EFUSE_GetBTArrayLen_MP_8822C_MPCIE(void);\n\nvoid EFUSE_GetBTMaskArray_MP_8822C_MPCIE(u8 *Array);\n\nBOOLEAN EFUSE_IsBTAddressMasked_MP_8822C_MPCIE(u16 Offset);\n\n"
  },
  {
    "path": "hal/efuse/rtl8822c/HalEfuseMask8822C_SDIO.c",
    "content": "/******************************************************************************\n*\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n*\n* This program is free software; you can redistribute it and/or modify it\n* under the terms of version 2 of the GNU General Public License as\n* published by the Free Software Foundation.\n*\n* This program is distributed in the hope that it will be useful, but WITHOUT\n* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n* more details.\n*\n *****************************************************************************/\n#include <drv_types.h>\n\n#include \"HalEfuseMask8822C_SDIO.h\"\n\n/******************************************************************************\n*                           MSDIO.TXT\n******************************************************************************/\t\nu8 Array_MP_8822C_MSDIO_BT[] = {\n\t\t0x00,\n\t\t0x41,\n\t\t0x00,\n\t\t0x70,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x02,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x08,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0xCF,\n\t\t0xFF,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n};\n\nu8 Array_MP_8822C_MSDIO[] = {\n\t0xFF,\n\t0xF7,\n\t0xEF,\n\t0xDE,\n\t0xFC,\n\t0xFB,\n\t0x10,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x03,\n\t0xF7,\n\t0xD7,\n\t0x00,\n\t0x00,\n\t0x71,\n\t0xF1,\n\t0x76,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x0E,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n};\n\n/*\tBT eFuse Mask  */\nu16 EFUSE_GetBTArrayLen_MP_8822C_MSDIO(void)\n{\n\treturn sizeof(Array_MP_8822C_MSDIO_BT) / sizeof(u8);\n}\n\nvoid EFUSE_GetBTMaskArray_MP_8822C_MSDIO(u8 *Array)\n{\n\tu16 len = EFUSE_GetBTArrayLen_MP_8822C_MSDIO(), i = 0;\n\n\tfor (i = 0; i < len; ++i)\n\t\tArray[i] = Array_MP_8822C_MSDIO_BT[i];\n}\n\nBOOLEAN EFUSE_IsBTAddressMasked_MP_8822C_MSDIO(u16 Offset)\n{\n\tint r = Offset / 16;\n\tint c = (Offset % 16) / 2;\n\tint result = 0;\n\n\tif (c < 4) /*Upper double word*/\n\t\tresult = (Array_MP_8822C_MSDIO_BT[r] & (0x10 << c));\n\telse\n\t\tresult = (Array_MP_8822C_MSDIO_BT[r] & (0x01 << (c - 4)));\n\n\treturn (result > 0) ? 0 : 1;\n}\n\n/*\tWiFi eFuse Mask  */\nu16 EFUSE_GetArrayLen_MP_8822C_MSDIO(void)\n{\n\treturn sizeof(Array_MP_8822C_MSDIO) / sizeof(u8);\n}\n\nvoid EFUSE_GetMaskArray_MP_8822C_MSDIO(u8 *Array)\n{\n\tu16 len = EFUSE_GetArrayLen_MP_8822C_MSDIO(), i = 0;\n\n\tfor (i = 0; i < len; ++i)\n\t\tArray[i] = Array_MP_8822C_MSDIO[i];\n}\n\nBOOLEAN EFUSE_IsAddressMasked_MP_8822C_MSDIO(u16 Offset)\n{\n\tint r = Offset / 16;\n\tint c = (Offset % 16) / 2;\n\tint result = 0;\n\n\tif (c < 4) /*Upper double word*/\n\t\tresult = (Array_MP_8822C_MSDIO[r] & (0x10 << c));\n\telse\n\t\tresult = (Array_MP_8822C_MSDIO[r] & (0x01 << (c - 4)));\n\n\treturn (result > 0) ? 0 : 1;\n}\n"
  },
  {
    "path": "hal/efuse/rtl8822c/HalEfuseMask8822C_SDIO.h",
    "content": "/******************************************************************************\n*\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n*\n* This program is free software; you can redistribute it and/or modify it\n* under the terms of version 2 of the GNU General Public License as\n* published by the Free Software Foundation.\n*\n* This program is distributed in the hope that it will be useful, but WITHOUT\n* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n* more details.\n*\n *****************************************************************************/\n\n\n\n/******************************************************************************\n*                           MSDIO.TXT\n******************************************************************************/\n\n\nu16 EFUSE_GetArrayLen_MP_8822C_MSDIO(void);\n\nvoid EFUSE_GetMaskArray_MP_8822C_MSDIO(u8 *Array);\n\nBOOLEAN EFUSE_IsAddressMasked_MP_8822C_MSDIO(u16 Offset);\n\nu16 EFUSE_GetBTArrayLen_MP_8822C_MSDIO(void);\n\nvoid EFUSE_GetBTMaskArray_MP_8822C_MSDIO(u8 *Array);\n\nBOOLEAN EFUSE_IsBTAddressMasked_MP_8822C_MSDIO(u16 Offset);\n\n"
  },
  {
    "path": "hal/efuse/rtl8822c/HalEfuseMask8822C_USB.c",
    "content": "/******************************************************************************\n*\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n*\n* This program is free software; you can redistribute it and/or modify it\n* under the terms of version 2 of the GNU General Public License as\n* published by the Free Software Foundation.\n*\n* This program is distributed in the hope that it will be useful, but WITHOUT\n* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n* more details.\n*\n *****************************************************************************/\n#include <drv_types.h>\n\n#include \"HalEfuseMask8822C_USB.h\"\n\n/******************************************************************************\n*                           MUSB.TXT\n******************************************************************************/\n\nu8 Array_MP_8822C_MUSB_BT[] = {\n\t\t0x00,\n\t\t0x41,\n\t\t0x00,\n\t\t0x70,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x02,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x08,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0xCF,\n\t\t0xFF,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n\t\t0x00,\n};\n\nu8 Array_MP_8822C_MUSB[] = {\n\t0xFF,\n\t0xF7,\n\t0xEF,\n\t0xDE,\n\t0xFC,\n\t0xFB,\n\t0x10,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x03,\n\t0xF7,\n\t0xD7,\n\t0x00,\n\t0x00,\n\t0x71,\n\t0xF1,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0xFF,\n\t0xFF,\n\t0xFF,\n\t0xFF,\n\t0xD0,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n\t0x00,\n};\n\n/* BT eFuse Mask */\n\nu16 EFUSE_GetBTArrayLen_MP_8822C_MUSB(void)\n{\n\treturn sizeof(Array_MP_8822C_MUSB_BT) / sizeof(u8);\n}\n\nvoid EFUSE_GetBTMaskArray_MP_8822C_MUSB(u8 *Array)\n{\n\tu16 len = EFUSE_GetBTArrayLen_MP_8822C_MUSB(), i = 0;\n\n\tfor (i = 0; i < len; ++i)\n\t\tArray[i] = Array_MP_8822C_MUSB_BT[i];\n}\n\nBOOLEAN EFUSE_IsBTAddressMasked_MP_8822C_MUSB(u16 Offset)\n{\n\tint r = Offset / 16;\n\tint c = (Offset % 16) / 2;\n\tint result = 0;\n\n\tif (c < 4) /*Upper double word*/\n\t\tresult = (Array_MP_8822C_MUSB_BT[r] & (0x10 << c));\n\telse\n\t\tresult = (Array_MP_8822C_MUSB_BT[r] & (0x01 << (c - 4)));\n\n\treturn (result > 0) ? 0 : 1;\n}\n\n\n/* WiFi eFuse Mask */\nu16 EFUSE_GetArrayLen_MP_8822C_MUSB(void)\n{\n\treturn sizeof(Array_MP_8822C_MUSB) / sizeof(u8);\n}\n\nvoid EFUSE_GetMaskArray_MP_8822C_MUSB(u8 *Array)\n{\n\tu16 len = EFUSE_GetArrayLen_MP_8822C_MUSB(), i = 0;\n\n\tfor (i = 0; i < len; ++i)\n\t\tArray[i] = Array_MP_8822C_MUSB[i];\n}\n\nBOOLEAN EFUSE_IsAddressMasked_MP_8822C_MUSB(u16 Offset)\n{\n\tint r = Offset / 16;\n\tint c = (Offset % 16) / 2;\n\tint result = 0;\n\n\tif (c < 4) /*Upper double word*/\n\t\tresult = (Array_MP_8822C_MUSB[r] & (0x10 << c));\n\telse\n\t\tresult = (Array_MP_8822C_MUSB[r] & (0x01 << (c - 4)));\n\n\treturn (result > 0) ? 0 : 1;\n}\n"
  },
  {
    "path": "hal/efuse/rtl8822c/HalEfuseMask8822C_USB.h",
    "content": "/******************************************************************************\n*\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n*\n* This program is free software; you can redistribute it and/or modify it\n* under the terms of version 2 of the GNU General Public License as\n* published by the Free Software Foundation.\n*\n* This program is distributed in the hope that it will be useful, but WITHOUT\n* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n* more details.\n*\n *****************************************************************************/\n\n\n\n/******************************************************************************\n*                           MUSB.TXT\n******************************************************************************/\n\n\nu16 EFUSE_GetArrayLen_MP_8822C_MUSB(void);\n\nvoid EFUSE_GetMaskArray_MP_8822C_MUSB(u8 *Array);\n\nBOOLEAN EFUSE_IsAddressMasked_MP_8822C_MUSB(u16 Offset);\n\nu16 EFUSE_GetBTArrayLen_MP_8822C_MUSB(void);\n\nvoid EFUSE_GetBTMaskArray_MP_8822C_MUSB(u8 *Array);\n\nBOOLEAN EFUSE_IsBTAddressMasked_MP_8822C_MUSB(u16 Offset);\n\n"
  },
  {
    "path": "hal/hal_btcoex.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define __HAL_BTCOEX_C__\n\n#ifdef CONFIG_BT_COEXIST\n\n#include <hal_data.h>\n#include <hal_btcoex.h>\n#include \"btc/mp_precomp.h\"\n\n/* ************************************\n *\t\tGlobal variables\n * ************************************ */\nconst char *const BtProfileString[] = {\n\t\"NONE\",\n\t\"A2DP\",\n\t\"PAN\",\n\t\"HID\",\n\t\"SCO\",\n};\n\nconst char *const BtSpecString[] = {\n\t\"1.0b\",\n\t\"1.1\",\n\t\"1.2\",\n\t\"2.0+EDR\",\n\t\"2.1+EDR\",\n\t\"3.0+HS\",\n\t\"4.0\",\n};\n\nconst char *const BtLinkRoleString[] = {\n\t\"Master\",\n\t\"Slave\",\n};\n\nconst char *const h2cStaString[] = {\n\t\"successful\",\n\t\"h2c busy\",\n\t\"rf off\",\n\t\"fw not read\",\n};\n\nconst char *const ioStaString[] = {\n\t\"success\",\n\t\"can not IO\",\n\t\"rf off\",\n\t\"fw not read\",\n\t\"wait io timeout\",\n\t\"invalid len\",\n\t\"idle Q empty\",\n\t\"insert waitQ fail\",\n\t\"unknown fail\",\n\t\"wrong level\",\n\t\"h2c stopped\",\n};\n\nconst char *const GLBtcWifiBwString[] = {\n\t\"11bg\",\n\t\"HT20\",\n\t\"HT40\",\n\t\"VHT80\",\n\t\"VHT160\"\n};\n\nconst char *const GLBtcWifiFreqString[] = {\n\t\"2.4G\",\n\t\"5G\",\n\t\"2.4G+5G\"\n};\n\nconst char *const GLBtcIotPeerString[] = {\n\t\"UNKNOWN\",\n\t\"REALTEK\",\n\t\"REALTEK_92SE\",\n\t\"BROADCOM\",\n\t\"RALINK\",\n\t\"ATHEROS\",\n\t\"CISCO\",\n\t\"MERU\",\n\t\"MARVELL\",\n\t\"REALTEK_SOFTAP\", /* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */\n\t\"SELF_SOFTAP\", /* Self is SoftAP */\n\t\"AIRGO\",\n\t\"INTEL\",\n\t\"RTK_APCLIENT\",\n\t\"REALTEK_81XX\",\n\t\"REALTEK_WOW\",\n\t\"REALTEK_JAGUAR_BCUTAP\",\n\t\"REALTEK_JAGUAR_CCUTAP\"\n};\n\nconst char *const coexOpcodeString[] = {\n\t\"Wifi status notify\",\n\t\"Wifi progress\",\n\t\"Wifi info\",\n\t\"Power state\",\n\t\"Set Control\",\n\t\"Get Control\"\n};\n\nconst char *const coexIndTypeString[] = {\n\t\"bt info\",\n\t\"pstdma\",\n\t\"limited tx/rx\",\n\t\"coex table\",\n\t\"request\"\n};\n\nconst char *const coexH2cResultString[] = {\n\t\"ok\",\n\t\"unknown\",\n\t\"un opcode\",\n\t\"opVer MM\",\n\t\"par Err\",\n\t\"par OoR\",\n\t\"reqNum MM\",\n\t\"halMac Fail\",\n\t\"h2c TimeOut\",\n\t\"Invalid c2h Len\",\n\t\"data overflow\"\n};\n\n#define HALBTCOUTSRC_AGG_CHK_WINDOW_IN_MS\t8000\n\nstruct btc_coexist GLBtCoexist;\nBTC_OFFLOAD gl_coex_offload;\nu8 GLBtcWiFiInScanState;\nu8 GLBtcWiFiInIQKState;\nu8 GLBtcWiFiInIPS;\nu8 GLBtcWiFiInLPS;\nu8 GLBtcBtCoexAliveRegistered;\n\n/*\n * BT control H2C/C2H\n */\n/* EXT_EID */\ntypedef enum _bt_ext_eid {\n\tC2H_WIFI_FW_ACTIVE_RSP\t= 0,\n\tC2H_TRIG_BY_BT_FW\n} BT_EXT_EID;\n\n/* C2H_STATUS */\ntypedef enum _bt_c2h_status {\n\tBT_STATUS_OK = 0,\n\tBT_STATUS_VERSION_MISMATCH,\n\tBT_STATUS_UNKNOWN_OPCODE,\n\tBT_STATUS_ERROR_PARAMETER\n} BT_C2H_STATUS;\n\n/* C2H BT OP CODES */\ntypedef enum _bt_op_code {\n\tBT_OP_GET_BT_VERSION\t\t\t\t\t= 0x00,\n\tBT_OP_WRITE_REG_ADDR\t\t\t\t\t= 0x0c,\n\tBT_OP_WRITE_REG_VALUE\t\t\t\t\t= 0x0d,\n\n\tBT_OP_READ_REG\t\t\t\t\t\t\t= 0x11,\n\n\tBT_LO_OP_GET_AFH_MAP_L\t\t\t\t\t= 0x1e,\n\tBT_LO_OP_GET_AFH_MAP_M\t\t\t\t\t= 0x1f,\n\tBT_LO_OP_GET_AFH_MAP_H\t\t\t\t\t= 0x20,\n\n\tBT_OP_GET_BT_COEX_SUPPORTED_FEATURE\t\t= 0x2a,\n\tBT_OP_GET_BT_COEX_SUPPORTED_VERSION\t\t= 0x2b,\n\tBT_OP_GET_BT_ANT_DET_VAL\t\t\t\t= 0x2c,\n\tBT_OP_GET_BT_BLE_SCAN_TYPE\t\t\t\t= 0x2d,\n\tBT_OP_GET_BT_BLE_SCAN_PARA\t\t\t\t= 0x2e,\n\tBT_OP_GET_BT_DEVICE_INFO\t\t\t\t= 0x30,\n\tBT_OP_GET_BT_FORBIDDEN_SLOT_VAL\t\t\t= 0x31,\n\tBT_OP_SET_BT_LANCONSTRAIN_LEVEL\t\t\t= 0x32,\n\tBT_OP_SET_BT_TEST_MODE_VAL\t\t\t\t= 0x33,\n\tBT_OP_MAX\n} BT_OP_CODE;\n\n#define BTC_MPOPER_TIMEOUT\t50\t/* unit: ms */\n\n#define C2H_MAX_SIZE\t\t16\nu8 GLBtcBtMpOperSeq;\n_mutex GLBtcBtMpOperLock;\n_timer GLBtcBtMpOperTimer;\n_sema GLBtcBtMpRptSema;\nu8 GLBtcBtMpRptSeq;\nu8 GLBtcBtMpRptStatus;\nu8 GLBtcBtMpRptRsp[C2H_MAX_SIZE];\nu8 GLBtcBtMpRptRspSize;\nu8 GLBtcBtMpRptWait;\nu8 GLBtcBtMpRptWiFiOK;\nu8 GLBtcBtMpRptBTOK;\n\n/*\n * Debug\n */\nu32 GLBtcDbgType[COMP_MAX];\nu8 GLBtcDbgBuf[BT_TMP_BUF_SIZE];\nu8\tgl_btc_trace_buf[BT_TMP_BUF_SIZE];\n\ntypedef struct _btcoexdbginfo {\n\tu8 *info;\n\tu32 size; /* buffer total size */\n\tu32 len; /* now used length */\n} BTCDBGINFO, *PBTCDBGINFO;\n\nBTCDBGINFO GLBtcDbgInfo;\n\n#define\tBT_Operation(Adapter)\t\t\t\t\t\t_FALSE\n\nstatic void DBG_BT_INFO_INIT(PBTCDBGINFO pinfo, u8 *pbuf, u32 size)\n{\n\tif (NULL == pinfo)\n\t\treturn;\n\n\t_rtw_memset(pinfo, 0, sizeof(BTCDBGINFO));\n\n\tif (pbuf && size) {\n\t\tpinfo->info = pbuf;\n\t\tpinfo->size = size;\n\t}\n}\n\nvoid DBG_BT_INFO(u8 *dbgmsg)\n{\n\tPBTCDBGINFO pinfo;\n\tu32 msglen, buflen;\n\tu8 *pbuf;\n\n\n\tpinfo = &GLBtcDbgInfo;\n\n\tif (NULL == pinfo->info)\n\t\treturn;\n\n\tmsglen = strlen(dbgmsg);\n\tif (pinfo->len + msglen > pinfo->size)\n\t\treturn;\n\n\tpbuf = pinfo->info + pinfo->len;\n\t_rtw_memcpy(pbuf, dbgmsg, msglen);\n\tpinfo->len += msglen;\n}\n\n/* ************************************\n *\t\tDebug related function\n * ************************************ */\nstatic u8 halbtcoutsrc_IsBtCoexistAvailable(PBTC_COEXIST pBtCoexist)\n{\n\tif (!pBtCoexist->bBinded ||\n\t    NULL == pBtCoexist->Adapter)\n\t\treturn _FALSE;\n\treturn _TRUE;\n}\n\nstatic void halbtcoutsrc_DbgInit(void)\n{\n\tu8\ti;\n\n\tfor (i = 0; i < COMP_MAX; i++)\n\t\tGLBtcDbgType[i] = 0;\n}\n\nstatic void halbtcoutsrc_EnterPwrLock(PBTC_COEXIST pBtCoexist)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj((PADAPTER)pBtCoexist->Adapter);\n\tstruct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);\n\n\t_enter_pwrlock(&pwrpriv->lock);\n}\n\nstatic void halbtcoutsrc_ExitPwrLock(PBTC_COEXIST pBtCoexist)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj((PADAPTER)pBtCoexist->Adapter);\n\tstruct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);\n\n\t_exit_pwrlock(&pwrpriv->lock);\n}\n\nstatic u8 halbtcoutsrc_IsHwMailboxExist(PBTC_COEXIST pBtCoexist)\n{\n\tif (pBtCoexist->board_info.bt_chip_type == BTC_CHIP_CSR_BC4\n\t    || pBtCoexist->board_info.bt_chip_type == BTC_CHIP_CSR_BC8\n\t   )\n\t\treturn _FALSE;\n\telse if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter))\n\t\treturn _FALSE;\n\telse\n\t\treturn _TRUE;\n}\n\nstatic u8 halbtcoutsrc_LeaveLps(PBTC_COEXIST pBtCoexist)\n{\n\tPADAPTER padapter;\n\n\n\tpadapter = pBtCoexist->Adapter;\n\n\tpBtCoexist->bt_info.bt_ctrl_lps = _TRUE;\n\tpBtCoexist->bt_info.bt_lps_on = _FALSE;\n\n\treturn rtw_btcoex_LPS_Leave(padapter);\n}\n\nvoid halbtcoutsrc_EnterLps(PBTC_COEXIST pBtCoexist)\n{\n\tPADAPTER padapter;\n\n\n\tpadapter = pBtCoexist->Adapter;\n\n\tif (pBtCoexist->bdontenterLPS == _FALSE) {\n\t\tpBtCoexist->bt_info.bt_ctrl_lps = _TRUE;\n\t\tpBtCoexist->bt_info.bt_lps_on = _TRUE;\n\n\t\trtw_btcoex_LPS_Enter(padapter);\n\t}\n}\n\nvoid halbtcoutsrc_NormalLps(PBTC_COEXIST pBtCoexist)\n{\n\tPADAPTER padapter;\n\n\n\n\tpadapter = pBtCoexist->Adapter;\n\n\tif (pBtCoexist->bt_info.bt_ctrl_lps) {\n\t\tpBtCoexist->bt_info.bt_lps_on = _FALSE;\n\t\trtw_btcoex_LPS_Leave(padapter);\n\t\tpBtCoexist->bt_info.bt_ctrl_lps = _FALSE;\n\n\t\t/* recover the LPS state to the original */\n#if 0\n\t\tpadapter->hal_func.UpdateLPSStatusHandler(\n\t\t\tpadapter,\n\t\t\tpPSC->RegLeisurePsMode,\n\t\t\tpPSC->RegPowerSaveMode);\n#endif\n\t}\n}\n\nvoid halbtcoutsrc_Pre_NormalLps(PBTC_COEXIST pBtCoexist)\n{\n\tPADAPTER padapter;\n\n\tpadapter = pBtCoexist->Adapter;\n\n\tif (pBtCoexist->bt_info.bt_ctrl_lps) {\n\t\tpBtCoexist->bt_info.bt_lps_on = _FALSE;\n\t\trtw_btcoex_LPS_Leave(padapter);\n\t}\n}\n\nvoid halbtcoutsrc_Post_NormalLps(PBTC_COEXIST pBtCoexist)\n{\n\tif (pBtCoexist->bt_info.bt_ctrl_lps)\n\t\tpBtCoexist->bt_info.bt_ctrl_lps = _FALSE;\n}\n\n/*\n *  Constraint:\n *\t   1. this function will request pwrctrl->lock\n */\nvoid halbtcoutsrc_LeaveLowPower(PBTC_COEXIST pBtCoexist)\n{\n#ifdef CONFIG_LPS_LCLK\n\tPADAPTER padapter;\n\tPHAL_DATA_TYPE pHalData;\n\tstruct pwrctrl_priv *pwrctrl;\n\ts32 ready;\n\tsystime stime;\n\ts32 utime;\n\tu32 timeout; /* unit: ms */\n\n\n\tpadapter = pBtCoexist->Adapter;\n\tpHalData = GET_HAL_DATA(padapter);\n\tpwrctrl = adapter_to_pwrctl(padapter);\n\tready = _FAIL;\n#ifdef LPS_RPWM_WAIT_MS\n\ttimeout = LPS_RPWM_WAIT_MS;\n#else /* !LPS_RPWM_WAIT_MS */\n\ttimeout = 30;\n#endif /* !LPS_RPWM_WAIT_MS */\n\n\tif (GLBtcBtCoexAliveRegistered == _TRUE)\n\t\treturn;\n\n\tstime = rtw_get_current_time();\n\tdo {\n\t\tready = rtw_register_task_alive(padapter, BTCOEX_ALIVE);\n\t\tif (_SUCCESS == ready)\n\t\t\tbreak;\n\n\t\tutime = rtw_get_passing_time_ms(stime);\n\t\tif (utime > timeout)\n\t\t\tbreak;\n\n\t\trtw_msleep_os(1);\n\t} while (1);\n\n\tGLBtcBtCoexAliveRegistered = _TRUE;\n#endif /* CONFIG_LPS_LCLK */\n}\n\n/*\n *  Constraint:\n *\t   1. this function will request pwrctrl->lock\n */\nvoid halbtcoutsrc_NormalLowPower(PBTC_COEXIST pBtCoexist)\n{\n#ifdef CONFIG_LPS_LCLK\n\tPADAPTER padapter;\n\n\tif (GLBtcBtCoexAliveRegistered == _FALSE)\n\t\treturn;\n\n\tpadapter = pBtCoexist->Adapter;\n\trtw_unregister_task_alive(padapter, BTCOEX_ALIVE);\n\n\tGLBtcBtCoexAliveRegistered = _FALSE;\n#endif /* CONFIG_LPS_LCLK */\n}\n\nvoid halbtcoutsrc_DisableLowPower(PBTC_COEXIST pBtCoexist, u8 bLowPwrDisable)\n{\n\tpBtCoexist->bt_info.bt_disable_low_pwr = bLowPwrDisable;\n\tif (bLowPwrDisable)\n\t\thalbtcoutsrc_LeaveLowPower(pBtCoexist);\t\t/* leave 32k low power. */\n\telse\n\t\thalbtcoutsrc_NormalLowPower(pBtCoexist);\t/* original 32k low power behavior. */\n}\n\nvoid halbtcoutsrc_AggregationCheck(PBTC_COEXIST pBtCoexist)\n{\n\tPADAPTER padapter;\n\tBOOLEAN bNeedToAct = _FALSE;\n\tstatic u32 preTime = 0;\n\tu32 curTime = 0;\n\n\tpadapter = pBtCoexist->Adapter;\n\n\t/* ===================================== */\n\t/* To void continuous deleteBA=>addBA=>deleteBA=>addBA */\n\t/* This function is not allowed to continuous called. */\n\t/* It can only be called after 8 seconds. */\n\t/* ===================================== */\n\n\tcurTime = rtw_systime_to_ms(rtw_get_current_time());\n\tif ((curTime - preTime) < HALBTCOUTSRC_AGG_CHK_WINDOW_IN_MS)\t/* over 8 seconds you can execute this function again. */\n\t\treturn;\n\telse\n\t\tpreTime = curTime;\n\n\tif (pBtCoexist->bt_info.reject_agg_pkt) {\n\t\tbNeedToAct = _TRUE;\n\t\tpBtCoexist->bt_info.pre_reject_agg_pkt = pBtCoexist->bt_info.reject_agg_pkt;\n\t} else {\n\t\tif (pBtCoexist->bt_info.pre_reject_agg_pkt) {\n\t\t\tbNeedToAct = _TRUE;\n\t\t\tpBtCoexist->bt_info.pre_reject_agg_pkt = pBtCoexist->bt_info.reject_agg_pkt;\n\t\t}\n\n\t\tif (pBtCoexist->bt_info.pre_bt_ctrl_agg_buf_size !=\n\t\t    pBtCoexist->bt_info.bt_ctrl_agg_buf_size) {\n\t\t\tbNeedToAct = _TRUE;\n\t\t\tpBtCoexist->bt_info.pre_bt_ctrl_agg_buf_size = pBtCoexist->bt_info.bt_ctrl_agg_buf_size;\n\t\t}\n\n\t\tif (pBtCoexist->bt_info.bt_ctrl_agg_buf_size) {\n\t\t\tif (pBtCoexist->bt_info.pre_agg_buf_size !=\n\t\t\t    pBtCoexist->bt_info.agg_buf_size)\n\t\t\t\tbNeedToAct = _TRUE;\n\t\t\tpBtCoexist->bt_info.pre_agg_buf_size = pBtCoexist->bt_info.agg_buf_size;\n\t\t}\n\t}\n\n\tif (bNeedToAct)\n\t\trtw_btcoex_rx_ampdu_apply(padapter);\n}\n\nu8 halbtcoutsrc_is_autoload_fail(PBTC_COEXIST pBtCoexist)\n{\n\tPADAPTER padapter;\n\tPHAL_DATA_TYPE pHalData;\n\n\tpadapter = pBtCoexist->Adapter;\n\tpHalData = GET_HAL_DATA(padapter);\n\n\treturn pHalData->bautoload_fail_flag;\n}\n\nu8 halbtcoutsrc_is_fw_ready(PBTC_COEXIST pBtCoexist)\n{\n\tPADAPTER padapter;\n\n\tpadapter = pBtCoexist->Adapter;\n\n\treturn GET_HAL_DATA(padapter)->bFWReady;\n}\n\nu8 halbtcoutsrc_IsDualBandConnected(PADAPTER padapter)\n{\n\tu8 ret = BTC_MULTIPORT_SCC;\n\n#ifdef CONFIG_MCC_MODE\n\tif (MCC_EN(padapter) && (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))) {\n\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\t\tstruct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);\n\t\tu8 band0 = mccobjpriv->iface[0]->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;\n\t\tu8 band1 = mccobjpriv->iface[1]->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;\n\n\t\tif (band0 != band1)\n\t\t\tret = BTC_MULTIPORT_MCC_DUAL_BAND;\n\t\telse\n\t\t\tret = BTC_MULTIPORT_MCC_DUAL_CHANNEL;\n\t}\n#endif\n\n\treturn ret;\n}\n\nu8 halbtcoutsrc_IsWifiBusy(PADAPTER padapter)\n{\n\tif (rtw_mi_check_status(padapter, MI_AP_ASSOC))\n\t\treturn _TRUE;\n\tif (rtw_mi_busy_traffic_check(padapter, _FALSE))\n\t\treturn _TRUE;\n\n\treturn _FALSE;\n}\n\nstatic u32 _halbtcoutsrc_GetWifiLinkStatus(PADAPTER padapter)\n{\n\tstruct mlme_priv *pmlmepriv;\n\tu8 bp2p;\n\tu32 portConnectedStatus;\n\n\n\tpmlmepriv = &padapter->mlmepriv;\n\tbp2p = _FALSE;\n\tportConnectedStatus = 0;\n\n#ifdef CONFIG_P2P\n\tif (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE))\n\t\tbp2p = _TRUE;\n#endif /* CONFIG_P2P */\n\n\tif (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {\n\t\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {\n\t\t\tif (_TRUE == bp2p)\n\t\t\t\tportConnectedStatus |= WIFI_P2P_GO_CONNECTED;\n\t\t\telse\n\t\t\t\tportConnectedStatus |= WIFI_AP_CONNECTED;\n\t\t} else {\n\t\t\tif (_TRUE == bp2p)\n\t\t\t\tportConnectedStatus |= WIFI_P2P_GC_CONNECTED;\n\t\t\telse\n\t\t\t\tportConnectedStatus |= WIFI_STA_CONNECTED;\n\t\t}\n\t}\n\n\treturn portConnectedStatus;\n}\n\nu32 halbtcoutsrc_GetWifiLinkStatus(PBTC_COEXIST pBtCoexist)\n{\n\t/* ================================= */\n\t/* return value: */\n\t/* [31:16]=> connected port number */\n\t/* [15:0]=> port connected bit define */\n\t/* ================================ */\n\n\tPADAPTER padapter;\n\tu32 retVal;\n\tu32 portConnectedStatus, numOfConnectedPort;\n\tstruct dvobj_priv *dvobj;\n\t_adapter *iface;\n\tint i;\n\n\tpadapter = pBtCoexist->Adapter;\n\tretVal = 0;\n\tportConnectedStatus = 0;\n\tnumOfConnectedPort = 0;\n\tdvobj = adapter_to_dvobj(padapter);\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif ((iface) && rtw_is_adapter_up(iface)) {\n\t\t\tretVal = _halbtcoutsrc_GetWifiLinkStatus(iface);\n\t\t\tif (retVal) {\n\t\t\t\tportConnectedStatus |= retVal;\n\t\t\t\tnumOfConnectedPort++;\n\t\t\t}\n\t\t}\n\t}\n\tretVal = (numOfConnectedPort << 16) | portConnectedStatus;\n\n\treturn retVal;\n}\n\nstruct btc_wifi_link_info halbtcoutsrc_getwifilinkinfo(PBTC_COEXIST pBtCoexist)\n{\n\tu8 n_assoc_iface = 0, i =0, mcc_en = _FALSE;\n\tPADAPTER adapter = NULL;\n\tPADAPTER iface = NULL;\n\tPADAPTER sta_iface = NULL, p2p_iface = NULL, ap_iface = NULL;\n\tBTC_LINK_MODE btc_link_moe = BTC_LINK_MAX;\n\tstruct dvobj_priv *dvobj = NULL;\n\tstruct mlme_ext_priv *mlmeext = NULL;\n\tstruct btc_wifi_link_info wifi_link_info;\n\n\tadapter = (PADAPTER)pBtCoexist->Adapter;\n\tdvobj = adapter_to_dvobj(adapter);\n\tn_assoc_iface = rtw_mi_get_assoc_if_num(adapter);\n\n\t/* init value */\n\twifi_link_info.link_mode = BTC_LINK_NONE;\n\twifi_link_info.sta_center_channel = 0;\n\twifi_link_info.p2p_center_channel = 0;\n\twifi_link_info.bany_client_join_go = _FALSE;\n\twifi_link_info.benable_noa = _FALSE;\n\twifi_link_info.bhotspot = _FALSE;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (!iface)\n\t\t\tcontinue;\n\t\t\n\t\tmlmeext = &iface->mlmeextpriv;\n\t\tif (MLME_IS_GO(iface)) {\n\t\t\twifi_link_info.link_mode = BTC_LINK_ONLY_GO;\n\t\t\twifi_link_info.p2p_center_channel =\n\t\t\t\trtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);\n\t\t\tp2p_iface\t = iface;\n\t\t\tif (rtw_linked_check(iface))\n\t\t\t\twifi_link_info.bany_client_join_go = _TRUE;\n\t\t} else if (MLME_IS_GC(iface)) {\n\t\t\twifi_link_info.link_mode = BTC_LINK_ONLY_GC;\n\t\t\twifi_link_info.p2p_center_channel =\n\t\t\t\trtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);\n\t\t\tp2p_iface = iface;\n\t\t} else if (MLME_IS_AP(iface)) {\n\t\t\twifi_link_info.link_mode = BTC_LINK_ONLY_AP;\n\t\t\tap_iface = iface;\n\t\t\twifi_link_info.p2p_center_channel =\n\t\t\t\trtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);\n\t\t} else if (MLME_IS_STA(iface) && rtw_linked_check(iface)) {\n\t\t\twifi_link_info.link_mode = BTC_LINK_ONLY_STA;\n\t\t\twifi_link_info.sta_center_channel =\n\t\t\t\trtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);\n\t\t\tsta_iface = iface;\n\t\t}\n\t}\n\n#ifdef CONFIG_MCC_MODE\n\tif (MCC_EN(adapter)) {\n\t\tif (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))\n\t\t\tmcc_en = _TRUE;\n\t}\n#endif/* CONFIG_MCC_MODE */\n\n\tif (n_assoc_iface == 0) {\n\t\twifi_link_info.link_mode = BTC_LINK_NONE;\n\t} else if (n_assoc_iface == 1) {\n\t\t/* by pass */\n\t} else if (n_assoc_iface == 2) {\t\n\t\tif (sta_iface && p2p_iface) {\n\t\t\tu8 band_sta = sta_iface->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;\n\t\t\tu8 band_p2p = p2p_iface->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;\n\t\t\tif (band_sta == band_p2p) {\n\t\t\t\tswitch (band_sta) {\n\t\t\t\tcase BAND_ON_2_4G:\n\t\t\t\t\tif (MLME_IS_GO(p2p_iface))\n\t\t\t\t\t\twifi_link_info.link_mode =\n\t\t\t\t\t\t\tmcc_en == _TRUE ?  BTC_LINK_2G_MCC_GO_STA : BTC_LINK_2G_SCC_GO_STA;\n\t\t\t\t\telse if (MLME_IS_GC(p2p_iface))\n\t\t\t\t\t\twifi_link_info.link_mode =\n\t\t\t\t\t\t\tmcc_en == _TRUE ?  BTC_LINK_2G_MCC_GC_STA : BTC_LINK_2G_SCC_GC_STA;\n\t\t\t\t\tbreak;\n\t\t\t\tcase BAND_ON_5G:\n\t\t\t\t\tif (MLME_IS_GO(p2p_iface))\n\t\t\t\t\t\twifi_link_info.link_mode =\n\t\t\t\t\t\t\tmcc_en == _TRUE ?  BTC_LINK_5G_MCC_GO_STA : BTC_LINK_5G_SCC_GO_STA;\n\t\t\t\t\telse if (MLME_IS_GC(p2p_iface))\n\t\t\t\t\t\twifi_link_info.link_mode =\n\t\t\t\t\t\t\tmcc_en == _TRUE ?  BTC_LINK_5G_MCC_GC_STA : BTC_LINK_5G_SCC_GC_STA;\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif (MLME_IS_GO(p2p_iface))\n\t\t\t\t\twifi_link_info.link_mode = BTC_LINK_25G_MCC_GO_STA;\n\t\t\t\telse if (MLME_IS_GC(p2p_iface))\n\t\t\t\t\twifi_link_info.link_mode = BTC_LINK_25G_MCC_GC_STA;\n\t\t\t}\n\t\t}\n\t} else {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tRTW_ERR(\"%s do not support n_assoc_iface > 2 (ant_num == 1)\", __func__);\n\t}\n\n\treturn wifi_link_info;\n}\n\n\nstatic void _btmpoper_timer_hdl(void *p)\n{\n\tif (GLBtcBtMpRptWait == _TRUE) {\n\t\tGLBtcBtMpRptWait = _FALSE;\n\t\t_rtw_up_sema(&GLBtcBtMpRptSema);\n\t}\n}\n\n/*\n * !IMPORTANT!\n *\tBefore call this function, caller should acquire \"GLBtcBtMpOperLock\"!\n *\tOthrewise there will be racing problem and something may go wrong.\n */\nstatic u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cmd, u8 size)\n{\n\tPADAPTER padapter;\n\tu8 buf[H2C_BTMP_OPER_LEN] = {0};\n\tu8 buflen;\n\tu8 seq;\n\ts32 ret;\n\n\n\tif (!cmd && size)\n\t\tsize = 0;\n\tif ((size + 2) > H2C_BTMP_OPER_LEN)\n\t\treturn BT_STATUS_H2C_LENGTH_EXCEEDED;\n\tbuflen = size + 2;\n\n\tseq = GLBtcBtMpOperSeq & 0xF;\n\tGLBtcBtMpOperSeq++;\n\n\tbuf[0] = (opcodever & 0xF) | (seq << 4);\n\tbuf[1] = opcode;\n\tif (cmd && size)\n\t\t_rtw_memcpy(buf + 2, cmd, size);\n\n\tGLBtcBtMpRptWait = _TRUE;\n\tGLBtcBtMpRptWiFiOK = _FALSE;\n\tGLBtcBtMpRptBTOK = _FALSE;\n\tGLBtcBtMpRptStatus = 0;\n\tpadapter = pBtCoexist->Adapter;\n\t_set_timer(&GLBtcBtMpOperTimer, BTC_MPOPER_TIMEOUT);\n\tif (rtw_hal_fill_h2c_cmd(padapter, H2C_BT_MP_OPER, buflen, buf) == _FAIL) {\n\t\t_cancel_timer_ex(&GLBtcBtMpOperTimer);\n\t\tret = BT_STATUS_H2C_FAIL;\n\t\tgoto exit;\n\t}\n\n\t_rtw_down_sema(&GLBtcBtMpRptSema);\n\t/* GLBtcBtMpRptWait should be _FALSE here*/\n\n\tif (GLBtcBtMpRptWiFiOK == _FALSE) {\n\t\tRTW_ERR(\"%s: Didn't get H2C Rsp Event!\\n\", __FUNCTION__);\n\t\tret = BT_STATUS_H2C_TIMTOUT;\n\t\tgoto exit;\n\t}\n\tif (GLBtcBtMpRptBTOK == _FALSE) {\n\t\tRTW_DBG(\"%s: Didn't get BT response!\\n\", __FUNCTION__);\n\t\tret = BT_STATUS_H2C_BT_NO_RSP;\n\t\tgoto exit;\n\t}\n\n\tif (seq != GLBtcBtMpRptSeq) {\n\t\tRTW_ERR(\"%s: Sequence number not match!(%d!=%d)!\\n\",\n\t\t\t __FUNCTION__, seq, GLBtcBtMpRptSeq);\n\t\tret = BT_STATUS_C2H_REQNUM_MISMATCH;\n\t\tgoto exit;\n\t}\n\n\tswitch (GLBtcBtMpRptStatus) {\n\t/* Examine the status reported from C2H */\n\tcase BT_STATUS_OK:\n\t\tret = BT_STATUS_BT_OP_SUCCESS;\n\t\tRTW_DBG(\"%s: C2H status = BT_STATUS_BT_OP_SUCCESS\\n\", __FUNCTION__);\n\t\tbreak;\n\tcase BT_STATUS_VERSION_MISMATCH:\n\t\tret = BT_STATUS_OPCODE_L_VERSION_MISMATCH;\n\t\tRTW_DBG(\"%s: C2H status = BT_STATUS_OPCODE_L_VERSION_MISMATCH\\n\", __FUNCTION__);\n\t\tbreak;\n\tcase BT_STATUS_UNKNOWN_OPCODE:\n\t\tret = BT_STATUS_UNKNOWN_OPCODE_L;\n\t\tRTW_DBG(\"%s: C2H status = MP_BT_STATUS_UNKNOWN_OPCODE_L\\n\", __FUNCTION__);\n\t\tbreak;\n\tcase BT_STATUS_ERROR_PARAMETER:\n\t\tret = BT_STATUS_PARAMETER_FORMAT_ERROR_L;\n\t\tRTW_DBG(\"%s: C2H status = MP_BT_STATUS_PARAMETER_FORMAT_ERROR_L\\n\", __FUNCTION__);\n\t\tbreak;\n\tdefault:\n\t\tret = BT_STATUS_UNKNOWN_STATUS_L;\n\t\tRTW_DBG(\"%s: C2H status = MP_BT_STATUS_UNKNOWN_STATUS_L\\n\", __FUNCTION__);\n\t\tbreak;\n\t}\n\nexit:\n\treturn ret;\n}\n\nu32 halbtcoutsrc_GetBtPatchVer(PBTC_COEXIST pBtCoexist)\n{\n\tif (pBtCoexist->bt_info.get_bt_fw_ver_cnt <= 5) {\n\t\tif (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {\n\t\t\t_irqL irqL;\n\t\t\tu8 ret;\n\n\t\t\t_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t\t\tret = _btmpoper_cmd(pBtCoexist, BT_OP_GET_BT_VERSION, 0, NULL, 0);\n\t\t\tif (BT_STATUS_BT_OP_SUCCESS == ret) {\n\t\t\t\tpBtCoexist->bt_info.bt_real_fw_ver = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);\n\t\t\t\tpBtCoexist->bt_info.get_bt_fw_ver_cnt++;\n\t\t\t}\n\n\t\t\t_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\t\t} else {\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\t\t\tu8 dataLen = 2;\n\t\t\tu8 buf[4] = {0};\n\n\t\t\tbuf[0] = 0x0;\t/* OP_Code */\n\t\t\tbuf[1] = 0x0;\t/* OP_Code_Length */\n\t\t\tBT_SendEventExtBtCoexControl(pBtCoexist->Adapter, _FALSE, dataLen, &buf[0]);\n#endif /* !CONFIG_BT_COEXIST_SOCKET_TRX */\n\t\t}\n\t}\n\n\treturn pBtCoexist->bt_info.bt_real_fw_ver;\n}\n\ns32 halbtcoutsrc_GetWifiRssi(PADAPTER padapter)\n{\n\treturn rtw_dm_get_min_rssi(padapter);\n}\n\nu32 halbtcoutsrc_GetBtCoexSupportedFeature(void *pBtcContext)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tu32 ret = BT_STATUS_BT_OP_SUCCESS;\n\tu32 data = 0;\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\n\tif (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {\n\t\tu8 buf[3] = {0};\n\t\t_irqL irqL;\n\t\tu8 op_code;\n\t\tu8 status;\n\n\t\t_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t\top_code = BT_OP_GET_BT_COEX_SUPPORTED_FEATURE;\n\t\tstatus = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);\n\t\tif (status == BT_STATUS_BT_OP_SUCCESS)\n\t\t\tdata = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);\n\t\telse\n\t\t\tret = SET_BT_MP_OPER_RET(op_code, status);\n\n\t\t_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t} else\n\t\tret = BT_STATUS_NOT_IMPLEMENT;\n\n\treturn data;\n}\n\nu32 halbtcoutsrc_GetBtCoexSupportedVersion(void *pBtcContext)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tu32 ret = BT_STATUS_BT_OP_SUCCESS;\n\tu32 data = 0xFFFF;\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\n\tif (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {\n\t\tu8 buf[3] = {0};\n\t\t_irqL irqL;\n\t\tu8 op_code;\n\t\tu8 status;\n\n\t\t_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t\top_code = BT_OP_GET_BT_COEX_SUPPORTED_VERSION;\n\t\tstatus = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);\n\t\tif (status == BT_STATUS_BT_OP_SUCCESS)\n\t\t\tdata = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);\n\t\telse\n\t\t\tret = SET_BT_MP_OPER_RET(op_code, status);\n\n\t\t_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t} else\n\t\tret = BT_STATUS_NOT_IMPLEMENT;\n\n\treturn data;\n}\n\nu32 halbtcoutsrc_GetBtDeviceInfo(void *pBtcContext)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tu32 ret = BT_STATUS_BT_OP_SUCCESS;\n\tu32 btDeviceInfo = 0;\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\n\tif (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {\n\t\tu8 buf[3] = {0};\n\t\t_irqL irqL;\n\t\tu8 op_code;\n\t\tu8 status;\n\n\t\t_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t\top_code = BT_OP_GET_BT_DEVICE_INFO;\n\t\tstatus = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);\n\t\tif (status == BT_STATUS_BT_OP_SUCCESS)\n\t\t\tbtDeviceInfo = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);\n\t\telse\n\t\t\tret = SET_BT_MP_OPER_RET(op_code, status);\n\n\t\t_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t} else\n\t\tret = BT_STATUS_NOT_IMPLEMENT;\n\n\treturn btDeviceInfo;\n}\n\nu32 halbtcoutsrc_GetBtForbiddenSlotVal(void *pBtcContext)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tu32 ret = BT_STATUS_BT_OP_SUCCESS;\n\tu32 btForbiddenSlotVal = 0;\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\n\tif (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {\n\t\tu8 buf[3] = {0};\n\t\t_irqL irqL;\n\t\tu8 op_code;\n\t\tu8 status;\n\n\t\t_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t\top_code = BT_OP_GET_BT_FORBIDDEN_SLOT_VAL;\n\t\tstatus = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);\n\t\tif (status == BT_STATUS_BT_OP_SUCCESS)\n\t\t\tbtForbiddenSlotVal = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);\n\t\telse\n\t\t\tret = SET_BT_MP_OPER_RET(op_code, status);\n\n\t\t_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t} else\n\t\tret = BT_STATUS_NOT_IMPLEMENT;\n\n\treturn btForbiddenSlotVal;\n}\n\nstatic u8 halbtcoutsrc_GetWifiScanAPNum(PADAPTER padapter)\n{\n\tstruct mlme_priv *pmlmepriv;\n\tstruct mlme_ext_priv *pmlmeext;\n\tstatic u8 scan_AP_num = 0;\n\n\n\tpmlmepriv = &padapter->mlmepriv;\n\tpmlmeext = &padapter->mlmeextpriv;\n\n\tif (GLBtcWiFiInScanState == _FALSE) {\n\t\tif (pmlmepriv->num_of_scanned > 0xFF)\n\t\t\tscan_AP_num = 0xFF;\n\t\telse\n\t\t\tscan_AP_num = (u8)pmlmepriv->num_of_scanned;\n\t}\n\n\treturn scan_AP_num;\n}\n\nu32 halbtcoutsrc_GetPhydmVersion(void *pBtcContext)\n{\n\tstruct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;\n\tPADAPTER\t\tAdapter = pBtCoexist->Adapter;\n\n#ifdef CONFIG_RTL8192E\n\treturn RELEASE_VERSION_8192E;\n#endif\n\n#ifdef CONFIG_RTL8821A\n\treturn RELEASE_VERSION_8821A;\n#endif\n\n#ifdef CONFIG_RTL8723B\n\treturn RELEASE_VERSION_8723B;\n#endif\n\n#ifdef CONFIG_RTL8812A\n\treturn RELEASE_VERSION_8812A;\n#endif\n\n#ifdef CONFIG_RTL8703B\n\treturn RELEASE_VERSION_8703B;\n#endif\n\n#ifdef CONFIG_RTL8822B\n\treturn RELEASE_VERSION_8822B;\n#endif\n\n#ifdef CONFIG_RTL8723D\n\treturn RELEASE_VERSION_8723D;\n#endif\n\n#ifdef CONFIG_RTL8821C\n\treturn RELEASE_VERSION_8821C;\n#endif\n\n#ifdef CONFIG_RTL8192F\n\treturn RELEASE_VERSION_8192F;\n#endif\n\n#ifdef CONFIG_RTL8822C\n\treturn RELEASE_VERSION_8822C;\n#endif\n\n#ifdef CONFIG_RTL8814A\n\treturn RELEASE_VERSION_8814A;\n#endif\n\n#ifdef CONFIG_RTL8814B\n\treturn RELEASE_VERSION_8814B;\n#endif\n}\n\nu8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tPADAPTER padapter;\n\tPHAL_DATA_TYPE pHalData;\n\tstruct mlme_ext_priv *mlmeext;\n\tstruct btc_wifi_link_info *wifi_link_info;\n\tu8 bSoftApExist, bVwifiExist;\n\tu8 *pu8;\n\ts32 *pS4Tmp;\n\tu32 *pU4Tmp;\n\tu8 *pU1Tmp;\n\tu16 *pU2Tmp;\n\tu8 ret;\n\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn _FALSE;\n\n\tpadapter = pBtCoexist->Adapter;\n\tpHalData = GET_HAL_DATA(padapter);\n\tmlmeext = &padapter->mlmeextpriv;\n\tbSoftApExist = _FALSE;\n\tbVwifiExist = _FALSE;\n\tpu8 = (u8 *)pOutBuf;\n\tpS4Tmp = (s32 *)pOutBuf;\n\tpU4Tmp = (u32 *)pOutBuf;\n\tpU1Tmp = (u8 *)pOutBuf;\n\tpU2Tmp = (u16*)pOutBuf;\n\twifi_link_info = (struct btc_wifi_link_info *)pOutBuf;\n\tret = _TRUE;\n\n\tswitch (getType) {\n\tcase BTC_GET_BL_HS_OPERATION:\n\t\t*pu8 = _FALSE;\n\t\tret = _FALSE;\n\t\tbreak;\n\n\tcase BTC_GET_BL_HS_CONNECTING:\n\t\t*pu8 = _FALSE;\n\t\tret = _FALSE;\n\t\tbreak;\n\n\tcase BTC_GET_BL_WIFI_FW_READY:\n\t\t*pu8 = halbtcoutsrc_is_fw_ready(pBtCoexist);\n\t\tbreak;\n\n\tcase BTC_GET_BL_WIFI_CONNECTED:\n\t\t*pu8 = (rtw_mi_check_status(padapter, MI_LINKED)) ? _TRUE : _FALSE;\n\t\tbreak;\n\n\tcase BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED:\n\t\t*pu8 = halbtcoutsrc_IsDualBandConnected(padapter);\n\t\tbreak;\n\n\tcase BTC_GET_BL_WIFI_BUSY:\n\t\t*pu8 = halbtcoutsrc_IsWifiBusy(padapter);\n\t\tbreak;\n\n\tcase BTC_GET_BL_WIFI_SCAN:\n#if 0\n\t\t*pu8 = (rtw_mi_check_fwstate(padapter, WIFI_SITE_MONITOR)) ? _TRUE : _FALSE;\n#else\n\t\t/* Use the value of the new variable GLBtcWiFiInScanState to judge whether WiFi is in scan state or not, since the originally used flag\n\t\t\tWIFI_SITE_MONITOR in fwstate may not be cleared in time */\n\t\t*pu8 = GLBtcWiFiInScanState;\n#endif\n\t\tbreak;\n\n\tcase BTC_GET_BL_WIFI_LINK:\n\t\t*pu8 = (rtw_mi_check_status(padapter, MI_STA_LINKING)) ? _TRUE : _FALSE;\n\t\tbreak;\n\n\tcase BTC_GET_BL_WIFI_ROAM:\n\t\t*pu8 = (rtw_mi_check_status(padapter, MI_STA_LINKING)) ? _TRUE : _FALSE;\n\t\tbreak;\n\n\tcase BTC_GET_BL_WIFI_4_WAY_PROGRESS:\n\t\t*pu8 = _FALSE;\n\t\tbreak;\n\n\tcase BTC_GET_BL_WIFI_UNDER_5G:\n\t\t*pu8 = (pHalData->current_band_type == BAND_ON_5G) ? _TRUE : _FALSE;\n\t\tbreak;\n\n\tcase BTC_GET_BL_WIFI_AP_MODE_ENABLE:\n\t\t*pu8 = (rtw_mi_check_status(padapter, MI_AP_MODE)) ? _TRUE : _FALSE;\n\t\tbreak;\n\n\tcase BTC_GET_BL_WIFI_ENABLE_ENCRYPTION:\n\t\t*pu8 = padapter->securitypriv.dot11PrivacyAlgrthm == 0 ? _FALSE : _TRUE;\n\t\tbreak;\n\n\tcase BTC_GET_BL_WIFI_UNDER_B_MODE:\n\t\tif (mlmeext->cur_wireless_mode == WIRELESS_11B)\n\t\t\t*pu8 = _TRUE;\n\t\telse\n\t\t\t*pu8 = _FALSE;\n\t\tbreak;\n\n\tcase BTC_GET_BL_WIFI_IS_IN_MP_MODE:\n\t\tif (padapter->registrypriv.mp_mode == 0)\n\t\t\t*pu8 = _FALSE;\n\t\telse\n\t\t\t*pu8 = _TRUE;\n\t\tbreak;\n\n\tcase BTC_GET_BL_EXT_SWITCH:\n\t\t*pu8 = _FALSE;\n\t\tbreak;\n\tcase BTC_GET_BL_IS_ASUS_8723B:\n\t\t/* Always return FALSE in linux driver since this case is added only for windows driver */\n\t\t*pu8 = _FALSE;\n\t\tbreak;\n\n\tcase BTC_GET_BL_RF4CE_CONNECTED:\n#ifdef CONFIG_RF4CE_COEXIST\n\t\tif (hal_btcoex_get_rf4ce_link_state() == 0)\n\t\t\t*pu8 = FALSE;\n\t\telse\n\t\t\t*pu8 = TRUE;\n#else\n\t\t*pu8 = FALSE;\n#endif\n\t\tbreak;\n\n\tcase BTC_GET_BL_WIFI_LW_PWR_STATE:\n\t\t/* return false due to coex do not run during 32K */\n\t\t*pu8 = FALSE;\n\t\tbreak;\n\n\tcase BTC_GET_S4_WIFI_RSSI:\n\t\t*pS4Tmp = halbtcoutsrc_GetWifiRssi(padapter);\n\t\tbreak;\n\n\tcase BTC_GET_S4_HS_RSSI:\n\t\t*pS4Tmp = 0;\n\t\tret = _FALSE;\n\t\tbreak;\n\n\tcase BTC_GET_U4_WIFI_BW:\n\t\tif (IsLegacyOnly(mlmeext->cur_wireless_mode))\n\t\t\t*pU4Tmp = BTC_WIFI_BW_LEGACY;\n\t\telse {\n\t\t\tswitch (pHalData->current_channel_bw) {\n\t\t\tcase CHANNEL_WIDTH_20:\n\t\t\t\t*pU4Tmp = BTC_WIFI_BW_HT20;\n\t\t\t\tbreak;\n\t\t\tcase CHANNEL_WIDTH_40:\n\t\t\t\t*pU4Tmp = BTC_WIFI_BW_HT40;\n\t\t\t\tbreak;\n\t\t\tcase CHANNEL_WIDTH_80:\n\t\t\t\t*pU4Tmp = BTC_WIFI_BW_HT80;\n\t\t\t\tbreak;\n\t\t\tcase CHANNEL_WIDTH_160:\n\t\t\t\t*pU4Tmp = BTC_WIFI_BW_HT160;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tRTW_INFO(\"[BTCOEX] unknown bandwidth(%d)\\n\", pHalData->current_channel_bw);\n\t\t\t\t*pU4Tmp = BTC_WIFI_BW_HT40;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t}\n\t\tbreak;\n\n\tcase BTC_GET_U4_WIFI_TRAFFIC_DIRECTION: \n\tcase BTC_GET_U4_WIFI_TRAFFIC_DIR:\n\t\t{\n\t\t\tPRT_LINK_DETECT_T plinkinfo;\n\t\t\tplinkinfo = &padapter->mlmepriv.LinkDetectInfo;\n\n\t\t\tif (plinkinfo->NumTxOkInPeriod > plinkinfo->NumRxOkInPeriod)\n\t\t\t\t*pU4Tmp = BTC_WIFI_TRAFFIC_TX;\n\t\t\telse\n\t\t\t\t*pU4Tmp = BTC_WIFI_TRAFFIC_RX;\n\t\t}\n\t\tbreak;\n\n\tcase BTC_GET_U4_WIFI_FW_VER:\n\t\t*pU4Tmp = pHalData->firmware_version << 16;\n\t\t*pU4Tmp |= pHalData->firmware_sub_version;\n\t\tbreak;\n\n\tcase BTC_GET_U4_WIFI_PHY_VER:\n\t\t*pU4Tmp = halbtcoutsrc_GetPhydmVersion(pBtCoexist);\n\t\tbreak;\n\n\tcase BTC_GET_U4_WIFI_LINK_STATUS:\n\t\t*pU4Tmp = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist);\n\t\tbreak;\n\tcase BTC_GET_BL_WIFI_LINK_INFO:\n\t\t*wifi_link_info = halbtcoutsrc_getwifilinkinfo(pBtCoexist);\n\t\tbreak;\n\tcase BTC_GET_U4_BT_PATCH_VER:\n\t\t*pU4Tmp = halbtcoutsrc_GetBtPatchVer(pBtCoexist);\n\t\tbreak;\n\n\tcase BTC_GET_U4_VENDOR:\n\t\t*pU4Tmp = BTC_VENDOR_OTHER;\n\t\tbreak;\n\n\tcase BTC_GET_U4_SUPPORTED_VERSION:\n\t\t*pU4Tmp = halbtcoutsrc_GetBtCoexSupportedVersion(pBtCoexist);\n\t\tbreak;\n\tcase BTC_GET_U4_SUPPORTED_FEATURE:\n\t\t*pU4Tmp = halbtcoutsrc_GetBtCoexSupportedFeature(pBtCoexist);\n\t\tbreak;\n\n\tcase BTC_GET_U4_BT_DEVICE_INFO:\n\t\t*pU4Tmp = halbtcoutsrc_GetBtDeviceInfo(pBtCoexist);\n\t\tbreak;\n\n\tcase BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL:\n\t\t*pU4Tmp = halbtcoutsrc_GetBtForbiddenSlotVal(pBtCoexist);\n\t\tbreak;\n\n\tcase BTC_GET_U4_WIFI_IQK_TOTAL:\n\t\t*pU4Tmp = pHalData->odmpriv.n_iqk_cnt;\n\t\tbreak;\n\n\tcase BTC_GET_U4_WIFI_IQK_OK:\n\t\t*pU4Tmp = pHalData->odmpriv.n_iqk_ok_cnt;\n\t\tbreak;\n\n\tcase BTC_GET_U4_WIFI_IQK_FAIL:\n\t\t*pU4Tmp = pHalData->odmpriv.n_iqk_fail_cnt;\n\t\tbreak;\n\n\tcase BTC_GET_U1_WIFI_DOT11_CHNL:\n\t\t*pU1Tmp = padapter->mlmeextpriv.cur_channel;\n\t\tbreak;\n\n\tcase BTC_GET_U1_WIFI_CENTRAL_CHNL:\n\t\t*pU1Tmp = pHalData->current_channel;\n\t\tbreak;\n\n\tcase BTC_GET_U1_WIFI_HS_CHNL:\n\t\t*pU1Tmp = 0;\n\t\tret = _FALSE;\n\t\tbreak;\n\n\tcase BTC_GET_U1_WIFI_P2P_CHNL:\n#ifdef CONFIG_P2P\n\t\t{\n\t\t\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n\t\t\t\n\t\t\t*pU1Tmp = pwdinfo->operating_channel;\n\t\t}\n#else\n\t\t*pU1Tmp = 0;\n#endif\n\t\tbreak;\n\n\tcase BTC_GET_U1_MAC_PHY_MODE:\n\t\t/*\t\t\t*pU1Tmp = BTC_SMSP;\n\t\t *\t\t\t*pU1Tmp = BTC_DMSP;\n\t\t *\t\t\t*pU1Tmp = BTC_DMDP;\n\t\t *\t\t\t*pU1Tmp = BTC_MP_UNKNOWN; */\n\t\tbreak;\n\n\tcase BTC_GET_U1_AP_NUM:\n\t\t*pU1Tmp = halbtcoutsrc_GetWifiScanAPNum(padapter);\n\t\tbreak;\n\tcase BTC_GET_U1_ANT_TYPE:\n\t\tswitch (pHalData->bt_coexist.btAntisolation) {\n\t\tcase 0:\n\t\t\t*pU1Tmp = (u8)BTC_ANT_TYPE_0;\n\t\t\tpBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_0;\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\t*pU1Tmp = (u8)BTC_ANT_TYPE_1;\n\t\t\tpBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_1;\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\t*pU1Tmp = (u8)BTC_ANT_TYPE_2;\n\t\t\tpBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_2;\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\t*pU1Tmp = (u8)BTC_ANT_TYPE_3;\n\t\t\tpBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_3;\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\t*pU1Tmp = (u8)BTC_ANT_TYPE_4;\n\t\t\tpBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_4;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase BTC_GET_U1_IOT_PEER:\n\t\t*pU1Tmp = mlmeext->mlmext_info.assoc_AP_vendor;\n\t\tbreak;\n\n\t/* =======1Ant=========== */\n\tcase BTC_GET_U1_LPS_MODE:\n\t\t*pU1Tmp = padapter->dvobj->pwrctl_priv.pwr_mode;\n\t\tbreak;\n\n\tcase BTC_GET_U2_BEACON_PERIOD:\n\t\t*pU2Tmp = mlmeext->mlmext_info.bcn_interval;\n\t\tbreak;\n\n\tdefault:\n\t\tret = _FALSE;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nu16 halbtcoutsrc_LnaConstrainLvl(void *pBtcContext, u8 *lna_constrain_level)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tu16 ret = BT_STATUS_BT_OP_SUCCESS;\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\n\tif (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {\n\t\t_irqL irqL;\n\t\tu8 op_code;\n\n\t\t_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t\tret = _btmpoper_cmd(pBtCoexist, BT_OP_SET_BT_LANCONSTRAIN_LEVEL, 0, lna_constrain_level, 1);\n\n\t\t_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\t} else { \n\t\tret = BT_STATUS_NOT_IMPLEMENT;\n\t\tRTW_INFO(\"%s halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == FALSE\\n\", __func__);\n\t}\n\n\treturn ret;\n}\n\nu8 halbtcoutsrc_SetBtGoldenRxRange(void *pBtcContext, u8 profile, u8 range_shift)\n{\n\t/* wait for implementation if necessary */\n\n\treturn 0;\n}\n\nu8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tPADAPTER padapter;\n\tPHAL_DATA_TYPE pHalData;\n\tu8 *pu8;\n\tu8 *pU1Tmp;\n\tu16 *pU2Tmp;\n\tu32\t*pU4Tmp;\n\tu8 ret;\n\tu8 result = _TRUE;\n\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn _FALSE;\n\n\tpadapter = pBtCoexist->Adapter;\n\tpHalData = GET_HAL_DATA(padapter);\n\tpu8 = (u8 *)pInBuf;\n\tpU1Tmp = (u8 *)pInBuf;\n\tpU2Tmp = (u16*)pInBuf;\n\tpU4Tmp = (u32 *)pInBuf;\n\tret = _TRUE;\n\n\tswitch (setType) {\n\t/* set some u8 type variables. */\n\tcase BTC_SET_BL_BT_DISABLE:\n\t\tpBtCoexist->bt_info.bt_disabled = *pu8;\n\t\tbreak;\n\n\tcase BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE:\n\t\tpBtCoexist->bt_info.bt_enable_disable_change = *pu8;\n\t\tbreak;\n\n\tcase BTC_SET_BL_BT_TRAFFIC_BUSY:\n\t\tpBtCoexist->bt_info.bt_busy = *pu8;\n\t\tbreak;\n\n\tcase BTC_SET_BL_BT_LIMITED_DIG:\n\t\tpBtCoexist->bt_info.limited_dig = *pu8;\n\t\tbreak;\n\n\tcase BTC_SET_BL_FORCE_TO_ROAM:\n\t\tpBtCoexist->bt_info.force_to_roam = *pu8;\n\t\tbreak;\n\n\tcase BTC_SET_BL_TO_REJ_AP_AGG_PKT:\n\t\tpBtCoexist->bt_info.reject_agg_pkt = *pu8;\n\t\tbreak;\n\n\tcase BTC_SET_BL_BT_CTRL_AGG_SIZE:\n\t\tpBtCoexist->bt_info.bt_ctrl_agg_buf_size = *pu8;\n\t\tbreak;\n\n\tcase BTC_SET_BL_INC_SCAN_DEV_NUM:\n\t\tpBtCoexist->bt_info.increase_scan_dev_num = *pu8;\n\t\tbreak;\n\n\tcase BTC_SET_BL_BT_TX_RX_MASK:\n\t\tpBtCoexist->bt_info.bt_tx_rx_mask = *pu8;\n\t\tbreak;\n\n\tcase BTC_SET_BL_MIRACAST_PLUS_BT:\n\t\tpBtCoexist->bt_info.miracast_plus_bt = *pu8;\n\t\tbreak;\n\n\t/* set some u8 type variables. */\n\tcase BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON:\n\t\tpBtCoexist->bt_info.rssi_adjust_for_agc_table_on = *pU1Tmp;\n\t\tbreak;\n\n\tcase BTC_SET_U1_AGG_BUF_SIZE:\n\t\tpBtCoexist->bt_info.agg_buf_size = *pU1Tmp;\n\t\tbreak;\n\n\t/* the following are some action which will be triggered */\n\tcase BTC_SET_ACT_GET_BT_RSSI:\n#if 0\n\t\tBT_SendGetBtRssiEvent(padapter);\n#else\n\t\tret = _FALSE;\n#endif\n\t\tbreak;\n\n\tcase BTC_SET_ACT_AGGREGATE_CTRL:\n\t\thalbtcoutsrc_AggregationCheck(pBtCoexist);\n\t\tbreak;\n\n\t/* =======1Ant=========== */\n\t/* set some u8 type variables. */\n\tcase BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE:\n\t\tpBtCoexist->bt_info.rssi_adjust_for_1ant_coex_type = *pU1Tmp;\n\t\tbreak;\n\n\tcase BTC_SET_U1_LPS_VAL:\n\t\tpBtCoexist->bt_info.lps_val = *pU1Tmp;\n\t\tbreak;\n\n\tcase BTC_SET_U1_RPWM_VAL:\n\t\tpBtCoexist->bt_info.rpwm_val = *pU1Tmp;\n\t\tbreak;\n\n\t/* the following are some action which will be triggered */\n\tcase BTC_SET_ACT_LEAVE_LPS:\n\t\tresult = halbtcoutsrc_LeaveLps(pBtCoexist);\n\t\tbreak;\n\n\tcase BTC_SET_ACT_ENTER_LPS:\n\t\thalbtcoutsrc_EnterLps(pBtCoexist);\n\t\tbreak;\n\n\tcase BTC_SET_ACT_NORMAL_LPS:\n\t\thalbtcoutsrc_NormalLps(pBtCoexist);\n\t\tbreak;\n\n\tcase BTC_SET_ACT_PRE_NORMAL_LPS:\n\t\thalbtcoutsrc_Pre_NormalLps(pBtCoexist);\n\t\tbreak;\n\n\tcase BTC_SET_ACT_POST_NORMAL_LPS:\n\t\thalbtcoutsrc_Post_NormalLps(pBtCoexist);\n\t\tbreak;\n\n\tcase BTC_SET_ACT_DISABLE_LOW_POWER:\n\t\thalbtcoutsrc_DisableLowPower(pBtCoexist, *pu8);\n\t\tbreak;\n\n\tcase BTC_SET_ACT_UPDATE_RAMASK:\n\t\t/*\n\t\tpBtCoexist->bt_info.ra_mask = *pU4Tmp;\n\n\t\tif (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {\n\t\t\tstruct sta_info *psta;\n\t\t\tPWLAN_BSSID_EX cur_network;\n\n\t\t\tcur_network = &padapter->mlmeextpriv.mlmext_info.network;\n\t\t\tpsta = rtw_get_stainfo(&padapter->stapriv, cur_network->MacAddress);\n\t\t\trtw_hal_update_ra_mask(psta);\n\t\t}\n\t\t*/\n\t\tbreak;\n\n\tcase BTC_SET_ACT_SEND_MIMO_PS: {\n\t\tu8 newMimoPsMode = 3;\n\t\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n\t\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\t\t/* *pU1Tmp = 0 use SM_PS static type */\n\t\t/* *pU1Tmp = 1 disable SM_PS */\n\t\tif (*pU1Tmp == 0)\n\t\t\tnewMimoPsMode = WLAN_HT_CAP_SM_PS_STATIC;\n\t\telse if (*pU1Tmp == 1)\n\t\t\tnewMimoPsMode = WLAN_HT_CAP_SM_PS_DISABLED;\n\n\t\tif (check_fwstate(&padapter->mlmepriv , WIFI_ASOC_STATE) == _TRUE) {\n\t\t\t/* issue_action_SM_PS(padapter, get_my_bssid(&(pmlmeinfo->network)), newMimoPsMode); */\n\t\t\tissue_action_SM_PS_wait_ack(padapter , get_my_bssid(&(pmlmeinfo->network)) , newMimoPsMode, 3 , 1);\n\t\t}\n\t}\n\tbreak;\n\n\tcase BTC_SET_ACT_CTRL_BT_INFO:\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\t\t{\n\t\t\tu8 dataLen = *pU1Tmp;\n\t\t\tu8 tmpBuf[BTC_TMP_BUF_SHORT];\n\t\t\tif (dataLen)\n\t\t\t\t_rtw_memcpy(tmpBuf, pU1Tmp + 1, dataLen);\n\t\t\tBT_SendEventExtBtInfoControl(padapter, dataLen, &tmpBuf[0]);\n\t\t}\n#else /* !CONFIG_BT_COEXIST_SOCKET_TRX */\n\t\tret = _FALSE;\n#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */\n\t\tbreak;\n\n\tcase BTC_SET_ACT_CTRL_BT_COEX:\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\t\t{\n\t\t\tu8 dataLen = *pU1Tmp;\n\t\t\tu8 tmpBuf[BTC_TMP_BUF_SHORT];\n\t\t\tif (dataLen)\n\t\t\t\t_rtw_memcpy(tmpBuf, pU1Tmp + 1, dataLen);\n\t\t\tBT_SendEventExtBtCoexControl(padapter, _FALSE, dataLen, &tmpBuf[0]);\n\t\t}\n#else /* !CONFIG_BT_COEXIST_SOCKET_TRX */\n\t\tret = _FALSE;\n#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */\n\t\tbreak;\n\tcase BTC_SET_ACT_CTRL_8723B_ANT:\n#if 0\n\t\t{\n\t\t\tu8\tdataLen = *pU1Tmp;\n\t\t\tu8\ttmpBuf[BTC_TMP_BUF_SHORT];\n\t\t\tif (dataLen)\n\t\t\t\tPlatformMoveMemory(&tmpBuf[0], pU1Tmp + 1, dataLen);\n\t\t\tBT_Set8723bAnt(Adapter, dataLen, &tmpBuf[0]);\n\t\t}\n#else\n\t\tret = _FALSE;\n#endif\n\t\tbreak;\n\tcase BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL:\n\t\thalbtcoutsrc_LnaConstrainLvl(pBtCoexist, pu8);\n\t\tbreak;\n\tcase BTC_SET_BL_BT_GOLDEN_RX_RANGE:\n\t\thalbtcoutsrc_SetBtGoldenRxRange(pBtCoexist, (*pU2Tmp & 0xff00) >> 8, (*pU2Tmp & 0xff));\n\t\tbreak;\n\tcase BTC_SET_RESET_COEX_VAR:\n\t\t_rtw_memset(&pBtCoexist->coex_dm, 0x00, sizeof(pBtCoexist->coex_dm));\n\t\t_rtw_memset(&pBtCoexist->coex_sta, 0x00, sizeof(pBtCoexist->coex_sta));\n\n\t\tswitch(pBtCoexist->chip_type) {\n#ifdef CONFIG_RTL8822B\n\t\tcase BTC_CHIP_RTL8822B:\n\t\t\t_rtw_memset(&pBtCoexist->coex_dm_8822b_1ant, 0x00, sizeof(pBtCoexist->coex_dm_8822b_1ant));\n\t\t\t_rtw_memset(&pBtCoexist->coex_dm_8822b_2ant, 0x00, sizeof(pBtCoexist->coex_dm_8822b_2ant));\n\t\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8821C\n\t\tcase BTC_CHIP_RTL8821C:\n\t\t\t_rtw_memset(&pBtCoexist->coex_dm_8821c_1ant, 0x00, sizeof(pBtCoexist->coex_dm_8821c_1ant));\n\t\t\t_rtw_memset(&pBtCoexist->coex_dm_8821c_2ant, 0x00, sizeof(pBtCoexist->coex_dm_8821c_2ant));\n\t\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8723D\n\t\tcase BTC_CHIP_RTL8723D:\n\t\t\t_rtw_memset(&pBtCoexist->coex_dm_8723d_1ant, 0x00, sizeof(pBtCoexist->coex_dm_8723d_1ant));\n\t\t\t_rtw_memset(&pBtCoexist->coex_dm_8723d_2ant, 0x00, sizeof(pBtCoexist->coex_dm_8723d_2ant));\n\t\t\tbreak;\n#endif\n\t\t}\n\t\tbreak;\n\t/* ===================== */\n\tdefault:\n\t\tret = _FALSE;\n\t\tbreak;\n\t}\n\n\treturn result;\n}\n\nu8 halbtcoutsrc_UnderIps(PBTC_COEXIST pBtCoexist)\n{\n\tPADAPTER padapter;\n\tstruct pwrctrl_priv *pwrpriv;\n\tu8 bMacPwrCtrlOn;\n\n\tpadapter = pBtCoexist->Adapter;\n\tpwrpriv = &padapter->dvobj->pwrctl_priv;\n\tbMacPwrCtrlOn = _FALSE;\n\n\tif ((_TRUE == pwrpriv->bips_processing)\n\t    && (IPS_NONE != pwrpriv->ips_mode_req)\n\t   )\n\t\treturn _TRUE;\n\n\tif (rf_off == pwrpriv->rf_pwrstate)\n\t\treturn _TRUE;\n\n\trtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);\n\tif (_FALSE == bMacPwrCtrlOn)\n\t\treturn _TRUE;\n\n\treturn _FALSE;\n}\n\nu8 halbtcoutsrc_UnderLps(PBTC_COEXIST pBtCoexist)\n{\n\treturn GLBtcWiFiInLPS;\n}\n\nu8 halbtcoutsrc_Under32K(PBTC_COEXIST pBtCoexist)\n{\n\t/* todo: the method to check whether wifi is under 32K or not */\n\treturn _FALSE;\n}\n\nvoid halbtcoutsrc_DisplayCoexStatistics(PBTC_COEXIST pBtCoexist)\n{\n#if 0\n\tPADAPTER padapter = (PADAPTER)pBtCoexist->Adapter;\n\tPBT_MGNT pBtMgnt = &padapter->MgntInfo.BtInfo.BtMgnt;\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);\n\tu8 *cliBuf = pBtCoexist->cliBuf;\n\tu8\t\t\ti, j;\n\tu8\t\t\ttmpbuf[BTC_TMP_BUF_SHORT];\n\n\n\tif (gl_coex_offload.cnt_h2c_sent) {\n\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s\", \"============[Coex h2c notify]============\");\n\t\tCL_PRINTF(cliBuf);\n\n\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = H2c(%d)/Ack(%d)\", \"Coex h2c/c2h overall statistics\",\n\t\t\tgl_coex_offload.cnt_h2c_sent, gl_coex_offload.cnt_c2h_ack);\n\t\tfor (j = 0; j < COL_STATUS_MAX; j++) {\n\t\t\tif (gl_coex_offload.status[j]) {\n\t\t\t\tCL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, \", %s:%d\", coexH2cResultString[j], gl_coex_offload.status[j]);\n\t\t\t\tCL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, BTC_TMP_BUF_SHORT);\n\t\t\t}\n\t\t}\n\t\tCL_PRINTF(cliBuf);\n\t}\n\tfor (i = 0; i < COL_OP_WIFI_OPCODE_MAX; i++) {\n\t\tif (gl_coex_offload.h2c_record[i].count) {\n\t\t\t/*==========================================*/\n\t\t\t/*\tH2C result statistics*/\n\t\t\t/*==========================================*/\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = total:%d\", coexOpcodeString[i], gl_coex_offload.h2c_record[i].count);\n\t\t\tfor (j = 0; j < COL_STATUS_MAX; j++) {\n\t\t\t\tif (gl_coex_offload.h2c_record[i].status[j]) {\n\t\t\t\t\tCL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, \", %s:%d\", coexH2cResultString[j], gl_coex_offload.h2c_record[i].status[j]);\n\t\t\t\t\tCL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, BTC_TMP_BUF_SHORT);\n\t\t\t\t}\n\t\t\t}\n\t\t\tCL_PRINTF(cliBuf);\n\t\t\t/*==========================================*/\n\t\t\t/*\tH2C/C2H content*/\n\t\t\t/*==========================================*/\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = \", \"H2C / C2H content\");\n\t\t\tfor (j = 0; j < gl_coex_offload.h2c_record[i].h2c_len; j++) {\n\t\t\t\tCL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, \"%02x \", gl_coex_offload.h2c_record[i].h2c_buf[j]);\n\t\t\t\tCL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, 3);\n\t\t\t}\n\t\t\tif (gl_coex_offload.h2c_record[i].c2h_ack_len) {\n\t\t\t\tCL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, \"/ \", 2);\n\t\t\t\tfor (j = 0; j < gl_coex_offload.h2c_record[i].c2h_ack_len; j++) {\n\t\t\t\t\tCL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, \"%02x \", gl_coex_offload.h2c_record[i].c2h_ack_buf[j]);\n\t\t\t\t\tCL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, 3);\n\t\t\t\t}\n\t\t\t}\n\t\t\tCL_PRINTF(cliBuf);\n\t\t\t/*==========================================*/\n\t\t}\n\t}\n\n\tif (gl_coex_offload.cnt_c2h_ind) {\n\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s\", \"============[Coex c2h indication]============\");\n\t\tCL_PRINTF(cliBuf);\n\n\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = Ind(%d)\", \"C2H indication statistics\",\n\t\t\t   gl_coex_offload.cnt_c2h_ind);\n\t\tfor (j = 0; j < COL_STATUS_MAX; j++) {\n\t\t\tif (gl_coex_offload.c2h_ind_status[j]) {\n\t\t\t\tCL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, \", %s:%d\", coexH2cResultString[j], gl_coex_offload.c2h_ind_status[j]);\n\t\t\t\tCL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, BTC_TMP_BUF_SHORT);\n\t\t\t}\n\t\t}\n\t\tCL_PRINTF(cliBuf);\n\t}\n\tfor (i = 0; i < COL_IND_MAX; i++) {\n\t\tif (gl_coex_offload.c2h_ind_record[i].count) {\n\t\t\t/*==========================================*/\n\t\t\t/*\tH2C result statistics*/\n\t\t\t/*==========================================*/\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = total:%d\", coexIndTypeString[i], gl_coex_offload.c2h_ind_record[i].count);\n\t\t\tfor (j = 0; j < COL_STATUS_MAX; j++) {\n\t\t\t\tif (gl_coex_offload.c2h_ind_record[i].status[j]) {\n\t\t\t\t\tCL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, \", %s:%d\", coexH2cResultString[j], gl_coex_offload.c2h_ind_record[i].status[j]);\n\t\t\t\t\tCL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, BTC_TMP_BUF_SHORT);\n\t\t\t\t}\n\t\t\t}\n\t\t\tCL_PRINTF(cliBuf);\n\t\t\t/*==========================================*/\n\t\t\t/*\tcontent*/\n\t\t\t/*==========================================*/\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = \", \"C2H indication content\");\n\t\t\tfor (j = 0; j < gl_coex_offload.c2h_ind_record[i].ind_len; j++) {\n\t\t\t\tCL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, \"%02x \", gl_coex_offload.c2h_ind_record[i].ind_buf[j]);\n\t\t\t\tCL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, 3);\n\t\t\t}\n\t\t\tCL_PRINTF(cliBuf);\n\t\t\t/*==========================================*/\n\t\t}\n\t}\n\n\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s\", \"============[Statistics]============\");\n\tCL_PRINTF(cliBuf);\n\n#if (H2C_USE_IO_THREAD != 1)\n\tfor (i = 0; i < H2C_STATUS_MAX; i++) {\n\t\tif (pHalData->h2cStatistics[i]) {\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = [%s] = %d\", \"H2C statistics\", \\\n\t\t\t\t   h2cStaString[i], pHalData->h2cStatistics[i]);\n\t\t\tCL_PRINTF(cliBuf);\n\t\t}\n\t}\n#else\n\tfor (i = 0; i < IO_STATUS_MAX; i++) {\n\t\tif (Adapter->ioComStr.ioH2cStatistics[i]) {\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = [%s] = %d\", \"H2C statistics\", \\\n\t\t\t\tioStaString[i], Adapter->ioComStr.ioH2cStatistics[i]);\n\t\t\tCL_PRINTF(cliBuf);\n\t\t}\n\t}\n#endif\n#if 0\n\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = 0x%x\", \"lastHMEBoxNum\", \\\n\t\t   pHalData->LastHMEBoxNum);\n\tCL_PRINTF(cliBuf);\n\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = 0x%x / 0x%x\", \"LastOkH2c/FirstFailH2c(fwNotRead)\", \\\n\t\t   pHalData->lastSuccessH2cEid, pHalData->firstFailedH2cEid);\n\tCL_PRINTF(cliBuf);\n\n\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d/ %d/ %d/ %d\", \"c2hIsr/c2hIntr/clr1AF/noRdy/noBuf\", \\\n\t\tpHalData->InterruptLog.nIMR_C2HCMD, DBG_Var.c2hInterruptCnt, DBG_Var.c2hClrReadC2hCnt,\n\t\t   DBG_Var.c2hNotReadyCnt, DBG_Var.c2hBufAlloFailCnt);\n\tCL_PRINTF(cliBuf);\n\n\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d\", \"c2hPacket\", \\\n\t\t   DBG_Var.c2hPacketCnt);\n\tCL_PRINTF(cliBuf);\n#endif\n\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d\", \"Periodical/ DbgCtrl\", \\\n\t\tpBtCoexist->statistics.cntPeriodical, pBtCoexist->statistics.cntDbgCtrl);\n\tCL_PRINTF(cliBuf);\n\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d/ %d/ %d\", \"PowerOn/InitHw/InitCoexDm/RfStatus\", \\\n\t\tpBtCoexist->statistics.cntPowerOn, pBtCoexist->statistics.cntInitHwConfig, pBtCoexist->statistics.cntInitCoexDm,\n\t\t   pBtCoexist->statistics.cntRfStatusNotify);\n\tCL_PRINTF(cliBuf);\n\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d/ %d/ %d/ %d\", \"Ips/Lps/Scan/Connect/Mstatus\", \\\n\t\tpBtCoexist->statistics.cntIpsNotify, pBtCoexist->statistics.cntLpsNotify,\n\t\tpBtCoexist->statistics.cntScanNotify, pBtCoexist->statistics.cntConnectNotify,\n\t\t   pBtCoexist->statistics.cntMediaStatusNotify);\n\tCL_PRINTF(cliBuf);\n\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d/ %d\", \"Special pkt/Bt info/ bind\",\n\t\tpBtCoexist->statistics.cntSpecialPacketNotify, pBtCoexist->statistics.cntBtInfoNotify,\n\t\t   pBtCoexist->statistics.cntBind);\n\tCL_PRINTF(cliBuf);\n#endif\n\tPADAPTER\t\tpadapter = pBtCoexist->Adapter;\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(padapter);\n\tu8\t\t\t\t*cliBuf = pBtCoexist->cli_buf;\n\n\tif (pHalData->EEPROMBluetoothCoexist == 1) {\n\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s\", \"============[Coex Status]============\");\n\t\tCL_PRINTF(cliBuf);\n\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d \", \"IsBtDisabled\", rtw_btcoex_IsBtDisabled(padapter));\n\t\tCL_PRINTF(cliBuf);\n\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d \", \"IsBtControlLps\", rtw_btcoex_IsBtControlLps(padapter));\n\t\tCL_PRINTF(cliBuf);\n\t}\n}\n\nvoid halbtcoutsrc_DisplayBtLinkInfo(PBTC_COEXIST pBtCoexist)\n{\n#if 0\n\tPADAPTER padapter = (PADAPTER)pBtCoexist->Adapter;\n\tPBT_MGNT pBtMgnt = &padapter->MgntInfo.BtInfo.BtMgnt;\n\tu8 *cliBuf = pBtCoexist->cliBuf;\n\tu8 i;\n\n\n\tif (pBtCoexist->stack_info.profile_notified) {\n\t\tfor (i = 0; i < pBtMgnt->ExtConfig.NumberOfACL; i++) {\n\t\t\tif (pBtMgnt->ExtConfig.HCIExtensionVer >= 1) {\n\t\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %s/ %s\", \"Bt link type/spec/role\", \\\n\t\t\t\t\tBtProfileString[pBtMgnt->ExtConfig.aclLink[i].BTProfile],\n\t\t\t\t\tBtSpecString[pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec],\n\t\t\t\t\tBtLinkRoleString[pBtMgnt->ExtConfig.aclLink[i].linkRole]);\n\t\t\t\tCL_PRINTF(cliBuf);\n\t\t\t} else {\n\t\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %s\", \"Bt link type/spec\", \\\n\t\t\t\t\tBtProfileString[pBtMgnt->ExtConfig.aclLink[i].BTProfile],\n\t\t\t\t\tBtSpecString[pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec]);\n\t\t\t\tCL_PRINTF(cliBuf);\n\t\t\t}\n\t\t}\n\t}\n#endif\n}\n\nvoid halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist)\n{\n\tPADAPTER\tpadapter = pBtCoexist->Adapter;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tu8\t\t\t*cliBuf = pBtCoexist->cli_buf;\n\ts32\t\t\twifiRssi = 0, btHsRssi = 0;\n\tBOOLEAN\tbScan = _FALSE, bLink = _FALSE, bRoam = _FALSE, bWifiBusy = _FALSE, bWifiUnderBMode = _FALSE;\n\tu32\t\t\twifiBw = BTC_WIFI_BW_HT20, wifiTrafficDir = BTC_WIFI_TRAFFIC_TX, wifiFreq = BTC_FREQ_2_4G;\n\tu32\t\t\twifiLinkStatus = 0x0;\n\tBOOLEAN\tbBtHsOn = _FALSE, bLowPower = _FALSE;\n\tu8\t\t\twifiChnl = 0, wifiP2PChnl = 0, nScanAPNum = 0, FwPSState;\n\tu32\t\t\tiqk_cnt_total = 0, iqk_cnt_ok = 0, iqk_cnt_fail = 0;\n\tu16\t\t\twifiBcnInterval = 0;\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);\n\tstruct btc_wifi_link_info wifi_link_info;\n\n\twifi_link_info = halbtcoutsrc_getwifilinkinfo(pBtCoexist);\n\n\tswitch (wifi_link_info.link_mode) {\n\t\tcase BTC_LINK_NONE:\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %d/ %d/ %d\", \"WifiLinkMode/HotSpa/Noa/ClientJoin\",\n\t\t\t\t\t\"None\", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);\n\t\t\twifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;\n\t\t\tbreak;\n\t\tcase BTC_LINK_ONLY_GO:\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %d/ %d/ %d\", \"WifiLinkMode/HotSpa/Noa/ClientJoin\",\n\t\t\t\t\t\"ONLY_GO\", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);\n\t\t\twifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;\n\t\t\tbreak;\n\t\tcase BTC_LINK_ONLY_GC:\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %d/ %d/ %d\", \"WifiLinkMode/HotSpa/Noa/ClientJoin\",\n\t\t\t\t\t\"ONLY_GC\", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);\n\t\t\twifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;\n\t\t\tbreak;\n\t\tcase BTC_LINK_ONLY_STA:\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %d/ %d/ %d\", \"WifiLinkMode/HotSpa/Noa/ClientJoin\",\n\t\t\t\t\t\"ONLY_STA\", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);\n\t\t\twifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;\n\t\t\tbreak;\n\t\tcase BTC_LINK_ONLY_AP:\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %d/ %d/ %d\", \"WifiLinkMode/HotSpa/Noa/ClientJoin\",\n\t\t\t\t\t\"ONLY_AP\", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);\n\t\t\twifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;\n\t\t\tbreak;\n\t\tcase BTC_LINK_2G_MCC_GO_STA:\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %d/ %d/ %d\", \"WifiLinkMode/HotSpa/Noa/ClientJoin\",\n\t\t\t\t\t\"24G_MCC_GO_STA\", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);\n\t\t\twifiFreq = BTC_FREQ_2_4G;\n\t\t\tbreak;\n\t\tcase BTC_LINK_5G_MCC_GO_STA:\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %d/ %d/ %d\", \"WifiLinkMode/HotSpa/Noa/ClientJoin\",\n\t\t\t\t\t\"5G_MCC_GO_STA\", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);\n\t\t\twifiFreq = BTC_FREQ_5G;\n\t\t\tbreak;\n\t\tcase BTC_LINK_25G_MCC_GO_STA:\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %d/ %d/ %d\", \"WifiLinkMode/HotSpa/Noa/ClientJoin\",\n\t\t\t\t\t\"2BANDS_MCC_GO_STA\", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);\n\t\t\twifiFreq = BTC_FREQ_25G;\n\t\t\tbreak;\n\t\tcase BTC_LINK_2G_MCC_GC_STA:\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %d/ %d/ %d\", \"WifiLinkMode/HotSpa/Noa/ClientJoin\",\n\t\t\t\t\t\"24G_MCC_GC_STA\", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);\n\t\t\twifiFreq = BTC_FREQ_2_4G;\n\t\t\tbreak;\n\t\tcase BTC_LINK_5G_MCC_GC_STA:\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %d/ %d/ %d\", \"WifiLinkMode/HotSpa/Noa/ClientJoin\",\n\t\t\t\t\t\"5G_MCC_GC_STA\", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);\n\t\t\twifiFreq = BTC_FREQ_5G;\n\t\t\tbreak;\n\t\tcase BTC_LINK_25G_MCC_GC_STA:\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %d/ %d/ %d\", \"WifiLinkMode/HotSpa/Noa/ClientJoin\",\n\t\t\t\t\t\"2BANDS_MCC_GC_STA\", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);\n\t\t\twifiFreq = BTC_FREQ_25G;\n\t\t\tbreak;\n\t\tcase BTC_LINK_2G_SCC_GO_STA:\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %d/ %d/ %d\", \"WifiLinkMode/HotSpa/Noa/ClientJoin\",\n\t\t\t\t\t\"24G_SCC_GO_STA\", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);\n\t\t\twifiFreq = BTC_FREQ_2_4G;\n\t\t\tbreak;\n\t\tcase BTC_LINK_5G_SCC_GO_STA:\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %d/ %d/ %d\", \"WifiLinkMode/HotSpa/Noa/ClientJoin\",\n\t\t\t\t\t\"5G_SCC_GO_STA\", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);\n\t\t\twifiFreq = BTC_FREQ_5G;\n\t\t\tbreak;\n\t\tcase BTC_LINK_2G_SCC_GC_STA:\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %d/ %d/ %d\", \"WifiLinkMode/HotSpa/Noa/ClientJoin\",\n\t\t\t\t\t\"24G_SCC_GC_STA\", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);\n\t\t\twifiFreq = BTC_FREQ_2_4G;\n\t\t\tbreak;\n\t\tcase BTC_LINK_5G_SCC_GC_STA:\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %d/ %d/ %d\", \"WifiLinkMode/HotSpa/Noa/ClientJoin\",\n\t\t\t\t\t\"5G_SCC_GC_STA\", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);\n\t\t\twifiFreq = BTC_FREQ_5G;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s/ %d/ %d/ %d\", \"WifiLinkMode/HotSpa/Noa/ClientJoin\",\n\t\t\t\t\t\"UNKNOWN\", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);\n\t\t\twifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;\n\t\t\tbreak;\n\t}\n\n\tCL_PRINTF(cliBuf);\n\n\twifiLinkStatus = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist);\n\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d/ %d/ %d/ %d\", \"STA/vWifi/HS/p2pGo/p2pGc\",\n\t\t((wifiLinkStatus & WIFI_STA_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_AP_CONNECTED) ? 1 : 0),\n\t\t((wifiLinkStatus & WIFI_HS_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_P2P_GO_CONNECTED) ? 1 : 0),\n\t\t((wifiLinkStatus & WIFI_P2P_GC_CONNECTED) ? 1 : 0));\n\tCL_PRINTF(cliBuf);\n\n\tpBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);\n\tpBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);\n\tpBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);\n\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d/ %d \", \"Link/ Roam/ Scan\",\n\t\tbLink, bRoam, bScan);\n\tCL_PRINTF(cliBuf);\t\n\n\tpBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_TOTAL, &iqk_cnt_total);\n\tpBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_OK, &iqk_cnt_ok);\n\tpBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_FAIL, &iqk_cnt_fail);\n\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d/ %d/ %d %s %s\",\n\t\t\"IQK All/ OK/ Fail/AutoLoad/FWDL\", iqk_cnt_total, iqk_cnt_ok, iqk_cnt_fail,\n\t\t((halbtcoutsrc_is_autoload_fail(pBtCoexist) == _TRUE) ? \"fail\":\"ok\"), ((halbtcoutsrc_is_fw_ready(pBtCoexist) == _TRUE) ? \"ok\":\"fail\"));\n\tCL_PRINTF(cliBuf);\n\t\n\tif (wifiLinkStatus & WIFI_STA_CONNECTED) {\n\t\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s\", \"IOT Peer\", GLBtcIotPeerString[padapter->mlmeextpriv.mlmext_info.assoc_AP_vendor]);\n\t\tCL_PRINTF(cliBuf);\n\t}\n\n\tpBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);\n\tpBtCoexist->btc_get(pBtCoexist, BTC_GET_U2_BEACON_PERIOD, &wifiBcnInterval);\n\twifiChnl = wifi_link_info.sta_center_channel;\n\twifiP2PChnl = wifi_link_info.p2p_center_channel;\n\n\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %d dBm/ %d/ %d/ %d\", \"RSSI/ STA_Chnl/ P2P_Chnl/ BI\",\n\t\twifiRssi-100, wifiChnl, wifiP2PChnl, wifiBcnInterval);\n\tCL_PRINTF(cliBuf);\n\n\tpBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);\n\tpBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);\n\tpBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);\n\tpBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode);\n\tpBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_AP_NUM, &nScanAPNum);\n\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s / %s/ %s/ %d \", \"Band/ BW/ Traffic/ APCnt\",\n\t\tGLBtcWifiFreqString[wifiFreq], ((bWifiUnderBMode) ? \"11b\" : GLBtcWifiBwString[wifiBw]),\n\t\t((!bWifiBusy) ? \"idle\" : ((BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) ? \"uplink\" : \"downlink\")),\n\t\t   nScanAPNum);\n\tCL_PRINTF(cliBuf);\n\n\t/* power status */\n\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %s%s%s\", \"Power Status\", \\\n\t\t((halbtcoutsrc_UnderIps(pBtCoexist) == _TRUE) ? \"IPS ON\" : \"IPS OFF\"),\n\t\t((halbtcoutsrc_UnderLps(pBtCoexist) == _TRUE) ? \", LPS ON\" : \", LPS OFF\"),\n\t\t((halbtcoutsrc_Under32K(pBtCoexist) == _TRUE) ? \", 32k\" : \"\"));\n\tCL_PRINTF(cliBuf);\n\n\tCL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, \"\\r\\n %-35s = %02x %02x %02x %02x %02x %02x (0x%x/0x%x)\", \"Power mode cmd(lps/rpwm)\",\n\t\t   pBtCoexist->pwrModeVal[0], pBtCoexist->pwrModeVal[1],\n\t\t   pBtCoexist->pwrModeVal[2], pBtCoexist->pwrModeVal[3],\n\t\t   pBtCoexist->pwrModeVal[4], pBtCoexist->pwrModeVal[5],\n\t\t   pBtCoexist->bt_info.lps_val,\n\t\t   pBtCoexist->bt_info.rpwm_val);\n\tCL_PRINTF(cliBuf);\n}\n\nvoid halbtcoutsrc_DisplayDbgMsg(void *pBtcContext, u8 dispType)\n{\n\tPBTC_COEXIST pBtCoexist;\n\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\tswitch (dispType) {\n\tcase BTC_DBG_DISP_COEX_STATISTICS:\n\t\thalbtcoutsrc_DisplayCoexStatistics(pBtCoexist);\n\t\tbreak;\n\tcase BTC_DBG_DISP_BT_LINK_INFO:\n\t\thalbtcoutsrc_DisplayBtLinkInfo(pBtCoexist);\n\t\tbreak;\n\tcase BTC_DBG_DISP_WIFI_STATUS:\n\t\thalbtcoutsrc_DisplayWifiStatus(pBtCoexist);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n/* ************************************\n *\t\tIO related function\n * ************************************ */\nu8 halbtcoutsrc_Read1Byte(void *pBtcContext, u32 RegAddr)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tPADAPTER padapter;\n\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\tpadapter = pBtCoexist->Adapter;\n\n\treturn rtw_read8(padapter, RegAddr);\n}\n\nu16 halbtcoutsrc_Read2Byte(void *pBtcContext, u32 RegAddr)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tPADAPTER padapter;\n\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\tpadapter = pBtCoexist->Adapter;\n\n\treturn\trtw_read16(padapter, RegAddr);\n}\n\nu32 halbtcoutsrc_Read4Byte(void *pBtcContext, u32 RegAddr)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tPADAPTER padapter;\n\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\tpadapter = pBtCoexist->Adapter;\n\n\treturn\trtw_read32(padapter, RegAddr);\n}\n\nvoid halbtcoutsrc_Write1Byte(void *pBtcContext, u32 RegAddr, u8 Data)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tPADAPTER padapter;\n\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\tpadapter = pBtCoexist->Adapter;\n\n\trtw_write8(padapter, RegAddr, Data);\n}\n\nvoid halbtcoutsrc_BitMaskWrite1Byte(void *pBtcContext, u32 regAddr, u8 bitMask, u8 data1b)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tPADAPTER padapter;\n\tu8 originalValue, bitShift;\n\tu8 i;\n\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\tpadapter = pBtCoexist->Adapter;\n\toriginalValue = 0;\n\tbitShift = 0;\n\n\tif (bitMask != 0xff) {\n\t\toriginalValue = rtw_read8(padapter, regAddr);\n\n\t\tfor (i = 0; i <= 7; i++) {\n\t\t\tif ((bitMask >> i) & 0x1)\n\t\t\t\tbreak;\n\t\t}\n\t\tbitShift = i;\n\n\t\tdata1b = (originalValue & ~bitMask) | ((data1b << bitShift) & bitMask);\n\t}\n\n\trtw_write8(padapter, regAddr, data1b);\n}\n\nvoid halbtcoutsrc_Write2Byte(void *pBtcContext, u32 RegAddr, u16 Data)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tPADAPTER padapter;\n\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\tpadapter = pBtCoexist->Adapter;\n\n\trtw_write16(padapter, RegAddr, Data);\n}\n\nvoid halbtcoutsrc_Write4Byte(void *pBtcContext, u32 RegAddr, u32 Data)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tPADAPTER padapter;\n\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\tpadapter = pBtCoexist->Adapter;\n\n\trtw_write32(padapter, RegAddr, Data);\n}\n\nvoid halbtcoutsrc_WriteLocalReg1Byte(void *pBtcContext, u32 RegAddr, u8 Data)\n{\n\tPBTC_COEXIST\t\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\tPADAPTER\t\t\tAdapter = pBtCoexist->Adapter;\n\n\tif (BTC_INTF_SDIO == pBtCoexist->chip_interface)\n\t\trtw_write8(Adapter, SDIO_LOCAL_BASE | RegAddr, Data);\n\telse\n\t\trtw_write8(Adapter, RegAddr, Data);\n}\n\nu32 halbtcoutsrc_WaitLIndirectReg_Ready(void *pBtcContext)\n{\n\tPBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;\n\tu32 delay_count = 0, reg = 0;\n\n\tif (!btc->chip_para->lte_indirect_access)\n\t\treturn 0;\n\n\tswitch (btc->chip_para->indirect_type) {\n\tcase BTC_INDIRECT_1700:\n\t\treg = 0x1703;\n\t\tbreak;\n\tcase BTC_INDIRECT_7C0:\n\t\treg = 0x7C3;\n\t\tbreak;\n\tdefault:\n\t\treturn 0;\n\t}\n\n\t/* wait for ready bit before access */\n\twhile (1) {\n\t\tif ((halbtcoutsrc_Read1Byte(btc, reg) & BIT(5)) == 0) {\n\t\t\trtw_mdelay_os(10);\n\t\t\tif (++delay_count >= 10)\n\t\t\t\tbreak;\n\t\t} else {\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn delay_count;\n}\n\nu32 halbtcoutsrc_ReadLIndirectReg(void *pBtcContext, u16 reg_addr)\n{\n\tPBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;\n\tu32 val = 0;\n\n\tif (!btc->chip_para->lte_indirect_access)\n\t\treturn 0;\n\n\t/* wait for ready bit before access */\n\thalbtcoutsrc_WaitLIndirectReg_Ready(btc);\n\n\tswitch (btc->chip_para->indirect_type) {\n\tcase BTC_INDIRECT_1700:\n\t\thalbtcoutsrc_Write4Byte(btc, 0x1700, 0x800F0000 | reg_addr);\n\t\tval = halbtcoutsrc_Read4Byte(btc, 0x1708); /* get read data */\n\t\tbreak;\n\tcase BTC_INDIRECT_7C0:\n\t\thalbtcoutsrc_Write4Byte(btc, 0x7c0, 0x800F0000 | reg_addr);\n\t\tval = halbtcoutsrc_Read4Byte(btc, 0x7c8); /* get read data */\n\t\tbreak;\n\t}\n\n\treturn val;\n}\n\nvoid halbtcoutsrc_WriteLIndirectReg(void *pBtcContext, u16 reg_addr, u32 bit_mask, u32 reg_value)\n{\n\tPBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;\n\tu32 val, i = 0, bitpos = 0, reg0, reg1;\n\n\tif (!btc->chip_para->lte_indirect_access)\n\t\treturn;\n\n\tif (bit_mask == 0x0)\n\t\treturn;\n\n\tswitch (btc->chip_para->indirect_type) {\n\tcase BTC_INDIRECT_1700:\n\t\treg0 = 0x1700;\n\t\treg1 = 0x1704;\n\t\tbreak;\n\tcase BTC_INDIRECT_7C0:\n\t\treg0 = 0x7C0;\n\t\treg1 = 0x7C4;\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\n\tif (bit_mask == 0xffffffff) {\n\t\t/* wait for ready bit before access 0x1700 */\n\t\thalbtcoutsrc_WaitLIndirectReg_Ready(btc);\n\n\t\t/* put write data */\n\t\thalbtcoutsrc_Write4Byte(btc, reg1, reg_value);\n\t\thalbtcoutsrc_Write4Byte(btc, reg0, 0xc00F0000 | reg_addr);\n\t} else {\n\t\tfor (i = 0; i <= 31; i++) {\n\t\t\tif (((bit_mask >> i) & 0x1) == 0x1) {\n\t\t\t\tbitpos = i;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\t/* read back register value before write */\n\t\tval = halbtcoutsrc_ReadLIndirectReg(btc, reg_addr);\n\t\tval = (val & (~bit_mask)) | (reg_value << bitpos);\n\n\t\t/* wait for ready bit before access 0x1700 */\n\t\thalbtcoutsrc_WaitLIndirectReg_Ready(btc);\n\n\t\thalbtcoutsrc_Write4Byte(btc, reg1, val); /* put write data */\n\t\thalbtcoutsrc_Write4Byte(btc, reg0, 0xc00F0000 | reg_addr);\n\t}\n}\n\nvoid halbtcoutsrc_Read_scbd(void *pBtcContext, u16* score_board_val)\n{\n\tPBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\n\tif (!chip_para->scbd_support)\n\t\treturn;\n\n\t*score_board_val = (btc->btc_read_2byte(btc, 0xaa)) & 0x7fff;\n\tcoex_sta->score_board_BW = *score_board_val;\n}\n\nvoid halbtcoutsrc_Write_scbd(void *pBtcContext, u16 bitpos, u8 state)\n{\n\tPBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;\n\tstruct btc_coex_sta *coex_sta = &btc->coex_sta;\n\tconst struct btc_chip_para *chip_para = btc->chip_para;\n\tu16 val = 0x2;\n\tu8* btc_dbg_buf = &gl_btc_trace_buf[0];\n\n\tif (!chip_para->scbd_support)\n\t\treturn;\n\n\tval = val | coex_sta->score_board_WB;\n\n\t/* for 8822b, Scoreboard[10]: 0: CQDDR off, 1: CQDDR on\n\t * for 8822c, Scoreboard[10]: 0: CQDDR on, 1:CQDDR fix 2M\n\t */\n\tif (!btc->chip_para->new_scbd10_def && (bitpos & BTC_SCBD_FIX2M)) {\n\t\tif (state)\n\t\t\tval = val & (~BTC_SCBD_FIX2M);\n\t\telse\n\t\t\tval = val | BTC_SCBD_FIX2M;\n\t} else {\n\t\tif (state)\n\t\t\tval = val | bitpos;\n\t\telse\n\t\t\tval = val & (~bitpos);\n\t}\n\n\tif (val != coex_sta->score_board_WB) {\n\t\tcoex_sta->score_board_WB = val;\n\t\tval = val | 0x8000;\n\t\tbtc->btc_write_2byte(btc, 0xaa, val);\n\n\t\tBTC_SPRINTF(btc_dbg_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], write scoreboard 0x%x\\n\", val);\n\t} else {\n\t\tBTC_SPRINTF(btc_dbg_buf, BT_TMP_BUF_SIZE,\n\t\t\t    \"[BTCoex], %s: return for nochange\\n\", __func__);\n\t}\n\n\tBTC_TRACE(btc_dbg_buf);\n}\n\nvoid halbtcoutsrc_SetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask, u32 Data)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tPADAPTER padapter;\n\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\tpadapter = pBtCoexist->Adapter;\n\n\tphy_set_bb_reg(padapter, RegAddr, BitMask, Data);\n}\n\n\nu32 halbtcoutsrc_GetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tPADAPTER padapter;\n\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\tpadapter = pBtCoexist->Adapter;\n\n\treturn phy_query_bb_reg(padapter, RegAddr, BitMask);\n}\n\nvoid halbtcoutsrc_SetRfReg(void *pBtcContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tPADAPTER padapter;\n\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\tpadapter = pBtCoexist->Adapter;\n\n\tphy_set_rf_reg(padapter, eRFPath, RegAddr, BitMask, Data);\n}\n\nu32 halbtcoutsrc_GetRfReg(void *pBtcContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tPADAPTER padapter;\n\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\tpadapter = pBtCoexist->Adapter;\n\n\treturn phy_query_rf_reg(padapter, eRFPath, RegAddr, BitMask);\n}\n\nu16 halbtcoutsrc_SetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr, u32 Data)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tu16 ret = BT_STATUS_BT_OP_SUCCESS;\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\n\tif (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {\n\t\tu8 buf[3] = {0};\n\t\t_irqL irqL;\n\t\tu8 op_code;\n\t\tu8 status;\n\n\t\t_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t\tData = cpu_to_le32(Data);\n\t\top_code = BT_OP_WRITE_REG_VALUE;\n\t\tstatus = _btmpoper_cmd(pBtCoexist, op_code, 0, (u8 *)&Data, 3);\n\t\tif (status != BT_STATUS_BT_OP_SUCCESS)\n\t\t\tret = SET_BT_MP_OPER_RET(op_code, status);\n\t\telse {\n\t\t\tbuf[0] = RegType;\n\t\t\t*(u16 *)(buf + 1) = cpu_to_le16((u16)RegAddr);\n\t\t\top_code = BT_OP_WRITE_REG_ADDR;\n\t\t\tstatus = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 3);\n\t\t\tif (status != BT_STATUS_BT_OP_SUCCESS)\n\t\t\t\tret = SET_BT_MP_OPER_RET(op_code, status);\n\t\t}\n\n\t\t_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\t} else\n\t\tret = BT_STATUS_NOT_IMPLEMENT;\n\n\treturn ret;\n}\n\nu8 halbtcoutsrc_SetBtAntDetection(void *pBtcContext, u8 txTime, u8 btChnl)\n{\n\t/* Always return _FALSE since we don't implement this yet */\n#if 0\n\tPBTC_COEXIST\t\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\tPADAPTER\t\t\tAdapter = pBtCoexist->Adapter;\n\tu8\t\t\t\tbtCanTx = 0;\n\tBOOLEAN\t\t\tbStatus = FALSE;\n\n\tbStatus = NDBG_SetBtAntDetection(Adapter, txTime, btChnl, &btCanTx);\n\tif (bStatus && btCanTx)\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n#else\n\treturn _FALSE;\n#endif\n}\n\nBOOLEAN\nhalbtcoutsrc_SetBtTRXMASK(\n\t\tvoid\t\t\t*pBtcContext,\n\t\tu8\t\t\tbt_trx_mask\n\t)\n{\n\t/* Always return _FALSE since we don't implement this yet */\n#if 0\n\tstruct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;\n\tPADAPTER\t\t\tAdapter = pBtCoexist->Adapter;\n\tBOOLEAN\t\t\t\tbStatus = FALSE;\n\tu8\t\t\t\tbtCanTx = 0;\n\n\tif (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter) || IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)\n\t\t\t|| IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\n\tif (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter))\n\t\tbStatus = NDBG_SetBtTRXMASK(Adapter, 1, bt_trx_mask, &btCanTx);\n\telse\n\t\tbStatus = NDBG_SetBtTRXMASK(Adapter, 2, bt_trx_mask, &btCanTx);\n\t}\n\n\t\n\tif (bStatus)\n\t\treturn TRUE;\n\telse\n\t\treturn FALSE;\n#else\n\treturn _FALSE;\n#endif\n}\n\nu16 halbtcoutsrc_GetBtReg_with_status(void *pBtcContext, u8 RegType, u32 RegAddr, u32 *data)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tu16 ret = BT_STATUS_BT_OP_SUCCESS;\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\n\tif (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {\n\t\tu8 buf[3] = {0};\n\t\t_irqL irqL;\n\t\tu8 op_code;\n\t\tu8 status;\n\n\t\tbuf[0] = RegType;\n\t\t*(u16 *)(buf + 1) = cpu_to_le16((u16)RegAddr);\n\n\t\t_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t\top_code = BT_OP_READ_REG;\n\t\tstatus = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 3);\n\t\tif (status == BT_STATUS_BT_OP_SUCCESS)\n\t\t\t*data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);\n\t\telse\n\t\t\tret = SET_BT_MP_OPER_RET(op_code, status);\n\n\t\t_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t} else\n\t\tret = BT_STATUS_NOT_IMPLEMENT;\n\n\treturn ret;\n}\n\nu32 halbtcoutsrc_GetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr)\n{\n\tu32 regVal;\n\t\n\treturn (BT_STATUS_BT_OP_SUCCESS == halbtcoutsrc_GetBtReg_with_status(pBtcContext, RegType, RegAddr, &regVal)) ? regVal : 0xffffffff;\n}\n\nu16 halbtcoutsrc_setbttestmode(void *pBtcContext, u8 Type)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tu16 ret = BT_STATUS_BT_OP_SUCCESS;\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\n\tif (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {\n\t\t_irqL irqL;\n\t\tu8 op_code;\n\t\tu8 status;\n\n\t\t_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t\tType = cpu_to_le32(Type);\n\t\top_code = BT_OP_SET_BT_TEST_MODE_VAL;\n\t\tstatus = _btmpoper_cmd(pBtCoexist, op_code, 0, (u8 *)&Type, 3);\n\t\tif (status != BT_STATUS_BT_OP_SUCCESS)\n\t\t\tret = SET_BT_MP_OPER_RET(op_code, status);\n\n\t\t_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\t} else\n\t\tret = BT_STATUS_NOT_IMPLEMENT;\n\n\treturn ret;\n\n}\n\n\nvoid halbtcoutsrc_FillH2cCmd(void *pBtcContext, u8 elementId, u32 cmdLen, u8 *pCmdBuffer)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tPADAPTER padapter;\n\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\tpadapter = pBtCoexist->Adapter;\n\n\trtw_hal_fill_h2c_cmd(padapter, elementId, cmdLen, pCmdBuffer);\n}\n\nstatic void halbtcoutsrc_coex_offload_init(void)\n{\n\tu8\ti;\n\n\tgl_coex_offload.h2c_req_num = 0;\n\tgl_coex_offload.cnt_h2c_sent = 0;\n\tgl_coex_offload.cnt_c2h_ack = 0;\n\tgl_coex_offload.cnt_c2h_ind = 0;\n\n\tfor (i = 0; i < COL_MAX_H2C_REQ_NUM; i++)\n\t\tinit_completion(&gl_coex_offload.c2h_event[i]);\n}\n\nstatic COL_H2C_STATUS halbtcoutsrc_send_h2c(PADAPTER Adapter, PCOL_H2C pcol_h2c, u16 h2c_cmd_len)\n{\n\tCOL_H2C_STATUS\t\th2c_status = COL_STATUS_C2H_OK;\n\tu8\t\t\t\ti;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0))\n\treinit_completion(&gl_coex_offload.c2h_event[pcol_h2c->req_num]);\t\t/* set event to un signaled state */\n#else\n\tINIT_COMPLETION(gl_coex_offload.c2h_event[pcol_h2c->req_num]);\n#endif\n\n\tif (TRUE) {\n#if 0\t/*(USE_HAL_MAC_API == 1) */\n\t\tif (RT_STATUS_SUCCESS == HAL_MAC_Send_BT_COEX(&GET_HAL_MAC_INFO(Adapter), (u8 *)(pcol_h2c), (u32)h2c_cmd_len, 1)) {\n\t\t\tif (!wait_for_completion_timeout(&gl_coex_offload.c2h_event[pcol_h2c->req_num], 20)) {\n\t\t\t\th2c_status = COL_STATUS_H2C_TIMTOUT;\n\t\t\t}\n\t\t} else {\n\t\t\th2c_status = COL_STATUS_H2C_HALMAC_FAIL;\n\t\t}\n#endif\n\t}\n\n\treturn h2c_status;\n}\n\nstatic COL_H2C_STATUS halbtcoutsrc_check_c2h_ack(PADAPTER Adapter, PCOL_SINGLE_H2C_RECORD pH2cRecord)\n{\n\tCOL_H2C_STATUS\tc2h_status = COL_STATUS_C2H_OK;\n\tPCOL_H2C\t\tp_h2c_cmd = (PCOL_H2C)&pH2cRecord->h2c_buf[0];\n\tu8\t\t\treq_num = p_h2c_cmd->req_num;\n\tPCOL_C2H_ACK\tp_c2h_ack = (PCOL_C2H_ACK)&gl_coex_offload.c2h_ack_buf[req_num];\n\n\n\tif ((COL_C2H_ACK_HDR_LEN + p_c2h_ack->ret_len) > gl_coex_offload.c2h_ack_len[req_num]) {\n\t\tc2h_status = COL_STATUS_COEX_DATA_OVERFLOW;\n\t\treturn c2h_status;\n\t}\n\t/* else */\n\t{\n\t\t_rtw_memmove(&pH2cRecord->c2h_ack_buf[0], &gl_coex_offload.c2h_ack_buf[req_num], gl_coex_offload.c2h_ack_len[req_num]);\n\t\tpH2cRecord->c2h_ack_len = gl_coex_offload.c2h_ack_len[req_num];\n\t}\n\n\n\tif (p_c2h_ack->req_num != p_h2c_cmd->req_num) {\n\t\tc2h_status = COL_STATUS_C2H_REQ_NUM_MISMATCH;\n\t} else if (p_c2h_ack->opcode_ver != p_h2c_cmd->opcode_ver) {\n\t\tc2h_status = COL_STATUS_C2H_OPCODE_VER_MISMATCH;\n\t} else {\n\t\tc2h_status = p_c2h_ack->status;\n\t}\n\n\treturn c2h_status;\n}\n\nCOL_H2C_STATUS halbtcoutsrc_CoexH2cProcess(void *pBtCoexist,\n\t\tu8 opcode, u8 opcode_ver, u8 *ph2c_par, u8 h2c_par_len)\n{\n\tPADAPTER\t\t\tAdapter = ((struct btc_coexist *)pBtCoexist)->Adapter;\n\tu8\t\t\t\tH2C_Parameter[BTC_TMP_BUF_SHORT] = {0};\n\tPCOL_H2C\t\t\tpcol_h2c = (PCOL_H2C)&H2C_Parameter[0];\n\tu16\t\t\t\tparaLen = 0;\n\tCOL_H2C_STATUS\t\th2c_status = COL_STATUS_C2H_OK, c2h_status = COL_STATUS_C2H_OK;\n\tCOL_H2C_STATUS\t\tret_status = COL_STATUS_C2H_OK;\n\tu16\t\t\t\ti, col_h2c_len = 0;\n\n\tpcol_h2c->opcode = opcode;\n\tpcol_h2c->opcode_ver = opcode_ver;\n\tpcol_h2c->req_num = gl_coex_offload.h2c_req_num;\n\tgl_coex_offload.h2c_req_num++;\n\tgl_coex_offload.h2c_req_num %= 16;\n\n\t_rtw_memmove(&pcol_h2c->buf[0], ph2c_par, h2c_par_len);\n\n\n\tcol_h2c_len = h2c_par_len + 2;\t/* 2=sizeof(OPCode, OPCode_version and  Request number) */\n\tBT_PrintData(Adapter, \"[COL], H2C cmd: \", col_h2c_len, H2C_Parameter);\n\n\tgl_coex_offload.cnt_h2c_sent++;\n\n\tgl_coex_offload.h2c_record[opcode].count++;\n\tgl_coex_offload.h2c_record[opcode].h2c_len = col_h2c_len;\n\t_rtw_memmove((void *)&gl_coex_offload.h2c_record[opcode].h2c_buf[0], (void *)pcol_h2c, col_h2c_len);\n\n\th2c_status = halbtcoutsrc_send_h2c(Adapter, pcol_h2c, col_h2c_len);\n\n\tgl_coex_offload.h2c_record[opcode].c2h_ack_len = 0;\n\n\tif (COL_STATUS_C2H_OK == h2c_status) {\n\t\t/* if reach here, it means H2C get the correct c2h response, */\n\t\tc2h_status = halbtcoutsrc_check_c2h_ack(Adapter, &gl_coex_offload.h2c_record[opcode]);\n\t\tret_status = c2h_status;\n\t} else {\n\t\t/* check h2c status error, return error status code to upper layer. */\n\t\tret_status = h2c_status;\n\t}\n\tgl_coex_offload.h2c_record[opcode].status[ret_status]++;\n\tgl_coex_offload.status[ret_status]++;\n\n\treturn ret_status;\n}\n\nu8 halbtcoutsrc_GetAntDetValFromBt(void *pBtcContext)\n{\n\t/* Always return 0 since we don't implement this yet */\n#if 0\n\tstruct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;\n\tPADAPTER\t\t\tAdapter = pBtCoexist->Adapter;\n\tu8\t\t\t\tAntDetVal = 0x0;\n\tu8\t\t\t\topcodeVer = 1;\n\tBOOLEAN\t\t\t\tstatus = false;\n\n\tstatus = NDBG_GetAntDetValFromBt(Adapter, opcodeVer, &AntDetVal);\n\n\tRT_TRACE(COMP_DBG, DBG_LOUD, (\"$$$ halbtcoutsrc_GetAntDetValFromBt(): status = %d, feature = %x\\n\", status, AntDetVal));\n\n\treturn AntDetVal;\n#else\n\treturn 0;\n#endif\n}\n\nu8 halbtcoutsrc_GetBleScanTypeFromBt(void *pBtcContext)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tu32 ret = BT_STATUS_BT_OP_SUCCESS;\n\tu8 data = 0;\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\n\tif (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {\n\t\tu8 buf[3] = {0};\n\t\t_irqL irqL;\n\t\tu8 op_code;\n\t\tu8 status;\n\n\n\t\t_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t\top_code = BT_OP_GET_BT_BLE_SCAN_TYPE;\n\t\tstatus = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);\n\t\tif (status == BT_STATUS_BT_OP_SUCCESS)\n\t\t\tdata = *(u8 *)GLBtcBtMpRptRsp;\n\t\telse\n\t\t\tret = SET_BT_MP_OPER_RET(op_code, status);\n\n\t\t_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t} else\n\t\tret = BT_STATUS_NOT_IMPLEMENT;\n\n\treturn data;\n}\n\nu32 halbtcoutsrc_GetBleScanParaFromBt(void *pBtcContext, u8 scanType)\n{\n\tPBTC_COEXIST pBtCoexist;\n\tu32 ret = BT_STATUS_BT_OP_SUCCESS;\n\tu32 data = 0;\n\n\tpBtCoexist = (PBTC_COEXIST)pBtcContext;\n\n\tif (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {\n\t\tu8 buf[3] = {0};\n\t\t_irqL irqL;\n\t\tu8 op_code;\n\t\tu8 status;\n\t\t\n\t\tbuf[0] = scanType;\n\n\t\t_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t\top_code = BT_OP_GET_BT_BLE_SCAN_PARA;\n\t\tstatus = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 1);\n\t\tif (status == BT_STATUS_BT_OP_SUCCESS)\n\t\t\tdata = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);\n\t\telse\n\t\t\tret = SET_BT_MP_OPER_RET(op_code, status);\n\n\t\t_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\t} else\n\t\tret = BT_STATUS_NOT_IMPLEMENT;\n\n\treturn data;\n}\n\nu8 halbtcoutsrc_GetBtAFHMapFromBt(void *pBtcContext, u8 mapType, u8 *afhMap)\n{\n\tstruct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;\n\tu8 buf[2] = {0};\n\t_irqL irqL;\n\tu8 op_code;\n\tu32 *AfhMapL = (u32 *)&(afhMap[0]);\n\tu32 *AfhMapM = (u32 *)&(afhMap[4]);\n\tu16 *AfhMapH = (u16 *)&(afhMap[8]);\n\tu8 status;\n\tu32 ret = BT_STATUS_BT_OP_SUCCESS;\n\n\tif (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _FALSE)\n\t\treturn _FALSE;\n\n\tbuf[0] = 0;\n\tbuf[1] = mapType;\n\n\t_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\top_code = BT_LO_OP_GET_AFH_MAP_L;\n\tstatus = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);\n\tif (status == BT_STATUS_BT_OP_SUCCESS)\n\t\t*AfhMapL = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);\n\telse {\n\t\tret = SET_BT_MP_OPER_RET(op_code, status);\n\t\tgoto exit;\n\t}\n\n\top_code = BT_LO_OP_GET_AFH_MAP_M;\n\tstatus = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);\n\tif (status == BT_STATUS_BT_OP_SUCCESS)\n\t\t*AfhMapM = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);\n\telse {\n\t\tret = SET_BT_MP_OPER_RET(op_code, status);\n\t\tgoto exit;\n\t}\n\n\top_code = BT_LO_OP_GET_AFH_MAP_H;\n\tstatus = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);\n\tif (status == BT_STATUS_BT_OP_SUCCESS)\n\t\t*AfhMapH = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);\n\telse {\n\t\tret = SET_BT_MP_OPER_RET(op_code, status);\n\t\tgoto exit;\n\t}\n\nexit:\n\n\t_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);\n\n\treturn (ret == BT_STATUS_BT_OP_SUCCESS) ? _TRUE : _FALSE;\n}\n\nu8 halbtcoutsrc_SetTimer(void *pBtcContext, u32 type, u32 val)\n{\n\tstruct btc_coexist *pBtCoexist=(struct btc_coexist *)pBtcContext;\n\n\tif (type >= BTC_TIMER_MAX)\n\t\treturn _FALSE;\n\n\tpBtCoexist->coex_sta.cnt_timer[type] = val;\n\n\tRTW_DBG(\"[BTC], Set Timer: type = %d, val = %d\\n\", type, val);\n\n\treturn _TRUE;\n}\n\nu32 halbtcoutsrc_SetAtomic (void *btc_ctx, u32 *target, u32 val)\n{\n\t*target = val;\n\treturn _SUCCESS;\n}\n\nvoid halbtcoutsrc_phydm_modify_AntDiv_HwSw(void *pBtcContext, u8 is_hw)\n{\n\t/* empty function since we don't need it */\n}\n\nvoid halbtcoutsrc_phydm_modify_RA_PCR_threshold(void *pBtcContext, u8 RA_offset_direction, u8 RA_threshold_offset)\n{\n\tstruct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;\n\n/* switch to #if 0 in case the phydm version does not provide the function */\n#if 1\n\tphydm_modify_RA_PCR_threshold(pBtCoexist->odm_priv, RA_offset_direction, RA_threshold_offset);\n#endif\n}\n\nu32 halbtcoutsrc_phydm_query_PHY_counter(void *pBtcContext, u8 info_type)\n{\n\tstruct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;\n\n/* switch to #if 0 in case the phydm version does not provide the function */\n#if 1\n\treturn phydm_cmn_info_query((struct dm_struct *)pBtCoexist->odm_priv, (enum phydm_info_query)info_type);\n#else\n\treturn 0;\n#endif\n}\n\nvoid halbtcoutsrc_reduce_wl_tx_power(void *pBtcContext, s8 tx_power)\n{\n\tstruct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA((PADAPTER)pBtCoexist->Adapter);\n\n\t/* The reduction of wl tx pwr should be processed inside the set tx pwr lvl function */\n\tif (IS_HARDWARE_TYPE_8822C(pBtCoexist->Adapter))\n\t\trtw_hal_set_tx_power_level(pBtCoexist->Adapter, pHalData->current_channel);\n}\n\n#if 0\nstatic void BT_CoexOffloadRecordErrC2hAck(PADAPTER\tAdapter)\n{\n\tPADAPTER\t\tpDefaultAdapter = GetDefaultAdapter(Adapter);\n\n\tif (pDefaultAdapter != Adapter)\n\t\treturn;\n\n\tif (!hal_btcoex_IsBtExist(Adapter))\n\t\treturn;\n\n\tgl_coex_offload.cnt_c2h_ack++;\n\n\tgl_coex_offload.status[COL_STATUS_INVALID_C2H_LEN]++;\n}\n\nstatic void BT_CoexOffloadC2hAckCheck(PADAPTER\tAdapter, u8 *tmpBuf, u8 length)\n{\n\tPADAPTER\t\tpDefaultAdapter = GetDefaultAdapter(Adapter);\n\tPCOL_C2H_ACK\tp_c2h_ack = NULL;\n\tu8\t\t\treq_num = 0xff;\n\n\tif (pDefaultAdapter != Adapter)\n\t\treturn;\n\n\tif (!hal_btcoex_IsBtExist(Adapter))\n\t\treturn;\n\n\tgl_coex_offload.cnt_c2h_ack++;\n\n\tif (length < COL_C2H_ACK_HDR_LEN) {\t\t/* c2h ack length must >= 3 (status, opcode_ver, req_num and ret_len) */\n\t\tgl_coex_offload.status[COL_STATUS_INVALID_C2H_LEN]++;\n\t} else {\n\t\tBT_PrintData(Adapter, \"[COL], c2h ack:\", length, tmpBuf);\n\n\t\tp_c2h_ack = (PCOL_C2H_ACK)tmpBuf;\n\t\treq_num = p_c2h_ack->req_num;\n\n\t\t_rtw_memmove(&gl_coex_offload.c2h_ack_buf[req_num][0], tmpBuf, length);\n\t\tgl_coex_offload.c2h_ack_len[req_num] = length;\n\n\t\tcomplete(&gl_coex_offload.c2h_event[req_num]);\n\t}\n}\n\nstatic void BT_CoexOffloadC2hIndCheck(PADAPTER Adapter, u8 *tmpBuf, u8 length)\n{\n\tPADAPTER\t\tpDefaultAdapter = GetDefaultAdapter(Adapter);\n\tPCOL_C2H_IND\tp_c2h_ind = NULL;\n\tu8\t\t\tind_type = 0, ind_version = 0, ind_length = 0;\n\n\tif (pDefaultAdapter != Adapter)\n\t\treturn;\n\n\tif (!hal_btcoex_IsBtExist(Adapter))\n\t\treturn;\n\n\tgl_coex_offload.cnt_c2h_ind++;\n\n\tif (length < COL_C2H_IND_HDR_LEN) {\t\t/* c2h indication length must >= 3 (type, version and length) */\n\t\tgl_coex_offload.c2h_ind_status[COL_STATUS_INVALID_C2H_LEN]++;\n\t} else {\n\t\tBT_PrintData(Adapter, \"[COL], c2h indication:\", length, tmpBuf);\n\n\t\tp_c2h_ind = (PCOL_C2H_IND)tmpBuf;\n\t\tind_type = p_c2h_ind->type;\n\t\tind_version = p_c2h_ind->version;\n\t\tind_length = p_c2h_ind->length;\n\n\t\t_rtw_memmove(&gl_coex_offload.c2h_ind_buf[0], tmpBuf, length);\n\t\tgl_coex_offload.c2h_ind_len = length;\n\n\t\t/* log */\n\t\tgl_coex_offload.c2h_ind_record[ind_type].count++;\n\t\tgl_coex_offload.c2h_ind_record[ind_type].status[COL_STATUS_C2H_OK]++;\n\t\t_rtw_memmove(&gl_coex_offload.c2h_ind_record[ind_type].ind_buf[0], tmpBuf, length);\n\t\tgl_coex_offload.c2h_ind_record[ind_type].ind_len = length;\n\n\t\tgl_coex_offload.c2h_ind_status[COL_STATUS_C2H_OK]++;\n\t\t/*TODO: need to check c2h indication length*/\n\t\t/* TODO: Notification */\n\t}\n}\n\nvoid BT_CoexOffloadC2hCheck(PADAPTER Adapter, u8 *Buffer, u8 Length)\n{\n#if 0 /*(USE_HAL_MAC_API == 1)*/\n\tu8\tc2hSubCmdId = 0, c2hAckLen = 0, h2cCmdId = 0, h2cSubCmdId = 0, c2hIndLen = 0;\n\n\tBT_PrintData(Adapter, \"[COL], c2h packet:\", Length - 2, Buffer + 2);\n\tc2hSubCmdId = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(Buffer);\n\n\tif (c2hSubCmdId == C2H_SUB_CMD_ID_H2C_ACK_HDR ||\n\t    c2hSubCmdId == C2H_SUB_CMD_ID_BT_COEX_INFO) {\n\t\tif (c2hSubCmdId == C2H_SUB_CMD_ID_H2C_ACK_HDR) {\n\t\t\t/* coex c2h ack */\n\t\t\th2cCmdId = (u8)H2C_ACK_HDR_GET_H2C_CMD_ID(Buffer);\n\t\t\th2cSubCmdId = (u8)H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(Buffer);\n\t\t\tif (h2cCmdId == 0xff && h2cSubCmdId == 0x60) {\n\t\t\t\tc2hAckLen = (u8)C2H_HDR_GET_LEN(Buffer);\n\t\t\t\tif (c2hAckLen >= 8)\n\t\t\t\t\tBT_CoexOffloadC2hAckCheck(Adapter, &Buffer[12], (u8)(c2hAckLen - 8));\n\t\t\t\telse\n\t\t\t\t\tBT_CoexOffloadRecordErrC2hAck(Adapter);\n\t\t\t}\n\t\t} else if (c2hSubCmdId == C2H_SUB_CMD_ID_BT_COEX_INFO) {\n\t\t\t/* coex c2h indication */\n\t\t\tc2hIndLen = (u8)C2H_HDR_GET_LEN(Buffer);\n\t\t\tBT_CoexOffloadC2hIndCheck(Adapter, &Buffer[4], (u8)c2hIndLen);\n\t\t}\n\t}\n#endif\n}\n#endif\n\n/* ************************************\n *\t\tExtern functions called by other module\n * ************************************ */\nu8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter)\n{\n\tPBTC_COEXIST\t\tpBtCoexist = &GLBtCoexist;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA((PADAPTER)padapter);\n\n\tif (pBtCoexist->bBinded)\n\t\treturn _FALSE;\n\telse\n\t\tpBtCoexist->bBinded = _TRUE;\n\n\tpBtCoexist->statistics.cnt_bind++;\n\n\tpBtCoexist->Adapter = padapter;\n\tpBtCoexist->odm_priv = (void *)&(pHalData->odmpriv);\n\n\tpBtCoexist->stack_info.profile_notified = _FALSE;\n\n\tpBtCoexist->bt_info.bt_ctrl_agg_buf_size = _FALSE;\n\tpBtCoexist->bt_info.agg_buf_size = 5;\n\n\tpBtCoexist->bt_info.increase_scan_dev_num = _FALSE;\n\tpBtCoexist->bt_info.miracast_plus_bt = _FALSE;\n\n\t/* for btc common architecture, inform chip type to coex. mechanism */\n\tif(IS_HARDWARE_TYPE_8822C(padapter)) {\n#ifdef CONFIG_RTL8822C\n\t\tpBtCoexist->chip_type = BTC_CHIP_RTL8822C;\n\t\tpBtCoexist->chip_para = &btc_chip_para_8822c;\n#endif\n\t}\n#ifdef CONFIG_RTL8192F\n\telse if (IS_HARDWARE_TYPE_8192F(padapter)) {\n\t\tpBtCoexist->chip_type = BTC_CHIP_RTL8725A;\n\t\tpBtCoexist->chip_para = &btc_chip_para_8725a;\n\t}\n#endif\n\telse {\n\t\tpBtCoexist->chip_type = BTC_CHIP_UNDEF;\n\t\tpBtCoexist->chip_para = NULL;\n\t}\n\n\treturn _TRUE;\n}\n\nvoid EXhalbtcoutsrc_AntInfoSetting(void *padapter)\n{\n\tPBTC_COEXIST\t\tpBtCoexist = &GLBtCoexist;\n\tu8\tantNum = 1, singleAntPath = 0;\n\n\tantNum = rtw_btcoex_get_pg_ant_num((PADAPTER)padapter);\n\tEXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_PG, antNum);\n\n\tif (antNum == 1) {\n\t\tsingleAntPath = rtw_btcoex_get_pg_single_ant_path((PADAPTER)padapter);\n\t\tEXhalbtcoutsrc_SetSingleAntPath(singleAntPath);\n\t}\n\n\tpBtCoexist->board_info.customerID = RT_CID_DEFAULT;\n\tpBtCoexist->board_info.customer_id = RT_CID_DEFAULT;\n\n\t/* set default antenna position to main  port */\n\tpBtCoexist->board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;\n\n\tpBtCoexist->board_info.btdm_ant_det_finish = _FALSE;\n\tpBtCoexist->board_info.btdm_ant_num_by_ant_det = 1;\n\n\tpBtCoexist->board_info.tfbga_package = rtw_btcoex_is_tfbga_package_type((PADAPTER)padapter);\n\n\tpBtCoexist->board_info.rfe_type = rtw_btcoex_get_pg_rfe_type((PADAPTER)padapter);\n\n\tpBtCoexist->board_info.ant_div_cfg = rtw_btcoex_get_ant_div_cfg((PADAPTER)padapter);\n\n\tpBtCoexist->board_info.ant_distance = 10;\n}\n\nu8 EXhalbtcoutsrc_InitlizeVariables(void *padapter)\n{\n\tPBTC_COEXIST pBtCoexist = &GLBtCoexist;\n\n\t/* pBtCoexist->statistics.cntBind++; */\n\n\thalbtcoutsrc_DbgInit();\n\n\thalbtcoutsrc_coex_offload_init();\n\n#ifdef CONFIG_PCI_HCI\n\tpBtCoexist->chip_interface = BTC_INTF_PCI;\n#elif defined(CONFIG_USB_HCI)\n\tpBtCoexist->chip_interface = BTC_INTF_USB;\n#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\tpBtCoexist->chip_interface = BTC_INTF_SDIO;\n#else\n\tpBtCoexist->chip_interface = BTC_INTF_UNKNOWN;\n#endif\n\n\tEXhalbtcoutsrc_BindBtCoexWithAdapter(padapter);\n\n\tpBtCoexist->btc_read_1byte = halbtcoutsrc_Read1Byte;\n\tpBtCoexist->btc_write_1byte = halbtcoutsrc_Write1Byte;\n\tpBtCoexist->btc_write_1byte_bitmask = halbtcoutsrc_BitMaskWrite1Byte;\n\tpBtCoexist->btc_read_2byte = halbtcoutsrc_Read2Byte;\n\tpBtCoexist->btc_write_2byte = halbtcoutsrc_Write2Byte;\n\tpBtCoexist->btc_read_4byte = halbtcoutsrc_Read4Byte;\n\tpBtCoexist->btc_write_4byte = halbtcoutsrc_Write4Byte;\n\tpBtCoexist->btc_write_local_reg_1byte = halbtcoutsrc_WriteLocalReg1Byte;\n\n\tpBtCoexist->btc_read_linderct = halbtcoutsrc_ReadLIndirectReg;\n\tpBtCoexist->btc_write_linderct = halbtcoutsrc_WriteLIndirectReg;\n\n\tpBtCoexist->btc_read_scbd = halbtcoutsrc_Read_scbd;\n\tpBtCoexist->btc_write_scbd = halbtcoutsrc_Write_scbd;\n\n\tpBtCoexist->btc_set_bb_reg = halbtcoutsrc_SetBbReg;\n\tpBtCoexist->btc_get_bb_reg = halbtcoutsrc_GetBbReg;\n\n\tpBtCoexist->btc_set_rf_reg = halbtcoutsrc_SetRfReg;\n\tpBtCoexist->btc_get_rf_reg = halbtcoutsrc_GetRfReg;\n\n\tpBtCoexist->btc_fill_h2c = halbtcoutsrc_FillH2cCmd;\n\tpBtCoexist->btc_disp_dbg_msg = halbtcoutsrc_DisplayDbgMsg;\n\n\tpBtCoexist->btc_get = halbtcoutsrc_Get;\n\tpBtCoexist->btc_set = halbtcoutsrc_Set;\n\tpBtCoexist->btc_get_bt_reg = halbtcoutsrc_GetBtReg;\n\tpBtCoexist->btc_set_bt_reg = halbtcoutsrc_SetBtReg;\n\tpBtCoexist->btc_set_bt_ant_detection = halbtcoutsrc_SetBtAntDetection;\n\tpBtCoexist->btc_set_bt_trx_mask = halbtcoutsrc_SetBtTRXMASK;\n\tpBtCoexist->btc_coex_h2c_process = halbtcoutsrc_CoexH2cProcess;\n\tpBtCoexist->btc_get_bt_coex_supported_feature = halbtcoutsrc_GetBtCoexSupportedFeature;\n\tpBtCoexist->btc_get_bt_coex_supported_version= halbtcoutsrc_GetBtCoexSupportedVersion;\n\tpBtCoexist->btc_get_ant_det_val_from_bt = halbtcoutsrc_GetAntDetValFromBt;\n\tpBtCoexist->btc_get_ble_scan_type_from_bt = halbtcoutsrc_GetBleScanTypeFromBt;\n\tpBtCoexist->btc_get_ble_scan_para_from_bt = halbtcoutsrc_GetBleScanParaFromBt;\n\tpBtCoexist->btc_get_bt_afh_map_from_bt = halbtcoutsrc_GetBtAFHMapFromBt;\n\tpBtCoexist->btc_get_bt_phydm_version = halbtcoutsrc_GetPhydmVersion;\n\tpBtCoexist->btc_set_timer = halbtcoutsrc_SetTimer;\n\tpBtCoexist->btc_set_atomic= halbtcoutsrc_SetAtomic;\n\tpBtCoexist->btc_phydm_modify_RA_PCR_threshold = halbtcoutsrc_phydm_modify_RA_PCR_threshold;\n\tpBtCoexist->btc_phydm_query_PHY_counter = halbtcoutsrc_phydm_query_PHY_counter;\n\tpBtCoexist->btc_reduce_wl_tx_power = halbtcoutsrc_reduce_wl_tx_power;\n\tpBtCoexist->btc_phydm_modify_antdiv_hwsw = halbtcoutsrc_phydm_modify_AntDiv_HwSw;\n\n\tpBtCoexist->cli_buf = &GLBtcDbgBuf[0];\n\n\tGLBtcWiFiInScanState = _FALSE;\n\n\tGLBtcWiFiInIQKState = _FALSE;\n\n\tGLBtcWiFiInIPS = _FALSE;\n\n\tGLBtcWiFiInLPS = _FALSE;\n\n\tGLBtcBtCoexAliveRegistered = _FALSE;\n\n\t/* BT Control H2C/C2H*/\n\tGLBtcBtMpOperSeq = 0;\n\t_rtw_mutex_init(&GLBtcBtMpOperLock);\n\trtw_init_timer(&GLBtcBtMpOperTimer, padapter, _btmpoper_timer_hdl, pBtCoexist);\n\t_rtw_init_sema(&GLBtcBtMpRptSema, 0);\n\tGLBtcBtMpRptSeq = 0;\n\tGLBtcBtMpRptStatus = 0;\n\t_rtw_memset(GLBtcBtMpRptRsp, 0, C2H_MAX_SIZE);\n\tGLBtcBtMpRptRspSize = 0;\n\tGLBtcBtMpRptWait = _FALSE;\n\tGLBtcBtMpRptWiFiOK = _FALSE;\n\tGLBtcBtMpRptBTOK = _FALSE;\n\n\treturn _TRUE;\n}\n\nvoid EXhalbtcoutsrc_PowerOnSetting(PBTC_COEXIST pBtCoexist)\n{\n\tHAL_DATA_TYPE\t*pHalData = NULL;\n\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\tpHalData = GET_HAL_DATA((PADAPTER)pBtCoexist->Adapter);\n\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\trtw_btc_ex_power_on_setting(pBtCoexist);\n\n#else\n\tif (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8723B\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723b2ant_power_on_setting(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_power_on_setting(pBtCoexist);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8703B\n\telse if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8703b1ant_power_on_setting(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_power_on_setting(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_power_on_setting(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821A\n\telse if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821a1ant_power_on_setting(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821a2ant_power_on_setting(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8822B\n\telse if ((IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8822b1ant_power_on_setting(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8822b2ant_power_on_setting(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if ((IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_power_on_setting(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_power_on_setting(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8814A\n\tif (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8814a2ant_power_on_setting(pBtCoexist);\n\t\t/* else if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8814a1ant_power_on_setting(pBtCoexist); */\n\t}\n#endif\n\n#endif\n}\n\nvoid EXhalbtcoutsrc_PreLoadFirmware(PBTC_COEXIST pBtCoexist)\n{\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\tpBtCoexist->statistics.cnt_pre_load_firmware++;\n\n\tif (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8723B\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723b2ant_pre_load_firmware(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_pre_load_firmware(pBtCoexist);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_pre_load_firmware(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_pre_load_firmware(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_pre_load_firmware(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_pre_load_firmware(pBtCoexist);\n\t}\n#endif\n}\n\nvoid EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly)\n{\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\tpBtCoexist->statistics.cnt_init_hw_config++;\n\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\trtw_btc_ex_init_hw_config(pBtCoexist, bWifiOnly);\n#else\n\n\tif (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8821A\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821a2ant_init_hw_config(pBtCoexist, bWifiOnly);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821a1ant_init_hw_config(pBtCoexist, bWifiOnly);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8723B\n\telse if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723b2ant_init_hw_config(pBtCoexist, bWifiOnly);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_init_hw_config(pBtCoexist, bWifiOnly);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8703B\n\telse if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8703b1ant_init_hw_config(pBtCoexist, bWifiOnly);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_init_hw_config(pBtCoexist, bWifiOnly);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_init_hw_config(pBtCoexist, bWifiOnly);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8192E\n\telse if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8192e2ant_init_hw_config(pBtCoexist, bWifiOnly);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8192e1ant_init_hw_config(pBtCoexist, bWifiOnly);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8812A\n\telse if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8812a2ant_init_hw_config(pBtCoexist, bWifiOnly);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8812a1ant_init_hw_config(pBtCoexist, bWifiOnly);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8822B\n\telse if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8822b1ant_init_hw_config(pBtCoexist, bWifiOnly);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8822b2ant_init_hw_config(pBtCoexist, bWifiOnly);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_init_hw_config(pBtCoexist, bWifiOnly);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_init_hw_config(pBtCoexist, bWifiOnly);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8814A\n\telse if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8814a2ant_init_hw_config(pBtCoexist, bWifiOnly);\n\t}\n#endif\n\n#endif\n}\n\nvoid EXhalbtcoutsrc_init_coex_dm(PBTC_COEXIST pBtCoexist)\n{\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\tpBtCoexist->statistics.cnt_init_coex_dm++;\n\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\trtw_btc_ex_init_coex_dm(pBtCoexist);\n#else\n\n\tif (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8821A\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821a2ant_init_coex_dm(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821a1ant_init_coex_dm(pBtCoexist);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8723B\n\telse if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723b2ant_init_coex_dm(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_init_coex_dm(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8703B\n\telse if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8703b1ant_init_coex_dm(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_init_coex_dm(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_init_coex_dm(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8192E\n\telse if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8192e2ant_init_coex_dm(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8192e1ant_init_coex_dm(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8812A\n\telse if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8812a2ant_init_coex_dm(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8812a1ant_init_coex_dm(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8822B\n\telse if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8822b1ant_init_coex_dm(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8822b2ant_init_coex_dm(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_init_coex_dm(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_init_coex_dm(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8814A\n\telse if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8814a2ant_init_coex_dm(pBtCoexist);\n\t}\n#endif\n\n#endif\n\n\tpBtCoexist->initilized = _TRUE;\n}\n\nvoid EXhalbtcoutsrc_ips_notify(PBTC_COEXIST pBtCoexist, u8 type)\n{\n\tu8\tipsType;\n\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\tpBtCoexist->statistics.cnt_ips_notify++;\n\tif (pBtCoexist->manual_control)\n\t\treturn;\n\n\tif (IPS_NONE == type) {\n\t\tipsType = BTC_IPS_LEAVE;\n\t\tGLBtcWiFiInIPS = _FALSE;\n\t} else {\n\t\tipsType = BTC_IPS_ENTER;\n\t\tGLBtcWiFiInIPS = _TRUE;\n\t}\n\n\t/* All notify is called in cmd thread, don't need to leave low power again\n\t*\thalbtcoutsrc_LeaveLowPower(pBtCoexist); */\n\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\trtw_btc_ex_ips_notify(pBtCoexist, ipsType);\n#else\n\n\tif (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8821A\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821a2ant_ips_notify(pBtCoexist, ipsType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821a1ant_ips_notify(pBtCoexist, ipsType);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8723B\n\telse if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723b2ant_ips_notify(pBtCoexist, ipsType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_ips_notify(pBtCoexist, ipsType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8703B\n\telse if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8703b1ant_ips_notify(pBtCoexist, ipsType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_ips_notify(pBtCoexist, ipsType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_ips_notify(pBtCoexist, ipsType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8192E\n\telse if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8192e2ant_ips_notify(pBtCoexist, ipsType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8192e1ant_ips_notify(pBtCoexist, ipsType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8812A\n\telse if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8812a2ant_ips_notify(pBtCoexist, ipsType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8812a1ant_ips_notify(pBtCoexist, ipsType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8822B\n\telse if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8822b1ant_ips_notify(pBtCoexist, ipsType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8822b2ant_ips_notify(pBtCoexist, ipsType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_ips_notify(pBtCoexist, ipsType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_ips_notify(pBtCoexist, ipsType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8814A\n\telse if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8814a2ant_ips_notify(pBtCoexist, ipsType);\n\t}\n#endif\n\n#endif\n\t/*\thalbtcoutsrc_NormalLowPower(pBtCoexist); */\n}\n\nvoid EXhalbtcoutsrc_lps_notify(PBTC_COEXIST pBtCoexist, u8 type)\n{\n\tu8 lpsType;\n\n\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\tpBtCoexist->statistics.cnt_lps_notify++;\n\tif (pBtCoexist->manual_control)\n\t\treturn;\n\n\tif (PS_MODE_ACTIVE == type) {\n\t\tlpsType = BTC_LPS_DISABLE;\n\t\tGLBtcWiFiInLPS = _FALSE;\n\t} else {\n\t\tlpsType = BTC_LPS_ENABLE;\n\t\tGLBtcWiFiInLPS = _TRUE;\n\t}\n\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\trtw_btc_ex_lps_notify(pBtCoexist, lpsType);\n#else\n\n\tif (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8821A\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821a2ant_lps_notify(pBtCoexist, lpsType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821a1ant_lps_notify(pBtCoexist, lpsType);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8723B\n\telse if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723b2ant_lps_notify(pBtCoexist, lpsType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_lps_notify(pBtCoexist, lpsType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8703B\n\telse if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8703b1ant_lps_notify(pBtCoexist, lpsType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_lps_notify(pBtCoexist, lpsType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_lps_notify(pBtCoexist, lpsType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8192E\n\telse if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8192e2ant_lps_notify(pBtCoexist, lpsType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8192e1ant_lps_notify(pBtCoexist, lpsType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8812A\n\telse if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8812a2ant_lps_notify(pBtCoexist, lpsType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8812a1ant_lps_notify(pBtCoexist, lpsType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8822B\n\telse if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8822b1ant_lps_notify(pBtCoexist, lpsType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8822b2ant_lps_notify(pBtCoexist, lpsType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_lps_notify(pBtCoexist, lpsType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_lps_notify(pBtCoexist, lpsType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8814A\n\telse if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8814a2ant_lps_notify(pBtCoexist, lpsType);\n\t}\n#endif\n\n#endif\n}\n\nvoid EXhalbtcoutsrc_scan_notify(PBTC_COEXIST pBtCoexist, u8 type)\n{\n\tu8\tscanType;\n\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\tpBtCoexist->statistics.cnt_scan_notify++;\n\tif (pBtCoexist->manual_control)\n\t\treturn;\n\n\tif (type) {\n\t\tscanType = BTC_SCAN_START;\n\t\tGLBtcWiFiInScanState = _TRUE;\n\t} else {\n\t\tscanType = BTC_SCAN_FINISH;\n\t\tGLBtcWiFiInScanState = _FALSE;\n\t}\n\n\t/* All notify is called in cmd thread, don't need to leave low power again\n\t*\thalbtcoutsrc_LeaveLowPower(pBtCoexist); */\n\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\trtw_btc_ex_scan_notify(pBtCoexist, scanType);\n#else\n\n\tif (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8821A\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821a2ant_scan_notify(pBtCoexist, scanType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821a1ant_scan_notify(pBtCoexist, scanType);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8723B\n\telse if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723b2ant_scan_notify(pBtCoexist, scanType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_scan_notify(pBtCoexist, scanType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8703B\n\telse if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8703b1ant_scan_notify(pBtCoexist, scanType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_scan_notify(pBtCoexist, scanType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_scan_notify(pBtCoexist, scanType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8192E\n\telse if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8192e2ant_scan_notify(pBtCoexist, scanType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8192e1ant_scan_notify(pBtCoexist, scanType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8812A\n\telse if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8812a2ant_scan_notify(pBtCoexist, scanType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8812a1ant_scan_notify(pBtCoexist, scanType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8822B\n\telse if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8822b1ant_scan_notify(pBtCoexist, scanType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8822b2ant_scan_notify(pBtCoexist, scanType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_scan_notify(pBtCoexist, scanType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_scan_notify(pBtCoexist, scanType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8814A\n\telse if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8814a2ant_scan_notify(pBtCoexist, scanType);\n\t}\n#endif\n\n#endif\n\n\t/*\thalbtcoutsrc_NormalLowPower(pBtCoexist); */\n}\n\nvoid EXhalbtcoutsrc_SetAntennaPathNotify(PBTC_COEXIST pBtCoexist, u8 type)\n{\n#if 0\n\tu8\tswitchType;\n\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\tif (pBtCoexist->manual_control)\n\t\treturn;\n\n\thalbtcoutsrc_LeaveLowPower(pBtCoexist);\n\n\tswitchType = type;\n\n\tif (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_set_antenna_notify(pBtCoexist, type);\n\t}\n\tif (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_set_antenna_notify(pBtCoexist, type);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_set_antenna_notify(pBtCoexist, type);\n\t}\n\n\thalbtcoutsrc_NormalLowPower(pBtCoexist);\n#endif\n}\n\nvoid EXhalbtcoutsrc_connect_notify(PBTC_COEXIST pBtCoexist, u8 assoType)\n{\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\tpBtCoexist->statistics.cnt_connect_notify++;\n\tif (pBtCoexist->manual_control)\n\t\treturn;\n\t\n\t/* All notify is called in cmd thread, don't need to leave low power again\n\t*\thalbtcoutsrc_LeaveLowPower(pBtCoexist); */\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\trtw_btc_ex_connect_notify(pBtCoexist, assoType);\n#else\n\n\tif (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8821A\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821a2ant_connect_notify(pBtCoexist, assoType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821a1ant_connect_notify(pBtCoexist, assoType);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8723B\n\telse if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723b2ant_connect_notify(pBtCoexist, assoType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_connect_notify(pBtCoexist, assoType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8703B\n\telse if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8703b1ant_connect_notify(pBtCoexist, assoType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_connect_notify(pBtCoexist, assoType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_connect_notify(pBtCoexist, assoType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8192E\n\telse if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8192e2ant_connect_notify(pBtCoexist, assoType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8192e1ant_connect_notify(pBtCoexist, assoType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8812A\n\telse if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8812a2ant_connect_notify(pBtCoexist, assoType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8812a1ant_connect_notify(pBtCoexist, assoType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8822B\n\telse if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8822b1ant_connect_notify(pBtCoexist, assoType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8822b2ant_connect_notify(pBtCoexist, assoType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_connect_notify(pBtCoexist, assoType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_connect_notify(pBtCoexist, assoType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8814A\n\telse if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8814a2ant_connect_notify(pBtCoexist, assoType);\n\t}\n#endif\n\n#endif\n\n\t/*\thalbtcoutsrc_NormalLowPower(pBtCoexist); */\n}\n\nvoid EXhalbtcoutsrc_media_status_notify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS mediaStatus)\n{\n\tu8 mStatus = BTC_MEDIA_MAX;\n\tPADAPTER adapter = NULL;\n\tHAL_DATA_TYPE *hal = NULL;\n\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\tif (pBtCoexist->manual_control)\n\t\treturn;\n\n\tpBtCoexist->statistics.cnt_media_status_notify++;\n\tadapter = (PADAPTER)pBtCoexist->Adapter;\n\thal = GET_HAL_DATA(adapter);\n\n\tif (RT_MEDIA_CONNECT == mediaStatus) {\n\t\tif (hal->current_band_type == BAND_ON_2_4G)\n\t\t\tmStatus = BTC_MEDIA_CONNECT;\n\t\telse if (hal->current_band_type == BAND_ON_5G)\n\t\t\tmStatus = BTC_MEDIA_CONNECT_5G;\n\t\telse {\n\t\t\tmStatus = BTC_MEDIA_CONNECT;\n\t\t\tRTW_ERR(\"%s unknow band type\\n\", __func__);\n\t\t}\n\t} else\n\t\tmStatus = BTC_MEDIA_DISCONNECT;\n\n\t/* All notify is called in cmd thread, don't need to leave low power again\n\t*\thalbtcoutsrc_LeaveLowPower(pBtCoexist); */\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\trtw_btc_ex_media_status_notify(pBtCoexist, mStatus);\n#else\n\n\tif (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8821A\n\t\t/* compatible for 8821A */\n\t\tif (mStatus == BTC_MEDIA_CONNECT_5G)\n\t\t\tmStatus = BTC_MEDIA_CONNECT;\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821a2ant_media_status_notify(pBtCoexist, mStatus);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821a1ant_media_status_notify(pBtCoexist, mStatus);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8723B\n\telse if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723b2ant_media_status_notify(pBtCoexist, mStatus);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_media_status_notify(pBtCoexist, mStatus);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8703B\n\telse if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8703b1ant_media_status_notify(pBtCoexist, mStatus);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_media_status_notify(pBtCoexist, mStatus);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_media_status_notify(pBtCoexist, mStatus);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8192E\n\telse if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8192e2ant_media_status_notify(pBtCoexist, mStatus);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8192e1ant_media_status_notify(pBtCoexist, mStatus);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8812A\n\telse if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {\n\t\t/* compatible for 8812A */\n\t\tif (mStatus == BTC_MEDIA_CONNECT_5G)\n\t\t\tmStatus = BTC_MEDIA_CONNECT;\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8812a2ant_media_status_notify(pBtCoexist, mStatus);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8812a1ant_media_status_notify(pBtCoexist, mStatus);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8822B\n\telse if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8822b1ant_media_status_notify(pBtCoexist, mStatus);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8822b2ant_media_status_notify(pBtCoexist, mStatus);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_media_status_notify(pBtCoexist, mStatus);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_media_status_notify(pBtCoexist, mStatus);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8814A\n\telse if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8814a2ant_media_status_notify(pBtCoexist, mStatus);\n\t}\n#endif\n\n#endif\n\n\t/*\thalbtcoutsrc_NormalLowPower(pBtCoexist); */\n}\n\nvoid EXhalbtcoutsrc_specific_packet_notify(PBTC_COEXIST pBtCoexist, u8 pktType)\n{\n\tu8 packetType;\n\tPADAPTER adapter = NULL;\n\tHAL_DATA_TYPE *hal = NULL;\n\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\t\n\tif (pBtCoexist->manual_control)\n\t\treturn;\n\n\tpBtCoexist->statistics.cnt_specific_packet_notify++;\n\tadapter = (PADAPTER)pBtCoexist->Adapter;\n\thal = GET_HAL_DATA(adapter);\n\n\tif (PACKET_DHCP == pktType)\n\t\tpacketType = BTC_PACKET_DHCP;\n\telse if (PACKET_EAPOL == pktType)\n\t\tpacketType = BTC_PACKET_EAPOL;\n\telse if (PACKET_ARP == pktType)\n\t\tpacketType = BTC_PACKET_ARP;\n\telse {\n\t\tpacketType = BTC_PACKET_UNKNOWN;\n\t\treturn;\n\t}\n\n\tif (hal->current_band_type == BAND_ON_5G)\n\t\tpacketType |=  BTC_5G_BAND;\n\n\t/* All notify is called in cmd thread, don't need to leave low power again\n\t*\thalbtcoutsrc_LeaveLowPower(pBtCoexist); */\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\trtw_btc_ex_specific_packet_notify(pBtCoexist, packetType);\n#else\n\n\tif (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8821A\n\t\t/* compatible for 8821A */\n\t\tif (hal->current_band_type == BAND_ON_5G)\n\t\t\tpacketType &= ~BTC_5G_BAND;\n\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821a2ant_specific_packet_notify(pBtCoexist, packetType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821a1ant_specific_packet_notify(pBtCoexist, packetType);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8723B\n\telse if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723b2ant_specific_packet_notify(pBtCoexist, packetType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_specific_packet_notify(pBtCoexist, packetType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8703B\n\telse if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8703b1ant_specific_packet_notify(pBtCoexist, packetType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_specific_packet_notify(pBtCoexist, packetType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_specific_packet_notify(pBtCoexist, packetType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8192E\n\telse if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8192e2ant_specific_packet_notify(pBtCoexist, packetType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8192e1ant_specific_packet_notify(pBtCoexist, packetType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8812A\n\telse if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {\n\t\t/* compatible for 8812A */\n\t\tif (hal->current_band_type == BAND_ON_5G)\n\t\t\tpacketType &= ~BTC_5G_BAND;\n\t\t\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8812a2ant_specific_packet_notify(pBtCoexist, packetType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8812a1ant_specific_packet_notify(pBtCoexist, packetType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8822B\n\telse if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8822b1ant_specific_packet_notify(pBtCoexist, packetType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8822b2ant_specific_packet_notify(pBtCoexist, packetType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_specific_packet_notify(pBtCoexist, packetType);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_specific_packet_notify(pBtCoexist, packetType);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8814A\n\telse if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8814a2ant_specific_packet_notify(pBtCoexist, packetType);\n\t}\n#endif\n\n#endif\n\n\t/*\thalbtcoutsrc_NormalLowPower(pBtCoexist); */\n}\n\nvoid EXhalbtcoutsrc_bt_info_notify(PBTC_COEXIST pBtCoexist, u8 *tmpBuf, u8 length)\n{\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\tpBtCoexist->statistics.cnt_bt_info_notify++;\n\n\t/* All notify is called in cmd thread, don't need to leave low power again\n\t*\thalbtcoutsrc_LeaveLowPower(pBtCoexist); */\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\trtw_btc_ex_bt_info_notify(pBtCoexist, tmpBuf, length);\n#else\n\n\tif (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8821A\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821a2ant_bt_info_notify(pBtCoexist, tmpBuf, length);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821a1ant_bt_info_notify(pBtCoexist, tmpBuf, length);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8723B\n\telse if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723b2ant_bt_info_notify(pBtCoexist, tmpBuf, length);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_bt_info_notify(pBtCoexist, tmpBuf, length);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8703B\n\telse if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8703b1ant_bt_info_notify(pBtCoexist, tmpBuf, length);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_bt_info_notify(pBtCoexist, tmpBuf, length);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_bt_info_notify(pBtCoexist, tmpBuf, length);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8192E\n\telse if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8192e2ant_bt_info_notify(pBtCoexist, tmpBuf, length);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8192e1ant_bt_info_notify(pBtCoexist, tmpBuf, length);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8812A\n\telse if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8812a2ant_bt_info_notify(pBtCoexist, tmpBuf, length);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8812a1ant_bt_info_notify(pBtCoexist, tmpBuf, length);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8822B\n\telse if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8822b1ant_bt_info_notify(pBtCoexist, tmpBuf, length);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8822b2ant_bt_info_notify(pBtCoexist, tmpBuf, length);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_bt_info_notify(pBtCoexist, tmpBuf, length);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_bt_info_notify(pBtCoexist, tmpBuf, length);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8814A\n\telse if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8814a2ant_bt_info_notify(pBtCoexist, tmpBuf, length);\n\t}\n#endif\n\n#endif\n\n\t/*\thalbtcoutsrc_NormalLowPower(pBtCoexist); */\n}\n\nvoid EXhalbtcoutsrc_WlFwDbgInfoNotify(PBTC_COEXIST pBtCoexist, u8* tmpBuf, u8 length)\n{\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\trtw_btc_ex_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);\n#else\n\n\tif (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8703B\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8703b1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);\n\t}\n#endif\n\n#endif\n}\n\nvoid EXhalbtcoutsrc_rx_rate_change_notify(PBTC_COEXIST pBtCoexist, u8 is_data_frame, u8 btc_rate_id)\n{\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\tpBtCoexist->statistics.cnt_rate_id_notify++;\n\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\trtw_btc_ex_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);\n#else\n\n\tif (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8703B\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8703b1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);\n\t}\n#endif\n\n#endif\n}\n\nvoid\nEXhalbtcoutsrc_RfStatusNotify(\n\t\tPBTC_COEXIST\t\tpBtCoexist,\n\t\tu8\t\t\t\ttype\n)\n{\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\tpBtCoexist->statistics.cnt_rf_status_notify++;\n\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\trtw_btc_ex_rf_status_notify(pBtCoexist, type);\n#else\n\n\tif (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8723B\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_rf_status_notify(pBtCoexist, type);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8703B\n\telse if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8703b1ant_rf_status_notify(pBtCoexist, type);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_rf_status_notify(pBtCoexist, type);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8822B\n\telse if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8822b1ant_rf_status_notify(pBtCoexist, type);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8822b2ant_rf_status_notify(pBtCoexist, type);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_rf_status_notify(pBtCoexist, type);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_rf_status_notify(pBtCoexist, type);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8814A\n\telse if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8814a2ant_rf_status_notify(pBtCoexist, type);\n\t}\n#endif\n\n#endif\n}\n\nvoid EXhalbtcoutsrc_StackOperationNotify(PBTC_COEXIST pBtCoexist, u8 type)\n{\n#if 0\n\tu8\tstackOpType;\n\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\tpBtCoexist->statistics.cntStackOperationNotify++;\n\tif (pBtCoexist->manual_control)\n\t\treturn;\n\n\tif ((HCI_BT_OP_INQUIRY_START == type) ||\n\t    (HCI_BT_OP_PAGING_START == type) ||\n\t    (HCI_BT_OP_PAIRING_START == type))\n\t\tstackOpType = BTC_STACK_OP_INQ_PAGE_PAIR_START;\n\telse if ((HCI_BT_OP_INQUIRY_FINISH == type) ||\n\t\t (HCI_BT_OP_PAGING_SUCCESS == type) ||\n\t\t (HCI_BT_OP_PAGING_UNSUCCESS == type) ||\n\t\t (HCI_BT_OP_PAIRING_FINISH == type))\n\t\tstackOpType = BTC_STACK_OP_INQ_PAGE_PAIR_FINISH;\n\telse\n\t\tstackOpType = BTC_STACK_OP_NONE;\n\n#endif\n}\n\nvoid EXhalbtcoutsrc_halt_notify(PBTC_COEXIST pBtCoexist)\n{\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\tpBtCoexist->statistics.cnt_halt_notify++;\n\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\trtw_btc_ex_halt_notify(pBtCoexist);\n#else\n\n\tif (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8821A\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821a2ant_halt_notify(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821a1ant_halt_notify(pBtCoexist);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8723B\n\telse if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723b2ant_halt_notify(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_halt_notify(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8703B\n\telse if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8703b1ant_halt_notify(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_halt_notify(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_halt_notify(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8192E\n\telse if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8192e2ant_halt_notify(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8192e1ant_halt_notify(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8812A\n\telse if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8812a2ant_halt_notify(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8812a1ant_halt_notify(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8822B\n\telse if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8822b1ant_halt_notify(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8822b2ant_halt_notify(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_halt_notify(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_halt_notify(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8814A\n\telse if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8814a2ant_halt_notify(pBtCoexist);\n\t}\n#endif\n\n#endif\n}\n\nvoid EXhalbtcoutsrc_SwitchBtTRxMask(PBTC_COEXIST pBtCoexist)\n{\n\tif (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2) {\n\t\t\thalbtcoutsrc_SetBtReg(pBtCoexist, 0, 0x3c, 0x01); /* BT goto standby while GNT_BT 1-->0 */\n\t\t} else if (pBtCoexist->board_info.btdm_ant_num == 1) {\n\t\t\thalbtcoutsrc_SetBtReg(pBtCoexist, 0, 0x3c, 0x15); /* BT goto standby while GNT_BT 1-->0 */\n\t\t}\n\t}\n}\n\nvoid EXhalbtcoutsrc_pnp_notify(PBTC_COEXIST pBtCoexist, u8 pnpState)\n{\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\tpBtCoexist->statistics.cnt_pnp_notify++;\n\n\t/*  */\n\t/* currently only 1ant we have to do the notification, */\n\t/* once pnp is notified to sleep state, we have to leave LPS that we can sleep normally. */\n\t/*  */\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\trtw_btc_ex_pnp_notify(pBtCoexist, pnpState);\n#else\n\n\tif (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8723B\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_pnp_notify(pBtCoexist, pnpState);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723b2ant_pnp_notify(pBtCoexist, pnpState);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8703B\n\telse if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8703b1ant_pnp_notify(pBtCoexist, pnpState);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_pnp_notify(pBtCoexist, pnpState);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_pnp_notify(pBtCoexist, pnpState);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821A\n\telse if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821a1ant_pnp_notify(pBtCoexist, pnpState);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821a2ant_pnp_notify(pBtCoexist, pnpState);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8192E\n\telse if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8192e1ant_pnp_notify(pBtCoexist, pnpState);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8812A\n\telse if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8812a1ant_pnp_notify(pBtCoexist, pnpState);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8822B\n\telse if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8822b1ant_pnp_notify(pBtCoexist, pnpState);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8822b2ant_pnp_notify(pBtCoexist, pnpState);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_pnp_notify(pBtCoexist, pnpState);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_pnp_notify(pBtCoexist, pnpState);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8814A\n\telse if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8814a2ant_pnp_notify(pBtCoexist, pnpState);\n\t}\n#endif\n\n#endif\n}\n\nvoid EXhalbtcoutsrc_CoexDmSwitch(PBTC_COEXIST pBtCoexist)\n{\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\tpBtCoexist->statistics.cnt_coex_dm_switch++;\n\n\thalbtcoutsrc_LeaveLowPower(pBtCoexist);\n\n\tif (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8723B\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1) {\n\t\t\tpBtCoexist->stop_coex_dm = TRUE;\n\t\t\tex_halbtc8723b1ant_coex_dm_reset(pBtCoexist);\n\t\t\tEXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_DETECTED, 2);\n\t\t\tex_halbtc8723b2ant_init_hw_config(pBtCoexist, FALSE);\n\t\t\tex_halbtc8723b2ant_init_coex_dm(pBtCoexist);\n\t\t\tpBtCoexist->stop_coex_dm = FALSE;\n\t\t}\n#endif\n\t}\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1) {\n\t\t\tpBtCoexist->stop_coex_dm = TRUE;\n\t\t\tex_halbtc8723d1ant_coex_dm_reset(pBtCoexist);\n\t\t\tEXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_DETECTED, 2);\n\t\t\tex_halbtc8723d2ant_init_hw_config(pBtCoexist, FALSE);\n\t\t\tex_halbtc8723d2ant_init_coex_dm(pBtCoexist);\n\t\t\tpBtCoexist->stop_coex_dm = FALSE;\n\t\t}\n\t}\n#endif\n\n\thalbtcoutsrc_NormalLowPower(pBtCoexist);\n}\n\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\nvoid EXhalbtcoutsrc_TimerNotify(PBTC_COEXIST pBtCoexist, u32 timer_type)\n{\n\trtw_btc_ex_timerup_notify(pBtCoexist, timer_type);\n}\n\nvoid EXhalbtcoutsrc_WLStatusChangeNotify(PBTC_COEXIST pBtCoexist, u32 change_type)\n{\n\trtw_btc_ex_wl_status_change_notify(pBtCoexist, change_type);\n}\n\nu32 EXhalbtcoutsrc_CoexTimerCheck(PBTC_COEXIST pBtCoexist)\n{\n\tu32 i, timer_map = 0;\n\n\tfor (i = 0; i < BTC_TIMER_MAX; i++) {\n\t\tif (pBtCoexist->coex_sta.cnt_timer[i] > 0) {\n\t\t\tif (pBtCoexist->coex_sta.cnt_timer[i] == 1) {\n\t\t\t\ttimer_map |= BIT(i);\n\t\t\t\tRTW_DBG(\"[BTC], %s(): timer_map = 0x%x\\n\", __func__, timer_map);\n\t\t\t}\n\n\t\t\tpBtCoexist->coex_sta.cnt_timer[i]--;\n\t\t}\n\t}\n\n\treturn timer_map;\n}\n\nu32 EXhalbtcoutsrc_WLStatusCheck(PBTC_COEXIST pBtCoexist)\n{\n\tstruct btc_wifi_link_info link_info;\n\tconst struct btc_chip_para *chip_para = pBtCoexist->chip_para;\n\tu32 change_map = 0;\n\tstatic bool wl_busy_pre;\n\tbool\twl_busy = _FALSE;\n\ts32 wl_rssi;\n\tu32 traffic_dir;\n\tu8 i, tmp;\n\tstatic u8 rssi_step_pre = 5, wl_noisy_level_pre = 4;\n\n\t/* WL busy to idle or idle to busy */\n\tpBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &wl_busy);\n\tif (wl_busy != wl_busy_pre) {\n\t\tif (wl_busy)\n\t\t\tchange_map |=  BIT(BTC_WLSTATUS_CHANGE_TOBUSY);\n\t\telse\n\t\t\tchange_map |=  BIT(BTC_WLSTATUS_CHANGE_TOIDLE);\n\n\t\twl_busy_pre = wl_busy;\n\t}\n\n\t/* WL RSSI */\n\tpBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wl_rssi);\n\ttmp = (u8)(wl_rssi & 0xff);\n\tfor (i = 0; i < 4; i++) {\n\t\tif (tmp >= chip_para->wl_rssi_step[i])\n\t\t\tbreak;\n\t}\n\n\tif (rssi_step_pre != i) {\n\t\trssi_step_pre = i;\n\t\tchange_map |=  BIT(BTC_WLSTATUS_CHANGE_RSSI);\n\t}\n\n\t/* WL Link info */\n\tpBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK_INFO, &link_info);\n\tif (link_info.link_mode != pBtCoexist->wifi_link_info.link_mode ||\n\t    link_info.sta_center_channel !=\n\t    \t\tpBtCoexist->wifi_link_info.sta_center_channel ||\n\t    link_info.p2p_center_channel !=\n\t    \t\tpBtCoexist->wifi_link_info.p2p_center_channel ||\n\t    link_info.bany_client_join_go !=\n\t    \t\tpBtCoexist->wifi_link_info.bany_client_join_go) {\n\t\tchange_map |=  BIT(BTC_WLSTATUS_CHANGE_LINKINFO);\n\t\tpBtCoexist->wifi_link_info = link_info;\n\t}\n\n\t/* WL Traffic Direction */\n\tpBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIR, &traffic_dir);\n\tif (wl_busy && traffic_dir != pBtCoexist->wifi_link_info_ext.traffic_dir) {\n\t\tchange_map |=  BIT(BTC_WLSTATUS_CHANGE_DIR);\n\t\tpBtCoexist->wifi_link_info_ext.traffic_dir = traffic_dir;\n\t}\n\n\t/* Noisy Detect */\n\tif (pBtCoexist->coex_sta.wl_noisy_level != wl_noisy_level_pre) {\n\t\tchange_map |=  BIT(BTC_WLSTATUS_CHANGE_NOISY);\n\t\twl_noisy_level_pre = pBtCoexist->coex_sta.wl_noisy_level;\n\t}\n\n\tRTW_DBG(\"[BTC], %s(): change_map = 0x%x\\n\", __func__, change_map);\n\n\treturn change_map;\n}\n\nvoid EXhalbtcoutsrc_status_monitor(PBTC_COEXIST pBtCoexist)\n{\n\tu32 timer_up_type = 0, wl_status_change_type = 0;\n\n\ttimer_up_type = EXhalbtcoutsrc_CoexTimerCheck(pBtCoexist);\n\tif (timer_up_type != 0)\n\t\tEXhalbtcoutsrc_TimerNotify(pBtCoexist, timer_up_type);\n\n\twl_status_change_type =  EXhalbtcoutsrc_WLStatusCheck(pBtCoexist);\n\tif (wl_status_change_type != 0)\n\t\tEXhalbtcoutsrc_WLStatusChangeNotify(pBtCoexist, wl_status_change_type);\n\n\trtw_btc_ex_periodical(pBtCoexist);\n}\n#endif\n\nvoid EXhalbtcoutsrc_periodical(PBTC_COEXIST pBtCoexist)\n{\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\tpBtCoexist->statistics.cnt_periodical++;\n\n\t/* Periodical should be called in cmd thread, */\n\t/* don't need to leave low power again\n\t*\thalbtcoutsrc_LeaveLowPower(pBtCoexist); */\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\tEXhalbtcoutsrc_status_monitor(pBtCoexist);\n#else\n\n\tif (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8821A\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821a2ant_periodical(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1) {\n\t\t\tif (!halbtcoutsrc_UnderIps(pBtCoexist))\n\t\t\t\tex_halbtc8821a1ant_periodical(pBtCoexist);\n\t\t}\n#endif\n\t}\n\n#ifdef CONFIG_RTL8723B\n\telse if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723b2ant_periodical(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_periodical(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_periodical(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_periodical(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8703B\n\telse if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8703b1ant_periodical(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8192E\n\telse if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8192e2ant_periodical(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8192e1ant_periodical(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8812A\n\telse if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8812a2ant_periodical(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8812a1ant_periodical(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8822B\n\telse if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8822b1ant_periodical(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8822b2ant_periodical(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_periodical(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_periodical(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8814A\n\telse if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8814a2ant_periodical(pBtCoexist);\n\t}\n#endif\n\n#endif\n\n\t/*\thalbtcoutsrc_NormalLowPower(pBtCoexist); */\n}\n\nvoid EXhalbtcoutsrc_dbg_control(PBTC_COEXIST pBtCoexist, u8 opCode, u8 opLen, u8 *pData)\n{\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\tpBtCoexist->statistics.cnt_dbg_ctrl++;\n\n\t/* This function doesn't be called yet, */\n\t/* default no need to leave low power to avoid deadlock\n\t*\thalbtcoutsrc_LeaveLowPower(pBtCoexist); */\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\t/* rtw_btc_ex_dbg_control(pBtCoexist, opCode, opLen, pData); */\n#else\n\n\tif (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8192E\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8192e1ant_dbg_control(pBtCoexist, opCode, opLen, pData);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8812A\n\telse if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8812a2ant_dbg_control(pBtCoexist, opCode, opLen, pData);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8812a1ant_dbg_control(pBtCoexist, opCode, opLen, pData);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8822B\n\telse if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter))\n\t\tif(pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8822b1ant_dbg_control(pBtCoexist, opCode, opLen, pData);\n#endif\n\n#endif\n\n\t/*\thalbtcoutsrc_NormalLowPower(pBtCoexist); */\n}\n\n#if 0\nvoid\nEXhalbtcoutsrc_AntennaDetection(\n\t\tPBTC_COEXIST\t\t\tpBtCoexist,\n\t\tu32\t\t\t\t\tcentFreq,\n\t\tu32\t\t\t\t\toffset,\n\t\tu32\t\t\t\t\tspan,\n\t\tu32\t\t\t\t\tseconds\n)\n{\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\t/* Need to refine the following power save operations to enable this function in the future */\n#if 0\n\tIPSDisable(pBtCoexist->Adapter, FALSE, 0);\n\tLeisurePSLeave(pBtCoexist->Adapter, LPS_DISABLE_BT_COEX);\n#endif\n\n\tif (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_AntennaDetection(pBtCoexist, centFreq, offset, span, seconds);\n\t}\n\n\t/* IPSReturn(pBtCoexist->Adapter, 0xff); */\n}\n#endif\n\nvoid EXhalbtcoutsrc_StackUpdateProfileInfo(void)\n{\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\tPBTC_COEXIST pBtCoexist = &GLBtCoexist;\n\tPADAPTER padapter = NULL;\n\tPBT_MGNT pBtMgnt = NULL;\n\tu8 i;\n\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\tpadapter = (PADAPTER)pBtCoexist->Adapter;\n\tpBtMgnt = &padapter->coex_info.BtMgnt;\n\n\tpBtCoexist->stack_info.profile_notified = _TRUE;\n\n\tpBtCoexist->stack_info.num_of_link =\n\t\tpBtMgnt->ExtConfig.NumberOfACL + pBtMgnt->ExtConfig.NumberOfSCO;\n\n\t/* reset first */\n\tpBtCoexist->stack_info.bt_link_exist = _FALSE;\n\tpBtCoexist->stack_info.sco_exist = _FALSE;\n\tpBtCoexist->stack_info.acl_exist = _FALSE;\n\tpBtCoexist->stack_info.a2dp_exist = _FALSE;\n\tpBtCoexist->stack_info.hid_exist = _FALSE;\n\tpBtCoexist->stack_info.num_of_hid = 0;\n\tpBtCoexist->stack_info.pan_exist = _FALSE;\n\n\tif (!pBtMgnt->ExtConfig.NumberOfACL)\n\t\tpBtCoexist->stack_info.min_bt_rssi = 0;\n\n\tif (pBtCoexist->stack_info.num_of_link) {\n\t\tpBtCoexist->stack_info.bt_link_exist = _TRUE;\n\t\tif (pBtMgnt->ExtConfig.NumberOfSCO)\n\t\t\tpBtCoexist->stack_info.sco_exist = _TRUE;\n\t\tif (pBtMgnt->ExtConfig.NumberOfACL)\n\t\t\tpBtCoexist->stack_info.acl_exist = _TRUE;\n\t}\n\n\tfor (i = 0; i < pBtMgnt->ExtConfig.NumberOfACL; i++) {\n\t\tif (BT_PROFILE_A2DP == pBtMgnt->ExtConfig.aclLink[i].BTProfile)\n\t\t\tpBtCoexist->stack_info.a2dp_exist = _TRUE;\n\t\telse if (BT_PROFILE_PAN == pBtMgnt->ExtConfig.aclLink[i].BTProfile)\n\t\t\tpBtCoexist->stack_info.pan_exist = _TRUE;\n\t\telse if (BT_PROFILE_HID == pBtMgnt->ExtConfig.aclLink[i].BTProfile) {\n\t\t\tpBtCoexist->stack_info.hid_exist = _TRUE;\n\t\t\tpBtCoexist->stack_info.num_of_hid++;\n\t\t} else\n\t\t\tpBtCoexist->stack_info.unknown_acl_exist = _TRUE;\n\t}\n#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */\n}\n\nvoid EXhalbtcoutsrc_UpdateMinBtRssi(s8 btRssi)\n{\n\tPBTC_COEXIST pBtCoexist = &GLBtCoexist;\n\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\tpBtCoexist->stack_info.min_bt_rssi = btRssi;\n}\n\nvoid EXhalbtcoutsrc_SetHciVersion(u16 hciVersion)\n{\n\tPBTC_COEXIST pBtCoexist = &GLBtCoexist;\n\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\tpBtCoexist->stack_info.hci_version = hciVersion;\n}\n\nvoid EXhalbtcoutsrc_SetBtPatchVersion(u16 btHciVersion, u16 btPatchVersion)\n{\n\tPBTC_COEXIST pBtCoexist = &GLBtCoexist;\n\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\tpBtCoexist->bt_info.bt_real_fw_ver = btPatchVersion;\n\tpBtCoexist->bt_info.bt_hci_ver = btHciVersion;\n}\n\n#if 0\nvoid EXhalbtcoutsrc_SetBtExist(u8 bBtExist)\n{\n\tGLBtCoexist.boardInfo.bBtExist = bBtExist;\n}\n#endif\nvoid EXhalbtcoutsrc_SetChipType(u8 chipType)\n{\n\tswitch (chipType) {\n\tdefault:\n\tcase BT_2WIRE:\n\tcase BT_ISSC_3WIRE:\n\tcase BT_ACCEL:\n\tcase BT_RTL8756:\n\t\tGLBtCoexist.board_info.bt_chip_type = BTC_CHIP_UNDEF;\n\t\tbreak;\n\tcase BT_CSR_BC4:\n\t\tGLBtCoexist.board_info.bt_chip_type = BTC_CHIP_CSR_BC4;\n\t\tbreak;\n\tcase BT_CSR_BC8:\n\t\tGLBtCoexist.board_info.bt_chip_type = BTC_CHIP_CSR_BC8;\n\t\tbreak;\n\tcase BT_RTL8723A:\n\t\tGLBtCoexist.board_info.bt_chip_type = BTC_CHIP_RTL8723A;\n\t\tbreak;\n\tcase BT_RTL8821:\n\t\tGLBtCoexist.board_info.bt_chip_type = BTC_CHIP_RTL8821;\n\t\tbreak;\n\tcase BT_RTL8723B:\n\t\tGLBtCoexist.board_info.bt_chip_type = BTC_CHIP_RTL8723B;\n\t\tbreak;\n\t}\n}\n\nvoid EXhalbtcoutsrc_SetAntNum(u8 type, u8 antNum)\n{\n\tif (BT_COEX_ANT_TYPE_PG == type) {\n\t\tGLBtCoexist.board_info.pg_ant_num = antNum;\n\t\tGLBtCoexist.board_info.btdm_ant_num = antNum;\n#if 0\n\t\t/* The antenna position: Main (default) or Aux for pgAntNum=2 && btdmAntNum =1 */\n\t\t/* The antenna position should be determined by auto-detect mechanism */\n\t\t/* The following is assumed to main, and those must be modified if y auto-detect mechanism is ready */\n\t\tif ((GLBtCoexist.board_info.pg_ant_num == 2) && (GLBtCoexist.board_info.btdm_ant_num == 1))\n\t\t\tGLBtCoexist.board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;\n\t\telse\n\t\t\tGLBtCoexist.board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;\n#endif\n\t} else if (BT_COEX_ANT_TYPE_ANTDIV == type) {\n\t\tGLBtCoexist.board_info.btdm_ant_num = antNum;\n\t\t/* GLBtCoexist.boardInfo.btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT;\t */\n\t} else if (BT_COEX_ANT_TYPE_DETECTED == type) {\n\t\tGLBtCoexist.board_info.btdm_ant_num = antNum;\n\t\t/* GLBtCoexist.boardInfo.btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; */\n\t}\n}\n\n/*\n * Currently used by 8723b only, S0 or S1\n *   */\nvoid EXhalbtcoutsrc_SetSingleAntPath(u8 singleAntPath)\n{\n\tGLBtCoexist.board_info.single_ant_path = singleAntPath;\n}\n\nvoid EXhalbtcoutsrc_DisplayBtCoexInfo(PBTC_COEXIST pBtCoexist)\n{\n\tHAL_DATA_TYPE\t*pHalData = NULL;\n\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\thalbtcoutsrc_LeaveLowPower(pBtCoexist);\n\n\t/* To prevent the racing with IPS enter */\n\thalbtcoutsrc_EnterPwrLock(pBtCoexist);\n\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\tpHalData = GET_HAL_DATA((PADAPTER)pBtCoexist->Adapter);\n\n\tif (pHalData->EEPROMBluetoothCoexist == _TRUE)\n\t\trtw_btc_ex_display_coex_info(pBtCoexist);\n#else\n\n\tif (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8821A\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821a2ant_display_coex_info(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821a1ant_display_coex_info(pBtCoexist);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8723B\n\telse if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723b2ant_display_coex_info(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_display_coex_info(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8703B\n\telse if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8703b1ant_display_coex_info(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8723D\n\telse if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8723d2ant_display_coex_info(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723d1ant_display_coex_info(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8192E\n\telse if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8192e2ant_display_coex_info(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8192e1ant_display_coex_info(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8812A\n\telse if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8812a2ant_display_coex_info(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8812a1ant_display_coex_info(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8822B\n\telse if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8822b1ant_display_coex_info(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8822b2ant_display_coex_info(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_display_coex_info(pBtCoexist);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_display_coex_info(pBtCoexist);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8814A\n\telse if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8814a2ant_display_coex_info(pBtCoexist);\n\t}\n#endif\n\n#endif\n\n\thalbtcoutsrc_ExitPwrLock(pBtCoexist);\n\n\thalbtcoutsrc_NormalLowPower(pBtCoexist);\n}\n\nvoid EXhalbtcoutsrc_DisplayAntDetection(PBTC_COEXIST pBtCoexist)\n{\n\tif (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\n\thalbtcoutsrc_LeaveLowPower(pBtCoexist);\n\n\tif (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8723B\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8723b1ant_display_ant_detection(pBtCoexist);\n#endif\n\t}\n\n\thalbtcoutsrc_NormalLowPower(pBtCoexist);\n}\n\nvoid ex_halbtcoutsrc_pta_off_on_notify(PBTC_COEXIST pBtCoexist, u8 bBTON)\n{\n\tif (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8812A\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8812a2ant_pta_off_on_notify(pBtCoexist, (bBTON == _TRUE) ? BTC_BT_ON : BTC_BT_OFF);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8814A\n\telse if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8814a2ant_pta_off_on_notify(pBtCoexist, (bBTON == _TRUE) ? BTC_BT_ON : BTC_BT_OFF);\n\t}\n#endif\n}\n\nvoid EXhalbtcoutsrc_set_rfe_type(u8 type)\n{\n\tGLBtCoexist.board_info.rfe_type= type;\n}\n\n#ifdef CONFIG_RF4CE_COEXIST\nvoid EXhalbtcoutsrc_set_rf4ce_link_state(u8 state)\n{\n\tGLBtCoexist.rf4ce_info.link_state = state;\n}\n\nu8 EXhalbtcoutsrc_get_rf4ce_link_state(void)\n{\n\treturn GLBtCoexist.rf4ce_info.link_state;\n}\n#endif\n\nvoid EXhalbtcoutsrc_switchband_notify(struct btc_coexist *pBtCoexist, u8 type)\n{\n\tif(!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))\n\t\treturn;\n\t\n\tif(pBtCoexist->manual_control)\n\t\treturn;\n\n\t/* Driver should guarantee that the HW status isn't in low power mode */\n\t/* halbtcoutsrc_LeaveLowPower(pBtCoexist); */\n#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)\n\trtw_btc_ex_switchband_notify(pBtCoexist, type);\n#else\n\n\tif(IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {\n#ifdef CONFIG_RTL8822B\n\t\tif(pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8822b1ant_switchband_notify(pBtCoexist, type);\n\t\telse if(pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8822b2ant_switchband_notify(pBtCoexist, type);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8821c2ant_switchband_notify(pBtCoexist, type);\n\t\telse if (pBtCoexist->board_info.btdm_ant_num == 1)\n\t\t\tex_halbtc8821c1ant_switchband_notify(pBtCoexist, type);\n\t}\n#endif\n\n#ifdef CONFIG_RTL8814A\n\telse if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {\n\t\tif (pBtCoexist->board_info.btdm_ant_num == 2)\n\t\t\tex_halbtc8814a2ant_switchband_notify(pBtCoexist, type);\n\t}\n#endif\n\n#endif\n\n\t/* halbtcoutsrc_NormalLowPower(pBtCoexist); */\n}\n\nu8 EXhalbtcoutsrc_rate_id_to_btc_rate_id(u8 rate_id)\n{\n\tu8 btc_rate_id = BTC_UNKNOWN;\n\n\tswitch (rate_id) {\n\t\t/* CCK rates */\n\t\tcase DESC_RATE1M:\n\t\t\tbtc_rate_id = BTC_CCK_1;\n\t\t\tbreak;\n\t\tcase DESC_RATE2M:\n\t\t\tbtc_rate_id = BTC_CCK_2;\n\t\t\tbreak;\n\t\tcase DESC_RATE5_5M:\n\t\t\tbtc_rate_id = BTC_CCK_5_5;\n\t\t\tbreak;\n\t\tcase DESC_RATE11M:\n\t\t\tbtc_rate_id = BTC_CCK_11;\n\t\t\tbreak;\n\n\t\t/* OFDM rates */\n\t\tcase DESC_RATE6M:\n\t\t\tbtc_rate_id = BTC_OFDM_6;\n\t\t\tbreak;\n\t\tcase DESC_RATE9M:\n\t\t\tbtc_rate_id = BTC_OFDM_9;\n\t\t\tbreak;\n\t\tcase DESC_RATE12M:\n\t\t\tbtc_rate_id = BTC_OFDM_12;\n\t\t\tbreak;\n\t\tcase DESC_RATE18M:\n\t\t\tbtc_rate_id = BTC_OFDM_18;\n\t\t\tbreak;\n\t\tcase DESC_RATE24M:\n\t\t\tbtc_rate_id = BTC_OFDM_24;\n\t\t\tbreak;\n\t\tcase DESC_RATE36M:\n\t\t\tbtc_rate_id = BTC_OFDM_36;\n\t\t\tbreak;\n\t\tcase DESC_RATE48M:\n\t\t\tbtc_rate_id = BTC_OFDM_48;\n\t\t\tbreak;\n\t\tcase DESC_RATE54M:\n\t\t\tbtc_rate_id = BTC_OFDM_54;\n\t\t\tbreak;\n\n\t\t/* MCS rates */\n\t\tcase DESC_RATEMCS0:\n\t\t\tbtc_rate_id = BTC_MCS_0;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS1:\n\t\t\tbtc_rate_id = BTC_MCS_1;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS2:\n\t\t\tbtc_rate_id = BTC_MCS_2;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS3:\n\t\t\tbtc_rate_id = BTC_MCS_3;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS4:\n\t\t\tbtc_rate_id = BTC_MCS_4;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS5:\n\t\t\tbtc_rate_id = BTC_MCS_5;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS6:\n\t\t\tbtc_rate_id = BTC_MCS_6;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS7:\n\t\t\tbtc_rate_id = BTC_MCS_7;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS8:\n\t\t\tbtc_rate_id = BTC_MCS_8;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS9:\n\t\t\tbtc_rate_id = BTC_MCS_9;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS10:\n\t\t\tbtc_rate_id = BTC_MCS_10;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS11:\n\t\t\tbtc_rate_id = BTC_MCS_11;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS12:\n\t\t\tbtc_rate_id = BTC_MCS_12;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS13:\n\t\t\tbtc_rate_id = BTC_MCS_13;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS14:\n\t\t\tbtc_rate_id = BTC_MCS_14;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS15:\n\t\t\tbtc_rate_id = BTC_MCS_15;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS16:\n\t\t\tbtc_rate_id = BTC_MCS_16;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS17:\n\t\t\tbtc_rate_id = BTC_MCS_17;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS18:\n\t\t\tbtc_rate_id = BTC_MCS_18;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS19:\n\t\t\tbtc_rate_id = BTC_MCS_19;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS20:\n\t\t\tbtc_rate_id = BTC_MCS_20;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS21:\n\t\t\tbtc_rate_id = BTC_MCS_21;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS22:\n\t\t\tbtc_rate_id = BTC_MCS_22;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS23:\n\t\t\tbtc_rate_id = BTC_MCS_23;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS24:\n\t\t\tbtc_rate_id = BTC_MCS_24;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS25:\n\t\t\tbtc_rate_id = BTC_MCS_25;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS26:\n\t\t\tbtc_rate_id = BTC_MCS_26;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS27:\n\t\t\tbtc_rate_id = BTC_MCS_27;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS28:\n\t\t\tbtc_rate_id = BTC_MCS_28;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS29:\n\t\t\tbtc_rate_id = BTC_MCS_29;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS30:\n\t\t\tbtc_rate_id = BTC_MCS_30;\n\t\t\tbreak;\n\t\tcase DESC_RATEMCS31:\n\t\t\tbtc_rate_id = BTC_MCS_31;\n\t\t\tbreak;\n\t\t\t\n\t\tcase DESC_RATEVHTSS1MCS0:\n\t\t\tbtc_rate_id = BTC_VHT_1SS_MCS_0;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS1MCS1:\n\t\t\tbtc_rate_id = BTC_VHT_1SS_MCS_1;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS1MCS2:\n\t\t\tbtc_rate_id = BTC_VHT_1SS_MCS_2;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS1MCS3:\n\t\t\tbtc_rate_id = BTC_VHT_1SS_MCS_3;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS1MCS4:\n\t\t\tbtc_rate_id = BTC_VHT_1SS_MCS_4;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS1MCS5:\n\t\t\tbtc_rate_id = BTC_VHT_1SS_MCS_5;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS1MCS6:\n\t\t\tbtc_rate_id = BTC_VHT_1SS_MCS_6;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS1MCS7:\n\t\t\tbtc_rate_id = BTC_VHT_1SS_MCS_7;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS1MCS8:\n\t\t\tbtc_rate_id = BTC_VHT_1SS_MCS_8;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS1MCS9:\n\t\t\tbtc_rate_id = BTC_VHT_1SS_MCS_9;\n\t\t\tbreak;\n\n\t\tcase DESC_RATEVHTSS2MCS0:\n\t\t\tbtc_rate_id = BTC_VHT_2SS_MCS_0;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS2MCS1:\n\t\t\tbtc_rate_id = BTC_VHT_2SS_MCS_1;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS2MCS2:\n\t\t\tbtc_rate_id = BTC_VHT_2SS_MCS_2;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS2MCS3:\n\t\t\tbtc_rate_id = BTC_VHT_2SS_MCS_3;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS2MCS4:\n\t\t\tbtc_rate_id = BTC_VHT_2SS_MCS_4;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS2MCS5:\n\t\t\tbtc_rate_id = BTC_VHT_2SS_MCS_5;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS2MCS6:\n\t\t\tbtc_rate_id = BTC_VHT_2SS_MCS_6;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS2MCS7:\n\t\t\tbtc_rate_id = BTC_VHT_2SS_MCS_7;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS2MCS8:\n\t\t\tbtc_rate_id = BTC_VHT_2SS_MCS_8;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS2MCS9:\n\t\t\tbtc_rate_id = BTC_VHT_2SS_MCS_9;\n\t\t\tbreak;\n\n\t\tcase DESC_RATEVHTSS3MCS0:\n\t\t\tbtc_rate_id = BTC_VHT_3SS_MCS_0;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS3MCS1:\n\t\t\tbtc_rate_id = BTC_VHT_3SS_MCS_1;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS3MCS2:\n\t\t\tbtc_rate_id = BTC_VHT_3SS_MCS_2;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS3MCS3:\n\t\t\tbtc_rate_id = BTC_VHT_3SS_MCS_3;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS3MCS4:\n\t\t\tbtc_rate_id = BTC_VHT_3SS_MCS_4;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS3MCS5:\n\t\t\tbtc_rate_id = BTC_VHT_3SS_MCS_5;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS3MCS6:\n\t\t\tbtc_rate_id = BTC_VHT_3SS_MCS_6;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS3MCS7:\n\t\t\tbtc_rate_id = BTC_VHT_3SS_MCS_7;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS3MCS8:\n\t\t\tbtc_rate_id = BTC_VHT_3SS_MCS_8;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS3MCS9:\n\t\t\tbtc_rate_id = BTC_VHT_3SS_MCS_9;\n\t\t\tbreak;\n\n\t\tcase DESC_RATEVHTSS4MCS0:\n\t\t\tbtc_rate_id = BTC_VHT_4SS_MCS_0;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS4MCS1:\n\t\t\tbtc_rate_id = BTC_VHT_4SS_MCS_1;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS4MCS2:\n\t\t\tbtc_rate_id = BTC_VHT_4SS_MCS_2;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS4MCS3:\n\t\t\tbtc_rate_id = BTC_VHT_4SS_MCS_3;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS4MCS4:\n\t\t\tbtc_rate_id = BTC_VHT_4SS_MCS_4;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS4MCS5:\n\t\t\tbtc_rate_id = BTC_VHT_4SS_MCS_5;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS4MCS6:\n\t\t\tbtc_rate_id = BTC_VHT_4SS_MCS_6;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS4MCS7:\n\t\t\tbtc_rate_id = BTC_VHT_4SS_MCS_7;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS4MCS8:\n\t\t\tbtc_rate_id = BTC_VHT_4SS_MCS_8;\n\t\t\tbreak;\n\t\tcase DESC_RATEVHTSS4MCS9:\n\t\t\tbtc_rate_id = BTC_VHT_4SS_MCS_9;\n\t\t\tbreak;\n\t}\n\t\n\treturn btc_rate_id;\n}\n\n/*\n * Description:\n *\tRun BT-Coexist mechansim or not\n *\n */\nvoid hal_btcoex_SetBTCoexist(PADAPTER padapter, u8 bBtExist)\n{\n\tPHAL_DATA_TYPE\tpHalData;\n\n\n\tpHalData = GET_HAL_DATA(padapter);\n\tpHalData->bt_coexist.bBtExist = bBtExist;\n}\n\n/*\n * Dewcription:\n *\tCheck is co-exist mechanism enabled or not\n *\n * Return:\n *\t_TRUE\tEnable BT co-exist mechanism\n *\t_FALSE\tDisable BT co-exist mechanism\n */\nu8 hal_btcoex_IsBtExist(PADAPTER padapter)\n{\n\tPHAL_DATA_TYPE\tpHalData;\n\n\n\tpHalData = GET_HAL_DATA(padapter);\n\treturn pHalData->bt_coexist.bBtExist;\n}\n\nu8 hal_btcoex_IsBtDisabled(PADAPTER padapter)\n{\n\tif (!hal_btcoex_IsBtExist(padapter))\n\t\treturn _TRUE;\n\n\tif (GLBtCoexist.bt_info.bt_disabled)\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\n\nvoid hal_btcoex_SetChipType(PADAPTER padapter, u8 chipType)\n{\n\tPHAL_DATA_TYPE\tpHalData;\n\n\tpHalData = GET_HAL_DATA(padapter);\n\tpHalData->bt_coexist.btChipType = chipType;\n}\n\nvoid hal_btcoex_SetPgAntNum(PADAPTER padapter, u8 antNum)\n{\n\tPHAL_DATA_TYPE\tpHalData;\n\n\tpHalData = GET_HAL_DATA(padapter);\n\n\tpHalData->bt_coexist.btTotalAntNum = antNum;\n}\n\nu8 hal_btcoex_Initialize(PADAPTER padapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tu8 ret;\n\n\t_rtw_memset(&GLBtCoexist, 0, sizeof(GLBtCoexist));\n\n\tret = EXhalbtcoutsrc_InitlizeVariables((void *)padapter);\n\n\treturn ret;\n}\n\nvoid hal_btcoex_PowerOnSetting(PADAPTER padapter)\n{\n\tEXhalbtcoutsrc_PowerOnSetting(&GLBtCoexist);\n}\n\nvoid hal_btcoex_AntInfoSetting(PADAPTER padapter)\n{\n\thal_btcoex_SetBTCoexist(padapter, rtw_btcoex_get_bt_coexist(padapter));\n\thal_btcoex_SetChipType(padapter, rtw_btcoex_get_chip_type(padapter));\n\thal_btcoex_SetPgAntNum(padapter, rtw_btcoex_get_pg_ant_num(padapter));\n\n\tEXhalbtcoutsrc_AntInfoSetting(padapter);\n}\n\nvoid hal_btcoex_PowerOffSetting(PADAPTER padapter)\n{\n\t/* Clear the WiFi on/off bit in scoreboard reg. if necessary */\n\tif (IS_HARDWARE_TYPE_8703B(padapter) || IS_HARDWARE_TYPE_8723D(padapter)\n\t\t|| IS_HARDWARE_TYPE_8821C(padapter) || IS_HARDWARE_TYPE_8822B(padapter)\n\t\t|| IS_HARDWARE_TYPE_8822C(padapter))\n\t\trtw_write16(padapter, 0xaa, 0x8000);\n}\n\nvoid hal_btcoex_PreLoadFirmware(PADAPTER padapter)\n{\n\tEXhalbtcoutsrc_PreLoadFirmware(&GLBtCoexist);\n}\n\nvoid hal_btcoex_InitHwConfig(PADAPTER padapter, u8 bWifiOnly)\n{\n\tif (!hal_btcoex_IsBtExist(padapter))\n\t\treturn;\n\n\tEXhalbtcoutsrc_init_hw_config(&GLBtCoexist, bWifiOnly);\n\tEXhalbtcoutsrc_init_coex_dm(&GLBtCoexist);\n}\n\nvoid hal_btcoex_IpsNotify(PADAPTER padapter, u8 type)\n{\n\tEXhalbtcoutsrc_ips_notify(&GLBtCoexist, type);\n}\n\nvoid hal_btcoex_LpsNotify(PADAPTER padapter, u8 type)\n{\n\tEXhalbtcoutsrc_lps_notify(&GLBtCoexist, type);\n}\n\nvoid hal_btcoex_ScanNotify(PADAPTER padapter, u8 type)\n{\n\tEXhalbtcoutsrc_scan_notify(&GLBtCoexist, type);\n}\n\nvoid hal_btcoex_ConnectNotify(PADAPTER padapter, u8 action)\n{\n\tu8 assoType = 0;\n\tu8 is_5g_band = _FALSE;\n\n\tis_5g_band = (padapter->mlmeextpriv.cur_channel > 14) ? _TRUE : _FALSE;\n\n\tif (action == _TRUE) {\n\t\tif (is_5g_band == _TRUE)\n\t\t\tassoType = BTC_ASSOCIATE_5G_START;\n\t\telse\n\t\t\tassoType = BTC_ASSOCIATE_START;\n\t}\n\telse {\n\t\tif (is_5g_band == _TRUE)\n\t\t\tassoType = BTC_ASSOCIATE_5G_FINISH;\n\t\telse\n\t\t\tassoType = BTC_ASSOCIATE_FINISH;\n\t}\n\t\n\tEXhalbtcoutsrc_connect_notify(&GLBtCoexist, assoType);\n}\n\nvoid hal_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus)\n{\n\tEXhalbtcoutsrc_media_status_notify(&GLBtCoexist, mediaStatus);\n}\n\nvoid hal_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType)\n{\n\tEXhalbtcoutsrc_specific_packet_notify(&GLBtCoexist, pktType);\n}\n\nvoid hal_btcoex_IQKNotify(PADAPTER padapter, u8 state)\n{\n\tGLBtcWiFiInIQKState = state;\n}\n\nvoid hal_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)\n{\n\tif (GLBtcWiFiInIQKState == _TRUE)\n\t\treturn;\n\n\tEXhalbtcoutsrc_bt_info_notify(&GLBtCoexist, tmpBuf, length);\n}\n\nvoid hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)\n{\n\tu8 extid, status, len, seq;\n\n\n\tif (GLBtcBtMpRptWait == _FALSE)\n\t\treturn;\n\n\tif ((length < 3) || (!tmpBuf))\n\t\treturn;\n\n\textid = tmpBuf[0];\n\t/* not response from BT FW then exit*/\n\tswitch (extid) {\n\tcase C2H_WIFI_FW_ACTIVE_RSP:\n\t\tGLBtcBtMpRptWiFiOK = _TRUE;\n\t\tbreak;\n\n\tcase C2H_TRIG_BY_BT_FW:\n\t\tGLBtcBtMpRptBTOK = _TRUE;\n\n\t\tstatus = tmpBuf[1] & 0xF;\n\t\tlen = length - 3;\n\t\tseq = tmpBuf[2] >> 4;\n\n\t\tGLBtcBtMpRptSeq = seq;\n\t\tGLBtcBtMpRptStatus = status;\n\t\t_rtw_memcpy(GLBtcBtMpRptRsp, tmpBuf + 3, len);\n\t\tGLBtcBtMpRptRspSize = len;\n\n\t\tbreak;\n\n\tdefault:\n\t\treturn;\n\t}\n\n\tif ((GLBtcBtMpRptWiFiOK == _TRUE) && (GLBtcBtMpRptBTOK == _TRUE)) {\n\t\tGLBtcBtMpRptWait = _FALSE;\n\t\t_cancel_timer_ex(&GLBtcBtMpOperTimer);\n\t\t_rtw_up_sema(&GLBtcBtMpRptSema);\n\t}\n}\n\nvoid hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state)\n{\n\tswitch (state) {\n\tcase BTCOEX_SUSPEND_STATE_SUSPEND:\n\t\tEXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP);\n\t\tbreak;\n\tcase BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT:\n\t\t/* should switch to \"#if 1\" once all ICs' coex. revision are upgraded to support the KEEP_ANT case */\n#if 0\n\t\tEXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP_KEEP_ANT);\n#else\n\t\tEXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP);\n\t\tEXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP_KEEP_ANT);\n#endif\n\t\tbreak;\n\tcase BTCOEX_SUSPEND_STATE_RESUME:\n#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\t\t/* re-download FW after resume, inform WL FW port number */\n\t\trtw_hal_set_wifi_btc_port_id_cmd(GLBtCoexist.Adapter);\n#endif\n\t\tEXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_WAKE_UP);\n\t\tbreak;\n\t}\n}\n\nvoid hal_btcoex_HaltNotify(PADAPTER padapter, u8 do_halt)\n{\n\tif (do_halt == 1)\n\t\tEXhalbtcoutsrc_halt_notify(&GLBtCoexist);\n\n\tGLBtCoexist.bBinded = _FALSE;\n\tGLBtCoexist.Adapter = NULL;\n}\n\nvoid hal_btcoex_SwitchBtTRxMask(PADAPTER padapter)\n{\n\tEXhalbtcoutsrc_SwitchBtTRxMask(&GLBtCoexist);\n}\n\nvoid hal_btcoex_Hanlder(PADAPTER padapter)\n{\n\tu32\tbt_patch_ver;\n\n\tEXhalbtcoutsrc_periodical(&GLBtCoexist);\n\n\tif (GLBtCoexist.bt_info.bt_get_fw_ver == 0) {\n\t\tGLBtCoexist.btc_get(&GLBtCoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);\n\t\tGLBtCoexist.bt_info.bt_get_fw_ver = bt_patch_ver;\n\t}\n}\n\ns32 hal_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter)\n{\n\treturn (s32)GLBtCoexist.bt_info.reject_agg_pkt;\n}\n\ns32 hal_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter)\n{\n\treturn (s32)GLBtCoexist.bt_info.bt_ctrl_agg_buf_size;\n}\n\nu32 hal_btcoex_GetAMPDUSize(PADAPTER padapter)\n{\n\treturn (u32)GLBtCoexist.bt_info.agg_buf_size;\n}\n\nvoid hal_btcoex_SetManualControl(PADAPTER padapter, u8 bmanual)\n{\n\tGLBtCoexist.manual_control = bmanual;\n}\n\nu8 hal_btcoex_1Ant(PADAPTER padapter)\n{\n\tif (hal_btcoex_IsBtExist(padapter) == _FALSE)\n\t\treturn _FALSE;\n\n\tif (GLBtCoexist.board_info.btdm_ant_num == 1)\n\t\treturn _TRUE;\n\n\treturn _FALSE;\n}\n\nu8 hal_btcoex_IsBtControlLps(PADAPTER padapter)\n{\n\tif (GLBtCoexist.bdontenterLPS == _TRUE)\n\t\treturn _TRUE;\n\t\n\tif (hal_btcoex_IsBtExist(padapter) == _FALSE)\n\t\treturn _FALSE;\n\n\tif (GLBtCoexist.bt_info.bt_disabled)\n\t\treturn _FALSE;\n\n\tif (GLBtCoexist.bt_info.bt_ctrl_lps)\n\t\treturn _TRUE;\n\n\treturn _FALSE;\n}\n\nu8 hal_btcoex_IsLpsOn(PADAPTER padapter)\n{\n\tif (GLBtCoexist.bdontenterLPS == _TRUE)\n\t\treturn _FALSE;\n\t\n\tif (hal_btcoex_IsBtExist(padapter) == _FALSE)\n\t\treturn _FALSE;\n\n\tif (GLBtCoexist.bt_info.bt_disabled)\n\t\treturn _FALSE;\n\n\tif (GLBtCoexist.bt_info.bt_lps_on)\n\t\treturn _TRUE;\n\n\treturn _FALSE;\n}\n\nu8 hal_btcoex_RpwmVal(PADAPTER padapter)\n{\n\treturn GLBtCoexist.bt_info.rpwm_val;\n}\n\nu8 hal_btcoex_LpsVal(PADAPTER padapter)\n{\n\treturn GLBtCoexist.bt_info.lps_val;\n}\n\nu32 hal_btcoex_GetRaMask(PADAPTER padapter)\n{\n\tif (!hal_btcoex_IsBtExist(padapter))\n\t\treturn 0;\n\n\tif (GLBtCoexist.bt_info.bt_disabled)\n\t\treturn 0;\n\n\t/* Modify by YiWei , suggest by Cosa and Jenyu\n\t * Remove the limit antenna number , because 2 antenna case (ex: 8192eu)also want to get BT coex report rate mask.\n\t */\n\t/*if (GLBtCoexist.board_info.btdm_ant_num != 1)\n\t\treturn 0;*/\n\n\treturn GLBtCoexist.bt_info.ra_mask;\n}\n\nu8 hal_btcoex_query_reduced_wl_pwr_lvl(PADAPTER padapter)\n{\n\treturn GLBtCoexist.coex_dm.cur_wl_pwr_lvl;\n}\n\nvoid hal_btcoex_set_reduced_wl_pwr_lvl(PADAPTER padapter, u8 val)\n{\n\tGLBtCoexist.coex_dm.cur_wl_pwr_lvl = val;\n}\n\nvoid hal_btcoex_do_reduce_wl_pwr_lvl(PADAPTER padapter)\n{\n\thalbtcoutsrc_reduce_wl_tx_power(&GLBtCoexist, 0);\n}\n\nvoid hal_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen)\n{\n\n\t_rtw_memcpy(GLBtCoexist.pwrModeVal, pCmdBuf, cmdLen);\n}\n\nvoid hal_btcoex_DisplayBtCoexInfo(PADAPTER padapter, u8 *pbuf, u32 bufsize)\n{\n\tPBTCDBGINFO pinfo;\n\n\n\tpinfo = &GLBtcDbgInfo;\n\tDBG_BT_INFO_INIT(pinfo, pbuf, bufsize);\n\tEXhalbtcoutsrc_DisplayBtCoexInfo(&GLBtCoexist);\n\tDBG_BT_INFO_INIT(pinfo, NULL, 0);\n}\n\nvoid hal_btcoex_SetDBG(PADAPTER padapter, u32 *pDbgModule)\n{\n\tu32 i;\n\n\n\tif (NULL == pDbgModule)\n\t\treturn;\n\n\tfor (i = 0; i < COMP_MAX; i++)\n\t\tGLBtcDbgType[i] = pDbgModule[i];\n}\n\nu32 hal_btcoex_GetDBG(PADAPTER padapter, u8 *pStrBuf, u32 bufSize)\n{\n\ts32 count;\n\tu8 *pstr;\n\tu32 leftSize;\n\n\n\tif ((NULL == pStrBuf) || (0 == bufSize))\n\t\treturn 0;\n\n\tcount = 0;\n\tpstr = pStrBuf;\n\tleftSize = bufSize;\n\t/*\tRTW_INFO(FUNC_ADPT_FMT \": bufsize=%d\\n\", FUNC_ADPT_ARG(padapter), bufSize); */\n\n\tcount = rtw_sprintf(pstr, leftSize, \"#define DBG\\t%d\\n\", DBG);\n\tif ((count < 0) || (count >= leftSize))\n\t\tgoto exit;\n\tpstr += count;\n\tleftSize -= count;\n\n\tcount = rtw_sprintf(pstr, leftSize, \"BTCOEX Debug Setting:\\n\");\n\tif ((count < 0) || (count >= leftSize))\n\t\tgoto exit;\n\tpstr += count;\n\tleftSize -= count;\n\n\tcount = rtw_sprintf(pstr, leftSize,\n\t\t\t    \"COMP_COEX: 0x%08X\\n\\n\",\n\t\t\t    GLBtcDbgType[COMP_COEX]);\n\tif ((count < 0) || (count >= leftSize))\n\t\tgoto exit;\n\tpstr += count;\n\tleftSize -= count;\n\n#if 0\n\tcount = rtw_sprintf(pstr, leftSize, \"INTERFACE Debug Setting Definition:\\n\");\n\tif ((count < 0) || (count >= leftSize))\n\t\tgoto exit;\n\tpstr += count;\n\tleftSize -= count;\n\tcount = rtw_sprintf(pstr, leftSize, \"\\tbit[0]=%d for INTF_INIT\\n\",\n\t\t    GLBtcDbgType[BTC_MSG_INTERFACE] & INTF_INIT ? 1 : 0);\n\tif ((count < 0) || (count >= leftSize))\n\t\tgoto exit;\n\tpstr += count;\n\tleftSize -= count;\n\tcount = rtw_sprintf(pstr, leftSize, \"\\tbit[2]=%d for INTF_NOTIFY\\n\\n\",\n\t\t    GLBtcDbgType[BTC_MSG_INTERFACE] & INTF_NOTIFY ? 1 : 0);\n\tif ((count < 0) || (count >= leftSize))\n\t\tgoto exit;\n\tpstr += count;\n\tleftSize -= count;\n\n\tcount = rtw_sprintf(pstr, leftSize, \"ALGORITHM Debug Setting Definition:\\n\");\n\tif ((count < 0) || (count >= leftSize))\n\t\tgoto exit;\n\tpstr += count;\n\tleftSize -= count;\n\tcount = rtw_sprintf(pstr, leftSize, \"\\tbit[0]=%d for BT_RSSI_STATE\\n\",\n\t\tGLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_BT_RSSI_STATE ? 1 : 0);\n\tif ((count < 0) || (count >= leftSize))\n\t\tgoto exit;\n\tpstr += count;\n\tleftSize -= count;\n\tcount = rtw_sprintf(pstr, leftSize, \"\\tbit[1]=%d for WIFI_RSSI_STATE\\n\",\n\t\tGLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_WIFI_RSSI_STATE ? 1 : 0);\n\tif ((count < 0) || (count >= leftSize))\n\t\tgoto exit;\n\tpstr += count;\n\tleftSize -= count;\n\tcount = rtw_sprintf(pstr, leftSize, \"\\tbit[2]=%d for BT_MONITOR\\n\",\n\t\t    GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_BT_MONITOR ? 1 : 0);\n\tif ((count < 0) || (count >= leftSize))\n\t\tgoto exit;\n\tpstr += count;\n\tleftSize -= count;\n\tcount = rtw_sprintf(pstr, leftSize, \"\\tbit[3]=%d for TRACE\\n\",\n\t\t    GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE ? 1 : 0);\n\tif ((count < 0) || (count >= leftSize))\n\t\tgoto exit;\n\tpstr += count;\n\tleftSize -= count;\n\tcount = rtw_sprintf(pstr, leftSize, \"\\tbit[4]=%d for TRACE_FW\\n\",\n\t\t    GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_FW ? 1 : 0);\n\tif ((count < 0) || (count >= leftSize))\n\t\tgoto exit;\n\tpstr += count;\n\tleftSize -= count;\n\tcount = rtw_sprintf(pstr, leftSize, \"\\tbit[5]=%d for TRACE_FW_DETAIL\\n\",\n\t\tGLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_FW_DETAIL ? 1 : 0);\n\tif ((count < 0) || (count >= leftSize))\n\t\tgoto exit;\n\tpstr += count;\n\tleftSize -= count;\n\tcount = rtw_sprintf(pstr, leftSize, \"\\tbit[6]=%d for TRACE_FW_EXEC\\n\",\n\t\tGLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_FW_EXEC ? 1 : 0);\n\tif ((count < 0) || (count >= leftSize))\n\t\tgoto exit;\n\tpstr += count;\n\tleftSize -= count;\n\tcount = rtw_sprintf(pstr, leftSize, \"\\tbit[7]=%d for TRACE_SW\\n\",\n\t\t    GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_SW ? 1 : 0);\n\tif ((count < 0) || (count >= leftSize))\n\t\tgoto exit;\n\tpstr += count;\n\tleftSize -= count;\n\tcount = rtw_sprintf(pstr, leftSize, \"\\tbit[8]=%d for TRACE_SW_DETAIL\\n\",\n\t\tGLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_SW_DETAIL ? 1 : 0);\n\tif ((count < 0) || (count >= leftSize))\n\t\tgoto exit;\n\tpstr += count;\n\tleftSize -= count;\n\tcount = rtw_sprintf(pstr, leftSize, \"\\tbit[9]=%d for TRACE_SW_EXEC\\n\",\n\t\tGLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_SW_EXEC ? 1 : 0);\n\tif ((count < 0) || (count >= leftSize))\n\t\tgoto exit;\n\tpstr += count;\n\tleftSize -= count;\n#endif\n\nexit:\n\tcount = pstr - pStrBuf;\n\t/*\tRTW_INFO(FUNC_ADPT_FMT \": usedsize=%d\\n\", FUNC_ADPT_ARG(padapter), count); */\n\n\treturn count;\n}\n\nu8 hal_btcoex_IncreaseScanDeviceNum(PADAPTER padapter)\n{\n\tif (!hal_btcoex_IsBtExist(padapter))\n\t\treturn _FALSE;\n\n\tif (GLBtCoexist.bt_info.increase_scan_dev_num)\n\t\treturn _TRUE;\n\n\treturn _FALSE;\n}\n\nu8 hal_btcoex_IsBtLinkExist(PADAPTER padapter)\n{\n\tif (GLBtCoexist.bt_link_info.bt_link_exist)\n\t\treturn _TRUE;\n\n\treturn _FALSE;\n}\n\nvoid hal_btcoex_SetBtPatchVersion(PADAPTER padapter, u16 btHciVer, u16 btPatchVer)\n{\n\tEXhalbtcoutsrc_SetBtPatchVersion(btHciVer, btPatchVer);\n}\n\nvoid hal_btcoex_SetHciVersion(PADAPTER padapter, u16 hciVersion)\n{\n\tEXhalbtcoutsrc_SetHciVersion(hciVersion);\n}\n\nvoid hal_btcoex_StackUpdateProfileInfo(void)\n{\n\tEXhalbtcoutsrc_StackUpdateProfileInfo();\n}\n\nvoid hal_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON)\n{\n\tex_halbtcoutsrc_pta_off_on_notify(&GLBtCoexist, bBTON);\n}\n\n/*\n *\tDescription:\n *\tSetting BT coex antenna isolation type .\n *\tcoex mechanisn/ spital stream/ best throughput\n *\tanttype = 0\t,\tPSTDMA\t/\t2SS\t/\t0.5T\t,\tbad isolation , WiFi/BT ANT Distance<15cm , (<20dB) for 2,3 antenna\n *\tanttype = 1\t,\tPSTDMA\t/\t1SS\t/\t0.5T\t,\tnormal isolaiton , 50cm>WiFi/BT ANT Distance>15cm , (>20dB) for 2 antenna\n *\tanttype = 2\t,\tTDMA\t/\t2SS\t/\tT ,\t\tnormal isolaiton , 50cm>WiFi/BT ANT Distance>15cm , (>20dB) for 3 antenna\n *\tanttype = 3\t,\tno TDMA\t/\t1SS\t/\t0.5T\t,\tgood isolation , WiFi/BT ANT Distance >50cm , (>40dB) for 2 antenna\n *\tanttype = 4\t,\tno TDMA\t/\t2SS\t/\tT ,\t\tgood isolation , WiFi/BT ANT Distance >50cm , (>40dB) for 3 antenna\n *\twifi only throughput ~ T\n *\twifi/BT share one antenna with SPDT\n */\nvoid hal_btcoex_SetAntIsolationType(PADAPTER padapter, u8 anttype)\n{\n\tPHAL_DATA_TYPE pHalData;\n\tPBTC_COEXIST\tpBtCoexist = &GLBtCoexist;\n\n\t/*RTW_INFO(\"####%s , anttype = %d  , %d\\n\" , __func__ , anttype , __LINE__); */\n\tpHalData = GET_HAL_DATA(padapter);\n\n\n\tpHalData->bt_coexist.btAntisolation = anttype;\n\n\tswitch (pHalData->bt_coexist.btAntisolation) {\n\tcase 0:\n\t\tpBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_0;\n\t\tbreak;\n\tcase 1:\n\t\tpBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_1;\n\t\tbreak;\n\tcase 2:\n\t\tpBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_2;\n\t\tbreak;\n\tcase 3:\n\t\tpBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_3;\n\t\tbreak;\n\tcase 4:\n\t\tpBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_4;\n\t\tbreak;\n\t}\n\n}\n\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\nint\nhal_btcoex_ParseAntIsolationConfigFile(\n\tPADAPTER\t\tAdapter,\n\tchar\t\t\t*buffer\n)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(Adapter);\n\tu32\ti = 0 , j = 0;\n\tchar\t*szLine , *ptmp;\n\tint rtStatus = _SUCCESS;\n\tchar param_value_string[10];\n\tu8 param_value;\n\tu8 anttype = 4;\n\n\tu8 ant_num = 3 , ant_distance = 50 , rfe_type = 1;\n\n\ttypedef struct ant_isolation {\n\t\tchar *param_name;  /* antenna isolation config parameter name */\n\t\tu8 *value; /* antenna isolation config parameter value */\n\t} ANT_ISOLATION;\n\n\tANT_ISOLATION ant_isolation_param[] = {\n\t\t{\"ANT_NUMBER\" , &ant_num},\n\t\t{\"ANT_DISTANCE\" , &ant_distance},\n\t\t{\"RFE_TYPE\" , &rfe_type},\n\t\t{NULL , 0}\n\t};\n\n\n\n\t/* RTW_INFO(\"===>Hal_ParseAntIsolationConfigFile()\\n\" ); */\n\n\tptmp = buffer;\n\tfor (szLine = GetLineFromBuffer(ptmp) ; szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {\n\t\t/* skip comment */\n\t\tif (IsCommentString(szLine))\n\t\t\tcontinue;\n\n\t\t/* RTW_INFO(\"%s : szLine = %s , strlen(szLine) = %d\\n\" , __func__ , szLine , strlen(szLine));*/\n\t\tfor (j = 0 ; ant_isolation_param[j].param_name != NULL ; j++) {\n\t\t\tif (strstr(szLine , ant_isolation_param[j].param_name) != NULL) {\n\t\t\t\ti = 0;\n\t\t\t\twhile (i < strlen(szLine)) {\n\t\t\t\t\tif (szLine[i] != '\"')\n\t\t\t\t\t\t++i;\n\t\t\t\t\telse {\n\t\t\t\t\t\t/* skip only has one \" */\n\t\t\t\t\t\tif (strpbrk(szLine , \"\\\"\") == strrchr(szLine , '\"')) {\n\t\t\t\t\t\t\tRTW_INFO(\"Fail to parse parameters , format error!\\n\");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t}\n\t\t\t\t\t\t_rtw_memset((void *)param_value_string , 0 , 10);\n\t\t\t\t\t\tif (!ParseQualifiedString(szLine , &i , param_value_string , '\"' , '\"')) {\n\t\t\t\t\t\t\tRTW_INFO(\"Fail to parse parameters\\n\");\n\t\t\t\t\t\t\treturn _FAIL;\n\t\t\t\t\t\t} else if (!GetU1ByteIntegerFromStringInDecimal(param_value_string , ant_isolation_param[j].value))\n\t\t\t\t\t\t\tRTW_INFO(\"Fail to GetU1ByteIntegerFromStringInDecimal\\n\");\n\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t/* YiWei 20140716 , for BT coex antenna isolation control */\n\t/* rfe_type = 0 was SPDT , rfe_type = 1 was coupler */\n\tif (ant_num == 3 && ant_distance >= 50)\n\t\tanttype = 3;\n\telse if (ant_num == 2 && ant_distance >= 50 && rfe_type == 1)\n\t\tanttype = 2;\n\telse if (ant_num == 3 && ant_distance >= 15 && ant_distance < 50)\n\t\tanttype = 2;\n\telse if (ant_num == 2 && ant_distance >= 15 && ant_distance < 50 && rfe_type == 1)\n\t\tanttype = 2;\n\telse if ((ant_num == 2 && ant_distance < 15 && rfe_type == 1) || (ant_num == 3 && ant_distance < 15))\n\t\tanttype = 1;\n\telse if (ant_num == 2 && rfe_type == 0)\n\t\tanttype = 0;\n\telse\n\t\tanttype = 0;\n\n\thal_btcoex_SetAntIsolationType(Adapter, anttype);\n\n\tRTW_INFO(\"%s : ant_num = %d\\n\" , __func__ , ant_num);\n\tRTW_INFO(\"%s : ant_distance = %d\\n\" , __func__ , ant_distance);\n\tRTW_INFO(\"%s : rfe_type = %d\\n\" , __func__ , rfe_type);\n\t/* RTW_INFO(\"<===Hal_ParseAntIsolationConfigFile()\\n\"); */\n\treturn rtStatus;\n}\n\n\nint\nhal_btcoex_AntIsolationConfig_ParaFile(\n\t\tPADAPTER\tAdapter,\n\t\tchar\t\t*pFileName\n)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\n\tint\trlen = 0 , rtStatus = _FAIL;\n\n\t_rtw_memset(pHalData->para_file_buf , 0 , MAX_PARA_FILE_BUF_LEN);\n\n\trtw_get_phy_file_path(Adapter, pFileName);\n\tif (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {\n\t\trlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);\n\t\tif (rlen > 0)\n\t\t\trtStatus = _SUCCESS;\n\t}\n\n\n\tif (rtStatus == _SUCCESS) {\n\t\t/*RTW_INFO(\"%s(): read %s ok\\n\", __func__ , pFileName);*/\n\t\trtStatus = hal_btcoex_ParseAntIsolationConfigFile(Adapter , pHalData->para_file_buf);\n\t} else\n\t\tRTW_INFO(\"%s(): No File %s, Load from *** Array!\\n\" , __func__ , pFileName);\n\n\treturn rtStatus;\n}\n#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */\n\nu16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data)\n{\n\tu16 ret = 0;\n\n\thalbtcoutsrc_LeaveLowPower(&GLBtCoexist);\n\n\tret = halbtcoutsrc_GetBtReg_with_status(&GLBtCoexist, type, addr, data);\n\n\thalbtcoutsrc_NormalLowPower(&GLBtCoexist);\n\n\treturn ret;\n}\n\nu16 hal_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val)\n{\n\tu16 ret = 0;\n\n\thalbtcoutsrc_LeaveLowPower(&GLBtCoexist);\n\n\tret = halbtcoutsrc_SetBtReg(&GLBtCoexist, type, addr, val);\n\n\thalbtcoutsrc_NormalLowPower(&GLBtCoexist);\n\n\treturn ret;\n}\n\nvoid hal_btcoex_set_rfe_type(u8 type)\n{\n\tEXhalbtcoutsrc_set_rfe_type(type);\n}\n\n#ifdef CONFIG_RF4CE_COEXIST\nvoid hal_btcoex_set_rf4ce_link_state(u8 state)\n{\n\tEXhalbtcoutsrc_set_rf4ce_link_state(state);\n}\n\nu8 hal_btcoex_get_rf4ce_link_state(void)\n{\n\treturn EXhalbtcoutsrc_get_rf4ce_link_state();\n}\n#endif /* CONFIG_RF4CE_COEXIST */\n\nvoid hal_btcoex_switchband_notify(u8 under_scan, u8 band_type)\n{\n\tswitch (band_type) {\n\tcase BAND_ON_2_4G:\n\t\tif (under_scan)\n\t\t\tEXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_24G);\n\t\telse\n\t\t\tEXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_24G_NOFORSCAN);\n\t\tbreak;\n\tcase BAND_ON_5G:\n\t\tEXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_5G);\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(\"[BTCOEX] unkown switch band type\\n\");\n\t\tbreak;\n\t}\n}\n\nvoid hal_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length)\n{\n\tEXhalbtcoutsrc_WlFwDbgInfoNotify(&GLBtCoexist, tmpBuf, length);\n}\n\nvoid hal_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id)\n{\n\tEXhalbtcoutsrc_rx_rate_change_notify(&GLBtCoexist, is_data_frame, EXhalbtcoutsrc_rate_id_to_btc_rate_id(rate_id));\n}\n\nu16 hal_btcoex_btset_testode(PADAPTER padapter, u8 type)\n{\n\tu16 ret = 0;\n\n\thalbtcoutsrc_LeaveLowPower(&GLBtCoexist);\n\n\tret = halbtcoutsrc_setbttestmode(&GLBtCoexist, type);\n\n\thalbtcoutsrc_NormalLowPower(&GLBtCoexist);\n\n\treturn ret;\n}\n\n#endif /* CONFIG_BT_COEXIST */\n"
  },
  {
    "path": "hal/hal_btcoex_wifionly.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#include <hal_btcoex_wifionly.h>\n\n#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1)\n\n#include \"btc/mp_precomp.h\"\n\nstruct  wifi_only_cfg GLBtCoexistWifiOnly;\n\nvoid halwifionly_write1byte(void *pwifionlyContext, u32 RegAddr, u8 Data)\n{\n\tstruct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;\n\tPADAPTER\t\tAdapter = pwifionlycfg->Adapter;\n\n\trtw_write8(Adapter, RegAddr, Data);\n}\n\nvoid halwifionly_write2byte(void *pwifionlyContext, u32 RegAddr, u16 Data)\n{\n\tstruct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;\n\tPADAPTER\t\tAdapter = pwifionlycfg->Adapter;\n\n\trtw_write16(Adapter, RegAddr, Data);\n}\n\nvoid halwifionly_write4byte(void *pwifionlyContext, u32 RegAddr, u32 Data)\n{\n\tstruct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;\n\tPADAPTER\t\tAdapter = pwifionlycfg->Adapter;\n\n\trtw_write32(Adapter, RegAddr, Data);\n}\n\nu8 halwifionly_read1byte(void *pwifionlyContext, u32 RegAddr)\n{\n\tstruct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;\n\tPADAPTER\t\tAdapter = pwifionlycfg->Adapter;\n\n\treturn rtw_read8(Adapter, RegAddr);\n}\n\nu16 halwifionly_read2byte(void * pwifionlyContext, u32 RegAddr)\n{\n\tstruct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;\n\tPADAPTER\t\tAdapter = pwifionlycfg->Adapter;\n\n\treturn rtw_read16(Adapter, RegAddr);\n}\n\nu32 halwifionly_read4byte(void *pwifionlyContext, u32 RegAddr)\n{\n\tstruct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;\n\tPADAPTER\t\tAdapter = pwifionlycfg->Adapter;\n\n\treturn rtw_read32(Adapter, RegAddr);\n}\n\nvoid halwifionly_bitmaskwrite1byte(void *pwifionlyContext, u32 regAddr, u8 bitMask, u8 data)\n{\n\tu8 originalValue, bitShift = 0;\n\tu8 i;\n\n\tstruct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;\n\tPADAPTER\t\tAdapter = pwifionlycfg->Adapter;\n\n\tif (bitMask != 0xff) {\n\t\toriginalValue = rtw_read8(Adapter, regAddr);\n\t\tfor (i = 0; i <= 7; i++) {\n\t\t\tif ((bitMask >> i) & 0x1)\n\t\t\t\tbreak;\n\t\t}\n\t\tbitShift = i;\n\t\tdata = ((originalValue) & (~bitMask)) | (((data << bitShift)) & bitMask);\n\t}\n\trtw_write8(Adapter, regAddr, data);\n}\n\nvoid halwifionly_phy_set_rf_reg(void *pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)\n{\n\tstruct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;\n\tPADAPTER\t\tAdapter = pwifionlycfg->Adapter;\n\n\tphy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data);\n}\n\nvoid halwifionly_phy_set_bb_reg(void *pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data)\n{\n\tstruct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;\n\tPADAPTER\t\tAdapter = pwifionlycfg->Adapter;\n\n\tphy_set_bb_reg(Adapter, RegAddr, BitMask, Data);\n}\n\nvoid hal_btcoex_wifionly_switchband_notify(PADAPTER padapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tu8 is_5g = _FALSE;\n\n\tif (pHalData->current_band_type == BAND_ON_5G)\n\t\tis_5g = _TRUE;\n\n\tif (IS_HARDWARE_TYPE_8822B(padapter)) {\n#ifdef CONFIG_RTL8822B\n\t\tex_hal8822b_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(padapter))\n\t\tex_hal8821c_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);\n#endif\n\n#ifdef CONFIG_RTL8822C\n\telse if (IS_HARDWARE_TYPE_8822C(padapter))\n\t\tex_hal8822c_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);\n#endif\n\n}\n\nvoid hal_btcoex_wifionly_scan_notify(PADAPTER padapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tu8 is_5g = _FALSE;\n\n\tif (pHalData->current_band_type == BAND_ON_5G)\n\t\tis_5g = _TRUE;\n\n\tif (IS_HARDWARE_TYPE_8822B(padapter)) {\n#ifdef CONFIG_RTL8822B\n\t\tex_hal8822b_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(padapter))\n\t\tex_hal8821c_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);\n#endif\n\n#ifdef CONFIG_RTL8822C\n\telse if (IS_HARDWARE_TYPE_8822C(padapter))\n\t\tex_hal8822c_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);\n#endif\n}\n\nvoid hal_btcoex_wifionly_connect_notify(PADAPTER padapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tu8 is_5g = _FALSE;\n\n\tif (pHalData->current_band_type == BAND_ON_5G)\n\t\tis_5g = _TRUE;\n\n\tif (IS_HARDWARE_TYPE_8822B(padapter)) {\n#ifdef CONFIG_RTL8822B\n\t\tex_hal8822b_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(padapter))\n\t\tex_hal8821c_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);\n#endif\n\n#ifdef CONFIG_RTL8822C\n\telse if (IS_HARDWARE_TYPE_8822C(padapter))\n\t\tex_hal8822c_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);\n#endif\n}\n\nvoid hal_btcoex_wifionly_hw_config(PADAPTER padapter)\n{\n\tstruct wifi_only_cfg *pwifionlycfg = &GLBtCoexistWifiOnly;\n\n\tif (IS_HARDWARE_TYPE_8723B(padapter)) {\n#ifdef CONFIG_RTL8723B\n\t\tex_hal8723b_wifi_only_hw_config(pwifionlycfg);\n#endif\n\t}\n\n#ifdef CONFIG_RTL8822B\n\telse if (IS_HARDWARE_TYPE_8822B(padapter))\n\t\tex_hal8822b_wifi_only_hw_config(pwifionlycfg);\n#endif\n\n#ifdef CONFIG_RTL8821C\n\telse if (IS_HARDWARE_TYPE_8821C(padapter))\n\t\tex_hal8821c_wifi_only_hw_config(pwifionlycfg);\n#endif\n\n#ifdef CONFIG_RTL8822C\n\telse if (IS_HARDWARE_TYPE_8822C(padapter))\n\t\tex_hal8822c_wifi_only_hw_config(pwifionlycfg);\n#endif\n}\n\nvoid hal_btcoex_wifionly_initlizevariables(PADAPTER padapter)\n{\n\tstruct wifi_only_cfg\t\t*pwifionlycfg = &GLBtCoexistWifiOnly;\n\tstruct wifi_only_haldata\t*pwifionly_haldata = &pwifionlycfg->haldata_info;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n\t_rtw_memset(&GLBtCoexistWifiOnly, 0, sizeof(GLBtCoexistWifiOnly));\n\n\tpwifionlycfg->Adapter = padapter;\n\n#ifdef CONFIG_PCI_HCI\n\tpwifionlycfg->chip_interface = WIFIONLY_INTF_PCI;\n#elif defined(CONFIG_USB_HCI)\n\tpwifionlycfg->chip_interface = WIFIONLY_INTF_USB;\n#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\tpwifionlycfg->chip_interface = WIFIONLY_INTF_SDIO;\n#else\n\tpwifionlycfg->chip_interface = WIFIONLY_INTF_UNKNOWN;\n#endif\n\n\tpwifionly_haldata->customer_id = CUSTOMER_NORMAL;\n}\n\nvoid hal_btcoex_wifionly_AntInfoSetting(PADAPTER padapter)\n{\n\tstruct wifi_only_cfg\t\t*pwifionlycfg = &GLBtCoexistWifiOnly;\n\tstruct wifi_only_haldata\t*pwifionly_haldata = &pwifionlycfg->haldata_info;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n\tpwifionly_haldata->efuse_pg_antnum = pHalData->EEPROMBluetoothAntNum;\n\tpwifionly_haldata->efuse_pg_antpath = pHalData->ant_path;\n\tpwifionly_haldata->rfe_type = pHalData->rfe_type;\n\tpwifionly_haldata->ant_div_cfg = pHalData->AntDivCfg;\n}\n\n#endif\n\n"
  },
  {
    "path": "hal/hal_com.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _HAL_COM_C_\n\n#include <drv_types.h>\n#include \"hal_com_h2c.h\"\n\n#include \"hal_data.h\"\n\n#ifdef RTW_HALMAC\n#include \"../../hal/hal_halmac.h\"\n#endif\n\nvoid rtw_dump_fw_info(void *sel, _adapter *adapter)\n{\n\tHAL_DATA_TYPE\t*hal_data = NULL;\n\n\tif (!adapter)\n\t\treturn;\n\n\thal_data = GET_HAL_DATA(adapter);\n\tif (hal_data->bFWReady)\n\t\tRTW_PRINT_SEL(sel, \"FW VER -%d.%d\\n\", hal_data->firmware_version, hal_data->firmware_sub_version);\n\telse\n\t\tRTW_PRINT_SEL(sel, \"FW not ready\\n\");\n}\n\nbool rsvd_page_cache_update_all(struct rsvd_page_cache_t *cache, u8 loc\n\t, u8 txdesc_len, u32 page_size, u8 *info, u32 info_len)\n{\n\tu8 page_num;\n\tbool modified = 0;\n\tbool loc_mod = 0, size_mod = 0, page_num_mod = 0;\n\n\tpage_num = info_len ? (u8)PageNum(txdesc_len + info_len, page_size) : 0;\n\tif (!info_len)\n\t\tloc = 0;\n\n\tif (cache->loc != loc) {\n\t\tRTW_INFO(\"%s %s loc change (%u -> %u)\\n\"\n\t\t\t, __func__, cache->name, cache->loc, loc);\n\t\tloc_mod = 1;\n\t}\n\tif (cache->size != info_len) {\n\t\tRTW_INFO(\"%s %s size change (%u -> %u)\\n\"\n\t\t\t, __func__, cache->name, cache->size, info_len);\n\t\tsize_mod = 1;\n\t}\n\tif (cache->page_num != page_num) {\n\t\tRTW_INFO(\"%s %s page_num change (%u -> %u)\\n\"\n\t\t\t, __func__, cache->name, cache->page_num, page_num);\n\t\tpage_num_mod = 1;\n\t}\n\n\tif (info && info_len) {\n\t\tif (cache->data) {\n\t\t\tif (cache->size == info_len) {\n\t\t\t\tif (_rtw_memcmp(cache->data, info, info_len) != _TRUE) {\n\t\t\t\t\tRTW_INFO(\"%s %s data change\\n\", __func__, cache->name);\n\t\t\t\t\tmodified = 1;\n\t\t\t\t}\n\t\t\t} else\n\t\t\t\trsvd_page_cache_free_data(cache);\n\t\t}\n\n\t\tif (!cache->data) {\n\t\t\tcache->data = rtw_malloc(info_len);\n\t\t\tif (!cache->data) {\n\t\t\t\tRTW_ERR(\"%s %s alloc data with size(%u) fail\\n\"\n\t\t\t\t\t, __func__, cache->name, info_len);\n\t\t\t\trtw_warn_on(1);\n\t\t\t} else {\n\t\t\t\tRTW_INFO(\"%s %s alloc data with size(%u)\\n\"\n\t\t\t\t\t, __func__, cache->name, info_len);\n\t\t\t}\n\t\t\tmodified = 1;\n\t\t}\n\n\t\tif (cache->data && modified)\n\t\t\t_rtw_memcpy(cache->data, info, info_len);\n\t} else {\n\t\tif (cache->data && size_mod)\n\t\t\trsvd_page_cache_free_data(cache);\n\t}\n\n\tcache->loc = loc;\n\tcache->page_num = page_num;\n\tcache->size = info_len;\n\n\treturn modified | loc_mod | size_mod | page_num_mod;\n}\n\nbool rsvd_page_cache_update_data(struct rsvd_page_cache_t *cache, u8 *info, u32 info_len)\n{\n\tbool modified = 0;\n\n\tif (!info || !info_len) {\n\t\tRTW_WARN(\"%s %s invalid input(info:%p, info_len:%u)\\n\"\n\t\t\t, __func__, cache->name, info, info_len);\n\t\tgoto exit;\n\t}\n\n\tif (!cache->loc || !cache->page_num || !cache->size) {\n\t\tRTW_ERR(\"%s %s layout not ready(loc:%u, page_num:%u, size:%u)\\n\"\n\t\t\t, __func__, cache->name, cache->loc, cache->page_num, cache->size);\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (cache->size != info_len) {\n\t\tRTW_ERR(\"%s %s size(%u) differ with info_len(%u)\\n\"\n\t\t\t, __func__, cache->name, cache->size, info_len);\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (!cache->data) {\n\t\tcache->data = rtw_zmalloc(cache->size);\n\t\tif (!cache->data) {\n\t\t\tRTW_ERR(\"%s %s alloc data with size(%u) fail\\n\"\n\t\t\t\t, __func__, cache->name, cache->size);\n\t\t\trtw_warn_on(1);\n\t\t\tgoto exit;\n\t\t} else {\n\t\t\tRTW_INFO(\"%s %s alloc data with size(%u)\\n\"\n\t\t\t\t, __func__, cache->name, info_len);\n\t\t}\n\t\tmodified = 1;\n\t}\n\n\tif (_rtw_memcmp(cache->data, info, cache->size) == _FALSE) {\n\t\tRTW_INFO(\"%s %s data change\\n\", __func__, cache->name);\n\t\t_rtw_memcpy(cache->data, info, cache->size);\n\t\tmodified = 1;\n\t}\n\nexit:\n\treturn modified;\n}\n\nvoid rsvd_page_cache_free_data(struct rsvd_page_cache_t *cache)\n{\n\tif (cache->data) {\n\t\trtw_mfree(cache->data, cache->size);\n\t\tcache->data = NULL;\n\t}\n}\n\nvoid rsvd_page_cache_free(struct rsvd_page_cache_t *cache)\n{\n\tcache->loc = 0;\n\tcache->page_num = 0;\n\trsvd_page_cache_free_data(cache);\n\tcache->size = 0;\n}\n\n/* #define CONFIG_GTK_OL_DBG */\n\n/*#define DBG_SEC_CAM_MOVE*/\n#ifdef DBG_SEC_CAM_MOVE\nvoid rtw_hal_move_sta_gk_to_dk(_adapter *adapter)\n{\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tint cam_id, index = 0;\n\tu8 *addr = NULL;\n\n\tif (!MLME_IS_STA(adapter))\n\t\treturn;\n\n\taddr = get_bssid(pmlmepriv);\n\n\tif (addr == NULL) {\n\t\tRTW_INFO(\"%s: get bssid MAC addr fail!!\\n\", __func__);\n\t\treturn;\n\t}\n\n\trtw_clean_dk_section(adapter);\n\n\tdo {\n\t\tcam_id = rtw_camid_search(adapter, addr, index, 1);\n\n\t\tif (cam_id == -1)\n\t\t\tRTW_INFO(\"%s: cam_id: %d, key_id:%d\\n\", __func__, cam_id, index);\n\t\telse\n\t\t\trtw_sec_cam_swap(adapter, cam_id, index);\n\n\t\tindex++;\n\t} while (index < 4);\n\n}\n\nvoid rtw_hal_read_sta_dk_key(_adapter *adapter, u8 key_id)\n{\n\tstruct security_priv *psecuritypriv = &adapter->securitypriv;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\t_irqL irqL;\n\tu8 get_key[16];\n\n\t_rtw_memset(get_key, 0, sizeof(get_key));\n\n\tif (key_id > 4) {\n\t\tRTW_INFO(\"%s [ERROR] gtk_keyindex:%d invalid\\n\", __func__, key_id);\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\trtw_sec_read_cam_ent(adapter, key_id, NULL, NULL, get_key);\n\n\t/*update key into related sw variable*/\n\t_enter_critical_bh(&cam_ctl->lock, &irqL);\n\tif (_rtw_camid_is_gk(adapter, key_id)) {\n\t\tRTW_INFO(\"[HW KEY] -Key-id:%d \"KEY_FMT\"\\n\", key_id, KEY_ARG(get_key));\n\t\tRTW_INFO(\"[cam_cache KEY] - Key-id:%d \"KEY_FMT\"\\n\", key_id, KEY_ARG(&dvobj->cam_cache[key_id].key));\n\t}\n\t_exit_critical_bh(&cam_ctl->lock, &irqL);\n\n}\n#endif\n\n\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\tchar\trtw_phy_para_file_path[PATH_LENGTH_MAX];\n#endif\n\nvoid dump_chip_info(HAL_VERSION\tChipVersion)\n{\n\tint cnt = 0;\n\tu8 buf[128] = {0};\n\n\tif (IS_8188E(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"Chip Version Info: CHIP_8188E_\");\n\telse if (IS_8188F(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"Chip Version Info: CHIP_8188F_\");\n\telse if (IS_8188GTV(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"Chip Version Info: CHIP_8188GTV_\");\n\telse if (IS_8812_SERIES(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"Chip Version Info: CHIP_8812_\");\n\telse if (IS_8192E(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"Chip Version Info: CHIP_8192E_\");\n\telse if (IS_8821_SERIES(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"Chip Version Info: CHIP_8821_\");\n\telse if (IS_8723B_SERIES(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"Chip Version Info: CHIP_8723B_\");\n\telse if (IS_8703B_SERIES(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"Chip Version Info: CHIP_8703B_\");\n\telse if (IS_8723D_SERIES(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"Chip Version Info: CHIP_8723D_\");\n\telse if (IS_8814A_SERIES(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"Chip Version Info: CHIP_8814A_\");\n\telse if (IS_8822B_SERIES(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"Chip Version Info: CHIP_8822B_\");\n\telse if (IS_8821C_SERIES(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"Chip Version Info: CHIP_8821C_\");\n\telse if (IS_8710B_SERIES(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"Chip Version Info: CHIP_8710B_\");\n\telse if (IS_8192F_SERIES(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"Chip Version Info: CHIP_8192F_\");\n\telse if (IS_8822C_SERIES(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"Chip Version Info: CHIP_8822C_\");\n\telse\n\t\tcnt += sprintf((buf + cnt), \"Chip Version Info: CHIP_UNKNOWN_\");\n\n\tcnt += sprintf((buf + cnt), \"%s_\", IS_NORMAL_CHIP(ChipVersion) ? \"Normal_Chip\" : \"Test_Chip\");\n\tif (IS_CHIP_VENDOR_TSMC(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"%s_\", \"TSMC\");\n\telse if (IS_CHIP_VENDOR_UMC(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"%s_\", \"UMC\");\n\telse if (IS_CHIP_VENDOR_SMIC(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"%s_\", \"SMIC\");\n\n\tif (IS_A_CUT(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"A_CUT_\");\n\telse if (IS_B_CUT(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"B_CUT_\");\n\telse if (IS_C_CUT(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"C_CUT_\");\n\telse if (IS_D_CUT(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"D_CUT_\");\n\telse if (IS_E_CUT(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"E_CUT_\");\n\telse if (IS_F_CUT(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"F_CUT_\");\n\telse if (IS_I_CUT(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"I_CUT_\");\n\telse if (IS_J_CUT(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"J_CUT_\");\n\telse if (IS_K_CUT(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"K_CUT_\");\n\telse\n\t\tcnt += sprintf((buf + cnt), \"UNKNOWN_CUT(%d)_\", ChipVersion.CUTVersion);\n\n\tif (IS_1T1R(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"1T1R_\");\n\telse if (IS_1T2R(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"1T2R_\");\n\telse if (IS_2T2R(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"2T2R_\");\n\telse if (IS_3T3R(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"3T3R_\");\n\telse if (IS_3T4R(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"3T4R_\");\n\telse if (IS_4T4R(ChipVersion))\n\t\tcnt += sprintf((buf + cnt), \"4T4R_\");\n\telse\n\t\tcnt += sprintf((buf + cnt), \"UNKNOWN_RFTYPE(%d)_\", ChipVersion.RFType);\n\n\tcnt += sprintf((buf + cnt), \"RomVer(%d)\\n\", ChipVersion.ROMVer);\n\n\tRTW_INFO(\"%s\", buf);\n}\n\nu8 rtw_hal_get_port(_adapter *adapter)\n{\n\tu8 hw_port = get_hw_port(adapter);\n#ifdef CONFIG_CLIENT_PORT_CFG\n\tu8 clt_port = get_clt_port(adapter);\n\n\tif (clt_port)\n\t\thw_port = clt_port;\n\n#ifdef DBG_HW_PORT\n\tif (MLME_IS_STA(adapter) && (adapter->client_id != MAX_CLIENT_PORT_NUM)) {\n\t\tif(hw_port == CLT_PORT_INVALID) {\n\t\t\tRTW_ERR(ADPT_FMT\" @@@@@ Client port == 0 @@@@@\\n\", ADPT_ARG(adapter));\n\t\t\trtw_warn_on(1);\n\t\t}\n\t}\n\telse if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {\n\t\tif (hw_port != HW_PORT0) {\n\t\t\tRTW_ERR(ADPT_FMT\" @@@@@ AP / MESH port != 0 @@@@@\\n\", ADPT_ARG(adapter));\n\t\t\trtw_warn_on(1);\n\t\t}\n\t}\n\tif (0)\n\t\tRTW_INFO(ADPT_FMT\" - HP:%d,CP:%d\\n\", ADPT_ARG(adapter), get_hw_port(adapter), get_clt_port(adapter));\n#endif /*DBG_HW_PORT*/\n\n#endif/*CONFIG_CLIENT_PORT_CFG*/\n\n\treturn hw_port;\n}\n\nvoid rtw_hal_config_rftype(PADAPTER  padapter)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\n\tif (IS_1T1R(pHalData->version_id)) {\n\t\tpHalData->rf_type = RF_1T1R;\n\t\tpHalData->NumTotalRFPath = 1;\n\t} else if (IS_2T2R(pHalData->version_id)) {\n\t\tpHalData->rf_type = RF_2T2R;\n\t\tpHalData->NumTotalRFPath = 2;\n\t} else if (IS_1T2R(pHalData->version_id)) {\n\t\tpHalData->rf_type = RF_1T2R;\n\t\tpHalData->NumTotalRFPath = 2;\n\t} else if (IS_3T3R(pHalData->version_id)) {\n\t\tpHalData->rf_type = RF_3T3R;\n\t\tpHalData->NumTotalRFPath = 3;\n\t} else if (IS_4T4R(pHalData->version_id)) {\n\t\tpHalData->rf_type = RF_4T4R;\n\t\tpHalData->NumTotalRFPath = 4;\n\t} else {\n\t\tpHalData->rf_type = RF_1T1R;\n\t\tpHalData->NumTotalRFPath = 1;\n\t}\n\n\tRTW_INFO(\"%s RF_Type is %d TotalTxPath is %d\\n\", __FUNCTION__, pHalData->rf_type, pHalData->NumTotalRFPath);\n}\n\n#define\tEEPROM_CHANNEL_PLAN_BY_HW_MASK\t0x80\n\n/*\n * Description:\n *\tUse hardware(efuse), driver parameter(registry) and default channel plan\n *\tto decide which one should be used.\n *\n * Parameters:\n *\tpadapter\t\t\tpointer of adapter\n *\thw_alpha2\t\tcountry code from HW (efuse/eeprom/mapfile)\n *\thw_chplan\t\tchannel plan from HW (efuse/eeprom/mapfile)\n *\t\t\t\t\t\tBIT[7] software configure mode; 0:Enable, 1:disable\n *\t\t\t\t\t\tBIT[6:0] Channel Plan\n *\tsw_alpha2\t\tcountry code from HW (registry/module param)\n *\tsw_chplan\t\tchannel plan from SW (registry/module param)\n *\tdef_chplan\t\tchannel plan used when HW/SW both invalid\n *\tAutoLoadFail\t\tefuse autoload fail or not\n *\n */\nvoid hal_com_config_channel_plan(\n\t\tPADAPTER padapter,\n\t\tchar *hw_alpha2,\n\t\tu8 hw_chplan,\n\t\tchar *sw_alpha2,\n\t\tu8 sw_chplan,\n\t\tu8 def_chplan,\n\t\tBOOLEAN AutoLoadFail\n)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tPHAL_DATA_TYPE\tpHalData;\n\tu8 force_hw_chplan = _FALSE;\n\tint chplan = -1;\n\tconst struct country_chplan *country_ent = NULL, *ent;\n\n\tpHalData = GET_HAL_DATA(padapter);\n\n\t/* treat 0xFF as invalid value, bypass hw_chplan & force_hw_chplan parsing */\n\tif (hw_chplan == 0xFF)\n\t\tgoto chk_hw_country_code;\n\n\tif (AutoLoadFail == _TRUE)\n\t\tgoto chk_sw_config;\n\n#ifndef CONFIG_FORCE_SW_CHANNEL_PLAN\n\tif (hw_chplan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)\n\t\tforce_hw_chplan = _TRUE;\n#endif\n\n\thw_chplan &= (~EEPROM_CHANNEL_PLAN_BY_HW_MASK);\n\nchk_hw_country_code:\n\tif (hw_alpha2 && !IS_ALPHA2_NO_SPECIFIED(hw_alpha2)) {\n\t\tent = rtw_get_chplan_from_country(hw_alpha2);\n\t\tif (ent) {\n\t\t\t/* get chplan from hw country code, by pass hw chplan setting */\n\t\t\tcountry_ent = ent;\n\t\t\tchplan = ent->chplan;\n\t\t\tgoto chk_sw_config;\n\t\t} else\n\t\t\tRTW_PRINT(\"%s unsupported hw_alpha2:\\\"%c%c\\\"\\n\", __func__, hw_alpha2[0], hw_alpha2[1]);\n\t}\n\n\tif (rtw_is_channel_plan_valid(hw_chplan))\n\t\tchplan = hw_chplan;\n\telse if (force_hw_chplan == _TRUE) {\n\t\tRTW_PRINT(\"%s unsupported hw_chplan:0x%02X\\n\", __func__, hw_chplan);\n\t\t/* hw infomaton invalid, refer to sw information */\n\t\tforce_hw_chplan = _FALSE;\n\t}\n\nchk_sw_config:\n\tif (force_hw_chplan == _TRUE)\n\t\tgoto done;\n\n\tif (sw_alpha2 && !IS_ALPHA2_NO_SPECIFIED(sw_alpha2)) {\n\t\tent = rtw_get_chplan_from_country(sw_alpha2);\n\t\tif (ent) {\n\t\t\t/* get chplan from sw country code, by pass sw chplan setting */\n\t\t\tcountry_ent = ent;\n\t\t\tchplan = ent->chplan;\n\t\t\tgoto done;\n\t\t} else\n\t\t\tRTW_PRINT(\"%s unsupported sw_alpha2:\\\"%c%c\\\"\\n\", __func__, sw_alpha2[0], sw_alpha2[1]);\n\t}\n\n\tif (rtw_is_channel_plan_valid(sw_chplan)) {\n\t\t/* cancel hw_alpha2 because chplan is specified by sw_chplan*/\n\t\tcountry_ent = NULL;\n\t\tchplan = sw_chplan;\n\t} else if (sw_chplan != RTW_CHPLAN_UNSPECIFIED)\n\t\tRTW_PRINT(\"%s unsupported sw_chplan:0x%02X\\n\", __func__, sw_chplan);\n\ndone:\n\tif (chplan == -1) {\n\t\tRTW_PRINT(\"%s use def_chplan:0x%02X\\n\", __func__, def_chplan);\n\t\tchplan = def_chplan;\n\t} else if (country_ent) {\n\t\tRTW_PRINT(\"%s country code:\\\"%c%c\\\" with chplan:0x%02X\\n\", __func__\n\t\t\t, country_ent->alpha2[0], country_ent->alpha2[1], country_ent->chplan);\n\t} else\n\t\tRTW_PRINT(\"%s chplan:0x%02X\\n\", __func__, chplan);\n\n\trfctl->country_ent = country_ent;\n\trfctl->ChannelPlan = chplan;\n\tpHalData->bDisableSWChannelPlan = force_hw_chplan;\n}\n\nBOOLEAN\nHAL_IsLegalChannel(\n\t\tPADAPTER\tAdapter,\n\t\tu32\t\t\tChannel\n)\n{\n\tBOOLEAN bLegalChannel = _TRUE;\n\n\tif (Channel > 14) {\n\t\tif (is_supported_5g(Adapter->registrypriv.wireless_mode) == _FALSE) {\n\t\t\tbLegalChannel = _FALSE;\n\t\t\tRTW_INFO(\"Channel > 14 but wireless_mode do not support 5G\\n\");\n\t\t}\n\t} else if ((Channel <= 14) && (Channel >= 1)) {\n\t\tif (IsSupported24G(Adapter->registrypriv.wireless_mode) == _FALSE) {\n\t\t\tbLegalChannel = _FALSE;\n\t\t\tRTW_INFO(\"(Channel <= 14) && (Channel >=1) but wireless_mode do not support 2.4G\\n\");\n\t\t}\n\t} else {\n\t\tbLegalChannel = _FALSE;\n\t\tRTW_INFO(\"Channel is Invalid !!!\\n\");\n\t}\n\n\treturn bLegalChannel;\n}\n\nu8\tMRateToHwRate(u8 rate)\n{\n\tu8\tret = DESC_RATE1M;\n\n\tswitch (rate) {\n\tcase MGN_1M:\n\t\tret = DESC_RATE1M;\n\t\tbreak;\n\tcase MGN_2M:\n\t\tret = DESC_RATE2M;\n\t\tbreak;\n\tcase MGN_5_5M:\n\t\tret = DESC_RATE5_5M;\n\t\tbreak;\n\tcase MGN_11M:\n\t\tret = DESC_RATE11M;\n\t\tbreak;\n\tcase MGN_6M:\n\t\tret = DESC_RATE6M;\n\t\tbreak;\n\tcase MGN_9M:\n\t\tret = DESC_RATE9M;\n\t\tbreak;\n\tcase MGN_12M:\n\t\tret = DESC_RATE12M;\n\t\tbreak;\n\tcase MGN_18M:\n\t\tret = DESC_RATE18M;\n\t\tbreak;\n\tcase MGN_24M:\n\t\tret = DESC_RATE24M;\n\t\tbreak;\n\tcase MGN_36M:\n\t\tret = DESC_RATE36M;\n\t\tbreak;\n\tcase MGN_48M:\n\t\tret = DESC_RATE48M;\n\t\tbreak;\n\tcase MGN_54M:\n\t\tret = DESC_RATE54M;\n\t\tbreak;\n\n\tcase MGN_MCS0:\n\t\tret = DESC_RATEMCS0;\n\t\tbreak;\n\tcase MGN_MCS1:\n\t\tret = DESC_RATEMCS1;\n\t\tbreak;\n\tcase MGN_MCS2:\n\t\tret = DESC_RATEMCS2;\n\t\tbreak;\n\tcase MGN_MCS3:\n\t\tret = DESC_RATEMCS3;\n\t\tbreak;\n\tcase MGN_MCS4:\n\t\tret = DESC_RATEMCS4;\n\t\tbreak;\n\tcase MGN_MCS5:\n\t\tret = DESC_RATEMCS5;\n\t\tbreak;\n\tcase MGN_MCS6:\n\t\tret = DESC_RATEMCS6;\n\t\tbreak;\n\tcase MGN_MCS7:\n\t\tret = DESC_RATEMCS7;\n\t\tbreak;\n\tcase MGN_MCS8:\n\t\tret = DESC_RATEMCS8;\n\t\tbreak;\n\tcase MGN_MCS9:\n\t\tret = DESC_RATEMCS9;\n\t\tbreak;\n\tcase MGN_MCS10:\n\t\tret = DESC_RATEMCS10;\n\t\tbreak;\n\tcase MGN_MCS11:\n\t\tret = DESC_RATEMCS11;\n\t\tbreak;\n\tcase MGN_MCS12:\n\t\tret = DESC_RATEMCS12;\n\t\tbreak;\n\tcase MGN_MCS13:\n\t\tret = DESC_RATEMCS13;\n\t\tbreak;\n\tcase MGN_MCS14:\n\t\tret = DESC_RATEMCS14;\n\t\tbreak;\n\tcase MGN_MCS15:\n\t\tret = DESC_RATEMCS15;\n\t\tbreak;\n\tcase MGN_MCS16:\n\t\tret = DESC_RATEMCS16;\n\t\tbreak;\n\tcase MGN_MCS17:\n\t\tret = DESC_RATEMCS17;\n\t\tbreak;\n\tcase MGN_MCS18:\n\t\tret = DESC_RATEMCS18;\n\t\tbreak;\n\tcase MGN_MCS19:\n\t\tret = DESC_RATEMCS19;\n\t\tbreak;\n\tcase MGN_MCS20:\n\t\tret = DESC_RATEMCS20;\n\t\tbreak;\n\tcase MGN_MCS21:\n\t\tret = DESC_RATEMCS21;\n\t\tbreak;\n\tcase MGN_MCS22:\n\t\tret = DESC_RATEMCS22;\n\t\tbreak;\n\tcase MGN_MCS23:\n\t\tret = DESC_RATEMCS23;\n\t\tbreak;\n\tcase MGN_MCS24:\n\t\tret = DESC_RATEMCS24;\n\t\tbreak;\n\tcase MGN_MCS25:\n\t\tret = DESC_RATEMCS25;\n\t\tbreak;\n\tcase MGN_MCS26:\n\t\tret = DESC_RATEMCS26;\n\t\tbreak;\n\tcase MGN_MCS27:\n\t\tret = DESC_RATEMCS27;\n\t\tbreak;\n\tcase MGN_MCS28:\n\t\tret = DESC_RATEMCS28;\n\t\tbreak;\n\tcase MGN_MCS29:\n\t\tret = DESC_RATEMCS29;\n\t\tbreak;\n\tcase MGN_MCS30:\n\t\tret = DESC_RATEMCS30;\n\t\tbreak;\n\tcase MGN_MCS31:\n\t\tret = DESC_RATEMCS31;\n\t\tbreak;\n\n\tcase MGN_VHT1SS_MCS0:\n\t\tret = DESC_RATEVHTSS1MCS0;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS1:\n\t\tret = DESC_RATEVHTSS1MCS1;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS2:\n\t\tret = DESC_RATEVHTSS1MCS2;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS3:\n\t\tret = DESC_RATEVHTSS1MCS3;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS4:\n\t\tret = DESC_RATEVHTSS1MCS4;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS5:\n\t\tret = DESC_RATEVHTSS1MCS5;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS6:\n\t\tret = DESC_RATEVHTSS1MCS6;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS7:\n\t\tret = DESC_RATEVHTSS1MCS7;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS8:\n\t\tret = DESC_RATEVHTSS1MCS8;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS9:\n\t\tret = DESC_RATEVHTSS1MCS9;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS0:\n\t\tret = DESC_RATEVHTSS2MCS0;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS1:\n\t\tret = DESC_RATEVHTSS2MCS1;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS2:\n\t\tret = DESC_RATEVHTSS2MCS2;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS3:\n\t\tret = DESC_RATEVHTSS2MCS3;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS4:\n\t\tret = DESC_RATEVHTSS2MCS4;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS5:\n\t\tret = DESC_RATEVHTSS2MCS5;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS6:\n\t\tret = DESC_RATEVHTSS2MCS6;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS7:\n\t\tret = DESC_RATEVHTSS2MCS7;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS8:\n\t\tret = DESC_RATEVHTSS2MCS8;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS9:\n\t\tret = DESC_RATEVHTSS2MCS9;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS0:\n\t\tret = DESC_RATEVHTSS3MCS0;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS1:\n\t\tret = DESC_RATEVHTSS3MCS1;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS2:\n\t\tret = DESC_RATEVHTSS3MCS2;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS3:\n\t\tret = DESC_RATEVHTSS3MCS3;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS4:\n\t\tret = DESC_RATEVHTSS3MCS4;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS5:\n\t\tret = DESC_RATEVHTSS3MCS5;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS6:\n\t\tret = DESC_RATEVHTSS3MCS6;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS7:\n\t\tret = DESC_RATEVHTSS3MCS7;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS8:\n\t\tret = DESC_RATEVHTSS3MCS8;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS9:\n\t\tret = DESC_RATEVHTSS3MCS9;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS0:\n\t\tret = DESC_RATEVHTSS4MCS0;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS1:\n\t\tret = DESC_RATEVHTSS4MCS1;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS2:\n\t\tret = DESC_RATEVHTSS4MCS2;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS3:\n\t\tret = DESC_RATEVHTSS4MCS3;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS4:\n\t\tret = DESC_RATEVHTSS4MCS4;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS5:\n\t\tret = DESC_RATEVHTSS4MCS5;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS6:\n\t\tret = DESC_RATEVHTSS4MCS6;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS7:\n\t\tret = DESC_RATEVHTSS4MCS7;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS8:\n\t\tret = DESC_RATEVHTSS4MCS8;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS9:\n\t\tret = DESC_RATEVHTSS4MCS9;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nu8\thw_rate_to_m_rate(u8 rate)\n{\n\tu8\tret_rate = MGN_1M;\n\n\tswitch (rate) {\n\n\tcase DESC_RATE1M:\n\t\tret_rate = MGN_1M;\n\t\tbreak;\n\tcase DESC_RATE2M:\n\t\tret_rate = MGN_2M;\n\t\tbreak;\n\tcase DESC_RATE5_5M:\n\t\tret_rate = MGN_5_5M;\n\t\tbreak;\n\tcase DESC_RATE11M:\n\t\tret_rate = MGN_11M;\n\t\tbreak;\n\tcase DESC_RATE6M:\n\t\tret_rate = MGN_6M;\n\t\tbreak;\n\tcase DESC_RATE9M:\n\t\tret_rate = MGN_9M;\n\t\tbreak;\n\tcase DESC_RATE12M:\n\t\tret_rate = MGN_12M;\n\t\tbreak;\n\tcase DESC_RATE18M:\n\t\tret_rate = MGN_18M;\n\t\tbreak;\n\tcase DESC_RATE24M:\n\t\tret_rate = MGN_24M;\n\t\tbreak;\n\tcase DESC_RATE36M:\n\t\tret_rate = MGN_36M;\n\t\tbreak;\n\tcase DESC_RATE48M:\n\t\tret_rate = MGN_48M;\n\t\tbreak;\n\tcase DESC_RATE54M:\n\t\tret_rate = MGN_54M;\n\t\tbreak;\n\tcase DESC_RATEMCS0:\n\t\tret_rate = MGN_MCS0;\n\t\tbreak;\n\tcase DESC_RATEMCS1:\n\t\tret_rate = MGN_MCS1;\n\t\tbreak;\n\tcase DESC_RATEMCS2:\n\t\tret_rate = MGN_MCS2;\n\t\tbreak;\n\tcase DESC_RATEMCS3:\n\t\tret_rate = MGN_MCS3;\n\t\tbreak;\n\tcase DESC_RATEMCS4:\n\t\tret_rate = MGN_MCS4;\n\t\tbreak;\n\tcase DESC_RATEMCS5:\n\t\tret_rate = MGN_MCS5;\n\t\tbreak;\n\tcase DESC_RATEMCS6:\n\t\tret_rate = MGN_MCS6;\n\t\tbreak;\n\tcase DESC_RATEMCS7:\n\t\tret_rate = MGN_MCS7;\n\t\tbreak;\n\tcase DESC_RATEMCS8:\n\t\tret_rate = MGN_MCS8;\n\t\tbreak;\n\tcase DESC_RATEMCS9:\n\t\tret_rate = MGN_MCS9;\n\t\tbreak;\n\tcase DESC_RATEMCS10:\n\t\tret_rate = MGN_MCS10;\n\t\tbreak;\n\tcase DESC_RATEMCS11:\n\t\tret_rate = MGN_MCS11;\n\t\tbreak;\n\tcase DESC_RATEMCS12:\n\t\tret_rate = MGN_MCS12;\n\t\tbreak;\n\tcase DESC_RATEMCS13:\n\t\tret_rate = MGN_MCS13;\n\t\tbreak;\n\tcase DESC_RATEMCS14:\n\t\tret_rate = MGN_MCS14;\n\t\tbreak;\n\tcase DESC_RATEMCS15:\n\t\tret_rate = MGN_MCS15;\n\t\tbreak;\n\tcase DESC_RATEMCS16:\n\t\tret_rate = MGN_MCS16;\n\t\tbreak;\n\tcase DESC_RATEMCS17:\n\t\tret_rate = MGN_MCS17;\n\t\tbreak;\n\tcase DESC_RATEMCS18:\n\t\tret_rate = MGN_MCS18;\n\t\tbreak;\n\tcase DESC_RATEMCS19:\n\t\tret_rate = MGN_MCS19;\n\t\tbreak;\n\tcase DESC_RATEMCS20:\n\t\tret_rate = MGN_MCS20;\n\t\tbreak;\n\tcase DESC_RATEMCS21:\n\t\tret_rate = MGN_MCS21;\n\t\tbreak;\n\tcase DESC_RATEMCS22:\n\t\tret_rate = MGN_MCS22;\n\t\tbreak;\n\tcase DESC_RATEMCS23:\n\t\tret_rate = MGN_MCS23;\n\t\tbreak;\n\tcase DESC_RATEMCS24:\n\t\tret_rate = MGN_MCS24;\n\t\tbreak;\n\tcase DESC_RATEMCS25:\n\t\tret_rate = MGN_MCS25;\n\t\tbreak;\n\tcase DESC_RATEMCS26:\n\t\tret_rate = MGN_MCS26;\n\t\tbreak;\n\tcase DESC_RATEMCS27:\n\t\tret_rate = MGN_MCS27;\n\t\tbreak;\n\tcase DESC_RATEMCS28:\n\t\tret_rate = MGN_MCS28;\n\t\tbreak;\n\tcase DESC_RATEMCS29:\n\t\tret_rate = MGN_MCS29;\n\t\tbreak;\n\tcase DESC_RATEMCS30:\n\t\tret_rate = MGN_MCS30;\n\t\tbreak;\n\tcase DESC_RATEMCS31:\n\t\tret_rate = MGN_MCS31;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS0:\n\t\tret_rate = MGN_VHT1SS_MCS0;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS1:\n\t\tret_rate = MGN_VHT1SS_MCS1;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS2:\n\t\tret_rate = MGN_VHT1SS_MCS2;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS3:\n\t\tret_rate = MGN_VHT1SS_MCS3;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS4:\n\t\tret_rate = MGN_VHT1SS_MCS4;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS5:\n\t\tret_rate = MGN_VHT1SS_MCS5;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS6:\n\t\tret_rate = MGN_VHT1SS_MCS6;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS7:\n\t\tret_rate = MGN_VHT1SS_MCS7;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS8:\n\t\tret_rate = MGN_VHT1SS_MCS8;\n\t\tbreak;\n\tcase DESC_RATEVHTSS1MCS9:\n\t\tret_rate = MGN_VHT1SS_MCS9;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS0:\n\t\tret_rate = MGN_VHT2SS_MCS0;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS1:\n\t\tret_rate = MGN_VHT2SS_MCS1;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS2:\n\t\tret_rate = MGN_VHT2SS_MCS2;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS3:\n\t\tret_rate = MGN_VHT2SS_MCS3;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS4:\n\t\tret_rate = MGN_VHT2SS_MCS4;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS5:\n\t\tret_rate = MGN_VHT2SS_MCS5;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS6:\n\t\tret_rate = MGN_VHT2SS_MCS6;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS7:\n\t\tret_rate = MGN_VHT2SS_MCS7;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS8:\n\t\tret_rate = MGN_VHT2SS_MCS8;\n\t\tbreak;\n\tcase DESC_RATEVHTSS2MCS9:\n\t\tret_rate = MGN_VHT2SS_MCS9;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS0:\n\t\tret_rate = MGN_VHT3SS_MCS0;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS1:\n\t\tret_rate = MGN_VHT3SS_MCS1;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS2:\n\t\tret_rate = MGN_VHT3SS_MCS2;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS3:\n\t\tret_rate = MGN_VHT3SS_MCS3;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS4:\n\t\tret_rate = MGN_VHT3SS_MCS4;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS5:\n\t\tret_rate = MGN_VHT3SS_MCS5;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS6:\n\t\tret_rate = MGN_VHT3SS_MCS6;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS7:\n\t\tret_rate = MGN_VHT3SS_MCS7;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS8:\n\t\tret_rate = MGN_VHT3SS_MCS8;\n\t\tbreak;\n\tcase DESC_RATEVHTSS3MCS9:\n\t\tret_rate = MGN_VHT3SS_MCS9;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS0:\n\t\tret_rate = MGN_VHT4SS_MCS0;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS1:\n\t\tret_rate = MGN_VHT4SS_MCS1;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS2:\n\t\tret_rate = MGN_VHT4SS_MCS2;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS3:\n\t\tret_rate = MGN_VHT4SS_MCS3;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS4:\n\t\tret_rate = MGN_VHT4SS_MCS4;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS5:\n\t\tret_rate = MGN_VHT4SS_MCS5;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS6:\n\t\tret_rate = MGN_VHT4SS_MCS6;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS7:\n\t\tret_rate = MGN_VHT4SS_MCS7;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS8:\n\t\tret_rate = MGN_VHT4SS_MCS8;\n\t\tbreak;\n\tcase DESC_RATEVHTSS4MCS9:\n\t\tret_rate = MGN_VHT4SS_MCS9;\n\t\tbreak;\n\n\tdefault:\n\t\tRTW_INFO(\"hw_rate_to_m_rate(): Non supported Rate [%x]!!!\\n\", rate);\n\t\tbreak;\n\t}\n\n\treturn ret_rate;\n}\n\nvoid\tHalSetBrateCfg(\n\tPADAPTER\t\tAdapter,\n\tu8\t\t\t*mBratesOS,\n\tu16\t\t\t*pBrateCfg)\n{\n\tu8\ti, is_brate, brate;\n\n\tfor (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {\n\t\tis_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;\n\t\tbrate = mBratesOS[i] & 0x7f;\n\n\t\tif (is_brate) {\n\t\t\tswitch (brate) {\n\t\t\tcase IEEE80211_CCK_RATE_1MB:\n\t\t\t\t*pBrateCfg |= RATE_1M;\n\t\t\t\tbreak;\n\t\t\tcase IEEE80211_CCK_RATE_2MB:\n\t\t\t\t*pBrateCfg |= RATE_2M;\n\t\t\t\tbreak;\n\t\t\tcase IEEE80211_CCK_RATE_5MB:\n\t\t\t\t*pBrateCfg |= RATE_5_5M;\n\t\t\t\tbreak;\n\t\t\tcase IEEE80211_CCK_RATE_11MB:\n\t\t\t\t*pBrateCfg |= RATE_11M;\n\t\t\t\tbreak;\n\t\t\tcase IEEE80211_OFDM_RATE_6MB:\n\t\t\t\t*pBrateCfg |= RATE_6M;\n\t\t\t\tbreak;\n\t\t\tcase IEEE80211_OFDM_RATE_9MB:\n\t\t\t\t*pBrateCfg |= RATE_9M;\n\t\t\t\tbreak;\n\t\t\tcase IEEE80211_OFDM_RATE_12MB:\n\t\t\t\t*pBrateCfg |= RATE_12M;\n\t\t\t\tbreak;\n\t\t\tcase IEEE80211_OFDM_RATE_18MB:\n\t\t\t\t*pBrateCfg |= RATE_18M;\n\t\t\t\tbreak;\n\t\t\tcase IEEE80211_OFDM_RATE_24MB:\n\t\t\t\t*pBrateCfg |= RATE_24M;\n\t\t\t\tbreak;\n\t\t\tcase IEEE80211_OFDM_RATE_36MB:\n\t\t\t\t*pBrateCfg |= RATE_36M;\n\t\t\t\tbreak;\n\t\t\tcase IEEE80211_OFDM_RATE_48MB:\n\t\t\t\t*pBrateCfg |= RATE_48M;\n\t\t\t\tbreak;\n\t\t\tcase IEEE80211_OFDM_RATE_54MB:\n\t\t\t\t*pBrateCfg |= RATE_54M;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic void\n_OneOutPipeMapping(\n\t\tPADAPTER\tpAdapter\n)\n{\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(pAdapter);\n\n\tpdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */\n\tpdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */\n\tpdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];/* BE */\n\tpdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */\n\n\tpdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */\n\tpdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */\n\tpdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */\n\tpdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */\n}\n\nstatic void\n_TwoOutPipeMapping(\n\t\tPADAPTER\tpAdapter,\n\t\tBOOLEAN\t\tbWIFICfg\n)\n{\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(pAdapter);\n\n\tif (bWIFICfg) { /* WMM */\n\n\t\t/*\tBK, \tBE, \tVI, \tVO, \tBCN,\tCMD,MGT,HIGH,HCCA  */\n\t\t/* {  0, \t1, \t0, \t1, \t0, \t0, \t0, \t0, \t\t0\t}; */\n\t\t/* 0:ep_0 num, 1:ep_1 num */\n\n\t\tpdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];/* VO */\n\t\tpdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */\n\t\tpdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */\n\t\tpdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */\n\n\t\tpdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */\n\t\tpdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */\n\t\tpdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */\n\t\tpdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */\n\n\t} else { /* typical setting */\n\n\n\t\t/* BK, \tBE, \tVI, \tVO, \tBCN,\tCMD,MGT,HIGH,HCCA */\n\t\t/* {  1, \t1, \t0, \t0, \t0, \t0, \t0, \t0, \t\t0\t};\t\t\t */\n\t\t/* 0:ep_0 num, 1:ep_1 num */\n\n\t\tpdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */\n\t\tpdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */\n\t\tpdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */\n\t\tpdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */\n\n\t\tpdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */\n\t\tpdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */\n\t\tpdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */\n\t\tpdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD\t */\n\n\t}\n\n}\n\nstatic void _ThreeOutPipeMapping(\n\t\tPADAPTER\tpAdapter,\n\t\tBOOLEAN\t\tbWIFICfg\n)\n{\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(pAdapter);\n\n\tif (bWIFICfg) { /* for WMM */\n\n\t\t/*\tBK, \tBE, \tVI, \tVO, \tBCN,\tCMD,MGT,HIGH,HCCA  */\n\t\t/* {  1, \t2, \t1, \t0, \t0, \t0, \t0, \t0, \t\t0\t}; */\n\t\t/* 0:H, 1:N, 2:L */\n\n\t\tpdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */\n\t\tpdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */\n\t\tpdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */\n\t\tpdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */\n\n\t\tpdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */\n\t\tpdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */\n\t\tpdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */\n\t\tpdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */\n\n\t} else { /* typical setting */\n\n\n\t\t/*\tBK, \tBE, \tVI, \tVO, \tBCN,\tCMD,MGT,HIGH,HCCA  */\n\t\t/* {  2, \t2, \t1, \t0, \t0, \t0, \t0, \t0, \t\t0\t};\t\t\t */\n\t\t/* 0:H, 1:N, 2:L */\n\n\t\tpdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */\n\t\tpdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */\n\t\tpdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */\n\t\tpdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */\n\n\t\tpdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */\n\t\tpdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */\n\t\tpdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */\n\t\tpdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD\t */\n\t}\n\n}\n#if 0\nstatic void _FourOutPipeMapping(\n\t\tPADAPTER\tpAdapter,\n\t\tBOOLEAN\t\tbWIFICfg\n)\n{\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(pAdapter);\n\n\tif (bWIFICfg) { /* for WMM */\n\n\t\t/*\tBK, \tBE, \tVI, \tVO, \tBCN,\tCMD,MGT,HIGH,HCCA  */\n\t\t/* {  1, \t2, \t1, \t0, \t0, \t0, \t0, \t0, \t\t0\t}; */\n\t\t/* 0:H, 1:N, 2:L ,3:E */\n\n\t\tpdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */\n\t\tpdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */\n\t\tpdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */\n\t\tpdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */\n\n\t\tpdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */\n\t\tpdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */\n\t\tpdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[3];/* HIGH */\n\t\tpdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */\n\n\t} else { /* typical setting */\n\n\n\t\t/*\tBK, \tBE, \tVI, \tVO, \tBCN,\tCMD,MGT,HIGH,HCCA  */\n\t\t/* {  2, \t2, \t1, \t0, \t0, \t0, \t0, \t0, \t\t0\t};\t\t\t */\n\t\t/* 0:H, 1:N, 2:L */\n\n\t\tpdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */\n\t\tpdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */\n\t\tpdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */\n\t\tpdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */\n\n\t\tpdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */\n\t\tpdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */\n\t\tpdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[3];/* HIGH */\n\t\tpdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD\t */\n\t}\n\n}\n#endif\nBOOLEAN\nHal_MappingOutPipe(\n\t\tPADAPTER\tpAdapter,\n\t\tu8\t\tNumOutPipe\n)\n{\n\tstruct registry_priv *pregistrypriv = &pAdapter->registrypriv;\n\n\tBOOLEAN\t bWIFICfg = (pregistrypriv->wifi_spec) ? _TRUE : _FALSE;\n\n\tBOOLEAN result = _TRUE;\n\n\tswitch (NumOutPipe) {\n\tcase 2:\n\t\t_TwoOutPipeMapping(pAdapter, bWIFICfg);\n\t\tbreak;\n\tcase 3:\n\tcase 4:\n\tcase 5:\n\tcase 6:\n\t\t_ThreeOutPipeMapping(pAdapter, bWIFICfg);\n\t\tbreak;\n\tcase 1:\n\t\t_OneOutPipeMapping(pAdapter);\n\t\tbreak;\n\tdefault:\n\t\tresult = _FALSE;\n\t\tbreak;\n\t}\n\n\treturn result;\n\n}\n\nvoid rtw_hal_reqtxrpt(_adapter *padapter, u8 macid)\n{\n\tif (padapter->hal_func.reqtxrpt)\n\t\tpadapter->hal_func.reqtxrpt(padapter, macid);\n}\n\nvoid rtw_hal_dump_macaddr(void *sel, _adapter *adapter)\n{\n\tint i;\n\t_adapter *iface;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tu8 mac_addr[ETH_ALEN];\n\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\trtw_mbid_cam_dump(sel, __func__, adapter);\n#else\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface) {\n\t\t\trtw_hal_get_hwreg(iface, HW_VAR_MAC_ADDR, mac_addr);\n\t\t\tRTW_PRINT_SEL(sel, ADPT_FMT\"- hw port(%d) mac_addr =\"MAC_FMT\"\\n\",\n\t\t\t\tADPT_ARG(iface), iface->hw_port, MAC_ARG(mac_addr));\n\t\t}\n\t}\n#endif\n}\n\n#ifdef RTW_HALMAC\nvoid rtw_hal_hw_port_enable(_adapter *adapter)\n{\n#if 1\n\tu8 port_enable = _TRUE;\n\n\trtw_hal_set_hwreg(adapter, HW_VAR_PORT_CFG, &port_enable);\n#else\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct rtw_halmac_bcn_ctrl bcn_ctrl;\n\n\t_rtw_memset(&bcn_ctrl, 0, sizeof(struct rtw_halmac_bcn_ctrl));\n\tbcn_ctrl.enable_bcn = 1;\n\tbcn_ctrl.rx_bssid_fit = 1;\n\tbcn_ctrl.rxbcn_rpt = 1;\n\n\t/*rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport,\n\t\t\t\tstruct rtw_halmac_bcn_ctrl *bcn_ctrl)*/\n\tif (rtw_halmac_set_bcn_ctrl(dvobj, get_hw_port(adapter), &bcn_ctrl) == -1) {\n\t\tRTW_ERR(ADPT_FMT\" - hw port(%d) enable fail!!\\n\", ADPT_ARG(adapter), get_hw_port(adapter));\n\t\trtw_warn_on(1);\n\t}\n#endif\n}\nvoid rtw_hal_hw_port_disable(_adapter *adapter)\n{\n\tu8 port_enable = _FALSE;\n\n\trtw_hal_set_hwreg(adapter, HW_VAR_PORT_CFG, &port_enable);\n}\n\nvoid rtw_restore_hw_port_cfg(_adapter *adapter)\n{\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\n#else\n\tint i;\n\t_adapter *iface;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface)\n\t\t\trtw_hal_hw_port_enable(iface);\n\t}\n#endif\n}\n#endif\n\nvoid rtw_mi_set_mac_addr(_adapter *adapter)\n{\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\trtw_mi_set_mbid_cam(adapter);\n#else\n\tint i;\n\t_adapter *iface;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface)\n\t\t\trtw_hal_set_hwreg(iface, HW_VAR_MAC_ADDR, adapter_mac_addr(iface));\n\t}\n#endif\n\tif (1)\n\t\trtw_hal_dump_macaddr(RTW_DBGDUMP, adapter);\n}\n\nvoid rtw_init_hal_com_default_value(PADAPTER Adapter)\n{\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(Adapter);\n\tstruct registry_priv *regsty = adapter_to_regsty(Adapter);\n\n\tpHalData->AntDetection = 1;\n\tpHalData->antenna_test = _FALSE;\n\tpHalData->RegIQKFWOffload = regsty->iqk_fw_offload;\n\tpHalData->ch_switch_offload = regsty->ch_switch_offload;\n\tpHalData->multi_ch_switch_mode = 0;\n#ifdef RTW_REDUCE_SCAN_SWITCH_CH_TIME\n\tif (pHalData->ch_switch_offload == 0)\n\t\tpHalData->ch_switch_offload = 1;\n#endif\n}\n\n#ifdef CONFIG_FW_C2H_REG\nvoid c2h_evt_clear(_adapter *adapter)\n{\n\trtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);\n}\n\ns32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf)\n{\n\ts32 ret = _FAIL;\n\tint i;\n\tu8 trigger;\n\n\tif (buf == NULL)\n\t\tgoto exit;\n\n\ttrigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);\n\n\tif (trigger == C2H_EVT_HOST_CLOSE) {\n\t\tgoto exit; /* Not ready */\n\t} else if (trigger != C2H_EVT_FW_CLOSE) {\n\t\tgoto clear_evt; /* Not a valid value */\n\t}\n\n\t_rtw_memset(buf, 0, C2H_REG_LEN);\n\n\t/* Read ID, LEN, SEQ */\n\tSET_C2H_ID_88XX(buf, rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL));\n\tSET_C2H_SEQ_88XX(buf, rtw_read8(adapter, REG_C2HEVT_CMD_SEQ_88XX));\n\tSET_C2H_PLEN_88XX(buf, rtw_read8(adapter, REG_C2HEVT_CMD_LEN_88XX));\n\n\tif (0) {\n\t\tRTW_INFO(\"%s id=0x%02x, seq=%u, plen=%u, trigger=0x%02x\\n\", __func__\n\t\t\t, C2H_ID_88XX(buf), C2H_SEQ_88XX(buf), C2H_PLEN_88XX(buf), trigger);\n\t}\n\n\t/* Read the content */\n\tfor (i = 0; i < C2H_PLEN_88XX(buf); i++)\n\t\t*(C2H_PAYLOAD_88XX(buf) + i) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);\n\n\tRTW_DBG_DUMP(\"payload: \", C2H_PAYLOAD_88XX(buf), C2H_PLEN_88XX(buf));\n\n\tret = _SUCCESS;\n\nclear_evt:\n\t/*\n\t* Clear event to notify FW we have read the command.\n\t* If this field isn't clear, the FW won't update the next command message.\n\t*/\n\tc2h_evt_clear(adapter);\n\nexit:\n\treturn ret;\n}\n#endif /* CONFIG_FW_C2H_REG */\n\n#ifdef CONFIG_FW_C2H_PKT\n#ifndef DBG_C2H_PKT_PRE_HDL\n#define DBG_C2H_PKT_PRE_HDL 0\n#endif\n#ifndef DBG_C2H_PKT_HDL\n#define DBG_C2H_PKT_HDL 0\n#endif\nvoid rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len)\n{\n#ifdef RTW_HALMAC\n\t/* TODO: extract hal_mac IC's code here*/\n#else\n\tu8 parse_fail = 0;\n\tu8 hdl_here = 0;\n\ts32 ret = _FAIL;\n\tu8 id, seq, plen;\n\tu8 *payload;\n\n\tif (rtw_hal_c2h_pkt_hdr_parse(adapter, buf, len, &id, &seq, &plen, &payload) != _SUCCESS) {\n\t\tparse_fail = 1;\n\t\tgoto exit;\n\t}\n\n\thdl_here = rtw_hal_c2h_id_handle_directly(adapter, id, seq, plen, payload) == _TRUE ? 1 : 0;\n\tif (hdl_here) \n\t\tret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload);\n\telse\n\t\tret = rtw_c2h_packet_wk_cmd(adapter, buf, len);\n\nexit:\n\tif (parse_fail)\n\t\tRTW_ERR(\"%s parse fail, buf=%p, len=:%u\\n\", __func__, buf, len);\n\telse if (ret != _SUCCESS || DBG_C2H_PKT_PRE_HDL > 0) {\n\t\tRTW_PRINT(\"%s: id=0x%02x, seq=%u, plen=%u, %s %s\\n\", __func__, id, seq, plen\n\t\t\t, hdl_here ? \"handle\" : \"enqueue\"\n\t\t\t, ret == _SUCCESS ? \"ok\" : \"fail\"\n\t\t);\n\t\tif (DBG_C2H_PKT_PRE_HDL >= 2)\n\t\t\tRTW_PRINT_DUMP(\"dump: \", buf, len);\n\t}\n#endif\n}\n\nvoid rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len)\n{\n#ifdef RTW_HALMAC\n\tadapter->hal_func.hal_mac_c2h_handler(adapter, buf, len);\n#else\n\tu8 parse_fail = 0;\n\tu8 bypass = 0;\n\ts32 ret = _FAIL;\n\tu8 id, seq, plen;\n\tu8 *payload;\n\n\tif (rtw_hal_c2h_pkt_hdr_parse(adapter, buf, len, &id, &seq, &plen, &payload) != _SUCCESS) {\n\t\tparse_fail = 1;\n\t\tgoto exit;\n\t}\n\n#ifdef CONFIG_WOWLAN\n\tif (adapter_to_pwrctl(adapter)->wowlan_mode == _TRUE) {\n\t\tbypass = 1;\n\t\tret = _SUCCESS;\n\t\tgoto exit;\n\t}\n#endif\n\n\tret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload);\n\nexit:\n\tif (parse_fail)\n\t\tRTW_ERR(\"%s parse fail, buf=%p, len=:%u\\n\", __func__, buf, len);\n\telse if (ret != _SUCCESS || bypass || DBG_C2H_PKT_HDL > 0) {\n\t\tRTW_PRINT(\"%s: id=0x%02x, seq=%u, plen=%u, %s %s\\n\", __func__, id, seq, plen\n\t\t\t, !bypass ? \"handle\" : \"bypass\"\n\t\t\t, ret == _SUCCESS ? \"ok\" : \"fail\"\n\t\t);\n\t\tif (DBG_C2H_PKT_HDL >= 2)\n\t\t\tRTW_PRINT_DUMP(\"dump: \", buf, len);\n\t}\n#endif\n}\n#endif /* CONFIG_FW_C2H_PKT */\n\nvoid c2h_iqk_offload(_adapter *adapter, u8 *data, u8 len)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct submit_ctx *iqk_sctx = &hal_data->iqk_sctx;\n\n\tRTW_INFO(\"IQK offload finish in %dms\\n\", rtw_get_passing_time_ms(iqk_sctx->submit_time));\n\tif (0)\n\t\tRTW_INFO_DUMP(\"C2H_IQK_FINISH: \", data, len);\n\n\trtw_sctx_done(&iqk_sctx);\n}\n\nint c2h_iqk_offload_wait(_adapter *adapter, u32 timeout_ms)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct submit_ctx *iqk_sctx = &hal_data->iqk_sctx;\n\n\tiqk_sctx->submit_time = rtw_get_current_time();\n\tiqk_sctx->timeout_ms = timeout_ms;\n\tiqk_sctx->status = RTW_SCTX_SUBMITTED;\n\n\treturn rtw_sctx_wait(iqk_sctx, __func__);\n}\n\n#define\tGET_C2H_MAC_HIDDEN_RPT_UUID_X(_data)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 0, 0, 8)\n#define\tGET_C2H_MAC_HIDDEN_RPT_UUID_Y(_data)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8)\n#define\tGET_C2H_MAC_HIDDEN_RPT_UUID_Z(_data)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 5)\n#define\tGET_C2H_MAC_HIDDEN_RPT_UUID_CRC(_data)\t\t\tLE_BITS_TO_2BYTE(((u8 *)(_data)) + 2, 5, 11)\n#define\tGET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(_data)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 0, 4)\n#define\tGET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(_data)\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 4, 3)\n#define\tGET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(_data)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 7, 1)\n#define\tGET_C2H_MAC_HIDDEN_RPT_WL_FUNC(_data)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 0, 4)\n#define\tGET_C2H_MAC_HIDDEN_RPT_HW_STYPE(_data)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 4, 4)\n#define\tGET_C2H_MAC_HIDDEN_RPT_BW(_data)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 3)\n#define\tGET_C2H_MAC_HIDDEN_RPT_ANT_NUM(_data)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 5, 3)\n#define\tGET_C2H_MAC_HIDDEN_RPT_80211_PROTOCOL(_data)\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 2, 2)\n#define\tGET_C2H_MAC_HIDDEN_RPT_NIC_ROUTER(_data)\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 6, 2)\n\n#ifndef DBG_C2H_MAC_HIDDEN_RPT_HANDLE\n#define DBG_C2H_MAC_HIDDEN_RPT_HANDLE 0\n#endif\n\n#ifdef CONFIG_RTW_MAC_HIDDEN_RPT\nint c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len)\n{\n\tHAL_DATA_TYPE\t*hal_data = GET_HAL_DATA(adapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tint ret = _FAIL;\n\n\tu32 uuid;\n\tu8 uuid_x;\n\tu8 uuid_y;\n\tu8 uuid_z;\n\tu16 uuid_crc;\n\n\tu8 hci_type;\n\tu8 package_type;\n\tu8 tr_switch;\n\tu8 wl_func;\n\tu8 hw_stype;\n\tu8 bw;\n\tu8 ss_num = 4;\n\tu8 ant_num;\n\tu8 protocol;\n\tu8 nic;\n\n\tint i;\n\n\tif (len < MAC_HIDDEN_RPT_LEN) {\n\t\tRTW_WARN(\"%s len(%u) < %d\\n\", __func__, len, MAC_HIDDEN_RPT_LEN);\n\t\tgoto exit;\n\t}\n\n\tuuid_x = GET_C2H_MAC_HIDDEN_RPT_UUID_X(data);\n\tuuid_y = GET_C2H_MAC_HIDDEN_RPT_UUID_Y(data);\n\tuuid_z = GET_C2H_MAC_HIDDEN_RPT_UUID_Z(data);\n\tuuid_crc = GET_C2H_MAC_HIDDEN_RPT_UUID_CRC(data);\n\n\thci_type = GET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(data);\n\tpackage_type = GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(data);\n\n\ttr_switch = GET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(data);\n\n\twl_func = GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(data);\n\thw_stype = GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(data);\n\n\tbw = GET_C2H_MAC_HIDDEN_RPT_BW(data);\n\tant_num = GET_C2H_MAC_HIDDEN_RPT_ANT_NUM(data);\n\n\tprotocol = GET_C2H_MAC_HIDDEN_RPT_80211_PROTOCOL(data);\n\tnic = GET_C2H_MAC_HIDDEN_RPT_NIC_ROUTER(data);\n\n\tif (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) {\n\t\tfor (i = 0; i < len; i++)\n\t\t\tRTW_PRINT(\"%s: 0x%02X\\n\", __func__, *(data + i));\n\n\t\tRTW_PRINT(\"uuid x:0x%02x y:0x%02x z:0x%x crc:0x%x\\n\", uuid_x, uuid_y, uuid_z, uuid_crc);\n\t\tRTW_PRINT(\"hci_type:0x%x\\n\", hci_type);\n\t\tRTW_PRINT(\"package_type:0x%x\\n\", package_type);\n\t\tRTW_PRINT(\"tr_switch:0x%x\\n\", tr_switch);\n\t\tRTW_PRINT(\"wl_func:0x%x\\n\", wl_func);\n\t\tRTW_PRINT(\"hw_stype:0x%x\\n\", hw_stype);\n\t\tRTW_PRINT(\"bw:0x%x\\n\", bw);\n\t\tRTW_PRINT(\"ant_num:0x%x\\n\", ant_num);\n\t\tRTW_PRINT(\"protocol:0x%x\\n\", protocol);\n\t\tRTW_PRINT(\"nic:0x%x\\n\", nic);\n\t}\n\n#if defined(CONFIG_RTL8822C)\n\tif (IS_8822C_SERIES(hal_data->version_id)) {\n\t\t#define GET_C2H_MAC_HIDDEN_RPT_SS_NUM(_data)\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 3, 2)\n\t\tss_num = GET_C2H_MAC_HIDDEN_RPT_SS_NUM(data);\n\n\t\tif (DBG_C2H_MAC_HIDDEN_RPT_HANDLE)\n\t\t\tRTW_PRINT(\"ss_num:0x%x\\n\", ss_num);\n\t}\n#endif\n\n#if defined(CONFIG_RTL8822C)\n\tif (IS_8822C_SERIES(hal_data->version_id)) {\n\t\tif (hw_stype == 0xE)\n\t\t\thal_data->rf_type = RF_1T2R; /* txpath:A, rxpath:AB */\n\t}\n#endif\n\thal_data->PackageType = package_type;\n\thal_spec->hci_type = hci_type;\n\thal_spec->wl_func &= mac_hidden_wl_func_to_hal_wl_func(wl_func);\n\thal_spec->bw_cap &= mac_hidden_max_bw_to_hal_bw_cap(bw);\n\thal_spec->proto_cap &= mac_hidden_proto_to_hal_proto_cap(protocol);\n\n\t/*\n\t* RF TX path num >= max_tx_cnt >= tx_nss_num\n\t* ex: RF TX path num(4) >= max_tx_cnt(2) >= tx_nss_num(1)\n\t* Select at most 2 out of 4 TX RF path to do 1SS 2TX\n\t*/\n\thal_spec->max_tx_cnt = rtw_min(hal_spec->max_tx_cnt, rf_type_to_rf_tx_cnt(hal_data->rf_type));\n\thal_spec->max_tx_cnt = rtw_min(hal_spec->max_tx_cnt, ant_num);\n\thal_spec->tx_nss_num = rtw_min(hal_spec->tx_nss_num, hal_spec->max_tx_cnt);\n\thal_spec->tx_nss_num = rtw_min(hal_spec->tx_nss_num, ss_num);\n\n\thal_spec->rx_nss_num = rtw_min(hal_spec->rx_nss_num, rf_type_to_rf_rx_cnt(hal_data->rf_type));\n\thal_spec->rx_nss_num = rtw_min(hal_spec->rx_nss_num, ant_num);\n\thal_spec->rx_nss_num = rtw_min(hal_spec->rx_nss_num, ss_num);\n\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n\nint c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len)\n{\n\tHAL_DATA_TYPE\t*hal_data = GET_HAL_DATA(adapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tint ret = _FAIL;\n\n\tint i;\n\n\tif (len < MAC_HIDDEN_RPT_2_LEN) {\n\t\tRTW_WARN(\"%s len(%u) < %d\\n\", __func__, len, MAC_HIDDEN_RPT_2_LEN);\n\t\tgoto exit;\n\t}\n\n\tif (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) {\n\t\tfor (i = 0; i < len; i++)\n\t\t\tRTW_PRINT(\"%s: 0x%02X\\n\", __func__, *(data + i));\n\t}\n\n\t#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)\n\tif (IS_8188F(hal_data->version_id) || IS_8188GTV(hal_data->version_id)) {\n\t\t#define GET_C2H_MAC_HIDDEN_RPT_IRV(_data)\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 0, 0, 4)\n\t\tu8 irv = GET_C2H_MAC_HIDDEN_RPT_IRV(data);\n\n\t\tif (DBG_C2H_MAC_HIDDEN_RPT_HANDLE)\n\t\t\tRTW_PRINT(\"irv:0x%x\\n\", irv);\n\n\t\tif(irv != 0xf)\n\t\t\thal_data->version_id.CUTVersion = irv;\n\t}\n\t#endif\n\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n\nint hal_read_mac_hidden_rpt(_adapter *adapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(adapter);\n\tint ret = _FAIL;\n\tint ret_fwdl;\n\tu8 mac_hidden_rpt[MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN] = {0};\n\tsystime start = rtw_get_current_time();\n\tu32 cnt = 0;\n\tu32 timeout_ms = 800;\n\tu32 min_cnt = 10;\n\tu8 id = C2H_DEFEATURE_RSVD;\n\tint i;\n\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)\n\tu8 hci_type = rtw_get_intf_type(adapter);\n\n\tif ((hci_type == RTW_USB || hci_type == RTW_PCIE)\n\t\t&& !rtw_is_hw_init_completed(adapter))\n\t\trtw_hal_power_on(adapter);\n#endif\n\n\t/* inform FW mac hidden rpt from reg is needed */\n\trtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DEFEATURE_RSVD);\n\n\t/* download FW */\n\tpHalData->not_xmitframe_fw_dl = 1;\n\tret_fwdl = rtw_hal_fw_dl(adapter, _FALSE);\n\tpHalData->not_xmitframe_fw_dl = 0;\n\tif (ret_fwdl != _SUCCESS)\n\t\tgoto mac_hidden_rpt_hdl;\n\n\t/* polling for data ready */\n\tstart = rtw_get_current_time();\n\tdo {\n\t\tcnt++;\n\t\tid = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);\n\t\tif (id == C2H_MAC_HIDDEN_RPT || RTW_CANNOT_IO(adapter))\n\t\t\tbreak;\n\t\trtw_msleep_os(10);\n\t} while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt);\n\n\tif (id == C2H_MAC_HIDDEN_RPT) {\n\t\t/* read data */\n\t\tfor (i = 0; i < MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN; i++)\n\t\t\tmac_hidden_rpt[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);\n\t}\n\n\t/* inform FW mac hidden rpt has read */\n\trtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DBG);\n\nmac_hidden_rpt_hdl:\n\tc2h_mac_hidden_rpt_hdl(adapter, mac_hidden_rpt, MAC_HIDDEN_RPT_LEN);\n\tc2h_mac_hidden_rpt_2_hdl(adapter, mac_hidden_rpt + MAC_HIDDEN_RPT_LEN, MAC_HIDDEN_RPT_2_LEN);\n\n\tif (ret_fwdl == _SUCCESS && id == C2H_MAC_HIDDEN_RPT)\n\t\tret = _SUCCESS;\n\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)\n\tif ((hci_type == RTW_USB || hci_type == RTW_PCIE)\n\t\t&& !rtw_is_hw_init_completed(adapter))\n\t\trtw_hal_power_off(adapter);\n#endif\n\n\tRTW_INFO(\"%s %s! (%u, %dms), fwdl:%d, id:0x%02x\\n\", __func__\n\t\t, (ret == _SUCCESS) ? \"OK\" : \"Fail\", cnt, rtw_get_passing_time_ms(start), ret_fwdl, id);\n\n\treturn ret;\n}\n#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */\n\nint c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len)\n{\n\tHAL_DATA_TYPE\t*hal_data = GET_HAL_DATA(adapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tint ret = _FAIL;\n\n\tint i;\n\n\tif (len < DEFEATURE_DBG_LEN) {\n\t\tRTW_WARN(\"%s len(%u) < %d\\n\", __func__, len, DEFEATURE_DBG_LEN);\n\t\tgoto exit;\n\t}\n\n\tfor (i = 0; i < len; i++)\n\t\tRTW_PRINT(\"%s: 0x%02X\\n\", __func__, *(data + i));\n\n\tret = _SUCCESS;\n\t\nexit:\n\treturn ret;\n}\n\n#ifndef DBG_CUSTOMER_STR_RPT_HANDLE\n#define DBG_CUSTOMER_STR_RPT_HANDLE 0\n#endif\n\n#ifdef CONFIG_RTW_CUSTOMER_STR\ns32 rtw_hal_h2c_customer_str_req(_adapter *adapter)\n{\n\tu8 h2c_data[H2C_CUSTOMER_STR_REQ_LEN] = {0};\n\n\tSET_H2CCMD_CUSTOMER_STR_REQ_EN(h2c_data, 1);\n\treturn rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_REQ, H2C_CUSTOMER_STR_REQ_LEN, h2c_data);\n}\n\n#define\tC2H_CUSTOMER_STR_RPT_BYTE0(_data)\t\t((u8 *)(_data))\n#define\tC2H_CUSTOMER_STR_RPT_2_BYTE8(_data)\t\t((u8 *)(_data))\n\nint c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tint ret = _FAIL;\n\tint i;\n\n\tif (len < CUSTOMER_STR_RPT_LEN) {\n\t\tRTW_WARN(\"%s len(%u) < %d\\n\", __func__, len, CUSTOMER_STR_RPT_LEN);\n\t\tgoto exit;\n\t}\n\n\tif (DBG_CUSTOMER_STR_RPT_HANDLE)\n\t\tRTW_PRINT_DUMP(\"customer_str_rpt: \", data, CUSTOMER_STR_RPT_LEN);\n\n\t_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\n\tif (dvobj->customer_str_sctx != NULL) {\n\t\tif (dvobj->customer_str_sctx->status != RTW_SCTX_SUBMITTED)\n\t\t\tRTW_WARN(\"%s invalid sctx.status:%d\\n\", __func__, dvobj->customer_str_sctx->status);\n\t\t_rtw_memcpy(dvobj->customer_str,  C2H_CUSTOMER_STR_RPT_BYTE0(data), CUSTOMER_STR_RPT_LEN);\n\t\tdvobj->customer_str_sctx->status = RTX_SCTX_CSTR_WAIT_RPT2;\n\t} else\n\t\tRTW_WARN(\"%s sctx not set\\n\", __func__);\n\n\t_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n\nint c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tint ret = _FAIL;\n\tint i;\n\n\tif (len < CUSTOMER_STR_RPT_2_LEN) {\n\t\tRTW_WARN(\"%s len(%u) < %d\\n\", __func__, len, CUSTOMER_STR_RPT_2_LEN);\n\t\tgoto exit;\n\t}\n\n\tif (DBG_CUSTOMER_STR_RPT_HANDLE)\n\t\tRTW_PRINT_DUMP(\"customer_str_rpt_2: \", data, CUSTOMER_STR_RPT_2_LEN);\n\n\t_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\n\tif (dvobj->customer_str_sctx != NULL) {\n\t\tif (dvobj->customer_str_sctx->status != RTX_SCTX_CSTR_WAIT_RPT2)\n\t\t\tRTW_WARN(\"%s rpt not ready\\n\", __func__);\n\t\t_rtw_memcpy(dvobj->customer_str + CUSTOMER_STR_RPT_LEN,  C2H_CUSTOMER_STR_RPT_2_BYTE8(data), CUSTOMER_STR_RPT_2_LEN);\n\t\trtw_sctx_done(&dvobj->customer_str_sctx);\n\t} else\n\t\tRTW_WARN(\"%s sctx not set\\n\", __func__);\n\n\t_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n\n/* read customer str */\ns32 rtw_hal_customer_str_read(_adapter *adapter, u8 *cs)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct submit_ctx sctx;\n\ts32 ret = _SUCCESS;\n\n\t_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\tif (dvobj->customer_str_sctx != NULL)\n\t\tret = _FAIL;\n\telse {\n\t\trtw_sctx_init(&sctx, 2 * 1000);\n\t\tdvobj->customer_str_sctx = &sctx;\n\t}\n\t_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\n\tif (ret == _FAIL) {\n\t\tRTW_WARN(\"%s another handle ongoing\\n\", __func__);\n\t\tgoto exit;\n\t}\n\n\tret = rtw_customer_str_req_cmd(adapter);\n\tif (ret != _SUCCESS) {\n\t\tRTW_WARN(\"%s read cmd fail\\n\", __func__);\n\t\t_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\t\tdvobj->customer_str_sctx = NULL;\n\t\t_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\t\tgoto exit;\n\t}\n\n\t/* wait till rpt done or timeout */\n\trtw_sctx_wait(&sctx, __func__);\n\n\t_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\tdvobj->customer_str_sctx = NULL;\n\tif (sctx.status == RTW_SCTX_DONE_SUCCESS)\n\t\t_rtw_memcpy(cs, dvobj->customer_str, RTW_CUSTOMER_STR_LEN);\n\telse\n\t\tret = _FAIL;\n\t_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\nexit:\n\treturn ret;\n}\n\ns32 rtw_hal_h2c_customer_str_write(_adapter *adapter, const u8 *cs)\n{\n\tu8 h2c_data_w1[H2C_CUSTOMER_STR_W1_LEN] = {0};\n\tu8 h2c_data_w2[H2C_CUSTOMER_STR_W2_LEN] = {0};\n\tu8 h2c_data_w3[H2C_CUSTOMER_STR_W3_LEN] = {0};\n\ts32 ret;\n\n\tSET_H2CCMD_CUSTOMER_STR_W1_EN(h2c_data_w1, 1);\n\t_rtw_memcpy(H2CCMD_CUSTOMER_STR_W1_BYTE0(h2c_data_w1), cs, 6);\n\n\tSET_H2CCMD_CUSTOMER_STR_W2_EN(h2c_data_w2, 1);\n\t_rtw_memcpy(H2CCMD_CUSTOMER_STR_W2_BYTE6(h2c_data_w2), cs + 6, 6);\n\n\tSET_H2CCMD_CUSTOMER_STR_W3_EN(h2c_data_w3, 1);\n\t_rtw_memcpy(H2CCMD_CUSTOMER_STR_W3_BYTE12(h2c_data_w3), cs + 6 + 6, 4);\n\n\tret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W1, H2C_CUSTOMER_STR_W1_LEN, h2c_data_w1);\n\tif (ret != _SUCCESS) {\n\t\tRTW_WARN(\"%s w1 fail\\n\", __func__);\n\t\tgoto exit;\n\t}\n\n\tret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W2, H2C_CUSTOMER_STR_W2_LEN, h2c_data_w2);\n\tif (ret != _SUCCESS) {\n\t\tRTW_WARN(\"%s w2 fail\\n\", __func__);\n\t\tgoto exit;\n\t}\n\n\tret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W3, H2C_CUSTOMER_STR_W3_LEN, h2c_data_w3);\n\tif (ret != _SUCCESS) {\n\t\tRTW_WARN(\"%s w3 fail\\n\", __func__);\n\t\tgoto exit;\n\t}\n\nexit:\n\treturn ret;\n}\n\n/* write customer str and check if value reported is the same as requested */\ns32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct submit_ctx sctx;\n\ts32 ret = _SUCCESS;\n\n\t_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\tif (dvobj->customer_str_sctx != NULL)\n\t\tret = _FAIL;\n\telse {\n\t\trtw_sctx_init(&sctx, 2 * 1000);\n\t\tdvobj->customer_str_sctx = &sctx;\n\t}\n\t_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\n\tif (ret == _FAIL) {\n\t\tRTW_WARN(\"%s another handle ongoing\\n\", __func__);\n\t\tgoto exit;\n\t}\n\n\tret = rtw_customer_str_write_cmd(adapter, cs);\n\tif (ret != _SUCCESS) {\n\t\tRTW_WARN(\"%s write cmd fail\\n\", __func__);\n\t\t_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\t\tdvobj->customer_str_sctx = NULL;\n\t\t_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\t\tgoto exit;\n\t}\n\n\tret = rtw_customer_str_req_cmd(adapter);\n\tif (ret != _SUCCESS) {\n\t\tRTW_WARN(\"%s read cmd fail\\n\", __func__);\n\t\t_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\t\tdvobj->customer_str_sctx = NULL;\n\t\t_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\t\tgoto exit;\n\t}\n\n\t/* wait till rpt done or timeout */\n\trtw_sctx_wait(&sctx, __func__);\n\n\t_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\tdvobj->customer_str_sctx = NULL;\n\tif (sctx.status == RTW_SCTX_DONE_SUCCESS) {\n\t\tif (_rtw_memcmp(cs, dvobj->customer_str, RTW_CUSTOMER_STR_LEN) != _TRUE) {\n\t\t\tRTW_WARN(\"%s read back check fail\\n\", __func__);\n\t\t\tRTW_INFO_DUMP(\"write req: \", cs, RTW_CUSTOMER_STR_LEN);\n\t\t\tRTW_INFO_DUMP(\"read back: \", dvobj->customer_str, RTW_CUSTOMER_STR_LEN);\n\t\t\tret = _FAIL;\n\t\t}\n\t} else\n\t\tret = _FAIL;\n\t_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);\n\nexit:\n\treturn ret;\n}\n#endif /* CONFIG_RTW_CUSTOMER_STR */\n\n#ifdef RTW_PER_CMD_SUPPORT_FW\n#define H2C_REQ_PER_RPT_LEN 5\n#define SET_H2CCMD_REQ_PER_RPT_GROUP_MACID(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)\n#define SET_H2CCMD_REQ_PER_RPT_RPT_TYPE(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)\n#define SET_H2CCMD_REQ_PER_RPT_MACID_BMAP(__pH2CCmd, __Value)\tSET_BITS_TO_LE_4BYTE(__pH2CCmd + 1, 0, 32, __Value)\n\nu8 rtw_hal_set_req_per_rpt_cmd(_adapter *adapter, u8 group_macid,\n\t\t\t\t      u8 rpt_type, u32 macid_bitmap)\n{\n\tu8 ret = _FAIL;\n\tu8 cmd_buf[H2C_REQ_PER_RPT_LEN] = {0};\n\n\tSET_H2CCMD_REQ_PER_RPT_GROUP_MACID(cmd_buf, group_macid);\n\tSET_H2CCMD_REQ_PER_RPT_RPT_TYPE(cmd_buf, rpt_type);\n\tSET_H2CCMD_REQ_PER_RPT_MACID_BMAP(cmd_buf, macid_bitmap);\n\n\tret = rtw_hal_fill_h2c_cmd(adapter, \n\t\t\t\t   H2C_REQ_PER_RPT, \n\t\t\t\t   H2C_REQ_PER_RPT_LEN, \n\t\t\t\t   cmd_buf);\n\treturn ret;\n}\n\n#define\tGET_C2H_PER_RATE_RPT_TYPE0_MACID0(_data)\tLE_BITS_TO_1BYTE(((u8 *)(_data)), 0, 8)\n#define\tGET_C2H_PER_RATE_RPT_TYPE0_PER0(_data)\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8)\n#define\tGET_C2H_PER_RATE_RPT_TYPE0_RATE0(_data)\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 8)\n#define\tGET_C2H_PER_RATE_RPT_TYPE0_BW0(_data)\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 3, 0, 2)\n#define\tGET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT0(_data)\tLE_BITS_TO_2BYTE(((u8 *)(_data)) + 4, 0, 16)\n#define\tGET_C2H_PER_RATE_RPT_TYPE0_MACID1(_data)\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 8)\n#define\tGET_C2H_PER_RATE_RPT_TYPE0_PER1(_data)\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 0, 8)\n#define\tGET_C2H_PER_RATE_RPT_TYPE0_RATE1(_data)\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 8, 0, 8)\n#define\tGET_C2H_PER_RATE_RPT_TYPE0_BW1(_data)\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 9, 0, 2)\n#define\tGET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT1(_data)\tLE_BITS_TO_2BYTE(((u8 *)(_data)) + 10, 0, 16)\n\n#define\tGET_C2H_PER_RATE_RPT_TYPE1_MACID0(_data)\tLE_BITS_TO_1BYTE(((u8 *)(_data)), 0, 8)\n#define\tGET_C2H_PER_RATE_RPT_TYPE1_PER0(_data)\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8)\n#define\tGET_C2H_PER_RATE_RPT_TYPE1_RATE0(_data)\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 8)\n#define\tGET_C2H_PER_RATE_RPT_TYPE1_BW0(_data)\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 3, 0, 2)\n#define\tGET_C2H_PER_RATE_RPT_TYPE1_MACID1(_data)\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 0, 8)\n#define\tGET_C2H_PER_RATE_RPT_TYPE1_PER1(_data)\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 0, 8)\n#define\tGET_C2H_PER_RATE_RPT_TYPE1_RATE1(_data)\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 8)\n#define\tGET_C2H_PER_RATE_RPT_TYPE1_BW1(_data)\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 0, 2)\n#define\tGET_C2H_PER_RATE_RPT_TYPE1_MACID2(_data)\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 8, 0, 8)\n#define\tGET_C2H_PER_RATE_RPT_TYPE1_PER2(_data)\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 9, 0, 8)\n#define\tGET_C2H_PER_RATE_RPT_TYPE1_RATE2(_data)\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 10, 0, 8)\n#define\tGET_C2H_PER_RATE_RPT_TYPE1_BW2(_data)\t\tLE_BITS_TO_1BYTE(((u8 *)(_data)) + 11, 0, 2)\n\nstatic void per_rate_rpt_update(_adapter *adapter, u8 mac_id,\n\t\t\t\tu8 per, u8 rate,\n\t\t\t\tu8 bw, u8 total_pkt)\n{\n#ifdef CONFIG_RTW_MESH\n\trtw_ieee80211s_update_metric(adapter, mac_id,\n\t\t\t\t     per, rate,\n\t\t\t\t     bw, total_pkt);\n#endif\n}\n\nint c2h_per_rate_rpt_hdl(_adapter *adapter, u8 *data, u8 len)\n{\n\t/* Now only consider type0, since it covers all params in type1\n\t * type0: mac_id, per, rate, bw, total_pkt\n\t * type1: mac_id, per, rate, bw\n\t */\n\tu8 mac_id[2] = {0}, per[2] = {0}, rate[2] = {0}, bw[2] = {0};\n\tu16 total_pkt[2] = {0};\n\tint ret = _FAIL, i, macid_cnt = 0;\n\n\t/* type0:\n\t * 1 macid includes   6 bytes info + 1 byte 0xff\n\t * 2 macid includes 2*6 bytes info\n\t */\n\tif (!(len == 7 || len == 12)) {\n\t\tRTW_WARN(\"%s len(%u) != 7 or 12\\n\", __FUNCTION__, len);\n\t\tgoto exit;\n\t}\n\n\tmacid_cnt++;\n\tmac_id[0] = GET_C2H_PER_RATE_RPT_TYPE0_MACID0(data);\n\tper[0] = GET_C2H_PER_RATE_RPT_TYPE0_PER0(data);\n\trate[0] = GET_C2H_PER_RATE_RPT_TYPE0_RATE0(data);\n\tbw[0] = GET_C2H_PER_RATE_RPT_TYPE0_BW0(data);\n\ttotal_pkt[0] = GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT0(data);\n\n\tmac_id[1] = GET_C2H_PER_RATE_RPT_TYPE0_MACID1(data);\n\t/* 0xff means no report anymore */\n\tif (mac_id[1] == 0xff)\n\t\tgoto update_per;\n\tif (len != 12) {\n\t\tRTW_WARN(\"%s incorrect format\\n\", __FUNCTION__);\n\t\tgoto exit;\n\t}\n\tmacid_cnt++;\n\tper[1] = GET_C2H_PER_RATE_RPT_TYPE0_PER1(data);\n\trate[1] = GET_C2H_PER_RATE_RPT_TYPE0_RATE1(data);\n\tbw[1] = GET_C2H_PER_RATE_RPT_TYPE0_BW1(data);\n\ttotal_pkt[1] = GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT1(data);\n\nupdate_per:\n\tfor (i = 0; i < macid_cnt; i++) {\n\t\tRTW_DBG(\"[%s] type0 rpt[%d]: macid = %u, per = %u, \"\n\t\t\t\"rate = %u, bw = %u, total_pkt = %u\\n\",\n\t\t\t__FUNCTION__, i, mac_id[i], per[i],\n\t\t\trate[i], bw[i], total_pkt[i]);\n\t\tper_rate_rpt_update(adapter, mac_id[i],\n\t\t\t\t    per[i], rate[i],\n\t\t\t\t    bw[i], total_pkt[i]);\n\t}\n\tret = _SUCCESS;\nexit:\n\treturn ret;\n}\n#endif /* RTW_PER_CMD_SUPPORT_FW */\n\nvoid rtw_hal_update_sta_wset(_adapter *adapter, struct sta_info *psta)\n{\n\tu8 w_set = 0;\n\n\tif (psta->wireless_mode & WIRELESS_11B)\n\t\tw_set |= WIRELESS_CCK;\n\n\tif ((psta->wireless_mode & WIRELESS_11G) || (psta->wireless_mode & WIRELESS_11A))\n\t\tw_set |= WIRELESS_OFDM;\n\n\tif (psta->wireless_mode & WIRELESS_11_24N)\n\t\tw_set |= WIRELESS_HT;\n\n\tif ((psta->wireless_mode & WIRELESS_11AC) || (psta->wireless_mode & WIRELESS_11_5N))\n\t\tw_set |= WIRELESS_VHT;\n\n\tpsta->cmn.support_wireless_set = w_set;\n}\n\nvoid rtw_hal_update_sta_mimo_type(_adapter *adapter, struct sta_info *psta)\n{\n\ts8 tx_nss, rx_nss;\n\n\ttx_nss = rtw_get_sta_tx_nss(adapter, psta);\n\trx_nss =  rtw_get_sta_rx_nss(adapter, psta);\n\tif ((tx_nss == 1) && (rx_nss == 1))\n\t\tpsta->cmn.mimo_type = RF_1T1R;\n\telse if ((tx_nss == 1) && (rx_nss == 2))\n\t\tpsta->cmn.mimo_type = RF_1T2R;\n\telse if ((tx_nss == 2) && (rx_nss == 2))\n\t\tpsta->cmn.mimo_type = RF_2T2R;\n\telse if ((tx_nss == 2) && (rx_nss == 3))\n\t\tpsta->cmn.mimo_type = RF_2T3R;\n\telse if ((tx_nss == 2) && (rx_nss == 4))\n\t\tpsta->cmn.mimo_type = RF_2T4R;\n\telse if ((tx_nss == 3) && (rx_nss == 3))\n\t\tpsta->cmn.mimo_type = RF_3T3R;\n\telse if ((tx_nss == 3) && (rx_nss == 4))\n\t\tpsta->cmn.mimo_type = RF_3T4R;\n\telse if ((tx_nss == 4) && (rx_nss == 4))\n\t\tpsta->cmn.mimo_type = RF_4T4R;\n\telse\n\t\trtw_warn_on(1);\n\n#ifdef CONFIG_CTRL_TXSS_BY_TP\n\trtw_ctrl_txss_update_mimo_type(adapter, psta);\n#endif\n\n\tRTW_INFO(\"STA - MAC_ID:%d, Tx - %d SS, Rx - %d SS\\n\",\n\t\t\tpsta->cmn.mac_id, tx_nss, rx_nss);\n}\n\nvoid rtw_hal_update_sta_smps_cap(_adapter *adapter, struct sta_info *psta)\n{\n\t/*Spatial Multiplexing Power Save*/\n#if 0\n\tif (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) {\n\t\t#ifdef CONFIG_80211N_HT\n\t\tif (psta->htpriv.ht_option) {\n\t\t\tif (psta->htpriv.smps_cap == 0)\n\t\t\t\tpsta->cmn.sm_ps = SM_PS_STATIC;\n\t\t\telse if (psta->htpriv.smps_cap == 1)\n\t\t\t\tpsta->cmn.sm_ps = SM_PS_DYNAMIC;\n\t\t\telse\n\t\t\t\tpsta->cmn.sm_ps = SM_PS_DISABLE;\n\t\t}\n\t\t#endif /* CONFIG_80211N_HT */\n\t} else\n#endif\n\t\tpsta->cmn.sm_ps = SM_PS_DISABLE;\n\n\tRTW_INFO(\"STA - MAC_ID:%d, SM_PS %d\\n\",\n\t\t\tpsta->cmn.mac_id, psta->cmn.sm_ps);\n}\n\nu8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type)\n{\n\n\tu8 raid;\n\tif (IS_NEW_GENERATION_IC(adapter)) {\n\n\t\traid = (network_type & WIRELESS_11B)\t? RATEID_IDX_B\n\t\t       : RATEID_IDX_G;\n\t} else {\n\t\traid = (network_type & WIRELESS_11B)\t? RATR_INX_WIRELESS_B\n\t\t       : RATR_INX_WIRELESS_G;\n\t}\n\treturn raid;\n}\n\nvoid rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);\n\tu8 i, rf_type, tx_nss;\n\tu64 tx_ra_bitmap = 0, tmp64=0;\n\n\tif (psta == NULL)\n\t\treturn;\n\n\t/* b/g mode ra_bitmap  */\n\tfor (i = 0; i < sizeof(psta->bssrateset); i++) {\n\t\tif (psta->bssrateset[i])\n\t\t\ttx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i] & 0x7f);\n\t}\n\n#ifdef CONFIG_80211N_HT\nif (padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode)) {\n\trtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));\n\ttx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);\n#ifdef CONFIG_80211AC_VHT\n\tif (psta->vhtpriv.vht_option) {\n\t\t/* AC mode ra_bitmap */\n\t\ttx_ra_bitmap |= (rtw_vht_mcs_map_to_bitmap(psta->vhtpriv.vht_mcs_map, tx_nss) << 12);\n\t} else\n#endif /* CONFIG_80211AC_VHT */\n\tif (psta->htpriv.ht_option) {\n\t\t/* n mode ra_bitmap */\n\n\t\t/* Handling SMPS mode for AP MODE only*/\n\t\tif (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) {\n\t\t\t/*0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/\n\t\t\tif (psta->htpriv.smps_cap == 0 || psta->htpriv.smps_cap == 1) {\n\t\t\t\t/*operate with only one active receive chain // 11n-MCS rate <= MSC7*/\n\t\t\t\ttx_nss = rtw_min(tx_nss, 1);\n\t\t\t}\n\t\t}\n\n\t\ttmp64 = rtw_ht_mcs_set_to_bitmap(psta->htpriv.ht_cap.supp_mcs_set, tx_nss);\n\t\ttx_ra_bitmap |= (tmp64 << 12);\n\t}\n}\n#endif /* CONFIG_80211N_HT */\n\tpsta->cmn.ra_info.ramask = tx_ra_bitmap;\n\tpsta->init_rate = get_highest_rate_idx(tx_ra_bitmap) & 0x3f;\n}\n\nvoid rtw_hal_update_sta_ra_info(PADAPTER padapter, struct sta_info *psta)\n{\n\trtw_hal_update_sta_mimo_type(padapter, psta);\n\trtw_hal_update_sta_smps_cap(padapter, psta);\n\trtw_hal_update_sta_rate_mask(padapter, psta);\n}\n\nstatic u32 hw_bcn_ctrl_addr(_adapter *adapter, u8 hw_port)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\n\tif (hw_port >= hal_spec->port_num) {\n\t\tRTW_ERR(FUNC_ADPT_FMT\" HW Port(%d) invalid\\n\", FUNC_ADPT_ARG(adapter), hw_port);\n\t\trtw_warn_on(1);\n\t\treturn 0;\n\t}\n\n\tswitch (hw_port) {\n\tcase HW_PORT0:\n\t\treturn REG_BCN_CTRL;\n\tcase HW_PORT1:\n\t\treturn REG_BCN_CTRL_1;\n\t}\n\n\treturn 0;\n}\n\nstatic void rtw_hal_get_msr(_adapter *adapter, u8 *net_type)\n{\n#ifdef RTW_HALMAC\n\trtw_halmac_get_network_type(adapter_to_dvobj(adapter),\n\t\t\t\tadapter->hw_port, net_type);\n#else /* !RTW_HALMAC */\n\tswitch (adapter->hw_port) {\n\tcase HW_PORT0:\n\t\t/*REG_CR - BIT[17:16]-Network Type for port 1*/\n\t\t*net_type = rtw_read8(adapter, MSR) & 0x03;\n\t\tbreak;\n\tcase HW_PORT1:\n\t\t/*REG_CR - BIT[19:18]-Network Type for port 1*/\n\t\t*net_type = (rtw_read8(adapter, MSR) & 0x0C) >> 2;\n\t\tbreak;\n#if defined(CONFIG_RTL8814A)\n\tcase HW_PORT2:\n\t\t/*REG_CR_EXT- BIT[1:0]-Network Type for port 2*/\n\t\t*net_type = rtw_read8(adapter, MSR1) & 0x03;\n\t\tbreak;\n\tcase HW_PORT3:\n\t\t/*REG_CR_EXT- BIT[3:2]-Network Type for port 3*/\n\t\t*net_type = (rtw_read8(adapter, MSR1) & 0x0C) >> 2;\n\t\tbreak;\n\tcase HW_PORT4:\n\t\t/*REG_CR_EXT- BIT[5:4]-Network Type for port 4*/\n\t\t*net_type = (rtw_read8(adapter, MSR1) & 0x30) >> 4;\n\t\tbreak;\n#endif /*#if defined(CONFIG_RTL8814A)*/\n\tdefault:\n\t\tRTW_INFO(\"[WARN] \"ADPT_FMT\"- invalid hw port -%d\\n\",\n\t\t\t ADPT_ARG(adapter), adapter->hw_port);\n\t\trtw_warn_on(1);\n\t\tbreak;\n\t}\n#endif /* !RTW_HALMAC */\n}\n\n#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM) /*For 2 hw ports - 88E/92E/8812/8821/8723B*/\nstatic u8 rtw_hal_net_type_decision(_adapter *adapter, u8 net_type)\n{\n\tif ((adapter->hw_port == HW_PORT0) && (rtw_get_mbid_cam_entry_num(adapter))) {\n\t\tif (net_type != _HW_STATE_NOLINK_)\n\t\t\treturn _HW_STATE_AP_;\n\t}\n\treturn net_type;\n}\n#endif\nstatic void rtw_hal_set_msr(_adapter *adapter, u8 net_type)\n{\n#ifdef RTW_HALMAC\n\t#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM)\n\tnet_type = rtw_hal_net_type_decision(adapter, net_type);\n\t#endif\n\trtw_halmac_set_network_type(adapter_to_dvobj(adapter),\n\t\t\t\tadapter->hw_port, net_type);\n#else /* !RTW_HALMAC */\n\tu8 val8 = 0;\n\n\tswitch (adapter->hw_port) {\n\tcase HW_PORT0:\n\t\t#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM)\n\t\tnet_type = rtw_hal_net_type_decision(adapter, net_type);\n\t\t#endif\n\t\t/*REG_CR - BIT[17:16]-Network Type for port 0*/\n\t\tval8 = rtw_read8(adapter, MSR) & 0x0C;\n\t\tval8 |= net_type;\n\t\trtw_write8(adapter, MSR, val8);\n\t\tbreak;\n\tcase HW_PORT1:\n\t\t/*REG_CR - BIT[19:18]-Network Type for port 1*/\n\t\tval8 = rtw_read8(adapter, MSR) & 0x03;\n\t\tval8 |= net_type << 2;\n\t\trtw_write8(adapter, MSR, val8);\n\t\tbreak;\n#if defined(CONFIG_RTL8814A)\n\tcase HW_PORT2:\n\t\t/*REG_CR_EXT- BIT[1:0]-Network Type for port 2*/\n\t\tval8 = rtw_read8(adapter, MSR1) & 0xFC;\n\t\tval8 |= net_type;\n\t\trtw_write8(adapter, MSR1, val8);\n\t\tbreak;\n\tcase HW_PORT3:\n\t\t/*REG_CR_EXT- BIT[3:2]-Network Type for port 3*/\n\t\tval8 = rtw_read8(adapter, MSR1) & 0xF3;\n\t\tval8 |= net_type << 2;\n\t\trtw_write8(adapter, MSR1, val8);\n\t\tbreak;\n\tcase HW_PORT4:\n\t\t/*REG_CR_EXT- BIT[5:4]-Network Type for port 4*/\n\t\tval8 = rtw_read8(adapter, MSR1) & 0xCF;\n\t\tval8 |= net_type << 4;\n\t\trtw_write8(adapter, MSR1, val8);\n\t\tbreak;\n#endif /* CONFIG_RTL8814A */\n\tdefault:\n\t\tRTW_INFO(\"[WARN] \"ADPT_FMT\"- invalid hw port -%d\\n\",\n\t\t\t ADPT_ARG(adapter), adapter->hw_port);\n\t\trtw_warn_on(1);\n\t\tbreak;\n\t}\n#endif /* !RTW_HALMAC */\n}\n\n#ifndef SEC_CAM_ACCESS_TIMEOUT_MS\n\t#define SEC_CAM_ACCESS_TIMEOUT_MS 200\n#endif\n\n#ifndef DBG_SEC_CAM_ACCESS\n\t#define DBG_SEC_CAM_ACCESS 0\n#endif\n\nu32 rtw_sec_read_cam(_adapter *adapter, u8 addr)\n{\n\t_mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex;\n\tu32 rdata;\n\tu32 cnt = 0;\n\tsystime start = 0, end = 0;\n\tu8 timeout = 0;\n\tu8 sr = 0;\n\n\t_enter_critical_mutex(mutex, NULL);\n\n\trtw_write32(adapter, REG_CAMCMD, CAM_POLLINIG | addr);\n\n\tstart = rtw_get_current_time();\n\twhile (1) {\n\t\tif (rtw_is_surprise_removed(adapter)) {\n\t\t\tsr = 1;\n\t\t\tbreak;\n\t\t}\n\n\t\tcnt++;\n\t\tif (0 == (rtw_read32(adapter, REG_CAMCMD) & CAM_POLLINIG))\n\t\t\tbreak;\n\n\t\tif (rtw_get_passing_time_ms(start) > SEC_CAM_ACCESS_TIMEOUT_MS) {\n\t\t\ttimeout = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\tend = rtw_get_current_time();\n\n\trdata = rtw_read32(adapter, REG_CAMREAD);\n\n\t_exit_critical_mutex(mutex, NULL);\n\n\tif (DBG_SEC_CAM_ACCESS || timeout) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" addr:0x%02x, rdata:0x%08x, to:%u, polling:%u, %d ms\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), addr, rdata, timeout, cnt, rtw_get_time_interval_ms(start, end));\n\t}\n\n\treturn rdata;\n}\n\nvoid rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata)\n{\n\t_mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex;\n\tu32 cnt = 0;\n\tsystime start = 0, end = 0;\n\tu8 timeout = 0;\n\tu8 sr = 0;\n\n\t_enter_critical_mutex(mutex, NULL);\n\n\trtw_write32(adapter, REG_CAMWRITE, wdata);\n\trtw_write32(adapter, REG_CAMCMD, CAM_POLLINIG | CAM_WRITE | addr);\n\n\tstart = rtw_get_current_time();\n\twhile (1) {\n\t\tif (rtw_is_surprise_removed(adapter)) {\n\t\t\tsr = 1;\n\t\t\tbreak;\n\t\t}\n\n\t\tcnt++;\n\t\tif (0 == (rtw_read32(adapter, REG_CAMCMD) & CAM_POLLINIG))\n\t\t\tbreak;\n\n\t\tif (rtw_get_passing_time_ms(start) > SEC_CAM_ACCESS_TIMEOUT_MS) {\n\t\t\ttimeout = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\tend = rtw_get_current_time();\n\n\t_exit_critical_mutex(mutex, NULL);\n\n\tif (DBG_SEC_CAM_ACCESS || timeout) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" addr:0x%02x, wdata:0x%08x, to:%u, polling:%u, %d ms\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), addr, wdata, timeout, cnt, rtw_get_time_interval_ms(start, end));\n\t}\n}\n\nvoid rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key)\n{\n\tunsigned int val, addr;\n\tu8 i;\n\tu32 rdata;\n\tu8 begin = 0;\n\tu8 end = 5; /* TODO: consider other key length accordingly */\n\n\tif (!ctrl && !mac && !key) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\t/* TODO: check id range */\n\n\tif (!ctrl && !mac)\n\t\tbegin = 2; /* read from key */\n\n\tif (!key && !mac)\n\t\tend = 0; /* read to ctrl */\n\telse if (!key)\n\t\tend = 2; /* read to mac */\n\n\tfor (i = begin; i <= end; i++) {\n\t\trdata = rtw_sec_read_cam(adapter, (id << 3) | i);\n\n\t\tswitch (i) {\n\t\tcase 0:\n\t\t\tif (ctrl)\n\t\t\t\t_rtw_memcpy(ctrl, (u8 *)(&rdata), 2);\n\t\t\tif (mac)\n\t\t\t\t_rtw_memcpy(mac, ((u8 *)(&rdata)) + 2, 2);\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tif (mac)\n\t\t\t\t_rtw_memcpy(mac + 2, (u8 *)(&rdata), 4);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tif (key)\n\t\t\t\t_rtw_memcpy(key + (i - 2) * 4, (u8 *)(&rdata), 4);\n\t\t\tbreak;\n\t\t}\n\t}\n\nexit:\n\treturn;\n}\n\n\nvoid rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)\n{\n\tunsigned int i;\n\tint j;\n\tu8 addr, addr1 = 0;\n\tu32 wdata, wdata1 = 0;\n\n\t/* TODO: consider other key length accordingly */\n#if 0\n\tswitch ((ctrl & 0x1c) >> 2) {\n\tcase _WEP40_:\n\tcase _TKIP_:\n\tcase _AES_:\n\tcase _WEP104_:\n\n\t}\n#else\n\tj = 7;\n#endif\n\n\tfor (; j >= 0; j--) {\n\t\tswitch (j) {\n\t\tcase 0:\n\t\t\twdata = (ctrl | (mac[0] << 16) | (mac[1] << 24));\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\twdata = (mac[2] | (mac[3] << 8) | (mac[4] << 16) | (mac[5] << 24));\n\t\t\tbreak;\n\t\tcase 6:\n\t\tcase 7:\n\t\t\twdata = 0;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\ti = (j - 2) << 2;\n\t\t\twdata = (key[i] | (key[i + 1] << 8) | (key[i + 2] << 16) | (key[i + 3] << 24));\n\t\t\tbreak;\n\t\t}\n\n\t\taddr = (id << 3) + j;\n\n#if defined(CONFIG_RTL8192F)\n\t\tif(j == 1) {\n\t\t\twdata1 = wdata;\n\t\t\taddr1 = addr;\n\t\t\tcontinue;\n\t\t}\n#endif\n\n\t\trtw_sec_write_cam(adapter, addr, wdata);\n\t}\n\n#if defined(CONFIG_RTL8192F)\n\trtw_sec_write_cam(adapter, addr1, wdata1);\n#endif\n}\n\nvoid rtw_sec_clr_cam_ent(_adapter *adapter, u8 id)\n{\n\tu8 addr;\n\n\taddr = (id << 3);\n\trtw_sec_write_cam(adapter, addr, 0);\n}\n\nbool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id)\n{\n\tbool res;\n\tu16 ctrl;\n\n\trtw_sec_read_cam_ent(adapter, id, (u8 *)&ctrl, NULL, NULL);\n\n\tres = (ctrl & BIT6) ? _TRUE : _FALSE;\n\treturn res;\n}\n#ifdef CONFIG_MBSSID_CAM\nvoid rtw_mbid_cam_init(struct dvobj_priv *dvobj)\n{\n\tstruct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;\n\n\t_rtw_spinlock_init(&mbid_cam_ctl->lock);\n\tmbid_cam_ctl->bitmap = 0;\n\tATOMIC_SET(&mbid_cam_ctl->mbid_entry_num, 0);\n\t_rtw_memset(&dvobj->mbid_cam_cache, 0, sizeof(dvobj->mbid_cam_cache));\n}\n\nvoid rtw_mbid_cam_deinit(struct dvobj_priv *dvobj)\n{\n\tstruct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;\n\n\t_rtw_spinlock_free(&mbid_cam_ctl->lock);\n}\n\nvoid rtw_mbid_cam_reset(_adapter *adapter)\n{\n\t_irqL irqL;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;\n\n\t_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\tmbid_cam_ctl->bitmap = 0;\n\t_rtw_memset(&dvobj->mbid_cam_cache, 0, sizeof(dvobj->mbid_cam_cache));\n\t_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\n\tATOMIC_SET(&mbid_cam_ctl->mbid_entry_num, 0);\n}\nstatic u8 _rtw_mbid_cam_search_by_macaddr(_adapter *adapter, u8 *mac_addr)\n{\n\tu8 i;\n\tu8 cam_id = INVALID_CAM_ID;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\n\tfor (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {\n\t\tif (mac_addr && _rtw_memcmp(dvobj->mbid_cam_cache[i].mac_addr, mac_addr, ETH_ALEN) == _TRUE) {\n\t\t\tcam_id = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tRTW_INFO(\"%s mac:\"MAC_FMT\" - cam_id:%d\\n\", __func__, MAC_ARG(mac_addr), cam_id);\n\treturn cam_id;\n}\n\nu8 rtw_mbid_cam_search_by_macaddr(_adapter *adapter, u8 *mac_addr)\n{\n\t_irqL irqL;\n\n\tu8 cam_id = INVALID_CAM_ID;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;\n\n\t_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\tcam_id = _rtw_mbid_cam_search_by_macaddr(adapter, mac_addr);\n\t_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\n\treturn cam_id;\n}\nstatic u8 _rtw_mbid_cam_search_by_ifaceid(_adapter *adapter, u8 iface_id)\n{\n\tu8 i;\n\tu8 cam_id = INVALID_CAM_ID;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\n\tfor (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {\n\t\tif (iface_id == dvobj->mbid_cam_cache[i].iface_id) {\n\t\t\tcam_id = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (cam_id != INVALID_CAM_ID)\n\t\tRTW_INFO(\"%s iface_id:%d mac:\"MAC_FMT\" - cam_id:%d\\n\",\n\t\t\t__func__, iface_id, MAC_ARG(dvobj->mbid_cam_cache[cam_id].mac_addr), cam_id);\n\n\treturn cam_id;\n}\n\nu8 rtw_mbid_cam_search_by_ifaceid(_adapter *adapter, u8 iface_id)\n{\n\t_irqL irqL;\n\tu8 cam_id = INVALID_CAM_ID;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;\n\n\t_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\tcam_id = _rtw_mbid_cam_search_by_ifaceid(adapter, iface_id);\n\t_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\n\treturn cam_id;\n}\nu8 rtw_get_max_mbid_cam_id(_adapter *adapter)\n{\n\t_irqL irqL;\n\ts8 i;\n\tu8 cam_id = INVALID_CAM_ID;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;\n\n\t_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\tfor (i = (TOTAL_MBID_CAM_NUM - 1); i >= 0; i--) {\n\t\tif (mbid_cam_ctl->bitmap & BIT(i)) {\n\t\t\tcam_id = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\t_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\t/*RTW_INFO(\"%s max cam_id:%d\\n\", __func__, cam_id);*/\n\treturn cam_id;\n}\n\ninline u8 rtw_get_mbid_cam_entry_num(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;\n\n\treturn ATOMIC_READ(&mbid_cam_ctl->mbid_entry_num);\n}\n\nstatic inline void mbid_cam_cache_init(_adapter *adapter, struct mbid_cam_cache *pmbid_cam, u8 *mac_addr)\n{\n\tif (adapter && pmbid_cam && mac_addr) {\n\t\t_rtw_memcpy(pmbid_cam->mac_addr, mac_addr, ETH_ALEN);\n\t\tpmbid_cam->iface_id = adapter->iface_id;\n\t}\n}\nstatic inline void mbid_cam_cache_clr(struct mbid_cam_cache *pmbid_cam)\n{\n\tif (pmbid_cam) {\n\t\t_rtw_memset(pmbid_cam->mac_addr, 0, ETH_ALEN);\n\t\tpmbid_cam->iface_id = CONFIG_IFACE_NUMBER;\n\t}\n}\n\nu8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr)\n{\n\t_irqL irqL;\n\tu8 cam_id = INVALID_CAM_ID, i;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;\n\tu8 entry_num = ATOMIC_READ(&mbid_cam_ctl->mbid_entry_num);\n\n\tif (INVALID_CAM_ID != rtw_mbid_cam_search_by_macaddr(adapter, mac_addr))\n\t\tgoto exit;\n\n\tif (entry_num >= TOTAL_MBID_CAM_NUM) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" failed !! MBSSID number :%d over TOTAL_CAM_ENTRY(8)\\n\", FUNC_ADPT_ARG(adapter), entry_num);\n\t\trtw_warn_on(1);\n\t}\n\n\t_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\tfor (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {\n\t\tif (!(mbid_cam_ctl->bitmap & BIT(i))) {\n\t\t\tmbid_cam_ctl->bitmap |= BIT(i);\n\t\t\tcam_id = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\tif ((cam_id != INVALID_CAM_ID) && (mac_addr))\n\t\tmbid_cam_cache_init(adapter, &dvobj->mbid_cam_cache[cam_id], mac_addr);\n\t_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\n\tif (cam_id != INVALID_CAM_ID) {\n\t\tATOMIC_INC(&mbid_cam_ctl->mbid_entry_num);\n\t\tRTW_INFO(\"%s mac:\"MAC_FMT\" - cam_id:%d\\n\", __func__, MAC_ARG(mac_addr), cam_id);\n#ifdef DBG_MBID_CAM_DUMP\n\t\trtw_mbid_cam_cache_dump(RTW_DBGDUMP, __func__, adapter);\n#endif\n\t} else\n\t\tRTW_INFO(\"%s [WARN] \"MAC_FMT\" - invalid cam_id:%d\\n\", __func__, MAC_ARG(mac_addr), cam_id);\nexit:\n\treturn cam_id;\n}\n\nu8 rtw_mbid_cam_info_change(_adapter *adapter, u8 *mac_addr)\n{\n\t_irqL irqL;\n\tu8 entry_id = INVALID_CAM_ID;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;\n\n\t_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\tentry_id = _rtw_mbid_cam_search_by_ifaceid(adapter, adapter->iface_id);\n\tif (entry_id != INVALID_CAM_ID)\n\t\tmbid_cam_cache_init(adapter, &dvobj->mbid_cam_cache[entry_id], mac_addr);\n\n\t_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\n\treturn entry_id;\n}\n\nu8 rtw_mbid_cam_assign(_adapter *adapter, u8 *mac_addr, u8 camid)\n{\n\t_irqL irqL;\n\tu8 ret = _FALSE;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;\n\n\tif ((camid >= TOTAL_MBID_CAM_NUM) || (camid == INVALID_CAM_ID)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" failed !! invlaid mbid_canid :%d\\n\", FUNC_ADPT_ARG(adapter), camid);\n\t\trtw_warn_on(1);\n\t}\n\tif (INVALID_CAM_ID != rtw_mbid_cam_search_by_macaddr(adapter, mac_addr))\n\t\tgoto exit;\n\n\t_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\tif (!(mbid_cam_ctl->bitmap & BIT(camid))) {\n\t\tif (mac_addr) {\n\t\t\tmbid_cam_ctl->bitmap |= BIT(camid);\n\t\t\tmbid_cam_cache_init(adapter, &dvobj->mbid_cam_cache[camid], mac_addr);\n\t\t\tret = _TRUE;\n\t\t}\n\t}\n\t_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\n\tif (ret == _TRUE) {\n\t\tATOMIC_INC(&mbid_cam_ctl->mbid_entry_num);\n\t\tRTW_INFO(\"%s mac:\"MAC_FMT\" - cam_id:%d\\n\", __func__, MAC_ARG(mac_addr), camid);\n#ifdef DBG_MBID_CAM_DUMP\n\t\trtw_mbid_cam_cache_dump(RTW_DBGDUMP, __func__, adapter);\n#endif\n\t} else\n\t\tRTW_INFO(\"%s  [WARN] mac:\"MAC_FMT\" - cam_id:%d assigned failed\\n\", __func__, MAC_ARG(mac_addr), camid);\n\nexit:\n\treturn ret;\n}\n\nvoid rtw_mbid_camid_clean(_adapter *adapter, u8 mbss_canid)\n{\n\t_irqL irqL;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;\n\n\tif ((mbss_canid >= TOTAL_MBID_CAM_NUM) || (mbss_canid == INVALID_CAM_ID)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" failed !! invlaid mbid_canid :%d\\n\", FUNC_ADPT_ARG(adapter), mbss_canid);\n\t\trtw_warn_on(1);\n\t}\n\t_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\tmbid_cam_cache_clr(&dvobj->mbid_cam_cache[mbss_canid]);\n\tmbid_cam_ctl->bitmap &= (~BIT(mbss_canid));\n\t_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\tATOMIC_DEC(&mbid_cam_ctl->mbid_entry_num);\n\tRTW_INFO(\"%s - cam_id:%d\\n\", __func__, mbss_canid);\n}\nint rtw_mbid_cam_cache_dump(void *sel, const char *fun_name, _adapter *adapter)\n{\n\t_irqL irqL;\n\tu8 i;\n\t_adapter *iface;\n\tu8 iface_id;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;\n\tu8 entry_num = ATOMIC_READ(&mbid_cam_ctl->mbid_entry_num);\n\tu8 max_cam_id = rtw_get_max_mbid_cam_id(adapter);\n\n\tRTW_PRINT_SEL(sel, \"== MBSSID CAM DUMP (%s)==\\n\", fun_name);\n\n\t_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\tRTW_PRINT_SEL(sel, \"Entry numbers:%d, max_camid:%d, bitmap:0x%08x\\n\", entry_num, max_cam_id, mbid_cam_ctl->bitmap);\n\tfor (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {\n\t\tRTW_PRINT_SEL(sel, \"CAM_ID = %d\\t\", i);\n\n\t\tif (mbid_cam_ctl->bitmap & BIT(i)) {\n\t\t\tiface_id = dvobj->mbid_cam_cache[i].iface_id;\n\t\t\t_RTW_PRINT_SEL(sel, \"IF_ID:%d\\t\", iface_id);\n\t\t\t_RTW_PRINT_SEL(sel, \"MAC Addr:\"MAC_FMT\"\\t\", MAC_ARG(dvobj->mbid_cam_cache[i].mac_addr));\n\n\t\t\tiface = dvobj->padapters[iface_id];\n\t\t\tif (iface) {\n\t\t\t\tif (MLME_IS_STA(iface))\n\t\t\t\t\t_RTW_PRINT_SEL(sel, \"ROLE:%s\\n\", \"STA\");\n\t\t\t\telse if (MLME_IS_AP(iface))\n\t\t\t\t\t_RTW_PRINT_SEL(sel, \"ROLE:%s\\n\", \"AP\");\n\t\t\t\telse if (MLME_IS_MESH(iface))\n\t\t\t\t\t_RTW_PRINT_SEL(sel, \"ROLE:%s\\n\", \"MESH\");\n\t\t\t\telse\n\t\t\t\t\t_RTW_PRINT_SEL(sel, \"ROLE:%s\\n\", \"NONE\");\n\t\t\t}\n\n\t\t} else\n\t\t\t_RTW_PRINT_SEL(sel, \"N/A\\n\");\n\t}\n\t_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);\n\treturn 0;\n}\n\nstatic void read_mbssid_cam(_adapter *padapter, u8 cam_addr, u8 *mac)\n{\n\tu8 poll = 1;\n\tu8 cam_ready = _FALSE;\n\tu32 cam_data1 = 0;\n\tu16 cam_data2 = 0;\n\n\tif (RTW_CANNOT_RUN(padapter))\n\t\treturn;\n\n\trtw_write32(padapter, REG_MBIDCAMCFG_2, BIT_MBIDCAM_POLL | ((cam_addr & MBIDCAM_ADDR_MASK) << MBIDCAM_ADDR_SHIFT));\n\n\tdo {\n\t\tif (0 == (rtw_read32(padapter, REG_MBIDCAMCFG_2) & BIT_MBIDCAM_POLL)) {\n\t\t\tcam_ready = _TRUE;\n\t\t\tbreak;\n\t\t}\n\t\tpoll++;\n\t} while ((poll % 10) != 0 && !RTW_CANNOT_RUN(padapter));\n\n\tif (cam_ready) {\n\t\tcam_data1 = rtw_read32(padapter, REG_MBIDCAMCFG_1);\n\t\tmac[0] = cam_data1 & 0xFF;\n\t\tmac[1] = (cam_data1 >> 8) & 0xFF;\n\t\tmac[2] = (cam_data1 >> 16) & 0xFF;\n\t\tmac[3] = (cam_data1 >> 24) & 0xFF;\n\n\t\tcam_data2 = rtw_read16(padapter, REG_MBIDCAMCFG_2);\n\t\tmac[4] = cam_data2 & 0xFF;\n\t\tmac[5] = (cam_data2 >> 8) & 0xFF;\n\t}\n\n}\nint rtw_mbid_cam_dump(void *sel, const char *fun_name, _adapter *adapter)\n{\n\t/*_irqL irqL;*/\n\tu8 i;\n\tu8 mac_addr[ETH_ALEN];\n\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;\n\n\tRTW_PRINT_SEL(sel, \"\\n== MBSSID HW-CAM DUMP (%s)==\\n\", fun_name);\n\n\t/*_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);*/\n\tfor (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {\n\t\tRTW_PRINT_SEL(sel, \"CAM_ID = %d\\t\", i);\n\t\t_rtw_memset(mac_addr, 0, ETH_ALEN);\n\t\tread_mbssid_cam(adapter, i, mac_addr);\n\t\t_RTW_PRINT_SEL(sel, \"MAC Addr:\"MAC_FMT\"\\n\", MAC_ARG(mac_addr));\n\t}\n\t/*_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);*/\n\treturn 0;\n}\n\nstatic void write_mbssid_cam(_adapter *padapter, u8 cam_addr, u8 *mac)\n{\n\tu32\tcam_val[2] = {0};\n\n\tcam_val[0] = (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0];\n\tcam_val[1] = ((cam_addr & MBIDCAM_ADDR_MASK) << MBIDCAM_ADDR_SHIFT)  | (mac[5] << 8) | mac[4];\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_MBSSID_CAM_WRITE, (u8 *)cam_val);\n}\n\n/*\nstatic void clear_mbssid_cam(_adapter *padapter, u8 cam_addr)\n{\n\trtw_hal_set_hwreg(padapter, HW_VAR_MBSSID_CAM_CLEAR, &cam_addr);\n}\n*/\n\nvoid rtw_ap_set_mbid_num(_adapter *adapter, u8 ap_num)\n{\n\trtw_write8(adapter, REG_MBID_NUM,\n\t\t((rtw_read8(adapter, REG_MBID_NUM) & 0xF8) | ((ap_num -1) & 0x07)));\n\n}\nvoid rtw_mbid_cam_enable(_adapter *adapter)\n{\n\t/*enable MBSSID*/\n\trtw_hal_rcr_add(adapter, RCR_ENMBID);\n}\nvoid rtw_mi_set_mbid_cam(_adapter *adapter)\n{\n\tu8 i;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;\n\n#ifdef DBG_MBID_CAM_DUMP\n\trtw_mbid_cam_cache_dump(RTW_DBGDUMP, __func__, adapter);\n#endif\n\n\tfor (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {\n\t\tif (mbid_cam_ctl->bitmap & BIT(i)) {\n\t\t\twrite_mbssid_cam(adapter, i, dvobj->mbid_cam_cache[i].mac_addr);\n\t\t\tRTW_INFO(\"%s - cam_id:%d => mac:\"MAC_FMT\"\\n\", __func__, i, MAC_ARG(dvobj->mbid_cam_cache[i].mac_addr));\n\t\t}\n\t}\n\trtw_mbid_cam_enable(adapter);\n}\n#endif /*CONFIG_MBSSID_CAM*/\n\n#ifdef CONFIG_FW_HANDLE_TXBCN\n#define H2C_BCN_OFFLOAD_LEN\t1\n\n#define SET_H2CCMD_BCN_OFFLOAD_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_H2CCMD_BCN_ROOT_TBTT_RPT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_H2CCMD_BCN_VAP1_TBTT_RPT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)\n#define SET_H2CCMD_BCN_VAP2_TBTT_RPT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)\n#define SET_H2CCMD_BCN_VAP3_TBTT_RPT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)\n#define SET_H2CCMD_BCN_VAP4_TBTT_RPT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)\n\nvoid rtw_hal_set_fw_ap_bcn_offload_cmd(_adapter *adapter, bool fw_bcn_en, u8 tbtt_rpt_map)\n{\n\tu8 fw_bcn_offload[1] = {0};\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\n\tif (fw_bcn_en)\n\t\tSET_H2CCMD_BCN_OFFLOAD_EN(fw_bcn_offload, 1);\n\n\tif (tbtt_rpt_map & BIT(0))\n\t\tSET_H2CCMD_BCN_ROOT_TBTT_RPT(fw_bcn_offload, 1);\n\tif (tbtt_rpt_map & BIT(1))\n\t\tSET_H2CCMD_BCN_VAP1_TBTT_RPT(fw_bcn_offload, 1);\n\tif (tbtt_rpt_map & BIT(2))\n\t\tSET_H2CCMD_BCN_VAP2_TBTT_RPT(fw_bcn_offload, 1);\n\tif (tbtt_rpt_map & BIT(3))\n\t\t\tSET_H2CCMD_BCN_VAP3_TBTT_RPT(fw_bcn_offload, 1);\n\n\tdvobj->vap_tbtt_rpt_map = tbtt_rpt_map;\n\tdvobj->fw_bcn_offload = fw_bcn_en;\n\tRTW_INFO(\"[FW BCN] Offload : %s\\n\", (dvobj->fw_bcn_offload) ? \"EN\" : \"DIS\");\n\tRTW_INFO(\"[FW BCN] TBTT RPT map : 0x%02x\\n\", dvobj->vap_tbtt_rpt_map);\n\n\trtw_hal_fill_h2c_cmd(adapter, H2C_FW_BCN_OFFLOAD,\n\t\t\t\t\tH2C_BCN_OFFLOAD_LEN, fw_bcn_offload);\n}\n\nvoid rtw_hal_set_bcn_rsvdpage_loc_cmd(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tu8 ret, vap_id;\n\tu32 page_size = 0;\n\tu8 bcn_rsvdpage[H2C_BCN_RSVDPAGE_LEN] = {0};\n\n\trtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&page_size);\n\t#if 1\n\tfor (vap_id = 0; vap_id < CONFIG_LIMITED_AP_NUM; vap_id++) {\n\t\tif (dvobj->vap_map & BIT(vap_id))\n\t\t\tbcn_rsvdpage[vap_id] = vap_id * (MAX_BEACON_LEN / page_size);\n\t}\n\t#else\n#define SET_H2CCMD_BCN_RSVDPAGE_LOC_ROOT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP1(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 8, __Value)\n#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP2(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 8, __Value)\n#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP3(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 8, __Value)\n#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP4(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 8, __Value)\n\n\tif (dvobj->vap_map & BIT(0))\n \t\tSET_H2CCMD_BCN_RSVDPAGE_LOC_ROOT(bcn_rsvdpage, 0);\n\tif (dvobj->vap_map & BIT(1))\n\t\tSET_H2CCMD_BCN_RSVDPAGE_LOC_VAP1(bcn_rsvdpage,\n\t\t\t\t\t1 * (MAX_BEACON_LEN / page_size));\n\tif (dvobj->vap_map & BIT(2))\n\t\tSET_H2CCMD_BCN_RSVDPAGE_LOC_VAP2(bcn_rsvdpage,\n\t\t\t\t\t2 * (MAX_BEACON_LEN / page_size));\n\tif (dvobj->vap_map & BIT(3))\n\t\tSET_H2CCMD_BCN_RSVDPAGE_LOC_VAP3(bcn_rsvdpage,\n\t\t\t\t\t3 * (MAX_BEACON_LEN / page_size));\n\tif (dvobj->vap_map & BIT(4))\n\t\tSET_H2CCMD_BCN_RSVDPAGE_LOC_VAP4(bcn_rsvdpage,\n\t\t\t\t\t4 * (MAX_BEACON_LEN / page_size));\n\t#endif\n\tif (1) {\n\t\tRTW_INFO(\"[BCN_LOC] vap_map : 0x%02x\\n\", dvobj->vap_map);\n\t\tRTW_INFO(\"[BCN_LOC] page_size :%d, @bcn_page_num :%d\\n\"\n\t\t\t, page_size, (MAX_BEACON_LEN / page_size));\n\t\tRTW_INFO(\"[BCN_LOC] root ap : 0x%02x\\n\", *bcn_rsvdpage);\n\t\tRTW_INFO(\"[BCN_LOC] vap_1 : 0x%02x\\n\", *(bcn_rsvdpage + 1));\n\t\tRTW_INFO(\"[BCN_LOC] vap_2 : 0x%02x\\n\", *(bcn_rsvdpage + 2));\n\t\tRTW_INFO(\"[BCN_LOC] vap_3 : 0x%02x\\n\", *(bcn_rsvdpage + 3));\n\t\tRTW_INFO(\"[BCN_LOC] vap_4 : 0x%02x\\n\", *(bcn_rsvdpage + 4));\n\t}\n\tret = rtw_hal_fill_h2c_cmd(adapter, H2C_BCN_RSVDPAGE,\n\t\t\t\t\tH2C_BCN_RSVDPAGE_LEN, bcn_rsvdpage);\n}\n\nvoid rtw_ap_multi_bcn_cfg(_adapter *adapter)\n{\n\tu8 dft_bcn_space = DEFAULT_BCN_INTERVAL;\n\tu8 sub_bcn_space = (DEFAULT_BCN_INTERVAL / CONFIG_LIMITED_AP_NUM);\n\n\t/*enable to rx data frame*/\n\trtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);\n\n\t/*Disable Port0's beacon function*/\n\trtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL) & ~BIT_EN_BCN_FUNCTION);\n\t/*Reset Port0's TSF*/\n\trtw_write8(adapter, REG_DUAL_TSF_RST, BIT_TSFTR_RST);\n\n\trtw_ap_set_mbid_num(adapter, CONFIG_LIMITED_AP_NUM);\n\n\t/*BCN space & BCN sub-space 0x554[15:0] = 0x64,0x5BC[23:16] = 0x21*/\n\trtw_halmac_set_bcn_interval(adapter_to_dvobj(adapter), HW_PORT0, dft_bcn_space);\n\trtw_write8(adapter, REG_MBSSID_BCN_SPACE3 + 2, sub_bcn_space);\n\n\t#if 0 /*setting in hw_var_set_opmode_mbid - ResumeTxBeacon*/\n\t/*BCN hold time  0x540[19:8] = 0x80*/\n\trtw_write8(adapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME & 0xFF);\n\trtw_write8(adapter, REG_TBTT_PROHIBIT + 2,\n\t\t(rtw_read8(adapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME >> 8));\n\t#endif\n\n\t/*ATIM window -0x55A = 0x32, reg 0x570 = 0x32, reg 0x5A0 = 0x32 */\n\trtw_write8(adapter, REG_ATIMWND, 0x32);\n\trtw_write8(adapter, REG_ATIMWND1_V1, 0x32);\n\trtw_write8(adapter, REG_ATIMWND2, 0x32);\n\trtw_write8(adapter, REG_ATIMWND3, 0x32);\n\t/*\n\trtw_write8(adapter, REG_ATIMWND4, 0x32);\n\trtw_write8(adapter, REG_ATIMWND5, 0x32);\n\trtw_write8(adapter, REG_ATIMWND6, 0x32);\n\trtw_write8(adapter, REG_ATIMWND7, 0x32);*/\n\n\t/*no limit setting - 0x5A7 = 0xFF - Packet in Hi Queue Tx immediately*/\n\trtw_write8(adapter, REG_HIQ_NO_LMT_EN, 0xFF);\n\n\t/*Mask all beacon*/\n\trtw_write8(adapter, REG_MBSSID_CTRL, 0);\n\n\t/*BCN invalid bit setting 0x454[6] = 1*/\n\t/*rtw_write8(adapter, REG_CCK_CHECK, rtw_read8(adapter, REG_CCK_CHECK) | BIT_EN_BCN_PKT_REL);*/\n\n\t/*Enable Port0's beacon function*/\n\trtw_write8(adapter, REG_BCN_CTRL,\n\trtw_read8(adapter, REG_BCN_CTRL) | BIT_DIS_RX_BSSID_FIT | BIT_P0_EN_TXBCN_RPT | BIT_DIS_TSF_UDT  | BIT_EN_BCN_FUNCTION);\n\n\t/* Enable HW seq for BCN\n\t* 0x4FC[0]: EN_HWSEQ / 0x4FC[1]: EN_HWSEQEXT  */\n\t #ifdef CONFIG_RTL8822B\n\tif (IS_HARDWARE_TYPE_8822B(adapter))\n\t\trtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822B, 0x01);\n\t#endif\n\n\t #ifdef CONFIG_RTL8822C\n\tif (IS_HARDWARE_TYPE_8822C(adapter))\n\t\trtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822C, 0x01);\n\t#endif\n}\nstatic void _rtw_mbid_bcn_cfg(_adapter *adapter, bool mbcnq_en, u8 mbcnq_id)\n{\n\tif (mbcnq_id >= CONFIG_LIMITED_AP_NUM) {\n\t\tRTW_ERR(FUNC_ADPT_FMT\"- mbid bcnq_id(%d) invalid\\n\", FUNC_ADPT_ARG(adapter), mbcnq_id);\n\t\trtw_warn_on(1);\n\t}\n\n\tif (mbcnq_en) {\n\t\trtw_write8(adapter, REG_MBSSID_CTRL,\n\t\t\trtw_read8(adapter, REG_MBSSID_CTRL) | BIT(mbcnq_id));\n\t\tRTW_INFO(FUNC_ADPT_FMT\"- mbid bcnq_id(%d) enabled\\n\", FUNC_ADPT_ARG(adapter), mbcnq_id);\n\t} else {\n\t\trtw_write8(adapter, REG_MBSSID_CTRL,\n\t\t\trtw_read8(adapter, REG_MBSSID_CTRL) & (~BIT(mbcnq_id)));\n\t\tRTW_INFO(FUNC_ADPT_FMT\"- mbid bcnq_id(%d) disabled\\n\", FUNC_ADPT_ARG(adapter), mbcnq_id);\n\t}\n}\n/*#define CONFIG_FW_TBTT_RPT*/\nvoid rtw_ap_mbid_bcn_en(_adapter *adapter, u8 ap_id)\n{\n\tRTW_INFO(FUNC_ADPT_FMT\"- ap_id(%d)\\n\", FUNC_ADPT_ARG(adapter), ap_id);\n\n\t#ifdef CONFIG_FW_TBTT_RPT\n\tif (rtw_ap_get_nums(adapter) >= 1) {\n\t\tu8 tbtt_rpt_map = adapter_to_dvobj(adapter)->vap_tbtt_rpt_map;\n\n\t\trtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _TRUE,\n\t\t\ttbtt_rpt_map | BIT(ap_id));/*H2C-0xBA*/\n\t}\n\t#else\n\tif (rtw_ap_get_nums(adapter) == 1)\n\t\trtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _TRUE, 0);/*H2C-0xBA*/\n\t#endif\n\n\trtw_hal_set_bcn_rsvdpage_loc_cmd(adapter);/*H2C-0x09*/\n\n\t_rtw_mbid_bcn_cfg(adapter, _TRUE, ap_id);\n}\nvoid rtw_ap_mbid_bcn_dis(_adapter *adapter, u8 ap_id)\n{\n\tRTW_INFO(FUNC_ADPT_FMT\"- ap_id(%d)\\n\", FUNC_ADPT_ARG(adapter), ap_id);\n\t_rtw_mbid_bcn_cfg(adapter, _FALSE, ap_id);\n\n\tif (rtw_ap_get_nums(adapter) == 0)\n\t\trtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _FALSE, 0);\n\t#ifdef CONFIG_FW_TBTT_RPT\n\telse if (rtw_ap_get_nums(adapter) >= 1) {\n\t\tu8 tbtt_rpt_map = adapter_to_dvobj(adapter)->vap_tbtt_rpt_map;\n\n\t\trtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _TRUE,\n\t\t\ttbtt_rpt_map & ~BIT(ap_id));/*H2C-0xBA*/\n\t}\n\t#endif\n}\n#endif\n#ifdef CONFIG_SWTIMER_BASED_TXBCN\nvoid rtw_ap_multi_bcn_cfg(_adapter *adapter)\n{\n\t#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)\n\trtw_write8(adapter, REG_BCN_CTRL, DIS_TSF_UDT);\n\t#else\n\trtw_write8(adapter, REG_BCN_CTRL, DIS_TSF_UDT | DIS_BCNQ_SUB);\n\t#endif\n\t/*enable to rx data frame*/\n\trtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);\n\n\t/*Beacon Control related register for first time*/\n\trtw_write8(adapter, REG_BCNDMATIM, 0x02); /* 2ms */\n\n\t/*rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);*/\n\trtw_write8(adapter, REG_ATIMWND, 0x0c); /* 12ms */\n\n\t#ifndef CONFIG_HW_P0_TSF_SYNC\n\trtw_write16(adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */\n\t#endif\n\n\t/*reset TSF*/\n\trtw_write8(adapter, REG_DUAL_TSF_RST, BIT(0));\n\n\t/*enable BCN0 Function for if1*/\n\t/*don't enable update TSF0 for if1 (due to TSF update when beacon,probe rsp are received)*/\n\t#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)\n\trtw_write8(adapter, REG_BCN_CTRL, BIT_DIS_RX_BSSID_FIT | BIT_P0_EN_TXBCN_RPT | BIT_DIS_TSF_UDT |BIT_EN_BCN_FUNCTION);\n\t#else\n\trtw_write8(adapter, REG_BCN_CTRL, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB));\n\t#endif\n\t#ifdef CONFIG_BCN_XMIT_PROTECT\n\trtw_write8(adapter, REG_CCK_CHECK, rtw_read8(adapter, REG_CCK_CHECK) | BIT_EN_BCN_PKT_REL);\n\t#endif\n\n\tif (IS_HARDWARE_TYPE_8821(adapter) || IS_HARDWARE_TYPE_8192E(adapter))/* select BCN on port 0 for DualBeacon*/\n\t\trtw_write8(adapter, REG_CCK_CHECK, rtw_read8(adapter, REG_CCK_CHECK) & (~BIT_BCN_PORT_SEL));\n\n\t/* Enable HW seq for BCN \n\t * 0x4FC[0]: EN_HWSEQ / 0x4FC[1]: EN_HWSEQEXT  */\n\t#ifdef CONFIG_RTL8822B\n\tif (IS_HARDWARE_TYPE_8822B(adapter))\n\t\trtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822B, 0x01);\n\t#endif\n\n\t#ifdef CONFIG_RTL8822C\n\tif (IS_HARDWARE_TYPE_8822C(adapter))\n\t\trtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822C, 0x01);\n\t#endif\n}\n#endif\n\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\nvoid rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr)\n{\n\n#if 0 /*TODO - modify for more flexible*/\n\tu8 idx = 0;\n\n\tif ((check_fwstate(&adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) &&\n\t    (DEV_STA_NUM(adapter_to_dvobj(adapter)) == 1)) {\n\t\tfor (idx = 0; idx < 6; idx++)\n\t\t\trtw_write8(GET_PRIMARY_ADAPTER(adapter), (REG_MACID + idx), val[idx]);\n\t}  else {\n\t\t/*MBID entry_id = 0~7 ,0 for root AP, 1~7 for VAP*/\n\t\tu8 entry_id;\n\n\t\tif ((check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) &&\n\t\t    (DEV_AP_NUM(adapter_to_dvobj(adapter)) == 1)) {\n\t\t\tentry_id = 0;\n\t\t\tif (rtw_mbid_cam_assign(adapter, val, entry_id)) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" Root AP assigned success\\n\", FUNC_ADPT_ARG(adapter));\n\t\t\t\twrite_mbssid_cam(adapter, entry_id, val);\n\t\t\t}\n\t\t} else {\n\t\t\tentry_id = rtw_mbid_camid_alloc(adapter, val);\n\t\t\tif (entry_id != INVALID_CAM_ID)\n\t\t\t\twrite_mbssid_cam(adapter, entry_id, val);\n\t\t}\n\t}\n#else\n\t{\n\t\t/*\n\t\t\tMBID entry_id = 0~7 ,for IFACE_ID0 ~ IFACE_IDx\n\t\t*/\n\t\tu8 entry_id = rtw_mbid_camid_alloc(adapter, mac_addr);\n\n\n\t\tif (entry_id != INVALID_CAM_ID) {\n\t\t\twrite_mbssid_cam(adapter, entry_id, mac_addr);\n\t\t\tRTW_INFO(\"%s \"ADPT_FMT\"- mbid(%d) mac_addr =\"MAC_FMT\"\\n\", __func__,\n\t\t\t\tADPT_ARG(adapter), entry_id, MAC_ARG(mac_addr));\n\t\t}\n\t}\n#endif\n}\n\nvoid rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr)\n{\n\tu8 idx = 0;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tu8 entry_id;\n\n\tif (!mac_addr) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\n\tentry_id = rtw_mbid_cam_info_change(adapter, mac_addr);\n\n\tif (entry_id != INVALID_CAM_ID)\n\t\twrite_mbssid_cam(adapter, entry_id, mac_addr);\n}\n\n#ifdef CONFIG_SWTIMER_BASED_TXBCN\nu16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval)\n{\n\tif (adapter_to_dvobj(adapter)->inter_bcn_space != bcn_interval)\n\t\treturn adapter_to_dvobj(adapter)->inter_bcn_space;\n\telse\n\t\treturn bcn_interval;\n}\n#endif/*CONFIG_SWTIMER_BASED_TXBCN*/\n\n#else\nstatic void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val)\n{\n\tu8 idx = 0;\n\tu32 reg_macid = 0;\n\tenum _hw_port hwport;\n\n\tif (val == NULL)\n\t\treturn;\n\thwport = get_hw_port(adapter);\n\n\tRTW_INFO(\"%s \"ADPT_FMT\"- hw port(%d) mac_addr =\"MAC_FMT\"\\n\",  __func__,\n\t\t ADPT_ARG(adapter), hwport, MAC_ARG(val));\n\n#ifdef RTW_HALMAC\n\trtw_halmac_set_mac_address(adapter_to_dvobj(adapter), hwport, val);\n#else /* !RTW_HALMAC */\n\tswitch (hwport) {\n\tcase HW_PORT0:\n\tdefault:\n\t\treg_macid = REG_MACID;\n\t\tbreak;\n\tcase HW_PORT1:\n\t\treg_macid = REG_MACID1;\n\t\tbreak;\n#if defined(CONFIG_RTL8814A)\n\tcase HW_PORT2:\n\t\treg_macid = REG_MACID2;\n\t\tbreak;\n\tcase HW_PORT3:\n\t\treg_macid = REG_MACID3;\n\t\tbreak;\n\tcase HW_PORT4:\n\t\treg_macid = REG_MACID4;\n\t\tbreak;\n#endif/*defined(CONFIG_RTL8814A)*/\n\t}\n\n\tfor (idx = 0; idx < ETH_ALEN; idx++)\n\t\trtw_write8(GET_PRIMARY_ADAPTER(adapter), (reg_macid + idx), val[idx]);\n#endif /* !RTW_HALMAC */\n}\n#endif/*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/\n\nstatic void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr)\n{\n\tu8 idx = 0;\n\tu32 reg_macid = 0;\n\n\tif (mac_addr == NULL)\n\t\treturn;\n\n\t_rtw_memset(mac_addr, 0, ETH_ALEN);\n#ifdef RTW_HALMAC\n\trtw_halmac_get_mac_address(adapter_to_dvobj(adapter), adapter->hw_port, mac_addr);\n#else /* !RTW_HALMAC */\n\tswitch (adapter->hw_port) {\n\tcase HW_PORT0:\n\tdefault:\n\t\treg_macid = REG_MACID;\n\t\tbreak;\n\tcase HW_PORT1:\n\t\treg_macid = REG_MACID1;\n\t\tbreak;\n#if defined(CONFIG_RTL8814A)\n\tcase HW_PORT2:\n\t\treg_macid = REG_MACID2;\n\t\tbreak;\n\tcase HW_PORT3:\n\t\treg_macid = REG_MACID3;\n\t\tbreak;\n\tcase HW_PORT4:\n\t\treg_macid = REG_MACID4;\n\t\tbreak;\n#endif /*defined(CONFIG_RTL8814A)*/\n\t}\n\n\tfor (idx = 0; idx < ETH_ALEN; idx++)\n\t\tmac_addr[idx] = rtw_read8(GET_PRIMARY_ADAPTER(adapter), (reg_macid + idx));\n#endif /* !RTW_HALMAC */\n\n\tRTW_INFO(\"%s \"ADPT_FMT\"- hw port(%d) mac_addr =\"MAC_FMT\"\\n\",  __func__,\n\t\t ADPT_ARG(adapter), adapter->hw_port, MAC_ARG(mac_addr));\n}\n\nstatic void rtw_hal_set_bssid(_adapter *adapter, u8 *val)\n{\n\tu8 hw_port = rtw_hal_get_port(adapter);\n\n#ifdef RTW_HALMAC\n\trtw_halmac_set_bssid(adapter_to_dvobj(adapter), hw_port, val);\n#else /* !RTW_HALMAC */\n\tu8\tidx = 0;\n\tu32 reg_bssid = 0;\n\n\tswitch (hw_port) {\n\tcase HW_PORT0:\n\tdefault:\n\t\treg_bssid = REG_BSSID;\n\t\tbreak;\n\tcase HW_PORT1:\n\t\treg_bssid = REG_BSSID1;\n\t\tbreak;\n#if defined(CONFIG_RTL8814A)\n\tcase HW_PORT2:\n\t\treg_bssid = REG_BSSID2;\n\t\tbreak;\n\tcase HW_PORT3:\n\t\treg_bssid = REG_BSSID3;\n\t\tbreak;\n\tcase HW_PORT4:\n\t\treg_bssid = REG_BSSID4;\n\t\tbreak;\n#endif/*defined(CONFIG_RTL8814A)*/\n\t}\n\n\tfor (idx = 0 ; idx < ETH_ALEN; idx++)\n\t\trtw_write8(adapter, (reg_bssid + idx), val[idx]);\n#endif /* !RTW_HALMAC */\n\n\tRTW_INFO(\"%s \"ADPT_FMT\"- hw port -%d BSSID: \"MAC_FMT\"\\n\",\n\t\t__func__, ADPT_ARG(adapter), hw_port, MAC_ARG(val));\n}\n\nstatic void rtw_hal_set_tsf_update(_adapter *adapter, u8 en)\n{\n\tu32 addr = 0;\n\tu8 val8;\n\n\trtw_hal_get_hwreg(adapter, HW_VAR_BCN_CTRL_ADDR, (u8 *)&addr);\n\tif (addr) {\n\t\tval8 = rtw_read8(adapter, addr);\n\t\tif (en && (val8 & DIS_TSF_UDT)) {\n\t\t\trtw_write8(adapter, addr, val8 & ~DIS_TSF_UDT);\n\t\t\t#ifdef DBG_TSF_UPDATE\n\t\t\tRTW_INFO(\"port%u(\"ADPT_FMT\") enable TSF update\\n\", adapter->hw_port, ADPT_ARG(adapter));\n\t\t\t#endif\n\t\t}\n\t\tif (!en && !(val8 & DIS_TSF_UDT)) {\n\t\t\trtw_write8(adapter, addr, val8 | DIS_TSF_UDT);\n\t\t\t#ifdef DBG_TSF_UPDATE\n\t\t\tRTW_INFO(\"port%u(\"ADPT_FMT\") disable TSF update\\n\", adapter->hw_port, ADPT_ARG(adapter));\n\t\t\t#endif\n\t\t}\n\t} else {\n\t\tRTW_WARN(\"unknown port%d(\"ADPT_FMT\") %s TSF update\\n\"\n\t\t\t, adapter->hw_port, ADPT_ARG(adapter), en ? \"enable\" : \"disable\");\n\t\trtw_warn_on(1);\n\t}\n}\n\nstatic void rtw_hal_set_hw_update_tsf(PADAPTER padapter)\n{\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) || defined(CONFIG_MI_WITH_MBSSID_CAM)\n\tRTW_INFO(\"[Warn] %s \"ADPT_FMT\" enter func\\n\", __func__, ADPT_ARG(padapter));\n\trtw_warn_on(1);\n\treturn;\n#endif\n\n\tif (!pmlmeext->en_hw_update_tsf)\n\t\treturn;\n\n\t/* check RCR */\n\tif (!rtw_hal_rcr_check(padapter, RCR_CBSSID_BCN))\n\t\treturn;\n\n\tif (pmlmeext->tsf_update_required) {\n\t\tpmlmeext->tsf_update_pause_stime = 0;\n\t\trtw_hal_set_tsf_update(padapter, 1);\n\t}\n\n\tpmlmeext->en_hw_update_tsf = 0;\n}\n\nvoid rtw_iface_enable_tsf_update(_adapter *adapter)\n{\n\tadapter->mlmeextpriv.tsf_update_pause_stime = 0;\n\tadapter->mlmeextpriv.tsf_update_required = 1;\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\n#else\n\trtw_hal_set_tsf_update(adapter, 1);\n#endif\n}\n\nvoid rtw_iface_disable_tsf_update(_adapter *adapter)\n{\n\tadapter->mlmeextpriv.tsf_update_required = 0;\n\tadapter->mlmeextpriv.tsf_update_pause_stime = 0;\n\tadapter->mlmeextpriv.en_hw_update_tsf = 0;\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\n#else\n\trtw_hal_set_tsf_update(adapter, 0);\n#endif\n}\n\nstatic void rtw_hal_tsf_update_pause(_adapter *adapter)\n{\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\n#else\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\t_adapter *iface;\n\tint i;\n\tu8 val8;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (!iface)\n\t\t\tcontinue;\n\n\t\trtw_hal_set_tsf_update(iface, 0);\n\t\tif (iface->mlmeextpriv.tsf_update_required) {\n\t\t\tiface->mlmeextpriv.tsf_update_pause_stime = rtw_get_current_time();\n\t\t\tif (!iface->mlmeextpriv.tsf_update_pause_stime)\n\t\t\t\tiface->mlmeextpriv.tsf_update_pause_stime++;\n\t\t}\n\t\tiface->mlmeextpriv.en_hw_update_tsf = 0;\n\t}\n#endif\n}\n\nstatic void rtw_hal_tsf_update_restore(_adapter *adapter)\n{\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\n#else\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\t_adapter *iface;\n\tint i;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (!iface)\n\t\t\tcontinue;\n\n\t\tif (iface->mlmeextpriv.tsf_update_required) {\n\t\t\t/* enable HW TSF update when recive beacon*/\n\t\t\tiface->mlmeextpriv.en_hw_update_tsf = 1;\n\t\t\t#ifdef DBG_TSF_UPDATE\n\t\t\tRTW_INFO(\"port%d(\"ADPT_FMT\") enabling TSF update...\\n\"\n\t\t\t\t, iface->hw_port, ADPT_ARG(iface));\n\t\t\t#endif\n\t\t}\n\t}\n#endif\n}\n\nvoid rtw_hal_periodic_tsf_update_chk(_adapter *adapter)\n{\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\n#else\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\t_adapter *iface;\n\tstruct mlme_ext_priv *mlmeext;\n\tint i;\n\tu32 restore_ms = 0;\n\n\tif (dvobj->periodic_tsf_update_etime) {\n\t\tif (rtw_time_after(rtw_get_current_time(), dvobj->periodic_tsf_update_etime)) {\n\t\t\t/* end for restore status */\n\t\t\tdvobj->periodic_tsf_update_etime = 0;\n\t\t\trtw_hal_rcr_set_chk_bssid(adapter, MLME_ACTION_NONE);\n\t\t}\n\t\treturn;\n\t}\n\n\tif (dvobj->rf_ctl.offch_state != OFFCHS_NONE)\n\t\treturn;\n\n\t/*\n\t* all required ifaces can switch to restore status together\n\t* loop all pause iface to get largest restore time required\n\t*/\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (!iface)\n\t\t\tcontinue;\n\n\t\tmlmeext = &iface->mlmeextpriv;\n\n\t\tif (mlmeext->tsf_update_required\n\t\t\t&& mlmeext->tsf_update_pause_stime\n\t\t\t&& rtw_get_passing_time_ms(mlmeext->tsf_update_pause_stime)\n\t\t\t\t> mlmeext->mlmext_info.bcn_interval * mlmeext->tsf_update_pause_factor\n\t\t) {\n\t\t\tif (restore_ms < mlmeext->mlmext_info.bcn_interval * mlmeext->tsf_update_restore_factor)\n\t\t\t\trestore_ms = mlmeext->mlmext_info.bcn_interval * mlmeext->tsf_update_restore_factor;\n\t\t}\n\t}\n\n\tif (!restore_ms)\n\t\treturn;\n\n\tdvobj->periodic_tsf_update_etime = rtw_get_current_time() + rtw_ms_to_systime(restore_ms);\n\tif (!dvobj->periodic_tsf_update_etime)\n\t\tdvobj->periodic_tsf_update_etime++;\n\n\trtw_hal_rcr_set_chk_bssid(adapter, MLME_ACTION_NONE);\n\n\t/* set timer to end restore status */\n\t_set_timer(&dvobj->periodic_tsf_update_end_timer, restore_ms);\n#endif\n}\n\nvoid rtw_hal_periodic_tsf_update_end_timer_hdl(void *ctx)\n{\n\tstruct dvobj_priv *dvobj = (struct dvobj_priv *)ctx;\n\n\tif (dev_is_surprise_removed(dvobj) || dev_is_drv_stopped(dvobj))\n\t\treturn;\n\n\trtw_periodic_tsf_update_end_cmd(dvobj_get_primary_adapter(dvobj));\n}\n\nstatic inline u8 hw_var_rcr_config(_adapter *adapter, u32 rcr)\n{\n\tint err;\n\n\terr = rtw_write32(adapter, REG_RCR, rcr);\n\tif (err == _SUCCESS)\n\t\tGET_HAL_DATA(adapter)->ReceiveConfig = rcr;\n\treturn err;\n}\n\nstatic inline u8 hw_var_rcr_get(_adapter *adapter, u32 *rcr)\n{\n\tu32 v32;\n\n\tv32 = rtw_read32(adapter, REG_RCR);\n\tif (rcr)\n\t\t*rcr = v32;\n\tGET_HAL_DATA(adapter)->ReceiveConfig = v32;\n\treturn _SUCCESS;\n}\n\n/* only check SW RCR variable */\ninline u8 rtw_hal_rcr_check(_adapter *adapter, u32 check_bit)\n{\n\tPHAL_DATA_TYPE hal;\n\tu32 rcr;\n\n\thal = GET_HAL_DATA(adapter);\n\n\trcr = hal->ReceiveConfig;\n\tif ((rcr & check_bit) == check_bit)\n\t\treturn 1;\n\n\treturn 0;\n}\n\ninline u8 rtw_hal_rcr_add(_adapter *adapter, u32 add)\n{\n\tPHAL_DATA_TYPE hal;\n\tu32 rcr;\n\tu8 ret = _SUCCESS;\n\n\thal = GET_HAL_DATA(adapter);\n\n\trtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);\n\trcr |= add;\n\tif (rcr != hal->ReceiveConfig)\n\t\tret = rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);\n\n\treturn ret;\n}\n\ninline u8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear)\n{\n\tPHAL_DATA_TYPE hal;\n\tu32 rcr;\n\tu8 ret = _SUCCESS;\n\n\thal = GET_HAL_DATA(adapter);\n\n\trtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);\n\trcr &= ~clear;\n\tif (rcr != hal->ReceiveConfig)\n\t\tret = rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);\n\n\treturn ret;\n}\n\nvoid rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tu32 rcr, rcr_new;\n\tstruct mi_state mstate, mstate_s;\n\n\trtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);\n\trcr_new = rcr;\n\n#if defined(CONFIG_MI_WITH_MBSSID_CAM) && !defined(CONFIG_CLIENT_PORT_CFG)\n\trcr_new &= ~(RCR_CBSSID_BCN | RCR_CBSSID_DATA);\n#else\n\trtw_mi_status_no_self(adapter, &mstate);\n\trtw_mi_status_no_others(adapter, &mstate_s);\n\n\t/* only adjust parameters interested */\n\tswitch (self_action) {\n\tcase MLME_SCAN_ENTER:\n\t\tmstate_s.scan_num = 1;\n\t\tmstate_s.scan_enter_num = 1;\n\t\tbreak;\n\tcase MLME_SCAN_DONE:\n\t\tmstate_s.scan_enter_num = 0;\n\t\tbreak;\n\tcase MLME_STA_CONNECTING:\n\t\tmstate_s.lg_sta_num = 1;\n\t\tmstate_s.ld_sta_num = 0;\n\t\tbreak;\n\tcase MLME_STA_CONNECTED:\n\t\tmstate_s.lg_sta_num = 0;\n\t\tmstate_s.ld_sta_num = 1;\n\t\tbreak;\n\tcase MLME_STA_DISCONNECTED:\n\t\tmstate_s.lg_sta_num = 0;\n\t\tmstate_s.ld_sta_num = 0;\n\t\tbreak;\n#ifdef CONFIG_TDLS\n\tcase MLME_TDLS_LINKED:\n\t\tmstate_s.ld_tdls_num = 1;\n\t\tbreak;\n\tcase MLME_TDLS_NOLINK:\n\t\tmstate_s.ld_tdls_num = 0;\n\t\tbreak;\n#endif\n#ifdef CONFIG_AP_MODE\n\tcase MLME_AP_STARTED:\n\t\tmstate_s.ap_num = 1;\n\t\tbreak;\n\tcase MLME_AP_STOPPED:\n\t\tmstate_s.ap_num = 0;\n\t\tmstate_s.ld_ap_num = 0;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTW_MESH\n\tcase MLME_MESH_STARTED:\n\t\tmstate_s.mesh_num = 1;\n\t\tbreak;\n\tcase MLME_MESH_STOPPED:\n\t\tmstate_s.mesh_num = 0;\n\t\tmstate_s.ld_mesh_num = 0;\n\t\tbreak;\n#endif\n\tcase MLME_ACTION_NONE:\n\tcase MLME_ADHOC_STARTED:\n\t\t/* caller without effect of decision */\n\t\tbreak;\n\tdefault:\n\t\trtw_warn_on(1);\n\t};\n\n\trtw_mi_status_merge(&mstate, &mstate_s);\n\n\tif (MSTATE_AP_NUM(&mstate) || MSTATE_MESH_NUM(&mstate) || MSTATE_TDLS_LD_NUM(&mstate)\n\t\t#ifdef CONFIG_FIND_BEST_CHANNEL\n\t\t|| MSTATE_SCAN_ENTER_NUM(&mstate)\n\t\t#endif\n\t\t|| hal_data->in_cta_test\n\t)\n\t\trcr_new &= ~RCR_CBSSID_DATA;\n\telse\n\t\trcr_new |= RCR_CBSSID_DATA;\n\n\tif (MSTATE_SCAN_ENTER_NUM(&mstate) || hal_data->in_cta_test)\n\t\trcr_new &= ~RCR_CBSSID_BCN;\n\telse if (MSTATE_STA_LG_NUM(&mstate)\n\t\t|| adapter_to_dvobj(adapter)->periodic_tsf_update_etime\n\t)\n\t\trcr_new |= RCR_CBSSID_BCN;\n\telse if ((MSTATE_AP_NUM(&mstate) && adapter->registrypriv.wifi_spec) /* for 11n Logo 4.2.31/4.2.32 */\n\t\t|| MSTATE_MESH_NUM(&mstate)\n\t)\n\t\trcr_new &= ~RCR_CBSSID_BCN;\t\n\telse\n\t\trcr_new |= RCR_CBSSID_BCN;\n\n\t#ifdef CONFIG_CLIENT_PORT_CFG\n\tif (get_clt_num(adapter) > MAX_CLIENT_PORT_NUM)\n\t\trcr_new &= ~RCR_CBSSID_BCN;\n\t#endif\n#endif /* CONFIG_MI_WITH_MBSSID_CAM */\n\n\tif (rcr == rcr_new)\n\t\treturn;\n\n\tif (!hal_spec->rx_tsf_filter\n\t\t&& (rcr & RCR_CBSSID_BCN) && !(rcr_new & RCR_CBSSID_BCN))\n\t\trtw_hal_tsf_update_pause(adapter);\n\n\trtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr_new);\n\n\tif (!hal_spec->rx_tsf_filter\n\t\t&& !(rcr & RCR_CBSSID_BCN) && (rcr_new & RCR_CBSSID_BCN)\n\t\t&& self_action != MLME_STA_CONNECTING)\n\t\trtw_hal_tsf_update_restore(adapter);\n}\n\nstatic void hw_var_set_rcr_am(_adapter *adapter, u8 enable)\n{\n\tu32 rcr = RCR_AM;\n\n\tif (enable)\n\t\trtw_hal_rcr_add(adapter, rcr);\n\telse\n\t\trtw_hal_rcr_clear(adapter, rcr);\n}\n\nstatic void hw_var_set_bcn_interval(_adapter *adapter, u16 interval)\n{\n#ifdef CONFIG_SWTIMER_BASED_TXBCN\n\tinterval = rtw_hal_bcn_interval_adjust(adapter, interval);\n#endif\n\n#ifdef RTW_HALMAC\n\trtw_halmac_set_bcn_interval(adapter_to_dvobj(adapter), adapter->hw_port, interval);\n#else\n\trtw_write16(adapter, REG_MBSSID_BCN_SPACE, interval);\n#endif\n\n#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT\n\t{\n\t\tstruct mlme_ext_priv\t*pmlmeext = &adapter->mlmeextpriv;\n\t\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\t\tif ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {\n\t\t\tRTW_INFO(\"%s==> bcn_interval:%d, eraly_int:%d\\n\", __func__, interval, interval >> 1);\n\t\t\trtw_write8(adapter, REG_DRVERLYINT, interval >> 1);\n\t\t}\n\t}\n#endif\n}\n\n#if CONFIG_TX_AC_LIFETIME\nconst char *const _tx_aclt_conf_str[] = {\n\t\"DEFAULT\",\n\t\"AP_M2U\",\n\t\"MESH\",\n\t\"INVALID\",\n};\n\nvoid dump_tx_aclt_force_val(void *sel, struct dvobj_priv *dvobj)\n{\n#define TX_ACLT_FORCE_MSG_LEN 64\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(dvobj_get_primary_adapter(dvobj));\n\tstruct tx_aclt_conf_t *conf = &dvobj->tx_aclt_force_val;\n\tchar buf[TX_ACLT_FORCE_MSG_LEN];\n\tint cnt = 0;\n\n\tRTW_PRINT_SEL(sel, \"unit:%uus, maximum:%uus\\n\"\n\t\t, hal_spec->tx_aclt_unit_factor * 32\n\t\t, 0xFFFF * hal_spec->tx_aclt_unit_factor * 32);\n\n\tRTW_PRINT_SEL(sel, \"%-5s %-12s %-12s\\n\", \"en\", \"vo_vi(us)\", \"be_bk(us)\");\n\tRTW_PRINT_SEL(sel, \" 0x%02x %12u %12u\\n\"\n\t\t, conf->en\n\t\t, conf->vo_vi * hal_spec->tx_aclt_unit_factor * 32\n\t\t, conf->be_bk * hal_spec->tx_aclt_unit_factor * 32\n\t);\n\n\tcnt += snprintf(buf + cnt, TX_ACLT_FORCE_MSG_LEN - cnt - 1, \"%5s\", conf->en == 0xFF ? \"AUTO\" : \"FORCE\");\n\tif (cnt >= TX_ACLT_FORCE_MSG_LEN - 1)\n\t\tgoto exit;\n\n\tif (conf->vo_vi)\n\t\tcnt += snprintf(buf + cnt, TX_ACLT_FORCE_MSG_LEN - cnt - 1, \" FORCE:0x%04x\", conf->vo_vi);\n\telse\n\t\tcnt += snprintf(buf + cnt, TX_ACLT_FORCE_MSG_LEN - cnt - 1, \"         AUTO\");\n\tif (cnt >= TX_ACLT_FORCE_MSG_LEN - 1)\n\t\tgoto exit;\n\n\n\tif (conf->be_bk)\n\t\tcnt += snprintf(buf + cnt, TX_ACLT_FORCE_MSG_LEN - cnt - 1, \" FORCE:0x%04x\", conf->be_bk);\n\telse\n\t\tcnt += snprintf(buf + cnt, TX_ACLT_FORCE_MSG_LEN - cnt - 1, \"         AUTO\");\n\tif (cnt >= TX_ACLT_FORCE_MSG_LEN - 1)\n\t\tgoto exit;\n\n\tRTW_PRINT_SEL(sel, \"%s\\n\", buf);\n\nexit:\n\treturn;\n}\n\nvoid rtw_hal_set_tx_aclt_force_val(_adapter *adapter, struct tx_aclt_conf_t *input, u8 arg_num)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct tx_aclt_conf_t *conf = &dvobj->tx_aclt_force_val;\n\n\tif (arg_num >= 1) {\n\t\tif (input->en == 0xFF)\n\t\t\tconf->en = input->en;\n\t\telse\n\t\t\tconf->en = input->en & 0xF;\n\t}\n\tif (arg_num >= 2) {\n\t\tconf->vo_vi = input->vo_vi / (hal_spec->tx_aclt_unit_factor * 32);\n\t\tif (conf->vo_vi > 0xFFFF)\n\t\t\tconf->vo_vi = 0xFFFF;\n\t}\n\tif (arg_num >= 3) {\n\t\tconf->be_bk = input->be_bk / (hal_spec->tx_aclt_unit_factor * 32);\n\t\tif (conf->be_bk > 0xFFFF)\n\t\t\tconf->be_bk = 0xFFFF;\n\t}\n}\n\nvoid dump_tx_aclt_confs(void *sel, struct dvobj_priv *dvobj)\n{\n#define TX_ACLT_CONF_MSG_LEN 32\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(dvobj_get_primary_adapter(dvobj));\n\tstruct tx_aclt_conf_t *conf;\n\tchar buf[TX_ACLT_CONF_MSG_LEN];\n\tint cnt;\n\tint i;\n\n\tRTW_PRINT_SEL(sel, \"unit:%uus, maximum:%uus\\n\"\n\t\t, hal_spec->tx_aclt_unit_factor * 32\n\t\t, 0xFFFF * hal_spec->tx_aclt_unit_factor * 32);\n\n\tRTW_PRINT_SEL(sel, \"%-7s %-1s %-3s %-9s %-9s %-10s %-10s\\n\"\n\t\t, \"name\", \"#\", \"en\", \"vo_vi(us)\", \"be_bk(us)\", \"vo_vi(reg)\", \"be_bk(reg)\");\n\n\tfor (i = 0; i < TX_ACLT_CONF_NUM; i++) {\n\t\tconf = &dvobj->tx_aclt_confs[i];\n\t\tcnt = 0;\n\n\t\tif (conf->vo_vi)\n\t\t\tcnt += snprintf(buf + cnt, TX_ACLT_CONF_MSG_LEN - cnt - 1, \"     0x%04x\", conf->vo_vi);\n\t\telse\n\t\t\tcnt += snprintf(buf + cnt, TX_ACLT_CONF_MSG_LEN - cnt - 1, \"        N/A\");\n\t\tif (cnt >= TX_ACLT_CONF_MSG_LEN - 1)\n\t\t\tcontinue;\n\t\t\n\t\tif (conf->be_bk)\n\t\t\tcnt += snprintf(buf + cnt, TX_ACLT_CONF_MSG_LEN - cnt - 1, \"     0x%04x\", conf->be_bk);\n\t\telse\n\t\t\tcnt += snprintf(buf + cnt, TX_ACLT_CONF_MSG_LEN - cnt - 1, \"        N/A\");\n\t\tif (cnt >= TX_ACLT_CONF_MSG_LEN - 1)\n\t\t\tcontinue;\n\n\t\tRTW_PRINT_SEL(sel, \"%7s %1u 0x%x %9u %9u%s\\n\"\n\t\t\t, tx_aclt_conf_str(i), i\n\t\t\t, conf->en\n\t\t\t, conf->vo_vi * hal_spec->tx_aclt_unit_factor * 32\n\t\t\t, conf->be_bk * hal_spec->tx_aclt_unit_factor * 32\n\t\t\t, buf\n\t\t);\n\t}\n}\n\nvoid rtw_hal_set_tx_aclt_conf(_adapter *adapter, u8 conf_idx, struct tx_aclt_conf_t *input, u8 arg_num)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct tx_aclt_conf_t *conf;\n\n\tif (conf_idx >= TX_ACLT_CONF_NUM)\n\t\treturn;\n\n\tconf = &dvobj->tx_aclt_confs[conf_idx];\n\n\tif (arg_num >= 1) {\n\t\tif (input->en != 0xFF)\n\t\t\tconf->en = input->en & 0xF;\n\t}\n\tif (arg_num >= 2) {\n\t\tconf->vo_vi = input->vo_vi / (hal_spec->tx_aclt_unit_factor * 32);\n\t\tif (conf->vo_vi > 0xFFFF)\n\t\t\tconf->vo_vi = 0xFFFF;\n\t}\n\tif (arg_num >= 3) {\n\t\tconf->be_bk = input->be_bk / (hal_spec->tx_aclt_unit_factor * 32);\n\t\tif (conf->be_bk > 0xFFFF)\n\t\t\tconf->be_bk = 0xFFFF;\n\t}\n}\n\nvoid rtw_hal_update_tx_aclt(_adapter *adapter)\n{\n#ifdef CONFIG_TX_MCAST2UNI\n\textern int rtw_mc2u_disable;\n#endif\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);\n\tu8 lt_en = 0, lt_en_ori;\n\tu16 lt_vo_vi = 0xFFFF, lt_be_bk = 0xFFFF;\n\tu32 lt, lt_ori;\n\tstruct tx_aclt_conf_t *conf;\n\tint i;\n\n\tlt_en_ori = rtw_read8(adapter, REG_LIFETIME_EN);\n\tlt_ori = rtw_read32(adapter, REG_PKT_LIFE_TIME);\n\n\tfor (i = 0; i < TX_ACLT_CONF_NUM; i++) {\n\t\tif (!(dvobj->tx_aclt_flags & BIT(i)))\n\t\t\tcontinue;\n\n\t\tconf = &dvobj->tx_aclt_confs[i];\n\n\t\tif (i == TX_ACLT_CONF_DEFAULT) {\n\t\t\t/* first and default status, assign directly */\n\t\t\tlt_en = conf->en;\n\t\t\tif (conf->vo_vi)\n\t\t\t\tlt_vo_vi = conf->vo_vi;\n\t\t\tif (conf->be_bk)\n\t\t\t\tlt_be_bk = conf->be_bk;\n\t\t}\n\t\t#if defined(CONFIG_TX_MCAST2UNI) || defined(CONFIG_RTW_MESH)\n\t\telse if (0\n\t\t\t#ifdef CONFIG_TX_MCAST2UNI\n\t\t\t|| (i == TX_ACLT_CONF_AP_M2U\n\t\t\t\t&& !rtw_mc2u_disable\n\t\t\t\t&& macid_ctl->op_num[H2C_MSR_ROLE_STA] /* having AP mode with STA connected */)\n\t\t\t#endif\n\t\t\t#ifdef CONFIG_RTW_MESH\n\t\t\t|| (i == TX_ACLT_CONF_MESH\n\t\t\t\t&& macid_ctl->op_num[H2C_MSR_ROLE_MESH] > 1 /* implies only 1 MESH mode supported */)\n\t\t\t#endif\n\t\t) {\n\t\t\t/* long term status, OR en and MIN lifetime */\n\t\t\tlt_en |= conf->en;\n\t\t\tif (conf->vo_vi && lt_vo_vi > conf->vo_vi)\n\t\t\t\tlt_vo_vi = conf->vo_vi;\n\t\t\tif (conf->be_bk && lt_be_bk > conf->be_bk)\n\t\t\t\tlt_be_bk = conf->be_bk;\n\t\t}\n\t\t#endif\n\t}\n\n\tif (dvobj->tx_aclt_force_val.en != 0xFF)\n\t\tlt_en = dvobj->tx_aclt_force_val.en;\n\tif (dvobj->tx_aclt_force_val.vo_vi)\n\t\tlt_vo_vi = dvobj->tx_aclt_force_val.vo_vi;\n\tif (dvobj->tx_aclt_force_val.be_bk)\n\t\tlt_be_bk = dvobj->tx_aclt_force_val.be_bk;\n\n\tlt_en = (lt_en_ori & 0xF0) | (lt_en & 0x0F);\n\tlt = (lt_be_bk << 16) | lt_vo_vi;\n\n\tif (0)\n\t\tRTW_INFO(\"lt_en:0x%x(0x%x), lt:0x%08x(0x%08x)\\n\", lt_en, lt_en_ori, lt, lt_ori);\n\n\tif (lt_en != lt_en_ori)\n\t\trtw_write8(adapter, REG_LIFETIME_EN, lt_en);\n\tif (lt != lt_ori)\n\t\trtw_write32(adapter, REG_PKT_LIFE_TIME, lt);\n}\n#endif /* CONFIG_TX_AC_LIFETIME */\n\nvoid hw_var_port_switch(_adapter *adapter)\n{\n#ifdef CONFIG_CONCURRENT_MODE\n#ifdef CONFIG_RUNTIME_PORT_SWITCH\n\t/*\n\t0x102: MSR\n\t0x550: REG_BCN_CTRL\n\t0x551: REG_BCN_CTRL_1\n\t0x55A: REG_ATIMWND\n\t0x560: REG_TSFTR\n\t0x568: REG_TSFTR1\n\t0x570: REG_ATIMWND_1\n\t0x610: REG_MACID\n\t0x618: REG_BSSID\n\t0x700: REG_MACID1\n\t0x708: REG_BSSID1\n\t*/\n\n\tint i;\n\tu8 msr;\n\tu8 bcn_ctrl;\n\tu8 bcn_ctrl_1;\n\tu8 atimwnd[2];\n\tu8 atimwnd_1[2];\n\tu8 tsftr[8];\n\tu8 tsftr_1[8];\n\tu8 macid[6];\n\tu8 bssid[6];\n\tu8 macid_1[6];\n\tu8 bssid_1[6];\n#if defined(CONFIG_RTL8192F)\n\tu16 wlan_act_mask_ctrl = 0;\n\tu16 en_port_mask = EN_PORT_0_FUNCTION | EN_PORT_1_FUNCTION;\n#endif\n\n\tu8 hw_port;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\t_adapter *iface = NULL;\n\n\tmsr = rtw_read8(adapter, MSR);\n\tbcn_ctrl = rtw_read8(adapter, REG_BCN_CTRL);\n\tbcn_ctrl_1 = rtw_read8(adapter, REG_BCN_CTRL_1);\n#if defined(CONFIG_RTL8192F)\n\twlan_act_mask_ctrl = rtw_read16(adapter, REG_WLAN_ACT_MASK_CTRL_1);\n#endif\n\n\tfor (i = 0; i < 2; i++)\n\t\tatimwnd[i] = rtw_read8(adapter, REG_ATIMWND + i);\n\tfor (i = 0; i < 2; i++)\n\t\tatimwnd_1[i] = rtw_read8(adapter, REG_ATIMWND_1 + i);\n\n\tfor (i = 0; i < 8; i++)\n\t\ttsftr[i] = rtw_read8(adapter, REG_TSFTR + i);\n\tfor (i = 0; i < 8; i++)\n\t\ttsftr_1[i] = rtw_read8(adapter, REG_TSFTR1 + i);\n\n\tfor (i = 0; i < 6; i++)\n\t\tmacid[i] = rtw_read8(adapter, REG_MACID + i);\n\n\tfor (i = 0; i < 6; i++)\n\t\tbssid[i] = rtw_read8(adapter, REG_BSSID + i);\n\n\tfor (i = 0; i < 6; i++)\n\t\tmacid_1[i] = rtw_read8(adapter, REG_MACID1 + i);\n\n\tfor (i = 0; i < 6; i++)\n\t\tbssid_1[i] = rtw_read8(adapter, REG_BSSID1 + i);\n\n#ifdef DBG_RUNTIME_PORT_SWITCH\n\tRTW_INFO(FUNC_ADPT_FMT\" before switch\\n\"\n\t\t \"msr:0x%02x\\n\"\n\t\t \"bcn_ctrl:0x%02x\\n\"\n\t\t \"bcn_ctrl_1:0x%02x\\n\"\n#if defined(CONFIG_RTL8192F)\n\t\t \"wlan_act_mask_ctrl:0x%02x\\n\"\n#endif\n\t\t \"atimwnd:0x%04x\\n\"\n\t\t \"atimwnd_1:0x%04x\\n\"\n\t\t \"tsftr:%llu\\n\"\n\t\t \"tsftr1:%llu\\n\"\n\t\t \"macid:\"MAC_FMT\"\\n\"\n\t\t \"bssid:\"MAC_FMT\"\\n\"\n\t\t \"macid_1:\"MAC_FMT\"\\n\"\n\t\t \"bssid_1:\"MAC_FMT\"\\n\"\n\t\t , FUNC_ADPT_ARG(adapter)\n\t\t , msr\n\t\t , bcn_ctrl\n\t\t , bcn_ctrl_1\n#if defined(CONFIG_RTL8192F)\n\t\t , wlan_act_mask_ctrl\n#endif\n\t\t , *((u16 *)atimwnd)\n\t\t , *((u16 *)atimwnd_1)\n\t\t , *((u64 *)tsftr)\n\t\t , *((u64 *)tsftr_1)\n\t\t , MAC_ARG(macid)\n\t\t , MAC_ARG(bssid)\n\t\t , MAC_ARG(macid_1)\n\t\t , MAC_ARG(bssid_1)\n\t\t);\n#endif /* DBG_RUNTIME_PORT_SWITCH */\n\n\t/* disable bcn function, disable update TSF */\n\trtw_write8(adapter, REG_BCN_CTRL, (bcn_ctrl & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT);\n\trtw_write8(adapter, REG_BCN_CTRL_1, (bcn_ctrl_1 & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT);\n\n#if defined(CONFIG_RTL8192F)\n\trtw_write16(adapter, REG_WLAN_ACT_MASK_CTRL_1, wlan_act_mask_ctrl & ~en_port_mask);\n#endif\n\n\t/* switch msr */\n\tmsr = (msr & 0xf0) | ((msr & 0x03) << 2) | ((msr & 0x0c) >> 2);\n\trtw_write8(adapter, MSR, msr);\n\n\t/* write port0 */\n\trtw_write8(adapter, REG_BCN_CTRL, bcn_ctrl_1 & ~EN_BCN_FUNCTION);\n\tfor (i = 0; i < 2; i++)\n\t\trtw_write8(adapter, REG_ATIMWND + i, atimwnd_1[i]);\n\tfor (i = 0; i < 8; i++)\n\t\trtw_write8(adapter, REG_TSFTR + i, tsftr_1[i]);\n\tfor (i = 0; i < 6; i++)\n\t\trtw_write8(adapter, REG_MACID + i, macid_1[i]);\n\tfor (i = 0; i < 6; i++)\n\t\trtw_write8(adapter, REG_BSSID + i, bssid_1[i]);\n\n\t/* write port1 */\n\trtw_write8(adapter, REG_BCN_CTRL_1, bcn_ctrl & ~EN_BCN_FUNCTION);\n\tfor (i = 0; i < 2; i++)\n\t\trtw_write8(adapter, REG_ATIMWND_1 + i, atimwnd[i]);\n\tfor (i = 0; i < 8; i++)\n\t\trtw_write8(adapter, REG_TSFTR1 + i, tsftr[i]);\n\tfor (i = 0; i < 6; i++)\n\t\trtw_write8(adapter, REG_MACID1 + i, macid[i]);\n\tfor (i = 0; i < 6; i++)\n\t\trtw_write8(adapter, REG_BSSID1 + i, bssid[i]);\n\n\t/* write bcn ctl */\n#ifdef CONFIG_BT_COEXIST\n\t/* always enable port0 beacon function for PSTDMA */\n\tif (IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8703B(adapter)\n\t    || IS_HARDWARE_TYPE_8723D(adapter))\n\t\tbcn_ctrl_1 |= EN_BCN_FUNCTION;\n\t/* always disable port1 beacon function for PSTDMA */\n\tif (IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8703B(adapter))\n\t\tbcn_ctrl &= ~EN_BCN_FUNCTION;\n#endif\n\trtw_write8(adapter, REG_BCN_CTRL, bcn_ctrl_1);\n\trtw_write8(adapter, REG_BCN_CTRL_1, bcn_ctrl);\n\n#if defined(CONFIG_RTL8192F)\n\t/* if the setting of port0 and port1 are the same, it does not need to switch port setting*/\n\tif(((wlan_act_mask_ctrl & en_port_mask) != 0) && ((wlan_act_mask_ctrl & en_port_mask)\n\t\t!= (EN_PORT_0_FUNCTION | EN_PORT_1_FUNCTION)))\n\t\twlan_act_mask_ctrl ^= en_port_mask;\n\trtw_write16(adapter, REG_WLAN_ACT_MASK_CTRL_1, wlan_act_mask_ctrl);\n#endif\n\n\tif (adapter->iface_id == IFACE_ID0)\n\t\tiface = dvobj->padapters[IFACE_ID1];\n\telse if (adapter->iface_id == IFACE_ID1)\n\t\tiface = dvobj->padapters[IFACE_ID0];\n\n\n\tif (adapter->hw_port == HW_PORT0) {\n\t\tadapter->hw_port = HW_PORT1;\n\t\tiface->hw_port = HW_PORT0;\n\t\tRTW_PRINT(\"port switch - port0(\"ADPT_FMT\"), port1(\"ADPT_FMT\")\\n\",\n\t\t\t  ADPT_ARG(iface), ADPT_ARG(adapter));\n\t} else {\n\t\tadapter->hw_port = HW_PORT0;\n\t\tiface->hw_port = HW_PORT1;\n\t\tRTW_PRINT(\"port switch - port0(\"ADPT_FMT\"), port1(\"ADPT_FMT\")\\n\",\n\t\t\t  ADPT_ARG(adapter), ADPT_ARG(iface));\n\t}\n\n#ifdef DBG_RUNTIME_PORT_SWITCH\n\tmsr = rtw_read8(adapter, MSR);\n\tbcn_ctrl = rtw_read8(adapter, REG_BCN_CTRL);\n\tbcn_ctrl_1 = rtw_read8(adapter, REG_BCN_CTRL_1);\n#if defined(CONFIG_RTL8192F)\n\twlan_act_mask_ctrl = rtw_read16(adapter, REG_WLAN_ACT_MASK_CTRL_1);\n#endif\n\n\tfor (i = 0; i < 2; i++)\n\t\tatimwnd[i] = rtw_read8(adapter, REG_ATIMWND + i);\n\tfor (i = 0; i < 2; i++)\n\t\tatimwnd_1[i] = rtw_read8(adapter, REG_ATIMWND_1 + i);\n\n\tfor (i = 0; i < 8; i++)\n\t\ttsftr[i] = rtw_read8(adapter, REG_TSFTR + i);\n\tfor (i = 0; i < 8; i++)\n\t\ttsftr_1[i] = rtw_read8(adapter, REG_TSFTR1 + i);\n\n\tfor (i = 0; i < 6; i++)\n\t\tmacid[i] = rtw_read8(adapter, REG_MACID + i);\n\n\tfor (i = 0; i < 6; i++)\n\t\tbssid[i] = rtw_read8(adapter, REG_BSSID + i);\n\n\tfor (i = 0; i < 6; i++)\n\t\tmacid_1[i] = rtw_read8(adapter, REG_MACID1 + i);\n\n\tfor (i = 0; i < 6; i++)\n\t\tbssid_1[i] = rtw_read8(adapter, REG_BSSID1 + i);\n\n\tRTW_INFO(FUNC_ADPT_FMT\" after switch\\n\"\n\t\t \"msr:0x%02x\\n\"\n\t\t \"bcn_ctrl:0x%02x\\n\"\n\t\t \"bcn_ctrl_1:0x%02x\\n\"\n#if defined(CONFIG_RTL8192F)\n\t\t \"wlan_act_mask_ctrl:0x%02x\\n\"\n#endif\n\t\t \"atimwnd:%u\\n\"\n\t\t \"atimwnd_1:%u\\n\"\n\t\t \"tsftr:%llu\\n\"\n\t\t \"tsftr1:%llu\\n\"\n\t\t \"macid:\"MAC_FMT\"\\n\"\n\t\t \"bssid:\"MAC_FMT\"\\n\"\n\t\t \"macid_1:\"MAC_FMT\"\\n\"\n\t\t \"bssid_1:\"MAC_FMT\"\\n\"\n\t\t , FUNC_ADPT_ARG(adapter)\n\t\t , msr\n\t\t , bcn_ctrl\n\t\t , bcn_ctrl_1\n#if defined(CONFIG_RTL8192F)\n\t\t , wlan_act_mask_ctrl\n#endif\n\t\t , *((u16 *)atimwnd)\n\t\t , *((u16 *)atimwnd_1)\n\t\t , *((u64 *)tsftr)\n\t\t , *((u64 *)tsftr_1)\n\t\t , MAC_ARG(macid)\n\t\t , MAC_ARG(bssid)\n\t\t , MAC_ARG(macid_1)\n\t\t , MAC_ARG(bssid_1)\n\t\t);\n#endif /* DBG_RUNTIME_PORT_SWITCH */\n\n#endif /* CONFIG_RUNTIME_PORT_SWITCH */\n#endif /* CONFIG_CONCURRENT_MODE */\n}\n\nconst char *const _h2c_msr_role_str[] = {\n\t\"RSVD\",\n\t\"STA\",\n\t\"AP\",\n\t\"GC\",\n\t\"GO\",\n\t\"TDLS\",\n\t\"ADHOC\",\n\t\"MESH\",\n\t\"INVALID\",\n};\n\n#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\ns32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id)\n{\n\ts32 ret = _SUCCESS;\n\tu8 parm[H2C_DEFAULT_PORT_ID_LEN] = {0};\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tu8 port_id = rtw_hal_get_port(adapter);\n\n\tif ((dvobj->dft.port_id == port_id) && (dvobj->dft.mac_id == mac_id))\n\t\treturn ret;\n\n\tSET_H2CCMD_DFTPID_PORT_ID(parm, port_id);\n\tSET_H2CCMD_DFTPID_MAC_ID(parm, mac_id);\n\n\tRTW_DBG_DUMP(\"DFT port id parm:\", parm, H2C_DEFAULT_PORT_ID_LEN);\n\tRTW_INFO(\"%s (\"ADPT_FMT\") port_id :%d, mad_id:%d\\n\",\n\t\t__func__, ADPT_ARG(adapter), port_id, mac_id);\n\n\tret = rtw_hal_fill_h2c_cmd(adapter, H2C_DEFAULT_PORT_ID, H2C_DEFAULT_PORT_ID_LEN, parm);\n\tdvobj->dft.port_id = port_id;\n\tdvobj->dft.mac_id = mac_id;\n\n\treturn ret;\n}\ns32 rtw_set_default_port_id(_adapter *adapter)\n{\n\ts32 ret = _SUCCESS;\n\tstruct sta_info\t\t*psta;\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\n\tif (is_client_associated_to_ap(adapter)) {\n\t\tpsta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));\n\t\tif (psta)\n\t\t\tret = rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id);\n\t} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {\n\n\t} else {\n\t}\n\n\treturn ret;\n}\ns32 rtw_set_ps_rsvd_page(_adapter *adapter)\n{\n\ts32 ret = _SUCCESS;\n\tu16 media_status_rpt = RT_MEDIA_CONNECT;\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);\n\n\tif (adapter->iface_id == pwrctl->fw_psmode_iface_id)\n\t\treturn ret;\n\n\trtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,\n\t\t\t  (u8 *)&media_status_rpt);\n\n\treturn ret;\n}\n\n#if 0\n_adapter * _rtw_search_dp_iface(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\t_adapter *iface;\n\t_adapter *target_iface = NULL;\n\tint i;\n\tu8 sta_num = 0, tdls_num = 0, ap_num = 0, mesh_num = 0, adhoc_num = 0;\n\tu8 p2p_go_num = 0, p2p_gc_num = 0;\n\t_adapter *sta_ifs[8];\n\t_adapter *ap_ifs[8];\n\t_adapter *mesh_ifs[8];\n\t_adapter *gc_ifs[8];\n\t_adapter *go_ifs[8];\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\n\t\tif (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) {\n\t\t\tif (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) {\n\t\t\t\tsta_ifs[sta_num++] = iface;\n\n\t\t\t\t#ifdef CONFIG_TDLS\n\t\t\t\tif (iface->tdlsinfo.link_established == _TRUE)\n\t\t\t\t\ttdls_num++;\n\t\t\t\t#endif\n\t\t\t\t#ifdef CONFIG_P2P\n\t\t\t\tif (MLME_IS_GC(iface))\n\t\t\t\t\tgc_ifs[p2p_gc_num++] = iface;\n\t\t\t\t#endif\n\t\t\t}\n#ifdef CONFIG_AP_MODE\n\t\t} else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE ) {\n\t\t\tif (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) {\n\t\t\t\tap_ifs[ap_num++] = iface;\n\t\t\t\t#ifdef CONFIG_P2P\n\t\t\t\tif (MLME_IS_GO(iface))\n\t\t\t\t\tgo_ifs[p2p_go_num++] = iface;\n\t\t\t\t#endif\n\t\t\t}\n#endif\n\t\t} else if (check_fwstate(&iface->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE\n\t\t\t&& check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE\n\t\t) {\n\t\t\tadhoc_num++;\n\n#ifdef CONFIG_RTW_MESH\n\t\t} else if (check_fwstate(&iface->mlmepriv, WIFI_MESH_STATE) == _TRUE\n\t\t\t&& check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE\n\t\t) {\n\t\t\tmesh_ifs[mesh_num++] = iface;\n#endif\n\t\t}\n\t}\n\n\tif (p2p_gc_num) {\n\t\ttarget_iface = gc_ifs[0];\n\t}\n\telse if (sta_num) {\n\t\tif(sta_num == 1) {\n\t\t\ttarget_iface = sta_ifs[0];\n\t\t} else if (sta_num >= 2) {\n\t\t\t/*TODO get target_iface by timestamp*/\n\t\t\ttarget_iface = sta_ifs[0];\n\t\t}\n\t} else if (ap_num) {\n\t\ttarget_iface = ap_ifs[0];\n\t}\n\n\tRTW_INFO(\"[IFS_ASSOC_STATUS] - STA :%d\", sta_num);\n\tRTW_INFO(\"[IFS_ASSOC_STATUS] - TDLS :%d\", tdls_num);\n\tRTW_INFO(\"[IFS_ASSOC_STATUS] - AP:%d\", ap_num);\n\tRTW_INFO(\"[IFS_ASSOC_STATUS] - MESH :%d\", mesh_num);\n\tRTW_INFO(\"[IFS_ASSOC_STATUS] - ADHOC :%d\", adhoc_num);\n\tRTW_INFO(\"[IFS_ASSOC_STATUS] - P2P-GC :%d\", p2p_gc_num);\n\tRTW_INFO(\"[IFS_ASSOC_STATUS] - P2P-GO :%d\", p2p_go_num);\n\n\tif (target_iface)\n\t\tRTW_INFO(\"%s => target_iface (\"ADPT_FMT\")\\n\",\n\t\t\t__func__, ADPT_ARG(target_iface));\n\telse\n\t\tRTW_INFO(\"%s => target_iface NULL\\n\", __func__);\n\n\treturn target_iface;\n}\n\nvoid rtw_search_default_port(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\t_adapter *adp_iface = NULL;\n#ifdef CONFIG_WOWLAN\n\tstruct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);\n\n\tif (pwrpriv->wowlan_mode == _TRUE) {\n\t\tadp_iface = adapter;\n\t\tgoto exit;\n\t}\n#endif\n\tadp_iface = _rtw_search_dp_iface(adapter);\n\nexit :\n\tif ((adp_iface != NULL) && (MLME_IS_STA(adp_iface)))\n\t\trtw_set_default_port_id(adp_iface);\n\telse\n\t\trtw_hal_set_default_port_id_cmd(adapter, 0);\n\n\tif (1) {\n\t\t_adapter *tmp_adp;\n\n\t\ttmp_adp = (adp_iface) ? adp_iface : adapter;\n\n\t\tRTW_INFO(\"%s (\"ADPT_FMT\")=> hw_port :%d, default_port(%d)\\n\",\n\t\t\t__func__, ADPT_ARG(adapter), get_hw_port(tmp_adp), get_dft_portid(tmp_adp));\n\t}\n}\n#endif\n#endif /*CONFIG_FW_MULTI_PORT_SUPPORT*/\n\n#ifdef CONFIG_P2P_PS\n#ifdef RTW_HALMAC\nvoid rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tstruct wifidirect_info *pwdinfo = &adapter->wdinfo;\n\tstruct mlme_ext_priv\t*pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t\t*cur_network = &(pmlmeinfo->network);\n\tstruct sta_priv\t\t*pstapriv = &adapter->stapriv;\n\tstruct sta_info\t\t*psta;\n\tHAL_P2P_PS_PARA p2p_ps_para;\n\tint status = -1;\n\tu8 i;\n\tu8 hw_port = rtw_hal_get_port(adapter);\n\n\t_rtw_memset(&p2p_ps_para, 0, sizeof(HAL_P2P_PS_PARA));\n\t_rtw_memcpy((&p2p_ps_para) , &hal->p2p_ps_offload , sizeof(hal->p2p_ps_offload));\n\n\t(&p2p_ps_para)->p2p_port_id = hw_port;\n\t(&p2p_ps_para)->p2p_group = 0;\n\tpsta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);\n\tif (psta) {\n\t\t(&p2p_ps_para)->p2p_macid = psta->cmn.mac_id;\n\t} else {\n\t\tif (p2p_ps_state != P2P_PS_DISABLE) {\n\t\t\tRTW_ERR(\"%s , psta was NULL\\n\", __func__);\n\t\t\treturn;\n\t\t}\n\t}\n\n\n\tswitch (p2p_ps_state) {\n\tcase P2P_PS_DISABLE:\n\t\tRTW_INFO(\"P2P_PS_DISABLE\\n\");\n\t\t_rtw_memset(&p2p_ps_para , 0, sizeof(HAL_P2P_PS_PARA));\n\t\tbreak;\n\n\tcase P2P_PS_ENABLE:\n\t\tRTW_INFO(\"P2P_PS_ENABLE\\n\");\n\t\t/* update CTWindow value. */\n\t\tif (pwdinfo->ctwindow > 0) {\n\t\t\t(&p2p_ps_para)->ctwindow_en = 1;\n\t\t\t(&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;\n\t\t\t/*RTW_INFO(\"%s , ctwindow_length = %d\\n\" , __func__ , (&p2p_ps_para)->ctwindow_length);*/\n\t\t}\n\n\n\t\tif ((pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0)) {\n\t\t\t(&p2p_ps_para)->offload_en = 1;\n\t\t\tif (pwdinfo->role == P2P_ROLE_GO) {\n\t\t\t\t(&p2p_ps_para)->role = 1;\n\t\t\t\t(&p2p_ps_para)->all_sta_sleep = 0;\n\t\t\t} else\n\t\t\t\t(&p2p_ps_para)->role = 0;\n\n\t\t\t(&p2p_ps_para)->discovery = 0;\n\t\t}\n\t\t/* hw only support 2 set of NoA */\n\t\tfor (i = 0; i < pwdinfo->noa_num; i++) {\n\t\t\t/* To control the register setting for which NOA */\n\t\t\t(&p2p_ps_para)->noa_sel = i;\n\t\t\t(&p2p_ps_para)->noa_en = 1;\n\t\t\t(&p2p_ps_para)->disable_close_rf = 0;\n#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP\n#ifdef CONFIG_CONCURRENT_MODE\n\t\t\tif (rtw_mi_buddy_check_fwstate(adapter, WIFI_ASOC_STATE))\n#endif /* CONFIG_CONCURRENT_MODE */\n\t\t\t\t(&p2p_ps_para)->disable_close_rf = 1;\n#endif /* CONFIG_P2P_PS_NOA_USE_MACID_SLEEP */\n\t\t\t/* config P2P NoA Descriptor Register */\n\t\t\t/* config NOA duration */\n\t\t\t(&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[i];\n\t\t\t/* config NOA interval */\n\t\t\t(&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[i];\n\t\t\t/* config NOA start time */\n\t\t\t(&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[i];\n\t\t\t/* config NOA count */\n\t\t\t(&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[i];\n\t\t\t/*RTW_INFO(\"%s , noa_duration_para = %d , noa_interval_para = %d , noa_start_time_para = %d , noa_count_para = %d\\n\" , __func__ ,\n\t\t\t\t(&p2p_ps_para)->noa_duration_para , (&p2p_ps_para)->noa_interval_para ,\n\t\t\t\t(&p2p_ps_para)->noa_start_time_para , (&p2p_ps_para)->noa_count_para);*/\n\t\t\tstatus = rtw_halmac_p2pps(adapter_to_dvobj(adapter) , (&p2p_ps_para));\n\t\t\tif (status == -1)\n\t\t\t\tRTW_ERR(\"%s , rtw_halmac_p2pps fail\\n\", __func__);\n\t\t}\n\n\t\tbreak;\n\n\tcase P2P_PS_SCAN:\n\t\t/*This feature FW not ready 20161116 YiWei*/\n\t\treturn;\n\t\tRTW_INFO(\"P2P_PS_SCAN\\n\");\n\t\t(&p2p_ps_para)->discovery = 1;\n\t\t/*\n\t\t(&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;\n\t\t(&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[0];\n\t\t(&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[0];\n\t\t(&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[0];\n\t\t(&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[0];\n\t\t*/\n\t\tbreak;\n\n\tcase P2P_PS_SCAN_DONE:\n\t\t/*This feature FW not ready 20161116 YiWei*/\n\t\treturn;\n\t\tRTW_INFO(\"P2P_PS_SCAN_DONE\\n\");\n\t\t(&p2p_ps_para)->discovery = 0;\n\t\t/*\n\t\tpwdinfo->p2p_ps_state = P2P_PS_ENABLE;\n\t\t(&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;\n\t\t(&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[0];\n\t\t(&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[0];\n\t\t(&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[0];\n\t\t(&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[0];\n\t\t*/\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (p2p_ps_state != P2P_PS_ENABLE || (&p2p_ps_para)->noa_en == 0) {\n\t\tstatus = rtw_halmac_p2pps(adapter_to_dvobj(adapter) , (&p2p_ps_para));\n\t\tif (status == -1)\n\t\t\tRTW_ERR(\"%s , rtw_halmac_p2pps fail\\n\", __func__);\n\t}\n\t_rtw_memcpy(&hal->p2p_ps_offload , (&p2p_ps_para) , sizeof(hal->p2p_ps_offload));\n\n}\n#endif /* RTW_HALMAC */\n#endif /* CONFIG_P2P */\n\n/*\n* rtw_hal_set_FwMediaStatusRpt_cmd -\n*\n* @adapter:\n* @opmode:  0:disconnect, 1:connect\n* @miracast: 0:it's not in miracast scenario. 1:it's in miracast scenario\n* @miracast_sink: 0:source. 1:sink\n* @role: The role of this macid. 0:rsvd. 1:STA. 2:AP. 3:GC. 4:GO. 5:TDLS\n* @macid:\n* @macid_ind:  0:update Media Status to macid.  1:update Media Status from macid to macid_end\n* @macid_end:\n*/\ns32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, bool macid_ind, u8 macid_end)\n{\n\tstruct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;\n\tu8 parm[H2C_MEDIA_STATUS_RPT_LEN] = {0};\n\tint i;\n\ts32 ret;\n#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\tu8 hw_port = rtw_hal_get_port(adapter);\n#endif\n\tu8 op_num_change_bmp = 0;\n\n\tSET_H2CCMD_MSRRPT_PARM_OPMODE(parm, opmode);\n\tSET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, macid_ind);\n\tSET_H2CCMD_MSRRPT_PARM_MIRACAST(parm, miracast);\n\tSET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(parm, miracast_sink);\n\tSET_H2CCMD_MSRRPT_PARM_ROLE(parm, role);\n\tSET_H2CCMD_MSRRPT_PARM_MACID(parm, macid);\n\tSET_H2CCMD_MSRRPT_PARM_MACID_END(parm, macid_end);\n#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\tSET_H2CCMD_MSRRPT_PARM_PORT_NUM(parm, hw_port);\n#endif\n\tRTW_DBG_DUMP(\"MediaStatusRpt parm:\", parm, H2C_MEDIA_STATUS_RPT_LEN);\n\n\tret = rtw_hal_fill_h2c_cmd(adapter, H2C_MEDIA_STATUS_RPT, H2C_MEDIA_STATUS_RPT_LEN, parm);\n\tif (ret != _SUCCESS)\n\t\tgoto exit;\n\n#if defined(CONFIG_RTL8188E)\n\tif (rtw_get_chip_type(adapter) == RTL8188E) {\n\t\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\n\t\t/* 8188E FW doesn't set macid no link, driver does it by self */\n\t\tif (opmode)\n\t\t\trtw_hal_set_hwreg(adapter, HW_VAR_MACID_LINK, &macid);\n\t\telse\n\t\t\trtw_hal_set_hwreg(adapter, HW_VAR_MACID_NOLINK, &macid);\n\n\t\t/* for 8188E RA */\n#if (RATE_ADAPTIVE_SUPPORT == 1)\n\t\tif (hal_data->fw_ractrl == _FALSE) {\n\t\t\tu8 max_macid;\n\n\t\t\tmax_macid = rtw_search_max_mac_id(adapter);\n\t\t\trtw_hal_set_hwreg(adapter, HW_VAR_TX_RPT_MAX_MACID, &max_macid);\n\t\t}\n#endif\n\t}\n#endif\n\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\n\t/* TODO: this should move to IOT issue area */\n\tif (rtw_get_chip_type(adapter) == RTL8812\n\t\t|| rtw_get_chip_type(adapter) == RTL8821\n\t) {\n\t\tif (MLME_IS_STA(adapter))\n\t\t\tHal_PatchwithJaguar_8812(adapter, opmode);\n\t}\n#endif\n\n\tSET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, 0);\n\tif (macid_ind == 0)\n\t\tmacid_end = macid;\n\n\tfor (i = macid; macid <= macid_end; macid++) {\n\t\top_num_change_bmp |= rtw_macid_ctl_set_h2c_msr(macid_ctl, macid, parm[0]);\n\t\tif (!opmode) {\n\t\t\trtw_macid_ctl_set_bw(macid_ctl, macid, CHANNEL_WIDTH_20);\n\t\t\trtw_macid_ctl_set_vht_en(macid_ctl, macid, 0);\n\t\t\trtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, 0);\n\t\t\trtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, 0);\n\t\t}\n\t}\n\n#if CONFIG_TX_AC_LIFETIME\n\tif (op_num_change_bmp)\n\t\trtw_hal_update_tx_aclt(adapter);\n#endif\n\n\tif (!opmode)\n\t\trtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));\n\nexit:\n\treturn ret;\n}\n\ninline s32 rtw_hal_set_FwMediaStatusRpt_single_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid)\n{\n\treturn rtw_hal_set_FwMediaStatusRpt_cmd(adapter, opmode, miracast, miracast_sink, role, macid, 0, 0);\n}\n\ninline s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, u8 macid_end)\n{\n\treturn rtw_hal_set_FwMediaStatusRpt_cmd(adapter, opmode, miracast, miracast_sink, role, macid, 1, macid_end);\n}\n\nvoid rtw_hal_set_FwRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)\n{\n\tstruct\thal_ops *pHalFunc = &padapter->hal_func;\n\tu8\tu1H2CRsvdPageParm[H2C_RSVDPAGE_LOC_LEN] = {0};\n\tu8\tret = 0;\n\n\tRTW_INFO(\"RsvdPageLoc: ProbeRsp=%d PsPoll=%d Null=%d QoSNull=%d BTNull=%d\\n\",\n\t\t rsvdpageloc->LocProbeRsp, rsvdpageloc->LocPsPoll,\n\t\t rsvdpageloc->LocNullData, rsvdpageloc->LocQosNull,\n\t\t rsvdpageloc->LocBTQosNull);\n\n\tSET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1H2CRsvdPageParm, rsvdpageloc->LocProbeRsp);\n\tSET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1H2CRsvdPageParm, rsvdpageloc->LocPsPoll);\n\tSET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocNullData);\n\tSET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocQosNull);\n\tSET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocBTQosNull);\n\n\tret = rtw_hal_fill_h2c_cmd(padapter,\n\t\t\t\t   H2C_RSVD_PAGE,\n\t\t\t\t   H2C_RSVDPAGE_LOC_LEN,\n\t\t\t\t   u1H2CRsvdPageParm);\n\n}\n\n#ifdef CONFIG_GPIO_WAKEUP\nvoid rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable)\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);\n\n\tif (IS_8723D_SERIES(pHalData->version_id) || IS_8192F_SERIES(pHalData->version_id)\n\t\t|| IS_8822B_SERIES(pHalData->version_id) || IS_8821C_SERIES(pHalData->version_id)\n\t\t|| IS_8822C_SERIES(pHalData->version_id))\n\t\trtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable));\n\t/*\n\t* Switch GPIO_13, GPIO_14 to wlan control, or pull GPIO_13,14 MUST fail.\n\t* It happended at 8723B/8192E/8821A. New IC will check multi function GPIO,\n\t* and implement HAL function.\n\t* TODO: GPIO_8 multi function?\n\t*/\n\n\tif ((index == 13 || index == 14)\n\t\t#if defined(CONFIG_RTL8821A) && defined(CONFIG_SDIO_HCI)\n\t\t/* 8821A's LED2 circuit(used by HW_LED strategy) needs enable WL GPIO control of GPIO[14:13], can't disable */\n\t\t&& (!IS_HW_LED_STRATEGY(rtw_led_get_strategy(padapter)) || enable)\n\t\t#endif\n\t)\n\t\trtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable));\n}\n\nvoid rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval)\n{\n#if defined(CONFIG_RTL8192F)\n\trtw_hal_set_hwreg(padapter, HW_VAR_WOW_OUTPUT_GPIO, (u8 *)(&index));\n#else\n\tif (index <= 7) {\n\t\t/* config GPIO mode */\n\t\trtw_write8(padapter, REG_GPIO_PIN_CTRL + 3,\n\t\t\trtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index));\n\n\t\t/* config GPIO Sel */\n\t\t/* 0: input */\n\t\t/* 1: output */\n\t\trtw_write8(padapter, REG_GPIO_PIN_CTRL + 2,\n\t\t\trtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) | BIT(index));\n\n\t\t/* set output value */\n\t\tif (outputval) {\n\t\t\trtw_write8(padapter, REG_GPIO_PIN_CTRL + 1,\n\t\t\t\trtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) | BIT(index));\n\t\t} else {\n\t\t\trtw_write8(padapter, REG_GPIO_PIN_CTRL + 1,\n\t\t\t\trtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) & ~BIT(index));\n\t\t}\n\t} else if (index <= 15) {\n\t\t/* 88C Series: */\n\t\t/* index: 11~8 transform to 3~0 */\n\t\t/* 8723 Series: */\n\t\t/* index: 12~8 transform to 4~0 */\n\n\t\tindex -= 8;\n\n\t\t/* config GPIO mode */\n\t\trtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3,\n\t\t\trtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index));\n\n\t\t/* config GPIO Sel */\n\t\t/* 0: input */\n\t\t/* 1: output */\n\t\trtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2,\n\t\t\trtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) | BIT(index));\n\n\t\t/* set output value */\n\t\tif (outputval) {\n\t\t\trtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1,\n\t\t\t\trtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) | BIT(index));\n\t\t} else {\n\t\t\trtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1,\n\t\t\t\trtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) & ~BIT(index));\n\t\t}\n\t} else {\n\t\tRTW_INFO(\"%s: invalid GPIO%d=%d\\n\",\n\t\t\t __FUNCTION__, index, outputval);\n\t}\n#endif\n}\nvoid rtw_hal_set_input_gpio(_adapter *padapter, u8 index)\n{\n#if defined(CONFIG_RTL8192F)\n\trtw_hal_set_hwreg(padapter, HW_VAR_WOW_INPUT_GPIO, (u8 *)(&index));\n#else\n\tif (index <= 7) {\n\t\t/* config GPIO mode */\n\t\trtw_write8(padapter, REG_GPIO_PIN_CTRL + 3,\n\t\t\trtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index));\n\n\t\t/* config GPIO Sel */\n\t\t/* 0: input */\n\t\t/* 1: output */\n\t\trtw_write8(padapter, REG_GPIO_PIN_CTRL + 2,\n\t\t\trtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) & ~BIT(index));\n\n\t} else if (index <= 15) {\n\t\t/* 88C Series: */\n\t\t/* index: 11~8 transform to 3~0 */\n\t\t/* 8723 Series: */\n\t\t/* index: 12~8 transform to 4~0 */\n\n\t\tindex -= 8;\n\n\t\t/* config GPIO mode */\n\t\trtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3,\n\t\t\trtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index));\n\n\t\t/* config GPIO Sel */\n\t\t/* 0: input */\n\t\t/* 1: output */\n\t\trtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2,\n\t\t\trtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) & ~BIT(index));\n\t} else\n\t\tRTW_INFO(\"%s: invalid GPIO%d\\n\", __func__, index);\n#endif\n}\n\n#endif\n\nvoid rtw_hal_set_FwAoacRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)\n{\n\tstruct\thal_ops *pHalFunc = &padapter->hal_func;\n\tstruct\tpwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tstruct\tmlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tu8\tres = 0, count = 0, ret = 0;\n#ifdef CONFIG_WOWLAN\n\tu8 u1H2CAoacRsvdPageParm[H2C_AOAC_RSVDPAGE_LOC_LEN] = {0};\n\n\tRTW_INFO(\"%s: RWC: %d ArpRsp: %d NbrAdv: %d LocNDPInfo: %d\\n\",\n\t\t __func__, rsvdpageloc->LocRemoteCtrlInfo,\n\t\t rsvdpageloc->LocArpRsp, rsvdpageloc->LocNbrAdv,\n\t\t rsvdpageloc->LocNDPInfo);\n\tRTW_INFO(\"%s:GtkRsp: %d GtkInfo: %d ProbeReq: %d NetworkList: %d\\n\",\n\t\t __func__, rsvdpageloc->LocGTKRsp, rsvdpageloc->LocGTKInfo,\n\t\t rsvdpageloc->LocProbeReq, rsvdpageloc->LocNetList);\n\n\tif (check_fwstate(pmlmepriv, _FW_LINKED)) {\n\t\tSET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocRemoteCtrlInfo);\n\t\tSET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocArpRsp);\n\t\tSET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(u1H2CAoacRsvdPageParm,\n\t\t\t\t\t\t\trsvdpageloc->LocNbrAdv);\n\t\tSET_H2CCMD_AOAC_RSVDPAGE_LOC_NDP_INFO(u1H2CAoacRsvdPageParm,\n\t\t\t\t\t\t      rsvdpageloc->LocNDPInfo);\n#ifdef CONFIG_GTK_OL\n\t\tSET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKRsp);\n\t\tSET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKInfo);\n\t\tSET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKEXTMEM);\n#endif /* CONFIG_GTK_OL */\n\t\tret = rtw_hal_fill_h2c_cmd(padapter,\n\t\t\t\t\t   H2C_AOAC_RSVD_PAGE,\n\t\t\t\t\t   H2C_AOAC_RSVDPAGE_LOC_LEN,\n\t\t\t\t\t   u1H2CAoacRsvdPageParm);\n\n\t\tRTW_INFO(\"AOAC Report=%d\\n\", rsvdpageloc->LocAOACReport);\n\t\t_rtw_memset(&u1H2CAoacRsvdPageParm, 0, sizeof(u1H2CAoacRsvdPageParm));\n\t\tSET_H2CCMD_AOAC_RSVDPAGE_LOC_AOAC_REPORT(u1H2CAoacRsvdPageParm,\n\t\t\t\t\t rsvdpageloc->LocAOACReport);\n\t\tret = rtw_hal_fill_h2c_cmd(padapter,\n\t\t\t\t   H2C_AOAC_RSVDPAGE3,\n\t\t\t\t   H2C_AOAC_RSVDPAGE_LOC_LEN,\n\t\t\t\t   u1H2CAoacRsvdPageParm);\n\t\tpwrpriv->wowlan_aoac_rpt_loc = rsvdpageloc->LocAOACReport;\n\t}\n#ifdef CONFIG_PNO_SUPPORT\n\telse {\n\n\t\tif (!pwrpriv->wowlan_in_resume) {\n\t\t\tRTW_INFO(\"NLO_INFO=%d\\n\", rsvdpageloc->LocPNOInfo);\n\t\t\t_rtw_memset(&u1H2CAoacRsvdPageParm, 0,\n\t\t\t\t    sizeof(u1H2CAoacRsvdPageParm));\n\t\t\tSET_H2CCMD_AOAC_RSVDPAGE_LOC_NLO_INFO(u1H2CAoacRsvdPageParm,\n\t\t\t\t\t\t      rsvdpageloc->LocPNOInfo);\n\t\t\tret = rtw_hal_fill_h2c_cmd(padapter,\n\t\t\t\t\t\t   H2C_AOAC_RSVDPAGE3,\n\t\t\t\t\t\t   H2C_AOAC_RSVDPAGE_LOC_LEN,\n\t\t\t\t\t\t   u1H2CAoacRsvdPageParm);\n\t\t}\n\t}\n#endif /* CONFIG_PNO_SUPPORT */\n#endif /* CONFIG_WOWLAN */\n}\n\n#ifdef DBG_FW_DEBUG_MSG_PKT\nvoid rtw_hal_set_fw_dbg_msg_pkt_rsvd_page_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)\n{\n\tstruct\thal_ops *pHalFunc = &padapter->hal_func;\n\tu8\tu1H2C_fw_dbg_msg_pkt_parm[H2C_FW_DBG_MSG_PKT_LEN] = {0};\n\tu8\tret = 0;\n\n\n\tRTW_INFO(\"RsvdPageLoc: loc_fw_dbg_msg_pkt =%d\\n\", rsvdpageloc->loc_fw_dbg_msg_pkt);\n\n\tSET_H2CCMD_FW_DBG_MSG_PKT_EN(u1H2C_fw_dbg_msg_pkt_parm, 1);\n\tSET_H2CCMD_RSVDPAGE_LOC_FW_DBG_MSG_PKT(u1H2C_fw_dbg_msg_pkt_parm, rsvdpageloc->loc_fw_dbg_msg_pkt);\n\tret = rtw_hal_fill_h2c_cmd(padapter,\n\t\t\t\t   H2C_FW_DBG_MSG_PKT,\n\t\t\t\t   H2C_FW_DBG_MSG_PKT_LEN,\n\t\t\t\t   u1H2C_fw_dbg_msg_pkt_parm);\n\n}\n#endif /*DBG_FW_DEBUG_MSG_PKT*/\n\n/*#define DBG_GET_RSVD_PAGE*/\nint rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset,\n\tu32 page_num, u8 *buffer, u32 buffer_size)\n{\n\tu32 addr = 0, size = 0, count = 0;\n\tu32 page_size = 0, data_low = 0, data_high = 0;\n\tu16 txbndy = 0, offset = 0;\n\tu8 i = 0;\n\tbool rst = _FALSE;\n\n#ifdef DBG_LA_MODE\n\tstruct registry_priv *registry_par = &adapter->registrypriv;\n\n\tif(registry_par->la_mode_en == 1) {\n\t\tRTW_INFO(\"%s LA debug mode can't dump rsvd pg \\n\", __func__);\n\t\treturn rst;\n\t}\n#endif\n\trtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);\n\n\taddr = page_offset * page_size;\n\tsize = page_num * page_size;\n\n\tif (buffer_size < size) {\n\t\tRTW_ERR(\"%s buffer_size(%d) < get page total size(%d)\\n\",\n\t\t\t__func__, buffer_size, size);\n\t\treturn rst;\n\t}\n#ifdef RTW_HALMAC\n\tif (rtw_halmac_dump_fifo(adapter_to_dvobj(adapter), 2, addr, size, buffer) < 0)\n\t\trst = _FALSE;\n\telse\n\t\trst = _TRUE;\n#else\n\ttxbndy = rtw_read8(adapter, REG_TDECTRL + 1);\n\n\toffset = (txbndy + page_offset) * page_size / 8;\n\tcount = (buffer_size / 8) + 1;\n\n\trtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, 0x69);\n\n\tfor (i = 0 ; i < count ; i++) {\n\t\trtw_write32(adapter, REG_PKTBUF_DBG_CTRL, offset + i);\n\t\tdata_low = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);\n\t\tdata_high = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);\n\t\t_rtw_memcpy(buffer + (i * 8),\n\t\t\t&data_low, sizeof(data_low));\n\t\t_rtw_memcpy(buffer + ((i * 8) + 4),\n\t\t\t&data_high, sizeof(data_high));\n\t}\n\trtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, 0x0);\n\trst = _TRUE;\n#endif /*RTW_HALMAC*/\n\n#ifdef DBG_GET_RSVD_PAGE\n\tRTW_INFO(\"%s [page_offset:%d , page_num:%d][start_addr:0x%04x , size:%d]\\n\",\n\t\t __func__, page_offset, page_num, addr, size);\n\tRTW_INFO_DUMP(\"\\n\", buffer, size);\n\tRTW_INFO(\" ==================================================\\n\");\n#endif\n\treturn rst;\n}\n\nvoid rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num)\n{\n\tu32 page_size = 0;\n\tu8 *buffer = NULL;\n\tu32 buf_size = 0;\n\n\tif (page_num == 0)\n\t\treturn;\n\n\tRTW_PRINT_SEL(sel, \"======= RSVD PAGE DUMP =======\\n\");\n\tRTW_PRINT_SEL(sel, \"page_offset:%d, page_num:%d\\n\", page_offset, page_num);\n\n\trtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);\n\tif (page_size) {\n\t\tbuf_size = page_size * page_num;\n\t\tbuffer = rtw_zvmalloc(buf_size);\n\n\t\tif (buffer) {\n\t\t\trtw_hal_get_rsvd_page(adapter, page_offset, page_num, buffer, buf_size);\n\t\t\tRTW_DUMP_SEL(sel, buffer, buf_size);\n\t\t\trtw_vmfree(buffer, buf_size);\n\t\t} else\n\t\t\tRTW_PRINT_SEL(sel, \"ERROR - rsvd_buf mem allocate failed\\n\");\n\t} else\n\t\t\tRTW_PRINT_SEL(sel, \"ERROR - Tx page size is zero ??\\n\");\n\n\tRTW_PRINT_SEL(sel, \"==========================\\n\");\n}\n\n#ifdef CONFIG_SUPPORT_FIFO_DUMP\nvoid rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 fifo_size)\n{\n\tu8 *buffer = NULL;\n\tu32 buff_size = 0;\n\tstatic const char * const fifo_sel_str[] = {\n\t\t\"TX\", \"RX\", \"RSVD_PAGE\", \"REPORT\", \"LLT\", \"RXBUF_FW\"\n\t};\n\n\tif (fifo_sel > 5) {\n\t\tRTW_ERR(\"fifo_sel:%d invalid\\n\", fifo_sel);\n\t\treturn;\n\t}\n\n\tRTW_PRINT_SEL(sel, \"========= FIFO DUMP =========\\n\");\n\tRTW_PRINT_SEL(sel, \"%s FIFO DUMP [start_addr:0x%04x , size:%d]\\n\", fifo_sel_str[fifo_sel], fifo_addr, fifo_size);\n\n\tif (fifo_size) {\n\t\tbuff_size = RND4(fifo_size);\n\t\tbuffer = rtw_zvmalloc(buff_size);\n\t\tif (buffer == NULL)\n\t\t\tbuff_size = 0;\n\t}\n\n\trtw_halmac_dump_fifo(adapter_to_dvobj(adapter), fifo_sel, fifo_addr, buff_size, buffer);\n\n\tif (buffer) {\n\t\tRTW_DUMP_SEL(sel, buffer, fifo_size);\n\t\trtw_vmfree(buffer, buff_size);\n\t}\n\n\tRTW_PRINT_SEL(sel, \"==========================\\n\");\n}\n#endif\n\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\nstatic void rtw_hal_force_enable_rxdma(_adapter *adapter)\n{\n\tRTW_INFO(\"%s: Set 0x690=0x00\\n\", __func__);\n\trtw_write8(adapter, REG_WOW_CTRL,\n\t\t   (rtw_read8(adapter, REG_WOW_CTRL) & 0xf0));\n\tRTW_PRINT(\"%s: Release RXDMA\\n\", __func__);\n\trtw_write32(adapter, REG_RXPKT_NUM,\n\t\t    (rtw_read32(adapter, REG_RXPKT_NUM) & (~RW_RELEASE_EN)));\n}\n#if defined(CONFIG_RTL8188E)\nstatic void rtw_hal_disable_tx_report(_adapter *adapter)\n{\n\trtw_write8(adapter, REG_TX_RPT_CTRL,\n\t\t   ((rtw_read8(adapter, REG_TX_RPT_CTRL) & ~BIT(1))) & ~BIT(5));\n\tRTW_INFO(\"disable TXRPT:0x%02x\\n\", rtw_read8(adapter, REG_TX_RPT_CTRL));\n}\n\nstatic void rtw_hal_enable_tx_report(_adapter *adapter)\n{\n\trtw_write8(adapter, REG_TX_RPT_CTRL,\n\t\t   ((rtw_read8(adapter, REG_TX_RPT_CTRL) | BIT(1))) | BIT(5));\n\tRTW_INFO(\"enable TX_RPT:0x%02x\\n\", rtw_read8(adapter, REG_TX_RPT_CTRL));\n}\n#endif\nstatic void rtw_hal_release_rx_dma(_adapter *adapter)\n{\n\tu32 val32 = 0;\n\n\tval32 = rtw_read32(adapter, REG_RXPKT_NUM);\n\n\trtw_write32(adapter, REG_RXPKT_NUM, (val32 & (~RW_RELEASE_EN)));\n\n\tRTW_INFO(\"%s, [0x%04x]: 0x%08x\\n\",\n\t\t __func__, REG_RXPKT_NUM, (u32)(val32 & (~RW_RELEASE_EN)));\n}\n\nstatic u8 rtw_hal_pause_rx_dma(_adapter *adapter)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tu8 ret = 0;\n\ts8 trycnt = 100;\n\tu32 tmp = 0;\n\tint res = 0;\n\t/* RX DMA stop */\n\tRTW_PRINT(\"Pause DMA\\n\");\n\trtw_write32(adapter, REG_RXPKT_NUM,\n\t\t    (rtw_read32(adapter, REG_RXPKT_NUM) | RW_RELEASE_EN));\n\tdo {\n\t\tif ((rtw_read32(adapter, REG_RXPKT_NUM) & RXDMA_IDLE)) {\n#ifdef CONFIG_USB_HCI\n\t\t\t/* stop interface before leave */\n\t\t\tif (_TRUE == hal->usb_intf_start) {\n\t\t\t\trtw_intf_stop(adapter);\n\t\t\t\tRTW_ENABLE_FUNC(adapter, DF_RX_BIT);\n\t\t\t\tRTW_ENABLE_FUNC(adapter, DF_TX_BIT);\n\t\t\t}\n#endif /* CONFIG_USB_HCI */\n\n\t\t\tRTW_PRINT(\"RX_DMA_IDLE is true\\n\");\n\t\t\tret = _SUCCESS;\n\t\t\tbreak;\n\t\t}\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t\telse {\n\t\t\tres = RecvOnePkt(adapter);\n\t\t\tRTW_PRINT(\"RecvOnePkt Result: %d\\n\", res);\n\t\t}\n#endif /* CONFIG_SDIO_HCI || CONFIG_GSPI_HCI */\n\n#ifdef CONFIG_USB_HCI\n\t\telse {\n\t\t\t/* to avoid interface start repeatedly  */\n\t\t\tif (_FALSE == hal->usb_intf_start)\n\t\t\t\trtw_intf_start(adapter);\n\t\t}\n#endif /* CONFIG_USB_HCI */\n\t} while (trycnt--);\n\n\tif (trycnt < 0) {\n\t\ttmp = rtw_read16(adapter, REG_RXPKT_NUM + 2);\n\n\t\tRTW_PRINT(\"Stop RX DMA failed......\\n\");\n#ifdef CONFIG_RTL8822C\n\t\tRTW_PRINT(\"%s, RXPKT_NUM: 0x%04x\\n\",\n\t\t\t  __func__, rtw_read16(adapter, 0x02B0));\n#else\n\t\tRTW_PRINT(\"%s, RXPKT_NUM: 0x%02x\\n\",\n\t\t\t  __func__, ((tmp & 0xFF00) >> 8));\n#endif\n\t\tif (tmp & BIT(3))\n\t\t\tRTW_PRINT(\"%s, RX DMA has req\\n\",\n\t\t\t\t  __func__);\n\t\telse\n\t\t\tRTW_PRINT(\"%s, RX DMA no req\\n\",\n\t\t\t\t  __func__);\n\t\tret = _FAIL;\n\t}\n\n\treturn ret;\n}\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n#ifndef RTW_HALMAC\nstatic u8 rtw_hal_enable_cpwm2(_adapter *adapter)\n{\n\tu8 ret = 0;\n\tint res = 0;\n\tu32 tmp = 0;\n#ifdef CONFIG_GPIO_WAKEUP\n\treturn _SUCCESS;\n#else\n\tRTW_PRINT(\"%s\\n\", __func__);\n\n\tres = sdio_local_read(adapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);\n\tif (!res)\n\t\tRTW_INFO(\"read SDIO_REG_HIMR: 0x%08x\\n\", tmp);\n\telse\n\t\tRTW_INFO(\"sdio_local_read fail\\n\");\n\n\ttmp = SDIO_HIMR_CPWM2_MSK;\n\n\tres = sdio_local_write(adapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);\n\n\tif (!res) {\n\t\tres = sdio_local_read(adapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);\n\t\tRTW_INFO(\"read again SDIO_REG_HIMR: 0x%08x\\n\", tmp);\n\t\tret = _SUCCESS;\n\t} else {\n\t\tRTW_INFO(\"sdio_local_write fail\\n\");\n\t\tret = _FAIL;\n\t}\n\treturn ret;\n#endif /* CONFIG_CPIO_WAKEUP */\n}\n#endif\n#endif /* CONFIG_SDIO_HCI, CONFIG_GSPI_HCI */\n#endif /* CONFIG_WOWLAN || CONFIG_AP_WOWLAN */\n\n#ifdef CONFIG_WOWLAN\n/*\n * rtw_hal_check_wow_ctrl\n * chk_type: _TRUE means to check enable, if 0x690 & bit1 (for 8051), WOW enable successful.\n *\t\t\t\t\t\t\t\t\tIf 0x1C7 == 0 (for 3081), WOW enable successful.\n *\t\t     _FALSE means to check disable, if 0x690 & bit1 (for 8051), WOW disable fail.\n *\t\t\t\t\t\t\t\t\tIf 0x120 & bit16 || 0x284 & bit18 (for 3081), WOW disable fail.\n */\nstatic u8 rtw_hal_check_wow_ctrl(_adapter *adapter, u8 chk_type)\n{\n\tu32 fe1_imr = 0xFF, rxpkt_num = 0xFF;\n\tu8 mstatus = 0;\n\tu8 reason = 0xFF;\n\tu8 trycnt = 25;\n\tu8 res = _FALSE;\n\n\tif (IS_HARDWARE_TYPE_JAGUAR2(adapter) || IS_HARDWARE_TYPE_JAGUAR3(adapter)) {\n\t\tif (chk_type) {\n\t\t\treason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);\n\t\t\tRTW_INFO(\"%s reason:0x%02x\\n\", __func__, reason);\n\n\t\t\twhile (reason && trycnt > 1) {\n\t\t\t\treason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);\n\t\t\t\tRTW_PRINT(\"Loop index: %d :0x%02x\\n\",\n\t\t\t\t\t  trycnt, reason);\n\t\t\t\ttrycnt--;\n\t\t\t\trtw_msleep_os(20);\n\t\t\t}\n\t\t\tif (!reason)\n\t\t\t\tres = _TRUE;\n\t\t\telse\n\t\t\t\tres = _FALSE;\n\t\t} else {\n\t\t\t/* Wait FW to cleare 0x120 bit16, 0x284 bit18 to 0 */\n\t\t\tfe1_imr = rtw_read32(adapter, REG_FE1IMR); /* RxDone IMR for 3081 */\n\t\t\trxpkt_num = rtw_read32(adapter, REG_RXPKT_NUM); /* Release RXDMA */\n\t\t\tRTW_PRINT(\"%s REG_FE1IMR (reg120): 0x%x, REG_RXPKT_NUM(reg284): 0x%x\\n\", __func__, fe1_imr, rxpkt_num);\n\n\t\t\twhile (((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN)) && trycnt > 1) {\n\t\t\t\trtw_msleep_os(20);\n\t\t\t\tfe1_imr = rtw_read32(adapter, REG_FE1IMR);\n\t\t\t\trxpkt_num = rtw_read32(adapter, REG_RXPKT_NUM);\n\t\t\t\tRTW_PRINT(\"Loop index: %d :0x%x, 0x%x\\n\",\n\t\t\t\t\t  trycnt, fe1_imr, rxpkt_num);\n\t\t\t\ttrycnt--;\n\t\t\t}\n\n\t\t\tif ((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN))\n\t\t\t\tres = _FALSE;\n\t\t\telse\n\t\t\t\tres = _TRUE;\n\t\t}\n\t} else {\n\t\tmstatus = rtw_read8(adapter, REG_WOW_CTRL);\n\t\tRTW_INFO(\"%s mstatus:0x%02x\\n\", __func__, mstatus);\n\n\n\t\tif (chk_type) {\n\t\t\twhile (!(mstatus & BIT1) && trycnt > 1) {\n\t\t\t\tmstatus = rtw_read8(adapter, REG_WOW_CTRL);\n\t\t\t\tRTW_PRINT(\"Loop index: %d :0x%02x\\n\",\n\t\t\t\t\t  trycnt, mstatus);\n\t\t\t\ttrycnt--;\n\t\t\t\trtw_msleep_os(20);\n\t\t\t}\n\t\t\tif (mstatus & BIT1)\n\t\t\t\tres = _TRUE;\n\t\t\telse\n\t\t\t\tres = _FALSE;\n\t\t} else {\n\t\t\twhile (mstatus & BIT1 && trycnt > 1) {\n\t\t\t\tmstatus = rtw_read8(adapter, REG_WOW_CTRL);\n\t\t\t\tRTW_PRINT(\"Loop index: %d :0x%02x\\n\",\n\t\t\t\t\t  trycnt, mstatus);\n\t\t\t\ttrycnt--;\n\t\t\t\trtw_msleep_os(20);\n\t\t\t}\n\n\t\t\tif (mstatus & BIT1)\n\t\t\t\tres = _FALSE;\n\t\t\telse\n\t\t\t\tres = _TRUE;\n\t\t}\n\t}\n\n\tRTW_PRINT(\"%s check_type: %d res: %d trycnt: %d\\n\",\n\t\t  __func__, chk_type, res, (25 - trycnt));\n\treturn res;\n}\n\n#ifdef CONFIG_PNO_SUPPORT\nstatic u8 rtw_hal_check_pno_enabled(_adapter *adapter)\n{\n\tstruct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);\n\tu8 res = 0, count = 0;\n\tu8 ret = _FALSE;\n\n\tif (ppwrpriv->wowlan_pno_enable && ppwrpriv->wowlan_in_resume == _FALSE) {\n\t\tres = rtw_read8(adapter, REG_PNO_STATUS);\n\t\twhile (!(res & BIT(7)) && count < 25) {\n\t\t\tRTW_INFO(\"[%d] cmd: 0x81 REG_PNO_STATUS: 0x%02x\\n\",\n\t\t\t\t count, res);\n\t\t\tres = rtw_read8(adapter, REG_PNO_STATUS);\n\t\t\tcount++;\n\t\t\trtw_msleep_os(2);\n\t\t}\n\t\tif (res & BIT(7))\n\t\t\tret = _TRUE;\n\t\telse\n\t\t\tret = _FALSE;\n\t\tRTW_INFO(\"cmd: 0x81 REG_PNO_STATUS: ret(%d)\\n\", ret);\n\t}\n\treturn ret;\n}\n#endif\n\nstatic void rtw_hal_backup_rate(_adapter *adapter)\n{\n\tRTW_INFO(\"%s\\n\", __func__);\n\t/* backup data rate to register 0x8b for wowlan FW */\n\trtw_write8(adapter, 0x8d, 1);\n\trtw_write8(adapter, 0x8c, 0);\n\trtw_write8(adapter, 0x8f, 0x40);\n\trtw_write8(adapter, 0x8b, rtw_read8(adapter, 0x2f0));\n}\n\n#ifdef CONFIG_GTK_OL\nstatic void rtw_hal_fw_sync_cam_id(_adapter *adapter)\n{\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tint cam_id, index = 0;\n\tu8 *addr = NULL;\n\n\tif (!MLME_IS_STA(adapter))\n\t\treturn;\n\n\taddr = get_bssid(pmlmepriv);\n\n\tif (addr == NULL) {\n\t\tRTW_INFO(\"%s: get bssid MAC addr fail!!\\n\", __func__);\n\t\treturn;\n\t}\n\n\trtw_clean_dk_section(adapter);\n\n\tdo {\n\t\tcam_id = rtw_camid_search(adapter, addr, index, 1);\n\n\t\tif (cam_id == -1)\n\t\t\tRTW_INFO(\"%s: cam_id: %d, key_id:%d\\n\", __func__, cam_id, index);\n\t\telse\n\t\t\trtw_sec_cam_swap(adapter, cam_id, index);\n\n\t\tindex++;\n\t} while (index < 4);\n\n\trtw_write8(adapter, REG_SECCFG, 0xcc);\n}\n\nstatic void rtw_hal_update_gtk_offload_info(_adapter *adapter)\n{\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);\n\tstruct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tstruct security_priv *psecuritypriv = &adapter->securitypriv;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\t_irqL irqL;\n\tu8 get_key[16];\n\tu8 gtk_id = 0, offset = 0, i = 0, sz = 0, aoac_rpt_ver = 0, has_rekey = _FALSE;\n\tu64 replay_count = 0, tmp_iv_hdr = 0, pkt_pn = 0;\n\n\tif (!MLME_IS_STA(adapter))\n\t\treturn;\n\n\t_rtw_memset(get_key, 0, sizeof(get_key));\n\t_rtw_memcpy(&replay_count,\n\t\tpaoac_rpt->replay_counter_eapol_key, 8);\n\n\t/*read gtk key index*/\n\tgtk_id = paoac_rpt->key_index;\n\taoac_rpt_ver = paoac_rpt->version_info;\n\n\tif (aoac_rpt_ver == 0) {\n\t\t/* initial verison */\n\t\tif (gtk_id == 5)\n\t\t\thas_rekey = _FALSE;\n\t\telse\n\t\t\thas_rekey = _TRUE;\n\t} else if (aoac_rpt_ver >= 1) {\n\t\t/* Add krack patch */\n\t\tif (gtk_id == 5)\n\t\t\tRTW_WARN(\"%s FW check iv fail\\n\", __func__);\n\n\t\tif (aoac_rpt_ver == 1)\n\t\t\tRTW_WARN(\"%s aoac report version should be update to v2\\n\", __func__);\n\n\t\t/* Fix key id mismatch */\n\t\tif (aoac_rpt_ver == 2)\n\t\t\thas_rekey = paoac_rpt->rekey_ok == 1 ? _TRUE : _FALSE;\n\t}\n\n\tif (has_rekey == _FALSE) {\n\t\tRTW_INFO(\"%s no rekey event happened.\\n\", __func__);\n\t} else if (has_rekey == _TRUE) {\n\t\tRTW_INFO(\"%s update security key.\\n\", __func__);\n\t\t/*read key from sec-cam,for DK ,keyindex is equal to cam-id*/\n\t\trtw_sec_read_cam_ent(adapter, gtk_id,\n\t\t\t\t     NULL, NULL, get_key);\n\t\trtw_clean_hw_dk_cam(adapter);\n\n\t\tif (_rtw_camid_is_gk(adapter, gtk_id)) {\n\t\t\t_enter_critical_bh(&cam_ctl->lock, &irqL);\n\t\t\t_rtw_memcpy(&dvobj->cam_cache[gtk_id].key,\n\t\t\t\t    get_key, 16);\n\t\t\t_exit_critical_bh(&cam_ctl->lock, &irqL);\n\t\t} else {\n\t\t\tstruct setkey_parm parm_gtk;\n\n\t\t\tparm_gtk.algorithm = paoac_rpt->security_type;\n\t\t\tparm_gtk.keyid = gtk_id;\n\t\t\t_rtw_memcpy(parm_gtk.key, get_key, 16);\n\t\t\tsetkey_hdl(adapter, (u8 *)&parm_gtk);\n\t\t}\n\n\t\t/*update key into related sw variable and sec-cam cache*/\n\t\tpsecuritypriv->dot118021XGrpKeyid = gtk_id;\n\t\t_rtw_memcpy(&psecuritypriv->dot118021XGrpKey[gtk_id],\n\t\t\t\tget_key, 16);\n\t\t/* update SW TKIP TX/RX MIC value */\n\t\tif (psecuritypriv->dot118021XGrpPrivacy == _TKIP_) {\n\t\t\toffset = RTW_KEK_LEN + RTW_TKIP_MIC_LEN;\n\t\t\t_rtw_memcpy(\n\t\t\t\t&psecuritypriv->dot118021XGrptxmickey[gtk_id],\n\t\t\t\t&(paoac_rpt->group_key[offset]),\n\t\t\t\tRTW_TKIP_MIC_LEN);\n\n\t\t\toffset = RTW_KEK_LEN;\n\t\t\t_rtw_memcpy(\n\t\t\t\t&psecuritypriv->dot118021XGrprxmickey[gtk_id],\n\t\t\t\t&(paoac_rpt->group_key[offset]),\n\t\t\t\tRTW_TKIP_MIC_LEN);\n\t\t}\n\t\tRTW_PRINT(\"GTK (%d) \"KEY_FMT\"\\n\", gtk_id,\n\t\t\tKEY_ARG(psecuritypriv->dot118021XGrpKey[gtk_id].skey));\n\t}\n\n\t/* Update broadcast RX IV */\n\tif (psecuritypriv->dot118021XGrpPrivacy == _AES_) {\n\t\tsz = sizeof(psecuritypriv->iv_seq[0]);\n\t\tfor (i = 0 ; i < 4 ; i++) {\n\t\t\t_rtw_memcpy(&tmp_iv_hdr, paoac_rpt->rxgtk_iv[i], sz);\n\t\t\ttmp_iv_hdr = le64_to_cpu(tmp_iv_hdr);\n\t\t\tpkt_pn = CCMPH_2_PN(tmp_iv_hdr);\n\t\t\t_rtw_memcpy(psecuritypriv->iv_seq[i], &pkt_pn, sz);\n\t\t}\n\t}\n\n\trtw_clean_dk_section(adapter);\n\n\trtw_write8(adapter, REG_SECCFG, 0x0c);\n\n\t#ifdef CONFIG_GTK_OL_DBG\n\t/* if (gtk_keyindex != 5) */\n\tdump_sec_cam(RTW_DBGDUMP, adapter);\n\tdump_sec_cam_cache(RTW_DBGDUMP, adapter);\n\t#endif\n}\n#endif /*CONFIG_GTK_OL*/\n\nstatic void rtw_dump_aoac_rpt(_adapter *adapter)\n{\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);\n\tstruct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;\n\tint i = 0;\n\n\tRTW_INFO_DUMP(\"[AOAC-RPT] IV -\", paoac_rpt->iv, 8);\n\tRTW_INFO_DUMP(\"[AOAC-RPT] Replay counter of EAPOL key - \",\n\t\tpaoac_rpt->replay_counter_eapol_key, 8);\n\tRTW_INFO_DUMP(\"[AOAC-RPT] Group key - \", paoac_rpt->group_key, 32);\n\tRTW_INFO(\"[AOAC-RPT] Key Index - %d\\n\", paoac_rpt->key_index);\n\tRTW_INFO(\"[AOAC-RPT] Security Type - %d\\n\", paoac_rpt->security_type);\n\tRTW_INFO(\"[AOAC-RPT] wow_pattern_idx - %d\\n\",\n\t\t paoac_rpt->wow_pattern_idx);\n\tRTW_INFO(\"[AOAC-RPT] version_info - %d\\n\", paoac_rpt->version_info);\n\tRTW_INFO(\"[AOAC-RPT] rekey_ok - %d\\n\", paoac_rpt->rekey_ok);\n\tRTW_INFO_DUMP(\"[AOAC-RPT] RX PTK IV-\", paoac_rpt->rxptk_iv, 8);\n\tRTW_INFO_DUMP(\"[AOAC-RPT] RX GTK[0] IV-\", paoac_rpt->rxgtk_iv[0], 8);\n\tRTW_INFO_DUMP(\"[AOAC-RPT] RX GTK[1] IV-\", paoac_rpt->rxgtk_iv[1], 8);\n\tRTW_INFO_DUMP(\"[AOAC-RPT] RX GTK[2] IV-\", paoac_rpt->rxgtk_iv[2], 8);\n\tRTW_INFO_DUMP(\"[AOAC-RPT] RX GTK[3] IV-\", paoac_rpt->rxgtk_iv[3], 8);\n}\n\nstatic void rtw_hal_get_aoac_rpt(_adapter *adapter)\n{\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);\n\tstruct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;\n\tu32 page_offset = 0, page_number = 0;\n\tu32 page_size = 0, buf_size = 0;\n\tu8 *buffer = NULL;\n\tu8 i = 0, tmp = 0;\n\tint ret = -1;\n\n\t/* read aoac report from rsvd page */\n\tpage_offset = pwrctl->wowlan_aoac_rpt_loc;\n\tpage_number = 1;\n\n\trtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);\n\tbuf_size = page_size * page_number;\n\n\tbuffer = rtw_zvmalloc(buf_size);\n\n\tif (buffer == NULL) {\n\t\tRTW_ERR(\"%s buffer allocate failed size(%d)\\n\",\n\t\t\t__func__, buf_size);\n\t\treturn;\n\t}\n\n\tRTW_INFO(\"Get AOAC Report from rsvd page_offset:%d\\n\", page_offset);\n\n\tret = rtw_hal_get_rsvd_page(adapter, page_offset,\n\t\tpage_number, buffer, buf_size);\n\n\tif (ret == _FALSE) {\n\t\tRTW_ERR(\"%s get aoac report failed\\n\", __func__);\n\t\trtw_warn_on(1);\n\t\tgoto _exit;\n\t}\n\n\t_rtw_memset(paoac_rpt, 0, sizeof(struct aoac_report));\n\t_rtw_memcpy(paoac_rpt, buffer, sizeof(struct aoac_report));\n\n\tfor (i = 0 ; i < 4 ; i++) {\n\t\ttmp = paoac_rpt->replay_counter_eapol_key[i];\n\t\tpaoac_rpt->replay_counter_eapol_key[i] =\n\t\t\tpaoac_rpt->replay_counter_eapol_key[7 - i];\n\t\tpaoac_rpt->replay_counter_eapol_key[7 - i] = tmp;\n\t}\n\n\trtw_dump_aoac_rpt(adapter);\n\n_exit:\n\tif (buffer)\n\t\trtw_vmfree(buffer, buf_size);\n}\n\nstatic void rtw_hal_update_tx_iv(_adapter *adapter)\n{\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);\n\tstruct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;\n\tstruct sta_info\t*psta;\n\tstruct mlme_ext_priv\t*pmlmeext = &(adapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct security_priv\t*psecpriv = &adapter->securitypriv;\n\n\tu16 val16 = 0;\n\tu32 val32 = 0;\n\tu64 txiv = 0;\n\tu8 *pval = NULL;\n\n\tpsta = rtw_get_stainfo(&adapter->stapriv,\n\t\t\t       get_my_bssid(&pmlmeinfo->network));\n\n\t/* Update TX iv data. */\n\tpval = (u8 *)&paoac_rpt->iv;\n\n\tif (psecpriv->dot11PrivacyAlgrthm == _TKIP_) {\n\t\tval16 = ((u16)(paoac_rpt->iv[2]) << 0) +\n\t\t\t((u16)(paoac_rpt->iv[0]) << 8);\n\t\tval32 = ((u32)(paoac_rpt->iv[4]) << 0) +\n\t\t\t((u32)(paoac_rpt->iv[5]) << 8) +\n\t\t\t((u32)(paoac_rpt->iv[6]) << 16) +\n\t\t\t((u32)(paoac_rpt->iv[7]) << 24);\n\t} else if (psecpriv->dot11PrivacyAlgrthm == _AES_) {\n\t\tval16 = ((u16)(paoac_rpt->iv[0]) << 0) +\n\t\t\t((u16)(paoac_rpt->iv[1]) << 8);\n\t\tval32 = ((u32)(paoac_rpt->iv[4]) << 0) +\n\t\t\t((u32)(paoac_rpt->iv[5]) << 8) +\n\t\t\t((u32)(paoac_rpt->iv[6]) << 16) +\n\t\t\t((u32)(paoac_rpt->iv[7]) << 24);\n\t}\n\n\tif (psta) {\n\t\ttxiv = val16 + ((u64)val32 << 16);\n\t\tif (txiv != 0)\n\t\t\tpsta->dot11txpn.val = txiv;\n\t}\n}\n\nstatic void rtw_hal_update_sw_security_info(_adapter *adapter)\n{\n\tstruct security_priv *psecpriv = &adapter->securitypriv;\n\tu8 sz = sizeof (psecpriv->iv_seq);\n\n\trtw_hal_update_tx_iv(adapter);\n#ifdef CONFIG_GTK_OL\n\tif (psecpriv->binstallKCK_KEK == _TRUE &&\n\t    psecpriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK)\n\t\trtw_hal_update_gtk_offload_info(adapter);\n#else\n\t_rtw_memset(psecpriv->iv_seq, 0, sz);\n#endif\n}\n\nstatic u8 rtw_hal_set_keep_alive_cmd(_adapter *adapter, u8 enable, u8 pkt_type)\n{\n\tstruct hal_ops *pHalFunc = &adapter->hal_func;\n\n\tu8 u1H2CKeepAliveParm[H2C_KEEP_ALIVE_CTRL_LEN] = {0};\n\tu8 adopt = 1, check_period = 5;\n\tu8 ret = _FAIL;\n\tu8 hw_port = rtw_hal_get_port(adapter);\n\n\tSET_H2CCMD_KEEPALIVE_PARM_ENABLE(u1H2CKeepAliveParm, enable);\n\tSET_H2CCMD_KEEPALIVE_PARM_ADOPT(u1H2CKeepAliveParm, adopt);\n\tSET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(u1H2CKeepAliveParm, pkt_type);\n\tSET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(u1H2CKeepAliveParm, check_period);\n#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\tSET_H2CCMD_KEEPALIVE_PARM_PORT_NUM(u1H2CKeepAliveParm, hw_port);\n\tRTW_INFO(\"%s(): enable = %d, port = %d\\n\", __func__, enable, hw_port);\n#else\n\tRTW_INFO(\"%s(): enable = %d\\n\", __func__, enable);\n#endif\n\tret = rtw_hal_fill_h2c_cmd(adapter,\n\t\t\t\t   H2C_KEEP_ALIVE,\n\t\t\t\t   H2C_KEEP_ALIVE_CTRL_LEN,\n\t\t\t\t   u1H2CKeepAliveParm);\n\n\treturn ret;\n}\n\nstatic u8 rtw_hal_set_disconnect_decision_cmd(_adapter *adapter, u8 enable)\n{\n\tstruct hal_ops *pHalFunc = &adapter->hal_func;\n\tu8 u1H2CDisconDecisionParm[H2C_DISCON_DECISION_LEN] = {0};\n\tu8 adopt = 1, check_period = 30, trypkt_num = 5;\n\tu8 ret = _FAIL;\n\tu8 hw_port = rtw_hal_get_port(adapter);\n\n\tSET_H2CCMD_DISCONDECISION_PARM_ENABLE(u1H2CDisconDecisionParm, enable);\n\tSET_H2CCMD_DISCONDECISION_PARM_ADOPT(u1H2CDisconDecisionParm, adopt);\n\t/* SET_H2CCMD_DISCONDECISION_PARM_DISCONNECT_EN(u1H2CDisconDecisionParm, adopt); */\n\tSET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(u1H2CDisconDecisionParm, check_period);\n\tSET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(u1H2CDisconDecisionParm, trypkt_num);\n#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\tSET_H2CCMD_DISCONDECISION_PORT_NUM(u1H2CDisconDecisionParm, hw_port);\n\tRTW_INFO(\"%s(): enable = %d, port = %d\\n\", __func__, enable, hw_port);\n#else\n\tRTW_INFO(\"%s(): enable = %d\\n\", __func__, enable);\n#endif\n\n\tret = rtw_hal_fill_h2c_cmd(adapter,\n\t\t\t\t   H2C_DISCON_DECISION,\n\t\t\t\t   H2C_DISCON_DECISION_LEN,\n\t\t\t\t   u1H2CDisconDecisionParm);\n\treturn ret;\n}\n\nstatic u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_unit)\n{\n\tstruct registry_priv  *registry_par = &adapter->registrypriv;\n\tstruct security_priv *psecpriv = &adapter->securitypriv;\n\tstruct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);\n\tstruct hal_ops *pHalFunc = &adapter->hal_func;\n\tstruct mlme_priv\t*pmlmepriv = &(adapter->mlmepriv);\n\n\tu8 u1H2CWoWlanCtrlParm[H2C_WOWLAN_LEN] = {0};\n\tu8 discont_wake = 0, gpionum = 0, gpio_dur = 0, no_wake = 0;\n\tu8 hw_unicast = 0, gpio_pulse_cnt = 0, gpio_pulse_en = 0;\n\tu8 sdio_wakeup_enable = 1;\n\tu8 gpio_high_active = 0;\n\tu8 magic_pkt = 0;\n\tu8 gpio_unit = 0; /*0: 64ns, 1: 8ms*/\n\tu8 ret = _FAIL;\n#ifdef CONFIG_DIS_UPHY\n\tu8 dis_uphy = 0, dis_uphy_unit = 0, dis_uphy_time = 0;\n#endif /* CONFIG_DIS_UPHY */\n\n#ifdef CONFIG_GPIO_WAKEUP\n\tgpio_high_active = ppwrpriv->is_high_active;\n\tgpionum = WAKEUP_GPIO_IDX;\n\tsdio_wakeup_enable = 0;\n#endif /* CONFIG_GPIO_WAKEUP */\n\t\n\tif(registry_par->suspend_type == FW_IPS_DISABLE_BBRF &&\n\t!check_fwstate(pmlmepriv, _FW_LINKED))\n\t\tno_wake = 1;\n\t\t\n\tif (!ppwrpriv->wowlan_pno_enable &&\n\t\tregistry_par->wakeup_event & BIT(0) && !no_wake)\n\t\tmagic_pkt = enable;\n\n\tif ((registry_par->wakeup_event & BIT(1)) &&\n\t\t(psecpriv->dot11PrivacyAlgrthm == _WEP40_ ||\n\t\tpsecpriv->dot11PrivacyAlgrthm == _WEP104_) && !no_wake)\n\t\t\thw_unicast = 1;\n\n\tif (registry_par->wakeup_event & BIT(2) && !no_wake)\n\t\tdiscont_wake = enable;\n\n\tRTW_INFO(\"%s(): enable=%d change_unit=%d\\n\", __func__,\n\t\t enable, change_unit);\n\n\t/* time = (gpio_dur/2) * gpio_unit, default:256 ms */\n\tif (enable && change_unit) {\n\t\tgpio_dur = 0x40;\n\t\tgpio_unit = 1;\n\t\tgpio_pulse_en = 1;\n\t}\n\n#ifdef CONFIG_PLATFORM_ARM_RK3188\n\tif (enable) {\n\t\tgpio_pulse_en = 1;\n\t\tgpio_pulse_cnt = 0x04;\n\t}\n#endif\n\n\tSET_H2CCMD_WOWLAN_FUNC_ENABLE(u1H2CWoWlanCtrlParm, enable);\n\tif(!no_wake)\n\t\tSET_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(u1H2CWoWlanCtrlParm, enable);\n\tSET_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(u1H2CWoWlanCtrlParm, magic_pkt);\n\tSET_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(u1H2CWoWlanCtrlParm, hw_unicast);\n\tSET_H2CCMD_WOWLAN_ALL_PKT_DROP(u1H2CWoWlanCtrlParm, 0);\n\tSET_H2CCMD_WOWLAN_GPIO_ACTIVE(u1H2CWoWlanCtrlParm, gpio_high_active);\n\n#ifdef CONFIG_GTK_OL\n\tif (psecpriv->binstallKCK_KEK == _TRUE &&\n\t    psecpriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK)\n\t\tSET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 0);\n\telse\n\t\tSET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 1);\n#else\n\tSET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, enable);\n#endif\n\tSET_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(u1H2CWoWlanCtrlParm, discont_wake);\n\tSET_H2CCMD_WOWLAN_GPIONUM(u1H2CWoWlanCtrlParm, gpionum);\n\tSET_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(u1H2CWoWlanCtrlParm, sdio_wakeup_enable);\n\n\tSET_H2CCMD_WOWLAN_GPIO_DURATION(u1H2CWoWlanCtrlParm, gpio_dur);\n\tSET_H2CCMD_WOWLAN_CHANGE_UNIT(u1H2CWoWlanCtrlParm, gpio_unit);\n\n\tSET_H2CCMD_WOWLAN_GPIO_PULSE_EN(u1H2CWoWlanCtrlParm, gpio_pulse_en);\n\tSET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(u1H2CWoWlanCtrlParm, gpio_pulse_cnt);\n\n#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE\n\tif (enable)\n\t\tSET_H2CCMD_WOWLAN_GPIO_INPUT_EN(u1H2CWoWlanCtrlParm, 1);\n#endif\n\n#ifdef CONFIG_DIS_UPHY\n\tif (enable) {\n\t\tdis_uphy = 1;\n\t\t/* time unit: 0 -> ms, 1 -> 256 ms*/\n\t\tdis_uphy_unit = 1;\n\t\tdis_uphy_time = 0x4;\n\t}\n\n\tSET_H2CCMD_WOWLAN_DISABLE_UPHY(u1H2CWoWlanCtrlParm, dis_uphy);\n\tSET_H2CCMD_WOWLAN_UNIT_FOR_UPHY_DISABLE(u1H2CWoWlanCtrlParm, dis_uphy_unit);\n\tSET_H2CCMD_WOWLAN_TIME_FOR_UPHY_DISABLE(u1H2CWoWlanCtrlParm, dis_uphy_time);\n\tif (ppwrpriv->hst2dev_high_active == 1)\n\t\tSET_H2CCMD_WOWLAN_RISE_HST2DEV(u1H2CWoWlanCtrlParm, 1);\n#ifdef CONFIG_RTW_ONE_PIN_GPIO\n\tSET_H2CCMD_WOWLAN_GPIO_INPUT_EN(u1H2CWoWlanCtrlParm, 1);\n\tSET_H2CCMD_WOWLAN_DEV2HST_EN(u1H2CWoWlanCtrlParm, 1);\n\tSET_H2CCMD_WOWLAN_HST2DEV_EN(u1H2CWoWlanCtrlParm, 0);\n#else\n\tSET_H2CCMD_WOWLAN_HST2DEV_EN(u1H2CWoWlanCtrlParm, 1);\n#endif /* CONFIG_RTW_ONE_PIN_GPIO */\n#endif /* CONFIG_DIS_UPHY */\n\n\n\tret = rtw_hal_fill_h2c_cmd(adapter,\n\t\t\t\t   H2C_WOWLAN,\n\t\t\t\t   H2C_WOWLAN_LEN,\n\t\t\t\t   u1H2CWoWlanCtrlParm);\n\treturn ret;\n}\n\nstatic u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable)\n{\n\tstruct hal_ops *pHalFunc = &adapter->hal_func;\n\tstruct security_priv *psecuritypriv = &(adapter->securitypriv);\n\tstruct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);\n\tstruct registry_priv *pregistrypriv = &adapter->registrypriv;\n\tu8 u1H2CRemoteWakeCtrlParm[H2C_REMOTE_WAKE_CTRL_LEN] = {0};\n\tu8 ret = _FAIL, count = 0, no_wake = 0;\n\tstruct mlme_priv\t*pmlmepriv = &(adapter->mlmepriv);\n\n\tRTW_INFO(\"%s(): enable=%d\\n\", __func__, enable);\n\n\tif(pregistrypriv->suspend_type == FW_IPS_DISABLE_BBRF &&\n\t!check_fwstate(pmlmepriv, _FW_LINKED))\n\t\tno_wake = 1;\n\tif(no_wake) {\n\t\tSET_H2CCMD_REMOTE_WAKECTRL_ENABLE(\n\t\t\tu1H2CRemoteWakeCtrlParm, enable);\n\t} else {\n\t\tif (!ppwrpriv->wowlan_pno_enable) {\n\t\t\tSET_H2CCMD_REMOTE_WAKECTRL_ENABLE(\n\t\t\t\tu1H2CRemoteWakeCtrlParm, enable);\n\t\t\tSET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(\n\t\t\t\tu1H2CRemoteWakeCtrlParm, 1);\n\t#ifdef CONFIG_GTK_OL\n\t\t\tif (psecuritypriv->binstallKCK_KEK == _TRUE &&\n\t\t\t    psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) {\n\t\t\t\tSET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(\n\t\t\t\t\tu1H2CRemoteWakeCtrlParm, 1);\n\t\t\t} else {\n\t\t\t\tRTW_INFO(\"no kck kek\\n\");\n\t\t\t\tSET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(\n\t\t\t\t\tu1H2CRemoteWakeCtrlParm, 0);\n\t\t\t}\n\t#endif /* CONFIG_GTK_OL */\n\t\n\t#ifdef CONFIG_IPV6\n\t\t\tif (ppwrpriv->wowlan_ns_offload_en == _TRUE) {\n\t\t\t\tRTW_INFO(\"enable NS offload\\n\");\n\t\t\t\tSET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(\n\t\t\t\t\tu1H2CRemoteWakeCtrlParm, enable);\n\t\t\t}\n\t\n\t\t\t/*\n\t\t\t * filter NetBios name service pkt to avoid being waked-up\n\t\t\t * by this kind of unicast pkt this exceptional modification\n\t\t\t * is used for match competitor's behavior\n\t\t\t */\n\t\n\t\t\tSET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN(\n\t\t\t\tu1H2CRemoteWakeCtrlParm, enable);\n\t#endif /*CONFIG_IPV6*/\n\t\n\t#ifdef CONFIG_RTL8192F\n\t\t\tif (IS_HARDWARE_TYPE_8192F(adapter)){\n\t\t\t\tSET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(\n\t\t\t\t\tu1H2CRemoteWakeCtrlParm, enable);\n\t\t\t}\n\t#endif /* CONFIG_RTL8192F */\n\t\n\t\t\tif ((psecuritypriv->dot11PrivacyAlgrthm == _AES_) ||\n\t\t\t\t(psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) ||\n\t\t\t\t(psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_)) {\n\t\t\t\tSET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(\n\t\t\t\t\tu1H2CRemoteWakeCtrlParm, 0);\n\t\t\t} else {\n\t\t\t\tSET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(\n\t\t\t\t\tu1H2CRemoteWakeCtrlParm, 1);\n\t\t\t}\n\t\n\t\t\tif (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_ &&\n\t\t\t    psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) {\n\t\t\t\tSET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(\n\t\t\t\t\t\tu1H2CRemoteWakeCtrlParm, enable);\n\t\n\t\t\t\tif (IS_HARDWARE_TYPE_8188E(adapter) ||\n\t\t\t\t    IS_HARDWARE_TYPE_8812(adapter)) {\n\t\t\t\t\tSET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(\n\t\t\t\t\t\tu1H2CRemoteWakeCtrlParm, 0);\n\t\t\t\t\tSET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(\n\t\t\t\t\t\tu1H2CRemoteWakeCtrlParm, 1);\n\t\t\t\t}\n\t\t\t}\n\t\n\t\t\tSET_H2CCMD_REMOTE_WAKE_CTRL_FW_PARSING_UNTIL_WAKEUP(\n\t\t\t\tu1H2CRemoteWakeCtrlParm, 1);\n\t\t}\n\t#ifdef CONFIG_PNO_SUPPORT\n\t\telse {\n\t\t\tSET_H2CCMD_REMOTE_WAKECTRL_ENABLE(\n\t\t\t\tu1H2CRemoteWakeCtrlParm, enable);\n\t\t\tSET_H2CCMD_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(\n\t\t\t\tu1H2CRemoteWakeCtrlParm, enable);\n\t\t}\n\t#endif\n\t\n\t#ifdef CONFIG_P2P_WOWLAN\n\t\tif (_TRUE == ppwrpriv->wowlan_p2p_mode) {\n\t\t\tRTW_INFO(\"P2P OFFLOAD ENABLE\\n\");\n\t\t\tSET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(u1H2CRemoteWakeCtrlParm, 1);\n\t\t} else {\n\t\t\tRTW_INFO(\"P2P OFFLOAD DISABLE\\n\");\n\t\t\tSET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(u1H2CRemoteWakeCtrlParm, 0);\n\t\t}\n\t#endif /* CONFIG_P2P_WOWLAN */\n\t}\n\n\n\tret = rtw_hal_fill_h2c_cmd(adapter,\n\t\t\t\t   H2C_REMOTE_WAKE_CTRL,\n\t\t\t\t   H2C_REMOTE_WAKE_CTRL_LEN,\n\t\t\t\t   u1H2CRemoteWakeCtrlParm);\n\treturn ret;\n}\n\nstatic u8 rtw_hal_set_global_info_cmd(_adapter *adapter, u8 group_alg, u8 pairwise_alg)\n{\n\tstruct hal_ops *pHalFunc = &adapter->hal_func;\n\tu8 ret = _FAIL;\n\tu8 u1H2CAOACGlobalInfoParm[H2C_AOAC_GLOBAL_INFO_LEN] = {0};\n\n\tRTW_INFO(\"%s(): group_alg=%d pairwise_alg=%d\\n\",\n\t\t __func__, group_alg, pairwise_alg);\n\tSET_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(u1H2CAOACGlobalInfoParm,\n\t\t\tpairwise_alg);\n\tSET_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(u1H2CAOACGlobalInfoParm,\n\t\t\tgroup_alg);\n\n\tret = rtw_hal_fill_h2c_cmd(adapter,\n\t\t\t\t   H2C_AOAC_GLOBAL_INFO,\n\t\t\t\t   H2C_AOAC_GLOBAL_INFO_LEN,\n\t\t\t\t   u1H2CAOACGlobalInfoParm);\n\n\treturn ret;\n}\n\n#ifdef CONFIG_PNO_SUPPORT\nstatic u8 rtw_hal_set_scan_offload_info_cmd(_adapter *adapter,\n\t\tPRSVDPAGE_LOC rsvdpageloc, u8 enable)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\tstruct hal_ops *pHalFunc = &adapter->hal_func;\n\n\tu8 u1H2CScanOffloadInfoParm[H2C_SCAN_OFFLOAD_CTRL_LEN] = {0};\n\tu8 res = 0, count = 0, ret = _FAIL;\n\n\tRTW_INFO(\"%s: loc_probe_packet:%d, loc_scan_info: %d loc_ssid_info:%d\\n\",\n\t\t __func__, rsvdpageloc->LocProbePacket,\n\t\t rsvdpageloc->LocScanInfo, rsvdpageloc->LocSSIDInfo);\n\n\tSET_H2CCMD_AOAC_NLO_FUN_EN(u1H2CScanOffloadInfoParm, enable);\n\tSET_H2CCMD_AOAC_NLO_IPS_EN(u1H2CScanOffloadInfoParm, enable);\n\tSET_H2CCMD_AOAC_RSVDPAGE_LOC_SCAN_INFO(u1H2CScanOffloadInfoParm,\n\t\t\t\t\t       rsvdpageloc->LocScanInfo);\n\tSET_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_PACKET(u1H2CScanOffloadInfoParm,\n\t\t\trsvdpageloc->LocProbePacket);\n\t/*\n\t\tSET_H2CCMD_AOAC_RSVDPAGE_LOC_SSID_INFO(u1H2CScanOffloadInfoParm,\n\t\t\t\trsvdpageloc->LocSSIDInfo);\n\t*/\n\tret = rtw_hal_fill_h2c_cmd(adapter,\n\t\t\t\t   H2C_D0_SCAN_OFFLOAD_INFO,\n\t\t\t\t   H2C_SCAN_OFFLOAD_CTRL_LEN,\n\t\t\t\t   u1H2CScanOffloadInfoParm);\n\treturn ret;\n}\n#endif /* CONFIG_PNO_SUPPORT */\n\nvoid rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable)\n{\n\tstruct security_priv *psecpriv = &padapter->securitypriv;\n\tstruct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(padapter);\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct registry_priv *pregistry = &padapter->registrypriv;\n\tstruct sta_info *psta = NULL;\n\tu16 media_status_rpt;\n\tu8\tpkt_type = 0, no_wake = 0;\n\tu8 ret = _SUCCESS;\n\t\n\tif(pregistry->suspend_type == FW_IPS_DISABLE_BBRF &&\n\t!check_fwstate(pmlmepriv, _FW_LINKED))\n\t\tno_wake = 1;\n\n\tRTW_PRINT(\"+%s()+: enable=%d\\n\", __func__, enable);\n\n\trtw_hal_set_wowlan_ctrl_cmd(padapter, enable, _FALSE);\n\n\tif (enable) {\n\t\tif(!no_wake)\n\t\t\trtw_hal_set_global_info_cmd(padapter,\n\t\t\t\t\t    psecpriv->dot118021XGrpPrivacy,\n\t\t\t\t\t    psecpriv->dot11PrivacyAlgrthm);\n\n\t\tif (!(ppwrpriv->wowlan_pno_enable)) {\n\t\t\tif (pregistry->wakeup_event & BIT(2) && !no_wake)\n\t\t\t\trtw_hal_set_disconnect_decision_cmd(padapter,\n\t\t\t\t\t\t\t\t    enable);\n#ifdef CONFIG_ARP_KEEP_ALIVE\n\t\t\tif ((psecpriv->dot11PrivacyAlgrthm == _WEP40_) ||\n\t\t\t    (psecpriv->dot11PrivacyAlgrthm == _WEP104_))\n\t\t\t\tpkt_type = 0;\n\t\t\telse\n\t\t\t\tpkt_type = 1;\n#else\n\t\t\tpkt_type = 0;\n#endif /* CONFIG_ARP_KEEP_ALIVE */\n\t\t\tif(!no_wake)\n\t\t\t\trtw_hal_set_keep_alive_cmd(padapter, enable, pkt_type);\n\t\t}\n\t\trtw_hal_set_remote_wake_ctrl_cmd(padapter, enable);\n#ifdef CONFIG_PNO_SUPPORT\n\t\trtw_hal_check_pno_enabled(padapter);\n#endif /* CONFIG_PNO_SUPPORT */\n\t} else {\n#if 0\n\t\t{\n\t\t\tu32 PageSize = 0;\n\t\t\trtw_hal_get_def_var(padapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&PageSize);\n\t\t\tdump_TX_FIFO(padapter, 4, PageSize);\n\t\t}\n#endif\n\n\t\trtw_hal_set_remote_wake_ctrl_cmd(padapter, enable);\n\t}\n\tRTW_PRINT(\"-%s()-\\n\", __func__);\n}\n#endif /* CONFIG_WOWLAN */\n\n#ifdef CONFIG_AP_WOWLAN\nstatic u8 rtw_hal_set_ap_wowlan_ctrl_cmd(_adapter *adapter, u8 enable)\n{\n\tstruct security_priv *psecpriv = &adapter->securitypriv;\n\tstruct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);\n\tstruct hal_ops *pHalFunc = &adapter->hal_func;\n\n\tu8 u1H2CAPWoWlanCtrlParm[H2C_AP_WOW_GPIO_CTRL_LEN] = {0};\n\tu8 gpionum = 0, gpio_dur = 0;\n\tu8 gpio_pulse = enable;\n\tu8 sdio_wakeup_enable = 1;\n\tu8 gpio_high_active = 0;\n\tu8 ret = _FAIL;\n\n#ifdef CONFIG_GPIO_WAKEUP\n\tgpio_high_active = ppwrpriv->is_high_active;\n\tgpionum = WAKEUP_GPIO_IDX;\n\tsdio_wakeup_enable = 0;\n#endif /*CONFIG_GPIO_WAKEUP*/\n\n\tRTW_INFO(\"%s(): enable=%d\\n\", __func__, enable);\n\n\tSET_H2CCMD_AP_WOW_GPIO_CTRL_INDEX(u1H2CAPWoWlanCtrlParm,\n\t\t\t\t\t  gpionum);\n\tSET_H2CCMD_AP_WOW_GPIO_CTRL_PLUS(u1H2CAPWoWlanCtrlParm,\n\t\t\t\t\t gpio_pulse);\n\tSET_H2CCMD_AP_WOW_GPIO_CTRL_HIGH_ACTIVE(u1H2CAPWoWlanCtrlParm,\n\t\t\t\t\t\tgpio_high_active);\n\tSET_H2CCMD_AP_WOW_GPIO_CTRL_EN(u1H2CAPWoWlanCtrlParm,\n\t\t\t\t       enable);\n\tSET_H2CCMD_AP_WOW_GPIO_CTRL_DURATION(u1H2CAPWoWlanCtrlParm,\n\t\t\t\t\t     gpio_dur);\n\n\tret = rtw_hal_fill_h2c_cmd(adapter,\n\t\t\t\t   H2C_AP_WOW_GPIO_CTRL,\n\t\t\t\t   H2C_AP_WOW_GPIO_CTRL_LEN,\n\t\t\t\t   u1H2CAPWoWlanCtrlParm);\n\n\treturn ret;\n}\n\nstatic u8 rtw_hal_set_ap_offload_ctrl_cmd(_adapter *adapter, u8 enable)\n{\n\tstruct hal_ops *pHalFunc = &adapter->hal_func;\n\tu8 u1H2CAPOffloadCtrlParm[H2C_WOWLAN_LEN] = {0};\n\tu8 ret = _FAIL;\n\n\tRTW_INFO(\"%s(): bFuncEn=%d\\n\", __func__, enable);\n\n\tSET_H2CCMD_AP_WOWLAN_EN(u1H2CAPOffloadCtrlParm, enable);\n\n\tret = rtw_hal_fill_h2c_cmd(adapter,\n\t\t\t\t   H2C_AP_OFFLOAD,\n\t\t\t\t   H2C_AP_OFFLOAD_LEN,\n\t\t\t\t   u1H2CAPOffloadCtrlParm);\n\n\treturn ret;\n}\n\nstatic u8 rtw_hal_set_ap_ps_cmd(_adapter *adapter, u8 enable)\n{\n\tstruct hal_ops *pHalFunc = &adapter->hal_func;\n\tu8 ap_ps_parm[H2C_AP_PS_LEN] = {0};\n\tu8 ret = _FAIL;\n\n\tRTW_INFO(\"%s(): enable=%d\\n\" , __func__ , enable);\n\n\tSET_H2CCMD_AP_WOW_PS_EN(ap_ps_parm, enable);\n#ifndef CONFIG_USB_HCI\n\tSET_H2CCMD_AP_WOW_PS_32K_EN(ap_ps_parm, enable);\n#endif /*CONFIG_USB_HCI*/\n\tSET_H2CCMD_AP_WOW_PS_RF(ap_ps_parm, enable);\n\n\tif (enable)\n\t\tSET_H2CCMD_AP_WOW_PS_DURATION(ap_ps_parm, 0x32);\n\telse\n\t\tSET_H2CCMD_AP_WOW_PS_DURATION(ap_ps_parm, 0x0);\n\n\tret = rtw_hal_fill_h2c_cmd(adapter, H2C_SAP_PS_,\n\t\t\t\t   H2C_AP_PS_LEN, ap_ps_parm);\n\n\treturn ret;\n}\n\nstatic void rtw_hal_set_ap_rsvdpage_loc_cmd(PADAPTER padapter,\n\t\tPRSVDPAGE_LOC rsvdpageloc)\n{\n\tstruct hal_ops *pHalFunc = &padapter->hal_func;\n\tu8 rsvdparm[H2C_AOAC_RSVDPAGE_LOC_LEN] = {0};\n\tu8 ret = _FAIL, header = 0;\n\n\tif (pHalFunc->fill_h2c_cmd == NULL) {\n\t\tRTW_INFO(\"%s: Please hook fill_h2c_cmd first!\\n\", __func__);\n\t\treturn;\n\t}\n\n\theader = rtw_read8(padapter, REG_BCNQ_BDNY);\n\n\tRTW_INFO(\"%s: beacon: %d, probeRsp: %d, header:0x%02x\\n\", __func__,\n\t\t rsvdpageloc->LocApOffloadBCN,\n\t\t rsvdpageloc->LocProbeRsp,\n\t\t header);\n\n\tSET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_BCN(rsvdparm,\n\t\t\t\t      rsvdpageloc->LocApOffloadBCN + header);\n\n\tret = rtw_hal_fill_h2c_cmd(padapter, H2C_BCN_RSVDPAGE,\n\t\t\t\t   H2C_BCN_RSVDPAGE_LEN, rsvdparm);\n\n\tif (ret == _FAIL)\n\t\tRTW_INFO(\"%s: H2C_BCN_RSVDPAGE cmd fail\\n\", __func__);\n\n\trtw_msleep_os(10);\n\n\t_rtw_memset(&rsvdparm, 0, sizeof(rsvdparm));\n\n\tSET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_ProbeRsp(rsvdparm,\n\t\t\trsvdpageloc->LocProbeRsp + header);\n\n\tret = rtw_hal_fill_h2c_cmd(padapter, H2C_PROBERSP_RSVDPAGE,\n\t\t\t\t   H2C_PROBERSP_RSVDPAGE_LEN, rsvdparm);\n\n\tif (ret == _FAIL)\n\t\tRTW_INFO(\"%s: H2C_PROBERSP_RSVDPAGE cmd fail\\n\", __func__);\n\n\trtw_msleep_os(10);\n}\n\nstatic void rtw_hal_set_fw_ap_wow_related_cmd(_adapter *padapter, u8 enable)\n{\n\trtw_hal_set_ap_offload_ctrl_cmd(padapter, enable);\n\trtw_hal_set_ap_wowlan_ctrl_cmd(padapter, enable);\n\trtw_hal_set_ap_ps_cmd(padapter, enable);\n}\n\nstatic void rtw_hal_ap_wow_enable(_adapter *padapter)\n{\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct hal_ops *pHalFunc = &padapter->hal_func;\n\tstruct sta_info *psta = NULL;\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);\n#ifdef DBG_CHECK_FW_PS_STATE\n\tstruct dvobj_priv *psdpriv = padapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &psdpriv->drv_dbg;\n#endif /*DBG_CHECK_FW_PS_STATE*/\n\tint res;\n\tu16 media_status_rpt;\n\n\tRTW_INFO(\"%s, WOWLAN_AP_ENABLE\\n\", __func__);\n#ifdef DBG_CHECK_FW_PS_STATE\n\tif (rtw_fw_ps_state(padapter) == _FAIL) {\n\t\tpdbgpriv->dbg_enwow_dload_fw_fail_cnt++;\n\t\tRTW_PRINT(\"wowlan enable no leave 32k\\n\");\n\t}\n#endif /*DBG_CHECK_FW_PS_STATE*/\n\n\t/* 1. Download WOWLAN FW*/\n\trtw_hal_fw_dl(padapter, _TRUE);\n\n\tmedia_status_rpt = RT_MEDIA_CONNECT;\n\trtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT,\n\t\t\t  (u8 *)&media_status_rpt);\n\n\tissue_beacon(padapter, 0);\n\n\trtw_msleep_os(2);\n\t#if defined(CONFIG_RTL8188E)\n\tif (IS_HARDWARE_TYPE_8188E(padapter))\n\t\trtw_hal_disable_tx_report(padapter);\n\t#endif\n\t/* RX DMA stop */\n\tres = rtw_hal_pause_rx_dma(padapter);\n\tif (res == _FAIL)\n\t\tRTW_PRINT(\"[WARNING] pause RX DMA fail\\n\");\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t/* Enable CPWM2 only. */\n\tres = rtw_hal_enable_cpwm2(padapter);\n\tif (res == _FAIL)\n\t\tRTW_PRINT(\"[WARNING] enable cpwm2 fail\\n\");\n#endif\n\n#ifdef CONFIG_GPIO_WAKEUP\n\trtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _TRUE);\n#endif\n\t/* 5. Set Enable WOWLAN H2C command. */\n\tRTW_PRINT(\"Set Enable AP WOWLan cmd\\n\");\n\trtw_hal_set_fw_ap_wow_related_cmd(padapter, 1);\n\n\trtw_write8(padapter, REG_MCUTST_WOWLAN, 0);\n#ifdef CONFIG_USB_HCI\n\trtw_mi_intf_stop(padapter);\n#endif\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)\n\t/* Invoid SE0 reset signal during suspending*/\n\trtw_write8(padapter, REG_RSV_CTRL, 0x20);\n\tif (IS_8188F(pHalData->version_id) == FALSE\n\t\t&& IS_8188GTV(pHalData->version_id) == FALSE)\n\t\trtw_write8(padapter, REG_RSV_CTRL, 0x60);\n#endif\n}\n\nstatic void rtw_hal_ap_wow_disable(_adapter *padapter)\n{\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);\n\tstruct hal_ops *pHalFunc = &padapter->hal_func;\n#ifdef DBG_CHECK_FW_PS_STATE\n\tstruct dvobj_priv *psdpriv = padapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &psdpriv->drv_dbg;\n#endif /*DBG_CHECK_FW_PS_STATE*/\n\tu16 media_status_rpt;\n\tu8 val8;\n\n\tRTW_INFO(\"%s, WOWLAN_AP_DISABLE\\n\", __func__);\n\t/* 1. Read wakeup reason*/\n\tpwrctl->wowlan_wake_reason = rtw_read8(padapter, REG_MCUTST_WOWLAN);\n\n\tRTW_PRINT(\"wakeup_reason: 0x%02x\\n\",\n\t\t  pwrctl->wowlan_wake_reason);\n\n\trtw_hal_set_fw_ap_wow_related_cmd(padapter, 0);\n\n\trtw_msleep_os(2);\n#ifdef DBG_CHECK_FW_PS_STATE\n\tif (rtw_fw_ps_state(padapter) == _FAIL) {\n\t\tpdbgpriv->dbg_diswow_dload_fw_fail_cnt++;\n\t\tRTW_PRINT(\"wowlan enable no leave 32k\\n\");\n\t}\n#endif /*DBG_CHECK_FW_PS_STATE*/\n\n\t#if defined(CONFIG_RTL8188E)\n\tif (IS_HARDWARE_TYPE_8188E(padapter))\n\t\trtw_hal_enable_tx_report(padapter);\n\t#endif\n\n\trtw_hal_force_enable_rxdma(padapter);\n\n\trtw_hal_fw_dl(padapter, _FALSE);\n\n#ifdef CONFIG_GPIO_WAKEUP\n#ifdef CONFIG_RTW_ONE_PIN_GPIO\n\trtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX);\n#else\n\t#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE\n\tif (pwrctl->is_high_active == 0)\n\t\trtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX);\n\telse\n\t\trtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, 0);\n\t#else\n\tval8 = (pwrctl->is_high_active == 0) ? 1 : 0;\n\tRTW_PRINT(\"Set Wake GPIO to default(%d).\\n\", val8);\n\trtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8);\n\n\trtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _FALSE);\n\t#endif/*CONFIG_WAKEUP_GPIO_INPUT_MODE*/\n#endif /* CONFIG_RTW_ONE_PIN_GPIO */\n#endif\n\tmedia_status_rpt = RT_MEDIA_CONNECT;\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT,\n\t\t\t  (u8 *)&media_status_rpt);\n\n\tissue_beacon(padapter, 0);\n}\n#endif /*CONFIG_AP_WOWLAN*/\n\n#ifdef CONFIG_P2P_WOWLAN\nstatic int update_hidden_ssid(u8 *ies, u32 ies_len, u8 hidden_ssid_mode)\n{\n\tu8 *ssid_ie;\n\tsint ssid_len_ori;\n\tint len_diff = 0;\n\n\tssid_ie = rtw_get_ie(ies,  WLAN_EID_SSID, &ssid_len_ori, ies_len);\n\n\t/* RTW_INFO(\"%s hidden_ssid_mode:%u, ssid_ie:%p, ssid_len_ori:%d\\n\", __FUNCTION__, hidden_ssid_mode, ssid_ie, ssid_len_ori); */\n\n\tif (ssid_ie && ssid_len_ori > 0) {\n\t\tswitch (hidden_ssid_mode) {\n\t\tcase 1: {\n\t\t\tu8 *next_ie = ssid_ie + 2 + ssid_len_ori;\n\t\t\tu32 remain_len = 0;\n\n\t\t\tremain_len = ies_len - (next_ie - ies);\n\n\t\t\tssid_ie[1] = 0;\n\t\t\t_rtw_memcpy(ssid_ie + 2, next_ie, remain_len);\n\t\t\tlen_diff -= ssid_len_ori;\n\n\t\t\tbreak;\n\t\t}\n\t\tcase 2:\n\t\t\t_rtw_memset(&ssid_ie[2], 0, ssid_len_ori);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn len_diff;\n}\n\nstatic void rtw_hal_construct_P2PBeacon(_adapter *padapter, u8 *pframe, u32 *pLength)\n{\n\t/* struct xmit_frame\t*pmgntframe; */\n\t/* struct pkt_attrib\t*pattrib; */\n\t/* unsigned char\t*pframe; */\n\tstruct rtw_ieee80211_hdr *pwlanhdr;\n\tunsigned short *fctrl;\n\tunsigned int\trate_len;\n\tstruct xmit_priv\t*pxmitpriv = &(padapter->xmitpriv);\n\tu32\tpktlen;\n\t/* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */\n\t/*\t_irqL irqL;\n\t *\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\t * #endif */ /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t\t*cur_network = &(pmlmeinfo->network);\n\tu8\tbc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n#endif /* CONFIG_P2P */\n\n\t/* for debug */\n\tu8 *dbgbuf = pframe;\n\tu8 dbgbufLen = 0, index = 0;\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\t/* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */\n\t/*\t_enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);\n\t * #endif */ /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);\n\t/* pmlmeext->mgnt_seq++; */\n\tset_frame_sub_type(pframe, WIFI_BEACON);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tif ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {\n\t\t/* RTW_INFO(\"ie len=%d\\n\", cur_network->IELength); */\n#ifdef CONFIG_P2P\n\t\t/* for P2P : Primary Device Type & Device Name */\n\t\tu32 wpsielen = 0, insert_len = 0;\n\t\tu8 *wpsie = NULL;\n\t\twpsie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen);\n\n\t\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && wpsie && wpsielen > 0) {\n\t\t\tuint wps_offset, remainder_ielen;\n\t\t\tu8 *premainder_ie, *pframe_wscie;\n\n\t\t\twps_offset = (uint)(wpsie - cur_network->IEs);\n\n\t\t\tpremainder_ie = wpsie + wpsielen;\n\n\t\t\tremainder_ielen = cur_network->IELength - wps_offset - wpsielen;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\t\t\tif (pwdinfo->driver_interface == DRIVER_CFG80211) {\n\t\t\t\tif (pmlmepriv->wps_beacon_ie && pmlmepriv->wps_beacon_ie_len > 0) {\n\t\t\t\t\t_rtw_memcpy(pframe, cur_network->IEs, wps_offset);\n\t\t\t\t\tpframe += wps_offset;\n\t\t\t\t\tpktlen += wps_offset;\n\n\t\t\t\t\t_rtw_memcpy(pframe, pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len);\n\t\t\t\t\tpframe += pmlmepriv->wps_beacon_ie_len;\n\t\t\t\t\tpktlen += pmlmepriv->wps_beacon_ie_len;\n\n\t\t\t\t\t/* copy remainder_ie to pframe */\n\t\t\t\t\t_rtw_memcpy(pframe, premainder_ie, remainder_ielen);\n\t\t\t\t\tpframe += remainder_ielen;\n\t\t\t\t\tpktlen += remainder_ielen;\n\t\t\t\t} else {\n\t\t\t\t\t_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);\n\t\t\t\t\tpframe += cur_network->IELength;\n\t\t\t\t\tpktlen += cur_network->IELength;\n\t\t\t\t}\n\t\t\t} else\n#endif /* CONFIG_IOCTL_CFG80211 */\n\t\t\t{\n\t\t\t\tpframe_wscie = pframe + wps_offset;\n\t\t\t\t_rtw_memcpy(pframe, cur_network->IEs, wps_offset + wpsielen);\n\t\t\t\tpframe += (wps_offset + wpsielen);\n\t\t\t\tpktlen += (wps_offset + wpsielen);\n\n\t\t\t\t/* now pframe is end of wsc ie, insert Primary Device Type & Device Name */\n\t\t\t\t/*\tPrimary Device Type */\n\t\t\t\t/*\tType: */\n\t\t\t\t*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);\n\t\t\t\tinsert_len += 2;\n\n\t\t\t\t/*\tLength: */\n\t\t\t\t*(u16 *)(pframe + insert_len) = cpu_to_be16(0x0008);\n\t\t\t\tinsert_len += 2;\n\n\t\t\t\t/*\tValue: */\n\t\t\t\t/*\tCategory ID */\n\t\t\t\t*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);\n\t\t\t\tinsert_len += 2;\n\n\t\t\t\t/*\tOUI */\n\t\t\t\t*(u32 *)(pframe + insert_len) = cpu_to_be32(WPSOUI);\n\t\t\t\tinsert_len += 4;\n\n\t\t\t\t/*\tSub Category ID */\n\t\t\t\t*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);\n\t\t\t\tinsert_len += 2;\n\n\n\t\t\t\t/*\tDevice Name */\n\t\t\t\t/*\tType: */\n\t\t\t\t*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);\n\t\t\t\tinsert_len += 2;\n\n\t\t\t\t/*\tLength: */\n\t\t\t\t*(u16 *)(pframe + insert_len) = cpu_to_be16(pwdinfo->device_name_len);\n\t\t\t\tinsert_len += 2;\n\n\t\t\t\t/*\tValue: */\n\t\t\t\t_rtw_memcpy(pframe + insert_len, pwdinfo->device_name, pwdinfo->device_name_len);\n\t\t\t\tinsert_len += pwdinfo->device_name_len;\n\n\n\t\t\t\t/* update wsc ie length */\n\t\t\t\t*(pframe_wscie + 1) = (wpsielen - 2) + insert_len;\n\n\t\t\t\t/* pframe move to end */\n\t\t\t\tpframe += insert_len;\n\t\t\t\tpktlen += insert_len;\n\n\t\t\t\t/* copy remainder_ie to pframe */\n\t\t\t\t_rtw_memcpy(pframe, premainder_ie, remainder_ielen);\n\t\t\t\tpframe += remainder_ielen;\n\t\t\t\tpktlen += remainder_ielen;\n\t\t\t}\n\t\t} else\n#endif /* CONFIG_P2P */\n\t\t{\n\t\t\tint len_diff;\n\t\t\t_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);\n\t\t\tlen_diff = update_hidden_ssid(\n\t\t\t\t\t   pframe + _BEACON_IE_OFFSET_\n\t\t\t\t   , cur_network->IELength - _BEACON_IE_OFFSET_\n\t\t\t\t\t   , pmlmeinfo->hidden_ssid_mode\n\t\t\t\t   );\n\t\t\tpframe += (cur_network->IELength + len_diff);\n\t\t\tpktlen += (cur_network->IELength + len_diff);\n\t\t}\n#if 0\n\t\t{\n\t\t\tu8 *wps_ie;\n\t\t\tuint wps_ielen;\n\t\t\tu8 sr = 0;\n\t\t\twps_ie = rtw_get_wps_ie(pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_,\n\t\t\t\tpattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_, NULL, &wps_ielen);\n\t\t\tif (wps_ie && wps_ielen > 0)\n\t\t\t\trtw_get_wps_attr_content(wps_ie,  wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);\n\t\t\tif (sr != 0)\n\t\t\t\tset_fwstate(pmlmepriv, WIFI_UNDER_WPS);\n\t\t\telse\n\t\t\t\t_clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS);\n\t\t}\n#endif\n#ifdef CONFIG_P2P\n\t\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\t\tu32 len;\n#ifdef CONFIG_IOCTL_CFG80211\n\t\t\tif (pwdinfo->driver_interface == DRIVER_CFG80211) {\n\t\t\t\tlen = pmlmepriv->p2p_beacon_ie_len;\n\t\t\t\tif (pmlmepriv->p2p_beacon_ie && len > 0)\n\t\t\t\t\t_rtw_memcpy(pframe, pmlmepriv->p2p_beacon_ie, len);\n\t\t\t} else\n#endif /* CONFIG_IOCTL_CFG80211 */\n\t\t\t{\n\t\t\t\tlen = build_beacon_p2p_ie(pwdinfo, pframe);\n\t\t\t}\n\n\t\t\tpframe += len;\n\t\t\tpktlen += len;\n\n\t\t\t#ifdef CONFIG_WFD\n\t\t\tlen = rtw_append_beacon_wfd_ie(padapter, pframe);\n\t\t\tpframe += len;\n\t\t\tpktlen += len;\n\t\t\t#endif\n\n\t\t}\n#endif /* CONFIG_P2P */\n\n\t\tgoto _issue_bcn;\n\n\t}\n\n\t/* below for ad-hoc mode */\n\n\t/* timestamp will be inserted by hardware */\n\tpframe += 8;\n\tpktlen += 8;\n\n\t/* beacon interval: 2 bytes */\n\n\t_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);\n\n\tpframe += 2;\n\tpktlen += 2;\n\n\t/* capability info: 2 bytes */\n\n\t_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);\n\n\tpframe += 2;\n\tpktlen += 2;\n\n\t/* SSID */\n\tpframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen);\n\n\t/* supported rates... */\n\trate_len = rtw_get_rateset_len(cur_network->SupportedRates);\n\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen);\n\n\t/* DS parameter set */\n\tpframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen);\n\n\t/* if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) */\n\t{\n\t\tu8 erpinfo = 0;\n\t\tu32 ATIMWindow;\n\t\t/* IBSS Parameter Set... */\n\t\t/* ATIMWindow = cur->Configuration.ATIMWindow; */\n\t\tATIMWindow = 0;\n\t\tpframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen);\n\n\t\t/* ERP IE */\n\t\tpframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pktlen);\n\t}\n\n\n\t/* EXTERNDED SUPPORTED RATE */\n\tif (rate_len > 8)\n\t\tpframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen);\n\n\n\t/* todo:HT for adhoc */\n\n_issue_bcn:\n\n\t/* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */\n\t/*\tpmlmepriv->update_bcn = _FALSE;\n\t *\n\t *\t_exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);\n\t * #endif */ /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */\n\n\t*pLength = pktlen;\n#if 0\n\t/* printf dbg msg */\n\tdbgbufLen = pktlen;\n\tRTW_INFO(\"======> DBG MSG FOR CONSTRAUCT P2P BEACON\\n\");\n\n\tfor (index = 0; index < dbgbufLen; index++)\n\t\tprintk(\"%x \", *(dbgbuf + index));\n\n\tprintk(\"\\n\");\n\tRTW_INFO(\"<====== DBG MSG FOR CONSTRAUCT P2P BEACON\\n\");\n\n#endif\n}\n\nstatic void rtw_hal_construct_P2PProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength)\n{\n\t/* struct xmit_frame\t\t\t*pmgntframe; */\n\t/* struct pkt_attrib\t\t\t*pattrib; */\n\t/* unsigned char\t\t\t\t\t*pframe; */\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tunsigned char\t\t\t\t\t*mac;\n\tstruct xmit_priv\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\t/* WLAN_BSSID_EX \t\t*cur_network = &(pmlmeinfo->network); */\n\tu16\t\t\t\t\tbeacon_interval = 100;\n\tu16\t\t\t\t\tcapInfo = 0;\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\tu8\t\t\t\t\twpsie[255] = { 0x00 };\n\tu32\t\t\t\t\twpsielen = 0, p2pielen = 0;\n\tu32\t\t\t\t\tpktlen;\n#ifdef CONFIG_WFD\n\tu32\t\t\t\t\twfdielen = 0;\n#endif\n\n\t/* for debug */\n\tu8 *dbgbuf = pframe;\n\tu8 dbgbufLen = 0, index = 0;\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tmac = adapter_mac_addr(padapter);\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t/* DA filled by FW */\n\t_rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);\n\n\t/*\tUse the device address for BSSID field.\t */\n\t_rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, 0);\n\tset_frame_sub_type(fctrl, WIFI_PROBERSP);\n\n\tpktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpframe += pktlen;\n\n\n\t/* timestamp will be inserted by hardware */\n\tpframe += 8;\n\tpktlen += 8;\n\n\t/* beacon interval: 2 bytes */\n\t_rtw_memcpy(pframe, (unsigned char *) &beacon_interval, 2);\n\tpframe += 2;\n\tpktlen += 2;\n\n\t/*\tcapability info: 2 bytes */\n\t/*\tESS and IBSS bits must be 0 (defined in the 3.1.2.1.1 of WiFi Direct Spec) */\n\tcapInfo |= cap_ShortPremble;\n\tcapInfo |= cap_ShortSlot;\n\n\t_rtw_memcpy(pframe, (unsigned char *) &capInfo, 2);\n\tpframe += 2;\n\tpktlen += 2;\n\n\n\t/* SSID */\n\tpframe = rtw_set_ie(pframe, _SSID_IE_, 7, pwdinfo->p2p_wildcard_ssid, &pktlen);\n\n\t/* supported rates... */\n\t/*\tUse the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) */\n\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pktlen);\n\n\t/* DS parameter set */\n\tpframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&pwdinfo->listen_channel, &pktlen);\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (pwdinfo->driver_interface == DRIVER_CFG80211) {\n\t\tif (pmlmepriv->wps_probe_resp_ie != NULL && pmlmepriv->p2p_probe_resp_ie != NULL) {\n\t\t\t/* WPS IE */\n\t\t\t_rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len);\n\t\t\tpktlen += pmlmepriv->wps_probe_resp_ie_len;\n\t\t\tpframe += pmlmepriv->wps_probe_resp_ie_len;\n\n\t\t\t/* P2P IE */\n\t\t\t_rtw_memcpy(pframe, pmlmepriv->p2p_probe_resp_ie, pmlmepriv->p2p_probe_resp_ie_len);\n\t\t\tpktlen += pmlmepriv->p2p_probe_resp_ie_len;\n\t\t\tpframe += pmlmepriv->p2p_probe_resp_ie_len;\n\t\t}\n\t} else\n#endif /* CONFIG_IOCTL_CFG80211\t\t */\n\t{\n\n\t\t/*\tTodo: WPS IE */\n\t\t/*\tNoted by Albert 20100907 */\n\t\t/*\tAccording to the WPS specification, all the WPS attribute is presented by Big Endian. */\n\n\t\twpsielen = 0;\n\t\t/*\tWPS OUI */\n\t\t*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);\n\t\twpsielen += 4;\n\n\t\t/*\tWPS version */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\twpsie[wpsielen++] = WPS_VERSION_1;\t/*\tVersion 1.0 */\n\n\t\t/*\tWiFi Simple Config State */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SIMPLE_CONF_STATE);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\twpsie[wpsielen++] = WPS_WSC_STATE_NOT_CONFIG;\t/*\tNot Configured. */\n\n\t\t/*\tResponse Type */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_RESP_TYPE);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\twpsie[wpsielen++] = WPS_RESPONSE_TYPE_8021X;\n\n\t\t/*\tUUID-E */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_UUID_E);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0010);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\tif (pwdinfo->external_uuid == 0) {\n\t\t\t_rtw_memset(wpsie + wpsielen, 0x0, 16);\n\t\t\t_rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN);\n\t\t} else\n\t\t\t_rtw_memcpy(wpsie + wpsielen, pwdinfo->uuid, 0x10);\n\t\twpsielen += 0x10;\n\n\t\t/*\tManufacturer */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MANUFACTURER);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0007);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\t_rtw_memcpy(wpsie + wpsielen, \"Realtek\", 7);\n\t\twpsielen += 7;\n\n\t\t/*\tModel Name */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NAME);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0006);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\t_rtw_memcpy(wpsie + wpsielen, \"8192CU\", 6);\n\t\twpsielen += 6;\n\n\t\t/*\tModel Number */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NUMBER);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\twpsie[wpsielen++] = 0x31;\t\t/*\tcharacter 1 */\n\n\t\t/*\tSerial Number */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SERIAL_NUMBER);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(ETH_ALEN);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\t_rtw_memcpy(wpsie + wpsielen, \"123456\" , ETH_ALEN);\n\t\twpsielen += ETH_ALEN;\n\n\t\t/*\tPrimary Device Type */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\t/*\tCategory ID */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);\n\t\twpsielen += 2;\n\n\t\t/*\tOUI */\n\t\t*(u32 *)(wpsie + wpsielen) = cpu_to_be32(WPSOUI);\n\t\twpsielen += 4;\n\n\t\t/*\tSub Category ID */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);\n\t\twpsielen += 2;\n\n\t\t/*\tDevice Name */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->device_name_len);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\t_rtw_memcpy(wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len);\n\t\twpsielen += pwdinfo->device_name_len;\n\n\t\t/*\tConfig Method */\n\t\t/*\tType: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);\n\t\twpsielen += 2;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);\n\t\twpsielen += 2;\n\n\t\t/*\tValue: */\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->supported_wps_cm);\n\t\twpsielen += 2;\n\n\n\t\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pktlen);\n\n\n\t\tp2pielen = build_probe_resp_p2p_ie(pwdinfo, pframe);\n\t\tpframe += p2pielen;\n\t\tpktlen += p2pielen;\n\t}\n\n#ifdef CONFIG_WFD\n\twfdielen = rtw_append_probe_resp_wfd_ie(padapter, pframe);\n\tpframe += wfdielen;\n\tpktlen += wfdielen;\n#endif\n\n\t*pLength = pktlen;\n\n#if 0\n\t/* printf dbg msg */\n\tdbgbufLen = pktlen;\n\tRTW_INFO(\"======> DBG MSG FOR CONSTRAUCT P2P Probe Rsp\\n\");\n\n\tfor (index = 0; index < dbgbufLen; index++)\n\t\tprintk(\"%x \", *(dbgbuf + index));\n\n\tprintk(\"\\n\");\n\tRTW_INFO(\"<====== DBG MSG FOR CONSTRAUCT P2P Probe Rsp\\n\");\n#endif\n}\nstatic void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pLength)\n{\n\tstruct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);\n\tunsigned char category = RTW_WLAN_CATEGORY_PUBLIC;\n\tu8\t\t\taction = P2P_PUB_ACTION_ACTION;\n\tu32\t\t\tp2poui = cpu_to_be32(P2POUI);\n\tu8\t\t\toui_subtype = P2P_GO_NEGO_RESP;\n\tu8\t\t\twpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };\n\tu8\t\t\tp2pielen = 0, i;\n\tuint\t\t\twpsielen = 0;\n\tu16\t\t\twps_devicepassword_id = 0x0000;\n\tuint\t\t\twps_devicepassword_id_len = 0;\n\tu8\t\t\tchannel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh;\n\tu16\t\t\tlen_channellist_attr = 0;\n\tu32\t\t\tpktlen;\n\tu8\t\t\tdialogToken = 0;\n\n\t/* struct xmit_frame\t\t\t*pmgntframe; */\n\t/* struct pkt_attrib\t\t\t*pattrib; */\n\t/* unsigned char\t\t\t\t\t*pframe; */\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\t/* WLAN_BSSID_EX \t\t*cur_network = &(pmlmeinfo->network); */\n\n#ifdef CONFIG_WFD\n\tu32\t\t\t\t\twfdielen = 0;\n#endif\n\n\t/* for debug */\n\tu8 *dbgbuf = pframe;\n\tu8 dbgbufLen = 0, index = 0;\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t/* RA, filled by FW */\n\t_rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, 0);\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpframe += pktlen;\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pktlen));\n\n\t/* dialog token, filled by FW */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pktlen));\n\n\t_rtw_memset(wpsie, 0x00, 255);\n\twpsielen = 0;\n\n\t/*\tWPS Section */\n\twpsielen = 0;\n\t/*\tWPS OUI */\n\t*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);\n\twpsielen += 4;\n\n\t/*\tWPS version */\n\t/*\tType: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);\n\twpsielen += 2;\n\n\t/*\tLength: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);\n\twpsielen += 2;\n\n\t/*\tValue: */\n\twpsie[wpsielen++] = WPS_VERSION_1;\t/*\tVersion 1.0 */\n\n\t/*\tDevice Password ID */\n\t/*\tType: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);\n\twpsielen += 2;\n\n\t/*\tLength: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);\n\twpsielen += 2;\n\n\t/*\tValue: */\n\tif (wps_devicepassword_id == WPS_DPID_USER_SPEC)\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);\n\telse if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC);\n\telse\n\t\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC);\n\twpsielen += 2;\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pktlen);\n\n\n\t/*\tP2P IE Section. */\n\n\t/*\tP2P OUI */\n\tp2pielen = 0;\n\tp2pie[p2pielen++] = 0x50;\n\tp2pie[p2pielen++] = 0x6F;\n\tp2pie[p2pielen++] = 0x9A;\n\tp2pie[p2pielen++] = 0x09;\t/*\tWFA P2P v1.0 */\n\n\t/*\tCommented by Albert 20100908 */\n\t/*\tAccording to the P2P Specification, the group negoitation response frame should contain 9 P2P attributes */\n\t/*\t1. Status */\n\t/*\t2. P2P Capability */\n\t/*\t3. Group Owner Intent */\n\t/*\t4. Configuration Timeout */\n\t/*\t5. Operating Channel */\n\t/*\t6. Intended P2P Interface Address */\n\t/*\t7. Channel List */\n\t/*\t8. Device Info */\n\t/*\t9. Group ID\t( Only GO ) */\n\n\n\t/*\tToDo: */\n\n\t/*\tP2P Status */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_STATUS;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);\n\tp2pielen += 2;\n\n\t/*\tValue, filled by FW */\n\tp2pie[p2pielen++] = 1;\n\n\t/*\tP2P Capability */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CAPABILITY;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tDevice Capability Bitmap, 1 byte */\n\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {\n\t\t/*\tCommented by Albert 2011/03/08 */\n\t\t/*\tAccording to the P2P specification */\n\t\t/*\tif the sending device will be client, the P2P Capability should be reserved of group negotation response frame */\n\t\tp2pie[p2pielen++] = 0;\n\t} else {\n\t\t/*\tBe group owner or meet the error case */\n\t\tp2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;\n\t}\n\n\t/*\tGroup Capability Bitmap, 1 byte */\n\tif (pwdinfo->persistent_supported)\n\t\tp2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;\n\telse\n\t\tp2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;\n\n\t/*\tGroup Owner Intent */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_GO_INTENT;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\tif (pwdinfo->peer_intent & 0x01) {\n\t\t/*\tPeer's tie breaker bit is 1, our tie breaker bit should be 0 */\n\t\tp2pie[p2pielen++] = (pwdinfo->intent << 1);\n\t} else {\n\t\t/*\tPeer's tie breaker bit is 0, our tie breaker bit should be 1 */\n\t\tp2pie[p2pielen++] = ((pwdinfo->intent << 1) | BIT(0));\n\t}\n\n\n\t/*\tConfiguration Timeout */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\tp2pie[p2pielen++] = 200;\t/*\t2 seconds needed to be the P2P GO */\n\tp2pie[p2pielen++] = 200;\t/*\t2 seconds needed to be the P2P Client */\n\n\t/*\tOperating Channel */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tCountry String */\n\tp2pie[p2pielen++] = 'X';\n\tp2pie[p2pielen++] = 'X';\n\n\t/*\tThe third byte should be set to 0x04. */\n\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\tp2pie[p2pielen++] = 0x04;\n\n\t/*\tOperating Class */\n\tif (pwdinfo->operating_channel <= 14) {\n\t\t/*\tOperating Class */\n\t\tp2pie[p2pielen++] = 0x51;\n\t} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {\n\t\t/*\tOperating Class */\n\t\tp2pie[p2pielen++] = 0x73;\n\t} else {\n\t\t/*\tOperating Class */\n\t\tp2pie[p2pielen++] = 0x7c;\n\t}\n\n\t/*\tChannel Number */\n\tp2pie[p2pielen++] = pwdinfo->operating_channel;\t/*\toperating channel number */\n\n\t/*\tIntended P2P Interface Address\t */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);\n\tp2pielen += ETH_ALEN;\n\n\t/*\tChannel List */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CH_LIST;\n\n\t/* Country String(3) */\n\t/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */\n\t/* + number of channels in all classes */\n\tlen_channellist_attr = 3\n\t\t       + (1 + 1) * (u16)ch_list->reg_classes\n\t\t       + get_reg_classes_full_count(ch_list);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_buddy_check_fwstate(padapter, _FW_LINKED))\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);\n\telse\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);\n\n#else\n\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);\n\n#endif\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tCountry String */\n\tp2pie[p2pielen++] = 'X';\n\tp2pie[p2pielen++] = 'X';\n\n\t/*\tThe third byte should be set to 0x04. */\n\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\tp2pie[p2pielen++] = 0x04;\n\n\t/*\tChannel Entry List */\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_check_status(padapter, MI_LINKED)) {\n\t\tu8 union_ch = rtw_mi_get_union_chan(padapter);\n\n\t\t/*\tOperating Class */\n\t\tif (union_ch > 14) {\n\t\t\tif (union_ch >= 149)\n\t\t\t\tp2pie[p2pielen++] = 0x7c;\n\t\t\telse\n\t\t\t\tp2pie[p2pielen++] = 0x73;\n\t\t} else\n\t\t\tp2pie[p2pielen++] = 0x51;\n\n\n\t\t/*\tNumber of Channels */\n\t\t/*\tJust support 1 channel and this channel is AP's channel */\n\t\tp2pie[p2pielen++] = 1;\n\n\t\t/*\tChannel List */\n\t\tp2pie[p2pielen++] = union_ch;\n\t} else\n#endif /* CONFIG_CONCURRENT_MODE */\n\t{\n\t\tint i, j;\n\t\tfor (j = 0; j < ch_list->reg_classes; j++) {\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].reg_class;\n\n\t\t\t/*\tNumber of Channels */\n\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].channels;\n\n\t\t\t/*\tChannel List */\n\t\t\tfor (i = 0; i < ch_list->reg_class[j].channels; i++)\n\t\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].channel[i];\n\t\t}\n\t}\n\n\t/*\tDevice Info */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\t21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */\n\t/*\t+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tP2P Device Address */\n\t_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);\n\tp2pielen += ETH_ALEN;\n\n\t/*\tConfig Method */\n\t/*\tThis field should be big endian. Noted by P2P specification. */\n\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm);\n\n\tp2pielen += 2;\n\n\t/*\tPrimary Device Type */\n\t/*\tCategory ID */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);\n\tp2pielen += 2;\n\n\t/*\tOUI */\n\t*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);\n\tp2pielen += 4;\n\n\t/*\tSub Category ID */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);\n\tp2pielen += 2;\n\n\t/*\tNumber of Secondary Device Types */\n\tp2pie[p2pielen++] = 0x00;\t/*\tNo Secondary Device Type List */\n\n\t/*\tDevice Name */\n\t/*\tType: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);\n\tp2pielen += 2;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len);\n\tp2pielen += pwdinfo->device_name_len;\n\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\t/*\tGroup ID Attribute */\n\t\t/*\tType: */\n\t\tp2pie[p2pielen++] = P2P_ATTR_GROUP_ID;\n\n\t\t/*\tLength: */\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen);\n\t\tp2pielen += 2;\n\n\t\t/*\tValue: */\n\t\t/*\tp2P Device Address */\n\t\t_rtw_memcpy(p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN);\n\t\tp2pielen += ETH_ALEN;\n\n\t\t/*\tSSID */\n\t\t_rtw_memcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);\n\t\tp2pielen += pwdinfo->nego_ssidlen;\n\n\t}\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pktlen);\n\n#ifdef CONFIG_WFD\n\twfdielen = build_nego_resp_wfd_ie(pwdinfo, pframe);\n\tpframe += wfdielen;\n\tpktlen += wfdielen;\n#endif\n\n\t*pLength = pktlen;\n#if 0\n\t/* printf dbg msg */\n\tdbgbufLen = pktlen;\n\tRTW_INFO(\"======> DBG MSG FOR CONSTRAUCT Nego Rsp\\n\");\n\n\tfor (index = 0; index < dbgbufLen; index++)\n\t\tprintk(\"%x \", *(dbgbuf + index));\n\n\tprintk(\"\\n\");\n\tRTW_INFO(\"<====== DBG MSG FOR CONSTRAUCT Nego Rsp\\n\");\n#endif\n}\n\nstatic void rtw_hal_construct_P2PInviteRsp(_adapter *padapter, u8 *pframe, u32 *pLength)\n{\n\tunsigned char category = RTW_WLAN_CATEGORY_PUBLIC;\n\tu8\t\t\taction = P2P_PUB_ACTION_ACTION;\n\tu32\t\t\tp2poui = cpu_to_be32(P2POUI);\n\tu8\t\t\toui_subtype = P2P_INVIT_RESP;\n\tu8\t\t\tp2pie[255] = { 0x00 };\n\tu8\t\t\tp2pielen = 0, i;\n\tu8\t\t\tchannel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0;\n\tu16\t\t\tlen_channellist_attr = 0;\n\tu32\t\t\tpktlen;\n\tu8\t\t\tdialogToken = 0;\n#ifdef CONFIG_WFD\n\tu32\t\t\t\t\twfdielen = 0;\n#endif\n\n\t/* struct xmit_frame\t\t\t*pmgntframe; */\n\t/* struct pkt_attrib\t\t\t*pattrib; */\n\t/* unsigned char\t\t\t\t\t*pframe; */\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\t/* for debug */\n\tu8 *dbgbuf = pframe;\n\tu8 dbgbufLen = 0, index = 0;\n\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t/* RA fill by FW */\n\t_rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\n\t/* BSSID fill by FW */\n\t_rtw_memset(pwlanhdr->addr3, 0, ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, 0);\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pktlen));\n\n\t/* dialog token, filled by FW */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pktlen));\n\n\t/*\tP2P IE Section. */\n\n\t/*\tP2P OUI */\n\tp2pielen = 0;\n\tp2pie[p2pielen++] = 0x50;\n\tp2pie[p2pielen++] = 0x6F;\n\tp2pie[p2pielen++] = 0x9A;\n\tp2pie[p2pielen++] = 0x09;\t/*\tWFA P2P v1.0 */\n\n\t/*\tCommented by Albert 20101005 */\n\t/*\tAccording to the P2P Specification, the P2P Invitation response frame should contain 5 P2P attributes */\n\t/*\t1. Status */\n\t/*\t2. Configuration Timeout */\n\t/*\t3. Operating Channel\t( Only GO ) */\n\t/*\t4. P2P Group BSSID\t( Only GO ) */\n\t/*\t5. Channel List */\n\n\t/*\tP2P Status */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_STATUS;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);\n\tp2pielen += 2;\n\n\t/*\tValue: filled by FW, defult value is FAIL INFO UNAVAILABLE */\n\tp2pie[p2pielen++] = P2P_STATUS_FAIL_INFO_UNAVAILABLE;\n\n\t/*\tConfiguration Timeout */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;\n\n\t/*\tLength: */\n\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\tp2pie[p2pielen++] = 200;\t/*\t2 seconds needed to be the P2P GO */\n\tp2pie[p2pielen++] = 200;\t/*\t2 seconds needed to be the P2P Client */\n\n\t/* due to defult value is FAIL INFO UNAVAILABLE, so the following IE is not needed */\n#if 0\n\tif (status_code == P2P_STATUS_SUCCESS) {\n\t\tstruct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);\n\n\t\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\t\t/*\tThe P2P Invitation request frame asks this Wi-Fi device to be the P2P GO */\n\t\t\t/*\tIn this case, the P2P Invitation response frame should carry the two more P2P attributes. */\n\t\t\t/*\tFirst one is operating channel attribute. */\n\t\t\t/*\tSecond one is P2P Group BSSID attribute. */\n\n\t\t\t/*\tOperating Channel */\n\t\t\t/*\tType: */\n\t\t\tp2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;\n\n\t\t\t/*\tLength: */\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);\n\t\t\tp2pielen += 2;\n\n\t\t\t/*\tValue: */\n\t\t\t/*\tCountry String */\n\t\t\tp2pie[p2pielen++] = 'X';\n\t\t\tp2pie[p2pielen++] = 'X';\n\n\t\t\t/*\tThe third byte should be set to 0x04. */\n\t\t\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\t\t\tp2pie[p2pielen++] = 0x04;\n\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = 0x51;\t/*\tCopy from SD7 */\n\n\t\t\t/*\tChannel Number */\n\t\t\tp2pie[p2pielen++] = pwdinfo->operating_channel;\t/*\toperating channel number */\n\n\n\t\t\t/*\tP2P Group BSSID */\n\t\t\t/*\tType: */\n\t\t\tp2pie[p2pielen++] = P2P_ATTR_GROUP_BSSID;\n\n\t\t\t/*\tLength: */\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);\n\t\t\tp2pielen += 2;\n\n\t\t\t/*\tValue: */\n\t\t\t/*\tP2P Device Address for GO */\n\t\t\t_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);\n\t\t\tp2pielen += ETH_ALEN;\n\n\t\t}\n\n\t\t/*\tChannel List */\n\t\t/*\tType: */\n\t\tp2pie[p2pielen++] = P2P_ATTR_CH_LIST;\n\n\t\t/*\tLength: */\n\t\t/* Country String(3) */\n\t\t/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */\n\t\t/* + number of channels in all classes */\n\t\tlen_channellist_attr = 3\n\t\t\t+ (1 + 1) * (u16)ch_list->reg_classes\n\t\t\t+ get_reg_classes_full_count(ch_list);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED))\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);\n\t\telse\n\t\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);\n\n#else\n\n\t\t*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);\n\n#endif\n\t\tp2pielen += 2;\n\n\t\t/*\tValue: */\n\t\t/*\tCountry String */\n\t\tp2pie[p2pielen++] = 'X';\n\t\tp2pie[p2pielen++] = 'X';\n\n\t\t/*\tThe third byte should be set to 0x04. */\n\t\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\t\tp2pie[p2pielen++] = 0x04;\n\n\t\t/*\tChannel Entry List */\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED)) {\n\t\t\tu8 union_ch = rtw_mi_get_union_chan(padapter);\n\n\t\t\t/*\tOperating Class */\n\t\t\tif (union_ch > 14) {\n\t\t\t\tif (union_ch >= 149)\n\t\t\t\t\tp2pie[p2pielen++] = 0x7c;\n\t\t\t\telse\n\t\t\t\t\tp2pie[p2pielen++] = 0x73;\n\n\t\t\t} else\n\t\t\t\tp2pie[p2pielen++] = 0x51;\n\n\n\t\t\t/*\tNumber of Channels */\n\t\t\t/*\tJust support 1 channel and this channel is AP's channel */\n\t\t\tp2pie[p2pielen++] = 1;\n\n\t\t\t/*\tChannel List */\n\t\t\tp2pie[p2pielen++] = union_ch;\n\t\t} else\n#endif /* CONFIG_CONCURRENT_MODE */\n\t\t{\n\t\t\tint i, j;\n\t\t\tfor (j = 0; j < ch_list->reg_classes; j++) {\n\t\t\t\t/*\tOperating Class */\n\t\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].reg_class;\n\n\t\t\t\t/*\tNumber of Channels */\n\t\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].channels;\n\n\t\t\t\t/*\tChannel List */\n\t\t\t\tfor (i = 0; i < ch_list->reg_class[j].channels; i++)\n\t\t\t\t\tp2pie[p2pielen++] = ch_list->reg_class[j].channel[i];\n\t\t\t}\n\t\t}\n\t}\n#endif\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pktlen);\n\n#ifdef CONFIG_WFD\n\twfdielen = build_invitation_resp_wfd_ie(pwdinfo, pframe);\n\tpframe += wfdielen;\n\tpktlen += wfdielen;\n#endif\n\n\t*pLength = pktlen;\n\n#if 0\n\t/* printf dbg msg */\n\tdbgbufLen = pktlen;\n\tRTW_INFO(\"======> DBG MSG FOR CONSTRAUCT Invite Rsp\\n\");\n\n\tfor (index = 0; index < dbgbufLen; index++)\n\t\tprintk(\"%x \", *(dbgbuf + index));\n\n\tprintk(\"\\n\");\n\tRTW_INFO(\"<====== DBG MSG FOR CONSTRAUCT Invite Rsp\\n\");\n#endif\n}\n\n\nstatic void rtw_hal_construct_P2PProvisionDisRsp(_adapter *padapter, u8 *pframe, u32 *pLength)\n{\n\tunsigned char category = RTW_WLAN_CATEGORY_PUBLIC;\n\tu8\t\t\taction = P2P_PUB_ACTION_ACTION;\n\tu8\t\t\tdialogToken = 0;\n\tu32\t\t\tp2poui = cpu_to_be32(P2POUI);\n\tu8\t\t\toui_subtype = P2P_PROVISION_DISC_RESP;\n\tu8\t\t\twpsie[100] = { 0x00 };\n\tu8\t\t\twpsielen = 0;\n\tu32\t\t\tpktlen;\n#ifdef CONFIG_WFD\n\tu32\t\t\t\t\twfdielen = 0;\n#endif\n\n\t/* struct xmit_frame\t\t\t*pmgntframe; */\n\t/* struct pkt_attrib\t\t\t*pattrib; */\n\t/* unsigned char\t\t\t\t\t*pframe; */\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\t/* for debug */\n\tu8 *dbgbuf = pframe;\n\tu8 dbgbufLen = 0, index = 0;\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t/* RA filled by FW */\n\t_rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, 0);\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pktlen));\n\t/* dialog token, filled by FW */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pktlen));\n\n\twpsielen = 0;\n\t/*\tWPS OUI */\n\t/* *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); */\n\tRTW_PUT_BE32(wpsie, WPSOUI);\n\twpsielen += 4;\n\n#if 0\n\t/*\tWPS version */\n\t/*\tType: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);\n\twpsielen += 2;\n\n\t/*\tLength: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);\n\twpsielen += 2;\n\n\t/*\tValue: */\n\twpsie[wpsielen++] = WPS_VERSION_1;\t/*\tVersion 1.0 */\n#endif\n\n\t/*\tConfig Method */\n\t/*\tType: */\n\t/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); */\n\tRTW_PUT_BE16(wpsie + wpsielen, WPS_ATTR_CONF_METHOD);\n\twpsielen += 2;\n\n\t/*\tLength: */\n\t/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); */\n\tRTW_PUT_BE16(wpsie + wpsielen, 0x0002);\n\twpsielen += 2;\n\n\t/*\tValue: filled by FW, default value is PBC */\n\t/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( config_method ); */\n\tRTW_PUT_BE16(wpsie + wpsielen, WPS_CM_PUSH_BUTTON);\n\twpsielen += 2;\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pktlen);\n\n#ifdef CONFIG_WFD\n\twfdielen = build_provdisc_resp_wfd_ie(pwdinfo, pframe);\n\tpframe += wfdielen;\n\tpktlen += wfdielen;\n#endif\n\n\t*pLength = pktlen;\n\n\t/* printf dbg msg */\n#if 0\n\tdbgbufLen = pktlen;\n\tRTW_INFO(\"======> DBG MSG FOR CONSTRAUCT  ProvisionDis Rsp\\n\");\n\n\tfor (index = 0; index < dbgbufLen; index++)\n\t\tprintk(\"%x \", *(dbgbuf + index));\n\n\tprintk(\"\\n\");\n\tRTW_INFO(\"<====== DBG MSG FOR CONSTRAUCT ProvisionDis Rsp\\n\");\n#endif\n}\n\nu8 rtw_hal_set_FwP2PRsvdPage_cmd(_adapter *adapter, PRSVDPAGE_LOC rsvdpageloc)\n{\n\tu8 u1H2CP2PRsvdPageParm[H2C_P2PRSVDPAGE_LOC_LEN] = {0};\n\tstruct hal_ops *pHalFunc = &adapter->hal_func;\n\tu8 ret = _FAIL;\n\n\tRTW_INFO(\"P2PRsvdPageLoc: P2PBeacon=%d P2PProbeRsp=%d NegoRsp=%d InviteRsp=%d PDRsp=%d\\n\",\n\t\t rsvdpageloc->LocP2PBeacon, rsvdpageloc->LocP2PProbeRsp,\n\t\t rsvdpageloc->LocNegoRsp, rsvdpageloc->LocInviteRsp,\n\t\t rsvdpageloc->LocPDRsp);\n\n\tSET_H2CCMD_RSVDPAGE_LOC_P2P_BCN(u1H2CP2PRsvdPageParm, rsvdpageloc->LocProbeRsp);\n\tSET_H2CCMD_RSVDPAGE_LOC_P2P_PROBE_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocPsPoll);\n\tSET_H2CCMD_RSVDPAGE_LOC_P2P_NEGO_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocNullData);\n\tSET_H2CCMD_RSVDPAGE_LOC_P2P_INVITE_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocQosNull);\n\tSET_H2CCMD_RSVDPAGE_LOC_P2P_PD_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocBTQosNull);\n\n\t/* FillH2CCmd8723B(padapter, H2C_8723B_P2P_OFFLOAD_RSVD_PAGE, H2C_P2PRSVDPAGE_LOC_LEN, u1H2CP2PRsvdPageParm); */\n\tret = rtw_hal_fill_h2c_cmd(adapter,\n\t\t\t\t   H2C_P2P_OFFLOAD_RSVD_PAGE,\n\t\t\t\t   H2C_P2PRSVDPAGE_LOC_LEN,\n\t\t\t\t   u1H2CP2PRsvdPageParm);\n\n\treturn ret;\n}\n\nu8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter *adapter)\n{\n\n\tu8 offload_cmd[H2C_P2P_OFFLOAD_LEN] = {0};\n\tstruct wifidirect_info\t*pwdinfo = &(adapter->wdinfo);\n\tstruct P2P_WoWlan_Offload_t *p2p_wowlan_offload = (struct P2P_WoWlan_Offload_t *)offload_cmd;\n\tstruct hal_ops *pHalFunc = &adapter->hal_func;\n\tu8 ret = _FAIL;\n\n\t_rtw_memset(p2p_wowlan_offload, 0 , sizeof(struct P2P_WoWlan_Offload_t));\n\tRTW_INFO(\"%s\\n\", __func__);\n\tswitch (pwdinfo->role) {\n\tcase P2P_ROLE_DEVICE:\n\t\tRTW_INFO(\"P2P_ROLE_DEVICE\\n\");\n\t\tp2p_wowlan_offload->role = 0;\n\t\tbreak;\n\tcase P2P_ROLE_CLIENT:\n\t\tRTW_INFO(\"P2P_ROLE_CLIENT\\n\");\n\t\tp2p_wowlan_offload->role = 1;\n\t\tbreak;\n\tcase P2P_ROLE_GO:\n\t\tRTW_INFO(\"P2P_ROLE_GO\\n\");\n\t\tp2p_wowlan_offload->role = 2;\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(\"P2P_ROLE_DISABLE\\n\");\n\t\tbreak;\n\t}\n\tp2p_wowlan_offload->Wps_Config[0] = pwdinfo->supported_wps_cm >> 8;\n\tp2p_wowlan_offload->Wps_Config[1] = pwdinfo->supported_wps_cm;\n\toffload_cmd = (u8 *)p2p_wowlan_offload;\n\tRTW_INFO(\"p2p_wowlan_offload: %x:%x:%x\\n\", offload_cmd[0], offload_cmd[1], offload_cmd[2]);\n\n\tret = rtw_hal_fill_h2c_cmd(adapter,\n\t\t\t\t   H2C_P2P_OFFLOAD,\n\t\t\t\t   H2C_P2P_OFFLOAD_LEN,\n\t\t\t\t   offload_cmd);\n\treturn ret;\n\n\t/* FillH2CCmd8723B(adapter, H2C_8723B_P2P_OFFLOAD, sizeof(struct P2P_WoWlan_Offload_t), (u8 *)p2p_wowlan_offload); */\n}\n#endif /* CONFIG_P2P_WOWLAN */\n\nvoid rtw_hal_construct_beacon(_adapter *padapter,\n\t\t\t\t     u8 *pframe, u32 *pLength)\n{\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tu16\t\t\t\t\t*fctrl;\n\tu32\t\t\t\t\trate_len, pktlen;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t\t*cur_network = &(pmlmeinfo->network);\n\tu8\tbc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\n\n\t/* RTW_INFO(\"%s\\n\", __FUNCTION__); */\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);\n\t/* pmlmeext->mgnt_seq++; */\n\tset_frame_sub_type(pframe, WIFI_BEACON);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\t/* timestamp will be inserted by hardware */\n\tpframe += 8;\n\tpktlen += 8;\n\n\t/* beacon interval: 2 bytes */\n\t_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);\n\n\tpframe += 2;\n\tpktlen += 2;\n\n#if 0\n\t/* capability info: 2 bytes */\n\t_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);\n\n\tpframe += 2;\n\tpktlen += 2;\n\n\tif ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {\n\t\t/* RTW_INFO(\"ie len=%d\\n\", cur_network->IELength); */\n\t\tpktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs);\n\t\t_rtw_memcpy(pframe, cur_network->IEs + sizeof(NDIS_802_11_FIXED_IEs), pktlen);\n\n\t\tgoto _ConstructBeacon;\n\t}\n\n\t/* below for ad-hoc mode */\n\n\t/* SSID */\n\tpframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen);\n\n\t/* supported rates... */\n\trate_len = rtw_get_rateset_len(cur_network->SupportedRates);\n\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen);\n\n\t/* DS parameter set */\n\tpframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen);\n\n\tif ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {\n\t\tu32 ATIMWindow;\n\t\t/* IBSS Parameter Set... */\n\t\t/* ATIMWindow = cur->Configuration.ATIMWindow; */\n\t\tATIMWindow = 0;\n\t\tpframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen);\n\t}\n\n\n\t/* todo: ERP IE */\n\n\n\t/* EXTERNDED SUPPORTED RATE */\n\tif (rate_len > 8)\n\t\tpframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen);\n\n\t/* todo:HT for adhoc */\n\n_ConstructBeacon:\n#endif\n\n\tif ((pktlen + TXDESC_SIZE) > MAX_BEACON_LEN) {\n\t\tRTW_ERR(\"beacon frame too large ,len(%d,%d)\\n\",\n\t\t\t(pktlen + TXDESC_SIZE), MAX_BEACON_LEN);\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\t*pLength = pktlen;\n\n\t/* RTW_INFO(\"%s bcn_sz=%d\\n\", __FUNCTION__, pktlen); */\n\n}\n\nstatic void rtw_hal_construct_PSPoll(_adapter *padapter,\n\t\t\t\t     u8 *pframe, u32 *pLength)\n{\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tu16\t\t\t\t\t*fctrl;\n\tu32\t\t\t\t\tpktlen;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\t/* RTW_INFO(\"%s\\n\", __FUNCTION__); */\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\t/* Frame control. */\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\tSetPwrMgt(fctrl);\n\tset_frame_sub_type(pframe, WIFI_PSPOLL);\n\n\t/* AID. */\n\tset_duration(pframe, (pmlmeinfo->aid | 0xc000));\n\n\t/* BSSID. */\n\t_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\n\t/* TA. */\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\n\t*pLength = 16;\n}\n\n\n#ifdef DBG_FW_DEBUG_MSG_PKT\nvoid rtw_hal_construct_fw_dbg_msg_pkt(\n\tPADAPTER padapter,\n\tu8\t\t*pframe,\n\tu32\t\t*plength)\n{\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tu16\t\t\t\t\t\t*fctrl;\n\tu32\t\t\t\t\t\tpktlen;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wlan_network\t\t*cur_network = &pmlmepriv->cur_network;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8\tbc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\n\n\t/* RTW_INFO(\"%s:%d\\n\", __FUNCTION__, bForcePowerSave); */\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &pwlanhdr->frame_ctl;\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, 0);\n\n\tset_frame_sub_type(pframe, WIFI_DATA);\n\n\tpktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\t*plength = pktlen;\n}\n#endif /*DBG_FW_DEBUG_MSG_PKT*/\n\nvoid rtw_hal_construct_NullFunctionData(\n\tPADAPTER padapter,\n\tu8\t\t*pframe,\n\tu32\t\t*pLength,\n\tu8\t\tbQoS,\n\tu8\t\tAC,\n\tu8\t\tbEosp,\n\tu8\t\tbForcePowerSave)\n{\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tu16\t\t\t\t\t\t*fctrl;\n\tu32\t\t\t\t\t\tpktlen;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wlan_network\t\t*cur_network = &pmlmepriv->cur_network;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8 *sta_addr = NULL;\n\tu8 bssid[ETH_ALEN] = {0};\n\n\t/* RTW_INFO(\"%s:%d\\n\", __FUNCTION__, bForcePowerSave); */\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &pwlanhdr->frame_ctl;\n\t*(fctrl) = 0;\n\tif (bForcePowerSave)\n\t\tSetPwrMgt(fctrl);\n\n\tsta_addr = get_my_bssid(&pmlmeinfo->network);\n\tif (NULL == sta_addr) {\n\t\t_rtw_memcpy(bssid, adapter_mac_addr(padapter), ETH_ALEN);\n\t\tsta_addr = bssid;\n\t}\n\n\tswitch (cur_network->network.InfrastructureMode) {\n\tcase Ndis802_11Infrastructure:\n\t\tSetToDs(fctrl);\n\t\t_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr3, sta_addr, ETH_ALEN);\n\t\tbreak;\n\tcase Ndis802_11APMode:\n\t\tSetFrDs(fctrl);\n\t\t_rtw_memcpy(pwlanhdr->addr1, sta_addr, ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);\n\t\tbreak;\n\tcase Ndis802_11IBSS:\n\tdefault:\n\t\t_rtw_memcpy(pwlanhdr->addr1, sta_addr, ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\t\tbreak;\n\t}\n\n\tSetSeqNum(pwlanhdr, 0);\n\tset_duration(pwlanhdr, 0);\n\n\tif (bQoS == _TRUE) {\n\t\tstruct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr;\n\n\t\tset_frame_sub_type(pframe, WIFI_QOS_DATA_NULL);\n\n\t\tpwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe;\n\t\tSetPriority(&pwlanqoshdr->qc, AC);\n\t\tSetEOSP(&pwlanqoshdr->qc, bEosp);\n\n\t\tpktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos);\n\t} else {\n\t\tset_frame_sub_type(pframe, WIFI_DATA_NULL);\n\n\t\tpktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\t}\n\n\t*pLength = pktlen;\n}\n\nvoid rtw_hal_construct_ProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength,\n\t\t\t\tBOOLEAN bHideSSID)\n{\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tu16\t\t\t\t\t*fctrl;\n\tu8\t\t\t\t\t*mac, *bssid, *sta_addr;\n\tu32\t\t\t\t\tpktlen;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX  *cur_network = &(pmlmeinfo->network);\n\n\t/*RTW_INFO(\"%s\\n\", __FUNCTION__);*/\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tmac = adapter_mac_addr(padapter);\n\tbssid = cur_network->MacAddress;\n\tsta_addr = get_my_bssid(&pmlmeinfo->network);\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\t_rtw_memcpy(pwlanhdr->addr1, sta_addr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, 0);\n\tset_frame_sub_type(fctrl, WIFI_PROBERSP);\n\n\tpktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpframe += pktlen;\n\n\tif (cur_network->IELength > MAX_IE_SZ)\n\t\treturn;\n\n\t_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);\n\tpframe += cur_network->IELength;\n\tpktlen += cur_network->IELength;\n\n\t*pLength = pktlen;\n}\n\n#ifdef CONFIG_WOWLAN\nstatic void rtw_hal_append_tkip_mic(PADAPTER padapter,\n\t\t\t\t    u8 *pframe, u32 offset)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tstruct mic_data\tmicdata;\n\tstruct sta_info\t*psta = NULL;\n\tint res = 0;\n\n\tu8\t*payload = (u8 *)(pframe + offset);\n\n\tu8\tmic[8];\n\tu8\tpriority[4] = {0x0};\n\tu8\tnull_key[16] = {0x0};\n\n\tRTW_INFO(\"%s(): Add MIC, offset: %d\\n\", __func__, offset);\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tpsta = rtw_get_stainfo(&padapter->stapriv,\n\t\t\tget_my_bssid(&(pmlmeinfo->network)));\n\tif (psta != NULL) {\n\t\tres = _rtw_memcmp(&psta->dot11tkiptxmickey.skey[0],\n\t\t\t\t  null_key, 16);\n\t\tif (res == _TRUE)\n\t\t\tRTW_INFO(\"%s(): STA dot11tkiptxmickey==0\\n\", __func__);\n\t\trtw_secmicsetkey(&micdata, &psta->dot11tkiptxmickey.skey[0]);\n\t}\n\n\trtw_secmicappend(&micdata, pwlanhdr->addr3, 6);  /* DA */\n\n\trtw_secmicappend(&micdata, pwlanhdr->addr2, 6); /* SA */\n\n\tpriority[0] = 0;\n\n\trtw_secmicappend(&micdata, &priority[0], 4);\n\n\trtw_secmicappend(&micdata, payload, 36); /* payload length = 8 + 28 */\n\n\trtw_secgetmic(&micdata, &(mic[0]));\n\n\tpayload += 36;\n\n\t_rtw_memcpy(payload, &(mic[0]), 8);\n}\n/*\n * Description:\n *\tConstruct the ARP response packet to support ARP offload.\n *   */\nstatic void rtw_hal_construct_ARPRsp(\n\tPADAPTER padapter,\n\tu8\t\t\t*pframe,\n\tu32\t\t\t*pLength,\n\tu8\t\t\t*pIPAddress\n)\n{\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tu16\t*fctrl;\n\tu32\tpktlen;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wlan_network\t*cur_network = &pmlmepriv->cur_network;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct security_priv\t*psecuritypriv = &padapter->securitypriv;\n\tstatic u8\tARPLLCHeader[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x08, 0x06};\n\tu8\t*pARPRspPkt = pframe;\n\t/* for TKIP Cal MIC */\n\tu8\t*payload = pframe;\n\tu8\tEncryptionHeadOverhead = 0, arp_offset = 0;\n\t/* RTW_INFO(\"%s:%d\\n\", __FUNCTION__, bForcePowerSave); */\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &pwlanhdr->frame_ctl;\n\t*(fctrl) = 0;\n\n\t/* ------------------------------------------------------------------------- */\n\t/* MAC Header. */\n\t/* ------------------------------------------------------------------------- */\n\tSetFrameType(fctrl, WIFI_DATA);\n\t/* set_frame_sub_type(fctrl, 0); */\n\tSetToDs(fctrl);\n\t_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, 0);\n\tset_duration(pwlanhdr, 0);\n\t/* SET_80211_HDR_FRAME_CONTROL(pARPRspPkt, 0); */\n\t/* SET_80211_HDR_TYPE_AND_SUBTYPE(pARPRspPkt, Type_Data); */\n\t/* SET_80211_HDR_TO_DS(pARPRspPkt, 1); */\n\t/* SET_80211_HDR_ADDRESS1(pARPRspPkt, pMgntInfo->Bssid); */\n\t/* SET_80211_HDR_ADDRESS2(pARPRspPkt, Adapter->CurrentAddress); */\n\t/* SET_80211_HDR_ADDRESS3(pARPRspPkt, pMgntInfo->Bssid); */\n\n\t/* SET_80211_HDR_DURATION(pARPRspPkt, 0); */\n\t/* SET_80211_HDR_FRAGMENT_SEQUENCE(pARPRspPkt, 0); */\n#ifdef CONFIG_WAPI_SUPPORT\n\t*pLength = sMacHdrLng;\n#else\n\t*pLength = 24;\n#endif\n\tswitch (psecuritypriv->dot11PrivacyAlgrthm) {\n\tcase _WEP40_:\n\tcase _WEP104_:\n\t\tEncryptionHeadOverhead = 4;\n\t\tbreak;\n\tcase _TKIP_:\n\t\tEncryptionHeadOverhead = 8;\n\t\tbreak;\n\tcase _AES_:\n\t\tEncryptionHeadOverhead = 8;\n\t\tbreak;\n#ifdef CONFIG_WAPI_SUPPORT\n\tcase _SMS4_:\n\t\tEncryptionHeadOverhead = 18;\n\t\tbreak;\n#endif\n\tdefault:\n\t\tEncryptionHeadOverhead = 0;\n\t}\n\n\tif (EncryptionHeadOverhead > 0) {\n\t\t_rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);\n\t\t*pLength += EncryptionHeadOverhead;\n\t\t/* SET_80211_HDR_WEP(pARPRspPkt, 1);  */ /* Suggested by CCW. */\n\t\tSetPrivacy(fctrl);\n\t}\n\n\t/* ------------------------------------------------------------------------- */\n\t/* Frame Body. */\n\t/* ------------------------------------------------------------------------- */\n\tarp_offset = *pLength;\n\tpARPRspPkt = (u8 *)(pframe + arp_offset);\n\tpayload = pARPRspPkt; /* Get Payload pointer */\n\t/* LLC header */\n\t_rtw_memcpy(pARPRspPkt, ARPLLCHeader, 8);\n\t*pLength += 8;\n\n\t/* ARP element */\n\tpARPRspPkt += 8;\n\tSET_ARP_HTYPE(pARPRspPkt, 1);\n\tSET_ARP_PTYPE(pARPRspPkt, ETH_P_IP);\t/* IP protocol */\n\tSET_ARP_HLEN(pARPRspPkt, ETH_ALEN);\n\tSET_ARP_PLEN(pARPRspPkt, RTW_IP_ADDR_LEN);\n\tSET_ARP_OPER(pARPRspPkt, 2);\t/* ARP response */\n\tSET_ARP_SENDER_MAC_ADDR(pARPRspPkt, adapter_mac_addr(padapter));\n\tSET_ARP_SENDER_IP_ADDR(pARPRspPkt, pIPAddress);\n#ifdef CONFIG_ARP_KEEP_ALIVE\n\tif (!is_zero_mac_addr(pmlmepriv->gw_mac_addr)) {\n\t\tSET_ARP_TARGET_MAC_ADDR(pARPRspPkt, pmlmepriv->gw_mac_addr);\n\t\tSET_ARP_TARGET_IP_ADDR(pARPRspPkt, pmlmepriv->gw_ip);\n\t} else\n#endif\n\t{\n\t\tSET_ARP_TARGET_MAC_ADDR(pARPRspPkt,\n\t\t\t\t    get_my_bssid(&(pmlmeinfo->network)));\n\t\tSET_ARP_TARGET_IP_ADDR(pARPRspPkt,\n\t\t\t\t\t   pIPAddress);\n\t\tRTW_INFO(\"%s Target Mac Addr:\" MAC_FMT \"\\n\", __FUNCTION__,\n\t\t\t MAC_ARG(get_my_bssid(&(pmlmeinfo->network))));\n\t\tRTW_INFO(\"%s Target IP Addr\" IP_FMT \"\\n\", __FUNCTION__,\n\t\t\t IP_ARG(pIPAddress));\n\t}\n\n\t*pLength += 28;\n\n\tif (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {\n\t\tif (IS_HARDWARE_TYPE_8188E(padapter) ||\n\t\t    IS_HARDWARE_TYPE_8812(padapter)) {\n\t\t\trtw_hal_append_tkip_mic(padapter, pframe, arp_offset);\n\t\t}\n\t\t*pLength += 8;\n\t}\n}\n\n#ifdef CONFIG_IPV6\n/*\n * Description: Neighbor Discovery Offload.\n */\nstatic void rtw_hal_construct_na_message(_adapter *padapter,\n\t\t\t\t     u8 *pframe, u32 *pLength)\n{\n\tstruct rtw_ieee80211_hdr *pwlanhdr = NULL;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wlan_network\t*cur_network = &pmlmepriv->cur_network;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &pmlmeext->mlmext_info;\n\tstruct security_priv\t*psecuritypriv = &padapter->securitypriv;\n\n\tu32 pktlen = 0;\n\tu16 *fctrl = NULL;\n\n\tu8 ns_hdr[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x86, 0xDD};\n\tu8 ipv6_info[4] = {0x60, 0x00, 0x00, 0x00};\n\tu8 ipv6_contx[4] = {0x00, 0x20, 0x3a, 0xff};\n\tu8 icmpv6_hdr[8] = {0x88, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00};\n\tu8 val8 = 0;\n\n\tu8 *p_na_msg = pframe;\n\t/* for TKIP Cal MIC */\n\tu8 *payload = pframe;\n\tu8 EncryptionHeadOverhead = 0, na_msg_offset = 0;\n\t/* RTW_INFO(\"%s:%d\\n\", __FUNCTION__, bForcePowerSave); */\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &pwlanhdr->frame_ctl;\n\t*(fctrl) = 0;\n\n\t/* ------------------------------------------------------------------------- */\n\t/* MAC Header. */\n\t/* ------------------------------------------------------------------------- */\n\tSetFrameType(fctrl, WIFI_DATA);\n\tSetToDs(fctrl);\n\t_rtw_memcpy(pwlanhdr->addr1,\n\t\t    get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2,\n\t\t    adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3,\n\t\t    get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, 0);\n\tset_duration(pwlanhdr, 0);\n\n#ifdef CONFIG_WAPI_SUPPORT\n\t*pLength = sMacHdrLng;\n#else\n\t*pLength = 24;\n#endif\n\tswitch (psecuritypriv->dot11PrivacyAlgrthm) {\n\tcase _WEP40_:\n\tcase _WEP104_:\n\t\tEncryptionHeadOverhead = 4;\n\t\tbreak;\n\tcase _TKIP_:\n\t\tEncryptionHeadOverhead = 8;\n\t\tbreak;\n\tcase _AES_:\n\t\tEncryptionHeadOverhead = 8;\n\t\tbreak;\n#ifdef CONFIG_WAPI_SUPPORT\n\tcase _SMS4_:\n\t\tEncryptionHeadOverhead = 18;\n\t\tbreak;\n#endif\n\tdefault:\n\t\tEncryptionHeadOverhead = 0;\n\t}\n\n\tif (EncryptionHeadOverhead > 0) {\n\t\t_rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);\n\t\t*pLength += EncryptionHeadOverhead;\n\t\t/* SET_80211_HDR_WEP(pARPRspPkt, 1);  */ /* Suggested by CCW. */\n\t\tSetPrivacy(fctrl);\n\t}\n\n\t/* ------------------------------------------------------------------------- */\n\t/* Frame Body. */\n\t/* ------------------------------------------------------------------------- */\n\tna_msg_offset = *pLength;\n\tp_na_msg = (u8 *)(pframe + na_msg_offset);\n\tpayload = p_na_msg; /* Get Payload pointer */\n\n\t/* LLC header */\n\tval8 = sizeof(ns_hdr);\n\t_rtw_memcpy(p_na_msg, ns_hdr, val8);\n\t*pLength += val8;\n\tp_na_msg += val8;\n\n\t/* IPv6 Header */\n\t/* 1 . Information (4 bytes): 0x60 0x00 0x00 0x00 */\n\tval8 = sizeof(ipv6_info);\n\t_rtw_memcpy(p_na_msg, ipv6_info, val8);\n\t*pLength += val8;\n\tp_na_msg += val8;\n\n\t/* 2 . playload : 0x00 0x20 , NextProt : 0x3a (ICMPv6) HopLim : 0xff */\n\tval8 = sizeof(ipv6_contx);\n\t_rtw_memcpy(p_na_msg, ipv6_contx, val8);\n\t*pLength += val8;\n\tp_na_msg += val8;\n\n\t/* 3 . SA : 16 bytes , DA : 16 bytes ( Fw will filled ) */\n\t_rtw_memset(&(p_na_msg[*pLength]), 0, 32);\n\t*pLength += 32;\n\tp_na_msg += 32;\n\n\t/* ICMPv6 */\n\t/* 1. Type : 0x88 (NA)\n\t * 2. Code : 0x00\n\t * 3. ChechSum : 0x00 0x00 (RSvd)\n\t * 4. NAFlag: 0x60 0x00 0x00 0x00 ( Solicited , Override)\n\t */\n\tval8 = sizeof(icmpv6_hdr);\n\t_rtw_memcpy(p_na_msg, icmpv6_hdr, val8);\n\t*pLength += val8;\n\tp_na_msg += val8;\n\n\t/* TA: 16 bytes*/\n\t_rtw_memset(&(p_na_msg[*pLength]), 0, 16);\n\t*pLength += 16;\n\tp_na_msg += 16;\n\n\t/* ICMPv6 Target Link Layer Address */\n\tp_na_msg[0] = 0x02; /* type */\n\tp_na_msg[1] = 0x01; /* len 1 unit of 8 octes */\n\t*pLength += 2;\n\tp_na_msg += 2;\n\n\t_rtw_memset(&(p_na_msg[*pLength]), 0, 6);\n\t*pLength += 6;\n\tp_na_msg += 6;\n\n\tif (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {\n\t\tif (IS_HARDWARE_TYPE_8188E(padapter) ||\n\t\t    IS_HARDWARE_TYPE_8812(padapter)) {\n\t\t\trtw_hal_append_tkip_mic(padapter, pframe,\n\t\t\t\t\t\tna_msg_offset);\n\t\t}\n\t\t*pLength += 8;\n\t}\n}\n/*\n * Description: Neighbor Discovery Protocol Information.\n */\nstatic void rtw_hal_construct_ndp_info(_adapter *padapter,\n\t\t\t\t     u8 *pframe, u32 *pLength)\n{\n\tstruct mlme_ext_priv *pmlmeext = NULL;\n\tstruct mlme_ext_info *pmlmeinfo = NULL;\n\tstruct rtw_ndp_info ndp_info;\n\tu8\t*pndp_info = pframe;\n\tu8\tlen = sizeof(struct rtw_ndp_info);\n\n\tRTW_INFO(\"%s: len: %d\\n\", __func__, len);\n\n\tpmlmeext =  &padapter->mlmeextpriv;\n\tpmlmeinfo = &pmlmeext->mlmext_info;\n\n\t_rtw_memset(pframe, 0, len);\n\t_rtw_memset(&ndp_info, 0, len);\n\n\tndp_info.enable = 1;\n\tndp_info.check_remote_ip = 0;\n\tndp_info.num_of_target_ip = 1;\n\n\t_rtw_memcpy(&ndp_info.target_link_addr, adapter_mac_addr(padapter),\n\t\t    ETH_ALEN);\n\t_rtw_memcpy(&ndp_info.target_ipv6_addr, pmlmeinfo->ip6_addr,\n\t\t    RTW_IPv6_ADDR_LEN);\n\n\t_rtw_memcpy(pndp_info, &ndp_info, len);\n}\n#endif /* CONFIG_IPV6 */\n\n#ifdef CONFIG_PNO_SUPPORT\nstatic void rtw_hal_construct_ProbeReq(_adapter *padapter, u8 *pframe,\n\t\t\t\t       u32 *pLength, pno_ssid_t *ssid)\n{\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tu16\t\t\t\t*fctrl;\n\tu32\t\t\t\tpktlen;\n\tunsigned char\t\t\t*mac;\n\tunsigned char\t\t\tbssrate[NumRates];\n\tstruct xmit_priv\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tint\tbssrate_len = 0;\n\tu8\tbc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\tmac = adapter_mac_addr(padapter);\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN);\n\n\t_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, 0);\n\tset_frame_sub_type(pframe, WIFI_PROBEREQ);\n\n\tpktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpframe += pktlen;\n\n\tif (ssid == NULL)\n\t\tpframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &pktlen);\n\telse {\n\t\t/* RTW_INFO(\"%s len:%d\\n\", ssid->SSID, ssid->SSID_len); */\n\t\tpframe = rtw_set_ie(pframe, _SSID_IE_, ssid->SSID_len, ssid->SSID, &pktlen);\n\t}\n\n\tget_rate_set(padapter, bssrate, &bssrate_len);\n\n\tif (bssrate_len > 8) {\n\t\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &pktlen);\n\t\tpframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &pktlen);\n\t} else\n\t\tpframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &pktlen);\n\n\t*pLength = pktlen;\n}\n\nstatic void rtw_hal_construct_PNO_info(_adapter *padapter,\n\t\t\t\t       u8 *pframe, u32 *pLength)\n{\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);\n\tint i;\n\n\tu8\t*pPnoInfoPkt = pframe;\n\tpPnoInfoPkt = (u8 *)(pframe + *pLength);\n\t_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_num, 1);\n\n\tpPnoInfoPkt += 1;\n\t_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->hidden_ssid_num, 1);\n\n\tpPnoInfoPkt += 3;\n\t_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->fast_scan_period, 1);\n\n\tpPnoInfoPkt += 4;\n\t_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->fast_scan_iterations, 4);\n\n\tpPnoInfoPkt += 4;\n\t_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->slow_scan_period, 4);\n\n\tpPnoInfoPkt += 4;\n\t_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_length, MAX_PNO_LIST_COUNT);\n\n\tpPnoInfoPkt += MAX_PNO_LIST_COUNT;\n\t_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_cipher_info, MAX_PNO_LIST_COUNT);\n\n\tpPnoInfoPkt += MAX_PNO_LIST_COUNT;\n\t_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_channel_info, MAX_PNO_LIST_COUNT);\n\n\tpPnoInfoPkt += MAX_PNO_LIST_COUNT;\n\t_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->loc_probe_req, MAX_HIDDEN_AP);\n\n\tpPnoInfoPkt += MAX_HIDDEN_AP;\n\n\t/*\n\tSSID is located at 128th Byte in NLO info Page\n\t*/\n\n\t*pLength += 128;\n\tpPnoInfoPkt = pframe + 128;\n\n\tfor (i = 0; i < pwrctl->pnlo_info->ssid_num ; i++) {\n\t\t_rtw_memcpy(pPnoInfoPkt, &pwrctl->pno_ssid_list->node[i].SSID,\n\t\t\t    pwrctl->pnlo_info->ssid_length[i]);\n\t\t*pLength += WLAN_SSID_MAXLEN;\n\t\tpPnoInfoPkt += WLAN_SSID_MAXLEN;\n\t}\n}\n\nstatic void rtw_hal_construct_ssid_list(_adapter *padapter,\n\t\t\t\t\tu8 *pframe, u32 *pLength)\n{\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);\n\tu8 *pSSIDListPkt = pframe;\n\tint i;\n\n\tpSSIDListPkt = (u8 *)(pframe + *pLength);\n\n\tfor (i = 0; i < pwrctl->pnlo_info->ssid_num ; i++) {\n\t\t_rtw_memcpy(pSSIDListPkt, &pwrctl->pno_ssid_list->node[i].SSID,\n\t\t\t    pwrctl->pnlo_info->ssid_length[i]);\n\n\t\t*pLength += WLAN_SSID_MAXLEN;\n\t\tpSSIDListPkt += WLAN_SSID_MAXLEN;\n\t}\n}\n\nstatic void rtw_hal_construct_scan_info(_adapter *padapter,\n\t\t\t\t\tu8 *pframe, u32 *pLength)\n{\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);\n\tu8 *pScanInfoPkt = pframe;\n\tint i;\n\n\tpScanInfoPkt = (u8 *)(pframe + *pLength);\n\n\t_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->channel_num, 1);\n\n\t*pLength += 1;\n\tpScanInfoPkt += 1;\n\t_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_ch, 1);\n\n\n\t*pLength += 1;\n\tpScanInfoPkt += 1;\n\t_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_bw, 1);\n\n\n\t*pLength += 1;\n\tpScanInfoPkt += 1;\n\t_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_40_offset, 1);\n\n\t*pLength += 1;\n\tpScanInfoPkt += 1;\n\t_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_80_offset, 1);\n\n\t*pLength += 1;\n\tpScanInfoPkt += 1;\n\t_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->periodScan, 1);\n\n\t*pLength += 1;\n\tpScanInfoPkt += 1;\n\t_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->period_scan_time, 1);\n\n\t*pLength += 1;\n\tpScanInfoPkt += 1;\n\t_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->enableRFE, 1);\n\n\t*pLength += 1;\n\tpScanInfoPkt += 1;\n\t_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->rfe_type, 8);\n\n\t*pLength += 8;\n\tpScanInfoPkt += 8;\n\n\tfor (i = 0 ; i < MAX_SCAN_LIST_COUNT ; i++) {\n\t\t_rtw_memcpy(pScanInfoPkt,\n\t\t\t    &pwrctl->pscan_info->ssid_channel_info[i], 4);\n\t\t*pLength += 4;\n\t\tpScanInfoPkt += 4;\n\t}\n}\n#endif /* CONFIG_PNO_SUPPORT */\n\n#ifdef CONFIG_GTK_OL\nstatic void rtw_hal_construct_GTKRsp(\n\tPADAPTER\tpadapter,\n\tu8\t\t*pframe,\n\tu32\t\t*pLength\n)\n{\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tu16\t*fctrl;\n\tu32\tpktlen;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct wlan_network\t*cur_network = &pmlmepriv->cur_network;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct security_priv\t*psecuritypriv = &padapter->securitypriv;\n\tstatic u8\tLLCHeader[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x88, 0x8E};\n\tstatic u8\tGTKbody_a[11] = {0x01, 0x03, 0x00, 0x5F, 0x02, 0x03, 0x12, 0x00, 0x10, 0x42, 0x0B};\n\tu8\t*pGTKRspPkt = pframe;\n\tu8\tEncryptionHeadOverhead = 0;\n\t/* RTW_INFO(\"%s:%d\\n\", __FUNCTION__, bForcePowerSave); */\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &pwlanhdr->frame_ctl;\n\t*(fctrl) = 0;\n\n\t/* ------------------------------------------------------------------------- */\n\t/* MAC Header. */\n\t/* ------------------------------------------------------------------------- */\n\tSetFrameType(fctrl, WIFI_DATA);\n\t/* set_frame_sub_type(fctrl, 0); */\n\tSetToDs(fctrl);\n\n\t_rtw_memcpy(pwlanhdr->addr1,\n\t\t    get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\n\t_rtw_memcpy(pwlanhdr->addr2,\n\t\t    adapter_mac_addr(padapter), ETH_ALEN);\n\n\t_rtw_memcpy(pwlanhdr->addr3,\n\t\t    get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, 0);\n\tset_duration(pwlanhdr, 0);\n\n#ifdef CONFIG_WAPI_SUPPORT\n\t*pLength = sMacHdrLng;\n#else\n\t*pLength = 24;\n#endif /* CONFIG_WAPI_SUPPORT */\n\n\t/* ------------------------------------------------------------------------- */\n\t/* Security Header: leave space for it if necessary. */\n\t/* ------------------------------------------------------------------------- */\n\tswitch (psecuritypriv->dot11PrivacyAlgrthm) {\n\tcase _WEP40_:\n\tcase _WEP104_:\n\t\tEncryptionHeadOverhead = 4;\n\t\tbreak;\n\tcase _TKIP_:\n\t\tEncryptionHeadOverhead = 8;\n\t\tbreak;\n\tcase _AES_:\n\t\tEncryptionHeadOverhead = 8;\n\t\tbreak;\n#ifdef CONFIG_WAPI_SUPPORT\n\tcase _SMS4_:\n\t\tEncryptionHeadOverhead = 18;\n\t\tbreak;\n#endif /* CONFIG_WAPI_SUPPORT */\n\tdefault:\n\t\tEncryptionHeadOverhead = 0;\n\t}\n\n\tif (EncryptionHeadOverhead > 0) {\n\t\t_rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);\n\t\t*pLength += EncryptionHeadOverhead;\n\t\t/* SET_80211_HDR_WEP(pGTKRspPkt, 1);  */ /* Suggested by CCW. */\n\t\t/* GTK's privacy bit is done by FW */\n\t\t/* SetPrivacy(fctrl); */\n\t}\n\t/* ------------------------------------------------------------------------- */\n\t/* Frame Body. */\n\t/* ------------------------------------------------------------------------- */\n\tpGTKRspPkt = (u8 *)(pframe + *pLength);\n\t/* LLC header */\n\t_rtw_memcpy(pGTKRspPkt, LLCHeader, 8);\n\t*pLength += 8;\n\n\t/* GTK element */\n\tpGTKRspPkt += 8;\n\n\t/* GTK frame body after LLC, part 1 */\n\t/* TKIP key_length = 32, AES key_length = 16 */\n\tif (psecuritypriv->dot118021XGrpPrivacy == _TKIP_)\n\t\tGTKbody_a[8] = 0x20;\n\n\t/* GTK frame body after LLC, part 1 */\n\t_rtw_memcpy(pGTKRspPkt, GTKbody_a, 11);\n\t*pLength += 11;\n\tpGTKRspPkt += 11;\n\t/* GTK frame body after LLC, part 2 */\n\t_rtw_memset(&(pframe[*pLength]), 0, 88);\n\t*pLength += 88;\n\tpGTKRspPkt += 88;\n\n\tif (psecuritypriv->dot118021XGrpPrivacy == _TKIP_)\n\t\t*pLength += 8;\n}\n#endif /* CONFIG_GTK_OL */\n\n#define PN_2_CCMPH(ch,key_id)\t((ch) & 0x000000000000ffff) \\\n\t\t\t\t| (((ch) & 0x0000ffffffff0000) << 16) \\\n\t\t\t\t| (((key_id) << 30)) \\\n\t\t\t\t| BIT(29)\nstatic void rtw_hal_construct_remote_control_info(_adapter *adapter,\n\t\t\t\t\t\t  u8 *pframe, u32 *pLength)\n{\n\tstruct mlme_priv   *pmlmepriv = &adapter->mlmepriv;\n\tstruct sta_priv *pstapriv = &adapter->stapriv;\n\tstruct security_priv *psecuritypriv = &adapter->securitypriv;\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;\n\tstruct sta_info *psta;\n\tstruct stainfo_rxcache *prxcache;\n\tu8 cur_dot11rxiv[8], id = 0, tid_id = 0, i = 0;\n\tsize_t sz = 0, total = 0;\n\tu64 ccmp_hdr = 0, tmp_key = 0;\n\n\tpsta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));\n\n\tif (psta == NULL) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tprxcache = &psta->sta_recvpriv.rxcache;\n\tsz = sizeof(cur_dot11rxiv);\n\n\t/* 3 SEC IV * 1 page */\n\trtw_get_sec_iv(adapter, cur_dot11rxiv,\n\t\t       get_my_bssid(&pmlmeinfo->network));\n\n\t_rtw_memcpy(pframe, cur_dot11rxiv, sz);\n\t*pLength += sz;\n\tpframe += sz;\n\n\t_rtw_memset(&cur_dot11rxiv, 0, sz);\n\n\tif (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) {\n\t\tid = psecuritypriv->dot118021XGrpKeyid;\n\t\ttid_id = prxcache->last_tid;\n\t\tREMOTE_INFO_CTRL_SET_VALD_EN(cur_dot11rxiv, 0xdd);\n\t\tREMOTE_INFO_CTRL_SET_PTK_EN(cur_dot11rxiv, 1);\n\t\tREMOTE_INFO_CTRL_SET_GTK_EN(cur_dot11rxiv, 1);\n\t\tREMOTE_INFO_CTRL_SET_GTK_IDX(cur_dot11rxiv, id);\n\t\t_rtw_memcpy(pframe, cur_dot11rxiv, sz);\n\t\t*pLength += sz;\n\t\tpframe += sz;\n\n\t\t_rtw_memcpy(pframe, prxcache->iv[tid_id], sz);\n\t\t*pLength += sz;\n\t\tpframe += sz;\n\n\t\ttotal = sizeof(psecuritypriv->iv_seq);\n\t\ttotal /= sizeof(psecuritypriv->iv_seq[0]);\n\n\t\tfor (i = 0 ; i < total ; i ++) {\n\t\t\tccmp_hdr =\n\t\t\t\tle64_to_cpu(*(u64*)psecuritypriv->iv_seq[i]);\n\t\t\t_rtw_memset(&cur_dot11rxiv, 0, sz);\n\t\t\tif (ccmp_hdr != 0) {\n\t\t\t\ttmp_key = i;\n\t\t\t\tccmp_hdr = PN_2_CCMPH(ccmp_hdr, tmp_key);\n\t\t\t\t*(u64*)cur_dot11rxiv = cpu_to_le64(ccmp_hdr);\n\t\t\t\t_rtw_memcpy(pframe, cur_dot11rxiv, sz);\n\t\t\t}\n\t\t\t*pLength += sz;\n\t\t\tpframe += sz;\n\t\t}\n\t}\n}\n\nvoid rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,\n\t\t  u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len,\n\t\t\t\t  RSVDPAGE_LOC *rsvd_page_loc)\n{\n\tstruct security_priv *psecuritypriv = &adapter->securitypriv;\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);\n\tstruct mlme_ext_priv\t*pmlmeext;\n\tstruct mlme_ext_info\t*pmlmeinfo;\n\tu32\tARPLength = 0, GTKLength = 0, PNOLength = 0, ScanInfoLength = 0;\n\tu32     SSIDLegnth = 0, ProbeReqLength = 0, ns_len = 0, rc_len = 0;\n\tu8 CurtPktPageNum = 0;\n\n#ifdef CONFIG_GTK_OL\n\tstruct sta_priv *pstapriv = &adapter->stapriv;\n\tstruct sta_info *psta;\n\tstruct security_priv *psecpriv = &adapter->securitypriv;\n\tu8 kek[RTW_KEK_LEN];\n\tu8 kck[RTW_KCK_LEN];\n#endif /* CONFIG_GTK_OL */\n#ifdef CONFIG_PNO_SUPPORT\n\tint pno_index;\n\tu8 ssid_num;\n#endif /* CONFIG_PNO_SUPPORT */\n\n\tpmlmeext = &adapter->mlmeextpriv;\n\tpmlmeinfo = &pmlmeext->mlmext_info;\n\n\tif (pwrctl->wowlan_pno_enable == _FALSE) {\n\t\t/* ARP RSP * 1 page */\n\n\t\trsvd_page_loc->LocArpRsp = *page_num;\n\n\t\tRTW_INFO(\"LocArpRsp: %d\\n\", rsvd_page_loc->LocArpRsp);\n\n\t\trtw_hal_construct_ARPRsp(adapter, &pframe[index],\n\t\t\t\t\t &ARPLength, pmlmeinfo->ip_addr);\n\n\t\trtw_hal_fill_fake_txdesc(adapter,\n\t\t\t\t\t &pframe[index - tx_desc],\n\t\t\t\t\t ARPLength, _FALSE, _FALSE, _TRUE);\n\n\t\tCurtPktPageNum = (u8)PageNum(tx_desc + ARPLength, page_size);\n\n\t\t*page_num += CurtPktPageNum;\n\n\t\tindex += (CurtPktPageNum * page_size);\n\t\tRSVD_PAGE_CFG(\"WOW-ARPRsp\", CurtPktPageNum, *page_num, 0);\n\n#ifdef CONFIG_IPV6\n\t\t/* 2 NS offload and NDP Info*/\n\t\tif (pwrctl->wowlan_ns_offload_en == _TRUE) {\n\t\t\trsvd_page_loc->LocNbrAdv = *page_num;\n\t\t\tRTW_INFO(\"LocNbrAdv: %d\\n\", rsvd_page_loc->LocNbrAdv);\n\t\t\trtw_hal_construct_na_message(adapter,\n\t\t\t\t\t\t     &pframe[index], &ns_len);\n\t\t\trtw_hal_fill_fake_txdesc(adapter,\n\t\t\t\t\t\t &pframe[index - tx_desc],\n\t\t\t\t\t\t ns_len, _FALSE,\n\t\t\t\t\t\t _FALSE, _TRUE);\n\t\t\tCurtPktPageNum = (u8)PageNum(tx_desc + ns_len,\n\t\t\t\t\t\t      page_size);\n\t\t\t*page_num += CurtPktPageNum;\n\t\t\tindex += (CurtPktPageNum * page_size);\n\t\t\tRSVD_PAGE_CFG(\"WOW-NbrAdv\", CurtPktPageNum, *page_num, 0);\n\n\t\t\trsvd_page_loc->LocNDPInfo = *page_num;\n\t\t\tRTW_INFO(\"LocNDPInfo: %d\\n\",\n\t\t\t\t rsvd_page_loc->LocNDPInfo);\n\n\t\t\trtw_hal_construct_ndp_info(adapter,\n\t\t\t\t\t\t   &pframe[index - tx_desc],\n\t\t\t\t\t\t   &ns_len);\n\t\t\tCurtPktPageNum =\n\t\t\t\t(u8)PageNum(tx_desc + ns_len, page_size);\n\t\t\t*page_num += CurtPktPageNum;\n\t\t\tindex += (CurtPktPageNum * page_size);\n\t\t\tRSVD_PAGE_CFG(\"WOW-NDPInfo\", CurtPktPageNum, *page_num, 0);\n\n\t\t}\n#endif /*CONFIG_IPV6*/\n\t\t/* 3 Remote Control Info. * 1 page */\n\t\trsvd_page_loc->LocRemoteCtrlInfo = *page_num;\n\t\tRTW_INFO(\"LocRemoteCtrlInfo: %d\\n\", rsvd_page_loc->LocRemoteCtrlInfo);\n\t\trtw_hal_construct_remote_control_info(adapter,\n\t\t\t\t\t\t      &pframe[index - tx_desc],\n\t\t\t\t\t\t      &rc_len);\n\t\tCurtPktPageNum = (u8)PageNum(rc_len, page_size);\n\t\t*page_num += CurtPktPageNum;\n\t\t*total_pkt_len = index + rc_len;\n\t\tRSVD_PAGE_CFG(\"WOW-RCI\", CurtPktPageNum, *page_num, *total_pkt_len);\n#ifdef CONFIG_GTK_OL\n\t\tindex += (CurtPktPageNum * page_size);\n\n\t\t/* if the ap staion info. exists, get the kek, kck from staion info. */\n\t\tpsta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));\n\t\tif (psta == NULL) {\n\t\t\t_rtw_memset(kek, 0, RTW_KEK_LEN);\n\t\t\t_rtw_memset(kck, 0, RTW_KCK_LEN);\n\t\t\tRTW_INFO(\"%s, KEK, KCK download rsvd page all zero\\n\",\n\t\t\t\t __func__);\n\t\t} else {\n\t\t\t_rtw_memcpy(kek, psta->kek, RTW_KEK_LEN);\n\t\t\t_rtw_memcpy(kck, psta->kck, RTW_KCK_LEN);\n\t\t}\n\n\t\t/* 3 KEK, KCK */\n\t\trsvd_page_loc->LocGTKInfo = *page_num;\n\t\tRTW_INFO(\"LocGTKInfo: %d\\n\", rsvd_page_loc->LocGTKInfo);\n\n\t\tif (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8812(adapter)) {\n\t\t\tstruct security_priv *psecpriv = NULL;\n\n\t\t\tpsecpriv = &adapter->securitypriv;\n\t\t\t_rtw_memcpy(pframe + index - tx_desc,\n\t\t\t\t    &psecpriv->dot11PrivacyAlgrthm, 1);\n\t\t\t_rtw_memcpy(pframe + index - tx_desc + 1,\n\t\t\t\t    &psecpriv->dot118021XGrpPrivacy, 1);\n\t\t\t_rtw_memcpy(pframe + index - tx_desc + 2,\n\t\t\t\t    kck, RTW_KCK_LEN);\n\t\t\t_rtw_memcpy(pframe + index - tx_desc + 2 + RTW_KCK_LEN,\n\t\t\t\t    kek, RTW_KEK_LEN);\n\t\t\tCurtPktPageNum = (u8)PageNum(tx_desc + 2 + RTW_KCK_LEN + RTW_KEK_LEN, page_size);\n\t\t} else {\n\n\t\t\t_rtw_memcpy(pframe + index - tx_desc, kck, RTW_KCK_LEN);\n\t\t\t_rtw_memcpy(pframe + index - tx_desc + RTW_KCK_LEN,\n\t\t\t\t    kek, RTW_KEK_LEN);\n\t\t\tGTKLength = tx_desc + RTW_KCK_LEN + RTW_KEK_LEN;\n\n\t\t\tif (psta != NULL &&\n\t\t\t\tpsecuritypriv->dot118021XGrpPrivacy == _TKIP_) {\n\t\t\t\t_rtw_memcpy(pframe + index - tx_desc + 56,\n\t\t\t\t\t&psta->dot11tkiptxmickey, RTW_TKIP_MIC_LEN);\n\t\t\t\tGTKLength += RTW_TKIP_MIC_LEN;\n\t\t\t}\n\t\t\tCurtPktPageNum = (u8)PageNum(GTKLength, page_size);\n\t\t}\n#if 0\n\t\t{\n\t\t\tint i;\n\t\t\tprintk(\"\\ntoFW KCK: \");\n\t\t\tfor (i = 0; i < 16; i++)\n\t\t\t\tprintk(\" %02x \", kck[i]);\n\t\t\tprintk(\"\\ntoFW KEK: \");\n\t\t\tfor (i = 0; i < 16; i++)\n\t\t\t\tprintk(\" %02x \", kek[i]);\n\t\t\tprintk(\"\\n\");\n\t\t}\n\n\t\tRTW_INFO(\"%s(): HW_VAR_SET_TX_CMD: KEK KCK %p %d\\n\",\n\t\t\t __FUNCTION__, &pframe[index - tx_desc],\n\t\t\t (tx_desc + RTW_KCK_LEN + RTW_KEK_LEN));\n#endif\n\n\t\t*page_num += CurtPktPageNum;\n\n\t\tindex += (CurtPktPageNum * page_size);\n\t\tRSVD_PAGE_CFG(\"WOW-GTKInfo\", CurtPktPageNum, *page_num, 0);\n\n\t\t/* 3 GTK Response */\n\t\trsvd_page_loc->LocGTKRsp = *page_num;\n\t\tRTW_INFO(\"LocGTKRsp: %d\\n\", rsvd_page_loc->LocGTKRsp);\n\t\trtw_hal_construct_GTKRsp(adapter, &pframe[index], &GTKLength);\n\n\t\trtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],\n\t\t\t\t\t GTKLength, _FALSE, _FALSE, _TRUE);\n#if 0\n\t\t{\n\t\t\tint gj;\n\t\t\tprintk(\"123GTK pkt=>\\n\");\n\t\t\tfor (gj = 0; gj < GTKLength + tx_desc; gj++) {\n\t\t\t\tprintk(\" %02x \", pframe[index - tx_desc + gj]);\n\t\t\t\tif ((gj + 1) % 16 == 0)\n\t\t\t\t\tprintk(\"\\n\");\n\t\t\t}\n\t\t\tprintk(\" <=end\\n\");\n\t\t}\n\n\t\tRTW_INFO(\"%s(): HW_VAR_SET_TX_CMD: GTK RSP %p %d\\n\",\n\t\t\t __FUNCTION__, &pframe[index - tx_desc],\n\t\t\t (tx_desc + GTKLength));\n#endif\n\n\t\tCurtPktPageNum = (u8)PageNum(tx_desc + GTKLength, page_size);\n\n\t\t*page_num += CurtPktPageNum;\n\n\t\tindex += (CurtPktPageNum * page_size);\n\t\tRSVD_PAGE_CFG(\"WOW-GTKRsp\", CurtPktPageNum, *page_num, 0);\n\n\t\t/* below page is empty for GTK extension memory */\n\t\t/* 3(11) GTK EXT MEM */\n\t\trsvd_page_loc->LocGTKEXTMEM = *page_num;\n\t\tRTW_INFO(\"LocGTKEXTMEM: %d\\n\", rsvd_page_loc->LocGTKEXTMEM);\n\t\tCurtPktPageNum = 2;\n\n\t\tif (page_size >= 256)\n\t\t\tCurtPktPageNum = 1;\n\n\t\t*page_num += CurtPktPageNum;\n\t\t/* extension memory for FW */\n\t\t*total_pkt_len = index + (page_size * CurtPktPageNum);\n\t\tRSVD_PAGE_CFG(\"WOW-GTKEXTMEM\", CurtPktPageNum, *page_num, *total_pkt_len);\n#endif /* CONFIG_GTK_OL */\n\n\t\tindex += (CurtPktPageNum * page_size);\n\n\t\t/*Reserve 1 page for AOAC report*/\n\t\trsvd_page_loc->LocAOACReport = *page_num;\n\t\tRTW_INFO(\"LocAOACReport: %d\\n\", rsvd_page_loc->LocAOACReport);\n\t\t*page_num += 1;\n\t\t*total_pkt_len = index + (page_size * 1);\n\t\tRSVD_PAGE_CFG(\"WOW-AOAC\", 1, *page_num, *total_pkt_len);\n\t} else {\n#ifdef CONFIG_PNO_SUPPORT\n\t\tif (pwrctl->wowlan_in_resume == _FALSE &&\n\t\t    pwrctl->pno_inited == _TRUE) {\n\n\t\t\t/* Broadcast Probe Request */\n\t\t\trsvd_page_loc->LocProbePacket = *page_num;\n\n\t\t\tRTW_INFO(\"loc_probe_req: %d\\n\",\n\t\t\t\t rsvd_page_loc->LocProbePacket);\n\n\t\t\trtw_hal_construct_ProbeReq(\n\t\t\t\tadapter,\n\t\t\t\t&pframe[index],\n\t\t\t\t&ProbeReqLength,\n\t\t\t\tNULL);\n\n\t\t\trtw_hal_fill_fake_txdesc(adapter,\n\t\t\t\t\t\t &pframe[index - tx_desc],\n\t\t\t\t ProbeReqLength, _FALSE, _FALSE, _FALSE);\n\n\t\t\tCurtPktPageNum =\n\t\t\t\t(u8)PageNum(tx_desc + ProbeReqLength, page_size);\n\n\t\t\t*page_num += CurtPktPageNum;\n\n\t\t\tindex += (CurtPktPageNum * page_size);\n\t\t\tRSVD_PAGE_CFG(\"WOW-ProbeReq\", CurtPktPageNum, *page_num, 0);\n\n\t\t\t/* Hidden SSID Probe Request */\n\t\t\tssid_num = pwrctl->pnlo_info->hidden_ssid_num;\n\n\t\t\tfor (pno_index = 0 ; pno_index < ssid_num ; pno_index++) {\n\t\t\t\tpwrctl->pnlo_info->loc_probe_req[pno_index] =\n\t\t\t\t\t*page_num;\n\n\t\t\t\trtw_hal_construct_ProbeReq(\n\t\t\t\t\tadapter,\n\t\t\t\t\t&pframe[index],\n\t\t\t\t\t&ProbeReqLength,\n\t\t\t\t\t&pwrctl->pno_ssid_list->node[pno_index]);\n\n\t\t\t\trtw_hal_fill_fake_txdesc(adapter,\n\t\t\t\t\t\t &pframe[index - tx_desc],\n\t\t\t\t\tProbeReqLength, _FALSE, _FALSE, _FALSE);\n\n\t\t\t\tCurtPktPageNum =\n\t\t\t\t\t(u8)PageNum(tx_desc + ProbeReqLength, page_size);\n\n\t\t\t\t*page_num += CurtPktPageNum;\n\n\t\t\t\tindex += (CurtPktPageNum * page_size);\n\t\t\t\tRSVD_PAGE_CFG(\"WOW-ProbeReq\", CurtPktPageNum, *page_num, 0);\n\t\t\t}\n\n\t\t\t/* PNO INFO Page */\n\t\t\trsvd_page_loc->LocPNOInfo = *page_num;\n\t\t\tRTW_INFO(\"LocPNOInfo: %d\\n\", rsvd_page_loc->LocPNOInfo);\n\t\t\trtw_hal_construct_PNO_info(adapter,\n\t\t\t\t\t\t   &pframe[index - tx_desc],\n\t\t\t\t\t\t   &PNOLength);\n\n\t\t\tCurtPktPageNum = (u8)PageNum(PNOLength, page_size);\n\t\t\t*page_num += CurtPktPageNum;\n\t\t\tindex += (CurtPktPageNum * page_size);\n\t\t\tRSVD_PAGE_CFG(\"WOW-PNOInfo\", CurtPktPageNum, *page_num, 0);\n\n\t\t\t/* Scan Info Page */\n\t\t\trsvd_page_loc->LocScanInfo = *page_num;\n\t\t\tRTW_INFO(\"LocScanInfo: %d\\n\", rsvd_page_loc->LocScanInfo);\n\t\t\trtw_hal_construct_scan_info(adapter,\n\t\t\t\t\t\t    &pframe[index - tx_desc],\n\t\t\t\t\t\t    &ScanInfoLength);\n\n\t\t\tCurtPktPageNum = (u8)PageNum(ScanInfoLength, page_size);\n\t\t\t*page_num += CurtPktPageNum;\n\t\t\t*total_pkt_len = index + ScanInfoLength;\n\t\t\tindex += (CurtPktPageNum * page_size);\n\t\t\tRSVD_PAGE_CFG(\"WOW-ScanInfo\", CurtPktPageNum, *page_num, *total_pkt_len);\n\t\t}\n#endif /* CONFIG_PNO_SUPPORT */\n\t}\n}\n\nstatic void rtw_hal_gate_bb(_adapter *adapter, bool stop)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\tu8 i = 0, val8 = 0, empty = _FAIL;\n\tu16 val16 = 0;\n\n\tif (stop) {\n\t\t/* checking TX queue status */\n\t\tfor (i = 0 ; i < 5 ; i++) {\n\t\t\trtw_hal_get_hwreg(adapter, HW_VAR_CHK_MGQ_CPU_EMPTY, &empty);\n\t\t\tif (empty) {\n\t\t\t\tbreak;\n\t\t\t} else {\n\t\t\t\tRTW_WARN(\"%s: MGQ_CPU is busy(%d)!\\n\",\n\t\t\t\t\t __func__, i);\n\t\t\t\trtw_mdelay_os(10);\n\t\t\t}\n\t\t}\n\n\t\tif (val8 == 5)\n\t\t\tRTW_ERR(\"%s: Polling MGQ_CPU empty fail!\\n\", __func__);\n\n\t\t/* Pause TX*/\n\t\tpwrpriv->wowlan_txpause_status = rtw_read8(adapter, REG_TXPAUSE);\n\t\trtw_write8(adapter, REG_TXPAUSE, 0xff);\n\t\tval8 = rtw_read8(adapter, REG_SYS_FUNC_EN);\n\t\tval8 &= ~BIT(0);\n\t\trtw_write8(adapter, REG_SYS_FUNC_EN, val8);\n\t\tRTW_INFO(\"%s: BB gated: 0x%02x, store TXPAUSE: %02x\\n\",\n\t\t\t __func__,\n\t\t\t rtw_read8(adapter, REG_SYS_FUNC_EN),\n\t\t\t pwrpriv->wowlan_txpause_status);\n\t} else {\n\t\tval8 = rtw_read8(adapter, REG_SYS_FUNC_EN);\n\t\tval8 |= BIT(0);\n\t\trtw_write8(adapter, REG_SYS_FUNC_EN, val8);\n\t\tRTW_INFO(\"%s: BB release: 0x%02x, recover TXPAUSE:%02x\\n\",\n\t\t\t __func__, rtw_read8(adapter, REG_SYS_FUNC_EN),\n\t\t\t pwrpriv->wowlan_txpause_status);\n\t\t/* release TX*/\n\t\trtw_write8(adapter, REG_TXPAUSE, pwrpriv->wowlan_txpause_status);\n\t}\n}\n\nstatic u8 rtw_hal_wow_pattern_generate(_adapter *adapter, u8 idx, struct rtl_wow_pattern *pwow_pattern)\n{\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);\n\t u8 *pattern;\n\t u8 len = 0;\n\t u8 *mask;\n\n\tu8 mask_hw[MAX_WKFM_SIZE] = {0};\n\tu8 content[MAX_WKFM_PATTERN_SIZE] = {0};\n\tu8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tu8 multicast_addr1[2] = {0x33, 0x33};\n\tu8 multicast_addr2[3] = {0x01, 0x00, 0x5e};\n\tu8 mask_len = 0;\n\tu8 mac_addr[ETH_ALEN] = {0};\n\tu16 count = 0;\n\tint i, j;\n\n\tif (pwrctl->wowlan_pattern_idx > MAX_WKFM_CAM_NUM) {\n\t\tRTW_INFO(\"%s pattern_idx is more than MAX_FMC_NUM: %d\\n\",\n\t\t\t __func__, MAX_WKFM_CAM_NUM);\n\t\treturn _FAIL;\n\t}\n\n\tpattern = pwrctl->patterns[idx].content;\n\tlen = pwrctl->patterns[idx].len;\n\tmask = pwrctl->patterns[idx].mask;\n\n\t_rtw_memcpy(mac_addr, adapter_mac_addr(adapter), ETH_ALEN);\n\t_rtw_memset(pwow_pattern, 0, sizeof(struct rtl_wow_pattern));\n\n\tmask_len = DIV_ROUND_UP(len, 8);\n\n\t/* 1. setup A1 table */\n\tif (memcmp(pattern, broadcast_addr, ETH_ALEN) == 0)\n\t\tpwow_pattern->type = PATTERN_BROADCAST;\n\telse if (memcmp(pattern, multicast_addr1, 2) == 0)\n\t\tpwow_pattern->type = PATTERN_MULTICAST;\n\telse if (memcmp(pattern, multicast_addr2, 3) == 0)\n\t\tpwow_pattern->type = PATTERN_MULTICAST;\n\telse if (memcmp(pattern, mac_addr, ETH_ALEN) == 0)\n\t\tpwow_pattern->type = PATTERN_UNICAST;\n\telse\n\t\tpwow_pattern->type = PATTERN_INVALID;\n\n\t/* translate mask from os to mask for hw */\n\n\t/******************************************************************************\n\t * pattern from OS uses 'ethenet frame', like this:\n\n\t\t|    6   |    6   |   2  |     20    |  Variable  |  4  |\n\t\t|--------+--------+------+-----------+------------+-----|\n\t\t|    802.3 Mac Header    | IP Header | TCP Packet | FCS |\n\t\t|   DA   |   SA   | Type |\n\n\t * BUT, packet catched by our HW is in '802.11 frame', begin from LLC,\n\n\t\t|     24 or 30      |    6   |   2  |     20    |  Variable  |  4  |\n\t\t|-------------------+--------+------+-----------+------------+-----|\n\t\t| 802.11 MAC Header |       LLC     | IP Header | TCP Packet | FCS |\n\t\t\t\t    | Others | Tpye |\n\n\t * Therefore, we need translate mask_from_OS to mask_to_hw.\n\t * We should left-shift mask by 6 bits, then set the new bit[0~5] = 0,\n\t * because new mask[0~5] means 'SA', but our HW packet begins from LLC,\n\t * bit[0~5] corresponds to first 6 Bytes in LLC, they just don't match.\n\t ******************************************************************************/\n\t/* Shift 6 bits */\n\tfor (i = 0; i < mask_len - 1; i++) {\n\t\tmask_hw[i] = mask[i] >> 6;\n\t\tmask_hw[i] |= (mask[i + 1] & 0x3F) << 2;\n\t}\n\n\tmask_hw[i] = (mask[i] >> 6) & 0x3F;\n\t/* Set bit 0-5 to zero */\n\tmask_hw[0] &= 0xC0;\n\n\tfor (i = 0; i < (MAX_WKFM_SIZE / 4); i++) {\n\t\tpwow_pattern->mask[i] = mask_hw[i * 4];\n\t\tpwow_pattern->mask[i] |= (mask_hw[i * 4 + 1] << 8);\n\t\tpwow_pattern->mask[i] |= (mask_hw[i * 4 + 2] << 16);\n\t\tpwow_pattern->mask[i] |= (mask_hw[i * 4 + 3] << 24);\n\t}\n\n\t/* To get the wake up pattern from the mask.\n\t * We do not count first 12 bits which means\n\t * DA[6] and SA[6] in the pattern to match HW design. */\n\tcount = 0;\n\tfor (i = 12; i < len; i++) {\n\t\tif ((mask[i / 8] >> (i % 8)) & 0x01) {\n\t\t\tcontent[count] = pattern[i];\n\t\t\tcount++;\n\t\t}\n\t}\n\n\tpwow_pattern->crc = rtw_calc_crc(content, count);\n\n\tif (pwow_pattern->crc != 0) {\n\t\tif (pwow_pattern->type == PATTERN_INVALID)\n\t\t\tpwow_pattern->type = PATTERN_VALID;\n\t}\n\n\treturn _SUCCESS;\n}\n\n#ifndef CONFIG_WOW_PATTERN_HW_CAM\nstatic void rtw_hal_reset_mac_rx(_adapter *adapter)\n{\n\tu8 val8 = 0;\n\t/* Set REG_CR bit1, bit3, bit7 to 0*/\n\tval8 = rtw_read8(adapter, REG_CR);\n\tval8 &= 0x75;\n\trtw_write8(adapter, REG_CR, val8);\n\tval8 = rtw_read8(adapter, REG_CR);\n\t/* Set REG_CR bit1, bit3, bit7 to 1*/\n\tval8 |= 0x8a;\n\trtw_write8(adapter, REG_CR, val8);\n\tRTW_INFO(\"0x%04x: %02x\\n\", REG_CR, rtw_read8(adapter, REG_CR));\n}\nstatic void rtw_hal_set_wow_rxff_boundary(_adapter *adapter, bool wow_mode)\n{\n\tu8 val8 = 0;\n\tu16 rxff_bndy = 0;\n\tu32 rx_dma_buff_sz = 0;\n\n\tval8 = rtw_read8(adapter, REG_FIFOPAGE + 3);\n\tif (val8 != 0)\n\t\tRTW_INFO(\"%s:[%04x]some PKTs in TXPKTBUF\\n\",\n\t\t\t __func__, (REG_FIFOPAGE + 3));\n\n\trtw_hal_reset_mac_rx(adapter);\n\n\tif (wow_mode) {\n\t\trtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,\n\t\t\t\t    (u8 *)&rx_dma_buff_sz);\n\t\trxff_bndy = rx_dma_buff_sz - 1;\n\n\t\trtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);\n\t\tRTW_INFO(\"%s: wow mode, 0x%04x: 0x%04x\\n\", __func__,\n\t\t\t REG_TRXFF_BNDY + 2,\n\t\t\t rtw_read16(adapter, (REG_TRXFF_BNDY + 2)));\n\t} else {\n\t\trtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ,\n\t\t\t\t    (u8 *)&rx_dma_buff_sz);\n\t\trxff_bndy = rx_dma_buff_sz - 1;\n\t\trtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);\n\t\tRTW_INFO(\"%s: normal mode, 0x%04x: 0x%04x\\n\", __func__,\n\t\t\t REG_TRXFF_BNDY + 2,\n\t\t\t rtw_read16(adapter, (REG_TRXFF_BNDY + 2)));\n\t}\n}\n\nbool rtw_read_from_frame_mask(_adapter *adapter, u8 idx)\n{\n\tu32 data_l = 0, data_h = 0, rx_dma_buff_sz = 0, page_sz = 0;\n\tu16 offset, rx_buf_ptr = 0;\n\tu16 cam_start_offset = 0;\n\tu16 ctrl_l = 0, ctrl_h = 0;\n\tu8 count = 0, tmp = 0;\n\tint i = 0;\n\tbool res = _TRUE;\n\n\tif (idx > MAX_WKFM_CAM_NUM) {\n\t\tRTW_INFO(\"[Error]: %s, pattern index is out of range\\n\",\n\t\t\t __func__);\n\t\treturn _FALSE;\n\t}\n\n\trtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,\n\t\t\t    (u8 *)&rx_dma_buff_sz);\n\n\tif (rx_dma_buff_sz == 0) {\n\t\tRTW_INFO(\"[Error]: %s, rx_dma_buff_sz is 0!!\\n\", __func__);\n\t\treturn _FALSE;\n\t}\n\n\trtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz);\n\n\tif (page_sz == 0) {\n\t\tRTW_INFO(\"[Error]: %s, page_sz is 0!!\\n\", __func__);\n\t\treturn _FALSE;\n\t}\n\n\toffset = (u16)PageNum(rx_dma_buff_sz, page_sz);\n\tcam_start_offset = offset * page_sz;\n\n\tctrl_l = 0x0;\n\tctrl_h = 0x0;\n\n\t/* Enable RX packet buffer access */\n\trtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);\n\n\t/* Read the WKFM CAM */\n\tfor (i = 0; i < (WKFMCAM_ADDR_NUM / 2); i++) {\n\t\t/*\n\t\t * Set Rx packet buffer offset.\n\t\t * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer.\n\t\t * CAM start offset (unit: 1 byte) =  Index*WKFMCAM_SIZE\n\t\t * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8\n\t\t * * Index: The index of the wake up frame mask\n\t\t * * WKFMCAM_SIZE: the total size of one WKFM CAM\n\t\t * * per entry offset of a WKFM CAM: Addr i * 4 bytes\n\t\t */\n\t\trx_buf_ptr =\n\t\t\t(cam_start_offset + idx * WKFMCAM_SIZE + i * 8) >> 3;\n\t\trtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr);\n\n\t\trtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);\n\t\tdata_l = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);\n\t\tdata_h = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);\n\n\t\tRTW_INFO(\"[%d]: %08x %08x\\n\", i, data_h, data_l);\n\n\t\tcount = 0;\n\n\t\tdo {\n\t\t\ttmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL);\n\t\t\trtw_udelay_os(2);\n\t\t\tcount++;\n\t\t} while (!tmp && count < 100);\n\n\t\tif (count >= 100) {\n\t\t\tRTW_INFO(\"%s count:%d\\n\", __func__, count);\n\t\t\tres = _FALSE;\n\t\t}\n\t}\n\n\t/* Disable RX packet buffer access */\n\trtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL,\n\t\t   DISABLE_TRXPKT_BUF_ACCESS);\n\treturn res;\n}\n\nbool rtw_write_to_frame_mask(_adapter *adapter, u8 idx,\n\t\t\t     struct  rtl_wow_pattern *context)\n{\n\tu32 data = 0, rx_dma_buff_sz = 0, page_sz = 0;\n\tu16 offset, rx_buf_ptr = 0;\n\tu16 cam_start_offset = 0;\n\tu16 ctrl_l = 0, ctrl_h = 0;\n\tu8 count = 0, tmp = 0;\n\tint res = 0, i = 0;\n\n\tif (idx > MAX_WKFM_CAM_NUM) {\n\t\tRTW_INFO(\"[Error]: %s, pattern index is out of range\\n\",\n\t\t\t __func__);\n\t\treturn _FALSE;\n\t}\n\n\trtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,\n\t\t\t    (u8 *)&rx_dma_buff_sz);\n\n\tif (rx_dma_buff_sz == 0) {\n\t\tRTW_INFO(\"[Error]: %s, rx_dma_buff_sz is 0!!\\n\", __func__);\n\t\treturn _FALSE;\n\t}\n\n\trtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz);\n\n\tif (page_sz == 0) {\n\t\tRTW_INFO(\"[Error]: %s, page_sz is 0!!\\n\", __func__);\n\t\treturn _FALSE;\n\t}\n\n\toffset = (u16)PageNum(rx_dma_buff_sz, page_sz);\n\n\tcam_start_offset = offset * page_sz;\n\n\tif (IS_HARDWARE_TYPE_8188E(adapter)) {\n\t\tctrl_l = 0x0001;\n\t\tctrl_h = 0x0001;\n\t} else {\n\t\tctrl_l = 0x0f01;\n\t\tctrl_h = 0xf001;\n\t}\n\n\t/* Enable RX packet buffer access */\n\trtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);\n\n\t/* Write the WKFM CAM */\n\tfor (i = 0; i < WKFMCAM_ADDR_NUM; i++) {\n\t\t/*\n\t\t * Set Rx packet buffer offset.\n\t\t * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer.\n\t\t * CAM start offset (unit: 1 byte) =  Index*WKFMCAM_SIZE\n\t\t * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8\n\t\t * * Index: The index of the wake up frame mask\n\t\t * * WKFMCAM_SIZE: the total size of one WKFM CAM\n\t\t * * per entry offset of a WKFM CAM: Addr i * 4 bytes\n\t\t */\n\t\trx_buf_ptr =\n\t\t\t(cam_start_offset + idx * WKFMCAM_SIZE + i * 4) >> 3;\n\t\trtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr);\n\n\t\tif (i == 0) {\n\t\t\tif (context->type == PATTERN_VALID)\n\t\t\t\tdata = BIT(31);\n\t\t\telse if (context->type == PATTERN_BROADCAST)\n\t\t\t\tdata = BIT(31) | BIT(26);\n\t\t\telse if (context->type == PATTERN_MULTICAST)\n\t\t\t\tdata = BIT(31) | BIT(25);\n\t\t\telse if (context->type == PATTERN_UNICAST)\n\t\t\t\tdata = BIT(31) | BIT(24);\n\n\t\t\tif (context->crc != 0)\n\t\t\t\tdata |= context->crc;\n\n\t\t\trtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data);\n\t\t\trtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);\n\t\t} else if (i == 1) {\n\t\t\tdata = 0;\n\t\t\trtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data);\n\t\t\trtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h);\n\t\t} else if (i == 2 || i == 4) {\n\t\t\tdata = context->mask[i - 2];\n\t\t\trtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data);\n\t\t\t/* write to RX packet buffer*/\n\t\t\trtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);\n\t\t} else if (i == 3 || i == 5) {\n\t\t\tdata = context->mask[i - 2];\n\t\t\trtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data);\n\t\t\t/* write to RX packet buffer*/\n\t\t\trtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h);\n\t\t}\n\n\t\tcount = 0;\n\t\tdo {\n\t\t\ttmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL);\n\t\t\trtw_udelay_os(2);\n\t\t\tcount++;\n\t\t} while (tmp && count < 100);\n\n\t\tif (count >= 100)\n\t\t\tres = _FALSE;\n\t\telse\n\t\t\tres = _TRUE;\n\t}\n\n\t/* Disable RX packet buffer access */\n\trtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL,\n\t\t   DISABLE_TRXPKT_BUF_ACCESS);\n\n\treturn res;\n}\nvoid rtw_clean_pattern(_adapter *adapter)\n{\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);\n\tstruct rtl_wow_pattern zero_pattern;\n\tint i = 0;\n\n\t_rtw_memset(&zero_pattern, 0, sizeof(struct rtl_wow_pattern));\n\n\tzero_pattern.type = PATTERN_INVALID;\n\n\tfor (i = 0; i < MAX_WKFM_CAM_NUM; i++)\n\t\trtw_write_to_frame_mask(adapter, i, &zero_pattern);\n\n\trtw_write8(adapter, REG_WKFMCAM_NUM, 0);\n}\n#if 0\nstatic int rtw_hal_set_pattern(_adapter *adapter, u8 *pattern,\n\t\t\t       u8 len, u8 *mask, u8 idx)\n{\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);\n\tstruct mlme_ext_priv *pmlmeext = NULL;\n\tstruct mlme_ext_info *pmlmeinfo = NULL;\n\tstruct rtl_wow_pattern wow_pattern;\n\tu8 mask_hw[MAX_WKFM_SIZE] = {0};\n\tu8 content[MAX_WKFM_PATTERN_SIZE] = {0};\n\tu8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tu8 multicast_addr1[2] = {0x33, 0x33};\n\tu8 multicast_addr2[3] = {0x01, 0x00, 0x5e};\n\tu8 res = _FALSE, index = 0, mask_len = 0;\n\tu8 mac_addr[ETH_ALEN] = {0};\n\tu16 count = 0;\n\tint i, j;\n\n\tif (pwrctl->wowlan_pattern_idx > MAX_WKFM_CAM_NUM) {\n\t\tRTW_INFO(\"%s pattern_idx is more than MAX_FMC_NUM: %d\\n\",\n\t\t\t __func__, MAX_WKFM_CAM_NUM);\n\t\treturn _FALSE;\n\t}\n\n\tpmlmeext = &adapter->mlmeextpriv;\n\tpmlmeinfo = &pmlmeext->mlmext_info;\n\t_rtw_memcpy(mac_addr, adapter_mac_addr(adapter), ETH_ALEN);\n\t_rtw_memset(&wow_pattern, 0, sizeof(struct rtl_wow_pattern));\n\n\tmask_len = DIV_ROUND_UP(len, 8);\n\n\t/* 1. setup A1 table */\n\tif (memcmp(pattern, broadcast_addr, ETH_ALEN) == 0)\n\t\twow_pattern.type = PATTERN_BROADCAST;\n\telse if (memcmp(pattern, multicast_addr1, 2) == 0)\n\t\twow_pattern.type = PATTERN_MULTICAST;\n\telse if (memcmp(pattern, multicast_addr2, 3) == 0)\n\t\twow_pattern.type = PATTERN_MULTICAST;\n\telse if (memcmp(pattern, mac_addr, ETH_ALEN) == 0)\n\t\twow_pattern.type = PATTERN_UNICAST;\n\telse\n\t\twow_pattern.type = PATTERN_INVALID;\n\n\t/* translate mask from os to mask for hw */\n\n/******************************************************************************\n * pattern from OS uses 'ethenet frame', like this:\n\n\t|    6   |    6   |   2  |     20    |  Variable  |  4  |\n\t|--------+--------+------+-----------+------------+-----|\n\t|    802.3 Mac Header    | IP Header | TCP Packet | FCS |\n\t|   DA   |   SA   | Type |\n\n * BUT, packet catched by our HW is in '802.11 frame', begin from LLC,\n\n\t|     24 or 30      |    6   |   2  |     20    |  Variable  |  4  |\n\t|-------------------+--------+------+-----------+------------+-----|\n\t| 802.11 MAC Header |       LLC     | IP Header | TCP Packet | FCS |\n\t\t\t    | Others | Tpye |\n\n * Therefore, we need translate mask_from_OS to mask_to_hw.\n * We should left-shift mask by 6 bits, then set the new bit[0~5] = 0,\n * because new mask[0~5] means 'SA', but our HW packet begins from LLC,\n * bit[0~5] corresponds to first 6 Bytes in LLC, they just don't match.\n ******************************************************************************/\n\t/* Shift 6 bits */\n\tfor (i = 0; i < mask_len - 1; i++) {\n\t\tmask_hw[i] = mask[i] >> 6;\n\t\tmask_hw[i] |= (mask[i + 1] & 0x3F) << 2;\n\t}\n\n\tmask_hw[i] = (mask[i] >> 6) & 0x3F;\n\t/* Set bit 0-5 to zero */\n\tmask_hw[0] &= 0xC0;\n\n\tfor (i = 0; i < (MAX_WKFM_SIZE / 4); i++) {\n\t\twow_pattern.mask[i] = mask_hw[i * 4];\n\t\twow_pattern.mask[i] |= (mask_hw[i * 4 + 1] << 8);\n\t\twow_pattern.mask[i] |= (mask_hw[i * 4 + 2] << 16);\n\t\twow_pattern.mask[i] |= (mask_hw[i * 4 + 3] << 24);\n\t}\n\n\t/* To get the wake up pattern from the mask.\n\t * We do not count first 12 bits which means\n\t * DA[6] and SA[6] in the pattern to match HW design. */\n\tcount = 0;\n\tfor (i = 12; i < len; i++) {\n\t\tif ((mask[i / 8] >> (i % 8)) & 0x01) {\n\t\t\tcontent[count] = pattern[i];\n\t\t\tcount++;\n\t\t}\n\t}\n\n\twow_pattern.crc = rtw_calc_crc(content, count);\n\n\tif (wow_pattern.crc != 0) {\n\t\tif (wow_pattern.type == PATTERN_INVALID)\n\t\t\twow_pattern.type = PATTERN_VALID;\n\t}\n\n\tindex = idx;\n\n\tif (!pwrctl->bInSuspend)\n\t\tindex += 2;\n\n\t/* write pattern */\n\tres = rtw_write_to_frame_mask(adapter, index, &wow_pattern);\n\n\tif (res == _FALSE)\n\t\tRTW_INFO(\"%s: ERROR!! idx: %d write_to_frame_mask_cam fail\\n\",\n\t\t\t __func__, idx);\n\n\treturn res;\n}\n#endif\n\nvoid rtw_fill_pattern(_adapter *adapter)\n{\n\tint i = 0, total = 0, index;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\tstruct rtl_wow_pattern wow_pattern;\n\n\ttotal = pwrpriv->wowlan_pattern_idx;\n\n\tif (total > MAX_WKFM_CAM_NUM)\n\t\ttotal = MAX_WKFM_CAM_NUM;\n\n\tfor (i = 0 ; i < total ; i++) {\n\t\tif (_SUCCESS == rtw_hal_wow_pattern_generate(adapter, i, &wow_pattern)) {\n\n\t\t\tindex = i;\n\t\t\tif (!pwrpriv->bInSuspend)\n\t\t\t\tindex += 2;\n\n\t\t\tif (rtw_write_to_frame_mask(adapter, index, &wow_pattern) == _FALSE)\n\t\t\t\tRTW_INFO(\"%s: ERROR!! idx: %d write_to_frame_mask_cam fail\\n\", __func__, i);\n\t\t}\n\n\t}\n\trtw_write8(adapter, REG_WKFMCAM_NUM, total);\n\n}\n\n#else /*CONFIG_WOW_PATTERN_HW_CAM*/\n\n#define WOW_CAM_ACCESS_TIMEOUT_MS\t200\n#define WOW_VALID_BIT\tBIT31\n#define WOW_BC_BIT\t\tBIT26\n#define WOW_MC_BIT\t\tBIT25\n#define WOW_UC_BIT\t\tBIT24\n\nstatic u32 _rtw_wow_pattern_read_cam(_adapter *adapter, u8 addr)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\t_mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;\n\n\tu32 rdata = 0;\n\tu32 cnt = 0;\n\tsystime start = 0;\n\tu8 timeout = 0;\n\tu8 rst = _FALSE;\n\n\t_enter_critical_mutex(mutex, NULL);\n\n\trtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_ADDR_V2(addr));\n\n\tstart = rtw_get_current_time();\n\twhile (1) {\n\t\tif (rtw_is_surprise_removed(adapter))\n\t\t\tbreak;\n\n\t\tcnt++;\n\t\tif (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1)) {\n\t\t\trst = _SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t\tif (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {\n\t\t\ttimeout = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\trdata = rtw_read32(adapter, REG_WKFMCAM_RWD);\n\n\t_exit_critical_mutex(mutex, NULL);\n\n\t/*RTW_INFO(\"%s ==> addr:0x%02x , rdata:0x%08x\\n\", __func__, addr, rdata);*/\n\n\tif (timeout)\n\t\tRTW_ERR(FUNC_ADPT_FMT\" failed due to polling timeout\\n\", FUNC_ADPT_ARG(adapter));\n\n\treturn rdata;\n}\nvoid rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct  rtl_wow_pattern *context)\n{\n\tint i;\n\tu32 rdata;\n\n\t_rtw_memset(context, 0, sizeof(struct  rtl_wow_pattern));\n\n\tfor (i = 4; i >= 0; i--) {\n\t\trdata = _rtw_wow_pattern_read_cam(adapter, (id << 3) | i);\n\n\t\tswitch (i) {\n\t\tcase 4:\n\t\t\tif (rdata & WOW_BC_BIT)\n\t\t\t\tcontext->type = PATTERN_BROADCAST;\n\t\t\telse if (rdata & WOW_MC_BIT)\n\t\t\t\tcontext->type = PATTERN_MULTICAST;\n\t\t\telse if (rdata & WOW_UC_BIT)\n\t\t\t\tcontext->type = PATTERN_UNICAST;\n\t\t\telse\n\t\t\t\tcontext->type = PATTERN_INVALID;\n\n\t\t\tcontext->crc = rdata & 0xFFFF;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t_rtw_memcpy(&context->mask[i], (u8 *)(&rdata), 4);\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\nstatic void _rtw_wow_pattern_write_cam(_adapter *adapter, u8 addr, u32 wdata)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\t_mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;\n\tu32 cnt = 0;\n\tsystime start = 0, end = 0;\n\tu8 timeout = 0;\n\n\t/*RTW_INFO(\"%s ==> addr:0x%02x , wdata:0x%08x\\n\", __func__, addr, wdata);*/\n\t_enter_critical_mutex(mutex, NULL);\n\n\trtw_write32(adapter, REG_WKFMCAM_RWD, wdata);\n\trtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_WE | BIT_WKFCAM_ADDR_V2(addr));\n\n\tstart = rtw_get_current_time();\n\twhile (1) {\n\t\tif (rtw_is_surprise_removed(adapter))\n\t\t\tbreak;\n\n\t\tcnt++;\n\t\tif (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1))\n\t\t\tbreak;\n\n\t\tif (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {\n\t\t\ttimeout = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\tend = rtw_get_current_time();\n\n\t_exit_critical_mutex(mutex, NULL);\n\n\tif (timeout) {\n\t\tRTW_ERR(FUNC_ADPT_FMT\" addr:0x%02x, wdata:0x%08x, to:%u, polling:%u, %d ms\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), addr, wdata, timeout, cnt, rtw_get_time_interval_ms(start, end));\n\t}\n}\n\nvoid rtw_wow_pattern_write_cam_ent(_adapter *adapter, u8 id, struct  rtl_wow_pattern *context)\n{\n\tint j;\n\tu8 addr;\n\tu32 wdata = 0;\n\n\tfor (j = 4; j >= 0; j--) {\n\t\tswitch (j) {\n\t\tcase 4:\n\t\t\twdata = context->crc;\n\n\t\t\tif (PATTERN_BROADCAST == context->type)\n\t\t\t\twdata |= WOW_BC_BIT;\n\t\t\tif (PATTERN_MULTICAST == context->type)\n\t\t\t\twdata |= WOW_MC_BIT;\n\t\t\tif (PATTERN_UNICAST == context->type)\n\t\t\t\twdata |= WOW_UC_BIT;\n\t\t\tif (PATTERN_INVALID != context->type)\n\t\t\t\twdata |= WOW_VALID_BIT;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\twdata = context->mask[j];\n\t\t\tbreak;\n\t\t}\n\n\t\taddr = (id << 3) + j;\n\n\t\t_rtw_wow_pattern_write_cam(adapter, addr, wdata);\n\t}\n}\n\nstatic u8 _rtw_wow_pattern_clean_cam(_adapter *adapter)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\t_mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;\n\tu32 cnt = 0;\n\tsystime start = 0;\n\tu8 timeout = 0;\n\tu8 rst = _FAIL;\n\n\t_enter_critical_mutex(mutex, NULL);\n\trtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_CLR_V1);\n\n\tstart = rtw_get_current_time();\n\twhile (1) {\n\t\tif (rtw_is_surprise_removed(adapter))\n\t\t\tbreak;\n\n\t\tcnt++;\n\t\tif (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1)) {\n\t\t\trst = _SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t\tif (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {\n\t\t\ttimeout = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\t_exit_critical_mutex(mutex, NULL);\n\n\tif (timeout)\n\t\tRTW_ERR(FUNC_ADPT_FMT\" falied ,polling timeout\\n\", FUNC_ADPT_ARG(adapter));\n\n\treturn rst;\n}\n\nvoid rtw_clean_pattern(_adapter *adapter)\n{\n\tif (_FAIL == _rtw_wow_pattern_clean_cam(adapter))\n\t\tRTW_ERR(\"rtw_clean_pattern failed\\n\");\n}\n\nvoid rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx)\n{\n\tint j;\n\n\tRTW_PRINT_SEL(sel, \"=======WOW CAM-ID[%d]=======\\n\", idx);\n\tRTW_PRINT_SEL(sel, \"[WOW CAM] type:%d\\n\", pwow_pattern->type);\n\tRTW_PRINT_SEL(sel, \"[WOW CAM] crc:0x%04x\\n\", pwow_pattern->crc);\n\tfor (j = 0; j < 4; j++)\n\t\tRTW_PRINT_SEL(sel, \"[WOW CAM] Mask:0x%08x\\n\", pwow_pattern->mask[j]);\n}\n\nvoid rtw_fill_pattern(_adapter *adapter)\n{\n\tint i = 0, total = 0;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\tstruct rtl_wow_pattern wow_pattern;\n\n\ttotal = pwrpriv->wowlan_pattern_idx;\n\n\tif (total > MAX_WKFM_CAM_NUM)\n\t\ttotal = MAX_WKFM_CAM_NUM;\n\n\tfor (i = 0 ; i < total ; i++) {\n\t\tif (_SUCCESS == rtw_hal_wow_pattern_generate(adapter, i, &wow_pattern)) {\n\t\t\trtw_dump_wow_pattern(RTW_DBGDUMP, &wow_pattern, i);\n\t\t\trtw_wow_pattern_write_cam_ent(adapter, i, &wow_pattern);\n\t\t}\n\t}\n}\n\n#endif\nvoid rtw_wow_pattern_cam_dump(_adapter *adapter)\n{\n\n#ifndef CONFIG_WOW_PATTERN_HW_CAM\n\tint i;\n\n\tfor (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) {\n\t\tRTW_INFO(\"=======[%d]=======\\n\", i);\n\t\trtw_read_from_frame_mask(adapter, i);\n\t}\n#else\n\tstruct  rtl_wow_pattern context;\n\tint i;\n\n\tfor (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) {\n\t\trtw_wow_pattern_read_cam_ent(adapter, i, &context);\n\t\trtw_dump_wow_pattern(RTW_DBGDUMP, &context, i);\n\t}\n\n#endif\n}\n\n\nstatic void rtw_hal_dl_pattern(_adapter *adapter, u8 mode)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\n\tswitch (mode) {\n\tcase 0:\n\t\trtw_clean_pattern(adapter);\n\t\tRTW_INFO(\"%s: total patterns: %d\\n\", __func__, pwrpriv->wowlan_pattern_idx);\n\t\tbreak;\n\tcase 1:\n\t\trtw_set_default_pattern(adapter);\n\t\trtw_fill_pattern(adapter);\n\t\tRTW_INFO(\"%s: pattern total: %d downloaded\\n\", __func__, pwrpriv->wowlan_pattern_idx);\n\t\tbreak;\n\tcase 2:\n\t\trtw_clean_pattern(adapter);\n\t\trtw_wow_pattern_sw_reset(adapter);\n\t\tRTW_INFO(\"%s: clean patterns\\n\", __func__);\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(\"%s: unknown mode\\n\", __func__);\n\t\tbreak;\n\t}\n}\n\nstatic void rtw_hal_wow_enable(_adapter *adapter)\n{\n\tstruct registry_priv  *registry_par = &adapter->registrypriv;\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);\n\tstruct security_priv *psecuritypriv = &adapter->securitypriv;\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tstruct hal_ops *pHalFunc = &adapter->hal_func;\n\tstruct sta_info *psta = NULL;\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);\n\tint res;\n\tu16 media_status_rpt;\n\tu8 no_wake = 0;\n\t\n#ifdef CONFIG_LPS_PG\n\tu8 lps_pg_hdl_id = 0;\n#endif\n\n\n\n\tif(registry_par->suspend_type == FW_IPS_DISABLE_BBRF &&\n\t!check_fwstate(pmlmepriv, _FW_LINKED))\n\t\tno_wake = 1;\n\n\tRTW_PRINT(FUNC_ADPT_FMT \" WOWLAN_ENABLE\\n\", FUNC_ADPT_ARG(adapter));\n\trtw_hal_gate_bb(adapter, _TRUE);\n#ifdef CONFIG_GTK_OL\n\tif (psecuritypriv->binstallKCK_KEK == _TRUE)\n\t\trtw_hal_fw_sync_cam_id(adapter);\n#endif\n\tif (IS_HARDWARE_TYPE_8723B(adapter))\n\t\trtw_hal_backup_rate(adapter);\n\n\trtw_hal_fw_dl(adapter, _TRUE);\n\tif(no_wake)\n\t\tmedia_status_rpt = RT_MEDIA_DISCONNECT;\n\telse\n\t\tmedia_status_rpt = RT_MEDIA_CONNECT;\n\trtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,\n\t\t\t  (u8 *)&media_status_rpt);\n\n\t/* RX DMA stop */\n\t#if defined(CONFIG_RTL8188E)\n\tif (IS_HARDWARE_TYPE_8188E(adapter))\n\t\trtw_hal_disable_tx_report(adapter);\n\t#endif\n\n\tres = rtw_hal_pause_rx_dma(adapter);\n\tif (res == _FAIL)\n\t\tRTW_PRINT(\"[WARNING] pause RX DMA fail\\n\");\n\n\t#ifndef CONFIG_WOW_PATTERN_HW_CAM\n\t/* Reconfig RX_FF Boundary */\n\trtw_hal_set_wow_rxff_boundary(adapter, _TRUE);\n\t#endif\n\n\t/* redownload wow pattern */\n\tif(!no_wake)\n\t\trtw_hal_dl_pattern(adapter, 1);\n\n\tif (!pwrctl->wowlan_pno_enable) {\n\t\tpsta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));\n\n\t\tif (psta != NULL) {\n\t\t\t#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\t\t\tadapter_to_dvobj(adapter)->dft.port_id = 0xFF;\n\t\t\tadapter_to_dvobj(adapter)->dft.mac_id = 0xFF;\n\t\t\trtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id);\n\t\t\t#endif\n\t\t\tif(!no_wake)\n\t\t\t\trtw_sta_media_status_rpt(adapter, psta, 1);\n\t\t}\n\t}\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t/* Enable CPWM2 only. */\n\tres = rtw_hal_enable_cpwm2(adapter);\n\tif (res == _FAIL)\n\t\tRTW_PRINT(\"[WARNING] enable cpwm2 fail\\n\");\n#endif\n#ifdef CONFIG_GPIO_WAKEUP\n\trtw_hal_switch_gpio_wl_ctrl(adapter, WAKEUP_GPIO_IDX, _TRUE);\n#endif\n\t/* Set WOWLAN H2C command. */\n\tRTW_PRINT(\"Set WOWLan cmd\\n\");\n\trtw_hal_set_fw_wow_related_cmd(adapter, 1);\n\n\tres = rtw_hal_check_wow_ctrl(adapter, _TRUE);\n\n\tif (res == _FALSE)\n\t\tRTW_INFO(\"[Error]%s: set wowlan CMD fail!!\\n\", __func__);\n\n\tpwrctl->wowlan_wake_reason =\n\t\trtw_read8(adapter, REG_WOWLAN_WAKE_REASON);\n\n\tRTW_PRINT(\"wowlan_wake_reason: 0x%02x\\n\",\n\t\t  pwrctl->wowlan_wake_reason);\n#ifdef CONFIG_GTK_OL_DBG\n\tdump_sec_cam(RTW_DBGDUMP, adapter);\n\tdump_sec_cam_cache(RTW_DBGDUMP, adapter);\n#endif\n\n#ifdef CONFIG_LPS_PG\n\tif (pwrctl->lps_level == LPS_PG) {\n\t\tlps_pg_hdl_id = LPS_PG_INFO_CFG;\n\t\trtw_hal_set_hwreg(adapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));\n\t}\n#endif\n\n#ifdef CONFIG_USB_HCI\n\t/* free adapter's resource */\n\trtw_mi_intf_stop(adapter);\n\n#endif\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)\n\t/* Invoid SE0 reset signal during suspending*/\n\trtw_write8(adapter, REG_RSV_CTRL, 0x20);\n\tif (IS_8188F(pHalData->version_id) == FALSE\n\t\t&& IS_8188GTV(pHalData->version_id) == FALSE)\n\t\trtw_write8(adapter, REG_RSV_CTRL, 0x60);\n#endif\n\n\trtw_hal_gate_bb(adapter, _FALSE);\n}\n\n#define DBG_WAKEUP_REASON\n#ifdef DBG_WAKEUP_REASON\nvoid _dbg_wake_up_reason_string(_adapter *adapter, const char *srt_res)\n{\n\tRTW_INFO(ADPT_FMT \"- wake up reason - %s\\n\", ADPT_ARG(adapter), srt_res);\n}\nvoid _dbg_rtw_wake_up_reason(_adapter *adapter, u8 reason)\n{\n\tif (RX_PAIRWISEKEY == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"Rx pairwise key\");\n\telse if (RX_GTK == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"Rx GTK\");\n\telse if (RX_FOURWAY_HANDSHAKE == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"Rx four way handshake\");\n\telse if (RX_DISASSOC == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"Rx disassoc\");\n\telse if (RX_DEAUTH == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"Rx deauth\");\n\telse if (RX_ARP_REQUEST == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"Rx ARP request\");\n\telse if (FW_DECISION_DISCONNECT == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"FW detect disconnect\");\n\telse if (RX_MAGIC_PKT == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"Rx magic packet\");\n\telse if (RX_UNICAST_PKT == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"Rx unicast packet\");\n\telse if (RX_PATTERN_PKT == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"Rx pattern packet\");\n\telse if (RTD3_SSID_MATCH == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"RTD3 SSID match\");\n\telse if (RX_REALWOW_V2_WAKEUP_PKT == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"Rx real WOW V2 wakeup packet\");\n\telse if (RX_REALWOW_V2_ACK_LOST == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"Rx real WOW V2 ack lost\");\n\telse if (ENABLE_FAIL_DMA_IDLE == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"enable fail DMA idle\");\n\telse if (ENABLE_FAIL_DMA_PAUSE == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"enable fail DMA pause\");\n\telse if (AP_OFFLOAD_WAKEUP == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"AP offload wakeup\");\n\telse if (CLK_32K_UNLOCK == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"clk 32k unlock\");\n\telse if (RTIME_FAIL_DMA_IDLE == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"RTIME fail DMA idle\");\n\telse if (CLK_32K_LOCK == reason)\n\t\t_dbg_wake_up_reason_string(adapter, \"clk 32k lock\");\n\telse\n\t\t_dbg_wake_up_reason_string(adapter, \"unknown reasoen\");\n}\n#endif\n\nstatic void rtw_hal_wow_disable(_adapter *adapter)\n{\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);\n\tstruct security_priv *psecuritypriv = &adapter->securitypriv;\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tstruct hal_ops *pHalFunc = &adapter->hal_func;\n\tstruct sta_info *psta = NULL;\n\tstruct registry_priv  *registry_par = &adapter->registrypriv;\n\tint res;\n\tu16 media_status_rpt;\n\tu8 val8;\n\n\tRTW_PRINT(\"%s, WOWLAN_DISABLE\\n\", __func__);\n\t\n\tif(registry_par->suspend_type == FW_IPS_DISABLE_BBRF && !check_fwstate(pmlmepriv, _FW_LINKED)) {\n\t\tRTW_INFO(\"FW_IPS_DISABLE_BBRF resume\\n\");\n\t\treturn;\n\t}\n\t\n\tif (!pwrctl->wowlan_pno_enable) {\n\t\tpsta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));\n\t\tif (psta != NULL)\n\t\t\trtw_sta_media_status_rpt(adapter, psta, 0);\n\t\telse\n\t\t\tRTW_INFO(\"%s: psta is null\\n\", __func__);\n\t}\n\n\tif (0) {\n\t\tRTW_INFO(\"0x630:0x%02x\\n\", rtw_read8(adapter, 0x630));\n\t\tRTW_INFO(\"0x631:0x%02x\\n\", rtw_read8(adapter, 0x631));\n\t\tRTW_INFO(\"0x634:0x%02x\\n\", rtw_read8(adapter, 0x634));\n\t\tRTW_INFO(\"0x1c7:0x%02x\\n\", rtw_read8(adapter, 0x1c7));\n\t}\n\n\tpwrctl->wowlan_wake_reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);\n\n\tRTW_PRINT(\"wakeup_reason: 0x%02x\\n\",\n\t\t  pwrctl->wowlan_wake_reason);\n\t#ifdef DBG_WAKEUP_REASON\n\t_dbg_rtw_wake_up_reason(adapter, pwrctl->wowlan_wake_reason);\n\t#endif\n\n\trtw_hal_set_fw_wow_related_cmd(adapter, 0);\n\n\tres = rtw_hal_check_wow_ctrl(adapter, _FALSE);\n\n\tif (res == _FALSE) {\n\t\tRTW_INFO(\"[Error]%s: disable WOW cmd fail\\n!!\", __func__);\n\t\trtw_hal_force_enable_rxdma(adapter);\n\t}\n\n\trtw_hal_gate_bb(adapter, _TRUE);\n\n\tres = rtw_hal_pause_rx_dma(adapter);\n\tif (res == _FAIL)\n\t\tRTW_PRINT(\"[WARNING] pause RX DMA fail\\n\");\n\n\t/* clean HW pattern match */\n\trtw_hal_dl_pattern(adapter, 0);\n\n\t#ifndef CONFIG_WOW_PATTERN_HW_CAM\n\t/* config RXFF boundary to original */\n\trtw_hal_set_wow_rxff_boundary(adapter, _FALSE);\n\t#endif\n\trtw_hal_release_rx_dma(adapter);\n\n\t#if defined(CONFIG_RTL8188E)\n\tif (IS_HARDWARE_TYPE_8188E(adapter))\n\t\trtw_hal_enable_tx_report(adapter);\n\t#endif\n\n\tif ((pwrctl->wowlan_wake_reason != RX_DISASSOC) &&\n\t\t(pwrctl->wowlan_wake_reason != RX_DEAUTH) &&\n\t\t(pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT)) {\n\t\trtw_hal_get_aoac_rpt(adapter);\n\t\trtw_hal_update_sw_security_info(adapter);\n\t}\n\n\trtw_hal_fw_dl(adapter, _FALSE);\n\n#ifdef CONFIG_GPIO_WAKEUP\n\n#ifdef CONFIG_RTW_ONE_PIN_GPIO\n\trtw_hal_set_input_gpio(adapter, WAKEUP_GPIO_IDX);\n#else\n#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE\n\tif (pwrctl->is_high_active == 0)\n\t\trtw_hal_set_input_gpio(adapter, WAKEUP_GPIO_IDX);\n\telse\n\t\trtw_hal_set_output_gpio(adapter, WAKEUP_GPIO_IDX, 0);\n#else\n\tval8 = (pwrctl->is_high_active == 0) ? 1 : 0;\n\tRTW_PRINT(\"Set Wake GPIO to default(%d).\\n\", val8);\n\n\trtw_hal_set_output_gpio(adapter, WAKEUP_GPIO_IDX, val8);\n\trtw_hal_switch_gpio_wl_ctrl(adapter, WAKEUP_GPIO_IDX, _FALSE);\n#endif\n#endif /* CONFIG_RTW_ONE_PIN_GPIO */\n#endif\n\tif ((pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT) &&\n\t    (pwrctl->wowlan_wake_reason != RX_PAIRWISEKEY) &&\n\t    (pwrctl->wowlan_wake_reason != RX_DISASSOC) &&\n\t    (pwrctl->wowlan_wake_reason != RX_DEAUTH)) {\n\n\t\tmedia_status_rpt = RT_MEDIA_CONNECT;\n\t\trtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,\n\t\t\t\t  (u8 *)&media_status_rpt);\n\n\t\tif (psta != NULL) {\n\t\t\t#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\t\t\tadapter_to_dvobj(adapter)->dft.port_id = 0xFF;\n\t\t\tadapter_to_dvobj(adapter)->dft.mac_id = 0xFF;\n\t\t\trtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id);\n\t\t\t#endif\n\t\t\trtw_sta_media_status_rpt(adapter, psta, 1);\n\t\t}\n\t}\n\trtw_hal_gate_bb(adapter, _FALSE);\n}\n#endif /*CONFIG_WOWLAN*/\n\n#ifdef CONFIG_P2P_WOWLAN\nvoid rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,\n\t      u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len,\n\t\t\t\t      RSVDPAGE_LOC *rsvd_page_loc)\n{\n\tu32 P2PNegoRspLength = 0, P2PInviteRspLength = 0;\n\tu32 P2PPDRspLength = 0, P2PProbeRspLength = 0, P2PBCNLength = 0;\n\tu8 CurtPktPageNum = 0;\n\n\t/* P2P Beacon */\n\trsvd_page_loc->LocP2PBeacon = *page_num;\n\trtw_hal_construct_P2PBeacon(adapter, &pframe[index], &P2PBCNLength);\n\trtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],\n\t\t\t\t P2PBCNLength, _FALSE, _FALSE, _FALSE);\n\n#if 0\n\tRTW_INFO(\"%s(): HW_VAR_SET_TX_CMD: PROBE RSP %p %d\\n\",\n\t\t__FUNCTION__, &pframe[index - tx_desc], (P2PBCNLength + tx_desc));\n#endif\n\n\tCurtPktPageNum = (u8)PageNum(tx_desc + P2PBCNLength, page_size);\n\n\t*page_num += CurtPktPageNum;\n\n\tindex += (CurtPktPageNum * page_size);\n\tRSVD_PAGE_CFG(\"WOW-P2P-Beacon\", CurtPktPageNum, *page_num, 0);\n\n\t/* P2P Probe rsp */\n\trsvd_page_loc->LocP2PProbeRsp = *page_num;\n\trtw_hal_construct_P2PProbeRsp(adapter, &pframe[index],\n\t\t\t\t      &P2PProbeRspLength);\n\trtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],\n\t\t\t\t P2PProbeRspLength, _FALSE, _FALSE, _FALSE);\n\n\t/* RTW_INFO(\"%s(): HW_VAR_SET_TX_CMD: PROBE RSP %p %d\\n\",  */\n\t/*\t__FUNCTION__, &pframe[index-tx_desc], (P2PProbeRspLength+tx_desc)); */\n\n\tCurtPktPageNum = (u8)PageNum(tx_desc + P2PProbeRspLength, page_size);\n\n\t*page_num += CurtPktPageNum;\n\n\tindex += (CurtPktPageNum * page_size);\n\tRSVD_PAGE_CFG(\"WOW-P2P-ProbeRsp\", CurtPktPageNum, *page_num, 0);\n\n\t/* P2P nego rsp */\n\trsvd_page_loc->LocNegoRsp = *page_num;\n\trtw_hal_construct_P2PNegoRsp(adapter, &pframe[index],\n\t\t\t\t     &P2PNegoRspLength);\n\trtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],\n\t\t\t\t P2PNegoRspLength, _FALSE, _FALSE, _FALSE);\n\n\t/* RTW_INFO(\"%s(): HW_VAR_SET_TX_CMD: QOS NULL DATA %p %d\\n\",  */\n\t/*\t__FUNCTION__, &pframe[index-tx_desc], (NegoRspLength+tx_desc)); */\n\n\tCurtPktPageNum = (u8)PageNum(tx_desc + P2PNegoRspLength, page_size);\n\n\t*page_num += CurtPktPageNum;\n\n\tindex += (CurtPktPageNum * page_size);\n\tRSVD_PAGE_CFG(\"WOW-P2P-NegoRsp\", CurtPktPageNum, *page_num, 0);\n\n\t/* P2P invite rsp */\n\trsvd_page_loc->LocInviteRsp = *page_num;\n\trtw_hal_construct_P2PInviteRsp(adapter, &pframe[index],\n\t\t\t\t       &P2PInviteRspLength);\n\trtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],\n\t\t\t\t P2PInviteRspLength, _FALSE, _FALSE, _FALSE);\n\n\t/* RTW_INFO(\"%s(): HW_VAR_SET_TX_CMD: QOS NULL DATA %p %d\\n\",  */\n\t/* __FUNCTION__, &pframe[index-tx_desc], (InviteRspLength+tx_desc)); */\n\n\tCurtPktPageNum = (u8)PageNum(tx_desc + P2PInviteRspLength, page_size);\n\n\t*page_num += CurtPktPageNum;\n\n\tindex += (CurtPktPageNum * page_size);\n\tRSVD_PAGE_CFG(\"WOW-P2P-InviteRsp\", CurtPktPageNum, *page_num, 0);\n\n\t/* P2P provision discovery rsp */\n\trsvd_page_loc->LocPDRsp = *page_num;\n\trtw_hal_construct_P2PProvisionDisRsp(adapter,\n\t\t\t\t\t     &pframe[index], &P2PPDRspLength);\n\n\trtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],\n\t\t\t\t P2PPDRspLength, _FALSE, _FALSE, _FALSE);\n\n\t/* RTW_INFO(\"%s(): HW_VAR_SET_TX_CMD: QOS NULL DATA %p %d\\n\",  */\n\t/*\t__FUNCTION__, &pframe[index-tx_desc], (PDRspLength+tx_desc)); */\n\n\tCurtPktPageNum = (u8)PageNum(tx_desc + P2PPDRspLength, page_size);\n\n\t*page_num += CurtPktPageNum;\n\n\t*total_pkt_len = index + P2PPDRspLength;\n\tRSVD_PAGE_CFG(\"WOW-P2P-PDR\", CurtPktPageNum, *page_num, *total_pkt_len);\n\n\tindex += (CurtPktPageNum * page_size);\n\n\n}\n#endif /* CONFIG_P2P_WOWLAN */\n\n#ifdef CONFIG_LPS_PG\n#ifndef DBG_LPSPG_INFO_DUMP\n#define DBG_LPSPG_INFO_DUMP 1\n#endif\n\n#include \"hal_halmac.h\"\n\n#ifdef CONFIG_RTL8822C\nstatic int rtw_lps_pg_set_dpk_info_rsvd_page(_adapter *adapter)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct dm_struct *dm = adapter_to_phydm(adapter);\n\tstruct rsvd_page_cache_t *cache = &pwrpriv->lpspg_dpk_info;\n\tu8 *info = NULL;\n\tu32 info_len;\n\tint ret = _FAIL;\n\n\t/* get length */\n\thalrf_dpk_info_rsvd_page(dm, NULL, &info_len);\n\tif (!info_len) {\n\t\tRTW_ERR(\"get %s length fail\\n\", cache->name);\n\t\tgoto exit;\n\t}\n\n\t/* allocate buf */\n\tinfo = rtw_zmalloc(info_len);\n\tif (!info) {\n\t\tRTW_ERR(\"alloc %s buffer fail(len=%d)\\n\", cache->name, info_len);\n\t\tgoto exit;\n\t}\n\n\t/* get content */\n\thalrf_dpk_info_rsvd_page(dm, info, NULL);\n\n\tif (rsvd_page_cache_update_data(cache, info, info_len)) {\n\n\t\t#if (DBG_LPSPG_INFO_DUMP >= 1)\n\t\tRTW_INFO_DUMP(cache->name, info, info_len);\n\t\t#endif\n\n\t\tret = rtw_halmac_download_rsvd_page(dvobj, cache->loc, info, info_len);\n\t\tret = !ret ? _SUCCESS : _FAIL;\n\t\tif (ret != _SUCCESS) {\n\t\t\tRTW_ERR(\"download %s rsvd page to offset:%u fail\\n\", cache->name, cache->loc);\n\t\t\tgoto free_mem;\n\t\t}\n\n\t\t#if (DBG_LPSPG_INFO_DUMP >= 2)\n\t\tRTW_INFO(\"get %s from rsvd page offset:%d\\n\", cache->name, cache->loc);\n\t\trtw_dump_rsvd_page(RTW_DBGDUMP, adapter, cache->loc, cache->page_num);\n\t\t#endif\n\t}\n\nfree_mem:\n\trtw_mfree(info, info_len);\n\nexit:\n\treturn ret;\n}\n\nstatic int rtw_lps_pg_set_iqk_info_rsvd_page(_adapter *adapter)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct dm_struct *dm = adapter_to_phydm(adapter);\n\tstruct rsvd_page_cache_t *cache = &pwrpriv->lpspg_iqk_info;\n\tu8 *info = NULL;\n\tu32 info_len = 0;\n\tint ret = _FAIL;\n\n\tif (hal_data->RegIQKFWOffload) {\n\t\trsvd_page_cache_free_data(cache);\n\t\tret = _SUCCESS;\n\t\tgoto exit;\n\t}\n\n\t/* get length */\n\thalrf_iqk_info_rsvd_page(dm, NULL, &info_len);\n\tif (!info_len) {\n\t\tRTW_ERR(\"get %s length fail\\n\", cache->name);\n\t\tgoto exit;\n\t}\n\n\t/* allocate buf */\n\tinfo = rtw_zmalloc(info_len);\n\tif (!info) {\n\t\tRTW_ERR(\"alloc %s buffer fail(len=%d)\\n\", cache->name, info_len);\n\t\tgoto exit;\n\t}\n\n\t/* get content */\n\thalrf_iqk_info_rsvd_page(dm, info, NULL);\n\n\tif (rsvd_page_cache_update_data(cache, info, info_len)) {\n\n\t\t#if (DBG_LPSPG_INFO_DUMP >= 1)\n\t\tRTW_INFO_DUMP(cache->name, info, info_len);\n\t\t#endif\n\n\t\tret = rtw_halmac_download_rsvd_page(dvobj, cache->loc, info, info_len);\n\t\tret = !ret ? _SUCCESS : _FAIL;\n\t\tif (ret != _SUCCESS) {\n\t\t\tRTW_ERR(\"download %s rsvd page to offset:%u fail\\n\", cache->name, cache->loc);\n\t\t\tgoto free_mem;\n\t\t}\n\n\t\t#if (DBG_LPSPG_INFO_DUMP >= 2)\n\t\tRTW_INFO(\"get %s from rsvd page offset:%d\\n\", cache->name, cache->loc);\n\t\trtw_dump_rsvd_page(RTW_DBGDUMP, adapter, cache->loc, cache->page_num);\n\t\t#endif\n\t}\n\nfree_mem:\n\trtw_mfree(info, info_len);\n\nexit:\n\treturn ret;\n}\n#endif /* CONFIG_RTL8822C */\n\nstatic void rtw_hal_build_lps_pg_info_rsvd_page(struct dvobj_priv *dvobj, _adapter *ld_sta_iface, u8 *buf, u32 *buf_size)\n{\n#define LPS_PG_INFO_RSVD_LEN\t16\n\n\tif (buf) {\n\t\t_adapter *adapter = dvobj_get_primary_adapter(dvobj);\n\t\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\t\tstruct sta_info *psta;\n#ifdef CONFIG_MBSSID_CAM\n\t\tu8 cam_id = INVALID_CAM_ID;\n#endif\n\t\tu8 *psec_cam_id = buf + 8;\n\t\tu8 sec_cam_num = 0;\n\t\tu8 drv_rsvdpage_num = 0;\n\n\t\tif (ld_sta_iface) {\n\t\t\tpsta = rtw_get_stainfo(&ld_sta_iface->stapriv, get_bssid(&ld_sta_iface->mlmepriv));\n\t\t\tif (!psta) {\n\t\t\t\tRTW_ERR(\"%s [ERROR] sta is NULL\\n\", __func__);\n\t\t\t\trtw_warn_on(1);\n\t\t\t\tgoto size_chk;\n\t\t\t}\n\t\t\t/*Byte 0 - used macid*/\n\t\t\tLPSPG_RSVD_PAGE_SET_MACID(buf, psta->cmn.mac_id);\n\t\t\tRTW_INFO(\"[LPSPG-INFO] mac_id:%d\\n\", psta->cmn.mac_id);\n\t\t}\n\n#ifdef CONFIG_MBSSID_CAM\n\t\t/*Byte 1 - used BSSID CAM entry*/\n\t\tcam_id = rtw_mbid_cam_search_by_ifaceid(adapter, adapter->iface_id);\n\t\tif (cam_id != INVALID_CAM_ID)\n\t\t\tLPSPG_RSVD_PAGE_SET_MBSSCAMID(buf, cam_id);\n\t\tRTW_INFO(\"[LPSPG-INFO] mbss_cam_id:%d\\n\", cam_id);\n#endif\n\n#ifdef CONFIG_WOWLAN /*&& pattern match cam used*/\n\t\t/*Btye 2 - Max used Pattern Match CAM entry*/\n\t\tif (pwrpriv->wowlan_mode == _TRUE\n\t\t\t&& ld_sta_iface && check_fwstate(&ld_sta_iface->mlmepriv, _FW_LINKED) == _TRUE) {\n\t\t\tLPSPG_RSVD_PAGE_SET_PMC_NUM(buf, pwrpriv->wowlan_pattern_idx);\n\t\t\tRTW_INFO(\"[LPSPG-INFO] Max Pattern Match CAM entry :%d\\n\", pwrpriv->wowlan_pattern_idx);\n\t\t}\n#endif\n#ifdef CONFIG_BEAMFORMING  /*&& MU BF*/\n\t\t/*Btye 3 - Max MU rate table Group ID*/\n\t\tLPSPG_RSVD_PAGE_SET_MU_RAID_GID(buf, 0);\n\t\tRTW_INFO(\"[LPSPG-INFO] Max MU rate table Group ID :%d\\n\", 0);\n#endif\n\n\t\t/*Btye 8 ~15 - used Security CAM entry */\n\t\tsec_cam_num = rtw_get_sec_camid(adapter, 8, psec_cam_id);\n\n\t\t/*Btye 4 - used Security CAM entry number*/\n\t\tif (sec_cam_num < 8)\n\t\t\tLPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(buf, sec_cam_num);\n\t\tRTW_INFO(\"[LPSPG-INFO] Security CAM entry number :%d\\n\", sec_cam_num);\n\n\t\t/*Btye 5 - Txbuf used page number for fw offload*/\n\t\tif (pwrpriv->wowlan_mode == _TRUE || pwrpriv->wowlan_ap_mode == _TRUE)\n\t\t\tdrv_rsvdpage_num = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE);\n\t\telse\n\t\t\tdrv_rsvdpage_num = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE);\n\t\tLPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(buf, drv_rsvdpage_num);\n\t\tRTW_INFO(\"[LPSPG-INFO] DRV's rsvd page numbers :%d\\n\", drv_rsvdpage_num);\n\t}\n\nsize_chk:\n\tif (buf_size)\n\t\t*buf_size = LPS_PG_INFO_RSVD_LEN;\n}\n\nstatic int rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct rsvd_page_cache_t *cache = &pwrpriv->lpspg_info;\n\tu8 *info = NULL;\n\tu32 info_len = 0;\n\tint ret = _FAIL;\n\n\t/* get length */\n\trtw_hal_build_lps_pg_info_rsvd_page(dvobj, adapter, NULL, &info_len);\n\tif (!info_len) {\n\t\tRTW_ERR(\"get %s length fail\\n\", cache->name);\n\t\tgoto exit;\n\t}\n\n\t/* allocate buf */\n\tinfo = rtw_zmalloc(info_len);\n\tif (!info) {\n\t\tRTW_ERR(\"alloc %s buffer fail(len=%d)\\n\", cache->name, info_len);\n\t\tgoto exit;\n\t}\n\n\t/* get content */\n\trtw_hal_build_lps_pg_info_rsvd_page(dvobj, adapter, info, NULL);\n\n\tif (rsvd_page_cache_update_data(cache, info, info_len)) {\n\n\t\t#if (DBG_LPSPG_INFO_DUMP >= 1)\n\t\tRTW_INFO_DUMP(cache->name, info, info_len);\n\t\t#endif\n\n\t\tret = rtw_halmac_download_rsvd_page(dvobj, cache->loc, info, info_len);\n\t\tret = !ret ? _SUCCESS : _FAIL;\n\t\tif (ret != _SUCCESS) {\n\t\t\tRTW_ERR(\"download %s rsvd page to offset:%u fail\\n\", cache->name, cache->loc);\n\t\t\tgoto free_mem;\n\t\t}\n\n\t\t#if (DBG_LPSPG_INFO_DUMP >= 2)\n\t\tRTW_INFO(\"get %s from rsvd page offset:%d\\n\", cache->name, cache->loc);\n\t\trtw_dump_rsvd_page(RTW_DBGDUMP, adapter, cache->loc, cache->page_num);\n\t\t#endif\n\t}\n\nfree_mem:\n\trtw_mfree(info, info_len);\n\nexit:\n\treturn ret;\n}\n\nstatic void rtw_lps_pg_set_rsvd_page(_adapter *adapter, u8 *frame, u16 *index\n\t, u8 txdesc_size, u32 page_size, u8 *total_page_num\n\t, bool is_wow_mode, _adapter *ld_sta_iface, bool only_get_page_num)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);\n\tstruct rsvd_page_cache_t *cache;\n\tbool rsvd = 1;\n\tu8 *pos;\n\tu32 len;\n\n\tif (is_wow_mode) {\n\t\t/* lps_level will not change when enter wow_mode */\n\t\tif (pwrctl->lps_level != LPS_PG)\n\t\t\trsvd = 0;\n\t} else {\n\t\tif (!only_get_page_num && !ld_sta_iface)\n\t\t\trsvd = 0;\n\t}\n\n\tpos = only_get_page_num ? NULL : frame + *index;\n\n#ifdef CONFIG_RTL8822C\n\tif (IS_8822C_SERIES(hal_data->version_id)) {\n\t\t/* LPSPG_DPK_INFO */\n\t\tcache = &pwrctl->lpspg_dpk_info;\n\t\tif (rsvd) {\n\t\t\tif (pwrctl->lps_level != LPS_PG)\n\t\t\t\tpos = NULL;\n\t\t\tlen = 0;\n\t\t\thalrf_dpk_info_rsvd_page(adapter_to_phydm(adapter), pos, &len);\n\t\t\t#if (DBG_LPSPG_INFO_DUMP >= 1)\n\t\t\tif (pos)\n\t\t\t\tRTW_INFO_DUMP(cache->name, pos, len);\n\t\t\t#endif\n\t\t\trsvd_page_cache_update_all(cache, *total_page_num, txdesc_size, page_size, pos, len);\n\t\t\t*total_page_num += cache->page_num;\n\t\t\t*index += page_size * cache->page_num;\n\t\t\tpos = only_get_page_num ? NULL : frame + *index;\n\t\t\tRSVD_PAGE_CFG(cache->name, cache->page_num, *total_page_num, *index);\n\t\t} else\n\t\t\trsvd_page_cache_free(cache);\n\n\t\t/* LPSPG_IQK_INFO */\n\t\tcache = &pwrctl->lpspg_iqk_info;\n\t\tif (rsvd\n\t\t\t/* RegIQKFWOffload will not change when enter wow_mode */\n\t\t\t&& !(is_wow_mode && hal_data->RegIQKFWOffload)\n\t\t) {\n\t\t\tif (pwrctl->lps_level != LPS_PG || hal_data->RegIQKFWOffload)\n\t\t\t\tpos = NULL;\n\t\t\tlen = 0;\n\t\t\thalrf_iqk_info_rsvd_page(adapter_to_phydm(adapter), pos, &len);\n\t\t\t#if (DBG_LPSPG_INFO_DUMP >= 1)\n\t\t\tif (pos)\n\t\t\t\tRTW_INFO_DUMP(cache->name, pos, len);\n\t\t\t#endif\n\t\t\trsvd_page_cache_update_all(cache, *total_page_num, txdesc_size, page_size, pos, len);\n\t\t\t*total_page_num += cache->page_num;\n\t\t\t*index += page_size * cache->page_num;\n\t\t\tpos = only_get_page_num ? NULL : frame + *index;\n\t\t\tRSVD_PAGE_CFG(cache->name, cache->page_num, *total_page_num, *index);\n\t\t} else\n\t\t\trsvd_page_cache_free(cache);\n\t}\n#endif\n\n\t/* LPSPG_INFO */\n\tcache = &pwrctl->lpspg_info;\n\tif (rsvd) {\n\t\tif (pwrctl->lps_level != LPS_PG)\n\t\t\tpos = NULL;\n\t\trtw_hal_build_lps_pg_info_rsvd_page(adapter_to_dvobj(adapter), ld_sta_iface, pos, &len);\n\t\t#if (DBG_LPSPG_INFO_DUMP >= 1)\n\t\tif (pos)\n\t\t\tRTW_INFO_DUMP(cache->name, pos, len);\n\t\t#endif\n\t\trsvd_page_cache_update_all(cache, *total_page_num, txdesc_size, page_size, pos, len);\n\t\t*total_page_num += cache->page_num;\n\t\t*index += page_size * cache->page_num;\n\t\tpos = only_get_page_num ? NULL : frame + *index;\n\t\tRSVD_PAGE_CFG(cache->name, cache->page_num, *total_page_num, *index);\n\t} else\n\t\trsvd_page_cache_free(cache);\n}\n\nstatic u8 rtw_hal_set_lps_pg_info_cmd(_adapter *adapter)\n{\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\n\tu8 lpspg_info[H2C_LPS_PG_INFO_LEN] = {0};\n\tu8 ret = _FAIL;\n\n\tif (_NO_PRIVACY_ != adapter->securitypriv.dot11PrivacyAlgrthm)\n\t\tSET_H2CCMD_LPSPG_SEC_CAM_EN(lpspg_info, 1);\t/*SecurityCAM_En*/\n\n#ifdef CONFIG_MBSSID_CAM\n\tSET_H2CCMD_LPSPG_MBID_CAM_EN(lpspg_info, 1);\t\t/*BSSIDCAM_En*/\n#endif\n\n#if defined(CONFIG_WOWLAN) && defined(CONFIG_WOW_PATTERN_HW_CAM)\n\tif (pwrpriv->wowlan_mode == _TRUE &&\n\t    check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {\n\n\t\tSET_H2CCMD_LPSPG_PMC_CAM_EN(lpspg_info, 1);\t/*PatternMatchCAM_En*/\n\t}\n#endif\n\n#ifdef CONFIG_MACID_SEARCH\n\tSET_H2CCMD_LPSPG_MACID_SEARCH_EN(lpspg_info, 1);\t/*MACIDSearch_En*/\n#endif\n\n#ifdef CONFIG_TX_SC\n\tSET_H2CCMD_LPSPG_TXSC_EN(lpspg_info, 1);\t/*TXSC_En*/\n#endif\n\n#ifdef CONFIG_BEAMFORMING  /*&& MU BF*/\n\tSET_H2CCMD_LPSPG_MU_RATE_TB_EN(lpspg_info, 1);\t/*MURateTable_En*/\n#endif\n\n\tSET_H2CCMD_LPSPG_LOC(lpspg_info, pwrpriv->lpspg_info.loc);\n\n#ifdef CONFIG_RTL8822C\n\tSET_H2CCMD_LPSPG_DPK_INFO_LOC(lpspg_info, pwrpriv->lpspg_dpk_info.loc);\n\tif (!GET_HAL_DATA(adapter)->RegIQKFWOffload)\n\t\tSET_H2CCMD_LPSPG_IQK_INFO_LOC(lpspg_info, pwrpriv->lpspg_iqk_info.loc);\n#endif\n\n#if (DBG_LPSPG_INFO_DUMP >= 1)\n\tRTW_INFO_DUMP(\"H2C_LPS_PG_INFO: \", lpspg_info, H2C_LPS_PG_INFO_LEN);\n#endif\n\n\tret = rtw_hal_fill_h2c_cmd(adapter,\n\t\t\t\t   H2C_LPS_PG_INFO,\n\t\t\t\t   H2C_LPS_PG_INFO_LEN,\n\t\t\t\t   lpspg_info);\n\treturn ret;\n}\nu8 rtw_hal_set_lps_pg_info(_adapter *adapter)\n{\n\tu8 ret = _FAIL;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\n\tif (pwrpriv->lpspg_info.loc == 0) {\n\t\tRTW_ERR(\"%s lpspg_info.loc = 0\\n\", __func__);\n\t\trtw_warn_on(1);\n\t\treturn ret;\n\t}\n\t#ifdef CONFIG_RTL8822C\n\trtw_lps_pg_set_dpk_info_rsvd_page(adapter);\n\trtw_lps_pg_set_iqk_info_rsvd_page(adapter);\n\t#endif\n\trtw_hal_set_lps_pg_info_rsvd_page(adapter);\n\n\tret = rtw_hal_set_lps_pg_info_cmd(adapter);\n\n\treturn ret;\n}\n\nvoid rtw_hal_lps_pg_rssi_lv_decide(_adapter *adapter, struct sta_info *sta)\n{\n#if 0\n\tif (sta->cmn.ra_info.rssi_level >= 4)\n\t\tsta->lps_pg_rssi_lv = 3;\t/*RSSI High - 1SS_VHT_MCS7*/\n\telse if (sta->cmn.ra_info.rssi_level >=  2)\n\t\tsta->lps_pg_rssi_lv = 2;\t/*RSSI Middle - 1SS_VHT_MCS3*/\n\telse\n\t\tsta->lps_pg_rssi_lv = 1;\t/*RSSI Lower - Lowest_rate*/\n#else\n\tsta->lps_pg_rssi_lv = 0;\n#endif\n\tRTW_INFO(\"%s mac-id:%d, rssi:%d, rssi_level:%d, lps_pg_rssi_lv:%d\\n\",\n\t\t__func__, sta->cmn.mac_id, sta->cmn.rssi_stat.rssi, sta->cmn.ra_info.rssi_level, sta->lps_pg_rssi_lv);\n}\n\nvoid rtw_hal_lps_pg_handler(_adapter *adapter, enum lps_pg_hdl_id hdl_id)\n{\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct sta_priv *pstapriv = &adapter->stapriv;\n\tstruct sta_info *sta;\n\n\tsta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);\n\n\tswitch (hdl_id) {\n\tcase LPS_PG_INFO_CFG:\n\t\trtw_hal_set_lps_pg_info(adapter);\n\t\tbreak;\n\tcase LPS_PG_REDLEMEM:\n\t\tif (IS_8822C_SERIES(GET_HAL_DATA(adapter)->version_id))\n\t\t\tbreak;\n\n\t\t/*set xmit_block*/\n\t\trtw_set_xmit_block(adapter, XMIT_BLOCK_REDLMEM);\n\t\tif (_FAIL == rtw_hal_fw_mem_dl(adapter, FW_EMEM))\n\t\t\trtw_warn_on(1);\n\t\t/*clearn xmit_block*/\n\t\trtw_clr_xmit_block(adapter, XMIT_BLOCK_REDLMEM);\n\t\tbreak;\n\tcase LPS_PG_PHYDM_DIS:/*Disable RA and PT by H2C*/\n\t\tif (IS_8822C_SERIES(GET_HAL_DATA(adapter)->version_id))\n\t\t\tbreak;\n\n\t\tif (sta)\n\t\t\trtw_phydm_lps_pg_hdl(adapter, sta, _TRUE);\n\t\tbreak;\n\tcase LPS_PG_PHYDM_EN:/*Enable RA and PT by H2C*/\n\t\tif (IS_8822C_SERIES(GET_HAL_DATA(adapter)->version_id))\n\t\t\tbreak;\n\n\t\tif (sta) {\n\t\t\trtw_hal_lps_pg_rssi_lv_decide(adapter, sta);\n\t\t\trtw_phydm_lps_pg_hdl(adapter, sta, _FALSE);\n\t\t\tsta->lps_pg_rssi_lv = 0;\n\t\t}\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n#endif /*CONFIG_LPS_PG*/\n\nstatic u8 _rtw_mi_assoc_if_num(_adapter *adapter)\n{\n\tu8 mi_iface_num = 0;\n\n\tif (0) {\n\t\tRTW_INFO(\"[IFS_ASSOC_STATUS] - STA :%d\", DEV_STA_LD_NUM(adapter_to_dvobj(adapter)));\n\t\tRTW_INFO(\"[IFS_ASSOC_STATUS] - AP:%d\", DEV_AP_NUM(adapter_to_dvobj(adapter)));\n\t\tRTW_INFO(\"[IFS_ASSOC_STATUS] - AP starting :%d\", DEV_AP_STARTING_NUM(adapter_to_dvobj(adapter)));\n\t\tRTW_INFO(\"[IFS_ASSOC_STATUS] - MESH :%d\", DEV_MESH_NUM(adapter_to_dvobj(adapter)));\n\t\tRTW_INFO(\"[IFS_ASSOC_STATUS] - ADHOC :%d\", DEV_ADHOC_NUM(adapter_to_dvobj(adapter)));\n\t\t/*RTW_INFO(\"[IFS_ASSOC_STATUS] - P2P-GC :%d\", DEV_P2P_GC_NUM(adapter_to_dvobj(adapter)));*/\n\t\t/*RTW_INFO(\"[IFS_ASSOC_STATUS] - P2P-GO :%d\", DEV_P2P_GO_NUM(adapter_to_dvobj(adapter)));*/\n\t}\n\n\tmi_iface_num = (DEV_STA_LD_NUM(adapter_to_dvobj(adapter)) +\n\t\tDEV_AP_NUM(adapter_to_dvobj(adapter)) +\n\t\tDEV_AP_STARTING_NUM(adapter_to_dvobj(adapter)));\n\treturn mi_iface_num;\n}\n#ifdef CONFIG_CONCURRENT_MODE\nstatic _adapter *_rtw_search_sta_iface(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\t_adapter *iface = NULL;\n\t_adapter *sta_iface = NULL;\n\tint i;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) {\n\t\t\tif (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) {\n\t\t\t\tsta_iface = iface;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\treturn sta_iface;\n}\n#if defined(CONFIG_AP_MODE) && defined(CONFIG_BT_COEXIST)\nstatic _adapter *_rtw_search_ap_iface(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\t_adapter *iface = NULL;\n\t_adapter *ap_iface = NULL;\n\tint i;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE ) {\n\t\t\tap_iface = iface;\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn ap_iface;\n}\n#endif/*CONFIG_AP_MODE*/\n#endif/*CONFIG_CONCURRENT_MODE*/\n\n#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA\nvoid rtw_hal_set_pathb_phase(_adapter *adapter, u8 phase_idx)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(adapter);\n\tstruct PHY_DM_STRUCT\t\t*pDM_Odm = &pHalData->odmpriv;\n\n\treturn phydm_pathb_q_matrix_rotate(pDM_Odm, phase_idx);\n}\n#endif\n\n/*\n * Description: Fill the reserved packets that FW will use to RSVD page.\n *\t\t\tNow we just send 4 types packet to rsvd page.\n *\t\t\t(1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp.\n * Input:\n * finished - FALSE:At the first time we will send all the packets as a large packet to Hw,\n *\t\t    so we need to set the packet length to total lengh.\n *\t      TRUE: At the second time, we should send the first packet (default:beacon)\n *\t\t    to Hw again and set the lengh in descriptor to the real beacon lengh.\n * page_num - The amount of reserved page which driver need.\n *\t      If this is not NULL, this function doesn't real download reserved\n *\t      page, but just count the number of reserved page.\n *\n * 2009.10.15 by tynli.\n * 2017.06.20 modified by Lucas.\n *\n * Page Size = 128: 8188e, 8723a/b, 8192c/d,\n * Page Size = 256: 8192e, 8821a\n * Page Size = 512: 8812a\n */\n\n/*#define DBG_DUMP_SET_RSVD_PAGE*/\nstatic void _rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished, u8 *page_num)\n{\n\tPHAL_DATA_TYPE pHalData;\n\tstruct xmit_frame\t*pcmdframe = NULL;\n\tstruct pkt_attrib\t*pattrib;\n\tstruct xmit_priv\t*pxmitpriv;\n\tstruct pwrctrl_priv *pwrctl;\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tstruct hal_ops *pHalFunc = &adapter->hal_func;\n\tu32\tBeaconLength = 0, ProbeRspLength = 0, PSPollLength = 0;\n\tu32\tNullDataLength = 0, QosNullLength = 0, BTQosNullLength = 0;\n\tu32\tProbeReqLength = 0, NullFunctionDataLength = 0;\n\tu8\tTxDescLen = TXDESC_SIZE, TxDescOffset = TXDESC_OFFSET;\n\tu8\tTotalPageNum = 0 , CurtPktPageNum = 0 , RsvdPageNum = 0;\n\tu8\t*ReservedPagePacket;\n\tu16\tBufIndex = 0;\n\tu32\tTotalPacketLen = 0, MaxRsvdPageBufSize = 0, PageSize = 0;\n\tRSVDPAGE_LOC\tRsvdPageLoc;\n\tstruct registry_priv  *registry_par = &adapter->registrypriv;\n\n#ifdef DBG_FW_DEBUG_MSG_PKT\n\tu32\tfw_dbg_msg_pkt_len = 0;\n#endif /*DBG_FW_DEBUG_MSG_PKT*/\n\n#ifdef DBG_CONFIG_ERROR_DETECT\n\tstruct sreset_priv *psrtpriv;\n#endif /* DBG_CONFIG_ERROR_DETECT */\n\n#ifdef CONFIG_MCC_MODE\n\tu8 dl_mcc_page = _FAIL;\n#endif /* CONFIG_MCC_MODE */\n\tu8 nr_assoc_if;\n\n\t_adapter *sta_iface = NULL;\n\t_adapter *ap_iface = NULL;\n\n\tbool is_wow_mode = _FALSE;\n\n\tpHalData = GET_HAL_DATA(adapter);\n#ifdef DBG_CONFIG_ERROR_DETECT\n\tpsrtpriv = &pHalData->srestpriv;\n#endif\n\tpxmitpriv = &adapter->xmitpriv;\n\tpwrctl = adapter_to_pwrctl(adapter);\n\n\trtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&PageSize);\n\n\tif (PageSize == 0) {\n\t\tRTW_ERR(\"[Error]: %s, PageSize is zero!!\\n\", __func__);\n\t\treturn;\n\t}\n\tnr_assoc_if = _rtw_mi_assoc_if_num(adapter);\n\n\tif ((pwrctl->wowlan_mode == _TRUE && pwrctl->wowlan_in_resume == _FALSE) ||\n\t\tpwrctl->wowlan_ap_mode == _TRUE ||\n\t\tpwrctl->wowlan_p2p_mode == _TRUE)\n\t\tis_wow_mode = _TRUE;\n\n\t/*page_num for init time to get rsvd page number*/\n\t/* Prepare ReservedPagePacket */\n\tif (page_num) {\n\t\tReservedPagePacket = rtw_zmalloc(MAX_CMDBUF_SZ);\n\t\tif (!ReservedPagePacket) {\n\t\t\tRTW_WARN(\"%s: alloc ReservedPagePacket fail!\\n\", __FUNCTION__);\n\t\t\t*page_num = 0xFF;\n\t\t\treturn;\n\t\t}\n\t\tRTW_INFO(FUNC_ADPT_FMT\" Get [ %s ] RsvdPageNUm  ==>\\n\",\n\t\t\tFUNC_ADPT_ARG(adapter), (is_wow_mode) ? \"WOW\" : \"NOR\");\n\n\t} else {\n\t\tif (is_wow_mode)\n\t\t\tRsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE);\n\t\telse\n\t\t\tRsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE);\n\n\t\tRTW_INFO(FUNC_ADPT_FMT\" PageSize: %d, [ %s ]-RsvdPageNUm: %d\\n\",\n\t\t\tFUNC_ADPT_ARG(adapter), PageSize, (is_wow_mode) ? \"WOW\" : \"NOR\", RsvdPageNum);\n\n\t\tMaxRsvdPageBufSize = RsvdPageNum * PageSize;\n\t\tif (MaxRsvdPageBufSize > MAX_CMDBUF_SZ) {\n\t\t\tRTW_ERR(\"%s MaxRsvdPageBufSize(%d) is larger than MAX_CMDBUF_SZ(%d)\",\n\t\t\t\t __func__, MaxRsvdPageBufSize, MAX_CMDBUF_SZ);\n\t\t\trtw_warn_on(1);\n\t\t\treturn;\n\t\t}\n\n\t\tpcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv);\n\t\tif (pcmdframe == NULL) {\n\t\t\tRTW_ERR(\"%s: alloc ReservedPagePacket fail!\\n\", __FUNCTION__);\n\t\t\treturn;\n\t\t}\n\n\t\tReservedPagePacket = pcmdframe->buf_addr;\n\t}\n\n\t_rtw_memset(&RsvdPageLoc, 0, sizeof(RSVDPAGE_LOC));\n\n\tBufIndex = TxDescOffset;\n\n\t/*======== beacon content =======*/\n\trtw_hal_construct_beacon(adapter,\n\t\t\t\t &ReservedPagePacket[BufIndex], &BeaconLength);\n\n\t/*\n\t* When we count the first page size, we need to reserve description size for the RSVD\n\t* packet, it will be filled in front of the packet in TXPKTBUF.\n\t*/\n\tBeaconLength = MAX_BEACON_LEN - TxDescLen;\n\tCurtPktPageNum = (u8)PageNum((TxDescLen + BeaconLength), PageSize);\n\n#ifdef CONFIG_FW_HANDLE_TXBCN\n\tCurtPktPageNum = CurtPktPageNum * CONFIG_LIMITED_AP_NUM;\n#endif\n\tTotalPageNum += CurtPktPageNum;\n\n\tBufIndex += (CurtPktPageNum * PageSize);\n\n\tRSVD_PAGE_CFG(\"Beacon\", CurtPktPageNum, TotalPageNum, TotalPacketLen);\n\n\t/*======== probe response content ========*/\n\tif (pwrctl->wowlan_ap_mode == _TRUE) {/*WOW mode*/\n\t\t#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (nr_assoc_if >= 2)\n\t\t\tRTW_ERR(\"Not support > 2 net-interface in WOW\\n\");\n\t\t#endif\n\t\t/* (4) probe response*/\n\t\tRsvdPageLoc.LocProbeRsp = TotalPageNum;\n\t\trtw_hal_construct_ProbeRsp(\n\t\t\tadapter, &ReservedPagePacket[BufIndex],\n\t\t\t&ProbeRspLength,\n\t\t\t_FALSE);\n\t\trtw_hal_fill_fake_txdesc(adapter,\n\t\t\t\t &ReservedPagePacket[BufIndex - TxDescLen],\n\t\t\t\t ProbeRspLength, _FALSE, _FALSE, _FALSE);\n\n\t\tCurtPktPageNum = (u8)PageNum(TxDescLen + ProbeRspLength, PageSize);\n\t\tTotalPageNum += CurtPktPageNum;\n\t\tTotalPacketLen = BufIndex + ProbeRspLength;\n\t\tBufIndex += (CurtPktPageNum * PageSize);\n\t\tRSVD_PAGE_CFG(\"ProbeRsp\", CurtPktPageNum, TotalPageNum, TotalPacketLen);\n\t\tgoto download_page;\n\t}\n\n\t/*======== ps-poll content * 1 page ========*/\n\tsta_iface = adapter;\n\t#ifdef CONFIG_CONCURRENT_MODE\n\tif (!MLME_IS_STA(sta_iface) && DEV_STA_LD_NUM(adapter_to_dvobj(sta_iface))) {\n\t\tsta_iface = _rtw_search_sta_iface(adapter);\n\t\tRTW_INFO(\"get (\"ADPT_FMT\") to create PS-Poll/Null/QosNull\\n\", ADPT_ARG(sta_iface));\n\t}\n\t#endif\n\n\tif (MLME_IS_STA(sta_iface) || (nr_assoc_if == 0)) {\n\t\tRsvdPageLoc.LocPsPoll = TotalPageNum;\n\t\tRTW_INFO(\"LocPsPoll: %d\\n\", RsvdPageLoc.LocPsPoll);\n\t\trtw_hal_construct_PSPoll(sta_iface,\n\t\t\t\t\t &ReservedPagePacket[BufIndex], &PSPollLength);\n\t\trtw_hal_fill_fake_txdesc(sta_iface,\n\t\t\t\t\t &ReservedPagePacket[BufIndex - TxDescLen],\n\t\t\t\t\t PSPollLength, _TRUE, _FALSE, _FALSE);\n\n\t\tCurtPktPageNum = (u8)PageNum((TxDescLen + PSPollLength), PageSize);\n\n\t\tTotalPageNum += CurtPktPageNum;\n\n\t\tBufIndex += (CurtPktPageNum * PageSize);\n\t\tRSVD_PAGE_CFG(\"PSPoll\", CurtPktPageNum, TotalPageNum, TotalPacketLen);\n\t}\n\n#ifdef CONFIG_MCC_MODE\n\t/*======== MCC * n page ======== */\n\tif (MCC_EN(adapter)) {/*Normal mode*/\n\t\tdl_mcc_page = rtw_hal_dl_mcc_fw_rsvd_page(adapter, ReservedPagePacket,\n\t\t\t\t&BufIndex, TxDescLen, PageSize, &TotalPageNum, &RsvdPageLoc, page_num);\n\t} else {\n\t\tdl_mcc_page = _FAIL;\n\t}\n\n\tif (dl_mcc_page == _FAIL)\n#endif /* CONFIG_MCC_MODE */\n\t{\t/*======== null data * 1 page ======== */\n\t\tif (MLME_IS_STA(sta_iface) || (nr_assoc_if == 0)) {\n\t\t\tRsvdPageLoc.LocNullData = TotalPageNum;\n\t\t\tRTW_INFO(\"LocNullData: %d\\n\", RsvdPageLoc.LocNullData);\n\t\t\trtw_hal_construct_NullFunctionData(\n\t\t\t\tsta_iface,\n\t\t\t\t&ReservedPagePacket[BufIndex],\n\t\t\t\t&NullDataLength,\n\t\t\t\t_FALSE, 0, 0, _FALSE);\n\t\t\trtw_hal_fill_fake_txdesc(sta_iface,\n\t\t\t\t &ReservedPagePacket[BufIndex - TxDescLen],\n\t\t\t\t NullDataLength, _FALSE, _FALSE, _FALSE);\n\n\t\t\tCurtPktPageNum = (u8)PageNum(TxDescLen + NullDataLength, PageSize);\n\n\t\t\tTotalPageNum += CurtPktPageNum;\n\n\t\t\tBufIndex += (CurtPktPageNum * PageSize);\n\t\t\tRSVD_PAGE_CFG(\"NullData\", CurtPktPageNum, TotalPageNum, TotalPacketLen);\n\t\t}\n\t}\n\n\t/*======== Qos null data * 1 page ======== */\n\tif (pwrctl->wowlan_mode == _FALSE ||\n\t\tpwrctl->wowlan_in_resume == _TRUE) {/*Normal mode*/\t\n\t\tif (MLME_IS_STA(sta_iface) || (nr_assoc_if == 0)) {\n\t\t\tRsvdPageLoc.LocQosNull = TotalPageNum;\n\t\t\tRTW_INFO(\"LocQosNull: %d\\n\", RsvdPageLoc.LocQosNull);\n\t\t\trtw_hal_construct_NullFunctionData(sta_iface,\n\t\t\t\t\t\t&ReservedPagePacket[BufIndex],\n\t\t\t\t\t\t&QosNullLength,\n\t\t\t\t\t\t_TRUE, 0, 0, _FALSE);\n\t\t\trtw_hal_fill_fake_txdesc(sta_iface,\n\t\t\t\t\t &ReservedPagePacket[BufIndex - TxDescLen],\n\t\t\t\t\t QosNullLength, _FALSE, _FALSE, _FALSE);\n\n\t\t\tCurtPktPageNum = (u8)PageNum(TxDescLen + QosNullLength,\n\t\t\t\t\t\t     PageSize);\n\n\t\t\tTotalPageNum += CurtPktPageNum;\n\n\t\t\tBufIndex += (CurtPktPageNum * PageSize);\n\t\t\tRSVD_PAGE_CFG(\"QosNull\", CurtPktPageNum, TotalPageNum, TotalPacketLen);\n\t\t}\n\t}\n\n#ifdef CONFIG_BT_COEXIST\n\t/*======== BT Qos null data * 1 page ======== */\n\tif (pwrctl->wowlan_mode == _FALSE ||\n\t\tpwrctl->wowlan_in_resume == _TRUE) {/*Normal mode*/\n\n\t\tap_iface = adapter;\n\t\t#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (!MLME_IS_AP(ap_iface) && DEV_AP_NUM(adapter_to_dvobj(ap_iface))) {\t/*DEV_AP_STARTING_NUM*/\n\t\t\tap_iface = _rtw_search_ap_iface(adapter);\n\t\t\tRTW_INFO(\"get (\"ADPT_FMT\") to create BTQoSNull\\n\", ADPT_ARG(ap_iface));\n\t\t}\n\t\t#endif\n\n\t\tif (MLME_IS_AP(ap_iface) || (nr_assoc_if == 0)) {\n\t\t\tRsvdPageLoc.LocBTQosNull = TotalPageNum;\n\n\t\t\tRTW_INFO(\"LocBTQosNull: %d\\n\", RsvdPageLoc.LocBTQosNull);\n\n\t\t\trtw_hal_construct_NullFunctionData(ap_iface,\n\t\t\t\t\t\t&ReservedPagePacket[BufIndex],\n\t\t\t\t\t\t&BTQosNullLength,\n\t\t\t\t\t\t_TRUE, 0, 0, _FALSE);\n\n\t\t\trtw_hal_fill_fake_txdesc(ap_iface,\n\t\t\t\t\t&ReservedPagePacket[BufIndex - TxDescLen],\n\t\t\t\t\tBTQosNullLength, _FALSE, _TRUE, _FALSE);\n\n\t\t\tCurtPktPageNum = (u8)PageNum(TxDescLen + BTQosNullLength,\n\t\t\t\t\t\t\t PageSize);\n\n\t\t\tTotalPageNum += CurtPktPageNum;\n\t\t\tBufIndex += (CurtPktPageNum * PageSize);\n\n\t\t\tRSVD_PAGE_CFG(\"BTQosNull\", CurtPktPageNum, TotalPageNum, TotalPacketLen);\n\t\t}\n\t}\n#endif /* CONFIG_BT_COEXIT */\n\n\tTotalPacketLen = BufIndex;\n\n#ifdef DBG_FW_DEBUG_MSG_PKT\n\t\t/*======== FW DEBUG MSG * n page ======== */\n\t\tRsvdPageLoc.loc_fw_dbg_msg_pkt = TotalPageNum;\n\t\tRTW_INFO(\"loc_fw_dbg_msg_pkt: %d\\n\", RsvdPageLoc.loc_fw_dbg_msg_pkt);\n\t\trtw_hal_construct_fw_dbg_msg_pkt(\n\t\t\tadapter,\n\t\t\t&ReservedPagePacket[BufIndex],\n\t\t\t&fw_dbg_msg_pkt_len);\n\n\t\trtw_hal_fill_fake_txdesc(adapter,\n\t\t\t\t &ReservedPagePacket[BufIndex - TxDescLen],\n\t\t\t\t fw_dbg_msg_pkt_len, _FALSE, _FALSE, _FALSE);\n\n\t\tCurtPktPageNum = (u8)PageNum(TxDescLen + fw_dbg_msg_pkt_len, PageSize);\n\n\t\tTotalPageNum += CurtPktPageNum;\n\n\t\tTotalPacketLen = BufIndex + fw_dbg_msg_pkt_len;\n\t\tBufIndex += (CurtPktPageNum * PageSize);\n#endif /*DBG_FW_DEBUG_MSG_PKT*/\n\n#ifdef CONFIG_LPS_PG\n\trtw_lps_pg_set_rsvd_page(adapter, ReservedPagePacket, &BufIndex\n\t\t, TxDescLen, PageSize, &TotalPageNum, is_wow_mode\n\t\t, (sta_iface && MLME_IS_STA(sta_iface) && MLME_IS_ASOC(sta_iface)) ? sta_iface : NULL\n\t\t, page_num ? 1 : 0\n\t);\n\tTotalPacketLen = BufIndex;\n#endif\n\n#ifdef CONFIG_WOWLAN\n\t/*======== WOW * n page ======== */\n\tif (pwrctl->wowlan_mode == _TRUE &&\n\t\tpwrctl->wowlan_in_resume == _FALSE &&\n\t\t!(registry_par->suspend_type == FW_IPS_DISABLE_BBRF && !check_fwstate(pmlmepriv, _FW_LINKED))) {/*WOW mode*/\n\t\trtw_hal_set_wow_fw_rsvd_page(adapter, ReservedPagePacket,\n\t\t\t\t\t     BufIndex, TxDescLen, PageSize,\n\t\t\t     &TotalPageNum, &TotalPacketLen, &RsvdPageLoc);\n\t}\n#endif /* CONFIG_WOWLAN */\n\n#ifdef CONFIG_P2P_WOWLAN\n\t/*======== P2P WOW * n page ======== */\n\tif (_TRUE == pwrctl->wowlan_p2p_mode) {/*WOW mode*/\n\t\trtw_hal_set_p2p_wow_fw_rsvd_page(adapter, ReservedPagePacket,\n\t\t\t\t\t\t BufIndex, TxDescLen, PageSize,\n\t\t\t\t &TotalPageNum, &TotalPacketLen, &RsvdPageLoc);\n\t}\n#endif /* CONFIG_P2P_WOWLAN */\n\n\t/*Note:  BufIndex already add a TxDescOffset offset in first Beacon page\n\t* The \"TotalPacketLen\" is calculate by BufIndex.\n\t* We need to decrease TxDescOffset before doing length check. by yiwei\n\t*/\n\tTotalPacketLen = TotalPacketLen - TxDescOffset;\n\ndownload_page:\n\tif (page_num) {\n\t\t*page_num = TotalPageNum;\n\t\trtw_mfree(ReservedPagePacket, MAX_CMDBUF_SZ);\n\t\tReservedPagePacket = NULL;\n\t\tRTW_INFO(FUNC_ADPT_FMT\" Get [ %s ] RsvdPageNUm <==\\n\",\n\t\t\tFUNC_ADPT_ARG(adapter), (is_wow_mode) ? \"WOW\" : \"NOR\");\n\t\treturn;\n\t}\n\n\t/* RTW_INFO(\"%s BufIndex(%d), TxDescLen(%d), PageSize(%d)\\n\",__func__, BufIndex, TxDescLen, PageSize);*/\n\tRTW_INFO(\"%s PageNum(%d), pktlen(%d)\\n\",\n\t\t __func__, TotalPageNum, TotalPacketLen);\n\n\tif (TotalPacketLen > MaxRsvdPageBufSize) {\n\t\tRTW_ERR(\"%s : rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\\n\",\n\t\t\t __FUNCTION__, TotalPacketLen, MaxRsvdPageBufSize);\n\t\trtw_warn_on(1);\n\t\tgoto error;\n\t} else {\n\t\t/* update attribute */\n\t\tpattrib = &pcmdframe->attrib;\n\t\tupdate_mgntframe_attrib(adapter, pattrib);\n\t\tpattrib->qsel = QSLT_BEACON;\n\t\tpattrib->pktlen = TotalPacketLen;\n\t\tpattrib->last_txcmdsz = TotalPacketLen;\n#ifdef CONFIG_PCI_HCI\n\t\tdump_mgntframe(adapter, pcmdframe);\n#else\n\t\tdump_mgntframe_and_wait(adapter, pcmdframe, 100);\n#endif\n\t}\n\n\tRTW_INFO(\"%s: Set RSVD page location to Fw ,TotalPacketLen(%d), TotalPageNum(%d)\\n\",\n\t\t __func__, TotalPacketLen, TotalPageNum);\n#ifdef DBG_DUMP_SET_RSVD_PAGE\n\tRTW_INFO(\" ==================================================\\n\");\n\tRTW_INFO_DUMP(\"\\n\", ReservedPagePacket, TotalPacketLen);\n\tRTW_INFO(\" ==================================================\\n\");\n#endif\n\n\n\tif (check_fwstate(pmlmepriv, _FW_LINKED)\n\t\t|| MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)){\n\t\trtw_hal_set_FwRsvdPage_cmd(adapter, &RsvdPageLoc);\n#ifdef DBG_FW_DEBUG_MSG_PKT\n\t\trtw_hal_set_fw_dbg_msg_pkt_rsvd_page_cmd(adapter, &RsvdPageLoc);\n#endif /*DBG_FW_DEBUG_MSG_PKT*/\n#ifdef CONFIG_WOWLAN\n\t\tif (pwrctl->wowlan_mode == _TRUE &&\n\t\t\tpwrctl->wowlan_in_resume == _FALSE)\n\t\t\trtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc);\n#endif /* CONFIG_WOWLAN */\n#ifdef CONFIG_AP_WOWLAN\n\t\tif (pwrctl->wowlan_ap_mode == _TRUE)\n\t\t\trtw_hal_set_ap_rsvdpage_loc_cmd(adapter, &RsvdPageLoc);\n#endif /* CONFIG_AP_WOWLAN */\n\t} else if (pwrctl->wowlan_pno_enable) {\n#ifdef CONFIG_PNO_SUPPORT\n\t\trtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc);\n\t\tif (pwrctl->wowlan_in_resume)\n\t\t\trtw_hal_set_scan_offload_info_cmd(adapter,\n\t\t\t\t\t\t\t  &RsvdPageLoc, 0);\n\t\telse\n\t\t\trtw_hal_set_scan_offload_info_cmd(adapter,\n\t\t\t\t\t\t\t  &RsvdPageLoc, 1);\n#endif /* CONFIG_PNO_SUPPORT */\n\t}\n\n#ifdef CONFIG_P2P_WOWLAN\n\tif (_TRUE == pwrctl->wowlan_p2p_mode)\n\t\trtw_hal_set_FwP2PRsvdPage_cmd(adapter, &RsvdPageLoc);\n#endif /* CONFIG_P2P_WOWLAN */\n\n\treturn;\nerror:\n\trtw_free_xmitframe(pxmitpriv, pcmdframe);\n}\n\nvoid rtw_hal_set_fw_rsvd_page(struct _ADAPTER *adapter, bool finished)\n{\n\tif (finished)\n\t\trtw_mi_tx_beacon_hdl(adapter);\n\telse\n\t\t_rtw_hal_set_fw_rsvd_page(adapter, finished, NULL);\n}\n\n/**\n * rtw_hal_get_rsvd_page_num() - Get needed reserved page number\n * @adapter:\tstruct _ADAPTER*\n *\n * Caculate needed reserved page number.\n * In different state would get different number, for example normal mode and\n * WOW mode would need different reserved page size.\n *\n * Return the number of reserved page which driver need.\n */\nu8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter)\n{\n\tu8 num = 0;\n\n\n\t_rtw_hal_set_fw_rsvd_page(adapter, _FALSE, &num);\n\n\treturn num;\n}\n\nstatic void hw_var_set_bcn_func(_adapter *adapter, u8 enable)\n{\n\tu32 bcn_ctrl_reg;\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (adapter->hw_port == HW_PORT1)\n\t\tbcn_ctrl_reg = REG_BCN_CTRL_1;\n\telse\n#endif\n\t\tbcn_ctrl_reg = REG_BCN_CTRL;\n\n\tif (enable)\n\t\trtw_write8(adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));\n\telse {\n\t\tu8 val8;\n\n\t\tval8 = rtw_read8(adapter, bcn_ctrl_reg);\n\t\tval8 &= ~(EN_BCN_FUNCTION | EN_TXBCN_RPT);\n\n#ifdef CONFIG_BT_COEXIST\n\t\tif (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist == 1) {\n\t\t\t/* Always enable port0 beacon function for PSTDMA */\n\t\t\tif (REG_BCN_CTRL == bcn_ctrl_reg)\n\t\t\t\tval8 |= EN_BCN_FUNCTION;\n\t\t}\n#endif\n\n\t\trtw_write8(adapter, bcn_ctrl_reg, val8);\n\t}\n\n#ifdef CONFIG_RTL8192F\n\tif (IS_HARDWARE_TYPE_8192F(adapter)) {\n\t\tu16 val16, val16_ori;\n\n\t\tval16_ori = val16 = rtw_read16(adapter, REG_WLAN_ACT_MASK_CTRL_1);\n\n\t\t#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (adapter->hw_port == HW_PORT1) {\n\t\t\tif (enable)\n\t\t\t\tval16 |= EN_PORT_1_FUNCTION;\n\t\t\telse\n\t\t\t\tval16 &= ~EN_PORT_1_FUNCTION;\n\t\t} else\n\t\t#endif\n\t\t{\n\t\t\tif (enable)\n\t\t\t\tval16 |= EN_PORT_0_FUNCTION;\n\t\t\telse\n\t\t\t\tval16 &= ~EN_PORT_0_FUNCTION;\n\n\t\t\t#ifdef CONFIG_BT_COEXIST\n\t\t\tif (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist == 1)\n\t\t\t\tval16 |= EN_PORT_0_FUNCTION;\n\t\t\t#endif\n\t\t}\n\n\t\tif (val16 != val16_ori)\n\t\t\trtw_write16(adapter, REG_WLAN_ACT_MASK_CTRL_1,  val16);\n\t}\n#endif\n}\n\nstatic void hw_var_set_mlme_disconnect(_adapter *adapter)\n{\n\tu8 val8;\n\n\t/* reject all data frames */\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE)\n#endif\n\t\trtw_write16(adapter, REG_RXFLTMAP2, 0x0000);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (adapter->hw_port == HW_PORT1) {\n\t\t/* reset TSF1 */\n\t\trtw_write8(adapter, REG_DUAL_TSF_RST, BIT(1));\n\n\t\t/* disable update TSF1 */\n\t\trtw_iface_disable_tsf_update(adapter);\n\n\t\tif (!IS_HARDWARE_TYPE_8723D(adapter)\n\t\t\t&& !IS_HARDWARE_TYPE_8192F(adapter)\n\t\t\t&& !IS_HARDWARE_TYPE_8710B(adapter)\n\t\t) {\n\t\t\t/* disable Port1's beacon function */\n\t\t\tval8 = rtw_read8(adapter, REG_BCN_CTRL_1);\n\t\t\tval8 &= ~EN_BCN_FUNCTION;\n\t\t\trtw_write8(adapter, REG_BCN_CTRL_1, val8);\n\t\t}\n\t} else\n#endif\n\t{\n\t\t/* reset TSF */\n\t\trtw_write8(adapter, REG_DUAL_TSF_RST, BIT(0));\n\n\t\t/* disable update TSF */\n\t\trtw_iface_disable_tsf_update(adapter);\n\t}\n}\n\nstatic void hw_var_set_mlme_sitesurvey(_adapter *adapter, u8 enable)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tu16 value_rxfltmap2;\n\tint i;\n\t_adapter *iface;\n\n#ifdef DBG_IFACE_STATUS\n\tDBG_IFACE_STATUS_DUMP(adapter);\n#endif\n\n#ifdef CONFIG_FIND_BEST_CHANNEL\n\t/* Receive all data frames */\n\tvalue_rxfltmap2 = 0xFFFF;\n#else\n\t/* not to receive data frame */\n\tvalue_rxfltmap2 = 0;\n#endif\n\n\tif (enable) { /* under sitesurvey */\n\t\t/*\n\t\t* 1. configure REG_RXFLTMAP2\n\t\t* 2. disable TSF update &  buddy TSF update to avoid updating wrong TSF due to clear RCR_CBSSID_BCN\n\t\t* 3. config RCR to receive different BSSID BCN or probe rsp\n\t\t*/\n\t\trtw_write16(adapter, REG_RXFLTMAP2, value_rxfltmap2);\n\n\t\trtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_ENTER);\n\n\t\t/* Save orignal RRSR setting, only 8812 set RRSR after set ch/bw/band */\n\t\t#if defined (CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\n\t\thal_data->RegRRSR = rtw_read32(adapter, REG_RRSR);\n\t\thal_data->RegRRSR &= 0x000FFFFF;\n\t\t#endif\n\n\t\t#if defined(CONFIG_BEAMFORMING) && (defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A))\n\t\tif (IS_8812_SERIES(hal_data->version_id) || IS_8821_SERIES(hal_data->version_id)) {\n\t\t\t/* set 718[1:0]=2'b00 to avoid BF scan hang */\n\t\t\thal_data->backup_snd_ptcl_ctrl = rtw_read8(adapter, REG_SND_PTCL_CTRL_8812A);\n\t\t\trtw_write8(adapter, REG_SND_PTCL_CTRL_8812A, (hal_data->backup_snd_ptcl_ctrl & 0xfc));\n\t\t}\n\t\t#endif\n\n\t\tif (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))\n\t\t\tStopTxBeacon(adapter);\n\t} else { /* sitesurvey done */\n\t\t/*\n\t\t* 1. enable rx data frame\n\t\t* 2. config RCR not to receive different BSSID BCN or probe rsp\n\t\t* 3. doesn't enable TSF update &  buddy TSF right now to avoid HW conflict\n\t\t*\t so, we enable TSF update when rx first BCN after sitesurvey done\n\t\t*/\n\t\tif (rtw_mi_check_fwstate(adapter, _FW_LINKED | WIFI_AP_STATE | WIFI_MESH_STATE)) {\n\t\t\t/* enable to rx data frame */\n\t\t\trtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);\n\t\t}\n\n\t\trtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_DONE);\n\n\t\t/* Restore orignal RRSR setting,only 8812 set RRSR after set ch/bw/band */\n\t\t#if defined (CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\n\t\t#ifdef RTW_DYNAMIC_RRSR\n\t\t\trtw_phydm_set_rrsr(adapter, hal_data->RegRRSR, TRUE);\n\t\t#else/*RTW_DYNAMIC_RRSR*/\n\t\t\tu32 temp_RRSR;\n\t\t\ttemp_RRSR = rtw_read32(adapter, REG_RRSR);\n\t\t\ttemp_RRSR &= 0xFFF00000;\n\t\t\thal_data->RegRRSR |= temp_RRSR;\n\t\t\trtw_write32(adapter, REG_RRSR, hal_data->RegRRSR);\n\t\t#endif/*RTW_DYNAMIC_RRSR*/\n\t\t#endif\n\n\t\t#if defined(CONFIG_BEAMFORMING) && (defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A))\n\t\tif (IS_8812_SERIES(hal_data->version_id) || IS_8821_SERIES(hal_data->version_id)) {\n\t\t\t/* Restore orignal 0x718 setting*/\n\t\t\trtw_write8(adapter, REG_SND_PTCL_CTRL_8812A, hal_data->backup_snd_ptcl_ctrl);\n\t\t}\n\t\t#endif\n\n\t\tif (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {\n\t\t\tResumeTxBeacon(adapter);\n\t\t\trtw_mi_tx_beacon_hdl(adapter);\n\t\t}\n\t}\n}\n\nstatic void hw_var_set_mlme_join(_adapter *adapter, u8 type)\n{\n\tu8 val8;\n\tu16 val16;\n\tu32 val32;\n\tu8 RetryLimit = RL_VAL_STA;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (type == 0) {\n\t\t/* prepare to join */\n\t\tif (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))\n\t\t\tStopTxBeacon(adapter);\n\n\t\t/* enable to rx data frame.Accept all data frame */\n\t\trtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);\n\n\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)\n\t\t\tRetryLimit = (hal_data->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA;\n\t\telse /* Ad-hoc Mode */\n\t\t\tRetryLimit = RL_VAL_AP;\n\n\t\trtw_iface_enable_tsf_update(adapter);\n\n\t} else if (type == 1) {\n\t\t/* joinbss_event call back when join res < 0 */\n\t\tif (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE)\n\t\t\trtw_write16(adapter, REG_RXFLTMAP2, 0x00);\n\n\t\trtw_iface_disable_tsf_update(adapter);\n\n\t\tif (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {\n\t\t\tResumeTxBeacon(adapter);\n\n\t\t\t/* reset TSF 1/2 after ResumeTxBeacon */\n\t\t\trtw_write8(adapter, REG_DUAL_TSF_RST, BIT(1) | BIT(0));\n\t\t}\n\n\t} else if (type == 2) {\n\t\t/* sta add event call back */\n\t\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {\n\t\t\t/* fixed beacon issue for 8191su........... */\n\t\t\trtw_write8(adapter, 0x542 , 0x02);\n\t\t\tRetryLimit = RL_VAL_AP;\n\t\t}\n\n\t\tif (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {\n\t\t\tResumeTxBeacon(adapter);\n\n\t\t\t/* reset TSF 1/2 after ResumeTxBeacon */\n\t\t\trtw_write8(adapter, REG_DUAL_TSF_RST, BIT(1) | BIT(0));\n\t\t}\n\t}\n\n\tval16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit);\n\trtw_write16(adapter, REG_RETRY_LIMIT, val16);\n#else /* !CONFIG_CONCURRENT_MODE */\n\tif (type == 0) { /* prepare to join */\n\t\t/* enable to rx data frame.Accept all data frame */\n\t\trtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);\n\n\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)\n\t\t\tRetryLimit = (hal_data->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA;\n\t\telse /* Ad-hoc Mode */\n\t\t\tRetryLimit = RL_VAL_AP;\n\n\t\trtw_iface_enable_tsf_update(adapter);\n\n\t} else if (type == 1) { /* joinbss_event call back when join res < 0 */\n\t\trtw_write16(adapter, REG_RXFLTMAP2, 0x00);\n\n\t\trtw_iface_disable_tsf_update(adapter);\n\n\t} else if (type == 2) { /* sta add event call back */\n\t\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE))\n\t\t\tRetryLimit = RL_VAL_AP;\n\t}\n\n\tval16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit);\n\trtw_write16(adapter, REG_RETRY_LIMIT, val16);\n#endif /* !CONFIG_CONCURRENT_MODE */\n}\n\n#ifdef CONFIG_TSF_RESET_OFFLOAD\nstatic int rtw_hal_h2c_reset_tsf(_adapter *adapter, u8 reset_port)\n{\n\tu8 buf[2];\n\tint ret;\n\n\tif (reset_port == HW_PORT0) {\n\t\tbuf[0] = 0x1;\n\t\tbuf[1] = 0;\n\t} else {\n\t\tbuf[0] = 0x0;\n\t\tbuf[1] = 0x1;\n\t}\n\n\tret = rtw_hal_fill_h2c_cmd(adapter, H2C_RESET_TSF, 2, buf);\n\n\treturn ret;\n}\n\nint rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port)\n{\n\tu8 reset_cnt_before = 0, reset_cnt_after = 0, loop_cnt = 0;\n\tu32 reg_reset_tsf_cnt = (reset_port == HW_PORT0) ?\n\t\t\t\tREG_FW_RESET_TSF_CNT_0 : REG_FW_RESET_TSF_CNT_1;\n\tint ret;\n\n\t/* site survey will cause reset tsf fail */\n\trtw_mi_buddy_scan_abort(adapter, _FALSE);\n\treset_cnt_after = reset_cnt_before = rtw_read8(adapter, reg_reset_tsf_cnt);\n\tret = rtw_hal_h2c_reset_tsf(adapter, reset_port);\n\tif (ret != _SUCCESS)\n\t\treturn ret;\n\n\twhile ((reset_cnt_after == reset_cnt_before) && (loop_cnt < 10)) {\n\t\trtw_msleep_os(100);\n\t\tloop_cnt++;\n\t\treset_cnt_after = rtw_read8(adapter, reg_reset_tsf_cnt);\n\t}\n\n\treturn (loop_cnt >= 10) ? _FAIL : _SUCCESS;\n}\n#endif /* CONFIG_TSF_RESET_OFFLOAD */\n\n#ifdef CONFIG_HW_P0_TSF_SYNC\n#ifdef CONFIG_CONCURRENT_MODE\nstatic void hw_port0_tsf_sync_sel(_adapter *adapter, u8 benable, u8 hw_port, u16 tr_offset)\n{\n\tu8 val8;\n\tu8 client_id = 0;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\n#ifdef CONFIG_MCC_MODE\n\tif (MCC_EN(adapter) && (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))) {\n\t\tRTW_INFO(\"[MCC] do not set HW TSF sync\\n\");\n\t\treturn;\n\t}\n#endif\n\t/* check if port0 is already synced */\n\tif (benable && dvobj->p0_tsf.sync_port != MAX_HW_PORT && dvobj->p0_tsf.sync_port == hw_port) {\n\t\tRTW_WARN(FUNC_ADPT_FMT \": port0 already enable TSF sync(%d)\\n\",\n\t\t\tFUNC_ADPT_ARG(adapter), dvobj->p0_tsf.sync_port);\n\t\treturn;\n\t}\n\n\t/* check if port0 already disable sync */\n\tif (!benable && dvobj->p0_tsf.sync_port == MAX_HW_PORT) {\n\t\tRTW_WARN(FUNC_ADPT_FMT \": port0 already disable TSF sync\\n\", FUNC_ADPT_ARG(adapter));\n\t\treturn;\n\t}\n\n\t/* check if port0 sync to port0 */\n\tif (benable && hw_port == HW_PORT0) {\n\t\tRTW_ERR(FUNC_ADPT_FMT \": hw_port is port0 under enable\\n\", FUNC_ADPT_ARG(adapter));\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\t/*0x5B4 [6:4] :SYNC_CLI_SEL - The selector for the CLINT port of sync tsft source for port 0*/\n\t/*\tBit[5:4] : 0 for clint0, 1 for clint1, 2 for clint2, 3 for clint3.\n\t\tBit6 : 1= enable sync to port 0. 0=disable sync to port 0.*/\n\n\tval8 = rtw_read8(adapter, REG_TIMER0_SRC_SEL);\n\n\tif (benable) {\n\t\t/*Disable Port0's beacon function*/\n\t\trtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL) & ~BIT_EN_BCN_FUNCTION);\n\n\t\t/*Reg 0x518[15:0]: TSFTR_SYN_OFFSET*/\n\t\tif (tr_offset)\n\t\t\trtw_write16(adapter, REG_TSFTR_SYN_OFFSET, tr_offset);\n\n\t\t/*reg 0x577[6]=1*/\t/*auto sync by tbtt*/\n\t\trtw_write8(adapter, REG_MISC_CTRL, rtw_read8(adapter, REG_MISC_CTRL) | BIT_AUTO_SYNC_BY_TBTT);\n\n\t\tif (HW_PORT1 == hw_port)\n\t\t\tclient_id = 0;\n\t\telse if (HW_PORT2 == hw_port)\n\t\t\tclient_id = 1;\n\t\telse if (HW_PORT3 == hw_port)\n\t\t\tclient_id = 2;\n\t\telse if (HW_PORT4 == hw_port)\n\t\t\tclient_id = 3;\n\n\t\tval8 &= 0x8F;\n\t\tval8 |= (BIT(6) | (client_id << 4));\n\n\t\tdvobj->p0_tsf.sync_port = hw_port;\n\t\tdvobj->p0_tsf.offset = tr_offset;\n\t\trtw_write8(adapter, REG_TIMER0_SRC_SEL, val8);\n\n\t\t/*Enable Port0's beacon function*/\n\t\trtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL)  | BIT_EN_BCN_FUNCTION);\n\t\tRTW_INFO(\"%s Port_%d TSF sync to P0, timer offset :%d\\n\", __func__, hw_port, tr_offset);\n\t} else {\n\t\tval8 &= ~BIT(6);\n\n\t\tdvobj->p0_tsf.sync_port = MAX_HW_PORT;\n\t\tdvobj->p0_tsf.offset = 0;\n\t\trtw_write8(adapter, REG_TIMER0_SRC_SEL, val8);\n\t\tRTW_INFO(\"%s P0 TSF sync disable\\n\", __func__);\n\t}\n}\nstatic _adapter * _search_ld_sta(_adapter *adapter, u8 include_self)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tu8 i;\n\t_adapter *iface = NULL;\n\n\tif (rtw_mi_get_assoced_sta_num(adapter) == 0) {\n\t\tRTW_ERR(\"STA_LD_NUM == 0\\n\");\n\t\trtw_warn_on(1);\n\t}\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (!iface)\n\t\t\tcontinue;\n\t\tif (include_self == _FALSE && adapter == iface)\n\t\t\tcontinue;\n\t\tif (is_client_associated_to_ap(iface))\n\t\t\tbreak;\n\t}\n\tif (iface)\n\t\tRTW_INFO(\"search STA iface -\"ADPT_FMT\"\\n\", ADPT_ARG(iface));\n\treturn iface;\n}\n#endif /*CONFIG_CONCURRENT_MODE*/\n/*Correct port0's TSF*/\n/*#define DBG_P0_TSF_SYNC*/\nvoid hw_var_set_correct_tsf(PADAPTER adapter, u8 mlme_state)\n{\n#ifdef CONFIG_CONCURRENT_MODE\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tu8 p0_tsfsync = _FALSE;\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;\n\t_adapter *sta_if = NULL;\n\tu8 hw_port;\n\n\tRTW_INFO(FUNC_ADPT_FMT \"\\n\", FUNC_ADPT_ARG(adapter));\n\t#ifdef DBG_P0_TSF_SYNC\n\tRTW_INFO(\"[TSF_SYNC] AP_NUM = %d\\n\", rtw_mi_get_ap_num(adapter));\n\tRTW_INFO(\"[TSF_SYNC] MESH_NUM = %d\\n\", rtw_mi_get_mesh_num(adapter));\n\tRTW_INFO(\"[TSF_SYNC] LD_STA_NUM = %d\\n\", rtw_mi_get_assoced_sta_num(adapter));\n\tif (dvobj->p0_tsf.sync_port == MAX_HW_PORT)\n\t\tRTW_INFO(\"[TSF_SYNC] org p0 sync port = N/A\\n\");\n\telse\n\t\tRTW_INFO(\"[TSF_SYNC] org p0 sync port = %d\\n\", dvobj->p0_tsf.sync_port);\n\tRTW_INFO(\"[TSF_SYNC] timer offset = %d\\n\", dvobj->p0_tsf.offset);\n\t#endif\n\tswitch (mlme_state) {\n\t\tcase MLME_STA_CONNECTED :\n\t\t\t{\n\t\t\t\thw_port = rtw_hal_get_port(adapter);\n\n\t\t\t\tif (!MLME_IS_STA(adapter)) {\n\t\t\t\t\tRTW_ERR(\"STA CON state,but iface(\"ADPT_FMT\") is not STA\\n\", ADPT_ARG(adapter));\n\t\t\t\t\trtw_warn_on(1);\n\t\t\t\t}\n\n\t\t\t\tif ((dvobj->p0_tsf.sync_port != MAX_HW_PORT) && (hw_port == HW_PORT0)) {\n\t\t\t\t\tRTW_ERR(ADPT_FMT\" is STA with P0 connected => DIS P0_TSF_SYNC\\n\", ADPT_ARG(adapter));\n\t\t\t\t\trtw_warn_on(1);\n\t\t\t\t\thw_port0_tsf_sync_sel(adapter, _FALSE, 0, 0);\n\t\t\t\t}\n\n\t\t\t\tif ((dvobj->p0_tsf.sync_port == MAX_HW_PORT) &&\n\t\t\t\t\t(rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))) {\n\t\t\t\t\thw_port0_tsf_sync_sel(adapter, _TRUE, hw_port, 50);/*timer offset 50ms*/\n\t\t\t\t\t#ifdef DBG_P0_TSF_SYNC\n\t\t\t\t\tRTW_INFO(\"[TSF_SYNC] STA_LINKED => EN P0_TSF_SYNC\\n\");\n\t\t\t\t\t#endif\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\tcase MLME_STA_DISCONNECTED :\n\t\t\t{\n\t\t\t\thw_port = rtw_hal_get_port(adapter);\n\n\t\t\t\tif (!MLME_IS_STA(adapter)) {\n\t\t\t\t\tRTW_ERR(\"STA DIS_CON state,but iface(\"ADPT_FMT\") is not STA\\n\", ADPT_ARG(adapter));\n\t\t\t\t\trtw_warn_on(1);\n\t\t\t\t}\n\n\t\t\t\tif (dvobj->p0_tsf.sync_port == hw_port) {\n\t\t\t\t\tif (rtw_mi_get_assoced_sta_num(adapter) >= 2) {\n\t\t\t\t\t\t/* search next appropriate sta*/\n\t\t\t\t\t\tsta_if = _search_ld_sta(adapter, _FALSE);\n\t\t\t\t\t\tif (sta_if) {\n\t\t\t\t\t\t\thw_port = rtw_hal_get_port(sta_if);\n\t\t\t\t\t\t\thw_port0_tsf_sync_sel(adapter, _TRUE, hw_port, 50);/*timer offset 50ms*/\n\t\t\t\t\t\t\t#ifdef DBG_P0_TSF_SYNC\n\t\t\t\t\t\t\tRTW_INFO(\"[TSF_SYNC] STA_DIS_CON => CHANGE P0_TSF_SYNC\\n\");\n\t\t\t\t\t\t\t#endif\n\t\t\t\t\t\t}\n\t\t\t\t\t} else if (rtw_mi_get_assoced_sta_num(adapter) == 1) {\n\t\t\t\t\t\thw_port0_tsf_sync_sel(adapter, _FALSE, 0, 0);\n\t\t\t\t\t\t#ifdef DBG_P0_TSF_SYNC\n\t\t\t\t\t\tRTW_INFO(\"[TSF_SYNC] STA_DIS_CON => DIS P0_TSF_SYNC\\n\");\n\t\t\t\t\t\t#endif\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\tcase MLME_AP_STARTED :\n\t\tcase MLME_MESH_STARTED :\n\t\t\t{\n\t\t\t\tif (!(MLME_IS_AP(adapter) || MLME_IS_MESH(adapter))) {\n\t\t\t\t\tRTW_ERR(\"AP START state,but iface(\"ADPT_FMT\") is not AP\\n\", ADPT_ARG(adapter));\n\t\t\t\t\trtw_warn_on(1);\n\t\t\t\t}\n\n\t\t\t\tif ((dvobj->p0_tsf.sync_port == MAX_HW_PORT) &&\n\t\t\t\t\trtw_mi_get_assoced_sta_num(adapter)) {\n\t\t\t\t\t/* get port of sta */\n\t\t\t\t\tsta_if = _search_ld_sta(adapter, _FALSE);\n\t\t\t\t\tif (sta_if) {\n\t\t\t\t\t\thw_port = rtw_hal_get_port(sta_if);\n\t\t\t\t\t\thw_port0_tsf_sync_sel(adapter, _TRUE, hw_port, 50);/*timer offset 50ms*/\n\t\t\t\t\t\t#ifdef DBG_P0_TSF_SYNC\n\t\t\t\t\t\tRTW_INFO(\"[TSF_SYNC] AP_START => EN P0_TSF_SYNC\\n\");\n\t\t\t\t\t\t#endif\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\tcase MLME_AP_STOPPED :\n\t\tcase MLME_MESH_STOPPED :\n\t\t\t{\n\t\t\t\tif (!(MLME_IS_AP(adapter) || MLME_IS_MESH(adapter))) {\n\t\t\t\t\tRTW_ERR(\"AP START state,but iface(\"ADPT_FMT\") is not AP\\n\", ADPT_ARG(adapter));\n\t\t\t\t\trtw_warn_on(1);\n\t\t\t\t}\n\t\t\t\t/*stop ap mode*/\n\t\t\t\tif ((rtw_mi_get_ap_num(adapter) + rtw_mi_get_mesh_num(adapter) == 1) &&\n\t\t\t\t\t(dvobj->p0_tsf.sync_port != MAX_HW_PORT)) {\n\t\t\t\t\thw_port0_tsf_sync_sel(adapter, _FALSE, 0, 0);\n\t\t\t\t\t#ifdef DBG_P0_TSF_SYNC\n\t\t\t\t\tRTW_INFO(\"[TSF_SYNC] AP_STOP => DIS P0_TSF_SYNC\\n\");\n\t\t\t\t\t#endif\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault :\n\t\t\tRTW_ERR(FUNC_ADPT_FMT\" unknow state(0x%02x)\\n\", FUNC_ADPT_ARG(adapter), mlme_state);\n\t\t\tbreak;\n\t}\n\n\t/*#ifdef DBG_P0_TSF_SYNC*/\n\t#if 1\n\tif (dvobj->p0_tsf.sync_port == MAX_HW_PORT)\n\t\tRTW_INFO(\"[TSF_SYNC] p0 sync port = N/A\\n\");\n\telse\n\t\tRTW_INFO(\"[TSF_SYNC] p0 sync port = %d\\n\", dvobj->p0_tsf.sync_port);\n\tRTW_INFO(\"[TSF_SYNC] timer offset = %d\\n\", dvobj->p0_tsf.offset);\n\t#endif\n#endif /*CONFIG_CONCURRENT_MODE*/\n}\n\n#else /*! CONFIG_HW_P0_TSF_SYNC*/\n\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\nstatic void hw_var_set_correct_tsf(_adapter *adapter, u8 mlme_state)\n{\n\t/*do nothing*/\n}\n#else /* !CONFIG_MI_WITH_MBSSID_CAM*/\nstatic void rtw_hal_correct_tsf(_adapter *padapter, u8 hw_port, u64 tsf)\n{\n\tif (hw_port == HW_PORT0) {\n\t\t/*disable related TSF function*/\n\t\trtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) & (~EN_BCN_FUNCTION));\n#if defined(CONFIG_RTL8192F)\n\t\trtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter,\n\t\t\t\t\tREG_WLAN_ACT_MASK_CTRL_1) & ~EN_PORT_0_FUNCTION);\n#endif\n\n\t\trtw_write32(padapter, REG_TSFTR, tsf);\n\t\trtw_write32(padapter, REG_TSFTR + 4, tsf >> 32);\n\n\t\t/*enable related TSF function*/\n\t\trtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) | EN_BCN_FUNCTION);\n#if defined(CONFIG_RTL8192F)\n\t\trtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter,\n\t\t\t\t\tREG_WLAN_ACT_MASK_CTRL_1) | EN_PORT_0_FUNCTION);\n#endif\n\t} else if (hw_port == HW_PORT1) {\n\t\t/*disable related TSF function*/\n\t\trtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) & (~EN_BCN_FUNCTION));\n#if defined(CONFIG_RTL8192F)\n\t\trtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter,\n\t\t\t\t\tREG_WLAN_ACT_MASK_CTRL_1) & ~EN_PORT_1_FUNCTION);\n#endif\n\n\t\trtw_write32(padapter, REG_TSFTR1, tsf);\n\t\trtw_write32(padapter, REG_TSFTR1 + 4, tsf >> 32);\n\n\t\t/*enable related TSF function*/\n\t\trtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) | EN_BCN_FUNCTION);\n#if defined(CONFIG_RTL8192F)\n\t\trtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter,\n\t\t\t\t\tREG_WLAN_ACT_MASK_CTRL_1) | EN_PORT_1_FUNCTION);\n#endif\n\t} else\n\t\tRTW_INFO(\"%s-[WARN] \"ADPT_FMT\" invalid hw_port:%d\\n\", __func__, ADPT_ARG(padapter), hw_port);\n}\nstatic void hw_var_set_correct_tsf(_adapter *adapter, u8 mlme_state)\n{\n\tu64 tsf;\n\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info);\n\n\ttsf = mlmeext->TSFValue - rtw_modular64(mlmeext->TSFValue, (mlmeinfo->bcn_interval * 1024)) - 1024; /*us*/\n\n\tif ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE\n\t\t|| (mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)\n\t\tStopTxBeacon(adapter);\n\n\trtw_hal_correct_tsf(adapter, adapter->hw_port, tsf);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t/* Update buddy port's TSF if it is SoftAP/Mesh for beacon TX issue! */\n\tif ((mlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE\n\t\t&& (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))\n\t) {\n\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\t\tint i;\n\t\t_adapter *iface;\n\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tif (!iface)\n\t\t\t\tcontinue;\n\t\t\tif (iface == adapter)\n\t\t\t\tcontinue;\n\n\t\t\tif ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))\n\t\t\t\t&& check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE\n\t\t\t) {\n\t\t\t\trtw_hal_correct_tsf(iface, iface->hw_port, tsf);\n\t\t\t\t#ifdef CONFIG_TSF_RESET_OFFLOAD\n\t\t\t\tif (rtw_hal_reset_tsf(iface, iface->hw_port) == _FAIL)\n\t\t\t\t\tRTW_INFO(\"%s-[ERROR] \"ADPT_FMT\" Reset port%d TSF fail\\n\"\n\t\t\t\t\t\t, __func__, ADPT_ARG(iface), iface->hw_port);\n\t\t\t\t#endif\t/* CONFIG_TSF_RESET_OFFLOAD*/\n\t\t\t}\n\t\t}\n\t}\n#endif /* CONFIG_CONCURRENT_MODE */\n\tif ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE\n\t\t|| (mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)\n\t\tResumeTxBeacon(adapter);\n}\n#endif /*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/\n#endif /*#ifdef CONFIG_HW_P0_TSF_SYNC*/\n\nu64 rtw_hal_get_tsftr_by_port(_adapter *adapter, u8 port)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tu64 tsftr = 0;\n\n\tif (port >= hal_spec->port_num) {\n\t\tRTW_ERR(\"%s invalid port(%d) \\n\", __func__, port);\n\t\tgoto exit;\n\t}\n\n\tswitch (rtw_get_chip_type(adapter)) {\n#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)\n\tcase RTL8814A:\n\tcase RTL8822B:\n\tcase RTL8821C:\n\tcase RTL8822C:\t\t\n\t{\n\t\tu8 val8;\n\n\t\t/* 0x554[30:28] - BIT_BCN_TIMER_SEL_FWRD */\n\t\tval8 = rtw_read8(adapter, REG_MBSSID_BCN_SPACE + 3);\n\t\tval8 &= 0x8F;\n\t\tval8 |= port << 4;\n\t\trtw_write8(adapter, REG_MBSSID_BCN_SPACE + 3, val8);\n\n\t\ttsftr = rtw_read32(adapter, REG_TSFTR + 4);\n\t\ttsftr = tsftr << 32;\n\t\ttsftr |= rtw_read32(adapter, REG_TSFTR);\n\n\t\tbreak;\n\t}\n#endif\n#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) \\\n\t\t|| defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8192F) \\\n\t\t|| defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8723D) \\\n\t\t|| defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) \\\n\t\t|| defined(CONFIG_RTL8710B)\n\tcase RTL8188E:\n\tcase RTL8188F:\n\tcase RTL8188GTV:\n\tcase RTL8192E:\n\tcase RTL8192F:\n\tcase RTL8723B:\n\tcase RTL8703B:\n\tcase RTL8723D:\n\tcase RTL8812:\n\tcase RTL8821:\n\tcase RTL8710B:\n\t{\n\t\tu32 addr;\n\n\t\tif (port == HW_PORT0)\n\t\t\taddr = REG_TSFTR;\n\t\telse if (port == HW_PORT1)\n\t\t\taddr = REG_TSFTR1;\n\t\telse {\n\t\t\tRTW_ERR(\"%s unknown port(%d) \\n\", __func__, port);\n\t\t\tgoto exit;\n\t\t}\n\n\t\ttsftr = rtw_read32(adapter, addr + 4);\n\t\ttsftr = tsftr << 32;\n\t\ttsftr |= rtw_read32(adapter, addr);\n\n\t\tbreak;\n\t}\n#endif\n\tdefault:\n\t\tRTW_ERR(\"%s unknow chip type\\n\", __func__);\n\t}\n\nexit:\n\treturn tsftr;\n}\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\ns32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode)\n{\n\tPHAL_DATA_TYPE\tpHalData =  GET_HAL_DATA(padapter);\n\tu8 ch_sw_h2c_buf[4] = {0x00, 0x00, 0x00, 0x00};\n\n\n\tSET_H2CCMD_CH_SW_OPER_OFFLOAD_CH_NUM(ch_sw_h2c_buf, channel);\n\tSET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_MODE(ch_sw_h2c_buf, bwmode);\n\tswitch (bwmode) {\n\tcase CHANNEL_WIDTH_40:\n\t\tSET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_40M_SC(ch_sw_h2c_buf, channel_offset);\n\t\tbreak;\n\tcase CHANNEL_WIDTH_80:\n\t\tSET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_80M_SC(ch_sw_h2c_buf, channel_offset);\n\t\tbreak;\n\tcase CHANNEL_WIDTH_20:\n\tdefault:\n\t\tbreak;\n\t}\n\tSET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(ch_sw_h2c_buf, pHalData->rfe_type);\n\n\treturn rtw_hal_fill_h2c_cmd(padapter, H2C_CHNL_SWITCH_OPER_OFFLOAD, sizeof(ch_sw_h2c_buf), ch_sw_h2c_buf);\n}\n#endif\n#endif\n\n#ifdef CONFIG_WMMPS_STA\nvoid rtw_hal_update_uapsd_tid(_adapter *adapter)\n{\n\tstruct mlme_priv\t\t*pmlmepriv = &adapter->mlmepriv;\n\tstruct qos_priv\t\t*pqospriv = &pmlmepriv->qospriv;\n\n\t/* write complement of pqospriv->uapsd_tid to mac register 0x693 because \n\t    it's designed  for \"0\" represents \"enable\" and \"1\" represents \"disable\" */\n\trtw_write8(adapter, REG_WMMPS_UAPSD_TID, (u8)(~pqospriv->uapsd_tid));\n}\n#endif /* CONFIG_WMMPS_STA */\n\n#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)\n/* For multi-port support, driver needs to inform the port ID to FW for btc operations */\ns32 rtw_hal_set_wifi_btc_port_id_cmd(_adapter *adapter)\n{\n\tu8 h2c_buf[H2C_BTC_WL_PORT_ID_LEN] = {0};\n\tu8 hw_port = rtw_hal_get_port(adapter);\n\n\tSET_H2CCMD_BTC_WL_PORT_ID(h2c_buf, hw_port);\n\tRTW_INFO(\"%s (\"ADPT_FMT\") - hw_port :%d\\n\", __func__, ADPT_ARG(adapter), hw_port);\n\treturn rtw_hal_fill_h2c_cmd(adapter, H2C_BTC_WL_PORT_ID, H2C_BTC_WL_PORT_ID_LEN, h2c_buf);\n}\n#endif\n\n#define LPS_ACTIVE_TIMEOUT\t10 /*number of times*/\nvoid rtw_lps_state_chk(_adapter *adapter, u8 ps_mode)\n{\n\tif (ps_mode == PS_MODE_ACTIVE) {\n\t\tu8 ps_ready = _FALSE;\n\t\ts8 leave_wait_count = LPS_ACTIVE_TIMEOUT;\n\n\t\tdo {\n\t\t\tif ((rtw_read8(adapter, REG_TCR) & BIT_PWRBIT_OW_EN) == 0) {\n\t\t\t\tps_ready = _TRUE;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\trtw_msleep_os(1);\n\t\t} while (leave_wait_count--);\n\n\t\tif (ps_ready == _FALSE) {\n\t\t\tRTW_ERR(FUNC_ADPT_FMT\" PS_MODE_ACTIVE check failed\\n\", FUNC_ADPT_ARG(adapter));\n\t\t\trtw_warn_on(1);\n\t\t}\n\t}\n}\nvoid rtw_var_set_basic_rate(PADAPTER padapter, u8 *val) {\n\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(padapter);\n\tstruct mlme_ext_info *mlmext_info = &padapter->mlmeextpriv.mlmext_info;\n\tu16 input_b = 0, masked = 0, ioted = 0, BrateCfg = 0;\n\tu16 rrsr_2g_force_mask = RRSR_CCK_RATES;\n\tu16 rrsr_2g_allow_mask = (RRSR_24M | RRSR_12M | RRSR_6M | RRSR_CCK_RATES);\n\t#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\tu16 rrsr_5g_force_mask = (RRSR_6M);\n\tu16 rrsr_5g_allow_mask = (RRSR_OFDM_RATES);\n\t#endif\n\t#ifdef RTW_DYNAMIC_RRSR\n\tu32 temp_RRSR;\n\t#endif\n\n\tHalSetBrateCfg(padapter, val, &BrateCfg);\n\tinput_b = BrateCfg;\n\n\t/* apply force and allow mask */\n\t#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\tif (pHalData->current_band_type != BAND_ON_2_4G) {\n\t\tBrateCfg |= rrsr_5g_force_mask;\n\t\tBrateCfg &= rrsr_5g_allow_mask;\n\t} else\n\t#endif\n\t{ /* 2.4G */\n\t\tBrateCfg |= rrsr_2g_force_mask;\n\t\tBrateCfg &= rrsr_2g_allow_mask;\n\t}\n\tmasked = BrateCfg;\n\n#ifdef CONFIG_CMCC_TEST\n\tBrateCfg |= (RRSR_11M | RRSR_5_5M | RRSR_1M); /* use 11M to send ACK */\n\tBrateCfg |= (RRSR_24M | RRSR_18M | RRSR_12M); /*CMCC_OFDM_ACK 12/18/24M */\n#endif\n\n\t/* IOT consideration */\n\tif (mlmext_info->assoc_AP_vendor == HT_IOT_PEER_CISCO) {\n\t\t/* if peer is cisco and didn't use ofdm rate, we enable 6M ack */\n\t\tif ((BrateCfg & (RRSR_24M | RRSR_12M | RRSR_6M)) == 0)\n\t\t\tBrateCfg |= RRSR_6M;\n\t}\n\t\tioted = BrateCfg;\n\n#ifdef CONFIG_NARROWBAND_SUPPORTING\n\tif ((padapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_10)\n\t\t|| (padapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_5)) {\n\t\tBrateCfg &= ~RRSR_CCK_RATES;\n\t\tBrateCfg |= RRSR_6M;\n\t}\n#endif\n\tpHalData->BasicRateSet = BrateCfg;\n\n\tRTW_INFO(\"HW_VAR_BASIC_RATE: %#x->%#x->%#x\\n\", input_b, masked, ioted);\n\n\t/* Set RRSR rate table. */\n\t#ifdef RTW_DYNAMIC_RRSR\n\t\ttemp_RRSR = rtw_read32(padapter, REG_RRSR);\n\t\ttemp_RRSR &=0xFFFF0000;\n\t\ttemp_RRSR |=BrateCfg;\n\t\trtw_phydm_set_rrsr(padapter, temp_RRSR, TRUE);\n\t#else\n\t\trtw_write16(padapter, REG_RRSR, BrateCfg);\n\t#endif\n\trtw_write8(padapter, REG_RRSR + 2, rtw_read8(padapter, REG_RRSR + 2) & 0xf0);\n\n\t#if defined(CONFIG_RTL8188E)\n\trtw_hal_set_hwreg(padapter, HW_VAR_INIT_RTS_RATE, (u8 *)&BrateCfg);\n\t#endif\n}\n\nu8 SetHwReg(_adapter *adapter, u8 variable, u8 *val)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tu8 ret = _SUCCESS;\n\n\tswitch (variable) {\n\tcase HW_VAR_MEDIA_STATUS: {\n\t\tu8 net_type = *((u8 *)val);\n\n\t\trtw_hal_set_msr(adapter, net_type);\n\t}\n\tbreak;\n\tcase HW_VAR_DO_IQK:\n\t\tif (*val)\n\t\t\thal_data->bNeedIQK = _TRUE;\n\t\telse\n\t\t\thal_data->bNeedIQK = _FALSE;\n\t\tbreak;\n\tcase HW_VAR_MAC_ADDR:\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\t\trtw_hal_set_macaddr_mbid(adapter, val);\n#else\n\t\trtw_hal_set_macaddr_port(adapter, val);\n#endif\n\t\tbreak;\n\tcase HW_VAR_BSSID:\n\t\trtw_hal_set_bssid(adapter, val);\n\t\tbreak;\n\tcase HW_VAR_RCR:\n\t\tret = hw_var_rcr_config(adapter, *((u32 *)val));\n\t\tbreak;\n\tcase HW_VAR_ON_RCR_AM:\n\t\thw_var_set_rcr_am(adapter, 1);\n\t\tbreak;\n\tcase HW_VAR_OFF_RCR_AM:\n\t\thw_var_set_rcr_am(adapter, 0);\n\t\tbreak;\n\tcase HW_VAR_BEACON_INTERVAL:\n\t\thw_var_set_bcn_interval(adapter, *(u16 *)val);\n\t\tbreak;\n#ifdef CONFIG_MBSSID_CAM\n\tcase HW_VAR_MBSSID_CAM_WRITE: {\n\t\tu32\tcmd = 0;\n\t\tu32\t*cam_val = (u32 *)val;\n\n\t\trtw_write32(adapter, REG_MBIDCAMCFG_1, cam_val[0]);\n\t\tcmd = BIT_MBIDCAM_POLL | BIT_MBIDCAM_WT_EN | BIT_MBIDCAM_VALID | cam_val[1];\n\t\trtw_write32(adapter, REG_MBIDCAMCFG_2, cmd);\n\t}\n\t\tbreak;\n\tcase HW_VAR_MBSSID_CAM_CLEAR: {\n\t\tu32 cmd;\n\t\tu8 entry_id = *(u8 *)val;\n\n\t\trtw_write32(adapter, REG_MBIDCAMCFG_1, 0);\n\n\t\tcmd = BIT_MBIDCAM_POLL | BIT_MBIDCAM_WT_EN | ((entry_id & MBIDCAM_ADDR_MASK) << MBIDCAM_ADDR_SHIFT);\n\t\trtw_write32(adapter, REG_MBIDCAMCFG_2, cmd);\n\t}\n\t\tbreak;\n\tcase HW_VAR_RCR_MBSSID_EN:\n\t\tif (*((u8 *)val))\n\t\t\trtw_hal_rcr_add(adapter, RCR_ENMBID);\n\t\telse\n\t\t\trtw_hal_rcr_clear(adapter, RCR_ENMBID);\n\t\tbreak;\n#endif\n\tcase HW_VAR_PORT_SWITCH:\n\t\thw_var_port_switch(adapter);\n\t\tbreak;\n\tcase HW_VAR_INIT_RTS_RATE: {\n\t\tu16 brate_cfg = *((u16 *)val);\n\t\tu8 rate_index = 0;\n\t\tHAL_VERSION *hal_ver = &hal_data->version_id;\n\n\t\tif (IS_8188E(*hal_ver)) {\n\n\t\t\twhile (brate_cfg > 0x1) {\n\t\t\t\tbrate_cfg = (brate_cfg >> 1);\n\t\t\t\trate_index++;\n\t\t\t}\n\t\t\trtw_write8(adapter, REG_INIRTS_RATE_SEL, rate_index);\n\t\t} else\n\t\t\trtw_warn_on(1);\n\t}\n\t\tbreak;\n\tcase HW_VAR_SEC_CFG: {\n\t\tu16 reg_scr_ori;\n\t\tu16 reg_scr;\n\n\t\treg_scr = reg_scr_ori = rtw_read16(adapter, REG_SECCFG);\n\t\treg_scr |= (SCR_CHK_KEYID | SCR_RxDecEnable | SCR_TxEncEnable);\n\n\t\tif (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC))\n\t\t\treg_scr |= SCR_CHK_BMC;\n\n\t\tif (_rtw_camctl_chk_flags(adapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH))\n\t\t\treg_scr |= SCR_NoSKMC;\n\n\t\tif (reg_scr != reg_scr_ori)\n\t\t\trtw_write16(adapter, REG_SECCFG, reg_scr);\n\t}\n\t\tbreak;\n\tcase HW_VAR_SEC_DK_CFG: {\n\t\tstruct security_priv *sec = &adapter->securitypriv;\n\t\tu8 reg_scr = rtw_read8(adapter, REG_SECCFG);\n\n\t\tif (val) { /* Enable default key related setting */\n\t\t\treg_scr |= SCR_TXBCUSEDK;\n\t\t\tif (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)\n\t\t\t\treg_scr |= (SCR_RxUseDK | SCR_TxUseDK);\n\t\t} else /* Disable default key related setting */\n\t\t\treg_scr &= ~(SCR_RXBCUSEDK | SCR_TXBCUSEDK | SCR_RxUseDK | SCR_TxUseDK);\n\n\t\trtw_write8(adapter, REG_SECCFG, reg_scr);\n\t}\n\t\tbreak;\n\n\tcase HW_VAR_ASIX_IOT:\n\t\t/* enable  ASIX IOT function */\n\t\tif (*((u8 *)val) == _TRUE) {\n\t\t\t/* 0xa2e[0]=0 (disable rake receiver) */\n\t\t\trtw_write8(adapter, rCCK0_FalseAlarmReport + 2,\n\t\t\t\trtw_read8(adapter, rCCK0_FalseAlarmReport + 2) & ~(BIT0));\n\t\t\t/* 0xa1c=0xa0 (reset channel estimation if signal quality is bad) */\n\t\t\trtw_write8(adapter, rCCK0_DSPParameter2, 0xa0);\n\t\t} else {\n\t\t\t/* restore reg:0xa2e,   reg:0xa1c */\n\t\t\trtw_write8(adapter, rCCK0_FalseAlarmReport + 2,\n\t\t\t\trtw_read8(adapter, rCCK0_FalseAlarmReport + 2) | (BIT0));\n\t\t\trtw_write8(adapter, rCCK0_DSPParameter2, 0x00);\n\t\t}\n\t\tbreak;\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\n\tcase HW_VAR_WOWLAN: {\n\t\tstruct wowlan_ioctl_param *poidparam;\n\n\t\tpoidparam = (struct wowlan_ioctl_param *)val;\n\t\tswitch (poidparam->subcode) {\n#ifdef CONFIG_WOWLAN\n\t\tcase WOWLAN_PATTERN_CLEAN:\n\t\t\trtw_hal_dl_pattern(adapter, 2);\n\t\t\tbreak;\n\t\tcase WOWLAN_ENABLE:\n\t\t\trtw_hal_wow_enable(adapter);\n\t\t\tbreak;\n\t\tcase WOWLAN_DISABLE:\n\t\t\trtw_hal_wow_disable(adapter);\n\t\t\tbreak;\n#endif /*CONFIG_WOWLAN*/\n#ifdef CONFIG_AP_WOWLAN\n\t\tcase WOWLAN_AP_ENABLE:\n\t\t\trtw_hal_ap_wow_enable(adapter);\n\t\t\tbreak;\n\t\tcase WOWLAN_AP_DISABLE:\n\t\t\trtw_hal_ap_wow_disable(adapter);\n\t\t\tbreak;\n#endif /*CONFIG_AP_WOWLAN*/\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\t\tbreak;\n#endif /*defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)*/\n\n\tcase HW_VAR_BCN_FUNC:\n\t\thw_var_set_bcn_func(adapter, *val);\n\t\tbreak;\n\n\tcase HW_VAR_MLME_DISCONNECT:\n\t\thw_var_set_mlme_disconnect(adapter);\n\t\tbreak;\n\n\tcase HW_VAR_MLME_SITESURVEY:\n\t\thw_var_set_mlme_sitesurvey(adapter, *val);\n\t\t#ifdef CONFIG_BT_COEXIST\n\t\tif (hal_data->EEPROMBluetoothCoexist == 1)\n\t\t\trtw_btcoex_ScanNotify(adapter, *val ? _TRUE : _FALSE);\n\t\t#endif\n\t\tbreak;\n\n\tcase HW_VAR_MLME_JOIN:\n\t\thw_var_set_mlme_join(adapter, *val);\n\t\t#ifdef CONFIG_BT_COEXIST\n\t\tif (hal_data->EEPROMBluetoothCoexist == 1) {\n\t\t\tswitch (*val) {\n\t\t\tcase 0:\n\t\t\t\t/* Notify coex. mechanism before join */\n\t\t\t\trtw_btcoex_ConnectNotify(adapter, _TRUE);\n\t\t\t\tbreak;\n\t\t\tcase 1:\n\t\t\tcase 2:\n\t\t\t\t/* Notify coex. mechanism after join, whether successful or failed */\n\t\t\t\trtw_btcoex_ConnectNotify(adapter, _FALSE);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t#endif /* CONFIG_BT_COEXIST */\n\t\tbreak;\n\n\tcase HW_VAR_EN_HW_UPDATE_TSF:\n\t\trtw_hal_set_hw_update_tsf(adapter);\n\t\tbreak;\n\tcase HW_VAR_CORRECT_TSF:\n\t\thw_var_set_correct_tsf(adapter, *val);\n\t\tbreak;\n\n#if defined(CONFIG_HW_P0_TSF_SYNC) && defined(CONFIG_CONCURRENT_MODE)\n\tcase HW_VAR_TSF_AUTO_SYNC:\n\t\tif (*val == _TRUE)\n\t\t\thw_port0_tsf_sync_sel(adapter, _TRUE, adapter->hw_port, 50);\n\t\telse\n\t\t\thw_port0_tsf_sync_sel(adapter, _FALSE, adapter->hw_port, 50);\n\t\tbreak;\n#endif\n\tcase HW_VAR_APFM_ON_MAC:\n\t\thal_data->bMacPwrCtrlOn = *val;\n\t\tRTW_INFO(\"%s: bMacPwrCtrlOn=%d\\n\", __func__, hal_data->bMacPwrCtrlOn);\n\t\tbreak;\n#ifdef CONFIG_WMMPS_STA\n\tcase  HW_VAR_UAPSD_TID:\n\t\trtw_hal_update_uapsd_tid(adapter);\n\t\tbreak;\n#endif /* CONFIG_WMMPS_STA */\n#ifdef CONFIG_LPS_PG\n\tcase HW_VAR_LPS_PG_HANDLE:\n\t\trtw_hal_lps_pg_handler(adapter, *val);\n\t\tbreak;\n#endif\n#ifdef CONFIG_LPS_LCLK_WD_TIMER\n\tcase HW_VAR_DM_IN_LPS_LCLK:\n\t\trtw_phydm_wd_lps_lclk_hdl(adapter);\n\t\tbreak;\n#endif\n\tcase HW_VAR_ENABLE_RX_BAR:\n\t\tif (*val == _TRUE) {\n\t\t\t/* enable RX BAR */\n\t\t\tu16 val16 = rtw_read16(adapter, REG_RXFLTMAP1);\n\n\t\t\tval16 |= BIT(8);\n\t\t\trtw_write16(adapter, REG_RXFLTMAP1, val16);\n\t\t} else {\n\t\t\t/* disable RX BAR */\n\t\t\tu16 val16 = rtw_read16(adapter, REG_RXFLTMAP1);\n\n\t\t\tval16 &= (~BIT(8));\n\t\t\trtw_write16(adapter, REG_RXFLTMAP1, val16);\n\t\t}\n\t\tRTW_INFO(\"[HW_VAR_ENABLE_RX_BAR] 0x%02X=0x%02X\\n\",\n\t\t\tREG_RXFLTMAP1, rtw_read16(adapter, REG_RXFLTMAP1));\n\t\tbreak;\n\tcase HW_VAR_HCI_SUS_STATE:\n\t\thal_data->hci_sus_state = *(u8 *)val;\n\t\tRTW_INFO(\"%s: hci_sus_state=%u\\n\", __func__, hal_data->hci_sus_state);\n\t\tbreak;\n#if defined(CONFIG_AP_MODE) && defined(CONFIG_FW_HANDLE_TXBCN) && defined(CONFIG_SUPPORT_MULTI_BCN)\n\t\tcase HW_VAR_BCN_HEAD_SEL:\n\t\t{\n\t\t\tu8 vap_id = *(u8 *)val;\n\n\t\t\tif ((vap_id >= CONFIG_LIMITED_AP_NUM) && (vap_id != 0xFF)) {\n\t\t\t\tRTW_ERR(ADPT_FMT \" vap_id(%d:%d) is invalid\\n\", ADPT_ARG(adapter),vap_id, adapter->vap_id);\n\t\t\t\trtw_warn_on(1);\n\t\t\t}\n\t\t\tif (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {\n\t\t\t\tu16 drv_pg_bndy = 0, bcn_addr = 0;\n\t\t\t\tu32 page_size = 0;\n\n\t\t\t\t/*rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_BOUNDARY, &drv_pg_bndy);*/\n\t\t\t\trtw_halmac_get_rsvd_drv_pg_bndy(adapter_to_dvobj(adapter), &drv_pg_bndy);\n\t\t\t\trtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&page_size);\n\n\t\t\t\tif (vap_id != 0xFF)\n\t\t\t\t\tbcn_addr = drv_pg_bndy + (vap_id * (MAX_BEACON_LEN / page_size));\n\t\t\t\telse\n\t\t\t\t\tbcn_addr = drv_pg_bndy;\n\t\t\t\tRTW_INFO(ADPT_FMT\" vap_id(%d) change BCN HEAD to 0x%04x\\n\",\n\t\t\t\t\tADPT_ARG(adapter), vap_id, bcn_addr);\n\t\t\t\trtw_write16(adapter, REG_FIFOPAGE_CTRL_2,\n\t\t\t\t\t(bcn_addr & BIT_MASK_BCN_HEAD_1_V1) | BIT_BCN_VALID_V1);\n\t\t\t}\n\t\t}\n\t\tbreak;\n#endif\n\tcase HW_VAR_LPS_STATE_CHK :\n\t\trtw_lps_state_chk(adapter, *(u8 *)val);\n\t\tbreak;\n\n#ifdef CONFIG_RTS_FULL_BW\n\tcase HW_VAR_SET_RTS_BW:\n\t{\n\t\t#ifdef RTW_HALMAC\n\t\t\trtw_halmac_set_rts_full_bw(adapter_to_dvobj(adapter), (*val));\n\t\t#else\n\t\t\tu8 temp;\n\t\t\tif(*val)\n\t\t\t\ttemp = (( rtw_read8(adapter, REG_INIRTS_RATE_SEL)) | BIT5 );\n\t\t\telse\n\t\t\t\ttemp = (( rtw_read8(adapter, REG_INIRTS_RATE_SEL)) & (~BIT5));\n\t\t\trtw_write8(adapter, REG_INIRTS_RATE_SEL, temp);\n\t\t\t/*RTW_INFO(\"HW_VAR_SET_RTS_BW\tval=%u REG480=0x%x\\n\", *val, rtw_read8(adapter, REG_INIRTS_RATE_SEL));*/\n\t\t#endif\n\t}\n\tbreak;\n#endif/*CONFIG_RTS_FULL_BW*/\n#if defined(CONFIG_PCI_HCI)\n\tcase HW_VAR_ENSWBCN: \n\tif (*val == _TRUE) {\n\t\trtw_write8(adapter, REG_CR + 1,\n\t\t\t   rtw_read8(adapter, REG_CR + 1) | BIT(0));\n\t} else\n\t\trtw_write8(adapter, REG_CR + 1,\n\t\t\t   rtw_read8(adapter, REG_CR + 1) & ~BIT(0));\n\tbreak;\n#endif\n\tdefault:\n\t\tif (0)\n\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" variable(%d) not defined!\\n\",\n\t\t\t\t  FUNC_ADPT_ARG(adapter), variable);\n\t\tret = _FAIL;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nvoid GetHwReg(_adapter *adapter, u8 variable, u8 *val)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tu64 val64;\n\n\n\tswitch (variable) {\n\tcase HW_VAR_MAC_ADDR:\n\t\trtw_hal_get_macaddr_port(adapter, val);\n\t\tbreak;\n\tcase HW_VAR_BASIC_RATE:\n\t\t*((u16 *)val) = hal_data->BasicRateSet;\n\t\tbreak;\n\tcase HW_VAR_RF_TYPE:\n\t\t*((u8 *)val) = hal_data->rf_type;\n#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA\t\t\n\t\t*((u8 *)val) = RF_1T1R;\n#endif\n\t\tbreak;\n\tcase HW_VAR_MEDIA_STATUS:\n\t\trtw_hal_get_msr(adapter, val);\n\t\tbreak;\n\tcase HW_VAR_DO_IQK:\n\t\t*val = hal_data->bNeedIQK;\n\t\tbreak;\n\tcase HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO:\n\t\tif (hal_is_band_support(adapter, BAND_ON_5G))\n\t\t\t*val = _TRUE;\n\t\telse\n\t\t\t*val = _FALSE;\n\t\tbreak;\n\tcase HW_VAR_APFM_ON_MAC:\n\t\t*val = hal_data->bMacPwrCtrlOn;\n\t\tbreak;\n\tcase HW_VAR_RCR:\n\t\thw_var_rcr_get(adapter, (u32 *)val);\n\t\tbreak;\n\tcase HW_VAR_FWLPS_RF_ON:\n\t\t/* When we halt NIC, we should check if FW LPS is leave. */\n\t\tif (rtw_is_surprise_removed(adapter)\n\t\t\t|| (adapter_to_pwrctl(adapter)->rf_pwrstate == rf_off)\n\t\t) {\n\t\t\t/*\n\t\t\t * If it is in HW/SW Radio OFF or IPS state,\n\t\t\t * we do not check Fw LPS Leave,\n\t\t\t * because Fw is unload.\n\t\t\t */\n\t\t\t*val = _TRUE;\n\t\t} else {\n\t\t\tu32 rcr = 0;\n\n\t\t\trtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);\n\t\t\tif (rcr & (RCR_UC_MD_EN | RCR_BC_MD_EN | RCR_TIM_PARSER_EN))\n\t\t\t\t*val = _FALSE;\n\t\t\telse\n\t\t\t\t*val = _TRUE;\n\t\t}\n\t\tbreak;\n\n\tcase HW_VAR_HCI_SUS_STATE:\n\t\t*((u8 *)val) = hal_data->hci_sus_state;\n\t\tbreak;\n\n\tcase HW_VAR_BCN_CTRL_ADDR:\n\t\t*((u32 *)val) = hw_bcn_ctrl_addr(adapter, adapter->hw_port);\n\t\tbreak;\n\n#ifdef CONFIG_WAPI_SUPPORT\n\tcase HW_VAR_CAM_EMPTY_ENTRY: {\n\t\tu8\tucIndex = *((u8 *)val);\n\t\tu8\ti;\n\t\tu32\tulCommand = 0;\n\t\tu32\tulContent = 0;\n\t\tu32\tulEncAlgo = CAM_AES;\n\n\t\tfor (i = 0; i < CAM_CONTENT_COUNT; i++) {\n\t\t\t/* filled id in CAM config 2 byte */\n\t\t\tif (i == 0)\n\t\t\t\tulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo) << 2);\n\t\t\telse\n\t\t\t\tulContent = 0;\n\t\t\t/* polling bit, and No Write enable, and address */\n\t\t\tulCommand = CAM_CONTENT_COUNT * ucIndex + i;\n\t\t\tulCommand = ulCommand | CAM_POLLINIG | CAM_WRITE;\n\t\t\t/* write content 0 is equall to mark invalid */\n\t\t\trtw_write32(adapter, REG_CAMWRITE, ulContent);  /* delay_ms(40); */\n\t\t\trtw_write32(adapter, REG_CAMCMD, ulCommand);  /* delay_ms(40); */\n\t\t}\n\t}\n#endif\n\n\tdefault:\n\t\tif (0)\n\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" variable(%d) not defined!\\n\",\n\t\t\t\t  FUNC_ADPT_ARG(adapter), variable);\n\t\tbreak;\n\t}\n\n}\n\nstatic u32 _get_page_size(struct _ADAPTER *a)\n{\n#ifdef RTW_HALMAC\n\tstruct dvobj_priv *d;\n\tu32 size = 0;\n\tint err = 0;\n\n\n\td = adapter_to_dvobj(a);\n\n\terr = rtw_halmac_get_page_size(d, &size);\n\tif (!err)\n\t\treturn size;\n\n\tRTW_WARN(FUNC_ADPT_FMT \": Fail to get Page size!!(err=%d)\\n\",\n\t\t FUNC_ADPT_ARG(a), err);\n#endif /* RTW_HALMAC */\n\n\treturn PAGE_SIZE_128;\n}\n\nu8\nSetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tu8 bResult = _SUCCESS;\n\n\tswitch (variable) {\n\n\tcase HAL_DEF_DBG_DUMP_RXPKT:\n\t\thal_data->bDumpRxPkt = *((u8 *)value);\n\t\tbreak;\n\tcase HAL_DEF_DBG_DUMP_TXPKT:\n\t\thal_data->bDumpTxPkt = *((u8 *)value);\n\t\tbreak;\n\tcase HAL_DEF_ANT_DETECT:\n\t\thal_data->AntDetection = *((u8 *)value);\n\t\tbreak;\n\tdefault:\n\t\tRTW_PRINT(\"%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\\n\", __FUNCTION__, variable);\n\t\tbResult = _FAIL;\n\t\tbreak;\n\t}\n\n\treturn bResult;\n}\n\n#ifdef CONFIG_BEAMFORMING\nu8 rtw_hal_query_txbfer_rf_num(_adapter *adapter)\n{\n\tstruct registry_priv\t*pregistrypriv = &adapter->registrypriv;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\n\tif ((pregistrypriv->beamformer_rf_num) && (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter) || IS_HARDWARE_TYPE_8822BU(adapter) || IS_HARDWARE_TYPE_8821C(adapter)))\n\t\treturn pregistrypriv->beamformer_rf_num;\n\telse if (IS_HARDWARE_TYPE_8814AE(adapter)\n#if 0\n#if defined(CONFIG_USB_HCI)\n\t\t|| (IS_HARDWARE_TYPE_8814AU(adapter) && (pUsbModeMech->CurUsbMode == 2 || pUsbModeMech->HubUsbMode == 2))  /* for USB3.0 */\n#endif\n#endif\n\t\t) {\n\t\t/*BF cap provided by Yu Chen, Sean, 2015, 01 */\n\t\tif (hal_data->rf_type == RF_3T3R)\n\t\t\treturn 2;\n\t\telse if (hal_data->rf_type == RF_4T4R)\n\t\t\treturn 3;\n\t\telse\n\t\t\treturn 1;\n\t} else\n\t\treturn 1;\n\n}\nu8 rtw_hal_query_txbfee_rf_num(_adapter *adapter)\n{\n\tstruct registry_priv\t\t*pregistrypriv = &adapter->registrypriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\n\tif ((pregistrypriv->beamformee_rf_num) && (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter) || IS_HARDWARE_TYPE_8822BU(adapter) || IS_HARDWARE_TYPE_8821C(adapter)))\n\t\treturn pregistrypriv->beamformee_rf_num;\n\telse if (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter)) {\n\t\tif (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM)\n\t\t\treturn 2;\n\t\telse\n\t\t\treturn 2;/*TODO: May be 3 in the future, by ChenYu. */\n\t} else\n\t\treturn 1;\n\n}\n#ifdef RTW_BEAMFORMING_VERSION_2\nvoid rtw_hal_beamforming_config_csirate(PADAPTER adapter)\n{\n\tstruct dm_struct *p_dm_odm;\n\tstruct beamforming_info *bf_info;\n\tu8 fix_rate_enable = 0;\n\tu8 new_csi_rate_idx;\n\tu8 rrsr_54_en;\n\tu32 temp_rrsr;\n\n\t/* Acting as BFee */\n\tif (IS_BEAMFORMEE(adapter)) {\n\t#if 0\n\t\t/* Do not enable now because it will affect MU performance and CTS/BA rate. 2016.07.19. by tynli. [PCIE-1660] */\n\t\tif (IS_HARDWARE_TYPE_8821C(Adapter))\n\t\t\tFixRateEnable = 1;\t/* Support after 8821C */\n\t#endif\n\n\t\tp_dm_odm = adapter_to_phydm(adapter);\n\t\tbf_info = GET_BEAMFORM_INFO(adapter);\n\n\t\trtw_halmac_bf_cfg_csi_rate(adapter_to_dvobj(adapter),\n\t\t\t\tp_dm_odm->rssi_min,\n\t\t\t\tbf_info->cur_csi_rpt_rate,\n\t\t\t\tfix_rate_enable, &new_csi_rate_idx, &rrsr_54_en);\n\n\t\ttemp_rrsr = rtw_read32(adapter,REG_RRSR);\n\t\tif(rrsr_54_en == 1) \n\t\t\ttemp_rrsr |= BIT(HALMAC_OFDM54);\n\t\t else if(rrsr_54_en == 0) \n\t\t\ttemp_rrsr &= ~(BIT(HALMAC_OFDM54));\n\t#ifdef RTW_DYNAMIC_RRSR\n\t\trtw_phydm_set_rrsr(adapter, temp_rrsr, FALSE);\n\t#else\n\t\trtw_write32(adapter, REG_RRSR, temp_rrsr);\n\t#endif\n\n\t\tif (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)\n\t\t\tbf_info->cur_csi_rpt_rate = new_csi_rate_idx;\n\t}\n}\n#endif\n#endif\n\nu8\nGetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tu8 bResult = _SUCCESS;\n\n\tswitch (variable) {\n\tcase HAL_DEF_UNDERCORATEDSMOOTHEDPWDB: {\n\t\tstruct mlme_priv *pmlmepriv;\n\t\tstruct sta_priv *pstapriv;\n\t\tstruct sta_info *psta;\n\n\t\tpmlmepriv = &adapter->mlmepriv;\n\t\tpstapriv = &adapter->stapriv;\n\t\tpsta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);\n\t\tif (psta)\n\t\t\t*((int *)value) = psta->cmn.rssi_stat.rssi;\n\t}\n\tbreak;\n\tcase HAL_DEF_DBG_DUMP_RXPKT:\n\t\t*((u8 *)value) = hal_data->bDumpRxPkt;\n\t\tbreak;\n\tcase HAL_DEF_DBG_DUMP_TXPKT:\n\t\t*((u8 *)value) = hal_data->bDumpTxPkt;\n\t\tbreak;\n\tcase HAL_DEF_ANT_DETECT:\n\t\t*((u8 *)value) = hal_data->AntDetection;\n\t\tbreak;\n\tcase HAL_DEF_TX_PAGE_SIZE:\n\t\t*((u32 *)value) = _get_page_size(adapter);\n\t\tbreak;\n\tcase HAL_DEF_EXPLICIT_BEAMFORMER:\n\tcase HAL_DEF_EXPLICIT_BEAMFORMEE:\n\tcase HAL_DEF_VHT_MU_BEAMFORMER:\n\tcase HAL_DEF_VHT_MU_BEAMFORMEE:\n\t\t*(u8 *)value = _FALSE;\n\t\tbreak;\n#ifdef CONFIG_BEAMFORMING\n\tcase HAL_DEF_BEAMFORMER_CAP:\n\t\t*(u8 *)value = rtw_hal_query_txbfer_rf_num(adapter);\n\t\tbreak;\n\tcase HAL_DEF_BEAMFORMEE_CAP:\n\t\t*(u8 *)value = rtw_hal_query_txbfee_rf_num(adapter);\n\t\tbreak;\n#endif\n\tdefault:\n\t\tRTW_PRINT(\"%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\\n\", __FUNCTION__, variable);\n\t\tbResult = _FAIL;\n\t\tbreak;\n\t}\n\n\treturn bResult;\n}\n\n\nBOOLEAN\neqNByte(\n\tu8\t*str1,\n\tu8\t*str2,\n\tu32\tnum\n)\n{\n\tif (num == 0)\n\t\treturn _FALSE;\n\twhile (num > 0) {\n\t\tnum--;\n\t\tif (str1[num] != str2[num])\n\t\t\treturn _FALSE;\n\t}\n\treturn _TRUE;\n}\n\n/*\n *\tDescription:\n *\t\tTranslate a character to hex digit.\n *   */\nu32\nMapCharToHexDigit(\n\t\t\tchar\t\tchTmp\n)\n{\n\tif (chTmp >= '0' && chTmp <= '9')\n\t\treturn chTmp - '0';\n\telse if (chTmp >= 'a' && chTmp <= 'f')\n\t\treturn 10 + (chTmp - 'a');\n\telse if (chTmp >= 'A' && chTmp <= 'F')\n\t\treturn 10 + (chTmp - 'A');\n\telse\n\t\treturn 0;\n}\n\n\n\n/*\n *\tDescription:\n *\t\tParse hex number from the string pucStr.\n *   */\nBOOLEAN\nGetHexValueFromString(\n\t\tchar\t\t\t*szStr,\n\t\tu32\t\t\t*pu4bVal,\n\t\tu32\t\t\t*pu4bMove\n)\n{\n\tchar\t\t*szScan = szStr;\n\n\t/* Check input parameter. */\n\tif (szStr == NULL || pu4bVal == NULL || pu4bMove == NULL) {\n\t\tRTW_INFO(\"GetHexValueFromString(): Invalid inpur argumetns! szStr: %p, pu4bVal: %p, pu4bMove: %p\\n\", szStr, pu4bVal, pu4bMove);\n\t\treturn _FALSE;\n\t}\n\n\t/* Initialize output. */\n\t*pu4bMove = 0;\n\t*pu4bVal = 0;\n\n\t/* Skip leading space. */\n\twhile (*szScan != '\\0' &&\n\t       (*szScan == ' ' || *szScan == '\\t')) {\n\t\tszScan++;\n\t\t(*pu4bMove)++;\n\t}\n\n\t/* Skip leading '0x' or '0X'. */\n\tif (*szScan == '0' && (*(szScan + 1) == 'x' || *(szScan + 1) == 'X')) {\n\t\tszScan += 2;\n\t\t(*pu4bMove) += 2;\n\t}\n\n\t/* Check if szScan is now pointer to a character for hex digit, */\n\t/* if not, it means this is not a valid hex number. */\n\tif (!IsHexDigit(*szScan))\n\t\treturn _FALSE;\n\n\t/* Parse each digit. */\n\tdo {\n\t\t(*pu4bVal) <<= 4;\n\t\t*pu4bVal += MapCharToHexDigit(*szScan);\n\n\t\tszScan++;\n\t\t(*pu4bMove)++;\n\t} while (IsHexDigit(*szScan));\n\n\treturn _TRUE;\n}\n\nBOOLEAN\nGetFractionValueFromString(\n\t\tchar\t\t\t*szStr,\n\t\tu8\t\t\t\t*pInteger,\n\t\tu8\t\t\t\t*pFraction,\n\t\tu32\t\t\t*pu4bMove\n)\n{\n\tchar\t*szScan = szStr;\n\n\t/* Initialize output. */\n\t*pu4bMove = 0;\n\t*pInteger = 0;\n\t*pFraction = 0;\n\n\t/* Skip leading space. */\n\twhile (*szScan != '\\0' &&\t(*szScan == ' ' || *szScan == '\\t')) {\n\t\t++szScan;\n\t\t++(*pu4bMove);\n\t}\n\n\tif (*szScan < '0' || *szScan > '9')\n\t\treturn _FALSE;\n\n\t/* Parse each digit. */\n\tdo {\n\t\t(*pInteger) *= 10;\n\t\t*pInteger += (*szScan - '0');\n\n\t\t++szScan;\n\t\t++(*pu4bMove);\n\n\t\tif (*szScan == '.') {\n\t\t\t++szScan;\n\t\t\t++(*pu4bMove);\n\n\t\t\tif (*szScan < '0' || *szScan > '9')\n\t\t\t\treturn _FALSE;\n\n\t\t\t*pFraction += (*szScan - '0') * 10;\n\t\t\t++szScan;\n\t\t\t++(*pu4bMove);\n\n\t\t\tif (*szScan >= '0' && *szScan <= '9') {\n\t\t\t\t*pFraction += *szScan - '0';\n\t\t\t\t++szScan;\n\t\t\t\t++(*pu4bMove);\n\t\t\t}\n\t\t\treturn _TRUE;\n\t\t}\n\t} while (*szScan >= '0' && *szScan <= '9');\n\n\treturn _TRUE;\n}\n\n/*\n *\tDescription:\n * Return TRUE if szStr is comment out with leading \" */ /* \".\n *   */\nBOOLEAN\nIsCommentString(\n\t\tchar\t\t\t*szStr\n)\n{\n\tif (*szStr == '/' && *(szStr + 1) == '/')\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\n\nBOOLEAN\nGetU1ByteIntegerFromStringInDecimal(\n\t\tchar\t*Str,\n\t\tu8\t\t*pInt\n)\n{\n\tu16 i = 0;\n\t*pInt = 0;\n\n\twhile (Str[i] != '\\0') {\n\t\tif (Str[i] >= '0' && Str[i] <= '9') {\n\t\t\t*pInt *= 10;\n\t\t\t*pInt += (Str[i] - '0');\n\t\t} else\n\t\t\treturn _FALSE;\n\t\t++i;\n\t}\n\n\treturn _TRUE;\n}\n\n/* <20121004, Kordan> For example,\n * ParseQualifiedString(inString, 0, outString, '[', ']') gets \"Kordan\" from a string \"Hello [Kordan]\".\n * If RightQualifier does not exist, it will hang on in the while loop */\nBOOLEAN\nParseQualifiedString(\n\t\t\tchar\t*In,\n\t\t\tu32\t*Start,\n\t\t\tchar\t*Out,\n\t\t\tchar\t\tLeftQualifier,\n\t\t\tchar\t\tRightQualifier\n)\n{\n\tu32\ti = 0, j = 0;\n\tchar\tc = In[(*Start)++];\n\n\tif (c != LeftQualifier)\n\t\treturn _FALSE;\n\n\ti = (*Start);\n\tc = In[(*Start)++];\n\twhile (c != RightQualifier && c != '\\0')\n\t\tc = In[(*Start)++];\n\n\tif (c == '\\0')\n\t\treturn _FALSE;\n\n\tj = (*Start) - 2;\n\tstrncpy((char *)Out, (const char *)(In + i), j - i + 1);\n\n\treturn _TRUE;\n}\n\nBOOLEAN\nisAllSpaceOrTab(\n\tu8\t*data,\n\tu8\tsize\n)\n{\n\tu8\tcnt = 0, NumOfSpaceAndTab = 0;\n\n\twhile (size > cnt) {\n\t\tif (data[cnt] == ' ' || data[cnt] == '\\t' || data[cnt] == '\\0')\n\t\t\t++NumOfSpaceAndTab;\n\n\t\t++cnt;\n\t}\n\n\treturn size == NumOfSpaceAndTab;\n}\n\n\nvoid rtw_hal_check_rxfifo_full(_adapter *adapter)\n{\n\tstruct dvobj_priv *psdpriv = adapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &psdpriv->drv_dbg;\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);\n\tstruct registry_priv *regsty = &adapter->registrypriv;\n\tint save_cnt = _FALSE;\n\n\tif (regsty->check_hw_status == 1) {\n\t\t/* switch counter to RX fifo */\n\t\tif (IS_8188E(pHalData->version_id) ||\n\t\t    IS_8188F(pHalData->version_id) ||\n\t\t    IS_8188GTV(pHalData->version_id) ||\n\t\t    IS_8812_SERIES(pHalData->version_id) ||\n\t\t    IS_8821_SERIES(pHalData->version_id) ||\n\t\t    IS_8723B_SERIES(pHalData->version_id) ||\n\t\t    IS_8192E(pHalData->version_id) ||\n\t\t    IS_8703B_SERIES(pHalData->version_id) ||\n\t\t    IS_8723D_SERIES(pHalData->version_id) ||\n\t\t    IS_8192F_SERIES(pHalData->version_id)) {\n\t\t\trtw_write8(adapter, REG_RXERR_RPT + 3, rtw_read8(adapter, REG_RXERR_RPT + 3) | 0xa0);\n\t\t\tsave_cnt = _TRUE;\n\t\t} else {\n\t\t\t/* todo: other chips */\n\t\t}\n\n\n\t\tif (save_cnt) {\n\t\t\tpdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow;\n\t\t\tpdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT);\n\t\t\tpdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow - pdbgpriv->dbg_rx_fifo_last_overflow;\n\t\t} else {\n\t\t\t/* special value to indicate no implementation */\n\t\t\tpdbgpriv->dbg_rx_fifo_last_overflow = 1;\n\t\t\tpdbgpriv->dbg_rx_fifo_curr_overflow = 1;\n\t\t\tpdbgpriv->dbg_rx_fifo_diff_overflow = 1;\n\t\t}\n\t}\n}\n\nvoid linked_info_dump(_adapter *padapter, u8 benable)\n{\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n\n\tif (padapter->bLinkInfoDump == benable)\n\t\treturn;\n\n\tRTW_INFO(\"%s %s\\n\", __FUNCTION__, (benable) ? \"enable\" : \"disable\");\n\n\tif (benable) {\n#ifdef CONFIG_LPS\n\t\tpwrctrlpriv->org_power_mgnt = pwrctrlpriv->power_mgnt;/* keep org value */\n\t\trtw_pm_set_lps(padapter, PS_MODE_ACTIVE);\n#endif\n\n#ifdef CONFIG_IPS\n\t\tpwrctrlpriv->ips_org_mode = pwrctrlpriv->ips_mode;/* keep org value */\n\t\trtw_pm_set_ips(padapter, IPS_NONE);\n#endif\n\t} else {\n#ifdef CONFIG_IPS\n\t\trtw_pm_set_ips(padapter, pwrctrlpriv->ips_org_mode);\n#endif /* CONFIG_IPS */\n\n#ifdef CONFIG_LPS\n\t\trtw_pm_set_lps(padapter, pwrctrlpriv->org_power_mgnt);\n#endif /* CONFIG_LPS */\n\t}\n\tpadapter->bLinkInfoDump = benable ;\n}\n\n#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA\nvoid rtw_get_raw_rssi_info(void *sel, _adapter *padapter)\n{\n\tu8 isCCKrate, rf_path;\n\tPHAL_DATA_TYPE\tpHalData =  GET_HAL_DATA(padapter);\n\tstruct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;\n\tRTW_PRINT_SEL(sel, \"RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\\n\",\n\t\tHDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);\n\tisCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? TRUE : FALSE;\n\n\tif (isCCKrate)\n\t\tpsample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball;\n\n\tfor (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {\n\t\tRTW_PRINT_SEL(sel, \"RF_PATH_%d=>signal_strength:%d(%%),signal_quality:%d(%%)\\n\"\n\t\t\t, rf_path, psample_pkt_rssi->mimo_signal_strength[rf_path], psample_pkt_rssi->mimo_signal_quality[rf_path]);\n\n\t\tif (!isCCKrate) {\n\t\t\tRTW_PRINT_SEL(sel, \"\\trx_ofdm_pwr:%d(dBm),rx_ofdm_snr:%d(dB)\\n\",\n\t\t\t\tpsample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);\n\t\t}\n\t}\n}\n\nvoid rtw_dump_raw_rssi_info(_adapter *padapter, void *sel)\n{\n\tu8 isCCKrate, rf_path;\n\tPHAL_DATA_TYPE\tpHalData =  GET_HAL_DATA(padapter);\n\tstruct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;\n\t_RTW_PRINT_SEL(sel, \"============ RAW Rx Info dump ===================\\n\");\n\t_RTW_PRINT_SEL(sel, \"RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\\n\", HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);\n\n\tisCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? TRUE : FALSE;\n\n\tif (isCCKrate)\n\t\tpsample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball;\n\n\tfor (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {\n\t\t_RTW_PRINT_SEL(sel , \"RF_PATH_%d=>signal_strength:%d(%%),signal_quality:%d(%%)\"\n\t\t\t, rf_path, psample_pkt_rssi->mimo_signal_strength[rf_path], psample_pkt_rssi->mimo_signal_quality[rf_path]);\n\n\t\tif (!isCCKrate)\n\t\t\t_RTW_PRINT_SEL(sel , \",rx_ofdm_pwr:%d(dBm),rx_ofdm_snr:%d(dB)\\n\", psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);\n\t\telse\n\t\t\t_RTW_PRINT_SEL(sel , \"\\n\");\n\n\t}\n}\n#endif\n\n#ifdef DBG_RX_DFRAME_RAW_DATA\nvoid rtw_dump_rx_dframe_info(_adapter *padapter, void *sel)\n{\n#define DBG_RX_DFRAME_RAW_DATA_UC\t\t0\n#define DBG_RX_DFRAME_RAW_DATA_BMC\t\t1\n#define DBG_RX_DFRAME_RAW_DATA_TYPES\t2\n\n\t_irqL irqL;\n\tu8 isCCKrate, rf_path;\n\tstruct recv_priv *precvpriv = &(padapter->recvpriv);\n\tPHAL_DATA_TYPE\tpHalData =  GET_HAL_DATA(padapter);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct sta_info *psta;\n\tstruct sta_recv_dframe_info *psta_dframe_info;\n\tint i, j;\n\t_list\t*plist, *phead;\n\tu8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tu8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};\n\n\tif (precvpriv->store_law_data_flag) {\n\n\t\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\t\tfor (i = 0; i < NUM_STA; i++) {\n\t\t\tphead = &(pstapriv->sta_hash[i]);\n\t\t\tplist = get_next(phead);\n\n\t\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\n\t\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\t\t\t\tplist = get_next(plist);\n\n\t\t\t\tif (psta) {\n\t\t\t\t\tif ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)  !=   _TRUE)\n\t\t\t\t\t    && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN)  !=  _TRUE)\n\t\t\t\t\t    && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN)  !=  _TRUE)) {\n\n\t\t\t\t\t\tRTW_PRINT_SEL(sel, \"==============================\\n\");\n\t\t\t\t\t\tRTW_PRINT_SEL(sel, \"macaddr =\" MAC_FMT \"\\n\", MAC_ARG(psta->cmn.mac_addr));\n\n\t\t\t\t\t\tfor (j = 0; j < DBG_RX_DFRAME_RAW_DATA_TYPES; j++) {\n\t\t\t\t\t\t\tif (j == DBG_RX_DFRAME_RAW_DATA_UC) {\n\t\t\t\t\t\t\t\tpsta_dframe_info = &psta->sta_dframe_info;\n\t\t\t\t\t\t\t\tRTW_PRINT_SEL(sel, \"\\n\");\n\t\t\t\t\t\t\t\tRTW_PRINT_SEL(sel, \"Unicast:\\n\");\n\t\t\t\t\t\t\t} else if (j == DBG_RX_DFRAME_RAW_DATA_BMC) {\n\t\t\t\t\t\t\t\tpsta_dframe_info = &psta->sta_dframe_info_bmc;\n\t\t\t\t\t\t\t\tRTW_PRINT_SEL(sel, \"\\n\");\n\t\t\t\t\t\t\t\tRTW_PRINT_SEL(sel, \"Broadcast/Multicast:\\n\");\n\t\t\t\t\t\t\t}\n\n\t\t\t\t\t\t\tisCCKrate = (psta_dframe_info->sta_data_rate <= DESC_RATE11M) ? TRUE : FALSE;\n\n\t\t\t\t\t\t\tRTW_PRINT_SEL(sel, \"BW=%s, sgi =%d\\n\", ch_width_str(psta_dframe_info->sta_bw_mode), psta_dframe_info->sta_sgi);\n\t\t\t\t\t\t\tRTW_PRINT_SEL(sel, \"Rx_Data_Rate = %s\\n\", HDATA_RATE(psta_dframe_info->sta_data_rate));\n\n\t\t\t\t\t\t\tfor (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {\n\t\t\t\t\t\t\t\tif (!isCCKrate) {\n\t\t\t\t\t\t\t\t\tRTW_PRINT_SEL(sel , \"RF_PATH_%d RSSI:%d(dBm)\", rf_path, psta_dframe_info->sta_RxPwr[rf_path]);\n\t\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(sel , \",rx_ofdm_snr:%d(dB)\\n\", psta_dframe_info->sta_ofdm_snr[rf_path]);\n\t\t\t\t\t\t\t\t} else\n\t\t\t\t\t\t\t\t\tRTW_PRINT_SEL(sel , \"RF_PATH_%d RSSI:%d(dBm)\\n\", rf_path, (psta_dframe_info->sta_mimo_signal_strength[rf_path]) - 100);\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\t}\n}\n#endif\nvoid rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe)\n{\n\tu8 isCCKrate, rf_path , dframe_type;\n\tu8 *ptr;\n\tu8\tbc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n#ifdef DBG_RX_DFRAME_RAW_DATA\n\tstruct sta_recv_dframe_info *psta_dframe_info;\n#endif\n\tstruct recv_priv *precvpriv = &(padapter->recvpriv);\n\tPHAL_DATA_TYPE\tpHalData =  GET_HAL_DATA(padapter);\n\tstruct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;\n\tstruct sta_info *psta = prframe->u.hdr.psta;\n\tstruct phydm_phyinfo_struct *p_phy_info = &pattrib->phy_info;\n\tstruct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;\n\tpsample_pkt_rssi->data_rate = pattrib->data_rate;\n\tptr = prframe->u.hdr.rx_data;\n\tdframe_type = GetFrameType(ptr);\n\t/*RTW_INFO(\"=>%s\\n\", __FUNCTION__);*/\n\n\n\tif (precvpriv->store_law_data_flag) {\n\t\tisCCKrate = (pattrib->data_rate <= DESC_RATE11M) ? TRUE : FALSE;\n\n\t\tpsample_pkt_rssi->pwdball = p_phy_info->rx_pwdb_all;\n\t\tpsample_pkt_rssi->pwr_all = p_phy_info->recv_signal_power;\n\n\t\tfor (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {\n\t\t\tpsample_pkt_rssi->mimo_signal_strength[rf_path] = p_phy_info->rx_mimo_signal_strength[rf_path];\n\t\t\tpsample_pkt_rssi->mimo_signal_quality[rf_path] = p_phy_info->rx_mimo_signal_quality[rf_path];\n\t\t\tif (!isCCKrate) {\n\t\t\t\tpsample_pkt_rssi->ofdm_pwr[rf_path] = p_phy_info->rx_pwr[rf_path];\n\t\t\t\tpsample_pkt_rssi->ofdm_snr[rf_path] = p_phy_info->rx_snr[rf_path];\n\t\t\t}\n\t\t}\n#ifdef DBG_RX_DFRAME_RAW_DATA\n\t\tif ((dframe_type == WIFI_DATA_TYPE) || (dframe_type == WIFI_QOS_DATA_TYPE) || (padapter->registrypriv.mp_mode == 1)) {\n\n\t\t\t/*RTW_INFO(\"=>%s WIFI_DATA_TYPE or WIFI_QOS_DATA_TYPE\\n\", __FUNCTION__);*/\n\t\t\tif (psta) {\n\t\t\t\tif (IS_MCAST(get_ra(get_recvframe_data(prframe))))\n\t\t\t\t\tpsta_dframe_info = &psta->sta_dframe_info_bmc;\n\t\t\t\telse\n\t\t\t\t\tpsta_dframe_info = &psta->sta_dframe_info;\n\t\t\t\t/*RTW_INFO(\"=>%s psta->cmn.mac_addr=\"MAC_FMT\" !\\n\",\n\t\t\t\t\t__FUNCTION__, MAC_ARG(psta->cmn.mac_addr));*/\n\t\t\t\tif ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) != _TRUE) || (padapter->registrypriv.mp_mode == 1)) {\n\t\t\t\t\tpsta_dframe_info->sta_data_rate = pattrib->data_rate;\n\t\t\t\t\tpsta_dframe_info->sta_sgi = pattrib->sgi;\n\t\t\t\t\tpsta_dframe_info->sta_bw_mode = pattrib->bw;\n\t\t\t\t\tfor (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {\n\n\t\t\t\t\t\tpsta_dframe_info->sta_mimo_signal_strength[rf_path] = (p_phy_info->rx_mimo_signal_strength[rf_path]);/*Percentage to dbm*/\n\n\t\t\t\t\t\tif (!isCCKrate) {\n\t\t\t\t\t\t\tpsta_dframe_info->sta_ofdm_snr[rf_path] = p_phy_info->rx_snr[rf_path];\n\t\t\t\t\t\t\tpsta_dframe_info->sta_RxPwr[rf_path] = p_phy_info->rx_pwr[rf_path];\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n#endif\n\t}\n\n}\n\nint hal_efuse_macaddr_offset(_adapter *adapter)\n{\n\tu8 interface_type = 0;\n\tint addr_offset = -1;\n\n\tinterface_type = rtw_get_intf_type(adapter);\n\n\tswitch (rtw_get_chip_type(adapter)) {\n#ifdef CONFIG_RTL8723B\n\tcase RTL8723B:\n\t\tif (interface_type == RTW_USB)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8723BU;\n\t\telse if (interface_type == RTW_SDIO)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8723BS;\n\t\telse if (interface_type == RTW_PCIE)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8723BE;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8703B\n\tcase RTL8703B:\n\t\tif (interface_type == RTW_USB)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8703BU;\n\t\telse if (interface_type == RTW_SDIO)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8703BS;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8723D\n\tcase RTL8723D:\n\t\tif (interface_type == RTW_USB)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8723DU;\n\t\telse if (interface_type == RTW_SDIO)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8723DS;\n\t\telse if (interface_type == RTW_PCIE)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8723DE;\n\t\tbreak;\n#endif\n\n#ifdef CONFIG_RTL8188E\n\tcase RTL8188E:\n\t\tif (interface_type == RTW_USB)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_88EU;\n\t\telse if (interface_type == RTW_SDIO)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_88ES;\n\t\telse if (interface_type == RTW_PCIE)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_88EE;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8188F\n\tcase RTL8188F:\n\t\tif (interface_type == RTW_USB)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8188FU;\n\t\telse if (interface_type == RTW_SDIO)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8188FS;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8188GTV\n\tcase RTL8188GTV:\n\t\tif (interface_type == RTW_USB)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8188GTVU;\n\t\telse if (interface_type == RTW_SDIO)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8188GTVS;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8812A\n\tcase RTL8812:\n\t\tif (interface_type == RTW_USB)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8812AU;\n\t\telse if (interface_type == RTW_PCIE)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8812AE;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8821A\n\tcase RTL8821:\n\t\tif (interface_type == RTW_USB)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8821AU;\n\t\telse if (interface_type == RTW_SDIO)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8821AS;\n\t\telse if (interface_type == RTW_PCIE)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8821AE;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8192E\n\tcase RTL8192E:\n\t\tif (interface_type == RTW_USB)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8192EU;\n\t\telse if (interface_type == RTW_SDIO)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8192ES;\n\t\telse if (interface_type == RTW_PCIE)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8192EE;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8814A\n\tcase RTL8814A:\n\t\tif (interface_type == RTW_USB)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8814AU;\n\t\telse if (interface_type == RTW_PCIE)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8814AE;\n\t\tbreak;\n#endif\n\n#ifdef CONFIG_RTL8822B\n\tcase RTL8822B:\n\t\tif (interface_type == RTW_USB)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8822BU;\n\t\telse if (interface_type == RTW_SDIO)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8822BS;\n\t\telse if (interface_type == RTW_PCIE)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8822BE;\n\t\tbreak;\n#endif /* CONFIG_RTL8822B */\n\n#ifdef CONFIG_RTL8821C\n\tcase RTL8821C:\n\t\tif (interface_type == RTW_USB)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8821CU;\n\t\telse if (interface_type == RTW_SDIO)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8821CS;\n\t\telse if (interface_type == RTW_PCIE)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8821CE;\n\t\tbreak;\n#endif /* CONFIG_RTL8821C */\n\n#ifdef CONFIG_RTL8710B\n\tcase RTL8710B:\n\t\tif (interface_type == RTW_USB)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8710B;\n\t\tbreak;\n#endif\n\n#ifdef CONFIG_RTL8192F\n\tcase RTL8192F:\n\t\tif (interface_type == RTW_USB)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8192FU;\n\t\telse if (interface_type == RTW_SDIO)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8192FS;\n\t\telse if (interface_type == RTW_PCIE)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8192FE;\n\t\tbreak;\n#endif /* CONFIG_RTL8192F */\n\n#ifdef CONFIG_RTL8822C\n\tcase RTL8822C:\n\t\tif (interface_type == RTW_USB)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8822CU;\n\t\telse if (interface_type == RTW_SDIO)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8822CS;\n\t\telse if (interface_type == RTW_PCIE)\n\t\t\taddr_offset = EEPROM_MAC_ADDR_8822CE;\n\t\tbreak;\n#endif /* CONFIG_RTL8822C */\n\n\t}\n\n\tif (addr_offset == -1) {\n\t\tRTW_ERR(\"%s: unknown combination - chip_type:%u, interface:%u\\n\"\n\t\t\t, __func__, rtw_get_chip_type(adapter), rtw_get_intf_type(adapter));\n\t}\n\n\treturn addr_offset;\n}\n\nint Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr)\n{\n\tint ret = _FAIL;\n\tint addr_offset;\n\n\taddr_offset = hal_efuse_macaddr_offset(padapter);\n\tif (addr_offset == -1)\n\t\tgoto exit;\n\n\tret = rtw_efuse_map_read(padapter, addr_offset, ETH_ALEN, mac_addr);\n\nexit:\n\treturn ret;\n}\n\nvoid rtw_dump_cur_efuse(PADAPTER padapter)\n{\n\tint i =0;\n\tint mapsize =0;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);\n\n\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapsize, _FALSE);\n\n\tif (mapsize <= 0 || mapsize > EEPROM_MAX_SIZE) {\n\t\tRTW_ERR(\"wrong map size %d\\n\", mapsize);\n\t\treturn;\n\t}\n\n#ifdef CONFIG_RTW_DEBUG\n\tif (hal_data->efuse_file_status == EFUSE_FILE_LOADED)\n\t\tRTW_MAP_DUMP_SEL(RTW_DBGDUMP, \"EFUSE FILE\", hal_data->efuse_eeprom_data, mapsize);\n\telse\n\t\tRTW_MAP_DUMP_SEL(RTW_DBGDUMP, \"HW EFUSE\", hal_data->efuse_eeprom_data, mapsize);\n#endif\n}\n\n\n#ifdef CONFIG_EFUSE_CONFIG_FILE\nu32 Hal_readPGDataFromConfigFile(PADAPTER padapter)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);\n\tu32 ret = _FALSE;\n\tu32 maplen = 0;\n\n\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&maplen, _FALSE);\n\n\tif (maplen < 256 || maplen > EEPROM_MAX_SIZE) {\n\t\tRTW_ERR(\"eFuse length error :%d\\n\", maplen);\n\t\treturn _FALSE;\n\t}\t\n\n\tret = rtw_read_efuse_from_file(EFUSE_MAP_PATH, hal_data->efuse_eeprom_data, maplen);\n\n\thal_data->efuse_file_status = ((ret == _FAIL) ? EFUSE_FILE_FAILED : EFUSE_FILE_LOADED);\n\n\tif (hal_data->efuse_file_status == EFUSE_FILE_LOADED)\n\t\trtw_dump_cur_efuse(padapter);\n\n\treturn ret;\n}\n\nu32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);\n\tu32 ret = _FAIL;\n\n\tif (rtw_read_macaddr_from_file(WIFIMAC_PATH, mac_addr) == _SUCCESS\n\t\t&& rtw_check_invalid_mac_address(mac_addr, _TRUE) == _FALSE\n\t) {\n\t\thal_data->macaddr_file_status = MACADDR_FILE_LOADED;\n\t\tret = _SUCCESS;\n\t} else\n\t\thal_data->macaddr_file_status = MACADDR_FILE_FAILED;\n\n\treturn ret;\n}\n#endif /* CONFIG_EFUSE_CONFIG_FILE */\n\nint hal_config_macaddr(_adapter *adapter, bool autoload_fail)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tu8 addr[ETH_ALEN];\n\tint addr_offset = hal_efuse_macaddr_offset(adapter);\n\tu8 *hw_addr = NULL;\n\tint ret = _SUCCESS;\n#if defined(CONFIG_RTL8822B) && defined(CONFIG_USB_HCI)\n\tu8 ft_mac_addr[ETH_ALEN] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff}; /* FT USB2 for 8822B */\n#endif\n\n\tif (autoload_fail)\n\t\tgoto bypass_hw_pg;\n\n\tif (addr_offset != -1)\n\t\thw_addr = &hal_data->efuse_eeprom_data[addr_offset];\n\n#ifdef CONFIG_EFUSE_CONFIG_FILE\n\t/* if the hw_addr is written by efuse file, set to NULL */\n\tif (hal_data->efuse_file_status == EFUSE_FILE_LOADED)\n\t\thw_addr = NULL;\n#endif\n\n\tif (!hw_addr) {\n\t\t/* try getting hw pg data */\n\t\tif (Hal_GetPhyEfuseMACAddr(adapter, addr) == _SUCCESS)\n\t\t\thw_addr = addr;\n\t}\n\n#if defined(CONFIG_RTL8822B) && defined(CONFIG_USB_HCI)\n\tif (_rtw_memcmp(hw_addr, ft_mac_addr, ETH_ALEN))\n\t\thw_addr[0] = 0xff;\n#endif\n\n\t/* check hw pg data */\n\tif (hw_addr && rtw_check_invalid_mac_address(hw_addr, _TRUE) == _FALSE) {\n\t\t_rtw_memcpy(hal_data->EEPROMMACAddr, hw_addr, ETH_ALEN);\n\t\tgoto exit;\n\t}\n\nbypass_hw_pg:\n\n#ifdef CONFIG_EFUSE_CONFIG_FILE\n\t/* check wifi mac file */\n\tif (Hal_ReadMACAddrFromFile(adapter, addr) == _SUCCESS) {\n\t\t_rtw_memcpy(hal_data->EEPROMMACAddr, addr, ETH_ALEN);\n\t\tgoto exit;\n\t}\n#endif\n\n\t_rtw_memset(hal_data->EEPROMMACAddr, 0, ETH_ALEN);\n\tret = _FAIL;\n\nexit:\n\treturn ret;\n}\n\n#ifdef CONFIG_RF_POWER_TRIM\nu32 Array_kfreemap[] = {\n\t0x08, 0xe,\n\t0x06, 0xc,\n\t0x04, 0xa,\n\t0x02, 0x8,\n\t0x00, 0x6,\n\t0x03, 0x4,\n\t0x05, 0x2,\n\t0x07, 0x0,\n\t0x09, 0x0,\n\t0x0c, 0x0,\n};\n\nvoid rtw_bb_rf_gain_offset(_adapter *padapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct registry_priv  *registry_par = &padapter->registrypriv;\n\tstruct kfree_data_t *kfree_data = &pHalData->kfree_data;\n\tu8\t\tvalue = pHalData->EEPROMRFGainOffset;\n\tu8\t\ttmp = 0x3e;\n\tu32\t\tres, i = 0;\n\tu32\t\tArrayLen\t= sizeof(Array_kfreemap) / sizeof(u32);\n\tu32\t\t*Array = Array_kfreemap;\n\tu32\t\tv1 = 0, v2 = 0, GainValue = 0, target = 0;\n\n\tif (registry_par->RegPwrTrimEnable == 2) {\n\t\tRTW_INFO(\"Registry kfree default force disable.\\n\");\n\t\treturn;\n\t}\n\n#if defined(CONFIG_RTL8723B)\n\tif (value & BIT4 && (registry_par->RegPwrTrimEnable == 1)) {\n\t\tRTW_INFO(\"Offset RF Gain.\\n\");\n\t\tRTW_INFO(\"Offset RF Gain.  pHalData->EEPROMRFGainVal=0x%x\\n\", pHalData->EEPROMRFGainVal);\n\n\t\tif (pHalData->EEPROMRFGainVal != 0xff) {\n\n\t\t\tif (pHalData->ant_path == RF_PATH_A)\n\t\t\t\tGainValue = (pHalData->EEPROMRFGainVal & 0x0f);\n\n\t\t\telse\n\t\t\t\tGainValue = (pHalData->EEPROMRFGainVal & 0xf0) >> 4;\n\t\t\tRTW_INFO(\"Ant PATH_%d GainValue Offset = 0x%x\\n\", (pHalData->ant_path == RF_PATH_A) ? (RF_PATH_A) : (RF_PATH_B), GainValue);\n\n\t\t\tfor (i = 0; i < ArrayLen; i += 2) {\n\t\t\t\t/* RTW_INFO(\"ArrayLen in =%d ,Array 1 =0x%x ,Array2 =0x%x\\n\",i,Array[i],Array[i]+1); */\n\t\t\t\tv1 = Array[i];\n\t\t\t\tv2 = Array[i + 1];\n\t\t\t\tif (v1 == GainValue) {\n\t\t\t\t\tRTW_INFO(\"Offset RF Gain. got v1 =0x%x ,v2 =0x%x\\n\", v1, v2);\n\t\t\t\t\ttarget = v2;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\tRTW_INFO(\"pHalData->EEPROMRFGainVal=0x%x ,Gain offset Target Value=0x%x\\n\", pHalData->EEPROMRFGainVal, target);\n\n\t\t\tres = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);\n\t\t\tRTW_INFO(\"Offset RF Gain. before reg 0x7f=0x%08x\\n\", res);\n\t\t\tphy_set_rf_reg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18 | BIT17 | BIT16 | BIT15, target);\n\t\t\tres = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);\n\n\t\t\tRTW_INFO(\"Offset RF Gain. After reg 0x7f=0x%08x\\n\", res);\n\n\t\t} else\n\n\t\t\tRTW_INFO(\"Offset RF Gain.  pHalData->EEPROMRFGainVal=0x%x\t!= 0xff, didn't run Kfree\\n\", pHalData->EEPROMRFGainVal);\n\t} else\n\t\tRTW_INFO(\"Using the default RF gain.\\n\");\n\n#elif defined(CONFIG_RTL8188E)\n\tif (value & BIT4 && (registry_par->RegPwrTrimEnable == 1)) {\n\t\tRTW_INFO(\"8188ES Offset RF Gain.\\n\");\n\t\tRTW_INFO(\"8188ES Offset RF Gain. EEPROMRFGainVal=0x%x\\n\",\n\t\t\t pHalData->EEPROMRFGainVal);\n\n\t\tif (pHalData->EEPROMRFGainVal != 0xff) {\n\t\t\tres = rtw_hal_read_rfreg(padapter, RF_PATH_A,\n\t\t\t\t\t REG_RF_BB_GAIN_OFFSET, 0xffffffff);\n\n\t\t\tRTW_INFO(\"Offset RF Gain. reg 0x55=0x%x\\n\", res);\n\t\t\tres &= 0xfff87fff;\n\n\t\t\tres |= (pHalData->EEPROMRFGainVal & 0x0f) << 15;\n\t\t\tRTW_INFO(\"Offset RF Gain. res=0x%x\\n\", res);\n\n\t\t\trtw_hal_write_rfreg(padapter, RF_PATH_A,\n\t\t\t\t\t    REG_RF_BB_GAIN_OFFSET,\n\t\t\t\t\t    RF_GAIN_OFFSET_MASK, res);\n\t\t} else {\n\t\t\tRTW_INFO(\"Offset RF Gain. EEPROMRFGainVal=0x%x == 0xff, didn't run Kfree\\n\",\n\t\t\t\t pHalData->EEPROMRFGainVal);\n\t\t}\n\t} else\n\t\tRTW_INFO(\"Using the default RF gain.\\n\");\n#else\n\t/* TODO: call this when channel switch */\n\tif (kfree_data->flag & KFREE_FLAG_ON)\n\t\trtw_rf_apply_tx_gain_offset(padapter, 6); /* input ch6 to select BB_GAIN_2G */\n#endif\n\n}\n#endif /*CONFIG_RF_POWER_TRIM */\n\nbool kfree_data_is_bb_gain_empty(struct kfree_data_t *data)\n{\n#ifdef CONFIG_RF_POWER_TRIM\n\tint i, j;\n\n\tfor (i = 0; i < BB_GAIN_NUM; i++)\n\t\tfor (j = 0; j < RF_PATH_MAX; j++)\n\t\t\tif (data->bb_gain[i][j] != 0)\n\t\t\t\treturn 0;\n#endif\n\treturn 1;\n}\n\n#ifdef CONFIG_USB_RX_AGGREGATION\nvoid rtw_set_usb_agg_by_mode_normal(_adapter *padapter, u8 cur_wireless_mode)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tif (cur_wireless_mode < WIRELESS_11_24N\n\t    && cur_wireless_mode > 0) { /* ABG mode */\n#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER\n\t\tu32 remainder = 0;\n\t\tu8 quotient = 0;\n\n\t\tremainder = MAX_RECVBUF_SZ % (4 * 1024);\n\t\tquotient = (u8)(MAX_RECVBUF_SZ >> 12);\n\n\t\tif (quotient > 5) {\n\t\t\tpHalData->rxagg_usb_size = 0x6;\n\t\t\tpHalData->rxagg_usb_timeout = 0x10;\n\t\t} else {\n\t\t\tif (remainder >= 2048) {\n\t\t\t\tpHalData->rxagg_usb_size = quotient;\n\t\t\t\tpHalData->rxagg_usb_timeout = 0x10;\n\t\t\t} else {\n\t\t\t\tpHalData->rxagg_usb_size = (quotient - 1);\n\t\t\t\tpHalData->rxagg_usb_timeout = 0x10;\n\t\t\t}\n\t\t}\n#else /* !CONFIG_PREALLOC_RX_SKB_BUFFER */\n\t\tif (0x6 != pHalData->rxagg_usb_size || 0x10 != pHalData->rxagg_usb_timeout) {\n\t\t\tpHalData->rxagg_usb_size = 0x6;\n\t\t\tpHalData->rxagg_usb_timeout = 0x10;\n\t\t\trtw_write16(padapter, REG_RXDMA_AGG_PG_TH,\n\t\t\t\tpHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));\n\t\t}\n#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */\n\n\t} else if (cur_wireless_mode >= WIRELESS_11_24N\n\t\t   && cur_wireless_mode <= WIRELESS_MODE_MAX) { /* N AC mode */\n#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER\n\t\tu32 remainder = 0;\n\t\tu8 quotient = 0;\n\n\t\tremainder = MAX_RECVBUF_SZ % (4 * 1024);\n\t\tquotient = (u8)(MAX_RECVBUF_SZ >> 12);\n\n\t\tif (quotient > 5) {\n\t\t\tpHalData->rxagg_usb_size = 0x5;\n\t\t\tpHalData->rxagg_usb_timeout = 0x20;\n\t\t} else {\n\t\t\tif (remainder >= 2048) {\n\t\t\t\tpHalData->rxagg_usb_size = quotient;\n\t\t\t\tpHalData->rxagg_usb_timeout = 0x10;\n\t\t\t} else {\n\t\t\t\tpHalData->rxagg_usb_size = (quotient - 1);\n\t\t\t\tpHalData->rxagg_usb_timeout = 0x10;\n\t\t\t}\n\t\t}\n#else /* !CONFIG_PREALLOC_RX_SKB_BUFFER */\n\t\tif ((0x5 != pHalData->rxagg_usb_size) || (0x20 != pHalData->rxagg_usb_timeout)) {\n\t\t\tpHalData->rxagg_usb_size = 0x5;\n\t\t\tpHalData->rxagg_usb_timeout = 0x20;\n\t\t\trtw_write16(padapter, REG_RXDMA_AGG_PG_TH,\n\t\t\t\tpHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));\n\t\t}\n#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */\n\n\t} else {\n\t\t/* RTW_INFO(\"%s: Unknow wireless mode(0x%x)\\n\",__func__,padapter->mlmeextpriv.cur_wireless_mode); */\n\t}\n}\n\nvoid rtw_set_usb_agg_by_mode_customer(_adapter *padapter, u8 cur_wireless_mode, u8 UsbDmaSize, u8 Legacy_UsbDmaSize)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n\tif (cur_wireless_mode < WIRELESS_11_24N\n\t    && cur_wireless_mode > 0) { /* ABG mode */\n\t\tif (Legacy_UsbDmaSize != pHalData->rxagg_usb_size\n\t\t    || 0x10 != pHalData->rxagg_usb_timeout) {\n\t\t\tpHalData->rxagg_usb_size = Legacy_UsbDmaSize;\n\t\t\tpHalData->rxagg_usb_timeout = 0x10;\n\t\t\trtw_write16(padapter, REG_RXDMA_AGG_PG_TH,\n\t\t\t\tpHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));\n\t\t}\n\t} else if (cur_wireless_mode >= WIRELESS_11_24N\n\t\t   && cur_wireless_mode <= WIRELESS_MODE_MAX) { /* N AC mode */\n\t\tif (UsbDmaSize != pHalData->rxagg_usb_size\n\t\t    || 0x20 != pHalData->rxagg_usb_timeout) {\n\t\t\tpHalData->rxagg_usb_size = UsbDmaSize;\n\t\t\tpHalData->rxagg_usb_timeout = 0x20;\n\t\t\trtw_write16(padapter, REG_RXDMA_AGG_PG_TH,\n\t\t\t\tpHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));\n\t\t}\n\t} else {\n\t\t/* RTW_INFO(\"%s: Unknown wireless mode(0x%x)\\n\",__func__,padapter->mlmeextpriv.cur_wireless_mode); */\n\t}\n}\n\nvoid rtw_set_usb_agg_by_mode(_adapter *padapter, u8 cur_wireless_mode)\n{\n#ifdef CONFIG_PLATFORM_NOVATEK_NT72668\n\trtw_set_usb_agg_by_mode_customer(padapter, cur_wireless_mode, 0x3, 0x3);\n\treturn;\n#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */\n\n\trtw_set_usb_agg_by_mode_normal(padapter, cur_wireless_mode);\n}\n#endif /* CONFIG_USB_RX_AGGREGATION */\n\n/* To avoid RX affect TX throughput */\nvoid dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer)\n{\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct mlme_priv\t\t*pmlmepriv = &(padapter->mlmepriv);\n\tstruct registry_priv *registry_par = &padapter->registrypriv;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tu8 cur_wireless_mode = WIRELESS_INVALID;\n\n#ifdef CONFIG_USB_RX_AGGREGATION\n\tif (!registry_par->dynamic_agg_enable)\n\t\treturn;\n\n#ifdef RTW_HALMAC\n\tif (IS_HARDWARE_TYPE_8822BU(padapter) || IS_HARDWARE_TYPE_8821CU(padapter) || IS_HARDWARE_TYPE_8822CU(padapter))\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, NULL);\n#else /* !RTW_HALMAC */\n\tif (IS_HARDWARE_TYPE_8821U(padapter)) { /* || IS_HARDWARE_TYPE_8192EU(padapter)) */\n\t\t/* This AGG_PH_TH only for UsbRxAggMode == USB_RX_AGG_USB */\n\t\tif ((pHalData->rxagg_mode == RX_AGG_USB) && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {\n\t\t\tif (pdvobjpriv->traffic_stat.cur_tx_tp > 2 && pdvobjpriv->traffic_stat.cur_rx_tp < 30)\n\t\t\t\trtw_write16(padapter , REG_RXDMA_AGG_PG_TH , 0x1010);\n\t\t\telse if (pdvobjpriv->traffic_stat.last_tx_bytes > 220000 && pdvobjpriv->traffic_stat.cur_rx_tp < 30)\n\t\t\t\trtw_write16(padapter , REG_RXDMA_AGG_PG_TH , 0x1006);\n\t\t\telse\n\t\t\t\trtw_write16(padapter, REG_RXDMA_AGG_PG_TH, 0x2005); /* dmc agg th 20K */\n\n\t\t\t/* RTW_INFO(\"TX_TP=%u, RX_TP=%u\\n\", pdvobjpriv->traffic_stat.cur_tx_tp, pdvobjpriv->traffic_stat.cur_rx_tp); */\n\t\t}\n\t} else if (IS_HARDWARE_TYPE_8812(padapter)) {\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tu8 i;\n\t\t_adapter *iface;\n\t\tu8 bassocaed = _FALSE;\n\t\tstruct mlme_ext_priv *mlmeext;\n\n\t\tfor (i = 0; i < pdvobjpriv->iface_nums; i++) {\n\t\t\tiface = pdvobjpriv->padapters[i];\n\t\t\tmlmeext = &iface->mlmeextpriv;\n\t\t\tif (rtw_linked_check(iface) == _TRUE) {\n\t\t\t\tif (mlmeext->cur_wireless_mode >= cur_wireless_mode)\n\t\t\t\t\tcur_wireless_mode = mlmeext->cur_wireless_mode;\n\t\t\t\tbassocaed = _TRUE;\n\t\t\t}\n\t\t}\n\t\tif (bassocaed)\n#endif\n\t\t\trtw_set_usb_agg_by_mode(padapter, cur_wireless_mode);\n#ifdef CONFIG_PLATFORM_NOVATEK_NT72668\n\t} else {\n\t\trtw_set_usb_agg_by_mode(padapter, cur_wireless_mode);\n#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */\n\t}\n#endif /* RTW_HALMAC */\n#endif /* CONFIG_USB_RX_AGGREGATION */\n\n}\n\n/* bus-agg check for SoftAP mode */\ninline u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qsel)\n{\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tu8 chk_rst = _SUCCESS;\n\n\tif (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))\n\t\treturn chk_rst;\n\n\t/* if((pre_qsel == 0xFF)||(next_qsel== 0xFF)) */\n\t/*\treturn chk_rst; */\n\n\tif (((pre_qsel == QSLT_HIGH) || ((next_qsel == QSLT_HIGH)))\n\t    && (pre_qsel != next_qsel)) {\n\t\t/* RTW_INFO(\"### bus-agg break cause of qsel misatch, pre_qsel=0x%02x,next_qsel=0x%02x ###\\n\", */\n\t\t/*\tpre_qsel,next_qsel); */\n\t\tchk_rst = _FAIL;\n\t}\n\treturn chk_rst;\n}\n\n/*\n * Description:\n * dump_TX_FIFO: This is only used to dump TX_FIFO for debug WoW mode offload\n * contant.\n *\n * Input:\n * adapter: adapter pointer.\n * page_num: The max. page number that user want to dump.\n * page_size: page size of each page. eg. 128 bytes, 256 bytes, 512byte.\n */\nvoid dump_TX_FIFO(_adapter *padapter, u8 page_num, u16 page_size)\n{\n\n\tint i;\n\tu8 val = 0;\n\tu8 base = 0;\n\tu32 addr = 0;\n\tu32 count = (page_size / 8);\n\n\tif (page_num <= 0) {\n\t\tRTW_INFO(\"!!%s: incorrect input page_num paramter!\\n\", __func__);\n\t\treturn;\n\t}\n\n\tif (page_size < 128 || page_size > 512) {\n\t\tRTW_INFO(\"!!%s: incorrect input page_size paramter!\\n\", __func__);\n\t\treturn;\n\t}\n\n\tRTW_INFO(\"+%s+\\n\", __func__);\n\tval = rtw_read8(padapter, 0x106);\n\trtw_write8(padapter, 0x106, 0x69);\n\tRTW_INFO(\"0x106: 0x%02x\\n\", val);\n\tbase = rtw_read8(padapter, 0x209);\n\tRTW_INFO(\"0x209: 0x%02x\\n\", base);\n\n\taddr = ((base)*page_size) / 8;\n\tfor (i = 0 ; i < page_num * count ; i += 2) {\n\t\trtw_write32(padapter, 0x140, addr + i);\n\t\tprintk(\" %08x %08x \", rtw_read32(padapter, 0x144), rtw_read32(padapter, 0x148));\n\t\trtw_write32(padapter, 0x140, addr + i + 1);\n\t\tprintk(\" %08x %08x\\n\", rtw_read32(padapter, 0x144), rtw_read32(padapter, 0x148));\n\t}\n}\n\n#ifdef CONFIG_GPIO_API\nu8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num)\n{\n\tu8 value = 0;\n\tu8 direction = 0;\n\tu32 gpio_pin_input_val = REG_GPIO_PIN_CTRL;\n\tu32 gpio_pin_output_val = REG_GPIO_PIN_CTRL + 1;\n\tu32 gpio_pin_output_en = REG_GPIO_PIN_CTRL + 2;\n\tu8 gpio_num_to_set = gpio_num;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\n\tif (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL)\n\t\treturn value;\n\n\trtw_ps_deny(adapter, PS_DENY_IOCTL);\n\n\tRTW_INFO(\"rf_pwrstate=0x%02x\\n\", pwrpriv->rf_pwrstate);\n\tLeaveAllPowerSaveModeDirect(adapter);\n\n\tif (gpio_num > 7) {\n\t\tgpio_pin_input_val = REG_GPIO_PIN_CTRL_2;\n\t\tgpio_pin_output_val = REG_GPIO_PIN_CTRL_2 + 1;\n\t\tgpio_pin_output_en = REG_GPIO_PIN_CTRL_2 + 2;\n\t\tgpio_num_to_set = gpio_num - 8;\n\t}\n\n\t/* Read GPIO Direction */\n\tdirection = (rtw_read8(adapter, gpio_pin_output_en) & BIT(gpio_num_to_set)) >> gpio_num_to_set;\n\n\t/* According the direction to read register value */\n\tif (direction)\n\t\tvalue =  (rtw_read8(adapter, gpio_pin_output_val) & BIT(gpio_num_to_set)) >> gpio_num_to_set;\n\telse\n\t\tvalue =  (rtw_read8(adapter, gpio_pin_input_val) & BIT(gpio_num_to_set)) >> gpio_num_to_set;\n\n\trtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);\n\tRTW_INFO(\"%s direction=%d value=%d\\n\", __FUNCTION__, direction, value);\n\n\treturn value;\n}\n\nint  rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh)\n{\n\tu8 direction = 0;\n\tu8 res = -1;\n\tu32 gpio_pin_output_val = REG_GPIO_PIN_CTRL + 1;\n\tu32 gpio_pin_output_en = REG_GPIO_PIN_CTRL + 2;\n\tu8 gpio_num_to_set = gpio_num;\n\n\tif (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL)\n\t\treturn -1;\n\n\trtw_ps_deny(adapter, PS_DENY_IOCTL);\n\n\tLeaveAllPowerSaveModeDirect(adapter);\n\n\tif (gpio_num > 7) {\n\t\tgpio_pin_output_val = REG_GPIO_PIN_CTRL_2 + 1;\n\t\tgpio_pin_output_en = REG_GPIO_PIN_CTRL_2 + 2;\n\t\tgpio_num_to_set = gpio_num - 8;\n\t}\n\n\t/* Read GPIO direction */\n\tdirection = (rtw_read8(adapter, gpio_pin_output_en) & BIT(gpio_num_to_set)) >> gpio_num_to_set;\n\n\t/* If GPIO is output direction, setting value. */\n\tif (direction) {\n\t\tif (isHigh)\n\t\t\trtw_write8(adapter, gpio_pin_output_val, rtw_read8(adapter, gpio_pin_output_val) | BIT(gpio_num_to_set));\n\t\telse\n\t\t\trtw_write8(adapter, gpio_pin_output_val, rtw_read8(adapter, gpio_pin_output_val) & ~BIT(gpio_num_to_set));\n\n\t\tRTW_INFO(\"%s Set gpio %x[%d]=%d\\n\", __FUNCTION__, REG_GPIO_PIN_CTRL + 1, gpio_num, isHigh);\n\t\tres = 0;\n\t} else {\n\t\tRTW_INFO(\"%s The gpio is input,not be set!\\n\", __FUNCTION__);\n\t\tres = -1;\n\t}\n\n\trtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);\n\treturn res;\n}\n\nint rtw_hal_config_gpio(_adapter *adapter, u8 gpio_num, bool isOutput)\n{\n\tu32 gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL + 2;\n\tu8 gpio_num_to_set = gpio_num;\n\n\tif (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL)\n\t\treturn -1;\n\n\tRTW_INFO(\"%s gpio_num =%d direction=%d\\n\", __FUNCTION__, gpio_num, isOutput);\n\n\trtw_ps_deny(adapter, PS_DENY_IOCTL);\n\n\tLeaveAllPowerSaveModeDirect(adapter);\n\n\trtw_hal_gpio_multi_func_reset(adapter, gpio_num);\n\n\tif (gpio_num > 7) {\n\t\tgpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL_2 + 2;\n\t\tgpio_num_to_set = gpio_num - 8;\n\t}\n\n\tif (isOutput)\n\t\trtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) | BIT(gpio_num_to_set));\n\telse\n\t\trtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) & ~BIT(gpio_num_to_set));\n\n\trtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);\n\n\treturn 0;\n}\nint rtw_hal_register_gpio_interrupt(_adapter *adapter, int gpio_num, void(*callback)(u8 level))\n{\n\tu8 value;\n\tu8 direction;\n\tPHAL_DATA_TYPE phal = GET_HAL_DATA(adapter);\n\n\tif (IS_HARDWARE_TYPE_8188E(adapter)) {\n\t\tif (gpio_num > 7 || gpio_num < 4) {\n\t\t\tRTW_PRINT(\"%s The gpio number does not included 4~7.\\n\", __FUNCTION__);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\trtw_ps_deny(adapter, PS_DENY_IOCTL);\n\n\tLeaveAllPowerSaveModeDirect(adapter);\n\n\t/* Read GPIO direction */\n\tdirection = (rtw_read8(adapter, REG_GPIO_PIN_CTRL + 2) & BIT(gpio_num)) >> gpio_num;\n\tif (direction) {\n\t\tRTW_PRINT(\"%s Can't register output gpio as interrupt.\\n\", __FUNCTION__);\n\t\treturn -1;\n\t}\n\n\t/* Config GPIO Mode */\n\trtw_write8(adapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 3) | BIT(gpio_num));\n\n\t/* Register GPIO interrupt handler*/\n\tadapter->gpiointpriv.callback[gpio_num] = callback;\n\n\t/* Set GPIO interrupt mode, 0:positive edge, 1:negative edge */\n\tvalue = rtw_read8(adapter, REG_GPIO_PIN_CTRL) & BIT(gpio_num);\n\tadapter->gpiointpriv.interrupt_mode = rtw_read8(adapter, REG_HSIMR + 2) ^ value;\n\trtw_write8(adapter, REG_GPIO_INTM, adapter->gpiointpriv.interrupt_mode);\n\n\t/* Enable GPIO interrupt */\n\tadapter->gpiointpriv.interrupt_enable_mask = rtw_read8(adapter, REG_HSIMR + 2) | BIT(gpio_num);\n\trtw_write8(adapter, REG_HSIMR + 2, adapter->gpiointpriv.interrupt_enable_mask);\n\n\trtw_hal_update_hisr_hsisr_ind(adapter, 1);\n\n\trtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);\n\n\treturn 0;\n}\nint rtw_hal_disable_gpio_interrupt(_adapter *adapter, int gpio_num)\n{\n\tu8 value;\n\tu8 direction;\n\tPHAL_DATA_TYPE phal = GET_HAL_DATA(adapter);\n\n\tif (IS_HARDWARE_TYPE_8188E(adapter)) {\n\t\tif (gpio_num > 7 || gpio_num < 4) {\n\t\t\tRTW_INFO(\"%s The gpio number does not included 4~7.\\n\", __FUNCTION__);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\trtw_ps_deny(adapter, PS_DENY_IOCTL);\n\n\tLeaveAllPowerSaveModeDirect(adapter);\n\n\t/* Config GPIO Mode */\n\trtw_write8(adapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(gpio_num));\n\n\t/* Unregister GPIO interrupt handler*/\n\tadapter->gpiointpriv.callback[gpio_num] = NULL;\n\n\t/* Reset GPIO interrupt mode, 0:positive edge, 1:negative edge */\n\tadapter->gpiointpriv.interrupt_mode = rtw_read8(adapter, REG_GPIO_INTM) & ~BIT(gpio_num);\n\trtw_write8(adapter, REG_GPIO_INTM, 0x00);\n\n\t/* Disable GPIO interrupt */\n\tadapter->gpiointpriv.interrupt_enable_mask = rtw_read8(adapter, REG_HSIMR + 2) & ~BIT(gpio_num);\n\trtw_write8(adapter, REG_HSIMR + 2, adapter->gpiointpriv.interrupt_enable_mask);\n\n\tif (!adapter->gpiointpriv.interrupt_enable_mask)\n\t\trtw_hal_update_hisr_hsisr_ind(adapter, 0);\n\n\trtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);\n\n\treturn 0;\n}\n#endif\n\ns8 rtw_hal_ch_sw_iqk_info_search(_adapter *padapter, u8 central_chnl, u8 bw_mode)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\tu8 i;\n\n\tfor (i = 0; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++) {\n\t\tif ((pHalData->iqk_reg_backup[i].central_chnl != 0)) {\n\t\t\tif ((pHalData->iqk_reg_backup[i].central_chnl == central_chnl)\n\t\t\t    && (pHalData->iqk_reg_backup[i].bw_mode == bw_mode))\n\t\t\t\treturn i;\n\t\t}\n\t}\n\n\treturn -1;\n}\n\nvoid rtw_hal_ch_sw_iqk_info_backup(_adapter *padapter)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\ts8 res;\n\tu8 i;\n\n\t/* If it's an existed record, overwrite it */\n\tres = rtw_hal_ch_sw_iqk_info_search(padapter, pHalData->current_channel, pHalData->current_channel_bw);\n\tif ((res >= 0) && (res < MAX_IQK_INFO_BACKUP_CHNL_NUM)) {\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8 *)&(pHalData->iqk_reg_backup[res]));\n\t\treturn;\n\t}\n\n\t/* Search for the empty record to use */\n\tfor (i = 0; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++) {\n\t\tif (pHalData->iqk_reg_backup[i].central_chnl == 0) {\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8 *)&(pHalData->iqk_reg_backup[i]));\n\t\t\treturn;\n\t\t}\n\t}\n\n\t/* Else, overwrite the oldest record */\n\tfor (i = 1; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++)\n\t\t_rtw_memcpy(&(pHalData->iqk_reg_backup[i - 1]), &(pHalData->iqk_reg_backup[i]), sizeof(struct hal_iqk_reg_backup));\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8 *)&(pHalData->iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM - 1]));\n}\n\nvoid rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case)\n{\n\trtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_RESTORE, &ch_sw_use_case);\n}\n\nvoid rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter)\n{\n\tu32\tmac_cck_ok = 0, mac_ofdm_ok = 0, mac_ht_ok = 0, mac_vht_ok = 0;\n\tu32\tmac_cck_err = 0, mac_ofdm_err = 0, mac_ht_err = 0, mac_vht_err = 0;\n\tu32\tmac_cck_fa = 0, mac_ofdm_fa = 0, mac_ht_fa = 0;\n\tu32\tDropPacket = 0;\n\n\tif (!rx_counter) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\tif (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter))\n\t\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/\n\n\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x3);\n\tmac_cck_ok\t= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]\t  */\n\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0);\n\tmac_ofdm_ok\t= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]\t */\n\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x6);\n\tmac_ht_ok\t= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]\t */\n\tmac_vht_ok\t= 0;\n\tif (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {\n\t\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0);\n\t\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1);\n\t\tmac_vht_ok\t= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/\n\t\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/\n\t}\n\n\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x4);\n\tmac_cck_err\t= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]\t */\n\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1);\n\tmac_ofdm_err\t= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]\t */\n\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x7);\n\tmac_ht_err\t= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]\t\t */\n\tmac_vht_err\t= 0;\n\tif (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {\n\t\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1);\n\t\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1);\n\t\tmac_vht_err\t= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/\n\t\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/\n\t}\n\n\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x5);\n\tmac_cck_fa\t= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]\t */\n\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x2);\n\tmac_ofdm_fa\t= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]\t */\n\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x9);\n\tmac_ht_fa\t= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]\t\t */\n\n\t/* Mac_DropPacket */\n\trtw_write32(padapter, REG_RXERR_RPT, (rtw_read32(padapter, REG_RXERR_RPT) & 0x0FFFFFFF) | Mac_DropPacket);\n\tDropPacket = rtw_read32(padapter, REG_RXERR_RPT) & 0x0000FFFF;\n\n\trx_counter->rx_pkt_ok = mac_cck_ok + mac_ofdm_ok + mac_ht_ok + mac_vht_ok;\n\trx_counter->rx_pkt_crc_error = mac_cck_err + mac_ofdm_err + mac_ht_err + mac_vht_err;\n\trx_counter->rx_cck_fa = mac_cck_fa;\n\trx_counter->rx_ofdm_fa = mac_ofdm_fa;\n\trx_counter->rx_ht_fa = mac_ht_fa;\n\trx_counter->rx_pkt_drop = DropPacket;\n}\nvoid rtw_reset_mac_rx_counters(_adapter *padapter)\n{\n\n\t/* If no packet rx, MaxRx clock be gating ,BIT_DISGCLK bit19 set 1 for fix*/\n\tif (IS_HARDWARE_TYPE_8703B(padapter) ||\n\t\tIS_HARDWARE_TYPE_8723D(padapter) ||\n\t\tIS_HARDWARE_TYPE_8188F(padapter) ||\n\t\tIS_HARDWARE_TYPE_8188GTV(padapter) ||\n\t\tIS_HARDWARE_TYPE_8192F(padapter) ||\n\t\tIS_HARDWARE_TYPE_8822C(padapter))\n\t\tphy_set_mac_reg(padapter, REG_RCR, BIT19, 0x1);\n\n\t/* reset mac counter */\n\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x1);\n\tphy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x0);\n}\n\nvoid rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter)\n{\n\tu32 cckok = 0, cckcrc = 0, ofdmok = 0, ofdmcrc = 0, htok = 0, htcrc = 0, OFDM_FA = 0, CCK_FA = 0, vht_ok = 0, vht_err = 0;\n\tif (!rx_counter) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\tif (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {\n\t\tcckok\t= phy_query_bb_reg(padapter, 0xF04, 0x3FFF);\t     /* [13:0] */\n\t\tofdmok\t= phy_query_bb_reg(padapter, 0xF14, 0x3FFF);\t     /* [13:0] */\n\t\thtok\t\t= phy_query_bb_reg(padapter, 0xF10, 0x3FFF);     /* [13:0] */\n\t\tvht_ok\t= phy_query_bb_reg(padapter, 0xF0C, 0x3FFF);     /* [13:0] */\n\t\tcckcrc\t= phy_query_bb_reg(padapter, 0xF04, 0x3FFF0000); /* [29:16]\t */\n\t\tofdmcrc\t= phy_query_bb_reg(padapter, 0xF14, 0x3FFF0000); /* [29:16] */\n\t\thtcrc\t= phy_query_bb_reg(padapter, 0xF10, 0x3FFF0000); /* [29:16] */\n\t\tvht_err\t= phy_query_bb_reg(padapter, 0xF0C, 0x3FFF0000); /* [29:16] */\n\t\tCCK_FA\t= phy_query_bb_reg(padapter, 0xA5C, bMaskLWord);\n\t\tOFDM_FA\t= phy_query_bb_reg(padapter, 0xF48, bMaskLWord);\n\t} else if(IS_HARDWARE_TYPE_JAGUAR3(padapter)){\n\t\tcckok = phy_query_bb_reg(padapter, 0x2c04, 0xffff);\n\t\tofdmok = phy_query_bb_reg(padapter, 0x2c14, 0xffff);\n\t\thtok = phy_query_bb_reg(padapter, 0x2c10, 0xffff);\n\t\tvht_ok = phy_query_bb_reg(padapter, 0x2c0c, 0xffff);\n\t\tcckcrc = phy_query_bb_reg(padapter, 0x2c04, 0xffff0000);\n\t\tofdmcrc = phy_query_bb_reg(padapter, 0x2c14, 0xffff0000);\n\t\thtcrc = phy_query_bb_reg(padapter, 0x2c10, 0xffff0000);\n\t\tvht_err = phy_query_bb_reg(padapter, 0x2c0c, 0xffff0000);\n\t\tCCK_FA\t= phy_query_bb_reg(padapter, 0x1a5c, bMaskLWord);\n\t\tOFDM_FA = phy_query_bb_reg(padapter, 0x2d00, bMaskLWord) - phy_query_bb_reg(padapter, 0x2de0, bMaskLWord);\n\n\t} else {\n\t\tcckok\t= phy_query_bb_reg(padapter, 0xF88, bMaskDWord);\n\t\tofdmok\t= phy_query_bb_reg(padapter, 0xF94, bMaskLWord);\n\t\thtok\t\t= phy_query_bb_reg(padapter, 0xF90, bMaskLWord);\n\t\tvht_ok\t= 0;\n\t\tcckcrc\t= phy_query_bb_reg(padapter, 0xF84, bMaskDWord);\n\t\tofdmcrc\t= phy_query_bb_reg(padapter, 0xF94, bMaskHWord);\n\t\thtcrc\t= phy_query_bb_reg(padapter, 0xF90, bMaskHWord);\n\t\tvht_err\t= 0;\n\t\tOFDM_FA = phy_query_bb_reg(padapter, 0xCF0, bMaskLWord) + phy_query_bb_reg(padapter, 0xCF2, bMaskLWord) +\n\t\t\tphy_query_bb_reg(padapter, 0xDA2, bMaskLWord) + phy_query_bb_reg(padapter, 0xDA4, bMaskLWord) +\n\t\t\tphy_query_bb_reg(padapter, 0xDA6, bMaskLWord) + phy_query_bb_reg(padapter, 0xDA8, bMaskLWord);\n\n\t\tCCK_FA = (rtw_read8(padapter, 0xA5B) << 8) | (rtw_read8(padapter, 0xA5C));\n\t}\n\n\trx_counter->rx_pkt_ok = cckok + ofdmok + htok + vht_ok;\n\trx_counter->rx_pkt_crc_error = cckcrc + ofdmcrc + htcrc + vht_err;\n\trx_counter->rx_ofdm_fa = OFDM_FA;\n\trx_counter->rx_cck_fa = CCK_FA;\n\n}\n\nvoid rtw_reset_phy_trx_ok_counters(_adapter *padapter)\n{\n\tif (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {\n\t\tphy_set_bb_reg(padapter, 0xB58, BIT0, 0x1);\n\t\tphy_set_bb_reg(padapter, 0xB58, BIT0, 0x0);\n\t} else if(IS_HARDWARE_TYPE_JAGUAR3(padapter)) {\n\t\tphy_set_bb_reg(padapter, 0x1EB4, BIT25, 0x1);\n\t\tphy_set_bb_reg(padapter, 0x1EB4, BIT25, 0x0);\n\t} else {\n\t\tphy_set_bb_reg(padapter, 0xF14, BIT16, 0x1);\n\t\tphy_set_bb_reg(padapter, 0xF14, BIT16, 0x0);\n\t}\n}\n\nvoid rtw_reset_phy_rx_counters(_adapter *padapter)\n{\n\t/* reset phy counter */\n\tif (IS_HARDWARE_TYPE_JAGUAR3(padapter)) {\n\t\t/* reset CCK FA counter */\n\t\tphy_set_bb_reg(padapter, 0x1a2c, BIT(15) | BIT(14), 0);\n\t\tphy_set_bb_reg(padapter, 0x1a2c, BIT(15) | BIT(14), 2);\n\n\t\t/* reset CCK CCA counter */\n\t\tphy_set_bb_reg(padapter, 0x1a2c, BIT(13) | BIT(12), 0);\n\t\tphy_set_bb_reg(padapter, 0x1a2c, BIT(13) | BIT(12), 2);\n\t\trtw_reset_phy_trx_ok_counters(padapter);\n\n\t} else if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {\n\t\trtw_reset_phy_trx_ok_counters(padapter);\n\n\t\tphy_set_bb_reg(padapter, 0x9A4, BIT17, 0x1);/* reset  OFDA FA counter */\n\t\tphy_set_bb_reg(padapter, 0x9A4, BIT17, 0x0);\n\n\t\tphy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset  CCK FA counter */\n\t\tphy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1);\n\t} else {\n\t\tphy_set_bb_reg(padapter, 0xF14, BIT16, 0x1);\n\t\trtw_msleep_os(10);\n\t\tphy_set_bb_reg(padapter, 0xF14, BIT16, 0x0);\n\n\t\tphy_set_bb_reg(padapter, 0xD00, BIT27, 0x1);/* reset  OFDA FA counter */\n\t\tphy_set_bb_reg(padapter, 0xC0C, BIT31, 0x1);/* reset  OFDA FA counter */\n\t\tphy_set_bb_reg(padapter, 0xD00, BIT27, 0x0);\n\t\tphy_set_bb_reg(padapter, 0xC0C, BIT31, 0x0);\n\n\t\tphy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset  CCK FA counter */\n\t\tphy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1);\n\t}\n}\n#ifdef DBG_RX_COUNTER_DUMP\nvoid rtw_dump_drv_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter)\n{\n\tstruct recv_priv *precvpriv = &padapter->recvpriv;\n\tif (!rx_counter) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\trx_counter->rx_pkt_ok = padapter->drv_rx_cnt_ok;\n\trx_counter->rx_pkt_crc_error = padapter->drv_rx_cnt_crcerror;\n\trx_counter->rx_pkt_drop = precvpriv->rx_drop - padapter->drv_rx_cnt_drop;\n}\nvoid rtw_reset_drv_rx_counters(_adapter *padapter)\n{\n\tstruct recv_priv *precvpriv = &padapter->recvpriv;\n\tpadapter->drv_rx_cnt_ok = 0;\n\tpadapter->drv_rx_cnt_crcerror = 0;\n\tpadapter->drv_rx_cnt_drop = precvpriv->rx_drop;\n}\nvoid rtw_dump_phy_rxcnts_preprocess(_adapter *padapter, u8 rx_cnt_mode)\n{\n\tu8 initialgain;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);\n\n\tif ((!(padapter->dump_rx_cnt_mode & DUMP_PHY_RX_COUNTER)) && (rx_cnt_mode & DUMP_PHY_RX_COUNTER)) {\n\t\trtw_hal_get_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, NULL);\n\t\tRTW_INFO(\"%s CurIGValue:0x%02x\\n\", __FUNCTION__, initialgain);\n\t\trtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);\n\t\t/*disable dynamic functions, such as high power, DIG*/\n\t\trtw_phydm_ability_backup(padapter);\n\t\trtw_phydm_func_clr(padapter, (ODM_BB_DIG | ODM_BB_FA_CNT));\n\t} else if ((padapter->dump_rx_cnt_mode & DUMP_PHY_RX_COUNTER) && (!(rx_cnt_mode & DUMP_PHY_RX_COUNTER))) {\n\t\t/* turn on phy-dynamic functions */\n\t\trtw_phydm_ability_restore(padapter);\n\t\tinitialgain = 0xff; /* restore RX GAIN */\n\t\trtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);\n\n\t}\n}\n\nvoid rtw_dump_rx_counters(_adapter *padapter)\n{\n\tstruct dbg_rx_counter rx_counter;\n\n\tif (padapter->dump_rx_cnt_mode & DUMP_DRV_RX_COUNTER) {\n\t\t_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));\n\t\trtw_dump_drv_rx_counters(padapter, &rx_counter);\n\t\tRTW_INFO(\"Drv Received packet OK:%d CRC error:%d Drop Packets: %d\\n\",\n\t\t\trx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_pkt_drop);\n\t\trtw_reset_drv_rx_counters(padapter);\n\t}\n\n\tif (padapter->dump_rx_cnt_mode & DUMP_MAC_RX_COUNTER) {\n\t\t_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));\n\t\trtw_dump_mac_rx_counters(padapter, &rx_counter);\n\t\tRTW_INFO(\"Mac Received packet OK:%d CRC error:%d FA Counter: %d Drop Packets: %d\\n\",\n\t\t\t rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error,\n\t\t\trx_counter.rx_cck_fa + rx_counter.rx_ofdm_fa + rx_counter.rx_ht_fa,\n\t\t\t rx_counter.rx_pkt_drop);\n\t\trtw_reset_mac_rx_counters(padapter);\n\t}\n\n\tif (padapter->dump_rx_cnt_mode & DUMP_PHY_RX_COUNTER) {\n\t\t_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));\n\t\trtw_dump_phy_rx_counters(padapter, &rx_counter);\n\t\t/* RTW_INFO(\"%s: OFDM_FA =%d\\n\", __FUNCTION__, rx_counter.rx_ofdm_fa); */\n\t\t/* RTW_INFO(\"%s: CCK_FA =%d\\n\", __FUNCTION__, rx_counter.rx_cck_fa); */\n\t\tRTW_INFO(\"Phy Received packet OK:%d CRC error:%d FA Counter: %d\\n\", rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error,\n\t\t\t rx_counter.rx_ofdm_fa + rx_counter.rx_cck_fa);\n\t\trtw_reset_phy_rx_counters(padapter);\n\t}\n}\n#endif\nu8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);\n\tu8 curr_tx_sgi = 0;\n\tstruct ra_sta_info *ra_info;\n\n\tif (!psta)\n\t\treturn curr_tx_sgi;\n\n\tif (padapter->fix_rate == 0xff) {\n#if defined(CONFIG_RTL8188E)\n#if (RATE_ADAPTIVE_SUPPORT == 1)\n\t\tcurr_tx_sgi = hal_data->odmpriv.ra_info[psta->cmn.mac_id].rate_sgi;\n#endif /* (RATE_ADAPTIVE_SUPPORT == 1)*/\n#else\n\t\tra_info = &psta->cmn.ra_info;\n\t\tcurr_tx_sgi = ((ra_info->curr_tx_rate) & 0x80) >> 7;\n#endif\n\t} else {\n\t\tcurr_tx_sgi = ((padapter->fix_rate) & 0x80) >> 7;\n\t}\n\n\treturn curr_tx_sgi;\n}\n\nu8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);\n\tu8 rate_id = 0;\n\tstruct ra_sta_info *ra_info;\n\n\tif (!psta)\n\t\treturn rate_id;\n\n\tif (padapter->fix_rate == 0xff) {\n#if defined(CONFIG_RTL8188E)\n#if (RATE_ADAPTIVE_SUPPORT == 1)\n\t\trate_id = hal_data->odmpriv.ra_info[psta->cmn.mac_id].decision_rate;\n#endif /* (RATE_ADAPTIVE_SUPPORT == 1)*/\n#else\n\t\tra_info = &psta->cmn.ra_info;\n\t\trate_id = ra_info->curr_tx_rate & 0x7f;\n#endif\n\t} else {\n\t\trate_id = padapter->fix_rate & 0x7f;\n\t}\n\n\treturn rate_id;\n}\n\nvoid update_IOT_info(_adapter *padapter)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tswitch (pmlmeinfo->assoc_AP_vendor) {\n\tcase HT_IOT_PEER_MARVELL:\n\t\tpmlmeinfo->turboMode_cts2self = 1;\n\t\tpmlmeinfo->turboMode_rtsen = 0;\n\t\tbreak;\n\n\tcase HT_IOT_PEER_RALINK:\n\t\tpmlmeinfo->turboMode_cts2self = 0;\n\t\tpmlmeinfo->turboMode_rtsen = 1;\n\t\tbreak;\n\tcase HT_IOT_PEER_REALTEK:\n\t\t/* rtw_write16(padapter, 0x4cc, 0xffff); */\n\t\t/* rtw_write16(padapter, 0x546, 0x01c0); */\n\t\tbreak;\n\tdefault:\n\t\tpmlmeinfo->turboMode_cts2self = 0;\n\t\tpmlmeinfo->turboMode_rtsen = 1;\n\t\tbreak;\n\t}\n\n}\n#ifdef CONFIG_RTS_FULL_BW \n/*\n8188E: not support full RTS BW feature(mac REG no define 480[5])\n*/\nvoid rtw_set_rts_bw(_adapter *padapter) {\n\tint i;\n\tu8 enable = 1;\n\tbool connect_to_8812 = _FALSE;\n\tu8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\tstruct sta_info *station = NULL;\n\n\tfor (i = 0; i < macid_ctl->num; i++) {\n\t\tif (rtw_macid_is_used(macid_ctl, i)) {\n\n\t\t\tstation = NULL;\n\t\t\tstation = macid_ctl->sta[i];\n\t\t\tif(station) {\n\t\t\t\t\n\t\t\t\t _adapter *sta_adapter =station->padapter;\n\t\t\t\tstruct mlme_ext_priv\t*pmlmeext = &(sta_adapter->mlmeextpriv);\n\t\t\t\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\t\t\t\t\n\t\t\t\tif ( pmlmeinfo->state != WIFI_FW_NULL_STATE) {\n\t\t\t\t\tif(_rtw_memcmp(macid_ctl->sta[i]->cmn.mac_addr, bc_addr, ETH_ALEN) !=  _TRUE) {\n\t\t\t\t\t\tif (  macid_ctl->sta[i]->vendor_8812) {\n\t\t\t\t\t\t\tconnect_to_8812 = _TRUE;\n\t\t\t\t\t\t\tenable = 0;\n\t\t\t\t\t\t}\t\n\t\t\t\t\t}\t\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif(connect_to_8812)\n\t\t\tbreak;\n\t}\n\t\n\t\tRTW_INFO(\"%s connect_to_8812=%d,enable=%u\\n\", __FUNCTION__,connect_to_8812,enable);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_SET_RTS_BW, &enable);\n}\n#endif/*CONFIG_RTS_FULL_BW*/\n\nint hal_spec_init(_adapter *adapter)\n{\n\tu8 interface_type = 0;\n\tint ret = _SUCCESS;\n\n\tinterface_type = rtw_get_intf_type(adapter);\n\n\tswitch (rtw_get_chip_type(adapter)) {\n#ifdef CONFIG_RTL8723B\n\tcase RTL8723B:\n\t\tinit_hal_spec_8723b(adapter);\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8703B\n\tcase RTL8703B:\n\t\tinit_hal_spec_8703b(adapter);\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8723D\n\tcase RTL8723D:\n\t\tinit_hal_spec_8723d(adapter);\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8188E\n\tcase RTL8188E:\n\t\tinit_hal_spec_8188e(adapter);\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8188F\n\tcase RTL8188F:\n\t\tinit_hal_spec_8188f(adapter);\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8188GTV\n\tcase RTL8188GTV:\n\t\tinit_hal_spec_8188gtv(adapter);\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8812A\n\tcase RTL8812:\n\t\tinit_hal_spec_8812a(adapter);\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8821A\n\tcase RTL8821:\n\t\tinit_hal_spec_8821a(adapter);\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8192E\n\tcase RTL8192E:\n\t\tinit_hal_spec_8192e(adapter);\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8814A\n\tcase RTL8814A:\n\t\tinit_hal_spec_8814a(adapter);\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8822B\n\tcase RTL8822B:\n\t\trtl8822b_init_hal_spec(adapter);\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8821C\n\tcase RTL8821C:\n\t\tinit_hal_spec_rtl8821c(adapter);\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8710B\n\tcase RTL8710B:\n\t\tinit_hal_spec_8710b(adapter);\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8192F\n\tcase RTL8192F:\n\t\tinit_hal_spec_8192f(adapter);\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8822C\n\tcase RTL8822C:\n\t\trtl8822c_init_hal_spec(adapter);\n\t\tbreak;\n#endif\n\tdefault:\n\t\tRTW_ERR(\"%s: unknown chip_type:%u\\n\"\n\t\t\t, __func__, rtw_get_chip_type(adapter));\n\t\tret = _FAIL;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstatic const char *const _band_cap_str[] = {\n\t/* BIT0 */\"2G\",\n\t/* BIT1 */\"5G\",\n};\n\nstatic const char *const _bw_cap_str[] = {\n\t/* BIT0 */\"5M\",\n\t/* BIT1 */\"10M\",\n\t/* BIT2 */\"20M\",\n\t/* BIT3 */\"40M\",\n\t/* BIT4 */\"80M\",\n\t/* BIT5 */\"160M\",\n\t/* BIT6 */\"80_80M\",\n};\n\nstatic const char *const _proto_cap_str[] = {\n\t/* BIT0 */\"b\",\n\t/* BIT1 */\"g\",\n\t/* BIT2 */\"n\",\n\t/* BIT3 */\"ac\",\n};\n\nstatic const char *const _wl_func_str[] = {\n\t/* BIT0 */\"P2P\",\n\t/* BIT1 */\"MIRACAST\",\n\t/* BIT2 */\"TDLS\",\n\t/* BIT3 */\"FTM\",\n};\n\nvoid dump_hal_spec(void *sel, _adapter *adapter)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tint i;\n\n\tRTW_PRINT_SEL(sel, \"macid_num:%u\\n\", hal_spec->macid_num);\n\tRTW_PRINT_SEL(sel, \"sec_cap:0x%02x\\n\", hal_spec->sec_cap);\n\tRTW_PRINT_SEL(sel, \"sec_cam_ent_num:%u\\n\", hal_spec->sec_cam_ent_num);\n\tRTW_PRINT_SEL(sel, \"rfpath_num_2g:%u\\n\", hal_spec->rfpath_num_2g);\n\tRTW_PRINT_SEL(sel, \"rfpath_num_5g:%u\\n\", hal_spec->rfpath_num_5g);\n\tRTW_PRINT_SEL(sel, \"txgi_max:%u\\n\", hal_spec->txgi_max);\n\tRTW_PRINT_SEL(sel, \"txgi_pdbm:%u\\n\", hal_spec->txgi_pdbm);\n\tRTW_PRINT_SEL(sel, \"max_tx_cnt:%u\\n\", hal_spec->max_tx_cnt);\n\tRTW_PRINT_SEL(sel, \"tx_nss_num:%u\\n\", hal_spec->tx_nss_num);\n\tRTW_PRINT_SEL(sel, \"rx_nss_num:%u\\n\", hal_spec->rx_nss_num);\n\n\tRTW_PRINT_SEL(sel, \"band_cap:\");\n\tfor (i = 0; i < BAND_CAP_BIT_NUM; i++) {\n\t\tif (((hal_spec->band_cap) >> i) & BIT0 && _band_cap_str[i])\n\t\t\t_RTW_PRINT_SEL(sel, \"%s \", _band_cap_str[i]);\n\t}\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"bw_cap:\");\n\tfor (i = 0; i < BW_CAP_BIT_NUM; i++) {\n\t\tif (((hal_spec->bw_cap) >> i) & BIT0 && _bw_cap_str[i])\n\t\t\t_RTW_PRINT_SEL(sel, \"%s \", _bw_cap_str[i]);\n\t}\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"proto_cap:\");\n\tfor (i = 0; i < PROTO_CAP_BIT_NUM; i++) {\n\t\tif (((hal_spec->proto_cap) >> i) & BIT0 && _proto_cap_str[i])\n\t\t\t_RTW_PRINT_SEL(sel, \"%s \", _proto_cap_str[i]);\n\t}\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"wl_func:\");\n\tfor (i = 0; i < WL_FUNC_BIT_NUM; i++) {\n\t\tif (((hal_spec->wl_func) >> i) & BIT0 && _wl_func_str[i])\n\t\t\t_RTW_PRINT_SEL(sel, \"%s \", _wl_func_str[i]);\n\t}\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\n#if CONFIG_TX_AC_LIFETIME\n\tRTW_PRINT_SEL(sel, \"tx_aclt_unit_factor:%u (unit:%uus)\\n\"\n\t\t, hal_spec->tx_aclt_unit_factor, hal_spec->tx_aclt_unit_factor * 32);\n#endif\n\n\tRTW_PRINT_SEL(sel, \"rx_tsf_filter:%u\\n\", hal_spec->rx_tsf_filter);\n\n\tRTW_PRINT_SEL(sel, \"pg_txpwr_saddr:0x%X\\n\", hal_spec->pg_txpwr_saddr);\n\tRTW_PRINT_SEL(sel, \"pg_txgi_diff_factor:%u\\n\", hal_spec->pg_txgi_diff_factor);\n}\n\ninline bool hal_chk_band_cap(_adapter *adapter, u8 cap)\n{\n\treturn GET_HAL_SPEC(adapter)->band_cap & cap;\n}\n\ninline bool hal_chk_bw_cap(_adapter *adapter, u8 cap)\n{\n\treturn GET_HAL_SPEC(adapter)->bw_cap & cap;\n}\n\ninline bool hal_chk_proto_cap(_adapter *adapter, u8 cap)\n{\n\treturn GET_HAL_SPEC(adapter)->proto_cap & cap;\n}\n\ninline bool hal_chk_wl_func(_adapter *adapter, u8 func)\n{\n\treturn GET_HAL_SPEC(adapter)->wl_func & func;\n}\n\ninline bool hal_is_band_support(_adapter *adapter, u8 band)\n{\n\treturn GET_HAL_SPEC(adapter)->band_cap & band_to_band_cap(band);\n}\n\ninline bool hal_is_bw_support(_adapter *adapter, u8 bw)\n{\n\treturn GET_HAL_SPEC(adapter)->bw_cap & ch_width_to_bw_cap(bw);\n}\n\ninline bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode)\n{\n\tu8 proto_cap = GET_HAL_SPEC(adapter)->proto_cap;\n\n\tif (mode == WIRELESS_11B)\n\t\tif ((proto_cap & PROTO_CAP_11B) && hal_chk_band_cap(adapter, BAND_CAP_2G))\n\t\t\treturn 1;\n\n\tif (mode == WIRELESS_11G)\n\t\tif ((proto_cap & PROTO_CAP_11G) && hal_chk_band_cap(adapter, BAND_CAP_2G))\n\t\t\treturn 1;\n\n\tif (mode == WIRELESS_11A)\n\t\tif ((proto_cap & PROTO_CAP_11G) && hal_chk_band_cap(adapter, BAND_CAP_5G))\n\t\t\treturn 1;\n\n\tif (mode == WIRELESS_11_24N)\n\t\tif ((proto_cap & PROTO_CAP_11N) && hal_chk_band_cap(adapter, BAND_CAP_2G))\n\t\t\treturn 1;\n\n\tif (mode == WIRELESS_11_5N)\n\t\tif ((proto_cap & PROTO_CAP_11N) && hal_chk_band_cap(adapter, BAND_CAP_5G))\n\t\t\treturn 1;\n\n\tif (mode == WIRELESS_11AC)\n\t\tif ((proto_cap & PROTO_CAP_11AC) && hal_chk_band_cap(adapter, BAND_CAP_5G))\n\t\t\treturn 1;\n\n\treturn 0;\n}\ninline bool hal_is_mimo_support(_adapter *adapter)\n{\n\tif ((GET_HAL_SPEC(adapter)->tx_nss_num == 1) &&\n\t\t(GET_HAL_SPEC(adapter)->rx_nss_num == 1))\n\t\treturn 0;\n\treturn 1;\n}\n\n/*\n* hal_largest_bw - starting from in_bw, get largest bw supported by HAL\n* @adapter:\n* @in_bw: starting bw, value of enum channel_width\n*\n* Returns: value of enum channel_width\n*/\nu8 hal_largest_bw(_adapter *adapter, u8 in_bw)\n{\n\tfor (; in_bw > CHANNEL_WIDTH_20; in_bw--) {\n\t\tif (hal_is_bw_support(adapter, in_bw))\n\t\t\tbreak;\n\t}\n\n\tif (!hal_is_bw_support(adapter, in_bw))\n\t\trtw_warn_on(1);\n\n\treturn in_bw;\n}\n\nvoid ResumeTxBeacon(_adapter *padapter)\n{\n\trtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2,\n\t\trtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2) | BIT(6));\n\n#ifdef RTW_HALMAC\n\t/* Add this for driver using HALMAC because driver doesn't have setup time init by self */\n\t/* TBTT setup time */\n\trtw_write8(padapter, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME);\n#endif\n\n\t/* TBTT hold time: 0x540[19:8] */\n\trtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME & 0xFF);\n\trtw_write8(padapter, REG_TBTT_PROHIBIT + 2,\n\t\t(rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME >> 8));\n}\n\nvoid StopTxBeacon(_adapter *padapter)\n{\n\trtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2,\n\t\trtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2) & (~BIT6));\n\n\t/* TBTT hold time: 0x540[19:8] */\n\trtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);\n\trtw_write8(padapter, REG_TBTT_PROHIBIT + 2,\n\t\t(rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8));\n}\n\n#ifdef CONFIG_MI_WITH_MBSSID_CAM /*HW port0 - MBSS*/\n\n#ifdef CONFIG_CLIENT_PORT_CFG\nconst u8 _clt_port_id[MAX_CLIENT_PORT_NUM] = {\n\tCLT_PORT0,\n\tCLT_PORT1,\n\tCLT_PORT2,\n\tCLT_PORT3\n};\n\nvoid rtw_clt_port_init(struct clt_port_t  *cltp)\n{\n\tcltp->bmp = 0;\n\tcltp->num = 0;\n\t_rtw_spinlock_init(&cltp->lock);\n}\nvoid rtw_clt_port_deinit(struct clt_port_t *cltp)\n{\n\t_rtw_spinlock_free(&cltp->lock);\n}\nstatic void _hw_client_port_alloc(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct clt_port_t  *cltp = &dvobj->clt_port;\n\t_irqL irql;\n\tint i;\n\n\t#if 0\n\tif (cltp->num > MAX_CLIENT_PORT_NUM) {\n\t\tRTW_ERR(ADPT_FMT\" cann't  alloc client (%d)\\n\", ADPT_ARG(adapter), cltp->num);\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\t#endif\n\n\tif (adapter->client_id !=  MAX_CLIENT_PORT_NUM) {\n\t\tRTW_INFO(ADPT_FMT\" client_id %d has allocated port:%d\\n\",\n\t\t\tADPT_ARG(adapter), adapter->client_id, adapter->client_port);\n\t\treturn;\n\t}\n\t_enter_critical_bh(&cltp->lock, &irql);\n\tfor (i = 0; i < MAX_CLIENT_PORT_NUM; i++) {\n\t\tif (!(cltp->bmp & BIT(i)))\n\t\t\tbreak;\n\t}\n\n\tif (i < MAX_CLIENT_PORT_NUM) {\n\t\tadapter->client_id = i;\n\t\tcltp->bmp |= BIT(i);\n\t\tadapter->client_port = _clt_port_id[i];\n\t}\n\tcltp->num++;\n\t_exit_critical_bh(&cltp->lock, &irql);\n\tRTW_INFO(\"%s(\"ADPT_FMT\")id:%d, port:%d clt_num:%d\\n\",\n\t\t__func__, ADPT_ARG(adapter), adapter->client_id, adapter->client_port, cltp->num);\n}\nstatic void _hw_client_port_free(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct clt_port_t  *cltp = &dvobj->clt_port;\n\t_irqL irql;\n\n\t#if 0\n\tif (adapter->client_id >=  MAX_CLIENT_PORT_NUM) {\n\t\tRTW_ERR(ADPT_FMT\" client_id %d is invalid\\n\", ADPT_ARG(adapter), adapter->client_id);\n\t\t/*rtw_warn_on(1);*/\n\t}\n\t#endif\n\n\tRTW_INFO(\"%s (\"ADPT_FMT\") id:%d, port:%d clt_num:%d\\n\",\n\t\t__func__, ADPT_ARG(adapter), adapter->client_id, adapter->client_port, cltp->num);\n\n\t_enter_critical_bh(&cltp->lock, &irql);\n\tif (adapter->client_id !=  MAX_CLIENT_PORT_NUM) {\n\t\tcltp->bmp &= ~ BIT(adapter->client_id);\n\t\tadapter->client_id = MAX_CLIENT_PORT_NUM;\n\t\tadapter->client_port = CLT_PORT_INVALID;\n\t}\n\tcltp->num--;\n\tif (cltp->num < 0)\n\t\tcltp->num = 0;\n\t_exit_critical_bh(&cltp->lock, &irql);\n}\nvoid rtw_hw_client_port_allocate(_adapter *adapter)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\n\tif (hal_spec->port_num != 5)\n\t\treturn;\n\n\t_hw_client_port_alloc(adapter);\n}\nvoid rtw_hw_client_port_release(_adapter *adapter)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\n\tif (hal_spec->port_num != 5)\n\t\treturn;\n\n\t_hw_client_port_free(adapter);\n}\n#endif /*CONFIG_CLIENT_PORT_CFG*/\n\nvoid hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode)\n{\n\tRTW_INFO(\"%s()-\"ADPT_FMT\" mode = %d\\n\", __func__, ADPT_ARG(Adapter), mode);\n\n\trtw_hal_rcr_set_chk_bssid(Adapter, MLME_ACTION_NONE);\n\n\t/* set net_type */\n\tSet_MSR(Adapter, mode);\n\n\tif ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {\n\t\tif (!rtw_mi_get_ap_num(Adapter) && !rtw_mi_get_mesh_num(Adapter))\n\t\t\tStopTxBeacon(Adapter);\n\t} else if (mode == _HW_STATE_ADHOC_)\n\t\tResumeTxBeacon(Adapter);\n\telse if (mode == _HW_STATE_AP_)\n\t\t/* enable rx ps-poll */\n\t\trtw_write16(Adapter, REG_RXFLTMAP1, rtw_read16(Adapter, REG_RXFLTMAP1) | BIT_CTRLFLT10EN);\n\n\t/* enable rx data frame */\n\trtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);\n\n#ifdef CONFIG_CLIENT_PORT_CFG\n\tif (mode == _HW_STATE_STATION_)\n\t\trtw_hw_client_port_allocate(Adapter);\n\telse\n\t\trtw_hw_client_port_release(Adapter);\n#endif\n#if defined(CONFIG_RTL8192F)\n\t\trtw_write16(Adapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(Adapter, \n\t\t\t\t\tREG_WLAN_ACT_MASK_CTRL_1) | EN_PORT_0_FUNCTION);\t\n#endif\n}\n#endif\n\n#ifdef CONFIG_ANTENNA_DIVERSITY\nu8\trtw_hal_antdiv_before_linked(_adapter *padapter)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\tu8 cur_ant, change_ant;\n\n\tif (!pHalData->AntDivCfg)\n\t\treturn _FALSE;\n\n\tif (pHalData->sw_antdiv_bl_state == 0) {\n\t\tpHalData->sw_antdiv_bl_state = 1;\n\n\t\trtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL);\n\t\tchange_ant = (cur_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;\n\n\t\treturn rtw_antenna_select_cmd(padapter, change_ant, _FALSE);\n\t}\n\n\tpHalData->sw_antdiv_bl_state = 0;\n\treturn _FALSE;\n}\n\nvoid\trtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\n\tif (pHalData->AntDivCfg) {\n\t\t/*RTW_INFO(\"update_network=> org-RSSI(%d), new-RSSI(%d)\\n\", dst->Rssi, src->Rssi);*/\n\t\t/*select optimum_antenna for before linked =>For antenna diversity*/\n\t\tif (dst->Rssi >=  src->Rssi) {/*keep org parameter*/\n\t\t\tsrc->Rssi = dst->Rssi;\n\t\t\tsrc->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna;\n\t\t}\n\t}\n}\n#endif\n\n#ifdef CONFIG_PHY_CAPABILITY_QUERY\nvoid rtw_dump_phy_cap_by_phydmapi(void *sel, _adapter *adapter)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);\n\tstruct phy_spec_t *phy_spec = &pHalData->phy_spec;\n\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] TRx Capability : 0x%08x\\n\", phy_spec->trx_cap);\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] Tx Stream Num Index : %d\\n\", (phy_spec->trx_cap >> 24) & 0xFF); /*Tx Stream Num Index [31:24]*/\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] Rx Stream Num Index : %d\\n\", (phy_spec->trx_cap >> 16) & 0xFF); /*Rx Stream Num Index [23:16]*/\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] Tx Path Num Index : %d\\n\", (phy_spec->trx_cap >> 8) & 0xFF);/*Tx Path Num Index\t[15:8]*/\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] Rx Path Num Index : %d\\n\\n\", (phy_spec->trx_cap & 0xFF));/*Rx Path Num Index\t[7:0]*/\n\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] STBC Capability : 0x%08x\\n\", phy_spec->stbc_cap);\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] VHT STBC Tx : %s\\n\", ((phy_spec->stbc_cap >> 24) & 0xFF) ? \"Supported\" : \"N/A\"); /*VHT STBC Tx [31:24]*/\n\t/*VHT STBC Rx [23:16]\n\t0 = not support\n\t1 = support for 1 spatial stream\n\t2 = support for 1 or 2 spatial streams\n\t3 = support for 1 or 2 or 3 spatial streams\n\t4 = support for 1 or 2 or 3 or 4 spatial streams*/\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] VHT STBC Rx :%d\\n\", ((phy_spec->stbc_cap >> 16) & 0xFF));\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] HT STBC Tx : %s\\n\", ((phy_spec->stbc_cap >> 8) & 0xFF) ? \"Supported\" : \"N/A\"); /*HT STBC Tx [15:8]*/\n\t/*HT STBC Rx [7:0]\n\t0 = not support\n\t1 = support for 1 spatial stream\n\t2 = support for 1 or 2 spatial streams\n\t3 = support for 1 or 2 or 3 spatial streams*/\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] HT STBC Rx : %d\\n\\n\", (phy_spec->stbc_cap & 0xFF));\n\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] LDPC Capability : 0x%08x\\n\", phy_spec->ldpc_cap);\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] VHT LDPC Tx : %s\\n\", ((phy_spec->ldpc_cap >> 24) & 0xFF) ? \"Supported\" : \"N/A\"); /*VHT LDPC Tx [31:24]*/\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] VHT LDPC Rx : %s\\n\", ((phy_spec->ldpc_cap >> 16) & 0xFF) ? \"Supported\" : \"N/A\"); /*VHT LDPC Rx [23:16]*/\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] HT LDPC Tx : %s\\n\", ((phy_spec->ldpc_cap >> 8) & 0xFF) ? \"Supported\" : \"N/A\"); /*HT LDPC Tx [15:8]*/\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] HT LDPC Rx : %s\\n\\n\", (phy_spec->ldpc_cap & 0xFF) ? \"Supported\" : \"N/A\"); /*HT LDPC Rx [7:0]*/\n\t#ifdef CONFIG_BEAMFORMING\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] TxBF Capability : 0x%08x\\n\", phy_spec->txbf_cap);\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] VHT MU Bfer : %s\\n\", ((phy_spec->txbf_cap >> 28) & 0xF) ? \"Supported\" : \"N/A\"); /*VHT MU Bfer [31:28]*/\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] VHT MU Bfee : %s\\n\", ((phy_spec->txbf_cap >> 24) & 0xF) ? \"Supported\" : \"N/A\"); /*VHT MU Bfee [27:24]*/\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] VHT SU Bfer : %s\\n\", ((phy_spec->txbf_cap >> 20) & 0xF) ? \"Supported\" : \"N/A\"); /*VHT SU Bfer [23:20]*/\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] VHT SU Bfee : %s\\n\", ((phy_spec->txbf_cap >> 16) & 0xF) ? \"Supported\" : \"N/A\"); /*VHT SU Bfee [19:16]*/\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] HT Bfer : %s\\n\", ((phy_spec->txbf_cap >> 4) & 0xF)  ? \"Supported\" : \"N/A\"); /*HT Bfer [7:4]*/\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] HT Bfee : %s\\n\\n\", (phy_spec->txbf_cap & 0xF) ? \"Supported\" : \"N/A\"); /*HT Bfee [3:0]*/\n\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] TxBF parameter : 0x%08x\\n\", phy_spec->txbf_param);\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] VHT Sounding Dim : %d\\n\", (phy_spec->txbf_param >> 24) & 0xFF); /*VHT Sounding Dim [31:24]*/\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] VHT Steering Ant : %d\\n\", (phy_spec->txbf_param >> 16) & 0xFF); /*VHT Steering Ant [23:16]*/\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] HT Sounding Dim : %d\\n\", (phy_spec->txbf_param >> 8) & 0xFF); /*HT Sounding Dim [15:8]*/\n\tRTW_PRINT_SEL(sel, \"[PHY SPEC] HT Steering Ant : %d\\n\", phy_spec->txbf_param & 0xFF); /*HT Steering Ant [7:0]*/\n\t#endif\n}\n#else\nvoid rtw_dump_phy_cap_by_hal(void *sel, _adapter *adapter)\n{\n\tu8 phy_cap = _FALSE;\n\n\t/* STBC */\n\trtw_hal_get_def_var(adapter, HAL_DEF_TX_STBC, (u8 *)&phy_cap);\n\tRTW_PRINT_SEL(sel, \"[HAL] STBC Tx : %s\\n\", (_TRUE == phy_cap) ? \"Supported\" : \"N/A\");\n\n\tphy_cap = _FALSE;\n\trtw_hal_get_def_var(adapter, HAL_DEF_RX_STBC, (u8 *)&phy_cap);\n\tRTW_PRINT_SEL(sel, \"[HAL] STBC Rx : %s\\n\\n\", (_TRUE == phy_cap) ? \"Supported\" : \"N/A\");\n\n\t/* LDPC support */\n\tphy_cap = _FALSE;\n\trtw_hal_get_def_var(adapter, HAL_DEF_TX_LDPC, (u8 *)&phy_cap);\n\tRTW_PRINT_SEL(sel, \"[HAL] LDPC Tx : %s\\n\", (_TRUE == phy_cap) ? \"Supported\" : \"N/A\");\n\n\tphy_cap = _FALSE;\n\trtw_hal_get_def_var(adapter, HAL_DEF_RX_LDPC, (u8 *)&phy_cap);\n\tRTW_PRINT_SEL(sel, \"[HAL] LDPC Rx : %s\\n\\n\", (_TRUE == phy_cap) ? \"Supported\" : \"N/A\");\n\t\n\t#ifdef CONFIG_BEAMFORMING\n\tphy_cap = _FALSE;\n\trtw_hal_get_def_var(adapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&phy_cap);\n\tRTW_PRINT_SEL(sel, \"[HAL] Beamformer: %s\\n\", (_TRUE == phy_cap) ? \"Supported\" : \"N/A\");\n\n\tphy_cap = _FALSE;\n\trtw_hal_get_def_var(adapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&phy_cap);\n\tRTW_PRINT_SEL(sel, \"[HAL] Beamformee: %s\\n\", (_TRUE == phy_cap) ? \"Supported\" : \"N/A\");\n\n\tphy_cap = _FALSE;\n\trtw_hal_get_def_var(adapter, HAL_DEF_VHT_MU_BEAMFORMER, &phy_cap);\n\tRTW_PRINT_SEL(sel, \"[HAL] VHT MU Beamformer: %s\\n\", (_TRUE == phy_cap) ? \"Supported\" : \"N/A\");\n\n\tphy_cap = _FALSE;\n\trtw_hal_get_def_var(adapter, HAL_DEF_VHT_MU_BEAMFORMEE, &phy_cap);\n\tRTW_PRINT_SEL(sel, \"[HAL] VHT MU Beamformee: %s\\n\", (_TRUE == phy_cap) ? \"Supported\" : \"N/A\");\n\t#endif\n}\n#endif\nvoid rtw_dump_phy_cap(void *sel, _adapter *adapter)\n{\n\tRTW_PRINT_SEL(sel, \"\\n ======== PHY Capability ========\\n\");\n#ifdef CONFIG_PHY_CAPABILITY_QUERY\n\trtw_dump_phy_cap_by_phydmapi(sel, adapter);\n#else\n\trtw_dump_phy_cap_by_hal(sel, adapter);\n#endif\n}\n\ninline s16 translate_dbm_to_percentage(s16 signal)\n{\n\tif ((signal <= -100) || (signal >= 20))\n\t\treturn\t0;\n\telse if (signal >= 0)\n\t\treturn\t100;\n\telse\n\t\treturn 100 + signal;\n}\n\n#ifdef CONFIG_SWTIMER_BASED_TXBCN\n#ifdef CONFIG_BCN_RECOVERY\n#define REG_CPU_MGQ_INFO\t0x041C\n#define BIT_BCN_POLL\t\t\tBIT(28)\nu8 rtw_ap_bcn_recovery(_adapter *padapter)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);\n\n\tif (hal_data->issue_bcn_fail >= 2) {\n\t\tRTW_ERR(\"%s ISSUE BCN Fail\\n\", __func__);\n\t\trtw_write8(padapter, REG_CPU_MGQ_INFO + 3, 0x10);\n\t\thal_data->issue_bcn_fail = 0;\n\t}\n\treturn _SUCCESS;\n}\n#endif /*CONFIG_BCN_RECOVERY*/\n\n#ifdef CONFIG_BCN_XMIT_PROTECT\nu8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms)\n{\n\tu32 start_time = rtw_get_current_time();\n\tu8 bcn_queue_empty = _FALSE;\n\n\tdo {\n\t\tif (rtw_read16(padapter, REG_TXPKT_EMPTY) & BIT(11)) {\n\t\t\tbcn_queue_empty = _TRUE;\n\t\t\tbreak;\n\t\t}\n\t} while (rtw_get_passing_time_ms(start_time) <= (txbcn_timer_ms + 10));\n\n\tif (bcn_queue_empty == _FALSE)\n\t\tRTW_ERR(\"%s BCN queue not empty\\n\", __func__);\n\n\treturn bcn_queue_empty;\n}\n#endif /*CONFIG_BCN_XMIT_PROTECT*/\n#endif /*CONFIG_SWTIMER_BASED_TXBCN*/\n\nstatic void _rf_type_to_ant_path(enum rf_type rf, enum bb_path *tx,\n\t\t\t\t enum bb_path *rx)\n{\n\tif (tx) {\n\t\tswitch (rf) {\n\t\tcase RF_1T1R:\n\t\tcase RF_1T2R:\n\t\t\t*tx = BB_PATH_A;\n\t\t\tbreak;\n\t\tcase RF_2T2R:\n\t\tcase RF_2T3R:\n\t\tcase RF_2T4R:\n\t\t\t*tx = BB_PATH_AB;\n\t\t\tbreak;\n\t\tcase RF_3T3R:\n\t\tcase RF_3T4R:\n\t\t\t*tx = BB_PATH_ABC;\n\t\t\tbreak;\n\t\tcase RF_4T4R:\n\t\tdefault:\n\t\t\t*tx = BB_PATH_ABCD;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (rx) {\n\t\tswitch (rf) {\n\t\tcase RF_1T1R:\n\t\t\t*rx = BB_PATH_A;\n\t\t\tbreak;\n\t\tcase RF_1T2R:\n\t\tcase RF_2T2R:\n\t\t\t*rx = BB_PATH_AB;\n\t\t\tbreak;\n\t\tcase RF_2T3R:\n\t\tcase RF_3T3R:\n\t\t\t*rx = BB_PATH_ABC;\n\t\t\tbreak;\n\t\tcase RF_2T4R:\n\t\tcase RF_3T4R:\n\t\tcase RF_4T4R:\n\t\tdefault:\n\t\t\t*rx = BB_PATH_ABCD;\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\n/**\n * rtw_hal_get_rf_path() - Get RF path related information\n * @d:\t\tstruct dvobj_priv*\n * @type:\tRF type, nTnR\n * @tx:\t\tTx path\n * @rx:\t\tRx path\n *\n * Get RF type, TX path and RX path information.\n */\nvoid rtw_hal_get_rf_path(struct dvobj_priv *d, enum rf_type *type,\n\t\t\t enum bb_path *tx, enum bb_path *rx)\n{\n\tstruct _ADAPTER *a;\n\tu8 val8 = RF_1T1R;\n\tenum rf_type rf;\n\n\n\ta = dvobj_get_primary_adapter(d);\n#ifndef CONFIG_CUSTOMER01_SMART_ANTENNA\n\trtw_hal_get_hwreg(a, HW_VAR_RF_TYPE, &val8);\n#else\n\tval8 = RF_2T2R;\n#endif\n\trf = (enum rf_type)val8;\n\tif (type)\n\t\t*type = rf;\n\n\tif (tx || rx)\n\t\t_rf_type_to_ant_path(rf, tx, rx);\n}\n\n#ifdef RTW_CHANNEL_SWITCH_OFFLOAD\nvoid rtw_hal_switch_chnl_and_set_bw_offload(_adapter *adapter, u8 central_ch, u8 pri_ch_idx, u8 bw)\n{\n\tu8 h2c[H2C_SINGLE_CHANNELSWITCH_V2_LEN] = {0};\n\tPHAL_DATA_TYPE hal;\n\tstruct submit_ctx *chsw_sctx;\n\n\thal = GET_HAL_DATA(adapter);\n\tchsw_sctx = &hal->chsw_sctx;\n\n\tSET_H2CCMD_SINGLE_CH_SWITCH_V2_CENTRAL_CH_NUM(h2c, central_ch);\n\tSET_H2CCMD_SINGLE_CH_SWITCH_V2_PRIMARY_CH_IDX(h2c, pri_ch_idx);\n\tSET_H2CCMD_SINGLE_CH_SWITCH_V2_BW(h2c, bw);\n\n\trtw_sctx_init(chsw_sctx, 10);\n\trtw_hal_fill_h2c_cmd(adapter, H2C_SINGLE_CHANNELSWITCH_V2, H2C_SINGLE_CHANNELSWITCH_V2_LEN, h2c);\n\trtw_sctx_wait(chsw_sctx, __func__);\n}\n#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */\n\n#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8812A) ||\\\n\tdefined(CONFIG_RTL8192F) || defined(CONFIG_RTL8192E) ||\\\n\tdefined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821A) ||\\\n\t defined (CONFIG_RTL8822C)\nu8 phy_get_current_tx_num(\n\t\tPADAPTER\t\tpAdapter,\n\t\tu8\t\t\t\tRate\n)\n{\n\tu8\ttx_num = RF_1TX;\n\n\tif (IS_1T_RATE(Rate)) {\n\t#if defined(CONFIG_RTW_TX_2PATH_EN)\n\t\ttx_num = RF_2TX;\n\t#else\n\t\ttx_num = RF_1TX;\n\t#endif\n\t} else if (IS_2T_RATE(Rate))\n\t\ttx_num = RF_2TX;\n\telse if (IS_3T_RATE(Rate))\n\t\ttx_num = RF_3TX;\n\telse\n\t\trtw_warn_on(1);\n\n\treturn tx_num;\n}\n#endif\n#ifdef CONFIG_RTL8812A\nu8 * rtw_hal_set_8812a_vendor_ie(_adapter *padapter , u8 *pframe ,uint *frlen ) {\n\tint vender_len = 7;\n\tunsigned char\tvendor_info[vender_len];\n\tunsigned char REALTEK_OUI[] = {0x00, 0xe0, 0x4c};\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n\tif( !IS_HARDWARE_TYPE_8812(padapter) )\n\t\treturn pframe;\n\n\t_rtw_memset(vendor_info,0,vender_len);\n\t_rtw_memcpy(vendor_info, REALTEK_OUI, 3);\n\tvendor_info[4] =2;\n\tif(pHalData->version_id.CUTVersion > B_CUT_VERSION )\n\t\tvendor_info[6] = RT_HT_CAP_USE_JAGUAR_CCUT;\n\telse\n\t\tvendor_info[6] = RT_HT_CAP_USE_JAGUAR_BCUT;\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_,vender_len,vendor_info , frlen);\n\t\n\treturn pframe;\n}\n#endif /*CONFIG_RTL8812A*/\n\n"
  },
  {
    "path": "hal/hal_com_c2h.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __COMMON_C2H_H__\n#define __COMMON_C2H_H__\n\n#define C2H_TYPE_REG 0\n#define C2H_TYPE_PKT 1\n\n/* \n* C2H event format:\n* Fields    TRIGGER    PAYLOAD    SEQ    PLEN    ID\n* BITS     [127:120]    [119:16]   [15:8]  [7:4]  [3:0]\n*/\n#define C2H_ID(_c2h)\t\tLE_BITS_TO_1BYTE(((u8*)(_c2h)), 0, 4)\n#define C2H_PLEN(_c2h)\t\tLE_BITS_TO_1BYTE(((u8*)(_c2h)), 4, 4)\n#define C2H_SEQ(_c2h)\t\tLE_BITS_TO_1BYTE(((u8*)(_c2h)) + 1, 0, 8)\n#define C2H_PAYLOAD(_c2h)\t(((u8*)(_c2h)) + 2)\n\n#define SET_C2H_ID(_c2h, _val)\t\tSET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 0, 4, _val)\n#define SET_C2H_PLEN(_c2h, _val)\tSET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 4, 4, _val)\n#define SET_C2H_SEQ(_c2h, _val)\t\tSET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 1 , 0, 8, _val)\n\n/* \n* C2H event format:\n* Fields    TRIGGER     PLEN      PAYLOAD    SEQ      ID\n* BITS    [127:120]  [119:112]  [111:16]   [15:8]   [7:0]\n*/\n#define C2H_ID_88XX(_c2h)\t\tLE_BITS_TO_1BYTE(((u8*)(_c2h)), 0, 8)\n#define C2H_SEQ_88XX(_c2h)\t\tLE_BITS_TO_1BYTE(((u8*)(_c2h)) + 1, 0, 8)\n#define C2H_PAYLOAD_88XX(_c2h)\t(((u8*)(_c2h)) + 2)\n#define C2H_PLEN_88XX(_c2h)\t\tLE_BITS_TO_1BYTE(((u8*)(_c2h)) + 14, 0, 8)\n#define C2H_TRIGGER_88XX(_c2h)\tLE_BITS_TO_1BYTE(((u8*)(_c2h)) + 15, 0, 8)\n\n#define SET_C2H_ID_88XX(_c2h, _val)\t\tSET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 0, 8, _val)\n#define SET_C2H_SEQ_88XX(_c2h, _val)\tSET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 1, 0, 8, _val)\n#define SET_C2H_PLEN_88XX(_c2h, _val)\tSET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 14, 0, 8, _val)\n\ntypedef enum _C2H_EVT {\n\tC2H_DBG = 0x00,\n\tC2H_LB = 0x01,\n\tC2H_TXBF = 0x02,\n\tC2H_CCX_TX_RPT = 0x03,\n\tC2H_AP_REQ_TXRPT = 0x04,\n\tC2H_FW_SCAN_COMPLETE = 0x7,\n\tC2H_BT_INFO = 0x09,\n\tC2H_BT_MP_INFO = 0x0B,\n\tC2H_RA_RPT = 0x0C,\n\tC2H_SPC_STAT = 0x0D,\n\tC2H_RA_PARA_RPT = 0x0E,\n\tC2H_FW_CHNL_SWITCH_COMPLETE = 0x10,\n\tC2H_IQK_FINISH = 0x11,\n\tC2H_MAILBOX_STATUS = 0x15,\n\tC2H_P2P_RPORT = 0x16,\n\tC2H_MCC = 0x17,\n\tC2H_MAC_HIDDEN_RPT = 0x19,\n\tC2H_MAC_HIDDEN_RPT_2 = 0x1A,\n\tC2H_BCN_EARLY_RPT = 0x1E,\n\tC2H_DEFEATURE_DBG = 0x22,\n\tC2H_CUSTOMER_STR_RPT = 0x24,\n\tC2H_CUSTOMER_STR_RPT_2 = 0x25,\n\tC2H_WLAN_INFO = 0x27,\n#ifdef RTW_PER_CMD_SUPPORT_FW\n\tC2H_PER_RATE_RPT = 0x2c,\n#endif\n\tC2H_LPS_STATUS_RPT = 0x32,\n\tC2H_DEFEATURE_RSVD = 0xFD,\n\tC2H_EXTEND = 0xff,\n} C2H_EVT;\n\ntypedef enum _EXTEND_C2H_EVT {\n\tEXTEND_C2H_DBG_PRINT = 0\n} EXTEND_C2H_EVT;\n\n#define C2H_REG_LEN 16\n\n/* C2H_IQK_FINISH, 0x11 */\n#define IQK_OFFLOAD_LEN 1\nvoid c2h_iqk_offload(_adapter *adapter, u8 *data, u8 len);\nint\tc2h_iqk_offload_wait(_adapter *adapter, u32 timeout_ms);\n#define rtl8812_iqk_wait c2h_iqk_offload_wait /* TODO: remove this after phydm call c2h_iqk_offload_wait instead */\n\n#ifdef CONFIG_RTW_MAC_HIDDEN_RPT\n/* C2H_MAC_HIDDEN_RPT, 0x19 */\n#define MAC_HIDDEN_RPT_LEN 8\nint c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len);\n\n/* C2H_MAC_HIDDEN_RPT_2, 0x1A */\n#define MAC_HIDDEN_RPT_2_LEN 5\nint c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len);\nint hal_read_mac_hidden_rpt(_adapter *adapter);\n#else\n#define hal_read_mac_hidden_rpt(adapter) _SUCCESS\n#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */\n\n/* C2H_DEFEATURE_DBG, 0x22 */\n#define DEFEATURE_DBG_LEN 1\nint c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len);\n\n#ifdef CONFIG_RTW_CUSTOMER_STR\n/* C2H_CUSTOMER_STR_RPT, 0x24 */\n#define CUSTOMER_STR_RPT_LEN 8\nint c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len);\n\n/* C2H_CUSTOMER_STR_RPT_2, 0x25 */\n#define CUSTOMER_STR_RPT_2_LEN 8\nint c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len);\n#endif /* CONFIG_RTW_CUSTOMER_STR */\n\n#ifdef RTW_PER_CMD_SUPPORT_FW\n/* C2H_PER_RATE_RPT, 0x2c */\nint c2h_per_rate_rpt_hdl(_adapter *adapter, u8 *data, u8 len);\n#endif\n\n#endif /* __COMMON_C2H_H__ */\n"
  },
  {
    "path": "hal/hal_com_phycfg.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _HAL_COM_PHYCFG_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\n#define PG_TXPWR_1PATH_BYTE_NUM_2G 18\n#define PG_TXPWR_BASE_BYTE_NUM_2G 11\n\n#define PG_TXPWR_1PATH_BYTE_NUM_5G 24\n#define PG_TXPWR_BASE_BYTE_NUM_5G 14\n\n#define PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) (((_pg_v) & 0xf0) >> 4)\n#define PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) ((_pg_v) & 0x0f)\n#define PG_TXPWR_MSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_MSB_DIFF_S4BIT(_pg_v))\n#define PG_TXPWR_LSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_LSB_DIFF_S4BIT(_pg_v))\n#define IS_PG_TXPWR_BASE_INVALID(hal_spec, _base) ((_base) > hal_spec->txgi_max)\n#define IS_PG_TXPWR_DIFF_INVALID(_diff) ((_diff) > 7 || (_diff) < -8)\n#define PG_TXPWR_INVALID_BASE 255\n#define PG_TXPWR_INVALID_DIFF 8\n\n#if !IS_PG_TXPWR_DIFF_INVALID(PG_TXPWR_INVALID_DIFF)\n#error \"PG_TXPWR_DIFF definition has problem\"\n#endif\n\n#define PG_TXPWR_SRC_PG_DATA\t0\n#define PG_TXPWR_SRC_IC_DEF\t\t1\n#define PG_TXPWR_SRC_DEF\t\t2\n#define PG_TXPWR_SRC_NUM\t\t3\n\nconst char *const _pg_txpwr_src_str[] = {\n\t\"PG_DATA\",\n\t\"IC_DEF\",\n\t\"DEF\",\n\t\"UNKNOWN\"\n};\n\n#define pg_txpwr_src_str(src) (((src) >= PG_TXPWR_SRC_NUM) ? _pg_txpwr_src_str[PG_TXPWR_SRC_NUM] : _pg_txpwr_src_str[(src)])\n\n#ifndef DBG_PG_TXPWR_READ\n#define DBG_PG_TXPWR_READ 0\n#endif\n\n#if DBG_PG_TXPWR_READ\nstatic void dump_pg_txpwr_info_2g(void *sel, TxPowerInfo24G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt)\n{\n\tint path, group, tx_idx;\n\n\tRTW_PRINT_SEL(sel, \"2.4G\\n\");\n\tRTW_PRINT_SEL(sel, \"CCK-1T base:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (group = 0; group < MAX_CHNL_GROUP_24G; group++)\n\t\t_RTW_PRINT_SEL(sel, \"G%02d \", group);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (group = 0; group < MAX_CHNL_GROUP_24G; group++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%3u \", txpwr_info->IndexCCK_Base[path][group]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"CCK diff:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)\n\t\t_RTW_PRINT_SEL(sel, \"%dT \", path + 1);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%2d \", txpwr_info->CCK_Diff[path][tx_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"BW40-1S base:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++)\n\t\t_RTW_PRINT_SEL(sel, \"G%02d \", group);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%3u \", txpwr_info->IndexBW40_Base[path][group]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"OFDM diff:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)\n\t\t_RTW_PRINT_SEL(sel, \"%dT \", path + 1);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%2d \", txpwr_info->OFDM_Diff[path][tx_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"BW20 diff:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)\n\t\t_RTW_PRINT_SEL(sel, \"%dS \", path + 1);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%2d \", txpwr_info->BW20_Diff[path][tx_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"BW40 diff:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)\n\t\t_RTW_PRINT_SEL(sel, \"%dS \", path + 1);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%2d \", txpwr_info->BW40_Diff[path][tx_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n}\n\nstatic void dump_pg_txpwr_info_5g(void *sel, TxPowerInfo5G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt)\n{\n\tint path, group, tx_idx;\n\n\tRTW_PRINT_SEL(sel, \"5G\\n\");\n\tRTW_PRINT_SEL(sel, \"BW40-1S base:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (group = 0; group < MAX_CHNL_GROUP_5G; group++)\n\t\t_RTW_PRINT_SEL(sel, \"G%02d \", group);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (group = 0; group < MAX_CHNL_GROUP_5G; group++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%3u \", txpwr_info->IndexBW40_Base[path][group]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"OFDM diff:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)\n\t\t_RTW_PRINT_SEL(sel, \"%dT \", path + 1);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%2d \", txpwr_info->OFDM_Diff[path][tx_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"BW20 diff:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)\n\t\t_RTW_PRINT_SEL(sel, \"%dS \", path + 1);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%2d \", txpwr_info->BW20_Diff[path][tx_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"BW40 diff:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)\n\t\t_RTW_PRINT_SEL(sel, \"%dS \", path + 1);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%2d \", txpwr_info->BW40_Diff[path][tx_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"BW80 diff:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)\n\t\t_RTW_PRINT_SEL(sel, \"%dS \", path + 1);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%2d \", txpwr_info->BW80_Diff[path][tx_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"BW160 diff:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)\n\t\t_RTW_PRINT_SEL(sel, \"%dS \", path + 1);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%2d \", txpwr_info->BW160_Diff[path][tx_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n}\n#endif /* DBG_PG_TXPWR_READ */\n\nconst struct map_t pg_txpwr_def_info =\n\tMAP_ENT(0xB8, 1, 0xFF\n\t\t, MAPSEG_ARRAY_ENT(0x10, 168,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE,\n\t\t\t0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,\n\t\t\t0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A,\n\t\t\t0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,\n\t\t\t0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24,\n\t\t\t0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,\n\t\t\t0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,\n\t\t\t0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE,\n\t\t\t0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE)\n\t);\n\n#ifdef CONFIG_RTL8188E\nstatic const struct map_t rtl8188e_pg_txpwr_def_info =\n\tMAP_ENT(0xB8, 1, 0xFF\n\t\t, MAPSEG_ARRAY_ENT(0x10, 12,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24)\n\t);\n#endif\n\n#ifdef CONFIG_RTL8188F\nstatic const struct map_t rtl8188f_pg_txpwr_def_info =\n\tMAP_ENT(0xB8, 1, 0xFF\n\t\t, MAPSEG_ARRAY_ENT(0x10, 12,\n\t\t\t0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x27, 0x27, 0x27, 0x27, 0x24)\n\t);\n#endif\n\n#ifdef CONFIG_RTL8188GTV\nstatic const struct map_t rtl8188gtv_pg_txpwr_def_info =\n\tMAP_ENT(0xB8, 1, 0xFF\n\t\t, MAPSEG_ARRAY_ENT(0x10, 12,\n\t\t\t0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x27, 0x27, 0x27, 0x27, 0x24)\n\t);\n#endif\n\n#ifdef CONFIG_RTL8723B\nstatic const struct map_t rtl8723b_pg_txpwr_def_info =\n\tMAP_ENT(0xB8, 2, 0xFF\n\t\t, MAPSEG_ARRAY_ENT(0x10, 12,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0xE0)\n\t\t, MAPSEG_ARRAY_ENT(0x3A, 12,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0xE0)\n\t);\n#endif\n\n#ifdef CONFIG_RTL8703B\nstatic const struct map_t rtl8703b_pg_txpwr_def_info =\n\tMAP_ENT(0xB8, 1, 0xFF\n\t\t, MAPSEG_ARRAY_ENT(0x10, 12,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)\n\t);\n#endif\n\n#ifdef CONFIG_RTL8723D\nstatic const struct map_t rtl8723d_pg_txpwr_def_info =\n\tMAP_ENT(0xB8, 2, 0xFF\n\t\t, MAPSEG_ARRAY_ENT(0x10, 12,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)\n\t\t, MAPSEG_ARRAY_ENT(0x3A, 12,\n\t\t\t0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x21, 0x21, 0x21, 0x21, 0x21, 0x02)\n\t);\n#endif\n\n#ifdef CONFIG_RTL8192E\nstatic const struct map_t rtl8192e_pg_txpwr_def_info =\n\tMAP_ENT(0xB8, 2, 0xFF\n\t\t, MAPSEG_ARRAY_ENT(0x10, 14,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)\n\t\t, MAPSEG_ARRAY_ENT(0x3A, 14,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)\n\t);\n#endif\n\n#ifdef CONFIG_RTL8821A\nstatic const struct map_t rtl8821a_pg_txpwr_def_info =\n\tMAP_ENT(0xB8, 1, 0xFF\n\t\t, MAPSEG_ARRAY_ENT(0x10, 39,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xFF, 0xFF, 0xFF, 0xFF,\n\t\t\t0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,\n\t\t\t0x04, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00)\n\t);\n#endif\n\n#ifdef CONFIG_RTL8821C\nstatic const struct map_t rtl8821c_pg_txpwr_def_info =\n\tMAP_ENT(0xB8, 1, 0xFF\n\t\t, MAPSEG_ARRAY_ENT(0x10, 54,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xFF, 0xFF, 0xFF, 0xFF,\n\t\t\t0xFF, 0xFF, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,\n\t\t\t0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xEC, 0xFF, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)\n\t);\n#endif\n\n#ifdef CONFIG_RTL8710B\nstatic const struct map_t rtl8710b_pg_txpwr_def_info =\n\tMAP_ENT(0xC8, 1, 0xFF\n\t\t, MAPSEG_ARRAY_ENT(0x20, 12,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x20)\n\t);\n#endif\n\n#ifdef CONFIG_RTL8812A\nstatic const struct map_t rtl8812a_pg_txpwr_def_info =\n\tMAP_ENT(0xB8, 1, 0xFF\n\t\t, MAPSEG_ARRAY_ENT(0x10, 82,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF,\n\t\t\t0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,\n\t\t\t0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, 0x00, 0xEE, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A,\n\t\t\t0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF,\n\t\t\t0x00, 0xEE)\n\t);\n#endif\n\n#ifdef CONFIG_RTL8822B\nstatic const struct map_t rtl8822b_pg_txpwr_def_info =\n\tMAP_ENT(0xB8, 1, 0xFF\n\t\t, MAPSEG_ARRAY_ENT(0x10, 82,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF,\n\t\t\t0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,\n\t\t\t0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, 0xEC, 0xEC, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A,\n\t\t\t0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF,\n\t\t\t0xEC, 0xEC)\n\t);\n#endif\n\n#ifdef CONFIG_RTL8822C\nstatic const struct map_t rtl8822c_pg_txpwr_def_info =\n\tMAP_ENT(0xB8, 1, 0xFF\n\t\t, MAPSEG_ARRAY_ENT(0x10, 82,\n\t\t\t0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x02, 0x00, 0x00, 0xFF, 0xFF,\n\t\t\t0xFF, 0xFF, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33,\n\t\t\t0x02, 0x00, 0xFF, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0xFF, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33,\n\t\t\t0x33, 0x33, 0x33, 0x33, 0x33, 0x02, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x33, 0x33, 0x33, 0x33,\n\t\t\t0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x02, 0x00, 0xFF, 0xFF, 0x00, 0xFF,\n\t\t\t0x00, 0x00)\n\t);\n#endif\n\n#ifdef CONFIG_RTL8814A\nstatic const struct map_t rtl8814a_pg_txpwr_def_info =\n\tMAP_ENT(0xB8, 1, 0xFF\n\t\t, MAPSEG_ARRAY_ENT(0x10, 168,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE,\n\t\t\t0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,\n\t\t\t0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A,\n\t\t\t0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,\n\t\t\t0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02,\n\t\t\t0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,\n\t\t\t0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,\n\t\t\t0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE,\n\t\t\t0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE)\n\t);\n#endif\n\n#ifdef CONFIG_RTL8192F/*use 8192F default,no document*/\nstatic const struct map_t rtl8192f_pg_txpwr_def_info =\n\tMAP_ENT(0xB8, 2, 0xFF\n\t\t, MAPSEG_ARRAY_ENT(0x10, 14,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)\n\t\t, MAPSEG_ARRAY_ENT(0x3A, 14,\n\t\t\t0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)\n\t);\n#endif\n\nconst struct map_t *hal_pg_txpwr_def_info(_adapter *adapter)\n{\n\tu8 interface_type = 0;\n\tconst struct map_t *map = NULL;\n\n\tinterface_type = rtw_get_intf_type(adapter);\n\n\tswitch (rtw_get_chip_type(adapter)) {\n#ifdef CONFIG_RTL8723B\n\tcase RTL8723B:\n\t\tmap = &rtl8723b_pg_txpwr_def_info;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8703B\n\tcase RTL8703B:\n\t\tmap = &rtl8703b_pg_txpwr_def_info;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8723D\n\tcase RTL8723D:\n\t\tmap = &rtl8723d_pg_txpwr_def_info;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8188E\n\tcase RTL8188E:\n\t\tmap = &rtl8188e_pg_txpwr_def_info;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8188F\n\tcase RTL8188F:\n\t\tmap = &rtl8188f_pg_txpwr_def_info;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8188GTV\n\tcase RTL8188GTV:\n\t\tmap = &rtl8188gtv_pg_txpwr_def_info;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8812A\n\tcase RTL8812:\n\t\tmap = &rtl8812a_pg_txpwr_def_info;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8821A\n\tcase RTL8821:\n\t\tmap = &rtl8821a_pg_txpwr_def_info;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8192E\n\tcase RTL8192E:\n\t\tmap = &rtl8192e_pg_txpwr_def_info;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8814A\n\tcase RTL8814A:\n\t\tmap = &rtl8814a_pg_txpwr_def_info;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8822B\n\tcase RTL8822B:\n\t\tmap = &rtl8822b_pg_txpwr_def_info;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8821C\n\tcase RTL8821C:\n\t\tmap = &rtl8821c_pg_txpwr_def_info;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8710B\n\tcase RTL8710B:\n\t\tmap = &rtl8710b_pg_txpwr_def_info;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8192F\n\tcase RTL8192F:\n\t\tmap = &rtl8192f_pg_txpwr_def_info;\n\t\tbreak;\n#endif\n#ifdef CONFIG_RTL8822C\n\tcase RTL8822C:\n\t\tmap = &rtl8822c_pg_txpwr_def_info;\n\t\tbreak;\n#endif\n\t}\n\n\tif (map == NULL) {\n\t\tRTW_ERR(\"%s: unknown chip_type:%u\\n\"\n\t\t\t, __func__, rtw_get_chip_type(adapter));\n\t\trtw_warn_on(1);\n\t}\n\n\treturn map;\n}\n\nstatic u8 hal_chk_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tu8 path, group, tx_idx;\n\n\tif (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G))\n\t\treturn _SUCCESS;\n\n\tfor (path = 0; path < MAX_RF_PATH; path++) {\n\t\tif (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path))\n\t\t\tcontinue;\n\t\tfor (group = 0; group < MAX_CHNL_GROUP_24G; group++) {\n\t\t\tif (IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexCCK_Base[path][group])\n\t\t\t\t|| IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group]))\n\t\t\t\treturn _FAIL;\n\t\t}\n\t\tfor (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {\n\t\t\tif (!HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx))\n\t\t\t\tcontinue;\n\t\t\tif (IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx])\n\t\t\t\t|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])\n\t\t\t\t|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])\n\t\t\t\t|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx]))\n\t\t\t\treturn _FAIL;\n\t\t}\n\t}\n\n\treturn _SUCCESS;\n}\n\nstatic u8 hal_chk_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info)\n{\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tu8 path, group, tx_idx;\n\n\tif (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G))\n\t\treturn _SUCCESS;\n\n\tfor (path = 0; path < MAX_RF_PATH; path++) {\n\t\tif (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))\n\t\t\tcontinue;\n\t\tfor (group = 0; group < MAX_CHNL_GROUP_5G; group++)\n\t\t\tif (IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group]))\n\t\t\t\treturn _FAIL;\n\t\tfor (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {\n\t\t\tif (!HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx))\n\t\t\t\tcontinue;\n\t\t\tif (IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])\n\t\t\t\t|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])\n\t\t\t\t|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])\n\t\t\t\t|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx])\n\t\t\t\t|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx]))\n\t\t\t\treturn _FAIL;\n\t\t}\n\t}\n#endif /* CONFIG_IEEE80211_BAND_5GHZ */\n\treturn _SUCCESS;\n}\n\nstatic inline void hal_init_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tu8 path, group, tx_idx;\n\n\tif (pwr_info == NULL)\n\t\treturn;\n\n\t_rtw_memset(pwr_info, 0, sizeof(TxPowerInfo24G));\n\n\t/* init with invalid value */\n\tfor (path = 0; path < MAX_RF_PATH; path++) {\n\t\tfor (group = 0; group < MAX_CHNL_GROUP_24G; group++) {\n\t\t\tpwr_info->IndexCCK_Base[path][group] = PG_TXPWR_INVALID_BASE;\n\t\t\tpwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE;\n\t\t}\n\t\tfor (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {\n\t\t\tpwr_info->CCK_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;\n\t\t\tpwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;\n\t\t\tpwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;\n\t\t\tpwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;\n\t\t}\n\t}\n\n\t/* init for dummy base and diff */\n\tfor (path = 0; path < MAX_RF_PATH; path++) {\n\t\tif (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path))\n\t\t\tbreak;\n\t\t/* 2.4G BW40 base has 1 less group than CCK base*/\n\t\tpwr_info->IndexBW40_Base[path][MAX_CHNL_GROUP_24G - 1] = 0;\n\n\t\t/* dummy diff */\n\t\tpwr_info->CCK_Diff[path][0] = 0; /* 2.4G CCK-1TX */\n\t\tpwr_info->BW40_Diff[path][0] = 0; /* 2.4G BW40-1S */\n\t}\n}\n\nstatic inline void hal_init_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info)\n{\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tu8 path, group, tx_idx;\n\n\tif (pwr_info == NULL)\n\t\treturn;\n\n\t_rtw_memset(pwr_info, 0, sizeof(TxPowerInfo5G));\n\n\t/* init with invalid value */\n\tfor (path = 0; path < MAX_RF_PATH; path++) {\n\t\tfor (group = 0; group < MAX_CHNL_GROUP_5G; group++)\n\t\t\tpwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE;\n\t\tfor (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {\n\t\t\tpwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;\n\t\t\tpwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;\n\t\t\tpwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;\n\t\t\tpwr_info->BW80_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;\n\t\t\tpwr_info->BW160_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;\n\t\t}\n\t}\n\n\tfor (path = 0; path < MAX_RF_PATH; path++) {\n\t\tif (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))\n\t\t\tbreak;\n\t\t/* dummy diff */\n\t\tpwr_info->BW40_Diff[path][0] = 0; /* 5G BW40-1S */\n\t}\n#endif /* CONFIG_IEEE80211_BAND_5GHZ */\n}\n\n#if DBG_PG_TXPWR_READ\n#define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) 1\n#else\n#define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) (_txpwr_src > PG_TXPWR_SRC_PG_DATA)\n#endif\n\nu16 hal_load_pg_txpwr_info_path_2g(\n\t_adapter *adapter,\n\tTxPowerInfo24G\t*pwr_info,\n\tu32 path,\n\tu8 txpwr_src,\n\tconst struct map_t *txpwr_map,\n\tu16 pg_offset)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tu16 offset = pg_offset;\n\tu8 group, tx_idx;\n\tu8 val;\n\tu8 tmp_base;\n\ts8 tmp_diff;\n\n\tif (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G)) {\n\t\toffset += PG_TXPWR_1PATH_BYTE_NUM_2G;\n\t\tgoto exit;\n\t}\n\n\tif (DBG_PG_TXPWR_READ)\n\t\tRTW_INFO(\"%s [%c] offset:0x%03x\\n\", __func__, rf_path_char(path), offset);\n\n\tfor (group = 0; group < MAX_CHNL_GROUP_24G; group++) {\n\t\tif (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {\n\t\t\ttmp_base = map_read8(txpwr_map, offset);\n\t\t\tif (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)\n\t\t\t\t&& IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexCCK_Base[path][group])\n\t\t\t) {\n\t\t\t\tpwr_info->IndexCCK_Base[path][group] = tmp_base;\n\t\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\t\tRTW_INFO(\"[%c] 2G G%02d CCK-1T base:%u from %s\\n\", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));\n\t\t\t}\n\t\t}\n\t\toffset++;\n\t}\n\n\tfor (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {\n\t\tif (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {\n\t\t\ttmp_base = map_read8(txpwr_map, offset);\n\t\t\tif (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)\n\t\t\t\t&& IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group])\n\t\t\t) {\n\t\t\t\tpwr_info->IndexBW40_Base[path][group] =\ttmp_base;\n\t\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\t\tRTW_INFO(\"[%c] 2G G%02d BW40-1S base:%u from %s\\n\", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));\n\t\t\t}\n\t\t}\n\t\toffset++;\n\t}\n\n\tfor (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {\n\t\tif (tx_idx == 0) {\n\t\t\tif (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {\n\t\t\t\tval = map_read8(txpwr_map, offset);\n\t\t\t\ttmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);\n\t\t\t\tif (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)\n\t\t\t\t\t&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])\n\t\t\t\t) {\n\t\t\t\t\tpwr_info->BW20_Diff[path][tx_idx] = tmp_diff;\n\t\t\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\t\t\tRTW_INFO(\"[%c] 2G BW20-%dS diff:%d from %s\\n\", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));\n\t\t\t\t}\n\t\t\t\ttmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);\n\t\t\t\tif (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)\n\t\t\t\t\t&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])\n\t\t\t\t) {\n\t\t\t\t\tpwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;\n\t\t\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\t\t\tRTW_INFO(\"[%c] 2G OFDM-%dT diff:%d from %s\\n\", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));\n\t\t\t\t}\n\t\t\t}\n\t\t\toffset++;\n\t\t} else {\n\t\t\tif (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {\n\t\t\t\tval = map_read8(txpwr_map, offset);\n\t\t\t\ttmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);\n\t\t\t\tif (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)\n\t\t\t\t\t&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])\n\t\t\t\t) {\n\t\t\t\t\tpwr_info->BW40_Diff[path][tx_idx] = tmp_diff;\n\t\t\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\t\t\tRTW_INFO(\"[%c] 2G BW40-%dS diff:%d from %s\\n\", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));\n\n\t\t\t\t}\n\t\t\t\ttmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);\n\t\t\t\tif (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)\n\t\t\t\t\t&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])\n\t\t\t\t) {\n\t\t\t\t\tpwr_info->BW20_Diff[path][tx_idx] = tmp_diff;\n\t\t\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\t\t\tRTW_INFO(\"[%c] 2G BW20-%dS diff:%d from %s\\n\", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));\n\t\t\t\t}\n\t\t\t}\n\t\t\toffset++;\n\n\t\t\tif (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {\n\t\t\t\tval = map_read8(txpwr_map, offset);\n\t\t\t\ttmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);\n\t\t\t\tif (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)\n\t\t\t\t\t&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])\n\t\t\t\t) {\n\t\t\t\t\tpwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;\n\t\t\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\t\t\tRTW_INFO(\"[%c] 2G OFDM-%dT diff:%d from %s\\n\", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));\n\t\t\t\t}\n\t\t\t\ttmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);\n\t\t\t\tif (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)\n\t\t\t\t\t&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx])\n\t\t\t\t) {\n\t\t\t\t\tpwr_info->CCK_Diff[path][tx_idx] =\ttmp_diff;\n\t\t\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\t\t\tRTW_INFO(\"[%c] 2G CCK-%dT diff:%d from %s\\n\", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));\n\t\t\t\t}\n\t\t\t}\n\t\t\toffset++;\n\t\t}\n\t}\n\n\tif (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_2G) {\n\t\tRTW_ERR(\"%s parse %d bytes != %d\\n\", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_2G);\n\t\trtw_warn_on(1);\n\t}\n\nexit:\n\treturn offset;\n}\n\nu16 hal_load_pg_txpwr_info_path_5g(\n\t_adapter *adapter,\n\tTxPowerInfo5G\t*pwr_info,\n\tu32 path,\n\tu8 txpwr_src,\n\tconst struct map_t *txpwr_map,\n\tu16 pg_offset)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tu16 offset = pg_offset;\n\tu8 group, tx_idx;\n\tu8 val;\n\tu8 tmp_base;\n\ts8 tmp_diff;\n\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\tif (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G))\n#endif\n\t{\n\t\toffset += PG_TXPWR_1PATH_BYTE_NUM_5G;\n\t\tgoto exit;\n\t}\n\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\tif (DBG_PG_TXPWR_READ)\n\t\tRTW_INFO(\"%s[%c] eaddr:0x%03x\\n\", __func__, rf_path_char(path), offset);\n\n\tfor (group = 0; group < MAX_CHNL_GROUP_5G; group++) {\n\t\tif (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) {\n\t\t\ttmp_base = map_read8(txpwr_map, offset);\n\t\t\tif (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)\n\t\t\t\t&& IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group])\n\t\t\t) {\n\t\t\t\tpwr_info->IndexBW40_Base[path][group] = tmp_base;\n\t\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\t\tRTW_INFO(\"[%c] 5G G%02d BW40-1S base:%u from %s\\n\", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));\n\t\t\t}\n\t\t}\n\t\toffset++;\n\t}\n\n\tfor (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {\n\t\tif (tx_idx == 0) {\n\t\t\tif (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {\n\t\t\t\tval = map_read8(txpwr_map, offset);\n\t\t\t\ttmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);\n\t\t\t\tif (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)\n\t\t\t\t\t&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])\n\t\t\t\t) {\n\t\t\t\t\tpwr_info->BW20_Diff[path][tx_idx] = tmp_diff;\n\t\t\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\t\t\tRTW_INFO(\"[%c] 5G BW20-%dS diff:%d from %s\\n\", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));\n\t\t\t\t}\n\t\t\t\ttmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);\n\t\t\t\tif (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)\n\t\t\t\t\t&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])\n\t\t\t\t) {\n\t\t\t\t\tpwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;\n\t\t\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\t\t\tRTW_INFO(\"[%c] 5G OFDM-%dT diff:%d from %s\\n\", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));\n\t\t\t\t}\n\t\t\t}\n\t\t\toffset++;\n\t\t} else {\n\t\t\tif (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {\n\t\t\t\tval = map_read8(txpwr_map, offset);\n\t\t\t\ttmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);\n\t\t\t\tif (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)\n\t\t\t\t\t&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])\n\t\t\t\t) {\n\t\t\t\t\tpwr_info->BW40_Diff[path][tx_idx] = tmp_diff;\n\t\t\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\t\t\tRTW_INFO(\"[%c] 5G BW40-%dS diff:%d from %s\\n\", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));\n\t\t\t\t}\n\t\t\t\ttmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);\n\t\t\t\tif (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)\n\t\t\t\t\t&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])\n\t\t\t\t) {\n\t\t\t\t\tpwr_info->BW20_Diff[path][tx_idx] = tmp_diff;\n\t\t\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\t\t\tRTW_INFO(\"[%c] 5G BW20-%dS diff:%d from %s\\n\", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));\n\t\t\t\t}\n\t\t\t}\n\t\t\toffset++;\n\t\t}\n\t}\n\n\t/* OFDM diff 2T ~ 3T */\n\tif (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, 1)) {\n\t\tval = map_read8(txpwr_map, offset);\n\t\ttmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);\n\t\tif (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)\n\t\t\t&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][1])\n\t\t) {\n\t\t\tpwr_info->OFDM_Diff[path][1] = tmp_diff;\n\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\tRTW_INFO(\"[%c] 5G OFDM-%dT diff:%d from %s\\n\", rf_path_char(path), 2, tmp_diff, pg_txpwr_src_str(txpwr_src));\n\t\t}\n\t\tif (HAL_SPEC_CHK_TX_CNT(hal_spec, 2)) {\n\t\t\ttmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);\n\t\t\tif (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)\n\t\t\t\t&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][2])\n\t\t\t) {\n\t\t\t\tpwr_info->OFDM_Diff[path][2] = tmp_diff;\n\t\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\t\tRTW_INFO(\"[%c] 5G OFDM-%dT diff:%d from %s\\n\", rf_path_char(path), 3, tmp_diff, pg_txpwr_src_str(txpwr_src));\n\t\t\t}\n\t\t}\n\t}\n\toffset++;\n\n\t/* OFDM diff 4T */\n\tif (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, 3)) {\n\t\tval = map_read8(txpwr_map, offset);\n\t\ttmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);\n\t\tif (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)\n\t\t\t&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][3])\n\t\t) {\n\t\t\tpwr_info->OFDM_Diff[path][3] = tmp_diff;\n\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\tRTW_INFO(\"[%c] 5G OFDM-%dT diff:%d from %s\\n\", rf_path_char(path), 4, tmp_diff, pg_txpwr_src_str(txpwr_src));\n\t\t}\n\t}\n\toffset++;\n\n\tfor (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {\n\t\tif (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {\n\t\t\tval = map_read8(txpwr_map, offset);\n\t\t\ttmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);\n\t\t\tif (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)\n\t\t\t\t&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx])\n\t\t\t) {\n\t\t\t\tpwr_info->BW80_Diff[path][tx_idx] = tmp_diff;\n\t\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\t\tRTW_INFO(\"[%c] 5G BW80-%dS diff:%d from %s\\n\", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));\n\t\t\t}\n\t\t\ttmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);\n\t\t\tif (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)\n\t\t\t\t&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx])\n\t\t\t) {\n\t\t\t\tpwr_info->BW160_Diff[path][tx_idx] = tmp_diff;\n\t\t\t\tif (LOAD_PG_TXPWR_WARN_COND(txpwr_src))\n\t\t\t\t\tRTW_INFO(\"[%c] 5G BW160-%dS diff:%d from %s\\n\", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));\n\t\t\t}\n\t\t}\n\t\toffset++;\n\t}\n\n\tif (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_5G) {\n\t\tRTW_ERR(\"%s parse %d bytes != %d\\n\", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_5G);\n\t\trtw_warn_on(1);\n\t}\n\n#endif /* #ifdef CONFIG_IEEE80211_BAND_5GHZ */\n\nexit:\n\treturn offset;\n}\n\nvoid hal_load_pg_txpwr_info(\n\t_adapter *adapter,\n\tTxPowerInfo24G *pwr_info_2g,\n\tTxPowerInfo5G *pwr_info_5g,\n\tu8 *pg_data,\n\tBOOLEAN AutoLoadFail\n)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tu8 path;\n\tu16 pg_offset;\n\tu8 txpwr_src = PG_TXPWR_SRC_PG_DATA;\n\tstruct map_t pg_data_map = MAP_ENT(184, 1, 0xFF, MAPSEG_PTR_ENT(0x00, 184, pg_data));\n\tconst struct map_t *txpwr_map = NULL;\n\n\t/* init with invalid value and some dummy base and diff */\n\thal_init_pg_txpwr_info_2g(adapter, pwr_info_2g);\n\thal_init_pg_txpwr_info_5g(adapter, pwr_info_5g);\n\nselect_src:\n\tpg_offset = hal_spec->pg_txpwr_saddr;\n\n\tswitch (txpwr_src) {\n\tcase PG_TXPWR_SRC_PG_DATA:\n\t\ttxpwr_map = &pg_data_map;\n\t\tbreak;\n\tcase PG_TXPWR_SRC_IC_DEF:\n\t\ttxpwr_map = hal_pg_txpwr_def_info(adapter);\n\t\tbreak;\n\tcase PG_TXPWR_SRC_DEF:\n\tdefault:\n\t\ttxpwr_map = &pg_txpwr_def_info;\n\t\tbreak;\n\t};\n\n\tif (txpwr_map == NULL)\n\t\tgoto end_parse;\n\n\tfor (path = 0; path < MAX_RF_PATH ; path++) {\n\t\tif (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))\n\t\t\tbreak;\n\t\tpg_offset = hal_load_pg_txpwr_info_path_2g(adapter, pwr_info_2g, path, txpwr_src, txpwr_map, pg_offset);\n\t\tpg_offset = hal_load_pg_txpwr_info_path_5g(adapter, pwr_info_5g, path, txpwr_src, txpwr_map, pg_offset);\n\t}\n\n\tif (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) == _SUCCESS\n\t\t&& hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) == _SUCCESS)\n\t\tgoto exit;\n\nend_parse:\n\ttxpwr_src++;\n\tif (txpwr_src < PG_TXPWR_SRC_NUM)\n\t\tgoto select_src;\n\n\tif (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) != _SUCCESS\n\t\t|| hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) != _SUCCESS)\n\t\trtw_warn_on(1);\n\nexit:\n\t#if DBG_PG_TXPWR_READ\n\tif (pwr_info_2g)\n\t\tdump_pg_txpwr_info_2g(RTW_DBGDUMP, pwr_info_2g, 4, 4);\n\tif (pwr_info_5g)\n\t\tdump_pg_txpwr_info_5g(RTW_DBGDUMP, pwr_info_5g, 4, 4);\n\t#endif\n\n\treturn;\n}\n\n#ifdef CONFIG_EFUSE_CONFIG_FILE\n\n#define EFUSE_POWER_INDEX_INVALID 0xFF\n\nstatic u8 _check_phy_efuse_tx_power_info_valid(u8 *pg_data, int base_len, u16 pg_offset)\n{\n\tint ff_cnt = 0;\n\tint i;\n\n\tfor (i = 0; i < base_len; i++) {\n\t\tif (*(pg_data + pg_offset + i) == 0xFF)\n\t\t\tff_cnt++;\n\t}\n\n\tif (ff_cnt == 0)\n\t\treturn _TRUE;\n\telse if (ff_cnt == base_len)\n\t\treturn _FALSE;\n\telse\n\t\treturn EFUSE_POWER_INDEX_INVALID;\n}\n\nint check_phy_efuse_tx_power_info_valid(_adapter *adapter)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tu8 *pg_data = hal_data->efuse_eeprom_data;\n\tu16 pg_offset = hal_spec->pg_txpwr_saddr;\n\tu8 path;\n\tu8 valid_2g_path_bmp = 0;\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\tu8 valid_5g_path_bmp = 0;\n#endif\n\tint result = _FALSE;\n\n\tfor (path = 0; path < MAX_RF_PATH; path++) {\n\t\tu8 ret = _FALSE;\n\n\t\tif (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))\n\t\t\tbreak;\n\n\t\tif (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {\n\t\t\tret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_2G, pg_offset);\n\t\t\tif (ret == _TRUE)\n\t\t\t\tvalid_2g_path_bmp |= BIT(path);\n\t\t\telse if (ret == EFUSE_POWER_INDEX_INVALID)\n\t\t\t\treturn _FALSE;\n\t\t}\n\t\tpg_offset += PG_TXPWR_1PATH_BYTE_NUM_2G;\n\n\t\t#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\t\tif (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) {\n\t\t\tret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_5G, pg_offset);\n\t\t\tif (ret == _TRUE)\n\t\t\t\tvalid_5g_path_bmp |= BIT(path);\n\t\t\telse if (ret == EFUSE_POWER_INDEX_INVALID)\n\t\t\t\treturn _FALSE;\n\t\t}\n\t\t#endif\n\t\tpg_offset += PG_TXPWR_1PATH_BYTE_NUM_5G;\n\t}\n\n\tif ((hal_chk_band_cap(adapter, BAND_CAP_2G) && valid_2g_path_bmp)\n\t\t#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\t\t|| (hal_chk_band_cap(adapter, BAND_CAP_5G) && valid_5g_path_bmp)\n\t\t#endif\n\t)\n\t\treturn _TRUE;\n\n\treturn _FALSE;\n}\n#endif /* CONFIG_EFUSE_CONFIG_FILE */\n\nvoid hal_load_txpwr_info(\n\t_adapter *adapter,\n\tTxPowerInfo24G *pwr_info_2g,\n\tTxPowerInfo5G *pwr_info_5g,\n\tu8 *pg_data\n)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tu8 max_tx_cnt = hal_spec->max_tx_cnt;\n\tu8 rfpath, ch_idx, group, tx_idx;\n\n\t/* load from pg data (or default value) */\n\thal_load_pg_txpwr_info(adapter, pwr_info_2g, pwr_info_5g, pg_data, _FALSE);\n\n\t/* transform to hal_data */\n\tfor (rfpath = 0; rfpath < MAX_RF_PATH; rfpath++) {\n\n\t\tif (!pwr_info_2g || !HAL_SPEC_CHK_RF_PATH_2G(hal_spec, rfpath))\n\t\t\tgoto bypass_2g;\n\n\t\t/* 2.4G base */\n\t\tfor (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++) {\n\t\t\tu8 cck_group;\n\n\t\t\tif (rtw_get_ch_group(ch_idx + 1, &group, &cck_group) != BAND_ON_2_4G)\n\t\t\t\tcontinue;\n\n\t\t\thal_data->Index24G_CCK_Base[rfpath][ch_idx] = pwr_info_2g->IndexCCK_Base[rfpath][cck_group];\n\t\t\thal_data->Index24G_BW40_Base[rfpath][ch_idx] = pwr_info_2g->IndexBW40_Base[rfpath][group];\n\t\t}\n\n\t\t/* 2.4G diff */\n\t\tfor (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {\n\t\t\tif (tx_idx >= max_tx_cnt)\n\t\t\t\tbreak;\n\n\t\t\thal_data->CCK_24G_Diff[rfpath][tx_idx] = pwr_info_2g->CCK_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;\n\t\t\thal_data->OFDM_24G_Diff[rfpath][tx_idx] = pwr_info_2g->OFDM_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;\n\t\t\thal_data->BW20_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW20_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;\n\t\t\thal_data->BW40_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW40_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;\n\t\t}\nbypass_2g:\n\t\t;\n\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\t\tif (!pwr_info_5g || !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, rfpath))\n\t\t\tgoto bypass_5g;\n\n\t\t/* 5G base */\n\t\tfor (ch_idx = 0; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {\n\t\t\tif (rtw_get_ch_group(center_ch_5g_all[ch_idx], &group, NULL) != BAND_ON_5G)\n\t\t\t\tcontinue;\n\t\t\thal_data->Index5G_BW40_Base[rfpath][ch_idx] = pwr_info_5g->IndexBW40_Base[rfpath][group];\n\t\t}\n\n\t\tfor (ch_idx = 0 ; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++) {\n\t\t\tu8 upper, lower;\n\n\t\t\tif (rtw_get_ch_group(center_ch_5g_80m[ch_idx], &group, NULL) != BAND_ON_5G)\n\t\t\t\tcontinue;\n\n\t\t\tupper = pwr_info_5g->IndexBW40_Base[rfpath][group];\n\t\t\tlower = pwr_info_5g->IndexBW40_Base[rfpath][group + 1];\n\t\t\thal_data->Index5G_BW80_Base[rfpath][ch_idx] = (upper + lower) / 2;\n\t\t}\n\n\t\t/* 5G diff */\n\t\tfor (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {\n\t\t\tif (tx_idx >= max_tx_cnt)\n\t\t\t\tbreak;\n\n\t\t\thal_data->OFDM_5G_Diff[rfpath][tx_idx] = pwr_info_5g->OFDM_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;\n\t\t\thal_data->BW20_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW20_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;\n\t\t\thal_data->BW40_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW40_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;\n\t\t\thal_data->BW80_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW80_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;\n\t\t}\nbypass_5g:\n\t\t;\n#endif /* CONFIG_IEEE80211_BAND_5GHZ */\n\t}\n}\n\nvoid dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tint path, ch_idx, tx_idx;\n\n\tRTW_PRINT_SEL(sel, \"2.4G\\n\");\n\tRTW_PRINT_SEL(sel, \"CCK-1T base:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)\n\t\t_RTW_PRINT_SEL(sel, \"%3d \", center_ch_2g[ch_idx]);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%3u \", hal_data->Index24G_CCK_Base[path][ch_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"CCK diff:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t_RTW_PRINT_SEL(sel, \"%dT \", tx_idx + 1);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%2d \", hal_data->CCK_24G_Diff[path][tx_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"BW40-1S base:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)\n\t\t_RTW_PRINT_SEL(sel, \"%3d \", center_ch_2g[ch_idx]);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%3u \", hal_data->Index24G_BW40_Base[path][ch_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"OFDM diff:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t_RTW_PRINT_SEL(sel, \"%dT \", tx_idx + 1);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%2d \", hal_data->OFDM_24G_Diff[path][tx_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"BW20 diff:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t_RTW_PRINT_SEL(sel, \"%dS \", tx_idx + 1);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%2d \", hal_data->BW20_24G_Diff[path][tx_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"BW40 diff:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t_RTW_PRINT_SEL(sel, \"%dS \", tx_idx + 1);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%2d \", hal_data->BW40_24G_Diff[path][tx_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n}\n\nvoid dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt)\n{\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tint path, ch_idx, tx_idx;\n\tu8 dump_section = 0;\n\tu8 ch_idx_s = 0;\n\n\tRTW_PRINT_SEL(sel, \"5G\\n\");\n\tRTW_PRINT_SEL(sel, \"BW40-1S base:\\n\");\n\tdo {\n\t\t#define DUMP_5G_BW40_BASE_SECTION_NUM 3\n\t\tu8 end[DUMP_5G_BW40_BASE_SECTION_NUM] = {64, 144, 177};\n\n\t\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\t\tfor (ch_idx = ch_idx_s; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {\n\t\t\t_RTW_PRINT_SEL(sel, \"%3d \", center_ch_5g_all[ch_idx]);\n\t\t\tif (end[dump_section] == center_ch_5g_all[ch_idx])\n\t\t\t\tbreak;\n\t\t}\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\t\tfor (ch_idx = ch_idx_s; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {\n\t\t\t\t_RTW_PRINT_SEL(sel, \"%3u \", hal_data->Index5G_BW40_Base[path][ch_idx]);\n\t\t\t\tif (end[dump_section] == center_ch_5g_all[ch_idx])\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t\t}\n\t\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\t\tch_idx_s = ch_idx + 1;\n\t\tdump_section++;\n\t\tif (dump_section >= DUMP_5G_BW40_BASE_SECTION_NUM)\n\t\t\tbreak;\n\t} while (1);\n\n\tRTW_PRINT_SEL(sel, \"BW80-1S base:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (ch_idx = 0; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++)\n\t\t_RTW_PRINT_SEL(sel, \"%3d \", center_ch_5g_80m[ch_idx]);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (ch_idx = 0; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%3u \", hal_data->Index5G_BW80_Base[path][ch_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"OFDM diff:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t_RTW_PRINT_SEL(sel, \"%dT \", tx_idx + 1);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%2d \", hal_data->OFDM_5G_Diff[path][tx_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"BW20 diff:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t_RTW_PRINT_SEL(sel, \"%dS \", tx_idx + 1);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%2d \", hal_data->BW20_5G_Diff[path][tx_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"BW40 diff:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t_RTW_PRINT_SEL(sel, \"%dS \", tx_idx + 1);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%2d \", hal_data->BW40_5G_Diff[path][tx_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\tRTW_PRINT_SEL(sel, \"BW80 diff:\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s \", \"\");\n\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t_RTW_PRINT_SEL(sel, \"%dS \", tx_idx + 1);\n\t_RTW_PRINT_SEL(sel, \"\\n\");\n\tfor (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {\n\t\tRTW_PRINT_SEL(sel, \"[%c]: \", rf_path_char(path));\n\t\tfor (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)\n\t\t\t_RTW_PRINT_SEL(sel, \"%2d \", hal_data->BW80_5G_Diff[path][tx_idx]);\n\t\t_RTW_PRINT_SEL(sel, \"\\n\");\n\t}\n\tRTW_PRINT_SEL(sel, \"\\n\");\n#endif /* CONFIG_IEEE80211_BAND_5GHZ */\n}\n\n/*\n* rtw_regsty_get_target_tx_power -\n*\n* Return dBm or -1 for undefined\n*/\ns8 rtw_regsty_get_target_tx_power(\n\t\tPADAPTER\t\tAdapter,\n\t\tu8\t\t\t\tBand,\n\t\tu8\t\t\t\tRfPath,\n\t\tRATE_SECTION\tRateSection\n)\n{\n\tstruct registry_priv *regsty = adapter_to_regsty(Adapter);\n\ts8 value = 0;\n\n\tif (RfPath > RF_PATH_D) {\n\t\tRTW_PRINT(\"%s invalid RfPath:%d\\n\", __func__, RfPath);\n\t\treturn -1;\n\t}\n\n\tif (Band != BAND_ON_2_4G\n\t\t#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\t\t&& Band != BAND_ON_5G\n\t\t#endif\n\t) {\n\t\tRTW_PRINT(\"%s invalid Band:%d\\n\", __func__, Band);\n\t\treturn -1;\n\t}\n\n\tif (RateSection >= RATE_SECTION_NUM\n\t\t#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\t\t|| (Band == BAND_ON_5G && RateSection == CCK)\n\t\t#endif\n\t) {\n\t\tRTW_PRINT(\"%s invalid RateSection:%d in Band:%d, RfPath:%d\\n\", __func__\n\t\t\t, RateSection, Band, RfPath);\n\t\treturn -1;\n\t}\n\n\tif (Band == BAND_ON_2_4G)\n\t\tvalue = regsty->target_tx_pwr_2g[RfPath][RateSection];\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\telse /* BAND_ON_5G */\n\t\tvalue = regsty->target_tx_pwr_5g[RfPath][RateSection - 1];\n#endif\n\n\treturn value;\n}\n\nbool rtw_regsty_chk_target_tx_power_valid(_adapter *adapter)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tint path, tx_num, band, rs;\n\ts8 target;\n\n\tfor (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {\n\t\tif (!hal_is_band_support(adapter, band))\n\t\t\tcontinue;\n\n\t\tfor (path = 0; path < RF_PATH_MAX; path++) {\n\t\t\tif (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))\n\t\t\t\tbreak;\n\n\t\t\tfor (rs = 0; rs < RATE_SECTION_NUM; rs++) {\n\t\t\t\ttx_num = rate_section_to_tx_num(rs);\n\t\t\t\tif (tx_num >= hal_spec->tx_nss_num)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))\n\t\t\t\t\tcontinue;\n\n\t\t\t\ttarget = rtw_regsty_get_target_tx_power(adapter, band, path, rs);\n\t\t\t\tif (target == -1) {\n\t\t\t\t\tRTW_PRINT(\"%s return _FALSE for band:%d, path:%d, rs:%d, t:%d\\n\", __func__, band, path, rs, target);\n\t\t\t\t\treturn _FALSE;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\treturn _TRUE;\n}\n\n/*\n* PHY_GetTxPowerByRateBase -\n*\n* Return value in unit of TX Gain Index\n*/\nu8\nPHY_GetTxPowerByRateBase(\n\t\tPADAPTER\t\tAdapter,\n\t\tu8\t\t\t\tBand,\n\t\tu8\t\t\t\tRfPath,\n\t\tRATE_SECTION\tRateSection\n)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\n\tu8 value = 0;\n\n\tif (RfPath > RF_PATH_D) {\n\t\tRTW_PRINT(\"%s invalid RfPath:%d\\n\", __func__, RfPath);\n\t\treturn 0;\n\t}\n\n\tif (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {\n\t\tRTW_PRINT(\"%s invalid Band:%d\\n\", __func__, Band);\n\t\treturn 0;\n\t}\n\n\tif (RateSection >= RATE_SECTION_NUM\n\t\t|| (Band == BAND_ON_5G && RateSection == CCK)\n\t) {\n\t\tRTW_PRINT(\"%s invalid RateSection:%d in Band:%d, RfPath:%d\\n\", __func__\n\t\t\t, RateSection, Band, RfPath);\n\t\treturn 0;\n\t}\n\n\tif (Band == BAND_ON_2_4G)\n\t\tvalue = pHalData->TxPwrByRateBase2_4G[RfPath][RateSection];\n\telse /* BAND_ON_5G */\n\t\tvalue = pHalData->TxPwrByRateBase5G[RfPath][RateSection - 1];\n\n\treturn value;\n}\n\nvoid\nphy_SetTxPowerByRateBase(\n\t\tPADAPTER\t\tAdapter,\n\t\tu8\t\t\t\tBand,\n\t\tu8\t\t\t\tRfPath,\n\t\tRATE_SECTION\tRateSection,\n\t\tu8\t\t\t\tValue\n)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\n\n\tif (RfPath > RF_PATH_D) {\n\t\tRTW_PRINT(\"%s invalid RfPath:%d\\n\", __func__, RfPath);\n\t\treturn;\n\t}\n\n\tif (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {\n\t\tRTW_PRINT(\"%s invalid Band:%d\\n\", __func__, Band);\n\t\treturn;\n\t}\n\n\tif (RateSection >= RATE_SECTION_NUM\n\t\t|| (Band == BAND_ON_5G && RateSection == CCK)\n\t) {\n\t\tRTW_PRINT(\"%s invalid RateSection:%d in %sG, RfPath:%d\\n\", __func__\n\t\t\t, RateSection, (Band == BAND_ON_2_4G) ? \"2.4\" : \"5\", RfPath);\n\t\treturn;\n\t}\n\n\tif (Band == BAND_ON_2_4G)\n\t\tpHalData->TxPwrByRateBase2_4G[RfPath][RateSection] = Value;\n\telse /* BAND_ON_5G */\n\t\tpHalData->TxPwrByRateBase5G[RfPath][RateSection - 1] = Value;\n}\n\nstatic inline BOOLEAN phy_is_txpwr_by_rate_undefined_of_band_path(_adapter *adapter, u8 band, u8 path)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tu8 rate_idx = 0;\n\n\tfor (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++) {\n\t\tif (hal_data->TxPwrByRateOffset[band][path][rate_idx] != 0)\n\t\t\tgoto exit;\n\t}\n\nexit:\n\treturn rate_idx >= TX_PWR_BY_RATE_NUM_RATE ? _TRUE : _FALSE;\n}\n\nstatic inline void phy_txpwr_by_rate_duplicate_band_path(_adapter *adapter, u8 band, u8 s_path, u8 t_path)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tu8 rate_idx = 0;\n\n\tfor (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++)\n\t\thal_data->TxPwrByRateOffset[band][t_path][rate_idx] = hal_data->TxPwrByRateOffset[band][s_path][rate_idx];\n}\n\nstatic void phy_txpwr_by_rate_chk_for_path_dup(_adapter *adapter)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tu8 band, path;\n\ts8 src_path;\n\n\tfor (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++)\n\t\tfor (path = RF_PATH_A; path < RF_PATH_MAX; path++)\n\t\t\thal_data->txpwr_by_rate_undefined_band_path[band][path] = 0;\n\n\tfor (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {\n\t\tif (!hal_is_band_support(adapter, band))\n\t\t\tcontinue;\n\n\t\tfor (path = RF_PATH_A; path < RF_PATH_MAX; path++) {\n\t\t\tif (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))\n\t\t\t\tcontinue;\n\n\t\t\tif (phy_is_txpwr_by_rate_undefined_of_band_path(adapter, band, path))\n\t\t\t\thal_data->txpwr_by_rate_undefined_band_path[band][path] = 1;\n\t\t}\n\t}\n\n\tfor (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {\n\t\tif (!hal_is_band_support(adapter, band))\n\t\t\tcontinue;\n\n\t\tsrc_path = -1;\n\t\tfor (path = RF_PATH_A; path < RF_PATH_MAX; path++) {\n\t\t\tif (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))\n\t\t\t\tcontinue;\n\n\t\t\t/* find src */\n\t\t\tif (src_path == -1 && hal_data->txpwr_by_rate_undefined_band_path[band][path] == 0)\n\t\t\t\tsrc_path = path;\n\t\t}\n\n\t\tif (src_path == -1) {\n\t\t\tRTW_ERR(\"%s all power by rate undefined\\n\", __func__);\n\t\t\tcontinue;\n\t\t}\n\n\t\tfor (path = RF_PATH_A; path < RF_PATH_MAX; path++) {\n\t\t\tif (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))\n\t\t\t\tcontinue;\n\n\t\t\t/* duplicate src to undefined one */\n\t\t\tif (hal_data->txpwr_by_rate_undefined_band_path[band][path] == 1) {\n\t\t\t\tRTW_INFO(\"%s duplicate %s [%c] to [%c]\\n\", __func__\n\t\t\t\t\t, band_str(band), rf_path_char(src_path), rf_path_char(path));\n\t\t\t\tphy_txpwr_by_rate_duplicate_band_path(adapter, band, src_path, path);\n\t\t\t}\n\t\t}\n\t}\n}\n\nvoid\nphy_StoreTxPowerByRateBase(\n\t\tPADAPTER\tpAdapter\n)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);\n\tstruct registry_priv *regsty = adapter_to_regsty(pAdapter);\n\n\tu8 rate_sec_base[RATE_SECTION_NUM] = {\n\t\tMGN_11M,\n\t\tMGN_54M,\n\t\tMGN_MCS7,\n\t\tMGN_MCS15,\n\t\tMGN_MCS23,\n\t\tMGN_MCS31,\n\t\tMGN_VHT1SS_MCS7,\n\t\tMGN_VHT2SS_MCS7,\n\t\tMGN_VHT3SS_MCS7,\n\t\tMGN_VHT4SS_MCS7,\n\t};\n\n\tu8 band, path, rs, tx_num, base, index;\n\n\tfor (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {\n\t\tif (!hal_is_band_support(pAdapter, band))\n\t\t\tcontinue;\n\n\t\tfor (path = RF_PATH_A; path < RF_PATH_MAX; path++) {\n\t\t\tif (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))\n\t\t\t\tbreak;\n\n\t\t\tfor (rs = 0; rs < RATE_SECTION_NUM; rs++) {\n\t\t\t\ttx_num = rate_section_to_tx_num(rs);\n\t\t\t\tif (tx_num >= hal_spec->tx_nss_num)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (regsty->target_tx_pwr_valid == _TRUE)\n\t\t\t\t\tbase = hal_spec->txgi_pdbm * rtw_regsty_get_target_tx_power(pAdapter, band, path, rs);\n\t\t\t\telse\n\t\t\t\t\tbase = _PHY_GetTxPowerByRate(pAdapter, band, path, rate_sec_base[rs]);\n\t\t\t\tphy_SetTxPowerByRateBase(pAdapter, band, path, rs, base);\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic u8 get_val_from_dhex(u32 dhex, u8 i)\n{\n\treturn (((dhex >> (i * 8 + 4)) & 0xF)) * 10 + ((dhex >> (i * 8)) & 0xF);\n}\n\nstatic u8 get_val_from_hex(u32 hex, u8 i)\n{\n\treturn (hex >> (i * 8)) & 0xFF;\n}\n\nvoid\nPHY_GetRateValuesOfTxPowerByRate(\n\t\tPADAPTER pAdapter,\n\t\tu32 RegAddr,\n\t\tu32 BitMask,\n\t\tu32 Value,\n\t\tu8 *Rate,\n\t\ts8 *PwrByRateVal,\n\t\tu8 *RateNum\n)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);\n\tstruct dm_struct\t\t*pDM_Odm = &pHalData->odmpriv;\n\tu8\t\t\t\tindex = 0, i = 0;\n\tu8 (*get_val)(u32, u8);\n\n\tif (pDM_Odm->phy_reg_pg_version == 1)\n\t\tget_val = get_val_from_dhex;\n\telse\n\t\tget_val = get_val_from_hex;\n\n\tswitch (RegAddr) {\n\tcase rTxAGC_A_Rate18_06:\n\tcase rTxAGC_B_Rate18_06:\n\t\tRate[0] = MGN_6M;\n\t\tRate[1] = MGN_9M;\n\t\tRate[2] = MGN_12M;\n\t\tRate[3] = MGN_18M;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase rTxAGC_A_Rate54_24:\n\tcase rTxAGC_B_Rate54_24:\n\t\tRate[0] = MGN_24M;\n\t\tRate[1] = MGN_36M;\n\t\tRate[2] = MGN_48M;\n\t\tRate[3] = MGN_54M;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase rTxAGC_A_CCK1_Mcs32:\n\t\tRate[0] = MGN_1M;\n\t\tPwrByRateVal[0] = (s8)get_val(Value, 1);\n\t\t*RateNum = 1;\n\t\tbreak;\n\n\tcase rTxAGC_B_CCK11_A_CCK2_11:\n\t\tif (BitMask == 0xffffff00) {\n\t\t\tRate[0] = MGN_2M;\n\t\t\tRate[1] = MGN_5_5M;\n\t\t\tRate[2] = MGN_11M;\n\t\t\tfor (i = 1; i < 4; ++i)\n\t\t\t\tPwrByRateVal[i - 1] = (s8)get_val(Value, i);\n\t\t\t*RateNum = 3;\n\t\t} else if (BitMask == 0x000000ff) {\n\t\t\tRate[0] = MGN_11M;\n\t\t\tPwrByRateVal[0] = (s8)get_val(Value, 0);\n\t\t\t*RateNum = 1;\n\t\t}\n\t\tbreak;\n\n\tcase rTxAGC_A_Mcs03_Mcs00:\n\tcase rTxAGC_B_Mcs03_Mcs00:\n\t\tRate[0] = MGN_MCS0;\n\t\tRate[1] = MGN_MCS1;\n\t\tRate[2] = MGN_MCS2;\n\t\tRate[3] = MGN_MCS3;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase rTxAGC_A_Mcs07_Mcs04:\n\tcase rTxAGC_B_Mcs07_Mcs04:\n\t\tRate[0] = MGN_MCS4;\n\t\tRate[1] = MGN_MCS5;\n\t\tRate[2] = MGN_MCS6;\n\t\tRate[3] = MGN_MCS7;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase rTxAGC_A_Mcs11_Mcs08:\n\tcase rTxAGC_B_Mcs11_Mcs08:\n\t\tRate[0] = MGN_MCS8;\n\t\tRate[1] = MGN_MCS9;\n\t\tRate[2] = MGN_MCS10;\n\t\tRate[3] = MGN_MCS11;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase rTxAGC_A_Mcs15_Mcs12:\n\tcase rTxAGC_B_Mcs15_Mcs12:\n\t\tRate[0] = MGN_MCS12;\n\t\tRate[1] = MGN_MCS13;\n\t\tRate[2] = MGN_MCS14;\n\t\tRate[3] = MGN_MCS15;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase rTxAGC_B_CCK1_55_Mcs32:\n\t\tRate[0] = MGN_1M;\n\t\tRate[1] = MGN_2M;\n\t\tRate[2] = MGN_5_5M;\n\t\tfor (i = 1; i < 4; ++i)\n\t\t\tPwrByRateVal[i - 1] = (s8)get_val(Value, i);\n\t\t*RateNum = 3;\n\t\tbreak;\n\n\tcase 0xC20:\n\tcase 0xE20:\n\tcase 0x1820:\n\tcase 0x1a20:\n\t\tRate[0] = MGN_1M;\n\t\tRate[1] = MGN_2M;\n\t\tRate[2] = MGN_5_5M;\n\t\tRate[3] = MGN_11M;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase 0xC24:\n\tcase 0xE24:\n\tcase 0x1824:\n\tcase 0x1a24:\n\t\tRate[0] = MGN_6M;\n\t\tRate[1] = MGN_9M;\n\t\tRate[2] = MGN_12M;\n\t\tRate[3] = MGN_18M;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase 0xC28:\n\tcase 0xE28:\n\tcase 0x1828:\n\tcase 0x1a28:\n\t\tRate[0] = MGN_24M;\n\t\tRate[1] = MGN_36M;\n\t\tRate[2] = MGN_48M;\n\t\tRate[3] = MGN_54M;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase 0xC2C:\n\tcase 0xE2C:\n\tcase 0x182C:\n\tcase 0x1a2C:\n\t\tRate[0] = MGN_MCS0;\n\t\tRate[1] = MGN_MCS1;\n\t\tRate[2] = MGN_MCS2;\n\t\tRate[3] = MGN_MCS3;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase 0xC30:\n\tcase 0xE30:\n\tcase 0x1830:\n\tcase 0x1a30:\n\t\tRate[0] = MGN_MCS4;\n\t\tRate[1] = MGN_MCS5;\n\t\tRate[2] = MGN_MCS6;\n\t\tRate[3] = MGN_MCS7;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase 0xC34:\n\tcase 0xE34:\n\tcase 0x1834:\n\tcase 0x1a34:\n\t\tRate[0] = MGN_MCS8;\n\t\tRate[1] = MGN_MCS9;\n\t\tRate[2] = MGN_MCS10;\n\t\tRate[3] = MGN_MCS11;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase 0xC38:\n\tcase 0xE38:\n\tcase 0x1838:\n\tcase 0x1a38:\n\t\tRate[0] = MGN_MCS12;\n\t\tRate[1] = MGN_MCS13;\n\t\tRate[2] = MGN_MCS14;\n\t\tRate[3] = MGN_MCS15;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase 0xC3C:\n\tcase 0xE3C:\n\tcase 0x183C:\n\tcase 0x1a3C:\n\t\tRate[0] = MGN_VHT1SS_MCS0;\n\t\tRate[1] = MGN_VHT1SS_MCS1;\n\t\tRate[2] = MGN_VHT1SS_MCS2;\n\t\tRate[3] = MGN_VHT1SS_MCS3;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase 0xC40:\n\tcase 0xE40:\n\tcase 0x1840:\n\tcase 0x1a40:\n\t\tRate[0] = MGN_VHT1SS_MCS4;\n\t\tRate[1] = MGN_VHT1SS_MCS5;\n\t\tRate[2] = MGN_VHT1SS_MCS6;\n\t\tRate[3] = MGN_VHT1SS_MCS7;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase 0xC44:\n\tcase 0xE44:\n\tcase 0x1844:\n\tcase 0x1a44:\n\t\tRate[0] = MGN_VHT1SS_MCS8;\n\t\tRate[1] = MGN_VHT1SS_MCS9;\n\t\tRate[2] = MGN_VHT2SS_MCS0;\n\t\tRate[3] = MGN_VHT2SS_MCS1;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase 0xC48:\n\tcase 0xE48:\n\tcase 0x1848:\n\tcase 0x1a48:\n\t\tRate[0] = MGN_VHT2SS_MCS2;\n\t\tRate[1] = MGN_VHT2SS_MCS3;\n\t\tRate[2] = MGN_VHT2SS_MCS4;\n\t\tRate[3] = MGN_VHT2SS_MCS5;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase 0xC4C:\n\tcase 0xE4C:\n\tcase 0x184C:\n\tcase 0x1a4C:\n\t\tRate[0] = MGN_VHT2SS_MCS6;\n\t\tRate[1] = MGN_VHT2SS_MCS7;\n\t\tRate[2] = MGN_VHT2SS_MCS8;\n\t\tRate[3] = MGN_VHT2SS_MCS9;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase 0xCD8:\n\tcase 0xED8:\n\tcase 0x18D8:\n\tcase 0x1aD8:\n\t\tRate[0] = MGN_MCS16;\n\t\tRate[1] = MGN_MCS17;\n\t\tRate[2] = MGN_MCS18;\n\t\tRate[3] = MGN_MCS19;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase 0xCDC:\n\tcase 0xEDC:\n\tcase 0x18DC:\n\tcase 0x1aDC:\n\t\tRate[0] = MGN_MCS20;\n\t\tRate[1] = MGN_MCS21;\n\t\tRate[2] = MGN_MCS22;\n\t\tRate[3] = MGN_MCS23;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase 0xCE0:\n\tcase 0xEE0:\n\tcase 0x18E0:\n\tcase 0x1aE0:\n\t\tRate[0] = MGN_VHT3SS_MCS0;\n\t\tRate[1] = MGN_VHT3SS_MCS1;\n\t\tRate[2] = MGN_VHT3SS_MCS2;\n\t\tRate[3] = MGN_VHT3SS_MCS3;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase 0xCE4:\n\tcase 0xEE4:\n\tcase 0x18E4:\n\tcase 0x1aE4:\n\t\tRate[0] = MGN_VHT3SS_MCS4;\n\t\tRate[1] = MGN_VHT3SS_MCS5;\n\t\tRate[2] = MGN_VHT3SS_MCS6;\n\t\tRate[3] = MGN_VHT3SS_MCS7;\n\t\tfor (i = 0; i < 4; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 4;\n\t\tbreak;\n\n\tcase 0xCE8:\n\tcase 0xEE8:\n\tcase 0x18E8:\n\tcase 0x1aE8:\n\t\tRate[0] = MGN_VHT3SS_MCS8;\n\t\tRate[1] = MGN_VHT3SS_MCS9;\n\t\tfor (i = 0; i < 2; ++i)\n\t\t\tPwrByRateVal[i] = (s8)get_val(Value, i);\n\t\t*RateNum = 2;\n\t\tbreak;\n\n\tdefault:\n\t\tRTW_PRINT(\"Invalid RegAddr 0x%x in %s()\\n\", RegAddr, __func__);\n\t\tbreak;\n\t};\n}\n\nvoid\nPHY_StoreTxPowerByRateNew(\n\t\tPADAPTER\tpAdapter,\n\t\tu32\t\t\tBand,\n\t\tu32\t\t\tRfPath,\n\t\tu32\t\t\tRegAddr,\n\t\tu32\t\t\tBitMask,\n\t\tu32\t\t\tData\n)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\n\tu8\ti = 0, rates[4] = {0}, rateNum = 0;\n\ts8\tPwrByRateVal[4] = {0};\n\n\tPHY_GetRateValuesOfTxPowerByRate(pAdapter, RegAddr, BitMask, Data, rates, PwrByRateVal, &rateNum);\n\n\tif (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {\n\t\tRTW_PRINT(\"Invalid Band %d\\n\", Band);\n\t\treturn;\n\t}\n\n\tif (RfPath > RF_PATH_D) {\n\t\tRTW_PRINT(\"Invalid RfPath %d\\n\", RfPath);\n\t\treturn;\n\t}\n\n\tfor (i = 0; i < rateNum; ++i) {\n\t\tu8 rate_idx = PHY_GetRateIndexOfTxPowerByRate(rates[i]);\n\n\t\tpHalData->TxPwrByRateOffset[Band][RfPath][rate_idx] = PwrByRateVal[i];\n\t}\n}\n\nvoid\nPHY_InitTxPowerByRate(\n\t\tPADAPTER\tpAdapter\n)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\tu8\tband = 0, rfPath = 0, rate = 0, i = 0, j = 0;\n\n\tfor (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band)\n\t\tfor (rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath)\n\t\t\t\tfor (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate)\n\t\t\t\t\tpHalData->TxPwrByRateOffset[band][rfPath][rate] = 0;\n}\n\nvoid\nphy_store_tx_power_by_rate(\n\t\tPADAPTER\tpAdapter,\n\t\tu32\t\t\tBand,\n\t\tu32\t\t\tRfPath,\n\t\tu32\t\t\tTxNum,\n\t\tu32\t\t\tRegAddr,\n\t\tu32\t\t\tBitMask,\n\t\tu32\t\t\tData\n)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\tstruct dm_struct\t\t*pDM_Odm = &pHalData->odmpriv;\n\n\tif (pDM_Odm->phy_reg_pg_version > 0)\n\t\tPHY_StoreTxPowerByRateNew(pAdapter, Band, RfPath, RegAddr, BitMask, Data);\n\telse\n\t\tRTW_INFO(\"Invalid PHY_REG_PG.txt version %d\\n\",  pDM_Odm->phy_reg_pg_version);\n\n}\n\nvoid\nphy_ConvertTxPowerByRateInDbmToRelativeValues(\n\t\tPADAPTER\tpAdapter\n)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\tu8\t\t\tbase = 0, i = 0, value = 0,\n\t\t\t\tband = 0, path = 0, index = 0,\n\t\t\t\tstartIndex = 0, endIndex = 0;\n\tu8\tcckRates[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M},\n\t\tofdmRates[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M},\n\t\tmcs0_7Rates[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7},\n\t\tmcs8_15Rates[8] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15},\n\t\tmcs16_23Rates[8] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23},\n\t\tvht1ssRates[10] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,\n\t\t\tMGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9},\n\t\tvht2ssRates[10] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,\n\t\t\tMGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9},\n\t\tvht3ssRates[10] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,\n\t\t\tMGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9};\n\n\t/* RTW_INFO(\"===>PHY_ConvertTxPowerByRateInDbmToRelativeValues()\\n\" ); */\n\n\tfor (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) {\n\t\tfor (path = RF_PATH_A; path <= RF_PATH_D; ++path) {\n\t\t\t/* CCK */\n\t\t\tif (band == BAND_ON_2_4G) {\n\t\t\t\tbase = PHY_GetTxPowerByRateBase(pAdapter, band, path, CCK);\n\t\t\t\tfor (i = 0; i < sizeof(cckRates); ++i) {\n\t\t\t\t\tvalue = PHY_GetTxPowerByRate(pAdapter, band, path, cckRates[i]);\n\t\t\t\t\tPHY_SetTxPowerByRate(pAdapter, band, path, cckRates[i], value - base);\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* OFDM */\n\t\t\tbase = PHY_GetTxPowerByRateBase(pAdapter, band, path, OFDM);\n\t\t\tfor (i = 0; i < sizeof(ofdmRates); ++i) {\n\t\t\t\tvalue = PHY_GetTxPowerByRate(pAdapter, band, path, ofdmRates[i]);\n\t\t\t\tPHY_SetTxPowerByRate(pAdapter, band, path, ofdmRates[i], value - base);\n\t\t\t}\n\n\t\t\t/* HT MCS0~7 */\n\t\t\tbase = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_1SS);\n\t\t\tfor (i = 0; i < sizeof(mcs0_7Rates); ++i) {\n\t\t\t\tvalue = PHY_GetTxPowerByRate(pAdapter, band, path, mcs0_7Rates[i]);\n\t\t\t\tPHY_SetTxPowerByRate(pAdapter, band, path, mcs0_7Rates[i], value - base);\n\t\t\t}\n\n\t\t\t/* HT MCS8~15 */\n\t\t\tbase = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_2SS);\n\t\t\tfor (i = 0; i < sizeof(mcs8_15Rates); ++i) {\n\t\t\t\tvalue = PHY_GetTxPowerByRate(pAdapter, band, path, mcs8_15Rates[i]);\n\t\t\t\tPHY_SetTxPowerByRate(pAdapter, band, path, mcs8_15Rates[i], value - base);\n\t\t\t}\n\n\t\t\t/* HT MCS16~23 */\n\t\t\tbase = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_3SS);\n\t\t\tfor (i = 0; i < sizeof(mcs16_23Rates); ++i) {\n\t\t\t\tvalue = PHY_GetTxPowerByRate(pAdapter, band, path, mcs16_23Rates[i]);\n\t\t\t\tPHY_SetTxPowerByRate(pAdapter, band, path, mcs16_23Rates[i], value - base);\n\t\t\t}\n\n\t\t\t/* VHT 1SS */\n\t\t\tbase = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_1SS);\n\t\t\tfor (i = 0; i < sizeof(vht1ssRates); ++i) {\n\t\t\t\tvalue = PHY_GetTxPowerByRate(pAdapter, band, path, vht1ssRates[i]);\n\t\t\t\tPHY_SetTxPowerByRate(pAdapter, band, path, vht1ssRates[i], value - base);\n\t\t\t}\n\n\t\t\t/* VHT 2SS */\n\t\t\tbase = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_2SS);\n\t\t\tfor (i = 0; i < sizeof(vht2ssRates); ++i) {\n\t\t\t\tvalue = PHY_GetTxPowerByRate(pAdapter, band, path, vht2ssRates[i]);\n\t\t\t\tPHY_SetTxPowerByRate(pAdapter, band, path, vht2ssRates[i], value - base);\n\t\t\t}\n\n\t\t\t/* VHT 3SS */\n\t\t\tbase = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_3SS);\n\t\t\tfor (i = 0; i < sizeof(vht3ssRates); ++i) {\n\t\t\t\tvalue = PHY_GetTxPowerByRate(pAdapter, band, path, vht3ssRates[i]);\n\t\t\t\tPHY_SetTxPowerByRate(pAdapter, band, path, vht3ssRates[i], value - base);\n\t\t\t}\n\t\t}\n\t}\n\n\t/* RTW_INFO(\"<===PHY_ConvertTxPowerByRateInDbmToRelativeValues()\\n\" ); */\n}\n\n/*\n  * This function must be called if the value in the PHY_REG_PG.txt(or header)\n  * is exact dBm values\n  */\nvoid\nPHY_TxPowerByRateConfiguration(\n\t\tPADAPTER\t\t\tpAdapter\n)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\n\tphy_txpwr_by_rate_chk_for_path_dup(pAdapter);\n\tphy_StoreTxPowerByRateBase(pAdapter);\n\tphy_ConvertTxPowerByRateInDbmToRelativeValues(pAdapter);\n}\n\nvoid\nphy_set_tx_power_index_by_rate_section(\n\t\tPADAPTER\t\tpAdapter,\n\t\tenum rf_path\t\tRFPath,\n\t\tu8\t\t\t\tChannel,\n\t\tu8\t\t\t\tRateSection\n)\n{\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(pAdapter);\n\n\tif (RateSection >= RATE_SECTION_NUM) {\n\t\tRTW_INFO(\"Invalid RateSection %d in %s\", RateSection, __func__);\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (RateSection == CCK && pHalData->current_band_type != BAND_ON_2_4G)\n\t\tgoto exit;\n\n\tPHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->current_channel_bw, Channel,\n\t\trates_by_sections[RateSection].rates, rates_by_sections[RateSection].rate_num);\n\nexit:\n\treturn;\n}\n\nBOOLEAN\nphy_GetChnlIndex(\n\t\tu8\tChannel,\n\t\tu8\t*ChannelIdx\n)\n{\n\tu8  i = 0;\n\tBOOLEAN bIn24G = _TRUE;\n\n\tif (Channel <= 14) {\n\t\tbIn24G = _TRUE;\n\t\t*ChannelIdx = Channel - 1;\n\t} else {\n\t\tbIn24G = _FALSE;\n\n\t\tfor (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) {\n\t\t\tif (center_ch_5g_all[i] == Channel) {\n\t\t\t\t*ChannelIdx = i;\n\t\t\t\treturn bIn24G;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn bIn24G;\n}\n\nu8 phy_get_pg_txpwr_idx(\n\t\tPADAPTER\t\tpAdapter,\n\t\tenum rf_path\t\tRFPath,\n\t\tu8\t\t\t\tRate,\n\t\tu8 ntx_idx,\n\t\tenum channel_width\tBandWidth,\n\t\tu8\t\t\t\tChannel,\n\t\tPBOOLEAN\t\tbIn24G\n)\n{\n\tPHAL_DATA_TYPE\t\tpHalData = GET_HAL_DATA(pAdapter);\n\tstruct dm_struct\t\t\t*pDM_Odm = &pHalData->odmpriv;\n\tu8\t\t\t\t\ti = 0;\t/* default set to 1S */\n\tu8\t\t\t\t\ttxPower = 0;\n\tu8\t\t\t\t\tchnlIdx = (Channel - 1);\n\n\tif (HAL_IsLegalChannel(pAdapter, Channel) == _FALSE) {\n\t\tchnlIdx = 0;\n\t\tRTW_INFO(\"Illegal channel!!\\n\");\n\t}\n\n\t*bIn24G = phy_GetChnlIndex(Channel, &chnlIdx);\n\n\tif (0)\n\t\tRTW_INFO(\"[%s] Channel Index: %d\\n\", (*bIn24G ? \"2.4G\" : \"5G\"), chnlIdx);\n\n\tif (*bIn24G) {\n\t\tif (IS_CCK_RATE(Rate)) {\n\t\t\t/* CCK-nTX */\n\t\t\ttxPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx];\n\t\t\ttxPower += pHalData->CCK_24G_Diff[RFPath][RF_1TX];\n\t\t\tif (ntx_idx >= RF_2TX)\n\t\t\t\ttxPower += pHalData->CCK_24G_Diff[RFPath][RF_2TX];\n\t\t\tif (ntx_idx >= RF_3TX)\n\t\t\t\ttxPower += pHalData->CCK_24G_Diff[RFPath][RF_3TX];\n\t\t\tif (ntx_idx >= RF_4TX)\n\t\t\t\ttxPower += pHalData->CCK_24G_Diff[RFPath][RF_4TX];\n\t\t\tgoto exit;\n\t\t}\n\n\t\ttxPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx];\n\n\t\t/* OFDM-nTX */\n\t\tif ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) {\n\t\t\ttxPower += pHalData->OFDM_24G_Diff[RFPath][RF_1TX];\n\t\t\tif (ntx_idx >= RF_2TX)\n\t\t\t\ttxPower += pHalData->OFDM_24G_Diff[RFPath][RF_2TX];\n\t\t\tif (ntx_idx >= RF_3TX)\n\t\t\t\ttxPower += pHalData->OFDM_24G_Diff[RFPath][RF_3TX];\n\t\t\tif (ntx_idx >= RF_4TX)\n\t\t\t\ttxPower += pHalData->OFDM_24G_Diff[RFPath][RF_4TX];\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* BW20-nS */\n\t\tif (BandWidth == CHANNEL_WIDTH_20) {\n\t\t\tif ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW20_24G_Diff[RFPath][RF_1TX];\n\t\t\tif ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW20_24G_Diff[RFPath][RF_2TX];\n\t\t\tif ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW20_24G_Diff[RFPath][RF_3TX];\n\t\t\tif ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW20_24G_Diff[RFPath][RF_4TX];\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* BW40-nS */\n\t\tif (BandWidth == CHANNEL_WIDTH_40) {\n\t\t\tif ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW40_24G_Diff[RFPath][RF_1TX];\n\t\t\tif ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW40_24G_Diff[RFPath][RF_2TX];\n\t\t\tif ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW40_24G_Diff[RFPath][RF_3TX];\n\t\t\tif ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW40_24G_Diff[RFPath][RF_4TX];\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* Willis suggest adopt BW 40M power index while in BW 80 mode */\n\t\tif (BandWidth == CHANNEL_WIDTH_80) {\n\t\t\tif ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW40_24G_Diff[RFPath][RF_1TX];\n\t\t\tif ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW40_24G_Diff[RFPath][RF_2TX];\n\t\t\tif ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW40_24G_Diff[RFPath][RF_3TX];\n\t\t\tif ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW40_24G_Diff[RFPath][RF_4TX];\n\t\t\tgoto exit;\n\t\t}\n\t}\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\telse {\n\t\tif (Rate >= MGN_6M)\n\t\t\ttxPower = pHalData->Index5G_BW40_Base[RFPath][chnlIdx];\n\t\telse {\n\t\t\tRTW_INFO(\"===>%s: INVALID Rate(0x%02x).\\n\", __func__, Rate);\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* OFDM-nTX */\n\t\tif ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) {\n\t\t\ttxPower += pHalData->OFDM_5G_Diff[RFPath][RF_1TX];\n\t\t\tif (ntx_idx >= RF_2TX)\n\t\t\t\ttxPower += pHalData->OFDM_5G_Diff[RFPath][RF_2TX];\n\t\t\tif (ntx_idx >= RF_3TX)\n\t\t\t\ttxPower += pHalData->OFDM_5G_Diff[RFPath][RF_3TX];\n\t\t\tif (ntx_idx >= RF_4TX)\n\t\t\t\ttxPower += pHalData->OFDM_5G_Diff[RFPath][RF_4TX];\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* BW20-nS */\n\t\tif (BandWidth == CHANNEL_WIDTH_20) {\n\t\t\tif ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31)  || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW20_5G_Diff[RFPath][RF_1TX];\n\t\t\tif ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW20_5G_Diff[RFPath][RF_2TX];\n\t\t\tif ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW20_5G_Diff[RFPath][RF_3TX];\n\t\t\tif ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW20_5G_Diff[RFPath][RF_4TX];\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* BW40-nS */\n\t\tif (BandWidth == CHANNEL_WIDTH_40) {\n\t\t\tif ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31)  || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW40_5G_Diff[RFPath][RF_1TX];\n\t\t\tif ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW40_5G_Diff[RFPath][RF_2TX];\n\t\t\tif ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW40_5G_Diff[RFPath][RF_3TX];\n\t\t\tif ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW40_5G_Diff[RFPath][RF_4TX];\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* BW80-nS */\n\t\tif (BandWidth == CHANNEL_WIDTH_80) {\n\t\t\t/* get 80MHz cch index */\n\t\t\tfor (i = 0; i < CENTER_CH_5G_80M_NUM; ++i) {\n\t\t\t\tif (center_ch_5g_80m[i] == Channel) {\n\t\t\t\t\tchnlIdx = i;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (i >= CENTER_CH_5G_80M_NUM) {\n\t\t\t#ifdef CONFIG_MP_INCLUDED\n\t\t\t\tif (rtw_mp_mode_check(pAdapter) == _FALSE)\n\t\t\t#endif\n\t\t\t\t\trtw_warn_on(1);\n\t\t\t\ttxPower = 0;\n\t\t\t\tgoto exit;\n\t\t\t}\n\n\t\t\ttxPower = pHalData->Index5G_BW80_Base[RFPath][chnlIdx];\n\n\t\t\tif ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31)  || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += + pHalData->BW80_5G_Diff[RFPath][RF_1TX];\n\t\t\tif ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW80_5G_Diff[RFPath][RF_2TX];\n\t\t\tif ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW80_5G_Diff[RFPath][RF_3TX];\n\t\t\tif ((MGN_MCS23 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))\n\t\t\t\ttxPower += pHalData->BW80_5G_Diff[RFPath][RF_4TX];\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* TODO: BW160-nS */\n\t\trtw_warn_on(1);\n\t}\n#endif /* CONFIG_IEEE80211_BAND_5GHZ */\n\nexit:\n\treturn txPower;\n}\n\ns8\nPHY_GetTxPowerTrackingOffset(\n\tPADAPTER\tpAdapter,\n\tenum rf_path\tRFPath,\n\tu8\t\t\tRate\n)\n{\n\tPHAL_DATA_TYPE\t\tpHalData = GET_HAL_DATA(pAdapter);\n\tstruct dm_struct\t\t\t*pDM_Odm = &pHalData->odmpriv;\n\ts8\toffset = 0;\n\n\tif (pDM_Odm->rf_calibrate_info.txpowertrack_control  == _FALSE)\n\t\treturn offset;\n\n\tif ((Rate == MGN_1M) || (Rate == MGN_2M) || (Rate == MGN_5_5M) || (Rate == MGN_11M)) {\n\t\toffset = pDM_Odm->rf_calibrate_info.remnant_cck_swing_idx;\n\t\t/*RTW_INFO(\"+Remnant_CCKSwingIdx = 0x%x\\n\", RFPath, Rate, pRFCalibrateInfo->Remnant_CCKSwingIdx);*/\n\t} else {\n\t\toffset = pDM_Odm->rf_calibrate_info.remnant_ofdm_swing_idx[RFPath];\n\t\t/*RTW_INFO(\"+Remanant_OFDMSwingIdx[RFPath %u][Rate 0x%x] = 0x%x\\n\", RFPath, Rate, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]);\t*/\n\n\t}\n\n\treturn offset;\n}\n\n/*The same as MRateToHwRate in hal_com.c*/\nu8\nPHY_GetRateIndexOfTxPowerByRate(\n\t\tu8\t\tRate\n)\n{\n\tu8\tindex = 0;\n\tswitch (Rate) {\n\tcase MGN_1M:\n\t\tindex = 0;\n\t\tbreak;\n\tcase MGN_2M:\n\t\tindex = 1;\n\t\tbreak;\n\tcase MGN_5_5M:\n\t\tindex = 2;\n\t\tbreak;\n\tcase MGN_11M:\n\t\tindex = 3;\n\t\tbreak;\n\tcase MGN_6M:\n\t\tindex = 4;\n\t\tbreak;\n\tcase MGN_9M:\n\t\tindex = 5;\n\t\tbreak;\n\tcase MGN_12M:\n\t\tindex = 6;\n\t\tbreak;\n\tcase MGN_18M:\n\t\tindex = 7;\n\t\tbreak;\n\tcase MGN_24M:\n\t\tindex = 8;\n\t\tbreak;\n\tcase MGN_36M:\n\t\tindex = 9;\n\t\tbreak;\n\tcase MGN_48M:\n\t\tindex = 10;\n\t\tbreak;\n\tcase MGN_54M:\n\t\tindex = 11;\n\t\tbreak;\n\tcase MGN_MCS0:\n\t\tindex = 12;\n\t\tbreak;\n\tcase MGN_MCS1:\n\t\tindex = 13;\n\t\tbreak;\n\tcase MGN_MCS2:\n\t\tindex = 14;\n\t\tbreak;\n\tcase MGN_MCS3:\n\t\tindex = 15;\n\t\tbreak;\n\tcase MGN_MCS4:\n\t\tindex = 16;\n\t\tbreak;\n\tcase MGN_MCS5:\n\t\tindex = 17;\n\t\tbreak;\n\tcase MGN_MCS6:\n\t\tindex = 18;\n\t\tbreak;\n\tcase MGN_MCS7:\n\t\tindex = 19;\n\t\tbreak;\n\tcase MGN_MCS8:\n\t\tindex = 20;\n\t\tbreak;\n\tcase MGN_MCS9:\n\t\tindex = 21;\n\t\tbreak;\n\tcase MGN_MCS10:\n\t\tindex = 22;\n\t\tbreak;\n\tcase MGN_MCS11:\n\t\tindex = 23;\n\t\tbreak;\n\tcase MGN_MCS12:\n\t\tindex = 24;\n\t\tbreak;\n\tcase MGN_MCS13:\n\t\tindex = 25;\n\t\tbreak;\n\tcase MGN_MCS14:\n\t\tindex = 26;\n\t\tbreak;\n\tcase MGN_MCS15:\n\t\tindex = 27;\n\t\tbreak;\n\tcase MGN_MCS16:\n\t\tindex = 28;\n\t\tbreak;\n\tcase MGN_MCS17:\n\t\tindex = 29;\n\t\tbreak;\n\tcase MGN_MCS18:\n\t\tindex = 30;\n\t\tbreak;\n\tcase MGN_MCS19:\n\t\tindex = 31;\n\t\tbreak;\n\tcase MGN_MCS20:\n\t\tindex = 32;\n\t\tbreak;\n\tcase MGN_MCS21:\n\t\tindex = 33;\n\t\tbreak;\n\tcase MGN_MCS22:\n\t\tindex = 34;\n\t\tbreak;\n\tcase MGN_MCS23:\n\t\tindex = 35;\n\t\tbreak;\n\tcase MGN_MCS24:\n\t\tindex = 36;\n\t\tbreak;\n\tcase MGN_MCS25:\n\t\tindex = 37;\n\t\tbreak;\n\tcase MGN_MCS26:\n\t\tindex = 38;\n\t\tbreak;\n\tcase MGN_MCS27:\n\t\tindex = 39;\n\t\tbreak;\n\tcase MGN_MCS28:\n\t\tindex = 40;\n\t\tbreak;\n\tcase MGN_MCS29:\n\t\tindex = 41;\n\t\tbreak;\n\tcase MGN_MCS30:\n\t\tindex = 42;\n\t\tbreak;\n\tcase MGN_MCS31:\n\t\tindex = 43;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS0:\n\t\tindex = 44;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS1:\n\t\tindex = 45;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS2:\n\t\tindex = 46;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS3:\n\t\tindex = 47;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS4:\n\t\tindex = 48;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS5:\n\t\tindex = 49;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS6:\n\t\tindex = 50;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS7:\n\t\tindex = 51;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS8:\n\t\tindex = 52;\n\t\tbreak;\n\tcase MGN_VHT1SS_MCS9:\n\t\tindex = 53;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS0:\n\t\tindex = 54;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS1:\n\t\tindex = 55;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS2:\n\t\tindex = 56;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS3:\n\t\tindex = 57;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS4:\n\t\tindex = 58;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS5:\n\t\tindex = 59;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS6:\n\t\tindex = 60;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS7:\n\t\tindex = 61;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS8:\n\t\tindex = 62;\n\t\tbreak;\n\tcase MGN_VHT2SS_MCS9:\n\t\tindex = 63;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS0:\n\t\tindex = 64;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS1:\n\t\tindex = 65;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS2:\n\t\tindex = 66;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS3:\n\t\tindex = 67;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS4:\n\t\tindex = 68;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS5:\n\t\tindex = 69;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS6:\n\t\tindex = 70;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS7:\n\t\tindex = 71;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS8:\n\t\tindex = 72;\n\t\tbreak;\n\tcase MGN_VHT3SS_MCS9:\n\t\tindex = 73;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS0:\n\t\tindex = 74;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS1:\n\t\tindex = 75;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS2:\n\t\tindex = 76;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS3:\n\t\tindex = 77;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS4:\n\t\tindex = 78;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS5:\n\t\tindex = 79;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS6:\n\t\tindex = 80;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS7:\n\t\tindex = 81;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS8:\n\t\tindex = 82;\n\t\tbreak;\n\tcase MGN_VHT4SS_MCS9:\n\t\tindex = 83;\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(\"Invalid rate 0x%x in %s\\n\", Rate, __FUNCTION__);\n\t\tbreak;\n\t};\n\n\treturn index;\n}\n\ns8\n_PHY_GetTxPowerByRate(\n\t\tPADAPTER\tpAdapter,\n\t\tu8\t\t\tBand,\n\t\tenum rf_path\tRFPath,\n\t\tu8\t\t\tRate\n)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\n\ts8 value = 0;\n\tu8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);\n\n\tif (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {\n\t\tRTW_INFO(\"Invalid band %d in %s\\n\", Band, __func__);\n\t\tgoto exit;\n\t}\n\tif (RFPath > RF_PATH_D) {\n\t\tRTW_INFO(\"Invalid RfPath %d in %s\\n\", RFPath, __func__);\n\t\tgoto exit;\n\t}\n\tif (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) {\n\t\tRTW_INFO(\"Invalid RateIndex %d in %s\\n\", rateIndex, __func__);\n\t\tgoto exit;\n\t}\n\n\tvalue = pHalData->TxPwrByRateOffset[Band][RFPath][rateIndex];\n\nexit:\n\treturn value;\n}\n\n\ns8\nPHY_GetTxPowerByRate(\n\t\tPADAPTER\tpAdapter,\n\t\tu8\t\t\tBand,\n\t\tenum rf_path\tRFPath,\n\t\tu8\t\t\tRate\n)\n{\n\tif (!phy_is_tx_power_by_rate_needed(pAdapter))\n\t\treturn 0;\n\n\treturn _PHY_GetTxPowerByRate(pAdapter, Band, RFPath, Rate);\n}\n\nvoid\nPHY_SetTxPowerByRate(\n\t\tPADAPTER\tpAdapter,\n\t\tu8\t\t\tBand,\n\t\tenum rf_path\tRFPath,\n\t\tu8\t\t\tRate,\n\t\ts8\t\t\tValue\n)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\tu8\trateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);\n\n\tif (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {\n\t\tRTW_INFO(\"Invalid band %d in %s\\n\", Band, __FUNCTION__);\n\t\treturn;\n\t}\n\tif (RFPath > RF_PATH_D) {\n\t\tRTW_INFO(\"Invalid RfPath %d in %s\\n\", RFPath, __FUNCTION__);\n\t\treturn;\n\t}\n\tif (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) {\n\t\tRTW_INFO(\"Invalid RateIndex %d in %s\\n\", rateIndex, __FUNCTION__);\n\t\treturn;\n\t}\n\n\tpHalData->TxPwrByRateOffset[Band][RFPath][rateIndex] = Value;\n}\n\nu8 phy_check_under_survey_ch(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\t_adapter *iface;\n\tstruct mlme_ext_priv *mlmeext;\n\tu8 ret = _FALSE;\n\tint i;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (!iface)\n\t\t\tcontinue;\n\t\tmlmeext = &iface->mlmeextpriv;\n\n\t\t/* check scan state */\n\t\tif (mlmeext_scan_state(mlmeext) != SCAN_DISABLE\n\t\t\t&& mlmeext_scan_state(mlmeext) != SCAN_COMPLETE\n\t\t\t\t&& mlmeext_scan_state(mlmeext) != SCAN_BACKING_OP) {\n\t\t\tret = _TRUE;\n\t\t} else if (mlmeext_scan_state(mlmeext) == SCAN_BACKING_OP\n\t\t\t&& !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME)) {\n\t\t\tret = _TRUE;\n\t\t}\n\t}\n\n\treturn ret;\n}\n\nvoid\nphy_set_tx_power_level_by_path(\n\t\tPADAPTER\tAdapter,\n\t\tu8\t\t\tchannel,\n\t\tu8\t\t\tpath\n)\n{\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(Adapter);\n\tBOOLEAN bIsIn24G = (pHalData->current_band_type == BAND_ON_2_4G);\n\tu8 under_survey_ch = phy_check_under_survey_ch(Adapter);\n\n\n\t/* if ( pMgntInfo->RegNByteAccess == 0 ) */\n\t{\n\t\tif (bIsIn24G)\n\t\t\tphy_set_tx_power_index_by_rate_section(Adapter, path, channel, CCK);\n\n\t\tphy_set_tx_power_index_by_rate_section(Adapter, path, channel, OFDM);\n\n\t\tif (!under_survey_ch) {\n\t\t\tphy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS0_MCS7);\n\n\t\t\tif (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))\n\t\t\t\tphy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_1SSMCS0_1SSMCS9);\n\n\t\t\tif (pHalData->NumTotalRFPath >= 2) {\n\t\t\t\tphy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS8_MCS15);\n\n\t\t\t\tif (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))\n\t\t\t\t\tphy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_2SSMCS0_2SSMCS9);\n\n\t\t\t\tif (IS_HARDWARE_TYPE_8814A(Adapter)) {\n\t\t\t\t\tphy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS16_MCS23);\n\t\t\t\t\tphy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_3SSMCS0_3SSMCS9);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\n#ifndef DBG_TX_POWER_IDX\n#define DBG_TX_POWER_IDX 0\n#endif\n\nvoid\nPHY_SetTxPowerIndexByRateArray(\n\t\tPADAPTER\t\t\tpAdapter,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tenum channel_width\tBandWidth,\n\t\tu8\t\t\t\t\tChannel,\n\t\tu8\t\t\t\t\t*Rates,\n\t\tu8\t\t\t\t\tRateArraySize\n)\n{\n\tu32\tpowerIndex = 0;\n\tint\ti = 0;\n\n\tfor (i = 0; i < RateArraySize; ++i) {\n#if DBG_TX_POWER_IDX\n\t\tstruct txpwr_idx_comp tic;\n\n\t\tpowerIndex = rtw_hal_get_tx_power_index(pAdapter, RFPath, Rates[i], BandWidth, Channel, &tic);\n\t\tRTW_INFO(\"TXPWR: [%c][%s]ch:%u, %s %uT, pwr_idx:%u(0x%02x) = %u + (%d=%d:%d) + (%d) + (%d) + (%d) + (%d)\\n\"\n\t\t\t, rf_path_char(RFPath), ch_width_str(BandWidth), Channel, MGN_RATE_STR(Rates[i]), tic.ntx_idx + 1\n\t\t\t, powerIndex, powerIndex, tic.pg, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt\n\t\t\t, tic.ebias, tic.btc, tic.dpd);\n#else\n\t\tpowerIndex = phy_get_tx_power_index(pAdapter, RFPath, Rates[i], BandWidth, Channel);\n#endif\n\t\tPHY_SetTxPowerIndex(pAdapter, powerIndex, RFPath, Rates[i]);\n\t}\n}\n\n#if CONFIG_TXPWR_LIMIT\nconst char *const _txpwr_lmt_rs_str[] = {\n\t\"CCK\",\n\t\"OFDM\",\n\t\"HT\",\n\t\"VHT\",\n\t\"UNKNOWN\",\n};\n\nstatic s8\nphy_GetChannelIndexOfTxPowerLimit(\n\t\tu8\t\t\tBand,\n\t\tu8\t\t\tChannel\n)\n{\n\ts8\tchannelIndex = -1;\n\tu8\ti = 0;\n\n\tif (Band == BAND_ON_2_4G)\n\t\tchannelIndex = Channel - 1;\n\telse if (Band == BAND_ON_5G) {\n\t\tfor (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) {\n\t\t\tif (center_ch_5g_all[i] == Channel)\n\t\t\t\tchannelIndex = i;\n\t\t}\n\t} else\n\t\tRTW_PRINT(\"Invalid Band %d in %s\\n\", Band, __func__);\n\n\tif (channelIndex == -1)\n\t\tRTW_PRINT(\"Invalid Channel %d of Band %d in %s\\n\", Channel, Band, __func__);\n\n\treturn channelIndex;\n}\n\nstatic s8 phy_txpwr_ww_lmt_value(_adapter *adapter)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\n\tif (hal_spec->txgi_max == 63)\n\t\treturn -63;\n\telse if (hal_spec->txgi_max == 127)\n\t\treturn -128;\n\n\trtw_warn_on(1);\n\treturn -128;\n}\n\n/*\n* return txpwr limit absolute value\n* hsl_spec->txgi_max is returned when NO limit\n*/\ns8 phy_get_txpwr_lmt_abs(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tconst char\t\t\t*regd_name,\n\t\tBAND_TYPE\t\t\tBand,\n\t\tenum channel_width\t\tbw,\n\tu8 tlrs,\n\tu8 ntx_idx,\n\tu8 cch,\n\tu8 lock\n)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(Adapter);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(Adapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);\n\tstruct txpwr_lmt_ent *ent = NULL;\n\t_irqL irqL;\n\t_list *cur, *head;\n\ts8 ch_idx;\n\tu8 is_ww_regd = 0;\n\ts8 ww_lmt_val = phy_txpwr_ww_lmt_value(Adapter);\n\ts8 lmt = hal_spec->txgi_max;\n\n\tif ((Adapter->registrypriv.RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory != 1) ||\n\t\tAdapter->registrypriv.RegEnableTxPowerLimit == 0)\n\t\tgoto exit;\n\n\tif (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {\n\t\tRTW_ERR(\"%s invalid band:%u\\n\", __func__, Band);\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (Band == BAND_ON_5G  && tlrs == TXPWR_LMT_RS_CCK) {\n\t\tRTW_ERR(\"5G has no CCK\\n\");\n\t\tgoto exit;\n\t}\n\n\tif (lock)\n\t\t_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\n\tif (!regd_name) /* no regd_name specified, use currnet */\n\t\tregd_name = rfctl->regd_name;\n\n\tif (rfctl->txpwr_regd_num == 0\n\t\t|| strcmp(regd_name, regd_str(TXPWR_LMT_NONE)) == 0)\n\t\tgoto release_lock;\n\n\tif (strcmp(regd_name, regd_str(TXPWR_LMT_WW)) == 0)\n\t\tis_ww_regd = 1;\n\n\tif (!is_ww_regd) {\n\t\tent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name);\n\t\tif (!ent)\n\t\t\tgoto release_lock;\n\t}\n\n\tch_idx = phy_GetChannelIndexOfTxPowerLimit(Band, cch);\n\tif (ch_idx == -1)\n\t\tgoto release_lock;\n\n\tif (Band == BAND_ON_2_4G) {\n\t\tif (!is_ww_regd) {\n\t\t\tlmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx];\n\t\t\tif (lmt != ww_lmt_val)\n\t\t\t\tgoto release_lock;\n\t\t}\n\n\t\t/* search for min value for WW regd or WW limit */\n\t\tlmt = hal_spec->txgi_max;\n\t\thead = &rfctl->txpwr_lmt_list;\n\t\tcur = get_next(head);\n\t\twhile ((rtw_end_of_queue_search(head, cur)) == _FALSE) {\n\t\t\tent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);\n\t\t\tcur = get_next(cur);\n\t\t\tif (ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] != ww_lmt_val)\n\t\t\t\tlmt = rtw_min(lmt, ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx]);\n\t\t}\n\t}\n\t#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\telse if (Band == BAND_ON_5G) {\n\t\tif (!is_ww_regd) {\n\t\t\tlmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx];\n\t\t\tif (lmt != ww_lmt_val)\n\t\t\t\tgoto release_lock;\n\t\t}\n\n\t\t/* search for min value for WW regd or WW limit */\n\t\tlmt = hal_spec->txgi_max;\n\t\thead = &rfctl->txpwr_lmt_list;\n\t\tcur = get_next(head);\n\t\twhile ((rtw_end_of_queue_search(head, cur)) == _FALSE) {\n\t\t\tent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);\n\t\t\tcur = get_next(cur);\n\t\t\tif (ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] != ww_lmt_val)\n\t\t\t\tlmt = rtw_min(lmt, ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx]);\n\t\t}\n\t}\n\t#endif\n\nrelease_lock:\n\tif (lock)\n\t\t_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\nexit:\n\treturn lmt;\n}\n\n/*\n* return txpwr limit diff value\n* hal_spec->txgi_max is returned when NO limit\n*/\ninline s8 phy_get_txpwr_lmt(_adapter *adapter\n\t, const char *regd_name\n\t, BAND_TYPE band, enum channel_width bw\n\t, u8 rfpath, u8 rs, u8 ntx_idx, u8 cch, u8 lock\n)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tu8 tlrs;\n\ts8 lmt = hal_spec->txgi_max;\n\n\tif (IS_CCK_RATE_SECTION(rs))\n\t\ttlrs = TXPWR_LMT_RS_CCK;\n\telse if (IS_OFDM_RATE_SECTION(rs))\n\t\ttlrs = TXPWR_LMT_RS_OFDM;\n\telse if (IS_HT_RATE_SECTION(rs))\n\t\ttlrs = TXPWR_LMT_RS_HT;\n\telse if (IS_VHT_RATE_SECTION(rs))\n\t\ttlrs = TXPWR_LMT_RS_VHT;\n\telse {\n\t\tRTW_ERR(\"%s invalid rs %u\\n\", __func__, rs);\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tlmt = phy_get_txpwr_lmt_abs(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock);\n\n\tif (lmt != hal_spec->txgi_max) {\n\t\t/* return diff value */\n\t\tlmt = lmt - PHY_GetTxPowerByRateBase(adapter, band, rfpath, rs);\n\t}\n\nexit:\n\treturn lmt;\n}\n\n/*\n* May search for secondary channels for min limit\n* return txpwr limit diff value\n*/\ns8\nPHY_GetTxPowerLimit(_adapter *adapter\n\t, const char *regd_name\n\t, BAND_TYPE band, enum channel_width bw\n\t, u8 rfpath, u8 rate, u8 ntx_idx, u8 cch)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tBOOLEAN no_sc = _FALSE;\n\ts8 tlrs = -1, rs = -1;\n\ts8 lmt = hal_spec->txgi_max;\n\tu8 tmp_cch = 0;\n\tu8 tmp_bw;\n\tu8 bw_bmp = 0;\n\ts8 min_lmt = hal_spec->txgi_max;\n\tu8 final_bw = bw, final_cch = cch;\n\t_irqL irqL;\n\n#ifdef CONFIG_MP_INCLUDED\n\t/* MP mode channel don't use secondary channel */\n\tif (rtw_mp_mode_check(adapter) == _TRUE)\n\t\tno_sc = _TRUE;\n#endif\n\tif (IS_CCK_RATE(rate)) {\n\t\ttlrs = TXPWR_LMT_RS_CCK;\n\t\trs = CCK;\n\t} else if (IS_OFDM_RATE(rate)) {\n\t\ttlrs = TXPWR_LMT_RS_OFDM;\n\t\trs = OFDM;\n\t} else if (IS_HT_RATE(rate)) {\n\t\ttlrs = TXPWR_LMT_RS_HT;\n\t\trs = HT_1SS + (IS_HT1SS_RATE(rate) ? 0 : IS_HT2SS_RATE(rate) ? 1 : IS_HT3SS_RATE(rate) ? 2 : IS_HT4SS_RATE(rate) ? 3 : 0);\n\t} else if (IS_VHT_RATE(rate)) {\n\t\ttlrs = TXPWR_LMT_RS_VHT;\n\t\trs = VHT_1SS + (IS_VHT1SS_RATE(rate) ? 0 : IS_VHT2SS_RATE(rate) ? 1 : IS_VHT3SS_RATE(rate) ? 2 : IS_VHT4SS_RATE(rate) ? 3 : 0);\n\t} else {\n\t\tRTW_ERR(\"%s invalid rate 0x%x\\n\", __func__, rate);\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (no_sc == _TRUE) {\n\t\t/* use the input center channel and bandwidth directly */\n\t\ttmp_cch = cch;\n\t\tbw_bmp = ch_width_to_bw_cap(bw);\n\t} else {\n\t\t/*\n\t\t* find the possible tx bandwidth bmp for this rate, and then will get center channel for each bandwidth\n\t\t* if no possible tx bandwidth bmp, select valid bandwidth up to current RF bandwidth into bmp\n\t\t*/\n\t\tif (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM)\n\t\t\tbw_bmp = BW_CAP_20M; /* CCK, OFDM only BW 20M */\n\t\telse if (tlrs == TXPWR_LMT_RS_HT) {\n\t\t\tbw_bmp = rtw_get_tx_bw_bmp_of_ht_rate(dvobj, rate, bw);\n\t\t\tif (bw_bmp == 0)\n\t\t\t\tbw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_40 ? CHANNEL_WIDTH_40 : bw);\n\t\t} else if (tlrs == TXPWR_LMT_RS_VHT) {\n\t\t\tbw_bmp = rtw_get_tx_bw_bmp_of_vht_rate(dvobj, rate, bw);\n\t\t\tif (bw_bmp == 0)\n\t\t\t\tbw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_160 ? CHANNEL_WIDTH_160 : bw);\n\t\t} else\n\t\t\trtw_warn_on(1);\n\t}\n\n\tif (bw_bmp == 0)\n\t\tgoto exit;\n\n\t_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\n\t/* loop for each possible tx bandwidth to find minimum limit */\n\tfor (tmp_bw = CHANNEL_WIDTH_20; tmp_bw <= bw; tmp_bw++) {\n\t\tif (!(ch_width_to_bw_cap(tmp_bw) & bw_bmp))\n\t\t\tcontinue;\n\n\t\tif (no_sc == _FALSE) {\n\t\t\tif (tmp_bw == CHANNEL_WIDTH_20)\n\t\t\t\ttmp_cch = hal_data->cch_20;\n\t\t\telse if (tmp_bw == CHANNEL_WIDTH_40)\n\t\t\t\ttmp_cch = hal_data->cch_40;\n\t\t\telse if (tmp_bw == CHANNEL_WIDTH_80)\n\t\t\t\ttmp_cch = hal_data->cch_80;\n\t\t\telse {\n\t\t\t\ttmp_cch = 0;\n\t\t\t\trtw_warn_on(1);\n\t\t\t}\n\t\t}\n\n\t\tlmt = phy_get_txpwr_lmt_abs(adapter, regd_name, band, tmp_bw, tlrs, ntx_idx, tmp_cch, 0);\n\n\t\tif (min_lmt >= lmt) {\n\t\t\tmin_lmt = lmt;\n\t\t\tfinal_cch = tmp_cch;\n\t\t\tfinal_bw = tmp_bw;\n\t\t}\n\n\t}\n\n\t_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\n\tif (min_lmt != hal_spec->txgi_max) {\n\t\t/* return diff value */\n\t\tmin_lmt = min_lmt - PHY_GetTxPowerByRateBase(adapter, band, rfpath, rs);\n\t}\n\nexit:\n\n\tif (0) {\n\t\tif (final_bw != bw && (IS_HT_RATE(rate) || IS_VHT_RATE(rate)))\n\t\t\tRTW_INFO(\"%s min_lmt: %s ch%u -> %s ch%u\\n\"\n\t\t\t\t, MGN_RATE_STR(rate)\n\t\t\t\t, ch_width_str(bw), cch\n\t\t\t\t, ch_width_str(final_bw), final_cch);\n\t}\n\n\treturn min_lmt;\n}\n\nstatic void phy_txpwr_lmt_cck_ofdm_mt_chk(_adapter *adapter)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tstruct txpwr_lmt_ent *ent;\n\t_list *cur, *head;\n\tu8 channel, tlrs, ntx_idx;\n\n\trfctl->txpwr_lmt_2g_cck_ofdm_state = 0;\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\trfctl->txpwr_lmt_5g_cck_ofdm_state = 0;\n#endif\n\n\thead = &rfctl->txpwr_lmt_list;\n\tcur = get_next(head);\n\n\twhile ((rtw_end_of_queue_search(head, cur)) == _FALSE) {\n\t\tent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);\n\t\tcur = get_next(cur);\n\n\t\t/* check 2G CCK, OFDM state*/\n\t\tfor (tlrs = TXPWR_LMT_RS_CCK; tlrs <= TXPWR_LMT_RS_OFDM; tlrs++) {\n\t\t\tfor (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {\n\t\t\t\tfor (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) {\n\t\t\t\t\tif (ent->lmt_2g[CHANNEL_WIDTH_20][tlrs][channel][ntx_idx] != hal_spec->txgi_max) {\n\t\t\t\t\t\tif (tlrs == TXPWR_LMT_RS_CCK)\n\t\t\t\t\t\t\trfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_CCK_1T << ntx_idx;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\trfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/* if 2G OFDM multi-TX is not defined, reference HT20 */\n\t\tfor (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) {\n\t\t\tfor (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {\n\t\t\t\tif (rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))\n\t\t\t\t\tcontinue;\n\t\t\t\tent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM][channel][ntx_idx] =\n\t\t\t\t\tent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT][channel][ntx_idx];\n\t\t\t}\n\t\t}\n\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\t\t/* check 5G OFDM state*/\n\t\tfor (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {\n\t\t\tfor (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {\n\t\t\t\tif (ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] != hal_spec->txgi_max) {\n\t\t\t\t\trfctl->txpwr_lmt_5g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tfor (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {\n\t\t\tfor (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {\n\t\t\t\tif (rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))\n\t\t\t\t\tcontinue;\n\t\t\t\t/* if 5G OFDM multi-TX is not defined, reference HT20 */\n\t\t\t\tent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] =\n\t\t\t\t\tent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT - 1][channel][ntx_idx];\n\t\t\t}\n\t\t}\n#endif /* CONFIG_IEEE80211_BAND_5GHZ */\n\t}\n}\n\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\nstatic void phy_txpwr_lmt_cross_ref_ht_vht(_adapter *adapter)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tstruct txpwr_lmt_ent *ent;\n\t_list *cur, *head;\n\tu8 bw, channel, tlrs, ref_tlrs, ntx_idx;\n\tint ht_ref_vht_5g_20_40 = 0;\n\tint vht_ref_ht_5g_20_40 = 0;\n\tint ht_has_ref_5g_20_40 = 0;\n\tint vht_has_ref_5g_20_40 = 0;\n\n\trfctl->txpwr_lmt_5g_20_40_ref = 0;\n\n\thead = &rfctl->txpwr_lmt_list;\n\tcur = get_next(head);\n\n\twhile ((rtw_end_of_queue_search(head, cur)) == _FALSE) {\n\t\tent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);\n\t\tcur = get_next(cur);\n\n\t\tfor (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {\n\n\t\t\tfor (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {\n\n\t\t\t\tfor (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; ++tlrs) {\n\n\t\t\t\t\t/* 5G 20M 40M VHT and HT can cross reference */\n\t\t\t\t\tif (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40) {\n\t\t\t\t\t\tif (tlrs == TXPWR_LMT_RS_HT)\n\t\t\t\t\t\t\tref_tlrs = TXPWR_LMT_RS_VHT;\n\t\t\t\t\t\telse if (tlrs == TXPWR_LMT_RS_VHT)\n\t\t\t\t\t\t\tref_tlrs = TXPWR_LMT_RS_HT;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tcontinue;\n\n\t\t\t\t\t\tfor (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {\n\n\t\t\t\t\t\t\tif (ent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx] == hal_spec->txgi_max)\n\t\t\t\t\t\t\t\tcontinue;\n\n\t\t\t\t\t\t\tif (tlrs == TXPWR_LMT_RS_HT)\n\t\t\t\t\t\t\t\tht_has_ref_5g_20_40++;\n\t\t\t\t\t\t\telse if (tlrs == TXPWR_LMT_RS_VHT)\n\t\t\t\t\t\t\t\tvht_has_ref_5g_20_40++;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tcontinue;\n\n\t\t\t\t\t\t\tif (ent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] != hal_spec->txgi_max)\n\t\t\t\t\t\t\t\tcontinue;\n\n\t\t\t\t\t\t\tif (tlrs == TXPWR_LMT_RS_HT && ref_tlrs == TXPWR_LMT_RS_VHT)\n\t\t\t\t\t\t\t\tht_ref_vht_5g_20_40++;\n\t\t\t\t\t\t\telse if (tlrs == TXPWR_LMT_RS_VHT && ref_tlrs == TXPWR_LMT_RS_HT)\n\t\t\t\t\t\t\t\tvht_ref_ht_5g_20_40++;\n\n\t\t\t\t\t\t\tif (0)\n\t\t\t\t\t\t\t\tRTW_INFO(\"reg:%s, bw:%u, ch:%u, %s-%uT ref %s-%uT\\n\"\n\t\t\t\t\t\t\t\t\t, ent->regd_name, bw, channel\n\t\t\t\t\t\t\t\t\t, txpwr_lmt_rs_str(tlrs), ntx_idx + 1\n\t\t\t\t\t\t\t\t\t, txpwr_lmt_rs_str(ref_tlrs), ntx_idx + 1);\n\n\t\t\t\t\t\t\tent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] =\n\t\t\t\t\t\t\t\tent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx];\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tif (0) {\n\t\tRTW_INFO(\"ht_ref_vht_5g_20_40:%d, ht_has_ref_5g_20_40:%d\\n\", ht_ref_vht_5g_20_40, ht_has_ref_5g_20_40);\n\t\tRTW_INFO(\"vht_ref_ht_5g_20_40:%d, vht_has_ref_5g_20_40:%d\\n\", vht_ref_ht_5g_20_40, vht_has_ref_5g_20_40);\n\t}\n\n\t/* 5G 20M&40M HT all come from VHT*/\n\tif (ht_ref_vht_5g_20_40 && ht_has_ref_5g_20_40 == ht_ref_vht_5g_20_40)\n\t\trfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_HT_FROM_VHT;\n\n\t/* 5G 20M&40M VHT all come from HT*/\n\tif (vht_ref_ht_5g_20_40 && vht_has_ref_5g_20_40 == vht_ref_ht_5g_20_40)\n\t\trfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_VHT_FROM_HT;\n}\n#endif /* CONFIG_IEEE80211_BAND_5GHZ */\n\n#ifndef DBG_TXPWR_LMT_BAND_CHK\n#define DBG_TXPWR_LMT_BAND_CHK 0\n#endif\n\n#if DBG_TXPWR_LMT_BAND_CHK\n/* check if larger bandwidth limit is less than smaller bandwidth for HT & VHT rate */\nvoid phy_txpwr_limit_bandwidth_chk(_adapter *adapter)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tu8 band, bw, path, tlrs, ntx_idx, cch, offset, scch;\n\tu8 ch_num, n, i;\n\n\tfor (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {\n\t\tif (!hal_is_band_support(adapter, band))\n\t\t\tcontinue;\n\n\t\tfor (bw = CHANNEL_WIDTH_40; bw <= CHANNEL_WIDTH_80; bw++) {\n\t\t\tif (bw >= CHANNEL_WIDTH_160)\n\t\t\t\tcontinue;\n\t\t\tif (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80)\n\t\t\t\tcontinue;\n\n\t\t\tif (band == BAND_ON_2_4G)\n\t\t\t\tch_num = center_chs_2g_num(bw);\n\t\t\telse\n\t\t\t\tch_num = center_chs_5g_num(bw);\n\n\t\t\tif (ch_num == 0) {\n\t\t\t\trtw_warn_on(1);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tfor (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; tlrs++) {\n\n\t\t\t\tif (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT)\n\t\t\t\t\tcontinue;\n\t\t\t\tif (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK)\n\t\t\t\t\tcontinue;\n\t\t\t\tif (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM))\n\t\t\t\t\tcontinue;\n\t\t\t\tif (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT)\n\t\t\t\t\tcontinue;\n\t\t\t\tif (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))\n\t\t\t\t\tcontinue;\n\n\t\t\t\tfor (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {\n\t\t\t\t\tstruct txpwr_lmt_ent *ent;\n\t\t\t\t\t_list *cur, *head;\n\n\t\t\t\t\tif (ntx_idx >= hal_spec->tx_nss_num)\n\t\t\t\t\t\tcontinue;\n\n\t\t\t\t\t/* bypass CCK multi-TX is not defined */\n\t\t\t\t\tif (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) {\n\t\t\t\t\t\tif (band == BAND_ON_2_4G\n\t\t\t\t\t\t\t&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx)))\n\t\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\n\n\t\t\t\t\t/* bypass OFDM multi-TX is not defined */\n\t\t\t\t\tif (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) {\n\t\t\t\t\t\tif (band == BAND_ON_2_4G\n\t\t\t\t\t\t\t&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))\n\t\t\t\t\t\t\tcontinue;\n\t\t\t\t\t\t#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\t\t\t\t\t\tif (band == BAND_ON_5G\n\t\t\t\t\t\t\t&& !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))\n\t\t\t\t\t\t\tcontinue;\n\t\t\t\t\t\t#endif\n\t\t\t\t\t}\n\n\t\t\t\t\t/* bypass 5G 20M, 40M pure reference */\n\t\t\t\t\t#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\t\t\t\t\tif (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) {\n\t\t\t\t\t\tif (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) {\n\t\t\t\t\t\t\tif (tlrs == TXPWR_LMT_RS_HT)\n\t\t\t\t\t\t\t\tcontinue;\n\t\t\t\t\t\t} else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) {\n\t\t\t\t\t\t\tif (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40)\n\t\t\t\t\t\t\t\tcontinue;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\t#endif\n\n\t\t\t\t\tfor (n = 0; n < ch_num; n++) {\n\t\t\t\t\t\tu8 cch_by_bw[3];\n\t\t\t\t\t\tu8 offset_by_bw; /* bitmap, 0 for lower, 1 for upper */\n\t\t\t\t\t\tu8 bw_pos;\n\t\t\t\t\t\ts8 lmt[3];\n\n\t\t\t\t\t\tif (band == BAND_ON_2_4G)\n\t\t\t\t\t\t\tcch = center_chs_2g(bw, n);\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tcch = center_chs_5g(bw, n);\n\n\t\t\t\t\t\tif (cch == 0) {\n\t\t\t\t\t\t\trtw_warn_on(1);\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t}\n\n\t\t\t\t\t\t_rtw_memset(cch_by_bw, 0, 3);\n\t\t\t\t\t\tcch_by_bw[bw] = cch;\n\t\t\t\t\t\toffset_by_bw = 0x01;\n\n\t\t\t\t\t\tdo {\n\t\t\t\t\t\t\tfor (bw_pos = bw; bw_pos >= CHANNEL_WIDTH_40; bw_pos--)\n\t\t\t\t\t\t\t\tcch_by_bw[bw_pos - 1] = rtw_get_scch_by_cch_offset(cch_by_bw[bw_pos], bw_pos, offset_by_bw & BIT(bw_pos) ? HAL_PRIME_CHNL_OFFSET_UPPER : HAL_PRIME_CHNL_OFFSET_LOWER);\n\n\t\t\t\t\t\t\thead = &rfctl->txpwr_lmt_list;\n\t\t\t\t\t\t\tcur = get_next(head);\n\t\t\t\t\t\t\twhile ((rtw_end_of_queue_search(head, cur)) == _FALSE) {\n\t\t\t\t\t\t\t\tent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);\n\t\t\t\t\t\t\t\tcur = get_next(cur);\n\n\t\t\t\t\t\t\t\tfor (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)\n\t\t\t\t\t\t\t\t\tlmt[bw_pos] = phy_get_txpwr_lmt_abs(adapter, ent->regd_name, band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0);\n\n\t\t\t\t\t\t\t\tfor (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--)\n\t\t\t\t\t\t\t\t\tif (lmt[bw_pos] > lmt[bw_pos - 1])\n\t\t\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t\tif (bw_pos == CHANNEL_WIDTH_20)\n\t\t\t\t\t\t\t\t\tcontinue;\n\n\t\t\t\t\t\t\t\tRTW_PRINT_SEL(RTW_DBGDUMP, \"[%s][%s][%s][%uT][%-4s] cch:\"\n\t\t\t\t\t\t\t\t\t, band_str(band)\n\t\t\t\t\t\t\t\t\t, ch_width_str(bw)\n\t\t\t\t\t\t\t\t\t, txpwr_lmt_rs_str(tlrs)\n\t\t\t\t\t\t\t\t\t, ntx_idx + 1\n\t\t\t\t\t\t\t\t\t, ent->regd_name\n\t\t\t\t\t\t\t\t);\n\t\t\t\t\t\t\t\tfor (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)\n\t\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(RTW_DBGDUMP, \"%03u \", cch_by_bw[bw_pos]);\n\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(RTW_DBGDUMP, \"limit:\");\n\t\t\t\t\t\t\t\tfor (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) {\n\t\t\t\t\t\t\t\t\tif (lmt[bw_pos] == hal_spec->txgi_max)\n\t\t\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(RTW_DBGDUMP, \"N/A \");\n\t\t\t\t\t\t\t\t\telse if (lmt[bw_pos] > -hal_spec->txgi_pdbm && lmt[bw_pos] < 0) /* -1 < value < 0 */\n\t\t\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(RTW_DBGDUMP, \"-0.%d\", (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);\n\t\t\t\t\t\t\t\t\telse if (lmt[bw_pos] % hal_spec->txgi_pdbm)\n\t\t\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(RTW_DBGDUMP, \"%2d.%d \", lmt[bw_pos] / hal_spec->txgi_pdbm, (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);\n\t\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(RTW_DBGDUMP, \"%2d \", lmt[bw_pos] / hal_spec->txgi_pdbm);\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(RTW_DBGDUMP, \"\\n\");\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tfor (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)\n\t\t\t\t\t\t\t\tlmt[bw_pos] = phy_get_txpwr_lmt_abs(adapter, regd_str(TXPWR_LMT_WW), band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0);\n\n\t\t\t\t\t\t\tfor (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--)\n\t\t\t\t\t\t\t\tif (lmt[bw_pos] > lmt[bw_pos - 1])\n\t\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tif (bw_pos != CHANNEL_WIDTH_20) {\n\t\t\t\t\t\t\t\tRTW_PRINT_SEL(RTW_DBGDUMP, \"[%s][%s][%s][%uT][%-4s] cch:\"\n\t\t\t\t\t\t\t\t\t, band_str(band)\n\t\t\t\t\t\t\t\t\t, ch_width_str(bw)\n\t\t\t\t\t\t\t\t\t, txpwr_lmt_rs_str(tlrs)\n\t\t\t\t\t\t\t\t\t, ntx_idx + 1\n\t\t\t\t\t\t\t\t\t, regd_str(TXPWR_LMT_WW)\n\t\t\t\t\t\t\t\t);\n\t\t\t\t\t\t\t\tfor (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)\n\t\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(RTW_DBGDUMP, \"%03u \", cch_by_bw[bw_pos]);\n\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(RTW_DBGDUMP, \"limit:\");\n\t\t\t\t\t\t\t\tfor (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) {\n\t\t\t\t\t\t\t\t\tif (lmt[bw_pos] == hal_spec->txgi_max)\n\t\t\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(RTW_DBGDUMP, \"N/A \");\n\t\t\t\t\t\t\t\t\telse if (lmt[bw_pos] > -hal_spec->txgi_pdbm && lmt[bw_pos] < 0) /* -1 < value < 0 */\n\t\t\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(RTW_DBGDUMP, \"-0.%d\", (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);\n\t\t\t\t\t\t\t\t\telse if (lmt[bw_pos] % hal_spec->txgi_pdbm)\n\t\t\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(RTW_DBGDUMP, \"%2d.%d \", lmt[bw_pos] / hal_spec->txgi_pdbm, (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);\n\t\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(RTW_DBGDUMP, \"%2d \", lmt[bw_pos] / hal_spec->txgi_pdbm);\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t_RTW_PRINT_SEL(RTW_DBGDUMP, \"\\n\");\n\t\t\t\t\t\t\t}\n\n\t\t\t\t\t\t\toffset_by_bw += 2;\n\t\t\t\t\t\t\tif (offset_by_bw & BIT(bw + 1))\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t} while (1); /* loop for all ch combinations */\n\t\t\t\t\t} /* loop for center channels */\n\t\t\t\t} /* loop fo each ntx_idx */\n\t\t\t} /* loop for tlrs */\n\t\t} /* loop for bandwidth */\n\t} /* loop for band */\n}\n#endif /* DBG_TXPWR_LMT_BAND_CHK */\n\nstatic void phy_txpwr_lmt_post_hdl(_adapter *adapter)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\t_irqL irqL;\n\n\t_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\tif (IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))\n\t\tphy_txpwr_lmt_cross_ref_ht_vht(adapter);\n#endif\n\tphy_txpwr_lmt_cck_ofdm_mt_chk(adapter);\n\n#if DBG_TXPWR_LMT_BAND_CHK\n\tphy_txpwr_limit_bandwidth_chk(adapter);\n#endif\n\n\t_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);\n}\n\nBOOLEAN\nGetS1ByteIntegerFromStringInDecimal(\n\t\t\tchar\t*str,\n\t\t\ts8\t\t*val\n)\n{\n\tu8 negative = 0;\n\tu16 i = 0;\n\n\t*val = 0;\n\n\twhile (str[i] != '\\0') {\n\t\tif (i == 0 && (str[i] == '+' || str[i] == '-')) {\n\t\t\tif (str[i] == '-')\n\t\t\t\tnegative = 1;\n\t\t} else if (str[i] >= '0' && str[i] <= '9') {\n\t\t\t*val *= 10;\n\t\t\t*val += (str[i] - '0');\n\t\t} else\n\t\t\treturn _FALSE;\n\t\t++i;\n\t}\n\n\tif (negative)\n\t\t*val = -*val;\n\n\treturn _TRUE;\n}\n#endif /* CONFIG_TXPWR_LIMIT */\n\n/*\n* phy_set_tx_power_limit - Parsing TX power limit from phydm array, called by odm_ConfigBB_TXPWR_LMT_XXX in phydm\n*/\nvoid\nphy_set_tx_power_limit(\n\t\tstruct dm_struct\t\t*pDM_Odm,\n\t\tu8\t\t\t\t*Regulation,\n\t\tu8\t\t\t\t*Band,\n\t\tu8\t\t\t\t*Bandwidth,\n\t\tu8\t\t\t\t*RateSection,\n\t\tu8\t\t\t\t*ntx,\n\t\tu8\t\t\t\t*Channel,\n\t\tu8\t\t\t\t*PowerLimit\n)\n{\n#if CONFIG_TXPWR_LIMIT\n\tPADAPTER Adapter = pDM_Odm->adapter;\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);\n\tu8 band = 0, bandwidth = 0, tlrs = 0, channel;\n\tu8 ntx_idx;\n\ts8 powerLimit = 0, prevPowerLimit, channelIndex;\n\ts8 ww_lmt_val = phy_txpwr_ww_lmt_value(Adapter);\n\n\tif (0)\n\t\tRTW_INFO(\"Index of power limit table [regulation %s][band %s][bw %s][rate section %s][ntx %s][chnl %s][val %s]\\n\"\n\t\t\t, Regulation, Band, Bandwidth, RateSection, ntx, Channel, PowerLimit);\n\n\tif (GetU1ByteIntegerFromStringInDecimal((char *)Channel, &channel) == _FALSE\n\t\t|| GetS1ByteIntegerFromStringInDecimal((char *)PowerLimit, &powerLimit) == _FALSE\n\t) {\n\t\tRTW_PRINT(\"Illegal index of power limit table [ch %s][val %s]\\n\", Channel, PowerLimit);\n\t\treturn;\n\t}\n\n\tif (powerLimit != ww_lmt_val) {\n\t\tif (powerLimit < -hal_spec->txgi_max || powerLimit > hal_spec->txgi_max)\n\t\t\tRTW_PRINT(\"Illegal power limit value [ch %s][val %s]\\n\", Channel, PowerLimit);\n\n\t\tif (powerLimit > hal_spec->txgi_max)\n\t\t\tpowerLimit = hal_spec->txgi_max;\n\t\telse if (powerLimit < -hal_spec->txgi_max)\n\t\t\tpowerLimit =  ww_lmt_val + 1;\n\t}\n\n\tif (eqNByte(RateSection, (u8 *)(\"CCK\"), 3))\n\t\ttlrs = TXPWR_LMT_RS_CCK;\n\telse if (eqNByte(RateSection, (u8 *)(\"OFDM\"), 4))\n\t\ttlrs = TXPWR_LMT_RS_OFDM;\n\telse if (eqNByte(RateSection, (u8 *)(\"HT\"), 2))\n\t\ttlrs = TXPWR_LMT_RS_HT;\n\telse if (eqNByte(RateSection, (u8 *)(\"VHT\"), 3))\n\t\ttlrs = TXPWR_LMT_RS_VHT;\n\telse {\n\t\tRTW_PRINT(\"Wrong rate section:%s\\n\", RateSection);\n\t\treturn;\n\t}\n\n\tif (eqNByte(ntx, (u8 *)(\"1T\"), 2))\n\t\tntx_idx = RF_1TX;\n\telse if (eqNByte(ntx, (u8 *)(\"2T\"), 2))\n\t\tntx_idx = RF_2TX;\n\telse if (eqNByte(ntx, (u8 *)(\"3T\"), 2))\n\t\tntx_idx = RF_3TX;\n\telse if (eqNByte(ntx, (u8 *)(\"4T\"), 2))\n\t\tntx_idx = RF_4TX;\n\telse {\n\t\tRTW_PRINT(\"Wrong tx num:%s\\n\", ntx);\n\t\treturn;\n\t}\n\n\tif (eqNByte(Bandwidth, (u8 *)(\"20M\"), 3))\n\t\tbandwidth = CHANNEL_WIDTH_20;\n\telse if (eqNByte(Bandwidth, (u8 *)(\"40M\"), 3))\n\t\tbandwidth = CHANNEL_WIDTH_40;\n\telse if (eqNByte(Bandwidth, (u8 *)(\"80M\"), 3))\n\t\tbandwidth = CHANNEL_WIDTH_80;\n\telse if (eqNByte(Bandwidth, (u8 *)(\"160M\"), 4))\n\t\tbandwidth = CHANNEL_WIDTH_160;\n\telse {\n\t\tRTW_PRINT(\"unknown bandwidth: %s\\n\", Bandwidth);\n\t\treturn;\n\t}\n\n\tif (eqNByte(Band, (u8 *)(\"2.4G\"), 4)) {\n\t\tband = BAND_ON_2_4G;\n\t\tchannelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, channel);\n\n\t\tif (channelIndex == -1) {\n\t\t\tRTW_PRINT(\"unsupported channel: %d at 2.4G\\n\", channel);\n\t\t\treturn;\n\t\t}\n\n\t\tif (bandwidth >= MAX_2_4G_BANDWIDTH_NUM) {\n\t\t\tRTW_PRINT(\"unsupported bandwidth: %s at 2.4G\\n\", Bandwidth);\n\t\t\treturn;\n\t\t}\n\n\t\trtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);\n\t}\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\telse if (eqNByte(Band, (u8 *)(\"5G\"), 2)) {\n\t\tband = BAND_ON_5G;\n\t\tchannelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, channel);\n\n\t\tif (channelIndex == -1) {\n\t\t\tRTW_PRINT(\"unsupported channel: %d at 5G\\n\", channel);\n\t\t\treturn;\n\t\t}\n\n\t\trtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);\n\t}\n#endif\n\telse {\n\t\tRTW_PRINT(\"unknown/unsupported band:%s\\n\", Band);\n\t\treturn;\n\t}\n#endif\n}\n\nu8\nphy_get_tx_power_index(\n\t\tPADAPTER\t\t\tpAdapter,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate,\n\t\tenum channel_width\tBandWidth,\n\t\tu8\t\t\t\t\tChannel\n)\n{\n\treturn rtw_hal_get_tx_power_index(pAdapter, RFPath, Rate, BandWidth, Channel, NULL);\n}\n\nvoid\nPHY_SetTxPowerIndex(\n\t\tPADAPTER\t\tpAdapter,\n\t\tu32\t\t\t\tPowerIndex,\n\t\tenum rf_path\t\tRFPath,\n\t\tu8\t\t\t\tRate\n)\n{\n\trtw_hal_set_tx_power_index(pAdapter, PowerIndex, RFPath, Rate);\n}\n\nvoid dump_tx_power_idx_title(void *sel, _adapter *adapter)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tu8 bw = hal_data->current_channel_bw;\n\n\tRTW_PRINT_SEL(sel, \"%s\", ch_width_str(bw));\n\tif (bw >= CHANNEL_WIDTH_80)\n\t\t_RTW_PRINT_SEL(sel, \", cch80:%u\", hal_data->cch_80);\n\tif (bw >= CHANNEL_WIDTH_40)\n\t\t_RTW_PRINT_SEL(sel, \", cch40:%u\", hal_data->cch_40);\n\t_RTW_PRINT_SEL(sel, \", cch20:%u\\n\", hal_data->cch_20);\n\n\tRTW_PRINT_SEL(sel, \"%-4s %-9s %2s %-3s%6s %-3s %-3s %-4s %-4s %-3s %-5s %-3s %-3s\\n\"\n\t\t, \"path\", \"rate\", \"\", \"pwr\", \"\", \"pg\", \"\", \"(byr\", \"lmt)\", \"tpt\", \"ebias\", \"btc\", \"dpd\");\n}\n\nvoid dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath, u8 rs)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tu8 power_idx;\n\tstruct txpwr_idx_comp tic;\n\tu8 tx_num, i;\n\tu8 band = hal_data->current_band_type;\n\tu8 cch = hal_data->current_channel;\n\tu8 bw = hal_data->current_channel_bw;\n\n\tif (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, rfpath))\n\t\treturn;\n\n\tif (rs >= RATE_SECTION_NUM)\n\t\treturn;\n\n\ttx_num = rate_section_to_tx_num(rs);\n\tif (tx_num >= hal_spec->tx_nss_num || tx_num >= hal_spec->max_tx_cnt)\n\t\treturn;\n\n\tif (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))\n\t\treturn;\n\n\tif (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))\n\t\treturn;\n\n\tfor (i = 0; i < rates_by_sections[rs].rate_num; i++) {\n\t\tpower_idx = rtw_hal_get_tx_power_index(adapter, rfpath, rates_by_sections[rs].rates[i], bw, cch, &tic);\n\n\t\tRTW_PRINT_SEL(sel, \"%4c %9s %uT %3u(0x%02x) %3u %3d (%3d %3d) %3d %5d %3d %3d\\n\"\n\t\t\t, rf_path_char(rfpath), MGN_RATE_STR(rates_by_sections[rs].rates[i]), tic.ntx_idx + 1\n\t\t\t, power_idx, power_idx, tic.pg, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate)\n\t\t\t, tic.by_rate, tic.limit, tic.tpt, tic.ebias, tic.btc, tic.dpd);\n\t}\n}\n\nvoid dump_tx_power_idx(void *sel, _adapter *adapter)\n{\n\tu8 rfpath, rs;\n\n\tdump_tx_power_idx_title(sel, adapter);\n\tfor (rfpath = RF_PATH_A; rfpath < RF_PATH_MAX; rfpath++)\n\t\tfor (rs = CCK; rs < RATE_SECTION_NUM; rs++)\n\t\t\tdump_tx_power_idx_by_path_rs(sel, adapter, rfpath, rs);\n}\n\nbool phy_is_tx_power_limit_needed(_adapter *adapter)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));\n\n#if CONFIG_TXPWR_LIMIT\n\tif (regsty->RegEnableTxPowerLimit == 1\n\t\t|| (regsty->RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory == 1))\n\t\treturn _TRUE;\n#endif\n\n\treturn _FALSE;\n}\n\nbool phy_is_tx_power_by_rate_needed(_adapter *adapter)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));\n\n\tif (regsty->RegEnableTxPowerByRate == 1\n\t\t|| (regsty->RegEnableTxPowerByRate == 2 && hal_data->EEPROMRegulatory != 2))\n\t\treturn _TRUE;\n\treturn _FALSE;\n}\n\nint phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));\n\tint ret = _FAIL;\n\n\thal_data->txpwr_by_rate_loaded = 0;\n\tPHY_InitTxPowerByRate(adapter);\n\n\t/* tx power limit is based on tx power by rate */\n\thal_data->txpwr_limit_loaded = 0;\n\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\tif (chk_file\n\t\t&& phy_ConfigBBWithPgParaFile(adapter, PHY_FILE_PHY_REG_PG) == _SUCCESS\n\t) {\n\t\thal_data->txpwr_by_rate_from_file = 1;\n\t\tgoto post_hdl;\n\t}\n#endif\n\n#ifdef CONFIG_EMBEDDED_FWIMG\n\tif (HAL_STATUS_SUCCESS == odm_config_bb_with_header_file(&hal_data->odmpriv, CONFIG_BB_PHY_REG_PG)) {\n\t\tRTW_INFO(\"default power by rate loaded\\n\");\n\t\thal_data->txpwr_by_rate_from_file = 0;\n\t\tgoto post_hdl;\n\t}\n#endif\n\n\tRTW_ERR(\"%s():Read Tx power by rate fail\\n\", __func__);\n\tgoto exit;\n\npost_hdl:\n\tif (hal_data->odmpriv.phy_reg_pg_value_type != PHY_REG_PG_EXACT_VALUE) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tPHY_TxPowerByRateConfiguration(adapter);\n\thal_data->txpwr_by_rate_loaded = 1;\n\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n\n#if CONFIG_TXPWR_LIMIT\nint phy_load_tx_power_limit(_adapter *adapter, u8 chk_file)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tint ret = _FAIL;\n\n\thal_data->txpwr_limit_loaded = 0;\n\trtw_regd_exc_list_free(rfctl);\n\trtw_txpwr_lmt_list_free(rfctl);\n\n\tif (!hal_data->txpwr_by_rate_loaded && regsty->target_tx_pwr_valid != _TRUE) {\n\t\tRTW_ERR(\"%s():Read Tx power limit before target tx power is specify\\n\", __func__);\n\t\tgoto exit;\n\t}\n\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\tif (chk_file\n\t\t&& PHY_ConfigRFWithPowerLimitTableParaFile(adapter, PHY_FILE_TXPWR_LMT) == _SUCCESS\n\t) {\n\t\thal_data->txpwr_limit_from_file = 1;\n\t\tgoto post_hdl;\n\t}\n#endif\n\n#ifdef CONFIG_EMBEDDED_FWIMG\n\tif (odm_config_rf_with_header_file(&hal_data->odmpriv, CONFIG_RF_TXPWR_LMT, RF_PATH_A) == HAL_STATUS_SUCCESS) {\n\t\tRTW_INFO(\"default power limit loaded\\n\");\n\t\thal_data->txpwr_limit_from_file = 0;\n\t\tgoto post_hdl;\n\t}\n#endif\n\n\tRTW_ERR(\"%s():Read Tx power limit fail\\n\", __func__);\n\tgoto exit;\n\npost_hdl:\n\tphy_txpwr_lmt_post_hdl(adapter);\n\trtw_txpwr_init_regd(rfctl);\n\thal_data->txpwr_limit_loaded = 1;\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n#endif /* CONFIG_TXPWR_LIMIT */\n\nvoid phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file)\n{\n\tstruct registry_priv *regsty = adapter_to_regsty(adapter);\n\n\t/* check registy target tx power */\n\tregsty->target_tx_pwr_valid = rtw_regsty_chk_target_tx_power_valid(adapter);\n\n\t/* power by rate and limit */\n\tif (phy_is_tx_power_by_rate_needed(adapter)\n\t\t|| (phy_is_tx_power_limit_needed(adapter) && regsty->target_tx_pwr_valid != _TRUE)\n\t)\n\t\tphy_load_tx_power_by_rate(adapter, chk_file);\n\n#if CONFIG_TXPWR_LIMIT\n\tif (phy_is_tx_power_limit_needed(adapter))\n\t\tphy_load_tx_power_limit(adapter, chk_file);\n#endif\n}\n\ninline void phy_reload_tx_power_ext_info(_adapter *adapter)\n{\n\tphy_load_tx_power_ext_info(adapter, 1);\n}\n\ninline void phy_reload_default_tx_power_ext_info(_adapter *adapter)\n{\n\tphy_load_tx_power_ext_info(adapter, 0);\n}\n\nvoid dump_tx_power_ext_info(void *sel, _adapter *adapter)\n{\n\tstruct registry_priv *regsty = adapter_to_regsty(adapter);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\n\tif (regsty->target_tx_pwr_valid == _TRUE)\n\t\tRTW_PRINT_SEL(sel, \"target_tx_power: from registry\\n\");\n\telse if (phy_is_tx_power_by_rate_needed(adapter))\n\t\tRTW_PRINT_SEL(sel, \"target_tx_power: from power by rate\\n\");\n\telse\n\t\tRTW_PRINT_SEL(sel, \"target_tx_power: unavailable\\n\");\n\n\tRTW_PRINT_SEL(sel, \"tx_power_by_rate: %s, %s, %s\\n\"\n\t\t, phy_is_tx_power_by_rate_needed(adapter) ? \"enabled\" : \"disabled\"\n\t\t, hal_data->txpwr_by_rate_loaded ? \"loaded\" : \"unloaded\"\n\t\t, hal_data->txpwr_by_rate_from_file ? \"file\" : \"default\"\n\t);\n\n\tRTW_PRINT_SEL(sel, \"tx_power_limit: %s, %s, %s\\n\"\n\t\t, phy_is_tx_power_limit_needed(adapter) ? \"enabled\" : \"disabled\"\n\t\t, hal_data->txpwr_limit_loaded ? \"loaded\" : \"unloaded\"\n\t\t, hal_data->txpwr_limit_from_file ? \"file\" : \"default\"\n\t);\n}\n\nvoid dump_target_tx_power(void *sel, _adapter *adapter)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct registry_priv *regsty = adapter_to_regsty(adapter);\n\tint path, tx_num, band, rs;\n\tu8 target;\n\n\tfor (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {\n\t\tif (!hal_is_band_support(adapter, band))\n\t\t\tcontinue;\n\n\t\tfor (path = 0; path < RF_PATH_MAX; path++) {\n\t\t\tif (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))\n\t\t\t\tbreak;\n\n\t\t\tRTW_PRINT_SEL(sel, \"[%s][%c]%s\\n\", band_str(band), rf_path_char(path)\n\t\t\t\t, (regsty->target_tx_pwr_valid == _FALSE && hal_data->txpwr_by_rate_undefined_band_path[band][path]) ? \"(dup)\" : \"\");\n\n\t\t\tfor (rs = 0; rs < RATE_SECTION_NUM; rs++) {\n\t\t\t\ttx_num = rate_section_to_tx_num(rs);\n\t\t\t\tif (tx_num >= hal_spec->tx_nss_num)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))\n\t\t\t\t\tcontinue;\n\n\t\t\t\ttarget = PHY_GetTxPowerByRateBase(adapter, band, path, rs);\n\n\t\t\t\tif (target % hal_spec->txgi_pdbm) {\n\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%7s: %2d.%d\\n\", rate_section_str(rs)\n\t\t\t\t\t\t, target / hal_spec->txgi_pdbm, (target % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);\n\t\t\t\t} else {\n\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%7s: %5d\\n\", rate_section_str(rs)\n\t\t\t\t\t\t, target / hal_spec->txgi_pdbm);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\treturn;\n}\n\nvoid dump_tx_power_by_rate(void *sel, _adapter *adapter)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tint path, tx_num, band, n, rs;\n\tu8 rate_num, max_rate_num, base;\n\ts8 by_rate_offset;\n\n\tfor (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {\n\t\tif (!hal_is_band_support(adapter, band))\n\t\t\tcontinue;\n\n\t\tfor (path = 0; path < RF_PATH_MAX; path++) {\n\t\t\tif (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))\n\t\t\t\tbreak;\n\n\t\t\tRTW_PRINT_SEL(sel, \"[%s][%c]%s\\n\", band_str(band), rf_path_char(path)\n\t\t\t\t, hal_data->txpwr_by_rate_undefined_band_path[band][path] ? \"(dup)\" : \"\");\n\n\t\t\tfor (rs = 0; rs < RATE_SECTION_NUM; rs++) {\n\t\t\t\ttx_num = rate_section_to_tx_num(rs);\n\t\t\t\tif (tx_num >= hal_spec->tx_nss_num)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))\n\t\t\t\t\tmax_rate_num = 10;\n\t\t\t\telse\n\t\t\t\t\tmax_rate_num = 8;\n\t\t\t\trate_num = rate_section_rate_num(rs);\n\t\t\t\tbase = PHY_GetTxPowerByRateBase(adapter, band, path, rs);\n\n\t\t\t\tRTW_PRINT_SEL(sel, \"%7s: \", rate_section_str(rs));\n\n\t\t\t\t/* dump power by rate in db */\n\t\t\t\tfor (n = rate_num - 1; n >= 0; n--) {\n\t\t\t\t\tby_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, rates_by_sections[rs].rates[n]);\n\n\t\t\t\t\tif ((base + by_rate_offset) % hal_spec->txgi_pdbm) {\n\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%2d.%d \", (base + by_rate_offset) / hal_spec->txgi_pdbm\n\t\t\t\t\t\t\t, ((base + by_rate_offset) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);\n\t\t\t\t\t} else\n\t\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%5d \", (base + by_rate_offset) / hal_spec->txgi_pdbm);\n\t\t\t\t}\n\t\t\t\tfor (n = 0; n < max_rate_num - rate_num; n++)\n\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%5s \", \"\");\n\n\t\t\t\t_RTW_PRINT_SEL(sel, \"|\");\n\n\t\t\t\t/* dump power by rate in offset */\n\t\t\t\tfor (n = rate_num - 1; n >= 0; n--) {\n\t\t\t\t\tby_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, rates_by_sections[rs].rates[n]);\n\t\t\t\t\t_RTW_PRINT_SEL(sel, \"%3d \", by_rate_offset);\n\t\t\t\t}\n\t\t\t\tRTW_PRINT_SEL(sel, \"\\n\");\n\n\t\t\t}\n\t\t}\n\t}\n}\n\n/*\n * phy file path is stored in global char array rtw_phy_para_file_path\n * need to care about racing\n */\nint rtw_get_phy_file_path(_adapter *adapter, const char *file_name)\n{\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tint len = 0;\n\n\tif (file_name) {\n\t\tlen += snprintf(rtw_phy_para_file_path, PATH_LENGTH_MAX, \"%s\", rtw_phy_file_path);\n\t\t#if defined(CONFIG_MULTIDRV) || defined(REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER)\n\t\tlen += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, \"%s/\", hal_spec->ic_name);\n\t\t#endif\n\t\tlen += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, \"%s\", file_name);\n\n\t\treturn _TRUE;\n\t}\n#endif\n\treturn _FALSE;\n}\n\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\nint\nphy_ConfigMACWithParaFile(\n\t\tPADAPTER\tAdapter,\n\t\tchar\t\t*pFileName\n)\n{\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(Adapter);\n\tint\trlen = 0, rtStatus = _FAIL;\n\tchar\t*szLine, *ptmp;\n\tu32\tu4bRegOffset, u4bRegValue, u4bMove;\n\n\tif (!(Adapter->registrypriv.load_phy_file & LOAD_MAC_PARA_FILE))\n\t\treturn rtStatus;\n\n\t_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);\n\n\tif ((pHalData->mac_reg_len == 0) && (pHalData->mac_reg == NULL)) {\n\t\trtw_get_phy_file_path(Adapter, pFileName);\n\t\tif (rtw_readable_file_sz_chk(rtw_phy_para_file_path, \n\t\t\tMAX_PARA_FILE_BUF_LEN) == _TRUE) {\n\t\t\trlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);\n\t\t\tif (rlen > 0) {\n\t\t\t\trtStatus = _SUCCESS;\n\t\t\t\tpHalData->mac_reg = rtw_zvmalloc(rlen);\n\t\t\t\tif (pHalData->mac_reg) {\n\t\t\t\t\t_rtw_memcpy(pHalData->mac_reg, pHalData->para_file_buf, rlen);\n\t\t\t\t\tpHalData->mac_reg_len = rlen;\n\t\t\t\t} else\n\t\t\t\t\tRTW_INFO(\"%s mac_reg alloc fail !\\n\", __FUNCTION__);\n\t\t\t}\n\t\t}\n\t} else {\n\t\tif ((pHalData->mac_reg_len != 0) && (pHalData->mac_reg != NULL)) {\n\t\t\t_rtw_memcpy(pHalData->para_file_buf, pHalData->mac_reg, pHalData->mac_reg_len);\n\t\t\trtStatus = _SUCCESS;\n\t\t} else\n\t\t\tRTW_INFO(\"%s(): Critical Error !!!\\n\", __FUNCTION__);\n\t}\n\n\tif (rtStatus == _SUCCESS) {\n\t\tptmp = pHalData->para_file_buf;\n\t\tfor (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {\n\t\t\tif (!IsCommentString(szLine)) {\n\t\t\t\t/* Get 1st hex value as register offset */\n\t\t\t\tif (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {\n\t\t\t\t\tif (u4bRegOffset == 0xffff) {\n\t\t\t\t\t\t/* Ending. */\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\n\t\t\t\t\t/* Get 2nd hex value as register value. */\n\t\t\t\t\tszLine += u4bMove;\n\t\t\t\t\tif (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove))\n\t\t\t\t\t\trtw_write8(Adapter, u4bRegOffset, (u8)u4bRegValue);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else\n\t\tRTW_INFO(\"%s(): No File %s, Load from HWImg Array!\\n\", __FUNCTION__, pFileName);\n\n\treturn rtStatus;\n}\n\nint\nphy_ConfigBBWithParaFile(\n\t\tPADAPTER\tAdapter,\n\t\tchar\t\t*pFileName,\n\t\tu32\t\t\tConfigType\n)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(Adapter);\n\tint\trlen = 0, rtStatus = _FAIL;\n\tchar\t*szLine, *ptmp;\n\tu32\tu4bRegOffset, u4bRegValue, u4bMove;\n\tchar\t*pBuf = NULL;\n\tu32\t*pBufLen = NULL;\n\n\tif (!(Adapter->registrypriv.load_phy_file & LOAD_BB_PARA_FILE))\n\t\treturn rtStatus;\n\n\tswitch (ConfigType) {\n\tcase CONFIG_BB_PHY_REG:\n\t\tpBuf = pHalData->bb_phy_reg;\n\t\tpBufLen = &pHalData->bb_phy_reg_len;\n\t\tbreak;\n\tcase CONFIG_BB_AGC_TAB:\n\t\tpBuf = pHalData->bb_agc_tab;\n\t\tpBufLen = &pHalData->bb_agc_tab_len;\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(\"Unknown ConfigType!! %d\\r\\n\", ConfigType);\n\t\tbreak;\n\t}\n\n\t_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);\n\n\tif ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) {\n\t\trtw_get_phy_file_path(Adapter, pFileName);\n\t\tif (rtw_readable_file_sz_chk(rtw_phy_para_file_path, \n\t\t\tMAX_PARA_FILE_BUF_LEN) == _TRUE) {\n\t\t\trlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);\n\t\t\tif (rlen > 0) {\n\t\t\t\trtStatus = _SUCCESS;\n\t\t\t\tpBuf = rtw_zvmalloc(rlen);\n\t\t\t\tif (pBuf) {\n\t\t\t\t\t_rtw_memcpy(pBuf, pHalData->para_file_buf, rlen);\n\t\t\t\t\t*pBufLen = rlen;\n\n\t\t\t\t\tswitch (ConfigType) {\n\t\t\t\t\tcase CONFIG_BB_PHY_REG:\n\t\t\t\t\t\tpHalData->bb_phy_reg = pBuf;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase CONFIG_BB_AGC_TAB:\n\t\t\t\t\t\tpHalData->bb_agc_tab = pBuf;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t} else\n\t\t\t\t\tRTW_INFO(\"%s(): ConfigType %d  alloc fail !\\n\", __FUNCTION__, ConfigType);\n\t\t\t}\n\t\t}\n\t} else {\n\t\tif ((pBufLen != NULL) && (*pBufLen != 0) && (pBuf != NULL)) {\n\t\t\t_rtw_memcpy(pHalData->para_file_buf, pBuf, *pBufLen);\n\t\t\trtStatus = _SUCCESS;\n\t\t} else\n\t\t\tRTW_INFO(\"%s(): Critical Error !!!\\n\", __FUNCTION__);\n\t}\n\n\tif (rtStatus == _SUCCESS) {\n\t\tptmp = pHalData->para_file_buf;\n\t\tfor (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {\n\t\t\tif (!IsCommentString(szLine)) {\n\t\t\t\t/* Get 1st hex value as register offset. */\n\t\t\t\tif (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {\n\t\t\t\t\tif (u4bRegOffset == 0xffff) {\n\t\t\t\t\t\t/* Ending. */\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t} else if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {\n#ifdef CONFIG_LONG_DELAY_ISSUE\n\t\t\t\t\t\trtw_msleep_os(50);\n#else\n\t\t\t\t\t\trtw_mdelay_os(50);\n#endif\n\t\t\t\t\t} else if (u4bRegOffset == 0xfd)\n\t\t\t\t\t\trtw_mdelay_os(5);\n\t\t\t\t\telse if (u4bRegOffset == 0xfc)\n\t\t\t\t\t\trtw_mdelay_os(1);\n\t\t\t\t\telse if (u4bRegOffset == 0xfb)\n\t\t\t\t\t\trtw_udelay_os(50);\n\t\t\t\t\telse if (u4bRegOffset == 0xfa)\n\t\t\t\t\t\trtw_udelay_os(5);\n\t\t\t\t\telse if (u4bRegOffset == 0xf9)\n\t\t\t\t\t\trtw_udelay_os(1);\n\n\t\t\t\t\t/* Get 2nd hex value as register value. */\n\t\t\t\t\tszLine += u4bMove;\n\t\t\t\t\tif (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {\n\t\t\t\t\t\t/* RTW_INFO(\"[BB-ADDR]%03lX=%08lX\\n\", u4bRegOffset, u4bRegValue); */\n\t\t\t\t\t\tphy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);\n\n\t\t\t\t\t\tif (u4bRegOffset == 0xa24)\n\t\t\t\t\t\t\tpHalData->odmpriv.rf_calibrate_info.rega24 = u4bRegValue;\n\n\t\t\t\t\t\t/* Add 1us delay between BB/RF register setting. */\n\t\t\t\t\t\trtw_udelay_os(1);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else\n\t\tRTW_INFO(\"%s(): No File %s, Load from HWImg Array!\\n\", __FUNCTION__, pFileName);\n\n\treturn rtStatus;\n}\n\nvoid\nphy_DecryptBBPgParaFile(\n\tPADAPTER\t\tAdapter,\n\tchar\t\t\t*buffer\n)\n{\n\tu32\ti = 0, j = 0;\n\tu8\tmap[95] = {0};\n\tu8\tcurrentChar;\n\tchar\t*BufOfLines, *ptmp;\n\n\t/* RTW_INFO(\"=====>phy_DecryptBBPgParaFile()\\n\"); */\n\t/* 32 the ascii code of the first visable char, 126 the last one */\n\tfor (i = 0; i < 95; ++i)\n\t\tmap[i] = (u8)(94 - i);\n\n\tptmp = buffer;\n\ti = 0;\n\tfor (BufOfLines = GetLineFromBuffer(ptmp); BufOfLines != NULL; BufOfLines = GetLineFromBuffer(ptmp)) {\n\t\t/* RTW_INFO(\"Encrypted Line: %s\\n\", BufOfLines); */\n\n\t\tfor (j = 0; j < strlen(BufOfLines); ++j) {\n\t\t\tcurrentChar = BufOfLines[j];\n\n\t\t\tif (currentChar == '\\0')\n\t\t\t\tbreak;\n\n\t\t\tcurrentChar -= (u8)((((i + j) * 3) % 128));\n\n\t\t\tBufOfLines[j] = map[currentChar - 32] + 32;\n\t\t}\n\t\t/* RTW_INFO(\"Decrypted Line: %s\\n\", BufOfLines ); */\n\t\tif (strlen(BufOfLines) != 0)\n\t\t\ti++;\n\t\tBufOfLines[strlen(BufOfLines)] = '\\n';\n\t}\n}\n\n#ifndef DBG_TXPWR_BY_RATE_FILE_PARSE\n#define DBG_TXPWR_BY_RATE_FILE_PARSE 0\n#endif\n\nint\nphy_ParseBBPgParaFile(\n\tPADAPTER\t\tAdapter,\n\tchar\t\t\t*buffer\n)\n{\n\tint\trtStatus = _FAIL;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(Adapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);\n\tchar\t*szLine, *ptmp;\n\tu32\tu4bRegOffset, u4bRegMask, u4bRegValue;\n\tu32\tu4bMove;\n\tBOOLEAN firstLine = _TRUE;\n\tu8\ttx_num = 0;\n\tu8\tband = 0, rf_path = 0;\n\n\tif (Adapter->registrypriv.RegDecryptCustomFile == 1)\n\t\tphy_DecryptBBPgParaFile(Adapter, buffer);\n\n\tptmp = buffer;\n\tfor (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {\n\t\tif (isAllSpaceOrTab(szLine, sizeof(*szLine)))\n\t\t\tcontinue;\n\n\t\tif (!IsCommentString(szLine)) {\n\t\t\t/* Get header info (relative value or exact value) */\n\t\t\tif (firstLine) {\n\t\t\t\tif (eqNByte(szLine, (u8 *)(\"#[v1]\"), 5)\n\t\t\t\t\t|| eqNByte(szLine, (u8 *)(\"#[v2]\"), 5))\n\t\t\t\t\tpHalData->odmpriv.phy_reg_pg_version = szLine[3] - '0';\n\t\t\t\telse {\n\t\t\t\t\tRTW_ERR(\"The format in PHY_REG_PG are invalid %s\\n\", szLine);\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\n\t\t\t\tif (eqNByte(szLine + 5, (u8 *)(\"[Exact]#\"), 8)) {\n\t\t\t\t\tpHalData->odmpriv.phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;\n\t\t\t\t\tfirstLine = _FALSE;\n\t\t\t\t\tcontinue;\n\t\t\t\t} else {\n\t\t\t\t\tRTW_ERR(\"The values in PHY_REG_PG are invalid %s\\n\", szLine);\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (pHalData->odmpriv.phy_reg_pg_version > 0) {\n\t\t\t\tu32\tindex = 0, cnt = 0;\n\n\t\t\t\tif (eqNByte(szLine, \"0xffff\", 6))\n\t\t\t\t\tbreak;\n\n\t\t\t\tif (!eqNByte(\"#[END]#\", szLine, 7)) {\n\t\t\t\t\t/* load the table label info */\n\t\t\t\t\tif (szLine[0] == '#') {\n\t\t\t\t\t\tindex = 0;\n\t\t\t\t\t\tif (eqNByte(szLine, \"#[2.4G]\" , 7)) {\n\t\t\t\t\t\t\tband = BAND_ON_2_4G;\n\t\t\t\t\t\t\tindex += 8;\n\t\t\t\t\t\t} else if (eqNByte(szLine, \"#[5G]\", 5)) {\n\t\t\t\t\t\t\tband = BAND_ON_5G;\n\t\t\t\t\t\t\tindex += 6;\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tRTW_ERR(\"Invalid band %s in PHY_REG_PG.txt\\n\", szLine);\n\t\t\t\t\t\t\tgoto exit;\n\t\t\t\t\t\t}\n\n\t\t\t\t\t\trf_path = szLine[index] - 'A';\n\t\t\t\t\t\tif (DBG_TXPWR_BY_RATE_FILE_PARSE)\n\t\t\t\t\t\t\tRTW_INFO(\" Table label Band %d, RfPath %d\\n\", band, rf_path );\n\t\t\t\t\t} else { /* load rows of tables */\n\t\t\t\t\t\tif (szLine[1] == '1')\n\t\t\t\t\t\t\ttx_num = RF_1TX;\n\t\t\t\t\t\telse if (szLine[1] == '2')\n\t\t\t\t\t\t\ttx_num = RF_2TX;\n\t\t\t\t\t\telse if (szLine[1] == '3')\n\t\t\t\t\t\t\ttx_num = RF_3TX;\n\t\t\t\t\t\telse if (szLine[1] == '4')\n\t\t\t\t\t\t\ttx_num = RF_4TX;\n\t\t\t\t\t\telse {\n\t\t\t\t\t\t\tRTW_ERR(\"Invalid row in PHY_REG_PG.txt '%c'(%d)\\n\", szLine[1], szLine[1]);\n\t\t\t\t\t\t\tgoto exit;\n\t\t\t\t\t\t}\n\n\t\t\t\t\t\twhile (szLine[index] != ']')\n\t\t\t\t\t\t\t++index;\n\t\t\t\t\t\t++index;/* skip ] */\n\n\t\t\t\t\t\t/* Get 2nd hex value as register offset. */\n\t\t\t\t\t\tszLine += index;\n\t\t\t\t\t\tif (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove))\n\t\t\t\t\t\t\tszLine += u4bMove;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tgoto exit;\n\n\t\t\t\t\t\t/* Get 2nd hex value as register mask. */\n\t\t\t\t\t\tif (GetHexValueFromString(szLine, &u4bRegMask, &u4bMove))\n\t\t\t\t\t\t\tszLine += u4bMove;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tgoto exit;\n\n\t\t\t\t\t\tif (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_EXACT_VALUE) {\n\t\t\t\t\t\t\tu32\tcombineValue = 0;\n\t\t\t\t\t\t\tu8\tinteger = 0, fraction = 0;\n\n\t\t\t\t\t\t\tif (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))\n\t\t\t\t\t\t\t\tszLine += u4bMove;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tgoto exit;\n\n\t\t\t\t\t\t\tinteger *= hal_spec->txgi_pdbm;\n\t\t\t\t\t\t\tinteger += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;\n\t\t\t\t\t\t\tif (pHalData->odmpriv.phy_reg_pg_version == 1)\n\t\t\t\t\t\t\t\tcombineValue |= (((integer / 10) << 4) + (integer % 10));\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tcombineValue |= integer;\n\n\t\t\t\t\t\t\tif (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))\n\t\t\t\t\t\t\t\tszLine += u4bMove;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tgoto exit;\n\n\t\t\t\t\t\t\tinteger *= hal_spec->txgi_pdbm;\n\t\t\t\t\t\t\tinteger += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;\n\t\t\t\t\t\t\tcombineValue <<= 8;\n\t\t\t\t\t\t\tif (pHalData->odmpriv.phy_reg_pg_version == 1)\n\t\t\t\t\t\t\t\tcombineValue |= (((integer / 10) << 4) + (integer % 10));\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tcombineValue |= integer;\n\n\t\t\t\t\t\t\tif (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))\n\t\t\t\t\t\t\t\tszLine += u4bMove;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tgoto exit;\n\n\t\t\t\t\t\t\tinteger *= hal_spec->txgi_pdbm;\n\t\t\t\t\t\t\tinteger += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;\n\t\t\t\t\t\t\tcombineValue <<= 8;\n\t\t\t\t\t\t\tif (pHalData->odmpriv.phy_reg_pg_version == 1)\n\t\t\t\t\t\t\t\tcombineValue |= (((integer / 10) << 4) + (integer % 10));\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tcombineValue |= integer;\n\n\t\t\t\t\t\t\tif (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))\n\t\t\t\t\t\t\t\tszLine += u4bMove;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tgoto exit;\n\n\t\t\t\t\t\t\tinteger *= hal_spec->txgi_pdbm;\n\t\t\t\t\t\t\tinteger += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;\n\t\t\t\t\t\t\tcombineValue <<= 8;\n\t\t\t\t\t\t\tif (pHalData->odmpriv.phy_reg_pg_version == 1)\n\t\t\t\t\t\t\t\tcombineValue |= (((integer / 10) << 4) + (integer % 10));\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tcombineValue |= integer;\n\n\t\t\t\t\t\t\tphy_store_tx_power_by_rate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, combineValue);\n\n\t\t\t\t\t\t\tif (DBG_TXPWR_BY_RATE_FILE_PARSE)\n\t\t\t\t\t\t\t\tRTW_INFO(\"addr:0x%3x mask:0x%08x %dTx = 0x%08x\\n\", u4bRegOffset, u4bRegMask, tx_num + 1, combineValue);\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\trtStatus = _SUCCESS;\n\nexit:\n\tRTW_INFO(\"%s return %d\\n\", __func__, rtStatus);\n\treturn rtStatus;\n}\n\nint\nphy_ConfigBBWithPgParaFile(\n\t\tPADAPTER\tAdapter,\n\t\tconst char\t*pFileName)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(Adapter);\n\tint\trlen = 0, rtStatus = _FAIL;\n\n\tif (!(Adapter->registrypriv.load_phy_file & LOAD_BB_PG_PARA_FILE))\n\t\treturn rtStatus;\n\n\t_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);\n\n\tif (pHalData->bb_phy_reg_pg == NULL) {\n\t\trtw_get_phy_file_path(Adapter, pFileName);\n\t\tif (rtw_readable_file_sz_chk(rtw_phy_para_file_path, \n\t\t\tMAX_PARA_FILE_BUF_LEN) == _TRUE) {\n\t\t\trlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);\n\t\t\tif (rlen > 0) {\n\t\t\t\trtStatus = _SUCCESS;\n\t\t\t\tpHalData->bb_phy_reg_pg = rtw_zvmalloc(rlen);\n\t\t\t\tif (pHalData->bb_phy_reg_pg) {\n\t\t\t\t\t_rtw_memcpy(pHalData->bb_phy_reg_pg, pHalData->para_file_buf, rlen);\n\t\t\t\t\tpHalData->bb_phy_reg_pg_len = rlen;\n\t\t\t\t} else\n\t\t\t\t\tRTW_INFO(\"%s bb_phy_reg_pg alloc fail !\\n\", __FUNCTION__);\n\t\t\t}\n\t\t}\n\t} else {\n\t\tif ((pHalData->bb_phy_reg_pg_len != 0) && (pHalData->bb_phy_reg_pg != NULL)) {\n\t\t\t_rtw_memcpy(pHalData->para_file_buf, pHalData->bb_phy_reg_pg, pHalData->bb_phy_reg_pg_len);\n\t\t\trtStatus = _SUCCESS;\n\t\t} else\n\t\t\tRTW_INFO(\"%s(): Critical Error !!!\\n\", __FUNCTION__);\n\t}\n\n\tif (rtStatus == _SUCCESS) {\n\t\t/* RTW_INFO(\"phy_ConfigBBWithPgParaFile(): read %s ok\\n\", pFileName); */\n\t\trtStatus = phy_ParseBBPgParaFile(Adapter, pHalData->para_file_buf);\n\t} else\n\t\tRTW_INFO(\"%s(): No File %s, Load from HWImg Array!\\n\", __FUNCTION__, pFileName);\n\n\treturn rtStatus;\n}\n\n#if (MP_DRIVER == 1)\n\nint\nphy_ConfigBBWithMpParaFile(\n\t\tPADAPTER\tAdapter,\n\t\tchar\t\t*pFileName\n)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(Adapter);\n\tint\trlen = 0, rtStatus = _FAIL;\n\tchar\t*szLine, *ptmp;\n\tu32\tu4bRegOffset, u4bRegValue, u4bMove;\n\n\tif (!(Adapter->registrypriv.load_phy_file & LOAD_BB_MP_PARA_FILE))\n\t\treturn rtStatus;\n\n\t_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);\n\n\tif ((pHalData->bb_phy_reg_mp_len == 0) && (pHalData->bb_phy_reg_mp == NULL)) {\n\t\trtw_get_phy_file_path(Adapter, pFileName);\n\t\tif (rtw_readable_file_sz_chk(rtw_phy_para_file_path, \n\t\t\tMAX_PARA_FILE_BUF_LEN) == _TRUE) {\n\t\t\trlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);\n\t\t\tif (rlen > 0) {\n\t\t\t\trtStatus = _SUCCESS;\n\t\t\t\tpHalData->bb_phy_reg_mp = rtw_zvmalloc(rlen);\n\t\t\t\tif (pHalData->bb_phy_reg_mp) {\n\t\t\t\t\t_rtw_memcpy(pHalData->bb_phy_reg_mp, pHalData->para_file_buf, rlen);\n\t\t\t\t\tpHalData->bb_phy_reg_mp_len = rlen;\n\t\t\t\t} else\n\t\t\t\t\tRTW_INFO(\"%s bb_phy_reg_mp alloc fail !\\n\", __FUNCTION__);\n\t\t\t}\n\t\t}\n\t} else {\n\t\tif ((pHalData->bb_phy_reg_mp_len != 0) && (pHalData->bb_phy_reg_mp != NULL)) {\n\t\t\t_rtw_memcpy(pHalData->para_file_buf, pHalData->bb_phy_reg_mp, pHalData->bb_phy_reg_mp_len);\n\t\t\trtStatus = _SUCCESS;\n\t\t} else\n\t\t\tRTW_INFO(\"%s(): Critical Error !!!\\n\", __FUNCTION__);\n\t}\n\n\tif (rtStatus == _SUCCESS) {\n\t\t/* RTW_INFO(\"phy_ConfigBBWithMpParaFile(): read %s ok\\n\", pFileName); */\n\n\t\tptmp = pHalData->para_file_buf;\n\t\tfor (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {\n\t\t\tif (!IsCommentString(szLine)) {\n\t\t\t\t/* Get 1st hex value as register offset. */\n\t\t\t\tif (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {\n\t\t\t\t\tif (u4bRegOffset == 0xffff) {\n\t\t\t\t\t\t/* Ending. */\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t} else if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {\n#ifdef CONFIG_LONG_DELAY_ISSUE\n\t\t\t\t\t\trtw_msleep_os(50);\n#else\n\t\t\t\t\t\trtw_mdelay_os(50);\n#endif\n\t\t\t\t\t} else if (u4bRegOffset == 0xfd)\n\t\t\t\t\t\trtw_mdelay_os(5);\n\t\t\t\t\telse if (u4bRegOffset == 0xfc)\n\t\t\t\t\t\trtw_mdelay_os(1);\n\t\t\t\t\telse if (u4bRegOffset == 0xfb)\n\t\t\t\t\t\trtw_udelay_os(50);\n\t\t\t\t\telse if (u4bRegOffset == 0xfa)\n\t\t\t\t\t\trtw_udelay_os(5);\n\t\t\t\t\telse if (u4bRegOffset == 0xf9)\n\t\t\t\t\t\trtw_udelay_os(1);\n\n\t\t\t\t\t/* Get 2nd hex value as register value. */\n\t\t\t\t\tszLine += u4bMove;\n\t\t\t\t\tif (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {\n\t\t\t\t\t\t/* RTW_INFO(\"[ADDR]%03lX=%08lX\\n\", u4bRegOffset, u4bRegValue); */\n\t\t\t\t\t\tphy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);\n\n\t\t\t\t\t\t/* Add 1us delay between BB/RF register setting. */\n\t\t\t\t\t\trtw_udelay_os(1);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else\n\t\tRTW_INFO(\"%s(): No File %s, Load from HWImg Array!\\n\", __FUNCTION__, pFileName);\n\n\treturn rtStatus;\n}\n\n#endif\n\nint\nPHY_ConfigRFWithParaFile(\n\t\tPADAPTER\tAdapter,\n\t\tchar\t\t*pFileName,\n\t\tenum rf_path\t\teRFPath\n)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(Adapter);\n\tint\trlen = 0, rtStatus = _FAIL;\n\tchar\t*szLine, *ptmp;\n\tu32\tu4bRegOffset, u4bRegValue, u4bMove;\n\tu16\ti;\n\tchar\t*pBuf = NULL;\n\tu32\t*pBufLen = NULL;\n\n\tif (!(Adapter->registrypriv.load_phy_file & LOAD_RF_PARA_FILE))\n\t\treturn rtStatus;\n\n\tswitch (eRFPath) {\n\tcase RF_PATH_A:\n\t\tpBuf = pHalData->rf_radio_a;\n\t\tpBufLen = &pHalData->rf_radio_a_len;\n\t\tbreak;\n\tcase RF_PATH_B:\n\t\tpBuf = pHalData->rf_radio_b;\n\t\tpBufLen = &pHalData->rf_radio_b_len;\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(\"Unknown RF path!! %d\\r\\n\", eRFPath);\n\t\tbreak;\n\t}\n\n\t_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);\n\n\tif ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) {\n\t\trtw_get_phy_file_path(Adapter, pFileName);\n\t\tif (rtw_readable_file_sz_chk(rtw_phy_para_file_path, \n\t\t\tMAX_PARA_FILE_BUF_LEN) == _TRUE) {\n\t\t\trlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);\n\t\t\tif (rlen > 0) {\n\t\t\t\trtStatus = _SUCCESS;\n\t\t\t\tpBuf = rtw_zvmalloc(rlen);\n\t\t\t\tif (pBuf) {\n\t\t\t\t\t_rtw_memcpy(pBuf, pHalData->para_file_buf, rlen);\n\t\t\t\t\t*pBufLen = rlen;\n\n\t\t\t\t\tswitch (eRFPath) {\n\t\t\t\t\tcase RF_PATH_A:\n\t\t\t\t\t\tpHalData->rf_radio_a = pBuf;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase RF_PATH_B:\n\t\t\t\t\t\tpHalData->rf_radio_b = pBuf;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tdefault:\n\t\t\t\t\t\tRTW_INFO(\"Unknown RF path!! %d\\r\\n\", eRFPath);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t} else\n\t\t\t\t\tRTW_INFO(\"%s(): eRFPath=%d  alloc fail !\\n\", __FUNCTION__, eRFPath);\n\t\t\t}\n\t\t}\n\t} else {\n\t\tif ((pBufLen != NULL) && (*pBufLen != 0) && (pBuf != NULL)) {\n\t\t\t_rtw_memcpy(pHalData->para_file_buf, pBuf, *pBufLen);\n\t\t\trtStatus = _SUCCESS;\n\t\t} else\n\t\t\tRTW_INFO(\"%s(): Critical Error !!!\\n\", __FUNCTION__);\n\t}\n\n\tif (rtStatus == _SUCCESS) {\n\t\t/* RTW_INFO(\"%s(): read %s successfully\\n\", __FUNCTION__, pFileName); */\n\n\t\tptmp = pHalData->para_file_buf;\n\t\tfor (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {\n\t\t\tif (!IsCommentString(szLine)) {\n\t\t\t\t/* Get 1st hex value as register offset. */\n\t\t\t\tif (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {\n\t\t\t\t\tif (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {\n\t\t\t\t\t\t/* Deay specific ms. Only RF configuration require delay.\t\t\t\t\t\t\t\t\t\t\t\t */\n#ifdef CONFIG_LONG_DELAY_ISSUE\n\t\t\t\t\t\trtw_msleep_os(50);\n#else\n\t\t\t\t\t\trtw_mdelay_os(50);\n#endif\n\t\t\t\t\t} else if (u4bRegOffset == 0xfd) {\n\t\t\t\t\t\t/* delay_ms(5); */\n\t\t\t\t\t\tfor (i = 0; i < 100; i++)\n\t\t\t\t\t\t\trtw_udelay_os(MAX_STALL_TIME);\n\t\t\t\t\t} else if (u4bRegOffset == 0xfc) {\n\t\t\t\t\t\t/* delay_ms(1); */\n\t\t\t\t\t\tfor (i = 0; i < 20; i++)\n\t\t\t\t\t\t\trtw_udelay_os(MAX_STALL_TIME);\n\t\t\t\t\t} else if (u4bRegOffset == 0xfb)\n\t\t\t\t\t\trtw_udelay_os(50);\n\t\t\t\t\telse if (u4bRegOffset == 0xfa)\n\t\t\t\t\t\trtw_udelay_os(5);\n\t\t\t\t\telse if (u4bRegOffset == 0xf9)\n\t\t\t\t\t\trtw_udelay_os(1);\n\t\t\t\t\telse if (u4bRegOffset == 0xffff)\n\t\t\t\t\t\tbreak;\n\n\t\t\t\t\t/* Get 2nd hex value as register value. */\n\t\t\t\t\tszLine += u4bMove;\n\t\t\t\t\tif (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {\n\t\t\t\t\t\tphy_set_rf_reg(Adapter, eRFPath, u4bRegOffset, bRFRegOffsetMask, u4bRegValue);\n\n\t\t\t\t\t\t/* Temp add, for frequency lock, if no delay, that may cause */\n\t\t\t\t\t\t/* frequency shift, ex: 2412MHz => 2417MHz */\n\t\t\t\t\t\t/* If frequency shift, the following action may works. */\n\t\t\t\t\t\t/* Fractional-N table in radio_a.txt */\n\t\t\t\t\t\t/* 0x2a 0x00001\t\t */ /* channel 1 */\n\t\t\t\t\t\t/* 0x2b 0x00808\t\tfrequency divider. */\n\t\t\t\t\t\t/* 0x2b 0x53333 */\n\t\t\t\t\t\t/* 0x2c 0x0000c */\n\t\t\t\t\t\trtw_udelay_os(1);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else\n\t\tRTW_INFO(\"%s(): No File %s, Load from HWImg Array!\\n\", __FUNCTION__, pFileName);\n\n\treturn rtStatus;\n}\n\nvoid\ninitDeltaSwingIndexTables(\n\tPADAPTER\tAdapter,\n\tchar\t\t*Band,\n\tchar\t\t*Path,\n\tchar\t\t*Sign,\n\tchar\t\t*Channel,\n\tchar\t\t*Rate,\n\tchar\t\t*Data\n)\n{\n#define STR_EQUAL_5G(_band, _path, _sign, _rate, _chnl) \\\n\t((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\\\n\t (strcmp(Rate, _rate) == 0) && (strcmp(Channel, _chnl) == 0)\\\n\t)\n#define STR_EQUAL_2G(_band, _path, _sign, _rate) \\\n\t((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\\\n\t (strcmp(Rate, _rate) == 0)\\\n\t)\n\n#define STORE_SWING_TABLE(_array, _iteratedIdx) \\\n\tdo {\t\\\n\tfor (token = strsep(&Data, delim); token != NULL; token = strsep(&Data, delim)) {\\\n\t\tsscanf(token, \"%d\", &idx);\\\n\t\t_array[_iteratedIdx++] = (u8)idx;\\\n\t} } while (0)\\\n\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(Adapter);\n\tstruct dm_struct\t\t*pDM_Odm = &pHalData->odmpriv;\n\tstruct dm_rf_calibration_struct\t*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);\n\tu32\tj = 0;\n\tchar\t*token;\n\tchar\tdelim[] = \",\";\n\tu32\tidx = 0;\n\n\t/* RTW_INFO(\"===>initDeltaSwingIndexTables(): Band: %s;\\nPath: %s;\\nSign: %s;\\nChannel: %s;\\nRate: %s;\\n, Data: %s;\\n\",  */\n\t/*\tBand, Path, Sign, Channel, Rate, Data); */\n\n\tif (STR_EQUAL_2G(\"2G\", \"A\", \"+\", \"CCK\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p, j);\n\telse if (STR_EQUAL_2G(\"2G\", \"A\", \"-\", \"CCK\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n, j);\n\telse if (STR_EQUAL_2G(\"2G\", \"B\", \"+\", \"CCK\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p, j);\n\telse if (STR_EQUAL_2G(\"2G\", \"B\", \"-\", \"CCK\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n, j);\n\telse if (STR_EQUAL_2G(\"2G\", \"A\", \"+\", \"ALL\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_p, j);\n\telse if (STR_EQUAL_2G(\"2G\", \"A\", \"-\", \"ALL\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_n, j);\n\telse if (STR_EQUAL_2G(\"2G\", \"B\", \"+\", \"ALL\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_p, j);\n\telse if (STR_EQUAL_2G(\"2G\", \"B\", \"-\", \"ALL\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_n, j);\n\telse if (STR_EQUAL_5G(\"5G\", \"A\", \"+\", \"ALL\", \"0\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[0], j);\n\telse if (STR_EQUAL_5G(\"5G\", \"A\", \"-\", \"ALL\", \"0\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[0], j);\n\telse if (STR_EQUAL_5G(\"5G\", \"B\", \"+\", \"ALL\", \"0\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[0], j);\n\telse if (STR_EQUAL_5G(\"5G\", \"B\", \"-\", \"ALL\", \"0\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[0], j);\n\telse if (STR_EQUAL_5G(\"5G\", \"A\", \"+\", \"ALL\", \"1\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[1], j);\n\telse if (STR_EQUAL_5G(\"5G\", \"A\", \"-\", \"ALL\", \"1\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[1], j);\n\telse if (STR_EQUAL_5G(\"5G\", \"B\", \"+\", \"ALL\", \"1\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[1], j);\n\telse if (STR_EQUAL_5G(\"5G\", \"B\", \"-\", \"ALL\", \"1\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[1], j);\n\telse if (STR_EQUAL_5G(\"5G\", \"A\", \"+\", \"ALL\", \"2\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[2], j);\n\telse if (STR_EQUAL_5G(\"5G\", \"A\", \"-\", \"ALL\", \"2\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[2], j);\n\telse if (STR_EQUAL_5G(\"5G\", \"B\", \"+\", \"ALL\", \"2\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[2], j);\n\telse if (STR_EQUAL_5G(\"5G\", \"B\", \"-\", \"ALL\", \"2\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[2], j);\n\telse if (STR_EQUAL_5G(\"5G\", \"A\", \"+\", \"ALL\", \"3\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[3], j);\n\telse if (STR_EQUAL_5G(\"5G\", \"A\", \"-\", \"ALL\", \"3\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[3], j);\n\telse if (STR_EQUAL_5G(\"5G\", \"B\", \"+\", \"ALL\", \"3\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[3], j);\n\telse if (STR_EQUAL_5G(\"5G\", \"B\", \"-\", \"ALL\", \"3\"))\n\t\tSTORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[3], j);\n\telse\n\t\tRTW_INFO(\"===>initDeltaSwingIndexTables(): The input is invalid!!\\n\");\n}\n\nint\nPHY_ConfigRFWithTxPwrTrackParaFile(\n\t\tPADAPTER\t\tAdapter,\n\t\tchar\t\t\t*pFileName\n)\n{\n\tHAL_DATA_TYPE\t\t*pHalData = GET_HAL_DATA(Adapter);\n\tstruct dm_struct\t\t\t*pDM_Odm = &pHalData->odmpriv;\n\tstruct dm_rf_calibration_struct\t\t*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);\n\tint\trlen = 0, rtStatus = _FAIL;\n\tchar\t*szLine, *ptmp;\n\tu32\ti = 0, j = 0;\n\tchar\tc = 0;\n\n\tif (!(Adapter->registrypriv.load_phy_file & LOAD_RF_TXPWR_TRACK_PARA_FILE))\n\t\treturn rtStatus;\n\n\t_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);\n\n\tif ((pHalData->rf_tx_pwr_track_len == 0) && (pHalData->rf_tx_pwr_track == NULL)) {\n\t\trtw_get_phy_file_path(Adapter, pFileName);\n\t\tif (rtw_readable_file_sz_chk(rtw_phy_para_file_path, \n\t\t\tMAX_PARA_FILE_BUF_LEN) == _TRUE) {\n\t\t\trlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);\n\t\t\tif (rlen > 0) {\n\t\t\t\trtStatus = _SUCCESS;\n\t\t\t\tpHalData->rf_tx_pwr_track = rtw_zvmalloc(rlen);\n\t\t\t\tif (pHalData->rf_tx_pwr_track) {\n\t\t\t\t\t_rtw_memcpy(pHalData->rf_tx_pwr_track, pHalData->para_file_buf, rlen);\n\t\t\t\t\tpHalData->rf_tx_pwr_track_len = rlen;\n\t\t\t\t} else\n\t\t\t\t\tRTW_INFO(\"%s rf_tx_pwr_track alloc fail !\\n\", __FUNCTION__);\n\t\t\t}\n\t\t}\n\t} else {\n\t\tif ((pHalData->rf_tx_pwr_track_len != 0) && (pHalData->rf_tx_pwr_track != NULL)) {\n\t\t\t_rtw_memcpy(pHalData->para_file_buf, pHalData->rf_tx_pwr_track, pHalData->rf_tx_pwr_track_len);\n\t\t\trtStatus = _SUCCESS;\n\t\t} else\n\t\t\tRTW_INFO(\"%s(): Critical Error !!!\\n\", __FUNCTION__);\n\t}\n\n\tif (rtStatus == _SUCCESS) {\n\t\t/* RTW_INFO(\"%s(): read %s successfully\\n\", __FUNCTION__, pFileName); */\n\n\t\tptmp = pHalData->para_file_buf;\n\t\tfor (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {\n\t\t\tif (!IsCommentString(szLine)) {\n\t\t\t\tchar\tband[5] = \"\", path[5] = \"\", sign[5]  = \"\";\n\t\t\t\tchar\tchnl[5] = \"\", rate[10] = \"\";\n\t\t\t\tchar\tdata[300] = \"\"; /* 100 is too small */\n\n\t\t\t\tif (strlen(szLine) < 10 || szLine[0] != '[')\n\t\t\t\t\tcontinue;\n\n\t\t\t\tstrncpy(band, szLine + 1, 2);\n\t\t\t\tstrncpy(path, szLine + 5, 1);\n\t\t\t\tstrncpy(sign, szLine + 8, 1);\n\n\t\t\t\ti = 10; /* szLine+10 */\n\t\t\t\tif (!ParseQualifiedString(szLine, &i, rate, '[', ']')) {\n\t\t\t\t\t/* RTW_INFO(\"Fail to parse rate!\\n\"); */\n\t\t\t\t}\n\t\t\t\tif (!ParseQualifiedString(szLine, &i, chnl, '[', ']')) {\n\t\t\t\t\t/* RTW_INFO(\"Fail to parse channel group!\\n\"); */\n\t\t\t\t}\n\t\t\t\twhile (szLine[i] != '{' && i < strlen(szLine))\n\t\t\t\t\ti++;\n\t\t\t\tif (!ParseQualifiedString(szLine, &i, data, '{', '}')) {\n\t\t\t\t\t/* RTW_INFO(\"Fail to parse data!\\n\"); */\n\t\t\t\t}\n\n\t\t\t\tinitDeltaSwingIndexTables(Adapter, band, path, sign, chnl, rate, data);\n\t\t\t}\n\t\t}\n\t} else\n\t\tRTW_INFO(\"%s(): No File %s, Load from HWImg Array!\\n\", __FUNCTION__, pFileName);\n#if 0\n\tfor (i = 0; i < DELTA_SWINGIDX_SIZE; ++i) {\n\t\tRTW_INFO(\"pRFCalibrateInfo->delta_swing_table_idx_2ga_p[%d] = %d\\n\", i, pRFCalibrateInfo->delta_swing_table_idx_2ga_p[i]);\n\t\tRTW_INFO(\"pRFCalibrateInfo->delta_swing_table_idx_2ga_n[%d] = %d\\n\", i, pRFCalibrateInfo->delta_swing_table_idx_2ga_n[i]);\n\t\tRTW_INFO(\"pRFCalibrateInfo->delta_swing_table_idx_2gb_p[%d] = %d\\n\", i, pRFCalibrateInfo->delta_swing_table_idx_2gb_p[i]);\n\t\tRTW_INFO(\"pRFCalibrateInfo->delta_swing_table_idx_2gb_n[%d] = %d\\n\", i, pRFCalibrateInfo->delta_swing_table_idx_2gb_n[i]);\n\t\tRTW_INFO(\"pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p[%d] = %d\\n\", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p[i]);\n\t\tRTW_INFO(\"pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n[%d] = %d\\n\", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n[i]);\n\t\tRTW_INFO(\"pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p[%d] = %d\\n\", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p[i]);\n\t\tRTW_INFO(\"pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n[%d] = %d\\n\", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n[i]);\n\n\t\tfor (j = 0; j < 3; ++j) {\n\t\t\tRTW_INFO(\"pRFCalibrateInfo->delta_swing_table_idx_5ga_p[%d][%d] = %d\\n\", j, i, pRFCalibrateInfo->delta_swing_table_idx_5ga_p[j][i]);\n\t\t\tRTW_INFO(\"pRFCalibrateInfo->delta_swing_table_idx_5ga_n[%d][%d] = %d\\n\", j, i, pRFCalibrateInfo->delta_swing_table_idx_5ga_n[j][i]);\n\t\t\tRTW_INFO(\"pRFCalibrateInfo->delta_swing_table_idx_5gb_p[%d][%d] = %d\\n\", j, i, pRFCalibrateInfo->delta_swing_table_idx_5gb_p[j][i]);\n\t\t\tRTW_INFO(\"pRFCalibrateInfo->delta_swing_table_idx_5gb_n[%d][%d] = %d\\n\", j, i, pRFCalibrateInfo->delta_swing_table_idx_5gb_n[j][i]);\n\t\t}\n\t}\n#endif\n\treturn rtStatus;\n}\n\n#if CONFIG_TXPWR_LIMIT\n\n#ifndef DBG_TXPWR_LMT_FILE_PARSE\n#define DBG_TXPWR_LMT_FILE_PARSE 0\n#endif\n\n#define PARSE_RET_NO_HDL\t0\n#define PARSE_RET_SUCCESS\t1\n#define PARSE_RET_FAIL\t\t2\n\n/*\n* @@Ver=2.0\n* or\n* @@DomainCode=0x28, Regulation=C6\n* or\n* @@CountryCode=GB, Regulation=C7\n*/\nstatic u8 parse_reg_exc_config(_adapter *adapter, char *szLine)\n{\n#define VER_PREFIX \"Ver=\"\n#define DOMAIN_PREFIX \"DomainCode=0x\"\n#define COUNTRY_PREFIX \"CountryCode=\"\n#define REG_PREFIX \"Regulation=\"\n\n\tconst u8 ver_prefix_len = strlen(VER_PREFIX);\n\tconst u8 domain_prefix_len = strlen(DOMAIN_PREFIX);\n\tconst u8 country_prefix_len = strlen(COUNTRY_PREFIX);\n\tconst u8 reg_prefix_len = strlen(REG_PREFIX);\n\tu32 i, i_val_s, i_val_e;\n\tu32 j;\n\tu8 domain = 0xFF;\n\tchar *country = NULL;\n\tu8 parse_reg = 0;\n\n\tif (szLine[0] != '@' || szLine[1] != '@')\n\t\treturn PARSE_RET_NO_HDL;\n\n\ti = 2;\n\tif (strncmp(szLine + i, VER_PREFIX, ver_prefix_len) == 0)\n\t\t; /* nothing to do */\n\telse if (strncmp(szLine + i, DOMAIN_PREFIX, domain_prefix_len) == 0) {\n\t\t/* get string after domain prefix to ',' */\n\t\ti += domain_prefix_len;\n\t\ti_val_s = i;\n\t\twhile (szLine[i] != ',') {\n\t\t\tif (szLine[i] == '\\0')\n\t\t\t\treturn PARSE_RET_FAIL;\n\t\t\ti++;\n\t\t}\n\t\ti_val_e = i;\n\n\t\t/* check if all hex */\n\t\tfor (j = i_val_s; j < i_val_e; j++)\n\t\t\tif (IsHexDigit(szLine[j]) == _FALSE)\n\t\t\t\treturn PARSE_RET_FAIL;\n\n\t\t/* get value from hex string */\n\t\tif (sscanf(szLine + i_val_s, \"%hhx\", &domain) != 1)\n\t\t\treturn PARSE_RET_FAIL;\n\n\t\tparse_reg = 1;\n\t} else if (strncmp(szLine + i, COUNTRY_PREFIX, country_prefix_len) == 0) {\n\t\t/* get string after country prefix to ',' */\n\t\ti += country_prefix_len;\n\t\ti_val_s = i;\n\t\twhile (szLine[i] != ',') {\n\t\t\tif (szLine[i] == '\\0')\n\t\t\t\treturn PARSE_RET_FAIL;\n\t\t\ti++;\n\t\t}\n\t\ti_val_e = i;\n\n\t\tif (i_val_e - i_val_s != 2)\n\t\t\treturn PARSE_RET_FAIL;\n\n\t\t/* check if all alpha */\n\t\tfor (j = i_val_s; j < i_val_e; j++)\n\t\t\tif (is_alpha(szLine[j]) == _FALSE)\n\t\t\t\treturn PARSE_RET_FAIL;\n\n\t\tcountry = szLine + i_val_s;\n\n\t\tparse_reg = 1;\n\n\t} else\n\t\treturn PARSE_RET_FAIL;\n\n\tif (parse_reg) {\n\t\t/* move to 'R' */\n\t\twhile (szLine[i] != 'R') {\n\t\t\tif (szLine[i] == '\\0')\n\t\t\t\treturn PARSE_RET_FAIL;\n\t\t\ti++;\n\t\t}\n\n\t\t/* check if matching regulation prefix */\n\t\tif (strncmp(szLine + i, REG_PREFIX, reg_prefix_len) != 0)\n\t\t\treturn PARSE_RET_FAIL;\n\n\t\t/* get string after regulation prefix ending with space */\n\t\ti += reg_prefix_len;\n\t\ti_val_s = i;\n\t\twhile (szLine[i] != ' ' && szLine[i] != '\\t' && szLine[i] != '\\0')\n\t\t\ti++;\n\n\t\tif (i == i_val_s)\n\t\t\treturn PARSE_RET_FAIL;\n\n\t\trtw_regd_exc_add_with_nlen(adapter_to_rfctl(adapter), country, domain, szLine + i_val_s, i - i_val_s);\n\t}\n\n\treturn PARSE_RET_SUCCESS;\n}\n\nstatic int\nphy_ParsePowerLimitTableFile(\n\tPADAPTER\t\tAdapter,\n\tchar\t\t\t*buffer\n)\n{\n#define LD_STAGE_EXC_MAPPING\t0\n#define LD_STAGE_TAB_DEFINE\t\t1\n#define LD_STAGE_TAB_START\t\t2\n#define LD_STAGE_COLUMN_DEFINE\t3\n#define LD_STAGE_CH_ROW\t\t\t4\n\n\tint\trtStatus = _FAIL;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(Adapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);\n\tstruct dm_struct\t*pDM_Odm = &(pHalData->odmpriv);\n\tu8\tloadingStage = LD_STAGE_EXC_MAPPING;\n\tu32\ti = 0, forCnt = 0;\n\tchar\t*szLine, *ptmp;\n\tchar band[10], bandwidth[10], rateSection[10], ntx[10], colNumBuf[10];\n\tchar **regulation = NULL;\n\tu8\tcolNum = 0;\n\n\tif (Adapter->registrypriv.RegDecryptCustomFile == 1)\n\t\tphy_DecryptBBPgParaFile(Adapter, buffer);\n\n\tptmp = buffer;\n\tfor (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {\n\t\tif (isAllSpaceOrTab(szLine, sizeof(*szLine)))\n\t\t\tcontinue;\n\t\tif (IsCommentString(szLine))\n\t\t\tcontinue;\n\n\t\tif (loadingStage == LD_STAGE_EXC_MAPPING) {\n\t\t\tif (szLine[0] == '#' || szLine[1] == '#') {\n\t\t\t\tloadingStage = LD_STAGE_TAB_DEFINE;\n\t\t\t\tif (DBG_TXPWR_LMT_FILE_PARSE)\n\t\t\t\t\tdump_regd_exc_list(RTW_DBGDUMP, adapter_to_rfctl(Adapter));\n\t\t\t} else {\n\t\t\t\tif (parse_reg_exc_config(Adapter, szLine) == PARSE_RET_FAIL) {\n\t\t\t\t\tRTW_ERR(\"Fail to parse regulation exception ruls!\\n\");\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t}\n\n\t\tif (loadingStage == LD_STAGE_TAB_DEFINE) {\n\t\t\t/* read \"##\t2.4G, 20M, 1T, CCK\" */\n\t\t\tif (szLine[0] != '#' || szLine[1] != '#')\n\t\t\t\tcontinue;\n\n\t\t\t/* skip the space */\n\t\t\ti = 2;\n\t\t\twhile (szLine[i] == ' ' || szLine[i] == '\\t')\n\t\t\t\t++i;\n\n\t\t\tszLine[--i] = ' '; /* return the space in front of the regulation info */\n\n\t\t\t/* Parse the label of the table */\n\t\t\t_rtw_memset((void *) band, 0, 10);\n\t\t\t_rtw_memset((void *) bandwidth, 0, 10);\n\t\t\t_rtw_memset((void *) ntx, 0, 10);\n\t\t\t_rtw_memset((void *) rateSection, 0, 10);\n\t\t\tif (!ParseQualifiedString(szLine, &i, band, ' ', ',')) {\n\t\t\t\tRTW_ERR(\"Fail to parse band!\\n\");\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tif (!ParseQualifiedString(szLine, &i, bandwidth, ' ', ',')) {\n\t\t\t\tRTW_ERR(\"Fail to parse bandwidth!\\n\");\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tif (!ParseQualifiedString(szLine, &i, ntx, ' ', ',')) {\n\t\t\t\tRTW_ERR(\"Fail to parse ntx!\\n\");\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tif (!ParseQualifiedString(szLine, &i, rateSection, ' ', ',')) {\n\t\t\t\tRTW_ERR(\"Fail to parse rate!\\n\");\n\t\t\t\tgoto exit;\n\t\t\t}\n\n\t\t\tloadingStage = LD_STAGE_TAB_START;\n\t\t} else if (loadingStage == LD_STAGE_TAB_START) {\n\t\t\t/* read \"##\tSTART\" */\n\t\t\tif (szLine[0] != '#' || szLine[1] != '#')\n\t\t\t\tcontinue;\n\n\t\t\t/* skip the space */\n\t\t\ti = 2;\n\t\t\twhile (szLine[i] == ' ' || szLine[i] == '\\t')\n\t\t\t\t++i;\n\n\t\t\tif (!eqNByte((u8 *)(szLine + i), (u8 *)(\"START\"), 5)) {\n\t\t\t\tRTW_ERR(\"Missing \\\"##   START\\\" label\\n\");\n\t\t\t\tgoto exit;\n\t\t\t}\n\n\t\t\tloadingStage = LD_STAGE_COLUMN_DEFINE;\n\t\t} else if (loadingStage == LD_STAGE_COLUMN_DEFINE) {\n\t\t\t/* read \"##\t#5#\tFCC\tETSI\tMKK\tIC\tKCC\" */\n\t\t\tif (szLine[0] != '#' || szLine[1] != '#')\n\t\t\t\tcontinue;\n\n\t\t\t/* skip the space */\n\t\t\ti = 2;\n\t\t\twhile (szLine[i] == ' ' || szLine[i] == '\\t')\n\t\t\t\t++i;\n\n\t\t\t_rtw_memset((void *) colNumBuf, 0, 10);\n\t\t\tif (!ParseQualifiedString(szLine, &i, colNumBuf, '#', '#')) {\n\t\t\t\tRTW_ERR(\"Fail to parse column number!\\n\");\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tif (!GetU1ByteIntegerFromStringInDecimal(colNumBuf, &colNum)) {\n\t\t\t\tRTW_ERR(\"Column number \\\"%s\\\" is not unsigned decimal\\n\", colNumBuf);\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tif (colNum == 0) {\n\t\t\t\tRTW_ERR(\"Column number is 0\\n\");\n\t\t\t\tgoto exit;\n\t\t\t}\n\n\t\t\tif (DBG_TXPWR_LMT_FILE_PARSE)\n\t\t\t\tRTW_PRINT(\"[%s][%s][%s][%s] column num:%d\\n\", band, bandwidth, rateSection, ntx, colNum);\n\n\t\t\tregulation = (char **)rtw_zmalloc(sizeof(char *) * colNum);\n\t\t\tif (!regulation) {\n\t\t\t\tRTW_ERR(\"Regulation alloc fail\\n\");\n\t\t\t\tgoto exit;\n\t\t\t}\n\n\t\t\tfor (forCnt = 0; forCnt < colNum; ++forCnt) {\n\t\t\t\tu32 i_ns;\n\n\t\t\t\t/* skip the space */\n\t\t\t\twhile (szLine[i] == ' ' || szLine[i] == '\\t')\n\t\t\t\t\ti++;\n\t\t\t\ti_ns = i;\n\n\t\t\t\twhile (szLine[i] != ' ' && szLine[i] != '\\t' && szLine[i] != '\\0')\n\t\t\t\t\ti++;\n\n\t\t\t\tregulation[forCnt] = (char *)rtw_malloc(i - i_ns + 1);\n\t\t\t\tif (!regulation[forCnt]) {\n\t\t\t\t\tRTW_ERR(\"Regulation alloc fail\\n\");\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\n\t\t\t\t_rtw_memcpy(regulation[forCnt], szLine + i_ns, i - i_ns);\n\t\t\t\tregulation[forCnt][i - i_ns] = '\\0';\n\t\t\t}\n\n\t\t\tif (DBG_TXPWR_LMT_FILE_PARSE) {\n\t\t\t\tRTW_PRINT(\"column name:\");\n\t\t\t\tfor (forCnt = 0; forCnt < colNum; ++forCnt)\n\t\t\t\t\t_RTW_PRINT(\" %s\", regulation[forCnt]);\n\t\t\t\t_RTW_PRINT(\"\\n\");\n\t\t\t}\n\n\t\t\tloadingStage = LD_STAGE_CH_ROW;\n\t\t} else if (loadingStage == LD_STAGE_CH_ROW) {\n\t\t\tchar\tchannel[10] = {0}, powerLimit[10] = {0};\n\t\t\tu8\tcnt = 0;\n\n\t\t\t/* the table ends */\n\t\t\tif (szLine[0] == '#' && szLine[1] == '#') {\n\t\t\t\ti = 2;\n\t\t\t\twhile (szLine[i] == ' ' || szLine[i] == '\\t')\n\t\t\t\t\t++i;\n\n\t\t\t\tif (eqNByte((u8 *)(szLine + i), (u8 *)(\"END\"), 3)) {\n\t\t\t\t\tloadingStage = LD_STAGE_TAB_DEFINE;\n\t\t\t\t\tif (regulation) {\n\t\t\t\t\t\tfor (forCnt = 0; forCnt < colNum; ++forCnt) {\n\t\t\t\t\t\t\tif (regulation[forCnt]) {\n\t\t\t\t\t\t\t\trtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1);\n\t\t\t\t\t\t\t\tregulation[forCnt] = NULL;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\trtw_mfree((u8 *)regulation, sizeof(char *) * colNum);\n\t\t\t\t\t\tregulation = NULL;\n\t\t\t\t\t}\n\t\t\t\t\tcolNum = 0;\n\t\t\t\t\tcontinue;\n\t\t\t\t} else {\n\t\t\t\t\tRTW_ERR(\"Missing \\\"##   END\\\" label\\n\");\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif ((szLine[0] != 'c' && szLine[0] != 'C') ||\n\t\t\t\t(szLine[1] != 'h' && szLine[1] != 'H')\n\t\t\t) {\n\t\t\t\tRTW_WARN(\"Wrong channel prefix: '%c','%c'(%d,%d)\\n\", szLine[0], szLine[1], szLine[0], szLine[1]);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\ti = 2;/* move to the  location behind 'h' */\n\n\t\t\t/* load the channel number */\n\t\t\tcnt = 0;\n\t\t\twhile (szLine[i] >= '0' && szLine[i] <= '9') {\n\t\t\t\tchannel[cnt] = szLine[i];\n\t\t\t\t++cnt;\n\t\t\t\t++i;\n\t\t\t}\n\t\t\t/* RTW_INFO(\"chnl %s!\\n\", channel); */\n\n\t\t\tfor (forCnt = 0; forCnt < colNum; ++forCnt) {\n\t\t\t\t/* skip the space between channel number and the power limit value */\n\t\t\t\twhile (szLine[i] == ' ' || szLine[i] == '\\t')\n\t\t\t\t\t++i;\n\n\t\t\t\t/* load the power limit value */\n\t\t\t\t_rtw_memset((void *) powerLimit, 0, 10);\n\n\t\t\t\tif (szLine[i] == 'W' && szLine[i + 1] == 'W') {\n\t\t\t\t\t/*\n\t\t\t\t\t* case \"WW\" assign special ww value\n\t\t\t\t\t* means to get minimal limit in other regulations at same channel\n\t\t\t\t\t*/\n\t\t\t\t\ts8 ww_value = phy_txpwr_ww_lmt_value(Adapter);\n\n\t\t\t\t\tsprintf(powerLimit, \"%d\", ww_value);\n\t\t\t\t\ti += 2;\n\n\t\t\t\t} else if (szLine[i] == 'N' && szLine[i + 1] == 'A') {\n\t\t\t\t\t/*\n\t\t\t\t\t* case \"NA\" assign max txgi value\n\t\t\t\t\t* means no limitation\n\t\t\t\t\t*/\n\t\t\t\t\tsprintf(powerLimit, \"%d\", hal_spec->txgi_max);\n\t\t\t\t\ti += 2;\n\n\t\t\t\t} else if ((szLine[i] >= '0' && szLine[i] <= '9') || szLine[i] == '.'\n\t\t\t\t\t|| szLine[i] == '+' || szLine[i] == '-'\n\t\t\t\t){\n\t\t\t\t\t/* case of dBm value */\n\t\t\t\t\tu8 integer = 0, fraction = 0, negative = 0;\n\t\t\t\t\tu32 u4bMove;\n\t\t\t\t\ts8 lmt = 0;\n\n\t\t\t\t\tif (szLine[i] == '+' || szLine[i] == '-') {\n\t\t\t\t\t\tif (szLine[i] == '-')\n\t\t\t\t\t\t\tnegative = 1;\n\t\t\t\t\t\ti++;\n\t\t\t\t\t}\n\n\t\t\t\t\tif (GetFractionValueFromString(&szLine[i], &integer, &fraction, &u4bMove))\n\t\t\t\t\t\ti += u4bMove;\n\t\t\t\t\telse {\n\t\t\t\t\t\tRTW_ERR(\"Limit \\\"%s\\\" is not valid decimal\\n\", &szLine[i]);\n\t\t\t\t\t\tgoto exit;\n\t\t\t\t\t}\n\n\t\t\t\t\t/* transform to string of value in unit of txgi */\n\t\t\t\t\tlmt = integer * hal_spec->txgi_pdbm + ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;\n\t\t\t\t\tif (negative)\n\t\t\t\t\t\tlmt = -lmt;\n\t\t\t\t\tsprintf(powerLimit, \"%d\", lmt);\n\n\t\t\t\t} else {\n\t\t\t\t\tRTW_ERR(\"Wrong limit expression \\\"%c%c\\\"(%d, %d)\\n\"\n\t\t\t\t\t\t, szLine[i], szLine[i + 1], szLine[i], szLine[i + 1]);\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\n\t\t\t\t/* store the power limit value */\n\t\t\t\tphy_set_tx_power_limit(pDM_Odm, (u8 *)regulation[forCnt], (u8 *)band,\n\t\t\t\t\t(u8 *)bandwidth, (u8 *)rateSection, (u8 *)ntx, (u8 *)channel, (u8 *)powerLimit);\n\n\t\t\t}\n\t\t}\n\t}\n\n\trtStatus = _SUCCESS;\n\nexit:\n\tif (regulation) {\n\t\tfor (forCnt = 0; forCnt < colNum; ++forCnt) {\n\t\t\tif (regulation[forCnt]) {\n\t\t\t\trtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1);\n\t\t\t\tregulation[forCnt] = NULL;\n\t\t\t}\n\t\t}\n\t\trtw_mfree((u8 *)regulation, sizeof(char *) * colNum);\n\t\tregulation = NULL;\n\t}\n\n\tRTW_INFO(\"%s return %d\\n\", __func__, rtStatus);\n\treturn rtStatus;\n}\n\nint\nPHY_ConfigRFWithPowerLimitTableParaFile(\n\t\tPADAPTER\tAdapter,\n\t\tconst char\t*pFileName\n)\n{\n\tHAL_DATA_TYPE\t\t*pHalData = GET_HAL_DATA(Adapter);\n\tint\trlen = 0, rtStatus = _FAIL;\n\n\tif (!(Adapter->registrypriv.load_phy_file & LOAD_RF_TXPWR_LMT_PARA_FILE))\n\t\treturn rtStatus;\n\n\t_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);\n\n\tif (pHalData->rf_tx_pwr_lmt == NULL) {\n\t\trtw_get_phy_file_path(Adapter, pFileName);\n\t\tif (rtw_readable_file_sz_chk(rtw_phy_para_file_path, \n\t\t\tMAX_PARA_FILE_BUF_LEN) == _TRUE) {\n\t\t\trlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);\n\t\t\tif (rlen > 0) {\n\t\t\t\trtStatus = _SUCCESS;\n\t\t\t\tpHalData->rf_tx_pwr_lmt = rtw_zvmalloc(rlen);\n\t\t\t\tif (pHalData->rf_tx_pwr_lmt) {\n\t\t\t\t\t_rtw_memcpy(pHalData->rf_tx_pwr_lmt, pHalData->para_file_buf, rlen);\n\t\t\t\t\tpHalData->rf_tx_pwr_lmt_len = rlen;\n\t\t\t\t} else\n\t\t\t\t\tRTW_INFO(\"%s rf_tx_pwr_lmt alloc fail !\\n\", __FUNCTION__);\n\t\t\t}\n\t\t}\n\t} else {\n\t\tif ((pHalData->rf_tx_pwr_lmt_len != 0) && (pHalData->rf_tx_pwr_lmt != NULL)) {\n\t\t\t_rtw_memcpy(pHalData->para_file_buf, pHalData->rf_tx_pwr_lmt, pHalData->rf_tx_pwr_lmt_len);\n\t\t\trtStatus = _SUCCESS;\n\t\t} else\n\t\t\tRTW_INFO(\"%s(): Critical Error !!!\\n\", __FUNCTION__);\n\t}\n\n\tif (rtStatus == _SUCCESS) {\n\t\t/* RTW_INFO(\"%s(): read %s ok\\n\", __FUNCTION__, pFileName); */\n\t\trtStatus = phy_ParsePowerLimitTableFile(Adapter, pHalData->para_file_buf);\n\t} else\n\t\tRTW_INFO(\"%s(): No File %s, Load from HWImg Array!\\n\", __FUNCTION__, pFileName);\n\n\treturn rtStatus;\n}\n#endif /* CONFIG_TXPWR_LIMIT */\n\nvoid phy_free_filebuf_mask(_adapter *padapter, u8 mask)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\n\tif (pHalData->mac_reg && (mask & LOAD_MAC_PARA_FILE)) {\n\t\trtw_vmfree(pHalData->mac_reg, pHalData->mac_reg_len);\n\t\tpHalData->mac_reg = NULL;\n\t}\n\tif (mask & LOAD_BB_PARA_FILE) {\n\t\tif (pHalData->bb_phy_reg) {\n\t\t\trtw_vmfree(pHalData->bb_phy_reg, pHalData->bb_phy_reg_len);\n\t\t\tpHalData->bb_phy_reg = NULL;\n\t\t}\n\t\tif (pHalData->bb_agc_tab) {\n\t\t\trtw_vmfree(pHalData->bb_agc_tab, pHalData->bb_agc_tab_len);\n\t\t\tpHalData->bb_agc_tab = NULL;\n\t\t}\n\t}\n\tif (pHalData->bb_phy_reg_pg && (mask & LOAD_BB_PG_PARA_FILE)) {\n\t\trtw_vmfree(pHalData->bb_phy_reg_pg, pHalData->bb_phy_reg_pg_len);\n\t\tpHalData->bb_phy_reg_pg = NULL;\n\t}\n\tif (pHalData->bb_phy_reg_mp && (mask & LOAD_BB_MP_PARA_FILE)) {\n\t\trtw_vmfree(pHalData->bb_phy_reg_mp, pHalData->bb_phy_reg_mp_len);\n\t\tpHalData->bb_phy_reg_mp = NULL;\n\t}\n\tif (mask & LOAD_RF_PARA_FILE) {\n\t\tif (pHalData->rf_radio_a) {\n\t\t\trtw_vmfree(pHalData->rf_radio_a, pHalData->rf_radio_a_len);\n\t\t\tpHalData->rf_radio_a = NULL;\n\t\t}\n\t\tif (pHalData->rf_radio_b) {\n\t\t\trtw_vmfree(pHalData->rf_radio_b, pHalData->rf_radio_b_len);\n\t\t\tpHalData->rf_radio_b = NULL;\n\t\t}\n\t}\n\tif (pHalData->rf_tx_pwr_track && (mask & LOAD_RF_TXPWR_TRACK_PARA_FILE)) {\n\t\trtw_vmfree(pHalData->rf_tx_pwr_track, pHalData->rf_tx_pwr_track_len);\n\t\tpHalData->rf_tx_pwr_track = NULL;\n\t}\n\tif (pHalData->rf_tx_pwr_lmt && (mask & LOAD_RF_TXPWR_LMT_PARA_FILE)) {\n\t\trtw_vmfree(pHalData->rf_tx_pwr_lmt, pHalData->rf_tx_pwr_lmt_len);\n\t\tpHalData->rf_tx_pwr_lmt = NULL;\n\t}\n}\n\ninline void phy_free_filebuf(_adapter *padapter)\n{\n\tphy_free_filebuf_mask(padapter, 0xFF);\n}\n\n#endif\n"
  },
  {
    "path": "hal/hal_dm.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2014 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include <drv_types.h>\n#include <hal_data.h>\n\n/* A mapping from HalData to ODM. */\nenum odm_board_type boardType(u8 InterfaceSel)\n{\n\tenum odm_board_type        board\t= ODM_BOARD_DEFAULT;\n\n#ifdef CONFIG_PCI_HCI\n\tINTERFACE_SELECT_PCIE   pcie\t= (INTERFACE_SELECT_PCIE)InterfaceSel;\n\tswitch (pcie) {\n\tcase INTF_SEL0_SOLO_MINICARD:\n\t\tboard |= ODM_BOARD_MINICARD;\n\t\tbreak;\n\tcase INTF_SEL1_BT_COMBO_MINICARD:\n\t\tboard |= ODM_BOARD_BT;\n\t\tboard |= ODM_BOARD_MINICARD;\n\t\tbreak;\n\tdefault:\n\t\tboard = ODM_BOARD_DEFAULT;\n\t\tbreak;\n\t}\n\n#elif defined(CONFIG_USB_HCI)\n\tINTERFACE_SELECT_USB    usb\t= (INTERFACE_SELECT_USB)InterfaceSel;\n\tswitch (usb) {\n\tcase INTF_SEL1_USB_High_Power:\n\t\tboard |= ODM_BOARD_EXT_LNA;\n\t\tboard |= ODM_BOARD_EXT_PA;\n\t\tbreak;\n\tcase INTF_SEL2_MINICARD:\n\t\tboard |= ODM_BOARD_MINICARD;\n\t\tbreak;\n\tcase INTF_SEL4_USB_Combo:\n\t\tboard |= ODM_BOARD_BT;\n\t\tbreak;\n\tcase INTF_SEL5_USB_Combo_MF:\n\t\tboard |= ODM_BOARD_BT;\n\t\tbreak;\n\tcase INTF_SEL0_USB:\n\tcase INTF_SEL3_USB_Solo:\n\tdefault:\n\t\tboard = ODM_BOARD_DEFAULT;\n\t\tbreak;\n\t}\n\n#endif\n\t/* RTW_INFO(\"===> boardType(): (pHalData->InterfaceSel, pDM_Odm->BoardType) = (%d, %d)\\n\", InterfaceSel, board); */\n\n\treturn board;\n}\n\nvoid rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tstruct dm_struct *p_dm_odm = adapter_to_phydm(adapter);\n\n\tif (hal->RegIQKFWOffload) {\n\t\trtw_sctx_init(&hal->iqk_sctx, 0);\n\t\tphydm_fwoffload_ability_init(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);\n\t} else\n\t\tphydm_fwoffload_ability_clear(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);\n\n\tRTW_INFO(\"IQK FW offload:%s\\n\", hal->RegIQKFWOffload ? \"enable\" : \"disable\");\n\n\tif (rtw_mi_check_status(adapter, MI_LINKED)) {\n\t\t#ifdef CONFIG_LPS\n\t\tLPS_Leave(adapter, \"SWITCH_IQK_OFFLOAD\");\n\t\t#endif\n\t\thalrf_iqk_trigger(p_dm_odm, _FALSE);\n\t}\n}\n\n#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))\nvoid rtw_phydm_iqk_trigger(_adapter *adapter)\n{\n\tstruct dm_struct *p_dm_odm = adapter_to_phydm(adapter);\n\tu8 clear = _TRUE;\n\tu8 segment = _FALSE;\n\tu8 rfk_forbidden = _FALSE;\n\n\thalrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);\n#if (RTL8822C_SUPPORT == 1)\n\t/* halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment); to do */\n\thalrf_rf_k_connect_trigger(p_dm_odm, _TRUE, SEGMENT_FREE);\n#else\n\t/*segment = _rtw_phydm_iqk_segment_chk(adapter);*/\n\thalrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment);\n\thalrf_segment_iqk_trigger(p_dm_odm, clear, segment);\n#endif\n}\n#endif\n\nvoid rtw_phydm_iqk_trigger_dbg(_adapter *adapter, bool recovery, bool clear, bool segment)\n{\n\tstruct dm_struct *p_dm_odm = adapter_to_phydm(adapter);\n\n#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))\n\t\thalrf_segment_iqk_trigger(p_dm_odm, clear, segment);\n#else\n\t\thalrf_iqk_trigger(p_dm_odm, recovery);\n#endif\n}\nvoid rtw_phydm_lck_trigger(_adapter *adapter)\n{\n\tstruct dm_struct *p_dm_odm = adapter_to_phydm(adapter);\n\n\thalrf_lck_trigger(p_dm_odm);\n}\n#ifdef CONFIG_DBG_RF_CAL\nvoid rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment)\n{\n\tstruct dm_struct *p_dm_odm = adapter_to_phydm(adapter);\n\n\trtw_ps_deny(adapter, PS_DENY_IOCTL);\n\tLeaveAllPowerSaveModeDirect(adapter);\n\n\trtw_phydm_ability_backup(adapter);\n\trtw_phydm_func_disable_all(adapter);\n\n\thalrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_IQK);\n\n\trtw_phydm_iqk_trigger_dbg(adapter, recovery, clear, segment);\n\trtw_phydm_ability_restore(adapter);\n\n\trtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);\n}\n\nvoid rtw_hal_lck_test(_adapter *adapter)\n{\n\tstruct dm_struct *p_dm_odm = adapter_to_phydm(adapter);\n\n\trtw_ps_deny(adapter, PS_DENY_IOCTL);\n\tLeaveAllPowerSaveModeDirect(adapter);\n\n\trtw_phydm_ability_backup(adapter);\n\trtw_phydm_func_disable_all(adapter);\n\n\thalrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_LCK);\n\n\trtw_phydm_lck_trigger(adapter);\n\n\trtw_phydm_ability_restore(adapter);\n\trtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);\n}\n#endif\n\n#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT\nvoid rtw_hal_update_param_init_fw_offload_cap(_adapter *adapter)\n{\n\tstruct dm_struct *p_dm_odm = adapter_to_phydm(adapter);\n\n\tif (adapter->registrypriv.fw_param_init)\n\t\tphydm_fwoffload_ability_init(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);\n\telse\n\t\tphydm_fwoffload_ability_clear(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);\n\n\tRTW_INFO(\"Init-Parameter FW offload:%s\\n\", adapter->registrypriv.fw_param_init ? \"enable\" : \"disable\");\n}\n#endif\n\nvoid record_ra_info(void *p_dm_void, u8 macid, struct cmn_sta_info *p_sta, u64 ra_mask)\n{\n\tstruct dm_struct *p_dm = (struct dm_struct *)p_dm_void;\n\t_adapter *adapter = p_dm->adapter;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\n\tif (p_sta) {\n\t\trtw_macid_ctl_set_bw(macid_ctl, macid, p_sta->ra_info.ra_bw_mode);\n\t\trtw_macid_ctl_set_vht_en(macid_ctl, macid, p_sta->ra_info.is_vht_enable);\n\t\trtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, ra_mask);\n\t\trtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, ra_mask >> 32);\n\n\t\trtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));\n\t}\n}\n\n#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR\nvoid rtw_phydm_fill_desc_dpt(void *dm, u8 *desc, u8 dpt_lv)\n{\n\tstruct dm_struct *p_dm = (struct dm_struct *)dm;\n\t_adapter *adapter = p_dm->adapter;\n\n\tswitch (rtw_get_chip_type(adapter)) {\n/*\n\t#ifdef CONFIG_RTL8188F\n\tcase RTL8188F:\n\t\tbreak;\n\t#endif\n\n\t#ifdef CONFIG_RTL8723B\n\tcase RTL8723B :\n\t\tbreak;\n\t#endif\n\n\t#ifdef CONFIG_RTL8703B\n\tcase RTL8703B :\n\t\tbreak;\n\t#endif\n\n\t#ifdef CONFIG_RTL8812A\n\tcase RTL8812 :\n\t\tbreak;\n\t#endif\n\n\t#ifdef CONFIG_RTL8821A\n\tcase RTL8821:\n\t\tbreak;\n\t#endif\n\n\t#ifdef CONFIG_RTL8814A\n\tcase RTL8814A :\n\t\tbreak;\n\t#endif\n\n\t#ifdef CONFIG_RTL8192F\n\tcase RTL8192F :\n\t\tbreak;\n\t#endif\n*/\n/*\n\t#ifdef CONFIG_RTL8192E\n\tcase RTL8192E :\n\t\tSET_TX_DESC_TX_POWER_0_PSET_92E(desc, dpt_lv);\n\t\tbreak;\n\t#endif\n*/\n\n\t#ifdef CONFIG_RTL8821C\n\tcase RTL8821C :\n\t\tSET_TX_DESC_TXPWR_OFSET_8821C(desc, dpt_lv);\n\tbreak;\n\t#endif\n\n\tdefault :\n\t\tRTW_ERR(\"%s IC not support dynamic tx power\\n\", __func__);\n\t\tbreak;\n\t}\n}\nvoid rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id)\n{\n\tstruct dm_struct *dm = adapter_to_phydm(adapter);\n\n\todm_set_dyntxpwr(dm, desc, mac_id);\n}\n#endif\n\n#ifdef CONFIG_RTW_TX_2PATH_EN\nvoid rtw_phydm_tx_2path_en(_adapter *adapter)\n{\n\tstruct dm_struct *dm = adapter_to_phydm(adapter);\n\n\tphydm_tx_2path(dm);\n}\n#endif\n#ifdef CONFIG_TDMADIG\nvoid rtw_phydm_tdmadig(_adapter *adapter, u8 state)\n{\n\tstruct registry_priv\t*pregistrypriv = &adapter->registrypriv;\n\tstruct mlme_priv\t\t*pmlmepriv = &(adapter->mlmepriv);\n\tstruct dm_struct *dm = adapter_to_phydm(adapter);\n\tu8 tdma_dig_en;\n\n\tswitch (state) {\n\tcase TDMADIG_INIT:\n\t\tphydm_tdma_dig_para_upd(dm, ENABLE_TDMA, pregistrypriv->tdmadig_en);\n\t\tphydm_tdma_dig_para_upd(dm, MODE_DECISION, pregistrypriv->tdmadig_mode);\n\t\tbreak;\n\tcase TDMADIG_NON_INIT:\n\t\tif(pregistrypriv->tdmadig_dynamic) {\n\t\t\tif(pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)\n\t\t\t\ttdma_dig_en = 0;\n\t\t\telse\n\t\t\t\ttdma_dig_en = pregistrypriv->tdmadig_en;\n\t\t\tphydm_tdma_dig_para_upd(dm, ENABLE_TDMA, tdma_dig_en);\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\n\t}\n}\n#endif/*CONFIG_TDMADIG*/\nvoid rtw_phydm_ops_func_init(struct dm_struct *p_phydm)\n{\n\tstruct ra_table *p_ra_t = &p_phydm->dm_ra_table;\n\n\tp_ra_t->record_ra_info = record_ra_info;\n\t#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR\n\tp_phydm->fill_desc_dyntxpwr = rtw_phydm_fill_desc_dpt;\n\t#endif\n}\nvoid rtw_phydm_priv_init(_adapter *adapter)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tstruct dm_struct *phydm = &(hal->odmpriv);\n\n\tphydm->adapter = adapter;\n\todm_cmn_info_init(phydm, ODM_CMNINFO_PLATFORM, ODM_CE);\n}\n\nvoid Init_ODM_ComInfo(_adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(adapter);\n\tstruct dm_struct\t*pDM_Odm = &(pHalData->odmpriv);\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);\n\tint i;\n\n\t/*phydm_op_mode could be change for different scenarios: ex: SoftAP - PHYDM_BALANCE_MODE*/\n\tpHalData->phydm_op_mode = PHYDM_PERFORMANCE_MODE;/*Service one device*/\n\trtw_odm_init_ic_type(adapter);\n\n\tif (rtw_get_intf_type(adapter) == RTW_GSPI)\n\t\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, ODM_ITRF_SDIO);\n\telse\n\t\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, rtw_get_intf_type(adapter));\n\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->version_id));\n\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID);\n\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec);\n\n#ifdef CONFIG_ADVANCE_OTA\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ADVANCE_OTA, adapter->registrypriv.adv_ota);\n#endif\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, pHalData->rf_type);\n\n\t{\n\t\t/* 1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= */\n\t\tu8 odm_board_type = ODM_BOARD_DEFAULT;\n\n\t\tif (pHalData->ExternalLNA_2G != 0) {\n\t\t\todm_board_type |= ODM_BOARD_EXT_LNA;\n\t\t\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1);\n\t\t}\n\t\tif (pHalData->external_lna_5g != 0) {\n\t\t\todm_board_type |= ODM_BOARD_EXT_LNA_5G;\n\t\t\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, 1);\n\t\t}\n\t\tif (pHalData->ExternalPA_2G != 0) {\n\t\t\todm_board_type |= ODM_BOARD_EXT_PA;\n\t\t\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_PA, 1);\n\t\t}\n\t\tif (pHalData->external_pa_5g != 0) {\n\t\t\todm_board_type |= ODM_BOARD_EXT_PA_5G;\n\t\t\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, 1);\n\t\t}\n\t\tif (pHalData->EEPROMBluetoothCoexist)\n\t\t\todm_board_type |= ODM_BOARD_BT;\n\n\t\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, odm_board_type);\n\t\t/* 1 ============== End of BoardType ============== */\n\t}\n\n\trtw_hal_set_odm_var(adapter, HAL_ODM_REGULATION, NULL, _TRUE);\n\n#ifdef CONFIG_DFS_MASTER\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_DFS_REGION_DOMAIN, adapter->registrypriv.dfs_region_domain);\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->radar_detect_enabled));\n#endif\n\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA);\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_APA, pHalData->TypeAPA);\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GLNA, pHalData->TypeGLNA);\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA);\n\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->rfe_type);\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_X_CAP_SETTING, pHalData->crystal_cap);\n\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0);\n\n\t/*Add by YuChen for kfree init*/\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_REGRFKFREEENABLE, adapter->registrypriv.RegPwrTrimEnable);\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFKFREEENABLE, pHalData->RfKFreeEnable);\n\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BE_FIX_TX_ANT, pHalData->b_fix_tx_ant);\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, pHalData->with_extenal_ant_switch);\n\n\t/* (8822B) efuse 0x3D7 & 0x3D8 for TX PA bias */\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D7, pHalData->efuse0x3d7);\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D8, pHalData->efuse0x3d8);\n\n\t/* waiting for PhyDMV034 support*/\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MANUAL_SUPPORTABILITY, &(adapter->registrypriv.phydm_ability)); \n\t/*Add by YuChen for adaptivity init*/\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVITY, &(adapter->registrypriv.adaptivity_en));\n\tphydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE);\n\tphydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini);\n\tphydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff);\n\n\t/*halrf info init*/\n\thalrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_EEPROM_THERMAL_VALUE, pHalData->eeprom_thermal_meter);\n\thalrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_PWT_TYPE, 0);\n\n\tif (rtw_odm_adaptivity_needed(adapter) == _TRUE)\n\t\trtw_odm_adaptivity_config_msg(RTW_DBGDUMP, adapter);\n\n#ifdef CONFIG_IQK_PA_OFF\n\todm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKPAOFF, 1);\n#endif\n\trtw_hal_update_iqk_fw_offload_cap(adapter);\n\t#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT\n\trtw_hal_update_param_init_fw_offload_cap(adapter);\n\t#endif\n\n\t/* Pointer reference */\n\t/*Antenna diversity relative parameters*/\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_DIV, &(pHalData->AntDivCfg));\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MP_MODE, &(adapter->registrypriv.mp_mode));\n\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BB_OPERATION_MODE, &(pHalData->phydm_op_mode));\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes));\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes));\n\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->current_band_type));\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate));\n\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC));\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm));\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->current_channel_bw));\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->current_channel));\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed));\n\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SCAN, &(pHalData->bScanInProcess));\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving));\n\t/*Add by Yuchen for phydm beamforming*/\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp));\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp));\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_TEST, &(pHalData->antenna_test));\n#ifdef CONFIG_RTL8723B\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_IS1ANTENNA, &pHalData->EEPROMBluetoothAntNum);\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RFDEFAULTPATH, &pHalData->ant_path);\n#endif /*CONFIG_RTL8723B*/\n#ifdef CONFIG_USB_HCI\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_HUBUSBMODE, &(dvobj->usb_speed));\n#endif\n\n#ifdef CONFIG_DYNAMIC_SOML\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVE_SOML, &(adapter->registrypriv.dyn_soml_en));\n#endif\n\n\todm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FCS_MODE, &(pHalData->multi_ch_switch_mode));\n\n\t/*halrf info hook*/\n\t/* waiting for PhyDMV034 support*/\n\thalrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY, &(adapter->registrypriv.halrf_ability));\n#ifdef CONFIG_MP_INCLUDED\n\thalrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CON_TX, &(adapter->mppriv.mpt_ctx.is_start_cont_tx));\n\thalrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_SINGLE_TONE, &(adapter->mppriv.mpt_ctx.is_single_tone));\n\thalrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CARRIER_SUPPRESSION, &(adapter->mppriv.mpt_ctx.is_carrier_suppression));\n\thalrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MP_RATE_INDEX, &(adapter->mppriv.mpt_ctx.mpt_rate_index));\n#endif/*CONFIG_MP_INCLUDED*/\n\tfor (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)\n\t\tphydm_cmn_sta_info_hook(pDM_Odm, i, NULL);\n\n\trtw_phydm_ops_func_init(pDM_Odm);\n\tphydm_dm_early_init(pDM_Odm);\n\t/* TODO */\n\t/* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */\n\t/* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */\n}\n\n\nstatic u32 edca_setting_UL[HT_IOT_PEER_MAX] =\n/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/\n/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(DownLink/Tx) */\n{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};\n\nstatic u32 edca_setting_DL[HT_IOT_PEER_MAX] =\n/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/\n/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(UpLink/Rx)*/\n{ 0xa44f, 0x5ea44f,\t 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};\n\nstatic u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] =\n/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/\n/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP */\n{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322,\t 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};\n\n\nstruct turbo_edca_setting{\n\tu32 edca_ul; /* uplink, tx */\n\tu32 edca_dl; /* downlink, rx */\n};\n\n#define TURBO_EDCA_ENT(UL, DL) {UL, DL}\n\n#if 0\n#define TURBO_EDCA_MODE_NUM 18\nstatic struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {\n\tTURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 0 */\n\tTURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */\n\tTURBO_EDCA_ENT(0x4319, 0x4319), /* mode 2 */\t\n\t\n\tTURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */\n\tTURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 4 */\n\tTURBO_EDCA_ENT(0x5e4319, 0x5e4319), /* mode 5 */\t\n\t\n\tTURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 6 */\n\tTURBO_EDCA_ENT(0x6e431c, 0x6e431c), /* mode 7 */\n\tTURBO_EDCA_ENT(0x6e4319, 0x6e4319), /* mode 8 */\n\t\n\tTURBO_EDCA_ENT(0x5ea42b, 0xa42b), /* mode 9 */\n\tTURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 10 */\n\tTURBO_EDCA_ENT(0x5e4319, 0x4319), /* mode 11 */\n\t\n\tTURBO_EDCA_ENT(0x6ea42b, 0xa42b), /* mode 12 */\n\tTURBO_EDCA_ENT(0x6e431c, 0x431c), /* mode 13 */\n\tTURBO_EDCA_ENT(0x6e4319, 0x4319), /* mode 14 */\n\n\tTURBO_EDCA_ENT(0x431c, 0x5e431c), /* mode 15 */\n\n\tTURBO_EDCA_ENT(0xa42b, 0x5ea42b), /* mode 16 */\n\n\tTURBO_EDCA_ENT(0x138642b, 0x431c), /* mode 17 */\n};\n#else\n#define TURBO_EDCA_MODE_NUM 8\nstatic struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {\n\t/* { UL, DL } */\n\tTURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 0 */\n\n\tTURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */\t\n\t\n\tTURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 2 */\n\n\tTURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */\n\t\n\tTURBO_EDCA_ENT(0x5ea42b, 0x431c), /* mode 4 */\n\t\n\tTURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 5 */\n\n\tTURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 6 */\n\t\n\tTURBO_EDCA_ENT(0x5e431c, 0xa42b), /* mode 7 */\n};\n#endif\n\nvoid rtw_hal_turbo_edca(_adapter *adapter)\n{\n\tHAL_DATA_TYPE\t\t*hal_data = GET_HAL_DATA(adapter);\n\tstruct dvobj_priv\t\t*dvobj = adapter_to_dvobj(adapter);\n\tstruct recv_priv\t\t*precvpriv = &(adapter->recvpriv);\n\tstruct registry_priv\t\t*pregpriv = &adapter->registrypriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &(adapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\t/* Parameter suggested by Scott  */\n#if 0\n\tu32\tEDCA_BE_UL = edca_setting_UL[p_mgnt_info->iot_peer];\n\tu32\tEDCA_BE_DL = edca_setting_DL[p_mgnt_info->iot_peer];\n#endif\n\tu32\tEDCA_BE_UL = 0x5ea42b;\n\tu32\tEDCA_BE_DL = 0x00a42b;\n\tu8\tic_type = rtw_get_chip_type(adapter);\n\n\tu8\tiot_peer = 0;\n\tu8\twireless_mode = 0xFF;                 /* invalid value */\n\tu8\ttraffic_index;\n\tu32\tedca_param;\n\tu64\tcur_tx_bytes = 0;\n\tu64\tcur_rx_bytes = 0;\n\tu8\tbbtchange = _TRUE;\n\tu8\tis_bias_on_rx = _FALSE;\n\tu8\tis_linked = _FALSE;\n\tu8\tinterface_type;\n\n\tif (hal_data->dis_turboedca == 1)\n\t\treturn;\n\n\tif (rtw_mi_check_status(adapter, MI_ASSOC))\n\t\tis_linked = _TRUE;\n\n\tif (is_linked != _TRUE) {\n\t\tprecvpriv->is_any_non_be_pkts = _FALSE;\n\t\treturn;\n\t}\n\n\tif ((pregpriv->wifi_spec == 1)) { /* || (pmlmeinfo->HT_enable == 0)) */\n\t\tprecvpriv->is_any_non_be_pkts = _FALSE;\n\t\treturn;\n\t}\n\n\tinterface_type = rtw_get_intf_type(adapter);\n\twireless_mode = pmlmeext->cur_wireless_mode;\n\n\tiot_peer = pmlmeinfo->assoc_AP_vendor;\n\n\tif (iot_peer >=  HT_IOT_PEER_MAX) {\n\t\tprecvpriv->is_any_non_be_pkts = _FALSE;\n\t\treturn;\n\t}\n\n\tif (ic_type == RTL8188E) {\n\t\tif ((iot_peer == HT_IOT_PEER_RALINK) || (iot_peer == HT_IOT_PEER_ATHEROS))\n\t\t\tis_bias_on_rx = _TRUE;\n\t}\n\n\t/* Check if the status needs to be changed. */\n\tif ((bbtchange) || (!precvpriv->is_any_non_be_pkts)) {\n\t\tcur_tx_bytes = dvobj->traffic_stat.cur_tx_bytes;\n\t\tcur_rx_bytes = dvobj->traffic_stat.cur_rx_bytes;\n\n\t\t/* traffic, TX or RX */\n\t\tif (is_bias_on_rx) {\n\t\t\tif (cur_tx_bytes > (cur_rx_bytes << 2)) {\n\t\t\t\t/* Uplink TP is present. */\n\t\t\t\ttraffic_index = UP_LINK;\n\t\t\t} else {\n\t\t\t\t/* Balance TP is present. */\n\t\t\t\ttraffic_index = DOWN_LINK;\n\t\t\t}\n\t\t} else {\n\t\t\tif (cur_rx_bytes > (cur_tx_bytes << 2)) {\n\t\t\t\t/* Downlink TP is present. */\n\t\t\t\ttraffic_index = DOWN_LINK;\n\t\t\t} else {\n\t\t\t\t/* Balance TP is present. */\n\t\t\t\ttraffic_index = UP_LINK;\n\t\t\t}\n\t\t}\n#if 0\n\t\tif ((p_dm_odm->dm_edca_table.prv_traffic_idx != traffic_index)\n\t\t\t|| (!p_dm_odm->dm_edca_table.is_current_turbo_edca))\n#endif\n\t\t{\n\t\t\tif (interface_type == RTW_PCIE) {\n\t\t\t\tEDCA_BE_UL = 0x6ea42b;\n\t\t\t\tEDCA_BE_DL = 0x6ea42b;\n\t\t\t}\n\n\t\t\t/* 92D txop can't be set to 0x3e for cisco1250 */\n\t\t\tif ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {\n\t\t\t\tEDCA_BE_DL = edca_setting_DL[iot_peer];\n\t\t\t\tEDCA_BE_UL = edca_setting_UL[iot_peer];\n\t\t\t}\n\t\t\t/* merge from 92s_92c_merge temp*/\n\t\t\telse if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))\n\t\t\t\tEDCA_BE_DL = edca_setting_dl_g_mode[iot_peer];\n\t\t\telse if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))\n\t\t\t\tEDCA_BE_DL = 0xa630;\n\t\t\telse if (iot_peer == HT_IOT_PEER_MARVELL) {\n\t\t\t\tEDCA_BE_DL = edca_setting_DL[iot_peer];\n\t\t\t\tEDCA_BE_UL = edca_setting_UL[iot_peer];\n\t\t\t} else if (iot_peer == HT_IOT_PEER_ATHEROS) {\n\t\t\t\t/* Set DL EDCA for Atheros peer to 0x3ea42b.*/\n\t\t\t\t/* Suggested by SD3 Wilson for ASUS TP issue.*/\n\t\t\t\tEDCA_BE_DL = edca_setting_DL[iot_peer];\n\t\t\t}\n\n\t\t\tif ((ic_type == RTL8812) || (ic_type == RTL8821) || (ic_type == RTL8192E) || (ic_type == RTL8192F)) { /* add 8812AU/8812AE */\n\t\t\t\tEDCA_BE_UL = 0x5ea42b;\n\t\t\t\tEDCA_BE_DL = 0x5ea42b;\n\n\t\t\t\tRTW_DBG(\"8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x\\n\", EDCA_BE_UL, EDCA_BE_DL);\n\t\t\t}\n\n\t\t\tif (interface_type == RTW_PCIE &&\n\t\t\t\t((ic_type == RTL8822B)\n\t\t\t\t|| (ic_type == RTL8822C)\n\t\t\t\t|| (ic_type == RTL8814A))) {\n\t\t\t\tEDCA_BE_UL = 0x6ea42b;\n\t\t\t\tEDCA_BE_DL = 0x6ea42b;\n\t\t\t}\n\n\t\t\tif ((ic_type == RTL8822B)\n\t\t\t    && (interface_type == RTW_SDIO))\n\t\t\t\tEDCA_BE_DL = 0x00431c;\n\n#ifdef CONFIG_RTW_TPT_MODE\n\t\t\tif ( dvobj->tpt_mode > 0 ) {\t\t\t\t\n\t\t\t\tEDCA_BE_UL = dvobj->edca_be_ul;\n\t\t\t\tEDCA_BE_DL = dvobj->edca_be_dl;\n\t\t\t}\n#endif /* CONFIG_RTW_TPT_MODE */\n\n\t\t\t/* keep this condition at last check */\n\t\t\tif (hal_data->dis_turboedca == 2) {\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\tif (hal_data->edca_param_mode < TURBO_EDCA_MODE_NUM) {\n\n\t\t\t\t\t\tstruct turbo_edca_setting param;\n\n\t\t\t\t\t\tparam = rtw_turbo_edca[hal_data->edca_param_mode];\n\n\t\t\t\t\t\tEDCA_BE_UL = param.edca_ul;\n\t\t\t\t\t\tEDCA_BE_DL = param.edca_dl;\n\t\t\t\t\t\t\n\t\t\t\t\t} else {\n\t\t\t\t\t\n\t\t\t\t\t\tEDCA_BE_UL = hal_data->edca_param_mode;\n\t\t\t\t\t\tEDCA_BE_DL = hal_data->edca_param_mode;\n\t\t\t\t\t}\t\t\t\t\n\t\t\t}\n\n\t\t\tif (traffic_index == DOWN_LINK)\n\t\t\t\tedca_param = EDCA_BE_DL;\n\t\t\telse\n\t\t\t\tedca_param = EDCA_BE_UL;\n\n#ifdef CONFIG_EXTEND_LOWRATE_TXOP\n#define TXOP_CCK1M\t\t\t0x01A6\n#define TXOP_CCK2M\t\t\t0x00E6\n#define TXOP_CCK5M\t\t\t0x006B\n#define TXOP_OFD6M\t\t\t0x0066\n#define TXOP_MCS6M\t\t\t0x0061\n{\n\t\t\tstruct sta_info *psta;\n\t\t\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\t\t\tu8 mac_id, role, current_rate_id;\n\t\t\t\n\t\t\t/*\tsearch all used & connect2AP macid\t*/\n\t\t\tfor (mac_id = 0; mac_id < macid_ctl->num; mac_id++) {\n\t\t\t\tif (rtw_macid_is_used(macid_ctl, mac_id))  {\n\t\t\t\t\trole = GET_H2CCMD_MSRRPT_PARM_ROLE(&(macid_ctl->h2c_msr[mac_id]));\n\t\t\t\t\tif (role != H2C_MSR_ROLE_AP)\n\t\t\t\t\t\tcontinue;\n\n\t\t\t\t\tpsta = macid_ctl->sta[mac_id];\n\t\t\t\t\tcurrent_rate_id = rtw_get_current_tx_rate(adapter, psta);\n\t\t\t\t\t/*  Check init tx_rate==1M and set 0x508[31:16]==0x019B(unit 32us) if it is \t*/\n\t\t\t\t\tswitch (current_rate_id) {\n\t\t\t\t\t\tcase DESC_RATE1M:\n\t\t\t\t\t\t\tedca_param &= 0x0000FFFF;\n\t\t\t\t\t\t\tedca_param |= (TXOP_CCK1M<<16);\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase DESC_RATE2M:\n\t\t\t\t\t\t\tedca_param &= 0x0000FFFF;\n\t\t\t\t\t\t\tedca_param |= (TXOP_CCK2M<<16);\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase DESC_RATE5_5M:\n\t\t\t\t\t\t\tedca_param &= 0x0000FFFF;\n\t\t\t\t\t\t\tedca_param |= (TXOP_CCK5M<<16);\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase DESC_RATE6M:\n\t\t\t\t\t\t\tedca_param &= 0x0000FFFF;\n\t\t\t\t\t\t\tedca_param |= (TXOP_OFD6M<<16);\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase DESC_RATEMCS0:\n\t\t\t\t\t\t\tedca_param &= 0x0000FFFF;\n\t\t\t\t\t\t\tedca_param |= (TXOP_MCS6M<<16);\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tdefault:\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n}\n#endif /* CONFIG_EXTEND_LOWRATE_TXOP */\n\n#ifdef \tCONFIG_RTW_CUSTOMIZE_BEEDCA\n\t\t\tedca_param = CONFIG_RTW_CUSTOMIZE_BEEDCA;\n#endif\n\n\t\t\tif ( edca_param != hal_data->ac_param_be) {\n\t\t\t\t\n\t\t\t\trtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));\n\n\t\t\t\tRTW_INFO(\"Turbo EDCA =0x%x\\n\", edca_param);\n\t\t\t}\n\n\t\t\thal_data->prv_traffic_idx = traffic_index;\n\t\t}\n\n\t\thal_data->is_turbo_edca = _TRUE;\n\t} else {\n\t\t/*  */\n\t\t/* Turn Off EDCA turbo here. */\n\t\t/* Restore original EDCA according to the declaration of AP. */\n\t\t/*  */\n\t\tif (hal_data->is_turbo_edca) {\n\t\t\tedca_param = hal_data->ac_param_be;\n\t\t\trtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));\n\t\t\thal_data->is_turbo_edca = _FALSE;\n\t\t}\n\t}\n\n}\n\ns8 rtw_dm_get_min_rssi(_adapter *adapter)\n{\n\tstruct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);\n\tstruct sta_info *sta;\n\ts8 min_rssi = 127, rssi;\n\tint i;\n\n\tfor (i = 0; i < MACID_NUM_SW_LIMIT; i++) {\n\t\tsta = macid_ctl->sta[i];\n\t\tif (!sta || !GET_H2CCMD_MSRRPT_PARM_OPMODE(macid_ctl->h2c_msr + i)\n\t\t\t|| is_broadcast_mac_addr(sta->cmn.mac_addr))\n\t\t\tcontinue;\n\t\trssi = sta->cmn.rssi_stat.rssi;\n\t\tif (rssi >= 0 && min_rssi > rssi)\n\t\t\tmin_rssi = rssi;\n\t}\n\n\treturn min_rssi == 127 ? 0 : min_rssi;\n}\n\ns8 rtw_phydm_get_min_rssi(_adapter *adapter)\n{\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n\ts8 rssi_min = 0;\n\n\trssi_min = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_RSSI_MIN);\n\treturn rssi_min;\n}\n\nu8 rtw_phydm_get_cur_igi(_adapter *adapter)\n{\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n\tu8 cur_igi = 0;\n\n\tcur_igi = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CURR_IGI);\n\treturn cur_igi;\n}\n\nbool rtw_phydm_get_edcca_flag(_adapter *adapter)\n{\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n\tbool cur_edcca_flag = 0;\n\n\tcur_edcca_flag = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_EDCCA_FLAG);\n\treturn cur_edcca_flag;\n}\n\nu32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt)\n{\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n\n\tif (cnt == FA_OFDM)\n\t\treturn  phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_OFDM);\n\telse if (cnt == FA_CCK)\n\t\treturn  phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_CCK);\n\telse if (cnt == FA_TOTAL)\n\t\treturn  phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_TOTAL);\n\telse if (cnt == CCA_OFDM)\n\t\treturn\tphydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_OFDM);\n\telse if (cnt == CCA_CCK)\n\t\treturn\tphydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_CCK);\n\telse if (cnt == CCA_ALL)\n\t\treturn\tphydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_ALL);\n\telse if (cnt == CRC32_OK_VHT)\n\t\treturn\tphydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_VHT);\n\telse if (cnt == CRC32_OK_HT)\n\t\treturn\tphydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_HT);\n\telse if (cnt == CRC32_OK_LEGACY)\n\t\treturn\tphydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_LEGACY);\n\telse if (cnt == CRC32_OK_CCK)\n\t\treturn\tphydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_CCK);\n\telse if (cnt == CRC32_ERROR_VHT)\n\t\treturn\tphydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_VHT);\n\telse if (cnt == CRC32_ERROR_HT)\n\t\treturn\tphydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_HT);\n\telse if (cnt == CRC32_ERROR_LEGACY)\n\t\treturn\tphydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_LEGACY);\n\telse if (cnt == CRC32_ERROR_CCK)\n\t\treturn\tphydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_CCK);\n\telse\n\t\treturn 0;\n}\n\nu8 rtw_phydm_is_iqk_in_progress(_adapter *adapter)\n{\n\tu8 rts = _FALSE;\n\tstruct dm_struct *podmpriv = adapter_to_phydm(adapter);\n\n\todm_acquire_spin_lock(podmpriv, RT_IQK_SPINLOCK);\n\tif (podmpriv->rf_calibrate_info.is_iqk_in_progress == _TRUE) {\n\t\tRTW_ERR(\"IQK InProgress\\n\");\n\t\trts = _TRUE;\n\t}\n\todm_release_spin_lock(podmpriv, RT_IQK_SPINLOCK);\n\n\treturn rts;\n}\n\nvoid SetHalODMVar(\n\tPADAPTER\t\t\t\tAdapter,\n\tHAL_ODM_VARIABLE\t\teVariable,\n\tvoid\t\t\t\t\t\t*pValue1,\n\tBOOLEAN\t\t\t\t\tbSet)\n{\n\tstruct dm_struct *podmpriv = adapter_to_phydm(Adapter);\n\t/* _irqL irqL; */\n\tswitch (eVariable) {\n\tcase HAL_ODM_STA_INFO: {\n\t\tstruct sta_info *psta = (struct sta_info *)pValue1;\n\n\t\tif (bSet) {\n\t\t\tRTW_INFO(\"### Set STA_(%d) info ###\\n\", psta->cmn.mac_id);\n\t\t\tpsta->cmn.dm_ctrl = STA_DM_CTRL_ACTIVE;\n\t\t\tphydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, &(psta->cmn));\n\t\t} else {\n\t\t\tRTW_INFO(\"### Clean STA_(%d) info ###\\n\", psta->cmn.mac_id);\n\t\t\t/* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */\n\t\t\tpsta->cmn.dm_ctrl = 0;\n\t\t\tphydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, NULL);\n\n\t\t\t/* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */\n\t\t}\n\t}\n\t\tbreak;\n\tcase HAL_ODM_P2P_STATE:\n\t\todm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);\n\t\tbreak;\n\tcase HAL_ODM_WIFI_DISPLAY_STATE:\n\t\todm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);\n\t\tbreak;\n\tcase HAL_ODM_REGULATION:\n\t\t/* used to auto enable/disable adaptivity by SD7 */\n\t\tphydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_2G, 0);\n\t\tphydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_5G, 0);\n\t\tbreak;\n\tcase HAL_ODM_INITIAL_GAIN: {\n\t\tu8 rx_gain = *((u8 *)(pValue1));\n\t\t/*printk(\"rx_gain:%x\\n\",rx_gain);*/\n\t\tif (rx_gain == 0xff) {/*restore rx gain*/\n\t\t\t/*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/\n\t\t\todm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain);\n\t\t} else {\n\t\t\t/*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/\n\t\t\t/*odm_write_dig(podmpriv,rx_gain);*/\n\t\t\todm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain);\n\t\t}\n\t}\n\tbreak;\n\tcase HAL_ODM_RX_INFO_DUMP: {\n\t\tu8 cur_igi = 0;\n\t\ts8 rssi_min;\n\t\tvoid *sel;\n\n\t\tsel = pValue1;\n\t\tcur_igi = rtw_phydm_get_cur_igi(Adapter);\n\t\trssi_min = rtw_phydm_get_min_rssi(Adapter);\n\n\t\t_RTW_PRINT_SEL(sel, \"============ Rx Info dump ===================\\n\");\n\t\t_RTW_PRINT_SEL(sel, \"is_linked = %d, rssi_min = %d(%%)(%d(%%)), current_igi = 0x%x\\n\"\n\t\t\t, podmpriv->is_linked, rssi_min, rtw_dm_get_min_rssi(Adapter), cur_igi);\n\t\t_RTW_PRINT_SEL(sel, \"cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\\n\",\n\t\t\trtw_phydm_get_phy_cnt(Adapter, FA_CCK),\n\t\t\trtw_phydm_get_phy_cnt(Adapter, FA_OFDM),\n\t\t\trtw_phydm_get_phy_cnt(Adapter, FA_TOTAL));\n\n\t\tif (podmpriv->is_linked) {\n\t\t\t_RTW_PRINT_SEL(sel, \"rx_rate = %s\", HDATA_RATE(podmpriv->rx_rate));\n\t\t\tif (IS_HARDWARE_TYPE_8814A(Adapter))\n\t\t\t\t_RTW_PRINT_SEL(sel, \" rssi_a = %d(%%), rssi_b = %d(%%), rssi_c = %d(%%), rssi_d = %d(%%)\\n\",\n\t\t\t\t\tpodmpriv->rssi_a, podmpriv->rssi_b, podmpriv->rssi_c, podmpriv->rssi_d);\n\t\t\telse\n\t\t\t\t_RTW_PRINT_SEL(sel, \" rssi_a = %d(%%), rssi_b = %d(%%)\\n\", podmpriv->rssi_a, podmpriv->rssi_b);\n#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA\n\t\t\trtw_dump_raw_rssi_info(Adapter, sel);\n#endif\n\t\t}\n\t}\n\t\tbreak;\n\tcase HAL_ODM_RX_Dframe_INFO: {\n\t\tvoid *sel;\n\n\t\tsel = pValue1;\n\n\t\t/*_RTW_PRINT_SEL(sel , \"HAL_ODM_RX_Dframe_INFO\\n\");*/\n#ifdef DBG_RX_DFRAME_RAW_DATA\n\t\trtw_dump_rx_dframe_info(Adapter, sel);\n#endif\n\t}\n\t\tbreak;\n\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\tcase HAL_ODM_ANTDIV_SELECT: {\n\t\tu8\tantenna = (*(u8 *)pValue1);\n\t\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(Adapter);\n\t\t/*switch antenna*/\n\t\todm_update_rx_idle_ant(&pHalData->odmpriv, antenna);\n\t\t/*RTW_INFO(\"==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\\n\", (antenna == MAIN_ANT) ? \"MAIN_ANT\" : \"AUX_ANT\");*/\n\n\t}\n\t\tbreak;\n#endif\n\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid GetHalODMVar(\n\tPADAPTER\t\t\t\tAdapter,\n\tHAL_ODM_VARIABLE\t\teVariable,\n\tvoid\t\t\t\t\t\t*pValue1,\n\tvoid\t\t\t\t\t\t*pValue2)\n{\n\tstruct dm_struct *podmpriv = adapter_to_phydm(Adapter);\n\n\tswitch (eVariable) {\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\tcase HAL_ODM_ANTDIV_SELECT: {\n\t\tstruct phydm_fat_struct\t*pDM_FatTable = &podmpriv->dm_fat_table;\n\t\t*((u8 *)pValue1) = pDM_FatTable->rx_idle_ant;\n\t}\n\t\tbreak;\n#endif\n\tcase HAL_ODM_INITIAL_GAIN:\n\t\t*((u8 *)pValue1) = rtw_phydm_get_cur_igi(Adapter);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n#ifdef RTW_HALMAC\n#include \"../hal_halmac.h\"\n#endif\n\nenum hal_status\nrtw_phydm_fw_iqk(\n\tstruct dm_struct\t*p_dm_odm,\n\tu8 clear,\n\tu8 segment\n)\n{\n\t#ifdef RTW_HALMAC\n\tstruct _ADAPTER *adapter = p_dm_odm->adapter;\n\n\tif (rtw_halmac_iqk(adapter_to_dvobj(adapter), clear, segment) == 0)\n\t\treturn HAL_STATUS_SUCCESS;\n\t#endif\n\treturn HAL_STATUS_FAILURE;\n}\n\nenum hal_status\nrtw_phydm_cfg_phy_para(\n\tstruct dm_struct\t*p_dm_odm,\n\tenum phydm_halmac_param config_type,\n\tu32 offset,\n\tu32 data,\n\tu32 mask,\n\tenum rf_path e_rf_path,\n\tu32 delay_time)\n{\n\t#ifdef RTW_HALMAC\n\tstruct _ADAPTER *adapter = p_dm_odm->adapter;\n\tstruct rtw_phy_parameter para;\n\n\tswitch (config_type) {\n\tcase PHYDM_HALMAC_CMD_MAC_W8:\n\t\tpara.cmd = 0; /* MAC register */\n\t\tpara.data.mac.offset = offset;\n\t\tpara.data.mac.value = data;\n\t\tpara.data.mac.msk = mask;\n\t\tpara.data.mac.msk_en = (mask) ? 1 : 0;\n\t\tpara.data.mac.size = 1;\n\tbreak;\n\tcase PHYDM_HALMAC_CMD_MAC_W16:\n\t\tpara.cmd = 0; /* MAC register */\n\t\tpara.data.mac.offset = offset;\n\t\tpara.data.mac.value = data;\n\t\tpara.data.mac.msk = mask;\n\t\tpara.data.mac.msk_en = (mask) ? 1 : 0;\n\t\tpara.data.mac.size = 2;\n\tbreak;\n\tcase PHYDM_HALMAC_CMD_MAC_W32:\n\t\tpara.cmd = 0; /* MAC register */\n\t\tpara.data.mac.offset = offset;\n\t\tpara.data.mac.value = data;\n\t\tpara.data.mac.msk = mask;\n\t\tpara.data.mac.msk_en = (mask) ? 1 : 0;\n\t\tpara.data.mac.size = 4;\n\tbreak;\n\tcase PHYDM_HALMAC_CMD_BB_W8:\n\t\tpara.cmd = 1; /* BB register */\n\t\tpara.data.bb.offset = offset;\n\t\tpara.data.bb.value = data;\n\t\tpara.data.bb.msk = mask;\n\t\tpara.data.bb.msk_en = (mask) ? 1 : 0;\n\t\tpara.data.bb.size = 1;\n\tbreak;\n\tcase PHYDM_HALMAC_CMD_BB_W16:\n\t\tpara.cmd = 1; /* BB register */\n\t\tpara.data.bb.offset = offset;\n\t\tpara.data.bb.value = data;\n\t\tpara.data.bb.msk = mask;\n\t\tpara.data.bb.msk_en = (mask) ? 1 : 0;\n\t\tpara.data.bb.size = 2;\n\tbreak;\n\tcase PHYDM_HALMAC_CMD_BB_W32:\n\t\tpara.cmd = 1; /* BB register */\n\t\tpara.data.bb.offset = offset;\n\t\tpara.data.bb.value = data;\n\t\tpara.data.bb.msk = mask;\n\t\tpara.data.bb.msk_en = (mask) ? 1 : 0;\n\t\tpara.data.bb.size = 4;\n\tbreak;\n\tcase PHYDM_HALMAC_CMD_RF_W:\n\t\tpara.cmd = 2; /* RF register */\n\t\tpara.data.rf.offset = offset;\n\t\tpara.data.rf.value = data;\n\t\tpara.data.rf.msk = mask;\n\t\tpara.data.rf.msk_en = (mask) ? 1 : 0;\n\t\tif (e_rf_path == RF_PATH_A)\n\t\t\tpara.data.rf.path = 0;\n\t\telse if (e_rf_path == RF_PATH_B)\n\t\t\tpara.data.rf.path = 1;\n\t\telse if (e_rf_path == RF_PATH_C)\n\t\t\tpara.data.rf.path = 2;\n\t\telse if (e_rf_path == RF_PATH_D)\n\t\t\tpara.data.rf.path = 3;\n\t\telse\n\t\t\tpara.data.rf.path = 0;\n\tbreak;\n\tcase PHYDM_HALMAC_CMD_DELAY_US:\n\t\tpara.cmd = 3; /* Delay */\n\t\tpara.data.delay.unit = 0; /* microsecond */\n\t\tpara.data.delay.value = delay_time;\n\tbreak;\n\tcase PHYDM_HALMAC_CMD_DELAY_MS:\n\t\tpara.cmd = 3; /* Delay */\n\t\tpara.data.delay.unit = 1; /* millisecond */\n\t\tpara.data.delay.value = delay_time;\n\tbreak;\n\tcase PHYDM_HALMAC_CMD_END:\n\t\tpara.cmd = 0xFF; /* End command */\n\tbreak;\n\tdefault:\n\t\treturn HAL_STATUS_FAILURE;\n\t}\n\n\tif (rtw_halmac_cfg_phy_para(adapter_to_dvobj(adapter), &para))\n\t\treturn HAL_STATUS_FAILURE;\n\t#endif /*RTW_HALMAC*/\n\treturn HAL_STATUS_SUCCESS;\n}\n\n\n#ifdef CONFIG_LPS_LCLK_WD_TIMER\nvoid rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter)\n{\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);\n\tstruct dm_struct\t*podmpriv = &(pHalData->odmpriv);\n\tstruct sta_priv *pstapriv = &adapter->stapriv;\n\tstruct sta_info *psta = NULL;\n\tu8 rssi_min = 0;\n\tu32\trssi_rpt = 0;\n\tbool is_linked = _FALSE;\n\n\tif (!rtw_is_hw_init_completed(adapter))\n\t\treturn;\n\n\tif (rtw_mi_check_status(adapter, MI_ASSOC))\n\t\tis_linked = _TRUE;\n\n\tif (is_linked == _FALSE)\n\t\treturn;\n\n\tpsta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));\n\tif (psta == NULL)\n\t\treturn;\n\n\todm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, is_linked);\n\n\tphydm_watchdog_lps_32k(&pHalData->odmpriv);\n}\n\nvoid rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter)\n{\n\tstruct mlme_priv\t*pmlmepriv = &adapter->mlmepriv;\n\tstruct sta_priv *pstapriv = &adapter->stapriv;\n\tu8 cur_igi = 0;\n\ts8 min_rssi = 0;\n\n\tif (!rtw_is_hw_init_completed(adapter))\n\t\treturn;\n\n\tcur_igi = rtw_phydm_get_cur_igi(adapter);\n\tmin_rssi = rtw_dm_get_min_rssi(adapter);\n\t/*RTW_INFO(\"%s \"ADPT_FMT\" cur_ig_value=%d, min_rssi = %d\\n\", __func__,  ADPT_ARG(adapter), cur_igi, min_rssi);*/\n\n\tif (min_rssi <= 0)\n\t\treturn;\n\n\tif ((cur_igi > min_rssi + 5) ||\n\t\t(cur_igi < min_rssi - 5)) {\n#ifdef CONFIG_LPS\n\t\trtw_dm_in_lps_wk_cmd(adapter);\n#endif\n\t}\n}\n#endif /*CONFIG_LPS_LCLK_WD_TIMER*/\n\nvoid dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta)\n{\n\tstruct ra_sta_info *ra_info;\n\tu8 curr_sgi = _FALSE;\n\tu32 tx_tp_mbips, rx_tp_mbips, bi_tp_mbips;\n\n\tif (!psta)\n\t\treturn;\n\tRTW_PRINT_SEL(sel, \"\\n\");\n\tRTW_PRINT_SEL(sel, \"====== mac_id : %d [\" MAC_FMT \"] ======\\n\",\n\t\tpsta->cmn.mac_id, MAC_ARG(psta->cmn.mac_addr));\n\n\tif (is_client_associated_to_ap(psta->padapter))\n\t\tRTW_PRINT_SEL(sel, \"BCN counts : %d (per-%d second), DTIM Period:%d\\n\",\n\t\trtw_get_bcn_cnt(psta->padapter) / 2, 1, rtw_get_bcn_dtim_period(psta->padapter));\n\n\tra_info = &psta->cmn.ra_info;\n\tcurr_sgi = rtw_get_current_tx_sgi(adapter, psta);\n\tRTW_PRINT_SEL(sel, \"tx_rate : %s(%s)  rx_rate : %s, rx_rate_bmc : %s, rssi : %d %%\\n\"\n\t\t, HDATA_RATE(rtw_get_current_tx_rate(adapter, psta)), (curr_sgi) ? \"S\" : \"L\"\n\t\t, HDATA_RATE((psta->curr_rx_rate & 0x7F)), HDATA_RATE((psta->curr_rx_rate_bmc & 0x7F)), psta->cmn.rssi_stat.rssi\n\t);\n\n\tif (0) {\n\t\tRTW_PRINT_SEL(sel, \"tx_bytes:%llu(%llu - %llu)\\n\"\n\t\t\t, psta->sta_stats.tx_bytes - psta->sta_stats.last_tx_bytes\n\t\t\t, psta->sta_stats.tx_bytes, psta->sta_stats.last_tx_bytes\n\t\t);\n\t\tRTW_PRINT_SEL(sel, \"rx_uc_bytes:%llu(%llu - %llu)\\n\"\n\t\t\t, sta_rx_uc_bytes(psta) - sta_last_rx_uc_bytes(psta)\n\t\t\t, sta_rx_uc_bytes(psta), sta_last_rx_uc_bytes(psta)\n\t\t);\n\t\tRTW_PRINT_SEL(sel, \"rx_mc_bytes:%llu(%llu - %llu)\\n\"\n\t\t\t, psta->sta_stats.rx_mc_bytes - psta->sta_stats.last_rx_mc_bytes\n\t\t\t, psta->sta_stats.rx_mc_bytes, psta->sta_stats.last_rx_mc_bytes\n\t\t);\n\t\tRTW_PRINT_SEL(sel, \"rx_bc_bytes:%llu(%llu - %llu)\\n\"\n\t\t\t, psta->sta_stats.rx_bc_bytes - psta->sta_stats.last_rx_bc_bytes\n\t\t\t, psta->sta_stats.rx_bc_bytes, psta->sta_stats.last_rx_bc_bytes\n\t\t);\n\t}\n\n\t_RTW_PRINT_SEL(sel, \"RTW: [TP] \");\n\ttx_tp_mbips = psta->sta_stats.tx_tp_kbits >> 10;\n\trx_tp_mbips = psta->sta_stats.rx_tp_kbits >> 10;\n\tbi_tp_mbips = tx_tp_mbips + rx_tp_mbips;\n\n\tif (tx_tp_mbips)\n\t\t_RTW_PRINT_SEL(sel, \"Tx : %d(Mbps) \", tx_tp_mbips);\n\telse\n\t\t_RTW_PRINT_SEL(sel, \"Tx : %d(Kbps) \", psta->sta_stats.tx_tp_kbits);\n\n\tif (rx_tp_mbips) \n\t\t_RTW_PRINT_SEL(sel, \"Rx : %d(Mbps) \", rx_tp_mbips);\n\telse\n\t\t_RTW_PRINT_SEL(sel, \"Rx : %d(Kbps) \", psta->sta_stats.rx_tp_kbits);\n\n\tif (bi_tp_mbips)\n\t\t_RTW_PRINT_SEL(sel, \"Total : %d(Mbps)\\n\", bi_tp_mbips);\n\telse\n\t\t_RTW_PRINT_SEL(sel, \"Total : %d(Kbps)\\n\", psta->sta_stats.tx_tp_kbits + psta->sta_stats.rx_tp_kbits);\n\n\n\t_RTW_PRINT_SEL(sel, \"RTW: [Smooth TP] \");\n\ttx_tp_mbips = psta->sta_stats.smooth_tx_tp_kbits >> 10;\n\trx_tp_mbips = psta->sta_stats.smooth_rx_tp_kbits >> 10;\n\tbi_tp_mbips = tx_tp_mbips + rx_tp_mbips;\n\tif (tx_tp_mbips)\n\t\t_RTW_PRINT_SEL(sel, \"Tx : %d(Mbps) \", tx_tp_mbips);\n\telse\n\t\t_RTW_PRINT_SEL(sel, \"Tx : %d(Kbps) \", psta->sta_stats.smooth_tx_tp_kbits);\n\n\tif (rx_tp_mbips) \n\t\t_RTW_PRINT_SEL(sel, \"Rx : %d(Mbps) \", rx_tp_mbips);\n\telse\n\t\t_RTW_PRINT_SEL(sel, \"Rx : %d(Kbps) \", psta->sta_stats.smooth_rx_tp_kbits);\n\n\tif (bi_tp_mbips)\n\t\t_RTW_PRINT_SEL(sel, \"Total : %d(Mbps)\\n\", bi_tp_mbips);\n\telse\n\t\t_RTW_PRINT_SEL(sel, \"Total : %d(Kbps)\\n\", psta->sta_stats.smooth_tx_tp_kbits + psta->sta_stats.rx_tp_kbits);\n\n\t#if 0\n\tRTW_PRINT_SEL(sel, \"Moving-AVG TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\\n\\n\",\n\t\t(psta->cmn.tx_moving_average_tp << 3), (psta->cmn.rx_moving_average_tp << 3),\n\t\t(psta->cmn.tx_moving_average_tp + psta->cmn.rx_moving_average_tp) << 3);\n\t#endif\n}\n\nvoid dump_sta_info(void *sel, struct sta_info *psta)\n{\n\tstruct ra_sta_info *ra_info;\n\tu8 curr_tx_sgi = _FALSE;\n\tu8 curr_tx_rate = 0;\n\n\tif (!psta)\n\t\treturn;\n\n\tra_info = &psta->cmn.ra_info;\n\n\tRTW_PRINT_SEL(sel, \"============ STA [\" MAC_FMT \"]  ===================\\n\",\n\t\tMAC_ARG(psta->cmn.mac_addr));\n\tRTW_PRINT_SEL(sel, \"mac_id : %d\\n\", psta->cmn.mac_id);\n\tRTW_PRINT_SEL(sel, \"wireless_mode : 0x%02x\\n\", psta->wireless_mode);\n\tRTW_PRINT_SEL(sel, \"mimo_type : %d\\n\", psta->cmn.mimo_type);\n\tRTW_PRINT_SEL(sel, \"static smps : %s\\n\", (psta->cmn.sm_ps == SM_PS_STATIC) ? \"Y\" : \"N\");\n\tRTW_PRINT_SEL(sel, \"bw_mode : %s, ra_bw_mode : %s\\n\",\n\t\t\tch_width_str(psta->cmn.bw_mode), ch_width_str(ra_info->ra_bw_mode));\n\tRTW_PRINT_SEL(sel, \"rate_id : %d\\n\", ra_info->rate_id);\n\tRTW_PRINT_SEL(sel, \"rssi : %d (%%), rssi_level : %d\\n\", psta->cmn.rssi_stat.rssi, ra_info->rssi_level);\n\tRTW_PRINT_SEL(sel, \"is_support_sgi : %s, is_vht_enable : %s\\n\",\n\t\t\t(ra_info->is_support_sgi) ? \"Y\" : \"N\", (ra_info->is_vht_enable) ? \"Y\" : \"N\");\n\tRTW_PRINT_SEL(sel, \"disable_ra : %s, disable_pt : %s\\n\",\n\t\t\t\t(ra_info->disable_ra) ? \"Y\" : \"N\", (ra_info->disable_pt) ? \"Y\" : \"N\");\n\tRTW_PRINT_SEL(sel, \"is_noisy : %s\\n\", (ra_info->is_noisy) ? \"Y\" : \"N\");\n\tRTW_PRINT_SEL(sel, \"txrx_state : %d\\n\", ra_info->txrx_state);/*0: uplink, 1:downlink, 2:bi-direction*/\n\n\tcurr_tx_sgi = rtw_get_current_tx_sgi(psta->padapter, psta);\n\tcurr_tx_rate = rtw_get_current_tx_rate(psta->padapter, psta);\n\tRTW_PRINT_SEL(sel, \"curr_tx_rate : %s (%s)\\n\",\n\t\t\tHDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? \"S\" : \"L\");\n\tRTW_PRINT_SEL(sel, \"curr_tx_bw : %s\\n\", ch_width_str(ra_info->curr_tx_bw));\n\tRTW_PRINT_SEL(sel, \"curr_retry_ratio : %d\\n\", ra_info->curr_retry_ratio);\n\tRTW_PRINT_SEL(sel, \"ra_mask : 0x%016llx\\n\\n\", ra_info->ramask);\n}\n\nvoid rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\n\tif (psta == NULL) {\n\t\tRTW_ERR(FUNC_ADPT_FMT\" sta is NULL\\n\", FUNC_ADPT_ARG(adapter));\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tphydm_ra_registed(&hal_data->odmpriv, psta->cmn.mac_id, psta->cmn.rssi_stat.rssi);\n\tdump_sta_info(RTW_DBGDUMP, psta);\n}\n\nstatic void init_phydm_info(_adapter *adapter)\n{\n\tPHAL_DATA_TYPE\thal_data = GET_HAL_DATA(adapter);\n\tstruct dm_struct *phydm = &(hal_data->odmpriv);\n\n\todm_cmn_info_update(phydm, ODM_CMNINFO_IS_DOWNLOAD_FW, hal_data->bFWReady);\n\todm_cmn_info_init(phydm, ODM_CMNINFO_FW_VER, hal_data->firmware_version);\n\todm_cmn_info_init(phydm, ODM_CMNINFO_FW_SUB_VER, hal_data->firmware_sub_version);\n}\nvoid rtw_phydm_init(_adapter *adapter)\n{\n\tPHAL_DATA_TYPE\thal_data = GET_HAL_DATA(adapter);\n\tstruct dm_struct\t*phydm = &(hal_data->odmpriv);\n\n\tinit_phydm_info(adapter);\n\todm_dm_init(phydm);\n#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA\n\tphydm_pathb_q_matrix_rotate_en(phydm);\n#endif\n}\n\nbool rtw_phydm_set_crystal_cap(_adapter *adapter, u8 crystal_cap)\n{\n\tPHAL_DATA_TYPE\thal_data = GET_HAL_DATA(adapter);\n\tstruct dm_struct\t*phydm = &(hal_data->odmpriv);\n\n\treturn phydm_set_crystal_cap_reg(phydm, crystal_cap);\n}\n\n#ifdef CONFIG_LPS_PG\n/*\nstatic void _lps_pg_state_update(_adapter *adapter)\n{\n\tu8\tis_in_lpspg = _FALSE;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(adapter);\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tstruct sta_priv *pstapriv = &adapter->stapriv;\n\tstruct sta_info *psta = NULL;\n\n\tif ((pwrpriv->lps_level == LPS_PG) && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) && (pwrpriv->rpwm <= PS_STATE_S2))\n\t\tis_in_lpspg = _TRUE;\n\tpsta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));\n\n\tif (psta)\n\t\tpsta->cmn.ra_info.disable_ra = (is_in_lpspg) ? _TRUE : _FALSE;\n}\n*/\nvoid rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg)\n{\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n\t/*u8 rate_id;*/\n\n\tif(sta == NULL) {\n\t\tRTW_ERR(\"%s sta is null\\n\", __func__);\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tif (in_lpspg) {\n\t\tsta->cmn.ra_info.disable_ra = _TRUE;\n\t\tsta->cmn.ra_info.disable_pt = _TRUE;\n\t\t/*TODO : DRV fix tx rate*/\n\t\t/*rate_id = phydm_get_rate_from_rssi_lv(phydm, sta->cmn.mac_id);*/\n\t} else {\n\t\tsta->cmn.ra_info.disable_ra = _FALSE;\n\t\tsta->cmn.ra_info.disable_pt = _FALSE;\n\t}\n\n\trtw_phydm_ra_registed(adapter, sta);\n}\n#endif\n\n/*#define DBG_PHYDM_STATE_CHK*/\n\n\nstatic u8 _rtw_phydm_rfk_condition_check(_adapter *adapter, u8 is_scaning, u8 ifs_linked)\n{\n\tu8 rfk_allowed = _TRUE;\n\n\t#ifdef CONFIG_SKIP_RFK_IN_DM\n\trfk_allowed = _FALSE;\n\tif (0)\n\t\tRTW_ERR(\"[RFK-CHK] RF-K not allowed due to CONFIG_SKIP_RFK_IN_DM\\n\");\n\treturn rfk_allowed;\n\t#endif\n\n\t#ifdef CONFIG_MCC_MODE\n\t/*not in MCC State*/\n\tif (MCC_EN(adapter) && \n\t\trtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {\n\t\trfk_allowed = _FALSE;\n\t\tif (0)\n\t\t\tRTW_INFO(\"[RFK-CHK] RF-K not allowed due to doing MCC\\n\");\n\t\treturn rfk_allowed;\n\t}\n\t#endif\n\n\t#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)\n\n\t#endif\n\n\tif (ifs_linked) {\n\t\tif (is_scaning) {\n\t\t\trfk_allowed = _FALSE;\n\t\t\tRTW_DBG(\"[RFK-CHK] RF-K not allowed due to ifaces under site-survey\\n\");\n\t\t}\n\t\telse {\n\t\t\trfk_allowed = rtw_mi_stayin_union_ch_chk(adapter) ? _TRUE : _FALSE;\n\t\t\tif (rfk_allowed == _FALSE)\n\t\t\t\tRTW_ERR(\"[RFK-CHK] RF-K not allowed due to ld_iface not stayin union ch\\n\");\n\t\t}\n\t}\n\n\treturn rfk_allowed;\n}\n\n#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))\nstatic u8 _rtw_phydm_iqk_segment_chk(_adapter *adapter, u8 ifs_linked)\n{\n\tu8 iqk_sgt = _FALSE;\n\n#if 0\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tif (ifs_linked && (dvobj->traffic_stat.cur_tx_tp > 2 || dvobj->traffic_stat.cur_rx_tp > 2))\n\t\trst = _TRUE;\n#else\n\tif (ifs_linked)\n\t\tiqk_sgt = _TRUE;\n#endif\n\treturn iqk_sgt;\n}\n#endif\n\n/*check the tx low rate while unlinked to any AP;for pwr tracking */\nstatic u8 _rtw_phydm_pwr_tracking_rate_check(_adapter *adapter)\n{\n\tint i;\n\t_adapter *iface;\n\tu8\t\tif_tx_rate = 0xFF;\n\tu8\t\ttx_rate = 0xFF;\n\tstruct mlme_ext_priv\t*pmlmeext = NULL;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tpmlmeext = &(iface->mlmeextpriv);\n\t\tif ((iface) && rtw_is_adapter_up(iface)) {\n#ifdef CONFIG_P2P\n\t\t\tif (!rtw_p2p_chk_role(&(iface)->wdinfo, P2P_ROLE_DISABLE))\n\t\t\t\tif_tx_rate = IEEE80211_OFDM_RATE_6MB;\n\t\t\telse\n#endif\n\t\t\t\tif_tx_rate = pmlmeext->tx_rate;\n\t\t\tif(if_tx_rate < tx_rate)\n\t\t\t\ttx_rate = if_tx_rate;\n\n\t\t\tRTW_DBG(\"%s i=%d tx_rate =0x%x\\n\", __func__, i, if_tx_rate);\n\t\t}\n\t}\n\tRTW_DBG(\"%s tx_low_rate (unlinked to any AP)=0x%x\\n\", __func__, tx_rate);\n\treturn tx_rate;\n}\n\n#ifdef CONFIG_DYNAMIC_SOML\nvoid rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size)\n{\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n\n\tphydm_soml_bytes_acq(phydm, data_rate, size);\n}\n\nvoid rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl,\n\t\t\tu8 period, u8 delay)\n{\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n\n\tphydm_adaptive_soml_para_set(phydm, train_num, intvl, period, delay);\n\tRTW_INFO(\"%s.\\n\", __func__);\n}\n\nvoid rtw_dyn_soml_config(_adapter *adapter)\n{\n\tRTW_INFO(\"%s.\\n\", __func__);\n\n\tif (adapter->registrypriv.dyn_soml_en == 1) {\n\t\t/* Must after phydm_adaptive_soml_init() */\n\t\trtw_hal_set_hwreg(adapter , HW_VAR_SET_SOML_PARAM , NULL);\n\t\tRTW_INFO(\"dyn_soml_en = 1\\n\");\n\t} else {\n\t\tif (adapter->registrypriv.dyn_soml_en == 2) {\n\t\t\trtw_dyn_soml_para_set(adapter, \n\t\t\t\tadapter->registrypriv.dyn_soml_train_num, \n\t\t\t\tadapter->registrypriv.dyn_soml_interval, \n\t\t\t\tadapter->registrypriv.dyn_soml_period,\n\t\t\t\tadapter->registrypriv.dyn_soml_delay);\n\t\t\tRTW_INFO(\"dyn_soml_en = 2\\n\");\n\t\t\tRTW_INFO(\"dyn_soml_en, param = %d, %d, %d, %d\\n\",\n\t\t\t\tadapter->registrypriv.dyn_soml_train_num,\n\t\t\t\tadapter->registrypriv.dyn_soml_interval, \n\t\t\t\tadapter->registrypriv.dyn_soml_period,\n\t\t\t\tadapter->registrypriv.dyn_soml_delay);\n\t\t} else if (adapter->registrypriv.dyn_soml_en == 0) {\n\t\t\tRTW_INFO(\"dyn_soml_en = 0\\n\");\n\t\t} else\n\t\t\tRTW_ERR(\"%s, wrong setting: dyn_soml_en = %d\\n\", __func__,\n\t\t\t\tadapter->registrypriv.dyn_soml_en);\n\t}\n}\n#endif\n\n#ifdef RTW_DYNAMIC_RRSR\nvoid rtw_phydm_set_rrsr(_adapter *adapter, u32 rrsr_value, bool write_rrsr)\n{\n\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n\n\todm_cmn_info_update(phydm, ODM_CMNINFO_RRSR_VAL, rrsr_value);\n\tif(write_rrsr)\n\t\tphydm_rrsr_set_register(phydm, rrsr_value);\n}\n#endif/*RTW_DYNAMIC_RRSR*/\nvoid rtw_phydm_read_efuse(_adapter *adapter)\n{\n\tPHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);\n\tstruct dm_struct *phydm = &(hal_data->odmpriv);\n\n\t/*PHYDM API - thermal trim*/\n\tphydm_get_thermal_trim_offset(phydm);\n\t/*PHYDM API - power trim*/\n\tphydm_get_power_trim_offset(phydm);\n}\n\n#ifdef CONFIG_LPS_PWR_TRACKING\nvoid rtw_phydm_pwr_tracking_directly(_adapter *adapter)\n{\n\tPHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);\n\tu8 rfk_forbidden = _TRUE;\n\tu8 is_linked = _FALSE;\n\n\tif (rtw_mi_check_status(adapter, MI_ASSOC))\n\t\tis_linked = _TRUE;\n\n\trfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, hal_data->bScanInProcess, is_linked) == _TRUE) ? _FALSE : _TRUE;\n\thalrf_cmn_info_set(&hal_data->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);\n\n\todm_txpowertracking_direct_ce(&hal_data->odmpriv);\n}\n#endif\n\nvoid rtw_phydm_watchdog(_adapter *adapter, bool in_lps)\n{\n\tu8\tbLinked = _FALSE;\n\tu8\tbsta_state = _FALSE;\n\tu8\tbBtDisabled = _TRUE;\n\tu8\trfk_forbidden = _FALSE;\n\t#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))\n\tu8\tsegment_iqk = _FALSE;\n\t#endif\n\tu8\ttx_unlinked_low_rate = 0xFF;\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(adapter);\n\n\tif (!rtw_is_hw_init_completed(adapter)) {\n\t\tRTW_DBG(\"%s skip due to hw_init_completed == FALSE\\n\", __func__);\n\t\treturn;\n\t}\n\tif (rtw_mi_check_fwstate(adapter, _FW_UNDER_SURVEY))\n\t\tpHalData->bScanInProcess = _TRUE;\n\telse\n\t\tpHalData->bScanInProcess = _FALSE;\n\n\tif (rtw_mi_check_status(adapter, MI_ASSOC)) {\n\t\tbLinked = _TRUE;\n\t\tif (rtw_mi_check_status(adapter, MI_STA_LINKED))\n\t\tbsta_state = _TRUE;\n\t}\n\n\todm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked);\n\todm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state);\n\n\t#ifdef CONFIG_BT_COEXIST\n\tbBtDisabled = rtw_btcoex_IsBtDisabled(adapter);\n\t#endif /* CONFIG_BT_COEXIST */\n\todm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED,\n\t\t\t\t\t\t\t(bBtDisabled == _TRUE) ? _FALSE : _TRUE);\n\n\trfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, pHalData->bScanInProcess, bLinked) == _TRUE) ? _FALSE : _TRUE;\n\thalrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);\n\n\t#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))\n\tsegment_iqk = _rtw_phydm_iqk_segment_chk(adapter, bLinked);\n\thalrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_IQK_SEGMENT, segment_iqk);\n\t#endif\n\t#ifdef DBG_PHYDM_STATE_CHK\n\tRTW_INFO(\"%s rfk_forbidden = %s, segment_iqk = %s\\n\",\n\t\t\t__func__, (rfk_forbidden) ? \"Y\" : \"N\", (segment_iqk) ? \"Y\" : \"N\");\n\t#endif\n\n\tif (bLinked == _FALSE) {\n\t\ttx_unlinked_low_rate = _rtw_phydm_pwr_tracking_rate_check(adapter);\n\t\thalrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RATE_INDEX, tx_unlinked_low_rate);\n\t}\n\n\t/*if (!rtw_mi_stayin_union_band_chk(adapter)) {\n\t\t#ifdef DBG_PHYDM_STATE_CHK\n\t\tRTW_ERR(\"Not stay in union band, skip phydm\\n\");\n\t\t#endif\n\t\tgoto _exit;\n\t}*/\n\n\t#ifdef CONFIG_TDMADIG\n\trtw_phydm_tdmadig(adapter, TDMADIG_NON_INIT);\n\t#endif/*CONFIG_TDMADIG*/\n\n\tif (in_lps)\n\t\tphydm_watchdog_lps(&pHalData->odmpriv);\n\telse\n\t\tphydm_watchdog(&pHalData->odmpriv);\n\n\t#ifdef CONFIG_RTW_ACS\n\trtw_acs_update_current_info(adapter);\n\t#endif\n\n\treturn;\n}\n\n#ifdef CONFIG_CTRL_TXSS_BY_TP\nvoid rtw_phydm_trx_cfg(_adapter *adapter, bool tx_1ss)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tenum bb_path txpath = BB_PATH_AB;\n\tenum bb_path rxpath = BB_PATH_AB;\n\t/*is_2tx = _FALSE for 8822B, or BB_PATH_AUTO for PATH_DIVERSITY for 8822B*/\n\tenum bb_path txpath_1ss = BB_PATH_A;\n\n\trtw_hal_get_rf_path(adapter_to_dvobj(adapter), NULL, &txpath, &rxpath);\n\ttxpath = (tx_1ss) ? BB_PATH_A : txpath;\n\n\tif (phydm_api_trx_mode(adapter_to_phydm(adapter), txpath, rxpath, txpath_1ss) == FALSE)\n\t\tRTW_ERR(\"%s failed\\n\", __func__);\n}\n#endif\n\n"
  },
  {
    "path": "hal/hal_dm.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HAL_DM_H__\n#define __HAL_DM_H__\n\n#define adapter_to_phydm(adapter) (&(GET_HAL_DATA(adapter)->odmpriv))\n#define dvobj_to_phydm(dvobj) adapter_to_phydm(dvobj_get_primary_adapter(dvobj))\n#ifdef CONFIG_TDMADIG\nvoid rtw_phydm_tdmadig(_adapter *adapter, u8 state);\n#endif\nvoid rtw_phydm_priv_init(_adapter *adapter);\nvoid Init_ODM_ComInfo(_adapter *adapter);\nvoid rtw_phydm_init(_adapter *adapter);\n\nvoid rtw_hal_turbo_edca(_adapter *adapter);\nu8 rtw_phydm_is_iqk_in_progress(_adapter *adapter);\n\nvoid GetHalODMVar(\n\tPADAPTER\t\t\t\tAdapter,\n\tHAL_ODM_VARIABLE\t\teVariable,\n\tvoid\t\t\t\t\t\t*pValue1,\n\tvoid\t\t\t\t\t\t*pValue2);\nvoid SetHalODMVar(\n\tPADAPTER\t\t\t\tAdapter,\n\tHAL_ODM_VARIABLE\t\teVariable,\n\tvoid\t\t\t\t\t\t*pValue1,\n\tBOOLEAN\t\t\t\t\tbSet);\n\nvoid rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta);\n\n#ifdef CONFIG_DYNAMIC_SOML\nvoid rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size);\nvoid rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl,\n\t\t\tu8 period, u8 delay);\nvoid rtw_dyn_soml_config(_adapter *adapter);\n#endif\n#ifdef RTW_DYNAMIC_RRSR\nvoid rtw_phydm_set_rrsr(_adapter *adapter, u32 rrsr_value, bool write_rrsr);\n#endif\nvoid rtw_phydm_watchdog(_adapter *adapter, bool in_lps);\n\nvoid rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter);\nvoid dump_sta_info(void *sel, struct sta_info *psta);\nvoid dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta);\n\n#ifdef CONFIG_DBG_RF_CAL\nvoid rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment);\nvoid rtw_hal_lck_test(_adapter *adapter);\n#endif\n\ns8 rtw_dm_get_min_rssi(_adapter *adapter);\ns8 rtw_phydm_get_min_rssi(_adapter *adapter);\nu8 rtw_phydm_get_cur_igi(_adapter *adapter);\nbool rtw_phydm_get_edcca_flag(_adapter *adapter);\n\n\n#ifdef CONFIG_LPS_LCLK_WD_TIMER\nextern void phydm_rssi_monitor_check(void *p_dm_void);\n\nvoid rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter);\nvoid rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter);\n#endif\n#ifdef CONFIG_TDMADIG\nenum rtw_tdmadig_state{\n\tTDMADIG_INIT,\n\tTDMADIG_NON_INIT,\n};\n#endif\nenum phy_cnt {\n\tFA_OFDM,\n\tFA_CCK,\n\tFA_TOTAL,\n\tCCA_OFDM,\n\tCCA_CCK,\n\tCCA_ALL,\n\tCRC32_OK_VHT,\n\tCRC32_OK_HT,\n\tCRC32_OK_LEGACY,\n\tCRC32_OK_CCK,\n\tCRC32_ERROR_VHT,\n\tCRC32_ERROR_HT,\n\tCRC32_ERROR_LEGACY,\n\tCRC32_ERROR_CCK,\n};\nu32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt);\n#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))\nvoid rtw_phydm_iqk_trigger(_adapter *adapter);\n#endif\nvoid rtw_phydm_read_efuse(_adapter *adapter);\nbool rtw_phydm_set_crystal_cap(_adapter *adapter, u8 crystal_cap);\n\n#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR\nvoid rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id);\n#endif\n#ifdef CONFIG_RTW_TX_2PATH_EN\nvoid rtw_phydm_tx_2path_en(_adapter *adapter);\n#endif\n#ifdef CONFIG_LPS_PG\nvoid rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg);\n#endif\n#ifdef CONFIG_LPS_PWR_TRACKING\nvoid rtw_phydm_pwr_tracking_directly(_adapter *adapter);\n#endif\n\n#ifdef CONFIG_CTRL_TXSS_BY_TP\nvoid rtw_phydm_trx_cfg(_adapter *adapter, bool tx_1ss);\n#endif\n\n#endif /* __HAL_DM_H__ */\n"
  },
  {
    "path": "hal/hal_dm_acs.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2014 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#include <drv_types.h>\n#include <hal_data.h>\n\n\n#if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)\nstatic void _rtw_bss_nums_count(_adapter *adapter, u8 *pbss_nums)\n{\n\tstruct mlme_priv\t*pmlmepriv = &(adapter->mlmepriv);\n\t_queue *queue = &(pmlmepriv->scanned_queue);\n\tstruct wlan_network *pnetwork = NULL;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\n\t_list\t*plist, *phead;\n\t_irqL irqL;\n\tint chan_idx = -1;\n\n\tif (pbss_nums == NULL) {\n\t\tRTW_ERR(\"%s pbss_nums is null pointer\\n\", __func__);\n\t\treturn;\n\t}\n\t_rtw_memset(pbss_nums, 0, MAX_CHANNEL_NUM);\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\twhile (1) {\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\t\tif (!pnetwork)\n\t\t\tbreak;\n\t\tchan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), pnetwork->network.Configuration.DSConfig);\n\t\tif ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {\n\t\t\tRTW_ERR(\"%s can't get chan_idx(CH:%d)\\n\",\n\t\t\t\t__func__, pnetwork->network.Configuration.DSConfig);\n\t\t\tchan_idx = 0;\n\t\t}\n\t\t/*if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ)*/\n\n\t\tpbss_nums[chan_idx]++;\n\n\t\tplist = get_next(plist);\n\t}\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n}\n\nu8 rtw_get_ch_num_by_idx(_adapter *adapter, u8 idx)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tRT_CHANNEL_INFO *pch_set = rfctl->channel_set;\n\tu8 max_chan_nums = rfctl->max_chan_nums;\n\n\tif (idx >= max_chan_nums)\n\t\treturn 0;\n\treturn pch_set[idx].ChannelNum;\n}\n#endif /*defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)*/\n\n\n#ifdef CONFIG_RTW_ACS\nvoid rtw_acs_version_dump(void *sel, _adapter *adapter)\n{\n\t_RTW_PRINT_SEL(sel, \"RTK_ACS VER_%d\\n\", RTK_ACS_VERSION);\n}\nu8 rtw_phydm_clm_ratio(_adapter *adapter)\n{\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n\n\treturn phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CLM_RATIO);\n}\nu8 rtw_phydm_nhm_ratio(_adapter *adapter)\n{\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n\n\treturn phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_NHM_RATIO);\n}\nvoid rtw_acs_reset(_adapter *adapter)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct auto_chan_sel *pacs = &hal_data->acs;\n\n\t_rtw_memset(pacs, 0, sizeof(struct auto_chan_sel));\n\t#ifdef CONFIG_RTW_ACS_DBG\n\trtw_acs_adv_reset(adapter);\n\t#endif /*CONFIG_RTW_ACS_DBG*/\n}\n\n#ifdef CONFIG_RTW_ACS_DBG\nu8 rtw_is_acs_igi_valid(_adapter *adapter)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct auto_chan_sel *pacs = &hal_data->acs;\n\n\tif ((pacs->igi) && ((pacs->igi >= 0x1E) || (pacs->igi < 0x60)))\n\t\treturn _TRUE;\n\n\treturn _FALSE;\n}\nvoid rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct auto_chan_sel *pacs = &hal_data->acs;\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;\n\n\tpacs->scan_type = scan_type;\n\tpacs->scan_time = scan_time;\n\tpacs->igi = igi;\n\tpacs->bw = bw;\n\tRTW_INFO(\"[ACS] ADV setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\\n\",\n\t\tpacs->scan_type ? 'A' : 'P', pacs->scan_time, pacs->igi, pacs->bw);\n}\nvoid rtw_acs_adv_reset(_adapter *adapter)\n{\n\trtw_acs_adv_setting(adapter, SCAN_ACTIVE, 0, 0, 0);\n}\n#endif /*CONFIG_RTW_ACS_DBG*/\n\nvoid rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n#if (RTK_ACS_VERSION == 3)\n\tstruct clm_para_info clm_para;\n\tstruct nhm_para_info nhm_para;\n\tstruct env_trig_rpt trig_rpt;\n\n\tscan_time_ms -= 10;\n\n\tinit_acs_clm(clm_para, scan_time_ms);\n\n\tif (pid == NHM_PID_IEEE_11K_HIGH)\n\t\tinit_11K_high_nhm(nhm_para, scan_time_ms);\n\telse if (pid == NHM_PID_IEEE_11K_LOW)\n\t\tinit_11K_low_nhm(nhm_para, scan_time_ms);\n\telse\n\t\tinit_acs_nhm(nhm_para, scan_time_ms);\n\n\thal_data->acs.trig_rst = phydm_env_mntr_trigger(phydm, &nhm_para, &clm_para, &trig_rpt);\n\tif (hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS)) {\n\t\thal_data->acs.trig_rpt.clm_rpt_stamp = trig_rpt.clm_rpt_stamp;\n\t\thal_data->acs.trig_rpt.nhm_rpt_stamp = trig_rpt.nhm_rpt_stamp;\n\t\t/*RTW_INFO(\"[ACS] trigger success (rst = 0x%02x, clm_stamp:%d, nhm_stamp:%d)\\n\",\n\t\t\thal_data->acs.trig_rst, hal_data->acs.trig_rpt.clm_rpt_stamp, hal_data->acs.trig_rpt.nhm_rpt_stamp);*/\n\t} else\n\t\tRTW_ERR(\"[ACS] trigger failed (rst = 0x%02x)\\n\", hal_data->acs.trig_rst);\n#else\n\tphydm_ccx_monitor_trigger(phydm, scan_time_ms);\n#endif\n\n\thal_data->acs.trigger_ch = scan_chan;\n\thal_data->acs.triggered = _TRUE;\n\n\t#ifdef CONFIG_RTW_ACS_DBG\n\tRTW_INFO(\"[ACS] Trigger CH:%d, Times:%d\\n\", hal_data->acs.trigger_ch, scan_time_ms);\n\t#endif\n}\nvoid rtw_acs_get_rst(_adapter *adapter)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n\tint chan_idx = -1;\n\tu8 cur_chan = hal_data->acs.trigger_ch;\n\n\tif (cur_chan == 0)\n\t\treturn;\n\n\tif (!hal_data->acs.triggered)\n\t\treturn;\n\n\tchan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), cur_chan);\n\tif ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {\n\t\tRTW_ERR(\"[ACS] %s can't get chan_idx(CH:%d)\\n\", __func__, cur_chan);\n\t\treturn;\n\t}\n#if (RTK_ACS_VERSION == 3)\n\tif (!(hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS))) {\n\t\tRTW_ERR(\"[ACS] get_rst return, due to acs trigger failed\\n\");\n\t\treturn;\n\t}\n\n\t{\n\t\tstruct env_mntr_rpt rpt = {0};\n\t\tu8 rst;\n\n\t\trst = phydm_env_mntr_result(phydm, &rpt);\n\t\tif ((rst == (NHM_SUCCESS | CLM_SUCCESS)) &&\n\t\t\t(rpt.clm_rpt_stamp == hal_data->acs.trig_rpt.clm_rpt_stamp) &&\n\t\t\t(rpt.nhm_rpt_stamp == hal_data->acs.trig_rpt.nhm_rpt_stamp)){\n\t\t\thal_data->acs.clm_ratio[chan_idx] = rpt.clm_ratio;\n\t\t\thal_data->acs.nhm_ratio[chan_idx] = rpt.nhm_ratio;\n\t\t\t_rtw_memcpy(&hal_data->acs.nhm[chan_idx][0], rpt.nhm_result, NHM_RPT_NUM);\n\n\t\t\t/*RTW_INFO(\"[ACS] get_rst success (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\\n\",\n\t\t\trst,\n\t\t\thal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp,\n\t\t\thal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp);*/\n\t\t} else {\n\t\t\tRTW_ERR(\"[ACS] get_rst failed (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\\n\",\n\t\t\trst,\n\t\t\thal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp,\n\t\t\thal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp);\n\t\t}\n\t}\n\n#else\n\tphydm_ccx_monitor_result(phydm);\n\n\thal_data->acs.clm_ratio[chan_idx] = rtw_phydm_clm_ratio(adapter);\n\thal_data->acs.nhm_ratio[chan_idx] = rtw_phydm_nhm_ratio(adapter);\n#endif\n\thal_data->acs.triggered = _FALSE;\n\t#ifdef CONFIG_RTW_ACS_DBG\n\tRTW_INFO(\"[ACS] Result CH:%d, CLM:%d NHM:%d\\n\",\n\t\tcur_chan, hal_data->acs.clm_ratio[chan_idx], hal_data->acs.nhm_ratio[chan_idx]);\n\t#endif\n}\n\nvoid _rtw_phydm_acs_select_best_chan(_adapter *adapter)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tu8 ch_idx;\n\tu8 ch_idx_24g = 0xFF, ch_idx_5g = 0xFF;\n\tu8 min_itf_24g = 0xFF,  min_itf_5g = 0xFF;\n\tu8 *pbss_nums = hal_data->acs.bss_nums;\n\tu8 *pclm_ratio = hal_data->acs.clm_ratio;\n\tu8 *pnhm_ratio = hal_data->acs.nhm_ratio;\n\tu8 *pinterference_time = hal_data->acs.interference_time;\n\tu8 max_chan_nums = rfctl->max_chan_nums;\n\n\tfor (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {\n\t\tif (pbss_nums[ch_idx])\n\t\t\tpinterference_time[ch_idx] = (pclm_ratio[ch_idx] / 2) + pnhm_ratio[ch_idx];\n\t\telse\n\t\t\tpinterference_time[ch_idx] = pclm_ratio[ch_idx] + pnhm_ratio[ch_idx];\n\n\t\tif (rtw_get_ch_num_by_idx(adapter, ch_idx) < 14) {\n\t\t\tif (pinterference_time[ch_idx] < min_itf_24g) {\n\t\t\t\tmin_itf_24g = pinterference_time[ch_idx];\n\t\t\t\tch_idx_24g = ch_idx;\n\t\t\t}\n\t\t} else {\n\t\t\tif (pinterference_time[ch_idx] < min_itf_5g) {\n\t\t\t\tmin_itf_5g = pinterference_time[ch_idx];\n\t\t\t\tch_idx_5g = ch_idx;\n\t\t\t}\n\t\t}\n\t}\n\tif (ch_idx_24g != 0xFF)\n\t\thal_data->acs.best_chan_24g = rtw_get_ch_num_by_idx(adapter, ch_idx_24g);\n\n\tif (ch_idx_5g != 0xFF)\n\t\thal_data->acs.best_chan_5g = rtw_get_ch_num_by_idx(adapter, ch_idx_5g);\n\n\thal_data->acs.trigger_ch = 0;\n}\n\nvoid rtw_acs_info_dump(void *sel, _adapter *adapter)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tu8 max_chan_nums = rfctl->max_chan_nums;\n\tu8 ch_idx, ch_num;\n\n\t_RTW_PRINT_SEL(sel, \"========== ACS (VER-%d) ==========\\n\", RTK_ACS_VERSION);\n\t_RTW_PRINT_SEL(sel, \"Best 24G Channel:%d\\n\", hal_data->acs.best_chan_24g);\n\t_RTW_PRINT_SEL(sel, \"Best 5G Channel:%d\\n\\n\", hal_data->acs.best_chan_5g);\n\n\t#ifdef CONFIG_RTW_ACS_DBG\n\t_RTW_PRINT_SEL(sel, \"Advanced setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\\n\",\n\t\thal_data->acs.scan_type ? 'A' : 'P', hal_data->acs.scan_time, hal_data->acs.igi, hal_data->acs.bw);\n\n\t_RTW_PRINT_SEL(sel, \"BW  20MHz\\n\");\n\t_RTW_PRINT_SEL(sel, \"%5s  %3s  %3s  %3s(%%)  %3s(%%)  %3s\\n\",\n\t\t\t\t\t\t\"Index\", \"CH\", \"BSS\", \"CLM\", \"NHM\", \"ITF\");\n\n\tfor (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {\n\t\tch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);\n\t\t_RTW_PRINT_SEL(sel, \"%5d  %3d  %3d  %6d  %6d  %3d\\n\",\n\t\t\t\t\t\tch_idx, ch_num, hal_data->acs.bss_nums[ch_idx],\n\t\t\t\t\t\thal_data->acs.clm_ratio[ch_idx],\n\t\t\t\t\t\thal_data->acs.nhm_ratio[ch_idx],\n\t\t\t\t\t\thal_data->acs.interference_time[ch_idx]);\n\t}\n\t#endif\n}\nvoid rtw_acs_select_best_chan(_adapter *adapter)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\n\t_rtw_bss_nums_count(adapter, hal_data->acs.bss_nums);\n\t_rtw_phydm_acs_select_best_chan(adapter);\n\trtw_acs_info_dump(RTW_DBGDUMP, adapter);\n}\n\nvoid rtw_acs_start(_adapter *adapter)\n{\n\trtw_acs_reset(adapter);\n\tif (GET_ACS_STATE(adapter) != ACS_ENABLE)\n\t\tSET_ACS_STATE(adapter, ACS_ENABLE);\n}\nvoid rtw_acs_stop(_adapter *adapter)\n{\n\tSET_ACS_STATE(adapter, ACS_DISABLE);\n}\n\n\nu8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tint chan_idx = -1;\n\n\tchan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);\n\tif ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {\n\t\tRTW_ERR(\"[ACS] Get CLM fail, can't get chan_idx(CH:%d)\\n\", chan);\n\t\treturn 0;\n\t}\n\n\treturn hal_data->acs.clm_ratio[chan_idx];\n}\nu8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\n\tif (ch_idx >= MAX_CHANNEL_NUM) {\n\t\tRTW_ERR(\"%s [ACS] ch_idx(%d) is invalid\\n\", __func__, ch_idx);\n\t\treturn 0;\n\t}\n\n\treturn hal_data->acs.clm_ratio[ch_idx];\n}\nu8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tint chan_idx = -1;\n\n\tchan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);\n\tif ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {\n\t\tRTW_ERR(\"[ACS] Get NHM fail, can't get chan_idx(CH:%d)\\n\", chan);\n\t\treturn 0;\n\t}\n\n\treturn hal_data->acs.nhm_ratio[chan_idx];\n}\nu8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\n\tif (ch_idx >= MAX_CHANNEL_NUM) {\n\t\tRTW_ERR(\"%s [ACS] ch_idx(%d) is invalid\\n\", __func__, ch_idx);\n\t\treturn 0;\n\t}\n\n\treturn hal_data->acs.nhm_ratio[ch_idx];\n}\nvoid rtw_acs_chan_info_dump(void *sel, _adapter *adapter)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tu8 max_chan_nums = rfctl->max_chan_nums;\n\tu8 ch_idx, ch_num;\n\tu8 utilization;\n\n\t_RTW_PRINT_SEL(sel, \"BW  20MHz\\n\");\n\t_RTW_PRINT_SEL(sel, \"%5s  %3s  %7s(%%)  %12s(%%)  %11s(%%)  %9s(%%)  %8s(%%)\\n\",\n\t\t\t\t\t\t\"Index\", \"CH\", \"Quality\", \"Availability\", \"Utilization\",\n\t\t\t\t\t\t\"WIFI Util\", \"Interference Util\");\n\n\tfor (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {\n\t\tch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);\n\t\tutilization = hal_data->acs.clm_ratio[ch_idx] + hal_data->acs.nhm_ratio[ch_idx];\n\t\t_RTW_PRINT_SEL(sel, \"%5d  %3d  %7d   %12d   %12d   %12d   %12d\\n\",\n\t\t\t\t\t\tch_idx, ch_num,\n\t\t\t\t\t\t(100-hal_data->acs.interference_time[ch_idx]),\n\t\t\t\t\t\t(100-utilization),\n\t\t\t\t\t\tutilization,\n\t\t\t\t\t\thal_data->acs.clm_ratio[ch_idx],\n\t\t\t\t\t\thal_data->acs.nhm_ratio[ch_idx]);\n\t}\n}\nvoid rtw_acs_current_info_dump(void *sel, _adapter *adapter)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tu8 ch, cen_ch, bw, offset;\n\n\t_RTW_PRINT_SEL(sel, \"========== ACS (VER-%d) ==========\\n\", RTK_ACS_VERSION);\n\n\tch = rtw_get_oper_ch(adapter);\n\tbw = rtw_get_oper_bw(adapter);\n\toffset = rtw_get_oper_choffset(adapter);\n\n\t_RTW_PRINT_SEL(sel, \"Current Channel:%d\\n\", ch);\n\tif ((bw == CHANNEL_WIDTH_80) ||(bw == CHANNEL_WIDTH_40)) {\n\t\tcen_ch = rtw_get_center_ch(ch, bw, offset);\n\t\t_RTW_PRINT_SEL(sel, \"Center Channel:%d\\n\", cen_ch);\n\t}\n\n\t_RTW_PRINT_SEL(sel, \"Current BW %s\\n\", ch_width_str(bw));\n\tif (0)\n\t\t_RTW_PRINT_SEL(sel, \"Current IGI 0x%02x\\n\", rtw_phydm_get_cur_igi(adapter));\n\t_RTW_PRINT_SEL(sel, \"CLM:%d, NHM:%d\\n\\n\",\n\t\thal_data->acs.cur_ch_clm_ratio, hal_data->acs.cur_ch_nhm_ratio);\n}\n\nvoid rtw_acs_update_current_info(_adapter *adapter)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\n\thal_data->acs.cur_ch_clm_ratio = rtw_phydm_clm_ratio(adapter);\n\thal_data->acs.cur_ch_nhm_ratio = rtw_phydm_nhm_ratio(adapter);\n\n\t#ifdef CONFIG_RTW_ACS_DBG\n\trtw_acs_current_info_dump(RTW_DBGDUMP, adapter);\n\t#endif\n}\n#endif /*CONFIG_RTW_ACS*/\n\n#ifdef CONFIG_BACKGROUND_NOISE_MONITOR\nvoid rtw_noise_monitor_version_dump(void *sel, _adapter *adapter)\n{\n\t_RTW_PRINT_SEL(sel, \"RTK_NOISE_MONITOR VER_%d\\n\", RTK_NOISE_MONITOR_VERSION);\n}\nvoid rtw_nm_enable(_adapter *adapter)\n{\n\tSET_NM_STATE(adapter, NM_ENABLE);\n}\nvoid rtw_nm_disable(_adapter *adapter)\n{\n\tSET_NM_STATE(adapter, NM_DISABLE);\n}\nvoid rtw_noise_info_dump(void *sel, _adapter *adapter)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tu8 max_chan_nums = rfctl->max_chan_nums;\n\tu8 ch_idx, ch_num;\n\n\t_RTW_PRINT_SEL(sel, \"========== NM (VER-%d) ==========\\n\", RTK_NOISE_MONITOR_VERSION);\n\n\t_RTW_PRINT_SEL(sel, \"%5s  %3s  %3s  %10s\", \"Index\", \"CH\", \"BSS\", \"Noise(dBm)\\n\");\n\n\t_rtw_bss_nums_count(adapter, hal_data->nm.bss_nums);\n\n\tfor (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {\n\t\tch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);\n\t\t_RTW_PRINT_SEL(sel, \"%5d  %3d  %3d  %10d\\n\",\n\t\t\t\t\t\tch_idx, ch_num, hal_data->nm.bss_nums[ch_idx],\n\t\t\t\t\t\thal_data->nm.noise[ch_idx]);\n\t}\n}\n\nvoid rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct dm_struct *phydm = &hal_data->odmpriv;\n\tint chan_idx = -1;\n\ts16 noise = 0;\n\n\t#ifdef DBG_NOISE_MONITOR\n\tRTW_INFO(\"[NM] chan(%d)-PauseDIG:%s,  IGIValue:0x%02x, max_time:%d (ms)\\n\",\n\t\tchan, (is_pause_dig) ? \"Y\" : \"N\", igi_value, max_time);\n\t#endif\n\n\tchan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);\n\tif ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {\n\t\tRTW_ERR(\"[NM] Get noise fail, can't get chan_idx(CH:%d)\\n\", chan);\n\t\treturn;\n\t}\n\tnoise = odm_inband_noise_monitor(phydm, is_pause_dig, igi_value, max_time); /*dBm*/\n\n\thal_data->nm.noise[chan_idx] = noise;\n\n\t#ifdef DBG_NOISE_MONITOR\n\tRTW_INFO(\"[NM] %s chan_%d, noise = %d (dBm)\\n\", __func__, chan, hal_data->nm.noise[chan_idx]);\n\n\tRTW_INFO(\"[NM] noise_a = %d, noise_b = %d  noise_all:%d\\n\",\n\t\t\t phydm->noise_level.noise[RF_PATH_A],\n\t\t\t phydm->noise_level.noise[RF_PATH_B],\n\t\t\t phydm->noise_level.noise_all);\n\t#endif /*DBG_NOISE_MONITOR*/\n}\n\ns16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\ts16 noise = 0;\n\tint chan_idx = -1;\n\n\tchan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);\n\tif ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {\n\t\tRTW_ERR(\"[NM] Get noise fail, can't get chan_idx(CH:%d)\\n\", chan);\n\t\treturn noise;\n\t}\n\tnoise = hal_data->nm.noise[chan_idx];\n\n\t#ifdef DBG_NOISE_MONITOR\n\tRTW_INFO(\"[NM] %s chan_%d, noise = %d (dBm)\\n\", __func__, chan, noise);\n\t#endif/*DBG_NOISE_MONITOR*/\n\treturn noise;\n}\ns16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\ts16 noise = 0;\n\n\tif (ch_idx >= MAX_CHANNEL_NUM) {\n\t\tRTW_ERR(\"[NM] %s ch_idx(%d) is invalid\\n\", __func__, ch_idx);\n\t\treturn noise;\n\t}\n\tnoise = hal_data->nm.noise[ch_idx];\n\n\t#ifdef DBG_NOISE_MONITOR\n\tRTW_INFO(\"[NM] %s ch_idx %d, noise = %d (dBm)\\n\", __func__, ch_idx, noise);\n\t#endif/*DBG_NOISE_MONITOR*/\n\treturn noise;\n}\n\ns16 rtw_noise_measure_curchan(_adapter *padapter)\n{\n\ts16 noise = 0;\n\tu8 igi_value = 0x1E;\n\tu32 max_time = 100;/* ms */\n\tu8 is_pause_dig = _TRUE;\n\tu8 cur_chan = rtw_get_oper_ch(padapter);\n\n\tif (rtw_linked_check(padapter) == _FALSE)\n\t\treturn noise;\n\n\trtw_ps_deny(padapter, PS_DENY_IOCTL);\n\tLeaveAllPowerSaveModeDirect(padapter);\n\trtw_noise_measure(padapter, cur_chan, is_pause_dig, igi_value, max_time);\n\tnoise = rtw_noise_query_by_chan_num(padapter, cur_chan);\n\trtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);\n\n\treturn noise;\n}\n#endif /*CONFIG_BACKGROUND_NOISE_MONITOR*/\n\n"
  },
  {
    "path": "hal/hal_dm_acs.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HAL_DM_ACS_H__\n#define __HAL_DM_ACS_H__\n#ifdef CONFIG_RTW_ACS\n#define RTK_ACS_VERSION\t3\n\n#if (RTK_ACS_VERSION == 3)\nenum NHM_PID {\n\tNHM_PID_ACS,\n\tNHM_PID_IEEE_11K_HIGH,\n\tNHM_PID_IEEE_11K_LOW,\n};\n\n#define init_clm_param(clm, app, lv, time) \\\n\tdo {\\\n\t\tclm.clm_app = app;\\\n\t\tclm.clm_lv = lv;\\\n\t\tclm.mntr_time = time;\\\n\t} while (0)\n\n#define init_nhm_param(nhm, txon, cca, cnt_opt, app, lv, time) \\\n\tdo {\\\n\t\tnhm.incld_txon = txon;\\\n\t\tnhm.incld_cca = cca;\\\n\t\tnhm.div_opt = cnt_opt;\\\n\t\tnhm.nhm_app = app;\\\n\t\tnhm.nhm_lv = lv;\\\n\t\tnhm.mntr_time = time;\\\n\t} while (0)\n\n\t\n#define init_acs_clm(clm, time) \\\n\tinit_clm_param(clm, CLM_ACS, CLM_LV_2, time)\n\n#define init_acs_nhm(nhm, time) \\\n\tinit_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, NHM_ACS, NHM_LV_2, time)\n\n#define init_11K_high_nhm(nhm, time) \\\n\tinit_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_HIGH, NHM_LV_2, time)\n\t\n#define init_11K_low_nhm(nhm, time) \\\n\t\tinit_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_LOW, NHM_LV_2, time)\n\n\n#endif /*(RTK_ACS_VERSION == 3)*/\nvoid rtw_acs_version_dump(void *sel, _adapter *adapter);\nextern void phydm_ccx_monitor_trigger(void *p_dm_void, u16 monitor_time);\nextern void phydm_ccx_monitor_result(void *p_dm_void);\n\n#define GET_ACS_STATE(padapter)\t\t\t\t\t(ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state))\n#define SET_ACS_STATE(padapter, set_state)\t\t\t(ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state))\n#define IS_ACS_ENABLE(padapter)\t\t\t\t\t((GET_ACS_STATE(padapter) == ACS_ENABLE) ? _TRUE : _FALSE)\n\nenum ACS_STATE {\n\tACS_DISABLE,\n\tACS_ENABLE,\n};\n\n#define ACS_BW_20M\tBIT(0)\n#define ACS_BW_40M\tBIT(1)\n#define ACS_BW_80M\tBIT(2)\n#define ACS_BW_160M\tBIT(3)\n\nstruct auto_chan_sel {\n\tATOMIC_T state;\n\tu8 trigger_ch;\n\tbool triggered;\n\tu8 clm_ratio[MAX_CHANNEL_NUM];\n\tu8 nhm_ratio[MAX_CHANNEL_NUM];\n\t#if (RTK_ACS_VERSION == 3)\n\tu8 nhm[MAX_CHANNEL_NUM][NHM_RPT_NUM];\n\t#endif\n\tu8 bss_nums[MAX_CHANNEL_NUM];\n\tu8 interference_time[MAX_CHANNEL_NUM];\n\tu8 cur_ch_clm_ratio;\n\tu8 cur_ch_nhm_ratio;\n\tu8 best_chan_5g;\n\tu8 best_chan_24g;\n\n\t#if (RTK_ACS_VERSION == 3)\n\tu8 trig_rst;\n\tstruct env_trig_rpt\ttrig_rpt;\n\t#endif\n\n\t#ifdef CONFIG_RTW_ACS_DBG\n\tRT_SCAN_TYPE scan_type;\n\tu16 scan_time;\n\tu8 igi;\n\tu8 bw;\n\t#endif\n};\n\n#define rtw_acs_get_best_chan_24g(adapter)\t\t(GET_HAL_DATA(adapter)->acs.best_chan_24g)\n#define rtw_acs_get_best_chan_5g(adapter)\t\t(GET_HAL_DATA(adapter)->acs.best_chan_5g)\n\n#ifdef CONFIG_RTW_ACS_DBG\n#define rtw_is_acs_passiv_scan(adapter)\t(((GET_HAL_DATA(adapter)->acs.scan_type) == SCAN_PASSIVE) ? _TRUE : _FALSE)\n\n#define rtw_acs_get_adv_st(adapter)\t(GET_HAL_DATA(adapter)->acs.scan_time)\n#define rtw_is_acs_st_valid(adapter)\t((GET_HAL_DATA(adapter)->acs.scan_time) ? _TRUE : _FALSE)\n\n#define rtw_acs_get_adv_igi(adapter)\t(GET_HAL_DATA(adapter)->acs.igi)\nu8 rtw_is_acs_igi_valid(_adapter *adapter);\n\n#define rtw_acs_get_adv_bw(adapter)\t(GET_HAL_DATA(adapter)->acs.bw)\n\nvoid rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw);\nvoid rtw_acs_adv_reset(_adapter *adapter);\n#endif\n\nu8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan);\nu8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx);\nu8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan);\nu8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx);\n\nvoid rtw_acs_reset(_adapter *adapter);\nvoid rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid);\nvoid rtw_acs_get_rst(_adapter *adapter);\nvoid rtw_acs_select_best_chan(_adapter *adapter);\nvoid rtw_acs_info_dump(void *sel, _adapter *adapter);\nvoid rtw_acs_update_current_info(_adapter *adapter);\nvoid rtw_acs_chan_info_dump(void *sel, _adapter *adapter);\nvoid rtw_acs_current_info_dump(void *sel, _adapter *adapter);\n\nvoid rtw_acs_start(_adapter *adapter);\nvoid rtw_acs_stop(_adapter *adapter);\n\n#endif /*CONFIG_RTW_ACS*/\n\n#ifdef CONFIG_BACKGROUND_NOISE_MONITOR\n#define RTK_NOISE_MONITOR_VERSION\t3\n#define GET_NM_STATE(padapter)\t\t\t\t\t(ATOMIC_READ(&GET_HAL_DATA(padapter)->nm.state))\n#define SET_NM_STATE(padapter, set_state)\t\t\t(ATOMIC_SET(&GET_HAL_DATA(padapter)->nm.state, set_state))\n#define IS_NM_ENABLE(padapter)\t\t\t\t\t((GET_NM_STATE(padapter) == NM_ENABLE) ? _TRUE : _FALSE)\n\nenum NM_STATE {\n\tNM_DISABLE,\n\tNM_ENABLE,\n};\n\nstruct noise_monitor {\n\tATOMIC_T state;\n\ts16 noise[MAX_CHANNEL_NUM];\n\tu8 bss_nums[MAX_CHANNEL_NUM];\n};\nvoid rtw_nm_enable(_adapter *adapter);\nvoid rtw_nm_disable(_adapter *adapter);\nvoid rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time);\ns16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan);\ns16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx);\ns16 rtw_noise_measure_curchan(_adapter *padapter);\nvoid rtw_noise_info_dump(void *sel, _adapter *adapter);\n#endif\n#endif /* __HAL_DM_ACS_H__ */\n"
  },
  {
    "path": "hal/hal_halmac.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2019 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _HAL_HALMAC_C_\n\n#include <drv_types.h>\t\t/* PADAPTER, struct dvobj_priv, SDIO_ERR_VAL8 and etc. */\n#include <hal_data.h>\t\t/* efuse, PHAL_DATA_TYPE and etc. */\n#include \"hal_halmac.h\"\t\t/* dvobj_to_halmac() and ect. */\n\n/*\n * HALMAC take return value 0 for fail and 1 for success to replace\n * _FALSE/_TRUE after V1_04_09\n */\n#define RTW_HALMAC_FAIL\t\t\t0\n#define RTW_HALMAC_SUCCESS\t\t1\n\n#define DEFAULT_INDICATOR_TIMELMT\t1000\t/* ms */\n#define MSG_PREFIX\t\t\t\"[HALMAC]\"\n\n#define RTW_HALMAC_DLFW_MEM_NO_STOP_TX\n\n/*\n * Driver API for HALMAC operations\n */\n\n#ifdef CONFIG_SDIO_HCI\n#include <rtw_sdio.h>\n\nstatic u8 _halmac_mac_reg_page0_chk(const char *func, struct dvobj_priv *dvobj, u32 offset)\n{\n#if defined(CONFIG_IO_CHECK_IN_ANA_LOW_CLK) && defined(CONFIG_LPS_LCLK)\n\tstruct pwrctrl_priv *pwrpriv = &dvobj->pwrctl_priv;\n\tu32 mac_reg_offset = 0;\n\n\tif (pwrpriv->pwr_mode == PS_MODE_ACTIVE)\n\t\treturn _TRUE;\n\n\tif (pwrpriv->lps_level == LPS_NORMAL)\n\t\treturn _TRUE;\n\n\tif (pwrpriv->rpwm >= PS_STATE_S2)\n\t\treturn _TRUE;\n\n\tif (offset & (WLAN_IOREG_DEVICE_ID << 13))  { /*WLAN_IOREG_OFFSET*/\n\t\tmac_reg_offset = offset & HALMAC_WLAN_MAC_REG_MSK;\n\t\tif (mac_reg_offset < 0x100) {\n\t\t\tRTW_ERR(FUNC_ADPT_FMT\n\t\t\t\t\"access MAC REG -0x%04x in PS-mode:0x%02x (rpwm:0x%02x, lps_level:0x%02x)\\n\",\n\t\t\t\tFUNC_ADPT_ARG(dvobj_get_primary_adapter(dvobj)), mac_reg_offset,\n\t\t\t\tpwrpriv->pwr_mode, pwrpriv->rpwm, pwrpriv->lps_level);\n\t\t\trtw_warn_on(1);\n\t\t\treturn _FALSE;\n\t\t}\n\t}\n#endif\n\treturn _TRUE;\n}\n\nstatic u8 _halmac_sdio_cmd52_read(void *p, u32 offset)\n{\n\tstruct dvobj_priv *d;\n\tu8 val;\n\tu8 ret;\n\n\n\td = (struct dvobj_priv *)p;\n\t_halmac_mac_reg_page0_chk(__func__, d, offset);\n\tret = rtw_sdio_read_cmd52(d, offset, &val, 1);\n\tif (_FAIL == ret) {\n\t\tRTW_ERR(\"%s: I/O FAIL!\\n\", __FUNCTION__);\n\t\treturn SDIO_ERR_VAL8;\n\t}\n\n\treturn val;\n}\n\nstatic void _halmac_sdio_cmd52_write(void *p, u32 offset, u8 val)\n{\n\tstruct dvobj_priv *d;\n\tu8 ret;\n\n\n\td = (struct dvobj_priv *)p;\n\t_halmac_mac_reg_page0_chk(__func__, d, offset);\n\tret = rtw_sdio_write_cmd52(d, offset, &val, 1);\n\tif (_FAIL == ret)\n\t\tRTW_ERR(\"%s: I/O FAIL!\\n\", __FUNCTION__);\n}\n\nstatic u8 _halmac_sdio_reg_read_8(void *p, u32 offset)\n{\n\tstruct dvobj_priv *d;\n\tu8 *pbuf;\n\tu8 val;\n\tu8 ret;\n\n\n\td = (struct dvobj_priv *)p;\n\tval = SDIO_ERR_VAL8;\n\t_halmac_mac_reg_page0_chk(__func__, d, offset);\n\tpbuf = rtw_zmalloc(1);\n\tif (!pbuf)\n\t\treturn val;\n\n\tret = rtw_sdio_read_cmd53(d, offset, pbuf, 1);\n\tif (ret == _FAIL) {\n\t\tRTW_ERR(\"%s: I/O FAIL!\\n\", __FUNCTION__);\n\t\tgoto exit;\n\t}\n\n\tval = *pbuf;\n\nexit:\n\trtw_mfree(pbuf, 1);\n\n\treturn val;\n}\n\nstatic u16 _halmac_sdio_reg_read_16(void *p, u32 offset)\n{\n\tstruct dvobj_priv *d;\n\tu8 *pbuf;\n\tu16 val;\n\tu8 ret;\n\n\n\td = (struct dvobj_priv *)p;\n\tval = SDIO_ERR_VAL16;\n\t_halmac_mac_reg_page0_chk(__func__, d, offset);\n\tpbuf = rtw_zmalloc(2);\n\tif (!pbuf)\n\t\treturn val;\n\n\tret = rtw_sdio_read_cmd53(d, offset, pbuf, 2);\n\tif (ret == _FAIL) {\n\t\tRTW_ERR(\"%s: I/O FAIL!\\n\", __FUNCTION__);\n\t\tgoto exit;\n\t}\n\n\tval = le16_to_cpu(*(u16 *)pbuf);\n\nexit:\n\trtw_mfree(pbuf, 2);\n\n\treturn val;\n}\n\nstatic u32 _halmac_sdio_reg_read_32(void *p, u32 offset)\n{\n\tstruct dvobj_priv *d;\n\tu8 *pbuf;\n\tu32 val;\n\tu8 ret;\n\n\n\td = (struct dvobj_priv *)p;\n\tval = SDIO_ERR_VAL32;\n\t_halmac_mac_reg_page0_chk(__func__, d, offset);\n\tpbuf = rtw_zmalloc(4);\n\tif (!pbuf)\n\t\treturn val;\n\n\tret = rtw_sdio_read_cmd53(d, offset, pbuf, 4);\n\tif (ret == _FAIL) {\n\t\tRTW_ERR(\"%s: I/O FAIL!\\n\", __FUNCTION__);\n\t\tgoto exit;\n\t}\n\n\tval = le32_to_cpu(*(u32 *)pbuf);\n\nexit:\n\trtw_mfree(pbuf, 4);\n\n\treturn val;\n}\n\nstatic u8 _halmac_sdio_reg_read_n(void *p, u32 offset, u32 size, u8 *data)\n{\n\tstruct dvobj_priv *d = (struct dvobj_priv *)p;\n\tu8 *pbuf;\n\tu8 ret;\n\tu8 rst = RTW_HALMAC_FAIL;\n\tu32 sdio_read_size;\n\n\n\tif (!data)\n\t\treturn rst;\n\n\tsdio_read_size = RND4(size);\n\tsdio_read_size = rtw_sdio_cmd53_align_size(d, sdio_read_size);\n\n\tpbuf = rtw_zmalloc(sdio_read_size);\n\tif (!pbuf)\n\t\treturn rst;\n\n\tret = rtw_sdio_read_cmd53(d, offset, pbuf, sdio_read_size);\n\tif (ret == _FAIL) {\n\t\tRTW_ERR(\"%s: I/O FAIL!\\n\", __FUNCTION__);\n\t\tgoto exit;\n\t}\n\n\t_rtw_memcpy(data, pbuf, size);\n\trst = RTW_HALMAC_SUCCESS;\nexit:\n\trtw_mfree(pbuf, sdio_read_size);\n\n\treturn rst;\n}\n\nstatic void _halmac_sdio_reg_write_8(void *p, u32 offset, u8 val)\n{\n\tstruct dvobj_priv *d;\n\tu8 *pbuf;\n\tu8 ret;\n\n\n\td = (struct dvobj_priv *)p;\n\t_halmac_mac_reg_page0_chk(__func__, d, offset);\n\tpbuf = rtw_zmalloc(1);\n\tif (!pbuf)\n\t\treturn;\n\t_rtw_memcpy(pbuf, &val, 1);\n\n\tret = rtw_sdio_write_cmd53(d, offset, pbuf, 1);\n\tif (ret == _FAIL)\n\t\tRTW_ERR(\"%s: I/O FAIL!\\n\", __FUNCTION__);\n\n\trtw_mfree(pbuf, 1);\n}\n\nstatic void _halmac_sdio_reg_write_16(void *p, u32 offset, u16 val)\n{\n\tstruct dvobj_priv *d;\n\tu8 *pbuf;\n\tu8 ret;\n\n\n\td = (struct dvobj_priv *)p;\n\t_halmac_mac_reg_page0_chk(__func__, d, offset);\n\tval = cpu_to_le16(val);\n\tpbuf = rtw_zmalloc(2);\n\tif (!pbuf)\n\t\treturn;\n\t_rtw_memcpy(pbuf, &val, 2);\n\n\tret = rtw_sdio_write_cmd53(d, offset, pbuf, 2);\n\tif (ret == _FAIL)\n\t\tRTW_ERR(\"%s: I/O FAIL!\\n\", __FUNCTION__);\n\n\trtw_mfree(pbuf, 2);\n}\n\nstatic void _halmac_sdio_reg_write_32(void *p, u32 offset, u32 val)\n{\n\tstruct dvobj_priv *d;\n\tu8 *pbuf;\n\tu8 ret;\n\n\n\td = (struct dvobj_priv *)p;\n\t_halmac_mac_reg_page0_chk(__func__, d, offset);\n\tval = cpu_to_le32(val);\n\tpbuf = rtw_zmalloc(4);\n\tif (!pbuf)\n\t\treturn;\n\t_rtw_memcpy(pbuf, &val, 4);\n\n\tret = rtw_sdio_write_cmd53(d, offset, pbuf, 4);\n\tif (ret == _FAIL)\n\t\tRTW_ERR(\"%s: I/O FAIL!\\n\", __FUNCTION__);\n\n\trtw_mfree(pbuf, 4);\n}\n\nstatic u8 _halmac_sdio_read_cia(void *p, u32 offset)\n{\n\tstruct dvobj_priv *d;\n\tu8 data = 0;\n\tu8 ret;\n\n\n\td = (struct dvobj_priv *)p;\n\n\tret = rtw_sdio_f0_read(d, offset, &data, 1);\n\tif (ret == _FAIL)\n\t\tRTW_ERR(\"%s: I/O FAIL!\\n\", __FUNCTION__);\n\n\treturn data;\n}\n\n#else /* !CONFIG_SDIO_HCI */\n\nstatic u8 _halmac_reg_read_8(void *p, u32 offset)\n{\n\tstruct dvobj_priv *d;\n\tPADAPTER adapter;\n\n\n\td = (struct dvobj_priv *)p;\n\tadapter = dvobj_get_primary_adapter(d);\n\n\treturn rtw_read8(adapter, offset);\n}\n\nstatic u16 _halmac_reg_read_16(void *p, u32 offset)\n{\n\tstruct dvobj_priv *d;\n\tPADAPTER adapter;\n\n\n\td = (struct dvobj_priv *)p;\n\tadapter = dvobj_get_primary_adapter(d);\n\n\treturn rtw_read16(adapter, offset);\n}\n\nstatic u32 _halmac_reg_read_32(void *p, u32 offset)\n{\n\tstruct dvobj_priv *d;\n\tPADAPTER adapter;\n\n\n\td = (struct dvobj_priv *)p;\n\tadapter = dvobj_get_primary_adapter(d);\n\n\treturn rtw_read32(adapter, offset);\n}\n\nstatic void _halmac_reg_write_8(void *p, u32 offset, u8 val)\n{\n\tstruct dvobj_priv *d;\n\tPADAPTER adapter;\n\tint err;\n\n\n\td = (struct dvobj_priv *)p;\n\tadapter = dvobj_get_primary_adapter(d);\n\n\terr = rtw_write8(adapter, offset, val);\n\tif (err == _FAIL)\n\t\tRTW_ERR(\"%s: I/O FAIL!\\n\", __FUNCTION__);\n}\n\nstatic void _halmac_reg_write_16(void *p, u32 offset, u16 val)\n{\n\tstruct dvobj_priv *d;\n\tPADAPTER adapter;\n\tint err;\n\n\n\td = (struct dvobj_priv *)p;\n\tadapter = dvobj_get_primary_adapter(d);\n\n\terr = rtw_write16(adapter, offset, val);\n\tif (err == _FAIL)\n\t\tRTW_ERR(\"%s: I/O FAIL!\\n\", __FUNCTION__);\n}\n\nstatic void _halmac_reg_write_32(void *p, u32 offset, u32 val)\n{\n\tstruct dvobj_priv *d;\n\tPADAPTER adapter;\n\tint err;\n\n\n\td = (struct dvobj_priv *)p;\n\tadapter = dvobj_get_primary_adapter(d);\n\n\terr = rtw_write32(adapter, offset, val);\n\tif (err == _FAIL)\n\t\tRTW_ERR(\"%s: I/O FAIL!\\n\", __FUNCTION__);\n}\n#endif /* !CONFIG_SDIO_HCI */\n\nstatic u8 _halmac_mfree(void *p, void *buffer, u32 size)\n{\n\trtw_mfree(buffer, size);\n\treturn RTW_HALMAC_SUCCESS;\n}\n\nstatic void *_halmac_malloc(void *p, u32 size)\n{\n\treturn rtw_zmalloc(size);\n}\n\nstatic u8 _halmac_memcpy(void *p, void *dest, void *src, u32 size)\n{\n\t_rtw_memcpy(dest, src, size);\n\treturn RTW_HALMAC_SUCCESS;\n}\n\nstatic u8 _halmac_memset(void *p, void *addr, u8 value, u32 size)\n{\n\t_rtw_memset(addr, value, size);\n\treturn RTW_HALMAC_SUCCESS;\n}\n\nstatic void _halmac_udelay(void *p, u32 us)\n{\n\t/* Most hardware polling wait time < 50us) */\n\tif (us <= 50)\n\t\trtw_udelay_os(us);\n\telse if (us <= 1000)\n\t\trtw_usleep_os(us);\n\telse\n\t\trtw_msleep_os(RTW_DIV_ROUND_UP(us, 1000));\n}\n\nstatic u8 _halmac_mutex_init(void *p, HALMAC_MUTEX *pMutex)\n{\n\t_rtw_mutex_init(pMutex);\n\treturn RTW_HALMAC_SUCCESS;\n}\n\nstatic u8 _halmac_mutex_deinit(void *p, HALMAC_MUTEX *pMutex)\n{\n\t_rtw_mutex_free(pMutex);\n\treturn RTW_HALMAC_SUCCESS;\n}\n\nstatic u8 _halmac_mutex_lock(void *p, HALMAC_MUTEX *pMutex)\n{\n\tint err;\n\n\terr = _enter_critical_mutex(pMutex, NULL);\n\tif (err)\n\t\treturn RTW_HALMAC_FAIL;\n\n\treturn RTW_HALMAC_SUCCESS;\n}\n\nstatic u8 _halmac_mutex_unlock(void *p, HALMAC_MUTEX *pMutex)\n{\n\t_exit_critical_mutex(pMutex, NULL);\n\treturn RTW_HALMAC_SUCCESS;\n}\n\n#ifndef CONFIG_SDIO_HCI\n#define DBG_MSG_FILTER\n#endif\n\n#ifdef DBG_MSG_FILTER\nstatic u8 is_msg_allowed(uint drv_lv, u8 msg_lv)\n{\n\tswitch (drv_lv) {\n\tcase _DRV_NONE_:\n\t\treturn _FALSE;\n\n\tcase _DRV_ALWAYS_:\n\t\tif (msg_lv > HALMAC_DBG_ALWAYS)\n\t\t\treturn _FALSE;\n\t\tbreak;\n\tcase _DRV_ERR_:\n\t\tif (msg_lv > HALMAC_DBG_ERR)\n\t\t\treturn _FALSE;\n\t\tbreak;\n\tcase _DRV_WARNING_:\n\t\tif (msg_lv > HALMAC_DBG_WARN)\n\t\t\treturn _FALSE;\n\t\tbreak;\n\tcase _DRV_INFO_:\n\t\tif (msg_lv >= HALMAC_DBG_TRACE)\n\t\t\treturn _FALSE;\n\t\tbreak;\n\t}\n\n\treturn _TRUE;\n}\n#endif /* DBG_MSG_FILTER */\n\nstatic u8 _halmac_msg_print(void *p, u32 msg_type, u8 msg_level, s8 *fmt, ...)\n{\n#define MSG_LEN\t\t100\n\tva_list args;\n\tu8 str[MSG_LEN] = {0};\n#ifdef DBG_MSG_FILTER\n\tuint drv_level = _DRV_NONE_;\n#endif\n\tint err;\n\tu8 ret = RTW_HALMAC_SUCCESS;\n\n\n#ifdef DBG_MSG_FILTER\n#ifdef CONFIG_RTW_DEBUG\n\tdrv_level = rtw_drv_log_level;\n#endif\n\tif (is_msg_allowed(drv_level, msg_level) == _FALSE)\n\t\treturn ret;\n#endif\n\n\tstr[0] = '\\n';\n\tva_start(args, fmt);\n\terr = vsnprintf(str, MSG_LEN, fmt, args);\n\tva_end(args);\n\n\t/* An output error is encountered */\n\tif (err < 0)\n\t\treturn RTW_HALMAC_FAIL;\n\t/* Output may be truncated due to size limit */\n\tif ((err == (MSG_LEN - 1)) && (str[MSG_LEN - 2] != '\\n'))\n\t\tret = RTW_HALMAC_FAIL;\n\n\tif (msg_level == HALMAC_DBG_ALWAYS)\n\t\tRTW_PRINT(MSG_PREFIX \"%s\", str);\n\telse if (msg_level <= HALMAC_DBG_ERR)\n\t\tRTW_ERR(MSG_PREFIX \"%s\", str);\n\telse if (msg_level <= HALMAC_DBG_WARN)\n\t\tRTW_WARN(MSG_PREFIX \"%s\", str);\n\telse\n\t\tRTW_DBG(MSG_PREFIX \"%s\", str);\n\n\treturn ret;\n}\n\nstatic u8 _halmac_buff_print(void *p, u32 msg_type, u8 msg_level, s8 *buf, u32 size)\n{\n\tif (msg_level <= HALMAC_DBG_WARN)\n\t\tRTW_INFO_DUMP(MSG_PREFIX, buf, size);\n\telse\n\t\tRTW_DBG_DUMP(MSG_PREFIX, buf, size);\n\n\treturn RTW_HALMAC_SUCCESS;\n}\n\n\nconst char *const RTW_HALMAC_FEATURE_NAME[] = {\n\t\"HALMAC_FEATURE_CFG_PARA\",\n\t\"HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE\",\n\t\"HALMAC_FEATURE_DUMP_LOGICAL_EFUSE\",\n\t\"HALMAC_FEATURE_UPDATE_PACKET\",\n\t\"HALMAC_FEATURE_UPDATE_DATAPACK\",\n\t\"HALMAC_FEATURE_RUN_DATAPACK\",\n\t\"HALMAC_FEATURE_CHANNEL_SWITCH\",\n\t\"HALMAC_FEATURE_IQK\",\n\t\"HALMAC_FEATURE_POWER_TRACKING\",\n\t\"HALMAC_FEATURE_PSD\",\n\t\"HALMAC_FEATURE_FW_SNDING\",\n\t\"HALMAC_FEATURE_ALL\"\n};\n\nstatic inline u8 is_valid_id_status(enum halmac_feature_id id, enum halmac_cmd_process_status status)\n{\n\tswitch (id) {\n\tcase HALMAC_FEATURE_CFG_PARA:\n\t\tRTW_DBG(\"%s: %s\\n\", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);\n\t\tbreak;\n\tcase HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:\n\t\tRTW_INFO(\"%s: %s\\n\", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);\n\t\tif (HALMAC_CMD_PROCESS_DONE != status)\n\t\t\tRTW_INFO(\"%s: id(%d) unspecified status(%d)!\\n\",\n\t\t\t\t __FUNCTION__, id, status);\n\t\tbreak;\n\tcase HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:\n\t\tRTW_INFO(\"%s: %s\\n\", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);\n\t\tif (HALMAC_CMD_PROCESS_DONE != status)\n\t\t\tRTW_INFO(\"%s: id(%d) unspecified status(%d)!\\n\",\n\t\t\t\t __FUNCTION__, id, status);\n\t\tbreak;\n\tcase HALMAC_FEATURE_UPDATE_PACKET:\n\t\tRTW_INFO(\"%s: %s\\n\", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);\n\t\tif (status != HALMAC_CMD_PROCESS_DONE)\n\t\t\tRTW_INFO(\"%s: id(%d) unspecified status(%d)!\\n\",\n\t\t\t\t __FUNCTION__, id, status);\n\t\tbreak;\n\tcase HALMAC_FEATURE_UPDATE_DATAPACK:\n\t\tRTW_INFO(\"%s: %s\\n\", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);\n\t\tbreak;\n\tcase HALMAC_FEATURE_RUN_DATAPACK:\n\t\tRTW_INFO(\"%s: %s\\n\", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);\n\t\tbreak;\n\tcase HALMAC_FEATURE_CHANNEL_SWITCH:\n\t\tRTW_INFO(\"%s: %s\\n\", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);\n\t\tif ((status != HALMAC_CMD_PROCESS_DONE) && (status != HALMAC_CMD_PROCESS_RCVD))\n\t\t\tRTW_INFO(\"%s: id(%d) unspecified status(%d)!\\n\",\n\t\t\t\t __FUNCTION__, id, status);\n\t\tif (status == HALMAC_CMD_PROCESS_DONE)\n\t\t\treturn _FALSE;\n\t\tbreak;\n\tcase HALMAC_FEATURE_IQK:\n\t\tRTW_INFO(\"%s: %s\\n\", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);\n\t\tbreak;\n\tcase HALMAC_FEATURE_POWER_TRACKING:\n\t\tRTW_INFO(\"%s: %s\\n\", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);\n\t\tbreak;\n\tcase HALMAC_FEATURE_PSD:\n\t\tRTW_INFO(\"%s: %s\\n\", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);\n\t\tbreak;\n\tcase HALMAC_FEATURE_FW_SNDING:\n\t\tRTW_INFO(\"%s: %s\\n\", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);\n\t\tbreak;\n\tcase HALMAC_FEATURE_ALL:\n\t\tRTW_INFO(\"%s: %s\\n\", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);\n\t\tbreak;\n\tdefault:\n\t\tRTW_ERR(\"%s: unknown feature id(%d)\\n\", __FUNCTION__, id);\n\t\treturn _FALSE;\n\t}\n\n\treturn _TRUE;\n}\n\nstatic int init_halmac_event_with_waittime(struct dvobj_priv *d, enum halmac_feature_id id, u8 *buf, u32 size, u32 time)\n{\n\tstruct submit_ctx *sctx;\n\n\n\tif (!d->hmpriv.indicator[id].sctx) {\n\t\tsctx = (struct submit_ctx *)rtw_zmalloc(sizeof(*sctx));\n\t\tif (!sctx)\n\t\t\treturn -1;\n\t} else {\n\t\tRTW_WARN(\"%s: id(%d) sctx is not NULL!!\\n\", __FUNCTION__, id);\n\t\tsctx = d->hmpriv.indicator[id].sctx;\n\t\td->hmpriv.indicator[id].sctx = NULL;\n\t}\n\n\trtw_sctx_init(sctx, time);\n\td->hmpriv.indicator[id].buffer = buf;\n\td->hmpriv.indicator[id].buf_size = size;\n\td->hmpriv.indicator[id].ret_size = 0;\n\td->hmpriv.indicator[id].status = 0;\n\t/* fill sctx at least to sure other variables are all ready! */\n\td->hmpriv.indicator[id].sctx = sctx;\n\n\treturn 0;\n}\n\nstatic inline int init_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id, u8 *buf, u32 size)\n{\n\treturn init_halmac_event_with_waittime(d, id, buf, size, DEFAULT_INDICATOR_TIMELMT);\n}\n\nstatic void free_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id)\n{\n\tstruct submit_ctx *sctx;\n\n\n\tif (!d->hmpriv.indicator[id].sctx)\n\t\treturn;\n\n\tsctx = d->hmpriv.indicator[id].sctx;\n\td->hmpriv.indicator[id].sctx = NULL;\n\trtw_mfree((u8 *)sctx, sizeof(*sctx));\n}\n\nstatic int wait_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tstruct submit_ctx *sctx;\n\tint ret;\n\n\n\tsctx = d->hmpriv.indicator[id].sctx;\n\tif (!sctx)\n\t\treturn -1;\n\n\tret = rtw_sctx_wait(sctx, RTW_HALMAC_FEATURE_NAME[id]);\n\tfree_halmac_event(d, id);\n\tif (_SUCCESS == ret)\n\t\treturn 0;\n\n\t/* timeout! We have to reset halmac state */\n\tRTW_ERR(\"%s: Wait id(%d, %s) TIMEOUT! Reset HALMAC state!\\n\",\n\t\t__FUNCTION__, id, RTW_HALMAC_FEATURE_NAME[id]);\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\tapi->halmac_reset_feature(mac, id);\n\n\treturn -1;\n}\n\n/*\n * Return:\n *\tAlways return RTW_HALMAC_SUCCESS, HALMAC don't care the return value.\n */\nstatic u8 _halmac_event_indication(void *p, enum halmac_feature_id feature_id, enum halmac_cmd_process_status process_status, u8 *buf, u32 size)\n{\n\tstruct dvobj_priv *d;\n\tPADAPTER adapter;\n\tPHAL_DATA_TYPE hal;\n\tstruct halmac_indicator *tbl, *indicator;\n\tstruct submit_ctx *sctx;\n\tu32 cpsz;\n\tu8 ret;\n\n\n\td = (struct dvobj_priv *)p;\n\tadapter = dvobj_get_primary_adapter(d);\n\thal = GET_HAL_DATA(adapter);\n\ttbl = d->hmpriv.indicator;\n\n\t/* Filter(Skip) middle status indication */\n\tret = is_valid_id_status(feature_id, process_status);\n\tif (_FALSE == ret)\n\t\tgoto exit;\n\n\tindicator = &tbl[feature_id];\n\tindicator->status = process_status;\n\tindicator->ret_size = size;\n\tif (!indicator->sctx) {\n\t\tRTW_WARN(\"%s: No feature id(%d, %s) waiting!!\\n\", __FUNCTION__, feature_id, RTW_HALMAC_FEATURE_NAME[feature_id]);\n\t\tgoto exit;\n\t}\n\tsctx = indicator->sctx;\n\n\tif (HALMAC_CMD_PROCESS_ERROR == process_status) {\n\t\tRTW_ERR(\"%s: Something wrong id(%d, %s)!!\\n\", __FUNCTION__, feature_id, RTW_HALMAC_FEATURE_NAME[feature_id]);\n\t\trtw_sctx_done_err(&sctx, RTW_SCTX_DONE_UNKNOWN);\n\t\tgoto exit;\n\t}\n\n\tif (size > indicator->buf_size) {\n\t\tRTW_WARN(\"%s: id(%d, %s) buffer is not enough(%d<%d), data will be truncated!\\n\",\n\t\t\t __FUNCTION__, feature_id, RTW_HALMAC_FEATURE_NAME[feature_id], indicator->buf_size, size);\n\t\tcpsz = indicator->buf_size;\n\t} else {\n\t\tcpsz = size;\n\t}\n\tif (cpsz && indicator->buffer)\n\t\t_rtw_memcpy(indicator->buffer, buf, cpsz);\n\n\trtw_sctx_done(&sctx);\n\nexit:\n\treturn RTW_HALMAC_SUCCESS;\n}\n\nstruct halmac_platform_api rtw_halmac_platform_api = {\n\t/* R/W register */\n#ifdef CONFIG_SDIO_HCI\n\t.SDIO_CMD52_READ = _halmac_sdio_cmd52_read,\n\t.SDIO_CMD53_READ_8 = _halmac_sdio_reg_read_8,\n\t.SDIO_CMD53_READ_16 = _halmac_sdio_reg_read_16,\n\t.SDIO_CMD53_READ_32 = _halmac_sdio_reg_read_32,\n\t.SDIO_CMD53_READ_N = _halmac_sdio_reg_read_n,\n\t.SDIO_CMD52_WRITE = _halmac_sdio_cmd52_write,\n\t.SDIO_CMD53_WRITE_8 = _halmac_sdio_reg_write_8,\n\t.SDIO_CMD53_WRITE_16 = _halmac_sdio_reg_write_16,\n\t.SDIO_CMD53_WRITE_32 = _halmac_sdio_reg_write_32,\n\t.SDIO_CMD52_CIA_READ = _halmac_sdio_read_cia,\n#endif /* CONFIG_SDIO_HCI */\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)\n\t.REG_READ_8 = _halmac_reg_read_8,\n\t.REG_READ_16 = _halmac_reg_read_16,\n\t.REG_READ_32 = _halmac_reg_read_32,\n\t.REG_WRITE_8 = _halmac_reg_write_8,\n\t.REG_WRITE_16 = _halmac_reg_write_16,\n\t.REG_WRITE_32 = _halmac_reg_write_32,\n#endif /* CONFIG_USB_HCI || CONFIG_PCI_HCI */\n\n\t/* Write data */\n#if 0\n\t/* impletement in HAL-IC level */\n\t.SEND_RSVD_PAGE = sdio_write_data_rsvd_page,\n\t.SEND_H2C_PKT = sdio_write_data_h2c,\n#endif\n\t/* Memory allocate */\n\t.RTL_FREE = _halmac_mfree,\n\t.RTL_MALLOC = _halmac_malloc,\n\t.RTL_MEMCPY = _halmac_memcpy,\n\t.RTL_MEMSET = _halmac_memset,\n\n\t/* Sleep */\n\t.RTL_DELAY_US = _halmac_udelay,\n\n\t/* Process Synchronization */\n\t.MUTEX_INIT = _halmac_mutex_init,\n\t.MUTEX_DEINIT = _halmac_mutex_deinit,\n\t.MUTEX_LOCK = _halmac_mutex_lock,\n\t.MUTEX_UNLOCK = _halmac_mutex_unlock,\n\n\t.MSG_PRINT = _halmac_msg_print,\n\t.BUFF_PRINT = _halmac_buff_print,\n\t.EVENT_INDICATION = _halmac_event_indication,\n};\n\nu8 rtw_halmac_read8(struct intf_hdl *pintfhdl, u32 addr)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\n\n\t/* WARNING: pintf_dev should not be null! */\n\tmac = dvobj_to_halmac(pintfhdl->pintf_dev);\n\tapi = HALMAC_GET_API(mac);\n\n\treturn api->halmac_reg_read_8(mac, addr);\n}\n\nu16 rtw_halmac_read16(struct intf_hdl *pintfhdl, u32 addr)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\n\n\t/* WARNING: pintf_dev should not be null! */\n\tmac = dvobj_to_halmac(pintfhdl->pintf_dev);\n\tapi = HALMAC_GET_API(mac);\n\n\treturn api->halmac_reg_read_16(mac, addr);\n}\n\nu32 rtw_halmac_read32(struct intf_hdl *pintfhdl, u32 addr)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\n\n\t/* WARNING: pintf_dev should not be null! */\n\tmac = dvobj_to_halmac(pintfhdl->pintf_dev);\n\tapi = HALMAC_GET_API(mac);\n\n\treturn api->halmac_reg_read_32(mac, addr);\n}\n\nstatic void _read_register(struct dvobj_priv *d, u32 addr, u32 cnt, u8 *buf)\n{\n#if 1\n\tstruct _ADAPTER *a;\n\tu32 i, n;\n\tu16 val16;\n\tu32 val32;\n\n\n\ta = dvobj_get_primary_adapter(d);\n\n\ti = addr & 0x3;\n\t/* Handle address not start from 4 bytes alignment case */\n\tif (i) {\n\t\tval32 = cpu_to_le32(rtw_read32(a, addr & ~0x3));\n\t\tn = 4 - i;\n\t\t_rtw_memcpy(buf, ((u8 *)&val32) + i, n);\n\t\ti = n;\n\t\tcnt -= n;\n\t}\n\n\twhile (cnt) {\n\t\tif (cnt >= 4)\n\t\t\tn = 4;\n\t\telse if (cnt >= 2)\n\t\t\tn = 2;\n\t\telse\n\t\t\tn = 1;\n\t\tcnt -= n;\n\n\t\tswitch (n) {\n\t\tcase 1:\n\t\t\tbuf[i] = rtw_read8(a, addr+i);\n\t\t\ti++;\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tval16 = cpu_to_le16(rtw_read16(a, addr+i));\n\t\t\t_rtw_memcpy(&buf[i], &val16, 2);\n\t\t\ti += 2;\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\tval32 = cpu_to_le32(rtw_read32(a, addr+i));\n\t\t\t_rtw_memcpy(&buf[i], &val32, 4);\n\t\t\ti += 4;\n\t\t\tbreak;\n\t\t}\n\t}\n#else\n\tstruct _ADAPTER *a;\n\tu32 i;\n\n\n\ta = dvobj_get_primary_adapter(d);\n\tfor (i = 0; i < cnt; i++)\n\t\tbuf[i] = rtw_read8(a, addr + i);\n#endif\n}\n\n#ifdef CONFIG_SDIO_HCI\nstatic int _sdio_read_local(struct dvobj_priv *d, u32 addr, u32 cnt, u8 *buf)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\n\n\tif (buf == NULL)\n\t\treturn -1;\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_reg_sdio_cmd53_read_n(mac, addr, cnt, buf);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tRTW_ERR(\"%s: addr=0x%08x cnt=%d err=%d\\n\",\n\t\t\t__FUNCTION__, addr, cnt, status);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n#endif /* CONFIG_SDIO_HCI */\n\nvoid rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem)\n{\n\tstruct dvobj_priv *d;\n\n\n\tif (pmem == NULL) {\n\t\tRTW_ERR(\"pmem is NULL\\n\");\n\t\treturn;\n\t}\n\n\td = pintfhdl->pintf_dev;\n\n#ifdef CONFIG_SDIO_HCI\n\tif (addr & 0xFFFF0000) {\n\t\tint err = 0;\n\n\t\terr = _sdio_read_local(d, addr, cnt, pmem);\n\t\tif (!err)\n\t\t\treturn;\n\t}\n#endif /* CONFIG_SDIO_HCI */\n\n\t_read_register(d, addr, cnt, pmem);\n}\n\n#ifdef CONFIG_SDIO_INDIRECT_ACCESS\nu8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\n\t/* WARNING: pintf_dev should not be null! */\n\tmac = dvobj_to_halmac(pintfhdl->pintf_dev);\n\tapi = HALMAC_GET_API(mac);\n\n\t/*return api->halmac_reg_read_indirect_8(mac, addr);*/\n\treturn api->halmac_reg_read_8(mac, addr);\n}\n\nu16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tu16 val16 = 0;\n\n\t/* WARNING: pintf_dev should not be null! */\n\tmac = dvobj_to_halmac(pintfhdl->pintf_dev);\n\tapi = HALMAC_GET_API(mac);\n\n\t/*return api->halmac_reg_read_indirect_16(mac, addr);*/\n\treturn api->halmac_reg_read_16(mac, addr);\n}\n\nu32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\n\n\t/* WARNING: pintf_dev should not be null! */\n\tmac = dvobj_to_halmac(pintfhdl->pintf_dev);\n\tapi = HALMAC_GET_API(mac);\n\n\treturn api->halmac_reg_read_indirect_32(mac, addr);\n}\n#endif /* CONFIG_SDIO_INDIRECT_ACCESS */\n\nint rtw_halmac_write8(struct intf_hdl *pintfhdl, u32 addr, u8 value)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\n\n\t/* WARNING: pintf_dev should not be null! */\n\tmac = dvobj_to_halmac(pintfhdl->pintf_dev);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_reg_write_8(mac, addr, value);\n\n\tif (status == HALMAC_RET_SUCCESS)\n\t\treturn 0;\n\n\treturn -1;\n}\n\nint rtw_halmac_write16(struct intf_hdl *pintfhdl, u32 addr, u16 value)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\n\n\t/* WARNING: pintf_dev should not be null! */\n\tmac = dvobj_to_halmac(pintfhdl->pintf_dev);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_reg_write_16(mac, addr, value);\n\n\tif (status == HALMAC_RET_SUCCESS)\n\t\treturn 0;\n\n\treturn -1;\n}\n\nint rtw_halmac_write32(struct intf_hdl *pintfhdl, u32 addr, u32 value)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\n\n\t/* WARNING: pintf_dev should not be null! */\n\tmac = dvobj_to_halmac(pintfhdl->pintf_dev);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_reg_write_32(mac, addr, value);\n\n\tif (status == HALMAC_RET_SUCCESS)\n\t\treturn 0;\n\n\treturn -1;\n}\n\nstatic int init_write_rsvd_page_size(struct dvobj_priv *d)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tu32 size = 0;\n\tstruct halmac_ofld_func_info ofld_info;\n\tenum halmac_ret_status status;\n\tint err = 0;\n\n\n#ifdef CONFIG_USB_HCI\n\t/* for USB do not exceed MAX_CMDBUF_SZ */\n\tsize = 0x1000;\n#elif defined(CONFIG_PCI_HCI)\n\tsize = MAX_CMDBUF_SZ - TXDESC_OFFSET;\n#elif defined(CONFIG_SDIO_HCI)\n\tsize = 0x7000; /* 28KB */\n#endif\n\n\t/* If size==0, use HALMAC default setting and don't call any function */\n\tif (!size)\n\t\treturn 0;\n\n\terr = rtw_halmac_set_max_dl_fw_size(d, size);\n\tif (err) {\n\t\tRTW_ERR(\"%s: Fail to set max download fw size!\\n\", __FUNCTION__);\n\t\treturn -1;\n\t}\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\t_rtw_memset(&ofld_info, 0, sizeof(ofld_info));\n\tofld_info.halmac_malloc_max_sz = 0xFFFFFFFF;\n\tofld_info.rsvd_pg_drv_buf_max_sz = size;\n\tstatus = api->halmac_ofld_func_cfg(mac, &ofld_info);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tRTW_ERR(\"%s: Fail to config offload parameters!\\n\", __FUNCTION__);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int init_priv(struct halmacpriv *priv)\n{\n\tstruct halmac_indicator *indicator;\n\tu32 count, size;\n\n\n\tif (priv->indicator)\n\t\tRTW_WARN(\"%s: HALMAC private data is not CLEAR!\\n\", __FUNCTION__);\n\tcount = HALMAC_FEATURE_ALL + 1;\n\tsize = sizeof(*indicator) * count;\n\tindicator = (struct halmac_indicator *)rtw_zmalloc(size);\n\tif (!indicator)\n\t\treturn -1;\n\tpriv->indicator = indicator;\n\n\treturn 0;\n}\n\nstatic void deinit_priv(struct halmacpriv *priv)\n{\n\tstruct halmac_indicator *indicator;\n\n\n\tindicator = priv->indicator;\n\tpriv->indicator = NULL;\n\tif (indicator) {\n\t\tu32 count, size;\n\n\t\tcount = HALMAC_FEATURE_ALL + 1;\n#ifdef CONFIG_RTW_DEBUG\n\t\t{\n\t\t\tstruct submit_ctx *sctx;\n\t\t\tu32 i;\n\n\t\t\tfor (i = 0; i < count; i++) {\n\t\t\t\tif (!indicator[i].sctx)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tRTW_WARN(\"%s: %s id(%d) sctx still exist!!\\n\",\n\t\t\t\t\t__FUNCTION__, RTW_HALMAC_FEATURE_NAME[i], i);\n\t\t\t\tsctx = indicator[i].sctx;\n\t\t\t\tindicator[i].sctx = NULL;\n\t\t\t\trtw_mfree((u8 *)sctx, sizeof(*sctx));\n\t\t\t}\n\t\t}\n#endif /* !CONFIG_RTW_DEBUG */\n\t\tsize = sizeof(*indicator) * count;\n\t\trtw_mfree((u8 *)indicator, size);\n\t}\n}\n\n#ifdef CONFIG_SDIO_HCI\nstatic enum halmac_sdio_spec_ver _sdio_ver_drv2halmac(struct dvobj_priv *d)\n{\n\tbool v3;\n\tenum halmac_sdio_spec_ver ver;\n\n\n\tv3 = rtw_is_sdio30(dvobj_get_primary_adapter(d));\n\tif (v3)\n\t\tver = HALMAC_SDIO_SPEC_VER_3_00;\n\telse\n\t\tver = HALMAC_SDIO_SPEC_VER_2_00;\n\n\treturn ver;\n}\n#endif /* CONFIG_SDIO_HCI */\n\nvoid rtw_halmac_get_version(char *str, u32 len)\n{\n\tenum halmac_ret_status status;\n\tstruct halmac_ver ver;\n\n\n\tstatus = halmac_get_version(&ver);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn;\n\n\trtw_sprintf(str, len, \"V%d_%02d_%02d\",\n\t\t    ver.major_ver, ver.prototype_ver, ver.minor_ver);\n}\n\nint rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf_api)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_interface intf;\n\tenum halmac_ret_status status;\n\tint err = 0;\n#ifdef CONFIG_SDIO_HCI\n\tstruct halmac_sdio_hw_info info;\n#endif /* CONFIG_SDIO_HCI */\n\n\n\thalmac = dvobj_to_halmac(d);\n\tif (halmac) {\n\t\tRTW_WARN(\"%s: initialize already completed!\\n\", __FUNCTION__);\n\t\tgoto error;\n\t}\n\n\terr = init_priv(&d->hmpriv);\n\tif (err)\n\t\tgoto error;\n\n#ifdef CONFIG_SDIO_HCI\n\tintf = HALMAC_INTERFACE_SDIO;\n#elif defined(CONFIG_USB_HCI)\n\tintf = HALMAC_INTERFACE_USB;\n#elif defined(CONFIG_PCI_HCI)\n\tintf = HALMAC_INTERFACE_PCIE;\n#else\n#warning \"INTERFACE(CONFIG_XXX_HCI) not be defined!!\"\n\tintf = HALMAC_INTERFACE_UNDEFINE;\n#endif\n\tstatus = halmac_init_adapter(d, pf_api, intf, &halmac, &api);\n\tif (HALMAC_RET_SUCCESS != status) {\n\t\tRTW_ERR(\"%s: halmac_init_adapter fail!(status=%d)\\n\", __FUNCTION__, status);\n\t\terr = -1;\n\t\tif (halmac)\n\t\t\tgoto deinit;\n\t\tgoto free;\n\t}\n\n\tdvobj_set_halmac(d, halmac);\n\n\tstatus = api->halmac_interface_integration_tuning(halmac);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tRTW_ERR(\"%s: halmac_interface_integration_tuning fail!(status=%d)\\n\", __FUNCTION__, status);\n\t\terr = -1;\n\t\tgoto deinit;\n\t}\n\n\tstatus = api->halmac_phy_cfg(halmac, HALMAC_INTF_PHY_PLATFORM_ALL);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tRTW_ERR(\"%s: halmac_phy_cfg fail!(status=%d)\\n\", __FUNCTION__, status);\n\t\terr = -1;\n\t\tgoto deinit;\n\t}\n\n\tinit_write_rsvd_page_size(d);\n\n#ifdef CONFIG_SDIO_HCI\n\t_rtw_memset(&info, 0, sizeof(info));\n\tinfo.spec_ver = _sdio_ver_drv2halmac(d);\n\t/* Convert clock speed unit to MHz from Hz */\n\tinfo.clock_speed = RTW_DIV_ROUND_UP(rtw_sdio_get_clock(d), 1000000);\n\tinfo.block_size = rtw_sdio_get_block_size(d);\n\tRTW_DBG(\"%s: SDIO ver=%u clock=%uMHz blk_size=%u bytes\\n\",\n\t\t__FUNCTION__, info.spec_ver+2, info.clock_speed,\n\t\tinfo.block_size);\n\tstatus = api->halmac_sdio_hw_info(halmac, &info);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tRTW_ERR(\"%s: halmac_sdio_hw_info fail!(status=%d)\\n\",\n\t\t\t__FUNCTION__, status);\n\t\terr = -1;\n\t\tgoto deinit;\n\t}\n#endif /* CONFIG_SDIO_HCI */\n\n\treturn 0;\n\ndeinit:\n\tstatus = halmac_deinit_adapter(halmac);\n\tdvobj_set_halmac(d, NULL);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tRTW_ERR(\"%s: halmac_deinit_adapter fail!(status=%d)\\n\",\n\t\t\t__FUNCTION__, status);\n\nfree:\n\tdeinit_priv(&d->hmpriv);\n\nerror:\n\treturn err;\n}\n\nint rtw_halmac_deinit_adapter(struct dvobj_priv *d)\n{\n\tstruct halmac_adapter *halmac;\n\tenum halmac_ret_status status;\n\tint err = 0;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tif (halmac) {\n\t\tstatus = halmac_deinit_adapter(halmac);\n\t\tdvobj_set_halmac(d, NULL);\n\t\tif (status != HALMAC_RET_SUCCESS)\n\t\t\terr = -1;\n\t}\n\n\tdeinit_priv(&d->hmpriv);\n\n\treturn err;\n}\n\nstatic inline enum halmac_portid _hw_port_drv2halmac(enum _hw_port hwport)\n{\n\tenum halmac_portid port = HALMAC_PORTID_NUM;\n\n\n\tswitch (hwport) {\n\tcase HW_PORT0:\n\t\tport = HALMAC_PORTID0;\n\t\tbreak;\n\tcase HW_PORT1:\n\t\tport = HALMAC_PORTID1;\n\t\tbreak;\n\tcase HW_PORT2:\n\t\tport = HALMAC_PORTID2;\n\t\tbreak;\n\tcase HW_PORT3:\n\t\tport = HALMAC_PORTID3;\n\t\tbreak;\n\tcase HW_PORT4:\n\t\tport = HALMAC_PORTID4;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn port;\n}\n\nstatic enum halmac_network_type_select _network_type_drv2halmac(u8 type)\n{\n\tenum halmac_network_type_select network = HALMAC_NETWORK_UNDEFINE;\n\n\n\tswitch (type) {\n\tcase _HW_STATE_NOLINK_:\n\tcase _HW_STATE_MONITOR_:\n\t\tnetwork = HALMAC_NETWORK_NO_LINK;\n\t\tbreak;\n\n\tcase _HW_STATE_ADHOC_:\n\t\tnetwork = HALMAC_NETWORK_ADHOC;\n\t\tbreak;\n\n\tcase _HW_STATE_STATION_:\n\t\tnetwork = HALMAC_NETWORK_INFRASTRUCTURE;\n\t\tbreak;\n\n\tcase _HW_STATE_AP_:\n\t\tnetwork = HALMAC_NETWORK_AP;\n\t\tbreak;\n\t}\n\n\treturn network;\n}\n\nstatic u8 _network_type_halmac2drv(enum halmac_network_type_select network)\n{\n\tu8 type = _HW_STATE_NOLINK_;\n\n\n\tswitch (network) {\n\tcase HALMAC_NETWORK_NO_LINK:\n\tcase HALMAC_NETWORK_UNDEFINE:\n\t\ttype = _HW_STATE_NOLINK_;\n\t\tbreak;\n\n\tcase HALMAC_NETWORK_ADHOC:\n\t\ttype = _HW_STATE_ADHOC_;\n\t\tbreak;\n\n\tcase HALMAC_NETWORK_INFRASTRUCTURE:\n\t\ttype = _HW_STATE_STATION_;\n\t\tbreak;\n\n\tcase HALMAC_NETWORK_AP:\n\t\ttype = _HW_STATE_AP_;\n\t\tbreak;\n\t}\n\n\treturn type;\n}\n\nstatic void _beacon_ctrl_halmac2drv(struct halmac_bcn_ctrl *ctrl,\n\t\t\t\tstruct rtw_halmac_bcn_ctrl *drv_ctrl)\n{\n\tdrv_ctrl->rx_bssid_fit = ctrl->dis_rx_bssid_fit ? 0 : 1;\n\tdrv_ctrl->txbcn_rpt = ctrl->en_txbcn_rpt ? 1 : 0;\n\tdrv_ctrl->tsf_update = ctrl->dis_tsf_udt ? 0 : 1;\n\tdrv_ctrl->enable_bcn = ctrl->en_bcn ? 1 : 0;\n\tdrv_ctrl->rxbcn_rpt = ctrl->en_rxbcn_rpt ? 1 : 0;\n\tdrv_ctrl->p2p_ctwin = ctrl->en_p2p_ctwin ? 1 : 0;\n\tdrv_ctrl->p2p_bcn_area = ctrl->en_p2p_bcn_area ? 1 : 0;\n}\n\nstatic void _beacon_ctrl_drv2halmac(struct rtw_halmac_bcn_ctrl *drv_ctrl,\n\t\t\t\tstruct halmac_bcn_ctrl *ctrl)\n{\n\tctrl->dis_rx_bssid_fit = drv_ctrl->rx_bssid_fit ? 0 : 1;\n\tctrl->en_txbcn_rpt = drv_ctrl->txbcn_rpt ? 1 : 0;\n\tctrl->dis_tsf_udt = drv_ctrl->tsf_update ? 0 : 1;\n\tctrl->en_bcn = drv_ctrl->enable_bcn ? 1 : 0;\n\tctrl->en_rxbcn_rpt = drv_ctrl->rxbcn_rpt ? 1 : 0;\n\tctrl->en_p2p_ctwin = drv_ctrl->p2p_ctwin ? 1 : 0;\n\tctrl->en_p2p_bcn_area = drv_ctrl->p2p_bcn_area ? 1 : 0;\n}\n\nint rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void *pvalue)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_get_hw_value(mac, hw_id, pvalue);\n\tif (HALMAC_RET_SUCCESS != status)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/**\n * rtw_halmac_get_tx_fifo_size() - TX FIFO size\n * @d:\t\tstruct dvobj_priv*\n * @size:\tTX FIFO size, unit is byte.\n *\n * Get TX FIFO size(byte) from HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 val = 0;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tstatus = api->halmac_get_hw_value(halmac, HALMAC_HW_TXFIFO_SIZE, &val);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\t*size = val;\n\n\treturn 0;\n}\n\n/**\n * rtw_halmac_get_rx_fifo_size() - RX FIFO size\n * @d:\t\tstruct dvobj_priv*\n * @size:\tRX FIFO size, unit is byte\n *\n * Get RX FIFO size(byte) from HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 val = 0;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tstatus = api->halmac_get_hw_value(halmac, HALMAC_HW_RXFIFO_SIZE, &val);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\t*size = val;\n\n\treturn 0;\n}\n\n/**\n * rtw_halmac_get_rsvd_drv_pg_bndy() - Reserve page boundary of driver\n * @d:\t\tstruct dvobj_priv*\n * @size:\tPage size, unit is byte\n *\n * Get reserve page boundary of driver from HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu16 val = 0;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tstatus = api->halmac_get_hw_value(halmac, HALMAC_HW_RSVD_PG_BNDY, &val);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\t*bndy = val;\n\n\treturn 0;\n}\n\n/**\n * rtw_halmac_get_page_size() - Page size\n * @d:\t\tstruct dvobj_priv*\n * @size:\tPage size, unit is byte\n *\n * Get TX/RX page size(byte) from HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 val = 0;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tstatus = api->halmac_get_hw_value(halmac, HALMAC_HW_PAGE_SIZE, &val);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\t*size = val;\n\n\treturn 0;\n}\n\n/**\n * rtw_halmac_get_tx_agg_align_size() - TX aggregation align size\n * @d:\t\tstruct dvobj_priv*\n * @size:\tTX aggregation align size, unit is byte\n *\n * Get TX aggregation align size(byte) from HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu16 val = 0;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tstatus = api->halmac_get_hw_value(halmac, HALMAC_HW_TX_AGG_ALIGN_SIZE, &val);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\t*size = val;\n\n\treturn 0;\n}\n\n/**\n * rtw_halmac_get_rx_agg_align_size() - RX aggregation align size\n * @d:\t\tstruct dvobj_priv*\n * @size:\tRX aggregation align size, unit is byte\n *\n * Get RX aggregation align size(byte) from HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu8 val = 0;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tstatus = api->halmac_get_hw_value(halmac, HALMAC_HW_RX_AGG_ALIGN_SIZE, &val);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\t*size = val;\n\n\treturn 0;\n}\n\n/*\n * Description:\n *\tGet RX driver info size. RX driver info is a small memory space between\n *\tscriptor and RX payload.\n *\n *\t+-------------------------+\n *\t| RX descriptor           |\n *\t| usually 24 bytes        |\n *\t+-------------------------+\n *\t| RX driver info          |\n *\t| depends on driver cfg   |\n *\t+-------------------------+\n *\t| RX paylad               |\n *\t|                         |\n *\t+-------------------------+\n *\n * Parameter:\n *\td\tpointer to struct dvobj_priv of driver\n *\tsz\trx driver info size in bytes.\n *\n * Rteurn:\n *\t0\tSuccess\n *\tother\tFail\n */\nint rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *d, u8 *sz)\n{\n\tenum halmac_ret_status status;\n\tstruct halmac_adapter *halmac = dvobj_to_halmac(d);\n\tstruct halmac_api *api = HALMAC_GET_API(halmac);\n\tu8 dw = 0;\n\n\tstatus = api->halmac_get_hw_value(halmac, HALMAC_HW_DRV_INFO_SIZE, &dw);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\t*sz = dw * 8;\n\treturn 0;\n}\n\n/**\n * rtw_halmac_get_tx_desc_size() - TX descriptor size\n * @d:\t\tstruct dvobj_priv*\n * @size:\tTX descriptor size, unit is byte.\n *\n * Get TX descriptor size(byte) from HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 val = 0;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tstatus = api->halmac_get_hw_value(halmac, HALMAC_HW_TX_DESC_SIZE, &val);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\t*size = val;\n\n\treturn 0;\n}\n\n/**\n * rtw_halmac_get_rx_desc_size() - RX descriptor size\n * @d:\t\tstruct dvobj_priv*\n * @size:\tRX descriptor size, unit is byte.\n *\n * Get RX descriptor size(byte) from HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 val = 0;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tstatus = api->halmac_get_hw_value(halmac, HALMAC_HW_RX_DESC_SIZE, &val);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\t*size = val;\n\n\treturn 0;\n}\n\n\n/**\n * rtw_halmac_get_fw_max_size() - Firmware MAX size\n * @d:\t\tstruct dvobj_priv*\n * @size:\tMAX Firmware size, unit is byte.\n *\n * Get Firmware MAX size(byte) from HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nstatic int rtw_halmac_get_fw_max_size(struct dvobj_priv *d, u32 *size)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 val = 0;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tstatus = api->halmac_get_hw_value(halmac, HALMAC_HW_FW_MAX_SIZE, &val);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\t*size = val;\n\n\treturn 0;\n}\n\n/**\n * rtw_halmac_get_ori_h2c_size() - Original H2C MAX size\n * @d:\t\tstruct dvobj_priv*\n * @size:\tH2C MAX size, unit is byte.\n *\n * Get original H2C MAX size(byte) from HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 val = 0;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tstatus = api->halmac_get_hw_value(halmac, HALMAC_HW_ORI_H2C_SIZE, &val);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\t*size = val;\n\n\treturn 0;\n}\n\nint rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size)\n{\n\tenum halmac_ret_status status;\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tu8 val;\n\n\n\tif (!size)\n\t\treturn -1;\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tstatus = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_OQT_SIZE, &val);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\t*size = val;\n\treturn 0;\n}\n\nint rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num)\n{\n\tenum halmac_ret_status status;\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tu8 val;\n\n\n\tif (!num)\n\t\treturn -1;\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tstatus = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_QUEUE_NUM, &val);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\t*num = val;\n\treturn 0;\n}\n\n/**\n * rtw_halmac_get_mac_address() - Get MAC address of specific port\n * @d:\t\tstruct dvobj_priv*\n * @hwport:\tport\n * @addr:\tbuffer for storing MAC address\n *\n * Get MAC address of specific port from HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_portid port;\n\tunion halmac_wlan_addr hwa;\n\tenum halmac_ret_status status;\n\tint err = -1;\n\n\n\tif (!addr)\n\t\tgoto out;\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\tport = _hw_port_drv2halmac(hwport);\n\t_rtw_memset(&hwa, 0, sizeof(hwa));\n\n\tstatus = api->halmac_get_mac_addr(halmac, port, &hwa);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n\t_rtw_memcpy(addr, hwa.addr, 6);\n\n\terr = 0;\nout:\n\treturn err;\n}\n\n/**\n * rtw_halmac_get_network_type() - Get network type of specific port\n * @d:\t\tstruct dvobj_priv*\n * @hwport:\tport\n * @type:\tbuffer to put network type (_HW_STATE_*)\n *\n * Get network type of specific port from HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type)\n{\n#if 0\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_portid port;\n\tenum halmac_network_type_select network;\n\tenum halmac_ret_status status;\n\tint err = -1;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\tport = _hw_port_drv2halmac(hwport);\n\tnetwork = HALMAC_NETWORK_UNDEFINE;\n\n\tstatus = api->halmac_get_net_type(halmac, port, &network);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n\t*type = _network_type_halmac2drv(network);\n\n\terr = 0;\nout:\n\treturn err;\n#else\n\tstruct _ADAPTER *a;\n\tenum halmac_portid port;\n\tenum halmac_network_type_select network;\n\tu32 val;\n\tint err = -1;\n\n\n\ta = dvobj_get_primary_adapter(d);\n\tport = _hw_port_drv2halmac(hwport);\n\tnetwork = HALMAC_NETWORK_UNDEFINE;\n\n\tswitch (port) {\n\tcase HALMAC_PORTID0:\n\t\tval = rtw_read32(a, REG_CR);\n\t\tnetwork = BIT_GET_NETYPE0(val);\n\t\tbreak;\n\n\tcase HALMAC_PORTID1:\n\t\tval = rtw_read32(a, REG_CR);\n\t\tnetwork = BIT_GET_NETYPE1(val);\n\t\tbreak;\n\n\tcase HALMAC_PORTID2:\n\t\tval = rtw_read32(a, REG_CR_EXT);\n\t\tnetwork = BIT_GET_NETYPE2(val);\n\t\tbreak;\n\n\tcase HALMAC_PORTID3:\n\t\tval = rtw_read32(a, REG_CR_EXT);\n\t\tnetwork = BIT_GET_NETYPE3(val);\n\t\tbreak;\n\n\tcase HALMAC_PORTID4:\n\t\tval = rtw_read32(a, REG_CR_EXT);\n\t\tnetwork = BIT_GET_NETYPE4(val);\n\t\tbreak;\n\n\tdefault:\n\t\tgoto out;\n\t}\n\n\t*type = _network_type_halmac2drv(network);\n\n\terr = 0;\nout:\n\treturn err;\n#endif\n}\n\n/**\n * rtw_halmac_get_bcn_ctrl() - Get beacon control setting of specific port\n * @d:\t\tstruct dvobj_priv*\n * @hwport:\tport\n * @bcn_ctrl:\tsetting of beacon control\n *\n * Get beacon control setting of specific port from HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport,\n\t\t\tstruct rtw_halmac_bcn_ctrl *bcn_ctrl)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_portid port;\n\tstruct halmac_bcn_ctrl ctrl;\n\tenum halmac_ret_status status;\n\tint err = -1;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\tport = _hw_port_drv2halmac(hwport);\n\t_rtw_memset(&ctrl, 0, sizeof(ctrl));\n\n\tstatus = api->halmac_rw_bcn_ctrl(halmac, port, 0, &ctrl);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\t_beacon_ctrl_halmac2drv(&ctrl, bcn_ctrl);\n\n\terr = 0;\nout:\n\treturn err;\n}\n\n/*\n * Note:\n *\tWhen this function return, the register REG_RCR may be changed.\n */\nint rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tint err = -1;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tstatus = api->halmac_cfg_drv_info(halmac, info);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n\terr = 0;\nout:\n\t/* Sync driver RCR cache with register setting */\n\trtw_hal_get_hwreg(dvobj_get_primary_adapter(d), HW_VAR_RCR, NULL);\n\n\treturn err;\n}\n\n/**\n * rtw_halmac_set_max_dl_fw_size() - Set the MAX download firmware size\n * @d:\t\tstruct dvobj_priv*\n * @size:\tthe max download firmware size in one I/O\n *\n * Set the max download firmware size in one I/O.\n * Please also consider the max size of the callback function \"SEND_RSVD_PAGE\"\n * could accept, because download firmware would call \"SEND_RSVD_PAGE\" to send\n * firmware to IC.\n *\n * If the value of \"size\" is not even, it would be rounded down to nearest\n * even, and 0 and 1 are both invalid value.\n *\n * Return 0 for setting OK, otherwise fail.\n */\nint rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\n\n\tif (!size || (size == 1))\n\t\treturn -1;\n\n\tmac = dvobj_to_halmac(d);\n\tif (!mac) {\n\t\tRTW_ERR(\"%s: HALMAC is not ready!!\\n\", __FUNCTION__);\n\t\treturn -1;\n\t}\n\tapi = HALMAC_GET_API(mac);\n\n\tsize &= ~1; /* round down to even */\n\tstatus = api->halmac_cfg_max_dl_size(mac, size);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tRTW_WARN(\"%s: Fail to cfg_max_dl_size(%d), err=%d!!\\n\",\n\t\t\t __FUNCTION__, size, status);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/**\n * rtw_halmac_set_mac_address() - Set mac address of specific port\n * @d:\t\tstruct dvobj_priv*\n * @hwport:\tport\n * @addr:\tmac address\n *\n * Set self mac address of specific port to HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_portid port;\n\tunion halmac_wlan_addr hwa;\n\tenum halmac_ret_status status;\n\tint err = -1;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tport = _hw_port_drv2halmac(hwport);\n\t_rtw_memset(&hwa, 0, sizeof(hwa));\n\t_rtw_memcpy(hwa.addr, addr, 6);\n\n\tstatus = api->halmac_cfg_mac_addr(halmac, port, &hwa);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n\terr = 0;\nout:\n\treturn err;\n}\n\n/**\n * rtw_halmac_set_bssid() - Set BSSID of specific port\n * @d:\t\tstruct dvobj_priv*\n * @hwport:\tport\n * @addr:\tBSSID, mac address of AP\n *\n * Set BSSID of specific port to HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_portid port;\n\tunion halmac_wlan_addr hwa;\n\tenum halmac_ret_status status;\n\tint err = -1;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\tport = _hw_port_drv2halmac(hwport);\n\n\t_rtw_memset(&hwa, 0, sizeof(hwa));\n\t_rtw_memcpy(hwa.addr, addr, 6);\n\tstatus = api->halmac_cfg_bssid(halmac, port, &hwa);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n\terr = 0;\nout:\n\treturn err;\n}\n\n/**\n * rtw_halmac_set_tx_address() - Set transmitter address of specific port\n * @d:\t\tstruct dvobj_priv*\n * @hwport:\tport\n * @addr:\ttransmitter address\n *\n * Set transmitter address of specific port to HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_portid port;\n\tunion halmac_wlan_addr hwa;\n\tenum halmac_ret_status status;\n\tint err = -1;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\tport = _hw_port_drv2halmac(hwport);\n\t_rtw_memset(&hwa, 0, sizeof(hwa));\n\t_rtw_memcpy(hwa.addr, addr, 6);\n\n\tstatus = api->halmac_cfg_transmitter_addr(halmac, port, &hwa);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n\terr = 0;\nout:\n\treturn err;\n}\n\n/**\n * rtw_halmac_set_network_type() - Set network type of specific port\n * @d:\t\tstruct dvobj_priv*\n * @hwport:\tport\n * @type:\tnetwork type (_HW_STATE_*)\n *\n * Set network type of specific port to HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_portid port;\n\tenum halmac_network_type_select network;\n\tenum halmac_ret_status status;\n\tint err = -1;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\tport = _hw_port_drv2halmac(hwport);\n\tnetwork = _network_type_drv2halmac(type);\n\n\tstatus = api->halmac_cfg_net_type(halmac, port, network);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n\terr = 0;\nout:\n\treturn err;\n}\n\n/**\n * rtw_halmac_reset_tsf() - Reset TSF timer of specific port\n * @d:\t\tstruct dvobj_priv*\n * @hwport:\tport\n *\n * Notice HALMAC to reset timing synchronization function(TSF) timer of\n * specific port.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_portid port;\n\tenum halmac_ret_status status;\n\tint err = -1;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\tport = _hw_port_drv2halmac(hwport);\n\n\tstatus = api->halmac_cfg_tsf_rst(halmac, port);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n\terr = 0;\nout:\n\treturn err;\n}\n\n/**\n * rtw_halmac_set_bcn_interval() - Set beacon interval of each port\n * @d:\t\tstruct dvobj_priv*\n * @hwport:\tport\n * @space:\tbeacon interval, unit is ms\n *\n * Set beacon interval of specific port to HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport,\n\t\t\t\tu32 interval)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_portid port;\n\tenum halmac_ret_status status;\n\tint err = -1;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\tport = _hw_port_drv2halmac(hwport);\n\n\tstatus = api->halmac_cfg_bcn_space(halmac, port, interval);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n\terr = 0;\nout:\n\treturn err;\n}\n\n/**\n * rtw_halmac_set_bcn_ctrl() - Set beacon control setting of each port\n * @d:\t\tstruct dvobj_priv*\n * @hwport:\tport\n * @bcn_ctrl:\tsetting of beacon control\n *\n * Set beacon control setting of specific port to HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport,\n\t\t\tstruct rtw_halmac_bcn_ctrl *bcn_ctrl)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_portid port;\n\tstruct halmac_bcn_ctrl ctrl;\n\tenum halmac_ret_status status;\n\tint err = -1;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\tport = _hw_port_drv2halmac(hwport);\n\t_rtw_memset(&ctrl, 0, sizeof(ctrl));\n\t_beacon_ctrl_drv2halmac(bcn_ctrl, &ctrl);\n\n\tstatus = api->halmac_rw_bcn_ctrl(halmac, port, 1, &ctrl);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n\terr = 0;\nout:\n\treturn err;\n}\n\n/**\n * rtw_halmac_set_aid() - Set association identifier(AID) of specific port\n * @d:\t\tstruct dvobj_priv*\n * @hwport:\tport\n * @aid:\tAssociation identifier\n *\n * Set association identifier(AID) of specific port to HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_portid port;\n\tenum halmac_ret_status status;\n\tint err = -1;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\tport = _hw_port_drv2halmac(hwport);\n\n#if 0\n\tstatus = api->halmac_cfg_aid(halmac, port, aid);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n#else\n{\n\tstruct _ADAPTER *a;\n\tu32 addr;\n\tu16 val;\n\n\ta = dvobj_get_primary_adapter(d);\n\n\tswitch (port) {\n\tcase 0:\n\t\taddr = REG_BCN_PSR_RPT;\n\t\tval = rtw_read16(a, addr);\n\t\tval = BIT_SET_PS_AID_0(val, aid);\n\t\trtw_write16(a, addr, val);\n\t\tbreak;\n\n\tcase 1:\n\t\taddr = REG_BCN_PSR_RPT1;\n\t\tval = rtw_read16(a, addr);\n\t\tval = BIT_SET_PS_AID_1(val, aid);\n\t\trtw_write16(a, addr, val);\n\t\tbreak;\n\n\tcase 2:\n\t\taddr = REG_BCN_PSR_RPT2;\n\t\tval = rtw_read16(a, addr);\n\t\tval = BIT_SET_PS_AID_2(val, aid);\n\t\trtw_write16(a, addr, val);\n\t\tbreak;\n\n\tcase 3:\n\t\taddr = REG_BCN_PSR_RPT3;\n\t\tval = rtw_read16(a, addr);\n\t\tval = BIT_SET_PS_AID_3(val, aid);\n\t\trtw_write16(a, addr, val);\n\t\tbreak;\n\n\tcase 4:\n\t\taddr = REG_BCN_PSR_RPT4;\n\t\tval = rtw_read16(a, addr);\n\t\tval = BIT_SET_PS_AID_4(val, aid);\n\t\trtw_write16(a, addr, val);\n\t\tbreak;\n\n\tdefault:\n\t\tgoto out;\n\t}\n}\n#endif\n\n\terr = 0;\nout:\n\treturn err;\n}\n\nint rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_cfg_ch_bw(mac, channel, pri_ch_idx, bw);\n\tif (HALMAC_RET_SUCCESS != status)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/**\n * rtw_halmac_set_edca() - config edca parameter\n * @d:\t\tstruct dvobj_priv*\n * @queue:\tXMIT_[VO/VI/BE/BK]_QUEUE\n * @aifs:\tArbitration inter-frame space(AIFS)\n * @cw:\t\tContention window(CW)\n * @txop:\tMAX Transmit Opportunity(TXOP)\n *\n * Return: 0 if process OK, otherwise -1.\n */\nint rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_acq_id ac;\n\tstruct halmac_edca_para edca;\n\tenum halmac_ret_status status;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tswitch (queue) {\n\tcase XMIT_VO_QUEUE:\n\t\tac = HALMAC_ACQ_ID_VO;\n\t\tbreak;\n\tcase XMIT_VI_QUEUE:\n\t\tac = HALMAC_ACQ_ID_VI;\n\t\tbreak;\n\tcase XMIT_BE_QUEUE:\n\t\tac = HALMAC_ACQ_ID_BE;\n\t\tbreak;\n\tcase XMIT_BK_QUEUE:\n\t\tac = HALMAC_ACQ_ID_BK;\n\t\tbreak;\n\tdefault:\n\t\treturn -1;\n\t}\n\n\tedca.aifs = aifs;\n\tedca.cw = cw;\n\tedca.txop_limit = txop;\n\n\tstatus = api->halmac_cfg_edca_para(mac, ac, &edca);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/**\n * rtw_halmac_set_rts_full_bw() - Send RTS to all covered channels\n * @d:\t\tstruct dvobj_priv*\n * @enable:\t_TRUE(enable), _FALSE(disable)\n *\n * Hradware will duplicate RTS packet to all channels which are covered in used\n * bandwidth.\n *\n * Return 0 if process OK, otherwise -1.\n */\nint rtw_halmac_set_rts_full_bw(struct dvobj_priv *d, u8 enable)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu8 full;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\tfull = (enable == _TRUE) ? 1 : 0;\n\n\tstatus = api->halmac_set_hw_value(mac, HALMAC_HW_RTS_FULL_BW, &full);\n\tif (HALMAC_RET_SUCCESS != status)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n#ifdef RTW_HALMAC_DBG_POWER_SWITCH\nstatic void _dump_mac_reg(struct dvobj_priv *d, u32 start, u32 end)\n{\n\tstruct _ADAPTER *adapter;\n\tint i, j = 1;\n\n\n\tadapter = dvobj_get_primary_adapter(d);\n\tfor (i = start; i < end; i += 4) {\n\t\tif (j % 4 == 1)\n\t\t\tRTW_PRINT(\"0x%04x\", i);\n\t\t_RTW_PRINT(\" 0x%08x \", rtw_read32(adapter, i));\n\t\tif ((j++) % 4 == 0)\n\t\t\t_RTW_PRINT(\"\\n\");\n\t}\n}\n\nvoid dump_dbg_val(struct _ADAPTER *a, u32 reg)\n{\n\tu32 v32;\n\n\n\trtw_write8(a, 0x3A, reg);\n\tv32 = rtw_read32(a, 0xC0);\n\tRTW_PRINT(\"0x3A = %02x, 0xC0 = 0x%08x\\n\",reg, v32);\n}\n\n#ifdef CONFIG_PCI_HCI\nstatic void _dump_pcie_cfg_space(struct dvobj_priv *d)\n{\n\tstruct _ADAPTER *padapter = dvobj_get_primary_adapter(d);\n\tstruct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct pci_dev  *pdev = pdvobjpriv->ppcidev;\n\tstruct pci_dev  *bridge_pdev = pdev->bus->self;\n\n        u32 tmp[4] = { 0 };\n        u32 i, j;\n\n\tRTW_PRINT(\"\\n*****  PCI Device Configuration Space *****\\n\\n\");\n\n        for(i = 0; i < 0x100; i += 0x10)\n        {\n                for (j = 0 ; j < 4 ; j++)\n                        pci_read_config_dword(pdev, i + j * 4, tmp+j);\n\n        \tRTW_PRINT(\"%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\\n\",\n                        i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,\n                        tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,\n                        tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,\n                        tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);\n        }\n\n\tRTW_PRINT(\"\\n*****  PCI Host Device Configuration Space*****\\n\\n\");\n\n        for(i = 0; i < 0x100; i += 0x10)\n        {\n                for (j = 0 ; j < 4 ; j++)\n                        pci_read_config_dword(bridge_pdev, i + j * 4, tmp+j);\n\n        \tRTW_PRINT(\"%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\\n\",\n                        i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,\n                        tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,\n                        tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,\n                        tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);\n        }\n}\n#endif\n\nstatic void _dump_mac_reg_for_power_switch(struct dvobj_priv *d,\n\t\t\t\t\t   const char* caller, char* desc)\n{\n\tstruct _ADAPTER *a;\n\tu8 v8;\n\n\n\tRTW_PRINT(\"%s: %s\\n\", caller, desc);\n\tRTW_PRINT(\"======= MAC REG =======\\n\");\n\t/* page 0/1 */\n\t_dump_mac_reg(d, 0x0, 0x200);\n\t_dump_mac_reg(d, 0x300, 0x400); /* also dump page 3 */\n\n\t/* dump debug register */\n\ta = dvobj_get_primary_adapter(d);\n\n#ifdef CONFIG_PCI_HCI\n\t_dump_pcie_cfg_space(d);\n\n\tv8 = rtw_read8(a, 0xF6) | 0x01;\n\trtw_write8(a, 0xF6, v8);\n\tRTW_PRINT(\"0xF6 = %02x\\n\", v8);\n\n\tdump_dbg_val(a, 0x63);\n\tdump_dbg_val(a, 0x64);\n\tdump_dbg_val(a, 0x68);\n\tdump_dbg_val(a, 0x69);\n\tdump_dbg_val(a, 0x6a);\n\tdump_dbg_val(a, 0x6b);\n\tdump_dbg_val(a, 0x71);\n\tdump_dbg_val(a, 0x72);\n#endif\n}\n\nstatic enum halmac_ret_status _power_switch(struct halmac_adapter *halmac,\n\t\t\t\t\t    struct halmac_api *api,\n\t\t\t\t\t    enum halmac_mac_power pwr)\n{\n\tenum halmac_ret_status status;\n\tchar desc[80] = {0};\n\n\n\trtw_sprintf(desc, 80, \"before calling power %s\",\n\t\t\t\t(pwr==HALMAC_MAC_POWER_ON)?\"on\":\"off\");\n\t_dump_mac_reg_for_power_switch((struct dvobj_priv *)halmac->drv_adapter,\n\t\t\t__FUNCTION__, desc);\n\n\tstatus = api->halmac_mac_power_switch(halmac, pwr);\n\tRTW_PRINT(\"%s: status=%d\\n\", __FUNCTION__, status);\n\n\trtw_sprintf(desc, 80, \"after calling power %s\",\n\t\t\t\t(pwr==HALMAC_MAC_POWER_ON)?\"on\":\"off\");\n\t_dump_mac_reg_for_power_switch((struct dvobj_priv *)halmac->drv_adapter,\n\t\t\t__FUNCTION__, desc);\n\n\treturn status;\n}\n#else /* !RTW_HALMAC_DBG_POWER_SWITCH */\n#define _power_switch(mac, api, pwr)\t(api)->halmac_mac_power_switch(mac, pwr)\n#endif /* !RTW_HALMAC_DBG_POWER_SWITCH */\n\n/*\n * Description:\n *\tPower on device hardware.\n *\t[Notice!] If device's power state is on before,\n *\tit would be power off first and turn on power again.\n *\n * Return:\n *\t0\tpower on success\n *\t-1\tpower on fail\n *\t-2\tpower state unchange\n */\nint rtw_halmac_poweron(struct dvobj_priv *d)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tint err = -1;\n#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B)\n\tstruct _ADAPTER *a;\n\tu8 v8;\n\tu32 addr;\n\n\ta = dvobj_get_primary_adapter(d);\n#endif\n\n\thalmac = dvobj_to_halmac(d);\n\tif (!halmac)\n\t\tgoto out;\n\n\tapi = HALMAC_GET_API(halmac);\n\n\tstatus = api->halmac_pre_init_system_cfg(halmac);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n#ifdef CONFIG_SDIO_HCI\n\tstatus = api->halmac_sdio_cmd53_4byte(halmac, HALMAC_SDIO_CMD53_4BYTE_MODE_RW);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n#endif /* CONFIG_SDIO_HCI */\n\n#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B)\n\taddr = 0x3F3;\n\tv8 = rtw_read8(a, addr);\n\tRTW_PRINT(\"%s: 0x%X = 0x%02x\\n\", __FUNCTION__, addr, v8);\n\t/* are we in pcie debug mode? */\n\tif (!(v8 & BIT(2))) {\n\t\tRTW_PRINT(\"%s: Enable pcie debug mode\\n\", __FUNCTION__);\n\t\tv8 |= BIT(2);\n\t\tv8 = rtw_write8(a, addr, v8);\n\t}\n#endif\n\n\tstatus = _power_switch(halmac, api, HALMAC_MAC_POWER_ON);\n\tif (HALMAC_RET_PWR_UNCHANGE == status) {\n\n#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B)\n\t\taddr = 0x3F3;\n\t\tv8 = rtw_read8(a, addr);\n\t\tRTW_PRINT(\"%s: 0x%X = 0x%02x\\n\", __FUNCTION__, addr, v8);\n\t\t\n\t\t/* are we in pcie debug mode? */\n\t\tif (!(v8 & BIT(2))) {\n\t\t\tRTW_PRINT(\"%s: Enable pcie debug mode\\n\", __FUNCTION__);\n\t\t\tv8 |= BIT(2);\n\t\t\tv8 = rtw_write8(a, addr, v8);\n\t\t} else if (v8 & BIT(0)) {\n\t\t\t/* DMA stuck */\n\t\t\taddr = 0x1350;\n\t\t\tv8 = rtw_read8(a, addr);\n\t\t\tRTW_PRINT(\"%s: 0x%X = 0x%02x\\n\", __FUNCTION__, addr, v8);\n\t\t\tRTW_PRINT(\"%s: recover DMA stuck\\n\", __FUNCTION__);\n\t\t\tv8 |= BIT(6);\n\t\t\tv8 = rtw_write8(a, addr, v8);\n\t\t\tRTW_PRINT(\"%s: 0x%X = 0x%02x\\n\", __FUNCTION__, addr, v8);\n\t\t}\n#endif\n\t\t/*\n\t\t * Work around for warm reboot but device not power off,\n\t\t * but it would also fall into this case when auto power on is enabled.\n\t\t */\n\t\t_power_switch(halmac, api, HALMAC_MAC_POWER_OFF);\n\t\tstatus = _power_switch(halmac, api, HALMAC_MAC_POWER_ON);\n\t\tRTW_WARN(\"%s: Power state abnormal, try to recover...%s\\n\",\n\t\t\t __FUNCTION__, (HALMAC_RET_SUCCESS == status)?\"OK\":\"FAIL!\");\n\t}\n\tif (HALMAC_RET_SUCCESS != status) {\n\t\tif (HALMAC_RET_PWR_UNCHANGE == status)\n\t\t\terr = -2;\n\t\tgoto out;\n\t}\n\n\tstatus = api->halmac_init_system_cfg(halmac);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n\terr = 0;\nout:\n\treturn err;\n}\n\n/*\n * Description:\n *\tPower off device hardware.\n *\n * Return:\n *\t0\tPower off success\n *\t-1\tPower off fail\n */\nint rtw_halmac_poweroff(struct dvobj_priv *d)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tint err = -1;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tif (!halmac)\n\t\tgoto out;\n\n\tapi = HALMAC_GET_API(halmac);\n\n\tstatus = _power_switch(halmac, api, HALMAC_MAC_POWER_OFF);\n\tif ((HALMAC_RET_SUCCESS != status)\n\t    && (HALMAC_RET_PWR_UNCHANGE != status))\n\t\tgoto out;\n\n\terr = 0;\nout:\n\treturn err;\n}\n\n#ifdef CONFIG_SUPPORT_TRX_SHARED\nstatic inline enum halmac_rx_fifo_expanding_mode _trx_share_mode_drv2halmac(u8 trx_share_mode)\n{\n\tif (0 == trx_share_mode)\n\t\treturn HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE;\n\telse if (1 == trx_share_mode)\n\t\treturn HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK;\n\telse if (2 == trx_share_mode)\n\t\treturn HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK;\n\telse if (3 == trx_share_mode)\n\t\treturn HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK;\n\telse\n\t\treturn HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE;\n}\n\nstatic enum halmac_rx_fifo_expanding_mode _rtw_get_trx_share_mode(struct _ADAPTER *adapter)\n{\n\tstruct registry_priv *registry_par = &adapter->registrypriv;\n\n\treturn _trx_share_mode_drv2halmac(registry_par->trx_share_mode);\n}\n\nvoid dump_trx_share_mode(void *sel, struct _ADAPTER *adapter)\n{\n\tstruct registry_priv  *registry_par = &adapter->registrypriv;\n\tu8 mode = _trx_share_mode_drv2halmac(registry_par->trx_share_mode);\n\n\tif (HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK == mode)\n\t\tRTW_PRINT_SEL(sel, \"TRx share mode : %s\\n\", \"RX_FIFO_EXPANDING_MODE_1\");\n\telse if (HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK == mode)\n\t\tRTW_PRINT_SEL(sel, \"TRx share mode : %s\\n\", \"RX_FIFO_EXPANDING_MODE_2\");\n\telse if (HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK == mode)\n\t\tRTW_PRINT_SEL(sel, \"TRx share mode : %s\\n\", \"RX_FIFO_EXPANDING_MODE_3\");\n\telse\n\t\tRTW_PRINT_SEL(sel, \"TRx share mode : %s\\n\", \"DISABLE\");\n}\n#endif\n\nstatic enum halmac_drv_rsvd_pg_num _rsvd_page_num_drv2halmac(u16 num)\n{\n\tif (num <= 8)\n\t\treturn HALMAC_RSVD_PG_NUM8;\n\tif (num <= 16)\n\t\treturn HALMAC_RSVD_PG_NUM16;\n\tif (num <= 24)\n\t\treturn HALMAC_RSVD_PG_NUM24;\n\tif (num <= 32)\n\t\treturn HALMAC_RSVD_PG_NUM32;\n\tif (num <= 64)\n\t\treturn HALMAC_RSVD_PG_NUM64;\n\tif (num <= 128)\n\t\treturn HALMAC_RSVD_PG_NUM128;\n\n\tif (num > 256)\n\t\tRTW_WARN(\"%s: Fail to allocate RSVD page(%d)!!\"\n\t\t\t \" The MAX RSVD page number is 256...\\n\",\n\t\t\t __FUNCTION__, num);\n\n\treturn HALMAC_RSVD_PG_NUM256;\n}\n\nstatic u16 _rsvd_page_num_halmac2drv(enum halmac_drv_rsvd_pg_num rsvd_page_number)\n{\n\tu16 num = 0;\n\n\n\tswitch (rsvd_page_number) {\n\tcase HALMAC_RSVD_PG_NUM8:\n\t\tnum = 8;\n\t\tbreak;\n\n\tcase HALMAC_RSVD_PG_NUM16:\n\t\tnum = 16;\n\t\tbreak;\n\n\tcase HALMAC_RSVD_PG_NUM24:\n\t\tnum = 24;\n\t\tbreak;\n\n\tcase HALMAC_RSVD_PG_NUM32:\n\t\tnum = 32;\n\t\tbreak;\n\n\tcase HALMAC_RSVD_PG_NUM64:\n\t\tnum = 64;\n\t\tbreak;\n\n\tcase HALMAC_RSVD_PG_NUM128:\n\t\tnum = 128;\n\t\tbreak;\n\n\tcase HALMAC_RSVD_PG_NUM256:\n\t\tnum = 256;\n\t\tbreak;\n\t}\n\n\treturn num;\n}\n\nstatic enum halmac_trx_mode _choose_trx_mode(struct dvobj_priv *d)\n{\n\tPADAPTER p;\n\n\n\tp = dvobj_get_primary_adapter(d);\n\n\tif (p->registrypriv.wifi_spec)\n\t\treturn HALMAC_TRX_MODE_WMM;\n\n#ifdef CONFIG_SUPPORT_TRX_SHARED\n\tif (_rtw_get_trx_share_mode(p))\n\t\treturn HALMAC_TRX_MODE_TRXSHARE;\n#endif\n\n\treturn HALMAC_TRX_MODE_NORMAL;\n}\n\nstatic inline enum halmac_rf_type _rf_type_drv2halmac(enum rf_type rf_drv)\n{\n\tenum halmac_rf_type rf_mac;\n\n\n\tswitch (rf_drv) {\n\tcase RF_1T1R:\n\t\trf_mac = HALMAC_RF_1T1R;\n\t\tbreak;\n\tcase RF_1T2R:\n\t\trf_mac = HALMAC_RF_1T2R;\n\t\tbreak;\n\tcase RF_2T2R:\n\t\trf_mac = HALMAC_RF_2T2R;\n\t\tbreak;\n\tcase RF_2T3R:\n\t\trf_mac = HALMAC_RF_2T3R;\n\t\tbreak;\n\tcase RF_2T4R:\n\t\trf_mac = HALMAC_RF_2T4R;\n\t\tbreak;\n\tcase RF_3T3R:\n\t\trf_mac = HALMAC_RF_3T3R;\n\t\tbreak;\n\tcase RF_3T4R:\n\t\trf_mac = HALMAC_RF_3T4R;\n\t\tbreak;\n\tcase RF_4T4R:\n\t\trf_mac = HALMAC_RF_4T4R;\n\t\tbreak;\n\tdefault:\n\t\trf_mac = HALMAC_RF_MAX_TYPE;\n\t\tRTW_ERR(\"%s: Invalid RF type(0x%x)!\\n\", __FUNCTION__, rf_drv);\n\t\tbreak;\n\t}\n\n\treturn rf_mac;\n}\n\nstatic inline enum rf_type _rf_type_halmac2drv(enum halmac_rf_type rf_mac)\n{\n\tenum rf_type rf_drv;\n\n\n\tswitch (rf_mac) {\n\tcase HALMAC_RF_1T2R:\n\t\trf_drv = RF_1T2R;\n\t\tbreak;\n\tcase HALMAC_RF_2T4R:\n\t\trf_drv = RF_2T4R;\n\t\tbreak;\n\tcase HALMAC_RF_2T2R:\n\tcase HALMAC_RF_2T2R_GREEN:\n\t\trf_drv = RF_2T2R;\n\t\tbreak;\n\tcase HALMAC_RF_2T3R:\n\t\trf_drv = RF_2T3R;\n\t\tbreak;\n\tcase HALMAC_RF_1T1R:\n\t\trf_drv = RF_1T1R;\n\t\tbreak;\n\tcase HALMAC_RF_3T3R:\n\t\trf_drv = RF_3T3R;\n\t\tbreak;\n\tcase HALMAC_RF_3T4R:\n\t\trf_drv = RF_3T4R;\n\t\tbreak;\n\tcase HALMAC_RF_4T4R:\n\t\trf_drv = RF_4T4R;\n\t\tbreak;\n\tdefault:\n\t\trf_drv = RF_TYPE_MAX;\n\t\tRTW_ERR(\"%s: Invalid RF type(0x%x)!\\n\", __FUNCTION__, rf_mac);\n\t\tbreak;\n\t}\n\n\treturn rf_drv;\n}\n\nstatic enum odm_cut_version _cut_version_drv2phydm(\n\t\t\t\tenum tag_HAL_Cut_Version_Definition cut_drv)\n{\n\tenum odm_cut_version cut_phydm = ODM_CUT_A;\n\tu32 diff;\n\n\n\tif (cut_drv > K_CUT_VERSION)\n\t\tRTW_WARN(\"%s: unknown cut_ver=%d !!\\n\", __FUNCTION__, cut_drv);\n\n\tdiff = cut_drv - A_CUT_VERSION;\n\tcut_phydm += diff;\n\n\treturn cut_phydm;\n}\n\nstatic int _send_general_info_by_reg(struct dvobj_priv *d,\n\t\t\t\t     struct halmac_general_info *info)\n{\n\tstruct _ADAPTER *a;\n\tstruct hal_com_data *hal;\n\tenum tag_HAL_Cut_Version_Definition cut_drv;\n\tenum rf_type rftype;\n\tenum odm_cut_version cut_phydm;\n\tu8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0};\n\n\n\ta = dvobj_get_primary_adapter(d);\n\thal = GET_HAL_DATA(a);\n\trftype = _rf_type_halmac2drv(info->rf_type);\n\tcut_drv = GET_CVID_CUT_VERSION(hal->version_id);\n\tcut_phydm = _cut_version_drv2phydm(cut_drv);\n\n#define CLASS_GENERAL_INFO_REG\t\t\t\t0x02\n#define CMD_ID_GENERAL_INFO_REG\t\t\t\t0x0C\n#define GENERAL_INFO_REG_SET_CMD_ID(buf, v)\t\tSET_BITS_TO_LE_4BYTE(buf, 0, 5, v)\n#define GENERAL_INFO_REG_SET_CLASS(buf, v)\t\tSET_BITS_TO_LE_4BYTE(buf, 5, 3, v)\n#define GENERAL_INFO_REG_SET_RFE_TYPE(buf, v)\t\tSET_BITS_TO_LE_4BYTE(buf, 8, 8, v)\n#define GENERAL_INFO_REG_SET_RF_TYPE(buf, v)\t\tSET_BITS_TO_LE_4BYTE(buf, 16, 8, v)\n#define GENERAL_INFO_REG_SET_CUT_VERSION(buf, v)\tSET_BITS_TO_LE_4BYTE(buf, 24, 8, v)\n#define GENERAL_INFO_REG_SET_RX_ANT_STATUS(buf, v)\tSET_BITS_TO_LE_1BYTE(buf+4, 0, 4, v)\n#define GENERAL_INFO_REG_SET_TX_ANT_STATUS(buf, v)\tSET_BITS_TO_LE_1BYTE(buf+4, 4, 4, v)\n\n\tGENERAL_INFO_REG_SET_CMD_ID(h2c, CMD_ID_GENERAL_INFO_REG);\n\tGENERAL_INFO_REG_SET_CLASS(h2c, CLASS_GENERAL_INFO_REG);\n\tGENERAL_INFO_REG_SET_RFE_TYPE(h2c, info->rfe_type);\n\tGENERAL_INFO_REG_SET_RF_TYPE(h2c, rftype);\n\tGENERAL_INFO_REG_SET_CUT_VERSION(h2c, cut_phydm);\n\tGENERAL_INFO_REG_SET_RX_ANT_STATUS(h2c, info->rx_ant_status);\n\tGENERAL_INFO_REG_SET_TX_ANT_STATUS(h2c, info->tx_ant_status);\n\n\treturn rtw_halmac_send_h2c(d, h2c);\n}\n\nstatic int _send_general_info(struct dvobj_priv *d)\n{\n\tstruct _ADAPTER *adapter;\n\tstruct hal_com_data *hal;\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tstruct halmac_general_info info;\n\tenum halmac_ret_status status;\n\tenum rf_type rf = RF_1T1R;\n\tenum bb_path txpath = BB_PATH_A;\n\tenum bb_path rxpath = BB_PATH_A;\n\tint err;\n\n\n\tadapter = dvobj_get_primary_adapter(d);\n\thal = GET_HAL_DATA(adapter);\n\thalmac = dvobj_to_halmac(d);\n\tif (!halmac)\n\t\treturn -1;\n\tapi = HALMAC_GET_API(halmac);\n\n\t_rtw_memset(&info, 0, sizeof(info));\n\tinfo.rfe_type = (u8)hal->rfe_type;\n\trtw_hal_get_rf_path(d, &rf, &txpath, &rxpath);\n\tinfo.rf_type = _rf_type_drv2halmac(rf);\n\tinfo.tx_ant_status = (u8)txpath;\n\tinfo.rx_ant_status = (u8)rxpath;\n\n\tstatus = api->halmac_send_general_info(halmac, &info);\n\tswitch (status) {\n\tcase HALMAC_RET_SUCCESS:\n\t\tbreak;\n\tcase HALMAC_RET_NO_DLFW:\n\t\tRTW_WARN(\"%s: halmac_send_general_info() fail because fw not dl!\\n\",\n\t\t\t __FUNCTION__);\n\t\t/* go through */\n\tdefault:\n\t\treturn -1;\n\t}\n\n\terr = _send_general_info_by_reg(d, &info);\n\tif (err) {\n\t\tRTW_ERR(\"%s: Fail to send general info by register!\\n\",\n\t\t\t __FUNCTION__);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int _cfg_drv_rsvd_pg_num(struct dvobj_priv *d)\n{\n\tstruct _ADAPTER *a;\n\tstruct hal_com_data *hal;\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_drv_rsvd_pg_num rsvd_page_number;\n\tenum halmac_ret_status status;\n\tu16 drv_rsvd_num;\n\tint ret = 0;\n\n\n\ta = dvobj_get_primary_adapter(d);\n\thal = GET_HAL_DATA(a);\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tdrv_rsvd_num = rtw_hal_get_rsvd_page_num(a);\n\trsvd_page_number = _rsvd_page_num_drv2halmac(drv_rsvd_num);\n\tstatus = api->halmac_cfg_drv_rsvd_pg_num(halmac, rsvd_page_number);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\thal->drv_rsvd_page_number = _rsvd_page_num_halmac2drv(rsvd_page_number);\n\nexit:\n#ifndef DBG_RSVD_PAGE_CFG\n\tif (drv_rsvd_num != _rsvd_page_num_halmac2drv(rsvd_page_number))\n#endif\n\t\tRTW_INFO(\"%s: request %d pages => halmac %d pages %s\\n\"\n\t\t\t, __FUNCTION__, drv_rsvd_num, _rsvd_page_num_halmac2drv(rsvd_page_number)\n\t\t\t, ret ? \"fail\" : \"success\");\n\n\treturn ret;\n}\n\nstatic void _debug_dlfw_fail(struct dvobj_priv *d)\n{\n\tstruct _ADAPTER *a;\n\tu32 addr;\n\tu32 v32, i, n;\n\tu8 data[0x100] = {0};\n\n\n\ta = dvobj_get_primary_adapter(d);\n\n\t/* read 0x80[15:0], 0x10F8[31:0] once */\n\taddr = 0x80;\n\tv32 = rtw_read16(a, addr);\n\tRTW_PRINT(\"%s: 0x%X = 0x%04x\\n\", __FUNCTION__, addr, v32);\n\n\taddr = 0x10F8;\n\tv32 = rtw_read32(a, addr);\n\tRTW_PRINT(\"%s: 0x%X = 0x%08x\\n\", __FUNCTION__, addr, v32);\n\n\t/* read 0x10FC[31:0], 5 times */\n\taddr = 0x10FC;\n\tn = 5;\n\tfor (i = 0; i < n; i++) {\n\t\tv32 = rtw_read32(a, addr);\n\t\tRTW_PRINT(\"%s: 0x%X = 0x%08x (%u/%u)\\n\",\n\t\t\t  __FUNCTION__, addr, v32, i, n);\n\t}\n\n\t/*\n\t * write 0x3A[7:0]=0x28 and 0xF6[7:0]=0x01\n\t * and then read 0xC0[31:0] 5 times\n\t */\n\taddr = 0x3A;\n\tv32 = 0x28;\n\trtw_write8(a, addr, (u8)v32);\n\tv32 = rtw_read8(a, addr);\n\tRTW_PRINT(\"%s: 0x%X = 0x%02x\\n\", __FUNCTION__, addr, v32);\n\n\taddr = 0xF6;\n\tv32 = 0x1;\n\trtw_write8(a, addr, (u8)v32);\n\tv32 = rtw_read8(a, addr);\n\tRTW_PRINT(\"%s: 0x%X = 0x%02x\\n\", __FUNCTION__, addr, v32);\n\n\taddr = 0xC0;\n\tn = 5;\n\tfor (i = 0; i < n; i++) {\n\t\tv32 = rtw_read32(a, addr);\n\t\tRTW_PRINT(\"%s: 0x%X = 0x%08x (%u/%u)\\n\",\n\t\t\t  __FUNCTION__, addr, v32, i, n);\n\t}\n\n\t/* 0x00~0xFF, 0x1000~0x10FF */\n\taddr = 0;\n\tn = 0x100;\n\tfor (i = 0; i < n; i+=4)\n\t\t*(u32*)&data[i] = cpu_to_le32(rtw_read32(a, addr+i));\n\tfor (i = 0; i < n; i++) {\n\t\tif (i % 16 == 0)\n\t\t\tRTW_PRINT(\"0x%04x\\t\", addr+i);\n\t\t_RTW_PRINT(\"0x%02x\", data[i]);\n\t\tif (i % 16 == 15)\n\t\t\t_RTW_PRINT(\"\\n\");\n\t\telse\n\t\t\t_RTW_PRINT(\" \");\n\t}\n\n\taddr = 0x1000;\n\tn = 0x100;\n\tfor (i = 0; i < n; i+=4)\n\t\t*(u32*)&data[i] = cpu_to_le32(rtw_read32(a, addr+i));\n\tfor (i = 0; i < n; i++) {\n\t\tif (i % 16 == 0)\n\t\t\tRTW_PRINT(\"0x%04x\\t\", addr+i);\n\t\t_RTW_PRINT(\"0x%02x\", data[i]);\n\t\tif (i % 16 == 15)\n\t\t\t_RTW_PRINT(\"\\n\");\n\t\telse\n\t\t\t_RTW_PRINT(\" \");\n\t}\n\n\t/* read 0x80 after 10 secs */\n\trtw_msleep_os(10000);\n\taddr = 0x80;\n\tv32 = rtw_read16(a, addr);\n\tRTW_PRINT(\"%s: 0x%X = 0x%04x (after 10 secs)\\n\",\n\t\t  __FUNCTION__, addr, v32);\n}\n\nstatic enum halmac_ret_status _enter_cpu_sleep_mode(struct dvobj_priv *d)\n{\n\tstruct hal_com_data *hal;\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\n\n\thal = GET_HAL_DATA(dvobj_get_primary_adapter(d));\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n#ifdef CONFIG_RTL8822B\n\t/* Support after firmware version 21 */\n\tif (hal->firmware_version < 21)\n\t\treturn HALMAC_RET_NOT_SUPPORT;\n#elif defined(CONFIG_RTL8821C)\n\t/* Support after firmware version 13.6 or 16 */\n\tif (hal->firmware_version == 13) {\n\t\tif (hal->firmware_sub_version < 6)\n\t\t\treturn HALMAC_RET_NOT_SUPPORT;\n\t} else if (hal->firmware_version < 16) {\n\t\treturn HALMAC_RET_NOT_SUPPORT;\n\t}\n#endif\n\n\treturn api->halmac_enter_cpu_sleep_mode(mac);\n}\n\n/*\n * _cpu_sleep() - Let IC CPU enter sleep mode\n * @d:\t\tstruct dvobj_priv*\n * @timeout:\ttime limit of wait, unit is ms\n *\t\t0 for no limit\n *\n * Rteurn 0 for CPU in sleep mode, otherwise fail to enter sleep mode.\n * Error codes definition are as follow:\n * \t-1\tHALMAC enter sleep return fail\n *\t-2\tHALMAC get CPU mode return fail\n *\t-110\ttimeout\n */\nstatic int _cpu_sleep(struct dvobj_priv *d, u32 timeout)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tenum halmac_wlcpu_mode mode = HALMAC_WLCPU_UNDEFINE;\n\tsystime start_t;\n\ts32 period = 0;\n\tu32 cnt = 0;\n\tint err = 0;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstart_t = rtw_get_current_time();\n\n\tstatus = _enter_cpu_sleep_mode(d);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tif (status != HALMAC_RET_NOT_SUPPORT)\n\t\t\terr = -1;\n\t\tgoto exit;\n\t}\n\n\tdo {\n\t\tcnt++;\n\n\t\tmode = HALMAC_WLCPU_UNDEFINE;\n\t\tstatus = api->halmac_get_cpu_mode(mac, &mode);\n\n\t\tperiod = rtw_get_passing_time_ms(start_t);\n\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\terr = -2;\n\t\t\tbreak;\n\t\t}\n\t\tif (mode == HALMAC_WLCPU_SLEEP)\n\t\t\tbreak;\n\t\tif (period > timeout) {\n\t\t\terr = -110;\n\t\t\tbreak;\n\t\t}\n\n\t\trtw_msleep_os(1);\n\t} while (1);\n\nexit:\n\tif (err)\n\t\tRTW_ERR(\"%s: Fail to enter sleep mode! (%d, %d)\\n\",\n\t\t\t__FUNCTION__, status, mode);\n\n\tRTW_INFO(\"%s: Cost %dms to polling %u times. (err=%d)\\n\",\n\t\t__FUNCTION__, period, cnt, err);\n\n\treturn err;\n}\n\nstatic void _init_trx_cfg_drv(struct dvobj_priv *d)\n{\n#ifdef CONFIG_PCI_HCI\n\trtw_hal_irp_reset(dvobj_get_primary_adapter(d));\n#endif\n}\n\n/*\n * Description:\n *\tDownlaod Firmware Flow\n *\n * Parameters:\n *\td\tpointer of struct dvobj_priv\n *\tfw\tfirmware array\n *\tfwsize\tfirmware size\n *\tre_dl\tre-download firmware or not\n *\t\t0: run in init hal flow, not re-download\n *\t\t1: it is a stand alone operation, not in init hal flow\n *\n * Return:\n *\t0\tSuccess\n *\tothers\tFail\n */\nstatic int download_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize, u8 re_dl)\n{\n\tPHAL_DATA_TYPE hal;\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tstruct halmac_fw_version fw_vesion;\n\tenum halmac_ret_status status;\n\tint err = 0;\n\n\n\thal = GET_HAL_DATA(dvobj_get_primary_adapter(d));\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tif ((!fw) || (!fwsize))\n\t\treturn -1;\n\n\t/* 1. Driver Stop Tx */\n\t/* ToDo */\n\n\t/* 2. Driver Check Tx FIFO is empty */\n\terr = rtw_halmac_txfifo_wait_empty(d, 2000); /* wait 2s */\n\tif (err) {\n\t\terr = -1;\n\t\tgoto resume_tx;\n\t}\n\n\t/* 3. Config MAX download size */\n\t/*\n\t * Already done in rtw_halmac_init_adapter() or\n\t * somewhere calling rtw_halmac_set_max_dl_fw_size().\n\t */\n\n\tif (re_dl) {\n\t\t/* 4. Enter IC CPU sleep mode */\n\t\terr = _cpu_sleep(d, 2000);\n\t\tif (err) {\n\t\t\tRTW_ERR(\"%s: IC CPU fail to enter sleep mode!(%d)\\n\",\n\t\t\t\t__FUNCTION__, err);\n\t\t\t/* skip this error */\n\t\t\terr = 0;\n\t\t}\n\t}\n\n\t/* 5. Download Firmware */\n\tstatus = api->halmac_download_firmware(mac, fw, fwsize);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tRTW_ERR(\"%s: download firmware FAIL! status=0x%02x\\n\",\n\t\t\t__FUNCTION__, status);\n\t\t_debug_dlfw_fail(d);\n\t\terr = -1;\n\t\tgoto resume_tx;\n\t}\n\n\t/* 5.1. (Driver) Reset driver variables if needed */\n\thal->LastHMEBoxNum = 0;\n\n\t/* 5.2. (Driver) Get FW version */\n\tstatus = api->halmac_get_fw_version(mac, &fw_vesion);\n\tif (status == HALMAC_RET_SUCCESS) {\n\t\thal->firmware_version = fw_vesion.version;\n\t\thal->firmware_sub_version = fw_vesion.sub_version;\n\t\thal->firmware_size = fwsize;\n\t}\n\nresume_tx:\n\t/* 6. Driver resume TX if needed */\n\t/* ToDo */\n\n\tif (err)\n\t\tgoto exit;\n\n\tif (re_dl) {\n\t\tenum halmac_trx_mode mode;\n\n\t\t/* 7. Change reserved page size */\n\t\terr = _cfg_drv_rsvd_pg_num(d);\n\t\tif (err)\n\t\t\treturn -1;\n\n\t\t/* 8. Init TRX Configuration */\n\t\tmode = _choose_trx_mode(d);\n\t\tstatus = api->halmac_init_trx_cfg(mac, mode);\n\t\tif (HALMAC_RET_SUCCESS != status)\n\t\t\treturn -1;\n\t\t_init_trx_cfg_drv(d);\n\n\t\t/* 9. Config RX Aggregation */\n\t\terr = rtw_halmac_rx_agg_switch(d, _TRUE);\n\t\tif (err)\n\t\t\treturn -1;\n\n\t\t/* 10. Send General Info */\n\t\terr = _send_general_info(d);\n\t\tif (err)\n\t\t\treturn -1;\n\t}\n\nexit:\n\treturn err;\n}\n\nstatic int init_mac_flow(struct dvobj_priv *d)\n{\n\tPADAPTER p;\n\tstruct hal_com_data *hal;\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_drv_rsvd_pg_num rsvd_page_number;\n\tunion halmac_wlan_addr hwa;\n\tenum halmac_trx_mode trx_mode;\n\tenum halmac_ret_status status;\n\tu8 drv_rsvd_num;\n\tu8 nettype;\n\tint err, err_ret = -1;\n\n\n\tp = dvobj_get_primary_adapter(d);\n\thal = GET_HAL_DATA(p);\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n#ifdef CONFIG_SUPPORT_TRX_SHARED\n\tstatus = api->halmac_cfg_rxff_expand_mode(halmac,\n\t\t\t\t\t\t  _rtw_get_trx_share_mode(p));\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n#endif\n\n#ifdef DBG_LA_MODE\n\tif (dvobj_to_regsty(d)->la_mode_en) {\n\t\tstatus = api->halmac_cfg_la_mode(halmac, HALMAC_LA_MODE_PARTIAL);\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\tRTW_ERR(\"%s: Fail to enable LA mode!\\n\", __FUNCTION__);\n\t\t\tgoto out;\n\t\t}\n\t\tRTW_PRINT(\"%s: Enable LA mode OK.\\n\", __FUNCTION__);\n\t}\n#endif\n\n\terr = _cfg_drv_rsvd_pg_num(d);\n\tif (err)\n\t\tgoto out;\n\n#ifdef CONFIG_USB_HCI\n\tstatus = api->halmac_set_bulkout_num(halmac, d->RtNumOutPipes);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n#endif /* CONFIG_USB_HCI */\n\n\ttrx_mode = _choose_trx_mode(d);\n\tstatus = api->halmac_init_mac_cfg(halmac, trx_mode);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n\t/* Driver insert flow: Sync driver setting with register */\n\t/* Sync driver RCR cache with register setting */\n\trtw_hal_get_hwreg(dvobj_get_primary_adapter(d), HW_VAR_RCR, NULL);\n\n\t_init_trx_cfg_drv(d);\n\t/* Driver inser flow end */\n\n\terr = rtw_halmac_rx_agg_switch(d, _TRUE);\n\tif (err)\n\t\tgoto out;\n\n\tnettype = dvobj_to_regsty(d)->wireless_mode;\n\tif (is_supported_vht(nettype) == _TRUE)\n\t\tstatus = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_AC);\n\telse if (is_supported_ht(nettype) == _TRUE)\n\t\tstatus = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_N);\n\telse if (IsSupportedTxOFDM(nettype) == _TRUE)\n\t\tstatus = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_G);\n\telse\n\t\tstatus = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_B);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n\terr_ret = 0;\nout:\n\treturn err_ret;\n}\n\nstatic int _drv_enable_trx(struct dvobj_priv *d)\n{\n\tstruct _ADAPTER *adapter;\n\tu32 status;\n\n\n\tadapter = dvobj_get_primary_adapter(d);\n\tif (adapter->bup == _FALSE) {\n#ifdef CONFIG_NEW_NETDEV_HDL\n\t\tstatus = rtw_mi_start_drv_threads(adapter);\n#else\n\t\tstatus = rtw_start_drv_threads(adapter);\n#endif\n\t\tif (status == _FAIL) {\n\t\t\tRTW_ERR(\"%s: Start threads Failed!\\n\", __FUNCTION__);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\trtw_intf_start(adapter);\n\n\treturn 0;\n}\n\n/*\n * Notices:\n *\tMake sure\n *\t1. rtw_hal_get_hwreg(HW_VAR_RF_TYPE)\n *\t2. HAL_DATA_TYPE.rfe_type\n *\talready ready for use before calling this function.\n */\nstatic int _halmac_init_hal(struct dvobj_priv *d, u8 *fw, u32 fwsize)\n{\n\tPADAPTER adapter;\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 ok;\n\tu8 fw_ok = _FALSE;\n\tint err, err_ret = -1;\n\n\n\tadapter = dvobj_get_primary_adapter(d);\n\thalmac = dvobj_to_halmac(d);\n\tif (!halmac)\n\t\tgoto out;\n\tapi = HALMAC_GET_API(halmac);\n\n\t/* StatePowerOff */\n\n\t/* SKIP: halmac_init_adapter (Already done before) */\n\n\t/* halmac_pre_Init_system_cfg */\n\t/* halmac_mac_power_switch(on) */\n\t/* halmac_Init_system_cfg */\n\tok = rtw_hal_power_on(adapter);\n\tif (_FAIL == ok)\n\t\tgoto out;\n\n\t/* StatePowerOn */\n\n\t/* DownloadFW */\n\tif (fw && fwsize) {\n\t\terr = download_fw(d, fw, fwsize, 0);\n\t\tif (err)\n\t\t\tgoto out;\n\t\tfw_ok = _TRUE;\n\t}\n\n\t/* InitMACFlow */\n\terr = init_mac_flow(d);\n\tif (err)\n\t\tgoto out;\n\n\t/* Driver insert flow: Enable TR/RX */\n\terr = _drv_enable_trx(d);\n\tif (err)\n\t\tgoto out;\n\n\t/* halmac_send_general_info */\n\tif (_TRUE == fw_ok) {\n\t\terr = _send_general_info(d);\n\t\tif (err)\n\t\t\tgoto out;\n\t}\n\n\t/* Init Phy parameter-MAC */\n\tok = rtw_hal_init_mac_register(adapter);\n\tif (_FALSE == ok)\n\t\tgoto out;\n\n\t/* StateMacInitialized */\n\n\t/* halmac_cfg_drv_info */\n\terr = rtw_halmac_config_rx_info(d, HALMAC_DRV_INFO_PHY_STATUS);\n\tif (err)\n\t\tgoto out;\n\n\t/* halmac_set_hw_value(HALMAC_HW_EN_BB_RF) */\n\t/* Init BB, RF */\n\tok = rtw_hal_init_phy(adapter);\n\tif (_FALSE == ok)\n\t\tgoto out;\n\n\tstatus = api->halmac_init_interface_cfg(halmac);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n\t/* SKIP: halmac_verify_platform_api */\n\t/* SKIP: halmac_h2c_lb */\n\n\t/* StateRxIdle */\n\n\terr_ret = 0;\nout:\n\treturn err_ret;\n}\n\nint rtw_halmac_init_hal(struct dvobj_priv *d)\n{\n\treturn _halmac_init_hal(d, NULL, 0);\n}\n\n/*\n * Notices:\n *\tMake sure\n *\t1. rtw_hal_get_hwreg(HW_VAR_RF_TYPE)\n *\t2. HAL_DATA_TYPE.rfe_type\n *\talready ready for use before calling this function.\n */\nint rtw_halmac_init_hal_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize)\n{\n\treturn _halmac_init_hal(d, fw, fwsize);\n}\n\n/*\n * Notices:\n *\tMake sure\n *\t1. rtw_hal_get_hwreg(HW_VAR_RF_TYPE)\n *\t2. HAL_DATA_TYPE.rfe_type\n *\talready ready for use before calling this function.\n */\nint rtw_halmac_init_hal_fw_file(struct dvobj_priv *d, u8 *fwpath)\n{\n\tu8 *fw = NULL;\n\tu32 fwmaxsize = 0, size = 0;\n\tint err = 0;\n\n\n\terr = rtw_halmac_get_fw_max_size(d, &fwmaxsize);\n\tif (err) {\n\t\tRTW_ERR(\"%s: Fail to get Firmware MAX size(err=%d)\\n\", __FUNCTION__, err);\n\t\treturn -1;\n\t}\n\n\tfw = rtw_zmalloc(fwmaxsize);\n\tif (!fw)\n\t\treturn -1;\n\n\tsize = rtw_retrieve_from_file(fwpath, fw, fwmaxsize);\n\tif (!size) {\n\t\terr = -1;\n\t\tgoto exit;\n\t}\n\n\terr = _halmac_init_hal(d, fw, size);\n\nexit:\n\trtw_mfree(fw, fwmaxsize);\n\t/*fw = NULL;*/\n\n\treturn err;\n}\n\nint rtw_halmac_deinit_hal(struct dvobj_priv *d)\n{\n\tPADAPTER adapter;\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tint err = -1;\n\n\n\tadapter = dvobj_get_primary_adapter(d);\n\thalmac = dvobj_to_halmac(d);\n\tif (!halmac)\n\t\tgoto out;\n\tapi = HALMAC_GET_API(halmac);\n\n\tstatus = api->halmac_deinit_interface_cfg(halmac);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n\trtw_hal_power_off(adapter);\n\n\terr = 0;\nout:\n\treturn err;\n}\n\nint rtw_halmac_self_verify(struct dvobj_priv *d)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tint err = -1;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_verify_platform_api(mac);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n\tstatus = api->halmac_h2c_lb(mac);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto out;\n\n\terr = 0;\nout:\n\treturn err;\n}\n\nstatic u8 rtw_halmac_txfifo_is_empty(struct dvobj_priv *d)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 chk_num = 10;\n\tu8 rst = _FALSE;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_txfifo_is_empty(mac, chk_num);\n\tif (status == HALMAC_RET_SUCCESS)\n\t\trst = _TRUE;\n\n\treturn rst;\n}\n\n/**\n * rtw_halmac_txfifo_wait_empty() - Wait TX FIFO to be emtpy\n * @d:\t\tstruct dvobj_priv*\n * @timeout:\ttime limit of wait, unit is ms\n *\t\t0 for no limit\n *\n * Wait TX FIFO to be emtpy.\n *\n * Rteurn 0 for TX FIFO is empty, otherwise not empty.\n */\nint rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout)\n{\n\tstruct _ADAPTER *a;\n\tu8 empty = _FALSE;\n\tu32 cnt = 0;\n\tsystime start_time = 0;\n\tu32 pass_time; /* ms */\n\n\n\ta = dvobj_get_primary_adapter(d);\n\tstart_time = rtw_get_current_time();\n\n\tdo {\n\t\tcnt++;\n\t\tempty = rtw_halmac_txfifo_is_empty(d);\n\t\tif (empty == _TRUE)\n\t\t\tbreak;\n\n\t\tif (timeout) {\n\t\t\tpass_time = rtw_get_passing_time_ms(start_time);\n\t\t\tif (pass_time > timeout)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (RTW_CANNOT_IO(a)) {\n\t\t\tRTW_WARN(\"%s: Interrupted by I/O forbiden!\\n\", __FUNCTION__);\n\t\t\tbreak;\n\t\t}\n\n\t\trtw_msleep_os(2);\n\t} while (1);\n\n\tif (empty == _FALSE) {\n#ifdef CONFIG_RTW_DEBUG\n\t\tu16 dbg_reg[] = {0x210, 0x230, 0x234, 0x238, 0x23C, 0x240,\n\t\t\t\t 0x418, 0x10FC, 0x10F8, 0x11F4, 0x11F8};\n\t\tu8 i;\n\t\tu32 val;\n\n\t\tif (!RTW_CANNOT_IO(a)) {\n\t\t\tfor (i = 0; i < ARRAY_SIZE(dbg_reg); i++) {\n\t\t\t\tval = rtw_read32(a, dbg_reg[i]);\n\t\t\t\tRTW_ERR(\"REG_%X:0x%08x\\n\", dbg_reg[i], val);\n\t\t\t}\n\t\t}\n#endif /* CONFIG_RTW_DEBUG */\n\n\t\tRTW_ERR(\"%s: Fail to wait txfifo empty!(cnt=%d)\\n\",\n\t\t\t__FUNCTION__, cnt);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic enum halmac_dlfw_mem _fw_mem_drv2halmac(enum fw_mem mem, u8 tx_stop)\n{\n\tenum halmac_dlfw_mem mem_halmac = HALMAC_DLFW_MEM_UNDEFINE;\n\n\n\tswitch (mem) {\n\tcase FW_EMEM:\n\t\tif (tx_stop == _FALSE)\n\t\t\tmem_halmac = HALMAC_DLFW_MEM_EMEM_RSVD_PG;\n\t\telse\n\t\t\tmem_halmac = HALMAC_DLFW_MEM_EMEM;\n\t\tbreak;\n\n\tcase FW_IMEM:\n\tcase FW_DMEM:\n\t\tmem_halmac = HALMAC_DLFW_MEM_UNDEFINE;\n\t\tbreak;\n\t}\n\n\treturn mem_halmac;\n}\n\nint rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tenum halmac_dlfw_mem dlfw_mem;\n\tu8 tx_stop = _FALSE;\n\tu32 chk_timeout = 2000; /* unit: ms */\n\tint err = 0;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tif ((!fw) || (!fwsize))\n\t\treturn -1;\n\n#ifndef RTW_HALMAC_DLFW_MEM_NO_STOP_TX\n\t/* 1. Driver Stop Tx */\n\t/* ToDo */\n\n\t/* 2. Driver Check Tx FIFO is empty */\n\terr = rtw_halmac_txfifo_wait_empty(d, chk_timeout);\n\tif (err)\n\t\ttx_stop = _FALSE;\n\telse\n\t\ttx_stop = _TRUE;\n#endif /* !RTW_HALMAC_DLFW_MEM_NO_STOP_TX */\n\n\t/* 3. Download Firmware MEM */\n\tdlfw_mem = _fw_mem_drv2halmac(mem, tx_stop);\n\tif (dlfw_mem == HALMAC_DLFW_MEM_UNDEFINE) {\n\t\terr = -1;\n\t\tgoto resume_tx;\n\t}\n\tstatus = api->halmac_free_download_firmware(mac, dlfw_mem, fw, fwsize);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tRTW_ERR(\"%s: halmac_free_download_firmware fail(err=0x%x)\\n\",\n\t\t\t__FUNCTION__, status);\n\t\terr = -1;\n\t\tgoto resume_tx;\n\t}\n\nresume_tx:\n#ifndef RTW_HALMAC_DLFW_MEM_NO_STOP_TX\n\t/* 4. Driver resume TX if needed */\n\t/* ToDo */\n#endif /* !RTW_HALMAC_DLFW_MEM_NO_STOP_TX */\n\n\treturn err;\n}\n\nint rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem)\n{\n\tu8 *fw = NULL;\n\tu32 fwmaxsize = 0, size = 0;\n\tint err = 0;\n\n\n\terr = rtw_halmac_get_fw_max_size(d, &fwmaxsize);\n\tif (err) {\n\t\tRTW_ERR(\"%s: Fail to get Firmware MAX size(err=%d)\\n\", __FUNCTION__, err);\n\t\treturn -1;\n\t}\n\n\tfw = rtw_zmalloc(fwmaxsize);\n\tif (!fw)\n\t\treturn -1;\n\n\tsize = rtw_retrieve_from_file(fwpath, fw, fwmaxsize);\n\tif (size)\n\t\terr = rtw_halmac_dlfw_mem(d, fw, size, mem);\n\telse\n\t\terr = -1;\n\n\trtw_mfree(fw, fwmaxsize);\n\t/*fw = NULL;*/\n\n\treturn err;\n}\n\n/*\n * Return:\n *\t0\tSuccess\n *\t-22\tInvalid arguemnt\n */\nint rtw_halmac_dlfw(struct dvobj_priv *d, u8 *fw, u32 fwsize)\n{\n\tPADAPTER adapter;\n\tenum halmac_ret_status status;\n\tu32 ok;\n\tint err, err_ret = -1;\n\n\n\tif (!fw || !fwsize)\n\t\treturn -22;\n\n\tadapter = dvobj_get_primary_adapter(d);\n\n\t/* re-download firmware */\n\tif (rtw_is_hw_init_completed(adapter))\n\t\treturn download_fw(d, fw, fwsize, 1);\n\n\t/* Download firmware before hal init */\n\t/* Power on, download firmware and init mac */\n\tok = rtw_hal_power_on(adapter);\n\tif (_FAIL == ok)\n\t\tgoto out;\n\n\terr = download_fw(d, fw, fwsize, 0);\n\tif (err) {\n\t\terr_ret = err;\n\t\tgoto out;\n\t}\n\n\terr = init_mac_flow(d);\n\tif (err)\n\t\tgoto out;\n\n\terr = _send_general_info(d);\n\tif (err)\n\t\tgoto out;\n\n\terr_ret = 0;\n\nout:\n\treturn err_ret;\n}\n\nint rtw_halmac_dlfw_from_file(struct dvobj_priv *d, u8 *fwpath)\n{\n\tu8 *fw = NULL;\n\tu32 fwmaxsize = 0, size = 0;\n\tint err = 0;\n\n\n\terr = rtw_halmac_get_fw_max_size(d, &fwmaxsize);\n\tif (err) {\n\t\tRTW_ERR(\"%s: Fail to get Firmware MAX size(err=%d)\\n\", __FUNCTION__, err);\n\t\treturn -1;\n\t}\n\n\tfw = rtw_zmalloc(fwmaxsize);\n\tif (!fw)\n\t\treturn -1;\n\n\tsize = rtw_retrieve_from_file(fwpath, fw, fwmaxsize);\n\tif (size)\n\t\terr = rtw_halmac_dlfw(d, fw, size);\n\telse\n\t\terr = -1;\n\n\trtw_mfree(fw, fwmaxsize);\n\t/*fw = NULL;*/\n\n\treturn err;\n}\n\n/*\n * Description:\n *\tPower on/off BB/RF domain.\n *\n * Parameters:\n *\tenable\t_TRUE/_FALSE for power on/off\n *\n * Return:\n *\t0\tSuccess\n *\tothers\tFail\n */\nint rtw_halmac_phy_power_switch(struct dvobj_priv *d, u8 enable)\n{\n\tPADAPTER adapter;\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu8 on;\n\n\n\tadapter = dvobj_get_primary_adapter(d);\n\thalmac = dvobj_to_halmac(d);\n\tif (!halmac)\n\t\treturn -1;\n\tapi = HALMAC_GET_API(halmac);\n\ton = (enable == _TRUE) ? 1 : 0;\n\n\tstatus = api->halmac_set_hw_value(halmac, HALMAC_HW_EN_BB_RF, &on);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic u8 _is_fw_read_cmd_down(PADAPTER adapter, u8 msgbox_num)\n{\n\tu8 read_down = _FALSE;\n\tint retry_cnts = 100;\n\tu8 valid;\n\n\tdo {\n\t\tvalid = rtw_read8(adapter, REG_HMETFR) & BIT(msgbox_num);\n\t\tif (0 == valid)\n\t\t\tread_down = _TRUE;\n\t\telse\n\t\t\trtw_msleep_os(1);\n\t} while ((!read_down) && (retry_cnts--));\n\n\tif (_FALSE == read_down)\n\t\tRTW_WARN(\"%s, reg_1cc(%x), msg_box(%d)...\\n\", __func__, rtw_read8(adapter, REG_HMETFR), msgbox_num);\n\n\treturn read_down;\n}\n\n/**\n * rtw_halmac_send_h2c() - Send H2C to firmware\n * @d:\t\tstruct dvobj_priv*\n * @h2c:\tH2C data buffer, suppose to be 8 bytes\n *\n * Send H2C to firmware by message box register(0x1D0~0x1D3 & 0x1F0~0x1F3).\n *\n * Assume firmware be ready to accept H2C here, please check\n * (hal->bFWReady == _TRUE) before call this function or make sure firmware is\n * ready.\n *\n * Return: 0 if process OK, otherwise fail to send this H2C.\n */\nint rtw_halmac_send_h2c(struct dvobj_priv *d, u8 *h2c)\n{\n\tPADAPTER adapter = dvobj_get_primary_adapter(d);\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tu8 h2c_box_num = 0;\n\tu32 msgbox_addr = 0;\n\tu32 msgbox_ex_addr = 0;\n\tu32 h2c_cmd = 0;\n\tu32 h2c_cmd_ex = 0;\n\tint err = -1;\n\n\n\tif (!h2c) {\n\t\tRTW_WARN(\"%s: pbuf is NULL\\n\", __FUNCTION__);\n\t\treturn err;\n\t}\n\n\tif (rtw_is_surprise_removed(adapter)) {\n\t\tRTW_WARN(\"%s: surprise removed\\n\", __FUNCTION__);\n\t\treturn err;\n\t}\n\n\t_enter_critical_mutex(&d->h2c_fwcmd_mutex, NULL);\n\n\t/* pay attention to if race condition happened in H2C cmd setting */\n\th2c_box_num = hal->LastHMEBoxNum;\n\n\tif (!_is_fw_read_cmd_down(adapter, h2c_box_num)) {\n\t\tRTW_WARN(\" fw read cmd failed...\\n\");\n#ifdef DBG_CONFIG_ERROR_DETECT\n\t\thal->srestpriv.self_dect_fw = _TRUE;\n\t\thal->srestpriv.self_dect_fw_cnt++;\n#endif /* DBG_CONFIG_ERROR_DETECT */\n\t\tgoto exit;\n\t}\n\n\t/* Write Ext command (byte 4~7) */\n\tmsgbox_ex_addr = REG_HMEBOX_E0 + (h2c_box_num * EX_MESSAGE_BOX_SIZE);\n\t_rtw_memcpy((u8 *)(&h2c_cmd_ex), h2c + 4, EX_MESSAGE_BOX_SIZE);\n\th2c_cmd_ex = le32_to_cpu(h2c_cmd_ex);\n\trtw_write32(adapter, msgbox_ex_addr, h2c_cmd_ex);\n\n\t/* Write command (byte 0~3) */\n\tmsgbox_addr = REG_HMEBOX0 + (h2c_box_num * MESSAGE_BOX_SIZE);\n\t_rtw_memcpy((u8 *)(&h2c_cmd), h2c, 4);\n\th2c_cmd = le32_to_cpu(h2c_cmd);\n\trtw_write32(adapter, msgbox_addr, h2c_cmd);\n\n\t/* update last msg box number */\n\thal->LastHMEBoxNum = (h2c_box_num + 1) % MAX_H2C_BOX_NUMS;\n\terr = 0;\n\n#ifdef DBG_H2C_CONTENT\n\tRTW_INFO_DUMP(\"[H2C] - \", h2c, RTW_HALMAC_H2C_MAX_SIZE);\n#endif\nexit:\n\t_exit_critical_mutex(&d->h2c_fwcmd_mutex, NULL);\n\treturn err;\n}\n\n/**\n * rtw_halmac_c2h_handle() - Handle C2H for HALMAC\n * @d:\t\tstruct dvobj_priv*\n * @c2h:\tFull C2H packet, including RX description and payload\n * @size:\tSize(byte) of c2h\n *\n * Send C2H packet to HALMAC to process C2H packets, and the expected C2H ID is\n * 0xFF. This function won't have any I/O, so caller doesn't have to call it in\n * I/O safe place(ex. command thread).\n *\n * Please sure doesn't call this function in the same thread as someone is\n * waiting HALMAC C2H ack, otherwise there is a deadlock happen.\n *\n * Return: 0 if process OK, otherwise no action for this C2H.\n */\nint rtw_halmac_c2h_handle(struct dvobj_priv *d, u8 *c2h, u32 size)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_get_c2h_info(mac, c2h, size);\n\tif (HALMAC_RET_SUCCESS != status)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nint rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 val;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_get_efuse_available_size(mac, &val);\n\tif (HALMAC_RET_SUCCESS != status)\n\t\treturn -1;\n\n\t*size = val;\n\treturn 0;\n}\n\nint rtw_halmac_get_physical_efuse_size(struct dvobj_priv *d, u32 *size)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 val;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_get_efuse_size(mac, &val);\n\tif (HALMAC_RET_SUCCESS != status)\n\t\treturn -1;\n\n\t*size = val;\n\treturn 0;\n}\n\nint rtw_halmac_read_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tenum halmac_feature_id id;\n\tint ret;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\tid = HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE;\n\n\tret = init_halmac_event(d, id, map, size);\n\tif (ret)\n\t\treturn -1;\n\n\tstatus = api->halmac_dump_efuse_map(mac, HALMAC_EFUSE_R_DRV);\n\tif (HALMAC_RET_SUCCESS != status) {\n\t\tfree_halmac_event(d, id);\n\t\treturn -1;\n\t}\n\n\tret = wait_halmac_event(d, id);\n\tif (ret)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nint rtw_halmac_read_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu8 v;\n\tu32 i;\n\tu8 *efuse = NULL;\n\tu32 size = 0;\n\tint err = 0;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tif (api->halmac_read_efuse) {\n\t\tfor (i = 0; i < cnt; i++) {\n\t\t\tstatus = api->halmac_read_efuse(mac, offset + i, &v);\n\t\t\tif (HALMAC_RET_SUCCESS != status)\n\t\t\t\treturn -1;\n\t\t\tdata[i] = v;\n\t\t}\n\t} else {\n\t\terr = rtw_halmac_get_physical_efuse_size(d, &size);\n\t\tif (err)\n\t\t\treturn -1;\n\n\t\tefuse = rtw_zmalloc(size);\n\t\tif (!efuse)\n\t\t\treturn -1;\n\n\t\terr = rtw_halmac_read_physical_efuse_map(d, efuse, size);\n\t\tif (err)\n\t\t\terr = -1;\n\t\telse\n\t\t\t_rtw_memcpy(data, efuse + offset, cnt);\n\n\t\trtw_mfree(efuse, size);\n\t}\n\n\treturn err;\n}\n\nint rtw_halmac_write_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 i;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tif (api->halmac_write_efuse == NULL)\n\t\treturn -1;\n\n\tfor (i = 0; i < cnt; i++) {\n\t\tstatus = api->halmac_write_efuse(mac, offset + i, data[i]);\n\t\tif (HALMAC_RET_SUCCESS != status)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nint rtw_halmac_get_logical_efuse_size(struct dvobj_priv *d, u32 *size)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 val;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_get_logical_efuse_size(mac, &val);\n\tif (HALMAC_RET_SUCCESS != status)\n\t\treturn -1;\n\n\t*size = val;\n\treturn 0;\n}\n\nint rtw_halmac_read_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, u8 *maskmap, u32 masksize)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tenum halmac_feature_id id;\n\tint ret;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\tid = HALMAC_FEATURE_DUMP_LOGICAL_EFUSE;\n\n\tret = init_halmac_event(d, id, map, size);\n\tif (ret)\n\t\treturn -1;\n\n\tstatus = api->halmac_dump_logical_efuse_map(mac, HALMAC_EFUSE_R_DRV);\n\tif (HALMAC_RET_SUCCESS != status) {\n\t\tfree_halmac_event(d, id);\n\t\treturn -1;\n\t}\n\n\tret = wait_halmac_event(d, id);\n\tif (ret)\n\t\treturn -1;\n\n\tif (maskmap && masksize) {\n\t\tstruct halmac_pg_efuse_info pginfo;\n\n\t\tpginfo.efuse_map = map;\n\t\tpginfo.efuse_map_size = size;\n\t\tpginfo.efuse_mask = maskmap;\n\t\tpginfo.efuse_mask_size = masksize;\n\n\t\tstatus = api->halmac_mask_logical_efuse(mac, &pginfo);\n\t\tif (status != HALMAC_RET_SUCCESS)\n\t\t\tRTW_WARN(\"%s: mask logical efuse FAIL!\\n\", __FUNCTION__);\n\t}\n\n\treturn 0;\n}\n\nint rtw_halmac_write_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, u8 *maskmap, u32 masksize)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tstruct halmac_pg_efuse_info pginfo;\n\tenum halmac_ret_status status;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tpginfo.efuse_map = map;\n\tpginfo.efuse_map_size = size;\n\tpginfo.efuse_mask = maskmap;\n\tpginfo.efuse_mask_size = masksize;\n\n\tstatus = api->halmac_pg_efuse_by_map(mac, &pginfo, HALMAC_EFUSE_R_AUTO);\n\tif (HALMAC_RET_SUCCESS != status)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nint rtw_halmac_read_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu8 v;\n\tu32 i;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tfor (i = 0; i < cnt; i++) {\n\t\tstatus = api->halmac_read_logical_efuse(mac, offset + i, &v);\n\t\tif (HALMAC_RET_SUCCESS != status)\n\t\t\treturn -1;\n\t\tdata[i] = v;\n\t}\n\n\treturn 0;\n}\n\nint rtw_halmac_write_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 i;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tfor (i = 0; i < cnt; i++) {\n\t\tstatus = api->halmac_write_logical_efuse(mac, offset + i, data[i]);\n\t\tif (HALMAC_RET_SUCCESS != status)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nint rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 i;\n\tu8 bank = 1;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tfor (i = 0; i < cnt; i++) {\n\t\tstatus = api->halmac_write_efuse_bt(mac, offset + i, data[i], bank);\n\t\tif (HALMAC_RET_SUCCESS != status) {\n\t\t\tprintk(\"%s: halmac_write_efuse_bt status = %d\\n\", __FUNCTION__, status);\n\t\t\treturn -1;\n\t\t}\n\t}\n\tprintk(\"%s: halmac_write_efuse_bt status = HALMAC_RET_SUCCESS %d\\n\", __FUNCTION__, status);\n\treturn 0;\n}\n\n\nint rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tint bank = 1;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_dump_efuse_map_bt(mac, bank, size, map);\n\tif (HALMAC_RET_SUCCESS != status) {\n\t\tprintk(\"%s: halmac_dump_efuse_map_bt fail!\\n\", __FUNCTION__);\n\t\treturn -1;\n\t}\n\n\tprintk(\"%s: OK!\\n\", __FUNCTION__);\n\n\treturn 0;\n}\n\nstatic enum hal_fifo_sel _fifo_sel_drv2halmac(u8 fifo_sel)\n{\n\tswitch (fifo_sel) {\n\tcase 0:\n\t\treturn HAL_FIFO_SEL_TX;\n\tcase 1:\n\t\treturn HAL_FIFO_SEL_RX;\n\tcase 2:\n\t\treturn HAL_FIFO_SEL_RSVD_PAGE;\n\tcase 3:\n\t\treturn HAL_FIFO_SEL_REPORT;\n\tcase 4:\n\t\treturn HAL_FIFO_SEL_LLT;\n\tcase 5:\n\t\treturn HAL_FIFO_SEL_RXBUF_FW;\n\t}\n\n\treturn HAL_FIFO_SEL_RSVD_PAGE;\n}\n\n/*#define CONFIG_HALMAC_FIFO_DUMP*/\nint rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum hal_fifo_sel halmac_fifo_sel;\n\tenum halmac_ret_status status;\n\tu8 *pfifo_map = NULL;\n\tu32 fifo_size = 0;\n\ts8 ret = 0;/* 0:success, -1:error */\n\tu8 mem_created = _FALSE;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tif ((size != 0) && (buffer == NULL))\n\t\treturn -1;\n\n\thalmac_fifo_sel = _fifo_sel_drv2halmac(fifo_sel);\n\n\tif ((size) && (buffer)) {\n\t\tpfifo_map = buffer;\n\t\tfifo_size = size;\n\t} else {\n\t\tfifo_size = api->halmac_get_fifo_size(mac, halmac_fifo_sel);\n\n\t\tif (fifo_size)\n\t\t\tpfifo_map = rtw_zvmalloc(fifo_size);\n\t\tif (pfifo_map == NULL)\n\t\t\treturn -1;\n\t\tmem_created = _TRUE;\n\t}\n\n\tstatus = api->halmac_dump_fifo(mac, halmac_fifo_sel, addr, fifo_size, pfifo_map);\n\tif (HALMAC_RET_SUCCESS != status) {\n\t\tret = -1;\n\t\tgoto _exit;\n\t}\n\n#ifdef CONFIG_HALMAC_FIFO_DUMP\n\t{\n\t\tstatic const char * const fifo_sel_str[] = {\n\t\t\t\"TX\", \"RX\", \"RSVD_PAGE\", \"REPORT\", \"LLT\", \"RXBUF_FW\"\n\t\t};\n\n\t\tRTW_INFO(\"%s FIFO DUMP [start_addr:0x%04x , size:%d]\\n\", fifo_sel_str[halmac_fifo_sel], addr, fifo_size);\n\t\tRTW_INFO_DUMP(\"\\n\", pfifo_map, fifo_size);\n\t\tRTW_INFO(\" ==================================================\\n\");\n\t}\n#endif /* CONFIG_HALMAC_FIFO_DUMP */\n\n_exit:\n\tif ((mem_created == _TRUE) && pfifo_map)\n\t\trtw_vmfree(pfifo_map, fifo_size);\n\n\treturn ret;\n}\n\n/*\n * rtw_halmac_rx_agg_switch() - Switch RX aggregation function and setting\n * @d\t\tstruct dvobj_priv *\n * @enable\t_FALSE/_TRUE for disable/enable RX aggregation function\n *\n * This function could help to on/off bus RX aggregation function, and is only\n * useful for SDIO and USB interface. Although only \"enable\" flag is brough in,\n * some setting would be taken from other places, and they are from:\n * [DMA aggregation]\n *\tstruct hal_com_data.rxagg_dma_size\n *\tstruct hal_com_data.rxagg_dma_timeout\n * [USB aggregation] (only use for USB interface)\n *\tstruct hal_com_data.rxagg_usb_size\n *\tstruct hal_com_data.rxagg_usb_timeout\n * If above values of size and timeout are both 0 means driver would not\n * control the threshold setting and leave it to HALMAC handle.\n *\n * From HALMAC V1_04_04, driver force the size threshold be hard limit, and the\n * rx size can not exceed the setting.\n *\n * Return 0 for success, otherwise fail.\n */\nint rtw_halmac_rx_agg_switch(struct dvobj_priv *d, u8 enable)\n{\n\tstruct _ADAPTER *adapter;\n\tstruct hal_com_data *hal;\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tstruct halmac_rxagg_cfg rxaggcfg;\n\tenum halmac_ret_status status;\n\n\n\tadapter = dvobj_get_primary_adapter(d);\n\thal = GET_HAL_DATA(adapter);\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\t_rtw_memset((void *)&rxaggcfg, 0, sizeof(rxaggcfg));\n\trxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE;\n\t/*\n\t * Always enable size limit to avoid rx size exceed\n\t * driver defined size.\n\t */\n\trxaggcfg.threshold.size_limit_en = 1;\n\n#ifdef RTW_RX_AGGREGATION\n\tif (_TRUE == enable) {\n#ifdef CONFIG_SDIO_HCI\n\t\trxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA;\n\t\trxaggcfg.threshold.drv_define = 0;\n\t\tif (hal->rxagg_dma_size || hal->rxagg_dma_timeout) {\n\t\t\trxaggcfg.threshold.drv_define = 1;\n\t\t\trxaggcfg.threshold.timeout = hal->rxagg_dma_timeout;\n\t\t\trxaggcfg.threshold.size = hal->rxagg_dma_size;\n\t\t\tRTW_INFO(\"%s: RX aggregation threshold: \"\n\t\t\t\t \"timeout=%u size=%u\\n\",\n\t\t\t\t __FUNCTION__,\n\t\t\t\t hal->rxagg_dma_timeout,\n\t\t\t\t hal->rxagg_dma_size);\n\t\t}\n#elif defined(CONFIG_USB_HCI)\n\t\tswitch (hal->rxagg_mode) {\n\t\tcase RX_AGG_DISABLE:\n\t\t\trxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE;\n\t\t\tbreak;\n\n\t\tcase RX_AGG_DMA:\n\t\t\trxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA;\n\t\t\tif (hal->rxagg_dma_size || hal->rxagg_dma_timeout) {\n\t\t\t\trxaggcfg.threshold.drv_define = 1;\n\t\t\t\trxaggcfg.threshold.timeout = hal->rxagg_dma_timeout;\n\t\t\t\trxaggcfg.threshold.size = hal->rxagg_dma_size;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase RX_AGG_USB:\n\t\tcase RX_AGG_MIX:\n\t\t\trxaggcfg.mode = HALMAC_RX_AGG_MODE_USB;\n\t\t\tif (hal->rxagg_usb_size || hal->rxagg_usb_timeout) {\n\t\t\t\trxaggcfg.threshold.drv_define = 1;\n\t\t\t\trxaggcfg.threshold.timeout = hal->rxagg_usb_timeout;\n\t\t\t\trxaggcfg.threshold.size = hal->rxagg_usb_size;\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n#endif /* CONFIG_USB_HCI */\n\t}\n#endif /* RTW_RX_AGGREGATION */\n\n\tstatus = api->halmac_cfg_rx_aggregation(halmac, &rxaggcfg);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nint rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tstruct halmac_adapter *halmac = dvobj_to_halmac(dvobj);\n\tstruct halmac_api *api = HALMAC_GET_API(halmac);\n\n\tstatus = api->halmac_dl_drv_rsvd_page(halmac, pg_offset, pbuf, size);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/*\n * Description\n *\tFill following spec info from HALMAC API:\n *\tsec_cam_ent_num\n *\n * Return\n *\t0\tSuccess\n *\tothers\tFail\n */\nint rtw_halmac_fill_hal_spec(struct dvobj_priv *dvobj, struct hal_spec_t *spec)\n{\n\tenum halmac_ret_status status;\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tu8 cam = 0;\t/* Security Cam Entry Number */\n\n\n\thalmac = dvobj_to_halmac(dvobj);\n\tapi = HALMAC_GET_API(halmac);\n\n\t/* Prepare data from HALMAC */\n\tstatus = api->halmac_get_hw_value(halmac, HALMAC_HW_CAM_ENTRY_NUM, &cam);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\t/* Fill data to hal_spec_t */\n\tspec->sec_cam_ent_num = cam;\n\n\treturn 0;\n}\n\nint rtw_halmac_p2pps(struct dvobj_priv *dvobj, struct hal_p2p_ps_para *pp2p_ps_para)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tstruct halmac_adapter *halmac = dvobj_to_halmac(dvobj);\n\tstruct halmac_api *api = HALMAC_GET_API(halmac);\n\tstruct halmac_p2pps halmac_p2p_ps;\n\n\t(&halmac_p2p_ps)->offload_en = pp2p_ps_para->offload_en;\n\t(&halmac_p2p_ps)->role = pp2p_ps_para->role;\n\t(&halmac_p2p_ps)->ctwindow_en = pp2p_ps_para->ctwindow_en;\n\t(&halmac_p2p_ps)->noa_en = pp2p_ps_para->noa_en;\n\t(&halmac_p2p_ps)->noa_sel = pp2p_ps_para->noa_sel;\n\t(&halmac_p2p_ps)->all_sta_sleep = pp2p_ps_para->all_sta_sleep;\n\t(&halmac_p2p_ps)->discovery = pp2p_ps_para->discovery;\n\t(&halmac_p2p_ps)->disable_close_rf = pp2p_ps_para->disable_close_rf;\n\t(&halmac_p2p_ps)->p2p_port_id = _hw_port_drv2halmac(pp2p_ps_para->p2p_port_id);\n\t(&halmac_p2p_ps)->p2p_group = pp2p_ps_para->p2p_group;\n\t(&halmac_p2p_ps)->p2p_macid = pp2p_ps_para->p2p_macid;\n\t(&halmac_p2p_ps)->ctwindow_length = pp2p_ps_para->ctwindow_length;\n\t(&halmac_p2p_ps)->noa_duration_para = pp2p_ps_para->noa_duration_para;\n\t(&halmac_p2p_ps)->noa_interval_para = pp2p_ps_para->noa_interval_para;\n\t(&halmac_p2p_ps)->noa_start_time_para = pp2p_ps_para->noa_start_time_para;\n\t(&halmac_p2p_ps)->noa_count_para = pp2p_ps_para->noa_count_para;\n\n\tstatus = api->halmac_p2pps(halmac, (&halmac_p2p_ps));\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\treturn 0;\n\n}\n\n/**\n * rtw_halmac_iqk() - Run IQ Calibration\n * @d:\t\tstruct dvobj_priv*\n * @clear:\tIQK parameters\n * @segment:\tIQK parameters\n *\n * Process IQ Calibration(IQK).\n *\n * Rteurn: 0 for OK, otherwise fail.\n */\nint rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tenum halmac_feature_id id;\n\tstruct halmac_iqk_para para;\n\tint ret;\n\tu8 retry = 3;\n\tu8 delay = 1; /* ms */\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\tid = HALMAC_FEATURE_IQK;\n\n\tret = init_halmac_event(d, id, NULL, 0);\n\tif (ret)\n\t\treturn -1;\n\n\tpara.clear = clear;\n\tpara.segment_iqk = segment;\n\n\tdo {\n\t\tstatus = api->halmac_start_iqk(mac, &para);\n\t\tif (status != HALMAC_RET_BUSY_STATE)\n\t\t\tbreak;\n\t\tRTW_WARN(\"%s: Fail to start IQK, status is BUSY! retry=%d\\n\", __FUNCTION__, retry);\n\t\tif (!retry)\n\t\t\tbreak;\n\t\tretry--;\n\t\trtw_msleep_os(delay);\n\t} while (1);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tfree_halmac_event(d, id);\n\t\treturn -1;\n\t}\n\n\tret = wait_halmac_event(d, id);\n\tif (ret)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic inline u32 _phy_parameter_val_drv2halmac(u32 val, u8 msk_en, u32 msk)\n{\n\tif (!msk_en)\n\t\treturn val;\n\n\treturn (val << bitshift(msk));\n}\n\nstatic int _phy_parameter_drv2halmac(struct rtw_phy_parameter *para, struct halmac_phy_parameter_info *info)\n{\n\tif (!para || !info)\n\t\treturn -1;\n\n\t_rtw_memset(info, 0, sizeof(*info));\n\n\tswitch (para->cmd) {\n\tcase 0:\n\t\t/* MAC register */\n\t\tswitch (para->data.mac.size) {\n\t\tcase 1:\n\t\t\tinfo->cmd_id = HALMAC_PARAMETER_CMD_MAC_W8;\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tinfo->cmd_id = HALMAC_PARAMETER_CMD_MAC_W16;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tinfo->cmd_id = HALMAC_PARAMETER_CMD_MAC_W32;\n\t\t\tbreak;\n\t\t}\n\t\tinfo->content.MAC_REG_W.value = _phy_parameter_val_drv2halmac(\n\t\t\t\t\t\t\tpara->data.mac.value,\n\t\t\t\t\t\t\tpara->data.mac.msk_en,\n\t\t\t\t\t\t\tpara->data.mac.msk);\n\t\tinfo->content.MAC_REG_W.msk = para->data.mac.msk;\n\t\tinfo->content.MAC_REG_W.offset = para->data.mac.offset;\n\t\tinfo->content.MAC_REG_W.msk_en = para->data.mac.msk_en;\n\t\tbreak;\n\n\tcase 1:\n\t\t/* BB register */\n\t\tswitch (para->data.bb.size) {\n\t\tcase 1:\n\t\t\tinfo->cmd_id = HALMAC_PARAMETER_CMD_BB_W8;\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tinfo->cmd_id = HALMAC_PARAMETER_CMD_BB_W16;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tinfo->cmd_id = HALMAC_PARAMETER_CMD_BB_W32;\n\t\t\tbreak;\n\t\t}\n\t\tinfo->content.BB_REG_W.value = _phy_parameter_val_drv2halmac(\n\t\t\t\t\t\t\tpara->data.bb.value,\n\t\t\t\t\t\t\tpara->data.bb.msk_en,\n\t\t\t\t\t\t\tpara->data.bb.msk);\n\t\tinfo->content.BB_REG_W.msk = para->data.bb.msk;\n\t\tinfo->content.BB_REG_W.offset = para->data.bb.offset;\n\t\tinfo->content.BB_REG_W.msk_en = para->data.bb.msk_en;\n\t\tbreak;\n\n\tcase 2:\n\t\t/* RF register */\n\t\tinfo->cmd_id = HALMAC_PARAMETER_CMD_RF_W;\n\t\tinfo->content.RF_REG_W.value = _phy_parameter_val_drv2halmac(\n\t\t\t\t\t\t\tpara->data.rf.value,\n\t\t\t\t\t\t\tpara->data.rf.msk_en,\n\t\t\t\t\t\t\tpara->data.rf.msk);\n\t\tinfo->content.RF_REG_W.msk = para->data.rf.msk;\n\t\tinfo->content.RF_REG_W.offset = para->data.rf.offset;\n\t\tinfo->content.RF_REG_W.msk_en = para->data.rf.msk_en;\n\t\tinfo->content.RF_REG_W.rf_path = para->data.rf.path;\n\t\tbreak;\n\n\tcase 3:\n\t\t/* Delay register */\n\t\tif (para->data.delay.unit == 0)\n\t\t\tinfo->cmd_id = HALMAC_PARAMETER_CMD_DELAY_US;\n\t\telse\n\t\t\tinfo->cmd_id = HALMAC_PARAMETER_CMD_DELAY_MS;\n\t\tinfo->content.DELAY_TIME.delay_time = para->data.delay.value;\n\t\tbreak;\n\n\tcase 0xFF:\n\t\t/* Latest(End) command */\n\t\tinfo->cmd_id = HALMAC_PARAMETER_CMD_END;\n\t\tbreak;\n\n\tdefault:\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/**\n * rtw_halmac_cfg_phy_para() - Register(Phy parameter) configuration\n * @d:\t\tstruct dvobj_priv*\n * @para:\tphy parameter\n *\n * Configure registers by firmware using H2C/C2H mechanism.\n * The latest command should be para->cmd==0xFF(End command) to finish all\n * processes.\n *\n * Return: 0 for OK, otherwise fail.\n */\nint rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tenum halmac_feature_id id;\n\tstruct halmac_phy_parameter_info info;\n\tu8 full_fifo;\n\tint err, ret;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\tid = HALMAC_FEATURE_CFG_PARA;\n\tfull_fifo = 1; /* ToDo: How to deciede? */\n\tret = 0;\n\n\terr = _phy_parameter_drv2halmac(para, &info);\n\tif (err)\n\t\treturn -1;\n\n\terr = init_halmac_event(d, id, NULL, 0);\n\tif (err)\n\t\treturn -1;\n\n\tstatus = api->halmac_cfg_parameter(mac, &info, full_fifo);\n\tif (info.cmd_id == HALMAC_PARAMETER_CMD_END) {\n\t\tif (status == HALMAC_RET_SUCCESS) {\n\t\t\terr = wait_halmac_event(d, id);\n\t\t\tif (err)\n\t\t\t\tret = -1;\n\t\t} else {\n\t\t\tfree_halmac_event(d, id);\n\t\t\tret = -1;\n\t\t\tRTW_ERR(\"%s: Fail to send END of cfg parameter, status is 0x%x!\\n\", __FUNCTION__, status);\n\t\t}\n\t} else {\n\t\tif (status == HALMAC_RET_PARA_SENDING) {\n\t\t\terr = wait_halmac_event(d, id);\n\t\t\tif (err)\n\t\t\t\tret = -1;\n\t\t} else {\n\t\t\tfree_halmac_event(d, id);\n\t\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\t\tret = -1;\n\t\t\t\tRTW_ERR(\"%s: Fail to cfg parameter, status is 0x%x!\\n\", __FUNCTION__, status);\n\t\t\t}\n\t\t}\n\t}\n\n\treturn ret;\n}\n\nstatic enum halmac_wlled_mode _led_mode_drv2halmac(u8 drv_mode)\n{\n\tenum halmac_wlled_mode halmac_mode;\n\n\n\tswitch (drv_mode) {\n\tcase 1:\n\t\thalmac_mode = HALMAC_WLLED_MODE_TX;\n\t\tbreak;\n\tcase 2:\n\t\thalmac_mode = HALMAC_WLLED_MODE_RX;\n\t\tbreak;\n\tcase 3:\n\t\thalmac_mode = HALMAC_WLLED_MODE_SW_CTRL;\n\t\tbreak;\n\tcase 0:\n\tdefault:\n\t\thalmac_mode = HALMAC_WLLED_MODE_TRX;\n\t\tbreak;\n\t}\n\n\treturn halmac_mode;\n}\n\n/**\n * rtw_halmac_led_cfg() - Configure Hardware LED Mode\n * @d:\t\tstruct dvobj_priv*\n * @enable:\tenable or disable LED function\n *\t\t0: disable\n *\t\t1: enable\n * @mode:\tWLan LED mode (valid when enable==1)\n *\t\t0: Blink when TX(transmit packet) and RX(receive packet)\n *\t\t1: Blink when TX only\n *\t\t2: Blink when RX only\n *\t\t3: Software control\n *\n * Configure hardware WLan LED mode.\n * If want to change LED mode after enabled, need to disable LED first and\n * enable again to set new mode.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_wlled_mode led_mode;\n\tenum halmac_ret_status status;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tif (enable) {\n\t\tstatus = api->halmac_pinmux_set_func(halmac,\n\t\t\t\t\t\t     HALMAC_GPIO_FUNC_WL_LED);\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\tRTW_ERR(\"%s: pinmux set fail!(0x%x)\\n\",\n\t\t\t\t__FUNCTION__, status);\n\t\t\treturn -1;\n\t\t}\n\n\t\tled_mode = _led_mode_drv2halmac(mode);\n\t\tstatus = api->halmac_pinmux_wl_led_mode(halmac, led_mode);\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\tRTW_ERR(\"%s: mode set fail!(0x%x)\\n\",\n\t\t\t\t__FUNCTION__, status);\n\t\t\treturn -1;\n\t\t}\n\t} else {\n\t\t/* Change LED to software control and turn off */\n\t\tapi->halmac_pinmux_wl_led_mode(halmac,\n\t\t\t\t\t       HALMAC_WLLED_MODE_SW_CTRL);\n\t\tapi->halmac_pinmux_wl_led_sw_ctrl(halmac, 0);\n\n\t\tstatus = api->halmac_pinmux_free_func(halmac,\n\t\t\t\t\t\t      HALMAC_GPIO_FUNC_WL_LED);\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\tRTW_ERR(\"%s: pinmux free fail!(0x%x)\\n\",\n\t\t\t\t__FUNCTION__, status);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/**\n * rtw_halmac_led_switch() - Turn Hardware LED on/off\n * @d:\t\tstruct dvobj_priv*\n * @on:\t\tLED light or not\n *\t\t0: Off\n *\t\t1: On(Light)\n *\n * Turn Hardware WLan LED On/Off.\n * Before use this function, user should call rtw_halmac_led_ctrl() to switch\n * mode to \"software control(3)\" first, otherwise control would fail.\n * The interval between on and off must be longer than 1 ms, or the LED would\n * keep light or dark only.\n * Ex. Turn off LED at first, turn on after 0.5ms and turn off again after\n * 0.5ms. The LED during this flow will only keep dark, and miss the turn on\n * operation between two turn off operations.\n */\nvoid rtw_halmac_led_switch(struct dvobj_priv *d, u8 on)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tapi->halmac_pinmux_wl_led_sw_ctrl(halmac, on);\n}\n\n/**\n * rtw_halmac_bt_wake_cfg() - Configure BT wake host function\n * @d:\t\tstruct dvobj_priv*\n * @enable:\tenable or disable BT wake host function\n *\t\t0: disable\n *\t\t1: enable\n *\n * Configure pinmux to allow BT to control BT wake host pin.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_bt_wake_cfg(struct dvobj_priv *d, u8 enable)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tif (enable) {\n\t\tstatus = api->halmac_pinmux_set_func(halmac,\n\t\t\t\t\t\tHALMAC_GPIO_FUNC_BT_HOST_WAKE1);\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\tRTW_ERR(\"%s: pinmux set BT_HOST_WAKE1 fail!(0x%x)\\n\",\n\t\t\t\t__FUNCTION__, status);\n\t\t\treturn -1;\n\t\t}\n\t} else {\n\t\tstatus = api->halmac_pinmux_free_func(halmac,\n\t\t\t\t\t\tHALMAC_GPIO_FUNC_BT_HOST_WAKE1);\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\tRTW_ERR(\"%s: pinmux free BT_HOST_WAKE1 fail!(0x%x)\\n\",\n\t\t\t\t__FUNCTION__, status);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n#ifdef CONFIG_PNO_SUPPORT\n/**\n * _halmac_scanoffload() - Switch channel by firmware during scanning\n * @d:\t\tstruct dvobj_priv*\n * @enable:\t1: enable, 0: disable\n * @nlo:\t1: nlo mode (no c2h event), 0: normal mode\n * @ssid:\tssid of probe request\n * @ssid_len:\tssid length\n *\n * Switch Channel and Send Porbe Request Offloaded by FW\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nstatic int _halmac_scanoffload(struct dvobj_priv *d, u32 enable, u8 nlo,\n\t\t\t       u8 *ssid, u8 ssid_len)\n{\n\tstruct _ADAPTER *adapter;\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tstruct halmac_ch_info ch_info;\n\tstruct halmac_ch_switch_option cs_option;\n\tstruct mlme_ext_priv *pmlmeext;\n\tenum halmac_feature_id id_update, id_ch_sw;\n\tstruct halmac_indicator *indicator, *tbl;\n\n\tint err = 0;\n\tu8 probereq[64];\n\tu32 len = 0;\n\tint i = 0;\n\tstruct pno_ssid pnossid;\n\tstruct rf_ctl_t *rfctl = NULL;\n\tstruct _RT_CHANNEL_INFO *ch_set;\n\n\n\ttbl = d->hmpriv.indicator;\n\tadapter = dvobj_get_primary_adapter(d);\n\tmac = dvobj_to_halmac(d);\n\tif (!mac)\n\t\treturn -1;\n\tapi = HALMAC_GET_API(mac);\n\tid_update = HALMAC_FEATURE_UPDATE_PACKET;\n\tid_ch_sw = HALMAC_FEATURE_CHANNEL_SWITCH;\n\tpmlmeext = &(adapter->mlmeextpriv);\n\trfctl = adapter_to_rfctl(adapter);\n\tch_set = rfctl->channel_set;\n\n\tRTW_INFO(\"%s: %s scanoffload, mode: %s\\n\",\n\t\t __FUNCTION__, enable?\"Enable\":\"Disable\",\n\t\t nlo?\"PNO/NLO\":\"Normal\");\n\n\tif (enable) {\n\t\t_rtw_memset(probereq, 0, sizeof(probereq));\n\n\t\t_rtw_memset(&pnossid, 0, sizeof(pnossid));\n\t\tif (ssid) {\n\t\t\tif (ssid_len > sizeof(pnossid.SSID)) {\n\t\t\t\tRTW_ERR(\"%s: SSID length(%d) is too long(>%d)!!\\n\",\n\t\t\t\t\t__FUNCTION__, ssid_len, sizeof(pnossid.SSID));\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\tpnossid.SSID_len = ssid_len;\n\t\t\t_rtw_memcpy(pnossid.SSID, ssid, ssid_len);\n\t\t}\n\n\t\trtw_hal_construct_ProbeReq(adapter, probereq, &len, &pnossid);\n\n\t\tif (!nlo) {\n\t\t\terr = init_halmac_event(d, id_update, NULL, 0);\n\t\t\tif (err)\n\t\t\t\treturn -1;\n\t\t}\n\n\t\tstatus = api->halmac_update_packet(mac, HALMAC_PACKET_PROBE_REQ,\n\t\t\t\t\t\t   probereq, len);\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\tif (!nlo)\n\t\t\t\tfree_halmac_event(d, id_update);\n\t\t\tRTW_ERR(\"%s: halmac_update_packet FAIL(%d)!!\\n\",\n\t\t\t\t__FUNCTION__, status);\n\t\t\treturn -1;\n\t\t}\n\n\t\tif (!nlo) {\n\t\t\terr = wait_halmac_event(d, id_update);\n\t\t\tif (err)\n\t\t\t\tRTW_ERR(\"%s: wait update packet FAIL(%d)!!\\n\",\n\t\t\t\t\t__FUNCTION__, err);\n\t\t}\n\n\t\tapi->halmac_clear_ch_info(mac);\n\n\t\tfor (i = 0; i < rfctl->max_chan_nums && ch_set[i].ChannelNum != 0; i++) {\n\t\t\t_rtw_memset(&ch_info, 0, sizeof(ch_info));\n\t\t\tch_info.extra_info = 0;\n\t\t\tch_info.channel = ch_set[i].ChannelNum;\n\t\t\tch_info.bw = HALMAC_BW_20;\n\t\t\tch_info.pri_ch_idx = HALMAC_CH_IDX_1;\n\t\t\tch_info.action_id = HALMAC_CS_ACTIVE_SCAN;\n\t\t\tch_info.timeout = 1;\n\t\t\tstatus = api->halmac_add_ch_info(mac, &ch_info);\n\t\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\t\tRTW_ERR(\"%s: add_ch_info FAIL(%d)!!\\n\",\n\t\t\t\t\t__FUNCTION__, status);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\n\t\t/* set channel switch option */\n\t\t_rtw_memset(&cs_option, 0, sizeof(cs_option));\n\t\tcs_option.dest_bw = HALMAC_BW_20;\n\t\tcs_option.periodic_option = HALMAC_CS_PERIODIC_2_PHASE;\n\t\tcs_option.dest_pri_ch_idx = HALMAC_CH_IDX_UNDEFINE;\n\t\tcs_option.tsf_low = 0;\n\t\tcs_option.switch_en = 1;\n\t\tcs_option.dest_ch_en = 1;\n\t\tcs_option.absolute_time_en = 0;\n\t\tcs_option.dest_ch = 1;\n\n\t\tcs_option.normal_period = 5;\n\t\tcs_option.normal_period_sel = 0;\n\t\tcs_option.normal_cycle = 10;\n\n\t\tcs_option.phase_2_period = 1;\n\t\tcs_option.phase_2_period_sel = 1;\n\n\t\t/* nlo is for wow fw,  1: no c2h response */\n\t\tcs_option.nlo_en = nlo;\n\n\t\tif (!nlo) {\n\t\t\terr = init_halmac_event(d, id_ch_sw, NULL, 0);\n\t\t\tif (err)\n\t\t\t\treturn -1;\n\t\t}\n\n\t\tstatus = api->halmac_ctrl_ch_switch(mac, &cs_option);\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\tif (!nlo)\n\t\t\t\tfree_halmac_event(d, id_ch_sw);\n\t\t\tRTW_ERR(\"%s: halmac_ctrl_ch_switch FAIL(%d)!!\\n\",\n\t\t\t\t__FUNCTION__, status);\n\t\t\treturn -1;\n\t\t}\n\n\t\tif (!nlo) {\n\t\t\terr = wait_halmac_event(d, id_ch_sw);\n\t\t\tif (err)\n\t\t\t\tRTW_ERR(\"%s: wait ctrl_ch_switch FAIL(%d)!!\\n\",\n\t\t\t\t\t__FUNCTION__, err);\n\t\t}\n\t} else {\n\t\tapi->halmac_clear_ch_info(mac);\n\n\t\t_rtw_memset(&cs_option, 0, sizeof(cs_option));\n\t\tcs_option.switch_en = 0;\n\n\t\tif (!nlo) {\n\t\t\terr = init_halmac_event(d, id_ch_sw, NULL, 0);\n\t\t\tif (err)\n\t\t\t\treturn -1;\n\t\t}\n\n\t\tstatus = api->halmac_ctrl_ch_switch(mac, &cs_option);\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\tif (!nlo)\n\t\t\t\tfree_halmac_event(d, id_ch_sw);\n\t\t\tRTW_ERR(\"%s: halmac_ctrl_ch_switch FAIL(%d)!!\\n\",\n\t\t\t\t__FUNCTION__, status);\n\t\t\treturn -1;\n\t\t}\n\n\t\tif (!nlo) {\n\t\t\terr = wait_halmac_event(d, id_ch_sw);\n\t\t\tif (err)\n\t\t\t\tRTW_ERR(\"%s: wait ctrl_ch_switch FAIL(%d)!!\\n\",\n\t\t\t\t\t__FUNCTION__, err);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/**\n * rtw_halmac_pno_scanoffload() - Control firmware scan AP function for PNO\n * @d:\t\tstruct dvobj_priv*\n * @enable:\t1: enable, 0: disable\n *\n * Switch firmware scan AP function for PNO(prefer network offload) or\n * NLO(network list offload).\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_pno_scanoffload(struct dvobj_priv *d, u32 enable)\n{\n\treturn _halmac_scanoffload(d, enable, 1, NULL, 0);\n}\n#endif /* CONFIG_PNO_SUPPORT */\n\n#ifdef CONFIG_SDIO_HCI\n\n/*\n * Description:\n *\tUpdate queue allocated page number to driver\n *\n * Parameter:\n *\td\tpointer to struct dvobj_priv of driver\n *\n * Rteurn:\n *\t0\tSuccess, \"page\" is valid.\n *\tothers\tFail, \"page\" is invalid.\n */\nint rtw_halmac_query_tx_page_num(struct dvobj_priv *d)\n{\n\tPADAPTER adapter;\n\tstruct halmacpriv *hmpriv;\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tstruct halmac_rqpn_map rqpn;\n\tenum halmac_dma_mapping dmaqueue;\n\tstruct halmac_txff_allocation fifosize;\n\tenum halmac_ret_status status;\n\tu8 i;\n\n\n\tadapter = dvobj_get_primary_adapter(d);\n\thmpriv = &d->hmpriv;\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\t_rtw_memset((void *)&rqpn, 0, sizeof(rqpn));\n\t_rtw_memset((void *)&fifosize, 0, sizeof(fifosize));\n\n\tstatus = api->halmac_get_hw_value(halmac, HALMAC_HW_RQPN_MAPPING, &rqpn);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\tstatus = api->halmac_get_hw_value(halmac, HALMAC_HW_TXFF_ALLOCATION, &fifosize);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\tfor (i = 0; i < HW_QUEUE_ENTRY; i++) {\n\t\thmpriv->txpage[i] = 0;\n\n\t\t/* Driver index mapping to HALMAC DMA queue */\n\t\tdmaqueue = HALMAC_DMA_MAPPING_UNDEFINE;\n\t\tswitch (i) {\n\t\tcase VO_QUEUE_INX:\n\t\t\tdmaqueue = rqpn.dma_map_vo;\n\t\t\tbreak;\n\t\tcase VI_QUEUE_INX:\n\t\t\tdmaqueue = rqpn.dma_map_vi;\n\t\t\tbreak;\n\t\tcase BE_QUEUE_INX:\n\t\t\tdmaqueue = rqpn.dma_map_be;\n\t\t\tbreak;\n\t\tcase BK_QUEUE_INX:\n\t\t\tdmaqueue = rqpn.dma_map_bk;\n\t\t\tbreak;\n\t\tcase MGT_QUEUE_INX:\n\t\t\tdmaqueue = rqpn.dma_map_mg;\n\t\t\tbreak;\n\t\tcase HIGH_QUEUE_INX:\n\t\t\tdmaqueue = rqpn.dma_map_hi;\n\t\t\tbreak;\n\t\tcase BCN_QUEUE_INX:\n\t\tcase TXCMD_QUEUE_INX:\n\t\t\t/* Unlimited */\n\t\t\thmpriv->txpage[i] = 0xFFFF;\n\t\t\tcontinue;\n\t\t}\n\n\t\tswitch (dmaqueue) {\n\t\tcase HALMAC_DMA_MAPPING_EXTRA:\n\t\t\thmpriv->txpage[i] = fifosize.extra_queue_pg_num;\n\t\t\tbreak;\n\t\tcase HALMAC_DMA_MAPPING_LOW:\n\t\t\thmpriv->txpage[i] = fifosize.low_queue_pg_num;\n\t\t\tbreak;\n\t\tcase HALMAC_DMA_MAPPING_NORMAL:\n\t\t\thmpriv->txpage[i] = fifosize.normal_queue_pg_num;\n\t\t\tbreak;\n\t\tcase HALMAC_DMA_MAPPING_HIGH:\n\t\t\thmpriv->txpage[i] = fifosize.high_queue_pg_num;\n\t\t\tbreak;\n\t\tcase HALMAC_DMA_MAPPING_UNDEFINE:\n\t\t\tbreak;\n\t\t}\n\t\thmpriv->txpage[i] += fifosize.pub_queue_pg_num;\n\t}\n\n\treturn 0;\n}\n\n/*\n * Description:\n *\tGet specific queue allocated page number\n *\n * Parameter:\n *\td\tpointer to struct dvobj_priv of driver\n *\tqueue\ttarget queue to query, VO/VI/BE/BK/.../TXCMD_QUEUE_INX\n *\tpage\treturn allocated page number\n *\n * Rteurn:\n *\t0\tSuccess, \"page\" is valid.\n *\tothers\tFail, \"page\" is invalid.\n */\nint rtw_halmac_get_tx_queue_page_num(struct dvobj_priv *d, u8 queue, u32 *page)\n{\n\t*page = 0;\n\tif (queue < HW_QUEUE_ENTRY)\n\t\t*page = d->hmpriv.txpage[queue];\n\n\treturn 0;\n}\n\n/*\n * Return:\n *\taddress for SDIO command\n */\nu32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *d, u8 *desc, u32 size)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 addr;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_get_sdio_tx_addr(mac, desc, size, &addr);\n\tif (HALMAC_RET_SUCCESS != status)\n\t\treturn 0;\n\n\treturn addr;\n}\n\nint rtw_halmac_sdio_tx_allowed(struct dvobj_priv *d, u8 *buf, u32 size)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_tx_allowed_sdio(mac, buf, size);\n\tif (HALMAC_RET_SUCCESS != status)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nu32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *d, u8 *seq)\n{\n\tu8 id;\n\n#define RTW_SDIO_ADDR_RX_RX0FF_PRFIX\t0x0E000\n#define RTW_SDIO_ADDR_RX_RX0FF_GEN(a)\t(RTW_SDIO_ADDR_RX_RX0FF_PRFIX|(a&0x3))\n\n\tid = *seq;\n\t(*seq)++;\n\treturn RTW_SDIO_ADDR_RX_RX0FF_GEN(id);\n}\n\nint rtw_halmac_sdio_set_tx_format(struct dvobj_priv *d, enum halmac_sdio_tx_format format)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_set_hw_value(mac, HALMAC_HW_SDIO_TX_FORMAT, &format);\n\tif (HALMAC_RET_SUCCESS != status)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n#ifdef CONFIG_SDIO_MONITOR\nu32 rtw_halmac_sdio_get_int_lat(struct dvobj_priv *d)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 int_lat = 0;\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_get_hw_value(mac, HALMAC_HW_SDIO_INT_LAT, &int_lat);\n\tif (HALMAC_RET_SUCCESS != status)\n\t\treturn 0;\n\n\treturn int_lat;\n}\n\nu32 rtw_halmac_sdio_get_lk_cnt(struct dvobj_priv *d)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 clk_cnt = 0;\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_get_hw_value(mac, HALMAC_HW_SDIO_CLK_CNT, &clk_cnt);\n\tif (HALMAC_RET_SUCCESS != status)\n\t\treturn 0;\n\n\treturn clk_cnt;\n}\n\nint rtw_halmac_sdio_set_wt_en(struct dvobj_priv *d)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu8\tenable = _TRUE;\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_set_hw_value(mac, HALMAC_HW_SDIO_WT_EN, &enable);\n\tif (HALMAC_RET_SUCCESS != status)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nint rtw_halmac_set_sdio_clk_monitor(struct dvobj_priv *d, u8 clk_moni_mode)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu32 halmac_clk_moni_mode = 0;\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tswitch (clk_moni_mode) {\n\tcase SDIO_MONITOR_MODE_SDIO_CLK_5US:\n\t\thalmac_clk_moni_mode = HALMAC_MONITOR_5US;\n\t\tbreak;\n\tcase SDIO_MONITOR_MODE_SDIO_CLK_50US:\n\t\thalmac_clk_moni_mode = HALMAC_MONITOR_50US;\n\t\tbreak;\n\tcase SDIO_MONITOR_MODE_SDIO_CLK_9MS:\n\t\thalmac_clk_moni_mode = HALMAC_MONITOR_9MS;\n\t\tbreak;\n\t}\n\n\tstatus = api->halmac_set_hw_value(mac, HALMAC_HW_SDIO_CLK_MONITOR, &halmac_clk_moni_mode);\n\tif (HALMAC_RET_SUCCESS != status)\n\t\treturn -1;\n\n\treturn 0;\n}\n#endif\n#endif /* CONFIG_SDIO_HCI */\n\n#ifdef CONFIG_USB_HCI\nu8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *d, u8 *buf, u32 size)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu8 bulkout_id;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_get_usb_bulkout_id(mac, buf, size, &bulkout_id);\n\tif (HALMAC_RET_SUCCESS != status)\n\t\treturn 0;\n\n\treturn bulkout_id;\n}\n\n/**\n * rtw_halmac_usb_get_txagg_desc_num() - MAX descriptor number in one bulk for TX\n * @d:\t\tstruct dvobj_priv*\n * @size:\tTX FIFO size, unit is byte.\n *\n * Get MAX descriptor number in one bulk out from HALMAC.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tu8 val = 0;\n\n\n\thalmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(halmac);\n\n\tstatus = api->halmac_get_hw_value(halmac, HALMAC_HW_USB_TXAGG_DESC_NUM, &val);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\t*num = val;\n\n\treturn 0;\n}\n\nstatic inline enum halmac_usb_mode _usb_mode_drv2halmac(enum RTW_USB_SPEED usb_mode)\n{\n\tenum halmac_usb_mode halmac_usb_mode = HALMAC_USB_MODE_U2;\n\n\tswitch (usb_mode) {\n\tcase RTW_USB_SPEED_2:\n\t\thalmac_usb_mode = HALMAC_USB_MODE_U2;\n\t\tbreak;\n\tcase RTW_USB_SPEED_3:\n\t\thalmac_usb_mode = HALMAC_USB_MODE_U3;\n\t\tbreak;\n\tdefault:\n\t\thalmac_usb_mode = HALMAC_USB_MODE_U2;\n\t\tbreak;\n\t}\n\n\treturn halmac_usb_mode;\n}\n\nu8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode)\n{\n\tPADAPTER adapter;\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tenum halmac_usb_mode halmac_usb_mode;\n\n\tadapter = dvobj_get_primary_adapter(d);\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\thalmac_usb_mode = _usb_mode_drv2halmac(usb_mode);\n\tstatus = api->halmac_set_hw_value(mac, HALMAC_HW_USB_MODE, (void *)&halmac_usb_mode);\n\n\tif (HALMAC_RET_SUCCESS != status)\n\t\treturn _FAIL;\n\n\treturn _SUCCESS;\n}\n#endif /* CONFIG_USB_HCI */\n\n#ifdef CONFIG_BEAMFORMING\n#ifdef RTW_BEAMFORMING_VERSION_2\nint rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para,\n\t\tu16 my_aid, enum halmac_csi_seg_len sel, u8 *addr)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tstruct halmac_mu_bfer_init_para param;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\t_rtw_memset(&param, 0, sizeof(param));\n\tparam.paid = paid;\n\tparam.csi_para = csi_para;\n\tparam.my_aid = my_aid;\n\tparam.csi_length_sel = sel;\n\t_rtw_memcpy(param.bfer_address.addr, addr, 6);\n\n\tstatus = api->halmac_mu_bfer_entry_init(mac, &param);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nint rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_mu_bfer_entry_del(mac);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n\nint rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d,\n\t\tenum halmac_snd_role role, enum halmac_data_rate rate)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_cfg_sounding(mac, role, rate);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nint rtw_halmac_bf_del_sounding(struct dvobj_priv *d,\n\t\tenum halmac_snd_role role)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_del_sounding(mac, role);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/**\n * rtw_halmac_bf_cfg_csi_rate() - Config data rate for CSI report by CSSI\n * @d:\t\tstruct dvobj_priv*\n * @rssi:\tRSSI vlaue, unit is percentage (0~100).\n * @current_rate:\tCurrent CSI frame rate\n *\t\t\tValid value example\n *\t\t\t0\tCCK 1M\n *\t\t\t3\tCCK 11M\n *\t\t\t4\tOFDM 6M\n *\t\t\tand so on\n * @fixrate_en:\tEnable to fix CSI frame in VHT rate, otherwise legacy OFDM rate.\n *\t\tThe value \"0\" for disable, otheriwse enable.\n * @new_rate:\tReturn new data rate, and value range is the same as current_rate\n * @bmp_ofdm54: Return to suggest enabling OFDM 54M for CSI report frame or not,\n *\t\tThe valid values and meanings are:\n *\t\t0x00\tdisable\n *\t\t0x01\tenable\n *\t\t0xFF\tKeep current setting\n *\n * According RSSI to config data rate for CSI report frame of Beamforming.\n *\n * Rteurn 0 for OK, otherwise fail.\n */\nint rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d,\n\t\tu8 rssi, u8 current_rate, u8 fixrate_en,\n\t\tu8 *new_rate, u8 *bmp_ofdm54)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\tstatus = api->halmac_cfg_csi_rate(mac,\n\t\t\trssi, current_rate, fixrate_en, new_rate, bmp_ofdm54);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nint rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role,\n\t\tu8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en,\n\t\tu32 *given_gid_tab, u32 *given_user_pos)\n{\n\tstruct halmac_adapter *mac;\n\tstruct halmac_api *api;\n\tenum halmac_ret_status status;\n\tstruct halmac_cfg_mumimo_para param;\n\n\n\tmac = dvobj_to_halmac(d);\n\tapi = HALMAC_GET_API(mac);\n\n\t_rtw_memset(&param, 0, sizeof(param));\n\n\tparam.role = role;\n\tparam.grouping_bitmap = grouping_bitmap;\n\tparam.mu_tx_en = mu_tx_en;\n\n\tif (sounding_sts)\n\t\t_rtw_memcpy(param.sounding_sts, sounding_sts, 6);\n\n\tif (given_gid_tab)\n\t\t_rtw_memcpy(param.given_gid_tab, given_gid_tab, 8);\n\n\tif (given_user_pos)\n\t\t_rtw_memcpy(param.given_user_pos, given_user_pos, 16);\n\n\tstatus = api->halmac_cfg_mumimo(mac, &param);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n#endif /* RTW_BEAMFORMING_VERSION_2 */\n#endif /* CONFIG_BEAMFORMING */\n"
  },
  {
    "path": "hal/hal_halmac.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2019 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _HAL_HALMAC_H_\n#define _HAL_HALMAC_H_\n\n#include <drv_types.h>\t\t/* adapter_to_dvobj(), struct intf_hdl and etc. */\n#include <hal_data.h>\t\t/* struct hal_spec_t */\n#include \"halmac/halmac_api.h\"\t/* struct halmac_adapter* and etc. */\n\n/* HALMAC Definition for Driver */\n#define RTW_HALMAC_H2C_MAX_SIZE\t\t8\n#define RTW_HALMAC_BA_SSN_RPT_SIZE\t4\n\n#define dvobj_set_halmac(d, mac)\t((d)->halmac = (mac))\n#define dvobj_to_halmac(d)\t\t((struct halmac_adapter *)((d)->halmac))\n#define adapter_to_halmac(p)\t\tdvobj_to_halmac(adapter_to_dvobj(p))\n\n/* for H2C cmd */\n#define MAX_H2C_BOX_NUMS 4\n#define MESSAGE_BOX_SIZE 4\n#define EX_MESSAGE_BOX_SIZE 4\n\ntypedef enum _RTW_HALMAC_MODE {\n\tRTW_HALMAC_MODE_NORMAL,\n\tRTW_HALMAC_MODE_WIFI_TEST,\n} RTW_HALMAC_MODE;\n\nunion rtw_phy_para_data {\n\tstruct _mac {\n\t\tu32\tvalue;\t/* value to be set in bit mask(msk) */\n\t\tu32\tmsk;\t/* bit mask */\n\t\tu16\toffset; /* address */\n\t\tu8\tmsk_en;\t/* 0/1 for msk invalid/valid */\n\t\tu8\tsize;\t/* Unit is bytes, and value should be 1/2/4 */\n\t} mac;\n\tstruct _bb {\n\t\tu32\tvalue;\n\t\tu32\tmsk;\n\t\tu16\toffset;\n\t\tu8\tmsk_en;\n\t\tu8\tsize;\n\t} bb;\n\tstruct _rf {\n\t\tu32\tvalue;\n\t\tu32\tmsk;\n\t\tu8\toffset;\n\t\tu8\tmsk_en;\n\t\t/*\n\t\t * 0: path A\n\t\t * 1: path B\n\t\t * 2: path C\n\t\t * 3: path D\n\t\t */\n\t\tu8\tpath;\n\t} rf;\n\tstruct _delay {\n\t\t/*\n\t\t * 0: microsecond (us)\n\t\t * 1: millisecond (ms)\n\t\t */\n\t\tu8\tunit;\n\t\tu16\tvalue;\n\t} delay;\n};\n\nstruct rtw_phy_parameter {\n\t/*\n\t * 0: MAC register\n\t * 1: BB register\n\t * 2: RF register\n\t * 3: Delay\n\t * 0xFF: Latest(End) command\n\t */\n\tu8 cmd;\n\tunion rtw_phy_para_data data;\n};\n\nstruct rtw_halmac_bcn_ctrl {\n\tu8 rx_bssid_fit:1;\t/* 0:HW handle beacon, 1:ignore */\n\tu8 txbcn_rpt:1;\t\t/* Enable TXBCN report in ad hoc and AP mode */\n\tu8 tsf_update:1;\t/* Update TSF when beacon or probe response */\n\tu8 enable_bcn:1;\t/* Enable beacon related functions */\n\tu8 rxbcn_rpt:1;\t\t/* Enable RXBCNOK report */\n\tu8 p2p_ctwin:1;\t\t/* Enable P2P CTN WINDOWS function */\n\tu8 p2p_bcn_area:1;\t/* Enable P2P BCN area on function */\n};\n\nextern struct halmac_platform_api rtw_halmac_platform_api;\n\n/* HALMAC API for Driver(HAL) */\nu8 rtw_halmac_read8(struct intf_hdl *, u32 addr);\nu16 rtw_halmac_read16(struct intf_hdl *, u32 addr);\nu32 rtw_halmac_read32(struct intf_hdl *, u32 addr);\nvoid rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);\n#ifdef CONFIG_SDIO_INDIRECT_ACCESS\nu8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr);\nu16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr);\nu32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr);\n#endif /* CONFIG_SDIO_INDIRECT_ACCESS */\nint rtw_halmac_write8(struct intf_hdl *, u32 addr, u8 value);\nint rtw_halmac_write16(struct intf_hdl *, u32 addr, u16 value);\nint rtw_halmac_write32(struct intf_hdl *, u32 addr, u32 value);\n\n/* Software Information */\nvoid rtw_halmac_get_version(char *str, u32 len);\n\n/* Software Initialization */\nint rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf_api);\nint rtw_halmac_deinit_adapter(struct dvobj_priv *);\n\n/* Get operations */\nint rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void *pvalue);\nint rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size);\nint rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size);\nint rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy);\nint rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size);\nint rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size);\nint rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size);\nint rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *, u8 *sz);\nint rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size);\nint rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size);\nint rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size);\nint rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size);\nint rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num);\nint rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);\nint rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type);\nint rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl);\n/*int rtw_halmac_get_wow_reason(struct dvobj_priv *, u8 *reason);*/\n\n/* Set operations */\nint rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info);\nint rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size);\nint rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);\nint rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);\nint rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);\nint rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type);\nint rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport);\nint rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport, u32 space);\nint rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl);\nint rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid);\nint rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw);\nint rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop);\nint rtw_halmac_set_rts_full_bw(struct dvobj_priv *d, u8 enable);\n\n/* Functions */\nint rtw_halmac_poweron(struct dvobj_priv *);\nint rtw_halmac_poweroff(struct dvobj_priv *);\nint rtw_halmac_init_hal(struct dvobj_priv *);\nint rtw_halmac_init_hal_fw(struct dvobj_priv *, u8 *fw, u32 fwsize);\nint rtw_halmac_init_hal_fw_file(struct dvobj_priv *, u8 *fwpath);\nint rtw_halmac_deinit_hal(struct dvobj_priv *);\nint rtw_halmac_self_verify(struct dvobj_priv *);\nint rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout);\nint rtw_halmac_dlfw(struct dvobj_priv *, u8 *fw, u32 fwsize);\nint rtw_halmac_dlfw_from_file(struct dvobj_priv *, u8 *fwpath);\nint rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem);\nint rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem);\nint rtw_halmac_phy_power_switch(struct dvobj_priv *, u8 enable);\nint rtw_halmac_send_h2c(struct dvobj_priv *, u8 *h2c);\nint rtw_halmac_c2h_handle(struct dvobj_priv *, u8 *c2h, u32 size);\n\n/* eFuse */\nint rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size);\nint rtw_halmac_get_physical_efuse_size(struct dvobj_priv *, u32 *size);\nint rtw_halmac_read_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size);\nint rtw_halmac_read_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);\nint rtw_halmac_write_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);\nint rtw_halmac_get_logical_efuse_size(struct dvobj_priv *, u32 *size);\nint rtw_halmac_read_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize);\nint rtw_halmac_write_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize);\nint rtw_halmac_read_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);\nint rtw_halmac_write_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);\n\nint rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);\nint rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size);\n\nint rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer);\nint rtw_halmac_rx_agg_switch(struct dvobj_priv *, u8 enable);\n\n/* Specific function APIs*/\nint rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size);\nint rtw_halmac_fill_hal_spec(struct dvobj_priv *, struct hal_spec_t *);\nint rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para);\nint rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment);\nint rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para);\nint rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode);\nvoid rtw_halmac_led_switch(struct dvobj_priv *d, u8 on);\nint rtw_halmac_bt_wake_cfg(struct dvobj_priv *d, u8 enable);\n#ifdef CONFIG_PNO_SUPPORT\nint rtw_halmac_pno_scanoffload(struct dvobj_priv *d, u32 enable);\n#endif\n\n#ifdef CONFIG_SDIO_HCI\nint rtw_halmac_query_tx_page_num(struct dvobj_priv *);\nint rtw_halmac_get_tx_queue_page_num(struct dvobj_priv *, u8 queue, u32 *page);\nu32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *, u8 *desc, u32 size);\nint rtw_halmac_sdio_tx_allowed(struct dvobj_priv *, u8 *buf, u32 size);\nu32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *, u8 *seq);\nint rtw_halmac_sdio_set_tx_format(struct dvobj_priv *d, enum halmac_sdio_tx_format format);\n#ifdef CONFIG_SDIO_MONITOR\nu32 rtw_halmac_sdio_get_int_lat(struct dvobj_priv *d);\nu32 rtw_halmac_sdio_get_lk_cnt(struct dvobj_priv *d);\nint rtw_halmac_sdio_set_wt_en(struct dvobj_priv *d);\nint rtw_halmac_set_sdio_clk_monitor(struct dvobj_priv *d, u8 clk_monitor_mode);\n#endif\n#endif /* CONFIG_SDIO_HCI */\n\n#ifdef CONFIG_USB_HCI\nu8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *, u8 *buf, u32 size);\nint rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num);\nu8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode);\n#endif /* CONFIG_USB_HCI */\n\n#ifdef CONFIG_SUPPORT_TRX_SHARED\nvoid dump_trx_share_mode(void *sel, _adapter *adapter);\n#endif\n\n#ifdef CONFIG_BEAMFORMING\n#ifdef RTW_BEAMFORMING_VERSION_2\nint rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para,\n\t\tu16 my_aid, enum halmac_csi_seg_len sel, u8 *addr);\nint rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d);\n\nint rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d, enum halmac_snd_role role,\n\t\tenum halmac_data_rate rate);\nint rtw_halmac_bf_del_sounding(struct dvobj_priv *d, enum halmac_snd_role role);\n\nint rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, u8 rssi, u8 current_rate,\n\t\tu8 fixrate_en, u8 *new_rate, u8 *bmp_ofdm54);\n\nint rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role,\n\t\tu8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en,\n\t\tu32 *given_gid_tab, u32 *given_user_pos);\n#define rtw_halmac_bf_cfg_mu_bfee(d, gid_tab, user_pos) \\\n\trtw_halmac_bf_cfg_mu_mimo(d, HAL_BFEE, NULL, 0, 0, gid_tab, user_pos)\n\n#endif /* RTW_BEAMFORMING_VERSION_2 */\n#endif /* CONFIG_BEAMFORMING */\n\n#endif /* _HAL_HALMAC_H_ */\n"
  },
  {
    "path": "hal/hal_hci/hal_pci.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _HAL_PCI_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n"
  },
  {
    "path": "hal/hal_intf.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#define _HAL_INTF_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\nconst u32 _chip_type_to_odm_ic_type[] = {\n\t0,\n\tODM_RTL8188E,\n\tODM_RTL8192E,\n\tODM_RTL8812,\n\tODM_RTL8821,\n\tODM_RTL8723B,\n\tODM_RTL8814A,\n\tODM_RTL8703B,\n\tODM_RTL8188F,\n\tODM_RTL8188F,\n\tODM_RTL8822B,\n\tODM_RTL8723D,\n\tODM_RTL8821C,\n\tODM_RTL8710B,\n\tODM_RTL8192F,\n\tODM_RTL8822C,\n\t0,\n};\n\nvoid rtw_hal_chip_configure(_adapter *padapter)\n{\n\tpadapter->hal_func.intf_chip_configure(padapter);\n}\n\n/*\n * Description:\n *\tRead chip internal ROM data\n *\n * Return:\n *\t_SUCCESS success\n *\t_FAIL\t fail\n */\nu8 rtw_hal_read_chip_info(_adapter *padapter)\n{\n\tu8 rtn = _SUCCESS;\n\tu8 hci_type = rtw_get_intf_type(padapter);\n\tsystime start = rtw_get_current_time();\n\n\t/*  before access eFuse, make sure card enable has been called */\n\tif ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)\n\t    && !rtw_is_hw_init_completed(padapter))\n\t\trtw_hal_power_on(padapter);\n\n\trtn = padapter->hal_func.read_adapter_info(padapter);\n\n\tif ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)\n\t    && !rtw_is_hw_init_completed(padapter))\n\t\trtw_hal_power_off(padapter);\n\n\tRTW_INFO(\"%s in %d ms\\n\", __func__, rtw_get_passing_time_ms(start));\n\n\treturn rtn;\n}\n\nvoid rtw_hal_read_chip_version(_adapter *padapter)\n{\n\tpadapter->hal_func.read_chip_version(padapter);\n\trtw_odm_init_ic_type(padapter);\n}\n\nstatic void rtw_init_wireless_mode(_adapter *padapter)\n{\n\tu8 proto_wireless_mode = 0;\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);\n\tif(hal_spec->proto_cap & PROTO_CAP_11B)\n\t\tproto_wireless_mode |= WIRELESS_11B;\n\t\n\tif(hal_spec->proto_cap & PROTO_CAP_11G)\n\t\tproto_wireless_mode |= WIRELESS_11G;\n#ifdef CONFIG_80211AC_VHT\n\tif(hal_spec->band_cap & BAND_CAP_5G)\n\t\tproto_wireless_mode |= WIRELESS_11A;\n#endif\n\n#ifdef CONFIG_80211N_HT\n\tif(hal_spec->proto_cap & PROTO_CAP_11N) {\n\n\t\tif(hal_spec->band_cap & BAND_CAP_2G)\n\t\t\tproto_wireless_mode |= WIRELESS_11_24N;\n\t\tif(hal_spec->band_cap & BAND_CAP_5G)\n\t\t\tproto_wireless_mode |= WIRELESS_11_5N;\n\t}\n#endif\n\n#ifdef CONFIG_80211AC_VHT\n\tif(hal_spec->proto_cap & PROTO_CAP_11AC) \n\t\tproto_wireless_mode |= WIRELESS_11AC;\n#endif\n\tpadapter->registrypriv.wireless_mode &= proto_wireless_mode;\n}\n\nvoid rtw_hal_def_value_init(_adapter *padapter)\n{\n\tif (is_primary_adapter(padapter)) {\n\t\t/*init fw_psmode_iface_id*/\n\t\tadapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff;\n\t\t/*wireless_mode*/\n\t\trtw_init_wireless_mode(padapter);\n\t\tpadapter->hal_func.init_default_value(padapter);\n\n\t\trtw_init_hal_com_default_value(padapter);\n\t\t\n\t\t#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\t\tadapter_to_dvobj(padapter)->dft.port_id = 0xFF;\n\t\tadapter_to_dvobj(padapter)->dft.mac_id = 0xFF;\n\t\t#endif\n\t\t#ifdef CONFIG_HW_P0_TSF_SYNC\n\t\tadapter_to_dvobj(padapter)->p0_tsf.sync_port = MAX_HW_PORT;\n\t\tadapter_to_dvobj(padapter)->p0_tsf.offset = 0;\n\t\t#endif\n\n\t\tGET_HAL_DATA(padapter)->rx_tsf_addr_filter_config = 0;\n\t}\n}\n\nu8 rtw_hal_data_init(_adapter *padapter)\n{\n\tif (is_primary_adapter(padapter)) {\n\t\tpadapter->hal_data_sz = sizeof(HAL_DATA_TYPE);\n\t\tpadapter->HalData = rtw_zvmalloc(padapter->hal_data_sz);\n\t\tif (padapter->HalData == NULL) {\n\t\t\tRTW_INFO(\"cant not alloc memory for HAL DATA\\n\");\n\t\t\treturn _FAIL;\n\t\t}\n\t\trtw_phydm_priv_init(padapter);\n\t}\n\treturn _SUCCESS;\n}\n\nvoid rtw_hal_data_deinit(_adapter *padapter)\n{\n\tif (is_primary_adapter(padapter)) {\n\t\tif (padapter->HalData) {\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\t\t\tphy_free_filebuf(padapter);\n#endif\n\t\t\trtw_vmfree(padapter->HalData, padapter->hal_data_sz);\n\t\t\tpadapter->HalData = NULL;\n\t\t\tpadapter->hal_data_sz = 0;\n\t\t}\n\t}\n}\n\nvoid\trtw_hal_free_data(_adapter *padapter)\n{\n\t/* free HAL Data\t */\n\trtw_hal_data_deinit(padapter);\n}\nvoid rtw_hal_dm_init(_adapter *padapter)\n{\n\tif (is_primary_adapter(padapter)) {\n\t\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(padapter);\n\n\t\tpadapter->hal_func.dm_init(padapter);\n\n\t\t_rtw_spinlock_init(&pHalData->IQKSpinLock);\n\n\t\tphy_load_tx_power_ext_info(padapter, 1);\n\t}\n}\nvoid rtw_hal_dm_deinit(_adapter *padapter)\n{\n\tif (is_primary_adapter(padapter)) {\n\t\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(padapter);\n\n\t\tpadapter->hal_func.dm_deinit(padapter);\n\n\t\t_rtw_spinlock_free(&pHalData->IQKSpinLock);\n\t}\n}\n\n#ifdef CONFIG_RTW_SW_LED\nvoid rtw_hal_sw_led_init(_adapter *padapter)\n{\n\tstruct led_priv *ledpriv = adapter_to_led(padapter);\n\n\tif (ledpriv->bRegUseLed == _FALSE)\n\t\treturn;\n\n\tif (!is_primary_adapter(padapter))\n\t\treturn;\n\n\tif (padapter->hal_func.InitSwLeds) {\n\t\tpadapter->hal_func.InitSwLeds(padapter);\n\t\trtw_led_set_ctl_en_mask_primary(padapter);\n\t\trtw_led_set_iface_en(padapter, 1);\n\t}\n}\n\nvoid rtw_hal_sw_led_deinit(_adapter *padapter)\n{\n\tstruct led_priv *ledpriv = adapter_to_led(padapter);\n\n\tif (ledpriv->bRegUseLed == _FALSE)\n\t\treturn;\n\n\tif (!is_primary_adapter(padapter))\n\t\treturn;\n\n\tif (padapter->hal_func.DeInitSwLeds)\n\t\tpadapter->hal_func.DeInitSwLeds(padapter);\n}\n#endif\n\nu32 rtw_hal_power_on(_adapter *padapter)\n{\n\tu32 ret = 0;\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);\n\n\tret = padapter->hal_func.hal_power_on(padapter);\n\n#ifdef CONFIG_BT_COEXIST\n\tif ((ret == _SUCCESS) && (pHalData->EEPROMBluetoothCoexist == _TRUE))\n\t\trtw_btcoex_PowerOnSetting(padapter);\n#endif\n\n\treturn ret;\n}\nvoid rtw_hal_power_off(_adapter *padapter)\n{\n\tstruct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl;\n\n\t_rtw_memset(macid_ctl->h2c_msr, 0, MACID_NUM_SW_LIMIT);\n\t_rtw_memset(macid_ctl->op_num, 0, H2C_MSR_ROLE_MAX);\n\n#ifdef CONFIG_LPS_1T1R\n\tGET_HAL_DATA(padapter)->lps_1t1r = 0;\n#endif\n\n#ifdef CONFIG_BT_COEXIST\n\trtw_btcoex_PowerOffSetting(padapter);\n#endif\n\n\tpadapter->hal_func.hal_power_off(padapter);\n}\n\n\nvoid rtw_hal_init_opmode(_adapter *padapter)\n{\n\tNDIS_802_11_NETWORK_INFRASTRUCTURE networkType = Ndis802_11InfrastructureMax;\n\tstruct  mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tsint fw_state;\n\n\tfw_state = get_fwstate(pmlmepriv);\n\n\tif (fw_state & WIFI_ADHOC_STATE)\n\t\tnetworkType = Ndis802_11IBSS;\n\telse if (fw_state & WIFI_STATION_STATE)\n\t\tnetworkType = Ndis802_11Infrastructure;\n#ifdef CONFIG_AP_MODE\n\telse if (fw_state & WIFI_AP_STATE)\n\t\tnetworkType = Ndis802_11APMode;\n#endif\n#ifdef CONFIG_RTW_MESH\n\telse if (fw_state & WIFI_MESH_STATE)\n\t\tnetworkType = Ndis802_11_mesh;\n#endif\n\telse\n\t\treturn;\n\n\trtw_setopmode_cmd(padapter, networkType, RTW_CMDF_DIRECTLY);\n}\n\n#ifdef CONFIG_NEW_NETDEV_HDL\nuint rtw_hal_iface_init(_adapter *adapter)\n{\n\tuint status = _SUCCESS;\n\n\trtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(adapter));\n\t#ifdef RTW_HALMAC\n\trtw_hal_hw_port_enable(adapter);\n\t#endif\n\trtw_sec_restore_wep_key(adapter);\n\trtw_hal_init_opmode(adapter);\n\trtw_hal_start_thread(adapter);\n\treturn status;\n}\nuint rtw_hal_init(_adapter *padapter)\n{\n\tuint status = _SUCCESS;\n\n\thalrf_set_rfsupportability(adapter_to_phydm(padapter));\n\n\tstatus = padapter->hal_func.hal_init(padapter);\n\n\tif (status == _SUCCESS) {\n\t\trtw_set_hw_init_completed(padapter, _TRUE);\n\t\tif (padapter->registrypriv.notch_filter == 1)\n\t\t\trtw_hal_notch_filter(padapter, 1);\n\t\trtw_led_control(padapter, LED_CTL_POWER_ON);\n\t\tinit_hw_mlme_ext(padapter);\n\t\t#ifdef CONFIG_RF_POWER_TRIM\n\t\trtw_bb_rf_gain_offset(padapter);\n\t\t#endif /*CONFIG_RF_POWER_TRIM*/\n\t\tGET_PRIMARY_ADAPTER(padapter)->bup = _TRUE; /*temporary*/\n\t\t#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\t\trtw_mi_set_mbid_cam(padapter);\n\t\t#endif\n\t\t#ifdef CONFIG_SUPPORT_MULTI_BCN\n\t\trtw_ap_multi_bcn_cfg(padapter);\n\t\t#endif\n\t\t#if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)\n\t\t#ifdef CONFIG_DYNAMIC_SOML\n\t\trtw_dyn_soml_config(padapter);\n\t\t#endif\n\t\t#endif\n\t\t#ifdef CONFIG_TDMADIG\n\t\trtw_phydm_tdmadig(padapter, TDMADIG_INIT);\n\t\t#endif/*CONFIG_TDMADIG*/\n#ifdef CONFIG_RTW_TX_2PATH_EN\n\t\trtw_phydm_tx_2path_en(padapter);\n#endif\n\t} else {\n\t\trtw_set_hw_init_completed(padapter, _FALSE);\n\t\tRTW_ERR(\"%s: hal_init fail\\n\", __func__);\n\t}\n\treturn status;\n}\n#else\nuint\t rtw_hal_init(_adapter *padapter)\n{\n\tuint\tstatus = _SUCCESS;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tint i;\n\n\thalrf_set_rfsupportability(adapter_to_phydm(padapter));\n\n\tstatus = padapter->hal_func.hal_init(padapter);\n\n\tif (status == _SUCCESS) {\n\t\trtw_set_hw_init_completed(padapter, _TRUE);\n\t\trtw_mi_set_mac_addr(padapter);/*set mac addr of all ifaces*/\n\t\t#ifdef RTW_HALMAC\n\t\trtw_restore_hw_port_cfg(padapter);\n\t\t#endif\n\t\tif (padapter->registrypriv.notch_filter == 1)\n\t\t\trtw_hal_notch_filter(padapter, 1);\n\n\t\tfor (i = 0; i < dvobj->iface_nums; i++)\n\t\t\trtw_sec_restore_wep_key(dvobj->padapters[i]);\n\n\t\trtw_led_control(padapter, LED_CTL_POWER_ON);\n\n\t\tinit_hw_mlme_ext(padapter);\n\n\t\trtw_hal_init_opmode(padapter);\n\n\t\t#ifdef CONFIG_RF_POWER_TRIM\n\t\trtw_bb_rf_gain_offset(padapter);\n\t\t#endif /*CONFIG_RF_POWER_TRIM*/\n\n\t\t#ifdef CONFIG_SUPPORT_MULTI_BCN\n\t\trtw_ap_multi_bcn_cfg(padapter);\n\t\t#endif\n\n#if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)\n#ifdef CONFIG_DYNAMIC_SOML\n\t\trtw_dyn_soml_config(padapter);\n#endif\n#endif\n\t\t#ifdef CONFIG_TDMADIG\n\t\trtw_phydm_tdmadig(padapter, TDMADIG_INIT);\n\t\t#endif/*CONFIG_TDMADIG*/\n\n#ifdef CONFIG_RTW_TX_2PATH_EN\n\t\trtw_phydm_tx_2path_en(padapter);\n#endif\n\t} else {\n\t\trtw_set_hw_init_completed(padapter, _FALSE);\n\t\tRTW_ERR(\"%s: fail\\n\", __func__);\n\t}\n\n\n\treturn status;\n\n}\n#endif\n\nuint rtw_hal_deinit(_adapter *padapter)\n{\n\tuint\tstatus = _SUCCESS;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tint i;\n\n\tstatus = padapter->hal_func.hal_deinit(padapter);\n\n\tif (status == _SUCCESS) {\n\t\trtw_led_control(padapter, LED_CTL_POWER_OFF);\n\t\trtw_set_hw_init_completed(padapter, _FALSE);\n\t} else\n\t\tRTW_INFO(\"\\n rtw_hal_deinit: hal_init fail\\n\");\n\n\n\treturn status;\n}\n\nu8 rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val)\n{\n\treturn padapter->hal_func.set_hw_reg_handler(padapter, variable, val);\n}\n\nvoid rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val)\n{\n\tpadapter->hal_func.GetHwRegHandler(padapter, variable, val);\n}\n\nu8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue)\n{\n\treturn padapter->hal_func.SetHalDefVarHandler(padapter, eVariable, pValue);\n}\nu8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue)\n{\n\treturn padapter->hal_func.get_hal_def_var_handler(padapter, eVariable, pValue);\n}\n\nvoid rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet)\n{\n\tpadapter->hal_func.SetHalODMVarHandler(padapter, eVariable, pValue1, bSet);\n}\nvoid\trtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2)\n{\n\tpadapter->hal_func.GetHalODMVarHandler(padapter, eVariable, pValue1, pValue2);\n}\n\n/* FOR SDIO & PCIE */\nvoid rtw_hal_enable_interrupt(_adapter *padapter)\n{\n#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)\n\tpadapter->hal_func.enable_interrupt(padapter);\n#endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */\n}\n\n/* FOR SDIO & PCIE */\nvoid rtw_hal_disable_interrupt(_adapter *padapter)\n{\n#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)\n\tpadapter->hal_func.disable_interrupt(padapter);\n#endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */\n}\n\n\nu8 rtw_hal_check_ips_status(_adapter *padapter)\n{\n\tu8 val = _FALSE;\n\tif (padapter->hal_func.check_ips_status)\n\t\tval = padapter->hal_func.check_ips_status(padapter);\n\telse\n\t\tRTW_INFO(\"%s: hal_func.check_ips_status is NULL!\\n\", __FUNCTION__);\n\n\treturn val;\n}\n\ns32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan)\n{\n\ts32 ret;\n\n\tret = padapter->hal_func.fw_dl(padapter, wowlan);\n\n#ifdef CONFIG_LPS_1T1R\n\tGET_HAL_DATA(padapter)->lps_1t1r = 0;\n#endif\n\n\treturn ret;\n}\n\n#ifdef RTW_HALMAC\ns32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem)\n{\n\tsystime dlfw_start_time = rtw_get_current_time();\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct debug_priv *pdbgpriv = &dvobj->drv_dbg;\n\ts32 rst = _FALSE;\n\n\trst = padapter->hal_func.fw_mem_dl(padapter, mem);\n\tRTW_INFO(\"%s in %dms\\n\", __func__, rtw_get_passing_time_ms(dlfw_start_time));\n\n\tif (rst == _FALSE)\n\t\tpdbgpriv->dbg_fw_mem_dl_error_cnt++;\n\tif (1)\n\t\tRTW_INFO(\"%s dbg_fw_mem_dl_error_cnt:%d\\n\", __func__, pdbgpriv->dbg_fw_mem_dl_error_cnt);\n\treturn rst;\n}\n#endif\n\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\nvoid rtw_hal_clear_interrupt(_adapter *padapter)\n{\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\tpadapter->hal_func.clear_interrupt(padapter);\n#endif\n}\n#endif\n\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)\nu32\trtw_hal_inirp_init(_adapter *padapter)\n{\n\tif (is_primary_adapter(padapter))\n\t\treturn padapter->hal_func.inirp_init(padapter);\n\treturn _SUCCESS;\n}\nu32\trtw_hal_inirp_deinit(_adapter *padapter)\n{\n\n\tif (is_primary_adapter(padapter))\n\t\treturn padapter->hal_func.inirp_deinit(padapter);\n\n\treturn _SUCCESS;\n}\n#endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */\n\n#if defined(CONFIG_PCI_HCI)\nvoid\trtw_hal_irp_reset(_adapter *padapter)\n{\n\tpadapter->hal_func.irp_reset(GET_PRIMARY_ADAPTER(padapter));\n}\n\nvoid rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data)\n{\n\tu16 cmd[2];\n\n\tcmd[0] = addr;\n\tcmd[1] = data;\n\n\tpadapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_DBI, (u8 *) cmd);\n}\n\nu8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr)\n{\n\tpadapter->hal_func.GetHwRegHandler(padapter, HW_VAR_DBI, (u8 *)(&addr));\n\n\treturn (u8)addr;\n}\n\nvoid rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data)\n{\n\tu16 cmd[2];\n\n\tcmd[0] = (u16)addr;\n\tcmd[1] = data;\n\n\tpadapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_MDIO, (u8 *) cmd);\n}\n\nu16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr)\n{\n\tpadapter->hal_func.GetHwRegHandler(padapter, HW_VAR_MDIO, &addr);\n\n\treturn (u8)addr;\n}\n\nu8 rtw_hal_pci_l1off_nic_support(_adapter *padapter)\n{\n\tu8 l1off;\n\n\tpadapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_NIC_SUPPORT, &l1off);\n\treturn l1off;\n}\n\nu8 rtw_hal_pci_l1off_capability(_adapter *padapter)\n{\n\tu8 l1off;\n\n\tpadapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_CAPABILITY, &l1off);\n\treturn l1off;\n}\n\n\n#endif /* #if defined(CONFIG_PCI_HCI) */\n\n/* for USB Auto-suspend */\nu8\trtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val)\n{\n\tif (padapter->hal_func.interface_ps_func)\n\t\treturn padapter->hal_func.interface_ps_func(padapter, efunc_id, val);\n\treturn _FAIL;\n}\n\ns32\trtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)\n{\n\treturn padapter->hal_func.hal_xmitframe_enqueue(padapter, pxmitframe);\n}\n\ns32\trtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)\n{\n\treturn padapter->hal_func.hal_xmit(padapter, pxmitframe);\n}\n\n/*\n * [IMPORTANT] This function would be run in interrupt context.\n */\ns32\trtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)\n{\n\ts32 ret = _FAIL;\n\n\tupdate_mgntframe_attrib_addr(padapter, pmgntframe);\n\n#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)\n\tif ((!MLME_IS_MESH(padapter) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE)\n\t\t#ifdef CONFIG_RTW_MESH\n\t\t|| (MLME_IS_MESH(padapter) && padapter->mesh_info.mesh_auth_id)\n\t\t#endif\n\t)\n\t\trtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe);\n#endif\n\n\tret = padapter->hal_func.mgnt_xmit(padapter, pmgntframe);\n\treturn ret;\n}\n\ns32\trtw_hal_init_xmit_priv(_adapter *padapter)\n{\n\treturn padapter->hal_func.init_xmit_priv(padapter);\n}\nvoid\trtw_hal_free_xmit_priv(_adapter *padapter)\n{\n\tpadapter->hal_func.free_xmit_priv(padapter);\n}\n\ns32\trtw_hal_init_recv_priv(_adapter *padapter)\n{\n\treturn padapter->hal_func.init_recv_priv(padapter);\n}\nvoid\trtw_hal_free_recv_priv(_adapter *padapter)\n{\n\tpadapter->hal_func.free_recv_priv(padapter);\n}\n\nvoid rtw_sta_ra_registed(_adapter *padapter, struct sta_info *psta)\n{\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);\n\n\tif (psta == NULL) {\n\t\tRTW_ERR(FUNC_ADPT_FMT\" sta is NULL\\n\", FUNC_ADPT_ARG(padapter));\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n#ifdef CONFIG_AP_MODE\n\tif (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {\n\t\tif (psta->cmn.aid > padapter->stapriv.max_aid) {\n\t\t\tRTW_ERR(\"station aid %d exceed the max number\\n\", psta->cmn.aid);\n\t\t\trtw_warn_on(1);\n\t\t\treturn;\n\t\t}\n\t\trtw_ap_update_sta_ra_info(padapter, psta);\n\t}\n#endif\n\n\tpsta->cmn.ra_info.ra_bw_mode = rtw_get_tx_bw_mode(padapter, psta);\n\t/*set correct initial date rate for each mac_id */\n\thal_data->INIDATA_RATE[psta->cmn.mac_id] = psta->init_rate;\n\n\trtw_phydm_ra_registed(padapter, psta);\n}\n\nvoid rtw_hal_update_ra_mask(struct sta_info *psta)\n{\n\t_adapter *padapter;\n\n\tif (!psta)\n\t\treturn;\n\n\tpadapter = psta->padapter;\n\trtw_sta_ra_registed(padapter, psta);\n}\n\n/*\tStart specifical interface thread\t\t*/\nvoid\trtw_hal_start_thread(_adapter *padapter)\n{\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n#ifndef CONFIG_SDIO_TX_TASKLET\n\tpadapter->hal_func.run_thread(padapter);\n#endif\n#endif\n}\n/*\tStart specifical interface thread\t\t*/\nvoid\trtw_hal_stop_thread(_adapter *padapter)\n{\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n#ifndef CONFIG_SDIO_TX_TASKLET\n\n\tpadapter->hal_func.cancel_thread(padapter);\n\n#endif\n#endif\n}\n\nu32\trtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask)\n{\n\tu32 data = 0;\n\tif (padapter->hal_func.read_bbreg)\n\t\tdata = padapter->hal_func.read_bbreg(padapter, RegAddr, BitMask);\n\treturn data;\n}\nvoid\trtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)\n{\n\tif (padapter->hal_func.write_bbreg)\n\t\tpadapter->hal_func.write_bbreg(padapter, RegAddr, BitMask, Data);\n}\n\nu32 rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask)\n{\n\tu32 data = 0;\n\n\tif (padapter->hal_func.read_rfreg) {\n\t\tdata = padapter->hal_func.read_rfreg(padapter, eRFPath, RegAddr, BitMask);\n\n\t\t#ifdef DBG_IO\n\t\tif (match_rf_read_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {\n\t\t\tRTW_INFO(\"DBG_IO rtw_hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\\n\"\n\t\t\t\t, eRFPath, RegAddr, BitMask, (data << PHY_CalculateBitShift(BitMask)), data);\n\t\t}\n\t\t#endif\n\t}\n\n\treturn data;\n}\n\nvoid rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)\n{\n\tif (padapter->hal_func.write_rfreg) {\n\n\t\t#ifdef DBG_IO\n\t\tif (match_rf_write_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {\n\t\t\tRTW_INFO(\"DBG_IO rtw_hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\\n\"\n\t\t\t\t, eRFPath, RegAddr, BitMask, (Data << PHY_CalculateBitShift(BitMask)), Data);\n\t\t}\n\t\t#endif\n\n\t\tpadapter->hal_func.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);\n\n#ifdef CONFIG_PCI_HCI\n\t\tif (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(padapter)) /*For N-Series IC, suggest by Jenyu*/\n\t\t\trtw_udelay_os(2);\n#endif\n\t}\n}\n\n#ifdef CONFIG_SYSON_INDIRECT_ACCESS\nu32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask)\n{\n\tu32 data = 0;\n\tif (padapter->hal_func.read_syson_reg)\n\t\tdata = padapter->hal_func.read_syson_reg(padapter, RegAddr, BitMask);\n\n\treturn data;\n}\n\nvoid rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)\n{\n\tif (padapter->hal_func.write_syson_reg)\n\t\tpadapter->hal_func.write_syson_reg(padapter, RegAddr, BitMask, Data);\n}\n#endif\n\n#if defined(CONFIG_PCI_HCI)\ns32\trtw_hal_interrupt_handler(_adapter *padapter)\n{\n\ts32 ret = _FAIL;\n\tret = padapter->hal_func.interrupt_handler(padapter);\n\treturn ret;\n}\n\nvoid\trtw_hal_unmap_beacon_icf(_adapter *padapter)\n{\n\tpadapter->hal_func.unmap_beacon_icf(padapter);\n}\n#endif\n#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)\nvoid\trtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf)\n{\n\tpadapter->hal_func.interrupt_handler(padapter, pkt_len, pbuf);\n}\n#endif\n\nvoid\trtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80)\n{\n\tPHAL_DATA_TYPE\tpHalData = GET_HAL_DATA(padapter);\n\tu8 cch_160 = Bandwidth == CHANNEL_WIDTH_160 ? channel : 0;\n\tu8 cch_80 = Bandwidth == CHANNEL_WIDTH_80 ? channel : 0;\n\tu8 cch_40 = Bandwidth == CHANNEL_WIDTH_40 ? channel : 0;\n\tu8 cch_20 = Bandwidth == CHANNEL_WIDTH_20 ? channel : 0;\n\n\tif (rtw_phydm_is_iqk_in_progress(padapter))\n\t\tRTW_ERR(\"%s, %d, IQK may race condition\\n\", __func__, __LINE__);\n\n#ifdef CONFIG_MP_INCLUDED\n\t/* MP mode channel don't use secondary channel */\n\tif (rtw_mp_mode_check(padapter) == _FALSE)\n#endif\n\t{\n\t\t#if 0\n\t\tif (cch_160 != 0)\n\t\t\tcch_80 = rtw_get_scch_by_cch_offset(cch_160, CHANNEL_WIDTH_160, Offset80);\n\t\t#endif\n\t\tif (cch_80 != 0)\n\t\t\tcch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, Offset80);\n\t\tif (cch_40 != 0)\n\t\t\tcch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, Offset40);\n\t}\n\n\tpHalData->cch_80 = cch_80;\n\tpHalData->cch_40 = cch_40;\n\tpHalData->cch_20 = cch_20;\n\n\tif (0)\n\t\tRTW_INFO(\"%s cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u)\\n\", __func__\n\t\t\t, channel, ch_width_str(Bandwidth), Offset40, Offset80\n\t\t\t, pHalData->cch_80, pHalData->cch_40, pHalData->cch_20);\n\n\tpadapter->hal_func.set_chnl_bw_handler(padapter, channel, Bandwidth, Offset40, Offset80);\n\tpHalData->current_band_type = channel > 14 ? BAND_ON_5G:BAND_ON_2_4G;\n}\n\nvoid\trtw_hal_dm_watchdog(_adapter *padapter)\n{\n\n\trtw_hal_turbo_edca(padapter);\n\tpadapter->hal_func.hal_dm_watchdog(padapter);\n\n#ifdef CONFIG_PCI_DYNAMIC_ASPM\n\trtw_pci_aspm_config_dynamic_l1_ilde_time(padapter);\n#endif\n}\n\n#ifdef CONFIG_LPS_LCLK_WD_TIMER\nvoid\trtw_hal_dm_watchdog_in_lps(_adapter *padapter)\n{\n#if defined(CONFIG_CONCURRENT_MODE)\n#ifndef CONFIG_FW_MULTI_PORT_SUPPORT\n\tif (padapter->hw_port != HW_PORT0)\n\t\treturn;\n#endif\n#endif\n\n\tif (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE)\n\t\trtw_phydm_watchdog_in_lps_lclk(padapter);/* this function caller is in interrupt context */\n}\n#endif /*CONFIG_LPS_LCLK_WD_TIMER*/\n\nvoid rtw_hal_bcn_related_reg_setting(_adapter *padapter)\n{\n\tpadapter->hal_func.SetBeaconRelatedRegistersHandler(padapter);\n}\n\n#ifdef CONFIG_HOSTAPD_MLME\ns32\trtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)\n{\n\tif (padapter->hal_func.hostap_mgnt_xmit_entry)\n\t\treturn padapter->hal_func.hostap_mgnt_xmit_entry(padapter, pkt);\n\treturn _FAIL;\n}\n#endif /* CONFIG_HOSTAPD_MLME */\n\n#ifdef DBG_CONFIG_ERROR_DETECT\nvoid\trtw_hal_sreset_init(_adapter *padapter)\n{\n\tpadapter->hal_func.sreset_init_value(padapter);\n}\nvoid rtw_hal_sreset_reset(_adapter *padapter)\n{\n\tpadapter = GET_PRIMARY_ADAPTER(padapter);\n\tpadapter->hal_func.silentreset(padapter);\n}\n\nvoid rtw_hal_sreset_reset_value(_adapter *padapter)\n{\n\tpadapter->hal_func.sreset_reset_value(padapter);\n}\n\nvoid rtw_hal_sreset_xmit_status_check(_adapter *padapter)\n{\n\tpadapter->hal_func.sreset_xmit_status_check(padapter);\n}\nvoid rtw_hal_sreset_linked_status_check(_adapter *padapter)\n{\n\tpadapter->hal_func.sreset_linked_status_check(padapter);\n}\nu8   rtw_hal_sreset_get_wifi_status(_adapter *padapter)\n{\n\treturn padapter->hal_func.sreset_get_wifi_status(padapter);\n}\n\nbool rtw_hal_sreset_inprogress(_adapter *padapter)\n{\n\tpadapter = GET_PRIMARY_ADAPTER(padapter);\n\treturn padapter->hal_func.sreset_inprogress(padapter);\n}\n#endif /* DBG_CONFIG_ERROR_DETECT */\n\n#ifdef CONFIG_IOL\nint rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_waiting_ms, u32 bndy_cnt)\n{\n\tif (adapter->hal_func.IOL_exec_cmds_sync)\n\t\treturn adapter->hal_func.IOL_exec_cmds_sync(adapter, xmit_frame, max_waiting_ms, bndy_cnt);\n\treturn _FAIL;\n}\n#endif\n\n#ifdef CONFIG_XMIT_THREAD_MODE\ns32 rtw_hal_xmit_thread_handler(_adapter *padapter)\n{\n\treturn padapter->hal_func.xmit_thread_handler(padapter);\n}\n#endif\n\n#ifdef CONFIG_RECV_THREAD_MODE\ns32 rtw_hal_recv_hdl(_adapter *adapter)\n{\n\treturn adapter->hal_func.recv_hdl(adapter);\n}\n#endif\n\nvoid rtw_hal_notch_filter(_adapter *adapter, bool enable)\n{\n\tif (adapter->hal_func.hal_notch_filter)\n\t\tadapter->hal_func.hal_notch_filter(adapter, enable);\n}\n\n#ifdef CONFIG_FW_C2H_REG\ninline bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf)\n{\n\tHAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);\n\tHAL_VERSION *hal_ver = &HalData->version_id;\n\tbool ret = _FAIL;\n\n\tret = C2H_ID_88XX(buf) || C2H_PLEN_88XX(buf);\n\n\treturn ret;\n}\n\ninline s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf)\n{\n\tHAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);\n\tHAL_VERSION *hal_ver = &HalData->version_id;\n\ts32 ret = _FAIL;\n\n\tret = c2h_evt_read_88xx(adapter, buf);\n\n\treturn ret;\n}\n\nbool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload)\n{\n\tHAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);\n\tHAL_VERSION *hal_ver = &HalData->version_id;\n\tbool ret = _FAIL;\n\n\t*id = C2H_ID_88XX(buf);\n\t*seq = C2H_SEQ_88XX(buf);\n\t*plen = C2H_PLEN_88XX(buf);\n\t*payload = C2H_PAYLOAD_88XX(buf);\n\tret = _SUCCESS;\n\n\treturn ret;\n}\n#endif /* CONFIG_FW_C2H_REG */\n\n#ifdef CONFIG_FW_C2H_PKT\nbool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload)\n{\n\tHAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);\n\tHAL_VERSION *hal_ver = &HalData->version_id;\n\tbool ret = _FAIL;\n\n\tif (!buf || len > 256 || len < 3)\n\t\tgoto exit;\n\n\t*id = C2H_ID_88XX(buf);\n\t*seq = C2H_SEQ_88XX(buf);\n\t*plen = len - 2;\n\t*payload = C2H_PAYLOAD_88XX(buf);\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n#endif /* CONFIG_FW_C2H_PKT */\n\n#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)\n#include <rtw_bt_mp.h> /* for MPTBT_FwC2hBtMpCtrl */\n#endif\ns32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)\n{\n\tu8 sub_id = 0;\n\ts32 ret = _SUCCESS;\n\n\tswitch (id) {\n\tcase C2H_FW_SCAN_COMPLETE:\n\t\tRTW_INFO(\"[C2H], FW Scan Complete\\n\");\n\t\tbreak;\n\n#ifdef CONFIG_BT_COEXIST\n\tcase C2H_BT_INFO:\n\t\trtw_btcoex_BtInfoNotify(adapter, plen, payload);\n\t\tbreak;\n\tcase C2H_BT_MP_INFO:\n\t\t#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)\n\t\tMPTBT_FwC2hBtMpCtrl(adapter, payload, plen);\n\t\t#endif\n\t\trtw_btcoex_BtMpRptNotify(adapter, plen, payload);\n\t\tbreak;\n\tcase C2H_MAILBOX_STATUS:\n\t\tRTW_DBG_DUMP(\"C2H_MAILBOX_STATUS: \", payload, plen);\n\t\tbreak;\n\tcase C2H_WLAN_INFO:\n\t\trtw_btcoex_WlFwDbgInfoNotify(adapter, payload, plen);\n\t\tbreak;\n#endif /* CONFIG_BT_COEXIST */\n\n\tcase C2H_IQK_FINISH:\n\t\tc2h_iqk_offload(adapter, payload, plen);\n\t\tbreak;\n\n#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)\n\tcase C2H_FW_CHNL_SWITCH_COMPLETE:\n\t\trtw_tdls_chsw_oper_done(adapter);\n\t\tbreak;\n\tcase C2H_BCN_EARLY_RPT:\n\t\trtw_tdls_ch_sw_back_to_base_chnl(adapter);\n\t\tbreak;\n#endif\n\n#ifdef CONFIG_MCC_MODE\n\tcase C2H_MCC:\n\t\trtw_hal_mcc_c2h_handler(adapter, plen, payload);\n\t\tbreak;\n#endif\n\n#ifdef CONFIG_RTW_MAC_HIDDEN_RPT\n\tcase C2H_MAC_HIDDEN_RPT:\n\t\tc2h_mac_hidden_rpt_hdl(adapter, payload, plen);\n\t\tbreak;\n\tcase C2H_MAC_HIDDEN_RPT_2:\n\t\tc2h_mac_hidden_rpt_2_hdl(adapter, payload, plen);\n\t\tbreak;\n#endif\n\n\tcase C2H_DEFEATURE_DBG:\n\t\tc2h_defeature_dbg_hdl(adapter, payload, plen);\n\t\tbreak;\n\n#ifdef CONFIG_RTW_CUSTOMER_STR\n\tcase C2H_CUSTOMER_STR_RPT:\n\t\tc2h_customer_str_rpt_hdl(adapter, payload, plen);\n\t\tbreak;\n\tcase C2H_CUSTOMER_STR_RPT_2:\n\t\tc2h_customer_str_rpt_2_hdl(adapter, payload, plen);\n\t\tbreak;\n#endif\n#ifdef RTW_PER_CMD_SUPPORT_FW\n\tcase C2H_PER_RATE_RPT:\n\t\tc2h_per_rate_rpt_hdl(adapter, payload, plen);\n\t\tbreak;\n#endif\n\n\tcase C2H_LPS_STATUS_RPT:\n\t\tbreak;\n\n\tcase C2H_EXTEND:\n\t\tsub_id = payload[0];\n\t\t/* no handle, goto default */\n\n\tdefault:\n\t\tif (phydm_c2H_content_parsing(adapter_to_phydm(adapter), id, plen, payload) != TRUE)\n\t\t\tret = _FAIL;\n\t\tbreak;\n\t}\n\n\tif (ret != _SUCCESS) {\n\t\tif (id == C2H_EXTEND)\n\t\t\tRTW_WARN(\"%s: unknown C2H(0x%02x, 0x%02x)\\n\", __func__, id, sub_id);\n\t\telse\n\t\t\tRTW_WARN(\"%s: unknown C2H(0x%02x)\\n\", __func__, id);\n\t}\n\n\treturn ret;\n}\n\n#ifndef RTW_HALMAC\ns32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)\n{\n\ts32 ret = _FAIL;\n\n\tret = adapter->hal_func.c2h_handler(adapter, id, seq, plen, payload);\n\tif (ret != _SUCCESS)\n\t\tret = c2h_handler(adapter, id, seq, plen, payload);\n\n\treturn ret;\n}\n\ns32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)\n{\n\tswitch (id) {\n\tcase C2H_CCX_TX_RPT:\n\tcase C2H_BT_MP_INFO:\n\tcase C2H_FW_CHNL_SWITCH_COMPLETE:\n\tcase C2H_IQK_FINISH:\n\tcase C2H_MCC:\n\tcase C2H_BCN_EARLY_RPT:\n\tcase C2H_AP_REQ_TXRPT:\n\tcase C2H_SPC_STAT:\n\t\treturn _TRUE;\n\tdefault:\n\t\treturn _FALSE;\n\t}\n}\n#endif /* !RTW_HALMAC */\n\ns32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter)\n{\n\treturn GET_HAL_DATA(padapter)->bDisableSWChannelPlan;\n}\n\nstatic s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep)\n{\n\tstruct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);\n\tu16 reg_sleep;\n\tu8 bit_shift;\n\tu32 val32;\n\ts32 ret = _FAIL;\n\n\tif (macid >= macid_ctl->num) {\n\t\tRTW_ERR(ADPT_FMT\" %s invalid macid(%u)\\n\"\n\t\t\t, ADPT_ARG(adapter), sleep ? \"sleep\" : \"wakeup\" , macid);\n\t\tgoto exit;\n\t}\n\n\tif (macid < 32) {\n\t\treg_sleep = macid_ctl->reg_sleep_m0;\n\t\tbit_shift = macid;\n\t#if (MACID_NUM_SW_LIMIT > 32)\n\t} else if (macid < 64) {\n\t\treg_sleep = macid_ctl->reg_sleep_m1;\n\t\tbit_shift = macid - 32;\n\t#endif\n\t#if (MACID_NUM_SW_LIMIT > 64)\n\t} else if (macid < 96) {\n\t\treg_sleep = macid_ctl->reg_sleep_m2;\n\t\tbit_shift = macid - 64;\n\t#endif\n\t#if (MACID_NUM_SW_LIMIT > 96)\n\t} else if (macid < 128) {\n\t\treg_sleep = macid_ctl->reg_sleep_m3;\n\t\tbit_shift = macid - 96;\n\t#endif\n\t} else {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (!reg_sleep) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tval32 = rtw_read32(adapter, reg_sleep);\n\tRTW_INFO(ADPT_FMT\" %s macid=%d, ori reg_0x%03x=0x%08x\\n\"\n\t\t, ADPT_ARG(adapter), sleep ? \"sleep\" : \"wakeup\"\n\t\t, macid, reg_sleep, val32);\n\n\tret = _SUCCESS;\n\n\tif (sleep) {\n\t\tif (val32 & BIT(bit_shift))\n\t\t\tgoto exit;\n\t\tval32 |= BIT(bit_shift);\n\t} else {\n\t\tif (!(val32 & BIT(bit_shift)))\n\t\t\tgoto exit;\n\t\tval32 &= ~BIT(bit_shift);\n\t}\n\n\trtw_write32(adapter, reg_sleep, val32);\n\nexit:\n\treturn ret;\n}\n\ninline s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid)\n{\n\treturn _rtw_hal_macid_sleep(adapter, macid, 1);\n}\n\ninline s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid)\n{\n\treturn _rtw_hal_macid_sleep(adapter, macid, 0);\n}\n\nstatic s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8 sleep)\n{\n\tstruct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);\n\tu16 reg_sleep;\n\tu32 m;\n\tu8 mid = 0;\n\tu32 val32;\n\n\tdo {\n\t\tif (mid == 0) {\n\t\t\tm = bmp->m0;\n\t\t\treg_sleep = macid_ctl->reg_sleep_m0;\n\t\t#if (MACID_NUM_SW_LIMIT > 32)\n\t\t} else if (mid == 1) {\n\t\t\tm = bmp->m1;\n\t\t\treg_sleep = macid_ctl->reg_sleep_m1;\n\t\t#endif\n\t\t#if (MACID_NUM_SW_LIMIT > 64)\n\t\t} else if (mid == 2) {\n\t\t\tm = bmp->m2;\n\t\t\treg_sleep = macid_ctl->reg_sleep_m2;\n\t\t#endif\n\t\t#if (MACID_NUM_SW_LIMIT > 96)\n\t\t} else if (mid == 3) {\n\t\t\tm = bmp->m3;\n\t\t\treg_sleep = macid_ctl->reg_sleep_m3;\n\t\t#endif\n\t\t} else {\n\t\t\trtw_warn_on(1);\n\t\t\tbreak;\n\t\t}\n\n\t\tif (m == 0)\n\t\t\tgoto move_next;\n\n\t\tif (!reg_sleep) {\n\t\t\trtw_warn_on(1);\n\t\t\tbreak;\n\t\t}\n\n\t\tval32 = rtw_read32(adapter, reg_sleep);\n\t\tRTW_INFO(ADPT_FMT\" %s m%u=0x%08x, ori reg_0x%03x=0x%08x\\n\"\n\t\t\t, ADPT_ARG(adapter), sleep ? \"sleep\" : \"wakeup\"\n\t\t\t, mid, m, reg_sleep, val32);\n\n\t\tif (sleep) {\n\t\t\tif ((val32 & m) == m)\n\t\t\t\tgoto move_next;\n\t\t\tval32 |= m;\n\t\t} else {\n\t\t\tif ((val32 & m) == 0)\n\t\t\t\tgoto move_next;\n\t\t\tval32 &= ~m;\n\t\t}\n\n\t\trtw_write32(adapter, reg_sleep, val32);\n\nmove_next:\n\t\tmid++;\n\t} while (mid * 32 < MACID_NUM_SW_LIMIT);\n\n\treturn _SUCCESS;\n}\n\ninline s32 rtw_hal_macid_sleep_all_used(_adapter *adapter)\n{\n\tstruct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);\n\n\treturn _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 1);\n}\n\ninline s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter)\n{\n\tstruct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);\n\n\treturn _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 0);\n}\n\ns32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)\n{\n\t_adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter);\n\n\tif (GET_HAL_DATA(pri_adapter)->bFWReady == _TRUE)\n\t\treturn padapter->hal_func.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer);\n\telse if (padapter->registrypriv.mp_mode == 0)\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\\n\"\n\t\t\t  , FUNC_ADPT_ARG(padapter), ElementID);\n\treturn _FAIL;\n}\n\nvoid rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen,\n\t\t\t      u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame)\n{\n\tpadapter->hal_func.fill_fake_txdesc(padapter, pDesc, BufferLen, IsPsPoll, IsBTQosNull, bDataFrame);\n\n}\n\nu8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan)\n{\n\tu8 num = 0;\n\n\n\tif (adapter->hal_func.hal_get_tx_buff_rsvd_page_num) {\n\t\tnum = adapter->hal_func.hal_get_tx_buff_rsvd_page_num(adapter, wowlan);\n\t} else {\n#ifdef RTW_HALMAC\n\t\tnum = GET_HAL_DATA(adapter)->drv_rsvd_page_number;\n#endif /* RTW_HALMAC */\n\t}\n\n\treturn num;\n}\n\n#ifdef CONFIG_GPIO_API\nvoid rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag)\n{\n\tif (padapter->hal_func.update_hisr_hsisr_ind)\n\t\tpadapter->hal_func.update_hisr_hsisr_ind(padapter, flag);\n}\n\nint rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num)\n{\n\tint ret = _SUCCESS;\n\n\tif (padapter->hal_func.hal_gpio_func_check)\n\t\tret = padapter->hal_func.hal_gpio_func_check(padapter, gpio_num);\n\n\treturn ret;\n}\n\nvoid rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num)\n{\n\tif (padapter->hal_func.hal_gpio_multi_func_reset)\n\t\tpadapter->hal_func.hal_gpio_multi_func_reset(padapter, gpio_num);\n}\n#endif\n\n#ifdef CONFIG_FW_CORRECT_BCN\nvoid rtw_hal_fw_correct_bcn(_adapter *padapter)\n{\n\tif (padapter->hal_func.fw_correct_bcn)\n\t\tpadapter->hal_func.fw_correct_bcn(padapter);\n}\n#endif\n\nvoid rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel)\n{\n\tadapter->hal_func.set_tx_power_level_handler(adapter, channel);\n\trtw_hal_set_txpwr_done(adapter);\n}\n\nvoid rtw_hal_set_txpwr_done(_adapter *adapter)\n{\n\tif (adapter->hal_func.set_txpwr_done)\n\t\tadapter->hal_func.set_txpwr_done(adapter);\n}\n\nvoid rtw_hal_set_tx_power_index(_adapter *adapter, u32 powerindex\n\t, enum rf_path rfpath, u8 rate)\n{\n\tadapter->hal_func.set_tx_power_index_handler(adapter, powerindex, rfpath, rate);\n}\n\nu8 rtw_hal_get_tx_power_index(_adapter *adapter, enum rf_path rfpath, u8 rate\n\t, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic)\n{\n\treturn adapter->hal_func.get_tx_power_index_handler(adapter, rfpath, rate\n\t\t, bandwidth, channel, tic);\n}\n\n#ifdef RTW_HALMAC\n/*\n * Description:\n *\tInitialize MAC registers\n *\n * Return:\n *\t_TRUE\tsuccess\n *\t_FALSE\tfail\n */\nu8 rtw_hal_init_mac_register(PADAPTER adapter)\n{\n\treturn adapter->hal_func.init_mac_register(adapter);\n}\n\n/*\n * Description:\n *\tInitialize PHY(BB/RF) related functions\n *\n * Return:\n *\t_TRUE\tsuccess\n *\t_FALSE\tfail\n */\nu8 rtw_hal_init_phy(PADAPTER adapter)\n{\n\treturn adapter->hal_func.init_phy(adapter);\n}\n#endif /* RTW_HALMAC */\n\n#ifdef CONFIG_RFKILL_POLL\nbool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid)\n{\n\tbool ret;\n\n\tif (adapter->hal_func.hal_radio_onoff_check)\n\t\tret = adapter->hal_func.hal_radio_onoff_check(adapter, valid);\n\telse {\n\t\t*valid = 0;\n\t\tret = _FALSE;\n\t}\n\treturn ret;\n}\n#endif\n\n#define rtw_hal_error_msg(ops_fun)\t\t\\\n\tRTW_PRINT(\"### %s - Error : Please hook hal_func.%s ###\\n\", __FUNCTION__, ops_fun)\n\nu8 rtw_hal_ops_check(_adapter *padapter)\n{\n\tu8 ret = _SUCCESS;\n#if 1\n\t/*** initialize section ***/\n\tif (NULL == padapter->hal_func.read_chip_version) {\n\t\trtw_hal_error_msg(\"read_chip_version\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.init_default_value) {\n\t\trtw_hal_error_msg(\"init_default_value\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.intf_chip_configure) {\n\t\trtw_hal_error_msg(\"intf_chip_configure\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.read_adapter_info) {\n\t\trtw_hal_error_msg(\"read_adapter_info\");\n\t\tret = _FAIL;\n\t}\n\n\tif (NULL == padapter->hal_func.hal_power_on) {\n\t\trtw_hal_error_msg(\"hal_power_on\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.hal_power_off) {\n\t\trtw_hal_error_msg(\"hal_power_off\");\n\t\tret = _FAIL;\n\t}\n\n\tif (NULL == padapter->hal_func.hal_init) {\n\t\trtw_hal_error_msg(\"hal_init\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.hal_deinit) {\n\t\trtw_hal_error_msg(\"hal_deinit\");\n\t\tret = _FAIL;\n\t}\n\n\t/*** xmit section ***/\n\tif (NULL == padapter->hal_func.init_xmit_priv) {\n\t\trtw_hal_error_msg(\"init_xmit_priv\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.free_xmit_priv) {\n\t\trtw_hal_error_msg(\"free_xmit_priv\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.hal_xmit) {\n\t\trtw_hal_error_msg(\"hal_xmit\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.mgnt_xmit) {\n\t\trtw_hal_error_msg(\"mgnt_xmit\");\n\t\tret = _FAIL;\n\t}\n#ifdef CONFIG_XMIT_THREAD_MODE\n\tif (NULL == padapter->hal_func.xmit_thread_handler) {\n\t\trtw_hal_error_msg(\"xmit_thread_handler\");\n\t\tret = _FAIL;\n\t}\n#endif\n\tif (NULL == padapter->hal_func.hal_xmitframe_enqueue) {\n\t\trtw_hal_error_msg(\"hal_xmitframe_enqueue\");\n\t\tret = _FAIL;\n\t}\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n#ifndef CONFIG_SDIO_TX_TASKLET\n\tif (NULL == padapter->hal_func.run_thread) {\n\t\trtw_hal_error_msg(\"run_thread\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.cancel_thread) {\n\t\trtw_hal_error_msg(\"cancel_thread\");\n\t\tret = _FAIL;\n\t}\n#endif\n#endif\n\n\t/*** recv section ***/\n\tif (NULL == padapter->hal_func.init_recv_priv) {\n\t\trtw_hal_error_msg(\"init_recv_priv\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.free_recv_priv) {\n\t\trtw_hal_error_msg(\"free_recv_priv\");\n\t\tret = _FAIL;\n\t}\n#ifdef CONFIG_RECV_THREAD_MODE\n\tif (NULL == padapter->hal_func.recv_hdl) {\n\t\trtw_hal_error_msg(\"recv_hdl\");\n\t\tret = _FAIL;\n\t}\n#endif\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)\n\tif (NULL == padapter->hal_func.inirp_init) {\n\t\trtw_hal_error_msg(\"inirp_init\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.inirp_deinit) {\n\t\trtw_hal_error_msg(\"inirp_deinit\");\n\t\tret = _FAIL;\n\t}\n#endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */\n\n\n\t/*** interrupt hdl section ***/\n#if defined(CONFIG_PCI_HCI)\n\tif (NULL == padapter->hal_func.irp_reset) {\n\t\trtw_hal_error_msg(\"irp_reset\");\n\t\tret = _FAIL;\n\t}\n#endif/*#if defined(CONFIG_PCI_HCI)*/\n#if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))\n\tif (NULL == padapter->hal_func.interrupt_handler) {\n\t\trtw_hal_error_msg(\"interrupt_handler\");\n\t\tret = _FAIL;\n\t}\n#endif /*#if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))*/\n\n#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)\n\tif (NULL == padapter->hal_func.enable_interrupt) {\n\t\trtw_hal_error_msg(\"enable_interrupt\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.disable_interrupt) {\n\t\trtw_hal_error_msg(\"disable_interrupt\");\n\t\tret = _FAIL;\n\t}\n#endif /* defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */\n\n\n\t/*** DM section ***/\n\tif (NULL == padapter->hal_func.dm_init) {\n\t\trtw_hal_error_msg(\"dm_init\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.dm_deinit) {\n\t\trtw_hal_error_msg(\"dm_deinit\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.hal_dm_watchdog) {\n\t\trtw_hal_error_msg(\"hal_dm_watchdog\");\n\t\tret = _FAIL;\n\t}\n\n\t/*** xxx section ***/\n\tif (NULL == padapter->hal_func.set_chnl_bw_handler) {\n\t\trtw_hal_error_msg(\"set_chnl_bw_handler\");\n\t\tret = _FAIL;\n\t}\n\n\tif (NULL == padapter->hal_func.set_hw_reg_handler) {\n\t\trtw_hal_error_msg(\"set_hw_reg_handler\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.GetHwRegHandler) {\n\t\trtw_hal_error_msg(\"GetHwRegHandler\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.get_hal_def_var_handler) {\n\t\trtw_hal_error_msg(\"get_hal_def_var_handler\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.SetHalDefVarHandler) {\n\t\trtw_hal_error_msg(\"SetHalDefVarHandler\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.GetHalODMVarHandler) {\n\t\trtw_hal_error_msg(\"GetHalODMVarHandler\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.SetHalODMVarHandler) {\n\t\trtw_hal_error_msg(\"SetHalODMVarHandler\");\n\t\tret = _FAIL;\n\t}\n\n\tif (NULL == padapter->hal_func.SetBeaconRelatedRegistersHandler) {\n\t\trtw_hal_error_msg(\"SetBeaconRelatedRegistersHandler\");\n\t\tret = _FAIL;\n\t}\n\n\tif (NULL == padapter->hal_func.fill_h2c_cmd) {\n\t\trtw_hal_error_msg(\"fill_h2c_cmd\");\n\t\tret = _FAIL;\n\t}\n\n#ifdef RTW_HALMAC\n\tif (NULL == padapter->hal_func.hal_mac_c2h_handler) {\n\t\trtw_hal_error_msg(\"hal_mac_c2h_handler\");\n\t\tret = _FAIL;\n\t}\n#elif !defined(CONFIG_RTL8188E)\n\tif (NULL == padapter->hal_func.c2h_handler) {\n\t\trtw_hal_error_msg(\"c2h_handler\");\n\t\tret = _FAIL;\n\t}\n#endif\n\n#if defined(CONFIG_LPS) || defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\n\tif (NULL == padapter->hal_func.fill_fake_txdesc) {\n\t\trtw_hal_error_msg(\"fill_fake_txdesc\");\n\t\tret = _FAIL;\n\t}\n#endif\n\n#ifndef RTW_HALMAC\n\tif (NULL == padapter->hal_func.hal_get_tx_buff_rsvd_page_num) {\n\t\trtw_hal_error_msg(\"hal_get_tx_buff_rsvd_page_num\");\n\t\tret = _FAIL;\n\t}\n#endif /* !RTW_HALMAC */\n\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\tif (NULL == padapter->hal_func.clear_interrupt) {\n\t\trtw_hal_error_msg(\"clear_interrupt\");\n\t\tret = _FAIL;\n\t}\n#endif\n#endif /* CONFIG_WOWLAN */\n\n\tif (NULL == padapter->hal_func.fw_dl) {\n\t\trtw_hal_error_msg(\"fw_dl\");\n\t\tret = _FAIL;\n\t}\n\n\t#ifdef CONFIG_FW_CORRECT_BCN\n\tif (IS_HARDWARE_TYPE_8814A(padapter)\n\t    && NULL == padapter->hal_func.fw_correct_bcn) {\n\t\trtw_hal_error_msg(\"fw_correct_bcn\");\n\t\tret = _FAIL;\n\t}\n\t#endif\n\n\tif (!padapter->hal_func.set_tx_power_level_handler) {\n\t\trtw_hal_error_msg(\"set_tx_power_level_handler\");\n\t\tret = _FAIL;\n\t}\n\tif (!padapter->hal_func.set_tx_power_index_handler) {\n\t\trtw_hal_error_msg(\"set_tx_power_index_handler\");\n\t\tret = _FAIL;\n\t}\n\tif (!padapter->hal_func.get_tx_power_index_handler) {\n\t\trtw_hal_error_msg(\"get_tx_power_index_handler\");\n\t\tret = _FAIL;\n\t}\n\n\t/*** SReset section ***/\n#ifdef DBG_CONFIG_ERROR_DETECT\n\tif (NULL == padapter->hal_func.sreset_init_value) {\n\t\trtw_hal_error_msg(\"sreset_init_value\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.sreset_reset_value) {\n\t\trtw_hal_error_msg(\"sreset_reset_value\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.silentreset) {\n\t\trtw_hal_error_msg(\"silentreset\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.sreset_xmit_status_check) {\n\t\trtw_hal_error_msg(\"sreset_xmit_status_check\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.sreset_linked_status_check) {\n\t\trtw_hal_error_msg(\"sreset_linked_status_check\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.sreset_get_wifi_status) {\n\t\trtw_hal_error_msg(\"sreset_get_wifi_status\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.sreset_inprogress) {\n\t\trtw_hal_error_msg(\"sreset_inprogress\");\n\t\tret = _FAIL;\n\t}\n#endif  /* #ifdef DBG_CONFIG_ERROR_DETECT */\n\n#ifdef RTW_HALMAC\n\tif (NULL == padapter->hal_func.init_mac_register) {\n\t\trtw_hal_error_msg(\"init_mac_register\");\n\t\tret = _FAIL;\n\t}\n\tif (NULL == padapter->hal_func.init_phy) {\n\t\trtw_hal_error_msg(\"init_phy\");\n\t\tret = _FAIL;\n\t}\n#endif /* RTW_HALMAC */\n\n#ifdef CONFIG_RFKILL_POLL\n\tif (padapter->hal_func.hal_radio_onoff_check == NULL) {\n\t\trtw_hal_error_msg(\"hal_radio_onoff_check\");\n\t\tret = _FAIL;\n\t}\n#endif\n#endif\n\treturn  ret;\n}\n"
  },
  {
    "path": "hal/hal_mcc.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifdef CONFIG_MCC_MODE\n#define _HAL_MCC_C_\n\n#include <drv_types.h> /* PADAPTER */\n#include <rtw_mcc.h> /* mcc structure */\n#include <hal_data.h> /* HAL_DATA */\n#include <rtw_pwrctrl.h> /* power control */\n\n/*  use for AP/GO + STA/GC case */\n#define MCC_DURATION_IDX 0 /* druration for station side */\n#define MCC_TSF_SYNC_OFFSET_IDX 1\n#define MCC_START_TIME_OFFSET_IDX 2\n#define MCC_INTERVAL_IDX 3\n#define MCC_GUARD_OFFSET0_IDX 4\n#define MCC_GUARD_OFFSET1_IDX 5\n#define MCC_STOP_THRESHOLD 6\n#define TU 1024 /* 1 TU equals 1024 microseconds */\n/* druration, TSF sync offset, start time offset, interval (unit:TU (1024 microseconds))*/\nu8 mcc_switch_channel_policy_table[][7]={\n\t{20, 50, 40, 100, 0, 0, 30},\n\t{80, 50, 10, 100, 0, 0, 30},\n\t{36, 50, 32, 100, 0, 0, 30},\n\t{30, 50, 35, 100, 0, 0, 30},\n};\n\nconst int mcc_max_policy_num = sizeof(mcc_switch_channel_policy_table) /sizeof(u8) /7;\n\nstatic void dump_iqk_val_table(PADAPTER padapter)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\tstruct hal_iqk_reg_backup *iqk_reg_backup = pHalData->iqk_reg_backup;\n\tu8 total_rf_path = pHalData->NumTotalRFPath;\n\tu8 rf_path_idx = 0;\n\tu8 backup_chan_idx = 0;\n\tu8 backup_reg_idx = 0;\n\n#ifdef CONFIG_MCC_MODE_V2\n#else\n\n\tRTW_INFO(\"=============dump IQK backup table================\\n\");\n\tfor (backup_chan_idx = 0; backup_chan_idx < MAX_IQK_INFO_BACKUP_CHNL_NUM; backup_chan_idx++) {\n\t\tfor (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx++) {\n\t\t\tfor(backup_reg_idx = 0; backup_reg_idx < MAX_IQK_INFO_BACKUP_REG_NUM; backup_reg_idx++) {\n\t\t\t\tRTW_INFO(\"ch:%d. bw:%d. rf path:%d. reg[%d] = 0x%02x \\n\"\n\t\t\t\t\t\t, iqk_reg_backup[backup_chan_idx].central_chnl\n\t\t\t\t\t\t, iqk_reg_backup[backup_chan_idx].bw_mode\n\t\t\t\t\t\t, rf_path_idx\n\t\t\t\t\t\t, backup_reg_idx\n\t\t\t\t\t\t, iqk_reg_backup[backup_chan_idx].reg_backup[rf_path_idx][backup_reg_idx]\n\t\t\t\t\t\t);\n\t\t\t}\n\t\t}\n\t}\t\n\tRTW_INFO(\"=============================================\\n\");\n\n#endif\n}\n\nstatic void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_len)\n{\n\tstruct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);\n\tu8 p2p_noa_attr_ie[MAX_P2P_IE_LEN] = {0x00};\n\tu32 p2p_noa_attr_len = 0;\n\tu8 noa_desc_num = 1;\n\tu8 opp_ps = 0; /* Disable OppPS */\n\tu8 noa_count = 255;\n\tu32 noa_duration;\n\tu32 noa_interval;\n\tu8 noa_index = 0;\n\tu8 mcc_policy_idx = 0;\n\n\tmcc_policy_idx = pmccobjpriv->policy_index;\n\tnoa_duration = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX] * TU;\n\tnoa_interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX] * TU;\n\n\t/* P2P OUI(4 bytes) */\n\t_rtw_memcpy(p2p_noa_attr_ie, P2P_OUI, 4);\n\tp2p_noa_attr_len = p2p_noa_attr_len + 4;\n\n\t/* attrute ID(1 byte) */\n\tp2p_noa_attr_ie[p2p_noa_attr_len] = P2P_ATTR_NOA;\n\tp2p_noa_attr_len = p2p_noa_attr_len + 1;\n\t\n\t/* attrute length(2 bytes) length = noa_desc_num*13 + 2 */\n\tRTW_PUT_LE16(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_desc_num * 13 + 2));\n\tp2p_noa_attr_len = p2p_noa_attr_len + 2;\n\n\t/* Index (1 byte) */\n\tp2p_noa_attr_ie[p2p_noa_attr_len] = noa_index;\n\tp2p_noa_attr_len = p2p_noa_attr_len + 1;\n\n\t/* CTWindow and OppPS Parameters (1 byte) */\n\tp2p_noa_attr_ie[p2p_noa_attr_len] = opp_ps;\n\tp2p_noa_attr_len = p2p_noa_attr_len+ 1;\n\n\t/* NoA Count (1 byte) */\n\tp2p_noa_attr_ie[p2p_noa_attr_len] = noa_count;\n\tp2p_noa_attr_len = p2p_noa_attr_len + 1;\n\n\t/* NoA Duration (4 bytes) unit: microseconds */\n\tRTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_duration);\n\tp2p_noa_attr_len = p2p_noa_attr_len + 4;\n\n\t/* NoA Interval (4 bytes) unit: microseconds */\n\tRTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_interval);\n\tp2p_noa_attr_len = p2p_noa_attr_len + 4;\n\n\t/* NoA Start Time (4 bytes) unit: microseconds */\n\tRTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, pmccadapriv->noa_start_time);\n\tif (0)\n\t\tRTW_INFO(\"indxe:%d, start_time=0x%02x:0x%02x:0x%02x:0x%02x\\n\"\n\t\t, noa_index\n\t\t, p2p_noa_attr_ie[p2p_noa_attr_len]\n\t\t, p2p_noa_attr_ie[p2p_noa_attr_len + 1]\n\t\t, p2p_noa_attr_ie[p2p_noa_attr_len + 2]\n\t\t, p2p_noa_attr_ie[p2p_noa_attr_len + 3]);\n\n\tp2p_noa_attr_len = p2p_noa_attr_len + 4;\n\trtw_set_ie(ie, _VENDOR_SPECIFIC_IE_, p2p_noa_attr_len, (u8 *)p2p_noa_attr_ie, ie_len);\n}\n\n\n/**\n * rtw_hal_mcc_update_go_p2p_ie - update go p2p ie(add NoA attribute)\n * @padapter: the adapter to be update go p2p ie\n */\nstatic void rtw_hal_mcc_update_go_p2p_ie(PADAPTER padapter)\n{\n\tstruct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;\n\tstruct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);\n\tu8 *pos = NULL;\n\n\n\t/* no noa attribute, build it */\n\tif (pmccadapriv->p2p_go_noa_ie_len == 0)\n\t\trtw_hal_mcc_build_p2p_noa_attr(padapter, pmccadapriv->p2p_go_noa_ie, &pmccadapriv->p2p_go_noa_ie_len);\n\telse {\n\t\t/* has noa attribut, modify it */\n\t\tu32 noa_duration = 0;\n\t\t\n\t\t/* update index */\n\t\tpos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 15;\n\t\t/* 0~255 */\n\t\t(*pos) = ((*pos) + 1) % 256;\n\t\tif (0)\n\t\t\tRTW_INFO(\"indxe:%d\\n\", (*pos));\n\n\n\t\t/* update duration */\n\t\tnoa_duration = mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX] * TU;\n\t\tpos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 12;\n\t\tRTW_PUT_LE32(pos, noa_duration);\n\n\t\t/* update start time */\n\t\tpos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 4;\n\t\tRTW_PUT_LE32(pos, pmccadapriv->noa_start_time);\n\t\tif (0)\n\t\t\tRTW_INFO(\"start_time=0x%02x:0x%02x:0x%02x:0x%02x\\n\"\n\t\t\t, ((u8*)(pos))[0]\n\t\t\t, ((u8*)(pos))[1]\n\t\t\t, ((u8*)(pos))[2]\n\t\t\t, ((u8*)(pos))[3]);\n\n\t}\n\n\tif (0) {\n\t\tRTW_INFO(\"p2p_go_noa_ie_len:%d\\n\", pmccadapriv->p2p_go_noa_ie_len);\n\t\tRTW_INFO_DUMP(\"\\n\", pmccadapriv->p2p_go_noa_ie, pmccadapriv->p2p_go_noa_ie_len);\n\t}\n\tupdate_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE, 0);\n}\n\n/**\n * rtw_hal_mcc_remove_go_p2p_ie - remove go p2p ie(add NoA attribute)\n * @padapter: the adapter to be update go p2p ie\n */\nstatic void rtw_hal_mcc_remove_go_p2p_ie(PADAPTER padapter)\n{\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;\n\n\t/* chech has noa ie or not */\n\tif (pmccadapriv->p2p_go_noa_ie_len == 0)\n\t\treturn;\n\n\tpmccadapriv->p2p_go_noa_ie_len = 0;\n\tupdate_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE, 0);\n}\n\n/* restore IQK value for all interface */\nvoid rtw_hal_mcc_restore_iqk_val(PADAPTER padapter)\n{\n\tu8 take_care_iqk = _FALSE;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\t_adapter *iface = NULL;\n\tstruct mcc_adapter_priv *mccadapriv = NULL;\n\tu8 i = 0;\n\n\trtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);\n\tif (take_care_iqk == _TRUE && MCC_EN(padapter)) {\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tif (iface == NULL)\n\t\t\t\tcontinue;\n\n\t\t\tmccadapriv = &iface->mcc_adapterpriv;\n\t\t\tif (mccadapriv->role == MCC_ROLE_MAX)\n\t\t\t\tcontinue;\n\n\t\t\trtw_hal_ch_sw_iqk_info_restore(iface, CH_SW_USE_CASE_MCC);\n\t\t}\n\t}\n\n\tif (0)\n\t\tdump_iqk_val_table(padapter);\n}\n\nu8 rtw_hal_check_mcc_status(PADAPTER padapter, u8 mcc_status)\n{\n\tstruct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);\n\n\tif (pmccobjpriv->mcc_status & (mcc_status))\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\n\nvoid rtw_hal_set_mcc_status(PADAPTER padapter, u8 mcc_status)\n{\n\tstruct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);\n\n\tpmccobjpriv->mcc_status |= (mcc_status);\n}\n\nvoid rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status)\n{\n\tstruct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);\n\n\tpmccobjpriv->mcc_status &= (~mcc_status);\n}\n\nstatic void rtw_hal_mcc_update_policy_table(PADAPTER adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);\n\tu8 mcc_duration = mccobjpriv->duration;\n\ts8 mcc_policy_idx = mccobjpriv->policy_index;\n\tu8 interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX];\n\tu8 new_mcc_duration_time = 0;\n\tu8 new_starttime_offset = 0;\n\n\t/* convert % to ms */\n\tnew_mcc_duration_time = mcc_duration * interval / 100;\n\n\t/* start time offset = (interval - duration time)/2 */\n\tnew_starttime_offset = (interval - new_mcc_duration_time) >> 1;\n\n\t/* update modified parameters */\n\tmcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX]\n\t\t= new_mcc_duration_time;\n\n\tmcc_switch_channel_policy_table[mcc_policy_idx][MCC_START_TIME_OFFSET_IDX]\n\t\t= new_starttime_offset;\n\t\n\n}\n\nstatic void rtw_hal_config_mcc_switch_channel_setting(PADAPTER padapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);\n\tstruct registry_priv *registry_par = &padapter->registrypriv;\n\tu8 mcc_duration = 0;\n\ts8 mcc_policy_idx = 0;\n\n\tmcc_policy_idx = registry_par->rtw_mcc_policy_table_idx;\n\tmcc_duration = mccobjpriv->duration;\n\n\tif (mcc_policy_idx < 0 || mcc_policy_idx >= mcc_max_policy_num) {\n\t\tmccobjpriv->policy_index = 0;\n\t\tRTW_INFO(\"[MCC] can't find table(%d), use default policy(%d)\\n\",\n\t\t\tmcc_policy_idx, mccobjpriv->policy_index);\n\t} else\n\t\tmccobjpriv->policy_index = mcc_policy_idx;\n\n\t/* convert % to time */\n\tif (mcc_duration != 0)\n\t\trtw_hal_mcc_update_policy_table(padapter);\n\n\tRTW_INFO(\"[MCC] policy(%d): %d,%d,%d,%d,%d,%d\\n\"\n\t\t, mccobjpriv->policy_index\n\t\t, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX]\n\t\t, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_TSF_SYNC_OFFSET_IDX]\n\t\t, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_START_TIME_OFFSET_IDX]\n\t\t, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_INTERVAL_IDX]\n\t\t, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX]\n\t\t, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX]);\n\n}\n\nstatic void rtw_hal_mcc_assign_tx_threshold(PADAPTER padapter) \n{\n\tstruct registry_priv *preg = &padapter->registrypriv;\n\tstruct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\n\tswitch (pmccadapriv->role) {\n\tcase MCC_ROLE_STA:\n\tcase MCC_ROLE_GC:\n\t\tswitch (pmlmeext->cur_bwmode) {\n\t\tcase CHANNEL_WIDTH_20:\n\t\t\t/*\n\t\t\t* target tx byte(bytes) = target tx tp(Mbits/sec) * 1024 * 1024 / 8 * (duration(ms) / 1024)\n\t\t\t*\t\t\t\t\t= target tx tp(Mbits/sec) * 128 * duration(ms)\n\t\t\t* note:\n\t\t\t* target tx tp(Mbits/sec) * 1024 * 1024 / 8 ==> Mbits to bytes\n\t\t\t* duration(ms) / 1024 ==> msec to sec\n\t\t\t*/\n\t\t\tpmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw20_target_tx_tp * 128 * pmccadapriv->mcc_duration;\n\t\t\tbreak;\n\t\tcase CHANNEL_WIDTH_40:\n\t\t\tpmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw40_target_tx_tp * 128 * pmccadapriv->mcc_duration;\n\t\t\tbreak;\n\t\tcase CHANNEL_WIDTH_80:\n\t\t\tpmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw80_target_tx_tp * 128 * pmccadapriv->mcc_duration;\n\t\t\tbreak;\n\t\tcase CHANNEL_WIDTH_160:\n\t\tcase CHANNEL_WIDTH_80_80:\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\": not support bwmode = %d\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode);\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase MCC_ROLE_AP:\n\tcase MCC_ROLE_GO:\n\t\tswitch (pmlmeext->cur_bwmode) {\n\t\tcase CHANNEL_WIDTH_20:\n\t\t\tpmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw20_target_tx_tp * 128 * pmccadapriv->mcc_duration;\n\t\t\tbreak;\n\t\tcase CHANNEL_WIDTH_40:\n\t\t\tpmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw40_target_tx_tp * 128 * pmccadapriv->mcc_duration;\n\t\t\tbreak;\n\t\tcase CHANNEL_WIDTH_80:\n\t\t\tpmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw80_target_tx_tp * 128 * pmccadapriv->mcc_duration;\n\t\t\tbreak;\n\t\tcase CHANNEL_WIDTH_160:\n\t\tcase CHANNEL_WIDTH_80_80:\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\": not support bwmode = %d\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode);\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(FUNC_ADPT_FMT\": unknown role = %d\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), pmccadapriv->role);\n\t\tbreak;\n\t}\n}\n\n#ifdef CONFIG_MCC_PHYDM_OFFLOAD\nstatic void mcc_cfg_phdym_rf_ch (_adapter *adapter)\n{\n\t\tstruct mcc_adapter_priv *mccadapriv = &adapter->mcc_adapterpriv;\n\t\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\t\tHAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);\n\t\tstruct dm_struct *dm = &hal->odmpriv;\n\t\tstruct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;\n\t\tu8 order = 0;\n\n\t\tset_channel_bwmode(adapter, mlmeext->cur_channel, mlmeext->cur_ch_offset, mlmeext->cur_bwmode);\n\t\torder = mccadapriv->order;\n\t\tmcc_dm->mcc_rf_channel[order] = phy_query_rf_reg(adapter, RF_PATH_A, 0x18, 0xffffffff);\n}\n\nstatic void mcc_cfg_phdym_update_macid (_adapter *adapter, u8 add, u8 mac_id)\n{\n\t\tstruct mcc_adapter_priv *mccadapriv = &adapter->mcc_adapterpriv;\n\t\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\t\tHAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);\n\t\tstruct dm_struct *dm = &hal->odmpriv;\n\t\tstruct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;\n\t\tu8 order = 0, i = 0;\n\n\t\torder = mccadapriv->order;\n\t\tif (add) {\n\t\t\tfor (i = 0; i < NUM_STA; i++) {\n\t\t\t\tif (mcc_dm->sta_macid[order][i] == 0xff) {\n\t\t\t\t\tmcc_dm->sta_macid[order][i] = mac_id;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tfor (i = 0; i < NUM_STA; i++) {\n\t\t\t\tif (mcc_dm->sta_macid[order][i] == mac_id) {\n\t\t\t\t\tmcc_dm->sta_macid[order][i] = 0xff;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t\n}\n\nstatic void mcc_cfg_phdym_start(_adapter *adapter, u8 start)\n{\n\tstruct dvobj_priv *dvobj;\n\tstruct mcc_obj_priv *mccobjpriv;\n\tHAL_DATA_TYPE *hal;\n\tstruct dm_struct *dm;\n\tstruct _phydm_mcc_dm_ *mcc_dm;\n\tu8 rfk_forbidden = _TRUE;\n\tu8 i = 0, j = 0;\n\n\tdvobj = adapter_to_dvobj(adapter);\n\tmccobjpriv = adapter_to_mccobjpriv(adapter);\n\thal = GET_HAL_DATA(adapter);\n\tdm = &hal->odmpriv;\n\tmcc_dm = &dm->mcc_dm;\n\n\tif (start) {\n\t\t#ifdef CONFIG_MCC_PHYDM_OFFLOAD\n\t\tmcc_dm->mcc_status = mccobjpriv->mcc_phydm_offload;\n\t\t#endif\n\n\t\trfk_forbidden = _TRUE;\n\t\thalrf_cmn_info_set(dm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);\n\t} else {\n\t\trfk_forbidden = _FALSE;\n\t\thalrf_cmn_info_set(dm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);\n\n\t\t#ifdef CONFIG_MCC_PHYDM_OFFLOAD\n\t\tfor(i = 0; i < MAX_MCC_NUM; i ++) {\n\t\t\tfor(j = 0; j < NUM_STA; j ++) {\n\t\t\t\tif (mcc_dm->sta_macid[i][j] != 0xff)\n\t\t\t\t\t/* clear all used value for mcc stop */\n\t\t\t\t\t/* do nothing for mcc start due to phydm will init to 0xff */\n\t\t\t\t\tmcc_dm->sta_macid[i][j] = 0xff;\n\t\t\t}\n\t\t\tmcc_dm->mcc_rf_channel[i] = 0xff;\n\t\t}\n\t\tmcc_dm->mcc_status = 0;\n\t\t#endif\n\t}\n}\n\nstatic void mcc_cfg_phdym_dump(_adapter *adapter, void *sel)\n{\n\tHAL_DATA_TYPE *hal;\n\tstruct dm_struct *dm;\n\tstruct _phydm_mcc_dm_ *mcc_dm;\n\tu8 rfk_forbidden = _TRUE;\n\tu8 i = 0, j = 0;\n\n\n\thal = GET_HAL_DATA(adapter);\n\tdm = &hal->odmpriv;\n\tmcc_dm = &dm->mcc_dm;\n\n\trfk_forbidden = halrf_cmn_info_get(dm, HALRF_CMNINFO_RFK_FORBIDDEN);\n\tRTW_PRINT_SEL(sel, \"dump mcc dm info\\n\");\n\tRTW_PRINT_SEL(sel, \"mcc_status=%d\\n\", mcc_dm->mcc_status);\n\tRTW_PRINT_SEL(sel, \"rfk_forbidden=%d\\n\", rfk_forbidden);\n\tfor(i = 0; i < MAX_MCC_NUM; i ++) {\n\n\t\tif (mcc_dm->mcc_rf_channel[i] != 0xff)\n\t\t\tRTW_PRINT_SEL(sel, \"mcc_dm->mcc_rf_channel[%d] = 0x%02x\\n\", i, mcc_dm->mcc_rf_channel[i]);\n\t\t\n\t\tfor(j = 0; j < NUM_STA; j ++) {\n\t\t\tif (mcc_dm->sta_macid[i][j] != 0xff)\n\t\t\t\tRTW_PRINT_SEL(sel, \"mcc_dm->sta_macid[%d][%d] = %d\\n\", i, j, mcc_dm->sta_macid[i][j]);\n\t\t}\n\t}\n}\n\nstatic void mcc_cfg_phdym_offload(_adapter *adapter, u8 enable)\n{\n\tstruct mcc_obj_priv *mccobjpriv = adapter_to_mccobjpriv(adapter);\n\t_adapter *iface = NULL;\n\tstruct mcc_adapter_priv *mccadapriv = NULL;\n\tHAL_DATA_TYPE *hal = NULL;\n\tstruct dm_struct *dm = NULL;\n\tstruct _phydm_mcc_dm_ *mcc_dm = NULL;\n\tstruct sta_priv *stapriv = NULL;\n\tstruct sta_info *sta = NULL;\n\tstruct wlan_network *cur_network = NULL;\n\t_irqL irqL;\n\t_list\t*head = NULL, *list = NULL;\n\tu8 i = 0;\n\n\n\thal = GET_HAL_DATA(adapter);\n\tdm = &hal->odmpriv;\n\tmcc_dm = &dm->mcc_dm;\n\n\t/* due to phydm will rst related date, driver must set related data */\n\tif (enable) {\n\t\tfor (i = 0; i < MAX_MCC_NUM; i++) {\n\t\t\tiface = mccobjpriv->iface[i];\n\t\t\tif (!iface)\n\t\t\t\tcontinue;\n\t\t\tstapriv = &iface->stapriv;\n\t\t\tmccadapriv = &iface->mcc_adapterpriv;\n\t\t\tswitch (mccadapriv->role) {\n\t\t\tcase MCC_ROLE_STA:\n\t\t\tcase MCC_ROLE_GC:\n\t\t\t\tcur_network = &iface->mlmepriv.cur_network;\n\t\t\t\tsta = rtw_get_stainfo(stapriv, cur_network->network.MacAddress);\n\t\t\t\tif (sta)\n\t\t\t\t\tmcc_cfg_phdym_update_macid(iface, _TRUE, sta->cmn.mac_id);\n\t\t\t\tbreak;\n\t\t\tcase MCC_ROLE_AP:\n\t\t\tcase MCC_ROLE_GO:\n\t\t\t\t_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);\n\n\t\t\t\thead = &stapriv->asoc_list;\n\t\t\t\tlist = get_next(head);\n\t\t\n\t\t\t\twhile ((rtw_end_of_queue_search(head, list)) == _FALSE) {\n\t\t\t\t\tsta = LIST_CONTAINOR(list, struct sta_info, asoc_list);\n\t\t\t\t\tlist = get_next(list);\n\t\t\t\t\tmcc_cfg_phdym_update_macid(iface, _TRUE, sta->cmn.mac_id);\n\t\t\t\t}\n\n\t\t\t\t_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tRTW_INFO(\"Unknown role\\n\");\n\t\t\t\trtw_warn_on(1);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\t\n\t\t}\n\t}\n\n\tmcc_dm->mcc_status = enable;\n}\n\nstatic void rtw_hal_mcc_cfg_phydm (_adapter *adapter, enum mcc_cfg_phydm_ops ops, void *data)\n{\n\tswitch (ops) {\n\tcase MCC_CFG_PHYDM_OFFLOAD:\n\t\tmcc_cfg_phdym_offload(adapter, *(u8 *)data);\n\t\tbreak;\n\tcase MCC_CFG_PHYDM_RF_CH:\n\t\tmcc_cfg_phdym_rf_ch(adapter);\n\t\tbreak;\n\tcase MCC_CFG_PHYDM_ADD_CLIENT:\n\t\tmcc_cfg_phdym_update_macid(adapter, _TRUE, *(u8 *)data);\n\t\tbreak;\n\tcase MCC_CFG_PHYDM_REMOVE_CLIENT:\n\t\tmcc_cfg_phdym_update_macid(adapter, _FALSE, *(u8 *)data);\n\t\tbreak;\n\tcase MCC_CFG_PHYDM_START:\n\t\tmcc_cfg_phdym_start(adapter, _TRUE);\n\t\tbreak;\n\tcase MCC_CFG_PHYDM_STOP:\n\t\tmcc_cfg_phdym_start(adapter, _FALSE);\n\t\tbreak;\n\tcase MCC_CFG_PHYDM_DUMP:\n\t\tmcc_cfg_phdym_dump(adapter, data);\n\t\tbreak;\n\tcase MCC_CFG_PHYDM_MAX:\n\tdefault:\n\t\tRTW_ERR(\"[MCC] rtw_hal_mcc_cfg_phydm ops error (%d)\\n\", ops);\n\t\tbreak;\n\n\t}\n}\n#endif\n\nstatic void rtw_hal_config_mcc_role_setting(PADAPTER padapter, u8 order)\n{\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);\n\tstruct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct wlan_network *cur_network = &(pmlmepriv->cur_network);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct sta_info *psta = NULL;\n\tstruct registry_priv *preg = &padapter->registrypriv;\n\t_irqL irqL;\n\t_list\t*phead =NULL, *plist = NULL;\n\tu8 policy_index = 0;\n\tu8 mcc_duration = 0;\n\tu8 mcc_interval = 0;\n\tu8 starting_ap_num = DEV_AP_STARTING_NUM(pdvobjpriv);\n\tu8 ap_num = DEV_AP_NUM(pdvobjpriv);\n\n\tpolicy_index = pmccobjpriv->policy_index;\n\tmcc_duration = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_DURATION_IDX]\n\t\t- mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX]\n\t\t\t- mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX];\n\tmcc_interval = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_INTERVAL_IDX];\n\n\tif (starting_ap_num == 0 && ap_num == 0) {\n\t\tpmccadapriv->order = order;\n\n\t\tif (pmccadapriv->order == 0) {\n\t\t\t/* setting is smiliar to GO/AP */\n\t\t\t/* pmccadapriv->mcc_duration = mcc_interval - mcc_duration;*/\n\t\t\tpmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID;\n\t\t} else if (pmccadapriv->order == 1) {\n\t\t\t/* pmccadapriv->mcc_duration = mcc_duration; */\n\t\t\tpmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID;\n\t\t} else {\n\t\t\tRTW_INFO(\"[MCC] not support >= 3 interface\\n\");\n\t\t\trtw_warn_on(1);\n\t\t}\n\n\t\trtw_hal_mcc_assign_tx_threshold(padapter);\n\n\t\tpsta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);\n\t\tif (psta) {\n\t\t\t/* combine AP/GO macid and mgmt queue macid to bitmap */\n\t\t\tpmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid);\n\t\t\t#ifdef CONFIG_MCC_PHYDM_OFFLOAD\n\t\t\trtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_ADD_CLIENT, &psta->cmn.mac_id);\n\t\t\t#endif\n\t\t} else {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\":AP/GO station info is NULL\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\trtw_warn_on(1);\n\t\t}\n\t} else {\n\t\t/* GO/AP is 1nd order  GC/STA is 2nd order */\n\t\tswitch (pmccadapriv->role) {\n\t\tcase MCC_ROLE_STA:\n\t\tcase MCC_ROLE_GC:\n\t\t\tpmccadapriv->order = 1;\n\t\t\tpmccadapriv->mcc_duration = mcc_duration;\n\n\t\t\trtw_hal_mcc_assign_tx_threshold(padapter);\n\t\t\t/* assign used mac to avoid affecting RA */\n\t\t\tpmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID;\n\n\t\t\tpsta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);\n\t\t\tif (psta) {\n\t\t\t\t/* combine AP/GO macid and mgmt queue macid to bitmap */\n\t\t\t\tpmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid);\n\t\t\t\t#ifdef CONFIG_MCC_PHYDM_OFFLOAD\n\t\t\t\trtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_ADD_CLIENT, &psta->cmn.mac_id);\n\t\t\t\t#endif\n\t\t\t} else {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\":AP/GO station info is NULL\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\t\trtw_warn_on(1);\n\t\t\t}\n\t\t\tbreak;\n\t\tcase MCC_ROLE_AP:\n\t\tcase MCC_ROLE_GO:\n\t\t\tpmccadapriv->order = 0;\n\t\t\t/* total druation value equals interval */\n\t\t\tpmccadapriv->mcc_duration = mcc_interval - mcc_duration;\n\t\t\tpmccadapriv->p2p_go_noa_ie_len = 0; /* not NoA attribute at init time */\n\n\t\t\trtw_hal_mcc_assign_tx_threshold(padapter);\n\n\t\t\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\t\t\tphead = &pstapriv->asoc_list;\n\t\t\tplist = get_next(phead);\n\t\t\tpmccadapriv->mcc_macid_bitmap = 0;\n\t\n\t\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);\n\t\t\t\tplist = get_next(plist);\n\t\t\t\tpmccadapriv->mcc_macid_bitmap |= BIT(psta->cmn.mac_id);\n\t\t\t\t#ifdef CONFIG_MCC_PHYDM_OFFLOAD\n\t\t\t\trtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_ADD_CLIENT, &psta->cmn.mac_id);\n\t\t\t\t#endif\n\t\t\t}\n\n\t\t\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\t\t\tpsta = rtw_get_bcmc_stainfo(padapter);\n\n\t\t\tif (psta != NULL)\n\t\t\t\tpmccadapriv->mgmt_queue_macid = psta->cmn.mac_id;\n\t\t\telse {\n\t\t\t\tpmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID;\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\":bcmc station is NULL, use macid %d\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), pmccadapriv->mgmt_queue_macid);\n\t\t\t}\n\n\t\t\t/* combine client macid and mgmt queue macid to bitmap */\n\t\t\tpmccadapriv->mcc_macid_bitmap |= BIT(pmccadapriv->mgmt_queue_macid);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tRTW_INFO(\"Unknown role\\n\");\n\t\t\trtw_warn_on(1);\n\t\t\tbreak;\n\t\t}\n\n\t}\n\n\t/* setting Null data parameters */\n\tif (pmccadapriv->role == MCC_ROLE_STA) {\n\t\t\tpmccadapriv->null_early = 3;\n\t\t\tpmccadapriv->null_rty_num= 5;\n\t} else if (pmccadapriv->role == MCC_ROLE_GC) {\n\t\t\tpmccadapriv->null_early = 2;\n\t\t\tpmccadapriv->null_rty_num= 5;\n\t} else {\n\t\t\tpmccadapriv->null_early = 0;\n\t\t\tpmccadapriv->null_rty_num= 0;\n\t}\n\n\tRTW_INFO(\"********* \"FUNC_ADPT_FMT\" *********\\n\", FUNC_ADPT_ARG(padapter));\n\tRTW_INFO(\"order:%d\\n\", pmccadapriv->order);\n\tRTW_INFO(\"role:%d\\n\", pmccadapriv->role);\n\tRTW_INFO(\"mcc duration:%d\\n\", pmccadapriv->mcc_duration);\n\tRTW_INFO(\"null_early:%d\\n\", pmccadapriv->null_early);\n\tRTW_INFO(\"null_rty_num:%d\\n\", pmccadapriv->null_rty_num);\n\tRTW_INFO(\"mgmt queue macid:%d\\n\", pmccadapriv->mgmt_queue_macid);\n\tRTW_INFO(\"bitmap:0x%02x\\n\", pmccadapriv->mcc_macid_bitmap);\n\tRTW_INFO(\"target tx bytes:%d\\n\", pmccadapriv->mcc_target_tx_bytes_to_port);\n\tRTW_INFO(\"**********************************\\n\");\n\n\tpmccobjpriv->iface[pmccadapriv->order] = padapter;\n\t#ifdef CONFIG_MCC_PHYDM_OFFLOAD\n\trtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_RF_CH, NULL);\n\t#endif\n\n}\n\nstatic void rtw_hal_mcc_rqt_tsf(PADAPTER padapter, u64 *out_tsf)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);\n\tPADAPTER order0_iface = NULL;\n\tPADAPTER order1_iface = NULL;\n\tstruct submit_ctx *tsf_req_sctx = NULL;\n\tenum _hw_port tsfx = MAX_HW_PORT;\n\tenum _hw_port tsfy = MAX_HW_PORT;\n\tu8 cmd[H2C_MCC_RQT_TSF_LEN] = {0};\n\n\t_enter_critical_mutex(&mccobjpriv->mcc_tsf_req_mutex, NULL);\n\n\torder0_iface = mccobjpriv->iface[0];\n\torder1_iface = mccobjpriv->iface[1];\n\n\ttsf_req_sctx = &mccobjpriv->mcc_tsf_req_sctx;\n\trtw_sctx_init(tsf_req_sctx, MCC_EXPIRE_TIME);\n\tmccobjpriv->mcc_tsf_req_sctx_order = 0;\n\ttsfx = rtw_hal_get_port(order0_iface);\n\ttsfy = rtw_hal_get_port(order1_iface);\n\n\tSET_H2CCMD_MCC_RQT_TSFX(cmd, tsfx);\n\tSET_H2CCMD_MCC_RQT_TSFY(cmd, tsfy);\n\n\trtw_hal_fill_h2c_cmd(padapter, H2C_MCC_RQT_TSF, H2C_MCC_RQT_TSF_LEN, cmd);\n\n\tif (!rtw_sctx_wait(tsf_req_sctx, __func__))\n\t\tRTW_INFO(FUNC_ADPT_FMT\": wait for mcc tsf req C2H time out\\n\", FUNC_ADPT_ARG(padapter));\n\n\tif (tsf_req_sctx->status  == RTW_SCTX_DONE_SUCCESS && out_tsf != NULL) {\n\t\tout_tsf[0] = order0_iface->mcc_adapterpriv.tsf;\n\t\tout_tsf[1] = order1_iface->mcc_adapterpriv.tsf;\n\t}\n\n\n\t_exit_critical_mutex(&mccobjpriv->mcc_tsf_req_mutex, NULL);\n}\n\nstatic u8 rtw_hal_mcc_check_start_time_is_valid(PADAPTER padapter, u8 case_num,\n\tu32 tsfdiff, s8 *upper_bound_0, s8 *lower_bound_0, s8 *upper_bound_1, s8 *lower_bound_1)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);\n\tu8 duration_0 = 0, duration_1 = 0;\n\ts8 final_upper_bound = 0, final_lower_bound = 0;\n\tu8 intersection =  _FALSE;\n\tu8 min_start_time = 5;\n\tu8 max_start_time = 95;\n\t\n\tduration_0 = mccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration;\n\tduration_1 = mccobjpriv->iface[1]->mcc_adapterpriv.mcc_duration;\n\n\tswitch(case_num) {\n\tcase 1:\n\t\t*upper_bound_0 = tsfdiff;\n\t\t*lower_bound_0 = tsfdiff - duration_1;\n\t\t*upper_bound_1 = 150 - duration_1;\n\t\t*lower_bound_1= 0;\n\t\tbreak;\n\tcase 2:\n\t\t*upper_bound_0 = tsfdiff + 100;\n\t\t*lower_bound_0 = tsfdiff + 100 - duration_1;\n\t\t*upper_bound_1 = 150 - duration_1;\n\t\t*lower_bound_1= 0;\n\t\tbreak;\n\tcase 3:\n\t\t*upper_bound_0 = tsfdiff + 50;\n\t\t*lower_bound_0 = tsfdiff + 50 - duration_1;\n\t\t*upper_bound_1 = 150 - duration_1;\n\t\t*lower_bound_1= 0;\n\t\tbreak;\n\tcase 4:\n\t\t*upper_bound_0 = tsfdiff;\n\t\t*lower_bound_0 = tsfdiff - duration_1;\n\t\t*upper_bound_1 = 150 - duration_1;\n\t\t*lower_bound_1= 0;\n\t\tbreak;\n\tcase 5:\n\t\t*upper_bound_0 = 200 - tsfdiff;\n\t\t*lower_bound_0 = 200 - tsfdiff - duration_1;\n\t\t*upper_bound_1 = 150 - duration_1;\n\t\t*lower_bound_1= 0;\n\t\tbreak;\n\tcase 6:\n\t\t*upper_bound_0 = tsfdiff - 50;\n\t\t*lower_bound_0 = tsfdiff - 50 - duration_1;\n\t\t*upper_bound_1 = 150 - duration_1;\n\t\t*lower_bound_1= 0;\n\t\tbreak;\n\tdefault:\n\t\tRTW_ERR(\"[MCC] %s: error case number(%d\\n)\", __func__, case_num);\n\t}\n\n\n\t/* check Intersection or not */\n\tif ((*lower_bound_1 >= *upper_bound_0) ||\n\t\t(*lower_bound_0 >= *upper_bound_1))\n\t\tintersection = _FALSE;\n\telse\n\t\tintersection = _TRUE;\n\n\tif (intersection) {\n\t\tif (*upper_bound_0 > *upper_bound_1)\n\t\t\tfinal_upper_bound = *upper_bound_1;\n\t\telse\n\t\t\tfinal_upper_bound = *upper_bound_0;\n\n\t\tif (*lower_bound_0 > *lower_bound_1)\n\t\t\tfinal_lower_bound = *lower_bound_0;\n\t\telse\n\t\t\tfinal_lower_bound = *lower_bound_1;\n\n\t\tmccobjpriv->start_time = (final_lower_bound + final_upper_bound) / 2;\n\n\t\t/* check start time less than 5ms, request by Pablo@SD1 */\n\t\tif (mccobjpriv->start_time <= min_start_time) {\n\t\t\tmccobjpriv->start_time = 6;\n\t\t\tif (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) {\n\t\t\t\tintersection = _FALSE;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\n\t\t/* check start time less than 95ms */\n\t\tif (mccobjpriv->start_time >= max_start_time) {\n\t\t\tmccobjpriv->start_time = 90;\n\t\t\tif (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) {\n\t\t\t\tintersection = _FALSE;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\t}\n\nexit:\n\treturn intersection;\n}\n\nstatic void rtw_hal_mcc_decide_duration(PADAPTER padapter)\n{\n\tstruct registry_priv *registry_par = &padapter->registrypriv;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);\n\tstruct mcc_adapter_priv *mccadapriv = NULL, *mccadapriv_order0 = NULL, *mccadapriv_order1 = NULL;\n\t_adapter *iface = NULL, *iface_order0 = NULL,  *iface_order1 = NULL;\n\tu8 duration = 0, i = 0, duration_time;\n\tu8 mcc_interval = 150;\n\n\tiface_order0 = mccobjpriv->iface[0];\n\tiface_order1 = mccobjpriv->iface[1];\n\tmccadapriv_order0 = &iface_order0->mcc_adapterpriv;\n\tmccadapriv_order1 = &iface_order1->mcc_adapterpriv;\n\t\n\tif (mccobjpriv->duration == 0) {\n\t\t/* default */\n\t\tduration = 30;/*(%)*/\n\t\tRTW_INFO(\"%s: mccobjpriv->duration=0, use default value(%d)\\n\",\n\t\t\t__FUNCTION__, duration);\n\t} else {\n\t\tduration = mccobjpriv->duration;/*(%)*/\n\t\tRTW_INFO(\"%s: mccobjpriv->duration=%d\\n\",\n\t\t\t__FUNCTION__, duration);\n\t}\n\n\tmccobjpriv->interval = mcc_interval;\n\tmccobjpriv->mcc_stop_threshold = 2000 * 4 / 300 - 6;\n\t/* convert % to ms, for primary adapter */\n\tduration_time = mccobjpriv->interval * duration / 100;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\n\t\tif (!iface)\n\t\t\tcontinue;\n\n\t\tmccadapriv = &iface->mcc_adapterpriv;\n\t\tif (mccadapriv->role == MCC_ROLE_MAX)\n\t\t\tcontinue;\n\n\t\tif (is_primary_adapter(iface))\n\t\t\tmccadapriv->mcc_duration = duration_time;\n\t\telse\n\t\t\tmccadapriv->mcc_duration = mccobjpriv->interval - duration_time;\n\t}\n\n\tRTW_INFO(\"[MCC]\"  FUNC_ADPT_FMT \" order 0 duration=%d\\n\", FUNC_ADPT_ARG(iface_order0), mccadapriv_order0->mcc_duration);\n\tRTW_INFO(\"[MCC]\"  FUNC_ADPT_FMT \" order 1 duration=%d\\n\", FUNC_ADPT_ARG(iface_order1), mccadapriv_order1->mcc_duration);\n}\n\nstatic u8 rtw_hal_mcc_update_timing_parameters(PADAPTER padapter, u8 force_update)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tu8 need_update = _FALSE;\n\tu8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);\n\tu8 ap_num = DEV_AP_NUM(dvobj);\n\n\n\t/* for STA+STA, modify policy table */\n\tif (starting_ap_num == 0 && ap_num == 0) {\n\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\t\tstruct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);\n\t\tstruct mcc_adapter_priv *pmccadapriv = NULL;\n\t\t_adapter *iface = NULL;\n\t\tu64 tsf[MAX_MCC_NUM] = {0};\n\t\tu64 tsf0 = 0, tsf1 = 0;\n\t\tu32 beaconperiod_0 = 0, beaconperiod_1 = 0, tsfdiff = 0;\n\t\ts8 upper_bound_0 = 0, lower_bound_0 = 0;\n\t\ts8 upper_bound_1 = 0, lower_bound_1 = 0;\n\t\tu8 valid = _FALSE;\n\t\tu8 case_num = 1;\n\t\tu8 i = 0;\n\t\t\n\t\t/* query TSF */\n\t\trtw_hal_mcc_rqt_tsf(padapter, tsf);\n\n\t\t/* selecet policy table according TSF diff */\n\t\ttsf0 = tsf[0];\n\t\tbeaconperiod_0 = pmccobjpriv->iface[0]->mlmepriv.cur_network.network.Configuration.BeaconPeriod;\n\t\ttsf0 = rtw_modular64(tsf0, (beaconperiod_0 * TU));\n\n\t\ttsf1 = tsf[1];\n\t\tbeaconperiod_1 = pmccobjpriv->iface[1]->mlmepriv.cur_network.network.Configuration.BeaconPeriod;\n\t\ttsf1 = rtw_modular64(tsf1, (beaconperiod_1 * TU));\n\n\t\tif (tsf0 > tsf1)\n\t\t\ttsfdiff = tsf0- tsf1;\n\t\telse\n\t\t\ttsfdiff = (tsf0 +  beaconperiod_0 * TU) - tsf1;\n\n\t\t/* convert to ms */\n\t\ttsfdiff = (tsfdiff / TU);\n\n\t\t/* force update*/\n\t\tif (force_update) {\n\t\t\tRTW_INFO(\"orig TSF0:%lld, orig TSF1:%lld\\n\",\n\t\t\t\tpmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);\n\t\t\tRTW_INFO(\"tsf0:%lld, tsf1:%lld\\n\", tsf0, tsf1);\n\t\t\tRTW_INFO(\"%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\\n\",\n\t\t\t\t__func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);\n\t\t\tpmccobjpriv->last_tsfdiff = tsfdiff;\n\t\t\tneed_update = _TRUE;\n\t\t} else {\n\t\t\tif (pmccobjpriv->last_tsfdiff > tsfdiff) {\n\t\t\t\t/* last tsfdiff - current tsfdiff > THRESHOLD, update parameters */\n\t\t\t\tif (pmccobjpriv->last_tsfdiff > (tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) {\n\t\t\t\t\tRTW_INFO(\"orig TSF0:%lld, orig TSF1:%lld\\n\",\n\t\t\t\t\t\tpmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);\n\t\t\t\t\tRTW_INFO(\"tsf0:%lld, tsf1:%lld\\n\", tsf0, tsf1);\n\t\t\t\t\tRTW_INFO(\"%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\\n\",\n\t\t\t\t\t\t__func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);\n\n\t\t\t\t\tpmccobjpriv->last_tsfdiff = tsfdiff;\n\t\t\t\t\tneed_update = _TRUE;\n\t\t\t\t} else {\n\t\t\t\t\tneed_update = _FALSE;\n\t\t\t\t}\n\t\t\t} else if (tsfdiff > pmccobjpriv->last_tsfdiff){\n\t\t\t\t/* current tsfdiff - last tsfdiff > THRESHOLD, update parameters */\n\t\t\t\tif (tsfdiff > (pmccobjpriv->last_tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) {\n\t\t\t\t\tRTW_INFO(\"orig TSF0:%lld, orig TSF1:%lld\\n\",\n\t\t\t\t\t\tpmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);\n\t\t\t\t\tRTW_INFO(\"tsf0:%lld, tsf1:%lld\\n\", tsf0, tsf1);\n\t\t\t\t\tRTW_INFO(\"%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\\n\",\n\t\t\t\t\t\t__func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);\n\n\t\t\t\t\tpmccobjpriv->last_tsfdiff = tsfdiff;\n\t\t\t\t\tneed_update = _TRUE;\n\t\t\t\t} else {\n\t\t\t\t\tneed_update = _FALSE;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tneed_update = _FALSE;\n\t\t\t}\n\t\t}\n\n\t\tif (need_update == _FALSE)\n\t\t\tgoto exit;\n\n\t\trtw_hal_mcc_decide_duration(padapter);\n\n\t\tif (tsfdiff <= 50) {\n\t\n\t\t\t/* RX TBTT 0 */\n\t\t\tcase_num = 1;\n\t\t\tvalid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,\n\t\t\t\t&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);\n\n\t\t\tif (valid)\n\t\t\t\tgoto valid_result;\n\t\n\t\t\t/* RX TBTT 1 */\n\t\t\tcase_num = 2;\n\t\t\tvalid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,\n\t\t\t\t&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);\n\n\t\t\tif (valid)\n\t\t\t\tgoto valid_result;\n\t\t\t\n\t\t\t/* RX TBTT 2 */\n\t\t\tcase_num = 3;\n\t\t\tvalid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,\n\t\t\t\t&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);\n\n\t\t\tif (valid)\n\t\t\t\tgoto valid_result;\n\n\t\t\tif (valid == _FALSE) {\n\t\t\t\tRTW_INFO(\"[MCC] do not find fit start time\\n\");\n\t\t\t\tRTW_INFO(\"[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\\n\",\n\t\t\t\t\ttsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval);\n\n\t\t\t}\n\n\t\t} else {\n\n\t\t\t/* RX TBTT 0 */\n\t\t\tcase_num = 4;\n\t\t\tvalid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,\n\t\t\t\t&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);\n\n\t\t\tif (valid)\n\t\t\t\tgoto valid_result;\n\t\t\t\n\t\t\t\n\t\t\t/* RX TBTT 1 */\n\t\t\tcase_num = 5;\n\t\t\tvalid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,\n\t\t\t\t&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);\n\n\t\t\tif (valid)\n\t\t\t\tgoto valid_result;\n\n\t\t\t\n\t\t\t/* RX TBTT 2 */\n\t\t\tcase_num = 6;\n\t\t\tvalid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,\n\t\t\t\t&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);\n\n\t\t\tif (valid)\n\t\t\t\tgoto valid_result;\n\n\t\t\tif (valid == _FALSE) {\n\t\t\t\tRTW_INFO(\"[MCC] do not find fit start time\\n\");\n\t\t\t\tRTW_INFO(\"[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\\n\",\n\t\t\t\t\ttsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval);\n\t\t\t}\n\t\t}\n\n\t\t\n\n\tvalid_result:\n\t\tRTW_INFO(\"********************\\n\");\n\t\tRTW_INFO(\"%s: case_num:%d, start time:%d\\n\",\n\t\t\t\t__func__, case_num, pmccobjpriv->start_time);\n\t\tRTW_INFO(\"%s: upper_bound_0:%d, lower_bound_0:%d\\n\",\n\t\t\t\t__func__, upper_bound_0, lower_bound_0);\n\t\tRTW_INFO(\"%s: upper_bound_1:%d, lower_bound_1:%d\\n\",\n\t\t\t\t__func__, upper_bound_1, lower_bound_1);\n\t\t\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tif (iface == NULL)\n\t\t\t\tcontinue;\n\n\t\t\tpmccadapriv = &iface->mcc_adapterpriv;\n\t\t\tpmccadapriv = &iface->mcc_adapterpriv;\n\t\t\tif (pmccadapriv->role == MCC_ROLE_MAX)\n\t\t\t\tcontinue;\n#if 0\n\t\t\tif (pmccadapriv->order == 0) {\n\t\t\t\tpmccadapriv->mcc_duration = mcc_duration;\n\t\t\t} else if (pmccadapriv->order == 1) {\n\t\t\t\tpmccadapriv->mcc_duration = mcc_interval - mcc_duration;\n\t\t\t} else {\n\t\t\t\tRTW_INFO(\"[MCC] not support >= 3 interface\\n\");\n\t\t\t\trtw_warn_on(1);\n\t\t\t}\n#endif\n\t\t\tRTW_INFO(\"********************\\n\");\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\": order:%d, role:%d\\n\",\n\t\t\t\tFUNC_ADPT_ARG(iface), pmccadapriv->order, pmccadapriv->role);\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\": mcc duration:%d, target tx bytes:%d\\n\",\n\t\t\t\tFUNC_ADPT_ARG(iface), pmccadapriv->mcc_duration, pmccadapriv->mcc_target_tx_bytes_to_port);\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\": mgmt queue macid:%d, bitmap:0x%02x\\n\",\n\t\t\t\tFUNC_ADPT_ARG(iface), pmccadapriv->mgmt_queue_macid, pmccadapriv->mcc_macid_bitmap);\n\t\t\tRTW_INFO(\"********************\\n\");\n\t\t}\n\t\t\n\t}\nexit:\n\treturn need_update;\n}\n\nstatic u8 rtw_hal_decide_mcc_role(PADAPTER padapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\t_adapter *iface = NULL;\n\tstruct mcc_adapter_priv *pmccadapriv = NULL;\n\tstruct wifidirect_info *pwdinfo = NULL;\n\tstruct mlme_priv *pmlmepriv = NULL;\n\tu8 ret = _SUCCESS, i = 0;\n\tu8 order = 1;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface == NULL)\n\t\t\tcontinue;\n\n\t\tpmccadapriv = &iface->mcc_adapterpriv;\n\t\tpwdinfo = &iface->wdinfo;\n\n\t\tif (MLME_IS_GO(iface))\n\t\t\tpmccadapriv->role = MCC_ROLE_GO;\n\t\telse if (MLME_IS_AP(iface))\n\t\t\tpmccadapriv->role = MCC_ROLE_AP;\n\t\telse if (MLME_IS_GC(iface))\n\t\t\tpmccadapriv->role = MCC_ROLE_GC;\n\t\telse if (MLME_IS_STA(iface)) {\n\t\t\tif (MLME_IS_LINKING(iface) || MLME_IS_ASOC(iface))\n\t\t\t\tpmccadapriv->role = MCC_ROLE_STA;\n\t\t\telse {\n\t\t\t\t/* bypass non-linked/non-linking interface */\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" mlme state:0x%2x\\n\",\n\t\t\t\t\tFUNC_ADPT_ARG(iface), MLME_STATE(iface));\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t} else {\n\t\t\t/* bypass non-linked/non-linking interface */\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" P2P Role:%d, mlme state:0x%2x\\n\",\n\t\t\t\tFUNC_ADPT_ARG(iface), pwdinfo->role, MLME_STATE(iface));\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (padapter == iface) {\n\t\t\t/* current adapter is order 0 */\n\t\t\trtw_hal_config_mcc_role_setting(iface, 0);\n\t\t} else {\n\t\t\trtw_hal_config_mcc_role_setting(iface, order);\n\t\t\torder ++;\n\t\t}\n\t}\n\n\trtw_hal_mcc_update_timing_parameters(padapter, _TRUE);\nexit:\n\treturn ret;\n}\n\nstatic void rtw_hal_construct_CTS(PADAPTER padapter, u8 *pframe, u32 *pLength)\n{\n\tu8 broadcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\n\t/* frame type, length = 1*/\n\tset_frame_sub_type(pframe, WIFI_RTS);\n\n\t/* frame control flag, length = 1 */\n\t*(pframe + 1) = 0;\n\n\t/* frame duration, length = 2 */\n\t*(pframe + 2) = 0x00;\n\t*(pframe + 3) = 0x78;\n\n\t/* frame recvaddr, length = 6 */\n\t_rtw_memcpy((pframe + 4), broadcast_addr, ETH_ALEN);\n\t_rtw_memcpy((pframe + 4 + ETH_ALEN), adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy((pframe + 4 + ETH_ALEN*2), adapter_mac_addr(padapter), ETH_ALEN);\n\t*pLength = 22;\n}\n\n/* avoid wrong information for power limit */\nvoid rtw_hal_mcc_upadate_chnl_bw(_adapter *padapter, u8 ch, u8 ch_offset, u8 bw, u8 print)\n{\n\n\tu8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tPHAL_DATA_TYPE\thal = GET_HAL_DATA(padapter);\n\tu8 cch_160, cch_80, cch_40, cch_20;\n\n\tcenter_ch = rtw_get_center_ch(ch, bw, ch_offset);\n\n\tif (bw == CHANNEL_WIDTH_80) {\n\t\tif (center_ch > ch)\n\t\t\tchnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\telse if (center_ch < ch)\n\t\t\tchnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\telse\n\t\t\tchnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t}\n\n\t/* set Channel */\n\t/* saved channel/bw info */\n\trtw_set_oper_ch(padapter, ch);\n\trtw_set_oper_bw(padapter, bw);\n\trtw_set_oper_choffset(padapter, ch_offset);\n\n\tcch_80 = bw == CHANNEL_WIDTH_80 ? center_ch : 0;\n\tcch_40 = bw == CHANNEL_WIDTH_40 ? center_ch : 0;\n\tcch_20 = bw == CHANNEL_WIDTH_20 ? center_ch : 0;\n\n\tif (cch_80 != 0)\n\t\tcch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, chnl_offset80);\n\tif (cch_40 != 0)\n\t\tcch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, ch_offset);\n\n\n\thal->cch_80 = cch_80;\n\thal->cch_40 = cch_40;\n\thal->cch_20 = cch_20;\n\thal->current_channel = center_ch;\n\thal->CurrentCenterFrequencyIndex1 = center_ch;\n\thal->current_channel_bw = bw;\n\thal->nCur40MhzPrimeSC = ch_offset;\n\thal->nCur80MhzPrimeSC = chnl_offset80;\n\thal->current_band_type = ch > 14 ? BAND_ON_5G:BAND_ON_2_4G;\n\n\tif (print) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u), band:%s\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), center_ch, ch_width_str(bw)\n\t\t\t, ch_offset, chnl_offset80\n\t\t\t, hal->cch_80, hal->cch_40, hal->cch_20\n\t\t\t, band_str(hal->current_band_type));\n\t}\n}\n\nu8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index,\n\tu8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num)\n{\n\tu32 len = 0;\n\t_adapter *iface = NULL;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);\n\tstruct mlme_ext_info *pmlmeinfo = NULL;\n\tstruct mlme_ext_priv *pmlmeext = NULL;\n\tstruct hal_com_data *hal = GET_HAL_DATA(adapter);\n\tstruct mcc_adapter_priv *mccadapriv = NULL;\n\tu8 ret = _SUCCESS, i = 0, j  =0, order = 0, CurtPktPageNum = 0;\n\tu8 *start = NULL;\n\tu8 path = RF_PATH_A;\n\n\tif (page_num) {\n#ifdef CONFIG_MCC_MODE_V2\n\t\tif (!hal->RegIQKFWOffload)\n\t\t\tRTW_WARN(\"[MCC] must enable FW IQK for New IC\\n\");\n#endif /* CONFIG_MCC_MODE_V2 */\n\t\t*total_page_num += (2 * MAX_MCC_NUM+ 1);\n\t\tRTW_INFO(\"[MCC] allocate mcc rsvd page num = %d\\n\", *total_page_num);\n\t\tgoto exit;\n\t}\n\n\t/* check proccess mcc start setting */\n\tif (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_PROCESS_MCC_START_SETTING)) {\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface == NULL)\n\t\t\tcontinue;\n\n\t\tmccadapriv = &iface->mcc_adapterpriv;\n\t\tif (mccadapriv->role == MCC_ROLE_MAX)\n\t\t\tcontinue;\n\n\t\torder = mccadapriv->order;\n\t\tpmccobjpriv->mcc_loc_rsvd_paga[order] = *total_page_num;\n\n\t\tswitch (mccadapriv->role) {\n\t\tcase MCC_ROLE_STA:\n\t\tcase MCC_ROLE_GC:\n\t\t\t/* Build NULL DATA */\n\t\t\tRTW_INFO(\"LocNull(order:%d): %d\\n\"\n\t\t\t\t, order, pmccobjpriv->mcc_loc_rsvd_paga[order]);\n\t\t\tlen = 0;\n\n\t\t\trtw_hal_construct_NullFunctionData(iface\n\t\t\t\t, &pframe[*index], &len, _FALSE, 0, 0, _FALSE);\n\t\t\trtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc],\n\t\t\t\tlen, _FALSE, _FALSE, _FALSE);\n\n\t\t\tCurtPktPageNum = (u8)PageNum(tx_desc + len, page_size);\n\t\t\t*total_page_num += CurtPktPageNum;\n\t\t\t*index += (CurtPktPageNum * page_size);\n\t\t\tRSVD_PAGE_CFG(\"LocNull\", CurtPktPageNum, *total_page_num, *index);\n\t\t\tbreak;\n\t\tcase MCC_ROLE_AP:\n\t\t\t/* Bulid CTS */\n\t\t\tRTW_INFO(\"LocCTS(order:%d): %d\\n\"\n\t\t\t\t, order, pmccobjpriv->mcc_loc_rsvd_paga[order]);\n\n\t\t\tlen = 0;\n\t\t\trtw_hal_construct_CTS(iface, &pframe[*index], &len);\n\t\t\trtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc],\n\t\t\t\tlen, _FALSE, _FALSE, _FALSE);\n\n\t\t\tCurtPktPageNum = (u8)PageNum(tx_desc + len, page_size);\n\t\t\t*total_page_num += CurtPktPageNum;\n\t\t\t*index += (CurtPktPageNum * page_size);\n\t\t\tRSVD_PAGE_CFG(\"LocCTS\", CurtPktPageNum, *total_page_num, *index);\n\t\t\tbreak;\n\t\tcase MCC_ROLE_GO:\n\t\t/* To DO */\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\": unknown role = %d\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(iface), mccadapriv->role);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tfor (i = 0; i < MAX_MCC_NUM; i++) {\n\t\tu8 center_ch = 0, ch = 0, bw = 0, bw_offset = 0;\n\t\tu8 power_index = 0;\n\t\tu8 rate_array_sz = 0;\n\t\tu8 *rates = NULL;\n\t\tu8 rate = 0;\n\t\tu8 shift = 0;\n\t\tu32 power_index_4bytes = 0;\n\t\tu8 total_rate = 0;\n\t\tu8 *total_rate_offset = NULL;\n\n\t\tiface = pmccobjpriv->iface[i];\n\t\tpmlmeext = &iface->mlmeextpriv;\n\t\tch = pmlmeext->cur_channel;\n\t\tbw = pmlmeext->cur_bwmode;\n\t\tbw_offset = pmlmeext->cur_ch_offset;\n\t\tcenter_ch = rtw_get_center_ch(ch, bw, bw_offset);\n\t\trtw_hal_mcc_upadate_chnl_bw(iface, ch, bw_offset, bw, _TRUE);\n\n\t\tstart = &pframe[*index - tx_desc];\n\t\t_rtw_memset(start, 0, page_size);\n\t\tpmccobjpriv->mcc_pwr_idx_rsvd_page[i] = *total_page_num;\n\t\tRTW_INFO(ADPT_FMT\" order:%d, pwr_idx_rsvd_page location[%d]: %d\\n\",\n\t\t\tADPT_ARG(iface), mccadapriv->order,\n\t\t\ti, pmccobjpriv->mcc_pwr_idx_rsvd_page[i]);\n\n\t\ttotal_rate_offset = start;\n\t\t\t\n\t\tfor (path = RF_PATH_A; path < hal->NumTotalRFPath; ++path) {\n\t\t\ttotal_rate = 0;\n\t\t\t/* PATH A for 0~63 byte, PATH B for 64~127 byte*/\n\t\t\tif (path == RF_PATH_A)\n\t\t\t\tstart = total_rate_offset + 1;\n\t\t\telse if (path == RF_PATH_B)\n\t\t\t\tstart = total_rate_offset + 64;\n\t\t\telse {\n\t\t\t\tRTW_INFO(\"[MCC] %s: unknow RF PATH(%d)\\n\", __func__, path);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* CCK */\n\t\t\tif (ch <= 14) {\n\t\t\t\trate_array_sz = rates_by_sections[CCK].rate_num;\n\t\t\t\trates = rates_by_sections[CCK].rates;\n\t\t\t\tfor (j = 0; j < rate_array_sz; ++j) {\n\t\t\t\t\tpower_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);\n\t\t\t\t\trate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);\n\n\t\t\t\t\tshift = rate % 4;\n\t\t\t\t\tif (shift == 0) {\n\t\t\t\t\t\t*start = rate;\n\t\t\t\t\t\tstart++;\n\t\t\t\t\t\ttotal_rate++;\n\n\t\t\t\t\t\t#ifdef DBG_PWR_IDX_RSVD_PAGE\n\t\t\t\t\t\tRTW_INFO(\"TXPWR(\"ADPT_FMT\"): [%c][%s]ch:%u, %s, pwr_idx:%u\\n\",\n\t\t\t\t\t\t\tADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),\n\t\t\t\t\t\t\tcenter_ch, MGN_RATE_STR(rates[j]), power_index);\n\t\t\t\t\t\t#endif\n\t\t\t\t\t}\n\n\t\t\t\t\t*start = power_index;\n\t\t\t\t\tstart++;\n\n\t\t\t\t\t#ifdef DBG_PWR_IDX_RSVD_PAGE\n\t\t\t\t\tRTW_INFO(\"TXPWR(\"ADPT_FMT\"): [%c][%s]ch:%u, %s, pwr_idx:%u\\n\",\n\t\t\t\t\t\tADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),\n\t\t\t\t\t\tcenter_ch, MGN_RATE_STR(rates[j]), power_index);\n\n\t\t\t\t\t\n\t\t\t\t\tshift = rate % 4;\n\t\t\t\t\tpower_index_4bytes |= ((power_index & 0xff) << (shift * 8));\n\t\t\t\t\tif (shift == 3) {\n\t\t\t\t\t\trate = rate - 3;\n\t\t\t\t\t\tRTW_INFO(\"(index:0x%02x, rfpath:%d, rate:0x%02x)\\n\", index, path, rate);\n\t\t\t\t\t\tpower_index_4bytes = 0;\n\t\t\t\t\t\ttotal_rate++;\n\t\t\t\t\t}\n\t\t\t\t\t#endif\n\t\t\t\t\t\t\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* OFDM */\n\t\t\trate_array_sz = rates_by_sections[OFDM].rate_num;\n\t\t\trates = rates_by_sections[OFDM].rates;\n\t\t\tfor (j = 0; j < rate_array_sz; ++j) {\n\t\t\t\tpower_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);\n\t\t\t\trate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);\n\n\t\t\t\tshift = rate % 4;\n\t\t\t\tif (shift == 0) {\n\t\t\t\t\t*start = rate;\n\t\t\t\t\tstart++;\n\t\t\t\t\ttotal_rate++;\n\n\t\t\t\t\t#ifdef DBG_PWR_IDX_RSVD_PAGE\n\t\t\t\t\tRTW_INFO(\"TXPWR(\"ADPT_FMT\"): [%c][%s]ch:%u, %s, pwr_idx:%u\\n\",\n\t\t\t\t\t\tADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),\n\t\t\t\t\t\tcenter_ch, MGN_RATE_STR(rates[j]), power_index);\n\t\t\t\t\t#endif\n\n\t\t\t\t}\n\n\t\t\t\t*start = power_index;\n\t\t\t\tstart++;\n\n\t\t\t\t#ifdef DBG_PWR_IDX_RSVD_PAGE\n\t\t\t\tRTW_INFO(\"TXPWR(\"ADPT_FMT\"): [%c][%s]ch:%u, %s, pwr_idx:%u\\n\",\n\t\t\t\t\tADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),\n\t\t\t\t\tcenter_ch, MGN_RATE_STR(rates[j]), power_index);\n\n\t\t\t\tshift = rate % 4;\n\t\t\t\tpower_index_4bytes |= ((power_index & 0xff) << (shift * 8));\n\t\t\t\tif (shift == 3) {\n\t\t\t\t\trate = rate - 3;\n\t\t\t\t\tRTW_INFO(\"(index:0x%02x, rfpath:%d, rate:0x%02x)\\n\", index, path, rate);\n\t\t\t\t\tpower_index_4bytes = 0;\n\t\t\t\t\ttotal_rate++;\n\t\t\t\t}\n\t\t\t\t#endif\n\t\t\t}\n\n\t\t\t/* HT_MCS0_MCS7 */\n\t\t\trate_array_sz = rates_by_sections[HT_MCS0_MCS7].rate_num;\n\t\t\trates = rates_by_sections[HT_MCS0_MCS7].rates;\n\t\t\tfor (j = 0; j < rate_array_sz; ++j) {\n\t\t\t\tpower_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);\n\t\t\t\trate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);\n\n\t\t\t\tshift = rate % 4;\n\t\t\t\tif (shift == 0) {\n\t\t\t\t\t*start = rate;\n\t\t\t\t\tstart++;\n\t\t\t\t\ttotal_rate++;\n\n\t\t\t\t\t#ifdef DBG_PWR_IDX_RSVD_PAGE\n\t\t\t\t\tRTW_INFO(\"TXPWR(\"ADPT_FMT\"): [%c][%s]ch:%u, %s, pwr_idx:%u\\n\",\n\t\t\t\t\t\tADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),\n\t\t\t\t\t\tcenter_ch, MGN_RATE_STR(rates[j]), power_index);\n\t\t\t\t\t#endif\n\n\t\t\t\t}\n\n\t\t\t\t*start = power_index;\n\t\t\t\tstart++;\n\n\t\t\t\t#ifdef DBG_PWR_IDX_RSVD_PAGE\n\t\t\t\tRTW_INFO(\"TXPWR(\"ADPT_FMT\"): [%c][%s]ch:%u, %s, pwr_idx:%u\\n\",\n\t\t\t\t\tADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),\n\t\t\t\t\tcenter_ch, MGN_RATE_STR(rates[j]), power_index);\n\n\t\t\t\tshift = rate % 4;\n\t\t\t\tpower_index_4bytes |= ((power_index & 0xff) << (shift * 8));\n\t\t\t\tif (shift == 3) {\n\t\t\t\t\trate = rate - 3;\n\t\t\t\t\tRTW_INFO(\"(index:0x%02x, rfpath:%d, rate:0x%02x)\\n\", index, path, rate);\n\t\t\t\t\tpower_index_4bytes = 0;\n\t\t\t\t\ttotal_rate++;\n\t\t\t\t}\n\t\t\t\t#endif\n\t\t\t}\n\n\t\t\t/* HT_MCS8_MCS15 */\n\t\t\trate_array_sz = rates_by_sections[HT_MCS8_MCS15].rate_num;\n\t\t\trates = rates_by_sections[HT_MCS8_MCS15].rates;\n\t\t\tfor (j = 0; j < rate_array_sz; ++j) {\n\t\t\t\tpower_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);\n\t\t\t\trate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);\n\n\t\t\t\tshift = rate % 4;\n\t\t\t\tif (shift == 0) {\n\t\t\t\t\t*start = rate;\n\t\t\t\t\tstart++;\n\t\t\t\t\ttotal_rate++;\n\n\t\t\t\t\t#ifdef DBG_PWR_IDX_RSVD_PAGE\n\t\t\t\t\tRTW_INFO(\"TXPWR(\"ADPT_FMT\"): [%c][%s]ch:%u, %s, pwr_idx:%u\\n\",\n\t\t\t\t\t\tADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),\n\t\t\t\t\t\tcenter_ch, MGN_RATE_STR(rates[j]), power_index);\n\t\t\t\t\t#endif\n\t\t\t\t}\n\n\t\t\t\t*start = power_index;\n\t\t\t\tstart++;\n\n\t\t\t\t#ifdef DBG_PWR_IDX_RSVD_PAGE\n\t\t\t\tRTW_INFO(\"TXPWR(\"ADPT_FMT\"): [%c][%s]ch:%u, %s, pwr_idx:%u\\n\",\n\t\t\t\t\tADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),\n\t\t\t\t\tcenter_ch, MGN_RATE_STR(rates[j]), power_index);\n\t\t\t\t\n\t\t\t\tshift = rate % 4;\n\t\t\t\tpower_index_4bytes |= ((power_index & 0xff) << (shift * 8));\n\t\t\t\tif (shift == 3) {\n\t\t\t\t\trate = rate - 3;\n\t\t\t\t\tRTW_INFO(\"(index:0x%02x, rfpath:%d, rate:0x%02x)\\n\", index, path, rate);\n\t\t\t\t\tpower_index_4bytes = 0;\n\t\t\t\t\ttotal_rate++;\n\t\t\t\t}\n\t\t\t\t#endif\n\t\t\t}\n\n\t\t\t/* VHT_1SSMCS0_1SSMCS9 */\n\t\t\trate_array_sz = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rate_num;\n\t\t\trates = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rates;\n\t\t\tfor (j = 0; j < rate_array_sz; ++j) {\n\t\t\t\tpower_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);\n\t\t\t\trate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);\n\n\t\t\t\tshift = rate % 4;\n\t\t\t\tif (shift == 0) {\n\t\t\t\t\t*start = rate;\n\t\t\t\t\tstart++;\n\t\t\t\t\ttotal_rate++;\n\t\t\t\t\t#ifdef DBG_PWR_IDX_RSVD_PAGE\n\t\t\t\t\tRTW_INFO(\"TXPWR(\"ADPT_FMT\"): [%c][%s]ch:%u, %s, pwr_idx:0x%02x\\n\",\n\t\t\t\t\t\tADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),\n\t\t\t\t\t\tcenter_ch, MGN_RATE_STR(rates[j]), power_index);\n\t\t\t\t\t#endif\n\t\t\t\t}\n\t\t\t\t*start = power_index;\n\t\t\t\tstart++;\n\t\t\t\t#ifdef DBG_PWR_IDX_RSVD_PAGE\n\t\t\t\tRTW_INFO(\"TXPWR(\"ADPT_FMT\"): [%c][%s]ch:%u, %s, pwr_idx:%u\\n\",\n\t\t\t\t\tADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),\n\t\t\t\t\tcenter_ch, MGN_RATE_STR(rates[j]), power_index);\n\n\t\t\t\tshift = rate % 4;\n\t\t\t\tpower_index_4bytes |= ((power_index & 0xff) << (shift * 8));\n\t\t\t\tif (shift == 3) {\n\t\t\t\t\trate = rate - 3;\n\t\t\t\t\tRTW_INFO(\"(index:0x%02x, rfpath:%d, rate:0x%02x)\\n\", index, path, rate);\n\t\t\t\t\tpower_index_4bytes = 0;\n\t\t\t\t\ttotal_rate++;\n\t\t\t\t}\n\t\t\t\t#endif\n\t\t\t}\n\n\t\t\t/* VHT_2SSMCS0_2SSMCS9 */\n\t\t\trate_array_sz = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rate_num;\n\t\t\trates = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rates;\n\t\t\tfor (j = 0; j < rate_array_sz; ++j) {\n\t\t\t\tpower_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);\n\t\t\t\trate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);\n\n\t\t\t\tshift = rate % 4;\n\t\t\t\tif (shift == 0) {\n\t\t\t\t\t*start = rate;\n\t\t\t\t\tstart++;\n\t\t\t\t\ttotal_rate++;\n\t\t\t\t\t#ifdef DBG_PWR_IDX_RSVD_PAGE\n\t\t\t\t\tRTW_INFO(\"TXPWR(\"ADPT_FMT\"): [%c][%s]ch:%u, %s, pwr_idx:%u\\n\",\n\t\t\t\t\t\tADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),\n\t\t\t\t\t\tcenter_ch, MGN_RATE_STR(rates[j]), power_index);\n\t\t\t\t\t#endif\n\t\t\t\t}\n\t\t\t\t*start = power_index;\n\t\t\t\tstart++;\n\t\t\t\t#ifdef DBG_PWR_IDX_RSVD_PAGE\n\t\t\t\tRTW_INFO(\"TXPWR(\"ADPT_FMT\"): [%c][%s]ch:%u, %s, pwr_idx:%u\\n\",\n\t\t\t\t\tADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),\n\t\t\t\t\tcenter_ch, MGN_RATE_STR(rates[j]), power_index);\n\n\t\t\t\tshift = rate % 4;\n\t\t\t\tpower_index_4bytes |= ((power_index & 0xff) << (shift * 8));\n\t\t\t\tif (shift == 3) {\n\t\t\t\t\trate = rate - 3;\n\t\t\t\t\tRTW_INFO(\"(index:0x%02x, rfpath:%d, rate:0x%02x)\\n\", index, path, rate);\n\t\t\t\t\tpower_index_4bytes = 0;\n\t\t\t\t\t\ttotal_rate++;\n\t\t\t\t}\n\t\t\t\t#endif\n\t\t\t}\n\t\t\t\t\n\t\t}\n\t\t/*  total rate store in offset 0 */\n\t\t*total_rate_offset = total_rate;\n\n#ifdef DBG_PWR_IDX_RSVD_PAGE\n\t\t\tRTW_INFO(\"total_rate=%d\\n\", total_rate);\n\t\t\tRTW_INFO(\" =======================\"ADPT_FMT\"===========================\\n\", ADPT_ARG(iface));\n\t\t\tRTW_INFO_DUMP(\"\\n\", total_rate_offset, 128);\n\t\t\tRTW_INFO(\" ==================================================\\n\");\n#endif\n\n\t\t\tCurtPktPageNum = 1;\n\t\t\t*total_page_num += CurtPktPageNum;\n\t\t\t*index += (CurtPktPageNum * page_size);\n\t\t\tRSVD_PAGE_CFG(\"mcc_pwr_idx_rsvd_page\", CurtPktPageNum, *total_page_num, *index);\n\t\t}\n\nexit:\n\treturn ret;\n}\n\n/*\n* 1. Download MCC rsvd page\n* 2. Re-Download beacon after download rsvd page\n*/\nstatic void rtw_hal_set_fw_mcc_rsvd_page(PADAPTER padapter)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\tstruct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tPADAPTER port0_iface = dvobj_get_port0_adapter(dvobj);\n\tPADAPTER iface = NULL;\n\tstruct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);\n\tu8 mstatus = RT_MEDIA_CONNECT, i = 0;\n\n\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n\n\trtw_hal_set_hwreg(port0_iface, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus));\n\n\t/* Re-Download beacon */\n\tfor (i = 0; i < MAX_MCC_NUM; i++) {\n\t\tiface = pmccobjpriv->iface[i];\n\t\tif (iface == NULL)\n\t\t\tcontinue;\n\n\t\tpmccadapriv = &iface->mcc_adapterpriv;\n\n\t\tif (pmccadapriv->role == MCC_ROLE_AP\n\t\t\t|| pmccadapriv->role == MCC_ROLE_GO) {\n\t\t\ttx_beacon_hdl(iface, NULL);\n\t\t}\n\t}\n}\n\nstatic void rtw_hal_set_mcc_rsvdpage_cmd(_adapter *padapter)\n{\n\tu8 cmd[H2C_MCC_LOCATION_LEN] = {0}, i = 0, order = 0;\n\t_adapter *iface = NULL;\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);\n\n\tSET_H2CCMD_MCC_PWRIDX_OFFLOAD_EN(cmd, _TRUE);\n\tSET_H2CCMD_MCC_PWRIDX_OFFLOAD_RFNUM(cmd, hal->NumTotalRFPath);\n\tfor (order = 0; order < MAX_MCC_NUM; order++) {\n\t\tiface = pmccobjpriv->iface[i];\n\n\t\tSET_H2CCMD_MCC_RSVDPAGE_LOC((cmd + order), pmccobjpriv->mcc_loc_rsvd_paga[order]);\n\t\tSET_H2CCMD_MCC_PWRIDX_RSVDPAGE_LOC ((cmd + order), pmccobjpriv->mcc_pwr_idx_rsvd_page[order]);\n\t}\n\n#ifdef CONFIG_MCC_MODE_DEBUG\n\tRTW_INFO(\"=========================\\n\");\n\tRTW_INFO(\"MCC RSVD PAGE LOC:\\n\");\n\tfor (i = 0; i < H2C_MCC_LOCATION_LEN; i++)\n\t\tpr_dbg(\"0x%x \", cmd[i]);\n\tpr_dbg(\"\\n\");\n\tRTW_INFO(\"=========================\\n\");\n#endif /* CONFIG_MCC_MODE_DEBUG */\n\n\trtw_hal_fill_h2c_cmd(padapter, H2C_MCC_LOCATION, H2C_MCC_LOCATION_LEN, cmd);\n}\n\nstatic void rtw_hal_set_mcc_time_setting_cmd(PADAPTER padapter)\n{\n\tstruct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);\n\tu8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0};\n\tu8 fw_eable = 1;\n\tu8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME;\n\tu8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);\n\tu8 ap_num = DEV_AP_NUM(dvobj);\t\n\n\tif (starting_ap_num == 0 && ap_num == 0)\n\t\t/* For STA+GC/STA+STA, TSF of GC/STA does not need to sync from TSF of other STA/GC */\n\t\tfw_eable = 0;\n\telse\n\t\t/* Only for STA+GO/STA+AP, TSF of AP/GO need to sync from TSF of STA */\n\t\tfw_eable = 1;\n\n\tif (fw_eable == 1) {\n\t\tPADAPTER order0_iface = NULL;\n\t\tPADAPTER order1_iface = NULL;\n\t\tu8 policy_idx = mccobjpriv->policy_index;\n\t\tu8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];\n\t\tu8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];\n\t\tu8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX];\n\t\tu8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX];\n\t\tu8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX];\n\t\tenum _hw_port tsf_bsae_port = MAX_HW_PORT;\n\t\tenum _hw_port tsf_sync_port = MAX_HW_PORT;\n\t\torder0_iface = mccobjpriv->iface[0];\n\t\torder1_iface = mccobjpriv->iface[1];\n\n\t\ttsf_bsae_port = rtw_hal_get_port(order1_iface);\n\t\ttsf_sync_port = rtw_hal_get_port(order0_iface);\n\t\t\n\t\t/* FW set enable */\n\t\tSET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, fw_eable);\n\t\t/* TSF Sync offset */\n\t\tSET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset);\n\t\t/* start time offset */\n\t\tSET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0));\n\t\t/* interval */\n\t\tSET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);\n\t\t/* Early time to inform driver by C2H before switch channel */\n\t\tSET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);\n\t\t/* Port0 sync from Port1, not support multi-port */\n\t\tSET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, tsf_bsae_port);\n\t\tSET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, tsf_sync_port);\n\t} else {\n\t\t/* start time offset */\n\t\tSET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, mccobjpriv->start_time);\n\t\t/* interval */\n\t\tSET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, mccobjpriv->interval);\n\t\t/* Early time to inform driver by C2H before switch channel */\n\t\tSET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);\n\t}\n\n#ifdef CONFIG_MCC_MODE_DEBUG\n\t{\n\t\tu8 i = 0;\n\n\t\tRTW_INFO(\"=========================\\n\");\n\t\tRTW_INFO(\"NoA:\\n\");\n\t\tfor (i = 0; i < H2C_MCC_TIME_SETTING_LEN; i++)\n\t\t\tpr_dbg(\"0x%x \", cmd[i]);\n\t\tpr_dbg(\"\\n\");\n\t\tRTW_INFO(\"=========================\\n\");\n\t}\n#endif /* CONFIG_MCC_MODE_DEBUG */\n\n\trtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd);\n}\n\nstatic void rtw_hal_set_mcc_IQK_offload_cmd(PADAPTER padapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);\n\tstruct mcc_adapter_priv *pmccadapriv = NULL;\n\t_adapter *iface = NULL;\n\tu8 cmd[H2C_MCC_IQK_PARAM_LEN] = {0}, bready = 0, i = 0, order = 0;\n\tu16 TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0;\n\tu8 total_rf_path = GET_HAL_DATA(padapter)->NumTotalRFPath;\n\tu8 rf_path_idx = 0, last_order = MAX_MCC_NUM - 1, last_rf_path_index = total_rf_path - 1;\n\n\t/* by order, last order & last_rf_path_index must set ready bit = 1 */\n\tfor (i = 0; i < MAX_MCC_NUM; i++) {\n\t\tiface = pmccobjpriv->iface[i];\n\t\tif (iface == NULL)\n\t\t\tcontinue;\n\n\t\tpmccadapriv = &iface->mcc_adapterpriv;\n\t\torder = pmccadapriv->order;\n\n\t\tfor (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx ++) {\n\n\t\t\t_rtw_memset(cmd, 0, H2C_MCC_IQK_PARAM_LEN);\n\t\t\tTX_X = pmccadapriv->mcc_iqk_arr[rf_path_idx].TX_X & 0x7ff;/* [10:0]  */\n\t\t\tTX_Y = pmccadapriv->mcc_iqk_arr[rf_path_idx].TX_Y & 0x7ff;/* [10:0]  */\n\t\t\tRX_X = pmccadapriv->mcc_iqk_arr[rf_path_idx].RX_X & 0x3ff;/* [9:0]  */\n\t\t\tRX_Y = pmccadapriv->mcc_iqk_arr[rf_path_idx].RX_Y & 0x3ff;/* [9:0]  */\n\n\t\t\t/* ready or not */\n\t\t\tif (order == last_order && rf_path_idx == last_rf_path_index)\n\t\t\t\tbready = 1;\n\t\t\telse\n\t\t\t\tbready = 0;\n\n\t\t\tSET_H2CCMD_MCC_IQK_READY(cmd, bready);\n\t\t\tSET_H2CCMD_MCC_IQK_ORDER(cmd, order);\n\t\t\tSET_H2CCMD_MCC_IQK_PATH(cmd, rf_path_idx);\n\n\t\t\t/* fill RX_X[7:0] to (cmd+1)[7:0] bitlen=8 */\n\t\t\tSET_H2CCMD_MCC_IQK_RX_L(cmd, (u8)(RX_X & 0xff));\n\t\t\t/* fill RX_X[9:8] to (cmd+2)[1:0] bitlen=2 */\n\t\t\tSET_H2CCMD_MCC_IQK_RX_M1(cmd, (u8)((RX_X >> 8) & 0x03));\n\t\t\t/* fill RX_Y[5:0] to (cmd+2)[7:2] bitlen=6 */\n\t\t\tSET_H2CCMD_MCC_IQK_RX_M2(cmd, (u8)(RX_Y & 0x3f));\n\t\t\t/* fill RX_Y[9:6] to (cmd+3)[3:0] bitlen=4 */\n\t\t\tSET_H2CCMD_MCC_IQK_RX_H(cmd, (u8)((RX_Y >> 6) & 0x0f));\n\n\n\t\t\t/* fill TX_X[7:0] to (cmd+4)[7:0] bitlen=8 */\n\t\t\tSET_H2CCMD_MCC_IQK_TX_L(cmd, (u8)(TX_X & 0xff));\n\t\t\t/* fill TX_X[10:8] to (cmd+5)[2:0] bitlen=3 */\n\t\t\tSET_H2CCMD_MCC_IQK_TX_M1(cmd, (u8)((TX_X >> 8) & 0x07));\n\t\t\t/* fill TX_Y[4:0] to (cmd+5)[7:3] bitlen=5 */\n\t\t\tSET_H2CCMD_MCC_IQK_TX_M2(cmd, (u8)(TX_Y & 0x1f));\n\t\t\t/* fill TX_Y[10:5] to (cmd+6)[5:0] bitlen=6 */\n\t\t\tSET_H2CCMD_MCC_IQK_TX_H(cmd, (u8)((TX_Y >> 5) & 0x3f));\n\n#ifdef CONFIG_MCC_MODE_DEBUG\n\t\t\tRTW_INFO(\"=========================\\n\");\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" IQK:\\n\", FUNC_ADPT_ARG(iface));\n\t\t\tRTW_INFO(\"TX_X: 0x%02x\\n\", TX_X);\n\t\t\tRTW_INFO(\"TX_Y: 0x%02x\\n\", TX_Y);\n\t\t\tRTW_INFO(\"RX_X: 0x%02x\\n\", RX_X);\n\t\t\tRTW_INFO(\"RX_Y: 0x%02x\\n\", RX_Y);\n\t\t\tRTW_INFO(\"cmd[0]:0x%02x\\n\", cmd[0]);\n\t\t\tRTW_INFO(\"cmd[1]:0x%02x\\n\", cmd[1]);\n\t\t\tRTW_INFO(\"cmd[2]:0x%02x\\n\", cmd[2]);\n\t\t\tRTW_INFO(\"cmd[3]:0x%02x\\n\", cmd[3]);\n\t\t\tRTW_INFO(\"cmd[4]:0x%02x\\n\", cmd[4]);\n\t\t\tRTW_INFO(\"cmd[5]:0x%02x\\n\", cmd[5]);\n\t\t\tRTW_INFO(\"cmd[6]:0x%02x\\n\", cmd[6]);\n\t\t\tRTW_INFO(\"=========================\\n\");\n#endif /* CONFIG_MCC_MODE_DEBUG */\n\n\t\t\trtw_hal_fill_h2c_cmd(padapter, H2C_MCC_IQK_PARAM, H2C_MCC_IQK_PARAM_LEN, cmd);\n\t\t}\n\t}\n}\n\n\nstatic void rtw_hal_set_mcc_macid_cmd(PADAPTER padapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_adapter_priv *pmccadapriv = NULL;\n\t_adapter *iface = NULL;\n\tu8 cmd[H2C_MCC_MACID_BITMAP_LEN] = {0}, i = 0, order = 0;\n\tu16 bitmap = 0;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface == NULL)\n\t\t\tcontinue;\n\n\t\tpmccadapriv = &iface->mcc_adapterpriv;\n\t\tif (pmccadapriv->role == MCC_ROLE_MAX)\n\t\t\tcontinue;\n\t\t\n\t\torder = pmccadapriv->order;\n\t\tbitmap = pmccadapriv->mcc_macid_bitmap;\n\n\t\tif (order >= (H2C_MCC_MACID_BITMAP_LEN/2)) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" only support 3 interface at most(%d)\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter), order);\n\t\t\tcontinue;\n\t\t}\n\t\tSET_H2CCMD_MCC_MACID_BITMAP_L((cmd + order * 2), (u8)(bitmap & 0xff));\n\t\tSET_H2CCMD_MCC_MACID_BITMAP_H((cmd + order * 2), (u8)((bitmap >> 8) & 0xff));\n\t}\n\n#ifdef CONFIG_MCC_MODE_DEBUG\n\tRTW_INFO(\"=========================\\n\");\n\tRTW_INFO(\"MACID BITMAP: \");\n\tfor (i = 0; i < H2C_MCC_MACID_BITMAP_LEN; i++)\n\t\tprintk(\"0x%x \", cmd[i]);\n\tprintk(\"\\n\");\n\tRTW_INFO(\"=========================\\n\");\n#endif /* CONFIG_MCC_MODE_DEBUG */\n\trtw_hal_fill_h2c_cmd(padapter, H2C_MCC_MACID_BITMAP, H2C_MCC_MACID_BITMAP_LEN, cmd);\n}\n\n#ifdef CONFIG_MCC_MODE_V2\nstatic u8 get_pri_ch_idx_by_adapter(u8 center_ch, u8 channel, u8 bw, u8 ch_offset40)\n{\n\tu8 pri_ch_idx = 0, chnl_offset80 = 0;\n\n\tif (bw == CHANNEL_WIDTH_80) {\n\t\tif (center_ch > channel)\n\t\t\tchnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\telse if (center_ch < channel)\n\t\t\tchnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\telse\n\t\t\tchnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t}\n\n\tif (bw == CHANNEL_WIDTH_80) {\n\t\t/* primary channel is at lower subband of 80MHz & 40MHz */\n\t\tif ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER))\n\t\t\tpri_ch_idx = VHT_DATA_SC_20_LOWEST_OF_80MHZ;\n\t\t/* primary channel is at lower subband of 80MHz & upper subband of 40MHz */\n\t\telse if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER))\n\t\t\tpri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;\n\t\t/* primary channel is at upper subband of 80MHz & lower subband of 40MHz */\n\t\telse if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER))\n\t\t\tpri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;\n\t\t/* primary channel is at upper subband of 80MHz & upper subband of 40MHz */\n\t\telse if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER))\n\t\t\tpri_ch_idx = VHT_DATA_SC_20_UPPERST_OF_80MHZ;\n\t\telse {\n\t\t\tif (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER)\n\t\t\t\tpri_ch_idx = VHT_DATA_SC_40_LOWER_OF_80MHZ;\n\t\t\telse if (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER)\n\t\t\t\tpri_ch_idx = VHT_DATA_SC_40_UPPER_OF_80MHZ;\n\t\t\telse\n\t\t\t\tRTW_INFO(\"SCMapping: DONOT CARE Mode Setting\\n\");\n\t\t}\n\t} else if (bw == CHANNEL_WIDTH_40) {\n\t\t/* primary channel is at upper subband of 40MHz */\n\t\tif (ch_offset40== HAL_PRIME_CHNL_OFFSET_UPPER)\n\t\t\tpri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;\n\t\t/* primary channel is at lower subband of 40MHz */\n\t\telse if (ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER)\n\t\t\tpri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;\n\t\telse\n\t\t\tRTW_INFO(\"SCMapping: DONOT CARE Mode Setting\\n\");\n\t}\n\n\treturn  pri_ch_idx;\n}\n\nstatic void rtw_hal_set_mcc_ctrl_cmd_v2(PADAPTER padapter, u8 stop)\n{\n\tu8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0;\n\tu8 order = 0, totalnum = 0;\n\tu8 center_ch = 0, pri_ch_idx = 0, bw = 0;\n\tu8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0;\n\tu8 dis_sw_retry = 0, null_early_time=2, tsfx = 0, update_parm = 0;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);\n\tstruct mcc_adapter_priv *mccadapriv = NULL;\n\tstruct mlme_ext_priv *pmlmeext = NULL;\n\tstruct mlme_ext_info *pmlmeinfo = NULL;\n\t_adapter *iface = NULL;\n\n\tRTW_INFO(FUNC_ADPT_FMT\": stop=%d\\n\", FUNC_ADPT_ARG(padapter), stop);\n\n\tfor (i = 0; i < MAX_MCC_NUM; i++) {\n\t\tiface = pmccobjpriv->iface[i];\n\t\tif (iface == NULL)\n\t\t\tcontinue;\n\n\t\tif (stop) {\n\t\t\tif (iface != padapter)\n\t\t\t\tcontinue;\n\t\t}\n\n\t\tmccadapriv = &iface->mcc_adapterpriv;\n\t\torder = mccadapriv->order;\n\n\t\tif (!stop)\n\t\t\ttotalnum = MAX_MCC_NUM;\n\t\telse\n\t\t\ttotalnum = 0xff; /* 0xff means stop */\n\n\t\tpmlmeext = &iface->mlmeextpriv;\n\t\tcenter_ch = rtw_get_center_ch(pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);\n\t\tpri_ch_idx = get_pri_ch_idx_by_adapter(center_ch, pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);\n\t\tbw = pmlmeext->cur_bwmode;\n\t\tduration = mccadapriv->mcc_duration;\n\t\trole = mccadapriv->role;\n\n\t\tincurch = _FALSE;\n\t\tdis_sw_retry = _TRUE;\n\n\t\t/* STA/GC TX NULL data to inform AP/GC for ps mode */\n\t\tswitch (role) {\n\t\tcase MCC_ROLE_GO:\n\t\tcase MCC_ROLE_AP:\n\t\t\tdistxnull = MCC_DISABLE_TX_NULL;\n\t\t\tbreak;\n\t\tcase MCC_ROLE_GC:\n\t\t\tset_channel_bwmode(iface, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);\n\t\t\tdistxnull = MCC_ENABLE_TX_NULL;\n\t\t\tbreak;\n\t\tcase MCC_ROLE_STA:\n\t\t\tdistxnull = MCC_ENABLE_TX_NULL;\n\t\t\tbreak;\n\t\t}\n\n\t\tnull_early_time = mccadapriv->null_early;\n\n\t\tc2hrpt = MCC_C2H_REPORT_ALL_STATUS;\n\t\ttsfx = rtw_hal_get_port(iface);\n\t\tupdate_parm = 0;\n\n\t\tSET_H2CCMD_MCC_CTRL_V2_ORDER(cmd, order);\n\t\tSET_H2CCMD_MCC_CTRL_V2_TOTALNUM(cmd, totalnum);\n\t\tSET_H2CCMD_MCC_CTRL_V2_CENTRAL_CH(cmd, center_ch);\n\t\tSET_H2CCMD_MCC_CTRL_V2_PRIMARY_CH(cmd, pri_ch_idx);\n\t\tSET_H2CCMD_MCC_CTRL_V2_BW(cmd, bw);\n\t\tSET_H2CCMD_MCC_CTRL_V2_DURATION(cmd, duration);\n\t\tSET_H2CCMD_MCC_CTRL_V2_ROLE(cmd, role);\n\t\tSET_H2CCMD_MCC_CTRL_V2_INCURCH(cmd, incurch);\n\t\tSET_H2CCMD_MCC_CTRL_V2_DIS_SW_RETRY(cmd, dis_sw_retry);\n\t\tSET_H2CCMD_MCC_CTRL_V2_DISTXNULL(cmd, distxnull);\n\t\tSET_H2CCMD_MCC_CTRL_V2_C2HRPT(cmd, c2hrpt);\n\t\tSET_H2CCMD_MCC_CTRL_V2_TSFX(cmd, tsfx);\n\t\tSET_H2CCMD_MCC_CTRL_V2_NULL_EARLY(cmd, null_early_time);\n\t\tSET_H2CCMD_MCC_CTRL_V2_UPDATE_PARM(cmd, update_parm);\n\n#ifdef CONFIG_MCC_MODE_DEBUG\n\t\tRTW_INFO(\"=========================\\n\");\n\t\tRTW_INFO(FUNC_ADPT_FMT\" MCC INFO:\\n\", FUNC_ADPT_ARG(iface));\n\t\tRTW_INFO(\"cmd[0]:0x%02x\\n\", cmd[0]);\n\t\tRTW_INFO(\"cmd[1]:0x%02x\\n\", cmd[1]);\n\t\tRTW_INFO(\"cmd[2]:0x%02x\\n\", cmd[2]);\n\t\tRTW_INFO(\"cmd[3]:0x%02x\\n\", cmd[3]);\n\t\tRTW_INFO(\"cmd[4]:0x%02x\\n\", cmd[4]);\n\t\tRTW_INFO(\"cmd[5]:0x%02x\\n\", cmd[5]);\n\t\tRTW_INFO(\"cmd[6]:0x%02x\\n\", cmd[6]);\n\t\tRTW_INFO(\"=========================\\n\");\n#endif /* CONFIG_MCC_MODE_DEBUG */\n\n\t\trtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL_V2, H2C_MCC_CTRL_LEN, cmd);\n\t}\n}\n\n#else\nstatic void rtw_hal_set_mcc_ctrl_cmd_v1(PADAPTER padapter, u8 stop)\n{\n\tu8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0;\n\tu8 order = 0, totalnum = 0, chidx = 0, bw = 0, bw40sc = 0, bw80sc = 0;\n\tu8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0, chscan = 0;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);\n\tstruct mcc_adapter_priv *mccadapriv = NULL;\n\tstruct mlme_ext_priv *pmlmeext = NULL;\n\tstruct mlme_ext_info *pmlmeinfo = NULL;\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\t_adapter *iface = NULL;\n\n\tRTW_INFO(FUNC_ADPT_FMT\": stop=%d\\n\", FUNC_ADPT_ARG(padapter), stop);\n\n\tfor (i = 0; i < MAX_MCC_NUM; i++) {\n\t\tiface = pmccobjpriv->iface[i];\n\t\tif (iface == NULL)\n\t\t\tcontinue;\n\n\t\tif (stop) {\n\t\t\tif (iface != padapter)\n\t\t\t\tcontinue;\n\t\t}\n\n\t\tmccadapriv = &iface->mcc_adapterpriv;\n\t\torder = mccadapriv->order;\n\n\t\tif (!stop)\n\t\t\ttotalnum = MAX_MCC_NUM;\n\t\telse\n\t\t\ttotalnum = 0xff; /* 0xff means stop */\n\n\t\tpmlmeext = &iface->mlmeextpriv;\n\t\tchidx = pmlmeext->cur_channel;\n\t\tbw = pmlmeext->cur_bwmode;\n\t\tbw40sc = pmlmeext->cur_ch_offset;\n\n\t\t/* decide 80 band width offset */\n\t\tif (bw == CHANNEL_WIDTH_80) {\n\t\t\tu8 center_ch = rtw_get_center_ch(chidx, bw, bw40sc);\n\n\t\t\tif (center_ch > chidx)\n\t\t\t\tbw80sc = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\t\telse if (center_ch < chidx)\n\t\t\t\tbw80sc = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\t\telse\n\t\t\t\tbw80sc = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t} else\n\t\t\tbw80sc = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\n\t\tduration = mccadapriv->mcc_duration;\n\t\trole = mccadapriv->role;\n\n\t\tincurch = _FALSE;\n\n\t\tif (IS_HARDWARE_TYPE_8812(padapter))\n\t\t\trfetype = pHalData->rfe_type; /* RFETYPE (only for 8812)*/\n\t\telse\n\t\t\trfetype = 0;\n\n\t\t/* STA/GC TX NULL data to inform AP/GC for ps mode */\n\t\tswitch (role) {\n\t\tcase MCC_ROLE_GO:\n\t\tcase MCC_ROLE_AP:\n\t\t\tdistxnull = MCC_DISABLE_TX_NULL;\n\t\t\tbreak;\n\t\tcase MCC_ROLE_GC:\n\t\tcase MCC_ROLE_STA:\n\t\t\tdistxnull = MCC_ENABLE_TX_NULL;\n\t\t\tbreak;\n\t\t}\n\n\t\tc2hrpt = MCC_C2H_REPORT_ALL_STATUS;\n\t\tchscan = MCC_CHIDX;\n\n\t\tSET_H2CCMD_MCC_CTRL_ORDER(cmd, order);\n\t\tSET_H2CCMD_MCC_CTRL_TOTALNUM(cmd, totalnum);\n\t\tSET_H2CCMD_MCC_CTRL_CHIDX(cmd, chidx);\n\t\tSET_H2CCMD_MCC_CTRL_BW(cmd, bw);\n\t\tSET_H2CCMD_MCC_CTRL_BW40SC(cmd, bw40sc);\n\t\tSET_H2CCMD_MCC_CTRL_BW80SC(cmd, bw80sc);\n\t\tSET_H2CCMD_MCC_CTRL_DURATION(cmd, duration);\n\t\tSET_H2CCMD_MCC_CTRL_ROLE(cmd, role);\n\t\tSET_H2CCMD_MCC_CTRL_INCURCH(cmd, incurch);\n\t\tSET_H2CCMD_MCC_CTRL_RFETYPE(cmd, rfetype);\n\t\tSET_H2CCMD_MCC_CTRL_DISTXNULL(cmd, distxnull);\n\t\tSET_H2CCMD_MCC_CTRL_C2HRPT(cmd, c2hrpt);\n\t\tSET_H2CCMD_MCC_CTRL_CHSCAN(cmd, chscan);\n\n#ifdef CONFIG_MCC_MODE_DEBUG\n\t\tRTW_INFO(\"=========================\\n\");\n\t\tRTW_INFO(FUNC_ADPT_FMT\" MCC INFO:\\n\", FUNC_ADPT_ARG(iface));\n\t\tRTW_INFO(\"cmd[0]:0x%02x\\n\", cmd[0]);\n\t\tRTW_INFO(\"cmd[1]:0x%02x\\n\", cmd[1]);\n\t\tRTW_INFO(\"cmd[2]:0x%02x\\n\", cmd[2]);\n\t\tRTW_INFO(\"cmd[3]:0x%02x\\n\", cmd[3]);\n\t\tRTW_INFO(\"cmd[4]:0x%02x\\n\", cmd[4]);\n\t\tRTW_INFO(\"cmd[5]:0x%02x\\n\", cmd[5]);\n\t\tRTW_INFO(\"cmd[6]:0x%02x\\n\", cmd[6]);\n\t\tRTW_INFO(\"=========================\\n\");\n#endif /* CONFIG_MCC_MODE_DEBUG */\n\n\t\trtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL, H2C_MCC_CTRL_LEN, cmd);\n\t}\n}\n#endif\n\nstatic void rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter, u8 stop)\n{\n\t#ifdef CONFIG_MCC_MODE_V2\n\t\t/* new cmd 0x17 */\n\t\trtw_hal_set_mcc_ctrl_cmd_v2(padapter, stop);\n\t#else\n\t\t/* old cmd 0x18 */\n\t\trtw_hal_set_mcc_ctrl_cmd_v1(padapter, stop);\n\t#endif\n}\n\nstatic u8 check_mcc_support(PADAPTER adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tu8 sta_linked_num = DEV_STA_LD_NUM(dvobj);\n\tu8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);\n\tu8 ap_num = DEV_AP_NUM(dvobj);\n\tu8 ret = _FAIL;\n\n\tRTW_INFO(\"[MCC] sta_linked_num=%d, starting_ap_num=%d,ap_num=%d\\n\",\n\t\tsta_linked_num, starting_ap_num, ap_num);\n\n\t/* case for sta + sta case  */\n\tif (sta_linked_num == MAX_MCC_NUM) {\n\t\tret = _SUCCESS;\n\t\tgoto exit;\n\t}\n\n\t/* case for starting AP + linked sta */\n\tif ((starting_ap_num + sta_linked_num) == MAX_MCC_NUM) {\n\t\tret = _SUCCESS;\n\t\tgoto exit;\n\t}\n\n\t/* case for started AP + linked sta */\n\tif ((ap_num + sta_linked_num) == MAX_MCC_NUM) {\n\t\tret = _SUCCESS;\n\t\tgoto exit;\n\t}\n\nexit:\n\t\treturn ret;\n}\n\nstatic void rtw_hal_mcc_start_prehdl(PADAPTER padapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\t_adapter *iface = NULL;\n\tstruct mcc_adapter_priv *mccadapriv = NULL;\n\tu8 i = 1;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface == NULL)\n\t\t\tcontinue;\n\n\t\tmccadapriv = &iface->mcc_adapterpriv;\n\t\tmccadapriv->role = MCC_ROLE_MAX;\n\t}\n}\n\nstatic u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status)\n{\n\tu8 ret = _SUCCESS, enable_tsf_auto_sync = _FALSE;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);\n\n\tif (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {\n\t\trtw_warn_on(1);\n\t\tRTW_INFO(\"PS mode is not active before start mcc, force exit ps mode\\n\");\n\t\tLeaveAllPowerSaveModeDirect(padapter);\n\t}\n\n\tif (check_mcc_support(padapter) == _FAIL) {\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\trtw_hal_mcc_start_prehdl(padapter);\n\n\t/* configure mcc switch channel setting */\n\trtw_hal_config_mcc_switch_channel_setting(padapter);\n\n\tif (rtw_hal_decide_mcc_role(padapter) == _FAIL) {\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t/* set mcc status to indicate process mcc start setting */\n\trtw_hal_set_mcc_status(padapter, MCC_STATUS_PROCESS_MCC_START_SETTING);\n\n\t/* only download rsvd page for connect */\n\tif (status == MCC_SETCMD_STATUS_START_CONNECT) {\n\t\t/* download mcc rsvd page */\n\t\trtw_hal_set_fw_mcc_rsvd_page(padapter);\n\t\trtw_hal_set_mcc_rsvdpage_cmd(padapter);\n\t}\n\n\t/* configure time setting */\n\trtw_hal_set_mcc_time_setting_cmd(padapter);\n\n#ifndef CONFIG_MCC_MODE_V2\n\t/* IQK value offload */\n\trtw_hal_set_mcc_IQK_offload_cmd(padapter);\n#endif\n\n\t/* set mac id to fw */\n\trtw_hal_set_mcc_macid_cmd(padapter);\n\n\tif (dvobj->p0_tsf.sync_port != MAX_HW_PORT ) {\n\t\t/* disable tsf auto sync */\n\t\tRTW_INFO(\"[MCC] disable HW TSF sync\\n\");\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_TSF_AUTO_SYNC, &enable_tsf_auto_sync);\n\t} else {\n\t\tRTW_INFO(\"[MCC] already disable HW TSF sync\\n\");\n\t}\n\n\t/* set mcc parameter  */\n\trtw_hal_set_mcc_ctrl_cmd(padapter, _FALSE);\n\nexit:\n\treturn ret;\n}\n\nstatic void rtw_hal_set_mcc_stop_setting(PADAPTER padapter, u8 status)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *mccobjpriv = &dvobj->mcc_objpriv;\n\t_adapter *iface = NULL;\n\tstruct mcc_adapter_priv *mccadapriv = NULL;\n\tu8 i = 0;\n\t/*\n\t * when adapter disconnect, stop mcc mod\n\t * total=0xf means stop mcc mode\n\t */\n\n\tswitch (status) {\n\tdefault:\n\t\t/* let fw switch to other interface channel */\n\t\tfor (i = 0; i < MAX_MCC_NUM; i++) {\n\t\t\tiface = mccobjpriv->iface[i];\n\t\t\tif (iface == NULL)\n\t\t\t\tcontinue;\n\n\t\t\tmccadapriv = &iface->mcc_adapterpriv;\n\n\t\t\t/* use other interface to set cmd */\n\t\t\tif (iface != padapter) {\n\t\t\t\trtw_hal_set_mcc_ctrl_cmd(iface, _TRUE);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tbreak;\n\t}\n}\n\nstatic void rtw_hal_mcc_status_hdl(PADAPTER padapter, u8 status)\n{\n\tswitch (status) {\n\tcase MCC_SETCMD_STATUS_STOP_DISCONNECT:\n\t\trtw_hal_clear_mcc_status(padapter, MCC_STATUS_NEED_MCC | MCC_STATUS_DOING_MCC);\n\t\tbreak;\n\tcase MCC_SETCMD_STATUS_STOP_SCAN_START:\n\t\trtw_hal_set_mcc_status(padapter, MCC_STATUS_NEED_MCC);\n\t\trtw_hal_clear_mcc_status(padapter, MCC_STATUS_DOING_MCC);\n\t\tbreak;\n\n\tcase MCC_SETCMD_STATUS_START_CONNECT:\n\tcase MCC_SETCMD_STATUS_START_SCAN_DONE:\n\t\trtw_hal_set_mcc_status(padapter, MCC_STATUS_NEED_MCC | MCC_STATUS_DOING_MCC);\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(FUNC_ADPT_FMT\" error status(%d)\\n\", FUNC_ADPT_ARG(padapter), status);\n\t\tbreak;\n\t}\n}\n\nstatic void rtw_hal_mcc_stop_posthdl(PADAPTER padapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);\n\tstruct mcc_adapter_priv *mccadapriv = NULL;\n\t_adapter *iface = NULL;\n\tPHAL_DATA_TYPE hal;\n\tu8 i = 0;\n\tu8 enable_rx_bar = _FALSE;\n\n\thal = GET_HAL_DATA(padapter);\n\n\tfor (i = 0; i < MAX_MCC_NUM; i++) {\n\t\tiface = mccobjpriv->iface[i];\n\t\tif (iface == NULL)\n\t\t\tcontinue;\n\n\t\t/* release network queue */\n\t\trtw_netif_wake_queue(iface->pnetdev);\n\t\tmccadapriv = &iface->mcc_adapterpriv;\n\t\tmccadapriv->mcc_tx_bytes_from_kernel = 0;\n\t\tmccadapriv->mcc_last_tx_bytes_from_kernel = 0;\n\t\tmccadapriv->mcc_tx_bytes_to_port = 0;\n\n\t\tif (mccadapriv->role == MCC_ROLE_GO)\n\t\t\trtw_hal_mcc_remove_go_p2p_ie(iface);\n\n#ifdef CONFIG_TDLS\n\t\tif (MLME_IS_STA(iface)) {\n\t\t\tif (mccadapriv->backup_tdls_en) {\n\t\t\t\trtw_enable_tdls_func(iface);\n\t\t\t\tRTW_INFO(\"%s: Disable MCC, Enable TDLS\\n\", __func__);\n\t\t\t\tmccadapriv->backup_tdls_en = _FALSE;\n\t\t\t}\n\t\t}\n#endif /* CONFIG_TDLS */\n\n\t\tmccadapriv->role = MCC_ROLE_MAX;\n\t\tmccobjpriv->iface[i] = NULL;\n\t}\n\n\t/* force switch channel */\n\thal->current_channel = 0;\n\thal->current_channel_bw = CHANNEL_WIDTH_MAX;\n\t#ifdef CONFIG_MCC_PHYDM_OFFLOAD\n\trtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_STOP, NULL);\n\t#endif\n}\n\nstatic void rtw_hal_mcc_start_posthdl(PADAPTER padapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);\n\tstruct mcc_adapter_priv *mccadapriv = NULL;\n\tstruct pwrctrl_priv\t*pwrpriv = adapter_to_pwrctl(padapter);\n\t_adapter *iface = NULL;\n\tu8 i = 0, order = 0;\n\tu8 enable_rx_bar = _TRUE;\n\n\tfor (i = 0; i < MAX_MCC_NUM; i++) {\n\t\tiface = mccobjpriv->iface[i];\n\t\tif (iface == NULL)\n\t\t\tcontinue;\n\n\t\tmccadapriv = &iface->mcc_adapterpriv;\n\t\tif (mccadapriv->role == MCC_ROLE_MAX)\n\t\t\tcontinue;\n\t\t\n\t\tmccadapriv->mcc_tx_bytes_from_kernel = 0;\n\t\tmccadapriv->mcc_last_tx_bytes_from_kernel = 0;\n\t\tmccadapriv->mcc_tx_bytes_to_port = 0;\n\n#ifdef CONFIG_TDLS\n\t\tif (MLME_IS_STA(iface)) {\n\t\t\tif (rtw_is_tdls_enabled(iface)) {\n\t\t\t\tmccadapriv->backup_tdls_en = _TRUE;\n\t\t\t\trtw_disable_tdls_func(iface, _TRUE);\n\t\t\t\tRTW_INFO(\"%s: Enable MCC, Disable TDLS\\n\", __func__);\n\t\t\t}\n\t\t}\n#endif /* CONFIG_TDLS */\n\t}\n\t#ifdef CONFIG_MCC_PHYDM_OFFLOAD\n\trtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_START, NULL);\n\t#endif\n}\n\n/*\n * rtw_hal_set_mcc_setting - set mcc setting\n * @padapter: currnet padapter to stop/start MCC\n * @stop: stop mcc or not\n * @return val: 1 for SUCCESS, 0 for fail\n */\nstatic u8 rtw_hal_set_mcc_setting(PADAPTER padapter, u8 status)\n{\n\tu8 ret = _FAIL;\n\tstruct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);\n\tu8 stop = (status < MCC_SETCMD_STATUS_START_CONNECT) ? _TRUE : _FALSE;\n\tu32 start_time = rtw_get_current_time();\n\n\tRTW_INFO(\"===> \"FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n\n\trtw_sctx_init(&pmccobjpriv->mcc_sctx, MCC_EXPIRE_TIME);\n\tpmccobjpriv->mcc_c2h_status = MCC_RPT_MAX;\n\n\tif (stop == _FALSE) {\n\t\t/* handle mcc start */\n\t\tif (rtw_hal_set_mcc_start_setting(padapter, status) == _FAIL)\n\t\t\tgoto exit;\n\n\t\t/* wait for C2H */\n\t\tif (!rtw_sctx_wait(&pmccobjpriv->mcc_sctx, __func__))\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\": wait for mcc start C2H time out\\n\", FUNC_ADPT_ARG(padapter));\n\t\telse\n\t\t\tret = _SUCCESS;\n\n\t\tif (ret == _SUCCESS) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\": mcc start sucecssfully\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\trtw_hal_mcc_status_hdl(padapter, status);\n\t\t\trtw_hal_mcc_start_posthdl(padapter);\n\t\t}\n\t} else {\n\n\t\t/* set mcc status to indicate process mcc start setting */\n\t\trtw_hal_set_mcc_status(padapter, MCC_STATUS_PROCESS_MCC_STOP_SETTING);\n\n\t\t/* handle mcc stop */\n\t\trtw_hal_set_mcc_stop_setting(padapter, status);\n\n\t\t/* wait for C2H */\n\t\tif (!rtw_sctx_wait(&pmccobjpriv->mcc_sctx, __func__))\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\": wait for mcc stop C2H time out\\n\", FUNC_ADPT_ARG(padapter));\n\t\telse {\n\t\t\tret = _SUCCESS;\n\t\t\trtw_hal_mcc_status_hdl(padapter, status);\n\t\t\trtw_hal_mcc_stop_posthdl(padapter);\n\t\t}\n\t}\n\nexit:\n\t/* clear mcc status */\n\trtw_hal_clear_mcc_status(padapter\n\t\t, MCC_STATUS_PROCESS_MCC_START_SETTING | MCC_STATUS_PROCESS_MCC_STOP_SETTING);\n\n\tRTW_INFO(FUNC_ADPT_FMT\" in %dms <===\\n\"\n\t\t, FUNC_ADPT_ARG(padapter), rtw_get_passing_time_ms(start_time));\n\treturn ret;\n}\n\n/**\n * rtw_hal_mcc_check_case_not_limit_traffic - handler flow ctrl for special case\n * @cur_iface: fw stay channel setting of this iface\n * @next_iface: fw will swich channel setting of this iface\n */\nstatic void rtw_hal_mcc_check_case_not_limit_traffic(PADAPTER cur_iface, PADAPTER next_iface)\n{\n\tu8 cur_bw = cur_iface->mlmeextpriv.cur_bwmode;\n\tu8 next_bw = next_iface->mlmeextpriv.cur_bwmode;\n\n\t/* for both interface are VHT80, doesn't limit_traffic according to iperf results */\n\tif (cur_bw == CHANNEL_WIDTH_80 && next_bw == CHANNEL_WIDTH_80) {\n\t\tcur_iface->mcc_adapterpriv.mcc_tp_limit = _FALSE;\n\t\tnext_iface->mcc_adapterpriv.mcc_tp_limit = _FALSE;\n\t}\n}\n\n\n/**\n * rtw_hal_mcc_sw_ch_fw_notify_hdl - handler flow ctrl\n */\nstatic void rtw_hal_mcc_sw_ch_fw_notify_hdl(PADAPTER padapter)\n{\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);\n\tstruct mcc_adapter_priv *cur_mccadapriv = NULL, *next_mccadapriv = NULL;\n\t_adapter *iface = NULL, *cur_iface = NULL, *next_iface = NULL;\n\tstruct registry_priv *preg = &padapter->registrypriv;\n\tu8 cur_op_ch = pdvobjpriv->oper_channel;\n\tu8 i = 0, iface_num = pdvobjpriv->iface_nums, cur_order = 0, next_order = 0;\n\tstatic u8 cnt = 1;\n\tu32 single_tx_cri = preg->rtw_mcc_single_tx_cri;\n\n\tfor (i = 0; i < iface_num; i++) {\n\t\tiface = pdvobjpriv->padapters[i];\n\t\tif (iface == NULL)\n\t\t\tcontinue;\n\n\t\tif (cur_op_ch == iface->mlmeextpriv.cur_channel) {\n\t\t\tcur_iface = iface;\n\t\t\tcur_mccadapriv = &cur_iface->mcc_adapterpriv;\n\t\t\tcur_order = cur_mccadapriv->order;\n\t\t\tnext_order = (cur_order + 1) % iface_num;\n\t\t\tnext_iface = pmccobjpriv->iface[next_order];\n\t\t\tnext_mccadapriv = &next_iface->mcc_adapterpriv;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (cur_iface == NULL || next_iface == NULL) {\n\t\tRTW_ERR(\"cur_iface=%p,next_iface=%p\\n\", cur_iface, next_iface);\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\t/* check other interface tx busy traffic or not under every 2 switch channel notify(Mbits/100ms) */\n\tif (cnt == 2) {\n\t\tcur_mccadapriv->mcc_tp = (cur_mccadapriv->mcc_tx_bytes_from_kernel\n\t\t\t- cur_mccadapriv->mcc_last_tx_bytes_from_kernel) * 10 * 8 / 1024 / 1024;\n\t\tcur_mccadapriv->mcc_last_tx_bytes_from_kernel = cur_mccadapriv->mcc_tx_bytes_from_kernel;\n\n\t\tnext_mccadapriv->mcc_tp = (next_mccadapriv->mcc_tx_bytes_from_kernel\n\t\t\t- next_mccadapriv->mcc_last_tx_bytes_from_kernel) * 10 * 8 / 1024 / 1024;\n\t\tnext_mccadapriv->mcc_last_tx_bytes_from_kernel = next_mccadapriv->mcc_tx_bytes_from_kernel;\n\n\t\tcnt = 1;\n\t} else\n\t\tcnt = 2;\n\n\t/* check single TX or cuncurrnet TX */\n\tif (next_mccadapriv->mcc_tp < single_tx_cri) {\n\t\t/* single TX, does not stop */\n\t\tcur_mccadapriv->mcc_tx_stop = _FALSE;\n\t\tcur_mccadapriv->mcc_tp_limit = _FALSE;\n\t} else {\n\t\t/* concurrent TX, stop */\n\t\tcur_mccadapriv->mcc_tx_stop = _TRUE;\n\t\tcur_mccadapriv->mcc_tp_limit = _TRUE;\n\t}\n\n\tif (cur_mccadapriv->mcc_tp < single_tx_cri) {\n\t\tnext_mccadapriv->mcc_tx_stop  = _FALSE;\n\t\tnext_mccadapriv->mcc_tp_limit = _FALSE;\n\t} else {\n\t\tnext_mccadapriv->mcc_tx_stop = _FALSE;\n\t\tnext_mccadapriv->mcc_tp_limit = _TRUE;\n\t\tnext_mccadapriv->mcc_tx_bytes_to_port = 0;\n\t}\n\n\t/* stop current iface kernel queue or not */\n\tif (cur_mccadapriv->mcc_tx_stop)\n\t\trtw_netif_stop_queue(cur_iface->pnetdev);\n\telse\n\t\trtw_netif_wake_queue(cur_iface->pnetdev);\n\n\t/* stop next iface kernel queue or not */\n\tif (next_mccadapriv->mcc_tx_stop)\n\t\trtw_netif_stop_queue(next_iface->pnetdev);\n\telse\n\t\trtw_netif_wake_queue(next_iface->pnetdev);\n\n\t/* start xmit tasklet */\n\trtw_os_xmit_schedule(next_iface);\n\n\trtw_hal_mcc_check_case_not_limit_traffic(cur_iface, next_iface);\n\n\tif (0) {\n\t\tRTW_INFO(\"order:%d, mcc_tx_stop:%d, mcc_tp:%d\\n\",\n\t\t\tcur_mccadapriv->order, cur_mccadapriv->mcc_tx_stop, cur_mccadapriv->mcc_tp);\n\t\tdump_os_queue(0, cur_iface);\n\t\tRTW_INFO(\"order:%d, mcc_tx_stop:%d, mcc_tp:%d\\n\",\n\t\t\tnext_mccadapriv->order, next_mccadapriv->mcc_tx_stop, next_mccadapriv->mcc_tp);\n\t\tdump_os_queue(0, next_iface);\n\t}\n}\n\nstatic void rtw_hal_mcc_update_noa_start_time_hdl(PADAPTER padapter, u8 buflen, u8 *tmpBuf)\n{\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);\n\tstruct mcc_adapter_priv *pmccadapriv = NULL;\n\tPADAPTER iface = NULL;\n\tu8 i = 0;\n\tu8 policy_idx = pmccobjpriv->policy_index;\n\tu8 noa_tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];\n\tu8 noa_start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];\n\t\n\tfor (i = 0; i < pdvobjpriv->iface_nums; i++) {\n\t\tiface = pdvobjpriv->padapters[i];\n\t\tif (iface == NULL)\n\t\t\tcontinue;\n\t\t\n\t\tpmccadapriv = &iface->mcc_adapterpriv;\n\t\tif (pmccadapriv->role == MCC_ROLE_MAX)\n\t\t\tcontinue;\n\n\t\t/* GO & channel match */\n\t\tif (pmccadapriv->role == MCC_ROLE_GO) {\n\t\t\t/* convert GO TBTT from FW to noa_start_time(TU convert to mircosecond) */\n\t\t\tpmccadapriv->noa_start_time = RTW_GET_LE32(tmpBuf + 2) + noa_start_time_offset * TU;\n\n\t\t\tif (0) {\n\t\t\t\tRTW_INFO(\"TBTT:0x%02x\\n\", RTW_GET_LE32(tmpBuf + 2));\n\t\t\t\tRTW_INFO(\"noa_tsf_sync_offset:%d, noa_start_time_offset:%d\\n\", noa_tsf_sync_offset, noa_start_time_offset);\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\"buf=0x%02x:0x%02x:0x%02x:0x%02x, noa_start_time=0x%02x\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(iface)\n\t\t\t\t\t, tmpBuf[2]\n\t\t\t\t\t, tmpBuf[3]\n\t\t\t\t\t, tmpBuf[4]\n\t\t\t\t\t, tmpBuf[5]\n\t\t\t\t\t,pmccadapriv->noa_start_time);\n\t\t\t\t}\n\n\t\t\trtw_hal_mcc_update_go_p2p_ie(iface);\n\n\t\t\tbreak;\n\t\t}\n\t}\n\n}\n\nstatic u8 mcc_get_reg_hdl(PADAPTER adapter, const u8 *val)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);\n\tstruct hal_com_data *hal = GET_HAL_DATA(adapter);\n\t_adapter *cur_iface = NULL;\n\tu8 ret = _SUCCESS;\n\tu8 cur_order = 0;\n\n\tu16 dbg_reg[DBG_MCC_REG_NUM] = {0x4d4,0x522,0xc50,0xe50};\n\tu16 dbg_rf_reg[DBG_MCC_RF_REG_NUM] = {0x18};\n\tu8 i;\n\tu32 reg_val;\n\tu8 path = 0, path_nums = 0;\n\n\tif (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tif (!val)\n\t\tcur_order = 0xff;\n\telse\n\t\tcur_order = *val;\n\n\tif (cur_order >= MAX_MCC_NUM && cur_order != 0xff) {\n\t\tRTW_ERR(\"%s: cur_order=%d\\n\", __func__, cur_order);\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpath_nums = hal->NumTotalRFPath;\n\tif (cur_order == 0xff)\n\t\tcur_iface = adapter;\n\telse\n\t\tcur_iface = mccobjpriv->iface[cur_order];\n\n\tif (!cur_iface) {\n\t\tRTW_ERR(\"%s: cur_iface = NULL,  cur_order=%d\\n\", __func__, cur_order);\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t_enter_critical_mutex(&mccobjpriv->mcc_dbg_reg_mutex, NULL);\n\tif (!RTW_CANNOT_IO(adapter)) {\n\t\t/* RTW_INFO(\"=================================\\n\");\n\t\tRTW_INFO(ADPT_FMT\": cur_order:%d\\n\", ADPT_ARG(cur_iface), cur_order); */\n\t\t\n\t\tfor (i = 0; i < ARRAY_SIZE(dbg_reg); i++) {\n\t\t\treg_val = rtw_read32(adapter, dbg_reg[i]);\n\t\t\tmccobjpriv->dbg_reg[i] = dbg_reg[i];\n\t\t\tmccobjpriv->dbg_reg_val[i] = reg_val;\n\t\t\t/* RTW_PRINT(\"REG_%X:0x%08x\\n\", dbg_reg[i], reg_val); */\n\t\t}\n\t\tfor (i = 0; i < ARRAY_SIZE(dbg_rf_reg); i++) {\n\t\t\tfor (path = 0; path < path_nums; path++) {\n\t\t\t\treg_val = rtw_hal_read_rfreg(adapter, path, dbg_rf_reg[i], 0xffffffff);\n\t\t\t\t/* RTW_PRINT(\"RF_PATH_%d_REG_%X:0x%08x\\n\",\n\t\t\t\t\tpath, dbg_rf_reg[i], reg_val); */\n\t\t\t\tmccobjpriv->dbg_rf_reg[i] = dbg_rf_reg[i];\n\t\t\t\tmccobjpriv->dbg_rf_reg_val[i][path] = reg_val;\n\t\t\t}\n\t\t}\n\t}\n\t_exit_critical_mutex(&mccobjpriv->mcc_dbg_reg_mutex, NULL);\n\nexit:\n\treturn ret;\n}\n\nstatic u8 mcc_get_reg_cmd(_adapter *adapter, u8 cur_order)\n{\n\tstruct cmd_obj *cmdobj;\n\tstruct drvextra_cmd_parm *pdrvextra_cmd_parm;\n\tstruct cmd_priv *pcmdpriv = &adapter->cmdpriv;\n\tu8 *mcc_cur_order = NULL;\n\tu8 res = _SUCCESS;\n\n\t\n\tcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (cmdobj == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tmcc_cur_order = rtw_zmalloc(sizeof(u8));\n\tif (mcc_cur_order == NULL) {\n\t\trtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));\n\t\trtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm->ec_id = MCC_CMD_WK_CID;\n\tpdrvextra_cmd_parm->type = MCC_GET_DBG_REG_WK_CID;\n\tpdrvextra_cmd_parm->size = 1;\n\tpdrvextra_cmd_parm->pbuf = mcc_cur_order;\n\n\t_rtw_memcpy(mcc_cur_order, &cur_order, 1);\n\n\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\tres = rtw_enqueue_cmd(pcmdpriv, cmdobj);\n\nexit:\n\treturn res;\n}\n\nstatic void rtw_hal_mcc_rpt_tsf_hdl(PADAPTER padapter, u8 buflen, u8 *tmpBuf)\n{\n\tstruct dvobj_priv *dvobjpriv = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);\n\tstruct submit_ctx *mcc_tsf_req_sctx = &mccobjpriv->mcc_tsf_req_sctx;\n\tstruct mcc_adapter_priv *mccadapriv = NULL;\n\t_adapter *iface = NULL;\n\tu8 order = 0;\n\n\torder = mccobjpriv->mcc_tsf_req_sctx_order;\n\tiface = mccobjpriv->iface[order];\n\tmccadapriv = &iface->mcc_adapterpriv;\n\tmccadapriv->tsf = RTW_GET_LE64(tmpBuf + 2);\n\n\n\tif (0)\n\t\tRTW_INFO(FUNC_ADPT_FMT\" TSF(order:%d):0x%02llx\\n\", FUNC_ADPT_ARG(iface), mccadapriv->order, mccadapriv->tsf);\n\n\tif (mccadapriv->order == (MAX_MCC_NUM - 1))\n\t\trtw_sctx_done(&mcc_tsf_req_sctx);\n\telse\n\t\tmccobjpriv->mcc_tsf_req_sctx_order ++;\n\n}\n\n/**\n * rtw_hal_mcc_c2h_handler - mcc c2h handler\n */\nvoid rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf)\n{\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);\n\tstruct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;\n\tstruct submit_ctx *mcc_sctx = &pmccobjpriv->mcc_sctx;\n\t_adapter *cur_adapter = NULL;\n\tu8 cur_ch = 0, cur_bw = 0, cur_ch_offset = 0;\n\t_irqL irqL;\n\n\t/* RTW_INFO(\"[length]=%d, [C2H data]=\"MAC_FMT\"\\n\", buflen, MAC_ARG(tmpBuf)); */\n\t/* To avoid reg is set, but driver recive c2h to set wrong oper_channel */\n\tif (MCC_RPT_STOPMCC == pmccobjpriv->mcc_c2h_status) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" MCC alread stops return\\n\", FUNC_ADPT_ARG(padapter));\n\t\treturn;\n\t}\n\n\t_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);\n\tpmccobjpriv->mcc_c2h_status = tmpBuf[0];\n\tpmccobjpriv->current_order = tmpBuf[1];\n\tcur_adapter = pmccobjpriv->iface[pmccobjpriv->current_order];\n\tcur_ch = cur_adapter->mlmeextpriv.cur_channel;\n\tcur_bw = cur_adapter->mlmeextpriv.cur_bwmode;\n\tcur_ch_offset = cur_adapter->mlmeextpriv.cur_ch_offset;\n\trtw_set_oper_ch(cur_adapter, cur_ch);\n\trtw_set_oper_bw(cur_adapter, cur_bw);\n\trtw_set_oper_choffset(cur_adapter, cur_ch_offset);\n\t_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);\n\n\tif (0)\n\t\tRTW_INFO(\"%d,order:%d,TSF:0x%llx\\n\", tmpBuf[0], tmpBuf[1], RTW_GET_LE64(tmpBuf + 2));\n\t\n\tswitch (pmccobjpriv->mcc_c2h_status) {\n\tcase MCC_RPT_SUCCESS:\n\t\t_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);\n\t\tpmccobjpriv->cur_mcc_success_cnt++;\n\t\trtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _FALSE);\n\t\tmcc_get_reg_cmd(padapter, pmccobjpriv->current_order);\n\t\t_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);\n\t\tbreak;\n\tcase MCC_RPT_TXNULL_FAIL:\n\t\tRTW_INFO(\"[MCC] TXNULL FAIL\\n\");\n\t\tbreak;\n\tcase MCC_RPT_STOPMCC:\n\t\tRTW_INFO(\"[MCC] MCC stop\\n\");\n\t\tpmccobjpriv->mcc_c2h_status = MCC_RPT_STOPMCC;\n\t\trtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _TRUE);\n\t\trtw_sctx_done(&mcc_sctx);\n\t\tbreak;\n\tcase MCC_RPT_READY:\n\t\t_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);\n\t\t/* initialize counter & time */\n\t\tpmccobjpriv->mcc_launch_time = rtw_get_current_time();\n\t\tpmccobjpriv->mcc_c2h_status = MCC_RPT_READY;\n\t\tpmccobjpriv->cur_mcc_success_cnt = 0;\n\t\tpmccobjpriv->prev_mcc_success_cnt = 0;\n\t\tpmccobjpriv->mcc_tolerance_time = MCC_TOLERANCE_TIME;\n\t\t_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);\n\n\t\tRTW_INFO(\"[MCC] MCC ready\\n\");\n\t\trtw_sctx_done(&mcc_sctx);\n\t\tbreak;\n\tcase MCC_RPT_SWICH_CHANNEL_NOTIFY:\n\t\trtw_hal_mcc_sw_ch_fw_notify_hdl(padapter);\n\t\tbreak;\n\tcase MCC_RPT_UPDATE_NOA_START_TIME:\n\t\trtw_hal_mcc_update_noa_start_time_hdl(padapter, buflen, tmpBuf);\n\t\tbreak;\n\tcase MCC_RPT_TSF:\n\t\t_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);\n\t\trtw_hal_mcc_rpt_tsf_hdl(padapter, buflen, tmpBuf);\n\t\t_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);\n\t\tbreak;\n\tdefault:\n\t\t/* RTW_INFO(\"[MCC] Other MCC status(%d)\\n\", pmccobjpriv->mcc_c2h_status); */\n\t\tbreak;\n\t}\n}\n\nvoid rtw_hal_mcc_update_parameter(PADAPTER padapter, u8 force_update)\n{\t\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);\n\tu8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0};\n\tu8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME;\n\tu8 ap_num = DEV_AP_NUM(dvobj);\t\n\n\tif (ap_num == 0) {\n\t\tu8 need_update = _FALSE;\n\t\tu8 start_time_offset = 0, interval = 0, duration = 0;\n\n\t\tneed_update = rtw_hal_mcc_update_timing_parameters(padapter, force_update);\n\n\t\tif (need_update == _FALSE)\n\t\t\treturn;\n\t\t\n\t\tstart_time_offset = mccobjpriv->start_time;\n\t\tinterval = mccobjpriv->interval;\n\t\tduration = mccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration;\n\n\t\tSET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, start_time_offset);\n\t\tSET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);\n\t\tSET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);\n\t\tSET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE);\n\t\tSET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, duration);\n\t} else {\n\t\tPADAPTER order0_iface = NULL;\n\t\tPADAPTER order1_iface = NULL;\n\t\tu8 policy_idx = mccobjpriv->policy_index;\n\t\tu8 duration = mcc_switch_channel_policy_table[policy_idx][MCC_DURATION_IDX];\n\t\tu8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];\n\t\tu8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];\n\t\tu8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX];\n\t\tu8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX];\n\t\tu8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX];\n\t\tu8 order0_duration = 0;\n\t\tu8 i = 0;\n\t\tenum _hw_port tsf_bsae_port = MAX_HW_PORT;\n\t\tenum _hw_port tsf_sync_port = MAX_HW_PORT;\n\n\t\tRTW_INFO(\"%s: policy_idx=%d\\n\", __func__, policy_idx);\n\n\t\torder0_iface = mccobjpriv->iface[0];\n\t\torder1_iface = mccobjpriv->iface[1];\n\n\t\t/* GO/AP is order 0, GC/STA is order 1 */\n\t\torder0_duration = order0_iface->mcc_adapterpriv.mcc_duration = interval - duration;\n\t\torder0_iface->mcc_adapterpriv.mcc_duration = duration;\n\n\t\ttsf_bsae_port = rtw_hal_get_port(order1_iface);\n\t\ttsf_sync_port = rtw_hal_get_port(order0_iface);\n\n\t\t/* update IE */\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tPADAPTER iface = NULL;\n\t\t\tstruct mcc_adapter_priv *mccadapriv = NULL;\n\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tif (iface == NULL)\n\t\t\t\tcontinue;\n\t\t\n\t\t\tmccadapriv = &iface->mcc_adapterpriv;\n\t\t\tif (mccadapriv->role == MCC_ROLE_MAX)\n\t\t\t\tcontinue;\n\t\t\t\n\t\t\tif (mccadapriv->role == MCC_ROLE_GO)\n\t\t\t\trtw_hal_mcc_update_go_p2p_ie(iface);\n\t\t}\n\n\t\t/* update H2C cmd */\n\t\t/* FW set enable */\n\t\tSET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, _TRUE);\n\t\t/* TSF Sync offset */\n\t\tSET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset);\n\t\t/* start time offset */\n\t\tSET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0));\n\t\t/* interval */\n\t\tSET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);\n\t\t/* Early time to inform driver by C2H before switch channel */\n\t\tSET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);\n\t\t/* Port0 sync from Port1, not support multi-port */\n\t\tSET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, tsf_bsae_port);\n\t\tSET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, tsf_sync_port);\n\t\tSET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE);\n\t\tSET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, order0_duration);\n\t}\n\n\trtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd);\n}\n\n/**\n * rtw_hal_mcc_sw_status_check - check mcc swich channel status\n * @padapter: primary adapter\n */\nvoid rtw_hal_mcc_sw_status_check(PADAPTER padapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);\n\tstruct pwrctrl_priv\t*pwrpriv = dvobj_to_pwrctl(dvobj);\n\tstruct mcc_adapter_priv *mccadapriv = NULL;\n\t_adapter *iface = NULL;\n\tu8 cur_cnt = 0, prev_cnt = 0, diff_cnt = 0, check_ret = _FAIL, threshold = 0;\n\tu8 policy_idx = pmccobjpriv->policy_index;\n\tu8 noa_enable = _FALSE;\n\tu8 i = 0;\n\t_irqL irqL;\n\tu8 ap_num = DEV_AP_NUM(dvobj);\t\n\n/* #define MCC_RESTART 1 */\n\n\tif (!MCC_EN(padapter))\n\t\treturn;\n\n\t_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);\n\n\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {\n\n\t\t/* check noa enable or not */\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tif (iface == NULL)\n\t\t\t\tcontinue;\n\n\t\t\tmccadapriv = &iface->mcc_adapterpriv;\n\t\t\tif (mccadapriv->role == MCC_ROLE_MAX)\n\t\t\t\tcontinue;\n\t\t\t\n\t\t\tif (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) {\n\t\t\t\tnoa_enable = _TRUE;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\t\t\n\n\t\tif (!noa_enable && ap_num == 0)\n\t\t\trtw_hal_mcc_update_parameter(padapter, _FALSE);\n\n\t\tthreshold = pmccobjpriv->mcc_stop_threshold;\n\n\t\tif (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {\n\t\t\trtw_warn_on(1);\n\t\t\tRTW_INFO(\"PS mode is not active under mcc, force exit ps mode\\n\");\n\t\t\tLeaveAllPowerSaveModeDirect(padapter);\n\t\t}\n\n\t\tif (rtw_get_passing_time_ms(pmccobjpriv->mcc_launch_time) > 2000) {\n\t\t\t_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);\n\n\t\t\tcur_cnt = pmccobjpriv->cur_mcc_success_cnt;\n\t\t\tprev_cnt = pmccobjpriv->prev_mcc_success_cnt;\n\t\t\tif (cur_cnt < prev_cnt)\n\t\t\t\tdiff_cnt = (cur_cnt + 255) - prev_cnt;\n\t\t\telse\n\t\t\t\tdiff_cnt = cur_cnt - prev_cnt;\n\n\t\t\tif (diff_cnt < threshold) {\n\t\t\t\tpmccobjpriv->mcc_tolerance_time--;\n\t\t\t\tRTW_INFO(\"%s: diff_cnt:%d, tolerance_time:%d\\n\",\n\t\t\t\t\t__func__, diff_cnt, pmccobjpriv->mcc_tolerance_time);\n\t\t\t} else\n\t\t\t\tpmccobjpriv->mcc_tolerance_time = MCC_TOLERANCE_TIME;\n\n\t\t\tpmccobjpriv->prev_mcc_success_cnt = pmccobjpriv->cur_mcc_success_cnt;\n\n\t\t\tif (pmccobjpriv->mcc_tolerance_time != 0)\n\t\t\t\tcheck_ret = _SUCCESS;\n\n\t\t\t_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);\n\n\t\t\tif (check_ret != _SUCCESS) {\n\t\t\t\tRTW_INFO(\"============ MCC swich channel check fail (%d)=============\\n\", diff_cnt);\n\t\t\t\t/* restart MCC */\n\t\t\t\t#ifdef MCC_RESTART\n\t\t\t\t\trtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_STOP_DISCONNECT);\n\t\t\t\t\trtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);\n\t\t\t\t#endif /* MCC_RESTART */\n\t\t\t}\n\t\t} else {\n\t\t\t_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);\n\t\t\tpmccobjpriv->prev_mcc_success_cnt = pmccobjpriv->cur_mcc_success_cnt;\n\t\t\t_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);\n\t\t}\n\n\t}\n\t_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);\n}\n\n/**\n * rtw_hal_mcc_change_scan_flag - change scan flag under mcc\n *\n * MCC mode under sitesurvey goto AP channel to tx bcn & data\n * MCC mode under sitesurvey doesn't support TX data for station mode (FW not support)\n *\n * @padapter: the adapter to be change scan flag\n * @ch: pointer to rerurn ch\n * @bw: pointer to rerurn bw\n * @offset: pointer to rerurn offset\n */\nu8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset)\n{\n\tu8 need_ch_setting_union = _TRUE, i = 0, flags = 0, back_op = _FALSE;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_adapter_priv *mccadapriv = NULL;\n\tstruct mlme_ext_priv *mlmeext = NULL;\n\t_adapter *iface = NULL;\n\n\tif (!MCC_EN(padapter))\n\t\tgoto exit;\n\n\tif (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC))\n\t\tgoto exit;\n\n\t/* disable PS_ANNC & TX_RESUME for all interface */\n\t/* ToDo: TX_RESUME by interface in SCAN_BACKING_OP */\n\tmlmeext = &padapter->mlmeextpriv;\n\t\n\tflags = mlmeext_scan_backop_flags(mlmeext);\n\tif (mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_PS_ANNC))\n\t\tflags &= ~SS_BACKOP_PS_ANNC;\n\n\tif (mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME))\n\t\tflags &= ~SS_BACKOP_TX_RESUME;\n\n\tmlmeext_assign_scan_backop_flags(mlmeext, flags);\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (!iface)\n\t\t\tcontinue;\n\n\t\tmlmeext = &iface->mlmeextpriv;\n\n\t\tif (MLME_IS_GO(iface) || MLME_IS_AP(iface))\n\t\t\tback_op = _TRUE;\n\t\telse if (MLME_IS_GC(iface) && (iface != padapter))\n\t\t\t/* switch to another linked interface(GO) to receive beacon to avoid no beacon disconnect */\n\t\t\tback_op = _TRUE;\n\t\telse if (MLME_IS_STA(iface) && MLME_IS_ASOC(iface) && (iface != padapter))\n\t\t\t/* switch to another linked interface(STA) to receive beacon to avoid no beacon disconnect  */\n\t\t\tback_op = _TRUE;\n\t\telse {\n\t\t\t/* bypass non-linked/non-linking interface/scan interface */\n\t\t\tcontinue;\n\t\t}\n\t\t\n\t\tif (back_op) {\n\t\t\t*ch = mlmeext->cur_channel;\n\t\t\t*bw = mlmeext->cur_bwmode;\n\t\t\t*offset = mlmeext->cur_ch_offset;\n\t\t\tneed_ch_setting_union = _FALSE;\n\t\t}\n\t}\nexit:\n\treturn need_ch_setting_union;\n}\n\n/**\n * rtw_hal_mcc_calc_tx_bytes_from_kernel - calculte tx bytes from kernel to check concurrent tx or not\n * @padapter: the adapter to be record tx bytes\n * @len: data len\n */\ninline void rtw_hal_mcc_calc_tx_bytes_from_kernel(PADAPTER padapter, u32 len)\n{\n\tstruct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;\n\n\tif (MCC_EN(padapter)) {\n\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {\n\t\t\tpmccadapriv->mcc_tx_bytes_from_kernel += len;\n\t\t\tif (0)\n\t\t\t\tRTW_INFO(\"%s(order:%d): mcc tx bytes from kernel:%lld\\n\"\n\t\t\t\t\t, __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_from_kernel);\n\t\t}\n\t}\n}\n\n/**\n * rtw_hal_mcc_calc_tx_bytes_to_port - calculte tx bytes to write port in order to flow crtl\n * @padapter: the adapter to be record tx bytes\n * @len: data len\n */\ninline void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len)\n{\n\tif (MCC_EN(padapter)) {\n\t\tstruct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);\n\t\tstruct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;\n\n\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {\n\t\t\tpmccadapriv->mcc_tx_bytes_to_port += len;\n\t\t\tif (0)\n\t\t\t\tRTW_INFO(\"%s(order:%d): mcc tx bytes to port:%d, mcc target tx bytes to port:%d\\n\"\n\t\t\t\t\t, __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_to_port\n\t\t\t\t\t, pmccadapriv->mcc_target_tx_bytes_to_port);\n\t\t}\n\t}\n}\n\n/**\n * rtw_hal_mcc_stop_tx_bytes_to_port - stop write port to hw or not\n * @padapter: the adapter to be stopped\n */\ninline u8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter)\n{\n\tif (MCC_EN(padapter)) {\n\t\tstruct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);\n\t\tstruct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;\n\n\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {\n\t\t\tif (pmccadapriv->mcc_tp_limit) {\n\t\t\t\tif (pmccadapriv->mcc_tx_bytes_to_port >= pmccadapriv->mcc_target_tx_bytes_to_port) {\n\t\t\t\t\tpmccadapriv->mcc_tx_stop = _TRUE;\n\t\t\t\t\trtw_netif_stop_queue(padapter->pnetdev);\n\t\t\t\t\treturn _TRUE;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\treturn _FALSE;\n}\n\nstatic void rtw_hal_mcc_assign_scan_flag(PADAPTER padapter, u8 scan_done)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_adapter_priv *mccadapriv = NULL;\n\t_adapter *iface = NULL;\n\tstruct mlme_ext_priv *pmlmeext = NULL;\n\tu8 i = 0, flags;\n\n\tif (!MCC_EN(padapter))\n\t\treturn;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface == NULL)\n\t\t\tcontinue;\n\n\t\tmccadapriv = &iface->mcc_adapterpriv;\n\t\tif (mccadapriv->role == MCC_ROLE_MAX)\n\t\t\tcontinue;\n\n\t\tpmlmeext = &iface->mlmeextpriv;\n\t\tif (is_client_associated_to_ap(iface)) {\n\t\t\tflags = mlmeext_scan_backop_flags_sta(pmlmeext);\n\t\t\tif (scan_done) {\n\t\t\t\tif (mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) {\n\t\t\t\t\tflags &= ~SS_BACKOP_EN;\n\t\t\t\t\tmlmeext_assign_scan_backop_flags_sta(pmlmeext, flags);\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif (!mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) {\n\t\t\t\t\tflags |= SS_BACKOP_EN;\n\t\t\t\t\tmlmeext_assign_scan_backop_flags_sta(pmlmeext, flags);\n\t\t\t\t}\n\t\t\t}\n\n\t\t}\n\t}\n}\n\n/**\n * rtw_hal_set_mcc_setting_scan_start - setting mcc under scan start\n * @padapter: the adapter to be setted\n * @ch_setting_changed: softap channel setting to be changed or not\n */\nu8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter)\n{\n\tu8 ret = _FAIL;\n\n\tif (MCC_EN(padapter)) {\n\t\tstruct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);\n\n\t\t_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);\n\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {\n\t\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {\n\t\t\t\tret = rtw_hal_set_mcc_setting(padapter,  MCC_SETCMD_STATUS_STOP_SCAN_START);\n\t\t\t\trtw_hal_mcc_assign_scan_flag(padapter, 0);\n\t\t\t}\n\t\t}\n\t\t_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);\n\t}\n\n\treturn ret;\n}\n\n/**\n * rtw_hal_set_mcc_setting_scan_complete - setting mcc after scan commplete\n * @padapter: the adapter to be setted\n * @ch_setting_changed: softap channel setting to be changed or not\n */\nu8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter)\n{\n\tu8 ret = _FAIL;\n\n\tif (MCC_EN(padapter)) {\n\t\tstruct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);\n\n\t\t_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);\n\n\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {\n\t\t\t\trtw_hal_mcc_assign_scan_flag(padapter, 1);\n\t\t\t\tret = rtw_hal_set_mcc_setting(padapter,  MCC_SETCMD_STATUS_START_SCAN_DONE);\t\n\t\t}\n\t\t_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);\n\t}\n\n\treturn ret;\n}\n\n\n/**\n * rtw_hal_set_mcc_setting_start_bss_network - setting mcc under softap start\n * @padapter: the adapter to be setted\n * @chbw_grouped: channel bw offset can not be allowed or not\n */\nu8 rtw_hal_set_mcc_setting_start_bss_network(PADAPTER padapter, u8 chbw_allow)\n{\n\tu8 ret = _FAIL;\n\n\tif (MCC_EN(padapter)) {\n\t\t/* channel bw offset can not be allowed, start MCC */\n\t\tif (chbw_allow == _FALSE) {\n\t\t\t\tstruct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);\n\n\t\t\t\trtw_hal_mcc_restore_iqk_val(padapter);\n\t\t\t\t_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);\n\t\t\t\tret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);\n\t\t\t\t_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);\n\t\t\t}\n\t\t}\n\n\treturn ret;\n}\n\n/**\n * rtw_hal_set_mcc_setting_disconnect - setting mcc under mlme disconnect(stop softap/disconnect from AP)\n * @padapter: the adapter to be setted\n */\nu8 rtw_hal_set_mcc_setting_disconnect(PADAPTER padapter)\n{\n\tu8 ret = _FAIL;\n\n\tif (MCC_EN(padapter)) {\n\t\tstruct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);\n\n\t\t_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);\n\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {\n\t\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))\n\t\t\t\tret = rtw_hal_set_mcc_setting(padapter,  MCC_SETCMD_STATUS_STOP_DISCONNECT);\n\t\t}\n\t\t_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);\n\t}\n\n\treturn ret;\n}\n\n/**\n * rtw_hal_set_mcc_setting_join_done_chk_ch - setting mcc under join done\n * @padapter: the adapter to be checked\n */\nu8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter)\n{\n\tu8 ret = _FAIL;\n\n\tif (MCC_EN(padapter)) {\n\t\tstruct mi_state mstate;\n\n\t\trtw_mi_status_no_self(padapter, &mstate);\n\n\t\tif (MSTATE_STA_LD_NUM(&mstate) || MSTATE_STA_LG_NUM(&mstate) || MSTATE_AP_NUM(&mstate)) {\n\t\t\tbool chbw_allow = _TRUE;\n\t\t\tu8 u_ch, u_offset, u_bw;\n\t\t\tstruct mlme_ext_priv *cur_mlmeext = &padapter->mlmeextpriv;\n\t\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\t\t\tif (rtw_mi_get_ch_setting_union_no_self(padapter, &u_ch, &u_bw, &u_offset) <= 0) {\n\t\t\t\tdump_adapters_status(RTW_DBGDUMP , dvobj);\n\t\t\t\trtw_warn_on(1);\n\t\t\t}\n\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" union no self: %u,%u,%u\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter), u_ch, u_bw, u_offset);\n\n\t\t\t/* chbw_allow? */\n\t\t\tchbw_allow = rtw_is_chbw_grouped(cur_mlmeext->cur_channel\n\t\t\t\t, cur_mlmeext->cur_bwmode, cur_mlmeext->cur_ch_offset\n\t\t\t\t\t, u_ch, u_bw, u_offset);\n\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" chbw_allow:%d\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter), chbw_allow);\n\n\t\t\t/* if chbw_allow = false, start MCC setting */\n\t\t\tif (chbw_allow == _FALSE) {\n\t\t\t\tstruct mcc_obj_priv *pmccobjpriv = &dvobj->mcc_objpriv;\n\n\t\t\t\trtw_hal_mcc_restore_iqk_val(padapter);\n\t\t\t\t_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);\n\t\t\t\tret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);\n\t\t\t\t_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);\n\t\t}\n\t}\n\t}\n\n\treturn ret;\n}\n\n/**\n * rtw_hal_set_mcc_setting_chk_start_clnt_join - check change channel under start clnt join\n * @padapter: the adapter to be checked\n * @ch: pointer to rerurn ch\n * @bw: pointer to rerurn bw\n * @offset: pointer to rerurn offset\n * @chbw_allow: allow to use adapter's channel setting\n */\nu8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset, u8 chbw_allow)\n{\n\tu8 ret = _FAIL;\n\n\t/* if chbw_allow = false under en_mcc = TRUE, we do not change channel related setting  */\n\tif (MCC_EN(padapter)) {\n\t\t/* restore union channel related setting to current channel related setting */\n\t\tif (chbw_allow == _FALSE) {\n\t\t\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\n\t\t\t/* issue null data to other interface connected to AP */\n\t\t\trtw_hal_mcc_issue_null_data(padapter, chbw_allow, _TRUE);\n\n\t\t\t*ch = pmlmeext->cur_channel;\n\t\t\t*bw = pmlmeext->cur_bwmode;\n\t\t\t*offset = pmlmeext->cur_ch_offset;\n\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" en_mcc:%d(%d,%d,%d,)\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter), MCC_EN(padapter)\n\t\t\t\t, *ch, *bw, *offset);\n\t\t\tret = _SUCCESS;\n\t\t}\n\t}\n\n\treturn ret;\n}\n\nstatic void rtw_hal_mcc_dump_noa_content(void *sel, PADAPTER padapter)\n{\n\tstruct mcc_adapter_priv *pmccadapriv = NULL;\n\tu8 *pos = NULL;\n\tpmccadapriv = &padapter->mcc_adapterpriv;\n\t/* last position for NoA attribute */\n\tpos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len;\n\n\n\tRTW_PRINT_SEL(sel, \"\\nStart to dump NoA Content\\n\");\n\tRTW_PRINT_SEL(sel, \"NoA Counts:%d\\n\", *(pos - 13));\n\tRTW_PRINT_SEL(sel, \"NoA Duration(TU):%d\\n\", (RTW_GET_LE32(pos - 12))/TU);\n\tRTW_PRINT_SEL(sel, \"NoA Interval(TU):%d\\n\", (RTW_GET_LE32(pos - 8))/TU);\n\tRTW_PRINT_SEL(sel, \"NoA Start time(microseconds):0x%02x\\n\", RTW_GET_LE32(pos - 4));\n\tRTW_PRINT_SEL(sel, \"End to dump NoA Content\\n\");\n}\n\nstatic void mcc_dump_dbg_reg(void *sel, _adapter *adapter)\n{\n\tstruct mcc_obj_priv *mccobjpriv = adapter_to_mccobjpriv(adapter);\n\tHAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);\n\tu8 i,j;\n\t_irqL irqL;\n\n\t_enter_critical_bh(&mccobjpriv->mcc_lock, &irqL);\n\tRTW_PRINT_SEL(sel, \"current order=%d\\n\", mccobjpriv->current_order);\n\t_exit_critical_bh(&mccobjpriv->mcc_lock, &irqL);\n\n\t_enter_critical_mutex(&mccobjpriv->mcc_dbg_reg_mutex, NULL);\n\tfor (i = 0; i < ARRAY_SIZE(mccobjpriv->dbg_reg); i++)\n\t\t\tRTW_PRINT_SEL(sel, \"REG_0x%X:0x%08x\\n\", mccobjpriv->dbg_reg[i], mccobjpriv->dbg_reg_val[i]);\n\n\tfor (i = 0; i < ARRAY_SIZE(mccobjpriv->dbg_rf_reg); i++) {\n\t\tfor (j = 0; j < hal->NumTotalRFPath; j++)\n\t\t\tRTW_PRINT_SEL(sel, \"RF_PATH_%d_REG_0x%X:0x%08x\\n\",\n\t\t\t\tj, mccobjpriv->dbg_rf_reg[i], mccobjpriv->dbg_rf_reg_val[i][j]);\n\t}\n\t_exit_critical_mutex(&mccobjpriv->mcc_dbg_reg_mutex, NULL);\n}\n\n\nvoid rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj)\n{\n\tstruct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);\n\tstruct mcc_adapter_priv *mccadapriv = NULL;\n\t_adapter *iface = NULL, *pri_adapter = NULL;\n\tstruct registry_priv *regpriv = NULL;\n\tHAL_DATA_TYPE *hal = NULL;\n\tu8 i = 0, j = 0;\n\tu64 tsf[MAX_MCC_NUM] = {0};\n\n\t/* regpriv is common for all adapter */\n\tpri_adapter = dvobj_get_primary_adapter(dvobj);\n\thal = GET_HAL_DATA(pri_adapter);\n\n\tRTW_PRINT_SEL(sel, \"**********************************************\\n\");\n\tRTW_PRINT_SEL(sel, \"en_mcc:%d\\n\", MCC_EN(pri_adapter));\n\tRTW_PRINT_SEL(sel, \"primary adapter(\"ADPT_FMT\") duration:%d%c\\n\",\n\t\tADPT_ARG(dvobj_get_primary_adapter(dvobj)), mccobjpriv->duration, 37);\n\tRTW_PRINT_SEL(sel, \"runtime duration:%s\\n\", mccobjpriv->enable_runtime_duration ? \"enable\":\"disable\");\n\tRTW_PRINT_SEL(sel, \"phydm offload:%s\\n\", mccobjpriv->mcc_phydm_offload ? \"enable\":\"disable\");\n\n\tif (rtw_hal_check_mcc_status(pri_adapter, MCC_STATUS_DOING_MCC)) {\n\t\trtw_hal_mcc_rqt_tsf(pri_adapter, tsf);\n\n\t\tfor (i = 0; i < MAX_MCC_NUM; i++) {\n\t\t\tiface = mccobjpriv->iface[i];\n\t\t\tif (!iface)\n\t\t\t\tcontinue;\n\n\t\t\tregpriv = &iface->registrypriv;\n\t\t\tmccadapriv = &iface->mcc_adapterpriv;\n\n\t\t\tif (mccadapriv) {\n\t\t\t\tu8 p2p_ps_mode = iface->wdinfo.p2p_ps_mode;\n\n\t\t\t\tRTW_PRINT_SEL(sel, \"adapter mcc info:\\n\");\n\t\t\t\tRTW_PRINT_SEL(sel, \"ifname:%s\\n\", ADPT_ARG(iface));\n\t\t\t\tRTW_PRINT_SEL(sel, \"order:%d\\n\", mccadapriv->order);\n\t\t\t\tRTW_PRINT_SEL(sel, \"duration:%d\\n\", mccadapriv->mcc_duration);\n\t\t\t\tRTW_PRINT_SEL(sel, \"target tx bytes:%d\\n\", mccadapriv->mcc_target_tx_bytes_to_port);\n\t\t\t\tRTW_PRINT_SEL(sel, \"current TP:%d\\n\", mccadapriv->mcc_tp);\n\t\t\t\tRTW_PRINT_SEL(sel, \"mgmt queue macid:%d\\n\", mccadapriv->mgmt_queue_macid);\n\t\t\t\tRTW_PRINT_SEL(sel, \"macid bitmap:0x%02x\\n\", mccadapriv->mcc_macid_bitmap);\n\t\t\t\tRTW_PRINT_SEL(sel, \"P2P NoA:%s\\n\\n\", p2p_ps_mode == P2P_PS_NOA ? \"enable\":\"disable\");\n\t\t\t\tRTW_PRINT_SEL(sel, \"registry data:\\n\");\n\t\t\t\tRTW_PRINT_SEL(sel, \"ap target tx TP(BW:20M):%d Mbps\\n\", regpriv->rtw_mcc_ap_bw20_target_tx_tp);\n\t\t\t\tRTW_PRINT_SEL(sel, \"ap target tx TP(BW:40M):%d Mbps\\n\", regpriv->rtw_mcc_ap_bw40_target_tx_tp);\n\t\t\t\tRTW_PRINT_SEL(sel, \"ap target tx TP(BW:80M):%d Mbps\\n\", regpriv->rtw_mcc_ap_bw80_target_tx_tp);\n\t\t\t\tRTW_PRINT_SEL(sel, \"sta target tx TP(BW:20M):%d Mbps\\n\", regpriv->rtw_mcc_sta_bw20_target_tx_tp);\n\t\t\t\tRTW_PRINT_SEL(sel, \"sta target tx TP(BW:40M ):%d Mbps\\n\", regpriv->rtw_mcc_sta_bw40_target_tx_tp);\n\t\t\t\tRTW_PRINT_SEL(sel, \"sta target tx TP(BW:80M):%d Mbps\\n\", regpriv->rtw_mcc_sta_bw80_target_tx_tp);\n\t\t\t\tRTW_PRINT_SEL(sel, \"single tx criteria:%d Mbps\\n\", regpriv->rtw_mcc_single_tx_cri);\n\t\t\t\tRTW_PRINT_SEL(sel, \"HW TSF=0x%llx\\n\", tsf[mccadapriv->order]);\n\t\t\t\tif (MLME_IS_GO(iface))\n\t\t\t\t\trtw_hal_mcc_dump_noa_content(sel, iface);\n\t\t\t\tRTW_PRINT_SEL(sel, \"**********************************************\\n\");\n\t\t\t}\n\t\t}\n\n\t\tmcc_dump_dbg_reg(sel, pri_adapter);\n\t}\n\n\t#ifdef CONFIG_MCC_PHYDM_OFFLOAD\n\tRTW_PRINT_SEL(sel, \"@@@@@@@@@@@@@@@@@@@@\\n\");\n\trtw_hal_mcc_cfg_phydm(pri_adapter, MCC_CFG_PHYDM_DUMP, sel);\n\tRTW_PRINT_SEL(sel, \"@@@@@@@@@@@@@@@@@@@@\\n\");\n\t#endif\n\t\n\tRTW_PRINT_SEL(sel, \"------------------------------------------\\n\");\n\tRTW_PRINT_SEL(sel, \"policy index:%d\\n\", mccobjpriv->policy_index);\t\n\tRTW_PRINT_SEL(sel, \"------------------------------------------\\n\");\n\tRTW_PRINT_SEL(sel, \"define data:\\n\");\n\tRTW_PRINT_SEL(sel, \"ap target tx TP(BW:20M):%d Mbps\\n\", MCC_AP_BW20_TARGET_TX_TP);\n\tRTW_PRINT_SEL(sel, \"ap target tx TP(BW:40M):%d Mbps\\n\", MCC_AP_BW40_TARGET_TX_TP);\n\tRTW_PRINT_SEL(sel, \"ap target tx TP(BW:80M):%d Mbps\\n\", MCC_AP_BW80_TARGET_TX_TP);\n\tRTW_PRINT_SEL(sel, \"sta target tx TP(BW:20M):%d Mbps\\n\", MCC_STA_BW20_TARGET_TX_TP);\n\tRTW_PRINT_SEL(sel, \"sta target tx TP(BW:40M):%d Mbps\\n\", MCC_STA_BW40_TARGET_TX_TP);\n\tRTW_PRINT_SEL(sel, \"sta target tx TP(BW:80M):%d Mbps\\n\", MCC_STA_BW80_TARGET_TX_TP);\n\tRTW_PRINT_SEL(sel, \"single tx criteria:%d Mbps\\n\", MCC_SINGLE_TX_CRITERIA);\n\tRTW_PRINT_SEL(sel, \"------------------------------------------\\n\");\n}\n\ninline void update_mcc_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib)\n{\n\tif (MCC_EN(padapter)) {\n\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {\n\t\t\t/* use QSLT_MGNT to check mgnt queue or bcn queue */\n\t\t\tif (pattrib->qsel == QSLT_MGNT) {\n\t\t\t\tpattrib->mac_id = padapter->mcc_adapterpriv.mgmt_queue_macid;\n\t\t\t\tpattrib->qsel = QSLT_VO;\n\t\t\t}\n\t\t}\n\t}\n}\n\ninline u8 rtw_hal_mcc_link_status_chk(_adapter *padapter, const char *msg)\n{\n\tu8 ret = _TRUE, i = 0;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\t_adapter *iface;\n\tstruct mlme_ext_priv *mlmeext;\n\n\tif (MCC_EN(padapter)) {\n\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {\n\t\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\t\tiface = dvobj->padapters[i];\n\t\t\t\tmlmeext = &iface->mlmeextpriv;\n\t\t\t\tif (mlmeext_scan_state(mlmeext) != SCAN_DISABLE) {\n\t\t\t\t\t#ifdef DBG_EXPIRATION_CHK\n\t\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" don't enter %s under scan for MCC mode\\n\", FUNC_ADPT_ARG(padapter), msg);\n\t\t\t\t\t#endif\n\t\t\t\t\tret = _FALSE;\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\nexit:\n\treturn ret;\n}\n\nvoid rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\t_adapter *iface = NULL;\n\tsystime start = rtw_get_current_time();\n\tu8 i = 0;\n\n\tif (!MCC_EN(padapter))\n\t\treturn;\n\n\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))\n\t\treturn;\n\n\tif (chbw_allow == _TRUE)\n\t\treturn;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\t/* issue null data to inform ap station will leave */\n\t\tif (is_client_associated_to_ap(iface)) {\n\t\t\tstruct mlme_ext_priv *mlmeext = &iface->mlmeextpriv;\n\t\t\tstruct mlme_ext_info *mlmeextinfo = &mlmeext->mlmext_info;\n\t\t\tu8 ch = mlmeext->cur_channel;\n\t\t\tu8 bw = mlmeext->cur_bwmode;\n\t\t\tu8 offset = mlmeext->cur_ch_offset;\n\t\t\tstruct sta_info *sta = rtw_get_stainfo(&iface->stapriv, get_my_bssid(&(mlmeextinfo->network)));\n\n\t\t\tif (!sta)\n\t\t\t\tcontinue;\n\n\t\t\tset_channel_bwmode(iface, ch, offset, bw);\n\n\t\t\tif (ps_mode)\n\t\t\t\trtw_hal_macid_sleep(iface, sta->cmn.mac_id);\n\t\t\telse\n\t\t\t\trtw_hal_macid_wakeup(iface, sta->cmn.mac_id);\n\n\t\t\tissue_nulldata(iface, NULL, ps_mode, 3, 50);\n\t\t}\n\t}\n\tRTW_INFO(\"%s(%d ms)\\n\", __func__, rtw_get_passing_time_ms(start));\n}\n\nu8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len)\n{\n\tstruct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;\n\n\tif (!MCC_EN(padapter))\n\t\treturn pframe;\n\t\n\tif (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))\n\t\treturn pframe;\n\n\tif (pmccadapriv->p2p_go_noa_ie_len == 0)\n\t\treturn pframe;\n\n\t_rtw_memcpy(pframe, pmccadapriv->p2p_go_noa_ie, pmccadapriv->p2p_go_noa_ie_len);\n\t*len = *len + pmccadapriv->p2p_go_noa_ie_len;\n\n\treturn pframe + pmccadapriv->p2p_go_noa_ie_len;\n}\n\nvoid rtw_hal_dump_mcc_policy_table(void *sel)\n{\n\tu8 idx = 0;\n\tRTW_PRINT_SEL(sel, \"duration\\t,tsf sync offset\\t,start time offset\\t,interval\\t,guard offset0\\t,guard offset1\\n\");\n\n\tfor (idx = 0; idx < mcc_max_policy_num; idx ++) {\n\t\tRTW_PRINT_SEL(sel, \"%d\\t\\t,%d\\t\\t\\t,%d\\t\\t\\t,%d\\t\\t,%d\\t\\t,%d\\n\"\n\t\t\t, mcc_switch_channel_policy_table[idx][MCC_DURATION_IDX]\n\t\t\t, mcc_switch_channel_policy_table[idx][MCC_TSF_SYNC_OFFSET_IDX]\n\t\t\t, mcc_switch_channel_policy_table[idx][MCC_START_TIME_OFFSET_IDX]\n\t\t\t, mcc_switch_channel_policy_table[idx][MCC_INTERVAL_IDX]\n\t\t\t, mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET0_IDX]\n\t\t\t, mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET1_IDX]);\n\t}\n}\n\nvoid rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add)\n{\n\tstruct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;\n\n\tif (!MCC_EN(padapter))\n\t\treturn;\n\n\tif (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))\n\t\treturn;\n\n\tif (pmccadapriv->role == MCC_ROLE_GC || pmccadapriv->role == MCC_ROLE_STA)\n\t\treturn;\n\n\tif (mac_id < 0) {\n\t\tRTW_WARN(\"%s: mac_id < 0(%d)\\n\", __func__, mac_id);\n\t\treturn;\n\t}\n\n\tRTW_INFO(ADPT_FMT\" %s macid=%d, ori mcc_macid_bitmap=0x%08x\\n\"\n\t\t, ADPT_ARG(padapter), add ? \"add\" : \"clear\"\n\t\t, mac_id, pmccadapriv->mcc_macid_bitmap);\n\n\tif (add) {\n\t\t#ifdef CONFIG_MCC_PHYDM_OFFLOAD\n\t\trtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_ADD_CLIENT, &mac_id);\n\t\t#endif\n\t\tpmccadapriv->mcc_macid_bitmap |= BIT(mac_id);\n\t} else {\n\t\t#ifdef CONFIG_MCC_PHYDM_OFFLOAD\n\t\trtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_REMOVE_CLIENT, &mac_id);\n\t\t#endif\n\t\tpmccadapriv->mcc_macid_bitmap &= ~(BIT(mac_id));\n\t}\n\trtw_hal_set_mcc_macid_cmd(padapter);\n}\n\nvoid rtw_hal_mcc_process_noa(PADAPTER padapter)\n{\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);\n\n\tif (!MCC_EN(padapter))\n\t\treturn;\n\n\tif (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))\n\t\treturn;\n\n\tif (!MLME_IS_GC(padapter))\n\t\treturn;\n\n\tswitch(pwdinfo->p2p_ps_mode) {\n\tcase P2P_PS_NONE:\n\t\tRTW_INFO(\"[MCC] Disable NoA under MCC\\n\");\n\t\trtw_hal_mcc_update_parameter(padapter, _TRUE);\n\t\tbreak;\n\tcase P2P_PS_NOA:\n\t\tRTW_INFO(\"[MCC] Enable NoA under MCC\\n\");\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\n\t}\n}\n\nvoid rtw_hal_mcc_parameter_init(PADAPTER padapter)\n{\n\tif (!padapter->registrypriv.en_mcc)\n\t\treturn;\n\n\tif (is_primary_adapter(padapter)) {\n\t\tSET_MCC_EN_FLAG(padapter, padapter->registrypriv.en_mcc);\n\t\tSET_MCC_DURATION(padapter, padapter->registrypriv.rtw_mcc_duration);\n\t\tSET_MCC_RUNTIME_DURATION(padapter, padapter->registrypriv.rtw_mcc_enable_runtime_duration);\n\t\tSET_MCC_PHYDM_OFFLOAD(padapter, padapter->registrypriv.rtw_mcc_phydm_offload);\n\t}\n}\n\n\nstatic u8 set_mcc_duration_hdl(PADAPTER adapter, const u8 *val)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);\n\t_adapter *iface = NULL;\n\tu8 duration = 50;\n\tu8 ret = _SUCCESS, noa_enable = _FALSE, i = 0;\n\tenum mcc_duration_setting type;\n\n\tif (!mccobjpriv->enable_runtime_duration)\n\t\tgoto exit;\n\n#ifdef CONFIG_P2P_PS\n\t/* check noa enable or not */\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) {\n\t\t\tnoa_enable = _TRUE;\n\t\t\tbreak;\n\t\t}\n\t}\n#endif /* CONFIG_P2P_PS */\n\n\ttype = val[0];\n\tduration = val[1];\n\n\tif (type == MCC_DURATION_MAPPING) {\n\t\tswitch (duration) {\n\t\t\t/* 0 = fair scheduling */\n\t\t\tcase 0:\n\t\t\t\tmccobjpriv->duration= 40;\n\t\t\t\tmccobjpriv->policy_index = 2;\n\t\t\t\tmccobjpriv->mchan_sched_mode = MCC_FAIR_SCHEDULE;\n\t\t\t\tbreak;\n\t\t\t/* 1 = favor STA */\n\t\t\tcase 1:\n\t\t\t\tmccobjpriv->duration= 70;\n\t\t\t\tmccobjpriv->policy_index = 1;\n\t\t\t\tmccobjpriv->mchan_sched_mode = MCC_FAVOR_STA;\n\t\t\t\tbreak;\n\t\t\t/* 2 = favor P2P*/\n\t\t\tcase 2:\n\t\t\tdefault:\n\t\t\t\tmccobjpriv->duration= 30;\n\t\t\t\tmccobjpriv->policy_index = 0;\n\t\t\t\tmccobjpriv->mchan_sched_mode = MCC_FAVOR_P2P;\n\t\t\t\tbreak;\n\t\t}\n\t} else {\n\t\tmccobjpriv->duration = duration;\n\t\trtw_hal_mcc_update_policy_table(adapter);\n\t}\n\n\t/* only update sw parameter under MCC \n\t    it will be force update during */\n\tif (noa_enable)\n\t\tgoto exit;\n\n\tif (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))\n\t\trtw_hal_mcc_update_parameter(adapter, _TRUE);\nexit:\n\treturn ret;\n}\n\nu8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val)\n{\n\tstruct cmd_obj *cmdobj;\n\tstruct drvextra_cmd_parm *pdrvextra_cmd_parm;\n\tstruct cmd_priv *pcmdpriv = &adapter->cmdpriv;\n\tu8 *buf = NULL;\n\tu8 sz = 2;\n\tu8 res = _SUCCESS;\n\n\t\n\tcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\tif (cmdobj == NULL) {\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\tif (pdrvextra_cmd_parm == NULL) {\n\t\trtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tbuf = rtw_zmalloc(sizeof(u8) * sz);\n\tif (buf == NULL) {\n\t\trtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));\n\t\trtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));\n\t\tres = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpdrvextra_cmd_parm->ec_id = MCC_CMD_WK_CID;\n\tpdrvextra_cmd_parm->type = MCC_SET_DURATION_WK_CID;\n\tpdrvextra_cmd_parm->size = sz;\n\tpdrvextra_cmd_parm->pbuf = buf;\n\n\t_rtw_memcpy(buf, &type, 1);\n\t_rtw_memcpy(buf + 1, &val, 1);\n\n\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\tres = rtw_enqueue_cmd(pcmdpriv, cmdobj);\n\nexit:\n\treturn res;\n}\n\n#ifdef CONFIG_MCC_PHYDM_OFFLOAD\nstatic u8 mcc_phydm_offload_enable_hdl(_adapter *adapter, const u8 *val)\n{\n\tstruct mcc_obj_priv *mccobjpriv =  adapter_to_mccobjpriv(adapter);\n\tu8 ret = _SUCCESS;\n\tu8 enable = *val;\n\n\t/*only modify driver parameter during non-mcc status */\n\tif (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {\n\t\tmccobjpriv->mcc_phydm_offload = enable;\n\t} else {\n\t\t/*modify both driver & phydm parameter during mcc status */\n\t\tmccobjpriv->mcc_phydm_offload = enable;\n\t\trtw_hal_mcc_cfg_phydm(adapter, MCC_CFG_PHYDM_OFFLOAD, &mccobjpriv->mcc_phydm_offload);\n\t}\n\n\tRTW_INFO(\"[MCC] phydm offload enable hdl(%d)\\n\", mccobjpriv->mcc_phydm_offload);\n\n\treturn ret;\n}\n\nu8 rtw_set_mcc_phydm_offload_enable_cmd(_adapter *adapter, u8 enable, u8 enqueue)\n{\n\tu8 res = _SUCCESS;\n\n\tif (enqueue) {\n\t\tstruct cmd_obj *cmdobj;\n\t\tstruct drvextra_cmd_parm *pdrvextra_cmd_parm;\n\t\tstruct cmd_priv *pcmdpriv = &adapter->cmdpriv;\n\t\tu8 *mcc_phydm_offload_enable = NULL;\n\n\t\t\n\t\tcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));\n\t\tif (cmdobj == NULL) {\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));\n\t\tif (pdrvextra_cmd_parm == NULL) {\n\t\t\trtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tmcc_phydm_offload_enable = rtw_zmalloc(sizeof(u8));\n\t\tif (mcc_phydm_offload_enable == NULL) {\n\t\t\trtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));\n\t\t\trtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));\n\t\t\tres = _FAIL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tpdrvextra_cmd_parm->ec_id = MCC_CMD_WK_CID;\n\t\tpdrvextra_cmd_parm->type = MCC_SET_PHYDM_OFFLOAD_WK_CID;\n\t\tpdrvextra_cmd_parm->size = 1;\n\t\tpdrvextra_cmd_parm->pbuf = mcc_phydm_offload_enable;\n\n\t\t_rtw_memcpy(mcc_phydm_offload_enable, &enable, 1);\n\t\tinit_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));\n\t\tres = rtw_enqueue_cmd(pcmdpriv, cmdobj);\n\t} else {\n\t\tmcc_phydm_offload_enable_hdl(adapter, &enable);\n\t}\n\nexit:\n\treturn res;\n}\n#endif\n\nu8 rtw_mcc_cmd_hdl(_adapter *adapter, u8 type, const u8 *val)\n{\n\tstruct mcc_obj_priv *mccobjpriv =  adapter_to_mccobjpriv(adapter);\n\tu8 ret = _SUCCESS;\n\n\tswitch (type) {\n\tcase MCC_SET_DURATION_WK_CID:\n\t\tset_mcc_duration_hdl(adapter, val);\n\t\tbreak;\n\tcase MCC_GET_DBG_REG_WK_CID:\n\t\tmcc_get_reg_hdl(adapter, val);\n\t\tbreak;\n\t#ifdef CONFIG_MCC_PHYDM_OFFLOAD\n\tcase MCC_SET_PHYDM_OFFLOAD_WK_CID:\n\t\tmcc_phydm_offload_enable_hdl(adapter, val);\n\t\tbreak;\n\t#endif\n\tdefault:\n\t\tRTW_ERR(\"[MCC] rtw_mcc_cmd_hdl fail(%d)\\n\", type);\n\t\tbreak;\n\t}\n\n\n\n\treturn ret;\n}\n\n#endif /* CONFIG_MCC_MODE */\n"
  },
  {
    "path": "hal/hal_mp.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _HAL_MP_C_\n\n#include <drv_types.h>\n\n#ifdef CONFIG_MP_INCLUDED\n\n#ifdef RTW_HALMAC\n\t#include <hal_data.h>\t\t/* struct HAL_DATA_TYPE, RF register definition and etc. */\n#else /* !RTW_HALMAC */\n\t#ifdef CONFIG_RTL8188E\n\t\t#include <rtl8188e_hal.h>\n\t#endif\n\t#ifdef CONFIG_RTL8723B\n\t\t#include <rtl8723b_hal.h>\n\t#endif\n\t#ifdef CONFIG_RTL8192E\n\t\t#include <rtl8192e_hal.h>\n\t#endif\n\t#ifdef CONFIG_RTL8814A\n\t\t#include <rtl8814a_hal.h>\n\t#endif\n\t#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\n\t\t#include <rtl8812a_hal.h>\n\t#endif\n\t#ifdef CONFIG_RTL8703B\n\t\t#include <rtl8703b_hal.h>\n\t#endif\n\t#ifdef CONFIG_RTL8723D\n\t\t#include <rtl8723d_hal.h>\n\t#endif\n\t#ifdef CONFIG_RTL8710B\n\t\t#include <rtl8710b_hal.h>\n\t#endif\n\t#ifdef CONFIG_RTL8188F\n\t\t#include <rtl8188f_hal.h>\n\t#endif\n\t#ifdef CONFIG_RTL8188GTV\n\t\t#include <rtl8188gtv_hal.h>\n\t#endif\n\t#ifdef CONFIG_RTL8192F\n\t\t#include <rtl8192f_hal.h>\n\t#endif\n#endif /* !RTW_HALMAC */\n\n\nu8 MgntQuery_NssTxRate(u16 Rate)\n{\n\tu8\tNssNum = RF_TX_NUM_NONIMPLEMENT;\n\n\tif ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||\n\t    (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))\n\t\tNssNum = RF_2TX;\n\telse if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||\n\t\t (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))\n\t\tNssNum = RF_3TX;\n\telse if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||\n\t\t (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))\n\t\tNssNum = RF_4TX;\n\telse\n\t\tNssNum = RF_1TX;\n\n\treturn NssNum;\n}\n\nvoid hal_mpt_SwitchRfSetting(PADAPTER\tpAdapter)\n{\n\tHAL_DATA_TYPE\t\t*pHalData = GET_HAL_DATA(pAdapter);\n\tPMPT_CONTEXT\t\tpMptCtx = &(pAdapter->mppriv.mpt_ctx);\n\tu8\t\t\t\tChannelToSw = pMptCtx->MptChannelToSw;\n\tu32\t\t\t\tulRateIdx = pMptCtx->mpt_rate_index;\n\tu32\t\t\t\tulbandwidth = pMptCtx->MptBandWidth;\n\n\t/* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/\n\tif (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&\n\t    (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {\n\t\tpMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);\n\t\tpMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);\n\n\t\tif ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {\n\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB);\n\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB);\n\t\t} else {\n\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);\n\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);\n\t\t}\n\t} else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/\n\t\tif (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {\n\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/\n\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/\n\t\t} else {\n\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/\n\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/\n\t\t}\n\t} else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);\n\t}\n}\n\ns32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct dm_struct\t\t*pDM_Odm = &(pHalData->odmpriv);\n\n\n\tif (!netif_running(padapter->pnetdev)) {\n\t\treturn _FAIL;\n\t}\n\n\tif (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {\n\t\treturn _FAIL;\n\t}\n\tif (enable)\n\t\tpDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;\n\telse\n\t\tpDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;\n\n\treturn _SUCCESS;\n}\n\nvoid hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct dm_struct\t\t*pDM_Odm = &(pHalData->odmpriv);\n\n\n\t*enable = pDM_Odm->rf_calibrate_info.txpowertrack_control;\n}\n\n\nvoid hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)\n{\n\tu32\t\tTempVal = 0, TempVal2 = 0, TempVal3 = 0;\n\tu32\t\tCurrCCKSwingVal = 0, CCKSwingIndex = 12;\n\tu8\t\ti;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(Adapter);\n\tPMPT_CONTEXT\t\tpMptCtx = &(Adapter->mppriv.mpt_ctx);\n\tu8\t\t\t\tu1Channel = pHalData->current_channel;\n\tu32\t\t\t\tulRateIdx = pMptCtx->mpt_rate_index;\n\tu8\t\t\t\tDataRate = 0xFF;\n\n\t/* Do not modify CCK TX filter parameters for 8822B*/\n\tif(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) ||\n\t\tIS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8192F(Adapter) || IS_HARDWARE_TYPE_8822C(Adapter))\n\t\treturn;\n\n\tDataRate = mpt_to_mgnt_rate(ulRateIdx);\n\n\tif (u1Channel == 14 && IS_CCK_RATE(DataRate))\n\t\tpHalData->bCCKinCH14 = TRUE;\n\telse\n\t\tpHalData->bCCKinCH14 = FALSE;\n\n\tif (IS_HARDWARE_TYPE_8703B(Adapter)) {\n\t\tif ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {\n\t\t\t/* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */\n\t\t\tphy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);\n\t\t\tphy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);\n\n\t\t} else {\n\t\t\t/* Normal setting for 8703B, just recover to the default setting. */\n\t\t\t/* This hardcore values reference from the parameter which BB team gave. */\n\t\t\tfor (i = 0 ; i < 2 ; ++i)\n\t\t\t\tphy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);\n\n\t\t}\n\t} else if (IS_HARDWARE_TYPE_8723D(Adapter)) {\n\t\t/* 2.4G CCK TX DFIR */\n\t\t/* 2016.01.20 Suggest from RS BB mingzhi*/\n\t\tif ((u1Channel == 14)) {\n\t\t\tphy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);\n\t\t\tphy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);\n\t\t\tphy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667);\n\t\t} else {\n\t\t\tfor (i = 0 ; i < 3 ; ++i) {\n\t\t\t\tphy_set_bb_reg(Adapter,\n\t\t\t\t\t     pHalData->RegForRecover[i].offset,\n\t\t\t\t\t     bMaskDWord,\n\t\t\t\t\t     pHalData->RegForRecover[i].value);\n\t\t\t}\n\t\t}\n\t} else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {\n\t\t/* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/\n\t\tCurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);\n\t\tCCKSwingIndex = 20; /* default index */\n\n\t\tif (!pHalData->bCCKinCH14) {\n\t\t\t/* Readback the current bb cck swing value and compare with the table to */\n\t\t\t/* get the current swing index */\n\t\t\tfor (i = 0; i < CCK_TABLE_SIZE_88F; i++) {\n\t\t\t\tif (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) &&\n\t\t\t\t    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) {\n\t\t\t\t\tCCKSwingIndex = i;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\twrite_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]);\n\t\t\twrite_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]);\n\t\t\twrite_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]);\n\t\t\twrite_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]);\n\t\t\twrite_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]);\n\t\t\twrite_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]);\n\t\t\twrite_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]);\n\t\t\twrite_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]);\n\t\t\twrite_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]);\n\t\t\twrite_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]);\n\t\t\twrite_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]);\n\t\t\twrite_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]);\n\t\t\twrite_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]);\n\t\t\twrite_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]);\n\t\t\twrite_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]);\n\t\t\twrite_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]);\n\t\t\tRTW_INFO(\"%s , cck_swing_table_ch1_ch13_88f[%d]\\n\", __func__, CCKSwingIndex);\n\t\t}  else {\n\t\t\tfor (i = 0; i < CCK_TABLE_SIZE_88F; i++) {\n\t\t\t\tif (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) &&\n\t\t\t\t    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) {\n\t\t\t\t\tCCKSwingIndex = i;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\twrite_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]);\n\t\t\twrite_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]);\n\t\t\twrite_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]);\n\t\t\twrite_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]);\n\t\t\twrite_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]);\n\t\t\twrite_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]);\n\t\t\twrite_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]);\n\t\t\twrite_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]);\n\t\t\twrite_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]);\n\t\t\twrite_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]);\n\t\t\twrite_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]);\n\t\t\twrite_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]);\n\t\t\twrite_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]);\n\t\t\twrite_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]);\n\t\t\twrite_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]);\n\t\t\twrite_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]);\n\t\t\tRTW_INFO(\"%s , cck_swing_table_ch14_88f[%d]\\n\", __func__, CCKSwingIndex);\n\t\t}\n\t} else {\n\n\t\t/* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/\n\t\tCurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);\n\n\t\tif (!pHalData->bCCKinCH14) {\n\t\t\t/* Readback the current bb cck swing value and compare with the table to */\n\t\t\t/* get the current swing index */\n\t\t\tfor (i = 0; i < CCK_TABLE_SIZE; i++) {\n\t\t\t\tif (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13[i][0]) &&\n\t\t\t\t    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13[i][1])) {\n\t\t\t\t\tCCKSwingIndex = i;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/*Write 0xa22 0xa23*/\n\t\t\tTempVal = cck_swing_table_ch1_ch13[CCKSwingIndex][0] +\n\t\t\t\t(cck_swing_table_ch1_ch13[CCKSwingIndex][1] << 8);\n\n\n\t\t\t/*Write 0xa24 ~ 0xa27*/\n\t\t\tTempVal2 = 0;\n\t\t\tTempVal2 = cck_swing_table_ch1_ch13[CCKSwingIndex][2] +\n\t\t\t\t(cck_swing_table_ch1_ch13[CCKSwingIndex][3] << 8) +\n\t\t\t\t(cck_swing_table_ch1_ch13[CCKSwingIndex][4] << 16) +\n\t\t\t\t(cck_swing_table_ch1_ch13[CCKSwingIndex][5] << 24);\n\n\t\t\t/*Write 0xa28  0xa29*/\n\t\t\tTempVal3 = 0;\n\t\t\tTempVal3 = cck_swing_table_ch1_ch13[CCKSwingIndex][6] +\n\t\t\t\t(cck_swing_table_ch1_ch13[CCKSwingIndex][7] << 8);\n\t\t}  else {\n\t\t\tfor (i = 0; i < CCK_TABLE_SIZE; i++) {\n\t\t\t\tif (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14[i][0]) &&\n\t\t\t\t    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14[i][1])) {\n\t\t\t\t\tCCKSwingIndex = i;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/*Write 0xa22 0xa23*/\n\t\t\tTempVal = cck_swing_table_ch14[CCKSwingIndex][0] +\n\t\t\t\t  (cck_swing_table_ch14[CCKSwingIndex][1] << 8);\n\n\t\t\t/*Write 0xa24 ~ 0xa27*/\n\t\t\tTempVal2 = 0;\n\t\t\tTempVal2 = cck_swing_table_ch14[CCKSwingIndex][2] +\n\t\t\t\t   (cck_swing_table_ch14[CCKSwingIndex][3] << 8) +\n\t\t\t\t(cck_swing_table_ch14[CCKSwingIndex][4] << 16) +\n\t\t\t\t   (cck_swing_table_ch14[CCKSwingIndex][5] << 24);\n\n\t\t\t/*Write 0xa28  0xa29*/\n\t\t\tTempVal3 = 0;\n\t\t\tTempVal3 = cck_swing_table_ch14[CCKSwingIndex][6] +\n\t\t\t\t   (cck_swing_table_ch14[CCKSwingIndex][7] << 8);\n\t\t}\n\n\t\twrite_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);\n\t\twrite_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);\n\t\twrite_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);\n\t}\n\n}\n\nvoid hal_mpt_SetChannel(PADAPTER pAdapter)\n{\n\tenum rf_path eRFPath;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\tstruct dm_struct\t\t*pDM_Odm = &(pHalData->odmpriv);\n\tstruct mp_priv\t*pmp = &pAdapter->mppriv;\n\tu8\t\tchannel = pmp->channel;\n\tu8\t\tbandwidth = pmp->bandwidth;\n\n\thal_mpt_SwitchRfSetting(pAdapter);\n\n\tpHalData->bSwChnl = _TRUE;\n\tpHalData->bSetChnlBW = _TRUE;\n\n\tif (bandwidth == 2) {\n\t\trtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);\n\t} else if (bandwidth == 1) {\n\t\trtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);\n\t} else\n\t\trtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);\n\n\thal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);\n\trtw_btcoex_wifionly_scan_notify(pAdapter);\n\n}\n\n/*\n * Notice\n *\tSwitch bandwitdth may change center frequency(channel)\n */\nvoid hal_mpt_SetBandwidth(PADAPTER pAdapter)\n{\n\tstruct mp_priv *pmp = &pAdapter->mppriv;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\n\tu8\t\tchannel = pmp->channel;\n\tu8\t\tbandwidth = pmp->bandwidth;\n\n\tpHalData->bSwChnl = _TRUE;\n\tpHalData->bSetChnlBW = _TRUE;\n\n\tif (bandwidth == 2) {\n\t\trtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);\n\t} else if (bandwidth == 1) {\n\t\trtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);\n\t} else\n\t\trtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);\n\n\thal_mpt_SwitchRfSetting(pAdapter);\n\trtw_btcoex_wifionly_scan_notify(pAdapter);\n\n}\n\nvoid mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)\n{\n\tswitch (Rate) {\n\tcase MPT_CCK: {\n\t\tu32\tTxAGC = 0, pwr = 0;\n\t\tu8\trf;\n\n\t\tpwr = pTxPower[RF_PATH_A];\n\t\tif (pwr < 0x3f) {\n\t\t\tTxAGC = (pwr << 16) | (pwr << 8) | (pwr);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[RF_PATH_A]);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);\n\t\t}\n\t\tpwr = pTxPower[RF_PATH_B];\n\t\tif (pwr < 0x3f) {\n\t\t\tTxAGC = (pwr << 16) | (pwr << 8) | (pwr);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[RF_PATH_B]);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);\n\t\t}\n\t}\n\tbreak;\n\n\tcase MPT_OFDM_AND_HT: {\n\t\tu32\tTxAGC = 0;\n\t\tu8\tpwr = 0, rf;\n\n\t\tpwr = pTxPower[0];\n\t\tif (pwr < 0x3f) {\n\t\t\tTxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);\n\t\t\tRTW_INFO(\"HT Tx-rf(A) Power = 0x%x\\n\", TxAGC);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);\n\t\t}\n\t\tTxAGC = 0;\n\t\tpwr = pTxPower[1];\n\t\tif (pwr < 0x3f) {\n\t\t\tTxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);\n\t\t\tRTW_INFO(\"HT Tx-rf(B) Power = 0x%x\\n\", TxAGC);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);\n\t\t}\n\t}\n\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\tRTW_INFO(\"<===mpt_SetTxPower_Old()\\n\");\n}\n\nvoid\nmpt_SetTxPower(\n\tPADAPTER\t\tpAdapter,\n\tMPT_TXPWR_DEF\tRate,\n\tu8 *pTxPower\n)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\n\tu8 path = 0 , i = 0, MaxRate = MGN_6M;\n\tu8 StartPath = RF_PATH_A, EndPath = RF_PATH_B;\n\n\tif (IS_HARDWARE_TYPE_8814A(pAdapter))\n\t\tEndPath = RF_PATH_D;\n\telse if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)\n\t\t|| IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))\n\t\tEndPath = RF_PATH_A;\n\n\tswitch (Rate) {\n\tcase MPT_CCK: {\n\t\tu8 rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};\n\n\t\tfor (path = StartPath; path <= EndPath; path++)\n\t\t\tfor (i = 0; i < sizeof(rate); ++i)\n\t\t\t\tPHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);\n\t}\n\tbreak;\n\tcase MPT_OFDM: {\n\t\tu8 rate[] = {\n\t\t\tMGN_6M, MGN_9M, MGN_12M, MGN_18M,\n\t\t\tMGN_24M, MGN_36M, MGN_48M, MGN_54M,\n\t\t};\n\n\t\tfor (path = StartPath; path <= EndPath; path++)\n\t\t\tfor (i = 0; i < sizeof(rate); ++i)\n\t\t\t\tPHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);\n\t}\n\tbreak;\n\tcase MPT_HT: {\n\t\tu8 rate[] = {\n\t\t\tMGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,\n\t\t\tMGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,\n\t\t\tMGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,\n\t\t\tMGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,\n\t\t\tMGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,\n\t\t\tMGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,\n\t\t\tMGN_MCS30, MGN_MCS31,\n\t\t};\n\t\tif (pHalData->rf_type == RF_3T3R)\n\t\t\tMaxRate = MGN_MCS23;\n\t\telse if (pHalData->rf_type == RF_2T2R)\n\t\t\tMaxRate = MGN_MCS15;\n\t\telse\n\t\t\tMaxRate = MGN_MCS7;\n\t\tfor (path = StartPath; path <= EndPath; path++) {\n\t\t\tfor (i = 0; i < sizeof(rate); ++i) {\n\t\t\t\tif (rate[i] > MaxRate)\n\t\t\t\t\tbreak;\n\t\t\t\tPHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);\n\t\t\t}\n\t\t}\n\t}\n\tbreak;\n\tcase MPT_VHT: {\n\t\tu8 rate[] = {\n\t\t\tMGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,\n\t\t\tMGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,\n\t\t\tMGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,\n\t\t\tMGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,\n\t\t\tMGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,\n\t\t\tMGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,\n\t\t\tMGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,\n\t\t\tMGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,\n\t\t};\n\t\tif (pHalData->rf_type == RF_3T3R)\n\t\t\tMaxRate = MGN_VHT3SS_MCS9;\n\t\telse if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)\n\t\t\tMaxRate = MGN_VHT2SS_MCS9;\n\t\telse\n\t\t\tMaxRate = MGN_VHT1SS_MCS9;\n\n\t\tfor (path = StartPath; path <= EndPath; path++) {\n\t\t\tfor (i = 0; i < sizeof(rate); ++i) {\n\t\t\t\tif (rate[i] > MaxRate)\n\t\t\t\t\tbreak;\n\t\t\t\tPHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);\n\t\t\t}\n\t\t}\n\t}\n\tbreak;\n\tdefault:\n\t\tRTW_INFO(\"<===mpt_SetTxPower: Illegal channel!!\\n\");\n\t\tbreak;\n\t}\n}\n\nvoid hal_mpt_SetTxPower(PADAPTER pAdapter)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\n\tPMPT_CONTEXT\t\tpMptCtx = &(pAdapter->mppriv.mpt_ctx);\n\tstruct dm_struct\t\t*pDM_Odm = &pHalData->odmpriv;\n\n\tif (pHalData->rf_chip < RF_CHIP_MAX) {\n\t\tif (IS_HARDWARE_TYPE_8188E(pAdapter) ||\n\t\t    IS_HARDWARE_TYPE_8723B(pAdapter) ||\n\t\t    IS_HARDWARE_TYPE_8192E(pAdapter) ||\n\t\t    IS_HARDWARE_TYPE_8703B(pAdapter) ||\n\t\t    IS_HARDWARE_TYPE_8188F(pAdapter) ||\n\t\t    IS_HARDWARE_TYPE_8188GTV(pAdapter)\n\t\t) {\n\t\t\tu8 path = (pHalData->antenna_tx_path == ANTENNA_A) ? (RF_PATH_A) : (RF_PATH_B);\n\n\t\t\tRTW_INFO(\"===> MPT_ProSetTxPower: Old\\n\");\n\n\t\t\tmpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);\n\t\t\tmpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);\n\n\t\t} else {\n\n\t\t\tmpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);\n\t\t\tmpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);\n\t\t\tmpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);\n\t\t\tif(IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {\n\t\t\t\tRTW_INFO(\"===> MPT_ProSetTxPower: Jaguar/Jaguar2\\n\");\n\t\t\t\tmpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);\n\t\t\t}\n\t\t}\n\n\t\trtw_hal_set_txpwr_done(pAdapter);\n\t} else\n\t\tRTW_INFO(\"RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\\n\", pHalData->rf_chip);\n\n\todm_clear_txpowertracking_state(pDM_Odm);\n}\n\nvoid hal_mpt_SetDataRate(PADAPTER pAdapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\tPMPT_CONTEXT\t\tpMptCtx = &(pAdapter->mppriv.mpt_ctx);\n\tu32 DataRate;\n\n\tDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);\n\n\thal_mpt_SwitchRfSetting(pAdapter);\n\n\thal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);\n#ifdef CONFIG_RTL8723B\n\tif (IS_HARDWARE_TYPE_8723B(pAdapter)) {\n\t\tif (IS_CCK_RATE(DataRate)) {\n\t\t\tif (pMptCtx->mpt_rf_path == RF_PATH_A)\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0x6);\n\t\t\telse\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0x6);\n\t\t} else {\n\t\t\tif (pMptCtx->mpt_rf_path == RF_PATH_A)\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);\n\t\t\telse\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);\n\t\t}\n\t}\n\n\tif ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&\n\t     ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {\n\t\tif (pMptCtx->mpt_rf_path == RF_PATH_A)\n\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);\n\t\telse\n\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);\n\t}\n#endif\n}\n\n#define RF_PATH_AB\t22\n\n#ifdef CONFIG_RTL8814A\nvoid mpt_ToggleIG_8814A(PADAPTER\tpAdapter)\n{\n\tu8 Path;\n\tu32 IGReg = rA_IGI_Jaguar, IGvalue = 0;\n\n\tfor (Path = 0; Path <= RF_PATH_D; Path++) {\n\t\tswitch (Path) {\n\t\tcase RF_PATH_B:\n\t\t\tIGReg = rB_IGI_Jaguar;\n\t\t\tbreak;\n\t\tcase RF_PATH_C:\n\t\t\tIGReg = rC_IGI_Jaguar2;\n\t\t\tbreak;\n\t\tcase RF_PATH_D:\n\t\t\tIGReg = rD_IGI_Jaguar2;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tIGReg = rA_IGI_Jaguar;\n\t\t\tbreak;\n\t\t}\n\n\t\tIGvalue = phy_query_bb_reg(pAdapter, IGReg, bMaskByte0);\n\t\tphy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);\n\t\tphy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue);\n\t}\n}\n\nvoid mpt_SetRFPath_8814A(PADAPTER\tpAdapter)\n{\n\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\tPMPT_CONTEXT\tpMptCtx = &pAdapter->mppriv.mpt_ctx;\n\tR_ANTENNA_SELECT_OFDM\t*p_ofdm_tx;\t/* OFDM Tx register */\n\tR_ANTENNA_SELECT_CCK\t*p_cck_txrx;\n\tu8\tForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);\n\t/*/PRT_HIGH_THROUGHPUT\t\tpHTInfo = GET_HT_INFO(pMgntInfo);*/\n\t/*/PRT_VERY_HIGH_THROUGHPUT\tpVHTInfo = GET_VHT_INFO(pMgntInfo);*/\n\n\tu32\tulAntennaTx = pHalData->antenna_tx_path;\n\tu32\tulAntennaRx = pHalData->AntennaRxPath;\n\tu8\tNssforRate = MgntQuery_NssTxRate(ForcedDataRate);\n\n\tif (NssforRate == RF_3TX) {\n\t\tRTW_INFO(\"===> SetAntenna 3T Rate ForcedDataRate %d NssforRate %d AntennaTx %d\\n\", ForcedDataRate, NssforRate, ulAntennaTx);\n\n\t\tswitch (ulAntennaTx) {\n\t\tcase ANTENNA_BCD:\n\t\t\tpMptCtx->mpt_rf_path = RF_PATH_BCD;\n\t\t\t/*pHalData->ValidTxPath = 0x0e;*/\n\t\t\tphy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e);\t/*/ 0x940[27:16]=12'b0010_0100_0111*/\n\t\t\tbreak;\n\n\t\tcase ANTENNA_ABC:\n\t\tdefault:\n\t\t\tpMptCtx->mpt_rf_path = RF_PATH_ABC;\n\t\t\t/*pHalData->ValidTxPath = 0x0d;*/\n\t\t\tphy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247);\t/*/ 0x940[27:16]=12'b0010_0100_0111*/\n\t\t\tbreak;\n\t\t}\n\n\t} else { /*/if(NssforRate == RF_1TX)*/\n\t\tRTW_INFO(\"===> SetAntenna for 1T/2T Rate, ForcedDataRate %d NssforRate %d AntennaTx %d\\n\", ForcedDataRate, NssforRate, ulAntennaTx);\n\t\tswitch (ulAntennaTx) {\n\t\tcase ANTENNA_BCD:\n\t\t\tpMptCtx->mpt_rf_path = RF_PATH_BCD;\n\t\t\t/*pHalData->ValidTxPath = 0x0e;*/\n\t\t\tphy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);\n\t\t\tphy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);\n\t\t\tbreak;\n\n\t\tcase ANTENNA_BC:\n\t\t\tpMptCtx->mpt_rf_path = RF_PATH_BC;\n\t\t\t/*pHalData->ValidTxPath = 0x06;*/\n\t\t\tphy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);\n\t\t\tphy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);\n\t\t\tphy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);\n\t\t\tbreak;\n\t\tcase ANTENNA_B:\n\t\t\tpMptCtx->mpt_rf_path = RF_PATH_B;\n\t\t\t/*pHalData->ValidTxPath = 0x02;*/\n\t\t\tphy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4);\t\t\t/*/ 0xa07[7:4] = 4'b0100*/\n\t\t\tphy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002);\t/*/ 0x93C[31:20]=12'b0000_0000_0010*/\n\t\t\tphy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2);\t\t\t\t\t/* 0x80C[7:4] = 4'b0010*/\n\t\t\tbreak;\n\n\t\tcase ANTENNA_C:\n\t\t\tpMptCtx->mpt_rf_path = RF_PATH_C;\n\t\t\t/*pHalData->ValidTxPath = 0x04;*/\n\t\t\tphy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2);\t\t\t/*/ 0xa07[7:4] = 4'b0010*/\n\t\t\tphy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004);\t/*/ 0x93C[31:20]=12'b0000_0000_0100*/\n\t\t\tphy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4);\t\t\t\t\t/*/ 0x80C[7:4] = 4'b0100*/\n\t\t\tbreak;\n\n\t\tcase ANTENNA_D:\n\t\t\tpMptCtx->mpt_rf_path = RF_PATH_D;\n\t\t\t/*pHalData->ValidTxPath = 0x08;*/\n\t\t\tphy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1);\t\t\t/*/ 0xa07[7:4] = 4'b0001*/\n\t\t\tphy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008);\t/*/ 0x93C[31:20]=12'b0000_0000_1000*/\n\t\t\tphy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8);\t\t\t\t\t/*/ 0x80C[7:4] = 4'b1000*/\n\t\t\tbreak;\n\n\t\tcase ANTENNA_A:\n\t\tdefault:\n\t\t\tpMptCtx->mpt_rf_path = RF_PATH_A;\n\t\t\t/*pHalData->ValidTxPath = 0x01;*/\n\t\t\tphy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8);\t\t\t/*/ 0xa07[7:4] = 4'b1000*/\n\t\t\tphy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001);\t/*/ 0x93C[31:20]=12'b0000_0000_0001*/\n\t\t\tphy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1);\t\t\t\t\t/*/ 0x80C[7:4] = 4'b0001*/\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tswitch (ulAntennaRx) {\n\tcase ANTENNA_A:\n\t\t/*pHalData->ValidRxPath = 0x01;*/\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);\n\t\tphy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);\n\t\tphy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);\n\t\tphy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);\n\t\tphy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/\n\t\t/*/ CCA related PD_delay_th*/\n\t\tphy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);\n\t\tphy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);\n\t\tbreak;\n\n\tcase ANTENNA_B:\n\t\t/*pHalData->ValidRxPath = 0x02;*/\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);\n\t\tphy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);\n\t\tphy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);\n\t\tphy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);\n\t\tphy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/\n\t\t/*/ CCA related PD_delay_th*/\n\t\tphy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);\n\t\tphy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);\n\t\tbreak;\n\n\tcase ANTENNA_C:\n\t\t/*pHalData->ValidRxPath = 0x04;*/\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);\n\t\tphy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);\n\t\tphy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);\n\t\tphy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);\n\t\tphy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/\n\t\t/*/ CCA related PD_delay_th*/\n\t\tphy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);\n\t\tphy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);\n\t\tbreak;\n\n\tcase ANTENNA_D:\n\t\t/*pHalData->ValidRxPath = 0x08;*/\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);\n\t\tphy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);\n\t\tphy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);\n\t\tphy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);\n\t\tphy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/\n\t\t/*/ CCA related PD_delay_th*/\n\t\tphy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);\n\t\tphy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);\n\t\tbreak;\n\n\tcase ANTENNA_BC:\n\t\t/*pHalData->ValidRxPath = 0x06;*/\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);\n\t\tphy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);\n\t\tphy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);\n\t\tphy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);\n\t\tphy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/\n\t\t/*/ CCA related PD_delay_th*/\n\t\tphy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);\n\t\tphy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);\n\t\tbreak;\n\n\tcase ANTENNA_CD:\n\t\t/*pHalData->ValidRxPath = 0x0C;*/\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);\n\t\tphy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);\n\t\tphy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);\n\t\tphy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);\n\t\tphy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/\n\t\t/*/ CCA related PD_delay_th*/\n\t\tphy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);\n\t\tphy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);\n\t\tbreak;\n\n\tcase ANTENNA_BCD:\n\t\t/*pHalData->ValidRxPath = 0x0e;*/\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);\n\t\tphy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);\n\t\tphy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);\n\t\tphy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);\n\t\tphy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/\n\t\t/*/ CCA related PD_delay_th*/\n\t\tphy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);\n\t\tphy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);\n\t\tbreak;\n\n\tcase ANTENNA_ABCD:\n\t\t/*pHalData->ValidRxPath = 0x0f;*/\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);\n\t\tphy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);\n\t\tphy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);\n\t\tphy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);\n\t\tphy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/\n\t\t/*/ CCA related PD_delay_th*/\n\t\tphy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);\n\t\tphy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\tPHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);\n\n\tmpt_ToggleIG_8814A(pAdapter);\n}\n#endif /* CONFIG_RTL8814A */\n#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)  || defined(CONFIG_RTL8822C)\nvoid\nmpt_SetSingleTone_8814A(\n\t\tPADAPTER\tpAdapter,\n\t\tBOOLEAN\tbSingleTone,\n\t\tBOOLEAN\tbEnPMacTx)\n{\n\n\tPMPT_CONTEXT\tpMptCtx = &(pAdapter->mppriv.mpt_ctx);\n\tu8 StartPath = RF_PATH_A,  EndPath = RF_PATH_A, path;\n\tstatic u32\t\tregIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;\n\n\tif (bSingleTone) {\n\t\tregIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord);\t\t/*/ 0xC1C[31:21]*/\n\t\tregIG1 = phy_query_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord);\t\t/*/ 0xE1C[31:21]*/\n\t\tregIG2 = phy_query_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord);\t/*/ 0x181C[31:21]*/\n\t\tregIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord);\t/*/ 0x1A1C[31:21]*/\n\n\t\tswitch (pMptCtx->mpt_rf_path) {\n\t\tcase RF_PATH_A:\n\t\tcase RF_PATH_B:\n\t\tcase RF_PATH_C:\n\t\tcase RF_PATH_D:\n\t\t\tStartPath = pMptCtx->mpt_rf_path;\n\t\t\tEndPath = pMptCtx->mpt_rf_path;\n\t\t\tbreak;\n\t\tcase RF_PATH_AB:\n\t\t\tEndPath = RF_PATH_B;\n\t\t\tbreak;\n\t\tcase RF_PATH_BC:\n\t\t\tStartPath = RF_PATH_B;\n\t\t\tEndPath = RF_PATH_C;\n\t\t\tbreak;\n\t\tcase RF_PATH_ABC:\n\t\t\tEndPath = RF_PATH_C;\n\t\t\tbreak;\n\t\tcase RF_PATH_BCD:\n\t\t\tStartPath = RF_PATH_B;\n\t\t\tEndPath = RF_PATH_D;\n\t\t\tbreak;\n\t\tcase RF_PATH_ABCD:\n\t\t\tEndPath = RF_PATH_D;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (bEnPMacTx == FALSE) {\n\t\t\thal_mpt_SetContinuousTx(pAdapter, _TRUE);\n\t\t\tissue_nulldata(pAdapter, NULL, 1, 3, 500);\n\t\t}\n\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/\n\n\t\tfor (path = StartPath; path <= EndPath; path++) {\n\t\t\tphy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */\n\t\t\tphy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/\n\n\t\t\tphy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/\n\t\t}\n\n\t\tphy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/\n\t\tphy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/\n\t\tphy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/\n\t\tphy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/\n\t} else {\n\t\tswitch (pMptCtx->mpt_rf_path) {\n\t\tcase RF_PATH_A:\n\t\tcase RF_PATH_B:\n\t\tcase RF_PATH_C:\n\t\tcase RF_PATH_D:\n\t\t\tStartPath = pMptCtx->mpt_rf_path;\n\t\t\tEndPath = pMptCtx->mpt_rf_path;\n\t\t\tbreak;\n\t\tcase RF_PATH_AB:\n\t\t\tEndPath = RF_PATH_B;\n\t\t\tbreak;\n\t\tcase RF_PATH_BC:\n\t\t\tStartPath = RF_PATH_B;\n\t\t\tEndPath = RF_PATH_C;\n\t\t\tbreak;\n\t\tcase RF_PATH_ABC:\n\t\t\tEndPath = RF_PATH_C;\n\t\t\tbreak;\n\t\tcase RF_PATH_BCD:\n\t\t\tStartPath = RF_PATH_B;\n\t\t\tEndPath = RF_PATH_D;\n\t\t\tbreak;\n\t\tcase RF_PATH_ABCD:\n\t\t\tEndPath = RF_PATH_D;\n\t\t\tbreak;\n\t\t}\n\t\tfor (path = StartPath; path <= EndPath; path++)\n\t\t\tphy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */\n\n\t\tphy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/\n\n\t\tif (bEnPMacTx == FALSE)\n\t\t\thal_mpt_SetContinuousTx(pAdapter, _FALSE);\n\n\t\tphy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/\n\t\tphy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/\n\t\tphy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/\n\t\tphy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/\n\t}\n}\n\n#endif\n\n#if\tdefined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\nvoid mpt_SetRFPath_8812A(PADAPTER pAdapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\tPMPT_CONTEXT\tpMptCtx = &pAdapter->mppriv.mpt_ctx;\n\tstruct mp_priv *pmp = &pAdapter->mppriv;\n\tu8\t\tchannel = pmp->channel;\n\tu8\t\tbandwidth = pmp->bandwidth;\n\tu8\t\teLNA_2g = pHalData->ExternalLNA_2G;\n\tu32\t\tulAntennaTx, ulAntennaRx;\n\n\tulAntennaTx = pHalData->antenna_tx_path;\n\tulAntennaRx = pHalData->AntennaRxPath;\n\n\tswitch (ulAntennaTx) {\n\tcase ANTENNA_A:\n\t\tpMptCtx->mpt_rf_path = RF_PATH_A;\n\t\tphy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);\n\t\tif (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))\n\t\t\tphy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);\n\t\tbreak;\n\tcase ANTENNA_B:\n\t\tpMptCtx->mpt_rf_path = RF_PATH_B;\n\t\tphy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);\n\t\tif (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))\n\t\t\tphy_set_bb_reg(pAdapter,\tr_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);\n\t\tbreak;\n\tcase ANTENNA_AB:\n\t\tpMptCtx->mpt_rf_path = RF_PATH_AB;\n\t\tphy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);\n\t\tif (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))\n\t\t\tphy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);\n\t\tbreak;\n\tdefault:\n\t\tpMptCtx->mpt_rf_path = RF_PATH_AB;\n\t\tRTW_INFO(\"Unknown Tx antenna.\\n\");\n\t\tbreak;\n\t}\n\n\tswitch (ulAntennaRx) {\n\t\tu32 reg0xC50 = 0;\n\tcase ANTENNA_A:\n\t\tphy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/\n\t\tphy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);\n\n\t\t/*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/\n\t\treg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);\n\t\tphy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);\n\t\tphy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);\n\n\t\t/* set PWED_TH for BB Yn user guide R29 */\n\t\tif (IS_HARDWARE_TYPE_8812(pAdapter)) {\n\t\t\tif (channel <= 14) { /* 2.4G */\n\t\t\t\tif (bandwidth == CHANNEL_WIDTH_20\n\t\t\t\t    && eLNA_2g == 0) {\n\t\t\t\t\t/* 0x830[3:1]=3'b010 */\n\t\t\t\t\tphy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);\n\t\t\t\t} else\n\t\t\t\t\t/* 0x830[3:1]=3'b100 */\n\t\t\t\t\tphy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);\n\t\t\t} else\n\t\t\t\t/* 0x830[3:1]=3'b100 for 5G */\n\t\t\t\tphy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);\n\t\t}\n\t\tbreak;\n\tcase ANTENNA_B:\n\t\tphy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */\n\t\tphy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);\n\n\t\t/*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/\n\t\treg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);\n\t\tphy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);\n\t\tphy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);\n\n\t\t/* set PWED_TH for BB Yn user guide R29 */\n\t\tif (IS_HARDWARE_TYPE_8812(pAdapter)) {\n\t\t\tif (channel <= 14) {\n\t\t\t\tif (bandwidth == CHANNEL_WIDTH_20\n\t\t\t\t    && eLNA_2g == 0) {\n\t\t\t\t\t/* 0x830[3:1]=3'b010 */\n\t\t\t\t\tphy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);\n\t\t\t\t} else\n\t\t\t\t\t/* 0x830[3:1]=3'b100 */\n\t\t\t\t\tphy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);\n\t\t\t} else\n\t\t\t\t/* 0x830[3:1]=3'b100 for 5G */\n\t\t\t\tphy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);\n\t\t}\n\t\tbreak;\n\tcase ANTENNA_AB:\n\t\tphy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/\n\t\tphy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);\n\t\t/* set PWED_TH for BB Yn user guide R29 */\n\t\tphy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(\"Unknown Rx antenna.\\n\");\n\t\tbreak;\n\t}\n\n\tif (pHalData->rfe_type == 5 || pHalData->rfe_type == 1) {\n\t\tif (ulAntennaTx == ANTENNA_A || ulAntennaTx == ANTENNA_AB) {\n\t\t\t/* WiFi */\n\t\t\tphy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x2);\n\t\t\tphy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);\n\t\t} else {\n\t\t\t/* BT */\n\t\t\tphy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x1);\n\t\t\tphy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);\n\t\t}\n\t}\n}\n#endif\n\n#ifdef CONFIG_RTL8723B\nvoid mpt_SetRFPath_8723B(PADAPTER pAdapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\tu32\t\tulAntennaTx, ulAntennaRx;\n\tPMPT_CONTEXT\tpMptCtx = &(pAdapter->mppriv.mpt_ctx);\n\tstruct dm_struct\t*pDM_Odm = &pHalData->odmpriv;\n\tstruct dm_rf_calibration_struct\t*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);\n\n\tulAntennaTx = pHalData->antenna_tx_path;\n\tulAntennaRx = pHalData->AntennaRxPath;\n\n\tif (pHalData->rf_chip >= RF_CHIP_MAX) {\n\t\tRTW_INFO(\"This RF chip ID is not supported\\n\");\n\t\treturn;\n\t}\n\n\tswitch (pAdapter->mppriv.antenna_tx) {\n\t\tu8 p = 0, i = 0;\n\tcase ANTENNA_A: { /*/ Actually path S1  (Wi-Fi)*/\n\t\tpMptCtx->mpt_rf_path = RF_PATH_A;\n\t\tphy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);\n\t\tphy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/\n\n\t\tfor (i = 0; i < 3; ++i) {\n\t\t\tu32 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];\n\t\t\tu32 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1];\n\n\t\t\tif (offset != 0) {\n\t\t\t\tphy_set_bb_reg(pAdapter, offset, bMaskDWord, data);\n\t\t\t\tRTW_INFO(\"Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\\n\", offset, data);\n\t\t\t}\n\t\t}\n\t\tfor (i = 0; i < 2; ++i) {\n\t\t\tu32 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];\n\t\t\tu32 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1];\n\n\t\t\tif (offset != 0) {\n\t\t\t\tphy_set_bb_reg(pAdapter, offset, bMaskDWord, data);\n\t\t\t\tRTW_INFO(\"Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\\n\", offset, data);\n\t\t\t}\n\t\t}\n\t}\n\tbreak;\n\tcase ANTENNA_B: { /*/ Actually path S0 (BT)*/\n\t\tu32 offset;\n\t\tu32 data;\n\n\t\tpMptCtx->mpt_rf_path = RF_PATH_B;\n\t\tphy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);\n\t\tphy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/\n\n\t\tfor (i = 0; i < 3; ++i) {\n\t\t\t/*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC  to S1 instead of S0.*/\n\t\t\toffset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];\n\t\t\tdata = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][1];\n\t\t\tif (pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][0] != 0) {\n\t\t\t\tphy_set_bb_reg(pAdapter, offset, bMaskDWord, data);\n\t\t\t\tRTW_INFO(\"Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\\n\", offset, data);\n\t\t\t}\n\t\t}\n\t\t/*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/\n\t\tfor (i = 0; i < 2; ++i) {\n\t\t\toffset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];\n\t\t\tdata = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][1];\n\t\t\tif (pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][0] != 0) {\n\t\t\t\tphy_set_bb_reg(pAdapter, offset, bMaskDWord, data);\n\t\t\t\tRTW_INFO(\"Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\\n\", offset, data);\n\t\t\t}\n\t\t}\n\t}\n\tbreak;\n\tdefault:\n\t\tpMptCtx->mpt_rf_path = RF_PATH_AB;\n\t\tbreak;\n\t}\n}\n#endif\n\n#ifdef CONFIG_RTL8703B\nvoid mpt_SetRFPath_8703B(PADAPTER pAdapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\tu32\t\t\t\t\tulAntennaTx, ulAntennaRx;\n\tPMPT_CONTEXT\t\tpMptCtx = &(pAdapter->mppriv.mpt_ctx);\n\tstruct dm_struct\t\t*pDM_Odm = &pHalData->odmpriv;\n\tstruct dm_rf_calibration_struct\t\t\t*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);\n\n\tulAntennaTx = pHalData->antenna_tx_path;\n\tulAntennaRx = pHalData->AntennaRxPath;\n\n\tif (pHalData->rf_chip >= RF_CHIP_MAX) {\n\t\tRTW_INFO(\"This RF chip ID is not supported\\n\");\n\t\treturn;\n\t}\n\n\tswitch (pAdapter->mppriv.antenna_tx) {\n\t\tu8 p = 0, i = 0;\n\n\tcase ANTENNA_A: { /* Actually path S1  (Wi-Fi) */\n\t\tpMptCtx->mpt_rf_path = RF_PATH_A;\n\t\tphy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);\n\t\tphy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/\n\n\t\tfor (i = 0; i < 3; ++i) {\n\t\t\tu32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];\n\t\t\tu32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];\n\n\t\t\tif (offset != 0) {\n\t\t\t\tphy_set_bb_reg(pAdapter, offset, bMaskDWord, data);\n\t\t\t\tRTW_INFO(\"Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\\n\", offset, data);\n\t\t\t}\n\n\t\t}\n\t\tfor (i = 0; i < 2; ++i) {\n\t\t\tu32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];\n\t\t\tu32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];\n\n\t\t\tif (offset != 0) {\n\t\t\t\tphy_set_bb_reg(pAdapter, offset, bMaskDWord, data);\n\t\t\t\tRTW_INFO(\"Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\\n\", offset, data);\n\t\t\t}\n\t\t}\n\t}\n\tbreak;\n\tcase ANTENNA_B: { /* Actually path S0 (BT)*/\n\t\tpMptCtx->mpt_rf_path = RF_PATH_B;\n\t\tphy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);\n\t\tphy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */\n\n\t\tfor (i = 0; i < 3; ++i) {\n\t\t\tu32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];\n\t\t\tu32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];\n\n\t\t\tif (pRFCalibrateInfo->tx_iqc_8703b[i][0] != 0) {\n\t\t\t\tphy_set_bb_reg(pAdapter, offset, bMaskDWord, data);\n\t\t\t\tRTW_INFO(\"Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\\n\", offset, data);\n\t\t\t}\n\t\t}\n\t\tfor (i = 0; i < 2; ++i) {\n\t\t\tu32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];\n\t\t\tu32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];\n\n\t\t\tif (pRFCalibrateInfo->rx_iqc_8703b[i][0] != 0) {\n\t\t\t\tphy_set_bb_reg(pAdapter, offset, bMaskDWord, data);\n\t\t\t\tRTW_INFO(\"Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\\n\", offset, data);\n\t\t\t}\n\t\t}\n\t}\n\tbreak;\n\tdefault:\n\t\tpMptCtx->mpt_rf_path = RF_PATH_AB;\n\t\tbreak;\n\t}\n\n}\n#endif\n\n#ifdef CONFIG_RTL8723D\nvoid mpt_SetRFPath_8723D(PADAPTER pAdapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\tu8\tp = 0, i = 0;\n\tu32\tulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;\n\tPMPT_CONTEXT\tpMptCtx = &(pAdapter->mppriv.mpt_ctx);\n\tstruct dm_struct\t*pDM_Odm = &pHalData->odmpriv;\n\tstruct dm_rf_calibration_struct\t*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);\n\n\tulAntennaTx = pHalData->antenna_tx_path;\n\tulAntennaRx = pHalData->AntennaRxPath;\n\n\tif (pHalData->rf_chip >= RF_CHIP_MAX) {\n\t\tRTW_INFO(\"This RF chip ID is not supported\\n\");\n\t\treturn;\n\t}\n\n\tswitch (pAdapter->mppriv.antenna_tx) {\n\t/* Actually path S1  (Wi-Fi) */\n\tcase ANTENNA_A: {\n\t\tpMptCtx->mpt_rf_path = RF_PATH_A;\n\t\tphy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0);\n\t}\n\tbreak;\n\t/* Actually path S0 (BT) */\n\tcase ANTENNA_B: {\n\t\tpMptCtx->mpt_rf_path = RF_PATH_B;\n\t\tphy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA);\n\n\t}\n\tbreak;\n\tdefault:\n\t\tpMptCtx->mpt_rf_path = RF_PATH_AB;\n\t\tbreak;\n\t}\n}\n#endif\n\nvoid mpt_SetRFPath_819X(PADAPTER\tpAdapter)\n{\n\tHAL_DATA_TYPE\t\t\t*pHalData\t= GET_HAL_DATA(pAdapter);\n\tPMPT_CONTEXT\t\tpMptCtx = &(pAdapter->mppriv.mpt_ctx);\n\tu32\t\t\tulAntennaTx, ulAntennaRx;\n\tR_ANTENNA_SELECT_OFDM\t*p_ofdm_tx;\t/* OFDM Tx register */\n\tR_ANTENNA_SELECT_CCK\t*p_cck_txrx;\n\tu8\t\tr_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;\n\tu8\t\tchgTx = 0, chgRx = 0;\n\tu32\t\tr_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;\n\n\tulAntennaTx = pHalData->antenna_tx_path;\n\tulAntennaRx = pHalData->AntennaRxPath;\n\n\tp_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;\n\tp_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;\n\n\tp_ofdm_tx->r_ant_ht1\t\t\t= 0x1;\n\tp_ofdm_tx->r_ant_ht2\t\t\t= 0x2;/*Second TX RF path is A*/\n\tp_ofdm_tx->r_ant_non_ht\t\t\t= 0x3;/*/ 0x1+0x2=0x3 */\n\n\tswitch (ulAntennaTx) {\n\tcase ANTENNA_A:\n\t\tp_ofdm_tx->r_tx_antenna\t\t= 0x1;\n\t\tr_ofdm_tx_en_val\t\t= 0x1;\n\t\tp_ofdm_tx->r_ant_l\t\t= 0x1;\n\t\tp_ofdm_tx->r_ant_ht_s1\t\t= 0x1;\n\t\tp_ofdm_tx->r_ant_non_ht_s1\t= 0x1;\n\t\tp_cck_txrx->r_ccktx_enable\t= 0x8;\n\t\tchgTx = 1;\n\t\t/*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/\n\t\t/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/\n\t\t{\n\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);\n\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);\n\t\t\tr_ofdm_tx_en_val\t\t\t= 0x3;\n\t\t\t/*/ Power save*/\n\t\t\t/*/cosa r_ant_select_ofdm_val = 0x11111111;*/\n\t\t\t/*/ We need to close RFB by SW control*/\n\t\t\tif (pHalData->rf_type == RF_2T2R) {\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);\n\t\t\t}\n\t\t}\n\t\tpMptCtx->mpt_rf_path = RF_PATH_A;\n\t\tbreak;\n\tcase ANTENNA_B:\n\t\tp_ofdm_tx->r_tx_antenna\t\t= 0x2;\n\t\tr_ofdm_tx_en_val\t\t= 0x2;\n\t\tp_ofdm_tx->r_ant_l\t\t= 0x2;\n\t\tp_ofdm_tx->r_ant_ht_s1\t\t= 0x2;\n\t\tp_ofdm_tx->r_ant_non_ht_s1\t= 0x2;\n\t\tp_cck_txrx->r_ccktx_enable\t= 0x4;\n\t\tchgTx = 1;\n\t\t/*/ From SD3 Willis suggestion !!! Set RF A as standby*/\n\t\t/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/\n\t\t{\n\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);\n\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);\n\n\t\t\t/*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/\n\t\t\t/*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/\n\t\t\tif (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);\n\t\t\t\t/*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);\n\t\t\t}\n\t\t}\n\t\tpMptCtx->mpt_rf_path = RF_PATH_B;\n\t\tbreak;\n\tcase ANTENNA_AB:/*/ For 8192S*/\n\t\tp_ofdm_tx->r_tx_antenna\t\t= 0x3;\n\t\tr_ofdm_tx_en_val\t\t= 0x3;\n\t\tp_ofdm_tx->r_ant_l\t\t= 0x3;\n\t\tp_ofdm_tx->r_ant_ht_s1\t\t= 0x3;\n\t\tp_ofdm_tx->r_ant_non_ht_s1\t= 0x3;\n\t\tp_cck_txrx->r_ccktx_enable\t= 0xC;\n\t\tchgTx = 1;\n\t\t/*/ From SD3Willis suggestion !!! Set RF B as standby*/\n\t\t/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/\n\t\t{\n\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);\n\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);\n\t\t\t/* Disable Power save*/\n\t\t\t/*cosa r_ant_select_ofdm_val = 0x3321333;*/\n\t\t\t/* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/\n\t\t\tif (pHalData->rf_type == RF_2T2R) {\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);\n\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);\n\t\t\t\t/*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);\n\t\t\t}\n\t\t}\n\t\tpMptCtx->mpt_rf_path = RF_PATH_AB;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n#if 0\n\t/*  r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */\n\t/*  r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */\n\t/* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D\t */\n#endif\n\tswitch (ulAntennaRx) {\n\tcase ANTENNA_A:\n\t\tr_rx_antenna_ofdm\t\t= 0x1;\t/* A*/\n\t\tp_cck_txrx->r_cckrx_enable\t= 0x0;\t/* default: A*/\n\t\tp_cck_txrx->r_cckrx_enable_2\t= 0x0;\t/* option: A*/\n\t\tchgRx = 1;\n\t\tbreak;\n\tcase ANTENNA_B:\n\t\tr_rx_antenna_ofdm\t\t\t= 0x2;\t/*/ B*/\n\t\tp_cck_txrx->r_cckrx_enable\t= 0x1;\t/*/ default: B*/\n\t\tp_cck_txrx->r_cckrx_enable_2\t= 0x1;\t/*/ option: B*/\n\t\tchgRx = 1;\n\t\tbreak;\n\tcase ANTENNA_AB:/*/ For 8192S and 8192E/U...*/\n\t\tr_rx_antenna_ofdm\t\t= 0x3;/*/ AB*/\n\t\tp_cck_txrx->r_cckrx_enable\t= 0x0;/*/ default:A*/\n\t\tp_cck_txrx->r_cckrx_enable_2\t= 0x1;/*/ option:B*/\n\t\tchgRx = 1;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\n\tif (chgTx && chgRx) {\n\t\tswitch (pHalData->rf_chip) {\n\t\tcase RF_8225:\n\t\tcase RF_8256:\n\t\tcase RF_6052:\n\t\t\t/*/r_ant_sel_cck_val = r_ant_select_cck_val;*/\n\t\t\tphy_set_bb_reg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val);\t\t/*/OFDM Tx*/\n\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val);\t\t/*/OFDM Tx*/\n\t\t\tphy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);\t/*/OFDM Rx*/\n\t\t\tphy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);\t/*/OFDM Rx*/\n\t\t\tif (IS_HARDWARE_TYPE_8192E(pAdapter)) {\n\t\t\t\tphy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm);\t/*/OFDM Rx*/\n\t\t\t\tphy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm);\t/*/OFDM Rx*/\n\t\t\t}\n\t\t\tphy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tRTW_INFO(\"Unsupported RFChipID for switching antenna.\\n\");\n\t\t\tbreak;\n\t\t}\n\t}\n}\t/* MPT_ProSetRFPath */\n\n#ifdef CONFIG_RTL8192F\n\nvoid mpt_set_rfpath_8192f(PADAPTER\tpAdapter)\n{\n\tHAL_DATA_TYPE\t\t\t*pHalData\t= GET_HAL_DATA(pAdapter);\n\tPMPT_CONTEXT\t\tpMptCtx = &(pAdapter->mppriv.mpt_ctx);\n\n\tu16\t\tForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);\n\tu8\t\t\t\tNssforRate, odmNssforRate;\n\tu32\t\t\t\tulAntennaTx, ulAntennaRx;\n\tu8\t\t\t\tRxAntToPhyDm;\n\tu8\t\t\t\tTxAntToPhyDm;\n\n\tulAntennaTx = pHalData->antenna_tx_path;\n\tulAntennaRx = pHalData->AntennaRxPath;\n\tNssforRate = MgntQuery_NssTxRate(ForcedDataRate);\n\n\tif (pHalData->rf_chip >= RF_TYPE_MAX)\n\t\tRTW_INFO(\"This RF chip ID is not supported\\n\");\n\n\tswitch (ulAntennaTx) {\n\tcase ANTENNA_A:\n\t\t\tpMptCtx->mpt_rf_path = RF_PATH_A;\n\t\t\tTxAntToPhyDm = BB_PATH_A;\n\t\t\tbreak;\n\tcase ANTENNA_B:\n\t\t\tpMptCtx->mpt_rf_path = RF_PATH_B;\n\t\t\tTxAntToPhyDm = BB_PATH_B;\n\t\t\tbreak;\n\tcase ANTENNA_AB:\n\t\t\tpMptCtx->mpt_rf_path = RF_PATH_AB;\n\t\t\tTxAntToPhyDm = (BB_PATH_A|BB_PATH_B);\n\t\t\tbreak;\n\tdefault:\n\t\t\tpMptCtx->mpt_rf_path = RF_PATH_AB;\n\t\t\tTxAntToPhyDm = (BB_PATH_A|BB_PATH_B);\n\t\t\tbreak;\n\t}\n\n\tswitch (ulAntennaRx) {\n\tcase ANTENNA_A:\n\t\t\tRxAntToPhyDm = BB_PATH_A;\n\t\t\tbreak;\n\tcase ANTENNA_B:\n\t\t\tRxAntToPhyDm = BB_PATH_B;\n\t\t\tbreak;\n\tcase ANTENNA_AB:\n\t\t\tRxAntToPhyDm = (BB_PATH_A|BB_PATH_B);\n\t\t\tbreak;\n\tdefault:\n\t\t\tRxAntToPhyDm = (BB_PATH_A|BB_PATH_B);\n\t\t\tbreak;\n\t}\n\n\tconfig_phydm_trx_mode_8192f(GET_PDM_ODM(pAdapter), TxAntToPhyDm, RxAntToPhyDm, FALSE);\n\n}\n\n#endif\n\nvoid hal_mpt_SetAntenna(PADAPTER\tpAdapter)\n\n{\n\tRTW_INFO(\"Do %s\\n\", __func__);\n#ifdef CONFIG_RTL8822C\n\tif (IS_HARDWARE_TYPE_8822C(pAdapter)) {\n\t\trtl8822c_mp_config_rfpath(pAdapter);\n\t\treturn;\n\t}\n#endif\n#ifdef CONFIG_RTL8814A\n\tif (IS_HARDWARE_TYPE_8814A(pAdapter)) {\n\t\tmpt_SetRFPath_8814A(pAdapter);\n\t\treturn;\n\t}\n#endif\n#ifdef CONFIG_RTL8822B\n\tif (IS_HARDWARE_TYPE_8822B(pAdapter)) {\n\t\trtl8822b_mp_config_rfpath(pAdapter);\n\t\treturn;\n\t}\n#endif\n#ifdef CONFIG_RTL8821C\n\tif (IS_HARDWARE_TYPE_8821C(pAdapter)) {\n\t\trtl8821c_mp_config_rfpath(pAdapter);\n\t\treturn;\n\t}\n#endif\n#if\tdefined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\n\tif (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {\n\t\tmpt_SetRFPath_8812A(pAdapter);\n\t\treturn;\n\t}\n#endif\n#ifdef CONFIG_RTL8723B\n\tif (IS_HARDWARE_TYPE_8723B(pAdapter)) {\n\t\tmpt_SetRFPath_8723B(pAdapter);\n\t\treturn;\n\t}\n#endif\n\n#ifdef CONFIG_RTL8703B\n\tif (IS_HARDWARE_TYPE_8703B(pAdapter)) {\n\t\tmpt_SetRFPath_8703B(pAdapter);\n\t\treturn;\n\t}\n#endif\n\n#ifdef CONFIG_RTL8723D\n\tif (IS_HARDWARE_TYPE_8723D(pAdapter)) {\n\t\tmpt_SetRFPath_8723D(pAdapter);\n\t\treturn;\n\t}\n#endif\n\n#ifdef CONFIG_RTL8192F\n\t\tif (IS_HARDWARE_TYPE_8192F(pAdapter)) {\n\t\t\tmpt_set_rfpath_8192f(pAdapter);\n\t\t\treturn;\n\t\t}\n#endif\n\n\t/*\telse if (IS_HARDWARE_TYPE_8821B(pAdapter))\n\t\t\tmpt_SetRFPath_8821B(pAdapter);\n\t\tPrepare for 8822B\n\t\telse if (IS_HARDWARE_TYPE_8822B(Context))\n\t\t\tmpt_SetRFPath_8822B(Context);\n\t*/\n\tmpt_SetRFPath_819X(pAdapter);\n\tRTW_INFO(\"mpt_SetRFPath_819X Do %s\\n\", __func__);\n}\n\ns32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\n\n\tif (!netif_running(pAdapter->pnetdev)) {\n\t\treturn _FAIL;\n\t}\n\n\n\tif (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {\n\t\treturn _FAIL;\n\t}\n\n\n\ttarget_ther &= 0xff;\n\tif (target_ther < 0x07)\n\t\ttarget_ther = 0x07;\n\telse if (target_ther > 0x1d)\n\t\ttarget_ther = 0x1d;\n\n\tpHalData->eeprom_thermal_meter = target_ther;\n\n\treturn _SUCCESS;\n}\n\n\nvoid hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)\n{\n\tif (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x0);\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);\n\t} else\n\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);\n\n}\n\n\nu8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path)\n\n{\n\tstruct dm_struct *p_dm_odm = adapter_to_phydm(pAdapter);\n\n\tu32 ThermalValue = 0;\n\ts32 thermal_value_temp = 0;\n\ts8 thermal_offset = 0;\n\tu32 thermal_reg_mask = 0;\n\n\tif (IS_8822C_SERIES(GET_HAL_DATA(pAdapter)->version_id))\n\t\t\tthermal_reg_mask = 0x007e; \t/*0x42: RF Reg[6:1], 35332(themal K  & bias k & power trim) & 35325(tssi )*/\n\telse\n\t\t\tthermal_reg_mask = 0xfc00;\t/*0x42: RF Reg[15:10]*/\n\n\tThermalValue = (u8)phy_query_rf_reg(pAdapter, rf_path, 0x42, thermal_reg_mask);\n\n\tthermal_offset = phydm_get_thermal_offset(p_dm_odm);\n\n\tthermal_value_temp = ThermalValue + thermal_offset;\n\n\tif (thermal_value_temp > 63)\n\t\tThermalValue = 63;\n\telse if (thermal_value_temp < 0)\n\t\tThermalValue = 0;\n\telse\n\t\tThermalValue = thermal_value_temp;\n\n\treturn (u8)ThermalValue;\n}\n\n\nvoid hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value)\n{\n#if 0\n\tfw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);\n\trtw_msleep_os(1000);\n\tfw_cmd_data(pAdapter, value, 1);\n\t*value &= 0xFF;\n#else\n\thal_mpt_TriggerRFThermalMeter(pAdapter);\n\trtw_msleep_os(1000);\n\t*value = hal_mpt_ReadRFThermalMeter(pAdapter, rfpath);\n#endif\n\n}\n\n\nvoid hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\n\n\tpAdapter->mppriv.mpt_ctx.bSingleCarrier = bStart;\n\n\tif (bStart) {/*/ Start Single Carrier.*/\n\t\t/*/ Start Single Carrier.*/\n\t\t/*/ 1. if OFDM block on?*/\n\t\tif (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))\n\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/\n\n\t\t/*/ 2. set CCK test mode off, set to CCK normal mode*/\n\t\tphy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);\n\n\t\t/*/ 3. turn on scramble setting*/\n\t\tphy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);\n\n\t\t/*/ 4. Turn On Continue Tx and turn off the other test modes.*/\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)\n\t\tif (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))\n\t\t\tphy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);\n\t\telse\n#endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */\n\t\t\tphy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);\n\n\t} else {\n\t\t/*/ Stop Single Carrier.*/\n\t\t/*/ Stop Single Carrier.*/\n\t\t/*/ Turn off all test modes.*/\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)\n\t\tif (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))\n\t\t\tphy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);\n\t\telse\n#endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */\n\t\t\tphy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);\n\n\t\trtw_msleep_os(10);\n\t\t/*/BB Reset*/\n\t\tphy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\n\t\tphy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\n\t}\n}\n\n\nvoid hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\tPMPT_CONTEXT\t\tpMptCtx = &(pAdapter->mppriv.mpt_ctx);\n\tstruct dm_struct\t\t*pDM_Odm = &pHalData->odmpriv;\n\tu32\t\t\tulAntennaTx = pHalData->antenna_tx_path;\n\tstatic u32\t\tregRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;\n\tu8 rfPath;\n\n\tif (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {\n#ifdef\tPHYDM_MP_SUPPORT\n\t\tphydm_mp_set_single_tone(pDM_Odm, bStart, pMptCtx->mpt_rf_path);\n#endif\n\t\treturn;\n\t}\n\n\tswitch (ulAntennaTx) {\n\tcase ANTENNA_B:\n\t\trfPath = RF_PATH_B;\n\t\tbreak;\n\tcase ANTENNA_C:\n\t\trfPath = RF_PATH_C;\n\t\tbreak;\n\tcase ANTENNA_D:\n\t\trfPath = RF_PATH_D;\n\t\tbreak;\n\tcase ANTENNA_A:\n\tdefault:\n\t\trfPath = RF_PATH_A;\n\t\tbreak;\n\t}\n\n\tpAdapter->mppriv.mpt_ctx.is_single_tone = bStart;\n\tif (bStart) {\n\t\t/*/ Start Single Tone.*/\n\t\t/*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/\n\t\tif (IS_HARDWARE_TYPE_8188E(pAdapter)) {\n\t\t\tregRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask);\n\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/\n\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);\n\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);\n\t\t} else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/\n\t\t\t/*/Set MAC REG 88C: Prevent SingleTone Fail*/\n\t\t\tphy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF);\n\t\t\tphy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/\n\t\t\tphy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/\n\t\t}\telse if (IS_HARDWARE_TYPE_8192F(pAdapter)) { /* USB need to do RF LO disable first, PCIE isn't required to follow this order.*/\n #ifdef CONFIG_RTL8192F\n\t\t\tphy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x1);\n\t\t\tphy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x1);\n\t\t\tphy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x1);\n\t\t\tphy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x1);\n\t\t\tphy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x1);\n\t\t\tphy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x1);\n\t\t\tphy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0xF);\n\t\t\tphy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x1); /* RF LO disabled*/\n\t\t\tphy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /* Tx mode*/\n#endif\n\t\t} else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {\n\t\t\tif (pMptCtx->mpt_rf_path == RF_PATH_A) {\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/\n\t\t\t} else {\n\t\t\t\t/*/ S0/S1 both use PATH A to configure*/\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/\n\t\t\t}\n\t\t} else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {\n\t\t\tif (pMptCtx->mpt_rf_path == RF_PATH_A) {\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */\n\t\t\t}\n\t\t} else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {\n\t\t\t/*Set BB REG 88C: Prevent SingleTone Fail*/\n\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);\n\t\t\tphy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1);\n\t\t\tphy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2);\n\n\t\t} else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {\n\t\t\tif (pMptCtx->mpt_rf_path == RF_PATH_A) {\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x1);\n\t\t\t} else {/* S0/S1 both use PATH A to configure */\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x1);\n\t\t\t}\n\t\t} else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)\n\t\t\tu8 p = RF_PATH_A;\n\n\t\t\tregRF = phy_query_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);\n\t\t\tregBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);\n\t\t\tregBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);\n\t\t\tregBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);\n\t\t\tregBB3 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);\n\n\t\t\tphy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/\n\n\t\t\tif (pMptCtx->mpt_rf_path == RF_PATH_AB) {\n\t\t\t\tfor (p = RF_PATH_A; p <= RF_PATH_B; ++p) {\n\t\t\t\t\tphy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */\n\t\t\t\t\tphy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/\n\t\t\t\t\tphy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tphy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */\n\t\t\t\tphy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/\n#ifdef CONFIG_RTL8821C\n\t\t\t\tif (IS_HARDWARE_TYPE_8821C(pAdapter) && pDM_Odm->current_rf_set_8821c == SWITCH_TO_BTG)\n\t\t\t\t\tphy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x75, BIT16, 0x1); /* RF LO (for BTG) enabled */\n\t\t\t\telse\n#endif\n\t\t\t\t\tphy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/\n\t\t\t}\n\t\t\tif (IS_HARDWARE_TYPE_8822B(pAdapter)) {\n\t\t\t\t\tphy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777);  /* 0xCB0=0x77777777*/\n\t\t\t\t\tphy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777);  /* 0xEB0=0x77777777*/\n\t\t\t\t\tphy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777);  /* 0xCB4[15:0] = 0x7777*/\n\t\t\t\t\tphy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777);  /* 0xEB4[15:0] = 0x7777*/\n\t\t\t\t\tphy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xFFF, 0xb); /* 0xCBC[23:16] = 0x12*/\n\t\t\t\t\tphy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xFFF, 0x830); /* 0xEBC[23:16] = 0x12*/\n\t\t\t} else if (IS_HARDWARE_TYPE_8821C(pAdapter)) {\n\t\t\t\tphy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xF0F0, 0x707);  /* 0xCB0[[15:12, 7:4] = 0x707*/\n\n\t\t\t\tif (pHalData->external_pa_5g)\n\t\t\t\t{\n\t\t\t\t\tphy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/\n\t\t\t\t}\n\t\t\t\telse if (pHalData->ExternalPA_2G)\n\t\t\t\t{\n\t\t\t\t\tphy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tphy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  /*/ 0xCB0[[23:16, 7:4] = 0x77007*/\n\t\t\t\tphy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  /*/ 0xCB0[[23:16, 7:4] = 0x77007*/\n\n\t\t\t\tif (pHalData->external_pa_5g) {\n\t\t\t\t\tphy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/\n\t\t\t\t\tphy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/\n\t\t\t\t} else if (pHalData->ExternalPA_2G) {\n\t\t\t\t\tphy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/\n\t\t\t\t\tphy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/\n\t\t\t\t}\n\t\t\t}\n#endif\n\t\t}\n#if defined(CONFIG_RTL8814A)\n\t\t\t\telse if (IS_HARDWARE_TYPE_8814A(pAdapter))\n\t\t\t\t\t\tmpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);\n#endif\n\t\telse\t/*/ Turn On SingleTone and turn off the other test modes.*/\n\t\t\tphy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);\n\n\t\twrite_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\n\t\twrite_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\n\n\t} else {/*/ Stop Single Ton e.*/\n\n\t\tif (IS_HARDWARE_TYPE_8188E(pAdapter)) {\n\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF);\n\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);\n\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);\n\t\t} else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {\n\t\t\tphy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/\n\t\t\tphy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */\n\t\t\t/*/ RESTORE MAC REG 88C: Enable RF Functions*/\n\t\t\tphy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0);\n\t\t} else if (IS_HARDWARE_TYPE_8192F(pAdapter)){\n#ifdef CONFIG_RTL8192F\n\t\t\tphy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x0);\n\t\t\tphy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x0);\n\t\t\tphy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x0);\n\t\t\tphy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x0);\n\t\t\tphy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x0);\n\t\t\tphy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x0);\n\t\t\tphy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0x0);\n\t\t\tphy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x0); /* RF LO disabled*/\n\t\t\tphy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /* Rx mode*/\n#endif\n\t\t} else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {\n\t\t\tif (pMptCtx->mpt_rf_path == RF_PATH_A) {\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/\n\t\t\t} else {\n\t\t\t\t/*/ S0/S1 both use PATH A to configure*/\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/\n\t\t\t}\n\t\t} else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {\n\t\t\tif (pMptCtx->mpt_rf_path == RF_PATH_A) {\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */\n\t\t\t}\n\t\t} else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {\n\t\t\tphy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/\n\t\t\tphy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/\n\t\t\t/*Set BB REG 88C: Prevent SingleTone Fail*/\n\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);\n\t\t} else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {\n\t\t\tif (pMptCtx->mpt_rf_path == RF_PATH_A) {\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x0);\n\t\t\t} else {\t/* S0/S1 both use PATH A to configure */\n\t\t\t\tphy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);\n\t\t\t\tphy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x0);\n\t\t\t}\n\t\t} else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)\n\t\t\tu8 p = RF_PATH_A;\n\n\t\t\tphy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/\n\n\t\t\tif (pMptCtx->mpt_rf_path == RF_PATH_AB) {\n\t\t\t\tfor (p = RF_PATH_A; p <= RF_PATH_B; ++p) {\n\t\t\t\t\tphy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);\n\t\t\t\t\tphy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tp = pMptCtx->mpt_rf_path;\n\t\t\t\tphy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);\n\n\t\t\t\tif (IS_HARDWARE_TYPE_8821C(pAdapter))\n\t\t\t\t\tphy_set_rf_reg(pAdapter, p, 0x75, BIT16, 0x0); /* RF LO (for BTG) disabled */\n\n\t\t\t\tphy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/\n\t\t\t}\n\n\t\t\tphy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);\n\t\t\tphy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);\n\t\t\tphy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);\n\t\t\tphy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);\n\n\t\t\tif (IS_HARDWARE_TYPE_8822B(pAdapter)) {\n\t\t\t\tRTW_INFO(\"Restore RFE control Pin cbc\\n\");\n\t\t\t\tphy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xfff, 0x0);\n\t\t\t\tphy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xfff, 0x0);\n\t\t\t}\n#endif\n\t\t}\n#if defined(CONFIG_RTL8814A)\n\t\telse if (IS_HARDWARE_TYPE_8814A(pAdapter))\n\t\t\tmpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);\n\n\t\telse/*/ Turn off all test modes.*/\n\t\t\tphy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);\n#endif\n\t\twrite_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\n\t\twrite_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\n\n\t}\n}\n\nvoid hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(pAdapter);\n\tstruct dm_struct\t\t*pdm_odm = &pHalData->odmpriv;\n\tu8 Rate;\n\n\tpAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart;\n\n\tif (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {\n#ifdef PHYDM_MP_SUPPORT\n\t\tphydm_mp_set_carrier_supp(pdm_odm, bStart, pAdapter->mppriv.rateidx);\n#endif\n\t\treturn;\n\t}\n\n\tRate = HwRateToMPTRate(pAdapter->mppriv.rateidx);\n\tif (bStart) {/* Start Carrier Suppression.*/\n\t\tif (Rate <= MPT_RATE_11M) {\n\t\t\t/*/ 1. if CCK block on?*/\n\t\t\tif (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))\n\t\t\t\twrite_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/\n\n\t\t\t/*/Turn Off All Test Mode*/\n\t\t\tif (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))\n\t\t\t\tphy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/\n\t\t\telse\n\t\t\t\tphy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);\n\n\t\t\twrite_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);    /*/transmit mode*/\n\t\t\twrite_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0);  /*/turn off scramble setting*/\n\n\t\t\t/*/Set CCK Tx Test Rate*/\n\t\t\twrite_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);    /*/Set FTxRate to 1Mbps*/\n\t\t}\n\n\t\t/*Set for dynamic set Power index*/\n\t\twrite_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\n\t\twrite_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\n\n\t} else {/* Stop Carrier Suppression.*/\n\n\t\tif (Rate <= MPT_RATE_11M) {\n\t\t\twrite_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);    /*normal mode*/\n\t\t\twrite_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1);  /*turn on scramble setting*/\n\n\t\t\t/*BB Reset*/\n\t\t\twrite_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\n\t\t\twrite_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\n\t\t}\n\t\t/*Stop for dynamic set Power index*/\n\t\twrite_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\n\t\twrite_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\n\t}\n\tRTW_INFO(\"\\n MPT_ProSetCarrierSupp() is finished.\\n\");\n}\n\nu32 hal_mpt_query_phytxok(PADAPTER\tpAdapter)\n{\n\tPMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);\n\tRT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;\n\tHAL_DATA_TYPE\t\t\t*pHalData\t= GET_HAL_DATA(pAdapter);\n\tu16 count = 0;\n\n#ifdef PHYDM_MP_SUPPORT\n\tstruct dm_struct *dm = (struct dm_struct *)&pHalData->odmpriv;\n\tstruct phydm_mp *mp = &dm->dm_mp_table;\n\n\tif (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {\n\t\tphydm_mp_get_tx_ok(&pHalData->odmpriv, pAdapter->mppriv.rateidx);\n\t\tcount = mp->tx_phy_ok_cnt;\n\n\t} else\n#endif\n\t{\n\n\tif (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))\n\t\tcount = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/\n\telse\n\t\tcount = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/\n\t}\n\n\tif (count > 50000) {\n\t\trtw_reset_phy_trx_ok_counters(pAdapter);\n\t\tpAdapter->mppriv.tx.sended += count;\n\t\tcount = 0;\n\t}\n\n\treturn pAdapter->mppriv.tx.sended + count;\n\n}\n\nstatic\tvoid mpt_StopCckContTx(\n\tPADAPTER\tpAdapter\n)\n{\n\tHAL_DATA_TYPE\t*pHalData\t= GET_HAL_DATA(pAdapter);\n\tPMPT_CONTEXT\tpMptCtx = &(pAdapter->mppriv.mpt_ctx);\n\tu8\t\t\tu1bReg;\n\n\tpMptCtx->bCckContTx = FALSE;\n\tpMptCtx->bOfdmContTx = FALSE;\n\n\tphy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);\t/*normal mode*/\n\tphy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1);\t/*turn on scramble setting*/\n\n\tif (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {\n\t\tphy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0);\t\t\t/* 0xa15[1:0] = 2b00*/\n\t\tphy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);\t\t/* 0xc08[16] = 0*/\n\n\t\tphy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);\n\t\tphy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0);\n\t\tphy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0);\n\t}\n\n\t/*BB Reset*/\n\tphy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\n\tphy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\n\n\tif (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {\n\tphy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\n\tphy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\n\t}\n\n\tif (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) || \n\t\tIS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || \n\t\tIS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) || \n\t\tIS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {\n\t\tphy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);/* patch Count CCK adjust Rate*/\n\t}\n\n}\t/* mpt_StopCckContTx */\n\n\nstatic\tvoid mpt_StopOfdmContTx(\n\tPADAPTER\tpAdapter\n)\n{\n\tHAL_DATA_TYPE\t*pHalData\t= GET_HAL_DATA(pAdapter);\n\tPMPT_CONTEXT\tpMptCtx = &(pAdapter->mppriv.mpt_ctx);\n\tu8\t\t\tu1bReg;\n\tu32\t\t\tdata;\n\n\tpMptCtx->bCckContTx = FALSE;\n\tpMptCtx->bOfdmContTx = FALSE;\n\n\tif (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))\n\t\tphy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);\n\telse\n\t\tphy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);\n\n\trtw_mdelay_os(10);\n\n\tif (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)){\n\t\tphy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0);\t\t\t/* 0xa15[1:0] = 0*/\n\t\tphy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);\t\t/* 0xc08[16] = 0*/\n\t}\n\n\t/*BB Reset*/\n\tphy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\n\tphy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\n\n\tif (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {\n\tphy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\n\tphy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\n\t}\n}\t/* mpt_StopOfdmContTx */\n\n\nstatic\tvoid mpt_StartCckContTx(\n\tPADAPTER\t\tpAdapter\n)\n{\n\tHAL_DATA_TYPE\t*pHalData\t= GET_HAL_DATA(pAdapter);\n\tPMPT_CONTEXT\tpMptCtx = &(pAdapter->mppriv.mpt_ctx);\n\tu32\t\t\tcckrate;\n\n\t/* 1. if CCK block on */\n\tif (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn))\n\t\tphy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/\n\n\t/*Turn Off All Test Mode*/\n\tif (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))\n\t\tphy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);\n\telse\n\t\tphy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);\n\n\tcckrate  = pAdapter->mppriv.rateidx;\n\n\tphy_set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);\n\n\tphy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);\t/*transmit mode*/\n\tphy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1);\t/*turn on scramble setting*/\n\n\tif (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {\n\t\tphy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3);\t\t\t/* 0xa15[1:0] = 11 force cck rxiq = 0*/\n\t\tphy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1);\t\t/* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/\n\t\tphy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);\n\t\tphy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1);\n\t\tphy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1);\n\t}\n\n\tif (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {\n\t\tphy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\n\t\tphy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\n\t}\n\n\tif (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) || \n\t\tIS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) || \n\t\tIS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) || \n\t\tIS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {\n\t\tif (pAdapter->mppriv.rateidx == MPT_RATE_1M) /* patch Count CCK adjust Rate*/\n\t\t\tphy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);\n\t\telse\n\t\t\tphy_set_bb_reg(pAdapter, 0xA70, BIT(14), bEnable);\n\t}\n\n\tpMptCtx->bCckContTx = TRUE;\n\tpMptCtx->bOfdmContTx = FALSE;\n\n}\t/* mpt_StartCckContTx */\n\n\nstatic\tvoid mpt_StartOfdmContTx(\n\tPADAPTER\t\tpAdapter\n)\n{\n\tHAL_DATA_TYPE\t*pHalData\t= GET_HAL_DATA(pAdapter);\n\tPMPT_CONTEXT\tpMptCtx = &(pAdapter->mppriv.mpt_ctx);\n\n\t/* 1. if OFDM block on?*/\n\tif (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))\n\t\tphy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/\n\n\t/* 2. set CCK test mode off, set to CCK normal mode*/\n\tphy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);\n\n\t/* 3. turn on scramble setting*/\n\tphy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);\n\n\tif (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {\n\t\tphy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3);\t\t\t/* 0xa15[1:0] = 2b'11*/\n\t\tphy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1);\t\t/* 0xc08[16] = 1*/\n\t}\n\n\t/* 4. Turn On Continue Tx and turn off the other test modes.*/\n\tif (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))\n\t\tphy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);\n\telse\n\t\tphy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);\n\n\tif (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {\n\tphy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\n\tphy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\n\t}\n\n\tpMptCtx->bCckContTx = FALSE;\n\tpMptCtx->bOfdmContTx = TRUE;\n}\t/* mpt_StartOfdmContTx */\n\n#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)  || defined(CONFIG_RTL8822C)\n#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT\nstatic void mpt_convert_phydm_txinfo_for_jaguar3(\n\tRT_PMAC_TX_INFO\tpMacTxInfo, struct phydm_pmac_info *phydmtxinfo)\n{\n\tphydmtxinfo->en_pmac_tx = pMacTxInfo.bEnPMacTx;\n\tphydmtxinfo->mode = pMacTxInfo.Mode;\n\tphydmtxinfo->tx_rate = MRateToHwRate(mpt_to_mgnt_rate(pMacTxInfo.TX_RATE));\n\tphydmtxinfo->tx_sc = pMacTxInfo.TX_SC;\n\tphydmtxinfo->is_short_preamble = pMacTxInfo.bSPreamble;\n\tphydmtxinfo->ndp_sound = pMacTxInfo.NDP_sound;\n\tphydmtxinfo->bw = pMacTxInfo.BandWidth;\n\tphydmtxinfo->m_stbc = pMacTxInfo.m_STBC;\n\tphydmtxinfo->packet_period = pMacTxInfo.PacketPeriod;\n\tphydmtxinfo->packet_count = pMacTxInfo.PacketCount;\n\tphydmtxinfo->packet_pattern = pMacTxInfo.PacketPattern;\n\tphydmtxinfo->sfd = pMacTxInfo.SFD;\n\tphydmtxinfo->signal_field = pMacTxInfo.SignalField;\n\tphydmtxinfo->service_field = pMacTxInfo.ServiceField;\n\tphydmtxinfo->length = pMacTxInfo.LENGTH;\n\t_rtw_memcpy(&phydmtxinfo->crc16,pMacTxInfo.CRC16, 2);\n\t_rtw_memcpy(&phydmtxinfo->lsig , pMacTxInfo.LSIG,3);\n\t_rtw_memcpy(&phydmtxinfo->ht_sig , pMacTxInfo.HT_SIG,6);\n\t_rtw_memcpy(&phydmtxinfo->vht_sig_a , pMacTxInfo.VHT_SIG_A,6);\n\t_rtw_memcpy(&phydmtxinfo->vht_sig_b , pMacTxInfo.VHT_SIG_B,4);\n\tphydmtxinfo->vht_sig_b_crc = pMacTxInfo.VHT_SIG_B_CRC;\n\t_rtw_memcpy(&phydmtxinfo->vht_delimiter,pMacTxInfo.VHT_Delimiter,4);\n}\n#endif\n\n/* for HW TX mode */\nvoid mpt_ProSetPMacTx(PADAPTER\tAdapter)\n{\n\tHAL_DATA_TYPE\t*pHalData\t= GET_HAL_DATA(Adapter);\n\tPMPT_CONTEXT\tpMptCtx\t\t=\t&(Adapter->mppriv.mpt_ctx);\n\tstruct mp_priv *pmppriv = &Adapter->mppriv;\n\tRT_PMAC_TX_INFO\tPMacTxInfo\t=\tpMptCtx->PMacTxInfo;\n\tu32\t\t\tu4bTmp;\n\tstruct dm_struct *p_dm_odm;\n\n\tp_dm_odm = &pHalData->odmpriv;\n\n#if 0\n\tPRINT_DATA(\"LSIG \", PMacTxInfo.LSIG, 3);\n\tPRINT_DATA(\"HT_SIG\", PMacTxInfo.HT_SIG, 6);\n\tPRINT_DATA(\"VHT_SIG_A\", PMacTxInfo.VHT_SIG_A, 6);\n\tPRINT_DATA(\"VHT_SIG_B\", PMacTxInfo.VHT_SIG_B, 4);\n\tdbg_print(\"VHT_SIG_B_CRC %x\\n\", PMacTxInfo.VHT_SIG_B_CRC);\n\tPRINT_DATA(\"VHT_Delimiter\", PMacTxInfo.VHT_Delimiter, 4);\n\n\tPRINT_DATA(\"Src Address\", Adapter->mac_addr, ETH_ALEN);\n\tPRINT_DATA(\"Dest Address\", PMacTxInfo.MacAddress, ETH_ALEN);\n#endif\n\tif (pmppriv->pktInterval != 0)\n\t\tPMacTxInfo.PacketPeriod = pmppriv->pktInterval;\n\n    \tif (pmppriv->tx.count != 0)\n        \tPMacTxInfo.PacketCount = pmppriv->tx.count;\n\n\tRTW_INFO(\"SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\\n\", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);\n\tRTW_INFO(\"TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\\n\", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,\n\t\t PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);\n\n\tif (IS_HARDWARE_TYPE_JAGUAR3(Adapter)) {\n#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT\n\t\tstruct phydm_pmac_info phydm_mactxinfo;\n\n\t\tif (PMacTxInfo.bEnPMacTx == TRUE) {\n\t\t\tpMptCtx->HWTxmode = PMacTxInfo.Mode;\n\t\t\tpMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;\n\t\t\tif (PMacTxInfo.Mode == CONTINUOUS_TX)\n\t\t\t\thal_mpt_SetTxPower(Adapter);\n\t\t} else {\n\t\t\tPMacTxInfo.Mode = pMptCtx->HWTxmode;\n\t\t\tPMacTxInfo.TX_RATE = pMptCtx->mpt_rate_index;\n\t\t\tpMptCtx->HWTxmode = TEST_NONE;\n\t\t}\n\t\tmpt_convert_phydm_txinfo_for_jaguar3(PMacTxInfo, &phydm_mactxinfo);\n\t\tphydm_set_pmac_tx(p_dm_odm, &phydm_mactxinfo, pMptCtx->mpt_rf_path);\n#endif\n\t\treturn;\n\t}\n\n\tif (PMacTxInfo.bEnPMacTx == FALSE) {\n\t\tif (pMptCtx->HWTxmode == CONTINUOUS_TX) {\n\t\t\tphy_set_bb_reg(Adapter, 0xb04, 0xf, 2);\t\t\t/*\tTX Stop*/\n\t\t\tif (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))\n\t\t\t\tmpt_StopCckContTx(Adapter);\n\t\t\telse\n\t\t\t\tmpt_StopOfdmContTx(Adapter);\n\t\t} else if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index)) {\n\t\t\tu4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord);\n\t\t\tphy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);\n\t\t\tphy_set_bb_reg(Adapter, 0xb04, 0xf, 2);\t\t/*TX Stop*/\n\t\t} else\n\t\t\tphy_set_bb_reg(Adapter, 0xb04, 0xf, 2);\t\t/*\tTX Stop*/\n\n\t\tif (pMptCtx->HWTxmode == OFDM_Single_Tone_TX) {\n\t\t\t/* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/\n\t\t\tif (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))\n\t\t\t\tmpt_StopCckContTx(Adapter);\n\t\t\telse\n\t\t\t\tmpt_StopOfdmContTx(Adapter);\n\n\t\t\tmpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);\n\t\t}\n\t\tpMptCtx->HWTxmode = TEST_NONE;\n\t\treturn;\n\t}\n\n    \tpMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;\n\n\tif (PMacTxInfo.Mode == CONTINUOUS_TX) {\n\t\tpMptCtx->HWTxmode = CONTINUOUS_TX;\n\t\tPMacTxInfo.PacketCount = 1;\n\n        \thal_mpt_SetTxPower(Adapter);\n\n\t\tif (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))\n\t\t\tmpt_StartCckContTx(Adapter);\n\t\telse\n\t\t\tmpt_StartOfdmContTx(Adapter);\n\t} else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {\n\t\t/* Continuous TX -> HW TX -> RF Setting */\n\t\tpMptCtx->HWTxmode = OFDM_Single_Tone_TX;\n\t\tPMacTxInfo.PacketCount = 1;\n\n\t\tif (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))\n\t\t\tmpt_StartCckContTx(Adapter);\n\t\telse\n\t\t\tmpt_StartOfdmContTx(Adapter);\n\t} else if (PMacTxInfo.Mode == PACKETS_TX) {\n\t\tpMptCtx->HWTxmode = PACKETS_TX;\n\t\tif (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)\n\t\t\tPMacTxInfo.PacketCount = 0xffff;\n\t}\n\n\tif (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {\n\t\t/* 0xb1c[0:15] TX packet count 0xb1C[31:16]\tSFD*/\n\t\tu4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16);\n\t\tphy_set_bb_reg(Adapter, 0xb1c, bMaskDWord, u4bTmp);\n\t\t/* 0xb40 7:0 SIGNAL\t15:8 SERVICE\t31:16 LENGTH*/\n\t\tu4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16);\n\t\tphy_set_bb_reg(Adapter, 0xb40, bMaskDWord, u4bTmp);\n\t\tu4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);\n\t\tphy_set_bb_reg(Adapter, 0xb44, bMaskLWord, u4bTmp);\n\n\t\tif (PMacTxInfo.bSPreamble)\n\t\t\tphy_set_bb_reg(Adapter, 0xb0c, BIT27, 0);\n\t\telse\n\t\t\tphy_set_bb_reg(Adapter, 0xb0c, BIT27, 1);\n\t} else {\n\t\tphy_set_bb_reg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);\n\n\t\tu4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24);\n\t\tphy_set_bb_reg(Adapter, 0xb08, bMaskDWord, u4bTmp);\t/*\tSet 0xb08[23:0] = LSIG, 0xb08[31:24] =  Data init octet*/\n\n\t\tif (PMacTxInfo.PacketPattern == 0x12)\n\t\t\tu4bTmp = 0x3000000;\n\t\telse\n\t\t\tu4bTmp = 0;\n\t}\n\n\tif (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {\n\t\tu4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16);\n\t\tphy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);\n\t\tu4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16);\n\t\tphy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);\n\t} else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {\n\t\tu4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16);\n\t\tphy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);\n\t\tu4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16);\n\t\tphy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);\n\n\t\t_rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);\n\t\tphy_set_bb_reg(Adapter, 0xb14, bMaskDWord, u4bTmp);\n\t}\n\n\tif (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {\n\t\tu4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod;\t/* for TX interval */\n\t\tphy_set_bb_reg(Adapter, 0xb20, bMaskDWord, u4bTmp);\n\n\t\t_rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);\n\t\tphy_set_bb_reg(Adapter, 0xb24, bMaskDWord, u4bTmp);\n\n\t\t/* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/\n\t\t/*& Duration & Frame control*/\n\t\tphy_set_bb_reg(Adapter, 0xb28, bMaskDWord, 0x00000040);\n\n\t\t/* Address1 [0:3]*/\n\t\tu4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);\n\t\tphy_set_bb_reg(Adapter, 0xb2C, bMaskDWord, u4bTmp);\n\n\t\t/* Address3 [3:0]*/\n\t\tphy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);\n\n\t\t/* Address2[0:1] & Address1 [5:4]*/\n\t\tu4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);\n\t\tphy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);\n\n\t\t/* Address2 [5:2]*/\n\t\tu4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);\n\t\tphy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);\n\n\t\t/* Sequence Control & Address3 [5:4]*/\n\t\t/*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/\n\t\t/*phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/\n\t} else {\n\t\tphy_set_bb_reg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod);\t/* for TX interval*/\n\t\t/* & Duration & Frame control */\n\t\tphy_set_bb_reg(Adapter, 0xb24, bMaskDWord, 0x00000040);\n\n\t\t/* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/\n\t\t/* Address1 [0:3]*/\n\t\tu4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);\n\t\tphy_set_bb_reg(Adapter, 0xb28, bMaskDWord, u4bTmp);\n\n\t\t/* Address3 [3:0]*/\n\t\tphy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);\n\n\t\t/* Address2[0:1] & Address1 [5:4]*/\n\t\tu4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);\n\t\tphy_set_bb_reg(Adapter, 0xb2c, bMaskDWord, u4bTmp);\n\n\t\t/* Address2 [5:2] */\n\t\tu4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);\n\t\tphy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);\n\n\t\t/* Sequence Control & Address3 [5:4]*/\n\t\tu4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);\n\t\tphy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);\n\t}\n\n\tphy_set_bb_reg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);\n\n\t/* 0xb4c 3:0 TXSC\t5:4\tBW\t7:6 m_STBC\t8 NDP_Sound*/\n\tu4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8);\n\tphy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp);\n\n\tif (IS_HARDWARE_TYPE_JAGUAR2(Adapter)) {\n\t\tu32 offset = 0xb44;\n\n\t\tif (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))\n\t\t\tphy_set_bb_reg(Adapter, offset, 0xc0000000, 0);\n\t\telse if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))\n\t\t\tphy_set_bb_reg(Adapter, offset, 0xc0000000, 1);\n\t\telse if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))\n\t\t\tphy_set_bb_reg(Adapter, offset, 0xc0000000, 2);\n\n\t} else if(IS_HARDWARE_TYPE_JAGUAR(Adapter)) {\n\t\tu32 offset = 0xb4c;\n\n\t\tif(IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))\n\t\t\tphy_set_bb_reg(Adapter, offset, 0xc0000000, 0);\n\t\telse if(IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))\n\t\t\tphy_set_bb_reg(Adapter, offset, 0xc0000000, 1);\n\t\telse if(IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))\n\t\t\tphy_set_bb_reg(Adapter, offset, 0xc0000000, 2);\n\t}\n\n\tphy_set_bb_reg(Adapter, 0xb00, BIT8, 1);\t\t/*\tTurn on PMAC*/\n\t/* phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);\t\t\t\t */ /* TX Stop */\n\tif (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {\n\t\tphy_set_bb_reg(Adapter, 0xb04, 0xf, 8);\t\t/*TX CCK ON*/\n\t\tphy_set_bb_reg(Adapter, 0xA84, BIT31, 0);\n\t} else\n\t\tphy_set_bb_reg(Adapter, 0xb04, 0xf, 4);\t\t/*\tTX Ofdm ON\t*/\n\n\tif (PMacTxInfo.Mode == OFDM_Single_Tone_TX)\n\t\tmpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);\n\n}\n\n#endif\n\nvoid hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)\n{\n\tu8 Rate;\n\n\tRTW_INFO(\"SetContinuousTx: rate:%d\\n\", pAdapter->mppriv.rateidx);\n\tRate = HwRateToMPTRate(pAdapter->mppriv.rateidx);\n\tpAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart;\n\n\tif (Rate <= MPT_RATE_11M) {\n\t\tif (bStart)\n\t\t\tmpt_StartCckContTx(pAdapter);\n\t\telse\n\t\t\tmpt_StopCckContTx(pAdapter);\n\n\t} else if (Rate >= MPT_RATE_6M) {\n\t\tif (bStart)\n\t\t\tmpt_StartOfdmContTx(pAdapter);\n\t\telse\n\t\t\tmpt_StopOfdmContTx(pAdapter);\n\t}\n}\n\n#endif /* CONFIG_MP_INCLUDE*/\n"
  },
  {
    "path": "hal/hal_phy.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _HAL_PHY_C_\n\n#include <drv_types.h>\n\n/**\n* Function:\tPHY_CalculateBitShift\n*\n* OverView:\tGet shifted position of the BitMask\n*\n* Input:\n*\t\t\tu32\t\tBitMask,\n*\n* Output:\tnone\n* Return:\t\tu32\t\tReturn the shift bit bit position of the mask\n*/\nu32\nPHY_CalculateBitShift(\n\tu32 BitMask\n)\n{\n\tu32 i;\n\n\tfor (i = 0; i <= 31; i++) {\n\t\tif (((BitMask >> i) &  0x1) == 1)\n\t\t\tbreak;\n\t}\n\n\treturn i;\n}\n\n\n#ifdef CONFIG_RF_SHADOW_RW\n/* ********************************************************************************\n *\tConstant.\n * ********************************************************************************\n * 2008/11/20 MH For Debug only, RF */\nstatic RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];\n\n/*\n * ==> RF shadow Operation API Code Section!!!\n *\n *-----------------------------------------------------------------------------\n * Function:\tPHY_RFShadowRead\n *\t\t\t\tPHY_RFShadowWrite\n *\t\t\t\tPHY_RFShadowCompare\n *\t\t\t\tPHY_RFShadowRecorver\n *\t\t\t\tPHY_RFShadowCompareAll\n *\t\t\t\tPHY_RFShadowRecorverAll\n *\t\t\t\tPHY_RFShadowCompareFlagSet\n *\t\t\t\tPHY_RFShadowRecorverFlagSet\n *\n * Overview:\tWhen we set RF register, we must write shadow at first.\n *\t\t\tWhen we are running, we must compare shadow abd locate error addr.\n *\t\t\tDecide to recorver or not.\n *\n * Input:       NONE\n *\n * Output:      NONE\n *\n * Return:      NONE\n *\n * Revised History:\n * When\t\t\tWho\t\tRemark\n * 11/20/2008\tMHC\t\tCreate Version 0.\n *\n *---------------------------------------------------------------------------*/\nu32\nPHY_RFShadowRead(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tOffset)\n{\n\treturn\tRF_Shadow[eRFPath][Offset].Value;\n\n}\t/* PHY_RFShadowRead */\n\n\nvoid\nPHY_RFShadowWrite(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tOffset,\n\t\tu32\t\t\t\tData)\n{\n\tRF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask);\n\tRF_Shadow[eRFPath][Offset].Driver_Write = _TRUE;\n\n}\t/* PHY_RFShadowWrite */\n\n\nBOOLEAN\nPHY_RFShadowCompare(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tOffset)\n{\n\tu32\treg;\n\t/* Check if we need to check the register */\n\tif (RF_Shadow[eRFPath][Offset].Compare == _TRUE) {\n\t\treg = rtw_hal_read_rfreg(Adapter, eRFPath, Offset, bRFRegOffsetMask);\n\t\t/* Compare shadow and real rf register for 20bits!! */\n\t\tif (RF_Shadow[eRFPath][Offset].Value != reg) {\n\t\t\t/* Locate error position. */\n\t\t\tRF_Shadow[eRFPath][Offset].ErrorOrNot = _TRUE;\n\t\t}\n\t\treturn RF_Shadow[eRFPath][Offset].ErrorOrNot ;\n\t}\n\treturn _FALSE;\n}\t/* PHY_RFShadowCompare */\n\n\nvoid\nPHY_RFShadowRecorver(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tOffset)\n{\n\t/* Check if the address is error */\n\tif (RF_Shadow[eRFPath][Offset].ErrorOrNot == _TRUE) {\n\t\t/* Check if we need to recorver the register. */\n\t\tif (RF_Shadow[eRFPath][Offset].Recorver == _TRUE) {\n\t\t\trtw_hal_write_rfreg(Adapter, eRFPath, Offset, bRFRegOffsetMask,\n\t\t\t\t\t    RF_Shadow[eRFPath][Offset].Value);\n\t\t}\n\t}\n\n}\t/* PHY_RFShadowRecorver */\n\n\nvoid\nPHY_RFShadowCompareAll(\n\t\tPADAPTER\t\t\tAdapter)\n{\n\tenum rf_path\teRFPath = RF_PATH_A;\n\tu32\t\tOffset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);\n\n\tfor (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {\n\t\tfor (Offset = 0; Offset < maxReg; Offset++)\n\t\t\tPHY_RFShadowCompare(Adapter, eRFPath, Offset);\n\t}\n\n}\t/* PHY_RFShadowCompareAll */\n\n\nvoid\nPHY_RFShadowRecorverAll(\n\t\tPADAPTER\t\t\tAdapter)\n{\n\tenum rf_path\t\teRFPath = RF_PATH_A;\n\tu32\t\tOffset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);\n\n\tfor (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {\n\t\tfor (Offset = 0; Offset < maxReg; Offset++)\n\t\t\tPHY_RFShadowRecorver(Adapter, eRFPath, Offset);\n\t}\n\n}\t/* PHY_RFShadowRecorverAll */\n\n\nvoid\nPHY_RFShadowCompareFlagSet(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tOffset,\n\t\tu8\t\t\t\tType)\n{\n\t/* Set True or False!!! */\n\tRF_Shadow[eRFPath][Offset].Compare = Type;\n\n}\t/* PHY_RFShadowCompareFlagSet */\n\n\nvoid\nPHY_RFShadowRecorverFlagSet(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tOffset,\n\t\tu8\t\t\t\tType)\n{\n\t/* Set True or False!!! */\n\tRF_Shadow[eRFPath][Offset].Recorver = Type;\n\n}\t/* PHY_RFShadowRecorverFlagSet */\n\n\nvoid\nPHY_RFShadowCompareFlagSetAll(\n\t\tPADAPTER\t\t\tAdapter)\n{\n\tenum rf_path\teRFPath = RF_PATH_A;\n\tu32\t\tOffset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);\n\n\tfor (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {\n\t\tfor (Offset = 0; Offset < maxReg; Offset++) {\n\t\t\t/* 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! */\n\t\t\tif (Offset != 0x26 && Offset != 0x27)\n\t\t\t\tPHY_RFShadowCompareFlagSet(Adapter, eRFPath, Offset, _FALSE);\n\t\t\telse\n\t\t\t\tPHY_RFShadowCompareFlagSet(Adapter, eRFPath, Offset, _TRUE);\n\t\t}\n\t}\n\n}\t/* PHY_RFShadowCompareFlagSetAll */\n\n\nvoid\nPHY_RFShadowRecorverFlagSetAll(\n\t\tPADAPTER\t\t\tAdapter)\n{\n\tenum rf_path\t\teRFPath = RF_PATH_A;\n\tu32\t\tOffset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);\n\n\tfor (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {\n\t\tfor (Offset = 0; Offset < maxReg; Offset++) {\n\t\t\t/* 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! */\n\t\t\tif (Offset != 0x26 && Offset != 0x27)\n\t\t\t\tPHY_RFShadowRecorverFlagSet(Adapter, eRFPath, Offset, _FALSE);\n\t\t\telse\n\t\t\t\tPHY_RFShadowRecorverFlagSet(Adapter, eRFPath, Offset, _TRUE);\n\t\t}\n\t}\n\n}\t/* PHY_RFShadowCompareFlagSetAll */\n\nvoid\nPHY_RFShadowRefresh(\n\t\tPADAPTER\t\t\tAdapter)\n{\n\tenum rf_path\t\teRFPath = RF_PATH_A;\n\tu32\t\tOffset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);\n\n\tfor (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {\n\t\tfor (Offset = 0; Offset < maxReg; Offset++) {\n\t\t\tRF_Shadow[eRFPath][Offset].Value = 0;\n\t\t\tRF_Shadow[eRFPath][Offset].Compare = _FALSE;\n\t\t\tRF_Shadow[eRFPath][Offset].Recorver  = _FALSE;\n\t\t\tRF_Shadow[eRFPath][Offset].ErrorOrNot = _FALSE;\n\t\t\tRF_Shadow[eRFPath][Offset].Driver_Write = _FALSE;\n\t\t}\n\t}\n\n}\t/* PHY_RFShadowRead */\n#endif /*CONFIG_RF_SHADOW_RW*/\n"
  },
  {
    "path": "hal/halmac/halmac_2_platform.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_2_PLATFORM_H_\n#define _HALMAC_2_PLATFORM_H_\n\n/*[Driver] always set BUILD_TEST =0*/\n#define BUILD_TEST\t0\n\n#if BUILD_TEST\n#include \"../Platform/App/Test/halmac_2_platformapi.h\"\n#else\n/*[Driver] use their own header files*/\n#include <drv_conf.h>\t\t\t/* for basic_types.h and osdep_service.h */\n#include <basic_types.h>\t\t/* u8, u16, u32 and etc.*/\n#include <osdep_service.h>\t\t/* __BIG_ENDIAN, __LITTLE_ENDIAN, _sema, _mutex */\n#endif\n\n/*[Driver] provide the define of NULL, u8, u16, u32*/\n#ifndef NULL\n#define NULL\t\t((void *)0)\n#endif\n\n#define HALMAC_INLINE\tinline\n\n/*\n * Ignore following typedef because Linux already have these\n * u8, u16, u32, s8, s16, s32\n * __le16, __le32, __be16, __be32\n */\n\n#define HALMAC_PLATFORM_LITTLE_ENDIAN\t1\n#define HALMAC_PLATFORM_BIG_ENDIAN\t0\n\n/* Note : Named HALMAC_PLATFORM_LITTLE_ENDIAN / HALMAC_PLATFORM_BIG_ENDIAN\n * is not mandatory. But Little endian must be '1'. Big endian must be '0'\n */\n/*[Driver] config the system endian*/\n#ifdef __LITTLE_ENDIAN\n#define HALMAC_SYSTEM_ENDIAN\tHALMAC_PLATFORM_LITTLE_ENDIAN\n#else /* !__LITTLE_ENDIAN */\n#define HALMAC_SYSTEM_ENDIAN\tHALMAC_PLATFORM_BIG_ENDIAN\n#endif /* !__LITTLE_ENDIAN */\n\n/*[Driver] config if the operating platform*/\n#define HALMAC_PLATFORM_WINDOWS\t\t0\n#define HALMAC_PLATFORM_LINUX\t\t1\n#define HALMAC_PLATFORM_AP\t\t0\n/*[Driver] must set HALMAC_PLATFORM_TESTPROGRAM = 0*/\n#define HALMAC_PLATFORM_TESTPROGRAM\t0\n\n/*[Driver] config if enable the dbg msg or notl*/\n#define HALMAC_DBG_MSG_ENABLE\t\t1\n\n#define HALMAC_MSG_LEVEL_TRACE\t\t3\n#define HALMAC_MSG_LEVEL_WARNING\t2\n#define HALMAC_MSG_LEVEL_ERR\t\t1\n#define HALMAC_MSG_LEVEL_NO_LOG\t\t0\n/*[Driver] config halmac msg level\n * Use HALMAC_MSG_LEVEL_XXXX\n */\n#define HALMAC_MSG_LEVEL HALMAC_MSG_LEVEL_TRACE\n\n/*[Driver] define the Rx FIFO expanding mode packet size unit for 8821C and 8822B */\n/*Should be 8 Byte alignment*/\n#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE\t80 /*Bytes*/\n\n#define HALMAC_USE_TYPEDEF\t\t0\n\n/*[Driver] provide the type mutex*/\n/* Mutex type */\ntypedef _mutex\t\tHALMAC_MUTEX;\n\n#endif /* _HALMAC_2_PLATFORM_H_ */\n\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_8822c/halmac_8822c_cfg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_8822C_CFG_H_\n#define _HALMAC_8822C_CFG_H_\n\n#include \"../../halmac_hw_cfg.h\"\n#include \"../halmac_88xx_cfg.h\"\n\n#if HALMAC_8822C_SUPPORT\n\n#define TX_FIFO_SIZE_8822C\t262144\n#define RX_FIFO_SIZE_8822C\t24576\n#define TRX_SHARE_SIZE0_8822C\t40960\n#define TRX_SHARE_SIZE1_8822C\t24576\n#define TRX_SHARE_SIZE2_8822C\t(TRX_SHARE_SIZE0_8822C + TRX_SHARE_SIZE1_8822C)\n\n#define TX_FIFO_SIZE_LA_8822C\t(TX_FIFO_SIZE_8822C >>  1)\n#define TX_FIFO_SIZE_RX_EXPAND_1BLK_8822C\t\\\n\t(TX_FIFO_SIZE_8822C - TRX_SHARE_SIZE0_8822C)\n#define RX_FIFO_SIZE_RX_EXPAND_1BLK_8822C\t\\\n\t(RX_FIFO_SIZE_8822C + TRX_SHARE_SIZE0_8822C)\n#define TX_FIFO_SIZE_RX_EXPAND_2BLK_8822C\t\\\n\t(TX_FIFO_SIZE_8822C - TRX_SHARE_SIZE2_8822C)\n#define RX_FIFO_SIZE_RX_EXPAND_2BLK_8822C\t\\\n\t(RX_FIFO_SIZE_8822C + TRX_SHARE_SIZE2_8822C)\n#define TX_FIFO_SIZE_RX_EXPAND_3BLK_8822C\t\\\n\t(TX_FIFO_SIZE_8822C - TRX_SHARE_SIZE2_8822C - TRX_SHARE_SIZE0_8822C)\n#define RX_FIFO_SIZE_RX_EXPAND_3BLK_8822C\t\\\n\t(RX_FIFO_SIZE_8822C + TRX_SHARE_SIZE2_8822C + TRX_SHARE_SIZE0_8822C)\n#define TX_FIFO_SIZE_RX_EXPAND_4BLK_8822C\t\\\n\t(TX_FIFO_SIZE_8822C - (2 * TRX_SHARE_SIZE2_8822C))\n#define RX_FIFO_SIZE_RX_EXPAND_4BLK_8822C\t\\\n\t(RX_FIFO_SIZE_8822C + (2 * TRX_SHARE_SIZE2_8822C))\n\n#define EFUSE_SIZE_8822C\t512\n#define EEPROM_SIZE_8822C\t768\n#define BT_EFUSE_SIZE_8822C\t128\n#define PRTCT_EFUSE_SIZE_8822C\t124\n\n#define SEC_CAM_NUM_8822C\t64\n\n#define OQT_ENTRY_AC_8822C\t32\n#define OQT_ENTRY_NOAC_8822C\t32\n#define MACID_MAX_8822C\t\t128\n\n#define WLAN_FW_IRAM_MAX_SIZE_8822C\t65536\n#define WLAN_FW_DRAM_MAX_SIZE_8822C\t65536\n#define WLAN_FW_ERAM_MAX_SIZE_8822C\t131072\n#define WLAN_FW_MAX_SIZE_8822C\t\t(WLAN_FW_IRAM_MAX_SIZE_8822C + \\\n\tWLAN_FW_DRAM_MAX_SIZE_8822C + WLAN_FW_ERAM_MAX_SIZE_8822C)\n\n#endif /* HALMAC_8822C_SUPPORT*/\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_8822c/halmac_cfg_wmac_8822c.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"halmac_cfg_wmac_8822c.h\"\n\n#if HALMAC_8822C_SUPPORT\n\n/**\n * cfg_drv_info_8822c() - config driver info\n * @adapter : the adapter of halmac\n * @drv_info : driver information selection\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_drv_info_8822c(struct halmac_adapter *adapter,\n\t\t   enum halmac_drv_info drv_info)\n{\n\tu8 drv_info_size = 0;\n\tu8 phy_status_en = 0;\n\tu8 sniffer_en = 0;\n\tu8 plcp_hdr_en = 0;\n\tu32 value32;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tstruct halmac_rx_ignore_info *info = &adapter->rx_ignore_info;\n\tstruct halmac_mac_rx_ignore_cfg cfg;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\tPLTFM_MSG_TRACE(\"[TRACE]drv info = %d\\n\", drv_info);\n\n\tswitch (drv_info) {\n\tcase HALMAC_DRV_INFO_NONE:\n\t\tdrv_info_size = 0;\n\t\tphy_status_en = 0;\n\t\tsniffer_en = 0;\n\t\tplcp_hdr_en = 0;\n\t\tinfo->hdr_chk_mask = 1;\n\t\tinfo->fcs_chk_mask = 1;\n\t\tbreak;\n\tcase HALMAC_DRV_INFO_PHY_STATUS:\n\t\tdrv_info_size = 4;\n\t\tphy_status_en = 1;\n\t\tsniffer_en = 0;\n\t\tplcp_hdr_en = 0;\n\t\tinfo->hdr_chk_mask = 1;\n\t\tinfo->fcs_chk_mask = 1;\n\t\tbreak;\n\tcase HALMAC_DRV_INFO_PHY_SNIFFER:\n\t\tdrv_info_size = 5; /* phy status 4byte, sniffer info 1byte */\n\t\tphy_status_en = 1;\n\t\tsniffer_en = 1;\n\t\tplcp_hdr_en = 0;\n\t\tinfo->hdr_chk_mask = 0;\n\t\tinfo->fcs_chk_mask = 0;\n\t\tbreak;\n\tcase HALMAC_DRV_INFO_PHY_PLCP:\n\t\tdrv_info_size = 6; /* phy status 4byte, plcp header 2byte */\n\t\tphy_status_en = 1;\n\t\tsniffer_en = 0;\n\t\tplcp_hdr_en = 1;\n\t\tinfo->hdr_chk_mask = 0;\n\t\tinfo->fcs_chk_mask = 0;\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_SW_CASE_NOT_SUPPORT;\n\t}\n\n\tcfg.hdr_chk_en = info->hdr_chk_en;\n\tcfg.fcs_chk_en = info->fcs_chk_en;\n\tcfg.cck_rst_en = info->cck_rst_en;\n\tcfg.fcs_chk_thr = info->fcs_chk_thr;\n\tapi->halmac_set_hw_value(adapter, HALMAC_HW_RX_IGNORE, &cfg);\n\n\tHALMAC_REG_W8(REG_RX_DRVINFO_SZ, drv_info_size);\n\n\tadapter->drv_info_size = drv_info_size;\n\n\tvalue32 = HALMAC_REG_R32(REG_RCR);\n\tvalue32 = (value32 & (~BIT_APP_PHYSTS));\n\tif (phy_status_en == 1)\n\t\tvalue32 = value32 | BIT_APP_PHYSTS;\n\tHALMAC_REG_W32(REG_RCR, value32);\n\n\tvalue32 = HALMAC_REG_R32(REG_WMAC_OPTION_FUNCTION + 4);\n\tvalue32 = (value32 & (~(BIT(8) | BIT(9))));\n\tif (sniffer_en == 1)\n\t\tvalue32 = value32 | BIT(9);\n\tif (plcp_hdr_en == 1)\n\t\tvalue32 = value32 | BIT(8);\n\tHALMAC_REG_W32(REG_WMAC_OPTION_FUNCTION + 4, value32);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * init_low_pwr_8822c() - config WMAC register\n * @adapter\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ninit_low_pwr_8822c(struct halmac_adapter *adapter)\n{\n\tu16 value16;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\t/*RXGCK FIFO threshold CFG*/\n\tvalue16 = (HALMAC_REG_R16(REG_RXPSF_CTRL + 2) & 0xF00F);\n\tvalue16 |= BIT(10) | BIT(8) | BIT(6) | BIT(4);\n\tHALMAC_REG_W16(REG_RXPSF_CTRL + 2, value16);\n\n\t/*invalid_pkt CFG*/\n\tvalue16 = 0;\n\tvalue16 = BIT_SET_RXPSF_PKTLENTHR(value16, 1);\n\tvalue16 |= BIT_RXPSF_CTRLEN | BIT_RXPSF_VHTCHKEN | BIT_RXPSF_HTCHKEN\n\t\t| BIT_RXPSF_OFDMCHKEN | BIT_RXPSF_CCKCHKEN\n\t\t| BIT_RXPSF_OFDMRST | BIT_RXPSF_CCKRST;\n\n\tHALMAC_REG_W16(REG_RXPSF_CTRL, value16);\n\tHALMAC_REG_W32(REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nvoid\ncfg_rxgck_fifo_8822c(struct halmac_adapter *adapter, u8 enable)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tif (enable == 1) {\n\t\tif (adapter->hw_cfg_info.trx_mode != HALMAC_TRNSFER_NORMAL)\n\t\t\tPLTFM_MSG_ERR(\"[ERR]trx_mode != normal\\n\");\n\t\telse\n\t\t\tHALMAC_REG_W8_SET(REG_RXPSF_CTRL + 3, BIT(4));\n\t} else {\n\t\tHALMAC_REG_W8_CLR(REG_RXPSF_CTRL + 3, BIT(4));\n\t}\n}\n\nvoid\ncfg_rx_ignore_8822c(struct halmac_adapter *adapter,\n\t\t    struct halmac_mac_rx_ignore_cfg *cfg)\n{\n\tu16 value16;\n\tstruct halmac_rx_ignore_info *info = &adapter->rx_ignore_info;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tvalue16 = HALMAC_REG_R16(REG_RXPSF_CTRL);\n\n\tinfo->hdr_chk_en = cfg->hdr_chk_en;\n\tinfo->fcs_chk_en = cfg->fcs_chk_en;\n\tinfo->cck_rst_en = cfg->cck_rst_en;\n\tinfo->fcs_chk_thr = cfg->fcs_chk_thr;\n\n\t/*mac header check enable*/\n\tif (cfg->hdr_chk_en == 1 && info->hdr_chk_mask == 1)\n\t\tvalue16 |= BIT_RXPSF_MHCHKEN;\n\telse\n\t\tvalue16 &= ~(BIT_RXPSF_MHCHKEN);\n\n\t/*continuous FCS error counter enable*/\n\tif (cfg->fcs_chk_en == 1 && info->fcs_chk_mask == 1)\n\t\tvalue16 |= BIT_RXPSF_CONT_ERRCHKEN;\n\telse\n\t\tvalue16 &= ~(BIT_RXPSF_CONT_ERRCHKEN);\n\n\t/*MAC Rx reset when CCK enable*/\n\tif (cfg->cck_rst_en == 1)\n\t\tvalue16 |= BIT_RXPSF_CCKRST;\n\telse\n\t\tvalue16 &= ~(BIT_RXPSF_CCKRST);\n\n\t/*FCS error counter threshold*/\n\tvalue16 = BIT_SET_RXPSF_ERRTHR(value16, cfg->fcs_chk_thr);\n\n\tHALMAC_REG_W16(REG_RXPSF_CTRL, value16);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n}\n\nvoid\ncfg_ampdu_8822c(struct halmac_adapter *adapter,\n\t\tstruct halmac_ampdu_config *cfg)\n{\n\tu32 ht_max_len;\n\tu32 vht_max_len;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tHALMAC_REG_W8(REG_PROT_MODE_CTRL + 2, cfg->max_agg_num);\n\tHALMAC_REG_W8(REG_PROT_MODE_CTRL + 3, cfg->max_agg_num);\n\n\tif (cfg->max_len_en == 1) {\n\t\tht_max_len = cfg->ht_max_len & 0xFFFF;\n\t\tvht_max_len = cfg->vht_max_len & 0xFFFFF;\n\t\tHALMAC_REG_W32(REG_AMPDU_MAX_LENGTH_HT, ht_max_len);\n\t\tHALMAC_REG_W32(REG_AMPDU_MAX_LENGTH_VHT, vht_max_len);\n\t}\n}\n\n#endif /* HALMAC_8822C_SUPPORT */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_8822c/halmac_cfg_wmac_8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_CFG_WMAC_8822C_H_\n#define _HALMAC_CFG_WMAC_8822C_H_\n\n#include \"../../halmac_api.h\"\n\n#if HALMAC_8822C_SUPPORT\n\nenum halmac_ret_status\ncfg_drv_info_8822c(struct halmac_adapter *adapter,\n\t\t   enum halmac_drv_info drv_info);\n\nenum halmac_ret_status\ninit_low_pwr_8822c(struct halmac_adapter *adapter);\n\nvoid\ncfg_rxgck_fifo_8822c(struct halmac_adapter *adapter, u8 enable);\n\nvoid\ncfg_rx_ignore_8822c(struct halmac_adapter *adapter,\n\t\t    struct halmac_mac_rx_ignore_cfg *cfg);\n\nvoid\ncfg_ampdu_8822c(struct halmac_adapter *adapter,\n\t\tstruct halmac_ampdu_config *cfg);\n\n#endif/* HALMAC_8822C_SUPPORT */\n\n#endif/* _HALMAC_CFG_WMAC_8822C_H_ */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_8822c/halmac_common_8822c.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"halmac_8822c_cfg.h\"\n#include \"halmac_common_8822c.h\"\n#include \"../halmac_common_88xx.h\"\n#if HALMAC_SDIO_SUPPORT\n#include \"halmac_sdio_8822c.h\"\n#endif\n#include \"halmac_cfg_wmac_8822c.h\"\n\n#if HALMAC_8822C_SUPPORT\n\nstatic void\ncfg_ldo25_8822c(struct halmac_adapter *adapter, u8 enable);\n\n/**\n * get_hw_value_8822c() -get hw config value\n * @adapter : the adapter of halmac\n * @hw_id : hw id for driver to query\n * @value : hw value, reference table to get data type\n * Author : KaiYuan Chang / Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nget_hw_value_8822c(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,\n\t\t   void *value)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (!value) {\n\t\tPLTFM_MSG_ERR(\"[ERR]%s (NULL ==value)\\n\", __func__);\n\t\treturn HALMAC_RET_NULL_POINTER;\n\t}\n\n\tif (get_hw_value_88xx(adapter, hw_id, value) == HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_SUCCESS;\n\n\tswitch (hw_id) {\n\tcase HALMAC_HW_FW_MAX_SIZE:\n\t\t*(u32 *)value = WLAN_FW_MAX_SIZE_8822C;\n\t\tbreak;\n#if HALMAC_SDIO_SUPPORT\n\tcase HALMAC_HW_SDIO_INT_LAT:\n\t\tif (adapter->intf != HALMAC_INTERFACE_SDIO)\n\t\t\treturn HALMAC_RET_WRONG_INTF;\n\t\t*(u32 *)value = get_sdio_int_lat_8822c(adapter);\n\t\tbreak;\n\tcase HALMAC_HW_SDIO_CLK_CNT:\n\t\tif (adapter->intf != HALMAC_INTERFACE_SDIO)\n\t\t\treturn HALMAC_RET_WRONG_INTF;\n\t\tstatus = get_sdio_clk_cnt_8822c(adapter, (u32 *)value);\n\t\tbreak;\n#endif\n\tdefault:\n\t\treturn HALMAC_RET_PARA_NOT_SUPPORT;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn status;\n}\n\n/**\n * set_hw_value_8822c() -set hw config value\n * @adapter : the adapter of halmac\n * @hw_id : hw id for driver to config\n * @value : hw value, reference table to get data type\n * Author : KaiYuan Chang / Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nset_hw_value_8822c(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,\n\t\t   void *value)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (!value) {\n\t\tPLTFM_MSG_ERR(\"[ERR]null pointer\\n\");\n\t\treturn HALMAC_RET_NULL_POINTER;\n\t}\n\n\tif (set_hw_value_88xx(adapter, hw_id, value) == HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_SUCCESS;\n\n\tswitch (hw_id) {\n\tcase HALMAC_HW_AMPDU_CONFIG:\n\t\tcfg_ampdu_8822c(adapter, (struct halmac_ampdu_config *)value);\n\t\tbreak;\n\tcase HALMAC_HW_RXGCK_FIFO:\n\t\tcfg_rxgck_fifo_8822c(adapter, *(u8 *)value);\n\t\tbreak;\n\tcase HALMAC_HW_RX_IGNORE:\n\t\tcfg_rx_ignore_8822c(adapter,\n\t\t\t\t    (struct halmac_mac_rx_ignore_cfg *)value);\n\t\tbreak;\n\tcase HALMAC_HW_LDO25_EN:\n\t\tcfg_ldo25_8822c(adapter, *(u8 *)value);\n\t\tbreak;\n\tcase HALMAC_HW_PCIE_REF_AUTOK:\n\t\tbreak;\n#if HALMAC_SDIO_SUPPORT\n\tcase HALMAC_HW_SDIO_TX_FORMAT:\n\t\tif (adapter->intf != HALMAC_INTERFACE_SDIO)\n\t\t\treturn HALMAC_RET_WRONG_INTF;\n\t\tstatus =\n\t\tcfg_tx_fmt_sdio_8822c(adapter,\n\t\t\t\t      *(enum halmac_sdio_tx_format *)value);\n\t\tbreak;\n\tcase HALMAC_HW_SDIO_WT_EN:\n\t\tif (adapter->intf != HALMAC_INTERFACE_SDIO)\n\t\t\treturn HALMAC_RET_WRONG_INTF;\n\t\tstatus = set_sdio_wt_en_8822c(adapter, 1);\n\t\tbreak;\n\tcase HALMAC_HW_SDIO_CLK_MONITOR:\n\t\tif (adapter->intf != HALMAC_INTERFACE_SDIO)\n\t\t\treturn HALMAC_RET_WRONG_INTF;\n\t\tstatus =\n\t\tset_sdio_clk_mon_8822c(adapter,\n\t\t\t\t       *(enum halmac_sdio_clk_monitor *)value);\n\t\tbreak;\n#endif\n\tdefault:\n\t\treturn HALMAC_RET_PARA_NOT_SUPPORT;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn status;\n}\n\n/**\n * halmac_fill_txdesc_check_sum_88xx() -  fill in tx desc check sum\n * @adapter : the adapter of halmac\n * @txdesc : tx desc packet\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nfill_txdesc_check_sum_8822c(struct halmac_adapter *adapter, u8 *txdesc)\n{\n\t__le16 chksum = 0;\n\tu16 txdesc_size;\n\t__le16 *data;\n\tu32 i;\n\n\tif (!txdesc) {\n\t\tPLTFM_MSG_ERR(\"[ERR]null pointer\\n\");\n\t\treturn HALMAC_RET_NULL_POINTER;\n\t}\n\n\tif (adapter->tx_desc_checksum != 1)\n\t\tPLTFM_MSG_TRACE(\"[TRACE]chksum disable\\n\");\n\n\tSET_TX_DESC_TXDESC_CHECKSUM(txdesc, 0x0000);\n\n\tdata = (u16 *)(txdesc);\n\n\t/*unit: 4 Bytes*/\n\ttxdesc_size = (u16)((GET_TX_DESC_PKT_OFFSET(txdesc) +\n\t\t\t\t\t(TX_DESC_SIZE_88XX >> 3)) << 1);\n\tfor (i = 0; i < txdesc_size; i++)\n\t\tchksum ^= (*(data + 2 * i) ^ *(data + (2 * i + 1)));\n\n\t/* *(data + 2 * i) & *(data + (2 * i + 1) have endain issue*/\n\t/* Process eniadn issue after checksum calculation */\n\tSET_TX_DESC_TXDESC_CHECKSUM(txdesc, rtk_le16_to_cpu(chksum));\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic void\ncfg_ldo25_8822c(struct halmac_adapter *adapter, u8 enable)\n{\n\tu8 value8;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tvalue8 = HALMAC_REG_R8(REG_ANAPARLDO_POW_MAC);\n\n\tif (enable == 1)\n\t\tHALMAC_REG_W8(REG_ANAPARLDO_POW_MAC, (u8)(value8 | BIT(0)));\n\telse\n\t\tHALMAC_REG_W8(REG_ANAPARLDO_POW_MAC, (u8)(value8 & ~BIT(0)));\n}\n\n#endif /* HALMAC_8822C_SUPPORT */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_8822c/halmac_common_8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_COMMON_8822C_H_\n#define _HALMAC_COMMON_8822C_H_\n\n#include \"../../halmac_api.h\"\n\n#if HALMAC_8822C_SUPPORT\n\nenum halmac_ret_status\nget_hw_value_8822c(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,\n\t\t   void *value);\n\nenum halmac_ret_status\nset_hw_value_8822c(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,\n\t\t   void *value);\n\nenum halmac_ret_status\nfill_txdesc_check_sum_8822c(struct halmac_adapter *adapter, u8 *txdesc);\n\n#endif/* HALMAC_8822C_SUPPORT */\n\n#endif/* _HALMAC_COMMON_8822C_H_ */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_8822c/halmac_gpio_8822c.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"halmac_gpio_8822c.h\"\n#include \"../halmac_gpio_88xx.h\"\n\n#if HALMAC_8822C_SUPPORT\n/* GPIO0 definition */\n#define GPIO0_BT_GPIO0_8822C\t\\\n\t{HALMAC_BT_GPIO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \\\n\t 0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)}\n#define GPIO0_BT_SDIO_INT_8822C\t\\\n\t{HALMAC_BT_SDIO_INT, HALMAC_GPIO0, HALMAC_GPIO_OUT, \\\n\t 0x4F, BIT(5), BIT(5)}\n#define GPIO0_USIN0_8822C\t\\\n\t{HALMAC_UART0, HALMAC_GPIO0, HALMAC_GPIO_IN, \\\n\t 0x66, BIT(6), BIT(6)}\n#define GPIO0_BT_ANT_SW_0_8822C\t\\\n\t{HALMAC_BT_RF, HALMAC_GPIO0, HALMAC_GPIO_OUT, \\\n\t 0x4F, BIT(6), BIT(6)}\n#define GPIO0_BT_ACT_8822C\t\\\n\t{HALMAC_BT_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \\\n\t 0x41, BIT(1), 0}\n#define GPIO0_WL_ACT_8822C\t\\\n\t{HALMAC_WL_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \\\n\t 0x41, BIT(2), BIT(2)}\n#define GPIO0_WLMAC_DBG_GPIO0_8822C\t\\\n\t{HALMAC_WLMAC_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(0)}\n#define GPIO0_WLPHY_DBG_GPIO0_8822C\t\\\n\t{HALMAC_WLPHY_DBG, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(1)}\n#define GPIO0_BT_DBG_GPIO0_8822C\t\\\n\t{HALMAC_BT_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}\n#define GPIO0_ANT_SW_GPIO0_8822C\t\\\n\t{HALMAC_SW_DPDT_SEL, HALMAC_GPIO0, HALMAC_GPIO_OUT, \\\n\t 0x4E, BIT(7), BIT(7)}\n#define GPIO0_BT_RFE_CTRL_1_8822C\t\\\n\t{HALMAC_BT_DPDT_SEL, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \\\n\t 0x42, BIT(1), BIT(1)}\n#define GPIO0_WL_RFE_CTRL_9_8822C\t\\\n\t{HALMAC_WL_DPDT_SEL, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \\\n\t 0x42, BIT(1), BIT(1)}\n#define GPIO0_RFE_CTRL_10_4_5_8822C\t\\\n\t{HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(2), BIT(2)}\n#define GPIO0_RFE_CTRL_10_6_7_8822C\t\\\n\t{HALMAC_WLPHY_RFE_CTRL2GPIO_2, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(3), BIT(3)}\n#define GPIO0_SW_IO_8822C\t\\\n\t{HALMAC_SW_IO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), 0}\n\n/* GPIO 1 definition */\n#define GPIO1_BT_GPIO1_8822C\t\\\n\t{HALMAC_BT_GPIO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \\\n\t 0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)}\n#define GPIO1_USOUT0_8822C\t\\\n\t{HALMAC_UART0, HALMAC_GPIO1, HALMAC_GPIO_OUT, \\\n\t 0x66, BIT(6), BIT(6)}\n#define GPIO1_BT_ANT_SW_1_8822C\t\\\n\t{HALMAC_BT_RF, HALMAC_GPIO1, HALMAC_GPIO_OUT, \\\n\t 0x4F, BIT(6), BIT(6)}\n#define GPIO1_BT_3DD_SYNC_A_8822C\t\\\n\t{HALMAC_BT_3DDLS_A, HALMAC_GPIO1, HALMAC_GPIO_IN, \\\n\t 0x66, BIT(2), 0}\n#define GPIO1_WL_CK_8822C\t\\\n\t{HALMAC_BT_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, \\\n\t 0x41, BIT(1), 0}\n#define GPIO1_BT_CK_8822C\t\\\n\t{HALMAC_WL_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, \\\n\t 0x41, BIT(2), BIT(2)}\n#define GPIO1_WLMAC_DBG_GPIO1_8822C\t\\\n\t{HALMAC_WLMAC_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(0)}\n#define GPIO1_WLPHY_DBG_GPIO1_8822C\t\\\n\t{HALMAC_WLPHY_DBG, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(1)}\n#define GPIO1_BT_DBG_GPIO1_8822C\t\\\n\t{HALMAC_BT_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}\n#define GPIO1_ANT_SWB_GPIO1_8822C\t\\\n\t{HALMAC_SW_DPDT_SEL, HALMAC_GPIO1, HALMAC_GPIO_OUT, \\\n\t 0x4E, BIT(7), BIT(7)}\n#define GPIO1_BT_RFE_CTRL_0_8822C\t\\\n\t{HALMAC_BT_DPDT_SEL, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \\\n\t 0x42, BIT(1), BIT(1)}\n#define GPIO1_WL_RFE_CTRL_8_8822C\t\\\n\t{HALMAC_WL_DPDT_SEL, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \\\n\t 0x42, BIT(1), BIT(1)}\n#define GPIO1_RFE_CTRL_5_4_5_8822C\t\\\n\t{HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(2), BIT(2)}\n#define GPIO1_RFE_CTRL_5_6_7_8822C\t\\\n\t{HALMAC_WLPHY_RFE_CTRL2GPIO_2, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(3), BIT(3)}\n#define GPIO1_SW_IO_8822C\t\\\n\t{HALMAC_SW_IO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), 0}\n\n/* GPIO2 definition */\n#define GPIO2_BT_GPIO2_8822C\t\\\n\t{HALMAC_BT_GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \\\n\t 0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)}\n#define GPIO2_BT_ANT_SW_2_8822C\t\\\n\t{HALMAC_BT_RF, HALMAC_GPIO2, HALMAC_GPIO_OUT, \\\n\t 0x4F, BIT(6), BIT(6)}\n#define GPIO2_WL_STATE_8822C\t\\\n\t{HALMAC_BT_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, \\\n\t 0x41, BIT(1), 0}\n#define GPIO2_BT_STATE_8822C\t\\\n\t{HALMAC_WL_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, \\\n\t 0x41, BIT(2), BIT(2)}\n#define GPIO2_WLMAC_DBG_GPIO2_8822C\t\\\n\t{HALMAC_WLMAC_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(0)}\n#define GPIO2_WLPHY_DBG_GPIO2_8822C\t\\\n\t{HALMAC_WLPHY_DBG, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(1)}\n#define GPIO2_BT_DBG_GPIO2_8822C\t\\\n\t{HALMAC_BT_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}\n#define GPIO2_RFE_CTRL_11_4_5_8822C\t\\\n\t{HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(2), BIT(2)}\n#define GPIO2_RFE_CTRL_11_6_7_8822C\t\\\n\t{HALMAC_WLPHY_RFE_CTRL2GPIO_2, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(3), BIT(3)}\n#define GPIO2_SW_IO_8822C\t\\\n\t{HALMAC_SW_IO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), 0}\n\n/* GPIO3 definition */\n#define GPIO3_BT_GPIO3_8822C\t\\\n\t{HALMAC_BT_GPIO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \\\n\t 0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)}\n#define GPIO3_BT_ANT_SW_3_8822C\t\\\n\t{HALMAC_BT_RF, HALMAC_GPIO3, HALMAC_GPIO_OUT, \\\n\t 0x4F, BIT(6), BIT(6)}\n#define GPIO3_WL_PRI_8822C\t\\\n\t{HALMAC_BT_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, \\\n\t 0x41, BIT(1), 0}\n#define GPIO3_BT_PRI_8822C\t\\\n\t{HALMAC_WL_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, \\\n\t 0x41, BIT(2), BIT(2)}\n#define GPIO3_WLMAC_DBG_GPIO3_8822C\t\\\n\t{HALMAC_WLMAC_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(0)}\n#define GPIO3_WLPHY_DBG_GPIO3_8822C\t\\\n\t{HALMAC_WLPHY_DBG, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(1)}\n#define GPIO3_BT_DBG_GPIO3_8822C\t\\\n\t{HALMAC_BT_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}\n#define GPIO3_LNAON_SEL_8822C\t\\\n\t{HALMAC_SW_LNAON_SET, HALMAC_GPIO3, HALMAC_GPIO_OUT, \\\n\t 0x4F, BIT(2), BIT(2)}\n#define GPIO3_BT_RFE_CTRL_5_8822C\t\\\n\t{HALMAC_BT_LNAON_SEL, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \\\n\t 0x42, BIT(0), BIT(0)}\n#define GPIO3_RFE_CTRL_3_8822C\t\\\n\t{HALMAC_WLBT_LNAON_SEL, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \\\n\t 0x42, BIT(0), BIT(0)}\n#define GPIO3_SW_IO_8822C\t\\\n\t{HALMAC_SW_IO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), 0}\n\n/* GPIO4 definition */\n#define GPIO4_BT_SPI_D0_8822C\t\\\n\t{HALMAC_BT_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \\\n\t 0x66, BIT(4), BIT(4)}\n#define GPIO4_WL_SPI_D0_8822C\t\\\n\t{HALMAC_WL_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \\\n\t 0x42, BIT(3), BIT(3)}\n#define GPIO4_BT_JTAG_TRST_8822C\t\\\n\t{HALMAC_BT_JTAG, HALMAC_GPIO4, HALMAC_GPIO_IN, \\\n\t 0x67, BIT(0), BIT(0)}\n#define GPIO4_WL_JTAG_TRST_8822C\t\\\n\t{HALMAC_WL_JTAG, HALMAC_GPIO4, HALMAC_GPIO_IN, \\\n\t 0x65, BIT(7), BIT(7)}\n#define GPIO4_DBG_GNT_WL_8822C\t\\\n\t{HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO4, HALMAC_GPIO_OUT, \\\n\t 0x73, BIT(3), BIT(3)}\n#define GPIO4_WLMAC_DBG_GPIO4_8822C\t\\\n\t{HALMAC_WLMAC_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(0)}\n#define GPIO4_WLPHY_DBG_GPIO4_8822C\t\\\n\t{HALMAC_WLPHY_DBG, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(1)}\n#define GPIO4_BT_DBG_GPIO4_8822C\t\\\n\t{HALMAC_BT_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}\n#define GPIO4_ANT_SWB_GPIO4_8822C\t\\\n\t{HALMAC_SW_DPDT_SEL, HALMAC_GPIO4, HALMAC_GPIO_OUT, \\\n\t 0x4E, BIT(7), BIT(7)}\n#define GPIO4_BT_RFE_CTRL_0_8822C\t\\\n\t{HALMAC_BT_DPDT_SEL, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \\\n\t 0x42, BIT(1), BIT(1)}\n#define GPIO4_WL_RFE_CTRL_8_8822C\t\\\n\t{HALMAC_WL_DPDT_SEL, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \\\n\t 0x42, BIT(1), BIT(1)}\n#define GPIO4_SW_IO_8822C\t\\\n\t{HALMAC_SW_IO, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), 0}\n\n/* GPIO5 definition */\n#define GPIO5_BT_SPI_D1_8822C\t\\\n\t{HALMAC_BT_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_OUT, \\\n\t 0x66, BIT(4), BIT(4)}\n#define GPIO5_WL_SPI_D1_8822C\t\\\n\t{HALMAC_WL_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_OUT, \\\n\t 0x42, BIT(3), BIT(3)}\n#define GPIO5_BT_JTAG_TDI_8822C\t\\\n\t{HALMAC_BT_JTAG, HALMAC_GPIO5, HALMAC_GPIO_IN, \\\n\t 0x67, BIT(0), BIT(0)}\n#define GPIO5_WL_JTAG_TDI_8822C\t\\\n\t{HALMAC_WL_JTAG, HALMAC_GPIO5, HALMAC_GPIO_IN, \\\n\t 0x65, BIT(7), BIT(7)}\n#define GPIO5_DBG_GNT_BT_8822C\t\\\n\t{HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO5, HALMAC_GPIO_OUT, \\\n\t 0x73, BIT(3), BIT(3)}\n#define GPIO5_BT_GPIO18_8822C\t\\\n\t{HALMAC_BT_GPIO, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \\\n\t 0x67, BIT(1), BIT(1)}\n#define GPIO5_SOUT_8822C\t\\\n\t{HALMAC_WL_UART, HALMAC_GPIO5, HALMAC_GPIO_OUT, \\\n\t 0x41, BIT(0), BIT(0)}\n#define GPIO5_WLMAC_DBG_GPIO5_8822C\t\\\n\t{HALMAC_WLMAC_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(0)}\n#define GPIO5_WLPHY_DBG_GPIO5_8822C\t\\\n\t{HALMAC_WLPHY_DBG, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(1)}\n#define GPIO5_BT_DBG_GPIO5_8822C\t\\\n\t{HALMAC_BT_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}\n#define GPIO5_I2C_INT_3_WIRE_8822C\t\\\n\t{HALMAC_MAILBOX_3W, HALMAC_GPIO5, HALMAC_GPIO_IN, \\\n\t 0x4F, BIT(4), BIT(4)}\n#define GPIO5_I2C_INT_1_WIRE_8822C\t\\\n\t{HALMAC_MAILBOX_1W, HALMAC_GPIO5, HALMAC_GPIO_IN, \\\n\t 0x4F, BIT(7), BIT(7)}\n#define GPIO5_SW_IO_8822C\t\\\n\t{HALMAC_SW_IO, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), 0}\n\n/* GPIO6 definition */\n#define GPIO6_BT_SPI_D2_8822C\t\\\n\t{HALMAC_BT_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_OUT, \\\n\t 0x66, BIT(4), BIT(4)}\n#define GPIO6_WL_SPI_D2_8822C\t\\\n\t{HALMAC_WL_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_OUT, \\\n\t 0x42, BIT(3), BIT(3)}\n#define GPIO6_EEDO_8822C\t\\\n\t{HALMAC_EEPROM, HALMAC_GPIO6, HALMAC_GPIO_IN, \\\n\t 0x40, BIT(4), BIT(4)}\n#define GPIO6_BT_JTAG_TDO_8822C\t\\\n\t{HALMAC_BT_JTAG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \\\n\t 0x67, BIT(0), BIT(0)}\n#define GPIO6_WL_JTAG_TDO_8822C\t\\\n\t{HALMAC_WL_JTAG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \\\n\t 0x65, BIT(0), BIT(0)}\n#define GPIO6_BT_3DD_SYNC_B_8822C\t\\\n\t{HALMAC_BT_3DDLS_B, HALMAC_GPIO6, HALMAC_GPIO_IN, \\\n\t 0x67, BIT(1), BIT(1)}\n#define GPIO6_SIN_8822C\t\\\n\t{HALMAC_WL_UART, HALMAC_GPIO6, HALMAC_GPIO_IN, \\\n\t 0x41, BIT(0), BIT(0)}\n#define GPIO6_WLMAC_DBG_GPIO6_8822C\t\\\n\t{HALMAC_WLMAC_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(0)}\n#define GPIO6_WLPHY_DBG_GPIO6_8822C\t\\\n\t{HALMAC_WLPHY_DBG, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(1)}\n#define GPIO6_BT_DBG_GPIO6_8822C\t\\\n\t{HALMAC_BT_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}\n#define GPIO6_SW_PAPE_SEL_8822C\t\\\n\t{HALMAC_SW_PAPE_SEL, HALMAC_GPIO6, HALMAC_GPIO_OUT, \\\n\t 0x4F, BIT(1), BIT(1)}\n#define GPIO6_BT_RFE_CTRL_3_8822C\t\\\n\t{HALMAC_BT_PAPE_SEL, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \\\n\t 0x4F, BIT(3), BIT(3)}\n#define GPIO6_RFE_CTRL_1_8822C\t\\\n\t{HALMAC_WLBT_PAPE_SEL, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \\\n\t 0x4F, BIT(3), BIT(3)}\n#define GPIO6_EXT_SWR_CTRL_8822C\t\\\n\t{HALMAC_SWR_CTRL_EN, HALMAC_GPIO6, HALMAC_GPIO_IN, \\\n\t 0x7F, BIT(7), BIT(7)}\n#define GPIO6_SW_IO_8822C\t\\\n\t{HALMAC_SW_IO, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), 0}\n\n/* GPIO7 definition */\n#define GPIO7_BT_SPI_D3_8822C\t\\\n\t{HALMAC_BT_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_OUT, \\\n\t 0x66, BIT(4), BIT(4)}\n#define GPIO7_WL_SPI_D3_8822C\t\\\n\t{HALMAC_WL_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_OUT, \\\n\t 0x42, BIT(3), BIT(3)}\n#define GPIO7_EEDI_8822C\t\\\n\t{HALMAC_EEPROM, HALMAC_GPIO7, HALMAC_GPIO_OUT, \\\n\t 0x40, BIT(4), BIT(4)}\n#define GPIO7_BT_JTAG_TMS_8822C\t\\\n\t{HALMAC_BT_JTAG, HALMAC_GPIO7, HALMAC_GPIO_IN, \\\n\t 0x67, BIT(0), BIT(0)}\n#define GPIO7_WL_JTAG_TMS_8822C\t\\\n\t{HALMAC_WL_JTAG, HALMAC_GPIO7, HALMAC_GPIO_IN, \\\n\t 0x65, BIT(7), BIT(7)}\n#define GPIO7_BT_GPIO16_8822C\t\\\n\t{HALMAC_BT_GPIO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \\\n\t 0x67, BIT(2), BIT(2)}\n#define GPIO7_SOUT_8822C\t\\\n\t{HALMAC_WL_UART, HALMAC_GPIO7, HALMAC_GPIO_OUT, \\\n\t 0x41, BIT(0), BIT(0)}\n#define GPIO7_WLMAC_DBG_GPIO7_8822C\t\\\n\t{HALMAC_WLMAC_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(0)}\n#define GPIO7_WLPHY_DBG_GPIO7_8822C\t\\\n\t{HALMAC_WLPHY_DBG, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(1)}\n#define GPIO7_BT_DBG_GPIO7_8822C\t\\\n\t{HALMAC_BT_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, \\\n\t 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}\n#define GPIO7_LNAON_SEL_8822C\t\\\n\t{HALMAC_SW_LNAON_SET, HALMAC_GPIO7, HALMAC_GPIO_OUT, \\\n\t 0x4F, BIT(2), BIT(2)}\n#define GPIO7_BT_RFE_CTRL_4_8822C\t\\\n\t{HALMAC_BT_LNAON_SEL, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \\\n\t 0x42, BIT(0), BIT(0)}\n#define GPIO7_RFE_CTRL_2_8822C\t\\\n\t{HALMAC_WLBT_LNAON_SEL, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \\\n\t 0x42, BIT(0), BIT(0)}\n#define GPIO7_SW_IO_8822C\t\\\n\t{HALMAC_SW_IO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), 0}\n\n/* GPIO8 definition */\n#define GPIO8_WL_EXT_WOL_8822C\t\\\n\t{HALMAC_WL_HW_EXTWOL, HALMAC_GPIO8, HALMAC_GPIO_IN, \\\n\t 0x4A, BIT(1) | BIT(0), BIT(1) | BIT(0)}\n#define GPIO8_WL_LED_8822C\t\\\n\t{HALMAC_WL_LED, HALMAC_GPIO8, HALMAC_GPIO_OUT, \\\n\t 0x4E, BIT(5), BIT(5)}\n#define GPIO8_SOUT_8822C\t\\\n\t{HALMAC_WL_UART, HALMAC_GPIO8, HALMAC_GPIO_OUT, \\\n\t 0x41, BIT(0), BIT(0)}\n#define GPIO8_SW_IO_8822C\t\\\n\t{HALMAC_SW_IO, HALMAC_GPIO8, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), 0}\n\n/* GPIO9 definition */\n#define GPIO9_DIS_WL_N_8822C\t\\\n\t{HALMAC_WL_HWPDN, HALMAC_GPIO9, HALMAC_GPIO_IN, \\\n\t 0x68, BIT(3) | BIT(0), BIT(3) | BIT(0)}\n#define GPIO9_WL_EXT_WOL_8822C\t\\\n\t{HALMAC_WL_HW_EXTWOL, HALMAC_GPIO9, HALMAC_GPIO_IN, \\\n\t 0x4A, BIT(1) | BIT(0), BIT(0)}\n#define GPIO9_USIN0_8822C\t\\\n\t{HALMAC_UART0, HALMAC_GPIO9, HALMAC_GPIO_IN, \\\n\t 0x66, BIT(6), BIT(6)}\n#define GPIO9_I2C_SD_8822C\t\\\n\t{HALMAC_MAILBOX_3W, HALMAC_GPIO9, HALMAC_GPIO_IN, \\\n\t 0x4F, BIT(4), BIT(4)}\n#define GPIO9_LNAON_SEL_8822C\t\\\n\t{HALMAC_SW_LNAON_SET, HALMAC_GPIO9, HALMAC_GPIO_OUT, \\\n\t 0x4F, BIT(2), BIT(2)}\n#define GPIO9_BT_RFE_CTRL_4_8822C\t\\\n\t{HALMAC_BT_LNAON_SEL, HALMAC_GPIO9, HALMAC_GPIO_IN_OUT, \\\n\t 0x42, BIT(0), BIT(0)}\n#define GPIO9_RFE_CTRL_2_8822C\t\\\n\t{HALMAC_WLBT_LNAON_SEL, HALMAC_GPIO9, HALMAC_GPIO_IN_OUT, \\\n\t 0x42, BIT(0), BIT(0)}\n#define GPIO9_SW_IO_8822C\t\\\n\t{HALMAC_SW_IO, HALMAC_GPIO9, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), 0}\n\n/* GPIO10 definition */\n#define GPIO10_WL_SDIO_INT_8822C\t\\\n\t{HALMAC_SDIO_INT, HALMAC_GPIO10, HALMAC_GPIO_OUT, \\\n\t 0x72, BIT(2), BIT(2)}\n#define GPIO10_SW_IO_8822C\t\\\n\t{HALMAC_SW_IO, HALMAC_GPIO10, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), 0}\n\n/* GPIO11 definition */\n#define GPIO11_DIS_BT_N_8822C\t\\\n\t{HALMAC_BT_HWPDN, HALMAC_GPIO11, HALMAC_GPIO_IN, \\\n\t 0x6A, BIT(3) | BIT(0), BIT(3) | BIT(0)}\n#define GPIO11_USOUT0_8822C\t\\\n\t{HALMAC_UART0, HALMAC_GPIO11, HALMAC_GPIO_OUT, \\\n\t 0x66, BIT(6), BIT(6)}\n#define GPIO11_RFE_CTRL_11_4_5_8822C\t\\\n\t{HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO11, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(2), BIT(2)}\n#define GPIO11_RFE_CTRL_11_6_7_8822C\t\\\n\t{HALMAC_WLPHY_RFE_CTRL2GPIO_2, HALMAC_GPIO11, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(3), BIT(3)}\n#define GPIO11_SW_IO_8822C\t\\\n\t{HALMAC_SW_IO, HALMAC_GPIO11, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), 0}\n\n/* GPIO12 definition */\n#define GPIO12_USCTS0_8822C\t\\\n\t{HALMAC_UART0, HALMAC_GPIO12, HALMAC_GPIO_IN, \\\n\t 0x66, BIT(6), BIT(6)}\n#define GPIO12_I2C_CLK_8822C\t\\\n\t{HALMAC_MAILBOX_3W, HALMAC_GPIO12, HALMAC_GPIO_IN, \\\n\t 0x4F, BIT(4), BIT(4)}\n#define GPIO12_ANT_SW_GPIO12_8822C\t\\\n\t{HALMAC_SW_DPDT_SEL, HALMAC_GPIO12, HALMAC_GPIO_OUT, \\\n\t 0x4E, BIT(7), BIT(7)}\n#define GPIO12_BT_RFE_CTRL_1_8822C\t\\\n\t{HALMAC_BT_DPDT_SEL, HALMAC_GPIO12, HALMAC_GPIO_IN_OUT, \\\n\t 0x42, BIT(1), BIT(1)}\n#define GPIO12_WL_RFE_CTRL_9_8822C\t\\\n\t{HALMAC_WL_DPDT_SEL, HALMAC_GPIO12, HALMAC_GPIO_IN_OUT, \\\n\t 0x42, BIT(1), BIT(1)}\n#define GPIO12_SW_IO_8822C\t\\\n\t{HALMAC_SW_IO, HALMAC_GPIO12, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), 0}\n\n/* GPIO13 definition */\n#define GPIO13_BT_WAKE_8822C\t\\\n\t{HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO13, HALMAC_GPIO_IN, \\\n\t 0x4E, BIT(6), BIT(6)}\n#define GPIO13_BT_ANT_SW_0_8822C\t\\\n\t{HALMAC_BT_RF, HALMAC_GPIO13, HALMAC_GPIO_OUT, \\\n\t 0x4F, BIT(6), BIT(6)}\n#define GPIO13_ANT_SW_GPIO13_8822C\t\\\n\t{HALMAC_SW_DPDT_SEL, HALMAC_GPIO13, HALMAC_GPIO_OUT, \\\n\t 0x4E, BIT(7), BIT(7)}\n#define GPIO13_BT_RFE_CTRL_1_8822C\t\\\n\t{HALMAC_BT_DPDT_SEL, HALMAC_GPIO13, HALMAC_GPIO_IN_OUT, \\\n\t 0x42, BIT(1), BIT(1)}\n#define GPIO13_WL_RFE_CTRL_9_8822C\t\\\n\t{HALMAC_WL_DPDT_SEL, HALMAC_GPIO13, HALMAC_GPIO_IN_OUT, \\\n\t 0x42, BIT(1), BIT(1)}\n#define GPIO13_RFE_CTRL_10_4_5_8822C\t\\\n\t{HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO13, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(2), BIT(2)}\n#define GPIO13_RFE_CTRL_10_6_7_8822C\t\\\n\t{HALMAC_WLPHY_RFE_CTRL2GPIO_2, HALMAC_GPIO13, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(3), BIT(3)}\n#define GPIO13_SW_IO_8822C\t\\\n\t{HALMAC_SW_IO, HALMAC_GPIO13, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), 0}\n\n/* GPIO14 definition */\n#define GPIO14_UART_WAKE_8822C\t\\\n\t{HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO14, HALMAC_GPIO_OUT, \\\n\t 0x4E, BIT(6), BIT(6)}\n#define GPIO14_BT_ANT_SW_1_8822C\t\\\n\t{HALMAC_BT_RF, HALMAC_GPIO14, HALMAC_GPIO_OUT, \\\n\t 0x4F, BIT(6), BIT(6)}\n#define GPIO14_RFE_CTRL_5_4_5_8822C\t\\\n\t{HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO14, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(2), BIT(2)}\n#define GPIO14_RFE_CTRL_5_6_7_8822C\t\\\n\t{HALMAC_WLPHY_RFE_CTRL2GPIO_2, HALMAC_GPIO14, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(3), BIT(3)}\n#define GPIO14_SW_IO_8822C\t\\\n\t{HALMAC_SW_IO, HALMAC_GPIO14, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), 0}\n\n/* GPIO15 definition */\n#define GPIO15_EXT_XTAL_8822C\t\\\n\t{HALMAC_EXT_XTAL, HALMAC_GPIO15, HALMAC_GPIO_OUT, \\\n\t 0x66, BIT(7), BIT(7)}\n#define GPIO15_SW_IO_8822C\t\\\n\t{HALMAC_SW_IO, HALMAC_GPIO15, HALMAC_GPIO_IN_OUT, \\\n\t 0x40, BIT(1) | BIT(0), 0}\n\nstatic const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO0_8822C[] = {\n\tGPIO0_BT_GPIO0_8822C,\n\tGPIO0_BT_SDIO_INT_8822C,\n\tGPIO0_USIN0_8822C,\n\tGPIO0_BT_ANT_SW_0_8822C,\n\tGPIO0_BT_ACT_8822C,\n\tGPIO0_WL_ACT_8822C,\n\tGPIO0_WLMAC_DBG_GPIO0_8822C,\n\tGPIO0_WLPHY_DBG_GPIO0_8822C,\n\tGPIO0_BT_DBG_GPIO0_8822C,\n\tGPIO0_ANT_SW_GPIO0_8822C,\n\tGPIO0_BT_RFE_CTRL_1_8822C,\n\tGPIO0_WL_RFE_CTRL_9_8822C,\n\tGPIO0_RFE_CTRL_10_4_5_8822C,\n\tGPIO0_RFE_CTRL_10_6_7_8822C,\n\tGPIO0_SW_IO_8822C\n};\n\nstatic const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO1_8822C[] = {\n\tGPIO1_BT_GPIO1_8822C,\n\tGPIO1_USOUT0_8822C,\n\tGPIO1_BT_ANT_SW_1_8822C,\n\tGPIO1_BT_3DD_SYNC_A_8822C,\n\tGPIO1_WL_CK_8822C,\n\tGPIO1_BT_CK_8822C,\n\tGPIO1_WLMAC_DBG_GPIO1_8822C,\n\tGPIO1_WLPHY_DBG_GPIO1_8822C,\n\tGPIO1_BT_DBG_GPIO1_8822C,\n\tGPIO1_ANT_SWB_GPIO1_8822C,\n\tGPIO1_BT_RFE_CTRL_0_8822C,\n\tGPIO1_WL_RFE_CTRL_8_8822C,\n\tGPIO1_RFE_CTRL_5_4_5_8822C,\n\tGPIO1_RFE_CTRL_5_6_7_8822C,\n\tGPIO1_SW_IO_8822C\n};\n\nstatic const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO2_8822C[] = {\n\tGPIO2_BT_GPIO2_8822C,\n\tGPIO2_BT_ANT_SW_2_8822C,\n\tGPIO2_WL_STATE_8822C,\n\tGPIO2_BT_STATE_8822C,\n\tGPIO2_WLMAC_DBG_GPIO2_8822C,\n\tGPIO2_WLPHY_DBG_GPIO2_8822C,\n\tGPIO2_BT_DBG_GPIO2_8822C,\n\tGPIO2_RFE_CTRL_11_4_5_8822C,\n\tGPIO2_RFE_CTRL_11_6_7_8822C,\n\tGPIO2_SW_IO_8822C\n};\n\nstatic const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO3_8822C[] = {\n\tGPIO3_BT_GPIO3_8822C,\n\tGPIO3_BT_ANT_SW_3_8822C,\n\tGPIO3_WL_PRI_8822C,\n\tGPIO3_BT_PRI_8822C,\n\tGPIO3_WLMAC_DBG_GPIO3_8822C,\n\tGPIO3_WLPHY_DBG_GPIO3_8822C,\n\tGPIO3_BT_DBG_GPIO3_8822C,\n\tGPIO3_LNAON_SEL_8822C,\n\tGPIO3_BT_RFE_CTRL_5_8822C,\n\tGPIO3_RFE_CTRL_3_8822C,\n\tGPIO3_SW_IO_8822C\n};\n\nstatic const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO4_8822C[] = {\n\tGPIO4_BT_SPI_D0_8822C,\n\tGPIO4_WL_SPI_D0_8822C,\n\tGPIO4_BT_JTAG_TRST_8822C,\n\tGPIO4_WL_JTAG_TRST_8822C,\n\tGPIO4_DBG_GNT_WL_8822C,\n\tGPIO4_WLMAC_DBG_GPIO4_8822C,\n\tGPIO4_WLPHY_DBG_GPIO4_8822C,\n\tGPIO4_BT_DBG_GPIO4_8822C,\n\tGPIO4_ANT_SWB_GPIO4_8822C,\n\tGPIO4_BT_RFE_CTRL_0_8822C,\n\tGPIO4_WL_RFE_CTRL_8_8822C,\n\tGPIO4_SW_IO_8822C\n};\n\nstatic const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO5_8822C[] = {\n\tGPIO5_BT_SPI_D1_8822C,\n\tGPIO5_WL_SPI_D1_8822C,\n\tGPIO5_BT_JTAG_TDI_8822C,\n\tGPIO5_WL_JTAG_TDI_8822C,\n\tGPIO5_DBG_GNT_BT_8822C,\n\tGPIO5_BT_GPIO18_8822C,\n\tGPIO5_SOUT_8822C,\n\tGPIO5_WLMAC_DBG_GPIO5_8822C,\n\tGPIO5_WLPHY_DBG_GPIO5_8822C,\n\tGPIO5_BT_DBG_GPIO5_8822C,\n\tGPIO5_I2C_INT_3_WIRE_8822C,\n\tGPIO5_I2C_INT_1_WIRE_8822C,\n\tGPIO5_SW_IO_8822C\n};\n\nstatic const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO6_8822C[] = {\n\tGPIO6_BT_SPI_D2_8822C,\n\tGPIO6_WL_SPI_D2_8822C,\n\tGPIO6_EEDO_8822C,\n\tGPIO6_BT_JTAG_TDO_8822C,\n\tGPIO6_WL_JTAG_TDO_8822C,\n\tGPIO6_BT_3DD_SYNC_B_8822C,\n\tGPIO6_SIN_8822C,\n\tGPIO6_WLMAC_DBG_GPIO6_8822C,\n\tGPIO6_WLPHY_DBG_GPIO6_8822C,\n\tGPIO6_BT_DBG_GPIO6_8822C,\n\tGPIO6_SW_PAPE_SEL_8822C,\n\tGPIO6_BT_RFE_CTRL_3_8822C,\n\tGPIO6_RFE_CTRL_1_8822C,\n\tGPIO6_EXT_SWR_CTRL_8822C,\n\tGPIO6_SW_IO_8822C\n};\n\nstatic const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO7_8822C[] = {\n\tGPIO7_BT_SPI_D3_8822C,\n\tGPIO7_WL_SPI_D3_8822C,\n\tGPIO7_EEDI_8822C,\n\tGPIO7_BT_JTAG_TMS_8822C,\n\tGPIO7_WL_JTAG_TMS_8822C,\n\tGPIO7_BT_GPIO16_8822C,\n\tGPIO7_SOUT_8822C,\n\tGPIO7_WLMAC_DBG_GPIO7_8822C,\n\tGPIO7_WLPHY_DBG_GPIO7_8822C,\n\tGPIO7_BT_DBG_GPIO7_8822C,\n\tGPIO7_LNAON_SEL_8822C,\n\tGPIO7_BT_RFE_CTRL_4_8822C,\n\tGPIO7_RFE_CTRL_2_8822C,\n\tGPIO7_SW_IO_8822C\n};\n\nstatic const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO8_8822C[] = {\n\tGPIO8_WL_EXT_WOL_8822C,\n\tGPIO8_WL_LED_8822C,\n\tGPIO8_SOUT_8822C,\n\tGPIO8_SW_IO_8822C\n};\n\nstatic const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO9_8822C[] = {\n\tGPIO9_DIS_WL_N_8822C,\n\tGPIO9_WL_EXT_WOL_8822C,\n\tGPIO9_USIN0_8822C,\n\tGPIO9_I2C_SD_8822C,\n\tGPIO9_LNAON_SEL_8822C,\n\tGPIO9_BT_RFE_CTRL_4_8822C,\n\tGPIO9_RFE_CTRL_2_8822C,\n\tGPIO9_SW_IO_8822C\n};\n\nstatic const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO10_8822C[] = {\n\tGPIO10_WL_SDIO_INT_8822C,\n\tGPIO10_SW_IO_8822C\n};\n\nstatic const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO11_8822C[] = {\n\tGPIO11_DIS_BT_N_8822C,\n\tGPIO11_USOUT0_8822C,\n\tGPIO11_RFE_CTRL_11_4_5_8822C,\n\tGPIO11_RFE_CTRL_11_6_7_8822C,\n\tGPIO11_SW_IO_8822C\n};\n\nstatic const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO12_8822C[] = {\n\tGPIO12_USCTS0_8822C,\n\tGPIO12_I2C_CLK_8822C,\n\tGPIO12_ANT_SW_GPIO12_8822C,\n\tGPIO12_BT_RFE_CTRL_1_8822C,\n\tGPIO12_WL_RFE_CTRL_9_8822C,\n\tGPIO12_SW_IO_8822C\n};\n\nstatic const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO13_8822C[] = {\n\tGPIO13_BT_WAKE_8822C,\n\tGPIO13_BT_ANT_SW_0_8822C,\n\tGPIO13_ANT_SW_GPIO13_8822C,\n\tGPIO13_BT_RFE_CTRL_1_8822C,\n\tGPIO13_WL_RFE_CTRL_9_8822C,\n\tGPIO13_RFE_CTRL_10_4_5_8822C,\n\tGPIO13_RFE_CTRL_10_6_7_8822C,\n\tGPIO13_SW_IO_8822C\n};\n\nstatic const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO14_8822C[] = {\n\tGPIO14_UART_WAKE_8822C,\n\tGPIO14_BT_ANT_SW_1_8822C,\n\tGPIO14_RFE_CTRL_5_4_5_8822C,\n\tGPIO14_RFE_CTRL_5_6_7_8822C,\n\tGPIO14_SW_IO_8822C\n};\n\nstatic const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO15_8822C[] = {\n\tGPIO15_EXT_XTAL_8822C,\n\tGPIO15_SW_IO_8822C\n};\n\nstatic enum halmac_ret_status\nget_pinmux_list_8822c(struct halmac_adapter *adapter,\n\t\t      enum halmac_gpio_func gpio_func,\n\t\t      const struct halmac_gpio_pimux_list **list,\n\t\t      u32 *list_size, u32 *gpio_id);\n\nstatic enum halmac_ret_status\nchk_pinmux_valid_8822c(struct halmac_adapter *adapter,\n\t\t       enum halmac_gpio_func gpio_func);\n\n/**\n * pinmux_get_func_8822c() -get current gpio status\n * @adapter : the adapter of halmac\n * @gpio_func : gpio function\n * @enable : function is enable(1) or disable(0)\n * Author : LIN YONG-CHING\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\npinmux_get_func_8822c(struct halmac_adapter *adapter,\n\t\t      enum halmac_gpio_func gpio_func, u8 *enable)\n{\n\tu32 list_size;\n\tu32 cur_func;\n\tu32 gpio_id;\n\tenum halmac_ret_status status;\n\tconst struct halmac_gpio_pimux_list *list = NULL;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tstatus = get_pinmux_list_8822c(adapter, gpio_func, &list, &list_size,\n\t\t\t\t       &gpio_id);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tstatus = pinmux_parser_88xx(adapter, list, list_size, gpio_id,\n\t\t\t\t    &cur_func);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tswitch (gpio_func) {\n\tcase HALMAC_GPIO_FUNC_WL_LED:\n\t\t*enable = (cur_func == HALMAC_WL_LED) ? 1 : 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SDIO_INT:\n\t\t*enable = (cur_func == HALMAC_SDIO_INT) ? 1 : 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_BT_HOST_WAKE1:\n\tcase HALMAC_GPIO_FUNC_BT_DEV_WAKE1:\n\t\t*enable = (cur_func == HALMAC_GPIO13_14_WL_CTRL_EN) ? 1 : 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_0:\n\tcase HALMAC_GPIO_FUNC_SW_IO_1:\n\tcase HALMAC_GPIO_FUNC_SW_IO_2:\n\tcase HALMAC_GPIO_FUNC_SW_IO_3:\n\tcase HALMAC_GPIO_FUNC_SW_IO_4:\n\tcase HALMAC_GPIO_FUNC_SW_IO_5:\n\tcase HALMAC_GPIO_FUNC_SW_IO_6:\n\tcase HALMAC_GPIO_FUNC_SW_IO_7:\n\tcase HALMAC_GPIO_FUNC_SW_IO_8:\n\tcase HALMAC_GPIO_FUNC_SW_IO_9:\n\tcase HALMAC_GPIO_FUNC_SW_IO_10:\n\tcase HALMAC_GPIO_FUNC_SW_IO_11:\n\tcase HALMAC_GPIO_FUNC_SW_IO_12:\n\tcase HALMAC_GPIO_FUNC_SW_IO_13:\n\tcase HALMAC_GPIO_FUNC_SW_IO_14:\n\tcase HALMAC_GPIO_FUNC_SW_IO_15:\n\t\t*enable = (cur_func == HALMAC_SW_IO) ? 1 : 0;\n\t\tbreak;\n\tdefault:\n\t\t*enable = 0;\n\t\treturn HALMAC_RET_GET_PINMUX_ERR;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * pinmux_set_func_8822c() -set gpio function\n * @adapter : the adapter of halmac\n * @gpio_func : gpio function\n * Author : LIN YONG-CHING\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\npinmux_set_func_8822c(struct halmac_adapter *adapter,\n\t\t      enum halmac_gpio_func gpio_func)\n{\n\tu32 list_size;\n\tu32 gpio_id;\n\tenum halmac_ret_status status;\n\tconst struct halmac_gpio_pimux_list *list = NULL;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\tPLTFM_MSG_TRACE(\"[TRACE]func name : %d\\n\", gpio_func);\n\n\tstatus = chk_pinmux_valid_8822c(adapter, gpio_func);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tstatus = get_pinmux_list_8822c(adapter, gpio_func, &list, &list_size,\n\t\t\t\t       &gpio_id);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tstatus = pinmux_switch_88xx(adapter, list, list_size, gpio_id,\n\t\t\t\t    gpio_func);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tstatus = pinmux_record_88xx(adapter, gpio_func, 1);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * pinmux_free_func_8822c() -free locked gpio function\n * @adapter : the adapter of halmac\n * @gpio_func : gpio function\n * Author : LIN YONG-CHING\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\npinmux_free_func_8822c(struct halmac_adapter *adapter,\n\t\t       enum halmac_gpio_func gpio_func)\n{\n\tstruct halmac_pinmux_info *info = &adapter->pinmux_info;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tswitch (gpio_func) {\n\tcase HALMAC_GPIO_FUNC_SW_IO_0:\n\t\tinfo->sw_io_0 = 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_1:\n\t\tinfo->sw_io_1 = 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_2:\n\t\tinfo->sw_io_2 = 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_3:\n\t\tinfo->sw_io_3 = 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_4:\n\t\tinfo->sw_io_4 = 0;\n\t\tinfo->sdio_int = 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_5:\n\t\tinfo->sw_io_5 = 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_6:\n\t\tinfo->sw_io_6 = 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_7:\n\t\tinfo->sw_io_7 = 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_8:\n\tcase HALMAC_GPIO_FUNC_WL_LED:\n\t\tinfo->sw_io_8 = 0;\n\t\tinfo->wl_led = 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_9:\n\t\tinfo->sw_io_9 = 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_10:\n\tcase HALMAC_GPIO_FUNC_SDIO_INT:\n\t\tinfo->sw_io_10 = 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_11:\n\t\tinfo->sw_io_11 = 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_12:\n\t\tinfo->sw_io_12 = 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_13:\n\tcase HALMAC_GPIO_FUNC_BT_DEV_WAKE1:\n\t\tinfo->bt_dev_wake = 0;\n\t\tinfo->sw_io_13 = 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_14:\n\tcase HALMAC_GPIO_FUNC_BT_HOST_WAKE1:\n\t\tinfo->bt_host_wake = 0;\n\t\tinfo->sw_io_14 = 0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_15:\n\t\tinfo->sw_io_15 = 0;\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_SWITCH_CASE_ERROR;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]func : %X\\n\", gpio_func);\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nget_pinmux_list_8822c(struct halmac_adapter *adapter,\n\t\t      enum halmac_gpio_func gpio_func,\n\t\t      const struct halmac_gpio_pimux_list **list,\n\t\t      u32 *list_size, u32 *gpio_id)\n{\n\tswitch (gpio_func) {\n\tcase HALMAC_GPIO_FUNC_SW_IO_0:\n\t\t*list = PINMUX_LIST_GPIO0_8822C;\n\t\t*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO0_8822C);\n\t\t*gpio_id = HALMAC_GPIO0;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_1:\n\t\t*list = PINMUX_LIST_GPIO1_8822C;\n\t\t*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO1_8822C);\n\t\t*gpio_id = HALMAC_GPIO1;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_2:\n\t\t*list = PINMUX_LIST_GPIO2_8822C;\n\t\t*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO2_8822C);\n\t\t*gpio_id = HALMAC_GPIO2;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_3:\n\t\t*list = PINMUX_LIST_GPIO3_8822C;\n\t\t*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO3_8822C);\n\t\t*gpio_id = HALMAC_GPIO3;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_4:\n\t\t*list = PINMUX_LIST_GPIO4_8822C;\n\t\t*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO4_8822C);\n\t\t*gpio_id = HALMAC_GPIO4;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_5:\n\t\t*list = PINMUX_LIST_GPIO5_8822C;\n\t\t*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO5_8822C);\n\t\t*gpio_id = HALMAC_GPIO5;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_6:\n\t\t*list = PINMUX_LIST_GPIO6_8822C;\n\t\t*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO6_8822C);\n\t\t*gpio_id = HALMAC_GPIO6;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_7:\n\t\t*list = PINMUX_LIST_GPIO7_8822C;\n\t\t*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO7_8822C);\n\t\t*gpio_id = HALMAC_GPIO7;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_8:\n\tcase HALMAC_GPIO_FUNC_WL_LED:\n\t\t*list = PINMUX_LIST_GPIO8_8822C;\n\t\t*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO8_8822C);\n\t\t*gpio_id = HALMAC_GPIO8;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_9:\n\t\t*list = PINMUX_LIST_GPIO9_8822C;\n\t\t*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO9_8822C);\n\t\t*gpio_id = HALMAC_GPIO9;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_10:\n\tcase HALMAC_GPIO_FUNC_SDIO_INT:\n\t\t*list = PINMUX_LIST_GPIO10_8822C;\n\t\t*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO10_8822C);\n\t\t*gpio_id = HALMAC_GPIO10;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_11:\n\t\t*list = PINMUX_LIST_GPIO11_8822C;\n\t\t*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO11_8822C);\n\t\t*gpio_id = HALMAC_GPIO11;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_12:\n\t\t*list = PINMUX_LIST_GPIO12_8822C;\n\t\t*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO12_8822C);\n\t\t*gpio_id = HALMAC_GPIO12;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_13:\n\tcase HALMAC_GPIO_FUNC_BT_DEV_WAKE1:\n\t\t*list = PINMUX_LIST_GPIO13_8822C;\n\t\t*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO13_8822C);\n\t\t*gpio_id = HALMAC_GPIO13;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_14:\n\tcase HALMAC_GPIO_FUNC_BT_HOST_WAKE1:\n\t\t*list = PINMUX_LIST_GPIO14_8822C;\n\t\t*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO14_8822C);\n\t\t*gpio_id = HALMAC_GPIO14;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_15:\n\t\t*list = PINMUX_LIST_GPIO15_8822C;\n\t\t*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO15_8822C);\n\t\t*gpio_id = HALMAC_GPIO15;\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_SWITCH_CASE_ERROR;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nchk_pinmux_valid_8822c(struct halmac_adapter *adapter,\n\t\t       enum halmac_gpio_func gpio_func)\n{\n\tstruct halmac_pinmux_info *info = &adapter->pinmux_info;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tswitch (gpio_func) {\n\tcase HALMAC_GPIO_FUNC_SW_IO_0:\n\t\tif (info->sw_io_0 == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_1:\n\t\tif (info->sw_io_1 == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_2:\n\t\tif (info->sw_io_2 == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_3:\n\t\tif (info->sw_io_3 == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_4:\n\t\tif (info->sw_io_4 == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_5:\n\t\tif (info->sw_io_5 == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_6:\n\t\tif (info->sw_io_6 == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_7:\n\t\tif (info->sw_io_7 == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_8:\n\t\tif (info->sw_io_8 == 1 || info->wl_led == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_WL_LED:\n\t\tif (info->sw_io_8 == 1 || info->wl_led == 1 ||\n\t\t    info->bt_dev_wake == 1 || info->bt_host_wake == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_9:\n\t\tif (info->sw_io_9 == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_10:\n\tcase HALMAC_GPIO_FUNC_SDIO_INT:\n\t\tif (info->sw_io_10 == 1 || info->sdio_int == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_11:\n\t\tif (info->sw_io_11 == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_12:\n\t\tif (info->sw_io_12 == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_13:\n\t\tif (info->sw_io_13 == 1 || info->bt_dev_wake == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_BT_DEV_WAKE1:\n\t\tif (info->sw_io_13 == 1 || info->bt_dev_wake == 1 ||\n\t\t    info->wl_led == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_14:\n\t\tif (info->sw_io_14 == 1 || info->bt_host_wake == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_BT_HOST_WAKE1:\n\t\tif (info->sw_io_14 == 1 || info->bt_host_wake == 1 ||\n\t\t    info->wl_led == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_15:\n\t\tif (info->sw_io_15 == 1)\n\t\t\tstatus = HALMAC_RET_PINMUX_USED;\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_SWITCH_CASE_ERROR;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]chk_pinmux_valid func : %X status : %X\\n\",\n\t\t\tgpio_func, status);\n\n\treturn status;\n}\n\n#endif /* HALMAC_8822C_SUPPORT */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_8822c/halmac_gpio_8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_GPIO_8822C_H_\n#define _HALMAC_GPIO_8822C_H_\n\n#include \"../../halmac_api.h\"\n#include \"../../halmac_gpio_cmd.h\"\n\n#if HALMAC_8822C_SUPPORT\n\nenum halmac_ret_status\npinmux_get_func_8822c(struct halmac_adapter *adapter,\n\t\t      enum halmac_gpio_func gpio_func, u8 *enable);\n\nenum halmac_ret_status\npinmux_set_func_8822c(struct halmac_adapter *adapter,\n\t\t      enum halmac_gpio_func gpio_func);\n\nenum halmac_ret_status\npinmux_free_func_8822c(struct halmac_adapter *adapter,\n\t\t       enum halmac_gpio_func gpio_func);\n\n#endif /* HALMAC_8822C_SUPPORT */\n\n#endif/* _HALMAC_GPIO_8822C_H_ */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_8822c/halmac_init_8822c.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"halmac_init_8822c.h\"\n#include \"halmac_8822c_cfg.h\"\n#if HALMAC_PCIE_SUPPORT\n#include \"halmac_pcie_8822c.h\"\n#endif\n#if HALMAC_SDIO_SUPPORT\n#include \"halmac_sdio_8822c.h\"\n#include \"../halmac_sdio_88xx.h\"\n#endif\n#if HALMAC_USB_SUPPORT\n#include \"halmac_usb_8822c.h\"\n#endif\n#include \"halmac_gpio_8822c.h\"\n#include \"halmac_common_8822c.h\"\n#include \"halmac_cfg_wmac_8822c.h\"\n#include \"../halmac_common_88xx.h\"\n#include \"../halmac_init_88xx.h\"\n#include \"../halmac_cfg_wmac_88xx.h\"\n\n#if HALMAC_8822C_SUPPORT\n\n#define SYS_FUNC_EN\t\t0xD8\n\n#define RSVD_PG_DRV_NUM\t\t\t16\n#define RSVD_PG_H2C_EXTRAINFO_NUM\t24\n#define RSVD_PG_H2C_STATICINFO_NUM\t8\n#define RSVD_PG_H2CQ_NUM\t\t8\n#define RSVD_PG_CPU_INSTRUCTION_NUM\t0\n#define RSVD_PG_FW_TXBUF_NUM\t\t4\n#define RSVD_PG_CSIBUF_NUM\t\t50\n#define RSVD_PG_DLLB_NUM\t\t(TX_FIFO_SIZE_8822C / 3 >> \\\n\t\t\t\t\tTX_PAGE_SIZE_SHIFT_88XX)\n\n#define MAC_TRX_ENABLE\t(BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \\\n\t\t\tBIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \\\n\t\t\tBIT_MACTXEN | BIT_MACRXEN)\n\n#define WLAN_TXQ_RPT_EN\t\t0x1F\n\n#define BLK_DESC_NUM\t0x3\n#define RX_DLK_TIME\t0x14\n\n#define WLAN_SLOT_TIME\t\t0x09\n#define WLAN_PIFS_TIME\t\t0x1C\n#define WLAN_SIFS_CCK_CONT_TX\t0x0A\n#define WLAN_SIFS_OFDM_CONT_TX\t0x0E\n#define WLAN_SIFS_CCK_TRX\t0x0A\n#define WLAN_SIFS_OFDM_TRX\t0x10\n#define WLAN_NAV_MAX\t\t0xC8\n#define WLAN_RDG_NAV\t\t0x05\n#define WLAN_TXOP_NAV\t\t0x1B\n#define WLAN_CCK_RX_TSF\t\t0x30\n#define WLAN_OFDM_RX_TSF\t0x30\n#define WLAN_TBTT_PROHIBIT\t0x04 /* unit : 32us */\n#define WLAN_TBTT_HOLD_TIME\t0x064 /* unit : 32us */\n#define WLAN_DRV_EARLY_INT\t0x04\n#define WLAN_BCN_CTRL_CLT0\t0x10\n#define WLAN_BCN_DMA_TIME\t0x02\n#define WLAN_BCN_MAX_ERR\t0xFF\n#define WLAN_SIFS_CCK_DUR_TUNE\t0x0A\n#define WLAN_SIFS_OFDM_DUR_TUNE\t0x10\n#define WLAN_SIFS_CCK_CTX\t0x0A\n#define WLAN_SIFS_CCK_IRX\t0x0A\n#define WLAN_SIFS_OFDM_CTX\t0x0E\n#define WLAN_SIFS_OFDM_IRX\t0x0E\n#define WLAN_EIFS_DUR_TUNE\t0x40\n#define WLAN_EDCA_VO_PARAM\t0x002FA226\n#define WLAN_EDCA_VI_PARAM\t0x005EA328\n#define WLAN_EDCA_BE_PARAM\t0x005EA42B\n#define WLAN_EDCA_BK_PARAM\t0x0000A44F\n\n#define WLAN_RX_FILTER0\t\t0xFFFFFFFF\n#define WLAN_RX_FILTER2\t\t0xFFFF\n#define WLAN_RCR_CFG\t\t0xE410220E\n#define WLAN_RXPKT_MAX_SZ\t12288\n#define WLAN_RXPKT_MAX_SZ_512\t(WLAN_RXPKT_MAX_SZ >> 9)\n\n#define WLAN_AMPDU_MAX_TIME\t\t0x70\n#define WLAN_RTS_LEN_TH\t\t\t0xFF\n#define WLAN_RTS_TX_TIME_TH\t\t0x08\n#define WLAN_MAX_AGG_PKT_LIMIT\t\t0x3F\n#define WLAN_RTS_MAX_AGG_PKT_LIMIT\t0x20\n#define WLAN_PRE_TXCNT_TIME_TH\t\t0x1E4\n#define WALN_FAST_EDCA_VO_TH\t\t0x06\n#define WLAN_FAST_EDCA_VI_TH\t\t0x06\n#define WLAN_FAST_EDCA_BE_TH\t\t0x06\n#define WLAN_FAST_EDCA_BK_TH\t\t0x06\n#define WLAN_BAR_RETRY_LIMIT\t\t0x01\n#define WLAN_BAR_ACK_TYPE\t\t0x05\n#define WLAN_RA_TRY_RATE_AGG_LIMIT\t0x08\n#define WLAN_RESP_TXRATE\t\t0x84\n#define WLAN_ACK_TO\t\t\t0x21\n#define WLAN_ACK_TO_CCK\t\t\t0x6A\n#define WLAN_DATA_RATE_FB_CNT_1_4\t0x01000000\n#define WLAN_DATA_RATE_FB_CNT_5_8\t0x08070504\n#define WLAN_RTS_RATE_FB_CNT_5_8\t0x08070504\n#define WLAN_DATA_RATE_FB_RATE0\t\t0xFE01F010\n#define WLAN_DATA_RATE_FB_RATE0_H\t0x40000000\n#define WLAN_RTS_RATE_FB_RATE1\t\t0x003FF010\n#define WLAN_RTS_RATE_FB_RATE1_H\t0x40000000\n#define WLAN_RTS_RATE_FB_RATE4\t\t0x0600F010\n#define WLAN_RTS_RATE_FB_RATE4_H\t0x400003E0\n#define WLAN_RTS_RATE_FB_RATE5\t\t0x0600F015\n#define WLAN_RTS_RATE_FB_RATE5_H\t0x000000E0\n\n#define WLAN_TX_FUNC_CFG1\t\t0x30\n#define WLAN_TX_FUNC_CFG2\t\t0x30\n#define WLAN_MAC_OPT_NORM_FUNC1\t\t0x98\n#define WLAN_MAC_OPT_LB_FUNC1\t\t0x80\n#define WLAN_MAC_OPT_FUNC2\t\t0xB1810041\n\n#define WLAN_SIFS_CFG\t(WLAN_SIFS_CCK_CONT_TX | \\\n\t\t\t(WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \\\n\t\t\t(WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \\\n\t\t\t(WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))\n\n#define WLAN_SIFS_DUR_TUNE\t(WLAN_SIFS_CCK_DUR_TUNE | \\\n\t\t\t\t(WLAN_SIFS_OFDM_DUR_TUNE << 8))\n\n#define WLAN_TBTT_TIME\t(WLAN_TBTT_PROHIBIT |\\\n\t\t\t(WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))\n\n#define WLAN_NAV_CFG\t\t(WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))\n#define WLAN_RX_TSF_CFG\t\t(WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)\n\n#if HALMAC_PLATFORM_WINDOWS\n/*SDIO RQPN Mapping for Windows, extra queue is not implemented in Driver code*/\nstatic struct halmac_rqpn HALMAC_RQPN_SDIO_8822C[] = {\n\t/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */\n\t{HALMAC_TRX_MODE_NORMAL,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_TRXSHARE,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_WMM,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_P2P,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_LOOPBACK,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_DELAY_LOOPBACK,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},\n};\n#else\n/*SDIO RQPN Mapping*/\nstatic struct halmac_rqpn HALMAC_RQPN_SDIO_8822C[] = {\n\t/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */\n\t{HALMAC_TRX_MODE_NORMAL,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_TRXSHARE,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_WMM,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_P2P,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_LOOPBACK,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_DELAY_LOOPBACK,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n};\n#endif\n\n/*PCIE RQPN Mapping*/\nstatic struct halmac_rqpn HALMAC_RQPN_PCIE_8822C[] = {\n\t/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */\n\t{HALMAC_TRX_MODE_NORMAL,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_TRXSHARE,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_WMM,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_P2P,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_LOOPBACK,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_DELAY_LOOPBACK,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n};\n\n/*USB 2 Bulkout RQPN Mapping*/\nstatic struct halmac_rqpn HALMAC_RQPN_2BULKOUT_8822C[] = {\n\t/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */\n\t{HALMAC_TRX_MODE_NORMAL,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_TRXSHARE,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_WMM,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_P2P,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_LOOPBACK,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_DELAY_LOOPBACK,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},\n};\n\n/*USB 3 Bulkout RQPN Mapping*/\nstatic struct halmac_rqpn HALMAC_RQPN_3BULKOUT_8822C[] = {\n\t/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */\n\t{HALMAC_TRX_MODE_NORMAL,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_TRXSHARE,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_WMM,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_P2P,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_LOOPBACK,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_DELAY_LOOPBACK,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},\n};\n\n/*USB 4 Bulkout RQPN Mapping*/\nstatic struct halmac_rqpn HALMAC_RQPN_4BULKOUT_8822C[] = {\n\t/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */\n\t{HALMAC_TRX_MODE_NORMAL,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_TRXSHARE,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_WMM,\n\t HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_P2P,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_LOOPBACK,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n\t{HALMAC_TRX_MODE_DELAY_LOOPBACK,\n\t HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,\n\t HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},\n};\n\n#if HALMAC_PLATFORM_WINDOWS\n/*SDIO Page Number*/\nstatic struct halmac_pg_num HALMAC_PG_NUM_SDIO_8822C[] = {\n\t/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */\n\t{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1},\n\t{HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 0, 1},\n\t{HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1},\n\t{HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1},\n\t{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 1},\n\t{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 1},\n};\n#else\n/*SDIO Page Number*/\nstatic struct halmac_pg_num HALMAC_PG_NUM_SDIO_8822C[] = {\n\t/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */\n\t{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},\n\t{HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 32, 1},\n\t{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},\n\t{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},\n\t{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 1},\n\t{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 1},\n};\n#endif\n\n/*PCIE Page Number*/\nstatic struct halmac_pg_num HALMAC_PG_NUM_PCIE_8822C[] = {\n\t/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */\n\t{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},\n\t{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1},\n\t{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},\n\t{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},\n\t{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 1},\n\t{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 1},\n};\n\n/*USB 2 Bulkout Page Number*/\nstatic struct halmac_pg_num HALMAC_PG_NUM_2BULKOUT_8822C[] = {\n\t/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */\n\t{HALMAC_TRX_MODE_NORMAL, 64, 64, 0, 0, 1},\n\t{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 0, 0, 1},\n\t{HALMAC_TRX_MODE_WMM, 64, 64, 0, 0, 1},\n\t{HALMAC_TRX_MODE_P2P, 64, 64, 0, 0, 1},\n\t{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 0, 0, 1},\n\t{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 0, 0, 1},\n};\n\n/*USB 3 Bulkout Page Number*/\nstatic struct halmac_pg_num HALMAC_PG_NUM_3BULKOUT_8822C[] = {\n\t/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */\n\t{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1},\n\t{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 0, 1},\n\t{HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1},\n\t{HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1},\n\t{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 1},\n\t{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 1},\n};\n\n/*USB 4 Bulkout Page Number*/\nstatic struct halmac_pg_num HALMAC_PG_NUM_4BULKOUT_8822C[] = {\n\t/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */\n\t{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},\n\t{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1},\n\t{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},\n\t{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},\n\t{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 1},\n\t{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 1},\n};\n\nstatic enum halmac_ret_status\ntxdma_queue_mapping_8822c(struct halmac_adapter *adapter,\n\t\t\t  enum halmac_trx_mode mode);\n\nstatic enum halmac_ret_status\npriority_queue_cfg_8822c(struct halmac_adapter *adapter,\n\t\t\t enum halmac_trx_mode mode);\n\nstatic enum halmac_ret_status\nset_trx_fifo_info_8822c(struct halmac_adapter *adapter,\n\t\t\tenum halmac_trx_mode mode);\n\nstatic void\ninit_txq_ctrl_8822c(struct halmac_adapter *adapter);\n\nstatic void\ninit_sifs_ctrl_8822c(struct halmac_adapter *adapter);\n\nstatic void\ninit_rate_fallback_ctrl_8822c(struct halmac_adapter *adapter);\n\nstatic enum halmac_ret_status\ninit_xtal_aac(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\nmount_api_8822c(struct halmac_adapter *adapter)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tadapter->chip_id = HALMAC_CHIP_ID_8822C;\n\tadapter->hw_cfg_info.efuse_size = EFUSE_SIZE_8822C;\n\tadapter->hw_cfg_info.eeprom_size = EEPROM_SIZE_8822C;\n\tadapter->hw_cfg_info.bt_efuse_size = BT_EFUSE_SIZE_8822C;\n\tadapter->hw_cfg_info.prtct_efuse_size = PRTCT_EFUSE_SIZE_8822C;\n\tadapter->hw_cfg_info.cam_entry_num = SEC_CAM_NUM_8822C;\n\tadapter->hw_cfg_info.tx_fifo_size = TX_FIFO_SIZE_8822C;\n\tadapter->hw_cfg_info.rx_fifo_size = RX_FIFO_SIZE_8822C;\n\tadapter->hw_cfg_info.ac_oqt_size = OQT_ENTRY_AC_8822C;\n\tadapter->hw_cfg_info.non_ac_oqt_size = OQT_ENTRY_NOAC_8822C;\n\tadapter->hw_cfg_info.usb_txagg_num = BLK_DESC_NUM;\n\tadapter->txff_alloc.rsvd_drv_pg_num = RSVD_PG_DRV_NUM;\n\n\tapi->halmac_init_trx_cfg = init_trx_cfg_8822c;\n\tapi->halmac_init_system_cfg = init_system_cfg_8822c;\n\tapi->halmac_init_protocol_cfg = init_protocol_cfg_8822c;\n\tapi->halmac_init_h2c = init_h2c_8822c;\n\tapi->halmac_pinmux_get_func = pinmux_get_func_8822c;\n\tapi->halmac_pinmux_set_func = pinmux_set_func_8822c;\n\tapi->halmac_pinmux_free_func = pinmux_free_func_8822c;\n\tapi->halmac_get_hw_value = get_hw_value_8822c;\n\tapi->halmac_set_hw_value = set_hw_value_8822c;\n\tapi->halmac_cfg_drv_info = cfg_drv_info_8822c;\n\tapi->halmac_fill_txdesc_checksum = fill_txdesc_check_sum_8822c;\n\tapi->halmac_init_low_pwr = init_low_pwr_8822c;\n\tapi->halmac_pre_init_system_cfg = pre_init_system_cfg_8822c;\n\n\tapi->halmac_init_wmac_cfg = init_wmac_cfg_8822c;\n\tapi->halmac_init_edca_cfg = init_edca_cfg_8822c;\n\n\tif (adapter->intf == HALMAC_INTERFACE_SDIO) {\n#if HALMAC_SDIO_SUPPORT\n\t\tadapter->sdio_hw_info.tx_addr_format = HALMAC_SDIO_AGG_MODE;\n\n\t\tapi->halmac_mac_power_switch = mac_pwr_switch_sdio_8822c;\n\t\tapi->halmac_phy_cfg = phy_cfg_sdio_8822c;\n\t\tapi->halmac_pcie_switch = pcie_switch_sdio_8822c;\n\t\tapi->halmac_interface_integration_tuning = intf_tun_sdio_8822c;\n\t\tapi->halmac_tx_allowed_sdio = tx_allowed_sdio_8822c;\n\t\tapi->halmac_get_sdio_tx_addr = get_sdio_tx_addr_8822c;\n\t\tapi->halmac_reg_read_8 = reg_r8_sdio_8822c;\n\t\tapi->halmac_reg_write_8 = reg_w8_sdio_8822c;\n\t\tapi->halmac_reg_read_16 = reg_r16_sdio_8822c;\n\t\tapi->halmac_reg_write_16 = reg_w16_sdio_8822c;\n\t\tapi->halmac_reg_read_32 = reg_r32_sdio_8822c;\n\t\tapi->halmac_reg_write_32 = reg_w32_sdio_8822c;\n\n\t\tadapter->sdio_fs.macid_map_size = MACID_MAX_8822C << 1;\n\t\tif (!adapter->sdio_fs.macid_map) {\n\t\t\tadapter->sdio_fs.macid_map =\n\t\t\t(u8 *)PLTFM_MALLOC(adapter->sdio_fs.macid_map_size);\n\t\t\tif (!adapter->sdio_fs.macid_map)\n\t\t\t\tPLTFM_MSG_ERR(\"[ERR]mac id map malloc!!\\n\");\n\t\t}\n#endif\n\t} else if (adapter->intf == HALMAC_INTERFACE_USB) {\n#if HALMAC_USB_SUPPORT\n\t\tapi->halmac_mac_power_switch = mac_pwr_switch_usb_8822c;\n\t\tapi->halmac_phy_cfg = phy_cfg_usb_8822c;\n\t\tapi->halmac_pcie_switch = pcie_switch_usb_8822c;\n\t\tapi->halmac_interface_integration_tuning = intf_tun_usb_8822c;\n#endif\n\t} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {\n#if HALMAC_PCIE_SUPPORT\n\t\tapi->halmac_mac_power_switch = mac_pwr_switch_pcie_8822c;\n\t\tapi->halmac_phy_cfg = phy_cfg_pcie_8822c;\n\t\tapi->halmac_pcie_switch = pcie_switch_8822c;\n\t\tapi->halmac_interface_integration_tuning = intf_tun_pcie_8822c;\n\t\tapi->halmac_cfgspc_set_pcie = cfgspc_set_pcie_8822c;\n#endif\n\t} else {\n\t\tPLTFM_MSG_ERR(\"[ERR]Undefined IC\\n\");\n\t\treturn HALMAC_RET_CHIP_NOT_SUPPORT;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * init_trx_cfg_8822c() - config trx dma register\n * @adapter : the adapter of halmac\n * @mode : trx mode selection\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ninit_trx_cfg_8822c(struct halmac_adapter *adapter, enum halmac_trx_mode mode)\n{\n\tu8 value8;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tu8 en_fwff;\n\tu16 value16;\n\n\tadapter->trx_mode = mode;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tstatus = txdma_queue_mapping_8822c(adapter, mode);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]queue mapping\\n\");\n\t\treturn status;\n\t}\n\n\ten_fwff = HALMAC_REG_R8(REG_WMAC_FWPKT_CR) & BIT_FWEN;\n\tif (en_fwff) {\n\t\tHALMAC_REG_W8_CLR(REG_WMAC_FWPKT_CR, BIT_FWEN);\n\t\tif (fwff_is_empty_88xx(adapter) != HALMAC_RET_SUCCESS)\n\t\t\tPLTFM_MSG_ERR(\"[ERR]fwff is not empty\\n\");\n\t}\n\tvalue8 = 0;\n\tHALMAC_REG_W8(REG_CR, value8);\n\tvalue16 = HALMAC_REG_R16(REG_FWFF_PKT_INFO);\n\tHALMAC_REG_W16(REG_FWFF_CTRL, value16);\n\n\tvalue8 = MAC_TRX_ENABLE;\n\tHALMAC_REG_W8(REG_CR, value8);\n\tif (en_fwff)\n\t\tHALMAC_REG_W8_SET(REG_WMAC_FWPKT_CR, BIT_FWEN);\n\tHALMAC_REG_W32(REG_H2CQ_CSR, BIT(31));\n\n\tstatus = priority_queue_cfg_8822c(adapter, mode);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]priority queue cfg\\n\");\n\t\treturn status;\n\t}\n\n\tstatus = init_h2c_8822c(adapter);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]init h2cq!\\n\");\n\t\treturn status;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\ntxdma_queue_mapping_8822c(struct halmac_adapter *adapter,\n\t\t\t  enum halmac_trx_mode mode)\n{\n\tu16 value16;\n\tstruct halmac_rqpn *cur_rqpn_sel = NULL;\n\tenum halmac_ret_status status;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tif (adapter->intf == HALMAC_INTERFACE_SDIO) {\n\t\tcur_rqpn_sel = HALMAC_RQPN_SDIO_8822C;\n\t} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {\n\t\tcur_rqpn_sel = HALMAC_RQPN_PCIE_8822C;\n\t} else if (adapter->intf == HALMAC_INTERFACE_USB) {\n\t\tif (adapter->bulkout_num == 2) {\n\t\t\tcur_rqpn_sel = HALMAC_RQPN_2BULKOUT_8822C;\n\t\t} else if (adapter->bulkout_num == 3) {\n\t\t\tcur_rqpn_sel = HALMAC_RQPN_3BULKOUT_8822C;\n\t\t} else if (adapter->bulkout_num == 4) {\n\t\t\tcur_rqpn_sel = HALMAC_RQPN_4BULKOUT_8822C;\n\t\t} else {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]interface not support\\n\");\n\t\t\treturn HALMAC_RET_NOT_SUPPORT;\n\t\t}\n\t} else {\n\t\treturn HALMAC_RET_NOT_SUPPORT;\n\t}\n\n\tstatus = rqpn_parser_88xx(adapter, mode, cur_rqpn_sel);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tvalue16 = 0;\n\tvalue16 |= BIT_TXDMA_HIQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_HI]);\n\tvalue16 |= BIT_TXDMA_MGQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_MG]);\n\tvalue16 |= BIT_TXDMA_BKQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_BK]);\n\tvalue16 |= BIT_TXDMA_BEQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_BE]);\n\tvalue16 |= BIT_TXDMA_VIQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_VI]);\n\tvalue16 |= BIT_TXDMA_VOQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_VO]);\n\tHALMAC_REG_W16(REG_TXDMA_PQ_MAP, value16);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\npriority_queue_cfg_8822c(struct halmac_adapter *adapter,\n\t\t\t enum halmac_trx_mode mode)\n{\n\tu8 transfer_mode = 0;\n\tu8 value8;\n\tu32 cnt;\n\tstruct halmac_txff_allocation *txff_info = &adapter->txff_alloc;\n\tenum halmac_ret_status status;\n\tstruct halmac_pg_num *cur_pg_num = NULL;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tstatus = set_trx_fifo_info_8822c(adapter, mode);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]set trx fifo!!\\n\");\n\t\treturn status;\n\t}\n\n\tif (adapter->intf == HALMAC_INTERFACE_SDIO) {\n\t\tcur_pg_num = HALMAC_PG_NUM_SDIO_8822C;\n\t} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {\n\t\tcur_pg_num = HALMAC_PG_NUM_PCIE_8822C;\n\t} else if (adapter->intf == HALMAC_INTERFACE_USB) {\n\t\tif (adapter->bulkout_num == 2) {\n\t\t\tcur_pg_num = HALMAC_PG_NUM_2BULKOUT_8822C;\n\t\t} else if (adapter->bulkout_num == 3) {\n\t\t\tcur_pg_num = HALMAC_PG_NUM_3BULKOUT_8822C;\n\t\t} else if (adapter->bulkout_num == 4) {\n\t\t\tcur_pg_num = HALMAC_PG_NUM_4BULKOUT_8822C;\n\t\t} else {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]interface not support\\n\");\n\t\t\treturn HALMAC_RET_NOT_SUPPORT;\n\t\t}\n\t} else {\n\t\treturn HALMAC_RET_NOT_SUPPORT;\n\t}\n\n\tstatus = pg_num_parser_88xx(adapter, mode, cur_pg_num);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]Set FIFO page\\n\");\n\n\tHALMAC_REG_W16(REG_FIFOPAGE_INFO_1, txff_info->high_queue_pg_num);\n\tHALMAC_REG_W16(REG_FIFOPAGE_INFO_2, txff_info->low_queue_pg_num);\n\tHALMAC_REG_W16(REG_FIFOPAGE_INFO_3, txff_info->normal_queue_pg_num);\n\tHALMAC_REG_W16(REG_FIFOPAGE_INFO_4, txff_info->extra_queue_pg_num);\n\tHALMAC_REG_W16(REG_FIFOPAGE_INFO_5, txff_info->pub_queue_pg_num);\n\tHALMAC_REG_W32_SET(REG_RQPN_CTRL_2, BIT(31));\n\n\tadapter->sdio_fs.hiq_pg_num = txff_info->high_queue_pg_num;\n\tadapter->sdio_fs.miq_pg_num = txff_info->normal_queue_pg_num;\n\tadapter->sdio_fs.lowq_pg_num = txff_info->low_queue_pg_num;\n\tadapter->sdio_fs.pubq_pg_num = txff_info->pub_queue_pg_num;\n\tadapter->sdio_fs.exq_pg_num = txff_info->extra_queue_pg_num;\n\n\tHALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, txff_info->rsvd_boundary);\n\tHALMAC_REG_W16(REG_WMAC_CSIDMA_CFG, txff_info->rsvd_csibuf_addr);\n\tHALMAC_REG_W8_SET(REG_FWHW_TXQ_CTRL + 2, BIT(4));\n\n\t/*20170411 Soar*/\n\t/* SDIO sometimes use two CMD52 to do HALMAC_REG_W16 */\n\t/* and may cause a mismatch between HW status and Reg value. */\n\t/* A patch is to write high byte first, suggested by Argis */\n\tif (adapter->intf == HALMAC_INTERFACE_SDIO) {\n\t\tvalue8 = (u8)(txff_info->rsvd_boundary >> 8 & 0xFF);\n\t\tHALMAC_REG_W8(REG_BCNQ_BDNY_V1 + 1, value8);\n\t\tvalue8 = (u8)(txff_info->rsvd_boundary & 0xFF);\n\t\tHALMAC_REG_W8(REG_BCNQ_BDNY_V1, value8);\n\t} else {\n\t\tHALMAC_REG_W16(REG_BCNQ_BDNY_V1, txff_info->rsvd_boundary);\n\t}\n\n\tHALMAC_REG_W16(REG_FIFOPAGE_CTRL_2 + 2, txff_info->rsvd_boundary);\n\n\t/*20170411 Soar*/\n\t/* SDIO sometimes use two CMD52 to do HALMAC_REG_W16 */\n\t/* and may cause a mismatch between HW status and Reg value. */\n\tif (adapter->intf == HALMAC_INTERFACE_SDIO) {\n\t\tvalue8 = (u8)(txff_info->rsvd_boundary >> 8 & 0xFF);\n\t\tHALMAC_REG_W8(REG_BCNQ1_BDNY_V1 + 1, value8);\n\t\tvalue8 = (u8)(txff_info->rsvd_boundary & 0xFF);\n\t\tHALMAC_REG_W8(REG_BCNQ1_BDNY_V1, value8);\n\t} else {\n\t\tHALMAC_REG_W16(REG_BCNQ1_BDNY_V1, txff_info->rsvd_boundary);\n\t}\n\n\tHALMAC_REG_W32(REG_RXFF_BNDY,\n\t\t       adapter->hw_cfg_info.rx_fifo_size -\n\t\t       C2H_PKT_BUF_88XX - 1);\n\n\tif (adapter->intf == HALMAC_INTERFACE_USB) {\n\t\tvalue8 = HALMAC_REG_R8(REG_AUTO_LLT_V1);\n\t\tvalue8 &= ~(BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM);\n\t\tvalue8 |= (BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM);\n\t\tHALMAC_REG_W8(REG_AUTO_LLT_V1, value8);\n\n\t\tHALMAC_REG_W8(REG_AUTO_LLT_V1 + 3, BLK_DESC_NUM);\n\t\tHALMAC_REG_W8_SET(REG_TXDMA_OFFSET_CHK + 1, BIT(1));\n\t}\n\n\tHALMAC_REG_W8_SET(REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1);\n\tcnt = 1000;\n\twhile (HALMAC_REG_R8(REG_AUTO_LLT_V1) & BIT_AUTO_INIT_LLT_V1) {\n\t\tcnt--;\n\t\tif (cnt == 0)\n\t\t\treturn HALMAC_RET_INIT_LLT_FAIL;\n\t}\n\n\tif (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK) {\n\t\ttransfer_mode = HALMAC_TRNSFER_LOOPBACK_DELAY;\n\t\tHALMAC_REG_W16(REG_WMAC_LBK_BUF_HD_V1,\n\t\t\t       adapter->txff_alloc.rsvd_boundary);\n\t} else if (mode == HALMAC_TRX_MODE_LOOPBACK) {\n\t\ttransfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT;\n\t} else {\n\t\ttransfer_mode = HALMAC_TRNSFER_NORMAL;\n\t}\n\n\tadapter->hw_cfg_info.trx_mode = transfer_mode;\n\tHALMAC_REG_W8(REG_CR + 3, (u8)transfer_mode);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nset_trx_fifo_info_8822c(struct halmac_adapter *adapter,\n\t\t\tenum halmac_trx_mode mode)\n{\n\tu16 cur_pg_addr;\n\tu32 txff_size = TX_FIFO_SIZE_8822C;\n\tu32 rxff_size = RX_FIFO_SIZE_8822C;\n\tstruct halmac_txff_allocation *info = &adapter->txff_alloc;\n\n\tif (info->rx_fifo_exp_mode == HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK) {\n\t\ttxff_size = TX_FIFO_SIZE_RX_EXPAND_1BLK_8822C;\n\t\trxff_size = RX_FIFO_SIZE_RX_EXPAND_1BLK_8822C;\n\t} else if (info->rx_fifo_exp_mode ==\n\t\t   HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK) {\n\t\ttxff_size = TX_FIFO_SIZE_RX_EXPAND_2BLK_8822C;\n\t\trxff_size = RX_FIFO_SIZE_RX_EXPAND_2BLK_8822C;\n\t} else if (info->rx_fifo_exp_mode ==\n\t\t   HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK) {\n\t\ttxff_size = TX_FIFO_SIZE_RX_EXPAND_3BLK_8822C;\n\t\trxff_size = RX_FIFO_SIZE_RX_EXPAND_3BLK_8822C;\n\t} else if (info->rx_fifo_exp_mode ==\n\t\t   HALMAC_RX_FIFO_EXPANDING_MODE_4_BLOCK) {\n\t\ttxff_size = TX_FIFO_SIZE_RX_EXPAND_4BLK_8822C;\n\t\trxff_size = RX_FIFO_SIZE_RX_EXPAND_4BLK_8822C;\n\t}\n\n\tif (info->la_mode != HALMAC_LA_MODE_DISABLE) {\n\t\ttxff_size = TX_FIFO_SIZE_LA_8822C;\n\t\trxff_size = RX_FIFO_SIZE_8822C;\n\t}\n\n\tadapter->hw_cfg_info.tx_fifo_size = txff_size;\n\tadapter->hw_cfg_info.rx_fifo_size = rxff_size;\n\tinfo->tx_fifo_pg_num = (u16)(txff_size >> TX_PAGE_SIZE_SHIFT_88XX);\n\n\tinfo->rsvd_pg_num = info->rsvd_drv_pg_num +\n\t\t\t\t\tRSVD_PG_H2C_EXTRAINFO_NUM +\n\t\t\t\t\tRSVD_PG_H2C_STATICINFO_NUM +\n\t\t\t\t\tRSVD_PG_H2CQ_NUM +\n\t\t\t\t\tRSVD_PG_CPU_INSTRUCTION_NUM +\n\t\t\t\t\tRSVD_PG_FW_TXBUF_NUM +\n\t\t\t\t\tRSVD_PG_CSIBUF_NUM;\n\n\tif (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK)\n\t\tinfo->rsvd_pg_num += RSVD_PG_DLLB_NUM;\n\n\tif (info->rsvd_pg_num > info->tx_fifo_pg_num)\n\t\treturn HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;\n\n\tinfo->acq_pg_num = info->tx_fifo_pg_num - info->rsvd_pg_num;\n\tinfo->rsvd_boundary = info->tx_fifo_pg_num - info->rsvd_pg_num;\n\n\tcur_pg_addr = info->tx_fifo_pg_num;\n\tcur_pg_addr -= RSVD_PG_CSIBUF_NUM;\n\tinfo->rsvd_csibuf_addr = cur_pg_addr;\n\tcur_pg_addr -= RSVD_PG_FW_TXBUF_NUM;\n\tinfo->rsvd_fw_txbuf_addr = cur_pg_addr;\n\tcur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM;\n\tinfo->rsvd_cpu_instr_addr = cur_pg_addr;\n\tcur_pg_addr -= RSVD_PG_H2CQ_NUM;\n\tinfo->rsvd_h2cq_addr = cur_pg_addr;\n\tcur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM;\n\tinfo->rsvd_h2c_sta_info_addr = cur_pg_addr;\n\tcur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM;\n\tinfo->rsvd_h2c_info_addr = cur_pg_addr;\n\tcur_pg_addr -= info->rsvd_drv_pg_num;\n\tinfo->rsvd_drv_addr = cur_pg_addr;\n\n\tif (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK)\n\t\tinfo->rsvd_drv_addr -= RSVD_PG_DLLB_NUM;\n\n\tif (info->rsvd_boundary != info->rsvd_drv_addr)\n\t\treturn HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * init_system_cfg_8822c() -  init system config\n * @adapter : the adapter of halmac\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ninit_system_cfg_8822c(struct halmac_adapter *adapter)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tu8 value8;\n\tu32 tmp = 0;\n\tu32 value32;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tvalue32 = HALMAC_REG_R32(REG_CPU_DMEM_CON);\n\tvalue32 |= (BIT_WL_PLATFORM_RST | BIT_DDMA_EN);\n\tHALMAC_REG_W32(REG_CPU_DMEM_CON, value32);\n\n\tHALMAC_REG_W8(REG_SYS_FUNC_EN + 1, SYS_FUNC_EN);\n\n\t/*PHY_REQ_DELAY reg 0x1100[27:24] = 0x0C*/\n\tvalue8 = (HALMAC_REG_R8(REG_CR_EXT + 3) & 0xF0) | 0x0C;\n\tHALMAC_REG_W8(REG_CR_EXT + 3, value8);\n\n\t/*disable boot-from-flash for driver's DL FW*/\n\ttmp = HALMAC_REG_R32(REG_MCUFW_CTRL);\n\tif (tmp & BIT_BOOT_FSPI_EN) {\n\t\tHALMAC_REG_W32(REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN));\n\t\tvalue32 = HALMAC_REG_R32(REG_GPIO_MUXCFG) & (~BIT_FSPI_EN);\n\t\tHALMAC_REG_W32(REG_GPIO_MUXCFG, value32);\n\t}\n\n\tif (adapter->chip_ver == HALMAC_CHIP_VER_B_CUT) {\n\t\tvalue8 = HALMAC_REG_R8(REG_ANAPAR_MAC_0);\n\t\tvalue8 = value8 & ~(BITS_LDO_VSEL);\n\t\tHALMAC_REG_W8(REG_ANAPAR_MAC_0, value8);\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * init_protocol_cfg_8822c() - config protocol register\n * @adapter : the adapter of halmac\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ninit_protocol_cfg_8822c(struct halmac_adapter *adapter)\n{\n\tu32 max_agg_num;\n\tu32 max_rts_agg_num;\n\tu32 value32;\n\tu16 pre_txcnt;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tinit_txq_ctrl_8822c(adapter);\n\tinit_sifs_ctrl_8822c(adapter);\n\tinit_rate_fallback_ctrl_8822c(adapter);\n\n\tHALMAC_REG_W8(REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);\n\tHALMAC_REG_W8_SET(REG_TX_HANG_CTRL, BIT_EN_EOF_V1);\n\n\tpre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT;\n\tHALMAC_REG_W8(REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));\n\tHALMAC_REG_W8(REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));\n\n\tmax_agg_num = WLAN_MAX_AGG_PKT_LIMIT;\n\tmax_rts_agg_num = WLAN_RTS_MAX_AGG_PKT_LIMIT;\n\tvalue32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |\n\t\t\t\t(max_agg_num << 16) | (max_rts_agg_num << 24);\n\tHALMAC_REG_W32(REG_PROT_MODE_CTRL, value32);\n\n\tHALMAC_REG_W16(REG_BAR_MODE_CTRL + 2,\n\t\t       WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);\n\n\tHALMAC_REG_W8(REG_FAST_EDCA_VOVI_SETTING, WALN_FAST_EDCA_VO_TH);\n\tHALMAC_REG_W8(REG_FAST_EDCA_VOVI_SETTING + 2, WLAN_FAST_EDCA_VI_TH);\n\tHALMAC_REG_W8(REG_FAST_EDCA_BEBK_SETTING, WLAN_FAST_EDCA_BE_TH);\n\tHALMAC_REG_W8(REG_FAST_EDCA_BEBK_SETTING + 2, WLAN_FAST_EDCA_BK_TH);\n\n\t/*close BA parser*/\n\tHALMAC_REG_W8_CLR(REG_LIFETIME_EN, BIT(5));\n\n\t/*Bypass TXBF error protection due to sounding failure*/\n\tvalue32 = HALMAC_REG_R32(REG_BF0_TIME_SETTING) & (~BIT_BF0_UPDATE_EN);\n\tHALMAC_REG_W32(REG_BF0_TIME_SETTING, value32 | BIT_BF0_TIMER_EN);\n\tvalue32 = HALMAC_REG_R32(REG_BF1_TIME_SETTING) & (~BIT_BF1_UPDATE_EN);\n\tHALMAC_REG_W32(REG_BF1_TIME_SETTING, value32 | BIT_BF1_TIMER_EN);\n\tvalue32 = HALMAC_REG_R32(REG_BF_TIMEOUT_EN) & (~BIT_BF0_TIMEOUT_EN) &\n\t\t (~BIT_BF1_TIMEOUT_EN);\n\tHALMAC_REG_W32(REG_BF_TIMEOUT_EN, value32);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * init_h2c_8822c() - config h2c packet buffer\n * @adapter : the adapter of halmac\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ninit_h2c_8822c(struct halmac_adapter *adapter)\n{\n\tu8 value8;\n\tu32 value32;\n\tu32 h2cq_addr;\n\tu32 h2cq_size;\n\tstruct halmac_txff_allocation *txff_info = &adapter->txff_alloc;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\th2cq_addr = txff_info->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT_88XX;\n\th2cq_size = RSVD_PG_H2CQ_NUM << TX_PAGE_SIZE_SHIFT_88XX;\n\n\tvalue32 = HALMAC_REG_R32(REG_H2C_HEAD);\n\tvalue32 = (value32 & 0xFFFC0000) | h2cq_addr;\n\tHALMAC_REG_W32(REG_H2C_HEAD, value32);\n\n\tvalue32 = HALMAC_REG_R32(REG_H2C_READ_ADDR);\n\tvalue32 = (value32 & 0xFFFC0000) | h2cq_addr;\n\tHALMAC_REG_W32(REG_H2C_READ_ADDR, value32);\n\n\tvalue32 = HALMAC_REG_R32(REG_H2C_TAIL);\n\tvalue32 = (value32 & 0xFFFC0000);\n\tvalue32 |= (h2cq_addr + h2cq_size);\n\tHALMAC_REG_W32(REG_H2C_TAIL, value32);\n\n\tvalue8 = HALMAC_REG_R8(REG_H2C_INFO);\n\tvalue8 = (u8)((value8 & 0xFC) | 0x01);\n\tHALMAC_REG_W8(REG_H2C_INFO, value8);\n\n\tvalue8 = HALMAC_REG_R8(REG_H2C_INFO);\n\tvalue8 = (u8)((value8 & 0xFB) | 0x04);\n\tHALMAC_REG_W8(REG_H2C_INFO, value8);\n\n\tvalue8 = HALMAC_REG_R8(REG_TXDMA_OFFSET_CHK + 1);\n\tvalue8 = (u8)((value8 & 0x7f) | 0x80);\n\tHALMAC_REG_W8(REG_TXDMA_OFFSET_CHK + 1, value8);\n\n\tadapter->h2c_info.buf_size = h2cq_size;\n\tget_h2c_buf_free_space_88xx(adapter);\n\n\tif (adapter->h2c_info.buf_size != adapter->h2c_info.buf_fs) {\n\t\tPLTFM_MSG_ERR(\"[ERR]get h2c free space error!\\n\");\n\t\treturn HALMAC_RET_GET_H2C_SPACE_ERR;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]h2c fs : %d\\n\", adapter->h2c_info.buf_fs);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * init_edca_cfg_8822c() - init EDCA config\n * @adapter : the adapter of halmac\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ninit_edca_cfg_8822c(struct halmac_adapter *adapter)\n{\n\tu8 value8;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tHALMAC_REG_W32(REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM);\n\tHALMAC_REG_W32(REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM);\n\tHALMAC_REG_W32(REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM);\n\tHALMAC_REG_W32(REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM);\n\n\tHALMAC_REG_W8(REG_PIFS, WLAN_PIFS_TIME);\n\n\tHALMAC_REG_W8_CLR(REG_TX_PTCL_CTRL + 1, BIT(4));\n\n\tvalue8 = HALMAC_REG_R8(REG_RD_CTRL + 1);\n\tvalue8 = (value8 | BIT(0) | BIT(1) | BIT(2));\n\tHALMAC_REG_W8(REG_RD_CTRL + 1, value8);\n\n\tcfg_mac_clk_88xx(adapter);\n\n\tvalue8 = HALMAC_REG_R8(REG_MISC_CTRL);\n\tvalue8 = (value8 | BIT(3) | BIT(1) | BIT(0));\n\tHALMAC_REG_W8(REG_MISC_CTRL, value8);\n\n\t/* Init SYNC_CLI_SEL : reg 0x5B4[6:4] = 0 */\n\tHALMAC_REG_W8_CLR(REG_TIMER0_SRC_SEL, BIT(4) | BIT(5) | BIT(6));\n\n\t/* Clear TX pause */\n\tHALMAC_REG_W16(REG_TXPAUSE, 0x0000);\n\n\tHALMAC_REG_W8(REG_SLOT, WLAN_SLOT_TIME);\n\n\tHALMAC_REG_W32(REG_RD_NAV_NXT, WLAN_NAV_CFG);\n\tHALMAC_REG_W16(REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);\n\n\t/* Set beacon cotnrol - enable TSF and other related functions */\n\tHALMAC_REG_W8(REG_BCN_CTRL, (u8)(HALMAC_REG_R8(REG_BCN_CTRL) |\n\t\t\t\t\t  BIT_EN_BCN_FUNCTION));\n\n\t/* Set send beacon related registers */\n\tHALMAC_REG_W32(REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);\n\tHALMAC_REG_W8(REG_DRVERLYINT, WLAN_DRV_EARLY_INT);\n\tHALMAC_REG_W8(REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0);\n\tHALMAC_REG_W8(REG_BCNDMATIM, WLAN_BCN_DMA_TIME);\n\tHALMAC_REG_W8(REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR);\n\n\t/* MU primary packet fail, BAR packet will not issue */\n\tHALMAC_REG_W8_SET(REG_BAR_TX_CTRL, BIT(0));\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic void\ninit_txq_ctrl_8822c(struct halmac_adapter *adapter)\n{\n\tu8 value8;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tvalue8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL);\n\tvalue8 |= (BIT(7) & ~BIT(1) & ~BIT(2));\n\tHALMAC_REG_W8(REG_FWHW_TXQ_CTRL, value8);\n\n\tHALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN);\n}\n\nstatic void\ninit_sifs_ctrl_8822c(struct halmac_adapter *adapter)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tHALMAC_REG_W16(REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE);\n\tHALMAC_REG_W32(REG_SIFS, WLAN_SIFS_CFG);\n\tHALMAC_REG_W16(REG_RESP_SIFS_CCK,\n\t\t       WLAN_SIFS_CCK_CTX | WLAN_SIFS_CCK_IRX << 8);\n\tHALMAC_REG_W16(REG_RESP_SIFS_OFDM,\n\t\t       WLAN_SIFS_OFDM_CTX | WLAN_SIFS_OFDM_IRX << 8);\n}\n\nstatic void\ninit_rate_fallback_ctrl_8822c(struct halmac_adapter *adapter)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tHALMAC_REG_W32(REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4);\n\tHALMAC_REG_W32(REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8);\n\tHALMAC_REG_W32(REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8);\n\n\tHALMAC_REG_W32(REG_ARFR0, WLAN_DATA_RATE_FB_RATE0);\n\tHALMAC_REG_W32(REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H);\n\tHALMAC_REG_W32(REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1);\n\tHALMAC_REG_W32(REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H);\n\tHALMAC_REG_W32(REG_ARFR4, WLAN_RTS_RATE_FB_RATE4);\n\tHALMAC_REG_W32(REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H);\n\tHALMAC_REG_W32(REG_ARFR5, WLAN_RTS_RATE_FB_RATE5);\n\tHALMAC_REG_W32(REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H);\n}\n\n/**\n * init_wmac_cfg_8822c() - init wmac config\n * @adapter : the adapter of halmac\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ninit_wmac_cfg_8822c(struct halmac_adapter *adapter)\n{\n\tu8 value8;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tHALMAC_REG_W32(REG_MAR, 0xFFFFFFFF);\n\tHALMAC_REG_W32(REG_MAR + 4, 0xFFFFFFFF);\n\n\tHALMAC_REG_W8(REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE);\n\tHALMAC_REG_W8(REG_ACKTO, WLAN_ACK_TO);\n\tHALMAC_REG_W8(REG_ACKTO_CCK, WLAN_ACK_TO_CCK);\n\tHALMAC_REG_W16(REG_EIFS, WLAN_EIFS_DUR_TUNE);\n\n\tHALMAC_REG_W8(REG_NAV_CTRL + 2, WLAN_NAV_MAX);\n\n\tHALMAC_REG_W8_SET(REG_WMAC_TRXPTCL_CTL_H, BIT_EN_TXCTS_IN_RXNAV_V1);\n\tHALMAC_REG_W8(REG_WMAC_TRXPTCL_CTL_H  + 2, WLAN_BAR_ACK_TYPE);\n\n\tHALMAC_REG_W32(REG_RXFLTMAP0, WLAN_RX_FILTER0);\n\tHALMAC_REG_W16(REG_RXFLTMAP2, WLAN_RX_FILTER2);\n\n\tHALMAC_REG_W32(REG_RCR, WLAN_RCR_CFG);\n\tvalue8 = HALMAC_REG_R8(REG_RXPSF_CTRL + 2);\n\tvalue8 = value8 | 0xe;\n\tHALMAC_REG_W8(REG_RXPSF_CTRL + 2, value8);\n\n\tHALMAC_REG_W8(REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);\n\n\tHALMAC_REG_W8(REG_TCR + 2, WLAN_TX_FUNC_CFG2);\n\tHALMAC_REG_W8(REG_TCR + 1, WLAN_TX_FUNC_CFG1);\n\n\tHALMAC_REG_W8_SET(REG_SND_PTCL_CTRL, BIT_R_DISABLE_CHECK_VHTSIGB_CRC);\n\n\tHALMAC_REG_W32(REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);\n\n\tif (adapter->hw_cfg_info.trx_mode == HALMAC_TRNSFER_NORMAL)\n\t\tvalue8 = WLAN_MAC_OPT_NORM_FUNC1;\n\telse\n\t\tvalue8 = WLAN_MAC_OPT_LB_FUNC1;\n\n\tHALMAC_REG_W8(REG_WMAC_OPTION_FUNCTION_1, value8);\n\n\tstatus = api->halmac_init_low_pwr(adapter);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * pre_init_system_cfg_8822c() - pre-init system config\n * @adapter : the adapter of halmac\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\npre_init_system_cfg_8822c(struct halmac_adapter *adapter)\n{\n\tu32 value32;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tu8 enable_bb;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tHALMAC_REG_W8(REG_RSV_CTRL, 0);\n\n\tif (adapter->intf == HALMAC_INTERFACE_SDIO) {\n#if HALMAC_SDIO_SUPPORT\n\t\tif (leave_sdio_suspend_88xx(adapter) != HALMAC_RET_SUCCESS)\n\t\t\treturn HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;\n#endif\n\t} else if (adapter->intf == HALMAC_INTERFACE_USB) {\n#if HALMAC_USB_SUPPORT\n\t\tif (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20)\n\t\t\tHALMAC_REG_W8(0xFE5B, HALMAC_REG_R8(0xFE5B) | BIT(4));\n#endif\n\t} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {\n#if HALMAC_PCIE_SUPPORT\n\t\t/* For PCIE power on fail issue */\n\t\tHALMAC_REG_W8(REG_HCI_OPT_CTRL + 1,\n\t\t\t      HALMAC_REG_R8(REG_HCI_OPT_CTRL + 1) | BIT(0));\n#endif\n\t}\n\n\t/* Config PIN Mux */\n\tvalue32 = HALMAC_REG_R32(REG_PAD_CTRL1);\n\tvalue32 = value32 & (~(BIT(28) | BIT(29)));\n\tvalue32 = value32 | BIT(28) | BIT(29);\n\tHALMAC_REG_W32(REG_PAD_CTRL1, value32);\n\n\tvalue32 = HALMAC_REG_R32(REG_LED_CFG);\n\tvalue32 = value32 & (~(BIT(25) | BIT(26)));\n\tHALMAC_REG_W32(REG_LED_CFG, value32);\n\n\tvalue32 = HALMAC_REG_R32(REG_GPIO_MUXCFG);\n\tvalue32 = value32 & (~(BIT(2)));\n\tvalue32 = value32 | BIT(2);\n\tHALMAC_REG_W32(REG_GPIO_MUXCFG, value32);\n\n\tenable_bb = 0;\n\tset_hw_value_88xx(adapter, HALMAC_HW_EN_BB_RF, &enable_bb);\n\n\t/* if (init_xtal_aac(adapter) != HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_INIT_XTAL_AAC_FAIL; */\n\n\tif (HALMAC_REG_R8(REG_SYS_CFG1 + 2) & BIT(4)) {\n\t\tPLTFM_MSG_ERR(\"[ERR]test mode!!\\n\");\n\t\treturn HALMAC_RET_WLAN_MODE_FAIL;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\ninit_xtal_aac(struct halmac_adapter *adapter)\n{\n\tu32 cnt;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tHALMAC_REG_W32_SET(REG_ANAPAR_XTAL_1, BIT_EN_XTAL_DRV_DIGI_V2);\n\tHALMAC_REG_W32_SET(REG_ANAPAR_XTAL_AACK_0, BIT_RESET_N);\n\tHALMAC_REG_W32_SET(REG_ANAPAR_XTAL_AACK_0, (BIT(3) | BIT(2)));\n\tHALMAC_REG_W32_SET(REG_ANAPAR_XTAL_AACK_1, (BIT(4) | BIT(3)));\n\tHALMAC_REG_W32_SET(REG_ANAPAR_XTAL_AACK_0, BIT_EN_XTAL_AAC_TRIG);\n\n\tcnt = 3000;\n\twhile (!(HALMAC_REG_R8(REG_XTAL_AAC_OUTPUT) & BIT_XAAC_READY_V1)) {\n\t\tif (cnt == 0) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]Init XTAL ACC fail\\n\");\n\n\t\t\treturn HALMAC_RET_INIT_XTAL_AAC_FAIL;\n\t\t}\n\t\tcnt--;\n\t\tPLTFM_DELAY_US(20);\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n#endif /* HALMAC_8822C_SUPPORT */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_8822c/halmac_init_8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_INIT_8822C_H_\n#define _HALMAC_INIT_8822C_H_\n\n#include \"../../halmac_api.h\"\n\n#if HALMAC_8822C_SUPPORT\n\nenum halmac_ret_status\nmount_api_8822c(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\ninit_trx_cfg_8822c(struct halmac_adapter *adapter, enum halmac_trx_mode mode);\n\nenum halmac_ret_status\ninit_system_cfg_8822c(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\ninit_protocol_cfg_8822c(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\ninit_h2c_8822c(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\ninit_edca_cfg_8822c(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\ninit_wmac_cfg_8822c(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\npre_init_system_cfg_8822c(struct halmac_adapter *adapter);\n\n#endif /* HALMAC_8822C_SUPPORT */\n\n#endif/* _HALMAC_INIT_8822C_H_ */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_8822c/halmac_pcie_8822c.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"halmac_pcie_8822c.h\"\n#include \"halmac_pwr_seq_8822c.h\"\n#include \"../halmac_init_88xx.h\"\n#include \"../halmac_common_88xx.h\"\n#include \"../halmac_pcie_88xx.h\"\n#include \"../halmac_88xx_cfg.h\"\n\n#if (HALMAC_8822C_SUPPORT && HALMAC_PCIE_SUPPORT)\n\n/**\n * mac_pwr_switch_pcie_8822c() - switch mac power\n * @adapter : the adapter of halmac\n * @pwr : power state\n * Author : KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\n\n#define INTF_INTGRA_MINREF_V1\t90\n#define INTF_INTGRA_HOSTREF_V1\t100\n\nstatic struct halmac_pcie_cfgspc_param pcie_cfgspc_param_def = {\n\t0,\n\t0,\n\tHALMAC_DISABLE,\n\tHALMAC_ENABLE,\n\tHALMAC_ENABLE,\n\tHALMAC_ENABLE,\n\tHALMAC_IGNORE,\n\tHALMAC_CLKDLY_0,\n\tHALMAC_L0SDLY_7US,\n\tHALMAC_L1DLY_16US,\n};\n\nenum pcie_clkdly_hw {\n\tPCIE_CLKDLY_HW_0 = 0,\n\tPCIE_CLKDLY_HW_30US = 0x1,\n\tPCIE_CLKDLY_HW_50US = 0x2,\n\tPCIE_CLKDLY_HW_100US = 0x3,\n\tPCIE_CLKDLY_HW_150US = 0x4,\n\tPCIE_CLKDLY_HW_200US = 0x5\n};\n\nenum pcie_l1dly_hw {\n\tPCIE_L1DLY_HW_16US = 4,\n\tPCIE_L1DLY_HW_32US = 5,\n\tPCIE_L1DLY_HW_64US = 6,\n\tPCIE_L1DLY_HW_INFI = 7\n};\n\nenum pcie_l0sdly_hw {\n\tPCIE_L0SDLY_HW_1US = 0,\n\tPCIE_L0SDLY_HW_3US = 2,\n\tPCIE_L0SDLY_HW_5US = 4,\n\tPCIE_L0SDLY_HW_7US = 6\n};\n\n#define GET_PCIE_FUNC_STUS(val, mask)                                          \\\n\t\t\t  ((val & mask) ? HALMAC_ENABLE : HALMAC_DISABLE)\n\nstatic u16\nget_target(struct halmac_adapter *adapter);\n\nstatic enum halmac_ret_status\npcie_cfgspc_write_8822c(struct halmac_adapter *adapter,\n\t\t\tstruct halmac_pcie_cfgspc_param *param);\n\nstatic enum halmac_ret_status\npcie_cfgspc_read_8822c(struct halmac_adapter *adapter,\n\t\t       struct halmac_pcie_cfgspc_param *param);\n\nstatic void\nupdate_pcie_func_8822c(u8 *val, u8 bitmask, enum halmac_func_ctrl ctrl,\n\t\t       enum halmac_func_ctrl def_ctrl);\n\nstatic u8\nchk_stus_l1ss_8822c(struct halmac_adapter *adapter);\n\nstatic enum halmac_ret_status\nupdate_clkdly_8822c(struct halmac_adapter *adapter, u8 *val,\n\t\t    enum halmac_pcie_clkdly ctrl,\n\t\t    enum halmac_pcie_clkdly def_ctrl);\n\nstatic enum halmac_ret_status\nupdate_pcie_clk_8822c(struct halmac_adapter *adapter, u8 *val);\n\nstatic enum halmac_ret_status\nupdate_aspmdly_8822c(struct halmac_adapter *adapter, u8 *val,\n\t\t     struct halmac_pcie_cfgspc_param *param,\n\t\t     struct halmac_pcie_cfgspc_param *param_def);\n\nenum halmac_ret_status\nmac_pwr_switch_pcie_8822c(struct halmac_adapter *adapter,\n\t\t\t  enum halmac_mac_power pwr)\n{\n\tu8 value8;\n\tu8 rpwm;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\tPLTFM_MSG_TRACE(\"[TRACE]pwr = %x\\n\", pwr);\n\tPLTFM_MSG_TRACE(\"[TRACE]8822C pwr seq ver = %s\\n\",\n\t\t\tHALMAC_8822C_PWR_SEQ_VER);\n\n\tadapter->rpwm = HALMAC_REG_R8(REG_PCIE_HRPWM1_V1);\n\n\t/* Check FW still exist or not */\n\tif (HALMAC_REG_R16(REG_MCUFW_CTRL) == 0xC078) {\n\t\t/* Leave 32K */\n\t\trpwm = (u8)((adapter->rpwm ^ BIT(7)) & 0x80);\n\t\tHALMAC_REG_W8(REG_PCIE_HRPWM1_V1, rpwm);\n\t}\n\n\tvalue8 = HALMAC_REG_R8(REG_CR);\n\tif (value8 == 0xEA)\n\t\tadapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;\n\telse\n\t\tadapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;\n\n\t/* Check if power switch is needed */\n\tif (pwr == HALMAC_MAC_POWER_ON &&\n\t    adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_ON) {\n\t\tPLTFM_MSG_WARN(\"[WARN]power state unchange!!\\n\");\n\t\treturn HALMAC_RET_PWR_UNCHANGE;\n\t}\n\n\tif (pwr == HALMAC_MAC_POWER_OFF) {\n\t\tif (pwr_seq_parser_88xx(adapter, card_dis_flow_8822c) !=\n\t\t    HALMAC_RET_SUCCESS) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]Handle power off cmd error\\n\");\n\t\t\treturn HALMAC_RET_POWER_OFF_FAIL;\n\t\t}\n\n\t\tadapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;\n\t\tadapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;\n\t\tinit_adapter_dynamic_param_88xx(adapter);\n\t} else {\n\t\tif (pwr_seq_parser_88xx(adapter, card_en_flow_8822c) !=\n\t\t    HALMAC_RET_SUCCESS) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]Handle power on cmd error\\n\");\n\t\t\treturn HALMAC_RET_POWER_ON_FAIL;\n\t\t}\n\n\t\tadapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * halmac_pcie_switch_8822c() - pcie gen1/gen2 switch\n * @adapter : the adapter of halmac\n * @cfg : gen1/gen2 selection\n * Author : KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\npcie_switch_8822c(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg)\n{\n\tu8 value8;\n\tu32 value32;\n\tu8 speed = 0;\n\tu32 cnt = 0;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (cfg == HALMAC_PCIE_GEN1) {\n\t\tvalue8 = dbi_r8_88xx(adapter, LINK_CTRL2_REG_OFFSET) & 0xF0;\n\t\tdbi_w8_88xx(adapter, LINK_CTRL2_REG_OFFSET, value8 | BIT(0));\n\n\t\tvalue32 = dbi_r32_88xx(adapter, GEN2_CTRL_OFFSET);\n\t\tdbi_w32_88xx(adapter, GEN2_CTRL_OFFSET, value32 | BIT(17));\n\n\t\tspeed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET) & 0x0F;\n\t\tcnt = 2000;\n\n\t\twhile ((speed != PCIE_GEN1_SPEED) && (cnt != 0)) {\n\t\t\tPLTFM_DELAY_US(50);\n\t\t\tspeed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET);\n\t\t\tspeed &= 0x0F;\n\t\t\tcnt--;\n\t\t}\n\n\t\tif (speed != PCIE_GEN1_SPEED) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]Speed change to GEN1 fail !\\n\");\n\t\t\treturn HALMAC_RET_FAIL;\n\t\t}\n\n\t} else if (cfg == HALMAC_PCIE_GEN2) {\n\t\tvalue8 = dbi_r8_88xx(adapter, LINK_CTRL2_REG_OFFSET) & 0xF0;\n\t\tdbi_w8_88xx(adapter, LINK_CTRL2_REG_OFFSET, value8 | BIT(1));\n\n\t\tvalue32 = dbi_r32_88xx(adapter, GEN2_CTRL_OFFSET);\n\t\tdbi_w32_88xx(adapter, GEN2_CTRL_OFFSET, value32 | BIT(17));\n\n\t\tspeed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET) & 0x0F;\n\t\tcnt = 2000;\n\n\t\twhile ((speed != PCIE_GEN2_SPEED) && (cnt != 0)) {\n\t\t\tPLTFM_DELAY_US(50);\n\t\t\tspeed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET);\n\t\t\tspeed &= 0x0F;\n\t\t\tcnt--;\n\t\t}\n\n\t\tif (speed != PCIE_GEN2_SPEED) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]Speed change to GEN1 fail !\\n\");\n\t\t\treturn HALMAC_RET_FAIL;\n\t\t}\n\n\t} else {\n\t\tPLTFM_MSG_ERR(\"[ERR]Error Speed !\\n\");\n\t\treturn HALMAC_RET_FAIL;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * phy_cfg_pcie_8822c() - phy config\n * @adapter : the adapter of halmac\n * Author : KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nphy_cfg_pcie_8822c(struct halmac_adapter *adapter,\n\t\t   enum halmac_intf_phy_platform pltfm)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tstatus = parse_intf_phy_88xx(adapter, pcie_gen1_phy_param_8822c, pltfm,\n\t\t\t\t     HAL_INTF_PHY_PCIE_GEN1);\n\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tstatus = parse_intf_phy_88xx(adapter, pcie_gen2_phy_param_8822c, pltfm,\n\t\t\t\t     HAL_INTF_PHY_PCIE_GEN2);\n\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * intf_tun_pcie_8822c() - pcie interface fine tuning\n * @adapter : the adapter of halmac\n * Author : Rick Liu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nintf_tun_pcie_8822c(struct halmac_adapter *adapter)\n{\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfgspc_set_pcie_8822c() - pcie configuration space setting\n * @adapter : the adapter of halmac\n * Author : Rick Liu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfgspc_set_pcie_8822c(struct halmac_adapter *adapter,\n\t\t      struct halmac_pcie_cfgspc_param *param)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tif (param->write == 1)\n\t\tstatus = pcie_cfgspc_write_8822c(adapter, param);\n\n\tif (param->read == 1)\n\t\tstatus = pcie_cfgspc_read_8822c(adapter, param);\n\n\treturn status;\n}\n\nstatic enum halmac_ret_status\npcie_cfgspc_write_8822c(struct halmac_adapter *adapter,\n\t\t\tstruct halmac_pcie_cfgspc_param *param)\n{\n\tu8 l1_val;\n\tu8 aspm_val;\n\tu8 l1ss_val;\n\tu8 clk_val;\n\tstruct halmac_pcie_cfgspc_param *param_def = &pcie_cfgspc_param_def;\n\tenum halmac_ret_status status;\n\n\tl1_val = dbi_r8_88xx(adapter, PCIE_L1_CTRL);\n\taspm_val = dbi_r8_88xx(adapter, PCIE_ASPM_CTRL);\n\tl1ss_val = dbi_r8_88xx(adapter, PCIE_L1SS_CTRL);\n\tclk_val = dbi_r8_88xx(adapter, PCIE_CLK_CTRL);\n\tif (l1_val == 0xFF || aspm_val == 0xFF || l1ss_val == 0xFF ||\n\t    clk_val == 0xFF) {\n\t\tPLTFM_MSG_ERR(\"[ERR] PCIE CFG reg read 0xFF!\\n\");\n\t\treturn HALMAC_RET_FAIL;\n\t}\n\n\tupdate_pcie_func_8822c(&aspm_val, PCIE_BIT_L0S,\n\t\t\t       param->l0s_ctrl, param_def->l0s_ctrl);\n\n\tstatus = update_pcie_clk_8822c(adapter, &l1_val);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tupdate_pcie_func_8822c(&l1_val, PCIE_BIT_L1,\n\t\t\t       param->l1_ctrl, param_def->l1_ctrl);\n\tupdate_pcie_func_8822c(&l1_val, PCIE_BIT_WAKE,\n\t\t\t       param->wake_ctrl, param_def->wake_ctrl);\n\tif (chk_stus_l1ss_8822c(adapter) == 1)\n\t\tupdate_pcie_func_8822c(&l1ss_val, PCIE_BIT_L1SS,\n\t\t\t\t       param->l1ss_ctrl, param_def->l1ss_ctrl);\n\tstatus = update_clkdly_8822c(adapter, &clk_val,\n\t\t\t\t     param->clkdly_ctrl,\n\t\t\t\t     param_def->clkdly_ctrl);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tstatus = update_aspmdly_8822c(adapter, &aspm_val, param, param_def);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tif (param->l0s_ctrl != HALMAC_IGNORE ||\n\t    param->l1dly_ctrl != HALMAC_L1DLY_IGNORE ||\n\t    param->l0sdly_ctrl != HALMAC_L0SDLY_IGNORE) {\n\t\tstatus = dbi_w8_88xx(adapter, PCIE_ASPM_CTRL, aspm_val);\n\t\tif (status != HALMAC_RET_SUCCESS)\n\t\t\treturn status;\n\t}\n\tif (param->l1_ctrl != HALMAC_IGNORE ||\n\t    param->wake_ctrl != HALMAC_IGNORE) {\n\t\tstatus = dbi_w8_88xx(adapter, PCIE_L1_CTRL, l1_val);\n\t\tif (status != HALMAC_RET_SUCCESS)\n\t\t\treturn status;\n\t}\n\tif (param->l1ss_ctrl != HALMAC_IGNORE) {\n\t\tstatus = dbi_w8_88xx(adapter, PCIE_L1SS_CTRL, l1ss_val);\n\t\tif (status != HALMAC_RET_SUCCESS)\n\t\t\treturn status;\n\t}\n\tif (param->clkdly_ctrl != HALMAC_CLKDLY_IGNORE) {\n\t\tstatus = dbi_w8_88xx(adapter, PCIE_CLK_CTRL, clk_val);\n\t\tif (status != HALMAC_RET_SUCCESS)\n\t\t\treturn status;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\npcie_cfgspc_read_8822c(struct halmac_adapter *adapter,\n\t\t       struct halmac_pcie_cfgspc_param *param)\n{\n\tu8 l1_val;\n\tu8 aspm_val;\n\tu8 l1ss_val;\n\tu8 clk_val;\n\tu8 l0smask;\n\tu8 l1mask;\n\n\tl1_val = dbi_r8_88xx(adapter, PCIE_L1_CTRL);\n\taspm_val = dbi_r8_88xx(adapter, PCIE_ASPM_CTRL);\n\tl1ss_val = dbi_r8_88xx(adapter, PCIE_L1SS_CTRL);\n\tclk_val = dbi_r8_88xx(adapter, PCIE_CLK_CTRL);\n\tif (l1_val == 0xFF || aspm_val == 0xFF ||\n\t    l1ss_val == 0xFF || clk_val == 0xFF) {\n\t\tPLTFM_MSG_ERR(\"[ERR] (2nd)PCIE CFG reg read 0xFF!\\n\");\n\t\treturn HALMAC_RET_FAIL;\n\t}\n\n\tparam->l0s_ctrl = GET_PCIE_FUNC_STUS(aspm_val, PCIE_BIT_L0S);\n\tparam->l1_ctrl = GET_PCIE_FUNC_STUS(l1_val, PCIE_BIT_L1);\n\tparam->l1ss_ctrl = GET_PCIE_FUNC_STUS(l1ss_val, PCIE_BIT_L1SS);\n\tparam->wake_ctrl = GET_PCIE_FUNC_STUS(l1_val, PCIE_BIT_WAKE);\n\tparam->crq_ctrl = GET_PCIE_FUNC_STUS(l1_val, PCIE_BIT_CLK);\n\n\tswitch (clk_val) {\n\tcase PCIE_CLKDLY_HW_0:\n\t\tparam->clkdly_ctrl = HALMAC_CLKDLY_0;\n\t\tbreak;\n\n\tcase PCIE_CLKDLY_HW_30US:\n\t\tparam->clkdly_ctrl = HALMAC_CLKDLY_30US;\n\t\tbreak;\n\n\tcase PCIE_CLKDLY_HW_50US:\n\t\tparam->clkdly_ctrl = HALMAC_CLKDLY_50US;\n\t\tbreak;\n\n\tcase PCIE_CLKDLY_HW_100US:\n\t\tparam->clkdly_ctrl = HALMAC_CLKDLY_100US;\n\t\tbreak;\n\n\tcase PCIE_CLKDLY_HW_150US:\n\t\tparam->clkdly_ctrl = HALMAC_CLKDLY_150US;\n\t\tbreak;\n\n\tcase PCIE_CLKDLY_HW_200US:\n\t\tparam->clkdly_ctrl = HALMAC_CLKDLY_200US;\n\t\tbreak;\n\n\tdefault:\n\t\tparam->clkdly_ctrl = HALMAC_CLKDLY_R_ERR;\n\t\tbreak;\n\t}\n\n\tl0smask = PCIE_ASPMDLY_MASK << SHFT_L0SDLY;\n\tl1mask = PCIE_ASPMDLY_MASK << SHFT_L1DLY;\n\n\tswitch ((aspm_val & l0smask) >> SHFT_L0SDLY) {\n\tcase PCIE_L0SDLY_HW_1US:\n\t\tparam->l0sdly_ctrl = HALMAC_L0SDLY_1US;\n\t\tbreak;\n\n\tcase PCIE_L0SDLY_HW_3US:\n\t\tparam->l0sdly_ctrl = HALMAC_L0SDLY_3US;\n\t\tbreak;\n\n\tcase PCIE_L0SDLY_HW_5US:\n\t\tparam->l0sdly_ctrl = HALMAC_L0SDLY_5US;\n\t\tbreak;\n\n\tcase PCIE_L0SDLY_HW_7US:\n\t\tparam->l0sdly_ctrl = HALMAC_L0SDLY_7US;\n\t\tbreak;\n\n\tdefault:\n\t\tparam->l0sdly_ctrl = HALMAC_L0SDLY_R_ERR;\n\t\tbreak;\n\t}\n\n\tswitch ((aspm_val & l1mask) >> SHFT_L1DLY) {\n\tcase PCIE_L1DLY_HW_16US:\n\t\tparam->l1dly_ctrl = HALMAC_L1DLY_16US;\n\t\tbreak;\n\n\tcase PCIE_L1DLY_HW_32US:\n\t\tparam->l1dly_ctrl = HALMAC_L1DLY_32US;\n\t\tbreak;\n\n\tcase PCIE_L1DLY_HW_64US:\n\t\tparam->l1dly_ctrl = HALMAC_L1DLY_64US;\n\t\tbreak;\n\n\tcase PCIE_L1DLY_HW_INFI:\n\t\tparam->l1dly_ctrl = HALMAC_L1DLY_INFI;\n\t\tbreak;\n\n\tdefault:\n\t\tparam->l1dly_ctrl = HALMAC_L1DLY_R_ERR;\n\t\tbreak;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic void\nupdate_pcie_func_8822c(u8 *val, u8 bitmask, enum halmac_func_ctrl ctrl,\n\t\t       enum halmac_func_ctrl def_ctrl)\n{\n\tif ((ctrl == HALMAC_DEFAULT &&\n\t     (def_ctrl == HALMAC_IGNORE || def_ctrl == HALMAC_DEFAULT)) ||\n\t    ctrl == HALMAC_IGNORE)\n\t\treturn;\n\n\tif ((ctrl == HALMAC_DEFAULT && def_ctrl == HALMAC_DISABLE) ||\n\t    ctrl == HALMAC_DISABLE)\n\t\t*val &= ~(bitmask);\n\telse\n\t\t*val |= bitmask;\n}\n\nstatic u8\nchk_stus_l1ss_8822c(struct halmac_adapter *adapter)\n{\n\tu16 cap_val;\n\tu8 stus_val;\n\tu8 sup_val;\n\n\tcap_val = (u16)((dbi_r8_88xx(adapter, PCIE_L1SS_CAP + 1) << 8) |\n\t\t\t dbi_r8_88xx(adapter, PCIE_L1SS_CAP));\n\tsup_val = dbi_r8_88xx(adapter, PCIE_L1SS_SUP);\n\tstus_val = dbi_r8_88xx(adapter, PCIE_L1SS_STS);\n\n\tif (cap_val == PCIE_L1SS_ID &&\n\t    (sup_val & PCIE_BIT_L1SSSUP) &&\n\t    (sup_val & PCIE_L1SS_MASK) != 0 &&\n\t    (stus_val & PCIE_L1SS_MASK) != 0)\n\t\treturn 1;\n\n\treturn 0;\n}\n\nstatic enum halmac_ret_status\nupdate_clkdly_8822c(struct halmac_adapter *adapter, u8 *val,\n\t\t    enum halmac_pcie_clkdly ctrl,\n\t\t    enum halmac_pcie_clkdly def_ctrl)\n{\n\tu8 tmp;\n\n\tif (ctrl == HALMAC_CLKDLY_IGNORE)\n\t\treturn HALMAC_RET_SUCCESS;\n\n\ttmp = (ctrl == HALMAC_CLKDLY_DEF) ? def_ctrl : ctrl;\n\tswitch (tmp) {\n\tcase HALMAC_CLKDLY_0:\n\t\t*val = PCIE_CLKDLY_HW_0;\n\t\tbreak;\n\n\tcase HALMAC_CLKDLY_30US:\n\t\t*val = PCIE_CLKDLY_HW_30US;\n\t\tbreak;\n\n\tcase HALMAC_CLKDLY_50US:\n\t\t*val = PCIE_CLKDLY_HW_50US;\n\t\tbreak;\n\n\tcase HALMAC_CLKDLY_100US:\n\t\t*val = PCIE_CLKDLY_HW_100US;\n\t\tbreak;\n\n\tcase HALMAC_CLKDLY_150US:\n\t\t*val = PCIE_CLKDLY_HW_150US;\n\t\tbreak;\n\n\tcase HALMAC_CLKDLY_200US:\n\t\t*val = PCIE_CLKDLY_HW_200US;\n\t\tbreak;\n\n\tdefault:\n\t\tPLTFM_MSG_ERR(\"[ERR]CLKDLY wt val illegal!\\n\");\n\t\treturn HALMAC_RET_FAIL;\n\t}\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nupdate_pcie_clk_8822c(struct halmac_adapter *adapter, u8 *val)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tif (*val & PCIE_BIT_CLK)\n\t\treturn HALMAC_RET_SUCCESS;\n\n\tif (*val & PCIE_BIT_L1) {\n\t\t*val &= ~(PCIE_BIT_L1);\n\t\tstatus = dbi_w8_88xx(adapter, PCIE_L1_CTRL, *val);\n\t\tif (status != HALMAC_RET_SUCCESS)\n\t\t\treturn status;\n\t\t*val |= PCIE_BIT_CLK;\n\t\tstatus = dbi_w8_88xx(adapter, PCIE_L1_CTRL, *val);\n\t\tif (status != HALMAC_RET_SUCCESS)\n\t\t\treturn status;\n\t\t*val |= PCIE_BIT_L1;\n\t\tstatus = dbi_w8_88xx(adapter, PCIE_L1_CTRL, *val);\n\t\tPLTFM_MSG_WARN(\"[WARN] L1 enable & CLKREQ disable!\\n\");\n\t} else {\n\t\t*val |= PCIE_BIT_CLK;\n\t\tstatus = dbi_w8_88xx(adapter, PCIE_L1_CTRL, *val);\n\t}\n\n\treturn status;\n}\n\nstatic enum halmac_ret_status\nupdate_aspmdly_8822c(struct halmac_adapter *adapter, u8 *val,\n\t\t     struct halmac_pcie_cfgspc_param *param,\n\t\t     struct halmac_pcie_cfgspc_param *param_def)\n{\n\tu8 l1mask = PCIE_ASPMDLY_MASK << SHFT_L1DLY;\n\tu8 l0smask = PCIE_ASPMDLY_MASK << SHFT_L0SDLY;\n\tu8 l1updval = param->l1dly_ctrl;\n\tu8 l0supdval = param->l0sdly_ctrl;\n\tu8 l1defval = param_def->l1dly_ctrl;\n\tu8 l0sdefval = param_def->l0sdly_ctrl;\n\tu8 tmp;\n\tu8 hwval;\n\n\tif (l1updval != HALMAC_L1DLY_IGNORE) {\n\t\ttmp = (l1updval == HALMAC_L1DLY_DEF) ? l1defval : l1updval;\n\t\tswitch (tmp) {\n\t\tcase HALMAC_L1DLY_16US:\n\t\t\thwval = PCIE_L1DLY_HW_16US;\n\t\t\tbreak;\n\n\t\tcase HALMAC_L1DLY_32US:\n\t\t\thwval = PCIE_L1DLY_HW_32US;\n\t\t\tbreak;\n\n\t\tcase HALMAC_L1DLY_64US:\n\t\t\thwval = PCIE_L1DLY_HW_64US;\n\t\t\tbreak;\n\n\t\tcase HALMAC_L1DLY_INFI:\n\t\t\thwval = PCIE_L1DLY_HW_INFI;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tPLTFM_MSG_ERR(\"[ERR]L1DLY wt val illegal!\\n\");\n\t\t\treturn HALMAC_RET_FAIL;\n\t\t}\n\n\t\ttmp = (hwval << SHFT_L1DLY) & l1mask;\n\t\t*val = (*val & ~(l1mask)) | tmp;\n\t}\n\n\tif (l0supdval != HALMAC_L0SDLY_IGNORE) {\n\t\ttmp = (l0supdval == HALMAC_L0SDLY_DEF) ? l0sdefval : l0supdval;\n\t\tswitch (tmp) {\n\t\tcase HALMAC_L0SDLY_1US:\n\t\t\thwval = PCIE_L0SDLY_HW_1US;\n\t\t\tbreak;\n\n\t\tcase HALMAC_L0SDLY_3US:\n\t\t\thwval = PCIE_L0SDLY_HW_3US;\n\t\t\tbreak;\n\n\t\tcase HALMAC_L0SDLY_5US:\n\t\t\thwval = PCIE_L0SDLY_HW_5US;\n\t\t\tbreak;\n\n\t\tcase HALMAC_L0SDLY_7US:\n\t\t\thwval = PCIE_L0SDLY_HW_7US;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tPLTFM_MSG_ERR(\"[ERR]L0SDLY wt val illegal!\\n\");\n\t\t\treturn HALMAC_RET_FAIL;\n\t\t}\n\t\ttmp = (hwval << SHFT_L0SDLY) & l0smask;\n\t\t*val = (*val & ~(l0smask)) | tmp;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nauto_refclk_cal_8822c_pcie(struct halmac_adapter *adapter)\n{\n\tu8 bdr_ori;\n\tu16 tmp_u16;\n\tu16 div_set;\n\tu16 mgn_tmp;\n\tu16 mgn_set;\n\tu16 tar;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tu8 l1_flag = 0;\n\n#if (INTF_INTGRA_HOSTREF_V1 <= INTF_INTGRA_MINREF_V1)\n\treturn status;\n#endif\n\t/* Disable L1BD */\n\tbdr_ori = dbi_r8_88xx(adapter, PCIE_L1_CTRL);\n\tif (bdr_ori & PCIE_BIT_L1) {\n\t\tstatus = dbi_w8_88xx(adapter, PCIE_L1_CTRL,\n\t\t\t\t     bdr_ori & ~(PCIE_BIT_L1));\n\t\tif (status != HALMAC_RET_SUCCESS)\n\t\t\treturn status;\n\t\tl1_flag = 1;\n\t}\n\n\t/* Disable function */\n\ttmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR_V1,\n\t\t\t\t HAL_INTF_PHY_PCIE_GEN1);\n\tif (tmp_u16 & BIT(13)) {\n\t\tstatus = mdio_write_88xx(adapter, RAC_CTRL_PPR_V1,\n\t\t\t\t\t tmp_u16 & ~(BIT(13)),\n\t\t\t\t\t HAL_INTF_PHY_PCIE_GEN1);\n\t\tif (status != HALMAC_RET_SUCCESS)\n\t\t\treturn status;\n\t}\n\tif (adapter->pcie_refautok_en == 0) {\n\t\tif (l1_flag == 1)\n\t\t\tstatus = dbi_w8_88xx(adapter, PCIE_L1_CTRL, bdr_ori);\n\t\treturn status;\n\t}\n\n\t/* Set div */\n\ttmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR_V1\n\t\t\t\t , HAL_INTF_PHY_PCIE_GEN1);\n\tstatus = mdio_write_88xx(adapter, RAC_CTRL_PPR_V1,\n\t\t\t\t tmp_u16 & ~(BIT(15) | BIT(14)),\n\t\t\t\t HAL_INTF_PHY_PCIE_GEN1);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\t/*  Obtain div and margin */\n\ttar = get_target(adapter);\n\tif (tar == 0xFFFF)\n\t\treturn HALMAC_RET_FAIL;\n\tmgn_tmp = tar * INTF_INTGRA_HOSTREF_V1 / INTF_INTGRA_MINREF_V1 - tar;\n\n\tif (mgn_tmp >= 128) {\n\t\tdiv_set = 0x0003;\n\t\tmgn_set = 0x000F;\n\t} else if (mgn_tmp >= 64) {\n\t\tdiv_set = 0x0003;\n\t\tmgn_set = mgn_tmp >> 3;\n\t} else if (mgn_tmp >= 32) {\n\t\tdiv_set = 0x0002;\n\t\tmgn_set = mgn_tmp >> 2;\n\t} else if (mgn_tmp >= 16) {\n\t\tdiv_set = 0x0001;\n\t\tmgn_set = mgn_tmp >> 1;\n\t} else if (mgn_tmp == 0) {\n\t\tdiv_set = 0x0000;\n\t\tmgn_set = 0x0001;\n\t} else {\n\t\tdiv_set = 0x0000;\n\t\tmgn_set = mgn_tmp;\n\t}\n\n\t/* Set div, margin, target*/\n\ttmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR_V1,\n\t\t\t\t HAL_INTF_PHY_PCIE_GEN1);\n\ttmp_u16 = (tmp_u16 & ~(BIT(15) | BIT(14))) | (div_set << 6);\n\tstatus = mdio_write_88xx(adapter, RAC_CTRL_PPR_V1,\n\t\t\t\t tmp_u16, HAL_INTF_PHY_PCIE_GEN1);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\ttar = get_target(adapter);\n\tif (tar == 0xFFFF)\n\t\treturn HALMAC_RET_FAIL;\n\tPLTFM_MSG_TRACE(\"[TRACE]target = 0x%X, div = 0x%X, margin = 0x%X\\n\",\n\t\t\ttar, div_set, mgn_set);\n\tstatus = mdio_write_88xx(adapter, RAC_SET_PPR_V1,\n\t\t\t\t (tar & 0x0FFF) | (mgn_set << 12),\n\t\t\t\t HAL_INTF_PHY_PCIE_GEN1);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\t/* Enable function */\n\ttmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR_V1,\n\t\t\t\t HAL_INTF_PHY_PCIE_GEN1);\n\tstatus = mdio_write_88xx(adapter, RAC_CTRL_PPR_V1, tmp_u16 | BIT(13),\n\t\t\t\t HAL_INTF_PHY_PCIE_GEN1);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\t/* Set L1BD to ori */\n\tif (l1_flag == 1)\n\t\tstatus = dbi_w8_88xx(adapter, PCIE_L1_CTRL, bdr_ori);\n\n\treturn status;\n}\n\nstatic u16\nget_target(struct halmac_adapter *adapter)\n{\n\tu16 tmp_u16;\n\tu16 tar;\n\tu16 count;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\t/* Enable counter */\n\ttmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR_V1,\n\t\t\t\t HAL_INTF_PHY_PCIE_GEN1);\n\tstatus = mdio_write_88xx(adapter, RAC_CTRL_PPR_V1,\n\t\t\t\t tmp_u16 | BIT(12), HAL_INTF_PHY_PCIE_GEN1);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn 0xFFFF;\n\n\t/* Obtain target */\n\tcount = 0;\n\tdo {\n\t\tPLTFM_DELAY_US(10);\n\t\ttmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR_V1,\n\t\t\t\t\t HAL_INTF_PHY_PCIE_GEN1);\n\t\tcount++;\n\t\tif (count > 100)\n\t\t\tbreak;\n\t} while ((tmp_u16 & BIT(12)) == BIT(12));\n\tif (count > 100) {\n\t\tPLTFM_MSG_ERR(\"[ERR]Get target timeout.\\n\");\n\t\treturn 0xFFFF;\n\t}\n\ttar = mdio_read_88xx(adapter, RAC_CTRL_PPR_V1, HAL_INTF_PHY_PCIE_GEN1);\n\ttar = tar & 0x0FFF;\n\tif (tar == 0) {\n\t\tPLTFM_MSG_ERR(\"[ERR]Get target failed.\\n\");\n\t\treturn 0xFFFF;\n\t}\n\treturn tar;\n}\n\n#endif /* HALMAC_8822C_SUPPORT*/\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_8822c/halmac_pcie_8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_API_8822C_PCIE_H_\n#define _HALMAC_API_8822C_PCIE_H_\n\n#include \"../../halmac_api.h\"\n\n#if (HALMAC_8822C_SUPPORT && HALMAC_PCIE_SUPPORT)\n\nextern struct halmac_intf_phy_para pcie_gen1_phy_param_8822c[];\nextern struct halmac_intf_phy_para pcie_gen2_phy_param_8822c[];\n\nenum halmac_ret_status\nmac_pwr_switch_pcie_8822c(struct halmac_adapter *adapter,\n\t\t\t  enum halmac_mac_power pwr);\n\nenum halmac_ret_status\npcie_switch_8822c(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg);\n\nenum halmac_ret_status\nphy_cfg_pcie_8822c(struct halmac_adapter *adapter,\n\t\t   enum halmac_intf_phy_platform pltfm);\n\nenum halmac_ret_status\nintf_tun_pcie_8822c(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\ncfgspc_set_pcie_8822c(struct halmac_adapter *adapter,\n\t\t      struct halmac_pcie_cfgspc_param *param);\n\nenum halmac_ret_status\nauto_refclk_cal_8822c_pcie(struct halmac_adapter *adapter);\n\n#endif /* HALMAC_8822C_SUPPORT*/\n\n#endif/* _HALMAC_API_8822C_PCIE_H_ */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_8822c/halmac_phy_8822c.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"../../halmac_type.h\"\n#if HALMAC_USB_SUPPORT\n#include \"halmac_usb_8822c.h\"\n#endif\n#if HALMAC_PCIE_SUPPORT\n#include \"halmac_pcie_8822c.h\"\n#endif\n\n/**\n * ============ip sel item list============\n * HALMAC_IP_INTF_PHY\n *\tUSB2 : usb2 phy, 1byte value\n *\tUSB3 : usb3 phy, 2byte value\n *\tPCIE1 : pcie gen1 mdio, 2byte value\n *\tPCIE2 : pcie gen2 mdio, 2byte value\n * HALMAC_IP_SEL_MAC\n *\tUSB2, USB3, PCIE1, PCIE2 : mac ip, 1byte value\n * HALMAC_IP_PCIE_DBI\n *\tUSB2 USB3 : none\n *\tPCIE1, PCIE2 : pcie dbi, 1byte value\n */\n\n#if HALMAC_8822C_SUPPORT\n\nstruct halmac_intf_phy_para usb2_phy_param_8822c[] = {\n\t/* {offset, value, ip sel, cut mask, platform mask} */\n\t{0xFFFF, 0x00,\n\t HALMAC_IP_INTF_PHY,\n\t HALMAC_INTF_PHY_CUT_ALL,\n\t HALMAC_INTF_PHY_PLATFORM_ALL},\n};\n\nstruct halmac_intf_phy_para usb3_phy_param_8822c[] = {\n\t/* {offset, value, ip sel, cut mask, platform mask} */\n\t{0xFFFF, 0x0000,\n\t HALMAC_IP_INTF_PHY,\n\t HALMAC_INTF_PHY_CUT_ALL,\n\t HALMAC_INTF_PHY_PLATFORM_ALL},\n};\n\nstruct halmac_intf_phy_para pcie_gen1_phy_param_8822c[] = {\n\t/* {offset, value, ip sel, cut mask, platform mask} */\n\t{0xFFFF, 0x0000,\n\t HALMAC_IP_INTF_PHY,\n\t HALMAC_INTF_PHY_CUT_ALL,\n\t HALMAC_INTF_PHY_PLATFORM_ALL},\n};\n\nstruct halmac_intf_phy_para pcie_gen2_phy_param_8822c[] = {\n\t/* {offset, value, ip sel, cut mask, platform mask} */\n\t{0xFFFF, 0x0000,\n\t HALMAC_IP_INTF_PHY,\n\t HALMAC_INTF_PHY_CUT_ALL,\n\t HALMAC_INTF_PHY_PLATFORM_ALL},\n};\n\n#endif /* HALMAC_8822C_SUPPORT*/\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_8822c/halmac_pwr_seq_8822c.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"halmac_pwr_seq_8822c.h\"\n\n#if HALMAC_8822C_SUPPORT\n\nstatic struct halmac_wlan_pwr_cfg TRANS_CARDDIS_TO_CARDEMU_8822C[] = {\n\t/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */\n\t{0x0086,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_SDIO,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), 0},\n\t{0x0086,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_SDIO,\n\t HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},\n\t{0x002E,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},\n\t{0x002D,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), 0},\n\t{0x007F,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(7), 0},\n\t{0x004A,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_USB_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), 0},\n\t{0x0005,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0},\n\t{0xFFFF,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t 0,\n\t HALMAC_PWR_CMD_END, 0, 0},\n};\n\nstatic struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_ACT_8822C[] = {\n\t/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */\n\t{0x0000,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(5), 0},\n\t{0x0005,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},\n\t{0x0075,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},\n\t{0x0006,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},\n\t{0x0075,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), 0},\n\t{0xFF1A,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_USB_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0},\n\t{0x002E,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(3), 0},\n\t{0x0006,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},\n\t{0x0005,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},\n\t{0x1018,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},\n\t{0x0005,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},\n\t{0x0005,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_POLLING, BIT(0), 0},\n\t{0x0074,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},\n\t{0x0071,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(4), 0},\n\t{0x0062,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),\n\t (BIT(7) | BIT(6) | BIT(5))},\n\t{0x0061,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},\n\t{0x001F,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)},\n\t{0x00EF,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)},\n\t{0x1045,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},\n\t{0x0010,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},\n\t{0xFFFF,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t 0,\n\t HALMAC_PWR_CMD_END, 0, 0},\n};\n\nstatic struct halmac_wlan_pwr_cfg TRANS_ACT_TO_CARDEMU_8822C[] = {\n\t/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */\n\t{0x0093,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(3), 0},\n\t{0x001F,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0},\n\t{0x00EF,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0},\n\t{0x1045,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(4), 0},\n\t{0xFF1A,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_USB_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x30},\n\t{0x0049,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(1), 0},\n\t{0x0006,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},\n\t{0x0002,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(1), 0},\n\t{0x0005,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},\n\t{0x0005,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_POLLING, BIT(1), 0},\n\t{0x0000,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},\n\t{0xFFFF,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t 0,\n\t HALMAC_PWR_CMD_END, 0, 0},\n};\n\nstatic struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_CARDDIS_8822C[] = {\n\t/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */\n\t{0x0007,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x00},\n\t{0x0067,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(5), 0},\n\t{0x004A,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_USB_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), 0},\n\t{0x0081,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},\n\t{0x0090,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(1), 0},\n\t{0x0092,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},\n\t{0x0093,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x04},\n\t{0x0005,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},\n\t{0x0005,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},\n\t{0x0086,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_SDIO,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},\n\t{0xFFFF,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t 0,\n\t HALMAC_PWR_CMD_END, 0, 0},\n};\n\n/* Card Enable Array */\nstruct halmac_wlan_pwr_cfg *card_en_flow_8822c[] = {\n\tTRANS_CARDDIS_TO_CARDEMU_8822C,\n\tTRANS_CARDEMU_TO_ACT_8822C,\n\tNULL\n};\n\n/* Card Disable Array */\nstruct halmac_wlan_pwr_cfg *card_dis_flow_8822c[] = {\n\tTRANS_ACT_TO_CARDEMU_8822C,\n\tTRANS_CARDEMU_TO_CARDDIS_8822C,\n\tNULL\n};\n\n#if HALMAC_PLATFORM_TESTPROGRAM\n\nstatic struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_SUS_8822C[] = {\n\t/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */\n\t{0x0005,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))},\n\t{0x0005,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},\n\t{0x0007,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},\n\t{0x0005,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\n\t{0x0086,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_SDIO,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},\n\t{0x0086,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_SDIO,\n\t HALMAC_PWR_CMD_POLLING, BIT(1), 0},\n\t{0xFFFF,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t 0,\n\t HALMAC_PWR_CMD_END, 0, 0},\n};\n\nstatic struct halmac_wlan_pwr_cfg TRANS_SUS_TO_CARDEMU_8822C[] = {\n\t/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */\n\t{0x0005,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0},\n\t{0x0086,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_SDIO,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), 0},\n\t{0x0086,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_SDIO,\n\t HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},\n\t{0x0005,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0},\n\t{0xFFFF,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t 0,\n\t HALMAC_PWR_CMD_END, 0, 0},\n};\n\nstatic struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_PDN_8822C[] = {\n\t/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */\n\t{0x0007,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_SDIO_MSK | HALMAC_PWR_INTF_USB_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},\n\t{0x0006,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), 0},\n\t{0x0005,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},\n\t{0xFFFF,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t 0,\n\t HALMAC_PWR_CMD_END, 0, 0},\n};\n\nstatic struct halmac_wlan_pwr_cfg TRANS_PDN_TO_CARDEMU_8822C[] = {\n\t/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */\n\t{0x0005,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(7), 0},\n\t{0xFFFF,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t 0,\n\t HALMAC_PWR_CMD_END, 0, 0},\n};\n\nstatic struct halmac_wlan_pwr_cfg TRANS_ACT_TO_LPS_8822C[] = {\n\t/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */\n\t{0x0101,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},\n\t{0x0199,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)},\n\t{0x019B,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},\n\t{0x1138,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)},\n\t{0x0194,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},\n\t{0x0093,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x06},\n\t{0x0092,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x68},\n\t{0x0093,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x02},\n\t{0x0092,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x68},\n\t{0x0093,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_USB_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x03},\n\t{0x0092,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_USB_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x68},\n\t{0x0090,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},\n\t{0x0301,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0x7F, 0xFF},\n\t{0x0522,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},\n\t{0x05F8,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_POLLING, 0xFF, 0},\n\t{0x05F9,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_POLLING, 0xFF, 0},\n\t{0x05FA,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_POLLING, 0xFF, 0},\n\t{0x05FB,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_POLLING, 0xFF, 0},\n\t{0x0002,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), 0},\n\t{0x0002,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_US},\n\t{0x0100,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F},\n\t{0x0008,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},\n\t{0x0109,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)},\n\t{0x0090,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},\n\t{0xFFFF,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t 0,\n\t HALMAC_PWR_CMD_END, 0, 0},\n};\n\nstatic struct halmac_wlan_pwr_cfg TRANS_ACT_TO_DEEP_LPS_8822C[] = {\n\t/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */\n\t{0x0101,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},\n\t{0x0199,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)},\n\t{0x019B,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},\n\t{0x1138,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)},\n\t{0x0194,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},\n\t{0x0093,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x04},\n\t{0x0092,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x28},\n\t{0x0093,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x00},\n\t{0x0092,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x28},\n\t{0x0093,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_USB_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x01},\n\t{0x0092,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_USB_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x28},\n\t{0x0090,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},\n\t{0x0301,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0x7F, 0xFF},\n\t{0x0522,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},\n\t{0x05F8,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_POLLING, 0xFF, 0},\n\t{0x05F9,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_POLLING, 0xFF, 0},\n\t{0x05FA,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_POLLING, 0xFF, 0},\n\t{0x05FB,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_POLLING, 0xFF, 0},\n\t{0x0002,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), 0},\n\t{0x0002,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_US},\n\t{0x0100,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F},\n\t{0x0008,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},\n\t{0x0109,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)},\n\t{0x0090,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},\n\t{0xFFFF,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t 0,\n\t HALMAC_PWR_CMD_END, 0, 0},\n};\n\nstatic struct halmac_wlan_pwr_cfg TRANS_LPS_TO_ACT_8822C[] = {\n\t/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */\n\t{0x0080,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_SDIO,\n\t HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},\n\t{0x0002,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS},\n\t{0x0080,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_SDIO_MSK,\n\t HALMAC_PWR_ADDR_SDIO,\n\t HALMAC_PWR_CMD_WRITE, BIT(7), 0},\n\t{0xFE58,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_USB_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x84},\n\t{0x03D9,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},\n\t{0x0002,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS},\n\t{0x03D9,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(7), 0},\n\t{0x0002,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS},\n\t{0x0008,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(4), 0},\n\t{0x0109,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_POLLING, BIT(7), 0},\n\t{0x0100,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF },\n\t{0x0002,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},\n\t{0x0522,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0},\n\t{0x113C,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0x03},\n\t{0x0124,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},\n\t{0x0125,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},\n\t{0x0126,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},\n\t{0x0127,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},\n\t{0x0090,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(1), 0},\n\t{0x0101,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, BIT(2), 0},\n\t{0x0301,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_PCI_MSK,\n\t HALMAC_PWR_ADDR_MAC,\n\t HALMAC_PWR_CMD_WRITE, 0x7F, 0x00},\n\t{0xFFFF,\n\t HALMAC_PWR_CUT_ALL_MSK,\n\t HALMAC_PWR_INTF_ALL_MSK,\n\t 0,\n\t HALMAC_PWR_CMD_END, 0, 0},\n};\n\n/* Suspend Array */\nstruct halmac_wlan_pwr_cfg *suspend_flow_8822c[] = {\n\tTRANS_ACT_TO_CARDEMU_8822C,\n\tTRANS_CARDEMU_TO_SUS_8822C,\n\tNULL\n};\n\n/* Resume Array */\nstruct halmac_wlan_pwr_cfg *resume_flow_8822c[] = {\n\tTRANS_SUS_TO_CARDEMU_8822C,\n\tTRANS_CARDEMU_TO_ACT_8822C,\n\tNULL\n};\n\n/* HWPDN Array - HW behavior */\nstruct halmac_wlan_pwr_cfg *hwpdn_flow_8822c[] = {\n\tNULL\n};\n\n/* Enter LPS - FW behavior */\nstruct halmac_wlan_pwr_cfg *enter_lps_flow_8822c[] = {\n\tTRANS_ACT_TO_LPS_8822C,\n\tNULL\n};\n\n/* Enter Deep LPS - FW behavior */\nstruct halmac_wlan_pwr_cfg *enter_dlps_flow_8822c[] = {\n\tTRANS_ACT_TO_DEEP_LPS_8822C,\n\tNULL\n};\n\n/* Leave LPS -FW behavior */\nstruct halmac_wlan_pwr_cfg *leave_lps_flow_8822c[] = {\n\tTRANS_LPS_TO_ACT_8822C,\n\tNULL\n};\n\n#endif\n\n#endif /* HALMAC_8822C_SUPPORT */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_8822c/halmac_pwr_seq_8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2019 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef HALMAC_POWER_SEQUENCE_8822C\n#define HALMAC_POWER_SEQUENCE_8822C\n\n#include \"../../halmac_pwr_seq_cmd.h\"\n#include \"../../halmac_hw_cfg.h\"\n\n#if HALMAC_8822C_SUPPORT\n\n#define HALMAC_8822C_PWR_SEQ_VER  \"V15\"\n\nextern struct halmac_wlan_pwr_cfg *card_en_flow_8822c[];\nextern struct halmac_wlan_pwr_cfg *card_dis_flow_8822c[];\n\n#if HALMAC_PLATFORM_TESTPROGRAM\nextern struct halmac_wlan_pwr_cfg *suspend_flow_8822c[];\nextern struct halmac_wlan_pwr_cfg *resume_flow_8822c[];\nextern struct halmac_wlan_pwr_cfg *hwpdn_flow_8822c[];\nextern struct halmac_wlan_pwr_cfg *enter_lps_flow_8822c[];\nextern struct halmac_wlan_pwr_cfg *enter_dlps_flow_8822c[];\nextern struct halmac_wlan_pwr_cfg *leave_lps_flow_8822c[];\n#endif\n\n#endif /* HALMAC_8822C_SUPPORT*/\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_88xx_cfg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_88XX_CFG_H_\n#define _HALMAC_88XX_CFG_H_\n\n#include \"../halmac_api.h\"\n\n#if HALMAC_88XX_SUPPORT\n\n#define TX_PAGE_SIZE_88XX\t\t128\n#define TX_PAGE_SIZE_SHIFT_88XX\t\t7 /* 128 = 2^7 */\n#define TX_ALIGN_SIZE_88XX\t\t8\n#define SDIO_TX_MAX_SIZE_88XX\t\t31744\n#define RX_BUF_FW_88XX\t\t\t12288\n\n#define TX_DESC_SIZE_88XX\t\t48\n#define RX_DESC_SIZE_88XX\t\t24\n\n#define H2C_PKT_SIZE_88XX\t\t32 /* Only support 32 byte packet now */\n#define H2C_PKT_HDR_SIZE_88XX\t\t8\n#define C2H_DATA_OFFSET_88XX\t\t10\n#define C2H_PKT_BUF_88XX\t\t256\n\n/* HW memory address */\n#define OCPBASE_TXBUF_88XX\t\t0x18780000\n#define OCPBASE_DMEM_88XX\t\t0x00200000\n#define OCPBASE_EMEM_88XX\t\t0x00100000\n\n#endif /* HALMAC_88XX_SUPPORT */\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"halmac_bb_rf_88xx.h\"\n#include \"halmac_88xx_cfg.h\"\n#include \"halmac_common_88xx.h\"\n#include \"halmac_init_88xx.h\"\n\n#if HALMAC_88XX_SUPPORT\n\n/**\n * start_iqk_88xx() -trigger FW IQK\n * @adapter : the adapter of halmac\n * @param : IQK parameter\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nstart_iqk_88xx(struct halmac_adapter *adapter, struct halmac_iqk_para *param)\n{\n\tu8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };\n\tu16 seq_num = 0;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tstruct halmac_h2c_header_info hdr_info;\n\tenum halmac_cmd_process_status *proc_status;\n\n\tproc_status = &adapter->halmac_state.iqk_state.proc_status;\n\n\tif (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_NO_DLFW;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (*proc_status == HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_TRACE(\"[TRACE]Wait event(iqk)\\n\");\n\t\treturn HALMAC_RET_BUSY_STATE;\n\t}\n\n\t*proc_status = HALMAC_CMD_PROCESS_SENDING;\n\n\tIQK_SET_CLEAR(h2c_buf, param->clear);\n\tIQK_SET_SEGMENT_IQK(h2c_buf, param->segment_iqk);\n\n\thdr_info.sub_cmd_id = SUB_CMD_ID_IQK;\n\thdr_info.content_size = 1;\n\thdr_info.ack = 1;\n\tset_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);\n\n\tadapter->halmac_state.iqk_state.seq_num = seq_num;\n\n\tstatus = send_h2c_pkt_88xx(adapter, h2c_buf);\n\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]send h2c pkt fail!!\\n\");\n\t\treset_ofld_feature_88xx(adapter, HALMAC_FEATURE_IQK);\n\t\treturn status;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * ctrl_pwr_tracking_88xx() -trigger FW power tracking\n * @adapter : the adapter of halmac\n * @opt : power tracking option\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nctrl_pwr_tracking_88xx(struct halmac_adapter *adapter,\n\t\t       struct halmac_pwr_tracking_option *opt)\n{\n\tu8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };\n\tu16 seq_num = 0;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tstruct halmac_h2c_header_info hdr_info;\n\tstruct halmac_pwr_tracking_para *param;\n\tenum halmac_cmd_process_status *proc_status;\n\n\tproc_status = &adapter->halmac_state.pwr_trk_state.proc_status;\n\n\tif (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_NO_DLFW;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (*proc_status == HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_TRACE(\"[TRACE]Wait event(pwr tracking)...\\n\");\n\t\treturn HALMAC_RET_BUSY_STATE;\n\t}\n\n\t*proc_status = HALMAC_CMD_PROCESS_SENDING;\n\n\tPWR_TRK_SET_TYPE(h2c_buf, opt->type);\n\tPWR_TRK_SET_BBSWING_INDEX(h2c_buf, opt->bbswing_index);\n\n\tparam = &opt->pwr_tracking_para[HALMAC_RF_PATH_A];\n\tPWR_TRK_SET_ENABLE_A(h2c_buf, param->enable);\n\tPWR_TRK_SET_TX_PWR_INDEX_A(h2c_buf, param->tx_pwr_index);\n\tPWR_TRK_SET_TSSI_VALUE_A(h2c_buf, param->tssi_value);\n\tPWR_TRK_SET_OFFSET_VALUE_A(h2c_buf, param->pwr_tracking_offset_value);\n\n\tparam = &opt->pwr_tracking_para[HALMAC_RF_PATH_B];\n\tPWR_TRK_SET_ENABLE_B(h2c_buf, param->enable);\n\tPWR_TRK_SET_TX_PWR_INDEX_B(h2c_buf, param->tx_pwr_index);\n\tPWR_TRK_SET_TSSI_VALUE_B(h2c_buf, param->tssi_value);\n\tPWR_TRK_SET_OFFSET_VALUE_B(h2c_buf, param->pwr_tracking_offset_value);\n\n\tparam = &opt->pwr_tracking_para[HALMAC_RF_PATH_C];\n\tPWR_TRK_SET_ENABLE_C(h2c_buf, param->enable);\n\tPWR_TRK_SET_TX_PWR_INDEX_C(h2c_buf, param->tx_pwr_index);\n\tPWR_TRK_SET_TSSI_VALUE_C(h2c_buf, param->tssi_value);\n\tPWR_TRK_SET_OFFSET_VALUE_C(h2c_buf, param->pwr_tracking_offset_value);\n\n\tparam = &opt->pwr_tracking_para[HALMAC_RF_PATH_D];\n\tPWR_TRK_SET_ENABLE_D(h2c_buf, param->enable);\n\tPWR_TRK_SET_TX_PWR_INDEX_D(h2c_buf, param->tx_pwr_index);\n\tPWR_TRK_SET_TSSI_VALUE_D(h2c_buf, param->tssi_value);\n\tPWR_TRK_SET_OFFSET_VALUE_D(h2c_buf, param->pwr_tracking_offset_value);\n\n\thdr_info.sub_cmd_id = SUB_CMD_ID_PWR_TRK;\n\thdr_info.content_size = 20;\n\thdr_info.ack = 1;\n\tset_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);\n\n\tadapter->halmac_state.pwr_trk_state.seq_num = seq_num;\n\n\tstatus = send_h2c_pkt_88xx(adapter, h2c_buf);\n\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]send h2c pkt fail!!\\n\");\n\t\treset_ofld_feature_88xx(adapter, HALMAC_FEATURE_POWER_TRACKING);\n\t\treturn status;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nget_iqk_status_88xx(struct halmac_adapter *adapter,\n\t\t    enum halmac_cmd_process_status *proc_status)\n{\n\t*proc_status = adapter->halmac_state.iqk_state.proc_status;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nget_pwr_trk_status_88xx(struct halmac_adapter *adapter,\n\t\t\tenum halmac_cmd_process_status *proc_status)\n{\n\t*proc_status = adapter->halmac_state.pwr_trk_state.proc_status;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nget_psd_status_88xx(struct halmac_adapter *adapter,\n\t\t    enum halmac_cmd_process_status *proc_status, u8 *data,\n\t\t    u32 *size)\n{\n\tstruct halmac_psd_state *state = &adapter->halmac_state.psd_state;\n\n\t*proc_status = state->proc_status;\n\n\tif (!data)\n\t\treturn HALMAC_RET_NULL_POINTER;\n\n\tif (!size)\n\t\treturn HALMAC_RET_NULL_POINTER;\n\n\tif (*proc_status == HALMAC_CMD_PROCESS_DONE) {\n\t\tif (*size < state->data_size) {\n\t\t\t*size = state->data_size;\n\t\t\treturn HALMAC_RET_BUFFER_TOO_SMALL;\n\t\t}\n\n\t\t*size = state->data_size;\n\t\tPLTFM_MEMCPY(data, state->data, *size);\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * psd_88xx() - trigger fw psd\n * @adapter : the adapter of halmac\n * @start_psd : start PSD\n * @end_psd : end PSD\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\npsd_88xx(struct halmac_adapter *adapter, u16 start_psd, u16 end_psd)\n{\n\tu8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };\n\tu16 seq_num = 0;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tstruct halmac_h2c_header_info hdr_info;\n\tenum halmac_cmd_process_status *proc_status;\n\n\tproc_status = &adapter->halmac_state.psd_state.proc_status;\n\n\tif (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_NO_DLFW;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (*proc_status == HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_TRACE(\"[TRACE]Wait event(psd)\\n\");\n\t\treturn HALMAC_RET_BUSY_STATE;\n\t}\n\n\tif (adapter->halmac_state.psd_state.data) {\n\t\tPLTFM_FREE(adapter->halmac_state.psd_state.data,\n\t\t\t   adapter->halmac_state.psd_state.data_size);\n\t\tadapter->halmac_state.psd_state.data = (u8 *)NULL;\n\t}\n\n\tadapter->halmac_state.psd_state.data_size = 0;\n\tadapter->halmac_state.psd_state.seg_size = 0;\n\n\t*proc_status = HALMAC_CMD_PROCESS_SENDING;\n\n\tPSD_SET_START_PSD(h2c_buf, start_psd);\n\tPSD_SET_END_PSD(h2c_buf, end_psd);\n\n\thdr_info.sub_cmd_id = SUB_CMD_ID_PSD;\n\thdr_info.content_size = 4;\n\thdr_info.ack = 1;\n\tset_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);\n\n\tstatus = send_h2c_pkt_88xx(adapter, h2c_buf);\n\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]send h2c pkt fail!!\\n\");\n\t\treset_ofld_feature_88xx(adapter, HALMAC_FEATURE_PSD);\n\t\treturn status;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nget_h2c_ack_iqk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)\n{\n\tu8 seq_num;\n\tu8 fw_rc;\n\tstruct halmac_iqk_state *state = &adapter->halmac_state.iqk_state;\n\tenum halmac_cmd_process_status proc_status;\n\n\tseq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);\n\tPLTFM_MSG_TRACE(\"[TRACE]Seq num : h2c->%d c2h->%d\\n\",\n\t\t\tstate->seq_num, seq_num);\n\tif (seq_num != state->seq_num) {\n\t\tPLTFM_MSG_ERR(\"[ERR]Seq num mismatch : h2c->%d c2h->%d\\n\",\n\t\t\t      state->seq_num, seq_num);\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tif (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_ERR(\"[ERR]not cmd sending\\n\");\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tfw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);\n\tstate->fw_rc = fw_rc;\n\n\tif ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {\n\t\tproc_status = HALMAC_CMD_PROCESS_DONE;\n\t\tstate->proc_status = proc_status;\n\t\tPLTFM_EVENT_SIG(HALMAC_FEATURE_IQK, proc_status, NULL, 0);\n\t} else {\n\t\tproc_status = HALMAC_CMD_PROCESS_ERROR;\n\t\tstate->proc_status = proc_status;\n\t\tPLTFM_EVENT_SIG(HALMAC_FEATURE_IQK, proc_status, &fw_rc, 1);\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nget_h2c_ack_pwr_trk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)\n{\n\tu8 seq_num;\n\tu8 fw_rc;\n\tstruct halmac_pwr_tracking_state *state;\n\tenum halmac_cmd_process_status proc_status;\n\n\tstate = &adapter->halmac_state.pwr_trk_state;\n\n\tseq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);\n\tPLTFM_MSG_TRACE(\"[TRACE]Seq num : h2c->%d c2h->%d\\n\",\n\t\t\tstate->seq_num, seq_num);\n\tif (seq_num != state->seq_num) {\n\t\tPLTFM_MSG_ERR(\"[ERR]Seq num mismatch : h2c->%d c2h->%d\\n\",\n\t\t\t      state->seq_num, seq_num);\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tif (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_ERR(\"[ERR]not cmd sending\\n\");\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tfw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);\n\tstate->fw_rc = fw_rc;\n\n\tif ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {\n\t\tproc_status = HALMAC_CMD_PROCESS_DONE;\n\t\tstate->proc_status = proc_status;\n\t\tPLTFM_EVENT_SIG(HALMAC_FEATURE_POWER_TRACKING, proc_status,\n\t\t\t\tNULL, 0);\n\t} else {\n\t\tproc_status = HALMAC_CMD_PROCESS_ERROR;\n\t\tstate->proc_status = proc_status;\n\t\tPLTFM_EVENT_SIG(HALMAC_FEATURE_POWER_TRACKING, proc_status,\n\t\t\t\t&fw_rc, 1);\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nget_psd_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)\n{\n\tu8 seg_id;\n\tu8 seg_size;\n\tu8 seq_num;\n\tu16 total_size;\n\tenum halmac_cmd_process_status proc_status;\n\tstruct halmac_psd_state *state = &adapter->halmac_state.psd_state;\n\n\tseq_num = (u8)PSD_DATA_GET_H2C_SEQ(buf);\n\tPLTFM_MSG_TRACE(\"[TRACE]seq num : h2c->%d c2h->%d\\n\",\n\t\t\tstate->seq_num, seq_num);\n\tif (seq_num != state->seq_num) {\n\t\tPLTFM_MSG_ERR(\"[ERR]seq num mismatch : h2c->%d c2h->%d\\n\",\n\t\t\t      state->seq_num, seq_num);\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tif (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_ERR(\"[ERR]not cmd sending\\n\");\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\ttotal_size = (u16)PSD_DATA_GET_TOTAL_SIZE(buf);\n\tseg_id = (u8)PSD_DATA_GET_SEGMENT_ID(buf);\n\tseg_size = (u8)PSD_DATA_GET_SEGMENT_SIZE(buf);\n\tstate->data_size = total_size;\n\n\tif (!state->data)\n\t\tstate->data = (u8 *)PLTFM_MALLOC(state->data_size);\n\n\tif (seg_id == 0)\n\t\tstate->seg_size = seg_size;\n\n\tPLTFM_MEMCPY(state->data + seg_id * state->seg_size,\n\t\t     buf + C2H_DATA_OFFSET_88XX, seg_size);\n\n\tif (PSD_DATA_GET_END_SEGMENT(buf) == 0)\n\t\treturn HALMAC_RET_SUCCESS;\n\n\tproc_status = HALMAC_CMD_PROCESS_DONE;\n\tstate->proc_status = proc_status;\n\n\tPLTFM_EVENT_SIG(HALMAC_FEATURE_PSD, proc_status, state->data,\n\t\t\tstate->data_size);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n#endif /* HALMAC_88XX_SUPPORT */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_BB_RF_88XX_H_\n#define _HALMAC_BB_RF_88XX_H_\n\n#include \"../halmac_api.h\"\n\n#if HALMAC_88XX_SUPPORT\n\nenum halmac_ret_status\nstart_iqk_88xx(struct halmac_adapter *adapter, struct halmac_iqk_para *param);\n\nenum halmac_ret_status\nctrl_pwr_tracking_88xx(struct halmac_adapter *adapter,\n\t\t       struct halmac_pwr_tracking_option *opt);\n\nenum halmac_ret_status\nget_iqk_status_88xx(struct halmac_adapter *adapter,\n\t\t    enum halmac_cmd_process_status *proc_status);\n\nenum halmac_ret_status\nget_pwr_trk_status_88xx(struct halmac_adapter *adapter,\n\t\t\tenum halmac_cmd_process_status *proc_status);\n\nenum halmac_ret_status\nget_psd_status_88xx(struct halmac_adapter *adapter,\n\t\t    enum halmac_cmd_process_status *proc_status, u8 *data,\n\t\t    u32 *size);\n\nenum halmac_ret_status\npsd_88xx(struct halmac_adapter *adapter, u16 start_psd, u16 end_psd);\n\nenum halmac_ret_status\nget_h2c_ack_iqk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\nenum halmac_ret_status\nget_h2c_ack_pwr_trk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\nenum halmac_ret_status\nget_psd_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\n#endif /* HALMAC_88XX_SUPPORT */\n\n#endif/* _HALMAC_BB_RF_88XX_H_ */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"halmac_cfg_wmac_88xx.h\"\n#include \"halmac_88xx_cfg.h\"\n#include \"halmac_efuse_88xx.h\"\n\n#if HALMAC_88XX_SUPPORT\n\n#define MAC_CLK_SPEED\t80 /* 80M */\n#define EFUSE_PCB_INFO_OFFSET\t0xCA\n\nenum mac_clock_hw_def {\n\tMAC_CLK_HW_DEF_80M = 0,\n\tMAC_CLK_HW_DEF_40M = 1,\n\tMAC_CLK_HW_DEF_20M = 2,\n};\n\nstatic enum halmac_ret_status\nboard_rf_fine_tune_88xx(struct halmac_adapter *adapter);\n\n/**\n * cfg_mac_addr_88xx() - config mac address\n * @adapter : the adapter of halmac\n * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4\n * @addr : mac address\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,\n\t\t  union halmac_wlan_addr *addr)\n{\n\tu32 offset;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (port >= HALMAC_PORTID_NUM) {\n\t\tPLTFM_MSG_ERR(\"[ERR]port index >= 5\\n\");\n\t\treturn HALMAC_RET_PORT_NOT_SUPPORT;\n\t}\n\n\tswitch (port) {\n\tcase HALMAC_PORTID0:\n\t\toffset = REG_MACID;\n\t\tbreak;\n\tcase HALMAC_PORTID1:\n\t\toffset = REG_MACID1;\n\t\tbreak;\n\tcase HALMAC_PORTID2:\n\t\toffset = REG_MACID2;\n\t\tbreak;\n\tcase HALMAC_PORTID3:\n\t\toffset = REG_MACID3;\n\t\tbreak;\n\tcase HALMAC_PORTID4:\n\t\toffset = REG_MACID4;\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_PORT_NOT_SUPPORT;\n\t}\n\n\tHALMAC_REG_W32(offset, rtk_le32_to_cpu(addr->addr_l_h.low));\n\tHALMAC_REG_W16(offset + 4, rtk_le16_to_cpu(addr->addr_l_h.high));\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfg_bssid_88xx() - config BSSID\n * @adapter : the adapter of halmac\n * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4\n * @addr : bssid\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_bssid_88xx(struct halmac_adapter *adapter, u8 port,\n\t       union halmac_wlan_addr *addr)\n{\n\tu32 offset;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (port >= HALMAC_PORTID_NUM) {\n\t\tPLTFM_MSG_ERR(\"[ERR]port index > 5\\n\");\n\t\treturn HALMAC_RET_PORT_NOT_SUPPORT;\n\t}\n\n\tswitch (port) {\n\tcase HALMAC_PORTID0:\n\t\toffset = REG_BSSID;\n\t\tbreak;\n\tcase HALMAC_PORTID1:\n\t\toffset = REG_BSSID1;\n\t\tbreak;\n\tcase HALMAC_PORTID2:\n\t\toffset = REG_BSSID2;\n\t\tbreak;\n\tcase HALMAC_PORTID3:\n\t\toffset = REG_BSSID3;\n\t\tbreak;\n\tcase HALMAC_PORTID4:\n\t\toffset = REG_BSSID4;\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_PORT_NOT_SUPPORT;\n\t}\n\n\tHALMAC_REG_W32(offset, rtk_le32_to_cpu(addr->addr_l_h.low));\n\tHALMAC_REG_W16(offset + 4, rtk_le16_to_cpu(addr->addr_l_h.high));\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfg_transmitter_addr_88xx() - config transmitter address\n * @adapter : the adapter of halmac\n * @port :  0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4\n * @addr :\n * Author : Alan\n * Return : enum halmac_ret_status\n */\nenum halmac_ret_status\ncfg_transmitter_addr_88xx(struct halmac_adapter *adapter, u8 port,\n\t\t\t  union halmac_wlan_addr *addr)\n{\n\tu32 offset;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (port >= HALMAC_PORTID_NUM) {\n\t\tPLTFM_MSG_ERR(\"[ERR]port index > 5\\n\");\n\t\treturn HALMAC_RET_PORT_NOT_SUPPORT;\n\t}\n\n\tswitch (port) {\n\tcase HALMAC_PORTID0:\n\t\toffset = REG_TRANSMIT_ADDRSS_0;\n\t\tbreak;\n\tcase HALMAC_PORTID1:\n\t\toffset = REG_TRANSMIT_ADDRSS_1;\n\t\tbreak;\n\tcase HALMAC_PORTID2:\n\t\toffset = REG_TRANSMIT_ADDRSS_2;\n\t\tbreak;\n\tcase HALMAC_PORTID3:\n\t\toffset = REG_TRANSMIT_ADDRSS_3;\n\t\tbreak;\n\tcase HALMAC_PORTID4:\n\t\toffset = REG_TRANSMIT_ADDRSS_4;\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_PORT_NOT_SUPPORT;\n\t}\n\n\tHALMAC_REG_W32(offset, rtk_le32_to_cpu(addr->addr_l_h.low));\n\tHALMAC_REG_W16(offset + 4, rtk_le16_to_cpu(addr->addr_l_h.high));\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfg_net_type_88xx() - config network type\n * @adapter : the adapter of halmac\n * @port :  0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4\n * @addr : mac address\n * Author : Alan\n * Return : enum halmac_ret_status\n */\nenum halmac_ret_status\ncfg_net_type_88xx(struct halmac_adapter *adapter, u8 port,\n\t\t  enum halmac_network_type_select net_type)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tu8 value8 = 0;\n\tu8 net_type_tmp = 0;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (net_type == HALMAC_NETWORK_AP) {\n\t\tif (port >= HALMAC_PORTID1) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]AP port > 1\\n\");\n\t\t\treturn HALMAC_RET_PORT_NOT_SUPPORT;\n\t\t}\n\t}\n\n\tswitch (port) {\n\tcase HALMAC_PORTID0:\n\t\tnet_type_tmp = net_type;\n\t\tvalue8 = ((HALMAC_REG_R8(REG_CR + 2) & 0xFC) | net_type_tmp);\n\t\tHALMAC_REG_W8(REG_CR + 2, value8);\n\t\tbreak;\n\tcase HALMAC_PORTID1:\n\t\tnet_type_tmp = (net_type << 2);\n\t\tvalue8 = ((HALMAC_REG_R8(REG_CR + 2) & 0xF3) | net_type_tmp);\n\t\tHALMAC_REG_W8(REG_CR + 2, value8);\n\t\tbreak;\n\tcase HALMAC_PORTID2:\n\t\tnet_type_tmp = net_type;\n\t\tvalue8 = ((HALMAC_REG_R8(REG_CR_EXT) & 0xFC) | net_type_tmp);\n\t\tHALMAC_REG_W8(REG_CR_EXT, value8);\n\t\tbreak;\n\tcase HALMAC_PORTID3:\n\t\tnet_type_tmp = (net_type << 2);\n\t\tvalue8 = ((HALMAC_REG_R8(REG_CR_EXT) & 0xF3) | net_type_tmp);\n\t\tHALMAC_REG_W8(REG_CR_EXT, value8);\n\t\tbreak;\n\tcase HALMAC_PORTID4:\n\t\tnet_type_tmp = (net_type << 4);\n\t\tvalue8 = ((HALMAC_REG_R8(REG_CR_EXT) & 0xCF) | net_type_tmp);\n\t\tHALMAC_REG_W8(REG_CR_EXT, value8);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfg_tsf_rst_88xx() - tsf reset\n * @adapter : the adapter of halmac\n * @port :  0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4\n * Author : Alan\n * Return : enum halmac_ret_status\n */\nenum halmac_ret_status\ncfg_tsf_rst_88xx(struct halmac_adapter *adapter, u8 port)\n{\n\tu8 tsf_rst = 0;\n\tu8 value8;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tswitch (port) {\n\tcase HALMAC_PORTID0:\n\t\ttsf_rst = BIT_TSFTR_RST;\n\t\tbreak;\n\tcase HALMAC_PORTID1:\n\t\ttsf_rst = BIT_TSFTR_CLI0_RST;\n\t\tbreak;\n\tcase HALMAC_PORTID2:\n\t\ttsf_rst = BIT_TSFTR_CLI1_RST;\n\t\tbreak;\n\tcase HALMAC_PORTID3:\n\t\ttsf_rst = BIT_TSFTR_CLI2_RST;\n\t\tbreak;\n\tcase HALMAC_PORTID4:\n\t\ttsf_rst = BIT_TSFTR_CLI3_RST;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tvalue8 = HALMAC_REG_R8(REG_DUAL_TSF_RST);\n\tHALMAC_REG_W8(REG_DUAL_TSF_RST, value8 | tsf_rst);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfg_bcn_space_88xx() - config beacon space\n * @adapter : the adapter of halmac\n * @port :  0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4\n * @bcn_space : beacon space\n * Author : Alan\n * Return : enum halmac_ret_status\n */\nenum halmac_ret_status\ncfg_bcn_space_88xx(struct halmac_adapter *adapter, u8 port, u32 bcn_space)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tu16 bcn_space_real = 0;\n\tu16 value16 = 0;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tbcn_space_real = ((u16)bcn_space);\n\n\tswitch (port) {\n\tcase HALMAC_PORTID0:\n\t\tHALMAC_REG_W16(REG_MBSSID_BCN_SPACE, bcn_space_real);\n\t\tbreak;\n\tcase HALMAC_PORTID1:\n\t\tvalue16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE + 2) & 0xF000;\n\t\tvalue16 |= bcn_space_real;\n\t\tHALMAC_REG_W16(REG_MBSSID_BCN_SPACE + 2, value16);\n\t\tbreak;\n\tcase HALMAC_PORTID2:\n\t\tvalue16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE2) & 0xF000;\n\t\tvalue16 |= bcn_space_real;\n\t\tHALMAC_REG_W16(REG_MBSSID_BCN_SPACE2, value16);\n\t\tbreak;\n\tcase HALMAC_PORTID3:\n\t\tvalue16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE2 + 2) & 0xF000;\n\t\tvalue16 |= bcn_space_real;\n\t\tHALMAC_REG_W16(REG_MBSSID_BCN_SPACE2 + 2, value16);\n\t\tbreak;\n\tcase HALMAC_PORTID4:\n\t\tvalue16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE3) & 0xF000;\n\t\tvalue16 |= bcn_space_real;\n\t\tHALMAC_REG_W16(REG_MBSSID_BCN_SPACE3, value16);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * rw_bcn_ctrl_88xx() - r/w beacon control\n * @adapter : the adapter of halmac\n * @port :  0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4\n * @write_en : 1->write beacon function 0->read beacon function\n * @pBcn_ctrl : beacon control info\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n */\nenum halmac_ret_status\nrw_bcn_ctrl_88xx(struct halmac_adapter *adapter, u8 port, u8 write_en,\n\t\t struct halmac_bcn_ctrl *ctrl)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tu8 ctrl_value = 0;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (write_en) {\n\t\tif (ctrl->dis_rx_bssid_fit == 1)\n\t\t\tctrl_value |= BIT_DIS_RX_BSSID_FIT;\n\n\t\tif (ctrl->en_txbcn_rpt == 1)\n\t\t\tctrl_value |= BIT_P0_EN_TXBCN_RPT;\n\n\t\tif (ctrl->dis_tsf_udt == 1)\n\t\t\tctrl_value |= BIT_DIS_TSF_UDT;\n\n\t\tif (ctrl->en_bcn == 1)\n\t\t\tctrl_value |= BIT_EN_BCN_FUNCTION;\n\n\t\tif (ctrl->en_rxbcn_rpt == 1)\n\t\t\tctrl_value |= BIT_P0_EN_RXBCN_RPT;\n\n\t\tif (ctrl->en_p2p_ctwin == 1)\n\t\t\tctrl_value |= BIT_EN_P2P_CTWINDOW;\n\n\t\tif (ctrl->en_p2p_bcn_area == 1)\n\t\t\tctrl_value |= BIT_EN_P2P_BCNQ_AREA;\n\n\t\tswitch (port) {\n\t\tcase HALMAC_PORTID0:\n\t\t\tHALMAC_REG_W8(REG_BCN_CTRL, ctrl_value);\n\t\t\tbreak;\n\t\tcase HALMAC_PORTID1:\n\t\t\tHALMAC_REG_W8(REG_BCN_CTRL_CLINT0, ctrl_value);\n\t\t\tbreak;\n\t\tcase HALMAC_PORTID2:\n\t\t\tHALMAC_REG_W8(REG_BCN_CTRL_CLINT1, ctrl_value);\n\t\t\tbreak;\n\t\tcase HALMAC_PORTID3:\n\t\t\tHALMAC_REG_W8(REG_BCN_CTRL_CLINT2, ctrl_value);\n\t\t\tbreak;\n\t\tcase HALMAC_PORTID4:\n\t\t\tHALMAC_REG_W8(REG_BCN_CTRL_CLINT3, ctrl_value);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t} else {\n\t\tswitch (port) {\n\t\tcase HALMAC_PORTID0:\n\t\t\tctrl_value = HALMAC_REG_R8(REG_BCN_CTRL);\n\t\t\tbreak;\n\t\tcase HALMAC_PORTID1:\n\t\t\tctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT0);\n\t\t\tbreak;\n\t\tcase HALMAC_PORTID2:\n\t\t\tctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT1);\n\t\t\tbreak;\n\t\tcase HALMAC_PORTID3:\n\t\t\tctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT2);\n\t\t\tbreak;\n\t\tcase HALMAC_PORTID4:\n\t\t\tctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT3);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tif (ctrl_value & BIT_EN_P2P_BCNQ_AREA)\n\t\t\tctrl->en_p2p_bcn_area = 1;\n\t\telse\n\t\t\tctrl->en_p2p_bcn_area = 0;\n\n\t\tif (ctrl_value & BIT_EN_P2P_CTWINDOW)\n\t\t\tctrl->en_p2p_ctwin = 1;\n\t\telse\n\t\t\tctrl->en_p2p_ctwin = 0;\n\n\t\tif (ctrl_value & BIT_P0_EN_RXBCN_RPT)\n\t\t\tctrl->en_rxbcn_rpt = 1;\n\t\telse\n\t\t\tctrl->en_rxbcn_rpt = 0;\n\n\t\tif (ctrl_value & BIT_EN_BCN_FUNCTION)\n\t\t\tctrl->en_bcn = 1;\n\t\telse\n\t\t\tctrl->en_bcn = 0;\n\n\t\tif (ctrl_value & BIT_DIS_TSF_UDT)\n\t\t\tctrl->dis_tsf_udt = 1;\n\t\telse\n\t\t\tctrl->dis_tsf_udt = 0;\n\n\t\tif (ctrl_value & BIT_P0_EN_TXBCN_RPT)\n\t\t\tctrl->en_txbcn_rpt = 1;\n\t\telse\n\t\t\tctrl->en_txbcn_rpt = 0;\n\n\t\tif (ctrl_value & BIT_DIS_RX_BSSID_FIT)\n\t\t\tctrl->dis_rx_bssid_fit = 1;\n\t\telse\n\t\t\tctrl->dis_rx_bssid_fit = 0;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfg_multicast_addr_88xx() - config multicast address\n * @adapter : the adapter of halmac\n * @addr : multicast address\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_multicast_addr_88xx(struct halmac_adapter *adapter,\n\t\t\tunion halmac_wlan_addr *addr)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tHALMAC_REG_W32(REG_MAR, rtk_le32_to_cpu(addr->addr_l_h.low));\n\tHALMAC_REG_W16(REG_MAR + 4, rtk_le16_to_cpu(addr->addr_l_h.high));\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfg_operation_mode_88xx() - config operation mode\n * @adapter : the adapter of halmac\n * @mode : 802.11 standard(b/g/n/ac)\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_operation_mode_88xx(struct halmac_adapter *adapter,\n\t\t\tenum halmac_wireless_mode mode)\n{\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfg_ch_bw_88xx() - config channel & bandwidth\n * @adapter : the adapter of halmac\n * @ch : WLAN channel, support 2.4G & 5G\n * @idx : primary channel index, idx1, idx2, idx3, idx4\n * @bw : band width, 20, 40, 80, 160, 5 ,10\n * Author : KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_ch_bw_88xx(struct halmac_adapter *adapter, u8 ch,\n\t       enum halmac_pri_ch_idx idx, enum halmac_bw bw)\n{\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tcfg_pri_ch_idx_88xx(adapter, idx);\n\tcfg_bw_88xx(adapter, bw);\n\tcfg_ch_88xx(adapter, ch);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\ncfg_ch_88xx(struct halmac_adapter *adapter, u8 ch)\n{\n\tu8 value8;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tvalue8 = HALMAC_REG_R8(REG_CCK_CHECK);\n\tvalue8 = value8 & (~(BIT(7)));\n\n\tif (ch > 35)\n\t\tvalue8 = value8 | BIT(7);\n\n\tHALMAC_REG_W8(REG_CCK_CHECK, value8);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\ncfg_pri_ch_idx_88xx(struct halmac_adapter *adapter, enum halmac_pri_ch_idx idx)\n{\n\tu8 txsc40 = 0, txsc20 = 0;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\ttxsc20 = idx;\n\tif (txsc20 == HALMAC_CH_IDX_1 || txsc20 == HALMAC_CH_IDX_3)\n\t\ttxsc40 = 9;\n\telse\n\t\ttxsc40 = 10;\n\n\tHALMAC_REG_W8(REG_DATA_SC, BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40));\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfg_bw_88xx() - config bandwidth\n * @adapter : the adapter of halmac\n * @bw : band width, 20, 40, 80, 160, 5 ,10\n * Author : KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw)\n{\n\tu32 value32;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tvalue32 = HALMAC_REG_R32(REG_WMAC_TRXPTCL_CTL);\n\tvalue32 = value32 & (~(BIT(7) | BIT(8)));\n\n\tswitch (bw) {\n\tcase HALMAC_BW_80:\n\t\tvalue32 |= BIT(8);\n\t\tbreak;\n\tcase HALMAC_BW_40:\n\t\tvalue32 |= BIT(7);\n\t\tbreak;\n\tcase HALMAC_BW_20:\n\tcase HALMAC_BW_10:\n\tcase HALMAC_BW_5:\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tHALMAC_REG_W32(REG_WMAC_TRXPTCL_CTL, value32);\n\n\tcfg_mac_clk_88xx(adapter);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nvoid\ncfg_txfifo_lt_88xx(struct halmac_adapter *adapter,\n\t\t   struct halmac_txfifo_lifetime_cfg *cfg)\n{\n\tu8 value8;\n\tu32 value32;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tif (cfg->enable == 1) {\n\t\tvalue8 = HALMAC_REG_R8(REG_LIFETIME_EN);\n\t\tvalue8 = value8 | BIT(0) | BIT(1) | BIT(2) | BIT(3);\n\t\tHALMAC_REG_W8(REG_LIFETIME_EN, value8);\n\n\t\tvalue32 = (cfg->lifetime) >> 8;\n\t\tvalue32 = value32 + (value32 << 16);\n\t\tHALMAC_REG_W32(REG_PKT_LIFE_TIME, value32);\n\t} else {\n\t\tvalue8 = HALMAC_REG_R8(REG_LIFETIME_EN);\n\t\tvalue8 = value8 & (~(BIT(0) | BIT(1) | BIT(2) | BIT(3)));\n\t\tHALMAC_REG_W8(REG_LIFETIME_EN, value8);\n\t}\n}\n\nenum halmac_ret_status\nenable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable)\n{\n\tu8 value8;\n\tu32 value32;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tif (enable == 1) {\n\t\tstatus = board_rf_fine_tune_88xx(adapter);\n\t\tvalue8 = HALMAC_REG_R8(REG_SYS_FUNC_EN);\n\t\tvalue8 = value8 | BIT(0) | BIT(1);\n\t\tHALMAC_REG_W8(REG_SYS_FUNC_EN, value8);\n\n\t\tvalue8 = HALMAC_REG_R8(REG_RF_CTRL);\n\t\tvalue8 = value8 | BIT(0) | BIT(1) | BIT(2);\n\t\tHALMAC_REG_W8(REG_RF_CTRL, value8);\n\n\t\tvalue32 = HALMAC_REG_R32(REG_WLRF1);\n\t\tvalue32 = value32 | BIT(24) | BIT(25) | BIT(26);\n\t\tHALMAC_REG_W32(REG_WLRF1, value32);\n\t} else {\n\t\tvalue8 = HALMAC_REG_R8(REG_SYS_FUNC_EN);\n\t\tvalue8 = value8 & (~(BIT(0) | BIT(1)));\n\t\tHALMAC_REG_W8(REG_SYS_FUNC_EN, value8);\n\n\t\tvalue8 = HALMAC_REG_R8(REG_RF_CTRL);\n\t\tvalue8 = value8 & (~(BIT(0) | BIT(1) | BIT(2)));\n\t\tHALMAC_REG_W8(REG_RF_CTRL, value8);\n\n\t\tvalue32 = HALMAC_REG_R32(REG_WLRF1);\n\t\tvalue32 = value32 & (~(BIT(24) | BIT(25) | BIT(26)));\n\t\tHALMAC_REG_W32(REG_WLRF1, value32);\n\t}\n\n\treturn status;\n}\n\nstatic enum halmac_ret_status\nboard_rf_fine_tune_88xx(struct halmac_adapter *adapter)\n{\n\tu8 *map = NULL;\n\tu32 size = adapter->hw_cfg_info.eeprom_size;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tif (adapter->chip_id == HALMAC_CHIP_ID_8822B) {\n\t\tif (!adapter->efuse_map_valid || !adapter->efuse_map) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]efuse map invalid!!\\n\");\n\t\t\treturn HALMAC_RET_EFUSE_R_FAIL;\n\t\t}\n\n\t\tmap = (u8 *)PLTFM_MALLOC(size);\n\t\tif (!map) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]malloc map\\n\");\n\t\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t\t}\n\n\t\tPLTFM_MEMSET(map, 0xFF, size);\n\n\t\tif (eeprom_parser_88xx(adapter, adapter->efuse_map, map) !=\n\t\t    HALMAC_RET_SUCCESS) {\n\t\t\tPLTFM_FREE(map, size);\n\t\t\treturn HALMAC_RET_EEPROM_PARSING_FAIL;\n\t\t}\n\n\t\t/* Fine-tune XTAL voltage for 2L PCB board */\n\t\tif (*(map + EFUSE_PCB_INFO_OFFSET) == 0x0C)\n\t\t\tHALMAC_REG_W8_SET(REG_AFE_CTRL1 + 1, BIT(1));\n\n\t\tPLTFM_FREE(map, size);\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nvoid\ncfg_mac_clk_88xx(struct halmac_adapter *adapter)\n{\n\tu32 value32;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tvalue32 = HALMAC_REG_R32(REG_AFE_CTRL1) & ~(BIT(20) | BIT(21));\n\tvalue32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL);\n\tHALMAC_REG_W32(REG_AFE_CTRL1, value32);\n\n\tHALMAC_REG_W8(REG_USTIME_TSF, MAC_CLK_SPEED);\n\tHALMAC_REG_W8(REG_USTIME_EDCA, MAC_CLK_SPEED);\n}\n\n/**\n * cfg_la_mode_88xx() - config la mode\n * @adapter : the adapter of halmac\n * @mode :\n *\tdisable : no TXFF space reserved for LA debug\n *\tpartial : partial TXFF space is reserved for LA debug\n *\tfull : all TXFF space is reserved for LA debug\n * Author : KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_la_mode_88xx(struct halmac_adapter *adapter, enum halmac_la_mode mode)\n{\n\tif (adapter->api_registry.la_mode_en == 0)\n\t\treturn HALMAC_RET_NOT_SUPPORT;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tadapter->txff_alloc.la_mode = mode;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfg_rxfifo_expand_mode_88xx() - rx fifo expanding\n * @adapter : the adapter of halmac\n * @mode :\n *\tdisable : normal mode\n *\t1 block : Rx FIFO + 1 FIFO block; Tx fifo - 1 FIFO block\n *\t2 block : Rx FIFO + 2 FIFO block; Tx fifo - 2 FIFO block\n *\t3 block : Rx FIFO + 3 FIFO block; Tx fifo - 3 FIFO block\n * Author : Soar\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_rxfifo_expand_mode_88xx(struct halmac_adapter *adapter,\n\t\t\t    enum halmac_rx_fifo_expanding_mode mode)\n{\n\tif (adapter->api_registry.rx_exp_en == 0)\n\t\treturn HALMAC_RET_NOT_SUPPORT;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tadapter->txff_alloc.rx_fifo_exp_mode = mode;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nconfig_security_88xx(struct halmac_adapter *adapter,\n\t\t     struct halmac_security_setting *setting)\n{\n\tu8 sec_cfg;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tHALMAC_REG_W16_SET(REG_CR, BIT_MAC_SEC_EN);\n\n\tif (setting->compare_keyid == 1) {\n\t\tHALMAC_REG_W8_SET(REG_SECCFG + 1, BIT(0));\n\t\tadapter->hw_cfg_info.chk_security_keyid = 1;\n\t} else {\n\t\tadapter->hw_cfg_info.chk_security_keyid = 0;\n\t}\n\n\tsec_cfg = HALMAC_REG_R8(REG_SECCFG);\n\n\t/* BC/MC uses default key */\n\t/* cam entry 0~3, kei id = 0 -> entry0, kei id = 1 -> entry1... */\n\tsec_cfg |= (BIT_TXBCUSEDK | BIT_RXBCUSEDK);\n\n\tif (setting->tx_encryption == 1)\n\t\tsec_cfg |= BIT_TXENC;\n\telse\n\t\tsec_cfg &= ~BIT_TXENC;\n\n\tif (setting->rx_decryption == 1)\n\t\tsec_cfg |= BIT_RXDEC;\n\telse\n\t\tsec_cfg &= ~BIT_RXDEC;\n\n\tHALMAC_REG_W8(REG_SECCFG, sec_cfg);\n\n\tif (setting->bip_enable == 1) {\n\t\tif (adapter->chip_id == HALMAC_CHIP_ID_8822B)\n\t\t\treturn HALMAC_RET_BIP_NO_SUPPORT;\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\t\tsec_cfg = HALMAC_REG_R8(REG_WSEC_OPTION + 2);\n\n\t\tif (setting->tx_encryption == 1)\n\t\t\tsec_cfg |= (BIT(3) | BIT(5));\n\t\telse\n\t\t\tsec_cfg &= ~(BIT(3) | BIT(5));\n\n\t\tif (setting->rx_decryption == 1)\n\t\t\tsec_cfg |= (BIT(4) | BIT(6));\n\t\telse\n\t\t\tsec_cfg &= ~(BIT(4) | BIT(6));\n\n\t\tHALMAC_REG_W8(REG_WSEC_OPTION + 2, sec_cfg);\n#endif\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nu8\nget_used_cam_entry_num_88xx(struct halmac_adapter *adapter,\n\t\t\t    enum hal_security_type sec_type)\n{\n\tu8 entry_num;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tswitch (sec_type) {\n\tcase HAL_SECURITY_TYPE_WEP40:\n\tcase HAL_SECURITY_TYPE_WEP104:\n\tcase HAL_SECURITY_TYPE_TKIP:\n\tcase HAL_SECURITY_TYPE_AES128:\n\tcase HAL_SECURITY_TYPE_GCMP128:\n\tcase HAL_SECURITY_TYPE_GCMSMS4:\n\tcase HAL_SECURITY_TYPE_BIP:\n\t\tentry_num = 1;\n\t\tbreak;\n\tcase HAL_SECURITY_TYPE_WAPI:\n\tcase HAL_SECURITY_TYPE_AES256:\n\tcase HAL_SECURITY_TYPE_GCMP256:\n\t\tentry_num = 2;\n\t\tbreak;\n\tdefault:\n\t\tentry_num = 0;\n\t\tbreak;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn entry_num;\n}\n\nenum halmac_ret_status\nwrite_cam_88xx(struct halmac_adapter *adapter, u32 idx,\n\t       struct halmac_cam_entry_info *info)\n{\n\tu32 i;\n\tu32 cmd = 0x80010000;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tstruct halmac_cam_entry_format *fmt = NULL;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (idx >= adapter->hw_cfg_info.cam_entry_num)\n\t\treturn HALMAC_RET_ENTRY_INDEX_ERROR;\n\n\tif (info->key_id > 3)\n\t\treturn HALMAC_RET_FAIL;\n\n\tfmt = (struct halmac_cam_entry_format *)PLTFM_MALLOC(sizeof(*fmt));\n\tif (!fmt)\n\t\treturn HALMAC_RET_NULL_POINTER;\n\tPLTFM_MEMSET(fmt, 0x00, sizeof(*fmt));\n\n\tif (adapter->hw_cfg_info.chk_security_keyid == 1)\n\t\tfmt->key_id = info->key_id;\n\tfmt->valid = info->valid;\n\tPLTFM_MEMCPY(fmt->mac_address, info->mac_address, 6);\n\tPLTFM_MEMCPY(fmt->key, info->key, 16);\n\n\tswitch (info->security_type) {\n\tcase HAL_SECURITY_TYPE_NONE:\n\t\tfmt->type = 0;\n\t\tbreak;\n\tcase HAL_SECURITY_TYPE_WEP40:\n\t\tfmt->type = 1;\n\t\tbreak;\n\tcase HAL_SECURITY_TYPE_WEP104:\n\t\tfmt->type = 5;\n\t\tbreak;\n\tcase HAL_SECURITY_TYPE_TKIP:\n\t\tfmt->type = 2;\n\t\tbreak;\n\tcase HAL_SECURITY_TYPE_AES128:\n\t\tfmt->type = 4;\n\t\tbreak;\n\tcase HAL_SECURITY_TYPE_WAPI:\n\t\tfmt->type = 6;\n\t\tbreak;\n\tcase HAL_SECURITY_TYPE_AES256:\n\t\tfmt->type = 4;\n\t\tfmt->ext_sectype = 1;\n\t\tbreak;\n\tcase HAL_SECURITY_TYPE_GCMP128:\n\t\tfmt->type = 7;\n\t\tbreak;\n\tcase HAL_SECURITY_TYPE_GCMP256:\n\tcase HAL_SECURITY_TYPE_GCMSMS4:\n\t\tfmt->type = 7;\n\t\tfmt->ext_sectype = 1;\n\t\tbreak;\n\tcase HAL_SECURITY_TYPE_BIP:\n\t\tfmt->type = (info->unicast == 1) ? 4 : 0;\n\t\tfmt->mgnt = 1;\n\t\tfmt->grp = (info->unicast == 1) ? 0 : 1;\n\t\tbreak;\n\tdefault:\n\t\tPLTFM_FREE(fmt, sizeof(*fmt));\n\t\treturn HALMAC_RET_FAIL;\n\t}\n\n\tfor (i = 0; i < 8; i++) {\n\t\tHALMAC_REG_W32(REG_CAMWRITE, *((u32 *)fmt + i));\n\t\tHALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i));\n\t}\n\n\tif (info->security_type == HAL_SECURITY_TYPE_WAPI ||\n\t    info->security_type == HAL_SECURITY_TYPE_AES256 ||\n\t    info->security_type == HAL_SECURITY_TYPE_GCMP256 ||\n\t    info->security_type == HAL_SECURITY_TYPE_GCMSMS4) {\n\t\tfmt->mic = 1;\n\t\tPLTFM_MEMCPY(fmt->key, info->key_ext, 16);\n\t\tidx++;\n\t\tfor (i = 0; i < 8; i++) {\n\t\t\tHALMAC_REG_W32(REG_CAMWRITE, *((u32 *)fmt + i));\n\t\t\tHALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i));\n\t\t}\n\t}\n\n\tPLTFM_FREE(fmt, sizeof(*fmt));\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nread_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx,\n\t\t    struct halmac_cam_entry_format *content)\n{\n\tu32 i;\n\tu32 cmd = 0x80000000;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (idx >= adapter->hw_cfg_info.cam_entry_num)\n\t\treturn HALMAC_RET_ENTRY_INDEX_ERROR;\n\n\tfor (i = 0; i < 8; i++) {\n\t\tHALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i));\n\t\t*((u32 *)content + i) = HALMAC_REG_R32(REG_CAMREAD);\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nclear_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx)\n{\n\tu32 i;\n\tu32 cmd = 0x80010000;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tstruct halmac_cam_entry_format *fmt = NULL;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (idx >= adapter->hw_cfg_info.cam_entry_num)\n\t\treturn HALMAC_RET_ENTRY_INDEX_ERROR;\n\n\tfmt = (struct halmac_cam_entry_format *)PLTFM_MALLOC(sizeof(*fmt));\n\tif (!fmt)\n\t\treturn HALMAC_RET_NULL_POINTER;\n\tPLTFM_MEMSET(fmt, 0x00, sizeof(*fmt));\n\n\tfor (i = 0; i < 8; i++) {\n\t\tHALMAC_REG_W32(REG_CAMWRITE, *((u32 *)fmt + i));\n\t\tHALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i));\n\t}\n\n\tPLTFM_FREE(fmt, sizeof(*fmt));\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nvoid\nrx_shift_88xx(struct halmac_adapter *adapter, u8 enable)\n{\n\tu8 value8;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tvalue8 = HALMAC_REG_R8(REG_TXDMA_PQ_MAP);\n\n\tif (enable == 1)\n\t\tHALMAC_REG_W8(REG_TXDMA_PQ_MAP, value8 | BIT(1));\n\telse\n\t\tHALMAC_REG_W8(REG_TXDMA_PQ_MAP, value8 & ~(BIT(1)));\n}\n\n/**\n * cfg_edca_para_88xx() - config edca parameter\n * @adapter : the adapter of halmac\n * @acq_id : VO/VI/BE/BK\n * @param : aifs, cw, txop limit\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_edca_para_88xx(struct halmac_adapter *adapter, enum halmac_acq_id acq_id,\n\t\t   struct halmac_edca_para *param)\n{\n\tu32 offset;\n\tu32 value32;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tswitch (acq_id) {\n\tcase HALMAC_ACQ_ID_VO:\n\t\toffset = REG_EDCA_VO_PARAM;\n\t\tbreak;\n\tcase HALMAC_ACQ_ID_VI:\n\t\toffset = REG_EDCA_VI_PARAM;\n\t\tbreak;\n\tcase HALMAC_ACQ_ID_BE:\n\t\toffset = REG_EDCA_BE_PARAM;\n\t\tbreak;\n\tcase HALMAC_ACQ_ID_BK:\n\t\toffset = REG_EDCA_BK_PARAM;\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_SWITCH_CASE_ERROR;\n\t}\n\n\tparam->txop_limit &= 0x7FF;\n\tvalue32 = (param->aifs) | (param->cw << 8) | (param->txop_limit << 16);\n\n\tHALMAC_REG_W32(offset, value32);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nvoid\nrx_clk_gate_88xx(struct halmac_adapter *adapter, u8 enable)\n{\n\tu8 value8;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tvalue8 = HALMAC_REG_R8(REG_RCR + 2);\n\n\tif (enable == 1)\n\t\tHALMAC_REG_W8(REG_RCR + 2, value8 & ~(BIT(3)));\n\telse\n\t\tHALMAC_REG_W8(REG_RCR + 2, value8 | BIT(3));\n}\n\nenum halmac_ret_status\nrx_cut_amsdu_cfg_88xx(struct halmac_adapter *adapter,\n\t\t      struct halmac_cut_amsdu_cfg *cfg)\n{\n\treturn HALMAC_RET_NOT_SUPPORT;\n}\n\nenum halmac_ret_status\nfast_edca_cfg_88xx(struct halmac_adapter *adapter,\n\t\t   struct halmac_fast_edca_cfg *cfg)\n{\n\tu16 value16;\n\tu32 offset;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tswitch (cfg->acq_id) {\n\tcase HALMAC_ACQ_ID_VO:\n\t\toffset = REG_FAST_EDCA_VOVI_SETTING;\n\t\tbreak;\n\tcase HALMAC_ACQ_ID_VI:\n\t\toffset = REG_FAST_EDCA_VOVI_SETTING + 2;\n\t\tbreak;\n\tcase HALMAC_ACQ_ID_BE:\n\t\toffset = REG_FAST_EDCA_BEBK_SETTING;\n\t\tbreak;\n\tcase HALMAC_ACQ_ID_BK:\n\t\toffset = REG_FAST_EDCA_BEBK_SETTING + 2;\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_SWITCH_CASE_ERROR;\n\t}\n\n\tvalue16 = HALMAC_REG_R16(offset);\n\tvalue16 &= 0xFF;\n\tvalue16 = value16 | (cfg->queue_to << 8);\n\n\tHALMAC_REG_W16(offset, value16);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * get_mac_addr_88xx() - get mac address\n * @adapter : the adapter of halmac\n * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4\n * @addr : mac address\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nget_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,\n\t\t  union halmac_wlan_addr *addr)\n{\n\tu16 mac_addr_h;\n\tu32 mac_addr_l;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (port >= HALMAC_PORTID_NUM) {\n\t\tPLTFM_MSG_ERR(\"[ERR]port index >= 5\\n\");\n\t\treturn HALMAC_RET_PORT_NOT_SUPPORT;\n\t}\n\n\tswitch (port) {\n\tcase HALMAC_PORTID0:\n\t\tmac_addr_l = HALMAC_REG_R32(REG_MACID);\n\t\tmac_addr_h = HALMAC_REG_R16(REG_MACID + 4);\n\t\tbreak;\n\tcase HALMAC_PORTID1:\n\t\tmac_addr_l = HALMAC_REG_R32(REG_MACID1);\n\t\tmac_addr_h = HALMAC_REG_R16(REG_MACID1 + 4);\n\t\tbreak;\n\tcase HALMAC_PORTID2:\n\t\tmac_addr_l = HALMAC_REG_R32(REG_MACID2);\n\t\tmac_addr_h = HALMAC_REG_R16(REG_MACID2 + 4);\n\t\tbreak;\n\tcase HALMAC_PORTID3:\n\t\tmac_addr_l = HALMAC_REG_R32(REG_MACID3);\n\t\tmac_addr_h = HALMAC_REG_R16(REG_MACID3 + 4);\n\t\tbreak;\n\tcase HALMAC_PORTID4:\n\t\tmac_addr_l = HALMAC_REG_R32(REG_MACID4);\n\t\tmac_addr_h = HALMAC_REG_R16(REG_MACID4 + 4);\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_PORT_NOT_SUPPORT;\n\t}\n\n\taddr->addr_l_h.low = rtk_cpu_to_le32(mac_addr_l);\n\taddr->addr_l_h.high = rtk_cpu_to_le16(mac_addr_h);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nvoid\nrts_full_bw_88xx(struct halmac_adapter *adapter, u8 enable)\n{\n\tu8 value8;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tvalue8 = HALMAC_REG_R8(REG_INIRTS_RATE_SEL);\n\n\tif (enable == 1)\n\t\tHALMAC_REG_W8(REG_INIRTS_RATE_SEL, value8 | BIT(5));\n\telse\n\t\tHALMAC_REG_W8(REG_INIRTS_RATE_SEL, value8 & ~(BIT(5)));\n}\n\n#endif /* HALMAC_88XX_SUPPORT */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_CFG_WMAC_88XX_H_\n#define _HALMAC_CFG_WMAC_88XX_H_\n\n#include \"../halmac_api.h\"\n\n#if HALMAC_88XX_SUPPORT\n\nenum halmac_ret_status\ncfg_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,\n\t\t  union halmac_wlan_addr *addr);\n\nenum halmac_ret_status\ncfg_bssid_88xx(struct halmac_adapter *adapter, u8 port,\n\t       union halmac_wlan_addr *addr);\n\nenum halmac_ret_status\ncfg_transmitter_addr_88xx(struct halmac_adapter *adapter, u8 port,\n\t\t\t  union halmac_wlan_addr *addr);\n\nenum halmac_ret_status\ncfg_net_type_88xx(struct halmac_adapter *adapter, u8 port,\n\t\t  enum halmac_network_type_select net_type);\n\nenum halmac_ret_status\ncfg_tsf_rst_88xx(struct halmac_adapter *adapter, u8 port);\n\nenum halmac_ret_status\ncfg_bcn_space_88xx(struct halmac_adapter *adapter, u8 port, u32 bcn_space);\n\nenum halmac_ret_status\nrw_bcn_ctrl_88xx(struct halmac_adapter *adapter, u8 port, u8 write_en,\n\t\t struct halmac_bcn_ctrl *ctrl);\n\nenum halmac_ret_status\ncfg_multicast_addr_88xx(struct halmac_adapter *adapter,\n\t\t\tunion halmac_wlan_addr *addr);\n\nenum halmac_ret_status\ncfg_operation_mode_88xx(struct halmac_adapter *adapter,\n\t\t\tenum halmac_wireless_mode mode);\n\nenum halmac_ret_status\ncfg_ch_bw_88xx(struct halmac_adapter *adapter, u8 ch,\n\t       enum halmac_pri_ch_idx idx, enum halmac_bw bw);\n\nenum halmac_ret_status\ncfg_ch_88xx(struct halmac_adapter *adapter, u8 ch);\n\nenum halmac_ret_status\ncfg_pri_ch_idx_88xx(struct halmac_adapter *adapter, enum halmac_pri_ch_idx idx);\n\nenum halmac_ret_status\ncfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw);\n\nvoid\ncfg_txfifo_lt_88xx(struct halmac_adapter *adapter,\n\t\t   struct halmac_txfifo_lifetime_cfg *cfg);\n\nenum halmac_ret_status\nenable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable);\n\nenum halmac_ret_status\ncfg_la_mode_88xx(struct halmac_adapter *adapter, enum halmac_la_mode mode);\n\nenum halmac_ret_status\ncfg_rxfifo_expand_mode_88xx(struct halmac_adapter *adapter,\n\t\t\t    enum halmac_rx_fifo_expanding_mode mode);\n\nenum halmac_ret_status\nconfig_security_88xx(struct halmac_adapter *adapter,\n\t\t     struct halmac_security_setting *setting);\n\nu8\nget_used_cam_entry_num_88xx(struct halmac_adapter *adapter,\n\t\t\t    enum hal_security_type sec_type);\n\nenum halmac_ret_status\nwrite_cam_88xx(struct halmac_adapter *adapter, u32 idx,\n\t       struct halmac_cam_entry_info *info);\n\nenum halmac_ret_status\nread_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx,\n\t\t    struct halmac_cam_entry_format *content);\n\nenum halmac_ret_status\nclear_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx);\n\nvoid\nrx_shift_88xx(struct halmac_adapter *adapter, u8 enable);\n\nenum halmac_ret_status\ncfg_edca_para_88xx(struct halmac_adapter *adapter, enum halmac_acq_id acq_id,\n\t\t   struct halmac_edca_para *param);\n\nvoid\nrx_clk_gate_88xx(struct halmac_adapter *adapter, u8 enable);\n\nenum halmac_ret_status\nrx_cut_amsdu_cfg_88xx(struct halmac_adapter *adapter,\n\t\t      struct halmac_cut_amsdu_cfg *cfg);\n\nenum halmac_ret_status\nfast_edca_cfg_88xx(struct halmac_adapter *adapter,\n\t\t   struct halmac_fast_edca_cfg *cfg);\n\nenum halmac_ret_status\nget_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,\n\t\t  union halmac_wlan_addr *addr);\n\nvoid\nrts_full_bw_88xx(struct halmac_adapter *adapter, u8 enable);\n\nvoid\ncfg_mac_clk_88xx(struct halmac_adapter *adapter);\n\n#endif/* HALMAC_88XX_SUPPORT */\n\n#endif/* _HALMAC_CFG_WMAC_88XX_H_ */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_common_88xx.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"halmac_common_88xx.h\"\n#include \"halmac_88xx_cfg.h\"\n#include \"halmac_init_88xx.h\"\n#include \"halmac_cfg_wmac_88xx.h\"\n#include \"halmac_efuse_88xx.h\"\n#include \"halmac_bb_rf_88xx.h\"\n#if HALMAC_USB_SUPPORT\n#include \"halmac_usb_88xx.h\"\n#endif\n#if HALMAC_SDIO_SUPPORT\n#include \"halmac_sdio_88xx.h\"\n#endif\n#if HALMAC_PCIE_SUPPORT\n#include \"halmac_pcie_88xx.h\"\n#endif\n#include \"halmac_mimo_88xx.h\"\n\n#if HALMAC_88XX_SUPPORT\n\n#define CFG_PARAM_H2C_INFO_SIZE\t12\n#define ORIGINAL_H2C_CMD_SIZE\t8\n\n#define WLHDR_PROT_VER\t0\n\n#define WLHDR_TYPE_MGMT\t\t0\n#define WLHDR_TYPE_CTRL\t\t1\n#define WLHDR_TYPE_DATA\t\t2\n\n/* mgmt frame */\n#define WLHDR_SUB_TYPE_ASSOC_REQ\t0\n#define WLHDR_SUB_TYPE_ASSOC_RSPNS\t1\n#define WLHDR_SUB_TYPE_REASSOC_REQ\t2\n#define WLHDR_SUB_TYPE_REASSOC_RSPNS\t3\n#define WLHDR_SUB_TYPE_PROBE_REQ\t4\n#define WLHDR_SUB_TYPE_PROBE_RSPNS\t5\n#define WLHDR_SUB_TYPE_BCN\t\t8\n#define WLHDR_SUB_TYPE_DISASSOC\t\t10\n#define WLHDR_SUB_TYPE_AUTH\t\t11\n#define WLHDR_SUB_TYPE_DEAUTH\t\t12\n#define WLHDR_SUB_TYPE_ACTION\t\t13\n#define WLHDR_SUB_TYPE_ACTION_NOACK\t14\n\n/* ctrl frame */\n#define WLHDR_SUB_TYPE_BF_RPT_POLL\t4\n#define WLHDR_SUB_TYPE_NDPA\t\t5\n\n/* data frame */\n#define WLHDR_SUB_TYPE_DATA\t\t0\n#define WLHDR_SUB_TYPE_NULL\t\t4\n#define WLHDR_SUB_TYPE_QOS_DATA\t\t8\n#define WLHDR_SUB_TYPE_QOS_NULL\t\t12\n\n#define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1\n\nstruct wlhdr_frame_ctrl {\n\tu16 protocol:2;\n\tu16 type:2;\n\tu16 sub_type:4;\n\tu16 to_ds:1;\n\tu16 from_ds:1;\n\tu16 more_frag:1;\n\tu16 retry:1;\n\tu16 pwr_mgmt:1;\n\tu16 more_data:1;\n\tu16 protect_frame:1;\n\tu16 order:1;\n};\n\nstatic enum halmac_ret_status\nparse_c2h_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\nstatic enum halmac_ret_status\nget_c2h_dbg_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\nstatic enum halmac_ret_status\nget_h2c_ack_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\nstatic enum halmac_ret_status\nget_scan_rpt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\nstatic enum halmac_ret_status\nget_h2c_ack_cfg_param_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\nstatic enum halmac_ret_status\nget_h2c_ack_update_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\nstatic enum halmac_ret_status\nget_h2c_ack_update_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf,\n\t\t\t\tu32 size);\n\nstatic enum halmac_ret_status\nget_h2c_ack_run_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\nstatic enum halmac_ret_status\nget_h2c_ack_ch_switch_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\nstatic enum halmac_ret_status\nmalloc_cfg_param_buf_88xx(struct halmac_adapter *adapter, u8 full_fifo);\n\nstatic enum halmac_cmd_construct_state\ncfg_param_cmd_cnstr_state_88xx(struct halmac_adapter *adapter);\n\nstatic enum halmac_ret_status\nproc_cfg_param_88xx(struct halmac_adapter *adapter,\n\t\t    struct halmac_phy_parameter_info *param, u8 full_fifo);\n\nstatic enum halmac_ret_status\nsend_cfg_param_h2c_88xx(struct halmac_adapter *adapter);\n\nstatic enum halmac_ret_status\ncnv_cfg_param_state_88xx(struct halmac_adapter *adapter,\n\t\t\t enum halmac_cmd_construct_state dest_state);\n\nstatic enum halmac_ret_status\nadd_param_buf_88xx(struct halmac_adapter *adapter,\n\t\t   struct halmac_phy_parameter_info *param, u8 *buf,\n\t\t   u8 *end_cmd);\n\nstatic enum halmac_ret_status\ngen_cfg_param_h2c_88xx(struct halmac_adapter *adapter, u8 *buff);\n\nstatic enum halmac_ret_status\nsend_h2c_update_packet_88xx(struct halmac_adapter *adapter,\n\t\t\t    enum halmac_packet_id pkt_id, u8 *pkt, u32 size);\n\nstatic enum halmac_ret_status\nsend_bt_coex_cmd_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,\n\t\t      u8 ack);\n\nstatic enum halmac_ret_status\nread_buf_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,\n\t      enum hal_fifo_sel sel, u8 *data);\n\nstatic enum halmac_cmd_construct_state\nscan_cmd_cnstr_state_88xx(struct halmac_adapter *adapter);\n\nstatic enum halmac_ret_status\ncnv_scan_state_88xx(struct halmac_adapter *adapter,\n\t\t    enum halmac_cmd_construct_state dest_state);\n\nstatic enum halmac_ret_status\nproc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,\n\t\t\t struct halmac_ch_switch_option *opt);\n\nstatic enum halmac_ret_status\nproc_p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info);\n\nstatic enum halmac_ret_status\nget_cfg_param_status_88xx(struct halmac_adapter *adapter,\n\t\t\t  enum halmac_cmd_process_status *proc_status);\n\nstatic enum halmac_ret_status\nget_ch_switch_status_88xx(struct halmac_adapter *adapter,\n\t\t\t  enum halmac_cmd_process_status *proc_status);\n\nstatic enum halmac_ret_status\nget_update_packet_status_88xx(struct halmac_adapter *adapter,\n\t\t\t      enum halmac_cmd_process_status *proc_status);\n\nstatic enum halmac_ret_status\npwr_sub_seq_parser_88xx(struct halmac_adapter *adapter, u8 cut, u8 intf,\n\t\t\tstruct halmac_wlan_pwr_cfg *cmd);\n\nstatic void\npwr_state_88xx(struct halmac_adapter *adapter, enum halmac_mac_power *state);\n\nstatic enum halmac_ret_status\npwr_cmd_polling_88xx(struct halmac_adapter *adapter,\n\t\t     struct halmac_wlan_pwr_cfg *cmd);\n\nstatic void\nget_pq_mapping_88xx(struct halmac_adapter *adapter,\n\t\t    struct halmac_rqpn_map *mapping);\n\nstatic void\ndump_reg_sdio_88xx(struct halmac_adapter *adapter);\n\nstatic enum halmac_ret_status\nwlhdr_valid_88xx(struct halmac_adapter *adapter, u8 *buf);\n\nstatic u8\nwlhdr_mgmt_valid_88xx(struct halmac_adapter *adapter,\n\t\t      struct wlhdr_frame_ctrl *wlhdr);\n\nstatic u8\nwlhdr_ctrl_valid_88xx(struct halmac_adapter *adapter,\n\t\t      struct wlhdr_frame_ctrl *wlhdr);\n\nstatic u8\nwlhdr_data_valid_88xx(struct halmac_adapter *adapter,\n\t\t      struct wlhdr_frame_ctrl *wlhdr);\n\nstatic void\ndump_reg_88xx(struct halmac_adapter *adapter);\n\nstatic u8\npacket_in_nlo_88xx(struct halmac_adapter *adapter,\n\t\t   enum halmac_packet_id pkt_id);\n\nstatic enum halmac_packet_id\nget_real_pkt_id_88xx(struct halmac_adapter *adapter,\n\t\t     enum halmac_packet_id pkt_id);\n\n/**\n * ofld_func_cfg_88xx() - config offload function\n * @adapter : the adapter of halmac\n * @info : offload function information\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nofld_func_cfg_88xx(struct halmac_adapter *adapter,\n\t\t   struct halmac_ofld_func_info *info)\n{\n\tif (adapter->intf == HALMAC_INTERFACE_SDIO &&\n\t    info->rsvd_pg_drv_buf_max_sz > SDIO_TX_MAX_SIZE_88XX)\n\t\treturn HALMAC_RET_FAIL;\n\n\tadapter->pltfm_info.malloc_size = info->halmac_malloc_max_sz;\n\tadapter->pltfm_info.rsvd_pg_size = info->rsvd_pg_drv_buf_max_sz;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * dl_drv_rsvd_page_88xx() - download packet to rsvd page\n * @adapter : the adapter of halmac\n * @pg_offset : page offset of driver's rsvd page\n * @halmac_buf : data to be downloaded, tx_desc is not included\n * @halmac_size : data size to be downloaded\n * Author : KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ndl_drv_rsvd_page_88xx(struct halmac_adapter *adapter, u8 pg_offset, u8 *buf,\n\t\t      u32 size)\n{\n\tenum halmac_ret_status status;\n\tu32 pg_size;\n\tu32 pg_num = 0;\n\tu16 pg_addr = 0;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tpg_size = adapter->hw_cfg_info.page_size;\n\tpg_num = size / pg_size + ((size & (pg_size - 1)) ? 1 : 0);\n\tif (pg_offset + pg_num > adapter->txff_alloc.rsvd_drv_pg_num) {\n\t\tPLTFM_MSG_ERR(\"[ERR] pkt overflow!!\\n\");\n\t\treturn HALMAC_RET_DRV_DL_ERR;\n\t}\n\n\tpg_addr = adapter->txff_alloc.rsvd_drv_addr + pg_offset;\n\n\tstatus = dl_rsvd_page_88xx(adapter, pg_addr, buf, size);\n\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]dl rsvd page fail!!\\n\");\n\t\treturn status;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\ndl_rsvd_page_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *buf,\n\t\t  u32 size)\n{\n\tu8 restore[2];\n\tu8 value8;\n\tu16 rsvd_pg_head;\n\tu32 cnt;\n\tenum halmac_rsvd_pg_state *state = &adapter->halmac_state.rsvd_pg_state;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tif (size == 0) {\n\t\tPLTFM_MSG_TRACE(\"[TRACE]pkt size = 0\\n\");\n\t\treturn HALMAC_RET_ZERO_LEN_RSVD_PACKET;\n\t}\n\n\tif (*state == HALMAC_RSVD_PG_STATE_BUSY)\n\t\treturn HALMAC_RET_BUSY_STATE;\n\n\t*state = HALMAC_RSVD_PG_STATE_BUSY;\n\n\tpg_addr &= BIT_MASK_BCN_HEAD_1_V1;\n\tHALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, (u16)(pg_addr | BIT(15)));\n\n\tvalue8 = HALMAC_REG_R8(REG_CR + 1);\n\trestore[0] = value8;\n\tvalue8 = (u8)(value8 | BIT(0));\n\tHALMAC_REG_W8(REG_CR + 1, value8);\n\n\tvalue8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL + 2);\n\trestore[1] = value8;\n\tvalue8 = (u8)(value8 & ~(BIT(6)));\n\tHALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8);\n\n\tif (PLTFM_SEND_RSVD_PAGE(buf, size) == 0) {\n\t\tPLTFM_MSG_ERR(\"[ERR]send rvsd pg(pltfm)!!\\n\");\n\t\tstatus = HALMAC_RET_DL_RSVD_PAGE_FAIL;\n\t\tgoto DL_RSVD_PG_END;\n\t}\n\n\tcnt = 1000;\n\twhile (!(HALMAC_REG_R8(REG_FIFOPAGE_CTRL_2 + 1) & BIT(7))) {\n\t\tPLTFM_DELAY_US(10);\n\t\tcnt--;\n\t\tif (cnt == 0) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]bcn valid!!\\n\");\n\t\t\tstatus = HALMAC_RET_POLLING_BCN_VALID_FAIL;\n\t\t\tbreak;\n\t\t}\n\t}\nDL_RSVD_PG_END:\n\trsvd_pg_head = adapter->txff_alloc.rsvd_boundary;\n\tHALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, rsvd_pg_head | BIT(15));\n\tHALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[1]);\n\tHALMAC_REG_W8(REG_CR + 1, restore[0]);\n\n\t*state = HALMAC_RSVD_PG_STATE_IDLE;\n\n\treturn status;\n}\n\nenum halmac_ret_status\nget_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,\n\t\t  void *value)\n{\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tswitch (hw_id) {\n\tcase HALMAC_HW_RQPN_MAPPING:\n\t\tget_pq_mapping_88xx(adapter, (struct halmac_rqpn_map *)value);\n\t\tbreak;\n\tcase HALMAC_HW_EFUSE_SIZE:\n\t\t*(u32 *)value = adapter->hw_cfg_info.efuse_size;\n\t\tbreak;\n\tcase HALMAC_HW_EEPROM_SIZE:\n\t\t*(u32 *)value = adapter->hw_cfg_info.eeprom_size;\n\t\tbreak;\n\tcase HALMAC_HW_BT_BANK_EFUSE_SIZE:\n\t\t*(u32 *)value = adapter->hw_cfg_info.bt_efuse_size;\n\t\tbreak;\n\tcase HALMAC_HW_BT_BANK1_EFUSE_SIZE:\n\tcase HALMAC_HW_BT_BANK2_EFUSE_SIZE:\n\t\t*(u32 *)value = 0;\n\t\tbreak;\n\tcase HALMAC_HW_TXFIFO_SIZE:\n\t\t*(u32 *)value = adapter->hw_cfg_info.tx_fifo_size;\n\t\tbreak;\n\tcase HALMAC_HW_RXFIFO_SIZE:\n\t\t*(u32 *)value = adapter->hw_cfg_info.rx_fifo_size;\n\t\tbreak;\n\tcase HALMAC_HW_RSVD_PG_BNDY:\n\t\t*(u16 *)value = adapter->txff_alloc.rsvd_drv_addr;\n\t\tbreak;\n\tcase HALMAC_HW_CAM_ENTRY_NUM:\n\t\t*(u8 *)value = adapter->hw_cfg_info.cam_entry_num;\n\t\tbreak;\n\tcase HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE:\n\t\tget_efuse_available_size_88xx(adapter, (u32 *)value);\n\t\tbreak;\n\tcase HALMAC_HW_IC_VERSION:\n\t\t*(u8 *)value = adapter->chip_ver;\n\t\tbreak;\n\tcase HALMAC_HW_PAGE_SIZE:\n\t\t*(u32 *)value = adapter->hw_cfg_info.page_size;\n\t\tbreak;\n\tcase HALMAC_HW_TX_AGG_ALIGN_SIZE:\n\t\t*(u16 *)value = adapter->hw_cfg_info.tx_align_size;\n\t\tbreak;\n\tcase HALMAC_HW_RX_AGG_ALIGN_SIZE:\n\t\t*(u8 *)value = 8;\n\t\tbreak;\n\tcase HALMAC_HW_DRV_INFO_SIZE:\n\t\t*(u8 *)value = adapter->drv_info_size;\n\t\tbreak;\n\tcase HALMAC_HW_TXFF_ALLOCATION:\n\t\tPLTFM_MEMCPY(value, &adapter->txff_alloc,\n\t\t\t     sizeof(struct halmac_txff_allocation));\n\t\tbreak;\n\tcase HALMAC_HW_RSVD_EFUSE_SIZE:\n\t\t*(u32 *)value = get_rsvd_efuse_size_88xx(adapter);\n\t\tbreak;\n\tcase HALMAC_HW_FW_HDR_SIZE:\n\t\t*(u32 *)value = WLAN_FW_HDR_SIZE;\n\t\tbreak;\n\tcase HALMAC_HW_TX_DESC_SIZE:\n\t\t*(u32 *)value = adapter->hw_cfg_info.txdesc_size;\n\t\tbreak;\n\tcase HALMAC_HW_RX_DESC_SIZE:\n\t\t*(u32 *)value = adapter->hw_cfg_info.rxdesc_size;\n\t\tbreak;\n\tcase HALMAC_HW_ORI_H2C_SIZE:\n\t\t*(u32 *)value = ORIGINAL_H2C_CMD_SIZE;\n\t\tbreak;\n\tcase HALMAC_HW_RSVD_DRV_PGNUM:\n\t\t*(u16 *)value = adapter->txff_alloc.rsvd_drv_pg_num;\n\t\tbreak;\n\tcase HALMAC_HW_TX_PAGE_SIZE:\n\t\t*(u16 *)value = TX_PAGE_SIZE_88XX;\n\t\tbreak;\n\tcase HALMAC_HW_USB_TXAGG_DESC_NUM:\n\t\t*(u8 *)value = adapter->hw_cfg_info.usb_txagg_num;\n\t\tbreak;\n\tcase HALMAC_HW_AC_OQT_SIZE:\n\t\t*(u8 *)value = adapter->hw_cfg_info.ac_oqt_size;\n\t\tbreak;\n\tcase HALMAC_HW_NON_AC_OQT_SIZE:\n\t\t*(u8 *)value = adapter->hw_cfg_info.non_ac_oqt_size;\n\t\tbreak;\n\tcase HALMAC_HW_AC_QUEUE_NUM:\n\t\t*(u8 *)value = adapter->hw_cfg_info.acq_num;\n\t\tbreak;\n\tcase HALMAC_HW_PWR_STATE:\n\t\tpwr_state_88xx(adapter, (enum halmac_mac_power *)value);\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_PARA_NOT_SUPPORT;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic void\nget_pq_mapping_88xx(struct halmac_adapter *adapter,\n\t\t    struct halmac_rqpn_map *mapping)\n{\n\tmapping->dma_map_vo = adapter->pq_map[HALMAC_PQ_MAP_VO];\n\tmapping->dma_map_vi = adapter->pq_map[HALMAC_PQ_MAP_VI];\n\tmapping->dma_map_be = adapter->pq_map[HALMAC_PQ_MAP_BE];\n\tmapping->dma_map_bk = adapter->pq_map[HALMAC_PQ_MAP_BK];\n\tmapping->dma_map_mg = adapter->pq_map[HALMAC_PQ_MAP_MG];\n\tmapping->dma_map_hi = adapter->pq_map[HALMAC_PQ_MAP_HI];\n}\n\n/**\n * set_hw_value_88xx() -set hw config value\n * @adapter : the adapter of halmac\n * @hw_id : hw id for driver to config\n * @value : hw value, reference table to get data type\n * Author : KaiYuan Chang / Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nset_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,\n\t\t  void *value)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tstruct halmac_tx_page_threshold_info *th_info = NULL;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (!value) {\n\t\tPLTFM_MSG_ERR(\"[ERR]null ptr-set hw value\\n\");\n\t\treturn HALMAC_RET_NULL_POINTER;\n\t}\n\n\tswitch (hw_id) {\n#if HALMAC_USB_SUPPORT\n\tcase HALMAC_HW_USB_MODE:\n\t\tstatus = set_usb_mode_88xx(adapter,\n\t\t\t\t\t   *(enum halmac_usb_mode *)value);\n\t\tif (status != HALMAC_RET_SUCCESS)\n\t\t\treturn status;\n\t\tbreak;\n#endif\n\tcase HALMAC_HW_BANDWIDTH:\n\t\tcfg_bw_88xx(adapter, *(enum halmac_bw *)value);\n\t\tbreak;\n\tcase HALMAC_HW_CHANNEL:\n\t\tcfg_ch_88xx(adapter, *(u8 *)value);\n\t\tbreak;\n\tcase HALMAC_HW_PRI_CHANNEL_IDX:\n\t\tcfg_pri_ch_idx_88xx(adapter, *(enum halmac_pri_ch_idx *)value);\n\t\tbreak;\n\tcase HALMAC_HW_EN_BB_RF:\n\t\tstatus = enable_bb_rf_88xx(adapter, *(u8 *)value);\n\t\tif (status != HALMAC_RET_SUCCESS)\n\t\t\treturn status;\n\t\tbreak;\n#if HALMAC_SDIO_SUPPORT\n\tcase HALMAC_HW_SDIO_TX_PAGE_THRESHOLD:\n\t\tif (adapter->intf == HALMAC_INTERFACE_SDIO) {\n\t\t\tth_info = (struct halmac_tx_page_threshold_info *)value;\n\t\t\tcfg_sdio_tx_page_threshold_88xx(adapter, th_info);\n\t\t} else {\n\t\t\treturn HALMAC_RET_FAIL;\n\t\t}\n\t\tbreak;\n#endif\n\tcase HALMAC_HW_RX_SHIFT:\n\t\trx_shift_88xx(adapter, *(u8 *)value);\n\t\tbreak;\n\tcase HALMAC_HW_TXDESC_CHECKSUM:\n\t\ttx_desc_chksum_88xx(adapter, *(u8 *)value);\n\t\tbreak;\n\tcase HALMAC_HW_RX_CLK_GATE:\n\t\trx_clk_gate_88xx(adapter, *(u8 *)value);\n\t\tbreak;\n\tcase HALMAC_HW_FAST_EDCA:\n\t\tfast_edca_cfg_88xx(adapter,\n\t\t\t\t   (struct halmac_fast_edca_cfg *)value);\n\t\tbreak;\n\tcase HALMAC_HW_RTS_FULL_BW:\n\t\trts_full_bw_88xx(adapter, *(u8 *)value);\n\t\tbreak;\n\tcase HALMAC_HW_FREE_CNT_EN:\n\t\tHALMAC_REG_W8_SET(REG_MISC_CTRL, BIT_EN_FREECNT);\n\t\tbreak;\n\tcase HALMAC_HW_TXFIFO_LIFETIME:\n\t\tcfg_txfifo_lt_88xx(adapter,\n\t\t\t\t   (struct halmac_txfifo_lifetime_cfg *)value);\n\tdefault:\n\t\treturn HALMAC_RET_PARA_NOT_SUPPORT;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nset_h2c_pkt_hdr_88xx(struct halmac_adapter *adapter, u8 *hdr,\n\t\t     struct halmac_h2c_header_info *info, u16 *seq_num)\n{\n\tu16 total_size;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s!!\\n\", __func__);\n\n\ttotal_size = H2C_PKT_HDR_SIZE_88XX + info->content_size;\n\tFW_OFFLOAD_H2C_SET_TOTAL_LEN(hdr, total_size);\n\tFW_OFFLOAD_H2C_SET_SUB_CMD_ID(hdr, info->sub_cmd_id);\n\n\tFW_OFFLOAD_H2C_SET_CATEGORY(hdr, 0x01);\n\tFW_OFFLOAD_H2C_SET_CMD_ID(hdr, 0xFF);\n\n\tPLTFM_MUTEX_LOCK(&adapter->h2c_seq_mutex);\n\tFW_OFFLOAD_H2C_SET_SEQ_NUM(hdr, adapter->h2c_info.seq_num);\n\t*seq_num = adapter->h2c_info.seq_num;\n\t(adapter->h2c_info.seq_num)++;\n\tPLTFM_MUTEX_UNLOCK(&adapter->h2c_seq_mutex);\n\n\tif (info->ack == 1)\n\t\tFW_OFFLOAD_H2C_SET_ACK(hdr, 1);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nsend_h2c_pkt_88xx(struct halmac_adapter *adapter, u8 *pkt)\n{\n\tu32 cnt = 100;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\twhile (adapter->h2c_info.buf_fs <= H2C_PKT_SIZE_88XX) {\n\t\tget_h2c_buf_free_space_88xx(adapter);\n\t\tcnt--;\n\t\tif (cnt == 0) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]h2c free space!!\\n\");\n\t\t\treturn HALMAC_RET_H2C_SPACE_FULL;\n\t\t}\n\t}\n\n\tcnt = 100;\n\tdo {\n\t\tif (PLTFM_SEND_H2C_PKT(pkt, H2C_PKT_SIZE_88XX) == 1)\n\t\t\tbreak;\n\t\tcnt--;\n\t\tif (cnt == 0) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]pltfm - sned h2c pkt!!\\n\");\n\t\t\treturn HALMAC_RET_SEND_H2C_FAIL;\n\t\t}\n\t\tPLTFM_DELAY_US(5);\n\n\t} while (1);\n\n\tadapter->h2c_info.buf_fs -= H2C_PKT_SIZE_88XX;\n\n\treturn status;\n}\n\nenum halmac_ret_status\nget_h2c_buf_free_space_88xx(struct halmac_adapter *adapter)\n{\n\tu32 hw_wptr;\n\tu32 fw_rptr;\n\tstruct halmac_h2c_info *info = &adapter->h2c_info;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\thw_wptr = HALMAC_REG_R32(REG_H2C_PKT_WRITEADDR) & 0x3FFFF;\n\tfw_rptr = HALMAC_REG_R32(REG_H2C_PKT_READADDR) & 0x3FFFF;\n\n\tif (hw_wptr >= fw_rptr)\n\t\tinfo->buf_fs = info->buf_size - (hw_wptr - fw_rptr);\n\telse\n\t\tinfo->buf_fs = fw_rptr - hw_wptr;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * get_c2h_info_88xx() - process halmac C2H packet\n * @adapter : the adapter of halmac\n * @buf : RX Packet pointer\n * @size : RX Packet size\n *\n * Note : Don't use any IO or DELAY in this API\n *\n * Author : KaiYuan Chang/Ivan Lin\n *\n * Used to process c2h packet info from RX path. After receiving the packet,\n * user need to call this api and pass the packet pointer.\n *\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nget_c2h_info_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tif (GET_RX_DESC_C2H(buf) == 1) {\n\t\tPLTFM_MSG_TRACE(\"[TRACE]Parse c2h pkt\\n\");\n\n\t\tstatus = parse_c2h_pkt_88xx(adapter, buf, size);\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]Parse c2h pkt\\n\");\n\t\t\treturn status;\n\t\t}\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nparse_c2h_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)\n{\n\tu8 cmd_id;\n\tu8 sub_cmd_id;\n\tu8 *c2h_pkt = buf + adapter->hw_cfg_info.rxdesc_size;\n\tu32 c2h_size = size - adapter->hw_cfg_info.rxdesc_size;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tcmd_id = (u8)C2H_HDR_GET_CMD_ID(c2h_pkt);\n\n\tif (cmd_id != 0xFF) {\n\t\tPLTFM_MSG_TRACE(\"[TRACE]Not 0xFF cmd!!\\n\");\n\t\treturn HALMAC_RET_C2H_NOT_HANDLED;\n\t}\n\n\tsub_cmd_id = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_pkt);\n\n\tswitch (sub_cmd_id) {\n\tcase C2H_SUB_CMD_ID_C2H_DBG:\n\t\tstatus = get_c2h_dbg_88xx(adapter, c2h_pkt, c2h_size);\n\t\tbreak;\n\tcase C2H_SUB_CMD_ID_H2C_ACK_HDR:\n\t\tstatus = get_h2c_ack_88xx(adapter, c2h_pkt, c2h_size);\n\t\tbreak;\n\tcase C2H_SUB_CMD_ID_BT_COEX_INFO:\n\t\tstatus = HALMAC_RET_C2H_NOT_HANDLED;\n\t\tbreak;\n\tcase C2H_SUB_CMD_ID_SCAN_STATUS_RPT:\n\t\tstatus = get_scan_rpt_88xx(adapter, c2h_pkt, c2h_size);\n\t\tbreak;\n\tcase C2H_SUB_CMD_ID_PSD_DATA:\n\t\tstatus = get_psd_data_88xx(adapter, c2h_pkt, c2h_size);\n\t\tbreak;\n\tcase C2H_SUB_CMD_ID_EFUSE_DATA:\n\t\tstatus = get_efuse_data_88xx(adapter, c2h_pkt, c2h_size);\n\t\tbreak;\n\tdefault:\n\t\tPLTFM_MSG_WARN(\"[WARN]Sub cmd id!!\\n\");\n\t\tstatus = HALMAC_RET_C2H_NOT_HANDLED;\n\t\tbreak;\n\t}\n\n\treturn status;\n}\n\nstatic enum halmac_ret_status\nget_c2h_dbg_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)\n{\n\tu8 i;\n\tu8 next_msg = 0;\n\tu8 cur_msg = 0;\n\tu8 msg_len = 0;\n\tchar *c2h_buf = (char *)NULL;\n\tu8 content_len = 0;\n\tu8 seq_num = 0;\n\n\tcontent_len = (u8)C2H_HDR_GET_LEN((u8 *)buf);\n\n\tif (content_len > C2H_DBG_CONTENT_MAX_LENGTH) {\n\t\tPLTFM_MSG_ERR(\"[ERR]c2h size > max len!\\n\");\n\t\treturn HALMAC_RET_C2H_NOT_HANDLED;\n\t}\n\n\tfor (i = 0; i < content_len; i++) {\n\t\tif (*(buf + C2H_DBG_HDR_LEN + i) == '\\n') {\n\t\t\tif ((*(buf + C2H_DBG_HDR_LEN + i + 1) == '\\0') ||\n\t\t\t    (*(buf + C2H_DBG_HDR_LEN + i + 1) == 0xff)) {\n\t\t\t\tnext_msg = C2H_DBG_HDR_LEN + i + 1;\n\t\t\t\tgoto _ENDFOUND;\n\t\t\t}\n\t\t}\n\t}\n\n_ENDFOUND:\n\tmsg_len = next_msg - C2H_DBG_HDR_LEN;\n\n\tc2h_buf = (char *)PLTFM_MALLOC(msg_len);\n\tif (!c2h_buf)\n\t\treturn HALMAC_RET_MALLOC_FAIL;\n\n\tPLTFM_MEMCPY(c2h_buf, buf + C2H_DBG_HDR_LEN, msg_len);\n\n\tseq_num = (u8)(*(c2h_buf));\n\t*(c2h_buf + msg_len - 1) = '\\0';\n\tPLTFM_MSG_ALWAYS(\"[RTKFW, SEQ=%d]: %s\\n\",\n\t\t\t seq_num, (char *)(c2h_buf + 1));\n\tPLTFM_FREE(c2h_buf, msg_len);\n\n\twhile (*(buf + next_msg) != '\\0') {\n\t\tcur_msg = next_msg;\n\n\t\tmsg_len = (u8)(*(buf + cur_msg + 3)) - 1;\n\t\tnext_msg += C2H_DBG_HDR_LEN + msg_len;\n\n\t\tc2h_buf = (char *)PLTFM_MALLOC(msg_len);\n\t\tif (!c2h_buf)\n\t\t\treturn HALMAC_RET_MALLOC_FAIL;\n\n\t\tPLTFM_MEMCPY(c2h_buf, buf + cur_msg + C2H_DBG_HDR_LEN, msg_len);\n\t\t*(c2h_buf + msg_len - 1) = '\\0';\n\t\tseq_num = (u8)(*(c2h_buf));\n\t\tPLTFM_MSG_ALWAYS(\"[RTKFW, SEQ=%d]: %s\\n\",\n\t\t\t\t seq_num, (char *)(c2h_buf + 1));\n\t\tPLTFM_FREE(c2h_buf, msg_len);\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nget_h2c_ack_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)\n{\n\tu8 cmd_id;\n\tu8 sub_cmd_id;\n\tu8 fw_rc;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]Ack for C2H!!\\n\");\n\n\tfw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);\n\tif (HALMAC_H2C_RETURN_SUCCESS != (enum halmac_h2c_return_code)fw_rc)\n\t\tPLTFM_MSG_TRACE(\"[TRACE]fw rc = %d\\n\", fw_rc);\n\n\tcmd_id = (u8)H2C_ACK_HDR_GET_H2C_CMD_ID(buf);\n\n\tif (cmd_id != 0xFF) {\n\t\tPLTFM_MSG_ERR(\"[ERR]h2c ack cmd id!!\\n\");\n\t\treturn HALMAC_RET_C2H_NOT_HANDLED;\n\t}\n\n\tsub_cmd_id = (u8)H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(buf);\n\n\tswitch (sub_cmd_id) {\n\tcase H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK:\n\t\tstatus = get_h2c_ack_phy_efuse_88xx(adapter, buf, size);\n\t\tbreak;\n\tcase H2C_SUB_CMD_ID_CFG_PARAM_ACK:\n\t\tstatus = get_h2c_ack_cfg_param_88xx(adapter, buf, size);\n\t\tbreak;\n\tcase H2C_SUB_CMD_ID_UPDATE_PKT_ACK:\n\t\tstatus = get_h2c_ack_update_pkt_88xx(adapter, buf, size);\n\t\tbreak;\n\tcase H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK:\n\t\tstatus = get_h2c_ack_update_datapkt_88xx(adapter, buf, size);\n\t\tbreak;\n\tcase H2C_SUB_CMD_ID_RUN_DATAPACK_ACK:\n\t\tstatus = get_h2c_ack_run_datapkt_88xx(adapter, buf, size);\n\t\tbreak;\n\tcase H2C_SUB_CMD_ID_CH_SWITCH_ACK:\n\t\tstatus = get_h2c_ack_ch_switch_88xx(adapter, buf, size);\n\t\tbreak;\n\tcase H2C_SUB_CMD_ID_IQK_ACK:\n\t\tstatus = get_h2c_ack_iqk_88xx(adapter, buf, size);\n\t\tbreak;\n\tcase H2C_SUB_CMD_ID_PWR_TRK_ACK:\n\t\tstatus = get_h2c_ack_pwr_trk_88xx(adapter, buf, size);\n\t\tbreak;\n\tcase H2C_SUB_CMD_ID_PSD_ACK:\n\t\tbreak;\n\tcase H2C_SUB_CMD_ID_FW_SNDING_ACK:\n\t\tstatus = get_h2c_ack_fw_snding_88xx(adapter, buf, size);\n\t\tbreak;\n\tdefault:\n\t\tstatus = HALMAC_RET_C2H_NOT_HANDLED;\n\t\tbreak;\n\t}\n\n\treturn status;\n}\n\nstatic enum halmac_ret_status\nget_scan_rpt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)\n{\n\tu8 fw_rc;\n\tenum halmac_cmd_process_status proc_status;\n\n\tfw_rc = (u8)SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(buf);\n\tproc_status = (HALMAC_H2C_RETURN_SUCCESS ==\n\t\t(enum halmac_h2c_return_code)fw_rc) ?\n\t\tHALMAC_CMD_PROCESS_DONE : HALMAC_CMD_PROCESS_ERROR;\n\n\tPLTFM_EVENT_SIG(HALMAC_FEATURE_CHANNEL_SWITCH, proc_status, NULL, 0);\n\n\tadapter->halmac_state.scan_state.proc_status = proc_status;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]scan : %X\\n\", proc_status);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nget_h2c_ack_cfg_param_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)\n{\n\tu8 seq_num;\n\tu8 fw_rc;\n\tu32 offset_accum;\n\tu32 value_accum;\n\tstruct halmac_cfg_param_state *state =\n\t\t&adapter->halmac_state.cfg_param_state;\n\tenum halmac_cmd_process_status proc_status =\n\t\tHALMAC_CMD_PROCESS_UNDEFINE;\n\n\tseq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);\n\tPLTFM_MSG_TRACE(\"[TRACE]Seq num : h2c->%d c2h->%d\\n\",\n\t\t\tstate->seq_num, seq_num);\n\tif (seq_num != state->seq_num) {\n\t\tPLTFM_MSG_ERR(\"[ERR]Seq num mismatch : h2c->%d c2h->%d\\n\",\n\t\t\t      state->seq_num, seq_num);\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tif (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_ERR(\"[ERR]not cmd sending\\n\");\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tfw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);\n\tstate->fw_rc = fw_rc;\n\toffset_accum = CFG_PARAM_ACK_GET_OFFSET_ACCUMULATION(buf);\n\tvalue_accum = CFG_PARAM_ACK_GET_VALUE_ACCUMULATION(buf);\n\n\tif (offset_accum != adapter->cfg_param_info.offset_accum ||\n\t    value_accum != adapter->cfg_param_info.value_accum) {\n\t\tPLTFM_MSG_ERR(\"[ERR][C2H]offset_accu : %x, value_accu : %xn\",\n\t\t\t      offset_accum, value_accum);\n\t\tPLTFM_MSG_ERR(\"[ERR][Ada]offset_accu : %x, value_accu : %x\\n\",\n\t\t\t      adapter->cfg_param_info.offset_accum,\n\t\t\t      adapter->cfg_param_info.value_accum);\n\t\tproc_status = HALMAC_CMD_PROCESS_ERROR;\n\t}\n\n\tif ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS &&\n\t    proc_status != HALMAC_CMD_PROCESS_ERROR) {\n\t\tproc_status = HALMAC_CMD_PROCESS_DONE;\n\t\tstate->proc_status = proc_status;\n\t\tPLTFM_EVENT_SIG(HALMAC_FEATURE_CFG_PARA, proc_status, NULL, 0);\n\t} else {\n\t\tproc_status = HALMAC_CMD_PROCESS_ERROR;\n\t\tstate->proc_status = proc_status;\n\t\tPLTFM_EVENT_SIG(HALMAC_FEATURE_CFG_PARA, proc_status,\n\t\t\t\t&fw_rc, 1);\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nget_h2c_ack_update_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)\n{\n\tu8 seq_num;\n\tu8 fw_rc;\n\tstruct halmac_update_pkt_state *state =\n\t\t&adapter->halmac_state.update_pkt_state;\n\tenum halmac_cmd_process_status proc_status;\n\n\tseq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);\n\tPLTFM_MSG_TRACE(\"[TRACE]Seq num : h2c->%d c2h->%d\\n\",\n\t\t\tstate->seq_num, seq_num);\n\tif (seq_num != state->seq_num) {\n\t\tPLTFM_MSG_ERR(\"[ERR]Seq num mismatch : h2c->%d c2h->%d\\n\",\n\t\t\t      state->seq_num, seq_num);\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tif (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_ERR(\"[ERR]not cmd sending\\n\");\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tfw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);\n\tstate->fw_rc = fw_rc;\n\n\tif (HALMAC_H2C_RETURN_SUCCESS == (enum halmac_h2c_return_code)fw_rc) {\n\t\tproc_status = HALMAC_CMD_PROCESS_DONE;\n\t\tstate->proc_status = proc_status;\n\t\tPLTFM_EVENT_SIG(HALMAC_FEATURE_UPDATE_PACKET, proc_status,\n\t\t\t\tNULL, 0);\n\t} else {\n\t\tproc_status = HALMAC_CMD_PROCESS_ERROR;\n\t\tstate->proc_status = proc_status;\n\t\tPLTFM_EVENT_SIG(HALMAC_FEATURE_UPDATE_PACKET, proc_status,\n\t\t\t\t&state->fw_rc, 1);\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nget_h2c_ack_update_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf,\n\t\t\t\tu32 size)\n{\n\treturn HALMAC_RET_NOT_SUPPORT;\n}\n\nstatic enum halmac_ret_status\nget_h2c_ack_run_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)\n{\n\treturn HALMAC_RET_NOT_SUPPORT;\n}\n\nstatic enum halmac_ret_status\nget_h2c_ack_ch_switch_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)\n{\n\tu8 seq_num;\n\tu8 fw_rc;\n\tstruct halmac_scan_state *state = &adapter->halmac_state.scan_state;\n\tenum halmac_cmd_process_status proc_status;\n\n\tseq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);\n\tPLTFM_MSG_TRACE(\"[TRACE]Seq num : h2c->%d c2h->%d\\n\",\n\t\t\tstate->seq_num, seq_num);\n\tif (seq_num != state->seq_num) {\n\t\tPLTFM_MSG_ERR(\"[ERR]Seq num mismatch : h2c->%d c2h->%d\\n\",\n\t\t\t      state->seq_num, seq_num);\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tif (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_ERR(\"[ERR]not cmd sending\\n\");\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tfw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);\n\tstate->fw_rc = fw_rc;\n\n\tif ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {\n\t\tproc_status = HALMAC_CMD_PROCESS_RCVD;\n\t\tstate->proc_status = proc_status;\n\t\tPLTFM_EVENT_SIG(HALMAC_FEATURE_CHANNEL_SWITCH, proc_status,\n\t\t\t\tNULL, 0);\n\t} else {\n\t\tproc_status = HALMAC_CMD_PROCESS_ERROR;\n\t\tstate->proc_status = proc_status;\n\t\tPLTFM_EVENT_SIG(HALMAC_FEATURE_CHANNEL_SWITCH, proc_status,\n\t\t\t\t&fw_rc, 1);\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * mac_debug_88xx_v1() - read some registers for debug\n * @adapter\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n */\nenum halmac_ret_status\nmac_debug_88xx(struct halmac_adapter *adapter)\n{\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (adapter->intf == HALMAC_INTERFACE_SDIO)\n\t\tdump_reg_sdio_88xx(adapter);\n\telse\n\t\tdump_reg_88xx(adapter);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic void\ndump_reg_sdio_88xx(struct halmac_adapter *adapter)\n{\n\tu8 tmp8;\n\tu32 i;\n\n\t/* Dump CCCR, it needs new platform api */\n\n\t/*Dump SDIO Local Register, use CMD52*/\n\tfor (i = 0x10250000; i < 0x102500ff; i++) {\n\t\ttmp8 = PLTFM_SDIO_CMD52_R(i);\n\t\tPLTFM_MSG_TRACE(\"[TRACE]dbg-sdio[%x]=%x\\n\", i, tmp8);\n\t}\n\n\t/*Dump MAC Register*/\n\tfor (i = 0x0000; i < 0x17ff; i++) {\n\t\ttmp8 = PLTFM_SDIO_CMD52_R(i);\n\t\tPLTFM_MSG_TRACE(\"[TRACE]dbg-mac[%x]=%x\\n\", i, tmp8);\n\t}\n\n\ttmp8 = PLTFM_SDIO_CMD52_R(REG_SDIO_CRC_ERR_IDX);\n\tif (tmp8)\n\t\tPLTFM_MSG_ERR(\"[ERR]sdio crc=%x\\n\", tmp8);\n\n\t/*Check RX Fifo status*/\n\ti = REG_RXFF_PTR_V1;\n\ttmp8 = PLTFM_SDIO_CMD52_R(i);\n\tPLTFM_MSG_TRACE(\"[TRACE]dbg-mac[%x]=%x\\n\", i, tmp8);\n\ti = REG_RXFF_WTR_V1;\n\ttmp8 = PLTFM_SDIO_CMD52_R(i);\n\tPLTFM_MSG_TRACE(\"[TRACE]dbg-mac[%x]=%x\\n\", i, tmp8);\n\ti = REG_RXFF_PTR_V1;\n\ttmp8 = PLTFM_SDIO_CMD52_R(i);\n\tPLTFM_MSG_TRACE(\"[TRACE]dbg-mac[%x]=%x\\n\", i, tmp8);\n\ti = REG_RXFF_WTR_V1;\n\ttmp8 = PLTFM_SDIO_CMD52_R(i);\n\tPLTFM_MSG_TRACE(\"[TRACE]dbg-mac[%x]=%x\\n\", i, tmp8);\n}\n\nstatic void\ndump_reg_88xx(struct halmac_adapter *adapter)\n{\n\tu32 tmp32;\n\tu32 i;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\t/*Dump MAC Register*/\n\tfor (i = 0x0000; i < 0x17fc; i += 4) {\n\t\ttmp32 = HALMAC_REG_R32(i);\n\t\tPLTFM_MSG_TRACE(\"[TRACE]dbg-mac[%x]=%x\\n\", i, tmp32);\n\t}\n\n\t/*Check RX Fifo status*/\n\ti = REG_RXFF_PTR_V1;\n\ttmp32 = HALMAC_REG_R32(i);\n\tPLTFM_MSG_TRACE(\"[TRACE]dbg-mac[%x]=%x\\n\", i, tmp32);\n\ti = REG_RXFF_WTR_V1;\n\ttmp32 = HALMAC_REG_R32(i);\n\tPLTFM_MSG_TRACE(\"[TRACE]dbg-mac[%x]=%x\\n\", i, tmp32);\n\ti = REG_RXFF_PTR_V1;\n\ttmp32 = HALMAC_REG_R32(i);\n\tPLTFM_MSG_TRACE(\"[TRACE]dbg-mac[%x]=%x\\n\", i, tmp32);\n\ti = REG_RXFF_WTR_V1;\n\ttmp32 = HALMAC_REG_R32(i);\n\tPLTFM_MSG_TRACE(\"[TRACE]dbg-mac[%x]=%x\\n\", i, tmp32);\n}\n\n/**\n * cfg_parameter_88xx() - config parameter by FW\n * @adapter : the adapter of halmac\n * @info : cmd id, content\n * @full_fifo : parameter information\n *\n * If msk_en = 1, the format of array is {reg_info, mask, value}.\n * If msk_en =_FAUSE, the format of array is {reg_info, value}\n * The format of reg_info is\n * reg_info[31]=rf_reg, 0: MAC_BB reg, 1: RF reg\n * reg_info[27:24]=rf_path, 0: path_A, 1: path_B\n * if rf_reg=0(MAC_BB reg), rf_path is meaningless.\n * ref_info[15:0]=offset\n *\n * Example: msk_en = 0\n * {0x8100000a, 0x00001122}\n * =>Set RF register, path_B, offset 0xA to 0x00001122\n * {0x00000824, 0x11224433}\n * =>Set MAC_BB register, offset 0x800 to 0x11224433\n *\n * Note : full fifo mode only for init flow\n *\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_parameter_88xx(struct halmac_adapter *adapter,\n\t\t   struct halmac_phy_parameter_info *info, u8 full_fifo)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tenum halmac_cmd_process_status *proc_status;\n\tenum halmac_cmd_construct_state cmd_state;\n\n\tproc_status = &adapter->halmac_state.cfg_param_state.proc_status;\n\n\tif (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_NO_DLFW;\n\n\tif (adapter->fw_ver.h2c_version < 4)\n\t\treturn HALMAC_RET_FW_NO_SUPPORT;\n\n\tif (*proc_status == HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_TRACE(\"[TRACE]Wait event(para)\\n\");\n\t\treturn HALMAC_RET_BUSY_STATE;\n\t}\n\n\tcmd_state = cfg_param_cmd_cnstr_state_88xx(adapter);\n\tif (cmd_state != HALMAC_CMD_CNSTR_IDLE &&\n\t    cmd_state != HALMAC_CMD_CNSTR_CNSTR) {\n\t\tPLTFM_MSG_TRACE(\"[TRACE]Not idle(para)\\n\");\n\t\treturn HALMAC_RET_BUSY_STATE;\n\t}\n\n\t*proc_status = HALMAC_CMD_PROCESS_IDLE;\n\n\tstatus = proc_cfg_param_88xx(adapter, info, full_fifo);\n\n\tif (status != HALMAC_RET_SUCCESS && status != HALMAC_RET_PARA_SENDING) {\n\t\tPLTFM_MSG_ERR(\"[ERR]send param h2c\\n\");\n\t\treturn status;\n\t}\n\n\treturn status;\n}\n\nstatic enum halmac_cmd_construct_state\ncfg_param_cmd_cnstr_state_88xx(struct halmac_adapter *adapter)\n{\n\treturn adapter->halmac_state.cfg_param_state.cmd_cnstr_state;\n}\n\nstatic enum halmac_ret_status\nproc_cfg_param_88xx(struct halmac_adapter *adapter,\n\t\t    struct halmac_phy_parameter_info *param, u8 full_fifo)\n{\n\tu8 end_cmd = 0;\n\tu32 rsvd_size;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tstruct halmac_cfg_param_info *info = &adapter->cfg_param_info;\n\tenum halmac_cmd_process_status *proc_status;\n\n\tproc_status = &adapter->halmac_state.cfg_param_state.proc_status;\n\n\tstatus = malloc_cfg_param_buf_88xx(adapter, full_fifo);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tif (cnv_cfg_param_state_88xx(adapter, HALMAC_CMD_CNSTR_CNSTR) !=\n\t    HALMAC_RET_SUCCESS) {\n\t\tPLTFM_FREE(info->buf, info->buf_size);\n\t\tinfo->buf = NULL;\n\t\tinfo->buf_wptr = NULL;\n\t\treturn HALMAC_RET_ERROR_STATE;\n\t}\n\n\tadd_param_buf_88xx(adapter, param, info->buf_wptr, &end_cmd);\n\tif (param->cmd_id != HALMAC_PARAMETER_CMD_END) {\n\t\tinfo->num++;\n\t\tinfo->buf_wptr += CFG_PARAM_H2C_INFO_SIZE;\n\t\tinfo->avl_buf_size -= CFG_PARAM_H2C_INFO_SIZE;\n\t}\n\n\trsvd_size = info->avl_buf_size - adapter->hw_cfg_info.txdesc_size;\n\tif (rsvd_size > CFG_PARAM_H2C_INFO_SIZE && end_cmd == 0)\n\t\treturn HALMAC_RET_SUCCESS;\n\n\tif (info->num == 0) {\n\t\tPLTFM_FREE(info->buf, info->buf_size);\n\t\tinfo->buf = NULL;\n\t\tinfo->buf_wptr = NULL;\n\t\tPLTFM_MSG_TRACE(\"[TRACE]param num = 0!!\\n\");\n\n\t\t*proc_status = HALMAC_CMD_PROCESS_DONE;\n\t\tPLTFM_EVENT_SIG(HALMAC_FEATURE_CFG_PARA, *proc_status, NULL, 0);\n\n\t\treset_ofld_feature_88xx(adapter, HALMAC_FEATURE_CFG_PARA);\n\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tstatus = send_cfg_param_h2c_88xx(adapter);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tif (info->buf) {\n\t\t\tPLTFM_FREE(info->buf, info->buf_size);\n\t\t\tinfo->buf = NULL;\n\t\t\tinfo->buf_wptr = NULL;\n\t\t}\n\t\treturn status;\n\t}\n\n\tif (end_cmd == 0) {\n\t\tPLTFM_MSG_TRACE(\"[TRACE]send h2c-buf full\\n\");\n\t\treturn HALMAC_RET_PARA_SENDING;\n\t}\n\n\treturn status;\n}\n\nstatic enum halmac_ret_status\nsend_cfg_param_h2c_88xx(struct halmac_adapter *adapter)\n{\n\tu8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };\n\tu16 pg_addr;\n\tu16 seq_num = 0;\n\tu32 info_size;\n\tstruct halmac_h2c_header_info hdr_info;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tstruct halmac_cfg_param_info *info = &adapter->cfg_param_info;\n\tenum halmac_cmd_process_status *proc_status;\n\n\tproc_status = &adapter->halmac_state.cfg_param_state.proc_status;\n\n\tif (cnv_cfg_param_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\t*proc_status = HALMAC_CMD_PROCESS_SENDING;\n\n\tif (info->full_fifo_mode == 1)\n\t\tpg_addr = 0;\n\telse\n\t\tpg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;\n\n\tinfo_size = info->num * CFG_PARAM_H2C_INFO_SIZE;\n\n\tstatus = dl_rsvd_page_88xx(adapter, pg_addr, info->buf, info_size);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]dl rsvd pg!!\\n\");\n\t\tgoto CFG_PARAM_H2C_FAIL;\n\t}\n\n\tgen_cfg_param_h2c_88xx(adapter, h2c_buf);\n\n\thdr_info.sub_cmd_id = SUB_CMD_ID_CFG_PARAM;\n\thdr_info.content_size = 4;\n\thdr_info.ack = 1;\n\tset_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);\n\n\tadapter->halmac_state.cfg_param_state.seq_num = seq_num;\n\n\tstatus = send_h2c_pkt_88xx(adapter, h2c_buf);\n\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]send h2c!!\\n\");\n\t\treset_ofld_feature_88xx(adapter, HALMAC_FEATURE_CFG_PARA);\n\t}\n\nCFG_PARAM_H2C_FAIL:\n\tPLTFM_FREE(info->buf, info->buf_size);\n\tinfo->buf = NULL;\n\tinfo->buf_wptr = NULL;\n\n\tif (cnv_cfg_param_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\treturn status;\n}\n\nstatic enum halmac_ret_status\ncnv_cfg_param_state_88xx(struct halmac_adapter *adapter,\n\t\t\t enum halmac_cmd_construct_state dest_state)\n{\n\tenum halmac_cmd_construct_state *state;\n\n\tstate = &adapter->halmac_state.cfg_param_state.cmd_cnstr_state;\n\n\tif ((*state != HALMAC_CMD_CNSTR_IDLE) &&\n\t    (*state != HALMAC_CMD_CNSTR_CNSTR) &&\n\t    (*state != HALMAC_CMD_CNSTR_H2C_SENT))\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\tif (dest_state == HALMAC_CMD_CNSTR_IDLE) {\n\t\tif (*state == HALMAC_CMD_CNSTR_CNSTR)\n\t\t\treturn HALMAC_RET_ERROR_STATE;\n\t} else if (dest_state == HALMAC_CMD_CNSTR_CNSTR) {\n\t\tif (*state == HALMAC_CMD_CNSTR_H2C_SENT)\n\t\t\treturn HALMAC_RET_ERROR_STATE;\n\t} else if (dest_state == HALMAC_CMD_CNSTR_H2C_SENT) {\n\t\tif ((*state == HALMAC_CMD_CNSTR_IDLE) ||\n\t\t    (*state == HALMAC_CMD_CNSTR_H2C_SENT))\n\t\t\treturn HALMAC_RET_ERROR_STATE;\n\t}\n\n\t*state = dest_state;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nadd_param_buf_88xx(struct halmac_adapter *adapter,\n\t\t   struct halmac_phy_parameter_info *param, u8 *buf,\n\t\t   u8 *end_cmd)\n{\n\tstruct halmac_cfg_param_info *info = &adapter->cfg_param_info;\n\tunion halmac_parameter_content *content = &param->content;\n\n\t*end_cmd = 0;\n\n\tPARAM_INFO_SET_LEN(buf, CFG_PARAM_H2C_INFO_SIZE);\n\tPARAM_INFO_SET_IO_CMD(buf, param->cmd_id);\n\n\tswitch (param->cmd_id) {\n\tcase HALMAC_PARAMETER_CMD_BB_W8:\n\tcase HALMAC_PARAMETER_CMD_BB_W16:\n\tcase HALMAC_PARAMETER_CMD_BB_W32:\n\tcase HALMAC_PARAMETER_CMD_MAC_W8:\n\tcase HALMAC_PARAMETER_CMD_MAC_W16:\n\tcase HALMAC_PARAMETER_CMD_MAC_W32:\n\t\tPARAM_INFO_SET_IO_ADDR(buf, content->MAC_REG_W.offset);\n\t\tPARAM_INFO_SET_DATA(buf, content->MAC_REG_W.value);\n\t\tPARAM_INFO_SET_MASK(buf, content->MAC_REG_W.msk);\n\t\tPARAM_INFO_SET_MSK_EN(buf, content->MAC_REG_W.msk_en);\n\t\tinfo->value_accum += content->MAC_REG_W.value;\n\t\tinfo->offset_accum += content->MAC_REG_W.offset;\n\t\tbreak;\n\tcase HALMAC_PARAMETER_CMD_RF_W:\n\t\t/*In rf register, the address is only 1 byte*/\n\t\tPARAM_INFO_SET_RF_ADDR(buf, content->RF_REG_W.offset);\n\t\tPARAM_INFO_SET_RF_PATH(buf, content->RF_REG_W.rf_path);\n\t\tPARAM_INFO_SET_DATA(buf, content->RF_REG_W.value);\n\t\tPARAM_INFO_SET_MASK(buf, content->RF_REG_W.msk);\n\t\tPARAM_INFO_SET_MSK_EN(buf, content->RF_REG_W.msk_en);\n\t\tinfo->value_accum += content->RF_REG_W.value;\n\t\tinfo->offset_accum += (content->RF_REG_W.offset +\n\t\t\t\t\t(content->RF_REG_W.rf_path << 8));\n\t\tbreak;\n\tcase HALMAC_PARAMETER_CMD_DELAY_US:\n\tcase HALMAC_PARAMETER_CMD_DELAY_MS:\n\t\tPARAM_INFO_SET_DELAY_VAL(buf, content->DELAY_TIME.delay_time);\n\t\tbreak;\n\tcase HALMAC_PARAMETER_CMD_END:\n\t\t*end_cmd = 1;\n\t\tbreak;\n\tdefault:\n\t\tPLTFM_MSG_ERR(\"[ERR]cmd id!!\\n\");\n\t\tbreak;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\ngen_cfg_param_h2c_88xx(struct halmac_adapter *adapter, u8 *buff)\n{\n\tstruct halmac_cfg_param_info *info = &adapter->cfg_param_info;\n\tu16 h2c_info_addr = adapter->txff_alloc.rsvd_h2c_info_addr;\n\tu16 rsvd_pg_addr = adapter->txff_alloc.rsvd_boundary;\n\n\tCFG_PARAM_SET_NUM(buff, info->num);\n\n\tif (info->full_fifo_mode == 1) {\n\t\tCFG_PARAM_SET_INIT_CASE(buff, 0x1);\n\t\tCFG_PARAM_SET_LOC(buff, 0);\n\t} else {\n\t\tCFG_PARAM_SET_INIT_CASE(buff, 0x0);\n\t\tCFG_PARAM_SET_LOC(buff, h2c_info_addr - rsvd_pg_addr);\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nmalloc_cfg_param_buf_88xx(struct halmac_adapter *adapter, u8 full_fifo)\n{\n\tstruct halmac_cfg_param_info *info = &adapter->cfg_param_info;\n\tstruct halmac_pltfm_cfg_info *pltfm_info = &adapter->pltfm_info;\n\n\tif (info->buf)\n\t\treturn HALMAC_RET_SUCCESS;\n\n\tif (full_fifo == 1)\n\t\tinfo->buf_size = pltfm_info->malloc_size;\n\telse\n\t\tinfo->buf_size = CFG_PARAM_RSVDPG_SIZE;\n\n\tif (info->buf_size > pltfm_info->rsvd_pg_size)\n\t\tinfo->buf_size = pltfm_info->rsvd_pg_size;\n\n\tinfo->buf = smart_malloc_88xx(adapter, info->buf_size, &info->buf_size);\n\tif (info->buf) {\n\t\tPLTFM_MEMSET(info->buf, 0x00, info->buf_size);\n\t\tinfo->full_fifo_mode = full_fifo;\n\t\tinfo->buf_wptr = info->buf;\n\t\tinfo->num = 0;\n\t\tinfo->avl_buf_size = info->buf_size;\n\t\tinfo->value_accum = 0;\n\t\tinfo->offset_accum = 0;\n\t} else {\n\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * update_packet_88xx() - send specific packet to FW\n * @adapter : the adapter of halmac\n * @pkt_id : packet id, to know the purpose of this packet\n * @pkt : packet\n * @size : packet size\n *\n * Note : TX_DESC is not included in the pkt\n *\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nupdate_packet_88xx(struct halmac_adapter *adapter, enum halmac_packet_id pkt_id,\n\t\t   u8 *pkt, u32 size)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tenum halmac_cmd_process_status *proc_status =\n\t\t&adapter->halmac_state.update_pkt_state.proc_status;\n\n\tif (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_NO_DLFW;\n\n\tif (adapter->fw_ver.h2c_version < 4)\n\t\treturn HALMAC_RET_FW_NO_SUPPORT;\n\n\tif (size > UPDATE_PKT_RSVDPG_SIZE)\n\t\treturn HALMAC_RET_RSVD_PG_OVERFLOW_FAIL;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (*proc_status == HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_TRACE(\"[TRACE]Wait event(upd)\\n\");\n\t\treturn HALMAC_RET_BUSY_STATE;\n\t}\n\n\t*proc_status = HALMAC_CMD_PROCESS_SENDING;\n\n\tstatus = send_h2c_update_packet_88xx(adapter, pkt_id, pkt, size);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]send h2c!!\\n\");\n\t\tPLTFM_MSG_ERR(\"[ERR]pkt id : %X!!\\n\", pkt_id);\n\t\treturn status;\n\t}\n\n\tif (packet_in_nlo_88xx(adapter, pkt_id)) {\n\t\t*proc_status = HALMAC_CMD_PROCESS_DONE;\n\t\tadapter->nlo_flag = 1;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nsend_h2c_update_packet_88xx(struct halmac_adapter *adapter,\n\t\t\t    enum halmac_packet_id pkt_id, u8 *pkt, u32 size)\n{\n\tu8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };\n\tu16 seq_num = 0;\n\tu16 pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;\n\tu16 pg_offset;\n\tstruct halmac_h2c_header_info hdr_info;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tenum halmac_packet_id real_pkt_id;\n\n\tstatus = dl_rsvd_page_88xx(adapter, pg_addr, pkt, size);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]dl rsvd pg!!\\n\");\n\t\treturn status;\n\t}\n\n\treal_pkt_id = get_real_pkt_id_88xx(adapter, pkt_id);\n\tpg_offset = pg_addr - adapter->txff_alloc.rsvd_boundary;\n\tUPDATE_PKT_SET_SIZE(h2c_buf, size + adapter->hw_cfg_info.txdesc_size);\n\tUPDATE_PKT_SET_ID(h2c_buf, real_pkt_id);\n\tUPDATE_PKT_SET_LOC(h2c_buf, pg_offset);\n\n\thdr_info.sub_cmd_id = SUB_CMD_ID_UPDATE_PKT;\n\thdr_info.content_size = 8;\n\tif (packet_in_nlo_88xx(adapter, pkt_id))\n\t\thdr_info.ack = 0;\n\telse\n\t\thdr_info.ack = 1;\n\tset_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);\n\tadapter->halmac_state.update_pkt_state.seq_num = seq_num;\n\n\tstatus = send_h2c_pkt_88xx(adapter, h2c_buf);\n\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]send h2c!!\\n\");\n\t\treset_ofld_feature_88xx(adapter, HALMAC_FEATURE_UPDATE_PACKET);\n\t\treturn status;\n\t}\n\n\treturn status;\n}\n\nenum halmac_ret_status\nbcn_ie_filter_88xx(struct halmac_adapter *adapter,\n\t\t   struct halmac_bcn_ie_info *info)\n{\n\treturn HALMAC_RET_NOT_SUPPORT;\n}\n\nenum halmac_ret_status\nupdate_datapack_88xx(struct halmac_adapter *adapter,\n\t\t     enum halmac_data_type data_type,\n\t\t     struct halmac_phy_parameter_info *info)\n{\n\treturn HALMAC_RET_NOT_SUPPORT;\n}\n\nenum halmac_ret_status\nrun_datapack_88xx(struct halmac_adapter *adapter,\n\t\t  enum halmac_data_type data_type)\n{\n\treturn HALMAC_RET_NOT_SUPPORT;\n}\n\nenum halmac_ret_status\nsend_bt_coex_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, u8 ack)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tif (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_NO_DLFW;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tstatus = send_bt_coex_cmd_88xx(adapter, buf, size, ack);\n\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]bt coex cmd!!\\n\");\n\t\treturn status;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nsend_bt_coex_cmd_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,\n\t\t      u8 ack)\n{\n\tu8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };\n\tu16 seq_num = 0;\n\tstruct halmac_h2c_header_info hdr_info;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tPLTFM_MEMCPY(h2c_buf + 8, buf, size);\n\n\thdr_info.sub_cmd_id = SUB_CMD_ID_BT_COEX;\n\thdr_info.content_size = (u16)size;\n\thdr_info.ack = ack;\n\tset_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);\n\n\tstatus = send_h2c_pkt_88xx(adapter, h2c_buf);\n\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]send h2c!!\\n\");\n\t\treturn status;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * dump_fifo_88xx() - dump fifo data\n * @adapter : the adapter of halmac\n * @sel : FIFO selection\n * @start_addr : start address of selected FIFO\n * @size : dump size of selected FIFO\n * @data : FIFO data\n *\n * Note : before dump fifo, user need to call halmac_get_fifo_size to\n * get fifo size. Then input this size to halmac_dump_fifo.\n *\n * Author : Ivan Lin/KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ndump_fifo_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel,\n\t       u32 start_addr, u32 size, u8 *data)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tu8 tmp8;\n\tu8 enable;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (sel == HAL_FIFO_SEL_TX &&\n\t    (start_addr + size) > adapter->hw_cfg_info.tx_fifo_size) {\n\t\tPLTFM_MSG_ERR(\"[ERR]size overflow!!\\n\");\n\t\treturn HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;\n\t}\n\n\tif (sel == HAL_FIFO_SEL_RX &&\n\t    (start_addr + size) > adapter->hw_cfg_info.rx_fifo_size) {\n\t\tPLTFM_MSG_ERR(\"[ERR]size overflow!!\\n\");\n\t\treturn HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;\n\t}\n\n\tif ((size & (4 - 1)) != 0) {\n\t\tPLTFM_MSG_ERR(\"[ERR]not 4byte alignment!!\\n\");\n\t\treturn HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;\n\t}\n\n\tif (!data)\n\t\treturn HALMAC_RET_NULL_POINTER;\n\n\ttmp8 = HALMAC_REG_R8(REG_RCR + 2);\n\tenable = 0;\n\tstatus = api->halmac_set_hw_value(adapter, HALMAC_HW_RX_CLK_GATE,\n\t\t\t\t\t  &enable);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\tstatus = read_buf_88xx(adapter, start_addr, size, sel, data);\n\n\tHALMAC_REG_W8(REG_RCR + 2, tmp8);\n\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]read buf!!\\n\");\n\t\treturn status;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nread_buf_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,\n\t      enum hal_fifo_sel sel, u8 *data)\n{\n\tu32 start_pg;\n\tu32 value32;\n\tu32 i;\n\tu32 residue;\n\tu32 cnt = 0;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tif (sel == HAL_FIFO_SEL_RSVD_PAGE)\n\t\toffset += (adapter->txff_alloc.rsvd_boundary <<\n\t\t\t   TX_PAGE_SIZE_SHIFT_88XX);\n\n\tstart_pg = offset >> 12;\n\tresidue = offset & (4096 - 1);\n\n\tif (sel == HAL_FIFO_SEL_TX || sel == HAL_FIFO_SEL_RSVD_PAGE)\n\t\tstart_pg += 0x780;\n\telse if (sel == HAL_FIFO_SEL_RX)\n\t\tstart_pg += 0x700;\n\telse if (sel == HAL_FIFO_SEL_REPORT)\n\t\tstart_pg += 0x660;\n\telse if (sel == HAL_FIFO_SEL_LLT)\n\t\tstart_pg += 0x650;\n\telse if (sel == HAL_FIFO_SEL_RXBUF_FW)\n\t\tstart_pg += 0x680;\n\telse\n\t\treturn HALMAC_RET_NOT_SUPPORT;\n\n\tvalue32 = HALMAC_REG_R16(REG_PKTBUF_DBG_CTRL) & 0xF000;\n\n\tdo {\n\t\tHALMAC_REG_W16(REG_PKTBUF_DBG_CTRL, (u16)(start_pg | value32));\n\n\t\tfor (i = 0x8000 + residue; i <= 0x8FFF; i += 4) {\n\t\t\t*(u32 *)(data + cnt) = HALMAC_REG_R32(i);\n\t\t\t*(u32 *)(data + cnt) =\n\t\t\t\trtk_le32_to_cpu(*(u32 *)(data + cnt));\n\t\t\tcnt += 4;\n\t\t\tif (size == cnt)\n\t\t\t\tgoto HALMAC_BUF_READ_OK;\n\t\t}\n\n\t\tresidue = 0;\n\t\tstart_pg++;\n\t} while (1);\n\nHALMAC_BUF_READ_OK:\n\tHALMAC_REG_W16(REG_PKTBUF_DBG_CTRL, (u16)value32);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * get_fifo_size_88xx() - get fifo size\n * @adapter : the adapter of halmac\n * @sel : FIFO selection\n * Author : Ivan Lin/KaiYuan Chang\n * Return : u32\n * More details of status code can be found in prototype document\n */\nu32\nget_fifo_size_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel)\n{\n\tu32 size = 0;\n\n\tif (sel == HAL_FIFO_SEL_TX)\n\t\tsize = adapter->hw_cfg_info.tx_fifo_size;\n\telse if (sel == HAL_FIFO_SEL_RX)\n\t\tsize = adapter->hw_cfg_info.rx_fifo_size;\n\telse if (sel == HAL_FIFO_SEL_RSVD_PAGE)\n\t\tsize = adapter->hw_cfg_info.tx_fifo_size -\n\t\t       (adapter->txff_alloc.rsvd_boundary <<\n\t\t\tTX_PAGE_SIZE_SHIFT_88XX);\n\telse if (sel == HAL_FIFO_SEL_REPORT)\n\t\tsize = 65536;\n\telse if (sel == HAL_FIFO_SEL_LLT)\n\t\tsize = 65536;\n\telse if (sel == HAL_FIFO_SEL_RXBUF_FW)\n\t\tsize = RX_BUF_FW_88XX;\n\n\treturn size;\n}\n\nenum halmac_ret_status\nset_h2c_header_88xx(struct halmac_adapter *adapter, u8 *hdr, u16 *seq, u8 ack)\n{\n\tPLTFM_MSG_TRACE(\"[TRACE]%s!!\\n\", __func__);\n\n\tH2C_CMD_HEADER_SET_CATEGORY(hdr, 0x00);\n\tH2C_CMD_HEADER_SET_TOTAL_LEN(hdr, 16);\n\n\tPLTFM_MUTEX_LOCK(&adapter->h2c_seq_mutex);\n\tH2C_CMD_HEADER_SET_SEQ_NUM(hdr, adapter->h2c_info.seq_num);\n\t*seq = adapter->h2c_info.seq_num;\n\t(adapter->h2c_info.seq_num)++;\n\tPLTFM_MUTEX_UNLOCK(&adapter->h2c_seq_mutex);\n\n\tif (ack == 1)\n\t\tH2C_CMD_HEADER_SET_ACK(hdr, 1);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * add_ch_info_88xx() -add channel information\n * @adapter : the adapter of halmac\n * @info : channel information\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nadd_ch_info_88xx(struct halmac_adapter *adapter, struct halmac_ch_info *info)\n{\n\tstruct halmac_ch_sw_info *ch_sw_info = &adapter->ch_sw_info;\n\tenum halmac_cmd_construct_state state;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT) {\n\t\tPLTFM_MSG_ERR(\"[ERR]gen info\\n\");\n\t\treturn HALMAC_RET_GEN_INFO_NOT_SENT;\n\t}\n\n\tstate = scan_cmd_cnstr_state_88xx(adapter);\n\tif (state != HALMAC_CMD_CNSTR_BUF_CLR &&\n\t    state != HALMAC_CMD_CNSTR_CNSTR) {\n\t\tPLTFM_MSG_WARN(\"[WARN]cmd state (scan)\\n\");\n\t\treturn HALMAC_RET_ERROR_STATE;\n\t}\n\n\tif (!ch_sw_info->buf) {\n\t\tch_sw_info->buf = (u8 *)PLTFM_MALLOC(SCAN_INFO_RSVDPG_SIZE);\n\t\tif (!ch_sw_info->buf)\n\t\t\treturn HALMAC_RET_NULL_POINTER;\n\t\tch_sw_info->buf_wptr = ch_sw_info->buf;\n\t\tch_sw_info->buf_size = SCAN_INFO_RSVDPG_SIZE;\n\t\tch_sw_info->avl_buf_size = SCAN_INFO_RSVDPG_SIZE;\n\t\tch_sw_info->total_size = 0;\n\t\tch_sw_info->extra_info_en = 0;\n\t\tch_sw_info->ch_num = 0;\n\t}\n\n\tif (ch_sw_info->extra_info_en == 1) {\n\t\tPLTFM_MSG_ERR(\"[ERR]extra info = 1!!\\n\");\n\t\treturn HALMAC_RET_CH_SW_SEQ_WRONG;\n\t}\n\n\tif (ch_sw_info->avl_buf_size < 4) {\n\t\tPLTFM_MSG_ERR(\"[ERR]buf full!!\\n\");\n\t\treturn HALMAC_RET_CH_SW_NO_BUF;\n\t}\n\n\tif (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_CNSTR) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\tCH_INFO_SET_CH(ch_sw_info->buf_wptr, info->channel);\n\tCH_INFO_SET_PRI_CH_IDX(ch_sw_info->buf_wptr, info->pri_ch_idx);\n\tCH_INFO_SET_BW(ch_sw_info->buf_wptr, info->bw);\n\tCH_INFO_SET_TIMEOUT(ch_sw_info->buf_wptr, info->timeout);\n\tCH_INFO_SET_ACTION_ID(ch_sw_info->buf_wptr, info->action_id);\n\tCH_INFO_SET_EXTRA_INFO(ch_sw_info->buf_wptr, info->extra_info);\n\n\tch_sw_info->avl_buf_size = ch_sw_info->avl_buf_size - 4;\n\tch_sw_info->total_size = ch_sw_info->total_size + 4;\n\tch_sw_info->ch_num++;\n\tch_sw_info->extra_info_en = info->extra_info;\n\tch_sw_info->buf_wptr = ch_sw_info->buf_wptr + 4;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_cmd_construct_state\nscan_cmd_cnstr_state_88xx(struct halmac_adapter *adapter)\n{\n\treturn adapter->halmac_state.scan_state.cmd_cnstr_state;\n}\n\nstatic enum halmac_ret_status\ncnv_scan_state_88xx(struct halmac_adapter *adapter,\n\t\t    enum halmac_cmd_construct_state dest_state)\n{\n\tenum halmac_cmd_construct_state *state;\n\n\tstate = &adapter->halmac_state.scan_state.cmd_cnstr_state;\n\n\tif (dest_state == HALMAC_CMD_CNSTR_IDLE) {\n\t\tif ((*state == HALMAC_CMD_CNSTR_BUF_CLR) ||\n\t\t    (*state == HALMAC_CMD_CNSTR_CNSTR))\n\t\t\treturn HALMAC_RET_ERROR_STATE;\n\t} else if (dest_state == HALMAC_CMD_CNSTR_BUF_CLR) {\n\t\tif (*state == HALMAC_CMD_CNSTR_H2C_SENT)\n\t\t\treturn HALMAC_RET_ERROR_STATE;\n\t} else if (dest_state == HALMAC_CMD_CNSTR_CNSTR) {\n\t\tif ((*state == HALMAC_CMD_CNSTR_IDLE) ||\n\t\t    (*state == HALMAC_CMD_CNSTR_H2C_SENT))\n\t\t\treturn HALMAC_RET_ERROR_STATE;\n\t} else if (dest_state == HALMAC_CMD_CNSTR_H2C_SENT) {\n\t\tif ((*state != HALMAC_CMD_CNSTR_CNSTR) &&\n\t\t    (*state != HALMAC_CMD_CNSTR_BUF_CLR))\n\t\t\treturn HALMAC_RET_ERROR_STATE;\n\t}\n\n\t*state = dest_state;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * add_extra_ch_info_88xx() -add extra channel information\n * @adapter : the adapter of halmac\n * @info : extra channel information\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nadd_extra_ch_info_88xx(struct halmac_adapter *adapter,\n\t\t       struct halmac_ch_extra_info *info)\n{\n\tstruct halmac_ch_sw_info *ch_sw_info = &adapter->ch_sw_info;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (!ch_sw_info->buf) {\n\t\tPLTFM_MSG_ERR(\"[ERR]buf = null!!\\n\");\n\t\treturn HALMAC_RET_CH_SW_SEQ_WRONG;\n\t}\n\n\tif (ch_sw_info->extra_info_en == 0) {\n\t\tPLTFM_MSG_ERR(\"[ERR]extra info = 0!!\\n\");\n\t\treturn HALMAC_RET_CH_SW_SEQ_WRONG;\n\t}\n\n\tif (ch_sw_info->avl_buf_size < (u32)(info->extra_info_size + 2)) {\n\t\tPLTFM_MSG_ERR(\"[ERR]no available buffer!!\\n\");\n\t\treturn HALMAC_RET_CH_SW_NO_BUF;\n\t}\n\n\tif (scan_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_CNSTR) {\n\t\tPLTFM_MSG_WARN(\"[WARN]cmd state (ex scan)\\n\");\n\t\treturn HALMAC_RET_ERROR_STATE;\n\t}\n\n\tif (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_CNSTR) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\tCH_EXTRA_INFO_SET_ID(ch_sw_info->buf_wptr, info->extra_action_id);\n\tCH_EXTRA_INFO_SET_INFO(ch_sw_info->buf_wptr, info->extra_info);\n\tCH_EXTRA_INFO_SET_SIZE(ch_sw_info->buf_wptr, info->extra_info_size);\n\tPLTFM_MEMCPY(ch_sw_info->buf_wptr + 2, info->extra_info_data,\n\t\t     info->extra_info_size);\n\n\tch_sw_info->avl_buf_size -= (2 + info->extra_info_size);\n\tch_sw_info->total_size += (2 + info->extra_info_size);\n\tch_sw_info->extra_info_en = info->extra_info;\n\tch_sw_info->buf_wptr += (2 + info->extra_info_size);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * ctrl_ch_switch_88xx() -send channel switch cmd\n * @adapter : the adapter of halmac\n * @opt : channel switch config\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nctrl_ch_switch_88xx(struct halmac_adapter *adapter,\n\t\t    struct halmac_ch_switch_option *opt)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tenum halmac_cmd_construct_state state;\n\tenum halmac_cmd_process_status *proc_status;\n\n\tproc_status = &adapter->halmac_state.scan_state.proc_status;\n\n\tif (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_NO_DLFW;\n\n\tif (adapter->fw_ver.h2c_version < 4)\n\t\treturn HALMAC_RET_FW_NO_SUPPORT;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (opt->switch_en == 0)\n\t\t*proc_status = HALMAC_CMD_PROCESS_IDLE;\n\n\tif ((*proc_status == HALMAC_CMD_PROCESS_SENDING) ||\n\t    (*proc_status == HALMAC_CMD_PROCESS_RCVD)) {\n\t\tPLTFM_MSG_TRACE(\"[TRACE]Wait event(scan)\\n\");\n\t\treturn HALMAC_RET_BUSY_STATE;\n\t}\n\n\tstate = scan_cmd_cnstr_state_88xx(adapter);\n\tif (opt->switch_en == 1) {\n\t\tif (state != HALMAC_CMD_CNSTR_CNSTR) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]state(en = 1)\\n\");\n\t\t\treturn HALMAC_RET_ERROR_STATE;\n\t\t}\n\t} else {\n\t\tif (state != HALMAC_CMD_CNSTR_BUF_CLR) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]state(en = 0)\\n\");\n\t\t\treturn HALMAC_RET_ERROR_STATE;\n\t\t}\n\t}\n\n\tstatus = proc_ctrl_ch_switch_88xx(adapter, opt);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]ctrl ch sw!!\\n\");\n\t\treturn status;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nproc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,\n\t\t\t struct halmac_ch_switch_option *opt)\n{\n\tu8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };\n\tu16 seq_num = 0;\n\tu16 pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;\n\tstruct halmac_h2c_header_info hdr_info;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tenum halmac_cmd_process_status *proc_status;\n\n\tproc_status = &adapter->halmac_state.scan_state.proc_status;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (opt->nlo_en == 1 && adapter->nlo_flag != 1)\n\t\tPLTFM_MSG_WARN(\"[WARN]probe req is NOT nlo pkt!!\\n\");\n\n\tif (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\t*proc_status = HALMAC_CMD_PROCESS_SENDING;\n\n\tif (opt->switch_en != 0) {\n\t\tstatus = dl_rsvd_page_88xx(adapter, pg_addr,\n\t\t\t\t\t   adapter->ch_sw_info.buf,\n\t\t\t\t\t   adapter->ch_sw_info.total_size);\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]dl rsvd pg!!\\n\");\n\t\t\treturn status;\n\t\t}\n\t}\n\n\tCH_SWITCH_SET_START(h2c_buf, opt->switch_en);\n\tCH_SWITCH_SET_CH_NUM(h2c_buf, adapter->ch_sw_info.ch_num);\n\tCH_SWITCH_SET_INFO_LOC(h2c_buf,\n\t\t\t       pg_addr - adapter->txff_alloc.rsvd_boundary);\n\tCH_SWITCH_SET_DEST_CH_EN(h2c_buf, opt->dest_ch_en);\n\tCH_SWITCH_SET_DEST_CH(h2c_buf, opt->dest_ch);\n\tCH_SWITCH_SET_PRI_CH_IDX(h2c_buf, opt->dest_pri_ch_idx);\n\tCH_SWITCH_SET_ABSOLUTE_TIME(h2c_buf, opt->absolute_time_en);\n\tCH_SWITCH_SET_TSF_LOW(h2c_buf, opt->tsf_low);\n\tCH_SWITCH_SET_PERIODIC_OPT(h2c_buf, opt->periodic_option);\n\tCH_SWITCH_SET_NORMAL_CYCLE(h2c_buf, opt->normal_cycle);\n\tCH_SWITCH_SET_NORMAL_PERIOD(h2c_buf, opt->normal_period);\n\tCH_SWITCH_SET_SLOW_PERIOD(h2c_buf, opt->phase_2_period);\n\tCH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_buf, opt->normal_period_sel);\n\tCH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_buf, opt->phase_2_period_sel);\n\tCH_SWITCH_SET_INFO_SIZE(h2c_buf, adapter->ch_sw_info.total_size);\n\n\thdr_info.sub_cmd_id = SUB_CMD_ID_CH_SWITCH;\n\thdr_info.content_size = 20;\n\tif (opt->nlo_en == 1)\n\t\thdr_info.ack = 0;\n\telse\n\t\thdr_info.ack = 1;\n\tset_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);\n\tadapter->halmac_state.scan_state.seq_num = seq_num;\n\n\tstatus = send_h2c_pkt_88xx(adapter, h2c_buf);\n\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]send h2c!!\\n\");\n\t\treset_ofld_feature_88xx(adapter, HALMAC_FEATURE_CHANNEL_SWITCH);\n\t}\n\tPLTFM_FREE(adapter->ch_sw_info.buf, adapter->ch_sw_info.buf_size);\n\tadapter->ch_sw_info.buf = NULL;\n\tadapter->ch_sw_info.buf_wptr = NULL;\n\tadapter->ch_sw_info.extra_info_en = 0;\n\tadapter->ch_sw_info.buf_size = 0;\n\tadapter->ch_sw_info.avl_buf_size = 0;\n\tadapter->ch_sw_info.total_size = 0;\n\tadapter->ch_sw_info.ch_num = 0;\n\n\tif (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\tadapter->nlo_flag = 0;\n\n\treturn status;\n}\n\n/**\n * clear_ch_info_88xx() -clear channel information\n * @adapter : the adapter of halmac\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nclear_ch_info_88xx(struct halmac_adapter *adapter)\n{\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (scan_cmd_cnstr_state_88xx(adapter) == HALMAC_CMD_CNSTR_H2C_SENT) {\n\t\tPLTFM_MSG_WARN(\"[WARN]state(clear)\\n\");\n\t\treturn HALMAC_RET_ERROR_STATE;\n\t}\n\n\tif (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_BUF_CLR) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\tPLTFM_FREE(adapter->ch_sw_info.buf, adapter->ch_sw_info.buf_size);\n\tadapter->ch_sw_info.buf = NULL;\n\tadapter->ch_sw_info.buf_wptr = NULL;\n\tadapter->ch_sw_info.extra_info_en = 0;\n\tadapter->ch_sw_info.buf_size = 0;\n\tadapter->ch_sw_info.avl_buf_size = 0;\n\tadapter->ch_sw_info.total_size = 0;\n\tadapter->ch_sw_info.ch_num = 0;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * chk_txdesc_88xx() -check if the tx packet format is incorrect\n * @adapter : the adapter of halmac\n * @buf : tx Packet buffer, tx desc is included\n * @size : tx packet size\n * Author : KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nchk_txdesc_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)\n{\n\tu32 mac_clk = 0;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (GET_TX_DESC_BMC(buf) == 1 && GET_TX_DESC_AGG_EN(buf) == 1)\n\t\tPLTFM_MSG_ERR(\"[ERR]txdesc - agg + bmc\\n\");\n\n\tif (size < (GET_TX_DESC_TXPKTSIZE(buf) +\n\t\t    adapter->hw_cfg_info.txdesc_size +\n\t\t    (GET_TX_DESC_PKT_OFFSET(buf) << 3))) {\n\t\tPLTFM_MSG_ERR(\"[ERR]txdesc - total size\\n\");\n\t\tstatus = HALMAC_RET_TXDESC_SET_FAIL;\n\t}\n\n\tif (wlhdr_valid_88xx(adapter, buf) != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]wlhdr\\n\");\n\t\tstatus = HALMAC_RET_WLHDR_FAIL;\n\t}\n\n\tif (GET_TX_DESC_AMSDU_PAD_EN(buf) != 0) {\n\t\tPLTFM_MSG_ERR(\"[ERR]txdesc - amsdu_pad\\n\");\n\t\tstatus = HALMAC_RET_TXDESC_SET_FAIL;\n\t}\n\n\tswitch (BIT_GET_MAC_CLK_SEL(HALMAC_REG_R32(REG_AFE_CTRL1))) {\n\tcase 0x0:\n\t\tmac_clk = 80;\n\t\tbreak;\n\tcase 0x1:\n\t\tmac_clk = 40;\n\t\tbreak;\n\tcase 0x2:\n\t\tmac_clk = 20;\n\t\tbreak;\n\tcase 0x3:\n\t\tmac_clk = 10;\n\t\tbreak;\n\t}\n\n\tPLTFM_MSG_ALWAYS(\"MAC clock : 0x%XM\\n\", mac_clk);\n\tPLTFM_MSG_ALWAYS(\"mac agg en : 0x%X\\n\", GET_TX_DESC_AGG_EN(buf));\n\tPLTFM_MSG_ALWAYS(\"mac agg num : 0x%X\\n\", GET_TX_DESC_MAX_AGG_NUM(buf));\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn status;\n}\n\nstatic enum halmac_ret_status\nwlhdr_valid_88xx(struct halmac_adapter *adapter, u8 *buf)\n{\n\tu32 txdesc_size = adapter->hw_cfg_info.txdesc_size +\n\t\t\t\t\t\tGET_TX_DESC_PKT_OFFSET(buf);\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tstruct wlhdr_frame_ctrl *wlhdr;\n\n\twlhdr = (struct wlhdr_frame_ctrl *)(buf + txdesc_size);\n\n\tif (wlhdr->protocol != WLHDR_PROT_VER) {\n\t\tPLTFM_MSG_ERR(\"[ERR]prot ver!!\\n\");\n\t\treturn HALMAC_RET_WLHDR_FAIL;\n\t}\n\n\tswitch (wlhdr->type) {\n\tcase WLHDR_TYPE_MGMT:\n\t\tif (wlhdr_mgmt_valid_88xx(adapter, wlhdr) != 1)\n\t\t\tstatus = HALMAC_RET_WLHDR_FAIL;\n\t\tbreak;\n\tcase WLHDR_TYPE_CTRL:\n\t\tif (wlhdr_ctrl_valid_88xx(adapter, wlhdr) != 1)\n\t\t\tstatus = HALMAC_RET_WLHDR_FAIL;\n\t\tbreak;\n\tcase WLHDR_TYPE_DATA:\n\t\tif (wlhdr_data_valid_88xx(adapter, wlhdr) != 1)\n\t\t\tstatus = HALMAC_RET_WLHDR_FAIL;\n\t\tbreak;\n\tdefault:\n\t\tPLTFM_MSG_ERR(\"[ERR]undefined type!!\\n\");\n\t\tstatus = HALMAC_RET_WLHDR_FAIL;\n\t\tbreak;\n\t}\n\n\treturn status;\n}\n\nstatic u8\nwlhdr_mgmt_valid_88xx(struct halmac_adapter *adapter,\n\t\t      struct wlhdr_frame_ctrl *wlhdr)\n{\n\tu8 state;\n\n\tswitch (wlhdr->sub_type) {\n\tcase WLHDR_SUB_TYPE_ASSOC_REQ:\n\tcase WLHDR_SUB_TYPE_ASSOC_RSPNS:\n\tcase WLHDR_SUB_TYPE_REASSOC_REQ:\n\tcase WLHDR_SUB_TYPE_REASSOC_RSPNS:\n\tcase WLHDR_SUB_TYPE_PROBE_REQ:\n\tcase WLHDR_SUB_TYPE_PROBE_RSPNS:\n\tcase WLHDR_SUB_TYPE_BCN:\n\tcase WLHDR_SUB_TYPE_DISASSOC:\n\tcase WLHDR_SUB_TYPE_AUTH:\n\tcase WLHDR_SUB_TYPE_DEAUTH:\n\tcase WLHDR_SUB_TYPE_ACTION:\n\tcase WLHDR_SUB_TYPE_ACTION_NOACK:\n\t\tstate = 1;\n\t\tbreak;\n\tdefault:\n\t\tPLTFM_MSG_ERR(\"[ERR]mgmt invalid!!\\n\");\n\t\tstate = 0;\n\t\tbreak;\n\t}\n\n\treturn state;\n}\n\nstatic u8\nwlhdr_ctrl_valid_88xx(struct halmac_adapter *adapter,\n\t\t      struct wlhdr_frame_ctrl *wlhdr)\n{\n\tu8 state;\n\n\tswitch (wlhdr->sub_type) {\n\tcase WLHDR_SUB_TYPE_BF_RPT_POLL:\n\tcase WLHDR_SUB_TYPE_NDPA:\n\t\tstate = 1;\n\t\tbreak;\n\tdefault:\n\t\tPLTFM_MSG_ERR(\"[ERR]ctrl invalid!!\\n\");\n\t\tstate = 0;\n\t\tbreak;\n\t}\n\n\treturn state;\n}\n\nstatic u8\nwlhdr_data_valid_88xx(struct halmac_adapter *adapter,\n\t\t      struct wlhdr_frame_ctrl *wlhdr)\n{\n\tu8 state;\n\n\tswitch (wlhdr->sub_type) {\n\tcase WLHDR_SUB_TYPE_DATA:\n\tcase WLHDR_SUB_TYPE_NULL:\n\tcase WLHDR_SUB_TYPE_QOS_DATA:\n\tcase WLHDR_SUB_TYPE_QOS_NULL:\n\t\tstate = 1;\n\t\tbreak;\n\tdefault:\n\t\tPLTFM_MSG_ERR(\"[ERR]data invalid!!\\n\");\n\t\tstate = 0;\n\t\tbreak;\n\t}\n\n\treturn state;\n}\n\n/**\n * get_version_88xx() - get HALMAC version\n * @ver : return version of major, prototype and minor information\n * Author : KaiYuan Chang / Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nget_version_88xx(struct halmac_adapter *adapter, struct halmac_ver *ver)\n{\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tver->major_ver = (u8)HALMAC_MAJOR_VER;\n\tver->prototype_ver = (u8)HALMAC_PROTOTYPE_VER;\n\tver->minor_ver = (u8)HALMAC_MINOR_VER;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\np2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tif (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_NO_DLFW;\n\n\tif (adapter->fw_ver.h2c_version < 6)\n\t\treturn HALMAC_RET_FW_NO_SUPPORT;\n\n\tstatus = proc_p2pps_88xx(adapter, info);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]p2pps!!\\n\");\n\t\treturn status;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nproc_p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info)\n{\n\tu8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };\n\tu16 seq_num = 0;\n\tstruct halmac_h2c_header_info hdr_info;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tP2PPS_SET_OFFLOAD_EN(h2c_buf, info->offload_en);\n\tP2PPS_SET_ROLE(h2c_buf, info->role);\n\tP2PPS_SET_CTWINDOW_EN(h2c_buf, info->ctwindow_en);\n\tP2PPS_SET_NOA_EN(h2c_buf, info->noa_en);\n\tP2PPS_SET_NOA_SEL(h2c_buf, info->noa_sel);\n\tP2PPS_SET_ALLSTASLEEP(h2c_buf, info->all_sta_sleep);\n\tP2PPS_SET_DISCOVERY(h2c_buf, info->discovery);\n\tP2PPS_SET_DISABLE_CLOSERF(h2c_buf, info->disable_close_rf);\n\tP2PPS_SET_P2P_PORT_ID(h2c_buf, info->p2p_port_id);\n\tP2PPS_SET_P2P_GROUP(h2c_buf, info->p2p_group);\n\tP2PPS_SET_P2P_MACID(h2c_buf, info->p2p_macid);\n\n\tP2PPS_SET_CTWINDOW_LENGTH(h2c_buf, info->ctwindow_length);\n\n\tP2PPS_SET_NOA_DURATION_PARA(h2c_buf, info->noa_duration_para);\n\tP2PPS_SET_NOA_INTERVAL_PARA(h2c_buf, info->noa_interval_para);\n\tP2PPS_SET_NOA_START_TIME_PARA(h2c_buf, info->noa_start_time_para);\n\tP2PPS_SET_NOA_COUNT_PARA(h2c_buf, info->noa_count_para);\n\n\thdr_info.sub_cmd_id = SUB_CMD_ID_P2PPS;\n\thdr_info.content_size = 24;\n\thdr_info.ack = 0;\n\tset_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);\n\n\tstatus = send_h2c_pkt_88xx(adapter, h2c_buf);\n\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tPLTFM_MSG_ERR(\"[ERR]send h2c!!\\n\");\n\n\treturn status;\n}\n\n/**\n * query_status_88xx() -query the offload feature status\n * @adapter : the adapter of halmac\n * @feature_id : feature_id\n * @proc_status : feature_status\n * @data : data buffer\n * @size : data size\n *\n * Note :\n * If user wants to know the data size, user can allocate zero\n * size buffer first. If this size less than the data size, halmac\n * will return  HALMAC_RET_BUFFER_TOO_SMALL. User need to\n * re-allocate data buffer with correct data size.\n *\n * Author : Ivan Lin/KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nquery_status_88xx(struct halmac_adapter *adapter,\n\t\t  enum halmac_feature_id feature_id,\n\t\t  enum halmac_cmd_process_status *proc_status, u8 *data,\n\t\t  u32 *size)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tif (!proc_status)\n\t\treturn HALMAC_RET_NULL_POINTER;\n\n\tswitch (feature_id) {\n\tcase HALMAC_FEATURE_CFG_PARA:\n\t\tstatus = get_cfg_param_status_88xx(adapter, proc_status);\n\t\tbreak;\n\tcase HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:\n\t\tstatus = get_dump_phy_efuse_status_88xx(adapter, proc_status,\n\t\t\t\t\t\t\tdata, size);\n\t\tbreak;\n\tcase HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:\n\t\tstatus = get_dump_log_efuse_status_88xx(adapter, proc_status,\n\t\t\t\t\t\t\tdata, size);\n\t\tbreak;\n\tcase HALMAC_FEATURE_CHANNEL_SWITCH:\n\t\tstatus = get_ch_switch_status_88xx(adapter, proc_status);\n\t\tbreak;\n\tcase HALMAC_FEATURE_UPDATE_PACKET:\n\t\tstatus = get_update_packet_status_88xx(adapter, proc_status);\n\t\tbreak;\n\tcase HALMAC_FEATURE_IQK:\n\t\tstatus = get_iqk_status_88xx(adapter, proc_status);\n\t\tbreak;\n\tcase HALMAC_FEATURE_POWER_TRACKING:\n\t\tstatus = get_pwr_trk_status_88xx(adapter, proc_status);\n\t\tbreak;\n\tcase HALMAC_FEATURE_PSD:\n\t\tstatus = get_psd_status_88xx(adapter, proc_status, data, size);\n\t\tbreak;\n\tcase HALMAC_FEATURE_FW_SNDING:\n\t\tstatus = get_fw_snding_status_88xx(adapter, proc_status);\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_INVALID_FEATURE_ID;\n\t}\n\n\treturn status;\n}\n\nstatic enum halmac_ret_status\nget_cfg_param_status_88xx(struct halmac_adapter *adapter,\n\t\t\t  enum halmac_cmd_process_status *proc_status)\n{\n\t*proc_status = adapter->halmac_state.cfg_param_state.proc_status;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nget_ch_switch_status_88xx(struct halmac_adapter *adapter,\n\t\t\t  enum halmac_cmd_process_status *proc_status)\n{\n\t*proc_status = adapter->halmac_state.scan_state.proc_status;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nget_update_packet_status_88xx(struct halmac_adapter *adapter,\n\t\t\t      enum halmac_cmd_process_status *proc_status)\n{\n\t*proc_status = adapter->halmac_state.update_pkt_state.proc_status;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfg_drv_rsvd_pg_num_88xx() -config reserved page number for driver\n * @adapter : the adapter of halmac\n * @pg_num : page number\n * Author : KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_drv_rsvd_pg_num_88xx(struct halmac_adapter *adapter,\n\t\t\t enum halmac_drv_rsvd_pg_num pg_num)\n{\n\tif (adapter->api_registry.cfg_drv_rsvd_pg_en == 0)\n\t\treturn HALMAC_RET_NOT_SUPPORT;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\tPLTFM_MSG_TRACE(\"[TRACE]pg_num = %d\\n\", pg_num);\n\n\tswitch (pg_num) {\n\tcase HALMAC_RSVD_PG_NUM8:\n\t\tadapter->txff_alloc.rsvd_drv_pg_num = 8;\n\t\tbreak;\n\tcase HALMAC_RSVD_PG_NUM16:\n\t\tadapter->txff_alloc.rsvd_drv_pg_num = 16;\n\t\tbreak;\n\tcase HALMAC_RSVD_PG_NUM24:\n\t\tadapter->txff_alloc.rsvd_drv_pg_num = 24;\n\t\tbreak;\n\tcase HALMAC_RSVD_PG_NUM32:\n\t\tadapter->txff_alloc.rsvd_drv_pg_num = 32;\n\t\tbreak;\n\tcase HALMAC_RSVD_PG_NUM64:\n\t\tadapter->txff_alloc.rsvd_drv_pg_num = 64;\n\t\tbreak;\n\tcase HALMAC_RSVD_PG_NUM128:\n\t\tadapter->txff_alloc.rsvd_drv_pg_num = 128;\n\t\tbreak;\n\tcase HALMAC_RSVD_PG_NUM256:\n\t\tadapter->txff_alloc.rsvd_drv_pg_num = 256;\n\t\tbreak;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * (debug API)h2c_lb_88xx() - send h2c loopback packet\n * @adapter : the adapter of halmac\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nh2c_lb_88xx(struct halmac_adapter *adapter)\n{\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\npwr_seq_parser_88xx(struct halmac_adapter *adapter,\n\t\t    struct halmac_wlan_pwr_cfg **cmd_seq)\n{\n\tu8 cut;\n\tu8 intf;\n\tu32 idx = 0;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tstruct halmac_wlan_pwr_cfg *cmd;\n\n\tswitch (adapter->chip_ver) {\n\tcase HALMAC_CHIP_VER_A_CUT:\n\t\tcut = HALMAC_PWR_CUT_A_MSK;\n\t\tbreak;\n\tcase HALMAC_CHIP_VER_B_CUT:\n\t\tcut = HALMAC_PWR_CUT_B_MSK;\n\t\tbreak;\n\tcase HALMAC_CHIP_VER_C_CUT:\n\t\tcut = HALMAC_PWR_CUT_C_MSK;\n\t\tbreak;\n\tcase HALMAC_CHIP_VER_D_CUT:\n\t\tcut = HALMAC_PWR_CUT_D_MSK;\n\t\tbreak;\n\tcase HALMAC_CHIP_VER_E_CUT:\n\t\tcut = HALMAC_PWR_CUT_E_MSK;\n\t\tbreak;\n\tcase HALMAC_CHIP_VER_F_CUT:\n\t\tcut = HALMAC_PWR_CUT_F_MSK;\n\t\tbreak;\n\tcase HALMAC_CHIP_VER_TEST:\n\t\tcut = HALMAC_PWR_CUT_TESTCHIP_MSK;\n\t\tbreak;\n\tdefault:\n\t\tPLTFM_MSG_ERR(\"[ERR]cut version!!\\n\");\n\t\treturn HALMAC_RET_SWITCH_CASE_ERROR;\n\t}\n\n\tswitch (adapter->intf) {\n\tcase HALMAC_INTERFACE_PCIE:\n\tcase HALMAC_INTERFACE_AXI:\n\t\tintf = HALMAC_PWR_INTF_PCI_MSK;\n\t\tbreak;\n\tcase HALMAC_INTERFACE_USB:\n\t\tintf = HALMAC_PWR_INTF_USB_MSK;\n\t\tbreak;\n\tcase HALMAC_INTERFACE_SDIO:\n\t\tintf = HALMAC_PWR_INTF_SDIO_MSK;\n\t\tbreak;\n\tdefault:\n\t\tPLTFM_MSG_ERR(\"[ERR]interface!!\\n\");\n\t\treturn HALMAC_RET_SWITCH_CASE_ERROR;\n\t}\n\n\tdo {\n\t\tcmd = cmd_seq[idx];\n\n\t\tif (!cmd)\n\t\t\tbreak;\n\n\t\tstatus = pwr_sub_seq_parser_88xx(adapter, cut, intf, cmd);\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]pwr sub seq!!\\n\");\n\t\t\treturn status;\n\t\t}\n\n\t\tidx++;\n\t} while (1);\n\n\treturn status;\n}\n\nstatic enum halmac_ret_status\npwr_sub_seq_parser_88xx(struct halmac_adapter *adapter, u8 cut, u8 intf,\n\t\t\tstruct halmac_wlan_pwr_cfg *cmd)\n{\n\tu8 value;\n\tu32 offset;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tdo {\n\t\tif ((cmd->interface_msk & intf) && (cmd->cut_msk & cut)) {\n\t\t\tswitch (cmd->cmd) {\n\t\t\tcase HALMAC_PWR_CMD_WRITE:\n\t\t\t\toffset = cmd->offset;\n\n\t\t\t\tif (cmd->base == HALMAC_PWR_ADDR_SDIO)\n\t\t\t\t\toffset |= SDIO_LOCAL_OFFSET;\n\n\t\t\t\tvalue = HALMAC_REG_R8(offset);\n\t\t\t\tvalue = (u8)(value & (u8)(~(cmd->msk)));\n\t\t\t\tvalue = (u8)(value | (cmd->value & cmd->msk));\n\n\t\t\t\tHALMAC_REG_W8(offset, value);\n\t\t\t\tbreak;\n\t\t\tcase HALMAC_PWR_CMD_POLLING:\n\t\t\t\tif (pwr_cmd_polling_88xx(adapter, cmd) !=\n\t\t\t\t    HALMAC_RET_SUCCESS)\n\t\t\t\t\treturn HALMAC_RET_PWRSEQ_POLLING_FAIL;\n\t\t\t\tbreak;\n\t\t\tcase HALMAC_PWR_CMD_DELAY:\n\t\t\t\tif (cmd->value == HALMAC_PWR_DELAY_US)\n\t\t\t\t\tPLTFM_DELAY_US(cmd->offset);\n\t\t\t\telse\n\t\t\t\t\tPLTFM_DELAY_US(1000 * cmd->offset);\n\t\t\t\tbreak;\n\t\t\tcase HALMAC_PWR_CMD_READ:\n\t\t\t\tbreak;\n\t\t\tcase HALMAC_PWR_CMD_END:\n\t\t\t\treturn HALMAC_RET_SUCCESS;\n\t\t\tdefault:\n\t\t\t\treturn HALMAC_RET_PWRSEQ_CMD_INCORRECT;\n\t\t\t}\n\t\t}\n\t\tcmd++;\n\t} while (1);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\npwr_cmd_polling_88xx(struct halmac_adapter *adapter,\n\t\t     struct halmac_wlan_pwr_cfg *cmd)\n{\n\tu8 value;\n\tu8 flg;\n\tu8 poll_bit;\n\tu32 offset;\n\tu32 cnt;\n\tstatic u32 stats;\n\tenum halmac_interface intf;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tpoll_bit = 0;\n\tcnt = HALMAC_PWR_POLLING_CNT;\n\tflg = 0;\n\tintf = adapter->intf;\n\n\tif (cmd->base == HALMAC_PWR_ADDR_SDIO)\n\t\toffset = cmd->offset | SDIO_LOCAL_OFFSET;\n\telse\n\t\toffset = cmd->offset;\n\n\tdo {\n\t\tcnt--;\n\t\tvalue = HALMAC_REG_R8(offset);\n\t\tvalue = (u8)(value & cmd->msk);\n\n\t\tif (value == (cmd->value & cmd->msk)) {\n\t\t\tpoll_bit = 1;\n\t\t} else {\n\t\t\tif (cnt == 0) {\n\t\t\t\tif (intf == HALMAC_INTERFACE_PCIE && flg == 0) {\n\t\t\t\t\t/* PCIE + USB package */\n\t\t\t\t\t/* power bit polling timeout issue */\n\t\t\t\t\tstats++;\n\t\t\t\t\tPLTFM_MSG_WARN(\"[WARN]PCIE stats:%d\\n\",\n\t\t\t\t\t\t       stats);\n\t\t\t\t\tvalue = HALMAC_REG_R8(REG_SYS_PW_CTRL);\n\t\t\t\t\tvalue |= BIT(3);\n\t\t\t\t\tHALMAC_REG_W8(REG_SYS_PW_CTRL, value);\n\t\t\t\t\tvalue &= ~BIT(3);\n\t\t\t\t\tHALMAC_REG_W8(REG_SYS_PW_CTRL, value);\n\t\t\t\t\tpoll_bit = 0;\n\t\t\t\t\tcnt = HALMAC_PWR_POLLING_CNT;\n\t\t\t\t\tflg = 1;\n\t\t\t\t} else {\n\t\t\t\t\tPLTFM_MSG_ERR(\"[ERR]polling to!!\\n\");\n\t\t\t\t\tPLTFM_MSG_ERR(\"[ERR]cmd offset:%X\\n\",\n\t\t\t\t\t\t      cmd->offset);\n\t\t\t\t\tPLTFM_MSG_ERR(\"[ERR]cmd value:%X\\n\",\n\t\t\t\t\t\t      cmd->value);\n\t\t\t\t\tPLTFM_MSG_ERR(\"[ERR]cmd msk:%X\\n\",\n\t\t\t\t\t\t      cmd->msk);\n\t\t\t\t\tPLTFM_MSG_ERR(\"[ERR]offset = %X\\n\",\n\t\t\t\t\t\t      offset);\n\t\t\t\t\tPLTFM_MSG_ERR(\"[ERR]value = %X\\n\",\n\t\t\t\t\t\t      value);\n\t\t\t\t\treturn HALMAC_RET_PWRSEQ_POLLING_FAIL;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tPLTFM_DELAY_US(50);\n\t\t\t}\n\t\t}\n\t} while (!poll_bit);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nparse_intf_phy_88xx(struct halmac_adapter *adapter,\n\t\t    struct halmac_intf_phy_para *param,\n\t\t    enum halmac_intf_phy_platform pltfm,\n\t\t    enum hal_intf_phy intf_phy)\n{\n\tu16 value;\n\tu16 cur_cut;\n\tu16 offset;\n\tu16 ip_sel;\n\tstruct halmac_intf_phy_para *cur_param;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tu8 result = HALMAC_RET_SUCCESS;\n\n\tswitch (adapter->chip_ver) {\n\tcase HALMAC_CHIP_VER_A_CUT:\n\t\tcur_cut = (u16)HALMAC_INTF_PHY_CUT_A;\n\t\tbreak;\n\tcase HALMAC_CHIP_VER_B_CUT:\n\t\tcur_cut = (u16)HALMAC_INTF_PHY_CUT_B;\n\t\tbreak;\n\tcase HALMAC_CHIP_VER_C_CUT:\n\t\tcur_cut = (u16)HALMAC_INTF_PHY_CUT_C;\n\t\tbreak;\n\tcase HALMAC_CHIP_VER_D_CUT:\n\t\tcur_cut = (u16)HALMAC_INTF_PHY_CUT_D;\n\t\tbreak;\n\tcase HALMAC_CHIP_VER_E_CUT:\n\t\tcur_cut = (u16)HALMAC_INTF_PHY_CUT_E;\n\t\tbreak;\n\tcase HALMAC_CHIP_VER_F_CUT:\n\t\tcur_cut = (u16)HALMAC_INTF_PHY_CUT_F;\n\t\tbreak;\n\tcase HALMAC_CHIP_VER_TEST:\n\t\tcur_cut = (u16)HALMAC_INTF_PHY_CUT_TESTCHIP;\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_FAIL;\n\t}\n\n\tcur_param = param;\n\n\tdo {\n\t\tif ((cur_param->cut & cur_cut) &&\n\t\t    (cur_param->plaform & (u16)pltfm)) {\n\t\t\toffset =  cur_param->offset;\n\t\t\tvalue = cur_param->value;\n\t\t\tip_sel = cur_param->ip_sel;\n\n\t\t\tif (offset == 0xFFFF)\n\t\t\t\tbreak;\n\n\t\t\tif (ip_sel == HALMAC_IP_SEL_MAC) {\n\t\t\t\tHALMAC_REG_W8((u32)offset, (u8)value);\n\t\t\t} else if (intf_phy == HAL_INTF_PHY_USB2 ||\n\t\t\t\t   intf_phy == HAL_INTF_PHY_USB3) {\n#if HALMAC_USB_SUPPORT\n\t\t\t\tresult = usbphy_write_88xx(adapter, (u8)offset,\n\t\t\t\t\t\t\t   value, intf_phy);\n\t\t\t\tif (result != HALMAC_RET_SUCCESS)\n\t\t\t\t\tPLTFM_MSG_ERR(\"[ERR]usb phy!!\\n\");\n#endif\n\t\t\t} else if (intf_phy == HAL_INTF_PHY_PCIE_GEN1 ||\n\t\t\t\t   intf_phy == HAL_INTF_PHY_PCIE_GEN2) {\n#if HALMAC_PCIE_SUPPORT\n\t\t\t\tif (ip_sel == HALMAC_IP_INTF_PHY)\n\t\t\t\t\tresult = mdio_write_88xx(adapter,\n\t\t\t\t\t\t\t\t (u8)offset,\n\t\t\t\t\t\t\t\t value,\n\t\t\t\t\t\t\t\t intf_phy);\n\t\t\t\telse\n\t\t\t\t\tresult = dbi_w8_88xx(adapter, offset,\n\t\t\t\t\t\t\t     (u8)value);\n\t\t\t\tif (result != HALMAC_RET_SUCCESS)\n\t\t\t\t\tPLTFM_MSG_ERR(\"[ERR]mdio/dbi!!\\n\");\n#endif\n\t\t\t} else {\n\t\t\t\tPLTFM_MSG_ERR(\"[ERR]intf phy sel!!\\n\");\n\t\t\t}\n\t\t}\n\t\tcur_param++;\n\t} while (1);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * txfifo_is_empty_88xx() -check if txfifo is empty\n * @adapter : the adapter of halmac\n * @chk_num : check number\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ntxfifo_is_empty_88xx(struct halmac_adapter *adapter, u32 chk_num)\n{\n\tu32 cnt;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tcnt = (chk_num <= 10) ? 10 : chk_num;\n\tdo {\n\t\tif (HALMAC_REG_R8(REG_TXPKT_EMPTY) != 0xFF)\n\t\t\treturn HALMAC_RET_TXFIFO_NO_EMPTY;\n\n\t\tif ((HALMAC_REG_R8(REG_TXPKT_EMPTY + 1) & 0x06) != 0x06)\n\t\t\treturn HALMAC_RET_TXFIFO_NO_EMPTY;\n\t\tcnt--;\n\n\t} while (cnt != 0);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * (internal use)\n * smart_malloc_88xx() - adapt malloc size\n * @adapter : the adapter of halmac\n * @size : expected malloc size\n * @pNew_size : real malloc size\n * Author : Ivan Lin\n * Return : address pointer\n */\nu8*\nsmart_malloc_88xx(struct halmac_adapter *adapter, u32 size, u32 *new_size)\n{\n\tu8 retry_num;\n\tu8 *malloc_buf = NULL;\n\n\tfor (retry_num = 0; retry_num < 5; retry_num++) {\n\t\tmalloc_buf = (u8 *)PLTFM_MALLOC(size);\n\n\t\tif (malloc_buf) {\n\t\t\t*new_size = size;\n\t\t\treturn malloc_buf;\n\t\t}\n\n\t\tsize = size >> 1;\n\n\t\tif (size == 0)\n\t\t\tbreak;\n\t}\n\n\tPLTFM_MSG_ERR(\"[ERR]adptive malloc!!\\n\");\n\n\treturn NULL;\n}\n\n/**\n * (internal use)\n * ltecoex_reg_read_88xx() - read ltecoex register\n * @adapter : the adapter of halmac\n * @offset : offset\n * @pValue : value\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n */\nenum halmac_ret_status\nltecoex_reg_read_88xx(struct halmac_adapter *adapter, u16 offset, u32 *value)\n{\n\tu32 cnt;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tcnt = 10000;\n\twhile ((HALMAC_REG_R8(LTECOEX_ACCESS_CTRL + 3) & BIT(5)) == 0) {\n\t\tif (cnt == 0) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]lte ready(R)\\n\");\n\t\t\treturn HALMAC_RET_LTECOEX_READY_FAIL;\n\t\t}\n\t\tcnt--;\n\t\tPLTFM_DELAY_US(50);\n\t}\n\n\tHALMAC_REG_W32(LTECOEX_ACCESS_CTRL, 0x800F0000 | offset);\n\t*value = HALMAC_REG_R32(REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * (internal use)\n * ltecoex_reg_write_88xx() - write ltecoex register\n * @adapter : the adapter of halmac\n * @offset : offset\n * @value : value\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n */\nenum halmac_ret_status\nltecoex_reg_write_88xx(struct halmac_adapter *adapter, u16 offset, u32 value)\n{\n\tu32 cnt;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tcnt = 10000;\n\twhile ((HALMAC_REG_R8(LTECOEX_ACCESS_CTRL + 3) & BIT(5)) == 0) {\n\t\tif (cnt == 0) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]lte ready(W)\\n\");\n\t\t\treturn HALMAC_RET_LTECOEX_READY_FAIL;\n\t\t}\n\t\tcnt--;\n\t\tPLTFM_DELAY_US(50);\n\t}\n\n\tHALMAC_REG_W32(REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1, value);\n\tHALMAC_REG_W32(LTECOEX_ACCESS_CTRL, 0xC00F0000 | offset);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic void\npwr_state_88xx(struct halmac_adapter *adapter, enum halmac_mac_power *state)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tif ((HALMAC_REG_R8(REG_SYS_FUNC_EN + 1) & BIT(3)) == 0)\n\t\t*state = HALMAC_MAC_POWER_OFF;\n\telse\n\t\t*state = HALMAC_MAC_POWER_ON;\n}\n\nstatic u8\npacket_in_nlo_88xx(struct halmac_adapter *adapter,\n\t\t   enum halmac_packet_id pkt_id)\n{\n\tenum halmac_packet_id nlo_pkt = HALMAC_PACKET_PROBE_REQ_NLO;\n\n\tif (pkt_id >= nlo_pkt)\n\t\treturn 1;\n\telse\n\t\treturn 0;\n}\n\nstatic enum halmac_packet_id\nget_real_pkt_id_88xx(struct halmac_adapter *adapter,\n\t\t     enum halmac_packet_id pkt_id)\n{\n\tenum halmac_packet_id real_pkt_id;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tswitch (pkt_id) {\n\tcase HALMAC_PACKET_PROBE_REQ_NLO:\n\t\treal_pkt_id = HALMAC_PACKET_PROBE_REQ;\n\t\tbreak;\n\tcase HALMAC_PACKET_SYNC_BCN_NLO:\n\t\treal_pkt_id = HALMAC_PACKET_SYNC_BCN;\n\t\tbreak;\n\tcase HALMAC_PACKET_DISCOVERY_BCN_NLO:\n\t\treal_pkt_id = HALMAC_PACKET_DISCOVERY_BCN;\n\t\tbreak;\n\tdefault:\n\t\treal_pkt_id = pkt_id;\n\t}\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\treturn real_pkt_id;\n}\n\n#endif /* HALMAC_88XX_SUPPORT */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_common_88xx.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_COMMON_88XX_H_\n#define _HALMAC_COMMON_88XX_H_\n\n#include \"../halmac_api.h\"\n#include \"../halmac_pwr_seq_cmd.h\"\n#include \"../halmac_gpio_cmd.h\"\n\n#if HALMAC_88XX_SUPPORT\n\nenum halmac_ret_status\nofld_func_cfg_88xx(struct halmac_adapter *adapter,\n\t\t   struct halmac_ofld_func_info *info);\n\nenum halmac_ret_status\ndl_drv_rsvd_page_88xx(struct halmac_adapter *adapter, u8 pg_offset, u8 *buf,\n\t\t      u32 size);\n\nenum halmac_ret_status\ndl_rsvd_page_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *buf,\n\t\t  u32 size);\n\nenum halmac_ret_status\nget_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,\n\t\t  void *value);\n\nenum halmac_ret_status\nset_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,\n\t\t  void *value);\n\nenum halmac_ret_status\nset_h2c_pkt_hdr_88xx(struct halmac_adapter *adapter, u8 *hdr,\n\t\t     struct halmac_h2c_header_info *info, u16 *seq_num);\n\nenum halmac_ret_status\nsend_h2c_pkt_88xx(struct halmac_adapter *adapter, u8 *pkt);\n\nenum halmac_ret_status\nget_h2c_buf_free_space_88xx(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\nget_c2h_info_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\nenum halmac_ret_status\nmac_debug_88xx(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\ncfg_parameter_88xx(struct halmac_adapter *adapter,\n\t\t   struct halmac_phy_parameter_info *info, u8 full_fifo);\n\nenum halmac_ret_status\nupdate_packet_88xx(struct halmac_adapter *adapter, enum halmac_packet_id pkt_id,\n\t\t   u8 *pkt, u32 size);\n\nenum halmac_ret_status\nbcn_ie_filter_88xx(struct halmac_adapter *adapter,\n\t\t   struct halmac_bcn_ie_info *info);\n\nenum halmac_ret_status\nupdate_datapack_88xx(struct halmac_adapter *adapter,\n\t\t     enum halmac_data_type data_type,\n\t\t     struct halmac_phy_parameter_info *info);\n\nenum halmac_ret_status\nrun_datapack_88xx(struct halmac_adapter *adapter,\n\t\t  enum halmac_data_type data_type);\n\nenum halmac_ret_status\nsend_bt_coex_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, u8 ack);\n\nenum halmac_ret_status\ndump_fifo_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel,\n\t       u32 start_addr, u32 size, u8 *data);\n\nu32\nget_fifo_size_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel);\n\nenum halmac_ret_status\nset_h2c_header_88xx(struct halmac_adapter *adapter, u8 *hdr, u16 *seq, u8 ack);\n\nenum halmac_ret_status\nadd_ch_info_88xx(struct halmac_adapter *adapter, struct halmac_ch_info *info);\n\nenum halmac_ret_status\nadd_extra_ch_info_88xx(struct halmac_adapter *adapter,\n\t\t       struct halmac_ch_extra_info *info);\n\nenum halmac_ret_status\nctrl_ch_switch_88xx(struct halmac_adapter *adapter,\n\t\t    struct halmac_ch_switch_option *opt);\n\nenum halmac_ret_status\nclear_ch_info_88xx(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\nchk_txdesc_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\nenum halmac_ret_status\nget_version_88xx(struct halmac_adapter *adapter, struct halmac_ver *ver);\n\nenum halmac_ret_status\np2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info);\n\nenum halmac_ret_status\nquery_status_88xx(struct halmac_adapter *adapter,\n\t\t  enum halmac_feature_id feature_id,\n\t\t  enum halmac_cmd_process_status *proc_status, u8 *data,\n\t\t  u32 *size);\n\nenum halmac_ret_status\ncfg_drv_rsvd_pg_num_88xx(struct halmac_adapter *adapter,\n\t\t\t enum halmac_drv_rsvd_pg_num pg_num);\n\nenum halmac_ret_status\nh2c_lb_88xx(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\npwr_seq_parser_88xx(struct halmac_adapter *adapter,\n\t\t    struct halmac_wlan_pwr_cfg **cmd_seq);\n\nenum halmac_ret_status\nparse_intf_phy_88xx(struct halmac_adapter *adapter,\n\t\t    struct halmac_intf_phy_para *param,\n\t\t    enum halmac_intf_phy_platform pltfm,\n\t\t    enum hal_intf_phy intf_phy);\n\nenum halmac_ret_status\ntxfifo_is_empty_88xx(struct halmac_adapter *adapter, u32 chk_num);\n\nu8*\nsmart_malloc_88xx(struct halmac_adapter *adapter, u32 size, u32 *new_size);\n\nenum halmac_ret_status\nltecoex_reg_read_88xx(struct halmac_adapter *adapter, u16 offset, u32 *value);\n\nenum halmac_ret_status\nltecoex_reg_write_88xx(struct halmac_adapter *adapter, u16 offset, u32 value);\n\n#endif/* HALMAC_88XX_SUPPORT */\n\n#endif/* _HALMAC_COMMON_88XX_H_ */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_efuse_88xx.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"halmac_efuse_88xx.h\"\n#include \"halmac_88xx_cfg.h\"\n#include \"halmac_common_88xx.h\"\n#include \"halmac_init_88xx.h\"\n\n#if HALMAC_88XX_SUPPORT\n\n#define RSVD_EFUSE_SIZE\t\t16\n#define RSVD_CS_EFUSE_SIZE\t24\n#define FEATURE_DUMP_PHY_EFUSE\tHALMAC_FEATURE_DUMP_PHYSICAL_EFUSE\n#define FEATURE_DUMP_LOG_EFUSE\tHALMAC_FEATURE_DUMP_LOGICAL_EFUSE\n\nstatic enum halmac_cmd_construct_state\nefuse_cmd_cnstr_state_88xx(struct halmac_adapter *adapter);\n\nstatic enum halmac_ret_status\nproc_dump_efuse_88xx(struct halmac_adapter *adapter,\n\t\t     enum halmac_efuse_read_cfg cfg);\n\nstatic enum halmac_ret_status\nread_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,\n\t\t   u8 *map);\n\nstatic enum halmac_ret_status\nread_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map);\n\nstatic enum halmac_ret_status\nproc_pg_efuse_by_map_88xx(struct halmac_adapter *adapter,\n\t\t\t  struct halmac_pg_efuse_info *info,\n\t\t\t  enum halmac_efuse_read_cfg cfg);\n\nstatic enum halmac_ret_status\ndump_efuse_fw_88xx(struct halmac_adapter *adapter);\n\nstatic enum halmac_ret_status\ndump_efuse_drv_88xx(struct halmac_adapter *adapter);\n\nstatic enum halmac_ret_status\nproc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);\n\nstatic enum halmac_ret_status\nupdate_eeprom_mask_88xx(struct halmac_adapter *adapter,\n\t\t\tstruct halmac_pg_efuse_info *info, u8 *updated_mask);\n\nstatic enum halmac_ret_status\ncheck_efuse_enough_88xx(struct halmac_adapter *adapter,\n\t\t\tstruct halmac_pg_efuse_info *info, u8 *updated_mask);\n\nstatic enum halmac_ret_status\npg_extend_efuse_88xx(struct halmac_adapter *adapter,\n\t\t     struct halmac_pg_efuse_info *info, u8 word_en,\n\t\t     u8 pre_word_en, u32 eeprom_offset);\n\nstatic enum halmac_ret_status\nproc_pg_efuse_88xx(struct halmac_adapter *adapter,\n\t\t   struct halmac_pg_efuse_info *info, u8 word_en,\n\t\t   u8 pre_word_en, u32 eeprom_offset);\n\nstatic enum halmac_ret_status\nprogram_efuse_88xx(struct halmac_adapter *adapter,\n\t\t   struct halmac_pg_efuse_info *info, u8 *updated_mask);\n\nstatic void\nmask_eeprom_88xx(struct halmac_adapter *adapter,\n\t\t struct halmac_pg_efuse_info *info);\n\n/**\n * dump_efuse_map_88xx() - dump \"physical\" efuse map\n * @adapter : the adapter of halmac\n * @cfg : dump efuse method\n * Author : Ivan Lin/KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ndump_efuse_map_88xx(struct halmac_adapter *adapter,\n\t\t    enum halmac_efuse_read_cfg cfg)\n{\n\tu8 *map = NULL;\n\tu8 *efuse_map;\n\tu32 efuse_size = adapter->hw_cfg_info.efuse_size;\n\tu32 prtct_efuse_size = adapter->hw_cfg_info.prtct_efuse_size;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tenum halmac_cmd_process_status *proc_status;\n\n\tproc_status = &adapter->halmac_state.efuse_state.proc_status;\n\n\tif (cfg == HALMAC_EFUSE_R_FW &&\n\t    halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_NO_DLFW;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\tPLTFM_MSG_TRACE(\"[TRACE]cfg = %d\\n\", cfg);\n\n\tif (*proc_status == HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_WARN(\"[WARN]Wait event(efuse)\\n\");\n\t\treturn HALMAC_RET_BUSY_STATE;\n\t}\n\n\tif (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {\n\t\tPLTFM_MSG_WARN(\"[WARN]Not idle(efuse)\\n\");\n\t\treturn HALMAC_RET_ERROR_STATE;\n\t}\n\n\tif (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF)\n\t\tPLTFM_MSG_ERR(\"[ERR]Dump efuse in suspend\\n\");\n\n\t*proc_status = HALMAC_CMD_PROCESS_IDLE;\n\tadapter->evnt.phy_efuse_map = 1;\n\n\tstatus = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]switch efuse bank!!\\n\");\n\t\treturn status;\n\t}\n\n\tstatus = proc_dump_efuse_88xx(adapter, cfg);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]dump efuse!!\\n\");\n\t\treturn status;\n\t}\n\n\tif (adapter->efuse_map_valid == 1) {\n\t\t*proc_status = HALMAC_CMD_PROCESS_DONE;\n\t\tefuse_map = adapter->efuse_map;\n\n\t\tmap = (u8 *)PLTFM_MALLOC(efuse_size);\n\t\tif (!map) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]malloc!!\\n\");\n\t\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t\t}\n\t\tPLTFM_MEMSET(map, 0xFF, efuse_size);\n\t\tPLTFM_MUTEX_LOCK(&adapter->efuse_mutex);\n#if HALMAC_PLATFORM_WINDOWS\n\t\tPLTFM_MEMCPY(map, efuse_map, efuse_size);\n#else\n\t\tPLTFM_MEMCPY(map, efuse_map, efuse_size - prtct_efuse_size);\n\t\tPLTFM_MEMCPY(map + efuse_size - prtct_efuse_size +\n\t\t\t     RSVD_CS_EFUSE_SIZE,\n\t\t\t     efuse_map + efuse_size - prtct_efuse_size +\n\t\t\t     RSVD_CS_EFUSE_SIZE,\n\t\t\t     prtct_efuse_size - RSVD_EFUSE_SIZE -\n\t\t\t     RSVD_CS_EFUSE_SIZE);\n#endif\n\t\tPLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);\n\n\t\tPLTFM_EVENT_SIG(HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE,\n\t\t\t\t*proc_status, map, efuse_size);\n\t\tadapter->evnt.phy_efuse_map = 0;\n\n\t\tPLTFM_FREE(map, efuse_size);\n\t}\n\n\tif (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * dump_efuse_map_bt_88xx() - dump \"BT physical\" efuse map\n * @adapter : the adapter of halmac\n * @bank : bt efuse bank\n * @size : bt efuse map size. get from halmac_get_efuse_size API\n * @map : bt efuse map\n * Author : Soar / Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ndump_efuse_map_bt_88xx(struct halmac_adapter *adapter,\n\t\t       enum halmac_efuse_bank bank, u32 size, u8 *map)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tenum halmac_cmd_process_status *proc_status;\n\n\tproc_status = &adapter->halmac_state.efuse_state.proc_status;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (adapter->hw_cfg_info.bt_efuse_size != size)\n\t\treturn HALMAC_RET_EFUSE_SIZE_INCORRECT;\n\n\tif (bank >= HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) {\n\t\tPLTFM_MSG_ERR(\"[ERR]Undefined BT bank\\n\");\n\t\treturn HALMAC_RET_EFUSE_BANK_INCORRECT;\n\t}\n\n\tif (*proc_status == HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_WARN(\"[WARN]Wait event(efuse)\\n\");\n\t\treturn HALMAC_RET_BUSY_STATE;\n\t}\n\n\tif (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {\n\t\tPLTFM_MSG_WARN(\"[WARN]Not idle(efuse)\\n\");\n\t\treturn HALMAC_RET_ERROR_STATE;\n\t}\n\n\tstatus = switch_efuse_bank_88xx(adapter, bank);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]switch efuse bank!!\\n\");\n\t\treturn status;\n\t}\n\n\tstatus = read_hw_efuse_88xx(adapter, 0, size, map);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]read hw efuse\\n\");\n\t\treturn status;\n\t}\n\n\tif (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * write_efuse_bt_88xx() - write \"BT physical\" efuse offset\n * @adapter : the adapter of halmac\n * @offset : offset\n * @value : Write value\n * @map : bt efuse map\n * Author : Soar\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nwrite_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 value,\n\t\t    enum halmac_efuse_bank bank)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tenum halmac_cmd_process_status *proc_status;\n\n\tproc_status = &adapter->halmac_state.efuse_state.proc_status;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (*proc_status == HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_WARN(\"[WARN]Wait event(efuse)\\n\");\n\t\treturn HALMAC_RET_BUSY_STATE;\n\t}\n\n\tif (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {\n\t\tPLTFM_MSG_WARN(\"[WARN]Not idle(efuse)\\n\");\n\t\treturn HALMAC_RET_ERROR_STATE;\n\t}\n\n\tif (offset >= adapter->hw_cfg_info.efuse_size) {\n\t\tPLTFM_MSG_ERR(\"[ERR]Offset is too large\\n\");\n\t\treturn HALMAC_RET_EFUSE_SIZE_INCORRECT;\n\t}\n\n\tif (bank > HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) {\n\t\tPLTFM_MSG_ERR(\"[ERR]Undefined BT bank\\n\");\n\t\treturn HALMAC_RET_EFUSE_BANK_INCORRECT;\n\t}\n\n\tstatus = switch_efuse_bank_88xx(adapter, bank);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]switch efuse bank!!\\n\");\n\t\treturn status;\n\t}\n\n\tstatus = write_hw_efuse_88xx(adapter, offset, value);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]write efuse\\n\");\n\t\treturn status;\n\t}\n\n\tif (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * read_efuse_bt_88xx() - read \"BT physical\" efuse offset\n * @adapter : the adapter of halmac\n * @offset : offset\n * @value : 1 byte efuse value\n * @bank : efuse bank\n * Author : Soar\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nread_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value,\n\t\t   enum halmac_efuse_bank bank)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tenum halmac_cmd_process_status *proc_status;\n\n\tproc_status = &adapter->halmac_state.efuse_state.proc_status;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (*proc_status == HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_WARN(\"[WARN]Wait event(efuse)\\n\");\n\t\treturn HALMAC_RET_BUSY_STATE;\n\t}\n\n\tif (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {\n\t\tPLTFM_MSG_WARN(\"[WARN]Not idle(efuse)\\n\");\n\t\treturn HALMAC_RET_ERROR_STATE;\n\t}\n\n\tif (offset >= adapter->hw_cfg_info.efuse_size) {\n\t\tPLTFM_MSG_ERR(\"[ERR]Offset is too large\\n\");\n\t\treturn HALMAC_RET_EFUSE_SIZE_INCORRECT;\n\t}\n\n\tif (bank > HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) {\n\t\tPLTFM_MSG_ERR(\"[ERR]Undefined BT bank\\n\");\n\t\treturn HALMAC_RET_EFUSE_BANK_INCORRECT;\n\t}\n\n\tstatus = switch_efuse_bank_88xx(adapter, bank);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]switch efuse bank\\n\");\n\t\treturn status;\n\t}\n\n\tstatus = read_efuse_88xx(adapter, offset, 1, value);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]read efuse\\n\");\n\t\treturn status;\n\t}\n\n\tif (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfg_efuse_auto_check_88xx() - check efuse after writing it\n * @adapter : the adapter of halmac\n * @enable : 1, enable efuse auto check. others, disable\n * Author : Soar\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_efuse_auto_check_88xx(struct halmac_adapter *adapter, u8 enable)\n{\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tadapter->efuse_auto_check_en = enable;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * get_efuse_available_size_88xx() - get efuse available size\n * @adapter : the adapter of halmac\n * @size : physical efuse available size\n * Author : Soar\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nget_efuse_available_size_88xx(struct halmac_adapter *adapter, u32 *size)\n{\n\tenum halmac_ret_status status;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tstatus = dump_log_efuse_map_88xx(adapter, HALMAC_EFUSE_R_DRV);\n\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\t*size = adapter->hw_cfg_info.efuse_size -\n\t\tadapter->hw_cfg_info.prtct_efuse_size -\tadapter->efuse_end;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * get_efuse_size_88xx() - get \"physical\" efuse size\n * @adapter : the adapter of halmac\n * @size : physical efuse size\n * Author : Ivan Lin/KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nget_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size)\n{\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\t*size = adapter->hw_cfg_info.efuse_size;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * get_log_efuse_size_88xx() - get \"logical\" efuse size\n * @adapter : the adapter of halmac\n * @size : logical efuse size\n * Author : Ivan Lin/KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nget_log_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size)\n{\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\t*size = adapter->hw_cfg_info.eeprom_size;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * dump_log_efuse_map_88xx() - dump \"logical\" efuse map\n * @adapter : the adapter of halmac\n * @cfg : dump efuse method\n * Author : Soar\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ndump_log_efuse_map_88xx(struct halmac_adapter *adapter,\n\t\t\tenum halmac_efuse_read_cfg cfg)\n{\n\tu8 *map = NULL;\n\tu32 size = adapter->hw_cfg_info.eeprom_size;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tenum halmac_cmd_process_status *proc_status;\n\n\tproc_status = &adapter->halmac_state.efuse_state.proc_status;\n\n\tif (cfg == HALMAC_EFUSE_R_FW &&\n\t    halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_NO_DLFW;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\tPLTFM_MSG_TRACE(\"[TRACE]cfg = %d\\n\", cfg);\n\n\tif (*proc_status == HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_WARN(\"[WARN]Wait event(efuse)\\n\");\n\t\treturn HALMAC_RET_BUSY_STATE;\n\t}\n\n\tif (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {\n\t\tPLTFM_MSG_WARN(\"[WARN]Not idle(efuse)\\n\");\n\t\treturn HALMAC_RET_ERROR_STATE;\n\t}\n\n\tif (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF)\n\t\tPLTFM_MSG_ERR(\"[ERR]Dump efuse in suspend\\n\");\n\n\t*proc_status = HALMAC_CMD_PROCESS_IDLE;\n\tadapter->evnt.log_efuse_map = 1;\n\n\tstatus = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]switch efuse bank\\n\");\n\t\treturn status;\n\t}\n\n\tstatus = proc_dump_efuse_88xx(adapter, cfg);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]dump efuse\\n\");\n\t\treturn status;\n\t}\n\n\tif (adapter->efuse_map_valid == 1) {\n\t\t*proc_status = HALMAC_CMD_PROCESS_DONE;\n\n\t\tmap = (u8 *)PLTFM_MALLOC(size);\n\t\tif (!map) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]malloc map\\n\");\n\t\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t\t}\n\t\tPLTFM_MEMSET(map, 0xFF, size);\n\n\t\tif (eeprom_parser_88xx(adapter, adapter->efuse_map, map) !=\n\t\t    HALMAC_RET_SUCCESS) {\n\t\t\tPLTFM_FREE(map, size);\n\t\t\treturn HALMAC_RET_EEPROM_PARSING_FAIL;\n\t\t}\n\n\t\tPLTFM_EVENT_SIG(HALMAC_FEATURE_DUMP_LOGICAL_EFUSE,\n\t\t\t\t*proc_status, map, size);\n\t\tadapter->evnt.log_efuse_map = 0;\n\n\t\tPLTFM_FREE(map, size);\n\t}\n\n\tif (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * read_logical_efuse_88xx() - read logical efuse map 1 byte\n * @adapter : the adapter of halmac\n * @offset : offset\n * @value : 1 byte efuse value\n * Author : Soar\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nread_logical_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value)\n{\n\tu8 *map = NULL;\n\tu32 size = adapter->hw_cfg_info.eeprom_size;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tenum halmac_cmd_process_status *proc_status;\n\n\tproc_status = &adapter->halmac_state.efuse_state.proc_status;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (offset >= size) {\n\t\tPLTFM_MSG_ERR(\"[ERR]Offset is too large\\n\");\n\t\treturn HALMAC_RET_EFUSE_SIZE_INCORRECT;\n\t}\n\n\tif (*proc_status == HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_WARN(\"[WARN]Wait event(efuse)\\n\");\n\t\treturn HALMAC_RET_BUSY_STATE;\n\t}\n\tif (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {\n\t\tPLTFM_MSG_WARN(\"[WARN]Not idle(efuse)\\n\");\n\t\treturn HALMAC_RET_ERROR_STATE;\n\t}\n\n\tstatus = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]switch efuse bank\\n\");\n\t\treturn status;\n\t}\n\n\tmap = (u8 *)PLTFM_MALLOC(size);\n\tif (!map) {\n\t\tPLTFM_MSG_ERR(\"[ERR]malloc map\\n\");\n\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t}\n\tPLTFM_MEMSET(map, 0xFF, size);\n\n\tstatus = read_log_efuse_map_88xx(adapter, map);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]read logical efuse\\n\");\n\t\tPLTFM_FREE(map, size);\n\t\treturn status;\n\t}\n\n\t*value = *(map + offset);\n\n\tif (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=\n\t    HALMAC_RET_SUCCESS) {\n\t\tPLTFM_FREE(map, size);\n\t\treturn HALMAC_RET_ERROR_STATE;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\tPLTFM_FREE(map, size);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * write_log_efuse_88xx() - write \"logical\" efuse offset\n * @adapter : the adapter of halmac\n * @offset : offset\n * @value : value\n * Author : Soar\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nwrite_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tenum halmac_cmd_process_status *proc_status;\n\n\tproc_status = &adapter->halmac_state.efuse_state.proc_status;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (offset >= adapter->hw_cfg_info.eeprom_size) {\n\t\tPLTFM_MSG_ERR(\"[ERR]Offset is too large\\n\");\n\t\treturn HALMAC_RET_EFUSE_SIZE_INCORRECT;\n\t}\n\n\tif (*proc_status == HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_WARN(\"[WARN]Wait event(efuse)\\n\");\n\t\treturn HALMAC_RET_BUSY_STATE;\n\t}\n\n\tif (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {\n\t\tPLTFM_MSG_WARN(\"[WARN]Not idle(efuse)\\n\");\n\t\treturn HALMAC_RET_ERROR_STATE;\n\t}\n\n\tstatus = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]switch efuse bank\\n\");\n\t\treturn status;\n\t}\n\n\tstatus = proc_write_log_efuse_88xx(adapter, offset, value);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]write logical efuse\\n\");\n\t\treturn status;\n\t}\n\n\tif (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * pg_efuse_by_map_88xx() - pg logical efuse by map\n * @adapter : the adapter of halmac\n * @info : efuse map information\n * @cfg : dump efuse method\n * Author : Soar\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\npg_efuse_by_map_88xx(struct halmac_adapter *adapter,\n\t\t     struct halmac_pg_efuse_info *info,\n\t\t     enum halmac_efuse_read_cfg cfg)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tenum halmac_cmd_process_status *proc_status;\n\n\tproc_status = &adapter->halmac_state.efuse_state.proc_status;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (info->efuse_map_size != adapter->hw_cfg_info.eeprom_size) {\n\t\tPLTFM_MSG_ERR(\"[ERR]map size error\\n\");\n\t\treturn HALMAC_RET_EFUSE_SIZE_INCORRECT;\n\t}\n\n\tif ((info->efuse_map_size & 0xF) > 0) {\n\t\tPLTFM_MSG_ERR(\"[ERR]not multiple of 16\\n\");\n\t\treturn HALMAC_RET_EFUSE_SIZE_INCORRECT;\n\t}\n\n\tif (info->efuse_mask_size != info->efuse_map_size >> 4) {\n\t\tPLTFM_MSG_ERR(\"[ERR]mask size error\\n\");\n\t\treturn HALMAC_RET_EFUSE_SIZE_INCORRECT;\n\t}\n\n\tif (!info->efuse_map) {\n\t\tPLTFM_MSG_ERR(\"[ERR]map is NULL\\n\");\n\t\treturn HALMAC_RET_NULL_POINTER;\n\t}\n\n\tif (!info->efuse_mask) {\n\t\tPLTFM_MSG_ERR(\"[ERR]mask is NULL\\n\");\n\t\treturn HALMAC_RET_NULL_POINTER;\n\t}\n\n\tif (*proc_status == HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_WARN(\"[WARN]Wait event(efuse)\\n\");\n\t\treturn HALMAC_RET_BUSY_STATE;\n\t}\n\n\tif (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {\n\t\tPLTFM_MSG_WARN(\"[WARN]Not idle(efuse)\\n\");\n\t\treturn HALMAC_RET_ERROR_STATE;\n\t}\n\n\tstatus = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]switch efuse bank\\n\");\n\t\treturn status;\n\t}\n\n\tstatus = proc_pg_efuse_by_map_88xx(adapter, info, cfg);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]pg efuse\\n\");\n\t\treturn status;\n\t}\n\n\tif (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * mask_log_efuse_88xx() - mask logical efuse\n * @adapter : the adapter of halmac\n * @info : efuse map information\n * Author : Soar\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nmask_log_efuse_88xx(struct halmac_adapter *adapter,\n\t\t    struct halmac_pg_efuse_info *info)\n{\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (info->efuse_map_size != adapter->hw_cfg_info.eeprom_size) {\n\t\tPLTFM_MSG_ERR(\"[ERR]map size error\\n\");\n\t\treturn HALMAC_RET_EFUSE_SIZE_INCORRECT;\n\t}\n\n\tif ((info->efuse_map_size & 0xF) > 0) {\n\t\tPLTFM_MSG_ERR(\"[ERR]not multiple of 16\\n\");\n\t\treturn HALMAC_RET_EFUSE_SIZE_INCORRECT;\n\t}\n\n\tif (info->efuse_mask_size != info->efuse_map_size >> 4) {\n\t\tPLTFM_MSG_ERR(\"[ERR]mask size error\\n\");\n\t\treturn HALMAC_RET_EFUSE_SIZE_INCORRECT;\n\t}\n\n\tif (!info->efuse_map) {\n\t\tPLTFM_MSG_ERR(\"[ERR]map is NULL\\n\");\n\t\treturn HALMAC_RET_NULL_POINTER;\n\t}\n\n\tif (!info->efuse_mask) {\n\t\tPLTFM_MSG_ERR(\"[ERR]mask is NULL\\n\");\n\t\treturn HALMAC_RET_NULL_POINTER;\n\t}\n\n\tmask_eeprom_88xx(adapter, info);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_cmd_construct_state\nefuse_cmd_cnstr_state_88xx(struct halmac_adapter *adapter)\n{\n\treturn adapter->halmac_state.efuse_state.cmd_cnstr_state;\n}\n\nenum halmac_ret_status\nswitch_efuse_bank_88xx(struct halmac_adapter *adapter,\n\t\t       enum halmac_efuse_bank bank)\n{\n\tu8 reg_value;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tif (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_BUSY) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\treg_value = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 1);\n\n\tif (bank == (reg_value & (BIT(0) | BIT(1))))\n\t\treturn HALMAC_RET_SUCCESS;\n\n\treg_value &= ~(BIT(0) | BIT(1));\n\treg_value |= bank;\n\tHALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 1, reg_value);\n\n\treg_value = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 1);\n\tif ((reg_value & (BIT(0) | BIT(1))) != bank)\n\t\treturn HALMAC_RET_SWITCH_EFUSE_BANK_FAIL;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nproc_dump_efuse_88xx(struct halmac_adapter *adapter,\n\t\t     enum halmac_efuse_read_cfg cfg)\n{\n\tu32 h2c_init;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tenum halmac_cmd_process_status *proc_status;\n\n\tproc_status = &adapter->halmac_state.efuse_state.proc_status;\n\n\t*proc_status = HALMAC_CMD_PROCESS_SENDING;\n\n\tif (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\tif (cfg == HALMAC_EFUSE_R_AUTO) {\n\t\th2c_init = HALMAC_REG_R32(REG_H2C_PKT_READADDR);\n\t\tif (adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE ||\n\t\t    h2c_init == 0)\n\t\t\tstatus = dump_efuse_drv_88xx(adapter);\n\t\telse\n\t\t\tstatus = dump_efuse_fw_88xx(adapter);\n\t} else if (cfg == HALMAC_EFUSE_R_FW) {\n\t\tstatus = dump_efuse_fw_88xx(adapter);\n\t} else {\n\t\tstatus = dump_efuse_drv_88xx(adapter);\n\t}\n\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]dump efsue drv/fw\\n\");\n\t\treturn status;\n\t}\n\n\treturn status;\n}\n\nenum halmac_ret_status\ncnv_efuse_state_88xx(struct halmac_adapter *adapter,\n\t\t     enum halmac_cmd_construct_state dest_state)\n{\n\tstruct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;\n\n\tif (state->cmd_cnstr_state != HALMAC_CMD_CNSTR_IDLE &&\n\t    state->cmd_cnstr_state != HALMAC_CMD_CNSTR_BUSY &&\n\t    state->cmd_cnstr_state != HALMAC_CMD_CNSTR_H2C_SENT)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\tif (state->cmd_cnstr_state == dest_state)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\tif (dest_state == HALMAC_CMD_CNSTR_BUSY) {\n\t\tif (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_H2C_SENT)\n\t\t\treturn HALMAC_RET_ERROR_STATE;\n\t} else if (dest_state == HALMAC_CMD_CNSTR_H2C_SENT) {\n\t\tif (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_IDLE)\n\t\t\treturn HALMAC_RET_ERROR_STATE;\n\t}\n\n\tstate->cmd_cnstr_state = dest_state;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nread_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,\n\t\t   u8 *map)\n{\n\tu8 enable;\n\tu32 value32;\n\tu32 addr;\n\tu32 tmp32;\n\tu32 cnt;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\t/* Read efuse no need 2.5V LDO */\n\tenable = 0;\n\tstatus = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]dis ldo25\\n\");\n\t\treturn status;\n\t}\n\tvalue32 = HALMAC_REG_R32(REG_EFUSE_CTRL);\n\n\tfor (addr = offset; addr < offset + size; addr++) {\n\t\tvalue32 &= ~(BIT_MASK_EF_DATA | BITS_EF_ADDR);\n\t\tvalue32 |= ((addr & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR);\n\t\tHALMAC_REG_W32(REG_EFUSE_CTRL, value32 & (~BIT_EF_FLAG));\n\n\t\tcnt = 1000000;\n\t\tdo {\n\t\t\tPLTFM_DELAY_US(1);\n\t\t\ttmp32 = HALMAC_REG_R32(REG_EFUSE_CTRL);\n\t\t\tcnt--;\n\t\t\tif (cnt == 0) {\n\t\t\t\tPLTFM_MSG_ERR(\"[ERR]read\\n\");\n\t\t\t\treturn HALMAC_RET_EFUSE_R_FAIL;\n\t\t\t}\n\t\t} while ((tmp32 & BIT_EF_FLAG) == 0);\n\n\t\t*(map + addr - offset) = (u8)(tmp32 & BIT_MASK_EF_DATA);\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nwrite_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)\n{\n\tconst u8 unlock_code = 0x69;\n\tu8 value_read = 0;\n\tu8 enable;\n\tu32 value32;\n\tu32 tmp32;\n\tu32 cnt;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MUTEX_LOCK(&adapter->efuse_mutex);\n\tadapter->efuse_map_valid = 0;\n\tPLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);\n\n\tHALMAC_REG_W8(REG_PMC_DBG_CTRL2 + 3, unlock_code);\n\n\t/* Enable 2.5V LDO */\n\tenable = 1;\n\tstatus = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]en ldo25\\n\");\n\t\treturn status;\n\t}\n\n\tvalue32 = HALMAC_REG_R32(REG_EFUSE_CTRL);\n\tvalue32 &= ~(BIT_MASK_EF_DATA | BITS_EF_ADDR);\n\tvalue32 = value32 | ((offset & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) |\n\t\t\t(value & BIT_MASK_EF_DATA);\n\tHALMAC_REG_W32(REG_EFUSE_CTRL, value32 | BIT_EF_FLAG);\n\n\tcnt = 1000000;\n\tdo {\n\t\tPLTFM_DELAY_US(1);\n\t\ttmp32 = HALMAC_REG_R32(REG_EFUSE_CTRL);\n\t\tcnt--;\n\t\tif (cnt == 0) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]write!!\\n\");\n\t\t\treturn HALMAC_RET_EFUSE_W_FAIL;\n\t\t}\n\t} while (BIT_EF_FLAG == (tmp32 & BIT_EF_FLAG));\n\n\tHALMAC_REG_W8(REG_PMC_DBG_CTRL2 + 3, 0x00);\n\n\t/* Disable 2.5V LDO */\n\tenable = 0;\n\tstatus = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]dis ldo25\\n\");\n\t\treturn status;\n\t}\n\n\tif (adapter->efuse_auto_check_en == 1) {\n\t\tif (read_hw_efuse_88xx(adapter, offset, 1, &value_read) !=\n\t\t    HALMAC_RET_SUCCESS)\n\t\t\treturn HALMAC_RET_EFUSE_R_FAIL;\n\t\tif (value_read != value) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]efuse compare\\n\");\n\t\t\treturn HALMAC_RET_EFUSE_W_FAIL;\n\t\t}\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\neeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map)\n{\n\tu8 i;\n\tu8 value8;\n\tu8 blk_idx;\n\tu8 word_en;\n\tu8 valid;\n\tu8 hdr;\n\tu8 hdr2 = 0;\n\tu32 eeprom_idx;\n\tu32 efuse_idx = 0;\n\tu32 prtct_efuse_size = adapter->hw_cfg_info.prtct_efuse_size;\n\tstruct halmac_hw_cfg_info *hw_info = &adapter->hw_cfg_info;\n\n\tPLTFM_MEMSET(log_map, 0xFF, hw_info->eeprom_size);\n\n\tdo {\n\t\tvalue8 = *(phy_map + efuse_idx);\n\t\thdr = value8;\n\n\t\tif ((hdr & 0x1f) == 0x0f) {\n\t\t\tefuse_idx++;\n\t\t\tvalue8 = *(phy_map + efuse_idx);\n\t\t\thdr2 = value8;\n\t\t\tif (hdr2 == 0xff)\n\t\t\t\tbreak;\n\t\t\tblk_idx = ((hdr2 & 0xF0) >> 1) | ((hdr >> 5) & 0x07);\n\t\t\tword_en = hdr2 & 0x0F;\n\t\t} else {\n\t\t\tblk_idx = (hdr & 0xF0) >> 4;\n\t\t\tword_en = hdr & 0x0F;\n\t\t}\n\n\t\tif (hdr == 0xff)\n\t\t\tbreak;\n\n\t\tefuse_idx++;\n\n\t\tif (efuse_idx >= hw_info->efuse_size - prtct_efuse_size - 1)\n\t\t\treturn HALMAC_RET_EEPROM_PARSING_FAIL;\n\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\tvalid = (u8)((~(word_en >> i)) & BIT(0));\n\t\t\tif (valid == 1) {\n\t\t\t\teeprom_idx = (blk_idx << 3) + (i << 1);\n\n\t\t\t\tif ((eeprom_idx + 1) > hw_info->eeprom_size) {\n\t\t\t\t\tPLTFM_MSG_ERR(\"[ERR]efuse idx:0x%X\\n\",\n\t\t\t\t\t\t      efuse_idx - 1);\n\n\t\t\t\t\tPLTFM_MSG_ERR(\"[ERR]read hdr:0x%X\\n\",\n\t\t\t\t\t\t      hdr);\n\n\t\t\t\t\tPLTFM_MSG_ERR(\"[ERR]rad hdr2:0x%X\\n\",\n\t\t\t\t\t\t      hdr2);\n\n\t\t\t\t\treturn HALMAC_RET_EEPROM_PARSING_FAIL;\n\t\t\t\t}\n\n\t\t\t\tvalue8 = *(phy_map + efuse_idx);\n\t\t\t\t*(log_map + eeprom_idx) = value8;\n\n\t\t\t\teeprom_idx++;\n\t\t\t\tefuse_idx++;\n\n\t\t\t\tif (efuse_idx > hw_info->efuse_size -\n\t\t\t\t    prtct_efuse_size - 1)\n\t\t\t\t\treturn HALMAC_RET_EEPROM_PARSING_FAIL;\n\n\t\t\t\tvalue8 = *(phy_map + efuse_idx);\n\t\t\t\t*(log_map + eeprom_idx) = value8;\n\n\t\t\t\tefuse_idx++;\n\n\t\t\t\tif (efuse_idx > hw_info->efuse_size -\n\t\t\t\t    prtct_efuse_size)\n\t\t\t\t\treturn HALMAC_RET_EEPROM_PARSING_FAIL;\n\t\t\t}\n\t\t}\n\t} while (1);\n\n\tadapter->efuse_end = efuse_idx;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nread_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map)\n{\n\tu8 *local_map = NULL;\n\tu32 efuse_size;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tif (adapter->efuse_map_valid == 0) {\n\t\tefuse_size = adapter->hw_cfg_info.efuse_size;\n\n\t\tlocal_map = (u8 *)PLTFM_MALLOC(efuse_size);\n\t\tif (!local_map) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]local map\\n\");\n\t\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t\t}\n\n\t\tstatus = read_efuse_88xx(adapter, 0, efuse_size, local_map);\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]read efuse\\n\");\n\t\t\tPLTFM_FREE(local_map, efuse_size);\n\t\t\treturn status;\n\t\t}\n\n\t\tif (!adapter->efuse_map) {\n\t\t\tadapter->efuse_map = (u8 *)PLTFM_MALLOC(efuse_size);\n\t\t\tif (!adapter->efuse_map) {\n\t\t\t\tPLTFM_MSG_ERR(\"[ERR]malloc adapter map\\n\");\n\t\t\t\tPLTFM_FREE(local_map, efuse_size);\n\t\t\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t\t\t}\n\t\t}\n\n\t\tPLTFM_MUTEX_LOCK(&adapter->efuse_mutex);\n\t\tPLTFM_MEMCPY(adapter->efuse_map, local_map, efuse_size);\n\t\tadapter->efuse_map_valid = 1;\n\t\tPLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);\n\n\t\tPLTFM_FREE(local_map, efuse_size);\n\t}\n\n\tif (eeprom_parser_88xx(adapter, adapter->efuse_map, map) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_EEPROM_PARSING_FAIL;\n\n\treturn status;\n}\n\nstatic enum halmac_ret_status\nproc_pg_efuse_by_map_88xx(struct halmac_adapter *adapter,\n\t\t\t  struct halmac_pg_efuse_info *info,\n\t\t\t  enum halmac_efuse_read_cfg cfg)\n{\n\tu8 *updated_mask = NULL;\n\tu32 mask_size = adapter->hw_cfg_info.eeprom_size >> 4;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tupdated_mask = (u8 *)PLTFM_MALLOC(mask_size);\n\tif (!updated_mask) {\n\t\tPLTFM_MSG_ERR(\"[ERR]malloc updated mask\\n\");\n\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t}\n\tPLTFM_MEMSET(updated_mask, 0x00, mask_size);\n\n\tstatus = update_eeprom_mask_88xx(adapter, info, updated_mask);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]update eeprom mask\\n\");\n\t\tPLTFM_FREE(updated_mask, mask_size);\n\t\treturn status;\n\t}\n\n\tstatus = check_efuse_enough_88xx(adapter, info, updated_mask);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]chk efuse enough\\n\");\n\t\tPLTFM_FREE(updated_mask, mask_size);\n\t\treturn status;\n\t}\n\n\tstatus = program_efuse_88xx(adapter, info, updated_mask);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]pg efuse\\n\");\n\t\tPLTFM_FREE(updated_mask, mask_size);\n\t\treturn status;\n\t}\n\n\tPLTFM_FREE(updated_mask, mask_size);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\ndump_efuse_drv_88xx(struct halmac_adapter *adapter)\n{\n\tu8 *map = NULL;\n\tu32 efuse_size = adapter->hw_cfg_info.efuse_size;\n\n\tif (!adapter->efuse_map) {\n\t\tadapter->efuse_map = (u8 *)PLTFM_MALLOC(efuse_size);\n\t\tif (!adapter->efuse_map) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]malloc adapter map!!\\n\");\n\t\t\treset_ofld_feature_88xx(adapter,\n\t\t\t\t\t\tFEATURE_DUMP_PHY_EFUSE);\n\t\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t\t}\n\t}\n\n\tif (adapter->efuse_map_valid == 0) {\n\t\tmap = (u8 *)PLTFM_MALLOC(efuse_size);\n\t\tif (!map) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]malloc map\\n\");\n\t\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t\t}\n\n\t\tif (read_hw_efuse_88xx(adapter, 0, efuse_size, map) !=\n\t\t    HALMAC_RET_SUCCESS) {\n\t\t\tPLTFM_FREE(map, efuse_size);\n\t\t\treturn HALMAC_RET_EFUSE_R_FAIL;\n\t\t}\n\n\t\tPLTFM_MUTEX_LOCK(&adapter->efuse_mutex);\n\t\tPLTFM_MEMCPY(adapter->efuse_map, map, efuse_size);\n\t\tadapter->efuse_map_valid = 1;\n\t\tPLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);\n\n\t\tPLTFM_FREE(map, efuse_size);\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\ndump_efuse_fw_88xx(struct halmac_adapter *adapter)\n{\n\tu8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };\n\tu16 seq_num = 0;\n\tu32 efuse_size = adapter->hw_cfg_info.efuse_size;\n\tstruct halmac_h2c_header_info hdr_info;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\thdr_info.sub_cmd_id = SUB_CMD_ID_DUMP_PHYSICAL_EFUSE;\n\thdr_info.content_size = 0;\n\thdr_info.ack = 1;\n\tset_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);\n\n\tadapter->halmac_state.efuse_state.seq_num = seq_num;\n\n\tif (!adapter->efuse_map) {\n\t\tadapter->efuse_map = (u8 *)PLTFM_MALLOC(efuse_size);\n\t\tif (!adapter->efuse_map) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]malloc adapter map\\n\");\n\t\t\treset_ofld_feature_88xx(adapter,\n\t\t\t\t\t\tFEATURE_DUMP_PHY_EFUSE);\n\t\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t\t}\n\t}\n\n\tif (adapter->efuse_map_valid == 0) {\n\t\tstatus = send_h2c_pkt_88xx(adapter, h2c_buf);\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]send h2c pkt\\n\");\n\t\t\treset_ofld_feature_88xx(adapter,\n\t\t\t\t\t\tFEATURE_DUMP_PHY_EFUSE);\n\t\t\treturn status;\n\t\t}\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nproc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)\n{\n\tu8 byte1;\n\tu8 byte2;\n\tu8 blk;\n\tu8 blk_idx;\n\tu8 hdr;\n\tu8 hdr2;\n\tu8 *map = NULL;\n\tu32 eeprom_size = adapter->hw_cfg_info.eeprom_size;\n\tu32 prtct_efuse_size = adapter->hw_cfg_info.prtct_efuse_size;\n\tu32 end;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tmap = (u8 *)PLTFM_MALLOC(eeprom_size);\n\tif (!map) {\n\t\tPLTFM_MSG_ERR(\"[ERR]malloc map\\n\");\n\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t}\n\tPLTFM_MEMSET(map, 0xFF, eeprom_size);\n\n\tstatus = read_log_efuse_map_88xx(adapter, map);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]read logical efuse\\n\");\n\t\tPLTFM_FREE(map, eeprom_size);\n\t\treturn status;\n\t}\n\n\tif (*(map + offset) != value) {\n\t\tend = adapter->efuse_end;\n\t\tblk = (u8)(offset >> 3);\n\t\tblk_idx = (u8)((offset & (8 - 1)) >> 1);\n\n\t\tif (offset > 0x7f) {\n\t\t\thdr = (((blk & 0x07) << 5) & 0xE0) | 0x0F;\n\t\t\thdr2 = (u8)(((blk & 0x78) << 1) +\n\t\t\t\t\t\t((0x1 << blk_idx) ^ 0x0F));\n\t\t} else {\n\t\t\thdr = (u8)((blk << 4) + ((0x01 << blk_idx) ^ 0x0F));\n\t\t}\n\n\t\tif ((offset & 1) == 0) {\n\t\t\tbyte1 = value;\n\t\t\tbyte2 = *(map + offset + 1);\n\t\t} else {\n\t\t\tbyte1 = *(map + offset - 1);\n\t\t\tbyte2 = value;\n\t\t}\n\n\t\tif (offset > 0x7f) {\n\t\t\tif (adapter->hw_cfg_info.efuse_size <=\n\t\t\t    4 + prtct_efuse_size + end) {\n\t\t\t\tPLTFM_FREE(map, eeprom_size);\n\t\t\t\treturn HALMAC_RET_EFUSE_NOT_ENOUGH;\n\t\t\t}\n\n\t\t\tstatus = write_hw_efuse_88xx(adapter, end, hdr);\n\t\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\t\tPLTFM_FREE(map, eeprom_size);\n\t\t\t\treturn status;\n\t\t\t}\n\n\t\t\tstatus = write_hw_efuse_88xx(adapter, end + 1, hdr2);\n\t\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\t\tPLTFM_FREE(map, eeprom_size);\n\t\t\t\treturn status;\n\t\t\t}\n\n\t\t\tstatus = write_hw_efuse_88xx(adapter, end + 2, byte1);\n\t\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\t\tPLTFM_FREE(map, eeprom_size);\n\t\t\t\treturn status;\n\t\t\t}\n\n\t\t\tstatus = write_hw_efuse_88xx(adapter, end + 3, byte2);\n\t\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\t\tPLTFM_FREE(map, eeprom_size);\n\t\t\t\treturn status;\n\t\t\t}\n\t\t} else {\n\t\t\tif (adapter->hw_cfg_info.efuse_size <=\n\t\t\t    3 + prtct_efuse_size + end) {\n\t\t\t\tPLTFM_FREE(map, eeprom_size);\n\t\t\t\treturn HALMAC_RET_EFUSE_NOT_ENOUGH;\n\t\t\t}\n\n\t\t\tstatus = write_hw_efuse_88xx(adapter, end, hdr);\n\t\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\t\tPLTFM_FREE(map, eeprom_size);\n\t\t\t\treturn status;\n\t\t\t}\n\n\t\t\tstatus = write_hw_efuse_88xx(adapter, end + 1, byte1);\n\t\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\t\tPLTFM_FREE(map, eeprom_size);\n\t\t\t\treturn status;\n\t\t\t}\n\n\t\t\tstatus = write_hw_efuse_88xx(adapter, end + 2, byte2);\n\t\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\t\tPLTFM_FREE(map, eeprom_size);\n\t\t\t\treturn status;\n\t\t\t}\n\t\t}\n\t}\n\n\tPLTFM_FREE(map, eeprom_size);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nread_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, u8 *map)\n{\n\tif (!map) {\n\t\tPLTFM_MSG_ERR(\"[ERR]malloc map\\n\");\n\t\treturn HALMAC_RET_NULL_POINTER;\n\t}\n\n\tif (adapter->efuse_map_valid == 1) {\n\t\tPLTFM_MEMCPY(map, adapter->efuse_map + offset, size);\n\t} else {\n\t\tif (read_hw_efuse_88xx(adapter, offset, size, map) !=\n\t\t    HALMAC_RET_SUCCESS)\n\t\t\treturn HALMAC_RET_EFUSE_R_FAIL;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nupdate_eeprom_mask_88xx(struct halmac_adapter *adapter,\n\t\t\tstruct halmac_pg_efuse_info *info, u8 *updated_mask)\n{\n\tu8 *map = NULL;\n\tu8 clr_bit = 0;\n\tu32 eeprom_size = adapter->hw_cfg_info.eeprom_size;\n\tu8 *map_pg;\n\tu8 *efuse_mask;\n\tu16 i;\n\tu16 j;\n\tu16 map_offset;\n\tu16 mask_offset;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tmap = (u8 *)PLTFM_MALLOC(eeprom_size);\n\tif (!map) {\n\t\tPLTFM_MSG_ERR(\"[ERR]malloc map\\n\");\n\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t}\n\tPLTFM_MEMSET(map, 0xFF, eeprom_size);\n\n\tPLTFM_MEMSET(updated_mask, 0x00, info->efuse_mask_size);\n\n\tstatus = read_log_efuse_map_88xx(adapter, map);\n\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_FREE(map, eeprom_size);\n\t\treturn status;\n\t}\n\n\tmap_pg = info->efuse_map;\n\tefuse_mask = info->efuse_mask;\n\n\tfor (i = 0; i < info->efuse_mask_size; i++)\n\t\t*(updated_mask + i) = *(efuse_mask + i);\n\n\tfor (i = 0; i < info->efuse_map_size; i += 16) {\n\t\tfor (j = 0; j < 16; j += 2) {\n\t\t\tmap_offset = i + j;\n\t\t\tmask_offset = i >> 4;\n\t\t\tif (*(u16 *)(map_pg + map_offset) ==\n\t\t\t    *(u16 *)(map + map_offset)) {\n\t\t\t\tswitch (j) {\n\t\t\t\tcase 0:\n\t\t\t\t\tclr_bit = BIT(4);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 2:\n\t\t\t\t\tclr_bit = BIT(5);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 4:\n\t\t\t\t\tclr_bit = BIT(6);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 6:\n\t\t\t\t\tclr_bit = BIT(7);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 8:\n\t\t\t\t\tclr_bit = BIT(0);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 10:\n\t\t\t\t\tclr_bit = BIT(1);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 12:\n\t\t\t\t\tclr_bit = BIT(2);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 14:\n\t\t\t\t\tclr_bit = BIT(3);\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\t*(updated_mask + mask_offset) &= ~clr_bit;\n\t\t\t}\n\t\t}\n\t}\n\n\tPLTFM_FREE(map, eeprom_size);\n\n\treturn status;\n}\n\nstatic enum halmac_ret_status\ncheck_efuse_enough_88xx(struct halmac_adapter *adapter,\n\t\t\tstruct halmac_pg_efuse_info *info, u8 *updated_mask)\n{\n\tu8 pre_word_en;\n\tu16 i;\n\tu16 j;\n\tu32 eeprom_offset;\n\tu32 pg_num = 0;\n\n\tfor (i = 0; i < info->efuse_map_size; i = i + 8) {\n\t\teeprom_offset = i;\n\n\t\tif ((eeprom_offset & 7) > 0)\n\t\t\tpre_word_en = (*(updated_mask + (i >> 4)) & 0x0F);\n\t\telse\n\t\t\tpre_word_en = (*(updated_mask + (i >> 4)) >> 4);\n\n\t\tif (pre_word_en > 0) {\n\t\t\tif (eeprom_offset > 0x7f) {\n\t\t\t\tpg_num += 2;\n\t\t\t\tfor (j = 0; j < 4; j++) {\n\t\t\t\t\tif (((pre_word_en >> j) & 0x1) > 0)\n\t\t\t\t\t\tpg_num += 2;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tpg_num++;\n\t\t\t\tfor (j = 0; j < 4; j++) {\n\t\t\t\t\tif (((pre_word_en >> j) & 0x1) > 0)\n\t\t\t\t\t\tpg_num += 2;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tif (adapter->hw_cfg_info.efuse_size <=\n\t    (pg_num + adapter->hw_cfg_info.prtct_efuse_size +\n\t    adapter->efuse_end))\n\t\treturn HALMAC_RET_EFUSE_NOT_ENOUGH;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\npg_extend_efuse_88xx(struct halmac_adapter *adapter,\n\t\t     struct halmac_pg_efuse_info *info, u8 word_en,\n\t\t     u8 pre_word_en, u32 eeprom_offset)\n{\n\tu8 blk;\n\tu8 hdr;\n\tu8 hdr2;\n\tu16 i;\n\tu32 efuse_end;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tefuse_end = adapter->efuse_end;\n\n\tblk = (u8)(eeprom_offset >> 3);\n\thdr = (((blk & 0x07) << 5) & 0xE0) | 0x0F;\n\thdr2 = (u8)(((blk & 0x78) << 1) + word_en);\n\n\tstatus = write_hw_efuse_88xx(adapter, efuse_end, hdr);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]write efuse\\n\");\n\t\treturn status;\n\t}\n\n\tstatus = write_hw_efuse_88xx(adapter, efuse_end + 1, hdr2);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]write efuse(+1)\\n\");\n\t\treturn status;\n\t}\n\n\tefuse_end = efuse_end + 2;\n\tfor (i = 0; i < 4; i++) {\n\t\tif (((pre_word_en >> i) & 0x1) > 0) {\n\t\t\tstatus = write_hw_efuse_88xx(adapter, efuse_end,\n\t\t\t\t\t\t     *(info->efuse_map +\n\t\t\t\t\t\t     eeprom_offset +\n\t\t\t\t\t\t     (i << 1)));\n\t\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\t\tPLTFM_MSG_ERR(\"[ERR]write efuse(<<1)\\n\");\n\t\t\t\treturn status;\n\t\t\t}\n\n\t\t\tstatus = write_hw_efuse_88xx(adapter, efuse_end + 1,\n\t\t\t\t\t\t     *(info->efuse_map +\n\t\t\t\t\t\t     eeprom_offset + (i << 1)\n\t\t\t\t\t\t     + 1));\n\t\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\t\tPLTFM_MSG_ERR(\"[ERR]write efuse(<<1)+1\\n\");\n\t\t\t\treturn status;\n\t\t\t}\n\t\t\tefuse_end = efuse_end + 2;\n\t\t}\n\t}\n\tadapter->efuse_end = efuse_end;\n\treturn status;\n}\n\nstatic enum halmac_ret_status\nproc_pg_efuse_88xx(struct halmac_adapter *adapter,\n\t\t   struct halmac_pg_efuse_info *info, u8 word_en,\n\t\t   u8 pre_word_en, u32 eeprom_offset)\n{\n\tu8 blk;\n\tu8 hdr;\n\tu16 i;\n\tu32 efuse_end;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tefuse_end = adapter->efuse_end;\n\n\tblk = (u8)(eeprom_offset >> 3);\n\thdr = (u8)((blk << 4) + word_en);\n\n\tstatus = write_hw_efuse_88xx(adapter, efuse_end, hdr);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]write efuse\\n\");\n\t\treturn status;\n\t}\n\tefuse_end = efuse_end + 1;\n\tfor (i = 0; i < 4; i++) {\n\t\tif (((pre_word_en >> i) & 0x1) > 0) {\n\t\t\tstatus = write_hw_efuse_88xx(adapter, efuse_end,\n\t\t\t\t\t\t     *(info->efuse_map +\n\t\t\t\t\t\t     eeprom_offset +\n\t\t\t\t\t\t     (i << 1)));\n\t\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\t\tPLTFM_MSG_ERR(\"[ERR]write efuse(<<1)\\n\");\n\t\t\t\treturn status;\n\t\t\t}\n\t\t\tstatus = write_hw_efuse_88xx(adapter, efuse_end + 1,\n\t\t\t\t\t\t     *(info->efuse_map +\n\t\t\t\t\t\t     eeprom_offset + (i << 1)\n\t\t\t\t\t\t     + 1));\n\t\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\t\tPLTFM_MSG_ERR(\"[ERR]write efuse(<<1)+1\\n\");\n\t\t\t\treturn status;\n\t\t\t}\n\t\t\tefuse_end = efuse_end + 2;\n\t\t}\n\t}\n\tadapter->efuse_end = efuse_end;\n\treturn status;\n}\n\nstatic enum halmac_ret_status\nprogram_efuse_88xx(struct halmac_adapter *adapter,\n\t\t   struct halmac_pg_efuse_info *info, u8 *updated_mask)\n{\n\tu8 pre_word_en;\n\tu8 word_en;\n\tu16 i;\n\tu32 eeprom_offset;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tfor (i = 0; i < info->efuse_map_size; i = i + 8) {\n\t\teeprom_offset = i;\n\n\t\tif (((eeprom_offset >> 3) & 1) > 0) {\n\t\t\tpre_word_en = (*(updated_mask + (i >> 4)) & 0x0F);\n\t\t\tword_en = pre_word_en ^ 0x0F;\n\t\t} else {\n\t\t\tpre_word_en = (*(updated_mask + (i >> 4)) >> 4);\n\t\t\tword_en = pre_word_en ^ 0x0F;\n\t\t}\n\n\t\tif (pre_word_en > 0) {\n\t\t\tif (eeprom_offset > 0x7f) {\n\t\t\t\tstatus = pg_extend_efuse_88xx(adapter, info,\n\t\t\t\t\t\t\t      word_en,\n\t\t\t\t\t\t\t      pre_word_en,\n\t\t\t\t\t\t\t      eeprom_offset);\n\t\t\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\t\t\tPLTFM_MSG_ERR(\"[ERR]extend efuse\\n\");\n\t\t\t\t\treturn status;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tstatus = proc_pg_efuse_88xx(adapter, info,\n\t\t\t\t\t\t\t    word_en,\n\t\t\t\t\t\t\t    pre_word_en,\n\t\t\t\t\t\t\t    eeprom_offset);\n\t\t\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\t\t\tPLTFM_MSG_ERR(\"[ERR]extend efuse\");\n\t\t\t\t\treturn status;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\treturn status;\n}\n\nstatic void\nmask_eeprom_88xx(struct halmac_adapter *adapter,\n\t\t struct halmac_pg_efuse_info *info)\n{\n\tu8 pre_word_en;\n\tu8 *updated_mask;\n\tu8 *efuse_map;\n\tu16 i;\n\tu16 j;\n\tu32 offset;\n\n\tupdated_mask = info->efuse_mask;\n\tefuse_map = info->efuse_map;\n\n\tfor (i = 0; i < info->efuse_map_size; i = i + 8) {\n\t\toffset = i;\n\n\t\tif (((offset >> 3) & 1) > 0)\n\t\t\tpre_word_en = (*(updated_mask + (i >> 4)) & 0x0F);\n\t\telse\n\t\t\tpre_word_en = (*(updated_mask + (i >> 4)) >> 4);\n\n\t\tfor (j = 0; j < 4; j++) {\n\t\t\tif (((pre_word_en >> j) & 0x1) == 0) {\n\t\t\t\t*(efuse_map + offset + (j << 1)) = 0xFF;\n\t\t\t\t*(efuse_map + offset + (j << 1) + 1) = 0xFF;\n\t\t\t}\n\t\t}\n\t}\n}\n\nenum halmac_ret_status\nget_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)\n{\n\tu8 seg_id;\n\tu8 seg_size;\n\tu8 seq_num;\n\tu8 fw_rc;\n\tu8 *map = NULL;\n\tu32 eeprom_size = adapter->hw_cfg_info.eeprom_size;\n\tstruct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;\n\tenum halmac_cmd_process_status proc_status;\n\n\tseq_num = (u8)EFUSE_DATA_GET_H2C_SEQ(buf);\n\tPLTFM_MSG_TRACE(\"[TRACE]Seq num : h2c->%d c2h->%d\\n\",\n\t\t\tstate->seq_num, seq_num);\n\tif (seq_num != state->seq_num) {\n\t\tPLTFM_MSG_ERR(\"[ERR]Seq num mismatch : h2c->%d c2h->%d\\n\",\n\t\t\t      state->seq_num, seq_num);\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tif (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_ERR(\"[ERR]not cmd sending\\n\");\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tseg_id = (u8)EFUSE_DATA_GET_SEGMENT_ID(buf);\n\tseg_size = (u8)EFUSE_DATA_GET_SEGMENT_SIZE(buf);\n\tif (seg_id == 0)\n\t\tadapter->efuse_seg_size = seg_size;\n\n\tmap = (u8 *)PLTFM_MALLOC(eeprom_size);\n\tif (!map) {\n\t\tPLTFM_MSG_ERR(\"[ERR]malloc map\\n\");\n\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t}\n\tPLTFM_MEMSET(map, 0xFF, eeprom_size);\n\n\tPLTFM_MUTEX_LOCK(&adapter->efuse_mutex);\n\tPLTFM_MEMCPY(adapter->efuse_map + seg_id * adapter->efuse_seg_size,\n\t\t     buf + C2H_DATA_OFFSET_88XX, seg_size);\n\tPLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);\n\n\tif (EFUSE_DATA_GET_END_SEGMENT(buf) == 0) {\n\t\tPLTFM_FREE(map, eeprom_size);\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tfw_rc = state->fw_rc;\n\n\tif ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {\n\t\tproc_status = HALMAC_CMD_PROCESS_DONE;\n\t\tstate->proc_status = proc_status;\n\n\t\tPLTFM_MUTEX_LOCK(&adapter->efuse_mutex);\n\t\tadapter->efuse_map_valid = 1;\n\t\tPLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);\n\n\t\tif (adapter->evnt.phy_efuse_map == 1) {\n\t\t\tPLTFM_EVENT_SIG(FEATURE_DUMP_PHY_EFUSE,\n\t\t\t\t\tproc_status, adapter->efuse_map,\n\t\t\t\t\tadapter->hw_cfg_info.efuse_size);\n\t\t\tadapter->evnt.phy_efuse_map = 0;\n\t\t}\n\n\t\tif (adapter->evnt.log_efuse_map == 1) {\n\t\t\tif (eeprom_parser_88xx(adapter, adapter->efuse_map,\n\t\t\t\t\t       map) != HALMAC_RET_SUCCESS) {\n\t\t\t\tPLTFM_FREE(map, eeprom_size);\n\t\t\t\treturn HALMAC_RET_EEPROM_PARSING_FAIL;\n\t\t\t}\n\t\t\tPLTFM_EVENT_SIG(FEATURE_DUMP_LOG_EFUSE, proc_status,\n\t\t\t\t\tmap, eeprom_size);\n\t\t\tadapter->evnt.log_efuse_map = 0;\n\t\t}\n\t} else {\n\t\tproc_status = HALMAC_CMD_PROCESS_ERROR;\n\t\tstate->proc_status = proc_status;\n\n\t\tif (adapter->evnt.phy_efuse_map == 1) {\n\t\t\tPLTFM_EVENT_SIG(FEATURE_DUMP_PHY_EFUSE, proc_status,\n\t\t\t\t\t&state->fw_rc, 1);\n\t\t\tadapter->evnt.phy_efuse_map = 0;\n\t\t}\n\n\t\tif (adapter->evnt.log_efuse_map == 1) {\n\t\t\tPLTFM_EVENT_SIG(FEATURE_DUMP_LOG_EFUSE, proc_status,\n\t\t\t\t\t&state->fw_rc, 1);\n\t\t\tadapter->evnt.log_efuse_map = 0;\n\t\t}\n\t}\n\n\tPLTFM_FREE(map, eeprom_size);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nget_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter,\n\t\t\t       enum halmac_cmd_process_status *proc_status,\n\t\t\t       u8 *data, u32 *size)\n{\n\tu8 *map = NULL;\n\tu32 efuse_size = adapter->hw_cfg_info.efuse_size;\n\tu32 prtct_efuse_size = adapter->hw_cfg_info.prtct_efuse_size;\n\tstruct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;\n\n\t*proc_status = state->proc_status;\n\n\tif (!data)\n\t\treturn HALMAC_RET_NULL_POINTER;\n\n\tif (!size)\n\t\treturn HALMAC_RET_NULL_POINTER;\n\n\tif (*proc_status == HALMAC_CMD_PROCESS_DONE) {\n\t\tif (*size < efuse_size) {\n\t\t\t*size = efuse_size;\n\t\t\treturn HALMAC_RET_BUFFER_TOO_SMALL;\n\t\t}\n\n\t\t*size = efuse_size;\n\n\t\tmap = (u8 *)PLTFM_MALLOC(efuse_size);\n\t\tif (!map) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]malloc map\\n\");\n\t\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t\t}\n\t\tPLTFM_MEMSET(map, 0xFF, efuse_size);\n\t\tPLTFM_MUTEX_LOCK(&adapter->efuse_mutex);\n\t\tPLTFM_MEMCPY(map, adapter->efuse_map,\n\t\t\t     efuse_size - prtct_efuse_size);\n\t\tPLTFM_MEMCPY(map + efuse_size - prtct_efuse_size +\n\t\t\t     RSVD_CS_EFUSE_SIZE,\n\t\t\t     adapter->efuse_map + efuse_size -\n\t\t\t     prtct_efuse_size + RSVD_CS_EFUSE_SIZE,\n\t\t\t     prtct_efuse_size - RSVD_EFUSE_SIZE -\n\t\t\t     RSVD_CS_EFUSE_SIZE);\n\t\tPLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);\n\n\t\tPLTFM_MEMCPY(data, map, *size);\n\n\t\tPLTFM_FREE(map, efuse_size);\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nget_dump_log_efuse_status_88xx(struct halmac_adapter *adapter,\n\t\t\t       enum halmac_cmd_process_status *proc_status,\n\t\t\t       u8 *data, u32 *size)\n{\n\tu8 *map = NULL;\n\tu32 eeprom_size = adapter->hw_cfg_info.eeprom_size;\n\tstruct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;\n\n\t*proc_status = state->proc_status;\n\n\tif (!data)\n\t\treturn HALMAC_RET_NULL_POINTER;\n\n\tif (!size)\n\t\treturn HALMAC_RET_NULL_POINTER;\n\n\tif (*proc_status == HALMAC_CMD_PROCESS_DONE) {\n\t\tif (*size < eeprom_size) {\n\t\t\t*size = eeprom_size;\n\t\t\treturn HALMAC_RET_BUFFER_TOO_SMALL;\n\t\t}\n\n\t\t*size = eeprom_size;\n\n\t\tmap = (u8 *)PLTFM_MALLOC(eeprom_size);\n\t\tif (!map) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]malloc map\\n\");\n\t\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t\t}\n\t\tPLTFM_MEMSET(map, 0xFF, eeprom_size);\n\n\t\tif (eeprom_parser_88xx(adapter, adapter->efuse_map, map) !=\n\t\t    HALMAC_RET_SUCCESS) {\n\t\t\tPLTFM_FREE(map, eeprom_size);\n\t\t\treturn HALMAC_RET_EEPROM_PARSING_FAIL;\n\t\t}\n\n\t\tPLTFM_MEMCPY(data, map, *size);\n\n\t\tPLTFM_FREE(map, eeprom_size);\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nget_h2c_ack_phy_efuse_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)\n{\n\tu8 seq_num = 0;\n\tu8 fw_rc;\n\tstruct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;\n\n\tseq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);\n\tPLTFM_MSG_TRACE(\"[TRACE]Seq num : h2c->%d c2h->%d\\n\",\n\t\t\tstate->seq_num, seq_num);\n\tif (seq_num != state->seq_num) {\n\t\tPLTFM_MSG_ERR(\"[ERR]Seq num mismatch : h2c->%d c2h->%d\\n\",\n\t\t\t      state->seq_num, seq_num);\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tif (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_ERR(\"[ERR]not cmd sending\\n\");\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tfw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);\n\tstate->fw_rc = fw_rc;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nu32\nget_rsvd_efuse_size_88xx(struct halmac_adapter *adapter)\n{\n\treturn adapter->hw_cfg_info.prtct_efuse_size;\n}\n\n#endif /* HALMAC_88XX_SUPPORT */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_efuse_88xx.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_EFUSE_88XX_H_\n#define _HALMAC_EFUSE_88XX_H_\n\n#include \"../halmac_api.h\"\n\n#if HALMAC_88XX_SUPPORT\n\nenum halmac_ret_status\ndump_efuse_map_88xx(struct halmac_adapter *adapter,\n\t\t    enum halmac_efuse_read_cfg cfg);\n\nenum halmac_ret_status\neeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map);\n\nenum halmac_ret_status\ndump_efuse_map_bt_88xx(struct halmac_adapter *adapter,\n\t\t       enum halmac_efuse_bank bank, u32 size, u8 *map);\n\nenum halmac_ret_status\nwrite_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 value,\n\t\t    enum halmac_efuse_bank bank);\n\nenum halmac_ret_status\nread_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value,\n\t\t   enum halmac_efuse_bank bank);\n\nenum halmac_ret_status\ncfg_efuse_auto_check_88xx(struct halmac_adapter *adapter, u8 enable);\n\nenum halmac_ret_status\nget_efuse_available_size_88xx(struct halmac_adapter *adapter, u32 *size);\n\nenum halmac_ret_status\nget_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size);\n\nenum halmac_ret_status\nget_log_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size);\n\nenum halmac_ret_status\ndump_log_efuse_map_88xx(struct halmac_adapter *adapter,\n\t\t\tenum halmac_efuse_read_cfg cfg);\n\nenum halmac_ret_status\nread_logical_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value);\n\nenum halmac_ret_status\nwrite_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);\n\nenum halmac_ret_status\npg_efuse_by_map_88xx(struct halmac_adapter *adapter,\n\t\t     struct halmac_pg_efuse_info *info,\n\t\t     enum halmac_efuse_read_cfg cfg);\n\nenum halmac_ret_status\nmask_log_efuse_88xx(struct halmac_adapter *adapter,\n\t\t    struct halmac_pg_efuse_info *info);\n\nenum halmac_ret_status\nread_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, u8 *map);\n\nenum halmac_ret_status\nwrite_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);\n\nenum halmac_ret_status\nswitch_efuse_bank_88xx(struct halmac_adapter *adapter,\n\t\t       enum halmac_efuse_bank bank);\n\nenum halmac_ret_status\nget_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\nenum halmac_ret_status\ncnv_efuse_state_88xx(struct halmac_adapter *adapter,\n\t\t     enum halmac_cmd_construct_state dest_state);\n\nenum halmac_ret_status\nget_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter,\n\t\t\t       enum halmac_cmd_process_status *proc_status,\n\t\t\t       u8 *data, u32 *size);\n\nenum halmac_ret_status\nget_dump_log_efuse_status_88xx(struct halmac_adapter *adapter,\n\t\t\t       enum halmac_cmd_process_status *proc_status,\n\t\t\t       u8 *data, u32 *size);\n\nenum halmac_ret_status\nget_h2c_ack_phy_efuse_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\nu32\nget_rsvd_efuse_size_88xx(struct halmac_adapter *adapter);\n\n#endif /* HALMAC_88XX_SUPPORT */\n\n#endif/* _HALMAC_EFUSE_88XX_H_ */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_flash_88xx.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"halmac_flash_88xx.h\"\n#include \"halmac_88xx_cfg.h\"\n#include \"halmac_common_88xx.h\"\n\n#if HALMAC_88XX_SUPPORT\n\n/**\n * download_flash_88xx() -download firmware to flash\n * @adapter : the adapter of halmac\n * @fw_bin : pointer to fw\n * @size : fw size\n * @rom_addr : flash start address where fw should be download\n * Author : Pablo Chiu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ndownload_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,\n\t\t    u32 rom_addr)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tenum halmac_ret_status rc;\n\tstruct halmac_h2c_header_info hdr_info;\n\tu8 value8;\n\tu8 restore[3];\n\tu8 h2c_buf[H2C_PKT_SIZE_88XX] = {0};\n\tu16 seq_num = 0;\n\tu16 h2c_info_offset;\n\tu32 pkt_size;\n\tu32 mem_offset;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tvalue8 = HALMAC_REG_R8(REG_CR + 1);\n\trestore[0] = value8;\n\tvalue8 = (u8)(value8 | BIT(0));\n\tHALMAC_REG_W8(REG_CR + 1, value8);\n\n\tvalue8 = HALMAC_REG_R8(REG_BCN_CTRL);\n\trestore[1] = value8;\n\tvalue8 = (u8)((value8 & ~(BIT(3))) | BIT(4));\n\tHALMAC_REG_W8(REG_BCN_CTRL, value8);\n\n\tvalue8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL + 2);\n\trestore[2] = value8;\n\tvalue8 = (u8)(value8 & ~(BIT(6)));\n\tHALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8);\n\n\t/* Download FW to Flash flow */\n\th2c_info_offset = adapter->txff_alloc.rsvd_h2c_info_addr -\n\t\t\t\t\tadapter->txff_alloc.rsvd_boundary;\n\tmem_offset = 0;\n\n\twhile (size != 0) {\n\t\tif (size >= (DL_FLASH_RSVDPG_SIZE - 48))\n\t\t\tpkt_size = DL_FLASH_RSVDPG_SIZE - 48;\n\t\telse\n\t\t\tpkt_size = size;\n\n\t\trc = dl_rsvd_page_88xx(adapter,\n\t\t\t\t       adapter->txff_alloc.rsvd_h2c_info_addr,\n\t\t\t\t       fw_bin + mem_offset, pkt_size);\n\t\tif (rc != HALMAC_RET_SUCCESS) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]dl rsvd pg!!\\n\");\n\t\t\treturn rc;\n\t\t}\n\n\t\tDOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, 0x02);\n\t\tDOWNLOAD_FLASH_SET_LOCATION(h2c_buf, h2c_info_offset);\n\t\tDOWNLOAD_FLASH_SET_SIZE(h2c_buf, pkt_size);\n\t\tDOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, rom_addr);\n\n\t\thdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;\n\t\thdr_info.content_size = 20;\n\t\thdr_info.ack = 1;\n\t\tset_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);\n\n\t\trc = send_h2c_pkt_88xx(adapter, h2c_buf);\n\n\t\tif (rc != HALMAC_RET_SUCCESS) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]send h2c!!\\n\");\n\t\t\treturn rc;\n\t\t}\n\n\t\tvalue8 = HALMAC_REG_R8(REG_MCUTST_I);\n\t\tvalue8 |= BIT(0);\n\t\tHALMAC_REG_W8(REG_MCUTST_I, value8);\n\n\t\trom_addr += pkt_size;\n\t\tmem_offset += pkt_size;\n\t\tsize -= pkt_size;\n\n\t\twhile (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0)\n\t\t\tPLTFM_DELAY_US(1000);\n\n\t\tif (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]dl flash!!\\n\");\n\t\t\treturn  HALMAC_RET_DLFW_FAIL;\n\t\t}\n\t}\n\n\tHALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[2]);\n\tHALMAC_REG_W8(REG_BCN_CTRL, restore[1]);\n\tHALMAC_REG_W8(REG_CR + 1, restore[0]);\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * read_flash_88xx() -read data from flash\n * @adapter : the adapter of halmac\n * @addr : flash start address where fw should be read\n * Author : Pablo Chiu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nread_flash_88xx(struct halmac_adapter *adapter, u32 addr, u32 length)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tenum halmac_ret_status status;\n\tstruct halmac_h2c_header_info hdr_info;\n\tu8 value8;\n\tu8 restore[3];\n\tu8 h2c_buf[H2C_PKT_SIZE_88XX] = {0};\n\tu16 seq_num = 0;\n\tu16 h2c_info_addr = adapter->txff_alloc.rsvd_h2c_info_addr;\n\tu16 rsvd_pg_addr = adapter->txff_alloc.rsvd_boundary;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tvalue8 = HALMAC_REG_R8(REG_CR + 1);\n\trestore[0] = value8;\n\tvalue8 = (u8)(value8 | BIT(0));\n\tHALMAC_REG_W8(REG_CR + 1, value8);\n\n\tvalue8 = HALMAC_REG_R8(REG_BCN_CTRL);\n\trestore[1] = value8;\n\tvalue8 = (u8)((value8 & ~(BIT(3))) | BIT(4));\n\tHALMAC_REG_W8(REG_BCN_CTRL, value8);\n\n\tvalue8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL + 2);\n\trestore[2] = value8;\n\tvalue8 = (u8)(value8 & ~(BIT(6)));\n\tHALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8);\n\n\tHALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, h2c_info_addr);\n\tvalue8 = HALMAC_REG_R8(REG_MCUTST_I);\n\tvalue8 |= BIT(0);\n\tHALMAC_REG_W8(REG_MCUTST_I, value8);\n\n\t/* Construct H2C Content */\n\tDOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, 0x03);\n\tDOWNLOAD_FLASH_SET_LOCATION(h2c_buf, h2c_info_addr - rsvd_pg_addr);\n\tDOWNLOAD_FLASH_SET_SIZE(h2c_buf, length);\n\tDOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, addr);\n\n\t/* Fill in H2C Header */\n\thdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;\n\thdr_info.content_size = 16;\n\thdr_info.ack = 1;\n\tset_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);\n\n\t/* Send H2C Cmd Packet */\n\tstatus = send_h2c_pkt_88xx(adapter, h2c_buf);\n\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]send h2c!!\\n\");\n\t\treturn status;\n\t}\n\n\twhile (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0)\n\t\tPLTFM_DELAY_US(1000);\n\n\tHALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, rsvd_pg_addr);\n\tHALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[2]);\n\tHALMAC_REG_W8(REG_BCN_CTRL, restore[1]);\n\tHALMAC_REG_W8(REG_CR + 1, restore[0]);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * erase_flash_88xx() -erase flash data\n * @adapter : the adapter of halmac\n * @erase_cmd : erase command\n * @addr : flash start address where fw should be erased\n * Author : Pablo Chiu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nerase_flash_88xx(struct halmac_adapter *adapter, u8 erase_cmd, u32 addr)\n{\n\tenum halmac_ret_status status;\n\tstruct halmac_h2c_header_info hdr_info;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tu8 value8;\n\tu8 h2c_buf[H2C_PKT_SIZE_88XX] = {0};\n\tu16 seq_num = 0;\n\tu32 cnt;\n\n\t/* Construct H2C Content */\n\tDOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, erase_cmd);\n\tDOWNLOAD_FLASH_SET_LOCATION(h2c_buf, 0);\n\tDOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, addr);\n\tDOWNLOAD_FLASH_SET_SIZE(h2c_buf, 0);\n\n\tvalue8 = HALMAC_REG_R8(REG_MCUTST_I);\n\tvalue8 |= BIT(0);\n\tHALMAC_REG_W8(REG_MCUTST_I, value8);\n\n\t/* Fill in H2C Header */\n\thdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;\n\thdr_info.content_size = 16;\n\thdr_info.ack = 1;\n\tset_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);\n\n\t/* Send H2C Cmd Packet */\n\tstatus = send_h2c_pkt_88xx(adapter, h2c_buf);\n\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tPLTFM_MSG_ERR(\"[ERR]send h2c!!\\n\");\n\n\tcnt = 5000;\n\twhile (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0 && cnt != 0) {\n\t\tPLTFM_DELAY_US(1000);\n\t\tcnt--;\n\t}\n\n\tif (cnt == 0)\n\t\treturn HALMAC_RET_FAIL;\n\telse\n\t\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * check_flash_88xx() -check flash data\n * @adapter : the adapter of halmac\n * @fw_bin : pointer to fw\n * @size : fw size\n * @addr : flash start address where fw should be checked\n * Author : Pablo Chiu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncheck_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,\n\t\t u32 addr)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tu8 value8;\n\tu16 i;\n\tu16 residue;\n\tu16 pg_addr;\n\tu32 pkt_size;\n\tu32 start_page;\n\tu32 cnt;\n\n\tpg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;\n\n\twhile (size != 0) {\n\t\tstart_page = ((pg_addr << 7) >> 12) + 0x780;\n\t\tresidue = (pg_addr << 7) & (4096 - 1);\n\n\t\tif (size >= DL_FLASH_RSVDPG_SIZE)\n\t\t\tpkt_size = DL_FLASH_RSVDPG_SIZE;\n\t\telse\n\t\t\tpkt_size = size;\n\n\t\tread_flash_88xx(adapter, addr, 4096);\n\n\t\tcnt = 0;\n\t\twhile (cnt < pkt_size) {\n\t\t\tHALMAC_REG_W16(REG_PKTBUF_DBG_CTRL, (u16)(start_page));\n\t\t\tfor (i = 0x8000 + residue; i <= 0x8FFF; i++) {\n\t\t\t\tvalue8 = HALMAC_REG_R8(i);\n\t\t\t\tif (*fw_bin != value8) {\n\t\t\t\t\tPLTFM_MSG_ERR(\"[ERR]check flash!!\\n\");\n\t\t\t\t\treturn HALMAC_RET_FAIL;\n\t\t\t\t}\n\n\t\t\t\tfw_bin++;\n\t\t\t\tcnt++;\n\t\t\t\tif (cnt == pkt_size)\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t\tresidue = 0;\n\t\t\tstart_page++;\n\t\t}\n\t\taddr += pkt_size;\n\t\tsize -= pkt_size;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n#endif /* HALMAC_88XX_SUPPORT */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_flash_88xx.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_FLASH_88XX_H_\n#define _HALMAC_FLASH_88XX_H_\n\n#include \"../halmac_api.h\"\n\n#if HALMAC_88XX_SUPPORT\n\nenum halmac_ret_status\ndownload_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,\n\t\t    u32 rom_addr);\n\nenum halmac_ret_status\nread_flash_88xx(struct halmac_adapter *adapter, u32 addr, u32 length);\n\nenum halmac_ret_status\nerase_flash_88xx(struct halmac_adapter *adapter, u8 erase_cmd, u32 addr);\n\nenum halmac_ret_status\ncheck_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,\n\t\t u32 addr);\n\n#endif /* HALMAC_88XX_SUPPORT */\n\n#endif/* _HALMAC_FLASH_88XX_H_ */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_fw_88xx.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"halmac_fw_88xx.h\"\n#include \"halmac_88xx_cfg.h\"\n#include \"halmac_common_88xx.h\"\n#include \"halmac_init_88xx.h\"\n\n#if HALMAC_88XX_SUPPORT\n\n#define DLFW_RESTORE_REG_NUM\t\t6\n#define ILLEGAL_KEY_GROUP\t\t0xFAAAAA00\n\n/* Max dlfw size can not over 31K, due to SDIO HW limitation */\n#define DLFW_PKT_SIZE_LIMIT\t\t31744\n\n#define ID_INFORM_DLEMEM_RDY\t\t0x80\n#define ID_INFORM_ENETR_CPU_SLEEP\t0x20\n#define ID_CHECK_DLEMEM_RDY\t\t0x80\n#define ID_CHECK_ENETR_CPU_SLEEP\t0x05\n\n#define FW_STATUS_CHK_FATAL\t(BIT(1) | BIT(20))\n#define FW_STATUS_CHK_ERR\t(BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | \\\n\t\t\t\t BIT(9) | BIT(12) | BIT(14) | BIT(15) | \\\n\t\t\t\t BIT(16) | BIT(17) | BIT(18) | BIT(19) | \\\n\t\t\t\t BIT(21) | BIT(22) | BIT(25))\n#define FW_STATUS_CHK_WARN\t~(FW_STATUS_CHK_FATAL | FW_STATUS_CHK_ERR)\n\nstruct halmac_backup_info {\n\tu32 mac_register;\n\tu32 value;\n\tu8 length;\n};\n\nstatic enum halmac_ret_status\nupdate_fw_info_88xx(struct halmac_adapter *adapter, u8 *fw_bin);\n\nstatic void\nrestore_mac_reg_88xx(struct halmac_adapter *adapter,\n\t\t     struct halmac_backup_info *info, u32 num);\n\nstatic enum halmac_ret_status\ndlfw_to_mem_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 src, u32 dest,\n\t\t u32 size);\n\nstatic enum halmac_ret_status\ndlfw_end_flow_88xx(struct halmac_adapter *adapter);\n\nstatic enum halmac_ret_status\nfree_dl_fw_end_flow_88xx(struct halmac_adapter *adapter);\n\nstatic enum halmac_ret_status\nsend_fwpkt_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *fw_bin,\n\t\tu32 size);\n\nstatic enum halmac_ret_status\niddma_dlfw_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 len,\n\t\tu8 first);\n\nstatic enum halmac_ret_status\niddma_en_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 ctrl);\n\nstatic enum halmac_ret_status\ncheck_fw_chksum_88xx(struct halmac_adapter *adapter, u32 mem_addr);\n\nstatic void\nfw_fatal_status_debug_88xx(struct halmac_adapter *adapter);\n\nstatic enum halmac_ret_status\nstart_dlfw_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,\n\t\tu32 dl_addr, u8 emem_only);\n\nstatic enum halmac_ret_status\nchk_fw_size_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size);\n\nstatic void\nchk_h2c_ver_88xx(struct halmac_adapter *adapter, u8 *fw_bin);\n\nstatic void\nwlan_cpu_en_88xx(struct halmac_adapter *adapter, u8 enable);\n\nstatic void\npltfm_reset_88xx(struct halmac_adapter *adapter);\n\nstatic enum halmac_ret_status\nproc_send_general_info_88xx(struct halmac_adapter *adapter,\n\t\t\t    struct halmac_general_info *info);\n\nstatic enum halmac_ret_status\nproc_send_phydm_info_88xx(struct halmac_adapter *adapter,\n\t\t\t  struct halmac_general_info *info);\n\n/**\n * download_firmware_88xx() - download Firmware\n * @adapter : the adapter of halmac\n * @fw_bin : firmware bin\n * @size : firmware size\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ndownload_firmware_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size)\n{\n\tu8 value8;\n\tu32 bckp_idx = 0;\n\tu32 lte_coex_backup = 0;\n\tstruct halmac_backup_info bckp[DLFW_RESTORE_REG_NUM];\n\tenum halmac_ret_status status;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tif (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF)\n\t\treturn HALMAC_RET_POWER_STATE_INVALID;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tstatus = chk_fw_size_88xx(adapter, fw_bin, size);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tchk_h2c_ver_88xx(adapter, fw_bin);\n\n\tif (adapter->halmac_state.wlcpu_mode == HALMAC_WLCPU_ENTER_SLEEP)\n\t\tPLTFM_MSG_WARN(\"[WARN]Enter Sleep..zZZ\\n\");\n\n\tadapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;\n\n\tstatus = ltecoex_reg_read_88xx(adapter, 0x38, &lte_coex_backup);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\twlan_cpu_en_88xx(adapter, 0);\n\n\t/* set HIQ to hi priority */\n\tbckp[bckp_idx].length = 1;\n\tbckp[bckp_idx].mac_register = REG_TXDMA_PQ_MAP + 1;\n\tbckp[bckp_idx].value = HALMAC_REG_R8(REG_TXDMA_PQ_MAP + 1);\n\tbckp_idx++;\n\tvalue8 = HALMAC_DMA_MAPPING_HIGH << 6;\n\tHALMAC_REG_W8(REG_TXDMA_PQ_MAP + 1, value8);\n\n\t/* DLFW only use HIQ, map HIQ to hi priority */\n\tadapter->pq_map[HALMAC_PQ_MAP_HI] = HALMAC_DMA_MAPPING_HIGH;\n\tbckp[bckp_idx].length = 1;\n\tbckp[bckp_idx].mac_register = REG_CR;\n\tbckp[bckp_idx].value = HALMAC_REG_R8(REG_CR);\n\tbckp_idx++;\n\tbckp[bckp_idx].length = 4;\n\tbckp[bckp_idx].mac_register = REG_H2CQ_CSR;\n\tbckp[bckp_idx].value = BIT(31);\n\tbckp_idx++;\n\tvalue8 = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN;\n\tHALMAC_REG_W8(REG_CR, value8);\n\tHALMAC_REG_W32(REG_H2CQ_CSR, BIT(31));\n\n\t/* Config hi priority queue and public priority queue page number */\n\tbckp[bckp_idx].length = 2;\n\tbckp[bckp_idx].mac_register = REG_FIFOPAGE_INFO_1;\n\tbckp[bckp_idx].value = HALMAC_REG_R16(REG_FIFOPAGE_INFO_1);\n\tbckp_idx++;\n\tbckp[bckp_idx].length = 4;\n\tbckp[bckp_idx].mac_register = REG_RQPN_CTRL_2;\n\tbckp[bckp_idx].value = HALMAC_REG_R32(REG_RQPN_CTRL_2) | BIT(31);\n\tbckp_idx++;\n\tHALMAC_REG_W16(REG_FIFOPAGE_INFO_1, 0x200);\n\tHALMAC_REG_W32(REG_RQPN_CTRL_2, bckp[bckp_idx - 1].value);\n\n\t/* Disable beacon related functions */\n\tvalue8 = HALMAC_REG_R8(REG_BCN_CTRL);\n\tbckp[bckp_idx].length = 1;\n\tbckp[bckp_idx].mac_register = REG_BCN_CTRL;\n\tbckp[bckp_idx].value = value8;\n\tbckp_idx++;\n\tvalue8 = (u8)((value8 & (~BIT(3))) | BIT(4));\n\tHALMAC_REG_W8(REG_BCN_CTRL, value8);\n\n\tif (adapter->intf == HALMAC_INTERFACE_SDIO)\n\t\tHALMAC_REG_R32(REG_SDIO_FREE_TXPG);\n\n\tpltfm_reset_88xx(adapter);\n\n\tstatus = start_dlfw_88xx(adapter, fw_bin, size, 0, 0);\n\n\trestore_mac_reg_88xx(adapter, bckp, DLFW_RESTORE_REG_NUM);\n\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto DLFW_FAIL;\n\n\tstatus = dlfw_end_flow_88xx(adapter);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto DLFW_FAIL;\n\n\tstatus = ltecoex_reg_write_88xx(adapter, 0x38, lte_coex_backup);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tadapter->halmac_state.dlfw_state = HALMAC_DLFW_DONE;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n\nDLFW_FAIL:\n\n\t/* Disable FWDL_EN */\n\tvalue8 = HALMAC_REG_R8(REG_MCUFW_CTRL);\n\tvalue8 &= ~BIT(0);\n\tHALMAC_REG_W8(REG_MCUFW_CTRL, value8);\n\n\tvalue8 = HALMAC_REG_R8(REG_SYS_FUNC_EN + 1);\n\tvalue8 |= BIT(2);\n\tHALMAC_REG_W8(REG_SYS_FUNC_EN + 1, value8);\n\n\tif (ltecoex_reg_write_88xx(adapter, 0x38, lte_coex_backup) !=\n\t    HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_LTECOEX_READY_FAIL;\n\n\treturn status;\n}\n\nstatic enum halmac_ret_status\nstart_dlfw_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,\n\t\tu32 dl_addr, u8 emem_only)\n{\n\tu8 *cur_fw;\n\tu16 value16;\n\tu32 imem_size;\n\tu32 dmem_size;\n\tu32 emem_size = 0;\n\tu32 addr;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tenum halmac_ret_status status;\n\n\tdmem_size =\n\t\trtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE)));\n\timem_size =\n\t\trtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE)));\n\tif (0 != ((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4)))\n\t\temem_size =\n\t\trtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE)));\n\n\tdmem_size += WLAN_FW_HDR_CHKSUM_SIZE;\n\timem_size += WLAN_FW_HDR_CHKSUM_SIZE;\n\tif (emem_size != 0)\n\t\temem_size += WLAN_FW_HDR_CHKSUM_SIZE;\n\n\tif (emem_only == 1) {\n\t\tif (!emem_size)\n\t\t\treturn HALMAC_RET_SUCCESS;\n\t\tgoto DLFW_EMEM;\n\t}\n\n\tvalue16 = (u16)(HALMAC_REG_R16(REG_MCUFW_CTRL) & 0x3800);\n\tvalue16 |= BIT(0);\n\tHALMAC_REG_W16(REG_MCUFW_CTRL, value16);\n\n\tcur_fw = fw_bin + WLAN_FW_HDR_SIZE;\n\taddr = rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_DMEM_ADDR)));\n\taddr &= ~BIT(31);\n\tstatus = dlfw_to_mem_88xx(adapter, cur_fw, 0, addr, dmem_size);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tcur_fw = fw_bin + WLAN_FW_HDR_SIZE + dmem_size;\n\taddr = rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_IMEM_ADDR)));\n\taddr &= ~BIT(31);\n\tstatus = dlfw_to_mem_88xx(adapter, cur_fw, 0, addr, imem_size);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\nDLFW_EMEM:\n\tif (emem_size) {\n\t\tcur_fw = fw_bin + WLAN_FW_HDR_SIZE +\n\t\t\t\tdmem_size + imem_size;\n\t\taddr = rtk_le32_to_cpu(*((__le32 *)(fw_bin +\n\t\t\t\t       WLAN_FW_HDR_EMEM_ADDR)));\n\t\taddr &= ~BIT(31);\n\t\tstatus = dlfw_to_mem_88xx(adapter, cur_fw, dl_addr << 7, addr,\n\t\t\t\t\t  emem_size);\n\t\tif (status != HALMAC_RET_SUCCESS)\n\t\t\treturn status;\n\n\t\tif (emem_only == 1)\n\t\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tupdate_fw_info_88xx(adapter, fw_bin);\n\tinit_ofld_feature_state_machine_88xx(adapter);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic void\nchk_h2c_ver_88xx(struct halmac_adapter *adapter, u8 *fw_bin)\n{\n\tu16 halmac_h2c_ver;\n\tu16 fw_h2c_ver;\n\n\tfw_h2c_ver = rtk_le16_to_cpu(*((__le16 *)(fw_bin +\n\t\t\t\t\t\t  WLAN_FW_HDR_H2C_FMT_VER)));\n\thalmac_h2c_ver = H2C_FORMAT_VERSION;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]halmac h2c ver = %x, fw h2c ver = %x!!\\n\",\n\t\t\thalmac_h2c_ver, fw_h2c_ver);\n}\n\nstatic enum halmac_ret_status\nchk_fw_size_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size)\n{\n\tu32 imem_size;\n\tu32 dmem_size;\n\tu32 emem_size = 0;\n\tu32 real_size;\n\n\tif (size < WLAN_FW_HDR_SIZE) {\n\t\tPLTFM_MSG_ERR(\"[ERR]FW size error!\\n\");\n\t\treturn HALMAC_RET_FW_SIZE_ERR;\n\t}\n\n\tdmem_size =\n\t\trtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE)));\n\timem_size =\n\t\trtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE)));\n\tif (0 != ((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4)))\n\t\temem_size =\n\t\trtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE)));\n\n\tdmem_size += WLAN_FW_HDR_CHKSUM_SIZE;\n\timem_size += WLAN_FW_HDR_CHKSUM_SIZE;\n\tif (emem_size != 0)\n\t\temem_size += WLAN_FW_HDR_CHKSUM_SIZE;\n\n\treal_size = WLAN_FW_HDR_SIZE + dmem_size + imem_size + emem_size;\n\tif (size != real_size) {\n\t\tPLTFM_MSG_ERR(\"[ERR]size != real size!\\n\");\n\t\treturn HALMAC_RET_FW_SIZE_ERR;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic void\nwlan_cpu_en_88xx(struct halmac_adapter *adapter, u8 enable)\n{\n\tu8 value8;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tif (enable == 1) {\n\t\t/* cpu io interface enable or disable */\n\t\tvalue8 = HALMAC_REG_R8(REG_RSV_CTRL + 1);\n\t\tvalue8 |= BIT(0);\n\t\tHALMAC_REG_W8(REG_RSV_CTRL + 1, value8);\n\n\t\t/* cpu enable or disable */\n\t\tvalue8 = HALMAC_REG_R8(REG_SYS_FUNC_EN + 1);\n\t\tvalue8 |= BIT(2);\n\t\tHALMAC_REG_W8(REG_SYS_FUNC_EN + 1, value8);\n\n\t} else {\n\t\t/* cpu enable or disable */\n\t\tvalue8 = HALMAC_REG_R8(REG_SYS_FUNC_EN + 1);\n\t\tvalue8 &= ~BIT(2);\n\t\tHALMAC_REG_W8(REG_SYS_FUNC_EN + 1, value8);\n\n\t\t/* cpu io interface enable or disable */\n\t\tvalue8 = HALMAC_REG_R8(REG_RSV_CTRL + 1);\n\t\tvalue8 &= ~BIT(0);\n\t\tHALMAC_REG_W8(REG_RSV_CTRL + 1, value8);\n\t}\n}\n\nstatic void\npltfm_reset_88xx(struct halmac_adapter *adapter)\n{\n\tu8 value8;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tvalue8 = HALMAC_REG_R8(REG_CPU_DMEM_CON + 2) & ~BIT(0);\n\tHALMAC_REG_W8(REG_CPU_DMEM_CON + 2, value8);\n\n\t/* For 8822B & 8821C clock sync issue */\n\tif (adapter->chip_id == HALMAC_CHIP_ID_8821C ||\n\t    adapter->chip_id == HALMAC_CHIP_ID_8822B) {\n\t\tvalue8 = HALMAC_REG_R8(REG_SYS_CLK_CTRL + 1) & ~BIT(6);\n\t\tHALMAC_REG_W8(REG_SYS_CLK_CTRL + 1, value8);\n\t}\n\n\tvalue8 = HALMAC_REG_R8(REG_CPU_DMEM_CON + 2) | BIT(0);\n\tHALMAC_REG_W8(REG_CPU_DMEM_CON + 2, value8);\n\n\tif (adapter->chip_id == HALMAC_CHIP_ID_8821C ||\n\t    adapter->chip_id == HALMAC_CHIP_ID_8822B) {\n\t\tvalue8 = HALMAC_REG_R8(REG_SYS_CLK_CTRL + 1) | BIT(6);\n\t\tHALMAC_REG_W8(REG_SYS_CLK_CTRL + 1, value8);\n\t}\n}\n\n/**\n * free_download_firmware_88xx() - download specific memory firmware\n * @adapter\n * @mem_sel : memory selection\n * @fw_bin : firmware bin\n * @size : firmware size\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n */\nenum halmac_ret_status\nfree_download_firmware_88xx(struct halmac_adapter *adapter,\n\t\t\t    enum halmac_dlfw_mem mem_sel, u8 *fw_bin, u32 size)\n{\n\tu8 tx_pause_bckp;\n\tu32 dl_addr;\n\tu32 dlfw_size_bckp;\n\tenum halmac_ret_status status;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tif (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_NO_DLFW;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tstatus = chk_fw_size_88xx(adapter, fw_bin, size);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tif (((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4)) == 0)\n\t\treturn HALMAC_RET_SUCCESS;\n\n\tdlfw_size_bckp = adapter->dlfw_pkt_size;\n\tif (mem_sel == HALMAC_DLFW_MEM_EMEM) {\n\t\tdl_addr = 0;\n\t} else {\n\t\tdl_addr = adapter->txff_alloc.rsvd_h2c_info_addr;\n\t\tadapter->dlfw_pkt_size = (dlfw_size_bckp > DLFW_RSVDPG_SIZE) ?\n\t\t\t\t\tDLFW_RSVDPG_SIZE : dlfw_size_bckp;\n\t}\n\n\ttx_pause_bckp = HALMAC_REG_R8(REG_TXPAUSE);\n\tHALMAC_REG_W8(REG_TXPAUSE, tx_pause_bckp | BIT(7));\n\n\tstatus = start_dlfw_88xx(adapter, fw_bin, size, dl_addr, 1);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tgoto DL_FREE_FW_END;\n\n\tstatus = free_dl_fw_end_flow_88xx(adapter);\n\nDL_FREE_FW_END:\n\tHALMAC_REG_W8(REG_TXPAUSE, tx_pause_bckp);\n\tadapter->dlfw_pkt_size = dlfw_size_bckp;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn status;\n}\n\n/**\n * reset_wifi_fw_88xx() - reset wifi fw\n * @adapter : the adapter of halmac\n * Author : LIN YONG-CHING\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nreset_wifi_fw_88xx(struct halmac_adapter *adapter)\n{\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\twlan_cpu_en_88xx(adapter, 0);\n\tpltfm_reset_88xx(adapter);\n\tinit_ofld_feature_state_machine_88xx(adapter);\n\twlan_cpu_en_88xx(adapter, 1);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * get_fw_version_88xx() - get FW version\n * @adapter : the adapter of halmac\n * @ver : fw version info\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nget_fw_version_88xx(struct halmac_adapter *adapter,\n\t\t    struct halmac_fw_version *ver)\n{\n\tstruct halmac_fw_version *info = &adapter->fw_ver;\n\n\tif (!ver)\n\t\treturn HALMAC_RET_NULL_POINTER;\n\n\tif (adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE)\n\t\treturn HALMAC_RET_NO_DLFW;\n\n\tver->version = info->version;\n\tver->sub_version = info->sub_version;\n\tver->sub_index = info->sub_index;\n\tver->h2c_version = info->h2c_version;\n\tver->build_time.month = info->build_time.month;\n\tver->build_time.date = info->build_time.date;\n\tver->build_time.hour = info->build_time.hour;\n\tver->build_time.min = info->build_time.min;\n\tver->build_time.year = info->build_time.year;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nupdate_fw_info_88xx(struct halmac_adapter *adapter, u8 *fw_bin)\n{\n\tstruct halmac_fw_version *info = &adapter->fw_ver;\n\n\tinfo->version =\n\t\trtk_le16_to_cpu(*((__le16 *)(fw_bin + WLAN_FW_HDR_VERSION)));\n\tinfo->sub_version = *(fw_bin + WLAN_FW_HDR_SUBVERSION);\n\tinfo->sub_index = *(fw_bin + WLAN_FW_HDR_SUBINDEX);\n\tinfo->h2c_version = rtk_le16_to_cpu(*((__le16 *)(fw_bin +\n\t\t\t\t\t    WLAN_FW_HDR_H2C_FMT_VER)));\n\tinfo->build_time.month = *(fw_bin + WLAN_FW_HDR_MONTH);\n\tinfo->build_time.date = *(fw_bin + WLAN_FW_HDR_DATE);\n\tinfo->build_time.hour = *(fw_bin + WLAN_FW_HDR_HOUR);\n\tinfo->build_time.min = *(fw_bin + WLAN_FW_HDR_MIN);\n\tinfo->build_time.year =\n\t\trtk_le16_to_cpu(*((__le16 *)(fw_bin + WLAN_FW_HDR_YEAR)));\n\n\tPLTFM_MSG_TRACE(\"[TRACE]=== FW info ===\\n\");\n\tPLTFM_MSG_TRACE(\"[TRACE]ver : %X\\n\", info->version);\n\tPLTFM_MSG_TRACE(\"[TRACE]sub-ver : %X\\n\",\n\t\t\tinfo->sub_version);\n\tPLTFM_MSG_TRACE(\"[TRACE]sub-idx : %X\\n\",\n\t\t\tinfo->sub_index);\n\tPLTFM_MSG_TRACE(\"[TRACE]build : %d/%d/%d %d:%d\\n\",\n\t\t\tinfo->build_time.year, info->build_time.month,\n\t\t\tinfo->build_time.date, info->build_time.hour,\n\t\t\tinfo->build_time.min);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\ndlfw_to_mem_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 src, u32 dest,\n\t\t u32 size)\n{\n\tu8 first_part;\n\tu32 mem_offset;\n\tu32 residue_size;\n\tu32 pkt_size;\n\tenum halmac_ret_status status;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tmem_offset = 0;\n\tfirst_part = 1;\n\tresidue_size = size;\n\n\tHALMAC_REG_W32_SET(REG_DDMA_CH0CTRL, BIT_DDMACH0_RESET_CHKSUM_STS);\n\n\twhile (residue_size != 0) {\n\t\tif (residue_size >= adapter->dlfw_pkt_size)\n\t\t\tpkt_size = adapter->dlfw_pkt_size;\n\t\telse\n\t\t\tpkt_size = residue_size;\n\n\t\tstatus = send_fwpkt_88xx(adapter, (u16)(src >> 7),\n\t\t\t\t\t fw_bin + mem_offset, pkt_size);\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]send fw pkt!!\\n\");\n\t\t\treturn status;\n\t\t}\n\n\t\tstatus = iddma_dlfw_88xx(adapter,\n\t\t\t\t\t OCPBASE_TXBUF_88XX +\n\t\t\t\t\t src + adapter->hw_cfg_info.txdesc_size,\n\t\t\t\t\t dest + mem_offset, pkt_size,\n\t\t\t\t\t first_part);\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]iddma dlfw!!\\n\");\n\t\t\treturn status;\n\t\t}\n\n\t\tfirst_part = 0;\n\t\tmem_offset += pkt_size;\n\t\tresidue_size -= pkt_size;\n\t}\n\n\tstatus = check_fw_chksum_88xx(adapter, dest);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]chk fw chksum!!\\n\");\n\t\treturn status;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic void\nrestore_mac_reg_88xx(struct halmac_adapter *adapter,\n\t\t     struct halmac_backup_info *info, u32 num)\n{\n\tu8 len;\n\tu32 i;\n\tu32 reg;\n\tu32 value;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tstruct halmac_backup_info *curr_info = info;\n\n\tfor (i = 0; i < num; i++) {\n\t\treg = curr_info->mac_register;\n\t\tvalue = curr_info->value;\n\t\tlen = curr_info->length;\n\n\t\tif (len == 1)\n\t\t\tHALMAC_REG_W8(reg, (u8)value);\n\t\telse if (len == 2)\n\t\t\tHALMAC_REG_W16(reg, (u16)value);\n\t\telse if (len == 4)\n\t\t\tHALMAC_REG_W32(reg, value);\n\n\t\tcurr_info++;\n\t}\n}\n\nstatic enum halmac_ret_status\ndlfw_end_flow_88xx(struct halmac_adapter *adapter)\n{\n\tu16 fw_ctrl;\n\tu32 cnt;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tHALMAC_REG_W32(REG_TXDMA_STATUS, BIT(2));\n\n\t/* Check IMEM & DMEM checksum is OK or not */\n\tfw_ctrl = HALMAC_REG_R16(REG_MCUFW_CTRL);\n\tif ((fw_ctrl & 0x50) != 0x50)\n\t\treturn HALMAC_RET_IDMEM_CHKSUM_FAIL;\n\n\tHALMAC_REG_W16(REG_MCUFW_CTRL, (fw_ctrl | BIT_FW_DW_RDY) & ~BIT(0));\n\n\twlan_cpu_en_88xx(adapter, 1);\n\tPLTFM_MSG_TRACE(\"[TRACE]Dlfw OK, enable CPU\\n\");\n\n\tcnt = 5000;\n\twhile (HALMAC_REG_R16(REG_MCUFW_CTRL) != 0xC078) {\n\t\tif (cnt == 0) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]Check 0x80 = 0xC078 fail\\n\");\n\t\t\tif ((HALMAC_REG_R32(REG_FW_DBG7) & 0xFFFFFF00) ==\n\t\t\t    ILLEGAL_KEY_GROUP) {\n\t\t\t\tPLTFM_MSG_ERR(\"[ERR]Key!!\\n\");\n\t\t\t\treturn HALMAC_RET_ILLEGAL_KEY_FAIL;\n\t\t\t}\n\t\t\treturn HALMAC_RET_FW_READY_CHK_FAIL;\n\t\t}\n\t\tcnt--;\n\t\tPLTFM_DELAY_US(50);\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]0x80=0xC078, cnt=%d\\n\", cnt);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nfree_dl_fw_end_flow_88xx(struct halmac_adapter *adapter)\n{\n\tu32 cnt;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tcnt = 100;\n\twhile (HALMAC_REG_R8(REG_HMETFR + 3) != 0) {\n\t\tcnt--;\n\t\tif (cnt == 0) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]0x1CF != 0\\n\");\n\t\t\treturn HALMAC_RET_DLFW_FAIL;\n\t\t}\n\t\tPLTFM_DELAY_US(50);\n\t}\n\n\tHALMAC_REG_W8(REG_HMETFR + 3, ID_INFORM_DLEMEM_RDY);\n\n\tcnt = 10000;\n\twhile (HALMAC_REG_R8(REG_MCU_TST_CFG) != ID_CHECK_DLEMEM_RDY) {\n\t\tcnt--;\n\t\tif (cnt == 0) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]0x84 != 0x80\\n\");\n\t\t\treturn HALMAC_RET_DLFW_FAIL;\n\t\t}\n\t\tPLTFM_DELAY_US(50);\n\t}\n\n\tHALMAC_REG_W8(REG_MCU_TST_CFG, 0);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nsend_fwpkt_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *fw_bin,\n\t\tu32 size)\n{\n\tu8 *fw_add_dum = NULL;\n\tenum halmac_ret_status status;\n\n\tif (adapter->intf == HALMAC_INTERFACE_USB &&\n\t    !((size + TX_DESC_SIZE_88XX) & (512 - 1))) {\n\t\tfw_add_dum = (u8 *)PLTFM_MALLOC(size + 1);\n\t\tif (!fw_add_dum) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]fw bin malloc!!\\n\");\n\t\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t\t}\n\n\t\tPLTFM_MEMCPY(fw_add_dum, fw_bin, size);\n\n\t\tstatus = dl_rsvd_page_88xx(adapter, pg_addr,\n\t\t\t\t\t   fw_add_dum, size + 1);\n\t\tif (status != HALMAC_RET_SUCCESS)\n\t\t\tPLTFM_MSG_ERR(\"[ERR]dl rsvd page - dum!!\\n\");\n\n\t\tPLTFM_FREE(fw_add_dum, size + 1);\n\n\t\treturn status;\n\t}\n\n\tstatus = dl_rsvd_page_88xx(adapter, pg_addr, fw_bin, size);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tPLTFM_MSG_ERR(\"[ERR]dl rsvd page!!\\n\");\n\n\treturn status;\n}\n\nstatic enum halmac_ret_status\niddma_dlfw_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 len,\n\t\tu8 first)\n{\n\tu32 cnt;\n\tu32 ch0_ctrl = (u32)(BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN);\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tcnt = HALMC_DDMA_POLLING_COUNT;\n\twhile (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) {\n\t\tcnt--;\n\t\tif (cnt == 0) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]ch0 ready!!\\n\");\n\t\t\treturn HALMAC_RET_DDMA_FAIL;\n\t\t}\n\t}\n\n\tch0_ctrl |= (len & BIT_MASK_DDMACH0_DLEN);\n\tif (first == 0)\n\t\tch0_ctrl |= BIT_DDMACH0_CHKSUM_CONT;\n\n\tif (iddma_en_88xx(adapter, src, dest, ch0_ctrl) !=\n\t    HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]iddma en!!\\n\");\n\t\treturn HALMAC_RET_DDMA_FAIL;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\niddma_en_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 ctrl)\n{\n\tu32 cnt = HALMC_DDMA_POLLING_COUNT;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tHALMAC_REG_W32(REG_DDMA_CH0SA, src);\n\tHALMAC_REG_W32(REG_DDMA_CH0DA, dest);\n\tHALMAC_REG_W32(REG_DDMA_CH0CTRL, ctrl);\n\n\twhile (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) {\n\t\tcnt--;\n\t\tif (cnt == 0)\n\t\t\treturn HALMAC_RET_DDMA_FAIL;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\ncheck_fw_chksum_88xx(struct halmac_adapter *adapter, u32 mem_addr)\n{\n\tu8 fw_ctrl;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tfw_ctrl = HALMAC_REG_R8(REG_MCUFW_CTRL);\n\n\tif (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) {\n\t\tif (mem_addr < OCPBASE_DMEM_88XX) {\n\t\t\tfw_ctrl |= BIT_IMEM_DW_OK;\n\t\t\tfw_ctrl &= ~BIT_IMEM_CHKSUM_OK;\n\t\t\tHALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl);\n\t\t} else {\n\t\t\tfw_ctrl |= BIT_DMEM_DW_OK;\n\t\t\tfw_ctrl &= ~BIT_DMEM_CHKSUM_OK;\n\t\t\tHALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl);\n\t\t}\n\n\t\tPLTFM_MSG_ERR(\"[ERR]fw chksum!!\\n\");\n\n\t\treturn HALMAC_RET_FW_CHECKSUM_FAIL;\n\t}\n\n\tif (mem_addr < OCPBASE_DMEM_88XX) {\n\t\tfw_ctrl |= (BIT_IMEM_DW_OK | BIT_IMEM_CHKSUM_OK);\n\t\tHALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl);\n\t} else {\n\t\tfw_ctrl |= (BIT_DMEM_DW_OK | BIT_DMEM_CHKSUM_OK);\n\t\tHALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl);\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * check_fw_status_88xx() -check fw status\n * @adapter : the adapter of halmac\n * @status : fw status\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncheck_fw_status_88xx(struct halmac_adapter *adapter, u8 *fw_status)\n{\n\tu32 cnt;\n\tu32 fw_dbg6;\n\tu32 fw_pc;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\t*fw_status = 1;\n\n\tfw_dbg6 = HALMAC_REG_R32(REG_FW_DBG6);\n\n\tif (fw_dbg6 != 0) {\n\t\tPLTFM_MSG_ERR(\"[ERR]REG_FW_DBG6 !=0\\n\");\n\t\tif ((fw_dbg6 & FW_STATUS_CHK_WARN) != 0)\n\t\t\tPLTFM_MSG_WARN(\"[WARN]fw status(warn):%X\\n\", fw_dbg6);\n\n\t\tif ((fw_dbg6 & FW_STATUS_CHK_ERR) != 0)\n\t\t\tPLTFM_MSG_ERR(\"[ERR]fw status(err):%X\\n\", fw_dbg6);\n\n\t\tif ((fw_dbg6 & FW_STATUS_CHK_FATAL) != 0) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]fw status(fatal):%X\\n\", fw_dbg6);\n\t\t\tfw_fatal_status_debug_88xx(adapter);\n\t\t\t*fw_status = 0;\n\t\t\treturn status;\n\t\t}\n\t}\n\n\tfw_pc = HALMAC_REG_R32(REG_FW_DBG7);\n\tcnt = 10;\n\twhile (HALMAC_REG_R32(REG_FW_DBG7) == fw_pc) {\n\t\tcnt--;\n\t\tif (cnt == 0)\n\t\t\tbreak;\n\t}\n\n\tif (cnt == 0) {\n\t\tcnt = 200;\n\t\twhile (HALMAC_REG_R32(REG_FW_DBG7) == fw_pc) {\n\t\t\tcnt--;\n\t\t\tif (cnt == 0) {\n\t\t\t\tPLTFM_MSG_ERR(\"[ERR]fw pc\\n\");\n\t\t\t\t*fw_status = 0;\n\t\t\t\treturn status;\n\t\t\t}\n\t\t\tPLTFM_DELAY_US(50);\n\t\t}\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn status;\n}\n\nstatic void\nfw_fatal_status_debug_88xx(struct halmac_adapter *adapter)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_ERR(\"[ERR]0x%X = %X\\n\",\n\t\t      REG_FW_DBG6, HALMAC_REG_R32(REG_FW_DBG6));\n\n\tPLTFM_MSG_ERR(\"[ERR]0x%X = %X\\n\",\n\t\t      REG_ARFR5, HALMAC_REG_R32(REG_ARFR5));\n\n\tPLTFM_MSG_ERR(\"[ERR]0x%X = %X\\n\",\n\t\t      REG_MCUTST_I, HALMAC_REG_R32(REG_MCUTST_I));\n}\n\nenum halmac_ret_status\ndump_fw_dmem_88xx(struct halmac_adapter *adapter, u8 *dmem, u32 *size)\n{\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfg_max_dl_size_88xx() - config max download FW size\n * @adapter : the adapter of halmac\n * @size : max download fw size\n *\n * Halmac uses this setting to set max packet size for\n * download FW.\n * If user has not called this API, halmac use default\n * setting for download FW\n * Note1 : size need multiple of 2\n * Note2 : max size is 31K\n *\n * Author : Ivan Lin/KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_max_dl_size_88xx(struct halmac_adapter *adapter, u32 size)\n{\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (size > DLFW_PKT_SIZE_LIMIT) {\n\t\tPLTFM_MSG_ERR(\"[ERR]size > max dl size!\\n\");\n\t\treturn HALMAC_RET_CFG_DLFW_SIZE_FAIL;\n\t}\n\n\tif ((size & (2 - 1)) != 0) {\n\t\tPLTFM_MSG_ERR(\"[ERR]not multiple of 2!\\n\");\n\t\treturn HALMAC_RET_CFG_DLFW_SIZE_FAIL;\n\t}\n\n\tadapter->dlfw_pkt_size = size;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]Cfg max size:%X\\n\", size);\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * enter_cpu_sleep_mode_88xx() -wlan cpu enter sleep mode\n * @adapter : the adapter of halmac\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nenter_cpu_sleep_mode_88xx(struct halmac_adapter *adapter)\n{\n\tu32 cnt;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tenum halmac_wlcpu_mode *cur_mode = &adapter->halmac_state.wlcpu_mode;\n\n\tif (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_NO_DLFW;\n\n\tif (*cur_mode != HALMAC_WLCPU_ACTIVE)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\tcnt = 100;\n\twhile (HALMAC_REG_R8(REG_HMETFR + 3) != 0) {\n\t\tcnt--;\n\t\tif (cnt == 0) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]0x1CF != 0\\n\");\n\t\t\treturn HALMAC_RET_STATE_INCORRECT;\n\t\t}\n\t\tPLTFM_DELAY_US(50);\n\t}\n\n\tHALMAC_REG_W8(REG_HMETFR + 3, ID_INFORM_ENETR_CPU_SLEEP);\n\n\t*cur_mode = HALMAC_WLCPU_ENTER_SLEEP;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * get_cpu_mode_88xx() -get wlcpu mode\n * @adapter : the adapter of halmac\n * @mode : cpu mode\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nget_cpu_mode_88xx(struct halmac_adapter *adapter,\n\t\t  enum halmac_wlcpu_mode *mode)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tenum halmac_wlcpu_mode *cur_mode = &adapter->halmac_state.wlcpu_mode;\n\n\tif (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_NO_DLFW;\n\n\tif (*cur_mode == HALMAC_WLCPU_ACTIVE) {\n\t\t*mode = HALMAC_WLCPU_ACTIVE;\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tif (*cur_mode == HALMAC_WLCPU_SLEEP) {\n\t\t*mode = HALMAC_WLCPU_SLEEP;\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tif (HALMAC_REG_R8(REG_MCU_TST_CFG) == ID_CHECK_ENETR_CPU_SLEEP) {\n\t\t*mode = HALMAC_WLCPU_SLEEP;\n\t\tHALMAC_REG_W8(REG_MCU_TST_CFG, 0);\n\t} else {\n\t\t*mode = HALMAC_WLCPU_ENTER_SLEEP;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * send_general_info_88xx() -send general information to FW\n * @adapter : the adapter of halmac\n * @info : general information\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nsend_general_info_88xx(struct halmac_adapter *adapter,\n\t\t       struct halmac_general_info *info)\n{\n\tu8 h2cq_ele[4] = {0};\n\tu32 h2cq_addr;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tif (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_NO_DLFW;\n\n\tif (adapter->fw_ver.h2c_version < 4)\n\t\treturn HALMAC_RET_FW_NO_SUPPORT;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) {\n\t\tPLTFM_MSG_ERR(\"[ERR]no dl fw!!\\n\");\n\t\treturn HALMAC_RET_NO_DLFW;\n\t}\n\n\tstatus = proc_send_general_info_88xx(adapter, info);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]send gen info!!\\n\");\n\t\treturn status;\n\t}\n\n\tstatus = proc_send_phydm_info_88xx(adapter, info);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]send phydm info\\n\");\n\t\treturn status;\n\t}\n\n\th2cq_addr = adapter->txff_alloc.rsvd_h2cq_addr;\n\th2cq_addr <<= TX_PAGE_SIZE_SHIFT_88XX;\n\tstatus = dump_fifo_88xx(adapter, HAL_FIFO_SEL_TX,\n\t\t\t\th2cq_addr, 4, h2cq_ele);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]dump h2cq!!\\n\");\n\t\treturn status;\n\t}\n\n\tif ((h2cq_ele[0] & 0x7F) != 0x01 || h2cq_ele[1] != 0xFF) {\n\t\tPLTFM_MSG_ERR(\"[ERR]h2cq compare!!\\n\");\n\t\treturn HALMAC_RET_SEND_H2C_FAIL;\n\t}\n\n\tif (adapter->halmac_state.dlfw_state == HALMAC_DLFW_DONE)\n\t\tadapter->halmac_state.dlfw_state = HALMAC_GEN_INFO_SENT;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nproc_send_general_info_88xx(struct halmac_adapter *adapter,\n\t\t\t    struct halmac_general_info *info)\n{\n\tu8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };\n\tu16 seq_num = 0;\n\tstruct halmac_h2c_header_info hdr_info;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s\\n\", __func__);\n\n\tGENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_buf,\n\t\t\t\t\tadapter->txff_alloc.rsvd_fw_txbuf_addr -\n\t\t\t\t\tadapter->txff_alloc.rsvd_boundary);\n\n\thdr_info.sub_cmd_id = SUB_CMD_ID_GENERAL_INFO;\n\thdr_info.content_size = 4;\n\thdr_info.ack = 0;\n\tset_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);\n\n\tstatus = send_h2c_pkt_88xx(adapter, h2c_buf);\n\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tPLTFM_MSG_ERR(\"[ERR]send h2c!!\\n\");\n\n\treturn status;\n}\n\nstatic enum halmac_ret_status\nproc_send_phydm_info_88xx(struct halmac_adapter *adapter,\n\t\t\t  struct halmac_general_info *info)\n{\n\tu8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };\n\tu16 seq_num = 0;\n\tstruct halmac_h2c_header_info hdr_info;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s\\n\", __func__);\n\n\tPHYDM_INFO_SET_REF_TYPE(h2c_buf, info->rfe_type);\n\tPHYDM_INFO_SET_RF_TYPE(h2c_buf, info->rf_type);\n\tPHYDM_INFO_SET_CUT_VER(h2c_buf, adapter->chip_ver);\n\tPHYDM_INFO_SET_RX_ANT_STATUS(h2c_buf, info->rx_ant_status);\n\tPHYDM_INFO_SET_TX_ANT_STATUS(h2c_buf, info->tx_ant_status);\n\n\thdr_info.sub_cmd_id = SUB_CMD_ID_PHYDM_INFO;\n\thdr_info.content_size = 8;\n\thdr_info.ack = 0;\n\tset_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);\n\n\tstatus = send_h2c_pkt_88xx(adapter, h2c_buf);\n\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tPLTFM_MSG_ERR(\"[ERR]send h2c!!\\n\");\n\n\treturn status;\n}\n\n/**\n * drv_fwctrl_88xx() - send drv-defined h2c pkt\n * @adapter : the adapter of halmac\n * @payload : no include offload pkt h2c header\n * @size : no include offload pkt h2c header\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ndrv_fwctrl_88xx(struct halmac_adapter *adapter, u8 *payload, u32 size, u8 ack)\n{\n\tu8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };\n\tu16 seq_num = 0;\n\tstruct halmac_h2c_header_info hdr_info;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tif (!payload)\n\t\treturn HALMAC_RET_DATA_BUF_NULL;\n\n\tif (size > H2C_PKT_SIZE_88XX - H2C_PKT_HDR_SIZE_88XX)\n\t\treturn HALMAC_RET_DATA_SIZE_INCORRECT;\n\n\tPLTFM_MEMCPY(h2c_buf + H2C_PKT_HDR_SIZE_88XX, payload, size);\n\n\thdr_info.sub_cmd_id = SUB_CMD_ID_FW_FWCTRL;\n\thdr_info.content_size = (u16)size;\n\thdr_info.ack = ack;\n\tset_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);\n\n\tstatus = send_h2c_pkt_88xx(adapter, h2c_buf);\n\n\tif (status != HALMAC_RET_SUCCESS)\n\t\tPLTFM_MSG_ERR(\"[ERR]send h2c!!\\n\");\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn status;\n}\n\n#endif /* HALMAC_88XX_SUPPORT */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_fw_88xx.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_FW_88XX_H_\n#define _HALMAC_FW_88XX_H_\n\n#include \"../halmac_api.h\"\n\n#if HALMAC_88XX_SUPPORT\n\n#define HALMC_DDMA_POLLING_COUNT\t\t1000\n\nenum halmac_ret_status\ndownload_firmware_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size);\n\nenum halmac_ret_status\nfree_download_firmware_88xx(struct halmac_adapter *adapter,\n\t\t\t    enum halmac_dlfw_mem mem_sel, u8 *fw_bin, u32 size);\n\nenum halmac_ret_status\nreset_wifi_fw_88xx(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\nget_fw_version_88xx(struct halmac_adapter *adapter,\n\t\t    struct halmac_fw_version *ver);\n\nenum halmac_ret_status\ncheck_fw_status_88xx(struct halmac_adapter *adapter, u8 *fw_status);\n\nenum halmac_ret_status\ndump_fw_dmem_88xx(struct halmac_adapter *adapter, u8 *dmem, u32 *size);\n\nenum halmac_ret_status\ncfg_max_dl_size_88xx(struct halmac_adapter *adapter, u32 size);\n\nenum halmac_ret_status\nenter_cpu_sleep_mode_88xx(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\nget_cpu_mode_88xx(struct halmac_adapter *adapter,\n\t\t  enum halmac_wlcpu_mode *mode);\n\nenum halmac_ret_status\nsend_general_info_88xx(struct halmac_adapter *adapter,\n\t\t       struct halmac_general_info *info);\n\nenum halmac_ret_status\ndrv_fwctrl_88xx(struct halmac_adapter *adapter, u8 *payload, u32 size, u8 ack);\n\n#endif /* HALMAC_88XX_SUPPORT */\n\n#endif/* _HALMAC_FW_88XX_H_ */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_gpio_88xx.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"halmac_gpio_88xx.h\"\n\n#if HALMAC_88XX_SUPPORT\n\n/**\n * pinmux_wl_led_mode_88xx() -control wlan led gpio function\n * @adapter : the adapter of halmac\n * @mode : wlan led mode\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\npinmux_wl_led_mode_88xx(struct halmac_adapter *adapter,\n\t\t\tenum halmac_wlled_mode mode)\n{\n\tu8 value8;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tvalue8 = HALMAC_REG_R8(REG_LED_CFG + 2);\n\tvalue8 &= ~(BIT(6));\n\tvalue8 |= BIT(3);\n\tvalue8 &= ~(BIT(0) | BIT(1) | BIT(2));\n\n\tswitch (mode) {\n\tcase HALMAC_WLLED_MODE_TRX:\n\t\tvalue8 |= 2;\n\t\tbreak;\n\tcase HALMAC_WLLED_MODE_TX:\n\t\tvalue8 |= 4;\n\t\tbreak;\n\tcase HALMAC_WLLED_MODE_RX:\n\t\tvalue8 |= 6;\n\t\tbreak;\n\tcase HALMAC_WLLED_MODE_SW_CTRL:\n\t\tvalue8 |= 0;\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_SWITCH_CASE_ERROR;\n\t}\n\n\tHALMAC_REG_W8(REG_LED_CFG + 2, value8);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * pinmux_wl_led_sw_ctrl_88xx() -control wlan led on/off\n * @adapter : the adapter of halmac\n * @on : on(1), off(0)\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nvoid\npinmux_wl_led_sw_ctrl_88xx(struct halmac_adapter *adapter, u8 on)\n{\n\tu8 value8;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tvalue8 = HALMAC_REG_R8(REG_LED_CFG + 2);\n\tvalue8 = (on == 0) ? value8 | BIT(3) : value8 & ~(BIT(3));\n\n\tHALMAC_REG_W8(REG_LED_CFG + 2, value8);\n}\n\n/**\n * pinmux_sdio_int_polarity_88xx() -control sdio int polarity\n * @adapter : the adapter of halmac\n * @low_active : low active(1), high active(0)\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nvoid\npinmux_sdio_int_polarity_88xx(struct halmac_adapter *adapter, u8 low_active)\n{\n\tu8 value8;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tvalue8 = HALMAC_REG_R8(REG_SYS_SDIO_CTRL + 2);\n\tvalue8 = (low_active == 0) ? value8 | BIT(3) : value8 & ~(BIT(3));\n\n\tHALMAC_REG_W8(REG_SYS_SDIO_CTRL + 2, value8);\n}\n\n/**\n * pinmux_gpio_mode_88xx() -control gpio io mode\n * @adapter : the adapter of halmac\n * @gpio_id : gpio0~15(0~15)\n * @output : output(1), input(0)\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\npinmux_gpio_mode_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 output)\n{\n\tu16 value16;\n\tu8 in_out;\n\tu32 offset;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tif (gpio_id <= 7)\n\t\toffset = REG_GPIO_PIN_CTRL + 2;\n\telse if (gpio_id >= 8 && gpio_id <= 15)\n\t\toffset = REG_GPIO_EXT_CTRL + 2;\n\telse\n\t\treturn HALMAC_RET_WRONG_GPIO;\n\n\tin_out = (output == 0) ? 0 : 1;\n\tgpio_id &= (8 - 1);\n\n\tvalue16 = HALMAC_REG_R16(offset);\n\tvalue16 &= ~((1 << gpio_id) | (1 << gpio_id << 8));\n\tvalue16 |= (in_out << gpio_id);\n\tHALMAC_REG_W16(offset, value16);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * pinmux_gpio_output_88xx() -control gpio output high/low\n * @adapter : the adapter of halmac\n * @gpio_id : gpio0~15(0~15)\n * @high : high(1), low(0)\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\npinmux_gpio_output_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 high)\n{\n\tu8 value8;\n\tu8 hi_low;\n\tu32 offset;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tif (gpio_id <= 7)\n\t\toffset = REG_GPIO_PIN_CTRL + 1;\n\telse if (gpio_id >= 8 && gpio_id <= 15)\n\t\toffset = REG_GPIO_EXT_CTRL + 1;\n\telse\n\t\treturn HALMAC_RET_WRONG_GPIO;\n\n\thi_low = (high == 0) ? 0 : 1;\n\tgpio_id &= (8 - 1);\n\n\tvalue8 = HALMAC_REG_R8(offset);\n\tvalue8 &= ~(1 << gpio_id);\n\tvalue8 |= (hi_low << gpio_id);\n\tHALMAC_REG_W8(offset, value8);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * halmac_pinmux_status_88xx() -get current gpio status(high/low)\n * @adapter : the adapter of halmac\n * @pin_id : 0~15(0~15)\n * @phigh : high(1), low(0)\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\npinmux_pin_status_88xx(struct halmac_adapter *adapter, u8 pin_id, u8 *high)\n{\n\tu8 value8;\n\tu32 offset;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tif (pin_id <= 7)\n\t\toffset = REG_GPIO_PIN_CTRL;\n\telse if (pin_id >= 8 && pin_id <= 15)\n\t\toffset = REG_GPIO_EXT_CTRL;\n\telse\n\t\treturn HALMAC_RET_WRONG_GPIO;\n\n\tpin_id &= (8 - 1);\n\n\tvalue8 = HALMAC_REG_R8(offset);\n\t*high = (value8 & (1 << pin_id)) >> pin_id;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\npinmux_parser_88xx(struct halmac_adapter *adapter,\n\t\t   const struct halmac_gpio_pimux_list *list, u32 size,\n\t\t   u32 gpio_id, u32 *cur_func)\n{\n\tu32 i;\n\tu8 value8;\n\tconst struct halmac_gpio_pimux_list *cur_list = list;\n\tenum halmac_gpio_cfg_state *state;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tstate = &adapter->halmac_state.gpio_cfg_state;\n\n\tif (*state == HALMAC_GPIO_CFG_STATE_BUSY)\n\t\treturn HALMAC_RET_BUSY_STATE;\n\n\t*state = HALMAC_GPIO_CFG_STATE_BUSY;\n\n\tfor (i = 0; i < size; i++) {\n\t\tif (gpio_id != cur_list->id) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]offset:%X, value:%X, func:%X\\n\",\n\t\t\t\t      cur_list->offset, cur_list->value,\n\t\t\t\t      cur_list->func);\n\t\t\tPLTFM_MSG_ERR(\"[ERR]id1 : %X, id2 : %X\\n\",\n\t\t\t\t      gpio_id, cur_list->id);\n\t\t\t*state = HALMAC_GPIO_CFG_STATE_IDLE;\n\t\t\treturn HALMAC_RET_GET_PINMUX_ERR;\n\t\t}\n\t\tvalue8 = HALMAC_REG_R8(cur_list->offset);\n\t\tvalue8 &= cur_list->msk;\n\t\tif (value8 == cur_list->value) {\n\t\t\t*cur_func = cur_list->func;\n\t\t\tbreak;\n\t\t}\n\t\tcur_list++;\n\t}\n\n\t*state = HALMAC_GPIO_CFG_STATE_IDLE;\n\n\tif (i == size)\n\t\treturn HALMAC_RET_GET_PINMUX_ERR;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\npinmux_switch_88xx(struct halmac_adapter *adapter,\n\t\t   const struct halmac_gpio_pimux_list *list, u32 size,\n\t\t   u32 gpio_id, enum halmac_gpio_func gpio_func)\n{\n\tu32 i;\n\tu8 value8;\n\tu16 switch_func;\n\tconst struct halmac_gpio_pimux_list *cur_list = list;\n\tenum halmac_gpio_cfg_state *state;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tstate = &adapter->halmac_state.gpio_cfg_state;\n\n\tif (*state == HALMAC_GPIO_CFG_STATE_BUSY)\n\t\treturn HALMAC_RET_BUSY_STATE;\n\n\tswitch (gpio_func) {\n\tcase HALMAC_GPIO_FUNC_WL_LED:\n\t\tswitch_func = HALMAC_WL_LED;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SDIO_INT:\n\t\tswitch_func = HALMAC_SDIO_INT;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_BT_HOST_WAKE1:\n\tcase HALMAC_GPIO_FUNC_BT_DEV_WAKE1:\n\t\tswitch_func = HALMAC_GPIO13_14_WL_CTRL_EN;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_0:\n\tcase HALMAC_GPIO_FUNC_SW_IO_1:\n\tcase HALMAC_GPIO_FUNC_SW_IO_2:\n\tcase HALMAC_GPIO_FUNC_SW_IO_3:\n\tcase HALMAC_GPIO_FUNC_SW_IO_4:\n\tcase HALMAC_GPIO_FUNC_SW_IO_5:\n\tcase HALMAC_GPIO_FUNC_SW_IO_6:\n\tcase HALMAC_GPIO_FUNC_SW_IO_7:\n\tcase HALMAC_GPIO_FUNC_SW_IO_8:\n\tcase HALMAC_GPIO_FUNC_SW_IO_9:\n\tcase HALMAC_GPIO_FUNC_SW_IO_10:\n\tcase HALMAC_GPIO_FUNC_SW_IO_11:\n\tcase HALMAC_GPIO_FUNC_SW_IO_12:\n\tcase HALMAC_GPIO_FUNC_SW_IO_13:\n\tcase HALMAC_GPIO_FUNC_SW_IO_14:\n\tcase HALMAC_GPIO_FUNC_SW_IO_15:\n\t\tswitch_func = HALMAC_SW_IO;\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_SWITCH_CASE_ERROR;\n\t}\n\n\tfor (i = 0; i < size; i++) {\n\t\tif (gpio_id != cur_list->id) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]offset:%X, value:%X, func:%X\\n\",\n\t\t\t\t      cur_list->offset, cur_list->value,\n\t\t\t\t      cur_list->func);\n\t\t\tPLTFM_MSG_ERR(\"[ERR]id1 : %X, id2 : %X\\n\",\n\t\t\t\t      gpio_id, cur_list->id);\n\t\t\treturn HALMAC_RET_GET_PINMUX_ERR;\n\t\t}\n\n\t\tif (switch_func == cur_list->func)\n\t\t\tbreak;\n\n\t\tcur_list++;\n\t}\n\n\tif (i == size) {\n\t\tPLTFM_MSG_ERR(\"[ERR]gpio func error:%X %X\\n\",\n\t\t\t      gpio_id, cur_list->id);\n\t\treturn HALMAC_RET_GET_PINMUX_ERR;\n\t}\n\n\t*state = HALMAC_GPIO_CFG_STATE_BUSY;\n\n\tcur_list = list;\n\tfor (i = 0; i < size; i++) {\n\t\tvalue8 = HALMAC_REG_R8(cur_list->offset);\n\t\tvalue8 &= ~(cur_list->msk);\n\n\t\tif (switch_func == cur_list->func) {\n\t\t\tvalue8 |= (cur_list->value & cur_list->msk);\n\t\t\tHALMAC_REG_W8(cur_list->offset, value8);\n\t\t\tbreak;\n\t\t}\n\n\t\tvalue8 |= (~cur_list->value & cur_list->msk);\n\t\tHALMAC_REG_W8(cur_list->offset, value8);\n\n\t\tcur_list++;\n\t}\n\n\t*state = HALMAC_GPIO_CFG_STATE_IDLE;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\npinmux_record_88xx(struct halmac_adapter *adapter,\n\t\t   enum halmac_gpio_func gpio_func, u8 val)\n{\n\tswitch (gpio_func) {\n\tcase HALMAC_GPIO_FUNC_WL_LED:\n\t\tadapter->pinmux_info.wl_led = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SDIO_INT:\n\t\tadapter->pinmux_info.sdio_int = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_BT_HOST_WAKE1:\n\t\tadapter->pinmux_info.bt_host_wake = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_BT_DEV_WAKE1:\n\t\tadapter->pinmux_info.bt_dev_wake = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_0:\n\t\tadapter->pinmux_info.sw_io_0 = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_1:\n\t\tadapter->pinmux_info.sw_io_1 = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_2:\n\t\tadapter->pinmux_info.sw_io_2 = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_3:\n\t\tadapter->pinmux_info.sw_io_3 = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_4:\n\t\tadapter->pinmux_info.sw_io_4 = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_5:\n\t\tadapter->pinmux_info.sw_io_5 = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_6:\n\t\tadapter->pinmux_info.sw_io_6 = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_7:\n\t\tadapter->pinmux_info.sw_io_7 = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_8:\n\t\tadapter->pinmux_info.sw_io_8 = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_9:\n\t\tadapter->pinmux_info.sw_io_9 = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_10:\n\t\tadapter->pinmux_info.sw_io_10 = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_11:\n\t\tadapter->pinmux_info.sw_io_11 = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_12:\n\t\tadapter->pinmux_info.sw_io_12 = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_13:\n\t\tadapter->pinmux_info.sw_io_13 = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_14:\n\t\tadapter->pinmux_info.sw_io_14 = val;\n\t\tbreak;\n\tcase HALMAC_GPIO_FUNC_SW_IO_15:\n\t\tadapter->pinmux_info.sw_io_15 = val;\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_GET_PINMUX_ERR;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n#endif /* HALMAC_88XX_SUPPORT */\n\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_gpio_88xx.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_GPIO_88XX_H_\n#define _HALMAC_GPIO_88XX_H_\n\n#include \"../halmac_api.h\"\n#include \"../halmac_gpio_cmd.h\"\n\n#if HALMAC_88XX_SUPPORT\n\nenum halmac_ret_status\npinmux_wl_led_mode_88xx(struct halmac_adapter *adapter,\n\t\t\tenum halmac_wlled_mode mode);\n\nvoid\npinmux_wl_led_sw_ctrl_88xx(struct halmac_adapter *adapter, u8 on);\n\nvoid\npinmux_sdio_int_polarity_88xx(struct halmac_adapter *adapter, u8 low_active);\n\nenum halmac_ret_status\npinmux_gpio_mode_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 output);\n\nenum halmac_ret_status\npinmux_gpio_output_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 high);\n\nenum halmac_ret_status\npinmux_pin_status_88xx(struct halmac_adapter *adapter, u8 pin_id, u8 *high);\n\nenum halmac_ret_status\npinmux_parser_88xx(struct halmac_adapter *adapter,\n\t\t   const struct halmac_gpio_pimux_list *list, u32 size,\n\t\t   u32 gpio_id, u32 *cur_func);\n\nenum halmac_ret_status\npinmux_switch_88xx(struct halmac_adapter *adapter,\n\t\t   const struct halmac_gpio_pimux_list *list, u32 size,\n\t\t   u32 gpio_id, enum halmac_gpio_func gpio_func);\n\nenum halmac_ret_status\npinmux_record_88xx(struct halmac_adapter *adapter,\n\t\t   enum halmac_gpio_func gpio_func, u8 val);\n\n#endif /* HALMAC_88XX_SUPPORT */\n\n#endif/* _HALMAC_GPIO_88XX_H_ */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_init_88xx.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"halmac_init_88xx.h\"\n#include \"halmac_88xx_cfg.h\"\n#include \"halmac_fw_88xx.h\"\n#include \"halmac_common_88xx.h\"\n#include \"halmac_cfg_wmac_88xx.h\"\n#include \"halmac_efuse_88xx.h\"\n#include \"halmac_mimo_88xx.h\"\n#include \"halmac_bb_rf_88xx.h\"\n#if HALMAC_SDIO_SUPPORT\n#include \"halmac_sdio_88xx.h\"\n#endif\n#if HALMAC_USB_SUPPORT\n#include \"halmac_usb_88xx.h\"\n#endif\n#if HALMAC_PCIE_SUPPORT\n#include \"halmac_pcie_88xx.h\"\n#endif\n#include \"halmac_gpio_88xx.h\"\n#include \"halmac_flash_88xx.h\"\n\n#if HALMAC_8822B_SUPPORT\n#include \"halmac_8822b/halmac_init_8822b.h\"\n#endif\n\n#if HALMAC_8821C_SUPPORT\n#include \"halmac_8821c/halmac_init_8821c.h\"\n#endif\n\n#if HALMAC_8822C_SUPPORT\n#include \"halmac_8822c/halmac_init_8822c.h\"\n#endif\n\n#if HALMAC_8812F_SUPPORT\n#include \"halmac_8812f/halmac_init_8812f.h\"\n#endif\n\n#if HALMAC_PLATFORM_TESTPROGRAM\n#include \"halmisc_api_88xx.h\"\n#endif\n\n#if HALMAC_88XX_SUPPORT\n\n#define PLTFM_INFO_MALLOC_MAX_SIZE\t16384\n#define PLTFM_INFO_RSVD_PG_SIZE\t\t16384\n#define DLFW_PKT_MAX_SIZE\t\t8192 /* need multiple of 2 */\n\nstatic void\ninit_state_machine_88xx(struct halmac_adapter *adapter);\n\nstatic enum halmac_ret_status\nverify_io_88xx(struct halmac_adapter *adapter);\n\nstatic enum halmac_ret_status\nverify_send_rsvd_page_88xx(struct halmac_adapter *adapter);\n\nvoid\ninit_adapter_param_88xx(struct halmac_adapter *adapter)\n{\n\tadapter->api_registry.rx_exp_en = 1;\n\tadapter->api_registry.la_mode_en = 1;\n\tadapter->api_registry.cfg_drv_rsvd_pg_en = 1;\n\tadapter->api_registry.sdio_cmd53_4byte_en = 1;\n\n\tadapter->efuse_map = (u8 *)NULL;\n\tadapter->efuse_map_valid = 0;\n\tadapter->efuse_end = 0;\n\n\tadapter->dlfw_pkt_size = DLFW_PKT_MAX_SIZE;\n\tadapter->pltfm_info.malloc_size = PLTFM_INFO_MALLOC_MAX_SIZE;\n\tadapter->pltfm_info.rsvd_pg_size = PLTFM_INFO_RSVD_PG_SIZE;\n\n\tadapter->cfg_param_info.buf = NULL;\n\tadapter->cfg_param_info.buf_wptr = NULL;\n\tadapter->cfg_param_info.num = 0;\n\tadapter->cfg_param_info.full_fifo_mode = 0;\n\tadapter->cfg_param_info.buf_size = 0;\n\tadapter->cfg_param_info.avl_buf_size = 0;\n\tadapter->cfg_param_info.offset_accum = 0;\n\tadapter->cfg_param_info.value_accum = 0;\n\n\tadapter->ch_sw_info.buf = NULL;\n\tadapter->ch_sw_info.buf_wptr = NULL;\n\tadapter->ch_sw_info.extra_info_en = 0;\n\tadapter->ch_sw_info.buf_size = 0;\n\tadapter->ch_sw_info.avl_buf_size = 0;\n\tadapter->ch_sw_info.total_size = 0;\n\tadapter->ch_sw_info.ch_num = 0;\n\n\tadapter->drv_info_size = 0;\n\tadapter->tx_desc_transfer = 0;\n\n\tadapter->txff_alloc.tx_fifo_pg_num = 0;\n\tadapter->txff_alloc.acq_pg_num = 0;\n\tadapter->txff_alloc.rsvd_boundary = 0;\n\tadapter->txff_alloc.rsvd_drv_addr = 0;\n\tadapter->txff_alloc.rsvd_h2c_info_addr = 0;\n\tadapter->txff_alloc.rsvd_h2cq_addr = 0;\n\tadapter->txff_alloc.rsvd_cpu_instr_addr = 0;\n\tadapter->txff_alloc.rsvd_fw_txbuf_addr = 0;\n\tadapter->txff_alloc.pub_queue_pg_num = 0;\n\tadapter->txff_alloc.high_queue_pg_num = 0;\n\tadapter->txff_alloc.low_queue_pg_num = 0;\n\tadapter->txff_alloc.normal_queue_pg_num = 0;\n\tadapter->txff_alloc.extra_queue_pg_num = 0;\n\n\tadapter->txff_alloc.la_mode = HALMAC_LA_MODE_DISABLE;\n\tadapter->txff_alloc.rx_fifo_exp_mode =\n\t\t\t\t\tHALMAC_RX_FIFO_EXPANDING_MODE_DISABLE;\n\n\tadapter->hw_cfg_info.chk_security_keyid = 0;\n\tadapter->hw_cfg_info.acq_num = 8;\n\tadapter->hw_cfg_info.page_size = TX_PAGE_SIZE_88XX;\n\tadapter->hw_cfg_info.tx_align_size = TX_ALIGN_SIZE_88XX;\n\tadapter->hw_cfg_info.txdesc_size = TX_DESC_SIZE_88XX;\n\tadapter->hw_cfg_info.rxdesc_size = RX_DESC_SIZE_88XX;\n\tadapter->hw_cfg_info.rx_desc_fifo_size = 0;\n\n\tadapter->sdio_cmd53_4byte = HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE;\n\tadapter->sdio_hw_info.io_hi_speed_flag = 0;\n\tadapter->sdio_hw_info.io_indir_flag = 0;\n\tadapter->sdio_hw_info.spec_ver = HALMAC_SDIO_SPEC_VER_2_00;\n\tadapter->sdio_hw_info.clock_speed = 50;\n\tadapter->sdio_hw_info.block_size = 512;\n\tadapter->sdio_hw_info.tx_seq = 1;\n\tadapter->sdio_fs.macid_map = (u8 *)NULL;\n\n\tadapter->pinmux_info.wl_led = 0;\n\tadapter->pinmux_info.sdio_int = 0;\n\tadapter->pinmux_info.sw_io_0 = 0;\n\tadapter->pinmux_info.sw_io_1 = 0;\n\tadapter->pinmux_info.sw_io_2 = 0;\n\tadapter->pinmux_info.sw_io_3 = 0;\n\tadapter->pinmux_info.sw_io_4 = 0;\n\tadapter->pinmux_info.sw_io_5 = 0;\n\tadapter->pinmux_info.sw_io_6 = 0;\n\tadapter->pinmux_info.sw_io_7 = 0;\n\tadapter->pinmux_info.sw_io_8 = 0;\n\tadapter->pinmux_info.sw_io_9 = 0;\n\tadapter->pinmux_info.sw_io_10 = 0;\n\tadapter->pinmux_info.sw_io_11 = 0;\n\tadapter->pinmux_info.sw_io_12 = 0;\n\tadapter->pinmux_info.sw_io_13 = 0;\n\tadapter->pinmux_info.sw_io_14 = 0;\n\tadapter->pinmux_info.sw_io_15 = 0;\n\n\tadapter->pcie_refautok_en = 1;\n\tadapter->pwr_off_flow_flag = 0;\n\n\tadapter->rx_ignore_info.hdr_chk_mask = 1;\n\tadapter->rx_ignore_info.fcs_chk_mask = 1;\n\tadapter->rx_ignore_info.hdr_chk_en = 0;\n\tadapter->rx_ignore_info.fcs_chk_en = 0;\n\tadapter->rx_ignore_info.cck_rst_en = 0;\n\tadapter->rx_ignore_info.fcs_chk_thr = HALMAC_PSF_FCS_CHK_THR_28;\n\n\tinit_adapter_dynamic_param_88xx(adapter);\n\tinit_state_machine_88xx(adapter);\n}\n\nvoid\ninit_adapter_dynamic_param_88xx(struct halmac_adapter *adapter)\n{\n\tadapter->h2c_info.seq_num = 0;\n\tadapter->h2c_info.buf_fs = 0;\n}\n\nenum halmac_ret_status\nmount_api_88xx(struct halmac_adapter *adapter)\n{\n\tstruct halmac_api *api = NULL;\n\n\tadapter->halmac_api =\n\t\t(struct halmac_api *)PLTFM_MALLOC(sizeof(struct halmac_api));\n\tif (!adapter->halmac_api)\n\t\treturn HALMAC_RET_MALLOC_FAIL;\n\n\tapi = (struct halmac_api *)adapter->halmac_api;\n\n\tapi->halmac_read_efuse = NULL;\n\tapi->halmac_write_efuse = NULL;\n\n\t/* Mount function pointer */\n\tapi->halmac_register_api = register_api_88xx;\n\tapi->halmac_download_firmware = download_firmware_88xx;\n\tapi->halmac_free_download_firmware = free_download_firmware_88xx;\n\tapi->halmac_reset_wifi_fw = reset_wifi_fw_88xx;\n\tapi->halmac_get_fw_version = get_fw_version_88xx;\n\tapi->halmac_cfg_mac_addr = cfg_mac_addr_88xx;\n\tapi->halmac_cfg_bssid = cfg_bssid_88xx;\n\tapi->halmac_cfg_transmitter_addr = cfg_transmitter_addr_88xx;\n\tapi->halmac_cfg_net_type = cfg_net_type_88xx;\n\tapi->halmac_cfg_tsf_rst = cfg_tsf_rst_88xx;\n\tapi->halmac_cfg_bcn_space = cfg_bcn_space_88xx;\n\tapi->halmac_rw_bcn_ctrl = rw_bcn_ctrl_88xx;\n\tapi->halmac_cfg_multicast_addr = cfg_multicast_addr_88xx;\n\tapi->halmac_cfg_operation_mode = cfg_operation_mode_88xx;\n\tapi->halmac_cfg_ch_bw = cfg_ch_bw_88xx;\n\tapi->halmac_cfg_bw = cfg_bw_88xx;\n\tapi->halmac_init_mac_cfg = init_mac_cfg_88xx;\n\tapi->halmac_dump_efuse_map = dump_efuse_map_88xx;\n\tapi->halmac_dump_efuse_map_bt = dump_efuse_map_bt_88xx;\n\tapi->halmac_write_efuse_bt = write_efuse_bt_88xx;\n\tapi->halmac_read_efuse_bt = read_efuse_bt_88xx;\n\tapi->halmac_cfg_efuse_auto_check = cfg_efuse_auto_check_88xx;\n\tapi->halmac_dump_logical_efuse_map = dump_log_efuse_map_88xx;\n\tapi->halmac_pg_efuse_by_map = pg_efuse_by_map_88xx;\n\tapi->halmac_mask_logical_efuse = mask_log_efuse_88xx;\n\tapi->halmac_get_efuse_size = get_efuse_size_88xx;\n\tapi->halmac_get_efuse_available_size = get_efuse_available_size_88xx;\n\tapi->halmac_get_c2h_info = get_c2h_info_88xx;\n\n\tapi->halmac_get_logical_efuse_size = get_log_efuse_size_88xx;\n\n\tapi->halmac_write_logical_efuse = write_log_efuse_88xx;\n\tapi->halmac_read_logical_efuse = read_logical_efuse_88xx;\n\n\tapi->halmac_ofld_func_cfg = ofld_func_cfg_88xx;\n\tapi->halmac_h2c_lb = h2c_lb_88xx;\n\tapi->halmac_debug = mac_debug_88xx;\n\tapi->halmac_cfg_parameter = cfg_parameter_88xx;\n\tapi->halmac_update_datapack = update_datapack_88xx;\n\tapi->halmac_run_datapack = run_datapack_88xx;\n\tapi->halmac_send_bt_coex = send_bt_coex_88xx;\n\tapi->halmac_verify_platform_api = verify_platform_api_88xx;\n\tapi->halmac_update_packet = update_packet_88xx;\n\tapi->halmac_bcn_ie_filter = bcn_ie_filter_88xx;\n\tapi->halmac_cfg_txbf = cfg_txbf_88xx;\n\tapi->halmac_cfg_mumimo = cfg_mumimo_88xx;\n\tapi->halmac_cfg_sounding = cfg_sounding_88xx;\n\tapi->halmac_del_sounding = del_sounding_88xx;\n\tapi->halmac_su_bfer_entry_init = su_bfer_entry_init_88xx;\n\tapi->halmac_su_bfee_entry_init = su_bfee_entry_init_88xx;\n\tapi->halmac_mu_bfer_entry_init = mu_bfer_entry_init_88xx;\n\tapi->halmac_mu_bfee_entry_init = mu_bfee_entry_init_88xx;\n\tapi->halmac_su_bfer_entry_del = su_bfer_entry_del_88xx;\n\tapi->halmac_su_bfee_entry_del = su_bfee_entry_del_88xx;\n\tapi->halmac_mu_bfer_entry_del = mu_bfer_entry_del_88xx;\n\tapi->halmac_mu_bfee_entry_del = mu_bfee_entry_del_88xx;\n\n\tapi->halmac_add_ch_info = add_ch_info_88xx;\n\tapi->halmac_add_extra_ch_info = add_extra_ch_info_88xx;\n\tapi->halmac_ctrl_ch_switch = ctrl_ch_switch_88xx;\n\tapi->halmac_p2pps = p2pps_88xx;\n\tapi->halmac_clear_ch_info = clear_ch_info_88xx;\n\tapi->halmac_send_general_info = send_general_info_88xx;\n\n\tapi->halmac_start_iqk = start_iqk_88xx;\n\tapi->halmac_ctrl_pwr_tracking = ctrl_pwr_tracking_88xx;\n\tapi->halmac_psd = psd_88xx;\n\tapi->halmac_cfg_la_mode = cfg_la_mode_88xx;\n\tapi->halmac_cfg_rxff_expand_mode = cfg_rxfifo_expand_mode_88xx;\n\n\tapi->halmac_config_security = config_security_88xx;\n\tapi->halmac_get_used_cam_entry_num = get_used_cam_entry_num_88xx;\n\tapi->halmac_read_cam_entry = read_cam_entry_88xx;\n\tapi->halmac_write_cam = write_cam_88xx;\n\tapi->halmac_clear_cam_entry = clear_cam_entry_88xx;\n\n\tapi->halmac_cfg_drv_rsvd_pg_num = cfg_drv_rsvd_pg_num_88xx;\n\tapi->halmac_get_chip_version = get_version_88xx;\n\n\tapi->halmac_query_status = query_status_88xx;\n\tapi->halmac_reset_feature = reset_ofld_feature_88xx;\n\tapi->halmac_check_fw_status = check_fw_status_88xx;\n\tapi->halmac_dump_fw_dmem = dump_fw_dmem_88xx;\n\tapi->halmac_cfg_max_dl_size = cfg_max_dl_size_88xx;\n\n\tapi->halmac_dump_fifo = dump_fifo_88xx;\n\tapi->halmac_get_fifo_size = get_fifo_size_88xx;\n\n\tapi->halmac_chk_txdesc = chk_txdesc_88xx;\n\tapi->halmac_dl_drv_rsvd_page = dl_drv_rsvd_page_88xx;\n\tapi->halmac_cfg_csi_rate = cfg_csi_rate_88xx;\n\n\tapi->halmac_txfifo_is_empty = txfifo_is_empty_88xx;\n\tapi->halmac_download_flash = download_flash_88xx;\n\tapi->halmac_read_flash = read_flash_88xx;\n\tapi->halmac_erase_flash = erase_flash_88xx;\n\tapi->halmac_check_flash = check_flash_88xx;\n\tapi->halmac_cfg_edca_para = cfg_edca_para_88xx;\n\tapi->halmac_pinmux_wl_led_mode = pinmux_wl_led_mode_88xx;\n\tapi->halmac_pinmux_wl_led_sw_ctrl = pinmux_wl_led_sw_ctrl_88xx;\n\tapi->halmac_pinmux_sdio_int_polarity = pinmux_sdio_int_polarity_88xx;\n\tapi->halmac_pinmux_gpio_mode = pinmux_gpio_mode_88xx;\n\tapi->halmac_pinmux_gpio_output = pinmux_gpio_output_88xx;\n\tapi->halmac_pinmux_pin_status = pinmux_pin_status_88xx;\n\n\tapi->halmac_rx_cut_amsdu_cfg = rx_cut_amsdu_cfg_88xx;\n\tapi->halmac_fw_snding = fw_snding_88xx;\n\tapi->halmac_get_mac_addr = get_mac_addr_88xx;\n\n\tapi->halmac_enter_cpu_sleep_mode = enter_cpu_sleep_mode_88xx;\n\tapi->halmac_get_cpu_mode = get_cpu_mode_88xx;\n\tapi->halmac_drv_fwctrl = drv_fwctrl_88xx;\n\n\tif (adapter->intf == HALMAC_INTERFACE_SDIO) {\n#if HALMAC_SDIO_SUPPORT\n\t\tapi->halmac_init_sdio_cfg = init_sdio_cfg_88xx;\n\t\tapi->halmac_deinit_sdio_cfg = deinit_sdio_cfg_88xx;\n\t\tapi->halmac_cfg_rx_aggregation = cfg_sdio_rx_agg_88xx;\n\t\tapi->halmac_init_interface_cfg = init_sdio_cfg_88xx;\n\t\tapi->halmac_deinit_interface_cfg = deinit_sdio_cfg_88xx;\n\t\tapi->halmac_cfg_tx_agg_align = cfg_txagg_sdio_align_88xx;\n\t\tapi->halmac_set_bulkout_num = set_sdio_bulkout_num_88xx;\n\t\tapi->halmac_get_usb_bulkout_id = get_sdio_bulkout_id_88xx;\n\t\tapi->halmac_reg_read_indirect_32 = sdio_indirect_reg_r32_88xx;\n\t\tapi->halmac_reg_sdio_cmd53_read_n = sdio_reg_rn_88xx;\n\t\tapi->halmac_sdio_cmd53_4byte = sdio_cmd53_4byte_88xx;\n\t\tapi->halmac_sdio_hw_info = sdio_hw_info_88xx;\n\n#endif\n\t} else if (adapter->intf == HALMAC_INTERFACE_USB) {\n#if HALMAC_USB_SUPPORT\n\t\tapi->halmac_init_usb_cfg = init_usb_cfg_88xx;\n\t\tapi->halmac_deinit_usb_cfg = deinit_usb_cfg_88xx;\n\t\tapi->halmac_cfg_rx_aggregation = cfg_usb_rx_agg_88xx;\n\t\tapi->halmac_init_interface_cfg = init_usb_cfg_88xx;\n\t\tapi->halmac_deinit_interface_cfg = deinit_usb_cfg_88xx;\n\t\tapi->halmac_cfg_tx_agg_align = cfg_txagg_usb_align_88xx;\n\t\tapi->halmac_tx_allowed_sdio = tx_allowed_usb_88xx;\n\t\tapi->halmac_set_bulkout_num = set_usb_bulkout_num_88xx;\n\t\tapi->halmac_get_sdio_tx_addr = get_usb_tx_addr_88xx;\n\t\tapi->halmac_get_usb_bulkout_id = get_usb_bulkout_id_88xx;\n\t\tapi->halmac_reg_read_8 = reg_r8_usb_88xx;\n\t\tapi->halmac_reg_write_8 = reg_w8_usb_88xx;\n\t\tapi->halmac_reg_read_16 = reg_r16_usb_88xx;\n\t\tapi->halmac_reg_write_16 = reg_w16_usb_88xx;\n\t\tapi->halmac_reg_read_32 = reg_r32_usb_88xx;\n\t\tapi->halmac_reg_write_32 = reg_w32_usb_88xx;\n\t\tapi->halmac_reg_read_indirect_32 = usb_indirect_reg_r32_88xx;\n\t\tapi->halmac_reg_sdio_cmd53_read_n = usb_reg_rn_88xx;\n#endif\n\t} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {\n#if HALMAC_PCIE_SUPPORT\n\t\tapi->halmac_init_pcie_cfg = init_pcie_cfg_88xx;\n\t\tapi->halmac_deinit_pcie_cfg = deinit_pcie_cfg_88xx;\n\t\tapi->halmac_cfg_rx_aggregation = cfg_pcie_rx_agg_88xx;\n\t\tapi->halmac_init_interface_cfg = init_pcie_cfg_88xx;\n\t\tapi->halmac_deinit_interface_cfg = deinit_pcie_cfg_88xx;\n\t\tapi->halmac_cfg_tx_agg_align = cfg_txagg_pcie_align_88xx;\n\t\tapi->halmac_tx_allowed_sdio = tx_allowed_pcie_88xx;\n\t\tapi->halmac_set_bulkout_num = set_pcie_bulkout_num_88xx;\n\t\tapi->halmac_get_sdio_tx_addr = get_pcie_tx_addr_88xx;\n\t\tapi->halmac_get_usb_bulkout_id = get_pcie_bulkout_id_88xx;\n\t\tapi->halmac_reg_read_8 = reg_r8_pcie_88xx;\n\t\tapi->halmac_reg_write_8 = reg_w8_pcie_88xx;\n\t\tapi->halmac_reg_read_16 = reg_r16_pcie_88xx;\n\t\tapi->halmac_reg_write_16 = reg_w16_pcie_88xx;\n\t\tapi->halmac_reg_read_32 = reg_r32_pcie_88xx;\n\t\tapi->halmac_reg_write_32 = reg_w32_pcie_88xx;\n\t\tapi->halmac_reg_read_indirect_32 = pcie_indirect_reg_r32_88xx;\n\t\tapi->halmac_reg_sdio_cmd53_read_n = pcie_reg_rn_88xx;\n\t\tapi->halmac_en_ref_autok_pcie = en_ref_autok_88xx;\n#endif\n\t} else {\n\t\tPLTFM_MSG_ERR(\"[ERR]Set halmac io function Error!!\\n\");\n\t}\n\n\tif (adapter->chip_id == HALMAC_CHIP_ID_8822B) {\n#if HALMAC_8822B_SUPPORT\n\t\tmount_api_8822b(adapter);\n#endif\n\t} else if (adapter->chip_id == HALMAC_CHIP_ID_8821C) {\n#if HALMAC_8821C_SUPPORT\n\t\tmount_api_8821c(adapter);\n#endif\n\t} else if (adapter->chip_id == HALMAC_CHIP_ID_8822C) {\n#if HALMAC_8822C_SUPPORT\n\t\tmount_api_8822c(adapter);\n#endif\n\t} else if (adapter->chip_id == HALMAC_CHIP_ID_8812F) {\n#if HALMAC_8812F_SUPPORT\n\t\tmount_api_8812f(adapter);\n#endif\n\t} else {\n\t\tPLTFM_MSG_ERR(\"[ERR]Chip ID undefine!!\\n\");\n\t\treturn HALMAC_RET_CHIP_NOT_SUPPORT;\n\t}\n\n#if HALMAC_PLATFORM_TESTPROGRAM\n\thalmac_mount_misc_api_88xx(adapter);\n#endif\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic void\ninit_state_machine_88xx(struct halmac_adapter *adapter)\n{\n\tstruct halmac_state *state = &adapter->halmac_state;\n\n\tinit_ofld_feature_state_machine_88xx(adapter);\n\n\tstate->api_state = HALMAC_API_STATE_INIT;\n\n\tstate->dlfw_state = HALMAC_DLFW_NONE;\n\tstate->mac_pwr = HALMAC_MAC_POWER_OFF;\n\tstate->gpio_cfg_state = HALMAC_GPIO_CFG_STATE_IDLE;\n\tstate->rsvd_pg_state = HALMAC_RSVD_PG_STATE_IDLE;\n}\n\nvoid\ninit_ofld_feature_state_machine_88xx(struct halmac_adapter *adapter)\n{\n\tstruct halmac_state *state = &adapter->halmac_state;\n\n\tstate->efuse_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;\n\tstate->efuse_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\tstate->efuse_state.seq_num = adapter->h2c_info.seq_num;\n\n\tstate->cfg_param_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;\n\tstate->cfg_param_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\tstate->cfg_param_state.seq_num = adapter->h2c_info.seq_num;\n\n\tstate->scan_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;\n\tstate->scan_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\tstate->scan_state.seq_num = adapter->h2c_info.seq_num;\n\n\tstate->update_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\tstate->update_pkt_state.seq_num = adapter->h2c_info.seq_num;\n\n\tstate->iqk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\tstate->iqk_state.seq_num = adapter->h2c_info.seq_num;\n\n\tstate->pwr_trk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\tstate->pwr_trk_state.seq_num = adapter->h2c_info.seq_num;\n\n\tstate->psd_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\tstate->psd_state.seq_num = adapter->h2c_info.seq_num;\n\tstate->psd_state.data_size = 0;\n\tstate->psd_state.seg_size = 0;\n\tstate->psd_state.data = NULL;\n\n\tstate->fw_snding_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;\n\tstate->fw_snding_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\tstate->fw_snding_state.seq_num = adapter->h2c_info.seq_num;\n\n\tstate->wlcpu_mode = HALMAC_WLCPU_ACTIVE;\n}\n\n/**\n * register_api_88xx() - register feature list\n * @adapter\n * @registry : feature list, 1->enable 0->disable\n * Author : Ivan Lin\n *\n * Default is enable all api registry\n *\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nregister_api_88xx(struct halmac_adapter *adapter,\n\t\t  struct halmac_api_registry *registry)\n{\n\tif (!registry)\n\t\treturn HALMAC_RET_NULL_POINTER;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tPLTFM_MEMCPY(&adapter->api_registry, registry, sizeof(*registry));\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * init_mac_cfg_88xx() - config page1~page7 register\n * @adapter : the adapter of halmac\n * @mode : trx mode\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ninit_mac_cfg_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tstatus = api->halmac_init_trx_cfg(adapter, mode);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]init trx %x\\n\", status);\n\t\treturn status;\n\t}\n\n\tstatus = api->halmac_init_protocol_cfg(adapter);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]init ptcl %x\\n\", status);\n\t\treturn status;\n\t}\n\n\tstatus = api->halmac_init_edca_cfg(adapter);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]init edca %x\\n\", status);\n\t\treturn status;\n\t}\n\n\tstatus = api->halmac_init_wmac_cfg(adapter);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]init wmac %x\\n\", status);\n\t\treturn status;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn status;\n}\n\n/**\n * reset_ofld_feature_88xx() -reset async api cmd status\n * @adapter : the adapter of halmac\n * @feature_id : feature_id\n * Author : Ivan Lin/KaiYuan Chang\n * Return : enum halmac_ret_status.\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nreset_ofld_feature_88xx(struct halmac_adapter *adapter,\n\t\t\tenum halmac_feature_id feature_id)\n{\n\tstruct halmac_state *state = &adapter->halmac_state;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tswitch (feature_id) {\n\tcase HALMAC_FEATURE_CFG_PARA:\n\t\tstate->cfg_param_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\t\tstate->cfg_param_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;\n\t\tbreak;\n\tcase HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:\n\tcase HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:\n\t\tstate->efuse_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\t\tstate->efuse_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;\n\t\tbreak;\n\tcase HALMAC_FEATURE_CHANNEL_SWITCH:\n\t\tstate->scan_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\t\tstate->scan_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;\n\t\tbreak;\n\tcase HALMAC_FEATURE_UPDATE_PACKET:\n\t\tstate->update_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\t\tbreak;\n\tcase HALMAC_FEATURE_IQK:\n\t\tstate->iqk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\t\tbreak;\n\tcase HALMAC_FEATURE_POWER_TRACKING:\n\t\tstate->pwr_trk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\t\tbreak;\n\tcase HALMAC_FEATURE_PSD:\n\t\tstate->psd_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\t\tbreak;\n\tcase HALMAC_FEATURE_FW_SNDING:\n\t\tstate->fw_snding_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\t\tstate->fw_snding_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;\n\t\tbreak;\n\tcase HALMAC_FEATURE_ALL:\n\t\tstate->cfg_param_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\t\tstate->cfg_param_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;\n\t\tstate->efuse_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\t\tstate->efuse_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;\n\t\tstate->scan_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\t\tstate->scan_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;\n\t\tstate->update_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\t\tstate->iqk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\t\tstate->pwr_trk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\t\tstate->psd_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\t\tstate->fw_snding_state.proc_status = HALMAC_CMD_PROCESS_IDLE;\n\t\tstate->fw_snding_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;\n\t\tbreak;\n\tdefault:\n\t\tPLTFM_MSG_ERR(\"[ERR]invalid feature id\\n\");\n\t\treturn HALMAC_RET_INVALID_FEATURE_ID;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * (debug API)verify_platform_api_88xx() - verify platform api\n * @adapter : the adapter of halmac\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nverify_platform_api_88xx(struct halmac_adapter *adapter)\n{\n\tenum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tret_status = verify_io_88xx(adapter);\n\n\tif (ret_status != HALMAC_RET_SUCCESS)\n\t\treturn ret_status;\n\n\tif (adapter->txff_alloc.la_mode != HALMAC_LA_MODE_FULL)\n\t\tret_status = verify_send_rsvd_page_88xx(adapter);\n\n\tif (ret_status != HALMAC_RET_SUCCESS)\n\t\treturn ret_status;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn ret_status;\n}\n\nvoid\ntx_desc_chksum_88xx(struct halmac_adapter *adapter, u8 enable)\n{\n\tu16 value16;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tadapter->tx_desc_checksum = enable;\n\n\tvalue16 = HALMAC_REG_R16(REG_TXDMA_OFFSET_CHK);\n\tif (enable == 1)\n\t\tHALMAC_REG_W16(REG_TXDMA_OFFSET_CHK, value16 | BIT(13));\n\telse\n\t\tHALMAC_REG_W16(REG_TXDMA_OFFSET_CHK, value16 & ~BIT(13));\n}\n\nstatic enum halmac_ret_status\nverify_io_88xx(struct halmac_adapter *adapter)\n{\n\tu8 value8;\n\tu8 wvalue8;\n\tu32 value32;\n\tu32 value32_2;\n\tu32 wvalue32;\n\tu32 offset;\n\tenum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;\n\n\tif (adapter->intf == HALMAC_INTERFACE_SDIO) {\n\t\toffset = REG_PAGE5_DUMMY;\n\t\tif (0 == (offset & 0xFFFF0000))\n\t\t\toffset |= WLAN_IOREG_OFFSET;\n#if HALMAC_SDIO_SUPPORT\n\t\tret_status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);\n#else\n\t\treturn HALMAC_RET_WRONG_INTF;\n#endif\n\t\t/* Verify CMD52 R/W */\n\t\twvalue8 = 0xab;\n\t\tPLTFM_SDIO_CMD52_W(offset, wvalue8);\n\n\t\tvalue8 = PLTFM_SDIO_CMD52_R(offset);\n\n\t\tif (value8 != wvalue8) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]cmd52 r/w\\n\");\n\t\t\tret_status = HALMAC_RET_PLATFORM_API_INCORRECT;\n\t\t}\n\n\t\t/* Verify CMD53 R/W */\n\t\tPLTFM_SDIO_CMD52_W(offset, 0xaa);\n\t\tPLTFM_SDIO_CMD52_W(offset + 1, 0xbb);\n\t\tPLTFM_SDIO_CMD52_W(offset + 2, 0xcc);\n\t\tPLTFM_SDIO_CMD52_W(offset + 3, 0xdd);\n\n\t\tvalue32 = PLTFM_SDIO_CMD53_R32(offset);\n\n\t\tif (value32 != 0xddccbbaa) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]cmd53 r\\n\");\n\t\t\tret_status = HALMAC_RET_PLATFORM_API_INCORRECT;\n\t\t}\n\n\t\twvalue32 = 0x11223344;\n\t\tPLTFM_SDIO_CMD53_W32(offset, wvalue32);\n\n\t\tvalue32 = PLTFM_SDIO_CMD53_R32(offset);\n\n\t\tif (value32 != wvalue32) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]cmd53 w\\n\");\n\t\t\tret_status = HALMAC_RET_PLATFORM_API_INCORRECT;\n\t\t}\n\n\t\t/* value32 should be 0x33441122 */\n\t\tvalue32 = PLTFM_SDIO_CMD53_R32(offset + 2);\n\n\t\twvalue32 = 0x11225566;\n\t\tPLTFM_SDIO_CMD53_W32(offset, wvalue32);\n\n\t\t/* value32 should be 0x55661122 */\n\t\tvalue32_2 = PLTFM_SDIO_CMD53_R32(offset + 2);\n\t\tif (value32_2 == value32) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]cmd52 is used\\n\");\n\t\t\tret_status = HALMAC_RET_PLATFORM_API_INCORRECT;\n\t\t}\n\t} else {\n\t\twvalue32 = 0x77665511;\n\t\tPLTFM_REG_W32(REG_PAGE5_DUMMY, wvalue32);\n\n\t\tvalue32 = PLTFM_REG_R32(REG_PAGE5_DUMMY);\n\t\tif (value32 != wvalue32) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]reg rw\\n\");\n\t\t\tret_status = HALMAC_RET_PLATFORM_API_INCORRECT;\n\t\t}\n\t}\n\n\treturn ret_status;\n}\n\nstatic enum halmac_ret_status\nverify_send_rsvd_page_88xx(struct halmac_adapter *adapter)\n{\n\tu8 txdesc_size = adapter->hw_cfg_info.txdesc_size;\n\tu8 *rsvd_buf = NULL;\n\tu8 *rsvd_page = NULL;\n\tu32 i;\n\tu32 pkt_size = 64;\n\tu32 payload = 0xab;\n\tenum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;\n\n\trsvd_buf = (u8 *)PLTFM_MALLOC(pkt_size);\n\n\tif (!rsvd_buf) {\n\t\tPLTFM_MSG_ERR(\"[ERR]rsvd buf malloc!!\\n\");\n\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t}\n\n\tPLTFM_MEMSET(rsvd_buf, (u8)payload, pkt_size);\n\n\tret_status = dl_rsvd_page_88xx(adapter,\n\t\t\t\t       adapter->txff_alloc.rsvd_boundary,\n\t\t\t\t       rsvd_buf, pkt_size);\n\tif (ret_status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_FREE(rsvd_buf, pkt_size);\n\t\treturn ret_status;\n\t}\n\n\trsvd_page = (u8 *)PLTFM_MALLOC(pkt_size + txdesc_size);\n\n\tif (!rsvd_page) {\n\t\tPLTFM_MSG_ERR(\"[ERR]rsvd page malloc!!\\n\");\n\t\tPLTFM_FREE(rsvd_buf, pkt_size);\n\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t}\n\n\tPLTFM_MEMSET(rsvd_page, 0x00, pkt_size + txdesc_size);\n\n\tret_status = dump_fifo_88xx(adapter, HAL_FIFO_SEL_RSVD_PAGE, 0,\n\t\t\t\t    pkt_size + txdesc_size, rsvd_page);\n\n\tif (ret_status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_FREE(rsvd_buf, pkt_size);\n\t\tPLTFM_FREE(rsvd_page, pkt_size + txdesc_size);\n\t\treturn ret_status;\n\t}\n\n\tfor (i = 0; i < pkt_size; i++) {\n\t\tif (*(rsvd_buf + i) != *(rsvd_page + (i + txdesc_size))) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]Compare RSVD page Fail\\n\");\n\t\t\tret_status = HALMAC_RET_PLATFORM_API_INCORRECT;\n\t\t}\n\t}\n\n\tPLTFM_FREE(rsvd_buf, pkt_size);\n\tPLTFM_FREE(rsvd_page, pkt_size + txdesc_size);\n\n\treturn ret_status;\n}\n\nenum halmac_ret_status\npg_num_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,\n\t\t   struct halmac_pg_num *tbl)\n{\n\tu8 flag;\n\tu16 hpq_num = 0;\n\tu16 lpq_num = 0;\n\tu16 npq_num = 0;\n\tu16 gapq_num = 0;\n\tu16 expq_num = 0;\n\tu16 pubq_num = 0;\n\tu32 i = 0;\n\n\tflag = 0;\n\tfor (i = 0; i < HALMAC_TRX_MODE_MAX; i++) {\n\t\tif (mode == tbl[i].mode) {\n\t\t\thpq_num = tbl[i].hq_num;\n\t\t\tlpq_num = tbl[i].lq_num;\n\t\t\tnpq_num = tbl[i].nq_num;\n\t\t\texpq_num = tbl[i].exq_num;\n\t\t\tgapq_num = tbl[i].gap_num;\n\t\t\tpubq_num = adapter->txff_alloc.acq_pg_num - hpq_num -\n\t\t\t\t\tlpq_num - npq_num - expq_num - gapq_num;\n\t\t\tflag = 1;\n\t\t\tPLTFM_MSG_TRACE(\"[TRACE]%s done\\n\", __func__);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (flag == 0) {\n\t\tPLTFM_MSG_ERR(\"[ERR]trx mode!!\\n\");\n\t\treturn HALMAC_RET_TRX_MODE_NOT_SUPPORT;\n\t}\n\n\tif (adapter->txff_alloc.acq_pg_num <\n\t    hpq_num + lpq_num + npq_num + expq_num + gapq_num) {\n\t\tPLTFM_MSG_ERR(\"[ERR]acqnum = %d\\n\",\n\t\t\t      adapter->txff_alloc.acq_pg_num);\n\t\tPLTFM_MSG_ERR(\"[ERR]hpq_num = %d\\n\", hpq_num);\n\t\tPLTFM_MSG_ERR(\"[ERR]LPQ_num = %d\\n\", lpq_num);\n\t\tPLTFM_MSG_ERR(\"[ERR]npq_num = %d\\n\", npq_num);\n\t\tPLTFM_MSG_ERR(\"[ERR]EPQ_num = %d\\n\", expq_num);\n\t\tPLTFM_MSG_ERR(\"[ERR]gapq_num = %d\\n\", gapq_num);\n\t\treturn HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;\n\t}\n\n\tadapter->txff_alloc.high_queue_pg_num = hpq_num;\n\tadapter->txff_alloc.low_queue_pg_num = lpq_num;\n\tadapter->txff_alloc.normal_queue_pg_num = npq_num;\n\tadapter->txff_alloc.extra_queue_pg_num = expq_num;\n\tadapter->txff_alloc.pub_queue_pg_num = pubq_num;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nrqpn_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,\n\t\t struct halmac_rqpn *tbl)\n{\n\tu8 flag;\n\tu32 i;\n\n\tflag = 0;\n\tfor (i = 0; i < HALMAC_TRX_MODE_MAX; i++) {\n\t\tif (mode == tbl[i].mode) {\n\t\t\tadapter->pq_map[HALMAC_PQ_MAP_VO] = tbl[i].dma_map_vo;\n\t\t\tadapter->pq_map[HALMAC_PQ_MAP_VI] = tbl[i].dma_map_vi;\n\t\t\tadapter->pq_map[HALMAC_PQ_MAP_BE] = tbl[i].dma_map_be;\n\t\t\tadapter->pq_map[HALMAC_PQ_MAP_BK] = tbl[i].dma_map_bk;\n\t\t\tadapter->pq_map[HALMAC_PQ_MAP_MG] = tbl[i].dma_map_mg;\n\t\t\tadapter->pq_map[HALMAC_PQ_MAP_HI] = tbl[i].dma_map_hi;\n\t\t\tflag = 1;\n\t\t\tPLTFM_MSG_TRACE(\"[TRACE]%s done\\n\", __func__);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (flag == 0) {\n\t\tPLTFM_MSG_ERR(\"[ERR]trx mdoe!!\\n\");\n\t\treturn HALMAC_RET_TRX_MODE_NOT_SUPPORT;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nfwff_is_empty_88xx(struct halmac_adapter *adapter)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tu32 cnt;\n\n\tcnt = 5000;\n\twhile (HALMAC_REG_R16(REG_FWFF_CTRL) !=\n\t\tHALMAC_REG_R16(REG_FWFF_PKT_INFO)) {\n\t\tif (cnt == 0) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]polling fwff empty fail\\n\");\n\t\t\treturn HALMAC_RET_FWFF_NO_EMPTY;\n\t\t}\n\t\tcnt--;\n\t\tPLTFM_DELAY_US(50);\n\t}\n\treturn HALMAC_RET_SUCCESS;\n}\n\n#endif /* HALMAC_88XX_SUPPORT */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_init_88xx.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_INIT_88XX_H_\n#define _HALMAC_INIT_88XX_H_\n\n#include \"../halmac_api.h\"\n\n#if HALMAC_88XX_SUPPORT\n\nenum halmac_ret_status\nregister_api_88xx(struct halmac_adapter *adapter,\n\t\t  struct halmac_api_registry *registry);\n\nvoid\ninit_adapter_param_88xx(struct halmac_adapter *adapter);\n\nvoid\ninit_adapter_dynamic_param_88xx(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\nmount_api_88xx(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\ninit_mac_cfg_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode);\n\nenum halmac_ret_status\nreset_ofld_feature_88xx(struct halmac_adapter *adapter,\n\t\t\tenum halmac_feature_id feature_id);\n\nenum halmac_ret_status\nverify_platform_api_88xx(struct halmac_adapter *adapter);\n\nvoid\ntx_desc_chksum_88xx(struct halmac_adapter *adapter, u8 enable);\n\nenum halmac_ret_status\npg_num_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,\n\t\t   struct halmac_pg_num *tbl);\n\nenum halmac_ret_status\nrqpn_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,\n\t\t struct halmac_rqpn *tbl);\n\nvoid\ninit_ofld_feature_state_machine_88xx(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\nfwff_is_empty_88xx(struct halmac_adapter *adapter);\n\n#endif /* HALMAC_88XX_SUPPORT */\n\n#endif/* _HALMAC_INIT_88XX_H_ */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_mimo_88xx.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"halmac_mimo_88xx.h\"\n#include \"halmac_88xx_cfg.h\"\n#include \"halmac_common_88xx.h\"\n#include \"halmac_init_88xx.h\"\n\n#if HALMAC_88XX_SUPPORT\n\n#define TXBF_CTRL_CFG\t(BIT_R_ENABLE_NDPA | BIT_USE_NDPA_PARAMETER | \\\n\t\t\t BIT_R_EN_NDPA_INT | BIT_DIS_NDP_BFEN)\n#define CSI_RATE_MAP\t0x55\n\nstatic void\ncfg_mu_bfee_88xx(struct halmac_adapter *adapter,\n\t\t struct halmac_cfg_mumimo_para *param);\n\nstatic void\ncfg_mu_bfer_88xx(struct halmac_adapter *adapter,\n\t\t struct halmac_cfg_mumimo_para *param);\n\nstatic enum halmac_cmd_construct_state\nfw_snding_cmd_cnstr_state_88xx(struct halmac_adapter *adapter);\n\nstatic enum halmac_ret_status\ncnv_fw_snding_state_88xx(struct halmac_adapter *adapter,\n\t\t\t enum halmac_cmd_construct_state dest_state);\n\nstatic u8\nsnding_pkt_chk_88xx(struct halmac_adapter *adapter, u8 *pkt);\n\n/**\n * cfg_txbf_88xx() - enable/disable specific user's txbf\n * @adapter : the adapter of halmac\n * @userid : su bfee userid = 0 or 1 to apply TXBF\n * @bw : the sounding bandwidth\n * @txbf_en : 0: disable TXBF, 1: enable TXBF\n * Author : chunchu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_txbf_88xx(struct halmac_adapter *adapter, u8 userid, enum halmac_bw bw,\n\t      u8 txbf_en)\n{\n\tu16 tmp42c = 0;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tif (txbf_en) {\n\t\tswitch (bw) {\n\t\tcase HALMAC_BW_80:\n\t\t\ttmp42c |= BIT_R_TXBF0_80M;\n\t\tcase HALMAC_BW_40:\n\t\t\ttmp42c |= BIT_R_TXBF0_40M;\n\t\tcase HALMAC_BW_20:\n\t\t\ttmp42c |= BIT_R_TXBF0_20M;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn HALMAC_RET_INVALID_SOUNDING_SETTING;\n\t\t}\n\t}\n\n\tswitch (userid) {\n\tcase 0:\n\t\ttmp42c |= HALMAC_REG_R16(REG_TXBF_CTRL) &\n\t\t\t~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);\n\t\tHALMAC_REG_W16(REG_TXBF_CTRL, tmp42c);\n\t\tbreak;\n\tcase 1:\n\t\ttmp42c |= HALMAC_REG_R16(REG_TXBF_CTRL + 2) &\n\t\t\t~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);\n\t\tHALMAC_REG_W16(REG_TXBF_CTRL + 2, tmp42c);\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_INVALID_SOUNDING_SETTING;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfg_mumimo_88xx() -config mumimo\n * @adapter : the adapter of halmac\n * @param : parameters to configure MU PPDU Tx/Rx\n * Author : chunchu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_mumimo_88xx(struct halmac_adapter *adapter,\n\t\tstruct halmac_cfg_mumimo_para *param)\n{\n\tif (param->role == HAL_BFEE)\n\t\tcfg_mu_bfee_88xx(adapter, param);\n\telse\n\t\tcfg_mu_bfer_88xx(adapter, param);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic void\ncfg_mu_bfee_88xx(struct halmac_adapter *adapter,\n\t\t struct halmac_cfg_mumimo_para *param)\n{\n\tu8 mu_tbl_sel;\n\tu8 tmp14c0;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\ttmp14c0 = HALMAC_REG_R8(REG_MU_TX_CTL) & ~BIT_MASK_R_MU_TABLE_VALID;\n\tHALMAC_REG_W8(REG_MU_TX_CTL, (tmp14c0 | BIT(0) | BIT(1)) & ~(BIT(7)));\n\n\t/*config GID valid table and user position table*/\n\tmu_tbl_sel = HALMAC_REG_R8(REG_MU_TX_CTL + 1) & 0xF8;\n\n\tHALMAC_REG_W8(REG_MU_TX_CTL + 1, mu_tbl_sel);\n\tHALMAC_REG_W32(REG_MU_STA_GID_VLD, param->given_gid_tab[0]);\n\tHALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->given_user_pos[0]);\n\tHALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->given_user_pos[1]);\n\n\tHALMAC_REG_W8(REG_MU_TX_CTL + 1, mu_tbl_sel | 1);\n\tHALMAC_REG_W32(REG_MU_STA_GID_VLD, param->given_gid_tab[1]);\n\tHALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->given_user_pos[2]);\n\tHALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->given_user_pos[3]);\n}\n\nstatic void\ncfg_mu_bfer_88xx(struct halmac_adapter *adapter,\n\t\t struct halmac_cfg_mumimo_para *param)\n{\n\tu8 i;\n\tu8 idx;\n\tu8 id0;\n\tu8 id1;\n\tu8 gid;\n\tu8 mu_tbl_sel;\n\tu8 mu_tbl_valid = 0;\n\tu32 gid_valid[6] = {0};\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tif (param->mu_tx_en == 0) {\n\t\tHALMAC_REG_W8(REG_MU_TX_CTL,\n\t\t\t      HALMAC_REG_R8(REG_MU_TX_CTL) & ~(BIT(7)));\n\t\treturn;\n\t}\n\n\tfor (idx = 0; idx < 15; idx++) {\n\t\tif (idx < 5) {\n\t\t\t/*grouping_bitmap bit0~4, MU_STA0 with MUSTA1~5*/\n\t\t\tid0 = 0;\n\t\t\tid1 = (u8)(idx + 1);\n\t\t} else if (idx < 9) {\n\t\t\t/*grouping_bitmap bit5~8, MU_STA1 with MUSTA2~5*/\n\t\t\tid0 = 1;\n\t\t\tid1 = (u8)(idx - 3);\n\t\t} else if (idx < 12) {\n\t\t\t/*grouping_bitmap bit9~11, MU_STA2 with MUSTA3~5*/\n\t\t\tid0 = 2;\n\t\t\tid1 = (u8)(idx - 6);\n\t\t} else if (idx < 14) {\n\t\t\t/*grouping_bitmap bit12~13, MU_STA3 with MUSTA4~5*/\n\t\t\tid0 = 3;\n\t\t\tid1 = (u8)(idx - 8);\n\t\t} else {\n\t\t\t/*grouping_bitmap bit14, MU_STA4 with MUSTA5*/\n\t\t\tid0 = 4;\n\t\t\tid1 = (u8)(idx - 9);\n\t\t}\n\t\tif (param->grouping_bitmap & BIT(idx)) {\n\t\t\t/*Pair 1*/\n\t\t\tgid = (idx << 1) + 1;\n\t\t\tgid_valid[id0] |= (BIT(gid));\n\t\t\tgid_valid[id1] |= (BIT(gid));\n\t\t\t/*Pair 2*/\n\t\t\tgid += 1;\n\t\t\tgid_valid[id0] |= (BIT(gid));\n\t\t\tgid_valid[id1] |= (BIT(gid));\n\t\t} else {\n\t\t\t/*Pair 1*/\n\t\t\tgid = (idx << 1) + 1;\n\t\t\tgid_valid[id0] &= ~(BIT(gid));\n\t\t\tgid_valid[id1] &= ~(BIT(gid));\n\t\t\t/*Pair 2*/\n\t\t\tgid += 1;\n\t\t\tgid_valid[id0] &= ~(BIT(gid));\n\t\t\tgid_valid[id1] &= ~(BIT(gid));\n\t\t}\n\t}\n\n\t/*set MU STA GID valid TABLE*/\n\tmu_tbl_sel = HALMAC_REG_R8(REG_MU_TX_CTL + 1) & 0xF8;\n\tfor (idx = 0; idx < 6; idx++) {\n\t\tHALMAC_REG_W8(REG_MU_TX_CTL + 1, idx | mu_tbl_sel);\n\t\tHALMAC_REG_W32(REG_MU_STA_GID_VLD, gid_valid[idx]);\n\t}\n\n\t/*To validate the sounding successful MU STA and enable MU TX*/\n\tfor (i = 0; i < 6; i++) {\n\t\tif (param->sounding_sts[i] == 1)\n\t\t\tmu_tbl_valid |= BIT(i);\n\t}\n\tHALMAC_REG_W8(REG_MU_TX_CTL, mu_tbl_valid | BIT(7));\n}\n\n/**\n * cfg_sounding_88xx() - configure general sounding\n * @adapter : the adapter of halmac\n * @role : driver's role, BFer or BFee\n * @rate : set ndpa tx rate if driver is BFer,\n * or set csi response rate if driver is BFee\n * Author : chunchu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role,\n\t\t  enum halmac_data_rate rate)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tu32 tmp6dc = 0;\n\tu8 csi_rsc = 0x0;\n\n\t/*use ndpa rx rate to decide csi rate*/\n\ttmp6dc = HALMAC_REG_R32(REG_BBPSF_CTRL) | BIT_WMAC_USE_NDPARATE\n\t\t\t\t\t\t\t| (csi_rsc << 13);\n\n\tswitch (role) {\n\tcase HAL_BFER:\n\t\tHALMAC_REG_W32_SET(REG_TXBF_CTRL, TXBF_CTRL_CFG);\n\t\tHALMAC_REG_W8(REG_NDPA_RATE, rate);\n\t\tHALMAC_REG_W8(REG_SND_PTCL_CTRL + 1, 0x2 | BIT(7));\n\t\tHALMAC_REG_W8(REG_SND_PTCL_CTRL + 2, 0x2);\n\t\tbreak;\n\tcase HAL_BFEE:\n\t\tHALMAC_REG_W8(REG_SND_PTCL_CTRL, 0xDB);\n\t\tHALMAC_REG_W8(REG_SND_PTCL_CTRL + 3, 0x26);\n\t\tHALMAC_REG_W8_CLR(REG_RXFLTMAP1, BIT(4));\n\t\tHALMAC_REG_W8_CLR(REG_RXFLTMAP4, BIT(4));\n\t\t#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\t\tif (adapter->chip_id == HALMAC_CHIP_ID_8822C)\n\t\t\tHALMAC_REG_W32(REG_CSI_RRSR,\n\t\t\t\t       BIT_CSI_RRSC_BITMAP(CSI_RATE_MAP) |\n\t\t\t\t       BIT_OFDM_LEN_TH(0));\n\t\telse if (adapter->chip_id == HALMAC_CHIP_ID_8812F)\n\t\t\tHALMAC_REG_W32(REG_CSI_RRSR,\n\t\t\t\t       BIT_CSI_RRSC_BITMAP(CSI_RATE_MAP) |\n\t\t\t\t       BIT_OFDM_LEN_TH(3));\n\t\t#endif\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_INVALID_SOUNDING_SETTING;\n\t}\n\n\t/*AP mode set tx gid to 63*/\n\t/*STA mode set tx gid to 0*/\n\tif (BIT_GET_NETYPE0(HALMAC_REG_R32(REG_CR)) == 0x3)\n\t\tHALMAC_REG_W32(REG_BBPSF_CTRL, tmp6dc | BIT(12));\n\telse\n\t\tHALMAC_REG_W32(REG_BBPSF_CTRL, tmp6dc & ~(BIT(12)));\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * del_sounding_88xx() - reset general sounding\n * @adapter : the adapter of halmac\n * @role : driver's role, BFer or BFee\n * Author : chunchu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ndel_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tswitch (role) {\n\tcase HAL_BFER:\n\t\tHALMAC_REG_W8(REG_TXBF_CTRL + 3, 0);\n\t\tbreak;\n\tcase HAL_BFEE:\n\t\tHALMAC_REG_W8(REG_SND_PTCL_CTRL, 0);\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_INVALID_SOUNDING_SETTING;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * su_bfee_entry_init_88xx() - config SU beamformee's registers\n * @adapter : the adapter of halmac\n * @userid : SU bfee userid = 0 or 1 to be added\n * @paid : partial AID of this bfee\n * Author : chunchu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nsu_bfee_entry_init_88xx(struct halmac_adapter *adapter, u8 userid, u16 paid)\n{\n\tu16 tmp42c = 0;\n\tu16 tmp168x = 0;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tswitch (userid) {\n\tcase 0:\n\t\ttmp42c = HALMAC_REG_R16(REG_TXBF_CTRL) &\n\t\t\t\t~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M |\n\t\t\t\tBIT_R_TXBF0_40M | BIT_R_TXBF0_80M);\n\t\tHALMAC_REG_W16(REG_TXBF_CTRL, tmp42c | paid);\n\t\tHALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, paid);\n\t\t#if HALMAC_8822C_SUPPORT\n\t\tif (adapter->chip_id == HALMAC_CHIP_ID_8822C)\n\t\t\tHALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, paid | BIT(9));\n\t\t#endif\n\t\tbreak;\n\tcase 1:\n\t\ttmp42c = HALMAC_REG_R16(REG_TXBF_CTRL + 2) &\n\t\t\t\t~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M |\n\t\t\t\tBIT_R_TXBF0_40M | BIT_R_TXBF0_80M);\n\t\tHALMAC_REG_W16(REG_TXBF_CTRL + 2, tmp42c | paid);\n\t\tHALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL + 2, paid | BIT(9));\n\t\tbreak;\n\tcase 2:\n\t\ttmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE2);\n\t\ttmp168x = BIT_CLEAR_WMAC_MU_BFEE2_AID(tmp168x);\n\t\ttmp168x |= (paid | BIT(9));\n\t\tHALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE2, tmp168x);\n\t\tbreak;\n\tcase 3:\n\t\ttmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE3);\n\t\ttmp168x = BIT_CLEAR_WMAC_MU_BFEE3_AID(tmp168x);\n\t\ttmp168x |= (paid | BIT(9));\n\t\tHALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE3, tmp168x);\n\t\tbreak;\n\tcase 4:\n\t\ttmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE4);\n\t\ttmp168x = BIT_CLEAR_WMAC_MU_BFEE4_AID(tmp168x);\n\t\ttmp168x |= (paid | BIT(9));\n\t\tHALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE4, tmp168x);\n\t\tbreak;\n\tcase 5:\n\t\ttmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE5);\n\t\ttmp168x = BIT_CLEAR_WMAC_MU_BFEE5_AID(tmp168x);\n\t\ttmp168x |= (paid | BIT(9));\n\t\tHALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE5, tmp168x);\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_INVALID_SOUNDING_SETTING;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * su_bfee_entry_init_88xx() - config SU beamformer's registers\n * @adapter : the adapter of halmac\n * @param : parameters to configure SU BFER entry\n * Author : chunchu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nsu_bfer_entry_init_88xx(struct halmac_adapter *adapter,\n\t\t\tstruct halmac_su_bfer_init_para *param)\n{\n\tu16 mac_addr_h;\n\tu32 mac_addr_l;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tmac_addr_l = rtk_le32_to_cpu(param->bfer_address.addr_l_h.low);\n\tmac_addr_h = rtk_le16_to_cpu(param->bfer_address.addr_l_h.high);\n\n\tswitch (param->userid) {\n\tcase 0:\n\t\tHALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, mac_addr_l);\n\t\tHALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 4, mac_addr_h);\n\t\tHALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 6, param->paid);\n\t\tHALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20, param->csi_para);\n\t\tbreak;\n\tcase 1:\n\t\tHALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO, mac_addr_l);\n\t\tHALMAC_REG_W16(REG_ASSOCIATED_BFMER1_INFO + 4, mac_addr_h);\n\t\tHALMAC_REG_W16(REG_ASSOCIATED_BFMER1_INFO + 6, param->paid);\n\t\tHALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20 + 2, param->csi_para);\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_INVALID_SOUNDING_SETTING;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * mu_bfee_entry_init_88xx() - config MU beamformee's registers\n * @adapter : the adapter of halmac\n * @param : parameters to configure MU BFEE entry\n * Author : chunchu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nmu_bfee_entry_init_88xx(struct halmac_adapter *adapter,\n\t\t\tstruct halmac_mu_bfee_init_para *param)\n{\n\tu16 tmp168x = 0;\n\tu16 tmp14c0;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\ttmp168x |= param->paid | BIT(9);\n\tHALMAC_REG_W16((0x1680 + param->userid * 2), tmp168x);\n\n\ttmp14c0 = HALMAC_REG_R16(REG_MU_TX_CTL) & ~(BIT(8) | BIT(9) | BIT(10));\n\tHALMAC_REG_W16(REG_MU_TX_CTL, tmp14c0 | ((param->userid - 2) << 8));\n\tHALMAC_REG_W32(REG_MU_STA_GID_VLD, 0);\n\tHALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->user_position_l);\n\tHALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->user_position_h);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * mu_bfer_entry_init_88xx() - config MU beamformer's registers\n * @adapter : the adapter of halmac\n * @param : parameters to configure MU BFER entry\n * Author : chunchu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nmu_bfer_entry_init_88xx(struct halmac_adapter *adapter,\n\t\t\tstruct halmac_mu_bfer_init_para *param)\n{\n\tu16 tmp1680 = 0;\n\tu16 mac_addr_h;\n\tu32 mac_addr_l;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tmac_addr_l = rtk_le32_to_cpu(param->bfer_address.addr_l_h.low);\n\tmac_addr_h = rtk_le16_to_cpu(param->bfer_address.addr_l_h.high);\n\n\tHALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, mac_addr_l);\n\tHALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 4, mac_addr_h);\n\tHALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 6, param->paid);\n\tHALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20, param->csi_para);\n\n\ttmp1680 = HALMAC_REG_R16(0x1680) & 0xC000;\n\ttmp1680 |= param->my_aid | (param->csi_length_sel << 12);\n\tHALMAC_REG_W16(0x1680, tmp1680);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * su_bfee_entry_del_88xx() - reset SU beamformee's registers\n * @adapter : the adapter of halmac\n * @userid : the SU BFee userid to be deleted\n * Author : chunchu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nsu_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid)\n{\n\tu16 value16;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tswitch (userid) {\n\tcase 0:\n\t\tvalue16 = HALMAC_REG_R16(REG_TXBF_CTRL);\n\t\tvalue16 &= ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M |\n\t\t\t\t\tBIT_R_TXBF0_40M | BIT_R_TXBF0_80M);\n\t\tHALMAC_REG_W16(REG_TXBF_CTRL, value16);\n\t\tHALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, 0);\n\t\tbreak;\n\tcase 1:\n\t\tvalue16 = HALMAC_REG_R16(REG_TXBF_CTRL + 2);\n\t\tvalue16 &= ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M |\n\t\t\t\t\tBIT_R_TXBF0_40M | BIT_R_TXBF0_80M);\n\t\tHALMAC_REG_W16(REG_TXBF_CTRL + 2, value16);\n\t\tHALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL + 2, 0);\n\t\tbreak;\n\tcase 2:\n\t\tHALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE2, 0);\n\t\tbreak;\n\tcase 3:\n\t\tHALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE3, 0);\n\t\tbreak;\n\tcase 4:\n\t\tHALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE4, 0);\n\t\tbreak;\n\tcase 5:\n\t\tHALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE5, 0);\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_INVALID_SOUNDING_SETTING;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * su_bfee_entry_del_88xx() - reset SU beamformer's registers\n * @adapter : the adapter of halmac\n * @userid : the SU BFer userid to be deleted\n * Author : chunchu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nsu_bfer_entry_del_88xx(struct halmac_adapter *adapter, u8 userid)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tswitch (userid) {\n\tcase 0:\n\t\tHALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, 0);\n\t\tHALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO + 4, 0);\n\t\tbreak;\n\tcase 1:\n\t\tHALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO, 0);\n\t\tHALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO + 4, 0);\n\t\tbreak;\n\tdefault:\n\t\treturn HALMAC_RET_INVALID_SOUNDING_SETTING;\n\t}\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * mu_bfee_entry_del_88xx() - reset MU beamformee's registers\n * @adapter : the adapter of halmac\n * @userid : the MU STA userid to be deleted\n * Author : chunchu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nmu_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tHALMAC_REG_W16(0x1680 + userid * 2, 0);\n\tHALMAC_REG_W8_CLR(REG_MU_TX_CTL, BIT(userid - 2));\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * mu_bfer_entry_del_88xx() -reset MU beamformer's registers\n * @adapter : the adapter of halmac\n * Author : chunchu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nmu_bfer_entry_del_88xx(struct halmac_adapter *adapter)\n{\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tHALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, 0);\n\tHALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO + 4, 0);\n\tHALMAC_REG_W16(0x1680, 0);\n\tHALMAC_REG_W8(REG_MU_TX_CTL, 0);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfg_csi_rate_88xx() - config CSI frame Tx rate\n * @adapter : the adapter of halmac\n * @rssi : rssi in decimal value\n * @cur_rate : current CSI frame rate\n * @fixrate_en : enable to fix CSI frame in VHT rate, otherwise legacy OFDM rate\n * @new_rate : API returns the final CSI frame rate\n * Author : chunchu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_csi_rate_88xx(struct halmac_adapter *adapter, u8 rssi, u8 cur_rate,\n\t\t  u8 fixrate_en, u8 *new_rate, u8 *bmp_ofdm54)\n{\n\tu32 csi_cfg;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\t*bmp_ofdm54 = 0xFF;\n\n#if HALMAC_8821C_SUPPORT\n\tif (adapter->chip_id == HALMAC_CHIP_ID_8821C && fixrate_en) {\n\t\tcsi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE;\n\t\tHALMAC_REG_W32(REG_BBPSF_CTRL,\n\t\t\t       csi_cfg | BIT_CSI_FORCE_RATE_EN |\n\t\t\t       BIT_CSI_RSC(1) |\n\t\t\t       BIT_WMAC_CSI_RATE(HALMAC_VHT_NSS1_MCS3));\n\t\t*new_rate = HALMAC_VHT_NSS1_MCS3;\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\tcsi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE &\n\t\t\t\t\t\t\t~BIT_CSI_FORCE_RATE_EN;\n#else\n\tcsi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE;\n#endif\n\n\n\tif (rssi >= 40) {\n\t\tif (cur_rate != HALMAC_OFDM54) {\n\t\t\tcsi_cfg |= BIT_WMAC_CSI_RATE(HALMAC_OFDM54);\n\t\t\tHALMAC_REG_W32(REG_BBPSF_CTRL, csi_cfg);\n\t\t\t*bmp_ofdm54 = 1;\n\t\t}\n\t\t*new_rate = HALMAC_OFDM54;\n\t} else {\n\t\tif (cur_rate != HALMAC_OFDM24) {\n\t\t\tcsi_cfg |= BIT_WMAC_CSI_RATE(HALMAC_OFDM24);\n\t\t\tHALMAC_REG_W32(REG_BBPSF_CTRL, csi_cfg);\n\t\t\t*bmp_ofdm54 = 0;\n\t\t}\n\t\t*new_rate = HALMAC_OFDM24;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * fw_snding_88xx() - fw sounding control\n * @adapter : the adapter of halmac\n * @su_info :\n *\tsu0_en : enable/disable fw sounding\n *\tsu0_ndpa_pkt : ndpa pkt, shall include txdesc\n *\tsu0_pkt_sz : ndpa pkt size, shall include txdesc\n * @mu_info : currently not in use, input NULL is acceptable\n * @period : sounding period, unit is 5ms\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nfw_snding_88xx(struct halmac_adapter *adapter,\n\t       struct halmac_su_snding_info *su_info,\n\t       struct halmac_mu_snding_info *mu_info, u8 period)\n{\n\tu8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };\n\tu16 seq_num;\n\tu16 snding_info_addr;\n\tstruct halmac_h2c_header_info hdr_info;\n\tenum halmac_cmd_process_status *proc_status;\n\tenum halmac_ret_status status;\n\n\tproc_status = &adapter->halmac_state.fw_snding_state.proc_status;\n\n\tif (adapter->chip_id == HALMAC_CHIP_ID_8821C)\n\t\treturn HALMAC_RET_NOT_SUPPORT;\n\n\tif (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_NO_DLFW;\n\n\tif (adapter->fw_ver.h2c_version < 9)\n\t\treturn HALMAC_RET_FW_NO_SUPPORT;\n\n\tif (*proc_status == HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_TRACE(\"[TRACE]Wait event(snd)\\n\");\n\t\treturn HALMAC_RET_BUSY_STATE;\n\t}\n\n\tif (su_info->su0_en == 1) {\n\t\tif (!su_info->su0_ndpa_pkt)\n\t\t\treturn HALMAC_RET_NULL_POINTER;\n\n\t\tif (su_info->su0_pkt_sz > (u32)SU0_SNDING_PKT_RSVDPG_SIZE -\n\t\t    adapter->hw_cfg_info.txdesc_size)\n\t\t\treturn HALMAC_RET_DATA_SIZE_INCORRECT;\n\n\t\tif (!snding_pkt_chk_88xx(adapter, su_info->su0_ndpa_pkt))\n\t\t\treturn HALMAC_RET_TXDESC_SET_FAIL;\n\n\t\tif (fw_snding_cmd_cnstr_state_88xx(adapter) !=\n\t\t    HALMAC_CMD_CNSTR_IDLE) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]Not idle(snd)\\n\");\n\t\t\treturn HALMAC_RET_ERROR_STATE;\n\t\t}\n\n\t\tsnding_info_addr = adapter->txff_alloc.rsvd_h2c_sta_info_addr +\n\t\t\t\t   SU0_SNDING_PKT_OFFSET;\n\t\tstatus = dl_rsvd_page_88xx(adapter, snding_info_addr,\n\t\t\t\t\t   su_info->su0_ndpa_pkt,\n\t\t\t\t\t   su_info->su0_pkt_sz);\n\t\tif (status != HALMAC_RET_SUCCESS) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]dl rsvd page\\n\");\n\t\t\treturn status;\n\t\t}\n\n\t\tFW_SNDING_SET_SU0(h2c_buf, 1);\n\t\tFW_SNDING_SET_PERIOD(h2c_buf, period);\n\t\tFW_SNDING_SET_NDPA0_HEAD_PG(h2c_buf, snding_info_addr -\n\t\t\t\t\t    adapter->txff_alloc.rsvd_boundary);\n\t} else {\n\t\tif (fw_snding_cmd_cnstr_state_88xx(adapter) !=\n\t\t    HALMAC_CMD_CNSTR_BUSY) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]Not snd(snd)\\n\");\n\t\t\treturn HALMAC_RET_ERROR_STATE;\n\t\t}\n\t\tFW_SNDING_SET_SU0(h2c_buf, 0);\n\t}\n\n\t*proc_status = HALMAC_CMD_PROCESS_SENDING;\n\n\thdr_info.sub_cmd_id = SUB_CMD_ID_FW_SNDING;\n\thdr_info.content_size = 8;\n\thdr_info.ack = 1;\n\tset_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);\n\tadapter->halmac_state.fw_snding_state.seq_num = seq_num;\n\n\tstatus = send_h2c_pkt_88xx(adapter, h2c_buf);\n\tif (status != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_MSG_ERR(\"[ERR]send h2c\\n\");\n\t\treset_ofld_feature_88xx(adapter, HALMAC_FEATURE_FW_SNDING);\n\t\treturn status;\n\t}\n\n\tif (cnv_fw_snding_state_88xx(adapter, su_info->su0_en == 1 ?\n\t\t\t\t     HALMAC_CMD_CNSTR_BUSY :\n\t\t\t\t     HALMAC_CMD_CNSTR_IDLE)\n\t\t\t\t     != HALMAC_RET_SUCCESS)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic u8\nsnding_pkt_chk_88xx(struct halmac_adapter *adapter, u8 *pkt)\n{\n\tu8 data_rate;\n\n\tif (GET_TX_DESC_NDPA(pkt) == 0) {\n\t\tPLTFM_MSG_ERR(\"[ERR]txdesc ndpa = 0\\n\");\n\t\treturn 0;\n\t}\n\n\tdata_rate = (u8)GET_TX_DESC_DATARATE(pkt);\n\tif (!(data_rate >= HALMAC_VHT_NSS2_MCS0 &&\n\t      data_rate <= HALMAC_VHT_NSS2_MCS9)) {\n\t\tif (!(data_rate >= HALMAC_MCS8 && data_rate <= HALMAC_MCS15)) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]txdesc rate\\n\");\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\tif (GET_TX_DESC_NAVUSEHDR(pkt) == 0) {\n\t\tPLTFM_MSG_ERR(\"[ERR]txdesc navusehdr = 0\\n\");\n\t\treturn 0;\n\t}\n\n\tif (GET_TX_DESC_USE_RATE(pkt) == 0) {\n\t\tPLTFM_MSG_ERR(\"[ERR]txdesc userate = 0\\n\");\n\t\treturn 0;\n\t}\n\n\treturn 1;\n}\n\nstatic enum halmac_cmd_construct_state\nfw_snding_cmd_cnstr_state_88xx(struct halmac_adapter *adapter)\n{\n\treturn adapter->halmac_state.fw_snding_state.cmd_cnstr_state;\n}\n\nenum halmac_ret_status\nget_h2c_ack_fw_snding_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)\n{\n\tu8 seq_num = 0;\n\tu8 fw_rc;\n\tstruct halmac_fw_snding_state *state;\n\tenum halmac_cmd_process_status proc_status;\n\n\tstate = &adapter->halmac_state.fw_snding_state;\n\n\tseq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);\n\tPLTFM_MSG_TRACE(\"[TRACE]Seq num:h2c->%d c2h->%d\\n\",\n\t\t\tstate->seq_num, seq_num);\n\tif (seq_num != state->seq_num) {\n\t\tPLTFM_MSG_ERR(\"[ERR]Seq num mismatch:h2c->%d c2h->%d\\n\",\n\t\t\t      state->seq_num, seq_num);\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tif (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {\n\t\tPLTFM_MSG_ERR(\"[ERR]not sending(snd)\\n\");\n\t\treturn HALMAC_RET_SUCCESS;\n\t}\n\n\tfw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);\n\tstate->fw_rc = fw_rc;\n\n\tif ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {\n\t\tproc_status = HALMAC_CMD_PROCESS_DONE;\n\t\tstate->proc_status = proc_status;\n\t\tPLTFM_EVENT_SIG(HALMAC_FEATURE_FW_SNDING, proc_status,\n\t\t\t\tNULL, 0);\n\t} else {\n\t\tproc_status = HALMAC_CMD_PROCESS_ERROR;\n\t\tstate->proc_status = proc_status;\n\t\tPLTFM_EVENT_SIG(HALMAC_FEATURE_FW_SNDING, proc_status,\n\t\t\t\t&fw_rc, 1);\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nenum halmac_ret_status\nget_fw_snding_status_88xx(struct halmac_adapter *adapter,\n\t\t\t  enum halmac_cmd_process_status *proc_status)\n{\n\t*proc_status = adapter->halmac_state.fw_snding_state.proc_status;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\ncnv_fw_snding_state_88xx(struct halmac_adapter *adapter,\n\t\t\t enum halmac_cmd_construct_state dest_state)\n{\n\tstruct halmac_fw_snding_state *state;\n\n\tstate = &adapter->halmac_state.fw_snding_state;\n\n\tif (state->cmd_cnstr_state != HALMAC_CMD_CNSTR_IDLE &&\n\t    state->cmd_cnstr_state != HALMAC_CMD_CNSTR_BUSY)\n\t\treturn HALMAC_RET_ERROR_STATE;\n\n\tif (dest_state == HALMAC_CMD_CNSTR_IDLE) {\n\t\tif (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_IDLE)\n\t\t\treturn HALMAC_RET_ERROR_STATE;\n\t} else if (dest_state == HALMAC_CMD_CNSTR_BUSY) {\n\t\tif (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_BUSY)\n\t\t\treturn HALMAC_RET_ERROR_STATE;\n\t}\n\n\tstate->cmd_cnstr_state = dest_state;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n#endif /* HALMAC_88XX_SUPPORT */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_mimo_88xx.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_MIMO_88XX_H_\n#define _HALMAC_MIMO_88XX_H_\n\n#include \"../halmac_api.h\"\n\n#if HALMAC_88XX_SUPPORT\n\nenum halmac_ret_status\ncfg_txbf_88xx(struct halmac_adapter *adapter, u8 userid, enum halmac_bw bw,\n\t      u8 txbf_en);\n\nenum halmac_ret_status\ncfg_mumimo_88xx(struct halmac_adapter *adapter,\n\t\tstruct halmac_cfg_mumimo_para *param);\n\nenum halmac_ret_status\ncfg_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role,\n\t\t  enum halmac_data_rate rate);\n\nenum halmac_ret_status\ndel_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role);\n\nenum halmac_ret_status\nsu_bfee_entry_init_88xx(struct halmac_adapter *adapter, u8 userid, u16 paid);\n\nenum halmac_ret_status\nsu_bfer_entry_init_88xx(struct halmac_adapter *adapter,\n\t\t\tstruct halmac_su_bfer_init_para *param);\n\nenum halmac_ret_status\nmu_bfee_entry_init_88xx(struct halmac_adapter *adapter,\n\t\t\tstruct halmac_mu_bfee_init_para *param);\n\nenum halmac_ret_status\nmu_bfer_entry_init_88xx(struct halmac_adapter *adapter,\n\t\t\tstruct halmac_mu_bfer_init_para *param);\n\nenum halmac_ret_status\nsu_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid);\n\nenum halmac_ret_status\nsu_bfer_entry_del_88xx(struct halmac_adapter *adapter, u8 userid);\n\nenum halmac_ret_status\nmu_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid);\n\nenum halmac_ret_status\nmu_bfer_entry_del_88xx(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\ncfg_csi_rate_88xx(struct halmac_adapter *adapter, u8 rssi, u8 cur_rate,\n\t\t  u8 fixrate_en, u8 *new_rate, u8 *bmp_ofdm54);\n\nenum halmac_ret_status\nfw_snding_88xx(struct halmac_adapter *adapter,\n\t       struct halmac_su_snding_info *su_info,\n\t       struct halmac_mu_snding_info *mu_info, u8 period);\n\nenum halmac_ret_status\nget_h2c_ack_fw_snding_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\nenum halmac_ret_status\nget_fw_snding_status_88xx(struct halmac_adapter *adapter,\n\t\t\t  enum halmac_cmd_process_status *proc_status);\n\n#endif /* HALMAC_88XX_SUPPORT */\n\n#endif/* _HALMAC_MIMO_88XX_H_ */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_pcie_88xx.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"halmac_pcie_88xx.h\"\n\n#if (HALMAC_88XX_SUPPORT && HALMAC_PCIE_SUPPORT)\n\n/**\n * init_pcie_cfg_88xx() -  init PCIe\n * @adapter : the adapter of halmac\n * Author : KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ninit_pcie_cfg_88xx(struct halmac_adapter *adapter)\n{\n#if HALMAC_8822C_SUPPORT\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tif (adapter->chip_id == HALMAC_CHIP_ID_8822C) {\n\t\tif (adapter->chip_ver == HALMAC_CHIP_VER_D_CUT ||\n\t\t    adapter->chip_ver == HALMAC_CHIP_VER_E_CUT ||\n\t\t    adapter->chip_ver == HALMAC_CHIP_VER_F_CUT)\n\t\t\t/* defined after 8822C D CUT */\n\t\t\tHALMAC_REG_W8_SET(REG_HCI_MIX_CFG + 3, BIT(2));\n\t}\n#endif\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * deinit_pcie_cfg_88xx() - deinit PCIE\n * @adapter : the adapter of halmac\n * Author : KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ndeinit_pcie_cfg_88xx(struct halmac_adapter *adapter)\n{\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfg_pcie_rx_agg_88xx() - config rx aggregation\n * @adapter : the adapter of halmac\n * @halmac_rx_agg_mode\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_pcie_rx_agg_88xx(struct halmac_adapter *adapter,\n\t\t     struct halmac_rxagg_cfg *cfg)\n{\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * reg_r8_pcie_88xx() - read 1byte register\n * @adapter : the adapter of halmac\n * @offset : register offset\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nu8\nreg_r8_pcie_88xx(struct halmac_adapter *adapter, u32 offset)\n{\n\treturn PLTFM_REG_R8(offset);\n}\n\n/**\n * reg_w8_pcie_88xx() - write 1byte register\n * @adapter : the adapter of halmac\n * @offset : register offset\n * @value : register value\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nreg_w8_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)\n{\n\tPLTFM_REG_W8(offset, value);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * reg_r16_pcie_88xx() - read 2byte register\n * @adapter : the adapter of halmac\n * @offset : register offset\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nu16\nreg_r16_pcie_88xx(struct halmac_adapter *adapter, u32 offset)\n{\n\treturn PLTFM_REG_R16(offset);\n}\n\n/**\n * reg_w16_pcie_88xx() - write 2byte register\n * @adapter : the adapter of halmac\n * @offset : register offset\n * @value : register value\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nreg_w16_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u16 value)\n{\n\tPLTFM_REG_W16(offset, value);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * reg_r32_pcie_88xx() - read 4byte register\n * @adapter : the adapter of halmac\n * @offset : register offset\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nu32\nreg_r32_pcie_88xx(struct halmac_adapter *adapter, u32 offset)\n{\n\treturn PLTFM_REG_R32(offset);\n}\n\n/**\n * reg_w32_pcie_88xx() - write 4byte register\n * @adapter : the adapter of halmac\n * @offset : register offset\n * @value : register value\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nreg_w32_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u32 value)\n{\n\tPLTFM_REG_W32(offset, value);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * cfg_txagg_pcie_align_88xx() -config sdio bus tx agg alignment\n * @adapter : the adapter of halmac\n * @enable : function enable(1)/disable(0)\n * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)\n * Author : Soar Tu\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ncfg_txagg_pcie_align_88xx(struct halmac_adapter *adapter, u8 enable,\n\t\t\t  u16 align_size)\n{\n\treturn HALMAC_RET_NOT_SUPPORT;\n}\n\n/**\n * tx_allowed_pcie_88xx() - check tx status\n * @adapter : the adapter of halmac\n * @buf : tx packet, include txdesc\n * @size : tx packet size, include txdesc\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\ntx_allowed_pcie_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)\n{\n\treturn HALMAC_RET_NOT_SUPPORT;\n}\n\n/**\n * pcie_indirect_reg_r32_88xx() - read MAC reg by SDIO reg\n * @adapter : the adapter of halmac\n * @offset : register offset\n * Author : Soar\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nu32\npcie_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset)\n{\n\treturn 0xFFFFFFFF;\n}\n\n/**\n * pcie_reg_rn_88xx() - read n byte register\n * @adapter : the adapter of halmac\n * @offset : register offset\n * @size : register value size\n * @value : register value\n * Author : Soar\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\npcie_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,\n\t\t u8 *value)\n{\n\treturn HALMAC_RET_NOT_SUPPORT;\n}\n\n/**\n * set_pcie_bulkout_num_88xx() - inform bulk-out num\n * @adapter : the adapter of halmac\n * @num : usb bulk-out number\n * Author : KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nset_pcie_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num)\n{\n\treturn HALMAC_RET_NOT_SUPPORT;\n}\n\n/**\n * get_pcie_tx_addr_88xx() - get CMD53 addr for the TX packet\n * @adapter : the adapter of halmac\n * @buf : tx packet, include txdesc\n * @size : tx packet size\n * @cmd53_addr : cmd53 addr value\n * Author : KaiYuan Chang/Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nget_pcie_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,\n\t\t      u32 *cmd53_addr)\n{\n\treturn HALMAC_RET_NOT_SUPPORT;\n}\n\n/**\n * get_pcie_bulkout_id_88xx() - get bulk out id for the TX packet\n * @adapter : the adapter of halmac\n * @buf : tx packet, include txdesc\n * @size : tx packet size\n * @id : usb bulk-out id\n * Author : KaiYuan Chang\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nget_pcie_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,\n\t\t\t u8 *id)\n{\n\treturn HALMAC_RET_NOT_SUPPORT;\n}\n\nenum halmac_ret_status\nmdio_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed)\n{\n\tu8 tmp_u1b = 0;\n\tu32 cnt = 0;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tu8 real_addr = 0;\n\n\tHALMAC_REG_W16(REG_MDIO_V1, data);\n\n\treal_addr = (addr & 0x1F);\n\tHALMAC_REG_W8(REG_PCIE_MIX_CFG, real_addr);\n\n\tif (speed == HAL_INTF_PHY_PCIE_GEN1) {\n\t\tif (addr < 0x20)\n\t\t\tHALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x00);\n\t\telse\n\t\t\tHALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x01);\n\t} else if (speed == HAL_INTF_PHY_PCIE_GEN2) {\n\t\tif (addr < 0x20)\n\t\t\tHALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x02);\n\t\telse\n\t\t\tHALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x03);\n\t} else {\n\t\tPLTFM_MSG_ERR(\"[ERR]Error Speed !\\n\");\n\t}\n\n\tHALMAC_REG_W8_SET(REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1);\n\n\ttmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1;\n\tcnt = 20;\n\n\twhile (tmp_u1b && (cnt != 0)) {\n\t\tPLTFM_DELAY_US(10);\n\t\ttmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1;\n\t\tcnt--;\n\t}\n\n\tif (tmp_u1b) {\n\t\tPLTFM_MSG_ERR(\"[ERR]MDIO write fail!\\n\");\n\t\treturn HALMAC_RET_FAIL;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nu16\nmdio_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed)\n{\n\tu16 ret = 0;\n\tu8 tmp_u1b = 0;\n\tu32 cnt = 0;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\tu8 real_addr = 0;\n\n\treal_addr = (addr & 0x1F);\n\tHALMAC_REG_W8(REG_PCIE_MIX_CFG, real_addr);\n\n\tif (speed == HAL_INTF_PHY_PCIE_GEN1) {\n\t\tif (addr < 0x20)\n\t\t\tHALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x00);\n\t\telse\n\t\t\tHALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x01);\n\t} else if (speed == HAL_INTF_PHY_PCIE_GEN2) {\n\t\tif (addr < 0x20)\n\t\t\tHALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x02);\n\t\telse\n\t\t\tHALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x03);\n\t} else {\n\t\tPLTFM_MSG_ERR(\"[ERR]Error Speed !\\n\");\n\t}\n\n\tHALMAC_REG_W8_SET(REG_PCIE_MIX_CFG, BIT_MDIO_RFLAG_V1);\n\n\ttmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1;\n\tcnt = 20;\n\twhile (tmp_u1b && (cnt != 0)) {\n\t\tPLTFM_DELAY_US(10);\n\t\ttmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1;\n\t\tcnt--;\n\t}\n\n\tif (tmp_u1b) {\n\t\tret  = 0xFFFF;\n\t\tPLTFM_MSG_ERR(\"[ERR]MDIO read fail!\\n\");\n\t} else {\n\t\tret = HALMAC_REG_R16(REG_MDIO_V1 + 2);\n\t\tPLTFM_MSG_TRACE(\"[TRACE]Value-R = %x\\n\", ret);\n\t}\n\n\treturn ret;\n}\n\nenum halmac_ret_status\ndbi_w32_88xx(struct halmac_adapter *adapter, u16 addr, u32 data)\n{\n\tu8 tmp_u1b = 0;\n\tu32 cnt = 0;\n\tu16 write_addr = 0;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tHALMAC_REG_W32(REG_DBI_WDATA_V1, data);\n\n\twrite_addr = ((addr & 0x0ffc) | (0x000F << 12));\n\tHALMAC_REG_W16(REG_DBI_FLAG_V1, write_addr);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]Addr-W = %x\\n\", write_addr);\n\n\tHALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x01);\n\ttmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);\n\n\tcnt = 20;\n\twhile (tmp_u1b && (cnt != 0)) {\n\t\tPLTFM_DELAY_US(10);\n\t\ttmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);\n\t\tcnt--;\n\t}\n\n\tif (tmp_u1b) {\n\t\tPLTFM_MSG_ERR(\"[ERR]DBI write fail!\\n\");\n\t\treturn HALMAC_RET_FAIL;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nu32\ndbi_r32_88xx(struct halmac_adapter *adapter, u16 addr)\n{\n\tu16 read_addr = addr & 0x0ffc;\n\tu8 tmp_u1b = 0;\n\tu32 cnt = 0;\n\tu32 ret = 0;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tHALMAC_REG_W16(REG_DBI_FLAG_V1, read_addr);\n\n\tHALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x2);\n\ttmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);\n\n\tcnt = 20;\n\twhile (tmp_u1b && (cnt != 0)) {\n\t\tPLTFM_DELAY_US(10);\n\t\ttmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);\n\t\tcnt--;\n\t}\n\n\tif (tmp_u1b) {\n\t\tret  = 0xFFFF;\n\t\tPLTFM_MSG_ERR(\"[ERR]DBI read fail!\\n\");\n\t} else {\n\t\tret = HALMAC_REG_R32(REG_DBI_RDATA_V1);\n\t\tPLTFM_MSG_TRACE(\"[TRACE]Value-R = %x\\n\", ret);\n\t}\n\n\treturn ret;\n}\n\nenum halmac_ret_status\ndbi_w8_88xx(struct halmac_adapter *adapter, u16 addr, u8 data)\n{\n\tu8 tmp_u1b = 0;\n\tu32 cnt = 0;\n\tu16 write_addr = 0;\n\tu16 remainder = addr & (4 - 1);\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tHALMAC_REG_W8(REG_DBI_WDATA_V1 + remainder, data);\n\n\twrite_addr = ((addr & 0x0ffc) | (BIT(0) << (remainder + 12)));\n\n\tHALMAC_REG_W16(REG_DBI_FLAG_V1, write_addr);\n\n\tPLTFM_MSG_TRACE(\"[TRACE]Addr-W = %x\\n\", write_addr);\n\n\tHALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x01);\n\n\ttmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);\n\n\tcnt = 20;\n\twhile (tmp_u1b && (cnt != 0)) {\n\t\tPLTFM_DELAY_US(10);\n\t\ttmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);\n\t\tcnt--;\n\t}\n\n\tif (tmp_u1b) {\n\t\tPLTFM_MSG_ERR(\"[ERR]DBI write fail!\\n\");\n\t\treturn HALMAC_RET_FAIL;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nu8\ndbi_r8_88xx(struct halmac_adapter *adapter, u16 addr)\n{\n\tu16 read_addr = addr & 0x0ffc;\n\tu8 tmp_u1b = 0;\n\tu32 cnt = 0;\n\tu8 ret = 0;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\tHALMAC_REG_W16(REG_DBI_FLAG_V1, read_addr);\n\tHALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x2);\n\n\ttmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);\n\n\tcnt = 20;\n\twhile (tmp_u1b && (cnt != 0)) {\n\t\tPLTFM_DELAY_US(10);\n\t\ttmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);\n\t\tcnt--;\n\t}\n\n\tif (tmp_u1b) {\n\t\tret  = 0xFF;\n\t\tPLTFM_MSG_ERR(\"[ERR]DBI read fail!\\n\");\n\t} else {\n\t\tret = HALMAC_REG_R8(REG_DBI_RDATA_V1 + (addr & (4 - 1)));\n\t\tPLTFM_MSG_TRACE(\"[TRACE]Value-R = %x\\n\", ret);\n\t}\n\n\treturn ret;\n}\n\nenum halmac_ret_status\ntrxdma_check_idle_88xx(struct halmac_adapter *adapter)\n{\n\tu32 cnt = 0;\n\tstruct halmac_api *api = (struct halmac_api *)adapter->halmac_api;\n\n\t/* Stop Tx & Rx DMA */\n\tHALMAC_REG_W32_SET(REG_RXPKT_NUM, BIT(18));\n\tHALMAC_REG_W16_SET(REG_PCIE_CTRL, ~(BIT(15) | BIT(8)));\n\n\t/* Stop FW */\n\tHALMAC_REG_W16_CLR(REG_SYS_FUNC_EN, BIT(10));\n\n\t/* Check Tx DMA is idle */\n\tcnt = 20;\n\twhile ((HALMAC_REG_R8(REG_SYS_CFG5) & BIT(2)) == BIT(2)) {\n\t\tPLTFM_DELAY_US(10);\n\t\tcnt--;\n\t\tif (cnt == 0) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]Chk tx idle\\n\");\n\t\t\treturn HALMAC_RET_POWER_OFF_FAIL;\n\t\t}\n\t}\n\n\t/* Check Rx DMA is idle */\n\tcnt = 20;\n\twhile ((HALMAC_REG_R32(REG_RXPKT_NUM) & BIT(17)) != BIT(17)) {\n\t\tPLTFM_DELAY_US(10);\n\t\tcnt--;\n\t\tif (cnt == 0) {\n\t\t\tPLTFM_MSG_ERR(\"[ERR]Chk rx idle\\n\");\n\t\t\treturn HALMAC_RET_POWER_OFF_FAIL;\n\t\t}\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nvoid\nen_ref_autok_88xx(struct halmac_adapter *adapter, u8 en)\n{\n\tif (en == 1)\n\t\tadapter->pcie_refautok_en = 1;\n\telse\n\t\tadapter->pcie_refautok_en = 0;\n}\n\n#endif /* HALMAC_88XX_SUPPORT */\n"
  },
  {
    "path": "hal/halmac/halmac_88xx/halmac_pcie_88xx.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_PCIE_88XX_H_\n#define _HALMAC_PCIE_88XX_H_\n\n#include \"../halmac_api.h\"\n\n#if (HALMAC_88XX_SUPPORT && HALMAC_PCIE_SUPPORT)\n\nenum halmac_ret_status\ninit_pcie_cfg_88xx(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\ndeinit_pcie_cfg_88xx(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\ncfg_pcie_rx_agg_88xx(struct halmac_adapter *adapter,\n\t\t     struct halmac_rxagg_cfg *cfg);\n\nu8\nreg_r8_pcie_88xx(struct halmac_adapter *adapter, u32 offset);\n\nenum halmac_ret_status\nreg_w8_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);\n\nu16\nreg_r16_pcie_88xx(struct halmac_adapter *adapter, u32 offset);\n\nenum halmac_ret_status\nreg_w16_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u16 value);\n\nu32\nreg_r32_pcie_88xx(struct halmac_adapter *adapter, u32 offset);\n\nenum halmac_ret_status\nreg_w32_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u32 value);\n\nenum halmac_ret_status\ncfg_txagg_pcie_align_88xx(struct halmac_adapter *adapter, u8 enable,\n\t\t\t  u16 align_size);\n\nenum halmac_ret_status\ntx_allowed_pcie_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\nu32\npcie_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset);\n\nenum halmac_ret_status\npcie_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,\n\t\t u8 *value);\n\nenum halmac_ret_status\nset_pcie_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num);\n\nenum halmac_ret_status\nget_pcie_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,\n\t\t      u32 *cmd53_addr);\n\nenum halmac_ret_status\nget_pcie_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,\n\t\t\t u8 *id);\n\nenum halmac_ret_status\nmdio_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed);\n\nu16\nmdio_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed);\n\nenum halmac_ret_status\ndbi_w32_88xx(struct halmac_adapter *adapter, u16 addr, u32 data);\n\nu32\ndbi_r32_88xx(struct halmac_adapter *adapter, u16 addr);\n\nenum halmac_ret_status\ndbi_w8_88xx(struct halmac_adapter *adapter, u16 addr, u8 data);\n\nu8\ndbi_r8_88xx(struct halmac_adapter *adapter, u16 addr);\n\nenum halmac_ret_status\ntrxdma_check_idle_88xx(struct halmac_adapter *adapter);\n\nvoid\nen_ref_autok_88xx(struct halmac_adapter *dapter, u8 en);\n\n#endif /* HALMAC_88XX_SUPPORT */\n\n#endif/* _HALMAC_PCIE_88XX_H_ */\n"
  },
  {
    "path": "hal/halmac/halmac_api.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#include \"halmac_type.h\"\n#include \"halmac_api.h\"\n\n#if (HALMAC_PLATFORM_WINDOWS)\n\n#if HALMAC_8822B_SUPPORT\n#include \"halmac_88xx/halmac_init_win8822b.h\"\n#endif\n\n#if HALMAC_8821C_SUPPORT\n#include \"halmac_88xx/halmac_init_win8821c.h\"\n#endif\n\n#if HALMAC_8814B_SUPPORT\n#include \"halmac_88xx_v1/halmac_init_win8814b_v1.h\"\n#endif\n\n#if HALMAC_8822C_SUPPORT\n#include \"halmac_88xx/halmac_init_win8822c.h\"\n#endif\n\n#else\n\n#if HALMAC_88XX_SUPPORT\n#include \"halmac_88xx/halmac_init_88xx.h\"\n#endif\n#if HALMAC_88XX_V1_SUPPORT\n#include \"halmac_88xx_v1/halmac_init_88xx_v1.h\"\n#if defined(HALMAC_DATA_CPU_EN)\n#include \"halmac_88xxd_v1/halmac_init_88xxd_v1.h\"\n#endif\n#endif\n\n#endif\n\nenum chip_id_hw_def {\n\tCHIP_ID_HW_DEF_8723A = 0x01,\n\tCHIP_ID_HW_DEF_8188E = 0x02,\n\tCHIP_ID_HW_DEF_8881A = 0x03,\n\tCHIP_ID_HW_DEF_8812A = 0x04,\n\tCHIP_ID_HW_DEF_8821A = 0x05,\n\tCHIP_ID_HW_DEF_8723B = 0x06,\n\tCHIP_ID_HW_DEF_8192E = 0x07,\n\tCHIP_ID_HW_DEF_8814A = 0x08,\n\tCHIP_ID_HW_DEF_8821C = 0x09,\n\tCHIP_ID_HW_DEF_8822B = 0x0A,\n\tCHIP_ID_HW_DEF_8703B = 0x0B,\n\tCHIP_ID_HW_DEF_8188F = 0x0C,\n\tCHIP_ID_HW_DEF_8192F = 0x0D,\n\tCHIP_ID_HW_DEF_8197F = 0x0E,\n\tCHIP_ID_HW_DEF_8723D = 0x0F,\n\tCHIP_ID_HW_DEF_8814B = 0x11,\n\tCHIP_ID_HW_DEF_8822C = 0x13,\n\tCHIP_ID_HW_DEF_8812F = 0x14,\n\tCHIP_ID_HW_DEF_UNDEFINE = 0x7F,\n\tCHIP_ID_HW_DEF_PS = 0xEA,\n};\n\nstatic enum halmac_ret_status\nchk_pltfm_api(void *drv_adapter, enum halmac_interface intf,\n\t      struct halmac_platform_api *pltfm_api);\n\nstatic enum halmac_ret_status\nget_chip_info(void *drv_adapter, struct halmac_platform_api *pltfm_api,\n\t      enum halmac_interface intf, struct halmac_adapter *adapter);\n\nstatic u8\npltfm_reg_r8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,\n\t\t  u32 offset);\n\nstatic enum halmac_ret_status\npltfm_reg_w8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,\n\t\t  u32 offset, u8 data);\n\nstatic u8\npltfm_reg_r_indir_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,\n\t\t       u32 offset);\n\nstatic enum halmac_ret_status\ncnv_to_sdio_bus_offset(u32 *offset);\n\n/**\n * halmac_init_adapter() - init halmac_adapter\n * @drv_adapter : the adapter of caller\n * @pltfm_api : the platform APIs which is used in halmac\n * @intf : bus interface\n * @halmac_adapter : the adapter of halmac\n * @halmac_api : the function pointer of APIs\n * Author : KaiYuan Chang / Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nhalmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api,\n\t\t    enum halmac_interface intf,\n\t\t    struct halmac_adapter **halmac_adapter,\n\t\t    struct halmac_api **halmac_api)\n{\n\tstruct halmac_adapter *adapter = NULL;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\tu8 *buf = NULL;\n\n\tunion {\n\t\tu32 i;\n\t\tu8 x[4];\n\t} ENDIAN_CHECK = { 0x01000000 };\n\n\tstatus = chk_pltfm_api(drv_adapter, intf, pltfm_api);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS,\n\t\t\t     HALMAC_SVN_VER \"\\n\"\n\t\t\t     \"HALMAC_MAJOR_VER = %x\\n\"\n\t\t\t     \"HALMAC_PROTOTYPE_VER = %x\\n\"\n\t\t\t     \"HALMAC_MINOR_VER = %x\\n\"\n\t\t\t     \"HALMAC_PATCH_VER = %x\\n\",\n\t\t\t     HALMAC_MAJOR_VER, HALMAC_PROTOTYPE_VER,\n\t\t\t     HALMAC_MINOR_VER, HALMAC_PATCH_VER);\n\n\tif (ENDIAN_CHECK.x[0] == HALMAC_SYSTEM_ENDIAN) {\n\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t     HALMAC_DBG_ERR,\n\t\t\t\t     \"[ERR]Endian setting err!!\\n\");\n\t\treturn HALMAC_RET_ENDIAN_ERR;\n\t}\n\n\tbuf = (u8 *)pltfm_api->RTL_MALLOC(drv_adapter, sizeof(*adapter));\n\n\tif (!buf) {\n\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t     HALMAC_DBG_ERR,\n\t\t\t\t     \"[ERR]Malloc HAL adapter err!!\\n\");\n\t\treturn HALMAC_RET_MALLOC_FAIL;\n\t}\n\tpltfm_api->RTL_MEMSET(drv_adapter, buf, 0x00, sizeof(*adapter));\n\tadapter = (struct halmac_adapter *)buf;\n\n\t*halmac_adapter = adapter;\n\n\tadapter->pltfm_api = pltfm_api;\n\tadapter->drv_adapter = drv_adapter;\n\tintf = (intf == HALMAC_INTERFACE_AXI) ? HALMAC_INTERFACE_PCIE : intf;\n\tadapter->intf = intf;\n\n\tif (get_chip_info(drv_adapter, pltfm_api, intf, adapter)\n\t    != HALMAC_RET_SUCCESS) {\n\t\tPLTFM_FREE(*halmac_adapter, sizeof(**halmac_adapter));\n\t\t*halmac_adapter = NULL;\n\t\treturn HALMAC_RET_CHIP_NOT_SUPPORT;\n\t}\n\n\tPLTFM_MUTEX_INIT(&adapter->efuse_mutex);\n\tPLTFM_MUTEX_INIT(&adapter->h2c_seq_mutex);\n\tPLTFM_MUTEX_INIT(&adapter->sdio_indir_mutex);\n\n#if (HALMAC_PLATFORM_WINDOWS == 0)\n\n#if HALMAC_88XX_SUPPORT\n\tif (adapter->chip_id == HALMAC_CHIP_ID_8822B ||\n\t    adapter->chip_id == HALMAC_CHIP_ID_8821C ||\n\t    adapter->chip_id == HALMAC_CHIP_ID_8822C ||\n\t    adapter->chip_id == HALMAC_CHIP_ID_8812F) {\n\t\tinit_adapter_param_88xx(adapter);\n\t\tstatus = mount_api_88xx(adapter);\n\t}\n#endif\n\n#if HALMAC_88XX_V1_SUPPORT\n\tif (adapter->chip_id == HALMAC_CHIP_ID_8814B) {\n\t\tinit_adapter_param_88xx_v1(adapter);\n\t\tstatus = mount_api_88xx_v1(adapter);\n\t}\n#if defined(HALMAC_DATA_CPU_EN)\n\tif (adapter->chip_id == HALMAC_CHIP_ID_8814B) {\n\t\tinit_adapter_param_88xxd_v1(adapter);\n\t\tstatus = mount_api_88xxd_v1(adapter);\n\t}\n#endif\n#endif\n\n#else\n\n#if HALMAC_8822B_SUPPORT\n\tif (adapter->chip_id == HALMAC_CHIP_ID_8822B) {\n\t\tinit_adapter_param_win8822b(adapter);\n\t\tstatus = mount_api_win8822b(adapter);\n\t}\n#endif\n\n#if HALMAC_8821C_SUPPORT\n\tif (adapter->chip_id == HALMAC_CHIP_ID_8821C) {\n\t\tinit_adapter_param_win8821c(adapter);\n\t\tstatus = mount_api_win8821c(adapter);\n\t}\n#endif\n\n#if HALMAC_8814B_SUPPORT\n\tif (adapter->chip_id == HALMAC_CHIP_ID_8814B) {\n\t\tinit_adapter_param_win8814b_v1(adapter);\n\t\tstatus = mount_api_win8814b_v1(adapter);\n\t}\n#endif\n\n#if HALMAC_8822C_SUPPORT\n\tif (adapter->chip_id == HALMAC_CHIP_ID_8822C) {\n\t\tinit_adapter_param_win8822c(adapter);\n\t\tstatus = mount_api_win8822c(adapter);\n\t}\n#endif\n\n#if HALMAC_8812F_SUPPORT\n\tif (adapter->chip_id == HALMAC_CHIP_ID_8812F) {\n\t\tinit_adapter_param_win8812f(adapter);\n\t\tstatus = mount_api_win8812f(adapter);\n\t}\n#endif\n\n#endif\n\t*halmac_api = (struct halmac_api *)adapter->halmac_api;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn status;\n}\n\n/**\n * halmac_halt_api() - stop halmac_api action\n * @adapter : the adapter of halmac\n * Author : Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nhalmac_halt_api(struct halmac_adapter *adapter)\n{\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tadapter->halmac_state.api_state = HALMAC_API_STATE_HALT;\n\n\tPLTFM_MSG_TRACE(\"[TRACE]%s <===\\n\", __func__);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * halmac_deinit_adapter() - deinit halmac adapter\n * @adapter : the adapter of halmac\n * Author : KaiYuan Chang / Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nhalmac_deinit_adapter(struct halmac_adapter *adapter)\n{\n\tPLTFM_MSG_TRACE(\"[TRACE]%s ===>\\n\", __func__);\n\n\tPLTFM_MUTEX_DEINIT(&adapter->efuse_mutex);\n\tPLTFM_MUTEX_DEINIT(&adapter->h2c_seq_mutex);\n\tPLTFM_MUTEX_DEINIT(&adapter->sdio_indir_mutex);\n\n\tif (adapter->efuse_map) {\n\t\tPLTFM_FREE(adapter->efuse_map, adapter->hw_cfg_info.efuse_size);\n\t\tadapter->efuse_map = (u8 *)NULL;\n\t}\n\n\tif (adapter->sdio_fs.macid_map) {\n\t\tPLTFM_FREE(adapter->sdio_fs.macid_map,\n\t\t\t   adapter->sdio_fs.macid_map_size);\n\t\tadapter->sdio_fs.macid_map = (u8 *)NULL;\n\t}\n\n\tif (adapter->halmac_state.psd_state.data) {\n\t\tPLTFM_FREE(adapter->halmac_state.psd_state.data,\n\t\t\t   adapter->halmac_state.psd_state.data_size);\n\t\tadapter->halmac_state.psd_state.data = (u8 *)NULL;\n\t}\n\n\tif (adapter->halmac_api) {\n\t\tPLTFM_FREE(adapter->halmac_api, sizeof(struct halmac_api));\n\t\tadapter->halmac_api = NULL;\n\t}\n\n\tPLTFM_FREE(adapter, sizeof(*adapter));\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nchk_pltfm_api(void *drv_adapter, enum halmac_interface intf,\n\t      struct halmac_platform_api *pltfm_api)\n{\n\tif (!pltfm_api)\n\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\n\tif (!pltfm_api->MSG_PRINT)\n\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\n\tif (intf == HALMAC_INTERFACE_SDIO) {\n\t\tif (!pltfm_api->SDIO_CMD52_READ) {\n\t\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]sdio-r\\n\");\n\t\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t\t}\n\t\tif (!pltfm_api->SDIO_CMD53_READ_8) {\n\t\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]sdio-r8\\n\");\n\t\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t\t}\n\t\tif (!pltfm_api->SDIO_CMD53_READ_16) {\n\t\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]sdio-r16\\n\");\n\t\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t\t}\n\t\tif (!pltfm_api->SDIO_CMD53_READ_32) {\n\t\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]sdio-r32\\n\");\n\t\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t\t}\n\t\tif (!pltfm_api->SDIO_CMD53_READ_N) {\n\t\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]sdio-rn\\n\");\n\t\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t\t}\n\t\tif (!pltfm_api->SDIO_CMD52_WRITE) {\n\t\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]sdio-w\\n\");\n\t\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t\t}\n\t\tif (!pltfm_api->SDIO_CMD53_WRITE_8) {\n\t\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]sdio-w8\\n\");\n\t\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t\t}\n\t\tif (!pltfm_api->SDIO_CMD53_WRITE_16) {\n\t\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]sdio-w16\\n\");\n\t\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t\t}\n\t\tif (!pltfm_api->SDIO_CMD53_WRITE_32) {\n\t\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]sdio-w32\\n\");\n\t\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t\t}\n\t\tif (!pltfm_api->SDIO_CMD52_CIA_READ) {\n\t\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]sdio-cia\\n\");\n\t\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t\t}\n\t}\n\n\tif (intf == HALMAC_INTERFACE_USB || intf == HALMAC_INTERFACE_PCIE) {\n\t\tif (!pltfm_api->REG_READ_8) {\n\t\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]reg-r8\\n\");\n\t\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t\t}\n\t\tif (!pltfm_api->REG_READ_16) {\n\t\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]reg-r16\\n\");\n\t\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t\t}\n\t\tif (!pltfm_api->REG_READ_32) {\n\t\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]reg-r32\\n\");\n\t\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t\t}\n\t\tif (!pltfm_api->REG_WRITE_8) {\n\t\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]reg-w8\\n\");\n\t\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t\t}\n\t\tif (!pltfm_api->REG_WRITE_16) {\n\t\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]reg-w16\\n\");\n\t\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t\t}\n\t\tif (!pltfm_api->REG_WRITE_32) {\n\t\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]reg-w32\\n\");\n\t\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t\t}\n\t}\n\n\tif (!pltfm_api->RTL_FREE) {\n\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]mem-free\\n\");\n\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t}\n\n\tif (!pltfm_api->RTL_MALLOC) {\n\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]mem-malloc\\n\");\n\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t}\n\tif (!pltfm_api->RTL_MEMCPY) {\n\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]mem-cpy\\n\");\n\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t}\n\tif (!pltfm_api->RTL_MEMSET) {\n\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]mem-set\\n\");\n\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t}\n\tif (!pltfm_api->RTL_DELAY_US) {\n\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]time-delay\\n\");\n\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t}\n\n\tif (!pltfm_api->MUTEX_INIT) {\n\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]mutex-init\\n\");\n\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t}\n\tif (!pltfm_api->MUTEX_DEINIT) {\n\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]mutex-deinit\\n\");\n\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t}\n\tif (!pltfm_api->MUTEX_LOCK) {\n\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]mutex-lock\\n\");\n\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t}\n\tif (!pltfm_api->MUTEX_UNLOCK) {\n\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]mutex-unlock\\n\");\n\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t}\n\tif (!pltfm_api->EVENT_INDICATION) {\n\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]event-indication\\n\");\n\t\treturn HALMAC_RET_PLATFORM_API_NULL;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n/**\n * halmac_get_version() - get HALMAC version\n * @version : return version of major, prototype and minor information\n * Author : KaiYuan Chang / Ivan Lin\n * Return : enum halmac_ret_status\n * More details of status code can be found in prototype document\n */\nenum halmac_ret_status\nhalmac_get_version(struct halmac_ver *version)\n{\n\tversion->major_ver = (u8)HALMAC_MAJOR_VER;\n\tversion->prototype_ver = (u8)HALMAC_PROTOTYPE_VER;\n\tversion->minor_ver = (u8)HALMAC_MINOR_VER;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic enum halmac_ret_status\nget_chip_info(void *drv_adapter, struct halmac_platform_api *pltfm_api,\n\t      enum halmac_interface intf, struct halmac_adapter *adapter)\n{\n\tu8 chip_id;\n\tu8 chip_ver;\n\tu32 cnt;\n\n\tif (adapter->intf == HALMAC_INTERFACE_SDIO) {\n\t\tpltfm_reg_w8_sdio(drv_adapter, pltfm_api, REG_SDIO_HSUS_CTRL,\n\t\t\t\t  pltfm_reg_r8_sdio(drv_adapter, pltfm_api,\n\t\t\t\t\t\t    REG_SDIO_HSUS_CTRL) &\n\t\t\t\t\t\t    ~(BIT(0)));\n\n\t\tcnt = 10000;\n\t\twhile (!(pltfm_reg_r8_sdio(drv_adapter, pltfm_api,\n\t\t\t\t\t   REG_SDIO_HSUS_CTRL) & BIT(1))) {\n\t\t\tcnt--;\n\t\t\tif (cnt == 0)\n\t\t\t\treturn HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;\n\t\t}\n\n\t\tchip_id = pltfm_reg_r_indir_sdio(drv_adapter, pltfm_api,\n\t\t\t\t\t\t REG_SYS_CFG2);\n\t\tchip_ver = pltfm_reg_r_indir_sdio(drv_adapter, pltfm_api,\n\t\t\t\t\t\t  REG_SYS_CFG1 + 1) >> 4;\n\t} else {\n\t\tchip_id = pltfm_api->REG_READ_8(drv_adapter, REG_SYS_CFG2);\n\t\tchip_ver = pltfm_api->REG_READ_8(drv_adapter,\n\t\t\t\t\t\t REG_SYS_CFG1 + 1) >> 4;\n\t}\n\n\tadapter->chip_ver = (enum halmac_chip_ver)chip_ver;\n\n\tif (chip_id == CHIP_ID_HW_DEF_8822B) {\n\t\tadapter->chip_id = HALMAC_CHIP_ID_8822B;\n\t} else if (chip_id == CHIP_ID_HW_DEF_8821C) {\n\t\tadapter->chip_id = HALMAC_CHIP_ID_8821C;\n\t} else if (chip_id == CHIP_ID_HW_DEF_8814B) {\n\t\tadapter->chip_id = HALMAC_CHIP_ID_8814B;\n\t} else if (chip_id == CHIP_ID_HW_DEF_8197F) {\n\t\tadapter->chip_id = HALMAC_CHIP_ID_8197F;\n\t} else if (chip_id == CHIP_ID_HW_DEF_8822C) {\n\t\tadapter->chip_id = HALMAC_CHIP_ID_8822C;\n\t} else if (chip_id == CHIP_ID_HW_DEF_8812F) {\n\t\tadapter->chip_id = HALMAC_CHIP_ID_8812F;\n\t} else {\n\t\tadapter->chip_id = HALMAC_CHIP_ID_UNDEFINE;\n\t\tPLTFM_MSG_ERR(\"[ERR]Chip id is undefined\\n\");\n\t\treturn HALMAC_RET_CHIP_NOT_SUPPORT;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic u8\npltfm_reg_r8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,\n\t\t  u32 offset)\n{\n\tu8 value8;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tif (0 == (offset & 0xFFFF0000))\n\t\toffset |= WLAN_IOREG_OFFSET;\n\n\tstatus = cnv_to_sdio_bus_offset(&offset);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tvalue8 = pltfm_api->SDIO_CMD52_READ(drv_adapter, offset);\n\n\treturn value8;\n}\n\nstatic enum halmac_ret_status\npltfm_reg_w8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,\n\t\t  u32 offset, u8 data)\n{\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tif (0 == (offset & 0xFFFF0000))\n\t\toffset |= WLAN_IOREG_OFFSET;\n\n\tstatus = cnv_to_sdio_bus_offset(&offset);\n\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tpltfm_api->SDIO_CMD52_WRITE(drv_adapter, offset, data);\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\nstatic u8\npltfm_reg_r_indir_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,\n\t\t       u32 offset)\n{\n\tu8 value8, tmp, cnt = 50;\n\tu32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;\n\tu32 reg_data = REG_SDIO_INDIRECT_REG_DATA;\n\tenum halmac_ret_status status = HALMAC_RET_SUCCESS;\n\n\tstatus = cnv_to_sdio_bus_offset(&reg_cfg);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\tstatus = cnv_to_sdio_bus_offset(&reg_data);\n\tif (status != HALMAC_RET_SUCCESS)\n\t\treturn status;\n\n\tpltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg, (u8)offset);\n\tpltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg + 1,\n\t\t\t\t    (u8)(offset >> 8));\n\tpltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg + 2,\n\t\t\t\t    (u8)(BIT(3) | BIT(4)));\n\n\tdo {\n\t\ttmp = pltfm_api->SDIO_CMD52_READ(drv_adapter, reg_cfg + 2);\n\t\tcnt--;\n\t} while (((tmp & BIT(4)) == 0) && (cnt > 0));\n\n\tif (((cnt & BIT(4)) == 0) && cnt == 0)\n\t\tpltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,\n\t\t\t\t     HALMAC_DBG_ERR, \"[ERR]sdio indir read\\n\");\n\n\tvalue8 = pltfm_api->SDIO_CMD52_READ(drv_adapter, reg_data);\n\n\treturn value8;\n}\n\n/*Note: copy from cnv_to_sdio_bus_offset_88xx*/\nstatic enum halmac_ret_status\ncnv_to_sdio_bus_offset(u32 *offset)\n{\n\tswitch ((*offset) & 0xFFFF0000) {\n\tcase WLAN_IOREG_OFFSET:\n\t\t*offset &= HALMAC_WLAN_MAC_REG_MSK;\n\t\t*offset |= HALMAC_SDIO_CMD_ADDR_MAC_REG << 13;\n\t\tbreak;\n\tcase SDIO_LOCAL_OFFSET:\n\t\t*offset &= HALMAC_SDIO_LOCAL_MSK;\n\t\t*offset |= HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13;\n\t\tbreak;\n\tdefault:\n\t\t*offset = 0xFFFFFFFF;\n\t\treturn HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL;\n\t}\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n"
  },
  {
    "path": "hal/halmac/halmac_api.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_API_H_\n#define _HALMAC_API_H_\n\n#define HALMAC_SVN_VER  \"11692M\"\n\n#define HALMAC_MAJOR_VER        0x0001\n#define HALMAC_PROTOTYPE_VER    0x0005\n#define HALMAC_MINOR_VER        0x0014\n#define HALMAC_PATCH_VER        0x0030\n\n#define HALMAC_88XX_SUPPORT\t(HALMAC_8821C_SUPPORT || \\\n\t\t\t\t HALMAC_8822B_SUPPORT || \\\n\t\t\t\t HALMAC_8822C_SUPPORT || \\\n\t\t\t\t HALMAC_8812F_SUPPORT)\n\n#define HALMAC_88XX_V1_SUPPORT\tHALMAC_8814B_SUPPORT\n\n#include \"halmac_2_platform.h\"\n#include \"halmac_type.h\"\n#include \"halmac_hw_cfg.h\"\n#include \"halmac_usb_reg.h\"\n#include \"halmac_sdio_reg.h\"\n#include \"halmac_pcie_reg.h\"\n#include \"halmac_bit2.h\"\n#include \"halmac_reg2.h\"\n\n#if HALMAC_PLATFORM_TESTPROGRAM\n#include \"halmac_type_testprogram.h\"\n#endif\n\n#ifndef HALMAC_USE_TYPEDEF\n#define HALMAC_USE_TYPEDEF\t1\n#endif\n\n#if HALMAC_USE_TYPEDEF\n#include \"halmac_typedef.h\"\n#endif\n\n#if HALMAC_8822B_SUPPORT\n#include \"halmac_reg_8822b.h\"\n#include \"halmac_bit_8822b.h\"\n#endif\n\n#if HALMAC_8821C_SUPPORT\n#include \"halmac_reg_8821c.h\"\n#include \"halmac_bit_8821c.h\"\n#endif\n\n#if HALMAC_8814B_SUPPORT\n#include \"halmac_reg_8814b.h\"\n#include \"halmac_bit_8814b.h\"\n#endif\n\n#if HALMAC_8822C_SUPPORT\n#include \"halmac_reg_8822c.h\"\n#include \"halmac_bit_8822c.h\"\n#endif\n\n#if (HALMAC_PLATFORM_WINDOWS || HALMAC_PLATFORM_LINUX)\n#include \"halmac_tx_desc_nic.h\"\n#include \"halmac_tx_desc_buffer_nic.h\"\n#include \"halmac_tx_desc_ie_nic.h\"\n#include \"halmac_rx_desc_nic.h\"\n#include \"halmac_tx_bd_nic.h\"\n#include \"halmac_rx_bd_nic.h\"\n#include \"halmac_fw_offload_c2h_nic.h\"\n#include \"halmac_fw_offload_h2c_nic.h\"\n#include \"halmac_h2c_extra_info_nic.h\"\n#include \"halmac_original_c2h_nic.h\"\n#include \"halmac_original_h2c_nic.h\"\n#endif\n\n#if (HALMAC_PLATFORM_AP)\n#include \"halmac_rx_desc_ap.h\"\n#include \"halmac_tx_desc_ap.h\"\n#include \"halmac_tx_desc_buffer_ap.h\"\n#include \"halmac_tx_desc_ie_ap.h\"\n#include \"halmac_fw_offload_c2h_ap.h\"\n#include \"halmac_fw_offload_h2c_ap.h\"\n#include \"halmac_h2c_extra_info_ap.h\"\n#include \"halmac_original_c2h_ap.h\"\n#include \"halmac_original_h2c_ap.h\"\n#endif\n\n#include \"halmac_tx_desc_chip.h\"\n#include \"halmac_rx_desc_chip.h\"\n#include \"halmac_tx_desc_buffer_chip.h\"\n#include \"halmac_tx_desc_ie_chip.h\"\n\nenum halmac_ret_status\nhalmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api,\n\t\t    enum halmac_interface intf,\n\t\t    struct halmac_adapter **halmac_adapter,\n\t\t    struct halmac_api **halmac_api);\n\nenum halmac_ret_status\nhalmac_deinit_adapter(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\nhalmac_halt_api(struct halmac_adapter *adapter);\n\nenum halmac_ret_status\nhalmac_get_version(struct halmac_ver *version);\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_bit2.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef __RTL_WLAN_BITDEF_H__\n#define __RTL_WLAN_BITDEF_H__\n\n#include \"halmac_hw_cfg.h\"\n\n#define CPU_OPT_WIDTH 0x1F\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n#define BIT_WRITE_ENABLE BIT(31)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n#define BIT_MEM_RMV_SIGN BIT(31)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define BIT_SHIFT_LLTE_RWM 30\n#define BIT_MASK_LLTE_RWM 0x3\n#define BIT_LLTE_RWM(x) (((x) & BIT_MASK_LLTE_RWM) << BIT_SHIFT_LLTE_RWM)\n#define BITS_LLTE_RWM (BIT_MASK_LLTE_RWM << BIT_SHIFT_LLTE_RWM)\n#define BIT_CLEAR_LLTE_RWM(x) ((x) & (~BITS_LLTE_RWM))\n#define BIT_GET_LLTE_RWM(x) (((x) >> BIT_SHIFT_LLTE_RWM) & BIT_MASK_LLTE_RWM)\n#define BIT_SET_LLTE_RWM(x, v) (BIT_CLEAR_LLTE_RWM(x) | BIT_LLTE_RWM(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n#define BIT_MEM_RMV_2PRF1 BIT(29)\n#define BIT_MEM_RMV_2PRF0 BIT(28)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_SHIFT_GTAB_ID 28\n#define BIT_MASK_GTAB_ID 0x7\n#define BIT_GTAB_ID(x) (((x) & BIT_MASK_GTAB_ID) << BIT_SHIFT_GTAB_ID)\n#define BITS_GTAB_ID (BIT_MASK_GTAB_ID << BIT_SHIFT_GTAB_ID)\n#define BIT_CLEAR_GTAB_ID(x) ((x) & (~BITS_GTAB_ID))\n#define BIT_GET_GTAB_ID(x) (((x) >> BIT_SHIFT_GTAB_ID) & BIT_MASK_GTAB_ID)\n#define BIT_SET_GTAB_ID(x, v) (BIT_CLEAR_GTAB_ID(x) | BIT_GTAB_ID(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n#define BIT_MULRW BIT(27)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n#define BIT_MEM_RMV_1PRF1 BIT(27)\n#define BIT_MEM_RMV_1PRF0 BIT(26)\n#define BIT_MEM_RMV_1PSR BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n#define BIT_SHIFT_MBIDCAM_ADDR 24\n#define BIT_MASK_MBIDCAM_ADDR 0x1f\n#define BIT_MBIDCAM_ADDR(x)                                                    \\\n\t(((x) & BIT_MASK_MBIDCAM_ADDR) << BIT_SHIFT_MBIDCAM_ADDR)\n#define BITS_MBIDCAM_ADDR (BIT_MASK_MBIDCAM_ADDR << BIT_SHIFT_MBIDCAM_ADDR)\n#define BIT_CLEAR_MBIDCAM_ADDR(x) ((x) & (~BITS_MBIDCAM_ADDR))\n#define BIT_GET_MBIDCAM_ADDR(x)                                                \\\n\t(((x) >> BIT_SHIFT_MBIDCAM_ADDR) & BIT_MASK_MBIDCAM_ADDR)\n#define BIT_SET_MBIDCAM_ADDR(x, v)                                             \\\n\t(BIT_CLEAR_MBIDCAM_ADDR(x) | BIT_MBIDCAM_ADDR(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n#define BIT_MEM_RMV_ROM BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n#define BIT_CPRST BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define BIT_CTS_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define BIT_SHIFT_R_OFDM_LEN_V1 16\n#define BIT_MASK_R_OFDM_LEN_V1 0xffff\n#define BIT_R_OFDM_LEN_V1(x)                                                   \\\n\t(((x) & BIT_MASK_R_OFDM_LEN_V1) << BIT_SHIFT_R_OFDM_LEN_V1)\n#define BITS_R_OFDM_LEN_V1 (BIT_MASK_R_OFDM_LEN_V1 << BIT_SHIFT_R_OFDM_LEN_V1)\n#define BIT_CLEAR_R_OFDM_LEN_V1(x) ((x) & (~BITS_R_OFDM_LEN_V1))\n#define BIT_GET_R_OFDM_LEN_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_R_OFDM_LEN_V1) & BIT_MASK_R_OFDM_LEN_V1)\n#define BIT_SET_R_OFDM_LEN_V1(x, v)                                            \\\n\t(BIT_CLEAR_R_OFDM_LEN_V1(x) | BIT_R_OFDM_LEN_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_SHIFT_COUNTER_BASE 16\n#define BIT_MASK_COUNTER_BASE 0x1fff\n#define BIT_COUNTER_BASE(x)                                                    \\\n\t(((x) & BIT_MASK_COUNTER_BASE) << BIT_SHIFT_COUNTER_BASE)\n#define BITS_COUNTER_BASE (BIT_MASK_COUNTER_BASE << BIT_SHIFT_COUNTER_BASE)\n#define BIT_CLEAR_COUNTER_BASE(x) ((x) & (~BITS_COUNTER_BASE))\n#define BIT_GET_COUNTER_BASE(x)                                                \\\n\t(((x) >> BIT_SHIFT_COUNTER_BASE) & BIT_MASK_COUNTER_BASE)\n#define BIT_SET_COUNTER_BASE(x, v)                                             \\\n\t(BIT_CLEAR_COUNTER_BASE(x) | BIT_COUNTER_BASE(v))\n\n#define BIT_SHIFT_AGG_VALUE2 16\n#define BIT_MASK_AGG_VALUE2 0x7f\n#define BIT_AGG_VALUE2(x) (((x) & BIT_MASK_AGG_VALUE2) << BIT_SHIFT_AGG_VALUE2)\n#define BITS_AGG_VALUE2 (BIT_MASK_AGG_VALUE2 << BIT_SHIFT_AGG_VALUE2)\n#define BIT_CLEAR_AGG_VALUE2(x) ((x) & (~BITS_AGG_VALUE2))\n#define BIT_GET_AGG_VALUE2(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AGG_VALUE2) & BIT_MASK_AGG_VALUE2)\n#define BIT_SET_AGG_VALUE2(x, v) (BIT_CLEAR_AGG_VALUE2(x) | BIT_AGG_VALUE2(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_WMAC_SRCH_FIFOFULL BIT(15)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1 BIT(15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_SHIFT_XTAL_DRV_RF1 13\n#define BIT_MASK_XTAL_DRV_RF1 0x3\n#define BIT_XTAL_DRV_RF1(x)                                                    \\\n\t(((x) & BIT_MASK_XTAL_DRV_RF1) << BIT_SHIFT_XTAL_DRV_RF1)\n#define BITS_XTAL_DRV_RF1 (BIT_MASK_XTAL_DRV_RF1 << BIT_SHIFT_XTAL_DRV_RF1)\n#define BIT_CLEAR_XTAL_DRV_RF1(x) ((x) & (~BITS_XTAL_DRV_RF1))\n#define BIT_GET_XTAL_DRV_RF1(x)                                                \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_RF1) & BIT_MASK_XTAL_DRV_RF1)\n#define BIT_SET_XTAL_DRV_RF1(x, v)                                             \\\n\t(BIT_CLEAR_XTAL_DRV_RF1(x) | BIT_XTAL_DRV_RF1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n#define BIT_DISABLE_B0 BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define BIT_ATIMEND BIT(12)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_SHIFT_GTAB_ID_V1 12\n#define BIT_MASK_GTAB_ID_V1 0x7\n#define BIT_GTAB_ID_V1(x) (((x) & BIT_MASK_GTAB_ID_V1) << BIT_SHIFT_GTAB_ID_V1)\n#define BITS_GTAB_ID_V1 (BIT_MASK_GTAB_ID_V1 << BIT_SHIFT_GTAB_ID_V1)\n#define BIT_CLEAR_GTAB_ID_V1(x) ((x) & (~BITS_GTAB_ID_V1))\n#define BIT_GET_GTAB_ID_V1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_V1) & BIT_MASK_GTAB_ID_V1)\n#define BIT_SET_GTAB_ID_V1(x, v) (BIT_CLEAR_GTAB_ID_V1(x) | BIT_GTAB_ID_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define BIT_SHIFT_WATCH_DOG_RECORD_V1 10\n#define BIT_MASK_WATCH_DOG_RECORD_V1 0x3fff\n#define BIT_WATCH_DOG_RECORD_V1(x)                                             \\\n\t(((x) & BIT_MASK_WATCH_DOG_RECORD_V1) << BIT_SHIFT_WATCH_DOG_RECORD_V1)\n#define BITS_WATCH_DOG_RECORD_V1                                               \\\n\t(BIT_MASK_WATCH_DOG_RECORD_V1 << BIT_SHIFT_WATCH_DOG_RECORD_V1)\n#define BIT_CLEAR_WATCH_DOG_RECORD_V1(x) ((x) & (~BITS_WATCH_DOG_RECORD_V1))\n#define BIT_GET_WATCH_DOG_RECORD_V1(x)                                         \\\n\t(((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1) & BIT_MASK_WATCH_DOG_RECORD_V1)\n#define BIT_SET_WATCH_DOG_RECORD_V1(x, v)                                      \\\n\t(BIT_CLEAR_WATCH_DOG_RECORD_V1(x) | BIT_WATCH_DOG_RECORD_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define BIT_R_8051_SPD BIT(9)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define BIT_R_IO_TIMEOUT_FLAG_V1 BIT(9)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_EN_RTS_REQ BIT(9)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n#define BIT_EN_WATCH_DOG_V1 BIT(8)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_EN_EDCA_REQ BIT(8)\n\n#define BIT_SHIFT_AGG_VALUE1 8\n#define BIT_MASK_AGG_VALUE1 0x7f\n#define BIT_AGG_VALUE1(x) (((x) & BIT_MASK_AGG_VALUE1) << BIT_SHIFT_AGG_VALUE1)\n#define BITS_AGG_VALUE1 (BIT_MASK_AGG_VALUE1 << BIT_SHIFT_AGG_VALUE1)\n#define BIT_CLEAR_AGG_VALUE1(x) ((x) & (~BITS_AGG_VALUE1))\n#define BIT_GET_AGG_VALUE1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AGG_VALUE1) & BIT_MASK_AGG_VALUE1)\n#define BIT_SET_AGG_VALUE1(x, v) (BIT_CLEAR_AGG_VALUE1(x) | BIT_AGG_VALUE1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_DIS_TXDMA_PRE BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define BIT_RAM_DL_SEL BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_EN_PTCL_REQ BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_DIS_RXDMA_PRE BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define BIT_WINTINI_RDY BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_EN_SCH_REQ BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_CLR_HGQ_REQ_BLOCK BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_SHIFT_I2C_M_BUS_GNT_FW 4\n#define BIT_MASK_I2C_M_BUS_GNT_FW 0x7\n#define BIT_I2C_M_BUS_GNT_FW(x)                                                \\\n\t(((x) & BIT_MASK_I2C_M_BUS_GNT_FW) << BIT_SHIFT_I2C_M_BUS_GNT_FW)\n#define BITS_I2C_M_BUS_GNT_FW                                                  \\\n\t(BIT_MASK_I2C_M_BUS_GNT_FW << BIT_SHIFT_I2C_M_BUS_GNT_FW)\n#define BIT_CLEAR_I2C_M_BUS_GNT_FW(x) ((x) & (~BITS_I2C_M_BUS_GNT_FW))\n#define BIT_GET_I2C_M_BUS_GNT_FW(x)                                            \\\n\t(((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW) & BIT_MASK_I2C_M_BUS_GNT_FW)\n#define BIT_SET_I2C_M_BUS_GNT_FW(x, v)                                         \\\n\t(BIT_CLEAR_I2C_M_BUS_GNT_FW(x) | BIT_I2C_M_BUS_GNT_FW(v))\n\n#define BIT_I2C_M_GNT_FW BIT(3)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define BIT_SYM_LPS_STATUS BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_TXFLAG_EXIT_L1_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define BIT_SYM_HCI_TXDMA_BUSY BIT(2)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_DATA_FW_STS_FILTER BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n#define BIT_EN_RXDMA_ALIGN_V1 BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_SHIFT_I2C_M_SPEED 1\n#define BIT_MASK_I2C_M_SPEED 0x3\n#define BIT_I2C_M_SPEED(x)                                                     \\\n\t(((x) & BIT_MASK_I2C_M_SPEED) << BIT_SHIFT_I2C_M_SPEED)\n#define BITS_I2C_M_SPEED (BIT_MASK_I2C_M_SPEED << BIT_SHIFT_I2C_M_SPEED)\n#define BIT_CLEAR_I2C_M_SPEED(x) ((x) & (~BITS_I2C_M_SPEED))\n#define BIT_GET_I2C_M_SPEED(x)                                                 \\\n\t(((x) >> BIT_SHIFT_I2C_M_SPEED) & BIT_MASK_I2C_M_SPEED)\n#define BIT_SET_I2C_M_SPEED(x, v)                                              \\\n\t(BIT_CLEAR_I2C_M_SPEED(x) | BIT_I2C_M_SPEED(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_CTRL_FW_STS_FILTER BIT(1)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n#define BIT_AFE_MBIAS BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT)\n\n#define BIT_SHIFT_MDIO_REG_ADDR 0\n#define BIT_MASK_MDIO_REG_ADDR 0x1f\n#define BIT_MDIO_REG_ADDR(x)                                                   \\\n\t(((x) & BIT_MASK_MDIO_REG_ADDR) << BIT_SHIFT_MDIO_REG_ADDR)\n#define BITS_MDIO_REG_ADDR (BIT_MASK_MDIO_REG_ADDR << BIT_SHIFT_MDIO_REG_ADDR)\n#define BIT_CLEAR_MDIO_REG_ADDR(x) ((x) & (~BITS_MDIO_REG_ADDR))\n#define BIT_GET_MDIO_REG_ADDR(x)                                               \\\n\t(((x) >> BIT_SHIFT_MDIO_REG_ADDR) & BIT_MASK_MDIO_REG_ADDR)\n#define BIT_SET_MDIO_REG_ADDR(x, v)                                            \\\n\t(BIT_CLEAR_MDIO_REG_ADDR(x) | BIT_MDIO_REG_ADDR(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n#define BIT_EN_TXDMA_ALIGN_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_SHIFT_RXFF0_BNDY_V2 0\n#define BIT_MASK_RXFF0_BNDY_V2 0x3ffff\n#define BIT_RXFF0_BNDY_V2(x)                                                   \\\n\t(((x) & BIT_MASK_RXFF0_BNDY_V2) << BIT_SHIFT_RXFF0_BNDY_V2)\n#define BITS_RXFF0_BNDY_V2 (BIT_MASK_RXFF0_BNDY_V2 << BIT_SHIFT_RXFF0_BNDY_V2)\n#define BIT_CLEAR_RXFF0_BNDY_V2(x) ((x) & (~BITS_RXFF0_BNDY_V2))\n#define BIT_GET_RXFF0_BNDY_V2(x)                                               \\\n\t(((x) >> BIT_SHIFT_RXFF0_BNDY_V2) & BIT_MASK_RXFF0_BNDY_V2)\n#define BIT_SET_RXFF0_BNDY_V2(x, v)                                            \\\n\t(BIT_CLEAR_RXFF0_BNDY_V2(x) | BIT_RXFF0_BNDY_V2(v))\n\n#define BIT_SHIFT_RXFF0_RDPTR_V2 0\n#define BIT_MASK_RXFF0_RDPTR_V2 0x3ffff\n#define BIT_RXFF0_RDPTR_V2(x)                                                  \\\n\t(((x) & BIT_MASK_RXFF0_RDPTR_V2) << BIT_SHIFT_RXFF0_RDPTR_V2)\n#define BITS_RXFF0_RDPTR_V2                                                    \\\n\t(BIT_MASK_RXFF0_RDPTR_V2 << BIT_SHIFT_RXFF0_RDPTR_V2)\n#define BIT_CLEAR_RXFF0_RDPTR_V2(x) ((x) & (~BITS_RXFF0_RDPTR_V2))\n#define BIT_GET_RXFF0_RDPTR_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_RXFF0_RDPTR_V2) & BIT_MASK_RXFF0_RDPTR_V2)\n#define BIT_SET_RXFF0_RDPTR_V2(x, v)                                           \\\n\t(BIT_CLEAR_RXFF0_RDPTR_V2(x) | BIT_RXFF0_RDPTR_V2(v))\n\n#define BIT_SHIFT_RXFF0_WTPTR_V2 0\n#define BIT_MASK_RXFF0_WTPTR_V2 0x3ffff\n#define BIT_RXFF0_WTPTR_V2(x)                                                  \\\n\t(((x) & BIT_MASK_RXFF0_WTPTR_V2) << BIT_SHIFT_RXFF0_WTPTR_V2)\n#define BITS_RXFF0_WTPTR_V2                                                    \\\n\t(BIT_MASK_RXFF0_WTPTR_V2 << BIT_SHIFT_RXFF0_WTPTR_V2)\n#define BIT_CLEAR_RXFF0_WTPTR_V2(x) ((x) & (~BITS_RXFF0_WTPTR_V2))\n#define BIT_GET_RXFF0_WTPTR_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_RXFF0_WTPTR_V2) & BIT_MASK_RXFF0_WTPTR_V2)\n#define BIT_SET_RXFF0_WTPTR_V2(x, v)                                           \\\n\t(BIT_CLEAR_RXFF0_WTPTR_V2(x) | BIT_RXFF0_WTPTR_V2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_SHIFT_AGG_VALUE0 0\n#define BIT_MASK_AGG_VALUE0 0x7f\n#define BIT_AGG_VALUE0(x) (((x) & BIT_MASK_AGG_VALUE0) << BIT_SHIFT_AGG_VALUE0)\n#define BITS_AGG_VALUE0 (BIT_MASK_AGG_VALUE0 << BIT_SHIFT_AGG_VALUE0)\n#define BIT_CLEAR_AGG_VALUE0(x) ((x) & (~BITS_AGG_VALUE0))\n#define BIT_GET_AGG_VALUE0(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AGG_VALUE0) & BIT_MASK_AGG_VALUE0)\n#define BIT_SET_AGG_VALUE0(x, v) (BIT_CLEAR_AGG_VALUE0(x) | BIT_AGG_VALUE0(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_SHIFT_BW_CFG 0\n#define BIT_MASK_BW_CFG 0x3\n#define BIT_BW_CFG(x) (((x) & BIT_MASK_BW_CFG) << BIT_SHIFT_BW_CFG)\n#define BITS_BW_CFG (BIT_MASK_BW_CFG << BIT_SHIFT_BW_CFG)\n#define BIT_CLEAR_BW_CFG(x) ((x) & (~BITS_BW_CFG))\n#define BIT_GET_BW_CFG(x) (((x) >> BIT_SHIFT_BW_CFG) & BIT_MASK_BW_CFG)\n#define BIT_SET_BW_CFG(x, v) (BIT_CLEAR_BW_CFG(x) | BIT_BW_CFG(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_I2C_M_UNLOCK BIT(0)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define BIT_MGNT_FW_STS_FILTER BIT(0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n#define BIT_ISO_MD2PP BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TX_CTRL\t\t\t(Offset 0x10250000) */\n\n#define BIT_SHIFT_SDIO_INT_TIMEOUT 16\n#define BIT_MASK_SDIO_INT_TIMEOUT 0xffff\n#define BIT_SDIO_INT_TIMEOUT(x)                                                \\\n\t(((x) & BIT_MASK_SDIO_INT_TIMEOUT) << BIT_SHIFT_SDIO_INT_TIMEOUT)\n#define BITS_SDIO_INT_TIMEOUT                                                  \\\n\t(BIT_MASK_SDIO_INT_TIMEOUT << BIT_SHIFT_SDIO_INT_TIMEOUT)\n#define BIT_CLEAR_SDIO_INT_TIMEOUT(x) ((x) & (~BITS_SDIO_INT_TIMEOUT))\n#define BIT_GET_SDIO_INT_TIMEOUT(x)                                            \\\n\t(((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT) & BIT_MASK_SDIO_INT_TIMEOUT)\n#define BIT_SET_SDIO_INT_TIMEOUT(x, v)                                         \\\n\t(BIT_CLEAR_SDIO_INT_TIMEOUT(x) | BIT_SDIO_INT_TIMEOUT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_PWC_EV12V BIT(15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_PWC_ON2EF BIT(15)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TX_CTRL\t\t\t(Offset 0x10250000) */\n\n#define BIT_IO_ERR_STATUS BIT(15)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_PWC_EBCOEB BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_PWC_EV25V BIT(14)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_PWC_EV2EF BIT(14)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TX_CTRL\t\t\t(Offset 0x10250000) */\n\n#define BIT_CMD53_W_MIX BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_PA33V_EN BIT(13)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TX_CTRL\t\t\t(Offset 0x10250000) */\n\n#define BIT_CMD53_TX_FORMAT BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_PA12V_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TX_CTRL\t\t\t(Offset 0x10250000) */\n\n#define BIT_CMD53_R_TIMEOUT_MASK BIT(12)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_PC_A15V BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_UA33V_EN BIT(11)\n#define BIT_UA12V_EN BIT(10)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TX_CTRL\t\t\t(Offset 0x10250000) */\n\n#define BIT_SHIFT_CMD53_R_TIMEOUT_UNIT 10\n#define BIT_MASK_CMD53_R_TIMEOUT_UNIT 0x3\n#define BIT_CMD53_R_TIMEOUT_UNIT(x)                                            \\\n\t(((x) & BIT_MASK_CMD53_R_TIMEOUT_UNIT)                                 \\\n\t << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT)\n#define BITS_CMD53_R_TIMEOUT_UNIT                                              \\\n\t(BIT_MASK_CMD53_R_TIMEOUT_UNIT << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT)\n#define BIT_CLEAR_CMD53_R_TIMEOUT_UNIT(x) ((x) & (~BITS_CMD53_R_TIMEOUT_UNIT))\n#define BIT_GET_CMD53_R_TIMEOUT_UNIT(x)                                        \\\n\t(((x) >> BIT_SHIFT_CMD53_R_TIMEOUT_UNIT) &                             \\\n\t BIT_MASK_CMD53_R_TIMEOUT_UNIT)\n#define BIT_SET_CMD53_R_TIMEOUT_UNIT(x, v)                                     \\\n\t(BIT_CLEAR_CMD53_R_TIMEOUT_UNIT(x) | BIT_CMD53_R_TIMEOUT_UNIT(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_AFE_OUTPUT_SIGNAL BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_RFDIO BIT(9)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TX_CTRL\t\t\t(Offset 0x10250000) */\n\n#define BIT_REPLY_ERRCRC_IN_DATA BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_EB2CORE BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_EF2PP BIT(8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TX_CTRL\t\t\t(Offset 0x10250000) */\n\n#define BIT_EN_CMD53_OVERLAP BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_DIOE BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_EXTIO BIT(7)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TX_CTRL\t\t\t(Offset 0x10250000) */\n\n#define BIT_REPLY_ERR_IN_R5 BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_DIOP BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_WLPON2PP BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TX_CTRL\t\t\t(Offset 0x10250000) */\n\n#define BIT_R18A_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_IP2MAC_WA2PP BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_WA2PP BIT(5)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TX_CTRL\t\t\t(Offset 0x10250000) */\n\n#define BIT_SDIO_CMD_FORCE_VLD BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_PD2CORE BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_PD2PP BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TX_CTRL\t\t\t(Offset 0x10250000) */\n\n#define BIT_INIT_CMD_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_PA2PCIE BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_PA2PD BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TX_CTRL\t\t\t(Offset 0x10250000) */\n\n#define BIT_RXINT_READ_MASK_DIS BIT(3)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SDIO_TX_CTRL\t\t\t(Offset 0x10250000) */\n\n#define BIT_EN_32K_TRANS BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_UD2CORE BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_UD2PP BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TX_CTRL\t\t\t(Offset 0x10250000) */\n\n#define BIT_EN_RXDMA_MASK_INT BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_HD2CORE BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_UA2USB BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_UA2UD BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TX_CTRL\t\t\t(Offset 0x10250000) */\n\n#define BIT_EN_MASK_TIMER BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_WD2PP BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_ISO_CTRL\t\t\t(Offset 0x0000) */\n\n#define BIT_ISO_WL2PP BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TX_CTRL\t\t\t(Offset 0x10250000) */\n\n#define BIT_CMD_ERR_STOP_INT_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_FUNC_EN\t\t\t\t(Offset 0x0002) */\n\n#define BIT_FEN_MREGEN BIT(15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_FUNC_EN\t\t\t\t(Offset 0x0002) */\n\n#define BIT_FEN_WLMACPON BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_FUNC_EN\t\t\t\t(Offset 0x0002) */\n\n#define BIT_FEN_HWPDN BIT(14)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_FUNC_EN\t\t\t\t(Offset 0x0002) */\n\n#define BIT_AIP_PD12_N BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_FUNC_EN\t\t\t\t(Offset 0x0002) */\n\n#define BIT_EN_25_1 BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_FUNC_EN\t\t\t\t(Offset 0x0002) */\n\n#define BIT_FEN_ELDR BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_FUNC_EN\t\t\t\t(Offset 0x0002) */\n\n#define BIT_FEN_DCORE BIT(11)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_FUNC_EN\t\t\t\t(Offset 0x0002) */\n\n#define BIT_FEN_WLMACPOF BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_FUNC_EN\t\t\t\t(Offset 0x0002) */\n\n#define BIT_FEN_CPUEN BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_FUNC_EN\t\t\t\t(Offset 0x0002) */\n\n#define BIT_FEN_DIOE BIT(9)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_FUNC_EN\t\t\t\t(Offset 0x0002) */\n\n#define BIT_FEN_EXTIO BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_FUNC_EN\t\t\t\t(Offset 0x0002) */\n\n#define BIT_FEN_PCIED BIT(8)\n#define BIT_FEN_PPLL BIT(7)\n#define BIT_FEN_PCIEA BIT(6)\n#define BIT_FEN_DIO_PCIE BIT(5)\n#define BIT_FEN_USBD BIT(4)\n#define BIT_FEN_UPLL BIT(3)\n#define BIT_FEN_USBA BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_FUNC_EN\t\t\t\t(Offset 0x0002) */\n\n#define BIT_FEN_BB_GLB_RSTN BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_FUNC_EN\t\t\t\t(Offset 0x0002) */\n\n#define BIT_FEN_WLPHYGLB BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_FUNC_EN\t\t\t\t(Offset 0x0002) */\n\n#define BIT_FEN_BBRSTB BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_FUNC_EN\t\t\t\t(Offset 0x0002) */\n\n#define BIT_FEN_WLPHYFUN BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_SOP_EABM BIT(31)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_SKP_ALD BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_SOP_ACKF BIT(30)\n#define BIT_SOP_ERCK BIT(29)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_SOP_ESWR BIT(28)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_SOP_AFEP BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_SOP_PWMM BIT(27)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_SOP_EPWM BIT(27)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_SOP_EECK BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_PMC_RATIO_BIT2 BIT(25)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_SOP_ANA_CLK_DIVISION_2 BIT(25)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_ROP_ENXT BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_SOP_EXTL BIT(24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_PMC_RATIO_BIT1 BIT(23)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_CHIPOFF_EN BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_SYM_OP_RING_12M BIT(22)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_DIS_USB3_SUS_ALD BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_ROP_SWPR BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_DIS_HW_LPLDM BIT(20)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_SOP_ALD BIT(20)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_OPT_SWRST_WLMCU BIT(19)\n#define BIT_RDY_SYSPWR BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_EN_WLON BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_APDM_HPDN BIT(15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_PMC_RATIO_BIT0 BIT(14)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_HSUS BIT(14)\n#define BIT_PDN_SEL BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_AFSM_PCIE_SUS_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_AFSM_WLSUS_EN BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_APFM_SWLPS BIT(10)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_APFM_SWLPS_EN BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_APFM_OFFMAC BIT(9)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_HW_AUTO_CTRL_EXT_SWR BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_APFN_ONMAC BIT(8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_USE_INTERNAL_SWR_AND_LDO BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_CHIP_PDN_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_BT_SUSEN BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_RDY_MACDIS BIT(6)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_PD_RF BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_RING_CLK_12M_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_CMD11_VOL_SWITCH\t\t(Offset 0x10250004) */\n\n#define BIT_SHIFT_CMD11_SEQ_END_DELAY 4\n#define BIT_MASK_CMD11_SEQ_END_DELAY 0xf\n#define BIT_CMD11_SEQ_END_DELAY(x)                                             \\\n\t(((x) & BIT_MASK_CMD11_SEQ_END_DELAY) << BIT_SHIFT_CMD11_SEQ_END_DELAY)\n#define BITS_CMD11_SEQ_END_DELAY                                               \\\n\t(BIT_MASK_CMD11_SEQ_END_DELAY << BIT_SHIFT_CMD11_SEQ_END_DELAY)\n#define BIT_CLEAR_CMD11_SEQ_END_DELAY(x) ((x) & (~BITS_CMD11_SEQ_END_DELAY))\n#define BIT_GET_CMD11_SEQ_END_DELAY(x)                                         \\\n\t(((x) >> BIT_SHIFT_CMD11_SEQ_END_DELAY) & BIT_MASK_CMD11_SEQ_END_DELAY)\n#define BIT_SET_CMD11_SEQ_END_DELAY(x, v)                                      \\\n\t(BIT_CLEAR_CMD11_SEQ_END_DELAY(x) | BIT_CMD11_SEQ_END_DELAY(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_ENPDN BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_PFM_WOWL BIT(3)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_SW_WAKE BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_PFM_LDKP BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_WL_HCI_ALD BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_ANA_CLK_DIVISION_2 BIT(1)\n\n#define BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL 1\n#define BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL 0x7\n#define BIT_CMD11_SEQ_SAMPLE_INTERVAL(x)                                       \\\n\t(((x) & BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL)                            \\\n\t << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL)\n#define BITS_CMD11_SEQ_SAMPLE_INTERVAL                                         \\\n\t(BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL                                    \\\n\t << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL)\n#define BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL(x)                                 \\\n\t((x) & (~BITS_CMD11_SEQ_SAMPLE_INTERVAL))\n#define BIT_GET_CMD11_SEQ_SAMPLE_INTERVAL(x)                                   \\\n\t(((x) >> BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL) &                        \\\n\t BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL)\n#define BIT_SET_CMD11_SEQ_SAMPLE_INTERVAL(x, v)                                \\\n\t(BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL(x) |                              \\\n\t BIT_CMD11_SEQ_SAMPLE_INTERVAL(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_PFM_ALDN BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_PW_CTRL\t\t\t\t(Offset 0x0004) */\n\n#define BIT_PFM_LDALL BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_CMD11_VOL_SWITCH\t\t(Offset 0x10250004) */\n\n#define BIT_CMD11_SEQ_EN BIT(0)\n\n/* 2 REG_SDIO_CTRL\t\t\t\t(Offset 0x10250005) */\n\n#define BIT_SIG_OUT_PH BIT(0)\n\n/* 2 REG_SDIO_DRIVING\t\t\t(Offset 0x10250006) */\n\n#define BIT_SHIFT_SDIO_DRV_TYPE_D 12\n#define BIT_MASK_SDIO_DRV_TYPE_D 0xf\n#define BIT_SDIO_DRV_TYPE_D(x)                                                 \\\n\t(((x) & BIT_MASK_SDIO_DRV_TYPE_D) << BIT_SHIFT_SDIO_DRV_TYPE_D)\n#define BITS_SDIO_DRV_TYPE_D                                                   \\\n\t(BIT_MASK_SDIO_DRV_TYPE_D << BIT_SHIFT_SDIO_DRV_TYPE_D)\n#define BIT_CLEAR_SDIO_DRV_TYPE_D(x) ((x) & (~BITS_SDIO_DRV_TYPE_D))\n#define BIT_GET_SDIO_DRV_TYPE_D(x)                                             \\\n\t(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_D) & BIT_MASK_SDIO_DRV_TYPE_D)\n#define BIT_SET_SDIO_DRV_TYPE_D(x, v)                                          \\\n\t(BIT_CLEAR_SDIO_DRV_TYPE_D(x) | BIT_SDIO_DRV_TYPE_D(v))\n\n#define BIT_SHIFT_SDIO_DRV_TYPE_C 8\n#define BIT_MASK_SDIO_DRV_TYPE_C 0xf\n#define BIT_SDIO_DRV_TYPE_C(x)                                                 \\\n\t(((x) & BIT_MASK_SDIO_DRV_TYPE_C) << BIT_SHIFT_SDIO_DRV_TYPE_C)\n#define BITS_SDIO_DRV_TYPE_C                                                   \\\n\t(BIT_MASK_SDIO_DRV_TYPE_C << BIT_SHIFT_SDIO_DRV_TYPE_C)\n#define BIT_CLEAR_SDIO_DRV_TYPE_C(x) ((x) & (~BITS_SDIO_DRV_TYPE_C))\n#define BIT_GET_SDIO_DRV_TYPE_C(x)                                             \\\n\t(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_C) & BIT_MASK_SDIO_DRV_TYPE_C)\n#define BIT_SET_SDIO_DRV_TYPE_C(x, v)                                          \\\n\t(BIT_CLEAR_SDIO_DRV_TYPE_C(x) | BIT_SDIO_DRV_TYPE_C(v))\n\n#define BIT_SHIFT_SDIO_DRV_TYPE_B 4\n#define BIT_MASK_SDIO_DRV_TYPE_B 0xf\n#define BIT_SDIO_DRV_TYPE_B(x)                                                 \\\n\t(((x) & BIT_MASK_SDIO_DRV_TYPE_B) << BIT_SHIFT_SDIO_DRV_TYPE_B)\n#define BITS_SDIO_DRV_TYPE_B                                                   \\\n\t(BIT_MASK_SDIO_DRV_TYPE_B << BIT_SHIFT_SDIO_DRV_TYPE_B)\n#define BIT_CLEAR_SDIO_DRV_TYPE_B(x) ((x) & (~BITS_SDIO_DRV_TYPE_B))\n#define BIT_GET_SDIO_DRV_TYPE_B(x)                                             \\\n\t(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_B) & BIT_MASK_SDIO_DRV_TYPE_B)\n#define BIT_SET_SDIO_DRV_TYPE_B(x, v)                                          \\\n\t(BIT_CLEAR_SDIO_DRV_TYPE_B(x) | BIT_SDIO_DRV_TYPE_B(v))\n\n#define BIT_SHIFT_SDIO_DRV_TYPE_A 0\n#define BIT_MASK_SDIO_DRV_TYPE_A 0xf\n#define BIT_SDIO_DRV_TYPE_A(x)                                                 \\\n\t(((x) & BIT_MASK_SDIO_DRV_TYPE_A) << BIT_SHIFT_SDIO_DRV_TYPE_A)\n#define BITS_SDIO_DRV_TYPE_A                                                   \\\n\t(BIT_MASK_SDIO_DRV_TYPE_A << BIT_SHIFT_SDIO_DRV_TYPE_A)\n#define BIT_CLEAR_SDIO_DRV_TYPE_A(x) ((x) & (~BITS_SDIO_DRV_TYPE_A))\n#define BIT_GET_SDIO_DRV_TYPE_A(x)                                             \\\n\t(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_A) & BIT_MASK_SDIO_DRV_TYPE_A)\n#define BIT_SET_SDIO_DRV_TYPE_A(x, v)                                          \\\n\t(BIT_CLEAR_SDIO_DRV_TYPE_A(x) | BIT_SDIO_DRV_TYPE_A(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_CPHY_LDO_CL_EN BIT(19)\n#define BIT_CPHY_LDO_OK BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_LDO_DUMMY BIT(15)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_ANA_CLK_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_DATA_CPU_CLK_EN BIT(15)\n#define BIT_DATA_CPU_PWC BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_CPU_CLK_EN BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_SYMREG_CLK_EN BIT(13)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_RING_CLK_EN BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_HCI_CLK_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_SYS_CLK_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_MAC_CLK_EN BIT(11)\n#define BIT_SEC_CLK_EN BIT(10)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_CTRL_SPS_PWM_FREQ BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_PHY_SSC_RSTB BIT(9)\n#define BIT_EXT_32K_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_EXT32K_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_DISABLE_OPEN_SPS_LDO BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_WL_CLK_TEST BIT(7)\n#define BIT_OP_SPS_PWM_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_SHIFT_MAC_CLK_SEL_V1 6\n#define BIT_MASK_MAC_CLK_SEL_V1 0x3\n#define BIT_MAC_CLK_SEL_V1(x)                                                  \\\n\t(((x) & BIT_MASK_MAC_CLK_SEL_V1) << BIT_SHIFT_MAC_CLK_SEL_V1)\n#define BITS_MAC_CLK_SEL_V1                                                    \\\n\t(BIT_MASK_MAC_CLK_SEL_V1 << BIT_SHIFT_MAC_CLK_SEL_V1)\n#define BIT_CLEAR_MAC_CLK_SEL_V1(x) ((x) & (~BITS_MAC_CLK_SEL_V1))\n#define BIT_GET_MAC_CLK_SEL_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_MAC_CLK_SEL_V1) & BIT_MASK_MAC_CLK_SEL_V1)\n#define BIT_SET_MAC_CLK_SEL_V1(x, v)                                           \\\n\t(BIT_CLEAR_MAC_CLK_SEL_V1(x) | BIT_MAC_CLK_SEL_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_LOADER_CLK_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_POW_PC_LDO3 BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_MACSLP BIT(4)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_POW_PC_LDO2 BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_WAKEPAD_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_ENB_LDO_DIODE_L BIT(3)\n#define BIT_POW_PC_LDO1 BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_ROMD16V_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_AFE_BGEN_PCIE_OP BIT(2)\n#define BIT_POW_PC_LDO0 BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_CKANA8M_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_CKANA12M_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_ANA8M_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_CNTD16V_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_MONITOR\t\t\t(Offset 0x10250008) */\n\n#define BIT_SHIFT_SDIO_INT_START 0\n#define BIT_MASK_SDIO_INT_START 0xffffffffL\n#define BIT_SDIO_INT_START(x)                                                  \\\n\t(((x) & BIT_MASK_SDIO_INT_START) << BIT_SHIFT_SDIO_INT_START)\n#define BITS_SDIO_INT_START                                                    \\\n\t(BIT_MASK_SDIO_INT_START << BIT_SHIFT_SDIO_INT_START)\n#define BIT_CLEAR_SDIO_INT_START(x) ((x) & (~BITS_SDIO_INT_START))\n#define BIT_GET_SDIO_INT_START(x)                                              \\\n\t(((x) >> BIT_SHIFT_SDIO_INT_START) & BIT_MASK_SDIO_INT_START)\n#define BIT_SET_SDIO_INT_START(x, v)                                           \\\n\t(BIT_CLEAR_SDIO_INT_START(x) | BIT_SDIO_INT_START(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYS_CLK_CTRL\t\t\t(Offset 0x0008) */\n\n#define BIT_POW_POWER_CUT BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_EEPROM_CTRL\t\t\t(Offset 0x000A) */\n\n#define BIT_SHIFT_VPDIDX 8\n#define BIT_MASK_VPDIDX 0xff\n#define BIT_VPDIDX(x) (((x) & BIT_MASK_VPDIDX) << BIT_SHIFT_VPDIDX)\n#define BITS_VPDIDX (BIT_MASK_VPDIDX << BIT_SHIFT_VPDIDX)\n#define BIT_CLEAR_VPDIDX(x) ((x) & (~BITS_VPDIDX))\n#define BIT_GET_VPDIDX(x) (((x) >> BIT_SHIFT_VPDIDX) & BIT_MASK_VPDIDX)\n#define BIT_SET_VPDIDX(x, v) (BIT_CLEAR_VPDIDX(x) | BIT_VPDIDX(v))\n\n#define BIT_SHIFT_EEM1_0 6\n#define BIT_MASK_EEM1_0 0x3\n#define BIT_EEM1_0(x) (((x) & BIT_MASK_EEM1_0) << BIT_SHIFT_EEM1_0)\n#define BITS_EEM1_0 (BIT_MASK_EEM1_0 << BIT_SHIFT_EEM1_0)\n#define BIT_CLEAR_EEM1_0(x) ((x) & (~BITS_EEM1_0))\n#define BIT_GET_EEM1_0(x) (((x) >> BIT_SHIFT_EEM1_0) & BIT_MASK_EEM1_0)\n#define BIT_SET_EEM1_0(x, v) (BIT_CLEAR_EEM1_0(x) | BIT_EEM1_0(v))\n\n#define BIT_AUTOLOAD_SUS BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_EEPROM_CTRL\t\t\t(Offset 0x000A) */\n\n#define BIT_EERPOMSEL BIT(4)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_EEPROM_CTRL\t\t\t(Offset 0x000A) */\n\n#define BIT_EEPROMSEL BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_EEPROM_CTRL\t\t\t(Offset 0x000A) */\n\n#define BIT_EECS_V1 BIT(3)\n#define BIT_EESK_V1 BIT(2)\n#define BIT_EEDI_V1 BIT(1)\n#define BIT_EEDO_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_MONITOR_2\t\t\t(Offset 0x1025000C) */\n\n#define BIT_CMD53_WT_EN BIT(23)\n\n#define BIT_SHIFT_SDIO_CLK_MONITOR 21\n#define BIT_MASK_SDIO_CLK_MONITOR 0x3\n#define BIT_SDIO_CLK_MONITOR(x)                                                \\\n\t(((x) & BIT_MASK_SDIO_CLK_MONITOR) << BIT_SHIFT_SDIO_CLK_MONITOR)\n#define BITS_SDIO_CLK_MONITOR                                                  \\\n\t(BIT_MASK_SDIO_CLK_MONITOR << BIT_SHIFT_SDIO_CLK_MONITOR)\n#define BIT_CLEAR_SDIO_CLK_MONITOR(x) ((x) & (~BITS_SDIO_CLK_MONITOR))\n#define BIT_GET_SDIO_CLK_MONITOR(x)                                            \\\n\t(((x) >> BIT_SHIFT_SDIO_CLK_MONITOR) & BIT_MASK_SDIO_CLK_MONITOR)\n#define BIT_SET_SDIO_CLK_MONITOR(x, v)                                         \\\n\t(BIT_CLEAR_SDIO_CLK_MONITOR(x) | BIT_SDIO_CLK_MONITOR(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_EE_VPD\t\t\t\t(Offset 0x000C) */\n\n#define BIT_SHIFT_VPD_DATA 0\n#define BIT_MASK_VPD_DATA 0xffffffffL\n#define BIT_VPD_DATA(x) (((x) & BIT_MASK_VPD_DATA) << BIT_SHIFT_VPD_DATA)\n#define BITS_VPD_DATA (BIT_MASK_VPD_DATA << BIT_SHIFT_VPD_DATA)\n#define BIT_CLEAR_VPD_DATA(x) ((x) & (~BITS_VPD_DATA))\n#define BIT_GET_VPD_DATA(x) (((x) >> BIT_SHIFT_VPD_DATA) & BIT_MASK_VPD_DATA)\n#define BIT_SET_VPD_DATA(x, v) (BIT_CLEAR_VPD_DATA(x) | BIT_VPD_DATA(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_MONITOR_2\t\t\t(Offset 0x1025000C) */\n\n#define BIT_SHIFT_SDIO_CLK_CNT 0\n#define BIT_MASK_SDIO_CLK_CNT 0x1fffff\n#define BIT_SDIO_CLK_CNT(x)                                                    \\\n\t(((x) & BIT_MASK_SDIO_CLK_CNT) << BIT_SHIFT_SDIO_CLK_CNT)\n#define BITS_SDIO_CLK_CNT (BIT_MASK_SDIO_CLK_CNT << BIT_SHIFT_SDIO_CLK_CNT)\n#define BIT_CLEAR_SDIO_CLK_CNT(x) ((x) & (~BITS_SDIO_CLK_CNT))\n#define BIT_GET_SDIO_CLK_CNT(x)                                                \\\n\t(((x) >> BIT_SHIFT_SDIO_CLK_CNT) & BIT_MASK_SDIO_CLK_CNT)\n#define BIT_SET_SDIO_CLK_CNT(x, v)                                             \\\n\t(BIT_CLEAR_SDIO_CLK_CNT(x) | BIT_SDIO_CLK_CNT(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_EE_VPD\t\t\t\t(Offset 0x000C) */\n\n#define BIT_SHIFT_VDP_DATA 0\n#define BIT_MASK_VDP_DATA 0xffffffffL\n#define BIT_VDP_DATA(x) (((x) & BIT_MASK_VDP_DATA) << BIT_SHIFT_VDP_DATA)\n#define BITS_VDP_DATA (BIT_MASK_VDP_DATA << BIT_SHIFT_VDP_DATA)\n#define BIT_CLEAR_VDP_DATA(x) ((x) & (~BITS_VDP_DATA))\n#define BIT_GET_VDP_DATA(x) (((x) >> BIT_SHIFT_VDP_DATA) & BIT_MASK_VDP_DATA)\n#define BIT_SET_VDP_DATA(x, v) (BIT_CLEAR_VDP_DATA(x) | BIT_VDP_DATA(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SW18_C2_BIT0 BIT(31)\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_C2_L_BIT0 BIT(31)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SHIFT_R1_L1_V1 30\n#define BIT_MASK_R1_L1_V1 0x3\n#define BIT_R1_L1_V1(x) (((x) & BIT_MASK_R1_L1_V1) << BIT_SHIFT_R1_L1_V1)\n#define BITS_R1_L1_V1 (BIT_MASK_R1_L1_V1 << BIT_SHIFT_R1_L1_V1)\n#define BIT_CLEAR_R1_L1_V1(x) ((x) & (~BITS_R1_L1_V1))\n#define BIT_GET_R1_L1_V1(x) (((x) >> BIT_SHIFT_R1_L1_V1) & BIT_MASK_R1_L1_V1)\n#define BIT_SET_R1_L1_V1(x, v) (BIT_CLEAR_R1_L1_V1(x) | BIT_R1_L1_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SHIFT_SW18_C1 29\n#define BIT_MASK_SW18_C1 0x3\n#define BIT_SW18_C1(x) (((x) & BIT_MASK_SW18_C1) << BIT_SHIFT_SW18_C1)\n#define BITS_SW18_C1 (BIT_MASK_SW18_C1 << BIT_SHIFT_SW18_C1)\n#define BIT_CLEAR_SW18_C1(x) ((x) & (~BITS_SW18_C1))\n#define BIT_GET_SW18_C1(x) (((x) >> BIT_SHIFT_SW18_C1) & BIT_MASK_SW18_C1)\n#define BIT_SET_SW18_C1(x, v) (BIT_CLEAR_SW18_C1(x) | BIT_SW18_C1(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SHIFT_C1_L 29\n#define BIT_MASK_C1_L 0x3\n#define BIT_C1_L(x) (((x) & BIT_MASK_C1_L) << BIT_SHIFT_C1_L)\n#define BITS_C1_L (BIT_MASK_C1_L << BIT_SHIFT_C1_L)\n#define BIT_CLEAR_C1_L(x) ((x) & (~BITS_C1_L))\n#define BIT_GET_C1_L(x) (((x) >> BIT_SHIFT_C1_L) & BIT_MASK_C1_L)\n#define BIT_SET_C1_L(x, v) (BIT_CLEAR_C1_L(x) | BIT_C1_L(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SHIFT_C3_L1_V1 28\n#define BIT_MASK_C3_L1_V1 0x3\n#define BIT_C3_L1_V1(x) (((x) & BIT_MASK_C3_L1_V1) << BIT_SHIFT_C3_L1_V1)\n#define BITS_C3_L1_V1 (BIT_MASK_C3_L1_V1 << BIT_SHIFT_C3_L1_V1)\n#define BIT_CLEAR_C3_L1_V1(x) ((x) & (~BITS_C3_L1_V1))\n#define BIT_GET_C3_L1_V1(x) (((x) >> BIT_SHIFT_C3_L1_V1) & BIT_MASK_C3_L1_V1)\n#define BIT_SET_C3_L1_V1(x, v) (BIT_CLEAR_C3_L1_V1(x) | BIT_C3_L1_V1(v))\n\n#define BIT_SHIFT_C2_L1_V1 26\n#define BIT_MASK_C2_L1_V1 0x3\n#define BIT_C2_L1_V1(x) (((x) & BIT_MASK_C2_L1_V1) << BIT_SHIFT_C2_L1_V1)\n#define BITS_C2_L1_V1 (BIT_MASK_C2_L1_V1 << BIT_SHIFT_C2_L1_V1)\n#define BIT_CLEAR_C2_L1_V1(x) ((x) & (~BITS_C2_L1_V1))\n#define BIT_GET_C2_L1_V1(x) (((x) >> BIT_SHIFT_C2_L1_V1) & BIT_MASK_C2_L1_V1)\n#define BIT_SET_C2_L1_V1(x, v) (BIT_CLEAR_C2_L1_V1(x) | BIT_C2_L1_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SHIFT_REG_FREQ_L 25\n#define BIT_MASK_REG_FREQ_L 0x7\n#define BIT_REG_FREQ_L(x) (((x) & BIT_MASK_REG_FREQ_L) << BIT_SHIFT_REG_FREQ_L)\n#define BITS_REG_FREQ_L (BIT_MASK_REG_FREQ_L << BIT_SHIFT_REG_FREQ_L)\n#define BIT_CLEAR_REG_FREQ_L(x) ((x) & (~BITS_REG_FREQ_L))\n#define BIT_GET_REG_FREQ_L(x)                                                  \\\n\t(((x) >> BIT_SHIFT_REG_FREQ_L) & BIT_MASK_REG_FREQ_L)\n#define BIT_SET_REG_FREQ_L(x, v) (BIT_CLEAR_REG_FREQ_L(x) | BIT_REG_FREQ_L(v))\n\n#define BIT_REG_EN_DUTY BIT(24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SHIFT_C1_L1_V1 24\n#define BIT_MASK_C1_L1_V1 0x3\n#define BIT_C1_L1_V1(x) (((x) & BIT_MASK_C1_L1_V1) << BIT_SHIFT_C1_L1_V1)\n#define BITS_C1_L1_V1 (BIT_MASK_C1_L1_V1 << BIT_SHIFT_C1_L1_V1)\n#define BIT_CLEAR_C1_L1_V1(x) ((x) & (~BITS_C1_L1_V1))\n#define BIT_GET_C1_L1_V1(x) (((x) >> BIT_SHIFT_C1_L1_V1) & BIT_MASK_C1_L1_V1)\n#define BIT_SET_C1_L1_V1(x, v) (BIT_CLEAR_C1_L1_V1(x) | BIT_C1_L1_V1(v))\n\n#define BIT_REG_TYPE_L_V3 BIT(23)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SHIFT_REG_MODE 22\n#define BIT_MASK_REG_MODE 0x3\n#define BIT_REG_MODE(x) (((x) & BIT_MASK_REG_MODE) << BIT_SHIFT_REG_MODE)\n#define BITS_REG_MODE (BIT_MASK_REG_MODE << BIT_SHIFT_REG_MODE)\n#define BIT_CLEAR_REG_MODE(x) ((x) & (~BITS_REG_MODE))\n#define BIT_GET_REG_MODE(x) (((x) >> BIT_SHIFT_REG_MODE) & BIT_MASK_REG_MODE)\n#define BIT_SET_REG_MODE(x, v) (BIT_CLEAR_REG_MODE(x) | BIT_REG_MODE(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_FPWM_L1_V1 BIT(22)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_REG_EN_SP BIT(21)\n#define BIT_REG_AUTO_L BIT(20)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SW18_SELD_BIT0 BIT(19)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SHIFT_V15ADJ_L1 19\n#define BIT_MASK_V15ADJ_L1 0x7\n#define BIT_V15ADJ_L1(x) (((x) & BIT_MASK_V15ADJ_L1) << BIT_SHIFT_V15ADJ_L1)\n#define BITS_V15ADJ_L1 (BIT_MASK_V15ADJ_L1 << BIT_SHIFT_V15ADJ_L1)\n#define BIT_CLEAR_V15ADJ_L1(x) ((x) & (~BITS_V15ADJ_L1))\n#define BIT_GET_V15ADJ_L1(x) (((x) >> BIT_SHIFT_V15ADJ_L1) & BIT_MASK_V15ADJ_L1)\n#define BIT_SET_V15ADJ_L1(x, v) (BIT_CLEAR_V15ADJ_L1(x) | BIT_V15ADJ_L1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SW18_POWOCP BIT(18)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SHIFT_IN_L1 16\n#define BIT_MASK_IN_L1 0x7\n#define BIT_IN_L1(x) (((x) & BIT_MASK_IN_L1) << BIT_SHIFT_IN_L1)\n#define BITS_IN_L1 (BIT_MASK_IN_L1 << BIT_SHIFT_IN_L1)\n#define BIT_CLEAR_IN_L1(x) ((x) & (~BITS_IN_L1))\n#define BIT_GET_IN_L1(x) (((x) >> BIT_SHIFT_IN_L1) & BIT_MASK_IN_L1)\n#define BIT_SET_IN_L1(x, v) (BIT_CLEAR_IN_L1(x) | BIT_IN_L1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SHIFT_SW18_OCP 15\n#define BIT_MASK_SW18_OCP 0x7\n#define BIT_SW18_OCP(x) (((x) & BIT_MASK_SW18_OCP) << BIT_SHIFT_SW18_OCP)\n#define BITS_SW18_OCP (BIT_MASK_SW18_OCP << BIT_SHIFT_SW18_OCP)\n#define BIT_CLEAR_SW18_OCP(x) ((x) & (~BITS_SW18_OCP))\n#define BIT_GET_SW18_OCP(x) (((x) >> BIT_SHIFT_SW18_OCP) & BIT_MASK_SW18_OCP)\n#define BIT_SET_SW18_OCP(x, v) (BIT_CLEAR_SW18_OCP(x) | BIT_SW18_OCP(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SHIFT_OCP_L1 15\n#define BIT_MASK_OCP_L1 0x7\n#define BIT_OCP_L1(x) (((x) & BIT_MASK_OCP_L1) << BIT_SHIFT_OCP_L1)\n#define BITS_OCP_L1 (BIT_MASK_OCP_L1 << BIT_SHIFT_OCP_L1)\n#define BIT_CLEAR_OCP_L1(x) ((x) & (~BITS_OCP_L1))\n#define BIT_GET_OCP_L1(x) (((x) >> BIT_SHIFT_OCP_L1) & BIT_MASK_OCP_L1)\n#define BIT_SET_OCP_L1(x, v) (BIT_CLEAR_OCP_L1(x) | BIT_OCP_L1(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SHIFT_STD_L1 14\n#define BIT_MASK_STD_L1 0x3\n#define BIT_STD_L1(x) (((x) & BIT_MASK_STD_L1) << BIT_SHIFT_STD_L1)\n#define BITS_STD_L1 (BIT_MASK_STD_L1 << BIT_SHIFT_STD_L1)\n#define BIT_CLEAR_STD_L1(x) ((x) & (~BITS_STD_L1))\n#define BIT_GET_STD_L1(x) (((x) >> BIT_SHIFT_STD_L1) & BIT_MASK_STD_L1)\n#define BIT_SET_STD_L1(x, v) (BIT_CLEAR_STD_L1(x) | BIT_STD_L1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SHIFT_CF_L_BIT0_TO_1 13\n#define BIT_MASK_CF_L_BIT0_TO_1 0x3\n#define BIT_CF_L_BIT0_TO_1(x)                                                  \\\n\t(((x) & BIT_MASK_CF_L_BIT0_TO_1) << BIT_SHIFT_CF_L_BIT0_TO_1)\n#define BITS_CF_L_BIT0_TO_1                                                    \\\n\t(BIT_MASK_CF_L_BIT0_TO_1 << BIT_SHIFT_CF_L_BIT0_TO_1)\n#define BIT_CLEAR_CF_L_BIT0_TO_1(x) ((x) & (~BITS_CF_L_BIT0_TO_1))\n#define BIT_GET_CF_L_BIT0_TO_1(x)                                              \\\n\t(((x) >> BIT_SHIFT_CF_L_BIT0_TO_1) & BIT_MASK_CF_L_BIT0_TO_1)\n#define BIT_SET_CF_L_BIT0_TO_1(x, v)                                           \\\n\t(BIT_CLEAR_CF_L_BIT0_TO_1(x) | BIT_CF_L_BIT0_TO_1(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SHIFT_CF_L 13\n#define BIT_MASK_CF_L 0x3\n#define BIT_CF_L(x) (((x) & BIT_MASK_CF_L) << BIT_SHIFT_CF_L)\n#define BITS_CF_L (BIT_MASK_CF_L << BIT_SHIFT_CF_L)\n#define BIT_CLEAR_CF_L(x) ((x) & (~BITS_CF_L))\n#define BIT_GET_CF_L(x) (((x) >> BIT_SHIFT_CF_L) & BIT_MASK_CF_L)\n#define BIT_SET_CF_L(x, v) (BIT_CLEAR_CF_L(x) | BIT_CF_L(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SW18_FPWM BIT(11)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SPS_FPWM BIT(11)\n#define BIT_WL_CTRL_SPS_PWMFREQ BIT(10)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SHIFT_VOL_L1 10\n#define BIT_MASK_VOL_L1 0xf\n#define BIT_VOL_L1(x) (((x) & BIT_MASK_VOL_L1) << BIT_SHIFT_VOL_L1)\n#define BITS_VOL_L1 (BIT_MASK_VOL_L1 << BIT_SHIFT_VOL_L1)\n#define BIT_CLEAR_VOL_L1(x) ((x) & (~BITS_VOL_L1))\n#define BIT_GET_VOL_L1(x) (((x) >> BIT_SHIFT_VOL_L1) & BIT_MASK_VOL_L1)\n#define BIT_SET_VOL_L1(x, v) (BIT_CLEAR_VOL_L1(x) | BIT_VOL_L1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SW18_SWEN BIT(9)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SPS_SWEN BIT(9)\n#define BIT_HALF_L BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SW18_LDEN BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_SPS_LDEN BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_MAC_ID_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_WL_CTRL_XTAL_CADJ BIT(6)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_LDO11_EN BIT(6)\n#define BIT_AFE_P3_PC BIT(5)\n#define BIT_AFE_P2_PC BIT(4)\n#define BIT_AFE_P1_PC BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_AFE_MBEN_PCIE_OPT BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_AFE_P0_PC BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_AFE_MBEN BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL1\t\t\t(Offset 0x0010) */\n\n#define BIT_AFE_BGEN BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_POW_ZCD_L BIT(31)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_CRCERR_MSK BIT(31)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_IO_READY_SIGNAL_ERR_MSK BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_ENABLE_ZCDOUT_L BIT(30)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_AUTOZCD_L BIT(30)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_HSISR3_IND_MSK BIT(30)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_TX_CRC__MSK BIT(30)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_HSISR2_IND_MSK BIT(29)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_REG_DELAY 28\n#define BIT_MASK_REG_DELAY 0x3\n#define BIT_REG_DELAY(x) (((x) & BIT_MASK_REG_DELAY) << BIT_SHIFT_REG_DELAY)\n#define BITS_REG_DELAY (BIT_MASK_REG_DELAY << BIT_SHIFT_REG_DELAY)\n#define BIT_CLEAR_REG_DELAY(x) ((x) & (~BITS_REG_DELAY))\n#define BIT_GET_REG_DELAY(x) (((x) >> BIT_SHIFT_REG_DELAY) & BIT_MASK_REG_DELAY)\n#define BIT_SET_REG_DELAY(x, v) (BIT_CLEAR_REG_DELAY(x) | BIT_REG_DELAY(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_HEISR_IND_MSK BIT(28)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_CTWEND_MSK BIT(27)\n#define BIT_SDIO_ATIMEND_E_MSK BIT(26)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIIO_ATIMEND_MSK BIT(25)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_ATIMEND_MSK BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_SW18_V15ADJ 24\n#define BIT_MASK_SW18_V15ADJ 0x7\n#define BIT_SW18_V15ADJ(x)                                                     \\\n\t(((x) & BIT_MASK_SW18_V15ADJ) << BIT_SHIFT_SW18_V15ADJ)\n#define BITS_SW18_V15ADJ (BIT_MASK_SW18_V15ADJ << BIT_SHIFT_SW18_V15ADJ)\n#define BIT_CLEAR_SW18_V15ADJ(x) ((x) & (~BITS_SW18_V15ADJ))\n#define BIT_GET_SW18_V15ADJ(x)                                                 \\\n\t(((x) >> BIT_SHIFT_SW18_V15ADJ) & BIT_MASK_SW18_V15ADJ)\n#define BIT_SET_SW18_V15ADJ(x, v)                                              \\\n\t(BIT_CLEAR_SW18_V15ADJ(x) | BIT_SW18_V15ADJ(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_V15ADJ_L1_V1 24\n#define BIT_MASK_V15ADJ_L1_V1 0x7\n#define BIT_V15ADJ_L1_V1(x)                                                    \\\n\t(((x) & BIT_MASK_V15ADJ_L1_V1) << BIT_SHIFT_V15ADJ_L1_V1)\n#define BITS_V15ADJ_L1_V1 (BIT_MASK_V15ADJ_L1_V1 << BIT_SHIFT_V15ADJ_L1_V1)\n#define BIT_CLEAR_V15ADJ_L1_V1(x) ((x) & (~BITS_V15ADJ_L1_V1))\n#define BIT_GET_V15ADJ_L1_V1(x)                                                \\\n\t(((x) >> BIT_SHIFT_V15ADJ_L1_V1) & BIT_MASK_V15ADJ_L1_V1)\n#define BIT_SET_V15ADJ_L1_V1(x, v)                                             \\\n\t(BIT_CLEAR_V15ADJ_L1_V1(x) | BIT_V15ADJ_L1_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_OCPINT_MSK BIT(24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_OCPSL BIT(24)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_PSTIMEOUT_MSK BIT(23)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_REG_LDOF_L_V1 BIT(23)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_GTINT4_MSK BIT(22)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_PARSW_DUMMY BIT(22)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_GTINT3_MSK BIT(21)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_CLAMP_MAX_DUTY BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_SW18_VOL 20\n#define BIT_MASK_SW18_VOL 0xf\n#define BIT_SW18_VOL(x) (((x) & BIT_MASK_SW18_VOL) << BIT_SHIFT_SW18_VOL)\n#define BITS_SW18_VOL (BIT_MASK_SW18_VOL << BIT_SHIFT_SW18_VOL)\n#define BIT_CLEAR_SW18_VOL(x) ((x) & (~BITS_SW18_VOL))\n#define BIT_GET_SW18_VOL(x) (((x) >> BIT_SHIFT_SW18_VOL) & BIT_MASK_SW18_VOL)\n#define BIT_SET_SW18_VOL(x, v) (BIT_CLEAR_SW18_VOL(x) | BIT_SW18_VOL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_VOL_L1_V1 20\n#define BIT_MASK_VOL_L1_V1 0xf\n#define BIT_VOL_L1_V1(x) (((x) & BIT_MASK_VOL_L1_V1) << BIT_SHIFT_VOL_L1_V1)\n#define BITS_VOL_L1_V1 (BIT_MASK_VOL_L1_V1 << BIT_SHIFT_VOL_L1_V1)\n#define BIT_CLEAR_VOL_L1_V1(x) ((x) & (~BITS_VOL_L1_V1))\n#define BIT_GET_VOL_L1_V1(x) (((x) >> BIT_SHIFT_VOL_L1_V1) & BIT_MASK_VOL_L1_V1)\n#define BIT_SET_VOL_L1_V1(x, v) (BIT_CLEAR_VOL_L1_V1(x) | BIT_VOL_L1_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_HSISR_IND_MSK BIT(20)\n#define BIT_SDIO_CPWM2_MSK BIT(19)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_TBOX_L1_V1 19\n#define BIT_MASK_TBOX_L1_V1 0x3\n#define BIT_TBOX_L1_V1(x) (((x) & BIT_MASK_TBOX_L1_V1) << BIT_SHIFT_TBOX_L1_V1)\n#define BITS_TBOX_L1_V1 (BIT_MASK_TBOX_L1_V1 << BIT_SHIFT_TBOX_L1_V1)\n#define BIT_CLEAR_TBOX_L1_V1(x) ((x) & (~BITS_TBOX_L1_V1))\n#define BIT_GET_TBOX_L1_V1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_TBOX_L1_V1) & BIT_MASK_TBOX_L1_V1)\n#define BIT_SET_TBOX_L1_V1(x, v) (BIT_CLEAR_TBOX_L1_V1(x) | BIT_TBOX_L1_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_CPWM1_MSK BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_SW18_IN 17\n#define BIT_MASK_SW18_IN 0x7\n#define BIT_SW18_IN(x) (((x) & BIT_MASK_SW18_IN) << BIT_SHIFT_SW18_IN)\n#define BITS_SW18_IN (BIT_MASK_SW18_IN << BIT_SHIFT_SW18_IN)\n#define BIT_CLEAR_SW18_IN(x) ((x) & (~BITS_SW18_IN))\n#define BIT_GET_SW18_IN(x) (((x) >> BIT_SHIFT_SW18_IN) & BIT_MASK_SW18_IN)\n#define BIT_SET_SW18_IN(x, v) (BIT_CLEAR_SW18_IN(x) | BIT_SW18_IN(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_IN_L1_V1 17\n#define BIT_MASK_IN_L1_V1 0x7\n#define BIT_IN_L1_V1(x) (((x) & BIT_MASK_IN_L1_V1) << BIT_SHIFT_IN_L1_V1)\n#define BITS_IN_L1_V1 (BIT_MASK_IN_L1_V1 << BIT_SHIFT_IN_L1_V1)\n#define BIT_CLEAR_IN_L1_V1(x) ((x) & (~BITS_IN_L1_V1))\n#define BIT_GET_IN_L1_V1(x) (((x) >> BIT_SHIFT_IN_L1_V1) & BIT_MASK_IN_L1_V1)\n#define BIT_SET_IN_L1_V1(x, v) (BIT_CLEAR_IN_L1_V1(x) | BIT_IN_L1_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_C2HCMD_INT_MSK BIT(17)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_REG_DELAY_V3 17\n#define BIT_MASK_REG_DELAY_V3 0x3\n#define BIT_REG_DELAY_V3(x)                                                    \\\n\t(((x) & BIT_MASK_REG_DELAY_V3) << BIT_SHIFT_REG_DELAY_V3)\n#define BITS_REG_DELAY_V3 (BIT_MASK_REG_DELAY_V3 << BIT_SHIFT_REG_DELAY_V3)\n#define BIT_CLEAR_REG_DELAY_V3(x) ((x) & (~BITS_REG_DELAY_V3))\n#define BIT_GET_REG_DELAY_V3(x)                                                \\\n\t(((x) >> BIT_SHIFT_REG_DELAY_V3) & BIT_MASK_REG_DELAY_V3)\n#define BIT_SET_REG_DELAY_V3(x, v)                                             \\\n\t(BIT_CLEAR_REG_DELAY_V3(x) | BIT_REG_DELAY_V3(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_BCNERLY_INT_MSK BIT(16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_REG_CLAMP_D_L_V2 BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_SW18_TBOX 15\n#define BIT_MASK_SW18_TBOX 0x3\n#define BIT_SW18_TBOX(x) (((x) & BIT_MASK_SW18_TBOX) << BIT_SHIFT_SW18_TBOX)\n#define BITS_SW18_TBOX (BIT_MASK_SW18_TBOX << BIT_SHIFT_SW18_TBOX)\n#define BIT_CLEAR_SW18_TBOX(x) ((x) & (~BITS_SW18_TBOX))\n#define BIT_GET_SW18_TBOX(x) (((x) >> BIT_SHIFT_SW18_TBOX) & BIT_MASK_SW18_TBOX)\n#define BIT_SET_SW18_TBOX(x, v) (BIT_CLEAR_SW18_TBOX(x) | BIT_SW18_TBOX(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_REG_BYPASS_L_V3 BIT(15)\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_TBOX_L1 15\n#define BIT_MASK_TBOX_L1 0x3\n#define BIT_TBOX_L1(x) (((x) & BIT_MASK_TBOX_L1) << BIT_SHIFT_TBOX_L1)\n#define BITS_TBOX_L1 (BIT_MASK_TBOX_L1 << BIT_SHIFT_TBOX_L1)\n#define BIT_CLEAR_TBOX_L1(x) ((x) & (~BITS_TBOX_L1))\n#define BIT_GET_TBOX_L1(x) (((x) >> BIT_SHIFT_TBOX_L1) & BIT_MASK_TBOX_L1)\n#define BIT_SET_TBOX_L1(x, v) (BIT_CLEAR_TBOX_L1(x) | BIT_TBOX_L1(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_ENABLE_ZCDOUT_L_V3 BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SW18_SEL BIT(13)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_POW_ZCD_L_V3 BIT(13)\n#define BIT_AREN_L1_V1 BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_SW18_STD 11\n#define BIT_MASK_SW18_STD 0x3\n#define BIT_SW18_STD(x) (((x) & BIT_MASK_SW18_STD) << BIT_SHIFT_SW18_STD)\n#define BITS_SW18_STD (BIT_MASK_SW18_STD << BIT_SHIFT_SW18_STD)\n#define BIT_CLEAR_SW18_STD(x) ((x) & (~BITS_SW18_STD))\n#define BIT_GET_SW18_STD(x) (((x) >> BIT_SHIFT_SW18_STD) & BIT_MASK_SW18_STD)\n#define BIT_SET_SW18_STD(x, v) (BIT_CLEAR_SW18_STD(x) | BIT_SW18_STD(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SW18_SD BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SW18_AREN BIT(9)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_OCP_V3 9\n#define BIT_MASK_OCP_V3 0x7\n#define BIT_OCP_V3(x) (((x) & BIT_MASK_OCP_V3) << BIT_SHIFT_OCP_V3)\n#define BITS_OCP_V3 (BIT_MASK_OCP_V3 << BIT_SHIFT_OCP_V3)\n#define BIT_CLEAR_OCP_V3(x) ((x) & (~BITS_OCP_V3))\n#define BIT_GET_OCP_V3(x) (((x) >> BIT_SHIFT_OCP_V3) & BIT_MASK_OCP_V3)\n#define BIT_SET_OCP_V3(x, v) (BIT_CLEAR_OCP_V3(x) | BIT_OCP_V3(v))\n\n#define BIT_POWOCP_V3 BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_SW18_R3 7\n#define BIT_MASK_SW18_R3 0x3\n#define BIT_SW18_R3(x) (((x) & BIT_MASK_SW18_R3) << BIT_SHIFT_SW18_R3)\n#define BITS_SW18_R3 (BIT_MASK_SW18_R3 << BIT_SHIFT_SW18_R3)\n#define BIT_CLEAR_SW18_R3(x) ((x) & (~BITS_SW18_R3))\n#define BIT_GET_SW18_R3(x) (((x) >> BIT_SHIFT_SW18_R3) & BIT_MASK_SW18_R3)\n#define BIT_SET_SW18_R3(x, v) (BIT_CLEAR_SW18_R3(x) | BIT_SW18_R3(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_TXBCNERR_MSK BIT(7)\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_R3_L 7\n#define BIT_MASK_R3_L 0x3\n#define BIT_R3_L(x) (((x) & BIT_MASK_R3_L) << BIT_SHIFT_R3_L)\n#define BITS_R3_L (BIT_MASK_R3_L << BIT_SHIFT_R3_L)\n#define BIT_CLEAR_R3_L(x) ((x) & (~BITS_R3_L))\n#define BIT_GET_R3_L(x) (((x) >> BIT_SHIFT_R3_L) & BIT_MASK_R3_L)\n#define BIT_SET_R3_L(x, v) (BIT_CLEAR_R3_L(x) | BIT_R3_L(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_TXBCNOK_MSK BIT(6)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_CF_L_V3 6\n#define BIT_MASK_CF_L_V3 0x3\n#define BIT_CF_L_V3(x) (((x) & BIT_MASK_CF_L_V3) << BIT_SHIFT_CF_L_V3)\n#define BITS_CF_L_V3 (BIT_MASK_CF_L_V3 << BIT_SHIFT_CF_L_V3)\n#define BIT_CLEAR_CF_L_V3(x) ((x) & (~BITS_CF_L_V3))\n#define BIT_GET_CF_L_V3(x) (((x) >> BIT_SHIFT_CF_L_V3) & BIT_MASK_CF_L_V3)\n#define BIT_SET_CF_L_V3(x, v) (BIT_CLEAR_CF_L_V3(x) | BIT_CF_L_V3(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_SW18_R2 5\n#define BIT_MASK_SW18_R2 0x3\n#define BIT_SW18_R2(x) (((x) & BIT_MASK_SW18_R2) << BIT_SHIFT_SW18_R2)\n#define BITS_SW18_R2 (BIT_MASK_SW18_R2 << BIT_SHIFT_SW18_R2)\n#define BIT_CLEAR_SW18_R2(x) ((x) & (~BITS_SW18_R2))\n#define BIT_GET_SW18_R2(x) (((x) >> BIT_SHIFT_SW18_R2) & BIT_MASK_SW18_R2)\n#define BIT_SET_SW18_R2(x, v) (BIT_CLEAR_SW18_R2(x) | BIT_SW18_R2(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_RXFOVW_MSK BIT(5)\n#define BIT_SDIO_TXFOVW_MSK BIT(4)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_CFC_L_BIT0_TO_1_V1 4\n#define BIT_MASK_CFC_L_BIT0_TO_1_V1 0x3\n#define BIT_CFC_L_BIT0_TO_1_V1(x)                                              \\\n\t(((x) & BIT_MASK_CFC_L_BIT0_TO_1_V1) << BIT_SHIFT_CFC_L_BIT0_TO_1_V1)\n#define BITS_CFC_L_BIT0_TO_1_V1                                                \\\n\t(BIT_MASK_CFC_L_BIT0_TO_1_V1 << BIT_SHIFT_CFC_L_BIT0_TO_1_V1)\n#define BIT_CLEAR_CFC_L_BIT0_TO_1_V1(x) ((x) & (~BITS_CFC_L_BIT0_TO_1_V1))\n#define BIT_GET_CFC_L_BIT0_TO_1_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_CFC_L_BIT0_TO_1_V1) & BIT_MASK_CFC_L_BIT0_TO_1_V1)\n#define BIT_SET_CFC_L_BIT0_TO_1_V1(x, v)                                       \\\n\t(BIT_CLEAR_CFC_L_BIT0_TO_1_V1(x) | BIT_CFC_L_BIT0_TO_1_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_SW18_R1 3\n#define BIT_MASK_SW18_R1 0x3\n#define BIT_SW18_R1(x) (((x) & BIT_MASK_SW18_R1) << BIT_SHIFT_SW18_R1)\n#define BITS_SW18_R1 (BIT_MASK_SW18_R1 << BIT_SHIFT_SW18_R1)\n#define BIT_CLEAR_SW18_R1(x) ((x) & (~BITS_SW18_R1))\n#define BIT_GET_SW18_R1(x) (((x) >> BIT_SHIFT_SW18_R1) & BIT_MASK_SW18_R1)\n#define BIT_SET_SW18_R1(x, v) (BIT_CLEAR_SW18_R1(x) | BIT_SW18_R1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_RXERR_MSK BIT(3)\n#define BIT_SDIO_TXERR_MSK BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_R3_L1_V1 2\n#define BIT_MASK_R3_L1_V1 0x3\n#define BIT_R3_L1_V1(x) (((x) & BIT_MASK_R3_L1_V1) << BIT_SHIFT_R3_L1_V1)\n#define BITS_R3_L1_V1 (BIT_MASK_R3_L1_V1 << BIT_SHIFT_R3_L1_V1)\n#define BIT_CLEAR_R3_L1_V1(x) ((x) & (~BITS_R3_L1_V1))\n#define BIT_GET_R3_L1_V1(x) (((x) >> BIT_SHIFT_R3_L1_V1) & BIT_MASK_R3_L1_V1)\n#define BIT_SET_R3_L1_V1(x, v) (BIT_CLEAR_R3_L1_V1(x) | BIT_R3_L1_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_SW18_C3 1\n#define BIT_MASK_SW18_C3 0x3\n#define BIT_SW18_C3(x) (((x) & BIT_MASK_SW18_C3) << BIT_SHIFT_SW18_C3)\n#define BITS_SW18_C3 (BIT_MASK_SW18_C3 << BIT_SHIFT_SW18_C3)\n#define BIT_CLEAR_SW18_C3(x) ((x) & (~BITS_SW18_C3))\n#define BIT_GET_SW18_C3(x) (((x) >> BIT_SHIFT_SW18_C3) & BIT_MASK_SW18_C3)\n#define BIT_SET_SW18_C3(x, v) (BIT_CLEAR_SW18_C3(x) | BIT_SW18_C3(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_SDIO_AVAL_MSK BIT(1)\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_C3_L_C3 1\n#define BIT_MASK_C3_L_C3 0x3\n#define BIT_C3_L_C3(x) (((x) & BIT_MASK_C3_L_C3) << BIT_SHIFT_C3_L_C3)\n#define BITS_C3_L_C3 (BIT_MASK_C3_L_C3 << BIT_SHIFT_C3_L_C3)\n#define BIT_CLEAR_C3_L_C3(x) ((x) & (~BITS_C3_L_C3))\n#define BIT_GET_C3_L_C3(x) (((x) >> BIT_SHIFT_C3_L_C3) & BIT_MASK_C3_L_C3)\n#define BIT_SET_C3_L_C3(x, v) (BIT_CLEAR_C3_L_C3(x) | BIT_C3_L_C3(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SW18_C2_BIT1 BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HIMR\t\t\t\t(Offset 0x10250014) */\n\n#define BIT_RX_REQUEST_MSK BIT(0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_SHIFT_R2_L1_V1 0\n#define BIT_MASK_R2_L1_V1 0x3\n#define BIT_R2_L1_V1(x) (((x) & BIT_MASK_R2_L1_V1) << BIT_SHIFT_R2_L1_V1)\n#define BITS_R2_L1_V1 (BIT_MASK_R2_L1_V1 << BIT_SHIFT_R2_L1_V1)\n#define BIT_CLEAR_R2_L1_V1(x) ((x) & (~BITS_R2_L1_V1))\n#define BIT_GET_R2_L1_V1(x) (((x) >> BIT_SHIFT_R2_L1_V1) & BIT_MASK_R2_L1_V1)\n#define BIT_SET_R2_L1_V1(x, v) (BIT_CLEAR_R2_L1_V1(x) | BIT_R2_L1_V1(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL2\t\t\t(Offset 0x0014) */\n\n#define BIT_C2_L_BIT1 BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL3\t\t\t(Offset 0x0018) */\n\n#define BIT_SPS18_OCP_DIS BIT(31)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HISR\t\t\t\t(Offset 0x10250018) */\n\n#define BIT_SDIO_CRCERR BIT(31)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SDIO_HISR\t\t\t\t(Offset 0x10250018) */\n\n#define BIT_IO_READY_SIGNAL_ERR BIT(31)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HISR\t\t\t\t(Offset 0x10250018) */\n\n#define BIT_SDIO_HSISR3_IND BIT(30)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SDIO_HISR\t\t\t\t(Offset 0x10250018) */\n\n#define BIT_TX_CRC BIT(30)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HISR\t\t\t\t(Offset 0x10250018) */\n\n#define BIT_SDIO_HSISR2_IND BIT(29)\n#define BIT_SDIO_HEISR_IND BIT(28)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HISR\t\t\t\t(Offset 0x10250018) */\n\n#define BIT_SDIO_CTWEND BIT(27)\n#define BIT_SDIO_ATIMEND_E BIT(26)\n#define BIT_SDIO_ATIMEND BIT(25)\n#define BIT_SDIO_OCPINT BIT(24)\n#define BIT_SDIO_PSTIMEOUT BIT(23)\n#define BIT_SDIO_GTINT4 BIT(22)\n#define BIT_SDIO_GTINT3 BIT(21)\n#define BIT_SDIO_HSISR_IND BIT(20)\n#define BIT_SDIO_CPWM2 BIT(19)\n#define BIT_SDIO_CPWM1 BIT(18)\n#define BIT_SDIO_C2HCMD_INT BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL3\t\t\t(Offset 0x0018) */\n\n#define BIT_SHIFT_SPS18_OCP_TH 16\n#define BIT_MASK_SPS18_OCP_TH 0x7fff\n#define BIT_SPS18_OCP_TH(x)                                                    \\\n\t(((x) & BIT_MASK_SPS18_OCP_TH) << BIT_SHIFT_SPS18_OCP_TH)\n#define BITS_SPS18_OCP_TH (BIT_MASK_SPS18_OCP_TH << BIT_SHIFT_SPS18_OCP_TH)\n#define BIT_CLEAR_SPS18_OCP_TH(x) ((x) & (~BITS_SPS18_OCP_TH))\n#define BIT_GET_SPS18_OCP_TH(x)                                                \\\n\t(((x) >> BIT_SHIFT_SPS18_OCP_TH) & BIT_MASK_SPS18_OCP_TH)\n#define BIT_SET_SPS18_OCP_TH(x, v)                                             \\\n\t(BIT_CLEAR_SPS18_OCP_TH(x) | BIT_SPS18_OCP_TH(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HISR\t\t\t\t(Offset 0x10250018) */\n\n#define BIT_SDIO_BCNERLY_INT BIT(16)\n#define BIT_SDIO_TXBCNERR BIT(7)\n#define BIT_SDIO_TXBCNOK BIT(6)\n#define BIT_SDIO_RXFOVW BIT(5)\n#define BIT_SDIO_TXFOVW BIT(4)\n#define BIT_SDIO_RXERR BIT(3)\n#define BIT_SDIO_TXERR BIT(2)\n#define BIT_SDIO_AVAL BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SWR_CTRL3\t\t\t(Offset 0x0018) */\n\n#define BIT_SHIFT_OCP_WINDOW 0\n#define BIT_MASK_OCP_WINDOW 0xffff\n#define BIT_OCP_WINDOW(x) (((x) & BIT_MASK_OCP_WINDOW) << BIT_SHIFT_OCP_WINDOW)\n#define BITS_OCP_WINDOW (BIT_MASK_OCP_WINDOW << BIT_SHIFT_OCP_WINDOW)\n#define BIT_CLEAR_OCP_WINDOW(x) ((x) & (~BITS_OCP_WINDOW))\n#define BIT_GET_OCP_WINDOW(x)                                                  \\\n\t(((x) >> BIT_SHIFT_OCP_WINDOW) & BIT_MASK_OCP_WINDOW)\n#define BIT_SET_OCP_WINDOW(x, v) (BIT_CLEAR_OCP_WINDOW(x) | BIT_OCP_WINDOW(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HISR\t\t\t\t(Offset 0x10250018) */\n\n#define BIT_RX_REQUEST BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RSV_CTRL\t\t\t\t(Offset 0x001C) */\n\n#define BIT_HREG_DBG BIT(23)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_RSV_CTRL\t\t\t\t(Offset 0x001C) */\n\n#define BIT_SHIFT_HREG_DBG_V1 12\n#define BIT_MASK_HREG_DBG_V1 0xfff\n#define BIT_HREG_DBG_V1(x)                                                     \\\n\t(((x) & BIT_MASK_HREG_DBG_V1) << BIT_SHIFT_HREG_DBG_V1)\n#define BITS_HREG_DBG_V1 (BIT_MASK_HREG_DBG_V1 << BIT_SHIFT_HREG_DBG_V1)\n#define BIT_CLEAR_HREG_DBG_V1(x) ((x) & (~BITS_HREG_DBG_V1))\n#define BIT_GET_HREG_DBG_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HREG_DBG_V1) & BIT_MASK_HREG_DBG_V1)\n#define BIT_SET_HREG_DBG_V1(x, v)                                              \\\n\t(BIT_CLEAR_HREG_DBG_V1(x) | BIT_HREG_DBG_V1(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RSV_CTRL\t\t\t\t(Offset 0x001C) */\n\n#define BIT_MCU_RST BIT(11)\n#define BIT_WLOCK_90 BIT(10)\n#define BIT_WLOCK_70 BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RSV_CTRL\t\t\t\t(Offset 0x001C) */\n\n#define BIT_WLMCUIOIF BIT(8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RSV_CTRL\t\t\t\t(Offset 0x001C) */\n\n#define BIT_WLOCK_78 BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RSV_CTRL\t\t\t\t(Offset 0x001C) */\n\n#define BIT_LOCK_ALL_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RSV_CTRL\t\t\t\t(Offset 0x001C) */\n\n#define BIT_R_DIS_PRST BIT(6)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RSV_CTRL\t\t\t\t(Offset 0x001C) */\n\n#define BIT_R_DIS_PRST_1 BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RSV_CTRL\t\t\t\t(Offset 0x001C) */\n\n#define BIT_WLOCK_1C_B6 BIT(5)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RSV_CTRL\t\t\t\t(Offset 0x001C) */\n\n#define BIT_R_DIS_PRST_0 BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RSV_CTRL\t\t\t\t(Offset 0x001C) */\n\n#define BIT_WLOCK_40 BIT(4)\n#define BIT_WLOCK_08 BIT(3)\n#define BIT_WLOCK_04 BIT(2)\n#define BIT_WLOCK_00 BIT(1)\n#define BIT_WLOCK_ALL BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_RX_REQ_LEN\t\t\t(Offset 0x1025001C) */\n\n#define BIT_SHIFT_RX_REQ_LEN_V1 0\n#define BIT_MASK_RX_REQ_LEN_V1 0x3ffff\n#define BIT_RX_REQ_LEN_V1(x)                                                   \\\n\t(((x) & BIT_MASK_RX_REQ_LEN_V1) << BIT_SHIFT_RX_REQ_LEN_V1)\n#define BITS_RX_REQ_LEN_V1 (BIT_MASK_RX_REQ_LEN_V1 << BIT_SHIFT_RX_REQ_LEN_V1)\n#define BIT_CLEAR_RX_REQ_LEN_V1(x) ((x) & (~BITS_RX_REQ_LEN_V1))\n#define BIT_GET_RX_REQ_LEN_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_RX_REQ_LEN_V1) & BIT_MASK_RX_REQ_LEN_V1)\n#define BIT_SET_RX_REQ_LEN_V1(x, v)                                            \\\n\t(BIT_CLEAR_RX_REQ_LEN_V1(x) | BIT_RX_REQ_LEN_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RF_CTRL\t\t\t\t(Offset 0x001F) */\n\n#define BIT_RF_SDMRSTB BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RF0_CTRL\t\t\t\t(Offset 0x001F) */\n\n#define BIT_RF0_SDMRSTB BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RF_CTRL\t\t\t\t(Offset 0x001F) */\n\n#define BIT_RF_RSTB BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RF0_CTRL\t\t\t\t(Offset 0x001F) */\n\n#define BIT_RF0_RSTB BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RF_CTRL\t\t\t\t(Offset 0x001F) */\n\n#define BIT_RF_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RF0_CTRL\t\t\t\t(Offset 0x001F) */\n\n#define BIT_RF0_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_FREE_TXPG_SEQ_V1\t\t(Offset 0x1025001F) */\n\n#define BIT_SHIFT_FREE_TXPG_SEQ 0\n#define BIT_MASK_FREE_TXPG_SEQ 0xff\n#define BIT_FREE_TXPG_SEQ(x)                                                   \\\n\t(((x) & BIT_MASK_FREE_TXPG_SEQ) << BIT_SHIFT_FREE_TXPG_SEQ)\n#define BITS_FREE_TXPG_SEQ (BIT_MASK_FREE_TXPG_SEQ << BIT_SHIFT_FREE_TXPG_SEQ)\n#define BIT_CLEAR_FREE_TXPG_SEQ(x) ((x) & (~BITS_FREE_TXPG_SEQ))\n#define BIT_GET_FREE_TXPG_SEQ(x)                                               \\\n\t(((x) >> BIT_SHIFT_FREE_TXPG_SEQ) & BIT_MASK_FREE_TXPG_SEQ)\n#define BIT_SET_FREE_TXPG_SEQ(x, v)                                            \\\n\t(BIT_CLEAR_FREE_TXPG_SEQ(x) | BIT_FREE_TXPG_SEQ(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_R_SYM_WLPON_EMEM1_EN BIT(31)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_LPLDH12_RSV1 BIT(31)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_R_SYM_WLPON_EMEM0_EN BIT(30)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_LPLDH12_RSV0 BIT(30)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_SHIFT_LPLDH12_RSV 29\n#define BIT_MASK_LPLDH12_RSV 0x7\n#define BIT_LPLDH12_RSV(x)                                                     \\\n\t(((x) & BIT_MASK_LPLDH12_RSV) << BIT_SHIFT_LPLDH12_RSV)\n#define BITS_LPLDH12_RSV (BIT_MASK_LPLDH12_RSV << BIT_SHIFT_LPLDH12_RSV)\n#define BIT_CLEAR_LPLDH12_RSV(x) ((x) & (~BITS_LPLDH12_RSV))\n#define BIT_GET_LPLDH12_RSV(x)                                                 \\\n\t(((x) >> BIT_SHIFT_LPLDH12_RSV) & BIT_MASK_LPLDH12_RSV)\n#define BIT_SET_LPLDH12_RSV(x, v)                                              \\\n\t(BIT_CLEAR_LPLDH12_RSV(x) | BIT_LPLDH12_RSV(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_LPLDH12_SLP BIT(28)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_R_SYM_WLPOFF_P4EN BIT(28)\n#define BIT_R_SYM_WLPOFF_P3EN BIT(27)\n#define BIT_R_SYM_WLPOFF_P2EN BIT(26)\n#define BIT_R_SYM_WLPOFF_P1EN BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_SHIFT_LPLDH12_VADJ 24\n#define BIT_MASK_LPLDH12_VADJ 0xf\n#define BIT_LPLDH12_VADJ(x)                                                    \\\n\t(((x) & BIT_MASK_LPLDH12_VADJ) << BIT_SHIFT_LPLDH12_VADJ)\n#define BITS_LPLDH12_VADJ (BIT_MASK_LPLDH12_VADJ << BIT_SHIFT_LPLDH12_VADJ)\n#define BIT_CLEAR_LPLDH12_VADJ(x) ((x) & (~BITS_LPLDH12_VADJ))\n#define BIT_GET_LPLDH12_VADJ(x)                                                \\\n\t(((x) >> BIT_SHIFT_LPLDH12_VADJ) & BIT_MASK_LPLDH12_VADJ)\n#define BIT_SET_LPLDH12_VADJ(x, v)                                             \\\n\t(BIT_CLEAR_LPLDH12_VADJ(x) | BIT_LPLDH12_VADJ(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_R_SYM_WLPOFF_EN BIT(24)\n#define BIT_R_SYM_WLPON_P3EN BIT(21)\n#define BIT_R_SYM_WLPON_P2EN BIT(20)\n#define BIT_R_SYM_WLPON_P1EN BIT(19)\n#define BIT_R_SYM_WLPON_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_PCIE_CALIB_EN BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_LDH12_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_FREE_TXPG\t\t\t(Offset 0x10250020) */\n\n#define BIT_SHIFT_MID_FREEPG_V1 16\n#define BIT_MASK_MID_FREEPG_V1 0xfff\n#define BIT_MID_FREEPG_V1(x)                                                   \\\n\t(((x) & BIT_MASK_MID_FREEPG_V1) << BIT_SHIFT_MID_FREEPG_V1)\n#define BITS_MID_FREEPG_V1 (BIT_MASK_MID_FREEPG_V1 << BIT_SHIFT_MID_FREEPG_V1)\n#define BIT_CLEAR_MID_FREEPG_V1(x) ((x) & (~BITS_MID_FREEPG_V1))\n#define BIT_GET_MID_FREEPG_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_MID_FREEPG_V1) & BIT_MASK_MID_FREEPG_V1)\n#define BIT_SET_MID_FREEPG_V1(x, v)                                            \\\n\t(BIT_CLEAR_MID_FREEPG_V1(x) | BIT_MID_FREEPG_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_R_SYM_LDOV12D_STBY BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_BB_POWER_CUT_CTRL_BY_BB BIT(15)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_WLBBOFF_BIG_PWC_EN BIT(14)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_SHIFT_XTAL_GM_REP_V8 13\n#define BIT_MASK_XTAL_GM_REP_V8 0x3\n#define BIT_XTAL_GM_REP_V8(x)                                                  \\\n\t(((x) & BIT_MASK_XTAL_GM_REP_V8) << BIT_SHIFT_XTAL_GM_REP_V8)\n#define BITS_XTAL_GM_REP_V8                                                    \\\n\t(BIT_MASK_XTAL_GM_REP_V8 << BIT_SHIFT_XTAL_GM_REP_V8)\n#define BIT_CLEAR_XTAL_GM_REP_V8(x) ((x) & (~BITS_XTAL_GM_REP_V8))\n#define BIT_GET_XTAL_GM_REP_V8(x)                                              \\\n\t(((x) >> BIT_SHIFT_XTAL_GM_REP_V8) & BIT_MASK_XTAL_GM_REP_V8)\n#define BIT_SET_XTAL_GM_REP_V8(x, v)                                           \\\n\t(BIT_CLEAR_XTAL_GM_REP_V8(x) | BIT_XTAL_GM_REP_V8(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_WLBBOFF_SMALL_PWC_EN BIT(13)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_POW_REGU_P3 BIT(12)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_WLMACOFF_BIG_PWC_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_POW_REGU_P2 BIT(11)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_WLPON_PWC_EN BIT(11)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_POW_REGU_P1 BIT(10)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_MEM_DS_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_R_SYM_WLBBOFF1_P4_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_LDOV12W_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_R_SYM_WLBBOFF1_P3_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_SHIFT_ANAPAR_RFC2 8\n#define BIT_MASK_ANAPAR_RFC2 0xff\n#define BIT_ANAPAR_RFC2(x)                                                     \\\n\t(((x) & BIT_MASK_ANAPAR_RFC2) << BIT_SHIFT_ANAPAR_RFC2)\n#define BITS_ANAPAR_RFC2 (BIT_MASK_ANAPAR_RFC2 << BIT_SHIFT_ANAPAR_RFC2)\n#define BIT_CLEAR_ANAPAR_RFC2(x) ((x) & (~BITS_ANAPAR_RFC2))\n#define BIT_GET_ANAPAR_RFC2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ANAPAR_RFC2) & BIT_MASK_ANAPAR_RFC2)\n#define BIT_SET_ANAPAR_RFC2(x, v)                                              \\\n\t(BIT_CLEAR_ANAPAR_RFC2(x) | BIT_ANAPAR_RFC2(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_EX_XTAL_DRV_DIGI BIT(7)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_R_SYM_WLBBOFF1_P2_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_EX_XTAL_DRV_USB BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_R_SYM_WLBBOFF1_P1_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_EX_XTAL_DRV_AFE BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_SHIFT_LDA12_VOADJ 4\n#define BIT_MASK_LDA12_VOADJ 0xf\n#define BIT_LDA12_VOADJ(x)                                                     \\\n\t(((x) & BIT_MASK_LDA12_VOADJ) << BIT_SHIFT_LDA12_VOADJ)\n#define BITS_LDA12_VOADJ (BIT_MASK_LDA12_VOADJ << BIT_SHIFT_LDA12_VOADJ)\n#define BIT_CLEAR_LDA12_VOADJ(x) ((x) & (~BITS_LDA12_VOADJ))\n#define BIT_GET_LDA12_VOADJ(x)                                                 \\\n\t(((x) >> BIT_SHIFT_LDA12_VOADJ) & BIT_MASK_LDA12_VOADJ)\n#define BIT_SET_LDA12_VOADJ(x, v)                                              \\\n\t(BIT_CLEAR_LDA12_VOADJ(x) | BIT_LDA12_VOADJ(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_EX_XTAL_DRV_RF2 BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_R_SYM_WLBBOFF_P4_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_REG_VOS BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_EX_XTAL_DRV_RF1 BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_R_SYM_WLBBOFF_P3_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_POW_REGU_P0 BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_R_SYM_WLBBOFF_P2_EN BIT(2)\n#define BIT_R_SYM_WLBBOFF_P1_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_LDA12_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_POW_PLL_LDO BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_FREE_TXPG\t\t\t(Offset 0x10250020) */\n\n#define BIT_SHIFT_HIQ_FREEPG_V1 0\n#define BIT_MASK_HIQ_FREEPG_V1 0xfff\n#define BIT_HIQ_FREEPG_V1(x)                                                   \\\n\t(((x) & BIT_MASK_HIQ_FREEPG_V1) << BIT_SHIFT_HIQ_FREEPG_V1)\n#define BITS_HIQ_FREEPG_V1 (BIT_MASK_HIQ_FREEPG_V1 << BIT_SHIFT_HIQ_FREEPG_V1)\n#define BIT_CLEAR_HIQ_FREEPG_V1(x) ((x) & (~BITS_HIQ_FREEPG_V1))\n#define BIT_GET_HIQ_FREEPG_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_HIQ_FREEPG_V1) & BIT_MASK_HIQ_FREEPG_V1)\n#define BIT_SET_HIQ_FREEPG_V1(x, v)                                            \\\n\t(BIT_CLEAR_HIQ_FREEPG_V1(x) | BIT_HIQ_FREEPG_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_R_SYM_WLBBOFF_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_LDO_CTRL\t\t\t(Offset 0x0020) */\n\n#define BIT_SHIFT_ANAPAR_RFC1 0\n#define BIT_MASK_ANAPAR_RFC1 0xff\n#define BIT_ANAPAR_RFC1(x)                                                     \\\n\t(((x) & BIT_MASK_ANAPAR_RFC1) << BIT_SHIFT_ANAPAR_RFC1)\n#define BITS_ANAPAR_RFC1 (BIT_MASK_ANAPAR_RFC1 << BIT_SHIFT_ANAPAR_RFC1)\n#define BIT_CLEAR_ANAPAR_RFC1(x) ((x) & (~BITS_ANAPAR_RFC1))\n#define BIT_GET_ANAPAR_RFC1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ANAPAR_RFC1) & BIT_MASK_ANAPAR_RFC1)\n#define BIT_SET_ANAPAR_RFC1(x, v)                                              \\\n\t(BIT_CLEAR_ANAPAR_RFC1(x) | BIT_ANAPAR_RFC1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_AGPIO_GPE BIT(31)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XQSEL_V3 BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_REG_CC 30\n#define BIT_MASK_REG_CC 0x3\n#define BIT_REG_CC(x) (((x) & BIT_MASK_REG_CC) << BIT_SHIFT_REG_CC)\n#define BITS_REG_CC (BIT_MASK_REG_CC << BIT_SHIFT_REG_CC)\n#define BIT_CLEAR_REG_CC(x) ((x) & (~BITS_REG_CC))\n#define BIT_GET_REG_CC(x) (((x) >> BIT_SHIFT_REG_CC) & BIT_MASK_REG_CC)\n#define BIT_SET_REG_CC(x, v) (BIT_CLEAR_REG_CC(x) | BIT_REG_CC(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_CKDELAY_AFE_V1 BIT(30)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_CKDLY_DIG BIT(28)\n#define BIT_CKDLY_USB BIT(27)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_GPIO_V1 27\n#define BIT_MASK_XTAL_GPIO_V1 0x7\n#define BIT_XTAL_GPIO_V1(x)                                                    \\\n\t(((x) & BIT_MASK_XTAL_GPIO_V1) << BIT_SHIFT_XTAL_GPIO_V1)\n#define BITS_XTAL_GPIO_V1 (BIT_MASK_XTAL_GPIO_V1 << BIT_SHIFT_XTAL_GPIO_V1)\n#define BIT_CLEAR_XTAL_GPIO_V1(x) ((x) & (~BITS_XTAL_GPIO_V1))\n#define BIT_GET_XTAL_GPIO_V1(x)                                                \\\n\t(((x) >> BIT_SHIFT_XTAL_GPIO_V1) & BIT_MASK_XTAL_GPIO_V1)\n#define BIT_SET_XTAL_GPIO_V1(x, v)                                             \\\n\t(BIT_CLEAR_XTAL_GPIO_V1(x) | BIT_XTAL_GPIO_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_CKDLY_AFE BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_CAP_XI 25\n#define BIT_MASK_XTAL_CAP_XI 0x3f\n#define BIT_XTAL_CAP_XI(x)                                                     \\\n\t(((x) & BIT_MASK_XTAL_CAP_XI) << BIT_SHIFT_XTAL_CAP_XI)\n#define BITS_XTAL_CAP_XI (BIT_MASK_XTAL_CAP_XI << BIT_SHIFT_XTAL_CAP_XI)\n#define BIT_CLEAR_XTAL_CAP_XI(x) ((x) & (~BITS_XTAL_CAP_XI))\n#define BIT_GET_XTAL_CAP_XI(x)                                                 \\\n\t(((x) >> BIT_SHIFT_XTAL_CAP_XI) & BIT_MASK_XTAL_CAP_XI)\n#define BIT_SET_XTAL_CAP_XI(x, v)                                              \\\n\t(BIT_CLEAR_XTAL_CAP_XI(x) | BIT_XTAL_CAP_XI(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_DIG_DRV_1_TO_0 25\n#define BIT_MASK_XTAL_DIG_DRV_1_TO_0 0x3\n#define BIT_XTAL_DIG_DRV_1_TO_0(x)                                             \\\n\t(((x) & BIT_MASK_XTAL_DIG_DRV_1_TO_0) << BIT_SHIFT_XTAL_DIG_DRV_1_TO_0)\n#define BITS_XTAL_DIG_DRV_1_TO_0                                               \\\n\t(BIT_MASK_XTAL_DIG_DRV_1_TO_0 << BIT_SHIFT_XTAL_DIG_DRV_1_TO_0)\n#define BIT_CLEAR_XTAL_DIG_DRV_1_TO_0(x) ((x) & (~BITS_XTAL_DIG_DRV_1_TO_0))\n#define BIT_GET_XTAL_DIG_DRV_1_TO_0(x)                                         \\\n\t(((x) >> BIT_SHIFT_XTAL_DIG_DRV_1_TO_0) & BIT_MASK_XTAL_DIG_DRV_1_TO_0)\n#define BIT_SET_XTAL_DIG_DRV_1_TO_0(x, v)                                      \\\n\t(BIT_CLEAR_XTAL_DIG_DRV_1_TO_0(x) | BIT_XTAL_DIG_DRV_1_TO_0(v))\n\n#define BIT_XTAL_GDIG BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_GPIO 23\n#define BIT_MASK_XTAL_GPIO 0x7\n#define BIT_XTAL_GPIO(x) (((x) & BIT_MASK_XTAL_GPIO) << BIT_SHIFT_XTAL_GPIO)\n#define BITS_XTAL_GPIO (BIT_MASK_XTAL_GPIO << BIT_SHIFT_XTAL_GPIO)\n#define BIT_CLEAR_XTAL_GPIO(x) ((x) & (~BITS_XTAL_GPIO))\n#define BIT_GET_XTAL_GPIO(x) (((x) >> BIT_SHIFT_XTAL_GPIO) & BIT_MASK_XTAL_GPIO)\n#define BIT_SET_XTAL_GPIO(x, v) (BIT_CLEAR_XTAL_GPIO(x) | BIT_XTAL_GPIO(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_DRV_DIGI 23\n#define BIT_MASK_XTAL_DRV_DIGI 0x3\n#define BIT_XTAL_DRV_DIGI(x)                                                   \\\n\t(((x) & BIT_MASK_XTAL_DRV_DIGI) << BIT_SHIFT_XTAL_DRV_DIGI)\n#define BITS_XTAL_DRV_DIGI (BIT_MASK_XTAL_DRV_DIGI << BIT_SHIFT_XTAL_DRV_DIGI)\n#define BIT_CLEAR_XTAL_DRV_DIGI(x) ((x) & (~BITS_XTAL_DRV_DIGI))\n#define BIT_GET_XTAL_DRV_DIGI(x)                                               \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_DIGI) & BIT_MASK_XTAL_DRV_DIGI)\n#define BIT_SET_XTAL_DRV_DIGI(x, v)                                            \\\n\t(BIT_CLEAR_XTAL_DRV_DIGI(x) | BIT_XTAL_DRV_DIGI(v))\n\n#define BIT_XTAL_DRV_USB_BIT1 BIT(22)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_DRV_RF_LATCH_V2 BIT(22)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0 22\n#define BIT_MASK_XTAL_RDRV_RF2_1_TO_0 0x3\n#define BIT_XTAL_RDRV_RF2_1_TO_0(x)                                            \\\n\t(((x) & BIT_MASK_XTAL_RDRV_RF2_1_TO_0)                                 \\\n\t << BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0)\n#define BITS_XTAL_RDRV_RF2_1_TO_0                                              \\\n\t(BIT_MASK_XTAL_RDRV_RF2_1_TO_0 << BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0)\n#define BIT_CLEAR_XTAL_RDRV_RF2_1_TO_0(x) ((x) & (~BITS_XTAL_RDRV_RF2_1_TO_0))\n#define BIT_GET_XTAL_RDRV_RF2_1_TO_0(x)                                        \\\n\t(((x) >> BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0) &                             \\\n\t BIT_MASK_XTAL_RDRV_RF2_1_TO_0)\n#define BIT_SET_XTAL_RDRV_RF2_1_TO_0(x, v)                                     \\\n\t(BIT_CLEAR_XTAL_RDRV_RF2_1_TO_0(x) | BIT_XTAL_RDRV_RF2_1_TO_0(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_GMN_4 BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_MAC_CLK_SEL 20\n#define BIT_MASK_MAC_CLK_SEL 0x3\n#define BIT_MAC_CLK_SEL(x)                                                     \\\n\t(((x) & BIT_MASK_MAC_CLK_SEL) << BIT_SHIFT_MAC_CLK_SEL)\n#define BITS_MAC_CLK_SEL (BIT_MASK_MAC_CLK_SEL << BIT_SHIFT_MAC_CLK_SEL)\n#define BIT_CLEAR_MAC_CLK_SEL(x) ((x) & (~BITS_MAC_CLK_SEL))\n#define BIT_GET_MAC_CLK_SEL(x)                                                 \\\n\t(((x) >> BIT_SHIFT_MAC_CLK_SEL) & BIT_MASK_MAC_CLK_SEL)\n#define BIT_SET_MAC_CLK_SEL(x, v)                                              \\\n\t(BIT_CLEAR_MAC_CLK_SEL(x) | BIT_MAC_CLK_SEL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_DRV_USB_BIT0 BIT(19)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_RDRV_1_TO_0 19\n#define BIT_MASK_XTAL_RDRV_1_TO_0 0x3\n#define BIT_XTAL_RDRV_1_TO_0(x)                                                \\\n\t(((x) & BIT_MASK_XTAL_RDRV_1_TO_0) << BIT_SHIFT_XTAL_RDRV_1_TO_0)\n#define BITS_XTAL_RDRV_1_TO_0                                                  \\\n\t(BIT_MASK_XTAL_RDRV_1_TO_0 << BIT_SHIFT_XTAL_RDRV_1_TO_0)\n#define BIT_CLEAR_XTAL_RDRV_1_TO_0(x) ((x) & (~BITS_XTAL_RDRV_1_TO_0))\n#define BIT_GET_XTAL_RDRV_1_TO_0(x)                                            \\\n\t(((x) >> BIT_SHIFT_XTAL_RDRV_1_TO_0) & BIT_MASK_XTAL_RDRV_1_TO_0)\n#define BIT_SET_XTAL_RDRV_1_TO_0(x, v)                                         \\\n\t(BIT_CLEAR_XTAL_RDRV_1_TO_0(x) | BIT_XTAL_RDRV_1_TO_0(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_DIG_DRV 18\n#define BIT_MASK_XTAL_DIG_DRV 0x3\n#define BIT_XTAL_DIG_DRV(x)                                                    \\\n\t(((x) & BIT_MASK_XTAL_DIG_DRV) << BIT_SHIFT_XTAL_DIG_DRV)\n#define BITS_XTAL_DIG_DRV (BIT_MASK_XTAL_DIG_DRV << BIT_SHIFT_XTAL_DIG_DRV)\n#define BIT_CLEAR_XTAL_DIG_DRV(x) ((x) & (~BITS_XTAL_DIG_DRV))\n#define BIT_GET_XTAL_DIG_DRV(x)                                                \\\n\t(((x) >> BIT_SHIFT_XTAL_DIG_DRV) & BIT_MASK_XTAL_DIG_DRV)\n#define BIT_SET_XTAL_DIG_DRV(x, v)                                             \\\n\t(BIT_CLEAR_XTAL_DIG_DRV(x) | BIT_XTAL_DIG_DRV(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_GMP_4 BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_GATE_DIG BIT(17)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_DRV_AFE 17\n#define BIT_MASK_XTAL_DRV_AFE 0x3\n#define BIT_XTAL_DRV_AFE(x)                                                    \\\n\t(((x) & BIT_MASK_XTAL_DRV_AFE) << BIT_SHIFT_XTAL_DRV_AFE)\n#define BITS_XTAL_DRV_AFE (BIT_MASK_XTAL_DRV_AFE << BIT_SHIFT_XTAL_DRV_AFE)\n#define BIT_CLEAR_XTAL_DRV_AFE(x) ((x) & (~BITS_XTAL_DRV_AFE))\n#define BIT_GET_XTAL_DRV_AFE(x)                                                \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_AFE) & BIT_MASK_XTAL_DRV_AFE)\n#define BIT_SET_XTAL_DRV_AFE(x, v)                                             \\\n\t(BIT_CLEAR_XTAL_DRV_AFE(x) | BIT_XTAL_DRV_AFE(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_FREE_TXPG2\t\t\t(Offset 0x10250024) */\n\n#define BIT_SHIFT_PUB_FREEPG_V1 16\n#define BIT_MASK_PUB_FREEPG_V1 0xfff\n#define BIT_PUB_FREEPG_V1(x)                                                   \\\n\t(((x) & BIT_MASK_PUB_FREEPG_V1) << BIT_SHIFT_PUB_FREEPG_V1)\n#define BITS_PUB_FREEPG_V1 (BIT_MASK_PUB_FREEPG_V1 << BIT_SHIFT_PUB_FREEPG_V1)\n#define BIT_CLEAR_PUB_FREEPG_V1(x) ((x) & (~BITS_PUB_FREEPG_V1))\n#define BIT_GET_PUB_FREEPG_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_PUB_FREEPG_V1) & BIT_MASK_PUB_FREEPG_V1)\n#define BIT_SET_PUB_FREEPG_V1(x, v)                                            \\\n\t(BIT_CLEAR_PUB_FREEPG_V1(x) | BIT_PUB_FREEPG_V1(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_ADRV_1_TO_0 16\n#define BIT_MASK_XTAL_ADRV_1_TO_0 0x3\n#define BIT_XTAL_ADRV_1_TO_0(x)                                                \\\n\t(((x) & BIT_MASK_XTAL_ADRV_1_TO_0) << BIT_SHIFT_XTAL_ADRV_1_TO_0)\n#define BITS_XTAL_ADRV_1_TO_0                                                  \\\n\t(BIT_MASK_XTAL_ADRV_1_TO_0 << BIT_SHIFT_XTAL_ADRV_1_TO_0)\n#define BIT_CLEAR_XTAL_ADRV_1_TO_0(x) ((x) & (~BITS_XTAL_ADRV_1_TO_0))\n#define BIT_GET_XTAL_ADRV_1_TO_0(x)                                            \\\n\t(((x) >> BIT_SHIFT_XTAL_ADRV_1_TO_0) & BIT_MASK_XTAL_ADRV_1_TO_0)\n#define BIT_SET_XTAL_ADRV_1_TO_0(x, v)                                         \\\n\t(BIT_CLEAR_XTAL_ADRV_1_TO_0(x) | BIT_XTAL_ADRV_1_TO_0(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_RF_DRV 15\n#define BIT_MASK_XTAL_RF_DRV 0x3\n#define BIT_XTAL_RF_DRV(x)                                                     \\\n\t(((x) & BIT_MASK_XTAL_RF_DRV) << BIT_SHIFT_XTAL_RF_DRV)\n#define BITS_XTAL_RF_DRV (BIT_MASK_XTAL_RF_DRV << BIT_SHIFT_XTAL_RF_DRV)\n#define BIT_CLEAR_XTAL_RF_DRV(x) ((x) & (~BITS_XTAL_RF_DRV))\n#define BIT_GET_XTAL_RF_DRV(x)                                                 \\\n\t(((x) >> BIT_SHIFT_XTAL_RF_DRV) & BIT_MASK_XTAL_RF_DRV)\n#define BIT_SET_XTAL_RF_DRV(x, v)                                              \\\n\t(BIT_CLEAR_XTAL_RF_DRV(x) | BIT_XTAL_RF_DRV(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_DRV_RF2 15\n#define BIT_MASK_XTAL_DRV_RF2 0x3\n#define BIT_XTAL_DRV_RF2(x)                                                    \\\n\t(((x) & BIT_MASK_XTAL_DRV_RF2) << BIT_SHIFT_XTAL_DRV_RF2)\n#define BITS_XTAL_DRV_RF2 (BIT_MASK_XTAL_DRV_RF2 << BIT_SHIFT_XTAL_DRV_RF2)\n#define BIT_CLEAR_XTAL_DRV_RF2(x) ((x) & (~BITS_XTAL_DRV_RF2))\n#define BIT_GET_XTAL_DRV_RF2(x)                                                \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_RF2) & BIT_MASK_XTAL_DRV_RF2)\n#define BIT_SET_XTAL_DRV_RF2(x, v)                                             \\\n\t(BIT_CLEAR_XTAL_DRV_RF2(x) | BIT_XTAL_DRV_RF2(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_GAFE BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_RF_GATE BIT(14)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_DDRV_1_TO_0 13\n#define BIT_MASK_XTAL_DDRV_1_TO_0 0x3\n#define BIT_XTAL_DDRV_1_TO_0(x)                                                \\\n\t(((x) & BIT_MASK_XTAL_DDRV_1_TO_0) << BIT_SHIFT_XTAL_DDRV_1_TO_0)\n#define BITS_XTAL_DDRV_1_TO_0                                                  \\\n\t(BIT_MASK_XTAL_DDRV_1_TO_0 << BIT_SHIFT_XTAL_DDRV_1_TO_0)\n#define BIT_CLEAR_XTAL_DDRV_1_TO_0(x) ((x) & (~BITS_XTAL_DDRV_1_TO_0))\n#define BIT_GET_XTAL_DDRV_1_TO_0(x)                                            \\\n\t(((x) >> BIT_SHIFT_XTAL_DDRV_1_TO_0) & BIT_MASK_XTAL_DDRV_1_TO_0)\n#define BIT_SET_XTAL_DDRV_1_TO_0(x, v)                                         \\\n\t(BIT_CLEAR_XTAL_DDRV_1_TO_0(x) | BIT_XTAL_DDRV_1_TO_0(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_AFE_DRV 12\n#define BIT_MASK_XTAL_AFE_DRV 0x3\n#define BIT_XTAL_AFE_DRV(x)                                                    \\\n\t(((x) & BIT_MASK_XTAL_AFE_DRV) << BIT_SHIFT_XTAL_AFE_DRV)\n#define BITS_XTAL_AFE_DRV (BIT_MASK_XTAL_AFE_DRV << BIT_SHIFT_XTAL_AFE_DRV)\n#define BIT_CLEAR_XTAL_AFE_DRV(x) ((x) & (~BITS_XTAL_AFE_DRV))\n#define BIT_GET_XTAL_AFE_DRV(x)                                                \\\n\t(((x) >> BIT_SHIFT_XTAL_AFE_DRV) & BIT_MASK_XTAL_AFE_DRV)\n#define BIT_SET_XTAL_AFE_DRV(x, v)                                             \\\n\t(BIT_CLEAR_XTAL_AFE_DRV(x) | BIT_XTAL_AFE_DRV(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_DELAY_DIGI BIT(12)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_GUSB BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_GATE_AFE BIT(11)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_DELAY_USB BIT(11)\n#define BIT_XTAL_DELAY_AFE BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_USB_DRV 9\n#define BIT_MASK_XTAL_USB_DRV 0x3\n#define BIT_XTAL_USB_DRV(x)                                                    \\\n\t(((x) & BIT_MASK_XTAL_USB_DRV) << BIT_SHIFT_XTAL_USB_DRV)\n#define BITS_XTAL_USB_DRV (BIT_MASK_XTAL_USB_DRV << BIT_SHIFT_XTAL_USB_DRV)\n#define BIT_CLEAR_XTAL_USB_DRV(x) ((x) & (~BITS_XTAL_USB_DRV))\n#define BIT_GET_XTAL_USB_DRV(x)                                                \\\n\t(((x) >> BIT_SHIFT_XTAL_USB_DRV) & BIT_MASK_XTAL_USB_DRV)\n#define BIT_SET_XTAL_USB_DRV(x, v)                                             \\\n\t(BIT_CLEAR_XTAL_USB_DRV(x) | BIT_XTAL_USB_DRV(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_LP_V1 BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_GATE_USB BIT(8)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_GM_SEP_V1 BIT(8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_GMN_3_TO_0 8\n#define BIT_MASK_XTAL_GMN_3_TO_0 0xf\n#define BIT_XTAL_GMN_3_TO_0(x)                                                 \\\n\t(((x) & BIT_MASK_XTAL_GMN_3_TO_0) << BIT_SHIFT_XTAL_GMN_3_TO_0)\n#define BITS_XTAL_GMN_3_TO_0                                                   \\\n\t(BIT_MASK_XTAL_GMN_3_TO_0 << BIT_SHIFT_XTAL_GMN_3_TO_0)\n#define BIT_CLEAR_XTAL_GMN_3_TO_0(x) ((x) & (~BITS_XTAL_GMN_3_TO_0))\n#define BIT_GET_XTAL_GMN_3_TO_0(x)                                             \\\n\t(((x) >> BIT_SHIFT_XTAL_GMN_3_TO_0) & BIT_MASK_XTAL_GMN_3_TO_0)\n#define BIT_SET_XTAL_GMN_3_TO_0(x, v)                                          \\\n\t(BIT_CLEAR_XTAL_GMN_3_TO_0(x) | BIT_XTAL_GMN_3_TO_0(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_LDO_VREF_V1 BIT(7)\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_LDO_VREF 7\n#define BIT_MASK_XTAL_LDO_VREF 0x7\n#define BIT_XTAL_LDO_VREF(x)                                                   \\\n\t(((x) & BIT_MASK_XTAL_LDO_VREF) << BIT_SHIFT_XTAL_LDO_VREF)\n#define BITS_XTAL_LDO_VREF (BIT_MASK_XTAL_LDO_VREF << BIT_SHIFT_XTAL_LDO_VREF)\n#define BIT_CLEAR_XTAL_LDO_VREF(x) ((x) & (~BITS_XTAL_LDO_VREF))\n#define BIT_GET_XTAL_LDO_VREF(x)                                               \\\n\t(((x) >> BIT_SHIFT_XTAL_LDO_VREF) & BIT_MASK_XTAL_LDO_VREF)\n#define BIT_SET_XTAL_LDO_VREF(x, v)                                            \\\n\t(BIT_CLEAR_XTAL_LDO_VREF(x) | BIT_XTAL_LDO_VREF(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_XQSEL_RF BIT(6)\n#define BIT_XTAL_XQSEL BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_GMP 4\n#define BIT_MASK_XTAL_GMP 0xf\n#define BIT_XTAL_GMP(x) (((x) & BIT_MASK_XTAL_GMP) << BIT_SHIFT_XTAL_GMP)\n#define BITS_XTAL_GMP (BIT_MASK_XTAL_GMP << BIT_SHIFT_XTAL_GMP)\n#define BIT_CLEAR_XTAL_GMP(x) ((x) & (~BITS_XTAL_GMP))\n#define BIT_GET_XTAL_GMP(x) (((x) >> BIT_SHIFT_XTAL_GMP) & BIT_MASK_XTAL_GMP)\n#define BIT_SET_XTAL_GMP(x, v) (BIT_CLEAR_XTAL_GMP(x) | BIT_XTAL_GMP(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_GMP_3_TO_0 4\n#define BIT_MASK_XTAL_GMP_3_TO_0 0xf\n#define BIT_XTAL_GMP_3_TO_0(x)                                                 \\\n\t(((x) & BIT_MASK_XTAL_GMP_3_TO_0) << BIT_SHIFT_XTAL_GMP_3_TO_0)\n#define BITS_XTAL_GMP_3_TO_0                                                   \\\n\t(BIT_MASK_XTAL_GMP_3_TO_0 << BIT_SHIFT_XTAL_GMP_3_TO_0)\n#define BIT_CLEAR_XTAL_GMP_3_TO_0(x) ((x) & (~BITS_XTAL_GMP_3_TO_0))\n#define BIT_GET_XTAL_GMP_3_TO_0(x)                                             \\\n\t(((x) >> BIT_SHIFT_XTAL_GMP_3_TO_0) & BIT_MASK_XTAL_GMP_3_TO_0)\n#define BIT_SET_XTAL_GMP_3_TO_0(x, v)                                          \\\n\t(BIT_CLEAR_XTAL_GMP_3_TO_0(x) | BIT_XTAL_GMP_3_TO_0(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_GMN_V2 3\n#define BIT_MASK_XTAL_GMN_V2 0x3\n#define BIT_XTAL_GMN_V2(x)                                                     \\\n\t(((x) & BIT_MASK_XTAL_GMN_V2) << BIT_SHIFT_XTAL_GMN_V2)\n#define BITS_XTAL_GMN_V2 (BIT_MASK_XTAL_GMN_V2 << BIT_SHIFT_XTAL_GMN_V2)\n#define BIT_CLEAR_XTAL_GMN_V2(x) ((x) & (~BITS_XTAL_GMN_V2))\n#define BIT_GET_XTAL_GMN_V2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_XTAL_GMN_V2) & BIT_MASK_XTAL_GMN_V2)\n#define BIT_SET_XTAL_GMN_V2(x, v)                                              \\\n\t(BIT_CLEAR_XTAL_GMN_V2(x) | BIT_XTAL_GMN_V2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_GMN_V1 3\n#define BIT_MASK_XTAL_GMN_V1 0x3\n#define BIT_XTAL_GMN_V1(x)                                                     \\\n\t(((x) & BIT_MASK_XTAL_GMN_V1) << BIT_SHIFT_XTAL_GMN_V1)\n#define BITS_XTAL_GMN_V1 (BIT_MASK_XTAL_GMN_V1 << BIT_SHIFT_XTAL_GMN_V1)\n#define BIT_CLEAR_XTAL_GMN_V1(x) ((x) & (~BITS_XTAL_GMN_V1))\n#define BIT_GET_XTAL_GMN_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_XTAL_GMN_V1) & BIT_MASK_XTAL_GMN_V1)\n#define BIT_SET_XTAL_GMN_V1(x, v)                                              \\\n\t(BIT_CLEAR_XTAL_GMN_V1(x) | BIT_XTAL_GMN_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_LDO_VCM 2\n#define BIT_MASK_XTAL_LDO_VCM 0x3\n#define BIT_XTAL_LDO_VCM(x)                                                    \\\n\t(((x) & BIT_MASK_XTAL_LDO_VCM) << BIT_SHIFT_XTAL_LDO_VCM)\n#define BITS_XTAL_LDO_VCM (BIT_MASK_XTAL_LDO_VCM << BIT_SHIFT_XTAL_LDO_VCM)\n#define BIT_CLEAR_XTAL_LDO_VCM(x) ((x) & (~BITS_XTAL_LDO_VCM))\n#define BIT_GET_XTAL_LDO_VCM(x)                                                \\\n\t(((x) >> BIT_SHIFT_XTAL_LDO_VCM) & BIT_MASK_XTAL_LDO_VCM)\n#define BIT_SET_XTAL_LDO_VCM(x, v)                                             \\\n\t(BIT_CLEAR_XTAL_LDO_VCM(x) | BIT_XTAL_LDO_VCM(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_DRV_LDO_VCM_1_TO_0 2\n#define BIT_MASK_DRV_LDO_VCM_1_TO_0 0x3\n#define BIT_DRV_LDO_VCM_1_TO_0(x)                                              \\\n\t(((x) & BIT_MASK_DRV_LDO_VCM_1_TO_0) << BIT_SHIFT_DRV_LDO_VCM_1_TO_0)\n#define BITS_DRV_LDO_VCM_1_TO_0                                                \\\n\t(BIT_MASK_DRV_LDO_VCM_1_TO_0 << BIT_SHIFT_DRV_LDO_VCM_1_TO_0)\n#define BIT_CLEAR_DRV_LDO_VCM_1_TO_0(x) ((x) & (~BITS_DRV_LDO_VCM_1_TO_0))\n#define BIT_GET_DRV_LDO_VCM_1_TO_0(x)                                          \\\n\t(((x) >> BIT_SHIFT_DRV_LDO_VCM_1_TO_0) & BIT_MASK_DRV_LDO_VCM_1_TO_0)\n#define BIT_SET_DRV_LDO_VCM_1_TO_0(x, v)                                       \\\n\t(BIT_CLEAR_DRV_LDO_VCM_1_TO_0(x) | BIT_DRV_LDO_VCM_1_TO_0(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_DUMMY BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_GMP_V2 1\n#define BIT_MASK_XTAL_GMP_V2 0x3\n#define BIT_XTAL_GMP_V2(x)                                                     \\\n\t(((x) & BIT_MASK_XTAL_GMP_V2) << BIT_SHIFT_XTAL_GMP_V2)\n#define BITS_XTAL_GMP_V2 (BIT_MASK_XTAL_GMP_V2 << BIT_SHIFT_XTAL_GMP_V2)\n#define BIT_CLEAR_XTAL_GMP_V2(x) ((x) & (~BITS_XTAL_GMP_V2))\n#define BIT_GET_XTAL_GMP_V2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_XTAL_GMP_V2) & BIT_MASK_XTAL_GMP_V2)\n#define BIT_SET_XTAL_GMP_V2(x, v)                                              \\\n\t(BIT_CLEAR_XTAL_GMP_V2(x) | BIT_XTAL_GMP_V2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_SHIFT_XTAL_GMP_V1 1\n#define BIT_MASK_XTAL_GMP_V1 0x3\n#define BIT_XTAL_GMP_V1(x)                                                     \\\n\t(((x) & BIT_MASK_XTAL_GMP_V1) << BIT_SHIFT_XTAL_GMP_V1)\n#define BITS_XTAL_GMP_V1 (BIT_MASK_XTAL_GMP_V1 << BIT_SHIFT_XTAL_GMP_V1)\n#define BIT_CLEAR_XTAL_GMP_V1(x) ((x) & (~BITS_XTAL_GMP_V1))\n#define BIT_GET_XTAL_GMP_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_XTAL_GMP_V1) & BIT_MASK_XTAL_GMP_V1)\n#define BIT_SET_XTAL_GMP_V1(x, v)                                              \\\n\t(BIT_CLEAR_XTAL_GMP_V1(x) | BIT_XTAL_GMP_V1(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XQSEL_RF_INITIAL_V1 BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL1\t\t\t\t(Offset 0x0024) */\n\n#define BIT_XTAL_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_FREE_TXPG2\t\t\t(Offset 0x10250024) */\n\n#define BIT_SHIFT_LOW_FREEPG_V1 0\n#define BIT_MASK_LOW_FREEPG_V1 0xfff\n#define BIT_LOW_FREEPG_V1(x)                                                   \\\n\t(((x) & BIT_MASK_LOW_FREEPG_V1) << BIT_SHIFT_LOW_FREEPG_V1)\n#define BITS_LOW_FREEPG_V1 (BIT_MASK_LOW_FREEPG_V1 << BIT_SHIFT_LOW_FREEPG_V1)\n#define BIT_CLEAR_LOW_FREEPG_V1(x) ((x) & (~BITS_LOW_FREEPG_V1))\n#define BIT_GET_LOW_FREEPG_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_LOW_FREEPG_V1) & BIT_MASK_LOW_FREEPG_V1)\n#define BIT_SET_LOW_FREEPG_V1(x, v)                                            \\\n\t(BIT_CLEAR_LOW_FREEPG_V1(x) | BIT_LOW_FREEPG_V1(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_REG_C3_V4 30\n#define BIT_MASK_REG_C3_V4 0x3\n#define BIT_REG_C3_V4(x) (((x) & BIT_MASK_REG_C3_V4) << BIT_SHIFT_REG_C3_V4)\n#define BITS_REG_C3_V4 (BIT_MASK_REG_C3_V4 << BIT_SHIFT_REG_C3_V4)\n#define BIT_CLEAR_REG_C3_V4(x) ((x) & (~BITS_REG_C3_V4))\n#define BIT_GET_REG_C3_V4(x) (((x) >> BIT_SHIFT_REG_C3_V4) & BIT_MASK_REG_C3_V4)\n#define BIT_SET_REG_C3_V4(x, v) (BIT_CLEAR_REG_C3_V4(x) | BIT_REG_C3_V4(v))\n\n#define BIT_REG_CP_BIT1 BIT(29)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_XTAL_GMN 28\n#define BIT_MASK_XTAL_GMN 0xf\n#define BIT_XTAL_GMN(x) (((x) & BIT_MASK_XTAL_GMN) << BIT_SHIFT_XTAL_GMN)\n#define BITS_XTAL_GMN (BIT_MASK_XTAL_GMN << BIT_SHIFT_XTAL_GMN)\n#define BIT_CLEAR_XTAL_GMN(x) ((x) & (~BITS_XTAL_GMN))\n#define BIT_GET_XTAL_GMN(x) (((x) >> BIT_SHIFT_XTAL_GMN) & BIT_MASK_XTAL_GMN)\n#define BIT_SET_XTAL_GMN(x, v) (BIT_CLEAR_XTAL_GMN(x) | BIT_XTAL_GMN(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_IOOFFSET_3_TO_0 28\n#define BIT_MASK_IOOFFSET_3_TO_0 0xf\n#define BIT_IOOFFSET_3_TO_0(x)                                                 \\\n\t(((x) & BIT_MASK_IOOFFSET_3_TO_0) << BIT_SHIFT_IOOFFSET_3_TO_0)\n#define BITS_IOOFFSET_3_TO_0                                                   \\\n\t(BIT_MASK_IOOFFSET_3_TO_0 << BIT_SHIFT_IOOFFSET_3_TO_0)\n#define BIT_CLEAR_IOOFFSET_3_TO_0(x) ((x) & (~BITS_IOOFFSET_3_TO_0))\n#define BIT_GET_IOOFFSET_3_TO_0(x)                                             \\\n\t(((x) >> BIT_SHIFT_IOOFFSET_3_TO_0) & BIT_MASK_IOOFFSET_3_TO_0)\n#define BIT_SET_IOOFFSET_3_TO_0(x, v)                                          \\\n\t(BIT_CLEAR_IOOFFSET_3_TO_0(x) | BIT_IOOFFSET_3_TO_0(v))\n\n#define BIT_REG_FREF_SEL_BIT3_V1 BIT(27)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_REG_VO_AD 26\n#define BIT_MASK_REG_VO_AD 0x3\n#define BIT_REG_VO_AD(x) (((x) & BIT_MASK_REG_VO_AD) << BIT_SHIFT_REG_VO_AD)\n#define BITS_REG_VO_AD (BIT_MASK_REG_VO_AD << BIT_SHIFT_REG_VO_AD)\n#define BIT_CLEAR_REG_VO_AD(x) ((x) & (~BITS_REG_VO_AD))\n#define BIT_GET_REG_VO_AD(x) (((x) >> BIT_SHIFT_REG_VO_AD) & BIT_MASK_REG_VO_AD)\n#define BIT_SET_REG_VO_AD(x, v) (BIT_CLEAR_REG_VO_AD(x) | BIT_REG_VO_AD(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_RS_SET 26\n#define BIT_MASK_RS_SET 0x7\n#define BIT_RS_SET(x) (((x) & BIT_MASK_RS_SET) << BIT_SHIFT_RS_SET)\n#define BITS_RS_SET (BIT_MASK_RS_SET << BIT_SHIFT_RS_SET)\n#define BIT_CLEAR_RS_SET(x) ((x) & (~BITS_RS_SET))\n#define BIT_GET_RS_SET(x) (((x) >> BIT_SHIFT_RS_SET) & BIT_MASK_RS_SET)\n#define BIT_SET_RS_SET(x, v) (BIT_CLEAR_RS_SET(x) | BIT_RS_SET(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_RS_SET_V2 26\n#define BIT_MASK_RS_SET_V2 0x7\n#define BIT_RS_SET_V2(x) (((x) & BIT_MASK_RS_SET_V2) << BIT_SHIFT_RS_SET_V2)\n#define BITS_RS_SET_V2 (BIT_MASK_RS_SET_V2 << BIT_SHIFT_RS_SET_V2)\n#define BIT_CLEAR_RS_SET_V2(x) ((x) & (~BITS_RS_SET_V2))\n#define BIT_GET_RS_SET_V2(x) (((x) >> BIT_SHIFT_RS_SET_V2) & BIT_MASK_RS_SET_V2)\n#define BIT_SET_RS_SET_V2(x, v) (BIT_CLEAR_RS_SET_V2(x) | BIT_RS_SET_V2(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_REG_RS_V4 26\n#define BIT_MASK_REG_RS_V4 0x7\n#define BIT_REG_RS_V4(x) (((x) & BIT_MASK_REG_RS_V4) << BIT_SHIFT_REG_RS_V4)\n#define BITS_REG_RS_V4 (BIT_MASK_REG_RS_V4 << BIT_SHIFT_REG_RS_V4)\n#define BIT_CLEAR_REG_RS_V4(x) ((x) & (~BITS_REG_RS_V4))\n#define BIT_GET_REG_RS_V4(x) (((x) >> BIT_SHIFT_REG_RS_V4) & BIT_MASK_REG_RS_V4)\n#define BIT_SET_REG_RS_V4(x, v) (BIT_CLEAR_REG_RS_V4(x) | BIT_REG_RS_V4(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_V12ADJ_V1 25\n#define BIT_MASK_V12ADJ_V1 0x3\n#define BIT_V12ADJ_V1(x) (((x) & BIT_MASK_V12ADJ_V1) << BIT_SHIFT_V12ADJ_V1)\n#define BITS_V12ADJ_V1 (BIT_MASK_V12ADJ_V1 << BIT_SHIFT_V12ADJ_V1)\n#define BIT_CLEAR_V12ADJ_V1(x) ((x) & (~BITS_V12ADJ_V1))\n#define BIT_GET_V12ADJ_V1(x) (((x) >> BIT_SHIFT_V12ADJ_V1) & BIT_MASK_V12ADJ_V1)\n#define BIT_SET_V12ADJ_V1(x, v) (BIT_CLEAR_V12ADJ_V1(x) | BIT_V12ADJ_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_OQT_FREE_TXPG_V1\t\t(Offset 0x10250028) */\n\n#define BIT_SHIFT_NOAC_OQT_FREEPG_V1 24\n#define BIT_MASK_NOAC_OQT_FREEPG_V1 0xff\n#define BIT_NOAC_OQT_FREEPG_V1(x)                                              \\\n\t(((x) & BIT_MASK_NOAC_OQT_FREEPG_V1) << BIT_SHIFT_NOAC_OQT_FREEPG_V1)\n#define BITS_NOAC_OQT_FREEPG_V1                                                \\\n\t(BIT_MASK_NOAC_OQT_FREEPG_V1 << BIT_SHIFT_NOAC_OQT_FREEPG_V1)\n#define BIT_CLEAR_NOAC_OQT_FREEPG_V1(x) ((x) & (~BITS_NOAC_OQT_FREEPG_V1))\n#define BIT_GET_NOAC_OQT_FREEPG_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1) & BIT_MASK_NOAC_OQT_FREEPG_V1)\n#define BIT_SET_NOAC_OQT_FREEPG_V1(x, v)                                       \\\n\t(BIT_CLEAR_NOAC_OQT_FREEPG_V1(x) | BIT_NOAC_OQT_FREEPG_V1(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_PS_EN BIT(24)\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_REG__CS 24\n#define BIT_MASK_REG__CS 0x3\n#define BIT_REG__CS(x) (((x) & BIT_MASK_REG__CS) << BIT_SHIFT_REG__CS)\n#define BITS_REG__CS (BIT_MASK_REG__CS << BIT_SHIFT_REG__CS)\n#define BIT_CLEAR_REG__CS(x) ((x) & (~BITS_REG__CS))\n#define BIT_GET_REG__CS(x) (((x) >> BIT_SHIFT_REG__CS) & BIT_MASK_REG__CS)\n#define BIT_SET_REG__CS(x, v) (BIT_CLEAR_REG__CS(x) | BIT_REG__CS(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_EN_CK320M_V1 BIT(23)\n#define BIT_AGPIO BIT(22)\n#define BIT_REG_EDGE_SEL_V1 BIT(21)\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_REG_CP_OFFSET 21\n#define BIT_MASK_REG_CP_OFFSET 0x7\n#define BIT_REG_CP_OFFSET(x)                                                   \\\n\t(((x) & BIT_MASK_REG_CP_OFFSET) << BIT_SHIFT_REG_CP_OFFSET)\n#define BITS_REG_CP_OFFSET (BIT_MASK_REG_CP_OFFSET << BIT_SHIFT_REG_CP_OFFSET)\n#define BIT_CLEAR_REG_CP_OFFSET(x) ((x) & (~BITS_REG_CP_OFFSET))\n#define BIT_GET_REG_CP_OFFSET(x)                                               \\\n\t(((x) >> BIT_SHIFT_REG_CP_OFFSET) & BIT_MASK_REG_CP_OFFSET)\n#define BIT_SET_REG_CP_OFFSET(x, v)                                            \\\n\t(BIT_CLEAR_REG_CP_OFFSET(x) | BIT_REG_CP_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_REG_VCO_BIAS_0 BIT(20)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_CP_BIAS 18\n#define BIT_MASK_CP_BIAS 0x7\n#define BIT_CP_BIAS(x) (((x) & BIT_MASK_CP_BIAS) << BIT_SHIFT_CP_BIAS)\n#define BITS_CP_BIAS (BIT_MASK_CP_BIAS << BIT_SHIFT_CP_BIAS)\n#define BIT_CLEAR_CP_BIAS(x) ((x) & (~BITS_CP_BIAS))\n#define BIT_GET_CP_BIAS(x) (((x) >> BIT_SHIFT_CP_BIAS) & BIT_MASK_CP_BIAS)\n#define BIT_SET_CP_BIAS(x, v) (BIT_CLEAR_CP_BIAS(x) | BIT_CP_BIAS(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_CP_BIAS_V2 18\n#define BIT_MASK_CP_BIAS_V2 0x7\n#define BIT_CP_BIAS_V2(x) (((x) & BIT_MASK_CP_BIAS_V2) << BIT_SHIFT_CP_BIAS_V2)\n#define BITS_CP_BIAS_V2 (BIT_MASK_CP_BIAS_V2 << BIT_SHIFT_CP_BIAS_V2)\n#define BIT_CLEAR_CP_BIAS_V2(x) ((x) & (~BITS_CP_BIAS_V2))\n#define BIT_GET_CP_BIAS_V2(x)                                                  \\\n\t(((x) >> BIT_SHIFT_CP_BIAS_V2) & BIT_MASK_CP_BIAS_V2)\n#define BIT_SET_CP_BIAS_V2(x, v) (BIT_CLEAR_CP_BIAS_V2(x) | BIT_CP_BIAS_V2(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1 17\n#define BIT_MASK_REG_PLLBIAS_2_TO_0_V1 0x7\n#define BIT_REG_PLLBIAS_2_TO_0_V1(x)                                           \\\n\t(((x) & BIT_MASK_REG_PLLBIAS_2_TO_0_V1)                                \\\n\t << BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1)\n#define BITS_REG_PLLBIAS_2_TO_0_V1                                             \\\n\t(BIT_MASK_REG_PLLBIAS_2_TO_0_V1 << BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1)\n#define BIT_CLEAR_REG_PLLBIAS_2_TO_0_V1(x) ((x) & (~BITS_REG_PLLBIAS_2_TO_0_V1))\n#define BIT_GET_REG_PLLBIAS_2_TO_0_V1(x)                                       \\\n\t(((x) >> BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1) &                            \\\n\t BIT_MASK_REG_PLLBIAS_2_TO_0_V1)\n#define BIT_SET_REG_PLLBIAS_2_TO_0_V1(x, v)                                    \\\n\t(BIT_CLEAR_REG_PLLBIAS_2_TO_0_V1(x) | BIT_REG_PLLBIAS_2_TO_0_V1(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_REG_IDOUBLE_V2 BIT(17)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_FREF_SEL BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_OQT_FREE_TXPG_V1\t\t(Offset 0x10250028) */\n\n#define BIT_SHIFT_AC_OQT_FREEPG_V1 16\n#define BIT_MASK_AC_OQT_FREEPG_V1 0xff\n#define BIT_AC_OQT_FREEPG_V1(x)                                                \\\n\t(((x) & BIT_MASK_AC_OQT_FREEPG_V1) << BIT_SHIFT_AC_OQT_FREEPG_V1)\n#define BITS_AC_OQT_FREEPG_V1                                                  \\\n\t(BIT_MASK_AC_OQT_FREEPG_V1 << BIT_SHIFT_AC_OQT_FREEPG_V1)\n#define BIT_CLEAR_AC_OQT_FREEPG_V1(x) ((x) & (~BITS_AC_OQT_FREEPG_V1))\n#define BIT_GET_AC_OQT_FREEPG_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1) & BIT_MASK_AC_OQT_FREEPG_V1)\n#define BIT_SET_AC_OQT_FREEPG_V1(x, v)                                         \\\n\t(BIT_CLEAR_AC_OQT_FREEPG_V1(x) | BIT_AC_OQT_FREEPG_V1(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_REG_IDOUBLE_V1 BIT(16)\n\n#define BIT_SHIFT_AC_OQT__FREEPG_V1 16\n#define BIT_MASK_AC_OQT__FREEPG_V1 0xff\n#define BIT_AC_OQT__FREEPG_V1(x)                                               \\\n\t(((x) & BIT_MASK_AC_OQT__FREEPG_V1) << BIT_SHIFT_AC_OQT__FREEPG_V1)\n#define BITS_AC_OQT__FREEPG_V1                                                 \\\n\t(BIT_MASK_AC_OQT__FREEPG_V1 << BIT_SHIFT_AC_OQT__FREEPG_V1)\n#define BIT_CLEAR_AC_OQT__FREEPG_V1(x) ((x) & (~BITS_AC_OQT__FREEPG_V1))\n#define BIT_GET_AC_OQT__FREEPG_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_AC_OQT__FREEPG_V1) & BIT_MASK_AC_OQT__FREEPG_V1)\n#define BIT_SET_AC_OQT__FREEPG_V1(x, v)                                        \\\n\t(BIT_CLEAR_AC_OQT__FREEPG_V1(x) | BIT_AC_OQT__FREEPG_V1(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_EN_SYN BIT(16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_REG_KVCO_V1 BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_APLL_320_GATEB BIT(14)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_MCCO 14\n#define BIT_MASK_MCCO 0x3\n#define BIT_MCCO(x) (((x) & BIT_MASK_MCCO) << BIT_SHIFT_MCCO)\n#define BITS_MCCO (BIT_MASK_MCCO << BIT_SHIFT_MCCO)\n#define BIT_CLEAR_MCCO(x) ((x) & (~BITS_MCCO))\n#define BIT_GET_MCCO(x) (((x) >> BIT_SHIFT_MCCO) & BIT_MASK_MCCO)\n#define BIT_SET_MCCO(x, v) (BIT_CLEAR_MCCO(x) | BIT_MCCO(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_MCCO_V2 14\n#define BIT_MASK_MCCO_V2 0x3\n#define BIT_MCCO_V2(x) (((x) & BIT_MASK_MCCO_V2) << BIT_SHIFT_MCCO_V2)\n#define BITS_MCCO_V2 (BIT_MASK_MCCO_V2 << BIT_SHIFT_MCCO_V2)\n#define BIT_CLEAR_MCCO_V2(x) ((x) & (~BITS_MCCO_V2))\n#define BIT_GET_MCCO_V2(x) (((x) >> BIT_SHIFT_MCCO_V2) & BIT_MASK_MCCO_V2)\n#define BIT_SET_MCCO_V2(x, v) (BIT_CLEAR_MCCO_V2(x) | BIT_MCCO_V2(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_REG_VCO_BIAS_1_V1 BIT(14)\n#define BIT_REG_DOGB_V1 BIT(13)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_CK320_EN 12\n#define BIT_MASK_CK320_EN 0x3\n#define BIT_CK320_EN(x) (((x) & BIT_MASK_CK320_EN) << BIT_SHIFT_CK320_EN)\n#define BITS_CK320_EN (BIT_MASK_CK320_EN << BIT_SHIFT_CK320_EN)\n#define BIT_CLEAR_CK320_EN(x) ((x) & (~BITS_CK320_EN))\n#define BIT_GET_CK320_EN(x) (((x) >> BIT_SHIFT_CK320_EN) & BIT_MASK_CK320_EN)\n#define BIT_SET_CK320_EN(x, v) (BIT_CLEAR_CK320_EN(x) | BIT_CK320_EN(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_REG_LDO_SEL 12\n#define BIT_MASK_REG_LDO_SEL 0x3\n#define BIT_REG_LDO_SEL(x)                                                     \\\n\t(((x) & BIT_MASK_REG_LDO_SEL) << BIT_SHIFT_REG_LDO_SEL)\n#define BITS_REG_LDO_SEL (BIT_MASK_REG_LDO_SEL << BIT_SHIFT_REG_LDO_SEL)\n#define BIT_CLEAR_REG_LDO_SEL(x) ((x) & (~BITS_REG_LDO_SEL))\n#define BIT_GET_REG_LDO_SEL(x)                                                 \\\n\t(((x) >> BIT_SHIFT_REG_LDO_SEL) & BIT_MASK_REG_LDO_SEL)\n#define BIT_SET_REG_LDO_SEL(x, v)                                              \\\n\t(BIT_CLEAR_REG_LDO_SEL(x) | BIT_REG_LDO_SEL(v))\n\n#define BIT_REG_KVCO_V2 BIT(10)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_AGPIO_GPO BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_APLL_BIAS 8\n#define BIT_MASK_APLL_BIAS 0x7\n#define BIT_APLL_BIAS(x) (((x) & BIT_MASK_APLL_BIAS) << BIT_SHIFT_APLL_BIAS)\n#define BITS_APLL_BIAS (BIT_MASK_APLL_BIAS << BIT_SHIFT_APLL_BIAS)\n#define BIT_CLEAR_APLL_BIAS(x) ((x) & (~BITS_APLL_BIAS))\n#define BIT_GET_APLL_BIAS(x) (((x) >> BIT_SHIFT_APLL_BIAS) & BIT_MASK_APLL_BIAS)\n#define BIT_SET_APLL_BIAS(x, v) (BIT_CLEAR_APLL_BIAS(x) | BIT_APLL_BIAS(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_AGPIO_DRV 7\n#define BIT_MASK_AGPIO_DRV 0x3\n#define BIT_AGPIO_DRV(x) (((x) & BIT_MASK_AGPIO_DRV) << BIT_SHIFT_AGPIO_DRV)\n#define BITS_AGPIO_DRV (BIT_MASK_AGPIO_DRV << BIT_SHIFT_AGPIO_DRV)\n#define BIT_CLEAR_AGPIO_DRV(x) ((x) & (~BITS_AGPIO_DRV))\n#define BIT_GET_AGPIO_DRV(x) (((x) >> BIT_SHIFT_AGPIO_DRV) & BIT_MASK_AGPIO_DRV)\n#define BIT_SET_AGPIO_DRV(x, v) (BIT_CLEAR_AGPIO_DRV(x) | BIT_AGPIO_DRV(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_REG_V15_3_TO_0_V1 7\n#define BIT_MASK_REG_V15_3_TO_0_V1 0xf\n#define BIT_REG_V15_3_TO_0_V1(x)                                               \\\n\t(((x) & BIT_MASK_REG_V15_3_TO_0_V1) << BIT_SHIFT_REG_V15_3_TO_0_V1)\n#define BITS_REG_V15_3_TO_0_V1                                                 \\\n\t(BIT_MASK_REG_V15_3_TO_0_V1 << BIT_SHIFT_REG_V15_3_TO_0_V1)\n#define BIT_CLEAR_REG_V15_3_TO_0_V1(x) ((x) & (~BITS_REG_V15_3_TO_0_V1))\n#define BIT_GET_REG_V15_3_TO_0_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_REG_V15_3_TO_0_V1) & BIT_MASK_REG_V15_3_TO_0_V1)\n#define BIT_SET_REG_V15_3_TO_0_V1(x, v)                                        \\\n\t(BIT_CLEAR_REG_V15_3_TO_0_V1(x) | BIT_REG_V15_3_TO_0_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_APLL_KVCO BIT(6)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_REG_SEL_LDO_PC BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_APLL_WDOGB BIT(4)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_REG_CC_1_TO_0_V1 4\n#define BIT_MASK_REG_CC_1_TO_0_V1 0x3\n#define BIT_REG_CC_1_TO_0_V1(x)                                                \\\n\t(((x) & BIT_MASK_REG_CC_1_TO_0_V1) << BIT_SHIFT_REG_CC_1_TO_0_V1)\n#define BITS_REG_CC_1_TO_0_V1                                                  \\\n\t(BIT_MASK_REG_CC_1_TO_0_V1 << BIT_SHIFT_REG_CC_1_TO_0_V1)\n#define BIT_CLEAR_REG_CC_1_TO_0_V1(x) ((x) & (~BITS_REG_CC_1_TO_0_V1))\n#define BIT_GET_REG_CC_1_TO_0_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_REG_CC_1_TO_0_V1) & BIT_MASK_REG_CC_1_TO_0_V1)\n#define BIT_SET_REG_CC_1_TO_0_V1(x, v)                                         \\\n\t(BIT_CLEAR_REG_CC_1_TO_0_V1(x) | BIT_REG_CC_1_TO_0_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_APLL_EDGE_SEL BIT(3)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_CKDELAY_USB_V1 BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_APLL_FREF_SEL_BIT0 BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_POW_MAC\t\t\t(Offset 0x0028) */\n\n#define BIT_POW_LDO15 BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_CKDELAY_DIG_V1 BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_SHIFT_XTAL_CAP_XO 1\n#define BIT_MASK_XTAL_CAP_XO 0x3f\n#define BIT_XTAL_CAP_XO(x)                                                     \\\n\t(((x) & BIT_MASK_XTAL_CAP_XO) << BIT_SHIFT_XTAL_CAP_XO)\n#define BITS_XTAL_CAP_XO (BIT_MASK_XTAL_CAP_XO << BIT_SHIFT_XTAL_CAP_XO)\n#define BIT_CLEAR_XTAL_CAP_XO(x) ((x) & (~BITS_XTAL_CAP_XO))\n#define BIT_GET_XTAL_CAP_XO(x)                                                 \\\n\t(((x) >> BIT_SHIFT_XTAL_CAP_XO) & BIT_MASK_XTAL_CAP_XO)\n#define BIT_SET_XTAL_CAP_XO(x, v)                                              \\\n\t(BIT_CLEAR_XTAL_CAP_XO(x) | BIT_XTAL_CAP_XO(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_POW_MAC\t\t\t(Offset 0x0028) */\n\n#define BIT_POW_SW BIT(1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_MPLL_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_APLL_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL2\t\t\t\t(Offset 0x0028) */\n\n#define BIT_POW_PLL BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_OQT_FREE_TXPG_V1\t\t(Offset 0x10250028) */\n\n#define BIT_SHIFT_EXQ_FREEPG_V1 0\n#define BIT_MASK_EXQ_FREEPG_V1 0xfff\n#define BIT_EXQ_FREEPG_V1(x)                                                   \\\n\t(((x) & BIT_MASK_EXQ_FREEPG_V1) << BIT_SHIFT_EXQ_FREEPG_V1)\n#define BITS_EXQ_FREEPG_V1 (BIT_MASK_EXQ_FREEPG_V1 << BIT_SHIFT_EXQ_FREEPG_V1)\n#define BIT_CLEAR_EXQ_FREEPG_V1(x) ((x) & (~BITS_EXQ_FREEPG_V1))\n#define BIT_GET_EXQ_FREEPG_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_EXQ_FREEPG_V1) & BIT_MASK_EXQ_FREEPG_V1)\n#define BIT_SET_EXQ_FREEPG_V1(x, v)                                            \\\n\t(BIT_CLEAR_EXQ_FREEPG_V1(x) | BIT_EXQ_FREEPG_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_POW_MAC\t\t\t(Offset 0x0028) */\n\n#define BIT_POW_LDO14 BIT(0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SDIO_OQT_FREE_TXPG_V1\t\t(Offset 0x10250028) */\n\n#define BIT_SHIFT_EXQ__FREEPG_V1 0\n#define BIT_MASK_EXQ__FREEPG_V1 0xfff\n#define BIT_EXQ__FREEPG_V1(x)                                                  \\\n\t(((x) & BIT_MASK_EXQ__FREEPG_V1) << BIT_SHIFT_EXQ__FREEPG_V1)\n#define BITS_EXQ__FREEPG_V1                                                    \\\n\t(BIT_MASK_EXQ__FREEPG_V1 << BIT_SHIFT_EXQ__FREEPG_V1)\n#define BIT_CLEAR_EXQ__FREEPG_V1(x) ((x) & (~BITS_EXQ__FREEPG_V1))\n#define BIT_GET_EXQ__FREEPG_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_EXQ__FREEPG_V1) & BIT_MASK_EXQ__FREEPG_V1)\n#define BIT_SET_EXQ__FREEPG_V1(x, v)                                           \\\n\t(BIT_CLEAR_EXQ__FREEPG_V1(x) | BIT_EXQ__FREEPG_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARLDO_POW_MAC\t\t\t(Offset 0x0029) */\n\n#define BIT_LDOE25_POW_L BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_POW_MAC\t\t\t(Offset 0x002A) */\n\n#define BIT_REG_STANDBY_L BIT(19)\n#define BIT_PD_REGU_L BIT(18)\n#define BIT_EN_PC_BT_L BIT(17)\n\n#define BIT_SHIFT_REG_LDOADJ_L 13\n#define BIT_MASK_REG_LDOADJ_L 0xf\n#define BIT_REG_LDOADJ_L(x)                                                    \\\n\t(((x) & BIT_MASK_REG_LDOADJ_L) << BIT_SHIFT_REG_LDOADJ_L)\n#define BITS_REG_LDOADJ_L (BIT_MASK_REG_LDOADJ_L << BIT_SHIFT_REG_LDOADJ_L)\n#define BIT_CLEAR_REG_LDOADJ_L(x) ((x) & (~BITS_REG_LDOADJ_L))\n#define BIT_GET_REG_LDOADJ_L(x)                                                \\\n\t(((x) >> BIT_SHIFT_REG_LDOADJ_L) & BIT_MASK_REG_LDOADJ_L)\n#define BIT_SET_REG_LDOADJ_L(x, v)                                             \\\n\t(BIT_CLEAR_REG_LDOADJ_L(x) | BIT_REG_LDOADJ_L(v))\n\n#define BIT_CK12M_EN BIT(11)\n#define BIT_CK12M_SEL BIT(10)\n#define BIT_EN_25_L BIT(9)\n#define BIT_EN_SLEEP BIT(8)\n#define BIT_DUMMY_V4 BIT(7)\n#define BIT_DUMMY_V3 BIT(6)\n#define BIT_DUMMY_V2 BIT(5)\n#define BIT_DUMMY_V1 BIT(4)\n\n#define BIT_SHIFT_LDOH12_V12ADJ_L 4\n#define BIT_MASK_LDOH12_V12ADJ_L 0xf\n#define BIT_LDOH12_V12ADJ_L(x)                                                 \\\n\t(((x) & BIT_MASK_LDOH12_V12ADJ_L) << BIT_SHIFT_LDOH12_V12ADJ_L)\n#define BITS_LDOH12_V12ADJ_L                                                   \\\n\t(BIT_MASK_LDOH12_V12ADJ_L << BIT_SHIFT_LDOH12_V12ADJ_L)\n#define BIT_CLEAR_LDOH12_V12ADJ_L(x) ((x) & (~BITS_LDOH12_V12ADJ_L))\n#define BIT_GET_LDOH12_V12ADJ_L(x)                                             \\\n\t(((x) >> BIT_SHIFT_LDOH12_V12ADJ_L) & BIT_MASK_LDOH12_V12ADJ_L)\n#define BIT_SET_LDOH12_V12ADJ_L(x, v)                                          \\\n\t(BIT_CLEAR_LDOH12_V12ADJ_L(x) | BIT_LDOH12_V12ADJ_L(v))\n\n#define BIT_POW_PC_LDO_PORT1 BIT(3)\n#define BIT_POW_PC_LDO_PORT0 BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_POW_MAC\t\t\t(Offset 0x002A) */\n\n#define BIT_POW_PLL_V1 BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_POW_MAC\t\t\t(Offset 0x002A) */\n\n#define BIT_POW_POWER_CUT_POW_LDO BIT(0)\n\n#define BIT_SHIFT_LDOE25_V12ADJ_L_V1 0\n#define BIT_MASK_LDOE25_V12ADJ_L_V1 0xf\n#define BIT_LDOE25_V12ADJ_L_V1(x)                                              \\\n\t(((x) & BIT_MASK_LDOE25_V12ADJ_L_V1) << BIT_SHIFT_LDOE25_V12ADJ_L_V1)\n#define BITS_LDOE25_V12ADJ_L_V1                                                \\\n\t(BIT_MASK_LDOE25_V12ADJ_L_V1 << BIT_SHIFT_LDOE25_V12ADJ_L_V1)\n#define BIT_CLEAR_LDOE25_V12ADJ_L_V1(x) ((x) & (~BITS_LDOE25_V12ADJ_L_V1))\n#define BIT_GET_LDOE25_V12ADJ_L_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_V1) & BIT_MASK_LDOE25_V12ADJ_L_V1)\n#define BIT_SET_LDOE25_V12ADJ_L_V1(x, v)                                       \\\n\t(BIT_CLEAR_LDOE25_V12ADJ_L_V1(x) | BIT_LDOE25_V12ADJ_L_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_POW_XTAL\t\t\t(Offset 0x002B) */\n\n#define BIT_PSTIMER_2 BIT(31)\n#define BIT_PSTIMER_1 BIT(30)\n#define BIT_PSTIMER_0 BIT(29)\n#define BIT_TXDMA_START_INT BIT(23)\n#define BIT_TXDMA_STOP_INT BIT(22)\n#define BIT_HISR7_IND BIT(21)\n#define BIT_HISR6_IND BIT(19)\n#define BIT_HISR5_IND BIT(18)\n#define BIT_HISR4_IND BIT(17)\n#define BIT_HISR3_IND BIT(14)\n#define BIT_HISR2_IND BIT(13)\n#define BIT_POW_XTAL BIT(1)\n#define BIT_POW_BG BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_XTAL_RF2_DRV 30\n#define BIT_MASK_XTAL_RF2_DRV 0x3\n#define BIT_XTAL_RF2_DRV(x)                                                    \\\n\t(((x) & BIT_MASK_XTAL_RF2_DRV) << BIT_SHIFT_XTAL_RF2_DRV)\n#define BITS_XTAL_RF2_DRV (BIT_MASK_XTAL_RF2_DRV << BIT_SHIFT_XTAL_RF2_DRV)\n#define BIT_CLEAR_XTAL_RF2_DRV(x) ((x) & (~BITS_XTAL_RF2_DRV))\n#define BIT_GET_XTAL_RF2_DRV(x)                                                \\\n\t(((x) >> BIT_SHIFT_XTAL_RF2_DRV) & BIT_MASK_XTAL_RF2_DRV)\n#define BIT_SET_XTAL_RF2_DRV(x, v)                                             \\\n\t(BIT_CLEAR_XTAL_RF2_DRV(x) | BIT_XTAL_RF2_DRV(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_REG_REF_SEL_V3 BIT(30)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_XTAL_GMN_BIT4 BIT(29)\n#define BIT_XTAL_GMP_BIT4 BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_XQSEL BIT(27)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_REG_FREF_SEL_2_TO_0 27\n#define BIT_MASK_REG_FREF_SEL_2_TO_0 0x7\n#define BIT_REG_FREF_SEL_2_TO_0(x)                                             \\\n\t(((x) & BIT_MASK_REG_FREF_SEL_2_TO_0) << BIT_SHIFT_REG_FREF_SEL_2_TO_0)\n#define BITS_REG_FREF_SEL_2_TO_0                                               \\\n\t(BIT_MASK_REG_FREF_SEL_2_TO_0 << BIT_SHIFT_REG_FREF_SEL_2_TO_0)\n#define BIT_CLEAR_REG_FREF_SEL_2_TO_0(x) ((x) & (~BITS_REG_FREF_SEL_2_TO_0))\n#define BIT_GET_REG_FREF_SEL_2_TO_0(x)                                         \\\n\t(((x) >> BIT_SHIFT_REG_FREF_SEL_2_TO_0) & BIT_MASK_REG_FREF_SEL_2_TO_0)\n#define BIT_SET_REG_FREF_SEL_2_TO_0(x, v)                                      \\\n\t(BIT_CLEAR_REG_FREF_SEL_2_TO_0(x) | BIT_REG_FREF_SEL_2_TO_0(v))\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_XQSEL_BIT0 BIT(27)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_APLL_DUMMY BIT(26)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1 21\n#define BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1 0x3f\n#define BIT_XTAL_CADJ_XOUT_5_TO_0_V1(x)                                        \\\n\t(((x) & BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1)                             \\\n\t << BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1)\n#define BITS_XTAL_CADJ_XOUT_5_TO_0_V1                                          \\\n\t(BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1                                     \\\n\t << BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1)\n#define BIT_CLEAR_XTAL_CADJ_XOUT_5_TO_0_V1(x)                                  \\\n\t((x) & (~BITS_XTAL_CADJ_XOUT_5_TO_0_V1))\n#define BIT_GET_XTAL_CADJ_XOUT_5_TO_0_V1(x)                                    \\\n\t(((x) >> BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1) &                         \\\n\t BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1)\n#define BIT_SET_XTAL_CADJ_XOUT_5_TO_0_V1(x, v)                                 \\\n\t(BIT_CLEAR_XTAL_CADJ_XOUT_5_TO_0_V1(x) |                               \\\n\t BIT_XTAL_CADJ_XOUT_5_TO_0_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_XTAL_CADJ_XOUT 18\n#define BIT_MASK_XTAL_CADJ_XOUT 0x3f\n#define BIT_XTAL_CADJ_XOUT(x)                                                  \\\n\t(((x) & BIT_MASK_XTAL_CADJ_XOUT) << BIT_SHIFT_XTAL_CADJ_XOUT)\n#define BITS_XTAL_CADJ_XOUT                                                    \\\n\t(BIT_MASK_XTAL_CADJ_XOUT << BIT_SHIFT_XTAL_CADJ_XOUT)\n#define BIT_CLEAR_XTAL_CADJ_XOUT(x) ((x) & (~BITS_XTAL_CADJ_XOUT))\n#define BIT_GET_XTAL_CADJ_XOUT(x)                                              \\\n\t(((x) >> BIT_SHIFT_XTAL_CADJ_XOUT) & BIT_MASK_XTAL_CADJ_XOUT)\n#define BIT_SET_XTAL_CADJ_XOUT(x, v)                                           \\\n\t(BIT_CLEAR_XTAL_CADJ_XOUT(x) | BIT_XTAL_CADJ_XOUT(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_XTAL_CADJ_XIN_V2 15\n#define BIT_MASK_XTAL_CADJ_XIN_V2 0x3f\n#define BIT_XTAL_CADJ_XIN_V2(x)                                                \\\n\t(((x) & BIT_MASK_XTAL_CADJ_XIN_V2) << BIT_SHIFT_XTAL_CADJ_XIN_V2)\n#define BITS_XTAL_CADJ_XIN_V2                                                  \\\n\t(BIT_MASK_XTAL_CADJ_XIN_V2 << BIT_SHIFT_XTAL_CADJ_XIN_V2)\n#define BIT_CLEAR_XTAL_CADJ_XIN_V2(x) ((x) & (~BITS_XTAL_CADJ_XIN_V2))\n#define BIT_GET_XTAL_CADJ_XIN_V2(x)                                            \\\n\t(((x) >> BIT_SHIFT_XTAL_CADJ_XIN_V2) & BIT_MASK_XTAL_CADJ_XIN_V2)\n#define BIT_SET_XTAL_CADJ_XIN_V2(x, v)                                         \\\n\t(BIT_CLEAR_XTAL_CADJ_XIN_V2(x) | BIT_XTAL_CADJ_XIN_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_XTAL_CADJ_XIN 12\n#define BIT_MASK_XTAL_CADJ_XIN 0x3f\n#define BIT_XTAL_CADJ_XIN(x)                                                   \\\n\t(((x) & BIT_MASK_XTAL_CADJ_XIN) << BIT_SHIFT_XTAL_CADJ_XIN)\n#define BITS_XTAL_CADJ_XIN (BIT_MASK_XTAL_CADJ_XIN << BIT_SHIFT_XTAL_CADJ_XIN)\n#define BIT_CLEAR_XTAL_CADJ_XIN(x) ((x) & (~BITS_XTAL_CADJ_XIN))\n#define BIT_GET_XTAL_CADJ_XIN(x)                                               \\\n\t(((x) >> BIT_SHIFT_XTAL_CADJ_XIN) & BIT_MASK_XTAL_CADJ_XIN)\n#define BIT_SET_XTAL_CADJ_XIN(x, v)                                            \\\n\t(BIT_CLEAR_XTAL_CADJ_XIN(x) | BIT_XTAL_CADJ_XIN(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_REG_RS_V3 12\n#define BIT_MASK_REG_RS_V3 0x7\n#define BIT_REG_RS_V3(x) (((x) & BIT_MASK_REG_RS_V3) << BIT_SHIFT_REG_RS_V3)\n#define BITS_REG_RS_V3 (BIT_MASK_REG_RS_V3 << BIT_SHIFT_REG_RS_V3)\n#define BIT_CLEAR_REG_RS_V3(x) ((x) & (~BITS_REG_RS_V3))\n#define BIT_GET_REG_RS_V3(x) (((x) >> BIT_SHIFT_REG_RS_V3) & BIT_MASK_REG_RS_V3)\n#define BIT_SET_REG_RS_V3(x, v) (BIT_CLEAR_REG_RS_V3(x) | BIT_REG_RS_V3(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TXPKT_EMPTY\t\t\t(Offset 0x1025002C) */\n\n#define BIT_SDIO_BCNQ_EMPTY BIT(11)\n#define BIT_SDIO_HQQ_EMPTY BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_REG_RS 9\n#define BIT_MASK_REG_RS 0x7\n#define BIT_REG_RS(x) (((x) & BIT_MASK_REG_RS) << BIT_SHIFT_REG_RS)\n#define BITS_REG_RS (BIT_MASK_REG_RS << BIT_SHIFT_REG_RS)\n#define BIT_CLEAR_REG_RS(x) ((x) & (~BITS_REG_RS))\n#define BIT_GET_REG_RS(x) (((x) >> BIT_SHIFT_REG_RS) & BIT_MASK_REG_RS)\n#define BIT_SET_REG_RS(x, v) (BIT_CLEAR_REG_RS(x) | BIT_REG_RS(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TXPKT_EMPTY\t\t\t(Offset 0x1025002C) */\n\n#define BIT_SDIO_MQQ_EMPTY BIT(9)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_REG_R3_V3 9\n#define BIT_MASK_REG_R3_V3 0x7\n#define BIT_REG_R3_V3(x) (((x) & BIT_MASK_REG_R3_V3) << BIT_SHIFT_REG_R3_V3)\n#define BITS_REG_R3_V3 (BIT_MASK_REG_R3_V3 << BIT_SHIFT_REG_R3_V3)\n#define BIT_CLEAR_REG_R3_V3(x) ((x) & (~BITS_REG_R3_V3))\n#define BIT_GET_REG_R3_V3(x) (((x) >> BIT_SHIFT_REG_R3_V3) & BIT_MASK_REG_R3_V3)\n#define BIT_SET_REG_R3_V3(x, v) (BIT_CLEAR_REG_R3_V3(x) | BIT_REG_R3_V3(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TXPKT_EMPTY\t\t\t(Offset 0x1025002C) */\n\n#define BIT_SDIO_MGQ_CPU_EMPTY BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_PS_V2 7\n#define BIT_MASK_PS_V2 0x7\n#define BIT_PS_V2(x) (((x) & BIT_MASK_PS_V2) << BIT_SHIFT_PS_V2)\n#define BITS_PS_V2 (BIT_MASK_PS_V2 << BIT_SHIFT_PS_V2)\n#define BIT_CLEAR_PS_V2(x) ((x) & (~BITS_PS_V2))\n#define BIT_GET_PS_V2(x) (((x) >> BIT_SHIFT_PS_V2) & BIT_MASK_PS_V2)\n#define BIT_SET_PS_V2(x, v) (BIT_CLEAR_PS_V2(x) | BIT_PS_V2(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TXPKT_EMPTY\t\t\t(Offset 0x1025002C) */\n\n#define BIT_SDIO_AC7Q_EMPTY BIT(7)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_REG_CS_V3 7\n#define BIT_MASK_REG_CS_V3 0x3\n#define BIT_REG_CS_V3(x) (((x) & BIT_MASK_REG_CS_V3) << BIT_SHIFT_REG_CS_V3)\n#define BITS_REG_CS_V3 (BIT_MASK_REG_CS_V3 << BIT_SHIFT_REG_CS_V3)\n#define BIT_CLEAR_REG_CS_V3(x) ((x) & (~BITS_REG_CS_V3))\n#define BIT_GET_REG_CS_V3(x) (((x) >> BIT_SHIFT_REG_CS_V3) & BIT_MASK_REG_CS_V3)\n#define BIT_SET_REG_CS_V3(x, v) (BIT_CLEAR_REG_CS_V3(x) | BIT_REG_CS_V3(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_PS 7\n#define BIT_MASK_PS 0x7\n#define BIT_PS(x) (((x) & BIT_MASK_PS) << BIT_SHIFT_PS)\n#define BITS_PS (BIT_MASK_PS << BIT_SHIFT_PS)\n#define BIT_CLEAR_PS(x) ((x) & (~BITS_PS))\n#define BIT_GET_PS(x) (((x) >> BIT_SHIFT_PS) & BIT_MASK_PS)\n#define BIT_SET_PS(x, v) (BIT_CLEAR_PS(x) | BIT_PS(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_REG_R3 6\n#define BIT_MASK_REG_R3 0x7\n#define BIT_REG_R3(x) (((x) & BIT_MASK_REG_R3) << BIT_SHIFT_REG_R3)\n#define BITS_REG_R3 (BIT_MASK_REG_R3 << BIT_SHIFT_REG_R3)\n#define BIT_CLEAR_REG_R3(x) ((x) & (~BITS_REG_R3))\n#define BIT_GET_REG_R3(x) (((x) >> BIT_SHIFT_REG_R3) & BIT_MASK_REG_R3)\n#define BIT_SET_REG_R3(x, v) (BIT_CLEAR_REG_R3(x) | BIT_REG_R3(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_PSEN BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TXPKT_EMPTY\t\t\t(Offset 0x1025002C) */\n\n#define BIT_SDIO_AC6Q_EMPTY BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_DOGENB BIT(5)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TXPKT_EMPTY\t\t\t(Offset 0x1025002C) */\n\n#define BIT_SDIO_AC5Q_EMPTY BIT(5)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_REG_CP_V3 5\n#define BIT_MASK_REG_CP_V3 0x3\n#define BIT_REG_CP_V3(x) (((x) & BIT_MASK_REG_CP_V3) << BIT_SHIFT_REG_CP_V3)\n#define BITS_REG_CP_V3 (BIT_MASK_REG_CP_V3 << BIT_SHIFT_REG_CP_V3)\n#define BIT_CLEAR_REG_CP_V3(x) ((x) & (~BITS_REG_CP_V3))\n#define BIT_GET_REG_CP_V3(x) (((x) >> BIT_SHIFT_REG_CP_V3) & BIT_MASK_REG_CP_V3)\n#define BIT_SET_REG_CP_V3(x, v) (BIT_CLEAR_REG_CP_V3(x) | BIT_REG_CP_V3(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_REG_CS 4\n#define BIT_MASK_REG_CS 0x3\n#define BIT_REG_CS(x) (((x) & BIT_MASK_REG_CS) << BIT_SHIFT_REG_CS)\n#define BITS_REG_CS (BIT_MASK_REG_CS << BIT_SHIFT_REG_CS)\n#define BIT_CLEAR_REG_CS(x) ((x) & (~BITS_REG_CS))\n#define BIT_GET_REG_CS(x) (((x) >> BIT_SHIFT_REG_CS) & BIT_MASK_REG_CS)\n#define BIT_SET_REG_CS(x, v) (BIT_CLEAR_REG_CS(x) | BIT_REG_CS(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TXPKT_EMPTY\t\t\t(Offset 0x1025002C) */\n\n#define BIT_SDIO_AC4Q_EMPTY BIT(4)\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_REG_MBIAS BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TXPKT_EMPTY\t\t\t(Offset 0x1025002C) */\n\n#define BIT_SDIO_AC3Q_EMPTY BIT(3)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_REG_C3_V3 3\n#define BIT_MASK_REG_C3_V3 0x3\n#define BIT_REG_C3_V3(x) (((x) & BIT_MASK_REG_C3_V3) << BIT_SHIFT_REG_C3_V3)\n#define BITS_REG_C3_V3 (BIT_MASK_REG_C3_V3 << BIT_SHIFT_REG_C3_V3)\n#define BIT_CLEAR_REG_C3_V3(x) ((x) & (~BITS_REG_C3_V3))\n#define BIT_GET_REG_C3_V3(x) (((x) >> BIT_SHIFT_REG_C3_V3) & BIT_MASK_REG_C3_V3)\n#define BIT_SET_REG_C3_V3(x, v) (BIT_CLEAR_REG_C3_V3(x) | BIT_REG_C3_V3(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_REG_CP 2\n#define BIT_MASK_REG_CP 0x3\n#define BIT_REG_CP(x) (((x) & BIT_MASK_REG_CP) << BIT_SHIFT_REG_CP)\n#define BITS_REG_CP (BIT_MASK_REG_CP << BIT_SHIFT_REG_CP)\n#define BIT_CLEAR_REG_CP(x) ((x) & (~BITS_REG_CP))\n#define BIT_GET_REG_CP(x) (((x) >> BIT_SHIFT_REG_CP) & BIT_MASK_REG_CP)\n#define BIT_SET_REG_CP(x, v) (BIT_CLEAR_REG_CP(x) | BIT_REG_CP(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TXPKT_EMPTY\t\t\t(Offset 0x1025002C) */\n\n#define BIT_SDIO_AC2Q_EMPTY BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_REG_320_SEL_V3 BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TXPKT_EMPTY\t\t\t(Offset 0x1025002C) */\n\n#define BIT_SDIO_AC1Q_EMPTY BIT(1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_EN_SYN_V1 BIT(1)\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_REG_R3_V4 1\n#define BIT_MASK_REG_R3_V4 0x7\n#define BIT_REG_R3_V4(x) (((x) & BIT_MASK_REG_R3_V4) << BIT_SHIFT_REG_R3_V4)\n#define BITS_REG_R3_V4 (BIT_MASK_REG_R3_V4 << BIT_SHIFT_REG_R3_V4)\n#define BIT_CLEAR_REG_R3_V4(x) ((x) & (~BITS_REG_R3_V4))\n#define BIT_GET_REG_R3_V4(x) (((x) >> BIT_SHIFT_REG_R3_V4) & BIT_MASK_REG_R3_V4)\n#define BIT_SET_REG_R3_V4(x, v) (BIT_CLEAR_REG_R3_V4(x) | BIT_REG_R3_V4(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_SHIFT_REG_C3 0\n#define BIT_MASK_REG_C3 0x3\n#define BIT_REG_C3(x) (((x) & BIT_MASK_REG_C3) << BIT_SHIFT_REG_C3)\n#define BITS_REG_C3 (BIT_MASK_REG_C3 << BIT_SHIFT_REG_C3)\n#define BIT_CLEAR_REG_C3(x) ((x) & (~BITS_REG_C3))\n#define BIT_GET_REG_C3(x) (((x) >> BIT_SHIFT_REG_C3) & BIT_MASK_REG_C3)\n#define BIT_SET_REG_C3(x, v) (BIT_CLEAR_REG_C3(x) | BIT_REG_C3(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TXPKT_EMPTY\t\t\t(Offset 0x1025002C) */\n\n#define BIT_SDIO_AC0Q_EMPTY BIT(0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_IOOFFSET_BIT4 BIT(0)\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL3\t\t\t\t(Offset 0x002C) */\n\n#define BIT_REG_CP_BIT0 BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_EFUSE_CTRL\t\t\t\t(Offset 0x0030) */\n\n#define BIT_EF_FLAG BIT(31)\n\n#define BIT_SHIFT_EF_PGPD 28\n#define BIT_MASK_EF_PGPD 0x7\n#define BIT_EF_PGPD(x) (((x) & BIT_MASK_EF_PGPD) << BIT_SHIFT_EF_PGPD)\n#define BITS_EF_PGPD (BIT_MASK_EF_PGPD << BIT_SHIFT_EF_PGPD)\n#define BIT_CLEAR_EF_PGPD(x) ((x) & (~BITS_EF_PGPD))\n#define BIT_GET_EF_PGPD(x) (((x) >> BIT_SHIFT_EF_PGPD) & BIT_MASK_EF_PGPD)\n#define BIT_SET_EF_PGPD(x, v) (BIT_CLEAR_EF_PGPD(x) | BIT_EF_PGPD(v))\n\n#define BIT_SHIFT_EF_RDT 24\n#define BIT_MASK_EF_RDT 0xf\n#define BIT_EF_RDT(x) (((x) & BIT_MASK_EF_RDT) << BIT_SHIFT_EF_RDT)\n#define BITS_EF_RDT (BIT_MASK_EF_RDT << BIT_SHIFT_EF_RDT)\n#define BIT_CLEAR_EF_RDT(x) ((x) & (~BITS_EF_RDT))\n#define BIT_GET_EF_RDT(x) (((x) >> BIT_SHIFT_EF_RDT) & BIT_MASK_EF_RDT)\n#define BIT_SET_EF_RDT(x, v) (BIT_CLEAR_EF_RDT(x) | BIT_EF_RDT(v))\n\n#define BIT_SHIFT_EF_PGTS 20\n#define BIT_MASK_EF_PGTS 0xf\n#define BIT_EF_PGTS(x) (((x) & BIT_MASK_EF_PGTS) << BIT_SHIFT_EF_PGTS)\n#define BITS_EF_PGTS (BIT_MASK_EF_PGTS << BIT_SHIFT_EF_PGTS)\n#define BIT_CLEAR_EF_PGTS(x) ((x) & (~BITS_EF_PGTS))\n#define BIT_GET_EF_PGTS(x) (((x) >> BIT_SHIFT_EF_PGTS) & BIT_MASK_EF_PGTS)\n#define BIT_SET_EF_PGTS(x, v) (BIT_CLEAR_EF_PGTS(x) | BIT_EF_PGTS(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_EFUSE_CTRL\t\t\t\t(Offset 0x0030) */\n\n#define BIT_EF_PDWN BIT(19)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_EFUSE_CTRL\t\t\t\t(Offset 0x0030) */\n\n#define BIT_EF_ALDEN BIT(18)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HTSFR_INFO\t\t\t(Offset 0x10250030) */\n\n#define BIT_SHIFT_HTSFR1 16\n#define BIT_MASK_HTSFR1 0xffff\n#define BIT_HTSFR1(x) (((x) & BIT_MASK_HTSFR1) << BIT_SHIFT_HTSFR1)\n#define BITS_HTSFR1 (BIT_MASK_HTSFR1 << BIT_SHIFT_HTSFR1)\n#define BIT_CLEAR_HTSFR1(x) ((x) & (~BITS_HTSFR1))\n#define BIT_GET_HTSFR1(x) (((x) >> BIT_SHIFT_HTSFR1) & BIT_MASK_HTSFR1)\n#define BIT_SET_HTSFR1(x, v) (BIT_CLEAR_HTSFR1(x) | BIT_HTSFR1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_EFUSE_CTRL\t\t\t\t(Offset 0x0030) */\n\n#define BIT_SHIFT_EF_ADDR 8\n#define BIT_MASK_EF_ADDR 0x3ff\n#define BIT_EF_ADDR(x) (((x) & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR)\n#define BITS_EF_ADDR (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)\n#define BIT_CLEAR_EF_ADDR(x) ((x) & (~BITS_EF_ADDR))\n#define BIT_GET_EF_ADDR(x) (((x) >> BIT_SHIFT_EF_ADDR) & BIT_MASK_EF_ADDR)\n#define BIT_SET_EF_ADDR(x, v) (BIT_CLEAR_EF_ADDR(x) | BIT_EF_ADDR(v))\n\n#define BIT_SHIFT_EF_DATA 0\n#define BIT_MASK_EF_DATA 0xff\n#define BIT_EF_DATA(x) (((x) & BIT_MASK_EF_DATA) << BIT_SHIFT_EF_DATA)\n#define BITS_EF_DATA (BIT_MASK_EF_DATA << BIT_SHIFT_EF_DATA)\n#define BIT_CLEAR_EF_DATA(x) ((x) & (~BITS_EF_DATA))\n#define BIT_GET_EF_DATA(x) (((x) >> BIT_SHIFT_EF_DATA) & BIT_MASK_EF_DATA)\n#define BIT_SET_EF_DATA(x, v) (BIT_CLEAR_EF_DATA(x) | BIT_EF_DATA(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HTSFR_INFO\t\t\t(Offset 0x10250030) */\n\n#define BIT_SHIFT_HTSFR0 0\n#define BIT_MASK_HTSFR0 0xffff\n#define BIT_HTSFR0(x) (((x) & BIT_MASK_HTSFR0) << BIT_SHIFT_HTSFR0)\n#define BITS_HTSFR0 (BIT_MASK_HTSFR0 << BIT_SHIFT_HTSFR0)\n#define BIT_CLEAR_HTSFR0(x) ((x) & (~BITS_HTSFR0))\n#define BIT_GET_HTSFR0(x) (((x) >> BIT_SHIFT_HTSFR0) & BIT_MASK_HTSFR0)\n#define BIT_SET_HTSFR0(x, v) (BIT_CLEAR_HTSFR0(x) | BIT_HTSFR0(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_LDOE25_EN BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2 28\n#define BIT_MASK_LDOE25_VADJ_BIT0_TO_2 0x7\n#define BIT_LDOE25_VADJ_BIT0_TO_2(x)                                           \\\n\t(((x) & BIT_MASK_LDOE25_VADJ_BIT0_TO_2)                                \\\n\t << BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2)\n#define BITS_LDOE25_VADJ_BIT0_TO_2                                             \\\n\t(BIT_MASK_LDOE25_VADJ_BIT0_TO_2 << BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2)\n#define BIT_CLEAR_LDOE25_VADJ_BIT0_TO_2(x) ((x) & (~BITS_LDOE25_VADJ_BIT0_TO_2))\n#define BIT_GET_LDOE25_VADJ_BIT0_TO_2(x)                                       \\\n\t(((x) >> BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2) &                            \\\n\t BIT_MASK_LDOE25_VADJ_BIT0_TO_2)\n#define BIT_SET_LDOE25_VADJ_BIT0_TO_2(x, v)                                    \\\n\t(BIT_CLEAR_LDOE25_VADJ_BIT0_TO_2(x) | BIT_LDOE25_VADJ_BIT0_TO_2(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_SHIFT_LDOE25_V12ADJ_L_LOW 28\n#define BIT_MASK_LDOE25_V12ADJ_L_LOW 0x7\n#define BIT_LDOE25_V12ADJ_L_LOW(x)                                             \\\n\t(((x) & BIT_MASK_LDOE25_V12ADJ_L_LOW) << BIT_SHIFT_LDOE25_V12ADJ_L_LOW)\n#define BITS_LDOE25_V12ADJ_L_LOW                                               \\\n\t(BIT_MASK_LDOE25_V12ADJ_L_LOW << BIT_SHIFT_LDOE25_V12ADJ_L_LOW)\n#define BIT_CLEAR_LDOE25_V12ADJ_L_LOW(x) ((x) & (~BITS_LDOE25_V12ADJ_L_LOW))\n#define BIT_GET_LDOE25_V12ADJ_L_LOW(x)                                         \\\n\t(((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_LOW) & BIT_MASK_LDOE25_V12ADJ_L_LOW)\n#define BIT_SET_LDOE25_V12ADJ_L_LOW(x, v)                                      \\\n\t(BIT_CLEAR_LDOE25_V12ADJ_L_LOW(x) | BIT_LDOE25_V12ADJ_L_LOW(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_LDOE25_VADJ_BIT3 BIT(27)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_LDOE25_V12ADJ_L_HIGH BIT(27)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_SHIFT_LDOE25_V12ADJ_L 27\n#define BIT_MASK_LDOE25_V12ADJ_L 0xf\n#define BIT_LDOE25_V12ADJ_L(x)                                                 \\\n\t(((x) & BIT_MASK_LDOE25_V12ADJ_L) << BIT_SHIFT_LDOE25_V12ADJ_L)\n#define BITS_LDOE25_V12ADJ_L                                                   \\\n\t(BIT_MASK_LDOE25_V12ADJ_L << BIT_SHIFT_LDOE25_V12ADJ_L)\n#define BIT_CLEAR_LDOE25_V12ADJ_L(x) ((x) & (~BITS_LDOE25_V12ADJ_L))\n#define BIT_GET_LDOE25_V12ADJ_L(x)                                             \\\n\t(((x) >> BIT_SHIFT_LDOE25_V12ADJ_L) & BIT_MASK_LDOE25_V12ADJ_L)\n#define BIT_SET_LDOE25_V12ADJ_L(x, v)                                          \\\n\t(BIT_CLEAR_LDOE25_V12ADJ_L(x) | BIT_LDOE25_V12ADJ_L(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_SHIFT_LDOE25_VADJ_3_TO_0 27\n#define BIT_MASK_LDOE25_VADJ_3_TO_0 0xf\n#define BIT_LDOE25_VADJ_3_TO_0(x)                                              \\\n\t(((x) & BIT_MASK_LDOE25_VADJ_3_TO_0) << BIT_SHIFT_LDOE25_VADJ_3_TO_0)\n#define BITS_LDOE25_VADJ_3_TO_0                                                \\\n\t(BIT_MASK_LDOE25_VADJ_3_TO_0 << BIT_SHIFT_LDOE25_VADJ_3_TO_0)\n#define BIT_CLEAR_LDOE25_VADJ_3_TO_0(x) ((x) & (~BITS_LDOE25_VADJ_3_TO_0))\n#define BIT_GET_LDOE25_VADJ_3_TO_0(x)                                          \\\n\t(((x) >> BIT_SHIFT_LDOE25_VADJ_3_TO_0) & BIT_MASK_LDOE25_VADJ_3_TO_0)\n#define BIT_SET_LDOE25_VADJ_3_TO_0(x, v)                                       \\\n\t(BIT_CLEAR_LDOE25_VADJ_3_TO_0(x) | BIT_LDOE25_VADJ_3_TO_0(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_EFCRES_SEL BIT(26)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_EF_CRES_SEL BIT(26)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_EF_CSER BIT(26)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_SHIFT_EF_SCAN_START 16\n#define BIT_MASK_EF_SCAN_START 0x1ff\n#define BIT_EF_SCAN_START(x)                                                   \\\n\t(((x) & BIT_MASK_EF_SCAN_START) << BIT_SHIFT_EF_SCAN_START)\n#define BITS_EF_SCAN_START (BIT_MASK_EF_SCAN_START << BIT_SHIFT_EF_SCAN_START)\n#define BIT_CLEAR_EF_SCAN_START(x) ((x) & (~BITS_EF_SCAN_START))\n#define BIT_GET_EF_SCAN_START(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_SCAN_START) & BIT_MASK_EF_SCAN_START)\n#define BIT_SET_EF_SCAN_START(x, v)                                            \\\n\t(BIT_CLEAR_EF_SCAN_START(x) | BIT_EF_SCAN_START(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_SHIFT_EF_SCAN_START_V1 16\n#define BIT_MASK_EF_SCAN_START_V1 0x3ff\n#define BIT_EF_SCAN_START_V1(x)                                                \\\n\t(((x) & BIT_MASK_EF_SCAN_START_V1) << BIT_SHIFT_EF_SCAN_START_V1)\n#define BITS_EF_SCAN_START_V1                                                  \\\n\t(BIT_MASK_EF_SCAN_START_V1 << BIT_SHIFT_EF_SCAN_START_V1)\n#define BIT_CLEAR_EF_SCAN_START_V1(x) ((x) & (~BITS_EF_SCAN_START_V1))\n#define BIT_GET_EF_SCAN_START_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_EF_SCAN_START_V1) & BIT_MASK_EF_SCAN_START_V1)\n#define BIT_SET_EF_SCAN_START_V1(x, v)                                         \\\n\t(BIT_CLEAR_EF_SCAN_START_V1(x) | BIT_EF_SCAN_START_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_SHIFT_EF_SCAN_END 12\n#define BIT_MASK_EF_SCAN_END 0xf\n#define BIT_EF_SCAN_END(x)                                                     \\\n\t(((x) & BIT_MASK_EF_SCAN_END) << BIT_SHIFT_EF_SCAN_END)\n#define BITS_EF_SCAN_END (BIT_MASK_EF_SCAN_END << BIT_SHIFT_EF_SCAN_END)\n#define BIT_CLEAR_EF_SCAN_END(x) ((x) & (~BITS_EF_SCAN_END))\n#define BIT_GET_EF_SCAN_END(x)                                                 \\\n\t(((x) >> BIT_SHIFT_EF_SCAN_END) & BIT_MASK_EF_SCAN_END)\n#define BIT_SET_EF_SCAN_END(x, v)                                              \\\n\t(BIT_CLEAR_EF_SCAN_END(x) | BIT_EF_SCAN_END(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_EF_FORCE_PGMEN BIT(11)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_EF_PD_DIS BIT(11)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_SCAN_EN BIT(11)\n#define BIT_SW_PG_EN BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_SHIFT_EF_CELL_SEL 8\n#define BIT_MASK_EF_CELL_SEL 0x3\n#define BIT_EF_CELL_SEL(x)                                                     \\\n\t(((x) & BIT_MASK_EF_CELL_SEL) << BIT_SHIFT_EF_CELL_SEL)\n#define BITS_EF_CELL_SEL (BIT_MASK_EF_CELL_SEL << BIT_SHIFT_EF_CELL_SEL)\n#define BIT_CLEAR_EF_CELL_SEL(x) ((x) & (~BITS_EF_CELL_SEL))\n#define BIT_GET_EF_CELL_SEL(x)                                                 \\\n\t(((x) >> BIT_SHIFT_EF_CELL_SEL) & BIT_MASK_EF_CELL_SEL)\n#define BIT_SET_EF_CELL_SEL(x, v)                                              \\\n\t(BIT_CLEAR_EF_CELL_SEL(x) | BIT_EF_CELL_SEL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LDO_EFUSE_CTRL\t\t\t(Offset 0x0034) */\n\n#define BIT_EF_TRPT BIT(7)\n\n#define BIT_SHIFT_EF_TTHD 0\n#define BIT_MASK_EF_TTHD 0x7f\n#define BIT_EF_TTHD(x) (((x) & BIT_MASK_EF_TTHD) << BIT_SHIFT_EF_TTHD)\n#define BITS_EF_TTHD (BIT_MASK_EF_TTHD << BIT_SHIFT_EF_TTHD)\n#define BIT_CLEAR_EF_TTHD(x) ((x) & (~BITS_EF_TTHD))\n#define BIT_GET_EF_TTHD(x) (((x) >> BIT_SHIFT_EF_TTHD) & BIT_MASK_EF_TTHD)\n#define BIT_SET_EF_TTHD(x, v) (BIT_CLEAR_EF_TTHD(x) | BIT_EF_TTHD(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SHIFT_UPHY_BG_ON_OPT 30\n#define BIT_MASK_UPHY_BG_ON_OPT 0x3\n#define BIT_UPHY_BG_ON_OPT(x)                                                  \\\n\t(((x) & BIT_MASK_UPHY_BG_ON_OPT) << BIT_SHIFT_UPHY_BG_ON_OPT)\n#define BITS_UPHY_BG_ON_OPT                                                    \\\n\t(BIT_MASK_UPHY_BG_ON_OPT << BIT_SHIFT_UPHY_BG_ON_OPT)\n#define BIT_CLEAR_UPHY_BG_ON_OPT(x) ((x) & (~BITS_UPHY_BG_ON_OPT))\n#define BIT_GET_UPHY_BG_ON_OPT(x)                                              \\\n\t(((x) >> BIT_SHIFT_UPHY_BG_ON_OPT) & BIT_MASK_UPHY_BG_ON_OPT)\n#define BIT_SET_UPHY_BG_ON_OPT(x, v)                                           \\\n\t(BIT_CLEAR_UPHY_BG_ON_OPT(x) | BIT_UPHY_BG_ON_OPT(v))\n\n#define BIT_UPHY_BG_ON_USB2 BIT(29)\n#define BIT_UPHY_BG_ON_PCIE BIT(28)\n#define BIT_VD33IO_LEFT_SHD_N_ BIT(27)\n#define BIT_VDIO_RIGHT1_SHD_N_ BIT(26)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SHIFT_AFE_USB_CURRENT_SEL 26\n#define BIT_MASK_AFE_USB_CURRENT_SEL 0x7\n#define BIT_AFE_USB_CURRENT_SEL(x)                                             \\\n\t(((x) & BIT_MASK_AFE_USB_CURRENT_SEL) << BIT_SHIFT_AFE_USB_CURRENT_SEL)\n#define BITS_AFE_USB_CURRENT_SEL                                               \\\n\t(BIT_MASK_AFE_USB_CURRENT_SEL << BIT_SHIFT_AFE_USB_CURRENT_SEL)\n#define BIT_CLEAR_AFE_USB_CURRENT_SEL(x) ((x) & (~BITS_AFE_USB_CURRENT_SEL))\n#define BIT_GET_AFE_USB_CURRENT_SEL(x)                                         \\\n\t(((x) >> BIT_SHIFT_AFE_USB_CURRENT_SEL) & BIT_MASK_AFE_USB_CURRENT_SEL)\n#define BIT_SET_AFE_USB_CURRENT_SEL(x, v)                                      \\\n\t(BIT_CLEAR_AFE_USB_CURRENT_SEL(x) | BIT_AFE_USB_CURRENT_SEL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_VDIO_RIGHT0_SHD_N_ BIT(25)\n#define BIT_DIS_LPS_WT_PDNSUS BIT(24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SHIFT_AFE_USB_PATH_SEL 24\n#define BIT_MASK_AFE_USB_PATH_SEL 0x3\n#define BIT_AFE_USB_PATH_SEL(x)                                                \\\n\t(((x) & BIT_MASK_AFE_USB_PATH_SEL) << BIT_SHIFT_AFE_USB_PATH_SEL)\n#define BITS_AFE_USB_PATH_SEL                                                  \\\n\t(BIT_MASK_AFE_USB_PATH_SEL << BIT_SHIFT_AFE_USB_PATH_SEL)\n#define BIT_CLEAR_AFE_USB_PATH_SEL(x) ((x) & (~BITS_AFE_USB_PATH_SEL))\n#define BIT_GET_AFE_USB_PATH_SEL(x)                                            \\\n\t(((x) >> BIT_SHIFT_AFE_USB_PATH_SEL) & BIT_MASK_AFE_USB_PATH_SEL)\n#define BIT_SET_AFE_USB_PATH_SEL(x, v)                                         \\\n\t(BIT_CLEAR_AFE_USB_PATH_SEL(x) | BIT_AFE_USB_PATH_SEL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SHIFT_DBG_SEL_V1 16\n#define BIT_MASK_DBG_SEL_V1 0xff\n#define BIT_DBG_SEL_V1(x) (((x) & BIT_MASK_DBG_SEL_V1) << BIT_SHIFT_DBG_SEL_V1)\n#define BITS_DBG_SEL_V1 (BIT_MASK_DBG_SEL_V1 << BIT_SHIFT_DBG_SEL_V1)\n#define BIT_CLEAR_DBG_SEL_V1(x) ((x) & (~BITS_DBG_SEL_V1))\n#define BIT_GET_DBG_SEL_V1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DBG_SEL_V1) & BIT_MASK_DBG_SEL_V1)\n#define BIT_SET_DBG_SEL_V1(x, v) (BIT_CLEAR_DBG_SEL_V1(x) | BIT_DBG_SEL_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_CLK_REQ_INPUT BIT(15)\n#define BIT_USB_XTAL_CLK_SEL BIT(14)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SHIFT_DBG_SEL_BYTE 14\n#define BIT_MASK_DBG_SEL_BYTE 0x3\n#define BIT_DBG_SEL_BYTE(x)                                                    \\\n\t(((x) & BIT_MASK_DBG_SEL_BYTE) << BIT_SHIFT_DBG_SEL_BYTE)\n#define BITS_DBG_SEL_BYTE (BIT_MASK_DBG_SEL_BYTE << BIT_SHIFT_DBG_SEL_BYTE)\n#define BIT_CLEAR_DBG_SEL_BYTE(x) ((x) & (~BITS_DBG_SEL_BYTE))\n#define BIT_GET_DBG_SEL_BYTE(x)                                                \\\n\t(((x) >> BIT_SHIFT_DBG_SEL_BYTE) & BIT_MASK_DBG_SEL_BYTE)\n#define BIT_SET_DBG_SEL_BYTE(x, v)                                             \\\n\t(BIT_CLEAR_DBG_SEL_BYTE(x) | BIT_DBG_SEL_BYTE(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_USB_REG_XTAL_SEL BIT(14)\n#define BIT_SYSON_BTIO1POW_PAD_E2 BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SHIFT_SYSON_SPS0_STD_L1 12\n#define BIT_MASK_SYSON_SPS0_STD_L1 0x3\n#define BIT_SYSON_SPS0_STD_L1(x)                                               \\\n\t(((x) & BIT_MASK_SYSON_SPS0_STD_L1) << BIT_SHIFT_SYSON_SPS0_STD_L1)\n#define BITS_SYSON_SPS0_STD_L1                                                 \\\n\t(BIT_MASK_SYSON_SPS0_STD_L1 << BIT_SHIFT_SYSON_SPS0_STD_L1)\n#define BIT_CLEAR_SYSON_SPS0_STD_L1(x) ((x) & (~BITS_SYSON_SPS0_STD_L1))\n#define BIT_GET_SYSON_SPS0_STD_L1(x)                                           \\\n\t(((x) >> BIT_SHIFT_SYSON_SPS0_STD_L1) & BIT_MASK_SYSON_SPS0_STD_L1)\n#define BIT_SET_SYSON_SPS0_STD_L1(x, v)                                        \\\n\t(BIT_CLEAR_SYSON_SPS0_STD_L1(x) | BIT_SYSON_SPS0_STD_L1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SHIFT_STD_L1_V1 12\n#define BIT_MASK_STD_L1_V1 0x3\n#define BIT_STD_L1_V1(x) (((x) & BIT_MASK_STD_L1_V1) << BIT_SHIFT_STD_L1_V1)\n#define BITS_STD_L1_V1 (BIT_MASK_STD_L1_V1 << BIT_SHIFT_STD_L1_V1)\n#define BIT_CLEAR_STD_L1_V1(x) ((x) & (~BITS_STD_L1_V1))\n#define BIT_GET_STD_L1_V1(x) (((x) >> BIT_SHIFT_STD_L1_V1) & BIT_MASK_STD_L1_V1)\n#define BIT_SET_STD_L1_V1(x, v) (BIT_CLEAR_STD_L1_V1(x) | BIT_STD_L1_V1(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SYSON_BTIOPOW_PAD_E2 BIT(12)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SHIFT_SYSON_LDOA12V_WT 12\n#define BIT_MASK_SYSON_LDOA12V_WT 0x3\n#define BIT_SYSON_LDOA12V_WT(x)                                                \\\n\t(((x) & BIT_MASK_SYSON_LDOA12V_WT) << BIT_SHIFT_SYSON_LDOA12V_WT)\n#define BITS_SYSON_LDOA12V_WT                                                  \\\n\t(BIT_MASK_SYSON_LDOA12V_WT << BIT_SHIFT_SYSON_LDOA12V_WT)\n#define BIT_CLEAR_SYSON_LDOA12V_WT(x) ((x) & (~BITS_SYSON_LDOA12V_WT))\n#define BIT_GET_SYSON_LDOA12V_WT(x)                                            \\\n\t(((x) >> BIT_SHIFT_SYSON_LDOA12V_WT) & BIT_MASK_SYSON_LDOA12V_WT)\n#define BIT_SET_SYSON_LDOA12V_WT(x, v)                                         \\\n\t(BIT_CLEAR_SYSON_LDOA12V_WT(x) | BIT_SYSON_LDOA12V_WT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SYSON_DBG_PAD_E2 BIT(11)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SYSON_SDIOPOW_PAD_E2 BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SYSON_LED_PAD_E2 BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SYSON_GPEE_PAD_E2 BIT(9)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SYSON_GPEE_PAD_E2_V33 BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SYSON_PCI_PAD_E2 BIT(8)\n\n#define BIT_SHIFT_MATCH_CNT 8\n#define BIT_MASK_MATCH_CNT 0xff\n#define BIT_MATCH_CNT(x) (((x) & BIT_MASK_MATCH_CNT) << BIT_SHIFT_MATCH_CNT)\n#define BITS_MATCH_CNT (BIT_MASK_MATCH_CNT << BIT_SHIFT_MATCH_CNT)\n#define BIT_CLEAR_MATCH_CNT(x) ((x) & (~BITS_MATCH_CNT))\n#define BIT_GET_MATCH_CNT(x) (((x) >> BIT_SHIFT_MATCH_CNT) & BIT_MASK_MATCH_CNT)\n#define BIT_SET_MATCH_CNT(x, v) (BIT_CLEAR_MATCH_CNT(x) | BIT_MATCH_CNT(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_AUTO_SW_LDO_VOL_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_AUTO_SW_LDO_VOL_EN_V1 BIT(6)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_ADJ_LDO_VOLT BIT(6)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SHIFT_SYSON_LDOHCI12_WT 6\n#define BIT_MASK_SYSON_LDOHCI12_WT 0x3\n#define BIT_SYSON_LDOHCI12_WT(x)                                               \\\n\t(((x) & BIT_MASK_SYSON_LDOHCI12_WT) << BIT_SHIFT_SYSON_LDOHCI12_WT)\n#define BITS_SYSON_LDOHCI12_WT                                                 \\\n\t(BIT_MASK_SYSON_LDOHCI12_WT << BIT_SHIFT_SYSON_LDOHCI12_WT)\n#define BIT_CLEAR_SYSON_LDOHCI12_WT(x) ((x) & (~BITS_SYSON_LDOHCI12_WT))\n#define BIT_GET_SYSON_LDOHCI12_WT(x)                                           \\\n\t(((x) >> BIT_SHIFT_SYSON_LDOHCI12_WT) & BIT_MASK_SYSON_LDOHCI12_WT)\n#define BIT_SET_SYSON_LDOHCI12_WT(x, v)                                        \\\n\t(BIT_CLEAR_SYSON_LDOHCI12_WT(x) | BIT_SYSON_LDOHCI12_WT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SHIFT_SYSON_SPS0WWV_WT 4\n#define BIT_MASK_SYSON_SPS0WWV_WT 0x3\n#define BIT_SYSON_SPS0WWV_WT(x)                                                \\\n\t(((x) & BIT_MASK_SYSON_SPS0WWV_WT) << BIT_SHIFT_SYSON_SPS0WWV_WT)\n#define BITS_SYSON_SPS0WWV_WT                                                  \\\n\t(BIT_MASK_SYSON_SPS0WWV_WT << BIT_SHIFT_SYSON_SPS0WWV_WT)\n#define BIT_CLEAR_SYSON_SPS0WWV_WT(x) ((x) & (~BITS_SYSON_SPS0WWV_WT))\n#define BIT_GET_SYSON_SPS0WWV_WT(x)                                            \\\n\t(((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT) & BIT_MASK_SYSON_SPS0WWV_WT)\n#define BIT_SET_SYSON_SPS0WWV_WT(x, v)                                         \\\n\t(BIT_CLEAR_SYSON_SPS0WWV_WT(x) | BIT_SYSON_SPS0WWV_WT(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SHIFT_SYSON_SPS0SPS_WT 4\n#define BIT_MASK_SYSON_SPS0SPS_WT 0x3\n#define BIT_SYSON_SPS0SPS_WT(x)                                                \\\n\t(((x) & BIT_MASK_SYSON_SPS0SPS_WT) << BIT_SHIFT_SYSON_SPS0SPS_WT)\n#define BITS_SYSON_SPS0SPS_WT                                                  \\\n\t(BIT_MASK_SYSON_SPS0SPS_WT << BIT_SHIFT_SYSON_SPS0SPS_WT)\n#define BIT_CLEAR_SYSON_SPS0SPS_WT(x) ((x) & (~BITS_SYSON_SPS0SPS_WT))\n#define BIT_GET_SYSON_SPS0SPS_WT(x)                                            \\\n\t(((x) >> BIT_SHIFT_SYSON_SPS0SPS_WT) & BIT_MASK_SYSON_SPS0SPS_WT)\n#define BIT_SET_SYSON_SPS0SPS_WT(x, v)                                         \\\n\t(BIT_CLEAR_SYSON_SPS0SPS_WT(x) | BIT_SYSON_SPS0SPS_WT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SHIFT_SYSON_SPS0LDO_WT 2\n#define BIT_MASK_SYSON_SPS0LDO_WT 0x3\n#define BIT_SYSON_SPS0LDO_WT(x)                                                \\\n\t(((x) & BIT_MASK_SYSON_SPS0LDO_WT) << BIT_SHIFT_SYSON_SPS0LDO_WT)\n#define BITS_SYSON_SPS0LDO_WT                                                  \\\n\t(BIT_MASK_SYSON_SPS0LDO_WT << BIT_SHIFT_SYSON_SPS0LDO_WT)\n#define BIT_CLEAR_SYSON_SPS0LDO_WT(x) ((x) & (~BITS_SYSON_SPS0LDO_WT))\n#define BIT_GET_SYSON_SPS0LDO_WT(x)                                            \\\n\t(((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT) & BIT_MASK_SYSON_SPS0LDO_WT)\n#define BIT_SET_SYSON_SPS0LDO_WT(x, v)                                         \\\n\t(BIT_CLEAR_SYSON_SPS0LDO_WT(x) | BIT_SYSON_SPS0LDO_WT(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SHIFT_SYSON_SPS11VLDO_WT 2\n#define BIT_MASK_SYSON_SPS11VLDO_WT 0x3\n#define BIT_SYSON_SPS11VLDO_WT(x)                                              \\\n\t(((x) & BIT_MASK_SYSON_SPS11VLDO_WT) << BIT_SHIFT_SYSON_SPS11VLDO_WT)\n#define BITS_SYSON_SPS11VLDO_WT                                                \\\n\t(BIT_MASK_SYSON_SPS11VLDO_WT << BIT_SHIFT_SYSON_SPS11VLDO_WT)\n#define BIT_CLEAR_SYSON_SPS11VLDO_WT(x) ((x) & (~BITS_SYSON_SPS11VLDO_WT))\n#define BIT_GET_SYSON_SPS11VLDO_WT(x)                                          \\\n\t(((x) >> BIT_SHIFT_SYSON_SPS11VLDO_WT) & BIT_MASK_SYSON_SPS11VLDO_WT)\n#define BIT_SET_SYSON_SPS11VLDO_WT(x, v)                                       \\\n\t(BIT_CLEAR_SYSON_SPS11VLDO_WT(x) | BIT_SYSON_SPS11VLDO_WT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PWR_OPTION_CTRL\t\t\t(Offset 0x0038) */\n\n#define BIT_SHIFT_SYSON_RCLK_SCALE 0\n#define BIT_MASK_SYSON_RCLK_SCALE 0x3\n#define BIT_SYSON_RCLK_SCALE(x)                                                \\\n\t(((x) & BIT_MASK_SYSON_RCLK_SCALE) << BIT_SHIFT_SYSON_RCLK_SCALE)\n#define BITS_SYSON_RCLK_SCALE                                                  \\\n\t(BIT_MASK_SYSON_RCLK_SCALE << BIT_SHIFT_SYSON_RCLK_SCALE)\n#define BIT_CLEAR_SYSON_RCLK_SCALE(x) ((x) & (~BITS_SYSON_RCLK_SCALE))\n#define BIT_GET_SYSON_RCLK_SCALE(x)                                            \\\n\t(((x) >> BIT_SHIFT_SYSON_RCLK_SCALE) & BIT_MASK_SYSON_RCLK_SCALE)\n#define BIT_SET_SYSON_RCLK_SCALE(x, v)                                         \\\n\t(BIT_CLEAR_SYSON_RCLK_SCALE(x) | BIT_SYSON_RCLK_SCALE(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HCPWM1_V2\t\t\t(Offset 0x10250038) */\n\n#define BIT_CUR_PS BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CAL_TIMER\t\t\t\t(Offset 0x003C) */\n\n#define BIT_SHIFT_CAL_SCAL 0\n#define BIT_MASK_CAL_SCAL 0xff\n#define BIT_CAL_SCAL(x) (((x) & BIT_MASK_CAL_SCAL) << BIT_SHIFT_CAL_SCAL)\n#define BITS_CAL_SCAL (BIT_MASK_CAL_SCAL << BIT_SHIFT_CAL_SCAL)\n#define BIT_CLEAR_CAL_SCAL(x) ((x) & (~BITS_CAL_SCAL))\n#define BIT_GET_CAL_SCAL(x) (((x) >> BIT_SHIFT_CAL_SCAL) & BIT_MASK_CAL_SCAL)\n#define BIT_SET_CAL_SCAL(x, v) (BIT_CLEAR_CAL_SCAL(x) | BIT_CAL_SCAL(v))\n\n/* 2 REG_ACLK_MON\t\t\t\t(Offset 0x003E) */\n\n#define BIT_SHIFT_RCLK_MON 5\n#define BIT_MASK_RCLK_MON 0x7ff\n#define BIT_RCLK_MON(x) (((x) & BIT_MASK_RCLK_MON) << BIT_SHIFT_RCLK_MON)\n#define BITS_RCLK_MON (BIT_MASK_RCLK_MON << BIT_SHIFT_RCLK_MON)\n#define BIT_CLEAR_RCLK_MON(x) ((x) & (~BITS_RCLK_MON))\n#define BIT_GET_RCLK_MON(x) (((x) >> BIT_SHIFT_RCLK_MON) & BIT_MASK_RCLK_MON)\n#define BIT_SET_RCLK_MON(x, v) (BIT_CLEAR_RCLK_MON(x) | BIT_RCLK_MON(v))\n\n#define BIT_CAL_EN BIT(4)\n\n#define BIT_SHIFT_DPSTU 2\n#define BIT_MASK_DPSTU 0x3\n#define BIT_DPSTU(x) (((x) & BIT_MASK_DPSTU) << BIT_SHIFT_DPSTU)\n#define BITS_DPSTU (BIT_MASK_DPSTU << BIT_SHIFT_DPSTU)\n#define BIT_CLEAR_DPSTU(x) ((x) & (~BITS_DPSTU))\n#define BIT_GET_DPSTU(x) (((x) >> BIT_SHIFT_DPSTU) & BIT_MASK_DPSTU)\n#define BIT_SET_DPSTU(x, v) (BIT_CLEAR_DPSTU(x) | BIT_DPSTU(v))\n\n#define BIT_SUS_16X BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ACLK_MON\t\t\t\t(Offset 0x003E) */\n\n#define BIT_RSM_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG_2\t\t\t(Offset 0x003F) */\n\n#define BIT_SOUT_GPIO8 BIT(7)\n#define BIT_SOUT_GPIO5 BIT(6)\n#define BIT_RFE_CTRL_5_GPIO14_V1 BIT(5)\n#define BIT_RFE_CTRL_10_GPIO13_V1 BIT(4)\n#define BIT_RFE_CTRL_11_GPIO4_V1 BIT(3)\n#define BIT_RFE_CTRL_5_GPIO14 BIT(2)\n#define BIT_RFE_CTRL_10_GPIO13 BIT(1)\n#define BIT_RFE_CTRL_11_GPIO4 BIT(0)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_RFE_CTRL_3_GPIO12 BIT(31)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_PAD_D_PAPE_2G_E BIT(31)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_BT_RFE_CTRL_5_GPIO12 BIT(30)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_PAD_D_PAPE_5G_E BIT(30)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_SIC_LOWEST_PRIORITY_V1 BIT(29)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_S0_TRSW_GPIO12 BIT(29)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_PAD_D_TRSW_E BIT(29)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_SIC_PRI_LOWEST BIT(28)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_SIC_LOWEST_PRIORITY BIT(28)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_RFE_CTRL_9_GPIO13 BIT(28)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_PAD_D_TRSWB_E BIT(28)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_WL_DSS_RSTN BIT(27)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_RFE_CTRL_9_GPIO12 BIT(27)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_PAD_D_PAPE_2G_O BIT(27)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_WL_DSS_EN_CLK BIT(26)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_RFE_CTRL_8_GPIO4 BIT(26)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_PAD_D_PAPE_5G_O BIT(26)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_BT_RFE_CTRL_1_GPIO13 BIT(25)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_PAD_D_TRSW_O BIT(25)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_SHIFT_PIN_USECASE 24\n#define BIT_MASK_PIN_USECASE 0xf\n#define BIT_PIN_USECASE(x)                                                     \\\n\t(((x) & BIT_MASK_PIN_USECASE) << BIT_SHIFT_PIN_USECASE)\n#define BITS_PIN_USECASE (BIT_MASK_PIN_USECASE << BIT_SHIFT_PIN_USECASE)\n#define BIT_CLEAR_PIN_USECASE(x) ((x) & (~BITS_PIN_USECASE))\n#define BIT_GET_PIN_USECASE(x)                                                 \\\n\t(((x) >> BIT_SHIFT_PIN_USECASE) & BIT_MASK_PIN_USECASE)\n#define BIT_SET_PIN_USECASE(x, v)                                              \\\n\t(BIT_CLEAR_PIN_USECASE(x) | BIT_PIN_USECASE(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_SHIFT_PIN_USECASE_V1 24\n#define BIT_MASK_PIN_USECASE_V1 0x1f\n#define BIT_PIN_USECASE_V1(x)                                                  \\\n\t(((x) & BIT_MASK_PIN_USECASE_V1) << BIT_SHIFT_PIN_USECASE_V1)\n#define BITS_PIN_USECASE_V1                                                    \\\n\t(BIT_MASK_PIN_USECASE_V1 << BIT_SHIFT_PIN_USECASE_V1)\n#define BIT_CLEAR_PIN_USECASE_V1(x) ((x) & (~BITS_PIN_USECASE_V1))\n#define BIT_GET_PIN_USECASE_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_PIN_USECASE_V1) & BIT_MASK_PIN_USECASE_V1)\n#define BIT_SET_PIN_USECASE_V1(x, v)                                           \\\n\t(BIT_CLEAR_PIN_USECASE_V1(x) | BIT_PIN_USECASE_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_BT_RFE_CTRL_1_GPIO12 BIT(24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_PAD_D_TRSWB_O BIT(24)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_EN_DATACPU_GPIO2 BIT(24)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_BT_RFE_CTRL_0_GPIO4 BIT(23)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_EN_A_ANTSEL BIT(23)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_EN_DATACPU_GPIO BIT(23)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_ANTSW_GPIO13 BIT(22)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_EN_A_ANTSELB BIT(22)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_EN_DATACPU_UART BIT(22)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_ANTSW_GPIO12 BIT(21)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_EN_D_PAPE_2G BIT(21)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_DATACPU_FSPI_EN BIT(21)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_INDIRECT_REG_CFG\t\t(Offset 0x10250040) */\n\n#define BIT_INDIRECT_REG_RDY BIT(20)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_ANTSWB_GPIO4 BIT(20)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_EN_D_PAPE_5G BIT(20)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_EN_GPIO8_UART_OUT BIT(20)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_FSPI_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_SW_IO_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_INDIRECT_REG_CFG\t\t(Offset 0x10250040) */\n\n#define BIT_INDIRECT_REG_R BIT(19)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_WL_RTS_EXT_32K_SEL BIT(18)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_INDIRECT_REG_CFG\t\t(Offset 0x10250040) */\n\n#define BIT_INDIRECT_REG_W BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_CKOUT33_EN BIT(17)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_WLBT_DPDT_SEL_EN BIT(17)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_XTAL_OUT_EN BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_WLGP_SPI_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_WLGP_CKOUT BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_INDIRECT_REG_CFG\t\t(Offset 0x10250040) */\n\n#define BIT_SHIFT_INDIRECT_REG_SIZE 16\n#define BIT_MASK_INDIRECT_REG_SIZE 0x3\n#define BIT_INDIRECT_REG_SIZE(x)                                               \\\n\t(((x) & BIT_MASK_INDIRECT_REG_SIZE) << BIT_SHIFT_INDIRECT_REG_SIZE)\n#define BITS_INDIRECT_REG_SIZE                                                 \\\n\t(BIT_MASK_INDIRECT_REG_SIZE << BIT_SHIFT_INDIRECT_REG_SIZE)\n#define BIT_CLEAR_INDIRECT_REG_SIZE(x) ((x) & (~BITS_INDIRECT_REG_SIZE))\n#define BIT_GET_INDIRECT_REG_SIZE(x)                                           \\\n\t(((x) >> BIT_SHIFT_INDIRECT_REG_SIZE) & BIT_MASK_INDIRECT_REG_SIZE)\n#define BIT_SET_INDIRECT_REG_SIZE(x, v)                                        \\\n\t(BIT_CLEAR_INDIRECT_REG_SIZE(x) | BIT_INDIRECT_REG_SIZE(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_WLBT_LNAON_SEL_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_SIC_LBK BIT(15)\n#define BIT_ENHTP BIT(14)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_PHY_TEST_EN BIT(13)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_WLPHY_DBG_EN BIT(13)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_BT_AOD_GPIO3 BIT(13)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_SIC_23 BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_ENSIC BIT(12)\n#define BIT_SIC_SWRST BIT(11)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_PO_WIFI_PTA_PINS BIT(10)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_ENPMAC BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_ENBTCMD BIT(9)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_COEX_MBOX BIT(9)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_BTCOEX_MBOX_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_PO_BT_PTA_PINS BIT(9)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_BTCMD_OUT_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_ENUART BIT(8)\n\n#define BIT_SHIFT_BTMODE 6\n#define BIT_MASK_BTMODE 0x3\n#define BIT_BTMODE(x) (((x) & BIT_MASK_BTMODE) << BIT_SHIFT_BTMODE)\n#define BITS_BTMODE (BIT_MASK_BTMODE << BIT_SHIFT_BTMODE)\n#define BIT_CLEAR_BTMODE(x) ((x) & (~BITS_BTMODE))\n#define BIT_GET_BTMODE(x) (((x) >> BIT_SHIFT_BTMODE) & BIT_MASK_BTMODE)\n#define BIT_SET_BTMODE(x, v) (BIT_CLEAR_BTMODE(x) | BIT_BTMODE(v))\n\n#define BIT_ENBT BIT(5)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_GEN1GEN2_SWITCH BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_EROM_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_ENUARTTX BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_WLRFE_6_7_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_WLRFE_12_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_EN_D_TRSW BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_WLRFE_4_5_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_SPDT_SEL BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_EN_D_TRSWB BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_MUXCFG\t\t\t\t(Offset 0x0040) */\n\n#define BIT_SHIFT_GPIOSEL 0\n#define BIT_MASK_GPIOSEL 0x3\n#define BIT_GPIOSEL(x) (((x) & BIT_MASK_GPIOSEL) << BIT_SHIFT_GPIOSEL)\n#define BITS_GPIOSEL (BIT_MASK_GPIOSEL << BIT_SHIFT_GPIOSEL)\n#define BIT_CLEAR_GPIOSEL(x) ((x) & (~BITS_GPIOSEL))\n#define BIT_GET_GPIOSEL(x) (((x) >> BIT_SHIFT_GPIOSEL) & BIT_MASK_GPIOSEL)\n#define BIT_SET_GPIOSEL(x, v) (BIT_CLEAR_GPIOSEL(x) | BIT_GPIOSEL(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_INDIRECT_REG_CFG\t\t(Offset 0x10250040) */\n\n#define BIT_SHIFT_INDIRECT_REG_ADDR 0\n#define BIT_MASK_INDIRECT_REG_ADDR 0xffff\n#define BIT_INDIRECT_REG_ADDR(x)                                               \\\n\t(((x) & BIT_MASK_INDIRECT_REG_ADDR) << BIT_SHIFT_INDIRECT_REG_ADDR)\n#define BITS_INDIRECT_REG_ADDR                                                 \\\n\t(BIT_MASK_INDIRECT_REG_ADDR << BIT_SHIFT_INDIRECT_REG_ADDR)\n#define BIT_CLEAR_INDIRECT_REG_ADDR(x) ((x) & (~BITS_INDIRECT_REG_ADDR))\n#define BIT_GET_INDIRECT_REG_ADDR(x)                                           \\\n\t(((x) >> BIT_SHIFT_INDIRECT_REG_ADDR) & BIT_MASK_INDIRECT_REG_ADDR)\n#define BIT_SET_INDIRECT_REG_ADDR(x, v)                                        \\\n\t(BIT_CLEAR_INDIRECT_REG_ADDR(x) | BIT_INDIRECT_REG_ADDR(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_PIN_CTRL\t\t\t(Offset 0x0044) */\n\n#define BIT_SHIFT_GPIO_MOD_7_TO_0 24\n#define BIT_MASK_GPIO_MOD_7_TO_0 0xff\n#define BIT_GPIO_MOD_7_TO_0(x)                                                 \\\n\t(((x) & BIT_MASK_GPIO_MOD_7_TO_0) << BIT_SHIFT_GPIO_MOD_7_TO_0)\n#define BITS_GPIO_MOD_7_TO_0                                                   \\\n\t(BIT_MASK_GPIO_MOD_7_TO_0 << BIT_SHIFT_GPIO_MOD_7_TO_0)\n#define BIT_CLEAR_GPIO_MOD_7_TO_0(x) ((x) & (~BITS_GPIO_MOD_7_TO_0))\n#define BIT_GET_GPIO_MOD_7_TO_0(x)                                             \\\n\t(((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0) & BIT_MASK_GPIO_MOD_7_TO_0)\n#define BIT_SET_GPIO_MOD_7_TO_0(x, v)                                          \\\n\t(BIT_CLEAR_GPIO_MOD_7_TO_0(x) | BIT_GPIO_MOD_7_TO_0(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_GPIO_PIN_CTRL\t\t\t(Offset 0x0044) */\n\n#define BIT_SHIFT_WLGP1_SWIOMOD 24\n#define BIT_MASK_WLGP1_SWIOMOD 0xff\n#define BIT_WLGP1_SWIOMOD(x)                                                   \\\n\t(((x) & BIT_MASK_WLGP1_SWIOMOD) << BIT_SHIFT_WLGP1_SWIOMOD)\n#define BITS_WLGP1_SWIOMOD (BIT_MASK_WLGP1_SWIOMOD << BIT_SHIFT_WLGP1_SWIOMOD)\n#define BIT_CLEAR_WLGP1_SWIOMOD(x) ((x) & (~BITS_WLGP1_SWIOMOD))\n#define BIT_GET_WLGP1_SWIOMOD(x)                                               \\\n\t(((x) >> BIT_SHIFT_WLGP1_SWIOMOD) & BIT_MASK_WLGP1_SWIOMOD)\n#define BIT_SET_WLGP1_SWIOMOD(x, v)                                            \\\n\t(BIT_CLEAR_WLGP1_SWIOMOD(x) | BIT_WLGP1_SWIOMOD(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_PIN_CTRL\t\t\t(Offset 0x0044) */\n\n#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0 16\n#define BIT_MASK_GPIO_IO_SEL_7_TO_0 0xff\n#define BIT_GPIO_IO_SEL_7_TO_0(x)                                              \\\n\t(((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0)\n#define BITS_GPIO_IO_SEL_7_TO_0                                                \\\n\t(BIT_MASK_GPIO_IO_SEL_7_TO_0 << BIT_SHIFT_GPIO_IO_SEL_7_TO_0)\n#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0(x) ((x) & (~BITS_GPIO_IO_SEL_7_TO_0))\n#define BIT_GET_GPIO_IO_SEL_7_TO_0(x)                                          \\\n\t(((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0) & BIT_MASK_GPIO_IO_SEL_7_TO_0)\n#define BIT_SET_GPIO_IO_SEL_7_TO_0(x, v)                                       \\\n\t(BIT_CLEAR_GPIO_IO_SEL_7_TO_0(x) | BIT_GPIO_IO_SEL_7_TO_0(v))\n\n#define BIT_SHIFT_GPIO_OUT_7_TO_0 8\n#define BIT_MASK_GPIO_OUT_7_TO_0 0xff\n#define BIT_GPIO_OUT_7_TO_0(x)                                                 \\\n\t(((x) & BIT_MASK_GPIO_OUT_7_TO_0) << BIT_SHIFT_GPIO_OUT_7_TO_0)\n#define BITS_GPIO_OUT_7_TO_0                                                   \\\n\t(BIT_MASK_GPIO_OUT_7_TO_0 << BIT_SHIFT_GPIO_OUT_7_TO_0)\n#define BIT_CLEAR_GPIO_OUT_7_TO_0(x) ((x) & (~BITS_GPIO_OUT_7_TO_0))\n#define BIT_GET_GPIO_OUT_7_TO_0(x)                                             \\\n\t(((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0) & BIT_MASK_GPIO_OUT_7_TO_0)\n#define BIT_SET_GPIO_OUT_7_TO_0(x, v)                                          \\\n\t(BIT_CLEAR_GPIO_OUT_7_TO_0(x) | BIT_GPIO_OUT_7_TO_0(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_PIN_CTRL\t\t\t(Offset 0x0044) */\n\n#define BIT_SHIFT_GPIO_IN_7_TO_0 0\n#define BIT_MASK_GPIO_IN_7_TO_0 0xff\n#define BIT_GPIO_IN_7_TO_0(x)                                                  \\\n\t(((x) & BIT_MASK_GPIO_IN_7_TO_0) << BIT_SHIFT_GPIO_IN_7_TO_0)\n#define BITS_GPIO_IN_7_TO_0                                                    \\\n\t(BIT_MASK_GPIO_IN_7_TO_0 << BIT_SHIFT_GPIO_IN_7_TO_0)\n#define BIT_CLEAR_GPIO_IN_7_TO_0(x) ((x) & (~BITS_GPIO_IN_7_TO_0))\n#define BIT_GET_GPIO_IN_7_TO_0(x)                                              \\\n\t(((x) >> BIT_SHIFT_GPIO_IN_7_TO_0) & BIT_MASK_GPIO_IN_7_TO_0)\n#define BIT_SET_GPIO_IN_7_TO_0(x, v)                                           \\\n\t(BIT_CLEAR_GPIO_IN_7_TO_0(x) | BIT_GPIO_IN_7_TO_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_INDIRECT_REG_DATA\t\t(Offset 0x10250044) */\n\n#define BIT_SHIFT_INDIRECT_REG_DATA 0\n#define BIT_MASK_INDIRECT_REG_DATA 0xffffffffL\n#define BIT_INDIRECT_REG_DATA(x)                                               \\\n\t(((x) & BIT_MASK_INDIRECT_REG_DATA) << BIT_SHIFT_INDIRECT_REG_DATA)\n#define BITS_INDIRECT_REG_DATA                                                 \\\n\t(BIT_MASK_INDIRECT_REG_DATA << BIT_SHIFT_INDIRECT_REG_DATA)\n#define BIT_CLEAR_INDIRECT_REG_DATA(x) ((x) & (~BITS_INDIRECT_REG_DATA))\n#define BIT_GET_INDIRECT_REG_DATA(x)                                           \\\n\t(((x) >> BIT_SHIFT_INDIRECT_REG_DATA) & BIT_MASK_INDIRECT_REG_DATA)\n#define BIT_SET_INDIRECT_REG_DATA(x, v)                                        \\\n\t(BIT_CLEAR_INDIRECT_REG_DATA(x) | BIT_INDIRECT_REG_DATA(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_INTM\t\t\t\t(Offset 0x0048) */\n\n#define BIT_SHIFT_MUXDBG_SEL 30\n#define BIT_MASK_MUXDBG_SEL 0x3\n#define BIT_MUXDBG_SEL(x) (((x) & BIT_MASK_MUXDBG_SEL) << BIT_SHIFT_MUXDBG_SEL)\n#define BITS_MUXDBG_SEL (BIT_MASK_MUXDBG_SEL << BIT_SHIFT_MUXDBG_SEL)\n#define BIT_CLEAR_MUXDBG_SEL(x) ((x) & (~BITS_MUXDBG_SEL))\n#define BIT_GET_MUXDBG_SEL(x)                                                  \\\n\t(((x) >> BIT_SHIFT_MUXDBG_SEL) & BIT_MASK_MUXDBG_SEL)\n#define BIT_SET_MUXDBG_SEL(x, v) (BIT_CLEAR_MUXDBG_SEL(x) | BIT_MUXDBG_SEL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_GPIO_INTM\t\t\t\t(Offset 0x0048) */\n\n#define BIT_PCI_LPS_LDACT BIT(29)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_GPIO_INTM\t\t\t\t(Offset 0x0048) */\n\n#define BIT_SHIFT_MUXDBG_SEL2 28\n#define BIT_MASK_MUXDBG_SEL2 0x3\n#define BIT_MUXDBG_SEL2(x)                                                     \\\n\t(((x) & BIT_MASK_MUXDBG_SEL2) << BIT_SHIFT_MUXDBG_SEL2)\n#define BITS_MUXDBG_SEL2 (BIT_MASK_MUXDBG_SEL2 << BIT_SHIFT_MUXDBG_SEL2)\n#define BIT_CLEAR_MUXDBG_SEL2(x) ((x) & (~BITS_MUXDBG_SEL2))\n#define BIT_GET_MUXDBG_SEL2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_MUXDBG_SEL2) & BIT_MASK_MUXDBG_SEL2)\n#define BIT_SET_MUXDBG_SEL2(x, v)                                              \\\n\t(BIT_CLEAR_MUXDBG_SEL2(x) | BIT_MUXDBG_SEL2(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_INTM\t\t\t\t(Offset 0x0048) */\n\n#define BIT_GPIO_EXT_EN BIT(20)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_GPIO_INTM\t\t\t\t(Offset 0x0048) */\n\n#define BIT_EXTWOL1_SEL BIT(19)\n#define BIT_EXTWOL1_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_INTM\t\t\t\t(Offset 0x0048) */\n\n#define BIT_EXTWOL0_SEL BIT(17)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_GPIO_INTM\t\t\t\t(Offset 0x0048) */\n\n#define BIT_BT_EXTWOL_DIS BIT(17)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_INTM\t\t\t\t(Offset 0x0048) */\n\n#define BIT_EXTWOL_SEL BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_INTM\t\t\t\t(Offset 0x0048) */\n\n#define BIT_EXTWOL0_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GPIO_INTM\t\t\t\t(Offset 0x0048) */\n\n#define BIT_EXTWOL_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GPIO_INTM\t\t\t\t(Offset 0x0048) */\n\n#define BIT_SHIFT_GPIO_EXT_WOL_V1 16\n#define BIT_MASK_GPIO_EXT_WOL_V1 0xf\n#define BIT_GPIO_EXT_WOL_V1(x)                                                 \\\n\t(((x) & BIT_MASK_GPIO_EXT_WOL_V1) << BIT_SHIFT_GPIO_EXT_WOL_V1)\n#define BITS_GPIO_EXT_WOL_V1                                                   \\\n\t(BIT_MASK_GPIO_EXT_WOL_V1 << BIT_SHIFT_GPIO_EXT_WOL_V1)\n#define BIT_CLEAR_GPIO_EXT_WOL_V1(x) ((x) & (~BITS_GPIO_EXT_WOL_V1))\n#define BIT_GET_GPIO_EXT_WOL_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_GPIO_EXT_WOL_V1) & BIT_MASK_GPIO_EXT_WOL_V1)\n#define BIT_SET_GPIO_EXT_WOL_V1(x, v)                                          \\\n\t(BIT_CLEAR_GPIO_EXT_WOL_V1(x) | BIT_GPIO_EXT_WOL_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_INTM\t\t\t\t(Offset 0x0048) */\n\n#define BIT_GPIOF_INT_MD BIT(15)\n#define BIT_GPIOE_INT_MD BIT(14)\n#define BIT_GPIOD_INT_MD BIT(13)\n#define BIT_GPIOC_INT_MD BIT(12)\n#define BIT_GPIOB_INT_MD BIT(11)\n#define BIT_GPIOA_INT_MD BIT(10)\n#define BIT_GPIO9_INT_MD BIT(9)\n#define BIT_GPIO8_INT_MD BIT(8)\n#define BIT_GPIO7_INT_MD BIT(7)\n#define BIT_GPIO6_INT_MD BIT(6)\n#define BIT_GPIO5_INT_MD BIT(5)\n#define BIT_GPIO4_INT_MD BIT(4)\n#define BIT_GPIO3_INT_MD BIT(3)\n#define BIT_GPIO2_INT_MD BIT(2)\n#define BIT_GPIO1_INT_MD BIT(1)\n#define BIT_GPIO0_INT_MD BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_MAILBOX_1WIRE_GPIO_CFG BIT(31)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_PAD_ANTSEL_I BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_ANT_SEL7_EN BIT(30)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_BT_RF_GPIO_CFG BIT(30)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_PAD_ANTSELB_I BIT(30)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_ANT_SEL46_EN BIT(29)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_BT_SDIO_INT_GPIO_CFG BIT(29)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_PAD_D_PAPE_2G_I BIT(29)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_ANT_SEL3_EN BIT(28)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_MAILBOX_3WIRE_GPIO_CFG BIT(28)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_PAD_D_PAPE_5G_I BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_TRSW_SEL_EN BIT(27)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_WLBT_PAPE_SEL_EN BIT(27)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_PAD_D_TRSW_I BIT(27)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_GPIO3_WL_CTRL_EN BIT(27)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_PAPE1_SEL_EN BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_LNAON_SEL_EN BIT(26)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_PAD_D_TRSWB_I BIT(26)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_PAPE0_SEL_EN BIT(25)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_PAPE_SEL_EN BIT(25)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_DWH_EN BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_ANTSEL2_EN BIT(24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_ANT01_EN BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_DPDT_WLBT_SEL BIT(24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_DHW_EN BIT(24)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_RFE_ANT_EXT_SEL BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_ANTSEL_EN BIT(23)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_DPDT_SEL_EN BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_GPIO13_14_WL_CTRL_EN BIT(22)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_SW_SPDT_SEL BIT(22)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_LED2DIS_V1 BIT(22)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_TRXIQ_DBG_EN BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_LED2DIS BIT(21)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_LED0_GPIO_EN BIT(21)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_LED2EN BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_LED2PL BIT(20)\n#define BIT_LED2SV BIT(19)\n\n#define BIT_SHIFT_LED2CM 16\n#define BIT_MASK_LED2CM 0x7\n#define BIT_LED2CM(x) (((x) & BIT_MASK_LED2CM) << BIT_SHIFT_LED2CM)\n#define BITS_LED2CM (BIT_MASK_LED2CM << BIT_SHIFT_LED2CM)\n#define BIT_CLEAR_LED2CM(x) ((x) & (~BITS_LED2CM))\n#define BIT_GET_LED2CM(x) (((x) >> BIT_SHIFT_LED2CM) & BIT_MASK_LED2CM)\n#define BIT_SET_LED2CM(x, v) (BIT_CLEAR_LED2CM(x) | BIT_LED2CM(v))\n\n#define BIT_LED1DIS BIT(15)\n#define BIT_LED1PL BIT(12)\n#define BIT_LED1SV BIT(11)\n\n#define BIT_SHIFT_LED1CM 8\n#define BIT_MASK_LED1CM 0x7\n#define BIT_LED1CM(x) (((x) & BIT_MASK_LED1CM) << BIT_SHIFT_LED1CM)\n#define BITS_LED1CM (BIT_MASK_LED1CM << BIT_SHIFT_LED1CM)\n#define BIT_CLEAR_LED1CM(x) ((x) & (~BITS_LED1CM))\n#define BIT_GET_LED1CM(x) (((x) >> BIT_SHIFT_LED1CM) & BIT_MASK_LED1CM)\n#define BIT_SET_LED1CM(x, v) (BIT_CLEAR_LED1CM(x) | BIT_LED1CM(v))\n\n#define BIT_LED0DIS BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_SHIFT_AFE_LDO_SWR_CHECK 5\n#define BIT_MASK_AFE_LDO_SWR_CHECK 0x3\n#define BIT_AFE_LDO_SWR_CHECK(x)                                               \\\n\t(((x) & BIT_MASK_AFE_LDO_SWR_CHECK) << BIT_SHIFT_AFE_LDO_SWR_CHECK)\n#define BITS_AFE_LDO_SWR_CHECK                                                 \\\n\t(BIT_MASK_AFE_LDO_SWR_CHECK << BIT_SHIFT_AFE_LDO_SWR_CHECK)\n#define BIT_CLEAR_AFE_LDO_SWR_CHECK(x) ((x) & (~BITS_AFE_LDO_SWR_CHECK))\n#define BIT_GET_AFE_LDO_SWR_CHECK(x)                                           \\\n\t(((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK) & BIT_MASK_AFE_LDO_SWR_CHECK)\n#define BIT_SET_AFE_LDO_SWR_CHECK(x, v)                                        \\\n\t(BIT_CLEAR_AFE_LDO_SWR_CHECK(x) | BIT_AFE_LDO_SWR_CHECK(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n\n#define BIT_LED0PL BIT(4)\n#define BIT_LED0SV BIT(3)\n\n#define BIT_SHIFT_LED0CM 0\n#define BIT_MASK_LED0CM 0x7\n#define BIT_LED0CM(x) (((x) & BIT_MASK_LED0CM) << BIT_SHIFT_LED0CM)\n#define BITS_LED0CM (BIT_MASK_LED0CM << BIT_SHIFT_LED0CM)\n#define BIT_CLEAR_LED0CM(x) ((x) & (~BITS_LED0CM))\n#define BIT_GET_LED0CM(x) (((x) >> BIT_SHIFT_LED0CM) & BIT_MASK_LED0CM)\n#define BIT_SET_LED0CM(x, v) (BIT_CLEAR_LED0CM(x) | BIT_LED0CM(v))\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_PDNINT_EN BIT(31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_NFC_INT_PAD_EN BIT(30)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_SPS_OCP_INT_EN BIT(29)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_SW_SPS_OCP_INT_EN BIT(29)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_PWMERR_INT_EN BIT(28)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_PWM_HW_ERR_EN BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIOF_INT_EN BIT(27)\n#define BIT_FS_GPIOE_INT_EN BIT(26)\n#define BIT_FS_GPIOD_INT_EN BIT(25)\n#define BIT_FS_GPIOC_INT_EN BIT(24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_ACT2RECOVERY_INT_EN BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIOB_INT_EN BIT(23)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_PCIE_GEN12_SWITCH_EN BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIOA_INT_EN BIT(22)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_HCI_SUS_EN_V1 BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO9_INT_EN BIT(21)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_HCI_RES_EN_V1 BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO8_INT_EN BIT(20)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_HCI_RESET_EN_V1 BIT(20)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO7_INT_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_32K_LEAVE_SETTING_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO6_INT_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_32K_ENTER_SETTING_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO5_INT_EN BIT(17)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_SIE_LPM_RSM_EN_V1 BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO4_INT_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_SIE_LPM_ACT_EN_V1 BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO3_INT_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIOF_INT_EN_V1 BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO2_INT_EN BIT(14)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIOE_INT_EN_V1 BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO1_INT_EN BIT(13)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIOD_INT_EN_V1 BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO0_INT_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIOC_INT_EN_V1 BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_HCI_SUS_EN BIT(11)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIOB_INT_EN_V1 BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_HCI_RES_EN BIT(10)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIOA_INT_EN_V1 BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_HCI_RESET_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO9_INT_EN_V1 BIT(9)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_AXI_EXCEPT_FINT_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_USB_SCSI_CMD_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO8_INT_EN_V1 BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_BTON_STS_UPDATE_MSK_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO7_INT_EN_V1 BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_ACT2RECOVERY_INT_EN_V1 BIT(6)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO6_INT_EN_V1 BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_TRPC_TO_INT_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO5_INT_EN_V1 BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_RPC_O_T_INT_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_HCI_TXDMA_REQ_HIMR BIT(4)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO4_INT_EN_V1 BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_32K_LEAVE_SETTING_MAK BIT(3)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO3_INT_EN_V1 BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_32K_ENTER_SETTING_MAK BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO2_INT_EN_V1 BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_USB_LPMRSM_MSK BIT(1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO1_INT_EN_V1 BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_USB_LPMINT_MSK BIT(0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSIMR\t\t\t\t(Offset 0x0050) */\n\n#define BIT_FS_GPIO0_INT_EN_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_PDNINT BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_SPS_OCP_INT BIT(29)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_SW_SPS_OCP_INT BIT(29)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_PWMERR_INT BIT(28)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_PWM_HW_ERR BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIOF_INT BIT(27)\n#define BIT_FS_GPIOE_INT BIT(26)\n#define BIT_FS_GPIOD_INT BIT(25)\n#define BIT_FS_GPIOC_INT BIT(24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_ACT2RECOVERY_INT BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIOB_INT BIT(23)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_PCIE_GEN12_SWITCH BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIOA_INT BIT(22)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_HCI_SUS_V1 BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO9_INT BIT(21)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_HCI_RES_V1 BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO8_INT BIT(20)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_HCI_RESET_V1 BIT(20)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO7_INT BIT(19)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_32K_LEAVE_SETTING BIT(19)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO6_INT BIT(18)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_32K_ENTER_SETTING BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO5_INT BIT(17)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_SIE_LPM_RSM_V1 BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO4_INT BIT(16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_SIE_LPM_ACT_V1 BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO3_INT BIT(15)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIOF_INT_V1 BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO2_INT BIT(14)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIOE_INT_V1 BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO1_INT BIT(13)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIOD_INT_V1 BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO0_INT BIT(12)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIOC_INT_V1 BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_HCI_SUS_INT BIT(11)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIOB_INT_V1 BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_HCI_RES_INT BIT(10)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIOA_INT_V1 BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_HCI_RESET_INT BIT(9)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO9_INT_V1 BIT(9)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_AXI_EXCEPT_FINT BIT(8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_USB_SCSI_CMD_INT BIT(8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO8_INT_V1 BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_BTON_STS_UPDATE_INT BIT(7)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO7_INT_V1 BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_ACT2RECOVERY_INT_V1 BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_ACT2RECOVERY BIT(6)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO6_INT_V1 BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_TRPC_TO_INT_INT BIT(5)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO5_INT_V1 BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_RPC_O_T_INT_INT BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_HCI_TXDMA_REQ_HISR BIT(4)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO4_INT_V1 BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_32K_LEAVE_SETTING_INT BIT(3)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO3_INT_V1 BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_32K_ENTER_SETTING_INT BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO2_INT_V1 BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_USB_LPMRSM_INT BIT(1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO1_INT_V1 BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_USB_LPMINT_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FSISR\t\t\t\t(Offset 0x0054) */\n\n#define BIT_FS_GPIO0_INT_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HSIMR\t\t\t\t(Offset 0x0058) */\n\n#define BIT_GPIOF_INT_EN BIT(31)\n#define BIT_GPIOE_INT_EN BIT(30)\n#define BIT_GPIOD_INT_EN BIT(29)\n#define BIT_GPIOC_INT_EN BIT(28)\n#define BIT_GPIOB_INT_EN BIT(27)\n#define BIT_GPIOA_INT_EN BIT(26)\n#define BIT_GPIO9_INT_EN BIT(25)\n#define BIT_GPIO8_INT_EN BIT(24)\n#define BIT_GPIO7_INT_EN BIT(23)\n#define BIT_GPIO6_INT_EN BIT(22)\n#define BIT_GPIO5_INT_EN BIT(21)\n#define BIT_GPIO4_INT_EN BIT(20)\n#define BIT_GPIO3_INT_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HSIMR\t\t\t\t(Offset 0x0058) */\n\n#define BIT_GPIO2_INT_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HSIMR\t\t\t\t(Offset 0x0058) */\n\n#define BIT_GPIO2_INT_EN_V1 BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HSIMR\t\t\t\t(Offset 0x0058) */\n\n#define BIT_GPIO1_INT_EN BIT(17)\n#define BIT_GPIO0_INT_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HSIMR\t\t\t\t(Offset 0x0058) */\n\n#define BIT_AXI_EXCEPT_HINT_EN BIT(9)\n#define BIT_PDNINT_EN_V2 BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HSIMR\t\t\t\t(Offset 0x0058) */\n\n#define BIT_PDNINT_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HSIMR\t\t\t\t(Offset 0x0058) */\n\n#define BIT_PDNINT_EN_V1 BIT(7)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HSIMR\t\t\t\t(Offset 0x0058) */\n\n#define BIT_PDN_INT_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HSIMR\t\t\t\t(Offset 0x0058) */\n\n#define BIT_RON_INT_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HSIMR\t\t\t\t(Offset 0x0058) */\n\n#define BIT_RON_INT_EN_V1 BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HSIMR\t\t\t\t(Offset 0x0058) */\n\n#define BIT_SPS_OCP_INT_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HSIMR\t\t\t\t(Offset 0x0058) */\n\n#define BIT_SPS_OCP_INT_EN_V1 BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HSIMR\t\t\t\t(Offset 0x0058) */\n\n#define BIT_GPIO15_0_INT_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HSIMR\t\t\t\t(Offset 0x0058) */\n\n#define BIT_GPIO15_0_INT_EN_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HSISR\t\t\t\t(Offset 0x005C) */\n\n#define BIT_GPIOF_INT BIT(31)\n#define BIT_GPIOE_INT BIT(30)\n#define BIT_GPIOD_INT BIT(29)\n#define BIT_GPIOC_INT BIT(28)\n#define BIT_GPIOB_INT BIT(27)\n#define BIT_GPIOA_INT BIT(26)\n#define BIT_GPIO9_INT BIT(25)\n#define BIT_GPIO8_INT BIT(24)\n#define BIT_GPIO7_INT BIT(23)\n#define BIT_GPIO6_INT BIT(22)\n#define BIT_GPIO5_INT BIT(21)\n#define BIT_GPIO4_INT BIT(20)\n#define BIT_GPIO3_INT BIT(19)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HSISR\t\t\t\t(Offset 0x005C) */\n\n#define BIT_GPIO2_INT BIT(18)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HSISR\t\t\t\t(Offset 0x005C) */\n\n#define BIT_GPIO2_INT_V1 BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HSISR\t\t\t\t(Offset 0x005C) */\n\n#define BIT_GPIO1_INT BIT(17)\n#define BIT_GPIO0_INT BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HSISR\t\t\t\t(Offset 0x005C) */\n\n#define BIT_AXI_EXCEPT_HINT BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HSISR\t\t\t\t(Offset 0x005C) */\n\n#define BIT_PDNINT BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HSISR\t\t\t\t(Offset 0x005C) */\n\n#define BIT_PDNINT_V1 BIT(7)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HSISR\t\t\t\t(Offset 0x005C) */\n\n#define BIT_PDN_INT BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HSISR\t\t\t\t(Offset 0x005C) */\n\n#define BIT_RON_INT BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HSISR\t\t\t\t(Offset 0x005C) */\n\n#define BIT_RON_INT_V1 BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HSISR\t\t\t\t(Offset 0x005C) */\n\n#define BIT_SPS_OCP_INT BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HSISR\t\t\t\t(Offset 0x005C) */\n\n#define BIT_SPS_OCP_INT_V1 BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HSISR\t\t\t\t(Offset 0x005C) */\n\n#define BIT_GPIO15_0_INT BIT(0)\n#define BIT_MCUFWDL_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HSISR\t\t\t\t(Offset 0x005C) */\n\n#define BIT_GPIO15_0_INT_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_EXT_CTRL\t\t\t(Offset 0x0060) */\n\n#define BIT_SHIFT_GPIO_MOD_15_TO_8 24\n#define BIT_MASK_GPIO_MOD_15_TO_8 0xff\n#define BIT_GPIO_MOD_15_TO_8(x)                                                \\\n\t(((x) & BIT_MASK_GPIO_MOD_15_TO_8) << BIT_SHIFT_GPIO_MOD_15_TO_8)\n#define BITS_GPIO_MOD_15_TO_8                                                  \\\n\t(BIT_MASK_GPIO_MOD_15_TO_8 << BIT_SHIFT_GPIO_MOD_15_TO_8)\n#define BIT_CLEAR_GPIO_MOD_15_TO_8(x) ((x) & (~BITS_GPIO_MOD_15_TO_8))\n#define BIT_GET_GPIO_MOD_15_TO_8(x)                                            \\\n\t(((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8) & BIT_MASK_GPIO_MOD_15_TO_8)\n#define BIT_SET_GPIO_MOD_15_TO_8(x, v)                                         \\\n\t(BIT_CLEAR_GPIO_MOD_15_TO_8(x) | BIT_GPIO_MOD_15_TO_8(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_EXT_CTRL\t\t\t(Offset 0x0060) */\n\n#define BIT_ROM_DLEN BIT(19)\n\n#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8 16\n#define BIT_MASK_GPIO_IO_SEL_15_TO_8 0xff\n#define BIT_GPIO_IO_SEL_15_TO_8(x)                                             \\\n\t(((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8)\n#define BITS_GPIO_IO_SEL_15_TO_8                                               \\\n\t(BIT_MASK_GPIO_IO_SEL_15_TO_8 << BIT_SHIFT_GPIO_IO_SEL_15_TO_8)\n#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8(x) ((x) & (~BITS_GPIO_IO_SEL_15_TO_8))\n#define BIT_GET_GPIO_IO_SEL_15_TO_8(x)                                         \\\n\t(((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8) & BIT_MASK_GPIO_IO_SEL_15_TO_8)\n#define BIT_SET_GPIO_IO_SEL_15_TO_8(x, v)                                      \\\n\t(BIT_CLEAR_GPIO_IO_SEL_15_TO_8(x) | BIT_GPIO_IO_SEL_15_TO_8(v))\n\n#define BIT_SHIFT_ROM_PGE 16\n#define BIT_MASK_ROM_PGE 0x7\n#define BIT_ROM_PGE(x) (((x) & BIT_MASK_ROM_PGE) << BIT_SHIFT_ROM_PGE)\n#define BITS_ROM_PGE (BIT_MASK_ROM_PGE << BIT_SHIFT_ROM_PGE)\n#define BIT_CLEAR_ROM_PGE(x) ((x) & (~BITS_ROM_PGE))\n#define BIT_GET_ROM_PGE(x) (((x) >> BIT_SHIFT_ROM_PGE) & BIT_MASK_ROM_PGE)\n#define BIT_SET_ROM_PGE(x, v) (BIT_CLEAR_ROM_PGE(x) | BIT_ROM_PGE(v))\n\n#define BIT_SHIFT_GPIO_OUT_15_TO_8 8\n#define BIT_MASK_GPIO_OUT_15_TO_8 0xff\n#define BIT_GPIO_OUT_15_TO_8(x)                                                \\\n\t(((x) & BIT_MASK_GPIO_OUT_15_TO_8) << BIT_SHIFT_GPIO_OUT_15_TO_8)\n#define BITS_GPIO_OUT_15_TO_8                                                  \\\n\t(BIT_MASK_GPIO_OUT_15_TO_8 << BIT_SHIFT_GPIO_OUT_15_TO_8)\n#define BIT_CLEAR_GPIO_OUT_15_TO_8(x) ((x) & (~BITS_GPIO_OUT_15_TO_8))\n#define BIT_GET_GPIO_OUT_15_TO_8(x)                                            \\\n\t(((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8) & BIT_MASK_GPIO_OUT_15_TO_8)\n#define BIT_SET_GPIO_OUT_15_TO_8(x, v)                                         \\\n\t(BIT_CLEAR_GPIO_OUT_15_TO_8(x) | BIT_GPIO_OUT_15_TO_8(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_EXT_CTRL\t\t\t(Offset 0x0060) */\n\n#define BIT_SHIFT_GPIO_IN_15_TO_8 0\n#define BIT_MASK_GPIO_IN_15_TO_8 0xff\n#define BIT_GPIO_IN_15_TO_8(x)                                                 \\\n\t(((x) & BIT_MASK_GPIO_IN_15_TO_8) << BIT_SHIFT_GPIO_IN_15_TO_8)\n#define BITS_GPIO_IN_15_TO_8                                                   \\\n\t(BIT_MASK_GPIO_IN_15_TO_8 << BIT_SHIFT_GPIO_IN_15_TO_8)\n#define BIT_CLEAR_GPIO_IN_15_TO_8(x) ((x) & (~BITS_GPIO_IN_15_TO_8))\n#define BIT_GET_GPIO_IN_15_TO_8(x)                                             \\\n\t(((x) >> BIT_SHIFT_GPIO_IN_15_TO_8) & BIT_MASK_GPIO_IN_15_TO_8)\n#define BIT_SET_GPIO_IN_15_TO_8(x, v)                                          \\\n\t(BIT_CLEAR_GPIO_IN_15_TO_8(x) | BIT_GPIO_IN_15_TO_8(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_H2C\t\t\t\t(Offset 0x10250060) */\n\n#define BIT_SHIFT_SDIO_H2C_MSG 0\n#define BIT_MASK_SDIO_H2C_MSG 0xffffffffL\n#define BIT_SDIO_H2C_MSG(x)                                                    \\\n\t(((x) & BIT_MASK_SDIO_H2C_MSG) << BIT_SHIFT_SDIO_H2C_MSG)\n#define BITS_SDIO_H2C_MSG (BIT_MASK_SDIO_H2C_MSG << BIT_SHIFT_SDIO_H2C_MSG)\n#define BIT_CLEAR_SDIO_H2C_MSG(x) ((x) & (~BITS_SDIO_H2C_MSG))\n#define BIT_GET_SDIO_H2C_MSG(x)                                                \\\n\t(((x) >> BIT_SHIFT_SDIO_H2C_MSG) & BIT_MASK_SDIO_H2C_MSG)\n#define BIT_SET_SDIO_H2C_MSG(x, v)                                             \\\n\t(BIT_CLEAR_SDIO_H2C_MSG(x) | BIT_SDIO_H2C_MSG(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_DATA_CPU_JTAG BIT(30)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_PAPE_WLBT_SEL BIT(29)\n#define BIT_LNAON_WLBT_SEL BIT(28)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_BDEN BIT(28)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_BT_BQB_GPIO_SEL BIT(27)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_BTGP_GPG3_FEN BIT(26)\n#define BIT_BTGP_GPG2_FEN BIT(25)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_BTGP_JTAG_EN BIT(24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_BB2PP_ISO BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_XTAL_CLK_EXTARNAL_EN BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_BTBRI_UART_EN BIT(22)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_BTGP_UART0_EN BIT(22)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_BTGP_UART1_EN BIT(21)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_BTCOEX_PU BIT(21)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_BTGP_SPI_EN BIT(20)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_EEPROM_SEL_PD BIT(20)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_BTGP_GPIO_E2 BIT(19)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_TST_MOD_PD BIT(19)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_BTGP_GPIO_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_BOOT_FLUSH_PD BIT(18)\n#define BIT_USB_XTAL_SEL1_PD BIT(17)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SHIFT_BTGP_GPIO_SL 16\n#define BIT_MASK_BTGP_GPIO_SL 0x3\n#define BIT_BTGP_GPIO_SL(x)                                                    \\\n\t(((x) & BIT_MASK_BTGP_GPIO_SL) << BIT_SHIFT_BTGP_GPIO_SL)\n#define BITS_BTGP_GPIO_SL (BIT_MASK_BTGP_GPIO_SL << BIT_SHIFT_BTGP_GPIO_SL)\n#define BIT_CLEAR_BTGP_GPIO_SL(x) ((x) & (~BITS_BTGP_GPIO_SL))\n#define BIT_GET_BTGP_GPIO_SL(x)                                                \\\n\t(((x) >> BIT_SHIFT_BTGP_GPIO_SL) & BIT_MASK_BTGP_GPIO_SL)\n#define BIT_SET_BTGP_GPIO_SL(x, v)                                             \\\n\t(BIT_CLEAR_BTGP_GPIO_SL(x) | BIT_BTGP_GPIO_SL(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_USB_XTAL_SEL0_PD BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_HST_WKE_DEV_SL BIT(15)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_BTSUSB_PL BIT(15)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_WL_JTAG BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_PAD_SDIO_SR BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_GPIO14_OUTPUT_PL BIT(13)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_DEVWHOST_POLARITY BIT(13)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_GPIO15_OUTPUT_PL BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_HOST_WAKE_PAD_PULL_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_HOST_WAKE_DEV_PLL_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_HOST_WAKE_PAD_SL BIT(11)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_TRSW_3 BIT(11)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_HOST_WAKE_DEV_POLARITY BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_PAD_TRSW_SR BIT(10)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_PAD_LNAON_SR BIT(10)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_TRSW_2 BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_PAD_TRSW_E2 BIT(9)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_PAD_LNAON_E2 BIT(9)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_TRSW_1 BIT(9)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_A_ANTSEL_SR BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_TRSW_P_SEL_DATA BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_LNAON_G_SEL_DATA BIT(8)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_TRSW_0 BIT(8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_A_ANTSEL_E2 BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_TRSW_N_SEL_DATA BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_LNAON_A_SEL_DATA BIT(7)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_PAPE_3 BIT(7)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_D_PAPE_2G_SR BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_PAD_PAPE_SR BIT(6)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_PAPE_2 BIT(6)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_D_PAPE_5G_SR BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_PAD_PAPE_E2 BIT(5)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_PAPE_1 BIT(5)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_D_TRSW_SR BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_PAPE_1_SEL_DATA BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_PAPE_G_SEL_DATA BIT(4)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_PAPE_0 BIT(4)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_D_TRSWB_SR BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_PAPE_0_SEL_DATA BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_PAPE_A_SEL_DATA BIT(3)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_ANTSEL_3 BIT(3)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_D_PAPE_2G_E2 BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_ANTSEL_2_SEL_DATA BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_PAD_DPDT_SR BIT(2)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_ANTSEL_2 BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_D_PAPE_5G_E2 BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_ANTSEL_N_SEL_DATA BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_PAD_DPDT_PAD_E2 BIT(1)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_ANTSEL_1 BIT(1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_D_TRSW_E2 BIT(1)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_PAD_DPDT_E2 BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_ANTSEL_P_SEL_DATA BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_DPDT_SEL_DATA BIT(0)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_SW_ANTSEL_0 BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_C2H\t\t\t\t(Offset 0x10250064) */\n\n#define BIT_SHIFT_SDIO_C2H_MSG 0\n#define BIT_MASK_SDIO_C2H_MSG 0xffffffffL\n#define BIT_SDIO_C2H_MSG(x)                                                    \\\n\t(((x) & BIT_MASK_SDIO_C2H_MSG) << BIT_SHIFT_SDIO_C2H_MSG)\n#define BITS_SDIO_C2H_MSG (BIT_MASK_SDIO_C2H_MSG << BIT_SHIFT_SDIO_C2H_MSG)\n#define BIT_CLEAR_SDIO_C2H_MSG(x) ((x) & (~BITS_SDIO_C2H_MSG))\n#define BIT_GET_SDIO_C2H_MSG(x)                                                \\\n\t(((x) >> BIT_SHIFT_SDIO_C2H_MSG) & BIT_MASK_SDIO_C2H_MSG)\n#define BIT_SET_SDIO_C2H_MSG(x, v)                                             \\\n\t(BIT_CLEAR_SDIO_C2H_MSG(x) | BIT_SDIO_C2H_MSG(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL1\t\t\t\t(Offset 0x0064) */\n\n#define BIT_D_TRSWB_E2 BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_ISO_BD2PP BIT(31)\n#define BIT_LDOV12B_EN BIT(30)\n#define BIT_CKEN_BTGPS BIT(29)\n#define BIT_FEN_BTGPS BIT(28)\n#define BIT_BTCPU_BOOTSEL BIT(27)\n#define BIT_SPI_SPEEDUP BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BT_LPS_EN BIT(25)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BT_LDO_MODE BIT(25)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BT_SUS BIT(25)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_DEVWAKE_PAD_TYPE_SEL BIT(24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_CLKREQ_PAD_PL BIT(23)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_CLKREQ_PAD_TYPE_SEL BIT(23)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_CKSL_BZSLP BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_EN_CPL_TIMEOUT_PS BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BT_WAKE_HST_EN BIT(22)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BTGP_WAKE_HST_EN BIT(22)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_ISO_BTPON2PP BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_REG_TXDMA_FAIL_PS BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_WAKE_BT_EN BIT(21)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BTGP_WAKE_BT_EN BIT(21)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BTCOEX_CMD BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_EN_BT BIT(20)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BTGP_EN BIT(20)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BT_UART_INTF BIT(20)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_EN_HWENTR_L1 BIT(19)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BT_SUSN_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BTGP_SUS_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BT_HWROF_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_S3_RF_HW_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_EN_ADV_CLKGATE BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BT_FUNC_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_S2_RF_HW_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BT_HWPDN_SL BIT(17)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_S1_RF_HW_EN BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BT_DISN_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BT_HWPDEN BIT(16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_S0_RF_HW_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BT_PDN_PULL_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_WL_PDN_PULL_EN BIT(14)\n#define BIT_EXTERNAL_REQUEST_PL BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_GPIO0_2_3_PULL_LOW_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_ISO_BA2PP BIT(11)\n#define BIT_BT_AFE_LDO_EN BIT(10)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_PDN_PIN_SEL BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_GPIO11_PULL_LOW_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BT_AFE_PLL_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_GPIO4_PULL_LOW_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BT_DIG_CLK_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BT_WAKE_HST_SL BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BT_WAKE_HST_PL BIT(7)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_ASSERT_SPS_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_UART_BRIDGE BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_WAKE_BT_SL BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_WAKE_BT_PL BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_WLAN_32K_SEL BIT(6)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_MASK_CHIPEN BIT(6)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_OSC32K_CTRL_SEL BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_WL_DRV_EXIST_IDX BIT(5)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_ASSERT_RF_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_DOP_EHPAD BIT(4)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_BIT_DOP_EHPAD BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_WL_HWROF_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_SDIO_PAD_SHUTDOWNB BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_WL_FUNC_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_SDIO_CLK_SMT BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WL_BT_PWR_CTRL\t\t\t(Offset 0x0068) */\n\n#define BIT_WL_HWPDN_SL BIT(1)\n#define BIT_WL_HWPDN_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SDM_DEBUG\t\t\t\t(Offset 0x006C) */\n\n#define BIT_SHIFT_F0N 23\n#define BIT_MASK_F0N 0x7\n#define BIT_F0N(x) (((x) & BIT_MASK_F0N) << BIT_SHIFT_F0N)\n#define BITS_F0N (BIT_MASK_F0N << BIT_SHIFT_F0N)\n#define BIT_CLEAR_F0N(x) ((x) & (~BITS_F0N))\n#define BIT_GET_F0N(x) (((x) >> BIT_SHIFT_F0N) & BIT_MASK_F0N)\n#define BIT_SET_F0N(x, v) (BIT_CLEAR_F0N(x) | BIT_F0N(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SDM_DEBUG\t\t\t\t(Offset 0x006C) */\n\n#define BIT_BT_WAKE_DEV_EN_V1 BIT(19)\n#define BIT_BT_WAKE_HST_EN_V1 BIT(18)\n#define BIT_BT_WAKE_HST_PL_V1 BIT(17)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GSSR\t\t\t\t(Offset 0x006C) */\n\n#define BIT_SHIFT_GPIO_15_TO_0_VAL 16\n#define BIT_MASK_GPIO_15_TO_0_VAL 0xffff\n#define BIT_GPIO_15_TO_0_VAL(x)                                                \\\n\t(((x) & BIT_MASK_GPIO_15_TO_0_VAL) << BIT_SHIFT_GPIO_15_TO_0_VAL)\n#define BITS_GPIO_15_TO_0_VAL                                                  \\\n\t(BIT_MASK_GPIO_15_TO_0_VAL << BIT_SHIFT_GPIO_15_TO_0_VAL)\n#define BIT_CLEAR_GPIO_15_TO_0_VAL(x) ((x) & (~BITS_GPIO_15_TO_0_VAL))\n#define BIT_GET_GPIO_15_TO_0_VAL(x)                                            \\\n\t(((x) >> BIT_SHIFT_GPIO_15_TO_0_VAL) & BIT_MASK_GPIO_15_TO_0_VAL)\n#define BIT_SET_GPIO_15_TO_0_VAL(x, v)                                         \\\n\t(BIT_CLEAR_GPIO_15_TO_0_VAL(x) | BIT_GPIO_15_TO_0_VAL(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SDM_DEBUG\t\t\t\t(Offset 0x006C) */\n\n#define BIT_BT_CLKREQ_EN_V1 BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SDM_DEBUG\t\t\t\t(Offset 0x006C) */\n\n#define BIT_SHIFT_F0F 10\n#define BIT_MASK_F0F 0x1fff\n#define BIT_F0F(x) (((x) & BIT_MASK_F0F) << BIT_SHIFT_F0F)\n#define BITS_F0F (BIT_MASK_F0F << BIT_SHIFT_F0F)\n#define BIT_CLEAR_F0F(x) ((x) & (~BITS_F0F))\n#define BIT_GET_F0F(x) (((x) >> BIT_SHIFT_F0F) & BIT_MASK_F0F)\n#define BIT_SET_F0F(x, v) (BIT_CLEAR_F0F(x) | BIT_F0F(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDM_DEBUG\t\t\t\t(Offset 0x006C) */\n\n#define BIT_GPIO_IE_V18 BIT(10)\n#define BIT_PCIE_IE_V18 BIT(9)\n#define BIT_UART_IE_V18 BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SDM_DEBUG\t\t\t\t(Offset 0x006C) */\n\n#define BIT_SHIFT_DIVN 4\n#define BIT_MASK_DIVN 0x3f\n#define BIT_DIVN(x) (((x) & BIT_MASK_DIVN) << BIT_SHIFT_DIVN)\n#define BITS_DIVN (BIT_MASK_DIVN << BIT_SHIFT_DIVN)\n#define BIT_CLEAR_DIVN(x) ((x) & (~BITS_DIVN))\n#define BIT_GET_DIVN(x) (((x) >> BIT_SHIFT_DIVN) & BIT_MASK_DIVN)\n#define BIT_SET_DIVN(x, v) (BIT_CLEAR_DIVN(x) | BIT_DIVN(v))\n\n#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM 0\n#define BIT_MASK_BB_DBG_SEL_AFE_SDM 0xf\n#define BIT_BB_DBG_SEL_AFE_SDM(x)                                              \\\n\t(((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM)\n#define BITS_BB_DBG_SEL_AFE_SDM                                                \\\n\t(BIT_MASK_BB_DBG_SEL_AFE_SDM << BIT_SHIFT_BB_DBG_SEL_AFE_SDM)\n#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM(x) ((x) & (~BITS_BB_DBG_SEL_AFE_SDM))\n#define BIT_GET_BB_DBG_SEL_AFE_SDM(x)                                          \\\n\t(((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM) & BIT_MASK_BB_DBG_SEL_AFE_SDM)\n#define BIT_SET_BB_DBG_SEL_AFE_SDM(x, v)                                       \\\n\t(BIT_CLEAR_BB_DBG_SEL_AFE_SDM(x) | BIT_BB_DBG_SEL_AFE_SDM(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDM_DEBUG\t\t\t\t(Offset 0x006C) */\n\n#define BIT_SHIFT_WLCLK_PHASE 0\n#define BIT_MASK_WLCLK_PHASE 0x1f\n#define BIT_WLCLK_PHASE(x)                                                     \\\n\t(((x) & BIT_MASK_WLCLK_PHASE) << BIT_SHIFT_WLCLK_PHASE)\n#define BITS_WLCLK_PHASE (BIT_MASK_WLCLK_PHASE << BIT_SHIFT_WLCLK_PHASE)\n#define BIT_CLEAR_WLCLK_PHASE(x) ((x) & (~BITS_WLCLK_PHASE))\n#define BIT_GET_WLCLK_PHASE(x)                                                 \\\n\t(((x) >> BIT_SHIFT_WLCLK_PHASE) & BIT_MASK_WLCLK_PHASE)\n#define BIT_SET_WLCLK_PHASE(x, v)                                              \\\n\t(BIT_CLEAR_WLCLK_PHASE(x) | BIT_WLCLK_PHASE(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_GSSR\t\t\t\t(Offset 0x006C) */\n\n#define BIT_SHIFT_GPIO_15_TO_0_EN 0\n#define BIT_MASK_GPIO_15_TO_0_EN 0xffff\n#define BIT_GPIO_15_TO_0_EN(x)                                                 \\\n\t(((x) & BIT_MASK_GPIO_15_TO_0_EN) << BIT_SHIFT_GPIO_15_TO_0_EN)\n#define BITS_GPIO_15_TO_0_EN                                                   \\\n\t(BIT_MASK_GPIO_15_TO_0_EN << BIT_SHIFT_GPIO_15_TO_0_EN)\n#define BIT_CLEAR_GPIO_15_TO_0_EN(x) ((x) & (~BITS_GPIO_15_TO_0_EN))\n#define BIT_GET_GPIO_15_TO_0_EN(x)                                             \\\n\t(((x) >> BIT_SHIFT_GPIO_15_TO_0_EN) & BIT_MASK_GPIO_15_TO_0_EN)\n#define BIT_SET_GPIO_15_TO_0_EN(x, v)                                          \\\n\t(BIT_CLEAR_GPIO_15_TO_0_EN(x) | BIT_GPIO_15_TO_0_EN(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_FORCE_RST_PCIE_APHY BIT(30)\n#define BIT_FORCE_OFF_EPC BIT(29)\n#define BIT_PTA_3W_MODE BIT(28)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_BBRSTB_STANDBY_V1 BIT(28)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_DBG_GNT_WL_BT BIT(27)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_AFE_PORT3_ISO BIT(27)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_LTE_MUX_CTRL_PATH BIT(26)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_AFE_PORT2_ISO BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_LTE_COEX_EN BIT(25)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_LTE_COEX_UART BIT(25)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_AFE_PORT1_ISO BIT(25)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_3W_LTE_GPIO_EN BIT(24)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_3W_LTE_WL_GPIO BIT(24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_AFE_PORT0_ISO BIT(24)\n#define BIT_USB_PWR_OFF_SEL BIT(23)\n#define BIT_USB_HOST_PWR_OFF_EN_V1 BIT(22)\n#define BIT_SYM_LPS_BLOCK_EN_V1 BIT(21)\n#define BIT_USB_LPM_ACT_EN_V1 BIT(20)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_SDIO_INT_POLARITY BIT(19)\n#define BIT_SDIO_INT BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_SDIO_OFF_EN BIT(17)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_SDIO_OFF_EN_V1 BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_SDIO_ON_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_SDIO_ON_EN_V1 BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_PCIE_FORCE_PWR_NGAT BIT(13)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_DIS_U3MB_INU2 BIT(13)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_PCIE_CALIB_EN_V1 BIT(12)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_USB3_MDIO_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_PAGE3_AUXCLK_GATE BIT(11)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_USB3_BG_EN BIT(11)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_PCIE_WAIT_TIMEOUT_EVENT BIT(10)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_USB3_MB_EN BIT(10)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_PCIE_WAIT_TIME BIT(9)\n#define BIT_MPCIE_REFCLK_XTAL_SEL BIT(8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_SHIFT_USB3_CK_MD 8\n#define BIT_MASK_USB3_CK_MD 0x3\n#define BIT_USB3_CK_MD(x) (((x) & BIT_MASK_USB3_CK_MD) << BIT_SHIFT_USB3_CK_MD)\n#define BITS_USB3_CK_MD (BIT_MASK_USB3_CK_MD << BIT_SHIFT_USB3_CK_MD)\n#define BIT_CLEAR_USB3_CK_MD(x) ((x) & (~BITS_USB3_CK_MD))\n#define BIT_GET_USB3_CK_MD(x)                                                  \\\n\t(((x) >> BIT_SHIFT_USB3_CK_MD) & BIT_MASK_USB3_CK_MD)\n#define BIT_SET_USB3_CK_MD(x, v) (BIT_CLEAR_USB3_CK_MD(x) | BIT_USB3_CK_MD(v))\n\n#define BIT_USB3_CKBUF BIT(7)\n#define BIT_USB3_IBX_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_BT_CLKREQ_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_BT_CTRL_USB_PWR_BACKDOOR BIT(5)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_U3_MB_MASK BIT(5)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_USB_D_STATE_HOLD BIT(4)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_U3_BG_MASK BIT(4)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_SHIFT_USB_CKREF_CML_R 4\n#define BIT_MASK_USB_CKREF_CML_R 0x3\n#define BIT_USB_CKREF_CML_R(x)                                                 \\\n\t(((x) & BIT_MASK_USB_CKREF_CML_R) << BIT_SHIFT_USB_CKREF_CML_R)\n#define BITS_USB_CKREF_CML_R                                                   \\\n\t(BIT_MASK_USB_CKREF_CML_R << BIT_SHIFT_USB_CKREF_CML_R)\n#define BIT_CLEAR_USB_CKREF_CML_R(x) ((x) & (~BITS_USB_CKREF_CML_R))\n#define BIT_GET_USB_CKREF_CML_R(x)                                             \\\n\t(((x) >> BIT_SHIFT_USB_CKREF_CML_R) & BIT_MASK_USB_CKREF_CML_R)\n#define BIT_SET_USB_CKREF_CML_R(x, v)                                          \\\n\t(BIT_CLEAR_USB_CKREF_CML_R(x) | BIT_USB_CKREF_CML_R(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_REG_FORCE_DP BIT(3)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_DIS_USB3_MB_POLLING BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_BTGP_CLKREQ_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_REG_DP_MODE BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_PDN_MASK BIT(2)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_SHIFT_USB_CKREF_D2S_I 2\n#define BIT_MASK_USB_CKREF_D2S_I 0x3\n#define BIT_USB_CKREF_D2S_I(x)                                                 \\\n\t(((x) & BIT_MASK_USB_CKREF_D2S_I) << BIT_SHIFT_USB_CKREF_D2S_I)\n#define BITS_USB_CKREF_D2S_I                                                   \\\n\t(BIT_MASK_USB_CKREF_D2S_I << BIT_SHIFT_USB_CKREF_D2S_I)\n#define BIT_CLEAR_USB_CKREF_D2S_I(x) ((x) & (~BITS_USB_CKREF_D2S_I))\n#define BIT_GET_USB_CKREF_D2S_I(x)                                             \\\n\t(((x) >> BIT_SHIFT_USB_CKREF_D2S_I) & BIT_MASK_USB_CKREF_D2S_I)\n#define BIT_SET_USB_CKREF_D2S_I(x, v)                                          \\\n\t(BIT_CLEAR_USB_CKREF_D2S_I(x) | BIT_USB_CKREF_D2S_I(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_USB_INSTALL_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_RES_USB_MASS_STORAGE_DESC BIT(1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_NO_PDN_CHIPOFF BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_USB_BT_CLKSEL BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_USB_WAIT_TIME BIT(0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CLKR\t\t\t\t(Offset 0x0070) */\n\n#define BIT_PDN_HCOUNT BIT(0)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_SDIO_CTRL\t\t\t(Offset 0x0070) */\n\n#define BIT_SHIFT_SI_AUTHORIZATION 0\n#define BIT_MASK_SI_AUTHORIZATION 0xff\n#define BIT_SI_AUTHORIZATION(x)                                                \\\n\t(((x) & BIT_MASK_SI_AUTHORIZATION) << BIT_SHIFT_SI_AUTHORIZATION)\n#define BITS_SI_AUTHORIZATION                                                  \\\n\t(BIT_MASK_SI_AUTHORIZATION << BIT_SHIFT_SI_AUTHORIZATION)\n#define BIT_CLEAR_SI_AUTHORIZATION(x) ((x) & (~BITS_SI_AUTHORIZATION))\n#define BIT_GET_SI_AUTHORIZATION(x)                                            \\\n\t(((x) >> BIT_SHIFT_SI_AUTHORIZATION) & BIT_MASK_SI_AUTHORIZATION)\n#define BIT_SET_SI_AUTHORIZATION(x, v)                                         \\\n\t(BIT_CLEAR_SI_AUTHORIZATION(x) | BIT_SI_AUTHORIZATION(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_SHIFT_HCI_RATIO 30\n#define BIT_MASK_HCI_RATIO 0x3\n#define BIT_HCI_RATIO(x) (((x) & BIT_MASK_HCI_RATIO) << BIT_SHIFT_HCI_RATIO)\n#define BITS_HCI_RATIO (BIT_MASK_HCI_RATIO << BIT_SHIFT_HCI_RATIO)\n#define BIT_CLEAR_HCI_RATIO(x) ((x) & (~BITS_HCI_RATIO))\n#define BIT_GET_HCI_RATIO(x) (((x) >> BIT_SHIFT_HCI_RATIO) & BIT_MASK_HCI_RATIO)\n#define BIT_SET_HCI_RATIO(x, v) (BIT_CLEAR_HCI_RATIO(x) | BIT_HCI_RATIO(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_SHIFT_TSFT_SEL 29\n#define BIT_MASK_TSFT_SEL 0x7\n#define BIT_TSFT_SEL(x) (((x) & BIT_MASK_TSFT_SEL) << BIT_SHIFT_TSFT_SEL)\n#define BITS_TSFT_SEL (BIT_MASK_TSFT_SEL << BIT_SHIFT_TSFT_SEL)\n#define BIT_CLEAR_TSFT_SEL(x) ((x) & (~BITS_TSFT_SEL))\n#define BIT_GET_TSFT_SEL(x) (((x) >> BIT_SHIFT_TSFT_SEL) & BIT_MASK_TSFT_SEL)\n#define BIT_SET_TSFT_SEL(x, v) (BIT_CLEAR_TSFT_SEL(x) | BIT_TSFT_SEL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_SHIFT_WAIT_HPOW_TIME 28\n#define BIT_MASK_WAIT_HPOW_TIME 0x3\n#define BIT_WAIT_HPOW_TIME(x)                                                  \\\n\t(((x) & BIT_MASK_WAIT_HPOW_TIME) << BIT_SHIFT_WAIT_HPOW_TIME)\n#define BITS_WAIT_HPOW_TIME                                                    \\\n\t(BIT_MASK_WAIT_HPOW_TIME << BIT_SHIFT_WAIT_HPOW_TIME)\n#define BIT_CLEAR_WAIT_HPOW_TIME(x) ((x) & (~BITS_WAIT_HPOW_TIME))\n#define BIT_GET_WAIT_HPOW_TIME(x)                                              \\\n\t(((x) >> BIT_SHIFT_WAIT_HPOW_TIME) & BIT_MASK_WAIT_HPOW_TIME)\n#define BIT_SET_WAIT_HPOW_TIME(x, v)                                           \\\n\t(BIT_CLEAR_WAIT_HPOW_TIME(x) | BIT_WAIT_HPOW_TIME(v))\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_SHIFT_XTAL_SEL_0_V1 28\n#define BIT_MASK_XTAL_SEL_0_V1 0xf\n#define BIT_XTAL_SEL_0_V1(x)                                                   \\\n\t(((x) & BIT_MASK_XTAL_SEL_0_V1) << BIT_SHIFT_XTAL_SEL_0_V1)\n#define BITS_XTAL_SEL_0_V1 (BIT_MASK_XTAL_SEL_0_V1 << BIT_SHIFT_XTAL_SEL_0_V1)\n#define BIT_CLEAR_XTAL_SEL_0_V1(x) ((x) & (~BITS_XTAL_SEL_0_V1))\n#define BIT_GET_XTAL_SEL_0_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_XTAL_SEL_0_V1) & BIT_MASK_XTAL_SEL_0_V1)\n#define BIT_SET_XTAL_SEL_0_V1(x, v)                                            \\\n\t(BIT_CLEAR_XTAL_SEL_0_V1(x) | BIT_XTAL_SEL_0_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_TSFT_BAND_SEL BIT(28)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_PCIE_HPOW_OPT2 BIT(27)\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_ISO_RFC2RF_3 BIT(27)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_PCIE_HPOW_OPT1 BIT(26)\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_ISO_RFC2RF_2 BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_PCIE_HPOW_OPT0 BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_SHIFT_RPWM 24\n#define BIT_MASK_RPWM 0xff\n#define BIT_RPWM(x) (((x) & BIT_MASK_RPWM) << BIT_SHIFT_RPWM)\n#define BITS_RPWM (BIT_MASK_RPWM << BIT_SHIFT_RPWM)\n#define BIT_CLEAR_RPWM(x) ((x) & (~BITS_RPWM))\n#define BIT_GET_RPWM(x) (((x) >> BIT_SHIFT_RPWM) & BIT_MASK_RPWM)\n#define BIT_SET_RPWM(x, v) (BIT_CLEAR_RPWM(x) | BIT_RPWM(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_PCIE_EPC_ISO BIT(24)\n#define BIT_PCIE_EPC_OPT BIT(23)\n#define BIT_PCIE_SUS_OPT BIT(22)\n#define BIT_PCIE_L1OF_OPT BIT(21)\n#define BIT_PCIE_L1OF_LDOA BIT(20)\n#define BIT_USB_SUS_LDOA BIT(19)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_SDIO_PAD_E5 BIT(18)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_USB_HOST_PWR_OFF_SEL BIT(13)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_R_FORCE_CLK_U3 BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_USB_HOST_PWR_OFF_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_R_USB2_AUTOLOAD BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_SYM_LPS_BLOCK_EN BIT(11)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_FORCE_U2CK BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_USB_LPM_ACT_EN BIT(10)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_FORCE_CLK BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_USB_LPM_NY BIT(9)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_IBX_EN_VALUE BIT(9)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_U2_FORCE BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_USB_SUS_DIS BIT(8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_IB_EN_VALUE BIT(8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_U3_FORCE BIT(8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_EN_LW_PWR BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_SHIFT_SDIO_PAD_E 5\n#define BIT_MASK_SDIO_PAD_E 0x7\n#define BIT_SDIO_PAD_E(x) (((x) & BIT_MASK_SDIO_PAD_E) << BIT_SHIFT_SDIO_PAD_E)\n#define BITS_SDIO_PAD_E (BIT_MASK_SDIO_PAD_E << BIT_SHIFT_SDIO_PAD_E)\n#define BIT_CLEAR_SDIO_PAD_E(x) ((x) & (~BITS_SDIO_PAD_E))\n#define BIT_GET_SDIO_PAD_E(x)                                                  \\\n\t(((x) >> BIT_SHIFT_SDIO_PAD_E) & BIT_MASK_SDIO_PAD_E)\n#define BIT_SET_SDIO_PAD_E(x, v) (BIT_CLEAR_SDIO_PAD_E(x) | BIT_SDIO_PAD_E(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_EN_REGU BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_USB_LPPLL_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_FORCED_IB_EN BIT(4)\n#define BIT_EN_PC BIT(4)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_SDIO_H3L1 BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_PERST_SYNC_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_USB1_1_USB2_0_DECISION BIT(3)\n#define BIT_EN_REGBG BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_ROP_SW15 BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_REG_BG_LPF BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_SHIFT_USB23_SW_MODE 2\n#define BIT_MASK_USB23_SW_MODE 0x3\n#define BIT_USB23_SW_MODE(x)                                                   \\\n\t(((x) & BIT_MASK_USB23_SW_MODE) << BIT_SHIFT_USB23_SW_MODE)\n#define BITS_USB23_SW_MODE (BIT_MASK_USB23_SW_MODE << BIT_SHIFT_USB23_SW_MODE)\n#define BIT_CLEAR_USB23_SW_MODE(x) ((x) & (~BITS_USB23_SW_MODE))\n#define BIT_GET_USB23_SW_MODE(x)                                               \\\n\t(((x) >> BIT_SHIFT_USB23_SW_MODE) & BIT_MASK_USB23_SW_MODE)\n#define BIT_SET_USB23_SW_MODE(x, v)                                            \\\n\t(BIT_CLEAR_USB23_SW_MODE(x) | BIT_USB23_SW_MODE(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_PCI_CKRDY_OPT BIT(1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_PCLK_VLD_SEL BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_PCI_VAUX_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_SHIFT_REG_BG 0\n#define BIT_MASK_REG_BG 0x3\n#define BIT_REG_BG(x) (((x) & BIT_MASK_REG_BG) << BIT_SHIFT_REG_BG)\n#define BITS_REG_BG (BIT_MASK_REG_BG << BIT_SHIFT_REG_BG)\n#define BIT_CLEAR_REG_BG(x) ((x) & (~BITS_REG_BG))\n#define BIT_GET_REG_BG(x) (((x) >> BIT_SHIFT_REG_BG) & BIT_MASK_REG_BG)\n#define BIT_SET_REG_BG(x, v) (BIT_CLEAR_REG_BG(x) | BIT_REG_BG(v))\n\n#define BIT_SHIFT_REG_VADJ 0\n#define BIT_MASK_REG_VADJ 0xf\n#define BIT_REG_VADJ(x) (((x) & BIT_MASK_REG_VADJ) << BIT_SHIFT_REG_VADJ)\n#define BITS_REG_VADJ (BIT_MASK_REG_VADJ << BIT_SHIFT_REG_VADJ)\n#define BIT_CLEAR_REG_VADJ(x) ((x) & (~BITS_REG_VADJ))\n#define BIT_GET_REG_VADJ(x) (((x) >> BIT_SHIFT_REG_VADJ) & BIT_MASK_REG_VADJ)\n#define BIT_SET_REG_VADJ(x, v) (BIT_CLEAR_REG_VADJ(x) | BIT_REG_VADJ(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HCI_OPT_CTRL\t\t\t(Offset 0x0074) */\n\n#define BIT_VAUX_EN BIT(0)\n\n/* 2 REG_AFE_XTAL_CTRL_EXT\t\t\t(Offset 0x0078) */\n\n#define BIT_SDM_ORDER BIT(30)\n#define BIT_XTAL_DRV_RF_LATCH_V1 BIT(29)\n#define BIT_XTAL_VDD_SEL_V1 BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_XTAL_DRV_RF_LATCH BIT(27)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_XTAL_CTRL_EXT\t\t\t(Offset 0x0078) */\n\n#define BIT_XQSEL_RF_AWAKE_V1 BIT(27)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_XTAL_VDD_SEL BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_RF1_SDMRSTB BIT(26)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_XTAL_CTRL_EXT\t\t\t(Offset 0x0078) */\n\n#define BIT_GATED_XTAL_OK0_V1 BIT(26)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_XQSEL_RF BIT(25)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_RF1_RSTB BIT(25)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_XQSEL_RF_AWAKE BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_XQSEL_RF_INITIAL BIT(24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_RF1_EN BIT(24)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_XQSEL_BIT1 BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_REG_VREF_SEL BIT(23)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_DITHER_SDM_BIT3 BIT(23)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_XTAL_CTRL_EXT\t\t\t(Offset 0x0078) */\n\n#define BIT_SHIFT_F0N_2_TO_0 23\n#define BIT_MASK_F0N_2_TO_0 0x7\n#define BIT_F0N_2_TO_0(x) (((x) & BIT_MASK_F0N_2_TO_0) << BIT_SHIFT_F0N_2_TO_0)\n#define BITS_F0N_2_TO_0 (BIT_MASK_F0N_2_TO_0 << BIT_SHIFT_F0N_2_TO_0)\n#define BIT_CLEAR_F0N_2_TO_0(x) ((x) & (~BITS_F0N_2_TO_0))\n#define BIT_GET_F0N_2_TO_0(x)                                                  \\\n\t(((x) >> BIT_SHIFT_F0N_2_TO_0) & BIT_MASK_F0N_2_TO_0)\n#define BIT_SET_F0N_2_TO_0(x, v) (BIT_CLEAR_F0N_2_TO_0(x) | BIT_F0N_2_TO_0(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_REG_LPFEN BIT(22)\n#define BIT_REG_KVCO BIT(21)\n#define BIT_XTAL_DRV_AGPIO_BIT1 BIT(20)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_SHIFT_XTAL_LDO 20\n#define BIT_MASK_XTAL_LDO 0x7\n#define BIT_XTAL_LDO(x) (((x) & BIT_MASK_XTAL_LDO) << BIT_SHIFT_XTAL_LDO)\n#define BITS_XTAL_LDO (BIT_MASK_XTAL_LDO << BIT_SHIFT_XTAL_LDO)\n#define BIT_CLEAR_XTAL_LDO(x) ((x) & (~BITS_XTAL_LDO))\n#define BIT_GET_XTAL_LDO(x) (((x) >> BIT_SHIFT_XTAL_LDO) & BIT_MASK_XTAL_LDO)\n#define BIT_SET_XTAL_LDO(x, v) (BIT_CLEAR_XTAL_LDO(x) | BIT_XTAL_LDO(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_XTAL_DRV_AGPIO_BIT0 BIT(19)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_XTAL_GRF2 BIT(18)\n#define BIT_REG_REF_SEL BIT(17)\n#define BIT_REG_320_SEL BIT(16)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_ADC_CK_SYNC_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_EN_SYM BIT(15)\n\n#define BIT_SHIFT_IOFFSET 10\n#define BIT_MASK_IOFFSET 0x1f\n#define BIT_IOFFSET(x) (((x) & BIT_MASK_IOFFSET) << BIT_SHIFT_IOFFSET)\n#define BITS_IOFFSET (BIT_MASK_IOFFSET << BIT_SHIFT_IOFFSET)\n#define BIT_CLEAR_IOFFSET(x) ((x) & (~BITS_IOFFSET))\n#define BIT_GET_IOFFSET(x) (((x) >> BIT_SHIFT_IOFFSET) & BIT_MASK_IOFFSET)\n#define BIT_SET_IOFFSET(x, v) (BIT_CLEAR_IOFFSET(x) | BIT_IOFFSET(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_RF2_SDMRSTB BIT(10)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_XTAL_CTRL_EXT\t\t\t(Offset 0x0078) */\n\n#define BIT_SHIFT_F0F_12_TO_0 10\n#define BIT_MASK_F0F_12_TO_0 0x1fff\n#define BIT_F0F_12_TO_0(x)                                                     \\\n\t(((x) & BIT_MASK_F0F_12_TO_0) << BIT_SHIFT_F0F_12_TO_0)\n#define BITS_F0F_12_TO_0 (BIT_MASK_F0F_12_TO_0 << BIT_SHIFT_F0F_12_TO_0)\n#define BIT_CLEAR_F0F_12_TO_0(x) ((x) & (~BITS_F0F_12_TO_0))\n#define BIT_GET_F0F_12_TO_0(x)                                                 \\\n\t(((x) >> BIT_SHIFT_F0F_12_TO_0) & BIT_MASK_F0F_12_TO_0)\n#define BIT_SET_F0F_12_TO_0(x, v)                                              \\\n\t(BIT_CLEAR_F0F_12_TO_0(x) | BIT_F0F_12_TO_0(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_RF2_RSTB BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1 8\n#define BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1 0x3\n#define BIT_APLL_FREF_SEL_BIT_2_TO_1(x)                                        \\\n\t(((x) & BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1)                             \\\n\t << BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1)\n#define BITS_APLL_FREF_SEL_BIT_2_TO_1                                          \\\n\t(BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1                                     \\\n\t << BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1)\n#define BIT_CLEAR_APLL_FREF_SEL_BIT_2_TO_1(x)                                  \\\n\t((x) & (~BITS_APLL_FREF_SEL_BIT_2_TO_1))\n#define BIT_GET_APLL_FREF_SEL_BIT_2_TO_1(x)                                    \\\n\t(((x) >> BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1) &                         \\\n\t BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1)\n#define BIT_SET_APLL_FREF_SEL_BIT_2_TO_1(x, v)                                 \\\n\t(BIT_CLEAR_APLL_FREF_SEL_BIT_2_TO_1(x) |                               \\\n\t BIT_APLL_FREF_SEL_BIT_2_TO_1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_RF2_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_APLL_FREF_SEL_BIT3 BIT(7)\n\n#define BIT_SHIFT_APLL_LDO_V12ADJ 5\n#define BIT_MASK_APLL_LDO_V12ADJ 0x3\n#define BIT_APLL_LDO_V12ADJ(x)                                                 \\\n\t(((x) & BIT_MASK_APLL_LDO_V12ADJ) << BIT_SHIFT_APLL_LDO_V12ADJ)\n#define BITS_APLL_LDO_V12ADJ                                                   \\\n\t(BIT_MASK_APLL_LDO_V12ADJ << BIT_SHIFT_APLL_LDO_V12ADJ)\n#define BIT_CLEAR_APLL_LDO_V12ADJ(x) ((x) & (~BITS_APLL_LDO_V12ADJ))\n#define BIT_GET_APLL_LDO_V12ADJ(x)                                             \\\n\t(((x) >> BIT_SHIFT_APLL_LDO_V12ADJ) & BIT_MASK_APLL_LDO_V12ADJ)\n#define BIT_SET_APLL_LDO_V12ADJ(x, v)                                          \\\n\t(BIT_CLEAR_APLL_LDO_V12ADJ(x) | BIT_APLL_LDO_V12ADJ(v))\n\n#define BIT_APLL_160_GATEB BIT(4)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_XTAL_CTRL_EXT\t\t\t(Offset 0x0078) */\n\n#define BIT_SHIFT_DIVN_5_TO_0 4\n#define BIT_MASK_DIVN_5_TO_0 0x3f\n#define BIT_DIVN_5_TO_0(x)                                                     \\\n\t(((x) & BIT_MASK_DIVN_5_TO_0) << BIT_SHIFT_DIVN_5_TO_0)\n#define BITS_DIVN_5_TO_0 (BIT_MASK_DIVN_5_TO_0 << BIT_SHIFT_DIVN_5_TO_0)\n#define BIT_CLEAR_DIVN_5_TO_0(x) ((x) & (~BITS_DIVN_5_TO_0))\n#define BIT_GET_DIVN_5_TO_0(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DIVN_5_TO_0) & BIT_MASK_DIVN_5_TO_0)\n#define BIT_SET_DIVN_5_TO_0(x, v)                                              \\\n\t(BIT_CLEAR_DIVN_5_TO_0(x) | BIT_DIVN_5_TO_0(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_AFE_DUMMY BIT(3)\n#define BIT_REG_IDOUBLE BIT(2)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_RF3_SDMRSTB BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_REG_VCO_BIAS_BIT0 BIT(1)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_RF3_RSTB BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_REG_VCO_BIAS_BIT1 BIT(0)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL4\t\t\t\t(Offset 0x0078) */\n\n#define BIT_RF3_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_AFE_XTAL_CTRL_EXT\t\t\t(Offset 0x0078) */\n\n#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0 0\n#define BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0 0xf\n#define BIT_BB_DBG_SEL_AFE_SDM_3_TO_0(x)                                       \\\n\t(((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0)                            \\\n\t << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0)\n#define BITS_BB_DBG_SEL_AFE_SDM_3_TO_0                                         \\\n\t(BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0                                    \\\n\t << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0)\n#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_3_TO_0(x)                                 \\\n\t((x) & (~BITS_BB_DBG_SEL_AFE_SDM_3_TO_0))\n#define BIT_GET_BB_DBG_SEL_AFE_SDM_3_TO_0(x)                                   \\\n\t(((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0) &                        \\\n\t BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0)\n#define BIT_SET_BB_DBG_SEL_AFE_SDM_3_TO_0(x, v)                                \\\n\t(BIT_CLEAR_BB_DBG_SEL_AFE_SDM_3_TO_0(x) |                              \\\n\t BIT_BB_DBG_SEL_AFE_SDM_3_TO_0(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SPS_EN_DIODE BIT(31)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_EXT_SWR_CTRL_EN BIT(31)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_REF_FREF_EDGE BIT(29)\n#define BIT_REG_VREF_SEL_V1 BIT(28)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_ZCD_HW_AUTO_EN BIT(27)\n#define BIT_ZCD_REGSEL BIT(26)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SHIFT_REG_CP_OFFSET_4_TO_0 23\n#define BIT_MASK_REG_CP_OFFSET_4_TO_0 0x1f\n#define BIT_REG_CP_OFFSET_4_TO_0(x)                                            \\\n\t(((x) & BIT_MASK_REG_CP_OFFSET_4_TO_0)                                 \\\n\t << BIT_SHIFT_REG_CP_OFFSET_4_TO_0)\n#define BITS_REG_CP_OFFSET_4_TO_0                                              \\\n\t(BIT_MASK_REG_CP_OFFSET_4_TO_0 << BIT_SHIFT_REG_CP_OFFSET_4_TO_0)\n#define BIT_CLEAR_REG_CP_OFFSET_4_TO_0(x) ((x) & (~BITS_REG_CP_OFFSET_4_TO_0))\n#define BIT_GET_REG_CP_OFFSET_4_TO_0(x)                                        \\\n\t(((x) >> BIT_SHIFT_REG_CP_OFFSET_4_TO_0) &                             \\\n\t BIT_MASK_REG_CP_OFFSET_4_TO_0)\n#define BIT_SET_REG_CP_OFFSET_4_TO_0(x, v)                                     \\\n\t(BIT_CLEAR_REG_CP_OFFSET_4_TO_0(x) | BIT_REG_CP_OFFSET_4_TO_0(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SHIFT_AUTO_ZCD_IN_CODE 21\n#define BIT_MASK_AUTO_ZCD_IN_CODE 0x1f\n#define BIT_AUTO_ZCD_IN_CODE(x)                                                \\\n\t(((x) & BIT_MASK_AUTO_ZCD_IN_CODE) << BIT_SHIFT_AUTO_ZCD_IN_CODE)\n#define BITS_AUTO_ZCD_IN_CODE                                                  \\\n\t(BIT_MASK_AUTO_ZCD_IN_CODE << BIT_SHIFT_AUTO_ZCD_IN_CODE)\n#define BIT_CLEAR_AUTO_ZCD_IN_CODE(x) ((x) & (~BITS_AUTO_ZCD_IN_CODE))\n#define BIT_GET_AUTO_ZCD_IN_CODE(x)                                            \\\n\t(((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE) & BIT_MASK_AUTO_ZCD_IN_CODE)\n#define BIT_SET_AUTO_ZCD_IN_CODE(x, v)                                         \\\n\t(BIT_CLEAR_AUTO_ZCD_IN_CODE(x) | BIT_AUTO_ZCD_IN_CODE(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SHIFT_REG_RS_SET_2_TO_0 20\n#define BIT_MASK_REG_RS_SET_2_TO_0 0x7\n#define BIT_REG_RS_SET_2_TO_0(x)                                               \\\n\t(((x) & BIT_MASK_REG_RS_SET_2_TO_0) << BIT_SHIFT_REG_RS_SET_2_TO_0)\n#define BITS_REG_RS_SET_2_TO_0                                                 \\\n\t(BIT_MASK_REG_RS_SET_2_TO_0 << BIT_SHIFT_REG_RS_SET_2_TO_0)\n#define BIT_CLEAR_REG_RS_SET_2_TO_0(x) ((x) & (~BITS_REG_RS_SET_2_TO_0))\n#define BIT_GET_REG_RS_SET_2_TO_0(x)                                           \\\n\t(((x) >> BIT_SHIFT_REG_RS_SET_2_TO_0) & BIT_MASK_REG_RS_SET_2_TO_0)\n#define BIT_SET_REG_RS_SET_2_TO_0(x, v)                                        \\\n\t(BIT_CLEAR_REG_RS_SET_2_TO_0(x) | BIT_REG_RS_SET_2_TO_0(v))\n\n#define BIT_SHIFT_REG_CS_SET_1_TO_0 18\n#define BIT_MASK_REG_CS_SET_1_TO_0 0x3\n#define BIT_REG_CS_SET_1_TO_0(x)                                               \\\n\t(((x) & BIT_MASK_REG_CS_SET_1_TO_0) << BIT_SHIFT_REG_CS_SET_1_TO_0)\n#define BITS_REG_CS_SET_1_TO_0                                                 \\\n\t(BIT_MASK_REG_CS_SET_1_TO_0 << BIT_SHIFT_REG_CS_SET_1_TO_0)\n#define BIT_CLEAR_REG_CS_SET_1_TO_0(x) ((x) & (~BITS_REG_CS_SET_1_TO_0))\n#define BIT_GET_REG_CS_SET_1_TO_0(x)                                           \\\n\t(((x) >> BIT_SHIFT_REG_CS_SET_1_TO_0) & BIT_MASK_REG_CS_SET_1_TO_0)\n#define BIT_SET_REG_CS_SET_1_TO_0(x, v)                                        \\\n\t(BIT_CLEAR_REG_CS_SET_1_TO_0(x) | BIT_REG_CS_SET_1_TO_0(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SHIFT_ZCD_CODE_IN_L 16\n#define BIT_MASK_ZCD_CODE_IN_L 0x1f\n#define BIT_ZCD_CODE_IN_L(x)                                                   \\\n\t(((x) & BIT_MASK_ZCD_CODE_IN_L) << BIT_SHIFT_ZCD_CODE_IN_L)\n#define BITS_ZCD_CODE_IN_L (BIT_MASK_ZCD_CODE_IN_L << BIT_SHIFT_ZCD_CODE_IN_L)\n#define BIT_CLEAR_ZCD_CODE_IN_L(x) ((x) & (~BITS_ZCD_CODE_IN_L))\n#define BIT_GET_ZCD_CODE_IN_L(x)                                               \\\n\t(((x) >> BIT_SHIFT_ZCD_CODE_IN_L) & BIT_MASK_ZCD_CODE_IN_L)\n#define BIT_SET_ZCD_CODE_IN_L(x, v)                                            \\\n\t(BIT_CLEAR_ZCD_CODE_IN_L(x) | BIT_ZCD_CODE_IN_L(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SHIFT_REG_CP_SET_1_TO_0 16\n#define BIT_MASK_REG_CP_SET_1_TO_0 0x3\n#define BIT_REG_CP_SET_1_TO_0(x)                                               \\\n\t(((x) & BIT_MASK_REG_CP_SET_1_TO_0) << BIT_SHIFT_REG_CP_SET_1_TO_0)\n#define BITS_REG_CP_SET_1_TO_0                                                 \\\n\t(BIT_MASK_REG_CP_SET_1_TO_0 << BIT_SHIFT_REG_CP_SET_1_TO_0)\n#define BIT_CLEAR_REG_CP_SET_1_TO_0(x) ((x) & (~BITS_REG_CP_SET_1_TO_0))\n#define BIT_GET_REG_CP_SET_1_TO_0(x)                                           \\\n\t(((x) >> BIT_SHIFT_REG_CP_SET_1_TO_0) & BIT_MASK_REG_CP_SET_1_TO_0)\n#define BIT_SET_REG_CP_SET_1_TO_0(x, v)                                        \\\n\t(BIT_CLEAR_REG_CP_SET_1_TO_0(x) | BIT_REG_CP_SET_1_TO_0(v))\n\n#define BIT_LPFEN BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SHIFT_LDO_HV5_DUMMY 14\n#define BIT_MASK_LDO_HV5_DUMMY 0x3\n#define BIT_LDO_HV5_DUMMY(x)                                                   \\\n\t(((x) & BIT_MASK_LDO_HV5_DUMMY) << BIT_SHIFT_LDO_HV5_DUMMY)\n#define BITS_LDO_HV5_DUMMY (BIT_MASK_LDO_HV5_DUMMY << BIT_SHIFT_LDO_HV5_DUMMY)\n#define BIT_CLEAR_LDO_HV5_DUMMY(x) ((x) & (~BITS_LDO_HV5_DUMMY))\n#define BIT_GET_LDO_HV5_DUMMY(x)                                               \\\n\t(((x) >> BIT_SHIFT_LDO_HV5_DUMMY) & BIT_MASK_LDO_HV5_DUMMY)\n#define BIT_SET_LDO_HV5_DUMMY(x, v)                                            \\\n\t(BIT_CLEAR_LDO_HV5_DUMMY(x) | BIT_LDO_HV5_DUMMY(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_REG_DOGENB BIT(14)\n#define BIT_REG_TEST_EN BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SHIFT_REG_VTUNE33 12\n#define BIT_MASK_REG_VTUNE33 0x3\n#define BIT_REG_VTUNE33(x)                                                     \\\n\t(((x) & BIT_MASK_REG_VTUNE33) << BIT_SHIFT_REG_VTUNE33)\n#define BITS_REG_VTUNE33 (BIT_MASK_REG_VTUNE33 << BIT_SHIFT_REG_VTUNE33)\n#define BIT_CLEAR_REG_VTUNE33(x) ((x) & (~BITS_REG_VTUNE33))\n#define BIT_GET_REG_VTUNE33(x)                                                 \\\n\t(((x) >> BIT_SHIFT_REG_VTUNE33) & BIT_MASK_REG_VTUNE33)\n#define BIT_SET_REG_VTUNE33(x, v)                                              \\\n\t(BIT_CLEAR_REG_VTUNE33(x) | BIT_REG_VTUNE33(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1 12\n#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1 0x3\n#define BIT_REG_VTUNE33_BIT0_TO_BIT1(x)                                        \\\n\t(((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1)                             \\\n\t << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1)\n#define BITS_REG_VTUNE33_BIT0_TO_BIT1                                          \\\n\t(BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1                                     \\\n\t << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1)\n#define BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1(x)                                  \\\n\t((x) & (~BITS_REG_VTUNE33_BIT0_TO_BIT1))\n#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1(x)                                    \\\n\t(((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) &                         \\\n\t BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1)\n#define BIT_SET_REG_VTUNE33_BIT0_TO_BIT1(x, v)                                 \\\n\t(BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1(x) |                               \\\n\t BIT_REG_VTUNE33_BIT0_TO_BIT1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SHIFT_REG_STANDBY33 10\n#define BIT_MASK_REG_STANDBY33 0x3\n#define BIT_REG_STANDBY33(x)                                                   \\\n\t(((x) & BIT_MASK_REG_STANDBY33) << BIT_SHIFT_REG_STANDBY33)\n#define BITS_REG_STANDBY33 (BIT_MASK_REG_STANDBY33 << BIT_SHIFT_REG_STANDBY33)\n#define BIT_CLEAR_REG_STANDBY33(x) ((x) & (~BITS_REG_STANDBY33))\n#define BIT_GET_REG_STANDBY33(x)                                               \\\n\t(((x) >> BIT_SHIFT_REG_STANDBY33) & BIT_MASK_REG_STANDBY33)\n#define BIT_SET_REG_STANDBY33(x, v)                                            \\\n\t(BIT_CLEAR_REG_STANDBY33(x) | BIT_REG_STANDBY33(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1 10\n#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1 0x3\n#define BIT_REG_STANDBY33_BIT0_TO_BIT1(x)                                      \\\n\t(((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1)                           \\\n\t << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1)\n#define BITS_REG_STANDBY33_BIT0_TO_BIT1                                        \\\n\t(BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1                                   \\\n\t << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1)\n#define BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1(x)                                \\\n\t((x) & (~BITS_REG_STANDBY33_BIT0_TO_BIT1))\n#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1(x)                                  \\\n\t(((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) &                       \\\n\t BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1)\n#define BIT_SET_REG_STANDBY33_BIT0_TO_BIT1(x, v)                               \\\n\t(BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1(x) |                             \\\n\t BIT_REG_STANDBY33_BIT0_TO_BIT1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SHIFT_REG_LOAD33 8\n#define BIT_MASK_REG_LOAD33 0x3\n#define BIT_REG_LOAD33(x) (((x) & BIT_MASK_REG_LOAD33) << BIT_SHIFT_REG_LOAD33)\n#define BITS_REG_LOAD33 (BIT_MASK_REG_LOAD33 << BIT_SHIFT_REG_LOAD33)\n#define BIT_CLEAR_REG_LOAD33(x) ((x) & (~BITS_REG_LOAD33))\n#define BIT_GET_REG_LOAD33(x)                                                  \\\n\t(((x) >> BIT_SHIFT_REG_LOAD33) & BIT_MASK_REG_LOAD33)\n#define BIT_SET_REG_LOAD33(x, v) (BIT_CLEAR_REG_LOAD33(x) | BIT_REG_LOAD33(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1 8\n#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 0x3\n#define BIT_REG_LOAD33_BIT0_TO_BIT1(x)                                         \\\n\t(((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1)                              \\\n\t << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1)\n#define BITS_REG_LOAD33_BIT0_TO_BIT1                                           \\\n\t(BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1)\n#define BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1(x)                                   \\\n\t((x) & (~BITS_REG_LOAD33_BIT0_TO_BIT1))\n#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1(x)                                     \\\n\t(((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) &                          \\\n\t BIT_MASK_REG_LOAD33_BIT0_TO_BIT1)\n#define BIT_SET_REG_LOAD33_BIT0_TO_BIT1(x, v)                                  \\\n\t(BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1(x) | BIT_REG_LOAD33_BIT0_TO_BIT1(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SHIFT_REG_DIV_SEL 8\n#define BIT_MASK_REG_DIV_SEL 0x1f\n#define BIT_REG_DIV_SEL(x)                                                     \\\n\t(((x) & BIT_MASK_REG_DIV_SEL) << BIT_SHIFT_REG_DIV_SEL)\n#define BITS_REG_DIV_SEL (BIT_MASK_REG_DIV_SEL << BIT_SHIFT_REG_DIV_SEL)\n#define BIT_CLEAR_REG_DIV_SEL(x) ((x) & (~BITS_REG_DIV_SEL))\n#define BIT_GET_REG_DIV_SEL(x)                                                 \\\n\t(((x) >> BIT_SHIFT_REG_DIV_SEL) & BIT_MASK_REG_DIV_SEL)\n#define BIT_SET_REG_DIV_SEL(x, v)                                              \\\n\t(BIT_CLEAR_REG_DIV_SEL(x) | BIT_REG_DIV_SEL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_REG_BYPASS_L BIT(7)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_EN_CK200M BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_REG_LDOF_L BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_REG_OCPS_L BIT(5)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SHIFT_REG_KVCO_200M_1_TO_0 5\n#define BIT_MASK_REG_KVCO_200M_1_TO_0 0x3\n#define BIT_REG_KVCO_200M_1_TO_0(x)                                            \\\n\t(((x) & BIT_MASK_REG_KVCO_200M_1_TO_0)                                 \\\n\t << BIT_SHIFT_REG_KVCO_200M_1_TO_0)\n#define BITS_REG_KVCO_200M_1_TO_0                                              \\\n\t(BIT_MASK_REG_KVCO_200M_1_TO_0 << BIT_SHIFT_REG_KVCO_200M_1_TO_0)\n#define BIT_CLEAR_REG_KVCO_200M_1_TO_0(x) ((x) & (~BITS_REG_KVCO_200M_1_TO_0))\n#define BIT_GET_REG_KVCO_200M_1_TO_0(x)                                        \\\n\t(((x) >> BIT_SHIFT_REG_KVCO_200M_1_TO_0) &                             \\\n\t BIT_MASK_REG_KVCO_200M_1_TO_0)\n#define BIT_SET_REG_KVCO_200M_1_TO_0(x, v)                                     \\\n\t(BIT_CLEAR_REG_KVCO_200M_1_TO_0(x) | BIT_REG_KVCO_200M_1_TO_0(v))\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_REG_TYPE_L_V1 BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_ARENB_L BIT(3)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0 2\n#define BIT_MASK_REG_CP_BIAS_200M_2_TO_0 0x7\n#define BIT_REG_CP_BIAS_200M_2_TO_0(x)                                         \\\n\t(((x) & BIT_MASK_REG_CP_BIAS_200M_2_TO_0)                              \\\n\t << BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0)\n#define BITS_REG_CP_BIAS_200M_2_TO_0                                           \\\n\t(BIT_MASK_REG_CP_BIAS_200M_2_TO_0 << BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0)\n#define BIT_CLEAR_REG_CP_BIAS_200M_2_TO_0(x)                                   \\\n\t((x) & (~BITS_REG_CP_BIAS_200M_2_TO_0))\n#define BIT_GET_REG_CP_BIAS_200M_2_TO_0(x)                                     \\\n\t(((x) >> BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0) &                          \\\n\t BIT_MASK_REG_CP_BIAS_200M_2_TO_0)\n#define BIT_SET_REG_CP_BIAS_200M_2_TO_0(x, v)                                  \\\n\t(BIT_CLEAR_REG_CP_BIAS_200M_2_TO_0(x) | BIT_REG_CP_BIAS_200M_2_TO_0(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SHIFT_CFC_L_BIT_1_TO_0 1\n#define BIT_MASK_CFC_L_BIT_1_TO_0 0x3\n#define BIT_CFC_L_BIT_1_TO_0(x)                                                \\\n\t(((x) & BIT_MASK_CFC_L_BIT_1_TO_0) << BIT_SHIFT_CFC_L_BIT_1_TO_0)\n#define BITS_CFC_L_BIT_1_TO_0                                                  \\\n\t(BIT_MASK_CFC_L_BIT_1_TO_0 << BIT_SHIFT_CFC_L_BIT_1_TO_0)\n#define BIT_CLEAR_CFC_L_BIT_1_TO_0(x) ((x) & (~BITS_CFC_L_BIT_1_TO_0))\n#define BIT_GET_CFC_L_BIT_1_TO_0(x)                                            \\\n\t(((x) >> BIT_SHIFT_CFC_L_BIT_1_TO_0) & BIT_MASK_CFC_L_BIT_1_TO_0)\n#define BIT_SET_CFC_L_BIT_1_TO_0(x, v)                                         \\\n\t(BIT_CLEAR_CFC_L_BIT_1_TO_0(x) | BIT_CFC_L_BIT_1_TO_0(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_SHIFT_CFC_L 1\n#define BIT_MASK_CFC_L 0x3\n#define BIT_CFC_L(x) (((x) & BIT_MASK_CFC_L) << BIT_SHIFT_CFC_L)\n#define BITS_CFC_L (BIT_MASK_CFC_L << BIT_SHIFT_CFC_L)\n#define BIT_CLEAR_CFC_L(x) ((x) & (~BITS_CFC_L))\n#define BIT_GET_CFC_L(x) (((x) >> BIT_SHIFT_CFC_L) & BIT_MASK_CFC_L)\n#define BIT_SET_CFC_L(x, v) (BIT_CLEAR_CFC_L(x) | BIT_CFC_L(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_REG_TYPE_L BIT(0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_XCK_OUT_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_LDO_SWR_CTRL\t\t\t(Offset 0x007C) */\n\n#define BIT_REG_OCPS_L_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_MCUSUS_EN BIT(23)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_ANA_PORT_EN BIT(22)\n#define BIT_MAC_PORT_EN BIT(21)\n#define BIT_BOOT_FSPI_EN BIT(20)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_SHIFT_MCUROM_DL 16\n#define BIT_MASK_MCUROM_DL 0xf\n#define BIT_MCUROM_DL(x) (((x) & BIT_MASK_MCUROM_DL) << BIT_SHIFT_MCUROM_DL)\n#define BITS_MCUROM_DL (BIT_MASK_MCUROM_DL << BIT_SHIFT_MCUROM_DL)\n#define BIT_CLEAR_MCUROM_DL(x) ((x) & (~BITS_MCUROM_DL))\n#define BIT_GET_MCUROM_DL(x) (((x) >> BIT_SHIFT_MCUROM_DL) & BIT_MASK_MCUROM_DL)\n#define BIT_SET_MCUROM_DL(x, v) (BIT_CLEAR_MCUROM_DL(x) | BIT_MCUROM_DL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_FW_INIT_RDY BIT(15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_SHIFT_MCUFWDL_DMA_2KB_SEL 14\n#define BIT_MASK_MCUFWDL_DMA_2KB_SEL 0x3\n#define BIT_MCUFWDL_DMA_2KB_SEL(x)                                             \\\n\t(((x) & BIT_MASK_MCUFWDL_DMA_2KB_SEL) << BIT_SHIFT_MCUFWDL_DMA_2KB_SEL)\n#define BITS_MCUFWDL_DMA_2KB_SEL                                               \\\n\t(BIT_MASK_MCUFWDL_DMA_2KB_SEL << BIT_SHIFT_MCUFWDL_DMA_2KB_SEL)\n#define BIT_CLEAR_MCUFWDL_DMA_2KB_SEL(x) ((x) & (~BITS_MCUFWDL_DMA_2KB_SEL))\n#define BIT_GET_MCUFWDL_DMA_2KB_SEL(x)                                         \\\n\t(((x) >> BIT_SHIFT_MCUFWDL_DMA_2KB_SEL) & BIT_MASK_MCUFWDL_DMA_2KB_SEL)\n#define BIT_SET_MCUFWDL_DMA_2KB_SEL(x, v)                                      \\\n\t(BIT_CLEAR_MCUFWDL_DMA_2KB_SEL(x) | BIT_MCUFWDL_DMA_2KB_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_FW_DW_RDY BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_8051FW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_FWDL_RSVDPAGE_RDY BIT(12)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_SHIFT_CPU_CLK_SEL 12\n#define BIT_MASK_CPU_CLK_SEL 0x3\n#define BIT_CPU_CLK_SEL(x)                                                     \\\n\t(((x) & BIT_MASK_CPU_CLK_SEL) << BIT_SHIFT_CPU_CLK_SEL)\n#define BITS_CPU_CLK_SEL (BIT_MASK_CPU_CLK_SEL << BIT_SHIFT_CPU_CLK_SEL)\n#define BIT_CLEAR_CPU_CLK_SEL(x) ((x) & (~BITS_CPU_CLK_SEL))\n#define BIT_GET_CPU_CLK_SEL(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CPU_CLK_SEL) & BIT_MASK_CPU_CLK_SEL)\n#define BIT_SET_CPU_CLK_SEL(x, v)                                              \\\n\t(BIT_CLEAR_CPU_CLK_SEL(x) | BIT_CPU_CLK_SEL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_8051FW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_R_8051_ROMDLFW_EN BIT(11)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_MCUFWDL_DMA_EN BIT(11)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_CCLK_CHG_MASK BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_8051FW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_R_8051_INIT_RDY BIT(10)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_MCUINI_WROMRDY BIT(10)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_FW_INIT_RDY_V1 BIT(10)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_EMEM__TXBUF_CHKSUM_OK BIT(10)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_EMEM_TXBUF_CHKSUM_OK BIT(10)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_MCUTXA_SPD BIT(9)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_EMEM_TXBUF_DW_RDY BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_8051FW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_R_8051_GAT BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_MCUCLK_TEN BIT(8)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_MCU_CLK_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_EMEM_CHKSUM_OK BIT(8)\n#define BIT_EMEM_DW_OK BIT(7)\n#define BIT_TOGGLE BIT(7)\n#define BIT_DMEM_CHKSUM_OK BIT(6)\n#define BIT_ACK BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_8051FW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_RFINI_RDY BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_MCUINI_WRFCRDY BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_RF_INIT_RDY BIT(5)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_DMEM_DW_OK BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_8051FW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_BBINI_RDY BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_MCUINI_WPHYRDY BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_BB_INIT_RDY BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_IMEM_CHKSUM_OK BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_8051FW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_MACINI_RDY BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_MCUINI_WMACRDY BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_MAC_INIT_RDY BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_IMEM_DW_OK BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_8051FW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_FWDL_CHK_RPT BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_8051FW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_MCUFWDL_RDY BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_IMEM_BOOT_LOAD_DW_OK BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_MCUFW_CTRL\t\t\t\t(Offset 0x0080) */\n\n#define BIT_MCU_FWDL_RDY BIT(1)\n#define BIT_MCU_FWDL_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HRPWM1\t\t\t\t(Offset 0x10250080) */\n\n#define BIT_REQ_PS BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MCU_TST_CFG\t\t\t\t(Offset 0x0084) */\n\n#define BIT_SHIFT_8051CODE_OFS 16\n#define BIT_MASK_8051CODE_OFS 0xffff\n#define BIT_8051CODE_OFS(x)                                                    \\\n\t(((x) & BIT_MASK_8051CODE_OFS) << BIT_SHIFT_8051CODE_OFS)\n#define BITS_8051CODE_OFS (BIT_MASK_8051CODE_OFS << BIT_SHIFT_8051CODE_OFS)\n#define BIT_CLEAR_8051CODE_OFS(x) ((x) & (~BITS_8051CODE_OFS))\n#define BIT_GET_8051CODE_OFS(x)                                                \\\n\t(((x) >> BIT_SHIFT_8051CODE_OFS) & BIT_MASK_8051CODE_OFS)\n#define BIT_SET_8051CODE_OFS(x, v)                                             \\\n\t(BIT_CLEAR_8051CODE_OFS(x) | BIT_8051CODE_OFS(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MCU_TST_CFG\t\t\t\t(Offset 0x0084) */\n\n#define BIT_SHIFT_LBKTST 0\n#define BIT_MASK_LBKTST 0xffff\n#define BIT_LBKTST(x) (((x) & BIT_MASK_LBKTST) << BIT_SHIFT_LBKTST)\n#define BITS_LBKTST (BIT_MASK_LBKTST << BIT_SHIFT_LBKTST)\n#define BIT_CLEAR_LBKTST(x) ((x) & (~BITS_LBKTST))\n#define BIT_GET_LBKTST(x) (((x) >> BIT_SHIFT_LBKTST) & BIT_MASK_LBKTST)\n#define BIT_SET_LBKTST(x, v) (BIT_CLEAR_LBKTST(x) | BIT_LBKTST(v))\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_MCU_TST_CFG\t\t\t\t(Offset 0x0084) */\n\n#define BIT_SHIFT_C2H_MSG 0\n#define BIT_MASK_C2H_MSG 0xffff\n#define BIT_C2H_MSG(x) (((x) & BIT_MASK_C2H_MSG) << BIT_SHIFT_C2H_MSG)\n#define BITS_C2H_MSG (BIT_MASK_C2H_MSG << BIT_SHIFT_C2H_MSG)\n#define BIT_CLEAR_C2H_MSG(x) ((x) & (~BITS_C2H_MSG))\n#define BIT_GET_C2H_MSG(x) (((x) >> BIT_SHIFT_C2H_MSG) & BIT_MASK_C2H_MSG)\n#define BIT_SET_C2H_MSG(x, v) (BIT_CLEAR_C2H_MSG(x) | BIT_C2H_MSG(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_BUS_CTRL\t\t\t(Offset 0x10250085) */\n\n#define BIT_INT_MASK_DIS BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_BUS_CTRL\t\t\t(Offset 0x10250085) */\n\n#define BIT_PAD_CLK_XHGE_EN BIT(3)\n#define BIT_INTER_CLK_EN BIT(2)\n#define BIT_EN_RPT_TXCRC BIT(1)\n#define BIT_DIS_RXDMA_STS BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n/* 2 REG_SDIO_HSUS_CTRL\t\t\t(Offset 0x10250086) */\n\n#define BIT_SPI_PHASE BIT(5)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HSUS_CTRL\t\t\t(Offset 0x10250086) */\n\n#define BIT_INTR_CTRL BIT(4)\n#define BIT_SDIO_VOLTAGE BIT(3)\n#define BIT_BYPASS_INIT BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HSUS_CTRL\t\t\t(Offset 0x10250086) */\n\n#define BIT_HCI_RESUME_RDY BIT(1)\n#define BIT_HCI_SUS_REQ BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HMEBOX_E0_E1\t\t\t(Offset 0x0088) */\n\n#define BIT_SHIFT_HOST_MSG_E1 16\n#define BIT_MASK_HOST_MSG_E1 0xffff\n#define BIT_HOST_MSG_E1(x)                                                     \\\n\t(((x) & BIT_MASK_HOST_MSG_E1) << BIT_SHIFT_HOST_MSG_E1)\n#define BITS_HOST_MSG_E1 (BIT_MASK_HOST_MSG_E1 << BIT_SHIFT_HOST_MSG_E1)\n#define BIT_CLEAR_HOST_MSG_E1(x) ((x) & (~BITS_HOST_MSG_E1))\n#define BIT_GET_HOST_MSG_E1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E1) & BIT_MASK_HOST_MSG_E1)\n#define BIT_SET_HOST_MSG_E1(x, v)                                              \\\n\t(BIT_CLEAR_HOST_MSG_E1(x) | BIT_HOST_MSG_E1(v))\n\n#define BIT_SHIFT_HOST_MSG_E0 0\n#define BIT_MASK_HOST_MSG_E0 0xffff\n#define BIT_HOST_MSG_E0(x)                                                     \\\n\t(((x) & BIT_MASK_HOST_MSG_E0) << BIT_SHIFT_HOST_MSG_E0)\n#define BITS_HOST_MSG_E0 (BIT_MASK_HOST_MSG_E0 << BIT_SHIFT_HOST_MSG_E0)\n#define BIT_CLEAR_HOST_MSG_E0(x) ((x) & (~BITS_HOST_MSG_E0))\n#define BIT_GET_HOST_MSG_E0(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E0) & BIT_MASK_HOST_MSG_E0)\n#define BIT_SET_HOST_MSG_E0(x, v)                                              \\\n\t(BIT_CLEAR_HOST_MSG_E0(x) | BIT_HOST_MSG_E0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_RESPONSE_TIMER\t\t\t(Offset 0x10250088) */\n\n#define BIT_SHIFT_CMDIN_2RESP_TIMER 0\n#define BIT_MASK_CMDIN_2RESP_TIMER 0xffff\n#define BIT_CMDIN_2RESP_TIMER(x)                                               \\\n\t(((x) & BIT_MASK_CMDIN_2RESP_TIMER) << BIT_SHIFT_CMDIN_2RESP_TIMER)\n#define BITS_CMDIN_2RESP_TIMER                                                 \\\n\t(BIT_MASK_CMDIN_2RESP_TIMER << BIT_SHIFT_CMDIN_2RESP_TIMER)\n#define BIT_CLEAR_CMDIN_2RESP_TIMER(x) ((x) & (~BITS_CMDIN_2RESP_TIMER))\n#define BIT_GET_CMDIN_2RESP_TIMER(x)                                           \\\n\t(((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER) & BIT_MASK_CMDIN_2RESP_TIMER)\n#define BIT_SET_CMDIN_2RESP_TIMER(x, v)                                        \\\n\t(BIT_CLEAR_CMDIN_2RESP_TIMER(x) | BIT_CMDIN_2RESP_TIMER(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SDIO_CMD_CRC\t\t\t(Offset 0x1025008A) */\n\n#define BIT_SHIFT_SDIO_CMD_CRC 1\n#define BIT_MASK_SDIO_CMD_CRC 0x7f\n#define BIT_SDIO_CMD_CRC(x)                                                    \\\n\t(((x) & BIT_MASK_SDIO_CMD_CRC) << BIT_SHIFT_SDIO_CMD_CRC)\n#define BITS_SDIO_CMD_CRC (BIT_MASK_SDIO_CMD_CRC << BIT_SHIFT_SDIO_CMD_CRC)\n#define BIT_CLEAR_SDIO_CMD_CRC(x) ((x) & (~BITS_SDIO_CMD_CRC))\n#define BIT_GET_SDIO_CMD_CRC(x)                                                \\\n\t(((x) >> BIT_SHIFT_SDIO_CMD_CRC) & BIT_MASK_SDIO_CMD_CRC)\n#define BIT_SET_SDIO_CMD_CRC(x, v)                                             \\\n\t(BIT_CLEAR_SDIO_CMD_CRC(x) | BIT_SDIO_CMD_CRC(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_CMD_CRC\t\t\t(Offset 0x1025008A) */\n\n#define BIT_SHIFT_SDIO_CMD_CRC_V1 0\n#define BIT_MASK_SDIO_CMD_CRC_V1 0xff\n#define BIT_SDIO_CMD_CRC_V1(x)                                                 \\\n\t(((x) & BIT_MASK_SDIO_CMD_CRC_V1) << BIT_SHIFT_SDIO_CMD_CRC_V1)\n#define BITS_SDIO_CMD_CRC_V1                                                   \\\n\t(BIT_MASK_SDIO_CMD_CRC_V1 << BIT_SHIFT_SDIO_CMD_CRC_V1)\n#define BIT_CLEAR_SDIO_CMD_CRC_V1(x) ((x) & (~BITS_SDIO_CMD_CRC_V1))\n#define BIT_GET_SDIO_CMD_CRC_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1) & BIT_MASK_SDIO_CMD_CRC_V1)\n#define BIT_SET_SDIO_CMD_CRC_V1(x, v)                                          \\\n\t(BIT_CLEAR_SDIO_CMD_CRC_V1(x) | BIT_SDIO_CMD_CRC_V1(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SDIO_CMD_CRC\t\t\t(Offset 0x1025008A) */\n\n#define BIT_SDIO_CMD_E_BIT BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HMEBOX_E2_E3\t\t\t(Offset 0x008C) */\n\n#define BIT_SHIFT_HOST_MSG_E3 16\n#define BIT_MASK_HOST_MSG_E3 0xffff\n#define BIT_HOST_MSG_E3(x)                                                     \\\n\t(((x) & BIT_MASK_HOST_MSG_E3) << BIT_SHIFT_HOST_MSG_E3)\n#define BITS_HOST_MSG_E3 (BIT_MASK_HOST_MSG_E3 << BIT_SHIFT_HOST_MSG_E3)\n#define BIT_CLEAR_HOST_MSG_E3(x) ((x) & (~BITS_HOST_MSG_E3))\n#define BIT_GET_HOST_MSG_E3(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E3) & BIT_MASK_HOST_MSG_E3)\n#define BIT_SET_HOST_MSG_E3(x, v)                                              \\\n\t(BIT_CLEAR_HOST_MSG_E3(x) | BIT_HOST_MSG_E3(v))\n\n#define BIT_SHIFT_HOST_MSG_E2 0\n#define BIT_MASK_HOST_MSG_E2 0xffff\n#define BIT_HOST_MSG_E2(x)                                                     \\\n\t(((x) & BIT_MASK_HOST_MSG_E2) << BIT_SHIFT_HOST_MSG_E2)\n#define BITS_HOST_MSG_E2 (BIT_MASK_HOST_MSG_E2 << BIT_SHIFT_HOST_MSG_E2)\n#define BIT_CLEAR_HOST_MSG_E2(x) ((x) & (~BITS_HOST_MSG_E2))\n#define BIT_GET_HOST_MSG_E2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E2) & BIT_MASK_HOST_MSG_E2)\n#define BIT_SET_HOST_MSG_E2(x, v)                                              \\\n\t(BIT_CLEAR_HOST_MSG_E2(x) | BIT_HOST_MSG_E2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_WLLPSOP_EABM BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_WLLPSOP_ACKF BIT(30)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_TXFIFO_TH_INT BIT(30)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_WLLPSOP_DLDM BIT(29)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_WLLPSOP_NODS BIT(29)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_WLLPSOP_AFEP BIT(29)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_WLLPSOP_ESWR BIT(28)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_LPS_DIS_SW BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_WLLPSOP_PWMM BIT(27)\n#define BIT_WLLPSOP_EECK BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_WLLPSOP_WLPON BIT(25)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_WLLPSOP_WLMACOFF BIT(25)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_WLLPSOP_ELDO BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_WLLPSOP_EXTAL BIT(24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_WL_SYNPON_VOLTSPDN BIT(23)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_LPS_BB_REG_EN BIT(23)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_LOP_SKIP BIT(22)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_WLLPSOP_WLBBOFF BIT(22)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_LPS_BB_PWR_EN BIT(22)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_LOP_MEMDS BIT(21)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_WLLPSOP_WLMEM_DS BIT(21)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_LPS_BB_GLB_EN BIT(21)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_WLLPSOP_LDO_WAIT_TIME BIT(20)\n#define BIT_WLLPSOP_ANA_CLK_DIVISION_2 BIT(19)\n#define BIT_AFE_BCN BIT(18)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_SUS_DIS_SW BIT(15)\n#define BIT_SUS_SKP_PAGE0_ALD BIT(14)\n#define BIT_SUS_LDO_SLEEP BIT(13)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN 12\n#define BIT_MASK_LPLDH12_VADJ_STEP_DN 0xf\n#define BIT_LPLDH12_VADJ_STEP_DN(x)                                            \\\n\t(((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN)                                 \\\n\t << BIT_SHIFT_LPLDH12_VADJ_STEP_DN)\n#define BITS_LPLDH12_VADJ_STEP_DN                                              \\\n\t(BIT_MASK_LPLDH12_VADJ_STEP_DN << BIT_SHIFT_LPLDH12_VADJ_STEP_DN)\n#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN(x) ((x) & (~BITS_LPLDH12_VADJ_STEP_DN))\n#define BIT_GET_LPLDH12_VADJ_STEP_DN(x)                                        \\\n\t(((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN) &                             \\\n\t BIT_MASK_LPLDH12_VADJ_STEP_DN)\n#define BIT_SET_LPLDH12_VADJ_STEP_DN(x, v)                                     \\\n\t(BIT_CLEAR_LPLDH12_VADJ_STEP_DN(x) | BIT_LPLDH12_VADJ_STEP_DN(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_PFM_EN_ZCD BIT(12)\n#define BIT_KEEP_RFC_EN BIT(11)\n#define BIT_MACON_NO_RFCISO_RELEASE BIT(10)\n#define BIT_MACON_NO_AFEPORT_PWR BIT(9)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_SHIFT_V15ADJ_L1_STEP_DN 8\n#define BIT_MASK_V15ADJ_L1_STEP_DN 0x7\n#define BIT_V15ADJ_L1_STEP_DN(x)                                               \\\n\t(((x) & BIT_MASK_V15ADJ_L1_STEP_DN) << BIT_SHIFT_V15ADJ_L1_STEP_DN)\n#define BITS_V15ADJ_L1_STEP_DN                                                 \\\n\t(BIT_MASK_V15ADJ_L1_STEP_DN << BIT_SHIFT_V15ADJ_L1_STEP_DN)\n#define BIT_CLEAR_V15ADJ_L1_STEP_DN(x) ((x) & (~BITS_V15ADJ_L1_STEP_DN))\n#define BIT_GET_V15ADJ_L1_STEP_DN(x)                                           \\\n\t(((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN) & BIT_MASK_V15ADJ_L1_STEP_DN)\n#define BIT_SET_V15ADJ_L1_STEP_DN(x, v)                                        \\\n\t(BIT_CLEAR_V15ADJ_L1_STEP_DN(x) | BIT_V15ADJ_L1_STEP_DN(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_SHIFT_V15ADJ_L1_STEP_DN_V1 8\n#define BIT_MASK_V15ADJ_L1_STEP_DN_V1 0xf\n#define BIT_V15ADJ_L1_STEP_DN_V1(x)                                            \\\n\t(((x) & BIT_MASK_V15ADJ_L1_STEP_DN_V1)                                 \\\n\t << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1)\n#define BITS_V15ADJ_L1_STEP_DN_V1                                              \\\n\t(BIT_MASK_V15ADJ_L1_STEP_DN_V1 << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1)\n#define BIT_CLEAR_V15ADJ_L1_STEP_DN_V1(x) ((x) & (~BITS_V15ADJ_L1_STEP_DN_V1))\n#define BIT_GET_V15ADJ_L1_STEP_DN_V1(x)                                        \\\n\t(((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_V1) &                             \\\n\t BIT_MASK_V15ADJ_L1_STEP_DN_V1)\n#define BIT_SET_V15ADJ_L1_STEP_DN_V1(x, v)                                     \\\n\t(BIT_CLEAR_V15ADJ_L1_STEP_DN_V1(x) | BIT_V15ADJ_L1_STEP_DN_V1(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_MACON_NO_CPU_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_LD_B15V_EN BIT(7)\n#define BIT_LPRX_BCN_EN BIT(5)\n#define BIT_LBN BIT(4)\n#define BIT_LXSPS_UNUSED BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_FORCE_LEAVE_LPS BIT(3)\n#define BIT_SW_AFE_MODE BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_REGU_32K_CLK_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HSISR\t\t\t\t(Offset 0x10250090) */\n\n#define BIT_DRV_WLAN_INT_CLR BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WLLPS_CTRL\t\t\t\t(Offset 0x0090) */\n\n#define BIT_WL_LPS_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HSISR\t\t\t\t(Offset 0x10250090) */\n\n#define BIT_DRV_WLAN_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_HSIMR\t\t\t\t(Offset 0x10250091) */\n\n#define BIT_HISR_MASK BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL5\t\t\t\t(Offset 0x0094) */\n\n#define BIT_BB_DBG_SEL_AFE_SDM_V3 BIT(31)\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL5\t\t\t\t(Offset 0x0094) */\n\n#define BIT_BB_DBG_SEL_AFE_SDM_BIT0 BIT(31)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL5\t\t\t\t(Offset 0x0094) */\n\n#define BIT_ORDER_SDM BIT(30)\n#define BIT_RFE_SEL_SDM BIT(29)\n\n#define BIT_SHIFT_REF_SEL 25\n#define BIT_MASK_REF_SEL 0xf\n#define BIT_REF_SEL(x) (((x) & BIT_MASK_REF_SEL) << BIT_SHIFT_REF_SEL)\n#define BITS_REF_SEL (BIT_MASK_REF_SEL << BIT_SHIFT_REF_SEL)\n#define BIT_CLEAR_REF_SEL(x) ((x) & (~BITS_REF_SEL))\n#define BIT_GET_REF_SEL(x) (((x) >> BIT_SHIFT_REF_SEL) & BIT_MASK_REF_SEL)\n#define BIT_SET_REF_SEL(x, v) (BIT_CLEAR_REF_SEL(x) | BIT_REF_SEL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL5\t\t\t\t(Offset 0x0094) */\n\n#define BIT_SHIFT_F0F_SDM_V2 12\n#define BIT_MASK_F0F_SDM_V2 0x1fff\n#define BIT_F0F_SDM_V2(x) (((x) & BIT_MASK_F0F_SDM_V2) << BIT_SHIFT_F0F_SDM_V2)\n#define BITS_F0F_SDM_V2 (BIT_MASK_F0F_SDM_V2 << BIT_SHIFT_F0F_SDM_V2)\n#define BIT_CLEAR_F0F_SDM_V2(x) ((x) & (~BITS_F0F_SDM_V2))\n#define BIT_GET_F0F_SDM_V2(x)                                                  \\\n\t(((x) >> BIT_SHIFT_F0F_SDM_V2) & BIT_MASK_F0F_SDM_V2)\n#define BIT_SET_F0F_SDM_V2(x, v) (BIT_CLEAR_F0F_SDM_V2(x) | BIT_F0F_SDM_V2(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL5\t\t\t\t(Offset 0x0094) */\n\n#define BIT_SHIFT_F0F_SDM 12\n#define BIT_MASK_F0F_SDM 0x1fff\n#define BIT_F0F_SDM(x) (((x) & BIT_MASK_F0F_SDM) << BIT_SHIFT_F0F_SDM)\n#define BITS_F0F_SDM (BIT_MASK_F0F_SDM << BIT_SHIFT_F0F_SDM)\n#define BIT_CLEAR_F0F_SDM(x) ((x) & (~BITS_F0F_SDM))\n#define BIT_GET_F0F_SDM(x) (((x) >> BIT_SHIFT_F0F_SDM) & BIT_MASK_F0F_SDM)\n#define BIT_SET_F0F_SDM(x, v) (BIT_CLEAR_F0F_SDM(x) | BIT_F0F_SDM(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL5\t\t\t\t(Offset 0x0094) */\n\n#define BIT_SHIFT_F0N_SDM_V2 9\n#define BIT_MASK_F0N_SDM_V2 0x7\n#define BIT_F0N_SDM_V2(x) (((x) & BIT_MASK_F0N_SDM_V2) << BIT_SHIFT_F0N_SDM_V2)\n#define BITS_F0N_SDM_V2 (BIT_MASK_F0N_SDM_V2 << BIT_SHIFT_F0N_SDM_V2)\n#define BIT_CLEAR_F0N_SDM_V2(x) ((x) & (~BITS_F0N_SDM_V2))\n#define BIT_GET_F0N_SDM_V2(x)                                                  \\\n\t(((x) >> BIT_SHIFT_F0N_SDM_V2) & BIT_MASK_F0N_SDM_V2)\n#define BIT_SET_F0N_SDM_V2(x, v) (BIT_CLEAR_F0N_SDM_V2(x) | BIT_F0N_SDM_V2(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL5\t\t\t\t(Offset 0x0094) */\n\n#define BIT_SHIFT_F0N_SDM 9\n#define BIT_MASK_F0N_SDM 0x7\n#define BIT_F0N_SDM(x) (((x) & BIT_MASK_F0N_SDM) << BIT_SHIFT_F0N_SDM)\n#define BITS_F0N_SDM (BIT_MASK_F0N_SDM << BIT_SHIFT_F0N_SDM)\n#define BIT_CLEAR_F0N_SDM(x) ((x) & (~BITS_F0N_SDM))\n#define BIT_GET_F0N_SDM(x) (((x) >> BIT_SHIFT_F0N_SDM) & BIT_MASK_F0N_SDM)\n#define BIT_SET_F0N_SDM(x, v) (BIT_CLEAR_F0N_SDM(x) | BIT_F0N_SDM(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL5\t\t\t\t(Offset 0x0094) */\n\n#define BIT_SHIFT_DIVN_SDM_V2 3\n#define BIT_MASK_DIVN_SDM_V2 0x3f\n#define BIT_DIVN_SDM_V2(x)                                                     \\\n\t(((x) & BIT_MASK_DIVN_SDM_V2) << BIT_SHIFT_DIVN_SDM_V2)\n#define BITS_DIVN_SDM_V2 (BIT_MASK_DIVN_SDM_V2 << BIT_SHIFT_DIVN_SDM_V2)\n#define BIT_CLEAR_DIVN_SDM_V2(x) ((x) & (~BITS_DIVN_SDM_V2))\n#define BIT_GET_DIVN_SDM_V2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DIVN_SDM_V2) & BIT_MASK_DIVN_SDM_V2)\n#define BIT_SET_DIVN_SDM_V2(x, v)                                              \\\n\t(BIT_CLEAR_DIVN_SDM_V2(x) | BIT_DIVN_SDM_V2(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL5\t\t\t\t(Offset 0x0094) */\n\n#define BIT_SHIFT_DIVN_SDM 3\n#define BIT_MASK_DIVN_SDM 0x3f\n#define BIT_DIVN_SDM(x) (((x) & BIT_MASK_DIVN_SDM) << BIT_SHIFT_DIVN_SDM)\n#define BITS_DIVN_SDM (BIT_MASK_DIVN_SDM << BIT_SHIFT_DIVN_SDM)\n#define BIT_CLEAR_DIVN_SDM(x) ((x) & (~BITS_DIVN_SDM))\n#define BIT_GET_DIVN_SDM(x) (((x) >> BIT_SHIFT_DIVN_SDM) & BIT_MASK_DIVN_SDM)\n#define BIT_SET_DIVN_SDM(x, v) (BIT_CLEAR_DIVN_SDM(x) | BIT_DIVN_SDM(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL5\t\t\t\t(Offset 0x0094) */\n\n#define BIT_SHIFT_DITHER_SDM_V2 0\n#define BIT_MASK_DITHER_SDM_V2 0x7\n#define BIT_DITHER_SDM_V2(x)                                                   \\\n\t(((x) & BIT_MASK_DITHER_SDM_V2) << BIT_SHIFT_DITHER_SDM_V2)\n#define BITS_DITHER_SDM_V2 (BIT_MASK_DITHER_SDM_V2 << BIT_SHIFT_DITHER_SDM_V2)\n#define BIT_CLEAR_DITHER_SDM_V2(x) ((x) & (~BITS_DITHER_SDM_V2))\n#define BIT_GET_DITHER_SDM_V2(x)                                               \\\n\t(((x) >> BIT_SHIFT_DITHER_SDM_V2) & BIT_MASK_DITHER_SDM_V2)\n#define BIT_SET_DITHER_SDM_V2(x, v)                                            \\\n\t(BIT_CLEAR_DITHER_SDM_V2(x) | BIT_DITHER_SDM_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GPIO_DEBOUNCE_CTRL\t\t\t(Offset 0x0098) */\n\n#define BIT_WLGP_DBC1EN BIT(15)\n\n#define BIT_SHIFT_WLGP_DBC1 8\n#define BIT_MASK_WLGP_DBC1 0xf\n#define BIT_WLGP_DBC1(x) (((x) & BIT_MASK_WLGP_DBC1) << BIT_SHIFT_WLGP_DBC1)\n#define BITS_WLGP_DBC1 (BIT_MASK_WLGP_DBC1 << BIT_SHIFT_WLGP_DBC1)\n#define BIT_CLEAR_WLGP_DBC1(x) ((x) & (~BITS_WLGP_DBC1))\n#define BIT_GET_WLGP_DBC1(x) (((x) >> BIT_SHIFT_WLGP_DBC1) & BIT_MASK_WLGP_DBC1)\n#define BIT_SET_WLGP_DBC1(x, v) (BIT_CLEAR_WLGP_DBC1(x) | BIT_WLGP_DBC1(v))\n\n#define BIT_WLGP_DBC0EN BIT(7)\n\n#define BIT_SHIFT_WLGP_DBC0 0\n#define BIT_MASK_WLGP_DBC0 0xf\n#define BIT_WLGP_DBC0(x) (((x) & BIT_MASK_WLGP_DBC0) << BIT_SHIFT_WLGP_DBC0)\n#define BITS_WLGP_DBC0 (BIT_MASK_WLGP_DBC0 << BIT_SHIFT_WLGP_DBC0)\n#define BIT_CLEAR_WLGP_DBC0(x) ((x) & (~BITS_WLGP_DBC0))\n#define BIT_GET_WLGP_DBC0(x) (((x) >> BIT_SHIFT_WLGP_DBC0) & BIT_MASK_WLGP_DBC0)\n#define BIT_SET_WLGP_DBC0(x, v) (BIT_CLEAR_WLGP_DBC0(x) | BIT_WLGP_DBC0(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RPWM2\t\t\t\t(Offset 0x009C) */\n\n#define BIT_SHIFT_RPWM2 16\n#define BIT_MASK_RPWM2 0xffff\n#define BIT_RPWM2(x) (((x) & BIT_MASK_RPWM2) << BIT_SHIFT_RPWM2)\n#define BITS_RPWM2 (BIT_MASK_RPWM2 << BIT_SHIFT_RPWM2)\n#define BIT_CLEAR_RPWM2(x) ((x) & (~BITS_RPWM2))\n#define BIT_GET_RPWM2(x) (((x) >> BIT_SHIFT_RPWM2) & BIT_MASK_RPWM2)\n#define BIT_SET_RPWM2(x, v) (BIT_CLEAR_RPWM2(x) | BIT_RPWM2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYSON_FSM_MON\t\t\t(Offset 0x00A0) */\n\n#define BIT_SHIFT_FSM_MON_SEL 24\n#define BIT_MASK_FSM_MON_SEL 0x7\n#define BIT_FSM_MON_SEL(x)                                                     \\\n\t(((x) & BIT_MASK_FSM_MON_SEL) << BIT_SHIFT_FSM_MON_SEL)\n#define BITS_FSM_MON_SEL (BIT_MASK_FSM_MON_SEL << BIT_SHIFT_FSM_MON_SEL)\n#define BIT_CLEAR_FSM_MON_SEL(x) ((x) & (~BITS_FSM_MON_SEL))\n#define BIT_GET_FSM_MON_SEL(x)                                                 \\\n\t(((x) >> BIT_SHIFT_FSM_MON_SEL) & BIT_MASK_FSM_MON_SEL)\n#define BIT_SET_FSM_MON_SEL(x, v)                                              \\\n\t(BIT_CLEAR_FSM_MON_SEL(x) | BIT_FSM_MON_SEL(v))\n\n#define BIT_DOP_ELDO BIT(23)\n#define BIT_FSM_MON_UPD BIT(15)\n\n#define BIT_SHIFT_FSM_PAR 0\n#define BIT_MASK_FSM_PAR 0x7fff\n#define BIT_FSM_PAR(x) (((x) & BIT_MASK_FSM_PAR) << BIT_SHIFT_FSM_PAR)\n#define BITS_FSM_PAR (BIT_MASK_FSM_PAR << BIT_SHIFT_FSM_PAR)\n#define BIT_CLEAR_FSM_PAR(x) ((x) & (~BITS_FSM_PAR))\n#define BIT_GET_FSM_PAR(x) (((x) >> BIT_SHIFT_FSM_PAR) & BIT_MASK_FSM_PAR)\n#define BIT_SET_FSM_PAR(x, v) (BIT_CLEAR_FSM_PAR(x) | BIT_FSM_PAR(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL6\t\t\t\t(Offset 0x00A4) */\n\n#define BIT_SHIFT_TSFT_SEL_V1 0\n#define BIT_MASK_TSFT_SEL_V1 0x7\n#define BIT_TSFT_SEL_V1(x)                                                     \\\n\t(((x) & BIT_MASK_TSFT_SEL_V1) << BIT_SHIFT_TSFT_SEL_V1)\n#define BITS_TSFT_SEL_V1 (BIT_MASK_TSFT_SEL_V1 << BIT_SHIFT_TSFT_SEL_V1)\n#define BIT_CLEAR_TSFT_SEL_V1(x) ((x) & (~BITS_TSFT_SEL_V1))\n#define BIT_GET_TSFT_SEL_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TSFT_SEL_V1) & BIT_MASK_TSFT_SEL_V1)\n#define BIT_SET_TSFT_SEL_V1(x, v)                                              \\\n\t(BIT_CLEAR_TSFT_SEL_V1(x) | BIT_TSFT_SEL_V1(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL6\t\t\t\t(Offset 0x00A4) */\n\n#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1 0\n#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1 0x7\n#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(x)                                       \\\n\t(((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1)                            \\\n\t << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1)\n#define BITS_BB_DBG_SEL_AFE_SDM_BIT3_1                                         \\\n\t(BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1                                    \\\n\t << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1)\n#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1(x)                                 \\\n\t((x) & (~BITS_BB_DBG_SEL_AFE_SDM_BIT3_1))\n#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1(x)                                   \\\n\t(((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) &                        \\\n\t BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1)\n#define BIT_SET_BB_DBG_SEL_AFE_SDM_BIT3_1(x, v)                                \\\n\t(BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1(x) |                              \\\n\t BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PMC_DBG_CTRL1\t\t\t(Offset 0x00A8) */\n\n#define BIT_BT_INT_EN BIT(31)\n\n#define BIT_SHIFT_RD_WR_WIFI_BT_INFO 16\n#define BIT_MASK_RD_WR_WIFI_BT_INFO 0x7fff\n#define BIT_RD_WR_WIFI_BT_INFO(x)                                              \\\n\t(((x) & BIT_MASK_RD_WR_WIFI_BT_INFO) << BIT_SHIFT_RD_WR_WIFI_BT_INFO)\n#define BITS_RD_WR_WIFI_BT_INFO                                                \\\n\t(BIT_MASK_RD_WR_WIFI_BT_INFO << BIT_SHIFT_RD_WR_WIFI_BT_INFO)\n#define BIT_CLEAR_RD_WR_WIFI_BT_INFO(x) ((x) & (~BITS_RD_WR_WIFI_BT_INFO))\n#define BIT_GET_RD_WR_WIFI_BT_INFO(x)                                          \\\n\t(((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO) & BIT_MASK_RD_WR_WIFI_BT_INFO)\n#define BIT_SET_RD_WR_WIFI_BT_INFO(x, v)                                       \\\n\t(BIT_CLEAR_RD_WR_WIFI_BT_INFO(x) | BIT_RD_WR_WIFI_BT_INFO(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PMC_DBG_CTRL1\t\t\t(Offset 0x00A8) */\n\n#define BIT_PMC_WR_OVF BIT(8)\n\n#define BIT_SHIFT_WLPMC_ERRINT 0\n#define BIT_MASK_WLPMC_ERRINT 0xff\n#define BIT_WLPMC_ERRINT(x)                                                    \\\n\t(((x) & BIT_MASK_WLPMC_ERRINT) << BIT_SHIFT_WLPMC_ERRINT)\n#define BITS_WLPMC_ERRINT (BIT_MASK_WLPMC_ERRINT << BIT_SHIFT_WLPMC_ERRINT)\n#define BIT_CLEAR_WLPMC_ERRINT(x) ((x) & (~BITS_WLPMC_ERRINT))\n#define BIT_GET_WLPMC_ERRINT(x)                                                \\\n\t(((x) >> BIT_SHIFT_WLPMC_ERRINT) & BIT_MASK_WLPMC_ERRINT)\n#define BIT_SET_WLPMC_ERRINT(x, v)                                             \\\n\t(BIT_CLEAR_WLPMC_ERRINT(x) | BIT_WLPMC_ERRINT(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL7\t\t\t\t(Offset 0x00AC) */\n\n#define BIT_SHIFT_SEL_V 30\n#define BIT_MASK_SEL_V 0x3\n#define BIT_SEL_V(x) (((x) & BIT_MASK_SEL_V) << BIT_SHIFT_SEL_V)\n#define BITS_SEL_V (BIT_MASK_SEL_V << BIT_SHIFT_SEL_V)\n#define BIT_CLEAR_SEL_V(x) ((x) & (~BITS_SEL_V))\n#define BIT_GET_SEL_V(x) (((x) >> BIT_SHIFT_SEL_V) & BIT_MASK_SEL_V)\n#define BIT_SET_SEL_V(x, v) (BIT_CLEAR_SEL_V(x) | BIT_SEL_V(v))\n\n#define BIT_SEL_LDO_PC BIT(29)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL7\t\t\t\t(Offset 0x00AC) */\n\n#define BIT_SHIFT_CK_MON_SEL 26\n#define BIT_MASK_CK_MON_SEL 0x7\n#define BIT_CK_MON_SEL(x) (((x) & BIT_MASK_CK_MON_SEL) << BIT_SHIFT_CK_MON_SEL)\n#define BITS_CK_MON_SEL (BIT_MASK_CK_MON_SEL << BIT_SHIFT_CK_MON_SEL)\n#define BIT_CLEAR_CK_MON_SEL(x) ((x) & (~BITS_CK_MON_SEL))\n#define BIT_GET_CK_MON_SEL(x)                                                  \\\n\t(((x) >> BIT_SHIFT_CK_MON_SEL) & BIT_MASK_CK_MON_SEL)\n#define BIT_SET_CK_MON_SEL(x, v) (BIT_CLEAR_CK_MON_SEL(x) | BIT_CK_MON_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL7\t\t\t\t(Offset 0x00AC) */\n\n#define BIT_SHIFT_CK_MON_SEL_V2 26\n#define BIT_MASK_CK_MON_SEL_V2 0x7\n#define BIT_CK_MON_SEL_V2(x)                                                   \\\n\t(((x) & BIT_MASK_CK_MON_SEL_V2) << BIT_SHIFT_CK_MON_SEL_V2)\n#define BITS_CK_MON_SEL_V2 (BIT_MASK_CK_MON_SEL_V2 << BIT_SHIFT_CK_MON_SEL_V2)\n#define BIT_CLEAR_CK_MON_SEL_V2(x) ((x) & (~BITS_CK_MON_SEL_V2))\n#define BIT_GET_CK_MON_SEL_V2(x)                                               \\\n\t(((x) >> BIT_SHIFT_CK_MON_SEL_V2) & BIT_MASK_CK_MON_SEL_V2)\n#define BIT_SET_CK_MON_SEL_V2(x, v)                                            \\\n\t(BIT_CLEAR_CK_MON_SEL_V2(x) | BIT_CK_MON_SEL_V2(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL7\t\t\t\t(Offset 0x00AC) */\n\n#define BIT_CK_MON_EN BIT(25)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL7\t\t\t\t(Offset 0x00AC) */\n\n#define BIT_WL_DSS_SPEED_EN BIT(25)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL7\t\t\t\t(Offset 0x00AC) */\n\n#define BIT_FREF_EDGE BIT(24)\n#define BIT_CK320M_EN BIT(23)\n#define BIT_CK_5M_EN BIT(22)\n#define BIT_TESTEN BIT(21)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL7\t\t\t\t(Offset 0x00AC) */\n\n#define BIT_LD_B12V_EN_V1 BIT(7)\n\n#define BIT_SHIFT_WL_DSS_COUNT_OUT 0\n#define BIT_MASK_WL_DSS_COUNT_OUT 0xfffff\n#define BIT_WL_DSS_COUNT_OUT(x)                                                \\\n\t(((x) & BIT_MASK_WL_DSS_COUNT_OUT) << BIT_SHIFT_WL_DSS_COUNT_OUT)\n#define BITS_WL_DSS_COUNT_OUT                                                  \\\n\t(BIT_MASK_WL_DSS_COUNT_OUT << BIT_SHIFT_WL_DSS_COUNT_OUT)\n#define BIT_CLEAR_WL_DSS_COUNT_OUT(x) ((x) & (~BITS_WL_DSS_COUNT_OUT))\n#define BIT_GET_WL_DSS_COUNT_OUT(x)                                            \\\n\t(((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT) & BIT_MASK_WL_DSS_COUNT_OUT)\n#define BIT_SET_WL_DSS_COUNT_OUT(x, v)                                         \\\n\t(BIT_CLEAR_WL_DSS_COUNT_OUT(x) | BIT_WL_DSS_COUNT_OUT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_TIMEOUT_INTERRUPT2_MASK BIT(31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_PSTIMER_2_MSK BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_TIMEOUT_INTERRUTP1_MASK BIT(30)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_PSTIMER_1_MSK BIT(30)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_PSTIMEOUT_MSK BIT(29)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_PSTIMER_0_MSK BIT(29)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_GTINT4_MSK BIT(28)\n#define BIT_GTINT4 BIT(28)\n#define BIT_GTINT3_MSK BIT(27)\n#define BIT_GTINT3 BIT(27)\n#define BIT_TXBCN0ERR_MSK BIT(26)\n#define BIT_TXBCN0ERR BIT(26)\n#define BIT_TXBCN0OK_MSK BIT(25)\n#define BIT_TXBCN0OK BIT(25)\n#define BIT_TSF_BIT32_TOGGLE_MSK BIT(24)\n#define BIT_TSF_BIT32_TOGGLE BIT(24)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_TXDMA_START_INT_MSK BIT(23)\n#define BIT_TXDMA_STOP_INT_MSK BIT(22)\n#define BIT_HISR7_IND_MSK BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_BCNDMAINT0_MSK BIT(20)\n#define BIT_BCNDMAINT0 BIT(20)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_HISR6_IND_MSK BIT(19)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_HISR5_MSK BIT(18)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_HISR5_IND_MSK BIT(18)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_HISR4_MSK BIT(17)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_HISR4_IND_MSK BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_BCNDERR0_MSK BIT(16)\n#define BIT_BCNDERR0 BIT(16)\n#define BIT_HSISR_IND_ON_INT_MSK BIT(15)\n#define BIT_HSISR_IND_ON_INT BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_BCNDMAINT_E_MSK BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_HISR3_IND_INT_MSK BIT(14)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_HISR3_IND_MSK BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_HISR2_IND_INT_MSK BIT(13)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_HISR2_IND_MSK BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_CTWEND_MSK BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_HISR1_IND_MSK BIT(11)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_HISR1_IND_INT_MSK BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_C2HCMD_MSK BIT(10)\n#define BIT_C2HCMD BIT(10)\n#define BIT_CPWM2_MSK BIT(9)\n#define BIT_CPWM2 BIT(9)\n#define BIT_CPWM_MSK BIT(8)\n#define BIT_CPWM BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_HIGHDOK_MSK BIT(7)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_TXDMAOK_CHANNEL15_MSK BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_MGTDOK_MSK BIT(6)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_TXDMAOK_CHANNEL14_MSK BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_BKDOK_MSK BIT(5)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_TXDMAOK_CHANNEL3_MSK BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_BEDOK_MSK BIT(4)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_TXDMAOK_CHANNEL2_MSK BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_VIDOK_MSK BIT(3)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_TXDMAOK_CHANNEL1_MSK BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_VODOK_MSK BIT(2)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_TXDMAOK_CHANNEL0_MSK BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR0\t\t\t\t(Offset 0x00B0) */\n\n#define BIT_RDU_MSK BIT(1)\n#define BIT_RDU BIT(1)\n#define BIT_RXOK_MSK BIT(0)\n#define BIT_RXOK BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HISR0\t\t\t\t(Offset 0x00B4) */\n\n#define BIT_PSTIMEOUT2 BIT(31)\n#define BIT_PSTIMEOUT1 BIT(30)\n#define BIT_PSTIMEOUT BIT(29)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HISR0\t\t\t\t(Offset 0x00B4) */\n\n#define BIT_HISR5_IND_INT BIT(18)\n#define BIT_HISR4_IND_INT BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HISR0\t\t\t\t(Offset 0x00B4) */\n\n#define BIT_BCNDMAINT_E BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_HISR0\t\t\t\t(Offset 0x00B4) */\n\n#define BIT_HISR3_IND_INT BIT(14)\n#define BIT_HISR2_IND_INT BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HISR0\t\t\t\t(Offset 0x00B4) */\n\n#define BIT_CTWEND BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HISR0\t\t\t\t(Offset 0x00B4) */\n\n#define BIT_HISR1_IND_INT BIT(11)\n#define BIT_HIGHDOK BIT(7)\n#define BIT_MGTDOK BIT(6)\n#define BIT_BKDOK BIT(5)\n#define BIT_BEDOK BIT(4)\n#define BIT_VIDOK BIT(3)\n#define BIT_VODOK BIT(2)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_PRETXERR_HANDLE_MSK BIT(31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_PRE_TX_ERR_INT_MSK BIT(31)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_BTON_STS_UPDATE_INT BIT(29)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_BTON_STS_UPDATE_MSK BIT(29)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_BTON_STS_UPDATE_MASK BIT(29)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_MCU_ERR_MASK BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_BCNDMAINT7 BIT(27)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_BCNDMAINT7_MSK BIT(27)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_BCNDMAINT7__MSK BIT(27)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_BCNDMAINT6 BIT(26)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_BCNDMAINT6_MSK BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_BCNDMAINT6__MSK BIT(26)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_BCNDMAINT5 BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_BCNDMAINT5_MSK BIT(25)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_BCNDMAINT5__MSK BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_BCNDMAINT4 BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_BCNDMAINT4_MSK BIT(24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_BCNDMAINT4__MSK BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_BCNDMAINT3_MSK BIT(23)\n#define BIT_BCNDMAINT3 BIT(23)\n#define BIT_BCNDMAINT2_MSK BIT(22)\n#define BIT_BCNDMAINT2 BIT(22)\n#define BIT_BCNDMAINT1_MSK BIT(21)\n#define BIT_BCNDMAINT1 BIT(21)\n#define BIT_BCNDERR7_MSK BIT(20)\n#define BIT_BCNDERR7 BIT(20)\n#define BIT_BCNDERR6_MSK BIT(19)\n#define BIT_BCNDERR6 BIT(19)\n#define BIT_BCNDERR5_MSK BIT(18)\n#define BIT_BCNDERR5 BIT(18)\n#define BIT_BCNDERR4_MSK BIT(17)\n#define BIT_BCNDERR4 BIT(17)\n#define BIT_BCNDERR3_MSK BIT(16)\n#define BIT_BCNDERR3 BIT(16)\n#define BIT_BCNDERR2_MSK BIT(15)\n#define BIT_BCNDERR2 BIT(15)\n#define BIT_BCNDERR1_MSK BIT(14)\n#define BIT_BCNDERR1 BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_ATIMEND_E_MSK BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_ATIMEND_MSK BIT(12)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_ATIMEND__MSK BIT(12)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_ATIMEND_E_V1_MSK BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_TXERR_MSK BIT(11)\n#define BIT_TXERR_INT BIT(11)\n#define BIT_RXERR_MSK BIT(10)\n#define BIT_RXERR_INT BIT(10)\n#define BIT_TXFOVW_MSK BIT(9)\n#define BIT_TXFOVW BIT(9)\n#define BIT_FOVW_MSK BIT(8)\n#define BIT_FOVW BIT(8)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_CPU_MGQ_EARLY_INT_MSK BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_CPU_MGQ_TXDONE_MSK BIT(5)\n#define BIT_CPU_MGQ_TXDONE BIT(5)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_PS_TIMER_C_MSK BIT(4)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_PSTIMER_5_MSK BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_PS_TIMER_B_MSK BIT(3)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_PSTIMER_4_MSK BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_PS_TIMER_A_MSK BIT(2)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_PSTIMER_3_MSK BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_CPUMGQ_TX_TIMER_MSK BIT(1)\n#define BIT_CPUMGQ_TX_TIMER BIT(1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR1\t\t\t\t(Offset 0x00B8) */\n\n#define BIT_BB_STOPRX_INT_MSK BIT(0)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HISR1\t\t\t\t(Offset 0x00BC) */\n\n#define BIT_PRETXERR_HANDLE_INT BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HISR1\t\t\t\t(Offset 0x00BC) */\n\n#define BIT_MCU_ERR BIT(28)\n#define BIT_ATIMEND_E BIT(13)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_HISR1\t\t\t\t(Offset 0x00BC) */\n\n#define BIT_ATIMEND_E_V1_INT BIT(12)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HISR1\t\t\t\t(Offset 0x00BC) */\n\n#define BIT_PS_TIMER_C BIT(4)\n#define BIT_PS_TIMER_B BIT(3)\n#define BIT_PS_TIMER_A BIT(2)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HISR1\t\t\t\t(Offset 0x00BC) */\n\n#define BIT_SHIFT_SYS_PINMUX_EN 0\n#define BIT_MASK_SYS_PINMUX_EN 0xfffffff\n#define BIT_SYS_PINMUX_EN(x)                                                   \\\n\t(((x) & BIT_MASK_SYS_PINMUX_EN) << BIT_SHIFT_SYS_PINMUX_EN)\n#define BITS_SYS_PINMUX_EN (BIT_MASK_SYS_PINMUX_EN << BIT_SHIFT_SYS_PINMUX_EN)\n#define BIT_CLEAR_SYS_PINMUX_EN(x) ((x) & (~BITS_SYS_PINMUX_EN))\n#define BIT_GET_SYS_PINMUX_EN(x)                                               \\\n\t(((x) >> BIT_SHIFT_SYS_PINMUX_EN) & BIT_MASK_SYS_PINMUX_EN)\n#define BIT_SET_SYS_PINMUX_EN(x, v)                                            \\\n\t(BIT_CLEAR_SYS_PINMUX_EN(x) | BIT_SYS_PINMUX_EN(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SDIO_ERR_RPT\t\t\t(Offset 0x102500C0) */\n\n#define BIT_HR_FF_OVF BIT(6)\n#define BIT_HR_FF_UDN BIT(5)\n#define BIT_TXDMA_BUSY_ERR BIT(4)\n#define BIT_TXDMA_VLD_ERR BIT(3)\n#define BIT_QSEL_UNKNOWN_ERR BIT(2)\n#define BIT_QSEL_MIS_ERR BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DBG_PORT_SEL\t\t\t(Offset 0x00C0) */\n\n#define BIT_SHIFT_DEBUG_ST 0\n#define BIT_MASK_DEBUG_ST 0xffffffffL\n#define BIT_DEBUG_ST(x) (((x) & BIT_MASK_DEBUG_ST) << BIT_SHIFT_DEBUG_ST)\n#define BITS_DEBUG_ST (BIT_MASK_DEBUG_ST << BIT_SHIFT_DEBUG_ST)\n#define BIT_CLEAR_DEBUG_ST(x) ((x) & (~BITS_DEBUG_ST))\n#define BIT_GET_DEBUG_ST(x) (((x) >> BIT_SHIFT_DEBUG_ST) & BIT_MASK_DEBUG_ST)\n#define BIT_SET_DEBUG_ST(x, v) (BIT_CLEAR_DEBUG_ST(x) | BIT_DEBUG_ST(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_DIOERR_RPT\t\t\t(Offset 0x102500C0) */\n\n#define BIT_SDIO_PAGE_ERR BIT(0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SDIO_ERR_RPT\t\t\t(Offset 0x102500C0) */\n\n#define BIT_SDIO_OVERRD_ERR BIT(0)\n\n#define BIT_SHIFT_SDIO_DATA_REPLY_TIME 0\n#define BIT_MASK_SDIO_DATA_REPLY_TIME 0x7\n#define BIT_SDIO_DATA_REPLY_TIME(x)                                            \\\n\t(((x) & BIT_MASK_SDIO_DATA_REPLY_TIME)                                 \\\n\t << BIT_SHIFT_SDIO_DATA_REPLY_TIME)\n#define BITS_SDIO_DATA_REPLY_TIME                                              \\\n\t(BIT_MASK_SDIO_DATA_REPLY_TIME << BIT_SHIFT_SDIO_DATA_REPLY_TIME)\n#define BIT_CLEAR_SDIO_DATA_REPLY_TIME(x) ((x) & (~BITS_SDIO_DATA_REPLY_TIME))\n#define BIT_GET_SDIO_DATA_REPLY_TIME(x)                                        \\\n\t(((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME) &                             \\\n\t BIT_MASK_SDIO_DATA_REPLY_TIME)\n#define BIT_SET_SDIO_DATA_REPLY_TIME(x, v)                                     \\\n\t(BIT_CLEAR_SDIO_DATA_REPLY_TIME(x) | BIT_SDIO_DATA_REPLY_TIME(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_CMD_ERRCNT\t\t\t(Offset 0x102500C2) */\n\n#define BIT_SHIFT_CMD_CRC_ERR_CNT 0\n#define BIT_MASK_CMD_CRC_ERR_CNT 0xff\n#define BIT_CMD_CRC_ERR_CNT(x)                                                 \\\n\t(((x) & BIT_MASK_CMD_CRC_ERR_CNT) << BIT_SHIFT_CMD_CRC_ERR_CNT)\n#define BITS_CMD_CRC_ERR_CNT                                                   \\\n\t(BIT_MASK_CMD_CRC_ERR_CNT << BIT_SHIFT_CMD_CRC_ERR_CNT)\n#define BIT_CLEAR_CMD_CRC_ERR_CNT(x) ((x) & (~BITS_CMD_CRC_ERR_CNT))\n#define BIT_GET_CMD_CRC_ERR_CNT(x)                                             \\\n\t(((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT) & BIT_MASK_CMD_CRC_ERR_CNT)\n#define BIT_SET_CMD_CRC_ERR_CNT(x, v)                                          \\\n\t(BIT_CLEAR_CMD_CRC_ERR_CNT(x) | BIT_CMD_CRC_ERR_CNT(v))\n\n/* 2 REG_SDIO_DATA_ERRCNT\t\t\t(Offset 0x102500C3) */\n\n#define BIT_SHIFT_DATA_CRC_ERR_CNT 0\n#define BIT_MASK_DATA_CRC_ERR_CNT 0xff\n#define BIT_DATA_CRC_ERR_CNT(x)                                                \\\n\t(((x) & BIT_MASK_DATA_CRC_ERR_CNT) << BIT_SHIFT_DATA_CRC_ERR_CNT)\n#define BITS_DATA_CRC_ERR_CNT                                                  \\\n\t(BIT_MASK_DATA_CRC_ERR_CNT << BIT_SHIFT_DATA_CRC_ERR_CNT)\n#define BIT_CLEAR_DATA_CRC_ERR_CNT(x) ((x) & (~BITS_DATA_CRC_ERR_CNT))\n#define BIT_GET_DATA_CRC_ERR_CNT(x)                                            \\\n\t(((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT) & BIT_MASK_DATA_CRC_ERR_CNT)\n#define BIT_SET_DATA_CRC_ERR_CNT(x, v)                                         \\\n\t(BIT_CLEAR_DATA_CRC_ERR_CNT(x) | BIT_DATA_CRC_ERR_CNT(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_MAC_SOP BIT(25)\n#define BIT_LDO11_ST_EXT BIT(24)\n#define BIT_ANTSELB_S2 BIT(23)\n#define BIT_ANTSELB_S1 BIT(22)\n#define BIT_ANTSEL_S3 BIT(21)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_USB3_USB2_TRANSITION BIT(20)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_ANTSEL_S2 BIT(20)\n#define BIT_ANTSEL_S1 BIT(19)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_SHIFT_USB23_SW_MODE_V1 18\n#define BIT_MASK_USB23_SW_MODE_V1 0x3\n#define BIT_USB23_SW_MODE_V1(x)                                                \\\n\t(((x) & BIT_MASK_USB23_SW_MODE_V1) << BIT_SHIFT_USB23_SW_MODE_V1)\n#define BITS_USB23_SW_MODE_V1                                                  \\\n\t(BIT_MASK_USB23_SW_MODE_V1 << BIT_SHIFT_USB23_SW_MODE_V1)\n#define BIT_CLEAR_USB23_SW_MODE_V1(x) ((x) & (~BITS_USB23_SW_MODE_V1))\n#define BIT_GET_USB23_SW_MODE_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_USB23_SW_MODE_V1) & BIT_MASK_USB23_SW_MODE_V1)\n#define BIT_SET_USB23_SW_MODE_V1(x, v)                                         \\\n\t(BIT_CLEAR_USB23_SW_MODE_V1(x) | BIT_USB23_SW_MODE_V1(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_FCSN_PU BIT(18)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_NO_PDN_CHIPOFF_V1 BIT(17)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_KEEP_PAD BIT(17)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_RSM_EN_V1 BIT(16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_PAD_ALD_SKP BIT(16)\n#define BIT_PAD_A_ANTSEL_E BIT(11)\n#define BIT_PAD_A_ANTSELB_E BIT(10)\n#define BIT_PAD_A_ANTSEL_O BIT(9)\n#define BIT_PAD_A_ANTSELB_O BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_LD_B12V_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_B15V_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_EESK_IOSEL BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_EECS_IOSEL_V1 BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_EESK_DATA_O BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_EECS_DATA_O_V1 BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_EESK_DATA_I BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_EECS_DATA_I_V1 BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_EECS_IOSEL BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_EESK_IOSEL_V1 BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_EECS_DATA_O BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_EESK_DATA_O_V1 BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_EECS_DATA_I BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PAD_CTRL2\t\t\t\t(Offset 0x00C4) */\n\n#define BIT_EESK_DATA_I_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_CMD_ERR_CONTENT\t\t(Offset 0x102500C4) */\n\n#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT 0\n#define BIT_MASK_SDIO_CMD_ERR_CONTENT 0xffffffffffL\n#define BIT_SDIO_CMD_ERR_CONTENT(x)                                            \\\n\t(((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT)                                 \\\n\t << BIT_SHIFT_SDIO_CMD_ERR_CONTENT)\n#define BITS_SDIO_CMD_ERR_CONTENT                                              \\\n\t(BIT_MASK_SDIO_CMD_ERR_CONTENT << BIT_SHIFT_SDIO_CMD_ERR_CONTENT)\n#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT(x) ((x) & (~BITS_SDIO_CMD_ERR_CONTENT))\n#define BIT_GET_SDIO_CMD_ERR_CONTENT(x)                                        \\\n\t(((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT) &                             \\\n\t BIT_MASK_SDIO_CMD_ERR_CONTENT)\n#define BIT_SET_SDIO_CMD_ERR_CONTENT(x, v)                                     \\\n\t(BIT_CLEAR_SDIO_CMD_ERR_CONTENT(x) | BIT_SDIO_CMD_ERR_CONTENT(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_MEM_RMC\t\t\t\t(Offset 0x00C8) */\n\n#define BIT_SHIFT_MEM_RME_WL_V2 4\n#define BIT_MASK_MEM_RME_WL_V2 0x3f\n#define BIT_MEM_RME_WL_V2(x)                                                   \\\n\t(((x) & BIT_MASK_MEM_RME_WL_V2) << BIT_SHIFT_MEM_RME_WL_V2)\n#define BITS_MEM_RME_WL_V2 (BIT_MASK_MEM_RME_WL_V2 << BIT_SHIFT_MEM_RME_WL_V2)\n#define BIT_CLEAR_MEM_RME_WL_V2(x) ((x) & (~BITS_MEM_RME_WL_V2))\n#define BIT_GET_MEM_RME_WL_V2(x)                                               \\\n\t(((x) >> BIT_SHIFT_MEM_RME_WL_V2) & BIT_MASK_MEM_RME_WL_V2)\n#define BIT_SET_MEM_RME_WL_V2(x, v)                                            \\\n\t(BIT_CLEAR_MEM_RME_WL_V2(x) | BIT_MEM_RME_WL_V2(v))\n\n#define BIT_SHIFT_MEM_RME_HCI_V2 0\n#define BIT_MASK_MEM_RME_HCI_V2 0x1f\n#define BIT_MEM_RME_HCI_V2(x)                                                  \\\n\t(((x) & BIT_MASK_MEM_RME_HCI_V2) << BIT_SHIFT_MEM_RME_HCI_V2)\n#define BITS_MEM_RME_HCI_V2                                                    \\\n\t(BIT_MASK_MEM_RME_HCI_V2 << BIT_SHIFT_MEM_RME_HCI_V2)\n#define BIT_CLEAR_MEM_RME_HCI_V2(x) ((x) & (~BITS_MEM_RME_HCI_V2))\n#define BIT_GET_MEM_RME_HCI_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_MEM_RME_HCI_V2) & BIT_MASK_MEM_RME_HCI_V2)\n#define BIT_SET_MEM_RME_HCI_V2(x, v)                                           \\\n\t(BIT_CLEAR_MEM_RME_HCI_V2(x) | BIT_MEM_RME_HCI_V2(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_CRC_ERR_IDX\t\t\t(Offset 0x102500C9) */\n\n#define BIT_D3_CRC_ERR BIT(4)\n#define BIT_D2_CRC_ERR BIT(3)\n#define BIT_D1_CRC_ERR BIT(2)\n#define BIT_D0_CRC_ERR BIT(1)\n#define BIT_CMD_CRC_ERR BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_DATA_CRC\t\t\t(Offset 0x102500CA) */\n\n#define BIT_SHIFT_SDIO_DATA_CRC 0\n#define BIT_MASK_SDIO_DATA_CRC 0xffff\n#define BIT_SDIO_DATA_CRC(x)                                                   \\\n\t(((x) & BIT_MASK_SDIO_DATA_CRC) << BIT_SHIFT_SDIO_DATA_CRC)\n#define BITS_SDIO_DATA_CRC (BIT_MASK_SDIO_DATA_CRC << BIT_SHIFT_SDIO_DATA_CRC)\n#define BIT_CLEAR_SDIO_DATA_CRC(x) ((x) & (~BITS_SDIO_DATA_CRC))\n#define BIT_GET_SDIO_DATA_CRC(x)                                               \\\n\t(((x) >> BIT_SHIFT_SDIO_DATA_CRC) & BIT_MASK_SDIO_DATA_CRC)\n#define BIT_SET_SDIO_DATA_CRC(x, v)                                            \\\n\t(BIT_CLEAR_SDIO_DATA_CRC(x) | BIT_SDIO_DATA_CRC(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PMC_DBG_CTRL2\t\t\t(Offset 0x00CC) */\n\n#define BIT_SHIFT_EFUSE_BURN_GNT 24\n#define BIT_MASK_EFUSE_BURN_GNT 0xff\n#define BIT_EFUSE_BURN_GNT(x)                                                  \\\n\t(((x) & BIT_MASK_EFUSE_BURN_GNT) << BIT_SHIFT_EFUSE_BURN_GNT)\n#define BITS_EFUSE_BURN_GNT                                                    \\\n\t(BIT_MASK_EFUSE_BURN_GNT << BIT_SHIFT_EFUSE_BURN_GNT)\n#define BIT_CLEAR_EFUSE_BURN_GNT(x) ((x) & (~BITS_EFUSE_BURN_GNT))\n#define BIT_GET_EFUSE_BURN_GNT(x)                                              \\\n\t(((x) >> BIT_SHIFT_EFUSE_BURN_GNT) & BIT_MASK_EFUSE_BURN_GNT)\n#define BIT_SET_EFUSE_BURN_GNT(x, v)                                           \\\n\t(BIT_CLEAR_EFUSE_BURN_GNT(x) | BIT_EFUSE_BURN_GNT(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PMC_DBG_CTRL2\t\t\t(Offset 0x00CC) */\n\n#define BIT_SHIFT_EFUSE_PG_PWD 24\n#define BIT_MASK_EFUSE_PG_PWD 0xff\n#define BIT_EFUSE_PG_PWD(x)                                                    \\\n\t(((x) & BIT_MASK_EFUSE_PG_PWD) << BIT_SHIFT_EFUSE_PG_PWD)\n#define BITS_EFUSE_PG_PWD (BIT_MASK_EFUSE_PG_PWD << BIT_SHIFT_EFUSE_PG_PWD)\n#define BIT_CLEAR_EFUSE_PG_PWD(x) ((x) & (~BITS_EFUSE_PG_PWD))\n#define BIT_GET_EFUSE_PG_PWD(x)                                                \\\n\t(((x) >> BIT_SHIFT_EFUSE_PG_PWD) & BIT_MASK_EFUSE_PG_PWD)\n#define BIT_SET_EFUSE_PG_PWD(x, v)                                             \\\n\t(BIT_CLEAR_EFUSE_PG_PWD(x) | BIT_EFUSE_PG_PWD(v))\n\n#define BIT_DBG_READ_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PMC_DBG_CTRL2\t\t\t(Offset 0x00CC) */\n\n#define BIT_STOP_WL_PMC BIT(9)\n#define BIT_STOP_SYM_PMC BIT(8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PMC_DBG_CTRL2\t\t\t(Offset 0x00CC) */\n\n#define BIT_SHIFT_EDATA1_V1 8\n#define BIT_MASK_EDATA1_V1 0xff\n#define BIT_EDATA1_V1(x) (((x) & BIT_MASK_EDATA1_V1) << BIT_SHIFT_EDATA1_V1)\n#define BITS_EDATA1_V1 (BIT_MASK_EDATA1_V1 << BIT_SHIFT_EDATA1_V1)\n#define BIT_CLEAR_EDATA1_V1(x) ((x) & (~BITS_EDATA1_V1))\n#define BIT_GET_EDATA1_V1(x) (((x) >> BIT_SHIFT_EDATA1_V1) & BIT_MASK_EDATA1_V1)\n#define BIT_SET_EDATA1_V1(x, v) (BIT_CLEAR_EDATA1_V1(x) | BIT_EDATA1_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PMC_DBG_CTRL2\t\t\t(Offset 0x00CC) */\n\n#define BIT_BT_ACCESS_WL_PAGE0 BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PMC_DBG_CTRL2\t\t\t(Offset 0x00CC) */\n\n#define BIT_REG_RST_WLPMC BIT(5)\n#define BIT_REG_RST_PD12N BIT(4)\n#define BIT_SYSON_DIS_WLREG_WRMSK BIT(3)\n#define BIT_SYSON_DIS_PMCREG_WRMSK BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TRANS_FIFO_STATUS\t\t(Offset 0x102500CC) */\n\n#define BIT_TRANS_FIFO_UNDERFLOW BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PMC_DBG_CTRL2\t\t\t(Offset 0x00CC) */\n\n#define BIT_SHIFT_SYSON_REG_ARB 0\n#define BIT_MASK_SYSON_REG_ARB 0x3\n#define BIT_SYSON_REG_ARB(x)                                                   \\\n\t(((x) & BIT_MASK_SYSON_REG_ARB) << BIT_SHIFT_SYSON_REG_ARB)\n#define BITS_SYSON_REG_ARB (BIT_MASK_SYSON_REG_ARB << BIT_SHIFT_SYSON_REG_ARB)\n#define BIT_CLEAR_SYSON_REG_ARB(x) ((x) & (~BITS_SYSON_REG_ARB))\n#define BIT_GET_SYSON_REG_ARB(x)                                               \\\n\t(((x) >> BIT_SHIFT_SYSON_REG_ARB) & BIT_MASK_SYSON_REG_ARB)\n#define BIT_SET_SYSON_REG_ARB(x, v)                                            \\\n\t(BIT_CLEAR_SYSON_REG_ARB(x) | BIT_SYSON_REG_ARB(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SDIO_TRANS_FIFO_STATUS\t\t(Offset 0x102500CC) */\n\n#define BIT_TRANS_FIFO_OVERFLOW BIT(0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PMC_DBG_CTRL2\t\t\t(Offset 0x00CC) */\n\n#define BIT_SHIFT_EDATA0_V1 0\n#define BIT_MASK_EDATA0_V1 0xff\n#define BIT_EDATA0_V1(x) (((x) & BIT_MASK_EDATA0_V1) << BIT_SHIFT_EDATA0_V1)\n#define BITS_EDATA0_V1 (BIT_MASK_EDATA0_V1 << BIT_SHIFT_EDATA0_V1)\n#define BIT_CLEAR_EDATA0_V1(x) ((x) & (~BITS_EDATA0_V1))\n#define BIT_GET_EDATA0_V1(x) (((x) >> BIT_SHIFT_EDATA0_V1) & BIT_MASK_EDATA0_V1)\n#define BIT_SET_EDATA0_V1(x, v) (BIT_CLEAR_EDATA0_V1(x) | BIT_EDATA0_V1(v))\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_SCAN_PLL_BYPASS BIT(30)\n#define BIT_DRF_BIST_FAIL_V1 BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_BIST_USB_DIS BIT(27)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_DRF_BIST_READY_V1 BIT(27)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_BIST_PCI_DIS BIT(26)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_BIST_FAIL_V1 BIT(26)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_BIST_BT_DIS BIT(25)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_BIST_READY_V1 BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_BIST_WL_DIS BIT(24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_BIST_START_PAUSE_V1 BIT(24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_SHIFT_BIST_RPT_SEL_V1 20\n#define BIT_MASK_BIST_RPT_SEL_V1 0xf\n#define BIT_BIST_RPT_SEL_V1(x)                                                 \\\n\t(((x) & BIT_MASK_BIST_RPT_SEL_V1) << BIT_SHIFT_BIST_RPT_SEL_V1)\n#define BITS_BIST_RPT_SEL_V1                                                   \\\n\t(BIT_MASK_BIST_RPT_SEL_V1 << BIT_SHIFT_BIST_RPT_SEL_V1)\n#define BIT_CLEAR_BIST_RPT_SEL_V1(x) ((x) & (~BITS_BIST_RPT_SEL_V1))\n#define BIT_GET_BIST_RPT_SEL_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_BIST_RPT_SEL_V1) & BIT_MASK_BIST_RPT_SEL_V1)\n#define BIT_SET_BIST_RPT_SEL_V1(x, v)                                          \\\n\t(BIT_CLEAR_BIST_RPT_SEL_V1(x) | BIT_BIST_RPT_SEL_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_SHIFT_BIST_RPT_SEL 16\n#define BIT_MASK_BIST_RPT_SEL 0xf\n#define BIT_BIST_RPT_SEL(x)                                                    \\\n\t(((x) & BIT_MASK_BIST_RPT_SEL) << BIT_SHIFT_BIST_RPT_SEL)\n#define BITS_BIST_RPT_SEL (BIT_MASK_BIST_RPT_SEL << BIT_SHIFT_BIST_RPT_SEL)\n#define BIT_CLEAR_BIST_RPT_SEL(x) ((x) & (~BITS_BIST_RPT_SEL))\n#define BIT_GET_BIST_RPT_SEL(x)                                                \\\n\t(((x) >> BIT_SHIFT_BIST_RPT_SEL) & BIT_MASK_BIST_RPT_SEL)\n#define BIT_SET_BIST_RPT_SEL(x, v)                                             \\\n\t(BIT_CLEAR_BIST_RPT_SEL(x) | BIT_BIST_RPT_SEL(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_SHIFT_MBIST_RSTNI 8\n#define BIT_MASK_MBIST_RSTNI 0x3ff\n#define BIT_MBIST_RSTNI(x)                                                     \\\n\t(((x) & BIT_MASK_MBIST_RSTNI) << BIT_SHIFT_MBIST_RSTNI)\n#define BITS_MBIST_RSTNI (BIT_MASK_MBIST_RSTNI << BIT_SHIFT_MBIST_RSTNI)\n#define BIT_CLEAR_MBIST_RSTNI(x) ((x) & (~BITS_MBIST_RSTNI))\n#define BIT_GET_MBIST_RSTNI(x)                                                 \\\n\t(((x) >> BIT_SHIFT_MBIST_RSTNI) & BIT_MASK_MBIST_RSTNI)\n#define BIT_SET_MBIST_RSTNI(x, v)                                              \\\n\t(BIT_CLEAR_MBIST_RSTNI(x) | BIT_MBIST_RSTNI(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_BISD_MODE BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_BIST_RESUME_PS_V1 BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_BIST_RESUME_PS BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_BIST_RESUME_V1 BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_BIST_RESUME BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_BIST_DRF BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_BIST_NORMAL BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_SHIFT_BIST_MODE 2\n#define BIT_MASK_BIST_MODE 0x3\n#define BIT_BIST_MODE(x) (((x) & BIT_MASK_BIST_MODE) << BIT_SHIFT_BIST_MODE)\n#define BITS_BIST_MODE (BIT_MASK_BIST_MODE << BIT_SHIFT_BIST_MODE)\n#define BIT_CLEAR_BIST_MODE(x) ((x) & (~BITS_BIST_MODE))\n#define BIT_GET_BIST_MODE(x) (((x) >> BIT_SHIFT_BIST_MODE) & BIT_MASK_BIST_MODE)\n#define BIT_SET_BIST_MODE(x, v) (BIT_CLEAR_BIST_MODE(x) | BIT_BIST_MODE(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_BIST_RSTN BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_SYM_HCI_TADMA_ALLOW BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_BIST_CLK_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_BIST_CTRL\t\t\t\t(Offset 0x00D0) */\n\n#define BIT_SYM_FW_CTL_HCI_TXDMA_EN BIT(0)\n\n#define BIT_SHIFT_TDE_H2C_RD_ADDR 0\n#define BIT_MASK_TDE_H2C_RD_ADDR 0x3ffff\n#define BIT_TDE_H2C_RD_ADDR(x)                                                 \\\n\t(((x) & BIT_MASK_TDE_H2C_RD_ADDR) << BIT_SHIFT_TDE_H2C_RD_ADDR)\n#define BITS_TDE_H2C_RD_ADDR                                                   \\\n\t(BIT_MASK_TDE_H2C_RD_ADDR << BIT_SHIFT_TDE_H2C_RD_ADDR)\n#define BIT_CLEAR_TDE_H2C_RD_ADDR(x) ((x) & (~BITS_TDE_H2C_RD_ADDR))\n#define BIT_GET_TDE_H2C_RD_ADDR(x)                                             \\\n\t(((x) >> BIT_SHIFT_TDE_H2C_RD_ADDR) & BIT_MASK_TDE_H2C_RD_ADDR)\n#define BIT_SET_TDE_H2C_RD_ADDR(x, v)                                          \\\n\t(BIT_CLEAR_TDE_H2C_RD_ADDR(x) | BIT_TDE_H2C_RD_ADDR(v))\n\n#define BIT_SHIFT_TDE_H2C_WR_ADDR 0\n#define BIT_MASK_TDE_H2C_WR_ADDR 0x3ffff\n#define BIT_TDE_H2C_WR_ADDR(x)                                                 \\\n\t(((x) & BIT_MASK_TDE_H2C_WR_ADDR) << BIT_SHIFT_TDE_H2C_WR_ADDR)\n#define BITS_TDE_H2C_WR_ADDR                                                   \\\n\t(BIT_MASK_TDE_H2C_WR_ADDR << BIT_SHIFT_TDE_H2C_WR_ADDR)\n#define BIT_CLEAR_TDE_H2C_WR_ADDR(x) ((x) & (~BITS_TDE_H2C_WR_ADDR))\n#define BIT_GET_TDE_H2C_WR_ADDR(x)                                             \\\n\t(((x) >> BIT_SHIFT_TDE_H2C_WR_ADDR) & BIT_MASK_TDE_H2C_WR_ADDR)\n#define BIT_SET_TDE_H2C_WR_ADDR(x, v)                                          \\\n\t(BIT_CLEAR_TDE_H2C_WR_ADDR(x) | BIT_TDE_H2C_WR_ADDR(v))\n\n#define BIT_SHIFT_BCAM_CTRL 0\n#define BIT_MASK_BCAM_CTRL 0xffffffffL\n#define BIT_BCAM_CTRL(x) (((x) & BIT_MASK_BCAM_CTRL) << BIT_SHIFT_BCAM_CTRL)\n#define BITS_BCAM_CTRL (BIT_MASK_BCAM_CTRL << BIT_SHIFT_BCAM_CTRL)\n#define BIT_CLEAR_BCAM_CTRL(x) ((x) & (~BITS_BCAM_CTRL))\n#define BIT_GET_BCAM_CTRL(x) (((x) >> BIT_SHIFT_BCAM_CTRL) & BIT_MASK_BCAM_CTRL)\n#define BIT_SET_BCAM_CTRL(x, v) (BIT_CLEAR_BCAM_CTRL(x) | BIT_BCAM_CTRL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BIST_RPT\t\t\t\t(Offset 0x00D4) */\n\n#define BIT_SHIFT_MBIST_REPORT 0\n#define BIT_MASK_MBIST_REPORT 0xffffffffL\n#define BIT_MBIST_REPORT(x)                                                    \\\n\t(((x) & BIT_MASK_MBIST_REPORT) << BIT_SHIFT_MBIST_REPORT)\n#define BITS_MBIST_REPORT (BIT_MASK_MBIST_REPORT << BIT_SHIFT_MBIST_REPORT)\n#define BIT_CLEAR_MBIST_REPORT(x) ((x) & (~BITS_MBIST_REPORT))\n#define BIT_GET_MBIST_REPORT(x)                                                \\\n\t(((x) >> BIT_SHIFT_MBIST_REPORT) & BIT_MASK_MBIST_REPORT)\n#define BIT_SET_MBIST_REPORT(x, v)                                             \\\n\t(BIT_CLEAR_MBIST_REPORT(x) | BIT_MBIST_REPORT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_MEM_CTRL\t\t\t\t(Offset 0x00D8) */\n\n#define BIT_RMV_SIGN BIT(31)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MEM_CTRL\t\t\t\t(Offset 0x00D8) */\n\n#define BIT_UMEM_RME BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_MEM_CTRL\t\t\t\t(Offset 0x00D8) */\n\n#define BIT_RMV_2PRF1 BIT(29)\n#define BIT_RMV_2PRF0 BIT(28)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MEM_CTRL\t\t\t\t(Offset 0x00D8) */\n\n#define BIT_SHIFT_BT_SPRAM 28\n#define BIT_MASK_BT_SPRAM 0x3\n#define BIT_BT_SPRAM(x) (((x) & BIT_MASK_BT_SPRAM) << BIT_SHIFT_BT_SPRAM)\n#define BITS_BT_SPRAM (BIT_MASK_BT_SPRAM << BIT_SHIFT_BT_SPRAM)\n#define BIT_CLEAR_BT_SPRAM(x) ((x) & (~BITS_BT_SPRAM))\n#define BIT_GET_BT_SPRAM(x) (((x) >> BIT_SHIFT_BT_SPRAM) & BIT_MASK_BT_SPRAM)\n#define BIT_SET_BT_SPRAM(x, v) (BIT_CLEAR_BT_SPRAM(x) | BIT_BT_SPRAM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_MEM_CTRL\t\t\t\t(Offset 0x00D8) */\n\n#define BIT_RMV_1PRF1 BIT(27)\n#define BIT_RMV_1PRF0 BIT(26)\n#define BIT_RMV_1PSR BIT(25)\n#define BIT_RMV_ROM BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MEM_CTRL\t\t\t\t(Offset 0x00D8) */\n\n#define BIT_SHIFT_BT_ROM 24\n#define BIT_MASK_BT_ROM 0xf\n#define BIT_BT_ROM(x) (((x) & BIT_MASK_BT_ROM) << BIT_SHIFT_BT_ROM)\n#define BITS_BT_ROM (BIT_MASK_BT_ROM << BIT_SHIFT_BT_ROM)\n#define BIT_CLEAR_BT_ROM(x) ((x) & (~BITS_BT_ROM))\n#define BIT_GET_BT_ROM(x) (((x) >> BIT_SHIFT_BT_ROM) & BIT_MASK_BT_ROM)\n#define BIT_SET_BT_ROM(x, v) (BIT_CLEAR_BT_ROM(x) | BIT_BT_ROM(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MEM_CTRL\t\t\t\t(Offset 0x00D8) */\n\n#define BIT_MEM_RMV1_2PRF1 BIT(19)\n#define BIT_MEM_RMV1_2PRF0 BIT(18)\n#define BIT_MEM_RMV1_1PRF1 BIT(17)\n#define BIT_MEM_RMV1_1PRF0 BIT(16)\n#define BIT_MEM_RMV1_1PSR BIT(15)\n#define BIT_MEM_RMV1_ROM BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MEM_CTRL\t\t\t\t(Offset 0x00D8) */\n\n#define BIT_SHIFT_PCI_DPRAM 10\n#define BIT_MASK_PCI_DPRAM 0x3\n#define BIT_PCI_DPRAM(x) (((x) & BIT_MASK_PCI_DPRAM) << BIT_SHIFT_PCI_DPRAM)\n#define BITS_PCI_DPRAM (BIT_MASK_PCI_DPRAM << BIT_SHIFT_PCI_DPRAM)\n#define BIT_CLEAR_PCI_DPRAM(x) ((x) & (~BITS_PCI_DPRAM))\n#define BIT_GET_PCI_DPRAM(x) (((x) >> BIT_SHIFT_PCI_DPRAM) & BIT_MASK_PCI_DPRAM)\n#define BIT_SET_PCI_DPRAM(x, v) (BIT_CLEAR_PCI_DPRAM(x) | BIT_PCI_DPRAM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_MEM_CTRL\t\t\t\t(Offset 0x00D8) */\n\n#define BIT_SHIFT_MEM_RME_BT 8\n#define BIT_MASK_MEM_RME_BT 0xf\n#define BIT_MEM_RME_BT(x) (((x) & BIT_MASK_MEM_RME_BT) << BIT_SHIFT_MEM_RME_BT)\n#define BITS_MEM_RME_BT (BIT_MASK_MEM_RME_BT << BIT_SHIFT_MEM_RME_BT)\n#define BIT_CLEAR_MEM_RME_BT(x) ((x) & (~BITS_MEM_RME_BT))\n#define BIT_GET_MEM_RME_BT(x)                                                  \\\n\t(((x) >> BIT_SHIFT_MEM_RME_BT) & BIT_MASK_MEM_RME_BT)\n#define BIT_SET_MEM_RME_BT(x, v) (BIT_CLEAR_MEM_RME_BT(x) | BIT_MEM_RME_BT(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MEM_CTRL\t\t\t\t(Offset 0x00D8) */\n\n#define BIT_SHIFT_PCI_SPRAM 8\n#define BIT_MASK_PCI_SPRAM 0x3\n#define BIT_PCI_SPRAM(x) (((x) & BIT_MASK_PCI_SPRAM) << BIT_SHIFT_PCI_SPRAM)\n#define BITS_PCI_SPRAM (BIT_MASK_PCI_SPRAM << BIT_SHIFT_PCI_SPRAM)\n#define BIT_CLEAR_PCI_SPRAM(x) ((x) & (~BITS_PCI_SPRAM))\n#define BIT_GET_PCI_SPRAM(x) (((x) >> BIT_SHIFT_PCI_SPRAM) & BIT_MASK_PCI_SPRAM)\n#define BIT_SET_PCI_SPRAM(x, v) (BIT_CLEAR_PCI_SPRAM(x) | BIT_PCI_SPRAM(v))\n\n#define BIT_SHIFT_USB_SPRAM 6\n#define BIT_MASK_USB_SPRAM 0x3\n#define BIT_USB_SPRAM(x) (((x) & BIT_MASK_USB_SPRAM) << BIT_SHIFT_USB_SPRAM)\n#define BITS_USB_SPRAM (BIT_MASK_USB_SPRAM << BIT_SHIFT_USB_SPRAM)\n#define BIT_CLEAR_USB_SPRAM(x) ((x) & (~BITS_USB_SPRAM))\n#define BIT_GET_USB_SPRAM(x) (((x) >> BIT_SHIFT_USB_SPRAM) & BIT_MASK_USB_SPRAM)\n#define BIT_SET_USB_SPRAM(x, v) (BIT_CLEAR_USB_SPRAM(x) | BIT_USB_SPRAM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MEM_CTRL\t\t\t\t(Offset 0x00D8) */\n\n#define BIT_SHIFT_MEM_RME_WL 4\n#define BIT_MASK_MEM_RME_WL 0xf\n#define BIT_MEM_RME_WL(x) (((x) & BIT_MASK_MEM_RME_WL) << BIT_SHIFT_MEM_RME_WL)\n#define BITS_MEM_RME_WL (BIT_MASK_MEM_RME_WL << BIT_SHIFT_MEM_RME_WL)\n#define BIT_CLEAR_MEM_RME_WL(x) ((x) & (~BITS_MEM_RME_WL))\n#define BIT_GET_MEM_RME_WL(x)                                                  \\\n\t(((x) >> BIT_SHIFT_MEM_RME_WL) & BIT_MASK_MEM_RME_WL)\n#define BIT_SET_MEM_RME_WL(x, v) (BIT_CLEAR_MEM_RME_WL(x) | BIT_MEM_RME_WL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MEM_CTRL\t\t\t\t(Offset 0x00D8) */\n\n#define BIT_SHIFT_USB_SPRF 4\n#define BIT_MASK_USB_SPRF 0x3\n#define BIT_USB_SPRF(x) (((x) & BIT_MASK_USB_SPRF) << BIT_SHIFT_USB_SPRF)\n#define BITS_USB_SPRF (BIT_MASK_USB_SPRF << BIT_SHIFT_USB_SPRF)\n#define BIT_CLEAR_USB_SPRF(x) ((x) & (~BITS_USB_SPRF))\n#define BIT_GET_USB_SPRF(x) (((x) >> BIT_SHIFT_USB_SPRF) & BIT_MASK_USB_SPRF)\n#define BIT_SET_USB_SPRF(x, v) (BIT_CLEAR_USB_SPRF(x) | BIT_USB_SPRF(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MEM_CTRL\t\t\t\t(Offset 0x00D8) */\n\n#define BIT_SHIFT_MEM_RME_HCI 0\n#define BIT_MASK_MEM_RME_HCI 0xf\n#define BIT_MEM_RME_HCI(x)                                                     \\\n\t(((x) & BIT_MASK_MEM_RME_HCI) << BIT_SHIFT_MEM_RME_HCI)\n#define BITS_MEM_RME_HCI (BIT_MASK_MEM_RME_HCI << BIT_SHIFT_MEM_RME_HCI)\n#define BIT_CLEAR_MEM_RME_HCI(x) ((x) & (~BITS_MEM_RME_HCI))\n#define BIT_GET_MEM_RME_HCI(x)                                                 \\\n\t(((x) >> BIT_SHIFT_MEM_RME_HCI) & BIT_MASK_MEM_RME_HCI)\n#define BIT_SET_MEM_RME_HCI(x, v)                                              \\\n\t(BIT_CLEAR_MEM_RME_HCI(x) | BIT_MEM_RME_HCI(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MEM_CTRL\t\t\t\t(Offset 0x00D8) */\n\n#define BIT_SHIFT_MCU_ROM 0\n#define BIT_MASK_MCU_ROM 0xf\n#define BIT_MCU_ROM(x) (((x) & BIT_MASK_MCU_ROM) << BIT_SHIFT_MCU_ROM)\n#define BITS_MCU_ROM (BIT_MASK_MCU_ROM << BIT_SHIFT_MCU_ROM)\n#define BIT_CLEAR_MCU_ROM(x) ((x) & (~BITS_MCU_ROM))\n#define BIT_GET_MCU_ROM(x) (((x) >> BIT_SHIFT_MCU_ROM) & BIT_MASK_MCU_ROM)\n#define BIT_SET_MCU_ROM(x, v) (BIT_CLEAR_MCU_ROM(x) | BIT_MCU_ROM(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_MEM_CTRL\t\t\t\t(Offset 0x00D8) */\n\n#define BIT_SHIFT_BIST_ROM 0\n#define BIT_MASK_BIST_ROM 0xffffffffL\n#define BIT_BIST_ROM(x) (((x) & BIT_MASK_BIST_ROM) << BIT_SHIFT_BIST_ROM)\n#define BITS_BIST_ROM (BIT_MASK_BIST_ROM << BIT_SHIFT_BIST_ROM)\n#define BIT_CLEAR_BIST_ROM(x) ((x) & (~BITS_BIST_ROM))\n#define BIT_GET_BIST_ROM(x) (((x) >> BIT_SHIFT_BIST_ROM) & BIT_MASK_BIST_ROM)\n#define BIT_SET_BIST_ROM(x, v) (BIT_CLEAR_BIST_ROM(x) | BIT_BIST_ROM(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL8\t\t\t\t(Offset 0x00DC) */\n\n#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4 26\n#define BIT_MASK_BB_DBG_SEL_AFE_SDM_V4 0x7\n#define BIT_BB_DBG_SEL_AFE_SDM_V4(x)                                           \\\n\t(((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4)                                \\\n\t << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4)\n#define BITS_BB_DBG_SEL_AFE_SDM_V4                                             \\\n\t(BIT_MASK_BB_DBG_SEL_AFE_SDM_V4 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4)\n#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4(x) ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_V4))\n#define BIT_GET_BB_DBG_SEL_AFE_SDM_V4(x)                                       \\\n\t(((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4) &                            \\\n\t BIT_MASK_BB_DBG_SEL_AFE_SDM_V4)\n#define BIT_SET_BB_DBG_SEL_AFE_SDM_V4(x, v)                                    \\\n\t(BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4(x) | BIT_BB_DBG_SEL_AFE_SDM_V4(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL8\t\t\t\t(Offset 0x00DC) */\n\n#define BIT_SYN_AGPIO BIT(20)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYN_RFC_CTRL\t\t\t(Offset 0x00DC) */\n\n#define BIT_SHIFT_SYN_RF1_CTRL 8\n#define BIT_MASK_SYN_RF1_CTRL 0xff\n#define BIT_SYN_RF1_CTRL(x)                                                    \\\n\t(((x) & BIT_MASK_SYN_RF1_CTRL) << BIT_SHIFT_SYN_RF1_CTRL)\n#define BITS_SYN_RF1_CTRL (BIT_MASK_SYN_RF1_CTRL << BIT_SHIFT_SYN_RF1_CTRL)\n#define BIT_CLEAR_SYN_RF1_CTRL(x) ((x) & (~BITS_SYN_RF1_CTRL))\n#define BIT_GET_SYN_RF1_CTRL(x)                                                \\\n\t(((x) >> BIT_SHIFT_SYN_RF1_CTRL) & BIT_MASK_SYN_RF1_CTRL)\n#define BIT_SET_SYN_RF1_CTRL(x, v)                                             \\\n\t(BIT_CLEAR_SYN_RF1_CTRL(x) | BIT_SYN_RF1_CTRL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_AFE_CTRL8\t\t\t\t(Offset 0x00DC) */\n\n#define BIT_SHIFT_XTAL_GM_REP 6\n#define BIT_MASK_XTAL_GM_REP 0x3\n#define BIT_XTAL_GM_REP(x)                                                     \\\n\t(((x) & BIT_MASK_XTAL_GM_REP) << BIT_SHIFT_XTAL_GM_REP)\n#define BITS_XTAL_GM_REP (BIT_MASK_XTAL_GM_REP << BIT_SHIFT_XTAL_GM_REP)\n#define BIT_CLEAR_XTAL_GM_REP(x) ((x) & (~BITS_XTAL_GM_REP))\n#define BIT_GET_XTAL_GM_REP(x)                                                 \\\n\t(((x) >> BIT_SHIFT_XTAL_GM_REP) & BIT_MASK_XTAL_GM_REP)\n#define BIT_SET_XTAL_GM_REP(x, v)                                              \\\n\t(BIT_CLEAR_XTAL_GM_REP(x) | BIT_XTAL_GM_REP(v))\n\n#define BIT_XTAL_DRV_RF_LATCH_V5 BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL8\t\t\t\t(Offset 0x00DC) */\n\n#define BIT_XTAL_LP BIT(4)\n#define BIT_XTAL_GM_SEP BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AFE_CTRL8\t\t\t\t(Offset 0x00DC) */\n\n#define BIT_SHIFT_XTAL_SEL_TOK_V2 0\n#define BIT_MASK_XTAL_SEL_TOK_V2 0x7\n#define BIT_XTAL_SEL_TOK_V2(x)                                                 \\\n\t(((x) & BIT_MASK_XTAL_SEL_TOK_V2) << BIT_SHIFT_XTAL_SEL_TOK_V2)\n#define BITS_XTAL_SEL_TOK_V2                                                   \\\n\t(BIT_MASK_XTAL_SEL_TOK_V2 << BIT_SHIFT_XTAL_SEL_TOK_V2)\n#define BIT_CLEAR_XTAL_SEL_TOK_V2(x) ((x) & (~BITS_XTAL_SEL_TOK_V2))\n#define BIT_GET_XTAL_SEL_TOK_V2(x)                                             \\\n\t(((x) >> BIT_SHIFT_XTAL_SEL_TOK_V2) & BIT_MASK_XTAL_SEL_TOK_V2)\n#define BIT_SET_XTAL_SEL_TOK_V2(x, v)                                          \\\n\t(BIT_CLEAR_XTAL_SEL_TOK_V2(x) | BIT_XTAL_SEL_TOK_V2(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WLAN_DBG\t\t\t\t(Offset 0x00DC) */\n\n#define BIT_SHIFT_WLAN_DBG 0\n#define BIT_MASK_WLAN_DBG 0xffffffffL\n#define BIT_WLAN_DBG(x) (((x) & BIT_MASK_WLAN_DBG) << BIT_SHIFT_WLAN_DBG)\n#define BITS_WLAN_DBG (BIT_MASK_WLAN_DBG << BIT_SHIFT_WLAN_DBG)\n#define BIT_CLEAR_WLAN_DBG(x) ((x) & (~BITS_WLAN_DBG))\n#define BIT_GET_WLAN_DBG(x) (((x) >> BIT_SHIFT_WLAN_DBG) & BIT_MASK_WLAN_DBG)\n#define BIT_SET_WLAN_DBG(x, v) (BIT_CLEAR_WLAN_DBG(x) | BIT_WLAN_DBG(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYN_RFC_CTRL\t\t\t(Offset 0x00DC) */\n\n#define BIT_SHIFT_SYN_RF0_CTRL 0\n#define BIT_MASK_SYN_RF0_CTRL 0xff\n#define BIT_SYN_RF0_CTRL(x)                                                    \\\n\t(((x) & BIT_MASK_SYN_RF0_CTRL) << BIT_SHIFT_SYN_RF0_CTRL)\n#define BITS_SYN_RF0_CTRL (BIT_MASK_SYN_RF0_CTRL << BIT_SHIFT_SYN_RF0_CTRL)\n#define BIT_CLEAR_SYN_RF0_CTRL(x) ((x) & (~BITS_SYN_RF0_CTRL))\n#define BIT_GET_SYN_RF0_CTRL(x)                                                \\\n\t(((x) >> BIT_SHIFT_SYN_RF0_CTRL) & BIT_MASK_SYN_RF0_CTRL)\n#define BIT_SET_SYN_RF0_CTRL(x, v)                                             \\\n\t(BIT_CLEAR_SYN_RF0_CTRL(x) | BIT_SYN_RF0_CTRL(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AFE_CTRL8\t\t\t\t(Offset 0x00DC) */\n\n#define BIT_SHIFT_XTAL_SEL_TOK 0\n#define BIT_MASK_XTAL_SEL_TOK 0x7\n#define BIT_XTAL_SEL_TOK(x)                                                    \\\n\t(((x) & BIT_MASK_XTAL_SEL_TOK) << BIT_SHIFT_XTAL_SEL_TOK)\n#define BITS_XTAL_SEL_TOK (BIT_MASK_XTAL_SEL_TOK << BIT_SHIFT_XTAL_SEL_TOK)\n#define BIT_CLEAR_XTAL_SEL_TOK(x) ((x) & (~BITS_XTAL_SEL_TOK))\n#define BIT_GET_XTAL_SEL_TOK(x)                                                \\\n\t(((x) >> BIT_SHIFT_XTAL_SEL_TOK) & BIT_MASK_XTAL_SEL_TOK)\n#define BIT_SET_XTAL_SEL_TOK(x, v)                                             \\\n\t(BIT_CLEAR_XTAL_SEL_TOK(x) | BIT_XTAL_SEL_TOK(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_USB_SIE_INTF\t\t\t(Offset 0x00E0) */\n\n#define BIT_RD_SEL BIT(31)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_USB_SIE_INTF\t\t\t(Offset 0x00E0) */\n\n#define BIT_CPU_REG_SEL BIT(31)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_USB_SIE_INTF\t\t\t(Offset 0x00E0) */\n\n#define BIT_USB_SIE_INTF_WE_V1 BIT(30)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_USB_SIE_INTF\t\t\t(Offset 0x00E0) */\n\n#define BIT_USB3_REG_SEL BIT(30)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_USB_SIE_INTF\t\t\t(Offset 0x00E0) */\n\n#define BIT_USB_SIE_INTF_BYIOREG_V1 BIT(29)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_USB_SIE_INTF\t\t\t(Offset 0x00E0) */\n\n#define BIT_SHIFT_USB_SIE_EN 28\n#define BIT_MASK_USB_SIE_EN 0x3\n#define BIT_USB_SIE_EN(x) (((x) & BIT_MASK_USB_SIE_EN) << BIT_SHIFT_USB_SIE_EN)\n#define BITS_USB_SIE_EN (BIT_MASK_USB_SIE_EN << BIT_SHIFT_USB_SIE_EN)\n#define BIT_CLEAR_USB_SIE_EN(x) ((x) & (~BITS_USB_SIE_EN))\n#define BIT_GET_USB_SIE_EN(x)                                                  \\\n\t(((x) >> BIT_SHIFT_USB_SIE_EN) & BIT_MASK_USB_SIE_EN)\n#define BIT_SET_USB_SIE_EN(x, v) (BIT_CLEAR_USB_SIE_EN(x) | BIT_USB_SIE_EN(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_USB_SIE_INTF\t\t\t(Offset 0x00E0) */\n\n#define BIT_USB_SIE_SELECT BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_USB_SIE_INTF\t\t\t(Offset 0x00E0) */\n\n#define BIT_USB_SIE_INTF_WE BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_USB_SIE_INTF\t\t\t(Offset 0x00E0) */\n\n#define BIT_USB_SIE_INTF_BYIOREG BIT(24)\n\n#define BIT_SHIFT_USB_SIE_INTF_ADDR 16\n#define BIT_MASK_USB_SIE_INTF_ADDR 0xff\n#define BIT_USB_SIE_INTF_ADDR(x)                                               \\\n\t(((x) & BIT_MASK_USB_SIE_INTF_ADDR) << BIT_SHIFT_USB_SIE_INTF_ADDR)\n#define BITS_USB_SIE_INTF_ADDR                                                 \\\n\t(BIT_MASK_USB_SIE_INTF_ADDR << BIT_SHIFT_USB_SIE_INTF_ADDR)\n#define BIT_CLEAR_USB_SIE_INTF_ADDR(x) ((x) & (~BITS_USB_SIE_INTF_ADDR))\n#define BIT_GET_USB_SIE_INTF_ADDR(x)                                           \\\n\t(((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR) & BIT_MASK_USB_SIE_INTF_ADDR)\n#define BIT_SET_USB_SIE_INTF_ADDR(x, v)                                        \\\n\t(BIT_CLEAR_USB_SIE_INTF_ADDR(x) | BIT_USB_SIE_INTF_ADDR(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_USB_SIE_INTF\t\t\t(Offset 0x00E0) */\n\n#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1 16\n#define BIT_MASK_USB_SIE_INTF_ADDR_V1 0x1ff\n#define BIT_USB_SIE_INTF_ADDR_V1(x)                                            \\\n\t(((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1)                                 \\\n\t << BIT_SHIFT_USB_SIE_INTF_ADDR_V1)\n#define BITS_USB_SIE_INTF_ADDR_V1                                              \\\n\t(BIT_MASK_USB_SIE_INTF_ADDR_V1 << BIT_SHIFT_USB_SIE_INTF_ADDR_V1)\n#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1(x) ((x) & (~BITS_USB_SIE_INTF_ADDR_V1))\n#define BIT_GET_USB_SIE_INTF_ADDR_V1(x)                                        \\\n\t(((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1) &                             \\\n\t BIT_MASK_USB_SIE_INTF_ADDR_V1)\n#define BIT_SET_USB_SIE_INTF_ADDR_V1(x, v)                                     \\\n\t(BIT_CLEAR_USB_SIE_INTF_ADDR_V1(x) | BIT_USB_SIE_INTF_ADDR_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_USB_SIE_INTF\t\t\t(Offset 0x00E0) */\n\n#define BIT_SHIFT_USB_SIE_INTF_RD 8\n#define BIT_MASK_USB_SIE_INTF_RD 0xff\n#define BIT_USB_SIE_INTF_RD(x)                                                 \\\n\t(((x) & BIT_MASK_USB_SIE_INTF_RD) << BIT_SHIFT_USB_SIE_INTF_RD)\n#define BITS_USB_SIE_INTF_RD                                                   \\\n\t(BIT_MASK_USB_SIE_INTF_RD << BIT_SHIFT_USB_SIE_INTF_RD)\n#define BIT_CLEAR_USB_SIE_INTF_RD(x) ((x) & (~BITS_USB_SIE_INTF_RD))\n#define BIT_GET_USB_SIE_INTF_RD(x)                                             \\\n\t(((x) >> BIT_SHIFT_USB_SIE_INTF_RD) & BIT_MASK_USB_SIE_INTF_RD)\n#define BIT_SET_USB_SIE_INTF_RD(x, v)                                          \\\n\t(BIT_CLEAR_USB_SIE_INTF_RD(x) | BIT_USB_SIE_INTF_RD(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_USB_SIE_INTF\t\t\t(Offset 0x00E0) */\n\n#define BIT_SHIFT_NPQ_AVAL_PG 8\n#define BIT_MASK_NPQ_AVAL_PG 0xff\n#define BIT_NPQ_AVAL_PG(x)                                                     \\\n\t(((x) & BIT_MASK_NPQ_AVAL_PG) << BIT_SHIFT_NPQ_AVAL_PG)\n#define BITS_NPQ_AVAL_PG (BIT_MASK_NPQ_AVAL_PG << BIT_SHIFT_NPQ_AVAL_PG)\n#define BIT_CLEAR_NPQ_AVAL_PG(x) ((x) & (~BITS_NPQ_AVAL_PG))\n#define BIT_GET_NPQ_AVAL_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_NPQ_AVAL_PG) & BIT_MASK_NPQ_AVAL_PG)\n#define BIT_SET_NPQ_AVAL_PG(x, v)                                              \\\n\t(BIT_CLEAR_NPQ_AVAL_PG(x) | BIT_NPQ_AVAL_PG(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_USB_SIE_INTF\t\t\t(Offset 0x00E0) */\n\n#define BIT_SHIFT_USB_SIE_INTF_WD 0\n#define BIT_MASK_USB_SIE_INTF_WD 0xff\n#define BIT_USB_SIE_INTF_WD(x)                                                 \\\n\t(((x) & BIT_MASK_USB_SIE_INTF_WD) << BIT_SHIFT_USB_SIE_INTF_WD)\n#define BITS_USB_SIE_INTF_WD                                                   \\\n\t(BIT_MASK_USB_SIE_INTF_WD << BIT_SHIFT_USB_SIE_INTF_WD)\n#define BIT_CLEAR_USB_SIE_INTF_WD(x) ((x) & (~BITS_USB_SIE_INTF_WD))\n#define BIT_GET_USB_SIE_INTF_WD(x)                                             \\\n\t(((x) >> BIT_SHIFT_USB_SIE_INTF_WD) & BIT_MASK_USB_SIE_INTF_WD)\n#define BIT_SET_USB_SIE_INTF_WD(x, v)                                          \\\n\t(BIT_CLEAR_USB_SIE_INTF_WD(x) | BIT_USB_SIE_INTF_WD(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PCIE_MIO_INTF\t\t\t(Offset 0x00E4) */\n\n#define BIT_PCIE_MIO_EXIT_L1 BIT(19)\n#define BIT_PCIE_MIO_EXT BIT(18)\n#define BIT_PCIE_MIO_ACK BIT(17)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_PCIE_MIO_INTF\t\t\t(Offset 0x00E4) */\n\n#define BIT_PCIE_MIO_RIO BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PCIE_MIO_INTF\t\t\t(Offset 0x00E4) */\n\n#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE 16\n#define BIT_MASK_PCIE_MIO_ADDR_PAGE 0x3\n#define BIT_PCIE_MIO_ADDR_PAGE(x)                                              \\\n\t(((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE) << BIT_SHIFT_PCIE_MIO_ADDR_PAGE)\n#define BITS_PCIE_MIO_ADDR_PAGE                                                \\\n\t(BIT_MASK_PCIE_MIO_ADDR_PAGE << BIT_SHIFT_PCIE_MIO_ADDR_PAGE)\n#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE(x) ((x) & (~BITS_PCIE_MIO_ADDR_PAGE))\n#define BIT_GET_PCIE_MIO_ADDR_PAGE(x)                                          \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE) & BIT_MASK_PCIE_MIO_ADDR_PAGE)\n#define BIT_SET_PCIE_MIO_ADDR_PAGE(x, v)                                       \\\n\t(BIT_CLEAR_PCIE_MIO_ADDR_PAGE(x) | BIT_PCIE_MIO_ADDR_PAGE(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PCIE_MIO_INTF\t\t\t(Offset 0x00E4) */\n\n#define BIT_PCIE_MIO_IOREG BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PCIE_MIO_INTF\t\t\t(Offset 0x00E4) */\n\n#define BIT_PCIE_MIO_BYIOREG BIT(13)\n#define BIT_PCIE_MIO_RE BIT(12)\n\n#define BIT_SHIFT_PCIE_MIO_WE 8\n#define BIT_MASK_PCIE_MIO_WE 0xf\n#define BIT_PCIE_MIO_WE(x)                                                     \\\n\t(((x) & BIT_MASK_PCIE_MIO_WE) << BIT_SHIFT_PCIE_MIO_WE)\n#define BITS_PCIE_MIO_WE (BIT_MASK_PCIE_MIO_WE << BIT_SHIFT_PCIE_MIO_WE)\n#define BIT_CLEAR_PCIE_MIO_WE(x) ((x) & (~BITS_PCIE_MIO_WE))\n#define BIT_GET_PCIE_MIO_WE(x)                                                 \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_WE) & BIT_MASK_PCIE_MIO_WE)\n#define BIT_SET_PCIE_MIO_WE(x, v)                                              \\\n\t(BIT_CLEAR_PCIE_MIO_WE(x) | BIT_PCIE_MIO_WE(v))\n\n#define BIT_SHIFT_PCIE_MIO_ADDR 0\n#define BIT_MASK_PCIE_MIO_ADDR 0xff\n#define BIT_PCIE_MIO_ADDR(x)                                                   \\\n\t(((x) & BIT_MASK_PCIE_MIO_ADDR) << BIT_SHIFT_PCIE_MIO_ADDR)\n#define BITS_PCIE_MIO_ADDR (BIT_MASK_PCIE_MIO_ADDR << BIT_SHIFT_PCIE_MIO_ADDR)\n#define BIT_CLEAR_PCIE_MIO_ADDR(x) ((x) & (~BITS_PCIE_MIO_ADDR))\n#define BIT_GET_PCIE_MIO_ADDR(x)                                               \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_ADDR) & BIT_MASK_PCIE_MIO_ADDR)\n#define BIT_SET_PCIE_MIO_ADDR(x, v)                                            \\\n\t(BIT_CLEAR_PCIE_MIO_ADDR(x) | BIT_PCIE_MIO_ADDR(v))\n\n/* 2 REG_PCIE_MIO_INTD\t\t\t(Offset 0x00E8) */\n\n#define BIT_SHIFT_PCIE_MIO_DATA 0\n#define BIT_MASK_PCIE_MIO_DATA 0xffffffffL\n#define BIT_PCIE_MIO_DATA(x)                                                   \\\n\t(((x) & BIT_MASK_PCIE_MIO_DATA) << BIT_SHIFT_PCIE_MIO_DATA)\n#define BITS_PCIE_MIO_DATA (BIT_MASK_PCIE_MIO_DATA << BIT_SHIFT_PCIE_MIO_DATA)\n#define BIT_CLEAR_PCIE_MIO_DATA(x) ((x) & (~BITS_PCIE_MIO_DATA))\n#define BIT_GET_PCIE_MIO_DATA(x)                                               \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_DATA) & BIT_MASK_PCIE_MIO_DATA)\n#define BIT_SET_PCIE_MIO_DATA(x, v)                                            \\\n\t(BIT_CLEAR_PCIE_MIO_DATA(x) | BIT_PCIE_MIO_DATA(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HPON_FSM\t\t\t\t(Offset 0x00EC) */\n\n#define BIT_SUSPEND_V1 BIT(31)\n#define BIT_FSM_RESUME_V1 BIT(30)\n#define BIT_HOST_RESUME_SYNC_V1 BIT(29)\n#define BIT_CHIP_PDNB_V1 BIT(28)\n\n#define BIT_SHIFT_FSM_SUSPEND_V1 25\n#define BIT_MASK_FSM_SUSPEND_V1 0x7\n#define BIT_FSM_SUSPEND_V1(x)                                                  \\\n\t(((x) & BIT_MASK_FSM_SUSPEND_V1) << BIT_SHIFT_FSM_SUSPEND_V1)\n#define BITS_FSM_SUSPEND_V1                                                    \\\n\t(BIT_MASK_FSM_SUSPEND_V1 << BIT_SHIFT_FSM_SUSPEND_V1)\n#define BIT_CLEAR_FSM_SUSPEND_V1(x) ((x) & (~BITS_FSM_SUSPEND_V1))\n#define BIT_GET_FSM_SUSPEND_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_FSM_SUSPEND_V1) & BIT_MASK_FSM_SUSPEND_V1)\n#define BIT_SET_FSM_SUSPEND_V1(x, v)                                           \\\n\t(BIT_CLEAR_FSM_SUSPEND_V1(x) | BIT_FSM_SUSPEND_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_WLRF1\t\t\t\t(Offset 0x00EC) */\n\n#define BIT_SHIFT_XTAL_SEL 25\n#define BIT_MASK_XTAL_SEL 0x3\n#define BIT_XTAL_SEL(x) (((x) & BIT_MASK_XTAL_SEL) << BIT_SHIFT_XTAL_SEL)\n#define BITS_XTAL_SEL (BIT_MASK_XTAL_SEL << BIT_SHIFT_XTAL_SEL)\n#define BIT_CLEAR_XTAL_SEL(x) ((x) & (~BITS_XTAL_SEL))\n#define BIT_GET_XTAL_SEL(x) (((x) >> BIT_SHIFT_XTAL_SEL) & BIT_MASK_XTAL_SEL)\n#define BIT_SET_XTAL_SEL(x, v) (BIT_CLEAR_XTAL_SEL(x) | BIT_XTAL_SEL(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WLRF1\t\t\t\t(Offset 0x00EC) */\n\n#define BIT_SHIFT_WLRF1_CTRL 24\n#define BIT_MASK_WLRF1_CTRL 0xff\n#define BIT_WLRF1_CTRL(x) (((x) & BIT_MASK_WLRF1_CTRL) << BIT_SHIFT_WLRF1_CTRL)\n#define BITS_WLRF1_CTRL (BIT_MASK_WLRF1_CTRL << BIT_SHIFT_WLRF1_CTRL)\n#define BIT_CLEAR_WLRF1_CTRL(x) ((x) & (~BITS_WLRF1_CTRL))\n#define BIT_GET_WLRF1_CTRL(x)                                                  \\\n\t(((x) >> BIT_SHIFT_WLRF1_CTRL) & BIT_MASK_WLRF1_CTRL)\n#define BIT_SET_WLRF1_CTRL(x, v) (BIT_CLEAR_WLRF1_CTRL(x) | BIT_WLRF1_CTRL(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HPON_FSM\t\t\t\t(Offset 0x00EC) */\n\n#define BIT_PMC_ALD_V1 BIT(24)\n\n#define BIT_SHIFT_HCI_SEL_1 22\n#define BIT_MASK_HCI_SEL_1 0x3\n#define BIT_HCI_SEL_1(x) (((x) & BIT_MASK_HCI_SEL_1) << BIT_SHIFT_HCI_SEL_1)\n#define BITS_HCI_SEL_1 (BIT_MASK_HCI_SEL_1 << BIT_SHIFT_HCI_SEL_1)\n#define BIT_CLEAR_HCI_SEL_1(x) ((x) & (~BITS_HCI_SEL_1))\n#define BIT_GET_HCI_SEL_1(x) (((x) >> BIT_SHIFT_HCI_SEL_1) & BIT_MASK_HCI_SEL_1)\n#define BIT_SET_HCI_SEL_1(x, v) (BIT_CLEAR_HCI_SEL_1(x) | BIT_HCI_SEL_1(v))\n\n#define BIT_LOAD_DONE_V1 BIT(21)\n#define BIT_CNT_MATCH BIT(20)\n#define BIT_TIMEUP_V1 BIT(19)\n#define BIT_SPS_12V_VLD BIT(18)\n#define BIT_PCIERST_V1 BIT(17)\n#define BIT_HOST_CLK_VLD BIT(16)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_WLRF1\t\t\t\t(Offset 0x00EC) */\n\n#define BIT_SHIFT_WLRF2_CTRL 16\n#define BIT_MASK_WLRF2_CTRL 0xff\n#define BIT_WLRF2_CTRL(x) (((x) & BIT_MASK_WLRF2_CTRL) << BIT_SHIFT_WLRF2_CTRL)\n#define BITS_WLRF2_CTRL (BIT_MASK_WLRF2_CTRL << BIT_SHIFT_WLRF2_CTRL)\n#define BIT_CLEAR_WLRF2_CTRL(x) ((x) & (~BITS_WLRF2_CTRL))\n#define BIT_GET_WLRF2_CTRL(x)                                                  \\\n\t(((x) >> BIT_SHIFT_WLRF2_CTRL) & BIT_MASK_WLRF2_CTRL)\n#define BIT_SET_WLRF2_CTRL(x, v) (BIT_CLEAR_WLRF2_CTRL(x) | BIT_WLRF2_CTRL(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HPON_FSM\t\t\t\t(Offset 0x00EC) */\n\n#define BIT_PMC_WR_V1 BIT(15)\n#define BIT_PMC_DATA_V1 BIT(14)\n\n#define BIT_SHIFT_PMC_ADDR_V1 8\n#define BIT_MASK_PMC_ADDR_V1 0x3f\n#define BIT_PMC_ADDR_V1(x)                                                     \\\n\t(((x) & BIT_MASK_PMC_ADDR_V1) << BIT_SHIFT_PMC_ADDR_V1)\n#define BITS_PMC_ADDR_V1 (BIT_MASK_PMC_ADDR_V1 << BIT_SHIFT_PMC_ADDR_V1)\n#define BIT_CLEAR_PMC_ADDR_V1(x) ((x) & (~BITS_PMC_ADDR_V1))\n#define BIT_GET_PMC_ADDR_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_PMC_ADDR_V1) & BIT_MASK_PMC_ADDR_V1)\n#define BIT_SET_PMC_ADDR_V1(x, v)                                              \\\n\t(BIT_CLEAR_PMC_ADDR_V1(x) | BIT_PMC_ADDR_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_WLRF1\t\t\t\t(Offset 0x00EC) */\n\n#define BIT_SHIFT_WLRF3_CTRL 8\n#define BIT_MASK_WLRF3_CTRL 0xff\n#define BIT_WLRF3_CTRL(x) (((x) & BIT_MASK_WLRF3_CTRL) << BIT_SHIFT_WLRF3_CTRL)\n#define BITS_WLRF3_CTRL (BIT_MASK_WLRF3_CTRL << BIT_SHIFT_WLRF3_CTRL)\n#define BIT_CLEAR_WLRF3_CTRL(x) ((x) & (~BITS_WLRF3_CTRL))\n#define BIT_GET_WLRF3_CTRL(x)                                                  \\\n\t(((x) >> BIT_SHIFT_WLRF3_CTRL) & BIT_MASK_WLRF3_CTRL)\n#define BIT_SET_WLRF3_CTRL(x, v) (BIT_CLEAR_WLRF3_CTRL(x) | BIT_WLRF3_CTRL(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HPON_FSM\t\t\t\t(Offset 0x00EC) */\n\n#define BIT_PMC_COUNT_EN_V1 BIT(7)\n\n#define BIT_SHIFT_FSM_STATE_V1 0\n#define BIT_MASK_FSM_STATE_V1 0x7f\n#define BIT_FSM_STATE_V1(x)                                                    \\\n\t(((x) & BIT_MASK_FSM_STATE_V1) << BIT_SHIFT_FSM_STATE_V1)\n#define BITS_FSM_STATE_V1 (BIT_MASK_FSM_STATE_V1 << BIT_SHIFT_FSM_STATE_V1)\n#define BIT_CLEAR_FSM_STATE_V1(x) ((x) & (~BITS_FSM_STATE_V1))\n#define BIT_GET_FSM_STATE_V1(x)                                                \\\n\t(((x) >> BIT_SHIFT_FSM_STATE_V1) & BIT_MASK_FSM_STATE_V1)\n#define BIT_SET_FSM_STATE_V1(x, v)                                             \\\n\t(BIT_CLEAR_FSM_STATE_V1(x) | BIT_FSM_STATE_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_SHIFT_TRP_ICFG 28\n#define BIT_MASK_TRP_ICFG 0xf\n#define BIT_TRP_ICFG(x) (((x) & BIT_MASK_TRP_ICFG) << BIT_SHIFT_TRP_ICFG)\n#define BITS_TRP_ICFG (BIT_MASK_TRP_ICFG << BIT_SHIFT_TRP_ICFG)\n#define BIT_CLEAR_TRP_ICFG(x) ((x) & (~BITS_TRP_ICFG))\n#define BIT_GET_TRP_ICFG(x) (((x) >> BIT_SHIFT_TRP_ICFG) & BIT_MASK_TRP_ICFG)\n#define BIT_SET_TRP_ICFG(x, v) (BIT_CLEAR_TRP_ICFG(x) | BIT_TRP_ICFG(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_RF_TYPE_ID BIT(27)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_BD_HCI_SEL BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_LDO_VLD BIT(26)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_SHIFT_BD_HCI_SEL_V1 26\n#define BIT_MASK_BD_HCI_SEL_V1 0x3\n#define BIT_BD_HCI_SEL_V1(x)                                                   \\\n\t(((x) & BIT_MASK_BD_HCI_SEL_V1) << BIT_SHIFT_BD_HCI_SEL_V1)\n#define BITS_BD_HCI_SEL_V1 (BIT_MASK_BD_HCI_SEL_V1 << BIT_SHIFT_BD_HCI_SEL_V1)\n#define BIT_CLEAR_BD_HCI_SEL_V1(x) ((x) & (~BITS_BD_HCI_SEL_V1))\n#define BIT_GET_BD_HCI_SEL_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_BD_HCI_SEL_V1) & BIT_MASK_BD_HCI_SEL_V1)\n#define BIT_SET_BD_HCI_SEL_V1(x, v)                                            \\\n\t(BIT_CLEAR_BD_HCI_SEL_V1(x) | BIT_BD_HCI_SEL_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_BD_PKG_SEL BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_SPSLDO_SEL BIT(24)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_INTERNAL_EXTERNAL_SWR BIT(24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_LDO_SPS_SEL BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_RTL_ID BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_PAD_HWPD_IDN BIT(22)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_DIS_WL BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_TESTMODE BIT(20)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_SHIFT_PSC_TESTCFG 20\n#define BIT_MASK_PSC_TESTCFG 0x3\n#define BIT_PSC_TESTCFG(x)                                                     \\\n\t(((x) & BIT_MASK_PSC_TESTCFG) << BIT_SHIFT_PSC_TESTCFG)\n#define BITS_PSC_TESTCFG (BIT_MASK_PSC_TESTCFG << BIT_SHIFT_PSC_TESTCFG)\n#define BIT_CLEAR_PSC_TESTCFG(x) ((x) & (~BITS_PSC_TESTCFG))\n#define BIT_GET_PSC_TESTCFG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_PSC_TESTCFG) & BIT_MASK_PSC_TESTCFG)\n#define BIT_SET_PSC_TESTCFG(x, v)                                              \\\n\t(BIT_CLEAR_PSC_TESTCFG(x) | BIT_PSC_TESTCFG(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_SHIFT_VENDOR_ID 16\n#define BIT_MASK_VENDOR_ID 0xf\n#define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID)\n#define BITS_VENDOR_ID (BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID)\n#define BIT_CLEAR_VENDOR_ID(x) ((x) & (~BITS_VENDOR_ID))\n#define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID)\n#define BIT_SET_VENDOR_ID(x, v) (BIT_CLEAR_VENDOR_ID(x) | BIT_VENDOR_ID(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_SHIFT_CHIP_VER_V2 16\n#define BIT_MASK_CHIP_VER_V2 0xf\n#define BIT_CHIP_VER_V2(x)                                                     \\\n\t(((x) & BIT_MASK_CHIP_VER_V2) << BIT_SHIFT_CHIP_VER_V2)\n#define BITS_CHIP_VER_V2 (BIT_MASK_CHIP_VER_V2 << BIT_SHIFT_CHIP_VER_V2)\n#define BIT_CLEAR_CHIP_VER_V2(x) ((x) & (~BITS_CHIP_VER_V2))\n#define BIT_GET_CHIP_VER_V2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CHIP_VER_V2) & BIT_MASK_CHIP_VER_V2)\n#define BIT_SET_CHIP_VER_V2(x, v)                                              \\\n\t(BIT_CLEAR_CHIP_VER_V2(x) | BIT_CHIP_VER_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_SHIFT_CHIP_VER 12\n#define BIT_MASK_CHIP_VER 0xf\n#define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER)\n#define BITS_CHIP_VER (BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER)\n#define BIT_CLEAR_CHIP_VER(x) ((x) & (~BITS_CHIP_VER))\n#define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER)\n#define BIT_SET_CHIP_VER(x, v) (BIT_CLEAR_CHIP_VER(x) | BIT_CHIP_VER(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_TST_MODE_SEL BIT(11)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_BD_MAC3 BIT(11)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_IC_MACPHY_MODE BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_BD_MAC1 BIT(10)\n#define BIT_BD_MAC2 BIT(9)\n#define BIT_SIC_IDLE BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_SW_OFFLOAD_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_OCP_SHUTDN BIT(6)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_OCP_SHUTDN_1 BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_V15_VLD BIT(5)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_V12_VLD BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_PCIRSTB BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_PCLK_VLD BIT(3)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_PCLK_VLD_1 BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_UCLK_VLD BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_ACLK_VLD BIT(1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_M200CLK_VLD_V1 BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG1\t\t\t\t(Offset 0x00F0) */\n\n#define BIT_XCLK_VLD BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SYM_OSC32K_OUTSEL BIT(31)\n#define BIT_BTGP_WAKE_BT_LOC_BIT0 BIT(31)\n\n#define BIT_SHIFT_SYM_SEC_CLKSEL 30\n#define BIT_MASK_SYM_SEC_CLKSEL 0x3\n#define BIT_SYM_SEC_CLKSEL(x)                                                  \\\n\t(((x) & BIT_MASK_SYM_SEC_CLKSEL) << BIT_SHIFT_SYM_SEC_CLKSEL)\n#define BITS_SYM_SEC_CLKSEL                                                    \\\n\t(BIT_MASK_SYM_SEC_CLKSEL << BIT_SHIFT_SYM_SEC_CLKSEL)\n#define BIT_CLEAR_SYM_SEC_CLKSEL(x) ((x) & (~BITS_SYM_SEC_CLKSEL))\n#define BIT_GET_SYM_SEC_CLKSEL(x)                                              \\\n\t(((x) >> BIT_SHIFT_SYM_SEC_CLKSEL) & BIT_MASK_SYM_SEC_CLKSEL)\n#define BIT_SET_SYM_SEC_CLKSEL(x, v)                                           \\\n\t(BIT_CLEAR_SYM_SEC_CLKSEL(x) | BIT_SYM_SEC_CLKSEL(v))\n\n#define BIT_SHIFT_WL_GPIO_SEL 30\n#define BIT_MASK_WL_GPIO_SEL 0x3\n#define BIT_WL_GPIO_SEL(x)                                                     \\\n\t(((x) & BIT_MASK_WL_GPIO_SEL) << BIT_SHIFT_WL_GPIO_SEL)\n#define BITS_WL_GPIO_SEL (BIT_MASK_WL_GPIO_SEL << BIT_SHIFT_WL_GPIO_SEL)\n#define BIT_CLEAR_WL_GPIO_SEL(x) ((x) & (~BITS_WL_GPIO_SEL))\n#define BIT_GET_WL_GPIO_SEL(x)                                                 \\\n\t(((x) >> BIT_SHIFT_WL_GPIO_SEL) & BIT_MASK_WL_GPIO_SEL)\n#define BIT_SET_WL_GPIO_SEL(x, v)                                              \\\n\t(BIT_CLEAR_WL_GPIO_SEL(x) | BIT_WL_GPIO_SEL(v))\n\n#define BIT_SHIFT_BT_MCM_CTRL_LOC 29\n#define BIT_MASK_BT_MCM_CTRL_LOC 0x3\n#define BIT_BT_MCM_CTRL_LOC(x)                                                 \\\n\t(((x) & BIT_MASK_BT_MCM_CTRL_LOC) << BIT_SHIFT_BT_MCM_CTRL_LOC)\n#define BITS_BT_MCM_CTRL_LOC                                                   \\\n\t(BIT_MASK_BT_MCM_CTRL_LOC << BIT_SHIFT_BT_MCM_CTRL_LOC)\n#define BIT_CLEAR_BT_MCM_CTRL_LOC(x) ((x) & (~BITS_BT_MCM_CTRL_LOC))\n#define BIT_GET_BT_MCM_CTRL_LOC(x)                                             \\\n\t(((x) >> BIT_SHIFT_BT_MCM_CTRL_LOC) & BIT_MASK_BT_MCM_CTRL_LOC)\n#define BIT_SET_BT_MCM_CTRL_LOC(x, v)                                          \\\n\t(BIT_CLEAR_BT_MCM_CTRL_LOC(x) | BIT_BT_MCM_CTRL_LOC(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_RF_RL_ID 28\n#define BIT_MASK_RF_RL_ID 0xf\n#define BIT_RF_RL_ID(x) (((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID)\n#define BITS_RF_RL_ID (BIT_MASK_RF_RL_ID << BIT_SHIFT_RF_RL_ID)\n#define BIT_CLEAR_RF_RL_ID(x) ((x) & (~BITS_RF_RL_ID))\n#define BIT_GET_RF_RL_ID(x) (((x) >> BIT_SHIFT_RF_RL_ID) & BIT_MASK_RF_RL_ID)\n#define BIT_SET_RF_RL_ID(x, v) (BIT_CLEAR_RF_RL_ID(x) | BIT_RF_RL_ID(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_SYM_MAC_CLKSEL 28\n#define BIT_MASK_SYM_MAC_CLKSEL 0x3\n#define BIT_SYM_MAC_CLKSEL(x)                                                  \\\n\t(((x) & BIT_MASK_SYM_MAC_CLKSEL) << BIT_SHIFT_SYM_MAC_CLKSEL)\n#define BITS_SYM_MAC_CLKSEL                                                    \\\n\t(BIT_MASK_SYM_MAC_CLKSEL << BIT_SHIFT_SYM_MAC_CLKSEL)\n#define BIT_CLEAR_SYM_MAC_CLKSEL(x) ((x) & (~BITS_SYM_MAC_CLKSEL))\n#define BIT_GET_SYM_MAC_CLKSEL(x)                                              \\\n\t(((x) >> BIT_SHIFT_SYM_MAC_CLKSEL) & BIT_MASK_SYM_MAC_CLKSEL)\n#define BIT_SET_SYM_MAC_CLKSEL(x, v)                                           \\\n\t(BIT_CLEAR_SYM_MAC_CLKSEL(x) | BIT_SYM_MAC_CLKSEL(v))\n\n#define BIT_SHIFT_SW_DPDT_LOC 27\n#define BIT_MASK_SW_DPDT_LOC 0x3\n#define BIT_SW_DPDT_LOC(x)                                                     \\\n\t(((x) & BIT_MASK_SW_DPDT_LOC) << BIT_SHIFT_SW_DPDT_LOC)\n#define BITS_SW_DPDT_LOC (BIT_MASK_SW_DPDT_LOC << BIT_SHIFT_SW_DPDT_LOC)\n#define BIT_CLEAR_SW_DPDT_LOC(x) ((x) & (~BITS_SW_DPDT_LOC))\n#define BIT_GET_SW_DPDT_LOC(x)                                                 \\\n\t(((x) >> BIT_SHIFT_SW_DPDT_LOC) & BIT_MASK_SW_DPDT_LOC)\n#define BIT_SET_SW_DPDT_LOC(x, v)                                              \\\n\t(BIT_CLEAR_SW_DPDT_LOC(x) | BIT_SW_DPDT_LOC(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_U3_CLK_VLD BIT(27)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_WLGP_HW_DIS_LOC_BIT0 BIT(26)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_PRST_VLD_V1 BIT(26)\n#define BIT_PDN BIT(25)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_PKG_SEL 24\n#define BIT_MASK_PKG_SEL 0x3\n#define BIT_PKG_SEL(x) (((x) & BIT_MASK_PKG_SEL) << BIT_SHIFT_PKG_SEL)\n#define BITS_PKG_SEL (BIT_MASK_PKG_SEL << BIT_SHIFT_PKG_SEL)\n#define BIT_CLEAR_PKG_SEL(x) ((x) & (~BITS_PKG_SEL))\n#define BIT_GET_PKG_SEL(x) (((x) >> BIT_SHIFT_PKG_SEL) & BIT_MASK_PKG_SEL)\n#define BIT_SET_PKG_SEL(x, v) (BIT_CLEAR_PKG_SEL(x) | BIT_PKG_SEL(v))\n\n#define BIT_SHIFT_SYM_OSC32K_RCAL 24\n#define BIT_MASK_SYM_OSC32K_RCAL 0x3f\n#define BIT_SYM_OSC32K_RCAL(x)                                                 \\\n\t(((x) & BIT_MASK_SYM_OSC32K_RCAL) << BIT_SHIFT_SYM_OSC32K_RCAL)\n#define BITS_SYM_OSC32K_RCAL                                                   \\\n\t(BIT_MASK_SYM_OSC32K_RCAL << BIT_SHIFT_SYM_OSC32K_RCAL)\n#define BIT_CLEAR_SYM_OSC32K_RCAL(x) ((x) & (~BITS_SYM_OSC32K_RCAL))\n#define BIT_GET_SYM_OSC32K_RCAL(x)                                             \\\n\t(((x) >> BIT_SHIFT_SYM_OSC32K_RCAL) & BIT_MASK_SYM_OSC32K_RCAL)\n#define BIT_SET_SYM_OSC32K_RCAL(x, v)                                          \\\n\t(BIT_CLEAR_SYM_OSC32K_RCAL(x) | BIT_SYM_OSC32K_RCAL(v))\n\n#define BIT_SHIFT_SW_GPIO_B_PD 24\n#define BIT_MASK_SW_GPIO_B_PD 0xff\n#define BIT_SW_GPIO_B_PD(x)                                                    \\\n\t(((x) & BIT_MASK_SW_GPIO_B_PD) << BIT_SHIFT_SW_GPIO_B_PD)\n#define BITS_SW_GPIO_B_PD (BIT_MASK_SW_GPIO_B_PD << BIT_SHIFT_SW_GPIO_B_PD)\n#define BIT_CLEAR_SW_GPIO_B_PD(x) ((x) & (~BITS_SW_GPIO_B_PD))\n#define BIT_GET_SW_GPIO_B_PD(x)                                                \\\n\t(((x) >> BIT_SHIFT_SW_GPIO_B_PD) & BIT_MASK_SW_GPIO_B_PD)\n#define BIT_SET_SW_GPIO_B_PD(x, v)                                             \\\n\t(BIT_CLEAR_SW_GPIO_B_PD(x) | BIT_SW_GPIO_B_PD(v))\n\n#define BIT_SHIFT_SW_GPIO_B_IN 24\n#define BIT_MASK_SW_GPIO_B_IN 0xff\n#define BIT_SW_GPIO_B_IN(x)                                                    \\\n\t(((x) & BIT_MASK_SW_GPIO_B_IN) << BIT_SHIFT_SW_GPIO_B_IN)\n#define BITS_SW_GPIO_B_IN (BIT_MASK_SW_GPIO_B_IN << BIT_SHIFT_SW_GPIO_B_IN)\n#define BIT_CLEAR_SW_GPIO_B_IN(x) ((x) & (~BITS_SW_GPIO_B_IN))\n#define BIT_GET_SW_GPIO_B_IN(x)                                                \\\n\t(((x) >> BIT_SHIFT_SW_GPIO_B_IN) & BIT_MASK_SW_GPIO_B_IN)\n#define BIT_SET_SW_GPIO_B_IN(x, v)                                             \\\n\t(BIT_CLEAR_SW_GPIO_B_IN(x) | BIT_SW_GPIO_B_IN(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_OCP_SHUTDN_V1 BIT(24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_ANT_SEL_01_LOC 23\n#define BIT_MASK_ANT_SEL_01_LOC 0x7\n#define BIT_ANT_SEL_01_LOC(x)                                                  \\\n\t(((x) & BIT_MASK_ANT_SEL_01_LOC) << BIT_SHIFT_ANT_SEL_01_LOC)\n#define BITS_ANT_SEL_01_LOC                                                    \\\n\t(BIT_MASK_ANT_SEL_01_LOC << BIT_SHIFT_ANT_SEL_01_LOC)\n#define BIT_CLEAR_ANT_SEL_01_LOC(x) ((x) & (~BITS_ANT_SEL_01_LOC))\n#define BIT_GET_ANT_SEL_01_LOC(x)                                              \\\n\t(((x) >> BIT_SHIFT_ANT_SEL_01_LOC) & BIT_MASK_ANT_SEL_01_LOC)\n#define BIT_SET_ANT_SEL_01_LOC(x, v)                                           \\\n\t(BIT_CLEAR_ANT_SEL_01_LOC(x) | BIT_ANT_SEL_01_LOC(v))\n\n#define BIT_SHIFT_AUTOLOADABLE_AT_1FC 23\n#define BIT_MASK_AUTOLOADABLE_AT_1FC 0x3f\n#define BIT_AUTOLOADABLE_AT_1FC(x)                                             \\\n\t(((x) & BIT_MASK_AUTOLOADABLE_AT_1FC) << BIT_SHIFT_AUTOLOADABLE_AT_1FC)\n#define BITS_AUTOLOADABLE_AT_1FC                                               \\\n\t(BIT_MASK_AUTOLOADABLE_AT_1FC << BIT_SHIFT_AUTOLOADABLE_AT_1FC)\n#define BIT_CLEAR_AUTOLOADABLE_AT_1FC(x) ((x) & (~BITS_AUTOLOADABLE_AT_1FC))\n#define BIT_GET_AUTOLOADABLE_AT_1FC(x)                                         \\\n\t(((x) >> BIT_SHIFT_AUTOLOADABLE_AT_1FC) & BIT_MASK_AUTOLOADABLE_AT_1FC)\n#define BIT_SET_AUTOLOADABLE_AT_1FC(x, v)                                      \\\n\t(BIT_CLEAR_AUTOLOADABLE_AT_1FC(x) | BIT_AUTOLOADABLE_AT_1FC(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_PCLK_VLD_V1 BIT(23)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_BT_DISN_EN_V1 BIT(22)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_U2_CLK_VLD BIT(22)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_ANT_SEL_23_LOC 21\n#define BIT_MASK_ANT_SEL_23_LOC 0x3\n#define BIT_ANT_SEL_23_LOC(x)                                                  \\\n\t(((x) & BIT_MASK_ANT_SEL_23_LOC) << BIT_SHIFT_ANT_SEL_23_LOC)\n#define BITS_ANT_SEL_23_LOC                                                    \\\n\t(BIT_MASK_ANT_SEL_23_LOC << BIT_SHIFT_ANT_SEL_23_LOC)\n#define BIT_CLEAR_ANT_SEL_23_LOC(x) ((x) & (~BITS_ANT_SEL_23_LOC))\n#define BIT_GET_ANT_SEL_23_LOC(x)                                              \\\n\t(((x) >> BIT_SHIFT_ANT_SEL_23_LOC) & BIT_MASK_ANT_SEL_23_LOC)\n#define BIT_SET_ANT_SEL_23_LOC(x, v)                                           \\\n\t(BIT_CLEAR_ANT_SEL_23_LOC(x) | BIT_ANT_SEL_23_LOC(v))\n\n#define BIT_BT_SUSN_LOC BIT(21)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_PLL_CLK_VLD BIT(21)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_SW_ICFG 20\n#define BIT_MASK_SW_ICFG 0xf\n#define BIT_SW_ICFG(x) (((x) & BIT_MASK_SW_ICFG) << BIT_SHIFT_SW_ICFG)\n#define BITS_SW_ICFG (BIT_MASK_SW_ICFG << BIT_SHIFT_SW_ICFG)\n#define BIT_CLEAR_SW_ICFG(x) ((x) & (~BITS_SW_ICFG))\n#define BIT_GET_SW_ICFG(x) (((x) >> BIT_SHIFT_SW_ICFG) & BIT_MASK_SW_ICFG)\n#define BIT_SET_SW_ICFG(x, v) (BIT_CLEAR_SW_ICFG(x) | BIT_SW_ICFG(v))\n\n#define BIT_SYM_CONF_BYTE_ENB BIT(20)\n#define BIT_WLBB_RFE_LED1 BIT(20)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_XCK_VLD BIT(20)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_HPHY_ICFG BIT(19)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_EXTCK32K_LOC 19\n#define BIT_MASK_EXTCK32K_LOC 0x3\n#define BIT_EXTCK32K_LOC(x)                                                    \\\n\t(((x) & BIT_MASK_EXTCK32K_LOC) << BIT_SHIFT_EXTCK32K_LOC)\n#define BITS_EXTCK32K_LOC (BIT_MASK_EXTCK32K_LOC << BIT_SHIFT_EXTCK32K_LOC)\n#define BIT_CLEAR_EXTCK32K_LOC(x) ((x) & (~BITS_EXTCK32K_LOC))\n#define BIT_GET_EXTCK32K_LOC(x)                                                \\\n\t(((x) >> BIT_SHIFT_EXTCK32K_LOC) & BIT_MASK_EXTCK32K_LOC)\n#define BIT_SET_EXTCK32K_LOC(x, v)                                             \\\n\t(BIT_CLEAR_EXTCK32K_LOC(x) | BIT_EXTCK32K_LOC(v))\n\n#define BIT_WLGP_LED1_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_CK200M_VLD BIT(19)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_BT_COEX_MBOX_LOC BIT(18)\n#define BIT_WLGP_ANT23_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_HCI_SEL_EMBEDDED BIT(18)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_BTEN_TRAP BIT(18)\n#define BIT_PKG_EN_V1 BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_SEL_0XC0 16\n#define BIT_MASK_SEL_0XC0 0x3\n#define BIT_SEL_0XC0(x) (((x) & BIT_MASK_SEL_0XC0) << BIT_SHIFT_SEL_0XC0)\n#define BITS_SEL_0XC0 (BIT_MASK_SEL_0XC0 << BIT_SHIFT_SEL_0XC0)\n#define BIT_CLEAR_SEL_0XC0(x) ((x) & (~BITS_SEL_0XC0))\n#define BIT_GET_SEL_0XC0(x) (((x) >> BIT_SHIFT_SEL_0XC0) & BIT_MASK_SEL_0XC0)\n#define BIT_SET_SEL_0XC0(x, v) (BIT_CLEAR_SEL_0XC0(x) | BIT_SEL_0XC0(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SYM_MCUFWDL_DDMA_EN BIT(16)\n#define BIT_SYM_SPIC_BOOT_ADDR_CMP BIT(16)\n\n#define BIT_SHIFT_SYM_OSC32K_CLKGEN0 16\n#define BIT_MASK_SYM_OSC32K_CLKGEN0 0xff\n#define BIT_SYM_OSC32K_CLKGEN0(x)                                              \\\n\t(((x) & BIT_MASK_SYM_OSC32K_CLKGEN0) << BIT_SHIFT_SYM_OSC32K_CLKGEN0)\n#define BITS_SYM_OSC32K_CLKGEN0                                                \\\n\t(BIT_MASK_SYM_OSC32K_CLKGEN0 << BIT_SHIFT_SYM_OSC32K_CLKGEN0)\n#define BIT_CLEAR_SYM_OSC32K_CLKGEN0(x) ((x) & (~BITS_SYM_OSC32K_CLKGEN0))\n#define BIT_GET_SYM_OSC32K_CLKGEN0(x)                                          \\\n\t(((x) >> BIT_SHIFT_SYM_OSC32K_CLKGEN0) & BIT_MASK_SYM_OSC32K_CLKGEN0)\n#define BIT_SET_SYM_OSC32K_CLKGEN0(x, v)                                       \\\n\t(BIT_CLEAR_SYM_OSC32K_CLKGEN0(x) | BIT_SYM_OSC32K_CLKGEN0(v))\n\n#define BIT_SHIFT_CRC16_RESULT 16\n#define BIT_MASK_CRC16_RESULT 0xffff\n#define BIT_CRC16_RESULT(x)                                                    \\\n\t(((x) & BIT_MASK_CRC16_RESULT) << BIT_SHIFT_CRC16_RESULT)\n#define BITS_CRC16_RESULT (BIT_MASK_CRC16_RESULT << BIT_SHIFT_CRC16_RESULT)\n#define BIT_CLEAR_CRC16_RESULT(x) ((x) & (~BITS_CRC16_RESULT))\n#define BIT_GET_CRC16_RESULT(x)                                                \\\n\t(((x) >> BIT_SHIFT_CRC16_RESULT) & BIT_MASK_CRC16_RESULT)\n#define BIT_SET_CRC16_RESULT(x, v)                                             \\\n\t(BIT_CLEAR_CRC16_RESULT(x) | BIT_CRC16_RESULT(v))\n\n#define BIT_SHIFT_BTGP_LEDIO_LOC 16\n#define BIT_MASK_BTGP_LEDIO_LOC 0x3\n#define BIT_BTGP_LEDIO_LOC(x)                                                  \\\n\t(((x) & BIT_MASK_BTGP_LEDIO_LOC) << BIT_SHIFT_BTGP_LEDIO_LOC)\n#define BITS_BTGP_LEDIO_LOC                                                    \\\n\t(BIT_MASK_BTGP_LEDIO_LOC << BIT_SHIFT_BTGP_LEDIO_LOC)\n#define BIT_CLEAR_BTGP_LEDIO_LOC(x) ((x) & (~BITS_BTGP_LEDIO_LOC))\n#define BIT_GET_BTGP_LEDIO_LOC(x)                                              \\\n\t(((x) >> BIT_SHIFT_BTGP_LEDIO_LOC) & BIT_MASK_BTGP_LEDIO_LOC)\n#define BIT_SET_BTGP_LEDIO_LOC(x, v)                                           \\\n\t(BIT_CLEAR_BTGP_LEDIO_LOC(x) | BIT_BTGP_LEDIO_LOC(v))\n\n#define BIT_SHIFT_FEM_EN 16\n#define BIT_MASK_FEM_EN 0x3\n#define BIT_FEM_EN(x) (((x) & BIT_MASK_FEM_EN) << BIT_SHIFT_FEM_EN)\n#define BITS_FEM_EN (BIT_MASK_FEM_EN << BIT_SHIFT_FEM_EN)\n#define BIT_CLEAR_FEM_EN(x) ((x) & (~BITS_FEM_EN))\n#define BIT_GET_FEM_EN(x) (((x) >> BIT_SHIFT_FEM_EN) & BIT_MASK_FEM_EN)\n#define BIT_SET_FEM_EN(x, v) (BIT_CLEAR_FEM_EN(x) | BIT_FEM_EN(v))\n\n#define BIT_SHIFT_SW_GPIO_B_PU 16\n#define BIT_MASK_SW_GPIO_B_PU 0xff\n#define BIT_SW_GPIO_B_PU(x)                                                    \\\n\t(((x) & BIT_MASK_SW_GPIO_B_PU) << BIT_SHIFT_SW_GPIO_B_PU)\n#define BITS_SW_GPIO_B_PU (BIT_MASK_SW_GPIO_B_PU << BIT_SHIFT_SW_GPIO_B_PU)\n#define BIT_CLEAR_SW_GPIO_B_PU(x) ((x) & (~BITS_SW_GPIO_B_PU))\n#define BIT_GET_SW_GPIO_B_PU(x)                                                \\\n\t(((x) >> BIT_SHIFT_SW_GPIO_B_PU) & BIT_MASK_SW_GPIO_B_PU)\n#define BIT_SET_SW_GPIO_B_PU(x, v)                                             \\\n\t(BIT_CLEAR_SW_GPIO_B_PU(x) | BIT_SW_GPIO_B_PU(v))\n\n#define BIT_SHIFT_SYM_INT_PERIODIC 16\n#define BIT_MASK_SYM_INT_PERIODIC 0x3ff\n#define BIT_SYM_INT_PERIODIC(x)                                                \\\n\t(((x) & BIT_MASK_SYM_INT_PERIODIC) << BIT_SHIFT_SYM_INT_PERIODIC)\n#define BITS_SYM_INT_PERIODIC                                                  \\\n\t(BIT_MASK_SYM_INT_PERIODIC << BIT_SHIFT_SYM_INT_PERIODIC)\n#define BIT_CLEAR_SYM_INT_PERIODIC(x) ((x) & (~BITS_SYM_INT_PERIODIC))\n#define BIT_GET_SYM_INT_PERIODIC(x)                                            \\\n\t(((x) >> BIT_SHIFT_SYM_INT_PERIODIC) & BIT_MASK_SYM_INT_PERIODIC)\n#define BIT_SET_SYM_INT_PERIODIC(x, v)                                         \\\n\t(BIT_CLEAR_SYM_INT_PERIODIC(x) | BIT_SYM_INT_PERIODIC(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_TRAP_LDO_SPS_V1 BIT(16)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_IDV_DPDTSEL_P BIT(15)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_MACRDY BIT(15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_LTE_COEX_UART_LOC 14\n#define BIT_MASK_LTE_COEX_UART_LOC 0x3\n#define BIT_LTE_COEX_UART_LOC(x)                                               \\\n\t(((x) & BIT_MASK_LTE_COEX_UART_LOC) << BIT_SHIFT_LTE_COEX_UART_LOC)\n#define BITS_LTE_COEX_UART_LOC                                                 \\\n\t(BIT_MASK_LTE_COEX_UART_LOC << BIT_SHIFT_LTE_COEX_UART_LOC)\n#define BIT_CLEAR_LTE_COEX_UART_LOC(x) ((x) & (~BITS_LTE_COEX_UART_LOC))\n#define BIT_GET_LTE_COEX_UART_LOC(x)                                           \\\n\t(((x) >> BIT_SHIFT_LTE_COEX_UART_LOC) & BIT_MASK_LTE_COEX_UART_LOC)\n#define BIT_SET_LTE_COEX_UART_LOC(x, v)                                        \\\n\t(BIT_CLEAR_LTE_COEX_UART_LOC(x) | BIT_LTE_COEX_UART_LOC(v))\n\n#define BIT_IDV_DPDTSEL_N BIT(14)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_12V_VLD BIT(14)\n#define BIT_U3PHY_RST BIT(13)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_SYM_LDOA12V_WT 12\n#define BIT_MASK_SYM_LDOA12V_WT 0x3\n#define BIT_SYM_LDOA12V_WT(x)                                                  \\\n\t(((x) & BIT_MASK_SYM_LDOA12V_WT) << BIT_SHIFT_SYM_LDOA12V_WT)\n#define BITS_SYM_LDOA12V_WT                                                    \\\n\t(BIT_MASK_SYM_LDOA12V_WT << BIT_SHIFT_SYM_LDOA12V_WT)\n#define BIT_CLEAR_SYM_LDOA12V_WT(x) ((x) & (~BITS_SYM_LDOA12V_WT))\n#define BIT_GET_SYM_LDOA12V_WT(x)                                              \\\n\t(((x) >> BIT_SHIFT_SYM_LDOA12V_WT) & BIT_MASK_SYM_LDOA12V_WT)\n#define BIT_SET_SYM_LDOA12V_WT(x, v)                                           \\\n\t(BIT_CLEAR_SYM_LDOA12V_WT(x) | BIT_SYM_LDOA12V_WT(v))\n\n#define BIT_SHIFT_SYM_OSC32K_TEMP_COMP 12\n#define BIT_MASK_SYM_OSC32K_TEMP_COMP 0xf\n#define BIT_SYM_OSC32K_TEMP_COMP(x)                                            \\\n\t(((x) & BIT_MASK_SYM_OSC32K_TEMP_COMP)                                 \\\n\t << BIT_SHIFT_SYM_OSC32K_TEMP_COMP)\n#define BITS_SYM_OSC32K_TEMP_COMP                                              \\\n\t(BIT_MASK_SYM_OSC32K_TEMP_COMP << BIT_SHIFT_SYM_OSC32K_TEMP_COMP)\n#define BIT_CLEAR_SYM_OSC32K_TEMP_COMP(x) ((x) & (~BITS_SYM_OSC32K_TEMP_COMP))\n#define BIT_GET_SYM_OSC32K_TEMP_COMP(x)                                        \\\n\t(((x) >> BIT_SHIFT_SYM_OSC32K_TEMP_COMP) &                             \\\n\t BIT_MASK_SYM_OSC32K_TEMP_COMP)\n#define BIT_SET_SYM_OSC32K_TEMP_COMP(x, v)                                     \\\n\t(BIT_CLEAR_SYM_OSC32K_TEMP_COMP(x) | BIT_SYM_OSC32K_TEMP_COMP(v))\n\n#define BIT_SHIFT_LTE_3W_LOC 12\n#define BIT_MASK_LTE_3W_LOC 0x3\n#define BIT_LTE_3W_LOC(x) (((x) & BIT_MASK_LTE_3W_LOC) << BIT_SHIFT_LTE_3W_LOC)\n#define BITS_LTE_3W_LOC (BIT_MASK_LTE_3W_LOC << BIT_SHIFT_LTE_3W_LOC)\n#define BIT_CLEAR_LTE_3W_LOC(x) ((x) & (~BITS_LTE_3W_LOC))\n#define BIT_GET_LTE_3W_LOC(x)                                                  \\\n\t(((x) >> BIT_SHIFT_LTE_3W_LOC) & BIT_MASK_LTE_3W_LOC)\n#define BIT_SET_LTE_3W_LOC(x, v) (BIT_CLEAR_LTE_3W_LOC(x) | BIT_LTE_3W_LOC(v))\n\n#define BIT_SHIFT_HW_EXTWOL_LOC 12\n#define BIT_MASK_HW_EXTWOL_LOC 0x3\n#define BIT_HW_EXTWOL_LOC(x)                                                   \\\n\t(((x) & BIT_MASK_HW_EXTWOL_LOC) << BIT_SHIFT_HW_EXTWOL_LOC)\n#define BITS_HW_EXTWOL_LOC (BIT_MASK_HW_EXTWOL_LOC << BIT_SHIFT_HW_EXTWOL_LOC)\n#define BIT_CLEAR_HW_EXTWOL_LOC(x) ((x) & (~BITS_HW_EXTWOL_LOC))\n#define BIT_GET_HW_EXTWOL_LOC(x)                                               \\\n\t(((x) >> BIT_SHIFT_HW_EXTWOL_LOC) & BIT_MASK_HW_EXTWOL_LOC)\n#define BIT_SET_HW_EXTWOL_LOC(x, v)                                            \\\n\t(BIT_CLEAR_HW_EXTWOL_LOC(x) | BIT_HW_EXTWOL_LOC(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_HCI_SEL_V4 12\n#define BIT_MASK_HCI_SEL_V4 0x3\n#define BIT_HCI_SEL_V4(x) (((x) & BIT_MASK_HCI_SEL_V4) << BIT_SHIFT_HCI_SEL_V4)\n#define BITS_HCI_SEL_V4 (BIT_MASK_HCI_SEL_V4 << BIT_SHIFT_HCI_SEL_V4)\n#define BIT_CLEAR_HCI_SEL_V4(x) ((x) & (~BITS_HCI_SEL_V4))\n#define BIT_GET_HCI_SEL_V4(x)                                                  \\\n\t(((x) >> BIT_SHIFT_HCI_SEL_V4) & BIT_MASK_HCI_SEL_V4)\n#define BIT_SET_HCI_SEL_V4(x, v) (BIT_CLEAR_HCI_SEL_V4(x) | BIT_HCI_SEL_V4(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_USB2_SEL_V1 BIT(12)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_HCI_SEL_V3 12\n#define BIT_MASK_HCI_SEL_V3 0x7\n#define BIT_HCI_SEL_V3(x) (((x) & BIT_MASK_HCI_SEL_V3) << BIT_SHIFT_HCI_SEL_V3)\n#define BITS_HCI_SEL_V3 (BIT_MASK_HCI_SEL_V3 << BIT_SHIFT_HCI_SEL_V3)\n#define BIT_CLEAR_HCI_SEL_V3(x) ((x) & (~BITS_HCI_SEL_V3))\n#define BIT_GET_HCI_SEL_V3(x)                                                  \\\n\t(((x) >> BIT_SHIFT_HCI_SEL_V3) & BIT_MASK_HCI_SEL_V3)\n#define BIT_SET_HCI_SEL_V3(x, v) (BIT_CLEAR_HCI_SEL_V3(x) | BIT_HCI_SEL_V3(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SIC_LOC BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_USB_OPERATION_MODE BIT(10)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_BTGP_WAKE_LOC 10\n#define BIT_MASK_BTGP_WAKE_LOC 0x3\n#define BIT_BTGP_WAKE_LOC(x)                                                   \\\n\t(((x) & BIT_MASK_BTGP_WAKE_LOC) << BIT_SHIFT_BTGP_WAKE_LOC)\n#define BITS_BTGP_WAKE_LOC (BIT_MASK_BTGP_WAKE_LOC << BIT_SHIFT_BTGP_WAKE_LOC)\n#define BIT_CLEAR_BTGP_WAKE_LOC(x) ((x) & (~BITS_BTGP_WAKE_LOC))\n#define BIT_GET_BTGP_WAKE_LOC(x)                                               \\\n\t(((x) >> BIT_SHIFT_BTGP_WAKE_LOC) & BIT_MASK_BTGP_WAKE_LOC)\n#define BIT_SET_BTGP_WAKE_LOC(x, v)                                            \\\n\t(BIT_CLEAR_BTGP_WAKE_LOC(x) | BIT_BTGP_WAKE_LOC(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_BT_PDN BIT(9)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_WLMAC_DBG_LOC 9\n#define BIT_MASK_WLMAC_DBG_LOC 0x3\n#define BIT_WLMAC_DBG_LOC(x)                                                   \\\n\t(((x) & BIT_MASK_WLMAC_DBG_LOC) << BIT_SHIFT_WLMAC_DBG_LOC)\n#define BITS_WLMAC_DBG_LOC (BIT_MASK_WLMAC_DBG_LOC << BIT_SHIFT_WLMAC_DBG_LOC)\n#define BIT_CLEAR_WLMAC_DBG_LOC(x) ((x) & (~BITS_WLMAC_DBG_LOC))\n#define BIT_GET_WLMAC_DBG_LOC(x)                                               \\\n\t(((x) >> BIT_SHIFT_WLMAC_DBG_LOC) & BIT_MASK_WLMAC_DBG_LOC)\n#define BIT_SET_WLMAC_DBG_LOC(x, v)                                            \\\n\t(BIT_CLEAR_WLMAC_DBG_LOC(x) | BIT_WLMAC_DBG_LOC(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_AUTO_WLPON BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SYM_MCU_CLK_DIV2 BIT(8)\n\n#define BIT_SHIFT_SYM_OSC32K_LDO_V18ADJ 8\n#define BIT_MASK_SYM_OSC32K_LDO_V18ADJ 0xf\n#define BIT_SYM_OSC32K_LDO_V18ADJ(x)                                           \\\n\t(((x) & BIT_MASK_SYM_OSC32K_LDO_V18ADJ)                                \\\n\t << BIT_SHIFT_SYM_OSC32K_LDO_V18ADJ)\n#define BITS_SYM_OSC32K_LDO_V18ADJ                                             \\\n\t(BIT_MASK_SYM_OSC32K_LDO_V18ADJ << BIT_SHIFT_SYM_OSC32K_LDO_V18ADJ)\n#define BIT_CLEAR_SYM_OSC32K_LDO_V18ADJ(x) ((x) & (~BITS_SYM_OSC32K_LDO_V18ADJ))\n#define BIT_GET_SYM_OSC32K_LDO_V18ADJ(x)                                       \\\n\t(((x) >> BIT_SHIFT_SYM_OSC32K_LDO_V18ADJ) &                            \\\n\t BIT_MASK_SYM_OSC32K_LDO_V18ADJ)\n#define BIT_SET_SYM_OSC32K_LDO_V18ADJ(x, v)                                    \\\n\t(BIT_CLEAR_SYM_OSC32K_LDO_V18ADJ(x) | BIT_SYM_OSC32K_LDO_V18ADJ(v))\n\n#define BIT_SHIFT_HOST_WAKE_WL_LOC 8\n#define BIT_MASK_HOST_WAKE_WL_LOC 0x3\n#define BIT_HOST_WAKE_WL_LOC(x)                                                \\\n\t(((x) & BIT_MASK_HOST_WAKE_WL_LOC) << BIT_SHIFT_HOST_WAKE_WL_LOC)\n#define BITS_HOST_WAKE_WL_LOC                                                  \\\n\t(BIT_MASK_HOST_WAKE_WL_LOC << BIT_SHIFT_HOST_WAKE_WL_LOC)\n#define BIT_CLEAR_HOST_WAKE_WL_LOC(x) ((x) & (~BITS_HOST_WAKE_WL_LOC))\n#define BIT_GET_HOST_WAKE_WL_LOC(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_WAKE_WL_LOC) & BIT_MASK_HOST_WAKE_WL_LOC)\n#define BIT_SET_HOST_WAKE_WL_LOC(x, v)                                         \\\n\t(BIT_CLEAR_HOST_WAKE_WL_LOC(x) | BIT_HOST_WAKE_WL_LOC(v))\n\n#define BIT_SHIFT_SW_GPIO_B_OE2 8\n#define BIT_MASK_SW_GPIO_B_OE2 0xff\n#define BIT_SW_GPIO_B_OE2(x)                                                   \\\n\t(((x) & BIT_MASK_SW_GPIO_B_OE2) << BIT_SHIFT_SW_GPIO_B_OE2)\n#define BITS_SW_GPIO_B_OE2 (BIT_MASK_SW_GPIO_B_OE2 << BIT_SHIFT_SW_GPIO_B_OE2)\n#define BIT_CLEAR_SW_GPIO_B_OE2(x) ((x) & (~BITS_SW_GPIO_B_OE2))\n#define BIT_GET_SW_GPIO_B_OE2(x)                                               \\\n\t(((x) >> BIT_SHIFT_SW_GPIO_B_OE2) & BIT_MASK_SW_GPIO_B_OE2)\n#define BIT_SET_SW_GPIO_B_OE2(x, v)                                            \\\n\t(BIT_CLEAR_SW_GPIO_B_OE2(x) | BIT_SW_GPIO_B_OE2(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_TRAP_ICFG 8\n#define BIT_MASK_TRAP_ICFG 0xf\n#define BIT_TRAP_ICFG(x) (((x) & BIT_MASK_TRAP_ICFG) << BIT_SHIFT_TRAP_ICFG)\n#define BITS_TRAP_ICFG (BIT_MASK_TRAP_ICFG << BIT_SHIFT_TRAP_ICFG)\n#define BIT_CLEAR_TRAP_ICFG(x) ((x) & (~BITS_TRAP_ICFG))\n#define BIT_GET_TRAP_ICFG(x) (((x) >> BIT_SHIFT_TRAP_ICFG) & BIT_MASK_TRAP_ICFG)\n#define BIT_SET_TRAP_ICFG(x, v) (BIT_CLEAR_TRAP_ICFG(x) | BIT_TRAP_ICFG(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_WL_MODE BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SPI_FLASH_LOC BIT(7)\n\n#define BIT_SHIFT_WLPHY_DBG_LOC 7\n#define BIT_MASK_WLPHY_DBG_LOC 0x3\n#define BIT_WLPHY_DBG_LOC(x)                                                   \\\n\t(((x) & BIT_MASK_WLPHY_DBG_LOC) << BIT_SHIFT_WLPHY_DBG_LOC)\n#define BITS_WLPHY_DBG_LOC (BIT_MASK_WLPHY_DBG_LOC << BIT_SHIFT_WLPHY_DBG_LOC)\n#define BIT_CLEAR_WLPHY_DBG_LOC(x) ((x) & (~BITS_WLPHY_DBG_LOC))\n#define BIT_GET_WLPHY_DBG_LOC(x)                                               \\\n\t(((x) >> BIT_SHIFT_WLPHY_DBG_LOC) & BIT_MASK_WLPHY_DBG_LOC)\n#define BIT_SET_WLPHY_DBG_LOC(x, v)                                            \\\n\t(BIT_CLEAR_WLPHY_DBG_LOC(x) | BIT_WLPHY_DBG_LOC(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_WLAN_ID BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_PKG_SEL_HCI BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_SYM_OSC32K_COMP_LOAD_CUR 6\n#define BIT_MASK_SYM_OSC32K_COMP_LOAD_CUR 0x3\n#define BIT_SYM_OSC32K_COMP_LOAD_CUR(x)                                        \\\n\t(((x) & BIT_MASK_SYM_OSC32K_COMP_LOAD_CUR)                             \\\n\t << BIT_SHIFT_SYM_OSC32K_COMP_LOAD_CUR)\n#define BITS_SYM_OSC32K_COMP_LOAD_CUR                                          \\\n\t(BIT_MASK_SYM_OSC32K_COMP_LOAD_CUR                                     \\\n\t << BIT_SHIFT_SYM_OSC32K_COMP_LOAD_CUR)\n#define BIT_CLEAR_SYM_OSC32K_COMP_LOAD_CUR(x)                                  \\\n\t((x) & (~BITS_SYM_OSC32K_COMP_LOAD_CUR))\n#define BIT_GET_SYM_OSC32K_COMP_LOAD_CUR(x)                                    \\\n\t(((x) >> BIT_SHIFT_SYM_OSC32K_COMP_LOAD_CUR) &                         \\\n\t BIT_MASK_SYM_OSC32K_COMP_LOAD_CUR)\n#define BIT_SET_SYM_OSC32K_COMP_LOAD_CUR(x, v)                                 \\\n\t(BIT_CLEAR_SYM_OSC32K_COMP_LOAD_CUR(x) |                               \\\n\t BIT_SYM_OSC32K_COMP_LOAD_CUR(v))\n\n#define BIT_WLGP_HW_DIS_LOC_BIT1 BIT(6)\n#define BIT_XTAL_CKOUT_LOC BIT(6)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_ALDN BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_XTAL_CLKREQ_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_BTCOEX_CMDEN BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_HCI_SEL 4\n#define BIT_MASK_HCI_SEL 0x3\n#define BIT_HCI_SEL(x) (((x) & BIT_MASK_HCI_SEL) << BIT_SHIFT_HCI_SEL)\n#define BITS_HCI_SEL (BIT_MASK_HCI_SEL << BIT_SHIFT_HCI_SEL)\n#define BIT_CLEAR_HCI_SEL(x) ((x) & (~BITS_HCI_SEL))\n#define BIT_GET_HCI_SEL(x) (((x) >> BIT_SHIFT_HCI_SEL) & BIT_MASK_HCI_SEL)\n#define BIT_SET_HCI_SEL(x, v) (BIT_CLEAR_HCI_SEL(x) | BIT_HCI_SEL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SYM_BOOT_SEL BIT(4)\n\n#define BIT_SHIFT_SYM_OSC32K_COMP_LATCH_CUR 4\n#define BIT_MASK_SYM_OSC32K_COMP_LATCH_CUR 0x3\n#define BIT_SYM_OSC32K_COMP_LATCH_CUR(x)                                       \\\n\t(((x) & BIT_MASK_SYM_OSC32K_COMP_LATCH_CUR)                            \\\n\t << BIT_SHIFT_SYM_OSC32K_COMP_LATCH_CUR)\n#define BITS_SYM_OSC32K_COMP_LATCH_CUR                                         \\\n\t(BIT_MASK_SYM_OSC32K_COMP_LATCH_CUR                                    \\\n\t << BIT_SHIFT_SYM_OSC32K_COMP_LATCH_CUR)\n#define BIT_CLEAR_SYM_OSC32K_COMP_LATCH_CUR(x)                                 \\\n\t((x) & (~BITS_SYM_OSC32K_COMP_LATCH_CUR))\n#define BIT_GET_SYM_OSC32K_COMP_LATCH_CUR(x)                                   \\\n\t(((x) >> BIT_SHIFT_SYM_OSC32K_COMP_LATCH_CUR) &                        \\\n\t BIT_MASK_SYM_OSC32K_COMP_LATCH_CUR)\n#define BIT_SET_SYM_OSC32K_COMP_LATCH_CUR(x, v)                                \\\n\t(BIT_CLEAR_SYM_OSC32K_COMP_LATCH_CUR(x) |                              \\\n\t BIT_SYM_OSC32K_COMP_LATCH_CUR(v))\n\n#define BIT_SHIFT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY 4\n#define BIT_MASK_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY 0x3ff\n#define BIT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(x)                            \\\n\t(((x) & BIT_MASK_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY)                 \\\n\t << BIT_SHIFT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY)\n#define BITS_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY                              \\\n\t(BIT_MASK_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY                         \\\n\t << BIT_SHIFT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY)\n#define BIT_CLEAR_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(x)                      \\\n\t((x) & (~BITS_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY))\n#define BIT_GET_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(x)                        \\\n\t(((x) >> BIT_SHIFT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY) &             \\\n\t BIT_MASK_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY)\n#define BIT_SET_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(x, v)                     \\\n\t(BIT_CLEAR_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(x) |                   \\\n\t BIT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(v))\n\n#define BIT_HOST_WAKE_WL_EN BIT(4)\n\n#define BIT_SHIFT_XTAL_CLKREQ_LOC 4\n#define BIT_MASK_XTAL_CLKREQ_LOC 0x3\n#define BIT_XTAL_CLKREQ_LOC(x)                                                 \\\n\t(((x) & BIT_MASK_XTAL_CLKREQ_LOC) << BIT_SHIFT_XTAL_CLKREQ_LOC)\n#define BITS_XTAL_CLKREQ_LOC                                                   \\\n\t(BIT_MASK_XTAL_CLKREQ_LOC << BIT_SHIFT_XTAL_CLKREQ_LOC)\n#define BIT_CLEAR_XTAL_CLKREQ_LOC(x) ((x) & (~BITS_XTAL_CLKREQ_LOC))\n#define BIT_GET_XTAL_CLKREQ_LOC(x)                                             \\\n\t(((x) >> BIT_SHIFT_XTAL_CLKREQ_LOC) & BIT_MASK_XTAL_CLKREQ_LOC)\n#define BIT_SET_XTAL_CLKREQ_LOC(x, v)                                          \\\n\t(BIT_CLEAR_XTAL_CLKREQ_LOC(x) | BIT_XTAL_CLKREQ_LOC(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_BT_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_BTGP_MCM_UART_EN BIT(3)\n#define BIT_WLGP_UART_LOC BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_PAD_HCI_SEL_V2 3\n#define BIT_MASK_PAD_HCI_SEL_V2 0x3\n#define BIT_PAD_HCI_SEL_V2(x)                                                  \\\n\t(((x) & BIT_MASK_PAD_HCI_SEL_V2) << BIT_SHIFT_PAD_HCI_SEL_V2)\n#define BITS_PAD_HCI_SEL_V2                                                    \\\n\t(BIT_MASK_PAD_HCI_SEL_V2 << BIT_SHIFT_PAD_HCI_SEL_V2)\n#define BIT_CLEAR_PAD_HCI_SEL_V2(x) ((x) & (~BITS_PAD_HCI_SEL_V2))\n#define BIT_GET_PAD_HCI_SEL_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_PAD_HCI_SEL_V2) & BIT_MASK_PAD_HCI_SEL_V2)\n#define BIT_SET_PAD_HCI_SEL_V2(x, v)                                           \\\n\t(BIT_CLEAR_PAD_HCI_SEL_V2(x) | BIT_PAD_HCI_SEL_V2(v))\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_PAD_HCI_SEL_V1 3\n#define BIT_MASK_PAD_HCI_SEL_V1 0x7\n#define BIT_PAD_HCI_SEL_V1(x)                                                  \\\n\t(((x) & BIT_MASK_PAD_HCI_SEL_V1) << BIT_SHIFT_PAD_HCI_SEL_V1)\n#define BITS_PAD_HCI_SEL_V1                                                    \\\n\t(BIT_MASK_PAD_HCI_SEL_V1 << BIT_SHIFT_PAD_HCI_SEL_V1)\n#define BIT_CLEAR_PAD_HCI_SEL_V1(x) ((x) & (~BITS_PAD_HCI_SEL_V1))\n#define BIT_GET_PAD_HCI_SEL_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_PAD_HCI_SEL_V1) & BIT_MASK_PAD_HCI_SEL_V1)\n#define BIT_SET_PAD_HCI_SEL_V1(x, v)                                           \\\n\t(BIT_CLEAR_PAD_HCI_SEL_V1(x) | BIT_PAD_HCI_SEL_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_PAD_HCI_SEL 2\n#define BIT_MASK_PAD_HCI_SEL 0x3\n#define BIT_PAD_HCI_SEL(x)                                                     \\\n\t(((x) & BIT_MASK_PAD_HCI_SEL) << BIT_SHIFT_PAD_HCI_SEL)\n#define BITS_PAD_HCI_SEL (BIT_MASK_PAD_HCI_SEL << BIT_SHIFT_PAD_HCI_SEL)\n#define BIT_CLEAR_PAD_HCI_SEL(x) ((x) & (~BITS_PAD_HCI_SEL))\n#define BIT_GET_PAD_HCI_SEL(x)                                                 \\\n\t(((x) >> BIT_SHIFT_PAD_HCI_SEL) & BIT_MASK_PAD_HCI_SEL)\n#define BIT_SET_PAD_HCI_SEL(x, v)                                              \\\n\t(BIT_CLEAR_PAD_HCI_SEL(x) | BIT_PAD_HCI_SEL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_SYM_OSC32K_COMP_GM_CUR 2\n#define BIT_MASK_SYM_OSC32K_COMP_GM_CUR 0x3\n#define BIT_SYM_OSC32K_COMP_GM_CUR(x)                                          \\\n\t(((x) & BIT_MASK_SYM_OSC32K_COMP_GM_CUR)                               \\\n\t << BIT_SHIFT_SYM_OSC32K_COMP_GM_CUR)\n#define BITS_SYM_OSC32K_COMP_GM_CUR                                            \\\n\t(BIT_MASK_SYM_OSC32K_COMP_GM_CUR << BIT_SHIFT_SYM_OSC32K_COMP_GM_CUR)\n#define BIT_CLEAR_SYM_OSC32K_COMP_GM_CUR(x)                                    \\\n\t((x) & (~BITS_SYM_OSC32K_COMP_GM_CUR))\n#define BIT_GET_SYM_OSC32K_COMP_GM_CUR(x)                                      \\\n\t(((x) >> BIT_SHIFT_SYM_OSC32K_COMP_GM_CUR) &                           \\\n\t BIT_MASK_SYM_OSC32K_COMP_GM_CUR)\n#define BIT_SET_SYM_OSC32K_COMP_GM_CUR(x, v)                                   \\\n\t(BIT_CLEAR_SYM_OSC32K_COMP_GM_CUR(x) | BIT_SYM_OSC32K_COMP_GM_CUR(v))\n\n#define BIT_WLGP_MCM_COEXFEN BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_HCI_SEL_V2 2\n#define BIT_MASK_HCI_SEL_V2 0x3\n#define BIT_HCI_SEL_V2(x) (((x) & BIT_MASK_HCI_SEL_V2) << BIT_SHIFT_HCI_SEL_V2)\n#define BITS_HCI_SEL_V2 (BIT_MASK_HCI_SEL_V2 << BIT_SHIFT_HCI_SEL_V2)\n#define BIT_CLEAR_HCI_SEL_V2(x) ((x) & (~BITS_HCI_SEL_V2))\n#define BIT_GET_HCI_SEL_V2(x)                                                  \\\n\t(((x) >> BIT_SHIFT_HCI_SEL_V2) & BIT_MASK_HCI_SEL_V2)\n#define BIT_SET_HCI_SEL_V2(x, v) (BIT_CLEAR_HCI_SEL_V2(x) | BIT_HCI_SEL_V2(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_BT_COEX_MCM_MBOX BIT(1)\n\n#define BIT_SHIFT_BTGP_WAKE_HST_LOC 1\n#define BIT_MASK_BTGP_WAKE_HST_LOC 0x3\n#define BIT_BTGP_WAKE_HST_LOC(x)                                               \\\n\t(((x) & BIT_MASK_BTGP_WAKE_HST_LOC) << BIT_SHIFT_BTGP_WAKE_HST_LOC)\n#define BITS_BTGP_WAKE_HST_LOC                                                 \\\n\t(BIT_MASK_BTGP_WAKE_HST_LOC << BIT_SHIFT_BTGP_WAKE_HST_LOC)\n#define BIT_CLEAR_BTGP_WAKE_HST_LOC(x) ((x) & (~BITS_BTGP_WAKE_HST_LOC))\n#define BIT_GET_BTGP_WAKE_HST_LOC(x)                                           \\\n\t(((x) >> BIT_SHIFT_BTGP_WAKE_HST_LOC) & BIT_MASK_BTGP_WAKE_HST_LOC)\n#define BIT_SET_BTGP_WAKE_HST_LOC(x, v)                                        \\\n\t(BIT_CLEAR_BTGP_WAKE_HST_LOC(x) | BIT_BTGP_WAKE_HST_LOC(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_TST_MOD_SEL BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_EFS_HCI_SEL 0\n#define BIT_MASK_EFS_HCI_SEL 0x3\n#define BIT_EFS_HCI_SEL(x)                                                     \\\n\t(((x) & BIT_MASK_EFS_HCI_SEL) << BIT_SHIFT_EFS_HCI_SEL)\n#define BITS_EFS_HCI_SEL (BIT_MASK_EFS_HCI_SEL << BIT_SHIFT_EFS_HCI_SEL)\n#define BIT_CLEAR_EFS_HCI_SEL(x) ((x) & (~BITS_EFS_HCI_SEL))\n#define BIT_GET_EFS_HCI_SEL(x)                                                 \\\n\t(((x) >> BIT_SHIFT_EFS_HCI_SEL) & BIT_MASK_EFS_HCI_SEL)\n#define BIT_SET_EFS_HCI_SEL(x, v)                                              \\\n\t(BIT_CLEAR_EFS_HCI_SEL(x) | BIT_EFS_HCI_SEL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SYM_BOOT_CFG BIT(0)\n\n#define BIT_SHIFT_SYM_SPIC_BOOT_EXT_ADDR 0\n#define BIT_MASK_SYM_SPIC_BOOT_EXT_ADDR 0xffff\n#define BIT_SYM_SPIC_BOOT_EXT_ADDR(x)                                          \\\n\t(((x) & BIT_MASK_SYM_SPIC_BOOT_EXT_ADDR)                               \\\n\t << BIT_SHIFT_SYM_SPIC_BOOT_EXT_ADDR)\n#define BITS_SYM_SPIC_BOOT_EXT_ADDR                                            \\\n\t(BIT_MASK_SYM_SPIC_BOOT_EXT_ADDR << BIT_SHIFT_SYM_SPIC_BOOT_EXT_ADDR)\n#define BIT_CLEAR_SYM_SPIC_BOOT_EXT_ADDR(x)                                    \\\n\t((x) & (~BITS_SYM_SPIC_BOOT_EXT_ADDR))\n#define BIT_GET_SYM_SPIC_BOOT_EXT_ADDR(x)                                      \\\n\t(((x) >> BIT_SHIFT_SYM_SPIC_BOOT_EXT_ADDR) &                           \\\n\t BIT_MASK_SYM_SPIC_BOOT_EXT_ADDR)\n#define BIT_SET_SYM_SPIC_BOOT_EXT_ADDR(x, v)                                   \\\n\t(BIT_CLEAR_SYM_SPIC_BOOT_EXT_ADDR(x) | BIT_SYM_SPIC_BOOT_EXT_ADDR(v))\n\n#define BIT_SHIFT_SYM_OSC32K_FREQSEL 0\n#define BIT_MASK_SYM_OSC32K_FREQSEL 0x3\n#define BIT_SYM_OSC32K_FREQSEL(x)                                              \\\n\t(((x) & BIT_MASK_SYM_OSC32K_FREQSEL) << BIT_SHIFT_SYM_OSC32K_FREQSEL)\n#define BITS_SYM_OSC32K_FREQSEL                                                \\\n\t(BIT_MASK_SYM_OSC32K_FREQSEL << BIT_SHIFT_SYM_OSC32K_FREQSEL)\n#define BIT_CLEAR_SYM_OSC32K_FREQSEL(x) ((x) & (~BITS_SYM_OSC32K_FREQSEL))\n#define BIT_GET_SYM_OSC32K_FREQSEL(x)                                          \\\n\t(((x) >> BIT_SHIFT_SYM_OSC32K_FREQSEL) & BIT_MASK_SYM_OSC32K_FREQSEL)\n#define BIT_SET_SYM_OSC32K_FREQSEL(x, v)                                       \\\n\t(BIT_CLEAR_SYM_OSC32K_FREQSEL(x) | BIT_SYM_OSC32K_FREQSEL(v))\n\n#define BIT_CRC16_CHECK_ENABLE BIT(0)\n#define BIT_SW_GPIO_FUNC BIT(0)\n#define BIT_BTGP_WAKE_BT_LOC BIT(0)\n\n#define BIT_SHIFT_SW_GPIO_A_OUT 0\n#define BIT_MASK_SW_GPIO_A_OUT 0xffffffffL\n#define BIT_SW_GPIO_A_OUT(x)                                                   \\\n\t(((x) & BIT_MASK_SW_GPIO_A_OUT) << BIT_SHIFT_SW_GPIO_A_OUT)\n#define BITS_SW_GPIO_A_OUT (BIT_MASK_SW_GPIO_A_OUT << BIT_SHIFT_SW_GPIO_A_OUT)\n#define BIT_CLEAR_SW_GPIO_A_OUT(x) ((x) & (~BITS_SW_GPIO_A_OUT))\n#define BIT_GET_SW_GPIO_A_OUT(x)                                               \\\n\t(((x) >> BIT_SHIFT_SW_GPIO_A_OUT) & BIT_MASK_SW_GPIO_A_OUT)\n#define BIT_SET_SW_GPIO_A_OUT(x, v)                                            \\\n\t(BIT_CLEAR_SW_GPIO_A_OUT(x) | BIT_SW_GPIO_A_OUT(v))\n\n#define BIT_SHIFT_SW_GPIO_A_OEN 0\n#define BIT_MASK_SW_GPIO_A_OEN 0xffffffffL\n#define BIT_SW_GPIO_A_OEN(x)                                                   \\\n\t(((x) & BIT_MASK_SW_GPIO_A_OEN) << BIT_SHIFT_SW_GPIO_A_OEN)\n#define BITS_SW_GPIO_A_OEN (BIT_MASK_SW_GPIO_A_OEN << BIT_SHIFT_SW_GPIO_A_OEN)\n#define BIT_CLEAR_SW_GPIO_A_OEN(x) ((x) & (~BITS_SW_GPIO_A_OEN))\n#define BIT_GET_SW_GPIO_A_OEN(x)                                               \\\n\t(((x) >> BIT_SHIFT_SW_GPIO_A_OEN) & BIT_MASK_SW_GPIO_A_OEN)\n#define BIT_SET_SW_GPIO_A_OEN(x, v)                                            \\\n\t(BIT_CLEAR_SW_GPIO_A_OEN(x) | BIT_SW_GPIO_A_OEN(v))\n\n#define BIT_SHIFT_SW_GPIO_A_OE2 0\n#define BIT_MASK_SW_GPIO_A_OE2 0xffffffffL\n#define BIT_SW_GPIO_A_OE2(x)                                                   \\\n\t(((x) & BIT_MASK_SW_GPIO_A_OE2) << BIT_SHIFT_SW_GPIO_A_OE2)\n#define BITS_SW_GPIO_A_OE2 (BIT_MASK_SW_GPIO_A_OE2 << BIT_SHIFT_SW_GPIO_A_OE2)\n#define BIT_CLEAR_SW_GPIO_A_OE2(x) ((x) & (~BITS_SW_GPIO_A_OE2))\n#define BIT_GET_SW_GPIO_A_OE2(x)                                               \\\n\t(((x) >> BIT_SHIFT_SW_GPIO_A_OE2) & BIT_MASK_SW_GPIO_A_OE2)\n#define BIT_SET_SW_GPIO_A_OE2(x, v)                                            \\\n\t(BIT_CLEAR_SW_GPIO_A_OE2(x) | BIT_SW_GPIO_A_OE2(v))\n\n#define BIT_SHIFT_SW_GPIO_A_PU 0\n#define BIT_MASK_SW_GPIO_A_PU 0xffffffffL\n#define BIT_SW_GPIO_A_PU(x)                                                    \\\n\t(((x) & BIT_MASK_SW_GPIO_A_PU) << BIT_SHIFT_SW_GPIO_A_PU)\n#define BITS_SW_GPIO_A_PU (BIT_MASK_SW_GPIO_A_PU << BIT_SHIFT_SW_GPIO_A_PU)\n#define BIT_CLEAR_SW_GPIO_A_PU(x) ((x) & (~BITS_SW_GPIO_A_PU))\n#define BIT_GET_SW_GPIO_A_PU(x)                                                \\\n\t(((x) >> BIT_SHIFT_SW_GPIO_A_PU) & BIT_MASK_SW_GPIO_A_PU)\n#define BIT_SET_SW_GPIO_A_PU(x, v)                                             \\\n\t(BIT_CLEAR_SW_GPIO_A_PU(x) | BIT_SW_GPIO_A_PU(v))\n\n#define BIT_SHIFT_SW_GPIO_A_PD 0\n#define BIT_MASK_SW_GPIO_A_PD 0xffffffffL\n#define BIT_SW_GPIO_A_PD(x)                                                    \\\n\t(((x) & BIT_MASK_SW_GPIO_A_PD) << BIT_SHIFT_SW_GPIO_A_PD)\n#define BITS_SW_GPIO_A_PD (BIT_MASK_SW_GPIO_A_PD << BIT_SHIFT_SW_GPIO_A_PD)\n#define BIT_CLEAR_SW_GPIO_A_PD(x) ((x) & (~BITS_SW_GPIO_A_PD))\n#define BIT_GET_SW_GPIO_A_PD(x)                                                \\\n\t(((x) >> BIT_SHIFT_SW_GPIO_A_PD) & BIT_MASK_SW_GPIO_A_PD)\n#define BIT_SET_SW_GPIO_A_PD(x, v)                                             \\\n\t(BIT_CLEAR_SW_GPIO_A_PD(x) | BIT_SW_GPIO_A_PD(v))\n\n#define BIT_SHIFT_SW_GPIO_A_IN 0\n#define BIT_MASK_SW_GPIO_A_IN 0xffffffffL\n#define BIT_SW_GPIO_A_IN(x)                                                    \\\n\t(((x) & BIT_MASK_SW_GPIO_A_IN) << BIT_SHIFT_SW_GPIO_A_IN)\n#define BITS_SW_GPIO_A_IN (BIT_MASK_SW_GPIO_A_IN << BIT_SHIFT_SW_GPIO_A_IN)\n#define BIT_CLEAR_SW_GPIO_A_IN(x) ((x) & (~BITS_SW_GPIO_A_IN))\n#define BIT_GET_SW_GPIO_A_IN(x)                                                \\\n\t(((x) >> BIT_SHIFT_SW_GPIO_A_IN) & BIT_MASK_SW_GPIO_A_IN)\n#define BIT_SET_SW_GPIO_A_IN(x, v)                                             \\\n\t(BIT_CLEAR_SW_GPIO_A_IN(x) | BIT_SW_GPIO_A_IN(v))\n\n#define BIT_SHIFT_SW_GPIO_B_OEN 0\n#define BIT_MASK_SW_GPIO_B_OEN 0xff\n#define BIT_SW_GPIO_B_OEN(x)                                                   \\\n\t(((x) & BIT_MASK_SW_GPIO_B_OEN) << BIT_SHIFT_SW_GPIO_B_OEN)\n#define BITS_SW_GPIO_B_OEN (BIT_MASK_SW_GPIO_B_OEN << BIT_SHIFT_SW_GPIO_B_OEN)\n#define BIT_CLEAR_SW_GPIO_B_OEN(x) ((x) & (~BITS_SW_GPIO_B_OEN))\n#define BIT_GET_SW_GPIO_B_OEN(x)                                               \\\n\t(((x) >> BIT_SHIFT_SW_GPIO_B_OEN) & BIT_MASK_SW_GPIO_B_OEN)\n#define BIT_SET_SW_GPIO_B_OEN(x, v)                                            \\\n\t(BIT_CLEAR_SW_GPIO_B_OEN(x) | BIT_SW_GPIO_B_OEN(v))\n\n#define BIT_SHIFT_SW_GPIO_B_OUT 0\n#define BIT_MASK_SW_GPIO_B_OUT 0xff\n#define BIT_SW_GPIO_B_OUT(x)                                                   \\\n\t(((x) & BIT_MASK_SW_GPIO_B_OUT) << BIT_SHIFT_SW_GPIO_B_OUT)\n#define BITS_SW_GPIO_B_OUT (BIT_MASK_SW_GPIO_B_OUT << BIT_SHIFT_SW_GPIO_B_OUT)\n#define BIT_CLEAR_SW_GPIO_B_OUT(x) ((x) & (~BITS_SW_GPIO_B_OUT))\n#define BIT_GET_SW_GPIO_B_OUT(x)                                               \\\n\t(((x) >> BIT_SHIFT_SW_GPIO_B_OUT) & BIT_MASK_SW_GPIO_B_OUT)\n#define BIT_SET_SW_GPIO_B_OUT(x, v)                                            \\\n\t(BIT_CLEAR_SW_GPIO_B_OUT(x) | BIT_SW_GPIO_B_OUT(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_SHIFT_EFS_HCI_SEL_V1 0\n#define BIT_MASK_EFS_HCI_SEL_V1 0x7\n#define BIT_EFS_HCI_SEL_V1(x)                                                  \\\n\t(((x) & BIT_MASK_EFS_HCI_SEL_V1) << BIT_SHIFT_EFS_HCI_SEL_V1)\n#define BITS_EFS_HCI_SEL_V1                                                    \\\n\t(BIT_MASK_EFS_HCI_SEL_V1 << BIT_SHIFT_EFS_HCI_SEL_V1)\n#define BIT_CLEAR_EFS_HCI_SEL_V1(x) ((x) & (~BITS_EFS_HCI_SEL_V1))\n#define BIT_GET_EFS_HCI_SEL_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_EFS_HCI_SEL_V1) & BIT_MASK_EFS_HCI_SEL_V1)\n#define BIT_SET_EFS_HCI_SEL_V1(x, v)                                           \\\n\t(BIT_CLEAR_EFS_HCI_SEL_V1(x) | BIT_EFS_HCI_SEL_V1(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_STATUS1\t\t\t\t(Offset 0x00F4) */\n\n#define BIT_PAD_HWPDB BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_STATUS2\t\t\t\t(Offset 0x00F8) */\n\n#define BIT_HIOE_ON_TIMEOUT BIT(23)\n#define BIT_SIC_ON_TIMEOUT BIT(22)\n#define BIT_CPU_ON_TIMEOUT BIT(21)\n#define BIT_HCI_ON_TIMEOUT BIT(20)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_STATUS2\t\t\t\t(Offset 0x00F8) */\n\n#define BIT_SIO_ALDN BIT(19)\n#define BIT_USB_ALDN BIT(18)\n#define BIT_PCI_ALDN BIT(17)\n#define BIT_SYS_ALDN BIT(16)\n\n#define BIT_SHIFT_EPVID1 8\n#define BIT_MASK_EPVID1 0xff\n#define BIT_EPVID1(x) (((x) & BIT_MASK_EPVID1) << BIT_SHIFT_EPVID1)\n#define BITS_EPVID1 (BIT_MASK_EPVID1 << BIT_SHIFT_EPVID1)\n#define BIT_CLEAR_EPVID1(x) ((x) & (~BITS_EPVID1))\n#define BIT_GET_EPVID1(x) (((x) >> BIT_SHIFT_EPVID1) & BIT_MASK_EPVID1)\n#define BIT_SET_EPVID1(x, v) (BIT_CLEAR_EPVID1(x) | BIT_EPVID1(v))\n\n#define BIT_SHIFT_EPVID0 0\n#define BIT_MASK_EPVID0 0xff\n#define BIT_EPVID0(x) (((x) & BIT_MASK_EPVID0) << BIT_SHIFT_EPVID0)\n#define BITS_EPVID0 (BIT_MASK_EPVID0 << BIT_SHIFT_EPVID0)\n#define BIT_CLEAR_EPVID0(x) ((x) & (~BITS_EPVID0))\n#define BIT_GET_EPVID0(x) (((x) >> BIT_SHIFT_EPVID0) & BIT_MASK_EPVID0)\n#define BIT_SET_EPVID0(x, v) (BIT_CLEAR_EPVID0(x) | BIT_EPVID0(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CFG2\t\t\t\t(Offset 0x00FC) */\n\n#define BIT_USB2_SEL_1 BIT(31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYS_CFG2\t\t\t\t(Offset 0x00FC) */\n\n#define BIT_USB2_SEL BIT(31)\n#define BIT_FEN_WLMAC_OFF BIT(31)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CFG2\t\t\t\t(Offset 0x00FC) */\n\n#define BIT_USB3PHY_RST BIT(30)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYS_CFG2\t\t\t\t(Offset 0x00FC) */\n\n#define BIT_U3PHY_RST_V1 BIT(30)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CFG2\t\t\t\t(Offset 0x00FC) */\n\n#define BIT_U3_TERM_DET BIT(29)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYS_CFG2\t\t\t\t(Offset 0x00FC) */\n\n#define BIT_U3_TERM_DETECT BIT(29)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CFG2\t\t\t\t(Offset 0x00FC) */\n\n#define BIT_USB23_DBG_SEL BIT(24)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_CFG2\t\t\t\t(Offset 0x00FC) */\n\n#define BIT_HCI_SEL_EMBEDDED BIT(8)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SYS_CFG2\t\t\t\t(Offset 0x00FC) */\n\n#define BIT_ISO_BB2PP BIT(7)\n#define BIT_ISO_DENG2PP BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SYS_CFG2\t\t\t\t(Offset 0x00FC) */\n\n#define BIT_SHIFT_HW_ID 0\n#define BIT_MASK_HW_ID 0xff\n#define BIT_HW_ID(x) (((x) & BIT_MASK_HW_ID) << BIT_SHIFT_HW_ID)\n#define BITS_HW_ID (BIT_MASK_HW_ID << BIT_SHIFT_HW_ID)\n#define BIT_CLEAR_HW_ID(x) ((x) & (~BITS_HW_ID))\n#define BIT_GET_HW_ID(x) (((x) >> BIT_SHIFT_HW_ID) & BIT_MASK_HW_ID)\n#define BIT_SET_HW_ID(x, v) (BIT_CLEAR_HW_ID(x) | BIT_HW_ID(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CFG2\t\t\t\t(Offset 0x00FC) */\n\n#define BIT_SHIFT_CHIPID 0\n#define BIT_MASK_CHIPID 0xff\n#define BIT_CHIPID(x) (((x) & BIT_MASK_CHIPID) << BIT_SHIFT_CHIPID)\n#define BITS_CHIPID (BIT_MASK_CHIPID << BIT_SHIFT_CHIPID)\n#define BIT_CLEAR_CHIPID(x) ((x) & (~BITS_CHIPID))\n#define BIT_GET_CHIPID(x) (((x) >> BIT_SHIFT_CHIPID) & BIT_MASK_CHIPID)\n#define BIT_SET_CHIPID(x, v) (BIT_CLEAR_CHIPID(x) | BIT_CHIPID(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_CR\t\t\t\t\t(Offset 0x0100) */\n\n#define BIT_BIST_H32BIT_SEL BIT(29)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_CR\t\t\t\t\t(Offset 0x0100) */\n\n#define BIT_MACIO_TIMEOUT_EN BIT(29)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CR\t\t\t\t\t(Offset 0x0100) */\n\n#define BIT_SHIFT_LBMODE 24\n#define BIT_MASK_LBMODE 0x1f\n#define BIT_LBMODE(x) (((x) & BIT_MASK_LBMODE) << BIT_SHIFT_LBMODE)\n#define BITS_LBMODE (BIT_MASK_LBMODE << BIT_SHIFT_LBMODE)\n#define BIT_CLEAR_LBMODE(x) ((x) & (~BITS_LBMODE))\n#define BIT_GET_LBMODE(x) (((x) >> BIT_SHIFT_LBMODE) & BIT_MASK_LBMODE)\n#define BIT_SET_LBMODE(x, v) (BIT_CLEAR_LBMODE(x) | BIT_LBMODE(v))\n\n#define BIT_SHIFT_NETYPE1 18\n#define BIT_MASK_NETYPE1 0x3\n#define BIT_NETYPE1(x) (((x) & BIT_MASK_NETYPE1) << BIT_SHIFT_NETYPE1)\n#define BITS_NETYPE1 (BIT_MASK_NETYPE1 << BIT_SHIFT_NETYPE1)\n#define BIT_CLEAR_NETYPE1(x) ((x) & (~BITS_NETYPE1))\n#define BIT_GET_NETYPE1(x) (((x) >> BIT_SHIFT_NETYPE1) & BIT_MASK_NETYPE1)\n#define BIT_SET_NETYPE1(x, v) (BIT_CLEAR_NETYPE1(x) | BIT_NETYPE1(v))\n\n#define BIT_SHIFT_NETYPE0 16\n#define BIT_MASK_NETYPE0 0x3\n#define BIT_NETYPE0(x) (((x) & BIT_MASK_NETYPE0) << BIT_SHIFT_NETYPE0)\n#define BITS_NETYPE0 (BIT_MASK_NETYPE0 << BIT_SHIFT_NETYPE0)\n#define BIT_CLEAR_NETYPE0(x) ((x) & (~BITS_NETYPE0))\n#define BIT_GET_NETYPE0(x) (((x) >> BIT_SHIFT_NETYPE0) & BIT_MASK_NETYPE0)\n#define BIT_SET_NETYPE0(x, v) (BIT_CLEAR_NETYPE0(x) | BIT_NETYPE0(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_CR\t\t\t\t\t(Offset 0x0100) */\n\n#define BIT_STAT_FUNC_RST BIT(13)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CR\t\t\t\t\t(Offset 0x0100) */\n\n#define BIT_COUNTER_STS_EN BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CR\t\t\t\t\t(Offset 0x0100) */\n\n#define BIT_PTA_I2C_MBOX_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CR\t\t\t\t\t(Offset 0x0100) */\n\n#define BIT_I2C_MAILBOX_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CR\t\t\t\t\t(Offset 0x0100) */\n\n#define BIT_SHCUT_EN BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CR\t\t\t\t\t(Offset 0x0100) */\n\n#define BIT_32K_CAL_TMR_EN BIT(10)\n#define BIT_MAC_SEC_EN BIT(9)\n#define BIT_ENSWBCN BIT(8)\n#define BIT_MACRXEN BIT(7)\n#define BIT_MACTXEN BIT(6)\n#define BIT_SCHEDULE_EN BIT(5)\n#define BIT_PROTOCOL_EN BIT(4)\n#define BIT_RXDMA_EN BIT(3)\n#define BIT_TXDMA_EN BIT(2)\n#define BIT_HCI_RXDMA_EN BIT(1)\n#define BIT_HCI_TXDMA_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PG_SIZE\t\t\t\t(Offset 0x0104) */\n\n#define BIT_SHIFT_DBG_FIFO_SEL 16\n#define BIT_MASK_DBG_FIFO_SEL 0xff\n#define BIT_DBG_FIFO_SEL(x)                                                    \\\n\t(((x) & BIT_MASK_DBG_FIFO_SEL) << BIT_SHIFT_DBG_FIFO_SEL)\n#define BITS_DBG_FIFO_SEL (BIT_MASK_DBG_FIFO_SEL << BIT_SHIFT_DBG_FIFO_SEL)\n#define BIT_CLEAR_DBG_FIFO_SEL(x) ((x) & (~BITS_DBG_FIFO_SEL))\n#define BIT_GET_DBG_FIFO_SEL(x)                                                \\\n\t(((x) >> BIT_SHIFT_DBG_FIFO_SEL) & BIT_MASK_DBG_FIFO_SEL)\n#define BIT_SET_DBG_FIFO_SEL(x, v)                                             \\\n\t(BIT_CLEAR_DBG_FIFO_SEL(x) | BIT_DBG_FIFO_SEL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PKT_BUFF_ACCESS_CTRL\t\t(Offset 0x0106) */\n\n#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL 0\n#define BIT_MASK_PKT_BUFF_ACCESS_CTRL 0xff\n#define BIT_PKT_BUFF_ACCESS_CTRL(x)                                            \\\n\t(((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL)                                 \\\n\t << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL)\n#define BITS_PKT_BUFF_ACCESS_CTRL                                              \\\n\t(BIT_MASK_PKT_BUFF_ACCESS_CTRL << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL)\n#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL(x) ((x) & (~BITS_PKT_BUFF_ACCESS_CTRL))\n#define BIT_GET_PKT_BUFF_ACCESS_CTRL(x)                                        \\\n\t(((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) &                             \\\n\t BIT_MASK_PKT_BUFF_ACCESS_CTRL)\n#define BIT_SET_PKT_BUFF_ACCESS_CTRL(x, v)                                     \\\n\t(BIT_CLEAR_PKT_BUFF_ACCESS_CTRL(x) | BIT_PKT_BUFF_ACCESS_CTRL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TSF_CLK_STATE\t\t\t(Offset 0x0108) */\n\n#define BIT_RXPKTBUF_DBG BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TSF_CLK_STATE\t\t\t(Offset 0x0108) */\n\n#define BIT_TSF_CLK_IDX BIT(15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TSF_CLK_STATE\t\t\t(Offset 0x0108) */\n\n#define BIT_TSF_CLK_STABLE BIT(15)\n\n#define BIT_SHIFT_PKTBUF_DBG_ADDR 0\n#define BIT_MASK_PKTBUF_DBG_ADDR 0x1fff\n#define BIT_PKTBUF_DBG_ADDR(x)                                                 \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_ADDR) << BIT_SHIFT_PKTBUF_DBG_ADDR)\n#define BITS_PKTBUF_DBG_ADDR                                                   \\\n\t(BIT_MASK_PKTBUF_DBG_ADDR << BIT_SHIFT_PKTBUF_DBG_ADDR)\n#define BIT_CLEAR_PKTBUF_DBG_ADDR(x) ((x) & (~BITS_PKTBUF_DBG_ADDR))\n#define BIT_GET_PKTBUF_DBG_ADDR(x)                                             \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR) & BIT_MASK_PKTBUF_DBG_ADDR)\n#define BIT_SET_PKTBUF_DBG_ADDR(x, v)                                          \\\n\t(BIT_CLEAR_PKTBUF_DBG_ADDR(x) | BIT_PKTBUF_DBG_ADDR(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXDMA_PQ_MAP\t\t\t(Offset 0x010C) */\n\n#define BIT_CSI_BW_EN BIT(31)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TXDMA_PQ_MAP\t\t\t(Offset 0x010C) */\n\n#define BIT_SHIFT_TXDMA_HIQ_MAP_V1 19\n#define BIT_MASK_TXDMA_HIQ_MAP_V1 0x7\n#define BIT_TXDMA_HIQ_MAP_V1(x)                                                \\\n\t(((x) & BIT_MASK_TXDMA_HIQ_MAP_V1) << BIT_SHIFT_TXDMA_HIQ_MAP_V1)\n#define BITS_TXDMA_HIQ_MAP_V1                                                  \\\n\t(BIT_MASK_TXDMA_HIQ_MAP_V1 << BIT_SHIFT_TXDMA_HIQ_MAP_V1)\n#define BIT_CLEAR_TXDMA_HIQ_MAP_V1(x) ((x) & (~BITS_TXDMA_HIQ_MAP_V1))\n#define BIT_GET_TXDMA_HIQ_MAP_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_V1) & BIT_MASK_TXDMA_HIQ_MAP_V1)\n#define BIT_SET_TXDMA_HIQ_MAP_V1(x, v)                                         \\\n\t(BIT_CLEAR_TXDMA_HIQ_MAP_V1(x) | BIT_TXDMA_HIQ_MAP_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_PQ_MAP\t\t\t(Offset 0x010C) */\n\n#define BIT_SHIFT_TXDMA_CMQ_MAP 16\n#define BIT_MASK_TXDMA_CMQ_MAP 0x3\n#define BIT_TXDMA_CMQ_MAP(x)                                                   \\\n\t(((x) & BIT_MASK_TXDMA_CMQ_MAP) << BIT_SHIFT_TXDMA_CMQ_MAP)\n#define BITS_TXDMA_CMQ_MAP (BIT_MASK_TXDMA_CMQ_MAP << BIT_SHIFT_TXDMA_CMQ_MAP)\n#define BIT_CLEAR_TXDMA_CMQ_MAP(x) ((x) & (~BITS_TXDMA_CMQ_MAP))\n#define BIT_GET_TXDMA_CMQ_MAP(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXDMA_CMQ_MAP) & BIT_MASK_TXDMA_CMQ_MAP)\n#define BIT_SET_TXDMA_CMQ_MAP(x, v)                                            \\\n\t(BIT_CLEAR_TXDMA_CMQ_MAP(x) | BIT_TXDMA_CMQ_MAP(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TXDMA_PQ_MAP\t\t\t(Offset 0x010C) */\n\n#define BIT_SHIFT_TXDMA_MGQ_MAP_V1 16\n#define BIT_MASK_TXDMA_MGQ_MAP_V1 0x7\n#define BIT_TXDMA_MGQ_MAP_V1(x)                                                \\\n\t(((x) & BIT_MASK_TXDMA_MGQ_MAP_V1) << BIT_SHIFT_TXDMA_MGQ_MAP_V1)\n#define BITS_TXDMA_MGQ_MAP_V1                                                  \\\n\t(BIT_MASK_TXDMA_MGQ_MAP_V1 << BIT_SHIFT_TXDMA_MGQ_MAP_V1)\n#define BIT_CLEAR_TXDMA_MGQ_MAP_V1(x) ((x) & (~BITS_TXDMA_MGQ_MAP_V1))\n#define BIT_GET_TXDMA_MGQ_MAP_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_V1) & BIT_MASK_TXDMA_MGQ_MAP_V1)\n#define BIT_SET_TXDMA_MGQ_MAP_V1(x, v)                                         \\\n\t(BIT_CLEAR_TXDMA_MGQ_MAP_V1(x) | BIT_TXDMA_MGQ_MAP_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXDMA_PQ_MAP\t\t\t(Offset 0x010C) */\n\n#define BIT_SHIFT_TXDMA_H2C_MAP 16\n#define BIT_MASK_TXDMA_H2C_MAP 0x3\n#define BIT_TXDMA_H2C_MAP(x)                                                   \\\n\t(((x) & BIT_MASK_TXDMA_H2C_MAP) << BIT_SHIFT_TXDMA_H2C_MAP)\n#define BITS_TXDMA_H2C_MAP (BIT_MASK_TXDMA_H2C_MAP << BIT_SHIFT_TXDMA_H2C_MAP)\n#define BIT_CLEAR_TXDMA_H2C_MAP(x) ((x) & (~BITS_TXDMA_H2C_MAP))\n#define BIT_GET_TXDMA_H2C_MAP(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXDMA_H2C_MAP) & BIT_MASK_TXDMA_H2C_MAP)\n#define BIT_SET_TXDMA_H2C_MAP(x, v)                                            \\\n\t(BIT_CLEAR_TXDMA_H2C_MAP(x) | BIT_TXDMA_H2C_MAP(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_PQ_MAP\t\t\t(Offset 0x010C) */\n\n#define BIT_SHIFT_TXDMA_HIQ_MAP 14\n#define BIT_MASK_TXDMA_HIQ_MAP 0x3\n#define BIT_TXDMA_HIQ_MAP(x)                                                   \\\n\t(((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP)\n#define BITS_TXDMA_HIQ_MAP (BIT_MASK_TXDMA_HIQ_MAP << BIT_SHIFT_TXDMA_HIQ_MAP)\n#define BIT_CLEAR_TXDMA_HIQ_MAP(x) ((x) & (~BITS_TXDMA_HIQ_MAP))\n#define BIT_GET_TXDMA_HIQ_MAP(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXDMA_HIQ_MAP) & BIT_MASK_TXDMA_HIQ_MAP)\n#define BIT_SET_TXDMA_HIQ_MAP(x, v)                                            \\\n\t(BIT_CLEAR_TXDMA_HIQ_MAP(x) | BIT_TXDMA_HIQ_MAP(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TXDMA_PQ_MAP\t\t\t(Offset 0x010C) */\n\n#define BIT_SHIFT_TXDMA_BKQ_MAP_V1 13\n#define BIT_MASK_TXDMA_BKQ_MAP_V1 0x7\n#define BIT_TXDMA_BKQ_MAP_V1(x)                                                \\\n\t(((x) & BIT_MASK_TXDMA_BKQ_MAP_V1) << BIT_SHIFT_TXDMA_BKQ_MAP_V1)\n#define BITS_TXDMA_BKQ_MAP_V1                                                  \\\n\t(BIT_MASK_TXDMA_BKQ_MAP_V1 << BIT_SHIFT_TXDMA_BKQ_MAP_V1)\n#define BIT_CLEAR_TXDMA_BKQ_MAP_V1(x) ((x) & (~BITS_TXDMA_BKQ_MAP_V1))\n#define BIT_GET_TXDMA_BKQ_MAP_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_V1) & BIT_MASK_TXDMA_BKQ_MAP_V1)\n#define BIT_SET_TXDMA_BKQ_MAP_V1(x, v)                                         \\\n\t(BIT_CLEAR_TXDMA_BKQ_MAP_V1(x) | BIT_TXDMA_BKQ_MAP_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_PQ_MAP\t\t\t(Offset 0x010C) */\n\n#define BIT_SHIFT_TXDMA_MGQ_MAP 12\n#define BIT_MASK_TXDMA_MGQ_MAP 0x3\n#define BIT_TXDMA_MGQ_MAP(x)                                                   \\\n\t(((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP)\n#define BITS_TXDMA_MGQ_MAP (BIT_MASK_TXDMA_MGQ_MAP << BIT_SHIFT_TXDMA_MGQ_MAP)\n#define BIT_CLEAR_TXDMA_MGQ_MAP(x) ((x) & (~BITS_TXDMA_MGQ_MAP))\n#define BIT_GET_TXDMA_MGQ_MAP(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXDMA_MGQ_MAP) & BIT_MASK_TXDMA_MGQ_MAP)\n#define BIT_SET_TXDMA_MGQ_MAP(x, v)                                            \\\n\t(BIT_CLEAR_TXDMA_MGQ_MAP(x) | BIT_TXDMA_MGQ_MAP(v))\n\n#define BIT_SHIFT_TXDMA_BKQ_MAP 10\n#define BIT_MASK_TXDMA_BKQ_MAP 0x3\n#define BIT_TXDMA_BKQ_MAP(x)                                                   \\\n\t(((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP)\n#define BITS_TXDMA_BKQ_MAP (BIT_MASK_TXDMA_BKQ_MAP << BIT_SHIFT_TXDMA_BKQ_MAP)\n#define BIT_CLEAR_TXDMA_BKQ_MAP(x) ((x) & (~BITS_TXDMA_BKQ_MAP))\n#define BIT_GET_TXDMA_BKQ_MAP(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXDMA_BKQ_MAP) & BIT_MASK_TXDMA_BKQ_MAP)\n#define BIT_SET_TXDMA_BKQ_MAP(x, v)                                            \\\n\t(BIT_CLEAR_TXDMA_BKQ_MAP(x) | BIT_TXDMA_BKQ_MAP(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TXDMA_PQ_MAP\t\t\t(Offset 0x010C) */\n\n#define BIT_SHIFT_TXDMA_BEQ_MAP_V1 10\n#define BIT_MASK_TXDMA_BEQ_MAP_V1 0x7\n#define BIT_TXDMA_BEQ_MAP_V1(x)                                                \\\n\t(((x) & BIT_MASK_TXDMA_BEQ_MAP_V1) << BIT_SHIFT_TXDMA_BEQ_MAP_V1)\n#define BITS_TXDMA_BEQ_MAP_V1                                                  \\\n\t(BIT_MASK_TXDMA_BEQ_MAP_V1 << BIT_SHIFT_TXDMA_BEQ_MAP_V1)\n#define BIT_CLEAR_TXDMA_BEQ_MAP_V1(x) ((x) & (~BITS_TXDMA_BEQ_MAP_V1))\n#define BIT_GET_TXDMA_BEQ_MAP_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_V1) & BIT_MASK_TXDMA_BEQ_MAP_V1)\n#define BIT_SET_TXDMA_BEQ_MAP_V1(x, v)                                         \\\n\t(BIT_CLEAR_TXDMA_BEQ_MAP_V1(x) | BIT_TXDMA_BEQ_MAP_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_PQ_MAP\t\t\t(Offset 0x010C) */\n\n#define BIT_SHIFT_TXDMA_BEQ_MAP 8\n#define BIT_MASK_TXDMA_BEQ_MAP 0x3\n#define BIT_TXDMA_BEQ_MAP(x)                                                   \\\n\t(((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP)\n#define BITS_TXDMA_BEQ_MAP (BIT_MASK_TXDMA_BEQ_MAP << BIT_SHIFT_TXDMA_BEQ_MAP)\n#define BIT_CLEAR_TXDMA_BEQ_MAP(x) ((x) & (~BITS_TXDMA_BEQ_MAP))\n#define BIT_GET_TXDMA_BEQ_MAP(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXDMA_BEQ_MAP) & BIT_MASK_TXDMA_BEQ_MAP)\n#define BIT_SET_TXDMA_BEQ_MAP(x, v)                                            \\\n\t(BIT_CLEAR_TXDMA_BEQ_MAP(x) | BIT_TXDMA_BEQ_MAP(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TXDMA_PQ_MAP\t\t\t(Offset 0x010C) */\n\n#define BIT_SHIFT_TXDMA_VIQ_MAP_V1 7\n#define BIT_MASK_TXDMA_VIQ_MAP_V1 0x7\n#define BIT_TXDMA_VIQ_MAP_V1(x)                                                \\\n\t(((x) & BIT_MASK_TXDMA_VIQ_MAP_V1) << BIT_SHIFT_TXDMA_VIQ_MAP_V1)\n#define BITS_TXDMA_VIQ_MAP_V1                                                  \\\n\t(BIT_MASK_TXDMA_VIQ_MAP_V1 << BIT_SHIFT_TXDMA_VIQ_MAP_V1)\n#define BIT_CLEAR_TXDMA_VIQ_MAP_V1(x) ((x) & (~BITS_TXDMA_VIQ_MAP_V1))\n#define BIT_GET_TXDMA_VIQ_MAP_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_V1) & BIT_MASK_TXDMA_VIQ_MAP_V1)\n#define BIT_SET_TXDMA_VIQ_MAP_V1(x, v)                                         \\\n\t(BIT_CLEAR_TXDMA_VIQ_MAP_V1(x) | BIT_TXDMA_VIQ_MAP_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_PQ_MAP\t\t\t(Offset 0x010C) */\n\n#define BIT_SHIFT_TXDMA_VIQ_MAP 6\n#define BIT_MASK_TXDMA_VIQ_MAP 0x3\n#define BIT_TXDMA_VIQ_MAP(x)                                                   \\\n\t(((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP)\n#define BITS_TXDMA_VIQ_MAP (BIT_MASK_TXDMA_VIQ_MAP << BIT_SHIFT_TXDMA_VIQ_MAP)\n#define BIT_CLEAR_TXDMA_VIQ_MAP(x) ((x) & (~BITS_TXDMA_VIQ_MAP))\n#define BIT_GET_TXDMA_VIQ_MAP(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXDMA_VIQ_MAP) & BIT_MASK_TXDMA_VIQ_MAP)\n#define BIT_SET_TXDMA_VIQ_MAP(x, v)                                            \\\n\t(BIT_CLEAR_TXDMA_VIQ_MAP(x) | BIT_TXDMA_VIQ_MAP(v))\n\n#define BIT_SHIFT_TXDMA_VOQ_MAP 4\n#define BIT_MASK_TXDMA_VOQ_MAP 0x3\n#define BIT_TXDMA_VOQ_MAP(x)                                                   \\\n\t(((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP)\n#define BITS_TXDMA_VOQ_MAP (BIT_MASK_TXDMA_VOQ_MAP << BIT_SHIFT_TXDMA_VOQ_MAP)\n#define BIT_CLEAR_TXDMA_VOQ_MAP(x) ((x) & (~BITS_TXDMA_VOQ_MAP))\n#define BIT_GET_TXDMA_VOQ_MAP(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXDMA_VOQ_MAP) & BIT_MASK_TXDMA_VOQ_MAP)\n#define BIT_SET_TXDMA_VOQ_MAP(x, v)                                            \\\n\t(BIT_CLEAR_TXDMA_VOQ_MAP(x) | BIT_TXDMA_VOQ_MAP(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TXDMA_PQ_MAP\t\t\t(Offset 0x010C) */\n\n#define BIT_SHIFT_TXDMA_VOQ_MAP_V1 4\n#define BIT_MASK_TXDMA_VOQ_MAP_V1 0x7\n#define BIT_TXDMA_VOQ_MAP_V1(x)                                                \\\n\t(((x) & BIT_MASK_TXDMA_VOQ_MAP_V1) << BIT_SHIFT_TXDMA_VOQ_MAP_V1)\n#define BITS_TXDMA_VOQ_MAP_V1                                                  \\\n\t(BIT_MASK_TXDMA_VOQ_MAP_V1 << BIT_SHIFT_TXDMA_VOQ_MAP_V1)\n#define BIT_CLEAR_TXDMA_VOQ_MAP_V1(x) ((x) & (~BITS_TXDMA_VOQ_MAP_V1))\n#define BIT_GET_TXDMA_VOQ_MAP_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_V1) & BIT_MASK_TXDMA_VOQ_MAP_V1)\n#define BIT_SET_TXDMA_VOQ_MAP_V1(x, v)                                         \\\n\t(BIT_CLEAR_TXDMA_VOQ_MAP_V1(x) | BIT_TXDMA_VOQ_MAP_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXDMA_PQ_MAP\t\t\t(Offset 0x010C) */\n\n#define BIT_TXDMA_BW_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_PQ_MAP\t\t\t(Offset 0x010C) */\n\n#define BIT_RXDMA_AGG_EN BIT(2)\n#define BIT_RXSHFT_EN BIT(1)\n#define BIT_RXDMA_ARBBW_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT)\n\n/* 2 REG_TRXFF_BNDY\t\t\t\t(Offset 0x0114) */\n\n#define BIT_SHIFT_RXFFOVFL_RSV_V1 28\n#define BIT_MASK_RXFFOVFL_RSV_V1 0xf\n#define BIT_RXFFOVFL_RSV_V1(x)                                                 \\\n\t(((x) & BIT_MASK_RXFFOVFL_RSV_V1) << BIT_SHIFT_RXFFOVFL_RSV_V1)\n#define BITS_RXFFOVFL_RSV_V1                                                   \\\n\t(BIT_MASK_RXFFOVFL_RSV_V1 << BIT_SHIFT_RXFFOVFL_RSV_V1)\n#define BIT_CLEAR_RXFFOVFL_RSV_V1(x) ((x) & (~BITS_RXFFOVFL_RSV_V1))\n#define BIT_GET_RXFFOVFL_RSV_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_RXFFOVFL_RSV_V1) & BIT_MASK_RXFFOVFL_RSV_V1)\n#define BIT_SET_RXFFOVFL_RSV_V1(x, v)                                          \\\n\t(BIT_CLEAR_RXFFOVFL_RSV_V1(x) | BIT_RXFFOVFL_RSV_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TRXFF_BNDY\t\t\t\t(Offset 0x0114) */\n\n#define BIT_SHIFT_RXFF0_BNDY 16\n#define BIT_MASK_RXFF0_BNDY 0xffff\n#define BIT_RXFF0_BNDY(x) (((x) & BIT_MASK_RXFF0_BNDY) << BIT_SHIFT_RXFF0_BNDY)\n#define BITS_RXFF0_BNDY (BIT_MASK_RXFF0_BNDY << BIT_SHIFT_RXFF0_BNDY)\n#define BIT_CLEAR_RXFF0_BNDY(x) ((x) & (~BITS_RXFF0_BNDY))\n#define BIT_GET_RXFF0_BNDY(x)                                                  \\\n\t(((x) >> BIT_SHIFT_RXFF0_BNDY) & BIT_MASK_RXFF0_BNDY)\n#define BIT_SET_RXFF0_BNDY(x, v) (BIT_CLEAR_RXFF0_BNDY(x) | BIT_RXFF0_BNDY(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TRXFF_BNDY\t\t\t\t(Offset 0x0114) */\n\n#define BIT_SHIFT_FWFFOVFL_RSV 16\n#define BIT_MASK_FWFFOVFL_RSV 0xf\n#define BIT_FWFFOVFL_RSV(x)                                                    \\\n\t(((x) & BIT_MASK_FWFFOVFL_RSV) << BIT_SHIFT_FWFFOVFL_RSV)\n#define BITS_FWFFOVFL_RSV (BIT_MASK_FWFFOVFL_RSV << BIT_SHIFT_FWFFOVFL_RSV)\n#define BIT_CLEAR_FWFFOVFL_RSV(x) ((x) & (~BITS_FWFFOVFL_RSV))\n#define BIT_GET_FWFFOVFL_RSV(x)                                                \\\n\t(((x) >> BIT_SHIFT_FWFFOVFL_RSV) & BIT_MASK_FWFFOVFL_RSV)\n#define BIT_SET_FWFFOVFL_RSV(x, v)                                             \\\n\t(BIT_CLEAR_FWFFOVFL_RSV(x) | BIT_FWFFOVFL_RSV(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TRXFF_BNDY\t\t\t\t(Offset 0x0114) */\n\n#define BIT_SHIFT_RXFFOVFL_RSV 8\n#define BIT_MASK_RXFFOVFL_RSV 0xf\n#define BIT_RXFFOVFL_RSV(x)                                                    \\\n\t(((x) & BIT_MASK_RXFFOVFL_RSV) << BIT_SHIFT_RXFFOVFL_RSV)\n#define BITS_RXFFOVFL_RSV (BIT_MASK_RXFFOVFL_RSV << BIT_SHIFT_RXFFOVFL_RSV)\n#define BIT_CLEAR_RXFFOVFL_RSV(x) ((x) & (~BITS_RXFFOVFL_RSV))\n#define BIT_GET_RXFFOVFL_RSV(x)                                                \\\n\t(((x) >> BIT_SHIFT_RXFFOVFL_RSV) & BIT_MASK_RXFFOVFL_RSV)\n#define BIT_SET_RXFFOVFL_RSV(x, v)                                             \\\n\t(BIT_CLEAR_RXFFOVFL_RSV(x) | BIT_RXFFOVFL_RSV(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TRXFF_BNDY\t\t\t\t(Offset 0x0114) */\n\n#define BIT_SHIFT_RXFFOVFL_RSV_V2 8\n#define BIT_MASK_RXFFOVFL_RSV_V2 0xf\n#define BIT_RXFFOVFL_RSV_V2(x)                                                 \\\n\t(((x) & BIT_MASK_RXFFOVFL_RSV_V2) << BIT_SHIFT_RXFFOVFL_RSV_V2)\n#define BITS_RXFFOVFL_RSV_V2                                                   \\\n\t(BIT_MASK_RXFFOVFL_RSV_V2 << BIT_SHIFT_RXFFOVFL_RSV_V2)\n#define BIT_CLEAR_RXFFOVFL_RSV_V2(x) ((x) & (~BITS_RXFFOVFL_RSV_V2))\n#define BIT_GET_RXFFOVFL_RSV_V2(x)                                             \\\n\t(((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2) & BIT_MASK_RXFFOVFL_RSV_V2)\n#define BIT_SET_RXFFOVFL_RSV_V2(x, v)                                          \\\n\t(BIT_CLEAR_RXFFOVFL_RSV_V2(x) | BIT_RXFFOVFL_RSV_V2(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT)\n\n/* 2 REG_TRXFF_BNDY\t\t\t\t(Offset 0x0114) */\n\n#define BIT_SHIFT_RXFF0_BNDY_V1 8\n#define BIT_MASK_RXFF0_BNDY_V1 0x3ffff\n#define BIT_RXFF0_BNDY_V1(x)                                                   \\\n\t(((x) & BIT_MASK_RXFF0_BNDY_V1) << BIT_SHIFT_RXFF0_BNDY_V1)\n#define BITS_RXFF0_BNDY_V1 (BIT_MASK_RXFF0_BNDY_V1 << BIT_SHIFT_RXFF0_BNDY_V1)\n#define BIT_CLEAR_RXFF0_BNDY_V1(x) ((x) & (~BITS_RXFF0_BNDY_V1))\n#define BIT_GET_RXFF0_BNDY_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_RXFF0_BNDY_V1) & BIT_MASK_RXFF0_BNDY_V1)\n#define BIT_SET_RXFF0_BNDY_V1(x, v)                                            \\\n\t(BIT_CLEAR_RXFF0_BNDY_V1(x) | BIT_RXFF0_BNDY_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TRXFF_BNDY\t\t\t\t(Offset 0x0114) */\n\n#define BIT_SHIFT_TXPKTBUF_PGBNDY 0\n#define BIT_MASK_TXPKTBUF_PGBNDY 0xff\n#define BIT_TXPKTBUF_PGBNDY(x)                                                 \\\n\t(((x) & BIT_MASK_TXPKTBUF_PGBNDY) << BIT_SHIFT_TXPKTBUF_PGBNDY)\n#define BITS_TXPKTBUF_PGBNDY                                                   \\\n\t(BIT_MASK_TXPKTBUF_PGBNDY << BIT_SHIFT_TXPKTBUF_PGBNDY)\n#define BIT_CLEAR_TXPKTBUF_PGBNDY(x) ((x) & (~BITS_TXPKTBUF_PGBNDY))\n#define BIT_GET_TXPKTBUF_PGBNDY(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY) & BIT_MASK_TXPKTBUF_PGBNDY)\n#define BIT_SET_TXPKTBUF_PGBNDY(x, v)                                          \\\n\t(BIT_CLEAR_TXPKTBUF_PGBNDY(x) | BIT_TXPKTBUF_PGBNDY(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PTA_I2C_MBOX\t\t\t(Offset 0x0118) */\n\n#define BIT_SHIFT_RESP_TXPOWER 18\n#define BIT_MASK_RESP_TXPOWER 0x7\n#define BIT_RESP_TXPOWER(x)                                                    \\\n\t(((x) & BIT_MASK_RESP_TXPOWER) << BIT_SHIFT_RESP_TXPOWER)\n#define BITS_RESP_TXPOWER (BIT_MASK_RESP_TXPOWER << BIT_SHIFT_RESP_TXPOWER)\n#define BIT_CLEAR_RESP_TXPOWER(x) ((x) & (~BITS_RESP_TXPOWER))\n#define BIT_GET_RESP_TXPOWER(x)                                                \\\n\t(((x) >> BIT_SHIFT_RESP_TXPOWER) & BIT_MASK_RESP_TXPOWER)\n#define BIT_SET_RESP_TXPOWER(x, v)                                             \\\n\t(BIT_CLEAR_RESP_TXPOWER(x) | BIT_RESP_TXPOWER(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT)\n\n/* 2 REG_FF_STATUS\t\t\t\t(Offset 0x0118) */\n\n#define BIT_SHIFT_RXFF0_RDPTR_V1 13\n#define BIT_MASK_RXFF0_RDPTR_V1 0x3ffff\n#define BIT_RXFF0_RDPTR_V1(x)                                                  \\\n\t(((x) & BIT_MASK_RXFF0_RDPTR_V1) << BIT_SHIFT_RXFF0_RDPTR_V1)\n#define BITS_RXFF0_RDPTR_V1                                                    \\\n\t(BIT_MASK_RXFF0_RDPTR_V1 << BIT_SHIFT_RXFF0_RDPTR_V1)\n#define BIT_CLEAR_RXFF0_RDPTR_V1(x) ((x) & (~BITS_RXFF0_RDPTR_V1))\n#define BIT_GET_RXFF0_RDPTR_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_RXFF0_RDPTR_V1) & BIT_MASK_RXFF0_RDPTR_V1)\n#define BIT_SET_RXFF0_RDPTR_V1(x, v)                                           \\\n\t(BIT_CLEAR_RXFF0_RDPTR_V1(x) | BIT_RXFF0_RDPTR_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PTA_I2C_MBOX\t\t\t(Offset 0x0118) */\n\n#define BIT_SHIFT_I2C_M_STATUS 8\n#define BIT_MASK_I2C_M_STATUS 0xf\n#define BIT_I2C_M_STATUS(x)                                                    \\\n\t(((x) & BIT_MASK_I2C_M_STATUS) << BIT_SHIFT_I2C_M_STATUS)\n#define BITS_I2C_M_STATUS (BIT_MASK_I2C_M_STATUS << BIT_SHIFT_I2C_M_STATUS)\n#define BIT_CLEAR_I2C_M_STATUS(x) ((x) & (~BITS_I2C_M_STATUS))\n#define BIT_GET_I2C_M_STATUS(x)                                                \\\n\t(((x) >> BIT_SHIFT_I2C_M_STATUS) & BIT_MASK_I2C_M_STATUS)\n#define BIT_SET_I2C_M_STATUS(x, v)                                             \\\n\t(BIT_CLEAR_I2C_M_STATUS(x) | BIT_I2C_M_STATUS(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PTA_I2C_MBOX\t\t\t(Offset 0x0118) */\n\n#define BIT_SHIFT_I2C_M_BUS_GNT 4\n#define BIT_MASK_I2C_M_BUS_GNT 0x7\n#define BIT_I2C_M_BUS_GNT(x)                                                   \\\n\t(((x) & BIT_MASK_I2C_M_BUS_GNT) << BIT_SHIFT_I2C_M_BUS_GNT)\n#define BITS_I2C_M_BUS_GNT (BIT_MASK_I2C_M_BUS_GNT << BIT_SHIFT_I2C_M_BUS_GNT)\n#define BIT_CLEAR_I2C_M_BUS_GNT(x) ((x) & (~BITS_I2C_M_BUS_GNT))\n#define BIT_GET_I2C_M_BUS_GNT(x)                                               \\\n\t(((x) >> BIT_SHIFT_I2C_M_BUS_GNT) & BIT_MASK_I2C_M_BUS_GNT)\n#define BIT_SET_I2C_M_BUS_GNT(x, v)                                            \\\n\t(BIT_CLEAR_I2C_M_BUS_GNT(x) | BIT_I2C_M_BUS_GNT(v))\n\n#define BIT_I2C_GNT_FW BIT(3)\n\n#define BIT_SHIFT_I2C_DATA_RATE 1\n#define BIT_MASK_I2C_DATA_RATE 0x3\n#define BIT_I2C_DATA_RATE(x)                                                   \\\n\t(((x) & BIT_MASK_I2C_DATA_RATE) << BIT_SHIFT_I2C_DATA_RATE)\n#define BITS_I2C_DATA_RATE (BIT_MASK_I2C_DATA_RATE << BIT_SHIFT_I2C_DATA_RATE)\n#define BIT_CLEAR_I2C_DATA_RATE(x) ((x) & (~BITS_I2C_DATA_RATE))\n#define BIT_GET_I2C_DATA_RATE(x)                                               \\\n\t(((x) >> BIT_SHIFT_I2C_DATA_RATE) & BIT_MASK_I2C_DATA_RATE)\n#define BIT_SET_I2C_DATA_RATE(x, v)                                            \\\n\t(BIT_CLEAR_I2C_DATA_RATE(x) | BIT_I2C_DATA_RATE(v))\n\n#define BIT_I2C_SW_CONTROL_UNLOCK BIT(0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT)\n\n/* 2 REG_FF_STATUS\t\t\t\t(Offset 0x0118) */\n\n#define BIT_SHIFT_RXFF0_WTPTR_V1 0\n#define BIT_MASK_RXFF0_WTPTR_V1 0x3ffff\n#define BIT_RXFF0_WTPTR_V1(x)                                                  \\\n\t(((x) & BIT_MASK_RXFF0_WTPTR_V1) << BIT_SHIFT_RXFF0_WTPTR_V1)\n#define BITS_RXFF0_WTPTR_V1                                                    \\\n\t(BIT_MASK_RXFF0_WTPTR_V1 << BIT_SHIFT_RXFF0_WTPTR_V1)\n#define BIT_CLEAR_RXFF0_WTPTR_V1(x) ((x) & (~BITS_RXFF0_WTPTR_V1))\n#define BIT_GET_RXFF0_WTPTR_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_RXFF0_WTPTR_V1) & BIT_MASK_RXFF0_WTPTR_V1)\n#define BIT_SET_RXFF0_WTPTR_V1(x, v)                                           \\\n\t(BIT_CLEAR_RXFF0_WTPTR_V1(x) | BIT_RXFF0_WTPTR_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXFF_PTR\t\t\t\t(Offset 0x011C) */\n\n#define BIT_SHIFT_RXFF0_RDPTR 16\n#define BIT_MASK_RXFF0_RDPTR 0xffff\n#define BIT_RXFF0_RDPTR(x)                                                     \\\n\t(((x) & BIT_MASK_RXFF0_RDPTR) << BIT_SHIFT_RXFF0_RDPTR)\n#define BITS_RXFF0_RDPTR (BIT_MASK_RXFF0_RDPTR << BIT_SHIFT_RXFF0_RDPTR)\n#define BIT_CLEAR_RXFF0_RDPTR(x) ((x) & (~BITS_RXFF0_RDPTR))\n#define BIT_GET_RXFF0_RDPTR(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RXFF0_RDPTR) & BIT_MASK_RXFF0_RDPTR)\n#define BIT_SET_RXFF0_RDPTR(x, v)                                              \\\n\t(BIT_CLEAR_RXFF0_RDPTR(x) | BIT_RXFF0_RDPTR(v))\n\n#define BIT_SHIFT_RXFF0_WTPTR 0\n#define BIT_MASK_RXFF0_WTPTR 0xffff\n#define BIT_RXFF0_WTPTR(x)                                                     \\\n\t(((x) & BIT_MASK_RXFF0_WTPTR) << BIT_SHIFT_RXFF0_WTPTR)\n#define BITS_RXFF0_WTPTR (BIT_MASK_RXFF0_WTPTR << BIT_SHIFT_RXFF0_WTPTR)\n#define BIT_CLEAR_RXFF0_WTPTR(x) ((x) & (~BITS_RXFF0_WTPTR))\n#define BIT_GET_RXFF0_WTPTR(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RXFF0_WTPTR) & BIT_MASK_RXFF0_WTPTR)\n#define BIT_SET_RXFF0_WTPTR(x, v)                                              \\\n\t(BIT_CLEAR_RXFF0_WTPTR(x) | BIT_RXFF0_WTPTR(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_H2C_OK_INT_MSK BIT(31)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_SW_PLL_LEAVE_32K_INT_EN BIT(31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT_EN BIT(31)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_H2C_CMD_FULL_INT_MSK BIT(30)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_FWFF_FULL_INT_EN BIT(30)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FWFF_FULL_INT_EN BIT(30)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_PWR_INT_127_MSK_V1 BIT(29)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_BB_STOP_RX_INT_EN BIT(29)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_BB_STOP_RX_INT_EN BIT(29)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_PWR_INT_126_MSK BIT(28)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_RXDMA2_DONE_INT_EN BIT(28)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_PWR_INT_125TO96_MSK BIT(27)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_RXDONE3_INT_EN BIT(27)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_PWR_INT_95TO64_MSK_V1 BIT(26)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_RXDONE2_INT_EN BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_PWR_INT_63TO32_MSK_V1 BIT(25)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_RX_BCN_P4_INT_EN BIT(25)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_PWR_INT_31TO0_MSK_V1 BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_RX_BCN_P3_INT_EN BIT(24)\n#define BIT_FS_RX_BCN_P2_INT_EN BIT(23)\n#define BIT_FS_RX_BCN_P1_INT_EN BIT(22)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_BF0_TIMEOUT_INT_MSK BIT(21)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_RX_BCN_P0_INT_EN BIT(21)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_BF1_TIMEOUT_INT_MSK BIT(20)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_RX_UMD0_INT_EN BIT(20)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_EVTQ_TXDONE_INT_MSK BIT(19)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_RX_UMD1_INT_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_EVTQ_START_INT_MSK BIT(18)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_RX_BMD0_INT_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_TXBCN2_OK_INT_MSK BIT(17)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_RX_BMD1_INT_EN BIT(17)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_TXBCN2_ERR_INT_MSK BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_RXDONE_INT_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_DWWIN_END_INT_MSK BIT(15)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_WWLAN_INT_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_BCN2_EARLY_INT_MSK BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_SOUND_DONE_INT_EN BIT(14)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_TBTT1_INT_MSK BIT(13)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_LP_STBY_INT_EN BIT(13)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_PSTIMERB_INT_MSK BIT(12)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_TRL_MTR_INT_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_PSTIMERA_INT_MSK BIT(11)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_BF1_PRETO_INT_EN BIT(11)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_P2P_RFOFF_EARLY_INT_MSK BIT(10)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_BF0_PRETO_INT_EN BIT(10)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_MACID_RELEASE_INT_MSK BIT(9)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_PTCL_RELEASE_MACID_INT_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_NANRPT_DONE_INT_MSK BIT(8)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_PRETXERR_HANDLE_FSIMR BIT(8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_PRETX_ERRHLD_INT_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_PRETX_ERRHLD_INT_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FTM_PTT_INT_MSK_V1 BIT(7)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_GTRD_INT_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_RXFTMREQ_OK_INT_MSK BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_LTE_COEX_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_RXFTM_INT_MSK_V1 BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_WLACTOFF_INT_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_TXFTM_INT_MSK_V1 BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_WLACTON_INT_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_LTECOEX_INT_MSK BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_BTCMD_INT_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_REG_MAILBOX_TO_I2C_INT BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_MAILBOX_INT_MSK BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_TRPC_TO_INT_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FLC_DRUTO_INT_MSK BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_TRPC_TO_INT_EN_V1 BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_BIT_RPC_O_T_INT_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEIMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FLC_PKTTH_INT_MSK BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1IMR\t\t\t\t(Offset 0x0120) */\n\n#define BIT_FS_RPC_O_T_INT_EN_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_H2C_OK_INT BIT(31)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_SW_PLL_LEAVE_32K_INT BIT(31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT BIT(31)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_H2C_CMD_FULL_INT BIT(30)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_FS_FWFF_FULL_INT BIT(30)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FWFF_FULL_INT BIT(30)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_PWR_INT_127_V2 BIT(29)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_BB_STOP_RX_INT BIT(29)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_BB_STOP_RX_INT BIT(29)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_PWR_INT_126 BIT(28)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_RXDMA2_DONE_INT BIT(28)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_PWR_INT_125TO96 BIT(27)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_RXDONE3_INT BIT(27)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_RXDONE3_INT_INT BIT(27)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_PWR_INT_95TO64_V1 BIT(26)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_RXDONE2_INT BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_PWR_INT_63TO32_V1 BIT(25)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_RX_BCN_P4_INT BIT(25)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_PWR_INT_31TO0_V1 BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_RX_BCN_P3_INT BIT(24)\n#define BIT_FS_RX_BCN_P2_INT BIT(23)\n#define BIT_FS_RX_BCN_P1_INT BIT(22)\n#define BIT_FS_RX_BCN_P0_INT BIT(21)\n#define BIT_FS_RX_UMD0_INT BIT(20)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_EVTQ_TXDONE_INT BIT(19)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_RX_UMD1_INT BIT(19)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_EVTQ_START_INT BIT(18)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_RX_BMD0_INT BIT(18)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_TXBCN2_OK_INT BIT(17)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_RX_BMD1_INT BIT(17)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_TXBCN2_ERR_INT BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_RXDONE_INT BIT(16)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_DWWIN_END_INT BIT(15)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_WWLAN_INT BIT(15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_BCN2_EARLY_INT BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_SOUND_DONE_INT BIT(14)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_TBTT1_INT BIT(13)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_LP_STBY_INT BIT(13)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_PSTIMERB_INT BIT(12)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_TRL_MTR_INT BIT(12)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_PSTIMERA_INT BIT(11)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_BF1_PRETO_INT BIT(11)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_P2P_RFOFF_EARLY_INT BIT(10)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_BF0_PRETO_INT BIT(10)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_MACID_RELEASE_INT BIT(9)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_PTCL_RELEASE_MACID_INT BIT(9)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_NANRPT_DONE_INT BIT(8)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_PRETXERR_HANDLE_FSISR BIT(8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_PRETX_ERRHLD_INT BIT(8)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_PRETX_ERRHLD_INT BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FTM_PTT_INT_V1 BIT(7)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_SND_RDY_INT BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_RXFTMREQ_OK_INT BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_LTE_COEX_INT BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_RXFTM_INT_V1 BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_WLACTOFF_INT BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_TXFTM_INT_V1 BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_WLACTON_INT BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_LTECOEX_INT BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_BCN_RX_INT_INT BIT(3)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_BT_CMD_INT BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_MAILBOX_TO_I2C BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_MAILBOX_INT BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_MAILBOX_TO_I2C_INT BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_TRPC_TO_INT BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FLC_DRUTO_INT BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_TRPC_TO_INT BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_RPC_O_T_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FEISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FLC_PKTTH_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE1ISR\t\t\t\t(Offset 0x0124) */\n\n#define BIT_FS_RPC_O_T_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CPWM\t\t\t\t(Offset 0x012C) */\n\n#define BIT_CPWM_TOGGLING BIT(31)\n\n#define BIT_SHIFT_CPWM_MOD 24\n#define BIT_MASK_CPWM_MOD 0x7f\n#define BIT_CPWM_MOD(x) (((x) & BIT_MASK_CPWM_MOD) << BIT_SHIFT_CPWM_MOD)\n#define BITS_CPWM_MOD (BIT_MASK_CPWM_MOD << BIT_SHIFT_CPWM_MOD)\n#define BIT_CLEAR_CPWM_MOD(x) ((x) & (~BITS_CPWM_MOD))\n#define BIT_GET_CPWM_MOD(x) (((x) >> BIT_SHIFT_CPWM_MOD) & BIT_MASK_CPWM_MOD)\n#define BIT_SET_CPWM_MOD(x, v) (BIT_CLEAR_CPWM_MOD(x) | BIT_CPWM_MOD(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_PCIE_BCNDMAERR_INT_MSK BIT(31)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXBCNOK_MB7_INT_EN BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_SOUND_DONE_MSK BIT(30)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_SOUND_DONE_INT_MSK BIT(30)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXBCNOK_MB6_INT_EN BIT(30)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_TRY_DONE_MSK BIT(29)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_TRY_DONE_INT_MSK BIT(29)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXBCNOK_MB5_INT_EN BIT(29)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_TXRPT_CNT_FULL_MSK BIT(28)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_TXRPT_CNT_FULL_INT_MSK BIT(28)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXBCNOK_MB4_INT_EN BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_WLACTOFF_INT_EN BIT(27)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_WLACTOFF_INT_MSK BIT(27)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXBCNOK_MB3_INT_EN BIT(27)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_WLACTON_INT_EN BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_WLACTON_INT_MSK BIT(26)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXBCNOK_MB2_INT_EN BIT(26)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_TXPKTIN_INT_EN BIT(25)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_TXPKTIN_INT_MSK BIT(25)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXBCNOK_MB1_INT_EN BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_TXBCNOK_MSK BIT(24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_TXBCNOK_INT_MSK BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXBCNOK_MB0_INT_EN BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_TXBCNERR_MSK BIT(23)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_TXBCNERR_INT_MSK BIT(23)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXBCNERR_MB7_INT_EN BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_RX_UMD0_EN BIT(22)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_RX_UMD0_INT_MSK BIT(22)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXBCNERR_MB6_INT_EN BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_RX_UMD1_EN BIT(21)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_RX_UMD1_INT_MSK BIT(21)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXBCNERR_MB5_INT_EN BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_RX_BMD0_EN BIT(20)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_RX_BMD0_INT_MSK BIT(20)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXBCNERR_MB4_INT_EN BIT(20)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_RX_BMD1_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_RX_BMD1_INT_MSK BIT(19)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXBCNERR_MB3_INT_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCN_RX_INT_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCN_RX_INT_INT_MSK BIT(18)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXBCNERR_MB2_INT_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_TBTTINT_MSK BIT(17)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_TBTTINT_INT_MSK BIT(17)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXBCNERR_MB1_INT_EN BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNERLY_MSK BIT(16)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNERLY_INT_MSK BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXBCNERR_MB0_INT_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNDMA7_MSK BIT(15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNDMA7_INT_MSK BIT(15)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_CPUMGN_POLLED_PKT_DONE_INT_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_CPU_MGQ_TXDONE_INT_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNDMA6_MSK BIT(14)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNDMA6_INT_MSK BIT(14)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_SIFS_OVERSPEC_INT_EN BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNDMA5_MSK BIT(13)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNDMA5_INT_MSK BIT(13)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNDMA4_MSK BIT(12)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNDMA4_INT_MSK BIT(12)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_MGNTQFF_TO_INT_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNDMA3_MSK BIT(11)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNDMA3_INT_MSK BIT(11)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_DDMA1_LP_INT_ENBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_EN BIT(11)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_CPUMGQ_ERR_INT_EN BIT(11)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_DDMA1_LP_INT_EN BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNDMA2_MSK BIT(10)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNDMA2_INT_MSK BIT(10)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_DDMA1_HP_INT_EN BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNDMA1_MSK BIT(9)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNDMA1_INT_MSK BIT(9)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_DDMA0_LP_INT_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNDMA0_MSK BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_BCNDMA0_INT_MSK BIT(8)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_DDMA0_HP_INT_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_LP_STBY_MSK BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_LP_STBY_INT_MSK BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TRXRPT_INT_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_CTWENDINT_MSK BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_CTWENDINT_INT_MSK BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_C2H_W_READY_INT_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_HRCV_MSK BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_HRCV_INT_MSK BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_HRCV_INT_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_H2CCMD_MSK BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_H2CCMD_INT_MSK BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_H2CCMD_INT_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_RXDONE_MSK BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_RXDONE_INT_MSK BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXPKTIN_INT_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_ERRORHDL_MSK BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_ERRORHDL_INT_MSK BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_ERRORHDL_INT_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_TXCCX_MSK_FW BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_TXCCX_INT_MSK BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXCCX_INT_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_TXCLOSE_MSK BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_TXCLOSE_INT_MSK BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWIMR\t\t\t\t(Offset 0x0130) */\n\n#define BIT_FS_TXCLOSE_INT_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_PCIE_BCNDMAERR_INT BIT(31)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXBCNOK_MB7_INT BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_SOUND_DONE_INT BIT(30)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXBCNOK_MB6_INT BIT(30)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_TRY_DONE_INT BIT(29)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXBCNOK_MB5_INT BIT(29)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_TXRPT_CNT_FULL_INT BIT(28)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXBCNOK_MB4_INT BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_WLACTOFF_INT BIT(27)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXBCNOK_MB3_INT BIT(27)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_WLACTON_INT BIT(26)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXBCNOK_MB2_INT BIT(26)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_TXPKTIN_INT BIT(25)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXBCNOK_MB1_INT BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_TXBCNOK_INT BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXBCNOK_MB0_INT BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_TXBCNERR_INT BIT(23)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXBCNERR_MB7_INT BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_RX_UMD0_INT BIT(22)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXBCNERR_MB6_INT BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_RX_UMD1_INT BIT(21)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXBCNERR_MB5_INT BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_RX_BMD0_INT BIT(20)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXBCNERR_MB4_INT BIT(20)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_RX_BMD1_INT BIT(19)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXBCNERR_MB3_INT BIT(19)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_BCN_RX_INT_INT BIT(18)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXBCNERR_MB2_INT BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_TBTTINT_INT BIT(17)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXBCNERR_MB1_INT BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_BCNERLY_INT BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXBCNERR_MB0_INT BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_BCNDMA7_INT BIT(15)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_CPUMGN_POLLED_PKT_DONE_INT BIT(15)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_CPU_MGQ_TXDONE_INT BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_BCNDMA6_INT BIT(14)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_SIFS_OVERSPEC_INT BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_BCNDMA5_INT BIT(13)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_MGNTQ_RPTR_RELEASE_INT BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_BCNDMA4_INT BIT(12)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_MGNTQFF_TO_INT BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_BCNDMA3_INT BIT(11)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_DDMA1_LP_INTBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT BIT(11)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_CPUMGQ_ERR_INT BIT(11)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_DDMA1_LP_INT BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_BCNDMA2_INT BIT(10)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_DDMA1_HP_INT BIT(10)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FWCMD_PKTIN_INT BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_BCNDMA1_INT BIT(9)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_DDMA0_LP_INT BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_BCNDMA0_INT BIT(8)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_DDMA0_HP_INT BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_LP_STBY_INT BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TRXRPT_INT BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_CTWENDINT_INT BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_C2H_W_READY_INT BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_HRCV_INT BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_HRCV_INT BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_H2CCMD_INT BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_H2CCMD_INT BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_RXDONE_INT BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXPKTIN_INT BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_ERRORHDL_INT BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_ERRORHDL_INT BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_TXCCX_INT BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXCCX_INT BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_TXCLOSE_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWISR\t\t\t\t(Offset 0x0134) */\n\n#define BIT_FS_TXCLOSE_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_GTINT6_MSK BIT(31)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_GT6INT_MSK BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_TX_NULL1_INT_MSK BIT(30)\n#define BIT_TX_NULL0_INT_MSK BIT(29)\n#define BIT_MTI_BCNIVLEAR_INT_MSK BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_ATIMINT_MSK BIT(27)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_ATIM_INT_MSK BIT(27)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_WWLAN_INT_EN BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_WWLAN_INT_MSK BIT(26)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_C2H_W_READY_EN BIT(25)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_C2H_W_READY_MSK BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_TRL_MTR_EN BIT(24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_TRL_MTR_INT_MSK BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_CLR_PS_STATUS_MSK BIT(23)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_PS_TIMER_C_EARLY_INT_EN BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_RETRIEVE_BUFFERED_MSK BIT(22)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_RETRIEVE_BUFFERED_INT_MSK BIT(22)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_PS_TIMER_B_EARLY_INT_EN BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_RPWMINT2_MSK BIT(21)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_RPWM2INT_MSK BIT(21)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_PS_TIMER_A_EARLY_INT_EN BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_TSF_BIT32_TOGGLE_MSK_V1 BIT(20)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_TSF_BIT32_TOGGLE_INT_MSK BIT(20)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN BIT(20)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_TRIGGER_PKT_MSK BIT(19)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_PS_TIMER_C_INT_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FW_BTCMD_INTMSK BIT(18)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FW_BTCMD_INT_MSK BIT(18)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_PS_TIMER_B_INT_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_P2P_RFOFF_INTMSK BIT(17)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_P2P_RFOFF_INT_MSK BIT(17)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_PS_TIMER_A_INT_EN BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_P2P_RFON_INTMSK BIT(16)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_P2P_RFON_INT_MSK BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_CPUMGQ_TX_TIMER_INT_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_TXBCN1ERR_MSK BIT(15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_TX_BCN1ERR_INT_MSK BIT(15)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FS_PS_TIMEOUT2_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_TXBCN1OK_MSK BIT(14)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_TX_BCN1OK_INT_MSK BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FS_PS_TIMEOUT1_EN BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FT_ATIMEND_EMSK BIT(13)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FT_ATIMEND_E_MSK BIT(13)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FS_PS_TIMEOUT0_EN BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_BCNDMAINT_EMSK BIT(12)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_BCNDMAINT_E_MSK_V1 BIT(12)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FS_GTINT12_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_GTINT5_MSK BIT(11)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_GT5INT_MSK BIT(11)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FS_GTINT11_EN BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_EOSP_INT_MSK BIT(10)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FS_GTINT10_EN BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_RX_BCN_E_MSK BIT(9)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_RX_BCN_E_INT_MSK BIT(9)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FS_GTINT9_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_RPWM_INT_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_RPWMINT_MSK BIT(8)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FS_GTINT8_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_PSTIMER_MSK BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_PSTIMER_INT_MSK BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FS_GTINT7_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_TIMEOUT1_MSK BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_TIMEOUT1_INT_MSK BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FS_GTINT6_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_TIMEOUT0_MSK BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_TIMEOUT0_INT_MSK BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FS_GTINT5_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FT_GTINT4_MSK BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FT_GT4INT_MSK BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FS_GTINT4_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FT_GTINT3_MSK BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FT_GT3INT_MSK BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FS_GTINT3_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_GTINT2_MSK BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_GT2INT_MSK BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FS_GTINT2_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_GTINT1_MSK BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_GT1INT_MSK BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FS_GTINT1_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_GTINT0_MSK BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_GT0INT_MSK BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTIMR\t\t\t\t(Offset 0x0138) */\n\n#define BIT_FS_GTINT0_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_GT6INT BIT(31)\n#define BIT_TX_NULL1_INT BIT(30)\n#define BIT_TX_NULL0_INT BIT(29)\n#define BIT_MTI_BCNIVLEAR_INT BIT(28)\n#define BIT_ATIM_INT BIT(27)\n#define BIT_WWLAN_INT BIT(26)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_5_EARLY__INT BIT(26)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_C2H_W_READY BIT(25)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_4_EARLY__INT BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_TRL_MTR_INT BIT(24)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_3_EARLY__INT BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_CLR_PS_STATUS BIT(23)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_C_EARLY__INT BIT(23)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_2_EARLY__INT BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_RETRIEVE_BUFFERED_INT BIT(22)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_B_EARLY__INT BIT(22)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_1_EARLY__INT BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_RPWM2INT BIT(21)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_A_EARLY__INT BIT(21)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_0_EARLY__INT BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_TSF_BIT32_TOGGLE_INT_V1 BIT(20)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_CPUMGQ_TX_TIMER_EARLY_INT BIT(20)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_TRIGGER_PKT BIT(19)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_C_INT BIT(19)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_5_INT BIT(19)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FW_BTCMD_INT BIT(18)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_B_INT BIT(18)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_4_INT BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_P2P_RFOFF_INT BIT(17)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_A_INT BIT(17)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_3_INT BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_P2P_RFON_INT BIT(16)\n\n#define BIT_SHIFT_LLTINI_PDATA 16\n#define BIT_MASK_LLTINI_PDATA 0xff\n#define BIT_LLTINI_PDATA(x)                                                    \\\n\t(((x) & BIT_MASK_LLTINI_PDATA) << BIT_SHIFT_LLTINI_PDATA)\n#define BITS_LLTINI_PDATA (BIT_MASK_LLTINI_PDATA << BIT_SHIFT_LLTINI_PDATA)\n#define BIT_CLEAR_LLTINI_PDATA(x) ((x) & (~BITS_LLTINI_PDATA))\n#define BIT_GET_LLTINI_PDATA(x)                                                \\\n\t(((x) >> BIT_SHIFT_LLTINI_PDATA) & BIT_MASK_LLTINI_PDATA)\n#define BIT_SET_LLTINI_PDATA(x, v)                                             \\\n\t(BIT_CLEAR_LLTINI_PDATA(x) | BIT_LLTINI_PDATA(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_CPUMGQ_TX_TIMER_INT BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_TX_BCN1ERR_INT BIT(15)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FS_PS_TIMEOUT2_INT BIT(15)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_2_INT BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_TX_BCN1OK_INT BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FS_PS_TIMEOUT1_INT BIT(14)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_1_INT BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FT_ATIMEND_E BIT(13)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FS_PS_TIMEOUT0_INT BIT(13)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PS_TIMER_0_INT BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_BCNDMAINT_E_V1 BIT(12)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FS_GTINT12_INT BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_GT5INT BIT(11)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FS_GTINT11_INT BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_EOSP_INT BIT(10)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FS_GTINT10_INT BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_RX_BCN_E_INT BIT(9)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FS_GTINT9_INT BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_RPWMINT BIT(8)\n\n#define BIT_SHIFT_LLTINI_ADDR 8\n#define BIT_MASK_LLTINI_ADDR 0xff\n#define BIT_LLTINI_ADDR(x)                                                     \\\n\t(((x) & BIT_MASK_LLTINI_ADDR) << BIT_SHIFT_LLTINI_ADDR)\n#define BITS_LLTINI_ADDR (BIT_MASK_LLTINI_ADDR << BIT_SHIFT_LLTINI_ADDR)\n#define BIT_CLEAR_LLTINI_ADDR(x) ((x) & (~BITS_LLTINI_ADDR))\n#define BIT_GET_LLTINI_ADDR(x)                                                 \\\n\t(((x) >> BIT_SHIFT_LLTINI_ADDR) & BIT_MASK_LLTINI_ADDR)\n#define BIT_SET_LLTINI_ADDR(x, v)                                              \\\n\t(BIT_CLEAR_LLTINI_ADDR(x) | BIT_LLTINI_ADDR(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FS_GTINT8_INT BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_PSTIMER_INT BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FS_GTINT7_INT BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_TIMEOUT1_INT BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FS_GTINT6_INT BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_TIMEOUT0_INT BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FS_GTINT5_INT BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FT_GT4INT BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FS_GTINT4_INT BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FT_GT3INT BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FS_GTINT3_INT BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_GT2INT BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FS_GTINT2_INT BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_GT1INT BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FS_GTINT1_INT BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_GT0INT BIT(0)\n\n#define BIT_SHIFT_LLTINI_HDATA 0\n#define BIT_MASK_LLTINI_HDATA 0xff\n#define BIT_LLTINI_HDATA(x)                                                    \\\n\t(((x) & BIT_MASK_LLTINI_HDATA) << BIT_SHIFT_LLTINI_HDATA)\n#define BITS_LLTINI_HDATA (BIT_MASK_LLTINI_HDATA << BIT_SHIFT_LLTINI_HDATA)\n#define BIT_CLEAR_LLTINI_HDATA(x) ((x) & (~BITS_LLTINI_HDATA))\n#define BIT_GET_LLTINI_HDATA(x)                                                \\\n\t(((x) >> BIT_SHIFT_LLTINI_HDATA) & BIT_MASK_LLTINI_HDATA)\n#define BIT_SET_LLTINI_HDATA(x, v)                                             \\\n\t(BIT_CLEAR_LLTINI_HDATA(x) | BIT_LLTINI_HDATA(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTISR\t\t\t\t(Offset 0x013C) */\n\n#define BIT_FS_GTINT0_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PKTBUF_DBG_CTRL\t\t\t(Offset 0x0140) */\n\n#define BIT_SHIFT_PKTBUF_WRITE_EN 24\n#define BIT_MASK_PKTBUF_WRITE_EN 0xff\n#define BIT_PKTBUF_WRITE_EN(x)                                                 \\\n\t(((x) & BIT_MASK_PKTBUF_WRITE_EN) << BIT_SHIFT_PKTBUF_WRITE_EN)\n#define BITS_PKTBUF_WRITE_EN                                                   \\\n\t(BIT_MASK_PKTBUF_WRITE_EN << BIT_SHIFT_PKTBUF_WRITE_EN)\n#define BIT_CLEAR_PKTBUF_WRITE_EN(x) ((x) & (~BITS_PKTBUF_WRITE_EN))\n#define BIT_GET_PKTBUF_WRITE_EN(x)                                             \\\n\t(((x) >> BIT_SHIFT_PKTBUF_WRITE_EN) & BIT_MASK_PKTBUF_WRITE_EN)\n#define BIT_SET_PKTBUF_WRITE_EN(x, v)                                          \\\n\t(BIT_CLEAR_PKTBUF_WRITE_EN(x) | BIT_PKTBUF_WRITE_EN(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PKTBUF_DBG_CTRL\t\t\t(Offset 0x0140) */\n\n#define BIT_TXPKT_BUF_READ_EN BIT(23)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_PKTBUF_DBG_CTRL\t\t\t(Offset 0x0140) */\n\n#define BIT_TXPKTBUF_DBG BIT(23)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PKTBUF_DBG_CTRL\t\t\t(Offset 0x0140) */\n\n#define BIT_TXRPTBUF_DBG BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PKTBUF_DBG_CTRL\t\t\t(Offset 0x0140) */\n\n#define BIT_TXRPT_BUF_READ_EN BIT(20)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_PKTBUF_DBG_CTRL\t\t\t(Offset 0x0140) */\n\n#define BIT_TXRPTBUF_DBG_V2 BIT(20)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PKTBUF_DBG_CTRL\t\t\t(Offset 0x0140) */\n\n#define BIT_TXPKTBUF_DBG_V2 BIT(20)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PKTBUF_DBG_CTRL\t\t\t(Offset 0x0140) */\n\n#define BIT_RXPKT_BUF_READ_EN BIT(16)\n\n#define BIT_SHIFT_PKTBUF_ADDR 0\n#define BIT_MASK_PKTBUF_ADDR 0x1fff\n#define BIT_PKTBUF_ADDR(x)                                                     \\\n\t(((x) & BIT_MASK_PKTBUF_ADDR) << BIT_SHIFT_PKTBUF_ADDR)\n#define BITS_PKTBUF_ADDR (BIT_MASK_PKTBUF_ADDR << BIT_SHIFT_PKTBUF_ADDR)\n#define BIT_CLEAR_PKTBUF_ADDR(x) ((x) & (~BITS_PKTBUF_ADDR))\n#define BIT_GET_PKTBUF_ADDR(x)                                                 \\\n\t(((x) >> BIT_SHIFT_PKTBUF_ADDR) & BIT_MASK_PKTBUF_ADDR)\n#define BIT_SET_PKTBUF_ADDR(x, v)                                              \\\n\t(BIT_CLEAR_PKTBUF_ADDR(x) | BIT_PKTBUF_ADDR(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PKTBUF_DBG_DATA_L\t\t\t(Offset 0x0144) */\n\n#define BIT_SHIFT_PKTBUF_DBG_DATA_L 0\n#define BIT_MASK_PKTBUF_DBG_DATA_L 0xffffffffL\n#define BIT_PKTBUF_DBG_DATA_L(x)                                               \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_DATA_L) << BIT_SHIFT_PKTBUF_DBG_DATA_L)\n#define BITS_PKTBUF_DBG_DATA_L                                                 \\\n\t(BIT_MASK_PKTBUF_DBG_DATA_L << BIT_SHIFT_PKTBUF_DBG_DATA_L)\n#define BIT_CLEAR_PKTBUF_DBG_DATA_L(x) ((x) & (~BITS_PKTBUF_DBG_DATA_L))\n#define BIT_GET_PKTBUF_DBG_DATA_L(x)                                           \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L) & BIT_MASK_PKTBUF_DBG_DATA_L)\n#define BIT_SET_PKTBUF_DBG_DATA_L(x, v)                                        \\\n\t(BIT_CLEAR_PKTBUF_DBG_DATA_L(x) | BIT_PKTBUF_DBG_DATA_L(v))\n\n/* 2 REG_PKTBUF_DBG_DATA_H\t\t\t(Offset 0x0148) */\n\n#define BIT_SHIFT_PKTBUF_DBG_DATA_H 0\n#define BIT_MASK_PKTBUF_DBG_DATA_H 0xffffffffL\n#define BIT_PKTBUF_DBG_DATA_H(x)                                               \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_DATA_H) << BIT_SHIFT_PKTBUF_DBG_DATA_H)\n#define BITS_PKTBUF_DBG_DATA_H                                                 \\\n\t(BIT_MASK_PKTBUF_DBG_DATA_H << BIT_SHIFT_PKTBUF_DBG_DATA_H)\n#define BIT_CLEAR_PKTBUF_DBG_DATA_H(x) ((x) & (~BITS_PKTBUF_DBG_DATA_H))\n#define BIT_GET_PKTBUF_DBG_DATA_H(x)                                           \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H) & BIT_MASK_PKTBUF_DBG_DATA_H)\n#define BIT_SET_PKTBUF_DBG_DATA_H(x, v)                                        \\\n\t(BIT_CLEAR_PKTBUF_DBG_DATA_H(x) | BIT_PKTBUF_DBG_DATA_H(v))\n\n/* 2 REG_CPWM2\t\t\t\t(Offset 0x014C) */\n\n#define BIT_SHIFT_L0S_TO_RCVY_NUM 16\n#define BIT_MASK_L0S_TO_RCVY_NUM 0xff\n#define BIT_L0S_TO_RCVY_NUM(x)                                                 \\\n\t(((x) & BIT_MASK_L0S_TO_RCVY_NUM) << BIT_SHIFT_L0S_TO_RCVY_NUM)\n#define BITS_L0S_TO_RCVY_NUM                                                   \\\n\t(BIT_MASK_L0S_TO_RCVY_NUM << BIT_SHIFT_L0S_TO_RCVY_NUM)\n#define BIT_CLEAR_L0S_TO_RCVY_NUM(x) ((x) & (~BITS_L0S_TO_RCVY_NUM))\n#define BIT_GET_L0S_TO_RCVY_NUM(x)                                             \\\n\t(((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM) & BIT_MASK_L0S_TO_RCVY_NUM)\n#define BIT_SET_L0S_TO_RCVY_NUM(x, v)                                          \\\n\t(BIT_CLEAR_L0S_TO_RCVY_NUM(x) | BIT_L0S_TO_RCVY_NUM(v))\n\n#define BIT_CPWM2_TOGGLING BIT(15)\n\n#define BIT_SHIFT_CPWM2_MOD 0\n#define BIT_MASK_CPWM2_MOD 0x7fff\n#define BIT_CPWM2_MOD(x) (((x) & BIT_MASK_CPWM2_MOD) << BIT_SHIFT_CPWM2_MOD)\n#define BITS_CPWM2_MOD (BIT_MASK_CPWM2_MOD << BIT_SHIFT_CPWM2_MOD)\n#define BIT_CLEAR_CPWM2_MOD(x) ((x) & (~BITS_CPWM2_MOD))\n#define BIT_GET_CPWM2_MOD(x) (((x) >> BIT_SHIFT_CPWM2_MOD) & BIT_MASK_CPWM2_MOD)\n#define BIT_SET_CPWM2_MOD(x, v) (BIT_CLEAR_CPWM2_MOD(x) | BIT_CPWM2_MOD(v))\n\n/* 2 REG_TC0_CTRL\t\t\t\t(Offset 0x0150) */\n\n#define BIT_TC0INT_EN BIT(26)\n#define BIT_TC0MODE BIT(25)\n#define BIT_TC0EN BIT(24)\n\n#define BIT_SHIFT_TC0DATA 0\n#define BIT_MASK_TC0DATA 0xffffff\n#define BIT_TC0DATA(x) (((x) & BIT_MASK_TC0DATA) << BIT_SHIFT_TC0DATA)\n#define BITS_TC0DATA (BIT_MASK_TC0DATA << BIT_SHIFT_TC0DATA)\n#define BIT_CLEAR_TC0DATA(x) ((x) & (~BITS_TC0DATA))\n#define BIT_GET_TC0DATA(x) (((x) >> BIT_SHIFT_TC0DATA) & BIT_MASK_TC0DATA)\n#define BIT_SET_TC0DATA(x, v) (BIT_CLEAR_TC0DATA(x) | BIT_TC0DATA(v))\n\n/* 2 REG_TC1_CTRL\t\t\t\t(Offset 0x0154) */\n\n#define BIT_TC1INT_EN BIT(26)\n#define BIT_TC1MODE BIT(25)\n#define BIT_TC1EN BIT(24)\n\n#define BIT_SHIFT_TC1DATA 0\n#define BIT_MASK_TC1DATA 0xffffff\n#define BIT_TC1DATA(x) (((x) & BIT_MASK_TC1DATA) << BIT_SHIFT_TC1DATA)\n#define BITS_TC1DATA (BIT_MASK_TC1DATA << BIT_SHIFT_TC1DATA)\n#define BIT_CLEAR_TC1DATA(x) ((x) & (~BITS_TC1DATA))\n#define BIT_GET_TC1DATA(x) (((x) >> BIT_SHIFT_TC1DATA) & BIT_MASK_TC1DATA)\n#define BIT_SET_TC1DATA(x, v) (BIT_CLEAR_TC1DATA(x) | BIT_TC1DATA(v))\n\n/* 2 REG_TC2_CTRL\t\t\t\t(Offset 0x0158) */\n\n#define BIT_TC2INT_EN BIT(26)\n#define BIT_TC2MODE BIT(25)\n#define BIT_TC2EN BIT(24)\n\n#define BIT_SHIFT_TC2DATA 0\n#define BIT_MASK_TC2DATA 0xffffff\n#define BIT_TC2DATA(x) (((x) & BIT_MASK_TC2DATA) << BIT_SHIFT_TC2DATA)\n#define BITS_TC2DATA (BIT_MASK_TC2DATA << BIT_SHIFT_TC2DATA)\n#define BIT_CLEAR_TC2DATA(x) ((x) & (~BITS_TC2DATA))\n#define BIT_GET_TC2DATA(x) (((x) >> BIT_SHIFT_TC2DATA) & BIT_MASK_TC2DATA)\n#define BIT_SET_TC2DATA(x, v) (BIT_CLEAR_TC2DATA(x) | BIT_TC2DATA(v))\n\n/* 2 REG_TC3_CTRL\t\t\t\t(Offset 0x015C) */\n\n#define BIT_TC3INT_EN BIT(26)\n#define BIT_TC3MODE BIT(25)\n#define BIT_TC3EN BIT(24)\n\n#define BIT_SHIFT_TC3DATA 0\n#define BIT_MASK_TC3DATA 0xffffff\n#define BIT_TC3DATA(x) (((x) & BIT_MASK_TC3DATA) << BIT_SHIFT_TC3DATA)\n#define BITS_TC3DATA (BIT_MASK_TC3DATA << BIT_SHIFT_TC3DATA)\n#define BIT_CLEAR_TC3DATA(x) ((x) & (~BITS_TC3DATA))\n#define BIT_GET_TC3DATA(x) (((x) >> BIT_SHIFT_TC3DATA) & BIT_MASK_TC3DATA)\n#define BIT_SET_TC3DATA(x, v) (BIT_CLEAR_TC3DATA(x) | BIT_TC3DATA(v))\n\n/* 2 REG_TC4_CTRL\t\t\t\t(Offset 0x0160) */\n\n#define BIT_TC4INT_EN BIT(26)\n#define BIT_TC4MODE BIT(25)\n#define BIT_TC4EN BIT(24)\n\n#define BIT_SHIFT_TC4DATA 0\n#define BIT_MASK_TC4DATA 0xffffff\n#define BIT_TC4DATA(x) (((x) & BIT_MASK_TC4DATA) << BIT_SHIFT_TC4DATA)\n#define BITS_TC4DATA (BIT_MASK_TC4DATA << BIT_SHIFT_TC4DATA)\n#define BIT_CLEAR_TC4DATA(x) ((x) & (~BITS_TC4DATA))\n#define BIT_GET_TC4DATA(x) (((x) >> BIT_SHIFT_TC4DATA) & BIT_MASK_TC4DATA)\n#define BIT_SET_TC4DATA(x, v) (BIT_CLEAR_TC4DATA(x) | BIT_TC4DATA(v))\n\n/* 2 REG_TCUNIT_BASE\t\t\t\t(Offset 0x0164) */\n\n#define BIT_SHIFT_TCUNIT_BASE 0\n#define BIT_MASK_TCUNIT_BASE 0x3fff\n#define BIT_TCUNIT_BASE(x)                                                     \\\n\t(((x) & BIT_MASK_TCUNIT_BASE) << BIT_SHIFT_TCUNIT_BASE)\n#define BITS_TCUNIT_BASE (BIT_MASK_TCUNIT_BASE << BIT_SHIFT_TCUNIT_BASE)\n#define BIT_CLEAR_TCUNIT_BASE(x) ((x) & (~BITS_TCUNIT_BASE))\n#define BIT_GET_TCUNIT_BASE(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TCUNIT_BASE) & BIT_MASK_TCUNIT_BASE)\n#define BIT_SET_TCUNIT_BASE(x, v)                                              \\\n\t(BIT_CLEAR_TCUNIT_BASE(x) | BIT_TCUNIT_BASE(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TC5_CTRL\t\t\t\t(Offset 0x0168) */\n\n#define BIT_TC50INT_EN BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TC5_CTRL\t\t\t\t(Offset 0x0168) */\n\n#define BIT_TC5INT_EN BIT(26)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TC5_CTRL\t\t\t\t(Offset 0x0168) */\n\n#define BIT_TC5MODE BIT(25)\n#define BIT_TC5EN BIT(24)\n\n#define BIT_SHIFT_TC5DATA 0\n#define BIT_MASK_TC5DATA 0xffffff\n#define BIT_TC5DATA(x) (((x) & BIT_MASK_TC5DATA) << BIT_SHIFT_TC5DATA)\n#define BITS_TC5DATA (BIT_MASK_TC5DATA << BIT_SHIFT_TC5DATA)\n#define BIT_CLEAR_TC5DATA(x) ((x) & (~BITS_TC5DATA))\n#define BIT_GET_TC5DATA(x) (((x) >> BIT_SHIFT_TC5DATA) & BIT_MASK_TC5DATA)\n#define BIT_SET_TC5DATA(x, v) (BIT_CLEAR_TC5DATA(x) | BIT_TC5DATA(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TC6_CTRL\t\t\t\t(Offset 0x016C) */\n\n#define BIT_TC60INT_EN BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TC6_CTRL\t\t\t\t(Offset 0x016C) */\n\n#define BIT_TC6INT_EN BIT(26)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TC6_CTRL\t\t\t\t(Offset 0x016C) */\n\n#define BIT_TC6MODE BIT(25)\n#define BIT_TC6EN BIT(24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TC6_CTRL\t\t\t\t(Offset 0x016C) */\n\n#define BIT_SHIFT_SEQNUM_MID 16\n#define BIT_MASK_SEQNUM_MID 0xffff\n#define BIT_SEQNUM_MID(x) (((x) & BIT_MASK_SEQNUM_MID) << BIT_SHIFT_SEQNUM_MID)\n#define BITS_SEQNUM_MID (BIT_MASK_SEQNUM_MID << BIT_SHIFT_SEQNUM_MID)\n#define BIT_CLEAR_SEQNUM_MID(x) ((x) & (~BITS_SEQNUM_MID))\n#define BIT_GET_SEQNUM_MID(x)                                                  \\\n\t(((x) >> BIT_SHIFT_SEQNUM_MID) & BIT_MASK_SEQNUM_MID)\n#define BIT_SET_SEQNUM_MID(x, v) (BIT_CLEAR_SEQNUM_MID(x) | BIT_SEQNUM_MID(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TC6_CTRL\t\t\t\t(Offset 0x016C) */\n\n#define BIT_SHIFT_TC6DATA 0\n#define BIT_MASK_TC6DATA 0xffffff\n#define BIT_TC6DATA(x) (((x) & BIT_MASK_TC6DATA) << BIT_SHIFT_TC6DATA)\n#define BITS_TC6DATA (BIT_MASK_TC6DATA << BIT_SHIFT_TC6DATA)\n#define BIT_CLEAR_TC6DATA(x) ((x) & (~BITS_TC6DATA))\n#define BIT_GET_TC6DATA(x) (((x) >> BIT_SHIFT_TC6DATA) & BIT_MASK_TC6DATA)\n#define BIT_SET_TC6DATA(x, v) (BIT_CLEAR_TC6DATA(x) | BIT_TC6DATA(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MBIST_DRF_FAIL\t\t\t(Offset 0x0170) */\n\n#define BIT_SHIFT_WLON_MBIST_DRF_FAIL 30\n#define BIT_MASK_WLON_MBIST_DRF_FAIL 0x3\n#define BIT_WLON_MBIST_DRF_FAIL(x)                                             \\\n\t(((x) & BIT_MASK_WLON_MBIST_DRF_FAIL) << BIT_SHIFT_WLON_MBIST_DRF_FAIL)\n#define BITS_WLON_MBIST_DRF_FAIL                                               \\\n\t(BIT_MASK_WLON_MBIST_DRF_FAIL << BIT_SHIFT_WLON_MBIST_DRF_FAIL)\n#define BIT_CLEAR_WLON_MBIST_DRF_FAIL(x) ((x) & (~BITS_WLON_MBIST_DRF_FAIL))\n#define BIT_GET_WLON_MBIST_DRF_FAIL(x)                                         \\\n\t(((x) >> BIT_SHIFT_WLON_MBIST_DRF_FAIL) & BIT_MASK_WLON_MBIST_DRF_FAIL)\n#define BIT_SET_WLON_MBIST_DRF_FAIL(x, v)                                      \\\n\t(BIT_CLEAR_WLON_MBIST_DRF_FAIL(x) | BIT_WLON_MBIST_DRF_FAIL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBIST_FAIL\t\t\t\t(Offset 0x0170) */\n\n#define BIT_SHIFT_8051_MBIST_FAIL 26\n#define BIT_MASK_8051_MBIST_FAIL 0x7\n#define BIT_8051_MBIST_FAIL(x)                                                 \\\n\t(((x) & BIT_MASK_8051_MBIST_FAIL) << BIT_SHIFT_8051_MBIST_FAIL)\n#define BITS_8051_MBIST_FAIL                                                   \\\n\t(BIT_MASK_8051_MBIST_FAIL << BIT_SHIFT_8051_MBIST_FAIL)\n#define BIT_CLEAR_8051_MBIST_FAIL(x) ((x) & (~BITS_8051_MBIST_FAIL))\n#define BIT_GET_8051_MBIST_FAIL(x)                                             \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_FAIL) & BIT_MASK_8051_MBIST_FAIL)\n#define BIT_SET_8051_MBIST_FAIL(x, v)                                          \\\n\t(BIT_CLEAR_8051_MBIST_FAIL(x) | BIT_8051_MBIST_FAIL(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MBIST_DRF_FAIL\t\t\t(Offset 0x0170) */\n\n#define BIT_SHIFT_8051_MBIST_DRF_FAIL 26\n#define BIT_MASK_8051_MBIST_DRF_FAIL 0x3f\n#define BIT_8051_MBIST_DRF_FAIL(x)                                             \\\n\t(((x) & BIT_MASK_8051_MBIST_DRF_FAIL) << BIT_SHIFT_8051_MBIST_DRF_FAIL)\n#define BITS_8051_MBIST_DRF_FAIL                                               \\\n\t(BIT_MASK_8051_MBIST_DRF_FAIL << BIT_SHIFT_8051_MBIST_DRF_FAIL)\n#define BIT_CLEAR_8051_MBIST_DRF_FAIL(x) ((x) & (~BITS_8051_MBIST_DRF_FAIL))\n#define BIT_GET_8051_MBIST_DRF_FAIL(x)                                         \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_DRF_FAIL) & BIT_MASK_8051_MBIST_DRF_FAIL)\n#define BIT_SET_8051_MBIST_DRF_FAIL(x, v)                                      \\\n\t(BIT_CLEAR_8051_MBIST_DRF_FAIL(x) | BIT_8051_MBIST_DRF_FAIL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBIST_FAIL\t\t\t\t(Offset 0x0170) */\n\n#define BIT_SHIFT_USB_MBIST_FAIL 24\n#define BIT_MASK_USB_MBIST_FAIL 0x3\n#define BIT_USB_MBIST_FAIL(x)                                                  \\\n\t(((x) & BIT_MASK_USB_MBIST_FAIL) << BIT_SHIFT_USB_MBIST_FAIL)\n#define BITS_USB_MBIST_FAIL                                                    \\\n\t(BIT_MASK_USB_MBIST_FAIL << BIT_SHIFT_USB_MBIST_FAIL)\n#define BIT_CLEAR_USB_MBIST_FAIL(x) ((x) & (~BITS_USB_MBIST_FAIL))\n#define BIT_GET_USB_MBIST_FAIL(x)                                              \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_FAIL) & BIT_MASK_USB_MBIST_FAIL)\n#define BIT_SET_USB_MBIST_FAIL(x, v)                                           \\\n\t(BIT_CLEAR_USB_MBIST_FAIL(x) | BIT_USB_MBIST_FAIL(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MBIST_DRF_FAIL\t\t\t(Offset 0x0170) */\n\n#define BIT_SHIFT_USB_MBIST_DRF_FAIL 24\n#define BIT_MASK_USB_MBIST_DRF_FAIL 0x3\n#define BIT_USB_MBIST_DRF_FAIL(x)                                              \\\n\t(((x) & BIT_MASK_USB_MBIST_DRF_FAIL) << BIT_SHIFT_USB_MBIST_DRF_FAIL)\n#define BITS_USB_MBIST_DRF_FAIL                                                \\\n\t(BIT_MASK_USB_MBIST_DRF_FAIL << BIT_SHIFT_USB_MBIST_DRF_FAIL)\n#define BIT_CLEAR_USB_MBIST_DRF_FAIL(x) ((x) & (~BITS_USB_MBIST_DRF_FAIL))\n#define BIT_GET_USB_MBIST_DRF_FAIL(x)                                          \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL) & BIT_MASK_USB_MBIST_DRF_FAIL)\n#define BIT_SET_USB_MBIST_DRF_FAIL(x, v)                                       \\\n\t(BIT_CLEAR_USB_MBIST_DRF_FAIL(x) | BIT_USB_MBIST_DRF_FAIL(v))\n\n#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL 18\n#define BIT_MASK_PCIE_MBIST_DRF_FAIL 0x3f\n#define BIT_PCIE_MBIST_DRF_FAIL(x)                                             \\\n\t(((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL) << BIT_SHIFT_PCIE_MBIST_DRF_FAIL)\n#define BITS_PCIE_MBIST_DRF_FAIL                                               \\\n\t(BIT_MASK_PCIE_MBIST_DRF_FAIL << BIT_SHIFT_PCIE_MBIST_DRF_FAIL)\n#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL(x) ((x) & (~BITS_PCIE_MBIST_DRF_FAIL))\n#define BIT_GET_PCIE_MBIST_DRF_FAIL(x)                                         \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL) & BIT_MASK_PCIE_MBIST_DRF_FAIL)\n#define BIT_SET_PCIE_MBIST_DRF_FAIL(x, v)                                      \\\n\t(BIT_CLEAR_PCIE_MBIST_DRF_FAIL(x) | BIT_PCIE_MBIST_DRF_FAIL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBIST_FAIL\t\t\t\t(Offset 0x0170) */\n\n#define BIT_SHIFT_PCIE_MBIST_FAIL 16\n#define BIT_MASK_PCIE_MBIST_FAIL 0x3f\n#define BIT_PCIE_MBIST_FAIL(x)                                                 \\\n\t(((x) & BIT_MASK_PCIE_MBIST_FAIL) << BIT_SHIFT_PCIE_MBIST_FAIL)\n#define BITS_PCIE_MBIST_FAIL                                                   \\\n\t(BIT_MASK_PCIE_MBIST_FAIL << BIT_SHIFT_PCIE_MBIST_FAIL)\n#define BIT_CLEAR_PCIE_MBIST_FAIL(x) ((x) & (~BITS_PCIE_MBIST_FAIL))\n#define BIT_GET_PCIE_MBIST_FAIL(x)                                             \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_FAIL) & BIT_MASK_PCIE_MBIST_FAIL)\n#define BIT_SET_PCIE_MBIST_FAIL(x, v)                                          \\\n\t(BIT_CLEAR_PCIE_MBIST_FAIL(x) | BIT_PCIE_MBIST_FAIL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MBIST_DRF_FAIL\t\t\t(Offset 0x0170) */\n\n#define BIT_SHIFT_WLOFF_MBIST_DRF_FAIL 16\n#define BIT_MASK_WLOFF_MBIST_DRF_FAIL 0x3fff\n#define BIT_WLOFF_MBIST_DRF_FAIL(x)                                            \\\n\t(((x) & BIT_MASK_WLOFF_MBIST_DRF_FAIL)                                 \\\n\t << BIT_SHIFT_WLOFF_MBIST_DRF_FAIL)\n#define BITS_WLOFF_MBIST_DRF_FAIL                                              \\\n\t(BIT_MASK_WLOFF_MBIST_DRF_FAIL << BIT_SHIFT_WLOFF_MBIST_DRF_FAIL)\n#define BIT_CLEAR_WLOFF_MBIST_DRF_FAIL(x) ((x) & (~BITS_WLOFF_MBIST_DRF_FAIL))\n#define BIT_GET_WLOFF_MBIST_DRF_FAIL(x)                                        \\\n\t(((x) >> BIT_SHIFT_WLOFF_MBIST_DRF_FAIL) &                             \\\n\t BIT_MASK_WLOFF_MBIST_DRF_FAIL)\n#define BIT_SET_WLOFF_MBIST_DRF_FAIL(x, v)                                     \\\n\t(BIT_CLEAR_WLOFF_MBIST_DRF_FAIL(x) | BIT_WLOFF_MBIST_DRF_FAIL(v))\n\n#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL_V1 11\n#define BIT_MASK_PCIE_MBIST_DRF_FAIL_V1 0x1f\n#define BIT_PCIE_MBIST_DRF_FAIL_V1(x)                                          \\\n\t(((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL_V1)                               \\\n\t << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_V1)\n#define BITS_PCIE_MBIST_DRF_FAIL_V1                                            \\\n\t(BIT_MASK_PCIE_MBIST_DRF_FAIL_V1 << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_V1)\n#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL_V1(x)                                    \\\n\t((x) & (~BITS_PCIE_MBIST_DRF_FAIL_V1))\n#define BIT_GET_PCIE_MBIST_DRF_FAIL_V1(x)                                      \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL_V1) &                           \\\n\t BIT_MASK_PCIE_MBIST_DRF_FAIL_V1)\n#define BIT_SET_PCIE_MBIST_DRF_FAIL_V1(x, v)                                   \\\n\t(BIT_CLEAR_PCIE_MBIST_DRF_FAIL_V1(x) | BIT_PCIE_MBIST_DRF_FAIL_V1(v))\n\n#define BIT_SHIFT_USB_MBIST_DRF_FAIL_V1 4\n#define BIT_MASK_USB_MBIST_DRF_FAIL_V1 0x7f\n#define BIT_USB_MBIST_DRF_FAIL_V1(x)                                           \\\n\t(((x) & BIT_MASK_USB_MBIST_DRF_FAIL_V1)                                \\\n\t << BIT_SHIFT_USB_MBIST_DRF_FAIL_V1)\n#define BITS_USB_MBIST_DRF_FAIL_V1                                             \\\n\t(BIT_MASK_USB_MBIST_DRF_FAIL_V1 << BIT_SHIFT_USB_MBIST_DRF_FAIL_V1)\n#define BIT_CLEAR_USB_MBIST_DRF_FAIL_V1(x) ((x) & (~BITS_USB_MBIST_DRF_FAIL_V1))\n#define BIT_GET_USB_MBIST_DRF_FAIL_V1(x)                                       \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL_V1) &                            \\\n\t BIT_MASK_USB_MBIST_DRF_FAIL_V1)\n#define BIT_SET_USB_MBIST_DRF_FAIL_V1(x, v)                                    \\\n\t(BIT_CLEAR_USB_MBIST_DRF_FAIL_V1(x) | BIT_USB_MBIST_DRF_FAIL_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBIST_FAIL\t\t\t\t(Offset 0x0170) */\n\n#define BIT_SHIFT_MAC_MBIST_FAIL 0\n#define BIT_MASK_MAC_MBIST_FAIL 0xfff\n#define BIT_MAC_MBIST_FAIL(x)                                                  \\\n\t(((x) & BIT_MASK_MAC_MBIST_FAIL) << BIT_SHIFT_MAC_MBIST_FAIL)\n#define BITS_MAC_MBIST_FAIL                                                    \\\n\t(BIT_MASK_MAC_MBIST_FAIL << BIT_SHIFT_MAC_MBIST_FAIL)\n#define BIT_CLEAR_MAC_MBIST_FAIL(x) ((x) & (~BITS_MAC_MBIST_FAIL))\n#define BIT_GET_MAC_MBIST_FAIL(x)                                              \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_FAIL) & BIT_MASK_MAC_MBIST_FAIL)\n#define BIT_SET_MAC_MBIST_FAIL(x, v)                                           \\\n\t(BIT_CLEAR_MAC_MBIST_FAIL(x) | BIT_MAC_MBIST_FAIL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MBIST_DRF_FAIL\t\t\t(Offset 0x0170) */\n\n#define BIT_SHIFT_USB_WLON_MBIST_DRF_FAIL 0\n#define BIT_MASK_USB_WLON_MBIST_DRF_FAIL 0xf\n#define BIT_USB_WLON_MBIST_DRF_FAIL(x)                                         \\\n\t(((x) & BIT_MASK_USB_WLON_MBIST_DRF_FAIL)                              \\\n\t << BIT_SHIFT_USB_WLON_MBIST_DRF_FAIL)\n#define BITS_USB_WLON_MBIST_DRF_FAIL                                           \\\n\t(BIT_MASK_USB_WLON_MBIST_DRF_FAIL << BIT_SHIFT_USB_WLON_MBIST_DRF_FAIL)\n#define BIT_CLEAR_USB_WLON_MBIST_DRF_FAIL(x)                                   \\\n\t((x) & (~BITS_USB_WLON_MBIST_DRF_FAIL))\n#define BIT_GET_USB_WLON_MBIST_DRF_FAIL(x)                                     \\\n\t(((x) >> BIT_SHIFT_USB_WLON_MBIST_DRF_FAIL) &                          \\\n\t BIT_MASK_USB_WLON_MBIST_DRF_FAIL)\n#define BIT_SET_USB_WLON_MBIST_DRF_FAIL(x, v)                                  \\\n\t(BIT_CLEAR_USB_WLON_MBIST_DRF_FAIL(x) | BIT_USB_WLON_MBIST_DRF_FAIL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_MBIST_FAIL\t\t\t\t(Offset 0x0170) */\n\n#define BIT_SHIFT_MAC_MBIST_FAIL_DRF 0\n#define BIT_MASK_MAC_MBIST_FAIL_DRF 0x3ffff\n#define BIT_MAC_MBIST_FAIL_DRF(x)                                              \\\n\t(((x) & BIT_MASK_MAC_MBIST_FAIL_DRF) << BIT_SHIFT_MAC_MBIST_FAIL_DRF)\n#define BITS_MAC_MBIST_FAIL_DRF                                                \\\n\t(BIT_MASK_MAC_MBIST_FAIL_DRF << BIT_SHIFT_MAC_MBIST_FAIL_DRF)\n#define BIT_CLEAR_MAC_MBIST_FAIL_DRF(x) ((x) & (~BITS_MAC_MBIST_FAIL_DRF))\n#define BIT_GET_MAC_MBIST_FAIL_DRF(x)                                          \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF) & BIT_MASK_MAC_MBIST_FAIL_DRF)\n#define BIT_SET_MAC_MBIST_FAIL_DRF(x, v)                                       \\\n\t(BIT_CLEAR_MAC_MBIST_FAIL_DRF(x) | BIT_MAC_MBIST_FAIL_DRF(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_MBIST_FAIL\t\t\t\t(Offset 0x0170) */\n\n#define BIT_SHIFT_MAC_MBIST_FAIL_DRF_V1 0\n#define BIT_MASK_MAC_MBIST_FAIL_DRF_V1 0x7ffff\n#define BIT_MAC_MBIST_FAIL_DRF_V1(x)                                           \\\n\t(((x) & BIT_MASK_MAC_MBIST_FAIL_DRF_V1)                                \\\n\t << BIT_SHIFT_MAC_MBIST_FAIL_DRF_V1)\n#define BITS_MAC_MBIST_FAIL_DRF_V1                                             \\\n\t(BIT_MASK_MAC_MBIST_FAIL_DRF_V1 << BIT_SHIFT_MAC_MBIST_FAIL_DRF_V1)\n#define BIT_CLEAR_MAC_MBIST_FAIL_DRF_V1(x) ((x) & (~BITS_MAC_MBIST_FAIL_DRF_V1))\n#define BIT_GET_MAC_MBIST_FAIL_DRF_V1(x)                                       \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF_V1) &                            \\\n\t BIT_MASK_MAC_MBIST_FAIL_DRF_V1)\n#define BIT_SET_MAC_MBIST_FAIL_DRF_V1(x, v)                                    \\\n\t(BIT_CLEAR_MAC_MBIST_FAIL_DRF_V1(x) | BIT_MAC_MBIST_FAIL_DRF_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MBIST_DRF_FAIL\t\t\t(Offset 0x0170) */\n\n#define BIT_SHIFT_MAC_MBIST_DRF_FAIL 0\n#define BIT_MASK_MAC_MBIST_DRF_FAIL 0x3ffff\n#define BIT_MAC_MBIST_DRF_FAIL(x)                                              \\\n\t(((x) & BIT_MASK_MAC_MBIST_DRF_FAIL) << BIT_SHIFT_MAC_MBIST_DRF_FAIL)\n#define BITS_MAC_MBIST_DRF_FAIL                                                \\\n\t(BIT_MASK_MAC_MBIST_DRF_FAIL << BIT_SHIFT_MAC_MBIST_DRF_FAIL)\n#define BIT_CLEAR_MAC_MBIST_DRF_FAIL(x) ((x) & (~BITS_MAC_MBIST_DRF_FAIL))\n#define BIT_GET_MAC_MBIST_DRF_FAIL(x)                                          \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_DRF_FAIL) & BIT_MASK_MAC_MBIST_DRF_FAIL)\n#define BIT_SET_MAC_MBIST_DRF_FAIL(x, v)                                       \\\n\t(BIT_CLEAR_MAC_MBIST_DRF_FAIL(x) | BIT_MAC_MBIST_DRF_FAIL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBIST_START_PAUSE\t\t\t(Offset 0x0174) */\n\n#define BIT_SHIFT_8051_MBIST_START_PAUSE 26\n#define BIT_MASK_8051_MBIST_START_PAUSE 0x7\n#define BIT_8051_MBIST_START_PAUSE(x)                                          \\\n\t(((x) & BIT_MASK_8051_MBIST_START_PAUSE)                               \\\n\t << BIT_SHIFT_8051_MBIST_START_PAUSE)\n#define BITS_8051_MBIST_START_PAUSE                                            \\\n\t(BIT_MASK_8051_MBIST_START_PAUSE << BIT_SHIFT_8051_MBIST_START_PAUSE)\n#define BIT_CLEAR_8051_MBIST_START_PAUSE(x)                                    \\\n\t((x) & (~BITS_8051_MBIST_START_PAUSE))\n#define BIT_GET_8051_MBIST_START_PAUSE(x)                                      \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE) &                           \\\n\t BIT_MASK_8051_MBIST_START_PAUSE)\n#define BIT_SET_8051_MBIST_START_PAUSE(x, v)                                   \\\n\t(BIT_CLEAR_8051_MBIST_START_PAUSE(x) | BIT_8051_MBIST_START_PAUSE(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MBIST_START_PAUSE\t\t\t(Offset 0x0174) */\n\n#define BIT_SHIFT_8051_MBIST_START_PAUSE_V1 26\n#define BIT_MASK_8051_MBIST_START_PAUSE_V1 0x3f\n#define BIT_8051_MBIST_START_PAUSE_V1(x)                                       \\\n\t(((x) & BIT_MASK_8051_MBIST_START_PAUSE_V1)                            \\\n\t << BIT_SHIFT_8051_MBIST_START_PAUSE_V1)\n#define BITS_8051_MBIST_START_PAUSE_V1                                         \\\n\t(BIT_MASK_8051_MBIST_START_PAUSE_V1                                    \\\n\t << BIT_SHIFT_8051_MBIST_START_PAUSE_V1)\n#define BIT_CLEAR_8051_MBIST_START_PAUSE_V1(x)                                 \\\n\t((x) & (~BITS_8051_MBIST_START_PAUSE_V1))\n#define BIT_GET_8051_MBIST_START_PAUSE_V1(x)                                   \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_V1) &                        \\\n\t BIT_MASK_8051_MBIST_START_PAUSE_V1)\n#define BIT_SET_8051_MBIST_START_PAUSE_V1(x, v)                                \\\n\t(BIT_CLEAR_8051_MBIST_START_PAUSE_V1(x) |                              \\\n\t BIT_8051_MBIST_START_PAUSE_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBIST_START_PAUSE\t\t\t(Offset 0x0174) */\n\n#define BIT_SHIFT_USB_MBIST_START_PAUSE 24\n#define BIT_MASK_USB_MBIST_START_PAUSE 0x3\n#define BIT_USB_MBIST_START_PAUSE(x)                                           \\\n\t(((x) & BIT_MASK_USB_MBIST_START_PAUSE)                                \\\n\t << BIT_SHIFT_USB_MBIST_START_PAUSE)\n#define BITS_USB_MBIST_START_PAUSE                                             \\\n\t(BIT_MASK_USB_MBIST_START_PAUSE << BIT_SHIFT_USB_MBIST_START_PAUSE)\n#define BIT_CLEAR_USB_MBIST_START_PAUSE(x) ((x) & (~BITS_USB_MBIST_START_PAUSE))\n#define BIT_GET_USB_MBIST_START_PAUSE(x)                                       \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE) &                            \\\n\t BIT_MASK_USB_MBIST_START_PAUSE)\n#define BIT_SET_USB_MBIST_START_PAUSE(x, v)                                    \\\n\t(BIT_CLEAR_USB_MBIST_START_PAUSE(x) | BIT_USB_MBIST_START_PAUSE(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MBIST_START_PAUSE\t\t\t(Offset 0x0174) */\n\n#define BIT_SHIFT_USB_MBIST_START_PAUSE_V1 24\n#define BIT_MASK_USB_MBIST_START_PAUSE_V1 0x3\n#define BIT_USB_MBIST_START_PAUSE_V1(x)                                        \\\n\t(((x) & BIT_MASK_USB_MBIST_START_PAUSE_V1)                             \\\n\t << BIT_SHIFT_USB_MBIST_START_PAUSE_V1)\n#define BITS_USB_MBIST_START_PAUSE_V1                                          \\\n\t(BIT_MASK_USB_MBIST_START_PAUSE_V1                                     \\\n\t << BIT_SHIFT_USB_MBIST_START_PAUSE_V1)\n#define BIT_CLEAR_USB_MBIST_START_PAUSE_V1(x)                                  \\\n\t((x) & (~BITS_USB_MBIST_START_PAUSE_V1))\n#define BIT_GET_USB_MBIST_START_PAUSE_V1(x)                                    \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V1) &                         \\\n\t BIT_MASK_USB_MBIST_START_PAUSE_V1)\n#define BIT_SET_USB_MBIST_START_PAUSE_V1(x, v)                                 \\\n\t(BIT_CLEAR_USB_MBIST_START_PAUSE_V1(x) |                               \\\n\t BIT_USB_MBIST_START_PAUSE_V1(v))\n\n#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1 18\n#define BIT_MASK_PCIE_MBIST_START_PAUSE_V1 0x3f\n#define BIT_PCIE_MBIST_START_PAUSE_V1(x)                                       \\\n\t(((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V1)                            \\\n\t << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1)\n#define BITS_PCIE_MBIST_START_PAUSE_V1                                         \\\n\t(BIT_MASK_PCIE_MBIST_START_PAUSE_V1                                    \\\n\t << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1)\n#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1(x)                                 \\\n\t((x) & (~BITS_PCIE_MBIST_START_PAUSE_V1))\n#define BIT_GET_PCIE_MBIST_START_PAUSE_V1(x)                                   \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1) &                        \\\n\t BIT_MASK_PCIE_MBIST_START_PAUSE_V1)\n#define BIT_SET_PCIE_MBIST_START_PAUSE_V1(x, v)                                \\\n\t(BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1(x) |                              \\\n\t BIT_PCIE_MBIST_START_PAUSE_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBIST_START_PAUSE\t\t\t(Offset 0x0174) */\n\n#define BIT_SHIFT_PCIE_MBIST_START_PAUSE 16\n#define BIT_MASK_PCIE_MBIST_START_PAUSE 0x3f\n#define BIT_PCIE_MBIST_START_PAUSE(x)                                          \\\n\t(((x) & BIT_MASK_PCIE_MBIST_START_PAUSE)                               \\\n\t << BIT_SHIFT_PCIE_MBIST_START_PAUSE)\n#define BITS_PCIE_MBIST_START_PAUSE                                            \\\n\t(BIT_MASK_PCIE_MBIST_START_PAUSE << BIT_SHIFT_PCIE_MBIST_START_PAUSE)\n#define BIT_CLEAR_PCIE_MBIST_START_PAUSE(x)                                    \\\n\t((x) & (~BITS_PCIE_MBIST_START_PAUSE))\n#define BIT_GET_PCIE_MBIST_START_PAUSE(x)                                      \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE) &                           \\\n\t BIT_MASK_PCIE_MBIST_START_PAUSE)\n#define BIT_SET_PCIE_MBIST_START_PAUSE(x, v)                                   \\\n\t(BIT_CLEAR_PCIE_MBIST_START_PAUSE(x) | BIT_PCIE_MBIST_START_PAUSE(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MBIST_START_PAUSE\t\t\t(Offset 0x0174) */\n\n#define BIT_SHIFT_WLON_MBIST_START_PAUSE_V1 9\n#define BIT_MASK_WLON_MBIST_START_PAUSE_V1 0x3\n#define BIT_WLON_MBIST_START_PAUSE_V1(x)                                       \\\n\t(((x) & BIT_MASK_WLON_MBIST_START_PAUSE_V1)                            \\\n\t << BIT_SHIFT_WLON_MBIST_START_PAUSE_V1)\n#define BITS_WLON_MBIST_START_PAUSE_V1                                         \\\n\t(BIT_MASK_WLON_MBIST_START_PAUSE_V1                                    \\\n\t << BIT_SHIFT_WLON_MBIST_START_PAUSE_V1)\n#define BIT_CLEAR_WLON_MBIST_START_PAUSE_V1(x)                                 \\\n\t((x) & (~BITS_WLON_MBIST_START_PAUSE_V1))\n#define BIT_GET_WLON_MBIST_START_PAUSE_V1(x)                                   \\\n\t(((x) >> BIT_SHIFT_WLON_MBIST_START_PAUSE_V1) &                        \\\n\t BIT_MASK_WLON_MBIST_START_PAUSE_V1)\n#define BIT_SET_WLON_MBIST_START_PAUSE_V1(x, v)                                \\\n\t(BIT_CLEAR_WLON_MBIST_START_PAUSE_V1(x) |                              \\\n\t BIT_WLON_MBIST_START_PAUSE_V1(v))\n\n#define BIT_SHIFT_WLOFF_MBIST_START_PAUSE_V1 4\n#define BIT_MASK_WLOFF_MBIST_START_PAUSE_V1 0x1f\n#define BIT_WLOFF_MBIST_START_PAUSE_V1(x)                                      \\\n\t(((x) & BIT_MASK_WLOFF_MBIST_START_PAUSE_V1)                           \\\n\t << BIT_SHIFT_WLOFF_MBIST_START_PAUSE_V1)\n#define BITS_WLOFF_MBIST_START_PAUSE_V1                                        \\\n\t(BIT_MASK_WLOFF_MBIST_START_PAUSE_V1                                   \\\n\t << BIT_SHIFT_WLOFF_MBIST_START_PAUSE_V1)\n#define BIT_CLEAR_WLOFF_MBIST_START_PAUSE_V1(x)                                \\\n\t((x) & (~BITS_WLOFF_MBIST_START_PAUSE_V1))\n#define BIT_GET_WLOFF_MBIST_START_PAUSE_V1(x)                                  \\\n\t(((x) >> BIT_SHIFT_WLOFF_MBIST_START_PAUSE_V1) &                       \\\n\t BIT_MASK_WLOFF_MBIST_START_PAUSE_V1)\n#define BIT_SET_WLOFF_MBIST_START_PAUSE_V1(x, v)                               \\\n\t(BIT_CLEAR_WLOFF_MBIST_START_PAUSE_V1(x) |                             \\\n\t BIT_WLOFF_MBIST_START_PAUSE_V1(v))\n\n#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V2 2\n#define BIT_MASK_PCIE_MBIST_START_PAUSE_V2 0x3\n#define BIT_PCIE_MBIST_START_PAUSE_V2(x)                                       \\\n\t(((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V2)                            \\\n\t << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V2)\n#define BITS_PCIE_MBIST_START_PAUSE_V2                                         \\\n\t(BIT_MASK_PCIE_MBIST_START_PAUSE_V2                                    \\\n\t << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V2)\n#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V2(x)                                 \\\n\t((x) & (~BITS_PCIE_MBIST_START_PAUSE_V2))\n#define BIT_GET_PCIE_MBIST_START_PAUSE_V2(x)                                   \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V2) &                        \\\n\t BIT_MASK_PCIE_MBIST_START_PAUSE_V2)\n#define BIT_SET_PCIE_MBIST_START_PAUSE_V2(x, v)                                \\\n\t(BIT_CLEAR_PCIE_MBIST_START_PAUSE_V2(x) |                              \\\n\t BIT_PCIE_MBIST_START_PAUSE_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBIST_START_PAUSE\t\t\t(Offset 0x0174) */\n\n#define BIT_SHIFT_MAC_MBIST_START_PAUSE 0\n#define BIT_MASK_MAC_MBIST_START_PAUSE 0xfff\n#define BIT_MAC_MBIST_START_PAUSE(x)                                           \\\n\t(((x) & BIT_MASK_MAC_MBIST_START_PAUSE)                                \\\n\t << BIT_SHIFT_MAC_MBIST_START_PAUSE)\n#define BITS_MAC_MBIST_START_PAUSE                                             \\\n\t(BIT_MASK_MAC_MBIST_START_PAUSE << BIT_SHIFT_MAC_MBIST_START_PAUSE)\n#define BIT_CLEAR_MAC_MBIST_START_PAUSE(x) ((x) & (~BITS_MAC_MBIST_START_PAUSE))\n#define BIT_GET_MAC_MBIST_START_PAUSE(x)                                       \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE) &                            \\\n\t BIT_MASK_MAC_MBIST_START_PAUSE)\n#define BIT_SET_MAC_MBIST_START_PAUSE(x, v)                                    \\\n\t(BIT_CLEAR_MAC_MBIST_START_PAUSE(x) | BIT_MAC_MBIST_START_PAUSE(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MBIST_START_PAUSE\t\t\t(Offset 0x0174) */\n\n#define BIT_SHIFT_USB_MBIST_START_PAUSE_V2 0\n#define BIT_MASK_USB_MBIST_START_PAUSE_V2 0x3\n#define BIT_USB_MBIST_START_PAUSE_V2(x)                                        \\\n\t(((x) & BIT_MASK_USB_MBIST_START_PAUSE_V2)                             \\\n\t << BIT_SHIFT_USB_MBIST_START_PAUSE_V2)\n#define BITS_USB_MBIST_START_PAUSE_V2                                          \\\n\t(BIT_MASK_USB_MBIST_START_PAUSE_V2                                     \\\n\t << BIT_SHIFT_USB_MBIST_START_PAUSE_V2)\n#define BIT_CLEAR_USB_MBIST_START_PAUSE_V2(x)                                  \\\n\t((x) & (~BITS_USB_MBIST_START_PAUSE_V2))\n#define BIT_GET_USB_MBIST_START_PAUSE_V2(x)                                    \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V2) &                         \\\n\t BIT_MASK_USB_MBIST_START_PAUSE_V2)\n#define BIT_SET_USB_MBIST_START_PAUSE_V2(x, v)                                 \\\n\t(BIT_CLEAR_USB_MBIST_START_PAUSE_V2(x) |                               \\\n\t BIT_USB_MBIST_START_PAUSE_V2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MBIST_START_PAUSE\t\t\t(Offset 0x0174) */\n\n#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1 0\n#define BIT_MASK_MAC_MBIST_START_PAUSE_V1 0x3ffff\n#define BIT_MAC_MBIST_START_PAUSE_V1(x)                                        \\\n\t(((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1)                             \\\n\t << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1)\n#define BITS_MAC_MBIST_START_PAUSE_V1                                          \\\n\t(BIT_MASK_MAC_MBIST_START_PAUSE_V1                                     \\\n\t << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1)\n#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1(x)                                  \\\n\t((x) & (~BITS_MAC_MBIST_START_PAUSE_V1))\n#define BIT_GET_MAC_MBIST_START_PAUSE_V1(x)                                    \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1) &                         \\\n\t BIT_MASK_MAC_MBIST_START_PAUSE_V1)\n#define BIT_SET_MAC_MBIST_START_PAUSE_V1(x, v)                                 \\\n\t(BIT_CLEAR_MAC_MBIST_START_PAUSE_V1(x) |                               \\\n\t BIT_MAC_MBIST_START_PAUSE_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_MBIST_START_PAUSE\t\t\t(Offset 0x0174) */\n\n#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V2 0\n#define BIT_MASK_MAC_MBIST_START_PAUSE_V2 0x1ff\n#define BIT_MAC_MBIST_START_PAUSE_V2(x)                                        \\\n\t(((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V2)                             \\\n\t << BIT_SHIFT_MAC_MBIST_START_PAUSE_V2)\n#define BITS_MAC_MBIST_START_PAUSE_V2                                          \\\n\t(BIT_MASK_MAC_MBIST_START_PAUSE_V2                                     \\\n\t << BIT_SHIFT_MAC_MBIST_START_PAUSE_V2)\n#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V2(x)                                  \\\n\t((x) & (~BITS_MAC_MBIST_START_PAUSE_V2))\n#define BIT_GET_MAC_MBIST_START_PAUSE_V2(x)                                    \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V2) &                         \\\n\t BIT_MASK_MAC_MBIST_START_PAUSE_V2)\n#define BIT_SET_MAC_MBIST_START_PAUSE_V2(x, v)                                 \\\n\t(BIT_CLEAR_MAC_MBIST_START_PAUSE_V2(x) |                               \\\n\t BIT_MAC_MBIST_START_PAUSE_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBIST_DONE\t\t\t\t(Offset 0x0178) */\n\n#define BIT_SHIFT_8051_MBIST_DONE 26\n#define BIT_MASK_8051_MBIST_DONE 0x7\n#define BIT_8051_MBIST_DONE(x)                                                 \\\n\t(((x) & BIT_MASK_8051_MBIST_DONE) << BIT_SHIFT_8051_MBIST_DONE)\n#define BITS_8051_MBIST_DONE                                                   \\\n\t(BIT_MASK_8051_MBIST_DONE << BIT_SHIFT_8051_MBIST_DONE)\n#define BIT_CLEAR_8051_MBIST_DONE(x) ((x) & (~BITS_8051_MBIST_DONE))\n#define BIT_GET_8051_MBIST_DONE(x)                                             \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_DONE) & BIT_MASK_8051_MBIST_DONE)\n#define BIT_SET_8051_MBIST_DONE(x, v)                                          \\\n\t(BIT_CLEAR_8051_MBIST_DONE(x) | BIT_8051_MBIST_DONE(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MBIST_DONE\t\t\t\t(Offset 0x0178) */\n\n#define BIT_SHIFT_8051_MBIST_DONE_V1 26\n#define BIT_MASK_8051_MBIST_DONE_V1 0x3f\n#define BIT_8051_MBIST_DONE_V1(x)                                              \\\n\t(((x) & BIT_MASK_8051_MBIST_DONE_V1) << BIT_SHIFT_8051_MBIST_DONE_V1)\n#define BITS_8051_MBIST_DONE_V1                                                \\\n\t(BIT_MASK_8051_MBIST_DONE_V1 << BIT_SHIFT_8051_MBIST_DONE_V1)\n#define BIT_CLEAR_8051_MBIST_DONE_V1(x) ((x) & (~BITS_8051_MBIST_DONE_V1))\n#define BIT_GET_8051_MBIST_DONE_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_DONE_V1) & BIT_MASK_8051_MBIST_DONE_V1)\n#define BIT_SET_8051_MBIST_DONE_V1(x, v)                                       \\\n\t(BIT_CLEAR_8051_MBIST_DONE_V1(x) | BIT_8051_MBIST_DONE_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBIST_DONE\t\t\t\t(Offset 0x0178) */\n\n#define BIT_SHIFT_USB_MBIST_DONE 24\n#define BIT_MASK_USB_MBIST_DONE 0x3\n#define BIT_USB_MBIST_DONE(x)                                                  \\\n\t(((x) & BIT_MASK_USB_MBIST_DONE) << BIT_SHIFT_USB_MBIST_DONE)\n#define BITS_USB_MBIST_DONE                                                    \\\n\t(BIT_MASK_USB_MBIST_DONE << BIT_SHIFT_USB_MBIST_DONE)\n#define BIT_CLEAR_USB_MBIST_DONE(x) ((x) & (~BITS_USB_MBIST_DONE))\n#define BIT_GET_USB_MBIST_DONE(x)                                              \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_DONE) & BIT_MASK_USB_MBIST_DONE)\n#define BIT_SET_USB_MBIST_DONE(x, v)                                           \\\n\t(BIT_CLEAR_USB_MBIST_DONE(x) | BIT_USB_MBIST_DONE(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MBIST_DONE\t\t\t\t(Offset 0x0178) */\n\n#define BIT_SHIFT_USB_MBIST_DONE_V1 24\n#define BIT_MASK_USB_MBIST_DONE_V1 0x3\n#define BIT_USB_MBIST_DONE_V1(x)                                               \\\n\t(((x) & BIT_MASK_USB_MBIST_DONE_V1) << BIT_SHIFT_USB_MBIST_DONE_V1)\n#define BITS_USB_MBIST_DONE_V1                                                 \\\n\t(BIT_MASK_USB_MBIST_DONE_V1 << BIT_SHIFT_USB_MBIST_DONE_V1)\n#define BIT_CLEAR_USB_MBIST_DONE_V1(x) ((x) & (~BITS_USB_MBIST_DONE_V1))\n#define BIT_GET_USB_MBIST_DONE_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_DONE_V1) & BIT_MASK_USB_MBIST_DONE_V1)\n#define BIT_SET_USB_MBIST_DONE_V1(x, v)                                        \\\n\t(BIT_CLEAR_USB_MBIST_DONE_V1(x) | BIT_USB_MBIST_DONE_V1(v))\n\n#define BIT_SHIFT_PCIE_MBIST_DONE_V1 18\n#define BIT_MASK_PCIE_MBIST_DONE_V1 0x3f\n#define BIT_PCIE_MBIST_DONE_V1(x)                                              \\\n\t(((x) & BIT_MASK_PCIE_MBIST_DONE_V1) << BIT_SHIFT_PCIE_MBIST_DONE_V1)\n#define BITS_PCIE_MBIST_DONE_V1                                                \\\n\t(BIT_MASK_PCIE_MBIST_DONE_V1 << BIT_SHIFT_PCIE_MBIST_DONE_V1)\n#define BIT_CLEAR_PCIE_MBIST_DONE_V1(x) ((x) & (~BITS_PCIE_MBIST_DONE_V1))\n#define BIT_GET_PCIE_MBIST_DONE_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V1) & BIT_MASK_PCIE_MBIST_DONE_V1)\n#define BIT_SET_PCIE_MBIST_DONE_V1(x, v)                                       \\\n\t(BIT_CLEAR_PCIE_MBIST_DONE_V1(x) | BIT_PCIE_MBIST_DONE_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBIST_DONE\t\t\t\t(Offset 0x0178) */\n\n#define BIT_SHIFT_PCIE_MBIST_DONE 16\n#define BIT_MASK_PCIE_MBIST_DONE 0x3f\n#define BIT_PCIE_MBIST_DONE(x)                                                 \\\n\t(((x) & BIT_MASK_PCIE_MBIST_DONE) << BIT_SHIFT_PCIE_MBIST_DONE)\n#define BITS_PCIE_MBIST_DONE                                                   \\\n\t(BIT_MASK_PCIE_MBIST_DONE << BIT_SHIFT_PCIE_MBIST_DONE)\n#define BIT_CLEAR_PCIE_MBIST_DONE(x) ((x) & (~BITS_PCIE_MBIST_DONE))\n#define BIT_GET_PCIE_MBIST_DONE(x)                                             \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_DONE) & BIT_MASK_PCIE_MBIST_DONE)\n#define BIT_SET_PCIE_MBIST_DONE(x, v)                                          \\\n\t(BIT_CLEAR_PCIE_MBIST_DONE(x) | BIT_PCIE_MBIST_DONE(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MBIST_DONE\t\t\t\t(Offset 0x0178) */\n\n#define BIT_SHIFT_WLON_MBIST_DONE_V1 9\n#define BIT_MASK_WLON_MBIST_DONE_V1 0x3\n#define BIT_WLON_MBIST_DONE_V1(x)                                              \\\n\t(((x) & BIT_MASK_WLON_MBIST_DONE_V1) << BIT_SHIFT_WLON_MBIST_DONE_V1)\n#define BITS_WLON_MBIST_DONE_V1                                                \\\n\t(BIT_MASK_WLON_MBIST_DONE_V1 << BIT_SHIFT_WLON_MBIST_DONE_V1)\n#define BIT_CLEAR_WLON_MBIST_DONE_V1(x) ((x) & (~BITS_WLON_MBIST_DONE_V1))\n#define BIT_GET_WLON_MBIST_DONE_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_WLON_MBIST_DONE_V1) & BIT_MASK_WLON_MBIST_DONE_V1)\n#define BIT_SET_WLON_MBIST_DONE_V1(x, v)                                       \\\n\t(BIT_CLEAR_WLON_MBIST_DONE_V1(x) | BIT_WLON_MBIST_DONE_V1(v))\n\n#define BIT_SHIFT_WLOFF_MBIST_DONE_V1 4\n#define BIT_MASK_WLOFF_MBIST_DONE_V1 0x1f\n#define BIT_WLOFF_MBIST_DONE_V1(x)                                             \\\n\t(((x) & BIT_MASK_WLOFF_MBIST_DONE_V1) << BIT_SHIFT_WLOFF_MBIST_DONE_V1)\n#define BITS_WLOFF_MBIST_DONE_V1                                               \\\n\t(BIT_MASK_WLOFF_MBIST_DONE_V1 << BIT_SHIFT_WLOFF_MBIST_DONE_V1)\n#define BIT_CLEAR_WLOFF_MBIST_DONE_V1(x) ((x) & (~BITS_WLOFF_MBIST_DONE_V1))\n#define BIT_GET_WLOFF_MBIST_DONE_V1(x)                                         \\\n\t(((x) >> BIT_SHIFT_WLOFF_MBIST_DONE_V1) & BIT_MASK_WLOFF_MBIST_DONE_V1)\n#define BIT_SET_WLOFF_MBIST_DONE_V1(x, v)                                      \\\n\t(BIT_CLEAR_WLOFF_MBIST_DONE_V1(x) | BIT_WLOFF_MBIST_DONE_V1(v))\n\n#define BIT_SHIFT_PCIE_MBIST_DONE_V2 2\n#define BIT_MASK_PCIE_MBIST_DONE_V2 0x3\n#define BIT_PCIE_MBIST_DONE_V2(x)                                              \\\n\t(((x) & BIT_MASK_PCIE_MBIST_DONE_V2) << BIT_SHIFT_PCIE_MBIST_DONE_V2)\n#define BITS_PCIE_MBIST_DONE_V2                                                \\\n\t(BIT_MASK_PCIE_MBIST_DONE_V2 << BIT_SHIFT_PCIE_MBIST_DONE_V2)\n#define BIT_CLEAR_PCIE_MBIST_DONE_V2(x) ((x) & (~BITS_PCIE_MBIST_DONE_V2))\n#define BIT_GET_PCIE_MBIST_DONE_V2(x)                                          \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V2) & BIT_MASK_PCIE_MBIST_DONE_V2)\n#define BIT_SET_PCIE_MBIST_DONE_V2(x, v)                                       \\\n\t(BIT_CLEAR_PCIE_MBIST_DONE_V2(x) | BIT_PCIE_MBIST_DONE_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBIST_DONE\t\t\t\t(Offset 0x0178) */\n\n#define BIT_SHIFT_MAC_MBIST_DONE 0\n#define BIT_MASK_MAC_MBIST_DONE 0xfff\n#define BIT_MAC_MBIST_DONE(x)                                                  \\\n\t(((x) & BIT_MASK_MAC_MBIST_DONE) << BIT_SHIFT_MAC_MBIST_DONE)\n#define BITS_MAC_MBIST_DONE                                                    \\\n\t(BIT_MASK_MAC_MBIST_DONE << BIT_SHIFT_MAC_MBIST_DONE)\n#define BIT_CLEAR_MAC_MBIST_DONE(x) ((x) & (~BITS_MAC_MBIST_DONE))\n#define BIT_GET_MAC_MBIST_DONE(x)                                              \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_DONE) & BIT_MASK_MAC_MBIST_DONE)\n#define BIT_SET_MAC_MBIST_DONE(x, v)                                           \\\n\t(BIT_CLEAR_MAC_MBIST_DONE(x) | BIT_MAC_MBIST_DONE(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MBIST_DONE\t\t\t\t(Offset 0x0178) */\n\n#define BIT_SHIFT_USB_MBIST_DONE_V2 0\n#define BIT_MASK_USB_MBIST_DONE_V2 0x3\n#define BIT_USB_MBIST_DONE_V2(x)                                               \\\n\t(((x) & BIT_MASK_USB_MBIST_DONE_V2) << BIT_SHIFT_USB_MBIST_DONE_V2)\n#define BITS_USB_MBIST_DONE_V2                                                 \\\n\t(BIT_MASK_USB_MBIST_DONE_V2 << BIT_SHIFT_USB_MBIST_DONE_V2)\n#define BIT_CLEAR_USB_MBIST_DONE_V2(x) ((x) & (~BITS_USB_MBIST_DONE_V2))\n#define BIT_GET_USB_MBIST_DONE_V2(x)                                           \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_DONE_V2) & BIT_MASK_USB_MBIST_DONE_V2)\n#define BIT_SET_USB_MBIST_DONE_V2(x, v)                                        \\\n\t(BIT_CLEAR_USB_MBIST_DONE_V2(x) | BIT_USB_MBIST_DONE_V2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MBIST_DONE\t\t\t\t(Offset 0x0178) */\n\n#define BIT_SHIFT_MAC_MBIST_DONE_V1 0\n#define BIT_MASK_MAC_MBIST_DONE_V1 0x3ffff\n#define BIT_MAC_MBIST_DONE_V1(x)                                               \\\n\t(((x) & BIT_MASK_MAC_MBIST_DONE_V1) << BIT_SHIFT_MAC_MBIST_DONE_V1)\n#define BITS_MAC_MBIST_DONE_V1                                                 \\\n\t(BIT_MASK_MAC_MBIST_DONE_V1 << BIT_SHIFT_MAC_MBIST_DONE_V1)\n#define BIT_CLEAR_MAC_MBIST_DONE_V1(x) ((x) & (~BITS_MAC_MBIST_DONE_V1))\n#define BIT_GET_MAC_MBIST_DONE_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1) & BIT_MASK_MAC_MBIST_DONE_V1)\n#define BIT_SET_MAC_MBIST_DONE_V1(x, v)                                        \\\n\t(BIT_CLEAR_MAC_MBIST_DONE_V1(x) | BIT_MAC_MBIST_DONE_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_MBIST_DONE\t\t\t\t(Offset 0x0178) */\n\n#define BIT_SHIFT_MAC_MBIST_DONE_V2 0\n#define BIT_MASK_MAC_MBIST_DONE_V2 0x1ff\n#define BIT_MAC_MBIST_DONE_V2(x)                                               \\\n\t(((x) & BIT_MASK_MAC_MBIST_DONE_V2) << BIT_SHIFT_MAC_MBIST_DONE_V2)\n#define BITS_MAC_MBIST_DONE_V2                                                 \\\n\t(BIT_MASK_MAC_MBIST_DONE_V2 << BIT_SHIFT_MAC_MBIST_DONE_V2)\n#define BIT_CLEAR_MAC_MBIST_DONE_V2(x) ((x) & (~BITS_MAC_MBIST_DONE_V2))\n#define BIT_GET_MAC_MBIST_DONE_V2(x)                                           \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_DONE_V2) & BIT_MASK_MAC_MBIST_DONE_V2)\n#define BIT_SET_MAC_MBIST_DONE_V2(x, v)                                        \\\n\t(BIT_CLEAR_MAC_MBIST_DONE_V2(x) | BIT_MAC_MBIST_DONE_V2(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MBIST_NRML_FAIL\t\t\t(Offset 0x017C) */\n\n#define BIT_SHIFT_WLON_MBIST_NRML_FAIL 30\n#define BIT_MASK_WLON_MBIST_NRML_FAIL 0x3\n#define BIT_WLON_MBIST_NRML_FAIL(x)                                            \\\n\t(((x) & BIT_MASK_WLON_MBIST_NRML_FAIL)                                 \\\n\t << BIT_SHIFT_WLON_MBIST_NRML_FAIL)\n#define BITS_WLON_MBIST_NRML_FAIL                                              \\\n\t(BIT_MASK_WLON_MBIST_NRML_FAIL << BIT_SHIFT_WLON_MBIST_NRML_FAIL)\n#define BIT_CLEAR_WLON_MBIST_NRML_FAIL(x) ((x) & (~BITS_WLON_MBIST_NRML_FAIL))\n#define BIT_GET_WLON_MBIST_NRML_FAIL(x)                                        \\\n\t(((x) >> BIT_SHIFT_WLON_MBIST_NRML_FAIL) &                             \\\n\t BIT_MASK_WLON_MBIST_NRML_FAIL)\n#define BIT_SET_WLON_MBIST_NRML_FAIL(x, v)                                     \\\n\t(BIT_CLEAR_WLON_MBIST_NRML_FAIL(x) | BIT_WLON_MBIST_NRML_FAIL(v))\n\n#define BIT_SHIFT_WLOFF_MBIST_NRML_FAIL 16\n#define BIT_MASK_WLOFF_MBIST_NRML_FAIL 0x3fff\n#define BIT_WLOFF_MBIST_NRML_FAIL(x)                                           \\\n\t(((x) & BIT_MASK_WLOFF_MBIST_NRML_FAIL)                                \\\n\t << BIT_SHIFT_WLOFF_MBIST_NRML_FAIL)\n#define BITS_WLOFF_MBIST_NRML_FAIL                                             \\\n\t(BIT_MASK_WLOFF_MBIST_NRML_FAIL << BIT_SHIFT_WLOFF_MBIST_NRML_FAIL)\n#define BIT_CLEAR_WLOFF_MBIST_NRML_FAIL(x) ((x) & (~BITS_WLOFF_MBIST_NRML_FAIL))\n#define BIT_GET_WLOFF_MBIST_NRML_FAIL(x)                                       \\\n\t(((x) >> BIT_SHIFT_WLOFF_MBIST_NRML_FAIL) &                            \\\n\t BIT_MASK_WLOFF_MBIST_NRML_FAIL)\n#define BIT_SET_WLOFF_MBIST_NRML_FAIL(x, v)                                    \\\n\t(BIT_CLEAR_WLOFF_MBIST_NRML_FAIL(x) | BIT_WLOFF_MBIST_NRML_FAIL(v))\n\n#define BIT_SHIFT_PCIE_MBIST_NRML_FAIL 11\n#define BIT_MASK_PCIE_MBIST_NRML_FAIL 0x1f\n#define BIT_PCIE_MBIST_NRML_FAIL(x)                                            \\\n\t(((x) & BIT_MASK_PCIE_MBIST_NRML_FAIL)                                 \\\n\t << BIT_SHIFT_PCIE_MBIST_NRML_FAIL)\n#define BITS_PCIE_MBIST_NRML_FAIL                                              \\\n\t(BIT_MASK_PCIE_MBIST_NRML_FAIL << BIT_SHIFT_PCIE_MBIST_NRML_FAIL)\n#define BIT_CLEAR_PCIE_MBIST_NRML_FAIL(x) ((x) & (~BITS_PCIE_MBIST_NRML_FAIL))\n#define BIT_GET_PCIE_MBIST_NRML_FAIL(x)                                        \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_NRML_FAIL) &                             \\\n\t BIT_MASK_PCIE_MBIST_NRML_FAIL)\n#define BIT_SET_PCIE_MBIST_NRML_FAIL(x, v)                                     \\\n\t(BIT_CLEAR_PCIE_MBIST_NRML_FAIL(x) | BIT_PCIE_MBIST_NRML_FAIL(v))\n\n#define BIT_SHIFT_USB_MBIST_NRML_FAIL 4\n#define BIT_MASK_USB_MBIST_NRML_FAIL 0x7f\n#define BIT_USB_MBIST_NRML_FAIL(x)                                             \\\n\t(((x) & BIT_MASK_USB_MBIST_NRML_FAIL) << BIT_SHIFT_USB_MBIST_NRML_FAIL)\n#define BITS_USB_MBIST_NRML_FAIL                                               \\\n\t(BIT_MASK_USB_MBIST_NRML_FAIL << BIT_SHIFT_USB_MBIST_NRML_FAIL)\n#define BIT_CLEAR_USB_MBIST_NRML_FAIL(x) ((x) & (~BITS_USB_MBIST_NRML_FAIL))\n#define BIT_GET_USB_MBIST_NRML_FAIL(x)                                         \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_NRML_FAIL) & BIT_MASK_USB_MBIST_NRML_FAIL)\n#define BIT_SET_USB_MBIST_NRML_FAIL(x, v)                                      \\\n\t(BIT_CLEAR_USB_MBIST_NRML_FAIL(x) | BIT_USB_MBIST_NRML_FAIL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBIST_ROM_CRC_DATA\t\t\t(Offset 0x017C) */\n\n#define BIT_SHIFT_MBIST_ROM_CRC_DATA 0\n#define BIT_MASK_MBIST_ROM_CRC_DATA 0xffffffffL\n#define BIT_MBIST_ROM_CRC_DATA(x)                                              \\\n\t(((x) & BIT_MASK_MBIST_ROM_CRC_DATA) << BIT_SHIFT_MBIST_ROM_CRC_DATA)\n#define BITS_MBIST_ROM_CRC_DATA                                                \\\n\t(BIT_MASK_MBIST_ROM_CRC_DATA << BIT_SHIFT_MBIST_ROM_CRC_DATA)\n#define BIT_CLEAR_MBIST_ROM_CRC_DATA(x) ((x) & (~BITS_MBIST_ROM_CRC_DATA))\n#define BIT_GET_MBIST_ROM_CRC_DATA(x)                                          \\\n\t(((x) >> BIT_SHIFT_MBIST_ROM_CRC_DATA) & BIT_MASK_MBIST_ROM_CRC_DATA)\n#define BIT_SET_MBIST_ROM_CRC_DATA(x, v)                                       \\\n\t(BIT_CLEAR_MBIST_ROM_CRC_DATA(x) | BIT_MBIST_ROM_CRC_DATA(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MBIST_NRML_FAIL\t\t\t(Offset 0x017C) */\n\n#define BIT_SHIFT_USB_WLON_MBIST_NRML_FAIL 0\n#define BIT_MASK_USB_WLON_MBIST_NRML_FAIL 0xf\n#define BIT_USB_WLON_MBIST_NRML_FAIL(x)                                        \\\n\t(((x) & BIT_MASK_USB_WLON_MBIST_NRML_FAIL)                             \\\n\t << BIT_SHIFT_USB_WLON_MBIST_NRML_FAIL)\n#define BITS_USB_WLON_MBIST_NRML_FAIL                                          \\\n\t(BIT_MASK_USB_WLON_MBIST_NRML_FAIL                                     \\\n\t << BIT_SHIFT_USB_WLON_MBIST_NRML_FAIL)\n#define BIT_CLEAR_USB_WLON_MBIST_NRML_FAIL(x)                                  \\\n\t((x) & (~BITS_USB_WLON_MBIST_NRML_FAIL))\n#define BIT_GET_USB_WLON_MBIST_NRML_FAIL(x)                                    \\\n\t(((x) >> BIT_SHIFT_USB_WLON_MBIST_NRML_FAIL) &                         \\\n\t BIT_MASK_USB_WLON_MBIST_NRML_FAIL)\n#define BIT_SET_USB_WLON_MBIST_NRML_FAIL(x, v)                                 \\\n\t(BIT_CLEAR_USB_WLON_MBIST_NRML_FAIL(x) |                               \\\n\t BIT_USB_WLON_MBIST_NRML_FAIL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_MBIST_FAIL_NRML\t\t\t(Offset 0x017C) */\n\n#define BIT_SHIFT_MBIST_FAIL_NRML_V1 0\n#define BIT_MASK_MBIST_FAIL_NRML_V1 0x3ffff\n#define BIT_MBIST_FAIL_NRML_V1(x)                                              \\\n\t(((x) & BIT_MASK_MBIST_FAIL_NRML_V1) << BIT_SHIFT_MBIST_FAIL_NRML_V1)\n#define BITS_MBIST_FAIL_NRML_V1                                                \\\n\t(BIT_MASK_MBIST_FAIL_NRML_V1 << BIT_SHIFT_MBIST_FAIL_NRML_V1)\n#define BIT_CLEAR_MBIST_FAIL_NRML_V1(x) ((x) & (~BITS_MBIST_FAIL_NRML_V1))\n#define BIT_GET_MBIST_FAIL_NRML_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V1) & BIT_MASK_MBIST_FAIL_NRML_V1)\n#define BIT_SET_MBIST_FAIL_NRML_V1(x, v)                                       \\\n\t(BIT_CLEAR_MBIST_FAIL_NRML_V1(x) | BIT_MBIST_FAIL_NRML_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_MBIST_FAIL_NRML\t\t\t(Offset 0x017C) */\n\n#define BIT_SHIFT_MBIST_FAIL_NRML_V2 0\n#define BIT_MASK_MBIST_FAIL_NRML_V2 0x7ffff\n#define BIT_MBIST_FAIL_NRML_V2(x)                                              \\\n\t(((x) & BIT_MASK_MBIST_FAIL_NRML_V2) << BIT_SHIFT_MBIST_FAIL_NRML_V2)\n#define BITS_MBIST_FAIL_NRML_V2                                                \\\n\t(BIT_MASK_MBIST_FAIL_NRML_V2 << BIT_SHIFT_MBIST_FAIL_NRML_V2)\n#define BIT_CLEAR_MBIST_FAIL_NRML_V2(x) ((x) & (~BITS_MBIST_FAIL_NRML_V2))\n#define BIT_GET_MBIST_FAIL_NRML_V2(x)                                          \\\n\t(((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V2) & BIT_MASK_MBIST_FAIL_NRML_V2)\n#define BIT_SET_MBIST_FAIL_NRML_V2(x, v)                                       \\\n\t(BIT_CLEAR_MBIST_FAIL_NRML_V2(x) | BIT_MBIST_FAIL_NRML_V2(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_MBIST_FAIL_NRML\t\t\t(Offset 0x017C) */\n\n#define BIT_SHIFT_MBIST_FAIL_NRML 0\n#define BIT_MASK_MBIST_FAIL_NRML 0xffffffffL\n#define BIT_MBIST_FAIL_NRML(x)                                                 \\\n\t(((x) & BIT_MASK_MBIST_FAIL_NRML) << BIT_SHIFT_MBIST_FAIL_NRML)\n#define BITS_MBIST_FAIL_NRML                                                   \\\n\t(BIT_MASK_MBIST_FAIL_NRML << BIT_SHIFT_MBIST_FAIL_NRML)\n#define BIT_CLEAR_MBIST_FAIL_NRML(x) ((x) & (~BITS_MBIST_FAIL_NRML))\n#define BIT_GET_MBIST_FAIL_NRML(x)                                             \\\n\t(((x) >> BIT_SHIFT_MBIST_FAIL_NRML) & BIT_MASK_MBIST_FAIL_NRML)\n#define BIT_SET_MBIST_FAIL_NRML(x, v)                                          \\\n\t(BIT_CLEAR_MBIST_FAIL_NRML(x) | BIT_MBIST_FAIL_NRML(v))\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD 0xffffffffffffffffffffffffffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD(x)                                              \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD)\n#define BITS_R_WMAC_IPV6_MYIPAD                                                \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD << BIT_SHIFT_R_WMAC_IPV6_MYIPAD)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD) & BIT_MASK_R_WMAC_IPV6_MYIPAD)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD(x, v)                                       \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD(x) | BIT_R_WMAC_IPV6_MYIPAD(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AES_DECRPT_DATA\t\t\t(Offset 0x0180) */\n\n#define BIT_SHIFT_IPS_CFG_ADDR 0\n#define BIT_MASK_IPS_CFG_ADDR 0xff\n#define BIT_IPS_CFG_ADDR(x)                                                    \\\n\t(((x) & BIT_MASK_IPS_CFG_ADDR) << BIT_SHIFT_IPS_CFG_ADDR)\n#define BITS_IPS_CFG_ADDR (BIT_MASK_IPS_CFG_ADDR << BIT_SHIFT_IPS_CFG_ADDR)\n#define BIT_CLEAR_IPS_CFG_ADDR(x) ((x) & (~BITS_IPS_CFG_ADDR))\n#define BIT_GET_IPS_CFG_ADDR(x)                                                \\\n\t(((x) >> BIT_SHIFT_IPS_CFG_ADDR) & BIT_MASK_IPS_CFG_ADDR)\n#define BIT_SET_IPS_CFG_ADDR(x, v)                                             \\\n\t(BIT_CLEAR_IPS_CFG_ADDR(x) | BIT_IPS_CFG_ADDR(v))\n\n/* 2 REG_AES_DECRPT_CFG\t\t\t(Offset 0x0184) */\n\n#define BIT_SHIFT_IPS_CFG_DATA 0\n#define BIT_MASK_IPS_CFG_DATA 0xffffffffL\n#define BIT_IPS_CFG_DATA(x)                                                    \\\n\t(((x) & BIT_MASK_IPS_CFG_DATA) << BIT_SHIFT_IPS_CFG_DATA)\n#define BITS_IPS_CFG_DATA (BIT_MASK_IPS_CFG_DATA << BIT_SHIFT_IPS_CFG_DATA)\n#define BIT_CLEAR_IPS_CFG_DATA(x) ((x) & (~BITS_IPS_CFG_DATA))\n#define BIT_GET_IPS_CFG_DATA(x)                                                \\\n\t(((x) >> BIT_SHIFT_IPS_CFG_DATA) & BIT_MASK_IPS_CFG_DATA)\n#define BIT_SET_IPS_CFG_DATA(x, v)                                             \\\n\t(BIT_CLEAR_IPS_CFG_DATA(x) | BIT_IPS_CFG_DATA(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIOE_CTRL\t\t\t\t(Offset 0x0188) */\n\n#define BIT_HIOE_CFG_FILE_LOC_SEL BIT(31)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIOE_CTRL\t\t\t\t(Offset 0x0188) */\n\n#define BIT_HIOE_WRITE_REQ BIT(30)\n#define BIT_HIOE_READ_REQ BIT(29)\n#define BIT_INST_FORMAT_ERR BIT(25)\n#define BIT_OP_TIMEOUT_ERR BIT(24)\n\n#define BIT_SHIFT_HIOE_OP_TIMEOUT 16\n#define BIT_MASK_HIOE_OP_TIMEOUT 0xff\n#define BIT_HIOE_OP_TIMEOUT(x)                                                 \\\n\t(((x) & BIT_MASK_HIOE_OP_TIMEOUT) << BIT_SHIFT_HIOE_OP_TIMEOUT)\n#define BITS_HIOE_OP_TIMEOUT                                                   \\\n\t(BIT_MASK_HIOE_OP_TIMEOUT << BIT_SHIFT_HIOE_OP_TIMEOUT)\n#define BIT_CLEAR_HIOE_OP_TIMEOUT(x) ((x) & (~BITS_HIOE_OP_TIMEOUT))\n#define BIT_GET_HIOE_OP_TIMEOUT(x)                                             \\\n\t(((x) >> BIT_SHIFT_HIOE_OP_TIMEOUT) & BIT_MASK_HIOE_OP_TIMEOUT)\n#define BIT_SET_HIOE_OP_TIMEOUT(x, v)                                          \\\n\t(BIT_CLEAR_HIOE_OP_TIMEOUT(x) | BIT_HIOE_OP_TIMEOUT(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MBIST_READ_BIST_RPT_V1\t\t(Offset 0x0188) */\n\n#define BIT_SHIFT_MBIST_READ_BIST_RPT 0\n#define BIT_MASK_MBIST_READ_BIST_RPT 0xffffffffL\n#define BIT_MBIST_READ_BIST_RPT(x)                                             \\\n\t(((x) & BIT_MASK_MBIST_READ_BIST_RPT) << BIT_SHIFT_MBIST_READ_BIST_RPT)\n#define BITS_MBIST_READ_BIST_RPT                                               \\\n\t(BIT_MASK_MBIST_READ_BIST_RPT << BIT_SHIFT_MBIST_READ_BIST_RPT)\n#define BIT_CLEAR_MBIST_READ_BIST_RPT(x) ((x) & (~BITS_MBIST_READ_BIST_RPT))\n#define BIT_GET_MBIST_READ_BIST_RPT(x)                                         \\\n\t(((x) >> BIT_SHIFT_MBIST_READ_BIST_RPT) & BIT_MASK_MBIST_READ_BIST_RPT)\n#define BIT_SET_MBIST_READ_BIST_RPT(x, v)                                      \\\n\t(BIT_CLEAR_MBIST_READ_BIST_RPT(x) | BIT_MBIST_READ_BIST_RPT(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIOE_CTRL\t\t\t\t(Offset 0x0188) */\n\n#define BIT_SHIFT_BITDATA_CHECKSUM 0\n#define BIT_MASK_BITDATA_CHECKSUM 0xffff\n#define BIT_BITDATA_CHECKSUM(x)                                                \\\n\t(((x) & BIT_MASK_BITDATA_CHECKSUM) << BIT_SHIFT_BITDATA_CHECKSUM)\n#define BITS_BITDATA_CHECKSUM                                                  \\\n\t(BIT_MASK_BITDATA_CHECKSUM << BIT_SHIFT_BITDATA_CHECKSUM)\n#define BIT_CLEAR_BITDATA_CHECKSUM(x) ((x) & (~BITS_BITDATA_CHECKSUM))\n#define BIT_GET_BITDATA_CHECKSUM(x)                                            \\\n\t(((x) >> BIT_SHIFT_BITDATA_CHECKSUM) & BIT_MASK_BITDATA_CHECKSUM)\n#define BIT_SET_BITDATA_CHECKSUM(x, v)                                         \\\n\t(BIT_CLEAR_BITDATA_CHECKSUM(x) | BIT_BITDATA_CHECKSUM(v))\n\n/* 2 REG_HIOE_CFG_FILE\t\t\t(Offset 0x018C) */\n\n#define BIT_SHIFT_TXBF_END_ADDR 16\n#define BIT_MASK_TXBF_END_ADDR 0xffff\n#define BIT_TXBF_END_ADDR(x)                                                   \\\n\t(((x) & BIT_MASK_TXBF_END_ADDR) << BIT_SHIFT_TXBF_END_ADDR)\n#define BITS_TXBF_END_ADDR (BIT_MASK_TXBF_END_ADDR << BIT_SHIFT_TXBF_END_ADDR)\n#define BIT_CLEAR_TXBF_END_ADDR(x) ((x) & (~BITS_TXBF_END_ADDR))\n#define BIT_GET_TXBF_END_ADDR(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXBF_END_ADDR) & BIT_MASK_TXBF_END_ADDR)\n#define BIT_SET_TXBF_END_ADDR(x, v)                                            \\\n\t(BIT_CLEAR_TXBF_END_ADDR(x) | BIT_TXBF_END_ADDR(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_MACCLKFRQ\t\t\t\t(Offset 0x018C) */\n\n#define BIT_SHIFT_MACCLK_FREQ_LOW32 0\n#define BIT_MASK_MACCLK_FREQ_LOW32 0xffffffffL\n#define BIT_MACCLK_FREQ_LOW32(x)                                               \\\n\t(((x) & BIT_MASK_MACCLK_FREQ_LOW32) << BIT_SHIFT_MACCLK_FREQ_LOW32)\n#define BITS_MACCLK_FREQ_LOW32                                                 \\\n\t(BIT_MASK_MACCLK_FREQ_LOW32 << BIT_SHIFT_MACCLK_FREQ_LOW32)\n#define BIT_CLEAR_MACCLK_FREQ_LOW32(x) ((x) & (~BITS_MACCLK_FREQ_LOW32))\n#define BIT_GET_MACCLK_FREQ_LOW32(x)                                           \\\n\t(((x) >> BIT_SHIFT_MACCLK_FREQ_LOW32) & BIT_MASK_MACCLK_FREQ_LOW32)\n#define BIT_SET_MACCLK_FREQ_LOW32(x, v)                                        \\\n\t(BIT_CLEAR_MACCLK_FREQ_LOW32(x) | BIT_MACCLK_FREQ_LOW32(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIOE_CFG_FILE\t\t\t(Offset 0x018C) */\n\n#define BIT_SHIFT_TXBF_STR_ADDR 0\n#define BIT_MASK_TXBF_STR_ADDR 0xffff\n#define BIT_TXBF_STR_ADDR(x)                                                   \\\n\t(((x) & BIT_MASK_TXBF_STR_ADDR) << BIT_SHIFT_TXBF_STR_ADDR)\n#define BITS_TXBF_STR_ADDR (BIT_MASK_TXBF_STR_ADDR << BIT_SHIFT_TXBF_STR_ADDR)\n#define BIT_CLEAR_TXBF_STR_ADDR(x) ((x) & (~BITS_TXBF_STR_ADDR))\n#define BIT_GET_TXBF_STR_ADDR(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXBF_STR_ADDR) & BIT_MASK_TXBF_STR_ADDR)\n#define BIT_SET_TXBF_STR_ADDR(x, v)                                            \\\n\t(BIT_CLEAR_TXBF_STR_ADDR(x) | BIT_TXBF_STR_ADDR(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TMETER\t\t\t\t(Offset 0x0190) */\n\n#define BIT_TEMP_VALID BIT(31)\n\n#define BIT_SHIFT_TEMP_VALUE 24\n#define BIT_MASK_TEMP_VALUE 0x3f\n#define BIT_TEMP_VALUE(x) (((x) & BIT_MASK_TEMP_VALUE) << BIT_SHIFT_TEMP_VALUE)\n#define BITS_TEMP_VALUE (BIT_MASK_TEMP_VALUE << BIT_SHIFT_TEMP_VALUE)\n#define BIT_CLEAR_TEMP_VALUE(x) ((x) & (~BITS_TEMP_VALUE))\n#define BIT_GET_TEMP_VALUE(x)                                                  \\\n\t(((x) >> BIT_SHIFT_TEMP_VALUE) & BIT_MASK_TEMP_VALUE)\n#define BIT_SET_TEMP_VALUE(x, v) (BIT_CLEAR_TEMP_VALUE(x) | BIT_TEMP_VALUE(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TMETER\t\t\t\t(Offset 0x0190) */\n\n#define BIT_SHIFT_NCO_OUTCLK_FREQ 12\n#define BIT_MASK_NCO_OUTCLK_FREQ 0xfffff\n#define BIT_NCO_OUTCLK_FREQ(x)                                                 \\\n\t(((x) & BIT_MASK_NCO_OUTCLK_FREQ) << BIT_SHIFT_NCO_OUTCLK_FREQ)\n#define BITS_NCO_OUTCLK_FREQ                                                   \\\n\t(BIT_MASK_NCO_OUTCLK_FREQ << BIT_SHIFT_NCO_OUTCLK_FREQ)\n#define BIT_CLEAR_NCO_OUTCLK_FREQ(x) ((x) & (~BITS_NCO_OUTCLK_FREQ))\n#define BIT_GET_NCO_OUTCLK_FREQ(x)                                             \\\n\t(((x) >> BIT_SHIFT_NCO_OUTCLK_FREQ) & BIT_MASK_NCO_OUTCLK_FREQ)\n#define BIT_SET_NCO_OUTCLK_FREQ(x, v)                                          \\\n\t(BIT_CLEAR_NCO_OUTCLK_FREQ(x) | BIT_NCO_OUTCLK_FREQ(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TMETER\t\t\t\t(Offset 0x0190) */\n\n#define BIT_SHIFT_REG_TMETER_TIMER 8\n#define BIT_MASK_REG_TMETER_TIMER 0xfff\n#define BIT_REG_TMETER_TIMER(x)                                                \\\n\t(((x) & BIT_MASK_REG_TMETER_TIMER) << BIT_SHIFT_REG_TMETER_TIMER)\n#define BITS_REG_TMETER_TIMER                                                  \\\n\t(BIT_MASK_REG_TMETER_TIMER << BIT_SHIFT_REG_TMETER_TIMER)\n#define BIT_CLEAR_REG_TMETER_TIMER(x) ((x) & (~BITS_REG_TMETER_TIMER))\n#define BIT_GET_REG_TMETER_TIMER(x)                                            \\\n\t(((x) >> BIT_SHIFT_REG_TMETER_TIMER) & BIT_MASK_REG_TMETER_TIMER)\n#define BIT_SET_REG_TMETER_TIMER(x, v)                                         \\\n\t(BIT_CLEAR_REG_TMETER_TIMER(x) | BIT_REG_TMETER_TIMER(v))\n\n#define BIT_SHIFT_REG_TEMP_DELTA 2\n#define BIT_MASK_REG_TEMP_DELTA 0x3f\n#define BIT_REG_TEMP_DELTA(x)                                                  \\\n\t(((x) & BIT_MASK_REG_TEMP_DELTA) << BIT_SHIFT_REG_TEMP_DELTA)\n#define BITS_REG_TEMP_DELTA                                                    \\\n\t(BIT_MASK_REG_TEMP_DELTA << BIT_SHIFT_REG_TEMP_DELTA)\n#define BIT_CLEAR_REG_TEMP_DELTA(x) ((x) & (~BITS_REG_TEMP_DELTA))\n#define BIT_GET_REG_TEMP_DELTA(x)                                              \\\n\t(((x) >> BIT_SHIFT_REG_TEMP_DELTA) & BIT_MASK_REG_TEMP_DELTA)\n#define BIT_SET_REG_TEMP_DELTA(x, v)                                           \\\n\t(BIT_CLEAR_REG_TEMP_DELTA(x) | BIT_REG_TEMP_DELTA(v))\n\n#define BIT_REG_TMETER_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TMETER\t\t\t\t(Offset 0x0190) */\n\n#define BIT_SHIFT_MACCLK_FREQ_HIGH10 0\n#define BIT_MASK_MACCLK_FREQ_HIGH10 0x3ff\n#define BIT_MACCLK_FREQ_HIGH10(x)                                              \\\n\t(((x) & BIT_MASK_MACCLK_FREQ_HIGH10) << BIT_SHIFT_MACCLK_FREQ_HIGH10)\n#define BITS_MACCLK_FREQ_HIGH10                                                \\\n\t(BIT_MASK_MACCLK_FREQ_HIGH10 << BIT_SHIFT_MACCLK_FREQ_HIGH10)\n#define BIT_CLEAR_MACCLK_FREQ_HIGH10(x) ((x) & (~BITS_MACCLK_FREQ_HIGH10))\n#define BIT_GET_MACCLK_FREQ_HIGH10(x)                                          \\\n\t(((x) >> BIT_SHIFT_MACCLK_FREQ_HIGH10) & BIT_MASK_MACCLK_FREQ_HIGH10)\n#define BIT_SET_MACCLK_FREQ_HIGH10(x, v)                                       \\\n\t(BIT_CLEAR_MACCLK_FREQ_HIGH10(x) | BIT_MACCLK_FREQ_HIGH10(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_OSC_32K_CTRL\t\t\t(Offset 0x0194) */\n\n#define BIT_SHIFT_OSC_32K_CLKGEN_0 16\n#define BIT_MASK_OSC_32K_CLKGEN_0 0xffff\n#define BIT_OSC_32K_CLKGEN_0(x)                                                \\\n\t(((x) & BIT_MASK_OSC_32K_CLKGEN_0) << BIT_SHIFT_OSC_32K_CLKGEN_0)\n#define BITS_OSC_32K_CLKGEN_0                                                  \\\n\t(BIT_MASK_OSC_32K_CLKGEN_0 << BIT_SHIFT_OSC_32K_CLKGEN_0)\n#define BIT_CLEAR_OSC_32K_CLKGEN_0(x) ((x) & (~BITS_OSC_32K_CLKGEN_0))\n#define BIT_GET_OSC_32K_CLKGEN_0(x)                                            \\\n\t(((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0) & BIT_MASK_OSC_32K_CLKGEN_0)\n#define BIT_SET_OSC_32K_CLKGEN_0(x, v)                                         \\\n\t(BIT_CLEAR_OSC_32K_CLKGEN_0(x) | BIT_OSC_32K_CLKGEN_0(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_OSC_32K_CTRL\t\t\t(Offset 0x0194) */\n\n#define BIT_32K_CLK_OUT_RDY BIT(12)\n\n#define BIT_SHIFT_MONITOR_CYCLE_LOG2 8\n#define BIT_MASK_MONITOR_CYCLE_LOG2 0xf\n#define BIT_MONITOR_CYCLE_LOG2(x)                                              \\\n\t(((x) & BIT_MASK_MONITOR_CYCLE_LOG2) << BIT_SHIFT_MONITOR_CYCLE_LOG2)\n#define BITS_MONITOR_CYCLE_LOG2                                                \\\n\t(BIT_MASK_MONITOR_CYCLE_LOG2 << BIT_SHIFT_MONITOR_CYCLE_LOG2)\n#define BIT_CLEAR_MONITOR_CYCLE_LOG2(x) ((x) & (~BITS_MONITOR_CYCLE_LOG2))\n#define BIT_GET_MONITOR_CYCLE_LOG2(x)                                          \\\n\t(((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2) & BIT_MASK_MONITOR_CYCLE_LOG2)\n#define BIT_SET_MONITOR_CYCLE_LOG2(x, v)                                       \\\n\t(BIT_CLEAR_MONITOR_CYCLE_LOG2(x) | BIT_MONITOR_CYCLE_LOG2(v))\n\n#define BIT_SHIFT_FREQVALUE_UNREGCLK 8\n#define BIT_MASK_FREQVALUE_UNREGCLK 0xffffff\n#define BIT_FREQVALUE_UNREGCLK(x)                                              \\\n\t(((x) & BIT_MASK_FREQVALUE_UNREGCLK) << BIT_SHIFT_FREQVALUE_UNREGCLK)\n#define BITS_FREQVALUE_UNREGCLK                                                \\\n\t(BIT_MASK_FREQVALUE_UNREGCLK << BIT_SHIFT_FREQVALUE_UNREGCLK)\n#define BIT_CLEAR_FREQVALUE_UNREGCLK(x) ((x) & (~BITS_FREQVALUE_UNREGCLK))\n#define BIT_GET_FREQVALUE_UNREGCLK(x)                                          \\\n\t(((x) >> BIT_SHIFT_FREQVALUE_UNREGCLK) & BIT_MASK_FREQVALUE_UNREGCLK)\n#define BIT_SET_FREQVALUE_UNREGCLK(x, v)                                       \\\n\t(BIT_CLEAR_FREQVALUE_UNREGCLK(x) | BIT_FREQVALUE_UNREGCLK(v))\n\n#define BIT_CAL32K_DBGMOD BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_OSC_32K_CTRL\t\t\t(Offset 0x0194) */\n\n#define BIT_SHIFT_OSC_32K_RES_COMP 4\n#define BIT_MASK_OSC_32K_RES_COMP 0x3\n#define BIT_OSC_32K_RES_COMP(x)                                                \\\n\t(((x) & BIT_MASK_OSC_32K_RES_COMP) << BIT_SHIFT_OSC_32K_RES_COMP)\n#define BITS_OSC_32K_RES_COMP                                                  \\\n\t(BIT_MASK_OSC_32K_RES_COMP << BIT_SHIFT_OSC_32K_RES_COMP)\n#define BIT_CLEAR_OSC_32K_RES_COMP(x) ((x) & (~BITS_OSC_32K_RES_COMP))\n#define BIT_GET_OSC_32K_RES_COMP(x)                                            \\\n\t(((x) >> BIT_SHIFT_OSC_32K_RES_COMP) & BIT_MASK_OSC_32K_RES_COMP)\n#define BIT_SET_OSC_32K_RES_COMP(x, v)                                         \\\n\t(BIT_CLEAR_OSC_32K_RES_COMP(x) | BIT_OSC_32K_RES_COMP(v))\n\n#define BIT_OSC_32K_OUT_SEL BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_OSC_32K_CTRL\t\t\t(Offset 0x0194) */\n\n#define BIT_ISO_WL_2_OSC_32K BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_OSC_32K_CTRL\t\t\t(Offset 0x0194) */\n\n#define BIT_POW_CKGEN BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_OSC_32K_CTRL\t\t\t(Offset 0x0194) */\n\n#define BIT_SHIFT_NCO_THRS 0\n#define BIT_MASK_NCO_THRS 0x7f\n#define BIT_NCO_THRS(x) (((x) & BIT_MASK_NCO_THRS) << BIT_SHIFT_NCO_THRS)\n#define BITS_NCO_THRS (BIT_MASK_NCO_THRS << BIT_SHIFT_NCO_THRS)\n#define BIT_CLEAR_NCO_THRS(x) ((x) & (~BITS_NCO_THRS))\n#define BIT_GET_NCO_THRS(x) (((x) >> BIT_SHIFT_NCO_THRS) & BIT_MASK_NCO_THRS)\n#define BIT_SET_NCO_THRS(x, v) (BIT_CLEAR_NCO_THRS(x) | BIT_NCO_THRS(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_32K_CAL_REG1\t\t\t(Offset 0x0198) */\n\n#define BIT_CAL_32K_REG_WR BIT(31)\n#define BIT_CAL_32K_DBG_SEL BIT(22)\n\n#define BIT_SHIFT_CAL_32K_REG_ADDR 16\n#define BIT_MASK_CAL_32K_REG_ADDR 0x3f\n#define BIT_CAL_32K_REG_ADDR(x)                                                \\\n\t(((x) & BIT_MASK_CAL_32K_REG_ADDR) << BIT_SHIFT_CAL_32K_REG_ADDR)\n#define BITS_CAL_32K_REG_ADDR                                                  \\\n\t(BIT_MASK_CAL_32K_REG_ADDR << BIT_SHIFT_CAL_32K_REG_ADDR)\n#define BIT_CLEAR_CAL_32K_REG_ADDR(x) ((x) & (~BITS_CAL_32K_REG_ADDR))\n#define BIT_GET_CAL_32K_REG_ADDR(x)                                            \\\n\t(((x) >> BIT_SHIFT_CAL_32K_REG_ADDR) & BIT_MASK_CAL_32K_REG_ADDR)\n#define BIT_SET_CAL_32K_REG_ADDR(x, v)                                         \\\n\t(BIT_CLEAR_CAL_32K_REG_ADDR(x) | BIT_CAL_32K_REG_ADDR(v))\n\n#define BIT_SHIFT_CAL_32K_REG_DATA 0\n#define BIT_MASK_CAL_32K_REG_DATA 0xffff\n#define BIT_CAL_32K_REG_DATA(x)                                                \\\n\t(((x) & BIT_MASK_CAL_32K_REG_DATA) << BIT_SHIFT_CAL_32K_REG_DATA)\n#define BITS_CAL_32K_REG_DATA                                                  \\\n\t(BIT_MASK_CAL_32K_REG_DATA << BIT_SHIFT_CAL_32K_REG_DATA)\n#define BIT_CLEAR_CAL_32K_REG_DATA(x) ((x) & (~BITS_CAL_32K_REG_DATA))\n#define BIT_GET_CAL_32K_REG_DATA(x)                                            \\\n\t(((x) >> BIT_SHIFT_CAL_32K_REG_DATA) & BIT_MASK_CAL_32K_REG_DATA)\n#define BIT_SET_CAL_32K_REG_DATA(x, v)                                         \\\n\t(BIT_CLEAR_CAL_32K_REG_DATA(x) | BIT_CAL_32K_REG_DATA(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_C2HEVT\t\t\t\t(Offset 0x01A0) */\n\n#define BIT_SHIFT_C2HEVT_MSG 0\n#define BIT_MASK_C2HEVT_MSG 0xffffffffffffffffffffffffffffffffL\n#define BIT_C2HEVT_MSG(x) (((x) & BIT_MASK_C2HEVT_MSG) << BIT_SHIFT_C2HEVT_MSG)\n#define BITS_C2HEVT_MSG (BIT_MASK_C2HEVT_MSG << BIT_SHIFT_C2HEVT_MSG)\n#define BIT_CLEAR_C2HEVT_MSG(x) ((x) & (~BITS_C2HEVT_MSG))\n#define BIT_GET_C2HEVT_MSG(x)                                                  \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG) & BIT_MASK_C2HEVT_MSG)\n#define BIT_SET_C2HEVT_MSG(x, v) (BIT_CLEAR_C2HEVT_MSG(x) | BIT_C2HEVT_MSG(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_C2HEVT\t\t\t\t(Offset 0x01A0) */\n\n#define BIT_SHIFT_C2HEVT_MSG_V1 0\n#define BIT_MASK_C2HEVT_MSG_V1 0xffffffffL\n#define BIT_C2HEVT_MSG_V1(x)                                                   \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_V1) << BIT_SHIFT_C2HEVT_MSG_V1)\n#define BITS_C2HEVT_MSG_V1 (BIT_MASK_C2HEVT_MSG_V1 << BIT_SHIFT_C2HEVT_MSG_V1)\n#define BIT_CLEAR_C2HEVT_MSG_V1(x) ((x) & (~BITS_C2HEVT_MSG_V1))\n#define BIT_GET_C2HEVT_MSG_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_V1) & BIT_MASK_C2HEVT_MSG_V1)\n#define BIT_SET_C2HEVT_MSG_V1(x, v)                                            \\\n\t(BIT_CLEAR_C2HEVT_MSG_V1(x) | BIT_C2HEVT_MSG_V1(v))\n\n/* 2 REG_C2HEVT_1\t\t\t\t(Offset 0x01A4) */\n\n#define BIT_SHIFT_C2HEVT_MSG_1 0\n#define BIT_MASK_C2HEVT_MSG_1 0xffffffffL\n#define BIT_C2HEVT_MSG_1(x)                                                    \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_1) << BIT_SHIFT_C2HEVT_MSG_1)\n#define BITS_C2HEVT_MSG_1 (BIT_MASK_C2HEVT_MSG_1 << BIT_SHIFT_C2HEVT_MSG_1)\n#define BIT_CLEAR_C2HEVT_MSG_1(x) ((x) & (~BITS_C2HEVT_MSG_1))\n#define BIT_GET_C2HEVT_MSG_1(x)                                                \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_1) & BIT_MASK_C2HEVT_MSG_1)\n#define BIT_SET_C2HEVT_MSG_1(x, v)                                             \\\n\t(BIT_CLEAR_C2HEVT_MSG_1(x) | BIT_C2HEVT_MSG_1(v))\n\n/* 2 REG_C2HEVT_2\t\t\t\t(Offset 0x01A8) */\n\n#define BIT_SHIFT_C2HEVT_MSG_2 0\n#define BIT_MASK_C2HEVT_MSG_2 0xffffffffL\n#define BIT_C2HEVT_MSG_2(x)                                                    \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_2) << BIT_SHIFT_C2HEVT_MSG_2)\n#define BITS_C2HEVT_MSG_2 (BIT_MASK_C2HEVT_MSG_2 << BIT_SHIFT_C2HEVT_MSG_2)\n#define BIT_CLEAR_C2HEVT_MSG_2(x) ((x) & (~BITS_C2HEVT_MSG_2))\n#define BIT_GET_C2HEVT_MSG_2(x)                                                \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_2) & BIT_MASK_C2HEVT_MSG_2)\n#define BIT_SET_C2HEVT_MSG_2(x, v)                                             \\\n\t(BIT_CLEAR_C2HEVT_MSG_2(x) | BIT_C2HEVT_MSG_2(v))\n\n/* 2 REG_C2HEVT_3\t\t\t\t(Offset 0x01AC) */\n\n#define BIT_SHIFT_C2HEVT_MSG_3 0\n#define BIT_MASK_C2HEVT_MSG_3 0xffffffffL\n#define BIT_C2HEVT_MSG_3(x)                                                    \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_3) << BIT_SHIFT_C2HEVT_MSG_3)\n#define BITS_C2HEVT_MSG_3 (BIT_MASK_C2HEVT_MSG_3 << BIT_SHIFT_C2HEVT_MSG_3)\n#define BIT_CLEAR_C2HEVT_MSG_3(x) ((x) & (~BITS_C2HEVT_MSG_3))\n#define BIT_GET_C2HEVT_MSG_3(x)                                                \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_3) & BIT_MASK_C2HEVT_MSG_3)\n#define BIT_SET_C2HEVT_MSG_3(x, v)                                             \\\n\t(BIT_CLEAR_C2HEVT_MSG_3(x) | BIT_C2HEVT_MSG_3(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MISC_CTRL_V1\t\t\t(Offset 0x01B0) */\n\n#define BIT_SHIFT_PHYWR_SETUP_CNT 28\n#define BIT_MASK_PHYWR_SETUP_CNT 0xf\n#define BIT_PHYWR_SETUP_CNT(x)                                                 \\\n\t(((x) & BIT_MASK_PHYWR_SETUP_CNT) << BIT_SHIFT_PHYWR_SETUP_CNT)\n#define BITS_PHYWR_SETUP_CNT                                                   \\\n\t(BIT_MASK_PHYWR_SETUP_CNT << BIT_SHIFT_PHYWR_SETUP_CNT)\n#define BIT_CLEAR_PHYWR_SETUP_CNT(x) ((x) & (~BITS_PHYWR_SETUP_CNT))\n#define BIT_GET_PHYWR_SETUP_CNT(x)                                             \\\n\t(((x) >> BIT_SHIFT_PHYWR_SETUP_CNT) & BIT_MASK_PHYWR_SETUP_CNT)\n#define BIT_SET_PHYWR_SETUP_CNT(x, v)                                          \\\n\t(BIT_CLEAR_PHYWR_SETUP_CNT(x) | BIT_PHYWR_SETUP_CNT(v))\n\n#define BIT_SHIFT_PHYWR_HOLD_CNT 24\n#define BIT_MASK_PHYWR_HOLD_CNT 0xf\n#define BIT_PHYWR_HOLD_CNT(x)                                                  \\\n\t(((x) & BIT_MASK_PHYWR_HOLD_CNT) << BIT_SHIFT_PHYWR_HOLD_CNT)\n#define BITS_PHYWR_HOLD_CNT                                                    \\\n\t(BIT_MASK_PHYWR_HOLD_CNT << BIT_SHIFT_PHYWR_HOLD_CNT)\n#define BIT_CLEAR_PHYWR_HOLD_CNT(x) ((x) & (~BITS_PHYWR_HOLD_CNT))\n#define BIT_GET_PHYWR_HOLD_CNT(x)                                              \\\n\t(((x) >> BIT_SHIFT_PHYWR_HOLD_CNT) & BIT_MASK_PHYWR_HOLD_CNT)\n#define BIT_SET_PHYWR_HOLD_CNT(x, v)                                           \\\n\t(BIT_CLEAR_PHYWR_HOLD_CNT(x) | BIT_PHYWR_HOLD_CNT(v))\n\n#define BIT_SHIFT_TXBUF_WKCAM_OFFSET 8\n#define BIT_MASK_TXBUF_WKCAM_OFFSET 0x1fff\n#define BIT_TXBUF_WKCAM_OFFSET(x)                                              \\\n\t(((x) & BIT_MASK_TXBUF_WKCAM_OFFSET) << BIT_SHIFT_TXBUF_WKCAM_OFFSET)\n#define BITS_TXBUF_WKCAM_OFFSET                                                \\\n\t(BIT_MASK_TXBUF_WKCAM_OFFSET << BIT_SHIFT_TXBUF_WKCAM_OFFSET)\n#define BIT_CLEAR_TXBUF_WKCAM_OFFSET(x) ((x) & (~BITS_TXBUF_WKCAM_OFFSET))\n#define BIT_GET_TXBUF_WKCAM_OFFSET(x)                                          \\\n\t(((x) >> BIT_SHIFT_TXBUF_WKCAM_OFFSET) & BIT_MASK_TXBUF_WKCAM_OFFSET)\n#define BIT_SET_TXBUF_WKCAM_OFFSET(x, v)                                       \\\n\t(BIT_CLEAR_TXBUF_WKCAM_OFFSET(x) | BIT_TXBUF_WKCAM_OFFSET(v))\n\n#define BIT_SHIFT_PHYRD_WAIT_CNT 4\n#define BIT_MASK_PHYRD_WAIT_CNT 0xf\n#define BIT_PHYRD_WAIT_CNT(x)                                                  \\\n\t(((x) & BIT_MASK_PHYRD_WAIT_CNT) << BIT_SHIFT_PHYRD_WAIT_CNT)\n#define BITS_PHYRD_WAIT_CNT                                                    \\\n\t(BIT_MASK_PHYRD_WAIT_CNT << BIT_SHIFT_PHYRD_WAIT_CNT)\n#define BIT_CLEAR_PHYRD_WAIT_CNT(x) ((x) & (~BITS_PHYRD_WAIT_CNT))\n#define BIT_GET_PHYRD_WAIT_CNT(x)                                              \\\n\t(((x) >> BIT_SHIFT_PHYRD_WAIT_CNT) & BIT_MASK_PHYRD_WAIT_CNT)\n#define BIT_SET_PHYRD_WAIT_CNT(x, v)                                           \\\n\t(BIT_CLEAR_PHYRD_WAIT_CNT(x) | BIT_PHYRD_WAIT_CNT(v))\n\n#define BIT_SHIFT_H2CQ_PRI 0\n#define BIT_MASK_H2CQ_PRI 0x3\n#define BIT_H2CQ_PRI(x) (((x) & BIT_MASK_H2CQ_PRI) << BIT_SHIFT_H2CQ_PRI)\n#define BITS_H2CQ_PRI (BIT_MASK_H2CQ_PRI << BIT_SHIFT_H2CQ_PRI)\n#define BIT_CLEAR_H2CQ_PRI(x) ((x) & (~BITS_H2CQ_PRI))\n#define BIT_GET_H2CQ_PRI(x) (((x) >> BIT_SHIFT_H2CQ_PRI) & BIT_MASK_H2CQ_PRI)\n#define BIT_SET_H2CQ_PRI(x, v) (BIT_CLEAR_H2CQ_PRI(x) | BIT_H2CQ_PRI(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_RXDESC_BUFF_RPTR\t\t\t(Offset 0x01B0) */\n\n#define BIT_SHIFT_RXDESC_BUFF_RPTR 0\n#define BIT_MASK_RXDESC_BUFF_RPTR 0xffffffffL\n#define BIT_RXDESC_BUFF_RPTR(x)                                                \\\n\t(((x) & BIT_MASK_RXDESC_BUFF_RPTR) << BIT_SHIFT_RXDESC_BUFF_RPTR)\n#define BITS_RXDESC_BUFF_RPTR                                                  \\\n\t(BIT_MASK_RXDESC_BUFF_RPTR << BIT_SHIFT_RXDESC_BUFF_RPTR)\n#define BIT_CLEAR_RXDESC_BUFF_RPTR(x) ((x) & (~BITS_RXDESC_BUFF_RPTR))\n#define BIT_GET_RXDESC_BUFF_RPTR(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXDESC_BUFF_RPTR) & BIT_MASK_RXDESC_BUFF_RPTR)\n#define BIT_SET_RXDESC_BUFF_RPTR(x, v)                                         \\\n\t(BIT_CLEAR_RXDESC_BUFF_RPTR(x) | BIT_RXDESC_BUFF_RPTR(v))\n\n/* 2 REG_RXDESC_BUFF_WPTR\t\t\t(Offset 0x01B4) */\n\n#define BIT_SHIFT_RXDESC_BUFF_WPTR 0\n#define BIT_MASK_RXDESC_BUFF_WPTR 0xffffffffL\n#define BIT_RXDESC_BUFF_WPTR(x)                                                \\\n\t(((x) & BIT_MASK_RXDESC_BUFF_WPTR) << BIT_SHIFT_RXDESC_BUFF_WPTR)\n#define BITS_RXDESC_BUFF_WPTR                                                  \\\n\t(BIT_MASK_RXDESC_BUFF_WPTR << BIT_SHIFT_RXDESC_BUFF_WPTR)\n#define BIT_CLEAR_RXDESC_BUFF_WPTR(x) ((x) & (~BITS_RXDESC_BUFF_WPTR))\n#define BIT_GET_RXDESC_BUFF_WPTR(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXDESC_BUFF_WPTR) & BIT_MASK_RXDESC_BUFF_WPTR)\n#define BIT_SET_RXDESC_BUFF_WPTR(x, v)                                         \\\n\t(BIT_CLEAR_RXDESC_BUFF_WPTR(x) | BIT_RXDESC_BUFF_WPTR(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SW_DEFINED_PAGE1\t\t\t(Offset 0x01B8) */\n\n#define BIT_SHIFT_SW_DEFINED_PAGE1 0\n#define BIT_MASK_SW_DEFINED_PAGE1 0xffffffffffffffffL\n#define BIT_SW_DEFINED_PAGE1(x)                                                \\\n\t(((x) & BIT_MASK_SW_DEFINED_PAGE1) << BIT_SHIFT_SW_DEFINED_PAGE1)\n#define BITS_SW_DEFINED_PAGE1                                                  \\\n\t(BIT_MASK_SW_DEFINED_PAGE1 << BIT_SHIFT_SW_DEFINED_PAGE1)\n#define BIT_CLEAR_SW_DEFINED_PAGE1(x) ((x) & (~BITS_SW_DEFINED_PAGE1))\n#define BIT_GET_SW_DEFINED_PAGE1(x)                                            \\\n\t(((x) >> BIT_SHIFT_SW_DEFINED_PAGE1) & BIT_MASK_SW_DEFINED_PAGE1)\n#define BIT_SET_SW_DEFINED_PAGE1(x, v)                                         \\\n\t(BIT_CLEAR_SW_DEFINED_PAGE1(x) | BIT_SW_DEFINED_PAGE1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SW_DEFINED_PAGE1\t\t\t(Offset 0x01B8) */\n\n#define BIT_SHIFT_SW_DEFINED_PAGE1_V1 0\n#define BIT_MASK_SW_DEFINED_PAGE1_V1 0xffffffffL\n#define BIT_SW_DEFINED_PAGE1_V1(x)                                             \\\n\t(((x) & BIT_MASK_SW_DEFINED_PAGE1_V1) << BIT_SHIFT_SW_DEFINED_PAGE1_V1)\n#define BITS_SW_DEFINED_PAGE1_V1                                               \\\n\t(BIT_MASK_SW_DEFINED_PAGE1_V1 << BIT_SHIFT_SW_DEFINED_PAGE1_V1)\n#define BIT_CLEAR_SW_DEFINED_PAGE1_V1(x) ((x) & (~BITS_SW_DEFINED_PAGE1_V1))\n#define BIT_GET_SW_DEFINED_PAGE1_V1(x)                                         \\\n\t(((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1) & BIT_MASK_SW_DEFINED_PAGE1_V1)\n#define BIT_SET_SW_DEFINED_PAGE1_V1(x, v)                                      \\\n\t(BIT_CLEAR_SW_DEFINED_PAGE1_V1(x) | BIT_SW_DEFINED_PAGE1_V1(v))\n\n/* 2 REG_SW_DEFINED_PAGE2\t\t\t(Offset 0x01BC) */\n\n#define BIT_SHIFT_SW_DEFINED_PAGE2 0\n#define BIT_MASK_SW_DEFINED_PAGE2 0xffffffffL\n#define BIT_SW_DEFINED_PAGE2(x)                                                \\\n\t(((x) & BIT_MASK_SW_DEFINED_PAGE2) << BIT_SHIFT_SW_DEFINED_PAGE2)\n#define BITS_SW_DEFINED_PAGE2                                                  \\\n\t(BIT_MASK_SW_DEFINED_PAGE2 << BIT_SHIFT_SW_DEFINED_PAGE2)\n#define BIT_CLEAR_SW_DEFINED_PAGE2(x) ((x) & (~BITS_SW_DEFINED_PAGE2))\n#define BIT_GET_SW_DEFINED_PAGE2(x)                                            \\\n\t(((x) >> BIT_SHIFT_SW_DEFINED_PAGE2) & BIT_MASK_SW_DEFINED_PAGE2)\n#define BIT_SET_SW_DEFINED_PAGE2(x, v)                                         \\\n\t(BIT_CLEAR_SW_DEFINED_PAGE2(x) | BIT_SW_DEFINED_PAGE2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MCUTST_I\t\t\t\t(Offset 0x01C0) */\n\n#define BIT_SHIFT_MCUDMSG_I 0\n#define BIT_MASK_MCUDMSG_I 0xffffffffL\n#define BIT_MCUDMSG_I(x) (((x) & BIT_MASK_MCUDMSG_I) << BIT_SHIFT_MCUDMSG_I)\n#define BITS_MCUDMSG_I (BIT_MASK_MCUDMSG_I << BIT_SHIFT_MCUDMSG_I)\n#define BIT_CLEAR_MCUDMSG_I(x) ((x) & (~BITS_MCUDMSG_I))\n#define BIT_GET_MCUDMSG_I(x) (((x) >> BIT_SHIFT_MCUDMSG_I) & BIT_MASK_MCUDMSG_I)\n#define BIT_SET_MCUDMSG_I(x, v) (BIT_CLEAR_MCUDMSG_I(x) | BIT_MCUDMSG_I(v))\n\n/* 2 REG_MCUTST_II\t\t\t\t(Offset 0x01C4) */\n\n#define BIT_SHIFT_MCUDMSG_II 0\n#define BIT_MASK_MCUDMSG_II 0xffffffffL\n#define BIT_MCUDMSG_II(x) (((x) & BIT_MASK_MCUDMSG_II) << BIT_SHIFT_MCUDMSG_II)\n#define BITS_MCUDMSG_II (BIT_MASK_MCUDMSG_II << BIT_SHIFT_MCUDMSG_II)\n#define BIT_CLEAR_MCUDMSG_II(x) ((x) & (~BITS_MCUDMSG_II))\n#define BIT_GET_MCUDMSG_II(x)                                                  \\\n\t(((x) >> BIT_SHIFT_MCUDMSG_II) & BIT_MASK_MCUDMSG_II)\n#define BIT_SET_MCUDMSG_II(x, v) (BIT_CLEAR_MCUDMSG_II(x) | BIT_MCUDMSG_II(v))\n\n/* 2 REG_FMETHR\t\t\t\t(Offset 0x01C8) */\n\n#define BIT_FMSG_INT BIT(31)\n\n#define BIT_SHIFT_FW_MSG 0\n#define BIT_MASK_FW_MSG 0xffffffffL\n#define BIT_FW_MSG(x) (((x) & BIT_MASK_FW_MSG) << BIT_SHIFT_FW_MSG)\n#define BITS_FW_MSG (BIT_MASK_FW_MSG << BIT_SHIFT_FW_MSG)\n#define BIT_CLEAR_FW_MSG(x) ((x) & (~BITS_FW_MSG))\n#define BIT_GET_FW_MSG(x) (((x) >> BIT_SHIFT_FW_MSG) & BIT_MASK_FW_MSG)\n#define BIT_SET_FW_MSG(x, v) (BIT_CLEAR_FW_MSG(x) | BIT_FW_MSG(v))\n\n/* 2 REG_HMETFR\t\t\t\t(Offset 0x01CC) */\n\n#define BIT_SHIFT_HRCV_MSG 24\n#define BIT_MASK_HRCV_MSG 0xff\n#define BIT_HRCV_MSG(x) (((x) & BIT_MASK_HRCV_MSG) << BIT_SHIFT_HRCV_MSG)\n#define BITS_HRCV_MSG (BIT_MASK_HRCV_MSG << BIT_SHIFT_HRCV_MSG)\n#define BIT_CLEAR_HRCV_MSG(x) ((x) & (~BITS_HRCV_MSG))\n#define BIT_GET_HRCV_MSG(x) (((x) >> BIT_SHIFT_HRCV_MSG) & BIT_MASK_HRCV_MSG)\n#define BIT_SET_HRCV_MSG(x, v) (BIT_CLEAR_HRCV_MSG(x) | BIT_HRCV_MSG(v))\n\n#define BIT_INT_BOX3 BIT(3)\n#define BIT_INT_BOX2 BIT(2)\n#define BIT_INT_BOX1 BIT(1)\n#define BIT_INT_BOX0 BIT(0)\n\n/* 2 REG_HMEBOX0\t\t\t\t(Offset 0x01D0) */\n\n#define BIT_SHIFT_HOST_MSG_0 0\n#define BIT_MASK_HOST_MSG_0 0xffffffffL\n#define BIT_HOST_MSG_0(x) (((x) & BIT_MASK_HOST_MSG_0) << BIT_SHIFT_HOST_MSG_0)\n#define BITS_HOST_MSG_0 (BIT_MASK_HOST_MSG_0 << BIT_SHIFT_HOST_MSG_0)\n#define BIT_CLEAR_HOST_MSG_0(x) ((x) & (~BITS_HOST_MSG_0))\n#define BIT_GET_HOST_MSG_0(x)                                                  \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_0) & BIT_MASK_HOST_MSG_0)\n#define BIT_SET_HOST_MSG_0(x, v) (BIT_CLEAR_HOST_MSG_0(x) | BIT_HOST_MSG_0(v))\n\n/* 2 REG_HMEBOX1\t\t\t\t(Offset 0x01D4) */\n\n#define BIT_SHIFT_HOST_MSG_1 0\n#define BIT_MASK_HOST_MSG_1 0xffffffffL\n#define BIT_HOST_MSG_1(x) (((x) & BIT_MASK_HOST_MSG_1) << BIT_SHIFT_HOST_MSG_1)\n#define BITS_HOST_MSG_1 (BIT_MASK_HOST_MSG_1 << BIT_SHIFT_HOST_MSG_1)\n#define BIT_CLEAR_HOST_MSG_1(x) ((x) & (~BITS_HOST_MSG_1))\n#define BIT_GET_HOST_MSG_1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_1) & BIT_MASK_HOST_MSG_1)\n#define BIT_SET_HOST_MSG_1(x, v) (BIT_CLEAR_HOST_MSG_1(x) | BIT_HOST_MSG_1(v))\n\n/* 2 REG_HMEBOX2\t\t\t\t(Offset 0x01D8) */\n\n#define BIT_SHIFT_HOST_MSG_2 0\n#define BIT_MASK_HOST_MSG_2 0xffffffffL\n#define BIT_HOST_MSG_2(x) (((x) & BIT_MASK_HOST_MSG_2) << BIT_SHIFT_HOST_MSG_2)\n#define BITS_HOST_MSG_2 (BIT_MASK_HOST_MSG_2 << BIT_SHIFT_HOST_MSG_2)\n#define BIT_CLEAR_HOST_MSG_2(x) ((x) & (~BITS_HOST_MSG_2))\n#define BIT_GET_HOST_MSG_2(x)                                                  \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_2) & BIT_MASK_HOST_MSG_2)\n#define BIT_SET_HOST_MSG_2(x, v) (BIT_CLEAR_HOST_MSG_2(x) | BIT_HOST_MSG_2(v))\n\n/* 2 REG_HMEBOX3\t\t\t\t(Offset 0x01DC) */\n\n#define BIT_SHIFT_HOST_MSG_3 0\n#define BIT_MASK_HOST_MSG_3 0xffffffffL\n#define BIT_HOST_MSG_3(x) (((x) & BIT_MASK_HOST_MSG_3) << BIT_SHIFT_HOST_MSG_3)\n#define BITS_HOST_MSG_3 (BIT_MASK_HOST_MSG_3 << BIT_SHIFT_HOST_MSG_3)\n#define BIT_CLEAR_HOST_MSG_3(x) ((x) & (~BITS_HOST_MSG_3))\n#define BIT_GET_HOST_MSG_3(x)                                                  \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_3) & BIT_MASK_HOST_MSG_3)\n#define BIT_SET_HOST_MSG_3(x, v) (BIT_CLEAR_HOST_MSG_3(x) | BIT_HOST_MSG_3(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_RXDESC_BUFF_BNDY\t\t\t(Offset 0x01E0) */\n\n#define BIT_FW_FIFO_PTR_RST BIT(18)\n#define BIT_PHY_FIFO_PTR_RST BIT(17)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_LLT_INIT\t\t\t\t(Offset 0x01E0) */\n\n#define BIT_SHIFT_LLTINI_PDATA_V1 16\n#define BIT_MASK_LLTINI_PDATA_V1 0xfff\n#define BIT_LLTINI_PDATA_V1(x)                                                 \\\n\t(((x) & BIT_MASK_LLTINI_PDATA_V1) << BIT_SHIFT_LLTINI_PDATA_V1)\n#define BITS_LLTINI_PDATA_V1                                                   \\\n\t(BIT_MASK_LLTINI_PDATA_V1 << BIT_SHIFT_LLTINI_PDATA_V1)\n#define BIT_CLEAR_LLTINI_PDATA_V1(x) ((x) & (~BITS_LLTINI_PDATA_V1))\n#define BIT_GET_LLTINI_PDATA_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_LLTINI_PDATA_V1) & BIT_MASK_LLTINI_PDATA_V1)\n#define BIT_SET_LLTINI_PDATA_V1(x, v)                                          \\\n\t(BIT_CLEAR_LLTINI_PDATA_V1(x) | BIT_LLTINI_PDATA_V1(v))\n\n#define BIT_SHIFT_LLTINI_HDATA_V1 0\n#define BIT_MASK_LLTINI_HDATA_V1 0xfff\n#define BIT_LLTINI_HDATA_V1(x)                                                 \\\n\t(((x) & BIT_MASK_LLTINI_HDATA_V1) << BIT_SHIFT_LLTINI_HDATA_V1)\n#define BITS_LLTINI_HDATA_V1                                                   \\\n\t(BIT_MASK_LLTINI_HDATA_V1 << BIT_SHIFT_LLTINI_HDATA_V1)\n#define BIT_CLEAR_LLTINI_HDATA_V1(x) ((x) & (~BITS_LLTINI_HDATA_V1))\n#define BIT_GET_LLTINI_HDATA_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_LLTINI_HDATA_V1) & BIT_MASK_LLTINI_HDATA_V1)\n#define BIT_SET_LLTINI_HDATA_V1(x, v)                                          \\\n\t(BIT_CLEAR_LLTINI_HDATA_V1(x) | BIT_LLTINI_HDATA_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_RXDESC_BUFF_BNDY\t\t\t(Offset 0x01E0) */\n\n#define BIT_SHIFT_RXDESC_BUFF_BNDY 0\n#define BIT_MASK_RXDESC_BUFF_BNDY 0xffffffffL\n#define BIT_RXDESC_BUFF_BNDY(x)                                                \\\n\t(((x) & BIT_MASK_RXDESC_BUFF_BNDY) << BIT_SHIFT_RXDESC_BUFF_BNDY)\n#define BITS_RXDESC_BUFF_BNDY                                                  \\\n\t(BIT_MASK_RXDESC_BUFF_BNDY << BIT_SHIFT_RXDESC_BUFF_BNDY)\n#define BIT_CLEAR_RXDESC_BUFF_BNDY(x) ((x) & (~BITS_RXDESC_BUFF_BNDY))\n#define BIT_GET_RXDESC_BUFF_BNDY(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXDESC_BUFF_BNDY) & BIT_MASK_RXDESC_BUFF_BNDY)\n#define BIT_SET_RXDESC_BUFF_BNDY(x, v)                                         \\\n\t(BIT_CLEAR_RXDESC_BUFF_BNDY(x) | BIT_RXDESC_BUFF_BNDY(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_GENTST\t\t\t\t(Offset 0x01E4) */\n\n#define BIT_SHIFT_GENTST 0\n#define BIT_MASK_GENTST 0xffffffffL\n#define BIT_GENTST(x) (((x) & BIT_MASK_GENTST) << BIT_SHIFT_GENTST)\n#define BITS_GENTST (BIT_MASK_GENTST << BIT_SHIFT_GENTST)\n#define BIT_CLEAR_GENTST(x) ((x) & (~BITS_GENTST))\n#define BIT_GET_GENTST(x) (((x) >> BIT_SHIFT_GENTST) & BIT_MASK_GENTST)\n#define BIT_SET_GENTST(x, v) (BIT_CLEAR_GENTST(x) | BIT_GENTST(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_LLT_INIT_ADDR\t\t\t(Offset 0x01E4) */\n\n#define BIT_SHIFT_LLTINI_ADDR_V1 0\n#define BIT_MASK_LLTINI_ADDR_V1 0xfff\n#define BIT_LLTINI_ADDR_V1(x)                                                  \\\n\t(((x) & BIT_MASK_LLTINI_ADDR_V1) << BIT_SHIFT_LLTINI_ADDR_V1)\n#define BITS_LLTINI_ADDR_V1                                                    \\\n\t(BIT_MASK_LLTINI_ADDR_V1 << BIT_SHIFT_LLTINI_ADDR_V1)\n#define BIT_CLEAR_LLTINI_ADDR_V1(x) ((x) & (~BITS_LLTINI_ADDR_V1))\n#define BIT_GET_LLTINI_ADDR_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_LLTINI_ADDR_V1) & BIT_MASK_LLTINI_ADDR_V1)\n#define BIT_SET_LLTINI_ADDR_V1(x, v)                                           \\\n\t(BIT_CLEAR_LLTINI_ADDR_V1(x) | BIT_LLTINI_ADDR_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BB_ACCESS_CTRL\t\t\t(Offset 0x01E8) */\n\n#define BIT_SHIFT_BB_WRITE_READ 30\n#define BIT_MASK_BB_WRITE_READ 0x3\n#define BIT_BB_WRITE_READ(x)                                                   \\\n\t(((x) & BIT_MASK_BB_WRITE_READ) << BIT_SHIFT_BB_WRITE_READ)\n#define BITS_BB_WRITE_READ (BIT_MASK_BB_WRITE_READ << BIT_SHIFT_BB_WRITE_READ)\n#define BIT_CLEAR_BB_WRITE_READ(x) ((x) & (~BITS_BB_WRITE_READ))\n#define BIT_GET_BB_WRITE_READ(x)                                               \\\n\t(((x) >> BIT_SHIFT_BB_WRITE_READ) & BIT_MASK_BB_WRITE_READ)\n#define BIT_SET_BB_WRITE_READ(x, v)                                            \\\n\t(BIT_CLEAR_BB_WRITE_READ(x) | BIT_BB_WRITE_READ(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_BB_ACCESS_CTRL\t\t\t(Offset 0x01E8) */\n\n#define BIT_SHIFT_BB_WRITE_EN_V1 16\n#define BIT_MASK_BB_WRITE_EN_V1 0xf\n#define BIT_BB_WRITE_EN_V1(x)                                                  \\\n\t(((x) & BIT_MASK_BB_WRITE_EN_V1) << BIT_SHIFT_BB_WRITE_EN_V1)\n#define BITS_BB_WRITE_EN_V1                                                    \\\n\t(BIT_MASK_BB_WRITE_EN_V1 << BIT_SHIFT_BB_WRITE_EN_V1)\n#define BIT_CLEAR_BB_WRITE_EN_V1(x) ((x) & (~BITS_BB_WRITE_EN_V1))\n#define BIT_GET_BB_WRITE_EN_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_BB_WRITE_EN_V1) & BIT_MASK_BB_WRITE_EN_V1)\n#define BIT_SET_BB_WRITE_EN_V1(x, v)                                           \\\n\t(BIT_CLEAR_BB_WRITE_EN_V1(x) | BIT_BB_WRITE_EN_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BB_ACCESS_CTRL\t\t\t(Offset 0x01E8) */\n\n#define BIT_SHIFT_BB_WRITE_EN 12\n#define BIT_MASK_BB_WRITE_EN 0xf\n#define BIT_BB_WRITE_EN(x)                                                     \\\n\t(((x) & BIT_MASK_BB_WRITE_EN) << BIT_SHIFT_BB_WRITE_EN)\n#define BITS_BB_WRITE_EN (BIT_MASK_BB_WRITE_EN << BIT_SHIFT_BB_WRITE_EN)\n#define BIT_CLEAR_BB_WRITE_EN(x) ((x) & (~BITS_BB_WRITE_EN))\n#define BIT_GET_BB_WRITE_EN(x)                                                 \\\n\t(((x) >> BIT_SHIFT_BB_WRITE_EN) & BIT_MASK_BB_WRITE_EN)\n#define BIT_SET_BB_WRITE_EN(x, v)                                              \\\n\t(BIT_CLEAR_BB_WRITE_EN(x) | BIT_BB_WRITE_EN(v))\n\n#define BIT_SHIFT_BB_ADDR 2\n#define BIT_MASK_BB_ADDR 0x1ff\n#define BIT_BB_ADDR(x) (((x) & BIT_MASK_BB_ADDR) << BIT_SHIFT_BB_ADDR)\n#define BITS_BB_ADDR (BIT_MASK_BB_ADDR << BIT_SHIFT_BB_ADDR)\n#define BIT_CLEAR_BB_ADDR(x) ((x) & (~BITS_BB_ADDR))\n#define BIT_GET_BB_ADDR(x) (((x) >> BIT_SHIFT_BB_ADDR) & BIT_MASK_BB_ADDR)\n#define BIT_SET_BB_ADDR(x, v) (BIT_CLEAR_BB_ADDR(x) | BIT_BB_ADDR(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_BB_ACCESS_CTRL\t\t\t(Offset 0x01E8) */\n\n#define BIT_SHIFT_BB_ADDR_V1 2\n#define BIT_MASK_BB_ADDR_V1 0xfff\n#define BIT_BB_ADDR_V1(x) (((x) & BIT_MASK_BB_ADDR_V1) << BIT_SHIFT_BB_ADDR_V1)\n#define BITS_BB_ADDR_V1 (BIT_MASK_BB_ADDR_V1 << BIT_SHIFT_BB_ADDR_V1)\n#define BIT_CLEAR_BB_ADDR_V1(x) ((x) & (~BITS_BB_ADDR_V1))\n#define BIT_GET_BB_ADDR_V1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BB_ADDR_V1) & BIT_MASK_BB_ADDR_V1)\n#define BIT_SET_BB_ADDR_V1(x, v) (BIT_CLEAR_BB_ADDR_V1(x) | BIT_BB_ADDR_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BB_ACCESS_CTRL\t\t\t(Offset 0x01E8) */\n\n#define BIT_BB_ERRACC BIT(0)\n\n/* 2 REG_BB_ACCESS_DATA\t\t\t(Offset 0x01EC) */\n\n#define BIT_SHIFT_BB_DATA 0\n#define BIT_MASK_BB_DATA 0xffffffffL\n#define BIT_BB_DATA(x) (((x) & BIT_MASK_BB_DATA) << BIT_SHIFT_BB_DATA)\n#define BITS_BB_DATA (BIT_MASK_BB_DATA << BIT_SHIFT_BB_DATA)\n#define BIT_CLEAR_BB_DATA(x) ((x) & (~BITS_BB_DATA))\n#define BIT_GET_BB_DATA(x) (((x) >> BIT_SHIFT_BB_DATA) & BIT_MASK_BB_DATA)\n#define BIT_SET_BB_DATA(x, v) (BIT_CLEAR_BB_DATA(x) | BIT_BB_DATA(v))\n\n/* 2 REG_HMEBOX_E0\t\t\t\t(Offset 0x01F0) */\n\n#define BIT_SHIFT_HMEBOX_E0 0\n#define BIT_MASK_HMEBOX_E0 0xffffffffL\n#define BIT_HMEBOX_E0(x) (((x) & BIT_MASK_HMEBOX_E0) << BIT_SHIFT_HMEBOX_E0)\n#define BITS_HMEBOX_E0 (BIT_MASK_HMEBOX_E0 << BIT_SHIFT_HMEBOX_E0)\n#define BIT_CLEAR_HMEBOX_E0(x) ((x) & (~BITS_HMEBOX_E0))\n#define BIT_GET_HMEBOX_E0(x) (((x) >> BIT_SHIFT_HMEBOX_E0) & BIT_MASK_HMEBOX_E0)\n#define BIT_SET_HMEBOX_E0(x, v) (BIT_CLEAR_HMEBOX_E0(x) | BIT_HMEBOX_E0(v))\n\n/* 2 REG_HMEBOX_E1\t\t\t\t(Offset 0x01F4) */\n\n#define BIT_SHIFT_HMEBOX_E1 0\n#define BIT_MASK_HMEBOX_E1 0xffffffffL\n#define BIT_HMEBOX_E1(x) (((x) & BIT_MASK_HMEBOX_E1) << BIT_SHIFT_HMEBOX_E1)\n#define BITS_HMEBOX_E1 (BIT_MASK_HMEBOX_E1 << BIT_SHIFT_HMEBOX_E1)\n#define BIT_CLEAR_HMEBOX_E1(x) ((x) & (~BITS_HMEBOX_E1))\n#define BIT_GET_HMEBOX_E1(x) (((x) >> BIT_SHIFT_HMEBOX_E1) & BIT_MASK_HMEBOX_E1)\n#define BIT_SET_HMEBOX_E1(x, v) (BIT_CLEAR_HMEBOX_E1(x) | BIT_HMEBOX_E1(v))\n\n/* 2 REG_HMEBOX_E2\t\t\t\t(Offset 0x01F8) */\n\n#define BIT_SHIFT_HMEBOX_E2 0\n#define BIT_MASK_HMEBOX_E2 0xffffffffL\n#define BIT_HMEBOX_E2(x) (((x) & BIT_MASK_HMEBOX_E2) << BIT_SHIFT_HMEBOX_E2)\n#define BITS_HMEBOX_E2 (BIT_MASK_HMEBOX_E2 << BIT_SHIFT_HMEBOX_E2)\n#define BIT_CLEAR_HMEBOX_E2(x) ((x) & (~BITS_HMEBOX_E2))\n#define BIT_GET_HMEBOX_E2(x) (((x) >> BIT_SHIFT_HMEBOX_E2) & BIT_MASK_HMEBOX_E2)\n#define BIT_SET_HMEBOX_E2(x, v) (BIT_CLEAR_HMEBOX_E2(x) | BIT_HMEBOX_E2(v))\n\n/* 2 REG_HMEBOX_E3\t\t\t\t(Offset 0x01FC) */\n\n#define BIT_SHIFT_HMEBOX_E3 0\n#define BIT_MASK_HMEBOX_E3 0xffffffffL\n#define BIT_HMEBOX_E3(x) (((x) & BIT_MASK_HMEBOX_E3) << BIT_SHIFT_HMEBOX_E3)\n#define BITS_HMEBOX_E3 (BIT_MASK_HMEBOX_E3 << BIT_SHIFT_HMEBOX_E3)\n#define BIT_CLEAR_HMEBOX_E3(x) ((x) & (~BITS_HMEBOX_E3))\n#define BIT_GET_HMEBOX_E3(x) (((x) >> BIT_SHIFT_HMEBOX_E3) & BIT_MASK_HMEBOX_E3)\n#define BIT_SET_HMEBOX_E3(x, v) (BIT_CLEAR_HMEBOX_E3(x) | BIT_HMEBOX_E3(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_BCN_CTRL_0\t\t\t\t(Offset 0x0200) */\n\n#define BIT_BCN1_VALID BIT(31)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_HLPQ\t\t\t(Offset 0x0200) */\n\n#define BIT_EP2Q_PUBLIC_DIS BIT(29)\n#define BIT_EP1Q_PUBLIC_DIS BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_HLPQ\t\t\t(Offset 0x0200) */\n\n#define BIT_EPQ_PUBLIC_DIS BIT(27)\n#define BIT_NPQ_PUBLIC_DIS BIT(26)\n#define BIT_LPQ_PUBLIC_DIS BIT(25)\n#define BIT_HPQ_PUBLIC_DIS BIT(24)\n\n#define BIT_SHIFT_PUBQ 16\n#define BIT_MASK_PUBQ 0xff\n#define BIT_PUBQ(x) (((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ)\n#define BITS_PUBQ (BIT_MASK_PUBQ << BIT_SHIFT_PUBQ)\n#define BIT_CLEAR_PUBQ(x) ((x) & (~BITS_PUBQ))\n#define BIT_GET_PUBQ(x) (((x) >> BIT_SHIFT_PUBQ) & BIT_MASK_PUBQ)\n#define BIT_SET_PUBQ(x, v) (BIT_CLEAR_PUBQ(x) | BIT_PUBQ(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FIFOPAGE_CTRL_1\t\t\t(Offset 0x0200) */\n\n#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1 16\n#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 0xff\n#define BIT_TX_OQT_HE_FREE_SPACE_V1(x)                                         \\\n\t(((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1)                              \\\n\t << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1)\n#define BITS_TX_OQT_HE_FREE_SPACE_V1                                           \\\n\t(BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1)\n#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1(x)                                   \\\n\t((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1))\n#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1(x)                                     \\\n\t(((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) &                          \\\n\t BIT_MASK_TX_OQT_HE_FREE_SPACE_V1)\n#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1(x, v)                                  \\\n\t(BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1(x) | BIT_TX_OQT_HE_FREE_SPACE_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_BCN_CTRL_0\t\t\t\t(Offset 0x0200) */\n\n#define BIT_SHIFT_BCN1_HEAD 16\n#define BIT_MASK_BCN1_HEAD 0xfff\n#define BIT_BCN1_HEAD(x) (((x) & BIT_MASK_BCN1_HEAD) << BIT_SHIFT_BCN1_HEAD)\n#define BITS_BCN1_HEAD (BIT_MASK_BCN1_HEAD << BIT_SHIFT_BCN1_HEAD)\n#define BIT_CLEAR_BCN1_HEAD(x) ((x) & (~BITS_BCN1_HEAD))\n#define BIT_GET_BCN1_HEAD(x) (((x) >> BIT_SHIFT_BCN1_HEAD) & BIT_MASK_BCN1_HEAD)\n#define BIT_SET_BCN1_HEAD(x, v) (BIT_CLEAR_BCN1_HEAD(x) | BIT_BCN1_HEAD(v))\n\n#define BIT_BCN0_VALID BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_HLPQ\t\t\t(Offset 0x0200) */\n\n#define BIT_SHIFT_LPQ 8\n#define BIT_MASK_LPQ 0xff\n#define BIT_LPQ(x) (((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ)\n#define BITS_LPQ (BIT_MASK_LPQ << BIT_SHIFT_LPQ)\n#define BIT_CLEAR_LPQ(x) ((x) & (~BITS_LPQ))\n#define BIT_GET_LPQ(x) (((x) >> BIT_SHIFT_LPQ) & BIT_MASK_LPQ)\n#define BIT_SET_LPQ(x, v) (BIT_CLEAR_LPQ(x) | BIT_LPQ(v))\n\n#define BIT_SHIFT_HPQ 0\n#define BIT_MASK_HPQ 0xff\n#define BIT_HPQ(x) (((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ)\n#define BITS_HPQ (BIT_MASK_HPQ << BIT_SHIFT_HPQ)\n#define BIT_CLEAR_HPQ(x) ((x) & (~BITS_HPQ))\n#define BIT_GET_HPQ(x) (((x) >> BIT_SHIFT_HPQ) & BIT_MASK_HPQ)\n#define BIT_SET_HPQ(x, v) (BIT_CLEAR_HPQ(x) | BIT_HPQ(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FIFOPAGE_CTRL_1\t\t\t(Offset 0x0200) */\n\n#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1 0\n#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 0xff\n#define BIT_TX_OQT_NL_FREE_SPACE_V1(x)                                         \\\n\t(((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1)                              \\\n\t << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1)\n#define BITS_TX_OQT_NL_FREE_SPACE_V1                                           \\\n\t(BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1)\n#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1(x)                                   \\\n\t((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1))\n#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1(x)                                     \\\n\t(((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) &                          \\\n\t BIT_MASK_TX_OQT_NL_FREE_SPACE_V1)\n#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1(x, v)                                  \\\n\t(BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1(x) | BIT_TX_OQT_NL_FREE_SPACE_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_BCN_CTRL_0\t\t\t\t(Offset 0x0200) */\n\n#define BIT_SHIFT_BCN0_HEAD 0\n#define BIT_MASK_BCN0_HEAD 0xfff\n#define BIT_BCN0_HEAD(x) (((x) & BIT_MASK_BCN0_HEAD) << BIT_SHIFT_BCN0_HEAD)\n#define BITS_BCN0_HEAD (BIT_MASK_BCN0_HEAD << BIT_SHIFT_BCN0_HEAD)\n#define BIT_CLEAR_BCN0_HEAD(x) ((x) & (~BITS_BCN0_HEAD))\n#define BIT_GET_BCN0_HEAD(x) (((x) >> BIT_SHIFT_BCN0_HEAD) & BIT_MASK_BCN0_HEAD)\n#define BIT_SET_BCN0_HEAD(x, v) (BIT_CLEAR_BCN0_HEAD(x) | BIT_BCN0_HEAD(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FIFOPAGE_CTRL_2\t\t\t(Offset 0x0204) */\n\n#define BIT_BCN_VALID_1_V1 BIT(31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_BCN_CTRL_1\t\t\t\t(Offset 0x0204) */\n\n#define BIT_BCN3_VALID BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FIFOPAGE_INFO\t\t\t(Offset 0x0204) */\n\n#define BIT_SHIFT_TXPKTNUM 24\n#define BIT_MASK_TXPKTNUM 0xff\n#define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM)\n#define BITS_TXPKTNUM (BIT_MASK_TXPKTNUM << BIT_SHIFT_TXPKTNUM)\n#define BIT_CLEAR_TXPKTNUM(x) ((x) & (~BITS_TXPKTNUM))\n#define BIT_GET_TXPKTNUM(x) (((x) >> BIT_SHIFT_TXPKTNUM) & BIT_MASK_TXPKTNUM)\n#define BIT_SET_TXPKTNUM(x, v) (BIT_CLEAR_TXPKTNUM(x) | BIT_TXPKTNUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_BCN_CTRL_1\t\t\t\t(Offset 0x0204) */\n\n#define BIT_SHIFT_R_BCN_HEAD_SEL_V1 20\n#define BIT_MASK_R_BCN_HEAD_SEL_V1 0x7\n#define BIT_R_BCN_HEAD_SEL_V1(x)                                               \\\n\t(((x) & BIT_MASK_R_BCN_HEAD_SEL_V1) << BIT_SHIFT_R_BCN_HEAD_SEL_V1)\n#define BITS_R_BCN_HEAD_SEL_V1                                                 \\\n\t(BIT_MASK_R_BCN_HEAD_SEL_V1 << BIT_SHIFT_R_BCN_HEAD_SEL_V1)\n#define BIT_CLEAR_R_BCN_HEAD_SEL_V1(x) ((x) & (~BITS_R_BCN_HEAD_SEL_V1))\n#define BIT_GET_R_BCN_HEAD_SEL_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_R_BCN_HEAD_SEL_V1) & BIT_MASK_R_BCN_HEAD_SEL_V1)\n#define BIT_SET_R_BCN_HEAD_SEL_V1(x, v)                                        \\\n\t(BIT_CLEAR_R_BCN_HEAD_SEL_V1(x) | BIT_R_BCN_HEAD_SEL_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FIFOPAGE_INFO\t\t\t(Offset 0x0204) */\n\n#define BIT_SHIFT_PUBQ_AVAL_PG 16\n#define BIT_MASK_PUBQ_AVAL_PG 0xff\n#define BIT_PUBQ_AVAL_PG(x)                                                    \\\n\t(((x) & BIT_MASK_PUBQ_AVAL_PG) << BIT_SHIFT_PUBQ_AVAL_PG)\n#define BITS_PUBQ_AVAL_PG (BIT_MASK_PUBQ_AVAL_PG << BIT_SHIFT_PUBQ_AVAL_PG)\n#define BIT_CLEAR_PUBQ_AVAL_PG(x) ((x) & (~BITS_PUBQ_AVAL_PG))\n#define BIT_GET_PUBQ_AVAL_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_PUBQ_AVAL_PG) & BIT_MASK_PUBQ_AVAL_PG)\n#define BIT_SET_PUBQ_AVAL_PG(x, v)                                             \\\n\t(BIT_CLEAR_PUBQ_AVAL_PG(x) | BIT_PUBQ_AVAL_PG(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FIFOPAGE_CTRL_2\t\t\t(Offset 0x0204) */\n\n#define BIT_SHIFT_BCN_HEAD_1_V1 16\n#define BIT_MASK_BCN_HEAD_1_V1 0xfff\n#define BIT_BCN_HEAD_1_V1(x)                                                   \\\n\t(((x) & BIT_MASK_BCN_HEAD_1_V1) << BIT_SHIFT_BCN_HEAD_1_V1)\n#define BITS_BCN_HEAD_1_V1 (BIT_MASK_BCN_HEAD_1_V1 << BIT_SHIFT_BCN_HEAD_1_V1)\n#define BIT_CLEAR_BCN_HEAD_1_V1(x) ((x) & (~BITS_BCN_HEAD_1_V1))\n#define BIT_GET_BCN_HEAD_1_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_BCN_HEAD_1_V1) & BIT_MASK_BCN_HEAD_1_V1)\n#define BIT_SET_BCN_HEAD_1_V1(x, v)                                            \\\n\t(BIT_CLEAR_BCN_HEAD_1_V1(x) | BIT_BCN_HEAD_1_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_BCN_CTRL_1\t\t\t\t(Offset 0x0204) */\n\n#define BIT_SHIFT_BCN3_HEAD 16\n#define BIT_MASK_BCN3_HEAD 0xfff\n#define BIT_BCN3_HEAD(x) (((x) & BIT_MASK_BCN3_HEAD) << BIT_SHIFT_BCN3_HEAD)\n#define BITS_BCN3_HEAD (BIT_MASK_BCN3_HEAD << BIT_SHIFT_BCN3_HEAD)\n#define BIT_CLEAR_BCN3_HEAD(x) ((x) & (~BITS_BCN3_HEAD))\n#define BIT_GET_BCN3_HEAD(x) (((x) >> BIT_SHIFT_BCN3_HEAD) & BIT_MASK_BCN3_HEAD)\n#define BIT_SET_BCN3_HEAD(x, v) (BIT_CLEAR_BCN3_HEAD(x) | BIT_BCN3_HEAD(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FIFOPAGE_CTRL_2\t\t\t(Offset 0x0204) */\n\n#define BIT_BCN_VALID_V1 BIT(15)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_BCN_CTRL_1\t\t\t\t(Offset 0x0204) */\n\n#define BIT_BCN2_VALID BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FIFOPAGE_INFO\t\t\t(Offset 0x0204) */\n\n#define BIT_SHIFT_LPQ_AVAL_PG 8\n#define BIT_MASK_LPQ_AVAL_PG 0xff\n#define BIT_LPQ_AVAL_PG(x)                                                     \\\n\t(((x) & BIT_MASK_LPQ_AVAL_PG) << BIT_SHIFT_LPQ_AVAL_PG)\n#define BITS_LPQ_AVAL_PG (BIT_MASK_LPQ_AVAL_PG << BIT_SHIFT_LPQ_AVAL_PG)\n#define BIT_CLEAR_LPQ_AVAL_PG(x) ((x) & (~BITS_LPQ_AVAL_PG))\n#define BIT_GET_LPQ_AVAL_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_LPQ_AVAL_PG) & BIT_MASK_LPQ_AVAL_PG)\n#define BIT_SET_LPQ_AVAL_PG(x, v)                                              \\\n\t(BIT_CLEAR_LPQ_AVAL_PG(x) | BIT_LPQ_AVAL_PG(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_BCN_CTRL_1\t\t\t\t(Offset 0x0204) */\n\n#define BIT_TDE_ERROR_STOP BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FIFOPAGE_INFO\t\t\t(Offset 0x0204) */\n\n#define BIT_SHIFT_HPQ_AVAL_PG 0\n#define BIT_MASK_HPQ_AVAL_PG 0xff\n#define BIT_HPQ_AVAL_PG(x)                                                     \\\n\t(((x) & BIT_MASK_HPQ_AVAL_PG) << BIT_SHIFT_HPQ_AVAL_PG)\n#define BITS_HPQ_AVAL_PG (BIT_MASK_HPQ_AVAL_PG << BIT_SHIFT_HPQ_AVAL_PG)\n#define BIT_CLEAR_HPQ_AVAL_PG(x) ((x) & (~BITS_HPQ_AVAL_PG))\n#define BIT_GET_HPQ_AVAL_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HPQ_AVAL_PG) & BIT_MASK_HPQ_AVAL_PG)\n#define BIT_SET_HPQ_AVAL_PG(x, v)                                              \\\n\t(BIT_CLEAR_HPQ_AVAL_PG(x) | BIT_HPQ_AVAL_PG(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FIFOPAGE_CTRL_2\t\t\t(Offset 0x0204) */\n\n#define BIT_SHIFT_BCN_HEAD_V1 0\n#define BIT_MASK_BCN_HEAD_V1 0xfff\n#define BIT_BCN_HEAD_V1(x)                                                     \\\n\t(((x) & BIT_MASK_BCN_HEAD_V1) << BIT_SHIFT_BCN_HEAD_V1)\n#define BITS_BCN_HEAD_V1 (BIT_MASK_BCN_HEAD_V1 << BIT_SHIFT_BCN_HEAD_V1)\n#define BIT_CLEAR_BCN_HEAD_V1(x) ((x) & (~BITS_BCN_HEAD_V1))\n#define BIT_GET_BCN_HEAD_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_BCN_HEAD_V1) & BIT_MASK_BCN_HEAD_V1)\n#define BIT_SET_BCN_HEAD_V1(x, v)                                              \\\n\t(BIT_CLEAR_BCN_HEAD_V1(x) | BIT_BCN_HEAD_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_BCN_CTRL_1\t\t\t\t(Offset 0x0204) */\n\n#define BIT_SHIFT_BCN2_HEAD 0\n#define BIT_MASK_BCN2_HEAD 0xfff\n#define BIT_BCN2_HEAD(x) (((x) & BIT_MASK_BCN2_HEAD) << BIT_SHIFT_BCN2_HEAD)\n#define BITS_BCN2_HEAD (BIT_MASK_BCN2_HEAD << BIT_SHIFT_BCN2_HEAD)\n#define BIT_CLEAR_BCN2_HEAD(x) ((x) & (~BITS_BCN2_HEAD))\n#define BIT_GET_BCN2_HEAD(x) (((x) >> BIT_SHIFT_BCN2_HEAD) & BIT_MASK_BCN2_HEAD)\n#define BIT_SET_BCN2_HEAD(x, v) (BIT_CLEAR_BCN2_HEAD(x) | BIT_BCN2_HEAD(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DWBCN0_CTRL\t\t\t\t(Offset 0x0208) */\n\n#define BIT_SHIFT_LLT_FREE_PAGE 24\n#define BIT_MASK_LLT_FREE_PAGE 0xff\n#define BIT_LLT_FREE_PAGE(x)                                                   \\\n\t(((x) & BIT_MASK_LLT_FREE_PAGE) << BIT_SHIFT_LLT_FREE_PAGE)\n#define BITS_LLT_FREE_PAGE (BIT_MASK_LLT_FREE_PAGE << BIT_SHIFT_LLT_FREE_PAGE)\n#define BIT_CLEAR_LLT_FREE_PAGE(x) ((x) & (~BITS_LLT_FREE_PAGE))\n#define BIT_GET_LLT_FREE_PAGE(x)                                               \\\n\t(((x) >> BIT_SHIFT_LLT_FREE_PAGE) & BIT_MASK_LLT_FREE_PAGE)\n#define BIT_SET_LLT_FREE_PAGE(x, v)                                            \\\n\t(BIT_CLEAR_LLT_FREE_PAGE(x) | BIT_LLT_FREE_PAGE(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AUTO_LLT_V1\t\t\t\t(Offset 0x0208) */\n\n#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 24\n#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 0xff\n#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x)                                  \\\n\t(((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)                       \\\n\t << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)\n#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1                                    \\\n\t(BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1                               \\\n\t << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)\n#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x)                            \\\n\t((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1))\n#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x)                              \\\n\t(((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) &                   \\\n\t BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)\n#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x, v)                           \\\n\t(BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) |                         \\\n\t BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AUTO_LLT_V1\t\t\t\t(Offset 0x0208) */\n\n#define BIT_SHIFT_MAX_TX_PKT_V1 24\n#define BIT_MASK_MAX_TX_PKT_V1 0xff\n#define BIT_MAX_TX_PKT_V1(x)                                                   \\\n\t(((x) & BIT_MASK_MAX_TX_PKT_V1) << BIT_SHIFT_MAX_TX_PKT_V1)\n#define BITS_MAX_TX_PKT_V1 (BIT_MASK_MAX_TX_PKT_V1 << BIT_SHIFT_MAX_TX_PKT_V1)\n#define BIT_CLEAR_MAX_TX_PKT_V1(x) ((x) & (~BITS_MAX_TX_PKT_V1))\n#define BIT_GET_MAX_TX_PKT_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_MAX_TX_PKT_V1) & BIT_MASK_MAX_TX_PKT_V1)\n#define BIT_SET_MAX_TX_PKT_V1(x, v)                                            \\\n\t(BIT_CLEAR_MAX_TX_PKT_V1(x) | BIT_MAX_TX_PKT_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AUTO_LLT_V1\t\t\t\t(Offset 0x0208) */\n\n#define BIT_TDE_ERROR_STOP_V1 BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DWBCN0_CTRL\t\t\t\t(Offset 0x0208) */\n\n#define BIT_BCN_VALID BIT(16)\n\n#define BIT_SHIFT_BCN_HEAD 8\n#define BIT_MASK_BCN_HEAD 0xff\n#define BIT_BCN_HEAD(x) (((x) & BIT_MASK_BCN_HEAD) << BIT_SHIFT_BCN_HEAD)\n#define BITS_BCN_HEAD (BIT_MASK_BCN_HEAD << BIT_SHIFT_BCN_HEAD)\n#define BIT_CLEAR_BCN_HEAD(x) ((x) & (~BITS_BCN_HEAD))\n#define BIT_GET_BCN_HEAD(x) (((x) >> BIT_SHIFT_BCN_HEAD) & BIT_MASK_BCN_HEAD)\n#define BIT_SET_BCN_HEAD(x, v) (BIT_CLEAR_BCN_HEAD(x) | BIT_BCN_HEAD(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_AUTO_LLT_V1\t\t\t\t(Offset 0x0208) */\n\n#define BIT_SHIFT_LLT_FREE_PAGE_V1 8\n#define BIT_MASK_LLT_FREE_PAGE_V1 0xffff\n#define BIT_LLT_FREE_PAGE_V1(x)                                                \\\n\t(((x) & BIT_MASK_LLT_FREE_PAGE_V1) << BIT_SHIFT_LLT_FREE_PAGE_V1)\n#define BITS_LLT_FREE_PAGE_V1                                                  \\\n\t(BIT_MASK_LLT_FREE_PAGE_V1 << BIT_SHIFT_LLT_FREE_PAGE_V1)\n#define BIT_CLEAR_LLT_FREE_PAGE_V1(x) ((x) & (~BITS_LLT_FREE_PAGE_V1))\n#define BIT_GET_LLT_FREE_PAGE_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1) & BIT_MASK_LLT_FREE_PAGE_V1)\n#define BIT_SET_LLT_FREE_PAGE_V1(x, v)                                         \\\n\t(BIT_CLEAR_LLT_FREE_PAGE_V1(x) | BIT_LLT_FREE_PAGE_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AUTO_LLT_V1\t\t\t\t(Offset 0x0208) */\n\n#define BIT_SHIFT_LLT_FREE_PAGE_V2 8\n#define BIT_MASK_LLT_FREE_PAGE_V2 0xfff\n#define BIT_LLT_FREE_PAGE_V2(x)                                                \\\n\t(((x) & BIT_MASK_LLT_FREE_PAGE_V2) << BIT_SHIFT_LLT_FREE_PAGE_V2)\n#define BITS_LLT_FREE_PAGE_V2                                                  \\\n\t(BIT_MASK_LLT_FREE_PAGE_V2 << BIT_SHIFT_LLT_FREE_PAGE_V2)\n#define BIT_CLEAR_LLT_FREE_PAGE_V2(x) ((x) & (~BITS_LLT_FREE_PAGE_V2))\n#define BIT_GET_LLT_FREE_PAGE_V2(x)                                            \\\n\t(((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2) & BIT_MASK_LLT_FREE_PAGE_V2)\n#define BIT_SET_LLT_FREE_PAGE_V2(x, v)                                         \\\n\t(BIT_CLEAR_LLT_FREE_PAGE_V2(x) | BIT_LLT_FREE_PAGE_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AUTO_LLT_V1\t\t\t\t(Offset 0x0208) */\n\n#define BIT_SHIFT_BLK_DESC_NUM 4\n#define BIT_MASK_BLK_DESC_NUM 0xf\n#define BIT_BLK_DESC_NUM(x)                                                    \\\n\t(((x) & BIT_MASK_BLK_DESC_NUM) << BIT_SHIFT_BLK_DESC_NUM)\n#define BITS_BLK_DESC_NUM (BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM)\n#define BIT_CLEAR_BLK_DESC_NUM(x) ((x) & (~BITS_BLK_DESC_NUM))\n#define BIT_GET_BLK_DESC_NUM(x)                                                \\\n\t(((x) >> BIT_SHIFT_BLK_DESC_NUM) & BIT_MASK_BLK_DESC_NUM)\n#define BIT_SET_BLK_DESC_NUM(x, v)                                             \\\n\t(BIT_CLEAR_BLK_DESC_NUM(x) | BIT_BLK_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AUTO_LLT_V1\t\t\t\t(Offset 0x0208) */\n\n#define BIT_R_BCN_HEAD_SEL BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AUTO_LLT_V1\t\t\t\t(Offset 0x0208) */\n\n#define BIT_R_EN_BCN_SW_HEAD_SEL BIT(2)\n#define BIT_LLT_DBG_SEL BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DWBCN0_CTRL\t\t\t\t(Offset 0x0208) */\n\n#define BIT_BLK_DESC_OPT BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AUTO_LLT_V1\t\t\t\t(Offset 0x0208) */\n\n#define BIT_AUTO_INIT_LLT_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_OFFSET_CHK\t\t\t(Offset 0x020C) */\n\n#define BIT_EM_CHKSUM_FIN BIT(31)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TXDMA_OFFSET_CHK\t\t\t(Offset 0x020C) */\n\n#define BIT_EN_CHKSUM_ERR_FIN BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_OFFSET_CHK\t\t\t(Offset 0x020C) */\n\n#define BIT_EMN_PCIE_DMA_MOD BIT(30)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TXDMA_OFFSET_CHK\t\t\t(Offset 0x020C) */\n\n#define BIT_EN_PCIE_DMA_MOD BIT(30)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXDMA_OFFSET_CHK\t\t\t(Offset 0x020C) */\n\n#define BIT_EN_TXQUE_CLR BIT(29)\n#define BIT_EN_PCIE_FIFO_MODE BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_OFFSET_CHK\t\t\t(Offset 0x020C) */\n\n#define BIT_SHIFT_PG_UNDER_TH 16\n#define BIT_MASK_PG_UNDER_TH 0xff\n#define BIT_PG_UNDER_TH(x)                                                     \\\n\t(((x) & BIT_MASK_PG_UNDER_TH) << BIT_SHIFT_PG_UNDER_TH)\n#define BITS_PG_UNDER_TH (BIT_MASK_PG_UNDER_TH << BIT_SHIFT_PG_UNDER_TH)\n#define BIT_CLEAR_PG_UNDER_TH(x) ((x) & (~BITS_PG_UNDER_TH))\n#define BIT_GET_PG_UNDER_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_PG_UNDER_TH) & BIT_MASK_PG_UNDER_TH)\n#define BIT_SET_PG_UNDER_TH(x, v)                                              \\\n\t(BIT_CLEAR_PG_UNDER_TH(x) | BIT_PG_UNDER_TH(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TXDMA_OFFSET_CHK\t\t\t(Offset 0x020C) */\n\n#define BIT_SHIFT_PG_UNDER_TH_V2 16\n#define BIT_MASK_PG_UNDER_TH_V2 0xff\n#define BIT_PG_UNDER_TH_V2(x)                                                  \\\n\t(((x) & BIT_MASK_PG_UNDER_TH_V2) << BIT_SHIFT_PG_UNDER_TH_V2)\n#define BITS_PG_UNDER_TH_V2                                                    \\\n\t(BIT_MASK_PG_UNDER_TH_V2 << BIT_SHIFT_PG_UNDER_TH_V2)\n#define BIT_CLEAR_PG_UNDER_TH_V2(x) ((x) & (~BITS_PG_UNDER_TH_V2))\n#define BIT_GET_PG_UNDER_TH_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_PG_UNDER_TH_V2) & BIT_MASK_PG_UNDER_TH_V2)\n#define BIT_SET_PG_UNDER_TH_V2(x, v)                                           \\\n\t(BIT_CLEAR_PG_UNDER_TH_V2(x) | BIT_PG_UNDER_TH_V2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXDMA_OFFSET_CHK\t\t\t(Offset 0x020C) */\n\n#define BIT_SHIFT_PG_UNDER_TH_V1 16\n#define BIT_MASK_PG_UNDER_TH_V1 0xfff\n#define BIT_PG_UNDER_TH_V1(x)                                                  \\\n\t(((x) & BIT_MASK_PG_UNDER_TH_V1) << BIT_SHIFT_PG_UNDER_TH_V1)\n#define BITS_PG_UNDER_TH_V1                                                    \\\n\t(BIT_MASK_PG_UNDER_TH_V1 << BIT_SHIFT_PG_UNDER_TH_V1)\n#define BIT_CLEAR_PG_UNDER_TH_V1(x) ((x) & (~BITS_PG_UNDER_TH_V1))\n#define BIT_GET_PG_UNDER_TH_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_PG_UNDER_TH_V1) & BIT_MASK_PG_UNDER_TH_V1)\n#define BIT_SET_PG_UNDER_TH_V1(x, v)                                           \\\n\t(BIT_CLEAR_PG_UNDER_TH_V1(x) | BIT_PG_UNDER_TH_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_TXDMA_OFFSET_CHK\t\t\t(Offset 0x020C) */\n\n#define BIT_EN_RESTORE_H2C_BY_RST BIT(15)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_TXDMA_OFFSET_CHK\t\t\t(Offset 0x020C) */\n\n#define BIT_EN_RESET_RESTORE_H2C BIT(15)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXDMA_OFFSET_CHK\t\t\t(Offset 0x020C) */\n\n#define BIT_R_EN_RESET_RESTORE_H2C BIT(15)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_TXDMA_OFFSET_CHK\t\t\t(Offset 0x020C) */\n\n#define BIT_RESTORE_H2C_ADDRESS BIT(15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXDMA_OFFSET_CHK\t\t\t(Offset 0x020C) */\n\n#define BIT_SDIO_TDE_FINISH BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_OFFSET_CHK\t\t\t(Offset 0x020C) */\n\n#define BIT_SDIO_TXDESC_CHKSUM_EN BIT(13)\n#define BIT_RST_RDPTR BIT(12)\n#define BIT_RST_WRPTR BIT(11)\n#define BIT_CHK_PG_TH_EN BIT(10)\n#define BIT_DROP_DATA_EN BIT(9)\n#define BIT_CHECK_OFFSET_EN BIT(8)\n\n#define BIT_SHIFT_CHECK_OFFSET 0\n#define BIT_MASK_CHECK_OFFSET 0xff\n#define BIT_CHECK_OFFSET(x)                                                    \\\n\t(((x) & BIT_MASK_CHECK_OFFSET) << BIT_SHIFT_CHECK_OFFSET)\n#define BITS_CHECK_OFFSET (BIT_MASK_CHECK_OFFSET << BIT_SHIFT_CHECK_OFFSET)\n#define BIT_CLEAR_CHECK_OFFSET(x) ((x) & (~BITS_CHECK_OFFSET))\n#define BIT_GET_CHECK_OFFSET(x)                                                \\\n\t(((x) >> BIT_SHIFT_CHECK_OFFSET) & BIT_MASK_CHECK_OFFSET)\n#define BIT_SET_CHECK_OFFSET(x, v)                                             \\\n\t(BIT_CLEAR_CHECK_OFFSET(x) | BIT_CHECK_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_LD_RQPN BIT(31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_AMSDU_PKT_SIZE_ERR BIT(31)\n#define BIT_AMSDU_EN_ERR BIT(30)\n#define BIT_CHKSUM_AMSDU_EN_ERR BIT(29)\n#define BIT_TXPKTBF_REQ_ERR BIT(28)\n#define BIT_OQT_UDN_16 BIT(27)\n#define BIT_OQT_OVF_16 BIT(26)\n#define BIT_OQT_UDN_14_15 BIT(25)\n#define BIT_OQT_OVF_14_15 BIT(24)\n#define BIT_OQT_UDN_13 BIT(23)\n#define BIT_OQT_OVF_13 BIT(22)\n#define BIT_OQT_UDN_12 BIT(21)\n#define BIT_OQT_OVF_12 BIT(20)\n#define BIT_OQT_UDN_8_11 BIT(19)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_TXPKTBUF_REQ_ERR BIT(18)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_OQT_OVF_8_11 BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_HI_OQT_UDN BIT(17)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_OQT_UDN_4_7 BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_HI_OQT_OVF BIT(16)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_OQT_OVF_4_7 BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_PAYLOAD_CHKSUM_ERR BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_RX_CLOSE_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_PAYLOAD_UDN BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_STOP_BCNQ BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_PAYLOAD_OVF BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_STOP_MGQ BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_DSC_CHKSUM_FAIL BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_STOP_VOQ BIT(12)\n#define BIT_UNKNOWN_QSEL BIT(11)\n#define BIT_STOP_VIQ BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_EP_QSEL_DIFF BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_STOP_BEQ BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_TX_OFFS_UNMATCH BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_STOP_BKQ BIT(9)\n#define BIT_TXOQT_UDN BIT(8)\n#define BIT_STOP_RXQ BIT(8)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_TXOQT_UDN_0_3 BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_TXOQT_OVF BIT(7)\n#define BIT_STOP_HI7Q BIT(7)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_TXOQT_OVF_0_3 BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_TXDMA_SFF_UDN BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_STOP_HI6Q BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_TXDMA_SFF_OVF BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_STOP_HI5Q BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_LLT_NULL_PG BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_STOP_HI4Q BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_PAGE_UDN BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_STOP_HI3Q BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_PAGE_OVF BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_STOP_HI2Q BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_TXFF_PG_UDN BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_STOP_HI1Q BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_TXFF_PG_OVF BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXDMA_STATUS\t\t\t(Offset 0x0210) */\n\n#define BIT_STOP_HI0Q BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RQPN_NPQ\t\t\t\t(Offset 0x0214) */\n\n#define BIT_SHIFT_EXQ_AVAL_PG 24\n#define BIT_MASK_EXQ_AVAL_PG 0xff\n#define BIT_EXQ_AVAL_PG(x)                                                     \\\n\t(((x) & BIT_MASK_EXQ_AVAL_PG) << BIT_SHIFT_EXQ_AVAL_PG)\n#define BITS_EXQ_AVAL_PG (BIT_MASK_EXQ_AVAL_PG << BIT_SHIFT_EXQ_AVAL_PG)\n#define BIT_CLEAR_EXQ_AVAL_PG(x) ((x) & (~BITS_EXQ_AVAL_PG))\n#define BIT_GET_EXQ_AVAL_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_EXQ_AVAL_PG) & BIT_MASK_EXQ_AVAL_PG)\n#define BIT_SET_EXQ_AVAL_PG(x, v)                                              \\\n\t(BIT_CLEAR_EXQ_AVAL_PG(x) | BIT_EXQ_AVAL_PG(v))\n\n#define BIT_SHIFT_EXQ 16\n#define BIT_MASK_EXQ 0xff\n#define BIT_EXQ(x) (((x) & BIT_MASK_EXQ) << BIT_SHIFT_EXQ)\n#define BITS_EXQ (BIT_MASK_EXQ << BIT_SHIFT_EXQ)\n#define BIT_CLEAR_EXQ(x) ((x) & (~BITS_EXQ))\n#define BIT_GET_EXQ(x) (((x) >> BIT_SHIFT_EXQ) & BIT_MASK_EXQ)\n#define BIT_SET_EXQ(x, v) (BIT_CLEAR_EXQ(x) | BIT_EXQ(v))\n\n#define BIT_SHIFT_NPQ 0\n#define BIT_MASK_NPQ 0xff\n#define BIT_NPQ(x) (((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ)\n#define BITS_NPQ (BIT_MASK_NPQ << BIT_SHIFT_NPQ)\n#define BIT_CLEAR_NPQ(x) ((x) & (~BITS_NPQ))\n#define BIT_GET_NPQ(x) (((x) >> BIT_SHIFT_NPQ) & BIT_MASK_NPQ)\n#define BIT_SET_NPQ(x, v) (BIT_CLEAR_NPQ(x) | BIT_NPQ(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TQPNT1\t\t\t\t(Offset 0x0218) */\n\n#define BIT_HPQ_INT_EN BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TQPNT1\t\t\t\t(Offset 0x0218) */\n\n#define BIT_SHIFT_NPQ_HIGH_TH 24\n#define BIT_MASK_NPQ_HIGH_TH 0xff\n#define BIT_NPQ_HIGH_TH(x)                                                     \\\n\t(((x) & BIT_MASK_NPQ_HIGH_TH) << BIT_SHIFT_NPQ_HIGH_TH)\n#define BITS_NPQ_HIGH_TH (BIT_MASK_NPQ_HIGH_TH << BIT_SHIFT_NPQ_HIGH_TH)\n#define BIT_CLEAR_NPQ_HIGH_TH(x) ((x) & (~BITS_NPQ_HIGH_TH))\n#define BIT_GET_NPQ_HIGH_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_NPQ_HIGH_TH) & BIT_MASK_NPQ_HIGH_TH)\n#define BIT_SET_NPQ_HIGH_TH(x, v)                                              \\\n\t(BIT_CLEAR_NPQ_HIGH_TH(x) | BIT_NPQ_HIGH_TH(v))\n\n#define BIT_SHIFT_NPQ_LOW_TH 16\n#define BIT_MASK_NPQ_LOW_TH 0xff\n#define BIT_NPQ_LOW_TH(x) (((x) & BIT_MASK_NPQ_LOW_TH) << BIT_SHIFT_NPQ_LOW_TH)\n#define BITS_NPQ_LOW_TH (BIT_MASK_NPQ_LOW_TH << BIT_SHIFT_NPQ_LOW_TH)\n#define BIT_CLEAR_NPQ_LOW_TH(x) ((x) & (~BITS_NPQ_LOW_TH))\n#define BIT_GET_NPQ_LOW_TH(x)                                                  \\\n\t(((x) >> BIT_SHIFT_NPQ_LOW_TH) & BIT_MASK_NPQ_LOW_TH)\n#define BIT_SET_NPQ_LOW_TH(x, v) (BIT_CLEAR_NPQ_LOW_TH(x) | BIT_NPQ_LOW_TH(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TQPNT1\t\t\t\t(Offset 0x0218) */\n\n#define BIT_SHIFT_HPQ_HIGH_TH_V1 16\n#define BIT_MASK_HPQ_HIGH_TH_V1 0xfff\n#define BIT_HPQ_HIGH_TH_V1(x)                                                  \\\n\t(((x) & BIT_MASK_HPQ_HIGH_TH_V1) << BIT_SHIFT_HPQ_HIGH_TH_V1)\n#define BITS_HPQ_HIGH_TH_V1                                                    \\\n\t(BIT_MASK_HPQ_HIGH_TH_V1 << BIT_SHIFT_HPQ_HIGH_TH_V1)\n#define BIT_CLEAR_HPQ_HIGH_TH_V1(x) ((x) & (~BITS_HPQ_HIGH_TH_V1))\n#define BIT_GET_HPQ_HIGH_TH_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1) & BIT_MASK_HPQ_HIGH_TH_V1)\n#define BIT_SET_HPQ_HIGH_TH_V1(x, v)                                           \\\n\t(BIT_CLEAR_HPQ_HIGH_TH_V1(x) | BIT_HPQ_HIGH_TH_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DMA_RQPN_INFO_PUB\t\t\t(Offset 0x0218) */\n\n#define BIT_SHIFT_PUB_AVAL_PG 16\n#define BIT_MASK_PUB_AVAL_PG 0xfff\n#define BIT_PUB_AVAL_PG(x)                                                     \\\n\t(((x) & BIT_MASK_PUB_AVAL_PG) << BIT_SHIFT_PUB_AVAL_PG)\n#define BITS_PUB_AVAL_PG (BIT_MASK_PUB_AVAL_PG << BIT_SHIFT_PUB_AVAL_PG)\n#define BIT_CLEAR_PUB_AVAL_PG(x) ((x) & (~BITS_PUB_AVAL_PG))\n#define BIT_GET_PUB_AVAL_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_PUB_AVAL_PG) & BIT_MASK_PUB_AVAL_PG)\n#define BIT_SET_PUB_AVAL_PG(x, v)                                              \\\n\t(BIT_CLEAR_PUB_AVAL_PG(x) | BIT_PUB_AVAL_PG(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TQPNT1\t\t\t\t(Offset 0x0218) */\n\n#define BIT_SHIFT_HPQ_HIGH_TH 8\n#define BIT_MASK_HPQ_HIGH_TH 0xff\n#define BIT_HPQ_HIGH_TH(x)                                                     \\\n\t(((x) & BIT_MASK_HPQ_HIGH_TH) << BIT_SHIFT_HPQ_HIGH_TH)\n#define BITS_HPQ_HIGH_TH (BIT_MASK_HPQ_HIGH_TH << BIT_SHIFT_HPQ_HIGH_TH)\n#define BIT_CLEAR_HPQ_HIGH_TH(x) ((x) & (~BITS_HPQ_HIGH_TH))\n#define BIT_GET_HPQ_HIGH_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HPQ_HIGH_TH) & BIT_MASK_HPQ_HIGH_TH)\n#define BIT_SET_HPQ_HIGH_TH(x, v)                                              \\\n\t(BIT_CLEAR_HPQ_HIGH_TH(x) | BIT_HPQ_HIGH_TH(v))\n\n#define BIT_SHIFT_HPQ_LOW_TH 0\n#define BIT_MASK_HPQ_LOW_TH 0xff\n#define BIT_HPQ_LOW_TH(x) (((x) & BIT_MASK_HPQ_LOW_TH) << BIT_SHIFT_HPQ_LOW_TH)\n#define BITS_HPQ_LOW_TH (BIT_MASK_HPQ_LOW_TH << BIT_SHIFT_HPQ_LOW_TH)\n#define BIT_CLEAR_HPQ_LOW_TH(x) ((x) & (~BITS_HPQ_LOW_TH))\n#define BIT_GET_HPQ_LOW_TH(x)                                                  \\\n\t(((x) >> BIT_SHIFT_HPQ_LOW_TH) & BIT_MASK_HPQ_LOW_TH)\n#define BIT_SET_HPQ_LOW_TH(x, v) (BIT_CLEAR_HPQ_LOW_TH(x) | BIT_HPQ_LOW_TH(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TQPNT1\t\t\t\t(Offset 0x0218) */\n\n#define BIT_SHIFT_HPQ_LOW_TH_V1 0\n#define BIT_MASK_HPQ_LOW_TH_V1 0xfff\n#define BIT_HPQ_LOW_TH_V1(x)                                                   \\\n\t(((x) & BIT_MASK_HPQ_LOW_TH_V1) << BIT_SHIFT_HPQ_LOW_TH_V1)\n#define BITS_HPQ_LOW_TH_V1 (BIT_MASK_HPQ_LOW_TH_V1 << BIT_SHIFT_HPQ_LOW_TH_V1)\n#define BIT_CLEAR_HPQ_LOW_TH_V1(x) ((x) & (~BITS_HPQ_LOW_TH_V1))\n#define BIT_GET_HPQ_LOW_TH_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_HPQ_LOW_TH_V1) & BIT_MASK_HPQ_LOW_TH_V1)\n#define BIT_SET_HPQ_LOW_TH_V1(x, v)                                            \\\n\t(BIT_CLEAR_HPQ_LOW_TH_V1(x) | BIT_HPQ_LOW_TH_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DMA_RQPN_INFO_PUB\t\t\t(Offset 0x0218) */\n\n#define BIT_SHIFT_PUB_RSVD_PG 0\n#define BIT_MASK_PUB_RSVD_PG 0xfff\n#define BIT_PUB_RSVD_PG(x)                                                     \\\n\t(((x) & BIT_MASK_PUB_RSVD_PG) << BIT_SHIFT_PUB_RSVD_PG)\n#define BITS_PUB_RSVD_PG (BIT_MASK_PUB_RSVD_PG << BIT_SHIFT_PUB_RSVD_PG)\n#define BIT_CLEAR_PUB_RSVD_PG(x) ((x) & (~BITS_PUB_RSVD_PG))\n#define BIT_GET_PUB_RSVD_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_PUB_RSVD_PG) & BIT_MASK_PUB_RSVD_PG)\n#define BIT_SET_PUB_RSVD_PG(x, v)                                              \\\n\t(BIT_CLEAR_PUB_RSVD_PG(x) | BIT_PUB_RSVD_PG(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TQPNT2\t\t\t\t(Offset 0x021C) */\n\n#define BIT_NPQ_INT_EN BIT(31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_2_V1\t\t\t(Offset 0x021C) */\n\n#define BIT_LD_RQPN_V1 BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TQPNT2\t\t\t\t(Offset 0x021C) */\n\n#define BIT_SHIFT_EXQ_HIGH_TH 24\n#define BIT_MASK_EXQ_HIGH_TH 0xff\n#define BIT_EXQ_HIGH_TH(x)                                                     \\\n\t(((x) & BIT_MASK_EXQ_HIGH_TH) << BIT_SHIFT_EXQ_HIGH_TH)\n#define BITS_EXQ_HIGH_TH (BIT_MASK_EXQ_HIGH_TH << BIT_SHIFT_EXQ_HIGH_TH)\n#define BIT_CLEAR_EXQ_HIGH_TH(x) ((x) & (~BITS_EXQ_HIGH_TH))\n#define BIT_GET_EXQ_HIGH_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_EXQ_HIGH_TH) & BIT_MASK_EXQ_HIGH_TH)\n#define BIT_SET_EXQ_HIGH_TH(x, v)                                              \\\n\t(BIT_CLEAR_EXQ_HIGH_TH(x) | BIT_EXQ_HIGH_TH(v))\n\n#define BIT_SHIFT_EXQ_LOW_TH 16\n#define BIT_MASK_EXQ_LOW_TH 0xff\n#define BIT_EXQ_LOW_TH(x) (((x) & BIT_MASK_EXQ_LOW_TH) << BIT_SHIFT_EXQ_LOW_TH)\n#define BITS_EXQ_LOW_TH (BIT_MASK_EXQ_LOW_TH << BIT_SHIFT_EXQ_LOW_TH)\n#define BIT_CLEAR_EXQ_LOW_TH(x) ((x) & (~BITS_EXQ_LOW_TH))\n#define BIT_GET_EXQ_LOW_TH(x)                                                  \\\n\t(((x) >> BIT_SHIFT_EXQ_LOW_TH) & BIT_MASK_EXQ_LOW_TH)\n#define BIT_SET_EXQ_LOW_TH(x, v) (BIT_CLEAR_EXQ_LOW_TH(x) | BIT_EXQ_LOW_TH(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TQPNT2\t\t\t\t(Offset 0x021C) */\n\n#define BIT_SHIFT_NPQ_HIGH_TH_V1 16\n#define BIT_MASK_NPQ_HIGH_TH_V1 0xfff\n#define BIT_NPQ_HIGH_TH_V1(x)                                                  \\\n\t(((x) & BIT_MASK_NPQ_HIGH_TH_V1) << BIT_SHIFT_NPQ_HIGH_TH_V1)\n#define BITS_NPQ_HIGH_TH_V1                                                    \\\n\t(BIT_MASK_NPQ_HIGH_TH_V1 << BIT_SHIFT_NPQ_HIGH_TH_V1)\n#define BIT_CLEAR_NPQ_HIGH_TH_V1(x) ((x) & (~BITS_NPQ_HIGH_TH_V1))\n#define BIT_GET_NPQ_HIGH_TH_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1) & BIT_MASK_NPQ_HIGH_TH_V1)\n#define BIT_SET_NPQ_HIGH_TH_V1(x, v)                                           \\\n\t(BIT_CLEAR_NPQ_HIGH_TH_V1(x) | BIT_NPQ_HIGH_TH_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_2_V1\t\t\t(Offset 0x021C) */\n\n#define BIT_CH16_PUBLIC_DIS BIT(16)\n#define BIT_CH15_PUBLIC_DIS BIT(15)\n#define BIT_CH14_PUBLIC_DIS BIT(14)\n#define BIT_CH13_PUBLIC_DIS BIT(13)\n#define BIT_CH12_PUBLIC_DIS BIT(12)\n#define BIT_CH11_PUBLIC_DIS BIT(11)\n#define BIT_CH10_PUBLIC_DIS BIT(10)\n#define BIT_CH9_PUBLIC_DIS BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TQPNT2\t\t\t\t(Offset 0x021C) */\n\n#define BIT_SHIFT_LPQ_HIGH_TH 8\n#define BIT_MASK_LPQ_HIGH_TH 0xff\n#define BIT_LPQ_HIGH_TH(x)                                                     \\\n\t(((x) & BIT_MASK_LPQ_HIGH_TH) << BIT_SHIFT_LPQ_HIGH_TH)\n#define BITS_LPQ_HIGH_TH (BIT_MASK_LPQ_HIGH_TH << BIT_SHIFT_LPQ_HIGH_TH)\n#define BIT_CLEAR_LPQ_HIGH_TH(x) ((x) & (~BITS_LPQ_HIGH_TH))\n#define BIT_GET_LPQ_HIGH_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_LPQ_HIGH_TH) & BIT_MASK_LPQ_HIGH_TH)\n#define BIT_SET_LPQ_HIGH_TH(x, v)                                              \\\n\t(BIT_CLEAR_LPQ_HIGH_TH(x) | BIT_LPQ_HIGH_TH(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_2_V1\t\t\t(Offset 0x021C) */\n\n#define BIT_CH8_PUBLIC_DIS BIT(8)\n#define BIT_CH7_PUBLIC_DIS BIT(7)\n#define BIT_CH6_PUBLIC_DIS BIT(6)\n#define BIT_CH5_PUBLIC_DIS BIT(5)\n#define BIT_CH4_PUBLIC_DIS BIT(4)\n#define BIT_CH3_PUBLIC_DIS BIT(3)\n#define BIT_CH2_PUBLIC_DIS BIT(2)\n#define BIT_CH1_PUBLIC_DIS BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TQPNT2\t\t\t\t(Offset 0x021C) */\n\n#define BIT_SHIFT_LPQ_LOW_TH 0\n#define BIT_MASK_LPQ_LOW_TH 0xff\n#define BIT_LPQ_LOW_TH(x) (((x) & BIT_MASK_LPQ_LOW_TH) << BIT_SHIFT_LPQ_LOW_TH)\n#define BITS_LPQ_LOW_TH (BIT_MASK_LPQ_LOW_TH << BIT_SHIFT_LPQ_LOW_TH)\n#define BIT_CLEAR_LPQ_LOW_TH(x) ((x) & (~BITS_LPQ_LOW_TH))\n#define BIT_GET_LPQ_LOW_TH(x)                                                  \\\n\t(((x) >> BIT_SHIFT_LPQ_LOW_TH) & BIT_MASK_LPQ_LOW_TH)\n#define BIT_SET_LPQ_LOW_TH(x, v) (BIT_CLEAR_LPQ_LOW_TH(x) | BIT_LPQ_LOW_TH(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TQPNT2\t\t\t\t(Offset 0x021C) */\n\n#define BIT_SHIFT_NPQ_LOW_TH_V1 0\n#define BIT_MASK_NPQ_LOW_TH_V1 0xfff\n#define BIT_NPQ_LOW_TH_V1(x)                                                   \\\n\t(((x) & BIT_MASK_NPQ_LOW_TH_V1) << BIT_SHIFT_NPQ_LOW_TH_V1)\n#define BITS_NPQ_LOW_TH_V1 (BIT_MASK_NPQ_LOW_TH_V1 << BIT_SHIFT_NPQ_LOW_TH_V1)\n#define BIT_CLEAR_NPQ_LOW_TH_V1(x) ((x) & (~BITS_NPQ_LOW_TH_V1))\n#define BIT_GET_NPQ_LOW_TH_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_NPQ_LOW_TH_V1) & BIT_MASK_NPQ_LOW_TH_V1)\n#define BIT_SET_NPQ_LOW_TH_V1(x, v)                                            \\\n\t(BIT_CLEAR_NPQ_LOW_TH_V1(x) | BIT_NPQ_LOW_TH_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_2_V1\t\t\t(Offset 0x021C) */\n\n#define BIT_CH0_PUBLIC_DIS BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TQPNT3\t\t\t\t(Offset 0x0220) */\n\n#define BIT_LPQ_INT_EN BIT(31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_BCN_CTRL_2\t\t\t\t(Offset 0x0220) */\n\n#define BIT_BCN0_EXT_VALID BIT(31)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TQPNT3\t\t\t\t(Offset 0x0220) */\n\n#define BIT_SHIFT_LPQ_HIGH_TH_V1 16\n#define BIT_MASK_LPQ_HIGH_TH_V1 0xfff\n#define BIT_LPQ_HIGH_TH_V1(x)                                                  \\\n\t(((x) & BIT_MASK_LPQ_HIGH_TH_V1) << BIT_SHIFT_LPQ_HIGH_TH_V1)\n#define BITS_LPQ_HIGH_TH_V1                                                    \\\n\t(BIT_MASK_LPQ_HIGH_TH_V1 << BIT_SHIFT_LPQ_HIGH_TH_V1)\n#define BIT_CLEAR_LPQ_HIGH_TH_V1(x) ((x) & (~BITS_LPQ_HIGH_TH_V1))\n#define BIT_GET_LPQ_HIGH_TH_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1) & BIT_MASK_LPQ_HIGH_TH_V1)\n#define BIT_SET_LPQ_HIGH_TH_V1(x, v)                                           \\\n\t(BIT_CLEAR_LPQ_HIGH_TH_V1(x) | BIT_LPQ_HIGH_TH_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_BCN_CTRL_2\t\t\t\t(Offset 0x0220) */\n\n#define BIT_SHIFT_BCN0_EXT_HEAD 16\n#define BIT_MASK_BCN0_EXT_HEAD 0xfff\n#define BIT_BCN0_EXT_HEAD(x)                                                   \\\n\t(((x) & BIT_MASK_BCN0_EXT_HEAD) << BIT_SHIFT_BCN0_EXT_HEAD)\n#define BITS_BCN0_EXT_HEAD (BIT_MASK_BCN0_EXT_HEAD << BIT_SHIFT_BCN0_EXT_HEAD)\n#define BIT_CLEAR_BCN0_EXT_HEAD(x) ((x) & (~BITS_BCN0_EXT_HEAD))\n#define BIT_GET_BCN0_EXT_HEAD(x)                                               \\\n\t(((x) >> BIT_SHIFT_BCN0_EXT_HEAD) & BIT_MASK_BCN0_EXT_HEAD)\n#define BIT_SET_BCN0_EXT_HEAD(x, v)                                            \\\n\t(BIT_CLEAR_BCN0_EXT_HEAD(x) | BIT_BCN0_EXT_HEAD(v))\n\n#define BIT_SHIFT_TXPKTNUM_CH4_7 16\n#define BIT_MASK_TXPKTNUM_CH4_7 0xfff\n#define BIT_TXPKTNUM_CH4_7(x)                                                  \\\n\t(((x) & BIT_MASK_TXPKTNUM_CH4_7) << BIT_SHIFT_TXPKTNUM_CH4_7)\n#define BITS_TXPKTNUM_CH4_7                                                    \\\n\t(BIT_MASK_TXPKTNUM_CH4_7 << BIT_SHIFT_TXPKTNUM_CH4_7)\n#define BIT_CLEAR_TXPKTNUM_CH4_7(x) ((x) & (~BITS_TXPKTNUM_CH4_7))\n#define BIT_GET_TXPKTNUM_CH4_7(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_CH4_7) & BIT_MASK_TXPKTNUM_CH4_7)\n#define BIT_SET_TXPKTNUM_CH4_7(x, v)                                           \\\n\t(BIT_CLEAR_TXPKTNUM_CH4_7(x) | BIT_TXPKTNUM_CH4_7(v))\n\n#define BIT_SHIFT_TXPKTNUM_CH12 16\n#define BIT_MASK_TXPKTNUM_CH12 0xfff\n#define BIT_TXPKTNUM_CH12(x)                                                   \\\n\t(((x) & BIT_MASK_TXPKTNUM_CH12) << BIT_SHIFT_TXPKTNUM_CH12)\n#define BITS_TXPKTNUM_CH12 (BIT_MASK_TXPKTNUM_CH12 << BIT_SHIFT_TXPKTNUM_CH12)\n#define BIT_CLEAR_TXPKTNUM_CH12(x) ((x) & (~BITS_TXPKTNUM_CH12))\n#define BIT_GET_TXPKTNUM_CH12(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_CH12) & BIT_MASK_TXPKTNUM_CH12)\n#define BIT_SET_TXPKTNUM_CH12(x, v)                                            \\\n\t(BIT_CLEAR_TXPKTNUM_CH12(x) | BIT_TXPKTNUM_CH12(v))\n\n#define BIT_SHIFT_TXPKTNUM_CH14_15 16\n#define BIT_MASK_TXPKTNUM_CH14_15 0xfff\n#define BIT_TXPKTNUM_CH14_15(x)                                                \\\n\t(((x) & BIT_MASK_TXPKTNUM_CH14_15) << BIT_SHIFT_TXPKTNUM_CH14_15)\n#define BITS_TXPKTNUM_CH14_15                                                  \\\n\t(BIT_MASK_TXPKTNUM_CH14_15 << BIT_SHIFT_TXPKTNUM_CH14_15)\n#define BIT_CLEAR_TXPKTNUM_CH14_15(x) ((x) & (~BITS_TXPKTNUM_CH14_15))\n#define BIT_GET_TXPKTNUM_CH14_15(x)                                            \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_CH14_15) & BIT_MASK_TXPKTNUM_CH14_15)\n#define BIT_SET_TXPKTNUM_CH14_15(x, v)                                         \\\n\t(BIT_CLEAR_TXPKTNUM_CH14_15(x) | BIT_TXPKTNUM_CH14_15(v))\n\n#define BIT_BCN4_VALID BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TDE_DEBUG\t\t\t\t(Offset 0x0220) */\n\n#define BIT_SHIFT_TDE_DEBUG 0\n#define BIT_MASK_TDE_DEBUG 0xffffffffL\n#define BIT_TDE_DEBUG(x) (((x) & BIT_MASK_TDE_DEBUG) << BIT_SHIFT_TDE_DEBUG)\n#define BITS_TDE_DEBUG (BIT_MASK_TDE_DEBUG << BIT_SHIFT_TDE_DEBUG)\n#define BIT_CLEAR_TDE_DEBUG(x) ((x) & (~BITS_TDE_DEBUG))\n#define BIT_GET_TDE_DEBUG(x) (((x) >> BIT_SHIFT_TDE_DEBUG) & BIT_MASK_TDE_DEBUG)\n#define BIT_SET_TDE_DEBUG(x, v) (BIT_CLEAR_TDE_DEBUG(x) | BIT_TDE_DEBUG(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TQPNT3\t\t\t\t(Offset 0x0220) */\n\n#define BIT_SHIFT_LPQ_LOW_TH_V1 0\n#define BIT_MASK_LPQ_LOW_TH_V1 0xfff\n#define BIT_LPQ_LOW_TH_V1(x)                                                   \\\n\t(((x) & BIT_MASK_LPQ_LOW_TH_V1) << BIT_SHIFT_LPQ_LOW_TH_V1)\n#define BITS_LPQ_LOW_TH_V1 (BIT_MASK_LPQ_LOW_TH_V1 << BIT_SHIFT_LPQ_LOW_TH_V1)\n#define BIT_CLEAR_LPQ_LOW_TH_V1(x) ((x) & (~BITS_LPQ_LOW_TH_V1))\n#define BIT_GET_LPQ_LOW_TH_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_LPQ_LOW_TH_V1) & BIT_MASK_LPQ_LOW_TH_V1)\n#define BIT_SET_LPQ_LOW_TH_V1(x, v)                                            \\\n\t(BIT_CLEAR_LPQ_LOW_TH_V1(x) | BIT_LPQ_LOW_TH_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_BCN_CTRL_2\t\t\t\t(Offset 0x0220) */\n\n#define BIT_SHIFT_BCN4_HEAD 0\n#define BIT_MASK_BCN4_HEAD 0xfff\n#define BIT_BCN4_HEAD(x) (((x) & BIT_MASK_BCN4_HEAD) << BIT_SHIFT_BCN4_HEAD)\n#define BITS_BCN4_HEAD (BIT_MASK_BCN4_HEAD << BIT_SHIFT_BCN4_HEAD)\n#define BIT_CLEAR_BCN4_HEAD(x) ((x) & (~BITS_BCN4_HEAD))\n#define BIT_GET_BCN4_HEAD(x) (((x) >> BIT_SHIFT_BCN4_HEAD) & BIT_MASK_BCN4_HEAD)\n#define BIT_SET_BCN4_HEAD(x, v) (BIT_CLEAR_BCN4_HEAD(x) | BIT_BCN4_HEAD(v))\n\n#define BIT_SHIFT_TXPKTNUM_CH0_3 0\n#define BIT_MASK_TXPKTNUM_CH0_3 0xfff\n#define BIT_TXPKTNUM_CH0_3(x)                                                  \\\n\t(((x) & BIT_MASK_TXPKTNUM_CH0_3) << BIT_SHIFT_TXPKTNUM_CH0_3)\n#define BITS_TXPKTNUM_CH0_3                                                    \\\n\t(BIT_MASK_TXPKTNUM_CH0_3 << BIT_SHIFT_TXPKTNUM_CH0_3)\n#define BIT_CLEAR_TXPKTNUM_CH0_3(x) ((x) & (~BITS_TXPKTNUM_CH0_3))\n#define BIT_GET_TXPKTNUM_CH0_3(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_CH0_3) & BIT_MASK_TXPKTNUM_CH0_3)\n#define BIT_SET_TXPKTNUM_CH0_3(x, v)                                           \\\n\t(BIT_CLEAR_TXPKTNUM_CH0_3(x) | BIT_TXPKTNUM_CH0_3(v))\n\n#define BIT_SHIFT_TXPKTNUM_CH8_11 0\n#define BIT_MASK_TXPKTNUM_CH8_11 0xfff\n#define BIT_TXPKTNUM_CH8_11(x)                                                 \\\n\t(((x) & BIT_MASK_TXPKTNUM_CH8_11) << BIT_SHIFT_TXPKTNUM_CH8_11)\n#define BITS_TXPKTNUM_CH8_11                                                   \\\n\t(BIT_MASK_TXPKTNUM_CH8_11 << BIT_SHIFT_TXPKTNUM_CH8_11)\n#define BIT_CLEAR_TXPKTNUM_CH8_11(x) ((x) & (~BITS_TXPKTNUM_CH8_11))\n#define BIT_GET_TXPKTNUM_CH8_11(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_CH8_11) & BIT_MASK_TXPKTNUM_CH8_11)\n#define BIT_SET_TXPKTNUM_CH8_11(x, v)                                          \\\n\t(BIT_CLEAR_TXPKTNUM_CH8_11(x) | BIT_TXPKTNUM_CH8_11(v))\n\n#define BIT_SHIFT_TXPKTNUM_CH13 0\n#define BIT_MASK_TXPKTNUM_CH13 0xfff\n#define BIT_TXPKTNUM_CH13(x)                                                   \\\n\t(((x) & BIT_MASK_TXPKTNUM_CH13) << BIT_SHIFT_TXPKTNUM_CH13)\n#define BITS_TXPKTNUM_CH13 (BIT_MASK_TXPKTNUM_CH13 << BIT_SHIFT_TXPKTNUM_CH13)\n#define BIT_CLEAR_TXPKTNUM_CH13(x) ((x) & (~BITS_TXPKTNUM_CH13))\n#define BIT_GET_TXPKTNUM_CH13(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_CH13) & BIT_MASK_TXPKTNUM_CH13)\n#define BIT_SET_TXPKTNUM_CH13(x, v)                                            \\\n\t(BIT_CLEAR_TXPKTNUM_CH13(x) | BIT_TXPKTNUM_CH13(v))\n\n#define BIT_SHIFT_TXPKTNUM_CH16 0\n#define BIT_MASK_TXPKTNUM_CH16 0xfff\n#define BIT_TXPKTNUM_CH16(x)                                                   \\\n\t(((x) & BIT_MASK_TXPKTNUM_CH16) << BIT_SHIFT_TXPKTNUM_CH16)\n#define BITS_TXPKTNUM_CH16 (BIT_MASK_TXPKTNUM_CH16 << BIT_SHIFT_TXPKTNUM_CH16)\n#define BIT_CLEAR_TXPKTNUM_CH16(x) ((x) & (~BITS_TXPKTNUM_CH16))\n#define BIT_GET_TXPKTNUM_CH16(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_CH16) & BIT_MASK_TXPKTNUM_CH16)\n#define BIT_SET_TXPKTNUM_CH16(x, v)                                            \\\n\t(BIT_CLEAR_TXPKTNUM_CH16(x) | BIT_TXPKTNUM_CH16(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TQPNT4\t\t\t\t(Offset 0x0224) */\n\n#define BIT_EXQ_INT_EN BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AUTO_LLT\t\t\t\t(Offset 0x0224) */\n\n#define BIT_SHIFT_TXPKTNUM_V1 24\n#define BIT_MASK_TXPKTNUM_V1 0xff\n#define BIT_TXPKTNUM_V1(x)                                                     \\\n\t(((x) & BIT_MASK_TXPKTNUM_V1) << BIT_SHIFT_TXPKTNUM_V1)\n#define BITS_TXPKTNUM_V1 (BIT_MASK_TXPKTNUM_V1 << BIT_SHIFT_TXPKTNUM_V1)\n#define BIT_CLEAR_TXPKTNUM_V1(x) ((x) & (~BITS_TXPKTNUM_V1))\n#define BIT_GET_TXPKTNUM_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_V1) & BIT_MASK_TXPKTNUM_V1)\n#define BIT_SET_TXPKTNUM_V1(x, v)                                              \\\n\t(BIT_CLEAR_TXPKTNUM_V1(x) | BIT_TXPKTNUM_V1(v))\n\n#define BIT_TDE_DBG_SEL BIT(23)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_AUTO_LLT\t\t\t\t(Offset 0x0224) */\n\n#define BIT_MASK_QSEL_DIFF BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AUTO_LLT\t\t\t\t(Offset 0x0224) */\n\n#define BIT_AUTO_INIT_LLT BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TQPNT4\t\t\t\t(Offset 0x0224) */\n\n#define BIT_SHIFT_EXQ_HIGH_TH_V1 16\n#define BIT_MASK_EXQ_HIGH_TH_V1 0xfff\n#define BIT_EXQ_HIGH_TH_V1(x)                                                  \\\n\t(((x) & BIT_MASK_EXQ_HIGH_TH_V1) << BIT_SHIFT_EXQ_HIGH_TH_V1)\n#define BITS_EXQ_HIGH_TH_V1                                                    \\\n\t(BIT_MASK_EXQ_HIGH_TH_V1 << BIT_SHIFT_EXQ_HIGH_TH_V1)\n#define BIT_CLEAR_EXQ_HIGH_TH_V1(x) ((x) & (~BITS_EXQ_HIGH_TH_V1))\n#define BIT_GET_EXQ_HIGH_TH_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1) & BIT_MASK_EXQ_HIGH_TH_V1)\n#define BIT_SET_EXQ_HIGH_TH_V1(x, v)                                           \\\n\t(BIT_CLEAR_EXQ_HIGH_TH_V1(x) | BIT_EXQ_HIGH_TH_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AUTO_LLT\t\t\t\t(Offset 0x0224) */\n\n#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE 8\n#define BIT_MASK_TX_OQT_HE_FREE_SPACE 0xff\n#define BIT_TX_OQT_HE_FREE_SPACE(x)                                            \\\n\t(((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE)                                 \\\n\t << BIT_SHIFT_TX_OQT_HE_FREE_SPACE)\n#define BITS_TX_OQT_HE_FREE_SPACE                                              \\\n\t(BIT_MASK_TX_OQT_HE_FREE_SPACE << BIT_SHIFT_TX_OQT_HE_FREE_SPACE)\n#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_HE_FREE_SPACE))\n#define BIT_GET_TX_OQT_HE_FREE_SPACE(x)                                        \\\n\t(((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE) &                             \\\n\t BIT_MASK_TX_OQT_HE_FREE_SPACE)\n#define BIT_SET_TX_OQT_HE_FREE_SPACE(x, v)                                     \\\n\t(BIT_CLEAR_TX_OQT_HE_FREE_SPACE(x) | BIT_TX_OQT_HE_FREE_SPACE(v))\n\n#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE 0\n#define BIT_MASK_TX_OQT_NL_FREE_SPACE 0xff\n#define BIT_TX_OQT_NL_FREE_SPACE(x)                                            \\\n\t(((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE)                                 \\\n\t << BIT_SHIFT_TX_OQT_NL_FREE_SPACE)\n#define BITS_TX_OQT_NL_FREE_SPACE                                              \\\n\t(BIT_MASK_TX_OQT_NL_FREE_SPACE << BIT_SHIFT_TX_OQT_NL_FREE_SPACE)\n#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_NL_FREE_SPACE))\n#define BIT_GET_TX_OQT_NL_FREE_SPACE(x)                                        \\\n\t(((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE) &                             \\\n\t BIT_MASK_TX_OQT_NL_FREE_SPACE)\n#define BIT_SET_TX_OQT_NL_FREE_SPACE(x, v)                                     \\\n\t(BIT_CLEAR_TX_OQT_NL_FREE_SPACE(x) | BIT_TX_OQT_NL_FREE_SPACE(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TQPNT4\t\t\t\t(Offset 0x0224) */\n\n#define BIT_SHIFT_EXQ_LOW_TH_V1 0\n#define BIT_MASK_EXQ_LOW_TH_V1 0xfff\n#define BIT_EXQ_LOW_TH_V1(x)                                                   \\\n\t(((x) & BIT_MASK_EXQ_LOW_TH_V1) << BIT_SHIFT_EXQ_LOW_TH_V1)\n#define BITS_EXQ_LOW_TH_V1 (BIT_MASK_EXQ_LOW_TH_V1 << BIT_SHIFT_EXQ_LOW_TH_V1)\n#define BIT_CLEAR_EXQ_LOW_TH_V1(x) ((x) & (~BITS_EXQ_LOW_TH_V1))\n#define BIT_GET_EXQ_LOW_TH_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_EXQ_LOW_TH_V1) & BIT_MASK_EXQ_LOW_TH_V1)\n#define BIT_SET_EXQ_LOW_TH_V1(x, v)                                            \\\n\t(BIT_CLEAR_EXQ_LOW_TH_V1(x) | BIT_EXQ_LOW_TH_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DWBCN1_CTRL\t\t\t\t(Offset 0x0228) */\n\n#define BIT_SHIFT_BCN_HEAD_2 24\n#define BIT_MASK_BCN_HEAD_2 0xff\n#define BIT_BCN_HEAD_2(x) (((x) & BIT_MASK_BCN_HEAD_2) << BIT_SHIFT_BCN_HEAD_2)\n#define BITS_BCN_HEAD_2 (BIT_MASK_BCN_HEAD_2 << BIT_SHIFT_BCN_HEAD_2)\n#define BIT_CLEAR_BCN_HEAD_2(x) ((x) & (~BITS_BCN_HEAD_2))\n#define BIT_GET_BCN_HEAD_2(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BCN_HEAD_2) & BIT_MASK_BCN_HEAD_2)\n#define BIT_SET_BCN_HEAD_2(x, v) (BIT_CLEAR_BCN_HEAD_2(x) | BIT_BCN_HEAD_2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DWBCN1_CTRL\t\t\t\t(Offset 0x0228) */\n\n#define BIT_SW_BCN_SEL BIT(20)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DWBCN1_CTRL\t\t\t\t(Offset 0x0228) */\n\n#define BIT_SHIFT_SW_BCN_SEL_V1 20\n#define BIT_MASK_SW_BCN_SEL_V1 0x3\n#define BIT_SW_BCN_SEL_V1(x)                                                   \\\n\t(((x) & BIT_MASK_SW_BCN_SEL_V1) << BIT_SHIFT_SW_BCN_SEL_V1)\n#define BITS_SW_BCN_SEL_V1 (BIT_MASK_SW_BCN_SEL_V1 << BIT_SHIFT_SW_BCN_SEL_V1)\n#define BIT_CLEAR_SW_BCN_SEL_V1(x) ((x) & (~BITS_SW_BCN_SEL_V1))\n#define BIT_GET_SW_BCN_SEL_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_SW_BCN_SEL_V1) & BIT_MASK_SW_BCN_SEL_V1)\n#define BIT_SET_SW_BCN_SEL_V1(x, v)                                            \\\n\t(BIT_CLEAR_SW_BCN_SEL_V1(x) | BIT_SW_BCN_SEL_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_1\t\t\t\t(Offset 0x0228) */\n\n#define BIT_ENABLE_GEN_RANDON_SLOT_TX BIT(20)\n#define BIT_ENABLE_RANDOM_SHIFT_TX BIT(19)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DWBCN1_CTRL\t\t\t\t(Offset 0x0228) */\n\n#define BIT_BCN_VALID_2 BIT(18)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_1\t\t\t\t(Offset 0x0228) */\n\n#define BIT_ENABLE_EDCA_REF_FUNCTION BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DWBCN1_CTRL\t\t\t\t(Offset 0x0228) */\n\n#define BIT_SW_BCN_SEL_EN BIT(17)\n#define BIT_BCN_VALID_1 BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_1\t\t\t\t(Offset 0x0228) */\n\n#define BIT_SHIFT_TXPKTNUM_H 16\n#define BIT_MASK_TXPKTNUM_H 0xffff\n#define BIT_TXPKTNUM_H(x) (((x) & BIT_MASK_TXPKTNUM_H) << BIT_SHIFT_TXPKTNUM_H)\n#define BITS_TXPKTNUM_H (BIT_MASK_TXPKTNUM_H << BIT_SHIFT_TXPKTNUM_H)\n#define BIT_CLEAR_TXPKTNUM_H(x) ((x) & (~BITS_TXPKTNUM_H))\n#define BIT_GET_TXPKTNUM_H(x)                                                  \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_H) & BIT_MASK_TXPKTNUM_H)\n#define BIT_SET_TXPKTNUM_H(x, v) (BIT_CLEAR_TXPKTNUM_H(x) | BIT_TXPKTNUM_H(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_1\t\t\t\t(Offset 0x0228) */\n\n#define BIT_SHIFT_TXPKTNUM_H_V2 16\n#define BIT_MASK_TXPKTNUM_H_V2 0xfff\n#define BIT_TXPKTNUM_H_V2(x)                                                   \\\n\t(((x) & BIT_MASK_TXPKTNUM_H_V2) << BIT_SHIFT_TXPKTNUM_H_V2)\n#define BITS_TXPKTNUM_H_V2 (BIT_MASK_TXPKTNUM_H_V2 << BIT_SHIFT_TXPKTNUM_H_V2)\n#define BIT_CLEAR_TXPKTNUM_H_V2(x) ((x) & (~BITS_TXPKTNUM_H_V2))\n#define BIT_GET_TXPKTNUM_H_V2(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_H_V2) & BIT_MASK_TXPKTNUM_H_V2)\n#define BIT_SET_TXPKTNUM_H_V2(x, v)                                            \\\n\t(BIT_CLEAR_TXPKTNUM_H_V2(x) | BIT_TXPKTNUM_H_V2(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DWBCN1_CTRL\t\t\t\t(Offset 0x0228) */\n\n#define BIT_ADJUSTABLE_SIZE_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DWBCN1_CTRL\t\t\t\t(Offset 0x0228) */\n\n#define BIT_SHIFT_BCN_HEAD_1 8\n#define BIT_MASK_BCN_HEAD_1 0xff\n#define BIT_BCN_HEAD_1(x) (((x) & BIT_MASK_BCN_HEAD_1) << BIT_SHIFT_BCN_HEAD_1)\n#define BITS_BCN_HEAD_1 (BIT_MASK_BCN_HEAD_1 << BIT_SHIFT_BCN_HEAD_1)\n#define BIT_CLEAR_BCN_HEAD_1(x) ((x) & (~BITS_BCN_HEAD_1))\n#define BIT_GET_BCN_HEAD_1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BCN_HEAD_1) & BIT_MASK_BCN_HEAD_1)\n#define BIT_SET_BCN_HEAD_1(x, v) (BIT_CLEAR_BCN_HEAD_1(x) | BIT_BCN_HEAD_1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_1\t\t\t\t(Offset 0x0228) */\n\n#define BIT_RST_PGSUB_CNT BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DWBCN1_CTRL\t\t\t\t(Offset 0x0228) */\n\n#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO 0\n#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO 0xff\n#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO(x)                                     \\\n\t(((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO)                          \\\n\t << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO)\n#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO                                       \\\n\t(BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO                                  \\\n\t << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO)\n#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO(x)                               \\\n\t((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO))\n#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO(x)                                 \\\n\t(((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO) &                      \\\n\t BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO)\n#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO(x, v)                              \\\n\t(BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO(x) |                            \\\n\t BIT_MAX_TX_PKT_FOR_USB_AND_SDIO(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DWBCN1_CTRL\t\t\t\t(Offset 0x0228) */\n\n#define BIT_SHIFT_ALIGNMENT_SIZE 0\n#define BIT_MASK_ALIGNMENT_SIZE 0xfff\n#define BIT_ALIGNMENT_SIZE(x)                                                  \\\n\t(((x) & BIT_MASK_ALIGNMENT_SIZE) << BIT_SHIFT_ALIGNMENT_SIZE)\n#define BITS_ALIGNMENT_SIZE                                                    \\\n\t(BIT_MASK_ALIGNMENT_SIZE << BIT_SHIFT_ALIGNMENT_SIZE)\n#define BIT_CLEAR_ALIGNMENT_SIZE(x) ((x) & (~BITS_ALIGNMENT_SIZE))\n#define BIT_GET_ALIGNMENT_SIZE(x)                                              \\\n\t(((x) >> BIT_SHIFT_ALIGNMENT_SIZE) & BIT_MASK_ALIGNMENT_SIZE)\n#define BIT_SET_ALIGNMENT_SIZE(x, v)                                           \\\n\t(BIT_CLEAR_ALIGNMENT_SIZE(x) | BIT_ALIGNMENT_SIZE(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_1\t\t\t\t(Offset 0x0228) */\n\n#define BIT_SHIFT_TXPKTNUM_H_V1 0\n#define BIT_MASK_TXPKTNUM_H_V1 0xffff\n#define BIT_TXPKTNUM_H_V1(x)                                                   \\\n\t(((x) & BIT_MASK_TXPKTNUM_H_V1) << BIT_SHIFT_TXPKTNUM_H_V1)\n#define BITS_TXPKTNUM_H_V1 (BIT_MASK_TXPKTNUM_H_V1 << BIT_SHIFT_TXPKTNUM_H_V1)\n#define BIT_CLEAR_TXPKTNUM_H_V1(x) ((x) & (~BITS_TXPKTNUM_H_V1))\n#define BIT_GET_TXPKTNUM_H_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_H_V1) & BIT_MASK_TXPKTNUM_H_V1)\n#define BIT_SET_TXPKTNUM_H_V1(x, v)                                            \\\n\t(BIT_CLEAR_TXPKTNUM_H_V1(x) | BIT_TXPKTNUM_H_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_1\t\t\t\t(Offset 0x0228) */\n\n#define BIT_SHIFT_TXPKTNUM_H_V3 0\n#define BIT_MASK_TXPKTNUM_H_V3 0xfff\n#define BIT_TXPKTNUM_H_V3(x)                                                   \\\n\t(((x) & BIT_MASK_TXPKTNUM_H_V3) << BIT_SHIFT_TXPKTNUM_H_V3)\n#define BITS_TXPKTNUM_H_V3 (BIT_MASK_TXPKTNUM_H_V3 << BIT_SHIFT_TXPKTNUM_H_V3)\n#define BIT_CLEAR_TXPKTNUM_H_V3(x) ((x) & (~BITS_TXPKTNUM_H_V3))\n#define BIT_GET_TXPKTNUM_H_V3(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_H_V3) & BIT_MASK_TXPKTNUM_H_V3)\n#define BIT_SET_TXPKTNUM_H_V3(x, v)                                            \\\n\t(BIT_CLEAR_TXPKTNUM_H_V3(x) | BIT_TXPKTNUM_H_V3(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_1\t\t\t\t(Offset 0x0228) */\n\n#define BIT_SHIFT_TXPKTNUM_V3 0\n#define BIT_MASK_TXPKTNUM_V3 0xfff\n#define BIT_TXPKTNUM_V3(x)                                                     \\\n\t(((x) & BIT_MASK_TXPKTNUM_V3) << BIT_SHIFT_TXPKTNUM_V3)\n#define BITS_TXPKTNUM_V3 (BIT_MASK_TXPKTNUM_V3 << BIT_SHIFT_TXPKTNUM_V3)\n#define BIT_CLEAR_TXPKTNUM_V3(x) ((x) & (~BITS_TXPKTNUM_V3))\n#define BIT_GET_TXPKTNUM_V3(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_V3) & BIT_MASK_TXPKTNUM_V3)\n#define BIT_SET_TXPKTNUM_V3(x, v)                                              \\\n\t(BIT_CLEAR_TXPKTNUM_V3(x) | BIT_TXPKTNUM_V3(v))\n\n#define BIT_PGSUB_CNT_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_1\t\t\t\t(Offset 0x0228) */\n\n#define BIT_SHIFT_TXPKTNUM_V2 0\n#define BIT_MASK_TXPKTNUM_V2 0xffff\n#define BIT_TXPKTNUM_V2(x)                                                     \\\n\t(((x) & BIT_MASK_TXPKTNUM_V2) << BIT_SHIFT_TXPKTNUM_V2)\n#define BITS_TXPKTNUM_V2 (BIT_MASK_TXPKTNUM_V2 << BIT_SHIFT_TXPKTNUM_V2)\n#define BIT_CLEAR_TXPKTNUM_V2(x) ((x) & (~BITS_TXPKTNUM_V2))\n#define BIT_GET_TXPKTNUM_V2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_V2) & BIT_MASK_TXPKTNUM_V2)\n#define BIT_SET_TXPKTNUM_V2(x, v)                                              \\\n\t(BIT_CLEAR_TXPKTNUM_V2(x) | BIT_TXPKTNUM_V2(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_2\t\t\t\t(Offset 0x022C) */\n\n#define BIT_EX2Q_PUBLIC_DIS_V1 BIT(21)\n#define BIT_EX1Q_PUBLIC_DIS_V1 BIT(20)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_2\t\t\t\t(Offset 0x022C) */\n\n#define BIT_EXQ_PUBLIC_DIS_V1 BIT(19)\n#define BIT_NPQ_PUBLIC_DIS_V1 BIT(18)\n#define BIT_LPQ_PUBLIC_DIS_V1 BIT(17)\n#define BIT_HPQ_PUBLIC_DIS_V1 BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RQPN_CTRL_2\t\t\t\t(Offset 0x022C) */\n\n#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN BIT(15)\n\n#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE 0\n#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE 0xfff\n#define BIT_SDIO_TXAGG_ALIGN_SIZE(x)                                           \\\n\t(((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE)                                \\\n\t << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE)\n#define BITS_SDIO_TXAGG_ALIGN_SIZE                                             \\\n\t(BIT_MASK_SDIO_TXAGG_ALIGN_SIZE << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE)\n#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE(x) ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE))\n#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE(x)                                       \\\n\t(((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE) &                            \\\n\t BIT_MASK_SDIO_TXAGG_ALIGN_SIZE)\n#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE(x, v)                                    \\\n\t(BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE(x) | BIT_SDIO_TXAGG_ALIGN_SIZE(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_RQPN_EXQ1_EXQ2\t\t\t(Offset 0x0230) */\n\n#define BIT_SHIFT_EXQ2_AVAL_PG 24\n#define BIT_MASK_EXQ2_AVAL_PG 0xff\n#define BIT_EXQ2_AVAL_PG(x)                                                    \\\n\t(((x) & BIT_MASK_EXQ2_AVAL_PG) << BIT_SHIFT_EXQ2_AVAL_PG)\n#define BITS_EXQ2_AVAL_PG (BIT_MASK_EXQ2_AVAL_PG << BIT_SHIFT_EXQ2_AVAL_PG)\n#define BIT_CLEAR_EXQ2_AVAL_PG(x) ((x) & (~BITS_EXQ2_AVAL_PG))\n#define BIT_GET_EXQ2_AVAL_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_EXQ2_AVAL_PG) & BIT_MASK_EXQ2_AVAL_PG)\n#define BIT_SET_EXQ2_AVAL_PG(x, v)                                             \\\n\t(BIT_CLEAR_EXQ2_AVAL_PG(x) | BIT_EXQ2_AVAL_PG(v))\n\n#define BIT_SHIFT_EXQ2 16\n#define BIT_MASK_EXQ2 0xff\n#define BIT_EXQ2(x) (((x) & BIT_MASK_EXQ2) << BIT_SHIFT_EXQ2)\n#define BITS_EXQ2 (BIT_MASK_EXQ2 << BIT_SHIFT_EXQ2)\n#define BIT_CLEAR_EXQ2(x) ((x) & (~BITS_EXQ2))\n#define BIT_GET_EXQ2(x) (((x) >> BIT_SHIFT_EXQ2) & BIT_MASK_EXQ2)\n#define BIT_SET_EXQ2(x, v) (BIT_CLEAR_EXQ2(x) | BIT_EXQ2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FIFOPAGE_INFO_1\t\t\t(Offset 0x0230) */\n\n#define BIT_SHIFT_HPQ_AVAL_PG_V1 16\n#define BIT_MASK_HPQ_AVAL_PG_V1 0xfff\n#define BIT_HPQ_AVAL_PG_V1(x)                                                  \\\n\t(((x) & BIT_MASK_HPQ_AVAL_PG_V1) << BIT_SHIFT_HPQ_AVAL_PG_V1)\n#define BITS_HPQ_AVAL_PG_V1                                                    \\\n\t(BIT_MASK_HPQ_AVAL_PG_V1 << BIT_SHIFT_HPQ_AVAL_PG_V1)\n#define BIT_CLEAR_HPQ_AVAL_PG_V1(x) ((x) & (~BITS_HPQ_AVAL_PG_V1))\n#define BIT_GET_HPQ_AVAL_PG_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1) & BIT_MASK_HPQ_AVAL_PG_V1)\n#define BIT_SET_HPQ_AVAL_PG_V1(x, v)                                           \\\n\t(BIT_CLEAR_HPQ_AVAL_PG_V1(x) | BIT_HPQ_AVAL_PG_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_RQPN_EXQ1_EXQ2\t\t\t(Offset 0x0230) */\n\n#define BIT_SHIFT_EXQ1_AVAL_PG 8\n#define BIT_MASK_EXQ1_AVAL_PG 0xff\n#define BIT_EXQ1_AVAL_PG(x)                                                    \\\n\t(((x) & BIT_MASK_EXQ1_AVAL_PG) << BIT_SHIFT_EXQ1_AVAL_PG)\n#define BITS_EXQ1_AVAL_PG (BIT_MASK_EXQ1_AVAL_PG << BIT_SHIFT_EXQ1_AVAL_PG)\n#define BIT_CLEAR_EXQ1_AVAL_PG(x) ((x) & (~BITS_EXQ1_AVAL_PG))\n#define BIT_GET_EXQ1_AVAL_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_EXQ1_AVAL_PG) & BIT_MASK_EXQ1_AVAL_PG)\n#define BIT_SET_EXQ1_AVAL_PG(x, v)                                             \\\n\t(BIT_CLEAR_EXQ1_AVAL_PG(x) | BIT_EXQ1_AVAL_PG(v))\n\n#define BIT_SHIFT_EXQ1 0\n#define BIT_MASK_EXQ1 0xff\n#define BIT_EXQ1(x) (((x) & BIT_MASK_EXQ1) << BIT_SHIFT_EXQ1)\n#define BITS_EXQ1 (BIT_MASK_EXQ1 << BIT_SHIFT_EXQ1)\n#define BIT_CLEAR_EXQ1(x) ((x) & (~BITS_EXQ1))\n#define BIT_GET_EXQ1(x) (((x) >> BIT_SHIFT_EXQ1) & BIT_MASK_EXQ1)\n#define BIT_SET_EXQ1(x, v) (BIT_CLEAR_EXQ1(x) | BIT_EXQ1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FIFOPAGE_INFO_1\t\t\t(Offset 0x0230) */\n\n#define BIT_SHIFT_HPQ_V1 0\n#define BIT_MASK_HPQ_V1 0xfff\n#define BIT_HPQ_V1(x) (((x) & BIT_MASK_HPQ_V1) << BIT_SHIFT_HPQ_V1)\n#define BITS_HPQ_V1 (BIT_MASK_HPQ_V1 << BIT_SHIFT_HPQ_V1)\n#define BIT_CLEAR_HPQ_V1(x) ((x) & (~BITS_HPQ_V1))\n#define BIT_GET_HPQ_V1(x) (((x) >> BIT_SHIFT_HPQ_V1) & BIT_MASK_HPQ_V1)\n#define BIT_SET_HPQ_V1(x, v) (BIT_CLEAR_HPQ_V1(x) | BIT_HPQ_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TQPNT3_V1\t\t\t\t(Offset 0x0234) */\n\n#define BIT_SHIFT_EXQ2_HIGH_TH 24\n#define BIT_MASK_EXQ2_HIGH_TH 0xff\n#define BIT_EXQ2_HIGH_TH(x)                                                    \\\n\t(((x) & BIT_MASK_EXQ2_HIGH_TH) << BIT_SHIFT_EXQ2_HIGH_TH)\n#define BITS_EXQ2_HIGH_TH (BIT_MASK_EXQ2_HIGH_TH << BIT_SHIFT_EXQ2_HIGH_TH)\n#define BIT_CLEAR_EXQ2_HIGH_TH(x) ((x) & (~BITS_EXQ2_HIGH_TH))\n#define BIT_GET_EXQ2_HIGH_TH(x)                                                \\\n\t(((x) >> BIT_SHIFT_EXQ2_HIGH_TH) & BIT_MASK_EXQ2_HIGH_TH)\n#define BIT_SET_EXQ2_HIGH_TH(x, v)                                             \\\n\t(BIT_CLEAR_EXQ2_HIGH_TH(x) | BIT_EXQ2_HIGH_TH(v))\n\n#define BIT_SHIFT_EXQ2_LOW_TH 16\n#define BIT_MASK_EXQ2_LOW_TH 0xff\n#define BIT_EXQ2_LOW_TH(x)                                                     \\\n\t(((x) & BIT_MASK_EXQ2_LOW_TH) << BIT_SHIFT_EXQ2_LOW_TH)\n#define BITS_EXQ2_LOW_TH (BIT_MASK_EXQ2_LOW_TH << BIT_SHIFT_EXQ2_LOW_TH)\n#define BIT_CLEAR_EXQ2_LOW_TH(x) ((x) & (~BITS_EXQ2_LOW_TH))\n#define BIT_GET_EXQ2_LOW_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_EXQ2_LOW_TH) & BIT_MASK_EXQ2_LOW_TH)\n#define BIT_SET_EXQ2_LOW_TH(x, v)                                              \\\n\t(BIT_CLEAR_EXQ2_LOW_TH(x) | BIT_EXQ2_LOW_TH(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FIFOPAGE_INFO_2\t\t\t(Offset 0x0234) */\n\n#define BIT_SHIFT_LPQ_AVAL_PG_V1 16\n#define BIT_MASK_LPQ_AVAL_PG_V1 0xfff\n#define BIT_LPQ_AVAL_PG_V1(x)                                                  \\\n\t(((x) & BIT_MASK_LPQ_AVAL_PG_V1) << BIT_SHIFT_LPQ_AVAL_PG_V1)\n#define BITS_LPQ_AVAL_PG_V1                                                    \\\n\t(BIT_MASK_LPQ_AVAL_PG_V1 << BIT_SHIFT_LPQ_AVAL_PG_V1)\n#define BIT_CLEAR_LPQ_AVAL_PG_V1(x) ((x) & (~BITS_LPQ_AVAL_PG_V1))\n#define BIT_GET_LPQ_AVAL_PG_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1) & BIT_MASK_LPQ_AVAL_PG_V1)\n#define BIT_SET_LPQ_AVAL_PG_V1(x, v)                                           \\\n\t(BIT_CLEAR_LPQ_AVAL_PG_V1(x) | BIT_LPQ_AVAL_PG_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TQPNT3_V1\t\t\t\t(Offset 0x0234) */\n\n#define BIT_SHIFT_EXQ1_HIGH_TH 8\n#define BIT_MASK_EXQ1_HIGH_TH 0xff\n#define BIT_EXQ1_HIGH_TH(x)                                                    \\\n\t(((x) & BIT_MASK_EXQ1_HIGH_TH) << BIT_SHIFT_EXQ1_HIGH_TH)\n#define BITS_EXQ1_HIGH_TH (BIT_MASK_EXQ1_HIGH_TH << BIT_SHIFT_EXQ1_HIGH_TH)\n#define BIT_CLEAR_EXQ1_HIGH_TH(x) ((x) & (~BITS_EXQ1_HIGH_TH))\n#define BIT_GET_EXQ1_HIGH_TH(x)                                                \\\n\t(((x) >> BIT_SHIFT_EXQ1_HIGH_TH) & BIT_MASK_EXQ1_HIGH_TH)\n#define BIT_SET_EXQ1_HIGH_TH(x, v)                                             \\\n\t(BIT_CLEAR_EXQ1_HIGH_TH(x) | BIT_EXQ1_HIGH_TH(v))\n\n#define BIT_SHIFT_EXQ1_LOW_TH 0\n#define BIT_MASK_EXQ1_LOW_TH 0xff\n#define BIT_EXQ1_LOW_TH(x)                                                     \\\n\t(((x) & BIT_MASK_EXQ1_LOW_TH) << BIT_SHIFT_EXQ1_LOW_TH)\n#define BITS_EXQ1_LOW_TH (BIT_MASK_EXQ1_LOW_TH << BIT_SHIFT_EXQ1_LOW_TH)\n#define BIT_CLEAR_EXQ1_LOW_TH(x) ((x) & (~BITS_EXQ1_LOW_TH))\n#define BIT_GET_EXQ1_LOW_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_EXQ1_LOW_TH) & BIT_MASK_EXQ1_LOW_TH)\n#define BIT_SET_EXQ1_LOW_TH(x, v)                                              \\\n\t(BIT_CLEAR_EXQ1_LOW_TH(x) | BIT_EXQ1_LOW_TH(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FIFOPAGE_INFO_2\t\t\t(Offset 0x0234) */\n\n#define BIT_SHIFT_LPQ_V1 0\n#define BIT_MASK_LPQ_V1 0xfff\n#define BIT_LPQ_V1(x) (((x) & BIT_MASK_LPQ_V1) << BIT_SHIFT_LPQ_V1)\n#define BITS_LPQ_V1 (BIT_MASK_LPQ_V1 << BIT_SHIFT_LPQ_V1)\n#define BIT_CLEAR_LPQ_V1(x) ((x) & (~BITS_LPQ_V1))\n#define BIT_GET_LPQ_V1(x) (((x) >> BIT_SHIFT_LPQ_V1) & BIT_MASK_LPQ_V1)\n#define BIT_SET_LPQ_V1(x, v) (BIT_CLEAR_LPQ_V1(x) | BIT_LPQ_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FIFOPAGE_INFO_3\t\t\t(Offset 0x0238) */\n\n#define BIT_SHIFT_NPQ_AVAL_PG_V1 16\n#define BIT_MASK_NPQ_AVAL_PG_V1 0xfff\n#define BIT_NPQ_AVAL_PG_V1(x)                                                  \\\n\t(((x) & BIT_MASK_NPQ_AVAL_PG_V1) << BIT_SHIFT_NPQ_AVAL_PG_V1)\n#define BITS_NPQ_AVAL_PG_V1                                                    \\\n\t(BIT_MASK_NPQ_AVAL_PG_V1 << BIT_SHIFT_NPQ_AVAL_PG_V1)\n#define BIT_CLEAR_NPQ_AVAL_PG_V1(x) ((x) & (~BITS_NPQ_AVAL_PG_V1))\n#define BIT_GET_NPQ_AVAL_PG_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1) & BIT_MASK_NPQ_AVAL_PG_V1)\n#define BIT_SET_NPQ_AVAL_PG_V1(x, v)                                           \\\n\t(BIT_CLEAR_NPQ_AVAL_PG_V1(x) | BIT_NPQ_AVAL_PG_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FIFOPAGE_INFO_3\t\t\t(Offset 0x0238) */\n\n#define BIT_SHIFT_NPQ_V1 0\n#define BIT_MASK_NPQ_V1 0xfff\n#define BIT_NPQ_V1(x) (((x) & BIT_MASK_NPQ_V1) << BIT_SHIFT_NPQ_V1)\n#define BITS_NPQ_V1 (BIT_MASK_NPQ_V1 << BIT_SHIFT_NPQ_V1)\n#define BIT_CLEAR_NPQ_V1(x) ((x) & (~BITS_NPQ_V1))\n#define BIT_GET_NPQ_V1(x) (((x) >> BIT_SHIFT_NPQ_V1) & BIT_MASK_NPQ_V1)\n#define BIT_SET_NPQ_V1(x, v) (BIT_CLEAR_NPQ_V1(x) | BIT_NPQ_V1(v))\n\n/* 2 REG_FIFOPAGE_INFO_4\t\t\t(Offset 0x023C) */\n\n#define BIT_SHIFT_EXQ_AVAL_PG_V1 16\n#define BIT_MASK_EXQ_AVAL_PG_V1 0xfff\n#define BIT_EXQ_AVAL_PG_V1(x)                                                  \\\n\t(((x) & BIT_MASK_EXQ_AVAL_PG_V1) << BIT_SHIFT_EXQ_AVAL_PG_V1)\n#define BITS_EXQ_AVAL_PG_V1                                                    \\\n\t(BIT_MASK_EXQ_AVAL_PG_V1 << BIT_SHIFT_EXQ_AVAL_PG_V1)\n#define BIT_CLEAR_EXQ_AVAL_PG_V1(x) ((x) & (~BITS_EXQ_AVAL_PG_V1))\n#define BIT_GET_EXQ_AVAL_PG_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1) & BIT_MASK_EXQ_AVAL_PG_V1)\n#define BIT_SET_EXQ_AVAL_PG_V1(x, v)                                           \\\n\t(BIT_CLEAR_EXQ_AVAL_PG_V1(x) | BIT_EXQ_AVAL_PG_V1(v))\n\n#define BIT_SHIFT_EXQ_V1 0\n#define BIT_MASK_EXQ_V1 0xfff\n#define BIT_EXQ_V1(x) (((x) & BIT_MASK_EXQ_V1) << BIT_SHIFT_EXQ_V1)\n#define BITS_EXQ_V1 (BIT_MASK_EXQ_V1 << BIT_SHIFT_EXQ_V1)\n#define BIT_CLEAR_EXQ_V1(x) ((x) & (~BITS_EXQ_V1))\n#define BIT_GET_EXQ_V1(x) (((x) >> BIT_SHIFT_EXQ_V1) & BIT_MASK_EXQ_V1)\n#define BIT_SET_EXQ_V1(x, v) (BIT_CLEAR_EXQ_V1(x) | BIT_EXQ_V1(v))\n\n/* 2 REG_FIFOPAGE_INFO_5\t\t\t(Offset 0x0240) */\n\n#define BIT_SHIFT_PUBQ_AVAL_PG_V1 16\n#define BIT_MASK_PUBQ_AVAL_PG_V1 0xfff\n#define BIT_PUBQ_AVAL_PG_V1(x)                                                 \\\n\t(((x) & BIT_MASK_PUBQ_AVAL_PG_V1) << BIT_SHIFT_PUBQ_AVAL_PG_V1)\n#define BITS_PUBQ_AVAL_PG_V1                                                   \\\n\t(BIT_MASK_PUBQ_AVAL_PG_V1 << BIT_SHIFT_PUBQ_AVAL_PG_V1)\n#define BIT_CLEAR_PUBQ_AVAL_PG_V1(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1))\n#define BIT_GET_PUBQ_AVAL_PG_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1) & BIT_MASK_PUBQ_AVAL_PG_V1)\n#define BIT_SET_PUBQ_AVAL_PG_V1(x, v)                                          \\\n\t(BIT_CLEAR_PUBQ_AVAL_PG_V1(x) | BIT_PUBQ_AVAL_PG_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TX_AGG_ALIGN\t\t\t(Offset 0x0240) */\n\n#define BIT_SHIFT_HW_FLOW_CTL_EN 16\n#define BIT_MASK_HW_FLOW_CTL_EN 0xffff\n#define BIT_HW_FLOW_CTL_EN(x)                                                  \\\n\t(((x) & BIT_MASK_HW_FLOW_CTL_EN) << BIT_SHIFT_HW_FLOW_CTL_EN)\n#define BITS_HW_FLOW_CTL_EN                                                    \\\n\t(BIT_MASK_HW_FLOW_CTL_EN << BIT_SHIFT_HW_FLOW_CTL_EN)\n#define BIT_CLEAR_HW_FLOW_CTL_EN(x) ((x) & (~BITS_HW_FLOW_CTL_EN))\n#define BIT_GET_HW_FLOW_CTL_EN(x)                                              \\\n\t(((x) >> BIT_SHIFT_HW_FLOW_CTL_EN) & BIT_MASK_HW_FLOW_CTL_EN)\n#define BIT_SET_HW_FLOW_CTL_EN(x, v)                                           \\\n\t(BIT_CLEAR_HW_FLOW_CTL_EN(x) | BIT_HW_FLOW_CTL_EN(v))\n\n#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_V1 BIT(15)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FIFOPAGE_INFO_5\t\t\t(Offset 0x0240) */\n\n#define BIT_SHIFT_PUBQ_V1 0\n#define BIT_MASK_PUBQ_V1 0xfff\n#define BIT_PUBQ_V1(x) (((x) & BIT_MASK_PUBQ_V1) << BIT_SHIFT_PUBQ_V1)\n#define BITS_PUBQ_V1 (BIT_MASK_PUBQ_V1 << BIT_SHIFT_PUBQ_V1)\n#define BIT_CLEAR_PUBQ_V1(x) ((x) & (~BITS_PUBQ_V1))\n#define BIT_GET_PUBQ_V1(x) (((x) >> BIT_SHIFT_PUBQ_V1) & BIT_MASK_PUBQ_V1)\n#define BIT_SET_PUBQ_V1(x, v) (BIT_CLEAR_PUBQ_V1(x) | BIT_PUBQ_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TX_AGG_ALIGN\t\t\t(Offset 0x0240) */\n\n#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1 0\n#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1 0xfff\n#define BIT_SDIO_TXAGG_ALIGN_SIZE_V1(x)                                        \\\n\t(((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1)                             \\\n\t << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1)\n#define BITS_SDIO_TXAGG_ALIGN_SIZE_V1                                          \\\n\t(BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1                                     \\\n\t << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1)\n#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1(x)                                  \\\n\t((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_V1))\n#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_V1(x)                                    \\\n\t(((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1) &                         \\\n\t BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1)\n#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_V1(x, v)                                 \\\n\t(BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1(x) |                               \\\n\t BIT_SDIO_TXAGG_ALIGN_SIZE_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_H2C_HEAD\t\t\t\t(Offset 0x0244) */\n\n#define BIT_SHIFT_H2C_HEAD_V2 0\n#define BIT_MASK_H2C_HEAD_V2 0xffff\n#define BIT_H2C_HEAD_V2(x)                                                     \\\n\t(((x) & BIT_MASK_H2C_HEAD_V2) << BIT_SHIFT_H2C_HEAD_V2)\n#define BITS_H2C_HEAD_V2 (BIT_MASK_H2C_HEAD_V2 << BIT_SHIFT_H2C_HEAD_V2)\n#define BIT_CLEAR_H2C_HEAD_V2(x) ((x) & (~BITS_H2C_HEAD_V2))\n#define BIT_GET_H2C_HEAD_V2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_H2C_HEAD_V2) & BIT_MASK_H2C_HEAD_V2)\n#define BIT_SET_H2C_HEAD_V2(x, v)                                              \\\n\t(BIT_CLEAR_H2C_HEAD_V2(x) | BIT_H2C_HEAD_V2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_H2C_HEAD\t\t\t\t(Offset 0x0244) */\n\n#define BIT_SHIFT_H2C_HEAD 0\n#define BIT_MASK_H2C_HEAD 0x3ffff\n#define BIT_H2C_HEAD(x) (((x) & BIT_MASK_H2C_HEAD) << BIT_SHIFT_H2C_HEAD)\n#define BITS_H2C_HEAD (BIT_MASK_H2C_HEAD << BIT_SHIFT_H2C_HEAD)\n#define BIT_CLEAR_H2C_HEAD(x) ((x) & (~BITS_H2C_HEAD))\n#define BIT_GET_H2C_HEAD(x) (((x) >> BIT_SHIFT_H2C_HEAD) & BIT_MASK_H2C_HEAD)\n#define BIT_SET_H2C_HEAD(x, v) (BIT_CLEAR_H2C_HEAD(x) | BIT_H2C_HEAD(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_H2C_HEAD\t\t\t\t(Offset 0x0244) */\n\n#define BIT_SHIFT_H2C_HEAD_V1 0\n#define BIT_MASK_H2C_HEAD_V1 0x7ffff\n#define BIT_H2C_HEAD_V1(x)                                                     \\\n\t(((x) & BIT_MASK_H2C_HEAD_V1) << BIT_SHIFT_H2C_HEAD_V1)\n#define BITS_H2C_HEAD_V1 (BIT_MASK_H2C_HEAD_V1 << BIT_SHIFT_H2C_HEAD_V1)\n#define BIT_CLEAR_H2C_HEAD_V1(x) ((x) & (~BITS_H2C_HEAD_V1))\n#define BIT_GET_H2C_HEAD_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_H2C_HEAD_V1) & BIT_MASK_H2C_HEAD_V1)\n#define BIT_SET_H2C_HEAD_V1(x, v)                                              \\\n\t(BIT_CLEAR_H2C_HEAD_V1(x) | BIT_H2C_HEAD_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_H2C_TAIL\t\t\t\t(Offset 0x0248) */\n\n#define BIT_SHIFT_H2C_TAIL_V2 0\n#define BIT_MASK_H2C_TAIL_V2 0xffff\n#define BIT_H2C_TAIL_V2(x)                                                     \\\n\t(((x) & BIT_MASK_H2C_TAIL_V2) << BIT_SHIFT_H2C_TAIL_V2)\n#define BITS_H2C_TAIL_V2 (BIT_MASK_H2C_TAIL_V2 << BIT_SHIFT_H2C_TAIL_V2)\n#define BIT_CLEAR_H2C_TAIL_V2(x) ((x) & (~BITS_H2C_TAIL_V2))\n#define BIT_GET_H2C_TAIL_V2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_H2C_TAIL_V2) & BIT_MASK_H2C_TAIL_V2)\n#define BIT_SET_H2C_TAIL_V2(x, v)                                              \\\n\t(BIT_CLEAR_H2C_TAIL_V2(x) | BIT_H2C_TAIL_V2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_H2C_TAIL\t\t\t\t(Offset 0x0248) */\n\n#define BIT_SHIFT_H2C_TAIL 0\n#define BIT_MASK_H2C_TAIL 0x3ffff\n#define BIT_H2C_TAIL(x) (((x) & BIT_MASK_H2C_TAIL) << BIT_SHIFT_H2C_TAIL)\n#define BITS_H2C_TAIL (BIT_MASK_H2C_TAIL << BIT_SHIFT_H2C_TAIL)\n#define BIT_CLEAR_H2C_TAIL(x) ((x) & (~BITS_H2C_TAIL))\n#define BIT_GET_H2C_TAIL(x) (((x) >> BIT_SHIFT_H2C_TAIL) & BIT_MASK_H2C_TAIL)\n#define BIT_SET_H2C_TAIL(x, v) (BIT_CLEAR_H2C_TAIL(x) | BIT_H2C_TAIL(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_H2C_TAIL\t\t\t\t(Offset 0x0248) */\n\n#define BIT_SHIFT_H2C_TAIL_V1 0\n#define BIT_MASK_H2C_TAIL_V1 0x7ffff\n#define BIT_H2C_TAIL_V1(x)                                                     \\\n\t(((x) & BIT_MASK_H2C_TAIL_V1) << BIT_SHIFT_H2C_TAIL_V1)\n#define BITS_H2C_TAIL_V1 (BIT_MASK_H2C_TAIL_V1 << BIT_SHIFT_H2C_TAIL_V1)\n#define BIT_CLEAR_H2C_TAIL_V1(x) ((x) & (~BITS_H2C_TAIL_V1))\n#define BIT_GET_H2C_TAIL_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_H2C_TAIL_V1) & BIT_MASK_H2C_TAIL_V1)\n#define BIT_SET_H2C_TAIL_V1(x, v)                                              \\\n\t(BIT_CLEAR_H2C_TAIL_V1(x) | BIT_H2C_TAIL_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_H2C_READ_ADDR\t\t\t(Offset 0x024C) */\n\n#define BIT_SHIFT_H2C_READ_ADDR_V2 0\n#define BIT_MASK_H2C_READ_ADDR_V2 0xffff\n#define BIT_H2C_READ_ADDR_V2(x)                                                \\\n\t(((x) & BIT_MASK_H2C_READ_ADDR_V2) << BIT_SHIFT_H2C_READ_ADDR_V2)\n#define BITS_H2C_READ_ADDR_V2                                                  \\\n\t(BIT_MASK_H2C_READ_ADDR_V2 << BIT_SHIFT_H2C_READ_ADDR_V2)\n#define BIT_CLEAR_H2C_READ_ADDR_V2(x) ((x) & (~BITS_H2C_READ_ADDR_V2))\n#define BIT_GET_H2C_READ_ADDR_V2(x)                                            \\\n\t(((x) >> BIT_SHIFT_H2C_READ_ADDR_V2) & BIT_MASK_H2C_READ_ADDR_V2)\n#define BIT_SET_H2C_READ_ADDR_V2(x, v)                                         \\\n\t(BIT_CLEAR_H2C_READ_ADDR_V2(x) | BIT_H2C_READ_ADDR_V2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_H2C_READ_ADDR\t\t\t(Offset 0x024C) */\n\n#define BIT_SHIFT_H2C_READ_ADDR 0\n#define BIT_MASK_H2C_READ_ADDR 0x3ffff\n#define BIT_H2C_READ_ADDR(x)                                                   \\\n\t(((x) & BIT_MASK_H2C_READ_ADDR) << BIT_SHIFT_H2C_READ_ADDR)\n#define BITS_H2C_READ_ADDR (BIT_MASK_H2C_READ_ADDR << BIT_SHIFT_H2C_READ_ADDR)\n#define BIT_CLEAR_H2C_READ_ADDR(x) ((x) & (~BITS_H2C_READ_ADDR))\n#define BIT_GET_H2C_READ_ADDR(x)                                               \\\n\t(((x) >> BIT_SHIFT_H2C_READ_ADDR) & BIT_MASK_H2C_READ_ADDR)\n#define BIT_SET_H2C_READ_ADDR(x, v)                                            \\\n\t(BIT_CLEAR_H2C_READ_ADDR(x) | BIT_H2C_READ_ADDR(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_H2C_READ_ADDR\t\t\t(Offset 0x024C) */\n\n#define BIT_SHIFT_H2C_READ_ADDR_V1 0\n#define BIT_MASK_H2C_READ_ADDR_V1 0x7ffff\n#define BIT_H2C_READ_ADDR_V1(x)                                                \\\n\t(((x) & BIT_MASK_H2C_READ_ADDR_V1) << BIT_SHIFT_H2C_READ_ADDR_V1)\n#define BITS_H2C_READ_ADDR_V1                                                  \\\n\t(BIT_MASK_H2C_READ_ADDR_V1 << BIT_SHIFT_H2C_READ_ADDR_V1)\n#define BIT_CLEAR_H2C_READ_ADDR_V1(x) ((x) & (~BITS_H2C_READ_ADDR_V1))\n#define BIT_GET_H2C_READ_ADDR_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_H2C_READ_ADDR_V1) & BIT_MASK_H2C_READ_ADDR_V1)\n#define BIT_SET_H2C_READ_ADDR_V1(x, v)                                         \\\n\t(BIT_CLEAR_H2C_READ_ADDR_V1(x) | BIT_H2C_READ_ADDR_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_H2C_WR_ADDR\t\t\t\t(Offset 0x0250) */\n\n#define BIT_SHIFT_H2C_WR_ADDR_V2 0\n#define BIT_MASK_H2C_WR_ADDR_V2 0xffff\n#define BIT_H2C_WR_ADDR_V2(x)                                                  \\\n\t(((x) & BIT_MASK_H2C_WR_ADDR_V2) << BIT_SHIFT_H2C_WR_ADDR_V2)\n#define BITS_H2C_WR_ADDR_V2                                                    \\\n\t(BIT_MASK_H2C_WR_ADDR_V2 << BIT_SHIFT_H2C_WR_ADDR_V2)\n#define BIT_CLEAR_H2C_WR_ADDR_V2(x) ((x) & (~BITS_H2C_WR_ADDR_V2))\n#define BIT_GET_H2C_WR_ADDR_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_H2C_WR_ADDR_V2) & BIT_MASK_H2C_WR_ADDR_V2)\n#define BIT_SET_H2C_WR_ADDR_V2(x, v)                                           \\\n\t(BIT_CLEAR_H2C_WR_ADDR_V2(x) | BIT_H2C_WR_ADDR_V2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_H2C_WR_ADDR\t\t\t\t(Offset 0x0250) */\n\n#define BIT_SHIFT_H2C_WR_ADDR 0\n#define BIT_MASK_H2C_WR_ADDR 0x3ffff\n#define BIT_H2C_WR_ADDR(x)                                                     \\\n\t(((x) & BIT_MASK_H2C_WR_ADDR) << BIT_SHIFT_H2C_WR_ADDR)\n#define BITS_H2C_WR_ADDR (BIT_MASK_H2C_WR_ADDR << BIT_SHIFT_H2C_WR_ADDR)\n#define BIT_CLEAR_H2C_WR_ADDR(x) ((x) & (~BITS_H2C_WR_ADDR))\n#define BIT_GET_H2C_WR_ADDR(x)                                                 \\\n\t(((x) >> BIT_SHIFT_H2C_WR_ADDR) & BIT_MASK_H2C_WR_ADDR)\n#define BIT_SET_H2C_WR_ADDR(x, v)                                              \\\n\t(BIT_CLEAR_H2C_WR_ADDR(x) | BIT_H2C_WR_ADDR(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_H2C_WR_ADDR\t\t\t\t(Offset 0x0250) */\n\n#define BIT_SHIFT_H2C_WR_ADDR_V1 0\n#define BIT_MASK_H2C_WR_ADDR_V1 0x7ffff\n#define BIT_H2C_WR_ADDR_V1(x)                                                  \\\n\t(((x) & BIT_MASK_H2C_WR_ADDR_V1) << BIT_SHIFT_H2C_WR_ADDR_V1)\n#define BITS_H2C_WR_ADDR_V1                                                    \\\n\t(BIT_MASK_H2C_WR_ADDR_V1 << BIT_SHIFT_H2C_WR_ADDR_V1)\n#define BIT_CLEAR_H2C_WR_ADDR_V1(x) ((x) & (~BITS_H2C_WR_ADDR_V1))\n#define BIT_GET_H2C_WR_ADDR_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_H2C_WR_ADDR_V1) & BIT_MASK_H2C_WR_ADDR_V1)\n#define BIT_SET_H2C_WR_ADDR_V1(x, v)                                           \\\n\t(BIT_CLEAR_H2C_WR_ADDR_V1(x) | BIT_H2C_WR_ADDR_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_H2C_INFO\t\t\t\t(Offset 0x0254) */\n\n#define BIT_SHIFT_MDIO_PHY_ADDR 24\n#define BIT_MASK_MDIO_PHY_ADDR 0x1f\n#define BIT_MDIO_PHY_ADDR(x)                                                   \\\n\t(((x) & BIT_MASK_MDIO_PHY_ADDR) << BIT_SHIFT_MDIO_PHY_ADDR)\n#define BITS_MDIO_PHY_ADDR (BIT_MASK_MDIO_PHY_ADDR << BIT_SHIFT_MDIO_PHY_ADDR)\n#define BIT_CLEAR_MDIO_PHY_ADDR(x) ((x) & (~BITS_MDIO_PHY_ADDR))\n#define BIT_GET_MDIO_PHY_ADDR(x)                                               \\\n\t(((x) >> BIT_SHIFT_MDIO_PHY_ADDR) & BIT_MASK_MDIO_PHY_ADDR)\n#define BIT_SET_MDIO_PHY_ADDR(x, v)                                            \\\n\t(BIT_CLEAR_MDIO_PHY_ADDR(x) | BIT_MDIO_PHY_ADDR(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_H2C_INFO\t\t\t\t(Offset 0x0254) */\n\n#define BIT_SHIFT_VI_PUB_LIMIT 16\n#define BIT_MASK_VI_PUB_LIMIT 0xfff\n#define BIT_VI_PUB_LIMIT(x)                                                    \\\n\t(((x) & BIT_MASK_VI_PUB_LIMIT) << BIT_SHIFT_VI_PUB_LIMIT)\n#define BITS_VI_PUB_LIMIT (BIT_MASK_VI_PUB_LIMIT << BIT_SHIFT_VI_PUB_LIMIT)\n#define BIT_CLEAR_VI_PUB_LIMIT(x) ((x) & (~BITS_VI_PUB_LIMIT))\n#define BIT_GET_VI_PUB_LIMIT(x)                                                \\\n\t(((x) >> BIT_SHIFT_VI_PUB_LIMIT) & BIT_MASK_VI_PUB_LIMIT)\n#define BIT_SET_VI_PUB_LIMIT(x, v)                                             \\\n\t(BIT_CLEAR_VI_PUB_LIMIT(x) | BIT_VI_PUB_LIMIT(v))\n\n#define BIT_SHIFT_BK_PUB_LIMIT 16\n#define BIT_MASK_BK_PUB_LIMIT 0xfff\n#define BIT_BK_PUB_LIMIT(x)                                                    \\\n\t(((x) & BIT_MASK_BK_PUB_LIMIT) << BIT_SHIFT_BK_PUB_LIMIT)\n#define BITS_BK_PUB_LIMIT (BIT_MASK_BK_PUB_LIMIT << BIT_SHIFT_BK_PUB_LIMIT)\n#define BIT_CLEAR_BK_PUB_LIMIT(x) ((x) & (~BITS_BK_PUB_LIMIT))\n#define BIT_GET_BK_PUB_LIMIT(x)                                                \\\n\t(((x) >> BIT_SHIFT_BK_PUB_LIMIT) & BIT_MASK_BK_PUB_LIMIT)\n#define BIT_SET_BK_PUB_LIMIT(x, v)                                             \\\n\t(BIT_CLEAR_BK_PUB_LIMIT(x) | BIT_BK_PUB_LIMIT(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_H2C_INFO\t\t\t\t(Offset 0x0254) */\n\n#define BIT_EX2Q_EN_PUBLIC_LIMIT BIT(13)\n#define BIT_EX1Q_EN_PUBLIC_LIMIT BIT(12)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_H2C_INFO\t\t\t\t(Offset 0x0254) */\n\n#define BIT_EXQ_EN_PUBLIC_LIMIT BIT(11)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_H2C_INFO\t\t\t\t(Offset 0x0254) */\n\n#define BIT_EQ_EN_PUBLIC_LIMIT BIT(11)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_H2C_INFO\t\t\t\t(Offset 0x0254) */\n\n#define BIT_NPQ_EN_PUBLIC_LIMIT BIT(10)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_H2C_INFO\t\t\t\t(Offset 0x0254) */\n\n#define BIT_NQ_EN_PUBLIC_LIMIT BIT(10)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_H2C_INFO\t\t\t\t(Offset 0x0254) */\n\n#define BIT_LPQ_EN_PUBLIC_LIMIT BIT(9)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_H2C_INFO\t\t\t\t(Offset 0x0254) */\n\n#define BIT_LQ_EN_PUBLIC_LIMIT BIT(9)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_H2C_INFO\t\t\t\t(Offset 0x0254) */\n\n#define BIT_HPQ_EN_PUBLIC_LIMIT BIT(8)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_H2C_INFO\t\t\t\t(Offset 0x0254) */\n\n#define BIT_HQ_EN_PUBLIC_LIMIT BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_H2C_INFO\t\t\t\t(Offset 0x0254) */\n\n#define BIT_H2C_SPACE_VLD BIT(3)\n#define BIT_H2C_WR_ADDR_RST BIT(2)\n\n#define BIT_SHIFT_H2C_LEN_SEL 0\n#define BIT_MASK_H2C_LEN_SEL 0x3\n#define BIT_H2C_LEN_SEL(x)                                                     \\\n\t(((x) & BIT_MASK_H2C_LEN_SEL) << BIT_SHIFT_H2C_LEN_SEL)\n#define BITS_H2C_LEN_SEL (BIT_MASK_H2C_LEN_SEL << BIT_SHIFT_H2C_LEN_SEL)\n#define BIT_CLEAR_H2C_LEN_SEL(x) ((x) & (~BITS_H2C_LEN_SEL))\n#define BIT_GET_H2C_LEN_SEL(x)                                                 \\\n\t(((x) >> BIT_SHIFT_H2C_LEN_SEL) & BIT_MASK_H2C_LEN_SEL)\n#define BIT_SET_H2C_LEN_SEL(x, v)                                              \\\n\t(BIT_CLEAR_H2C_LEN_SEL(x) | BIT_H2C_LEN_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_H2C_INFO\t\t\t\t(Offset 0x0254) */\n\n#define BIT_SHIFT_VO_PUB_LIMIT 0\n#define BIT_MASK_VO_PUB_LIMIT 0xfff\n#define BIT_VO_PUB_LIMIT(x)                                                    \\\n\t(((x) & BIT_MASK_VO_PUB_LIMIT) << BIT_SHIFT_VO_PUB_LIMIT)\n#define BITS_VO_PUB_LIMIT (BIT_MASK_VO_PUB_LIMIT << BIT_SHIFT_VO_PUB_LIMIT)\n#define BIT_CLEAR_VO_PUB_LIMIT(x) ((x) & (~BITS_VO_PUB_LIMIT))\n#define BIT_GET_VO_PUB_LIMIT(x)                                                \\\n\t(((x) >> BIT_SHIFT_VO_PUB_LIMIT) & BIT_MASK_VO_PUB_LIMIT)\n#define BIT_SET_VO_PUB_LIMIT(x, v)                                             \\\n\t(BIT_CLEAR_VO_PUB_LIMIT(x) | BIT_VO_PUB_LIMIT(v))\n\n#define BIT_SHIFT_BE_PUB_LIMIT 0\n#define BIT_MASK_BE_PUB_LIMIT 0xfff\n#define BIT_BE_PUB_LIMIT(x)                                                    \\\n\t(((x) & BIT_MASK_BE_PUB_LIMIT) << BIT_SHIFT_BE_PUB_LIMIT)\n#define BITS_BE_PUB_LIMIT (BIT_MASK_BE_PUB_LIMIT << BIT_SHIFT_BE_PUB_LIMIT)\n#define BIT_CLEAR_BE_PUB_LIMIT(x) ((x) & (~BITS_BE_PUB_LIMIT))\n#define BIT_GET_BE_PUB_LIMIT(x)                                                \\\n\t(((x) >> BIT_SHIFT_BE_PUB_LIMIT) & BIT_MASK_BE_PUB_LIMIT)\n#define BIT_SET_BE_PUB_LIMIT(x, v)                                             \\\n\t(BIT_CLEAR_BE_PUB_LIMIT(x) | BIT_BE_PUB_LIMIT(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_FIFOPAGE_CTRL_5\t\t\t(Offset 0x0258) */\n\n#define BIT_SHIFT_NQ_PG_PUBLIC_LIMIT 16\n#define BIT_MASK_NQ_PG_PUBLIC_LIMIT 0xfff\n#define BIT_NQ_PG_PUBLIC_LIMIT(x)                                              \\\n\t(((x) & BIT_MASK_NQ_PG_PUBLIC_LIMIT) << BIT_SHIFT_NQ_PG_PUBLIC_LIMIT)\n#define BITS_NQ_PG_PUBLIC_LIMIT                                                \\\n\t(BIT_MASK_NQ_PG_PUBLIC_LIMIT << BIT_SHIFT_NQ_PG_PUBLIC_LIMIT)\n#define BIT_CLEAR_NQ_PG_PUBLIC_LIMIT(x) ((x) & (~BITS_NQ_PG_PUBLIC_LIMIT))\n#define BIT_GET_NQ_PG_PUBLIC_LIMIT(x)                                          \\\n\t(((x) >> BIT_SHIFT_NQ_PG_PUBLIC_LIMIT) & BIT_MASK_NQ_PG_PUBLIC_LIMIT)\n#define BIT_SET_NQ_PG_PUBLIC_LIMIT(x, v)                                       \\\n\t(BIT_CLEAR_NQ_PG_PUBLIC_LIMIT(x) | BIT_NQ_PG_PUBLIC_LIMIT(v))\n\n#define BIT_SHIFT_HQ_PG_PUBLIC_LIMIT 0\n#define BIT_MASK_HQ_PG_PUBLIC_LIMIT 0xfff\n#define BIT_HQ_PG_PUBLIC_LIMIT(x)                                              \\\n\t(((x) & BIT_MASK_HQ_PG_PUBLIC_LIMIT) << BIT_SHIFT_HQ_PG_PUBLIC_LIMIT)\n#define BITS_HQ_PG_PUBLIC_LIMIT                                                \\\n\t(BIT_MASK_HQ_PG_PUBLIC_LIMIT << BIT_SHIFT_HQ_PG_PUBLIC_LIMIT)\n#define BIT_CLEAR_HQ_PG_PUBLIC_LIMIT(x) ((x) & (~BITS_HQ_PG_PUBLIC_LIMIT))\n#define BIT_GET_HQ_PG_PUBLIC_LIMIT(x)                                          \\\n\t(((x) >> BIT_SHIFT_HQ_PG_PUBLIC_LIMIT) & BIT_MASK_HQ_PG_PUBLIC_LIMIT)\n#define BIT_SET_HQ_PG_PUBLIC_LIMIT(x, v)                                       \\\n\t(BIT_CLEAR_HQ_PG_PUBLIC_LIMIT(x) | BIT_HQ_PG_PUBLIC_LIMIT(v))\n\n/* 2 REG_FIFOPAGE_CTRL_3\t\t\t(Offset 0x025C) */\n\n#define BIT_SHIFT_EQ_PG_PUBLIC_LIMIT 16\n#define BIT_MASK_EQ_PG_PUBLIC_LIMIT 0xfff\n#define BIT_EQ_PG_PUBLIC_LIMIT(x)                                              \\\n\t(((x) & BIT_MASK_EQ_PG_PUBLIC_LIMIT) << BIT_SHIFT_EQ_PG_PUBLIC_LIMIT)\n#define BITS_EQ_PG_PUBLIC_LIMIT                                                \\\n\t(BIT_MASK_EQ_PG_PUBLIC_LIMIT << BIT_SHIFT_EQ_PG_PUBLIC_LIMIT)\n#define BIT_CLEAR_EQ_PG_PUBLIC_LIMIT(x) ((x) & (~BITS_EQ_PG_PUBLIC_LIMIT))\n#define BIT_GET_EQ_PG_PUBLIC_LIMIT(x)                                          \\\n\t(((x) >> BIT_SHIFT_EQ_PG_PUBLIC_LIMIT) & BIT_MASK_EQ_PG_PUBLIC_LIMIT)\n#define BIT_SET_EQ_PG_PUBLIC_LIMIT(x, v)                                       \\\n\t(BIT_CLEAR_EQ_PG_PUBLIC_LIMIT(x) | BIT_EQ_PG_PUBLIC_LIMIT(v))\n\n#define BIT_SHIFT_LQ_PG_PUBLIC_LIMIT 0\n#define BIT_MASK_LQ_PG_PUBLIC_LIMIT 0xfff\n#define BIT_LQ_PG_PUBLIC_LIMIT(x)                                              \\\n\t(((x) & BIT_MASK_LQ_PG_PUBLIC_LIMIT) << BIT_SHIFT_LQ_PG_PUBLIC_LIMIT)\n#define BITS_LQ_PG_PUBLIC_LIMIT                                                \\\n\t(BIT_MASK_LQ_PG_PUBLIC_LIMIT << BIT_SHIFT_LQ_PG_PUBLIC_LIMIT)\n#define BIT_CLEAR_LQ_PG_PUBLIC_LIMIT(x) ((x) & (~BITS_LQ_PG_PUBLIC_LIMIT))\n#define BIT_GET_LQ_PG_PUBLIC_LIMIT(x)                                          \\\n\t(((x) >> BIT_SHIFT_LQ_PG_PUBLIC_LIMIT) & BIT_MASK_LQ_PG_PUBLIC_LIMIT)\n#define BIT_SET_LQ_PG_PUBLIC_LIMIT(x, v)                                       \\\n\t(BIT_CLEAR_LQ_PG_PUBLIC_LIMIT(x) | BIT_LQ_PG_PUBLIC_LIMIT(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DMA_OQT_0\t\t\t\t(Offset 0x0260) */\n\n#define BIT_SHIFT_TX_OQT_12_FREE_SPACE 24\n#define BIT_MASK_TX_OQT_12_FREE_SPACE 0xff\n#define BIT_TX_OQT_12_FREE_SPACE(x)                                            \\\n\t(((x) & BIT_MASK_TX_OQT_12_FREE_SPACE)                                 \\\n\t << BIT_SHIFT_TX_OQT_12_FREE_SPACE)\n#define BITS_TX_OQT_12_FREE_SPACE                                              \\\n\t(BIT_MASK_TX_OQT_12_FREE_SPACE << BIT_SHIFT_TX_OQT_12_FREE_SPACE)\n#define BIT_CLEAR_TX_OQT_12_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_12_FREE_SPACE))\n#define BIT_GET_TX_OQT_12_FREE_SPACE(x)                                        \\\n\t(((x) >> BIT_SHIFT_TX_OQT_12_FREE_SPACE) &                             \\\n\t BIT_MASK_TX_OQT_12_FREE_SPACE)\n#define BIT_SET_TX_OQT_12_FREE_SPACE(x, v)                                     \\\n\t(BIT_CLEAR_TX_OQT_12_FREE_SPACE(x) | BIT_TX_OQT_12_FREE_SPACE(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TQPNT5\t\t\t\t(Offset 0x0260) */\n\n#define BIT_SHIFT_EX1Q_HIGH_TH_V1 16\n#define BIT_MASK_EX1Q_HIGH_TH_V1 0xfff\n#define BIT_EX1Q_HIGH_TH_V1(x)                                                 \\\n\t(((x) & BIT_MASK_EX1Q_HIGH_TH_V1) << BIT_SHIFT_EX1Q_HIGH_TH_V1)\n#define BITS_EX1Q_HIGH_TH_V1                                                   \\\n\t(BIT_MASK_EX1Q_HIGH_TH_V1 << BIT_SHIFT_EX1Q_HIGH_TH_V1)\n#define BIT_CLEAR_EX1Q_HIGH_TH_V1(x) ((x) & (~BITS_EX1Q_HIGH_TH_V1))\n#define BIT_GET_EX1Q_HIGH_TH_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_EX1Q_HIGH_TH_V1) & BIT_MASK_EX1Q_HIGH_TH_V1)\n#define BIT_SET_EX1Q_HIGH_TH_V1(x, v)                                          \\\n\t(BIT_CLEAR_EX1Q_HIGH_TH_V1(x) | BIT_EX1Q_HIGH_TH_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DMA_OQT_0\t\t\t\t(Offset 0x0260) */\n\n#define BIT_SHIFT_TX_OQT_8_11_FREE_SPACE 16\n#define BIT_MASK_TX_OQT_8_11_FREE_SPACE 0xff\n#define BIT_TX_OQT_8_11_FREE_SPACE(x)                                          \\\n\t(((x) & BIT_MASK_TX_OQT_8_11_FREE_SPACE)                               \\\n\t << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE)\n#define BITS_TX_OQT_8_11_FREE_SPACE                                            \\\n\t(BIT_MASK_TX_OQT_8_11_FREE_SPACE << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE)\n#define BIT_CLEAR_TX_OQT_8_11_FREE_SPACE(x)                                    \\\n\t((x) & (~BITS_TX_OQT_8_11_FREE_SPACE))\n#define BIT_GET_TX_OQT_8_11_FREE_SPACE(x)                                      \\\n\t(((x) >> BIT_SHIFT_TX_OQT_8_11_FREE_SPACE) &                           \\\n\t BIT_MASK_TX_OQT_8_11_FREE_SPACE)\n#define BIT_SET_TX_OQT_8_11_FREE_SPACE(x, v)                                   \\\n\t(BIT_CLEAR_TX_OQT_8_11_FREE_SPACE(x) | BIT_TX_OQT_8_11_FREE_SPACE(v))\n\n#define BIT_SHIFT_TX_OQT_16_FREE_SPACE 16\n#define BIT_MASK_TX_OQT_16_FREE_SPACE 0xff\n#define BIT_TX_OQT_16_FREE_SPACE(x)                                            \\\n\t(((x) & BIT_MASK_TX_OQT_16_FREE_SPACE)                                 \\\n\t << BIT_SHIFT_TX_OQT_16_FREE_SPACE)\n#define BITS_TX_OQT_16_FREE_SPACE                                              \\\n\t(BIT_MASK_TX_OQT_16_FREE_SPACE << BIT_SHIFT_TX_OQT_16_FREE_SPACE)\n#define BIT_CLEAR_TX_OQT_16_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_16_FREE_SPACE))\n#define BIT_GET_TX_OQT_16_FREE_SPACE(x)                                        \\\n\t(((x) >> BIT_SHIFT_TX_OQT_16_FREE_SPACE) &                             \\\n\t BIT_MASK_TX_OQT_16_FREE_SPACE)\n#define BIT_SET_TX_OQT_16_FREE_SPACE(x, v)                                     \\\n\t(BIT_CLEAR_TX_OQT_16_FREE_SPACE(x) | BIT_TX_OQT_16_FREE_SPACE(v))\n\n#define BIT_SHIFT_TX_OQT_4_7_FREE_SPACE 8\n#define BIT_MASK_TX_OQT_4_7_FREE_SPACE 0xff\n#define BIT_TX_OQT_4_7_FREE_SPACE(x)                                           \\\n\t(((x) & BIT_MASK_TX_OQT_4_7_FREE_SPACE)                                \\\n\t << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE)\n#define BITS_TX_OQT_4_7_FREE_SPACE                                             \\\n\t(BIT_MASK_TX_OQT_4_7_FREE_SPACE << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE)\n#define BIT_CLEAR_TX_OQT_4_7_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_4_7_FREE_SPACE))\n#define BIT_GET_TX_OQT_4_7_FREE_SPACE(x)                                       \\\n\t(((x) >> BIT_SHIFT_TX_OQT_4_7_FREE_SPACE) &                            \\\n\t BIT_MASK_TX_OQT_4_7_FREE_SPACE)\n#define BIT_SET_TX_OQT_4_7_FREE_SPACE(x, v)                                    \\\n\t(BIT_CLEAR_TX_OQT_4_7_FREE_SPACE(x) | BIT_TX_OQT_4_7_FREE_SPACE(v))\n\n#define BIT_SHIFT_TX_OQT_14_15_FREE_SPACE 8\n#define BIT_MASK_TX_OQT_14_15_FREE_SPACE 0xff\n#define BIT_TX_OQT_14_15_FREE_SPACE(x)                                         \\\n\t(((x) & BIT_MASK_TX_OQT_14_15_FREE_SPACE)                              \\\n\t << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE)\n#define BITS_TX_OQT_14_15_FREE_SPACE                                           \\\n\t(BIT_MASK_TX_OQT_14_15_FREE_SPACE << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE)\n#define BIT_CLEAR_TX_OQT_14_15_FREE_SPACE(x)                                   \\\n\t((x) & (~BITS_TX_OQT_14_15_FREE_SPACE))\n#define BIT_GET_TX_OQT_14_15_FREE_SPACE(x)                                     \\\n\t(((x) >> BIT_SHIFT_TX_OQT_14_15_FREE_SPACE) &                          \\\n\t BIT_MASK_TX_OQT_14_15_FREE_SPACE)\n#define BIT_SET_TX_OQT_14_15_FREE_SPACE(x, v)                                  \\\n\t(BIT_CLEAR_TX_OQT_14_15_FREE_SPACE(x) | BIT_TX_OQT_14_15_FREE_SPACE(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TQPNT5\t\t\t\t(Offset 0x0260) */\n\n#define BIT_SHIFT_EX1Q_LOW_TH_V1 0\n#define BIT_MASK_EX1Q_LOW_TH_V1 0xfff\n#define BIT_EX1Q_LOW_TH_V1(x)                                                  \\\n\t(((x) & BIT_MASK_EX1Q_LOW_TH_V1) << BIT_SHIFT_EX1Q_LOW_TH_V1)\n#define BITS_EX1Q_LOW_TH_V1                                                    \\\n\t(BIT_MASK_EX1Q_LOW_TH_V1 << BIT_SHIFT_EX1Q_LOW_TH_V1)\n#define BIT_CLEAR_EX1Q_LOW_TH_V1(x) ((x) & (~BITS_EX1Q_LOW_TH_V1))\n#define BIT_GET_EX1Q_LOW_TH_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_EX1Q_LOW_TH_V1) & BIT_MASK_EX1Q_LOW_TH_V1)\n#define BIT_SET_EX1Q_LOW_TH_V1(x, v)                                           \\\n\t(BIT_CLEAR_EX1Q_LOW_TH_V1(x) | BIT_EX1Q_LOW_TH_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DMA_OQT_0\t\t\t\t(Offset 0x0260) */\n\n#define BIT_SHIFT_TX_OQT_0_3_FREE_SPACE 0\n#define BIT_MASK_TX_OQT_0_3_FREE_SPACE 0xff\n#define BIT_TX_OQT_0_3_FREE_SPACE(x)                                           \\\n\t(((x) & BIT_MASK_TX_OQT_0_3_FREE_SPACE)                                \\\n\t << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE)\n#define BITS_TX_OQT_0_3_FREE_SPACE                                             \\\n\t(BIT_MASK_TX_OQT_0_3_FREE_SPACE << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE)\n#define BIT_CLEAR_TX_OQT_0_3_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_0_3_FREE_SPACE))\n#define BIT_GET_TX_OQT_0_3_FREE_SPACE(x)                                       \\\n\t(((x) >> BIT_SHIFT_TX_OQT_0_3_FREE_SPACE) &                            \\\n\t BIT_MASK_TX_OQT_0_3_FREE_SPACE)\n#define BIT_SET_TX_OQT_0_3_FREE_SPACE(x, v)                                    \\\n\t(BIT_CLEAR_TX_OQT_0_3_FREE_SPACE(x) | BIT_TX_OQT_0_3_FREE_SPACE(v))\n\n#define BIT_SHIFT_TX_OQT_13_FREE_SPACE 0\n#define BIT_MASK_TX_OQT_13_FREE_SPACE 0xff\n#define BIT_TX_OQT_13_FREE_SPACE(x)                                            \\\n\t(((x) & BIT_MASK_TX_OQT_13_FREE_SPACE)                                 \\\n\t << BIT_SHIFT_TX_OQT_13_FREE_SPACE)\n#define BITS_TX_OQT_13_FREE_SPACE                                              \\\n\t(BIT_MASK_TX_OQT_13_FREE_SPACE << BIT_SHIFT_TX_OQT_13_FREE_SPACE)\n#define BIT_CLEAR_TX_OQT_13_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_13_FREE_SPACE))\n#define BIT_GET_TX_OQT_13_FREE_SPACE(x)                                        \\\n\t(((x) >> BIT_SHIFT_TX_OQT_13_FREE_SPACE) &                             \\\n\t BIT_MASK_TX_OQT_13_FREE_SPACE)\n#define BIT_SET_TX_OQT_13_FREE_SPACE(x, v)                                     \\\n\t(BIT_CLEAR_TX_OQT_13_FREE_SPACE(x) | BIT_TX_OQT_13_FREE_SPACE(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TQPNT6\t\t\t\t(Offset 0x0264) */\n\n#define BIT_SHIFT_EX2Q_HIGH_TH_V1 16\n#define BIT_MASK_EX2Q_HIGH_TH_V1 0xfff\n#define BIT_EX2Q_HIGH_TH_V1(x)                                                 \\\n\t(((x) & BIT_MASK_EX2Q_HIGH_TH_V1) << BIT_SHIFT_EX2Q_HIGH_TH_V1)\n#define BITS_EX2Q_HIGH_TH_V1                                                   \\\n\t(BIT_MASK_EX2Q_HIGH_TH_V1 << BIT_SHIFT_EX2Q_HIGH_TH_V1)\n#define BIT_CLEAR_EX2Q_HIGH_TH_V1(x) ((x) & (~BITS_EX2Q_HIGH_TH_V1))\n#define BIT_GET_EX2Q_HIGH_TH_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_EX2Q_HIGH_TH_V1) & BIT_MASK_EX2Q_HIGH_TH_V1)\n#define BIT_SET_EX2Q_HIGH_TH_V1(x, v)                                          \\\n\t(BIT_CLEAR_EX2Q_HIGH_TH_V1(x) | BIT_EX2Q_HIGH_TH_V1(v))\n\n#define BIT_SHIFT_EX2Q_LOW_TH_V1 0\n#define BIT_MASK_EX2Q_LOW_TH_V1 0xfff\n#define BIT_EX2Q_LOW_TH_V1(x)                                                  \\\n\t(((x) & BIT_MASK_EX2Q_LOW_TH_V1) << BIT_SHIFT_EX2Q_LOW_TH_V1)\n#define BITS_EX2Q_LOW_TH_V1                                                    \\\n\t(BIT_MASK_EX2Q_LOW_TH_V1 << BIT_SHIFT_EX2Q_LOW_TH_V1)\n#define BIT_CLEAR_EX2Q_LOW_TH_V1(x) ((x) & (~BITS_EX2Q_LOW_TH_V1))\n#define BIT_GET_EX2Q_LOW_TH_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_EX2Q_LOW_TH_V1) & BIT_MASK_EX2Q_LOW_TH_V1)\n#define BIT_SET_EX2Q_LOW_TH_V1(x, v)                                           \\\n\t(BIT_CLEAR_EX2Q_LOW_TH_V1(x) | BIT_EX2Q_LOW_TH_V1(v))\n\n/* 2 REG_FIFOPAGE_INFO_6\t\t\t(Offset 0x0268) */\n\n#define BIT_SHIFT_EX1Q_AVAL_PG_V1 16\n#define BIT_MASK_EX1Q_AVAL_PG_V1 0xfff\n#define BIT_EX1Q_AVAL_PG_V1(x)                                                 \\\n\t(((x) & BIT_MASK_EX1Q_AVAL_PG_V1) << BIT_SHIFT_EX1Q_AVAL_PG_V1)\n#define BITS_EX1Q_AVAL_PG_V1                                                   \\\n\t(BIT_MASK_EX1Q_AVAL_PG_V1 << BIT_SHIFT_EX1Q_AVAL_PG_V1)\n#define BIT_CLEAR_EX1Q_AVAL_PG_V1(x) ((x) & (~BITS_EX1Q_AVAL_PG_V1))\n#define BIT_GET_EX1Q_AVAL_PG_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_EX1Q_AVAL_PG_V1) & BIT_MASK_EX1Q_AVAL_PG_V1)\n#define BIT_SET_EX1Q_AVAL_PG_V1(x, v)                                          \\\n\t(BIT_CLEAR_EX1Q_AVAL_PG_V1(x) | BIT_EX1Q_AVAL_PG_V1(v))\n\n#define BIT_SHIFT_EX1Q_V1 0\n#define BIT_MASK_EX1Q_V1 0xfff\n#define BIT_EX1Q_V1(x) (((x) & BIT_MASK_EX1Q_V1) << BIT_SHIFT_EX1Q_V1)\n#define BITS_EX1Q_V1 (BIT_MASK_EX1Q_V1 << BIT_SHIFT_EX1Q_V1)\n#define BIT_CLEAR_EX1Q_V1(x) ((x) & (~BITS_EX1Q_V1))\n#define BIT_GET_EX1Q_V1(x) (((x) >> BIT_SHIFT_EX1Q_V1) & BIT_MASK_EX1Q_V1)\n#define BIT_SET_EX1Q_V1(x, v) (BIT_CLEAR_EX1Q_V1(x) | BIT_EX1Q_V1(v))\n\n/* 2 REG_FIFOPAGE_INFO_7\t\t\t(Offset 0x026C) */\n\n#define BIT_SHIFT_EX2Q_AVAL_PG_V1 16\n#define BIT_MASK_EX2Q_AVAL_PG_V1 0xfff\n#define BIT_EX2Q_AVAL_PG_V1(x)                                                 \\\n\t(((x) & BIT_MASK_EX2Q_AVAL_PG_V1) << BIT_SHIFT_EX2Q_AVAL_PG_V1)\n#define BITS_EX2Q_AVAL_PG_V1                                                   \\\n\t(BIT_MASK_EX2Q_AVAL_PG_V1 << BIT_SHIFT_EX2Q_AVAL_PG_V1)\n#define BIT_CLEAR_EX2Q_AVAL_PG_V1(x) ((x) & (~BITS_EX2Q_AVAL_PG_V1))\n#define BIT_GET_EX2Q_AVAL_PG_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_EX2Q_AVAL_PG_V1) & BIT_MASK_EX2Q_AVAL_PG_V1)\n#define BIT_SET_EX2Q_AVAL_PG_V1(x, v)                                          \\\n\t(BIT_CLEAR_EX2Q_AVAL_PG_V1(x) | BIT_EX2Q_AVAL_PG_V1(v))\n\n#define BIT_SHIFT_EX2Q_V1 0\n#define BIT_MASK_EX2Q_V1 0xfff\n#define BIT_EX2Q_V1(x) (((x) & BIT_MASK_EX2Q_V1) << BIT_SHIFT_EX2Q_V1)\n#define BITS_EX2Q_V1 (BIT_MASK_EX2Q_V1 << BIT_SHIFT_EX2Q_V1)\n#define BIT_CLEAR_EX2Q_V1(x) ((x) & (~BITS_EX2Q_V1))\n#define BIT_GET_EX2Q_V1(x) (((x) >> BIT_SHIFT_EX2Q_V1) & BIT_MASK_EX2Q_V1)\n#define BIT_SET_EX2Q_V1(x, v) (BIT_CLEAR_EX2Q_V1(x) | BIT_EX2Q_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_FIFOPAGE_CTRL_4\t\t\t(Offset 0x0270) */\n\n#define BIT_SHIFT_EX1Q_PG_PUBLIC_LIMIT 16\n#define BIT_MASK_EX1Q_PG_PUBLIC_LIMIT 0xfff\n#define BIT_EX1Q_PG_PUBLIC_LIMIT(x)                                            \\\n\t(((x) & BIT_MASK_EX1Q_PG_PUBLIC_LIMIT)                                 \\\n\t << BIT_SHIFT_EX1Q_PG_PUBLIC_LIMIT)\n#define BITS_EX1Q_PG_PUBLIC_LIMIT                                              \\\n\t(BIT_MASK_EX1Q_PG_PUBLIC_LIMIT << BIT_SHIFT_EX1Q_PG_PUBLIC_LIMIT)\n#define BIT_CLEAR_EX1Q_PG_PUBLIC_LIMIT(x) ((x) & (~BITS_EX1Q_PG_PUBLIC_LIMIT))\n#define BIT_GET_EX1Q_PG_PUBLIC_LIMIT(x)                                        \\\n\t(((x) >> BIT_SHIFT_EX1Q_PG_PUBLIC_LIMIT) &                             \\\n\t BIT_MASK_EX1Q_PG_PUBLIC_LIMIT)\n#define BIT_SET_EX1Q_PG_PUBLIC_LIMIT(x, v)                                     \\\n\t(BIT_CLEAR_EX1Q_PG_PUBLIC_LIMIT(x) | BIT_EX1Q_PG_PUBLIC_LIMIT(v))\n\n#define BIT_SHIFT_EX2Q_PG_PUBLIC_LIMIT 0\n#define BIT_MASK_EX2Q_PG_PUBLIC_LIMIT 0xfff\n#define BIT_EX2Q_PG_PUBLIC_LIMIT(x)                                            \\\n\t(((x) & BIT_MASK_EX2Q_PG_PUBLIC_LIMIT)                                 \\\n\t << BIT_SHIFT_EX2Q_PG_PUBLIC_LIMIT)\n#define BITS_EX2Q_PG_PUBLIC_LIMIT                                              \\\n\t(BIT_MASK_EX2Q_PG_PUBLIC_LIMIT << BIT_SHIFT_EX2Q_PG_PUBLIC_LIMIT)\n#define BIT_CLEAR_EX2Q_PG_PUBLIC_LIMIT(x) ((x) & (~BITS_EX2Q_PG_PUBLIC_LIMIT))\n#define BIT_GET_EX2Q_PG_PUBLIC_LIMIT(x)                                        \\\n\t(((x) >> BIT_SHIFT_EX2Q_PG_PUBLIC_LIMIT) &                             \\\n\t BIT_MASK_EX2Q_PG_PUBLIC_LIMIT)\n#define BIT_SET_EX2Q_PG_PUBLIC_LIMIT(x, v)                                     \\\n\t(BIT_CLEAR_EX2Q_PG_PUBLIC_LIMIT(x) | BIT_EX2Q_PG_PUBLIC_LIMIT(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PGSUB_H\t\t\t\t(Offset 0x0270) */\n\n#define BIT_SHIFT_HPQ_PGSUB_CNT 0\n#define BIT_MASK_HPQ_PGSUB_CNT 0xffffffffL\n#define BIT_HPQ_PGSUB_CNT(x)                                                   \\\n\t(((x) & BIT_MASK_HPQ_PGSUB_CNT) << BIT_SHIFT_HPQ_PGSUB_CNT)\n#define BITS_HPQ_PGSUB_CNT (BIT_MASK_HPQ_PGSUB_CNT << BIT_SHIFT_HPQ_PGSUB_CNT)\n#define BIT_CLEAR_HPQ_PGSUB_CNT(x) ((x) & (~BITS_HPQ_PGSUB_CNT))\n#define BIT_GET_HPQ_PGSUB_CNT(x)                                               \\\n\t(((x) >> BIT_SHIFT_HPQ_PGSUB_CNT) & BIT_MASK_HPQ_PGSUB_CNT)\n#define BIT_SET_HPQ_PGSUB_CNT(x, v)                                            \\\n\t(BIT_CLEAR_HPQ_PGSUB_CNT(x) | BIT_HPQ_PGSUB_CNT(v))\n\n/* 2 REG_PGSUB_N\t\t\t\t(Offset 0x0274) */\n\n#define BIT_SHIFT_NPQ_PGSUB_CNT 0\n#define BIT_MASK_NPQ_PGSUB_CNT 0xffffffffL\n#define BIT_NPQ_PGSUB_CNT(x)                                                   \\\n\t(((x) & BIT_MASK_NPQ_PGSUB_CNT) << BIT_SHIFT_NPQ_PGSUB_CNT)\n#define BITS_NPQ_PGSUB_CNT (BIT_MASK_NPQ_PGSUB_CNT << BIT_SHIFT_NPQ_PGSUB_CNT)\n#define BIT_CLEAR_NPQ_PGSUB_CNT(x) ((x) & (~BITS_NPQ_PGSUB_CNT))\n#define BIT_GET_NPQ_PGSUB_CNT(x)                                               \\\n\t(((x) >> BIT_SHIFT_NPQ_PGSUB_CNT) & BIT_MASK_NPQ_PGSUB_CNT)\n#define BIT_SET_NPQ_PGSUB_CNT(x, v)                                            \\\n\t(BIT_CLEAR_NPQ_PGSUB_CNT(x) | BIT_NPQ_PGSUB_CNT(v))\n\n/* 2 REG_PGSUB_L\t\t\t\t(Offset 0x0278) */\n\n#define BIT_SHIFT_LPQ_PGSUB_CNT 0\n#define BIT_MASK_LPQ_PGSUB_CNT 0xffffffffL\n#define BIT_LPQ_PGSUB_CNT(x)                                                   \\\n\t(((x) & BIT_MASK_LPQ_PGSUB_CNT) << BIT_SHIFT_LPQ_PGSUB_CNT)\n#define BITS_LPQ_PGSUB_CNT (BIT_MASK_LPQ_PGSUB_CNT << BIT_SHIFT_LPQ_PGSUB_CNT)\n#define BIT_CLEAR_LPQ_PGSUB_CNT(x) ((x) & (~BITS_LPQ_PGSUB_CNT))\n#define BIT_GET_LPQ_PGSUB_CNT(x)                                               \\\n\t(((x) >> BIT_SHIFT_LPQ_PGSUB_CNT) & BIT_MASK_LPQ_PGSUB_CNT)\n#define BIT_SET_LPQ_PGSUB_CNT(x, v)                                            \\\n\t(BIT_CLEAR_LPQ_PGSUB_CNT(x) | BIT_LPQ_PGSUB_CNT(v))\n\n/* 2 REG_PGSUB_E\t\t\t\t(Offset 0x027C) */\n\n#define BIT_SHIFT_EPQ_PGSUB_CNT 0\n#define BIT_MASK_EPQ_PGSUB_CNT 0xffffffffL\n#define BIT_EPQ_PGSUB_CNT(x)                                                   \\\n\t(((x) & BIT_MASK_EPQ_PGSUB_CNT) << BIT_SHIFT_EPQ_PGSUB_CNT)\n#define BITS_EPQ_PGSUB_CNT (BIT_MASK_EPQ_PGSUB_CNT << BIT_SHIFT_EPQ_PGSUB_CNT)\n#define BIT_CLEAR_EPQ_PGSUB_CNT(x) ((x) & (~BITS_EPQ_PGSUB_CNT))\n#define BIT_GET_EPQ_PGSUB_CNT(x)                                               \\\n\t(((x) >> BIT_SHIFT_EPQ_PGSUB_CNT) & BIT_MASK_EPQ_PGSUB_CNT)\n#define BIT_SET_EPQ_PGSUB_CNT(x, v)                                            \\\n\t(BIT_CLEAR_EPQ_PGSUB_CNT(x) | BIT_EPQ_PGSUB_CNT(v))\n\n#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V2 0\n#define BIT_MASK_FWFF_PKT_STR_ADDR_V2 0x3fff\n#define BIT_FWFF_PKT_STR_ADDR_V2(x)                                            \\\n\t(((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V2)                                 \\\n\t << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2)\n#define BITS_FWFF_PKT_STR_ADDR_V2                                              \\\n\t(BIT_MASK_FWFF_PKT_STR_ADDR_V2 << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2)\n#define BIT_CLEAR_FWFF_PKT_STR_ADDR_V2(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR_V2))\n#define BIT_GET_FWFF_PKT_STR_ADDR_V2(x)                                        \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V2) &                             \\\n\t BIT_MASK_FWFF_PKT_STR_ADDR_V2)\n#define BIT_SET_FWFF_PKT_STR_ADDR_V2(x, v)                                     \\\n\t(BIT_CLEAR_FWFF_PKT_STR_ADDR_V2(x) | BIT_FWFF_PKT_STR_ADDR_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_USB_RXDMA_AGG_EN BIT(31)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_RXDMA_AGG_OLD_MOD_V1 BIT(31)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_DMA_STORE_MODE BIT(31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_DMA_STORE BIT(31)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_EN_FW_ADD BIT(30)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_RXAGG_TH_MODE BIT(29)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_EN_PRE_CALC BIT(29)\n#define BIT_RXAGG_SW_EN BIT(28)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_RXAGG_SW_TRIG BIT(27)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_SHIFT_BCNERR_CNT_OTHERS 24\n#define BIT_MASK_BCNERR_CNT_OTHERS 0xff\n#define BIT_BCNERR_CNT_OTHERS(x)                                               \\\n\t(((x) & BIT_MASK_BCNERR_CNT_OTHERS) << BIT_SHIFT_BCNERR_CNT_OTHERS)\n#define BITS_BCNERR_CNT_OTHERS                                                 \\\n\t(BIT_MASK_BCNERR_CNT_OTHERS << BIT_SHIFT_BCNERR_CNT_OTHERS)\n#define BIT_CLEAR_BCNERR_CNT_OTHERS(x) ((x) & (~BITS_BCNERR_CNT_OTHERS))\n#define BIT_GET_BCNERR_CNT_OTHERS(x)                                           \\\n\t(((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS) & BIT_MASK_BCNERR_CNT_OTHERS)\n#define BIT_SET_BCNERR_CNT_OTHERS(x, v)                                        \\\n\t(BIT_CLEAR_BCNERR_CNT_OTHERS(x) | BIT_BCNERR_CNT_OTHERS(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_SHIFT_RXDMA_AGG_OLD_MOD 24\n#define BIT_MASK_RXDMA_AGG_OLD_MOD 0xff\n#define BIT_RXDMA_AGG_OLD_MOD(x)                                               \\\n\t(((x) & BIT_MASK_RXDMA_AGG_OLD_MOD) << BIT_SHIFT_RXDMA_AGG_OLD_MOD)\n#define BITS_RXDMA_AGG_OLD_MOD                                                 \\\n\t(BIT_MASK_RXDMA_AGG_OLD_MOD << BIT_SHIFT_RXDMA_AGG_OLD_MOD)\n#define BIT_CLEAR_RXDMA_AGG_OLD_MOD(x) ((x) & (~BITS_RXDMA_AGG_OLD_MOD))\n#define BIT_GET_RXDMA_AGG_OLD_MOD(x)                                           \\\n\t(((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD) & BIT_MASK_RXDMA_AGG_OLD_MOD)\n#define BIT_SET_RXDMA_AGG_OLD_MOD(x, v)                                        \\\n\t(BIT_CLEAR_RXDMA_AGG_OLD_MOD(x) | BIT_RXDMA_AGG_OLD_MOD(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_SHIFT_PKT_NUM_WOL 16\n#define BIT_MASK_PKT_NUM_WOL 0xff\n#define BIT_PKT_NUM_WOL(x)                                                     \\\n\t(((x) & BIT_MASK_PKT_NUM_WOL) << BIT_SHIFT_PKT_NUM_WOL)\n#define BITS_PKT_NUM_WOL (BIT_MASK_PKT_NUM_WOL << BIT_SHIFT_PKT_NUM_WOL)\n#define BIT_CLEAR_PKT_NUM_WOL(x) ((x) & (~BITS_PKT_NUM_WOL))\n#define BIT_GET_PKT_NUM_WOL(x)                                                 \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_WOL) & BIT_MASK_PKT_NUM_WOL)\n#define BIT_SET_PKT_NUM_WOL(x, v)                                              \\\n\t(BIT_CLEAR_PKT_NUM_WOL(x) | BIT_PKT_NUM_WOL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_SHIFT_RXBCN_TIMER 16\n#define BIT_MASK_RXBCN_TIMER 0xffff\n#define BIT_RXBCN_TIMER(x)                                                     \\\n\t(((x) & BIT_MASK_RXBCN_TIMER) << BIT_SHIFT_RXBCN_TIMER)\n#define BITS_RXBCN_TIMER (BIT_MASK_RXBCN_TIMER << BIT_SHIFT_RXBCN_TIMER)\n#define BIT_CLEAR_RXBCN_TIMER(x) ((x) & (~BITS_RXBCN_TIMER))\n#define BIT_GET_RXBCN_TIMER(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RXBCN_TIMER) & BIT_MASK_RXBCN_TIMER)\n#define BIT_SET_RXBCN_TIMER(x, v)                                              \\\n\t(BIT_CLEAR_RXBCN_TIMER(x) | BIT_RXBCN_TIMER(v))\n\n#define BIT_SHIFT_BCNERR_CNT_INVALID 16\n#define BIT_MASK_BCNERR_CNT_INVALID 0xff\n#define BIT_BCNERR_CNT_INVALID(x)                                              \\\n\t(((x) & BIT_MASK_BCNERR_CNT_INVALID) << BIT_SHIFT_BCNERR_CNT_INVALID)\n#define BITS_BCNERR_CNT_INVALID                                                \\\n\t(BIT_MASK_BCNERR_CNT_INVALID << BIT_SHIFT_BCNERR_CNT_INVALID)\n#define BIT_CLEAR_BCNERR_CNT_INVALID(x) ((x) & (~BITS_BCNERR_CNT_INVALID))\n#define BIT_GET_BCNERR_CNT_INVALID(x)                                          \\\n\t(((x) >> BIT_SHIFT_BCNERR_CNT_INVALID) & BIT_MASK_BCNERR_CNT_INVALID)\n#define BIT_SET_BCNERR_CNT_INVALID(x, v)                                       \\\n\t(BIT_CLEAR_BCNERR_CNT_INVALID(x) | BIT_BCNERR_CNT_INVALID(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_SHIFT_DMA_AGG_TO_V1 8\n#define BIT_MASK_DMA_AGG_TO_V1 0xff\n#define BIT_DMA_AGG_TO_V1(x)                                                   \\\n\t(((x) & BIT_MASK_DMA_AGG_TO_V1) << BIT_SHIFT_DMA_AGG_TO_V1)\n#define BITS_DMA_AGG_TO_V1 (BIT_MASK_DMA_AGG_TO_V1 << BIT_SHIFT_DMA_AGG_TO_V1)\n#define BIT_CLEAR_DMA_AGG_TO_V1(x) ((x) & (~BITS_DMA_AGG_TO_V1))\n#define BIT_GET_DMA_AGG_TO_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_DMA_AGG_TO_V1) & BIT_MASK_DMA_AGG_TO_V1)\n#define BIT_SET_DMA_AGG_TO_V1(x, v)                                            \\\n\t(BIT_CLEAR_DMA_AGG_TO_V1(x) | BIT_DMA_AGG_TO_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_SHIFT_BCNERR_CNT_MAC 8\n#define BIT_MASK_BCNERR_CNT_MAC 0xff\n#define BIT_BCNERR_CNT_MAC(x)                                                  \\\n\t(((x) & BIT_MASK_BCNERR_CNT_MAC) << BIT_SHIFT_BCNERR_CNT_MAC)\n#define BITS_BCNERR_CNT_MAC                                                    \\\n\t(BIT_MASK_BCNERR_CNT_MAC << BIT_SHIFT_BCNERR_CNT_MAC)\n#define BIT_CLEAR_BCNERR_CNT_MAC(x) ((x) & (~BITS_BCNERR_CNT_MAC))\n#define BIT_GET_BCNERR_CNT_MAC(x)                                              \\\n\t(((x) >> BIT_SHIFT_BCNERR_CNT_MAC) & BIT_MASK_BCNERR_CNT_MAC)\n#define BIT_SET_BCNERR_CNT_MAC(x, v)                                           \\\n\t(BIT_CLEAR_BCNERR_CNT_MAC(x) | BIT_BCNERR_CNT_MAC(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_SHIFT_DMA_AGG_TO 8\n#define BIT_MASK_DMA_AGG_TO 0xf\n#define BIT_DMA_AGG_TO(x) (((x) & BIT_MASK_DMA_AGG_TO) << BIT_SHIFT_DMA_AGG_TO)\n#define BITS_DMA_AGG_TO (BIT_MASK_DMA_AGG_TO << BIT_SHIFT_DMA_AGG_TO)\n#define BIT_CLEAR_DMA_AGG_TO(x) ((x) & (~BITS_DMA_AGG_TO))\n#define BIT_GET_DMA_AGG_TO(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DMA_AGG_TO) & BIT_MASK_DMA_AGG_TO)\n#define BIT_SET_DMA_AGG_TO(x, v) (BIT_CLEAR_DMA_AGG_TO(x) | BIT_DMA_AGG_TO(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1 0\n#define BIT_MASK_RXDMA_AGG_PG_TH_V1 0xf\n#define BIT_RXDMA_AGG_PG_TH_V1(x)                                              \\\n\t(((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1)\n#define BITS_RXDMA_AGG_PG_TH_V1                                                \\\n\t(BIT_MASK_RXDMA_AGG_PG_TH_V1 << BIT_SHIFT_RXDMA_AGG_PG_TH_V1)\n#define BIT_CLEAR_RXDMA_AGG_PG_TH_V1(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_V1))\n#define BIT_GET_RXDMA_AGG_PG_TH_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1) & BIT_MASK_RXDMA_AGG_PG_TH_V1)\n#define BIT_SET_RXDMA_AGG_PG_TH_V1(x, v)                                       \\\n\t(BIT_CLEAR_RXDMA_AGG_PG_TH_V1(x) | BIT_RXDMA_AGG_PG_TH_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_SHIFT_RXDMA_AGG_PG_TH 0\n#define BIT_MASK_RXDMA_AGG_PG_TH 0xff\n#define BIT_RXDMA_AGG_PG_TH(x)                                                 \\\n\t(((x) & BIT_MASK_RXDMA_AGG_PG_TH) << BIT_SHIFT_RXDMA_AGG_PG_TH)\n#define BITS_RXDMA_AGG_PG_TH                                                   \\\n\t(BIT_MASK_RXDMA_AGG_PG_TH << BIT_SHIFT_RXDMA_AGG_PG_TH)\n#define BIT_CLEAR_RXDMA_AGG_PG_TH(x) ((x) & (~BITS_RXDMA_AGG_PG_TH))\n#define BIT_GET_RXDMA_AGG_PG_TH(x)                                             \\\n\t(((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH) & BIT_MASK_RXDMA_AGG_PG_TH)\n#define BIT_SET_RXDMA_AGG_PG_TH(x, v)                                          \\\n\t(BIT_CLEAR_RXDMA_AGG_PG_TH(x) | BIT_RXDMA_AGG_PG_TH(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_SHIFT_QINFO_INDEX 0\n#define BIT_MASK_QINFO_INDEX 0x1f\n#define BIT_QINFO_INDEX(x)                                                     \\\n\t(((x) & BIT_MASK_QINFO_INDEX) << BIT_SHIFT_QINFO_INDEX)\n#define BITS_QINFO_INDEX (BIT_MASK_QINFO_INDEX << BIT_SHIFT_QINFO_INDEX)\n#define BIT_CLEAR_QINFO_INDEX(x) ((x) & (~BITS_QINFO_INDEX))\n#define BIT_GET_QINFO_INDEX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_QINFO_INDEX) & BIT_MASK_QINFO_INDEX)\n#define BIT_SET_QINFO_INDEX(x, v)                                              \\\n\t(BIT_CLEAR_QINFO_INDEX(x) | BIT_QINFO_INDEX(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_SHIFT_BCNERR_CNT_CCA 0\n#define BIT_MASK_BCNERR_CNT_CCA 0xff\n#define BIT_BCNERR_CNT_CCA(x)                                                  \\\n\t(((x) & BIT_MASK_BCNERR_CNT_CCA) << BIT_SHIFT_BCNERR_CNT_CCA)\n#define BITS_BCNERR_CNT_CCA                                                    \\\n\t(BIT_MASK_BCNERR_CNT_CCA << BIT_SHIFT_BCNERR_CNT_CCA)\n#define BIT_CLEAR_BCNERR_CNT_CCA(x) ((x) & (~BITS_BCNERR_CNT_CCA))\n#define BIT_GET_BCNERR_CNT_CCA(x)                                              \\\n\t(((x) >> BIT_SHIFT_BCNERR_CNT_CCA) & BIT_MASK_BCNERR_CNT_CCA)\n#define BIT_SET_BCNERR_CNT_CCA(x, v)                                           \\\n\t(BIT_CLEAR_BCNERR_CNT_CCA(x) | BIT_BCNERR_CNT_CCA(v))\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RXDMA_AGG_PG_TH\t\t\t(Offset 0x0280) */\n\n#define BIT_SHIFT_RXDMA_AGG_PG_TH_V2 0\n#define BIT_MASK_RXDMA_AGG_PG_TH_V2 0xff\n#define BIT_RXDMA_AGG_PG_TH_V2(x)                                              \\\n\t(((x) & BIT_MASK_RXDMA_AGG_PG_TH_V2) << BIT_SHIFT_RXDMA_AGG_PG_TH_V2)\n#define BITS_RXDMA_AGG_PG_TH_V2                                                \\\n\t(BIT_MASK_RXDMA_AGG_PG_TH_V2 << BIT_SHIFT_RXDMA_AGG_PG_TH_V2)\n#define BIT_CLEAR_RXDMA_AGG_PG_TH_V2(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_V2))\n#define BIT_GET_RXDMA_AGG_PG_TH_V2(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V2) & BIT_MASK_RXDMA_AGG_PG_TH_V2)\n#define BIT_SET_RXDMA_AGG_PG_TH_V2(x, v)                                       \\\n\t(BIT_CLEAR_RXDMA_AGG_PG_TH_V2(x) | BIT_RXDMA_AGG_PG_TH_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXPKT_NUM\t\t\t\t(Offset 0x0284) */\n\n#define BIT_SHIFT_RXPKT_NUM 24\n#define BIT_MASK_RXPKT_NUM 0xff\n#define BIT_RXPKT_NUM(x) (((x) & BIT_MASK_RXPKT_NUM) << BIT_SHIFT_RXPKT_NUM)\n#define BITS_RXPKT_NUM (BIT_MASK_RXPKT_NUM << BIT_SHIFT_RXPKT_NUM)\n#define BIT_CLEAR_RXPKT_NUM(x) ((x) & (~BITS_RXPKT_NUM))\n#define BIT_GET_RXPKT_NUM(x) (((x) >> BIT_SHIFT_RXPKT_NUM) & BIT_MASK_RXPKT_NUM)\n#define BIT_SET_RXPKT_NUM(x, v) (BIT_CLEAR_RXPKT_NUM(x) | BIT_RXPKT_NUM(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_RXPKT_NUM\t\t\t\t(Offset 0x0284) */\n\n#define BIT_STOP_RXDMA BIT(20)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXPKT_NUM\t\t\t\t(Offset 0x0284) */\n\n#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16 20\n#define BIT_MASK_FW_UPD_RDPTR19_TO_16 0xf\n#define BIT_FW_UPD_RDPTR19_TO_16(x)                                            \\\n\t(((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16)                                 \\\n\t << BIT_SHIFT_FW_UPD_RDPTR19_TO_16)\n#define BITS_FW_UPD_RDPTR19_TO_16                                              \\\n\t(BIT_MASK_FW_UPD_RDPTR19_TO_16 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16)\n#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16(x) ((x) & (~BITS_FW_UPD_RDPTR19_TO_16))\n#define BIT_GET_FW_UPD_RDPTR19_TO_16(x)                                        \\\n\t(((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16) &                             \\\n\t BIT_MASK_FW_UPD_RDPTR19_TO_16)\n#define BIT_SET_FW_UPD_RDPTR19_TO_16(x, v)                                     \\\n\t(BIT_CLEAR_FW_UPD_RDPTR19_TO_16(x) | BIT_FW_UPD_RDPTR19_TO_16(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXPKT_NUM\t\t\t\t(Offset 0x0284) */\n\n#define BIT_RXDMA_REQ BIT(19)\n#define BIT_RW_RELEASE_EN BIT(18)\n#define BIT_RXDMA_IDLE BIT(17)\n#define BIT_RXPKT_RELEASE_POLL BIT(16)\n\n#define BIT_SHIFT_FW_UPD_RDPTR 0\n#define BIT_MASK_FW_UPD_RDPTR 0xffff\n#define BIT_FW_UPD_RDPTR(x)                                                    \\\n\t(((x) & BIT_MASK_FW_UPD_RDPTR) << BIT_SHIFT_FW_UPD_RDPTR)\n#define BITS_FW_UPD_RDPTR (BIT_MASK_FW_UPD_RDPTR << BIT_SHIFT_FW_UPD_RDPTR)\n#define BIT_CLEAR_FW_UPD_RDPTR(x) ((x) & (~BITS_FW_UPD_RDPTR))\n#define BIT_GET_FW_UPD_RDPTR(x)                                                \\\n\t(((x) >> BIT_SHIFT_FW_UPD_RDPTR) & BIT_MASK_FW_UPD_RDPTR)\n#define BIT_SET_FW_UPD_RDPTR(x, v)                                             \\\n\t(BIT_CLEAR_FW_UPD_RDPTR(x) | BIT_FW_UPD_RDPTR(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_RXDMA_STATUS\t\t\t(Offset 0x0288) */\n\n#define BIT_FC2H_PKT_OVERFLOW BIT(8)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RXDMA_STATUS\t\t\t(Offset 0x0288) */\n\n#define BIT_FC2H_PKT_OVF BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXDMA_STATUS\t\t\t(Offset 0x0288) */\n\n#define BIT_C2H_PKT_OVF BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXDMA_STATUS\t\t\t(Offset 0x0288) */\n\n#define BIT_AGG_CFG_ISSUE BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXDMA_STATUS\t\t\t(Offset 0x0288) */\n\n#define BIT_AGG_CONFGI_ISSUE BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXDMA_STATUS\t\t\t(Offset 0x0288) */\n\n#define BIT_FW_POLL_ISSUE BIT(5)\n#define BIT_RX_DATA_UDN BIT(4)\n#define BIT_RX_SFF_UDN BIT(3)\n#define BIT_RX_SFF_OVF BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXDMA_STATUS\t\t\t(Offset 0x0288) */\n\n#define BIT_USB_REQ_LEN_OVF BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXDMA_STATUS\t\t\t(Offset 0x0288) */\n\n#define BIT_RXPKT_OVF BIT(0)\n\n/* 2 REG_RXDMA_DPR\t\t\t\t(Offset 0x028C) */\n\n#define BIT_SHIFT_RDE_DEBUG 0\n#define BIT_MASK_RDE_DEBUG 0xffffffffL\n#define BIT_RDE_DEBUG(x) (((x) & BIT_MASK_RDE_DEBUG) << BIT_SHIFT_RDE_DEBUG)\n#define BITS_RDE_DEBUG (BIT_MASK_RDE_DEBUG << BIT_SHIFT_RDE_DEBUG)\n#define BIT_CLEAR_RDE_DEBUG(x) ((x) & (~BITS_RDE_DEBUG))\n#define BIT_GET_RDE_DEBUG(x) (((x) >> BIT_SHIFT_RDE_DEBUG) & BIT_MASK_RDE_DEBUG)\n#define BIT_SET_RDE_DEBUG(x, v) (BIT_CLEAR_RDE_DEBUG(x) | BIT_RDE_DEBUG(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXDMA_MODE\t\t\t\t(Offset 0x0290) */\n\n#define BIT_SHIFT_PKTNUM_TH_V2 24\n#define BIT_MASK_PKTNUM_TH_V2 0x1f\n#define BIT_PKTNUM_TH_V2(x)                                                    \\\n\t(((x) & BIT_MASK_PKTNUM_TH_V2) << BIT_SHIFT_PKTNUM_TH_V2)\n#define BITS_PKTNUM_TH_V2 (BIT_MASK_PKTNUM_TH_V2 << BIT_SHIFT_PKTNUM_TH_V2)\n#define BIT_CLEAR_PKTNUM_TH_V2(x) ((x) & (~BITS_PKTNUM_TH_V2))\n#define BIT_GET_PKTNUM_TH_V2(x)                                                \\\n\t(((x) >> BIT_SHIFT_PKTNUM_TH_V2) & BIT_MASK_PKTNUM_TH_V2)\n#define BIT_SET_PKTNUM_TH_V2(x, v)                                             \\\n\t(BIT_CLEAR_PKTNUM_TH_V2(x) | BIT_PKTNUM_TH_V2(v))\n\n#define BIT_TXBA_BREAK_USBAGG BIT(23)\n\n#define BIT_SHIFT_PKTLEN_PARA 16\n#define BIT_MASK_PKTLEN_PARA 0x7\n#define BIT_PKTLEN_PARA(x)                                                     \\\n\t(((x) & BIT_MASK_PKTLEN_PARA) << BIT_SHIFT_PKTLEN_PARA)\n#define BITS_PKTLEN_PARA (BIT_MASK_PKTLEN_PARA << BIT_SHIFT_PKTLEN_PARA)\n#define BIT_CLEAR_PKTLEN_PARA(x) ((x) & (~BITS_PKTLEN_PARA))\n#define BIT_GET_PKTLEN_PARA(x)                                                 \\\n\t(((x) >> BIT_SHIFT_PKTLEN_PARA) & BIT_MASK_PKTLEN_PARA)\n#define BIT_SET_PKTLEN_PARA(x, v)                                              \\\n\t(BIT_CLEAR_PKTLEN_PARA(x) | BIT_PKTLEN_PARA(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RXDMA_MODE\t\t\t\t(Offset 0x0290) */\n\n#define BIT_EN_SDIO_FAIL BIT(9)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RXDMA_MODE\t\t\t\t(Offset 0x0290) */\n\n#define BIT_GRAYCODE_SYNC_WITH_BIN BIT(8)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RXDMA_MODE\t\t\t\t(Offset 0x0290) */\n\n#define BIT_RXDMA_DBD_SEL BIT(7)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXDMA_MODE\t\t\t\t(Offset 0x0290) */\n\n#define BIT_RX_DBG_SEL BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXDMA_MODE\t\t\t\t(Offset 0x0290) */\n\n#define BIT_EN_SPD BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXDMA_MODE\t\t\t\t(Offset 0x0290) */\n\n#define BIT_SHIFT_BURST_SIZE 4\n#define BIT_MASK_BURST_SIZE 0x3\n#define BIT_BURST_SIZE(x) (((x) & BIT_MASK_BURST_SIZE) << BIT_SHIFT_BURST_SIZE)\n#define BITS_BURST_SIZE (BIT_MASK_BURST_SIZE << BIT_SHIFT_BURST_SIZE)\n#define BIT_CLEAR_BURST_SIZE(x) ((x) & (~BITS_BURST_SIZE))\n#define BIT_GET_BURST_SIZE(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BURST_SIZE) & BIT_MASK_BURST_SIZE)\n#define BIT_SET_BURST_SIZE(x, v) (BIT_CLEAR_BURST_SIZE(x) | BIT_BURST_SIZE(v))\n\n#define BIT_SHIFT_BURST_CNT 2\n#define BIT_MASK_BURST_CNT 0x3\n#define BIT_BURST_CNT(x) (((x) & BIT_MASK_BURST_CNT) << BIT_SHIFT_BURST_CNT)\n#define BITS_BURST_CNT (BIT_MASK_BURST_CNT << BIT_SHIFT_BURST_CNT)\n#define BIT_CLEAR_BURST_CNT(x) ((x) & (~BITS_BURST_CNT))\n#define BIT_GET_BURST_CNT(x) (((x) >> BIT_SHIFT_BURST_CNT) & BIT_MASK_BURST_CNT)\n#define BIT_SET_BURST_CNT(x, v) (BIT_CLEAR_BURST_CNT(x) | BIT_BURST_CNT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXDMA_MODE\t\t\t\t(Offset 0x0290) */\n\n#define BIT_DAM_MODE BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXDMA_MODE\t\t\t\t(Offset 0x0290) */\n\n#define BIT_DMA_MODE BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_C2H_PKT\t\t\t\t(Offset 0x0294) */\n\n#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19 24\n#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19 0xf\n#define BIT_R_C2H_STR_ADDR_16_TO_19(x)                                         \\\n\t(((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19)                              \\\n\t << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19)\n#define BITS_R_C2H_STR_ADDR_16_TO_19                                           \\\n\t(BIT_MASK_R_C2H_STR_ADDR_16_TO_19 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19)\n#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19(x)                                   \\\n\t((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19))\n#define BIT_GET_R_C2H_STR_ADDR_16_TO_19(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) &                          \\\n\t BIT_MASK_R_C2H_STR_ADDR_16_TO_19)\n#define BIT_SET_R_C2H_STR_ADDR_16_TO_19(x, v)                                  \\\n\t(BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19(x) | BIT_R_C2H_STR_ADDR_16_TO_19(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_C2H_PKT\t\t\t\t(Offset 0x0294) */\n\n#define BIT_R_C2H_PKT_REQ BIT(16)\n\n#define BIT_SHIFT_R_C2H_STR_ADDR 0\n#define BIT_MASK_R_C2H_STR_ADDR 0xffff\n#define BIT_R_C2H_STR_ADDR(x)                                                  \\\n\t(((x) & BIT_MASK_R_C2H_STR_ADDR) << BIT_SHIFT_R_C2H_STR_ADDR)\n#define BITS_R_C2H_STR_ADDR                                                    \\\n\t(BIT_MASK_R_C2H_STR_ADDR << BIT_SHIFT_R_C2H_STR_ADDR)\n#define BIT_CLEAR_R_C2H_STR_ADDR(x) ((x) & (~BITS_R_C2H_STR_ADDR))\n#define BIT_GET_R_C2H_STR_ADDR(x)                                              \\\n\t(((x) >> BIT_SHIFT_R_C2H_STR_ADDR) & BIT_MASK_R_C2H_STR_ADDR)\n#define BIT_SET_R_C2H_STR_ADDR(x, v)                                           \\\n\t(BIT_CLEAR_R_C2H_STR_ADDR(x) | BIT_R_C2H_STR_ADDR(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWFF_C2H\t\t\t\t(Offset 0x0298) */\n\n#define BIT_SHIFT_C2H_DMA_ADDR 0\n#define BIT_MASK_C2H_DMA_ADDR 0x3ffff\n#define BIT_C2H_DMA_ADDR(x)                                                    \\\n\t(((x) & BIT_MASK_C2H_DMA_ADDR) << BIT_SHIFT_C2H_DMA_ADDR)\n#define BITS_C2H_DMA_ADDR (BIT_MASK_C2H_DMA_ADDR << BIT_SHIFT_C2H_DMA_ADDR)\n#define BIT_CLEAR_C2H_DMA_ADDR(x) ((x) & (~BITS_C2H_DMA_ADDR))\n#define BIT_GET_C2H_DMA_ADDR(x)                                                \\\n\t(((x) >> BIT_SHIFT_C2H_DMA_ADDR) & BIT_MASK_C2H_DMA_ADDR)\n#define BIT_SET_C2H_DMA_ADDR(x, v)                                             \\\n\t(BIT_CLEAR_C2H_DMA_ADDR(x) | BIT_C2H_DMA_ADDR(v))\n\n/* 2 REG_FWFF_CTRL\t\t\t\t(Offset 0x029C) */\n\n#define BIT_FWFF_DMAPKT_REQ BIT(31)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWFF_CTRL\t\t\t\t(Offset 0x029C) */\n\n#define BIT_SHIFT_FWFF_DMA_PKT_NUM 16\n#define BIT_MASK_FWFF_DMA_PKT_NUM 0xff\n#define BIT_FWFF_DMA_PKT_NUM(x)                                                \\\n\t(((x) & BIT_MASK_FWFF_DMA_PKT_NUM) << BIT_SHIFT_FWFF_DMA_PKT_NUM)\n#define BITS_FWFF_DMA_PKT_NUM                                                  \\\n\t(BIT_MASK_FWFF_DMA_PKT_NUM << BIT_SHIFT_FWFF_DMA_PKT_NUM)\n#define BIT_CLEAR_FWFF_DMA_PKT_NUM(x) ((x) & (~BITS_FWFF_DMA_PKT_NUM))\n#define BIT_GET_FWFF_DMA_PKT_NUM(x)                                            \\\n\t(((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM) & BIT_MASK_FWFF_DMA_PKT_NUM)\n#define BIT_SET_FWFF_DMA_PKT_NUM(x, v)                                         \\\n\t(BIT_CLEAR_FWFF_DMA_PKT_NUM(x) | BIT_FWFF_DMA_PKT_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FWFF_CTRL\t\t\t\t(Offset 0x029C) */\n\n#define BIT_SHIFT_FWFF_DMA_PKT_NUM_V1 16\n#define BIT_MASK_FWFF_DMA_PKT_NUM_V1 0x7fff\n#define BIT_FWFF_DMA_PKT_NUM_V1(x)                                             \\\n\t(((x) & BIT_MASK_FWFF_DMA_PKT_NUM_V1) << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1)\n#define BITS_FWFF_DMA_PKT_NUM_V1                                               \\\n\t(BIT_MASK_FWFF_DMA_PKT_NUM_V1 << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1)\n#define BIT_CLEAR_FWFF_DMA_PKT_NUM_V1(x) ((x) & (~BITS_FWFF_DMA_PKT_NUM_V1))\n#define BIT_GET_FWFF_DMA_PKT_NUM_V1(x)                                         \\\n\t(((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_V1) & BIT_MASK_FWFF_DMA_PKT_NUM_V1)\n#define BIT_SET_FWFF_DMA_PKT_NUM_V1(x, v)                                      \\\n\t(BIT_CLEAR_FWFF_DMA_PKT_NUM_V1(x) | BIT_FWFF_DMA_PKT_NUM_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWFF_CTRL\t\t\t\t(Offset 0x029C) */\n\n#define BIT_SHIFT_FWFF_STR_ADDR 0\n#define BIT_MASK_FWFF_STR_ADDR 0xffff\n#define BIT_FWFF_STR_ADDR(x)                                                   \\\n\t(((x) & BIT_MASK_FWFF_STR_ADDR) << BIT_SHIFT_FWFF_STR_ADDR)\n#define BITS_FWFF_STR_ADDR (BIT_MASK_FWFF_STR_ADDR << BIT_SHIFT_FWFF_STR_ADDR)\n#define BIT_CLEAR_FWFF_STR_ADDR(x) ((x) & (~BITS_FWFF_STR_ADDR))\n#define BIT_GET_FWFF_STR_ADDR(x)                                               \\\n\t(((x) >> BIT_SHIFT_FWFF_STR_ADDR) & BIT_MASK_FWFF_STR_ADDR)\n#define BIT_SET_FWFF_STR_ADDR(x, v)                                            \\\n\t(BIT_CLEAR_FWFF_STR_ADDR(x) | BIT_FWFF_STR_ADDR(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWFF_PKT_INFO\t\t\t(Offset 0x02A0) */\n\n#define BIT_SHIFT_FWFF_PKT_QUEUED 16\n#define BIT_MASK_FWFF_PKT_QUEUED 0xff\n#define BIT_FWFF_PKT_QUEUED(x)                                                 \\\n\t(((x) & BIT_MASK_FWFF_PKT_QUEUED) << BIT_SHIFT_FWFF_PKT_QUEUED)\n#define BITS_FWFF_PKT_QUEUED                                                   \\\n\t(BIT_MASK_FWFF_PKT_QUEUED << BIT_SHIFT_FWFF_PKT_QUEUED)\n#define BIT_CLEAR_FWFF_PKT_QUEUED(x) ((x) & (~BITS_FWFF_PKT_QUEUED))\n#define BIT_GET_FWFF_PKT_QUEUED(x)                                             \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_QUEUED) & BIT_MASK_FWFF_PKT_QUEUED)\n#define BIT_SET_FWFF_PKT_QUEUED(x, v)                                          \\\n\t(BIT_CLEAR_FWFF_PKT_QUEUED(x) | BIT_FWFF_PKT_QUEUED(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FWFF_PKT_INFO\t\t\t(Offset 0x02A0) */\n\n#define BIT_SHIFT_FWFF_PKT_READ_ADDR 16\n#define BIT_MASK_FWFF_PKT_READ_ADDR 0xffff\n#define BIT_FWFF_PKT_READ_ADDR(x)                                              \\\n\t(((x) & BIT_MASK_FWFF_PKT_READ_ADDR) << BIT_SHIFT_FWFF_PKT_READ_ADDR)\n#define BITS_FWFF_PKT_READ_ADDR                                                \\\n\t(BIT_MASK_FWFF_PKT_READ_ADDR << BIT_SHIFT_FWFF_PKT_READ_ADDR)\n#define BIT_CLEAR_FWFF_PKT_READ_ADDR(x) ((x) & (~BITS_FWFF_PKT_READ_ADDR))\n#define BIT_GET_FWFF_PKT_READ_ADDR(x)                                          \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_READ_ADDR) & BIT_MASK_FWFF_PKT_READ_ADDR)\n#define BIT_SET_FWFF_PKT_READ_ADDR(x, v)                                       \\\n\t(BIT_CLEAR_FWFF_PKT_READ_ADDR(x) | BIT_FWFF_PKT_READ_ADDR(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_FWFF_PKT_INFO\t\t\t(Offset 0x02A0) */\n\n#define BIT_SHIFT_FWFF_PKT_STR_ADDR 0\n#define BIT_MASK_FWFF_PKT_STR_ADDR 0xffff\n#define BIT_FWFF_PKT_STR_ADDR(x)                                               \\\n\t(((x) & BIT_MASK_FWFF_PKT_STR_ADDR) << BIT_SHIFT_FWFF_PKT_STR_ADDR)\n#define BITS_FWFF_PKT_STR_ADDR                                                 \\\n\t(BIT_MASK_FWFF_PKT_STR_ADDR << BIT_SHIFT_FWFF_PKT_STR_ADDR)\n#define BIT_CLEAR_FWFF_PKT_STR_ADDR(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR))\n#define BIT_GET_FWFF_PKT_STR_ADDR(x)                                           \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR) & BIT_MASK_FWFF_PKT_STR_ADDR)\n#define BIT_SET_FWFF_PKT_STR_ADDR(x, v)                                        \\\n\t(BIT_CLEAR_FWFF_PKT_STR_ADDR(x) | BIT_FWFF_PKT_STR_ADDR(v))\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FWFF_PKT_INFO\t\t\t(Offset 0x02A0) */\n\n#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V1 0\n#define BIT_MASK_FWFF_PKT_STR_ADDR_V1 0x7ff\n#define BIT_FWFF_PKT_STR_ADDR_V1(x)                                            \\\n\t(((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V1)                                 \\\n\t << BIT_SHIFT_FWFF_PKT_STR_ADDR_V1)\n#define BITS_FWFF_PKT_STR_ADDR_V1                                              \\\n\t(BIT_MASK_FWFF_PKT_STR_ADDR_V1 << BIT_SHIFT_FWFF_PKT_STR_ADDR_V1)\n#define BIT_CLEAR_FWFF_PKT_STR_ADDR_V1(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR_V1))\n#define BIT_GET_FWFF_PKT_STR_ADDR_V1(x)                                        \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V1) &                             \\\n\t BIT_MASK_FWFF_PKT_STR_ADDR_V1)\n#define BIT_SET_FWFF_PKT_STR_ADDR_V1(x, v)                                     \\\n\t(BIT_CLEAR_FWFF_PKT_STR_ADDR_V1(x) | BIT_FWFF_PKT_STR_ADDR_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FWFF_PKT_INFO\t\t\t(Offset 0x02A0) */\n\n#define BIT_SHIFT_FWFF_PKT_WRITE_ADDR 0\n#define BIT_MASK_FWFF_PKT_WRITE_ADDR 0xffff\n#define BIT_FWFF_PKT_WRITE_ADDR(x)                                             \\\n\t(((x) & BIT_MASK_FWFF_PKT_WRITE_ADDR) << BIT_SHIFT_FWFF_PKT_WRITE_ADDR)\n#define BITS_FWFF_PKT_WRITE_ADDR                                               \\\n\t(BIT_MASK_FWFF_PKT_WRITE_ADDR << BIT_SHIFT_FWFF_PKT_WRITE_ADDR)\n#define BIT_CLEAR_FWFF_PKT_WRITE_ADDR(x) ((x) & (~BITS_FWFF_PKT_WRITE_ADDR))\n#define BIT_GET_FWFF_PKT_WRITE_ADDR(x)                                         \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_WRITE_ADDR) & BIT_MASK_FWFF_PKT_WRITE_ADDR)\n#define BIT_SET_FWFF_PKT_WRITE_ADDR(x, v)                                      \\\n\t(BIT_CLEAR_FWFF_PKT_WRITE_ADDR(x) | BIT_FWFF_PKT_WRITE_ADDR(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_FC2H_INFO\t\t\t\t(Offset 0x02A4) */\n\n#define BIT_FC2H_PKT_REQ BIT(16)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FC2H_INFO\t\t\t\t(Offset 0x02A4) */\n\n#define BIT_FC2H_DMAPKT_REQ BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FC2H_INFO\t\t\t\t(Offset 0x02A4) */\n\n#define BIT_SHIFT_FC2H_STR_ADDR 0\n#define BIT_MASK_FC2H_STR_ADDR 0xffff\n#define BIT_FC2H_STR_ADDR(x)                                                   \\\n\t(((x) & BIT_MASK_FC2H_STR_ADDR) << BIT_SHIFT_FC2H_STR_ADDR)\n#define BITS_FC2H_STR_ADDR (BIT_MASK_FC2H_STR_ADDR << BIT_SHIFT_FC2H_STR_ADDR)\n#define BIT_CLEAR_FC2H_STR_ADDR(x) ((x) & (~BITS_FC2H_STR_ADDR))\n#define BIT_GET_FC2H_STR_ADDR(x)                                               \\\n\t(((x) >> BIT_SHIFT_FC2H_STR_ADDR) & BIT_MASK_FC2H_STR_ADDR)\n#define BIT_SET_FC2H_STR_ADDR(x, v)                                            \\\n\t(BIT_CLEAR_FC2H_STR_ADDR(x) | BIT_FC2H_STR_ADDR(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FWFF_PKT_INFO2\t\t\t(Offset 0x02A4) */\n\n#define BIT_SHIFT_FWFF_PKT_QUEUED_V1 0\n#define BIT_MASK_FWFF_PKT_QUEUED_V1 0xffff\n#define BIT_FWFF_PKT_QUEUED_V1(x)                                              \\\n\t(((x) & BIT_MASK_FWFF_PKT_QUEUED_V1) << BIT_SHIFT_FWFF_PKT_QUEUED_V1)\n#define BITS_FWFF_PKT_QUEUED_V1                                                \\\n\t(BIT_MASK_FWFF_PKT_QUEUED_V1 << BIT_SHIFT_FWFF_PKT_QUEUED_V1)\n#define BIT_CLEAR_FWFF_PKT_QUEUED_V1(x) ((x) & (~BITS_FWFF_PKT_QUEUED_V1))\n#define BIT_GET_FWFF_PKT_QUEUED_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_V1) & BIT_MASK_FWFF_PKT_QUEUED_V1)\n#define BIT_SET_FWFF_PKT_QUEUED_V1(x, v)                                       \\\n\t(BIT_CLEAR_FWFF_PKT_QUEUED_V1(x) | BIT_FWFF_PKT_QUEUED_V1(v))\n\n#define BIT_SHIFT_FW_UPD_RXDES_RD_PTR 0\n#define BIT_MASK_FW_UPD_RXDES_RD_PTR 0x3ffff\n#define BIT_FW_UPD_RXDES_RD_PTR(x)                                             \\\n\t(((x) & BIT_MASK_FW_UPD_RXDES_RD_PTR) << BIT_SHIFT_FW_UPD_RXDES_RD_PTR)\n#define BITS_FW_UPD_RXDES_RD_PTR                                               \\\n\t(BIT_MASK_FW_UPD_RXDES_RD_PTR << BIT_SHIFT_FW_UPD_RXDES_RD_PTR)\n#define BIT_CLEAR_FW_UPD_RXDES_RD_PTR(x) ((x) & (~BITS_FW_UPD_RXDES_RD_PTR))\n#define BIT_GET_FW_UPD_RXDES_RD_PTR(x)                                         \\\n\t(((x) >> BIT_SHIFT_FW_UPD_RXDES_RD_PTR) & BIT_MASK_FW_UPD_RXDES_RD_PTR)\n#define BIT_SET_FW_UPD_RXDES_RD_PTR(x, v)                                      \\\n\t(BIT_CLEAR_FW_UPD_RXDES_RD_PTR(x) | BIT_FW_UPD_RXDES_RD_PTR(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXPKTNUM\t\t\t\t(Offset 0x02B0) */\n\n#define BIT_SHIFT_PKT_NUM_WOL_V1 16\n#define BIT_MASK_PKT_NUM_WOL_V1 0xffff\n#define BIT_PKT_NUM_WOL_V1(x)                                                  \\\n\t(((x) & BIT_MASK_PKT_NUM_WOL_V1) << BIT_SHIFT_PKT_NUM_WOL_V1)\n#define BITS_PKT_NUM_WOL_V1                                                    \\\n\t(BIT_MASK_PKT_NUM_WOL_V1 << BIT_SHIFT_PKT_NUM_WOL_V1)\n#define BIT_CLEAR_PKT_NUM_WOL_V1(x) ((x) & (~BITS_PKT_NUM_WOL_V1))\n#define BIT_GET_PKT_NUM_WOL_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_WOL_V1) & BIT_MASK_PKT_NUM_WOL_V1)\n#define BIT_SET_PKT_NUM_WOL_V1(x, v)                                           \\\n\t(BIT_CLEAR_PKT_NUM_WOL_V1(x) | BIT_PKT_NUM_WOL_V1(v))\n\n#define BIT_SHIFT_RXPKT_NUM_V1 0\n#define BIT_MASK_RXPKT_NUM_V1 0xffff\n#define BIT_RXPKT_NUM_V1(x)                                                    \\\n\t(((x) & BIT_MASK_RXPKT_NUM_V1) << BIT_SHIFT_RXPKT_NUM_V1)\n#define BITS_RXPKT_NUM_V1 (BIT_MASK_RXPKT_NUM_V1 << BIT_SHIFT_RXPKT_NUM_V1)\n#define BIT_CLEAR_RXPKT_NUM_V1(x) ((x) & (~BITS_RXPKT_NUM_V1))\n#define BIT_GET_RXPKT_NUM_V1(x)                                                \\\n\t(((x) >> BIT_SHIFT_RXPKT_NUM_V1) & BIT_MASK_RXPKT_NUM_V1)\n#define BIT_SET_RXPKT_NUM_V1(x, v)                                             \\\n\t(BIT_CLEAR_RXPKT_NUM_V1(x) | BIT_RXPKT_NUM_V1(v))\n\n#define BIT_SHIFT_RXPKT_NUM_TH 0\n#define BIT_MASK_RXPKT_NUM_TH 0xff\n#define BIT_RXPKT_NUM_TH(x)                                                    \\\n\t(((x) & BIT_MASK_RXPKT_NUM_TH) << BIT_SHIFT_RXPKT_NUM_TH)\n#define BITS_RXPKT_NUM_TH (BIT_MASK_RXPKT_NUM_TH << BIT_SHIFT_RXPKT_NUM_TH)\n#define BIT_CLEAR_RXPKT_NUM_TH(x) ((x) & (~BITS_RXPKT_NUM_TH))\n#define BIT_GET_RXPKT_NUM_TH(x)                                                \\\n\t(((x) >> BIT_SHIFT_RXPKT_NUM_TH) & BIT_MASK_RXPKT_NUM_TH)\n#define BIT_SET_RXPKT_NUM_TH(x, v)                                             \\\n\t(BIT_CLEAR_RXPKT_NUM_TH(x) | BIT_RXPKT_NUM_TH(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FW_MSG1\t\t\t\t(Offset 0x02E0) */\n\n#define BIT_SHIFT_FW_MSG_REG1 0\n#define BIT_MASK_FW_MSG_REG1 0xffffffffL\n#define BIT_FW_MSG_REG1(x)                                                     \\\n\t(((x) & BIT_MASK_FW_MSG_REG1) << BIT_SHIFT_FW_MSG_REG1)\n#define BITS_FW_MSG_REG1 (BIT_MASK_FW_MSG_REG1 << BIT_SHIFT_FW_MSG_REG1)\n#define BIT_CLEAR_FW_MSG_REG1(x) ((x) & (~BITS_FW_MSG_REG1))\n#define BIT_GET_FW_MSG_REG1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_FW_MSG_REG1) & BIT_MASK_FW_MSG_REG1)\n#define BIT_SET_FW_MSG_REG1(x, v)                                              \\\n\t(BIT_CLEAR_FW_MSG_REG1(x) | BIT_FW_MSG_REG1(v))\n\n/* 2 REG_FW_MSG2\t\t\t\t(Offset 0x02E4) */\n\n#define BIT_SHIFT_FW_MSG_REG2 0\n#define BIT_MASK_FW_MSG_REG2 0xffffffffL\n#define BIT_FW_MSG_REG2(x)                                                     \\\n\t(((x) & BIT_MASK_FW_MSG_REG2) << BIT_SHIFT_FW_MSG_REG2)\n#define BITS_FW_MSG_REG2 (BIT_MASK_FW_MSG_REG2 << BIT_SHIFT_FW_MSG_REG2)\n#define BIT_CLEAR_FW_MSG_REG2(x) ((x) & (~BITS_FW_MSG_REG2))\n#define BIT_GET_FW_MSG_REG2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_FW_MSG_REG2) & BIT_MASK_FW_MSG_REG2)\n#define BIT_SET_FW_MSG_REG2(x, v)                                              \\\n\t(BIT_CLEAR_FW_MSG_REG2(x) | BIT_FW_MSG_REG2(v))\n\n/* 2 REG_FW_MSG3\t\t\t\t(Offset 0x02E8) */\n\n#define BIT_SHIFT_FW_MSG_REG3 0\n#define BIT_MASK_FW_MSG_REG3 0xffffffffL\n#define BIT_FW_MSG_REG3(x)                                                     \\\n\t(((x) & BIT_MASK_FW_MSG_REG3) << BIT_SHIFT_FW_MSG_REG3)\n#define BITS_FW_MSG_REG3 (BIT_MASK_FW_MSG_REG3 << BIT_SHIFT_FW_MSG_REG3)\n#define BIT_CLEAR_FW_MSG_REG3(x) ((x) & (~BITS_FW_MSG_REG3))\n#define BIT_GET_FW_MSG_REG3(x)                                                 \\\n\t(((x) >> BIT_SHIFT_FW_MSG_REG3) & BIT_MASK_FW_MSG_REG3)\n#define BIT_SET_FW_MSG_REG3(x, v)                                              \\\n\t(BIT_CLEAR_FW_MSG_REG3(x) | BIT_FW_MSG_REG3(v))\n\n/* 2 REG_FW_MSG4\t\t\t\t(Offset 0x02EC) */\n\n#define BIT_SHIFT_FW_MSG_REG4 0\n#define BIT_MASK_FW_MSG_REG4 0xffffffffL\n#define BIT_FW_MSG_REG4(x)                                                     \\\n\t(((x) & BIT_MASK_FW_MSG_REG4) << BIT_SHIFT_FW_MSG_REG4)\n#define BITS_FW_MSG_REG4 (BIT_MASK_FW_MSG_REG4 << BIT_SHIFT_FW_MSG_REG4)\n#define BIT_CLEAR_FW_MSG_REG4(x) ((x) & (~BITS_FW_MSG_REG4))\n#define BIT_GET_FW_MSG_REG4(x)                                                 \\\n\t(((x) >> BIT_SHIFT_FW_MSG_REG4) & BIT_MASK_FW_MSG_REG4)\n#define BIT_SET_FW_MSG_REG4(x, v)                                              \\\n\t(BIT_CLEAR_FW_MSG_REG4(x) | BIT_FW_MSG_REG4(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PCIE_CTRL\t\t\t\t(Offset 0x0300) */\n\n#define BIT_PCIEIO_PERSTB_SEL BIT(31)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HCI_CTRL\t\t\t\t(Offset 0x0300) */\n\n#define BIT_HCIIO_PERSTB_SEL BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PCIE_CTRL\t\t\t\t(Offset 0x0300) */\n\n#define BIT_SHIFT_PCIE_MAX_RXDMA 28\n#define BIT_MASK_PCIE_MAX_RXDMA 0x7\n#define BIT_PCIE_MAX_RXDMA(x)                                                  \\\n\t(((x) & BIT_MASK_PCIE_MAX_RXDMA) << BIT_SHIFT_PCIE_MAX_RXDMA)\n#define BITS_PCIE_MAX_RXDMA                                                    \\\n\t(BIT_MASK_PCIE_MAX_RXDMA << BIT_SHIFT_PCIE_MAX_RXDMA)\n#define BIT_CLEAR_PCIE_MAX_RXDMA(x) ((x) & (~BITS_PCIE_MAX_RXDMA))\n#define BIT_GET_PCIE_MAX_RXDMA(x)                                              \\\n\t(((x) >> BIT_SHIFT_PCIE_MAX_RXDMA) & BIT_MASK_PCIE_MAX_RXDMA)\n#define BIT_SET_PCIE_MAX_RXDMA(x, v)                                           \\\n\t(BIT_CLEAR_PCIE_MAX_RXDMA(x) | BIT_PCIE_MAX_RXDMA(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HCI_CTRL\t\t\t\t(Offset 0x0300) */\n\n#define BIT_SHIFT_HCI_MAX_RXDMA 28\n#define BIT_MASK_HCI_MAX_RXDMA 0x7\n#define BIT_HCI_MAX_RXDMA(x)                                                   \\\n\t(((x) & BIT_MASK_HCI_MAX_RXDMA) << BIT_SHIFT_HCI_MAX_RXDMA)\n#define BITS_HCI_MAX_RXDMA (BIT_MASK_HCI_MAX_RXDMA << BIT_SHIFT_HCI_MAX_RXDMA)\n#define BIT_CLEAR_HCI_MAX_RXDMA(x) ((x) & (~BITS_HCI_MAX_RXDMA))\n#define BIT_GET_HCI_MAX_RXDMA(x)                                               \\\n\t(((x) >> BIT_SHIFT_HCI_MAX_RXDMA) & BIT_MASK_HCI_MAX_RXDMA)\n#define BIT_SET_HCI_MAX_RXDMA(x, v)                                            \\\n\t(BIT_CLEAR_HCI_MAX_RXDMA(x) | BIT_HCI_MAX_RXDMA(v))\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LX_CTRL1\t\t\t\t(Offset 0x0300) */\n\n#define BIT_RX_LIT_EDN_SEL BIT(27)\n#define BIT_TX_LIT_EDN_SEL BIT(26)\n#define BIT_WT_LIT_EDN BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PCIE_CTRL\t\t\t\t(Offset 0x0300) */\n\n#define BIT_SHIFT_PCIE_MAX_TXDMA 24\n#define BIT_MASK_PCIE_MAX_TXDMA 0x7\n#define BIT_PCIE_MAX_TXDMA(x)                                                  \\\n\t(((x) & BIT_MASK_PCIE_MAX_TXDMA) << BIT_SHIFT_PCIE_MAX_TXDMA)\n#define BITS_PCIE_MAX_TXDMA                                                    \\\n\t(BIT_MASK_PCIE_MAX_TXDMA << BIT_SHIFT_PCIE_MAX_TXDMA)\n#define BIT_CLEAR_PCIE_MAX_TXDMA(x) ((x) & (~BITS_PCIE_MAX_TXDMA))\n#define BIT_GET_PCIE_MAX_TXDMA(x)                                              \\\n\t(((x) >> BIT_SHIFT_PCIE_MAX_TXDMA) & BIT_MASK_PCIE_MAX_TXDMA)\n#define BIT_SET_PCIE_MAX_TXDMA(x, v)                                           \\\n\t(BIT_CLEAR_PCIE_MAX_TXDMA(x) | BIT_PCIE_MAX_TXDMA(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HCI_CTRL\t\t\t\t(Offset 0x0300) */\n\n#define BIT_SHIFT_HCI_MAX_TXDMA 24\n#define BIT_MASK_HCI_MAX_TXDMA 0x7\n#define BIT_HCI_MAX_TXDMA(x)                                                   \\\n\t(((x) & BIT_MASK_HCI_MAX_TXDMA) << BIT_SHIFT_HCI_MAX_TXDMA)\n#define BITS_HCI_MAX_TXDMA (BIT_MASK_HCI_MAX_TXDMA << BIT_SHIFT_HCI_MAX_TXDMA)\n#define BIT_CLEAR_HCI_MAX_TXDMA(x) ((x) & (~BITS_HCI_MAX_TXDMA))\n#define BIT_GET_HCI_MAX_TXDMA(x)                                               \\\n\t(((x) >> BIT_SHIFT_HCI_MAX_TXDMA) & BIT_MASK_HCI_MAX_TXDMA)\n#define BIT_SET_HCI_MAX_TXDMA(x, v)                                            \\\n\t(BIT_CLEAR_HCI_MAX_TXDMA(x) | BIT_HCI_MAX_TXDMA(v))\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LX_CTRL1\t\t\t\t(Offset 0x0300) */\n\n#define BIT_RD_LITT_EDN BIT(24)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PCIE_CTRL\t\t\t\t(Offset 0x0300) */\n\n#define BIT_PWR_SCALE_START_PS BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PCIE_CTRL\t\t\t\t(Offset 0x0300) */\n\n#define BIT_PCIE_RST_TRXDMA_INTF BIT(20)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HCI_CTRL\t\t\t\t(Offset 0x0300) */\n\n#define BIT_HCI_RST_TRXDMA_INTF BIT(20)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LX_CTRL1\t\t\t\t(Offset 0x0300) */\n\n#define BIT_SHIFT_MAX_RXDMA 20\n#define BIT_MASK_MAX_RXDMA 0x7\n#define BIT_MAX_RXDMA(x) (((x) & BIT_MASK_MAX_RXDMA) << BIT_SHIFT_MAX_RXDMA)\n#define BITS_MAX_RXDMA (BIT_MASK_MAX_RXDMA << BIT_SHIFT_MAX_RXDMA)\n#define BIT_CLEAR_MAX_RXDMA(x) ((x) & (~BITS_MAX_RXDMA))\n#define BIT_GET_MAX_RXDMA(x) (((x) >> BIT_SHIFT_MAX_RXDMA) & BIT_MASK_MAX_RXDMA)\n#define BIT_SET_MAX_RXDMA(x, v) (BIT_CLEAR_MAX_RXDMA(x) | BIT_MAX_RXDMA(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PCIE_CTRL\t\t\t\t(Offset 0x0300) */\n\n#define BIT_PCIE_EN_SWENT_L23 BIT(17)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HCI_CTRL\t\t\t\t(Offset 0x0300) */\n\n#define BIT_HCI_EN_SWENT_L23 BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PCIE_CTRL\t\t\t\t(Offset 0x0300) */\n\n#define BIT_PCIE_EN_HWEXT_L1 BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HCI_CTRL\t\t\t\t(Offset 0x0300) */\n\n#define BIT_HCI_EN_HWEXT_L1 BIT(16)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LX_CTRL1\t\t\t\t(Offset 0x0300) */\n\n#define BIT_SHIFT_MAX_TXDMA 16\n#define BIT_MASK_MAX_TXDMA 0x7\n#define BIT_MAX_TXDMA(x) (((x) & BIT_MASK_MAX_TXDMA) << BIT_SHIFT_MAX_TXDMA)\n#define BITS_MAX_TXDMA (BIT_MASK_MAX_TXDMA << BIT_SHIFT_MAX_TXDMA)\n#define BIT_CLEAR_MAX_TXDMA(x) ((x) & (~BITS_MAX_TXDMA))\n#define BIT_GET_MAX_TXDMA(x) (((x) >> BIT_SHIFT_MAX_TXDMA) & BIT_MASK_MAX_TXDMA)\n#define BIT_SET_MAX_TXDMA(x, v) (BIT_CLEAR_MAX_TXDMA(x) | BIT_MAX_TXDMA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PCIE_CTRL\t\t\t\t(Offset 0x0300) */\n\n#define BIT_STOP_P0_MPRT_BCNQ4 BIT(6)\n#define BIT_STOP_P0_MPRT_BCNQ3 BIT(4)\n#define BIT_STOP_P0_MPRT_BCNQ2 BIT(2)\n#define BIT_STOP_P0_MPRT_BCNQ1 BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_INT_MIG\t\t\t\t(Offset 0x0304) */\n\n#define BIT_SHIFT_TXTTIMER_MATCH_NUM 28\n#define BIT_MASK_TXTTIMER_MATCH_NUM 0xf\n#define BIT_TXTTIMER_MATCH_NUM(x)                                              \\\n\t(((x) & BIT_MASK_TXTTIMER_MATCH_NUM) << BIT_SHIFT_TXTTIMER_MATCH_NUM)\n#define BITS_TXTTIMER_MATCH_NUM                                                \\\n\t(BIT_MASK_TXTTIMER_MATCH_NUM << BIT_SHIFT_TXTTIMER_MATCH_NUM)\n#define BIT_CLEAR_TXTTIMER_MATCH_NUM(x) ((x) & (~BITS_TXTTIMER_MATCH_NUM))\n#define BIT_GET_TXTTIMER_MATCH_NUM(x)                                          \\\n\t(((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM) & BIT_MASK_TXTTIMER_MATCH_NUM)\n#define BIT_SET_TXTTIMER_MATCH_NUM(x, v)                                       \\\n\t(BIT_CLEAR_TXTTIMER_MATCH_NUM(x) | BIT_TXTTIMER_MATCH_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH_CTRL\t\t\t\t(Offset 0x0304) */\n\n#define BIT_STOP_P0HIQ19 BIT(27)\n#define BIT_STOP_P0HIQ18 BIT(26)\n#define BIT_STOP_P0HIQ17 BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_INT_MIG\t\t\t\t(Offset 0x0304) */\n\n#define BIT_SHIFT_TXPKT_NUM_MATCH 24\n#define BIT_MASK_TXPKT_NUM_MATCH 0xf\n#define BIT_TXPKT_NUM_MATCH(x)                                                 \\\n\t(((x) & BIT_MASK_TXPKT_NUM_MATCH) << BIT_SHIFT_TXPKT_NUM_MATCH)\n#define BITS_TXPKT_NUM_MATCH                                                   \\\n\t(BIT_MASK_TXPKT_NUM_MATCH << BIT_SHIFT_TXPKT_NUM_MATCH)\n#define BIT_CLEAR_TXPKT_NUM_MATCH(x) ((x) & (~BITS_TXPKT_NUM_MATCH))\n#define BIT_GET_TXPKT_NUM_MATCH(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXPKT_NUM_MATCH) & BIT_MASK_TXPKT_NUM_MATCH)\n#define BIT_SET_TXPKT_NUM_MATCH(x, v)                                          \\\n\t(BIT_CLEAR_TXPKT_NUM_MATCH(x) | BIT_TXPKT_NUM_MATCH(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_INT_MIG\t\t\t\t(Offset 0x0304) */\n\n#define BIT_SHIFT_TRXCOUNTER_MATCH 24\n#define BIT_MASK_TRXCOUNTER_MATCH 0xff\n#define BIT_TRXCOUNTER_MATCH(x)                                                \\\n\t(((x) & BIT_MASK_TRXCOUNTER_MATCH) << BIT_SHIFT_TRXCOUNTER_MATCH)\n#define BITS_TRXCOUNTER_MATCH                                                  \\\n\t(BIT_MASK_TRXCOUNTER_MATCH << BIT_SHIFT_TRXCOUNTER_MATCH)\n#define BIT_CLEAR_TRXCOUNTER_MATCH(x) ((x) & (~BITS_TRXCOUNTER_MATCH))\n#define BIT_GET_TRXCOUNTER_MATCH(x)                                            \\\n\t(((x) >> BIT_SHIFT_TRXCOUNTER_MATCH) & BIT_MASK_TRXCOUNTER_MATCH)\n#define BIT_SET_TRXCOUNTER_MATCH(x, v)                                         \\\n\t(BIT_CLEAR_TRXCOUNTER_MATCH(x) | BIT_TRXCOUNTER_MATCH(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH_CTRL\t\t\t\t(Offset 0x0304) */\n\n#define BIT_STOP_P0HIQ16 BIT(24)\n#define BIT_RX_CLOSE_EN_V1 BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_INT_MIG\t\t\t\t(Offset 0x0304) */\n\n#define BIT_SHIFT_RXTTIMER_MATCH_NUM 20\n#define BIT_MASK_RXTTIMER_MATCH_NUM 0xf\n#define BIT_RXTTIMER_MATCH_NUM(x)                                              \\\n\t(((x) & BIT_MASK_RXTTIMER_MATCH_NUM) << BIT_SHIFT_RXTTIMER_MATCH_NUM)\n#define BITS_RXTTIMER_MATCH_NUM                                                \\\n\t(BIT_MASK_RXTTIMER_MATCH_NUM << BIT_SHIFT_RXTTIMER_MATCH_NUM)\n#define BIT_CLEAR_RXTTIMER_MATCH_NUM(x) ((x) & (~BITS_RXTTIMER_MATCH_NUM))\n#define BIT_GET_RXTTIMER_MATCH_NUM(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM) & BIT_MASK_RXTTIMER_MATCH_NUM)\n#define BIT_SET_RXTTIMER_MATCH_NUM(x, v)                                       \\\n\t(BIT_CLEAR_RXTTIMER_MATCH_NUM(x) | BIT_RXTTIMER_MATCH_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH_CTRL\t\t\t\t(Offset 0x0304) */\n\n#define BIT_STOP_FWCMDQ BIT(20)\n#define BIT_STOP_P0BCNQ BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_INT_MIG\t\t\t\t(Offset 0x0304) */\n\n#define BIT_SHIFT_RXPKT_NUM_MATCH 16\n#define BIT_MASK_RXPKT_NUM_MATCH 0xf\n#define BIT_RXPKT_NUM_MATCH(x)                                                 \\\n\t(((x) & BIT_MASK_RXPKT_NUM_MATCH) << BIT_SHIFT_RXPKT_NUM_MATCH)\n#define BITS_RXPKT_NUM_MATCH                                                   \\\n\t(BIT_MASK_RXPKT_NUM_MATCH << BIT_SHIFT_RXPKT_NUM_MATCH)\n#define BIT_CLEAR_RXPKT_NUM_MATCH(x) ((x) & (~BITS_RXPKT_NUM_MATCH))\n#define BIT_GET_RXPKT_NUM_MATCH(x)                                             \\\n\t(((x) >> BIT_SHIFT_RXPKT_NUM_MATCH) & BIT_MASK_RXPKT_NUM_MATCH)\n#define BIT_SET_RXPKT_NUM_MATCH(x, v)                                          \\\n\t(BIT_CLEAR_RXPKT_NUM_MATCH(x) | BIT_RXPKT_NUM_MATCH(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_INT_MIG\t\t\t\t(Offset 0x0304) */\n\n#define BIT_SHIFT_TRXTIMER_MATCH 16\n#define BIT_MASK_TRXTIMER_MATCH 0xff\n#define BIT_TRXTIMER_MATCH(x)                                                  \\\n\t(((x) & BIT_MASK_TRXTIMER_MATCH) << BIT_SHIFT_TRXTIMER_MATCH)\n#define BITS_TRXTIMER_MATCH                                                    \\\n\t(BIT_MASK_TRXTIMER_MATCH << BIT_SHIFT_TRXTIMER_MATCH)\n#define BIT_CLEAR_TRXTIMER_MATCH(x) ((x) & (~BITS_TRXTIMER_MATCH))\n#define BIT_GET_TRXTIMER_MATCH(x)                                              \\\n\t(((x) >> BIT_SHIFT_TRXTIMER_MATCH) & BIT_MASK_TRXTIMER_MATCH)\n#define BIT_SET_TRXTIMER_MATCH(x, v)                                           \\\n\t(BIT_CLEAR_TRXTIMER_MATCH(x) | BIT_TRXTIMER_MATCH(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH_CTRL\t\t\t\t(Offset 0x0304) */\n\n#define BIT_STOP_P0MGQ BIT(16)\n#define BIT_STOP_ACH13 BIT(15)\n#define BIT_STOP_ACH12 BIT(14)\n#define BIT_STOP_ACH11 BIT(13)\n#define BIT_STOP_ACH10 BIT(12)\n#define BIT_STOP_ACH9 BIT(11)\n#define BIT_STOP_ACH8 BIT(10)\n#define BIT_STOP_ACH7 BIT(9)\n#define BIT_STOP_ACH6 BIT(8)\n#define BIT_STOP_ACH5 BIT(7)\n#define BIT_STOP_ACH4 BIT(6)\n#define BIT_STOP_ACH3 BIT(5)\n#define BIT_STOP_ACH2 BIT(4)\n#define BIT_STOP_ACH1 BIT(3)\n#define BIT_STOP_ACH0 BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_INT_MIG\t\t\t\t(Offset 0x0304) */\n\n#define BIT_SHIFT_MIGRATE_TIMER 0\n#define BIT_MASK_MIGRATE_TIMER 0xffff\n#define BIT_MIGRATE_TIMER(x)                                                   \\\n\t(((x) & BIT_MASK_MIGRATE_TIMER) << BIT_SHIFT_MIGRATE_TIMER)\n#define BITS_MIGRATE_TIMER (BIT_MASK_MIGRATE_TIMER << BIT_SHIFT_MIGRATE_TIMER)\n#define BIT_CLEAR_MIGRATE_TIMER(x) ((x) & (~BITS_MIGRATE_TIMER))\n#define BIT_GET_MIGRATE_TIMER(x)                                               \\\n\t(((x) >> BIT_SHIFT_MIGRATE_TIMER) & BIT_MASK_MIGRATE_TIMER)\n#define BIT_SET_MIGRATE_TIMER(x, v)                                            \\\n\t(BIT_CLEAR_MIGRATE_TIMER(x) | BIT_MIGRATE_TIMER(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_INT_MIG\t\t\t\t(Offset 0x0304) */\n\n#define BIT_SHIFT_TRXTIMER_UNIT 0\n#define BIT_MASK_TRXTIMER_UNIT 0x3\n#define BIT_TRXTIMER_UNIT(x)                                                   \\\n\t(((x) & BIT_MASK_TRXTIMER_UNIT) << BIT_SHIFT_TRXTIMER_UNIT)\n#define BITS_TRXTIMER_UNIT (BIT_MASK_TRXTIMER_UNIT << BIT_SHIFT_TRXTIMER_UNIT)\n#define BIT_CLEAR_TRXTIMER_UNIT(x) ((x) & (~BITS_TRXTIMER_UNIT))\n#define BIT_GET_TRXTIMER_UNIT(x)                                               \\\n\t(((x) >> BIT_SHIFT_TRXTIMER_UNIT) & BIT_MASK_TRXTIMER_UNIT)\n#define BIT_SET_TRXTIMER_UNIT(x, v)                                            \\\n\t(BIT_CLEAR_TRXTIMER_UNIT(x) | BIT_TRXTIMER_UNIT(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH_CTRL\t\t\t\t(Offset 0x0304) */\n\n#define BIT_STOP_P0RX BIT(0)\n\n/* 2 REG_HIQ_CTRL\t\t\t\t(Offset 0x0308) */\n\n#define BIT_STOP_P0HIQ15 BIT(15)\n#define BIT_STOP_P0HIQ14 BIT(14)\n#define BIT_STOP_P0HIQ13 BIT(13)\n#define BIT_STOP_P0HIQ12 BIT(12)\n#define BIT_STOP_P0HIQ11 BIT(11)\n#define BIT_STOP_P0HIQ10 BIT(10)\n#define BIT_STOP_P0HIQ9 BIT(9)\n#define BIT_STOP_P0HIQ8 BIT(8)\n#define BIT_STOP_P0HIQ7 BIT(7)\n#define BIT_STOP_P0HIQ6 BIT(6)\n#define BIT_STOP_P0HIQ5 BIT(5)\n#define BIT_STOP_P0HIQ4 BIT(4)\n#define BIT_STOP_P0HIQ3 BIT(3)\n#define BIT_STOP_P0HIQ2 BIT(2)\n#define BIT_STOP_P0HIQ1 BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BCNQ_TXBD_DESA\t\t\t(Offset 0x0308) */\n\n#define BIT_SHIFT_BCNQ_TXBD_DESA 0\n#define BIT_MASK_BCNQ_TXBD_DESA 0xffffffffffffffffL\n#define BIT_BCNQ_TXBD_DESA(x)                                                  \\\n\t(((x) & BIT_MASK_BCNQ_TXBD_DESA) << BIT_SHIFT_BCNQ_TXBD_DESA)\n#define BITS_BCNQ_TXBD_DESA                                                    \\\n\t(BIT_MASK_BCNQ_TXBD_DESA << BIT_SHIFT_BCNQ_TXBD_DESA)\n#define BIT_CLEAR_BCNQ_TXBD_DESA(x) ((x) & (~BITS_BCNQ_TXBD_DESA))\n#define BIT_GET_BCNQ_TXBD_DESA(x)                                              \\\n\t(((x) >> BIT_SHIFT_BCNQ_TXBD_DESA) & BIT_MASK_BCNQ_TXBD_DESA)\n#define BIT_SET_BCNQ_TXBD_DESA(x, v)                                           \\\n\t(BIT_CLEAR_BCNQ_TXBD_DESA(x) | BIT_BCNQ_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIQ_CTRL\t\t\t\t(Offset 0x0308) */\n\n#define BIT_STOP_P0HIQ0 BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MGQ_TXBD_DESA\t\t\t(Offset 0x0310) */\n\n#define BIT_SHIFT_MGQ_TXBD_DESA 0\n#define BIT_MASK_MGQ_TXBD_DESA 0xffffffffffffffffL\n#define BIT_MGQ_TXBD_DESA(x)                                                   \\\n\t(((x) & BIT_MASK_MGQ_TXBD_DESA) << BIT_SHIFT_MGQ_TXBD_DESA)\n#define BITS_MGQ_TXBD_DESA (BIT_MASK_MGQ_TXBD_DESA << BIT_SHIFT_MGQ_TXBD_DESA)\n#define BIT_CLEAR_MGQ_TXBD_DESA(x) ((x) & (~BITS_MGQ_TXBD_DESA))\n#define BIT_GET_MGQ_TXBD_DESA(x)                                               \\\n\t(((x) >> BIT_SHIFT_MGQ_TXBD_DESA) & BIT_MASK_MGQ_TXBD_DESA)\n#define BIT_SET_MGQ_TXBD_DESA(x, v)                                            \\\n\t(BIT_CLEAR_MGQ_TXBD_DESA(x) | BIT_MGQ_TXBD_DESA(v))\n\n/* 2 REG_VOQ_TXBD_DESA\t\t\t(Offset 0x0318) */\n\n#define BIT_SHIFT_VOQ_TXBD_DESA 0\n#define BIT_MASK_VOQ_TXBD_DESA 0xffffffffffffffffL\n#define BIT_VOQ_TXBD_DESA(x)                                                   \\\n\t(((x) & BIT_MASK_VOQ_TXBD_DESA) << BIT_SHIFT_VOQ_TXBD_DESA)\n#define BITS_VOQ_TXBD_DESA (BIT_MASK_VOQ_TXBD_DESA << BIT_SHIFT_VOQ_TXBD_DESA)\n#define BIT_CLEAR_VOQ_TXBD_DESA(x) ((x) & (~BITS_VOQ_TXBD_DESA))\n#define BIT_GET_VOQ_TXBD_DESA(x)                                               \\\n\t(((x) >> BIT_SHIFT_VOQ_TXBD_DESA) & BIT_MASK_VOQ_TXBD_DESA)\n#define BIT_SET_VOQ_TXBD_DESA(x, v)                                            \\\n\t(BIT_CLEAR_VOQ_TXBD_DESA(x) | BIT_VOQ_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH0_TXBD_DESA_L\t\t\t(Offset 0x0318) */\n\n#define BIT_SHIFT_ACH0_TXBD_DESA_L 0\n#define BIT_MASK_ACH0_TXBD_DESA_L 0xffffffffL\n#define BIT_ACH0_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_ACH0_TXBD_DESA_L) << BIT_SHIFT_ACH0_TXBD_DESA_L)\n#define BITS_ACH0_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_ACH0_TXBD_DESA_L << BIT_SHIFT_ACH0_TXBD_DESA_L)\n#define BIT_CLEAR_ACH0_TXBD_DESA_L(x) ((x) & (~BITS_ACH0_TXBD_DESA_L))\n#define BIT_GET_ACH0_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH0_TXBD_DESA_L) & BIT_MASK_ACH0_TXBD_DESA_L)\n#define BIT_SET_ACH0_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_ACH0_TXBD_DESA_L(x) | BIT_ACH0_TXBD_DESA_L(v))\n\n/* 2 REG_ACH0_TXBD_DESA_H\t\t\t(Offset 0x031C) */\n\n#define BIT_SHIFT_ACH0_TXBD_DESA_H 0\n#define BIT_MASK_ACH0_TXBD_DESA_H 0xffffffffL\n#define BIT_ACH0_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_ACH0_TXBD_DESA_H) << BIT_SHIFT_ACH0_TXBD_DESA_H)\n#define BITS_ACH0_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_ACH0_TXBD_DESA_H << BIT_SHIFT_ACH0_TXBD_DESA_H)\n#define BIT_CLEAR_ACH0_TXBD_DESA_H(x) ((x) & (~BITS_ACH0_TXBD_DESA_H))\n#define BIT_GET_ACH0_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH0_TXBD_DESA_H) & BIT_MASK_ACH0_TXBD_DESA_H)\n#define BIT_SET_ACH0_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_ACH0_TXBD_DESA_H(x) | BIT_ACH0_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_VIQ_TXBD_DESA\t\t\t(Offset 0x0320) */\n\n#define BIT_SHIFT_VIQ_TXBD_DESA 0\n#define BIT_MASK_VIQ_TXBD_DESA 0xffffffffffffffffL\n#define BIT_VIQ_TXBD_DESA(x)                                                   \\\n\t(((x) & BIT_MASK_VIQ_TXBD_DESA) << BIT_SHIFT_VIQ_TXBD_DESA)\n#define BITS_VIQ_TXBD_DESA (BIT_MASK_VIQ_TXBD_DESA << BIT_SHIFT_VIQ_TXBD_DESA)\n#define BIT_CLEAR_VIQ_TXBD_DESA(x) ((x) & (~BITS_VIQ_TXBD_DESA))\n#define BIT_GET_VIQ_TXBD_DESA(x)                                               \\\n\t(((x) >> BIT_SHIFT_VIQ_TXBD_DESA) & BIT_MASK_VIQ_TXBD_DESA)\n#define BIT_SET_VIQ_TXBD_DESA(x, v)                                            \\\n\t(BIT_CLEAR_VIQ_TXBD_DESA(x) | BIT_VIQ_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH1_TXBD_DESA_L\t\t\t(Offset 0x0320) */\n\n#define BIT_SHIFT_ACH1_TXBD_DESA_L 0\n#define BIT_MASK_ACH1_TXBD_DESA_L 0xffffffffL\n#define BIT_ACH1_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_ACH1_TXBD_DESA_L) << BIT_SHIFT_ACH1_TXBD_DESA_L)\n#define BITS_ACH1_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_ACH1_TXBD_DESA_L << BIT_SHIFT_ACH1_TXBD_DESA_L)\n#define BIT_CLEAR_ACH1_TXBD_DESA_L(x) ((x) & (~BITS_ACH1_TXBD_DESA_L))\n#define BIT_GET_ACH1_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH1_TXBD_DESA_L) & BIT_MASK_ACH1_TXBD_DESA_L)\n#define BIT_SET_ACH1_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_ACH1_TXBD_DESA_L(x) | BIT_ACH1_TXBD_DESA_L(v))\n\n/* 2 REG_ACH1_TXBD_DESA_H\t\t\t(Offset 0x0324) */\n\n#define BIT_SHIFT_ACH1_TXBD_DESA_H 0\n#define BIT_MASK_ACH1_TXBD_DESA_H 0xffffffffL\n#define BIT_ACH1_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_ACH1_TXBD_DESA_H) << BIT_SHIFT_ACH1_TXBD_DESA_H)\n#define BITS_ACH1_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_ACH1_TXBD_DESA_H << BIT_SHIFT_ACH1_TXBD_DESA_H)\n#define BIT_CLEAR_ACH1_TXBD_DESA_H(x) ((x) & (~BITS_ACH1_TXBD_DESA_H))\n#define BIT_GET_ACH1_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH1_TXBD_DESA_H) & BIT_MASK_ACH1_TXBD_DESA_H)\n#define BIT_SET_ACH1_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_ACH1_TXBD_DESA_H(x) | BIT_ACH1_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BEQ_TXBD_DESA\t\t\t(Offset 0x0328) */\n\n#define BIT_SHIFT_BEQ_TXBD_DESA 0\n#define BIT_MASK_BEQ_TXBD_DESA 0xffffffffffffffffL\n#define BIT_BEQ_TXBD_DESA(x)                                                   \\\n\t(((x) & BIT_MASK_BEQ_TXBD_DESA) << BIT_SHIFT_BEQ_TXBD_DESA)\n#define BITS_BEQ_TXBD_DESA (BIT_MASK_BEQ_TXBD_DESA << BIT_SHIFT_BEQ_TXBD_DESA)\n#define BIT_CLEAR_BEQ_TXBD_DESA(x) ((x) & (~BITS_BEQ_TXBD_DESA))\n#define BIT_GET_BEQ_TXBD_DESA(x)                                               \\\n\t(((x) >> BIT_SHIFT_BEQ_TXBD_DESA) & BIT_MASK_BEQ_TXBD_DESA)\n#define BIT_SET_BEQ_TXBD_DESA(x, v)                                            \\\n\t(BIT_CLEAR_BEQ_TXBD_DESA(x) | BIT_BEQ_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH2_TXBD_DESA_L\t\t\t(Offset 0x0328) */\n\n#define BIT_SHIFT_ACH2_TXBD_DESA_L 0\n#define BIT_MASK_ACH2_TXBD_DESA_L 0xffffffffL\n#define BIT_ACH2_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_ACH2_TXBD_DESA_L) << BIT_SHIFT_ACH2_TXBD_DESA_L)\n#define BITS_ACH2_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_ACH2_TXBD_DESA_L << BIT_SHIFT_ACH2_TXBD_DESA_L)\n#define BIT_CLEAR_ACH2_TXBD_DESA_L(x) ((x) & (~BITS_ACH2_TXBD_DESA_L))\n#define BIT_GET_ACH2_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH2_TXBD_DESA_L) & BIT_MASK_ACH2_TXBD_DESA_L)\n#define BIT_SET_ACH2_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_ACH2_TXBD_DESA_L(x) | BIT_ACH2_TXBD_DESA_L(v))\n\n/* 2 REG_ACH2_TXBD_DESA_H\t\t\t(Offset 0x032C) */\n\n#define BIT_SHIFT_ACH2_TXBD_DESA_H 0\n#define BIT_MASK_ACH2_TXBD_DESA_H 0xffffffffL\n#define BIT_ACH2_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_ACH2_TXBD_DESA_H) << BIT_SHIFT_ACH2_TXBD_DESA_H)\n#define BITS_ACH2_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_ACH2_TXBD_DESA_H << BIT_SHIFT_ACH2_TXBD_DESA_H)\n#define BIT_CLEAR_ACH2_TXBD_DESA_H(x) ((x) & (~BITS_ACH2_TXBD_DESA_H))\n#define BIT_GET_ACH2_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH2_TXBD_DESA_H) & BIT_MASK_ACH2_TXBD_DESA_H)\n#define BIT_SET_ACH2_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_ACH2_TXBD_DESA_H(x) | BIT_ACH2_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BKQ_TXBD_DESA\t\t\t(Offset 0x0330) */\n\n#define BIT_SHIFT_BKQ_TXBD_DESA 0\n#define BIT_MASK_BKQ_TXBD_DESA 0xffffffffffffffffL\n#define BIT_BKQ_TXBD_DESA(x)                                                   \\\n\t(((x) & BIT_MASK_BKQ_TXBD_DESA) << BIT_SHIFT_BKQ_TXBD_DESA)\n#define BITS_BKQ_TXBD_DESA (BIT_MASK_BKQ_TXBD_DESA << BIT_SHIFT_BKQ_TXBD_DESA)\n#define BIT_CLEAR_BKQ_TXBD_DESA(x) ((x) & (~BITS_BKQ_TXBD_DESA))\n#define BIT_GET_BKQ_TXBD_DESA(x)                                               \\\n\t(((x) >> BIT_SHIFT_BKQ_TXBD_DESA) & BIT_MASK_BKQ_TXBD_DESA)\n#define BIT_SET_BKQ_TXBD_DESA(x, v)                                            \\\n\t(BIT_CLEAR_BKQ_TXBD_DESA(x) | BIT_BKQ_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH3_TXBD_DESA_L\t\t\t(Offset 0x0330) */\n\n#define BIT_SHIFT_ACH3_TXBD_DESA_L 0\n#define BIT_MASK_ACH3_TXBD_DESA_L 0xffffffffL\n#define BIT_ACH3_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_ACH3_TXBD_DESA_L) << BIT_SHIFT_ACH3_TXBD_DESA_L)\n#define BITS_ACH3_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_ACH3_TXBD_DESA_L << BIT_SHIFT_ACH3_TXBD_DESA_L)\n#define BIT_CLEAR_ACH3_TXBD_DESA_L(x) ((x) & (~BITS_ACH3_TXBD_DESA_L))\n#define BIT_GET_ACH3_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH3_TXBD_DESA_L) & BIT_MASK_ACH3_TXBD_DESA_L)\n#define BIT_SET_ACH3_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_ACH3_TXBD_DESA_L(x) | BIT_ACH3_TXBD_DESA_L(v))\n\n/* 2 REG_ACH3_TXBD_DESA_H\t\t\t(Offset 0x0334) */\n\n#define BIT_SHIFT_ACH3_TXBD_DESA_H 0\n#define BIT_MASK_ACH3_TXBD_DESA_H 0xffffffffL\n#define BIT_ACH3_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_ACH3_TXBD_DESA_H) << BIT_SHIFT_ACH3_TXBD_DESA_H)\n#define BITS_ACH3_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_ACH3_TXBD_DESA_H << BIT_SHIFT_ACH3_TXBD_DESA_H)\n#define BIT_CLEAR_ACH3_TXBD_DESA_H(x) ((x) & (~BITS_ACH3_TXBD_DESA_H))\n#define BIT_GET_ACH3_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH3_TXBD_DESA_H) & BIT_MASK_ACH3_TXBD_DESA_H)\n#define BIT_SET_ACH3_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_ACH3_TXBD_DESA_H(x) | BIT_ACH3_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXQ_RXBD_DESA\t\t\t(Offset 0x0338) */\n\n#define BIT_SHIFT_RXQ_RXBD_DESA 0\n#define BIT_MASK_RXQ_RXBD_DESA 0xffffffffffffffffL\n#define BIT_RXQ_RXBD_DESA(x)                                                   \\\n\t(((x) & BIT_MASK_RXQ_RXBD_DESA) << BIT_SHIFT_RXQ_RXBD_DESA)\n#define BITS_RXQ_RXBD_DESA (BIT_MASK_RXQ_RXBD_DESA << BIT_SHIFT_RXQ_RXBD_DESA)\n#define BIT_CLEAR_RXQ_RXBD_DESA(x) ((x) & (~BITS_RXQ_RXBD_DESA))\n#define BIT_GET_RXQ_RXBD_DESA(x)                                               \\\n\t(((x) >> BIT_SHIFT_RXQ_RXBD_DESA) & BIT_MASK_RXQ_RXBD_DESA)\n#define BIT_SET_RXQ_RXBD_DESA(x, v)                                            \\\n\t(BIT_CLEAR_RXQ_RXBD_DESA(x) | BIT_RXQ_RXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0RXQ_RXBD_DESA_L\t\t\t(Offset 0x0338) */\n\n#define BIT_SHIFT_P0RXQ_RXBD_DESA_L 0\n#define BIT_MASK_P0RXQ_RXBD_DESA_L 0xffffffffL\n#define BIT_P0RXQ_RXBD_DESA_L(x)                                               \\\n\t(((x) & BIT_MASK_P0RXQ_RXBD_DESA_L) << BIT_SHIFT_P0RXQ_RXBD_DESA_L)\n#define BITS_P0RXQ_RXBD_DESA_L                                                 \\\n\t(BIT_MASK_P0RXQ_RXBD_DESA_L << BIT_SHIFT_P0RXQ_RXBD_DESA_L)\n#define BIT_CLEAR_P0RXQ_RXBD_DESA_L(x) ((x) & (~BITS_P0RXQ_RXBD_DESA_L))\n#define BIT_GET_P0RXQ_RXBD_DESA_L(x)                                           \\\n\t(((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_L) & BIT_MASK_P0RXQ_RXBD_DESA_L)\n#define BIT_SET_P0RXQ_RXBD_DESA_L(x, v)                                        \\\n\t(BIT_CLEAR_P0RXQ_RXBD_DESA_L(x) | BIT_P0RXQ_RXBD_DESA_L(v))\n\n/* 2 REG_P0RXQ_RXBD_DESA_H\t\t\t(Offset 0x033C) */\n\n#define BIT_SHIFT_P0RXQ_RXBD_DESA_H 0\n#define BIT_MASK_P0RXQ_RXBD_DESA_H 0xffffffffL\n#define BIT_P0RXQ_RXBD_DESA_H(x)                                               \\\n\t(((x) & BIT_MASK_P0RXQ_RXBD_DESA_H) << BIT_SHIFT_P0RXQ_RXBD_DESA_H)\n#define BITS_P0RXQ_RXBD_DESA_H                                                 \\\n\t(BIT_MASK_P0RXQ_RXBD_DESA_H << BIT_SHIFT_P0RXQ_RXBD_DESA_H)\n#define BIT_CLEAR_P0RXQ_RXBD_DESA_H(x) ((x) & (~BITS_P0RXQ_RXBD_DESA_H))\n#define BIT_GET_P0RXQ_RXBD_DESA_H(x)                                           \\\n\t(((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_H) & BIT_MASK_P0RXQ_RXBD_DESA_H)\n#define BIT_SET_P0RXQ_RXBD_DESA_H(x, v)                                        \\\n\t(BIT_CLEAR_P0RXQ_RXBD_DESA_H(x) | BIT_P0RXQ_RXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI0Q_TXBD_DESA\t\t\t(Offset 0x0340) */\n\n#define BIT_SHIFT_HI0Q_TXBD_DESA 0\n#define BIT_MASK_HI0Q_TXBD_DESA 0xffffffffffffffffL\n#define BIT_HI0Q_TXBD_DESA(x)                                                  \\\n\t(((x) & BIT_MASK_HI0Q_TXBD_DESA) << BIT_SHIFT_HI0Q_TXBD_DESA)\n#define BITS_HI0Q_TXBD_DESA                                                    \\\n\t(BIT_MASK_HI0Q_TXBD_DESA << BIT_SHIFT_HI0Q_TXBD_DESA)\n#define BIT_CLEAR_HI0Q_TXBD_DESA(x) ((x) & (~BITS_HI0Q_TXBD_DESA))\n#define BIT_GET_HI0Q_TXBD_DESA(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA) & BIT_MASK_HI0Q_TXBD_DESA)\n#define BIT_SET_HI0Q_TXBD_DESA(x, v)                                           \\\n\t(BIT_CLEAR_HI0Q_TXBD_DESA(x) | BIT_HI0Q_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0BCNQ_TXBD_DESA_L\t\t\t(Offset 0x0340) */\n\n#define BIT_SHIFT_P0BCNQ_TXBD_DESA_L 0\n#define BIT_MASK_P0BCNQ_TXBD_DESA_L 0xffffffffL\n#define BIT_P0BCNQ_TXBD_DESA_L(x)                                              \\\n\t(((x) & BIT_MASK_P0BCNQ_TXBD_DESA_L) << BIT_SHIFT_P0BCNQ_TXBD_DESA_L)\n#define BITS_P0BCNQ_TXBD_DESA_L                                                \\\n\t(BIT_MASK_P0BCNQ_TXBD_DESA_L << BIT_SHIFT_P0BCNQ_TXBD_DESA_L)\n#define BIT_CLEAR_P0BCNQ_TXBD_DESA_L(x) ((x) & (~BITS_P0BCNQ_TXBD_DESA_L))\n#define BIT_GET_P0BCNQ_TXBD_DESA_L(x)                                          \\\n\t(((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_L) & BIT_MASK_P0BCNQ_TXBD_DESA_L)\n#define BIT_SET_P0BCNQ_TXBD_DESA_L(x, v)                                       \\\n\t(BIT_CLEAR_P0BCNQ_TXBD_DESA_L(x) | BIT_P0BCNQ_TXBD_DESA_L(v))\n\n/* 2 REG_P0BCNQ_TXBD_DESA_H\t\t\t(Offset 0x0344) */\n\n#define BIT_SHIFT_P0BCNQ_TXBD_DESA_H 0\n#define BIT_MASK_P0BCNQ_TXBD_DESA_H 0xffffffffL\n#define BIT_P0BCNQ_TXBD_DESA_H(x)                                              \\\n\t(((x) & BIT_MASK_P0BCNQ_TXBD_DESA_H) << BIT_SHIFT_P0BCNQ_TXBD_DESA_H)\n#define BITS_P0BCNQ_TXBD_DESA_H                                                \\\n\t(BIT_MASK_P0BCNQ_TXBD_DESA_H << BIT_SHIFT_P0BCNQ_TXBD_DESA_H)\n#define BIT_CLEAR_P0BCNQ_TXBD_DESA_H(x) ((x) & (~BITS_P0BCNQ_TXBD_DESA_H))\n#define BIT_GET_P0BCNQ_TXBD_DESA_H(x)                                          \\\n\t(((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_H) & BIT_MASK_P0BCNQ_TXBD_DESA_H)\n#define BIT_SET_P0BCNQ_TXBD_DESA_H(x, v)                                       \\\n\t(BIT_CLEAR_P0BCNQ_TXBD_DESA_H(x) | BIT_P0BCNQ_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI1Q_TXBD_DESA\t\t\t(Offset 0x0348) */\n\n#define BIT_SHIFT_HI1Q_TXBD_DESA 0\n#define BIT_MASK_HI1Q_TXBD_DESA 0xffffffffffffffffL\n#define BIT_HI1Q_TXBD_DESA(x)                                                  \\\n\t(((x) & BIT_MASK_HI1Q_TXBD_DESA) << BIT_SHIFT_HI1Q_TXBD_DESA)\n#define BITS_HI1Q_TXBD_DESA                                                    \\\n\t(BIT_MASK_HI1Q_TXBD_DESA << BIT_SHIFT_HI1Q_TXBD_DESA)\n#define BIT_CLEAR_HI1Q_TXBD_DESA(x) ((x) & (~BITS_HI1Q_TXBD_DESA))\n#define BIT_GET_HI1Q_TXBD_DESA(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA) & BIT_MASK_HI1Q_TXBD_DESA)\n#define BIT_SET_HI1Q_TXBD_DESA(x, v)                                           \\\n\t(BIT_CLEAR_HI1Q_TXBD_DESA(x) | BIT_HI1Q_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FWCMDQ_TXBD_DESA_L\t\t\t(Offset 0x0348) */\n\n#define BIT_SHIFT_FWCMDQ_TXBD_DESA_L 0\n#define BIT_MASK_FWCMDQ_TXBD_DESA_L 0xffffffffL\n#define BIT_FWCMDQ_TXBD_DESA_L(x)                                              \\\n\t(((x) & BIT_MASK_FWCMDQ_TXBD_DESA_L) << BIT_SHIFT_FWCMDQ_TXBD_DESA_L)\n#define BITS_FWCMDQ_TXBD_DESA_L                                                \\\n\t(BIT_MASK_FWCMDQ_TXBD_DESA_L << BIT_SHIFT_FWCMDQ_TXBD_DESA_L)\n#define BIT_CLEAR_FWCMDQ_TXBD_DESA_L(x) ((x) & (~BITS_FWCMDQ_TXBD_DESA_L))\n#define BIT_GET_FWCMDQ_TXBD_DESA_L(x)                                          \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_L) & BIT_MASK_FWCMDQ_TXBD_DESA_L)\n#define BIT_SET_FWCMDQ_TXBD_DESA_L(x, v)                                       \\\n\t(BIT_CLEAR_FWCMDQ_TXBD_DESA_L(x) | BIT_FWCMDQ_TXBD_DESA_L(v))\n\n/* 2 REG_FWCMDQ_TXBD_DESA_H\t\t\t(Offset 0x034C) */\n\n#define BIT_SHIFT_FWCMDQ_TXBD_DESA_H 0\n#define BIT_MASK_FWCMDQ_TXBD_DESA_H 0xffffffffL\n#define BIT_FWCMDQ_TXBD_DESA_H(x)                                              \\\n\t(((x) & BIT_MASK_FWCMDQ_TXBD_DESA_H) << BIT_SHIFT_FWCMDQ_TXBD_DESA_H)\n#define BITS_FWCMDQ_TXBD_DESA_H                                                \\\n\t(BIT_MASK_FWCMDQ_TXBD_DESA_H << BIT_SHIFT_FWCMDQ_TXBD_DESA_H)\n#define BIT_CLEAR_FWCMDQ_TXBD_DESA_H(x) ((x) & (~BITS_FWCMDQ_TXBD_DESA_H))\n#define BIT_GET_FWCMDQ_TXBD_DESA_H(x)                                          \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_H) & BIT_MASK_FWCMDQ_TXBD_DESA_H)\n#define BIT_SET_FWCMDQ_TXBD_DESA_H(x, v)                                       \\\n\t(BIT_CLEAR_FWCMDQ_TXBD_DESA_H(x) | BIT_FWCMDQ_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI2Q_TXBD_DESA\t\t\t(Offset 0x0350) */\n\n#define BIT_SHIFT_HI2Q_TXBD_DESA 0\n#define BIT_MASK_HI2Q_TXBD_DESA 0xffffffffffffffffL\n#define BIT_HI2Q_TXBD_DESA(x)                                                  \\\n\t(((x) & BIT_MASK_HI2Q_TXBD_DESA) << BIT_SHIFT_HI2Q_TXBD_DESA)\n#define BITS_HI2Q_TXBD_DESA                                                    \\\n\t(BIT_MASK_HI2Q_TXBD_DESA << BIT_SHIFT_HI2Q_TXBD_DESA)\n#define BIT_CLEAR_HI2Q_TXBD_DESA(x) ((x) & (~BITS_HI2Q_TXBD_DESA))\n#define BIT_GET_HI2Q_TXBD_DESA(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA) & BIT_MASK_HI2Q_TXBD_DESA)\n#define BIT_SET_HI2Q_TXBD_DESA(x, v)                                           \\\n\t(BIT_CLEAR_HI2Q_TXBD_DESA(x) | BIT_HI2Q_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PCIE_HRPWM1_HCPWM1_DCPU\t\t(Offset 0x0354) */\n\n#define BIT_SHIFT_PCIE_HCPWM1_DCPU 16\n#define BIT_MASK_PCIE_HCPWM1_DCPU 0xff\n#define BIT_PCIE_HCPWM1_DCPU(x)                                                \\\n\t(((x) & BIT_MASK_PCIE_HCPWM1_DCPU) << BIT_SHIFT_PCIE_HCPWM1_DCPU)\n#define BITS_PCIE_HCPWM1_DCPU                                                  \\\n\t(BIT_MASK_PCIE_HCPWM1_DCPU << BIT_SHIFT_PCIE_HCPWM1_DCPU)\n#define BIT_CLEAR_PCIE_HCPWM1_DCPU(x) ((x) & (~BITS_PCIE_HCPWM1_DCPU))\n#define BIT_GET_PCIE_HCPWM1_DCPU(x)                                            \\\n\t(((x) >> BIT_SHIFT_PCIE_HCPWM1_DCPU) & BIT_MASK_PCIE_HCPWM1_DCPU)\n#define BIT_SET_PCIE_HCPWM1_DCPU(x, v)                                         \\\n\t(BIT_CLEAR_PCIE_HCPWM1_DCPU(x) | BIT_PCIE_HCPWM1_DCPU(v))\n\n#define BIT_SHIFT_PCIE_HRPWM1_DCPU 8\n#define BIT_MASK_PCIE_HRPWM1_DCPU 0xff\n#define BIT_PCIE_HRPWM1_DCPU(x)                                                \\\n\t(((x) & BIT_MASK_PCIE_HRPWM1_DCPU) << BIT_SHIFT_PCIE_HRPWM1_DCPU)\n#define BITS_PCIE_HRPWM1_DCPU                                                  \\\n\t(BIT_MASK_PCIE_HRPWM1_DCPU << BIT_SHIFT_PCIE_HRPWM1_DCPU)\n#define BIT_CLEAR_PCIE_HRPWM1_DCPU(x) ((x) & (~BITS_PCIE_HRPWM1_DCPU))\n#define BIT_GET_PCIE_HRPWM1_DCPU(x)                                            \\\n\t(((x) >> BIT_SHIFT_PCIE_HRPWM1_DCPU) & BIT_MASK_PCIE_HRPWM1_DCPU)\n#define BIT_SET_PCIE_HRPWM1_DCPU(x, v)                                         \\\n\t(BIT_CLEAR_PCIE_HRPWM1_DCPU(x) | BIT_PCIE_HRPWM1_DCPU(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI3Q_TXBD_DESA\t\t\t(Offset 0x0358) */\n\n#define BIT_SHIFT_HI3Q_TXBD_DESA 0\n#define BIT_MASK_HI3Q_TXBD_DESA 0xffffffffffffffffL\n#define BIT_HI3Q_TXBD_DESA(x)                                                  \\\n\t(((x) & BIT_MASK_HI3Q_TXBD_DESA) << BIT_SHIFT_HI3Q_TXBD_DESA)\n#define BITS_HI3Q_TXBD_DESA                                                    \\\n\t(BIT_MASK_HI3Q_TXBD_DESA << BIT_SHIFT_HI3Q_TXBD_DESA)\n#define BIT_CLEAR_HI3Q_TXBD_DESA(x) ((x) & (~BITS_HI3Q_TXBD_DESA))\n#define BIT_GET_HI3Q_TXBD_DESA(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA) & BIT_MASK_HI3Q_TXBD_DESA)\n#define BIT_SET_HI3Q_TXBD_DESA(x, v)                                           \\\n\t(BIT_CLEAR_HI3Q_TXBD_DESA(x) | BIT_HI3Q_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_L\t\t(Offset 0x0358) */\n\n#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L 0\n#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L 0xffffffffL\n#define BIT_P0_MPRT_BCNQ_TXBD_DESA_L(x)                                        \\\n\t(((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L)                             \\\n\t << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L)\n#define BITS_P0_MPRT_BCNQ_TXBD_DESA_L                                          \\\n\t(BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L                                     \\\n\t << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L)\n#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L(x)                                  \\\n\t((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_L))\n#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_L(x)                                    \\\n\t(((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L) &                         \\\n\t BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L)\n#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_L(x, v)                                 \\\n\t(BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L(x) |                               \\\n\t BIT_P0_MPRT_BCNQ_TXBD_DESA_L(v))\n\n/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_H\t\t(Offset 0x035C) */\n\n#define BIT_CLR_P0HI15Q_HW_IDX BIT(29)\n#define BIT_CLR_P0HI14Q_HW_IDX BIT(28)\n#define BIT_CLR_P0HI13Q_HW_IDX BIT(27)\n#define BIT_CLR_P0HI12Q_HW_IDX BIT(26)\n#define BIT_CLR_P0HI11Q_HW_IDX BIT(25)\n#define BIT_CLR_P0HI10Q_HW_IDX BIT(24)\n#define BIT_CLR_P0HI9Q_HW_IDX BIT(23)\n#define BIT_CLR_P0HI8Q_HW_IDX BIT(22)\n#define BIT_CLR_ACH7_HW_IDX BIT(21)\n#define BIT_CLR_ACH13_HW_IDX BIT(21)\n#define BIT_CLR_ACH6_HW_IDX BIT(20)\n#define BIT_CLR_ACH12_HW_IDX BIT(20)\n#define BIT_CLR_ACH5_HW_IDX BIT(19)\n#define BIT_CLR_ACH11_HW_IDX BIT(19)\n#define BIT_CLR_ACH4_HW_IDX BIT(18)\n#define BIT_CLR_ACH10_HW_IDX BIT(18)\n#define BIT_CLR_ACH9_HW_IDX BIT(17)\n#define BIT_CLR_ACH8_HW_IDX BIT(16)\n\n#define BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE 13\n#define BIT_MASK_P0_MPRT_BCNQ_DESC_MODE 0x3\n#define BIT_P0_MPRT_BCNQ_DESC_MODE(x)                                          \\\n\t(((x) & BIT_MASK_P0_MPRT_BCNQ_DESC_MODE)                               \\\n\t << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE)\n#define BITS_P0_MPRT_BCNQ_DESC_MODE                                            \\\n\t(BIT_MASK_P0_MPRT_BCNQ_DESC_MODE << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE)\n#define BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE(x)                                    \\\n\t((x) & (~BITS_P0_MPRT_BCNQ_DESC_MODE))\n#define BIT_GET_P0_MPRT_BCNQ_DESC_MODE(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE) &                           \\\n\t BIT_MASK_P0_MPRT_BCNQ_DESC_MODE)\n#define BIT_SET_P0_MPRT_BCNQ_DESC_MODE(x, v)                                   \\\n\t(BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE(x) | BIT_P0_MPRT_BCNQ_DESC_MODE(v))\n\n#define BIT_CLR_P0HI15Q_HOST_IDX BIT(13)\n#define BIT_CLR_P0HI14Q_HOST_IDX BIT(12)\n#define BIT_PCIE_P0MPRT_BCNQ4_FLAG BIT(11)\n#define BIT_CLR_P0HI13Q_HOST_IDX BIT(11)\n#define BIT_PCIE_P0MPRT_BCNQ3_FLAG BIT(10)\n#define BIT_CLR_P0HI12Q_HOST_IDX BIT(10)\n#define BIT_PCIE_P0MPRT_BCNQ2_FLAG BIT(9)\n#define BIT_CLR_P0HI11Q_HOST_IDX BIT(9)\n#define BIT_PCIE_P0MPRT_BCNQ1_FLAG BIT(8)\n#define BIT_CLR_P0HI10Q_HOST_IDX BIT(8)\n#define BIT_CLR_P0HI9Q_HOST_IDX BIT(7)\n#define BIT_CLR_P0HI8Q_HOST_IDX BIT(6)\n#define BIT_CLR_ACH7_HOST_IDX BIT(5)\n#define BIT_CLR_ACH13_HOST_IDX BIT(5)\n#define BIT_CLR_ACH6_HOST_IDX BIT(4)\n#define BIT_CLR_ACH12_HOST_IDX BIT(4)\n#define BIT_CLR_ACH5_HOST_IDX BIT(3)\n#define BIT_CLR_ACH11_HOST_IDX BIT(3)\n#define BIT_CLR_ACH4_HOST_IDX BIT(2)\n#define BIT_CLR_ACH10_HOST_IDX BIT(2)\n#define BIT_EPHY_CAL_DONE BIT(1)\n#define BIT_CLR_ACH9_HOST_IDX BIT(1)\n\n#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H 0\n#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H 0xffffffffL\n#define BIT_P0_MPRT_BCNQ_TXBD_DESA_H(x)                                        \\\n\t(((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H)                             \\\n\t << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H)\n#define BITS_P0_MPRT_BCNQ_TXBD_DESA_H                                          \\\n\t(BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H                                     \\\n\t << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H)\n#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H(x)                                  \\\n\t((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_H))\n#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_H(x)                                    \\\n\t(((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H) &                         \\\n\t BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H)\n#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_H(x, v)                                 \\\n\t(BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H(x) |                               \\\n\t BIT_P0_MPRT_BCNQ_TXBD_DESA_H(v))\n\n#define BIT_RESET_APHY BIT(0)\n#define BIT_CLR_ACH8_HOST_IDX BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI4Q_TXBD_DESA\t\t\t(Offset 0x0360) */\n\n#define BIT_SHIFT_HI4Q_TXBD_DESA 0\n#define BIT_MASK_HI4Q_TXBD_DESA 0xffffffffffffffffL\n#define BIT_HI4Q_TXBD_DESA(x)                                                  \\\n\t(((x) & BIT_MASK_HI4Q_TXBD_DESA) << BIT_SHIFT_HI4Q_TXBD_DESA)\n#define BITS_HI4Q_TXBD_DESA                                                    \\\n\t(BIT_MASK_HI4Q_TXBD_DESA << BIT_SHIFT_HI4Q_TXBD_DESA)\n#define BIT_CLEAR_HI4Q_TXBD_DESA(x) ((x) & (~BITS_HI4Q_TXBD_DESA))\n#define BIT_GET_HI4Q_TXBD_DESA(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA) & BIT_MASK_HI4Q_TXBD_DESA)\n#define BIT_SET_HI4Q_TXBD_DESA(x, v)                                           \\\n\t(BIT_CLEAR_HI4Q_TXBD_DESA(x) | BIT_HI4Q_TXBD_DESA(v))\n\n/* 2 REG_HI5Q_TXBD_DESA\t\t\t(Offset 0x0368) */\n\n#define BIT_SHIFT_HI5Q_TXBD_DESA 0\n#define BIT_MASK_HI5Q_TXBD_DESA 0xffffffffffffffffL\n#define BIT_HI5Q_TXBD_DESA(x)                                                  \\\n\t(((x) & BIT_MASK_HI5Q_TXBD_DESA) << BIT_SHIFT_HI5Q_TXBD_DESA)\n#define BITS_HI5Q_TXBD_DESA                                                    \\\n\t(BIT_MASK_HI5Q_TXBD_DESA << BIT_SHIFT_HI5Q_TXBD_DESA)\n#define BIT_CLEAR_HI5Q_TXBD_DESA(x) ((x) & (~BITS_HI5Q_TXBD_DESA))\n#define BIT_GET_HI5Q_TXBD_DESA(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA) & BIT_MASK_HI5Q_TXBD_DESA)\n#define BIT_SET_HI5Q_TXBD_DESA(x, v)                                           \\\n\t(BIT_CLEAR_HI5Q_TXBD_DESA(x) | BIT_HI5Q_TXBD_DESA(v))\n\n/* 2 REG_HI6Q_TXBD_DESA\t\t\t(Offset 0x0370) */\n\n#define BIT_SHIFT_HI6Q_TXBD_DESA 0\n#define BIT_MASK_HI6Q_TXBD_DESA 0xffffffffffffffffL\n#define BIT_HI6Q_TXBD_DESA(x)                                                  \\\n\t(((x) & BIT_MASK_HI6Q_TXBD_DESA) << BIT_SHIFT_HI6Q_TXBD_DESA)\n#define BITS_HI6Q_TXBD_DESA                                                    \\\n\t(BIT_MASK_HI6Q_TXBD_DESA << BIT_SHIFT_HI6Q_TXBD_DESA)\n#define BIT_CLEAR_HI6Q_TXBD_DESA(x) ((x) & (~BITS_HI6Q_TXBD_DESA))\n#define BIT_GET_HI6Q_TXBD_DESA(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA) & BIT_MASK_HI6Q_TXBD_DESA)\n#define BIT_SET_HI6Q_TXBD_DESA(x, v)                                           \\\n\t(BIT_CLEAR_HI6Q_TXBD_DESA(x) | BIT_HI6Q_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0MGQ_RXQ_TXRXBD_NUM\t\t(Offset 0x0378) */\n\n#define BIT_SYS_32_64_V1 BIT(31)\n\n#define BIT_SHIFT_P0BCNQ_DESC_MODE 29\n#define BIT_MASK_P0BCNQ_DESC_MODE 0x3\n#define BIT_P0BCNQ_DESC_MODE(x)                                                \\\n\t(((x) & BIT_MASK_P0BCNQ_DESC_MODE) << BIT_SHIFT_P0BCNQ_DESC_MODE)\n#define BITS_P0BCNQ_DESC_MODE                                                  \\\n\t(BIT_MASK_P0BCNQ_DESC_MODE << BIT_SHIFT_P0BCNQ_DESC_MODE)\n#define BIT_CLEAR_P0BCNQ_DESC_MODE(x) ((x) & (~BITS_P0BCNQ_DESC_MODE))\n#define BIT_GET_P0BCNQ_DESC_MODE(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0BCNQ_DESC_MODE) & BIT_MASK_P0BCNQ_DESC_MODE)\n#define BIT_SET_P0BCNQ_DESC_MODE(x, v)                                         \\\n\t(BIT_CLEAR_P0BCNQ_DESC_MODE(x) | BIT_P0BCNQ_DESC_MODE(v))\n\n#define BIT_PCIE_P0BCNQ_FLAG BIT(28)\n\n#define BIT_SHIFT_P0RXQ_DESC_NUM 16\n#define BIT_MASK_P0RXQ_DESC_NUM 0xfff\n#define BIT_P0RXQ_DESC_NUM(x)                                                  \\\n\t(((x) & BIT_MASK_P0RXQ_DESC_NUM) << BIT_SHIFT_P0RXQ_DESC_NUM)\n#define BITS_P0RXQ_DESC_NUM                                                    \\\n\t(BIT_MASK_P0RXQ_DESC_NUM << BIT_SHIFT_P0RXQ_DESC_NUM)\n#define BIT_CLEAR_P0RXQ_DESC_NUM(x) ((x) & (~BITS_P0RXQ_DESC_NUM))\n#define BIT_GET_P0RXQ_DESC_NUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_P0RXQ_DESC_NUM) & BIT_MASK_P0RXQ_DESC_NUM)\n#define BIT_SET_P0RXQ_DESC_NUM(x, v)                                           \\\n\t(BIT_CLEAR_P0RXQ_DESC_NUM(x) | BIT_P0RXQ_DESC_NUM(v))\n\n#define BIT_PCIE_P0MGQ_FLAG BIT(14)\n\n#define BIT_SHIFT_P0MGQ_DESC_MODE 12\n#define BIT_MASK_P0MGQ_DESC_MODE 0x3\n#define BIT_P0MGQ_DESC_MODE(x)                                                 \\\n\t(((x) & BIT_MASK_P0MGQ_DESC_MODE) << BIT_SHIFT_P0MGQ_DESC_MODE)\n#define BITS_P0MGQ_DESC_MODE                                                   \\\n\t(BIT_MASK_P0MGQ_DESC_MODE << BIT_SHIFT_P0MGQ_DESC_MODE)\n#define BIT_CLEAR_P0MGQ_DESC_MODE(x) ((x) & (~BITS_P0MGQ_DESC_MODE))\n#define BIT_GET_P0MGQ_DESC_MODE(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0MGQ_DESC_MODE) & BIT_MASK_P0MGQ_DESC_MODE)\n#define BIT_SET_P0MGQ_DESC_MODE(x, v)                                          \\\n\t(BIT_CLEAR_P0MGQ_DESC_MODE(x) | BIT_P0MGQ_DESC_MODE(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI7Q_TXBD_DESA\t\t\t(Offset 0x0378) */\n\n#define BIT_SHIFT_HI7Q_TXBD_DESA 0\n#define BIT_MASK_HI7Q_TXBD_DESA 0xffffffffffffffffL\n#define BIT_HI7Q_TXBD_DESA(x)                                                  \\\n\t(((x) & BIT_MASK_HI7Q_TXBD_DESA) << BIT_SHIFT_HI7Q_TXBD_DESA)\n#define BITS_HI7Q_TXBD_DESA                                                    \\\n\t(BIT_MASK_HI7Q_TXBD_DESA << BIT_SHIFT_HI7Q_TXBD_DESA)\n#define BIT_CLEAR_HI7Q_TXBD_DESA(x) ((x) & (~BITS_HI7Q_TXBD_DESA))\n#define BIT_GET_HI7Q_TXBD_DESA(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA) & BIT_MASK_HI7Q_TXBD_DESA)\n#define BIT_SET_HI7Q_TXBD_DESA(x, v)                                           \\\n\t(BIT_CLEAR_HI7Q_TXBD_DESA(x) | BIT_HI7Q_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0MGQ_RXQ_TXRXBD_NUM\t\t(Offset 0x0378) */\n\n#define BIT_SHIFT_P0MGQ_DESC_NUM 0\n#define BIT_MASK_P0MGQ_DESC_NUM 0xfff\n#define BIT_P0MGQ_DESC_NUM(x)                                                  \\\n\t(((x) & BIT_MASK_P0MGQ_DESC_NUM) << BIT_SHIFT_P0MGQ_DESC_NUM)\n#define BITS_P0MGQ_DESC_NUM                                                    \\\n\t(BIT_MASK_P0MGQ_DESC_NUM << BIT_SHIFT_P0MGQ_DESC_NUM)\n#define BIT_CLEAR_P0MGQ_DESC_NUM(x) ((x) & (~BITS_P0MGQ_DESC_NUM))\n#define BIT_GET_P0MGQ_DESC_NUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_P0MGQ_DESC_NUM) & BIT_MASK_P0MGQ_DESC_NUM)\n#define BIT_SET_P0MGQ_DESC_NUM(x, v)                                           \\\n\t(BIT_CLEAR_P0MGQ_DESC_NUM(x) | BIT_P0MGQ_DESC_NUM(v))\n\n/* 2 REG_CHNL_DMA_CFG\t\t\t(Offset 0x037C) */\n\n#define BIT_TXHCI_EN BIT(26)\n#define BIT_TXHCI_IDLE BIT(25)\n#define BIT_DMA_PRI_EN BIT(24)\n#define BIT_PCIE_FWCMDQ_FLAG BIT(14)\n\n#define BIT_SHIFT_FWCMDQ_DESC_MODE 12\n#define BIT_MASK_FWCMDQ_DESC_MODE 0x3\n#define BIT_FWCMDQ_DESC_MODE(x)                                                \\\n\t(((x) & BIT_MASK_FWCMDQ_DESC_MODE) << BIT_SHIFT_FWCMDQ_DESC_MODE)\n#define BITS_FWCMDQ_DESC_MODE                                                  \\\n\t(BIT_MASK_FWCMDQ_DESC_MODE << BIT_SHIFT_FWCMDQ_DESC_MODE)\n#define BIT_CLEAR_FWCMDQ_DESC_MODE(x) ((x) & (~BITS_FWCMDQ_DESC_MODE))\n#define BIT_GET_FWCMDQ_DESC_MODE(x)                                            \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_DESC_MODE) & BIT_MASK_FWCMDQ_DESC_MODE)\n#define BIT_SET_FWCMDQ_DESC_MODE(x, v)                                         \\\n\t(BIT_CLEAR_FWCMDQ_DESC_MODE(x) | BIT_FWCMDQ_DESC_MODE(v))\n\n#define BIT_SHIFT_FWCMDQ_DESC_NUM 0\n#define BIT_MASK_FWCMDQ_DESC_NUM 0xfff\n#define BIT_FWCMDQ_DESC_NUM(x)                                                 \\\n\t(((x) & BIT_MASK_FWCMDQ_DESC_NUM) << BIT_SHIFT_FWCMDQ_DESC_NUM)\n#define BITS_FWCMDQ_DESC_NUM                                                   \\\n\t(BIT_MASK_FWCMDQ_DESC_NUM << BIT_SHIFT_FWCMDQ_DESC_NUM)\n#define BIT_CLEAR_FWCMDQ_DESC_NUM(x) ((x) & (~BITS_FWCMDQ_DESC_NUM))\n#define BIT_GET_FWCMDQ_DESC_NUM(x)                                             \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_DESC_NUM) & BIT_MASK_FWCMDQ_DESC_NUM)\n#define BIT_SET_FWCMDQ_DESC_NUM(x, v)                                          \\\n\t(BIT_CLEAR_FWCMDQ_DESC_NUM(x) | BIT_FWCMDQ_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MGQ_TXBD_NUM\t\t\t(Offset 0x0380) */\n\n#define BIT_PCIE_MGQ_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_MGQ_TXBD_NUM\t\t\t(Offset 0x0380) */\n\n#define BIT_HCI_MGQ_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MGQ_TXBD_NUM\t\t\t(Offset 0x0380) */\n\n#define BIT_SHIFT_MGQ_DESC_MODE 12\n#define BIT_MASK_MGQ_DESC_MODE 0x3\n#define BIT_MGQ_DESC_MODE(x)                                                   \\\n\t(((x) & BIT_MASK_MGQ_DESC_MODE) << BIT_SHIFT_MGQ_DESC_MODE)\n#define BITS_MGQ_DESC_MODE (BIT_MASK_MGQ_DESC_MODE << BIT_SHIFT_MGQ_DESC_MODE)\n#define BIT_CLEAR_MGQ_DESC_MODE(x) ((x) & (~BITS_MGQ_DESC_MODE))\n#define BIT_GET_MGQ_DESC_MODE(x)                                               \\\n\t(((x) >> BIT_SHIFT_MGQ_DESC_MODE) & BIT_MASK_MGQ_DESC_MODE)\n#define BIT_SET_MGQ_DESC_MODE(x, v)                                            \\\n\t(BIT_CLEAR_MGQ_DESC_MODE(x) | BIT_MGQ_DESC_MODE(v))\n\n#define BIT_SHIFT_MGQ_DESC_NUM 0\n#define BIT_MASK_MGQ_DESC_NUM 0xfff\n#define BIT_MGQ_DESC_NUM(x)                                                    \\\n\t(((x) & BIT_MASK_MGQ_DESC_NUM) << BIT_SHIFT_MGQ_DESC_NUM)\n#define BITS_MGQ_DESC_NUM (BIT_MASK_MGQ_DESC_NUM << BIT_SHIFT_MGQ_DESC_NUM)\n#define BIT_CLEAR_MGQ_DESC_NUM(x) ((x) & (~BITS_MGQ_DESC_NUM))\n#define BIT_GET_MGQ_DESC_NUM(x)                                                \\\n\t(((x) >> BIT_SHIFT_MGQ_DESC_NUM) & BIT_MASK_MGQ_DESC_NUM)\n#define BIT_SET_MGQ_DESC_NUM(x, v)                                             \\\n\t(BIT_CLEAR_MGQ_DESC_NUM(x) | BIT_MGQ_DESC_NUM(v))\n\n/* 2 REG_RX_RXBD_NUM\t\t\t\t(Offset 0x0382) */\n\n#define BIT_SYS_32_64 BIT(15)\n\n#define BIT_SHIFT_BCNQ_DESC_MODE 13\n#define BIT_MASK_BCNQ_DESC_MODE 0x3\n#define BIT_BCNQ_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_BCNQ_DESC_MODE) << BIT_SHIFT_BCNQ_DESC_MODE)\n#define BITS_BCNQ_DESC_MODE                                                    \\\n\t(BIT_MASK_BCNQ_DESC_MODE << BIT_SHIFT_BCNQ_DESC_MODE)\n#define BIT_CLEAR_BCNQ_DESC_MODE(x) ((x) & (~BITS_BCNQ_DESC_MODE))\n#define BIT_GET_BCNQ_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_BCNQ_DESC_MODE) & BIT_MASK_BCNQ_DESC_MODE)\n#define BIT_SET_BCNQ_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_BCNQ_DESC_MODE(x) | BIT_BCNQ_DESC_MODE(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RX_RXBD_NUM\t\t\t\t(Offset 0x0382) */\n\n#define BIT_PCIE_BCNQ_FLAG BIT(12)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RX_RXBD_NUM\t\t\t\t(Offset 0x0382) */\n\n#define BIT_HCI_BCNQ_FLAG BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RX_RXBD_NUM\t\t\t\t(Offset 0x0382) */\n\n#define BIT_SHIFT_RXQ_DESC_NUM 0\n#define BIT_MASK_RXQ_DESC_NUM 0xfff\n#define BIT_RXQ_DESC_NUM(x)                                                    \\\n\t(((x) & BIT_MASK_RXQ_DESC_NUM) << BIT_SHIFT_RXQ_DESC_NUM)\n#define BITS_RXQ_DESC_NUM (BIT_MASK_RXQ_DESC_NUM << BIT_SHIFT_RXQ_DESC_NUM)\n#define BIT_CLEAR_RXQ_DESC_NUM(x) ((x) & (~BITS_RXQ_DESC_NUM))\n#define BIT_GET_RXQ_DESC_NUM(x)                                                \\\n\t(((x) >> BIT_SHIFT_RXQ_DESC_NUM) & BIT_MASK_RXQ_DESC_NUM)\n#define BIT_SET_RXQ_DESC_NUM(x, v)                                             \\\n\t(BIT_CLEAR_RXQ_DESC_NUM(x) | BIT_RXQ_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH0_ACH1_TXBD_NUM\t\t\t(Offset 0x0384) */\n\n#define BIT_PCIE_ACH1_FLAG_V1 BIT(30)\n\n#define BIT_SHIFT_ACH1_DESC_MODE_V1 28\n#define BIT_MASK_ACH1_DESC_MODE_V1 0x3\n#define BIT_ACH1_DESC_MODE_V1(x)                                               \\\n\t(((x) & BIT_MASK_ACH1_DESC_MODE_V1) << BIT_SHIFT_ACH1_DESC_MODE_V1)\n#define BITS_ACH1_DESC_MODE_V1                                                 \\\n\t(BIT_MASK_ACH1_DESC_MODE_V1 << BIT_SHIFT_ACH1_DESC_MODE_V1)\n#define BIT_CLEAR_ACH1_DESC_MODE_V1(x) ((x) & (~BITS_ACH1_DESC_MODE_V1))\n#define BIT_GET_ACH1_DESC_MODE_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH1_DESC_MODE_V1) & BIT_MASK_ACH1_DESC_MODE_V1)\n#define BIT_SET_ACH1_DESC_MODE_V1(x, v)                                        \\\n\t(BIT_CLEAR_ACH1_DESC_MODE_V1(x) | BIT_ACH1_DESC_MODE_V1(v))\n\n#define BIT_SHIFT_ACH1_DESC_NUM_V1 16\n#define BIT_MASK_ACH1_DESC_NUM_V1 0xfff\n#define BIT_ACH1_DESC_NUM_V1(x)                                                \\\n\t(((x) & BIT_MASK_ACH1_DESC_NUM_V1) << BIT_SHIFT_ACH1_DESC_NUM_V1)\n#define BITS_ACH1_DESC_NUM_V1                                                  \\\n\t(BIT_MASK_ACH1_DESC_NUM_V1 << BIT_SHIFT_ACH1_DESC_NUM_V1)\n#define BIT_CLEAR_ACH1_DESC_NUM_V1(x) ((x) & (~BITS_ACH1_DESC_NUM_V1))\n#define BIT_GET_ACH1_DESC_NUM_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH1_DESC_NUM_V1) & BIT_MASK_ACH1_DESC_NUM_V1)\n#define BIT_SET_ACH1_DESC_NUM_V1(x, v)                                         \\\n\t(BIT_CLEAR_ACH1_DESC_NUM_V1(x) | BIT_ACH1_DESC_NUM_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_VOQ_TXBD_NUM\t\t\t(Offset 0x0384) */\n\n#define BIT_PCIE_VOQ_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_VOQ_TXBD_NUM\t\t\t(Offset 0x0384) */\n\n#define BIT_HCI_VOQ_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH0_ACH1_TXBD_NUM\t\t\t(Offset 0x0384) */\n\n#define BIT_PCIE_ACH0_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_VOQ_TXBD_NUM\t\t\t(Offset 0x0384) */\n\n#define BIT_SHIFT_VOQ_DESC_MODE 12\n#define BIT_MASK_VOQ_DESC_MODE 0x3\n#define BIT_VOQ_DESC_MODE(x)                                                   \\\n\t(((x) & BIT_MASK_VOQ_DESC_MODE) << BIT_SHIFT_VOQ_DESC_MODE)\n#define BITS_VOQ_DESC_MODE (BIT_MASK_VOQ_DESC_MODE << BIT_SHIFT_VOQ_DESC_MODE)\n#define BIT_CLEAR_VOQ_DESC_MODE(x) ((x) & (~BITS_VOQ_DESC_MODE))\n#define BIT_GET_VOQ_DESC_MODE(x)                                               \\\n\t(((x) >> BIT_SHIFT_VOQ_DESC_MODE) & BIT_MASK_VOQ_DESC_MODE)\n#define BIT_SET_VOQ_DESC_MODE(x, v)                                            \\\n\t(BIT_CLEAR_VOQ_DESC_MODE(x) | BIT_VOQ_DESC_MODE(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH0_ACH1_TXBD_NUM\t\t\t(Offset 0x0384) */\n\n#define BIT_SHIFT_ACH0_DESC_MODE 12\n#define BIT_MASK_ACH0_DESC_MODE 0x3\n#define BIT_ACH0_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_ACH0_DESC_MODE) << BIT_SHIFT_ACH0_DESC_MODE)\n#define BITS_ACH0_DESC_MODE                                                    \\\n\t(BIT_MASK_ACH0_DESC_MODE << BIT_SHIFT_ACH0_DESC_MODE)\n#define BIT_CLEAR_ACH0_DESC_MODE(x) ((x) & (~BITS_ACH0_DESC_MODE))\n#define BIT_GET_ACH0_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_ACH0_DESC_MODE) & BIT_MASK_ACH0_DESC_MODE)\n#define BIT_SET_ACH0_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_ACH0_DESC_MODE(x) | BIT_ACH0_DESC_MODE(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_VOQ_TXBD_NUM\t\t\t(Offset 0x0384) */\n\n#define BIT_SHIFT_VOQ_DESC_NUM 0\n#define BIT_MASK_VOQ_DESC_NUM 0xfff\n#define BIT_VOQ_DESC_NUM(x)                                                    \\\n\t(((x) & BIT_MASK_VOQ_DESC_NUM) << BIT_SHIFT_VOQ_DESC_NUM)\n#define BITS_VOQ_DESC_NUM (BIT_MASK_VOQ_DESC_NUM << BIT_SHIFT_VOQ_DESC_NUM)\n#define BIT_CLEAR_VOQ_DESC_NUM(x) ((x) & (~BITS_VOQ_DESC_NUM))\n#define BIT_GET_VOQ_DESC_NUM(x)                                                \\\n\t(((x) >> BIT_SHIFT_VOQ_DESC_NUM) & BIT_MASK_VOQ_DESC_NUM)\n#define BIT_SET_VOQ_DESC_NUM(x, v)                                             \\\n\t(BIT_CLEAR_VOQ_DESC_NUM(x) | BIT_VOQ_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH0_ACH1_TXBD_NUM\t\t\t(Offset 0x0384) */\n\n#define BIT_SHIFT_ACH0_DESC_NUM 0\n#define BIT_MASK_ACH0_DESC_NUM 0xfff\n#define BIT_ACH0_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_ACH0_DESC_NUM) << BIT_SHIFT_ACH0_DESC_NUM)\n#define BITS_ACH0_DESC_NUM (BIT_MASK_ACH0_DESC_NUM << BIT_SHIFT_ACH0_DESC_NUM)\n#define BIT_CLEAR_ACH0_DESC_NUM(x) ((x) & (~BITS_ACH0_DESC_NUM))\n#define BIT_GET_ACH0_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH0_DESC_NUM) & BIT_MASK_ACH0_DESC_NUM)\n#define BIT_SET_ACH0_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_ACH0_DESC_NUM(x) | BIT_ACH0_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_VIQ_TXBD_NUM\t\t\t(Offset 0x0386) */\n\n#define BIT_PCIE_VIQ_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_VIQ_TXBD_NUM\t\t\t(Offset 0x0386) */\n\n#define BIT_HCI_VIQ_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_VIQ_TXBD_NUM\t\t\t(Offset 0x0386) */\n\n#define BIT_SHIFT_VIQ_DESC_MODE 12\n#define BIT_MASK_VIQ_DESC_MODE 0x3\n#define BIT_VIQ_DESC_MODE(x)                                                   \\\n\t(((x) & BIT_MASK_VIQ_DESC_MODE) << BIT_SHIFT_VIQ_DESC_MODE)\n#define BITS_VIQ_DESC_MODE (BIT_MASK_VIQ_DESC_MODE << BIT_SHIFT_VIQ_DESC_MODE)\n#define BIT_CLEAR_VIQ_DESC_MODE(x) ((x) & (~BITS_VIQ_DESC_MODE))\n#define BIT_GET_VIQ_DESC_MODE(x)                                               \\\n\t(((x) >> BIT_SHIFT_VIQ_DESC_MODE) & BIT_MASK_VIQ_DESC_MODE)\n#define BIT_SET_VIQ_DESC_MODE(x, v)                                            \\\n\t(BIT_CLEAR_VIQ_DESC_MODE(x) | BIT_VIQ_DESC_MODE(v))\n\n#define BIT_SHIFT_VIQ_DESC_NUM 0\n#define BIT_MASK_VIQ_DESC_NUM 0xfff\n#define BIT_VIQ_DESC_NUM(x)                                                    \\\n\t(((x) & BIT_MASK_VIQ_DESC_NUM) << BIT_SHIFT_VIQ_DESC_NUM)\n#define BITS_VIQ_DESC_NUM (BIT_MASK_VIQ_DESC_NUM << BIT_SHIFT_VIQ_DESC_NUM)\n#define BIT_CLEAR_VIQ_DESC_NUM(x) ((x) & (~BITS_VIQ_DESC_NUM))\n#define BIT_GET_VIQ_DESC_NUM(x)                                                \\\n\t(((x) >> BIT_SHIFT_VIQ_DESC_NUM) & BIT_MASK_VIQ_DESC_NUM)\n#define BIT_SET_VIQ_DESC_NUM(x, v)                                             \\\n\t(BIT_CLEAR_VIQ_DESC_NUM(x) | BIT_VIQ_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH2_ACH3_TXBD_NUM\t\t\t(Offset 0x0388) */\n\n#define BIT_PCIE_ACH3_FLAG_V1 BIT(30)\n\n#define BIT_SHIFT_ACH3_DESC_MODE_V1 28\n#define BIT_MASK_ACH3_DESC_MODE_V1 0x3\n#define BIT_ACH3_DESC_MODE_V1(x)                                               \\\n\t(((x) & BIT_MASK_ACH3_DESC_MODE_V1) << BIT_SHIFT_ACH3_DESC_MODE_V1)\n#define BITS_ACH3_DESC_MODE_V1                                                 \\\n\t(BIT_MASK_ACH3_DESC_MODE_V1 << BIT_SHIFT_ACH3_DESC_MODE_V1)\n#define BIT_CLEAR_ACH3_DESC_MODE_V1(x) ((x) & (~BITS_ACH3_DESC_MODE_V1))\n#define BIT_GET_ACH3_DESC_MODE_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH3_DESC_MODE_V1) & BIT_MASK_ACH3_DESC_MODE_V1)\n#define BIT_SET_ACH3_DESC_MODE_V1(x, v)                                        \\\n\t(BIT_CLEAR_ACH3_DESC_MODE_V1(x) | BIT_ACH3_DESC_MODE_V1(v))\n\n#define BIT_SHIFT_ACH3_DESC_NUM_V1 16\n#define BIT_MASK_ACH3_DESC_NUM_V1 0xfff\n#define BIT_ACH3_DESC_NUM_V1(x)                                                \\\n\t(((x) & BIT_MASK_ACH3_DESC_NUM_V1) << BIT_SHIFT_ACH3_DESC_NUM_V1)\n#define BITS_ACH3_DESC_NUM_V1                                                  \\\n\t(BIT_MASK_ACH3_DESC_NUM_V1 << BIT_SHIFT_ACH3_DESC_NUM_V1)\n#define BIT_CLEAR_ACH3_DESC_NUM_V1(x) ((x) & (~BITS_ACH3_DESC_NUM_V1))\n#define BIT_GET_ACH3_DESC_NUM_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH3_DESC_NUM_V1) & BIT_MASK_ACH3_DESC_NUM_V1)\n#define BIT_SET_ACH3_DESC_NUM_V1(x, v)                                         \\\n\t(BIT_CLEAR_ACH3_DESC_NUM_V1(x) | BIT_ACH3_DESC_NUM_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BEQ_TXBD_NUM\t\t\t(Offset 0x0388) */\n\n#define BIT_PCIE_BEQ_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_BEQ_TXBD_NUM\t\t\t(Offset 0x0388) */\n\n#define BIT_HCI_BEQ_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH2_ACH3_TXBD_NUM\t\t\t(Offset 0x0388) */\n\n#define BIT_PCIE_ACH2_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BEQ_TXBD_NUM\t\t\t(Offset 0x0388) */\n\n#define BIT_SHIFT_BEQ_DESC_MODE 12\n#define BIT_MASK_BEQ_DESC_MODE 0x3\n#define BIT_BEQ_DESC_MODE(x)                                                   \\\n\t(((x) & BIT_MASK_BEQ_DESC_MODE) << BIT_SHIFT_BEQ_DESC_MODE)\n#define BITS_BEQ_DESC_MODE (BIT_MASK_BEQ_DESC_MODE << BIT_SHIFT_BEQ_DESC_MODE)\n#define BIT_CLEAR_BEQ_DESC_MODE(x) ((x) & (~BITS_BEQ_DESC_MODE))\n#define BIT_GET_BEQ_DESC_MODE(x)                                               \\\n\t(((x) >> BIT_SHIFT_BEQ_DESC_MODE) & BIT_MASK_BEQ_DESC_MODE)\n#define BIT_SET_BEQ_DESC_MODE(x, v)                                            \\\n\t(BIT_CLEAR_BEQ_DESC_MODE(x) | BIT_BEQ_DESC_MODE(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH2_ACH3_TXBD_NUM\t\t\t(Offset 0x0388) */\n\n#define BIT_SHIFT_ACH2_DESC_MODE 12\n#define BIT_MASK_ACH2_DESC_MODE 0x3\n#define BIT_ACH2_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_ACH2_DESC_MODE) << BIT_SHIFT_ACH2_DESC_MODE)\n#define BITS_ACH2_DESC_MODE                                                    \\\n\t(BIT_MASK_ACH2_DESC_MODE << BIT_SHIFT_ACH2_DESC_MODE)\n#define BIT_CLEAR_ACH2_DESC_MODE(x) ((x) & (~BITS_ACH2_DESC_MODE))\n#define BIT_GET_ACH2_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_ACH2_DESC_MODE) & BIT_MASK_ACH2_DESC_MODE)\n#define BIT_SET_ACH2_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_ACH2_DESC_MODE(x) | BIT_ACH2_DESC_MODE(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BEQ_TXBD_NUM\t\t\t(Offset 0x0388) */\n\n#define BIT_SHIFT_BEQ_DESC_NUM 0\n#define BIT_MASK_BEQ_DESC_NUM 0xfff\n#define BIT_BEQ_DESC_NUM(x)                                                    \\\n\t(((x) & BIT_MASK_BEQ_DESC_NUM) << BIT_SHIFT_BEQ_DESC_NUM)\n#define BITS_BEQ_DESC_NUM (BIT_MASK_BEQ_DESC_NUM << BIT_SHIFT_BEQ_DESC_NUM)\n#define BIT_CLEAR_BEQ_DESC_NUM(x) ((x) & (~BITS_BEQ_DESC_NUM))\n#define BIT_GET_BEQ_DESC_NUM(x)                                                \\\n\t(((x) >> BIT_SHIFT_BEQ_DESC_NUM) & BIT_MASK_BEQ_DESC_NUM)\n#define BIT_SET_BEQ_DESC_NUM(x, v)                                             \\\n\t(BIT_CLEAR_BEQ_DESC_NUM(x) | BIT_BEQ_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH2_ACH3_TXBD_NUM\t\t\t(Offset 0x0388) */\n\n#define BIT_SHIFT_ACH2_DESC_NUM 0\n#define BIT_MASK_ACH2_DESC_NUM 0xfff\n#define BIT_ACH2_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_ACH2_DESC_NUM) << BIT_SHIFT_ACH2_DESC_NUM)\n#define BITS_ACH2_DESC_NUM (BIT_MASK_ACH2_DESC_NUM << BIT_SHIFT_ACH2_DESC_NUM)\n#define BIT_CLEAR_ACH2_DESC_NUM(x) ((x) & (~BITS_ACH2_DESC_NUM))\n#define BIT_GET_ACH2_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH2_DESC_NUM) & BIT_MASK_ACH2_DESC_NUM)\n#define BIT_SET_ACH2_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_ACH2_DESC_NUM(x) | BIT_ACH2_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BKQ_TXBD_NUM\t\t\t(Offset 0x038A) */\n\n#define BIT_PCIE_BKQ_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_BKQ_TXBD_NUM\t\t\t(Offset 0x038A) */\n\n#define BIT_HCI_BKQ_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BKQ_TXBD_NUM\t\t\t(Offset 0x038A) */\n\n#define BIT_SHIFT_BKQ_DESC_MODE 12\n#define BIT_MASK_BKQ_DESC_MODE 0x3\n#define BIT_BKQ_DESC_MODE(x)                                                   \\\n\t(((x) & BIT_MASK_BKQ_DESC_MODE) << BIT_SHIFT_BKQ_DESC_MODE)\n#define BITS_BKQ_DESC_MODE (BIT_MASK_BKQ_DESC_MODE << BIT_SHIFT_BKQ_DESC_MODE)\n#define BIT_CLEAR_BKQ_DESC_MODE(x) ((x) & (~BITS_BKQ_DESC_MODE))\n#define BIT_GET_BKQ_DESC_MODE(x)                                               \\\n\t(((x) >> BIT_SHIFT_BKQ_DESC_MODE) & BIT_MASK_BKQ_DESC_MODE)\n#define BIT_SET_BKQ_DESC_MODE(x, v)                                            \\\n\t(BIT_CLEAR_BKQ_DESC_MODE(x) | BIT_BKQ_DESC_MODE(v))\n\n#define BIT_SHIFT_BKQ_DESC_NUM 0\n#define BIT_MASK_BKQ_DESC_NUM 0xfff\n#define BIT_BKQ_DESC_NUM(x)                                                    \\\n\t(((x) & BIT_MASK_BKQ_DESC_NUM) << BIT_SHIFT_BKQ_DESC_NUM)\n#define BITS_BKQ_DESC_NUM (BIT_MASK_BKQ_DESC_NUM << BIT_SHIFT_BKQ_DESC_NUM)\n#define BIT_CLEAR_BKQ_DESC_NUM(x) ((x) & (~BITS_BKQ_DESC_NUM))\n#define BIT_GET_BKQ_DESC_NUM(x)                                                \\\n\t(((x) >> BIT_SHIFT_BKQ_DESC_NUM) & BIT_MASK_BKQ_DESC_NUM)\n#define BIT_SET_BKQ_DESC_NUM(x, v)                                             \\\n\t(BIT_CLEAR_BKQ_DESC_NUM(x) | BIT_BKQ_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM\t\t(Offset 0x038C) */\n\n#define BIT_P0HI1Q_FLAG BIT(30)\n\n#define BIT_SHIFT_P0HI1Q_DESC_MODE 28\n#define BIT_MASK_P0HI1Q_DESC_MODE 0x3\n#define BIT_P0HI1Q_DESC_MODE(x)                                                \\\n\t(((x) & BIT_MASK_P0HI1Q_DESC_MODE) << BIT_SHIFT_P0HI1Q_DESC_MODE)\n#define BITS_P0HI1Q_DESC_MODE                                                  \\\n\t(BIT_MASK_P0HI1Q_DESC_MODE << BIT_SHIFT_P0HI1Q_DESC_MODE)\n#define BIT_CLEAR_P0HI1Q_DESC_MODE(x) ((x) & (~BITS_P0HI1Q_DESC_MODE))\n#define BIT_GET_P0HI1Q_DESC_MODE(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI1Q_DESC_MODE) & BIT_MASK_P0HI1Q_DESC_MODE)\n#define BIT_SET_P0HI1Q_DESC_MODE(x, v)                                         \\\n\t(BIT_CLEAR_P0HI1Q_DESC_MODE(x) | BIT_P0HI1Q_DESC_MODE(v))\n\n#define BIT_SHIFT_P0HI1Q_DESC_NUM 16\n#define BIT_MASK_P0HI1Q_DESC_NUM 0xfff\n#define BIT_P0HI1Q_DESC_NUM(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI1Q_DESC_NUM) << BIT_SHIFT_P0HI1Q_DESC_NUM)\n#define BITS_P0HI1Q_DESC_NUM                                                   \\\n\t(BIT_MASK_P0HI1Q_DESC_NUM << BIT_SHIFT_P0HI1Q_DESC_NUM)\n#define BIT_CLEAR_P0HI1Q_DESC_NUM(x) ((x) & (~BITS_P0HI1Q_DESC_NUM))\n#define BIT_GET_P0HI1Q_DESC_NUM(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI1Q_DESC_NUM) & BIT_MASK_P0HI1Q_DESC_NUM)\n#define BIT_SET_P0HI1Q_DESC_NUM(x, v)                                          \\\n\t(BIT_CLEAR_P0HI1Q_DESC_NUM(x) | BIT_P0HI1Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI0Q_TXBD_NUM\t\t\t(Offset 0x038C) */\n\n#define BIT_HI0Q_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM\t\t(Offset 0x038C) */\n\n#define BIT_P0HI0Q_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI0Q_TXBD_NUM\t\t\t(Offset 0x038C) */\n\n#define BIT_SHIFT_HI0Q_DESC_MODE 12\n#define BIT_MASK_HI0Q_DESC_MODE 0x3\n#define BIT_HI0Q_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_HI0Q_DESC_MODE) << BIT_SHIFT_HI0Q_DESC_MODE)\n#define BITS_HI0Q_DESC_MODE                                                    \\\n\t(BIT_MASK_HI0Q_DESC_MODE << BIT_SHIFT_HI0Q_DESC_MODE)\n#define BIT_CLEAR_HI0Q_DESC_MODE(x) ((x) & (~BITS_HI0Q_DESC_MODE))\n#define BIT_GET_HI0Q_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI0Q_DESC_MODE) & BIT_MASK_HI0Q_DESC_MODE)\n#define BIT_SET_HI0Q_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_HI0Q_DESC_MODE(x) | BIT_HI0Q_DESC_MODE(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM\t\t(Offset 0x038C) */\n\n#define BIT_SHIFT_P0HI0Q_DESC_MODE 12\n#define BIT_MASK_P0HI0Q_DESC_MODE 0x3\n#define BIT_P0HI0Q_DESC_MODE(x)                                                \\\n\t(((x) & BIT_MASK_P0HI0Q_DESC_MODE) << BIT_SHIFT_P0HI0Q_DESC_MODE)\n#define BITS_P0HI0Q_DESC_MODE                                                  \\\n\t(BIT_MASK_P0HI0Q_DESC_MODE << BIT_SHIFT_P0HI0Q_DESC_MODE)\n#define BIT_CLEAR_P0HI0Q_DESC_MODE(x) ((x) & (~BITS_P0HI0Q_DESC_MODE))\n#define BIT_GET_P0HI0Q_DESC_MODE(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI0Q_DESC_MODE) & BIT_MASK_P0HI0Q_DESC_MODE)\n#define BIT_SET_P0HI0Q_DESC_MODE(x, v)                                         \\\n\t(BIT_CLEAR_P0HI0Q_DESC_MODE(x) | BIT_P0HI0Q_DESC_MODE(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI0Q_TXBD_NUM\t\t\t(Offset 0x038C) */\n\n#define BIT_SHIFT_HI0Q_DESC_NUM 0\n#define BIT_MASK_HI0Q_DESC_NUM 0xfff\n#define BIT_HI0Q_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_HI0Q_DESC_NUM) << BIT_SHIFT_HI0Q_DESC_NUM)\n#define BITS_HI0Q_DESC_NUM (BIT_MASK_HI0Q_DESC_NUM << BIT_SHIFT_HI0Q_DESC_NUM)\n#define BIT_CLEAR_HI0Q_DESC_NUM(x) ((x) & (~BITS_HI0Q_DESC_NUM))\n#define BIT_GET_HI0Q_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI0Q_DESC_NUM) & BIT_MASK_HI0Q_DESC_NUM)\n#define BIT_SET_HI0Q_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_HI0Q_DESC_NUM(x) | BIT_HI0Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM\t\t(Offset 0x038C) */\n\n#define BIT_SHIFT_P0HI0Q_DESC_NUM 0\n#define BIT_MASK_P0HI0Q_DESC_NUM 0xfff\n#define BIT_P0HI0Q_DESC_NUM(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI0Q_DESC_NUM) << BIT_SHIFT_P0HI0Q_DESC_NUM)\n#define BITS_P0HI0Q_DESC_NUM                                                   \\\n\t(BIT_MASK_P0HI0Q_DESC_NUM << BIT_SHIFT_P0HI0Q_DESC_NUM)\n#define BIT_CLEAR_P0HI0Q_DESC_NUM(x) ((x) & (~BITS_P0HI0Q_DESC_NUM))\n#define BIT_GET_P0HI0Q_DESC_NUM(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI0Q_DESC_NUM) & BIT_MASK_P0HI0Q_DESC_NUM)\n#define BIT_SET_P0HI0Q_DESC_NUM(x, v)                                          \\\n\t(BIT_CLEAR_P0HI0Q_DESC_NUM(x) | BIT_P0HI0Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI1Q_TXBD_NUM\t\t\t(Offset 0x038E) */\n\n#define BIT_HI1Q_FLAG BIT(14)\n\n#define BIT_SHIFT_HI1Q_DESC_MODE 12\n#define BIT_MASK_HI1Q_DESC_MODE 0x3\n#define BIT_HI1Q_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_HI1Q_DESC_MODE) << BIT_SHIFT_HI1Q_DESC_MODE)\n#define BITS_HI1Q_DESC_MODE                                                    \\\n\t(BIT_MASK_HI1Q_DESC_MODE << BIT_SHIFT_HI1Q_DESC_MODE)\n#define BIT_CLEAR_HI1Q_DESC_MODE(x) ((x) & (~BITS_HI1Q_DESC_MODE))\n#define BIT_GET_HI1Q_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI1Q_DESC_MODE) & BIT_MASK_HI1Q_DESC_MODE)\n#define BIT_SET_HI1Q_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_HI1Q_DESC_MODE(x) | BIT_HI1Q_DESC_MODE(v))\n\n#define BIT_SHIFT_HI1Q_DESC_NUM 0\n#define BIT_MASK_HI1Q_DESC_NUM 0xfff\n#define BIT_HI1Q_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_HI1Q_DESC_NUM) << BIT_SHIFT_HI1Q_DESC_NUM)\n#define BITS_HI1Q_DESC_NUM (BIT_MASK_HI1Q_DESC_NUM << BIT_SHIFT_HI1Q_DESC_NUM)\n#define BIT_CLEAR_HI1Q_DESC_NUM(x) ((x) & (~BITS_HI1Q_DESC_NUM))\n#define BIT_GET_HI1Q_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI1Q_DESC_NUM) & BIT_MASK_HI1Q_DESC_NUM)\n#define BIT_SET_HI1Q_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_HI1Q_DESC_NUM(x) | BIT_HI1Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM\t\t(Offset 0x0390) */\n\n#define BIT_P0HI3Q_FLAG BIT(30)\n\n#define BIT_SHIFT_P0HI3Q_DESC_MODE 28\n#define BIT_MASK_P0HI3Q_DESC_MODE 0x3\n#define BIT_P0HI3Q_DESC_MODE(x)                                                \\\n\t(((x) & BIT_MASK_P0HI3Q_DESC_MODE) << BIT_SHIFT_P0HI3Q_DESC_MODE)\n#define BITS_P0HI3Q_DESC_MODE                                                  \\\n\t(BIT_MASK_P0HI3Q_DESC_MODE << BIT_SHIFT_P0HI3Q_DESC_MODE)\n#define BIT_CLEAR_P0HI3Q_DESC_MODE(x) ((x) & (~BITS_P0HI3Q_DESC_MODE))\n#define BIT_GET_P0HI3Q_DESC_MODE(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI3Q_DESC_MODE) & BIT_MASK_P0HI3Q_DESC_MODE)\n#define BIT_SET_P0HI3Q_DESC_MODE(x, v)                                         \\\n\t(BIT_CLEAR_P0HI3Q_DESC_MODE(x) | BIT_P0HI3Q_DESC_MODE(v))\n\n#define BIT_SHIFT_P0HI3Q_DESC_NUM 16\n#define BIT_MASK_P0HI3Q_DESC_NUM 0xfff\n#define BIT_P0HI3Q_DESC_NUM(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI3Q_DESC_NUM) << BIT_SHIFT_P0HI3Q_DESC_NUM)\n#define BITS_P0HI3Q_DESC_NUM                                                   \\\n\t(BIT_MASK_P0HI3Q_DESC_NUM << BIT_SHIFT_P0HI3Q_DESC_NUM)\n#define BIT_CLEAR_P0HI3Q_DESC_NUM(x) ((x) & (~BITS_P0HI3Q_DESC_NUM))\n#define BIT_GET_P0HI3Q_DESC_NUM(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI3Q_DESC_NUM) & BIT_MASK_P0HI3Q_DESC_NUM)\n#define BIT_SET_P0HI3Q_DESC_NUM(x, v)                                          \\\n\t(BIT_CLEAR_P0HI3Q_DESC_NUM(x) | BIT_P0HI3Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI2Q_TXBD_NUM\t\t\t(Offset 0x0390) */\n\n#define BIT_HI2Q_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM\t\t(Offset 0x0390) */\n\n#define BIT_P0HI2Q_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI2Q_TXBD_NUM\t\t\t(Offset 0x0390) */\n\n#define BIT_SHIFT_HI2Q_DESC_MODE 12\n#define BIT_MASK_HI2Q_DESC_MODE 0x3\n#define BIT_HI2Q_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_HI2Q_DESC_MODE) << BIT_SHIFT_HI2Q_DESC_MODE)\n#define BITS_HI2Q_DESC_MODE                                                    \\\n\t(BIT_MASK_HI2Q_DESC_MODE << BIT_SHIFT_HI2Q_DESC_MODE)\n#define BIT_CLEAR_HI2Q_DESC_MODE(x) ((x) & (~BITS_HI2Q_DESC_MODE))\n#define BIT_GET_HI2Q_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI2Q_DESC_MODE) & BIT_MASK_HI2Q_DESC_MODE)\n#define BIT_SET_HI2Q_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_HI2Q_DESC_MODE(x) | BIT_HI2Q_DESC_MODE(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM\t\t(Offset 0x0390) */\n\n#define BIT_SHIFT_P0HI2Q_DESC_MODE 12\n#define BIT_MASK_P0HI2Q_DESC_MODE 0x3\n#define BIT_P0HI2Q_DESC_MODE(x)                                                \\\n\t(((x) & BIT_MASK_P0HI2Q_DESC_MODE) << BIT_SHIFT_P0HI2Q_DESC_MODE)\n#define BITS_P0HI2Q_DESC_MODE                                                  \\\n\t(BIT_MASK_P0HI2Q_DESC_MODE << BIT_SHIFT_P0HI2Q_DESC_MODE)\n#define BIT_CLEAR_P0HI2Q_DESC_MODE(x) ((x) & (~BITS_P0HI2Q_DESC_MODE))\n#define BIT_GET_P0HI2Q_DESC_MODE(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI2Q_DESC_MODE) & BIT_MASK_P0HI2Q_DESC_MODE)\n#define BIT_SET_P0HI2Q_DESC_MODE(x, v)                                         \\\n\t(BIT_CLEAR_P0HI2Q_DESC_MODE(x) | BIT_P0HI2Q_DESC_MODE(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI2Q_TXBD_NUM\t\t\t(Offset 0x0390) */\n\n#define BIT_SHIFT_HI2Q_DESC_NUM 0\n#define BIT_MASK_HI2Q_DESC_NUM 0xfff\n#define BIT_HI2Q_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_HI2Q_DESC_NUM) << BIT_SHIFT_HI2Q_DESC_NUM)\n#define BITS_HI2Q_DESC_NUM (BIT_MASK_HI2Q_DESC_NUM << BIT_SHIFT_HI2Q_DESC_NUM)\n#define BIT_CLEAR_HI2Q_DESC_NUM(x) ((x) & (~BITS_HI2Q_DESC_NUM))\n#define BIT_GET_HI2Q_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI2Q_DESC_NUM) & BIT_MASK_HI2Q_DESC_NUM)\n#define BIT_SET_HI2Q_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_HI2Q_DESC_NUM(x) | BIT_HI2Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM\t\t(Offset 0x0390) */\n\n#define BIT_SHIFT_P0HI2Q_DESC_NUM 0\n#define BIT_MASK_P0HI2Q_DESC_NUM 0xfff\n#define BIT_P0HI2Q_DESC_NUM(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI2Q_DESC_NUM) << BIT_SHIFT_P0HI2Q_DESC_NUM)\n#define BITS_P0HI2Q_DESC_NUM                                                   \\\n\t(BIT_MASK_P0HI2Q_DESC_NUM << BIT_SHIFT_P0HI2Q_DESC_NUM)\n#define BIT_CLEAR_P0HI2Q_DESC_NUM(x) ((x) & (~BITS_P0HI2Q_DESC_NUM))\n#define BIT_GET_P0HI2Q_DESC_NUM(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI2Q_DESC_NUM) & BIT_MASK_P0HI2Q_DESC_NUM)\n#define BIT_SET_P0HI2Q_DESC_NUM(x, v)                                          \\\n\t(BIT_CLEAR_P0HI2Q_DESC_NUM(x) | BIT_P0HI2Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI3Q_TXBD_NUM\t\t\t(Offset 0x0392) */\n\n#define BIT_HI3Q_FLAG BIT(14)\n\n#define BIT_SHIFT_HI3Q_DESC_MODE 12\n#define BIT_MASK_HI3Q_DESC_MODE 0x3\n#define BIT_HI3Q_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_HI3Q_DESC_MODE) << BIT_SHIFT_HI3Q_DESC_MODE)\n#define BITS_HI3Q_DESC_MODE                                                    \\\n\t(BIT_MASK_HI3Q_DESC_MODE << BIT_SHIFT_HI3Q_DESC_MODE)\n#define BIT_CLEAR_HI3Q_DESC_MODE(x) ((x) & (~BITS_HI3Q_DESC_MODE))\n#define BIT_GET_HI3Q_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI3Q_DESC_MODE) & BIT_MASK_HI3Q_DESC_MODE)\n#define BIT_SET_HI3Q_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_HI3Q_DESC_MODE(x) | BIT_HI3Q_DESC_MODE(v))\n\n#define BIT_SHIFT_HI3Q_DESC_NUM 0\n#define BIT_MASK_HI3Q_DESC_NUM 0xfff\n#define BIT_HI3Q_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_HI3Q_DESC_NUM) << BIT_SHIFT_HI3Q_DESC_NUM)\n#define BITS_HI3Q_DESC_NUM (BIT_MASK_HI3Q_DESC_NUM << BIT_SHIFT_HI3Q_DESC_NUM)\n#define BIT_CLEAR_HI3Q_DESC_NUM(x) ((x) & (~BITS_HI3Q_DESC_NUM))\n#define BIT_GET_HI3Q_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI3Q_DESC_NUM) & BIT_MASK_HI3Q_DESC_NUM)\n#define BIT_SET_HI3Q_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_HI3Q_DESC_NUM(x) | BIT_HI3Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM\t\t(Offset 0x0394) */\n\n#define BIT_P0HI5Q_FLAG BIT(30)\n\n#define BIT_SHIFT_P0HI5Q_DESC_MODE 28\n#define BIT_MASK_P0HI5Q_DESC_MODE 0x3\n#define BIT_P0HI5Q_DESC_MODE(x)                                                \\\n\t(((x) & BIT_MASK_P0HI5Q_DESC_MODE) << BIT_SHIFT_P0HI5Q_DESC_MODE)\n#define BITS_P0HI5Q_DESC_MODE                                                  \\\n\t(BIT_MASK_P0HI5Q_DESC_MODE << BIT_SHIFT_P0HI5Q_DESC_MODE)\n#define BIT_CLEAR_P0HI5Q_DESC_MODE(x) ((x) & (~BITS_P0HI5Q_DESC_MODE))\n#define BIT_GET_P0HI5Q_DESC_MODE(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI5Q_DESC_MODE) & BIT_MASK_P0HI5Q_DESC_MODE)\n#define BIT_SET_P0HI5Q_DESC_MODE(x, v)                                         \\\n\t(BIT_CLEAR_P0HI5Q_DESC_MODE(x) | BIT_P0HI5Q_DESC_MODE(v))\n\n#define BIT_SHIFT_P0HI5Q_DESC_NUM 16\n#define BIT_MASK_P0HI5Q_DESC_NUM 0xfff\n#define BIT_P0HI5Q_DESC_NUM(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI5Q_DESC_NUM) << BIT_SHIFT_P0HI5Q_DESC_NUM)\n#define BITS_P0HI5Q_DESC_NUM                                                   \\\n\t(BIT_MASK_P0HI5Q_DESC_NUM << BIT_SHIFT_P0HI5Q_DESC_NUM)\n#define BIT_CLEAR_P0HI5Q_DESC_NUM(x) ((x) & (~BITS_P0HI5Q_DESC_NUM))\n#define BIT_GET_P0HI5Q_DESC_NUM(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI5Q_DESC_NUM) & BIT_MASK_P0HI5Q_DESC_NUM)\n#define BIT_SET_P0HI5Q_DESC_NUM(x, v)                                          \\\n\t(BIT_CLEAR_P0HI5Q_DESC_NUM(x) | BIT_P0HI5Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI4Q_TXBD_NUM\t\t\t(Offset 0x0394) */\n\n#define BIT_HI4Q_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM\t\t(Offset 0x0394) */\n\n#define BIT_P0HI4Q_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI4Q_TXBD_NUM\t\t\t(Offset 0x0394) */\n\n#define BIT_SHIFT_HI4Q_DESC_MODE 12\n#define BIT_MASK_HI4Q_DESC_MODE 0x3\n#define BIT_HI4Q_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_HI4Q_DESC_MODE) << BIT_SHIFT_HI4Q_DESC_MODE)\n#define BITS_HI4Q_DESC_MODE                                                    \\\n\t(BIT_MASK_HI4Q_DESC_MODE << BIT_SHIFT_HI4Q_DESC_MODE)\n#define BIT_CLEAR_HI4Q_DESC_MODE(x) ((x) & (~BITS_HI4Q_DESC_MODE))\n#define BIT_GET_HI4Q_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI4Q_DESC_MODE) & BIT_MASK_HI4Q_DESC_MODE)\n#define BIT_SET_HI4Q_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_HI4Q_DESC_MODE(x) | BIT_HI4Q_DESC_MODE(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM\t\t(Offset 0x0394) */\n\n#define BIT_SHIFT_P0HI4Q_DESC_MODE 12\n#define BIT_MASK_P0HI4Q_DESC_MODE 0x3\n#define BIT_P0HI4Q_DESC_MODE(x)                                                \\\n\t(((x) & BIT_MASK_P0HI4Q_DESC_MODE) << BIT_SHIFT_P0HI4Q_DESC_MODE)\n#define BITS_P0HI4Q_DESC_MODE                                                  \\\n\t(BIT_MASK_P0HI4Q_DESC_MODE << BIT_SHIFT_P0HI4Q_DESC_MODE)\n#define BIT_CLEAR_P0HI4Q_DESC_MODE(x) ((x) & (~BITS_P0HI4Q_DESC_MODE))\n#define BIT_GET_P0HI4Q_DESC_MODE(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI4Q_DESC_MODE) & BIT_MASK_P0HI4Q_DESC_MODE)\n#define BIT_SET_P0HI4Q_DESC_MODE(x, v)                                         \\\n\t(BIT_CLEAR_P0HI4Q_DESC_MODE(x) | BIT_P0HI4Q_DESC_MODE(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI4Q_TXBD_NUM\t\t\t(Offset 0x0394) */\n\n#define BIT_SHIFT_HI4Q_DESC_NUM 0\n#define BIT_MASK_HI4Q_DESC_NUM 0xfff\n#define BIT_HI4Q_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_HI4Q_DESC_NUM) << BIT_SHIFT_HI4Q_DESC_NUM)\n#define BITS_HI4Q_DESC_NUM (BIT_MASK_HI4Q_DESC_NUM << BIT_SHIFT_HI4Q_DESC_NUM)\n#define BIT_CLEAR_HI4Q_DESC_NUM(x) ((x) & (~BITS_HI4Q_DESC_NUM))\n#define BIT_GET_HI4Q_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI4Q_DESC_NUM) & BIT_MASK_HI4Q_DESC_NUM)\n#define BIT_SET_HI4Q_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_HI4Q_DESC_NUM(x) | BIT_HI4Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM\t\t(Offset 0x0394) */\n\n#define BIT_SHIFT_P0HI4Q_DESC_NUM 0\n#define BIT_MASK_P0HI4Q_DESC_NUM 0xfff\n#define BIT_P0HI4Q_DESC_NUM(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI4Q_DESC_NUM) << BIT_SHIFT_P0HI4Q_DESC_NUM)\n#define BITS_P0HI4Q_DESC_NUM                                                   \\\n\t(BIT_MASK_P0HI4Q_DESC_NUM << BIT_SHIFT_P0HI4Q_DESC_NUM)\n#define BIT_CLEAR_P0HI4Q_DESC_NUM(x) ((x) & (~BITS_P0HI4Q_DESC_NUM))\n#define BIT_GET_P0HI4Q_DESC_NUM(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI4Q_DESC_NUM) & BIT_MASK_P0HI4Q_DESC_NUM)\n#define BIT_SET_P0HI4Q_DESC_NUM(x, v)                                          \\\n\t(BIT_CLEAR_P0HI4Q_DESC_NUM(x) | BIT_P0HI4Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI5Q_TXBD_NUM\t\t\t(Offset 0x0396) */\n\n#define BIT_HI5Q_FLAG BIT(14)\n\n#define BIT_SHIFT_HI5Q_DESC_MODE 12\n#define BIT_MASK_HI5Q_DESC_MODE 0x3\n#define BIT_HI5Q_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_HI5Q_DESC_MODE) << BIT_SHIFT_HI5Q_DESC_MODE)\n#define BITS_HI5Q_DESC_MODE                                                    \\\n\t(BIT_MASK_HI5Q_DESC_MODE << BIT_SHIFT_HI5Q_DESC_MODE)\n#define BIT_CLEAR_HI5Q_DESC_MODE(x) ((x) & (~BITS_HI5Q_DESC_MODE))\n#define BIT_GET_HI5Q_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI5Q_DESC_MODE) & BIT_MASK_HI5Q_DESC_MODE)\n#define BIT_SET_HI5Q_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_HI5Q_DESC_MODE(x) | BIT_HI5Q_DESC_MODE(v))\n\n#define BIT_SHIFT_HI5Q_DESC_NUM 0\n#define BIT_MASK_HI5Q_DESC_NUM 0xfff\n#define BIT_HI5Q_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_HI5Q_DESC_NUM) << BIT_SHIFT_HI5Q_DESC_NUM)\n#define BITS_HI5Q_DESC_NUM (BIT_MASK_HI5Q_DESC_NUM << BIT_SHIFT_HI5Q_DESC_NUM)\n#define BIT_CLEAR_HI5Q_DESC_NUM(x) ((x) & (~BITS_HI5Q_DESC_NUM))\n#define BIT_GET_HI5Q_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI5Q_DESC_NUM) & BIT_MASK_HI5Q_DESC_NUM)\n#define BIT_SET_HI5Q_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_HI5Q_DESC_NUM(x) | BIT_HI5Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM\t\t(Offset 0x0398) */\n\n#define BIT_P0HI7Q_FLAG BIT(30)\n#define BIT_CLR_FWCMDQ_HW_IDX BIT(30)\n#define BIT_CLR_P0HI7Q_HW_IDX BIT(29)\n\n#define BIT_SHIFT_P0HI7Q_DESC_MODE 28\n#define BIT_MASK_P0HI7Q_DESC_MODE 0x3\n#define BIT_P0HI7Q_DESC_MODE(x)                                                \\\n\t(((x) & BIT_MASK_P0HI7Q_DESC_MODE) << BIT_SHIFT_P0HI7Q_DESC_MODE)\n#define BITS_P0HI7Q_DESC_MODE                                                  \\\n\t(BIT_MASK_P0HI7Q_DESC_MODE << BIT_SHIFT_P0HI7Q_DESC_MODE)\n#define BIT_CLEAR_P0HI7Q_DESC_MODE(x) ((x) & (~BITS_P0HI7Q_DESC_MODE))\n#define BIT_GET_P0HI7Q_DESC_MODE(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI7Q_DESC_MODE) & BIT_MASK_P0HI7Q_DESC_MODE)\n#define BIT_SET_P0HI7Q_DESC_MODE(x, v)                                         \\\n\t(BIT_CLEAR_P0HI7Q_DESC_MODE(x) | BIT_P0HI7Q_DESC_MODE(v))\n\n#define BIT_CLR_P0HI6Q_HW_IDX BIT(28)\n#define BIT_CLR_P0HI5Q_HW_IDX BIT(27)\n#define BIT_CLR_P0HI4Q_HW_IDX BIT(26)\n#define BIT_CLR_P0HI3Q_HW_IDX BIT(25)\n#define BIT_CLR_P0HI2Q_HW_IDX BIT(24)\n#define BIT_CLR_P0HI1Q_HW_IDX BIT(23)\n#define BIT_CLR_P0HI0Q_HW_IDX BIT(22)\n#define BIT_CLR_ACH3_HW_IDX BIT(21)\n#define BIT_CLR_ACH2_HW_IDX BIT(20)\n#define BIT_CLR_ACH1_HW_IDX BIT(19)\n#define BIT_CLR_ACH0_HW_IDX BIT(18)\n#define BIT_CLR_P0MGQ_HW_IDX BIT(17)\n\n#define BIT_SHIFT_P0HI7Q_DESC_NUM 16\n#define BIT_MASK_P0HI7Q_DESC_NUM 0xfff\n#define BIT_P0HI7Q_DESC_NUM(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI7Q_DESC_NUM) << BIT_SHIFT_P0HI7Q_DESC_NUM)\n#define BITS_P0HI7Q_DESC_NUM                                                   \\\n\t(BIT_MASK_P0HI7Q_DESC_NUM << BIT_SHIFT_P0HI7Q_DESC_NUM)\n#define BIT_CLEAR_P0HI7Q_DESC_NUM(x) ((x) & (~BITS_P0HI7Q_DESC_NUM))\n#define BIT_GET_P0HI7Q_DESC_NUM(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI7Q_DESC_NUM) & BIT_MASK_P0HI7Q_DESC_NUM)\n#define BIT_SET_P0HI7Q_DESC_NUM(x, v)                                          \\\n\t(BIT_CLEAR_P0HI7Q_DESC_NUM(x) | BIT_P0HI7Q_DESC_NUM(v))\n\n#define BIT_CLR_P0RXQ_HW_IDX BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI6Q_TXBD_NUM\t\t\t(Offset 0x0398) */\n\n#define BIT_HI6Q_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM\t\t(Offset 0x0398) */\n\n#define BIT_P0HI6Q_FLAG BIT(14)\n#define BIT_CLR_PFWCMDQ_HOST_IDX BIT(14)\n#define BIT_CLR_P0HI7Q_HOST_IDX BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI6Q_TXBD_NUM\t\t\t(Offset 0x0398) */\n\n#define BIT_SHIFT_HI6Q_DESC_MODE 12\n#define BIT_MASK_HI6Q_DESC_MODE 0x3\n#define BIT_HI6Q_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_HI6Q_DESC_MODE) << BIT_SHIFT_HI6Q_DESC_MODE)\n#define BITS_HI6Q_DESC_MODE                                                    \\\n\t(BIT_MASK_HI6Q_DESC_MODE << BIT_SHIFT_HI6Q_DESC_MODE)\n#define BIT_CLEAR_HI6Q_DESC_MODE(x) ((x) & (~BITS_HI6Q_DESC_MODE))\n#define BIT_GET_HI6Q_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI6Q_DESC_MODE) & BIT_MASK_HI6Q_DESC_MODE)\n#define BIT_SET_HI6Q_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_HI6Q_DESC_MODE(x) | BIT_HI6Q_DESC_MODE(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM\t\t(Offset 0x0398) */\n\n#define BIT_SHIFT_P0HI6Q_DESC_MODE 12\n#define BIT_MASK_P0HI6Q_DESC_MODE 0x3\n#define BIT_P0HI6Q_DESC_MODE(x)                                                \\\n\t(((x) & BIT_MASK_P0HI6Q_DESC_MODE) << BIT_SHIFT_P0HI6Q_DESC_MODE)\n#define BITS_P0HI6Q_DESC_MODE                                                  \\\n\t(BIT_MASK_P0HI6Q_DESC_MODE << BIT_SHIFT_P0HI6Q_DESC_MODE)\n#define BIT_CLEAR_P0HI6Q_DESC_MODE(x) ((x) & (~BITS_P0HI6Q_DESC_MODE))\n#define BIT_GET_P0HI6Q_DESC_MODE(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI6Q_DESC_MODE) & BIT_MASK_P0HI6Q_DESC_MODE)\n#define BIT_SET_P0HI6Q_DESC_MODE(x, v)                                         \\\n\t(BIT_CLEAR_P0HI6Q_DESC_MODE(x) | BIT_P0HI6Q_DESC_MODE(v))\n\n#define BIT_CLR_P0HI6Q_HOST_IDX BIT(12)\n#define BIT_CLR_P0HI5Q_HOST_IDX BIT(11)\n#define BIT_CLR_P0HI4Q_HOST_IDX BIT(10)\n#define BIT_CLR_P0HI3Q_HOST_IDX BIT(9)\n#define BIT_CLR_P0HI2Q_HOST_IDX BIT(8)\n#define BIT_CLR_P0HI1Q_HOST_IDX BIT(7)\n#define BIT_CLR_P0HI0Q_HOST_IDX BIT(6)\n#define BIT_CLR_ACH3_HOST_IDX BIT(5)\n#define BIT_CLR_ACH2_HOST_IDX BIT(4)\n#define BIT_CLR_ACH1_HOST_IDX BIT(3)\n#define BIT_CLR_ACH0_HOST_IDX BIT(2)\n#define BIT_CLR_P0MGQ_HOST_IDX BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI6Q_TXBD_NUM\t\t\t(Offset 0x0398) */\n\n#define BIT_SHIFT_HI6Q_DESC_NUM 0\n#define BIT_MASK_HI6Q_DESC_NUM 0xfff\n#define BIT_HI6Q_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_HI6Q_DESC_NUM) << BIT_SHIFT_HI6Q_DESC_NUM)\n#define BITS_HI6Q_DESC_NUM (BIT_MASK_HI6Q_DESC_NUM << BIT_SHIFT_HI6Q_DESC_NUM)\n#define BIT_CLEAR_HI6Q_DESC_NUM(x) ((x) & (~BITS_HI6Q_DESC_NUM))\n#define BIT_GET_HI6Q_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI6Q_DESC_NUM) & BIT_MASK_HI6Q_DESC_NUM)\n#define BIT_SET_HI6Q_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_HI6Q_DESC_NUM(x) | BIT_HI6Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM\t\t(Offset 0x0398) */\n\n#define BIT_SHIFT_P0HI6Q_DESC_NUM 0\n#define BIT_MASK_P0HI6Q_DESC_NUM 0xfff\n#define BIT_P0HI6Q_DESC_NUM(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI6Q_DESC_NUM) << BIT_SHIFT_P0HI6Q_DESC_NUM)\n#define BITS_P0HI6Q_DESC_NUM                                                   \\\n\t(BIT_MASK_P0HI6Q_DESC_NUM << BIT_SHIFT_P0HI6Q_DESC_NUM)\n#define BIT_CLEAR_P0HI6Q_DESC_NUM(x) ((x) & (~BITS_P0HI6Q_DESC_NUM))\n#define BIT_GET_P0HI6Q_DESC_NUM(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI6Q_DESC_NUM) & BIT_MASK_P0HI6Q_DESC_NUM)\n#define BIT_SET_P0HI6Q_DESC_NUM(x, v)                                          \\\n\t(BIT_CLEAR_P0HI6Q_DESC_NUM(x) | BIT_P0HI6Q_DESC_NUM(v))\n\n#define BIT_CLR_P0RXQ_HOST_IDX BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI7Q_TXBD_NUM\t\t\t(Offset 0x039A) */\n\n#define BIT_HI7Q_FLAG BIT(14)\n\n#define BIT_SHIFT_HI7Q_DESC_MODE 12\n#define BIT_MASK_HI7Q_DESC_MODE 0x3\n#define BIT_HI7Q_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_HI7Q_DESC_MODE) << BIT_SHIFT_HI7Q_DESC_MODE)\n#define BITS_HI7Q_DESC_MODE                                                    \\\n\t(BIT_MASK_HI7Q_DESC_MODE << BIT_SHIFT_HI7Q_DESC_MODE)\n#define BIT_CLEAR_HI7Q_DESC_MODE(x) ((x) & (~BITS_HI7Q_DESC_MODE))\n#define BIT_GET_HI7Q_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI7Q_DESC_MODE) & BIT_MASK_HI7Q_DESC_MODE)\n#define BIT_SET_HI7Q_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_HI7Q_DESC_MODE(x) | BIT_HI7Q_DESC_MODE(v))\n\n#define BIT_SHIFT_HI7Q_DESC_NUM 0\n#define BIT_MASK_HI7Q_DESC_NUM 0xfff\n#define BIT_HI7Q_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_HI7Q_DESC_NUM) << BIT_SHIFT_HI7Q_DESC_NUM)\n#define BITS_HI7Q_DESC_NUM (BIT_MASK_HI7Q_DESC_NUM << BIT_SHIFT_HI7Q_DESC_NUM)\n#define BIT_CLEAR_HI7Q_DESC_NUM(x) ((x) & (~BITS_HI7Q_DESC_NUM))\n#define BIT_GET_HI7Q_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI7Q_DESC_NUM) & BIT_MASK_HI7Q_DESC_NUM)\n#define BIT_SET_HI7Q_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_HI7Q_DESC_NUM(x) | BIT_HI7Q_DESC_NUM(v))\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_HI7Q_HW_IDX BIT(29)\n#define BIT_CLR_HI6Q_HW_IDX BIT(28)\n#define BIT_CLR_HI5Q_HW_IDX BIT(27)\n#define BIT_CLR_HI4Q_HW_IDX BIT(26)\n#define BIT_CLR_HI3Q_HW_IDX BIT(25)\n#define BIT_CLR_HI2Q_HW_IDX BIT(24)\n#define BIT_CLR_HI1Q_HW_IDX BIT(23)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_BCN7DOK BIT(23)\n#define BIT_BCN7DOKM BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_HI0Q_HW_IDX BIT(22)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_BCN6DOK BIT(22)\n#define BIT_BCN6DOKM BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_BKQ_HW_IDX BIT(21)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_BCN5DOK BIT(21)\n#define BIT_BCN5DOKM BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_BEQ_HW_IDX BIT(20)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_BCN4DOK BIT(20)\n#define BIT_BCN4DOKM BIT(20)\n#define BIT_RX_OVER_RD_ERR BIT(20)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_VIQ_HW_IDX BIT(19)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_BCN3DOK BIT(19)\n#define BIT_BCN3DOKM BIT(19)\n#define BIT_RXDMA_STUCK BIT(19)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_VOQ_HW_IDX BIT(18)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_BCN2DOK BIT(18)\n#define BIT_BCN2DOKM BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_MGQ_HW_IDX BIT(17)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_BCN1DOK BIT(17)\n#define BIT_BCN1DOKM BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TSFTIMER_HCI\t\t\t(Offset 0x039C) */\n\n#define BIT_SHIFT_TSFT2_HCI 16\n#define BIT_MASK_TSFT2_HCI 0xffff\n#define BIT_TSFT2_HCI(x) (((x) & BIT_MASK_TSFT2_HCI) << BIT_SHIFT_TSFT2_HCI)\n#define BITS_TSFT2_HCI (BIT_MASK_TSFT2_HCI << BIT_SHIFT_TSFT2_HCI)\n#define BIT_CLEAR_TSFT2_HCI(x) ((x) & (~BITS_TSFT2_HCI))\n#define BIT_GET_TSFT2_HCI(x) (((x) >> BIT_SHIFT_TSFT2_HCI) & BIT_MASK_TSFT2_HCI)\n#define BIT_SET_TSFT2_HCI(x, v) (BIT_CLEAR_TSFT2_HCI(x) | BIT_TSFT2_HCI(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_RXQ_HW_IDX BIT(16)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_BCN0DOK BIT(16)\n#define BIT_BCN0DOKM BIT(16)\n\n#define BIT_SHIFT_RX_STATE 16\n#define BIT_MASK_RX_STATE 0x7\n#define BIT_RX_STATE(x) (((x) & BIT_MASK_RX_STATE) << BIT_SHIFT_RX_STATE)\n#define BITS_RX_STATE (BIT_MASK_RX_STATE << BIT_SHIFT_RX_STATE)\n#define BIT_CLEAR_RX_STATE(x) ((x) & (~BITS_RX_STATE))\n#define BIT_GET_RX_STATE(x) (((x) >> BIT_SHIFT_RX_STATE) & BIT_MASK_RX_STATE)\n#define BIT_SET_RX_STATE(x, v) (BIT_CLEAR_RX_STATE(x) | BIT_RX_STATE(v))\n\n#define BIT_SRST_TX BIT(15)\n#define BIT_M7DOK BIT(15)\n#define BIT_M7DOKM BIT(15)\n#define BIT_TDE_NO_IDLE BIT(15)\n#define BIT_SRST_RX BIT(14)\n#define BIT_M6DOK BIT(14)\n#define BIT_M6DOKM BIT(14)\n#define BIT_TXDMA_STUCK BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_HI7Q_HOST_IDX BIT(13)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_M5DOK BIT(13)\n#define BIT_M5DOKM BIT(13)\n#define BIT_TDE_FULL_ERR BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_HI6Q_HOST_IDX BIT(12)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_M4DOK BIT(12)\n#define BIT_M4DOKM BIT(12)\n#define BIT_HD_SIZE_ERR BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_HI5Q_HOST_IDX BIT(11)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_M3DOK BIT(11)\n#define BIT_M3DOKM BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_HI4Q_HOST_IDX BIT(10)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_M2DOK BIT(10)\n#define BIT_M2DOKM BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_HI3Q_HOST_IDX BIT(9)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_M1DOK BIT(9)\n#define BIT_M1DOKM BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_HI2Q_HOST_IDX BIT(8)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_M0DOK BIT(8)\n#define BIT_M0DOKM BIT(8)\n\n#define BIT_SHIFT_TX_STATE 8\n#define BIT_MASK_TX_STATE 0xf\n#define BIT_TX_STATE(x) (((x) & BIT_MASK_TX_STATE) << BIT_SHIFT_TX_STATE)\n#define BITS_TX_STATE (BIT_MASK_TX_STATE << BIT_SHIFT_TX_STATE)\n#define BIT_CLEAR_TX_STATE(x) ((x) & (~BITS_TX_STATE))\n#define BIT_GET_TX_STATE(x) (((x) >> BIT_SHIFT_TX_STATE) & BIT_MASK_TX_STATE)\n#define BIT_SET_TX_STATE(x, v) (BIT_CLEAR_TX_STATE(x) | BIT_TX_STATE(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_HI1Q_HOST_IDX BIT(7)\n#define BIT_CLR_HI0Q_HOST_IDX BIT(6)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_MGQDOK BIT(6)\n#define BIT_MGQDOKM BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_BKQ_HOST_IDX BIT(5)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_BKQDOK BIT(5)\n#define BIT_BKQDOKM BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_BEQ_HOST_IDX BIT(4)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_SHIFT_HPS_CLKR 4\n#define BIT_MASK_HPS_CLKR 0x3\n#define BIT_HPS_CLKR(x) (((x) & BIT_MASK_HPS_CLKR) << BIT_SHIFT_HPS_CLKR)\n#define BITS_HPS_CLKR (BIT_MASK_HPS_CLKR << BIT_SHIFT_HPS_CLKR)\n#define BIT_CLEAR_HPS_CLKR(x) ((x) & (~BITS_HPS_CLKR))\n#define BIT_GET_HPS_CLKR(x) (((x) >> BIT_SHIFT_HPS_CLKR) & BIT_MASK_HPS_CLKR)\n#define BIT_SET_HPS_CLKR(x, v) (BIT_CLEAR_HPS_CLKR(x) | BIT_HPS_CLKR(v))\n\n#define BIT_BEQDOK BIT(4)\n#define BIT_BEQDOKM BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_VIQ_HOST_IDX BIT(3)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_LX_INT BIT(3)\n#define BIT_VIQDOK BIT(3)\n#define BIT_VIQDOKM BIT(3)\n#define BIT_MST_BUSY BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_VOQ_HOST_IDX BIT(2)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_VOQDOK BIT(2)\n#define BIT_VOQDOKM BIT(2)\n#define BIT_SLV_BUSY BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_MGQ_HOST_IDX BIT(1)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_RDUM BIT(1)\n#define BIT_RXDES_UNAVAIL BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TSFTIMER_HCI\t\t\t(Offset 0x039C) */\n\n#define BIT_SHIFT_TSFT1_HCI 0\n#define BIT_MASK_TSFT1_HCI 0xffff\n#define BIT_TSFT1_HCI(x) (((x) & BIT_MASK_TSFT1_HCI) << BIT_SHIFT_TSFT1_HCI)\n#define BITS_TSFT1_HCI (BIT_MASK_TSFT1_HCI << BIT_SHIFT_TSFT1_HCI)\n#define BIT_CLEAR_TSFT1_HCI(x) ((x) & (~BITS_TSFT1_HCI))\n#define BIT_GET_TSFT1_HCI(x) (((x) >> BIT_SHIFT_TSFT1_HCI) & BIT_MASK_TSFT1_HCI)\n#define BIT_SET_TSFT1_HCI(x, v) (BIT_CLEAR_TSFT1_HCI(x) | BIT_TSFT1_HCI(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_CLR_RXQ_HOST_IDX BIT(0)\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BD_RWPTR_CLR\t\t\t(Offset 0x039C) */\n\n#define BIT_RXDOK BIT(0)\n#define BIT_RXDOKM BIT(0)\n#define BIT_EN_DBG_STUCK BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_VOQ_TXBD_IDX\t\t\t(Offset 0x03A0) */\n\n#define BIT_SHIFT_VOQ_HW_IDX 16\n#define BIT_MASK_VOQ_HW_IDX 0xfff\n#define BIT_VOQ_HW_IDX(x) (((x) & BIT_MASK_VOQ_HW_IDX) << BIT_SHIFT_VOQ_HW_IDX)\n#define BITS_VOQ_HW_IDX (BIT_MASK_VOQ_HW_IDX << BIT_SHIFT_VOQ_HW_IDX)\n#define BIT_CLEAR_VOQ_HW_IDX(x) ((x) & (~BITS_VOQ_HW_IDX))\n#define BIT_GET_VOQ_HW_IDX(x)                                                  \\\n\t(((x) >> BIT_SHIFT_VOQ_HW_IDX) & BIT_MASK_VOQ_HW_IDX)\n#define BIT_SET_VOQ_HW_IDX(x, v) (BIT_CLEAR_VOQ_HW_IDX(x) | BIT_VOQ_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH0_TXBD_IDX\t\t\t(Offset 0x03A0) */\n\n#define BIT_SHIFT_ACH0_HW_IDX 16\n#define BIT_MASK_ACH0_HW_IDX 0xfff\n#define BIT_ACH0_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_ACH0_HW_IDX) << BIT_SHIFT_ACH0_HW_IDX)\n#define BITS_ACH0_HW_IDX (BIT_MASK_ACH0_HW_IDX << BIT_SHIFT_ACH0_HW_IDX)\n#define BIT_CLEAR_ACH0_HW_IDX(x) ((x) & (~BITS_ACH0_HW_IDX))\n#define BIT_GET_ACH0_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ACH0_HW_IDX) & BIT_MASK_ACH0_HW_IDX)\n#define BIT_SET_ACH0_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_ACH0_HW_IDX(x) | BIT_ACH0_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_VOQ_TXBD_IDX\t\t\t(Offset 0x03A0) */\n\n#define BIT_SHIFT_VOQ_HOST_IDX 0\n#define BIT_MASK_VOQ_HOST_IDX 0xfff\n#define BIT_VOQ_HOST_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_VOQ_HOST_IDX) << BIT_SHIFT_VOQ_HOST_IDX)\n#define BITS_VOQ_HOST_IDX (BIT_MASK_VOQ_HOST_IDX << BIT_SHIFT_VOQ_HOST_IDX)\n#define BIT_CLEAR_VOQ_HOST_IDX(x) ((x) & (~BITS_VOQ_HOST_IDX))\n#define BIT_GET_VOQ_HOST_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_VOQ_HOST_IDX) & BIT_MASK_VOQ_HOST_IDX)\n#define BIT_SET_VOQ_HOST_IDX(x, v)                                             \\\n\t(BIT_CLEAR_VOQ_HOST_IDX(x) | BIT_VOQ_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH0_TXBD_IDX\t\t\t(Offset 0x03A0) */\n\n#define BIT_SHIFT_ACH0_HOST_IDX 0\n#define BIT_MASK_ACH0_HOST_IDX 0xfff\n#define BIT_ACH0_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_ACH0_HOST_IDX) << BIT_SHIFT_ACH0_HOST_IDX)\n#define BITS_ACH0_HOST_IDX (BIT_MASK_ACH0_HOST_IDX << BIT_SHIFT_ACH0_HOST_IDX)\n#define BIT_CLEAR_ACH0_HOST_IDX(x) ((x) & (~BITS_ACH0_HOST_IDX))\n#define BIT_GET_ACH0_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH0_HOST_IDX) & BIT_MASK_ACH0_HOST_IDX)\n#define BIT_SET_ACH0_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_ACH0_HOST_IDX(x) | BIT_ACH0_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_VIQ_TXBD_IDX\t\t\t(Offset 0x03A4) */\n\n#define BIT_SHIFT_VIQ_HW_IDX 16\n#define BIT_MASK_VIQ_HW_IDX 0xfff\n#define BIT_VIQ_HW_IDX(x) (((x) & BIT_MASK_VIQ_HW_IDX) << BIT_SHIFT_VIQ_HW_IDX)\n#define BITS_VIQ_HW_IDX (BIT_MASK_VIQ_HW_IDX << BIT_SHIFT_VIQ_HW_IDX)\n#define BIT_CLEAR_VIQ_HW_IDX(x) ((x) & (~BITS_VIQ_HW_IDX))\n#define BIT_GET_VIQ_HW_IDX(x)                                                  \\\n\t(((x) >> BIT_SHIFT_VIQ_HW_IDX) & BIT_MASK_VIQ_HW_IDX)\n#define BIT_SET_VIQ_HW_IDX(x, v) (BIT_CLEAR_VIQ_HW_IDX(x) | BIT_VIQ_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH1_TXBD_IDX\t\t\t(Offset 0x03A4) */\n\n#define BIT_SHIFT_ACH1_HW_IDX 16\n#define BIT_MASK_ACH1_HW_IDX 0xfff\n#define BIT_ACH1_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_ACH1_HW_IDX) << BIT_SHIFT_ACH1_HW_IDX)\n#define BITS_ACH1_HW_IDX (BIT_MASK_ACH1_HW_IDX << BIT_SHIFT_ACH1_HW_IDX)\n#define BIT_CLEAR_ACH1_HW_IDX(x) ((x) & (~BITS_ACH1_HW_IDX))\n#define BIT_GET_ACH1_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ACH1_HW_IDX) & BIT_MASK_ACH1_HW_IDX)\n#define BIT_SET_ACH1_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_ACH1_HW_IDX(x) | BIT_ACH1_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_VIQ_TXBD_IDX\t\t\t(Offset 0x03A4) */\n\n#define BIT_SHIFT_VIQ_HOST_IDX 0\n#define BIT_MASK_VIQ_HOST_IDX 0xfff\n#define BIT_VIQ_HOST_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_VIQ_HOST_IDX) << BIT_SHIFT_VIQ_HOST_IDX)\n#define BITS_VIQ_HOST_IDX (BIT_MASK_VIQ_HOST_IDX << BIT_SHIFT_VIQ_HOST_IDX)\n#define BIT_CLEAR_VIQ_HOST_IDX(x) ((x) & (~BITS_VIQ_HOST_IDX))\n#define BIT_GET_VIQ_HOST_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_VIQ_HOST_IDX) & BIT_MASK_VIQ_HOST_IDX)\n#define BIT_SET_VIQ_HOST_IDX(x, v)                                             \\\n\t(BIT_CLEAR_VIQ_HOST_IDX(x) | BIT_VIQ_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH1_TXBD_IDX\t\t\t(Offset 0x03A4) */\n\n#define BIT_SHIFT_ACH1_HOST_IDX 0\n#define BIT_MASK_ACH1_HOST_IDX 0xfff\n#define BIT_ACH1_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_ACH1_HOST_IDX) << BIT_SHIFT_ACH1_HOST_IDX)\n#define BITS_ACH1_HOST_IDX (BIT_MASK_ACH1_HOST_IDX << BIT_SHIFT_ACH1_HOST_IDX)\n#define BIT_CLEAR_ACH1_HOST_IDX(x) ((x) & (~BITS_ACH1_HOST_IDX))\n#define BIT_GET_ACH1_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH1_HOST_IDX) & BIT_MASK_ACH1_HOST_IDX)\n#define BIT_SET_ACH1_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_ACH1_HOST_IDX(x) | BIT_ACH1_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BEQ_TXBD_IDX\t\t\t(Offset 0x03A8) */\n\n#define BIT_SHIFT_BEQ_HW_IDX 16\n#define BIT_MASK_BEQ_HW_IDX 0xfff\n#define BIT_BEQ_HW_IDX(x) (((x) & BIT_MASK_BEQ_HW_IDX) << BIT_SHIFT_BEQ_HW_IDX)\n#define BITS_BEQ_HW_IDX (BIT_MASK_BEQ_HW_IDX << BIT_SHIFT_BEQ_HW_IDX)\n#define BIT_CLEAR_BEQ_HW_IDX(x) ((x) & (~BITS_BEQ_HW_IDX))\n#define BIT_GET_BEQ_HW_IDX(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BEQ_HW_IDX) & BIT_MASK_BEQ_HW_IDX)\n#define BIT_SET_BEQ_HW_IDX(x, v) (BIT_CLEAR_BEQ_HW_IDX(x) | BIT_BEQ_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH2_TXBD_IDX\t\t\t(Offset 0x03A8) */\n\n#define BIT_SHIFT_ACH2_HW_IDX 16\n#define BIT_MASK_ACH2_HW_IDX 0xfff\n#define BIT_ACH2_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_ACH2_HW_IDX) << BIT_SHIFT_ACH2_HW_IDX)\n#define BITS_ACH2_HW_IDX (BIT_MASK_ACH2_HW_IDX << BIT_SHIFT_ACH2_HW_IDX)\n#define BIT_CLEAR_ACH2_HW_IDX(x) ((x) & (~BITS_ACH2_HW_IDX))\n#define BIT_GET_ACH2_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ACH2_HW_IDX) & BIT_MASK_ACH2_HW_IDX)\n#define BIT_SET_ACH2_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_ACH2_HW_IDX(x) | BIT_ACH2_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BEQ_TXBD_IDX\t\t\t(Offset 0x03A8) */\n\n#define BIT_SHIFT_BEQ_HOST_IDX 0\n#define BIT_MASK_BEQ_HOST_IDX 0xfff\n#define BIT_BEQ_HOST_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_BEQ_HOST_IDX) << BIT_SHIFT_BEQ_HOST_IDX)\n#define BITS_BEQ_HOST_IDX (BIT_MASK_BEQ_HOST_IDX << BIT_SHIFT_BEQ_HOST_IDX)\n#define BIT_CLEAR_BEQ_HOST_IDX(x) ((x) & (~BITS_BEQ_HOST_IDX))\n#define BIT_GET_BEQ_HOST_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_BEQ_HOST_IDX) & BIT_MASK_BEQ_HOST_IDX)\n#define BIT_SET_BEQ_HOST_IDX(x, v)                                             \\\n\t(BIT_CLEAR_BEQ_HOST_IDX(x) | BIT_BEQ_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH2_TXBD_IDX\t\t\t(Offset 0x03A8) */\n\n#define BIT_SHIFT_ACH2_HOST_IDX 0\n#define BIT_MASK_ACH2_HOST_IDX 0xfff\n#define BIT_ACH2_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_ACH2_HOST_IDX) << BIT_SHIFT_ACH2_HOST_IDX)\n#define BITS_ACH2_HOST_IDX (BIT_MASK_ACH2_HOST_IDX << BIT_SHIFT_ACH2_HOST_IDX)\n#define BIT_CLEAR_ACH2_HOST_IDX(x) ((x) & (~BITS_ACH2_HOST_IDX))\n#define BIT_GET_ACH2_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH2_HOST_IDX) & BIT_MASK_ACH2_HOST_IDX)\n#define BIT_SET_ACH2_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_ACH2_HOST_IDX(x) | BIT_ACH2_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BKQ_TXBD_IDX\t\t\t(Offset 0x03AC) */\n\n#define BIT_SHIFT_BKQ_HW_IDX 16\n#define BIT_MASK_BKQ_HW_IDX 0xfff\n#define BIT_BKQ_HW_IDX(x) (((x) & BIT_MASK_BKQ_HW_IDX) << BIT_SHIFT_BKQ_HW_IDX)\n#define BITS_BKQ_HW_IDX (BIT_MASK_BKQ_HW_IDX << BIT_SHIFT_BKQ_HW_IDX)\n#define BIT_CLEAR_BKQ_HW_IDX(x) ((x) & (~BITS_BKQ_HW_IDX))\n#define BIT_GET_BKQ_HW_IDX(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BKQ_HW_IDX) & BIT_MASK_BKQ_HW_IDX)\n#define BIT_SET_BKQ_HW_IDX(x, v) (BIT_CLEAR_BKQ_HW_IDX(x) | BIT_BKQ_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH3_TXBD_IDX\t\t\t(Offset 0x03AC) */\n\n#define BIT_SHIFT_ACH3_HW_IDX 16\n#define BIT_MASK_ACH3_HW_IDX 0xfff\n#define BIT_ACH3_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_ACH3_HW_IDX) << BIT_SHIFT_ACH3_HW_IDX)\n#define BITS_ACH3_HW_IDX (BIT_MASK_ACH3_HW_IDX << BIT_SHIFT_ACH3_HW_IDX)\n#define BIT_CLEAR_ACH3_HW_IDX(x) ((x) & (~BITS_ACH3_HW_IDX))\n#define BIT_GET_ACH3_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ACH3_HW_IDX) & BIT_MASK_ACH3_HW_IDX)\n#define BIT_SET_ACH3_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_ACH3_HW_IDX(x) | BIT_ACH3_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BKQ_TXBD_IDX\t\t\t(Offset 0x03AC) */\n\n#define BIT_SHIFT_BKQ_HOST_IDX 0\n#define BIT_MASK_BKQ_HOST_IDX 0xfff\n#define BIT_BKQ_HOST_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_BKQ_HOST_IDX) << BIT_SHIFT_BKQ_HOST_IDX)\n#define BITS_BKQ_HOST_IDX (BIT_MASK_BKQ_HOST_IDX << BIT_SHIFT_BKQ_HOST_IDX)\n#define BIT_CLEAR_BKQ_HOST_IDX(x) ((x) & (~BITS_BKQ_HOST_IDX))\n#define BIT_GET_BKQ_HOST_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_BKQ_HOST_IDX) & BIT_MASK_BKQ_HOST_IDX)\n#define BIT_SET_BKQ_HOST_IDX(x, v)                                             \\\n\t(BIT_CLEAR_BKQ_HOST_IDX(x) | BIT_BKQ_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH3_TXBD_IDX\t\t\t(Offset 0x03AC) */\n\n#define BIT_SHIFT_ACH3_HOST_IDX 0\n#define BIT_MASK_ACH3_HOST_IDX 0xfff\n#define BIT_ACH3_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_ACH3_HOST_IDX) << BIT_SHIFT_ACH3_HOST_IDX)\n#define BITS_ACH3_HOST_IDX (BIT_MASK_ACH3_HOST_IDX << BIT_SHIFT_ACH3_HOST_IDX)\n#define BIT_CLEAR_ACH3_HOST_IDX(x) ((x) & (~BITS_ACH3_HOST_IDX))\n#define BIT_GET_ACH3_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH3_HOST_IDX) & BIT_MASK_ACH3_HOST_IDX)\n#define BIT_SET_ACH3_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_ACH3_HOST_IDX(x) | BIT_ACH3_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MGQ_TXBD_IDX\t\t\t(Offset 0x03B0) */\n\n#define BIT_SHIFT_MGQ_HW_IDX 16\n#define BIT_MASK_MGQ_HW_IDX 0xfff\n#define BIT_MGQ_HW_IDX(x) (((x) & BIT_MASK_MGQ_HW_IDX) << BIT_SHIFT_MGQ_HW_IDX)\n#define BITS_MGQ_HW_IDX (BIT_MASK_MGQ_HW_IDX << BIT_SHIFT_MGQ_HW_IDX)\n#define BIT_CLEAR_MGQ_HW_IDX(x) ((x) & (~BITS_MGQ_HW_IDX))\n#define BIT_GET_MGQ_HW_IDX(x)                                                  \\\n\t(((x) >> BIT_SHIFT_MGQ_HW_IDX) & BIT_MASK_MGQ_HW_IDX)\n#define BIT_SET_MGQ_HW_IDX(x, v) (BIT_CLEAR_MGQ_HW_IDX(x) | BIT_MGQ_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0MGQ_TXBD_IDX\t\t\t(Offset 0x03B0) */\n\n#define BIT_SHIFT_P0MGQ_HW_IDX 16\n#define BIT_MASK_P0MGQ_HW_IDX 0xfff\n#define BIT_P0MGQ_HW_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_P0MGQ_HW_IDX) << BIT_SHIFT_P0MGQ_HW_IDX)\n#define BITS_P0MGQ_HW_IDX (BIT_MASK_P0MGQ_HW_IDX << BIT_SHIFT_P0MGQ_HW_IDX)\n#define BIT_CLEAR_P0MGQ_HW_IDX(x) ((x) & (~BITS_P0MGQ_HW_IDX))\n#define BIT_GET_P0MGQ_HW_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_P0MGQ_HW_IDX) & BIT_MASK_P0MGQ_HW_IDX)\n#define BIT_SET_P0MGQ_HW_IDX(x, v)                                             \\\n\t(BIT_CLEAR_P0MGQ_HW_IDX(x) | BIT_P0MGQ_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MGQ_TXBD_IDX\t\t\t(Offset 0x03B0) */\n\n#define BIT_SHIFT_MGQ_HOST_IDX 0\n#define BIT_MASK_MGQ_HOST_IDX 0xfff\n#define BIT_MGQ_HOST_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_MGQ_HOST_IDX) << BIT_SHIFT_MGQ_HOST_IDX)\n#define BITS_MGQ_HOST_IDX (BIT_MASK_MGQ_HOST_IDX << BIT_SHIFT_MGQ_HOST_IDX)\n#define BIT_CLEAR_MGQ_HOST_IDX(x) ((x) & (~BITS_MGQ_HOST_IDX))\n#define BIT_GET_MGQ_HOST_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_MGQ_HOST_IDX) & BIT_MASK_MGQ_HOST_IDX)\n#define BIT_SET_MGQ_HOST_IDX(x, v)                                             \\\n\t(BIT_CLEAR_MGQ_HOST_IDX(x) | BIT_MGQ_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0MGQ_TXBD_IDX\t\t\t(Offset 0x03B0) */\n\n#define BIT_SHIFT_P0MGQ_HOST_IDX 0\n#define BIT_MASK_P0MGQ_HOST_IDX 0xfff\n#define BIT_P0MGQ_HOST_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_P0MGQ_HOST_IDX) << BIT_SHIFT_P0MGQ_HOST_IDX)\n#define BITS_P0MGQ_HOST_IDX                                                    \\\n\t(BIT_MASK_P0MGQ_HOST_IDX << BIT_SHIFT_P0MGQ_HOST_IDX)\n#define BIT_CLEAR_P0MGQ_HOST_IDX(x) ((x) & (~BITS_P0MGQ_HOST_IDX))\n#define BIT_GET_P0MGQ_HOST_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_P0MGQ_HOST_IDX) & BIT_MASK_P0MGQ_HOST_IDX)\n#define BIT_SET_P0MGQ_HOST_IDX(x, v)                                           \\\n\t(BIT_CLEAR_P0MGQ_HOST_IDX(x) | BIT_P0MGQ_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXQ_RXBD_IDX\t\t\t(Offset 0x03B4) */\n\n#define BIT_SHIFT_RXQ_HW_IDX 16\n#define BIT_MASK_RXQ_HW_IDX 0xfff\n#define BIT_RXQ_HW_IDX(x) (((x) & BIT_MASK_RXQ_HW_IDX) << BIT_SHIFT_RXQ_HW_IDX)\n#define BITS_RXQ_HW_IDX (BIT_MASK_RXQ_HW_IDX << BIT_SHIFT_RXQ_HW_IDX)\n#define BIT_CLEAR_RXQ_HW_IDX(x) ((x) & (~BITS_RXQ_HW_IDX))\n#define BIT_GET_RXQ_HW_IDX(x)                                                  \\\n\t(((x) >> BIT_SHIFT_RXQ_HW_IDX) & BIT_MASK_RXQ_HW_IDX)\n#define BIT_SET_RXQ_HW_IDX(x, v) (BIT_CLEAR_RXQ_HW_IDX(x) | BIT_RXQ_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0RXQ_RXBD_IDX\t\t\t(Offset 0x03B4) */\n\n#define BIT_SHIFT_P0RXQ_HW_IDX 16\n#define BIT_MASK_P0RXQ_HW_IDX 0xfff\n#define BIT_P0RXQ_HW_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_P0RXQ_HW_IDX) << BIT_SHIFT_P0RXQ_HW_IDX)\n#define BITS_P0RXQ_HW_IDX (BIT_MASK_P0RXQ_HW_IDX << BIT_SHIFT_P0RXQ_HW_IDX)\n#define BIT_CLEAR_P0RXQ_HW_IDX(x) ((x) & (~BITS_P0RXQ_HW_IDX))\n#define BIT_GET_P0RXQ_HW_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_P0RXQ_HW_IDX) & BIT_MASK_P0RXQ_HW_IDX)\n#define BIT_SET_P0RXQ_HW_IDX(x, v)                                             \\\n\t(BIT_CLEAR_P0RXQ_HW_IDX(x) | BIT_P0RXQ_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXQ_RXBD_IDX\t\t\t(Offset 0x03B4) */\n\n#define BIT_SHIFT_RXQ_HOST_IDX 0\n#define BIT_MASK_RXQ_HOST_IDX 0xfff\n#define BIT_RXQ_HOST_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_RXQ_HOST_IDX) << BIT_SHIFT_RXQ_HOST_IDX)\n#define BITS_RXQ_HOST_IDX (BIT_MASK_RXQ_HOST_IDX << BIT_SHIFT_RXQ_HOST_IDX)\n#define BIT_CLEAR_RXQ_HOST_IDX(x) ((x) & (~BITS_RXQ_HOST_IDX))\n#define BIT_GET_RXQ_HOST_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_RXQ_HOST_IDX) & BIT_MASK_RXQ_HOST_IDX)\n#define BIT_SET_RXQ_HOST_IDX(x, v)                                             \\\n\t(BIT_CLEAR_RXQ_HOST_IDX(x) | BIT_RXQ_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0RXQ_RXBD_IDX\t\t\t(Offset 0x03B4) */\n\n#define BIT_SHIFT_P0RXQ_HOST_IDX 0\n#define BIT_MASK_P0RXQ_HOST_IDX 0xfff\n#define BIT_P0RXQ_HOST_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_P0RXQ_HOST_IDX) << BIT_SHIFT_P0RXQ_HOST_IDX)\n#define BITS_P0RXQ_HOST_IDX                                                    \\\n\t(BIT_MASK_P0RXQ_HOST_IDX << BIT_SHIFT_P0RXQ_HOST_IDX)\n#define BIT_CLEAR_P0RXQ_HOST_IDX(x) ((x) & (~BITS_P0RXQ_HOST_IDX))\n#define BIT_GET_P0RXQ_HOST_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_P0RXQ_HOST_IDX) & BIT_MASK_P0RXQ_HOST_IDX)\n#define BIT_SET_P0RXQ_HOST_IDX(x, v)                                           \\\n\t(BIT_CLEAR_P0RXQ_HOST_IDX(x) | BIT_P0RXQ_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI0Q_TXBD_IDX\t\t\t(Offset 0x03B8) */\n\n#define BIT_SHIFT_HI0Q_HW_IDX 16\n#define BIT_MASK_HI0Q_HW_IDX 0xfff\n#define BIT_HI0Q_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_HI0Q_HW_IDX) << BIT_SHIFT_HI0Q_HW_IDX)\n#define BITS_HI0Q_HW_IDX (BIT_MASK_HI0Q_HW_IDX << BIT_SHIFT_HI0Q_HW_IDX)\n#define BIT_CLEAR_HI0Q_HW_IDX(x) ((x) & (~BITS_HI0Q_HW_IDX))\n#define BIT_GET_HI0Q_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HI0Q_HW_IDX) & BIT_MASK_HI0Q_HW_IDX)\n#define BIT_SET_HI0Q_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_HI0Q_HW_IDX(x) | BIT_HI0Q_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI0Q_TXBD_IDX\t\t\t(Offset 0x03B8) */\n\n#define BIT_SHIFT_P0HI0Q_HW_IDX 16\n#define BIT_MASK_P0HI0Q_HW_IDX 0xfff\n#define BIT_P0HI0Q_HW_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_P0HI0Q_HW_IDX) << BIT_SHIFT_P0HI0Q_HW_IDX)\n#define BITS_P0HI0Q_HW_IDX (BIT_MASK_P0HI0Q_HW_IDX << BIT_SHIFT_P0HI0Q_HW_IDX)\n#define BIT_CLEAR_P0HI0Q_HW_IDX(x) ((x) & (~BITS_P0HI0Q_HW_IDX))\n#define BIT_GET_P0HI0Q_HW_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_P0HI0Q_HW_IDX) & BIT_MASK_P0HI0Q_HW_IDX)\n#define BIT_SET_P0HI0Q_HW_IDX(x, v)                                            \\\n\t(BIT_CLEAR_P0HI0Q_HW_IDX(x) | BIT_P0HI0Q_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI0Q_TXBD_IDX\t\t\t(Offset 0x03B8) */\n\n#define BIT_SHIFT_HI0Q_HOST_IDX 0\n#define BIT_MASK_HI0Q_HOST_IDX 0xfff\n#define BIT_HI0Q_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_HI0Q_HOST_IDX) << BIT_SHIFT_HI0Q_HOST_IDX)\n#define BITS_HI0Q_HOST_IDX (BIT_MASK_HI0Q_HOST_IDX << BIT_SHIFT_HI0Q_HOST_IDX)\n#define BIT_CLEAR_HI0Q_HOST_IDX(x) ((x) & (~BITS_HI0Q_HOST_IDX))\n#define BIT_GET_HI0Q_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI0Q_HOST_IDX) & BIT_MASK_HI0Q_HOST_IDX)\n#define BIT_SET_HI0Q_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_HI0Q_HOST_IDX(x) | BIT_HI0Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI0Q_TXBD_IDX\t\t\t(Offset 0x03B8) */\n\n#define BIT_SHIFT_P0HI0Q_HOST_IDX 0\n#define BIT_MASK_P0HI0Q_HOST_IDX 0xfff\n#define BIT_P0HI0Q_HOST_IDX(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI0Q_HOST_IDX) << BIT_SHIFT_P0HI0Q_HOST_IDX)\n#define BITS_P0HI0Q_HOST_IDX                                                   \\\n\t(BIT_MASK_P0HI0Q_HOST_IDX << BIT_SHIFT_P0HI0Q_HOST_IDX)\n#define BIT_CLEAR_P0HI0Q_HOST_IDX(x) ((x) & (~BITS_P0HI0Q_HOST_IDX))\n#define BIT_GET_P0HI0Q_HOST_IDX(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI0Q_HOST_IDX) & BIT_MASK_P0HI0Q_HOST_IDX)\n#define BIT_SET_P0HI0Q_HOST_IDX(x, v)                                          \\\n\t(BIT_CLEAR_P0HI0Q_HOST_IDX(x) | BIT_P0HI0Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI1Q_TXBD_IDX\t\t\t(Offset 0x03BC) */\n\n#define BIT_SHIFT_HI1Q_HW_IDX 16\n#define BIT_MASK_HI1Q_HW_IDX 0xfff\n#define BIT_HI1Q_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_HI1Q_HW_IDX) << BIT_SHIFT_HI1Q_HW_IDX)\n#define BITS_HI1Q_HW_IDX (BIT_MASK_HI1Q_HW_IDX << BIT_SHIFT_HI1Q_HW_IDX)\n#define BIT_CLEAR_HI1Q_HW_IDX(x) ((x) & (~BITS_HI1Q_HW_IDX))\n#define BIT_GET_HI1Q_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HI1Q_HW_IDX) & BIT_MASK_HI1Q_HW_IDX)\n#define BIT_SET_HI1Q_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_HI1Q_HW_IDX(x) | BIT_HI1Q_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI1Q_TXBD_IDX\t\t\t(Offset 0x03BC) */\n\n#define BIT_SHIFT_P0HI1Q_HW_IDX 16\n#define BIT_MASK_P0HI1Q_HW_IDX 0xfff\n#define BIT_P0HI1Q_HW_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_P0HI1Q_HW_IDX) << BIT_SHIFT_P0HI1Q_HW_IDX)\n#define BITS_P0HI1Q_HW_IDX (BIT_MASK_P0HI1Q_HW_IDX << BIT_SHIFT_P0HI1Q_HW_IDX)\n#define BIT_CLEAR_P0HI1Q_HW_IDX(x) ((x) & (~BITS_P0HI1Q_HW_IDX))\n#define BIT_GET_P0HI1Q_HW_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_P0HI1Q_HW_IDX) & BIT_MASK_P0HI1Q_HW_IDX)\n#define BIT_SET_P0HI1Q_HW_IDX(x, v)                                            \\\n\t(BIT_CLEAR_P0HI1Q_HW_IDX(x) | BIT_P0HI1Q_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI1Q_TXBD_IDX\t\t\t(Offset 0x03BC) */\n\n#define BIT_SHIFT_HI1Q_HOST_IDX 0\n#define BIT_MASK_HI1Q_HOST_IDX 0xfff\n#define BIT_HI1Q_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_HI1Q_HOST_IDX) << BIT_SHIFT_HI1Q_HOST_IDX)\n#define BITS_HI1Q_HOST_IDX (BIT_MASK_HI1Q_HOST_IDX << BIT_SHIFT_HI1Q_HOST_IDX)\n#define BIT_CLEAR_HI1Q_HOST_IDX(x) ((x) & (~BITS_HI1Q_HOST_IDX))\n#define BIT_GET_HI1Q_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI1Q_HOST_IDX) & BIT_MASK_HI1Q_HOST_IDX)\n#define BIT_SET_HI1Q_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_HI1Q_HOST_IDX(x) | BIT_HI1Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI1Q_TXBD_IDX\t\t\t(Offset 0x03BC) */\n\n#define BIT_SHIFT_P0HI1Q_HOST_IDX 0\n#define BIT_MASK_P0HI1Q_HOST_IDX 0xfff\n#define BIT_P0HI1Q_HOST_IDX(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI1Q_HOST_IDX) << BIT_SHIFT_P0HI1Q_HOST_IDX)\n#define BITS_P0HI1Q_HOST_IDX                                                   \\\n\t(BIT_MASK_P0HI1Q_HOST_IDX << BIT_SHIFT_P0HI1Q_HOST_IDX)\n#define BIT_CLEAR_P0HI1Q_HOST_IDX(x) ((x) & (~BITS_P0HI1Q_HOST_IDX))\n#define BIT_GET_P0HI1Q_HOST_IDX(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI1Q_HOST_IDX) & BIT_MASK_P0HI1Q_HOST_IDX)\n#define BIT_SET_P0HI1Q_HOST_IDX(x, v)                                          \\\n\t(BIT_CLEAR_P0HI1Q_HOST_IDX(x) | BIT_P0HI1Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI2Q_TXBD_IDX\t\t\t(Offset 0x03C0) */\n\n#define BIT_SHIFT_HI2Q_HW_IDX 16\n#define BIT_MASK_HI2Q_HW_IDX 0xfff\n#define BIT_HI2Q_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_HI2Q_HW_IDX) << BIT_SHIFT_HI2Q_HW_IDX)\n#define BITS_HI2Q_HW_IDX (BIT_MASK_HI2Q_HW_IDX << BIT_SHIFT_HI2Q_HW_IDX)\n#define BIT_CLEAR_HI2Q_HW_IDX(x) ((x) & (~BITS_HI2Q_HW_IDX))\n#define BIT_GET_HI2Q_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HI2Q_HW_IDX) & BIT_MASK_HI2Q_HW_IDX)\n#define BIT_SET_HI2Q_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_HI2Q_HW_IDX(x) | BIT_HI2Q_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI2Q_TXBD_IDX\t\t\t(Offset 0x03C0) */\n\n#define BIT_SHIFT_P0HI2Q_HW_IDX 16\n#define BIT_MASK_P0HI2Q_HW_IDX 0xfff\n#define BIT_P0HI2Q_HW_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_P0HI2Q_HW_IDX) << BIT_SHIFT_P0HI2Q_HW_IDX)\n#define BITS_P0HI2Q_HW_IDX (BIT_MASK_P0HI2Q_HW_IDX << BIT_SHIFT_P0HI2Q_HW_IDX)\n#define BIT_CLEAR_P0HI2Q_HW_IDX(x) ((x) & (~BITS_P0HI2Q_HW_IDX))\n#define BIT_GET_P0HI2Q_HW_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_P0HI2Q_HW_IDX) & BIT_MASK_P0HI2Q_HW_IDX)\n#define BIT_SET_P0HI2Q_HW_IDX(x, v)                                            \\\n\t(BIT_CLEAR_P0HI2Q_HW_IDX(x) | BIT_P0HI2Q_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI2Q_TXBD_IDX\t\t\t(Offset 0x03C0) */\n\n#define BIT_SHIFT_HI2Q_HOST_IDX 0\n#define BIT_MASK_HI2Q_HOST_IDX 0xfff\n#define BIT_HI2Q_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_HI2Q_HOST_IDX) << BIT_SHIFT_HI2Q_HOST_IDX)\n#define BITS_HI2Q_HOST_IDX (BIT_MASK_HI2Q_HOST_IDX << BIT_SHIFT_HI2Q_HOST_IDX)\n#define BIT_CLEAR_HI2Q_HOST_IDX(x) ((x) & (~BITS_HI2Q_HOST_IDX))\n#define BIT_GET_HI2Q_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI2Q_HOST_IDX) & BIT_MASK_HI2Q_HOST_IDX)\n#define BIT_SET_HI2Q_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_HI2Q_HOST_IDX(x) | BIT_HI2Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI2Q_TXBD_IDX\t\t\t(Offset 0x03C0) */\n\n#define BIT_SHIFT_P0HI2Q_HOST_IDX 0\n#define BIT_MASK_P0HI2Q_HOST_IDX 0xfff\n#define BIT_P0HI2Q_HOST_IDX(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI2Q_HOST_IDX) << BIT_SHIFT_P0HI2Q_HOST_IDX)\n#define BITS_P0HI2Q_HOST_IDX                                                   \\\n\t(BIT_MASK_P0HI2Q_HOST_IDX << BIT_SHIFT_P0HI2Q_HOST_IDX)\n#define BIT_CLEAR_P0HI2Q_HOST_IDX(x) ((x) & (~BITS_P0HI2Q_HOST_IDX))\n#define BIT_GET_P0HI2Q_HOST_IDX(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI2Q_HOST_IDX) & BIT_MASK_P0HI2Q_HOST_IDX)\n#define BIT_SET_P0HI2Q_HOST_IDX(x, v)                                          \\\n\t(BIT_CLEAR_P0HI2Q_HOST_IDX(x) | BIT_P0HI2Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI3Q_TXBD_IDX\t\t\t(Offset 0x03C4) */\n\n#define BIT_SHIFT_HI3Q_HW_IDX 16\n#define BIT_MASK_HI3Q_HW_IDX 0xfff\n#define BIT_HI3Q_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_HI3Q_HW_IDX) << BIT_SHIFT_HI3Q_HW_IDX)\n#define BITS_HI3Q_HW_IDX (BIT_MASK_HI3Q_HW_IDX << BIT_SHIFT_HI3Q_HW_IDX)\n#define BIT_CLEAR_HI3Q_HW_IDX(x) ((x) & (~BITS_HI3Q_HW_IDX))\n#define BIT_GET_HI3Q_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HI3Q_HW_IDX) & BIT_MASK_HI3Q_HW_IDX)\n#define BIT_SET_HI3Q_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_HI3Q_HW_IDX(x) | BIT_HI3Q_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI3Q_TXBD_IDX\t\t\t(Offset 0x03C4) */\n\n#define BIT_SHIFT_P0HI3Q_HW_IDX 16\n#define BIT_MASK_P0HI3Q_HW_IDX 0xfff\n#define BIT_P0HI3Q_HW_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_P0HI3Q_HW_IDX) << BIT_SHIFT_P0HI3Q_HW_IDX)\n#define BITS_P0HI3Q_HW_IDX (BIT_MASK_P0HI3Q_HW_IDX << BIT_SHIFT_P0HI3Q_HW_IDX)\n#define BIT_CLEAR_P0HI3Q_HW_IDX(x) ((x) & (~BITS_P0HI3Q_HW_IDX))\n#define BIT_GET_P0HI3Q_HW_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_P0HI3Q_HW_IDX) & BIT_MASK_P0HI3Q_HW_IDX)\n#define BIT_SET_P0HI3Q_HW_IDX(x, v)                                            \\\n\t(BIT_CLEAR_P0HI3Q_HW_IDX(x) | BIT_P0HI3Q_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI3Q_TXBD_IDX\t\t\t(Offset 0x03C4) */\n\n#define BIT_SHIFT_HI3Q_HOST_IDX 0\n#define BIT_MASK_HI3Q_HOST_IDX 0xfff\n#define BIT_HI3Q_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_HI3Q_HOST_IDX) << BIT_SHIFT_HI3Q_HOST_IDX)\n#define BITS_HI3Q_HOST_IDX (BIT_MASK_HI3Q_HOST_IDX << BIT_SHIFT_HI3Q_HOST_IDX)\n#define BIT_CLEAR_HI3Q_HOST_IDX(x) ((x) & (~BITS_HI3Q_HOST_IDX))\n#define BIT_GET_HI3Q_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI3Q_HOST_IDX) & BIT_MASK_HI3Q_HOST_IDX)\n#define BIT_SET_HI3Q_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_HI3Q_HOST_IDX(x) | BIT_HI3Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI3Q_TXBD_IDX\t\t\t(Offset 0x03C4) */\n\n#define BIT_SHIFT_P0HI3Q_HOST_IDX 0\n#define BIT_MASK_P0HI3Q_HOST_IDX 0xfff\n#define BIT_P0HI3Q_HOST_IDX(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI3Q_HOST_IDX) << BIT_SHIFT_P0HI3Q_HOST_IDX)\n#define BITS_P0HI3Q_HOST_IDX                                                   \\\n\t(BIT_MASK_P0HI3Q_HOST_IDX << BIT_SHIFT_P0HI3Q_HOST_IDX)\n#define BIT_CLEAR_P0HI3Q_HOST_IDX(x) ((x) & (~BITS_P0HI3Q_HOST_IDX))\n#define BIT_GET_P0HI3Q_HOST_IDX(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI3Q_HOST_IDX) & BIT_MASK_P0HI3Q_HOST_IDX)\n#define BIT_SET_P0HI3Q_HOST_IDX(x, v)                                          \\\n\t(BIT_CLEAR_P0HI3Q_HOST_IDX(x) | BIT_P0HI3Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI4Q_TXBD_IDX\t\t\t(Offset 0x03C8) */\n\n#define BIT_SHIFT_HI4Q_HW_IDX 16\n#define BIT_MASK_HI4Q_HW_IDX 0xfff\n#define BIT_HI4Q_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_HI4Q_HW_IDX) << BIT_SHIFT_HI4Q_HW_IDX)\n#define BITS_HI4Q_HW_IDX (BIT_MASK_HI4Q_HW_IDX << BIT_SHIFT_HI4Q_HW_IDX)\n#define BIT_CLEAR_HI4Q_HW_IDX(x) ((x) & (~BITS_HI4Q_HW_IDX))\n#define BIT_GET_HI4Q_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HI4Q_HW_IDX) & BIT_MASK_HI4Q_HW_IDX)\n#define BIT_SET_HI4Q_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_HI4Q_HW_IDX(x) | BIT_HI4Q_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI4Q_TXBD_IDX\t\t\t(Offset 0x03C8) */\n\n#define BIT_SHIFT_P0HI4Q_HW_IDX 16\n#define BIT_MASK_P0HI4Q_HW_IDX 0xfff\n#define BIT_P0HI4Q_HW_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_P0HI4Q_HW_IDX) << BIT_SHIFT_P0HI4Q_HW_IDX)\n#define BITS_P0HI4Q_HW_IDX (BIT_MASK_P0HI4Q_HW_IDX << BIT_SHIFT_P0HI4Q_HW_IDX)\n#define BIT_CLEAR_P0HI4Q_HW_IDX(x) ((x) & (~BITS_P0HI4Q_HW_IDX))\n#define BIT_GET_P0HI4Q_HW_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_P0HI4Q_HW_IDX) & BIT_MASK_P0HI4Q_HW_IDX)\n#define BIT_SET_P0HI4Q_HW_IDX(x, v)                                            \\\n\t(BIT_CLEAR_P0HI4Q_HW_IDX(x) | BIT_P0HI4Q_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI4Q_TXBD_IDX\t\t\t(Offset 0x03C8) */\n\n#define BIT_SHIFT_HI4Q_HOST_IDX 0\n#define BIT_MASK_HI4Q_HOST_IDX 0xfff\n#define BIT_HI4Q_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_HI4Q_HOST_IDX) << BIT_SHIFT_HI4Q_HOST_IDX)\n#define BITS_HI4Q_HOST_IDX (BIT_MASK_HI4Q_HOST_IDX << BIT_SHIFT_HI4Q_HOST_IDX)\n#define BIT_CLEAR_HI4Q_HOST_IDX(x) ((x) & (~BITS_HI4Q_HOST_IDX))\n#define BIT_GET_HI4Q_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI4Q_HOST_IDX) & BIT_MASK_HI4Q_HOST_IDX)\n#define BIT_SET_HI4Q_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_HI4Q_HOST_IDX(x) | BIT_HI4Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI4Q_TXBD_IDX\t\t\t(Offset 0x03C8) */\n\n#define BIT_SHIFT_P0HI4Q_HOST_IDX 0\n#define BIT_MASK_P0HI4Q_HOST_IDX 0xfff\n#define BIT_P0HI4Q_HOST_IDX(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI4Q_HOST_IDX) << BIT_SHIFT_P0HI4Q_HOST_IDX)\n#define BITS_P0HI4Q_HOST_IDX                                                   \\\n\t(BIT_MASK_P0HI4Q_HOST_IDX << BIT_SHIFT_P0HI4Q_HOST_IDX)\n#define BIT_CLEAR_P0HI4Q_HOST_IDX(x) ((x) & (~BITS_P0HI4Q_HOST_IDX))\n#define BIT_GET_P0HI4Q_HOST_IDX(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI4Q_HOST_IDX) & BIT_MASK_P0HI4Q_HOST_IDX)\n#define BIT_SET_P0HI4Q_HOST_IDX(x, v)                                          \\\n\t(BIT_CLEAR_P0HI4Q_HOST_IDX(x) | BIT_P0HI4Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI5Q_TXBD_IDX\t\t\t(Offset 0x03CC) */\n\n#define BIT_SHIFT_HI5Q_HW_IDX 16\n#define BIT_MASK_HI5Q_HW_IDX 0xfff\n#define BIT_HI5Q_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_HI5Q_HW_IDX) << BIT_SHIFT_HI5Q_HW_IDX)\n#define BITS_HI5Q_HW_IDX (BIT_MASK_HI5Q_HW_IDX << BIT_SHIFT_HI5Q_HW_IDX)\n#define BIT_CLEAR_HI5Q_HW_IDX(x) ((x) & (~BITS_HI5Q_HW_IDX))\n#define BIT_GET_HI5Q_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HI5Q_HW_IDX) & BIT_MASK_HI5Q_HW_IDX)\n#define BIT_SET_HI5Q_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_HI5Q_HW_IDX(x) | BIT_HI5Q_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI5Q_TXBD_IDX\t\t\t(Offset 0x03CC) */\n\n#define BIT_SHIFT_P0HI5Q_HW_IDX 16\n#define BIT_MASK_P0HI5Q_HW_IDX 0xfff\n#define BIT_P0HI5Q_HW_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_P0HI5Q_HW_IDX) << BIT_SHIFT_P0HI5Q_HW_IDX)\n#define BITS_P0HI5Q_HW_IDX (BIT_MASK_P0HI5Q_HW_IDX << BIT_SHIFT_P0HI5Q_HW_IDX)\n#define BIT_CLEAR_P0HI5Q_HW_IDX(x) ((x) & (~BITS_P0HI5Q_HW_IDX))\n#define BIT_GET_P0HI5Q_HW_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_P0HI5Q_HW_IDX) & BIT_MASK_P0HI5Q_HW_IDX)\n#define BIT_SET_P0HI5Q_HW_IDX(x, v)                                            \\\n\t(BIT_CLEAR_P0HI5Q_HW_IDX(x) | BIT_P0HI5Q_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI5Q_TXBD_IDX\t\t\t(Offset 0x03CC) */\n\n#define BIT_SHIFT_HI5Q_HOST_IDX 0\n#define BIT_MASK_HI5Q_HOST_IDX 0xfff\n#define BIT_HI5Q_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_HI5Q_HOST_IDX) << BIT_SHIFT_HI5Q_HOST_IDX)\n#define BITS_HI5Q_HOST_IDX (BIT_MASK_HI5Q_HOST_IDX << BIT_SHIFT_HI5Q_HOST_IDX)\n#define BIT_CLEAR_HI5Q_HOST_IDX(x) ((x) & (~BITS_HI5Q_HOST_IDX))\n#define BIT_GET_HI5Q_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI5Q_HOST_IDX) & BIT_MASK_HI5Q_HOST_IDX)\n#define BIT_SET_HI5Q_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_HI5Q_HOST_IDX(x) | BIT_HI5Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI5Q_TXBD_IDX\t\t\t(Offset 0x03CC) */\n\n#define BIT_SHIFT_P0HI5Q_HOST_IDX 0\n#define BIT_MASK_P0HI5Q_HOST_IDX 0xfff\n#define BIT_P0HI5Q_HOST_IDX(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI5Q_HOST_IDX) << BIT_SHIFT_P0HI5Q_HOST_IDX)\n#define BITS_P0HI5Q_HOST_IDX                                                   \\\n\t(BIT_MASK_P0HI5Q_HOST_IDX << BIT_SHIFT_P0HI5Q_HOST_IDX)\n#define BIT_CLEAR_P0HI5Q_HOST_IDX(x) ((x) & (~BITS_P0HI5Q_HOST_IDX))\n#define BIT_GET_P0HI5Q_HOST_IDX(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI5Q_HOST_IDX) & BIT_MASK_P0HI5Q_HOST_IDX)\n#define BIT_SET_P0HI5Q_HOST_IDX(x, v)                                          \\\n\t(BIT_CLEAR_P0HI5Q_HOST_IDX(x) | BIT_P0HI5Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI6Q_TXBD_IDX\t\t\t(Offset 0x03D0) */\n\n#define BIT_SHIFT_HI6Q_HW_IDX 16\n#define BIT_MASK_HI6Q_HW_IDX 0xfff\n#define BIT_HI6Q_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_HI6Q_HW_IDX) << BIT_SHIFT_HI6Q_HW_IDX)\n#define BITS_HI6Q_HW_IDX (BIT_MASK_HI6Q_HW_IDX << BIT_SHIFT_HI6Q_HW_IDX)\n#define BIT_CLEAR_HI6Q_HW_IDX(x) ((x) & (~BITS_HI6Q_HW_IDX))\n#define BIT_GET_HI6Q_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HI6Q_HW_IDX) & BIT_MASK_HI6Q_HW_IDX)\n#define BIT_SET_HI6Q_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_HI6Q_HW_IDX(x) | BIT_HI6Q_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI6Q_TXBD_IDX\t\t\t(Offset 0x03D0) */\n\n#define BIT_SHIFT_P0HI6Q_HW_IDX 16\n#define BIT_MASK_P0HI6Q_HW_IDX 0xfff\n#define BIT_P0HI6Q_HW_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_P0HI6Q_HW_IDX) << BIT_SHIFT_P0HI6Q_HW_IDX)\n#define BITS_P0HI6Q_HW_IDX (BIT_MASK_P0HI6Q_HW_IDX << BIT_SHIFT_P0HI6Q_HW_IDX)\n#define BIT_CLEAR_P0HI6Q_HW_IDX(x) ((x) & (~BITS_P0HI6Q_HW_IDX))\n#define BIT_GET_P0HI6Q_HW_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_P0HI6Q_HW_IDX) & BIT_MASK_P0HI6Q_HW_IDX)\n#define BIT_SET_P0HI6Q_HW_IDX(x, v)                                            \\\n\t(BIT_CLEAR_P0HI6Q_HW_IDX(x) | BIT_P0HI6Q_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI6Q_TXBD_IDX\t\t\t(Offset 0x03D0) */\n\n#define BIT_SHIFT_HI6Q_HOST_IDX 0\n#define BIT_MASK_HI6Q_HOST_IDX 0xfff\n#define BIT_HI6Q_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_HI6Q_HOST_IDX) << BIT_SHIFT_HI6Q_HOST_IDX)\n#define BITS_HI6Q_HOST_IDX (BIT_MASK_HI6Q_HOST_IDX << BIT_SHIFT_HI6Q_HOST_IDX)\n#define BIT_CLEAR_HI6Q_HOST_IDX(x) ((x) & (~BITS_HI6Q_HOST_IDX))\n#define BIT_GET_HI6Q_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI6Q_HOST_IDX) & BIT_MASK_HI6Q_HOST_IDX)\n#define BIT_SET_HI6Q_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_HI6Q_HOST_IDX(x) | BIT_HI6Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI6Q_TXBD_IDX\t\t\t(Offset 0x03D0) */\n\n#define BIT_SHIFT_P0HI6Q_HOST_IDX 0\n#define BIT_MASK_P0HI6Q_HOST_IDX 0xfff\n#define BIT_P0HI6Q_HOST_IDX(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI6Q_HOST_IDX) << BIT_SHIFT_P0HI6Q_HOST_IDX)\n#define BITS_P0HI6Q_HOST_IDX                                                   \\\n\t(BIT_MASK_P0HI6Q_HOST_IDX << BIT_SHIFT_P0HI6Q_HOST_IDX)\n#define BIT_CLEAR_P0HI6Q_HOST_IDX(x) ((x) & (~BITS_P0HI6Q_HOST_IDX))\n#define BIT_GET_P0HI6Q_HOST_IDX(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI6Q_HOST_IDX) & BIT_MASK_P0HI6Q_HOST_IDX)\n#define BIT_SET_P0HI6Q_HOST_IDX(x, v)                                          \\\n\t(BIT_CLEAR_P0HI6Q_HOST_IDX(x) | BIT_P0HI6Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI7Q_TXBD_IDX\t\t\t(Offset 0x03D4) */\n\n#define BIT_SHIFT_HI7Q_HW_IDX 16\n#define BIT_MASK_HI7Q_HW_IDX 0xfff\n#define BIT_HI7Q_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_HI7Q_HW_IDX) << BIT_SHIFT_HI7Q_HW_IDX)\n#define BITS_HI7Q_HW_IDX (BIT_MASK_HI7Q_HW_IDX << BIT_SHIFT_HI7Q_HW_IDX)\n#define BIT_CLEAR_HI7Q_HW_IDX(x) ((x) & (~BITS_HI7Q_HW_IDX))\n#define BIT_GET_HI7Q_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HI7Q_HW_IDX) & BIT_MASK_HI7Q_HW_IDX)\n#define BIT_SET_HI7Q_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_HI7Q_HW_IDX(x) | BIT_HI7Q_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI7Q_TXBD_IDX\t\t\t(Offset 0x03D4) */\n\n#define BIT_SHIFT_P0HI7Q_HW_IDX 16\n#define BIT_MASK_P0HI7Q_HW_IDX 0xfff\n#define BIT_P0HI7Q_HW_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_P0HI7Q_HW_IDX) << BIT_SHIFT_P0HI7Q_HW_IDX)\n#define BITS_P0HI7Q_HW_IDX (BIT_MASK_P0HI7Q_HW_IDX << BIT_SHIFT_P0HI7Q_HW_IDX)\n#define BIT_CLEAR_P0HI7Q_HW_IDX(x) ((x) & (~BITS_P0HI7Q_HW_IDX))\n#define BIT_GET_P0HI7Q_HW_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_P0HI7Q_HW_IDX) & BIT_MASK_P0HI7Q_HW_IDX)\n#define BIT_SET_P0HI7Q_HW_IDX(x, v)                                            \\\n\t(BIT_CLEAR_P0HI7Q_HW_IDX(x) | BIT_P0HI7Q_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HI7Q_TXBD_IDX\t\t\t(Offset 0x03D4) */\n\n#define BIT_SHIFT_HI7Q_HOST_IDX 0\n#define BIT_MASK_HI7Q_HOST_IDX 0xfff\n#define BIT_HI7Q_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_HI7Q_HOST_IDX) << BIT_SHIFT_HI7Q_HOST_IDX)\n#define BITS_HI7Q_HOST_IDX (BIT_MASK_HI7Q_HOST_IDX << BIT_SHIFT_HI7Q_HOST_IDX)\n#define BIT_CLEAR_HI7Q_HOST_IDX(x) ((x) & (~BITS_HI7Q_HOST_IDX))\n#define BIT_GET_HI7Q_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI7Q_HOST_IDX) & BIT_MASK_HI7Q_HOST_IDX)\n#define BIT_SET_HI7Q_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_HI7Q_HOST_IDX(x) | BIT_HI7Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI7Q_TXBD_IDX\t\t\t(Offset 0x03D4) */\n\n#define BIT_SHIFT_P0HI7Q_HOST_IDX 0\n#define BIT_MASK_P0HI7Q_HOST_IDX 0xfff\n#define BIT_P0HI7Q_HOST_IDX(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI7Q_HOST_IDX) << BIT_SHIFT_P0HI7Q_HOST_IDX)\n#define BITS_P0HI7Q_HOST_IDX                                                   \\\n\t(BIT_MASK_P0HI7Q_HOST_IDX << BIT_SHIFT_P0HI7Q_HOST_IDX)\n#define BIT_CLEAR_P0HI7Q_HOST_IDX(x) ((x) & (~BITS_P0HI7Q_HOST_IDX))\n#define BIT_GET_P0HI7Q_HOST_IDX(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI7Q_HOST_IDX) & BIT_MASK_P0HI7Q_HOST_IDX)\n#define BIT_SET_P0HI7Q_HOST_IDX(x, v)                                          \\\n\t(BIT_CLEAR_P0HI7Q_HOST_IDX(x) | BIT_P0HI7Q_HOST_IDX(v))\n\n/* 2 REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1\t(Offset 0x03D8) */\n\n#define BIT_DIS_TXDMA_PRE_V1 BIT(31)\n#define BIT_DIS_RXDMA_PRE_V1 BIT(30)\n\n#define BIT_SHIFT_HPS_CLKR_PCIE_V1 28\n#define BIT_MASK_HPS_CLKR_PCIE_V1 0x3\n#define BIT_HPS_CLKR_PCIE_V1(x)                                                \\\n\t(((x) & BIT_MASK_HPS_CLKR_PCIE_V1) << BIT_SHIFT_HPS_CLKR_PCIE_V1)\n#define BITS_HPS_CLKR_PCIE_V1                                                  \\\n\t(BIT_MASK_HPS_CLKR_PCIE_V1 << BIT_SHIFT_HPS_CLKR_PCIE_V1)\n#define BIT_CLEAR_HPS_CLKR_PCIE_V1(x) ((x) & (~BITS_HPS_CLKR_PCIE_V1))\n#define BIT_GET_HPS_CLKR_PCIE_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_HPS_CLKR_PCIE_V1) & BIT_MASK_HPS_CLKR_PCIE_V1)\n#define BIT_SET_HPS_CLKR_PCIE_V1(x, v)                                         \\\n\t(BIT_CLEAR_HPS_CLKR_PCIE_V1(x) | BIT_HPS_CLKR_PCIE_V1(v))\n\n#define BIT_PCIE_INT_V1 BIT(27)\n#define BIT_TXFLAG_EXIT_L1_EN_V1 BIT(26)\n#define BIT_EN_RXDMA_ALIGN_V2 BIT(25)\n#define BIT_EN_TXDMA_ALIGN_V2 BIT(24)\n\n#define BIT_SHIFT_PCIE_HCPWM_V1 16\n#define BIT_MASK_PCIE_HCPWM_V1 0xff\n#define BIT_PCIE_HCPWM_V1(x)                                                   \\\n\t(((x) & BIT_MASK_PCIE_HCPWM_V1) << BIT_SHIFT_PCIE_HCPWM_V1)\n#define BITS_PCIE_HCPWM_V1 (BIT_MASK_PCIE_HCPWM_V1 << BIT_SHIFT_PCIE_HCPWM_V1)\n#define BIT_CLEAR_PCIE_HCPWM_V1(x) ((x) & (~BITS_PCIE_HCPWM_V1))\n#define BIT_GET_PCIE_HCPWM_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_PCIE_HCPWM_V1) & BIT_MASK_PCIE_HCPWM_V1)\n#define BIT_SET_PCIE_HCPWM_V1(x, v)                                            \\\n\t(BIT_CLEAR_PCIE_HCPWM_V1(x) | BIT_PCIE_HCPWM_V1(v))\n\n#define BIT_SHIFT_PCIE_HRPWM_V1 8\n#define BIT_MASK_PCIE_HRPWM_V1 0xff\n#define BIT_PCIE_HRPWM_V1(x)                                                   \\\n\t(((x) & BIT_MASK_PCIE_HRPWM_V1) << BIT_SHIFT_PCIE_HRPWM_V1)\n#define BITS_PCIE_HRPWM_V1 (BIT_MASK_PCIE_HRPWM_V1 << BIT_SHIFT_PCIE_HRPWM_V1)\n#define BIT_CLEAR_PCIE_HRPWM_V1(x) ((x) & (~BITS_PCIE_HRPWM_V1))\n#define BIT_GET_PCIE_HRPWM_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_PCIE_HRPWM_V1) & BIT_MASK_PCIE_HRPWM_V1)\n#define BIT_SET_PCIE_HRPWM_V1(x, v)                                            \\\n\t(BIT_CLEAR_PCIE_HRPWM_V1(x) | BIT_PCIE_HRPWM_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DBG_SEL_V1\t\t\t\t(Offset 0x03D8) */\n\n#define BIT_SHIFT_DBG_SEL 0\n#define BIT_MASK_DBG_SEL 0xff\n#define BIT_DBG_SEL(x) (((x) & BIT_MASK_DBG_SEL) << BIT_SHIFT_DBG_SEL)\n#define BITS_DBG_SEL (BIT_MASK_DBG_SEL << BIT_SHIFT_DBG_SEL)\n#define BIT_CLEAR_DBG_SEL(x) ((x) & (~BITS_DBG_SEL))\n#define BIT_GET_DBG_SEL(x) (((x) >> BIT_SHIFT_DBG_SEL) & BIT_MASK_DBG_SEL)\n#define BIT_SET_DBG_SEL(x, v) (BIT_CLEAR_DBG_SEL(x) | BIT_DBG_SEL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PCIE_HRPWM1_V1\t\t\t(Offset 0x03D9) */\n\n#define BIT_SHIFT_PCIE_HRPWM 0\n#define BIT_MASK_PCIE_HRPWM 0xff\n#define BIT_PCIE_HRPWM(x) (((x) & BIT_MASK_PCIE_HRPWM) << BIT_SHIFT_PCIE_HRPWM)\n#define BITS_PCIE_HRPWM (BIT_MASK_PCIE_HRPWM << BIT_SHIFT_PCIE_HRPWM)\n#define BIT_CLEAR_PCIE_HRPWM(x) ((x) & (~BITS_PCIE_HRPWM))\n#define BIT_GET_PCIE_HRPWM(x)                                                  \\\n\t(((x) >> BIT_SHIFT_PCIE_HRPWM) & BIT_MASK_PCIE_HRPWM)\n#define BIT_SET_PCIE_HRPWM(x, v) (BIT_CLEAR_PCIE_HRPWM(x) | BIT_PCIE_HRPWM(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HCI_HRPWM1_V1\t\t\t(Offset 0x03D9) */\n\n#define BIT_SHIFT_HCI_HRPWM 0\n#define BIT_MASK_HCI_HRPWM 0xff\n#define BIT_HCI_HRPWM(x) (((x) & BIT_MASK_HCI_HRPWM) << BIT_SHIFT_HCI_HRPWM)\n#define BITS_HCI_HRPWM (BIT_MASK_HCI_HRPWM << BIT_SHIFT_HCI_HRPWM)\n#define BIT_CLEAR_HCI_HRPWM(x) ((x) & (~BITS_HCI_HRPWM))\n#define BIT_GET_HCI_HRPWM(x) (((x) >> BIT_SHIFT_HCI_HRPWM) & BIT_MASK_HCI_HRPWM)\n#define BIT_SET_HCI_HRPWM(x, v) (BIT_CLEAR_HCI_HRPWM(x) | BIT_HCI_HRPWM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PCIE_HCPWM1_V1\t\t\t(Offset 0x03DA) */\n\n#define BIT_SHIFT_PCIE_HCPWM 0\n#define BIT_MASK_PCIE_HCPWM 0xff\n#define BIT_PCIE_HCPWM(x) (((x) & BIT_MASK_PCIE_HCPWM) << BIT_SHIFT_PCIE_HCPWM)\n#define BITS_PCIE_HCPWM (BIT_MASK_PCIE_HCPWM << BIT_SHIFT_PCIE_HCPWM)\n#define BIT_CLEAR_PCIE_HCPWM(x) ((x) & (~BITS_PCIE_HCPWM))\n#define BIT_GET_PCIE_HCPWM(x)                                                  \\\n\t(((x) >> BIT_SHIFT_PCIE_HCPWM) & BIT_MASK_PCIE_HCPWM)\n#define BIT_SET_PCIE_HCPWM(x, v) (BIT_CLEAR_PCIE_HCPWM(x) | BIT_PCIE_HCPWM(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HCI_HCPWM1_V1\t\t\t(Offset 0x03DA) */\n\n#define BIT_SHIFT_HCI_HCPWM 0\n#define BIT_MASK_HCI_HCPWM 0xff\n#define BIT_HCI_HCPWM(x) (((x) & BIT_MASK_HCI_HCPWM) << BIT_SHIFT_HCI_HCPWM)\n#define BITS_HCI_HCPWM (BIT_MASK_HCI_HCPWM << BIT_SHIFT_HCI_HCPWM)\n#define BIT_CLEAR_HCI_HCPWM(x) ((x) & (~BITS_HCI_HCPWM))\n#define BIT_GET_HCI_HCPWM(x) (((x) >> BIT_SHIFT_HCI_HCPWM) & BIT_MASK_HCI_HCPWM)\n#define BIT_SET_HCI_HCPWM(x, v) (BIT_CLEAR_HCI_HCPWM(x) | BIT_HCI_HCPWM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PCIE_CTRL2\t\t\t\t(Offset 0x03DB) */\n\n#define BIT_SHIFT_HPS_CLKR_PCIE 4\n#define BIT_MASK_HPS_CLKR_PCIE 0x3\n#define BIT_HPS_CLKR_PCIE(x)                                                   \\\n\t(((x) & BIT_MASK_HPS_CLKR_PCIE) << BIT_SHIFT_HPS_CLKR_PCIE)\n#define BITS_HPS_CLKR_PCIE (BIT_MASK_HPS_CLKR_PCIE << BIT_SHIFT_HPS_CLKR_PCIE)\n#define BIT_CLEAR_HPS_CLKR_PCIE(x) ((x) & (~BITS_HPS_CLKR_PCIE))\n#define BIT_GET_HPS_CLKR_PCIE(x)                                               \\\n\t(((x) >> BIT_SHIFT_HPS_CLKR_PCIE) & BIT_MASK_HPS_CLKR_PCIE)\n#define BIT_SET_HPS_CLKR_PCIE(x, v)                                            \\\n\t(BIT_CLEAR_HPS_CLKR_PCIE(x) | BIT_HPS_CLKR_PCIE(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HCI_CTRL2\t\t\t\t(Offset 0x03DB) */\n\n#define BIT_SHIFT_HPS_CLKR_HCI 4\n#define BIT_MASK_HPS_CLKR_HCI 0x3\n#define BIT_HPS_CLKR_HCI(x)                                                    \\\n\t(((x) & BIT_MASK_HPS_CLKR_HCI) << BIT_SHIFT_HPS_CLKR_HCI)\n#define BITS_HPS_CLKR_HCI (BIT_MASK_HPS_CLKR_HCI << BIT_SHIFT_HPS_CLKR_HCI)\n#define BIT_CLEAR_HPS_CLKR_HCI(x) ((x) & (~BITS_HPS_CLKR_HCI))\n#define BIT_GET_HPS_CLKR_HCI(x)                                                \\\n\t(((x) >> BIT_SHIFT_HPS_CLKR_HCI) & BIT_MASK_HPS_CLKR_HCI)\n#define BIT_SET_HPS_CLKR_HCI(x, v)                                             \\\n\t(BIT_CLEAR_HPS_CLKR_HCI(x) | BIT_HPS_CLKR_HCI(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PCIE_CTRL2\t\t\t\t(Offset 0x03DB) */\n\n#define BIT_PCIE_INT BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HCI_CTRL2\t\t\t\t(Offset 0x03DB) */\n\n#define BIT_HCI_INT BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PCIE_CTRL2\t\t\t\t(Offset 0x03DB) */\n\n#define BIT_EN_RXDMA_ALIGN BIT(1)\n#define BIT_EN_TXDMA_ALIGN BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PCIE_HRPWM2_HCPWM2_V1\t\t(Offset 0x03DC) */\n\n#define BIT_SHIFT_PCIE_HCPWM2_V1 16\n#define BIT_MASK_PCIE_HCPWM2_V1 0xffff\n#define BIT_PCIE_HCPWM2_V1(x)                                                  \\\n\t(((x) & BIT_MASK_PCIE_HCPWM2_V1) << BIT_SHIFT_PCIE_HCPWM2_V1)\n#define BITS_PCIE_HCPWM2_V1                                                    \\\n\t(BIT_MASK_PCIE_HCPWM2_V1 << BIT_SHIFT_PCIE_HCPWM2_V1)\n#define BIT_CLEAR_PCIE_HCPWM2_V1(x) ((x) & (~BITS_PCIE_HCPWM2_V1))\n#define BIT_GET_PCIE_HCPWM2_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_PCIE_HCPWM2_V1) & BIT_MASK_PCIE_HCPWM2_V1)\n#define BIT_SET_PCIE_HCPWM2_V1(x, v)                                           \\\n\t(BIT_CLEAR_PCIE_HCPWM2_V1(x) | BIT_PCIE_HCPWM2_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PCIE_HRPWM2_V1\t\t\t(Offset 0x03DC) */\n\n#define BIT_SHIFT_PCIE_HRPWM2 0\n#define BIT_MASK_PCIE_HRPWM2 0xffff\n#define BIT_PCIE_HRPWM2(x)                                                     \\\n\t(((x) & BIT_MASK_PCIE_HRPWM2) << BIT_SHIFT_PCIE_HRPWM2)\n#define BITS_PCIE_HRPWM2 (BIT_MASK_PCIE_HRPWM2 << BIT_SHIFT_PCIE_HRPWM2)\n#define BIT_CLEAR_PCIE_HRPWM2(x) ((x) & (~BITS_PCIE_HRPWM2))\n#define BIT_GET_PCIE_HRPWM2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_PCIE_HRPWM2) & BIT_MASK_PCIE_HRPWM2)\n#define BIT_SET_PCIE_HRPWM2(x, v)                                              \\\n\t(BIT_CLEAR_PCIE_HRPWM2(x) | BIT_PCIE_HRPWM2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HCI_HRPWM2_V1\t\t\t(Offset 0x03DC) */\n\n#define BIT_SHIFT_HCI_HRPWM2 0\n#define BIT_MASK_HCI_HRPWM2 0xffff\n#define BIT_HCI_HRPWM2(x) (((x) & BIT_MASK_HCI_HRPWM2) << BIT_SHIFT_HCI_HRPWM2)\n#define BITS_HCI_HRPWM2 (BIT_MASK_HCI_HRPWM2 << BIT_SHIFT_HCI_HRPWM2)\n#define BIT_CLEAR_HCI_HRPWM2(x) ((x) & (~BITS_HCI_HRPWM2))\n#define BIT_GET_HCI_HRPWM2(x)                                                  \\\n\t(((x) >> BIT_SHIFT_HCI_HRPWM2) & BIT_MASK_HCI_HRPWM2)\n#define BIT_SET_HCI_HRPWM2(x, v) (BIT_CLEAR_HCI_HRPWM2(x) | BIT_HCI_HRPWM2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PCIE_HCPWM2_V1\t\t\t(Offset 0x03DE) */\n\n#define BIT_SHIFT_PCIE_HCPWM2 0\n#define BIT_MASK_PCIE_HCPWM2 0xffff\n#define BIT_PCIE_HCPWM2(x)                                                     \\\n\t(((x) & BIT_MASK_PCIE_HCPWM2) << BIT_SHIFT_PCIE_HCPWM2)\n#define BITS_PCIE_HCPWM2 (BIT_MASK_PCIE_HCPWM2 << BIT_SHIFT_PCIE_HCPWM2)\n#define BIT_CLEAR_PCIE_HCPWM2(x) ((x) & (~BITS_PCIE_HCPWM2))\n#define BIT_GET_PCIE_HCPWM2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_PCIE_HCPWM2) & BIT_MASK_PCIE_HCPWM2)\n#define BIT_SET_PCIE_HCPWM2(x, v)                                              \\\n\t(BIT_CLEAR_PCIE_HCPWM2(x) | BIT_PCIE_HCPWM2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HCI_HCPWM2_V1\t\t\t(Offset 0x03DE) */\n\n#define BIT_SHIFT_HCI_HCPWM2 0\n#define BIT_MASK_HCI_HCPWM2 0xffff\n#define BIT_HCI_HCPWM2(x) (((x) & BIT_MASK_HCI_HCPWM2) << BIT_SHIFT_HCI_HCPWM2)\n#define BITS_HCI_HCPWM2 (BIT_MASK_HCI_HCPWM2 << BIT_SHIFT_HCI_HCPWM2)\n#define BIT_CLEAR_HCI_HCPWM2(x) ((x) & (~BITS_HCI_HCPWM2))\n#define BIT_GET_HCI_HCPWM2(x)                                                  \\\n\t(((x) >> BIT_SHIFT_HCI_HCPWM2) & BIT_MASK_HCI_HCPWM2)\n#define BIT_SET_HCI_HCPWM2(x, v) (BIT_CLEAR_HCI_HCPWM2(x) | BIT_HCI_HCPWM2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PCIE_H2C_MSG_V1\t\t\t(Offset 0x03E0) */\n\n#define BIT_AC7Q_EMPTY BIT(7)\n#define BIT_AC6Q_EMPTY BIT(6)\n#define BIT_AC5Q_EMPTY BIT(5)\n#define BIT_AC4Q_EMPTY BIT(4)\n#define BIT_AC3Q_EMPTY BIT(3)\n#define BIT_AC2Q_EMPTY BIT(2)\n#define BIT_AC1Q_EMPTY BIT(1)\n\n#define BIT_SHIFT_DRV2FW_INFO 0\n#define BIT_MASK_DRV2FW_INFO 0xffffffffL\n#define BIT_DRV2FW_INFO(x)                                                     \\\n\t(((x) & BIT_MASK_DRV2FW_INFO) << BIT_SHIFT_DRV2FW_INFO)\n#define BITS_DRV2FW_INFO (BIT_MASK_DRV2FW_INFO << BIT_SHIFT_DRV2FW_INFO)\n#define BIT_CLEAR_DRV2FW_INFO(x) ((x) & (~BITS_DRV2FW_INFO))\n#define BIT_GET_DRV2FW_INFO(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DRV2FW_INFO) & BIT_MASK_DRV2FW_INFO)\n#define BIT_SET_DRV2FW_INFO(x, v)                                              \\\n\t(BIT_CLEAR_DRV2FW_INFO(x) | BIT_DRV2FW_INFO(v))\n\n#define BIT_AC0Q_EMPTY BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PCIE_C2H_MSG_V1\t\t\t(Offset 0x03E4) */\n\n#define BIT_SHIFT_HCI_PCIE_C2H_MSG 0\n#define BIT_MASK_HCI_PCIE_C2H_MSG 0xffffffffL\n#define BIT_HCI_PCIE_C2H_MSG(x)                                                \\\n\t(((x) & BIT_MASK_HCI_PCIE_C2H_MSG) << BIT_SHIFT_HCI_PCIE_C2H_MSG)\n#define BITS_HCI_PCIE_C2H_MSG                                                  \\\n\t(BIT_MASK_HCI_PCIE_C2H_MSG << BIT_SHIFT_HCI_PCIE_C2H_MSG)\n#define BIT_CLEAR_HCI_PCIE_C2H_MSG(x) ((x) & (~BITS_HCI_PCIE_C2H_MSG))\n#define BIT_GET_HCI_PCIE_C2H_MSG(x)                                            \\\n\t(((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG) & BIT_MASK_HCI_PCIE_C2H_MSG)\n#define BIT_SET_HCI_PCIE_C2H_MSG(x, v)                                         \\\n\t(BIT_CLEAR_HCI_PCIE_C2H_MSG(x) | BIT_HCI_PCIE_C2H_MSG(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HCI_C2H_MSG_V1\t\t\t(Offset 0x03E4) */\n\n#define BIT_SHIFT_HCI_C2H_MSG 0\n#define BIT_MASK_HCI_C2H_MSG 0xffffffffL\n#define BIT_HCI_C2H_MSG(x)                                                     \\\n\t(((x) & BIT_MASK_HCI_C2H_MSG) << BIT_SHIFT_HCI_C2H_MSG)\n#define BITS_HCI_C2H_MSG (BIT_MASK_HCI_C2H_MSG << BIT_SHIFT_HCI_C2H_MSG)\n#define BIT_CLEAR_HCI_C2H_MSG(x) ((x) & (~BITS_HCI_C2H_MSG))\n#define BIT_GET_HCI_C2H_MSG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HCI_C2H_MSG) & BIT_MASK_HCI_C2H_MSG)\n#define BIT_SET_HCI_C2H_MSG(x, v)                                              \\\n\t(BIT_CLEAR_HCI_C2H_MSG(x) | BIT_HCI_C2H_MSG(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DBI_WDATA_V1\t\t\t(Offset 0x03E8) */\n\n#define BIT_SHIFT_DBI_WDATA 0\n#define BIT_MASK_DBI_WDATA 0xffffffffL\n#define BIT_DBI_WDATA(x) (((x) & BIT_MASK_DBI_WDATA) << BIT_SHIFT_DBI_WDATA)\n#define BITS_DBI_WDATA (BIT_MASK_DBI_WDATA << BIT_SHIFT_DBI_WDATA)\n#define BIT_CLEAR_DBI_WDATA(x) ((x) & (~BITS_DBI_WDATA))\n#define BIT_GET_DBI_WDATA(x) (((x) >> BIT_SHIFT_DBI_WDATA) & BIT_MASK_DBI_WDATA)\n#define BIT_SET_DBI_WDATA(x, v) (BIT_CLEAR_DBI_WDATA(x) | BIT_DBI_WDATA(v))\n\n/* 2 REG_DBI_RDATA_V1\t\t\t(Offset 0x03EC) */\n\n#define BIT_SHIFT_DBI_RDATA 0\n#define BIT_MASK_DBI_RDATA 0xffffffffL\n#define BIT_DBI_RDATA(x) (((x) & BIT_MASK_DBI_RDATA) << BIT_SHIFT_DBI_RDATA)\n#define BITS_DBI_RDATA (BIT_MASK_DBI_RDATA << BIT_SHIFT_DBI_RDATA)\n#define BIT_CLEAR_DBI_RDATA(x) ((x) & (~BITS_DBI_RDATA))\n#define BIT_GET_DBI_RDATA(x) (((x) >> BIT_SHIFT_DBI_RDATA) & BIT_MASK_DBI_RDATA)\n#define BIT_SET_DBI_RDATA(x, v) (BIT_CLEAR_DBI_RDATA(x) | BIT_DBI_RDATA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DBI_FLAG_V1\t\t\t\t(Offset 0x03F0) */\n\n#define BIT_SHIFT_LOOPBACK_DBG_SEL 28\n#define BIT_MASK_LOOPBACK_DBG_SEL 0xf\n#define BIT_LOOPBACK_DBG_SEL(x)                                                \\\n\t(((x) & BIT_MASK_LOOPBACK_DBG_SEL) << BIT_SHIFT_LOOPBACK_DBG_SEL)\n#define BITS_LOOPBACK_DBG_SEL                                                  \\\n\t(BIT_MASK_LOOPBACK_DBG_SEL << BIT_SHIFT_LOOPBACK_DBG_SEL)\n#define BIT_CLEAR_LOOPBACK_DBG_SEL(x) ((x) & (~BITS_LOOPBACK_DBG_SEL))\n#define BIT_GET_LOOPBACK_DBG_SEL(x)                                            \\\n\t(((x) >> BIT_SHIFT_LOOPBACK_DBG_SEL) & BIT_MASK_LOOPBACK_DBG_SEL)\n#define BIT_SET_LOOPBACK_DBG_SEL(x, v)                                         \\\n\t(BIT_CLEAR_LOOPBACK_DBG_SEL(x) | BIT_LOOPBACK_DBG_SEL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_STUCK_FLAG_V1\t\t\t(Offset 0x03F0) */\n\n#define BIT_EN_STUCK_DBG BIT(26)\n#define BIT_RX_STUCK BIT(25)\n#define BIT_TX_STUCK BIT(24)\n#define BIT_DBI_RFLAG BIT(17)\n#define BIT_DBI_WFLAG BIT(16)\n\n#define BIT_SHIFT_DBI_WREN 12\n#define BIT_MASK_DBI_WREN 0xf\n#define BIT_DBI_WREN(x) (((x) & BIT_MASK_DBI_WREN) << BIT_SHIFT_DBI_WREN)\n#define BITS_DBI_WREN (BIT_MASK_DBI_WREN << BIT_SHIFT_DBI_WREN)\n#define BIT_CLEAR_DBI_WREN(x) ((x) & (~BITS_DBI_WREN))\n#define BIT_GET_DBI_WREN(x) (((x) >> BIT_SHIFT_DBI_WREN) & BIT_MASK_DBI_WREN)\n#define BIT_SET_DBI_WREN(x, v) (BIT_CLEAR_DBI_WREN(x) | BIT_DBI_WREN(v))\n\n#define BIT_SHIFT_DBI_ADDR 0\n#define BIT_MASK_DBI_ADDR 0xfff\n#define BIT_DBI_ADDR(x) (((x) & BIT_MASK_DBI_ADDR) << BIT_SHIFT_DBI_ADDR)\n#define BITS_DBI_ADDR (BIT_MASK_DBI_ADDR << BIT_SHIFT_DBI_ADDR)\n#define BIT_CLEAR_DBI_ADDR(x) ((x) & (~BITS_DBI_ADDR))\n#define BIT_GET_DBI_ADDR(x) (((x) >> BIT_SHIFT_DBI_ADDR) & BIT_MASK_DBI_ADDR)\n#define BIT_SET_DBI_ADDR(x, v) (BIT_CLEAR_DBI_ADDR(x) | BIT_DBI_ADDR(v))\n\n/* 2 REG_MDIO_V1\t\t\t\t(Offset 0x03F4) */\n\n#define BIT_SHIFT_MDIO_RDATA 16\n#define BIT_MASK_MDIO_RDATA 0xffff\n#define BIT_MDIO_RDATA(x) (((x) & BIT_MASK_MDIO_RDATA) << BIT_SHIFT_MDIO_RDATA)\n#define BITS_MDIO_RDATA (BIT_MASK_MDIO_RDATA << BIT_SHIFT_MDIO_RDATA)\n#define BIT_CLEAR_MDIO_RDATA(x) ((x) & (~BITS_MDIO_RDATA))\n#define BIT_GET_MDIO_RDATA(x)                                                  \\\n\t(((x) >> BIT_SHIFT_MDIO_RDATA) & BIT_MASK_MDIO_RDATA)\n#define BIT_SET_MDIO_RDATA(x, v) (BIT_CLEAR_MDIO_RDATA(x) | BIT_MDIO_RDATA(v))\n\n#define BIT_SHIFT_MDIO_WDATA 0\n#define BIT_MASK_MDIO_WDATA 0xffff\n#define BIT_MDIO_WDATA(x) (((x) & BIT_MASK_MDIO_WDATA) << BIT_SHIFT_MDIO_WDATA)\n#define BITS_MDIO_WDATA (BIT_MASK_MDIO_WDATA << BIT_SHIFT_MDIO_WDATA)\n#define BIT_CLEAR_MDIO_WDATA(x) ((x) & (~BITS_MDIO_WDATA))\n#define BIT_GET_MDIO_WDATA(x)                                                  \\\n\t(((x) >> BIT_SHIFT_MDIO_WDATA) & BIT_MASK_MDIO_WDATA)\n#define BIT_SET_MDIO_WDATA(x, v) (BIT_CLEAR_MDIO_WDATA(x) | BIT_MDIO_WDATA(v))\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BUS_MIX_CFG\t\t\t\t(Offset 0x03F8) */\n\n#define BIT_SHIFT_DELAY_TIME 24\n#define BIT_MASK_DELAY_TIME 0xff\n#define BIT_DELAY_TIME(x) (((x) & BIT_MASK_DELAY_TIME) << BIT_SHIFT_DELAY_TIME)\n#define BITS_DELAY_TIME (BIT_MASK_DELAY_TIME << BIT_SHIFT_DELAY_TIME)\n#define BIT_CLEAR_DELAY_TIME(x) ((x) & (~BITS_DELAY_TIME))\n#define BIT_GET_DELAY_TIME(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DELAY_TIME) & BIT_MASK_DELAY_TIME)\n#define BIT_SET_DELAY_TIME(x, v) (BIT_CLEAR_DELAY_TIME(x) | BIT_DELAY_TIME(v))\n\n#define BIT_RX_TIMER_DELAY_EN BIT(17)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PCIE_MIX_CFG\t\t\t(Offset 0x03F8) */\n\n#define BIT_EN_WATCH_DOG BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MDIO2_V1\t\t\t\t(Offset 0x03F8) */\n\n#define BIT_ECRC_EN BIT(7)\n#define BIT_MDIO_RFLAG BIT(6)\n#define BIT_MDIO_WFLAG BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_MDIO2_V1\t\t\t\t(Offset 0x03F8) */\n\n#define BIT_SHIFT_MDIO_ADDR 0\n#define BIT_MASK_MDIO_ADDR 0x1f\n#define BIT_MDIO_ADDR(x) (((x) & BIT_MASK_MDIO_ADDR) << BIT_SHIFT_MDIO_ADDR)\n#define BITS_MDIO_ADDR (BIT_MASK_MDIO_ADDR << BIT_SHIFT_MDIO_ADDR)\n#define BIT_CLEAR_MDIO_ADDR(x) ((x) & (~BITS_MDIO_ADDR))\n#define BIT_GET_MDIO_ADDR(x) (((x) >> BIT_SHIFT_MDIO_ADDR) & BIT_MASK_MDIO_ADDR)\n#define BIT_SET_MDIO_ADDR(x, v) (BIT_CLEAR_MDIO_ADDR(x) | BIT_MDIO_ADDR(v))\n\n#define BIT_SHIFT_TXFAIL_DROPCNT 0\n#define BIT_MASK_TXFAIL_DROPCNT 0xffff\n#define BIT_TXFAIL_DROPCNT(x)                                                  \\\n\t(((x) & BIT_MASK_TXFAIL_DROPCNT) << BIT_SHIFT_TXFAIL_DROPCNT)\n#define BITS_TXFAIL_DROPCNT                                                    \\\n\t(BIT_MASK_TXFAIL_DROPCNT << BIT_SHIFT_TXFAIL_DROPCNT)\n#define BIT_CLEAR_TXFAIL_DROPCNT(x) ((x) & (~BITS_TXFAIL_DROPCNT))\n#define BIT_GET_TXFAIL_DROPCNT(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXFAIL_DROPCNT) & BIT_MASK_TXFAIL_DROPCNT)\n#define BIT_SET_TXFAIL_DROPCNT(x, v)                                           \\\n\t(BIT_CLEAR_TXFAIL_DROPCNT(x) | BIT_TXFAIL_DROPCNT(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PCIE_MIX_CFG\t\t\t(Offset 0x03F8) */\n\n#define BIT_SHIFT_MDIO_REG_ADDR_V1 0\n#define BIT_MASK_MDIO_REG_ADDR_V1 0x1f\n#define BIT_MDIO_REG_ADDR_V1(x)                                                \\\n\t(((x) & BIT_MASK_MDIO_REG_ADDR_V1) << BIT_SHIFT_MDIO_REG_ADDR_V1)\n#define BITS_MDIO_REG_ADDR_V1                                                  \\\n\t(BIT_MASK_MDIO_REG_ADDR_V1 << BIT_SHIFT_MDIO_REG_ADDR_V1)\n#define BIT_CLEAR_MDIO_REG_ADDR_V1(x) ((x) & (~BITS_MDIO_REG_ADDR_V1))\n#define BIT_GET_MDIO_REG_ADDR_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1) & BIT_MASK_MDIO_REG_ADDR_V1)\n#define BIT_SET_MDIO_REG_ADDR_V1(x, v)                                         \\\n\t(BIT_CLEAR_MDIO_REG_ADDR_V1(x) | BIT_MDIO_REG_ADDR_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_RXRST_BACKDOOR BIT(31)\n#define BIT_TXRST_BACKDOOR BIT(30)\n#define BIT_RXIDX_RSTB BIT(29)\n#define BIT_TXIDX_RSTB BIT(28)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_SHIFT_WATCH_DOG_TIMER 28\n#define BIT_MASK_WATCH_DOG_TIMER 0xf\n#define BIT_WATCH_DOG_TIMER(x)                                                 \\\n\t(((x) & BIT_MASK_WATCH_DOG_TIMER) << BIT_SHIFT_WATCH_DOG_TIMER)\n#define BITS_WATCH_DOG_TIMER                                                   \\\n\t(BIT_MASK_WATCH_DOG_TIMER << BIT_SHIFT_WATCH_DOG_TIMER)\n#define BIT_CLEAR_WATCH_DOG_TIMER(x) ((x) & (~BITS_WATCH_DOG_TIMER))\n#define BIT_GET_WATCH_DOG_TIMER(x)                                             \\\n\t(((x) >> BIT_SHIFT_WATCH_DOG_TIMER) & BIT_MASK_WATCH_DOG_TIMER)\n#define BIT_SET_WATCH_DOG_TIMER(x, v)                                          \\\n\t(BIT_CLEAR_WATCH_DOG_TIMER(x) | BIT_WATCH_DOG_TIMER(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_DROP_NEXT_RXPKT BIT(27)\n#define BIT_SHORT_CORE_RST_SEL BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_EXCEPT_RESUME_EN BIT(25)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_EXCEPT_FLAG BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_EXCEPT_RESUME_FLAG BIT(24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_ALIGN_MTU BIT(23)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_EN_ALIGN_MTU BIT(23)\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_EARLY_TAG_RETURN BIT(22)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_SHIFT_LATENCY_CONTROL 21\n#define BIT_MASK_LATENCY_CONTROL 0x3\n#define BIT_LATENCY_CONTROL(x)                                                 \\\n\t(((x) & BIT_MASK_LATENCY_CONTROL) << BIT_SHIFT_LATENCY_CONTROL)\n#define BITS_LATENCY_CONTROL                                                   \\\n\t(BIT_MASK_LATENCY_CONTROL << BIT_SHIFT_LATENCY_CONTROL)\n#define BIT_CLEAR_LATENCY_CONTROL(x) ((x) & (~BITS_LATENCY_CONTROL))\n#define BIT_GET_LATENCY_CONTROL(x)                                             \\\n\t(((x) >> BIT_SHIFT_LATENCY_CONTROL) & BIT_MASK_LATENCY_CONTROL)\n#define BIT_SET_LATENCY_CONTROL(x, v)                                          \\\n\t(BIT_CLEAR_LATENCY_CONTROL(x) | BIT_LATENCY_CONTROL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_HOST_GEN2_SUPPORT BIT(20)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_SHIFT_TXDMA_ERR_FLAG 16\n#define BIT_MASK_TXDMA_ERR_FLAG 0xf\n#define BIT_TXDMA_ERR_FLAG(x)                                                  \\\n\t(((x) & BIT_MASK_TXDMA_ERR_FLAG) << BIT_SHIFT_TXDMA_ERR_FLAG)\n#define BITS_TXDMA_ERR_FLAG                                                    \\\n\t(BIT_MASK_TXDMA_ERR_FLAG << BIT_SHIFT_TXDMA_ERR_FLAG)\n#define BIT_CLEAR_TXDMA_ERR_FLAG(x) ((x) & (~BITS_TXDMA_ERR_FLAG))\n#define BIT_GET_TXDMA_ERR_FLAG(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXDMA_ERR_FLAG) & BIT_MASK_TXDMA_ERR_FLAG)\n#define BIT_SET_TXDMA_ERR_FLAG(x, v)                                           \\\n\t(BIT_CLEAR_TXDMA_ERR_FLAG(x) | BIT_TXDMA_ERR_FLAG(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_SHIFT_TXDMA_ERR_FLAG_V1 15\n#define BIT_MASK_TXDMA_ERR_FLAG_V1 0x1f\n#define BIT_TXDMA_ERR_FLAG_V1(x)                                               \\\n\t(((x) & BIT_MASK_TXDMA_ERR_FLAG_V1) << BIT_SHIFT_TXDMA_ERR_FLAG_V1)\n#define BITS_TXDMA_ERR_FLAG_V1                                                 \\\n\t(BIT_MASK_TXDMA_ERR_FLAG_V1 << BIT_SHIFT_TXDMA_ERR_FLAG_V1)\n#define BIT_CLEAR_TXDMA_ERR_FLAG_V1(x) ((x) & (~BITS_TXDMA_ERR_FLAG_V1))\n#define BIT_GET_TXDMA_ERR_FLAG_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_V1) & BIT_MASK_TXDMA_ERR_FLAG_V1)\n#define BIT_SET_TXDMA_ERR_FLAG_V1(x, v)                                        \\\n\t(BIT_CLEAR_TXDMA_ERR_FLAG_V1(x) | BIT_TXDMA_ERR_FLAG_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_SHIFT_EARLY_MODE_SEL 12\n#define BIT_MASK_EARLY_MODE_SEL 0xf\n#define BIT_EARLY_MODE_SEL(x)                                                  \\\n\t(((x) & BIT_MASK_EARLY_MODE_SEL) << BIT_SHIFT_EARLY_MODE_SEL)\n#define BITS_EARLY_MODE_SEL                                                    \\\n\t(BIT_MASK_EARLY_MODE_SEL << BIT_SHIFT_EARLY_MODE_SEL)\n#define BIT_CLEAR_EARLY_MODE_SEL(x) ((x) & (~BITS_EARLY_MODE_SEL))\n#define BIT_GET_EARLY_MODE_SEL(x)                                              \\\n\t(((x) >> BIT_SHIFT_EARLY_MODE_SEL) & BIT_MASK_EARLY_MODE_SEL)\n#define BIT_SET_EARLY_MODE_SEL(x, v)                                           \\\n\t(BIT_CLEAR_EARLY_MODE_SEL(x) | BIT_EARLY_MODE_SEL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_EPHY_RX50_EN BIT(11)\n\n#define BIT_SHIFT_MSI_TIMEOUT_ID_V1 8\n#define BIT_MASK_MSI_TIMEOUT_ID_V1 0x7\n#define BIT_MSI_TIMEOUT_ID_V1(x)                                               \\\n\t(((x) & BIT_MASK_MSI_TIMEOUT_ID_V1) << BIT_SHIFT_MSI_TIMEOUT_ID_V1)\n#define BITS_MSI_TIMEOUT_ID_V1                                                 \\\n\t(BIT_MASK_MSI_TIMEOUT_ID_V1 << BIT_SHIFT_MSI_TIMEOUT_ID_V1)\n#define BIT_CLEAR_MSI_TIMEOUT_ID_V1(x) ((x) & (~BITS_MSI_TIMEOUT_ID_V1))\n#define BIT_GET_MSI_TIMEOUT_ID_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1) & BIT_MASK_MSI_TIMEOUT_ID_V1)\n#define BIT_SET_MSI_TIMEOUT_ID_V1(x, v)                                        \\\n\t(BIT_CLEAR_MSI_TIMEOUT_ID_V1(x) | BIT_MSI_TIMEOUT_ID_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_SHIFT_RXDMA_ERR_CNT 8\n#define BIT_MASK_RXDMA_ERR_CNT 0xff\n#define BIT_RXDMA_ERR_CNT(x)                                                   \\\n\t(((x) & BIT_MASK_RXDMA_ERR_CNT) << BIT_SHIFT_RXDMA_ERR_CNT)\n#define BITS_RXDMA_ERR_CNT (BIT_MASK_RXDMA_ERR_CNT << BIT_SHIFT_RXDMA_ERR_CNT)\n#define BIT_CLEAR_RXDMA_ERR_CNT(x) ((x) & (~BITS_RXDMA_ERR_CNT))\n#define BIT_GET_RXDMA_ERR_CNT(x)                                               \\\n\t(((x) >> BIT_SHIFT_RXDMA_ERR_CNT) & BIT_MASK_RXDMA_ERR_CNT)\n#define BIT_SET_RXDMA_ERR_CNT(x, v)                                            \\\n\t(BIT_CLEAR_RXDMA_ERR_CNT(x) | BIT_RXDMA_ERR_CNT(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_RADDR_RD BIT(7)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_TXDMA_ERR_HANDLE_REQ BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_EN_MUL_TAG BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_TXDMA_ERROR_PS BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_L1OFF_PWR_OFF_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_EN_EARLY_MODE BIT(5)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_EN_TXDMA_STUCK_ERR_HANDLE BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_L0S_LINK_OFF BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_EN_TXDMA_RTN_ERR_HANDLE BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_ACT_LINK_OFF BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_RXDMA_ERR_HANDLE_REQ BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_EN_SLOW_MAC_TX BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_RXDMA_ERROR_PS BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_EN_SLOW_MAC_RX BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HCI_MIX_CFG\t\t\t\t(Offset 0x03FC) */\n\n#define BIT_EN_RXDMA_STUCK_ERR_HANDLE BIT(1)\n#define BIT_EN_SLOW_MAC_HW BIT(0)\n#define BIT_EN_RXDMA_RTN_ERR_HANDLE BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q0_INFO\t\t\t\t(Offset 0x0400) */\n\n#define BIT_SHIFT_QUEUEMACID_Q0_V1 25\n#define BIT_MASK_QUEUEMACID_Q0_V1 0x7f\n#define BIT_QUEUEMACID_Q0_V1(x)                                                \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q0_V1) << BIT_SHIFT_QUEUEMACID_Q0_V1)\n#define BITS_QUEUEMACID_Q0_V1                                                  \\\n\t(BIT_MASK_QUEUEMACID_Q0_V1 << BIT_SHIFT_QUEUEMACID_Q0_V1)\n#define BIT_CLEAR_QUEUEMACID_Q0_V1(x) ((x) & (~BITS_QUEUEMACID_Q0_V1))\n#define BIT_GET_QUEUEMACID_Q0_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1) & BIT_MASK_QUEUEMACID_Q0_V1)\n#define BIT_SET_QUEUEMACID_Q0_V1(x, v)                                         \\\n\t(BIT_CLEAR_QUEUEMACID_Q0_V1(x) | BIT_QUEUEMACID_Q0_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_QUEUE_INFO1\t\t\t\t(Offset 0x0400) */\n\n#define BIT_SHIFT_QUEUEMACID 25\n#define BIT_MASK_QUEUEMACID 0x7f\n#define BIT_QUEUEMACID(x) (((x) & BIT_MASK_QUEUEMACID) << BIT_SHIFT_QUEUEMACID)\n#define BITS_QUEUEMACID (BIT_MASK_QUEUEMACID << BIT_SHIFT_QUEUEMACID)\n#define BIT_CLEAR_QUEUEMACID(x) ((x) & (~BITS_QUEUEMACID))\n#define BIT_GET_QUEUEMACID(x)                                                  \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID) & BIT_MASK_QUEUEMACID)\n#define BIT_SET_QUEUEMACID(x, v) (BIT_CLEAR_QUEUEMACID(x) | BIT_QUEUEMACID(v))\n\n#define BIT_DONE BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q0_INFO\t\t\t\t(Offset 0x0400) */\n\n#define BIT_SHIFT_QUEUEAC_Q0_V1 23\n#define BIT_MASK_QUEUEAC_Q0_V1 0x3\n#define BIT_QUEUEAC_Q0_V1(x)                                                   \\\n\t(((x) & BIT_MASK_QUEUEAC_Q0_V1) << BIT_SHIFT_QUEUEAC_Q0_V1)\n#define BITS_QUEUEAC_Q0_V1 (BIT_MASK_QUEUEAC_Q0_V1 << BIT_SHIFT_QUEUEAC_Q0_V1)\n#define BIT_CLEAR_QUEUEAC_Q0_V1(x) ((x) & (~BITS_QUEUEAC_Q0_V1))\n#define BIT_GET_QUEUEAC_Q0_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q0_V1) & BIT_MASK_QUEUEAC_Q0_V1)\n#define BIT_SET_QUEUEAC_Q0_V1(x, v)                                            \\\n\t(BIT_CLEAR_QUEUEAC_Q0_V1(x) | BIT_QUEUEAC_Q0_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_QUEUE_INFO1\t\t\t\t(Offset 0x0400) */\n\n#define BIT_SHIFT_QUEUEAC 23\n#define BIT_MASK_QUEUEAC 0x3\n#define BIT_QUEUEAC(x) (((x) & BIT_MASK_QUEUEAC) << BIT_SHIFT_QUEUEAC)\n#define BITS_QUEUEAC (BIT_MASK_QUEUEAC << BIT_SHIFT_QUEUEAC)\n#define BIT_CLEAR_QUEUEAC(x) ((x) & (~BITS_QUEUEAC))\n#define BIT_GET_QUEUEAC(x) (((x) >> BIT_SHIFT_QUEUEAC) & BIT_MASK_QUEUEAC)\n#define BIT_SET_QUEUEAC(x, v) (BIT_CLEAR_QUEUEAC(x) | BIT_QUEUEAC(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q0_INFO\t\t\t\t(Offset 0x0400) */\n\n#define BIT_TIDEMPTY_Q0_V1 BIT(22)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_QUEUE_INFO1\t\t\t\t(Offset 0x0400) */\n\n#define BIT_TIDEMPTY BIT(22)\n\n#define BIT_SHIFT_ACCWBITEN 20\n#define BIT_MASK_ACCWBITEN 0xf\n#define BIT_ACCWBITEN(x) (((x) & BIT_MASK_ACCWBITEN) << BIT_SHIFT_ACCWBITEN)\n#define BITS_ACCWBITEN (BIT_MASK_ACCWBITEN << BIT_SHIFT_ACCWBITEN)\n#define BIT_CLEAR_ACCWBITEN(x) ((x) & (~BITS_ACCWBITEN))\n#define BIT_GET_ACCWBITEN(x) (((x) >> BIT_SHIFT_ACCWBITEN) & BIT_MASK_ACCWBITEN)\n#define BIT_SET_ACCWBITEN(x, v) (BIT_CLEAR_ACCWBITEN(x) | BIT_ACCWBITEN(v))\n\n#define BIT_BCNQ_EMPTY_V1 BIT(19)\n#define BIT_HIQ_EMPTY_V1 BIT(18)\n#define BIT_MQQ_EMPTY_V1 BIT(17)\n\n#define BIT_SHIFT_COL_CNT 16\n#define BIT_MASK_COL_CNT 0xf\n#define BIT_COL_CNT(x) (((x) & BIT_MASK_COL_CNT) << BIT_SHIFT_COL_CNT)\n#define BITS_COL_CNT (BIT_MASK_COL_CNT << BIT_SHIFT_COL_CNT)\n#define BIT_CLEAR_COL_CNT(x) ((x) & (~BITS_COL_CNT))\n#define BIT_GET_COL_CNT(x) (((x) >> BIT_SHIFT_COL_CNT) & BIT_MASK_COL_CNT)\n#define BIT_SET_COL_CNT(x, v) (BIT_CLEAR_COL_CNT(x) | BIT_COL_CNT(v))\n\n#define BIT_CPU_MGT_EMPTY BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q0_INFO\t\t\t\t(Offset 0x0400) */\n\n#define BIT_SHIFT_TAIL_PKT_Q0_V1 15\n#define BIT_MASK_TAIL_PKT_Q0_V1 0xff\n#define BIT_TAIL_PKT_Q0_V1(x)                                                  \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q0_V1) << BIT_SHIFT_TAIL_PKT_Q0_V1)\n#define BITS_TAIL_PKT_Q0_V1                                                    \\\n\t(BIT_MASK_TAIL_PKT_Q0_V1 << BIT_SHIFT_TAIL_PKT_Q0_V1)\n#define BIT_CLEAR_TAIL_PKT_Q0_V1(x) ((x) & (~BITS_TAIL_PKT_Q0_V1))\n#define BIT_GET_TAIL_PKT_Q0_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q0_V1) & BIT_MASK_TAIL_PKT_Q0_V1)\n#define BIT_SET_TAIL_PKT_Q0_V1(x, v)                                           \\\n\t(BIT_CLEAR_TAIL_PKT_Q0_V1(x) | BIT_TAIL_PKT_Q0_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_QUEUE_INFO1\t\t\t\t(Offset 0x0400) */\n\n#define BIT_AC_MACID_NOT_SAME BIT(15)\n\n#define BIT_SHIFT_GROUP_TABLE_ID 12\n#define BIT_MASK_GROUP_TABLE_ID 0x7\n#define BIT_GROUP_TABLE_ID(x)                                                  \\\n\t(((x) & BIT_MASK_GROUP_TABLE_ID) << BIT_SHIFT_GROUP_TABLE_ID)\n#define BITS_GROUP_TABLE_ID                                                    \\\n\t(BIT_MASK_GROUP_TABLE_ID << BIT_SHIFT_GROUP_TABLE_ID)\n#define BIT_CLEAR_GROUP_TABLE_ID(x) ((x) & (~BITS_GROUP_TABLE_ID))\n#define BIT_GET_GROUP_TABLE_ID(x)                                              \\\n\t(((x) >> BIT_SHIFT_GROUP_TABLE_ID) & BIT_MASK_GROUP_TABLE_ID)\n#define BIT_SET_GROUP_TABLE_ID(x, v)                                           \\\n\t(BIT_CLEAR_GROUP_TABLE_ID(x) | BIT_GROUP_TABLE_ID(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q0_INFO\t\t\t\t(Offset 0x0400) */\n\n#define BIT_SHIFT_TAIL_PKT_Q0_V2 11\n#define BIT_MASK_TAIL_PKT_Q0_V2 0x7ff\n#define BIT_TAIL_PKT_Q0_V2(x)                                                  \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q0_V2) << BIT_SHIFT_TAIL_PKT_Q0_V2)\n#define BITS_TAIL_PKT_Q0_V2                                                    \\\n\t(BIT_MASK_TAIL_PKT_Q0_V2 << BIT_SHIFT_TAIL_PKT_Q0_V2)\n#define BIT_CLEAR_TAIL_PKT_Q0_V2(x) ((x) & (~BITS_TAIL_PKT_Q0_V2))\n#define BIT_GET_TAIL_PKT_Q0_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2) & BIT_MASK_TAIL_PKT_Q0_V2)\n#define BIT_SET_TAIL_PKT_Q0_V2(x, v)                                           \\\n\t(BIT_CLEAR_TAIL_PKT_Q0_V2(x) | BIT_TAIL_PKT_Q0_V2(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_QUEUE_INFO1\t\t\t\t(Offset 0x0400) */\n\n#define BIT_SHIFT_TAIL_PKT 11\n#define BIT_MASK_TAIL_PKT 0x7ff\n#define BIT_TAIL_PKT(x) (((x) & BIT_MASK_TAIL_PKT) << BIT_SHIFT_TAIL_PKT)\n#define BITS_TAIL_PKT (BIT_MASK_TAIL_PKT << BIT_SHIFT_TAIL_PKT)\n#define BIT_CLEAR_TAIL_PKT(x) ((x) & (~BITS_TAIL_PKT))\n#define BIT_GET_TAIL_PKT(x) (((x) >> BIT_SHIFT_TAIL_PKT) & BIT_MASK_TAIL_PKT)\n#define BIT_SET_TAIL_PKT(x, v) (BIT_CLEAR_TAIL_PKT(x) | BIT_TAIL_PKT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q0_INFO\t\t\t\t(Offset 0x0400) */\n\n#define BIT_SHIFT_PKT_NUM_Q0_V1 8\n#define BIT_MASK_PKT_NUM_Q0_V1 0x7f\n#define BIT_PKT_NUM_Q0_V1(x)                                                   \\\n\t(((x) & BIT_MASK_PKT_NUM_Q0_V1) << BIT_SHIFT_PKT_NUM_Q0_V1)\n#define BITS_PKT_NUM_Q0_V1 (BIT_MASK_PKT_NUM_Q0_V1 << BIT_SHIFT_PKT_NUM_Q0_V1)\n#define BIT_CLEAR_PKT_NUM_Q0_V1(x) ((x) & (~BITS_PKT_NUM_Q0_V1))\n#define BIT_GET_PKT_NUM_Q0_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_Q0_V1) & BIT_MASK_PKT_NUM_Q0_V1)\n#define BIT_SET_PKT_NUM_Q0_V1(x, v)                                            \\\n\t(BIT_CLEAR_PKT_NUM_Q0_V1(x) | BIT_PKT_NUM_Q0_V1(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q0 0\n#define BIT_MASK_HEAD_PKT_Q0 0xff\n#define BIT_HEAD_PKT_Q0(x)                                                     \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q0) << BIT_SHIFT_HEAD_PKT_Q0)\n#define BITS_HEAD_PKT_Q0 (BIT_MASK_HEAD_PKT_Q0 << BIT_SHIFT_HEAD_PKT_Q0)\n#define BIT_CLEAR_HEAD_PKT_Q0(x) ((x) & (~BITS_HEAD_PKT_Q0))\n#define BIT_GET_HEAD_PKT_Q0(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q0) & BIT_MASK_HEAD_PKT_Q0)\n#define BIT_SET_HEAD_PKT_Q0(x, v)                                              \\\n\t(BIT_CLEAR_HEAD_PKT_Q0(x) | BIT_HEAD_PKT_Q0(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q0_INFO\t\t\t\t(Offset 0x0400) */\n\n#define BIT_SHIFT_HEAD_PKT_Q0_V1 0\n#define BIT_MASK_HEAD_PKT_Q0_V1 0x7ff\n#define BIT_HEAD_PKT_Q0_V1(x)                                                  \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q0_V1) << BIT_SHIFT_HEAD_PKT_Q0_V1)\n#define BITS_HEAD_PKT_Q0_V1                                                    \\\n\t(BIT_MASK_HEAD_PKT_Q0_V1 << BIT_SHIFT_HEAD_PKT_Q0_V1)\n#define BIT_CLEAR_HEAD_PKT_Q0_V1(x) ((x) & (~BITS_HEAD_PKT_Q0_V1))\n#define BIT_GET_HEAD_PKT_Q0_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1) & BIT_MASK_HEAD_PKT_Q0_V1)\n#define BIT_SET_HEAD_PKT_Q0_V1(x, v)                                           \\\n\t(BIT_CLEAR_HEAD_PKT_Q0_V1(x) | BIT_HEAD_PKT_Q0_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_QUEUE_INFO1\t\t\t\t(Offset 0x0400) */\n\n#define BIT_SHIFT_HEAD_PKT 0\n#define BIT_MASK_HEAD_PKT 0x7ff\n#define BIT_HEAD_PKT(x) (((x) & BIT_MASK_HEAD_PKT) << BIT_SHIFT_HEAD_PKT)\n#define BITS_HEAD_PKT (BIT_MASK_HEAD_PKT << BIT_SHIFT_HEAD_PKT)\n#define BIT_CLEAR_HEAD_PKT(x) ((x) & (~BITS_HEAD_PKT))\n#define BIT_GET_HEAD_PKT(x) (((x) >> BIT_SHIFT_HEAD_PKT) & BIT_MASK_HEAD_PKT)\n#define BIT_SET_HEAD_PKT(x, v) (BIT_CLEAR_HEAD_PKT(x) | BIT_HEAD_PKT(v))\n\n#define BIT_SHIFT_PKT_NUMBER 0\n#define BIT_MASK_PKT_NUMBER 0xfff\n#define BIT_PKT_NUMBER(x) (((x) & BIT_MASK_PKT_NUMBER) << BIT_SHIFT_PKT_NUMBER)\n#define BITS_PKT_NUMBER (BIT_MASK_PKT_NUMBER << BIT_SHIFT_PKT_NUMBER)\n#define BIT_CLEAR_PKT_NUMBER(x) ((x) & (~BITS_PKT_NUMBER))\n#define BIT_GET_PKT_NUMBER(x)                                                  \\\n\t(((x) >> BIT_SHIFT_PKT_NUMBER) & BIT_MASK_PKT_NUMBER)\n#define BIT_SET_PKT_NUMBER(x, v) (BIT_CLEAR_PKT_NUMBER(x) | BIT_PKT_NUMBER(v))\n\n#define BIT_SHIFT_ACCW 0\n#define BIT_MASK_ACCW 0x3ff\n#define BIT_ACCW(x) (((x) & BIT_MASK_ACCW) << BIT_SHIFT_ACCW)\n#define BITS_ACCW (BIT_MASK_ACCW << BIT_SHIFT_ACCW)\n#define BIT_CLEAR_ACCW(x) ((x) & (~BITS_ACCW))\n#define BIT_GET_ACCW(x) (((x) >> BIT_SHIFT_ACCW) & BIT_MASK_ACCW)\n#define BIT_SET_ACCW(x, v) (BIT_CLEAR_ACCW(x) | BIT_ACCW(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_QUEUELIST_INFO0\t\t\t(Offset 0x0400) */\n\n#define BIT_SHIFT_QINFO0 0\n#define BIT_MASK_QINFO0 0xffffffffL\n#define BIT_QINFO0(x) (((x) & BIT_MASK_QINFO0) << BIT_SHIFT_QINFO0)\n#define BITS_QINFO0 (BIT_MASK_QINFO0 << BIT_SHIFT_QINFO0)\n#define BIT_CLEAR_QINFO0(x) ((x) & (~BITS_QINFO0))\n#define BIT_GET_QINFO0(x) (((x) >> BIT_SHIFT_QINFO0) & BIT_MASK_QINFO0)\n#define BIT_SET_QINFO0(x, v) (BIT_CLEAR_QINFO0(x) | BIT_QINFO0(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q1_INFO\t\t\t\t(Offset 0x0404) */\n\n#define BIT_SHIFT_QUEUEMACID_Q1_V1 25\n#define BIT_MASK_QUEUEMACID_Q1_V1 0x7f\n#define BIT_QUEUEMACID_Q1_V1(x)                                                \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q1_V1) << BIT_SHIFT_QUEUEMACID_Q1_V1)\n#define BITS_QUEUEMACID_Q1_V1                                                  \\\n\t(BIT_MASK_QUEUEMACID_Q1_V1 << BIT_SHIFT_QUEUEMACID_Q1_V1)\n#define BIT_CLEAR_QUEUEMACID_Q1_V1(x) ((x) & (~BITS_QUEUEMACID_Q1_V1))\n#define BIT_GET_QUEUEMACID_Q1_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1) & BIT_MASK_QUEUEMACID_Q1_V1)\n#define BIT_SET_QUEUEMACID_Q1_V1(x, v)                                         \\\n\t(BIT_CLEAR_QUEUEMACID_Q1_V1(x) | BIT_QUEUEMACID_Q1_V1(v))\n\n#define BIT_SHIFT_QUEUEAC_Q1_V1 23\n#define BIT_MASK_QUEUEAC_Q1_V1 0x3\n#define BIT_QUEUEAC_Q1_V1(x)                                                   \\\n\t(((x) & BIT_MASK_QUEUEAC_Q1_V1) << BIT_SHIFT_QUEUEAC_Q1_V1)\n#define BITS_QUEUEAC_Q1_V1 (BIT_MASK_QUEUEAC_Q1_V1 << BIT_SHIFT_QUEUEAC_Q1_V1)\n#define BIT_CLEAR_QUEUEAC_Q1_V1(x) ((x) & (~BITS_QUEUEAC_Q1_V1))\n#define BIT_GET_QUEUEAC_Q1_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q1_V1) & BIT_MASK_QUEUEAC_Q1_V1)\n#define BIT_SET_QUEUEAC_Q1_V1(x, v)                                            \\\n\t(BIT_CLEAR_QUEUEAC_Q1_V1(x) | BIT_QUEUEAC_Q1_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q1_INFO\t\t\t\t(Offset 0x0404) */\n\n#define BIT_TIDEMPTY_Q1_V1 BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q1_INFO\t\t\t\t(Offset 0x0404) */\n\n#define BIT_SHIFT_TAIL_PKT_Q1_V1 15\n#define BIT_MASK_TAIL_PKT_Q1_V1 0xff\n#define BIT_TAIL_PKT_Q1_V1(x)                                                  \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q1_V1) << BIT_SHIFT_TAIL_PKT_Q1_V1)\n#define BITS_TAIL_PKT_Q1_V1                                                    \\\n\t(BIT_MASK_TAIL_PKT_Q1_V1 << BIT_SHIFT_TAIL_PKT_Q1_V1)\n#define BIT_CLEAR_TAIL_PKT_Q1_V1(x) ((x) & (~BITS_TAIL_PKT_Q1_V1))\n#define BIT_GET_TAIL_PKT_Q1_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q1_V1) & BIT_MASK_TAIL_PKT_Q1_V1)\n#define BIT_SET_TAIL_PKT_Q1_V1(x, v)                                           \\\n\t(BIT_CLEAR_TAIL_PKT_Q1_V1(x) | BIT_TAIL_PKT_Q1_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q1_INFO\t\t\t\t(Offset 0x0404) */\n\n#define BIT_SHIFT_TAIL_PKT_Q1_V2 11\n#define BIT_MASK_TAIL_PKT_Q1_V2 0x7ff\n#define BIT_TAIL_PKT_Q1_V2(x)                                                  \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q1_V2) << BIT_SHIFT_TAIL_PKT_Q1_V2)\n#define BITS_TAIL_PKT_Q1_V2                                                    \\\n\t(BIT_MASK_TAIL_PKT_Q1_V2 << BIT_SHIFT_TAIL_PKT_Q1_V2)\n#define BIT_CLEAR_TAIL_PKT_Q1_V2(x) ((x) & (~BITS_TAIL_PKT_Q1_V2))\n#define BIT_GET_TAIL_PKT_Q1_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2) & BIT_MASK_TAIL_PKT_Q1_V2)\n#define BIT_SET_TAIL_PKT_Q1_V2(x, v)                                           \\\n\t(BIT_CLEAR_TAIL_PKT_Q1_V2(x) | BIT_TAIL_PKT_Q1_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q1_INFO\t\t\t\t(Offset 0x0404) */\n\n#define BIT_SHIFT_PKT_NUM_Q1_V1 8\n#define BIT_MASK_PKT_NUM_Q1_V1 0x7f\n#define BIT_PKT_NUM_Q1_V1(x)                                                   \\\n\t(((x) & BIT_MASK_PKT_NUM_Q1_V1) << BIT_SHIFT_PKT_NUM_Q1_V1)\n#define BITS_PKT_NUM_Q1_V1 (BIT_MASK_PKT_NUM_Q1_V1 << BIT_SHIFT_PKT_NUM_Q1_V1)\n#define BIT_CLEAR_PKT_NUM_Q1_V1(x) ((x) & (~BITS_PKT_NUM_Q1_V1))\n#define BIT_GET_PKT_NUM_Q1_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_Q1_V1) & BIT_MASK_PKT_NUM_Q1_V1)\n#define BIT_SET_PKT_NUM_Q1_V1(x, v)                                            \\\n\t(BIT_CLEAR_PKT_NUM_Q1_V1(x) | BIT_PKT_NUM_Q1_V1(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q1 0\n#define BIT_MASK_HEAD_PKT_Q1 0xff\n#define BIT_HEAD_PKT_Q1(x)                                                     \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q1) << BIT_SHIFT_HEAD_PKT_Q1)\n#define BITS_HEAD_PKT_Q1 (BIT_MASK_HEAD_PKT_Q1 << BIT_SHIFT_HEAD_PKT_Q1)\n#define BIT_CLEAR_HEAD_PKT_Q1(x) ((x) & (~BITS_HEAD_PKT_Q1))\n#define BIT_GET_HEAD_PKT_Q1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q1) & BIT_MASK_HEAD_PKT_Q1)\n#define BIT_SET_HEAD_PKT_Q1(x, v)                                              \\\n\t(BIT_CLEAR_HEAD_PKT_Q1(x) | BIT_HEAD_PKT_Q1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q1_INFO\t\t\t\t(Offset 0x0404) */\n\n#define BIT_SHIFT_HEAD_PKT_Q1_V1 0\n#define BIT_MASK_HEAD_PKT_Q1_V1 0x7ff\n#define BIT_HEAD_PKT_Q1_V1(x)                                                  \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q1_V1) << BIT_SHIFT_HEAD_PKT_Q1_V1)\n#define BITS_HEAD_PKT_Q1_V1                                                    \\\n\t(BIT_MASK_HEAD_PKT_Q1_V1 << BIT_SHIFT_HEAD_PKT_Q1_V1)\n#define BIT_CLEAR_HEAD_PKT_Q1_V1(x) ((x) & (~BITS_HEAD_PKT_Q1_V1))\n#define BIT_GET_HEAD_PKT_Q1_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1) & BIT_MASK_HEAD_PKT_Q1_V1)\n#define BIT_SET_HEAD_PKT_Q1_V1(x, v)                                           \\\n\t(BIT_CLEAR_HEAD_PKT_Q1_V1(x) | BIT_HEAD_PKT_Q1_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_QUEUELIST_INFO1\t\t\t(Offset 0x0404) */\n\n#define BIT_SHIFT_QINFO1 0\n#define BIT_MASK_QINFO1 0xffffffffL\n#define BIT_QINFO1(x) (((x) & BIT_MASK_QINFO1) << BIT_SHIFT_QINFO1)\n#define BITS_QINFO1 (BIT_MASK_QINFO1 << BIT_SHIFT_QINFO1)\n#define BIT_CLEAR_QINFO1(x) ((x) & (~BITS_QINFO1))\n#define BIT_GET_QINFO1(x) (((x) >> BIT_SHIFT_QINFO1) & BIT_MASK_QINFO1)\n#define BIT_SET_QINFO1(x, v) (BIT_CLEAR_QINFO1(x) | BIT_QINFO1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q2_INFO\t\t\t\t(Offset 0x0408) */\n\n#define BIT_SHIFT_QUEUEMACID_Q2_V1 25\n#define BIT_MASK_QUEUEMACID_Q2_V1 0x7f\n#define BIT_QUEUEMACID_Q2_V1(x)                                                \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q2_V1) << BIT_SHIFT_QUEUEMACID_Q2_V1)\n#define BITS_QUEUEMACID_Q2_V1                                                  \\\n\t(BIT_MASK_QUEUEMACID_Q2_V1 << BIT_SHIFT_QUEUEMACID_Q2_V1)\n#define BIT_CLEAR_QUEUEMACID_Q2_V1(x) ((x) & (~BITS_QUEUEMACID_Q2_V1))\n#define BIT_GET_QUEUEMACID_Q2_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1) & BIT_MASK_QUEUEMACID_Q2_V1)\n#define BIT_SET_QUEUEMACID_Q2_V1(x, v)                                         \\\n\t(BIT_CLEAR_QUEUEMACID_Q2_V1(x) | BIT_QUEUEMACID_Q2_V1(v))\n\n#define BIT_SHIFT_QUEUEAC_Q2_V1 23\n#define BIT_MASK_QUEUEAC_Q2_V1 0x3\n#define BIT_QUEUEAC_Q2_V1(x)                                                   \\\n\t(((x) & BIT_MASK_QUEUEAC_Q2_V1) << BIT_SHIFT_QUEUEAC_Q2_V1)\n#define BITS_QUEUEAC_Q2_V1 (BIT_MASK_QUEUEAC_Q2_V1 << BIT_SHIFT_QUEUEAC_Q2_V1)\n#define BIT_CLEAR_QUEUEAC_Q2_V1(x) ((x) & (~BITS_QUEUEAC_Q2_V1))\n#define BIT_GET_QUEUEAC_Q2_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q2_V1) & BIT_MASK_QUEUEAC_Q2_V1)\n#define BIT_SET_QUEUEAC_Q2_V1(x, v)                                            \\\n\t(BIT_CLEAR_QUEUEAC_Q2_V1(x) | BIT_QUEUEAC_Q2_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q2_INFO\t\t\t\t(Offset 0x0408) */\n\n#define BIT_TIDEMPTY_Q2_V1 BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q2_INFO\t\t\t\t(Offset 0x0408) */\n\n#define BIT_SHIFT_TAIL_PKT_Q2_V1 15\n#define BIT_MASK_TAIL_PKT_Q2_V1 0xff\n#define BIT_TAIL_PKT_Q2_V1(x)                                                  \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q2_V1) << BIT_SHIFT_TAIL_PKT_Q2_V1)\n#define BITS_TAIL_PKT_Q2_V1                                                    \\\n\t(BIT_MASK_TAIL_PKT_Q2_V1 << BIT_SHIFT_TAIL_PKT_Q2_V1)\n#define BIT_CLEAR_TAIL_PKT_Q2_V1(x) ((x) & (~BITS_TAIL_PKT_Q2_V1))\n#define BIT_GET_TAIL_PKT_Q2_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q2_V1) & BIT_MASK_TAIL_PKT_Q2_V1)\n#define BIT_SET_TAIL_PKT_Q2_V1(x, v)                                           \\\n\t(BIT_CLEAR_TAIL_PKT_Q2_V1(x) | BIT_TAIL_PKT_Q2_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q2_INFO\t\t\t\t(Offset 0x0408) */\n\n#define BIT_SHIFT_TAIL_PKT_Q2_V2 11\n#define BIT_MASK_TAIL_PKT_Q2_V2 0x7ff\n#define BIT_TAIL_PKT_Q2_V2(x)                                                  \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q2_V2) << BIT_SHIFT_TAIL_PKT_Q2_V2)\n#define BITS_TAIL_PKT_Q2_V2                                                    \\\n\t(BIT_MASK_TAIL_PKT_Q2_V2 << BIT_SHIFT_TAIL_PKT_Q2_V2)\n#define BIT_CLEAR_TAIL_PKT_Q2_V2(x) ((x) & (~BITS_TAIL_PKT_Q2_V2))\n#define BIT_GET_TAIL_PKT_Q2_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2) & BIT_MASK_TAIL_PKT_Q2_V2)\n#define BIT_SET_TAIL_PKT_Q2_V2(x, v)                                           \\\n\t(BIT_CLEAR_TAIL_PKT_Q2_V2(x) | BIT_TAIL_PKT_Q2_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q2_INFO\t\t\t\t(Offset 0x0408) */\n\n#define BIT_SHIFT_PKT_NUM_Q2_V1 8\n#define BIT_MASK_PKT_NUM_Q2_V1 0x7f\n#define BIT_PKT_NUM_Q2_V1(x)                                                   \\\n\t(((x) & BIT_MASK_PKT_NUM_Q2_V1) << BIT_SHIFT_PKT_NUM_Q2_V1)\n#define BITS_PKT_NUM_Q2_V1 (BIT_MASK_PKT_NUM_Q2_V1 << BIT_SHIFT_PKT_NUM_Q2_V1)\n#define BIT_CLEAR_PKT_NUM_Q2_V1(x) ((x) & (~BITS_PKT_NUM_Q2_V1))\n#define BIT_GET_PKT_NUM_Q2_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_Q2_V1) & BIT_MASK_PKT_NUM_Q2_V1)\n#define BIT_SET_PKT_NUM_Q2_V1(x, v)                                            \\\n\t(BIT_CLEAR_PKT_NUM_Q2_V1(x) | BIT_PKT_NUM_Q2_V1(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q2 0\n#define BIT_MASK_HEAD_PKT_Q2 0xff\n#define BIT_HEAD_PKT_Q2(x)                                                     \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q2) << BIT_SHIFT_HEAD_PKT_Q2)\n#define BITS_HEAD_PKT_Q2 (BIT_MASK_HEAD_PKT_Q2 << BIT_SHIFT_HEAD_PKT_Q2)\n#define BIT_CLEAR_HEAD_PKT_Q2(x) ((x) & (~BITS_HEAD_PKT_Q2))\n#define BIT_GET_HEAD_PKT_Q2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q2) & BIT_MASK_HEAD_PKT_Q2)\n#define BIT_SET_HEAD_PKT_Q2(x, v)                                              \\\n\t(BIT_CLEAR_HEAD_PKT_Q2(x) | BIT_HEAD_PKT_Q2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q2_INFO\t\t\t\t(Offset 0x0408) */\n\n#define BIT_SHIFT_HEAD_PKT_Q2_V1 0\n#define BIT_MASK_HEAD_PKT_Q2_V1 0x7ff\n#define BIT_HEAD_PKT_Q2_V1(x)                                                  \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q2_V1) << BIT_SHIFT_HEAD_PKT_Q2_V1)\n#define BITS_HEAD_PKT_Q2_V1                                                    \\\n\t(BIT_MASK_HEAD_PKT_Q2_V1 << BIT_SHIFT_HEAD_PKT_Q2_V1)\n#define BIT_CLEAR_HEAD_PKT_Q2_V1(x) ((x) & (~BITS_HEAD_PKT_Q2_V1))\n#define BIT_GET_HEAD_PKT_Q2_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1) & BIT_MASK_HEAD_PKT_Q2_V1)\n#define BIT_SET_HEAD_PKT_Q2_V1(x, v)                                           \\\n\t(BIT_CLEAR_HEAD_PKT_Q2_V1(x) | BIT_HEAD_PKT_Q2_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_QUEUELIST_INFO2\t\t\t(Offset 0x0408) */\n\n#define BIT_SHIFT_QINFO2 0\n#define BIT_MASK_QINFO2 0xffffffffL\n#define BIT_QINFO2(x) (((x) & BIT_MASK_QINFO2) << BIT_SHIFT_QINFO2)\n#define BITS_QINFO2 (BIT_MASK_QINFO2 << BIT_SHIFT_QINFO2)\n#define BIT_CLEAR_QINFO2(x) ((x) & (~BITS_QINFO2))\n#define BIT_GET_QINFO2(x) (((x) >> BIT_SHIFT_QINFO2) & BIT_MASK_QINFO2)\n#define BIT_SET_QINFO2(x, v) (BIT_CLEAR_QINFO2(x) | BIT_QINFO2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q3_INFO\t\t\t\t(Offset 0x040C) */\n\n#define BIT_SHIFT_QUEUEMACID_Q3_V1 25\n#define BIT_MASK_QUEUEMACID_Q3_V1 0x7f\n#define BIT_QUEUEMACID_Q3_V1(x)                                                \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q3_V1) << BIT_SHIFT_QUEUEMACID_Q3_V1)\n#define BITS_QUEUEMACID_Q3_V1                                                  \\\n\t(BIT_MASK_QUEUEMACID_Q3_V1 << BIT_SHIFT_QUEUEMACID_Q3_V1)\n#define BIT_CLEAR_QUEUEMACID_Q3_V1(x) ((x) & (~BITS_QUEUEMACID_Q3_V1))\n#define BIT_GET_QUEUEMACID_Q3_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1) & BIT_MASK_QUEUEMACID_Q3_V1)\n#define BIT_SET_QUEUEMACID_Q3_V1(x, v)                                         \\\n\t(BIT_CLEAR_QUEUEMACID_Q3_V1(x) | BIT_QUEUEMACID_Q3_V1(v))\n\n#define BIT_SHIFT_QUEUEAC_Q3_V1 23\n#define BIT_MASK_QUEUEAC_Q3_V1 0x3\n#define BIT_QUEUEAC_Q3_V1(x)                                                   \\\n\t(((x) & BIT_MASK_QUEUEAC_Q3_V1) << BIT_SHIFT_QUEUEAC_Q3_V1)\n#define BITS_QUEUEAC_Q3_V1 (BIT_MASK_QUEUEAC_Q3_V1 << BIT_SHIFT_QUEUEAC_Q3_V1)\n#define BIT_CLEAR_QUEUEAC_Q3_V1(x) ((x) & (~BITS_QUEUEAC_Q3_V1))\n#define BIT_GET_QUEUEAC_Q3_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q3_V1) & BIT_MASK_QUEUEAC_Q3_V1)\n#define BIT_SET_QUEUEAC_Q3_V1(x, v)                                            \\\n\t(BIT_CLEAR_QUEUEAC_Q3_V1(x) | BIT_QUEUEAC_Q3_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q3_INFO\t\t\t\t(Offset 0x040C) */\n\n#define BIT_TIDEMPTY_Q3_V1 BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q3_INFO\t\t\t\t(Offset 0x040C) */\n\n#define BIT_SHIFT_TAIL_PKT_Q3_V1 15\n#define BIT_MASK_TAIL_PKT_Q3_V1 0xff\n#define BIT_TAIL_PKT_Q3_V1(x)                                                  \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q3_V1) << BIT_SHIFT_TAIL_PKT_Q3_V1)\n#define BITS_TAIL_PKT_Q3_V1                                                    \\\n\t(BIT_MASK_TAIL_PKT_Q3_V1 << BIT_SHIFT_TAIL_PKT_Q3_V1)\n#define BIT_CLEAR_TAIL_PKT_Q3_V1(x) ((x) & (~BITS_TAIL_PKT_Q3_V1))\n#define BIT_GET_TAIL_PKT_Q3_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q3_V1) & BIT_MASK_TAIL_PKT_Q3_V1)\n#define BIT_SET_TAIL_PKT_Q3_V1(x, v)                                           \\\n\t(BIT_CLEAR_TAIL_PKT_Q3_V1(x) | BIT_TAIL_PKT_Q3_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q3_INFO\t\t\t\t(Offset 0x040C) */\n\n#define BIT_SHIFT_TAIL_PKT_Q3_V2 11\n#define BIT_MASK_TAIL_PKT_Q3_V2 0x7ff\n#define BIT_TAIL_PKT_Q3_V2(x)                                                  \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q3_V2) << BIT_SHIFT_TAIL_PKT_Q3_V2)\n#define BITS_TAIL_PKT_Q3_V2                                                    \\\n\t(BIT_MASK_TAIL_PKT_Q3_V2 << BIT_SHIFT_TAIL_PKT_Q3_V2)\n#define BIT_CLEAR_TAIL_PKT_Q3_V2(x) ((x) & (~BITS_TAIL_PKT_Q3_V2))\n#define BIT_GET_TAIL_PKT_Q3_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2) & BIT_MASK_TAIL_PKT_Q3_V2)\n#define BIT_SET_TAIL_PKT_Q3_V2(x, v)                                           \\\n\t(BIT_CLEAR_TAIL_PKT_Q3_V2(x) | BIT_TAIL_PKT_Q3_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q3_INFO\t\t\t\t(Offset 0x040C) */\n\n#define BIT_SHIFT_PKT_NUM_Q3_V1 8\n#define BIT_MASK_PKT_NUM_Q3_V1 0x7f\n#define BIT_PKT_NUM_Q3_V1(x)                                                   \\\n\t(((x) & BIT_MASK_PKT_NUM_Q3_V1) << BIT_SHIFT_PKT_NUM_Q3_V1)\n#define BITS_PKT_NUM_Q3_V1 (BIT_MASK_PKT_NUM_Q3_V1 << BIT_SHIFT_PKT_NUM_Q3_V1)\n#define BIT_CLEAR_PKT_NUM_Q3_V1(x) ((x) & (~BITS_PKT_NUM_Q3_V1))\n#define BIT_GET_PKT_NUM_Q3_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_Q3_V1) & BIT_MASK_PKT_NUM_Q3_V1)\n#define BIT_SET_PKT_NUM_Q3_V1(x, v)                                            \\\n\t(BIT_CLEAR_PKT_NUM_Q3_V1(x) | BIT_PKT_NUM_Q3_V1(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q3 0\n#define BIT_MASK_HEAD_PKT_Q3 0xff\n#define BIT_HEAD_PKT_Q3(x)                                                     \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q3) << BIT_SHIFT_HEAD_PKT_Q3)\n#define BITS_HEAD_PKT_Q3 (BIT_MASK_HEAD_PKT_Q3 << BIT_SHIFT_HEAD_PKT_Q3)\n#define BIT_CLEAR_HEAD_PKT_Q3(x) ((x) & (~BITS_HEAD_PKT_Q3))\n#define BIT_GET_HEAD_PKT_Q3(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q3) & BIT_MASK_HEAD_PKT_Q3)\n#define BIT_SET_HEAD_PKT_Q3(x, v)                                              \\\n\t(BIT_CLEAR_HEAD_PKT_Q3(x) | BIT_HEAD_PKT_Q3(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q3_INFO\t\t\t\t(Offset 0x040C) */\n\n#define BIT_SHIFT_HEAD_PKT_Q3_V1 0\n#define BIT_MASK_HEAD_PKT_Q3_V1 0x7ff\n#define BIT_HEAD_PKT_Q3_V1(x)                                                  \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q3_V1) << BIT_SHIFT_HEAD_PKT_Q3_V1)\n#define BITS_HEAD_PKT_Q3_V1                                                    \\\n\t(BIT_MASK_HEAD_PKT_Q3_V1 << BIT_SHIFT_HEAD_PKT_Q3_V1)\n#define BIT_CLEAR_HEAD_PKT_Q3_V1(x) ((x) & (~BITS_HEAD_PKT_Q3_V1))\n#define BIT_GET_HEAD_PKT_Q3_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1) & BIT_MASK_HEAD_PKT_Q3_V1)\n#define BIT_SET_HEAD_PKT_Q3_V1(x, v)                                           \\\n\t(BIT_CLEAR_HEAD_PKT_Q3_V1(x) | BIT_HEAD_PKT_Q3_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_QUEUELIST_INFO3\t\t\t(Offset 0x040C) */\n\n#define BIT_SHIFT_QINFO3 0\n#define BIT_MASK_QINFO3 0xffffffffL\n#define BIT_QINFO3(x) (((x) & BIT_MASK_QINFO3) << BIT_SHIFT_QINFO3)\n#define BITS_QINFO3 (BIT_MASK_QINFO3 << BIT_SHIFT_QINFO3)\n#define BIT_CLEAR_QINFO3(x) ((x) & (~BITS_QINFO3))\n#define BIT_GET_QINFO3(x) (((x) >> BIT_SHIFT_QINFO3) & BIT_MASK_QINFO3)\n#define BIT_SET_QINFO3(x, v) (BIT_CLEAR_QINFO3(x) | BIT_QINFO3(v))\n\n/* 2 REG_QUEUELIST_INFO_EMPTY\t\t(Offset 0x0410) */\n\n#define BIT_FWCMDQ_EMPTY BIT(31)\n#define BIT_MGQ_CPU_EMPTY_V1 BIT(30)\n#define BIT_BCNQ_EMPTY_EXTP0 BIT(29)\n#define BIT_BCNQ_EMPTY_PORT4 BIT(28)\n#define BIT_BCNQ_EMPTY_PORT3 BIT(27)\n#define BIT_BCNQ_EMPTY_PORT2 BIT(26)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MGQ_INFO\t\t\t\t(Offset 0x0410) */\n\n#define BIT_SHIFT_QUEUEMACID_MGQ_V1 25\n#define BIT_MASK_QUEUEMACID_MGQ_V1 0x7f\n#define BIT_QUEUEMACID_MGQ_V1(x)                                               \\\n\t(((x) & BIT_MASK_QUEUEMACID_MGQ_V1) << BIT_SHIFT_QUEUEMACID_MGQ_V1)\n#define BITS_QUEUEMACID_MGQ_V1                                                 \\\n\t(BIT_MASK_QUEUEMACID_MGQ_V1 << BIT_SHIFT_QUEUEMACID_MGQ_V1)\n#define BIT_CLEAR_QUEUEMACID_MGQ_V1(x) ((x) & (~BITS_QUEUEMACID_MGQ_V1))\n#define BIT_GET_QUEUEMACID_MGQ_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1) & BIT_MASK_QUEUEMACID_MGQ_V1)\n#define BIT_SET_QUEUEMACID_MGQ_V1(x, v)                                        \\\n\t(BIT_CLEAR_QUEUEMACID_MGQ_V1(x) | BIT_QUEUEMACID_MGQ_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_QUEUELIST_INFO_EMPTY\t\t(Offset 0x0410) */\n\n#define BIT_BCNQ_EMPTY_PORT1 BIT(25)\n#define BIT_BCNQ_EMPTY_PORT0 BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MGQ_INFO\t\t\t\t(Offset 0x0410) */\n\n#define BIT_SHIFT_QUEUEAC_MGQ_V1 23\n#define BIT_MASK_QUEUEAC_MGQ_V1 0x3\n#define BIT_QUEUEAC_MGQ_V1(x)                                                  \\\n\t(((x) & BIT_MASK_QUEUEAC_MGQ_V1) << BIT_SHIFT_QUEUEAC_MGQ_V1)\n#define BITS_QUEUEAC_MGQ_V1                                                    \\\n\t(BIT_MASK_QUEUEAC_MGQ_V1 << BIT_SHIFT_QUEUEAC_MGQ_V1)\n#define BIT_CLEAR_QUEUEAC_MGQ_V1(x) ((x) & (~BITS_QUEUEAC_MGQ_V1))\n#define BIT_GET_QUEUEAC_MGQ_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1) & BIT_MASK_QUEUEAC_MGQ_V1)\n#define BIT_SET_QUEUEAC_MGQ_V1(x, v)                                           \\\n\t(BIT_CLEAR_QUEUEAC_MGQ_V1(x) | BIT_QUEUEAC_MGQ_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_QUEUELIST_INFO_EMPTY\t\t(Offset 0x0410) */\n\n#define BIT_HQQ_EMPTY_V1 BIT(23)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MGQ_INFO\t\t\t\t(Offset 0x0410) */\n\n#define BIT_TIDEMPTY_MGQ_V1 BIT(22)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_QUEUELIST_INFO_EMPTY\t\t(Offset 0x0410) */\n\n#define BIT_MQQ_EMPTY_V2 BIT(22)\n#define BIT_S1_EMPTY BIT(21)\n#define BIT_S0_EMPTY BIT(20)\n#define BIT_AC19Q_EMPTY BIT(19)\n#define BIT_AC18Q_EMPTY BIT(18)\n#define BIT_AC17Q_EMPTY BIT(17)\n#define BIT_AC16Q_EMPTY BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MGQ_INFO\t\t\t\t(Offset 0x0410) */\n\n#define BIT_SHIFT_TAIL_PKT_MGQ_V1 15\n#define BIT_MASK_TAIL_PKT_MGQ_V1 0xff\n#define BIT_TAIL_PKT_MGQ_V1(x)                                                 \\\n\t(((x) & BIT_MASK_TAIL_PKT_MGQ_V1) << BIT_SHIFT_TAIL_PKT_MGQ_V1)\n#define BITS_TAIL_PKT_MGQ_V1                                                   \\\n\t(BIT_MASK_TAIL_PKT_MGQ_V1 << BIT_SHIFT_TAIL_PKT_MGQ_V1)\n#define BIT_CLEAR_TAIL_PKT_MGQ_V1(x) ((x) & (~BITS_TAIL_PKT_MGQ_V1))\n#define BIT_GET_TAIL_PKT_MGQ_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V1) & BIT_MASK_TAIL_PKT_MGQ_V1)\n#define BIT_SET_TAIL_PKT_MGQ_V1(x, v)                                          \\\n\t(BIT_CLEAR_TAIL_PKT_MGQ_V1(x) | BIT_TAIL_PKT_MGQ_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT)\n\n/* 2 REG_QUEUELIST_INFO_EMPTY\t\t(Offset 0x0410) */\n\n#define BIT_AC15Q_EMPTY BIT(15)\n#define BIT_AC14Q_EMPTY BIT(14)\n#define BIT_AC13Q_EMPTY BIT(13)\n#define BIT_AC12Q_EMPTY BIT(12)\n#define BIT_AC11Q_EMPTY BIT(11)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MGQ_INFO\t\t\t\t(Offset 0x0410) */\n\n#define BIT_SHIFT_TAIL_PKT_MGQ_V2 11\n#define BIT_MASK_TAIL_PKT_MGQ_V2 0x7ff\n#define BIT_TAIL_PKT_MGQ_V2(x)                                                 \\\n\t(((x) & BIT_MASK_TAIL_PKT_MGQ_V2) << BIT_SHIFT_TAIL_PKT_MGQ_V2)\n#define BITS_TAIL_PKT_MGQ_V2                                                   \\\n\t(BIT_MASK_TAIL_PKT_MGQ_V2 << BIT_SHIFT_TAIL_PKT_MGQ_V2)\n#define BIT_CLEAR_TAIL_PKT_MGQ_V2(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2))\n#define BIT_GET_TAIL_PKT_MGQ_V2(x)                                             \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2) & BIT_MASK_TAIL_PKT_MGQ_V2)\n#define BIT_SET_TAIL_PKT_MGQ_V2(x, v)                                          \\\n\t(BIT_CLEAR_TAIL_PKT_MGQ_V2(x) | BIT_TAIL_PKT_MGQ_V2(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT)\n\n/* 2 REG_QUEUELIST_INFO_EMPTY\t\t(Offset 0x0410) */\n\n#define BIT_AC10Q_EMPTY BIT(10)\n#define BIT_AC9Q_EMPTY BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MGQ_INFO\t\t\t\t(Offset 0x0410) */\n\n#define BIT_SHIFT_PKT_NUM_MGQ_V1 8\n#define BIT_MASK_PKT_NUM_MGQ_V1 0x7f\n#define BIT_PKT_NUM_MGQ_V1(x)                                                  \\\n\t(((x) & BIT_MASK_PKT_NUM_MGQ_V1) << BIT_SHIFT_PKT_NUM_MGQ_V1)\n#define BITS_PKT_NUM_MGQ_V1                                                    \\\n\t(BIT_MASK_PKT_NUM_MGQ_V1 << BIT_SHIFT_PKT_NUM_MGQ_V1)\n#define BIT_CLEAR_PKT_NUM_MGQ_V1(x) ((x) & (~BITS_PKT_NUM_MGQ_V1))\n#define BIT_GET_PKT_NUM_MGQ_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_MGQ_V1) & BIT_MASK_PKT_NUM_MGQ_V1)\n#define BIT_SET_PKT_NUM_MGQ_V1(x, v)                                           \\\n\t(BIT_CLEAR_PKT_NUM_MGQ_V1(x) | BIT_PKT_NUM_MGQ_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT)\n\n/* 2 REG_QUEUELIST_INFO_EMPTY\t\t(Offset 0x0410) */\n\n#define BIT_AC8Q_EMPTY BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MGQ_INFO\t\t\t\t(Offset 0x0410) */\n\n#define BIT_SHIFT_HEAD_PKT_MGQ 0\n#define BIT_MASK_HEAD_PKT_MGQ 0xff\n#define BIT_HEAD_PKT_MGQ(x)                                                    \\\n\t(((x) & BIT_MASK_HEAD_PKT_MGQ) << BIT_SHIFT_HEAD_PKT_MGQ)\n#define BITS_HEAD_PKT_MGQ (BIT_MASK_HEAD_PKT_MGQ << BIT_SHIFT_HEAD_PKT_MGQ)\n#define BIT_CLEAR_HEAD_PKT_MGQ(x) ((x) & (~BITS_HEAD_PKT_MGQ))\n#define BIT_GET_HEAD_PKT_MGQ(x)                                                \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_MGQ) & BIT_MASK_HEAD_PKT_MGQ)\n#define BIT_SET_HEAD_PKT_MGQ(x, v)                                             \\\n\t(BIT_CLEAR_HEAD_PKT_MGQ(x) | BIT_HEAD_PKT_MGQ(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MGQ_INFO\t\t\t\t(Offset 0x0410) */\n\n#define BIT_SHIFT_HEAD_PKT_MGQ_V1 0\n#define BIT_MASK_HEAD_PKT_MGQ_V1 0x7ff\n#define BIT_HEAD_PKT_MGQ_V1(x)                                                 \\\n\t(((x) & BIT_MASK_HEAD_PKT_MGQ_V1) << BIT_SHIFT_HEAD_PKT_MGQ_V1)\n#define BITS_HEAD_PKT_MGQ_V1                                                   \\\n\t(BIT_MASK_HEAD_PKT_MGQ_V1 << BIT_SHIFT_HEAD_PKT_MGQ_V1)\n#define BIT_CLEAR_HEAD_PKT_MGQ_V1(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1))\n#define BIT_GET_HEAD_PKT_MGQ_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1) & BIT_MASK_HEAD_PKT_MGQ_V1)\n#define BIT_SET_HEAD_PKT_MGQ_V1(x, v)                                          \\\n\t(BIT_CLEAR_HEAD_PKT_MGQ_V1(x) | BIT_HEAD_PKT_MGQ_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIQ_INFO\t\t\t\t(Offset 0x0414) */\n\n#define BIT_SHIFT_QUEUEMACID_HIQ_V1 25\n#define BIT_MASK_QUEUEMACID_HIQ_V1 0x7f\n#define BIT_QUEUEMACID_HIQ_V1(x)                                               \\\n\t(((x) & BIT_MASK_QUEUEMACID_HIQ_V1) << BIT_SHIFT_QUEUEMACID_HIQ_V1)\n#define BITS_QUEUEMACID_HIQ_V1                                                 \\\n\t(BIT_MASK_QUEUEMACID_HIQ_V1 << BIT_SHIFT_QUEUEMACID_HIQ_V1)\n#define BIT_CLEAR_QUEUEMACID_HIQ_V1(x) ((x) & (~BITS_QUEUEMACID_HIQ_V1))\n#define BIT_GET_QUEUEMACID_HIQ_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1) & BIT_MASK_QUEUEMACID_HIQ_V1)\n#define BIT_SET_QUEUEMACID_HIQ_V1(x, v)                                        \\\n\t(BIT_CLEAR_QUEUEMACID_HIQ_V1(x) | BIT_QUEUEMACID_HIQ_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_QUEUELIST_ACQ_EN\t\t\t(Offset 0x0414) */\n\n#define BIT_SHIFT_QINFO_CTRL 24\n#define BIT_MASK_QINFO_CTRL 0x3f\n#define BIT_QINFO_CTRL(x) (((x) & BIT_MASK_QINFO_CTRL) << BIT_SHIFT_QINFO_CTRL)\n#define BITS_QINFO_CTRL (BIT_MASK_QINFO_CTRL << BIT_SHIFT_QINFO_CTRL)\n#define BIT_CLEAR_QINFO_CTRL(x) ((x) & (~BITS_QINFO_CTRL))\n#define BIT_GET_QINFO_CTRL(x)                                                  \\\n\t(((x) >> BIT_SHIFT_QINFO_CTRL) & BIT_MASK_QINFO_CTRL)\n#define BIT_SET_QINFO_CTRL(x, v) (BIT_CLEAR_QINFO_CTRL(x) | BIT_QINFO_CTRL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIQ_INFO\t\t\t\t(Offset 0x0414) */\n\n#define BIT_SHIFT_QUEUEAC_HIQ_V1 23\n#define BIT_MASK_QUEUEAC_HIQ_V1 0x3\n#define BIT_QUEUEAC_HIQ_V1(x)                                                  \\\n\t(((x) & BIT_MASK_QUEUEAC_HIQ_V1) << BIT_SHIFT_QUEUEAC_HIQ_V1)\n#define BITS_QUEUEAC_HIQ_V1                                                    \\\n\t(BIT_MASK_QUEUEAC_HIQ_V1 << BIT_SHIFT_QUEUEAC_HIQ_V1)\n#define BIT_CLEAR_QUEUEAC_HIQ_V1(x) ((x) & (~BITS_QUEUEAC_HIQ_V1))\n#define BIT_GET_QUEUEAC_HIQ_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1) & BIT_MASK_QUEUEAC_HIQ_V1)\n#define BIT_SET_QUEUEAC_HIQ_V1(x, v)                                           \\\n\t(BIT_CLEAR_QUEUEAC_HIQ_V1(x) | BIT_QUEUEAC_HIQ_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIQ_INFO\t\t\t\t(Offset 0x0414) */\n\n#define BIT_TIDEMPTY_HIQ_V1 BIT(22)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_QUEUELIST_ACQ_EN\t\t\t(Offset 0x0414) */\n\n#define BIT_SHIFT_QINFO_MODE_BAND 20\n#define BIT_MASK_QINFO_MODE_BAND 0x7\n#define BIT_QINFO_MODE_BAND(x)                                                 \\\n\t(((x) & BIT_MASK_QINFO_MODE_BAND) << BIT_SHIFT_QINFO_MODE_BAND)\n#define BITS_QINFO_MODE_BAND                                                   \\\n\t(BIT_MASK_QINFO_MODE_BAND << BIT_SHIFT_QINFO_MODE_BAND)\n#define BIT_CLEAR_QINFO_MODE_BAND(x) ((x) & (~BITS_QINFO_MODE_BAND))\n#define BIT_GET_QINFO_MODE_BAND(x)                                             \\\n\t(((x) >> BIT_SHIFT_QINFO_MODE_BAND) & BIT_MASK_QINFO_MODE_BAND)\n#define BIT_SET_QINFO_MODE_BAND(x, v)                                          \\\n\t(BIT_CLEAR_QINFO_MODE_BAND(x) | BIT_QINFO_MODE_BAND(v))\n\n#define BIT_ACQ19_ENABLE BIT(19)\n#define BIT_ACQ18_ENABLE BIT(18)\n#define BIT_ACQ17_ENABLE BIT(17)\n#define BIT_ACQ16_ENABLE BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIQ_INFO\t\t\t\t(Offset 0x0414) */\n\n#define BIT_SHIFT_TAIL_PKT_HIQ_V1 15\n#define BIT_MASK_TAIL_PKT_HIQ_V1 0xff\n#define BIT_TAIL_PKT_HIQ_V1(x)                                                 \\\n\t(((x) & BIT_MASK_TAIL_PKT_HIQ_V1) << BIT_SHIFT_TAIL_PKT_HIQ_V1)\n#define BITS_TAIL_PKT_HIQ_V1                                                   \\\n\t(BIT_MASK_TAIL_PKT_HIQ_V1 << BIT_SHIFT_TAIL_PKT_HIQ_V1)\n#define BIT_CLEAR_TAIL_PKT_HIQ_V1(x) ((x) & (~BITS_TAIL_PKT_HIQ_V1))\n#define BIT_GET_TAIL_PKT_HIQ_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V1) & BIT_MASK_TAIL_PKT_HIQ_V1)\n#define BIT_SET_TAIL_PKT_HIQ_V1(x, v)                                          \\\n\t(BIT_CLEAR_TAIL_PKT_HIQ_V1(x) | BIT_TAIL_PKT_HIQ_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_QUEUELIST_ACQ_EN\t\t\t(Offset 0x0414) */\n\n#define BIT_ACQ15_ENABLE BIT(15)\n#define BIT_ACQ14_ENABLE BIT(14)\n#define BIT_ACQ13_ENABLE BIT(13)\n#define BIT_ACQ12_ENABLE BIT(12)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIQ_INFO\t\t\t\t(Offset 0x0414) */\n\n#define BIT_SHIFT_TAIL_PKT_HIQ_V2 11\n#define BIT_MASK_TAIL_PKT_HIQ_V2 0x7ff\n#define BIT_TAIL_PKT_HIQ_V2(x)                                                 \\\n\t(((x) & BIT_MASK_TAIL_PKT_HIQ_V2) << BIT_SHIFT_TAIL_PKT_HIQ_V2)\n#define BITS_TAIL_PKT_HIQ_V2                                                   \\\n\t(BIT_MASK_TAIL_PKT_HIQ_V2 << BIT_SHIFT_TAIL_PKT_HIQ_V2)\n#define BIT_CLEAR_TAIL_PKT_HIQ_V2(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2))\n#define BIT_GET_TAIL_PKT_HIQ_V2(x)                                             \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2) & BIT_MASK_TAIL_PKT_HIQ_V2)\n#define BIT_SET_TAIL_PKT_HIQ_V2(x, v)                                          \\\n\t(BIT_CLEAR_TAIL_PKT_HIQ_V2(x) | BIT_TAIL_PKT_HIQ_V2(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_QUEUELIST_ACQ_EN\t\t\t(Offset 0x0414) */\n\n#define BIT_ACQ11_ENABLE BIT(11)\n#define BIT_ACQ10_ENABLE BIT(10)\n#define BIT_ACQ9_ENABLE BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIQ_INFO\t\t\t\t(Offset 0x0414) */\n\n#define BIT_SHIFT_PKT_NUM_HIQ_V1 8\n#define BIT_MASK_PKT_NUM_HIQ_V1 0x7f\n#define BIT_PKT_NUM_HIQ_V1(x)                                                  \\\n\t(((x) & BIT_MASK_PKT_NUM_HIQ_V1) << BIT_SHIFT_PKT_NUM_HIQ_V1)\n#define BITS_PKT_NUM_HIQ_V1                                                    \\\n\t(BIT_MASK_PKT_NUM_HIQ_V1 << BIT_SHIFT_PKT_NUM_HIQ_V1)\n#define BIT_CLEAR_PKT_NUM_HIQ_V1(x) ((x) & (~BITS_PKT_NUM_HIQ_V1))\n#define BIT_GET_PKT_NUM_HIQ_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_HIQ_V1) & BIT_MASK_PKT_NUM_HIQ_V1)\n#define BIT_SET_PKT_NUM_HIQ_V1(x, v)                                           \\\n\t(BIT_CLEAR_PKT_NUM_HIQ_V1(x) | BIT_PKT_NUM_HIQ_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_QUEUELIST_ACQ_EN\t\t\t(Offset 0x0414) */\n\n#define BIT_ACQ8_ENABLE BIT(8)\n#define BIT_ACQ7_ENABLE BIT(7)\n#define BIT_ACQ6_ENABLE BIT(6)\n#define BIT_ACQ5_ENABLE BIT(5)\n#define BIT_ACQ4_ENABLE BIT(4)\n#define BIT_ACQ3_ENABLE BIT(3)\n#define BIT_ACQ2_ENABLE BIT(2)\n#define BIT_ACQ1_ENABLE BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIQ_INFO\t\t\t\t(Offset 0x0414) */\n\n#define BIT_SHIFT_HEAD_PKT_HIQ 0\n#define BIT_MASK_HEAD_PKT_HIQ 0xff\n#define BIT_HEAD_PKT_HIQ(x)                                                    \\\n\t(((x) & BIT_MASK_HEAD_PKT_HIQ) << BIT_SHIFT_HEAD_PKT_HIQ)\n#define BITS_HEAD_PKT_HIQ (BIT_MASK_HEAD_PKT_HIQ << BIT_SHIFT_HEAD_PKT_HIQ)\n#define BIT_CLEAR_HEAD_PKT_HIQ(x) ((x) & (~BITS_HEAD_PKT_HIQ))\n#define BIT_GET_HEAD_PKT_HIQ(x)                                                \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_HIQ) & BIT_MASK_HEAD_PKT_HIQ)\n#define BIT_SET_HEAD_PKT_HIQ(x, v)                                             \\\n\t(BIT_CLEAR_HEAD_PKT_HIQ(x) | BIT_HEAD_PKT_HIQ(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIQ_INFO\t\t\t\t(Offset 0x0414) */\n\n#define BIT_SHIFT_HEAD_PKT_HIQ_V1 0\n#define BIT_MASK_HEAD_PKT_HIQ_V1 0x7ff\n#define BIT_HEAD_PKT_HIQ_V1(x)                                                 \\\n\t(((x) & BIT_MASK_HEAD_PKT_HIQ_V1) << BIT_SHIFT_HEAD_PKT_HIQ_V1)\n#define BITS_HEAD_PKT_HIQ_V1                                                   \\\n\t(BIT_MASK_HEAD_PKT_HIQ_V1 << BIT_SHIFT_HEAD_PKT_HIQ_V1)\n#define BIT_CLEAR_HEAD_PKT_HIQ_V1(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1))\n#define BIT_GET_HEAD_PKT_HIQ_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1) & BIT_MASK_HEAD_PKT_HIQ_V1)\n#define BIT_SET_HEAD_PKT_HIQ_V1(x, v)                                          \\\n\t(BIT_CLEAR_HEAD_PKT_HIQ_V1(x) | BIT_HEAD_PKT_HIQ_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_QUEUELIST_ACQ_EN\t\t\t(Offset 0x0414) */\n\n#define BIT_ACQ0_ENABLE BIT(0)\n\n/* 2 REG_BCNQ_BDNY_V2\t\t\t(Offset 0x0418) */\n\n#define BIT_SHIFT_BCNQ_PGBNDY_WSEL 28\n#define BIT_MASK_BCNQ_PGBNDY_WSEL 0x7\n#define BIT_BCNQ_PGBNDY_WSEL(x)                                                \\\n\t(((x) & BIT_MASK_BCNQ_PGBNDY_WSEL) << BIT_SHIFT_BCNQ_PGBNDY_WSEL)\n#define BITS_BCNQ_PGBNDY_WSEL                                                  \\\n\t(BIT_MASK_BCNQ_PGBNDY_WSEL << BIT_SHIFT_BCNQ_PGBNDY_WSEL)\n#define BIT_CLEAR_BCNQ_PGBNDY_WSEL(x) ((x) & (~BITS_BCNQ_PGBNDY_WSEL))\n#define BIT_GET_BCNQ_PGBNDY_WSEL(x)                                            \\\n\t(((x) >> BIT_SHIFT_BCNQ_PGBNDY_WSEL) & BIT_MASK_BCNQ_PGBNDY_WSEL)\n#define BIT_SET_BCNQ_PGBNDY_WSEL(x, v)                                         \\\n\t(BIT_CLEAR_BCNQ_PGBNDY_WSEL(x) | BIT_BCNQ_PGBNDY_WSEL(v))\n\n#define BIT_SHIFT_BCNQ_PGBNDY_RCONTENT 12\n#define BIT_MASK_BCNQ_PGBNDY_RCONTENT 0xfff\n#define BIT_BCNQ_PGBNDY_RCONTENT(x)                                            \\\n\t(((x) & BIT_MASK_BCNQ_PGBNDY_RCONTENT)                                 \\\n\t << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT)\n#define BITS_BCNQ_PGBNDY_RCONTENT                                              \\\n\t(BIT_MASK_BCNQ_PGBNDY_RCONTENT << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT)\n#define BIT_CLEAR_BCNQ_PGBNDY_RCONTENT(x) ((x) & (~BITS_BCNQ_PGBNDY_RCONTENT))\n#define BIT_GET_BCNQ_PGBNDY_RCONTENT(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNQ_PGBNDY_RCONTENT) &                             \\\n\t BIT_MASK_BCNQ_PGBNDY_RCONTENT)\n#define BIT_SET_BCNQ_PGBNDY_RCONTENT(x, v)                                     \\\n\t(BIT_CLEAR_BCNQ_PGBNDY_RCONTENT(x) | BIT_BCNQ_PGBNDY_RCONTENT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BCNQ_INFO\t\t\t\t(Offset 0x0418) */\n\n#define BIT_SHIFT_PKT_NUM_BCNQ 8\n#define BIT_MASK_PKT_NUM_BCNQ 0xff\n#define BIT_PKT_NUM_BCNQ(x)                                                    \\\n\t(((x) & BIT_MASK_PKT_NUM_BCNQ) << BIT_SHIFT_PKT_NUM_BCNQ)\n#define BITS_PKT_NUM_BCNQ (BIT_MASK_PKT_NUM_BCNQ << BIT_SHIFT_PKT_NUM_BCNQ)\n#define BIT_CLEAR_PKT_NUM_BCNQ(x) ((x) & (~BITS_PKT_NUM_BCNQ))\n#define BIT_GET_PKT_NUM_BCNQ(x)                                                \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_BCNQ) & BIT_MASK_PKT_NUM_BCNQ)\n#define BIT_SET_PKT_NUM_BCNQ(x, v)                                             \\\n\t(BIT_CLEAR_PKT_NUM_BCNQ(x) | BIT_PKT_NUM_BCNQ(v))\n\n#define BIT_SHIFT_BCNQ_HEAD_PG 0\n#define BIT_MASK_BCNQ_HEAD_PG 0xff\n#define BIT_BCNQ_HEAD_PG(x)                                                    \\\n\t(((x) & BIT_MASK_BCNQ_HEAD_PG) << BIT_SHIFT_BCNQ_HEAD_PG)\n#define BITS_BCNQ_HEAD_PG (BIT_MASK_BCNQ_HEAD_PG << BIT_SHIFT_BCNQ_HEAD_PG)\n#define BIT_CLEAR_BCNQ_HEAD_PG(x) ((x) & (~BITS_BCNQ_HEAD_PG))\n#define BIT_GET_BCNQ_HEAD_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_BCNQ_HEAD_PG) & BIT_MASK_BCNQ_HEAD_PG)\n#define BIT_SET_BCNQ_HEAD_PG(x, v)                                             \\\n\t(BIT_CLEAR_BCNQ_HEAD_PG(x) | BIT_BCNQ_HEAD_PG(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCNQ_INFO\t\t\t\t(Offset 0x0418) */\n\n#define BIT_SHIFT_BCNQ_HEAD_PG_V1 0\n#define BIT_MASK_BCNQ_HEAD_PG_V1 0xfff\n#define BIT_BCNQ_HEAD_PG_V1(x)                                                 \\\n\t(((x) & BIT_MASK_BCNQ_HEAD_PG_V1) << BIT_SHIFT_BCNQ_HEAD_PG_V1)\n#define BITS_BCNQ_HEAD_PG_V1                                                   \\\n\t(BIT_MASK_BCNQ_HEAD_PG_V1 << BIT_SHIFT_BCNQ_HEAD_PG_V1)\n#define BIT_CLEAR_BCNQ_HEAD_PG_V1(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1))\n#define BIT_GET_BCNQ_HEAD_PG_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1) & BIT_MASK_BCNQ_HEAD_PG_V1)\n#define BIT_SET_BCNQ_HEAD_PG_V1(x, v)                                          \\\n\t(BIT_CLEAR_BCNQ_HEAD_PG_V1(x) | BIT_BCNQ_HEAD_PG_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_BCNQ_BDNY_V2\t\t\t(Offset 0x0418) */\n\n#define BIT_SHIFT_BCNQ_PGBNDY_WCONTENT 0\n#define BIT_MASK_BCNQ_PGBNDY_WCONTENT 0xfff\n#define BIT_BCNQ_PGBNDY_WCONTENT(x)                                            \\\n\t(((x) & BIT_MASK_BCNQ_PGBNDY_WCONTENT)                                 \\\n\t << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT)\n#define BITS_BCNQ_PGBNDY_WCONTENT                                              \\\n\t(BIT_MASK_BCNQ_PGBNDY_WCONTENT << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT)\n#define BIT_CLEAR_BCNQ_PGBNDY_WCONTENT(x) ((x) & (~BITS_BCNQ_PGBNDY_WCONTENT))\n#define BIT_GET_BCNQ_PGBNDY_WCONTENT(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNQ_PGBNDY_WCONTENT) &                             \\\n\t BIT_MASK_BCNQ_PGBNDY_WCONTENT)\n#define BIT_SET_BCNQ_PGBNDY_WCONTENT(x, v)                                     \\\n\t(BIT_CLEAR_BCNQ_PGBNDY_WCONTENT(x) | BIT_BCNQ_PGBNDY_WCONTENT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXPKT_EMPTY\t\t\t\t(Offset 0x041A) */\n\n#define BIT_BCNQ_EMPTY BIT(11)\n#define BIT_HQQ_EMPTY BIT(10)\n#define BIT_MQQ_EMPTY BIT(9)\n#define BIT_MGQ_CPU_EMPTY BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_BCN_POLL2 BIT(31)\n#define BIT_BCN_POLL1 BIT(30)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_BCN1_POLL BIT(30)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_CPUMGT_CLR_V1 BIT(30)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_CPUMGT_POLL BIT(29)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_CPUMGT_POLL_SET BIT(29)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_BCN_POLL BIT(28)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_CPUMGT_POLL_CLR BIT(27)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_CPUMGT_CLR BIT(27)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_EVTQ_VALID BIT(26)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_BCN_EXT_POLL BIT(21)\n#define BIT_BCN4_POLL BIT(20)\n#define BIT_BCN3_POLL BIT(19)\n#define BIT_BCN2_POLL BIT(18)\n#define BIT_BCN1_POLL_V1 BIT(17)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_EN_RTY_BK_COND BIT(16)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_BCN_POLL_V1 BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_CPUMGQ_FW_NUM_V1 BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_CPUMGQ_FW_NUM BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_EN_EVTQ_RPT BIT(2)\n#define BIT_HWSEQ_EVTQ_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_SHIFT_CPUMGQ_HEAD_PG 0\n#define BIT_MASK_CPUMGQ_HEAD_PG 0xff\n#define BIT_CPUMGQ_HEAD_PG(x)                                                  \\\n\t(((x) & BIT_MASK_CPUMGQ_HEAD_PG) << BIT_SHIFT_CPUMGQ_HEAD_PG)\n#define BITS_CPUMGQ_HEAD_PG                                                    \\\n\t(BIT_MASK_CPUMGQ_HEAD_PG << BIT_SHIFT_CPUMGQ_HEAD_PG)\n#define BIT_CLEAR_CPUMGQ_HEAD_PG(x) ((x) & (~BITS_CPUMGQ_HEAD_PG))\n#define BIT_GET_CPUMGQ_HEAD_PG(x)                                              \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_HEAD_PG) & BIT_MASK_CPUMGQ_HEAD_PG)\n#define BIT_SET_CPUMGQ_HEAD_PG(x, v)                                           \\\n\t(BIT_CLEAR_CPUMGQ_HEAD_PG(x) | BIT_CPUMGQ_HEAD_PG(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_SHIFT_FW_FREE_TAIL_V1 0\n#define BIT_MASK_FW_FREE_TAIL_V1 0xfff\n#define BIT_FW_FREE_TAIL_V1(x)                                                 \\\n\t(((x) & BIT_MASK_FW_FREE_TAIL_V1) << BIT_SHIFT_FW_FREE_TAIL_V1)\n#define BITS_FW_FREE_TAIL_V1                                                   \\\n\t(BIT_MASK_FW_FREE_TAIL_V1 << BIT_SHIFT_FW_FREE_TAIL_V1)\n#define BIT_CLEAR_FW_FREE_TAIL_V1(x) ((x) & (~BITS_FW_FREE_TAIL_V1))\n#define BIT_GET_FW_FREE_TAIL_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_FW_FREE_TAIL_V1) & BIT_MASK_FW_FREE_TAIL_V1)\n#define BIT_SET_FW_FREE_TAIL_V1(x, v)                                          \\\n\t(BIT_CLEAR_FW_FREE_TAIL_V1(x) | BIT_FW_FREE_TAIL_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CPU_MGQ_INFO\t\t\t(Offset 0x041C) */\n\n#define BIT_SHIFT_FREE_TAIL_PAGE 0\n#define BIT_MASK_FREE_TAIL_PAGE 0xfff\n#define BIT_FREE_TAIL_PAGE(x)                                                  \\\n\t(((x) & BIT_MASK_FREE_TAIL_PAGE) << BIT_SHIFT_FREE_TAIL_PAGE)\n#define BITS_FREE_TAIL_PAGE                                                    \\\n\t(BIT_MASK_FREE_TAIL_PAGE << BIT_SHIFT_FREE_TAIL_PAGE)\n#define BIT_CLEAR_FREE_TAIL_PAGE(x) ((x) & (~BITS_FREE_TAIL_PAGE))\n#define BIT_GET_FREE_TAIL_PAGE(x)                                              \\\n\t(((x) >> BIT_SHIFT_FREE_TAIL_PAGE) & BIT_MASK_FREE_TAIL_PAGE)\n#define BIT_SET_FREE_TAIL_PAGE(x, v)                                           \\\n\t(BIT_CLEAR_FREE_TAIL_PAGE(x) | BIT_FREE_TAIL_PAGE(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_RTS_LIMIT_IN_OFDM BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_EN_BCNQ_DL BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_EN_RD_RESP_NAV_BK BIT(21)\n#define BIT_EN_WR_FREE_TAIL BIT(20)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_TXRPT_DIS BIT(19)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_NOTXRPT_USERATE_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_DIS_TXFAIL_RPT BIT(18)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_FTM_TIMEOUT_BYPASS BIT(16)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_EN_BCNQ_DL5 BIT(13)\n#define BIT_EN_BCNQ_DL4 BIT(12)\n#define BIT_EN_BCNQ_DL3 BIT(11)\n#define BIT_EN_BCNQ_DL2 BIT(10)\n#define BIT_EN_BCNQ_DL1 BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_SHIFT_EN_QUEUE_RPT 8\n#define BIT_MASK_EN_QUEUE_RPT 0xff\n#define BIT_EN_QUEUE_RPT(x)                                                    \\\n\t(((x) & BIT_MASK_EN_QUEUE_RPT) << BIT_SHIFT_EN_QUEUE_RPT)\n#define BITS_EN_QUEUE_RPT (BIT_MASK_EN_QUEUE_RPT << BIT_SHIFT_EN_QUEUE_RPT)\n#define BIT_CLEAR_EN_QUEUE_RPT(x) ((x) & (~BITS_EN_QUEUE_RPT))\n#define BIT_GET_EN_QUEUE_RPT(x)                                                \\\n\t(((x) >> BIT_SHIFT_EN_QUEUE_RPT) & BIT_MASK_EN_QUEUE_RPT)\n#define BIT_SET_EN_QUEUE_RPT(x, v)                                             \\\n\t(BIT_CLEAR_EN_QUEUE_RPT(x) | BIT_EN_QUEUE_RPT(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_EN_BCNQ_DL0 BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_EN_RTY_BK BIT(7)\n#define BIT_EN_USE_INI_RAT BIT(6)\n#define BIT_EN_RTS_NAV_BK BIT(5)\n#define BIT_DIS_SSN_CHECK BIT(4)\n#define BIT_MACID_MATCH_RTS BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_EN_BCN_TRXRPT_V1 BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_R_EN_FTMRPT BIT(1)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_R_EN_FTMRPT_V1 BIT(1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_EN_FTMRPT_V1 BIT(1)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_EN_FTMACKRPT BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_R_BMC_NAV_PROTECT BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_BMC_NAV_PROTECT BIT(0)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_FWHW_TXQ_CTRL\t\t\t(Offset 0x0420) */\n\n#define BIT_EN_FTMRPT BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HWSEQ_CTRL\t\t\t\t(Offset 0x0423) */\n\n#define BIT_HWSEQ_CPUM_EN BIT(7)\n#define BIT_HWSEQ_BCN_EN BIT(6)\n#define BIT_HWSEQ_HI_EN BIT(5)\n#define BIT_HWSEQ_MGT_EN BIT(4)\n#define BIT_HWSEQ_BK_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DATAFB_SEL\t\t\t\t(Offset 0x0423) */\n\n#define BIT_BROADCAST_RTY_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DATAFB_SEL\t\t\t\t(Offset 0x0423) */\n\n#define BIT_R_BROADCAST_RETRY_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HWSEQ_CTRL\t\t\t\t(Offset 0x0423) */\n\n#define BIT_HWSEQ_BE_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DATAFB_SEL\t\t\t\t(Offset 0x0423) */\n\n#define BIT__R_EN_RTY_BK_COD BIT(2)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DATAFB_SEL\t\t\t\t(Offset 0x0423) */\n\n#define BIT_EN_RTY_BK_COD BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HWSEQ_CTRL\t\t\t\t(Offset 0x0423) */\n\n#define BIT_HWSEQ_VI_EN BIT(1)\n#define BIT_HWSEQ_VO_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DATAFB_SEL\t\t\t\t(Offset 0x0423) */\n\n#define BIT_SHIFT__R_DATA_FALLBACK_SEL 0\n#define BIT_MASK__R_DATA_FALLBACK_SEL 0x3\n#define BIT__R_DATA_FALLBACK_SEL(x)                                            \\\n\t(((x) & BIT_MASK__R_DATA_FALLBACK_SEL)                                 \\\n\t << BIT_SHIFT__R_DATA_FALLBACK_SEL)\n#define BITS__R_DATA_FALLBACK_SEL                                              \\\n\t(BIT_MASK__R_DATA_FALLBACK_SEL << BIT_SHIFT__R_DATA_FALLBACK_SEL)\n#define BIT_CLEAR__R_DATA_FALLBACK_SEL(x) ((x) & (~BITS__R_DATA_FALLBACK_SEL))\n#define BIT_GET__R_DATA_FALLBACK_SEL(x)                                        \\\n\t(((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL) &                             \\\n\t BIT_MASK__R_DATA_FALLBACK_SEL)\n#define BIT_SET__R_DATA_FALLBACK_SEL(x, v)                                     \\\n\t(BIT_CLEAR__R_DATA_FALLBACK_SEL(x) | BIT__R_DATA_FALLBACK_SEL(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATAFB_SEL\t\t\t\t(Offset 0x0423) */\n\n#define BIT_SHIFT__DATA_FALLBACK_SEL 0\n#define BIT_MASK__DATA_FALLBACK_SEL 0x3\n#define BIT__DATA_FALLBACK_SEL(x)                                              \\\n\t(((x) & BIT_MASK__DATA_FALLBACK_SEL) << BIT_SHIFT__DATA_FALLBACK_SEL)\n#define BITS__DATA_FALLBACK_SEL                                                \\\n\t(BIT_MASK__DATA_FALLBACK_SEL << BIT_SHIFT__DATA_FALLBACK_SEL)\n#define BIT_CLEAR__DATA_FALLBACK_SEL(x) ((x) & (~BITS__DATA_FALLBACK_SEL))\n#define BIT_GET__DATA_FALLBACK_SEL(x)                                          \\\n\t(((x) >> BIT_SHIFT__DATA_FALLBACK_SEL) & BIT_MASK__DATA_FALLBACK_SEL)\n#define BIT_SET__DATA_FALLBACK_SEL(x, v)                                       \\\n\t(BIT_CLEAR__DATA_FALLBACK_SEL(x) | BIT__DATA_FALLBACK_SEL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_BCNQ_BDNY\t\t\t\t(Offset 0x0424) */\n\n#define BIT_SHIFT_MGQ_PGBNDY_V2 8\n#define BIT_MASK_MGQ_PGBNDY_V2 0xff\n#define BIT_MGQ_PGBNDY_V2(x)                                                   \\\n\t(((x) & BIT_MASK_MGQ_PGBNDY_V2) << BIT_SHIFT_MGQ_PGBNDY_V2)\n#define BITS_MGQ_PGBNDY_V2 (BIT_MASK_MGQ_PGBNDY_V2 << BIT_SHIFT_MGQ_PGBNDY_V2)\n#define BIT_CLEAR_MGQ_PGBNDY_V2(x) ((x) & (~BITS_MGQ_PGBNDY_V2))\n#define BIT_GET_MGQ_PGBNDY_V2(x)                                               \\\n\t(((x) >> BIT_SHIFT_MGQ_PGBNDY_V2) & BIT_MASK_MGQ_PGBNDY_V2)\n#define BIT_SET_MGQ_PGBNDY_V2(x, v)                                            \\\n\t(BIT_CLEAR_MGQ_PGBNDY_V2(x) | BIT_MGQ_PGBNDY_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BCNQ_BDNY\t\t\t\t(Offset 0x0424) */\n\n#define BIT_SHIFT_BCNQ_PGBNDY 0\n#define BIT_MASK_BCNQ_PGBNDY 0xff\n#define BIT_BCNQ_PGBNDY(x)                                                     \\\n\t(((x) & BIT_MASK_BCNQ_PGBNDY) << BIT_SHIFT_BCNQ_PGBNDY)\n#define BITS_BCNQ_PGBNDY (BIT_MASK_BCNQ_PGBNDY << BIT_SHIFT_BCNQ_PGBNDY)\n#define BIT_CLEAR_BCNQ_PGBNDY(x) ((x) & (~BITS_BCNQ_PGBNDY))\n#define BIT_GET_BCNQ_PGBNDY(x)                                                 \\\n\t(((x) >> BIT_SHIFT_BCNQ_PGBNDY) & BIT_MASK_BCNQ_PGBNDY)\n#define BIT_SET_BCNQ_PGBNDY(x, v)                                              \\\n\t(BIT_CLEAR_BCNQ_PGBNDY(x) | BIT_BCNQ_PGBNDY(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCNQ_BDNY_V1\t\t\t(Offset 0x0424) */\n\n#define BIT_SHIFT_BCNQ_PGBNDY_V1 0\n#define BIT_MASK_BCNQ_PGBNDY_V1 0xfff\n#define BIT_BCNQ_PGBNDY_V1(x)                                                  \\\n\t(((x) & BIT_MASK_BCNQ_PGBNDY_V1) << BIT_SHIFT_BCNQ_PGBNDY_V1)\n#define BITS_BCNQ_PGBNDY_V1                                                    \\\n\t(BIT_MASK_BCNQ_PGBNDY_V1 << BIT_SHIFT_BCNQ_PGBNDY_V1)\n#define BIT_CLEAR_BCNQ_PGBNDY_V1(x) ((x) & (~BITS_BCNQ_PGBNDY_V1))\n#define BIT_GET_BCNQ_PGBNDY_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1) & BIT_MASK_BCNQ_PGBNDY_V1)\n#define BIT_SET_BCNQ_PGBNDY_V1(x, v)                                           \\\n\t(BIT_CLEAR_BCNQ_PGBNDY_V1(x) | BIT_BCNQ_PGBNDY_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXBDNY\t\t\t\t(Offset 0x0424) */\n\n#define BIT_SHIFT_TXBNDY 0\n#define BIT_MASK_TXBNDY 0xfff\n#define BIT_TXBNDY(x) (((x) & BIT_MASK_TXBNDY) << BIT_SHIFT_TXBNDY)\n#define BITS_TXBNDY (BIT_MASK_TXBNDY << BIT_SHIFT_TXBNDY)\n#define BIT_CLEAR_TXBNDY(x) ((x) & (~BITS_TXBNDY))\n#define BIT_GET_TXBNDY(x) (((x) >> BIT_SHIFT_TXBNDY) & BIT_MASK_TXBNDY)\n#define BIT_SET_TXBNDY(x, v) (BIT_CLEAR_TXBNDY(x) | BIT_TXBNDY(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MGQ_BDNY\t\t\t\t(Offset 0x0425) */\n\n#define BIT_SHIFT_MGQ_PGBNDY 0\n#define BIT_MASK_MGQ_PGBNDY 0xff\n#define BIT_MGQ_PGBNDY(x) (((x) & BIT_MASK_MGQ_PGBNDY) << BIT_SHIFT_MGQ_PGBNDY)\n#define BITS_MGQ_PGBNDY (BIT_MASK_MGQ_PGBNDY << BIT_SHIFT_MGQ_PGBNDY)\n#define BIT_CLEAR_MGQ_PGBNDY(x) ((x) & (~BITS_MGQ_PGBNDY))\n#define BIT_GET_MGQ_PGBNDY(x)                                                  \\\n\t(((x) >> BIT_SHIFT_MGQ_PGBNDY) & BIT_MASK_MGQ_PGBNDY)\n#define BIT_SET_MGQ_PGBNDY(x, v) (BIT_CLEAR_MGQ_PGBNDY(x) | BIT_MGQ_PGBNDY(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LIFETIME_EN\t\t\t\t(Offset 0x0426) */\n\n#define BIT_BT_INT_CPU BIT(7)\n#define BIT_BT_INT_PTA BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LIFETIME_EN\t\t\t\t(Offset 0x0426) */\n\n#define BIT_SPERPT_ENTRY BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LIFETIME_EN\t\t\t\t(Offset 0x0426) */\n\n#define BIT_RTYCNT_FB BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_LIFETIME_EN\t\t\t\t(Offset 0x0426) */\n\n#define BIT_EN_CTRL_RTYBIT BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LIFETIME_EN\t\t\t\t(Offset 0x0426) */\n\n#define BIT_LIFETIME_BK_EN BIT(3)\n#define BIT_LIFETIME_BE_EN BIT(2)\n#define BIT_LIFETIME_VI_EN BIT(1)\n#define BIT_LIFETIME_VO_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FW_FREE_TAIL\t\t\t(Offset 0x0427) */\n\n#define BIT_SHIFT_FW_FREE_TAIL 0\n#define BIT_MASK_FW_FREE_TAIL 0xff\n#define BIT_FW_FREE_TAIL(x)                                                    \\\n\t(((x) & BIT_MASK_FW_FREE_TAIL) << BIT_SHIFT_FW_FREE_TAIL)\n#define BITS_FW_FREE_TAIL (BIT_MASK_FW_FREE_TAIL << BIT_SHIFT_FW_FREE_TAIL)\n#define BIT_CLEAR_FW_FREE_TAIL(x) ((x) & (~BITS_FW_FREE_TAIL))\n#define BIT_GET_FW_FREE_TAIL(x)                                                \\\n\t(((x) >> BIT_SHIFT_FW_FREE_TAIL) & BIT_MASK_FW_FREE_TAIL)\n#define BIT_SET_FW_FREE_TAIL(x, v)                                             \\\n\t(BIT_CLEAR_FW_FREE_TAIL(x) | BIT_FW_FREE_TAIL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SPEC_SIFS\t\t\t\t(Offset 0x0428) */\n\n#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL 8\n#define BIT_MASK_SPEC_SIFS_OFDM_PTCL 0xff\n#define BIT_SPEC_SIFS_OFDM_PTCL(x)                                             \\\n\t(((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL)\n#define BITS_SPEC_SIFS_OFDM_PTCL                                               \\\n\t(BIT_MASK_SPEC_SIFS_OFDM_PTCL << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL)\n#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL(x) ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL))\n#define BIT_GET_SPEC_SIFS_OFDM_PTCL(x)                                         \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) & BIT_MASK_SPEC_SIFS_OFDM_PTCL)\n#define BIT_SET_SPEC_SIFS_OFDM_PTCL(x, v)                                      \\\n\t(BIT_CLEAR_SPEC_SIFS_OFDM_PTCL(x) | BIT_SPEC_SIFS_OFDM_PTCL(v))\n\n#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL 0\n#define BIT_MASK_SPEC_SIFS_CCK_PTCL 0xff\n#define BIT_SPEC_SIFS_CCK_PTCL(x)                                              \\\n\t(((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL)\n#define BITS_SPEC_SIFS_CCK_PTCL                                                \\\n\t(BIT_MASK_SPEC_SIFS_CCK_PTCL << BIT_SHIFT_SPEC_SIFS_CCK_PTCL)\n#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL(x) ((x) & (~BITS_SPEC_SIFS_CCK_PTCL))\n#define BIT_GET_SPEC_SIFS_CCK_PTCL(x)                                          \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL) & BIT_MASK_SPEC_SIFS_CCK_PTCL)\n#define BIT_SET_SPEC_SIFS_CCK_PTCL(x, v)                                       \\\n\t(BIT_CLEAR_SPEC_SIFS_CCK_PTCL(x) | BIT_SPEC_SIFS_CCK_PTCL(v))\n\n/* 2 REG_RETRY_LIMIT\t\t\t\t(Offset 0x042A) */\n\n#define BIT_SHIFT_SRL 8\n#define BIT_MASK_SRL 0x3f\n#define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL)\n#define BITS_SRL (BIT_MASK_SRL << BIT_SHIFT_SRL)\n#define BIT_CLEAR_SRL(x) ((x) & (~BITS_SRL))\n#define BIT_GET_SRL(x) (((x) >> BIT_SHIFT_SRL) & BIT_MASK_SRL)\n#define BIT_SET_SRL(x, v) (BIT_CLEAR_SRL(x) | BIT_SRL(v))\n\n#define BIT_SHIFT_LRL 0\n#define BIT_MASK_LRL 0x3f\n#define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL)\n#define BITS_LRL (BIT_MASK_LRL << BIT_SHIFT_LRL)\n#define BIT_CLEAR_LRL(x) ((x) & (~BITS_LRL))\n#define BIT_GET_LRL(x) (((x) >> BIT_SHIFT_LRL) & BIT_MASK_LRL)\n#define BIT_SET_LRL(x, v) (BIT_CLEAR_LRL(x) | BIT_LRL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_R_ENABLE_NDPA BIT(31)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_ENABLE_NDPA BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_USE_NDPA_PARAMETER BIT(30)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_NDPA_PARA BIT(30)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_R_PROP_TXBF BIT(29)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_PROP_TXBF BIT(29)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_R_EN_NDPA_INT BIT(28)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_EN_NDPA_INT BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_R_TXBF1_80M BIT(27)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_TXBF1_80M BIT(27)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_TXBF1_80M_160M BIT(27)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_R_TXBF1_40M BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_TXBF1_40M BIT(26)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_R_TXBF1_20M BIT(25)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_TXBF1_20M BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_SHIFT_R_TXBF1_AID 16\n#define BIT_MASK_R_TXBF1_AID 0x1ff\n#define BIT_R_TXBF1_AID(x)                                                     \\\n\t(((x) & BIT_MASK_R_TXBF1_AID) << BIT_SHIFT_R_TXBF1_AID)\n#define BITS_R_TXBF1_AID (BIT_MASK_R_TXBF1_AID << BIT_SHIFT_R_TXBF1_AID)\n#define BIT_CLEAR_R_TXBF1_AID(x) ((x) & (~BITS_R_TXBF1_AID))\n#define BIT_GET_R_TXBF1_AID(x)                                                 \\\n\t(((x) >> BIT_SHIFT_R_TXBF1_AID) & BIT_MASK_R_TXBF1_AID)\n#define BIT_SET_R_TXBF1_AID(x, v)                                              \\\n\t(BIT_CLEAR_R_TXBF1_AID(x) | BIT_R_TXBF1_AID(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_SHIFT_TXBF1_AID 16\n#define BIT_MASK_TXBF1_AID 0x1ff\n#define BIT_TXBF1_AID(x) (((x) & BIT_MASK_TXBF1_AID) << BIT_SHIFT_TXBF1_AID)\n#define BITS_TXBF1_AID (BIT_MASK_TXBF1_AID << BIT_SHIFT_TXBF1_AID)\n#define BIT_CLEAR_TXBF1_AID(x) ((x) & (~BITS_TXBF1_AID))\n#define BIT_GET_TXBF1_AID(x) (((x) >> BIT_SHIFT_TXBF1_AID) & BIT_MASK_TXBF1_AID)\n#define BIT_SET_TXBF1_AID(x, v) (BIT_CLEAR_TXBF1_AID(x) | BIT_TXBF1_AID(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_DIS_NDP_BFEN BIT(15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_TXBCN_NOBLOCK_NDP BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_R_TXBCN_NOBLOCK_NDP BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_R_TXBF0_80M BIT(11)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_TXBF0_80M BIT(11)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_TXBF0_80M_160M BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_R_TXBF0_40M BIT(10)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_TXBF0_40M BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_R_TXBF0_20M BIT(9)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_TXBF0_20M BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_SHIFT_R_TXBF0_AID 0\n#define BIT_MASK_R_TXBF0_AID 0x1ff\n#define BIT_R_TXBF0_AID(x)                                                     \\\n\t(((x) & BIT_MASK_R_TXBF0_AID) << BIT_SHIFT_R_TXBF0_AID)\n#define BITS_R_TXBF0_AID (BIT_MASK_R_TXBF0_AID << BIT_SHIFT_R_TXBF0_AID)\n#define BIT_CLEAR_R_TXBF0_AID(x) ((x) & (~BITS_R_TXBF0_AID))\n#define BIT_GET_R_TXBF0_AID(x)                                                 \\\n\t(((x) >> BIT_SHIFT_R_TXBF0_AID) & BIT_MASK_R_TXBF0_AID)\n#define BIT_SET_R_TXBF0_AID(x, v)                                              \\\n\t(BIT_CLEAR_R_TXBF0_AID(x) | BIT_R_TXBF0_AID(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXBF_CTRL\t\t\t\t(Offset 0x042C) */\n\n#define BIT_SHIFT_TXBF0_AID 0\n#define BIT_MASK_TXBF0_AID 0x1ff\n#define BIT_TXBF0_AID(x) (((x) & BIT_MASK_TXBF0_AID) << BIT_SHIFT_TXBF0_AID)\n#define BITS_TXBF0_AID (BIT_MASK_TXBF0_AID << BIT_SHIFT_TXBF0_AID)\n#define BIT_CLEAR_TXBF0_AID(x) ((x) & (~BITS_TXBF0_AID))\n#define BIT_GET_TXBF0_AID(x) (((x) >> BIT_SHIFT_TXBF0_AID) & BIT_MASK_TXBF0_AID)\n#define BIT_SET_TXBF0_AID(x, v) (BIT_CLEAR_TXBF0_AID(x) | BIT_TXBF0_AID(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DARFRC\t\t\t\t(Offset 0x0430) */\n\n#define BIT_SHIFT_DARF_RC8 (56 & CPU_OPT_WIDTH)\n#define BIT_MASK_DARF_RC8 0x1f\n#define BIT_DARF_RC8(x) (((x) & BIT_MASK_DARF_RC8) << BIT_SHIFT_DARF_RC8)\n#define BITS_DARF_RC8 (BIT_MASK_DARF_RC8 << BIT_SHIFT_DARF_RC8)\n#define BIT_CLEAR_DARF_RC8(x) ((x) & (~BITS_DARF_RC8))\n#define BIT_GET_DARF_RC8(x) (((x) >> BIT_SHIFT_DARF_RC8) & BIT_MASK_DARF_RC8)\n#define BIT_SET_DARF_RC8(x, v) (BIT_CLEAR_DARF_RC8(x) | BIT_DARF_RC8(v))\n\n#define BIT_SHIFT_DARF_RC7 (48 & CPU_OPT_WIDTH)\n#define BIT_MASK_DARF_RC7 0x1f\n#define BIT_DARF_RC7(x) (((x) & BIT_MASK_DARF_RC7) << BIT_SHIFT_DARF_RC7)\n#define BITS_DARF_RC7 (BIT_MASK_DARF_RC7 << BIT_SHIFT_DARF_RC7)\n#define BIT_CLEAR_DARF_RC7(x) ((x) & (~BITS_DARF_RC7))\n#define BIT_GET_DARF_RC7(x) (((x) >> BIT_SHIFT_DARF_RC7) & BIT_MASK_DARF_RC7)\n#define BIT_SET_DARF_RC7(x, v) (BIT_CLEAR_DARF_RC7(x) | BIT_DARF_RC7(v))\n\n#define BIT_SHIFT_DARF_RC6 (40 & CPU_OPT_WIDTH)\n#define BIT_MASK_DARF_RC6 0x1f\n#define BIT_DARF_RC6(x) (((x) & BIT_MASK_DARF_RC6) << BIT_SHIFT_DARF_RC6)\n#define BITS_DARF_RC6 (BIT_MASK_DARF_RC6 << BIT_SHIFT_DARF_RC6)\n#define BIT_CLEAR_DARF_RC6(x) ((x) & (~BITS_DARF_RC6))\n#define BIT_GET_DARF_RC6(x) (((x) >> BIT_SHIFT_DARF_RC6) & BIT_MASK_DARF_RC6)\n#define BIT_SET_DARF_RC6(x, v) (BIT_CLEAR_DARF_RC6(x) | BIT_DARF_RC6(v))\n\n#define BIT_SHIFT_DARF_RC5 (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_DARF_RC5 0x1f\n#define BIT_DARF_RC5(x) (((x) & BIT_MASK_DARF_RC5) << BIT_SHIFT_DARF_RC5)\n#define BITS_DARF_RC5 (BIT_MASK_DARF_RC5 << BIT_SHIFT_DARF_RC5)\n#define BIT_CLEAR_DARF_RC5(x) ((x) & (~BITS_DARF_RC5))\n#define BIT_GET_DARF_RC5(x) (((x) >> BIT_SHIFT_DARF_RC5) & BIT_MASK_DARF_RC5)\n#define BIT_SET_DARF_RC5(x, v) (BIT_CLEAR_DARF_RC5(x) | BIT_DARF_RC5(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DARFRC\t\t\t\t(Offset 0x0430) */\n\n#define BIT_SHIFT_DARF_RC4 24\n#define BIT_MASK_DARF_RC4 0x1f\n#define BIT_DARF_RC4(x) (((x) & BIT_MASK_DARF_RC4) << BIT_SHIFT_DARF_RC4)\n#define BITS_DARF_RC4 (BIT_MASK_DARF_RC4 << BIT_SHIFT_DARF_RC4)\n#define BIT_CLEAR_DARF_RC4(x) ((x) & (~BITS_DARF_RC4))\n#define BIT_GET_DARF_RC4(x) (((x) >> BIT_SHIFT_DARF_RC4) & BIT_MASK_DARF_RC4)\n#define BIT_SET_DARF_RC4(x, v) (BIT_CLEAR_DARF_RC4(x) | BIT_DARF_RC4(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DARFRC\t\t\t\t(Offset 0x0430) */\n\n#define BIT_SHIFT_DARF_RC4_V2 24\n#define BIT_MASK_DARF_RC4_V2 0x1f\n#define BIT_DARF_RC4_V2(x)                                                     \\\n\t(((x) & BIT_MASK_DARF_RC4_V2) << BIT_SHIFT_DARF_RC4_V2)\n#define BITS_DARF_RC4_V2 (BIT_MASK_DARF_RC4_V2 << BIT_SHIFT_DARF_RC4_V2)\n#define BIT_CLEAR_DARF_RC4_V2(x) ((x) & (~BITS_DARF_RC4_V2))\n#define BIT_GET_DARF_RC4_V2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DARF_RC4_V2) & BIT_MASK_DARF_RC4_V2)\n#define BIT_SET_DARF_RC4_V2(x, v)                                              \\\n\t(BIT_CLEAR_DARF_RC4_V2(x) | BIT_DARF_RC4_V2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DARFRC\t\t\t\t(Offset 0x0430) */\n\n#define BIT_SHIFT_DARF_RC4_V1 24\n#define BIT_MASK_DARF_RC4_V1 0x3f\n#define BIT_DARF_RC4_V1(x)                                                     \\\n\t(((x) & BIT_MASK_DARF_RC4_V1) << BIT_SHIFT_DARF_RC4_V1)\n#define BITS_DARF_RC4_V1 (BIT_MASK_DARF_RC4_V1 << BIT_SHIFT_DARF_RC4_V1)\n#define BIT_CLEAR_DARF_RC4_V1(x) ((x) & (~BITS_DARF_RC4_V1))\n#define BIT_GET_DARF_RC4_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DARF_RC4_V1) & BIT_MASK_DARF_RC4_V1)\n#define BIT_SET_DARF_RC4_V1(x, v)                                              \\\n\t(BIT_CLEAR_DARF_RC4_V1(x) | BIT_DARF_RC4_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DARFRC\t\t\t\t(Offset 0x0430) */\n\n#define BIT_SHIFT_DARF_RC3 16\n#define BIT_MASK_DARF_RC3 0x1f\n#define BIT_DARF_RC3(x) (((x) & BIT_MASK_DARF_RC3) << BIT_SHIFT_DARF_RC3)\n#define BITS_DARF_RC3 (BIT_MASK_DARF_RC3 << BIT_SHIFT_DARF_RC3)\n#define BIT_CLEAR_DARF_RC3(x) ((x) & (~BITS_DARF_RC3))\n#define BIT_GET_DARF_RC3(x) (((x) >> BIT_SHIFT_DARF_RC3) & BIT_MASK_DARF_RC3)\n#define BIT_SET_DARF_RC3(x, v) (BIT_CLEAR_DARF_RC3(x) | BIT_DARF_RC3(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DARFRC\t\t\t\t(Offset 0x0430) */\n\n#define BIT_SHIFT_DARF_RC3_V2 16\n#define BIT_MASK_DARF_RC3_V2 0x1f\n#define BIT_DARF_RC3_V2(x)                                                     \\\n\t(((x) & BIT_MASK_DARF_RC3_V2) << BIT_SHIFT_DARF_RC3_V2)\n#define BITS_DARF_RC3_V2 (BIT_MASK_DARF_RC3_V2 << BIT_SHIFT_DARF_RC3_V2)\n#define BIT_CLEAR_DARF_RC3_V2(x) ((x) & (~BITS_DARF_RC3_V2))\n#define BIT_GET_DARF_RC3_V2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DARF_RC3_V2) & BIT_MASK_DARF_RC3_V2)\n#define BIT_SET_DARF_RC3_V2(x, v)                                              \\\n\t(BIT_CLEAR_DARF_RC3_V2(x) | BIT_DARF_RC3_V2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DARFRC\t\t\t\t(Offset 0x0430) */\n\n#define BIT_SHIFT_DARF_RC3_V1 16\n#define BIT_MASK_DARF_RC3_V1 0x3f\n#define BIT_DARF_RC3_V1(x)                                                     \\\n\t(((x) & BIT_MASK_DARF_RC3_V1) << BIT_SHIFT_DARF_RC3_V1)\n#define BITS_DARF_RC3_V1 (BIT_MASK_DARF_RC3_V1 << BIT_SHIFT_DARF_RC3_V1)\n#define BIT_CLEAR_DARF_RC3_V1(x) ((x) & (~BITS_DARF_RC3_V1))\n#define BIT_GET_DARF_RC3_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DARF_RC3_V1) & BIT_MASK_DARF_RC3_V1)\n#define BIT_SET_DARF_RC3_V1(x, v)                                              \\\n\t(BIT_CLEAR_DARF_RC3_V1(x) | BIT_DARF_RC3_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DARFRC\t\t\t\t(Offset 0x0430) */\n\n#define BIT_SHIFT_DARF_RC2 8\n#define BIT_MASK_DARF_RC2 0x1f\n#define BIT_DARF_RC2(x) (((x) & BIT_MASK_DARF_RC2) << BIT_SHIFT_DARF_RC2)\n#define BITS_DARF_RC2 (BIT_MASK_DARF_RC2 << BIT_SHIFT_DARF_RC2)\n#define BIT_CLEAR_DARF_RC2(x) ((x) & (~BITS_DARF_RC2))\n#define BIT_GET_DARF_RC2(x) (((x) >> BIT_SHIFT_DARF_RC2) & BIT_MASK_DARF_RC2)\n#define BIT_SET_DARF_RC2(x, v) (BIT_CLEAR_DARF_RC2(x) | BIT_DARF_RC2(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DARFRC\t\t\t\t(Offset 0x0430) */\n\n#define BIT_SHIFT_DARF_RC2_V2 8\n#define BIT_MASK_DARF_RC2_V2 0x1f\n#define BIT_DARF_RC2_V2(x)                                                     \\\n\t(((x) & BIT_MASK_DARF_RC2_V2) << BIT_SHIFT_DARF_RC2_V2)\n#define BITS_DARF_RC2_V2 (BIT_MASK_DARF_RC2_V2 << BIT_SHIFT_DARF_RC2_V2)\n#define BIT_CLEAR_DARF_RC2_V2(x) ((x) & (~BITS_DARF_RC2_V2))\n#define BIT_GET_DARF_RC2_V2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DARF_RC2_V2) & BIT_MASK_DARF_RC2_V2)\n#define BIT_SET_DARF_RC2_V2(x, v)                                              \\\n\t(BIT_CLEAR_DARF_RC2_V2(x) | BIT_DARF_RC2_V2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DARFRC\t\t\t\t(Offset 0x0430) */\n\n#define BIT_SHIFT_DARF_RC2_V1 8\n#define BIT_MASK_DARF_RC2_V1 0x3f\n#define BIT_DARF_RC2_V1(x)                                                     \\\n\t(((x) & BIT_MASK_DARF_RC2_V1) << BIT_SHIFT_DARF_RC2_V1)\n#define BITS_DARF_RC2_V1 (BIT_MASK_DARF_RC2_V1 << BIT_SHIFT_DARF_RC2_V1)\n#define BIT_CLEAR_DARF_RC2_V1(x) ((x) & (~BITS_DARF_RC2_V1))\n#define BIT_GET_DARF_RC2_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DARF_RC2_V1) & BIT_MASK_DARF_RC2_V1)\n#define BIT_SET_DARF_RC2_V1(x, v)                                              \\\n\t(BIT_CLEAR_DARF_RC2_V1(x) | BIT_DARF_RC2_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DARFRC\t\t\t\t(Offset 0x0430) */\n\n#define BIT_SHIFT_DARF_RC1 0\n#define BIT_MASK_DARF_RC1 0x1f\n#define BIT_DARF_RC1(x) (((x) & BIT_MASK_DARF_RC1) << BIT_SHIFT_DARF_RC1)\n#define BITS_DARF_RC1 (BIT_MASK_DARF_RC1 << BIT_SHIFT_DARF_RC1)\n#define BIT_CLEAR_DARF_RC1(x) ((x) & (~BITS_DARF_RC1))\n#define BIT_GET_DARF_RC1(x) (((x) >> BIT_SHIFT_DARF_RC1) & BIT_MASK_DARF_RC1)\n#define BIT_SET_DARF_RC1(x, v) (BIT_CLEAR_DARF_RC1(x) | BIT_DARF_RC1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DARFRC\t\t\t\t(Offset 0x0430) */\n\n#define BIT_SHIFT_DARF_RC1_V2 0\n#define BIT_MASK_DARF_RC1_V2 0x1f\n#define BIT_DARF_RC1_V2(x)                                                     \\\n\t(((x) & BIT_MASK_DARF_RC1_V2) << BIT_SHIFT_DARF_RC1_V2)\n#define BITS_DARF_RC1_V2 (BIT_MASK_DARF_RC1_V2 << BIT_SHIFT_DARF_RC1_V2)\n#define BIT_CLEAR_DARF_RC1_V2(x) ((x) & (~BITS_DARF_RC1_V2))\n#define BIT_GET_DARF_RC1_V2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DARF_RC1_V2) & BIT_MASK_DARF_RC1_V2)\n#define BIT_SET_DARF_RC1_V2(x, v)                                              \\\n\t(BIT_CLEAR_DARF_RC1_V2(x) | BIT_DARF_RC1_V2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DARFRC\t\t\t\t(Offset 0x0430) */\n\n#define BIT_SHIFT_DARF_RC1_V1 0\n#define BIT_MASK_DARF_RC1_V1 0x3f\n#define BIT_DARF_RC1_V1(x)                                                     \\\n\t(((x) & BIT_MASK_DARF_RC1_V1) << BIT_SHIFT_DARF_RC1_V1)\n#define BITS_DARF_RC1_V1 (BIT_MASK_DARF_RC1_V1 << BIT_SHIFT_DARF_RC1_V1)\n#define BIT_CLEAR_DARF_RC1_V1(x) ((x) & (~BITS_DARF_RC1_V1))\n#define BIT_GET_DARF_RC1_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DARF_RC1_V1) & BIT_MASK_DARF_RC1_V1)\n#define BIT_SET_DARF_RC1_V1(x, v)                                              \\\n\t(BIT_CLEAR_DARF_RC1_V1(x) | BIT_DARF_RC1_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DARFRCH\t\t\t\t(Offset 0x0434) */\n\n#define BIT_SHIFT_DARF_RC8_V3 24\n#define BIT_MASK_DARF_RC8_V3 0x1f\n#define BIT_DARF_RC8_V3(x)                                                     \\\n\t(((x) & BIT_MASK_DARF_RC8_V3) << BIT_SHIFT_DARF_RC8_V3)\n#define BITS_DARF_RC8_V3 (BIT_MASK_DARF_RC8_V3 << BIT_SHIFT_DARF_RC8_V3)\n#define BIT_CLEAR_DARF_RC8_V3(x) ((x) & (~BITS_DARF_RC8_V3))\n#define BIT_GET_DARF_RC8_V3(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DARF_RC8_V3) & BIT_MASK_DARF_RC8_V3)\n#define BIT_SET_DARF_RC8_V3(x, v)                                              \\\n\t(BIT_CLEAR_DARF_RC8_V3(x) | BIT_DARF_RC8_V3(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DARFRCH\t\t\t\t(Offset 0x0434) */\n\n#define BIT_SHIFT_DARF_RC8_V1 24\n#define BIT_MASK_DARF_RC8_V1 0x1f\n#define BIT_DARF_RC8_V1(x)                                                     \\\n\t(((x) & BIT_MASK_DARF_RC8_V1) << BIT_SHIFT_DARF_RC8_V1)\n#define BITS_DARF_RC8_V1 (BIT_MASK_DARF_RC8_V1 << BIT_SHIFT_DARF_RC8_V1)\n#define BIT_CLEAR_DARF_RC8_V1(x) ((x) & (~BITS_DARF_RC8_V1))\n#define BIT_GET_DARF_RC8_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DARF_RC8_V1) & BIT_MASK_DARF_RC8_V1)\n#define BIT_SET_DARF_RC8_V1(x, v)                                              \\\n\t(BIT_CLEAR_DARF_RC8_V1(x) | BIT_DARF_RC8_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DARFRCH\t\t\t\t(Offset 0x0434) */\n\n#define BIT_SHIFT_DARF_RC7_V3 16\n#define BIT_MASK_DARF_RC7_V3 0x1f\n#define BIT_DARF_RC7_V3(x)                                                     \\\n\t(((x) & BIT_MASK_DARF_RC7_V3) << BIT_SHIFT_DARF_RC7_V3)\n#define BITS_DARF_RC7_V3 (BIT_MASK_DARF_RC7_V3 << BIT_SHIFT_DARF_RC7_V3)\n#define BIT_CLEAR_DARF_RC7_V3(x) ((x) & (~BITS_DARF_RC7_V3))\n#define BIT_GET_DARF_RC7_V3(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DARF_RC7_V3) & BIT_MASK_DARF_RC7_V3)\n#define BIT_SET_DARF_RC7_V3(x, v)                                              \\\n\t(BIT_CLEAR_DARF_RC7_V3(x) | BIT_DARF_RC7_V3(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DARFRCH\t\t\t\t(Offset 0x0434) */\n\n#define BIT_SHIFT_DARF_RC7_V1 16\n#define BIT_MASK_DARF_RC7_V1 0x1f\n#define BIT_DARF_RC7_V1(x)                                                     \\\n\t(((x) & BIT_MASK_DARF_RC7_V1) << BIT_SHIFT_DARF_RC7_V1)\n#define BITS_DARF_RC7_V1 (BIT_MASK_DARF_RC7_V1 << BIT_SHIFT_DARF_RC7_V1)\n#define BIT_CLEAR_DARF_RC7_V1(x) ((x) & (~BITS_DARF_RC7_V1))\n#define BIT_GET_DARF_RC7_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DARF_RC7_V1) & BIT_MASK_DARF_RC7_V1)\n#define BIT_SET_DARF_RC7_V1(x, v)                                              \\\n\t(BIT_CLEAR_DARF_RC7_V1(x) | BIT_DARF_RC7_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DARFRCH\t\t\t\t(Offset 0x0434) */\n\n#define BIT_SHIFT_DARF_RC6_V3 8\n#define BIT_MASK_DARF_RC6_V3 0x1f\n#define BIT_DARF_RC6_V3(x)                                                     \\\n\t(((x) & BIT_MASK_DARF_RC6_V3) << BIT_SHIFT_DARF_RC6_V3)\n#define BITS_DARF_RC6_V3 (BIT_MASK_DARF_RC6_V3 << BIT_SHIFT_DARF_RC6_V3)\n#define BIT_CLEAR_DARF_RC6_V3(x) ((x) & (~BITS_DARF_RC6_V3))\n#define BIT_GET_DARF_RC6_V3(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DARF_RC6_V3) & BIT_MASK_DARF_RC6_V3)\n#define BIT_SET_DARF_RC6_V3(x, v)                                              \\\n\t(BIT_CLEAR_DARF_RC6_V3(x) | BIT_DARF_RC6_V3(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DARFRCH\t\t\t\t(Offset 0x0434) */\n\n#define BIT_SHIFT_DARF_RC6_V1 8\n#define BIT_MASK_DARF_RC6_V1 0x1f\n#define BIT_DARF_RC6_V1(x)                                                     \\\n\t(((x) & BIT_MASK_DARF_RC6_V1) << BIT_SHIFT_DARF_RC6_V1)\n#define BITS_DARF_RC6_V1 (BIT_MASK_DARF_RC6_V1 << BIT_SHIFT_DARF_RC6_V1)\n#define BIT_CLEAR_DARF_RC6_V1(x) ((x) & (~BITS_DARF_RC6_V1))\n#define BIT_GET_DARF_RC6_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DARF_RC6_V1) & BIT_MASK_DARF_RC6_V1)\n#define BIT_SET_DARF_RC6_V1(x, v)                                              \\\n\t(BIT_CLEAR_DARF_RC6_V1(x) | BIT_DARF_RC6_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DARFRCH\t\t\t\t(Offset 0x0434) */\n\n#define BIT_SHIFT_DARF_RC5_V3 0\n#define BIT_MASK_DARF_RC5_V3 0x1f\n#define BIT_DARF_RC5_V3(x)                                                     \\\n\t(((x) & BIT_MASK_DARF_RC5_V3) << BIT_SHIFT_DARF_RC5_V3)\n#define BITS_DARF_RC5_V3 (BIT_MASK_DARF_RC5_V3 << BIT_SHIFT_DARF_RC5_V3)\n#define BIT_CLEAR_DARF_RC5_V3(x) ((x) & (~BITS_DARF_RC5_V3))\n#define BIT_GET_DARF_RC5_V3(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DARF_RC5_V3) & BIT_MASK_DARF_RC5_V3)\n#define BIT_SET_DARF_RC5_V3(x, v)                                              \\\n\t(BIT_CLEAR_DARF_RC5_V3(x) | BIT_DARF_RC5_V3(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DARFRCH\t\t\t\t(Offset 0x0434) */\n\n#define BIT_SHIFT_DARF_RC5_V1 0\n#define BIT_MASK_DARF_RC5_V1 0x1f\n#define BIT_DARF_RC5_V1(x)                                                     \\\n\t(((x) & BIT_MASK_DARF_RC5_V1) << BIT_SHIFT_DARF_RC5_V1)\n#define BITS_DARF_RC5_V1 (BIT_MASK_DARF_RC5_V1 << BIT_SHIFT_DARF_RC5_V1)\n#define BIT_CLEAR_DARF_RC5_V1(x) ((x) & (~BITS_DARF_RC5_V1))\n#define BIT_GET_DARF_RC5_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DARF_RC5_V1) & BIT_MASK_DARF_RC5_V1)\n#define BIT_SET_DARF_RC5_V1(x, v)                                              \\\n\t(BIT_CLEAR_DARF_RC5_V1(x) | BIT_DARF_RC5_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RARFRC\t\t\t\t(Offset 0x0438) */\n\n#define BIT_SHIFT_RARF_RC8 (56 & CPU_OPT_WIDTH)\n#define BIT_MASK_RARF_RC8 0x1f\n#define BIT_RARF_RC8(x) (((x) & BIT_MASK_RARF_RC8) << BIT_SHIFT_RARF_RC8)\n#define BITS_RARF_RC8 (BIT_MASK_RARF_RC8 << BIT_SHIFT_RARF_RC8)\n#define BIT_CLEAR_RARF_RC8(x) ((x) & (~BITS_RARF_RC8))\n#define BIT_GET_RARF_RC8(x) (((x) >> BIT_SHIFT_RARF_RC8) & BIT_MASK_RARF_RC8)\n#define BIT_SET_RARF_RC8(x, v) (BIT_CLEAR_RARF_RC8(x) | BIT_RARF_RC8(v))\n\n#define BIT_SHIFT_RARF_RC7 (48 & CPU_OPT_WIDTH)\n#define BIT_MASK_RARF_RC7 0x1f\n#define BIT_RARF_RC7(x) (((x) & BIT_MASK_RARF_RC7) << BIT_SHIFT_RARF_RC7)\n#define BITS_RARF_RC7 (BIT_MASK_RARF_RC7 << BIT_SHIFT_RARF_RC7)\n#define BIT_CLEAR_RARF_RC7(x) ((x) & (~BITS_RARF_RC7))\n#define BIT_GET_RARF_RC7(x) (((x) >> BIT_SHIFT_RARF_RC7) & BIT_MASK_RARF_RC7)\n#define BIT_SET_RARF_RC7(x, v) (BIT_CLEAR_RARF_RC7(x) | BIT_RARF_RC7(v))\n\n#define BIT_SHIFT_RARF_RC6 (40 & CPU_OPT_WIDTH)\n#define BIT_MASK_RARF_RC6 0x1f\n#define BIT_RARF_RC6(x) (((x) & BIT_MASK_RARF_RC6) << BIT_SHIFT_RARF_RC6)\n#define BITS_RARF_RC6 (BIT_MASK_RARF_RC6 << BIT_SHIFT_RARF_RC6)\n#define BIT_CLEAR_RARF_RC6(x) ((x) & (~BITS_RARF_RC6))\n#define BIT_GET_RARF_RC6(x) (((x) >> BIT_SHIFT_RARF_RC6) & BIT_MASK_RARF_RC6)\n#define BIT_SET_RARF_RC6(x, v) (BIT_CLEAR_RARF_RC6(x) | BIT_RARF_RC6(v))\n\n#define BIT_SHIFT_RARF_RC5 (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_RARF_RC5 0x1f\n#define BIT_RARF_RC5(x) (((x) & BIT_MASK_RARF_RC5) << BIT_SHIFT_RARF_RC5)\n#define BITS_RARF_RC5 (BIT_MASK_RARF_RC5 << BIT_SHIFT_RARF_RC5)\n#define BIT_CLEAR_RARF_RC5(x) ((x) & (~BITS_RARF_RC5))\n#define BIT_GET_RARF_RC5(x) (((x) >> BIT_SHIFT_RARF_RC5) & BIT_MASK_RARF_RC5)\n#define BIT_SET_RARF_RC5(x, v) (BIT_CLEAR_RARF_RC5(x) | BIT_RARF_RC5(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RARFRC\t\t\t\t(Offset 0x0438) */\n\n#define BIT_SHIFT_RARF_RC4 24\n#define BIT_MASK_RARF_RC4 0x1f\n#define BIT_RARF_RC4(x) (((x) & BIT_MASK_RARF_RC4) << BIT_SHIFT_RARF_RC4)\n#define BITS_RARF_RC4 (BIT_MASK_RARF_RC4 << BIT_SHIFT_RARF_RC4)\n#define BIT_CLEAR_RARF_RC4(x) ((x) & (~BITS_RARF_RC4))\n#define BIT_GET_RARF_RC4(x) (((x) >> BIT_SHIFT_RARF_RC4) & BIT_MASK_RARF_RC4)\n#define BIT_SET_RARF_RC4(x, v) (BIT_CLEAR_RARF_RC4(x) | BIT_RARF_RC4(v))\n\n#define BIT_SHIFT_RARF_RC3 16\n#define BIT_MASK_RARF_RC3 0x1f\n#define BIT_RARF_RC3(x) (((x) & BIT_MASK_RARF_RC3) << BIT_SHIFT_RARF_RC3)\n#define BITS_RARF_RC3 (BIT_MASK_RARF_RC3 << BIT_SHIFT_RARF_RC3)\n#define BIT_CLEAR_RARF_RC3(x) ((x) & (~BITS_RARF_RC3))\n#define BIT_GET_RARF_RC3(x) (((x) >> BIT_SHIFT_RARF_RC3) & BIT_MASK_RARF_RC3)\n#define BIT_SET_RARF_RC3(x, v) (BIT_CLEAR_RARF_RC3(x) | BIT_RARF_RC3(v))\n\n#define BIT_SHIFT_RARF_RC2 8\n#define BIT_MASK_RARF_RC2 0x1f\n#define BIT_RARF_RC2(x) (((x) & BIT_MASK_RARF_RC2) << BIT_SHIFT_RARF_RC2)\n#define BITS_RARF_RC2 (BIT_MASK_RARF_RC2 << BIT_SHIFT_RARF_RC2)\n#define BIT_CLEAR_RARF_RC2(x) ((x) & (~BITS_RARF_RC2))\n#define BIT_GET_RARF_RC2(x) (((x) >> BIT_SHIFT_RARF_RC2) & BIT_MASK_RARF_RC2)\n#define BIT_SET_RARF_RC2(x, v) (BIT_CLEAR_RARF_RC2(x) | BIT_RARF_RC2(v))\n\n#define BIT_SHIFT_RARF_RC1 0\n#define BIT_MASK_RARF_RC1 0x1f\n#define BIT_RARF_RC1(x) (((x) & BIT_MASK_RARF_RC1) << BIT_SHIFT_RARF_RC1)\n#define BITS_RARF_RC1 (BIT_MASK_RARF_RC1 << BIT_SHIFT_RARF_RC1)\n#define BIT_CLEAR_RARF_RC1(x) ((x) & (~BITS_RARF_RC1))\n#define BIT_GET_RARF_RC1(x) (((x) >> BIT_SHIFT_RARF_RC1) & BIT_MASK_RARF_RC1)\n#define BIT_SET_RARF_RC1(x, v) (BIT_CLEAR_RARF_RC1(x) | BIT_RARF_RC1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RARFRCH\t\t\t\t(Offset 0x043C) */\n\n#define BIT_SHIFT_RARF_RC8_V1 24\n#define BIT_MASK_RARF_RC8_V1 0x1f\n#define BIT_RARF_RC8_V1(x)                                                     \\\n\t(((x) & BIT_MASK_RARF_RC8_V1) << BIT_SHIFT_RARF_RC8_V1)\n#define BITS_RARF_RC8_V1 (BIT_MASK_RARF_RC8_V1 << BIT_SHIFT_RARF_RC8_V1)\n#define BIT_CLEAR_RARF_RC8_V1(x) ((x) & (~BITS_RARF_RC8_V1))\n#define BIT_GET_RARF_RC8_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RARF_RC8_V1) & BIT_MASK_RARF_RC8_V1)\n#define BIT_SET_RARF_RC8_V1(x, v)                                              \\\n\t(BIT_CLEAR_RARF_RC8_V1(x) | BIT_RARF_RC8_V1(v))\n\n#define BIT_SHIFT_RARF_RC7_V1 16\n#define BIT_MASK_RARF_RC7_V1 0x1f\n#define BIT_RARF_RC7_V1(x)                                                     \\\n\t(((x) & BIT_MASK_RARF_RC7_V1) << BIT_SHIFT_RARF_RC7_V1)\n#define BITS_RARF_RC7_V1 (BIT_MASK_RARF_RC7_V1 << BIT_SHIFT_RARF_RC7_V1)\n#define BIT_CLEAR_RARF_RC7_V1(x) ((x) & (~BITS_RARF_RC7_V1))\n#define BIT_GET_RARF_RC7_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RARF_RC7_V1) & BIT_MASK_RARF_RC7_V1)\n#define BIT_SET_RARF_RC7_V1(x, v)                                              \\\n\t(BIT_CLEAR_RARF_RC7_V1(x) | BIT_RARF_RC7_V1(v))\n\n#define BIT_SHIFT_RARF_RC6_V1 8\n#define BIT_MASK_RARF_RC6_V1 0x1f\n#define BIT_RARF_RC6_V1(x)                                                     \\\n\t(((x) & BIT_MASK_RARF_RC6_V1) << BIT_SHIFT_RARF_RC6_V1)\n#define BITS_RARF_RC6_V1 (BIT_MASK_RARF_RC6_V1 << BIT_SHIFT_RARF_RC6_V1)\n#define BIT_CLEAR_RARF_RC6_V1(x) ((x) & (~BITS_RARF_RC6_V1))\n#define BIT_GET_RARF_RC6_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RARF_RC6_V1) & BIT_MASK_RARF_RC6_V1)\n#define BIT_SET_RARF_RC6_V1(x, v)                                              \\\n\t(BIT_CLEAR_RARF_RC6_V1(x) | BIT_RARF_RC6_V1(v))\n\n#define BIT_SHIFT_RARF_RC5_V1 0\n#define BIT_MASK_RARF_RC5_V1 0x1f\n#define BIT_RARF_RC5_V1(x)                                                     \\\n\t(((x) & BIT_MASK_RARF_RC5_V1) << BIT_SHIFT_RARF_RC5_V1)\n#define BITS_RARF_RC5_V1 (BIT_MASK_RARF_RC5_V1 << BIT_SHIFT_RARF_RC5_V1)\n#define BIT_CLEAR_RARF_RC5_V1(x) ((x) & (~BITS_RARF_RC5_V1))\n#define BIT_GET_RARF_RC5_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RARF_RC5_V1) & BIT_MASK_RARF_RC5_V1)\n#define BIT_SET_RARF_RC5_V1(x, v)                                              \\\n\t(BIT_CLEAR_RARF_RC5_V1(x) | BIT_RARF_RC5_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RRSR\t\t\t\t(Offset 0x0440) */\n\n#define BIT_EN_VHTBW_FALL BIT(31)\n#define BIT_EN_HTBW_FALL BIT(30)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RRSR\t\t\t\t(Offset 0x0440) */\n\n#define BIT_SHIFT_RRSR_RSC 21\n#define BIT_MASK_RRSR_RSC 0x3\n#define BIT_RRSR_RSC(x) (((x) & BIT_MASK_RRSR_RSC) << BIT_SHIFT_RRSR_RSC)\n#define BITS_RRSR_RSC (BIT_MASK_RRSR_RSC << BIT_SHIFT_RRSR_RSC)\n#define BIT_CLEAR_RRSR_RSC(x) ((x) & (~BITS_RRSR_RSC))\n#define BIT_GET_RRSR_RSC(x) (((x) >> BIT_SHIFT_RRSR_RSC) & BIT_MASK_RRSR_RSC)\n#define BIT_SET_RRSR_RSC(x, v) (BIT_CLEAR_RRSR_RSC(x) | BIT_RRSR_RSC(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RRSR\t\t\t\t(Offset 0x0440) */\n\n#define BIT_RRSR_BW BIT(20)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RRSR\t\t\t\t(Offset 0x0440) */\n\n#define BIT_SHIFT_RRSC_BITMAP 0\n#define BIT_MASK_RRSC_BITMAP 0xfffff\n#define BIT_RRSC_BITMAP(x)                                                     \\\n\t(((x) & BIT_MASK_RRSC_BITMAP) << BIT_SHIFT_RRSC_BITMAP)\n#define BITS_RRSC_BITMAP (BIT_MASK_RRSC_BITMAP << BIT_SHIFT_RRSC_BITMAP)\n#define BIT_CLEAR_RRSC_BITMAP(x) ((x) & (~BITS_RRSC_BITMAP))\n#define BIT_GET_RRSC_BITMAP(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RRSC_BITMAP) & BIT_MASK_RRSC_BITMAP)\n#define BIT_SET_RRSC_BITMAP(x, v)                                              \\\n\t(BIT_CLEAR_RRSC_BITMAP(x) | BIT_RRSC_BITMAP(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RRSR_H\t\t\t\t(Offset 0x0443) */\n\n#define BIT_EN_VHTBW_FALL_V1 BIT(7)\n#define BIT_EN_HTBW_FALL_V1 BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ARFR0\t\t\t\t(Offset 0x0444) */\n\n#define BIT_SHIFT_ARFR0_V1 0\n#define BIT_MASK_ARFR0_V1 0xffffffffffffffffL\n#define BIT_ARFR0_V1(x) (((x) & BIT_MASK_ARFR0_V1) << BIT_SHIFT_ARFR0_V1)\n#define BITS_ARFR0_V1 (BIT_MASK_ARFR0_V1 << BIT_SHIFT_ARFR0_V1)\n#define BIT_CLEAR_ARFR0_V1(x) ((x) & (~BITS_ARFR0_V1))\n#define BIT_GET_ARFR0_V1(x) (((x) >> BIT_SHIFT_ARFR0_V1) & BIT_MASK_ARFR0_V1)\n#define BIT_SET_ARFR0_V1(x, v) (BIT_CLEAR_ARFR0_V1(x) | BIT_ARFR0_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ARFR0\t\t\t\t(Offset 0x0444) */\n\n#define BIT_SHIFT_ARFRL0 0\n#define BIT_MASK_ARFRL0 0xffffffffL\n#define BIT_ARFRL0(x) (((x) & BIT_MASK_ARFRL0) << BIT_SHIFT_ARFRL0)\n#define BITS_ARFRL0 (BIT_MASK_ARFRL0 << BIT_SHIFT_ARFRL0)\n#define BIT_CLEAR_ARFRL0(x) ((x) & (~BITS_ARFRL0))\n#define BIT_GET_ARFRL0(x) (((x) >> BIT_SHIFT_ARFRL0) & BIT_MASK_ARFRL0)\n#define BIT_SET_ARFRL0(x, v) (BIT_CLEAR_ARFRL0(x) | BIT_ARFRL0(v))\n\n/* 2 REG_ARFRH0\t\t\t\t(Offset 0x0448) */\n\n#define BIT_SHIFT_ARFRH0 0\n#define BIT_MASK_ARFRH0 0xffffffffL\n#define BIT_ARFRH0(x) (((x) & BIT_MASK_ARFRH0) << BIT_SHIFT_ARFRH0)\n#define BITS_ARFRH0 (BIT_MASK_ARFRH0 << BIT_SHIFT_ARFRH0)\n#define BIT_CLEAR_ARFRH0(x) ((x) & (~BITS_ARFRH0))\n#define BIT_GET_ARFRH0(x) (((x) >> BIT_SHIFT_ARFRH0) & BIT_MASK_ARFRH0)\n#define BIT_SET_ARFRH0(x, v) (BIT_CLEAR_ARFRH0(x) | BIT_ARFRH0(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_REG_ARFR_WT0\t\t\t(Offset 0x044C) */\n\n#define BIT_SHIFT_RATE7_WEIGHTING 28\n#define BIT_MASK_RATE7_WEIGHTING 0xf\n#define BIT_RATE7_WEIGHTING(x)                                                 \\\n\t(((x) & BIT_MASK_RATE7_WEIGHTING) << BIT_SHIFT_RATE7_WEIGHTING)\n#define BITS_RATE7_WEIGHTING                                                   \\\n\t(BIT_MASK_RATE7_WEIGHTING << BIT_SHIFT_RATE7_WEIGHTING)\n#define BIT_CLEAR_RATE7_WEIGHTING(x) ((x) & (~BITS_RATE7_WEIGHTING))\n#define BIT_GET_RATE7_WEIGHTING(x)                                             \\\n\t(((x) >> BIT_SHIFT_RATE7_WEIGHTING) & BIT_MASK_RATE7_WEIGHTING)\n#define BIT_SET_RATE7_WEIGHTING(x, v)                                          \\\n\t(BIT_CLEAR_RATE7_WEIGHTING(x) | BIT_RATE7_WEIGHTING(v))\n\n#define BIT_SHIFT_RATE6_WEIGHTING 24\n#define BIT_MASK_RATE6_WEIGHTING 0xf\n#define BIT_RATE6_WEIGHTING(x)                                                 \\\n\t(((x) & BIT_MASK_RATE6_WEIGHTING) << BIT_SHIFT_RATE6_WEIGHTING)\n#define BITS_RATE6_WEIGHTING                                                   \\\n\t(BIT_MASK_RATE6_WEIGHTING << BIT_SHIFT_RATE6_WEIGHTING)\n#define BIT_CLEAR_RATE6_WEIGHTING(x) ((x) & (~BITS_RATE6_WEIGHTING))\n#define BIT_GET_RATE6_WEIGHTING(x)                                             \\\n\t(((x) >> BIT_SHIFT_RATE6_WEIGHTING) & BIT_MASK_RATE6_WEIGHTING)\n#define BIT_SET_RATE6_WEIGHTING(x, v)                                          \\\n\t(BIT_CLEAR_RATE6_WEIGHTING(x) | BIT_RATE6_WEIGHTING(v))\n\n#define BIT_SHIFT_RATE5_WEIGHTING 20\n#define BIT_MASK_RATE5_WEIGHTING 0xf\n#define BIT_RATE5_WEIGHTING(x)                                                 \\\n\t(((x) & BIT_MASK_RATE5_WEIGHTING) << BIT_SHIFT_RATE5_WEIGHTING)\n#define BITS_RATE5_WEIGHTING                                                   \\\n\t(BIT_MASK_RATE5_WEIGHTING << BIT_SHIFT_RATE5_WEIGHTING)\n#define BIT_CLEAR_RATE5_WEIGHTING(x) ((x) & (~BITS_RATE5_WEIGHTING))\n#define BIT_GET_RATE5_WEIGHTING(x)                                             \\\n\t(((x) >> BIT_SHIFT_RATE5_WEIGHTING) & BIT_MASK_RATE5_WEIGHTING)\n#define BIT_SET_RATE5_WEIGHTING(x, v)                                          \\\n\t(BIT_CLEAR_RATE5_WEIGHTING(x) | BIT_RATE5_WEIGHTING(v))\n\n#define BIT_SHIFT_RATE4_WEIGHTING 16\n#define BIT_MASK_RATE4_WEIGHTING 0xf\n#define BIT_RATE4_WEIGHTING(x)                                                 \\\n\t(((x) & BIT_MASK_RATE4_WEIGHTING) << BIT_SHIFT_RATE4_WEIGHTING)\n#define BITS_RATE4_WEIGHTING                                                   \\\n\t(BIT_MASK_RATE4_WEIGHTING << BIT_SHIFT_RATE4_WEIGHTING)\n#define BIT_CLEAR_RATE4_WEIGHTING(x) ((x) & (~BITS_RATE4_WEIGHTING))\n#define BIT_GET_RATE4_WEIGHTING(x)                                             \\\n\t(((x) >> BIT_SHIFT_RATE4_WEIGHTING) & BIT_MASK_RATE4_WEIGHTING)\n#define BIT_SET_RATE4_WEIGHTING(x, v)                                          \\\n\t(BIT_CLEAR_RATE4_WEIGHTING(x) | BIT_RATE4_WEIGHTING(v))\n\n#define BIT_SHIFT_RATE3_WEIGHTING 12\n#define BIT_MASK_RATE3_WEIGHTING 0xf\n#define BIT_RATE3_WEIGHTING(x)                                                 \\\n\t(((x) & BIT_MASK_RATE3_WEIGHTING) << BIT_SHIFT_RATE3_WEIGHTING)\n#define BITS_RATE3_WEIGHTING                                                   \\\n\t(BIT_MASK_RATE3_WEIGHTING << BIT_SHIFT_RATE3_WEIGHTING)\n#define BIT_CLEAR_RATE3_WEIGHTING(x) ((x) & (~BITS_RATE3_WEIGHTING))\n#define BIT_GET_RATE3_WEIGHTING(x)                                             \\\n\t(((x) >> BIT_SHIFT_RATE3_WEIGHTING) & BIT_MASK_RATE3_WEIGHTING)\n#define BIT_SET_RATE3_WEIGHTING(x, v)                                          \\\n\t(BIT_CLEAR_RATE3_WEIGHTING(x) | BIT_RATE3_WEIGHTING(v))\n\n#define BIT_SHIFT_RATE2_WEIGHTING 8\n#define BIT_MASK_RATE2_WEIGHTING 0xf\n#define BIT_RATE2_WEIGHTING(x)                                                 \\\n\t(((x) & BIT_MASK_RATE2_WEIGHTING) << BIT_SHIFT_RATE2_WEIGHTING)\n#define BITS_RATE2_WEIGHTING                                                   \\\n\t(BIT_MASK_RATE2_WEIGHTING << BIT_SHIFT_RATE2_WEIGHTING)\n#define BIT_CLEAR_RATE2_WEIGHTING(x) ((x) & (~BITS_RATE2_WEIGHTING))\n#define BIT_GET_RATE2_WEIGHTING(x)                                             \\\n\t(((x) >> BIT_SHIFT_RATE2_WEIGHTING) & BIT_MASK_RATE2_WEIGHTING)\n#define BIT_SET_RATE2_WEIGHTING(x, v)                                          \\\n\t(BIT_CLEAR_RATE2_WEIGHTING(x) | BIT_RATE2_WEIGHTING(v))\n\n#define BIT_SHIFT_RATE1_WEIGHTING 4\n#define BIT_MASK_RATE1_WEIGHTING 0xf\n#define BIT_RATE1_WEIGHTING(x)                                                 \\\n\t(((x) & BIT_MASK_RATE1_WEIGHTING) << BIT_SHIFT_RATE1_WEIGHTING)\n#define BITS_RATE1_WEIGHTING                                                   \\\n\t(BIT_MASK_RATE1_WEIGHTING << BIT_SHIFT_RATE1_WEIGHTING)\n#define BIT_CLEAR_RATE1_WEIGHTING(x) ((x) & (~BITS_RATE1_WEIGHTING))\n#define BIT_GET_RATE1_WEIGHTING(x)                                             \\\n\t(((x) >> BIT_SHIFT_RATE1_WEIGHTING) & BIT_MASK_RATE1_WEIGHTING)\n#define BIT_SET_RATE1_WEIGHTING(x, v)                                          \\\n\t(BIT_CLEAR_RATE1_WEIGHTING(x) | BIT_RATE1_WEIGHTING(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ARFR1_V1\t\t\t\t(Offset 0x044C) */\n\n#define BIT_SHIFT_ARFR1_V1 0\n#define BIT_MASK_ARFR1_V1 0xffffffffffffffffL\n#define BIT_ARFR1_V1(x) (((x) & BIT_MASK_ARFR1_V1) << BIT_SHIFT_ARFR1_V1)\n#define BITS_ARFR1_V1 (BIT_MASK_ARFR1_V1 << BIT_SHIFT_ARFR1_V1)\n#define BIT_CLEAR_ARFR1_V1(x) ((x) & (~BITS_ARFR1_V1))\n#define BIT_GET_ARFR1_V1(x) (((x) >> BIT_SHIFT_ARFR1_V1) & BIT_MASK_ARFR1_V1)\n#define BIT_SET_ARFR1_V1(x, v) (BIT_CLEAR_ARFR1_V1(x) | BIT_ARFR1_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ARFR1_V1\t\t\t\t(Offset 0x044C) */\n\n#define BIT_SHIFT_ARFRL1 0\n#define BIT_MASK_ARFRL1 0xffffffffL\n#define BIT_ARFRL1(x) (((x) & BIT_MASK_ARFRL1) << BIT_SHIFT_ARFRL1)\n#define BITS_ARFRL1 (BIT_MASK_ARFRL1 << BIT_SHIFT_ARFRL1)\n#define BIT_CLEAR_ARFRL1(x) ((x) & (~BITS_ARFRL1))\n#define BIT_GET_ARFRL1(x) (((x) >> BIT_SHIFT_ARFRL1) & BIT_MASK_ARFRL1)\n#define BIT_SET_ARFRL1(x, v) (BIT_CLEAR_ARFRL1(x) | BIT_ARFRL1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_REG_ARFR_WT0\t\t\t(Offset 0x044C) */\n\n#define BIT_SHIFT_RATE0_WEIGHTING 0\n#define BIT_MASK_RATE0_WEIGHTING 0xf\n#define BIT_RATE0_WEIGHTING(x)                                                 \\\n\t(((x) & BIT_MASK_RATE0_WEIGHTING) << BIT_SHIFT_RATE0_WEIGHTING)\n#define BITS_RATE0_WEIGHTING                                                   \\\n\t(BIT_MASK_RATE0_WEIGHTING << BIT_SHIFT_RATE0_WEIGHTING)\n#define BIT_CLEAR_RATE0_WEIGHTING(x) ((x) & (~BITS_RATE0_WEIGHTING))\n#define BIT_GET_RATE0_WEIGHTING(x)                                             \\\n\t(((x) >> BIT_SHIFT_RATE0_WEIGHTING) & BIT_MASK_RATE0_WEIGHTING)\n#define BIT_SET_RATE0_WEIGHTING(x, v)                                          \\\n\t(BIT_CLEAR_RATE0_WEIGHTING(x) | BIT_RATE0_WEIGHTING(v))\n\n/* 2 REG_REG_ARFR_WT1\t\t\t(Offset 0x0450) */\n\n#define BIT_SHIFT_RATE15_WEIGHTING 28\n#define BIT_MASK_RATE15_WEIGHTING 0xf\n#define BIT_RATE15_WEIGHTING(x)                                                \\\n\t(((x) & BIT_MASK_RATE15_WEIGHTING) << BIT_SHIFT_RATE15_WEIGHTING)\n#define BITS_RATE15_WEIGHTING                                                  \\\n\t(BIT_MASK_RATE15_WEIGHTING << BIT_SHIFT_RATE15_WEIGHTING)\n#define BIT_CLEAR_RATE15_WEIGHTING(x) ((x) & (~BITS_RATE15_WEIGHTING))\n#define BIT_GET_RATE15_WEIGHTING(x)                                            \\\n\t(((x) >> BIT_SHIFT_RATE15_WEIGHTING) & BIT_MASK_RATE15_WEIGHTING)\n#define BIT_SET_RATE15_WEIGHTING(x, v)                                         \\\n\t(BIT_CLEAR_RATE15_WEIGHTING(x) | BIT_RATE15_WEIGHTING(v))\n\n#define BIT_SHIFT_RATE14_WEIGHTING 24\n#define BIT_MASK_RATE14_WEIGHTING 0xf\n#define BIT_RATE14_WEIGHTING(x)                                                \\\n\t(((x) & BIT_MASK_RATE14_WEIGHTING) << BIT_SHIFT_RATE14_WEIGHTING)\n#define BITS_RATE14_WEIGHTING                                                  \\\n\t(BIT_MASK_RATE14_WEIGHTING << BIT_SHIFT_RATE14_WEIGHTING)\n#define BIT_CLEAR_RATE14_WEIGHTING(x) ((x) & (~BITS_RATE14_WEIGHTING))\n#define BIT_GET_RATE14_WEIGHTING(x)                                            \\\n\t(((x) >> BIT_SHIFT_RATE14_WEIGHTING) & BIT_MASK_RATE14_WEIGHTING)\n#define BIT_SET_RATE14_WEIGHTING(x, v)                                         \\\n\t(BIT_CLEAR_RATE14_WEIGHTING(x) | BIT_RATE14_WEIGHTING(v))\n\n#define BIT_SHIFT_RATE13_WEIGHTING 20\n#define BIT_MASK_RATE13_WEIGHTING 0xf\n#define BIT_RATE13_WEIGHTING(x)                                                \\\n\t(((x) & BIT_MASK_RATE13_WEIGHTING) << BIT_SHIFT_RATE13_WEIGHTING)\n#define BITS_RATE13_WEIGHTING                                                  \\\n\t(BIT_MASK_RATE13_WEIGHTING << BIT_SHIFT_RATE13_WEIGHTING)\n#define BIT_CLEAR_RATE13_WEIGHTING(x) ((x) & (~BITS_RATE13_WEIGHTING))\n#define BIT_GET_RATE13_WEIGHTING(x)                                            \\\n\t(((x) >> BIT_SHIFT_RATE13_WEIGHTING) & BIT_MASK_RATE13_WEIGHTING)\n#define BIT_SET_RATE13_WEIGHTING(x, v)                                         \\\n\t(BIT_CLEAR_RATE13_WEIGHTING(x) | BIT_RATE13_WEIGHTING(v))\n\n#define BIT_SHIFT_RATE12_WEIGHTING 16\n#define BIT_MASK_RATE12_WEIGHTING 0xf\n#define BIT_RATE12_WEIGHTING(x)                                                \\\n\t(((x) & BIT_MASK_RATE12_WEIGHTING) << BIT_SHIFT_RATE12_WEIGHTING)\n#define BITS_RATE12_WEIGHTING                                                  \\\n\t(BIT_MASK_RATE12_WEIGHTING << BIT_SHIFT_RATE12_WEIGHTING)\n#define BIT_CLEAR_RATE12_WEIGHTING(x) ((x) & (~BITS_RATE12_WEIGHTING))\n#define BIT_GET_RATE12_WEIGHTING(x)                                            \\\n\t(((x) >> BIT_SHIFT_RATE12_WEIGHTING) & BIT_MASK_RATE12_WEIGHTING)\n#define BIT_SET_RATE12_WEIGHTING(x, v)                                         \\\n\t(BIT_CLEAR_RATE12_WEIGHTING(x) | BIT_RATE12_WEIGHTING(v))\n\n#define BIT_SHIFT_RATE11_WEIGHTING 12\n#define BIT_MASK_RATE11_WEIGHTING 0xf\n#define BIT_RATE11_WEIGHTING(x)                                                \\\n\t(((x) & BIT_MASK_RATE11_WEIGHTING) << BIT_SHIFT_RATE11_WEIGHTING)\n#define BITS_RATE11_WEIGHTING                                                  \\\n\t(BIT_MASK_RATE11_WEIGHTING << BIT_SHIFT_RATE11_WEIGHTING)\n#define BIT_CLEAR_RATE11_WEIGHTING(x) ((x) & (~BITS_RATE11_WEIGHTING))\n#define BIT_GET_RATE11_WEIGHTING(x)                                            \\\n\t(((x) >> BIT_SHIFT_RATE11_WEIGHTING) & BIT_MASK_RATE11_WEIGHTING)\n#define BIT_SET_RATE11_WEIGHTING(x, v)                                         \\\n\t(BIT_CLEAR_RATE11_WEIGHTING(x) | BIT_RATE11_WEIGHTING(v))\n\n#define BIT_SHIFT_RATE10_WEIGHTING 8\n#define BIT_MASK_RATE10_WEIGHTING 0xf\n#define BIT_RATE10_WEIGHTING(x)                                                \\\n\t(((x) & BIT_MASK_RATE10_WEIGHTING) << BIT_SHIFT_RATE10_WEIGHTING)\n#define BITS_RATE10_WEIGHTING                                                  \\\n\t(BIT_MASK_RATE10_WEIGHTING << BIT_SHIFT_RATE10_WEIGHTING)\n#define BIT_CLEAR_RATE10_WEIGHTING(x) ((x) & (~BITS_RATE10_WEIGHTING))\n#define BIT_GET_RATE10_WEIGHTING(x)                                            \\\n\t(((x) >> BIT_SHIFT_RATE10_WEIGHTING) & BIT_MASK_RATE10_WEIGHTING)\n#define BIT_SET_RATE10_WEIGHTING(x, v)                                         \\\n\t(BIT_CLEAR_RATE10_WEIGHTING(x) | BIT_RATE10_WEIGHTING(v))\n\n#define BIT_SHIFT_RATE9_WEIGHTING 4\n#define BIT_MASK_RATE9_WEIGHTING 0xf\n#define BIT_RATE9_WEIGHTING(x)                                                 \\\n\t(((x) & BIT_MASK_RATE9_WEIGHTING) << BIT_SHIFT_RATE9_WEIGHTING)\n#define BITS_RATE9_WEIGHTING                                                   \\\n\t(BIT_MASK_RATE9_WEIGHTING << BIT_SHIFT_RATE9_WEIGHTING)\n#define BIT_CLEAR_RATE9_WEIGHTING(x) ((x) & (~BITS_RATE9_WEIGHTING))\n#define BIT_GET_RATE9_WEIGHTING(x)                                             \\\n\t(((x) >> BIT_SHIFT_RATE9_WEIGHTING) & BIT_MASK_RATE9_WEIGHTING)\n#define BIT_SET_RATE9_WEIGHTING(x, v)                                          \\\n\t(BIT_CLEAR_RATE9_WEIGHTING(x) | BIT_RATE9_WEIGHTING(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ARFRH1\t\t\t\t(Offset 0x0450) */\n\n#define BIT_SHIFT_ARFRH1 0\n#define BIT_MASK_ARFRH1 0xffffffffL\n#define BIT_ARFRH1(x) (((x) & BIT_MASK_ARFRH1) << BIT_SHIFT_ARFRH1)\n#define BITS_ARFRH1 (BIT_MASK_ARFRH1 << BIT_SHIFT_ARFRH1)\n#define BIT_CLEAR_ARFRH1(x) ((x) & (~BITS_ARFRH1))\n#define BIT_GET_ARFRH1(x) (((x) >> BIT_SHIFT_ARFRH1) & BIT_MASK_ARFRH1)\n#define BIT_SET_ARFRH1(x, v) (BIT_CLEAR_ARFRH1(x) | BIT_ARFRH1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_REG_ARFR_WT1\t\t\t(Offset 0x0450) */\n\n#define BIT_SHIFT_RATE8_WEIGHTING 0\n#define BIT_MASK_RATE8_WEIGHTING 0xf\n#define BIT_RATE8_WEIGHTING(x)                                                 \\\n\t(((x) & BIT_MASK_RATE8_WEIGHTING) << BIT_SHIFT_RATE8_WEIGHTING)\n#define BITS_RATE8_WEIGHTING                                                   \\\n\t(BIT_MASK_RATE8_WEIGHTING << BIT_SHIFT_RATE8_WEIGHTING)\n#define BIT_CLEAR_RATE8_WEIGHTING(x) ((x) & (~BITS_RATE8_WEIGHTING))\n#define BIT_GET_RATE8_WEIGHTING(x)                                             \\\n\t(((x) >> BIT_SHIFT_RATE8_WEIGHTING) & BIT_MASK_RATE8_WEIGHTING)\n#define BIT_SET_RATE8_WEIGHTING(x, v)                                          \\\n\t(BIT_CLEAR_RATE8_WEIGHTING(x) | BIT_RATE8_WEIGHTING(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CCK_CHECK\t\t\t\t(Offset 0x0454) */\n\n#define BIT_CHECK_CCK_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CCK_CHECK\t\t\t\t(Offset 0x0454) */\n\n#define BIT_EN_BCN_PKT_REL BIT(6)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CCK_CHECK\t\t\t\t(Offset 0x0454) */\n\n#define BIT_EN_BCN_PKT_REL_P0 BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CCK_CHECK\t\t\t\t(Offset 0x0454) */\n\n#define BIT_BCN_PORT_SEL BIT(5)\n#define BIT_MOREDATA_BYPASS BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CCK_CHECK\t\t\t\t(Offset 0x0454) */\n\n#define BIT_EN_CLR_CMD_REL_BCN_PKT BIT(3)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CCK_CHECK\t\t\t\t(Offset 0x0454) */\n\n#define BIT_EN_CLR_CMD_REL_BCN_PKT_P0 BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CCK_CHECK\t\t\t\t(Offset 0x0454) */\n\n#define BIT_EN_SET_MOREDATA BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CCK_CHECK\t\t\t\t(Offset 0x0454) */\n\n#define BIT_R_EN_SET_MOREDATA BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CCK_CHECK\t\t\t\t(Offset 0x0454) */\n\n#define BIT__R_DIS_CLEAR_MACID_RELEASE BIT(1)\n#define BIT__R_MACID_RELEASE_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AMPDU_MAX_TIME_V1\t\t\t(Offset 0x0455) */\n\n#define BIT_SHIFT_AMPDU_MAX_TIME 0\n#define BIT_MASK_AMPDU_MAX_TIME 0xff\n#define BIT_AMPDU_MAX_TIME(x)                                                  \\\n\t(((x) & BIT_MASK_AMPDU_MAX_TIME) << BIT_SHIFT_AMPDU_MAX_TIME)\n#define BITS_AMPDU_MAX_TIME                                                    \\\n\t(BIT_MASK_AMPDU_MAX_TIME << BIT_SHIFT_AMPDU_MAX_TIME)\n#define BIT_CLEAR_AMPDU_MAX_TIME(x) ((x) & (~BITS_AMPDU_MAX_TIME))\n#define BIT_GET_AMPDU_MAX_TIME(x)                                              \\\n\t(((x) >> BIT_SHIFT_AMPDU_MAX_TIME) & BIT_MASK_AMPDU_MAX_TIME)\n#define BIT_SET_AMPDU_MAX_TIME(x, v)                                           \\\n\t(BIT_CLEAR_AMPDU_MAX_TIME(x) | BIT_AMPDU_MAX_TIME(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AMPDU_BURST_CTRL\t\t\t(Offset 0x0455) */\n\n#define BIT_AMPDU_BURST_GLOBAL_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_BCNQ2_HEAD\t\t\t\t(Offset 0x0455) */\n\n#define BIT_SHIFT_BCNQ2_HEAD 0\n#define BIT_MASK_BCNQ2_HEAD 0xff\n#define BIT_BCNQ2_HEAD(x) (((x) & BIT_MASK_BCNQ2_HEAD) << BIT_SHIFT_BCNQ2_HEAD)\n#define BITS_BCNQ2_HEAD (BIT_MASK_BCNQ2_HEAD << BIT_SHIFT_BCNQ2_HEAD)\n#define BIT_CLEAR_BCNQ2_HEAD(x) ((x) & (~BITS_BCNQ2_HEAD))\n#define BIT_GET_BCNQ2_HEAD(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BCNQ2_HEAD) & BIT_MASK_BCNQ2_HEAD)\n#define BIT_SET_BCNQ2_HEAD(x, v) (BIT_CLEAR_BCNQ2_HEAD(x) | BIT_BCNQ2_HEAD(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCNQ1_BDNY_V1\t\t\t(Offset 0x0456) */\n\n#define BIT_SHIFT_BCNQ1_PGBNDY_V1 0\n#define BIT_MASK_BCNQ1_PGBNDY_V1 0xfff\n#define BIT_BCNQ1_PGBNDY_V1(x)                                                 \\\n\t(((x) & BIT_MASK_BCNQ1_PGBNDY_V1) << BIT_SHIFT_BCNQ1_PGBNDY_V1)\n#define BITS_BCNQ1_PGBNDY_V1                                                   \\\n\t(BIT_MASK_BCNQ1_PGBNDY_V1 << BIT_SHIFT_BCNQ1_PGBNDY_V1)\n#define BIT_CLEAR_BCNQ1_PGBNDY_V1(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1))\n#define BIT_GET_BCNQ1_PGBNDY_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1) & BIT_MASK_BCNQ1_PGBNDY_V1)\n#define BIT_SET_BCNQ1_PGBNDY_V1(x, v)                                          \\\n\t(BIT_CLEAR_BCNQ1_PGBNDY_V1(x) | BIT_BCNQ1_PGBNDY_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TAB_SEL\t\t\t\t(Offset 0x0456) */\n\n#define BIT_SHIFT_RATE_SEL 0\n#define BIT_MASK_RATE_SEL 0xf\n#define BIT_RATE_SEL(x) (((x) & BIT_MASK_RATE_SEL) << BIT_SHIFT_RATE_SEL)\n#define BITS_RATE_SEL (BIT_MASK_RATE_SEL << BIT_SHIFT_RATE_SEL)\n#define BIT_CLEAR_RATE_SEL(x) ((x) & (~BITS_RATE_SEL))\n#define BIT_GET_RATE_SEL(x) (((x) >> BIT_SHIFT_RATE_SEL) & BIT_MASK_RATE_SEL)\n#define BIT_SET_RATE_SEL(x, v) (BIT_CLEAR_RATE_SEL(x) | BIT_RATE_SEL(v))\n\n/* 2 REG_BCN_INVALID_CTRL\t\t\t(Offset 0x0457) */\n\n#define BIT_EN_CLR_CMD_REL_BCN_PKT_P4 BIT(7)\n#define BIT_EN_BCN_PKT_REL_P4 BIT(6)\n#define BIT_EN_CLR_CMD_REL_BCN_PKT_P3 BIT(5)\n#define BIT_EN_BCN_PKT_REL_P3 BIT(4)\n#define BIT_EN_CLR_CMD_REL_BCN_PKT_P2 BIT(3)\n#define BIT_EN_BCN_PKT_REL_P2 BIT(2)\n#define BIT_EN_CLR_CMD_REL_BCN_PKT_P1 BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BCNQ1_BDNY\t\t\t\t(Offset 0x0457) */\n\n#define BIT_SHIFT_BCNQ1_PGBNDY 0\n#define BIT_MASK_BCNQ1_PGBNDY 0xff\n#define BIT_BCNQ1_PGBNDY(x)                                                    \\\n\t(((x) & BIT_MASK_BCNQ1_PGBNDY) << BIT_SHIFT_BCNQ1_PGBNDY)\n#define BITS_BCNQ1_PGBNDY (BIT_MASK_BCNQ1_PGBNDY << BIT_SHIFT_BCNQ1_PGBNDY)\n#define BIT_CLEAR_BCNQ1_PGBNDY(x) ((x) & (~BITS_BCNQ1_PGBNDY))\n#define BIT_GET_BCNQ1_PGBNDY(x)                                                \\\n\t(((x) >> BIT_SHIFT_BCNQ1_PGBNDY) & BIT_MASK_BCNQ1_PGBNDY)\n#define BIT_SET_BCNQ1_PGBNDY(x, v)                                             \\\n\t(BIT_CLEAR_BCNQ1_PGBNDY(x) | BIT_BCNQ1_PGBNDY(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_BCNQ1_BDNY\t\t\t\t(Offset 0x0457) */\n\n#define BIT_SHIFT_BCNQ1_HEAD 0\n#define BIT_MASK_BCNQ1_HEAD 0xff\n#define BIT_BCNQ1_HEAD(x) (((x) & BIT_MASK_BCNQ1_HEAD) << BIT_SHIFT_BCNQ1_HEAD)\n#define BITS_BCNQ1_HEAD (BIT_MASK_BCNQ1_HEAD << BIT_SHIFT_BCNQ1_HEAD)\n#define BIT_CLEAR_BCNQ1_HEAD(x) ((x) & (~BITS_BCNQ1_HEAD))\n#define BIT_GET_BCNQ1_HEAD(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BCNQ1_HEAD) & BIT_MASK_BCNQ1_HEAD)\n#define BIT_SET_BCNQ1_HEAD(x, v) (BIT_CLEAR_BCNQ1_HEAD(x) | BIT_BCNQ1_HEAD(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_BCN_INVALID_CTRL\t\t\t(Offset 0x0457) */\n\n#define BIT_EN_BCN_PKT_REL_P1 BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AMPDU_MAX_LENGTH\t\t\t(Offset 0x0458) */\n\n#define BIT_SHIFT_AMPDU_MAX_LENGTH 0\n#define BIT_MASK_AMPDU_MAX_LENGTH 0xffffffffL\n#define BIT_AMPDU_MAX_LENGTH(x)                                                \\\n\t(((x) & BIT_MASK_AMPDU_MAX_LENGTH) << BIT_SHIFT_AMPDU_MAX_LENGTH)\n#define BITS_AMPDU_MAX_LENGTH                                                  \\\n\t(BIT_MASK_AMPDU_MAX_LENGTH << BIT_SHIFT_AMPDU_MAX_LENGTH)\n#define BIT_CLEAR_AMPDU_MAX_LENGTH(x) ((x) & (~BITS_AMPDU_MAX_LENGTH))\n#define BIT_GET_AMPDU_MAX_LENGTH(x)                                            \\\n\t(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH) & BIT_MASK_AMPDU_MAX_LENGTH)\n#define BIT_SET_AMPDU_MAX_LENGTH(x, v)                                         \\\n\t(BIT_CLEAR_AMPDU_MAX_LENGTH(x) | BIT_AMPDU_MAX_LENGTH(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AMPDU_MAX_LENGTH_HT\t\t\t(Offset 0x0458) */\n\n#define BIT_SHIFT_AMPDU_MAX_LENGTH_HT 0\n#define BIT_MASK_AMPDU_MAX_LENGTH_HT 0xffff\n#define BIT_AMPDU_MAX_LENGTH_HT(x)                                             \\\n\t(((x) & BIT_MASK_AMPDU_MAX_LENGTH_HT) << BIT_SHIFT_AMPDU_MAX_LENGTH_HT)\n#define BITS_AMPDU_MAX_LENGTH_HT                                               \\\n\t(BIT_MASK_AMPDU_MAX_LENGTH_HT << BIT_SHIFT_AMPDU_MAX_LENGTH_HT)\n#define BIT_CLEAR_AMPDU_MAX_LENGTH_HT(x) ((x) & (~BITS_AMPDU_MAX_LENGTH_HT))\n#define BIT_GET_AMPDU_MAX_LENGTH_HT(x)                                         \\\n\t(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_HT) & BIT_MASK_AMPDU_MAX_LENGTH_HT)\n#define BIT_SET_AMPDU_MAX_LENGTH_HT(x, v)                                      \\\n\t(BIT_CLEAR_AMPDU_MAX_LENGTH_HT(x) | BIT_AMPDU_MAX_LENGTH_HT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ACQ_STOP\t\t\t\t(Offset 0x045C) */\n\n#define BIT_AC7Q_STOP BIT(7)\n#define BIT_AC6Q_STOP BIT(6)\n#define BIT_AC5Q_STOP BIT(5)\n#define BIT_AC4Q_STOP BIT(4)\n#define BIT_AC3Q_STOP BIT(3)\n#define BIT_AC2Q_STOP BIT(2)\n#define BIT_AC1Q_STOP BIT(1)\n#define BIT_AC0Q_STOP BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_LBK_BUF_HD\t\t\t(Offset 0x045D) */\n\n#define BIT_SHIFT_WMAC_LBK_BUF_HEAD 0\n#define BIT_MASK_WMAC_LBK_BUF_HEAD 0xff\n#define BIT_WMAC_LBK_BUF_HEAD(x)                                               \\\n\t(((x) & BIT_MASK_WMAC_LBK_BUF_HEAD) << BIT_SHIFT_WMAC_LBK_BUF_HEAD)\n#define BITS_WMAC_LBK_BUF_HEAD                                                 \\\n\t(BIT_MASK_WMAC_LBK_BUF_HEAD << BIT_SHIFT_WMAC_LBK_BUF_HEAD)\n#define BIT_CLEAR_WMAC_LBK_BUF_HEAD(x) ((x) & (~BITS_WMAC_LBK_BUF_HEAD))\n#define BIT_GET_WMAC_LBK_BUF_HEAD(x)                                           \\\n\t(((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD) & BIT_MASK_WMAC_LBK_BUF_HEAD)\n#define BIT_SET_WMAC_LBK_BUF_HEAD(x, v)                                        \\\n\t(BIT_CLEAR_WMAC_LBK_BUF_HEAD(x) | BIT_WMAC_LBK_BUF_HEAD(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_NDPA_RATE\t\t\t\t(Offset 0x045D) */\n\n#define BIT_SHIFT_R_NDPA_RATE_V1 0\n#define BIT_MASK_R_NDPA_RATE_V1 0xff\n#define BIT_R_NDPA_RATE_V1(x)                                                  \\\n\t(((x) & BIT_MASK_R_NDPA_RATE_V1) << BIT_SHIFT_R_NDPA_RATE_V1)\n#define BITS_R_NDPA_RATE_V1                                                    \\\n\t(BIT_MASK_R_NDPA_RATE_V1 << BIT_SHIFT_R_NDPA_RATE_V1)\n#define BIT_CLEAR_R_NDPA_RATE_V1(x) ((x) & (~BITS_R_NDPA_RATE_V1))\n#define BIT_GET_R_NDPA_RATE_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_R_NDPA_RATE_V1) & BIT_MASK_R_NDPA_RATE_V1)\n#define BIT_SET_R_NDPA_RATE_V1(x, v)                                           \\\n\t(BIT_CLEAR_R_NDPA_RATE_V1(x) | BIT_R_NDPA_RATE_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TX_HANG_CTRL\t\t\t(Offset 0x045E) */\n\n#define BIT_EN_GNT_BT_AWAKE BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TX_HANG_CTRL\t\t\t(Offset 0x045E) */\n\n#define BIT_R_EN_GNT_BT_AWAKE BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TX_HANG_CTRL\t\t\t(Offset 0x045E) */\n\n#define BIT_DIS_RELEASE_RETRY BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TX_HANG_CTRL\t\t\t(Offset 0x045E) */\n\n#define BIT_EN_EOF_V1 BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TX_HANG_CTRL\t\t\t(Offset 0x045E) */\n\n#define BIT_DIS_OQT_BLOCK BIT(1)\n#define BIT_SEARCH_QUEUE_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_NDPA_OPT_CTRL\t\t\t(Offset 0x045F) */\n\n#define BIT_R_DIS_MACID_RELEASE_RTY BIT(5)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_NDPA_OPT_CTRL\t\t\t(Offset 0x045F) */\n\n#define BIT_DIS_MACID_RELEASE_RTY BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_NDPA_OPT_CTRL\t\t\t(Offset 0x045F) */\n\n#define BIT_SHIFT_BW_SIGTA 3\n#define BIT_MASK_BW_SIGTA 0x3\n#define BIT_BW_SIGTA(x) (((x) & BIT_MASK_BW_SIGTA) << BIT_SHIFT_BW_SIGTA)\n#define BITS_BW_SIGTA (BIT_MASK_BW_SIGTA << BIT_SHIFT_BW_SIGTA)\n#define BIT_CLEAR_BW_SIGTA(x) ((x) & (~BITS_BW_SIGTA))\n#define BIT_GET_BW_SIGTA(x) (((x) >> BIT_SHIFT_BW_SIGTA) & BIT_MASK_BW_SIGTA)\n#define BIT_SET_BW_SIGTA(x, v) (BIT_CLEAR_BW_SIGTA(x) | BIT_BW_SIGTA(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_NDPA_OPT_CTRL\t\t\t(Offset 0x045F) */\n\n#define BIT_SHIFT_R_NDPA_RATE 2\n#define BIT_MASK_R_NDPA_RATE 0x3f\n#define BIT_R_NDPA_RATE(x)                                                     \\\n\t(((x) & BIT_MASK_R_NDPA_RATE) << BIT_SHIFT_R_NDPA_RATE)\n#define BITS_R_NDPA_RATE (BIT_MASK_R_NDPA_RATE << BIT_SHIFT_R_NDPA_RATE)\n#define BIT_CLEAR_R_NDPA_RATE(x) ((x) & (~BITS_R_NDPA_RATE))\n#define BIT_GET_R_NDPA_RATE(x)                                                 \\\n\t(((x) >> BIT_SHIFT_R_NDPA_RATE) & BIT_MASK_R_NDPA_RATE)\n#define BIT_SET_R_NDPA_RATE(x, v)                                              \\\n\t(BIT_CLEAR_R_NDPA_RATE(x) | BIT_R_NDPA_RATE(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_NDPA_OPT_CTRL\t\t\t(Offset 0x045F) */\n\n#define BIT_EN_BAR_SIGTA BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_NDPA_OPT_CTRL\t\t\t(Offset 0x045F) */\n\n#define BIT_SHIFT_R_NDPA_BW 0\n#define BIT_MASK_R_NDPA_BW 0x3\n#define BIT_R_NDPA_BW(x) (((x) & BIT_MASK_R_NDPA_BW) << BIT_SHIFT_R_NDPA_BW)\n#define BITS_R_NDPA_BW (BIT_MASK_R_NDPA_BW << BIT_SHIFT_R_NDPA_BW)\n#define BIT_CLEAR_R_NDPA_BW(x) ((x) & (~BITS_R_NDPA_BW))\n#define BIT_GET_R_NDPA_BW(x) (((x) >> BIT_SHIFT_R_NDPA_BW) & BIT_MASK_R_NDPA_BW)\n#define BIT_SET_R_NDPA_BW(x, v) (BIT_CLEAR_R_NDPA_BW(x) | BIT_R_NDPA_BW(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_NDPA_OPT_CTRL\t\t\t(Offset 0x045F) */\n\n#define BIT_SHIFT_NDPA_BW 0\n#define BIT_MASK_NDPA_BW 0x3\n#define BIT_NDPA_BW(x) (((x) & BIT_MASK_NDPA_BW) << BIT_SHIFT_NDPA_BW)\n#define BITS_NDPA_BW (BIT_MASK_NDPA_BW << BIT_SHIFT_NDPA_BW)\n#define BIT_CLEAR_NDPA_BW(x) ((x) & (~BITS_NDPA_BW))\n#define BIT_GET_NDPA_BW(x) (((x) >> BIT_SHIFT_NDPA_BW) & BIT_MASK_NDPA_BW)\n#define BIT_SET_NDPA_BW(x, v) (BIT_CLEAR_NDPA_BW(x) | BIT_NDPA_BW(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FAST_EDCA_CTRL\t\t\t(Offset 0x0460) */\n\n#define BIT_SHIFT_FAST_EDCA_TO_V1 16\n#define BIT_MASK_FAST_EDCA_TO_V1 0xff\n#define BIT_FAST_EDCA_TO_V1(x)                                                 \\\n\t(((x) & BIT_MASK_FAST_EDCA_TO_V1) << BIT_SHIFT_FAST_EDCA_TO_V1)\n#define BITS_FAST_EDCA_TO_V1                                                   \\\n\t(BIT_MASK_FAST_EDCA_TO_V1 << BIT_SHIFT_FAST_EDCA_TO_V1)\n#define BIT_CLEAR_FAST_EDCA_TO_V1(x) ((x) & (~BITS_FAST_EDCA_TO_V1))\n#define BIT_GET_FAST_EDCA_TO_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_FAST_EDCA_TO_V1) & BIT_MASK_FAST_EDCA_TO_V1)\n#define BIT_SET_FAST_EDCA_TO_V1(x, v)                                          \\\n\t(BIT_CLEAR_FAST_EDCA_TO_V1(x) | BIT_FAST_EDCA_TO_V1(v))\n\n#define BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH 12\n#define BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH 0xf\n#define BIT_AC3_AC7_FAST_EDCA_PKT_TH(x)                                        \\\n\t(((x) & BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH)                             \\\n\t << BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH)\n#define BITS_AC3_AC7_FAST_EDCA_PKT_TH                                          \\\n\t(BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH                                     \\\n\t << BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH)\n#define BIT_CLEAR_AC3_AC7_FAST_EDCA_PKT_TH(x)                                  \\\n\t((x) & (~BITS_AC3_AC7_FAST_EDCA_PKT_TH))\n#define BIT_GET_AC3_AC7_FAST_EDCA_PKT_TH(x)                                    \\\n\t(((x) >> BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH) &                         \\\n\t BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH)\n#define BIT_SET_AC3_AC7_FAST_EDCA_PKT_TH(x, v)                                 \\\n\t(BIT_CLEAR_AC3_AC7_FAST_EDCA_PKT_TH(x) |                               \\\n\t BIT_AC3_AC7_FAST_EDCA_PKT_TH(v))\n\n#define BIT_SHIFT_AC2_FAST_EDCA_PKT_TH 8\n#define BIT_MASK_AC2_FAST_EDCA_PKT_TH 0xf\n#define BIT_AC2_FAST_EDCA_PKT_TH(x)                                            \\\n\t(((x) & BIT_MASK_AC2_FAST_EDCA_PKT_TH)                                 \\\n\t << BIT_SHIFT_AC2_FAST_EDCA_PKT_TH)\n#define BITS_AC2_FAST_EDCA_PKT_TH                                              \\\n\t(BIT_MASK_AC2_FAST_EDCA_PKT_TH << BIT_SHIFT_AC2_FAST_EDCA_PKT_TH)\n#define BIT_CLEAR_AC2_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC2_FAST_EDCA_PKT_TH))\n#define BIT_GET_AC2_FAST_EDCA_PKT_TH(x)                                        \\\n\t(((x) >> BIT_SHIFT_AC2_FAST_EDCA_PKT_TH) &                             \\\n\t BIT_MASK_AC2_FAST_EDCA_PKT_TH)\n#define BIT_SET_AC2_FAST_EDCA_PKT_TH(x, v)                                     \\\n\t(BIT_CLEAR_AC2_FAST_EDCA_PKT_TH(x) | BIT_AC2_FAST_EDCA_PKT_TH(v))\n\n#define BIT_SHIFT_AC1_FAST_EDCA_PKT_TH 4\n#define BIT_MASK_AC1_FAST_EDCA_PKT_TH 0xf\n#define BIT_AC1_FAST_EDCA_PKT_TH(x)                                            \\\n\t(((x) & BIT_MASK_AC1_FAST_EDCA_PKT_TH)                                 \\\n\t << BIT_SHIFT_AC1_FAST_EDCA_PKT_TH)\n#define BITS_AC1_FAST_EDCA_PKT_TH                                              \\\n\t(BIT_MASK_AC1_FAST_EDCA_PKT_TH << BIT_SHIFT_AC1_FAST_EDCA_PKT_TH)\n#define BIT_CLEAR_AC1_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC1_FAST_EDCA_PKT_TH))\n#define BIT_GET_AC1_FAST_EDCA_PKT_TH(x)                                        \\\n\t(((x) >> BIT_SHIFT_AC1_FAST_EDCA_PKT_TH) &                             \\\n\t BIT_MASK_AC1_FAST_EDCA_PKT_TH)\n#define BIT_SET_AC1_FAST_EDCA_PKT_TH(x, v)                                     \\\n\t(BIT_CLEAR_AC1_FAST_EDCA_PKT_TH(x) | BIT_AC1_FAST_EDCA_PKT_TH(v))\n\n#define BIT_SHIFT_AC0_FAST_EDCA_PKT_TH 0\n#define BIT_MASK_AC0_FAST_EDCA_PKT_TH 0xf\n#define BIT_AC0_FAST_EDCA_PKT_TH(x)                                            \\\n\t(((x) & BIT_MASK_AC0_FAST_EDCA_PKT_TH)                                 \\\n\t << BIT_SHIFT_AC0_FAST_EDCA_PKT_TH)\n#define BITS_AC0_FAST_EDCA_PKT_TH                                              \\\n\t(BIT_MASK_AC0_FAST_EDCA_PKT_TH << BIT_SHIFT_AC0_FAST_EDCA_PKT_TH)\n#define BIT_CLEAR_AC0_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC0_FAST_EDCA_PKT_TH))\n#define BIT_GET_AC0_FAST_EDCA_PKT_TH(x)                                        \\\n\t(((x) >> BIT_SHIFT_AC0_FAST_EDCA_PKT_TH) &                             \\\n\t BIT_MASK_AC0_FAST_EDCA_PKT_TH)\n#define BIT_SET_AC0_FAST_EDCA_PKT_TH(x, v)                                     \\\n\t(BIT_CLEAR_AC0_FAST_EDCA_PKT_TH(x) | BIT_AC0_FAST_EDCA_PKT_TH(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AMPDU_MAX_LENGTH_VHT\t\t(Offset 0x0460) */\n\n#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1 0\n#define BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1 0xfffff\n#define BIT_AMPDU_MAX_LENGTH_VHT_V1(x)                                         \\\n\t(((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1)                              \\\n\t << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1)\n#define BITS_AMPDU_MAX_LENGTH_VHT_V1                                           \\\n\t(BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1 << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1)\n#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1(x)                                   \\\n\t((x) & (~BITS_AMPDU_MAX_LENGTH_VHT_V1))\n#define BIT_GET_AMPDU_MAX_LENGTH_VHT_V1(x)                                     \\\n\t(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1) &                          \\\n\t BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1)\n#define BIT_SET_AMPDU_MAX_LENGTH_VHT_V1(x, v)                                  \\\n\t(BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1(x) | BIT_AMPDU_MAX_LENGTH_VHT_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_AMPDU_MAX_LENGTH_VHT\t\t(Offset 0x0460) */\n\n#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT 0\n#define BIT_MASK_AMPDU_MAX_LENGTH_VHT 0x3ffff\n#define BIT_AMPDU_MAX_LENGTH_VHT(x)                                            \\\n\t(((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT)                                 \\\n\t << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT)\n#define BITS_AMPDU_MAX_LENGTH_VHT                                              \\\n\t(BIT_MASK_AMPDU_MAX_LENGTH_VHT << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT)\n#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT(x) ((x) & (~BITS_AMPDU_MAX_LENGTH_VHT))\n#define BIT_GET_AMPDU_MAX_LENGTH_VHT(x)                                        \\\n\t(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT) &                             \\\n\t BIT_MASK_AMPDU_MAX_LENGTH_VHT)\n#define BIT_SET_AMPDU_MAX_LENGTH_VHT(x, v)                                     \\\n\t(BIT_CLEAR_AMPDU_MAX_LENGTH_VHT(x) | BIT_AMPDU_MAX_LENGTH_VHT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RD_RESP_PKT_TH\t\t\t(Offset 0x0463) */\n\n#define BIT_SHIFT_RD_RESP_PKT_TH 0\n#define BIT_MASK_RD_RESP_PKT_TH 0x1f\n#define BIT_RD_RESP_PKT_TH(x)                                                  \\\n\t(((x) & BIT_MASK_RD_RESP_PKT_TH) << BIT_SHIFT_RD_RESP_PKT_TH)\n#define BITS_RD_RESP_PKT_TH                                                    \\\n\t(BIT_MASK_RD_RESP_PKT_TH << BIT_SHIFT_RD_RESP_PKT_TH)\n#define BIT_CLEAR_RD_RESP_PKT_TH(x) ((x) & (~BITS_RD_RESP_PKT_TH))\n#define BIT_GET_RD_RESP_PKT_TH(x)                                              \\\n\t(((x) >> BIT_SHIFT_RD_RESP_PKT_TH) & BIT_MASK_RD_RESP_PKT_TH)\n#define BIT_SET_RD_RESP_PKT_TH(x, v)                                           \\\n\t(BIT_CLEAR_RD_RESP_PKT_TH(x) | BIT_RD_RESP_PKT_TH(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RD_RESP_PKT_TH\t\t\t(Offset 0x0463) */\n\n#define BIT_SHIFT_RD_RESP_PKT_TH_V1 0\n#define BIT_MASK_RD_RESP_PKT_TH_V1 0x3f\n#define BIT_RD_RESP_PKT_TH_V1(x)                                               \\\n\t(((x) & BIT_MASK_RD_RESP_PKT_TH_V1) << BIT_SHIFT_RD_RESP_PKT_TH_V1)\n#define BITS_RD_RESP_PKT_TH_V1                                                 \\\n\t(BIT_MASK_RD_RESP_PKT_TH_V1 << BIT_SHIFT_RD_RESP_PKT_TH_V1)\n#define BIT_CLEAR_RD_RESP_PKT_TH_V1(x) ((x) & (~BITS_RD_RESP_PKT_TH_V1))\n#define BIT_GET_RD_RESP_PKT_TH_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1) & BIT_MASK_RD_RESP_PKT_TH_V1)\n#define BIT_SET_RD_RESP_PKT_TH_V1(x, v)                                        \\\n\t(BIT_CLEAR_RD_RESP_PKT_TH_V1(x) | BIT_RD_RESP_PKT_TH_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CMDQ_INFO\t\t\t\t(Offset 0x0464) */\n\n#define BIT_SHIFT_QUEUEMACID_CMDQ_V1 25\n#define BIT_MASK_QUEUEMACID_CMDQ_V1 0x7f\n#define BIT_QUEUEMACID_CMDQ_V1(x)                                              \\\n\t(((x) & BIT_MASK_QUEUEMACID_CMDQ_V1) << BIT_SHIFT_QUEUEMACID_CMDQ_V1)\n#define BITS_QUEUEMACID_CMDQ_V1                                                \\\n\t(BIT_MASK_QUEUEMACID_CMDQ_V1 << BIT_SHIFT_QUEUEMACID_CMDQ_V1)\n#define BIT_CLEAR_QUEUEMACID_CMDQ_V1(x) ((x) & (~BITS_QUEUEMACID_CMDQ_V1))\n#define BIT_GET_QUEUEMACID_CMDQ_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1) & BIT_MASK_QUEUEMACID_CMDQ_V1)\n#define BIT_SET_QUEUEMACID_CMDQ_V1(x, v)                                       \\\n\t(BIT_CLEAR_QUEUEMACID_CMDQ_V1(x) | BIT_QUEUEMACID_CMDQ_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CMDQ_INFO\t\t\t\t(Offset 0x0464) */\n\n#define BIT_SHIFT_PKT_NUM_CMDQ_V2 24\n#define BIT_MASK_PKT_NUM_CMDQ_V2 0xff\n#define BIT_PKT_NUM_CMDQ_V2(x)                                                 \\\n\t(((x) & BIT_MASK_PKT_NUM_CMDQ_V2) << BIT_SHIFT_PKT_NUM_CMDQ_V2)\n#define BITS_PKT_NUM_CMDQ_V2                                                   \\\n\t(BIT_MASK_PKT_NUM_CMDQ_V2 << BIT_SHIFT_PKT_NUM_CMDQ_V2)\n#define BIT_CLEAR_PKT_NUM_CMDQ_V2(x) ((x) & (~BITS_PKT_NUM_CMDQ_V2))\n#define BIT_GET_PKT_NUM_CMDQ_V2(x)                                             \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_CMDQ_V2) & BIT_MASK_PKT_NUM_CMDQ_V2)\n#define BIT_SET_PKT_NUM_CMDQ_V2(x, v)                                          \\\n\t(BIT_CLEAR_PKT_NUM_CMDQ_V2(x) | BIT_PKT_NUM_CMDQ_V2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_CMDQ_INFO\t\t\t\t(Offset 0x0464) */\n\n#define BIT_SHIFT_PKT_NUM 23\n#define BIT_MASK_PKT_NUM 0x1ff\n#define BIT_PKT_NUM(x) (((x) & BIT_MASK_PKT_NUM) << BIT_SHIFT_PKT_NUM)\n#define BITS_PKT_NUM (BIT_MASK_PKT_NUM << BIT_SHIFT_PKT_NUM)\n#define BIT_CLEAR_PKT_NUM(x) ((x) & (~BITS_PKT_NUM))\n#define BIT_GET_PKT_NUM(x) (((x) >> BIT_SHIFT_PKT_NUM) & BIT_MASK_PKT_NUM)\n#define BIT_SET_PKT_NUM(x, v) (BIT_CLEAR_PKT_NUM(x) | BIT_PKT_NUM(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CMDQ_INFO\t\t\t\t(Offset 0x0464) */\n\n#define BIT_SHIFT_QUEUEAC_CMDQ_V1 23\n#define BIT_MASK_QUEUEAC_CMDQ_V1 0x3\n#define BIT_QUEUEAC_CMDQ_V1(x)                                                 \\\n\t(((x) & BIT_MASK_QUEUEAC_CMDQ_V1) << BIT_SHIFT_QUEUEAC_CMDQ_V1)\n#define BITS_QUEUEAC_CMDQ_V1                                                   \\\n\t(BIT_MASK_QUEUEAC_CMDQ_V1 << BIT_SHIFT_QUEUEAC_CMDQ_V1)\n#define BIT_CLEAR_QUEUEAC_CMDQ_V1(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1))\n#define BIT_GET_QUEUEAC_CMDQ_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1) & BIT_MASK_QUEUEAC_CMDQ_V1)\n#define BIT_SET_QUEUEAC_CMDQ_V1(x, v)                                          \\\n\t(BIT_CLEAR_QUEUEAC_CMDQ_V1(x) | BIT_QUEUEAC_CMDQ_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CMDQ_INFO\t\t\t\t(Offset 0x0464) */\n\n#define BIT_TIDEMPTY_CMDQ_V1 BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CMDQ_INFO\t\t\t\t(Offset 0x0464) */\n\n#define BIT_SHIFT_TAIL_PKT_CMDQ 16\n#define BIT_MASK_TAIL_PKT_CMDQ 0xff\n#define BIT_TAIL_PKT_CMDQ(x)                                                   \\\n\t(((x) & BIT_MASK_TAIL_PKT_CMDQ) << BIT_SHIFT_TAIL_PKT_CMDQ)\n#define BITS_TAIL_PKT_CMDQ (BIT_MASK_TAIL_PKT_CMDQ << BIT_SHIFT_TAIL_PKT_CMDQ)\n#define BIT_CLEAR_TAIL_PKT_CMDQ(x) ((x) & (~BITS_TAIL_PKT_CMDQ))\n#define BIT_GET_TAIL_PKT_CMDQ(x)                                               \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_CMDQ) & BIT_MASK_TAIL_PKT_CMDQ)\n#define BIT_SET_TAIL_PKT_CMDQ(x, v)                                            \\\n\t(BIT_CLEAR_TAIL_PKT_CMDQ(x) | BIT_TAIL_PKT_CMDQ(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_CMDQ_INFO\t\t\t\t(Offset 0x0464) */\n\n#define BIT_SHIFT_TAIL_PKT_CMDQ_V2 11\n#define BIT_MASK_TAIL_PKT_CMDQ_V2 0x7ff\n#define BIT_TAIL_PKT_CMDQ_V2(x)                                                \\\n\t(((x) & BIT_MASK_TAIL_PKT_CMDQ_V2) << BIT_SHIFT_TAIL_PKT_CMDQ_V2)\n#define BITS_TAIL_PKT_CMDQ_V2                                                  \\\n\t(BIT_MASK_TAIL_PKT_CMDQ_V2 << BIT_SHIFT_TAIL_PKT_CMDQ_V2)\n#define BIT_CLEAR_TAIL_PKT_CMDQ_V2(x) ((x) & (~BITS_TAIL_PKT_CMDQ_V2))\n#define BIT_GET_TAIL_PKT_CMDQ_V2(x)                                            \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2) & BIT_MASK_TAIL_PKT_CMDQ_V2)\n#define BIT_SET_TAIL_PKT_CMDQ_V2(x, v)                                         \\\n\t(BIT_CLEAR_TAIL_PKT_CMDQ_V2(x) | BIT_TAIL_PKT_CMDQ_V2(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_NEW_EDCA_CTRL_V1\t\t\t(Offset 0x0464) */\n\n#define BIT_SHIFT_RANDOM_VALUE_SHIFT 9\n#define BIT_MASK_RANDOM_VALUE_SHIFT 0x7\n#define BIT_RANDOM_VALUE_SHIFT(x)                                              \\\n\t(((x) & BIT_MASK_RANDOM_VALUE_SHIFT) << BIT_SHIFT_RANDOM_VALUE_SHIFT)\n#define BITS_RANDOM_VALUE_SHIFT                                                \\\n\t(BIT_MASK_RANDOM_VALUE_SHIFT << BIT_SHIFT_RANDOM_VALUE_SHIFT)\n#define BIT_CLEAR_RANDOM_VALUE_SHIFT(x) ((x) & (~BITS_RANDOM_VALUE_SHIFT))\n#define BIT_GET_RANDOM_VALUE_SHIFT(x)                                          \\\n\t(((x) >> BIT_SHIFT_RANDOM_VALUE_SHIFT) & BIT_MASK_RANDOM_VALUE_SHIFT)\n#define BIT_SET_RANDOM_VALUE_SHIFT(x, v)                                       \\\n\t(BIT_CLEAR_RANDOM_VALUE_SHIFT(x) | BIT_RANDOM_VALUE_SHIFT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CMDQ_INFO\t\t\t\t(Offset 0x0464) */\n\n#define BIT_SHIFT_PKT_NUM_CMDQ 8\n#define BIT_MASK_PKT_NUM_CMDQ 0xff\n#define BIT_PKT_NUM_CMDQ(x)                                                    \\\n\t(((x) & BIT_MASK_PKT_NUM_CMDQ) << BIT_SHIFT_PKT_NUM_CMDQ)\n#define BITS_PKT_NUM_CMDQ (BIT_MASK_PKT_NUM_CMDQ << BIT_SHIFT_PKT_NUM_CMDQ)\n#define BIT_CLEAR_PKT_NUM_CMDQ(x) ((x) & (~BITS_PKT_NUM_CMDQ))\n#define BIT_GET_PKT_NUM_CMDQ(x)                                                \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_CMDQ) & BIT_MASK_PKT_NUM_CMDQ)\n#define BIT_SET_PKT_NUM_CMDQ(x, v)                                             \\\n\t(BIT_CLEAR_PKT_NUM_CMDQ(x) | BIT_PKT_NUM_CMDQ(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_NEW_EDCA_CTRL_V1\t\t\t(Offset 0x0464) */\n\n#define BIT_ENABLE_NEW_EDCA BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CMDQ_INFO\t\t\t\t(Offset 0x0464) */\n\n#define BIT_SHIFT_HEAD_PKT_CMDQ 0\n#define BIT_MASK_HEAD_PKT_CMDQ 0xff\n#define BIT_HEAD_PKT_CMDQ(x)                                                   \\\n\t(((x) & BIT_MASK_HEAD_PKT_CMDQ) << BIT_SHIFT_HEAD_PKT_CMDQ)\n#define BITS_HEAD_PKT_CMDQ (BIT_MASK_HEAD_PKT_CMDQ << BIT_SHIFT_HEAD_PKT_CMDQ)\n#define BIT_CLEAR_HEAD_PKT_CMDQ(x) ((x) & (~BITS_HEAD_PKT_CMDQ))\n#define BIT_GET_HEAD_PKT_CMDQ(x)                                               \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_CMDQ) & BIT_MASK_HEAD_PKT_CMDQ)\n#define BIT_SET_HEAD_PKT_CMDQ(x, v)                                            \\\n\t(BIT_CLEAR_HEAD_PKT_CMDQ(x) | BIT_HEAD_PKT_CMDQ(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CMDQ_INFO\t\t\t\t(Offset 0x0464) */\n\n#define BIT_SHIFT_HEAD_PKT_CMDQ_V1 0\n#define BIT_MASK_HEAD_PKT_CMDQ_V1 0x7ff\n#define BIT_HEAD_PKT_CMDQ_V1(x)                                                \\\n\t(((x) & BIT_MASK_HEAD_PKT_CMDQ_V1) << BIT_SHIFT_HEAD_PKT_CMDQ_V1)\n#define BITS_HEAD_PKT_CMDQ_V1                                                  \\\n\t(BIT_MASK_HEAD_PKT_CMDQ_V1 << BIT_SHIFT_HEAD_PKT_CMDQ_V1)\n#define BIT_CLEAR_HEAD_PKT_CMDQ_V1(x) ((x) & (~BITS_HEAD_PKT_CMDQ_V1))\n#define BIT_GET_HEAD_PKT_CMDQ_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1) & BIT_MASK_HEAD_PKT_CMDQ_V1)\n#define BIT_SET_HEAD_PKT_CMDQ_V1(x, v)                                         \\\n\t(BIT_CLEAR_HEAD_PKT_CMDQ_V1(x) | BIT_HEAD_PKT_CMDQ_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_NEW_EDCA_CTRL_V1\t\t\t(Offset 0x0464) */\n\n#define BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER 0\n#define BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER 0xff\n#define BIT_MEDIUM_HAS_IDKE_TRIGGER(x)                                         \\\n\t(((x) & BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER)                              \\\n\t << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER)\n#define BITS_MEDIUM_HAS_IDKE_TRIGGER                                           \\\n\t(BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER)\n#define BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER(x)                                   \\\n\t((x) & (~BITS_MEDIUM_HAS_IDKE_TRIGGER))\n#define BIT_GET_MEDIUM_HAS_IDKE_TRIGGER(x)                                     \\\n\t(((x) >> BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER) &                          \\\n\t BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER)\n#define BIT_SET_MEDIUM_HAS_IDKE_TRIGGER(x, v)                                  \\\n\t(BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER(x) | BIT_MEDIUM_HAS_IDKE_TRIGGER(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q4_INFO\t\t\t\t(Offset 0x0468) */\n\n#define BIT_SHIFT_QUEUEMACID_Q4_V1 25\n#define BIT_MASK_QUEUEMACID_Q4_V1 0x7f\n#define BIT_QUEUEMACID_Q4_V1(x)                                                \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q4_V1) << BIT_SHIFT_QUEUEMACID_Q4_V1)\n#define BITS_QUEUEMACID_Q4_V1                                                  \\\n\t(BIT_MASK_QUEUEMACID_Q4_V1 << BIT_SHIFT_QUEUEMACID_Q4_V1)\n#define BIT_CLEAR_QUEUEMACID_Q4_V1(x) ((x) & (~BITS_QUEUEMACID_Q4_V1))\n#define BIT_GET_QUEUEMACID_Q4_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1) & BIT_MASK_QUEUEMACID_Q4_V1)\n#define BIT_SET_QUEUEMACID_Q4_V1(x, v)                                         \\\n\t(BIT_CLEAR_QUEUEMACID_Q4_V1(x) | BIT_QUEUEMACID_Q4_V1(v))\n\n#define BIT_SHIFT_QUEUEAC_Q4_V1 23\n#define BIT_MASK_QUEUEAC_Q4_V1 0x3\n#define BIT_QUEUEAC_Q4_V1(x)                                                   \\\n\t(((x) & BIT_MASK_QUEUEAC_Q4_V1) << BIT_SHIFT_QUEUEAC_Q4_V1)\n#define BITS_QUEUEAC_Q4_V1 (BIT_MASK_QUEUEAC_Q4_V1 << BIT_SHIFT_QUEUEAC_Q4_V1)\n#define BIT_CLEAR_QUEUEAC_Q4_V1(x) ((x) & (~BITS_QUEUEAC_Q4_V1))\n#define BIT_GET_QUEUEAC_Q4_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q4_V1) & BIT_MASK_QUEUEAC_Q4_V1)\n#define BIT_SET_QUEUEAC_Q4_V1(x, v)                                            \\\n\t(BIT_CLEAR_QUEUEAC_Q4_V1(x) | BIT_QUEUEAC_Q4_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q4_INFO\t\t\t\t(Offset 0x0468) */\n\n#define BIT_TIDEMPTY_Q4_V1 BIT(22)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACQ_STOP_V2\t\t\t\t(Offset 0x0468) */\n\n#define BIT_AC19Q_STOP BIT(19)\n#define BIT_AC18Q_STOP BIT(18)\n#define BIT_AC17Q_STOP BIT(17)\n#define BIT_AC16Q_STOP BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q4_INFO\t\t\t\t(Offset 0x0468) */\n\n#define BIT_SHIFT_TAIL_PKT_Q4_V1 15\n#define BIT_MASK_TAIL_PKT_Q4_V1 0xff\n#define BIT_TAIL_PKT_Q4_V1(x)                                                  \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q4_V1) << BIT_SHIFT_TAIL_PKT_Q4_V1)\n#define BITS_TAIL_PKT_Q4_V1                                                    \\\n\t(BIT_MASK_TAIL_PKT_Q4_V1 << BIT_SHIFT_TAIL_PKT_Q4_V1)\n#define BIT_CLEAR_TAIL_PKT_Q4_V1(x) ((x) & (~BITS_TAIL_PKT_Q4_V1))\n#define BIT_GET_TAIL_PKT_Q4_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q4_V1) & BIT_MASK_TAIL_PKT_Q4_V1)\n#define BIT_SET_TAIL_PKT_Q4_V1(x, v)                                           \\\n\t(BIT_CLEAR_TAIL_PKT_Q4_V1(x) | BIT_TAIL_PKT_Q4_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACQ_STOP_V2\t\t\t\t(Offset 0x0468) */\n\n#define BIT_AC15Q_STOP BIT(15)\n#define BIT_AC14Q_STOP BIT(14)\n#define BIT_AC13Q_STOP BIT(13)\n#define BIT_AC12Q_STOP BIT(12)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q4_INFO\t\t\t\t(Offset 0x0468) */\n\n#define BIT_SHIFT_TAIL_PKT_Q4_V2 11\n#define BIT_MASK_TAIL_PKT_Q4_V2 0x7ff\n#define BIT_TAIL_PKT_Q4_V2(x)                                                  \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q4_V2) << BIT_SHIFT_TAIL_PKT_Q4_V2)\n#define BITS_TAIL_PKT_Q4_V2                                                    \\\n\t(BIT_MASK_TAIL_PKT_Q4_V2 << BIT_SHIFT_TAIL_PKT_Q4_V2)\n#define BIT_CLEAR_TAIL_PKT_Q4_V2(x) ((x) & (~BITS_TAIL_PKT_Q4_V2))\n#define BIT_GET_TAIL_PKT_Q4_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2) & BIT_MASK_TAIL_PKT_Q4_V2)\n#define BIT_SET_TAIL_PKT_Q4_V2(x, v)                                           \\\n\t(BIT_CLEAR_TAIL_PKT_Q4_V2(x) | BIT_TAIL_PKT_Q4_V2(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACQ_STOP_V2\t\t\t\t(Offset 0x0468) */\n\n#define BIT_AC11Q_STOP BIT(11)\n#define BIT_AC10Q_STOP BIT(10)\n#define BIT_AC9Q_STOP BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q4_INFO\t\t\t\t(Offset 0x0468) */\n\n#define BIT_SHIFT_PKT_NUM_Q4_V1 8\n#define BIT_MASK_PKT_NUM_Q4_V1 0x7f\n#define BIT_PKT_NUM_Q4_V1(x)                                                   \\\n\t(((x) & BIT_MASK_PKT_NUM_Q4_V1) << BIT_SHIFT_PKT_NUM_Q4_V1)\n#define BITS_PKT_NUM_Q4_V1 (BIT_MASK_PKT_NUM_Q4_V1 << BIT_SHIFT_PKT_NUM_Q4_V1)\n#define BIT_CLEAR_PKT_NUM_Q4_V1(x) ((x) & (~BITS_PKT_NUM_Q4_V1))\n#define BIT_GET_PKT_NUM_Q4_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_Q4_V1) & BIT_MASK_PKT_NUM_Q4_V1)\n#define BIT_SET_PKT_NUM_Q4_V1(x, v)                                            \\\n\t(BIT_CLEAR_PKT_NUM_Q4_V1(x) | BIT_PKT_NUM_Q4_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACQ_STOP_V2\t\t\t\t(Offset 0x0468) */\n\n#define BIT_AC8Q_STOP BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q4_INFO\t\t\t\t(Offset 0x0468) */\n\n#define BIT_SHIFT_HEAD_PKT_Q4 0\n#define BIT_MASK_HEAD_PKT_Q4 0xff\n#define BIT_HEAD_PKT_Q4(x)                                                     \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q4) << BIT_SHIFT_HEAD_PKT_Q4)\n#define BITS_HEAD_PKT_Q4 (BIT_MASK_HEAD_PKT_Q4 << BIT_SHIFT_HEAD_PKT_Q4)\n#define BIT_CLEAR_HEAD_PKT_Q4(x) ((x) & (~BITS_HEAD_PKT_Q4))\n#define BIT_GET_HEAD_PKT_Q4(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q4) & BIT_MASK_HEAD_PKT_Q4)\n#define BIT_SET_HEAD_PKT_Q4(x, v)                                              \\\n\t(BIT_CLEAR_HEAD_PKT_Q4(x) | BIT_HEAD_PKT_Q4(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q4_INFO\t\t\t\t(Offset 0x0468) */\n\n#define BIT_SHIFT_HEAD_PKT_Q4_V1 0\n#define BIT_MASK_HEAD_PKT_Q4_V1 0x7ff\n#define BIT_HEAD_PKT_Q4_V1(x)                                                  \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q4_V1) << BIT_SHIFT_HEAD_PKT_Q4_V1)\n#define BITS_HEAD_PKT_Q4_V1                                                    \\\n\t(BIT_MASK_HEAD_PKT_Q4_V1 << BIT_SHIFT_HEAD_PKT_Q4_V1)\n#define BIT_CLEAR_HEAD_PKT_Q4_V1(x) ((x) & (~BITS_HEAD_PKT_Q4_V1))\n#define BIT_GET_HEAD_PKT_Q4_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1) & BIT_MASK_HEAD_PKT_Q4_V1)\n#define BIT_SET_HEAD_PKT_Q4_V1(x, v)                                           \\\n\t(BIT_CLEAR_HEAD_PKT_Q4_V1(x) | BIT_HEAD_PKT_Q4_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q5_INFO\t\t\t\t(Offset 0x046C) */\n\n#define BIT_SHIFT_QUEUEMACID_Q5_V1 25\n#define BIT_MASK_QUEUEMACID_Q5_V1 0x7f\n#define BIT_QUEUEMACID_Q5_V1(x)                                                \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q5_V1) << BIT_SHIFT_QUEUEMACID_Q5_V1)\n#define BITS_QUEUEMACID_Q5_V1                                                  \\\n\t(BIT_MASK_QUEUEMACID_Q5_V1 << BIT_SHIFT_QUEUEMACID_Q5_V1)\n#define BIT_CLEAR_QUEUEMACID_Q5_V1(x) ((x) & (~BITS_QUEUEMACID_Q5_V1))\n#define BIT_GET_QUEUEMACID_Q5_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1) & BIT_MASK_QUEUEMACID_Q5_V1)\n#define BIT_SET_QUEUEMACID_Q5_V1(x, v)                                         \\\n\t(BIT_CLEAR_QUEUEMACID_Q5_V1(x) | BIT_QUEUEMACID_Q5_V1(v))\n\n#define BIT_SHIFT_QUEUEAC_Q5_V1 23\n#define BIT_MASK_QUEUEAC_Q5_V1 0x3\n#define BIT_QUEUEAC_Q5_V1(x)                                                   \\\n\t(((x) & BIT_MASK_QUEUEAC_Q5_V1) << BIT_SHIFT_QUEUEAC_Q5_V1)\n#define BITS_QUEUEAC_Q5_V1 (BIT_MASK_QUEUEAC_Q5_V1 << BIT_SHIFT_QUEUEAC_Q5_V1)\n#define BIT_CLEAR_QUEUEAC_Q5_V1(x) ((x) & (~BITS_QUEUEAC_Q5_V1))\n#define BIT_GET_QUEUEAC_Q5_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q5_V1) & BIT_MASK_QUEUEAC_Q5_V1)\n#define BIT_SET_QUEUEAC_Q5_V1(x, v)                                            \\\n\t(BIT_CLEAR_QUEUEAC_Q5_V1(x) | BIT_QUEUEAC_Q5_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q5_INFO\t\t\t\t(Offset 0x046C) */\n\n#define BIT_TIDEMPTY_Q5_V1 BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q5_INFO\t\t\t\t(Offset 0x046C) */\n\n#define BIT_SHIFT_TAIL_PKT_Q5_V1 15\n#define BIT_MASK_TAIL_PKT_Q5_V1 0xff\n#define BIT_TAIL_PKT_Q5_V1(x)                                                  \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q5_V1) << BIT_SHIFT_TAIL_PKT_Q5_V1)\n#define BITS_TAIL_PKT_Q5_V1                                                    \\\n\t(BIT_MASK_TAIL_PKT_Q5_V1 << BIT_SHIFT_TAIL_PKT_Q5_V1)\n#define BIT_CLEAR_TAIL_PKT_Q5_V1(x) ((x) & (~BITS_TAIL_PKT_Q5_V1))\n#define BIT_GET_TAIL_PKT_Q5_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q5_V1) & BIT_MASK_TAIL_PKT_Q5_V1)\n#define BIT_SET_TAIL_PKT_Q5_V1(x, v)                                           \\\n\t(BIT_CLEAR_TAIL_PKT_Q5_V1(x) | BIT_TAIL_PKT_Q5_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q5_INFO\t\t\t\t(Offset 0x046C) */\n\n#define BIT_SHIFT_TAIL_PKT_Q5_V2 11\n#define BIT_MASK_TAIL_PKT_Q5_V2 0x7ff\n#define BIT_TAIL_PKT_Q5_V2(x)                                                  \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q5_V2) << BIT_SHIFT_TAIL_PKT_Q5_V2)\n#define BITS_TAIL_PKT_Q5_V2                                                    \\\n\t(BIT_MASK_TAIL_PKT_Q5_V2 << BIT_SHIFT_TAIL_PKT_Q5_V2)\n#define BIT_CLEAR_TAIL_PKT_Q5_V2(x) ((x) & (~BITS_TAIL_PKT_Q5_V2))\n#define BIT_GET_TAIL_PKT_Q5_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2) & BIT_MASK_TAIL_PKT_Q5_V2)\n#define BIT_SET_TAIL_PKT_Q5_V2(x, v)                                           \\\n\t(BIT_CLEAR_TAIL_PKT_Q5_V2(x) | BIT_TAIL_PKT_Q5_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q5_INFO\t\t\t\t(Offset 0x046C) */\n\n#define BIT_SHIFT_PKT_NUM_Q5_V1 8\n#define BIT_MASK_PKT_NUM_Q5_V1 0x7f\n#define BIT_PKT_NUM_Q5_V1(x)                                                   \\\n\t(((x) & BIT_MASK_PKT_NUM_Q5_V1) << BIT_SHIFT_PKT_NUM_Q5_V1)\n#define BITS_PKT_NUM_Q5_V1 (BIT_MASK_PKT_NUM_Q5_V1 << BIT_SHIFT_PKT_NUM_Q5_V1)\n#define BIT_CLEAR_PKT_NUM_Q5_V1(x) ((x) & (~BITS_PKT_NUM_Q5_V1))\n#define BIT_GET_PKT_NUM_Q5_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_Q5_V1) & BIT_MASK_PKT_NUM_Q5_V1)\n#define BIT_SET_PKT_NUM_Q5_V1(x, v)                                            \\\n\t(BIT_CLEAR_PKT_NUM_Q5_V1(x) | BIT_PKT_NUM_Q5_V1(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q5 0\n#define BIT_MASK_HEAD_PKT_Q5 0xff\n#define BIT_HEAD_PKT_Q5(x)                                                     \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q5) << BIT_SHIFT_HEAD_PKT_Q5)\n#define BITS_HEAD_PKT_Q5 (BIT_MASK_HEAD_PKT_Q5 << BIT_SHIFT_HEAD_PKT_Q5)\n#define BIT_CLEAR_HEAD_PKT_Q5(x) ((x) & (~BITS_HEAD_PKT_Q5))\n#define BIT_GET_HEAD_PKT_Q5(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q5) & BIT_MASK_HEAD_PKT_Q5)\n#define BIT_SET_HEAD_PKT_Q5(x, v)                                              \\\n\t(BIT_CLEAR_HEAD_PKT_Q5(x) | BIT_HEAD_PKT_Q5(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q5_INFO\t\t\t\t(Offset 0x046C) */\n\n#define BIT_SHIFT_HEAD_PKT_Q5_V1 0\n#define BIT_MASK_HEAD_PKT_Q5_V1 0x7ff\n#define BIT_HEAD_PKT_Q5_V1(x)                                                  \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q5_V1) << BIT_SHIFT_HEAD_PKT_Q5_V1)\n#define BITS_HEAD_PKT_Q5_V1                                                    \\\n\t(BIT_MASK_HEAD_PKT_Q5_V1 << BIT_SHIFT_HEAD_PKT_Q5_V1)\n#define BIT_CLEAR_HEAD_PKT_Q5_V1(x) ((x) & (~BITS_HEAD_PKT_Q5_V1))\n#define BIT_GET_HEAD_PKT_Q5_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1) & BIT_MASK_HEAD_PKT_Q5_V1)\n#define BIT_SET_HEAD_PKT_Q5_V1(x, v)                                           \\\n\t(BIT_CLEAR_HEAD_PKT_Q5_V1(x) | BIT_HEAD_PKT_Q5_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q6_INFO\t\t\t\t(Offset 0x0470) */\n\n#define BIT_SHIFT_QUEUEMACID_Q6_V1 25\n#define BIT_MASK_QUEUEMACID_Q6_V1 0x7f\n#define BIT_QUEUEMACID_Q6_V1(x)                                                \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q6_V1) << BIT_SHIFT_QUEUEMACID_Q6_V1)\n#define BITS_QUEUEMACID_Q6_V1                                                  \\\n\t(BIT_MASK_QUEUEMACID_Q6_V1 << BIT_SHIFT_QUEUEMACID_Q6_V1)\n#define BIT_CLEAR_QUEUEMACID_Q6_V1(x) ((x) & (~BITS_QUEUEMACID_Q6_V1))\n#define BIT_GET_QUEUEMACID_Q6_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1) & BIT_MASK_QUEUEMACID_Q6_V1)\n#define BIT_SET_QUEUEMACID_Q6_V1(x, v)                                         \\\n\t(BIT_CLEAR_QUEUEMACID_Q6_V1(x) | BIT_QUEUEMACID_Q6_V1(v))\n\n#define BIT_SHIFT_QUEUEAC_Q6_V1 23\n#define BIT_MASK_QUEUEAC_Q6_V1 0x3\n#define BIT_QUEUEAC_Q6_V1(x)                                                   \\\n\t(((x) & BIT_MASK_QUEUEAC_Q6_V1) << BIT_SHIFT_QUEUEAC_Q6_V1)\n#define BITS_QUEUEAC_Q6_V1 (BIT_MASK_QUEUEAC_Q6_V1 << BIT_SHIFT_QUEUEAC_Q6_V1)\n#define BIT_CLEAR_QUEUEAC_Q6_V1(x) ((x) & (~BITS_QUEUEAC_Q6_V1))\n#define BIT_GET_QUEUEAC_Q6_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q6_V1) & BIT_MASK_QUEUEAC_Q6_V1)\n#define BIT_SET_QUEUEAC_Q6_V1(x, v)                                            \\\n\t(BIT_CLEAR_QUEUEAC_Q6_V1(x) | BIT_QUEUEAC_Q6_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q6_INFO\t\t\t\t(Offset 0x0470) */\n\n#define BIT_TIDEMPTY_Q6_V1 BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q6_INFO\t\t\t\t(Offset 0x0470) */\n\n#define BIT_SHIFT_TAIL_PKT_Q6_V1 15\n#define BIT_MASK_TAIL_PKT_Q6_V1 0xff\n#define BIT_TAIL_PKT_Q6_V1(x)                                                  \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q6_V1) << BIT_SHIFT_TAIL_PKT_Q6_V1)\n#define BITS_TAIL_PKT_Q6_V1                                                    \\\n\t(BIT_MASK_TAIL_PKT_Q6_V1 << BIT_SHIFT_TAIL_PKT_Q6_V1)\n#define BIT_CLEAR_TAIL_PKT_Q6_V1(x) ((x) & (~BITS_TAIL_PKT_Q6_V1))\n#define BIT_GET_TAIL_PKT_Q6_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q6_V1) & BIT_MASK_TAIL_PKT_Q6_V1)\n#define BIT_SET_TAIL_PKT_Q6_V1(x, v)                                           \\\n\t(BIT_CLEAR_TAIL_PKT_Q6_V1(x) | BIT_TAIL_PKT_Q6_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q6_INFO\t\t\t\t(Offset 0x0470) */\n\n#define BIT_SHIFT_TAIL_PKT_Q6_V2 11\n#define BIT_MASK_TAIL_PKT_Q6_V2 0x7ff\n#define BIT_TAIL_PKT_Q6_V2(x)                                                  \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q6_V2) << BIT_SHIFT_TAIL_PKT_Q6_V2)\n#define BITS_TAIL_PKT_Q6_V2                                                    \\\n\t(BIT_MASK_TAIL_PKT_Q6_V2 << BIT_SHIFT_TAIL_PKT_Q6_V2)\n#define BIT_CLEAR_TAIL_PKT_Q6_V2(x) ((x) & (~BITS_TAIL_PKT_Q6_V2))\n#define BIT_GET_TAIL_PKT_Q6_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2) & BIT_MASK_TAIL_PKT_Q6_V2)\n#define BIT_SET_TAIL_PKT_Q6_V2(x, v)                                           \\\n\t(BIT_CLEAR_TAIL_PKT_Q6_V2(x) | BIT_TAIL_PKT_Q6_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q6_INFO\t\t\t\t(Offset 0x0470) */\n\n#define BIT_SHIFT_PKT_NUM_Q6_V1 8\n#define BIT_MASK_PKT_NUM_Q6_V1 0x7f\n#define BIT_PKT_NUM_Q6_V1(x)                                                   \\\n\t(((x) & BIT_MASK_PKT_NUM_Q6_V1) << BIT_SHIFT_PKT_NUM_Q6_V1)\n#define BITS_PKT_NUM_Q6_V1 (BIT_MASK_PKT_NUM_Q6_V1 << BIT_SHIFT_PKT_NUM_Q6_V1)\n#define BIT_CLEAR_PKT_NUM_Q6_V1(x) ((x) & (~BITS_PKT_NUM_Q6_V1))\n#define BIT_GET_PKT_NUM_Q6_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_Q6_V1) & BIT_MASK_PKT_NUM_Q6_V1)\n#define BIT_SET_PKT_NUM_Q6_V1(x, v)                                            \\\n\t(BIT_CLEAR_PKT_NUM_Q6_V1(x) | BIT_PKT_NUM_Q6_V1(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q6 0\n#define BIT_MASK_HEAD_PKT_Q6 0xff\n#define BIT_HEAD_PKT_Q6(x)                                                     \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q6) << BIT_SHIFT_HEAD_PKT_Q6)\n#define BITS_HEAD_PKT_Q6 (BIT_MASK_HEAD_PKT_Q6 << BIT_SHIFT_HEAD_PKT_Q6)\n#define BIT_CLEAR_HEAD_PKT_Q6(x) ((x) & (~BITS_HEAD_PKT_Q6))\n#define BIT_GET_HEAD_PKT_Q6(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q6) & BIT_MASK_HEAD_PKT_Q6)\n#define BIT_SET_HEAD_PKT_Q6(x, v)                                              \\\n\t(BIT_CLEAR_HEAD_PKT_Q6(x) | BIT_HEAD_PKT_Q6(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q6_INFO\t\t\t\t(Offset 0x0470) */\n\n#define BIT_SHIFT_HEAD_PKT_Q6_V1 0\n#define BIT_MASK_HEAD_PKT_Q6_V1 0x7ff\n#define BIT_HEAD_PKT_Q6_V1(x)                                                  \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q6_V1) << BIT_SHIFT_HEAD_PKT_Q6_V1)\n#define BITS_HEAD_PKT_Q6_V1                                                    \\\n\t(BIT_MASK_HEAD_PKT_Q6_V1 << BIT_SHIFT_HEAD_PKT_Q6_V1)\n#define BIT_CLEAR_HEAD_PKT_Q6_V1(x) ((x) & (~BITS_HEAD_PKT_Q6_V1))\n#define BIT_GET_HEAD_PKT_Q6_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1) & BIT_MASK_HEAD_PKT_Q6_V1)\n#define BIT_SET_HEAD_PKT_Q6_V1(x, v)                                           \\\n\t(BIT_CLEAR_HEAD_PKT_Q6_V1(x) | BIT_HEAD_PKT_Q6_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q7_INFO\t\t\t\t(Offset 0x0474) */\n\n#define BIT_SHIFT_QUEUEMACID_Q7_V1 25\n#define BIT_MASK_QUEUEMACID_Q7_V1 0x7f\n#define BIT_QUEUEMACID_Q7_V1(x)                                                \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q7_V1) << BIT_SHIFT_QUEUEMACID_Q7_V1)\n#define BITS_QUEUEMACID_Q7_V1                                                  \\\n\t(BIT_MASK_QUEUEMACID_Q7_V1 << BIT_SHIFT_QUEUEMACID_Q7_V1)\n#define BIT_CLEAR_QUEUEMACID_Q7_V1(x) ((x) & (~BITS_QUEUEMACID_Q7_V1))\n#define BIT_GET_QUEUEMACID_Q7_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1) & BIT_MASK_QUEUEMACID_Q7_V1)\n#define BIT_SET_QUEUEMACID_Q7_V1(x, v)                                         \\\n\t(BIT_CLEAR_QUEUEMACID_Q7_V1(x) | BIT_QUEUEMACID_Q7_V1(v))\n\n#define BIT_SHIFT_QUEUEAC_Q7_V1 23\n#define BIT_MASK_QUEUEAC_Q7_V1 0x3\n#define BIT_QUEUEAC_Q7_V1(x)                                                   \\\n\t(((x) & BIT_MASK_QUEUEAC_Q7_V1) << BIT_SHIFT_QUEUEAC_Q7_V1)\n#define BITS_QUEUEAC_Q7_V1 (BIT_MASK_QUEUEAC_Q7_V1 << BIT_SHIFT_QUEUEAC_Q7_V1)\n#define BIT_CLEAR_QUEUEAC_Q7_V1(x) ((x) & (~BITS_QUEUEAC_Q7_V1))\n#define BIT_GET_QUEUEAC_Q7_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q7_V1) & BIT_MASK_QUEUEAC_Q7_V1)\n#define BIT_SET_QUEUEAC_Q7_V1(x, v)                                            \\\n\t(BIT_CLEAR_QUEUEAC_Q7_V1(x) | BIT_QUEUEAC_Q7_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q7_INFO\t\t\t\t(Offset 0x0474) */\n\n#define BIT_TIDEMPTY_Q7_V1 BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q7_INFO\t\t\t\t(Offset 0x0474) */\n\n#define BIT_SHIFT_TAIL_PKT_Q7_V1 15\n#define BIT_MASK_TAIL_PKT_Q7_V1 0xff\n#define BIT_TAIL_PKT_Q7_V1(x)                                                  \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q7_V1) << BIT_SHIFT_TAIL_PKT_Q7_V1)\n#define BITS_TAIL_PKT_Q7_V1                                                    \\\n\t(BIT_MASK_TAIL_PKT_Q7_V1 << BIT_SHIFT_TAIL_PKT_Q7_V1)\n#define BIT_CLEAR_TAIL_PKT_Q7_V1(x) ((x) & (~BITS_TAIL_PKT_Q7_V1))\n#define BIT_GET_TAIL_PKT_Q7_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q7_V1) & BIT_MASK_TAIL_PKT_Q7_V1)\n#define BIT_SET_TAIL_PKT_Q7_V1(x, v)                                           \\\n\t(BIT_CLEAR_TAIL_PKT_Q7_V1(x) | BIT_TAIL_PKT_Q7_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q7_INFO\t\t\t\t(Offset 0x0474) */\n\n#define BIT_SHIFT_TAIL_PKT_Q7_V2 11\n#define BIT_MASK_TAIL_PKT_Q7_V2 0x7ff\n#define BIT_TAIL_PKT_Q7_V2(x)                                                  \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q7_V2) << BIT_SHIFT_TAIL_PKT_Q7_V2)\n#define BITS_TAIL_PKT_Q7_V2                                                    \\\n\t(BIT_MASK_TAIL_PKT_Q7_V2 << BIT_SHIFT_TAIL_PKT_Q7_V2)\n#define BIT_CLEAR_TAIL_PKT_Q7_V2(x) ((x) & (~BITS_TAIL_PKT_Q7_V2))\n#define BIT_GET_TAIL_PKT_Q7_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2) & BIT_MASK_TAIL_PKT_Q7_V2)\n#define BIT_SET_TAIL_PKT_Q7_V2(x, v)                                           \\\n\t(BIT_CLEAR_TAIL_PKT_Q7_V2(x) | BIT_TAIL_PKT_Q7_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_Q7_INFO\t\t\t\t(Offset 0x0474) */\n\n#define BIT_SHIFT_PKT_NUM_Q7_V1 8\n#define BIT_MASK_PKT_NUM_Q7_V1 0x7f\n#define BIT_PKT_NUM_Q7_V1(x)                                                   \\\n\t(((x) & BIT_MASK_PKT_NUM_Q7_V1) << BIT_SHIFT_PKT_NUM_Q7_V1)\n#define BITS_PKT_NUM_Q7_V1 (BIT_MASK_PKT_NUM_Q7_V1 << BIT_SHIFT_PKT_NUM_Q7_V1)\n#define BIT_CLEAR_PKT_NUM_Q7_V1(x) ((x) & (~BITS_PKT_NUM_Q7_V1))\n#define BIT_GET_PKT_NUM_Q7_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_Q7_V1) & BIT_MASK_PKT_NUM_Q7_V1)\n#define BIT_SET_PKT_NUM_Q7_V1(x, v)                                            \\\n\t(BIT_CLEAR_PKT_NUM_Q7_V1(x) | BIT_PKT_NUM_Q7_V1(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q7 0\n#define BIT_MASK_HEAD_PKT_Q7 0xff\n#define BIT_HEAD_PKT_Q7(x)                                                     \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q7) << BIT_SHIFT_HEAD_PKT_Q7)\n#define BITS_HEAD_PKT_Q7 (BIT_MASK_HEAD_PKT_Q7 << BIT_SHIFT_HEAD_PKT_Q7)\n#define BIT_CLEAR_HEAD_PKT_Q7(x) ((x) & (~BITS_HEAD_PKT_Q7))\n#define BIT_GET_HEAD_PKT_Q7(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q7) & BIT_MASK_HEAD_PKT_Q7)\n#define BIT_SET_HEAD_PKT_Q7(x, v)                                              \\\n\t(BIT_CLEAR_HEAD_PKT_Q7(x) | BIT_HEAD_PKT_Q7(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q7_INFO\t\t\t\t(Offset 0x0474) */\n\n#define BIT_SHIFT_HEAD_PKT_Q7_V1 0\n#define BIT_MASK_HEAD_PKT_Q7_V1 0x7ff\n#define BIT_HEAD_PKT_Q7_V1(x)                                                  \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q7_V1) << BIT_SHIFT_HEAD_PKT_Q7_V1)\n#define BITS_HEAD_PKT_Q7_V1                                                    \\\n\t(BIT_MASK_HEAD_PKT_Q7_V1 << BIT_SHIFT_HEAD_PKT_Q7_V1)\n#define BIT_CLEAR_HEAD_PKT_Q7_V1(x) ((x) & (~BITS_HEAD_PKT_Q7_V1))\n#define BIT_GET_HEAD_PKT_Q7_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1) & BIT_MASK_HEAD_PKT_Q7_V1)\n#define BIT_SET_HEAD_PKT_Q7_V1(x, v)                                           \\\n\t(BIT_CLEAR_HEAD_PKT_Q7_V1(x) | BIT_HEAD_PKT_Q7_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_LBK_BUF_HD_V1\t\t\t(Offset 0x0478) */\n\n#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1 0\n#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1 0xfff\n#define BIT_WMAC_LBK_BUF_HEAD_V1(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1)                                 \\\n\t << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1)\n#define BITS_WMAC_LBK_BUF_HEAD_V1                                              \\\n\t(BIT_MASK_WMAC_LBK_BUF_HEAD_V1 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1)\n#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1(x) ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1))\n#define BIT_GET_WMAC_LBK_BUF_HEAD_V1(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) &                             \\\n\t BIT_MASK_WMAC_LBK_BUF_HEAD_V1)\n#define BIT_SET_WMAC_LBK_BUF_HEAD_V1(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1(x) | BIT_WMAC_LBK_BUF_HEAD_V1(v))\n\n/* 2 REG_MGQ_BDNY_V1\t\t\t\t(Offset 0x047A) */\n\n#define BIT_SHIFT_MGQ_PGBNDY_V1 0\n#define BIT_MASK_MGQ_PGBNDY_V1 0xfff\n#define BIT_MGQ_PGBNDY_V1(x)                                                   \\\n\t(((x) & BIT_MASK_MGQ_PGBNDY_V1) << BIT_SHIFT_MGQ_PGBNDY_V1)\n#define BITS_MGQ_PGBNDY_V1 (BIT_MASK_MGQ_PGBNDY_V1 << BIT_SHIFT_MGQ_PGBNDY_V1)\n#define BIT_CLEAR_MGQ_PGBNDY_V1(x) ((x) & (~BITS_MGQ_PGBNDY_V1))\n#define BIT_GET_MGQ_PGBNDY_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_MGQ_PGBNDY_V1) & BIT_MASK_MGQ_PGBNDY_V1)\n#define BIT_SET_MGQ_PGBNDY_V1(x, v)                                            \\\n\t(BIT_CLEAR_MGQ_PGBNDY_V1(x) | BIT_MGQ_PGBNDY_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXRPT_CTRL\t\t\t\t(Offset 0x047C) */\n\n#define BIT_SHIFT_SPC_READ_PTR 24\n#define BIT_MASK_SPC_READ_PTR 0xf\n#define BIT_SPC_READ_PTR(x)                                                    \\\n\t(((x) & BIT_MASK_SPC_READ_PTR) << BIT_SHIFT_SPC_READ_PTR)\n#define BITS_SPC_READ_PTR (BIT_MASK_SPC_READ_PTR << BIT_SHIFT_SPC_READ_PTR)\n#define BIT_CLEAR_SPC_READ_PTR(x) ((x) & (~BITS_SPC_READ_PTR))\n#define BIT_GET_SPC_READ_PTR(x)                                                \\\n\t(((x) >> BIT_SHIFT_SPC_READ_PTR) & BIT_MASK_SPC_READ_PTR)\n#define BIT_SET_SPC_READ_PTR(x, v)                                             \\\n\t(BIT_CLEAR_SPC_READ_PTR(x) | BIT_SPC_READ_PTR(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXRPT_CTRL\t\t\t\t(Offset 0x047C) */\n\n#define BIT_SHIFT_TRXRPT_TIMER_TH 24\n#define BIT_MASK_TRXRPT_TIMER_TH 0xff\n#define BIT_TRXRPT_TIMER_TH(x)                                                 \\\n\t(((x) & BIT_MASK_TRXRPT_TIMER_TH) << BIT_SHIFT_TRXRPT_TIMER_TH)\n#define BITS_TRXRPT_TIMER_TH                                                   \\\n\t(BIT_MASK_TRXRPT_TIMER_TH << BIT_SHIFT_TRXRPT_TIMER_TH)\n#define BIT_CLEAR_TRXRPT_TIMER_TH(x) ((x) & (~BITS_TRXRPT_TIMER_TH))\n#define BIT_GET_TRXRPT_TIMER_TH(x)                                             \\\n\t(((x) >> BIT_SHIFT_TRXRPT_TIMER_TH) & BIT_MASK_TRXRPT_TIMER_TH)\n#define BIT_SET_TRXRPT_TIMER_TH(x, v)                                          \\\n\t(BIT_CLEAR_TRXRPT_TIMER_TH(x) | BIT_TRXRPT_TIMER_TH(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXRPT_CTRL\t\t\t\t(Offset 0x047C) */\n\n#define BIT_SHIFT_SPC_WRITE_PTR 16\n#define BIT_MASK_SPC_WRITE_PTR 0xf\n#define BIT_SPC_WRITE_PTR(x)                                                   \\\n\t(((x) & BIT_MASK_SPC_WRITE_PTR) << BIT_SHIFT_SPC_WRITE_PTR)\n#define BITS_SPC_WRITE_PTR (BIT_MASK_SPC_WRITE_PTR << BIT_SHIFT_SPC_WRITE_PTR)\n#define BIT_CLEAR_SPC_WRITE_PTR(x) ((x) & (~BITS_SPC_WRITE_PTR))\n#define BIT_GET_SPC_WRITE_PTR(x)                                               \\\n\t(((x) >> BIT_SHIFT_SPC_WRITE_PTR) & BIT_MASK_SPC_WRITE_PTR)\n#define BIT_SET_SPC_WRITE_PTR(x, v)                                            \\\n\t(BIT_CLEAR_SPC_WRITE_PTR(x) | BIT_SPC_WRITE_PTR(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXRPT_CTRL\t\t\t\t(Offset 0x047C) */\n\n#define BIT_SHIFT_TRXRPT_LEN_TH 16\n#define BIT_MASK_TRXRPT_LEN_TH 0xff\n#define BIT_TRXRPT_LEN_TH(x)                                                   \\\n\t(((x) & BIT_MASK_TRXRPT_LEN_TH) << BIT_SHIFT_TRXRPT_LEN_TH)\n#define BITS_TRXRPT_LEN_TH (BIT_MASK_TRXRPT_LEN_TH << BIT_SHIFT_TRXRPT_LEN_TH)\n#define BIT_CLEAR_TRXRPT_LEN_TH(x) ((x) & (~BITS_TRXRPT_LEN_TH))\n#define BIT_GET_TRXRPT_LEN_TH(x)                                               \\\n\t(((x) >> BIT_SHIFT_TRXRPT_LEN_TH) & BIT_MASK_TRXRPT_LEN_TH)\n#define BIT_SET_TRXRPT_LEN_TH(x, v)                                            \\\n\t(BIT_CLEAR_TRXRPT_LEN_TH(x) | BIT_TRXRPT_LEN_TH(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXRPT_CTRL\t\t\t\t(Offset 0x047C) */\n\n#define BIT_SHIFT_AC_READ_PTR 8\n#define BIT_MASK_AC_READ_PTR 0xf\n#define BIT_AC_READ_PTR(x)                                                     \\\n\t(((x) & BIT_MASK_AC_READ_PTR) << BIT_SHIFT_AC_READ_PTR)\n#define BITS_AC_READ_PTR (BIT_MASK_AC_READ_PTR << BIT_SHIFT_AC_READ_PTR)\n#define BIT_CLEAR_AC_READ_PTR(x) ((x) & (~BITS_AC_READ_PTR))\n#define BIT_GET_AC_READ_PTR(x)                                                 \\\n\t(((x) >> BIT_SHIFT_AC_READ_PTR) & BIT_MASK_AC_READ_PTR)\n#define BIT_SET_AC_READ_PTR(x, v)                                              \\\n\t(BIT_CLEAR_AC_READ_PTR(x) | BIT_AC_READ_PTR(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXRPT_CTRL\t\t\t\t(Offset 0x047C) */\n\n#define BIT_SHIFT_TRXRPT_READ_PTR 8\n#define BIT_MASK_TRXRPT_READ_PTR 0xff\n#define BIT_TRXRPT_READ_PTR(x)                                                 \\\n\t(((x) & BIT_MASK_TRXRPT_READ_PTR) << BIT_SHIFT_TRXRPT_READ_PTR)\n#define BITS_TRXRPT_READ_PTR                                                   \\\n\t(BIT_MASK_TRXRPT_READ_PTR << BIT_SHIFT_TRXRPT_READ_PTR)\n#define BIT_CLEAR_TRXRPT_READ_PTR(x) ((x) & (~BITS_TRXRPT_READ_PTR))\n#define BIT_GET_TRXRPT_READ_PTR(x)                                             \\\n\t(((x) >> BIT_SHIFT_TRXRPT_READ_PTR) & BIT_MASK_TRXRPT_READ_PTR)\n#define BIT_SET_TRXRPT_READ_PTR(x, v)                                          \\\n\t(BIT_CLEAR_TRXRPT_READ_PTR(x) | BIT_TRXRPT_READ_PTR(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXRPT_CTRL\t\t\t\t(Offset 0x047C) */\n\n#define BIT_SHIFT_AC_WRITE_PTR 0\n#define BIT_MASK_AC_WRITE_PTR 0xf\n#define BIT_AC_WRITE_PTR(x)                                                    \\\n\t(((x) & BIT_MASK_AC_WRITE_PTR) << BIT_SHIFT_AC_WRITE_PTR)\n#define BITS_AC_WRITE_PTR (BIT_MASK_AC_WRITE_PTR << BIT_SHIFT_AC_WRITE_PTR)\n#define BIT_CLEAR_AC_WRITE_PTR(x) ((x) & (~BITS_AC_WRITE_PTR))\n#define BIT_GET_AC_WRITE_PTR(x)                                                \\\n\t(((x) >> BIT_SHIFT_AC_WRITE_PTR) & BIT_MASK_AC_WRITE_PTR)\n#define BIT_SET_AC_WRITE_PTR(x, v)                                             \\\n\t(BIT_CLEAR_AC_WRITE_PTR(x) | BIT_AC_WRITE_PTR(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXRPT_CTRL\t\t\t\t(Offset 0x047C) */\n\n#define BIT_SHIFT_TRXRPT_WRITE_PTR 0\n#define BIT_MASK_TRXRPT_WRITE_PTR 0xff\n#define BIT_TRXRPT_WRITE_PTR(x)                                                \\\n\t(((x) & BIT_MASK_TRXRPT_WRITE_PTR) << BIT_SHIFT_TRXRPT_WRITE_PTR)\n#define BITS_TRXRPT_WRITE_PTR                                                  \\\n\t(BIT_MASK_TRXRPT_WRITE_PTR << BIT_SHIFT_TRXRPT_WRITE_PTR)\n#define BIT_CLEAR_TRXRPT_WRITE_PTR(x) ((x) & (~BITS_TRXRPT_WRITE_PTR))\n#define BIT_GET_TRXRPT_WRITE_PTR(x)                                            \\\n\t(((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR) & BIT_MASK_TRXRPT_WRITE_PTR)\n#define BIT_SET_TRXRPT_WRITE_PTR(x, v)                                         \\\n\t(BIT_CLEAR_TRXRPT_WRITE_PTR(x) | BIT_TRXRPT_WRITE_PTR(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_INIRTS_RATE_SEL\t\t\t(Offset 0x0480) */\n\n#define BIT_LEAG_RTS_BW_DUP BIT(5)\n\n/* 2 REG_BASIC_CFEND_RATE\t\t\t(Offset 0x0481) */\n\n#define BIT_SHIFT_BASIC_CFEND_RATE 0\n#define BIT_MASK_BASIC_CFEND_RATE 0x1f\n#define BIT_BASIC_CFEND_RATE(x)                                                \\\n\t(((x) & BIT_MASK_BASIC_CFEND_RATE) << BIT_SHIFT_BASIC_CFEND_RATE)\n#define BITS_BASIC_CFEND_RATE                                                  \\\n\t(BIT_MASK_BASIC_CFEND_RATE << BIT_SHIFT_BASIC_CFEND_RATE)\n#define BIT_CLEAR_BASIC_CFEND_RATE(x) ((x) & (~BITS_BASIC_CFEND_RATE))\n#define BIT_GET_BASIC_CFEND_RATE(x)                                            \\\n\t(((x) >> BIT_SHIFT_BASIC_CFEND_RATE) & BIT_MASK_BASIC_CFEND_RATE)\n#define BIT_SET_BASIC_CFEND_RATE(x, v)                                         \\\n\t(BIT_CLEAR_BASIC_CFEND_RATE(x) | BIT_BASIC_CFEND_RATE(v))\n\n/* 2 REG_STBC_CFEND_RATE\t\t\t(Offset 0x0482) */\n\n#define BIT_SHIFT_STBC_CFEND_RATE 0\n#define BIT_MASK_STBC_CFEND_RATE 0x1f\n#define BIT_STBC_CFEND_RATE(x)                                                 \\\n\t(((x) & BIT_MASK_STBC_CFEND_RATE) << BIT_SHIFT_STBC_CFEND_RATE)\n#define BITS_STBC_CFEND_RATE                                                   \\\n\t(BIT_MASK_STBC_CFEND_RATE << BIT_SHIFT_STBC_CFEND_RATE)\n#define BIT_CLEAR_STBC_CFEND_RATE(x) ((x) & (~BITS_STBC_CFEND_RATE))\n#define BIT_GET_STBC_CFEND_RATE(x)                                             \\\n\t(((x) >> BIT_SHIFT_STBC_CFEND_RATE) & BIT_MASK_STBC_CFEND_RATE)\n#define BIT_SET_STBC_CFEND_RATE(x, v)                                          \\\n\t(BIT_CLEAR_STBC_CFEND_RATE(x) | BIT_STBC_CFEND_RATE(v))\n\n/* 2 REG_DATA_SC\t\t\t\t(Offset 0x0483) */\n\n#define BIT_SHIFT_TXSC_40M 4\n#define BIT_MASK_TXSC_40M 0xf\n#define BIT_TXSC_40M(x) (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M)\n#define BITS_TXSC_40M (BIT_MASK_TXSC_40M << BIT_SHIFT_TXSC_40M)\n#define BIT_CLEAR_TXSC_40M(x) ((x) & (~BITS_TXSC_40M))\n#define BIT_GET_TXSC_40M(x) (((x) >> BIT_SHIFT_TXSC_40M) & BIT_MASK_TXSC_40M)\n#define BIT_SET_TXSC_40M(x, v) (BIT_CLEAR_TXSC_40M(x) | BIT_TXSC_40M(v))\n\n#define BIT_SHIFT_TXSC_20M 0\n#define BIT_MASK_TXSC_20M 0xf\n#define BIT_TXSC_20M(x) (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M)\n#define BITS_TXSC_20M (BIT_MASK_TXSC_20M << BIT_SHIFT_TXSC_20M)\n#define BIT_CLEAR_TXSC_20M(x) ((x) & (~BITS_TXSC_20M))\n#define BIT_GET_TXSC_20M(x) (((x) >> BIT_SHIFT_TXSC_20M) & BIT_MASK_TXSC_20M)\n#define BIT_SET_TXSC_20M(x, v) (BIT_CLEAR_TXSC_20M(x) | BIT_TXSC_20M(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MACID_SLEEP3\t\t\t(Offset 0x0484) */\n\n#define BIT_SHIFT_MACID127_96_PKTSLEEP 0\n#define BIT_MASK_MACID127_96_PKTSLEEP 0xffffffffL\n#define BIT_MACID127_96_PKTSLEEP(x)                                            \\\n\t(((x) & BIT_MASK_MACID127_96_PKTSLEEP)                                 \\\n\t << BIT_SHIFT_MACID127_96_PKTSLEEP)\n#define BITS_MACID127_96_PKTSLEEP                                              \\\n\t(BIT_MASK_MACID127_96_PKTSLEEP << BIT_SHIFT_MACID127_96_PKTSLEEP)\n#define BIT_CLEAR_MACID127_96_PKTSLEEP(x) ((x) & (~BITS_MACID127_96_PKTSLEEP))\n#define BIT_GET_MACID127_96_PKTSLEEP(x)                                        \\\n\t(((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP) &                             \\\n\t BIT_MASK_MACID127_96_PKTSLEEP)\n#define BIT_SET_MACID127_96_PKTSLEEP(x, v)                                     \\\n\t(BIT_CLEAR_MACID127_96_PKTSLEEP(x) | BIT_MACID127_96_PKTSLEEP(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MACID_SLEEP3\t\t\t(Offset 0x0484) */\n\n#define BIT_SHIFT_MACID103_96_PKTSLEEP 0\n#define BIT_MASK_MACID103_96_PKTSLEEP 0xff\n#define BIT_MACID103_96_PKTSLEEP(x)                                            \\\n\t(((x) & BIT_MASK_MACID103_96_PKTSLEEP)                                 \\\n\t << BIT_SHIFT_MACID103_96_PKTSLEEP)\n#define BITS_MACID103_96_PKTSLEEP                                              \\\n\t(BIT_MASK_MACID103_96_PKTSLEEP << BIT_SHIFT_MACID103_96_PKTSLEEP)\n#define BIT_CLEAR_MACID103_96_PKTSLEEP(x) ((x) & (~BITS_MACID103_96_PKTSLEEP))\n#define BIT_GET_MACID103_96_PKTSLEEP(x)                                        \\\n\t(((x) >> BIT_SHIFT_MACID103_96_PKTSLEEP) &                             \\\n\t BIT_MASK_MACID103_96_PKTSLEEP)\n#define BIT_SET_MACID103_96_PKTSLEEP(x, v)                                     \\\n\t(BIT_CLEAR_MACID103_96_PKTSLEEP(x) | BIT_MACID103_96_PKTSLEEP(v))\n\n/* 2 REG_MACID_SLEEP4\t\t\t(Offset 0x0485) */\n\n#define BIT_SHIFT_MACID119_104_PKTSLEEP 0\n#define BIT_MASK_MACID119_104_PKTSLEEP 0xffff\n#define BIT_MACID119_104_PKTSLEEP(x)                                           \\\n\t(((x) & BIT_MASK_MACID119_104_PKTSLEEP)                                \\\n\t << BIT_SHIFT_MACID119_104_PKTSLEEP)\n#define BITS_MACID119_104_PKTSLEEP                                             \\\n\t(BIT_MASK_MACID119_104_PKTSLEEP << BIT_SHIFT_MACID119_104_PKTSLEEP)\n#define BIT_CLEAR_MACID119_104_PKTSLEEP(x) ((x) & (~BITS_MACID119_104_PKTSLEEP))\n#define BIT_GET_MACID119_104_PKTSLEEP(x)                                       \\\n\t(((x) >> BIT_SHIFT_MACID119_104_PKTSLEEP) &                            \\\n\t BIT_MASK_MACID119_104_PKTSLEEP)\n#define BIT_SET_MACID119_104_PKTSLEEP(x, v)                                    \\\n\t(BIT_CLEAR_MACID119_104_PKTSLEEP(x) | BIT_MACID119_104_PKTSLEEP(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATA_SC1\t\t\t\t(Offset 0x0487) */\n\n#define BIT_SHIFT_TXSC_160M 4\n#define BIT_MASK_TXSC_160M 0xf\n#define BIT_TXSC_160M(x) (((x) & BIT_MASK_TXSC_160M) << BIT_SHIFT_TXSC_160M)\n#define BITS_TXSC_160M (BIT_MASK_TXSC_160M << BIT_SHIFT_TXSC_160M)\n#define BIT_CLEAR_TXSC_160M(x) ((x) & (~BITS_TXSC_160M))\n#define BIT_GET_TXSC_160M(x) (((x) >> BIT_SHIFT_TXSC_160M) & BIT_MASK_TXSC_160M)\n#define BIT_SET_TXSC_160M(x, v) (BIT_CLEAR_TXSC_160M(x) | BIT_TXSC_160M(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MACID_SLEEP5\t\t\t(Offset 0x0487) */\n\n#define BIT_SHIFT_MACID127_120_PKTSLEEP 0\n#define BIT_MASK_MACID127_120_PKTSLEEP 0xff\n#define BIT_MACID127_120_PKTSLEEP(x)                                           \\\n\t(((x) & BIT_MASK_MACID127_120_PKTSLEEP)                                \\\n\t << BIT_SHIFT_MACID127_120_PKTSLEEP)\n#define BITS_MACID127_120_PKTSLEEP                                             \\\n\t(BIT_MASK_MACID127_120_PKTSLEEP << BIT_SHIFT_MACID127_120_PKTSLEEP)\n#define BIT_CLEAR_MACID127_120_PKTSLEEP(x) ((x) & (~BITS_MACID127_120_PKTSLEEP))\n#define BIT_GET_MACID127_120_PKTSLEEP(x)                                       \\\n\t(((x) >> BIT_SHIFT_MACID127_120_PKTSLEEP) &                            \\\n\t BIT_MASK_MACID127_120_PKTSLEEP)\n#define BIT_SET_MACID127_120_PKTSLEEP(x, v)                                    \\\n\t(BIT_CLEAR_MACID127_120_PKTSLEEP(x) | BIT_MACID127_120_PKTSLEEP(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATA_SC1\t\t\t\t(Offset 0x0487) */\n\n#define BIT_SHIFT_TXSC_80M 0\n#define BIT_MASK_TXSC_80M 0xf\n#define BIT_TXSC_80M(x) (((x) & BIT_MASK_TXSC_80M) << BIT_SHIFT_TXSC_80M)\n#define BITS_TXSC_80M (BIT_MASK_TXSC_80M << BIT_SHIFT_TXSC_80M)\n#define BIT_CLEAR_TXSC_80M(x) ((x) & (~BITS_TXSC_80M))\n#define BIT_GET_TXSC_80M(x) (((x) >> BIT_SHIFT_TXSC_80M) & BIT_MASK_TXSC_80M)\n#define BIT_SET_TXSC_80M(x, v) (BIT_CLEAR_TXSC_80M(x) | BIT_TXSC_80M(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MACID_SLEEP1\t\t\t(Offset 0x0488) */\n\n#define BIT_SHIFT_MACID63_32_PKTSLEEP 0\n#define BIT_MASK_MACID63_32_PKTSLEEP 0xffffffffL\n#define BIT_MACID63_32_PKTSLEEP(x)                                             \\\n\t(((x) & BIT_MASK_MACID63_32_PKTSLEEP) << BIT_SHIFT_MACID63_32_PKTSLEEP)\n#define BITS_MACID63_32_PKTSLEEP                                               \\\n\t(BIT_MASK_MACID63_32_PKTSLEEP << BIT_SHIFT_MACID63_32_PKTSLEEP)\n#define BIT_CLEAR_MACID63_32_PKTSLEEP(x) ((x) & (~BITS_MACID63_32_PKTSLEEP))\n#define BIT_GET_MACID63_32_PKTSLEEP(x)                                         \\\n\t(((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP) & BIT_MASK_MACID63_32_PKTSLEEP)\n#define BIT_SET_MACID63_32_PKTSLEEP(x, v)                                      \\\n\t(BIT_CLEAR_MACID63_32_PKTSLEEP(x) | BIT_MACID63_32_PKTSLEEP(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ARFR2_V1\t\t\t\t(Offset 0x048C) */\n\n#define BIT_SHIFT_ARFR2_V1 0\n#define BIT_MASK_ARFR2_V1 0xffffffffffffffffL\n#define BIT_ARFR2_V1(x) (((x) & BIT_MASK_ARFR2_V1) << BIT_SHIFT_ARFR2_V1)\n#define BITS_ARFR2_V1 (BIT_MASK_ARFR2_V1 << BIT_SHIFT_ARFR2_V1)\n#define BIT_CLEAR_ARFR2_V1(x) ((x) & (~BITS_ARFR2_V1))\n#define BIT_GET_ARFR2_V1(x) (((x) >> BIT_SHIFT_ARFR2_V1) & BIT_MASK_ARFR2_V1)\n#define BIT_SET_ARFR2_V1(x, v) (BIT_CLEAR_ARFR2_V1(x) | BIT_ARFR2_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ARFR2\t\t\t\t(Offset 0x048C) */\n\n#define BIT_SHIFT_ARFRL2 0\n#define BIT_MASK_ARFRL2 0xffffffffL\n#define BIT_ARFRL2(x) (((x) & BIT_MASK_ARFRL2) << BIT_SHIFT_ARFRL2)\n#define BITS_ARFRL2 (BIT_MASK_ARFRL2 << BIT_SHIFT_ARFRL2)\n#define BIT_CLEAR_ARFRL2(x) ((x) & (~BITS_ARFRL2))\n#define BIT_GET_ARFRL2(x) (((x) >> BIT_SHIFT_ARFRL2) & BIT_MASK_ARFRL2)\n#define BIT_SET_ARFRL2(x, v) (BIT_CLEAR_ARFRL2(x) | BIT_ARFRL2(v))\n\n/* 2 REG_ARFRH2\t\t\t\t(Offset 0x0490) */\n\n#define BIT_SHIFT_ARFRH2 0\n#define BIT_MASK_ARFRH2 0xffffffffL\n#define BIT_ARFRH2(x) (((x) & BIT_MASK_ARFRH2) << BIT_SHIFT_ARFRH2)\n#define BITS_ARFRH2 (BIT_MASK_ARFRH2 << BIT_SHIFT_ARFRH2)\n#define BIT_CLEAR_ARFRH2(x) ((x) & (~BITS_ARFRH2))\n#define BIT_GET_ARFRH2(x) (((x) >> BIT_SHIFT_ARFRH2) & BIT_MASK_ARFRH2)\n#define BIT_SET_ARFRH2(x, v) (BIT_CLEAR_ARFRH2(x) | BIT_ARFRH2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ARFR3_V1\t\t\t\t(Offset 0x0494) */\n\n#define BIT_SHIFT_ARFR3_V1 0\n#define BIT_MASK_ARFR3_V1 0xffffffffffffffffL\n#define BIT_ARFR3_V1(x) (((x) & BIT_MASK_ARFR3_V1) << BIT_SHIFT_ARFR3_V1)\n#define BITS_ARFR3_V1 (BIT_MASK_ARFR3_V1 << BIT_SHIFT_ARFR3_V1)\n#define BIT_CLEAR_ARFR3_V1(x) ((x) & (~BITS_ARFR3_V1))\n#define BIT_GET_ARFR3_V1(x) (((x) >> BIT_SHIFT_ARFR3_V1) & BIT_MASK_ARFR3_V1)\n#define BIT_SET_ARFR3_V1(x, v) (BIT_CLEAR_ARFR3_V1(x) | BIT_ARFR3_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ARFR3_V1\t\t\t\t(Offset 0x0494) */\n\n#define BIT_SHIFT_ARFRL3 0\n#define BIT_MASK_ARFRL3 0xffffffffL\n#define BIT_ARFRL3(x) (((x) & BIT_MASK_ARFRL3) << BIT_SHIFT_ARFRL3)\n#define BITS_ARFRL3 (BIT_MASK_ARFRL3 << BIT_SHIFT_ARFRL3)\n#define BIT_CLEAR_ARFRL3(x) ((x) & (~BITS_ARFRL3))\n#define BIT_GET_ARFRL3(x) (((x) >> BIT_SHIFT_ARFRL3) & BIT_MASK_ARFRL3)\n#define BIT_SET_ARFRL3(x, v) (BIT_CLEAR_ARFRL3(x) | BIT_ARFRL3(v))\n\n/* 2 REG_ARFRH3_V1\t\t\t\t(Offset 0x0498) */\n\n#define BIT_SHIFT_ARFRH3 0\n#define BIT_MASK_ARFRH3 0xffffffffL\n#define BIT_ARFRH3(x) (((x) & BIT_MASK_ARFRH3) << BIT_SHIFT_ARFRH3)\n#define BITS_ARFRH3 (BIT_MASK_ARFRH3 << BIT_SHIFT_ARFRH3)\n#define BIT_CLEAR_ARFRH3(x) ((x) & (~BITS_ARFRH3))\n#define BIT_GET_ARFRH3(x) (((x) >> BIT_SHIFT_ARFRH3) & BIT_MASK_ARFRH3)\n#define BIT_SET_ARFRH3(x, v) (BIT_CLEAR_ARFRH3(x) | BIT_ARFRH3(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ARFR4\t\t\t\t(Offset 0x049C) */\n\n#define BIT_SHIFT_ARFR4 0\n#define BIT_MASK_ARFR4 0xffffffffffffffffL\n#define BIT_ARFR4(x) (((x) & BIT_MASK_ARFR4) << BIT_SHIFT_ARFR4)\n#define BITS_ARFR4 (BIT_MASK_ARFR4 << BIT_SHIFT_ARFR4)\n#define BIT_CLEAR_ARFR4(x) ((x) & (~BITS_ARFR4))\n#define BIT_GET_ARFR4(x) (((x) >> BIT_SHIFT_ARFR4) & BIT_MASK_ARFR4)\n#define BIT_SET_ARFR4(x, v) (BIT_CLEAR_ARFR4(x) | BIT_ARFR4(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ARFR4\t\t\t\t(Offset 0x049C) */\n\n#define BIT_SHIFT_ARFRL4 0\n#define BIT_MASK_ARFRL4 0xffffffffL\n#define BIT_ARFRL4(x) (((x) & BIT_MASK_ARFRL4) << BIT_SHIFT_ARFRL4)\n#define BITS_ARFRL4 (BIT_MASK_ARFRL4 << BIT_SHIFT_ARFRL4)\n#define BIT_CLEAR_ARFRL4(x) ((x) & (~BITS_ARFRL4))\n#define BIT_GET_ARFRL4(x) (((x) >> BIT_SHIFT_ARFRL4) & BIT_MASK_ARFRL4)\n#define BIT_SET_ARFRL4(x, v) (BIT_CLEAR_ARFRL4(x) | BIT_ARFRL4(v))\n\n/* 2 REG_ARFRH4\t\t\t\t(Offset 0x04A0) */\n\n#define BIT_SHIFT_ARFRH4 0\n#define BIT_MASK_ARFRH4 0xffffffffL\n#define BIT_ARFRH4(x) (((x) & BIT_MASK_ARFRH4) << BIT_SHIFT_ARFRH4)\n#define BITS_ARFRH4 (BIT_MASK_ARFRH4 << BIT_SHIFT_ARFRH4)\n#define BIT_CLEAR_ARFRH4(x) ((x) & (~BITS_ARFRH4))\n#define BIT_GET_ARFRH4(x) (((x) >> BIT_SHIFT_ARFRH4) & BIT_MASK_ARFRH4)\n#define BIT_SET_ARFRH4(x, v) (BIT_CLEAR_ARFRH4(x) | BIT_ARFRH4(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ARFR5\t\t\t\t(Offset 0x04A4) */\n\n#define BIT_SHIFT_ARFR5 0\n#define BIT_MASK_ARFR5 0xffffffffffffffffL\n#define BIT_ARFR5(x) (((x) & BIT_MASK_ARFR5) << BIT_SHIFT_ARFR5)\n#define BITS_ARFR5 (BIT_MASK_ARFR5 << BIT_SHIFT_ARFR5)\n#define BIT_CLEAR_ARFR5(x) ((x) & (~BITS_ARFR5))\n#define BIT_GET_ARFR5(x) (((x) >> BIT_SHIFT_ARFR5) & BIT_MASK_ARFR5)\n#define BIT_SET_ARFR5(x, v) (BIT_CLEAR_ARFR5(x) | BIT_ARFR5(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ARFR5\t\t\t\t(Offset 0x04A4) */\n\n#define BIT_SHIFT_ARFRL5 0\n#define BIT_MASK_ARFRL5 0xffffffffL\n#define BIT_ARFRL5(x) (((x) & BIT_MASK_ARFRL5) << BIT_SHIFT_ARFRL5)\n#define BITS_ARFRL5 (BIT_MASK_ARFRL5 << BIT_SHIFT_ARFRL5)\n#define BIT_CLEAR_ARFRL5(x) ((x) & (~BITS_ARFRL5))\n#define BIT_GET_ARFRL5(x) (((x) >> BIT_SHIFT_ARFRL5) & BIT_MASK_ARFRL5)\n#define BIT_SET_ARFRL5(x, v) (BIT_CLEAR_ARFRL5(x) | BIT_ARFRL5(v))\n\n/* 2 REG_ARFRH5\t\t\t\t(Offset 0x04A8) */\n\n#define BIT_SHIFT_ARFRH5 0\n#define BIT_MASK_ARFRH5 0xffffffffL\n#define BIT_ARFRH5(x) (((x) & BIT_MASK_ARFRH5) << BIT_SHIFT_ARFRH5)\n#define BITS_ARFRH5 (BIT_MASK_ARFRH5 << BIT_SHIFT_ARFRH5)\n#define BIT_CLEAR_ARFRH5(x) ((x) & (~BITS_ARFRH5))\n#define BIT_GET_ARFRH5(x) (((x) >> BIT_SHIFT_ARFRH5) & BIT_MASK_ARFRH5)\n#define BIT_SET_ARFRH5(x, v) (BIT_CLEAR_ARFRH5(x) | BIT_ARFRH5(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_RPTFIFO_RPTNUM_OPT BIT(31)\n\n#define BIT_SHIFT_MISSED_RPT_NUM 28\n#define BIT_MASK_MISSED_RPT_NUM 0x7\n#define BIT_MISSED_RPT_NUM(x)                                                  \\\n\t(((x) & BIT_MASK_MISSED_RPT_NUM) << BIT_SHIFT_MISSED_RPT_NUM)\n#define BITS_MISSED_RPT_NUM                                                    \\\n\t(BIT_MASK_MISSED_RPT_NUM << BIT_SHIFT_MISSED_RPT_NUM)\n#define BIT_CLEAR_MISSED_RPT_NUM(x) ((x) & (~BITS_MISSED_RPT_NUM))\n#define BIT_GET_MISSED_RPT_NUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_MISSED_RPT_NUM) & BIT_MASK_MISSED_RPT_NUM)\n#define BIT_SET_MISSED_RPT_NUM(x, v)                                           \\\n\t(BIT_CLEAR_MISSED_RPT_NUM(x) | BIT_MISSED_RPT_NUM(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_SHCUT_PARSE_DASA BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_SHIFT_INDEX_15 24\n#define BIT_MASK_INDEX_15 0xff\n#define BIT_INDEX_15(x) (((x) & BIT_MASK_INDEX_15) << BIT_SHIFT_INDEX_15)\n#define BITS_INDEX_15 (BIT_MASK_INDEX_15 << BIT_SHIFT_INDEX_15)\n#define BIT_CLEAR_INDEX_15(x) ((x) & (~BITS_INDEX_15))\n#define BIT_GET_INDEX_15(x) (((x) >> BIT_SHIFT_INDEX_15) & BIT_MASK_INDEX_15)\n#define BIT_SET_INDEX_15(x, v) (BIT_CLEAR_INDEX_15(x) | BIT_INDEX_15(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_SHIFT_LOC_AMPDU_BURST_CTRL 24\n#define BIT_MASK_LOC_AMPDU_BURST_CTRL 0xff\n#define BIT_LOC_AMPDU_BURST_CTRL(x)                                            \\\n\t(((x) & BIT_MASK_LOC_AMPDU_BURST_CTRL)                                 \\\n\t << BIT_SHIFT_LOC_AMPDU_BURST_CTRL)\n#define BITS_LOC_AMPDU_BURST_CTRL                                              \\\n\t(BIT_MASK_LOC_AMPDU_BURST_CTRL << BIT_SHIFT_LOC_AMPDU_BURST_CTRL)\n#define BIT_CLEAR_LOC_AMPDU_BURST_CTRL(x) ((x) & (~BITS_LOC_AMPDU_BURST_CTRL))\n#define BIT_GET_LOC_AMPDU_BURST_CTRL(x)                                        \\\n\t(((x) >> BIT_SHIFT_LOC_AMPDU_BURST_CTRL) &                             \\\n\t BIT_MASK_LOC_AMPDU_BURST_CTRL)\n#define BIT_SET_LOC_AMPDU_BURST_CTRL(x, v)                                     \\\n\t(BIT_CLEAR_LOC_AMPDU_BURST_CTRL(x) | BIT_LOC_AMPDU_BURST_CTRL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_SHIFT_LOC_SWPS_RPT_CTRL 24\n#define BIT_MASK_LOC_SWPS_RPT_CTRL 0xff\n#define BIT_LOC_SWPS_RPT_CTRL(x)                                               \\\n\t(((x) & BIT_MASK_LOC_SWPS_RPT_CTRL) << BIT_SHIFT_LOC_SWPS_RPT_CTRL)\n#define BITS_LOC_SWPS_RPT_CTRL                                                 \\\n\t(BIT_MASK_LOC_SWPS_RPT_CTRL << BIT_SHIFT_LOC_SWPS_RPT_CTRL)\n#define BIT_CLEAR_LOC_SWPS_RPT_CTRL(x) ((x) & (~BITS_LOC_SWPS_RPT_CTRL))\n#define BIT_GET_LOC_SWPS_RPT_CTRL(x)                                           \\\n\t(((x) >> BIT_SHIFT_LOC_SWPS_RPT_CTRL) & BIT_MASK_LOC_SWPS_RPT_CTRL)\n#define BIT_SET_LOC_SWPS_RPT_CTRL(x, v)                                        \\\n\t(BIT_CLEAR_LOC_SWPS_RPT_CTRL(x) | BIT_LOC_SWPS_RPT_CTRL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_SHCUT_BYPASS BIT(24)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_SHIFT_MACID_MURATE_OFFSET 24\n#define BIT_MASK_MACID_MURATE_OFFSET 0xff\n#define BIT_MACID_MURATE_OFFSET(x)                                             \\\n\t(((x) & BIT_MASK_MACID_MURATE_OFFSET) << BIT_SHIFT_MACID_MURATE_OFFSET)\n#define BITS_MACID_MURATE_OFFSET                                               \\\n\t(BIT_MASK_MACID_MURATE_OFFSET << BIT_SHIFT_MACID_MURATE_OFFSET)\n#define BIT_CLEAR_MACID_MURATE_OFFSET(x) ((x) & (~BITS_MACID_MURATE_OFFSET))\n#define BIT_GET_MACID_MURATE_OFFSET(x)                                         \\\n\t(((x) >> BIT_SHIFT_MACID_MURATE_OFFSET) & BIT_MASK_MACID_MURATE_OFFSET)\n#define BIT_SET_MACID_MURATE_OFFSET(x, v)                                      \\\n\t(BIT_CLEAR_MACID_MURATE_OFFSET(x) | BIT_MACID_MURATE_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET 24\n#define BIT_MASK_R_MUTAB_TXRPT_OFFSET 0xff\n#define BIT_R_MUTAB_TXRPT_OFFSET(x)                                            \\\n\t(((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET)                                 \\\n\t << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET)\n#define BITS_R_MUTAB_TXRPT_OFFSET                                              \\\n\t(BIT_MASK_R_MUTAB_TXRPT_OFFSET << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET)\n#define BIT_CLEAR_R_MUTAB_TXRPT_OFFSET(x) ((x) & (~BITS_R_MUTAB_TXRPT_OFFSET))\n#define BIT_GET_R_MUTAB_TXRPT_OFFSET(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET) &                             \\\n\t BIT_MASK_R_MUTAB_TXRPT_OFFSET)\n#define BIT_SET_R_MUTAB_TXRPT_OFFSET(x, v)                                     \\\n\t(BIT_CLEAR_R_MUTAB_TXRPT_OFFSET(x) | BIT_R_MUTAB_TXRPT_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_SHIFT_TXRPT_MISS_COUNT 17\n#define BIT_MASK_TXRPT_MISS_COUNT 0x7\n#define BIT_TXRPT_MISS_COUNT(x)                                                \\\n\t(((x) & BIT_MASK_TXRPT_MISS_COUNT) << BIT_SHIFT_TXRPT_MISS_COUNT)\n#define BITS_TXRPT_MISS_COUNT                                                  \\\n\t(BIT_MASK_TXRPT_MISS_COUNT << BIT_SHIFT_TXRPT_MISS_COUNT)\n#define BIT_CLEAR_TXRPT_MISS_COUNT(x) ((x) & (~BITS_TXRPT_MISS_COUNT))\n#define BIT_GET_TXRPT_MISS_COUNT(x)                                            \\\n\t(((x) >> BIT_SHIFT_TXRPT_MISS_COUNT) & BIT_MASK_TXRPT_MISS_COUNT)\n#define BIT_SET_TXRPT_MISS_COUNT(x, v)                                         \\\n\t(BIT_CLEAR_TXRPT_MISS_COUNT(x) | BIT_TXRPT_MISS_COUNT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_SHIFT_LOC_BCN_RPT 16\n#define BIT_MASK_LOC_BCN_RPT 0xff\n#define BIT_LOC_BCN_RPT(x)                                                     \\\n\t(((x) & BIT_MASK_LOC_BCN_RPT) << BIT_SHIFT_LOC_BCN_RPT)\n#define BITS_LOC_BCN_RPT (BIT_MASK_LOC_BCN_RPT << BIT_SHIFT_LOC_BCN_RPT)\n#define BIT_CLEAR_LOC_BCN_RPT(x) ((x) & (~BITS_LOC_BCN_RPT))\n#define BIT_GET_LOC_BCN_RPT(x)                                                 \\\n\t(((x) >> BIT_SHIFT_LOC_BCN_RPT) & BIT_MASK_LOC_BCN_RPT)\n#define BIT_SET_LOC_BCN_RPT(x, v)                                              \\\n\t(BIT_CLEAR_LOC_BCN_RPT(x) | BIT_LOC_BCN_RPT(v))\n\n#define BIT_SHIFT_INDEX_14 16\n#define BIT_MASK_INDEX_14 0xff\n#define BIT_INDEX_14(x) (((x) & BIT_MASK_INDEX_14) << BIT_SHIFT_INDEX_14)\n#define BITS_INDEX_14 (BIT_MASK_INDEX_14 << BIT_SHIFT_INDEX_14)\n#define BIT_CLEAR_INDEX_14(x) ((x) & (~BITS_INDEX_14))\n#define BIT_GET_INDEX_14(x) (((x) >> BIT_SHIFT_INDEX_14) & BIT_MASK_INDEX_14)\n#define BIT_SET_INDEX_14(x, v) (BIT_CLEAR_INDEX_14(x) | BIT_INDEX_14(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT__R_RPTFIFO_1K BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_RPTFIFO_SIZE_OPT BIT(16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_SHIFT_MACID_SHCUT_OFFSET 16\n#define BIT_MASK_MACID_SHCUT_OFFSET 0xff\n#define BIT_MACID_SHCUT_OFFSET(x)                                              \\\n\t(((x) & BIT_MASK_MACID_SHCUT_OFFSET) << BIT_SHIFT_MACID_SHCUT_OFFSET)\n#define BITS_MACID_SHCUT_OFFSET                                                \\\n\t(BIT_MASK_MACID_SHCUT_OFFSET << BIT_SHIFT_MACID_SHCUT_OFFSET)\n#define BIT_CLEAR_MACID_SHCUT_OFFSET(x) ((x) & (~BITS_MACID_SHCUT_OFFSET))\n#define BIT_GET_MACID_SHCUT_OFFSET(x)                                          \\\n\t(((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET) & BIT_MASK_MACID_SHCUT_OFFSET)\n#define BIT_SET_MACID_SHCUT_OFFSET(x, v)                                       \\\n\t(BIT_CLEAR_MACID_SHCUT_OFFSET(x) | BIT_MACID_SHCUT_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_SHIFT_MACID_CTRL_OFFSET_V1 16\n#define BIT_MASK_MACID_CTRL_OFFSET_V1 0x1ff\n#define BIT_MACID_CTRL_OFFSET_V1(x)                                            \\\n\t(((x) & BIT_MASK_MACID_CTRL_OFFSET_V1)                                 \\\n\t << BIT_SHIFT_MACID_CTRL_OFFSET_V1)\n#define BITS_MACID_CTRL_OFFSET_V1                                              \\\n\t(BIT_MASK_MACID_CTRL_OFFSET_V1 << BIT_SHIFT_MACID_CTRL_OFFSET_V1)\n#define BIT_CLEAR_MACID_CTRL_OFFSET_V1(x) ((x) & (~BITS_MACID_CTRL_OFFSET_V1))\n#define BIT_GET_MACID_CTRL_OFFSET_V1(x)                                        \\\n\t(((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_V1) &                             \\\n\t BIT_MASK_MACID_CTRL_OFFSET_V1)\n#define BIT_SET_MACID_CTRL_OFFSET_V1(x, v)                                     \\\n\t(BIT_CLEAR_MACID_CTRL_OFFSET_V1(x) | BIT_MACID_CTRL_OFFSET_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_SHIFT_LOC_TXRPT 8\n#define BIT_MASK_LOC_TXRPT 0xff\n#define BIT_LOC_TXRPT(x) (((x) & BIT_MASK_LOC_TXRPT) << BIT_SHIFT_LOC_TXRPT)\n#define BITS_LOC_TXRPT (BIT_MASK_LOC_TXRPT << BIT_SHIFT_LOC_TXRPT)\n#define BIT_CLEAR_LOC_TXRPT(x) ((x) & (~BITS_LOC_TXRPT))\n#define BIT_GET_LOC_TXRPT(x) (((x) >> BIT_SHIFT_LOC_TXRPT) & BIT_MASK_LOC_TXRPT)\n#define BIT_SET_LOC_TXRPT(x, v) (BIT_CLEAR_LOC_TXRPT(x) | BIT_LOC_TXRPT(v))\n\n#define BIT_SHIFT_INDEX_13 8\n#define BIT_MASK_INDEX_13 0xff\n#define BIT_INDEX_13(x) (((x) & BIT_MASK_INDEX_13) << BIT_SHIFT_INDEX_13)\n#define BITS_INDEX_13 (BIT_MASK_INDEX_13 << BIT_SHIFT_INDEX_13)\n#define BIT_CLEAR_INDEX_13(x) ((x) & (~BITS_INDEX_13))\n#define BIT_GET_INDEX_13(x) (((x) >> BIT_SHIFT_INDEX_13) & BIT_MASK_INDEX_13)\n#define BIT_SET_INDEX_13(x, v) (BIT_CLEAR_INDEX_13(x) | BIT_INDEX_13(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_SHIFT_MACID_CTRL_OFFSET 8\n#define BIT_MASK_MACID_CTRL_OFFSET 0xff\n#define BIT_MACID_CTRL_OFFSET(x)                                               \\\n\t(((x) & BIT_MASK_MACID_CTRL_OFFSET) << BIT_SHIFT_MACID_CTRL_OFFSET)\n#define BITS_MACID_CTRL_OFFSET                                                 \\\n\t(BIT_MASK_MACID_CTRL_OFFSET << BIT_SHIFT_MACID_CTRL_OFFSET)\n#define BIT_CLEAR_MACID_CTRL_OFFSET(x) ((x) & (~BITS_MACID_CTRL_OFFSET))\n#define BIT_GET_MACID_CTRL_OFFSET(x)                                           \\\n\t(((x) >> BIT_SHIFT_MACID_CTRL_OFFSET) & BIT_MASK_MACID_CTRL_OFFSET)\n#define BIT_SET_MACID_CTRL_OFFSET(x, v)                                        \\\n\t(BIT_CLEAR_MACID_CTRL_OFFSET(x) | BIT_MACID_CTRL_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_SHIFT_LOC_SRFF 0\n#define BIT_MASK_LOC_SRFF 0xff\n#define BIT_LOC_SRFF(x) (((x) & BIT_MASK_LOC_SRFF) << BIT_SHIFT_LOC_SRFF)\n#define BITS_LOC_SRFF (BIT_MASK_LOC_SRFF << BIT_SHIFT_LOC_SRFF)\n#define BIT_CLEAR_LOC_SRFF(x) ((x) & (~BITS_LOC_SRFF))\n#define BIT_GET_LOC_SRFF(x) (((x) >> BIT_SHIFT_LOC_SRFF) & BIT_MASK_LOC_SRFF)\n#define BIT_SET_LOC_SRFF(x, v) (BIT_CLEAR_LOC_SRFF(x) | BIT_LOC_SRFF(v))\n\n#define BIT_SHIFT_INDEX_12 0\n#define BIT_MASK_INDEX_12 0xff\n#define BIT_INDEX_12(x) (((x) & BIT_MASK_INDEX_12) << BIT_SHIFT_INDEX_12)\n#define BITS_INDEX_12 (BIT_MASK_INDEX_12 << BIT_SHIFT_INDEX_12)\n#define BIT_CLEAR_INDEX_12(x) ((x) & (~BITS_INDEX_12))\n#define BIT_GET_INDEX_12(x) (((x) >> BIT_SHIFT_INDEX_12) & BIT_MASK_INDEX_12)\n#define BIT_SET_INDEX_12(x, v) (BIT_CLEAR_INDEX_12(x) | BIT_INDEX_12(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT 0\n#define BIT_MASK_RA_TRY_RATE_AGG_LMT 0x1f\n#define BIT_RA_TRY_RATE_AGG_LMT(x)                                             \\\n\t(((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT)\n#define BITS_RA_TRY_RATE_AGG_LMT                                               \\\n\t(BIT_MASK_RA_TRY_RATE_AGG_LMT << BIT_SHIFT_RA_TRY_RATE_AGG_LMT)\n#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT(x) ((x) & (~BITS_RA_TRY_RATE_AGG_LMT))\n#define BIT_GET_RA_TRY_RATE_AGG_LMT(x)                                         \\\n\t(((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT) & BIT_MASK_RA_TRY_RATE_AGG_LMT)\n#define BIT_SET_RA_TRY_RATE_AGG_LMT(x, v)                                      \\\n\t(BIT_CLEAR_RA_TRY_RATE_AGG_LMT(x) | BIT_RA_TRY_RATE_AGG_LMT(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_SHIFT_AMPDU_TXRPT_OFFSET 0\n#define BIT_MASK_AMPDU_TXRPT_OFFSET 0xff\n#define BIT_AMPDU_TXRPT_OFFSET(x)                                              \\\n\t(((x) & BIT_MASK_AMPDU_TXRPT_OFFSET) << BIT_SHIFT_AMPDU_TXRPT_OFFSET)\n#define BITS_AMPDU_TXRPT_OFFSET                                                \\\n\t(BIT_MASK_AMPDU_TXRPT_OFFSET << BIT_SHIFT_AMPDU_TXRPT_OFFSET)\n#define BIT_CLEAR_AMPDU_TXRPT_OFFSET(x) ((x) & (~BITS_AMPDU_TXRPT_OFFSET))\n#define BIT_GET_AMPDU_TXRPT_OFFSET(x)                                          \\\n\t(((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET) & BIT_MASK_AMPDU_TXRPT_OFFSET)\n#define BIT_SET_AMPDU_TXRPT_OFFSET(x, v)                                       \\\n\t(BIT_CLEAR_AMPDU_TXRPT_OFFSET(x) | BIT_AMPDU_TXRPT_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXRPT_START_OFFSET\t\t\t(Offset 0x04AC) */\n\n#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1 0\n#define BIT_MASK_AMPDU_TXRPT_OFFSET_V1 0x1ff\n#define BIT_AMPDU_TXRPT_OFFSET_V1(x)                                           \\\n\t(((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_V1)                                \\\n\t << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1)\n#define BITS_AMPDU_TXRPT_OFFSET_V1                                             \\\n\t(BIT_MASK_AMPDU_TXRPT_OFFSET_V1 << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1)\n#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1(x) ((x) & (~BITS_AMPDU_TXRPT_OFFSET_V1))\n#define BIT_GET_AMPDU_TXRPT_OFFSET_V1(x)                                       \\\n\t(((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1) &                            \\\n\t BIT_MASK_AMPDU_TXRPT_OFFSET_V1)\n#define BIT_SET_AMPDU_TXRPT_OFFSET_V1(x, v)                                    \\\n\t(BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1(x) | BIT_AMPDU_TXRPT_OFFSET_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n/* 2 REG_RRSR_CTS\t\t\t\t(Offset 0x04B0) */\n\n#define BIT_SHIFT_RRCTSSR_RSC 21\n#define BIT_MASK_RRCTSSR_RSC 0x3\n#define BIT_RRCTSSR_RSC(x)                                                     \\\n\t(((x) & BIT_MASK_RRCTSSR_RSC) << BIT_SHIFT_RRCTSSR_RSC)\n#define BITS_RRCTSSR_RSC (BIT_MASK_RRCTSSR_RSC << BIT_SHIFT_RRCTSSR_RSC)\n#define BIT_CLEAR_RRCTSSR_RSC(x) ((x) & (~BITS_RRCTSSR_RSC))\n#define BIT_GET_RRCTSSR_RSC(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RRCTSSR_RSC) & BIT_MASK_RRCTSSR_RSC)\n#define BIT_SET_RRCTSSR_RSC(x, v)                                              \\\n\t(BIT_CLEAR_RRCTSSR_RSC(x) | BIT_RRCTSSR_RSC(v))\n\n#define BIT_SHIFT_RRCTSSC_BITMAP 0\n#define BIT_MASK_RRCTSSC_BITMAP 0xfffff\n#define BIT_RRCTSSC_BITMAP(x)                                                  \\\n\t(((x) & BIT_MASK_RRCTSSC_BITMAP) << BIT_SHIFT_RRCTSSC_BITMAP)\n#define BITS_RRCTSSC_BITMAP                                                    \\\n\t(BIT_MASK_RRCTSSC_BITMAP << BIT_SHIFT_RRCTSSC_BITMAP)\n#define BIT_CLEAR_RRCTSSC_BITMAP(x) ((x) & (~BITS_RRCTSSC_BITMAP))\n#define BIT_GET_RRCTSSC_BITMAP(x)                                              \\\n\t(((x) >> BIT_SHIFT_RRCTSSC_BITMAP) & BIT_MASK_RRCTSSC_BITMAP)\n#define BIT_SET_RRCTSSC_BITMAP(x, v)                                           \\\n\t(BIT_CLEAR_RRCTSSC_BITMAP(x) | BIT_RRCTSSC_BITMAP(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_POWER_STAGE1\t\t\t(Offset 0x04B4) */\n\n#define BIT_PTA_WL_PRI_MASK_CPU_MGQ BIT(31)\n#define BIT_PTA_WL_PRI_MASK_BCNQ BIT(30)\n#define BIT_PTA_WL_PRI_MASK_HIQ BIT(29)\n#define BIT_PTA_WL_PRI_MASK_MGQ BIT(28)\n#define BIT_PTA_WL_PRI_MASK_BK BIT(27)\n#define BIT_PTA_WL_PRI_MASK_BE BIT(26)\n#define BIT_PTA_WL_PRI_MASK_VI BIT(25)\n#define BIT_PTA_WL_PRI_MASK_VO BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_POWER_STAGE1\t\t\t(Offset 0x04B4) */\n\n#define BIT_SHIFT_POWER_STAGE1 0\n#define BIT_MASK_POWER_STAGE1 0xffffff\n#define BIT_POWER_STAGE1(x)                                                    \\\n\t(((x) & BIT_MASK_POWER_STAGE1) << BIT_SHIFT_POWER_STAGE1)\n#define BITS_POWER_STAGE1 (BIT_MASK_POWER_STAGE1 << BIT_SHIFT_POWER_STAGE1)\n#define BIT_CLEAR_POWER_STAGE1(x) ((x) & (~BITS_POWER_STAGE1))\n#define BIT_GET_POWER_STAGE1(x)                                                \\\n\t(((x) >> BIT_SHIFT_POWER_STAGE1) & BIT_MASK_POWER_STAGE1)\n#define BIT_SET_POWER_STAGE1(x, v)                                             \\\n\t(BIT_CLEAR_POWER_STAGE1(x) | BIT_POWER_STAGE1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_POWER_STAGE2\t\t\t(Offset 0x04B8) */\n\n#define BIT_SHIFT_EVTQ_TXRPT 27\n#define BIT_MASK_EVTQ_TXRPT 0x7\n#define BIT_EVTQ_TXRPT(x) (((x) & BIT_MASK_EVTQ_TXRPT) << BIT_SHIFT_EVTQ_TXRPT)\n#define BITS_EVTQ_TXRPT (BIT_MASK_EVTQ_TXRPT << BIT_SHIFT_EVTQ_TXRPT)\n#define BIT_CLEAR_EVTQ_TXRPT(x) ((x) & (~BITS_EVTQ_TXRPT))\n#define BIT_GET_EVTQ_TXRPT(x)                                                  \\\n\t(((x) >> BIT_SHIFT_EVTQ_TXRPT) & BIT_MASK_EVTQ_TXRPT)\n#define BIT_SET_EVTQ_TXRPT(x, v) (BIT_CLEAR_EVTQ_TXRPT(x) | BIT_EVTQ_TXRPT(v))\n\n#define BIT_PTA_WL_PRI_MASK_EVT BIT(25)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_POWER_STAGE2\t\t\t(Offset 0x04B8) */\n\n#define BIT__CTRL_PKT_POW_ADJ BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_POWER_STAGE2\t\t\t(Offset 0x04B8) */\n\n#define BIT__R_CTRL_PKT_POW_ADJ BIT(24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_POWER_STAGE2\t\t\t(Offset 0x04B8) */\n\n#define BIT_SHIFT_POWER_STAGE2 0\n#define BIT_MASK_POWER_STAGE2 0xffffff\n#define BIT_POWER_STAGE2(x)                                                    \\\n\t(((x) & BIT_MASK_POWER_STAGE2) << BIT_SHIFT_POWER_STAGE2)\n#define BITS_POWER_STAGE2 (BIT_MASK_POWER_STAGE2 << BIT_SHIFT_POWER_STAGE2)\n#define BIT_CLEAR_POWER_STAGE2(x) ((x) & (~BITS_POWER_STAGE2))\n#define BIT_GET_POWER_STAGE2(x)                                                \\\n\t(((x) >> BIT_SHIFT_POWER_STAGE2) & BIT_MASK_POWER_STAGE2)\n#define BIT_SET_POWER_STAGE2(x, v)                                             \\\n\t(BIT_CLEAR_POWER_STAGE2(x) | BIT_POWER_STAGE2(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL\t\t(Offset 0x04BC) */\n\n#define BIT_SHIFT_EVTQ_HEAD 24\n#define BIT_MASK_EVTQ_HEAD 0xff\n#define BIT_EVTQ_HEAD(x) (((x) & BIT_MASK_EVTQ_HEAD) << BIT_SHIFT_EVTQ_HEAD)\n#define BITS_EVTQ_HEAD (BIT_MASK_EVTQ_HEAD << BIT_SHIFT_EVTQ_HEAD)\n#define BIT_CLEAR_EVTQ_HEAD(x) ((x) & (~BITS_EVTQ_HEAD))\n#define BIT_GET_EVTQ_HEAD(x) (((x) >> BIT_SHIFT_EVTQ_HEAD) & BIT_MASK_EVTQ_HEAD)\n#define BIT_SET_EVTQ_HEAD(x, v) (BIT_CLEAR_EVTQ_HEAD(x) | BIT_EVTQ_HEAD(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL\t\t(Offset 0x04BC) */\n\n#define BIT_SHIFT_PAD_NUM_THRES 24\n#define BIT_MASK_PAD_NUM_THRES 0x3f\n#define BIT_PAD_NUM_THRES(x)                                                   \\\n\t(((x) & BIT_MASK_PAD_NUM_THRES) << BIT_SHIFT_PAD_NUM_THRES)\n#define BITS_PAD_NUM_THRES (BIT_MASK_PAD_NUM_THRES << BIT_SHIFT_PAD_NUM_THRES)\n#define BIT_CLEAR_PAD_NUM_THRES(x) ((x) & (~BITS_PAD_NUM_THRES))\n#define BIT_GET_PAD_NUM_THRES(x)                                               \\\n\t(((x) >> BIT_SHIFT_PAD_NUM_THRES) & BIT_MASK_PAD_NUM_THRES)\n#define BIT_SET_PAD_NUM_THRES(x, v)                                            \\\n\t(BIT_CLEAR_PAD_NUM_THRES(x) | BIT_PAD_NUM_THRES(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL\t\t(Offset 0x04BC) */\n\n#define BIT_R_DMA_THIS_QUEUE_BK BIT(23)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL\t\t(Offset 0x04BC) */\n\n#define BIT_DMA_THIS_QUEUE_BK BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL\t\t(Offset 0x04BC) */\n\n#define BIT_R_DMA_THIS_QUEUE_BE BIT(22)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL\t\t(Offset 0x04BC) */\n\n#define BIT_DMA_THIS_QUEUE_BE BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL\t\t(Offset 0x04BC) */\n\n#define BIT_R_DMA_THIS_QUEUE_VI BIT(21)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL\t\t(Offset 0x04BC) */\n\n#define BIT_DMA_THIS_QUEUE_VI BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL\t\t(Offset 0x04BC) */\n\n#define BIT_R_DMA_THIS_QUEUE_VO BIT(20)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL\t\t(Offset 0x04BC) */\n\n#define BIT_DMA_THIS_QUEUE_VO BIT(20)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL\t\t(Offset 0x04BC) */\n\n#define BIT_SHIFT_R_TOTAL_LEN_TH 8\n#define BIT_MASK_R_TOTAL_LEN_TH 0xfff\n#define BIT_R_TOTAL_LEN_TH(x)                                                  \\\n\t(((x) & BIT_MASK_R_TOTAL_LEN_TH) << BIT_SHIFT_R_TOTAL_LEN_TH)\n#define BITS_R_TOTAL_LEN_TH                                                    \\\n\t(BIT_MASK_R_TOTAL_LEN_TH << BIT_SHIFT_R_TOTAL_LEN_TH)\n#define BIT_CLEAR_R_TOTAL_LEN_TH(x) ((x) & (~BITS_R_TOTAL_LEN_TH))\n#define BIT_GET_R_TOTAL_LEN_TH(x)                                              \\\n\t(((x) >> BIT_SHIFT_R_TOTAL_LEN_TH) & BIT_MASK_R_TOTAL_LEN_TH)\n#define BIT_SET_R_TOTAL_LEN_TH(x, v)                                           \\\n\t(BIT_CLEAR_R_TOTAL_LEN_TH(x) | BIT_R_TOTAL_LEN_TH(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL\t\t(Offset 0x04BC) */\n\n#define BIT_SHIFT_TOTAL_LEN_TH 8\n#define BIT_MASK_TOTAL_LEN_TH 0xfff\n#define BIT_TOTAL_LEN_TH(x)                                                    \\\n\t(((x) & BIT_MASK_TOTAL_LEN_TH) << BIT_SHIFT_TOTAL_LEN_TH)\n#define BITS_TOTAL_LEN_TH (BIT_MASK_TOTAL_LEN_TH << BIT_SHIFT_TOTAL_LEN_TH)\n#define BIT_CLEAR_TOTAL_LEN_TH(x) ((x) & (~BITS_TOTAL_LEN_TH))\n#define BIT_GET_TOTAL_LEN_TH(x)                                                \\\n\t(((x) >> BIT_SHIFT_TOTAL_LEN_TH) & BIT_MASK_TOTAL_LEN_TH)\n#define BIT_SET_TOTAL_LEN_TH(x, v)                                             \\\n\t(BIT_CLEAR_TOTAL_LEN_TH(x) | BIT_TOTAL_LEN_TH(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL\t\t(Offset 0x04BC) */\n\n#define BIT_WEP_PRETX_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL\t\t(Offset 0x04BC) */\n\n#define BIT_EN_NEW_EARLY BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL\t\t(Offset 0x04BC) */\n\n#define BIT_PRE_TX_CMD BIT(6)\n\n#define BIT_SHIFT_NUM_SCL_EN 4\n#define BIT_MASK_NUM_SCL_EN 0x3\n#define BIT_NUM_SCL_EN(x) (((x) & BIT_MASK_NUM_SCL_EN) << BIT_SHIFT_NUM_SCL_EN)\n#define BITS_NUM_SCL_EN (BIT_MASK_NUM_SCL_EN << BIT_SHIFT_NUM_SCL_EN)\n#define BIT_CLEAR_NUM_SCL_EN(x) ((x) & (~BITS_NUM_SCL_EN))\n#define BIT_GET_NUM_SCL_EN(x)                                                  \\\n\t(((x) >> BIT_SHIFT_NUM_SCL_EN) & BIT_MASK_NUM_SCL_EN)\n#define BIT_SET_NUM_SCL_EN(x, v) (BIT_CLEAR_NUM_SCL_EN(x) | BIT_NUM_SCL_EN(v))\n\n#define BIT_BK_EN BIT(3)\n#define BIT_BE_EN BIT(2)\n#define BIT_VI_EN BIT(1)\n#define BIT_VO_EN BIT(0)\n\n/* 2 REG_PKT_LIFE_TIME\t\t\t(Offset 0x04C0) */\n\n#define BIT_SHIFT_PKT_LIFTIME_BEBK 16\n#define BIT_MASK_PKT_LIFTIME_BEBK 0xffff\n#define BIT_PKT_LIFTIME_BEBK(x)                                                \\\n\t(((x) & BIT_MASK_PKT_LIFTIME_BEBK) << BIT_SHIFT_PKT_LIFTIME_BEBK)\n#define BITS_PKT_LIFTIME_BEBK                                                  \\\n\t(BIT_MASK_PKT_LIFTIME_BEBK << BIT_SHIFT_PKT_LIFTIME_BEBK)\n#define BIT_CLEAR_PKT_LIFTIME_BEBK(x) ((x) & (~BITS_PKT_LIFTIME_BEBK))\n#define BIT_GET_PKT_LIFTIME_BEBK(x)                                            \\\n\t(((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK) & BIT_MASK_PKT_LIFTIME_BEBK)\n#define BIT_SET_PKT_LIFTIME_BEBK(x, v)                                         \\\n\t(BIT_CLEAR_PKT_LIFTIME_BEBK(x) | BIT_PKT_LIFTIME_BEBK(v))\n\n#define BIT_SHIFT_PKT_LIFTIME_VOVI 0\n#define BIT_MASK_PKT_LIFTIME_VOVI 0xffff\n#define BIT_PKT_LIFTIME_VOVI(x)                                                \\\n\t(((x) & BIT_MASK_PKT_LIFTIME_VOVI) << BIT_SHIFT_PKT_LIFTIME_VOVI)\n#define BITS_PKT_LIFTIME_VOVI                                                  \\\n\t(BIT_MASK_PKT_LIFTIME_VOVI << BIT_SHIFT_PKT_LIFTIME_VOVI)\n#define BIT_CLEAR_PKT_LIFTIME_VOVI(x) ((x) & (~BITS_PKT_LIFTIME_VOVI))\n#define BIT_GET_PKT_LIFTIME_VOVI(x)                                            \\\n\t(((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI) & BIT_MASK_PKT_LIFTIME_VOVI)\n#define BIT_SET_PKT_LIFTIME_VOVI(x, v)                                         \\\n\t(BIT_CLEAR_PKT_LIFTIME_VOVI(x) | BIT_PKT_LIFTIME_VOVI(v))\n\n/* 2 REG_STBC_SETTING\t\t\t(Offset 0x04C4) */\n\n#define BIT_SHIFT_CDEND_TXTIME_L 4\n#define BIT_MASK_CDEND_TXTIME_L 0xf\n#define BIT_CDEND_TXTIME_L(x)                                                  \\\n\t(((x) & BIT_MASK_CDEND_TXTIME_L) << BIT_SHIFT_CDEND_TXTIME_L)\n#define BITS_CDEND_TXTIME_L                                                    \\\n\t(BIT_MASK_CDEND_TXTIME_L << BIT_SHIFT_CDEND_TXTIME_L)\n#define BIT_CLEAR_CDEND_TXTIME_L(x) ((x) & (~BITS_CDEND_TXTIME_L))\n#define BIT_GET_CDEND_TXTIME_L(x)                                              \\\n\t(((x) >> BIT_SHIFT_CDEND_TXTIME_L) & BIT_MASK_CDEND_TXTIME_L)\n#define BIT_SET_CDEND_TXTIME_L(x, v)                                           \\\n\t(BIT_CLEAR_CDEND_TXTIME_L(x) | BIT_CDEND_TXTIME_L(v))\n\n#define BIT_SHIFT_NESS 2\n#define BIT_MASK_NESS 0x3\n#define BIT_NESS(x) (((x) & BIT_MASK_NESS) << BIT_SHIFT_NESS)\n#define BITS_NESS (BIT_MASK_NESS << BIT_SHIFT_NESS)\n#define BIT_CLEAR_NESS(x) ((x) & (~BITS_NESS))\n#define BIT_GET_NESS(x) (((x) >> BIT_SHIFT_NESS) & BIT_MASK_NESS)\n#define BIT_SET_NESS(x, v) (BIT_CLEAR_NESS(x) | BIT_NESS(v))\n\n#define BIT_SHIFT_STBC_CFEND 0\n#define BIT_MASK_STBC_CFEND 0x3\n#define BIT_STBC_CFEND(x) (((x) & BIT_MASK_STBC_CFEND) << BIT_SHIFT_STBC_CFEND)\n#define BITS_STBC_CFEND (BIT_MASK_STBC_CFEND << BIT_SHIFT_STBC_CFEND)\n#define BIT_CLEAR_STBC_CFEND(x) ((x) & (~BITS_STBC_CFEND))\n#define BIT_GET_STBC_CFEND(x)                                                  \\\n\t(((x) >> BIT_SHIFT_STBC_CFEND) & BIT_MASK_STBC_CFEND)\n#define BIT_SET_STBC_CFEND(x, v) (BIT_CLEAR_STBC_CFEND(x) | BIT_STBC_CFEND(v))\n\n/* 2 REG_STBC_SETTING2\t\t\t(Offset 0x04C5) */\n\n#define BIT_SHIFT_CDEND_TXTIME_H 0\n#define BIT_MASK_CDEND_TXTIME_H 0x1f\n#define BIT_CDEND_TXTIME_H(x)                                                  \\\n\t(((x) & BIT_MASK_CDEND_TXTIME_H) << BIT_SHIFT_CDEND_TXTIME_H)\n#define BITS_CDEND_TXTIME_H                                                    \\\n\t(BIT_MASK_CDEND_TXTIME_H << BIT_SHIFT_CDEND_TXTIME_H)\n#define BIT_CLEAR_CDEND_TXTIME_H(x) ((x) & (~BITS_CDEND_TXTIME_H))\n#define BIT_GET_CDEND_TXTIME_H(x)                                              \\\n\t(((x) >> BIT_SHIFT_CDEND_TXTIME_H) & BIT_MASK_CDEND_TXTIME_H)\n#define BIT_SET_CDEND_TXTIME_H(x, v)                                           \\\n\t(BIT_CLEAR_CDEND_TXTIME_H(x) | BIT_CDEND_TXTIME_H(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_QUEUE_CTRL\t\t\t\t(Offset 0x04C6) */\n\n#define BIT_FORCE_RND_PRI BIT(6)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_QUEUE_CTRL\t\t\t\t(Offset 0x04C6) */\n\n#define BIT_R_FORCE_RND_PRI BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_QUEUE_CTRL\t\t\t\t(Offset 0x04C6) */\n\n#define BIT_PTA_EDCCA_EN BIT(5)\n#define BIT_PTA_WL_TX_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_QUEUE_CTRL\t\t\t\t(Offset 0x04C6) */\n\n#define BIT_R_USE_DATA_BW BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_QUEUE_CTRL\t\t\t\t(Offset 0x04C6) */\n\n#define BIT_USE_DATA_BW BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_QUEUE_CTRL\t\t\t\t(Offset 0x04C6) */\n\n#define BIT_TRI_PKT_INT_MODE1 BIT(2)\n#define BIT_TRI_PKT_INT_MODE0 BIT(1)\n#define BIT_ACQ_MODE_SEL BIT(0)\n\n/* 2 REG_SINGLE_AMPDU_CTRL\t\t\t(Offset 0x04C7) */\n\n#define BIT_EN_SINGLE_APMDU BIT(7)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SINGLE_AMPDU_CTRL\t\t\t(Offset 0x04C7) */\n\n#define BIT_SHIFT_SNDTX_MAXTIME 0\n#define BIT_MASK_SNDTX_MAXTIME 0x7f\n#define BIT_SNDTX_MAXTIME(x)                                                   \\\n\t(((x) & BIT_MASK_SNDTX_MAXTIME) << BIT_SHIFT_SNDTX_MAXTIME)\n#define BITS_SNDTX_MAXTIME (BIT_MASK_SNDTX_MAXTIME << BIT_SHIFT_SNDTX_MAXTIME)\n#define BIT_CLEAR_SNDTX_MAXTIME(x) ((x) & (~BITS_SNDTX_MAXTIME))\n#define BIT_GET_SNDTX_MAXTIME(x)                                               \\\n\t(((x) >> BIT_SHIFT_SNDTX_MAXTIME) & BIT_MASK_SNDTX_MAXTIME)\n#define BIT_SET_SNDTX_MAXTIME(x, v)                                            \\\n\t(BIT_CLEAR_SNDTX_MAXTIME(x) | BIT_SNDTX_MAXTIME(v))\n\n/* 2 REG_PROT_MODE_CTRL\t\t\t(Offset 0x04C8) */\n\n#define BIT_SND_SIFS_TXDATA BIT(31)\n#define BIT_TX_SND_MATCH_MACID BIT(30)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PROT_MODE_CTRL\t\t\t(Offset 0x04C8) */\n\n#define BIT_SHIFT_RTS_MAX_AGG_NUM 24\n#define BIT_MASK_RTS_MAX_AGG_NUM 0x3f\n#define BIT_RTS_MAX_AGG_NUM(x)                                                 \\\n\t(((x) & BIT_MASK_RTS_MAX_AGG_NUM) << BIT_SHIFT_RTS_MAX_AGG_NUM)\n#define BITS_RTS_MAX_AGG_NUM                                                   \\\n\t(BIT_MASK_RTS_MAX_AGG_NUM << BIT_SHIFT_RTS_MAX_AGG_NUM)\n#define BIT_CLEAR_RTS_MAX_AGG_NUM(x) ((x) & (~BITS_RTS_MAX_AGG_NUM))\n#define BIT_GET_RTS_MAX_AGG_NUM(x)                                             \\\n\t(((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM) & BIT_MASK_RTS_MAX_AGG_NUM)\n#define BIT_SET_RTS_MAX_AGG_NUM(x, v)                                          \\\n\t(BIT_CLEAR_RTS_MAX_AGG_NUM(x) | BIT_RTS_MAX_AGG_NUM(v))\n\n#define BIT_SHIFT_MAX_AGG_NUM 16\n#define BIT_MASK_MAX_AGG_NUM 0x3f\n#define BIT_MAX_AGG_NUM(x)                                                     \\\n\t(((x) & BIT_MASK_MAX_AGG_NUM) << BIT_SHIFT_MAX_AGG_NUM)\n#define BITS_MAX_AGG_NUM (BIT_MASK_MAX_AGG_NUM << BIT_SHIFT_MAX_AGG_NUM)\n#define BIT_CLEAR_MAX_AGG_NUM(x) ((x) & (~BITS_MAX_AGG_NUM))\n#define BIT_GET_MAX_AGG_NUM(x)                                                 \\\n\t(((x) >> BIT_SHIFT_MAX_AGG_NUM) & BIT_MASK_MAX_AGG_NUM)\n#define BIT_SET_MAX_AGG_NUM(x, v)                                              \\\n\t(BIT_CLEAR_MAX_AGG_NUM(x) | BIT_MAX_AGG_NUM(v))\n\n#define BIT_SHIFT_RTS_TXTIME_TH 8\n#define BIT_MASK_RTS_TXTIME_TH 0xff\n#define BIT_RTS_TXTIME_TH(x)                                                   \\\n\t(((x) & BIT_MASK_RTS_TXTIME_TH) << BIT_SHIFT_RTS_TXTIME_TH)\n#define BITS_RTS_TXTIME_TH (BIT_MASK_RTS_TXTIME_TH << BIT_SHIFT_RTS_TXTIME_TH)\n#define BIT_CLEAR_RTS_TXTIME_TH(x) ((x) & (~BITS_RTS_TXTIME_TH))\n#define BIT_GET_RTS_TXTIME_TH(x)                                               \\\n\t(((x) >> BIT_SHIFT_RTS_TXTIME_TH) & BIT_MASK_RTS_TXTIME_TH)\n#define BIT_SET_RTS_TXTIME_TH(x, v)                                            \\\n\t(BIT_CLEAR_RTS_TXTIME_TH(x) | BIT_RTS_TXTIME_TH(v))\n\n#define BIT_SHIFT_RTS_LEN_TH 0\n#define BIT_MASK_RTS_LEN_TH 0xff\n#define BIT_RTS_LEN_TH(x) (((x) & BIT_MASK_RTS_LEN_TH) << BIT_SHIFT_RTS_LEN_TH)\n#define BITS_RTS_LEN_TH (BIT_MASK_RTS_LEN_TH << BIT_SHIFT_RTS_LEN_TH)\n#define BIT_CLEAR_RTS_LEN_TH(x) ((x) & (~BITS_RTS_LEN_TH))\n#define BIT_GET_RTS_LEN_TH(x)                                                  \\\n\t(((x) >> BIT_SHIFT_RTS_LEN_TH) & BIT_MASK_RTS_LEN_TH)\n#define BIT_SET_RTS_LEN_TH(x, v) (BIT_CLEAR_RTS_LEN_TH(x) | BIT_RTS_LEN_TH(v))\n\n/* 2 REG_BAR_MODE_CTRL\t\t\t(Offset 0x04CC) */\n\n#define BIT_SHIFT_BAR_RTY_LMT 16\n#define BIT_MASK_BAR_RTY_LMT 0x3\n#define BIT_BAR_RTY_LMT(x)                                                     \\\n\t(((x) & BIT_MASK_BAR_RTY_LMT) << BIT_SHIFT_BAR_RTY_LMT)\n#define BITS_BAR_RTY_LMT (BIT_MASK_BAR_RTY_LMT << BIT_SHIFT_BAR_RTY_LMT)\n#define BIT_CLEAR_BAR_RTY_LMT(x) ((x) & (~BITS_BAR_RTY_LMT))\n#define BIT_GET_BAR_RTY_LMT(x)                                                 \\\n\t(((x) >> BIT_SHIFT_BAR_RTY_LMT) & BIT_MASK_BAR_RTY_LMT)\n#define BIT_SET_BAR_RTY_LMT(x, v)                                              \\\n\t(BIT_CLEAR_BAR_RTY_LMT(x) | BIT_BAR_RTY_LMT(v))\n\n#define BIT_SHIFT_BAR_PKT_TXTIME_TH 8\n#define BIT_MASK_BAR_PKT_TXTIME_TH 0xff\n#define BIT_BAR_PKT_TXTIME_TH(x)                                               \\\n\t(((x) & BIT_MASK_BAR_PKT_TXTIME_TH) << BIT_SHIFT_BAR_PKT_TXTIME_TH)\n#define BITS_BAR_PKT_TXTIME_TH                                                 \\\n\t(BIT_MASK_BAR_PKT_TXTIME_TH << BIT_SHIFT_BAR_PKT_TXTIME_TH)\n#define BIT_CLEAR_BAR_PKT_TXTIME_TH(x) ((x) & (~BITS_BAR_PKT_TXTIME_TH))\n#define BIT_GET_BAR_PKT_TXTIME_TH(x)                                           \\\n\t(((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH) & BIT_MASK_BAR_PKT_TXTIME_TH)\n#define BIT_SET_BAR_PKT_TXTIME_TH(x, v)                                        \\\n\t(BIT_CLEAR_BAR_PKT_TXTIME_TH(x) | BIT_BAR_PKT_TXTIME_TH(v))\n\n#define BIT_BAR_EN_V1 BIT(6)\n\n#define BIT_SHIFT_BAR_PKTNUM_TH_V1 0\n#define BIT_MASK_BAR_PKTNUM_TH_V1 0x3f\n#define BIT_BAR_PKTNUM_TH_V1(x)                                                \\\n\t(((x) & BIT_MASK_BAR_PKTNUM_TH_V1) << BIT_SHIFT_BAR_PKTNUM_TH_V1)\n#define BITS_BAR_PKTNUM_TH_V1                                                  \\\n\t(BIT_MASK_BAR_PKTNUM_TH_V1 << BIT_SHIFT_BAR_PKTNUM_TH_V1)\n#define BIT_CLEAR_BAR_PKTNUM_TH_V1(x) ((x) & (~BITS_BAR_PKTNUM_TH_V1))\n#define BIT_GET_BAR_PKTNUM_TH_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1) & BIT_MASK_BAR_PKTNUM_TH_V1)\n#define BIT_SET_BAR_PKTNUM_TH_V1(x, v)                                         \\\n\t(BIT_CLEAR_BAR_PKTNUM_TH_V1(x) | BIT_BAR_PKTNUM_TH_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RA_TRY_RATE_AGG_LMT\t\t\t(Offset 0x04CF) */\n\n#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1 0\n#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 0x3f\n#define BIT_RA_TRY_RATE_AGG_LMT_V1(x)                                          \\\n\t(((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1)                               \\\n\t << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1)\n#define BITS_RA_TRY_RATE_AGG_LMT_V1                                            \\\n\t(BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1)\n#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1(x)                                    \\\n\t((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1))\n#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1(x)                                      \\\n\t(((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) &                           \\\n\t BIT_MASK_RA_TRY_RATE_AGG_LMT_V1)\n#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1(x, v)                                   \\\n\t(BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1(x) | BIT_RA_TRY_RATE_AGG_LMT_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MACID_SLEEP_CTRL\t\t\t(Offset 0x04D0) */\n\n#define BIT_SHIFT_DEBUG_PROTOCOL 24\n#define BIT_MASK_DEBUG_PROTOCOL 0xff\n#define BIT_DEBUG_PROTOCOL(x)                                                  \\\n\t(((x) & BIT_MASK_DEBUG_PROTOCOL) << BIT_SHIFT_DEBUG_PROTOCOL)\n#define BITS_DEBUG_PROTOCOL                                                    \\\n\t(BIT_MASK_DEBUG_PROTOCOL << BIT_SHIFT_DEBUG_PROTOCOL)\n#define BIT_CLEAR_DEBUG_PROTOCOL(x) ((x) & (~BITS_DEBUG_PROTOCOL))\n#define BIT_GET_DEBUG_PROTOCOL(x)                                              \\\n\t(((x) >> BIT_SHIFT_DEBUG_PROTOCOL) & BIT_MASK_DEBUG_PROTOCOL)\n#define BIT_SET_DEBUG_PROTOCOL(x, v)                                           \\\n\t(BIT_CLEAR_DEBUG_PROTOCOL(x) | BIT_DEBUG_PROTOCOL(v))\n\n#define BIT_SHIFT_BCNQ_PGBNDY_RSEL 16\n#define BIT_MASK_BCNQ_PGBNDY_RSEL 0x7\n#define BIT_BCNQ_PGBNDY_RSEL(x)                                                \\\n\t(((x) & BIT_MASK_BCNQ_PGBNDY_RSEL) << BIT_SHIFT_BCNQ_PGBNDY_RSEL)\n#define BITS_BCNQ_PGBNDY_RSEL                                                  \\\n\t(BIT_MASK_BCNQ_PGBNDY_RSEL << BIT_SHIFT_BCNQ_PGBNDY_RSEL)\n#define BIT_CLEAR_BCNQ_PGBNDY_RSEL(x) ((x) & (~BITS_BCNQ_PGBNDY_RSEL))\n#define BIT_GET_BCNQ_PGBNDY_RSEL(x)                                            \\\n\t(((x) >> BIT_SHIFT_BCNQ_PGBNDY_RSEL) & BIT_MASK_BCNQ_PGBNDY_RSEL)\n#define BIT_SET_BCNQ_PGBNDY_RSEL(x, v)                                         \\\n\t(BIT_CLEAR_BCNQ_PGBNDY_RSEL(x) | BIT_BCNQ_PGBNDY_RSEL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MACID_SLEEP2\t\t\t(Offset 0x04D0) */\n\n#define BIT_SHIFT_MACID95_64PKTSLEEP 0\n#define BIT_MASK_MACID95_64PKTSLEEP 0xffffffffL\n#define BIT_MACID95_64PKTSLEEP(x)                                              \\\n\t(((x) & BIT_MASK_MACID95_64PKTSLEEP) << BIT_SHIFT_MACID95_64PKTSLEEP)\n#define BITS_MACID95_64PKTSLEEP                                                \\\n\t(BIT_MASK_MACID95_64PKTSLEEP << BIT_SHIFT_MACID95_64PKTSLEEP)\n#define BIT_CLEAR_MACID95_64PKTSLEEP(x) ((x) & (~BITS_MACID95_64PKTSLEEP))\n#define BIT_GET_MACID95_64PKTSLEEP(x)                                          \\\n\t(((x) >> BIT_SHIFT_MACID95_64PKTSLEEP) & BIT_MASK_MACID95_64PKTSLEEP)\n#define BIT_SET_MACID95_64PKTSLEEP(x, v)                                       \\\n\t(BIT_CLEAR_MACID95_64PKTSLEEP(x) | BIT_MACID95_64PKTSLEEP(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MACID_SLEEP_CTRL\t\t\t(Offset 0x04D0) */\n\n#define BIT_SHIFT_MACID_SLEEP_SEL 0\n#define BIT_MASK_MACID_SLEEP_SEL 0x7\n#define BIT_MACID_SLEEP_SEL(x)                                                 \\\n\t(((x) & BIT_MASK_MACID_SLEEP_SEL) << BIT_SHIFT_MACID_SLEEP_SEL)\n#define BITS_MACID_SLEEP_SEL                                                   \\\n\t(BIT_MASK_MACID_SLEEP_SEL << BIT_SHIFT_MACID_SLEEP_SEL)\n#define BIT_CLEAR_MACID_SLEEP_SEL(x) ((x) & (~BITS_MACID_SLEEP_SEL))\n#define BIT_GET_MACID_SLEEP_SEL(x)                                             \\\n\t(((x) >> BIT_SHIFT_MACID_SLEEP_SEL) & BIT_MASK_MACID_SLEEP_SEL)\n#define BIT_SET_MACID_SLEEP_SEL(x, v)                                          \\\n\t(BIT_CLEAR_MACID_SLEEP_SEL(x) | BIT_MACID_SLEEP_SEL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MACID_SLEEP\t\t\t\t(Offset 0x04D4) */\n\n#define BIT_SHIFT_MACID31_0_PKTSLEEP 0\n#define BIT_MASK_MACID31_0_PKTSLEEP 0xffffffffL\n#define BIT_MACID31_0_PKTSLEEP(x)                                              \\\n\t(((x) & BIT_MASK_MACID31_0_PKTSLEEP) << BIT_SHIFT_MACID31_0_PKTSLEEP)\n#define BITS_MACID31_0_PKTSLEEP                                                \\\n\t(BIT_MASK_MACID31_0_PKTSLEEP << BIT_SHIFT_MACID31_0_PKTSLEEP)\n#define BIT_CLEAR_MACID31_0_PKTSLEEP(x) ((x) & (~BITS_MACID31_0_PKTSLEEP))\n#define BIT_GET_MACID31_0_PKTSLEEP(x)                                          \\\n\t(((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP) & BIT_MASK_MACID31_0_PKTSLEEP)\n#define BIT_SET_MACID31_0_PKTSLEEP(x, v)                                       \\\n\t(BIT_CLEAR_MACID31_0_PKTSLEEP(x) | BIT_MACID31_0_PKTSLEEP(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MACID_SLEEP\t\t\t\t(Offset 0x04D4) */\n\n#define BIT_SHIFT_MACID31_0PKTSLEEP 0\n#define BIT_MASK_MACID31_0PKTSLEEP 0xffffffffL\n#define BIT_MACID31_0PKTSLEEP(x)                                               \\\n\t(((x) & BIT_MASK_MACID31_0PKTSLEEP) << BIT_SHIFT_MACID31_0PKTSLEEP)\n#define BITS_MACID31_0PKTSLEEP                                                 \\\n\t(BIT_MASK_MACID31_0PKTSLEEP << BIT_SHIFT_MACID31_0PKTSLEEP)\n#define BIT_CLEAR_MACID31_0PKTSLEEP(x) ((x) & (~BITS_MACID31_0PKTSLEEP))\n#define BIT_GET_MACID31_0PKTSLEEP(x)                                           \\\n\t(((x) >> BIT_SHIFT_MACID31_0PKTSLEEP) & BIT_MASK_MACID31_0PKTSLEEP)\n#define BIT_SET_MACID31_0PKTSLEEP(x, v)                                        \\\n\t(BIT_CLEAR_MACID31_0PKTSLEEP(x) | BIT_MACID31_0PKTSLEEP(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MACID_SLEEP_INFO\t\t\t(Offset 0x04D4) */\n\n#define BIT_SHIFT_MACID_SLEEP_INFO 0\n#define BIT_MASK_MACID_SLEEP_INFO 0xffffffffL\n#define BIT_MACID_SLEEP_INFO(x)                                                \\\n\t(((x) & BIT_MASK_MACID_SLEEP_INFO) << BIT_SHIFT_MACID_SLEEP_INFO)\n#define BITS_MACID_SLEEP_INFO                                                  \\\n\t(BIT_MASK_MACID_SLEEP_INFO << BIT_SHIFT_MACID_SLEEP_INFO)\n#define BIT_CLEAR_MACID_SLEEP_INFO(x) ((x) & (~BITS_MACID_SLEEP_INFO))\n#define BIT_GET_MACID_SLEEP_INFO(x)                                            \\\n\t(((x) >> BIT_SHIFT_MACID_SLEEP_INFO) & BIT_MASK_MACID_SLEEP_INFO)\n#define BIT_SET_MACID_SLEEP_INFO(x, v)                                         \\\n\t(BIT_CLEAR_MACID_SLEEP_INFO(x) | BIT_MACID_SLEEP_INFO(v))\n\n#define BIT_SHIFT_PTCL_TOTAL_PG_V3 0\n#define BIT_MASK_PTCL_TOTAL_PG_V3 0x1fff\n#define BIT_PTCL_TOTAL_PG_V3(x)                                                \\\n\t(((x) & BIT_MASK_PTCL_TOTAL_PG_V3) << BIT_SHIFT_PTCL_TOTAL_PG_V3)\n#define BITS_PTCL_TOTAL_PG_V3                                                  \\\n\t(BIT_MASK_PTCL_TOTAL_PG_V3 << BIT_SHIFT_PTCL_TOTAL_PG_V3)\n#define BIT_CLEAR_PTCL_TOTAL_PG_V3(x) ((x) & (~BITS_PTCL_TOTAL_PG_V3))\n#define BIT_GET_PTCL_TOTAL_PG_V3(x)                                            \\\n\t(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V3) & BIT_MASK_PTCL_TOTAL_PG_V3)\n#define BIT_SET_PTCL_TOTAL_PG_V3(x, v)                                         \\\n\t(BIT_CLEAR_PTCL_TOTAL_PG_V3(x) | BIT_PTCL_TOTAL_PG_V3(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HW_SEQ0\t\t\t\t(Offset 0x04D8) */\n\n#define BIT_SHIFT_HW_SSN_SEQ0 0\n#define BIT_MASK_HW_SSN_SEQ0 0xfff\n#define BIT_HW_SSN_SEQ0(x)                                                     \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ0) << BIT_SHIFT_HW_SSN_SEQ0)\n#define BITS_HW_SSN_SEQ0 (BIT_MASK_HW_SSN_SEQ0 << BIT_SHIFT_HW_SSN_SEQ0)\n#define BIT_CLEAR_HW_SSN_SEQ0(x) ((x) & (~BITS_HW_SSN_SEQ0))\n#define BIT_GET_HW_SSN_SEQ0(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ0) & BIT_MASK_HW_SSN_SEQ0)\n#define BIT_SET_HW_SSN_SEQ0(x, v)                                              \\\n\t(BIT_CLEAR_HW_SSN_SEQ0(x) | BIT_HW_SSN_SEQ0(v))\n\n/* 2 REG_HW_SEQ1\t\t\t\t(Offset 0x04DA) */\n\n#define BIT_SHIFT_HW_SSN_SEQ1 0\n#define BIT_MASK_HW_SSN_SEQ1 0xfff\n#define BIT_HW_SSN_SEQ1(x)                                                     \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ1) << BIT_SHIFT_HW_SSN_SEQ1)\n#define BITS_HW_SSN_SEQ1 (BIT_MASK_HW_SSN_SEQ1 << BIT_SHIFT_HW_SSN_SEQ1)\n#define BIT_CLEAR_HW_SSN_SEQ1(x) ((x) & (~BITS_HW_SSN_SEQ1))\n#define BIT_GET_HW_SSN_SEQ1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ1) & BIT_MASK_HW_SSN_SEQ1)\n#define BIT_SET_HW_SSN_SEQ1(x, v)                                              \\\n\t(BIT_CLEAR_HW_SSN_SEQ1(x) | BIT_HW_SSN_SEQ1(v))\n\n/* 2 REG_HW_SEQ2\t\t\t\t(Offset 0x04DC) */\n\n#define BIT_SHIFT_HW_SSN_SEQ2 0\n#define BIT_MASK_HW_SSN_SEQ2 0xfff\n#define BIT_HW_SSN_SEQ2(x)                                                     \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ2) << BIT_SHIFT_HW_SSN_SEQ2)\n#define BITS_HW_SSN_SEQ2 (BIT_MASK_HW_SSN_SEQ2 << BIT_SHIFT_HW_SSN_SEQ2)\n#define BIT_CLEAR_HW_SSN_SEQ2(x) ((x) & (~BITS_HW_SSN_SEQ2))\n#define BIT_GET_HW_SSN_SEQ2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ2) & BIT_MASK_HW_SSN_SEQ2)\n#define BIT_SET_HW_SSN_SEQ2(x, v)                                              \\\n\t(BIT_CLEAR_HW_SSN_SEQ2(x) | BIT_HW_SSN_SEQ2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HW_SEQ3\t\t\t\t(Offset 0x04DE) */\n\n#define BIT_SHIFT_CSI_HWSSN_SEL 12\n#define BIT_MASK_CSI_HWSSN_SEL 0x3\n#define BIT_CSI_HWSSN_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_CSI_HWSSN_SEL) << BIT_SHIFT_CSI_HWSSN_SEL)\n#define BITS_CSI_HWSSN_SEL (BIT_MASK_CSI_HWSSN_SEL << BIT_SHIFT_CSI_HWSSN_SEL)\n#define BIT_CLEAR_CSI_HWSSN_SEL(x) ((x) & (~BITS_CSI_HWSSN_SEL))\n#define BIT_GET_CSI_HWSSN_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_CSI_HWSSN_SEL) & BIT_MASK_CSI_HWSSN_SEL)\n#define BIT_SET_CSI_HWSSN_SEL(x, v)                                            \\\n\t(BIT_CLEAR_CSI_HWSSN_SEL(x) | BIT_CSI_HWSSN_SEL(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HW_SEQ3\t\t\t\t(Offset 0x04DE) */\n\n#define BIT_SHIFT_CSI_HWSEQ_SEL 12\n#define BIT_MASK_CSI_HWSEQ_SEL 0x3\n#define BIT_CSI_HWSEQ_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_CSI_HWSEQ_SEL) << BIT_SHIFT_CSI_HWSEQ_SEL)\n#define BITS_CSI_HWSEQ_SEL (BIT_MASK_CSI_HWSEQ_SEL << BIT_SHIFT_CSI_HWSEQ_SEL)\n#define BIT_CLEAR_CSI_HWSEQ_SEL(x) ((x) & (~BITS_CSI_HWSEQ_SEL))\n#define BIT_GET_CSI_HWSEQ_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_CSI_HWSEQ_SEL) & BIT_MASK_CSI_HWSEQ_SEL)\n#define BIT_SET_CSI_HWSEQ_SEL(x, v)                                            \\\n\t(BIT_CLEAR_CSI_HWSEQ_SEL(x) | BIT_CSI_HWSEQ_SEL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HW_SEQ3\t\t\t\t(Offset 0x04DE) */\n\n#define BIT_SHIFT_HW_SSN_SEQ3 0\n#define BIT_MASK_HW_SSN_SEQ3 0xfff\n#define BIT_HW_SSN_SEQ3(x)                                                     \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ3) << BIT_SHIFT_HW_SSN_SEQ3)\n#define BITS_HW_SSN_SEQ3 (BIT_MASK_HW_SSN_SEQ3 << BIT_SHIFT_HW_SSN_SEQ3)\n#define BIT_CLEAR_HW_SSN_SEQ3(x) ((x) & (~BITS_HW_SSN_SEQ3))\n#define BIT_GET_HW_SSN_SEQ3(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ3) & BIT_MASK_HW_SSN_SEQ3)\n#define BIT_SET_HW_SSN_SEQ3(x, v)                                              \\\n\t(BIT_CLEAR_HW_SSN_SEQ3(x) | BIT_HW_SSN_SEQ3(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_CSI_SEQ\t\t\t\t(Offset 0x04DE) */\n\n#define BIT_SHIFT_HW_CSI_SEQ 0\n#define BIT_MASK_HW_CSI_SEQ 0xfff\n#define BIT_HW_CSI_SEQ(x) (((x) & BIT_MASK_HW_CSI_SEQ) << BIT_SHIFT_HW_CSI_SEQ)\n#define BITS_HW_CSI_SEQ (BIT_MASK_HW_CSI_SEQ << BIT_SHIFT_HW_CSI_SEQ)\n#define BIT_CLEAR_HW_CSI_SEQ(x) ((x) & (~BITS_HW_CSI_SEQ))\n#define BIT_GET_HW_CSI_SEQ(x)                                                  \\\n\t(((x) >> BIT_SHIFT_HW_CSI_SEQ) & BIT_MASK_HW_CSI_SEQ)\n#define BIT_SET_HW_CSI_SEQ(x, v) (BIT_CLEAR_HW_CSI_SEQ(x) | BIT_HW_CSI_SEQ(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_NULL_PKT_STATUS_V1\t\t\t(Offset 0x04E0) */\n\n#define BIT_SHIFT_PTCL_TOTAL_PG_V1 2\n#define BIT_MASK_PTCL_TOTAL_PG_V1 0x1fff\n#define BIT_PTCL_TOTAL_PG_V1(x)                                                \\\n\t(((x) & BIT_MASK_PTCL_TOTAL_PG_V1) << BIT_SHIFT_PTCL_TOTAL_PG_V1)\n#define BITS_PTCL_TOTAL_PG_V1                                                  \\\n\t(BIT_MASK_PTCL_TOTAL_PG_V1 << BIT_SHIFT_PTCL_TOTAL_PG_V1)\n#define BIT_CLEAR_PTCL_TOTAL_PG_V1(x) ((x) & (~BITS_PTCL_TOTAL_PG_V1))\n#define BIT_GET_PTCL_TOTAL_PG_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V1) & BIT_MASK_PTCL_TOTAL_PG_V1)\n#define BIT_SET_PTCL_TOTAL_PG_V1(x, v)                                         \\\n\t(BIT_CLEAR_PTCL_TOTAL_PG_V1(x) | BIT_PTCL_TOTAL_PG_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_NULL_PKT_STATUS_V1\t\t\t(Offset 0x04E0) */\n\n#define BIT_SHIFT_PTCL_TOTAL_PG_V5 2\n#define BIT_MASK_PTCL_TOTAL_PG_V5 0x1fff\n#define BIT_PTCL_TOTAL_PG_V5(x)                                                \\\n\t(((x) & BIT_MASK_PTCL_TOTAL_PG_V5) << BIT_SHIFT_PTCL_TOTAL_PG_V5)\n#define BITS_PTCL_TOTAL_PG_V5                                                  \\\n\t(BIT_MASK_PTCL_TOTAL_PG_V5 << BIT_SHIFT_PTCL_TOTAL_PG_V5)\n#define BIT_CLEAR_PTCL_TOTAL_PG_V5(x) ((x) & (~BITS_PTCL_TOTAL_PG_V5))\n#define BIT_GET_PTCL_TOTAL_PG_V5(x)                                            \\\n\t(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V5) & BIT_MASK_PTCL_TOTAL_PG_V5)\n#define BIT_SET_PTCL_TOTAL_PG_V5(x, v)                                         \\\n\t(BIT_CLEAR_PTCL_TOTAL_PG_V5(x) | BIT_PTCL_TOTAL_PG_V5(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_NULL_PKT_STATUS_V1\t\t\t(Offset 0x04E0) */\n\n#define BIT_SHIFT_PTCL_TOTAL_PG_V2 2\n#define BIT_MASK_PTCL_TOTAL_PG_V2 0x3fff\n#define BIT_PTCL_TOTAL_PG_V2(x)                                                \\\n\t(((x) & BIT_MASK_PTCL_TOTAL_PG_V2) << BIT_SHIFT_PTCL_TOTAL_PG_V2)\n#define BITS_PTCL_TOTAL_PG_V2                                                  \\\n\t(BIT_MASK_PTCL_TOTAL_PG_V2 << BIT_SHIFT_PTCL_TOTAL_PG_V2)\n#define BIT_CLEAR_PTCL_TOTAL_PG_V2(x) ((x) & (~BITS_PTCL_TOTAL_PG_V2))\n#define BIT_GET_PTCL_TOTAL_PG_V2(x)                                            \\\n\t(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2) & BIT_MASK_PTCL_TOTAL_PG_V2)\n#define BIT_SET_PTCL_TOTAL_PG_V2(x, v)                                         \\\n\t(BIT_CLEAR_PTCL_TOTAL_PG_V2(x) | BIT_PTCL_TOTAL_PG_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_NULL_PKT_STATUS\t\t\t(Offset 0x04E0) */\n\n#define BIT_TX_NULL_1 BIT(1)\n#define BIT_TX_NULL_0 BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS_V1\t\t\t(Offset 0x04E2) */\n\n#define BIT_MUARB_SEARCH_ERR BIT(14)\n#define BIT_MU_BFEN_ERR BIT(12)\n#define BIT_NDPA_DROPNULL_ERR BIT(11)\n#define BIT_NDPA_DROPPKT_ERR BIT(10)\n#define BIT_PTCL_PKYIN_ERR BIT(9)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS_V1\t\t\t(Offset 0x04E2) */\n\n#define BIT_SHIFT_PTCL_TOTAL_PG_V4 8\n#define BIT_MASK_PTCL_TOTAL_PG_V4 0xff\n#define BIT_PTCL_TOTAL_PG_V4(x)                                                \\\n\t(((x) & BIT_MASK_PTCL_TOTAL_PG_V4) << BIT_SHIFT_PTCL_TOTAL_PG_V4)\n#define BITS_PTCL_TOTAL_PG_V4                                                  \\\n\t(BIT_MASK_PTCL_TOTAL_PG_V4 << BIT_SHIFT_PTCL_TOTAL_PG_V4)\n#define BIT_CLEAR_PTCL_TOTAL_PG_V4(x) ((x) & (~BITS_PTCL_TOTAL_PG_V4))\n#define BIT_GET_PTCL_TOTAL_PG_V4(x)                                            \\\n\t(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V4) & BIT_MASK_PTCL_TOTAL_PG_V4)\n#define BIT_SET_PTCL_TOTAL_PG_V4(x, v)                                         \\\n\t(BIT_CLEAR_PTCL_TOTAL_PG_V4(x) | BIT_PTCL_TOTAL_PG_V4(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS_V1\t\t\t(Offset 0x04E2) */\n\n#define BIT_PTCL_QSELCNL_ERR BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS_V1\t\t\t(Offset 0x04E2) */\n\n#define BIT_PTCL_TOTAL_PG_8 BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS_V1\t\t\t(Offset 0x04E2) */\n\n#define BIT_PTCL_RATE_TABLE_INVALID BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS\t\t\t(Offset 0x04E2) */\n\n#define BIT_P2P_OFF_DISTX_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS_V1\t\t\t(Offset 0x04E2) */\n\n#define BIT_PTCL_RATE_TABLE_INVALID_V1 BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS_V1\t\t\t(Offset 0x04E2) */\n\n#define BIT_FTM_T2R_ERROR BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS\t\t\t(Offset 0x04E2) */\n\n#define BIT_PTCL_ERR0 BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS_V1\t\t\t(Offset 0x04E2) */\n\n#define BIT_TXTIMEOUT_ERR BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS\t\t\t(Offset 0x04E2) */\n\n#define BIT_PTCL_ERR1 BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS_V1\t\t\t(Offset 0x04E2) */\n\n#define BIT_NULLPAGE_ERR BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS\t\t\t(Offset 0x04E2) */\n\n#define BIT_PTCL_ERR2 BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS_V1\t\t\t(Offset 0x04E2) */\n\n#define BIT_CONTENTION_ERR BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS\t\t\t(Offset 0x04E2) */\n\n#define BIT_PTCL_ERR3 BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS_V1\t\t\t(Offset 0x04E2) */\n\n#define BIT_HEADNULL_ERR BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS\t\t\t(Offset 0x04E2) */\n\n#define BIT_PTCL_ERR4 BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS_V1\t\t\t(Offset 0x04E2) */\n\n#define BIT_OVERFLOW_ERR BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS\t\t\t(Offset 0x04E2) */\n\n#define BIT_PTCL_ERR5 BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PTCL_ERR_STATUS_V1\t\t\t(Offset 0x04E2) */\n\n#define BIT_QUEUE_INDEX_ERR BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_NULL_PKT_STATUS_EXTEND\t\t(Offset 0x04E3) */\n\n#define BIT_CLI3_TX_NULL_1 BIT(7)\n#define BIT_CLI3_TX_NULL_0 BIT(6)\n#define BIT_CLI2_TX_NULL_1 BIT(5)\n#define BIT_CLI2_TX_NULL_0 BIT(4)\n#define BIT_CLI1_TX_NULL_1 BIT(3)\n#define BIT_CLI1_TX_NULL_0 BIT(2)\n#define BIT_CLI0_TX_NULL_1 BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PTCL_PKT_NUM\t\t\t(Offset 0x04E3) */\n\n#define BIT_SHIFT_PTCL_TOTAL_PG 0\n#define BIT_MASK_PTCL_TOTAL_PG 0xff\n#define BIT_PTCL_TOTAL_PG(x)                                                   \\\n\t(((x) & BIT_MASK_PTCL_TOTAL_PG) << BIT_SHIFT_PTCL_TOTAL_PG)\n#define BITS_PTCL_TOTAL_PG (BIT_MASK_PTCL_TOTAL_PG << BIT_SHIFT_PTCL_TOTAL_PG)\n#define BIT_CLEAR_PTCL_TOTAL_PG(x) ((x) & (~BITS_PTCL_TOTAL_PG))\n#define BIT_GET_PTCL_TOTAL_PG(x)                                               \\\n\t(((x) >> BIT_SHIFT_PTCL_TOTAL_PG) & BIT_MASK_PTCL_TOTAL_PG)\n#define BIT_SET_PTCL_TOTAL_PG(x, v)                                            \\\n\t(BIT_CLEAR_PTCL_TOTAL_PG(x) | BIT_PTCL_TOTAL_PG(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_NULL_PKT_STATUS_EXTEND\t\t(Offset 0x04E3) */\n\n#define BIT_CLI0_TX_NULL_0 BIT(0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_TRXRPT_MISS_CNT\t\t\t(Offset 0x04E3) */\n\n#define BIT_SHIFT_TRXRPT_MISS_CNT 0\n#define BIT_MASK_TRXRPT_MISS_CNT 0x7\n#define BIT_TRXRPT_MISS_CNT(x)                                                 \\\n\t(((x) & BIT_MASK_TRXRPT_MISS_CNT) << BIT_SHIFT_TRXRPT_MISS_CNT)\n#define BITS_TRXRPT_MISS_CNT                                                   \\\n\t(BIT_MASK_TRXRPT_MISS_CNT << BIT_SHIFT_TRXRPT_MISS_CNT)\n#define BIT_CLEAR_TRXRPT_MISS_CNT(x) ((x) & (~BITS_TRXRPT_MISS_CNT))\n#define BIT_GET_TRXRPT_MISS_CNT(x)                                             \\\n\t(((x) >> BIT_SHIFT_TRXRPT_MISS_CNT) & BIT_MASK_TRXRPT_MISS_CNT)\n#define BIT_SET_TRXRPT_MISS_CNT(x, v)                                          \\\n\t(BIT_CLEAR_TRXRPT_MISS_CNT(x) | BIT_TRXRPT_MISS_CNT(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_VIDEO_ENHANCEMENT_FUN\t\t(Offset 0x04E4) */\n\n#define BIT_MAX_PRETX_AGGR_EN BIT(19)\n\n#define BIT_SHIFT_MAX_PRETX_AGGR_TIME 8\n#define BIT_MASK_MAX_PRETX_AGGR_TIME 0x7ff\n#define BIT_MAX_PRETX_AGGR_TIME(x)                                             \\\n\t(((x) & BIT_MASK_MAX_PRETX_AGGR_TIME) << BIT_SHIFT_MAX_PRETX_AGGR_TIME)\n#define BITS_MAX_PRETX_AGGR_TIME                                               \\\n\t(BIT_MASK_MAX_PRETX_AGGR_TIME << BIT_SHIFT_MAX_PRETX_AGGR_TIME)\n#define BIT_CLEAR_MAX_PRETX_AGGR_TIME(x) ((x) & (~BITS_MAX_PRETX_AGGR_TIME))\n#define BIT_GET_MAX_PRETX_AGGR_TIME(x)                                         \\\n\t(((x) >> BIT_SHIFT_MAX_PRETX_AGGR_TIME) & BIT_MASK_MAX_PRETX_AGGR_TIME)\n#define BIT_SET_MAX_PRETX_AGGR_TIME(x, v)                                      \\\n\t(BIT_CLEAR_MAX_PRETX_AGGR_TIME(x) | BIT_MAX_PRETX_AGGR_TIME(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_NULL_PKT_STATUS_V2\t\t\t(Offset 0x04E4) */\n\n#define BIT_HIQ_DROP BIT(7)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_VIDEO_ENHANCEMENT_FUN\t\t(Offset 0x04E4) */\n\n#define BIT_HGQ_DEL_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_NULL_PKT_STATUS_V2\t\t\t(Offset 0x04E4) */\n\n#define BIT_MGQ_DROP BIT(6)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_VIDEO_ENHANCEMENT_FUN\t\t(Offset 0x04E4) */\n\n#define BIT_MGQ_DEL_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_VIDEO_ENHANCEMENT_FUN\t\t(Offset 0x04E4) */\n\n#define BIT_VIDEO_JUST_DROP BIT(1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_NULL_PKT_STATUS_V2\t\t\t(Offset 0x04E4) */\n\n#define BIT_TX_NULL_1_V1 BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_VIDEO_ENHANCEMENT_FUN\t\t(Offset 0x04E4) */\n\n#define BIT_VIDEO_ENHANCEMENT_FUN_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_VIDEO_ENHANCEMENT_FUN\t\t(Offset 0x04E4) */\n\n#define BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER 0\n#define BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER 0xff\n#define BIT_MEDIUM_HAS_IDLE_TRIGGER(x)                                         \\\n\t(((x) & BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER)                              \\\n\t << BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER)\n#define BITS_MEDIUM_HAS_IDLE_TRIGGER                                           \\\n\t(BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER << BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER)\n#define BIT_CLEAR_MEDIUM_HAS_IDLE_TRIGGER(x)                                   \\\n\t((x) & (~BITS_MEDIUM_HAS_IDLE_TRIGGER))\n#define BIT_GET_MEDIUM_HAS_IDLE_TRIGGER(x)                                     \\\n\t(((x) >> BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER) &                          \\\n\t BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER)\n#define BIT_SET_MEDIUM_HAS_IDLE_TRIGGER(x, v)                                  \\\n\t(BIT_CLEAR_MEDIUM_HAS_IDLE_TRIGGER(x) | BIT_MEDIUM_HAS_IDLE_TRIGGER(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_NULL_PKT_STATUS_V2\t\t\t(Offset 0x04E4) */\n\n#define BIT_TX_NULL_0_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)\n\n/* 2 REG_PRECNT_CTRL\t\t\t\t(Offset 0x04E5) */\n\n#define BIT_SHIFT_COLLISION_DETECT_TIME 12\n#define BIT_MASK_COLLISION_DETECT_TIME 0xf\n#define BIT_COLLISION_DETECT_TIME(x)                                           \\\n\t(((x) & BIT_MASK_COLLISION_DETECT_TIME)                                \\\n\t << BIT_SHIFT_COLLISION_DETECT_TIME)\n#define BITS_COLLISION_DETECT_TIME                                             \\\n\t(BIT_MASK_COLLISION_DETECT_TIME << BIT_SHIFT_COLLISION_DETECT_TIME)\n#define BIT_CLEAR_COLLISION_DETECT_TIME(x) ((x) & (~BITS_COLLISION_DETECT_TIME))\n#define BIT_GET_COLLISION_DETECT_TIME(x)                                       \\\n\t(((x) >> BIT_SHIFT_COLLISION_DETECT_TIME) &                            \\\n\t BIT_MASK_COLLISION_DETECT_TIME)\n#define BIT_SET_COLLISION_DETECT_TIME(x, v)                                    \\\n\t(BIT_CLEAR_COLLISION_DETECT_TIME(x) | BIT_COLLISION_DETECT_TIME(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PRECNT_CTRL\t\t\t\t(Offset 0x04E5) */\n\n#define BIT_EN_PRECNT BIT(11)\n\n#define BIT_SHIFT_PRECNT_TH 0\n#define BIT_MASK_PRECNT_TH 0x7ff\n#define BIT_PRECNT_TH(x) (((x) & BIT_MASK_PRECNT_TH) << BIT_SHIFT_PRECNT_TH)\n#define BITS_PRECNT_TH (BIT_MASK_PRECNT_TH << BIT_SHIFT_PRECNT_TH)\n#define BIT_CLEAR_PRECNT_TH(x) ((x) & (~BITS_PRECNT_TH))\n#define BIT_GET_PRECNT_TH(x) (((x) >> BIT_SHIFT_PRECNT_TH) & BIT_MASK_PRECNT_TH)\n#define BIT_SET_PRECNT_TH(x, v) (BIT_CLEAR_PRECNT_TH(x) | BIT_PRECNT_TH(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_NULL_PKT_STATUS_EXTEND_V1\t\t(Offset 0x04E7) */\n\n#define BIT_CLI3_TX_NULL_1_V1 BIT(7)\n#define BIT_CLI3_TX_NULL_0_V1 BIT(6)\n#define BIT_CLI2_TX_NULL_1_V1 BIT(5)\n#define BIT_CLI2_TX_NULL_0_V1 BIT(4)\n#define BIT_CLI1_TX_NULL_1_V1 BIT(3)\n#define BIT_CLI1_TX_NULL_0_V1 BIT(2)\n#define BIT_CLI0_TX_NULL_1_V1 BIT(1)\n#define BIT_CLI0_TX_NULL_0_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BT_POLLUTE_PKT_CNT\t\t\t(Offset 0x04E8) */\n\n#define BIT_SHIFT_BT_POLLUTE_PKT_CNT 0\n#define BIT_MASK_BT_POLLUTE_PKT_CNT 0xffff\n#define BIT_BT_POLLUTE_PKT_CNT(x)                                              \\\n\t(((x) & BIT_MASK_BT_POLLUTE_PKT_CNT) << BIT_SHIFT_BT_POLLUTE_PKT_CNT)\n#define BITS_BT_POLLUTE_PKT_CNT                                                \\\n\t(BIT_MASK_BT_POLLUTE_PKT_CNT << BIT_SHIFT_BT_POLLUTE_PKT_CNT)\n#define BIT_CLEAR_BT_POLLUTE_PKT_CNT(x) ((x) & (~BITS_BT_POLLUTE_PKT_CNT))\n#define BIT_GET_BT_POLLUTE_PKT_CNT(x)                                          \\\n\t(((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT) & BIT_MASK_BT_POLLUTE_PKT_CNT)\n#define BIT_SET_BT_POLLUTE_PKT_CNT(x, v)                                       \\\n\t(BIT_CLEAR_BT_POLLUTE_PKT_CNT(x) | BIT_BT_POLLUTE_PKT_CNT(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DROP_NUM\t\t\t\t(Offset 0x04EC) */\n\n#define BIT_SHIFT_DROP_PKT_NUM 0\n#define BIT_MASK_DROP_PKT_NUM 0xffff\n#define BIT_DROP_PKT_NUM(x)                                                    \\\n\t(((x) & BIT_MASK_DROP_PKT_NUM) << BIT_SHIFT_DROP_PKT_NUM)\n#define BITS_DROP_PKT_NUM (BIT_MASK_DROP_PKT_NUM << BIT_SHIFT_DROP_PKT_NUM)\n#define BIT_CLEAR_DROP_PKT_NUM(x) ((x) & (~BITS_DROP_PKT_NUM))\n#define BIT_GET_DROP_PKT_NUM(x)                                                \\\n\t(((x) >> BIT_SHIFT_DROP_PKT_NUM) & BIT_MASK_DROP_PKT_NUM)\n#define BIT_SET_DROP_PKT_NUM(x, v)                                             \\\n\t(BIT_CLEAR_DROP_PKT_NUM(x) | BIT_DROP_PKT_NUM(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PTCL_DBG_V1\t\t\t\t(Offset 0x04EC) */\n\n#define BIT_SHIFT_PTCL_DBG 0\n#define BIT_MASK_PTCL_DBG 0xffffffffL\n#define BIT_PTCL_DBG(x) (((x) & BIT_MASK_PTCL_DBG) << BIT_SHIFT_PTCL_DBG)\n#define BITS_PTCL_DBG (BIT_MASK_PTCL_DBG << BIT_SHIFT_PTCL_DBG)\n#define BIT_CLEAR_PTCL_DBG(x) ((x) & (~BITS_PTCL_DBG))\n#define BIT_GET_PTCL_DBG(x) (((x) >> BIT_SHIFT_PTCL_DBG) & BIT_MASK_PTCL_DBG)\n#define BIT_SET_PTCL_DBG(x, v) (BIT_CLEAR_PTCL_DBG(x) | BIT_PTCL_DBG(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PTCL_TX_RPT\t\t\t\t(Offset 0x04F0) */\n\n#define BIT_SHIFT_AC_TX_RPT_INFO 0\n#define BIT_MASK_AC_TX_RPT_INFO 0xffffffffffffffffL\n#define BIT_AC_TX_RPT_INFO(x)                                                  \\\n\t(((x) & BIT_MASK_AC_TX_RPT_INFO) << BIT_SHIFT_AC_TX_RPT_INFO)\n#define BITS_AC_TX_RPT_INFO                                                    \\\n\t(BIT_MASK_AC_TX_RPT_INFO << BIT_SHIFT_AC_TX_RPT_INFO)\n#define BIT_CLEAR_AC_TX_RPT_INFO(x) ((x) & (~BITS_AC_TX_RPT_INFO))\n#define BIT_GET_AC_TX_RPT_INFO(x)                                              \\\n\t(((x) >> BIT_SHIFT_AC_TX_RPT_INFO) & BIT_MASK_AC_TX_RPT_INFO)\n#define BIT_SET_AC_TX_RPT_INFO(x, v)                                           \\\n\t(BIT_CLEAR_AC_TX_RPT_INFO(x) | BIT_AC_TX_RPT_INFO(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TX_RPT_INFO_L32\t\t\t(Offset 0x04F0) */\n\n#define BIT_SHIFT_AC_TX_RPT_INFO_L32 0\n#define BIT_MASK_AC_TX_RPT_INFO_L32 0xffffffffL\n#define BIT_AC_TX_RPT_INFO_L32(x)                                              \\\n\t(((x) & BIT_MASK_AC_TX_RPT_INFO_L32) << BIT_SHIFT_AC_TX_RPT_INFO_L32)\n#define BITS_AC_TX_RPT_INFO_L32                                                \\\n\t(BIT_MASK_AC_TX_RPT_INFO_L32 << BIT_SHIFT_AC_TX_RPT_INFO_L32)\n#define BIT_CLEAR_AC_TX_RPT_INFO_L32(x) ((x) & (~BITS_AC_TX_RPT_INFO_L32))\n#define BIT_GET_AC_TX_RPT_INFO_L32(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC_TX_RPT_INFO_L32) & BIT_MASK_AC_TX_RPT_INFO_L32)\n#define BIT_SET_AC_TX_RPT_INFO_L32(x, v)                                       \\\n\t(BIT_CLEAR_AC_TX_RPT_INFO_L32(x) | BIT_AC_TX_RPT_INFO_L32(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TXOP_EXTRA_CTRL\t\t\t(Offset 0x04F0) */\n\n#define BIT_TXOP_EFFICIENCY_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_BT_POLLUTE_PKTCNT\t\t\t(Offset 0x04F0) */\n\n#define BIT_SHIFT_BT_POLLUTE_PKTCNT 0\n#define BIT_MASK_BT_POLLUTE_PKTCNT 0xffff\n#define BIT_BT_POLLUTE_PKTCNT(x)                                               \\\n\t(((x) & BIT_MASK_BT_POLLUTE_PKTCNT) << BIT_SHIFT_BT_POLLUTE_PKTCNT)\n#define BITS_BT_POLLUTE_PKTCNT                                                 \\\n\t(BIT_MASK_BT_POLLUTE_PKTCNT << BIT_SHIFT_BT_POLLUTE_PKTCNT)\n#define BIT_CLEAR_BT_POLLUTE_PKTCNT(x) ((x) & (~BITS_BT_POLLUTE_PKTCNT))\n#define BIT_GET_BT_POLLUTE_PKTCNT(x)                                           \\\n\t(((x) >> BIT_SHIFT_BT_POLLUTE_PKTCNT) & BIT_MASK_BT_POLLUTE_PKTCNT)\n#define BIT_SET_BT_POLLUTE_PKTCNT(x, v)                                        \\\n\t(BIT_CLEAR_BT_POLLUTE_PKTCNT(x) | BIT_BT_POLLUTE_PKTCNT(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CPUMGQ_TIMER_CTRL2\t\t\t(Offset 0x04F4) */\n\n#define BIT_SHIFT_TRI_HEAD_ADDR 16\n#define BIT_MASK_TRI_HEAD_ADDR 0xfff\n#define BIT_TRI_HEAD_ADDR(x)                                                   \\\n\t(((x) & BIT_MASK_TRI_HEAD_ADDR) << BIT_SHIFT_TRI_HEAD_ADDR)\n#define BITS_TRI_HEAD_ADDR (BIT_MASK_TRI_HEAD_ADDR << BIT_SHIFT_TRI_HEAD_ADDR)\n#define BIT_CLEAR_TRI_HEAD_ADDR(x) ((x) & (~BITS_TRI_HEAD_ADDR))\n#define BIT_GET_TRI_HEAD_ADDR(x)                                               \\\n\t(((x) >> BIT_SHIFT_TRI_HEAD_ADDR) & BIT_MASK_TRI_HEAD_ADDR)\n#define BIT_SET_TRI_HEAD_ADDR(x, v)                                            \\\n\t(BIT_CLEAR_TRI_HEAD_ADDR(x) | BIT_TRI_HEAD_ADDR(v))\n\n#define BIT_DROP_TH_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TX_RPT_INFO_H32\t\t\t(Offset 0x04F4) */\n\n#define BIT_SHIFT_AC_TX_RPT_INFO_H32 0\n#define BIT_MASK_AC_TX_RPT_INFO_H32 0xffffffffL\n#define BIT_AC_TX_RPT_INFO_H32(x)                                              \\\n\t(((x) & BIT_MASK_AC_TX_RPT_INFO_H32) << BIT_SHIFT_AC_TX_RPT_INFO_H32)\n#define BITS_AC_TX_RPT_INFO_H32                                                \\\n\t(BIT_MASK_AC_TX_RPT_INFO_H32 << BIT_SHIFT_AC_TX_RPT_INFO_H32)\n#define BIT_CLEAR_AC_TX_RPT_INFO_H32(x) ((x) & (~BITS_AC_TX_RPT_INFO_H32))\n#define BIT_GET_AC_TX_RPT_INFO_H32(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC_TX_RPT_INFO_H32) & BIT_MASK_AC_TX_RPT_INFO_H32)\n#define BIT_SET_AC_TX_RPT_INFO_H32(x, v)                                       \\\n\t(BIT_CLEAR_AC_TX_RPT_INFO_H32(x) | BIT_AC_TX_RPT_INFO_H32(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CPUMGQ_TIMER_CTRL2\t\t\t(Offset 0x04F4) */\n\n#define BIT_SHIFT_DROP_TH 0\n#define BIT_MASK_DROP_TH 0xff\n#define BIT_DROP_TH(x) (((x) & BIT_MASK_DROP_TH) << BIT_SHIFT_DROP_TH)\n#define BITS_DROP_TH (BIT_MASK_DROP_TH << BIT_SHIFT_DROP_TH)\n#define BIT_CLEAR_DROP_TH(x) ((x) & (~BITS_DROP_TH))\n#define BIT_GET_DROP_TH(x) (((x) >> BIT_SHIFT_DROP_TH) & BIT_MASK_DROP_TH)\n#define BIT_SET_DROP_TH(x, v) (BIT_CLEAR_DROP_TH(x) | BIT_DROP_TH(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PTCL_DBG_OUT\t\t\t(Offset 0x04F8) */\n\n#define BIT_SHIFT_PTCL_DBG_OUT 0\n#define BIT_MASK_PTCL_DBG_OUT 0xffffffffL\n#define BIT_PTCL_DBG_OUT(x)                                                    \\\n\t(((x) & BIT_MASK_PTCL_DBG_OUT) << BIT_SHIFT_PTCL_DBG_OUT)\n#define BITS_PTCL_DBG_OUT (BIT_MASK_PTCL_DBG_OUT << BIT_SHIFT_PTCL_DBG_OUT)\n#define BIT_CLEAR_PTCL_DBG_OUT(x) ((x) & (~BITS_PTCL_DBG_OUT))\n#define BIT_GET_PTCL_DBG_OUT(x)                                                \\\n\t(((x) >> BIT_SHIFT_PTCL_DBG_OUT) & BIT_MASK_PTCL_DBG_OUT)\n#define BIT_SET_PTCL_DBG_OUT(x, v)                                             \\\n\t(BIT_CLEAR_PTCL_DBG_OUT(x) | BIT_PTCL_DBG_OUT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_DUMMY_PAGE4\t\t\t\t(Offset 0x04FC) */\n\n#define BIT_MOREDATA_CTRL2_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DUMMY_PAGE4\t\t\t\t(Offset 0x04FC) */\n\n#define BIT_MOREDATA_CTRL2_EN_V2 BIT(19)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n/* 2 REG_DUMMY_PAGE4\t\t\t\t(Offset 0x04FC) */\n\n#define BIT_MOREDATA_CTRL1_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DUMMY_PAGE4\t\t\t\t(Offset 0x04FC) */\n\n#define BIT_MOREDATA_CTRL1_EN_V2 BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DUMMY_PAGE4\t\t\t\t(Offset 0x04FC) */\n\n#define BIT_EN_BCN_TRXRPT BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DUMMY_PAGE4\t\t\t\t(Offset 0x04FC) */\n\n#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE BIT(16)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_DUMMY_PAGE4_V1\t\t\t(Offset 0x04FC) */\n\n#define BIT_BCN_EN_EXTHWSEQ BIT(1)\n#define BIT_BCN_EN_HWSEQ BIT(0)\n\n#define BIT_SHIFT_R_MU_STA_GTAB_POSITION 0\n#define BIT_MASK_R_MU_STA_GTAB_POSITION 0xffffffffffffffffL\n#define BIT_R_MU_STA_GTAB_POSITION(x)                                          \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION)                               \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION)\n#define BITS_R_MU_STA_GTAB_POSITION                                            \\\n\t(BIT_MASK_R_MU_STA_GTAB_POSITION << BIT_SHIFT_R_MU_STA_GTAB_POSITION)\n#define BIT_CLEAR_R_MU_STA_GTAB_POSITION(x)                                    \\\n\t((x) & (~BITS_R_MU_STA_GTAB_POSITION))\n#define BIT_GET_R_MU_STA_GTAB_POSITION(x)                                      \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION) &                           \\\n\t BIT_MASK_R_MU_STA_GTAB_POSITION)\n#define BIT_SET_R_MU_STA_GTAB_POSITION(x, v)                                   \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_POSITION(x) | BIT_R_MU_STA_GTAB_POSITION(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MOREDATA\t\t\t\t(Offset 0x04FE) */\n\n#define BIT_MOREDATA_CTRL2_EN_V1 BIT(3)\n#define BIT_MOREDATA_CTRL1_EN_V1 BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DUMMY_PAGE4_1\t\t\t(Offset 0x04FE) */\n\n#define BIT_EN_BCN_TRXRPT_V2 BIT(1)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MOREDATA\t\t\t\t(Offset 0x04FE) */\n\n#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_EDCA_VO_PARAM\t\t\t(Offset 0x0500) */\n\n#define BIT_SHIFT_TXOPLIMIT 16\n#define BIT_MASK_TXOPLIMIT 0x7ff\n#define BIT_TXOPLIMIT(x) (((x) & BIT_MASK_TXOPLIMIT) << BIT_SHIFT_TXOPLIMIT)\n#define BITS_TXOPLIMIT (BIT_MASK_TXOPLIMIT << BIT_SHIFT_TXOPLIMIT)\n#define BIT_CLEAR_TXOPLIMIT(x) ((x) & (~BITS_TXOPLIMIT))\n#define BIT_GET_TXOPLIMIT(x) (((x) >> BIT_SHIFT_TXOPLIMIT) & BIT_MASK_TXOPLIMIT)\n#define BIT_SET_TXOPLIMIT(x, v) (BIT_CLEAR_TXOPLIMIT(x) | BIT_TXOPLIMIT(v))\n\n#define BIT_SHIFT_CW 8\n#define BIT_MASK_CW 0xff\n#define BIT_CW(x) (((x) & BIT_MASK_CW) << BIT_SHIFT_CW)\n#define BITS_CW (BIT_MASK_CW << BIT_SHIFT_CW)\n#define BIT_CLEAR_CW(x) ((x) & (~BITS_CW))\n#define BIT_GET_CW(x) (((x) >> BIT_SHIFT_CW) & BIT_MASK_CW)\n#define BIT_SET_CW(x, v) (BIT_CLEAR_CW(x) | BIT_CW(v))\n\n#define BIT_SHIFT_AIFS 0\n#define BIT_MASK_AIFS 0xff\n#define BIT_AIFS(x) (((x) & BIT_MASK_AIFS) << BIT_SHIFT_AIFS)\n#define BITS_AIFS (BIT_MASK_AIFS << BIT_SHIFT_AIFS)\n#define BIT_CLEAR_AIFS(x) ((x) & (~BITS_AIFS))\n#define BIT_GET_AIFS(x) (((x) >> BIT_SHIFT_AIFS) & BIT_MASK_AIFS)\n#define BIT_SET_AIFS(x, v) (BIT_CLEAR_AIFS(x) | BIT_AIFS(v))\n\n/* 2 REG_BCNTCFG\t\t\t\t(Offset 0x0510) */\n\n#define BIT_SHIFT_BCNCW_MAX 12\n#define BIT_MASK_BCNCW_MAX 0xf\n#define BIT_BCNCW_MAX(x) (((x) & BIT_MASK_BCNCW_MAX) << BIT_SHIFT_BCNCW_MAX)\n#define BITS_BCNCW_MAX (BIT_MASK_BCNCW_MAX << BIT_SHIFT_BCNCW_MAX)\n#define BIT_CLEAR_BCNCW_MAX(x) ((x) & (~BITS_BCNCW_MAX))\n#define BIT_GET_BCNCW_MAX(x) (((x) >> BIT_SHIFT_BCNCW_MAX) & BIT_MASK_BCNCW_MAX)\n#define BIT_SET_BCNCW_MAX(x, v) (BIT_CLEAR_BCNCW_MAX(x) | BIT_BCNCW_MAX(v))\n\n#define BIT_SHIFT_BCNCW_MIN 8\n#define BIT_MASK_BCNCW_MIN 0xf\n#define BIT_BCNCW_MIN(x) (((x) & BIT_MASK_BCNCW_MIN) << BIT_SHIFT_BCNCW_MIN)\n#define BITS_BCNCW_MIN (BIT_MASK_BCNCW_MIN << BIT_SHIFT_BCNCW_MIN)\n#define BIT_CLEAR_BCNCW_MIN(x) ((x) & (~BITS_BCNCW_MIN))\n#define BIT_GET_BCNCW_MIN(x) (((x) >> BIT_SHIFT_BCNCW_MIN) & BIT_MASK_BCNCW_MIN)\n#define BIT_SET_BCNCW_MIN(x, v) (BIT_CLEAR_BCNCW_MIN(x) | BIT_BCNCW_MIN(v))\n\n#define BIT_SHIFT_BCNIFS 0\n#define BIT_MASK_BCNIFS 0xff\n#define BIT_BCNIFS(x) (((x) & BIT_MASK_BCNIFS) << BIT_SHIFT_BCNIFS)\n#define BITS_BCNIFS (BIT_MASK_BCNIFS << BIT_SHIFT_BCNIFS)\n#define BIT_CLEAR_BCNIFS(x) ((x) & (~BITS_BCNIFS))\n#define BIT_GET_BCNIFS(x) (((x) >> BIT_SHIFT_BCNIFS) & BIT_MASK_BCNIFS)\n#define BIT_SET_BCNIFS(x, v) (BIT_CLEAR_BCNIFS(x) | BIT_BCNIFS(v))\n\n/* 2 REG_PIFS\t\t\t\t(Offset 0x0512) */\n\n#define BIT_SHIFT_PIFS 0\n#define BIT_MASK_PIFS 0xff\n#define BIT_PIFS(x) (((x) & BIT_MASK_PIFS) << BIT_SHIFT_PIFS)\n#define BITS_PIFS (BIT_MASK_PIFS << BIT_SHIFT_PIFS)\n#define BIT_CLEAR_PIFS(x) ((x) & (~BITS_PIFS))\n#define BIT_GET_PIFS(x) (((x) >> BIT_SHIFT_PIFS) & BIT_MASK_PIFS)\n#define BIT_SET_PIFS(x, v) (BIT_CLEAR_PIFS(x) | BIT_PIFS(v))\n\n/* 2 REG_RDG_PIFS\t\t\t\t(Offset 0x0513) */\n\n#define BIT_SHIFT_RDG_PIFS 0\n#define BIT_MASK_RDG_PIFS 0xff\n#define BIT_RDG_PIFS(x) (((x) & BIT_MASK_RDG_PIFS) << BIT_SHIFT_RDG_PIFS)\n#define BITS_RDG_PIFS (BIT_MASK_RDG_PIFS << BIT_SHIFT_RDG_PIFS)\n#define BIT_CLEAR_RDG_PIFS(x) ((x) & (~BITS_RDG_PIFS))\n#define BIT_GET_RDG_PIFS(x) (((x) >> BIT_SHIFT_RDG_PIFS) & BIT_MASK_RDG_PIFS)\n#define BIT_SET_RDG_PIFS(x, v) (BIT_CLEAR_RDG_PIFS(x) | BIT_RDG_PIFS(v))\n\n/* 2 REG_SIFS\t\t\t\t(Offset 0x0514) */\n\n#define BIT_SHIFT_SIFS_OFDM_TRX 24\n#define BIT_MASK_SIFS_OFDM_TRX 0xff\n#define BIT_SIFS_OFDM_TRX(x)                                                   \\\n\t(((x) & BIT_MASK_SIFS_OFDM_TRX) << BIT_SHIFT_SIFS_OFDM_TRX)\n#define BITS_SIFS_OFDM_TRX (BIT_MASK_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)\n#define BIT_CLEAR_SIFS_OFDM_TRX(x) ((x) & (~BITS_SIFS_OFDM_TRX))\n#define BIT_GET_SIFS_OFDM_TRX(x)                                               \\\n\t(((x) >> BIT_SHIFT_SIFS_OFDM_TRX) & BIT_MASK_SIFS_OFDM_TRX)\n#define BIT_SET_SIFS_OFDM_TRX(x, v)                                            \\\n\t(BIT_CLEAR_SIFS_OFDM_TRX(x) | BIT_SIFS_OFDM_TRX(v))\n\n#define BIT_SHIFT_SIFS_CCK_TRX 16\n#define BIT_MASK_SIFS_CCK_TRX 0xff\n#define BIT_SIFS_CCK_TRX(x)                                                    \\\n\t(((x) & BIT_MASK_SIFS_CCK_TRX) << BIT_SHIFT_SIFS_CCK_TRX)\n#define BITS_SIFS_CCK_TRX (BIT_MASK_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX)\n#define BIT_CLEAR_SIFS_CCK_TRX(x) ((x) & (~BITS_SIFS_CCK_TRX))\n#define BIT_GET_SIFS_CCK_TRX(x)                                                \\\n\t(((x) >> BIT_SHIFT_SIFS_CCK_TRX) & BIT_MASK_SIFS_CCK_TRX)\n#define BIT_SET_SIFS_CCK_TRX(x, v)                                             \\\n\t(BIT_CLEAR_SIFS_CCK_TRX(x) | BIT_SIFS_CCK_TRX(v))\n\n#define BIT_SHIFT_SIFS_OFDM_CTX 8\n#define BIT_MASK_SIFS_OFDM_CTX 0xff\n#define BIT_SIFS_OFDM_CTX(x)                                                   \\\n\t(((x) & BIT_MASK_SIFS_OFDM_CTX) << BIT_SHIFT_SIFS_OFDM_CTX)\n#define BITS_SIFS_OFDM_CTX (BIT_MASK_SIFS_OFDM_CTX << BIT_SHIFT_SIFS_OFDM_CTX)\n#define BIT_CLEAR_SIFS_OFDM_CTX(x) ((x) & (~BITS_SIFS_OFDM_CTX))\n#define BIT_GET_SIFS_OFDM_CTX(x)                                               \\\n\t(((x) >> BIT_SHIFT_SIFS_OFDM_CTX) & BIT_MASK_SIFS_OFDM_CTX)\n#define BIT_SET_SIFS_OFDM_CTX(x, v)                                            \\\n\t(BIT_CLEAR_SIFS_OFDM_CTX(x) | BIT_SIFS_OFDM_CTX(v))\n\n#define BIT_SHIFT_SIFS_CCK_CTX 0\n#define BIT_MASK_SIFS_CCK_CTX 0xff\n#define BIT_SIFS_CCK_CTX(x)                                                    \\\n\t(((x) & BIT_MASK_SIFS_CCK_CTX) << BIT_SHIFT_SIFS_CCK_CTX)\n#define BITS_SIFS_CCK_CTX (BIT_MASK_SIFS_CCK_CTX << BIT_SHIFT_SIFS_CCK_CTX)\n#define BIT_CLEAR_SIFS_CCK_CTX(x) ((x) & (~BITS_SIFS_CCK_CTX))\n#define BIT_GET_SIFS_CCK_CTX(x)                                                \\\n\t(((x) >> BIT_SHIFT_SIFS_CCK_CTX) & BIT_MASK_SIFS_CCK_CTX)\n#define BIT_SET_SIFS_CCK_CTX(x, v)                                             \\\n\t(BIT_CLEAR_SIFS_CCK_CTX(x) | BIT_SIFS_CCK_CTX(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TSFTR_SYN_OFFSET\t\t\t(Offset 0x0518) */\n\n#define BIT_SHIFT_TSFTR_SNC_OFFSET 0\n#define BIT_MASK_TSFTR_SNC_OFFSET 0xffff\n#define BIT_TSFTR_SNC_OFFSET(x)                                                \\\n\t(((x) & BIT_MASK_TSFTR_SNC_OFFSET) << BIT_SHIFT_TSFTR_SNC_OFFSET)\n#define BITS_TSFTR_SNC_OFFSET                                                  \\\n\t(BIT_MASK_TSFTR_SNC_OFFSET << BIT_SHIFT_TSFTR_SNC_OFFSET)\n#define BIT_CLEAR_TSFTR_SNC_OFFSET(x) ((x) & (~BITS_TSFTR_SNC_OFFSET))\n#define BIT_GET_TSFTR_SNC_OFFSET(x)                                            \\\n\t(((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET) & BIT_MASK_TSFTR_SNC_OFFSET)\n#define BIT_SET_TSFTR_SNC_OFFSET(x, v)                                         \\\n\t(BIT_CLEAR_TSFTR_SNC_OFFSET(x) | BIT_TSFTR_SNC_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_AGGR_BREAK_TIME\t\t\t(Offset 0x051A) */\n\n#define BIT_SHIFT_AGGR_BK_TIME 0\n#define BIT_MASK_AGGR_BK_TIME 0xff\n#define BIT_AGGR_BK_TIME(x)                                                    \\\n\t(((x) & BIT_MASK_AGGR_BK_TIME) << BIT_SHIFT_AGGR_BK_TIME)\n#define BITS_AGGR_BK_TIME (BIT_MASK_AGGR_BK_TIME << BIT_SHIFT_AGGR_BK_TIME)\n#define BIT_CLEAR_AGGR_BK_TIME(x) ((x) & (~BITS_AGGR_BK_TIME))\n#define BIT_GET_AGGR_BK_TIME(x)                                                \\\n\t(((x) >> BIT_SHIFT_AGGR_BK_TIME) & BIT_MASK_AGGR_BK_TIME)\n#define BIT_SET_AGGR_BK_TIME(x, v)                                             \\\n\t(BIT_CLEAR_AGGR_BK_TIME(x) | BIT_AGGR_BK_TIME(v))\n\n/* 2 REG_SLOT\t\t\t\t(Offset 0x051B) */\n\n#define BIT_SHIFT_SLOT 0\n#define BIT_MASK_SLOT 0xff\n#define BIT_SLOT(x) (((x) & BIT_MASK_SLOT) << BIT_SHIFT_SLOT)\n#define BITS_SLOT (BIT_MASK_SLOT << BIT_SHIFT_SLOT)\n#define BIT_CLEAR_SLOT(x) ((x) & (~BITS_SLOT))\n#define BIT_GET_SLOT(x) (((x) >> BIT_SHIFT_SLOT) & BIT_MASK_SLOT)\n#define BIT_SET_SLOT(x, v) (BIT_CLEAR_SLOT(x) | BIT_SLOT(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_EDCA_CPUMGQ_PARAM\t\t\t(Offset 0x051C) */\n\n#define BIT_SHIFT_CW_V1 8\n#define BIT_MASK_CW_V1 0xff\n#define BIT_CW_V1(x) (((x) & BIT_MASK_CW_V1) << BIT_SHIFT_CW_V1)\n#define BITS_CW_V1 (BIT_MASK_CW_V1 << BIT_SHIFT_CW_V1)\n#define BIT_CLEAR_CW_V1(x) ((x) & (~BITS_CW_V1))\n#define BIT_GET_CW_V1(x) (((x) >> BIT_SHIFT_CW_V1) & BIT_MASK_CW_V1)\n#define BIT_SET_CW_V1(x, v) (BIT_CLEAR_CW_V1(x) | BIT_CW_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_NOA_ON_ERLY_TIME\t\t\t(Offset 0x051C) */\n\n#define BIT_SHIFT__NOA_ON_ERLY_TIME 0\n#define BIT_MASK__NOA_ON_ERLY_TIME 0xff\n#define BIT__NOA_ON_ERLY_TIME(x)                                               \\\n\t(((x) & BIT_MASK__NOA_ON_ERLY_TIME) << BIT_SHIFT__NOA_ON_ERLY_TIME)\n#define BITS__NOA_ON_ERLY_TIME                                                 \\\n\t(BIT_MASK__NOA_ON_ERLY_TIME << BIT_SHIFT__NOA_ON_ERLY_TIME)\n#define BIT_CLEAR__NOA_ON_ERLY_TIME(x) ((x) & (~BITS__NOA_ON_ERLY_TIME))\n#define BIT_GET__NOA_ON_ERLY_TIME(x)                                           \\\n\t(((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME) & BIT_MASK__NOA_ON_ERLY_TIME)\n#define BIT_SET__NOA_ON_ERLY_TIME(x, v)                                        \\\n\t(BIT_CLEAR__NOA_ON_ERLY_TIME(x) | BIT__NOA_ON_ERLY_TIME(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_EDCA_CPUMGQ_PARAM\t\t\t(Offset 0x051C) */\n\n#define BIT_SHIFT_AIFS_V1 0\n#define BIT_MASK_AIFS_V1 0xff\n#define BIT_AIFS_V1(x) (((x) & BIT_MASK_AIFS_V1) << BIT_SHIFT_AIFS_V1)\n#define BITS_AIFS_V1 (BIT_MASK_AIFS_V1 << BIT_SHIFT_AIFS_V1)\n#define BIT_CLEAR_AIFS_V1(x) ((x) & (~BITS_AIFS_V1))\n#define BIT_GET_AIFS_V1(x) (((x) >> BIT_SHIFT_AIFS_V1) & BIT_MASK_AIFS_V1)\n#define BIT_SET_AIFS_V1(x, v) (BIT_CLEAR_AIFS_V1(x) | BIT_AIFS_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_NOA_OFF_ERLY_TIME\t\t\t(Offset 0x051D) */\n\n#define BIT_SHIFT__NOA_OFF_ERLY_TIME 0\n#define BIT_MASK__NOA_OFF_ERLY_TIME 0xff\n#define BIT__NOA_OFF_ERLY_TIME(x)                                              \\\n\t(((x) & BIT_MASK__NOA_OFF_ERLY_TIME) << BIT_SHIFT__NOA_OFF_ERLY_TIME)\n#define BITS__NOA_OFF_ERLY_TIME                                                \\\n\t(BIT_MASK__NOA_OFF_ERLY_TIME << BIT_SHIFT__NOA_OFF_ERLY_TIME)\n#define BIT_CLEAR__NOA_OFF_ERLY_TIME(x) ((x) & (~BITS__NOA_OFF_ERLY_TIME))\n#define BIT_GET__NOA_OFF_ERLY_TIME(x)                                          \\\n\t(((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME) & BIT_MASK__NOA_OFF_ERLY_TIME)\n#define BIT_SET__NOA_OFF_ERLY_TIME(x, v)                                       \\\n\t(BIT_CLEAR__NOA_OFF_ERLY_TIME(x) | BIT__NOA_OFF_ERLY_TIME(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CPUMGQ_PAUSE\t\t\t(Offset 0x051E) */\n\n#define BIT_MAC_STOP_CPUMGQ_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_PS_TIMER_CTRL\t\t\t(Offset 0x051F) */\n\n#define BIT_PS_TIMER_B_EN_V1 BIT(7)\n\n#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_V1 4\n#define BIT_MASK_PS_TIMER_B_TSF_SEL_V1 0x3\n#define BIT_PS_TIMER_B_TSF_SEL_V1(x)                                           \\\n\t(((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_V1)                                \\\n\t << BIT_SHIFT_PS_TIMER_B_TSF_SEL_V1)\n#define BITS_PS_TIMER_B_TSF_SEL_V1                                             \\\n\t(BIT_MASK_PS_TIMER_B_TSF_SEL_V1 << BIT_SHIFT_PS_TIMER_B_TSF_SEL_V1)\n#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_V1(x) ((x) & (~BITS_PS_TIMER_B_TSF_SEL_V1))\n#define BIT_GET_PS_TIMER_B_TSF_SEL_V1(x)                                       \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_V1) &                            \\\n\t BIT_MASK_PS_TIMER_B_TSF_SEL_V1)\n#define BIT_SET_PS_TIMER_B_TSF_SEL_V1(x, v)                                    \\\n\t(BIT_CLEAR_PS_TIMER_B_TSF_SEL_V1(x) | BIT_PS_TIMER_B_TSF_SEL_V1(v))\n\n#define BIT_PS_TIMER_A_EN_V1 BIT(3)\n\n#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_V1 0\n#define BIT_MASK_PS_TIMER_A_TSF_SEL_V1 0x3\n#define BIT_PS_TIMER_A_TSF_SEL_V1(x)                                           \\\n\t(((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_V1)                                \\\n\t << BIT_SHIFT_PS_TIMER_A_TSF_SEL_V1)\n#define BITS_PS_TIMER_A_TSF_SEL_V1                                             \\\n\t(BIT_MASK_PS_TIMER_A_TSF_SEL_V1 << BIT_SHIFT_PS_TIMER_A_TSF_SEL_V1)\n#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_V1(x) ((x) & (~BITS_PS_TIMER_A_TSF_SEL_V1))\n#define BIT_GET_PS_TIMER_A_TSF_SEL_V1(x)                                       \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_V1) &                            \\\n\t BIT_MASK_PS_TIMER_A_TSF_SEL_V1)\n#define BIT_SET_PS_TIMER_A_TSF_SEL_V1(x, v)                                    \\\n\t(BIT_CLEAR_PS_TIMER_A_TSF_SEL_V1(x) | BIT_PS_TIMER_A_TSF_SEL_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TX_PTCL_CTRL\t\t\t(Offset 0x0520) */\n\n#define BIT_DIS_EDCCA BIT(15)\n#define BIT_DIS_CCA BIT(14)\n#define BIT_LSIG_TXOP_TXCMD_NAV BIT(13)\n#define BIT_SIFS_BK_EN BIT(12)\n\n#define BIT_SHIFT_TXQ_NAV_MSK 8\n#define BIT_MASK_TXQ_NAV_MSK 0xf\n#define BIT_TXQ_NAV_MSK(x)                                                     \\\n\t(((x) & BIT_MASK_TXQ_NAV_MSK) << BIT_SHIFT_TXQ_NAV_MSK)\n#define BITS_TXQ_NAV_MSK (BIT_MASK_TXQ_NAV_MSK << BIT_SHIFT_TXQ_NAV_MSK)\n#define BIT_CLEAR_TXQ_NAV_MSK(x) ((x) & (~BITS_TXQ_NAV_MSK))\n#define BIT_GET_TXQ_NAV_MSK(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TXQ_NAV_MSK) & BIT_MASK_TXQ_NAV_MSK)\n#define BIT_SET_TXQ_NAV_MSK(x, v)                                              \\\n\t(BIT_CLEAR_TXQ_NAV_MSK(x) | BIT_TXQ_NAV_MSK(v))\n\n#define BIT_DIS_CW BIT(7)\n#define BIT_NAV_END_TXOP BIT(6)\n#define BIT_RDG_END_TXOP BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TX_PTCL_CTRL\t\t\t(Offset 0x0520) */\n\n#define BIT_AC_INBCN_HOLD BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TX_PTCL_CTRL\t\t\t(Offset 0x0520) */\n\n#define BIT_MGTQ_TXOP_EN BIT(3)\n#define BIT_MGTQ_RTSMF_EN BIT(2)\n#define BIT_HIQ_RTSMF_EN BIT(1)\n#define BIT_BCN_RTSMF_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXPAUSE\t\t\t\t(Offset 0x0522) */\n\n#define BIT_STOP_BCN_HI_MGT BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TXPAUSE\t\t\t\t(Offset 0x0522) */\n\n#define BIT_MAC_STOPCPUMGQ BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXPAUSE\t\t\t\t(Offset 0x0522) */\n\n#define BIT_MAC_STOPBCNQ BIT(6)\n#define BIT_MAC_STOPHIQ BIT(5)\n#define BIT_MAC_STOPMGQ BIT(4)\n#define BIT_MAC_STOPBK BIT(3)\n#define BIT_MAC_STOPBE BIT(2)\n#define BIT_MAC_STOPVI BIT(1)\n#define BIT_MAC_STOPVO BIT(0)\n\n/* 2 REG_DIS_TXREQ_CLR\t\t\t(Offset 0x0523) */\n\n#define BIT_DIS_BT_CCA BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DIS_TXREQ_CLR\t\t\t(Offset 0x0523) */\n\n#define BIT_DIS_TXREQ_CLR_CPUMGQ BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DIS_TXREQ_CLR\t\t\t(Offset 0x0523) */\n\n#define BIT_DIS_TXREQ_CLR_HI BIT(5)\n#define BIT_DIS_TXREQ_CLR_MGQ BIT(4)\n#define BIT_DIS_TXREQ_CLR_VO BIT(3)\n#define BIT_DIS_TXREQ_CLR_VI BIT(2)\n#define BIT_DIS_TXREQ_CLR_BE BIT(1)\n#define BIT_DIS_TXREQ_CLR_BK BIT(0)\n\n/* 2 REG_RD_CTRL\t\t\t\t(Offset 0x0524) */\n\n#define BIT_EN_CLR_TXREQ_INCCA BIT(15)\n#define BIT_DIS_TX_OVER_BCNQ BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RD_CTRL\t\t\t\t(Offset 0x0524) */\n\n#define BIT_EN_BCNERR_INCCCA BIT(13)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RD_CTRL\t\t\t\t(Offset 0x0524) */\n\n#define BIT_EN_BCNERR_INCCA BIT(13)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RD_CTRL\t\t\t\t(Offset 0x0524) */\n\n#define BIT_EN_BCNERR_INEDCCA BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RD_CTRL\t\t\t\t(Offset 0x0524) */\n\n#define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11)\n#define BIT_DIS_TXOP_CFE BIT(10)\n#define BIT_DIS_LSIG_CFE BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RD_CTRL\t\t\t\t(Offset 0x0524) */\n\n#define BIT_DIS_STBC_CFE BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RD_CTRL\t\t\t\t(Offset 0x0524) */\n\n#define BIT_BKQ_RD_INIT_EN BIT(7)\n#define BIT_BEQ_RD_INIT_EN BIT(6)\n#define BIT_VIQ_RD_INIT_EN BIT(5)\n#define BIT_VOQ_RD_INIT_EN BIT(4)\n#define BIT_BKQ_RD_RESP_EN BIT(3)\n#define BIT_BEQ_RD_RESP_EN BIT(2)\n#define BIT_VIQ_RD_RESP_EN BIT(1)\n#define BIT_VOQ_RD_RESP_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBSSID_CTRL\t\t\t\t(Offset 0x0526) */\n\n#define BIT_MBID_BCNQ7_EN BIT(7)\n#define BIT_MBID_BCNQ6_EN BIT(6)\n#define BIT_MBID_BCNQ5_EN BIT(5)\n#define BIT_MBID_BCNQ4_EN BIT(4)\n#define BIT_MBID_BCNQ3_EN BIT(3)\n#define BIT_MBID_BCNQ2_EN BIT(2)\n#define BIT_MBID_BCNQ1_EN BIT(1)\n#define BIT_MBID_BCNQ0_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_P2PPS_CTRL\t\t\t\t(Offset 0x0527) */\n\n#define BIT_P2P_CTW_ALLSTASLEEP BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_P2PPS_CTRL\t\t\t\t(Offset 0x0527) */\n\n#define BIT_P2P_DISTX_SEL BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_P2PPS_CTRL\t\t\t\t(Offset 0x0527) */\n\n#define BIT_PWR_MGT_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_P2PPS_CTRL\t\t\t\t(Offset 0x0527) */\n\n#define BIT_P2P_BCN_AREA_EN BIT(4)\n#define BIT_P2P_CTWND_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_P2PPS_CTRL\t\t\t\t(Offset 0x0527) */\n\n#define BIT_P2P_NOA1_EN BIT(2)\n#define BIT_P2P_NOA0_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_P2PPS_CTRL\t\t\t\t(Offset 0x0527) */\n\n#define BIT_P2P_BCN_SEL BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PKT_LIFETIME_CTRL\t\t\t(Offset 0x0528) */\n\n#define BIT_EN_P2P_CTWND1 BIT(23)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_PKT_LIFETIME_CTRL\t\t\t(Offset 0x0528) */\n\n#define BIT_EN_TBTT_AREA_FOR_BB BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PKT_LIFETIME_CTRL\t\t\t(Offset 0x0528) */\n\n#define BIT_EN_BKF_CLR_TXREQ BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PKT_LIFETIME_CTRL\t\t\t(Offset 0x0528) */\n\n#define BIT_EN_TSFBIT32_RST_P2P BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PKT_LIFETIME_CTRL\t\t\t(Offset 0x0528) */\n\n#define BIT_EN_BCN_TX_BTCCA BIT(20)\n#define BIT_DIS_PKT_TX_ATIM BIT(19)\n#define BIT_DIS_BCN_DIS_CTN BIT(18)\n#define BIT_EN_NAVEND_RST_TXOP BIT(17)\n#define BIT_EN_FILTER_CCA BIT(16)\n\n#define BIT_SHIFT_CCA_FILTER_THRS 8\n#define BIT_MASK_CCA_FILTER_THRS 0xff\n#define BIT_CCA_FILTER_THRS(x)                                                 \\\n\t(((x) & BIT_MASK_CCA_FILTER_THRS) << BIT_SHIFT_CCA_FILTER_THRS)\n#define BITS_CCA_FILTER_THRS                                                   \\\n\t(BIT_MASK_CCA_FILTER_THRS << BIT_SHIFT_CCA_FILTER_THRS)\n#define BIT_CLEAR_CCA_FILTER_THRS(x) ((x) & (~BITS_CCA_FILTER_THRS))\n#define BIT_GET_CCA_FILTER_THRS(x)                                             \\\n\t(((x) >> BIT_SHIFT_CCA_FILTER_THRS) & BIT_MASK_CCA_FILTER_THRS)\n#define BIT_SET_CCA_FILTER_THRS(x, v)                                          \\\n\t(BIT_CLEAR_CCA_FILTER_THRS(x) | BIT_CCA_FILTER_THRS(v))\n\n#define BIT_SHIFT_EDCCA_THRS 0\n#define BIT_MASK_EDCCA_THRS 0xff\n#define BIT_EDCCA_THRS(x) (((x) & BIT_MASK_EDCCA_THRS) << BIT_SHIFT_EDCCA_THRS)\n#define BITS_EDCCA_THRS (BIT_MASK_EDCCA_THRS << BIT_SHIFT_EDCCA_THRS)\n#define BIT_CLEAR_EDCCA_THRS(x) ((x) & (~BITS_EDCCA_THRS))\n#define BIT_GET_EDCCA_THRS(x)                                                  \\\n\t(((x) >> BIT_SHIFT_EDCCA_THRS) & BIT_MASK_EDCCA_THRS)\n#define BIT_SET_EDCCA_THRS(x, v) (BIT_CLEAR_EDCCA_THRS(x) | BIT_EDCCA_THRS(v))\n\n/* 2 REG_P2PPS_SPEC_STATE\t\t\t(Offset 0x052B) */\n\n#define BIT_SPEC_POWER_STATE BIT(7)\n#define BIT_SPEC_CTWINDOW_ON BIT(6)\n#define BIT_SPEC_BEACON_AREA_ON BIT(5)\n#define BIT_SPEC_CTWIN_EARLY_DISTX BIT(4)\n#define BIT_SPEC_NOA1_OFF_PERIOD BIT(3)\n#define BIT_SPEC_FORCE_DOZE1 BIT(2)\n#define BIT_SPEC_NOA0_OFF_PERIOD BIT(1)\n#define BIT_SPEC_FORCE_DOZE0 BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXOP_LIMIT_CTRL\t\t\t(Offset 0x052C) */\n\n#define BIT_SHIFT_TXOP_TBTT_CNT 24\n#define BIT_MASK_TXOP_TBTT_CNT 0xff\n#define BIT_TXOP_TBTT_CNT(x)                                                   \\\n\t(((x) & BIT_MASK_TXOP_TBTT_CNT) << BIT_SHIFT_TXOP_TBTT_CNT)\n#define BITS_TXOP_TBTT_CNT (BIT_MASK_TXOP_TBTT_CNT << BIT_SHIFT_TXOP_TBTT_CNT)\n#define BIT_CLEAR_TXOP_TBTT_CNT(x) ((x) & (~BITS_TXOP_TBTT_CNT))\n#define BIT_GET_TXOP_TBTT_CNT(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXOP_TBTT_CNT) & BIT_MASK_TXOP_TBTT_CNT)\n#define BIT_SET_TXOP_TBTT_CNT(x, v)                                            \\\n\t(BIT_CLEAR_TXOP_TBTT_CNT(x) | BIT_TXOP_TBTT_CNT(v))\n\n#define BIT_SHIFT_TXOP_TBTT_CNT_SEL 20\n#define BIT_MASK_TXOP_TBTT_CNT_SEL 0xf\n#define BIT_TXOP_TBTT_CNT_SEL(x)                                               \\\n\t(((x) & BIT_MASK_TXOP_TBTT_CNT_SEL) << BIT_SHIFT_TXOP_TBTT_CNT_SEL)\n#define BITS_TXOP_TBTT_CNT_SEL                                                 \\\n\t(BIT_MASK_TXOP_TBTT_CNT_SEL << BIT_SHIFT_TXOP_TBTT_CNT_SEL)\n#define BIT_CLEAR_TXOP_TBTT_CNT_SEL(x) ((x) & (~BITS_TXOP_TBTT_CNT_SEL))\n#define BIT_GET_TXOP_TBTT_CNT_SEL(x)                                           \\\n\t(((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL) & BIT_MASK_TXOP_TBTT_CNT_SEL)\n#define BIT_SET_TXOP_TBTT_CNT_SEL(x, v)                                        \\\n\t(BIT_CLEAR_TXOP_TBTT_CNT_SEL(x) | BIT_TXOP_TBTT_CNT_SEL(v))\n\n#define BIT_SHIFT_TXOP_LMT_EN 16\n#define BIT_MASK_TXOP_LMT_EN 0xf\n#define BIT_TXOP_LMT_EN(x)                                                     \\\n\t(((x) & BIT_MASK_TXOP_LMT_EN) << BIT_SHIFT_TXOP_LMT_EN)\n#define BITS_TXOP_LMT_EN (BIT_MASK_TXOP_LMT_EN << BIT_SHIFT_TXOP_LMT_EN)\n#define BIT_CLEAR_TXOP_LMT_EN(x) ((x) & (~BITS_TXOP_LMT_EN))\n#define BIT_GET_TXOP_LMT_EN(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TXOP_LMT_EN) & BIT_MASK_TXOP_LMT_EN)\n#define BIT_SET_TXOP_LMT_EN(x, v)                                              \\\n\t(BIT_CLEAR_TXOP_LMT_EN(x) | BIT_TXOP_LMT_EN(v))\n\n#define BIT_SHIFT_TXOP_LMT_TX_TIME 8\n#define BIT_MASK_TXOP_LMT_TX_TIME 0xff\n#define BIT_TXOP_LMT_TX_TIME(x)                                                \\\n\t(((x) & BIT_MASK_TXOP_LMT_TX_TIME) << BIT_SHIFT_TXOP_LMT_TX_TIME)\n#define BITS_TXOP_LMT_TX_TIME                                                  \\\n\t(BIT_MASK_TXOP_LMT_TX_TIME << BIT_SHIFT_TXOP_LMT_TX_TIME)\n#define BIT_CLEAR_TXOP_LMT_TX_TIME(x) ((x) & (~BITS_TXOP_LMT_TX_TIME))\n#define BIT_GET_TXOP_LMT_TX_TIME(x)                                            \\\n\t(((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME) & BIT_MASK_TXOP_LMT_TX_TIME)\n#define BIT_SET_TXOP_LMT_TX_TIME(x, v)                                         \\\n\t(BIT_CLEAR_TXOP_LMT_TX_TIME(x) | BIT_TXOP_LMT_TX_TIME(v))\n\n#define BIT_TXOP_CNT_TRIGGER_RESET BIT(7)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_TBTT_AREA_BLK_4AC\t\t\t(Offset 0x052C) */\n\n#define BIT_EN_TBTT_AREA_BLK_4AC BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_PS_TIMER_A_V2\t\t\t(Offset 0x052C) */\n\n#define BIT_SHIFT_PS_TIMER_A_V2 0\n#define BIT_MASK_PS_TIMER_A_V2 0xffffffffL\n#define BIT_PS_TIMER_A_V2(x)                                                   \\\n\t(((x) & BIT_MASK_PS_TIMER_A_V2) << BIT_SHIFT_PS_TIMER_A_V2)\n#define BITS_PS_TIMER_A_V2 (BIT_MASK_PS_TIMER_A_V2 << BIT_SHIFT_PS_TIMER_A_V2)\n#define BIT_CLEAR_PS_TIMER_A_V2(x) ((x) & (~BITS_PS_TIMER_A_V2))\n#define BIT_GET_PS_TIMER_A_V2(x)                                               \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_A_V2) & BIT_MASK_PS_TIMER_A_V2)\n#define BIT_SET_PS_TIMER_A_V2(x, v)                                            \\\n\t(BIT_CLEAR_PS_TIMER_A_V2(x) | BIT_PS_TIMER_A_V2(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXOP_LIMIT_CTRL\t\t\t(Offset 0x052C) */\n\n#define BIT_SHIFT_TXOP_LMT_PKT_NUM 0\n#define BIT_MASK_TXOP_LMT_PKT_NUM 0x3f\n#define BIT_TXOP_LMT_PKT_NUM(x)                                                \\\n\t(((x) & BIT_MASK_TXOP_LMT_PKT_NUM) << BIT_SHIFT_TXOP_LMT_PKT_NUM)\n#define BITS_TXOP_LMT_PKT_NUM                                                  \\\n\t(BIT_MASK_TXOP_LMT_PKT_NUM << BIT_SHIFT_TXOP_LMT_PKT_NUM)\n#define BIT_CLEAR_TXOP_LMT_PKT_NUM(x) ((x) & (~BITS_TXOP_LMT_PKT_NUM))\n#define BIT_GET_TXOP_LMT_PKT_NUM(x)                                            \\\n\t(((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM) & BIT_MASK_TXOP_LMT_PKT_NUM)\n#define BIT_SET_TXOP_LMT_PKT_NUM(x, v)                                         \\\n\t(BIT_CLEAR_TXOP_LMT_PKT_NUM(x) | BIT_TXOP_LMT_PKT_NUM(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PON_DIS_TXTIME\t\t\t(Offset 0x0531) */\n\n#define BIT_SHIFT_P2PON_DIS_TXTIME 0\n#define BIT_MASK_P2PON_DIS_TXTIME 0xff\n#define BIT_P2PON_DIS_TXTIME(x)                                                \\\n\t(((x) & BIT_MASK_P2PON_DIS_TXTIME) << BIT_SHIFT_P2PON_DIS_TXTIME)\n#define BITS_P2PON_DIS_TXTIME                                                  \\\n\t(BIT_MASK_P2PON_DIS_TXTIME << BIT_SHIFT_P2PON_DIS_TXTIME)\n#define BIT_CLEAR_P2PON_DIS_TXTIME(x) ((x) & (~BITS_P2PON_DIS_TXTIME))\n#define BIT_GET_P2PON_DIS_TXTIME(x)                                            \\\n\t(((x) >> BIT_SHIFT_P2PON_DIS_TXTIME) & BIT_MASK_P2PON_DIS_TXTIME)\n#define BIT_SET_P2PON_DIS_TXTIME(x, v)                                         \\\n\t(BIT_CLEAR_P2PON_DIS_TXTIME(x) | BIT_P2PON_DIS_TXTIME(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_PS_TIMER_B_V2\t\t\t(Offset 0x0534) */\n\n#define BIT_FTM_PTT_TSF_R2T_SEL_V1 BIT(24)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CCA_TXEN_CNT\t\t\t(Offset 0x0534) */\n\n#define BIT_ENABLE_STOP_UPDATE_NAV BIT(21)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_PS_TIMER_B_V2\t\t\t(Offset 0x0534) */\n\n#define BIT_TBTT_DIG BIT(20)\n#define BIT_FTM_PTT_TSF_T2R_SEL_V1 BIT(20)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CCA_TXEN_CNT\t\t\t(Offset 0x0534) */\n\n#define BIT_CCA_TXEN_CNT_SWITCH BIT(17)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_PS_TIMER_B_V2\t\t\t(Offset 0x0534) */\n\n#define BIT_FTM_PTT_TSF_SEL_V1 BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CCA_TXEN_CNT\t\t\t(Offset 0x0534) */\n\n#define BIT_CCA_TXEN_CNT_EN BIT(16)\n\n#define BIT_SHIFT_CCA_TXEN_BIG_CNT 8\n#define BIT_MASK_CCA_TXEN_BIG_CNT 0xff\n#define BIT_CCA_TXEN_BIG_CNT(x)                                                \\\n\t(((x) & BIT_MASK_CCA_TXEN_BIG_CNT) << BIT_SHIFT_CCA_TXEN_BIG_CNT)\n#define BITS_CCA_TXEN_BIG_CNT                                                  \\\n\t(BIT_MASK_CCA_TXEN_BIG_CNT << BIT_SHIFT_CCA_TXEN_BIG_CNT)\n#define BIT_CLEAR_CCA_TXEN_BIG_CNT(x) ((x) & (~BITS_CCA_TXEN_BIG_CNT))\n#define BIT_GET_CCA_TXEN_BIG_CNT(x)                                            \\\n\t(((x) >> BIT_SHIFT_CCA_TXEN_BIG_CNT) & BIT_MASK_CCA_TXEN_BIG_CNT)\n#define BIT_SET_CCA_TXEN_BIG_CNT(x, v)                                         \\\n\t(BIT_CLEAR_CCA_TXEN_BIG_CNT(x) | BIT_CCA_TXEN_BIG_CNT(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_PS_TIMER_B_V2\t\t\t(Offset 0x0534) */\n\n#define BIT_SHIFT_PS_TIMER_B_V2 0\n#define BIT_MASK_PS_TIMER_B_V2 0xffffffffL\n#define BIT_PS_TIMER_B_V2(x)                                                   \\\n\t(((x) & BIT_MASK_PS_TIMER_B_V2) << BIT_SHIFT_PS_TIMER_B_V2)\n#define BITS_PS_TIMER_B_V2 (BIT_MASK_PS_TIMER_B_V2 << BIT_SHIFT_PS_TIMER_B_V2)\n#define BIT_CLEAR_PS_TIMER_B_V2(x) ((x) & (~BITS_PS_TIMER_B_V2))\n#define BIT_GET_PS_TIMER_B_V2(x)                                               \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_B_V2) & BIT_MASK_PS_TIMER_B_V2)\n#define BIT_SET_PS_TIMER_B_V2(x, v)                                            \\\n\t(BIT_CLEAR_PS_TIMER_B_V2(x) | BIT_PS_TIMER_B_V2(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CCA_TXEN_CNT\t\t\t(Offset 0x0534) */\n\n#define BIT_SHIFT_CCA_TXEN_SMALL_CNT 0\n#define BIT_MASK_CCA_TXEN_SMALL_CNT 0xff\n#define BIT_CCA_TXEN_SMALL_CNT(x)                                              \\\n\t(((x) & BIT_MASK_CCA_TXEN_SMALL_CNT) << BIT_SHIFT_CCA_TXEN_SMALL_CNT)\n#define BITS_CCA_TXEN_SMALL_CNT                                                \\\n\t(BIT_MASK_CCA_TXEN_SMALL_CNT << BIT_SHIFT_CCA_TXEN_SMALL_CNT)\n#define BIT_CLEAR_CCA_TXEN_SMALL_CNT(x) ((x) & (~BITS_CCA_TXEN_SMALL_CNT))\n#define BIT_GET_CCA_TXEN_SMALL_CNT(x)                                          \\\n\t(((x) >> BIT_SHIFT_CCA_TXEN_SMALL_CNT) & BIT_MASK_CCA_TXEN_SMALL_CNT)\n#define BIT_SET_CCA_TXEN_SMALL_CNT(x, v)                                       \\\n\t(BIT_CLEAR_CCA_TXEN_SMALL_CNT(x) | BIT_CCA_TXEN_SMALL_CNT(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_QUEUE_INCOL_THR\t\t\t(Offset 0x0538) */\n\n#define BIT_SHIFT_BK_QUEUE_THR 24\n#define BIT_MASK_BK_QUEUE_THR 0xff\n#define BIT_BK_QUEUE_THR(x)                                                    \\\n\t(((x) & BIT_MASK_BK_QUEUE_THR) << BIT_SHIFT_BK_QUEUE_THR)\n#define BITS_BK_QUEUE_THR (BIT_MASK_BK_QUEUE_THR << BIT_SHIFT_BK_QUEUE_THR)\n#define BIT_CLEAR_BK_QUEUE_THR(x) ((x) & (~BITS_BK_QUEUE_THR))\n#define BIT_GET_BK_QUEUE_THR(x)                                                \\\n\t(((x) >> BIT_SHIFT_BK_QUEUE_THR) & BIT_MASK_BK_QUEUE_THR)\n#define BIT_SET_BK_QUEUE_THR(x, v)                                             \\\n\t(BIT_CLEAR_BK_QUEUE_THR(x) | BIT_BK_QUEUE_THR(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MAX_INTER_COLLISION\t\t\t(Offset 0x0538) */\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_BK 24\n#define BIT_MASK_MAX_INTER_COLLISION_BK 0xff\n#define BIT_MAX_INTER_COLLISION_BK(x)                                          \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_BK)                               \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_BK)\n#define BITS_MAX_INTER_COLLISION_BK                                            \\\n\t(BIT_MASK_MAX_INTER_COLLISION_BK << BIT_SHIFT_MAX_INTER_COLLISION_BK)\n#define BIT_CLEAR_MAX_INTER_COLLISION_BK(x)                                    \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_BK))\n#define BIT_GET_MAX_INTER_COLLISION_BK(x)                                      \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BK) &                           \\\n\t BIT_MASK_MAX_INTER_COLLISION_BK)\n#define BIT_SET_MAX_INTER_COLLISION_BK(x, v)                                   \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_BK(x) | BIT_MAX_INTER_COLLISION_BK(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_QUEUE_INCOL_THR\t\t\t(Offset 0x0538) */\n\n#define BIT_SHIFT_BE_QUEUE_THR 16\n#define BIT_MASK_BE_QUEUE_THR 0xff\n#define BIT_BE_QUEUE_THR(x)                                                    \\\n\t(((x) & BIT_MASK_BE_QUEUE_THR) << BIT_SHIFT_BE_QUEUE_THR)\n#define BITS_BE_QUEUE_THR (BIT_MASK_BE_QUEUE_THR << BIT_SHIFT_BE_QUEUE_THR)\n#define BIT_CLEAR_BE_QUEUE_THR(x) ((x) & (~BITS_BE_QUEUE_THR))\n#define BIT_GET_BE_QUEUE_THR(x)                                                \\\n\t(((x) >> BIT_SHIFT_BE_QUEUE_THR) & BIT_MASK_BE_QUEUE_THR)\n#define BIT_SET_BE_QUEUE_THR(x, v)                                             \\\n\t(BIT_CLEAR_BE_QUEUE_THR(x) | BIT_BE_QUEUE_THR(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MAX_INTER_COLLISION\t\t\t(Offset 0x0538) */\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_BE 16\n#define BIT_MASK_MAX_INTER_COLLISION_BE 0xff\n#define BIT_MAX_INTER_COLLISION_BE(x)                                          \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_BE)                               \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_BE)\n#define BITS_MAX_INTER_COLLISION_BE                                            \\\n\t(BIT_MASK_MAX_INTER_COLLISION_BE << BIT_SHIFT_MAX_INTER_COLLISION_BE)\n#define BIT_CLEAR_MAX_INTER_COLLISION_BE(x)                                    \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_BE))\n#define BIT_GET_MAX_INTER_COLLISION_BE(x)                                      \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BE) &                           \\\n\t BIT_MASK_MAX_INTER_COLLISION_BE)\n#define BIT_SET_MAX_INTER_COLLISION_BE(x, v)                                   \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_BE(x) | BIT_MAX_INTER_COLLISION_BE(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_QUEUE_INCOL_THR\t\t\t(Offset 0x0538) */\n\n#define BIT_SHIFT_VI_QUEUE_THR 8\n#define BIT_MASK_VI_QUEUE_THR 0xff\n#define BIT_VI_QUEUE_THR(x)                                                    \\\n\t(((x) & BIT_MASK_VI_QUEUE_THR) << BIT_SHIFT_VI_QUEUE_THR)\n#define BITS_VI_QUEUE_THR (BIT_MASK_VI_QUEUE_THR << BIT_SHIFT_VI_QUEUE_THR)\n#define BIT_CLEAR_VI_QUEUE_THR(x) ((x) & (~BITS_VI_QUEUE_THR))\n#define BIT_GET_VI_QUEUE_THR(x)                                                \\\n\t(((x) >> BIT_SHIFT_VI_QUEUE_THR) & BIT_MASK_VI_QUEUE_THR)\n#define BIT_SET_VI_QUEUE_THR(x, v)                                             \\\n\t(BIT_CLEAR_VI_QUEUE_THR(x) | BIT_VI_QUEUE_THR(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MAX_INTER_COLLISION\t\t\t(Offset 0x0538) */\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_VI 8\n#define BIT_MASK_MAX_INTER_COLLISION_VI 0xff\n#define BIT_MAX_INTER_COLLISION_VI(x)                                          \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_VI)                               \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_VI)\n#define BITS_MAX_INTER_COLLISION_VI                                            \\\n\t(BIT_MASK_MAX_INTER_COLLISION_VI << BIT_SHIFT_MAX_INTER_COLLISION_VI)\n#define BIT_CLEAR_MAX_INTER_COLLISION_VI(x)                                    \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_VI))\n#define BIT_GET_MAX_INTER_COLLISION_VI(x)                                      \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VI) &                           \\\n\t BIT_MASK_MAX_INTER_COLLISION_VI)\n#define BIT_SET_MAX_INTER_COLLISION_VI(x, v)                                   \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_VI(x) | BIT_MAX_INTER_COLLISION_VI(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_QUEUE_INCOL_THR\t\t\t(Offset 0x0538) */\n\n#define BIT_SHIFT_VO_QUEUE_THR 0\n#define BIT_MASK_VO_QUEUE_THR 0xff\n#define BIT_VO_QUEUE_THR(x)                                                    \\\n\t(((x) & BIT_MASK_VO_QUEUE_THR) << BIT_SHIFT_VO_QUEUE_THR)\n#define BITS_VO_QUEUE_THR (BIT_MASK_VO_QUEUE_THR << BIT_SHIFT_VO_QUEUE_THR)\n#define BIT_CLEAR_VO_QUEUE_THR(x) ((x) & (~BITS_VO_QUEUE_THR))\n#define BIT_GET_VO_QUEUE_THR(x)                                                \\\n\t(((x) >> BIT_SHIFT_VO_QUEUE_THR) & BIT_MASK_VO_QUEUE_THR)\n#define BIT_SET_VO_QUEUE_THR(x, v)                                             \\\n\t(BIT_CLEAR_VO_QUEUE_THR(x) | BIT_VO_QUEUE_THR(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MAX_INTER_COLLISION\t\t\t(Offset 0x0538) */\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_VO 0\n#define BIT_MASK_MAX_INTER_COLLISION_VO 0xff\n#define BIT_MAX_INTER_COLLISION_VO(x)                                          \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_VO)                               \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_VO)\n#define BITS_MAX_INTER_COLLISION_VO                                            \\\n\t(BIT_MASK_MAX_INTER_COLLISION_VO << BIT_SHIFT_MAX_INTER_COLLISION_VO)\n#define BIT_CLEAR_MAX_INTER_COLLISION_VO(x)                                    \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_VO))\n#define BIT_GET_MAX_INTER_COLLISION_VO(x)                                      \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VO) &                           \\\n\t BIT_MASK_MAX_INTER_COLLISION_VO)\n#define BIT_SET_MAX_INTER_COLLISION_VO(x, v)                                   \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_VO(x) | BIT_MAX_INTER_COLLISION_VO(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_QUEUE_INCOL_EN\t\t\t(Offset 0x053C) */\n\n#define BIT_QUEUE_INCOL_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MAX_INTER_COLLISION_CNT\t\t(Offset 0x053C) */\n\n#define BIT_MAX_INTER_COLLISION_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_QUEUE_INCOL_EN\t\t\t(Offset 0x053C) */\n\n#define BIT_SHIFT_BK_TRIGGER_NUM_V1 12\n#define BIT_MASK_BK_TRIGGER_NUM_V1 0xf\n#define BIT_BK_TRIGGER_NUM_V1(x)                                               \\\n\t(((x) & BIT_MASK_BK_TRIGGER_NUM_V1) << BIT_SHIFT_BK_TRIGGER_NUM_V1)\n#define BITS_BK_TRIGGER_NUM_V1                                                 \\\n\t(BIT_MASK_BK_TRIGGER_NUM_V1 << BIT_SHIFT_BK_TRIGGER_NUM_V1)\n#define BIT_CLEAR_BK_TRIGGER_NUM_V1(x) ((x) & (~BITS_BK_TRIGGER_NUM_V1))\n#define BIT_GET_BK_TRIGGER_NUM_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1) & BIT_MASK_BK_TRIGGER_NUM_V1)\n#define BIT_SET_BK_TRIGGER_NUM_V1(x, v)                                        \\\n\t(BIT_CLEAR_BK_TRIGGER_NUM_V1(x) | BIT_BK_TRIGGER_NUM_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MAX_INTER_COLLISION_CNT\t\t(Offset 0x053C) */\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK 12\n#define BIT_MASK_MAX_INTER_COLLISION_CNT_BK 0xf\n#define BIT_MAX_INTER_COLLISION_CNT_BK(x)                                      \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BK)                           \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK)\n#define BITS_MAX_INTER_COLLISION_CNT_BK                                        \\\n\t(BIT_MASK_MAX_INTER_COLLISION_CNT_BK                                   \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK)\n#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK(x)                                \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_CNT_BK))\n#define BIT_GET_MAX_INTER_COLLISION_CNT_BK(x)                                  \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK) &                       \\\n\t BIT_MASK_MAX_INTER_COLLISION_CNT_BK)\n#define BIT_SET_MAX_INTER_COLLISION_CNT_BK(x, v)                               \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK(x) |                             \\\n\t BIT_MAX_INTER_COLLISION_CNT_BK(v))\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_QUEUE_INCOL_EN\t\t\t(Offset 0x053C) */\n\n#define BIT_SHIFT_BE_TRIGGER_NUM 12\n#define BIT_MASK_BE_TRIGGER_NUM 0xf\n#define BIT_BE_TRIGGER_NUM(x)                                                  \\\n\t(((x) & BIT_MASK_BE_TRIGGER_NUM) << BIT_SHIFT_BE_TRIGGER_NUM)\n#define BITS_BE_TRIGGER_NUM                                                    \\\n\t(BIT_MASK_BE_TRIGGER_NUM << BIT_SHIFT_BE_TRIGGER_NUM)\n#define BIT_CLEAR_BE_TRIGGER_NUM(x) ((x) & (~BITS_BE_TRIGGER_NUM))\n#define BIT_GET_BE_TRIGGER_NUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_BE_TRIGGER_NUM) & BIT_MASK_BE_TRIGGER_NUM)\n#define BIT_SET_BE_TRIGGER_NUM(x, v)                                           \\\n\t(BIT_CLEAR_BE_TRIGGER_NUM(x) | BIT_BE_TRIGGER_NUM(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_QUEUE_INCOL_EN\t\t\t(Offset 0x053C) */\n\n#define BIT_SHIFT_BE_TRIGGER_NUM_V1 8\n#define BIT_MASK_BE_TRIGGER_NUM_V1 0xf\n#define BIT_BE_TRIGGER_NUM_V1(x)                                               \\\n\t(((x) & BIT_MASK_BE_TRIGGER_NUM_V1) << BIT_SHIFT_BE_TRIGGER_NUM_V1)\n#define BITS_BE_TRIGGER_NUM_V1                                                 \\\n\t(BIT_MASK_BE_TRIGGER_NUM_V1 << BIT_SHIFT_BE_TRIGGER_NUM_V1)\n#define BIT_CLEAR_BE_TRIGGER_NUM_V1(x) ((x) & (~BITS_BE_TRIGGER_NUM_V1))\n#define BIT_GET_BE_TRIGGER_NUM_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1) & BIT_MASK_BE_TRIGGER_NUM_V1)\n#define BIT_SET_BE_TRIGGER_NUM_V1(x, v)                                        \\\n\t(BIT_CLEAR_BE_TRIGGER_NUM_V1(x) | BIT_BE_TRIGGER_NUM_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MAX_INTER_COLLISION_CNT\t\t(Offset 0x053C) */\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE 8\n#define BIT_MASK_MAX_INTER_COLLISION_CNT_BE 0xf\n#define BIT_MAX_INTER_COLLISION_CNT_BE(x)                                      \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BE)                           \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE)\n#define BITS_MAX_INTER_COLLISION_CNT_BE                                        \\\n\t(BIT_MASK_MAX_INTER_COLLISION_CNT_BE                                   \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE)\n#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE(x)                                \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_CNT_BE))\n#define BIT_GET_MAX_INTER_COLLISION_CNT_BE(x)                                  \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE) &                       \\\n\t BIT_MASK_MAX_INTER_COLLISION_CNT_BE)\n#define BIT_SET_MAX_INTER_COLLISION_CNT_BE(x, v)                               \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE(x) |                             \\\n\t BIT_MAX_INTER_COLLISION_CNT_BE(v))\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_QUEUE_INCOL_EN\t\t\t(Offset 0x053C) */\n\n#define BIT_SHIFT_BK_TRIGGER_NUM 8\n#define BIT_MASK_BK_TRIGGER_NUM 0xf\n#define BIT_BK_TRIGGER_NUM(x)                                                  \\\n\t(((x) & BIT_MASK_BK_TRIGGER_NUM) << BIT_SHIFT_BK_TRIGGER_NUM)\n#define BITS_BK_TRIGGER_NUM                                                    \\\n\t(BIT_MASK_BK_TRIGGER_NUM << BIT_SHIFT_BK_TRIGGER_NUM)\n#define BIT_CLEAR_BK_TRIGGER_NUM(x) ((x) & (~BITS_BK_TRIGGER_NUM))\n#define BIT_GET_BK_TRIGGER_NUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_BK_TRIGGER_NUM) & BIT_MASK_BK_TRIGGER_NUM)\n#define BIT_SET_BK_TRIGGER_NUM(x, v)                                           \\\n\t(BIT_CLEAR_BK_TRIGGER_NUM(x) | BIT_BK_TRIGGER_NUM(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_QUEUE_INCOL_EN\t\t\t(Offset 0x053C) */\n\n#define BIT_SHIFT_VI_TRIGGER_NUM 4\n#define BIT_MASK_VI_TRIGGER_NUM 0xf\n#define BIT_VI_TRIGGER_NUM(x)                                                  \\\n\t(((x) & BIT_MASK_VI_TRIGGER_NUM) << BIT_SHIFT_VI_TRIGGER_NUM)\n#define BITS_VI_TRIGGER_NUM                                                    \\\n\t(BIT_MASK_VI_TRIGGER_NUM << BIT_SHIFT_VI_TRIGGER_NUM)\n#define BIT_CLEAR_VI_TRIGGER_NUM(x) ((x) & (~BITS_VI_TRIGGER_NUM))\n#define BIT_GET_VI_TRIGGER_NUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_VI_TRIGGER_NUM) & BIT_MASK_VI_TRIGGER_NUM)\n#define BIT_SET_VI_TRIGGER_NUM(x, v)                                           \\\n\t(BIT_CLEAR_VI_TRIGGER_NUM(x) | BIT_VI_TRIGGER_NUM(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MAX_INTER_COLLISION_CNT\t\t(Offset 0x053C) */\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI 4\n#define BIT_MASK_MAX_INTER_COLLISION_CNT_VI 0xf\n#define BIT_MAX_INTER_COLLISION_CNT_VI(x)                                      \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VI)                           \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI)\n#define BITS_MAX_INTER_COLLISION_CNT_VI                                        \\\n\t(BIT_MASK_MAX_INTER_COLLISION_CNT_VI                                   \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI)\n#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI(x)                                \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_CNT_VI))\n#define BIT_GET_MAX_INTER_COLLISION_CNT_VI(x)                                  \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI) &                       \\\n\t BIT_MASK_MAX_INTER_COLLISION_CNT_VI)\n#define BIT_SET_MAX_INTER_COLLISION_CNT_VI(x, v)                               \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI(x) |                             \\\n\t BIT_MAX_INTER_COLLISION_CNT_VI(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_QUEUE_INCOL_EN\t\t\t(Offset 0x053C) */\n\n#define BIT_SHIFT_VO_TRIGGER_NUM 0\n#define BIT_MASK_VO_TRIGGER_NUM 0xf\n#define BIT_VO_TRIGGER_NUM(x)                                                  \\\n\t(((x) & BIT_MASK_VO_TRIGGER_NUM) << BIT_SHIFT_VO_TRIGGER_NUM)\n#define BITS_VO_TRIGGER_NUM                                                    \\\n\t(BIT_MASK_VO_TRIGGER_NUM << BIT_SHIFT_VO_TRIGGER_NUM)\n#define BIT_CLEAR_VO_TRIGGER_NUM(x) ((x) & (~BITS_VO_TRIGGER_NUM))\n#define BIT_GET_VO_TRIGGER_NUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_VO_TRIGGER_NUM) & BIT_MASK_VO_TRIGGER_NUM)\n#define BIT_SET_VO_TRIGGER_NUM(x, v)                                           \\\n\t(BIT_CLEAR_VO_TRIGGER_NUM(x) | BIT_VO_TRIGGER_NUM(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MAX_INTER_COLLISION_CNT\t\t(Offset 0x053C) */\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO 0\n#define BIT_MASK_MAX_INTER_COLLISION_CNT_VO 0xf\n#define BIT_MAX_INTER_COLLISION_CNT_VO(x)                                      \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VO)                           \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO)\n#define BITS_MAX_INTER_COLLISION_CNT_VO                                        \\\n\t(BIT_MASK_MAX_INTER_COLLISION_CNT_VO                                   \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO)\n#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO(x)                                \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_CNT_VO))\n#define BIT_GET_MAX_INTER_COLLISION_CNT_VO(x)                                  \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO) &                       \\\n\t BIT_MASK_MAX_INTER_COLLISION_CNT_VO)\n#define BIT_SET_MAX_INTER_COLLISION_CNT_VO(x, v)                               \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO(x) |                             \\\n\t BIT_MAX_INTER_COLLISION_CNT_VO(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TBTT_PROHIBIT\t\t\t(Offset 0x0540) */\n\n#define BIT_SHIFT_TBTT_HOLD_TIME_AP 8\n#define BIT_MASK_TBTT_HOLD_TIME_AP 0xfff\n#define BIT_TBTT_HOLD_TIME_AP(x)                                               \\\n\t(((x) & BIT_MASK_TBTT_HOLD_TIME_AP) << BIT_SHIFT_TBTT_HOLD_TIME_AP)\n#define BITS_TBTT_HOLD_TIME_AP                                                 \\\n\t(BIT_MASK_TBTT_HOLD_TIME_AP << BIT_SHIFT_TBTT_HOLD_TIME_AP)\n#define BIT_CLEAR_TBTT_HOLD_TIME_AP(x) ((x) & (~BITS_TBTT_HOLD_TIME_AP))\n#define BIT_GET_TBTT_HOLD_TIME_AP(x)                                           \\\n\t(((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP) & BIT_MASK_TBTT_HOLD_TIME_AP)\n#define BIT_SET_TBTT_HOLD_TIME_AP(x, v)                                        \\\n\t(BIT_CLEAR_TBTT_HOLD_TIME_AP(x) | BIT_TBTT_HOLD_TIME_AP(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TBTT_PROHIBIT\t\t\t(Offset 0x0540) */\n\n#define BIT_SHIFT_TBTT_HOLD_TIME_INFRA 4\n#define BIT_MASK_TBTT_HOLD_TIME_INFRA 0xf\n#define BIT_TBTT_HOLD_TIME_INFRA(x)                                            \\\n\t(((x) & BIT_MASK_TBTT_HOLD_TIME_INFRA)                                 \\\n\t << BIT_SHIFT_TBTT_HOLD_TIME_INFRA)\n#define BITS_TBTT_HOLD_TIME_INFRA                                              \\\n\t(BIT_MASK_TBTT_HOLD_TIME_INFRA << BIT_SHIFT_TBTT_HOLD_TIME_INFRA)\n#define BIT_CLEAR_TBTT_HOLD_TIME_INFRA(x) ((x) & (~BITS_TBTT_HOLD_TIME_INFRA))\n#define BIT_GET_TBTT_HOLD_TIME_INFRA(x)                                        \\\n\t(((x) >> BIT_SHIFT_TBTT_HOLD_TIME_INFRA) &                             \\\n\t BIT_MASK_TBTT_HOLD_TIME_INFRA)\n#define BIT_SET_TBTT_HOLD_TIME_INFRA(x, v)                                     \\\n\t(BIT_CLEAR_TBTT_HOLD_TIME_INFRA(x) | BIT_TBTT_HOLD_TIME_INFRA(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_P2PPS_STATE\t\t\t\t(Offset 0x0543) */\n\n#define BIT_POWER_STATE BIT(7)\n#define BIT_CTWINDOW_ON BIT(6)\n#define BIT_BEACON_AREA_ON BIT(5)\n#define BIT_CTWIN_EARLY_DISTX BIT(4)\n#define BIT_NOA1_OFF_PERIOD BIT(3)\n#define BIT_FORCE_DOZE1 BIT(2)\n#define BIT_NOA0_OFF_PERIOD BIT(1)\n#define BIT_FORCE_DOZE0 BIT(0)\n\n/* 2 REG_RD_NAV_NXT\t\t\t\t(Offset 0x0544) */\n\n#define BIT_SHIFT_RD_NAV_PROT_NXT 0\n#define BIT_MASK_RD_NAV_PROT_NXT 0xffff\n#define BIT_RD_NAV_PROT_NXT(x)                                                 \\\n\t(((x) & BIT_MASK_RD_NAV_PROT_NXT) << BIT_SHIFT_RD_NAV_PROT_NXT)\n#define BITS_RD_NAV_PROT_NXT                                                   \\\n\t(BIT_MASK_RD_NAV_PROT_NXT << BIT_SHIFT_RD_NAV_PROT_NXT)\n#define BIT_CLEAR_RD_NAV_PROT_NXT(x) ((x) & (~BITS_RD_NAV_PROT_NXT))\n#define BIT_GET_RD_NAV_PROT_NXT(x)                                             \\\n\t(((x) >> BIT_SHIFT_RD_NAV_PROT_NXT) & BIT_MASK_RD_NAV_PROT_NXT)\n#define BIT_SET_RD_NAV_PROT_NXT(x, v)                                          \\\n\t(BIT_CLEAR_RD_NAV_PROT_NXT(x) | BIT_RD_NAV_PROT_NXT(v))\n\n/* 2 REG_NAV_PROT_LEN\t\t\t(Offset 0x0546) */\n\n#define BIT_SHIFT_NAV_PROT_LEN 0\n#define BIT_MASK_NAV_PROT_LEN 0xffff\n#define BIT_NAV_PROT_LEN(x)                                                    \\\n\t(((x) & BIT_MASK_NAV_PROT_LEN) << BIT_SHIFT_NAV_PROT_LEN)\n#define BITS_NAV_PROT_LEN (BIT_MASK_NAV_PROT_LEN << BIT_SHIFT_NAV_PROT_LEN)\n#define BIT_CLEAR_NAV_PROT_LEN(x) ((x) & (~BITS_NAV_PROT_LEN))\n#define BIT_GET_NAV_PROT_LEN(x)                                                \\\n\t(((x) >> BIT_SHIFT_NAV_PROT_LEN) & BIT_MASK_NAV_PROT_LEN)\n#define BIT_SET_NAV_PROT_LEN(x, v)                                             \\\n\t(BIT_CLEAR_NAV_PROT_LEN(x) | BIT_NAV_PROT_LEN(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FTM_CTRL\t\t\t\t(Offset 0x0548) */\n\n#define BIT_SHIFT_FTM_TSF_R2T_PORT 22\n#define BIT_MASK_FTM_TSF_R2T_PORT 0x7\n#define BIT_FTM_TSF_R2T_PORT(x)                                                \\\n\t(((x) & BIT_MASK_FTM_TSF_R2T_PORT) << BIT_SHIFT_FTM_TSF_R2T_PORT)\n#define BITS_FTM_TSF_R2T_PORT                                                  \\\n\t(BIT_MASK_FTM_TSF_R2T_PORT << BIT_SHIFT_FTM_TSF_R2T_PORT)\n#define BIT_CLEAR_FTM_TSF_R2T_PORT(x) ((x) & (~BITS_FTM_TSF_R2T_PORT))\n#define BIT_GET_FTM_TSF_R2T_PORT(x)                                            \\\n\t(((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT) & BIT_MASK_FTM_TSF_R2T_PORT)\n#define BIT_SET_FTM_TSF_R2T_PORT(x, v)                                         \\\n\t(BIT_CLEAR_FTM_TSF_R2T_PORT(x) | BIT_FTM_TSF_R2T_PORT(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTM_PTT\t\t\t\t(Offset 0x0548) */\n\n#define BIT_SHIFT_FTM_PTT_TSF_R2T_SEL 22\n#define BIT_MASK_FTM_PTT_TSF_R2T_SEL 0x7\n#define BIT_FTM_PTT_TSF_R2T_SEL(x)                                             \\\n\t(((x) & BIT_MASK_FTM_PTT_TSF_R2T_SEL) << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL)\n#define BITS_FTM_PTT_TSF_R2T_SEL                                               \\\n\t(BIT_MASK_FTM_PTT_TSF_R2T_SEL << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL)\n#define BIT_CLEAR_FTM_PTT_TSF_R2T_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_R2T_SEL))\n#define BIT_GET_FTM_PTT_TSF_R2T_SEL(x)                                         \\\n\t(((x) >> BIT_SHIFT_FTM_PTT_TSF_R2T_SEL) & BIT_MASK_FTM_PTT_TSF_R2T_SEL)\n#define BIT_SET_FTM_PTT_TSF_R2T_SEL(x, v)                                      \\\n\t(BIT_CLEAR_FTM_PTT_TSF_R2T_SEL(x) | BIT_FTM_PTT_TSF_R2T_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FTM_CTRL\t\t\t\t(Offset 0x0548) */\n\n#define BIT_SHIFT_FTM_TSF_T2R_PORT 19\n#define BIT_MASK_FTM_TSF_T2R_PORT 0x7\n#define BIT_FTM_TSF_T2R_PORT(x)                                                \\\n\t(((x) & BIT_MASK_FTM_TSF_T2R_PORT) << BIT_SHIFT_FTM_TSF_T2R_PORT)\n#define BITS_FTM_TSF_T2R_PORT                                                  \\\n\t(BIT_MASK_FTM_TSF_T2R_PORT << BIT_SHIFT_FTM_TSF_T2R_PORT)\n#define BIT_CLEAR_FTM_TSF_T2R_PORT(x) ((x) & (~BITS_FTM_TSF_T2R_PORT))\n#define BIT_GET_FTM_TSF_T2R_PORT(x)                                            \\\n\t(((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT) & BIT_MASK_FTM_TSF_T2R_PORT)\n#define BIT_SET_FTM_TSF_T2R_PORT(x, v)                                         \\\n\t(BIT_CLEAR_FTM_TSF_T2R_PORT(x) | BIT_FTM_TSF_T2R_PORT(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTM_PTT\t\t\t\t(Offset 0x0548) */\n\n#define BIT_SHIFT_FTM_PTT_TSF_T2R_SEL 19\n#define BIT_MASK_FTM_PTT_TSF_T2R_SEL 0x7\n#define BIT_FTM_PTT_TSF_T2R_SEL(x)                                             \\\n\t(((x) & BIT_MASK_FTM_PTT_TSF_T2R_SEL) << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL)\n#define BITS_FTM_PTT_TSF_T2R_SEL                                               \\\n\t(BIT_MASK_FTM_PTT_TSF_T2R_SEL << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL)\n#define BIT_CLEAR_FTM_PTT_TSF_T2R_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_T2R_SEL))\n#define BIT_GET_FTM_PTT_TSF_T2R_SEL(x)                                         \\\n\t(((x) >> BIT_SHIFT_FTM_PTT_TSF_T2R_SEL) & BIT_MASK_FTM_PTT_TSF_T2R_SEL)\n#define BIT_SET_FTM_PTT_TSF_T2R_SEL(x, v)                                      \\\n\t(BIT_CLEAR_FTM_PTT_TSF_T2R_SEL(x) | BIT_FTM_PTT_TSF_T2R_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FTM_CTRL\t\t\t\t(Offset 0x0548) */\n\n#define BIT_SHIFT_FTM_PTT_PORT 16\n#define BIT_MASK_FTM_PTT_PORT 0x7\n#define BIT_FTM_PTT_PORT(x)                                                    \\\n\t(((x) & BIT_MASK_FTM_PTT_PORT) << BIT_SHIFT_FTM_PTT_PORT)\n#define BITS_FTM_PTT_PORT (BIT_MASK_FTM_PTT_PORT << BIT_SHIFT_FTM_PTT_PORT)\n#define BIT_CLEAR_FTM_PTT_PORT(x) ((x) & (~BITS_FTM_PTT_PORT))\n#define BIT_GET_FTM_PTT_PORT(x)                                                \\\n\t(((x) >> BIT_SHIFT_FTM_PTT_PORT) & BIT_MASK_FTM_PTT_PORT)\n#define BIT_SET_FTM_PTT_PORT(x, v)                                             \\\n\t(BIT_CLEAR_FTM_PTT_PORT(x) | BIT_FTM_PTT_PORT(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTM_PTT\t\t\t\t(Offset 0x0548) */\n\n#define BIT_SHIFT_FTM_PTT_TSF_SEL 16\n#define BIT_MASK_FTM_PTT_TSF_SEL 0x7\n#define BIT_FTM_PTT_TSF_SEL(x)                                                 \\\n\t(((x) & BIT_MASK_FTM_PTT_TSF_SEL) << BIT_SHIFT_FTM_PTT_TSF_SEL)\n#define BITS_FTM_PTT_TSF_SEL                                                   \\\n\t(BIT_MASK_FTM_PTT_TSF_SEL << BIT_SHIFT_FTM_PTT_TSF_SEL)\n#define BIT_CLEAR_FTM_PTT_TSF_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_SEL))\n#define BIT_GET_FTM_PTT_TSF_SEL(x)                                             \\\n\t(((x) >> BIT_SHIFT_FTM_PTT_TSF_SEL) & BIT_MASK_FTM_PTT_TSF_SEL)\n#define BIT_SET_FTM_PTT_TSF_SEL(x, v)                                          \\\n\t(BIT_CLEAR_FTM_PTT_TSF_SEL(x) | BIT_FTM_PTT_TSF_SEL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FTM_CTRL\t\t\t\t(Offset 0x0548) */\n\n#define BIT_SHIFT_FTM_PTT 0\n#define BIT_MASK_FTM_PTT 0xffff\n#define BIT_FTM_PTT(x) (((x) & BIT_MASK_FTM_PTT) << BIT_SHIFT_FTM_PTT)\n#define BITS_FTM_PTT (BIT_MASK_FTM_PTT << BIT_SHIFT_FTM_PTT)\n#define BIT_CLEAR_FTM_PTT(x) ((x) & (~BITS_FTM_PTT))\n#define BIT_GET_FTM_PTT(x) (((x) >> BIT_SHIFT_FTM_PTT) & BIT_MASK_FTM_PTT)\n#define BIT_SET_FTM_PTT(x, v) (BIT_CLEAR_FTM_PTT(x) | BIT_FTM_PTT(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTM_PTT\t\t\t\t(Offset 0x0548) */\n\n#define BIT_SHIFT_FTM_PTT_VALUE 0\n#define BIT_MASK_FTM_PTT_VALUE 0xffff\n#define BIT_FTM_PTT_VALUE(x)                                                   \\\n\t(((x) & BIT_MASK_FTM_PTT_VALUE) << BIT_SHIFT_FTM_PTT_VALUE)\n#define BITS_FTM_PTT_VALUE (BIT_MASK_FTM_PTT_VALUE << BIT_SHIFT_FTM_PTT_VALUE)\n#define BIT_CLEAR_FTM_PTT_VALUE(x) ((x) & (~BITS_FTM_PTT_VALUE))\n#define BIT_GET_FTM_PTT_VALUE(x)                                               \\\n\t(((x) >> BIT_SHIFT_FTM_PTT_VALUE) & BIT_MASK_FTM_PTT_VALUE)\n#define BIT_SET_FTM_PTT_VALUE(x, v)                                            \\\n\t(BIT_CLEAR_FTM_PTT_VALUE(x) | BIT_FTM_PTT_VALUE(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FTM_TSF_CNT\t\t\t\t(Offset 0x054C) */\n\n#define BIT_SHIFT_FTM_TSF_R2T 16\n#define BIT_MASK_FTM_TSF_R2T 0xffff\n#define BIT_FTM_TSF_R2T(x)                                                     \\\n\t(((x) & BIT_MASK_FTM_TSF_R2T) << BIT_SHIFT_FTM_TSF_R2T)\n#define BITS_FTM_TSF_R2T (BIT_MASK_FTM_TSF_R2T << BIT_SHIFT_FTM_TSF_R2T)\n#define BIT_CLEAR_FTM_TSF_R2T(x) ((x) & (~BITS_FTM_TSF_R2T))\n#define BIT_GET_FTM_TSF_R2T(x)                                                 \\\n\t(((x) >> BIT_SHIFT_FTM_TSF_R2T) & BIT_MASK_FTM_TSF_R2T)\n#define BIT_SET_FTM_TSF_R2T(x, v)                                              \\\n\t(BIT_CLEAR_FTM_TSF_R2T(x) | BIT_FTM_TSF_R2T(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTM_TSF\t\t\t\t(Offset 0x054C) */\n\n#define BIT_SHIFT_FTM_T2_TSF 16\n#define BIT_MASK_FTM_T2_TSF 0xffff\n#define BIT_FTM_T2_TSF(x) (((x) & BIT_MASK_FTM_T2_TSF) << BIT_SHIFT_FTM_T2_TSF)\n#define BITS_FTM_T2_TSF (BIT_MASK_FTM_T2_TSF << BIT_SHIFT_FTM_T2_TSF)\n#define BIT_CLEAR_FTM_T2_TSF(x) ((x) & (~BITS_FTM_T2_TSF))\n#define BIT_GET_FTM_T2_TSF(x)                                                  \\\n\t(((x) >> BIT_SHIFT_FTM_T2_TSF) & BIT_MASK_FTM_T2_TSF)\n#define BIT_SET_FTM_T2_TSF(x, v) (BIT_CLEAR_FTM_T2_TSF(x) | BIT_FTM_T2_TSF(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FTM_TSF_CNT\t\t\t\t(Offset 0x054C) */\n\n#define BIT_SHIFT_FTM_TSF_T2R 0\n#define BIT_MASK_FTM_TSF_T2R 0xffff\n#define BIT_FTM_TSF_T2R(x)                                                     \\\n\t(((x) & BIT_MASK_FTM_TSF_T2R) << BIT_SHIFT_FTM_TSF_T2R)\n#define BITS_FTM_TSF_T2R (BIT_MASK_FTM_TSF_T2R << BIT_SHIFT_FTM_TSF_T2R)\n#define BIT_CLEAR_FTM_TSF_T2R(x) ((x) & (~BITS_FTM_TSF_T2R))\n#define BIT_GET_FTM_TSF_T2R(x)                                                 \\\n\t(((x) >> BIT_SHIFT_FTM_TSF_T2R) & BIT_MASK_FTM_TSF_T2R)\n#define BIT_SET_FTM_TSF_T2R(x, v)                                              \\\n\t(BIT_CLEAR_FTM_TSF_T2R(x) | BIT_FTM_TSF_T2R(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FTM_TSF\t\t\t\t(Offset 0x054C) */\n\n#define BIT_SHIFT_FTM_T1_TSF 0\n#define BIT_MASK_FTM_T1_TSF 0xffff\n#define BIT_FTM_T1_TSF(x) (((x) & BIT_MASK_FTM_T1_TSF) << BIT_SHIFT_FTM_T1_TSF)\n#define BITS_FTM_T1_TSF (BIT_MASK_FTM_T1_TSF << BIT_SHIFT_FTM_T1_TSF)\n#define BIT_CLEAR_FTM_T1_TSF(x) ((x) & (~BITS_FTM_T1_TSF))\n#define BIT_GET_FTM_T1_TSF(x)                                                  \\\n\t(((x) >> BIT_SHIFT_FTM_T1_TSF) & BIT_MASK_FTM_T1_TSF)\n#define BIT_SET_FTM_T1_TSF(x, v) (BIT_CLEAR_FTM_T1_TSF(x) | BIT_FTM_T1_TSF(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_CTRL\t\t\t\t(Offset 0x0550) */\n\n#define BIT_P0_EN_TXBCN_RPT BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BCN_CTRL\t\t\t\t(Offset 0x0550) */\n\n#define BIT_EN_BCN_FUNCTION BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BCN_CTRL\t\t\t\t(Offset 0x0550) */\n\n#define BIT_EN_TXBCN_RPT BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_CTRL\t\t\t\t(Offset 0x0550) */\n\n#define BIT_P0_EN_RXBCN_RPT BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BCN_CTRL\t\t\t\t(Offset 0x0550) */\n\n#define BIT_DIS_BCNQ_SUB BIT(1)\n\n/* 2 REG_BCN_CTRL1\t\t\t\t(Offset 0x0551) */\n\n#define BIT_DIS_RX_BSSID_FIT1 BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_CTRL_CLINT0\t\t\t(Offset 0x0551) */\n\n#define BIT_CLI0_DIS_RX_BSSID_FIT BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BCN_CTRL1\t\t\t\t(Offset 0x0551) */\n\n#define BIT_DIS_TSF1_UDT BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_CTRL_CLINT0\t\t\t(Offset 0x0551) */\n\n#define BIT_CLI0_DIS_TSF_UDT BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BCN_CTRL1\t\t\t\t(Offset 0x0551) */\n\n#define BIT_EN_BCN1_FUNCTION BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_CTRL_CLINT0\t\t\t(Offset 0x0551) */\n\n#define BIT_CLI0_EN_BCN_FUNCTION BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BCN_CTRL1\t\t\t\t(Offset 0x0551) */\n\n#define BIT_EN_TXBCN1_RPT BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_CTRL_CLINT0\t\t\t(Offset 0x0551) */\n\n#define BIT_CLI0_EN_RXBCN_RPT BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_BCN_CTRL_CLINT0\t\t\t(Offset 0x0551) */\n\n#define BIT_CLI0_EN_BCN_RPT BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BCN_CTRL1\t\t\t\t(Offset 0x0551) */\n\n#define BIT_DIS_BCNQ1_SUB BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_CTRL_CLINT0\t\t\t(Offset 0x0551) */\n\n#define BIT_CLI0_ENP2P_CTWINDOW BIT(1)\n#define BIT_CLI0_ENP2P_BCNQ_AREA BIT(0)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_MBID_NUM\t\t\t\t(Offset 0x0552) */\n\n#define BIT_SHIFT_MBID_BCN_NUM_V2 4\n#define BIT_MASK_MBID_BCN_NUM_V2 0xf\n#define BIT_MBID_BCN_NUM_V2(x)                                                 \\\n\t(((x) & BIT_MASK_MBID_BCN_NUM_V2) << BIT_SHIFT_MBID_BCN_NUM_V2)\n#define BITS_MBID_BCN_NUM_V2                                                   \\\n\t(BIT_MASK_MBID_BCN_NUM_V2 << BIT_SHIFT_MBID_BCN_NUM_V2)\n#define BIT_CLEAR_MBID_BCN_NUM_V2(x) ((x) & (~BITS_MBID_BCN_NUM_V2))\n#define BIT_GET_MBID_BCN_NUM_V2(x)                                             \\\n\t(((x) >> BIT_SHIFT_MBID_BCN_NUM_V2) & BIT_MASK_MBID_BCN_NUM_V2)\n#define BIT_SET_MBID_BCN_NUM_V2(x, v)                                          \\\n\t(BIT_CLEAR_MBID_BCN_NUM_V2(x) | BIT_MBID_BCN_NUM_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBID_NUM\t\t\t\t(Offset 0x0552) */\n\n#define BIT_EN_PRE_DL_BEACON BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBID_NUM\t\t\t\t(Offset 0x0552) */\n\n#define BIT_SHIFT_MBID_BCN_NUM 0\n#define BIT_MASK_MBID_BCN_NUM 0x7\n#define BIT_MBID_BCN_NUM(x)                                                    \\\n\t(((x) & BIT_MASK_MBID_BCN_NUM) << BIT_SHIFT_MBID_BCN_NUM)\n#define BITS_MBID_BCN_NUM (BIT_MASK_MBID_BCN_NUM << BIT_SHIFT_MBID_BCN_NUM)\n#define BIT_CLEAR_MBID_BCN_NUM(x) ((x) & (~BITS_MBID_BCN_NUM))\n#define BIT_GET_MBID_BCN_NUM(x)                                                \\\n\t(((x) >> BIT_SHIFT_MBID_BCN_NUM) & BIT_MASK_MBID_BCN_NUM)\n#define BIT_SET_MBID_BCN_NUM(x, v)                                             \\\n\t(BIT_CLEAR_MBID_BCN_NUM(x) | BIT_MBID_BCN_NUM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DUAL_TSF_RST\t\t\t(Offset 0x0553) */\n\n#define BIT_P2P_PWR_RST1 BIT(6)\n#define BIT_SCHEDULER_RST BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DUAL_TSF_RST\t\t\t(Offset 0x0553) */\n\n#define BIT_FREECNT_RST BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DUAL_TSF_RST\t\t\t(Offset 0x0553) */\n\n#define BIT_P2P_PWR_RST0 BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DUAL_TSF_RST\t\t\t(Offset 0x0553) */\n\n#define BIT_TSFTR_CLI3_RST BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DUAL_TSF_RST\t\t\t(Offset 0x0553) */\n\n#define BIT_TSFTR1_SYNC_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DUAL_TSF_RST\t\t\t(Offset 0x0553) */\n\n#define BIT_TSFTR_CLI2_RST BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DUAL_TSF_RST\t\t\t(Offset 0x0553) */\n\n#define BIT_TSFTR_SYNC_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DUAL_TSF_RST\t\t\t(Offset 0x0553) */\n\n#define BIT_TSFTR_CLI1_RST BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DUAL_TSF_RST\t\t\t(Offset 0x0553) */\n\n#define BIT_TSFTR1_RST BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DUAL_TSF_RST\t\t\t(Offset 0x0553) */\n\n#define BIT_TSFTR_CLI0_RST BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DUAL_TSF_RST\t\t\t(Offset 0x0553) */\n\n#define BIT_TSFTR_RST BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MBSSID_BCN_SPACE\t\t\t(Offset 0x0554) */\n\n#define BIT_SHIFT_BCN_TIMER_SEL_FWRD 28\n#define BIT_MASK_BCN_TIMER_SEL_FWRD 0x7\n#define BIT_BCN_TIMER_SEL_FWRD(x)                                              \\\n\t(((x) & BIT_MASK_BCN_TIMER_SEL_FWRD) << BIT_SHIFT_BCN_TIMER_SEL_FWRD)\n#define BITS_BCN_TIMER_SEL_FWRD                                                \\\n\t(BIT_MASK_BCN_TIMER_SEL_FWRD << BIT_SHIFT_BCN_TIMER_SEL_FWRD)\n#define BIT_CLEAR_BCN_TIMER_SEL_FWRD(x) ((x) & (~BITS_BCN_TIMER_SEL_FWRD))\n#define BIT_GET_BCN_TIMER_SEL_FWRD(x)                                          \\\n\t(((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD) & BIT_MASK_BCN_TIMER_SEL_FWRD)\n#define BIT_SET_BCN_TIMER_SEL_FWRD(x, v)                                       \\\n\t(BIT_CLEAR_BCN_TIMER_SEL_FWRD(x) | BIT_BCN_TIMER_SEL_FWRD(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBSSID_BCN_SPACE\t\t\t(Offset 0x0554) */\n\n#define BIT_SHIFT_BCN_SPACE1 16\n#define BIT_MASK_BCN_SPACE1 0xffff\n#define BIT_BCN_SPACE1(x) (((x) & BIT_MASK_BCN_SPACE1) << BIT_SHIFT_BCN_SPACE1)\n#define BITS_BCN_SPACE1 (BIT_MASK_BCN_SPACE1 << BIT_SHIFT_BCN_SPACE1)\n#define BIT_CLEAR_BCN_SPACE1(x) ((x) & (~BITS_BCN_SPACE1))\n#define BIT_GET_BCN_SPACE1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE1) & BIT_MASK_BCN_SPACE1)\n#define BIT_SET_BCN_SPACE1(x, v) (BIT_CLEAR_BCN_SPACE1(x) | BIT_BCN_SPACE1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MBSSID_BCN_SPACE\t\t\t(Offset 0x0554) */\n\n#define BIT_SHIFT_BCN_SPACE_CLINT0 16\n#define BIT_MASK_BCN_SPACE_CLINT0 0xfff\n#define BIT_BCN_SPACE_CLINT0(x)                                                \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT0) << BIT_SHIFT_BCN_SPACE_CLINT0)\n#define BITS_BCN_SPACE_CLINT0                                                  \\\n\t(BIT_MASK_BCN_SPACE_CLINT0 << BIT_SHIFT_BCN_SPACE_CLINT0)\n#define BIT_CLEAR_BCN_SPACE_CLINT0(x) ((x) & (~BITS_BCN_SPACE_CLINT0))\n#define BIT_GET_BCN_SPACE_CLINT0(x)                                            \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT0) & BIT_MASK_BCN_SPACE_CLINT0)\n#define BIT_SET_BCN_SPACE_CLINT0(x, v)                                         \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT0(x) | BIT_BCN_SPACE_CLINT0(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBSSID_BCN_SPACE\t\t\t(Offset 0x0554) */\n\n#define BIT_SHIFT_BCN_SPACE0 0\n#define BIT_MASK_BCN_SPACE0 0xffff\n#define BIT_BCN_SPACE0(x) (((x) & BIT_MASK_BCN_SPACE0) << BIT_SHIFT_BCN_SPACE0)\n#define BITS_BCN_SPACE0 (BIT_MASK_BCN_SPACE0 << BIT_SHIFT_BCN_SPACE0)\n#define BIT_CLEAR_BCN_SPACE0(x) ((x) & (~BITS_BCN_SPACE0))\n#define BIT_GET_BCN_SPACE0(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE0) & BIT_MASK_BCN_SPACE0)\n#define BIT_SET_BCN_SPACE0(x, v) (BIT_CLEAR_BCN_SPACE0(x) | BIT_BCN_SPACE0(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ATIMWND\t\t\t\t(Offset 0x055A) */\n\n#define BIT_SHIFT_ATIMWND 0\n#define BIT_MASK_ATIMWND 0xffff\n#define BIT_ATIMWND(x) (((x) & BIT_MASK_ATIMWND) << BIT_SHIFT_ATIMWND)\n#define BITS_ATIMWND (BIT_MASK_ATIMWND << BIT_SHIFT_ATIMWND)\n#define BIT_CLEAR_ATIMWND(x) ((x) & (~BITS_ATIMWND))\n#define BIT_GET_ATIMWND(x) (((x) >> BIT_SHIFT_ATIMWND) & BIT_MASK_ATIMWND)\n#define BIT_SET_ATIMWND(x, v) (BIT_CLEAR_ATIMWND(x) | BIT_ATIMWND(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ATIMWND\t\t\t\t(Offset 0x055A) */\n\n#define BIT_SHIFT_ATIMWND0 0\n#define BIT_MASK_ATIMWND0 0xffff\n#define BIT_ATIMWND0(x) (((x) & BIT_MASK_ATIMWND0) << BIT_SHIFT_ATIMWND0)\n#define BITS_ATIMWND0 (BIT_MASK_ATIMWND0 << BIT_SHIFT_ATIMWND0)\n#define BIT_CLEAR_ATIMWND0(x) ((x) & (~BITS_ATIMWND0))\n#define BIT_GET_ATIMWND0(x) (((x) >> BIT_SHIFT_ATIMWND0) & BIT_MASK_ATIMWND0)\n#define BIT_SET_ATIMWND0(x, v) (BIT_CLEAR_ATIMWND0(x) | BIT_ATIMWND0(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_USTIME_TSF\t\t\t\t(Offset 0x055C) */\n\n#define BIT_SHIFT_USTIME_TSF_V1 0\n#define BIT_MASK_USTIME_TSF_V1 0xff\n#define BIT_USTIME_TSF_V1(x)                                                   \\\n\t(((x) & BIT_MASK_USTIME_TSF_V1) << BIT_SHIFT_USTIME_TSF_V1)\n#define BITS_USTIME_TSF_V1 (BIT_MASK_USTIME_TSF_V1 << BIT_SHIFT_USTIME_TSF_V1)\n#define BIT_CLEAR_USTIME_TSF_V1(x) ((x) & (~BITS_USTIME_TSF_V1))\n#define BIT_GET_USTIME_TSF_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_USTIME_TSF_V1) & BIT_MASK_USTIME_TSF_V1)\n#define BIT_SET_USTIME_TSF_V1(x, v)                                            \\\n\t(BIT_CLEAR_USTIME_TSF_V1(x) | BIT_USTIME_TSF_V1(v))\n\n/* 2 REG_BCN_MAX_ERR\t\t\t\t(Offset 0x055D) */\n\n#define BIT_SHIFT_BCN_MAX_ERR 0\n#define BIT_MASK_BCN_MAX_ERR 0xff\n#define BIT_BCN_MAX_ERR(x)                                                     \\\n\t(((x) & BIT_MASK_BCN_MAX_ERR) << BIT_SHIFT_BCN_MAX_ERR)\n#define BITS_BCN_MAX_ERR (BIT_MASK_BCN_MAX_ERR << BIT_SHIFT_BCN_MAX_ERR)\n#define BIT_CLEAR_BCN_MAX_ERR(x) ((x) & (~BITS_BCN_MAX_ERR))\n#define BIT_GET_BCN_MAX_ERR(x)                                                 \\\n\t(((x) >> BIT_SHIFT_BCN_MAX_ERR) & BIT_MASK_BCN_MAX_ERR)\n#define BIT_SET_BCN_MAX_ERR(x, v)                                              \\\n\t(BIT_CLEAR_BCN_MAX_ERR(x) | BIT_BCN_MAX_ERR(v))\n\n/* 2 REG_RXTSF_OFFSET_CCK\t\t\t(Offset 0x055E) */\n\n#define BIT_SHIFT_CCK_RXTSF_OFFSET 0\n#define BIT_MASK_CCK_RXTSF_OFFSET 0xff\n#define BIT_CCK_RXTSF_OFFSET(x)                                                \\\n\t(((x) & BIT_MASK_CCK_RXTSF_OFFSET) << BIT_SHIFT_CCK_RXTSF_OFFSET)\n#define BITS_CCK_RXTSF_OFFSET                                                  \\\n\t(BIT_MASK_CCK_RXTSF_OFFSET << BIT_SHIFT_CCK_RXTSF_OFFSET)\n#define BIT_CLEAR_CCK_RXTSF_OFFSET(x) ((x) & (~BITS_CCK_RXTSF_OFFSET))\n#define BIT_GET_CCK_RXTSF_OFFSET(x)                                            \\\n\t(((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET) & BIT_MASK_CCK_RXTSF_OFFSET)\n#define BIT_SET_CCK_RXTSF_OFFSET(x, v)                                         \\\n\t(BIT_CLEAR_CCK_RXTSF_OFFSET(x) | BIT_CCK_RXTSF_OFFSET(v))\n\n/* 2 REG_RXTSF_OFFSET_OFDM\t\t\t(Offset 0x055F) */\n\n#define BIT_SHIFT_OFDM_RXTSF_OFFSET 0\n#define BIT_MASK_OFDM_RXTSF_OFFSET 0xff\n#define BIT_OFDM_RXTSF_OFFSET(x)                                               \\\n\t(((x) & BIT_MASK_OFDM_RXTSF_OFFSET) << BIT_SHIFT_OFDM_RXTSF_OFFSET)\n#define BITS_OFDM_RXTSF_OFFSET                                                 \\\n\t(BIT_MASK_OFDM_RXTSF_OFFSET << BIT_SHIFT_OFDM_RXTSF_OFFSET)\n#define BIT_CLEAR_OFDM_RXTSF_OFFSET(x) ((x) & (~BITS_OFDM_RXTSF_OFFSET))\n#define BIT_GET_OFDM_RXTSF_OFFSET(x)                                           \\\n\t(((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET) & BIT_MASK_OFDM_RXTSF_OFFSET)\n#define BIT_SET_OFDM_RXTSF_OFFSET(x, v)                                        \\\n\t(BIT_CLEAR_OFDM_RXTSF_OFFSET(x) | BIT_OFDM_RXTSF_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TSFTR\t\t\t\t(Offset 0x0560) */\n\n#define BIT_SHIFT_TSF_TIMER 0\n#define BIT_MASK_TSF_TIMER 0xffffffffffffffffL\n#define BIT_TSF_TIMER(x) (((x) & BIT_MASK_TSF_TIMER) << BIT_SHIFT_TSF_TIMER)\n#define BITS_TSF_TIMER (BIT_MASK_TSF_TIMER << BIT_SHIFT_TSF_TIMER)\n#define BIT_CLEAR_TSF_TIMER(x) ((x) & (~BITS_TSF_TIMER))\n#define BIT_GET_TSF_TIMER(x) (((x) >> BIT_SHIFT_TSF_TIMER) & BIT_MASK_TSF_TIMER)\n#define BIT_SET_TSF_TIMER(x, v) (BIT_CLEAR_TSF_TIMER(x) | BIT_TSF_TIMER(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TSFTR0_L\t\t\t\t(Offset 0x0560) */\n\n#define BIT_SHIFT_TSF0_TIMER_L 0\n#define BIT_MASK_TSF0_TIMER_L 0xffffffffL\n#define BIT_TSF0_TIMER_L(x)                                                    \\\n\t(((x) & BIT_MASK_TSF0_TIMER_L) << BIT_SHIFT_TSF0_TIMER_L)\n#define BITS_TSF0_TIMER_L (BIT_MASK_TSF0_TIMER_L << BIT_SHIFT_TSF0_TIMER_L)\n#define BIT_CLEAR_TSF0_TIMER_L(x) ((x) & (~BITS_TSF0_TIMER_L))\n#define BIT_GET_TSF0_TIMER_L(x)                                                \\\n\t(((x) >> BIT_SHIFT_TSF0_TIMER_L) & BIT_MASK_TSF0_TIMER_L)\n#define BIT_SET_TSF0_TIMER_L(x, v)                                             \\\n\t(BIT_CLEAR_TSF0_TIMER_L(x) | BIT_TSF0_TIMER_L(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TSFTR\t\t\t\t(Offset 0x0560) */\n\n#define BIT_SHIFT_TSF_TIMER_V1 0\n#define BIT_MASK_TSF_TIMER_V1 0xffffffffL\n#define BIT_TSF_TIMER_V1(x)                                                    \\\n\t(((x) & BIT_MASK_TSF_TIMER_V1) << BIT_SHIFT_TSF_TIMER_V1)\n#define BITS_TSF_TIMER_V1 (BIT_MASK_TSF_TIMER_V1 << BIT_SHIFT_TSF_TIMER_V1)\n#define BIT_CLEAR_TSF_TIMER_V1(x) ((x) & (~BITS_TSF_TIMER_V1))\n#define BIT_GET_TSF_TIMER_V1(x)                                                \\\n\t(((x) >> BIT_SHIFT_TSF_TIMER_V1) & BIT_MASK_TSF_TIMER_V1)\n#define BIT_SET_TSF_TIMER_V1(x, v)                                             \\\n\t(BIT_CLEAR_TSF_TIMER_V1(x) | BIT_TSF_TIMER_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TSFTR0_H\t\t\t\t(Offset 0x0564) */\n\n#define BIT_SHIFT_TSF0_TIMER_H 0\n#define BIT_MASK_TSF0_TIMER_H 0xffffffffL\n#define BIT_TSF0_TIMER_H(x)                                                    \\\n\t(((x) & BIT_MASK_TSF0_TIMER_H) << BIT_SHIFT_TSF0_TIMER_H)\n#define BITS_TSF0_TIMER_H (BIT_MASK_TSF0_TIMER_H << BIT_SHIFT_TSF0_TIMER_H)\n#define BIT_CLEAR_TSF0_TIMER_H(x) ((x) & (~BITS_TSF0_TIMER_H))\n#define BIT_GET_TSF0_TIMER_H(x)                                                \\\n\t(((x) >> BIT_SHIFT_TSF0_TIMER_H) & BIT_MASK_TSF0_TIMER_H)\n#define BIT_SET_TSF0_TIMER_H(x, v)                                             \\\n\t(BIT_CLEAR_TSF0_TIMER_H(x) | BIT_TSF0_TIMER_H(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TSFTR_1\t\t\t\t(Offset 0x0564) */\n\n#define BIT_SHIFT_TSF_TIMER_V2 0\n#define BIT_MASK_TSF_TIMER_V2 0xffffffffL\n#define BIT_TSF_TIMER_V2(x)                                                    \\\n\t(((x) & BIT_MASK_TSF_TIMER_V2) << BIT_SHIFT_TSF_TIMER_V2)\n#define BITS_TSF_TIMER_V2 (BIT_MASK_TSF_TIMER_V2 << BIT_SHIFT_TSF_TIMER_V2)\n#define BIT_CLEAR_TSF_TIMER_V2(x) ((x) & (~BITS_TSF_TIMER_V2))\n#define BIT_GET_TSF_TIMER_V2(x)                                                \\\n\t(((x) >> BIT_SHIFT_TSF_TIMER_V2) & BIT_MASK_TSF_TIMER_V2)\n#define BIT_SET_TSF_TIMER_V2(x, v)                                             \\\n\t(BIT_CLEAR_TSF_TIMER_V2(x) | BIT_TSF_TIMER_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TSFTR1\t\t\t\t(Offset 0x0568) */\n\n#define BIT_SHIFT_TSF_TIMER1 0\n#define BIT_MASK_TSF_TIMER1 0xffffffffffffffffL\n#define BIT_TSF_TIMER1(x) (((x) & BIT_MASK_TSF_TIMER1) << BIT_SHIFT_TSF_TIMER1)\n#define BITS_TSF_TIMER1 (BIT_MASK_TSF_TIMER1 << BIT_SHIFT_TSF_TIMER1)\n#define BIT_CLEAR_TSF_TIMER1(x) ((x) & (~BITS_TSF_TIMER1))\n#define BIT_GET_TSF_TIMER1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_TSF_TIMER1) & BIT_MASK_TSF_TIMER1)\n#define BIT_SET_TSF_TIMER1(x, v) (BIT_CLEAR_TSF_TIMER1(x) | BIT_TSF_TIMER1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TSFTR1_L\t\t\t\t(Offset 0x0568) */\n\n#define BIT_SHIFT_TSF1_TIMER_L 0\n#define BIT_MASK_TSF1_TIMER_L 0xffffffffL\n#define BIT_TSF1_TIMER_L(x)                                                    \\\n\t(((x) & BIT_MASK_TSF1_TIMER_L) << BIT_SHIFT_TSF1_TIMER_L)\n#define BITS_TSF1_TIMER_L (BIT_MASK_TSF1_TIMER_L << BIT_SHIFT_TSF1_TIMER_L)\n#define BIT_CLEAR_TSF1_TIMER_L(x) ((x) & (~BITS_TSF1_TIMER_L))\n#define BIT_GET_TSF1_TIMER_L(x)                                                \\\n\t(((x) >> BIT_SHIFT_TSF1_TIMER_L) & BIT_MASK_TSF1_TIMER_L)\n#define BIT_SET_TSF1_TIMER_L(x, v)                                             \\\n\t(BIT_CLEAR_TSF1_TIMER_L(x) | BIT_TSF1_TIMER_L(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_FREERUN_CNT\t\t\t\t(Offset 0x0568) */\n\n#define BIT_SHIFT_FREERUN_CNT 0\n#define BIT_MASK_FREERUN_CNT 0xffffffffffffffffL\n#define BIT_FREERUN_CNT(x)                                                     \\\n\t(((x) & BIT_MASK_FREERUN_CNT) << BIT_SHIFT_FREERUN_CNT)\n#define BITS_FREERUN_CNT (BIT_MASK_FREERUN_CNT << BIT_SHIFT_FREERUN_CNT)\n#define BIT_CLEAR_FREERUN_CNT(x) ((x) & (~BITS_FREERUN_CNT))\n#define BIT_GET_FREERUN_CNT(x)                                                 \\\n\t(((x) >> BIT_SHIFT_FREERUN_CNT) & BIT_MASK_FREERUN_CNT)\n#define BIT_SET_FREERUN_CNT(x, v)                                              \\\n\t(BIT_CLEAR_FREERUN_CNT(x) | BIT_FREERUN_CNT(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FREERUN_CNT\t\t\t\t(Offset 0x0568) */\n\n#define BIT_SHIFT_FREERUN_CNT_V1 0\n#define BIT_MASK_FREERUN_CNT_V1 0xffffffffL\n#define BIT_FREERUN_CNT_V1(x)                                                  \\\n\t(((x) & BIT_MASK_FREERUN_CNT_V1) << BIT_SHIFT_FREERUN_CNT_V1)\n#define BITS_FREERUN_CNT_V1                                                    \\\n\t(BIT_MASK_FREERUN_CNT_V1 << BIT_SHIFT_FREERUN_CNT_V1)\n#define BIT_CLEAR_FREERUN_CNT_V1(x) ((x) & (~BITS_FREERUN_CNT_V1))\n#define BIT_GET_FREERUN_CNT_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_FREERUN_CNT_V1) & BIT_MASK_FREERUN_CNT_V1)\n#define BIT_SET_FREERUN_CNT_V1(x, v)                                           \\\n\t(BIT_CLEAR_FREERUN_CNT_V1(x) | BIT_FREERUN_CNT_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TSFTR1_H\t\t\t\t(Offset 0x056C) */\n\n#define BIT_SHIFT_TSF1_TIMER_H 0\n#define BIT_MASK_TSF1_TIMER_H 0xffffffffL\n#define BIT_TSF1_TIMER_H(x)                                                    \\\n\t(((x) & BIT_MASK_TSF1_TIMER_H) << BIT_SHIFT_TSF1_TIMER_H)\n#define BITS_TSF1_TIMER_H (BIT_MASK_TSF1_TIMER_H << BIT_SHIFT_TSF1_TIMER_H)\n#define BIT_CLEAR_TSF1_TIMER_H(x) ((x) & (~BITS_TSF1_TIMER_H))\n#define BIT_GET_TSF1_TIMER_H(x)                                                \\\n\t(((x) >> BIT_SHIFT_TSF1_TIMER_H) & BIT_MASK_TSF1_TIMER_H)\n#define BIT_SET_TSF1_TIMER_H(x, v)                                             \\\n\t(BIT_CLEAR_TSF1_TIMER_H(x) | BIT_TSF1_TIMER_H(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FREERUN_CNT_1\t\t\t(Offset 0x056C) */\n\n#define BIT_SHIFT_FREERUN_CNT_V2 0\n#define BIT_MASK_FREERUN_CNT_V2 0xffffffffL\n#define BIT_FREERUN_CNT_V2(x)                                                  \\\n\t(((x) & BIT_MASK_FREERUN_CNT_V2) << BIT_SHIFT_FREERUN_CNT_V2)\n#define BITS_FREERUN_CNT_V2                                                    \\\n\t(BIT_MASK_FREERUN_CNT_V2 << BIT_SHIFT_FREERUN_CNT_V2)\n#define BIT_CLEAR_FREERUN_CNT_V2(x) ((x) & (~BITS_FREERUN_CNT_V2))\n#define BIT_GET_FREERUN_CNT_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_FREERUN_CNT_V2) & BIT_MASK_FREERUN_CNT_V2)\n#define BIT_SET_FREERUN_CNT_V2(x, v)                                           \\\n\t(BIT_CLEAR_FREERUN_CNT_V2(x) | BIT_FREERUN_CNT_V2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ATIMWND1\t\t\t\t(Offset 0x0570) */\n\n#define BIT_SHIFT_ATIMWND1 0\n#define BIT_MASK_ATIMWND1 0xffff\n#define BIT_ATIMWND1(x) (((x) & BIT_MASK_ATIMWND1) << BIT_SHIFT_ATIMWND1)\n#define BITS_ATIMWND1 (BIT_MASK_ATIMWND1 << BIT_SHIFT_ATIMWND1)\n#define BIT_CLEAR_ATIMWND1(x) ((x) & (~BITS_ATIMWND1))\n#define BIT_GET_ATIMWND1(x) (((x) >> BIT_SHIFT_ATIMWND1) & BIT_MASK_ATIMWND1)\n#define BIT_SET_ATIMWND1(x, v) (BIT_CLEAR_ATIMWND1(x) | BIT_ATIMWND1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_ATIMWND1_V1\t\t\t\t(Offset 0x0570) */\n\n#define BIT_SHIFT_ATIMWND1_V2 0\n#define BIT_MASK_ATIMWND1_V2 0xffff\n#define BIT_ATIMWND1_V2(x)                                                     \\\n\t(((x) & BIT_MASK_ATIMWND1_V2) << BIT_SHIFT_ATIMWND1_V2)\n#define BITS_ATIMWND1_V2 (BIT_MASK_ATIMWND1_V2 << BIT_SHIFT_ATIMWND1_V2)\n#define BIT_CLEAR_ATIMWND1_V2(x) ((x) & (~BITS_ATIMWND1_V2))\n#define BIT_GET_ATIMWND1_V2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ATIMWND1_V2) & BIT_MASK_ATIMWND1_V2)\n#define BIT_SET_ATIMWND1_V2(x, v)                                              \\\n\t(BIT_CLEAR_ATIMWND1_V2(x) | BIT_ATIMWND1_V2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ATIMWND1_V1\t\t\t\t(Offset 0x0570) */\n\n#define BIT_SHIFT_ATIMWND1_V1 0\n#define BIT_MASK_ATIMWND1_V1 0xff\n#define BIT_ATIMWND1_V1(x)                                                     \\\n\t(((x) & BIT_MASK_ATIMWND1_V1) << BIT_SHIFT_ATIMWND1_V1)\n#define BITS_ATIMWND1_V1 (BIT_MASK_ATIMWND1_V1 << BIT_SHIFT_ATIMWND1_V1)\n#define BIT_CLEAR_ATIMWND1_V1(x) ((x) & (~BITS_ATIMWND1_V1))\n#define BIT_GET_ATIMWND1_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ATIMWND1_V1) & BIT_MASK_ATIMWND1_V1)\n#define BIT_SET_ATIMWND1_V1(x, v)                                              \\\n\t(BIT_CLEAR_ATIMWND1_V1(x) | BIT_ATIMWND1_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TBTT_PROHIBIT_INFRA\t\t\t(Offset 0x0571) */\n\n#define BIT_SHIFT_TBTT_PROHIBIT_INFRA 0\n#define BIT_MASK_TBTT_PROHIBIT_INFRA 0xff\n#define BIT_TBTT_PROHIBIT_INFRA(x)                                             \\\n\t(((x) & BIT_MASK_TBTT_PROHIBIT_INFRA) << BIT_SHIFT_TBTT_PROHIBIT_INFRA)\n#define BITS_TBTT_PROHIBIT_INFRA                                               \\\n\t(BIT_MASK_TBTT_PROHIBIT_INFRA << BIT_SHIFT_TBTT_PROHIBIT_INFRA)\n#define BIT_CLEAR_TBTT_PROHIBIT_INFRA(x) ((x) & (~BITS_TBTT_PROHIBIT_INFRA))\n#define BIT_GET_TBTT_PROHIBIT_INFRA(x)                                         \\\n\t(((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA) & BIT_MASK_TBTT_PROHIBIT_INFRA)\n#define BIT_SET_TBTT_PROHIBIT_INFRA(x, v)                                      \\\n\t(BIT_CLEAR_TBTT_PROHIBIT_INFRA(x) | BIT_TBTT_PROHIBIT_INFRA(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BCNIVLCUNT\t\t\t\t(Offset 0x0573) */\n\n#define BIT_SHIFT_BCNIVLCUNT 0\n#define BIT_MASK_BCNIVLCUNT 0x7f\n#define BIT_BCNIVLCUNT(x) (((x) & BIT_MASK_BCNIVLCUNT) << BIT_SHIFT_BCNIVLCUNT)\n#define BITS_BCNIVLCUNT (BIT_MASK_BCNIVLCUNT << BIT_SHIFT_BCNIVLCUNT)\n#define BIT_CLEAR_BCNIVLCUNT(x) ((x) & (~BITS_BCNIVLCUNT))\n#define BIT_GET_BCNIVLCUNT(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BCNIVLCUNT) & BIT_MASK_BCNIVLCUNT)\n#define BIT_SET_BCNIVLCUNT(x, v) (BIT_CLEAR_BCNIVLCUNT(x) | BIT_BCNIVLCUNT(v))\n\n/* 2 REG_BCNDROPCTRL\t\t\t\t(Offset 0x0574) */\n\n#define BIT_BEACON_DROP_EN BIT(7)\n\n#define BIT_SHIFT_BEACON_DROP_IVL 0\n#define BIT_MASK_BEACON_DROP_IVL 0x7f\n#define BIT_BEACON_DROP_IVL(x)                                                 \\\n\t(((x) & BIT_MASK_BEACON_DROP_IVL) << BIT_SHIFT_BEACON_DROP_IVL)\n#define BITS_BEACON_DROP_IVL                                                   \\\n\t(BIT_MASK_BEACON_DROP_IVL << BIT_SHIFT_BEACON_DROP_IVL)\n#define BIT_CLEAR_BEACON_DROP_IVL(x) ((x) & (~BITS_BEACON_DROP_IVL))\n#define BIT_GET_BEACON_DROP_IVL(x)                                             \\\n\t(((x) >> BIT_SHIFT_BEACON_DROP_IVL) & BIT_MASK_BEACON_DROP_IVL)\n#define BIT_SET_BEACON_DROP_IVL(x, v)                                          \\\n\t(BIT_CLEAR_BEACON_DROP_IVL(x) | BIT_BEACON_DROP_IVL(v))\n\n/* 2 REG_HGQ_TIMEOUT_PERIOD\t\t\t(Offset 0x0575) */\n\n#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD 0\n#define BIT_MASK_HGQ_TIMEOUT_PERIOD 0xff\n#define BIT_HGQ_TIMEOUT_PERIOD(x)                                              \\\n\t(((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD)\n#define BITS_HGQ_TIMEOUT_PERIOD                                                \\\n\t(BIT_MASK_HGQ_TIMEOUT_PERIOD << BIT_SHIFT_HGQ_TIMEOUT_PERIOD)\n#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD(x) ((x) & (~BITS_HGQ_TIMEOUT_PERIOD))\n#define BIT_GET_HGQ_TIMEOUT_PERIOD(x)                                          \\\n\t(((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD) & BIT_MASK_HGQ_TIMEOUT_PERIOD)\n#define BIT_SET_HGQ_TIMEOUT_PERIOD(x, v)                                       \\\n\t(BIT_CLEAR_HGQ_TIMEOUT_PERIOD(x) | BIT_HGQ_TIMEOUT_PERIOD(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXCMD_TIMEOUT_PERIOD\t\t(Offset 0x0576) */\n\n#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD 0\n#define BIT_MASK_TXCMD_TIMEOUT_PERIOD 0xff\n#define BIT_TXCMD_TIMEOUT_PERIOD(x)                                            \\\n\t(((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD)                                 \\\n\t << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD)\n#define BITS_TXCMD_TIMEOUT_PERIOD                                              \\\n\t(BIT_MASK_TXCMD_TIMEOUT_PERIOD << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD)\n#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD(x) ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD))\n#define BIT_GET_TXCMD_TIMEOUT_PERIOD(x)                                        \\\n\t(((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) &                             \\\n\t BIT_MASK_TXCMD_TIMEOUT_PERIOD)\n#define BIT_SET_TXCMD_TIMEOUT_PERIOD(x, v)                                     \\\n\t(BIT_CLEAR_TXCMD_TIMEOUT_PERIOD(x) | BIT_TXCMD_TIMEOUT_PERIOD(v))\n\n#define BIT_SHIFT_EARLY_128US 0\n#define BIT_MASK_EARLY_128US 0x7\n#define BIT_EARLY_128US(x)                                                     \\\n\t(((x) & BIT_MASK_EARLY_128US) << BIT_SHIFT_EARLY_128US)\n#define BITS_EARLY_128US (BIT_MASK_EARLY_128US << BIT_SHIFT_EARLY_128US)\n#define BIT_CLEAR_EARLY_128US(x) ((x) & (~BITS_EARLY_128US))\n#define BIT_GET_EARLY_128US(x)                                                 \\\n\t(((x) >> BIT_SHIFT_EARLY_128US) & BIT_MASK_EARLY_128US)\n#define BIT_SET_EARLY_128US(x, v)                                              \\\n\t(BIT_CLEAR_EARLY_128US(x) | BIT_EARLY_128US(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_MISC_CTRL\t\t\t\t(Offset 0x0577) */\n\n#define BIT_DIS_MARK_TSF_US BIT(7)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MISC_CTRL\t\t\t\t(Offset 0x0577) */\n\n#define BIT_DIS_MARK_TSF_US_V2 BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_MISC_CTRL\t\t\t\t(Offset 0x0577) */\n\n#define BIT_EN_TSFAUTO_SYNC BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MISC_CTRL\t\t\t\t(Offset 0x0577) */\n\n#define BIT_AUTO_SYNC_BY_TBTT BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MISC_CTRL\t\t\t\t(Offset 0x0577) */\n\n#define BIT_DIS_TRX_CAL_BCN BIT(5)\n#define BIT_DIS_TX_CAL_TBTT BIT(4)\n#define BIT_EN_FREECNT BIT(3)\n#define BIT_BCN_AGGRESSION BIT(2)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MISC_CTRL\t\t\t\t(Offset 0x0577) */\n\n#define BIT_DIS_SECONDARY_CCA_80M BIT(2)\n#define BIT_DIS_SECONDARY_CCA_40M BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MISC_CTRL\t\t\t\t(Offset 0x0577) */\n\n#define BIT_SHIFT_DIS_SECONDARY_CCA 0\n#define BIT_MASK_DIS_SECONDARY_CCA 0x3\n#define BIT_DIS_SECONDARY_CCA(x)                                               \\\n\t(((x) & BIT_MASK_DIS_SECONDARY_CCA) << BIT_SHIFT_DIS_SECONDARY_CCA)\n#define BITS_DIS_SECONDARY_CCA                                                 \\\n\t(BIT_MASK_DIS_SECONDARY_CCA << BIT_SHIFT_DIS_SECONDARY_CCA)\n#define BIT_CLEAR_DIS_SECONDARY_CCA(x) ((x) & (~BITS_DIS_SECONDARY_CCA))\n#define BIT_GET_DIS_SECONDARY_CCA(x)                                           \\\n\t(((x) >> BIT_SHIFT_DIS_SECONDARY_CCA) & BIT_MASK_DIS_SECONDARY_CCA)\n#define BIT_SET_DIS_SECONDARY_CCA(x, v)                                        \\\n\t(BIT_CLEAR_DIS_SECONDARY_CCA(x) | BIT_DIS_SECONDARY_CCA(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_MISC_CTRL\t\t\t\t(Offset 0x0577) */\n\n#define BIT_SHIFT_TBTT_INT_SHIFT_CLI0 0\n#define BIT_MASK_TBTT_INT_SHIFT_CLI0 0x7f\n#define BIT_TBTT_INT_SHIFT_CLI0(x)                                             \\\n\t(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0) << BIT_SHIFT_TBTT_INT_SHIFT_CLI0)\n#define BITS_TBTT_INT_SHIFT_CLI0                                               \\\n\t(BIT_MASK_TBTT_INT_SHIFT_CLI0 << BIT_SHIFT_TBTT_INT_SHIFT_CLI0)\n#define BIT_CLEAR_TBTT_INT_SHIFT_CLI0(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI0))\n#define BIT_GET_TBTT_INT_SHIFT_CLI0(x)                                         \\\n\t(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0) & BIT_MASK_TBTT_INT_SHIFT_CLI0)\n#define BIT_SET_TBTT_INT_SHIFT_CLI0(x, v)                                      \\\n\t(BIT_CLEAR_TBTT_INT_SHIFT_CLI0(x) | BIT_TBTT_INT_SHIFT_CLI0(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MISC_CTRL\t\t\t\t(Offset 0x0577) */\n\n#define BIT_DIS_SECONDARY_CCA_20M BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_CTRL_CLINT1\t\t\t(Offset 0x0578) */\n\n#define BIT_CLI1_DIS_RX_BSSID_FIT BIT(6)\n#define BIT_CLI1_DIS_TSF_UDT BIT(4)\n#define BIT_CLI1_EN_BCN_FUNCTION BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_CTRL_CLINT1\t\t\t(Offset 0x0578) */\n\n#define BIT_CLI1_EN_RXBCN_RPT BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_BCN_CTRL_CLINT1\t\t\t(Offset 0x0578) */\n\n#define BIT_CLI1_EN_BCN_RPT BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_CTRL_CLINT1\t\t\t(Offset 0x0578) */\n\n#define BIT_CLI1_ENP2P_CTWINDOW BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TSFTR2_L\t\t\t\t(Offset 0x0578) */\n\n#define BIT_SHIFT_TSF2_TIMER_L 0\n#define BIT_MASK_TSF2_TIMER_L 0xffffffffL\n#define BIT_TSF2_TIMER_L(x)                                                    \\\n\t(((x) & BIT_MASK_TSF2_TIMER_L) << BIT_SHIFT_TSF2_TIMER_L)\n#define BITS_TSF2_TIMER_L (BIT_MASK_TSF2_TIMER_L << BIT_SHIFT_TSF2_TIMER_L)\n#define BIT_CLEAR_TSF2_TIMER_L(x) ((x) & (~BITS_TSF2_TIMER_L))\n#define BIT_GET_TSF2_TIMER_L(x)                                                \\\n\t(((x) >> BIT_SHIFT_TSF2_TIMER_L) & BIT_MASK_TSF2_TIMER_L)\n#define BIT_SET_TSF2_TIMER_L(x, v)                                             \\\n\t(BIT_CLEAR_TSF2_TIMER_L(x) | BIT_TSF2_TIMER_L(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_CTRL_CLINT1\t\t\t(Offset 0x0578) */\n\n#define BIT_CLI1_ENP2P_BCNQ_AREA BIT(0)\n\n/* 2 REG_BCN_CTRL_CLINT2\t\t\t(Offset 0x0579) */\n\n#define BIT_CLI2_DIS_RX_BSSID_FIT BIT(6)\n#define BIT_CLI2_DIS_TSF_UDT BIT(4)\n#define BIT_CLI2_EN_BCN_FUNCTION BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_CTRL_CLINT2\t\t\t(Offset 0x0579) */\n\n#define BIT_CLI2_EN_RXBCN_RPT BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_BCN_CTRL_CLINT2\t\t\t(Offset 0x0579) */\n\n#define BIT_CLI2_EN_BCN_RPT BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_CTRL_CLINT2\t\t\t(Offset 0x0579) */\n\n#define BIT_CLI2_ENP2P_CTWINDOW BIT(1)\n#define BIT_CLI2_ENP2P_BCNQ_AREA BIT(0)\n\n/* 2 REG_BCN_CTRL_CLINT3\t\t\t(Offset 0x057A) */\n\n#define BIT_CLI3_DIS_RX_BSSID_FIT BIT(6)\n#define BIT_CLI3_DIS_TSF_UDT BIT(4)\n#define BIT_CLI3_EN_BCN_FUNCTION BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_CTRL_CLINT3\t\t\t(Offset 0x057A) */\n\n#define BIT_CLI3_EN_RXBCN_RPT BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_BCN_CTRL_CLINT3\t\t\t(Offset 0x057A) */\n\n#define BIT_CLI3_EN_BCN_RPT BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_CTRL_CLINT3\t\t\t(Offset 0x057A) */\n\n#define BIT_CLI3_ENP2P_CTWINDOW BIT(1)\n#define BIT_CLI3_ENP2P_BCNQ_AREA BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_EXTEND_CTRL\t\t\t\t(Offset 0x057B) */\n\n#define BIT_EN_TSFBIT32_RST_P2P2 BIT(5)\n#define BIT_EN_TSFBIT32_RST_P2P1 BIT(4)\n\n#define BIT_SHIFT_PORT_SEL 0\n#define BIT_MASK_PORT_SEL 0x7\n#define BIT_PORT_SEL(x) (((x) & BIT_MASK_PORT_SEL) << BIT_SHIFT_PORT_SEL)\n#define BITS_PORT_SEL (BIT_MASK_PORT_SEL << BIT_SHIFT_PORT_SEL)\n#define BIT_CLEAR_PORT_SEL(x) ((x) & (~BITS_PORT_SEL))\n#define BIT_GET_PORT_SEL(x) (((x) >> BIT_SHIFT_PORT_SEL) & BIT_MASK_PORT_SEL)\n#define BIT_SET_PORT_SEL(x, v) (BIT_CLEAR_PORT_SEL(x) | BIT_PORT_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PPS1_SPEC_STATE\t\t\t(Offset 0x057C) */\n\n#define BIT_P2P1_SPEC_POWER_STATE BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PPS1_SPEC_STATE\t\t\t(Offset 0x057C) */\n\n#define BIT_P2P1_SPEC_CTWINDOW_ON BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PPS1_SPEC_STATE\t\t\t(Offset 0x057C) */\n\n#define BIT_P2P1_SPEC_BCN_AREA_ON BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PPS1_SPEC_STATE\t\t\t(Offset 0x057C) */\n\n#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX BIT(4)\n#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD BIT(3)\n#define BIT_P2P1_SPEC_FORCE_DOZE1 BIT(2)\n#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TSFTR2_H\t\t\t\t(Offset 0x057C) */\n\n#define BIT_SHIFT_TSF2_TIMER_H 0\n#define BIT_MASK_TSF2_TIMER_H 0xffffffffL\n#define BIT_TSF2_TIMER_H(x)                                                    \\\n\t(((x) & BIT_MASK_TSF2_TIMER_H) << BIT_SHIFT_TSF2_TIMER_H)\n#define BITS_TSF2_TIMER_H (BIT_MASK_TSF2_TIMER_H << BIT_SHIFT_TSF2_TIMER_H)\n#define BIT_CLEAR_TSF2_TIMER_H(x) ((x) & (~BITS_TSF2_TIMER_H))\n#define BIT_GET_TSF2_TIMER_H(x)                                                \\\n\t(((x) >> BIT_SHIFT_TSF2_TIMER_H) & BIT_MASK_TSF2_TIMER_H)\n#define BIT_SET_TSF2_TIMER_H(x, v)                                             \\\n\t(BIT_CLEAR_TSF2_TIMER_H(x) | BIT_TSF2_TIMER_H(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PPS1_SPEC_STATE\t\t\t(Offset 0x057C) */\n\n#define BIT_P2P1_SPEC_FORCE_DOZE0 BIT(0)\n\n/* 2 REG_P2PPS1_STATE\t\t\t(Offset 0x057D) */\n\n#define BIT_P2P1_POWER_STATE BIT(7)\n#define BIT_P2P1_CTWINDOW_ON BIT(6)\n#define BIT_P2P1_BEACON_AREA_ON BIT(5)\n#define BIT_P2P1_CTWIN_EARLY_DISTX BIT(4)\n#define BIT_P2P1_NOA1_OFF_PERIOD BIT(3)\n#define BIT_P2P1_FORCE_DOZE1 BIT(2)\n#define BIT_P2P1_NOA0_OFF_PERIOD BIT(1)\n#define BIT_P2P1_FORCE_DOZE0 BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PPS2_SPEC_STATE\t\t\t(Offset 0x057E) */\n\n#define BIT_P2P2_SPEC_POWER_STATE BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PPS2_SPEC_STATE\t\t\t(Offset 0x057E) */\n\n#define BIT_P2P2_SPEC_CTWINDOW_ON BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PPS2_SPEC_STATE\t\t\t(Offset 0x057E) */\n\n#define BIT_P2P2_SPEC_BCN_AREA_ON BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PPS2_SPEC_STATE\t\t\t(Offset 0x057E) */\n\n#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX BIT(4)\n#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD BIT(3)\n#define BIT_P2P2_SPEC_FORCE_DOZE1 BIT(2)\n#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD BIT(1)\n#define BIT_P2P2_SPEC_FORCE_DOZE0 BIT(0)\n\n/* 2 REG_P2PPS2_STATE\t\t\t(Offset 0x057F) */\n\n#define BIT_P2P2_POWER_STATE BIT(7)\n#define BIT_P2P2_CTWINDOW_ON BIT(6)\n#define BIT_P2P2_BEACON_AREA_ON BIT(5)\n#define BIT_P2P2_CTWIN_EARLY_DISTX BIT(4)\n#define BIT_P2P2_NOA1_OFF_PERIOD BIT(3)\n#define BIT_P2P2_FORCE_DOZE1 BIT(2)\n#define BIT_P2P2_NOA0_OFF_PERIOD BIT(1)\n#define BIT_P2P2_FORCE_DOZE0 BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PS_TIMER\t\t\t\t(Offset 0x0580) */\n\n#define BIT_SHIFT_PSTIMER 5\n#define BIT_MASK_PSTIMER 0x7ffffff\n#define BIT_PSTIMER(x) (((x) & BIT_MASK_PSTIMER) << BIT_SHIFT_PSTIMER)\n#define BITS_PSTIMER (BIT_MASK_PSTIMER << BIT_SHIFT_PSTIMER)\n#define BIT_CLEAR_PSTIMER(x) ((x) & (~BITS_PSTIMER))\n#define BIT_GET_PSTIMER(x) (((x) >> BIT_SHIFT_PSTIMER) & BIT_MASK_PSTIMER)\n#define BIT_SET_PSTIMER(x, v) (BIT_CLEAR_PSTIMER(x) | BIT_PSTIMER(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PS_TIMER0\t\t\t\t(Offset 0x0580) */\n\n#define BIT_SHIFT_PSTIMER0_INT 5\n#define BIT_MASK_PSTIMER0_INT 0x7ffffff\n#define BIT_PSTIMER0_INT(x)                                                    \\\n\t(((x) & BIT_MASK_PSTIMER0_INT) << BIT_SHIFT_PSTIMER0_INT)\n#define BITS_PSTIMER0_INT (BIT_MASK_PSTIMER0_INT << BIT_SHIFT_PSTIMER0_INT)\n#define BIT_CLEAR_PSTIMER0_INT(x) ((x) & (~BITS_PSTIMER0_INT))\n#define BIT_GET_PSTIMER0_INT(x)                                                \\\n\t(((x) >> BIT_SHIFT_PSTIMER0_INT) & BIT_MASK_PSTIMER0_INT)\n#define BIT_SET_PSTIMER0_INT(x, v)                                             \\\n\t(BIT_CLEAR_PSTIMER0_INT(x) | BIT_PSTIMER0_INT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TIMER0\t\t\t\t(Offset 0x0584) */\n\n#define BIT_SHIFT_TIMER0_INT 5\n#define BIT_MASK_TIMER0_INT 0x7ffffff\n#define BIT_TIMER0_INT(x) (((x) & BIT_MASK_TIMER0_INT) << BIT_SHIFT_TIMER0_INT)\n#define BITS_TIMER0_INT (BIT_MASK_TIMER0_INT << BIT_SHIFT_TIMER0_INT)\n#define BIT_CLEAR_TIMER0_INT(x) ((x) & (~BITS_TIMER0_INT))\n#define BIT_GET_TIMER0_INT(x)                                                  \\\n\t(((x) >> BIT_SHIFT_TIMER0_INT) & BIT_MASK_TIMER0_INT)\n#define BIT_SET_TIMER0_INT(x, v) (BIT_CLEAR_TIMER0_INT(x) | BIT_TIMER0_INT(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PS_TIMER1\t\t\t\t(Offset 0x0584) */\n\n#define BIT_SHIFT_PSTIMER1_INT 5\n#define BIT_MASK_PSTIMER1_INT 0x7ffffff\n#define BIT_PSTIMER1_INT(x)                                                    \\\n\t(((x) & BIT_MASK_PSTIMER1_INT) << BIT_SHIFT_PSTIMER1_INT)\n#define BITS_PSTIMER1_INT (BIT_MASK_PSTIMER1_INT << BIT_SHIFT_PSTIMER1_INT)\n#define BIT_CLEAR_PSTIMER1_INT(x) ((x) & (~BITS_PSTIMER1_INT))\n#define BIT_GET_PSTIMER1_INT(x)                                                \\\n\t(((x) >> BIT_SHIFT_PSTIMER1_INT) & BIT_MASK_PSTIMER1_INT)\n#define BIT_SET_PSTIMER1_INT(x, v)                                             \\\n\t(BIT_CLEAR_PSTIMER1_INT(x) | BIT_PSTIMER1_INT(v))\n\n/* 2 REG_PS_TIMER2\t\t\t\t(Offset 0x0588) */\n\n#define BIT_SHIFT_INFO_INDEX_OFFSET 16\n#define BIT_MASK_INFO_INDEX_OFFSET 0x1fff\n#define BIT_INFO_INDEX_OFFSET(x)                                               \\\n\t(((x) & BIT_MASK_INFO_INDEX_OFFSET) << BIT_SHIFT_INFO_INDEX_OFFSET)\n#define BITS_INFO_INDEX_OFFSET                                                 \\\n\t(BIT_MASK_INFO_INDEX_OFFSET << BIT_SHIFT_INFO_INDEX_OFFSET)\n#define BIT_CLEAR_INFO_INDEX_OFFSET(x) ((x) & (~BITS_INFO_INDEX_OFFSET))\n#define BIT_GET_INFO_INDEX_OFFSET(x)                                           \\\n\t(((x) >> BIT_SHIFT_INFO_INDEX_OFFSET) & BIT_MASK_INFO_INDEX_OFFSET)\n#define BIT_SET_INFO_INDEX_OFFSET(x, v)                                        \\\n\t(BIT_CLEAR_INFO_INDEX_OFFSET(x) | BIT_INFO_INDEX_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TIMER1\t\t\t\t(Offset 0x0588) */\n\n#define BIT_SHIFT_TIMER1_INT 5\n#define BIT_MASK_TIMER1_INT 0x7ffffff\n#define BIT_TIMER1_INT(x) (((x) & BIT_MASK_TIMER1_INT) << BIT_SHIFT_TIMER1_INT)\n#define BITS_TIMER1_INT (BIT_MASK_TIMER1_INT << BIT_SHIFT_TIMER1_INT)\n#define BIT_CLEAR_TIMER1_INT(x) ((x) & (~BITS_TIMER1_INT))\n#define BIT_GET_TIMER1_INT(x)                                                  \\\n\t(((x) >> BIT_SHIFT_TIMER1_INT) & BIT_MASK_TIMER1_INT)\n#define BIT_SET_TIMER1_INT(x, v) (BIT_CLEAR_TIMER1_INT(x) | BIT_TIMER1_INT(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PS_TIMER2\t\t\t\t(Offset 0x0588) */\n\n#define BIT_SHIFT_PSTIMER2_INT 5\n#define BIT_MASK_PSTIMER2_INT 0x7ffffff\n#define BIT_PSTIMER2_INT(x)                                                    \\\n\t(((x) & BIT_MASK_PSTIMER2_INT) << BIT_SHIFT_PSTIMER2_INT)\n#define BITS_PSTIMER2_INT (BIT_MASK_PSTIMER2_INT << BIT_SHIFT_PSTIMER2_INT)\n#define BIT_CLEAR_PSTIMER2_INT(x) ((x) & (~BITS_PSTIMER2_INT))\n#define BIT_GET_PSTIMER2_INT(x)                                                \\\n\t(((x) >> BIT_SHIFT_PSTIMER2_INT) & BIT_MASK_PSTIMER2_INT)\n#define BIT_SET_PSTIMER2_INT(x, v)                                             \\\n\t(BIT_CLEAR_PSTIMER2_INT(x) | BIT_PSTIMER2_INT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TBTT_CTN_AREA\t\t\t(Offset 0x058C) */\n\n#define BIT_SHIFT_TBTT_CTN_AREA 0\n#define BIT_MASK_TBTT_CTN_AREA 0xff\n#define BIT_TBTT_CTN_AREA(x)                                                   \\\n\t(((x) & BIT_MASK_TBTT_CTN_AREA) << BIT_SHIFT_TBTT_CTN_AREA)\n#define BITS_TBTT_CTN_AREA (BIT_MASK_TBTT_CTN_AREA << BIT_SHIFT_TBTT_CTN_AREA)\n#define BIT_CLEAR_TBTT_CTN_AREA(x) ((x) & (~BITS_TBTT_CTN_AREA))\n#define BIT_GET_TBTT_CTN_AREA(x)                                               \\\n\t(((x) >> BIT_SHIFT_TBTT_CTN_AREA) & BIT_MASK_TBTT_CTN_AREA)\n#define BIT_SET_TBTT_CTN_AREA(x, v)                                            \\\n\t(BIT_CLEAR_TBTT_CTN_AREA(x) | BIT_TBTT_CTN_AREA(v))\n\n/* 2 REG_FORCE_BCN_IFS\t\t\t(Offset 0x058E) */\n\n#define BIT_SHIFT_FORCE_BCN_IFS 0\n#define BIT_MASK_FORCE_BCN_IFS 0xff\n#define BIT_FORCE_BCN_IFS(x)                                                   \\\n\t(((x) & BIT_MASK_FORCE_BCN_IFS) << BIT_SHIFT_FORCE_BCN_IFS)\n#define BITS_FORCE_BCN_IFS (BIT_MASK_FORCE_BCN_IFS << BIT_SHIFT_FORCE_BCN_IFS)\n#define BIT_CLEAR_FORCE_BCN_IFS(x) ((x) & (~BITS_FORCE_BCN_IFS))\n#define BIT_GET_FORCE_BCN_IFS(x)                                               \\\n\t(((x) >> BIT_SHIFT_FORCE_BCN_IFS) & BIT_MASK_FORCE_BCN_IFS)\n#define BIT_SET_FORCE_BCN_IFS(x, v)                                            \\\n\t(BIT_CLEAR_FORCE_BCN_IFS(x) | BIT_FORCE_BCN_IFS(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DRVERLYINT_V1\t\t\t(Offset 0x058F) */\n\n#define BIT_SHIFT_PRE_BCN_DMATIM 0\n#define BIT_MASK_PRE_BCN_DMATIM 0xff\n#define BIT_PRE_BCN_DMATIM(x)                                                  \\\n\t(((x) & BIT_MASK_PRE_BCN_DMATIM) << BIT_SHIFT_PRE_BCN_DMATIM)\n#define BITS_PRE_BCN_DMATIM                                                    \\\n\t(BIT_MASK_PRE_BCN_DMATIM << BIT_SHIFT_PRE_BCN_DMATIM)\n#define BIT_CLEAR_PRE_BCN_DMATIM(x) ((x) & (~BITS_PRE_BCN_DMATIM))\n#define BIT_GET_PRE_BCN_DMATIM(x)                                              \\\n\t(((x) >> BIT_SHIFT_PRE_BCN_DMATIM) & BIT_MASK_PRE_BCN_DMATIM)\n#define BIT_SET_PRE_BCN_DMATIM(x, v)                                           \\\n\t(BIT_CLEAR_PRE_BCN_DMATIM(x) | BIT_PRE_BCN_DMATIM(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TXOP_MIN\t\t\t\t(Offset 0x0590) */\n\n#define BIT_NAV_BLK_HGQ BIT(15)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXOP_MIN\t\t\t\t(Offset 0x0590) */\n\n#define BIT_HIQ_NAV_BREAK_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TXOP_MIN\t\t\t\t(Offset 0x0590) */\n\n#define BIT_NAV_BLK_MGQ BIT(14)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXOP_MIN\t\t\t\t(Offset 0x0590) */\n\n#define BIT_MGQ_NAV_BREAK_EN BIT(14)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TXOP_MIN\t\t\t\t(Offset 0x0590) */\n\n#define BIT_SHIFT_TXPAUSE1 8\n#define BIT_MASK_TXPAUSE1 0xff\n#define BIT_TXPAUSE1(x) (((x) & BIT_MASK_TXPAUSE1) << BIT_SHIFT_TXPAUSE1)\n#define BITS_TXPAUSE1 (BIT_MASK_TXPAUSE1 << BIT_SHIFT_TXPAUSE1)\n#define BIT_CLEAR_TXPAUSE1(x) ((x) & (~BITS_TXPAUSE1))\n#define BIT_GET_TXPAUSE1(x) (((x) >> BIT_SHIFT_TXPAUSE1) & BIT_MASK_TXPAUSE1)\n#define BIT_SET_TXPAUSE1(x, v) (BIT_CLEAR_TXPAUSE1(x) | BIT_TXPAUSE1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXOP_MIN\t\t\t\t(Offset 0x0590) */\n\n#define BIT_SHIFT_TXOP_MIN 0\n#define BIT_MASK_TXOP_MIN 0x3fff\n#define BIT_TXOP_MIN(x) (((x) & BIT_MASK_TXOP_MIN) << BIT_SHIFT_TXOP_MIN)\n#define BITS_TXOP_MIN (BIT_MASK_TXOP_MIN << BIT_SHIFT_TXOP_MIN)\n#define BIT_CLEAR_TXOP_MIN(x) ((x) & (~BITS_TXOP_MIN))\n#define BIT_GET_TXOP_MIN(x) (((x) >> BIT_SHIFT_TXOP_MIN) & BIT_MASK_TXOP_MIN)\n#define BIT_SET_TXOP_MIN(x, v) (BIT_CLEAR_TXOP_MIN(x) | BIT_TXOP_MIN(v))\n\n/* 2 REG_PRE_BKF_TIME\t\t\t(Offset 0x0592) */\n\n#define BIT_SHIFT_PRE_BKF_TIME 0\n#define BIT_MASK_PRE_BKF_TIME 0xff\n#define BIT_PRE_BKF_TIME(x)                                                    \\\n\t(((x) & BIT_MASK_PRE_BKF_TIME) << BIT_SHIFT_PRE_BKF_TIME)\n#define BITS_PRE_BKF_TIME (BIT_MASK_PRE_BKF_TIME << BIT_SHIFT_PRE_BKF_TIME)\n#define BIT_CLEAR_PRE_BKF_TIME(x) ((x) & (~BITS_PRE_BKF_TIME))\n#define BIT_GET_PRE_BKF_TIME(x)                                                \\\n\t(((x) >> BIT_SHIFT_PRE_BKF_TIME) & BIT_MASK_PRE_BKF_TIME)\n#define BIT_SET_PRE_BKF_TIME(x, v)                                             \\\n\t(BIT_CLEAR_PRE_BKF_TIME(x) | BIT_PRE_BKF_TIME(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_CROSS_TXOP_CTRL\t\t\t(Offset 0x0593) */\n\n#define BIT_NOPKT_END_RTSMF BIT(7)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CROSS_TXOP_CTRL\t\t\t(Offset 0x0593) */\n\n#define BIT_TBTT_RETRY BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_CROSS_TXOP_CTRL\t\t\t(Offset 0x0593) */\n\n#define BIT_SHIFT_PRETX_US 3\n#define BIT_MASK_PRETX_US 0xf\n#define BIT_PRETX_US(x) (((x) & BIT_MASK_PRETX_US) << BIT_SHIFT_PRETX_US)\n#define BITS_PRETX_US (BIT_MASK_PRETX_US << BIT_SHIFT_PRETX_US)\n#define BIT_CLEAR_PRETX_US(x) ((x) & (~BITS_PRETX_US))\n#define BIT_GET_PRETX_US(x) (((x) >> BIT_SHIFT_PRETX_US) & BIT_MASK_PRETX_US)\n#define BIT_SET_PRETX_US(x, v) (BIT_CLEAR_PRETX_US(x) | BIT_PRETX_US(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_CROSS_TXOP_CTRL\t\t\t(Offset 0x0593) */\n\n#define BIT_TXOP_FAIL_BREAK BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CROSS_TXOP_CTRL\t\t\t(Offset 0x0593) */\n\n#define BIT_TXFAIL_BREACK_TXOP_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CROSS_TXOP_CTRL\t\t\t(Offset 0x0593) */\n\n#define BIT_DTIM_BYPASS BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CROSS_TXOP_CTRL\t\t\t(Offset 0x0593) */\n\n#define BIT_RTS_NAV_TXOP BIT(1)\n#define BIT_NOT_CROSS_TXOP BIT(0)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_TBTT_INT_SHIFT_CLI\t\t\t(Offset 0x0594) */\n\n#define BIT_TBTT_INT_SHIFT_DIR_CLI3_V1 BIT(31)\n\n#define BIT_SHIFT_TBTT_INT_SHIFT_CLI3_V1 24\n#define BIT_MASK_TBTT_INT_SHIFT_CLI3_V1 0x7f\n#define BIT_TBTT_INT_SHIFT_CLI3_V1(x)                                          \\\n\t(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3_V1)                               \\\n\t << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_V1)\n#define BITS_TBTT_INT_SHIFT_CLI3_V1                                            \\\n\t(BIT_MASK_TBTT_INT_SHIFT_CLI3_V1 << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_V1)\n#define BIT_CLEAR_TBTT_INT_SHIFT_CLI3_V1(x)                                    \\\n\t((x) & (~BITS_TBTT_INT_SHIFT_CLI3_V1))\n#define BIT_GET_TBTT_INT_SHIFT_CLI3_V1(x)                                      \\\n\t(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3_V1) &                           \\\n\t BIT_MASK_TBTT_INT_SHIFT_CLI3_V1)\n#define BIT_SET_TBTT_INT_SHIFT_CLI3_V1(x, v)                                   \\\n\t(BIT_CLEAR_TBTT_INT_SHIFT_CLI3_V1(x) | BIT_TBTT_INT_SHIFT_CLI3_V1(v))\n\n#define BIT_TBTT_INT_SHIFT_DIR_CLI2_V1 BIT(23)\n\n#define BIT_SHIFT_TBTT_INT_SHIFT_CLI2_V1 16\n#define BIT_MASK_TBTT_INT_SHIFT_CLI2_V1 0x7f\n#define BIT_TBTT_INT_SHIFT_CLI2_V1(x)                                          \\\n\t(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2_V1)                               \\\n\t << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_V1)\n#define BITS_TBTT_INT_SHIFT_CLI2_V1                                            \\\n\t(BIT_MASK_TBTT_INT_SHIFT_CLI2_V1 << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_V1)\n#define BIT_CLEAR_TBTT_INT_SHIFT_CLI2_V1(x)                                    \\\n\t((x) & (~BITS_TBTT_INT_SHIFT_CLI2_V1))\n#define BIT_GET_TBTT_INT_SHIFT_CLI2_V1(x)                                      \\\n\t(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2_V1) &                           \\\n\t BIT_MASK_TBTT_INT_SHIFT_CLI2_V1)\n#define BIT_SET_TBTT_INT_SHIFT_CLI2_V1(x, v)                                   \\\n\t(BIT_CLEAR_TBTT_INT_SHIFT_CLI2_V1(x) | BIT_TBTT_INT_SHIFT_CLI2_V1(v))\n\n#define BIT_SHIFT_DIS_ATIM_V1 16\n#define BIT_MASK_DIS_ATIM_V1 0xff\n#define BIT_DIS_ATIM_V1(x)                                                     \\\n\t(((x) & BIT_MASK_DIS_ATIM_V1) << BIT_SHIFT_DIS_ATIM_V1)\n#define BITS_DIS_ATIM_V1 (BIT_MASK_DIS_ATIM_V1 << BIT_SHIFT_DIS_ATIM_V1)\n#define BIT_CLEAR_DIS_ATIM_V1(x) ((x) & (~BITS_DIS_ATIM_V1))\n#define BIT_GET_DIS_ATIM_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DIS_ATIM_V1) & BIT_MASK_DIS_ATIM_V1)\n#define BIT_SET_DIS_ATIM_V1(x, v)                                              \\\n\t(BIT_CLEAR_DIS_ATIM_V1(x) | BIT_DIS_ATIM_V1(v))\n\n#define BIT_TBTT_INT_SHIFT_DIR_CLI1_V1 BIT(15)\n\n#define BIT_SHIFT_TBTT_INT_SHIFT_CLI1_V1 8\n#define BIT_MASK_TBTT_INT_SHIFT_CLI1_V1 0x7f\n#define BIT_TBTT_INT_SHIFT_CLI1_V1(x)                                          \\\n\t(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1_V1)                               \\\n\t << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_V1)\n#define BITS_TBTT_INT_SHIFT_CLI1_V1                                            \\\n\t(BIT_MASK_TBTT_INT_SHIFT_CLI1_V1 << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_V1)\n#define BIT_CLEAR_TBTT_INT_SHIFT_CLI1_V1(x)                                    \\\n\t((x) & (~BITS_TBTT_INT_SHIFT_CLI1_V1))\n#define BIT_GET_TBTT_INT_SHIFT_CLI1_V1(x)                                      \\\n\t(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1_V1) &                           \\\n\t BIT_MASK_TBTT_INT_SHIFT_CLI1_V1)\n#define BIT_SET_TBTT_INT_SHIFT_CLI1_V1(x, v)                                   \\\n\t(BIT_CLEAR_TBTT_INT_SHIFT_CLI1_V1(x) | BIT_TBTT_INT_SHIFT_CLI1_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TBTT_INT_SHIFT_CLI0\t\t\t(Offset 0x0594) */\n\n#define BIT_TBTT_INT_SHIFT_DIR_CLI0 BIT(7)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_TBTT_INT_SHIFT_CLI\t\t\t(Offset 0x0594) */\n\n#define BIT_TBTT_INT_SHIFT_DIR_CLI0_V1 BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FREERUN_CNT_L\t\t\t(Offset 0x0594) */\n\n#define BIT_SHIFT_FREERUN_CNT_L 0\n#define BIT_MASK_FREERUN_CNT_L 0xffffffffL\n#define BIT_FREERUN_CNT_L(x)                                                   \\\n\t(((x) & BIT_MASK_FREERUN_CNT_L) << BIT_SHIFT_FREERUN_CNT_L)\n#define BITS_FREERUN_CNT_L (BIT_MASK_FREERUN_CNT_L << BIT_SHIFT_FREERUN_CNT_L)\n#define BIT_CLEAR_FREERUN_CNT_L(x) ((x) & (~BITS_FREERUN_CNT_L))\n#define BIT_GET_FREERUN_CNT_L(x)                                               \\\n\t(((x) >> BIT_SHIFT_FREERUN_CNT_L) & BIT_MASK_FREERUN_CNT_L)\n#define BIT_SET_FREERUN_CNT_L(x, v)                                            \\\n\t(BIT_CLEAR_FREERUN_CNT_L(x) | BIT_FREERUN_CNT_L(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_TBTT_INT_SHIFT_CLI\t\t\t(Offset 0x0594) */\n\n#define BIT_SHIFT_MBID_BCNQ_EN_V1 0\n#define BIT_MASK_MBID_BCNQ_EN_V1 0xff\n#define BIT_MBID_BCNQ_EN_V1(x)                                                 \\\n\t(((x) & BIT_MASK_MBID_BCNQ_EN_V1) << BIT_SHIFT_MBID_BCNQ_EN_V1)\n#define BITS_MBID_BCNQ_EN_V1                                                   \\\n\t(BIT_MASK_MBID_BCNQ_EN_V1 << BIT_SHIFT_MBID_BCNQ_EN_V1)\n#define BIT_CLEAR_MBID_BCNQ_EN_V1(x) ((x) & (~BITS_MBID_BCNQ_EN_V1))\n#define BIT_GET_MBID_BCNQ_EN_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_MBID_BCNQ_EN_V1) & BIT_MASK_MBID_BCNQ_EN_V1)\n#define BIT_SET_MBID_BCNQ_EN_V1(x, v)                                          \\\n\t(BIT_CLEAR_MBID_BCNQ_EN_V1(x) | BIT_MBID_BCNQ_EN_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TBTT_INT_SHIFT_CLI1\t\t\t(Offset 0x0595) */\n\n#define BIT_TBTT_INT_SHIFT_DIR_CLI1 BIT(7)\n\n#define BIT_SHIFT_TBTT_INT_SHIFT_CLI1 0\n#define BIT_MASK_TBTT_INT_SHIFT_CLI1 0x7f\n#define BIT_TBTT_INT_SHIFT_CLI1(x)                                             \\\n\t(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1) << BIT_SHIFT_TBTT_INT_SHIFT_CLI1)\n#define BITS_TBTT_INT_SHIFT_CLI1                                               \\\n\t(BIT_MASK_TBTT_INT_SHIFT_CLI1 << BIT_SHIFT_TBTT_INT_SHIFT_CLI1)\n#define BIT_CLEAR_TBTT_INT_SHIFT_CLI1(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI1))\n#define BIT_GET_TBTT_INT_SHIFT_CLI1(x)                                         \\\n\t(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1) & BIT_MASK_TBTT_INT_SHIFT_CLI1)\n#define BIT_SET_TBTT_INT_SHIFT_CLI1(x, v)                                      \\\n\t(BIT_CLEAR_TBTT_INT_SHIFT_CLI1(x) | BIT_TBTT_INT_SHIFT_CLI1(v))\n\n/* 2 REG_TBTT_INT_SHIFT_CLI2\t\t\t(Offset 0x0596) */\n\n#define BIT_TBTT_INT_SHIFT_DIR_CLI2 BIT(7)\n\n#define BIT_SHIFT_TBTT_INT_SHIFT_CLI2 0\n#define BIT_MASK_TBTT_INT_SHIFT_CLI2 0x7f\n#define BIT_TBTT_INT_SHIFT_CLI2(x)                                             \\\n\t(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2) << BIT_SHIFT_TBTT_INT_SHIFT_CLI2)\n#define BITS_TBTT_INT_SHIFT_CLI2                                               \\\n\t(BIT_MASK_TBTT_INT_SHIFT_CLI2 << BIT_SHIFT_TBTT_INT_SHIFT_CLI2)\n#define BIT_CLEAR_TBTT_INT_SHIFT_CLI2(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI2))\n#define BIT_GET_TBTT_INT_SHIFT_CLI2(x)                                         \\\n\t(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2) & BIT_MASK_TBTT_INT_SHIFT_CLI2)\n#define BIT_SET_TBTT_INT_SHIFT_CLI2(x, v)                                      \\\n\t(BIT_CLEAR_TBTT_INT_SHIFT_CLI2(x) | BIT_TBTT_INT_SHIFT_CLI2(v))\n\n/* 2 REG_TBTT_INT_SHIFT_CLI3\t\t\t(Offset 0x0597) */\n\n#define BIT_TBTT_INT_SHIFT_DIR_CLI3 BIT(7)\n\n#define BIT_SHIFT_TBTT_INT_SHIFT_CLI3 0\n#define BIT_MASK_TBTT_INT_SHIFT_CLI3 0x7f\n#define BIT_TBTT_INT_SHIFT_CLI3(x)                                             \\\n\t(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3) << BIT_SHIFT_TBTT_INT_SHIFT_CLI3)\n#define BITS_TBTT_INT_SHIFT_CLI3                                               \\\n\t(BIT_MASK_TBTT_INT_SHIFT_CLI3 << BIT_SHIFT_TBTT_INT_SHIFT_CLI3)\n#define BIT_CLEAR_TBTT_INT_SHIFT_CLI3(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI3))\n#define BIT_GET_TBTT_INT_SHIFT_CLI3(x)                                         \\\n\t(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3) & BIT_MASK_TBTT_INT_SHIFT_CLI3)\n#define BIT_SET_TBTT_INT_SHIFT_CLI3(x, v)                                      \\\n\t(BIT_CLEAR_TBTT_INT_SHIFT_CLI3(x) | BIT_TBTT_INT_SHIFT_CLI3(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RX_TBTT_SHIFT_V1\t\t\t(Offset 0x0598) */\n\n#define BIT_RX_TBTT_SHIFT_RW_FLAG_V1 BIT(31)\n\n#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1 16\n#define BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1 0xfff\n#define BIT_RX_TBTT_SHIFT_OFFSET_V1(x)                                         \\\n\t(((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1)                              \\\n\t << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1)\n#define BITS_RX_TBTT_SHIFT_OFFSET_V1                                           \\\n\t(BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1 << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1)\n#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1(x)                                   \\\n\t((x) & (~BITS_RX_TBTT_SHIFT_OFFSET_V1))\n#define BIT_GET_RX_TBTT_SHIFT_OFFSET_V1(x)                                     \\\n\t(((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1) &                          \\\n\t BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1)\n#define BIT_SET_RX_TBTT_SHIFT_OFFSET_V1(x, v)                                  \\\n\t(BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1(x) | BIT_RX_TBTT_SHIFT_OFFSET_V1(v))\n\n#define BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1 8\n#define BIT_MASK_RX_TBTT_SHIFT_SEL_V1 0x7\n#define BIT_RX_TBTT_SHIFT_SEL_V1(x)                                            \\\n\t(((x) & BIT_MASK_RX_TBTT_SHIFT_SEL_V1)                                 \\\n\t << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1)\n#define BITS_RX_TBTT_SHIFT_SEL_V1                                              \\\n\t(BIT_MASK_RX_TBTT_SHIFT_SEL_V1 << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1)\n#define BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1(x) ((x) & (~BITS_RX_TBTT_SHIFT_SEL_V1))\n#define BIT_GET_RX_TBTT_SHIFT_SEL_V1(x)                                        \\\n\t(((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1) &                             \\\n\t BIT_MASK_RX_TBTT_SHIFT_SEL_V1)\n#define BIT_SET_RX_TBTT_SHIFT_SEL_V1(x, v)                                     \\\n\t(BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1(x) | BIT_RX_TBTT_SHIFT_SEL_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TBTT_INT_SHIFT_ENABLE\t\t(Offset 0x0598) */\n\n#define BIT_EN_TBTT_RTY BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FREERUN_CNT_H\t\t\t(Offset 0x0598) */\n\n#define BIT_SHIFT_FREERUN_CNT_H 0\n#define BIT_MASK_FREERUN_CNT_H 0xffffffffL\n#define BIT_FREERUN_CNT_H(x)                                                   \\\n\t(((x) & BIT_MASK_FREERUN_CNT_H) << BIT_SHIFT_FREERUN_CNT_H)\n#define BITS_FREERUN_CNT_H (BIT_MASK_FREERUN_CNT_H << BIT_SHIFT_FREERUN_CNT_H)\n#define BIT_CLEAR_FREERUN_CNT_H(x) ((x) & (~BITS_FREERUN_CNT_H))\n#define BIT_GET_FREERUN_CNT_H(x)                                               \\\n\t(((x) >> BIT_SHIFT_FREERUN_CNT_H) & BIT_MASK_FREERUN_CNT_H)\n#define BIT_SET_FREERUN_CNT_H(x, v)                                            \\\n\t(BIT_CLEAR_FREERUN_CNT_H(x) | BIT_FREERUN_CNT_H(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TBTT_INT_SHIFT_ENABLE\t\t(Offset 0x0598) */\n\n#define BIT_TBTT_INT_SHIFT_ENABLE BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ATIMWND2\t\t\t\t(Offset 0x05A0) */\n\n#define BIT_SHIFT_ATIMWND2 0\n#define BIT_MASK_ATIMWND2 0xff\n#define BIT_ATIMWND2(x) (((x) & BIT_MASK_ATIMWND2) << BIT_SHIFT_ATIMWND2)\n#define BITS_ATIMWND2 (BIT_MASK_ATIMWND2 << BIT_SHIFT_ATIMWND2)\n#define BIT_CLEAR_ATIMWND2(x) ((x) & (~BITS_ATIMWND2))\n#define BIT_GET_ATIMWND2(x) (((x) >> BIT_SHIFT_ATIMWND2) & BIT_MASK_ATIMWND2)\n#define BIT_SET_ATIMWND2(x, v) (BIT_CLEAR_ATIMWND2(x) | BIT_ATIMWND2(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_ATIMWND_GROUP1\t\t\t(Offset 0x05A0) */\n\n#define BIT_SHIFT_ATIMWND_GROUP1 0\n#define BIT_MASK_ATIMWND_GROUP1 0xff\n#define BIT_ATIMWND_GROUP1(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND_GROUP1) << BIT_SHIFT_ATIMWND_GROUP1)\n#define BITS_ATIMWND_GROUP1                                                    \\\n\t(BIT_MASK_ATIMWND_GROUP1 << BIT_SHIFT_ATIMWND_GROUP1)\n#define BIT_CLEAR_ATIMWND_GROUP1(x) ((x) & (~BITS_ATIMWND_GROUP1))\n#define BIT_GET_ATIMWND_GROUP1(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND_GROUP1) & BIT_MASK_ATIMWND_GROUP1)\n#define BIT_SET_ATIMWND_GROUP1(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND_GROUP1(x) | BIT_ATIMWND_GROUP1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ATIMWND3\t\t\t\t(Offset 0x05A1) */\n\n#define BIT_SHIFT_ATIMWND3 0\n#define BIT_MASK_ATIMWND3 0xff\n#define BIT_ATIMWND3(x) (((x) & BIT_MASK_ATIMWND3) << BIT_SHIFT_ATIMWND3)\n#define BITS_ATIMWND3 (BIT_MASK_ATIMWND3 << BIT_SHIFT_ATIMWND3)\n#define BIT_CLEAR_ATIMWND3(x) ((x) & (~BITS_ATIMWND3))\n#define BIT_GET_ATIMWND3(x) (((x) >> BIT_SHIFT_ATIMWND3) & BIT_MASK_ATIMWND3)\n#define BIT_SET_ATIMWND3(x, v) (BIT_CLEAR_ATIMWND3(x) | BIT_ATIMWND3(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_ATIMWND_GROUP2\t\t\t(Offset 0x05A1) */\n\n#define BIT_SHIFT_ATIMWND_GROUP2 0\n#define BIT_MASK_ATIMWND_GROUP2 0xff\n#define BIT_ATIMWND_GROUP2(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND_GROUP2) << BIT_SHIFT_ATIMWND_GROUP2)\n#define BITS_ATIMWND_GROUP2                                                    \\\n\t(BIT_MASK_ATIMWND_GROUP2 << BIT_SHIFT_ATIMWND_GROUP2)\n#define BIT_CLEAR_ATIMWND_GROUP2(x) ((x) & (~BITS_ATIMWND_GROUP2))\n#define BIT_GET_ATIMWND_GROUP2(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND_GROUP2) & BIT_MASK_ATIMWND_GROUP2)\n#define BIT_SET_ATIMWND_GROUP2(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND_GROUP2(x) | BIT_ATIMWND_GROUP2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ATIMWND4\t\t\t\t(Offset 0x05A2) */\n\n#define BIT_SHIFT_ATIMWND4 0\n#define BIT_MASK_ATIMWND4 0xff\n#define BIT_ATIMWND4(x) (((x) & BIT_MASK_ATIMWND4) << BIT_SHIFT_ATIMWND4)\n#define BITS_ATIMWND4 (BIT_MASK_ATIMWND4 << BIT_SHIFT_ATIMWND4)\n#define BIT_CLEAR_ATIMWND4(x) ((x) & (~BITS_ATIMWND4))\n#define BIT_GET_ATIMWND4(x) (((x) >> BIT_SHIFT_ATIMWND4) & BIT_MASK_ATIMWND4)\n#define BIT_SET_ATIMWND4(x, v) (BIT_CLEAR_ATIMWND4(x) | BIT_ATIMWND4(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_ATIMWND_GROUP3\t\t\t(Offset 0x05A2) */\n\n#define BIT_SHIFT_ATIMWND_GROUP3 0\n#define BIT_MASK_ATIMWND_GROUP3 0xff\n#define BIT_ATIMWND_GROUP3(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND_GROUP3) << BIT_SHIFT_ATIMWND_GROUP3)\n#define BITS_ATIMWND_GROUP3                                                    \\\n\t(BIT_MASK_ATIMWND_GROUP3 << BIT_SHIFT_ATIMWND_GROUP3)\n#define BIT_CLEAR_ATIMWND_GROUP3(x) ((x) & (~BITS_ATIMWND_GROUP3))\n#define BIT_GET_ATIMWND_GROUP3(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND_GROUP3) & BIT_MASK_ATIMWND_GROUP3)\n#define BIT_SET_ATIMWND_GROUP3(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND_GROUP3(x) | BIT_ATIMWND_GROUP3(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ATIMWND5\t\t\t\t(Offset 0x05A3) */\n\n#define BIT_SHIFT_ATIMWND5 0\n#define BIT_MASK_ATIMWND5 0xff\n#define BIT_ATIMWND5(x) (((x) & BIT_MASK_ATIMWND5) << BIT_SHIFT_ATIMWND5)\n#define BITS_ATIMWND5 (BIT_MASK_ATIMWND5 << BIT_SHIFT_ATIMWND5)\n#define BIT_CLEAR_ATIMWND5(x) ((x) & (~BITS_ATIMWND5))\n#define BIT_GET_ATIMWND5(x) (((x) >> BIT_SHIFT_ATIMWND5) & BIT_MASK_ATIMWND5)\n#define BIT_SET_ATIMWND5(x, v) (BIT_CLEAR_ATIMWND5(x) | BIT_ATIMWND5(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_ATIMWND_GROUP4\t\t\t(Offset 0x05A3) */\n\n#define BIT_SHIFT_ATIMWND_GROUP4 0\n#define BIT_MASK_ATIMWND_GROUP4 0xff\n#define BIT_ATIMWND_GROUP4(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND_GROUP4) << BIT_SHIFT_ATIMWND_GROUP4)\n#define BITS_ATIMWND_GROUP4                                                    \\\n\t(BIT_MASK_ATIMWND_GROUP4 << BIT_SHIFT_ATIMWND_GROUP4)\n#define BIT_CLEAR_ATIMWND_GROUP4(x) ((x) & (~BITS_ATIMWND_GROUP4))\n#define BIT_GET_ATIMWND_GROUP4(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND_GROUP4) & BIT_MASK_ATIMWND_GROUP4)\n#define BIT_SET_ATIMWND_GROUP4(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND_GROUP4(x) | BIT_ATIMWND_GROUP4(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ATIMWND6\t\t\t\t(Offset 0x05A4) */\n\n#define BIT_SHIFT_ATIMWND6 0\n#define BIT_MASK_ATIMWND6 0xff\n#define BIT_ATIMWND6(x) (((x) & BIT_MASK_ATIMWND6) << BIT_SHIFT_ATIMWND6)\n#define BITS_ATIMWND6 (BIT_MASK_ATIMWND6 << BIT_SHIFT_ATIMWND6)\n#define BIT_CLEAR_ATIMWND6(x) ((x) & (~BITS_ATIMWND6))\n#define BIT_GET_ATIMWND6(x) (((x) >> BIT_SHIFT_ATIMWND6) & BIT_MASK_ATIMWND6)\n#define BIT_SET_ATIMWND6(x, v) (BIT_CLEAR_ATIMWND6(x) | BIT_ATIMWND6(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DTIM_COUNT_GROUP1\t\t\t(Offset 0x05A4) */\n\n#define BIT_SHIFT_DTIM_COUNT_GROUP1 0\n#define BIT_MASK_DTIM_COUNT_GROUP1 0xff\n#define BIT_DTIM_COUNT_GROUP1(x)                                               \\\n\t(((x) & BIT_MASK_DTIM_COUNT_GROUP1) << BIT_SHIFT_DTIM_COUNT_GROUP1)\n#define BITS_DTIM_COUNT_GROUP1                                                 \\\n\t(BIT_MASK_DTIM_COUNT_GROUP1 << BIT_SHIFT_DTIM_COUNT_GROUP1)\n#define BIT_CLEAR_DTIM_COUNT_GROUP1(x) ((x) & (~BITS_DTIM_COUNT_GROUP1))\n#define BIT_GET_DTIM_COUNT_GROUP1(x)                                           \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_GROUP1) & BIT_MASK_DTIM_COUNT_GROUP1)\n#define BIT_SET_DTIM_COUNT_GROUP1(x, v)                                        \\\n\t(BIT_CLEAR_DTIM_COUNT_GROUP1(x) | BIT_DTIM_COUNT_GROUP1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ATIMWND7\t\t\t\t(Offset 0x05A5) */\n\n#define BIT_SHIFT_ATIMWND7 0\n#define BIT_MASK_ATIMWND7 0xff\n#define BIT_ATIMWND7(x) (((x) & BIT_MASK_ATIMWND7) << BIT_SHIFT_ATIMWND7)\n#define BITS_ATIMWND7 (BIT_MASK_ATIMWND7 << BIT_SHIFT_ATIMWND7)\n#define BIT_CLEAR_ATIMWND7(x) ((x) & (~BITS_ATIMWND7))\n#define BIT_GET_ATIMWND7(x) (((x) >> BIT_SHIFT_ATIMWND7) & BIT_MASK_ATIMWND7)\n#define BIT_SET_ATIMWND7(x, v) (BIT_CLEAR_ATIMWND7(x) | BIT_ATIMWND7(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DTIM_COUNT_GROUP2\t\t\t(Offset 0x05A5) */\n\n#define BIT_SHIFT_DTIM_COUNT_GROUP2 0\n#define BIT_MASK_DTIM_COUNT_GROUP2 0xff\n#define BIT_DTIM_COUNT_GROUP2(x)                                               \\\n\t(((x) & BIT_MASK_DTIM_COUNT_GROUP2) << BIT_SHIFT_DTIM_COUNT_GROUP2)\n#define BITS_DTIM_COUNT_GROUP2                                                 \\\n\t(BIT_MASK_DTIM_COUNT_GROUP2 << BIT_SHIFT_DTIM_COUNT_GROUP2)\n#define BIT_CLEAR_DTIM_COUNT_GROUP2(x) ((x) & (~BITS_DTIM_COUNT_GROUP2))\n#define BIT_GET_DTIM_COUNT_GROUP2(x)                                           \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_GROUP2) & BIT_MASK_DTIM_COUNT_GROUP2)\n#define BIT_SET_DTIM_COUNT_GROUP2(x, v)                                        \\\n\t(BIT_CLEAR_DTIM_COUNT_GROUP2(x) | BIT_DTIM_COUNT_GROUP2(v))\n\n/* 2 REG_DTIM_COUNT_GROUP3\t\t\t(Offset 0x05A6) */\n\n#define BIT_SHIFT_DTIM_COUNT_GROUP3 0\n#define BIT_MASK_DTIM_COUNT_GROUP3 0xff\n#define BIT_DTIM_COUNT_GROUP3(x)                                               \\\n\t(((x) & BIT_MASK_DTIM_COUNT_GROUP3) << BIT_SHIFT_DTIM_COUNT_GROUP3)\n#define BITS_DTIM_COUNT_GROUP3                                                 \\\n\t(BIT_MASK_DTIM_COUNT_GROUP3 << BIT_SHIFT_DTIM_COUNT_GROUP3)\n#define BIT_CLEAR_DTIM_COUNT_GROUP3(x) ((x) & (~BITS_DTIM_COUNT_GROUP3))\n#define BIT_GET_DTIM_COUNT_GROUP3(x)                                           \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_GROUP3) & BIT_MASK_DTIM_COUNT_GROUP3)\n#define BIT_SET_DTIM_COUNT_GROUP3(x, v)                                        \\\n\t(BIT_CLEAR_DTIM_COUNT_GROUP3(x) | BIT_DTIM_COUNT_GROUP3(v))\n\n/* 2 REG_DTIM_COUNT_GROUP4\t\t\t(Offset 0x05A7) */\n\n#define BIT_SHIFT_ATIM_CFG_SEL 24\n#define BIT_MASK_ATIM_CFG_SEL 0x3\n#define BIT_ATIM_CFG_SEL(x)                                                    \\\n\t(((x) & BIT_MASK_ATIM_CFG_SEL) << BIT_SHIFT_ATIM_CFG_SEL)\n#define BITS_ATIM_CFG_SEL (BIT_MASK_ATIM_CFG_SEL << BIT_SHIFT_ATIM_CFG_SEL)\n#define BIT_CLEAR_ATIM_CFG_SEL(x) ((x) & (~BITS_ATIM_CFG_SEL))\n#define BIT_GET_ATIM_CFG_SEL(x)                                                \\\n\t(((x) >> BIT_SHIFT_ATIM_CFG_SEL) & BIT_MASK_ATIM_CFG_SEL)\n#define BIT_SET_ATIM_CFG_SEL(x, v)                                             \\\n\t(BIT_CLEAR_ATIM_CFG_SEL(x) | BIT_ATIM_CFG_SEL(v))\n\n#define BIT_SHIFT_ATIM_URGENT_V1 16\n#define BIT_MASK_ATIM_URGENT_V1 0xff\n#define BIT_ATIM_URGENT_V1(x)                                                  \\\n\t(((x) & BIT_MASK_ATIM_URGENT_V1) << BIT_SHIFT_ATIM_URGENT_V1)\n#define BITS_ATIM_URGENT_V1                                                    \\\n\t(BIT_MASK_ATIM_URGENT_V1 << BIT_SHIFT_ATIM_URGENT_V1)\n#define BIT_CLEAR_ATIM_URGENT_V1(x) ((x) & (~BITS_ATIM_URGENT_V1))\n#define BIT_GET_ATIM_URGENT_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIM_URGENT_V1) & BIT_MASK_ATIM_URGENT_V1)\n#define BIT_SET_ATIM_URGENT_V1(x, v)                                           \\\n\t(BIT_CLEAR_ATIM_URGENT_V1(x) | BIT_ATIM_URGENT_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIQ_NO_LMT_EN\t\t\t(Offset 0x05A7) */\n\n#define BIT_HIQ_NO_LMT_EN_VAP7 BIT(7)\n#define BIT_HIQ_NO_LMT_EN_VAP6 BIT(6)\n#define BIT_HIQ_NO_LMT_EN_VAP5 BIT(5)\n#define BIT_HIQ_NO_LMT_EN_VAP4 BIT(4)\n#define BIT_HIQ_NO_LMT_EN_VAP3 BIT(3)\n#define BIT_HIQ_NO_LMT_EN_VAP2 BIT(2)\n#define BIT_HIQ_NO_LMT_EN_VAP1 BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_HIQ_NO_LMT_EN\t\t\t(Offset 0x05A7) */\n\n#define BIT_HIQ_NO_LMT_EN_ROOT BIT(0)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DTIM_COUNT_GROUP4\t\t\t(Offset 0x05A7) */\n\n#define BIT_SHIFT_DTIM_COUNT_GROUP4 0\n#define BIT_MASK_DTIM_COUNT_GROUP4 0xff\n#define BIT_DTIM_COUNT_GROUP4(x)                                               \\\n\t(((x) & BIT_MASK_DTIM_COUNT_GROUP4) << BIT_SHIFT_DTIM_COUNT_GROUP4)\n#define BITS_DTIM_COUNT_GROUP4                                                 \\\n\t(BIT_MASK_DTIM_COUNT_GROUP4 << BIT_SHIFT_DTIM_COUNT_GROUP4)\n#define BIT_CLEAR_DTIM_COUNT_GROUP4(x) ((x) & (~BITS_DTIM_COUNT_GROUP4))\n#define BIT_GET_DTIM_COUNT_GROUP4(x)                                           \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_GROUP4) & BIT_MASK_DTIM_COUNT_GROUP4)\n#define BIT_SET_DTIM_COUNT_GROUP4(x, v)                                        \\\n\t(BIT_CLEAR_DTIM_COUNT_GROUP4(x) | BIT_DTIM_COUNT_GROUP4(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HIQ_NO_LMT_EN_V2\t\t\t(Offset 0x05A8) */\n\n#define BIT_SHIFT_DIS_ATIM 16\n#define BIT_MASK_DIS_ATIM 0xffff\n#define BIT_DIS_ATIM(x) (((x) & BIT_MASK_DIS_ATIM) << BIT_SHIFT_DIS_ATIM)\n#define BITS_DIS_ATIM (BIT_MASK_DIS_ATIM << BIT_SHIFT_DIS_ATIM)\n#define BIT_CLEAR_DIS_ATIM(x) ((x) & (~BITS_DIS_ATIM))\n#define BIT_GET_DIS_ATIM(x) (((x) >> BIT_SHIFT_DIS_ATIM) & BIT_MASK_DIS_ATIM)\n#define BIT_SET_DIS_ATIM(x, v) (BIT_CLEAR_DIS_ATIM(x) | BIT_DIS_ATIM(v))\n\n#define BIT_SHIFT_BCNERR_PORT_SEL_V1 16\n#define BIT_MASK_BCNERR_PORT_SEL_V1 0xf\n#define BIT_BCNERR_PORT_SEL_V1(x)                                              \\\n\t(((x) & BIT_MASK_BCNERR_PORT_SEL_V1) << BIT_SHIFT_BCNERR_PORT_SEL_V1)\n#define BITS_BCNERR_PORT_SEL_V1                                                \\\n\t(BIT_MASK_BCNERR_PORT_SEL_V1 << BIT_SHIFT_BCNERR_PORT_SEL_V1)\n#define BIT_CLEAR_BCNERR_PORT_SEL_V1(x) ((x) & (~BITS_BCNERR_PORT_SEL_V1))\n#define BIT_GET_BCNERR_PORT_SEL_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_BCNERR_PORT_SEL_V1) & BIT_MASK_BCNERR_PORT_SEL_V1)\n#define BIT_SET_BCNERR_PORT_SEL_V1(x, v)                                       \\\n\t(BIT_CLEAR_BCNERR_PORT_SEL_V1(x) | BIT_BCNERR_PORT_SEL_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DTIM_COUNTER_ROOT\t\t\t(Offset 0x05A8) */\n\n#define BIT_SHIFT_DTIM_COUNT_ROOT 0\n#define BIT_MASK_DTIM_COUNT_ROOT 0xff\n#define BIT_DTIM_COUNT_ROOT(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_COUNT_ROOT) << BIT_SHIFT_DTIM_COUNT_ROOT)\n#define BITS_DTIM_COUNT_ROOT                                                   \\\n\t(BIT_MASK_DTIM_COUNT_ROOT << BIT_SHIFT_DTIM_COUNT_ROOT)\n#define BIT_CLEAR_DTIM_COUNT_ROOT(x) ((x) & (~BITS_DTIM_COUNT_ROOT))\n#define BIT_GET_DTIM_COUNT_ROOT(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_ROOT) & BIT_MASK_DTIM_COUNT_ROOT)\n#define BIT_SET_DTIM_COUNT_ROOT(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_COUNT_ROOT(x) | BIT_DTIM_COUNT_ROOT(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HIQ_NO_LMT_EN_V2\t\t\t(Offset 0x05A8) */\n\n#define BIT_SHIFT_MBID_BCNQ_EN 0\n#define BIT_MASK_MBID_BCNQ_EN 0xffff\n#define BIT_MBID_BCNQ_EN(x)                                                    \\\n\t(((x) & BIT_MASK_MBID_BCNQ_EN) << BIT_SHIFT_MBID_BCNQ_EN)\n#define BITS_MBID_BCNQ_EN (BIT_MASK_MBID_BCNQ_EN << BIT_SHIFT_MBID_BCNQ_EN)\n#define BIT_CLEAR_MBID_BCNQ_EN(x) ((x) & (~BITS_MBID_BCNQ_EN))\n#define BIT_GET_MBID_BCNQ_EN(x)                                                \\\n\t(((x) >> BIT_SHIFT_MBID_BCNQ_EN) & BIT_MASK_MBID_BCNQ_EN)\n#define BIT_SET_MBID_BCNQ_EN(x, v)                                             \\\n\t(BIT_CLEAR_MBID_BCNQ_EN(x) | BIT_MBID_BCNQ_EN(v))\n\n#define BIT_TSF_SYNC_SIGNAL BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DTIM_COUNTER_VAP1\t\t\t(Offset 0x05A9) */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP1 0\n#define BIT_MASK_DTIM_COUNT_VAP1 0xff\n#define BIT_DTIM_COUNT_VAP1(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP1) << BIT_SHIFT_DTIM_COUNT_VAP1)\n#define BITS_DTIM_COUNT_VAP1                                                   \\\n\t(BIT_MASK_DTIM_COUNT_VAP1 << BIT_SHIFT_DTIM_COUNT_VAP1)\n#define BIT_CLEAR_DTIM_COUNT_VAP1(x) ((x) & (~BITS_DTIM_COUNT_VAP1))\n#define BIT_GET_DTIM_COUNT_VAP1(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP1) & BIT_MASK_DTIM_COUNT_VAP1)\n#define BIT_SET_DTIM_COUNT_VAP1(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP1(x) | BIT_DTIM_COUNT_VAP1(v))\n\n/* 2 REG_DTIM_COUNTER_VAP2\t\t\t(Offset 0x05AA) */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP2 0\n#define BIT_MASK_DTIM_COUNT_VAP2 0xff\n#define BIT_DTIM_COUNT_VAP2(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP2) << BIT_SHIFT_DTIM_COUNT_VAP2)\n#define BITS_DTIM_COUNT_VAP2                                                   \\\n\t(BIT_MASK_DTIM_COUNT_VAP2 << BIT_SHIFT_DTIM_COUNT_VAP2)\n#define BIT_CLEAR_DTIM_COUNT_VAP2(x) ((x) & (~BITS_DTIM_COUNT_VAP2))\n#define BIT_GET_DTIM_COUNT_VAP2(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP2) & BIT_MASK_DTIM_COUNT_VAP2)\n#define BIT_SET_DTIM_COUNT_VAP2(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP2(x) | BIT_DTIM_COUNT_VAP2(v))\n\n/* 2 REG_DTIM_COUNTER_VAP3\t\t\t(Offset 0x05AB) */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP3 0\n#define BIT_MASK_DTIM_COUNT_VAP3 0xff\n#define BIT_DTIM_COUNT_VAP3(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP3) << BIT_SHIFT_DTIM_COUNT_VAP3)\n#define BITS_DTIM_COUNT_VAP3                                                   \\\n\t(BIT_MASK_DTIM_COUNT_VAP3 << BIT_SHIFT_DTIM_COUNT_VAP3)\n#define BIT_CLEAR_DTIM_COUNT_VAP3(x) ((x) & (~BITS_DTIM_COUNT_VAP3))\n#define BIT_GET_DTIM_COUNT_VAP3(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP3) & BIT_MASK_DTIM_COUNT_VAP3)\n#define BIT_SET_DTIM_COUNT_VAP3(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP3(x) | BIT_DTIM_COUNT_VAP3(v))\n\n/* 2 REG_DTIM_COUNTER_VAP4\t\t\t(Offset 0x05AC) */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP4 0\n#define BIT_MASK_DTIM_COUNT_VAP4 0xff\n#define BIT_DTIM_COUNT_VAP4(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP4) << BIT_SHIFT_DTIM_COUNT_VAP4)\n#define BITS_DTIM_COUNT_VAP4                                                   \\\n\t(BIT_MASK_DTIM_COUNT_VAP4 << BIT_SHIFT_DTIM_COUNT_VAP4)\n#define BIT_CLEAR_DTIM_COUNT_VAP4(x) ((x) & (~BITS_DTIM_COUNT_VAP4))\n#define BIT_GET_DTIM_COUNT_VAP4(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP4) & BIT_MASK_DTIM_COUNT_VAP4)\n#define BIT_SET_DTIM_COUNT_VAP4(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP4(x) | BIT_DTIM_COUNT_VAP4(v))\n\n/* 2 REG_DTIM_COUNTER_VAP5\t\t\t(Offset 0x05AD) */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP5 0\n#define BIT_MASK_DTIM_COUNT_VAP5 0xff\n#define BIT_DTIM_COUNT_VAP5(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP5) << BIT_SHIFT_DTIM_COUNT_VAP5)\n#define BITS_DTIM_COUNT_VAP5                                                   \\\n\t(BIT_MASK_DTIM_COUNT_VAP5 << BIT_SHIFT_DTIM_COUNT_VAP5)\n#define BIT_CLEAR_DTIM_COUNT_VAP5(x) ((x) & (~BITS_DTIM_COUNT_VAP5))\n#define BIT_GET_DTIM_COUNT_VAP5(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP5) & BIT_MASK_DTIM_COUNT_VAP5)\n#define BIT_SET_DTIM_COUNT_VAP5(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP5(x) | BIT_DTIM_COUNT_VAP5(v))\n\n/* 2 REG_DTIM_COUNTER_VAP6\t\t\t(Offset 0x05AE) */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP6 0\n#define BIT_MASK_DTIM_COUNT_VAP6 0xff\n#define BIT_DTIM_COUNT_VAP6(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP6) << BIT_SHIFT_DTIM_COUNT_VAP6)\n#define BITS_DTIM_COUNT_VAP6                                                   \\\n\t(BIT_MASK_DTIM_COUNT_VAP6 << BIT_SHIFT_DTIM_COUNT_VAP6)\n#define BIT_CLEAR_DTIM_COUNT_VAP6(x) ((x) & (~BITS_DTIM_COUNT_VAP6))\n#define BIT_GET_DTIM_COUNT_VAP6(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP6) & BIT_MASK_DTIM_COUNT_VAP6)\n#define BIT_SET_DTIM_COUNT_VAP6(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP6(x) | BIT_DTIM_COUNT_VAP6(v))\n\n/* 2 REG_DTIM_COUNTER_VAP7\t\t\t(Offset 0x05AF) */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP7 0\n#define BIT_MASK_DTIM_COUNT_VAP7 0xff\n#define BIT_DTIM_COUNT_VAP7(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP7) << BIT_SHIFT_DTIM_COUNT_VAP7)\n#define BITS_DTIM_COUNT_VAP7                                                   \\\n\t(BIT_MASK_DTIM_COUNT_VAP7 << BIT_SHIFT_DTIM_COUNT_VAP7)\n#define BIT_CLEAR_DTIM_COUNT_VAP7(x) ((x) & (~BITS_DTIM_COUNT_VAP7))\n#define BIT_GET_DTIM_COUNT_VAP7(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP7) & BIT_MASK_DTIM_COUNT_VAP7)\n#define BIT_SET_DTIM_COUNT_VAP7(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP7(x) | BIT_DTIM_COUNT_VAP7(v))\n\n/* 2 REG_DIS_ATIM\t\t\t\t(Offset 0x05B0) */\n\n#define BIT_MBIDCAM_VALID BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DIS_ATIM\t\t\t\t(Offset 0x05B0) */\n\n#define BIT_DIS_ATIM_VAP7 BIT(7)\n#define BIT_DIS_ATIM_VAP6 BIT(6)\n#define BIT_DIS_ATIM_VAP5 BIT(5)\n#define BIT_DIS_ATIM_VAP4 BIT(4)\n#define BIT_DIS_ATIM_VAP3 BIT(3)\n#define BIT_DIS_ATIM_VAP2 BIT(2)\n#define BIT_DIS_ATIM_VAP1 BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_DIS_ATIM\t\t\t\t(Offset 0x05B0) */\n\n#define BIT_DIS_ATIM_ROOT BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_EARLY_128US\t\t\t\t(Offset 0x05B1) */\n\n#define BIT_SHIFT_EARLY_128US_2ST 3\n#define BIT_MASK_EARLY_128US_2ST 0x7\n#define BIT_EARLY_128US_2ST(x)                                                 \\\n\t(((x) & BIT_MASK_EARLY_128US_2ST) << BIT_SHIFT_EARLY_128US_2ST)\n#define BITS_EARLY_128US_2ST                                                   \\\n\t(BIT_MASK_EARLY_128US_2ST << BIT_SHIFT_EARLY_128US_2ST)\n#define BIT_CLEAR_EARLY_128US_2ST(x) ((x) & (~BITS_EARLY_128US_2ST))\n#define BIT_GET_EARLY_128US_2ST(x)                                             \\\n\t(((x) >> BIT_SHIFT_EARLY_128US_2ST) & BIT_MASK_EARLY_128US_2ST)\n#define BIT_SET_EARLY_128US_2ST(x, v)                                          \\\n\t(BIT_CLEAR_EARLY_128US_2ST(x) | BIT_EARLY_128US_2ST(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_EARLY_128US\t\t\t\t(Offset 0x05B1) */\n\n#define BIT_SHIFT_TSFT_SEL_TIMER1 3\n#define BIT_MASK_TSFT_SEL_TIMER1 0x7\n#define BIT_TSFT_SEL_TIMER1(x)                                                 \\\n\t(((x) & BIT_MASK_TSFT_SEL_TIMER1) << BIT_SHIFT_TSFT_SEL_TIMER1)\n#define BITS_TSFT_SEL_TIMER1                                                   \\\n\t(BIT_MASK_TSFT_SEL_TIMER1 << BIT_SHIFT_TSFT_SEL_TIMER1)\n#define BIT_CLEAR_TSFT_SEL_TIMER1(x) ((x) & (~BITS_TSFT_SEL_TIMER1))\n#define BIT_GET_TSFT_SEL_TIMER1(x)                                             \\\n\t(((x) >> BIT_SHIFT_TSFT_SEL_TIMER1) & BIT_MASK_TSFT_SEL_TIMER1)\n#define BIT_SET_TSFT_SEL_TIMER1(x, v)                                          \\\n\t(BIT_CLEAR_TSFT_SEL_TIMER1(x) | BIT_TSFT_SEL_TIMER1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TBTT_HOLD_PREDICT_P1\t\t(Offset 0x05B2) */\n\n#define BIT_DIS_BCN_3RD BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PPS1_CTRL\t\t\t\t(Offset 0x05B2) */\n\n#define BIT_P2P1_CTW_ALLSTASLEEP BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TBTT_HOLD_PREDICT_P1\t\t(Offset 0x05B2) */\n\n#define BIT_DIS_BCN_2ST BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PPS1_CTRL\t\t\t\t(Offset 0x05B2) */\n\n#define BIT_P2P1_OFF_DISTX_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TBTT_HOLD_PREDICT_P1\t\t(Offset 0x05B2) */\n\n#define BIT_DIS_BCN_1ST BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PPS1_CTRL\t\t\t\t(Offset 0x05B2) */\n\n#define BIT_P2P1_PWR_MGT_EN BIT(5)\n#define BIT_P2P1_NOA1_EN BIT(2)\n#define BIT_P2P1_NOA0_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TBTT_HOLD_PREDICT_P1\t\t(Offset 0x05B2) */\n\n#define BIT_SHIFT_TBTT_HOLD_PREDICT_P1 0\n#define BIT_MASK_TBTT_HOLD_PREDICT_P1 0x1f\n#define BIT_TBTT_HOLD_PREDICT_P1(x)                                            \\\n\t(((x) & BIT_MASK_TBTT_HOLD_PREDICT_P1)                                 \\\n\t << BIT_SHIFT_TBTT_HOLD_PREDICT_P1)\n#define BITS_TBTT_HOLD_PREDICT_P1                                              \\\n\t(BIT_MASK_TBTT_HOLD_PREDICT_P1 << BIT_SHIFT_TBTT_HOLD_PREDICT_P1)\n#define BIT_CLEAR_TBTT_HOLD_PREDICT_P1(x) ((x) & (~BITS_TBTT_HOLD_PREDICT_P1))\n#define BIT_GET_TBTT_HOLD_PREDICT_P1(x)                                        \\\n\t(((x) >> BIT_SHIFT_TBTT_HOLD_PREDICT_P1) &                             \\\n\t BIT_MASK_TBTT_HOLD_PREDICT_P1)\n#define BIT_SET_TBTT_HOLD_PREDICT_P1(x, v)                                     \\\n\t(BIT_CLEAR_TBTT_HOLD_PREDICT_P1(x) | BIT_TBTT_HOLD_PREDICT_P1(v))\n\n/* 2 REG_MULTI_BCN_CS\t\t\t(Offset 0x05B3) */\n\n#define BIT_EN_FREECNT_V2 BIT(13)\n#define BIT_RESET_FREECNT_P BIT(12)\n#define BIT_TSFTR3_SYNC_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PPS2_CTRL\t\t\t\t(Offset 0x05B3) */\n\n#define BIT_P2P2_CTW_ALLSTASLEEP BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MULTI_BCN_CS\t\t\t(Offset 0x05B3) */\n\n#define BIT_SHIFT_P1_TSFT_SHIFT 6\n#define BIT_MASK_P1_TSFT_SHIFT 0x3f\n#define BIT_P1_TSFT_SHIFT(x)                                                   \\\n\t(((x) & BIT_MASK_P1_TSFT_SHIFT) << BIT_SHIFT_P1_TSFT_SHIFT)\n#define BITS_P1_TSFT_SHIFT (BIT_MASK_P1_TSFT_SHIFT << BIT_SHIFT_P1_TSFT_SHIFT)\n#define BIT_CLEAR_P1_TSFT_SHIFT(x) ((x) & (~BITS_P1_TSFT_SHIFT))\n#define BIT_GET_P1_TSFT_SHIFT(x)                                               \\\n\t(((x) >> BIT_SHIFT_P1_TSFT_SHIFT) & BIT_MASK_P1_TSFT_SHIFT)\n#define BIT_SET_P1_TSFT_SHIFT(x, v)                                            \\\n\t(BIT_CLEAR_P1_TSFT_SHIFT(x) | BIT_P1_TSFT_SHIFT(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PPS2_CTRL\t\t\t\t(Offset 0x05B3) */\n\n#define BIT_P2P2_OFF_DISTX_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MULTI_BCN_CS\t\t\t(Offset 0x05B3) */\n\n#define BIT_TSFTR2_SYNC_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PPS2_CTRL\t\t\t\t(Offset 0x05B3) */\n\n#define BIT_P2P2_PWR_MGT_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MULTI_BCN_CS\t\t\t(Offset 0x05B3) */\n\n#define BIT_TSFTR2_RST BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PPS2_CTRL\t\t\t\t(Offset 0x05B3) */\n\n#define BIT_P2P2_NOA1_EN BIT(2)\n#define BIT_P2P2_NOA0_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MULTI_BCN_CS\t\t\t(Offset 0x05B3) */\n\n#define BIT_SHIFT_MULTI_BCN_CS 0\n#define BIT_MASK_MULTI_BCN_CS 0xf\n#define BIT_MULTI_BCN_CS(x)                                                    \\\n\t(((x) & BIT_MASK_MULTI_BCN_CS) << BIT_SHIFT_MULTI_BCN_CS)\n#define BITS_MULTI_BCN_CS (BIT_MASK_MULTI_BCN_CS << BIT_SHIFT_MULTI_BCN_CS)\n#define BIT_CLEAR_MULTI_BCN_CS(x) ((x) & (~BITS_MULTI_BCN_CS))\n#define BIT_GET_MULTI_BCN_CS(x)                                                \\\n\t(((x) >> BIT_SHIFT_MULTI_BCN_CS) & BIT_MASK_MULTI_BCN_CS)\n#define BIT_SET_MULTI_BCN_CS(x, v)                                             \\\n\t(BIT_CLEAR_MULTI_BCN_CS(x) | BIT_MULTI_BCN_CS(v))\n\n#define BIT_SHIFT_P0_TSFT_SHIFT 0\n#define BIT_MASK_P0_TSFT_SHIFT 0x3f\n#define BIT_P0_TSFT_SHIFT(x)                                                   \\\n\t(((x) & BIT_MASK_P0_TSFT_SHIFT) << BIT_SHIFT_P0_TSFT_SHIFT)\n#define BITS_P0_TSFT_SHIFT (BIT_MASK_P0_TSFT_SHIFT << BIT_SHIFT_P0_TSFT_SHIFT)\n#define BIT_CLEAR_P0_TSFT_SHIFT(x) ((x) & (~BITS_P0_TSFT_SHIFT))\n#define BIT_GET_P0_TSFT_SHIFT(x)                                               \\\n\t(((x) >> BIT_SHIFT_P0_TSFT_SHIFT) & BIT_MASK_P0_TSFT_SHIFT)\n#define BIT_SET_P0_TSFT_SHIFT(x, v)                                            \\\n\t(BIT_CLEAR_P0_TSFT_SHIFT(x) | BIT_P0_TSFT_SHIFT(v))\n\n#define BIT_DIS_NDPA_NAV_CHK_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TIMER0_SRC_SEL\t\t\t(Offset 0x05B4) */\n\n#define BIT_SHIFT_SYNC_CLI_SEL 4\n#define BIT_MASK_SYNC_CLI_SEL 0x7\n#define BIT_SYNC_CLI_SEL(x)                                                    \\\n\t(((x) & BIT_MASK_SYNC_CLI_SEL) << BIT_SHIFT_SYNC_CLI_SEL)\n#define BITS_SYNC_CLI_SEL (BIT_MASK_SYNC_CLI_SEL << BIT_SHIFT_SYNC_CLI_SEL)\n#define BIT_CLEAR_SYNC_CLI_SEL(x) ((x) & (~BITS_SYNC_CLI_SEL))\n#define BIT_GET_SYNC_CLI_SEL(x)                                                \\\n\t(((x) >> BIT_SHIFT_SYNC_CLI_SEL) & BIT_MASK_SYNC_CLI_SEL)\n#define BIT_SET_SYNC_CLI_SEL(x, v)                                             \\\n\t(BIT_CLEAR_SYNC_CLI_SEL(x) | BIT_SYNC_CLI_SEL(v))\n\n#define BIT_SHIFT_TSFT_SEL_TIMER0 0\n#define BIT_MASK_TSFT_SEL_TIMER0 0x7\n#define BIT_TSFT_SEL_TIMER0(x)                                                 \\\n\t(((x) & BIT_MASK_TSFT_SEL_TIMER0) << BIT_SHIFT_TSFT_SEL_TIMER0)\n#define BITS_TSFT_SEL_TIMER0                                                   \\\n\t(BIT_MASK_TSFT_SEL_TIMER0 << BIT_SHIFT_TSFT_SEL_TIMER0)\n#define BIT_CLEAR_TSFT_SEL_TIMER0(x) ((x) & (~BITS_TSFT_SEL_TIMER0))\n#define BIT_GET_TSFT_SEL_TIMER0(x)                                             \\\n\t(((x) >> BIT_SHIFT_TSFT_SEL_TIMER0) & BIT_MASK_TSFT_SEL_TIMER0)\n#define BIT_SET_TSFT_SEL_TIMER0(x, v)                                          \\\n\t(BIT_CLEAR_TSFT_SEL_TIMER0(x) | BIT_TSFT_SEL_TIMER0(v))\n\n/* 2 REG_NOA_UNIT_SEL\t\t\t(Offset 0x05B5) */\n\n#define BIT_SHIFT_NOA_UNIT2_SEL 8\n#define BIT_MASK_NOA_UNIT2_SEL 0x7\n#define BIT_NOA_UNIT2_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_NOA_UNIT2_SEL) << BIT_SHIFT_NOA_UNIT2_SEL)\n#define BITS_NOA_UNIT2_SEL (BIT_MASK_NOA_UNIT2_SEL << BIT_SHIFT_NOA_UNIT2_SEL)\n#define BIT_CLEAR_NOA_UNIT2_SEL(x) ((x) & (~BITS_NOA_UNIT2_SEL))\n#define BIT_GET_NOA_UNIT2_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT2_SEL) & BIT_MASK_NOA_UNIT2_SEL)\n#define BIT_SET_NOA_UNIT2_SEL(x, v)                                            \\\n\t(BIT_CLEAR_NOA_UNIT2_SEL(x) | BIT_NOA_UNIT2_SEL(v))\n\n#define BIT_SHIFT_NOA_UNIT1_SEL 4\n#define BIT_MASK_NOA_UNIT1_SEL 0x7\n#define BIT_NOA_UNIT1_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_NOA_UNIT1_SEL) << BIT_SHIFT_NOA_UNIT1_SEL)\n#define BITS_NOA_UNIT1_SEL (BIT_MASK_NOA_UNIT1_SEL << BIT_SHIFT_NOA_UNIT1_SEL)\n#define BIT_CLEAR_NOA_UNIT1_SEL(x) ((x) & (~BITS_NOA_UNIT1_SEL))\n#define BIT_GET_NOA_UNIT1_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT1_SEL) & BIT_MASK_NOA_UNIT1_SEL)\n#define BIT_SET_NOA_UNIT1_SEL(x, v)                                            \\\n\t(BIT_CLEAR_NOA_UNIT1_SEL(x) | BIT_NOA_UNIT1_SEL(v))\n\n#define BIT_SHIFT_NOA_UNIT0_SEL 0\n#define BIT_MASK_NOA_UNIT0_SEL 0x7\n#define BIT_NOA_UNIT0_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_NOA_UNIT0_SEL) << BIT_SHIFT_NOA_UNIT0_SEL)\n#define BITS_NOA_UNIT0_SEL (BIT_MASK_NOA_UNIT0_SEL << BIT_SHIFT_NOA_UNIT0_SEL)\n#define BIT_CLEAR_NOA_UNIT0_SEL(x) ((x) & (~BITS_NOA_UNIT0_SEL))\n#define BIT_GET_NOA_UNIT0_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT0_SEL) & BIT_MASK_NOA_UNIT0_SEL)\n#define BIT_SET_NOA_UNIT0_SEL(x, v)                                            \\\n\t(BIT_CLEAR_NOA_UNIT0_SEL(x) | BIT_NOA_UNIT0_SEL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2POFF_DIS_TXTIME\t\t\t(Offset 0x05B7) */\n\n#define BIT_SHIFT_P2POFF_DIS_TXTIME 0\n#define BIT_MASK_P2POFF_DIS_TXTIME 0xff\n#define BIT_P2POFF_DIS_TXTIME(x)                                               \\\n\t(((x) & BIT_MASK_P2POFF_DIS_TXTIME) << BIT_SHIFT_P2POFF_DIS_TXTIME)\n#define BITS_P2POFF_DIS_TXTIME                                                 \\\n\t(BIT_MASK_P2POFF_DIS_TXTIME << BIT_SHIFT_P2POFF_DIS_TXTIME)\n#define BIT_CLEAR_P2POFF_DIS_TXTIME(x) ((x) & (~BITS_P2POFF_DIS_TXTIME))\n#define BIT_GET_P2POFF_DIS_TXTIME(x)                                           \\\n\t(((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME) & BIT_MASK_P2POFF_DIS_TXTIME)\n#define BIT_SET_P2POFF_DIS_TXTIME(x, v)                                        \\\n\t(BIT_CLEAR_P2POFF_DIS_TXTIME(x) | BIT_P2POFF_DIS_TXTIME(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MBSSID_BCN_SPACE2\t\t\t(Offset 0x05B8) */\n\n#define BIT_SHIFT_BCN_SPACE_CLINT2 16\n#define BIT_MASK_BCN_SPACE_CLINT2 0xfff\n#define BIT_BCN_SPACE_CLINT2(x)                                                \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT2) << BIT_SHIFT_BCN_SPACE_CLINT2)\n#define BITS_BCN_SPACE_CLINT2                                                  \\\n\t(BIT_MASK_BCN_SPACE_CLINT2 << BIT_SHIFT_BCN_SPACE_CLINT2)\n#define BIT_CLEAR_BCN_SPACE_CLINT2(x) ((x) & (~BITS_BCN_SPACE_CLINT2))\n#define BIT_GET_BCN_SPACE_CLINT2(x)                                            \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT2) & BIT_MASK_BCN_SPACE_CLINT2)\n#define BIT_SET_BCN_SPACE_CLINT2(x, v)                                         \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT2(x) | BIT_BCN_SPACE_CLINT2(v))\n\n#define BIT_SHIFT_BCN_SPACE_CLINT1 0\n#define BIT_MASK_BCN_SPACE_CLINT1 0xfff\n#define BIT_BCN_SPACE_CLINT1(x)                                                \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT1) << BIT_SHIFT_BCN_SPACE_CLINT1)\n#define BITS_BCN_SPACE_CLINT1                                                  \\\n\t(BIT_MASK_BCN_SPACE_CLINT1 << BIT_SHIFT_BCN_SPACE_CLINT1)\n#define BIT_CLEAR_BCN_SPACE_CLINT1(x) ((x) & (~BITS_BCN_SPACE_CLINT1))\n#define BIT_GET_BCN_SPACE_CLINT1(x)                                            \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT1) & BIT_MASK_BCN_SPACE_CLINT1)\n#define BIT_SET_BCN_SPACE_CLINT1(x, v)                                         \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT1(x) | BIT_BCN_SPACE_CLINT1(v))\n\n/* 2 REG_MBSSID_BCN_SPACE3\t\t\t(Offset 0x05BC) */\n\n#define BIT_SHIFT_SUB_BCN_SPACE 16\n#define BIT_MASK_SUB_BCN_SPACE 0xff\n#define BIT_SUB_BCN_SPACE(x)                                                   \\\n\t(((x) & BIT_MASK_SUB_BCN_SPACE) << BIT_SHIFT_SUB_BCN_SPACE)\n#define BITS_SUB_BCN_SPACE (BIT_MASK_SUB_BCN_SPACE << BIT_SHIFT_SUB_BCN_SPACE)\n#define BIT_CLEAR_SUB_BCN_SPACE(x) ((x) & (~BITS_SUB_BCN_SPACE))\n#define BIT_GET_SUB_BCN_SPACE(x)                                               \\\n\t(((x) >> BIT_SHIFT_SUB_BCN_SPACE) & BIT_MASK_SUB_BCN_SPACE)\n#define BIT_SET_SUB_BCN_SPACE(x, v)                                            \\\n\t(BIT_CLEAR_SUB_BCN_SPACE(x) | BIT_SUB_BCN_SPACE(v))\n\n#define BIT_SHIFT_BCN_SPACE_CLINT3 0\n#define BIT_MASK_BCN_SPACE_CLINT3 0xfff\n#define BIT_BCN_SPACE_CLINT3(x)                                                \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT3) << BIT_SHIFT_BCN_SPACE_CLINT3)\n#define BITS_BCN_SPACE_CLINT3                                                  \\\n\t(BIT_MASK_BCN_SPACE_CLINT3 << BIT_SHIFT_BCN_SPACE_CLINT3)\n#define BIT_CLEAR_BCN_SPACE_CLINT3(x) ((x) & (~BITS_BCN_SPACE_CLINT3))\n#define BIT_GET_BCN_SPACE_CLINT3(x)                                            \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT3) & BIT_MASK_BCN_SPACE_CLINT3)\n#define BIT_SET_BCN_SPACE_CLINT3(x, v)                                         \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT3(x) | BIT_BCN_SPACE_CLINT3(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ACMHWCTRL\t\t\t\t(Offset 0x05C0) */\n\n#define BIT_BEQ_ACM_STATUS BIT(7)\n#define BIT_VIQ_ACM_STATUS BIT(6)\n#define BIT_VOQ_ACM_STATUS BIT(5)\n#define BIT_BEQ_ACM_EN BIT(3)\n#define BIT_VIQ_ACM_EN BIT(2)\n#define BIT_VOQ_ACM_EN BIT(1)\n#define BIT_ACMHWEN BIT(0)\n\n/* 2 REG_ACMRSTCTRL\t\t\t\t(Offset 0x05C1) */\n\n#define BIT_BE_ACM_RESET_USED_TIME BIT(2)\n#define BIT_VI_ACM_RESET_USED_TIME BIT(1)\n#define BIT_VO_ACM_RESET_USED_TIME BIT(0)\n\n/* 2 REG_ACMAVG\t\t\t\t(Offset 0x05C2) */\n\n#define BIT_SHIFT_AVGPERIOD 0\n#define BIT_MASK_AVGPERIOD 0xffff\n#define BIT_AVGPERIOD(x) (((x) & BIT_MASK_AVGPERIOD) << BIT_SHIFT_AVGPERIOD)\n#define BITS_AVGPERIOD (BIT_MASK_AVGPERIOD << BIT_SHIFT_AVGPERIOD)\n#define BIT_CLEAR_AVGPERIOD(x) ((x) & (~BITS_AVGPERIOD))\n#define BIT_GET_AVGPERIOD(x) (((x) >> BIT_SHIFT_AVGPERIOD) & BIT_MASK_AVGPERIOD)\n#define BIT_SET_AVGPERIOD(x, v) (BIT_CLEAR_AVGPERIOD(x) | BIT_AVGPERIOD(v))\n\n/* 2 REG_VO_ADMTIME\t\t\t\t(Offset 0x05C4) */\n\n#define BIT_SHIFT_VO_ADMITTED_TIME 0\n#define BIT_MASK_VO_ADMITTED_TIME 0xffff\n#define BIT_VO_ADMITTED_TIME(x)                                                \\\n\t(((x) & BIT_MASK_VO_ADMITTED_TIME) << BIT_SHIFT_VO_ADMITTED_TIME)\n#define BITS_VO_ADMITTED_TIME                                                  \\\n\t(BIT_MASK_VO_ADMITTED_TIME << BIT_SHIFT_VO_ADMITTED_TIME)\n#define BIT_CLEAR_VO_ADMITTED_TIME(x) ((x) & (~BITS_VO_ADMITTED_TIME))\n#define BIT_GET_VO_ADMITTED_TIME(x)                                            \\\n\t(((x) >> BIT_SHIFT_VO_ADMITTED_TIME) & BIT_MASK_VO_ADMITTED_TIME)\n#define BIT_SET_VO_ADMITTED_TIME(x, v)                                         \\\n\t(BIT_CLEAR_VO_ADMITTED_TIME(x) | BIT_VO_ADMITTED_TIME(v))\n\n/* 2 REG_VI_ADMTIME\t\t\t\t(Offset 0x05C6) */\n\n#define BIT_SHIFT_VI_ADMITTED_TIME 0\n#define BIT_MASK_VI_ADMITTED_TIME 0xffff\n#define BIT_VI_ADMITTED_TIME(x)                                                \\\n\t(((x) & BIT_MASK_VI_ADMITTED_TIME) << BIT_SHIFT_VI_ADMITTED_TIME)\n#define BITS_VI_ADMITTED_TIME                                                  \\\n\t(BIT_MASK_VI_ADMITTED_TIME << BIT_SHIFT_VI_ADMITTED_TIME)\n#define BIT_CLEAR_VI_ADMITTED_TIME(x) ((x) & (~BITS_VI_ADMITTED_TIME))\n#define BIT_GET_VI_ADMITTED_TIME(x)                                            \\\n\t(((x) >> BIT_SHIFT_VI_ADMITTED_TIME) & BIT_MASK_VI_ADMITTED_TIME)\n#define BIT_SET_VI_ADMITTED_TIME(x, v)                                         \\\n\t(BIT_CLEAR_VI_ADMITTED_TIME(x) | BIT_VI_ADMITTED_TIME(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_BE_ADMTIME\t\t\t\t(Offset 0x05C8) */\n\n#define BIT_PRETX_ERRHDL_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_BE_ADMTIME\t\t\t\t(Offset 0x05C8) */\n\n#define BIT_CHANGE_POW_BCN_AREA BIT(9)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_BE_ADMTIME\t\t\t\t(Offset 0x05C8) */\n\n#define BIT_DIS_NDPA_NAV_CHK BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BE_ADMTIME\t\t\t\t(Offset 0x05C8) */\n\n#define BIT_SHIFT_BE_ADMITTED_TIME 0\n#define BIT_MASK_BE_ADMITTED_TIME 0xffff\n#define BIT_BE_ADMITTED_TIME(x)                                                \\\n\t(((x) & BIT_MASK_BE_ADMITTED_TIME) << BIT_SHIFT_BE_ADMITTED_TIME)\n#define BITS_BE_ADMITTED_TIME                                                  \\\n\t(BIT_MASK_BE_ADMITTED_TIME << BIT_SHIFT_BE_ADMITTED_TIME)\n#define BIT_CLEAR_BE_ADMITTED_TIME(x) ((x) & (~BITS_BE_ADMITTED_TIME))\n#define BIT_GET_BE_ADMITTED_TIME(x)                                            \\\n\t(((x) >> BIT_SHIFT_BE_ADMITTED_TIME) & BIT_MASK_BE_ADMITTED_TIME)\n#define BIT_SET_BE_ADMITTED_TIME(x, v)                                         \\\n\t(BIT_CLEAR_BE_ADMITTED_TIME(x) | BIT_BE_ADMITTED_TIME(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_BE_ADMTIME\t\t\t\t(Offset 0x05C8) */\n\n#define BIT_SHIFT_MHDR_NAV_OFFSET 0\n#define BIT_MASK_MHDR_NAV_OFFSET 0xff\n#define BIT_MHDR_NAV_OFFSET(x)                                                 \\\n\t(((x) & BIT_MASK_MHDR_NAV_OFFSET) << BIT_SHIFT_MHDR_NAV_OFFSET)\n#define BITS_MHDR_NAV_OFFSET                                                   \\\n\t(BIT_MASK_MHDR_NAV_OFFSET << BIT_SHIFT_MHDR_NAV_OFFSET)\n#define BIT_CLEAR_MHDR_NAV_OFFSET(x) ((x) & (~BITS_MHDR_NAV_OFFSET))\n#define BIT_GET_MHDR_NAV_OFFSET(x)                                             \\\n\t(((x) >> BIT_SHIFT_MHDR_NAV_OFFSET) & BIT_MASK_MHDR_NAV_OFFSET)\n#define BIT_SET_MHDR_NAV_OFFSET(x, v)                                          \\\n\t(BIT_CLEAR_MHDR_NAV_OFFSET(x) | BIT_MHDR_NAV_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MAC_HEADER_NAV_OFFSET\t\t(Offset 0x05CA) */\n\n#define BIT_SHIFT_MAC_HEADER_NAV_OFFSET 0\n#define BIT_MASK_MAC_HEADER_NAV_OFFSET 0xff\n#define BIT_MAC_HEADER_NAV_OFFSET(x)                                           \\\n\t(((x) & BIT_MASK_MAC_HEADER_NAV_OFFSET)                                \\\n\t << BIT_SHIFT_MAC_HEADER_NAV_OFFSET)\n#define BITS_MAC_HEADER_NAV_OFFSET                                             \\\n\t(BIT_MASK_MAC_HEADER_NAV_OFFSET << BIT_SHIFT_MAC_HEADER_NAV_OFFSET)\n#define BIT_CLEAR_MAC_HEADER_NAV_OFFSET(x) ((x) & (~BITS_MAC_HEADER_NAV_OFFSET))\n#define BIT_GET_MAC_HEADER_NAV_OFFSET(x)                                       \\\n\t(((x) >> BIT_SHIFT_MAC_HEADER_NAV_OFFSET) &                            \\\n\t BIT_MASK_MAC_HEADER_NAV_OFFSET)\n#define BIT_SET_MAC_HEADER_NAV_OFFSET(x, v)                                    \\\n\t(BIT_CLEAR_MAC_HEADER_NAV_OFFSET(x) | BIT_MAC_HEADER_NAV_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DIS_NDPA_NAV_CHECK\t\t\t(Offset 0x05CB) */\n\n#define BIT_CHG_POWER_BCN_AREA_V1 BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DIS_NDPA_NAV_CHECK\t\t\t(Offset 0x05CB) */\n\n#define BIT_DIS_NDPA_NAV_CHECK BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_EDCA_RANDOM_GEN\t\t\t(Offset 0x05CC) */\n\n#define BIT_SHIFT_RANDOM_GEN 0\n#define BIT_MASK_RANDOM_GEN 0xffffff\n#define BIT_RANDOM_GEN(x) (((x) & BIT_MASK_RANDOM_GEN) << BIT_SHIFT_RANDOM_GEN)\n#define BITS_RANDOM_GEN (BIT_MASK_RANDOM_GEN << BIT_SHIFT_RANDOM_GEN)\n#define BIT_CLEAR_RANDOM_GEN(x) ((x) & (~BITS_RANDOM_GEN))\n#define BIT_GET_RANDOM_GEN(x)                                                  \\\n\t(((x) >> BIT_SHIFT_RANDOM_GEN) & BIT_MASK_RANDOM_GEN)\n#define BIT_SET_RANDOM_GEN(x, v) (BIT_CLEAR_RANDOM_GEN(x) | BIT_RANDOM_GEN(v))\n\n#define BIT_SHIFT_TXCMD_SEG_SEL 0\n#define BIT_MASK_TXCMD_SEG_SEL 0xf\n#define BIT_TXCMD_SEG_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_TXCMD_SEG_SEL) << BIT_SHIFT_TXCMD_SEG_SEL)\n#define BITS_TXCMD_SEG_SEL (BIT_MASK_TXCMD_SEG_SEL << BIT_SHIFT_TXCMD_SEG_SEL)\n#define BIT_CLEAR_TXCMD_SEG_SEL(x) ((x) & (~BITS_TXCMD_SEG_SEL))\n#define BIT_GET_TXCMD_SEG_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXCMD_SEG_SEL) & BIT_MASK_TXCMD_SEG_SEL)\n#define BIT_SET_TXCMD_SEG_SEL(x, v)                                            \\\n\t(BIT_CLEAR_TXCMD_SEG_SEL(x) | BIT_TXCMD_SEG_SEL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TXCMD_NOA_SEL\t\t\t(Offset 0x05CF) */\n\n#define BIT_SHIFT_EVTQ_EARLY 5\n#define BIT_MASK_EVTQ_EARLY 0x7\n#define BIT_EVTQ_EARLY(x) (((x) & BIT_MASK_EVTQ_EARLY) << BIT_SHIFT_EVTQ_EARLY)\n#define BITS_EVTQ_EARLY (BIT_MASK_EVTQ_EARLY << BIT_SHIFT_EVTQ_EARLY)\n#define BIT_CLEAR_EVTQ_EARLY(x) ((x) & (~BITS_EVTQ_EARLY))\n#define BIT_GET_EVTQ_EARLY(x)                                                  \\\n\t(((x) >> BIT_SHIFT_EVTQ_EARLY) & BIT_MASK_EVTQ_EARLY)\n#define BIT_SET_EVTQ_EARLY(x, v) (BIT_CLEAR_EVTQ_EARLY(x) | BIT_EVTQ_EARLY(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TXCMD_NOA_SEL\t\t\t(Offset 0x05CF) */\n\n#define BIT_NOA_SEL BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXCMD_NOA_SEL\t\t\t(Offset 0x05CF) */\n\n#define BIT_SHIFT_NOA_SEL_V2 4\n#define BIT_MASK_NOA_SEL_V2 0x7\n#define BIT_NOA_SEL_V2(x) (((x) & BIT_MASK_NOA_SEL_V2) << BIT_SHIFT_NOA_SEL_V2)\n#define BITS_NOA_SEL_V2 (BIT_MASK_NOA_SEL_V2 << BIT_SHIFT_NOA_SEL_V2)\n#define BIT_CLEAR_NOA_SEL_V2(x) ((x) & (~BITS_NOA_SEL_V2))\n#define BIT_GET_NOA_SEL_V2(x)                                                  \\\n\t(((x) >> BIT_SHIFT_NOA_SEL_V2) & BIT_MASK_NOA_SEL_V2)\n#define BIT_SET_NOA_SEL_V2(x, v) (BIT_CLEAR_NOA_SEL_V2(x) | BIT_NOA_SEL_V2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_BCNERR_CFG\t\t\t\t(Offset 0x05D0) */\n\n#define BIT_BCNERR_CNT_EN BIT(20)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_32K_CLK_SEL\t\t\t\t(Offset 0x05D0) */\n\n#define BIT_R_BCNERR_CNT_EN BIT(20)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DRVERLYINT2\t\t\t\t(Offset 0x05D0) */\n\n#define BIT_SHIFT_TSF_DIFF_P1P2 16\n#define BIT_MASK_TSF_DIFF_P1P2 0xffff\n#define BIT_TSF_DIFF_P1P2(x)                                                   \\\n\t(((x) & BIT_MASK_TSF_DIFF_P1P2) << BIT_SHIFT_TSF_DIFF_P1P2)\n#define BITS_TSF_DIFF_P1P2 (BIT_MASK_TSF_DIFF_P1P2 << BIT_SHIFT_TSF_DIFF_P1P2)\n#define BIT_CLEAR_TSF_DIFF_P1P2(x) ((x) & (~BITS_TSF_DIFF_P1P2))\n#define BIT_GET_TSF_DIFF_P1P2(x)                                               \\\n\t(((x) >> BIT_SHIFT_TSF_DIFF_P1P2) & BIT_MASK_TSF_DIFF_P1P2)\n#define BIT_SET_TSF_DIFF_P1P2(x, v)                                            \\\n\t(BIT_CLEAR_TSF_DIFF_P1P2(x) | BIT_TSF_DIFF_P1P2(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_BCNERR_CFG\t\t\t\t(Offset 0x05D0) */\n\n#define BIT_SHIFT_BCNERR_PORT_SEL_V2 16\n#define BIT_MASK_BCNERR_PORT_SEL_V2 0x7\n#define BIT_BCNERR_PORT_SEL_V2(x)                                              \\\n\t(((x) & BIT_MASK_BCNERR_PORT_SEL_V2) << BIT_SHIFT_BCNERR_PORT_SEL_V2)\n#define BITS_BCNERR_PORT_SEL_V2                                                \\\n\t(BIT_MASK_BCNERR_PORT_SEL_V2 << BIT_SHIFT_BCNERR_PORT_SEL_V2)\n#define BIT_CLEAR_BCNERR_PORT_SEL_V2(x) ((x) & (~BITS_BCNERR_PORT_SEL_V2))\n#define BIT_GET_BCNERR_PORT_SEL_V2(x)                                          \\\n\t(((x) >> BIT_SHIFT_BCNERR_PORT_SEL_V2) & BIT_MASK_BCNERR_PORT_SEL_V2)\n#define BIT_SET_BCNERR_PORT_SEL_V2(x, v)                                       \\\n\t(BIT_CLEAR_BCNERR_PORT_SEL_V2(x) | BIT_BCNERR_PORT_SEL_V2(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_32K_CLK_SEL\t\t\t\t(Offset 0x05D0) */\n\n#define BIT_SHIFT_R_BCNERR_PORT_SEL 16\n#define BIT_MASK_R_BCNERR_PORT_SEL 0x7\n#define BIT_R_BCNERR_PORT_SEL(x)                                               \\\n\t(((x) & BIT_MASK_R_BCNERR_PORT_SEL) << BIT_SHIFT_R_BCNERR_PORT_SEL)\n#define BITS_R_BCNERR_PORT_SEL                                                 \\\n\t(BIT_MASK_R_BCNERR_PORT_SEL << BIT_SHIFT_R_BCNERR_PORT_SEL)\n#define BIT_CLEAR_R_BCNERR_PORT_SEL(x) ((x) & (~BITS_R_BCNERR_PORT_SEL))\n#define BIT_GET_R_BCNERR_PORT_SEL(x)                                           \\\n\t(((x) >> BIT_SHIFT_R_BCNERR_PORT_SEL) & BIT_MASK_R_BCNERR_PORT_SEL)\n#define BIT_SET_R_BCNERR_PORT_SEL(x, v)                                        \\\n\t(BIT_CLEAR_R_BCNERR_PORT_SEL(x) | BIT_R_BCNERR_PORT_SEL(v))\n\n#define BIT_SHIFT_R_TXPAUSE1 8\n#define BIT_MASK_R_TXPAUSE1 0xff\n#define BIT_R_TXPAUSE1(x) (((x) & BIT_MASK_R_TXPAUSE1) << BIT_SHIFT_R_TXPAUSE1)\n#define BITS_R_TXPAUSE1 (BIT_MASK_R_TXPAUSE1 << BIT_SHIFT_R_TXPAUSE1)\n#define BIT_CLEAR_R_TXPAUSE1(x) ((x) & (~BITS_R_TXPAUSE1))\n#define BIT_GET_R_TXPAUSE1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_R_TXPAUSE1) & BIT_MASK_R_TXPAUSE1)\n#define BIT_SET_R_TXPAUSE1(x, v) (BIT_CLEAR_R_TXPAUSE1(x) | BIT_R_TXPAUSE1(v))\n\n#define BIT_SLEEP_32K_EN_V1 BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_DRVERLYINT2\t\t\t\t(Offset 0x05D0) */\n\n#define BIT_SHIFT_DRVERLYITV2 0\n#define BIT_MASK_DRVERLYITV2 0xff\n#define BIT_DRVERLYITV2(x)                                                     \\\n\t(((x) & BIT_MASK_DRVERLYITV2) << BIT_SHIFT_DRVERLYITV2)\n#define BITS_DRVERLYITV2 (BIT_MASK_DRVERLYITV2 << BIT_SHIFT_DRVERLYITV2)\n#define BIT_CLEAR_DRVERLYITV2(x) ((x) & (~BITS_DRVERLYITV2))\n#define BIT_GET_DRVERLYITV2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DRVERLYITV2) & BIT_MASK_DRVERLYITV2)\n#define BIT_SET_DRVERLYITV2(x, v)                                              \\\n\t(BIT_CLEAR_DRVERLYITV2(x) | BIT_DRVERLYITV2(v))\n\n/* 2 REG_NAN_SETTING\t\t\t\t(Offset 0x05D4) */\n\n#define BIT_EN_MULTI_BCN BIT(31)\n#define BIT_ENP2P_DW_AREA BIT(30)\n\n#define BIT_SHIFT_TBTT_PROHIBIT_HOLD_P2 18\n#define BIT_MASK_TBTT_PROHIBIT_HOLD_P2 0xfff\n#define BIT_TBTT_PROHIBIT_HOLD_P2(x)                                           \\\n\t(((x) & BIT_MASK_TBTT_PROHIBIT_HOLD_P2)                                \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_HOLD_P2)\n#define BITS_TBTT_PROHIBIT_HOLD_P2                                             \\\n\t(BIT_MASK_TBTT_PROHIBIT_HOLD_P2 << BIT_SHIFT_TBTT_PROHIBIT_HOLD_P2)\n#define BIT_CLEAR_TBTT_PROHIBIT_HOLD_P2(x) ((x) & (~BITS_TBTT_PROHIBIT_HOLD_P2))\n#define BIT_GET_TBTT_PROHIBIT_HOLD_P2(x)                                       \\\n\t(((x) >> BIT_SHIFT_TBTT_PROHIBIT_HOLD_P2) &                            \\\n\t BIT_MASK_TBTT_PROHIBIT_HOLD_P2)\n#define BIT_SET_TBTT_PROHIBIT_HOLD_P2(x, v)                                    \\\n\t(BIT_CLEAR_TBTT_PROHIBIT_HOLD_P2(x) | BIT_TBTT_PROHIBIT_HOLD_P2(v))\n\n#define BIT_SHIFT_BCN_PORT_PRI 16\n#define BIT_MASK_BCN_PORT_PRI 0x3\n#define BIT_BCN_PORT_PRI(x)                                                    \\\n\t(((x) & BIT_MASK_BCN_PORT_PRI) << BIT_SHIFT_BCN_PORT_PRI)\n#define BITS_BCN_PORT_PRI (BIT_MASK_BCN_PORT_PRI << BIT_SHIFT_BCN_PORT_PRI)\n#define BIT_CLEAR_BCN_PORT_PRI(x) ((x) & (~BITS_BCN_PORT_PRI))\n#define BIT_GET_BCN_PORT_PRI(x)                                                \\\n\t(((x) >> BIT_SHIFT_BCN_PORT_PRI) & BIT_MASK_BCN_PORT_PRI)\n#define BIT_SET_BCN_PORT_PRI(x, v)                                             \\\n\t(BIT_CLEAR_BCN_PORT_PRI(x) | BIT_BCN_PORT_PRI(v))\n\n#define BIT_SHIFT_DRVERLYITV1 8\n#define BIT_MASK_DRVERLYITV1 0xff\n#define BIT_DRVERLYITV1(x)                                                     \\\n\t(((x) & BIT_MASK_DRVERLYITV1) << BIT_SHIFT_DRVERLYITV1)\n#define BITS_DRVERLYITV1 (BIT_MASK_DRVERLYITV1 << BIT_SHIFT_DRVERLYITV1)\n#define BIT_CLEAR_DRVERLYITV1(x) ((x) & (~BITS_DRVERLYITV1))\n#define BIT_GET_DRVERLYITV1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DRVERLYITV1) & BIT_MASK_DRVERLYITV1)\n#define BIT_SET_DRVERLYITV1(x, v)                                              \\\n\t(BIT_CLEAR_DRVERLYITV1(x) | BIT_DRVERLYITV1(v))\n\n#define BIT_DIS_RX_BSSID_FIT2 BIT(6)\n#define BIT_DIS_TSF2_UDT BIT(4)\n#define BIT_EN_BCN2_FUNCTION BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_BCN_ELY_ADJ\t\t\t\t(Offset 0x05D4) */\n\n#define BIT_SHIFT_BCN_ELY_ADJ 0\n#define BIT_MASK_BCN_ELY_ADJ 0xffff\n#define BIT_BCN_ELY_ADJ(x)                                                     \\\n\t(((x) & BIT_MASK_BCN_ELY_ADJ) << BIT_SHIFT_BCN_ELY_ADJ)\n#define BITS_BCN_ELY_ADJ (BIT_MASK_BCN_ELY_ADJ << BIT_SHIFT_BCN_ELY_ADJ)\n#define BIT_CLEAR_BCN_ELY_ADJ(x) ((x) & (~BITS_BCN_ELY_ADJ))\n#define BIT_GET_BCN_ELY_ADJ(x)                                                 \\\n\t(((x) >> BIT_SHIFT_BCN_ELY_ADJ) & BIT_MASK_BCN_ELY_ADJ)\n#define BIT_SET_BCN_ELY_ADJ(x, v)                                              \\\n\t(BIT_CLEAR_BCN_ELY_ADJ(x) | BIT_BCN_ELY_ADJ(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_EARLYINT_ADJUST\t\t\t(Offset 0x05D4) */\n\n#define BIT_SHIFT_R_ERLYINTADJ 0\n#define BIT_MASK_R_ERLYINTADJ 0xffff\n#define BIT_R_ERLYINTADJ(x)                                                    \\\n\t(((x) & BIT_MASK_R_ERLYINTADJ) << BIT_SHIFT_R_ERLYINTADJ)\n#define BITS_R_ERLYINTADJ (BIT_MASK_R_ERLYINTADJ << BIT_SHIFT_R_ERLYINTADJ)\n#define BIT_CLEAR_R_ERLYINTADJ(x) ((x) & (~BITS_R_ERLYINTADJ))\n#define BIT_GET_R_ERLYINTADJ(x)                                                \\\n\t(((x) >> BIT_SHIFT_R_ERLYINTADJ) & BIT_MASK_R_ERLYINTADJ)\n#define BIT_SET_R_ERLYINTADJ(x, v)                                             \\\n\t(BIT_CLEAR_R_ERLYINTADJ(x) | BIT_R_ERLYINTADJ(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_NAN_BCNSPACE\t\t\t(Offset 0x05D8) */\n\n#define BIT_SHIFT_BCN_SPACE4 16\n#define BIT_MASK_BCN_SPACE4 0xffff\n#define BIT_BCN_SPACE4(x) (((x) & BIT_MASK_BCN_SPACE4) << BIT_SHIFT_BCN_SPACE4)\n#define BITS_BCN_SPACE4 (BIT_MASK_BCN_SPACE4 << BIT_SHIFT_BCN_SPACE4)\n#define BIT_CLEAR_BCN_SPACE4(x) ((x) & (~BITS_BCN_SPACE4))\n#define BIT_GET_BCN_SPACE4(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE4) & BIT_MASK_BCN_SPACE4)\n#define BIT_SET_BCN_SPACE4(x, v) (BIT_CLEAR_BCN_SPACE4(x) | BIT_BCN_SPACE4(v))\n\n#define BIT_SHIFT_BCN_SPACE3 0\n#define BIT_MASK_BCN_SPACE3 0xffff\n#define BIT_BCN_SPACE3(x) (((x) & BIT_MASK_BCN_SPACE3) << BIT_SHIFT_BCN_SPACE3)\n#define BITS_BCN_SPACE3 (BIT_MASK_BCN_SPACE3 << BIT_SHIFT_BCN_SPACE3)\n#define BIT_CLEAR_BCN_SPACE3(x) ((x) & (~BITS_BCN_SPACE3))\n#define BIT_GET_BCN_SPACE3(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE3) & BIT_MASK_BCN_SPACE3)\n#define BIT_SET_BCN_SPACE3(x, v) (BIT_CLEAR_BCN_SPACE3(x) | BIT_BCN_SPACE3(v))\n\n/* 2 REG_NAN_SETTING1\t\t\t(Offset 0x05DC) */\n\n#define BIT_SHIFT_SYNCBCN_RXNUM 27\n#define BIT_MASK_SYNCBCN_RXNUM 0x1f\n#define BIT_SYNCBCN_RXNUM(x)                                                   \\\n\t(((x) & BIT_MASK_SYNCBCN_RXNUM) << BIT_SHIFT_SYNCBCN_RXNUM)\n#define BITS_SYNCBCN_RXNUM (BIT_MASK_SYNCBCN_RXNUM << BIT_SHIFT_SYNCBCN_RXNUM)\n#define BIT_CLEAR_SYNCBCN_RXNUM(x) ((x) & (~BITS_SYNCBCN_RXNUM))\n#define BIT_GET_SYNCBCN_RXNUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_SYNCBCN_RXNUM) & BIT_MASK_SYNCBCN_RXNUM)\n#define BIT_SET_SYNCBCN_RXNUM(x, v)                                            \\\n\t(BIT_CLEAR_SYNCBCN_RXNUM(x) | BIT_SYNCBCN_RXNUM(v))\n\n#define BIT_DW_END_EARLY BIT(26)\n\n#define BIT_SHIFT_NAN_ROLE 24\n#define BIT_MASK_NAN_ROLE 0x3\n#define BIT_NAN_ROLE(x) (((x) & BIT_MASK_NAN_ROLE) << BIT_SHIFT_NAN_ROLE)\n#define BITS_NAN_ROLE (BIT_MASK_NAN_ROLE << BIT_SHIFT_NAN_ROLE)\n#define BIT_CLEAR_NAN_ROLE(x) ((x) & (~BITS_NAN_ROLE))\n#define BIT_GET_NAN_ROLE(x) (((x) >> BIT_SHIFT_NAN_ROLE) & BIT_MASK_NAN_ROLE)\n#define BIT_SET_NAN_ROLE(x, v) (BIT_CLEAR_NAN_ROLE(x) | BIT_NAN_ROLE(v))\n\n#define BIT_SHIFT_MSLOT_EVTQ 16\n#define BIT_MASK_MSLOT_EVTQ 0xff\n#define BIT_MSLOT_EVTQ(x) (((x) & BIT_MASK_MSLOT_EVTQ) << BIT_SHIFT_MSLOT_EVTQ)\n#define BITS_MSLOT_EVTQ (BIT_MASK_MSLOT_EVTQ << BIT_SHIFT_MSLOT_EVTQ)\n#define BIT_CLEAR_MSLOT_EVTQ(x) ((x) & (~BITS_MSLOT_EVTQ))\n#define BIT_GET_MSLOT_EVTQ(x)                                                  \\\n\t(((x) >> BIT_SHIFT_MSLOT_EVTQ) & BIT_MASK_MSLOT_EVTQ)\n#define BIT_SET_MSLOT_EVTQ(x, v) (BIT_CLEAR_MSLOT_EVTQ(x) | BIT_MSLOT_EVTQ(v))\n\n#define BIT_SHIFT_MDW_EVTQ 8\n#define BIT_MASK_MDW_EVTQ 0xff\n#define BIT_MDW_EVTQ(x) (((x) & BIT_MASK_MDW_EVTQ) << BIT_SHIFT_MDW_EVTQ)\n#define BITS_MDW_EVTQ (BIT_MASK_MDW_EVTQ << BIT_SHIFT_MDW_EVTQ)\n#define BIT_CLEAR_MDW_EVTQ(x) ((x) & (~BITS_MDW_EVTQ))\n#define BIT_GET_MDW_EVTQ(x) (((x) >> BIT_SHIFT_MDW_EVTQ) & BIT_MASK_MDW_EVTQ)\n#define BIT_SET_MDW_EVTQ(x, v) (BIT_CLEAR_MDW_EVTQ(x) | BIT_MDW_EVTQ(v))\n\n#define BIT_SHIFT_HC 0\n#define BIT_MASK_HC 0xff\n#define BIT_HC(x) (((x) & BIT_MASK_HC) << BIT_SHIFT_HC)\n#define BITS_HC (BIT_MASK_HC << BIT_SHIFT_HC)\n#define BIT_CLEAR_HC(x) ((x) & (~BITS_HC))\n#define BIT_GET_HC(x) (((x) >> BIT_SHIFT_HC) & BIT_MASK_HC)\n#define BIT_SET_HC(x, v) (BIT_CLEAR_HC(x) | BIT_HC(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_NOA_PARAM\t\t\t\t(Offset 0x05E0) */\n\n#define BIT_SHIFT_NOA_COUNT (96 & CPU_OPT_WIDTH)\n#define BIT_MASK_NOA_COUNT 0xff\n#define BIT_NOA_COUNT(x) (((x) & BIT_MASK_NOA_COUNT) << BIT_SHIFT_NOA_COUNT)\n#define BITS_NOA_COUNT (BIT_MASK_NOA_COUNT << BIT_SHIFT_NOA_COUNT)\n#define BIT_CLEAR_NOA_COUNT(x) ((x) & (~BITS_NOA_COUNT))\n#define BIT_GET_NOA_COUNT(x) (((x) >> BIT_SHIFT_NOA_COUNT) & BIT_MASK_NOA_COUNT)\n#define BIT_SET_NOA_COUNT(x, v) (BIT_CLEAR_NOA_COUNT(x) | BIT_NOA_COUNT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_NOA_PARAM\t\t\t\t(Offset 0x05E0) */\n\n#define BIT_SHIFT_NOA_DURATION 0\n#define BIT_MASK_NOA_DURATION 0xffffffffL\n#define BIT_NOA_DURATION(x)                                                    \\\n\t(((x) & BIT_MASK_NOA_DURATION) << BIT_SHIFT_NOA_DURATION)\n#define BITS_NOA_DURATION (BIT_MASK_NOA_DURATION << BIT_SHIFT_NOA_DURATION)\n#define BIT_CLEAR_NOA_DURATION(x) ((x) & (~BITS_NOA_DURATION))\n#define BIT_GET_NOA_DURATION(x)                                                \\\n\t(((x) >> BIT_SHIFT_NOA_DURATION) & BIT_MASK_NOA_DURATION)\n#define BIT_SET_NOA_DURATION(x, v)                                             \\\n\t(BIT_CLEAR_NOA_DURATION(x) | BIT_NOA_DURATION(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_NOA_PARAM\t\t\t\t(Offset 0x05E0) */\n\n#define BIT_SHIFT_NOA_DURATION_V1 0\n#define BIT_MASK_NOA_DURATION_V1 0xffffffffL\n#define BIT_NOA_DURATION_V1(x)                                                 \\\n\t(((x) & BIT_MASK_NOA_DURATION_V1) << BIT_SHIFT_NOA_DURATION_V1)\n#define BITS_NOA_DURATION_V1                                                   \\\n\t(BIT_MASK_NOA_DURATION_V1 << BIT_SHIFT_NOA_DURATION_V1)\n#define BIT_CLEAR_NOA_DURATION_V1(x) ((x) & (~BITS_NOA_DURATION_V1))\n#define BIT_GET_NOA_DURATION_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_NOA_DURATION_V1) & BIT_MASK_NOA_DURATION_V1)\n#define BIT_SET_NOA_DURATION_V1(x, v)                                          \\\n\t(BIT_CLEAR_NOA_DURATION_V1(x) | BIT_NOA_DURATION_V1(v))\n\n/* 2 REG_NOA_PARAM_1\t\t\t\t(Offset 0x05E4) */\n\n#define BIT_SHIFT_NOA_INTERVAL_V1 0\n#define BIT_MASK_NOA_INTERVAL_V1 0xffffffffL\n#define BIT_NOA_INTERVAL_V1(x)                                                 \\\n\t(((x) & BIT_MASK_NOA_INTERVAL_V1) << BIT_SHIFT_NOA_INTERVAL_V1)\n#define BITS_NOA_INTERVAL_V1                                                   \\\n\t(BIT_MASK_NOA_INTERVAL_V1 << BIT_SHIFT_NOA_INTERVAL_V1)\n#define BIT_CLEAR_NOA_INTERVAL_V1(x) ((x) & (~BITS_NOA_INTERVAL_V1))\n#define BIT_GET_NOA_INTERVAL_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_NOA_INTERVAL_V1) & BIT_MASK_NOA_INTERVAL_V1)\n#define BIT_SET_NOA_INTERVAL_V1(x, v)                                          \\\n\t(BIT_CLEAR_NOA_INTERVAL_V1(x) | BIT_NOA_INTERVAL_V1(v))\n\n/* 2 REG_NOA_PARAM_2\t\t\t\t(Offset 0x05E8) */\n\n#define BIT_SHIFT_NOA_START_TIME_V1 0\n#define BIT_MASK_NOA_START_TIME_V1 0xffffffffL\n#define BIT_NOA_START_TIME_V1(x)                                               \\\n\t(((x) & BIT_MASK_NOA_START_TIME_V1) << BIT_SHIFT_NOA_START_TIME_V1)\n#define BITS_NOA_START_TIME_V1                                                 \\\n\t(BIT_MASK_NOA_START_TIME_V1 << BIT_SHIFT_NOA_START_TIME_V1)\n#define BIT_CLEAR_NOA_START_TIME_V1(x) ((x) & (~BITS_NOA_START_TIME_V1))\n#define BIT_GET_NOA_START_TIME_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_NOA_START_TIME_V1) & BIT_MASK_NOA_START_TIME_V1)\n#define BIT_SET_NOA_START_TIME_V1(x, v)                                        \\\n\t(BIT_CLEAR_NOA_START_TIME_V1(x) | BIT_NOA_START_TIME_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MU_DBG_INFO\t\t\t\t(Offset 0x05E8) */\n\n#define BIT_SHIFT_MU_DBG_INFO 0\n#define BIT_MASK_MU_DBG_INFO 0xffffffffL\n#define BIT_MU_DBG_INFO(x)                                                     \\\n\t(((x) & BIT_MASK_MU_DBG_INFO) << BIT_SHIFT_MU_DBG_INFO)\n#define BITS_MU_DBG_INFO (BIT_MASK_MU_DBG_INFO << BIT_SHIFT_MU_DBG_INFO)\n#define BIT_CLEAR_MU_DBG_INFO(x) ((x) & (~BITS_MU_DBG_INFO))\n#define BIT_GET_MU_DBG_INFO(x)                                                 \\\n\t(((x) >> BIT_SHIFT_MU_DBG_INFO) & BIT_MASK_MU_DBG_INFO)\n#define BIT_SET_MU_DBG_INFO(x, v)                                              \\\n\t(BIT_CLEAR_MU_DBG_INFO(x) | BIT_MU_DBG_INFO(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_NOA_PARAM_3\t\t\t\t(Offset 0x05EC) */\n\n#define BIT_SHIFT_NOA_COUNT_V3 0\n#define BIT_MASK_NOA_COUNT_V3 0xff\n#define BIT_NOA_COUNT_V3(x)                                                    \\\n\t(((x) & BIT_MASK_NOA_COUNT_V3) << BIT_SHIFT_NOA_COUNT_V3)\n#define BITS_NOA_COUNT_V3 (BIT_MASK_NOA_COUNT_V3 << BIT_SHIFT_NOA_COUNT_V3)\n#define BIT_CLEAR_NOA_COUNT_V3(x) ((x) & (~BITS_NOA_COUNT_V3))\n#define BIT_GET_NOA_COUNT_V3(x)                                                \\\n\t(((x) >> BIT_SHIFT_NOA_COUNT_V3) & BIT_MASK_NOA_COUNT_V3)\n#define BIT_SET_NOA_COUNT_V3(x, v)                                             \\\n\t(BIT_CLEAR_NOA_COUNT_V3(x) | BIT_NOA_COUNT_V3(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_NOA_PARAM_3\t\t\t\t(Offset 0x05EC) */\n\n#define BIT_SHIFT_NOA_COUNT_V1 0\n#define BIT_MASK_NOA_COUNT_V1 0xffffffffL\n#define BIT_NOA_COUNT_V1(x)                                                    \\\n\t(((x) & BIT_MASK_NOA_COUNT_V1) << BIT_SHIFT_NOA_COUNT_V1)\n#define BITS_NOA_COUNT_V1 (BIT_MASK_NOA_COUNT_V1 << BIT_SHIFT_NOA_COUNT_V1)\n#define BIT_CLEAR_NOA_COUNT_V1(x) ((x) & (~BITS_NOA_COUNT_V1))\n#define BIT_GET_NOA_COUNT_V1(x)                                                \\\n\t(((x) >> BIT_SHIFT_NOA_COUNT_V1) & BIT_MASK_NOA_COUNT_V1)\n#define BIT_SET_NOA_COUNT_V1(x, v)                                             \\\n\t(BIT_CLEAR_NOA_COUNT_V1(x) | BIT_NOA_COUNT_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MU_DBG_INFO_1\t\t\t(Offset 0x05EC) */\n\n#define BIT_SHIFT_MU_DBG_INFO_1 0\n#define BIT_MASK_MU_DBG_INFO_1 0xffffffffL\n#define BIT_MU_DBG_INFO_1(x)                                                   \\\n\t(((x) & BIT_MASK_MU_DBG_INFO_1) << BIT_SHIFT_MU_DBG_INFO_1)\n#define BITS_MU_DBG_INFO_1 (BIT_MASK_MU_DBG_INFO_1 << BIT_SHIFT_MU_DBG_INFO_1)\n#define BIT_CLEAR_MU_DBG_INFO_1(x) ((x) & (~BITS_MU_DBG_INFO_1))\n#define BIT_GET_MU_DBG_INFO_1(x)                                               \\\n\t(((x) >> BIT_SHIFT_MU_DBG_INFO_1) & BIT_MASK_MU_DBG_INFO_1)\n#define BIT_SET_MU_DBG_INFO_1(x, v)                                            \\\n\t(BIT_CLEAR_MU_DBG_INFO_1(x) | BIT_MU_DBG_INFO_1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_NOA_SUBIE\t\t\t\t(Offset 0x05ED) */\n\n#define BIT_MORE_NOA_DESC BIT(19)\n#define BIT_NOA_DESC1_VALID BIT(18)\n#define BIT_NOA_DESC0_VALID BIT(17)\n#define BIT_NOA_HEAD_VALID BIT(16)\n#define BIT_NOA_OPP_PS BIT(15)\n\n#define BIT_SHIFT_NOA_CTW 8\n#define BIT_MASK_NOA_CTW 0x7f\n#define BIT_NOA_CTW(x) (((x) & BIT_MASK_NOA_CTW) << BIT_SHIFT_NOA_CTW)\n#define BITS_NOA_CTW (BIT_MASK_NOA_CTW << BIT_SHIFT_NOA_CTW)\n#define BIT_CLEAR_NOA_CTW(x) ((x) & (~BITS_NOA_CTW))\n#define BIT_GET_NOA_CTW(x) (((x) >> BIT_SHIFT_NOA_CTW) & BIT_MASK_NOA_CTW)\n#define BIT_SET_NOA_CTW(x, v) (BIT_CLEAR_NOA_CTW(x) | BIT_NOA_CTW(v))\n\n#define BIT_SHIFT_NOA_INDEX 0\n#define BIT_MASK_NOA_INDEX 0xff\n#define BIT_NOA_INDEX(x) (((x) & BIT_MASK_NOA_INDEX) << BIT_SHIFT_NOA_INDEX)\n#define BITS_NOA_INDEX (BIT_MASK_NOA_INDEX << BIT_SHIFT_NOA_INDEX)\n#define BIT_CLEAR_NOA_INDEX(x) ((x) & (~BITS_NOA_INDEX))\n#define BIT_GET_NOA_INDEX(x) (((x) >> BIT_SHIFT_NOA_INDEX) & BIT_MASK_NOA_INDEX)\n#define BIT_SET_NOA_INDEX(x, v) (BIT_CLEAR_NOA_INDEX(x) | BIT_NOA_INDEX(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2P_RST\t\t\t\t(Offset 0x05F0) */\n\n#define BIT_P2P2_PWR_RST1 BIT(5)\n#define BIT_P2P2_PWR_RST0 BIT(4)\n#define BIT_P2P1_PWR_RST1 BIT(3)\n#define BIT_P2P1_PWR_RST0 BIT(2)\n#define BIT_P2P_PWR_RST1_V1 BIT(1)\n#define BIT_P2P_PWR_RST0_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SCH_DBG_SEL\t\t\t\t(Offset 0x05F0) */\n\n#define BIT_SHIFT_SCH_DBG_SEL 0\n#define BIT_MASK_SCH_DBG_SEL 0xff\n#define BIT_SCH_DBG_SEL(x)                                                     \\\n\t(((x) & BIT_MASK_SCH_DBG_SEL) << BIT_SHIFT_SCH_DBG_SEL)\n#define BITS_SCH_DBG_SEL (BIT_MASK_SCH_DBG_SEL << BIT_SHIFT_SCH_DBG_SEL)\n#define BIT_CLEAR_SCH_DBG_SEL(x) ((x) & (~BITS_SCH_DBG_SEL))\n#define BIT_GET_SCH_DBG_SEL(x)                                                 \\\n\t(((x) >> BIT_SHIFT_SCH_DBG_SEL) & BIT_MASK_SCH_DBG_SEL)\n#define BIT_SET_SCH_DBG_SEL(x, v)                                              \\\n\t(BIT_CLEAR_SCH_DBG_SEL(x) | BIT_SCH_DBG_SEL(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SCHEDULER_RST\t\t\t(Offset 0x05F1) */\n\n#define BIT_MAC_STOP_CPUMGQ BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_SCHEDULER_RST\t\t\t(Offset 0x05F1) */\n\n#define BIT_SYNC_TSF_NOW BIT(2)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SCHEDULER_RST\t\t\t(Offset 0x05F1) */\n\n#define BIT_SYNC_CLI_ONCE_RIGHT_NOW BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SCHEDULER_RST\t\t\t(Offset 0x05F1) */\n\n#define BIT_EN_P2P_CTWINDOW BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SCHEDULER_RST\t\t\t(Offset 0x05F1) */\n\n#define BIT_SYNC_CLI BIT(1)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SCHEDULER_RST\t\t\t(Offset 0x05F1) */\n\n#define BIT_SYNC_CLI_ONCE_BY_TBTT BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SCHEDULER_RST\t\t\t(Offset 0x05F1) */\n\n#define BIT_SCHEDULER_RST_V1 BIT(0)\n#define BIT_EN_P2P_BCNQ_AREA BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MU_DBG_ERR_FLAG\t\t\t(Offset 0x05F2) */\n\n#define BIT_BCN_PORTID_ERR BIT(2)\n\n#define BIT_SHIFT_MU_DBG_ERR_FLAG 0\n#define BIT_MASK_MU_DBG_ERR_FLAG 0x3\n#define BIT_MU_DBG_ERR_FLAG(x)                                                 \\\n\t(((x) & BIT_MASK_MU_DBG_ERR_FLAG) << BIT_SHIFT_MU_DBG_ERR_FLAG)\n#define BITS_MU_DBG_ERR_FLAG                                                   \\\n\t(BIT_MASK_MU_DBG_ERR_FLAG << BIT_SHIFT_MU_DBG_ERR_FLAG)\n#define BIT_CLEAR_MU_DBG_ERR_FLAG(x) ((x) & (~BITS_MU_DBG_ERR_FLAG))\n#define BIT_GET_MU_DBG_ERR_FLAG(x)                                             \\\n\t(((x) >> BIT_SHIFT_MU_DBG_ERR_FLAG) & BIT_MASK_MU_DBG_ERR_FLAG)\n#define BIT_SET_MU_DBG_ERR_FLAG(x, v)                                          \\\n\t(BIT_CLEAR_MU_DBG_ERR_FLAG(x) | BIT_MU_DBG_ERR_FLAG(v))\n\n/* 2 REG_TX_ERR_RECOVERY_RST\t\t\t(Offset 0x05F3) */\n\n#define BIT_SHIFT_ERR_RECOVER_CNT 4\n#define BIT_MASK_ERR_RECOVER_CNT 0xf\n#define BIT_ERR_RECOVER_CNT(x)                                                 \\\n\t(((x) & BIT_MASK_ERR_RECOVER_CNT) << BIT_SHIFT_ERR_RECOVER_CNT)\n#define BITS_ERR_RECOVER_CNT                                                   \\\n\t(BIT_MASK_ERR_RECOVER_CNT << BIT_SHIFT_ERR_RECOVER_CNT)\n#define BIT_CLEAR_ERR_RECOVER_CNT(x) ((x) & (~BITS_ERR_RECOVER_CNT))\n#define BIT_GET_ERR_RECOVER_CNT(x)                                             \\\n\t(((x) >> BIT_SHIFT_ERR_RECOVER_CNT) & BIT_MASK_ERR_RECOVER_CNT)\n#define BIT_SET_ERR_RECOVER_CNT(x, v)                                          \\\n\t(BIT_CLEAR_ERR_RECOVER_CNT(x) | BIT_ERR_RECOVER_CNT(v))\n\n#define BIT_RX_HANG_ERR BIT(2)\n#define BIT_TX_HANG_ERR BIT(1)\n#define BIT_TX_ERR_RECOVERY_RST BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SCH_DBG\t\t\t\t(Offset 0x05F4) */\n\n#define BIT_SHIFT_SCH_DBG 0\n#define BIT_MASK_SCH_DBG 0xffffffffL\n#define BIT_SCH_DBG(x) (((x) & BIT_MASK_SCH_DBG) << BIT_SHIFT_SCH_DBG)\n#define BITS_SCH_DBG (BIT_MASK_SCH_DBG << BIT_SHIFT_SCH_DBG)\n#define BIT_CLEAR_SCH_DBG(x) ((x) & (~BITS_SCH_DBG))\n#define BIT_GET_SCH_DBG(x) (((x) >> BIT_SHIFT_SCH_DBG) & BIT_MASK_SCH_DBG)\n#define BIT_SET_SCH_DBG(x, v) (BIT_CLEAR_SCH_DBG(x) | BIT_SCH_DBG(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SCH_DBG_VALUE\t\t\t(Offset 0x05F4) */\n\n#define BIT_SHIFT_SCH_DBG_VALUE 0\n#define BIT_MASK_SCH_DBG_VALUE 0xffffffffL\n#define BIT_SCH_DBG_VALUE(x)                                                   \\\n\t(((x) & BIT_MASK_SCH_DBG_VALUE) << BIT_SHIFT_SCH_DBG_VALUE)\n#define BITS_SCH_DBG_VALUE (BIT_MASK_SCH_DBG_VALUE << BIT_SHIFT_SCH_DBG_VALUE)\n#define BIT_CLEAR_SCH_DBG_VALUE(x) ((x) & (~BITS_SCH_DBG_VALUE))\n#define BIT_GET_SCH_DBG_VALUE(x)                                               \\\n\t(((x) >> BIT_SHIFT_SCH_DBG_VALUE) & BIT_MASK_SCH_DBG_VALUE)\n#define BIT_SET_SCH_DBG_VALUE(x, v)                                            \\\n\t(BIT_CLEAR_SCH_DBG_VALUE(x) | BIT_SCH_DBG_VALUE(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SCH_TXCMD\t\t\t\t(Offset 0x05F8) */\n\n#define BIT_DIS_RX_BSSID_FIT BIT(6)\n#define BIT_DIS_TSF_UDT BIT(4)\n\n#define BIT_SHIFT_SCH_TXCMD 0\n#define BIT_MASK_SCH_TXCMD 0xffffffffL\n#define BIT_SCH_TXCMD(x) (((x) & BIT_MASK_SCH_TXCMD) << BIT_SHIFT_SCH_TXCMD)\n#define BITS_SCH_TXCMD (BIT_MASK_SCH_TXCMD << BIT_SHIFT_SCH_TXCMD)\n#define BIT_CLEAR_SCH_TXCMD(x) ((x) & (~BITS_SCH_TXCMD))\n#define BIT_GET_SCH_TXCMD(x) (((x) >> BIT_SHIFT_SCH_TXCMD) & BIT_MASK_SCH_TXCMD)\n#define BIT_SET_SCH_TXCMD(x, v) (BIT_CLEAR_SCH_TXCMD(x) | BIT_SCH_TXCMD(v))\n\n#define BIT_SHIFT_TBTT_PROHIBIT_SETUP 0\n#define BIT_MASK_TBTT_PROHIBIT_SETUP 0xf\n#define BIT_TBTT_PROHIBIT_SETUP(x)                                             \\\n\t(((x) & BIT_MASK_TBTT_PROHIBIT_SETUP) << BIT_SHIFT_TBTT_PROHIBIT_SETUP)\n#define BITS_TBTT_PROHIBIT_SETUP                                               \\\n\t(BIT_MASK_TBTT_PROHIBIT_SETUP << BIT_SHIFT_TBTT_PROHIBIT_SETUP)\n#define BIT_CLEAR_TBTT_PROHIBIT_SETUP(x) ((x) & (~BITS_TBTT_PROHIBIT_SETUP))\n#define BIT_GET_TBTT_PROHIBIT_SETUP(x)                                         \\\n\t(((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP) & BIT_MASK_TBTT_PROHIBIT_SETUP)\n#define BIT_SET_TBTT_PROHIBIT_SETUP(x, v)                                      \\\n\t(BIT_CLEAR_TBTT_PROHIBIT_SETUP(x) | BIT_TBTT_PROHIBIT_SETUP(v))\n\n#define BIT_SHIFT_DRVERLYITV 0\n#define BIT_MASK_DRVERLYITV 0xff\n#define BIT_DRVERLYITV(x) (((x) & BIT_MASK_DRVERLYITV) << BIT_SHIFT_DRVERLYITV)\n#define BITS_DRVERLYITV (BIT_MASK_DRVERLYITV << BIT_SHIFT_DRVERLYITV)\n#define BIT_CLEAR_DRVERLYITV(x) ((x) & (~BITS_DRVERLYITV))\n#define BIT_GET_DRVERLYITV(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DRVERLYITV) & BIT_MASK_DRVERLYITV)\n#define BIT_SET_DRVERLYITV(x, v) (BIT_CLEAR_DRVERLYITV(x) | BIT_DRVERLYITV(v))\n\n#define BIT_SHIFT_BCNDMATIM 0\n#define BIT_MASK_BCNDMATIM 0xff\n#define BIT_BCNDMATIM(x) (((x) & BIT_MASK_BCNDMATIM) << BIT_SHIFT_BCNDMATIM)\n#define BITS_BCNDMATIM (BIT_MASK_BCNDMATIM << BIT_SHIFT_BCNDMATIM)\n#define BIT_CLEAR_BCNDMATIM(x) ((x) & (~BITS_BCNDMATIM))\n#define BIT_GET_BCNDMATIM(x) (((x) >> BIT_SHIFT_BCNDMATIM) & BIT_MASK_BCNDMATIM)\n#define BIT_SET_BCNDMATIM(x, v) (BIT_CLEAR_BCNDMATIM(x) | BIT_BCNDMATIM(v))\n\n#define BIT_SHIFT_CTWND 0\n#define BIT_MASK_CTWND 0xff\n#define BIT_CTWND(x) (((x) & BIT_MASK_CTWND) << BIT_SHIFT_CTWND)\n#define BITS_CTWND (BIT_MASK_CTWND << BIT_SHIFT_CTWND)\n#define BIT_CLEAR_CTWND(x) ((x) & (~BITS_CTWND))\n#define BIT_GET_CTWND(x) (((x) >> BIT_SHIFT_CTWND) & BIT_MASK_CTWND)\n#define BIT_SET_CTWND(x, v) (BIT_CLEAR_CTWND(x) | BIT_CTWND(v))\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT)\n\n/* 2 REG_PAGE5_DUMMY\t\t\t\t(Offset 0x05FC) */\n\n#define BIT_ECO_TXOP_BREAK_FORCE_CFEND BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WMAC_CR\t\t\t\t(Offset 0x0600) */\n\n#define BIT_APSDOFF_STATUS BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WMAC_CR\t\t\t\t(Offset 0x0600) */\n\n#define BIT_APSDOFF BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WMAC_CR\t\t\t\t(Offset 0x0600) */\n\n#define BIT_STANDBY_STATUS BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_CR\t\t\t\t(Offset 0x0600) */\n\n#define BIT_IC_MACPHY_M BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_FWPKT_CR\t\t\t(Offset 0x0601) */\n\n#define BIT_FWEN BIT(7)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_WMAC_FWPKT_CR\t\t\t(Offset 0x0601) */\n\n#define BIT_FWRX_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_FWPKT_CR\t\t\t(Offset 0x0601) */\n\n#define BIT_PHYSTS_PKT_CTRL BIT(6)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)\n\n/* 2 REG_WMAC_FWPKT_CR\t\t\t(Offset 0x0601) */\n\n#define BIT_FWFULL_TO_RXFF_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_FWPKT_CR\t\t\t(Offset 0x0601) */\n\n#define BIT_APPHDR_MIDSRCH_FAIL BIT(4)\n#define BIT_FWPARSING_EN BIT(3)\n\n#define BIT_SHIFT_APPEND_MHDR_LEN 0\n#define BIT_MASK_APPEND_MHDR_LEN 0x7\n#define BIT_APPEND_MHDR_LEN(x)                                                 \\\n\t(((x) & BIT_MASK_APPEND_MHDR_LEN) << BIT_SHIFT_APPEND_MHDR_LEN)\n#define BITS_APPEND_MHDR_LEN                                                   \\\n\t(BIT_MASK_APPEND_MHDR_LEN << BIT_SHIFT_APPEND_MHDR_LEN)\n#define BIT_CLEAR_APPEND_MHDR_LEN(x) ((x) & (~BITS_APPEND_MHDR_LEN))\n#define BIT_GET_APPEND_MHDR_LEN(x)                                             \\\n\t(((x) >> BIT_SHIFT_APPEND_MHDR_LEN) & BIT_MASK_APPEND_MHDR_LEN)\n#define BIT_SET_APPEND_MHDR_LEN(x, v)                                          \\\n\t(BIT_CLEAR_APPEND_MHDR_LEN(x) | BIT_APPEND_MHDR_LEN(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_WMAC_EN_RTS_ADDR BIT(31)\n#define BIT_WMAC_DISABLE_CCK BIT(30)\n#define BIT_WMAC_RAW_LEN BIT(29)\n#define BIT_WMAC_NOTX_IN_RXNDP BIT(28)\n#define BIT_WMAC_EN_EOF BIT(27)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_WMAC_TCRPWRMGT_HWCTL_V1 BIT(26)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_WMAC_BF_SEL BIT(26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_BF_SEL BIT(25)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_WMAC_ANTMODE_SEL BIT(25)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_RXLEN_SEL BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_WMAC_TCRPWRMGT_HWCTL BIT(24)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_WMAC_TCRPWRMGT_HWCTL_EN BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_WMAC_SMOOTH_VAL BIT(23)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_WMAC_EN_SCRAM_INC BIT(22)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_UNDERFLOWEN_CMPLEN_SEL BIT(21)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_SHIFT_TSFT_CMP 20\n#define BIT_MASK_TSFT_CMP 0xf\n#define BIT_TSFT_CMP(x) (((x) & BIT_MASK_TSFT_CMP) << BIT_SHIFT_TSFT_CMP)\n#define BITS_TSFT_CMP (BIT_MASK_TSFT_CMP << BIT_SHIFT_TSFT_CMP)\n#define BIT_CLEAR_TSFT_CMP(x) ((x) & (~BITS_TSFT_CMP))\n#define BIT_GET_TSFT_CMP(x) (((x) >> BIT_SHIFT_TSFT_CMP) & BIT_MASK_TSFT_CMP)\n#define BIT_SET_TSFT_CMP(x, v) (BIT_CLEAR_TSFT_CMP(x) | BIT_TSFT_CMP(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_FETCH_MPDU_AFTER_WSEC_RDY BIT(20)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_WMAC_TCR_EN_20MST BIT(19)\n#define BIT_WMAC_DIS_SIGTA BIT(18)\n#define BIT_WMAC_DIS_A2B0 BIT(17)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_SHIFT_TSFT_CMP_CCK 16\n#define BIT_MASK_TSFT_CMP_CCK 0xf\n#define BIT_TSFT_CMP_CCK(x)                                                    \\\n\t(((x) & BIT_MASK_TSFT_CMP_CCK) << BIT_SHIFT_TSFT_CMP_CCK)\n#define BITS_TSFT_CMP_CCK (BIT_MASK_TSFT_CMP_CCK << BIT_SHIFT_TSFT_CMP_CCK)\n#define BIT_CLEAR_TSFT_CMP_CCK(x) ((x) & (~BITS_TSFT_CMP_CCK))\n#define BIT_GET_TSFT_CMP_CCK(x)                                                \\\n\t(((x) >> BIT_SHIFT_TSFT_CMP_CCK) & BIT_MASK_TSFT_CMP_CCK)\n#define BIT_SET_TSFT_CMP_CCK(x, v)                                             \\\n\t(BIT_CLEAR_TSFT_CMP_CCK(x) | BIT_TSFT_CMP_CCK(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_WMAC_MSK_SIGBCRC BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_WMAC_TCR_ERRSTEN_3 BIT(15)\n#define BIT_WMAC_TCR_ERRSTEN_2 BIT(14)\n#define BIT_WMAC_TCR_ERRSTEN_1 BIT(13)\n#define BIT_WMAC_TCR_ERRSTEN_0 BIT(12)\n#define BIT_WMAC_TCR_TXSK_PERPKT BIT(11)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT__TXSK_PERPKT BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_ICV BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_CFEND_FORMAT BIT(9)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_CFENDFORM BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_CRC BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_PWRBIT_OW_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_PWRMGT_CTL BIT(7)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_WMAC_TCRPWRMGT_HWDATA_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_PWR_ST BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_PWRMGT_VAL BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_WMAC_TCR_UPD_TIMIE BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_UPD_TIMIE BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_WMAC_TCR_UPD_HGQMD BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_UPD_HGQMD BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_VHTSIGA1_TXPS BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_PAD_SEL BIT(2)\n#define BIT_DIS_GCLK BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_TSFRST BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_WMAC_TCRPWRMGT_HWACT_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_TCR\t\t\t\t\t(Offset 0x0604) */\n\n#define BIT_R_WMAC_TCR_LSIG BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_APP_FCS BIT(31)\n#define BIT_APP_MIC BIT(30)\n#define BIT_APP_ICV BIT(29)\n#define BIT_APP_PHYSTS BIT(28)\n#define BIT_APP_BASSN BIT(27)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_VHT_DACK BIT(26)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_TCPOFLD_EN BIT(25)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_ENMBID BIT(24)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_ENADDRCAM BIT(24)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_LSIGEN BIT(23)\n#define BIT_MFBEN BIT(22)\n#define BIT_DISCHKPPDLLEN BIT(21)\n#define BIT_PKTCTL_DLEN BIT(20)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_DISGCLK BIT(19)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_TIM_PARSER_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_TIMPSR_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_BC_MD_EN BIT(17)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_BCMDINT_EN BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_UC_MD_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_UCMDINT_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_RXSK_PERPKT BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_HTC_LOC_CTRL BIT(14)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_HTCBFMC BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_AMF BIT(13)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_CHK_PREVTCA2 BIT(13)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_ACK_WITH_CBSSID_DATA_OPTION BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_ACF BIT(12)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_ACK_WITH_CBSSID_DATA_OPTION_V1 BIT(12)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_RPFM_CAM_ENABLE BIT(12)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_ADF BIT(11)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_TA_BCN BIT(11)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_DISDECMYPKT BIT(10)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_DISDECNMYPKT BIT(10)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_AICV BIT(9)\n#define BIT_ACRC32 BIT(8)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_CBSSID_BCN BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_CBSSID_MGNT BIT(7)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RCR\t\t\t\t\t(Offset 0x0608) */\n\n#define BIT_CBSSID_DATA BIT(6)\n#define BIT_APWRMGT BIT(5)\n#define BIT_ADD3 BIT(4)\n#define BIT_AB BIT(3)\n#define BIT_AM BIT(2)\n#define BIT_APM BIT(1)\n#define BIT_AAP BIT(0)\n\n#define BIT_SHIFT_RXPKTLMT 0\n#define BIT_MASK_RXPKTLMT 0x3f\n#define BIT_RXPKTLMT(x) (((x) & BIT_MASK_RXPKTLMT) << BIT_SHIFT_RXPKTLMT)\n#define BITS_RXPKTLMT (BIT_MASK_RXPKTLMT << BIT_SHIFT_RXPKTLMT)\n#define BIT_CLEAR_RXPKTLMT(x) ((x) & (~BITS_RXPKTLMT))\n#define BIT_GET_RXPKTLMT(x) (((x) >> BIT_SHIFT_RXPKTLMT) & BIT_MASK_RXPKTLMT)\n#define BIT_SET_RXPKTLMT(x, v) (BIT_CLEAR_RXPKTLMT(x) | BIT_RXPKTLMT(v))\n\n/* 2 REG_RX_DLK_TIME\t\t\t\t(Offset 0x060D) */\n\n#define BIT_SHIFT_RX_DLK_TIME 0\n#define BIT_MASK_RX_DLK_TIME 0xff\n#define BIT_RX_DLK_TIME(x)                                                     \\\n\t(((x) & BIT_MASK_RX_DLK_TIME) << BIT_SHIFT_RX_DLK_TIME)\n#define BITS_RX_DLK_TIME (BIT_MASK_RX_DLK_TIME << BIT_SHIFT_RX_DLK_TIME)\n#define BIT_CLEAR_RX_DLK_TIME(x) ((x) & (~BITS_RX_DLK_TIME))\n#define BIT_GET_RX_DLK_TIME(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RX_DLK_TIME) & BIT_MASK_RX_DLK_TIME)\n#define BIT_SET_RX_DLK_TIME(x, v)                                              \\\n\t(BIT_CLEAR_RX_DLK_TIME(x) | BIT_RX_DLK_TIME(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SDIO_RXINT_LEN_TH\t\t\t(Offset 0x1025060E) */\n\n#define BIT_SHIFT_SDIO_RXINT_LEN_TH 0\n#define BIT_MASK_SDIO_RXINT_LEN_TH 0xff\n#define BIT_SDIO_RXINT_LEN_TH(x)                                               \\\n\t(((x) & BIT_MASK_SDIO_RXINT_LEN_TH) << BIT_SHIFT_SDIO_RXINT_LEN_TH)\n#define BITS_SDIO_RXINT_LEN_TH                                                 \\\n\t(BIT_MASK_SDIO_RXINT_LEN_TH << BIT_SHIFT_SDIO_RXINT_LEN_TH)\n#define BIT_CLEAR_SDIO_RXINT_LEN_TH(x) ((x) & (~BITS_SDIO_RXINT_LEN_TH))\n#define BIT_GET_SDIO_RXINT_LEN_TH(x)                                           \\\n\t(((x) >> BIT_SHIFT_SDIO_RXINT_LEN_TH) & BIT_MASK_SDIO_RXINT_LEN_TH)\n#define BIT_SET_SDIO_RXINT_LEN_TH(x, v)                                        \\\n\t(BIT_CLEAR_SDIO_RXINT_LEN_TH(x) | BIT_SDIO_RXINT_LEN_TH(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RX_DRVINFO_SZ\t\t\t(Offset 0x060F) */\n\n#define BIT_APP_PHYSTS_PER_SUBMPDU BIT(7)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RX_DRVINFO_SZ\t\t\t(Offset 0x060F) */\n\n#define BIT_PHYSTS_PER_PKT_MODE BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RX_DRVINFO_SZ\t\t\t(Offset 0x060F) */\n\n#define BIT_APP_MH_SHIFT_VAL BIT(6)\n#define BIT_WMAC_ENSHIFT BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RX_DRVINFO_SZ\t\t\t(Offset 0x060F) */\n\n#define BIT_SHIFT_BITMAP_SSNBK_COUNTER 2\n#define BIT_MASK_BITMAP_SSNBK_COUNTER 0x3f\n#define BIT_BITMAP_SSNBK_COUNTER(x)                                            \\\n\t(((x) & BIT_MASK_BITMAP_SSNBK_COUNTER)                                 \\\n\t << BIT_SHIFT_BITMAP_SSNBK_COUNTER)\n#define BITS_BITMAP_SSNBK_COUNTER                                              \\\n\t(BIT_MASK_BITMAP_SSNBK_COUNTER << BIT_SHIFT_BITMAP_SSNBK_COUNTER)\n#define BIT_CLEAR_BITMAP_SSNBK_COUNTER(x) ((x) & (~BITS_BITMAP_SSNBK_COUNTER))\n#define BIT_GET_BITMAP_SSNBK_COUNTER(x)                                        \\\n\t(((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER) &                             \\\n\t BIT_MASK_BITMAP_SSNBK_COUNTER)\n#define BIT_SET_BITMAP_SSNBK_COUNTER(x, v)                                     \\\n\t(BIT_CLEAR_BITMAP_SSNBK_COUNTER(x) | BIT_BITMAP_SSNBK_COUNTER(v))\n\n#define BIT_BITMAP_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RX_DRVINFO_SZ\t\t\t(Offset 0x060F) */\n\n#define BIT_SHIFT_DRVINFO_SZ 0\n#define BIT_MASK_DRVINFO_SZ 0xff\n#define BIT_DRVINFO_SZ(x) (((x) & BIT_MASK_DRVINFO_SZ) << BIT_SHIFT_DRVINFO_SZ)\n#define BITS_DRVINFO_SZ (BIT_MASK_DRVINFO_SZ << BIT_SHIFT_DRVINFO_SZ)\n#define BIT_CLEAR_DRVINFO_SZ(x) ((x) & (~BITS_DRVINFO_SZ))\n#define BIT_GET_DRVINFO_SZ(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DRVINFO_SZ) & BIT_MASK_DRVINFO_SZ)\n#define BIT_SET_DRVINFO_SZ(x, v) (BIT_CLEAR_DRVINFO_SZ(x) | BIT_DRVINFO_SZ(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RX_DRVINFO_SZ\t\t\t(Offset 0x060F) */\n\n#define BIT_SHIFT_DRVINFO_SZ_V1 0\n#define BIT_MASK_DRVINFO_SZ_V1 0xf\n#define BIT_DRVINFO_SZ_V1(x)                                                   \\\n\t(((x) & BIT_MASK_DRVINFO_SZ_V1) << BIT_SHIFT_DRVINFO_SZ_V1)\n#define BITS_DRVINFO_SZ_V1 (BIT_MASK_DRVINFO_SZ_V1 << BIT_SHIFT_DRVINFO_SZ_V1)\n#define BIT_CLEAR_DRVINFO_SZ_V1(x) ((x) & (~BITS_DRVINFO_SZ_V1))\n#define BIT_GET_DRVINFO_SZ_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_DRVINFO_SZ_V1) & BIT_MASK_DRVINFO_SZ_V1)\n#define BIT_SET_DRVINFO_SZ_V1(x, v)                                            \\\n\t(BIT_CLEAR_DRVINFO_SZ_V1(x) | BIT_DRVINFO_SZ_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MACID\t\t\t\t(Offset 0x0610) */\n\n#define BIT_SHIFT_MACID 0\n#define BIT_MASK_MACID 0xffffffffffffL\n#define BIT_MACID(x) (((x) & BIT_MASK_MACID) << BIT_SHIFT_MACID)\n#define BITS_MACID (BIT_MASK_MACID << BIT_SHIFT_MACID)\n#define BIT_CLEAR_MACID(x) ((x) & (~BITS_MACID))\n#define BIT_GET_MACID(x) (((x) >> BIT_SHIFT_MACID) & BIT_MASK_MACID)\n#define BIT_SET_MACID(x, v) (BIT_CLEAR_MACID(x) | BIT_MACID(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MACID\t\t\t\t(Offset 0x0610) */\n\n#define BIT_SHIFT_MACID_V1 0\n#define BIT_MASK_MACID_V1 0xffffffffL\n#define BIT_MACID_V1(x) (((x) & BIT_MASK_MACID_V1) << BIT_SHIFT_MACID_V1)\n#define BITS_MACID_V1 (BIT_MASK_MACID_V1 << BIT_SHIFT_MACID_V1)\n#define BIT_CLEAR_MACID_V1(x) ((x) & (~BITS_MACID_V1))\n#define BIT_GET_MACID_V1(x) (((x) >> BIT_SHIFT_MACID_V1) & BIT_MASK_MACID_V1)\n#define BIT_SET_MACID_V1(x, v) (BIT_CLEAR_MACID_V1(x) | BIT_MACID_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_MACID_H\t\t\t\t(Offset 0x0614) */\n\n#define BIT_SHIFT_MACID_H 0\n#define BIT_MASK_MACID_H 0xffff\n#define BIT_MACID_H(x) (((x) & BIT_MASK_MACID_H) << BIT_SHIFT_MACID_H)\n#define BITS_MACID_H (BIT_MASK_MACID_H << BIT_SHIFT_MACID_H)\n#define BIT_CLEAR_MACID_H(x) ((x) & (~BITS_MACID_H))\n#define BIT_GET_MACID_H(x) (((x) >> BIT_SHIFT_MACID_H) & BIT_MASK_MACID_H)\n#define BIT_SET_MACID_H(x, v) (BIT_CLEAR_MACID_H(x) | BIT_MACID_H(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MACID_H\t\t\t\t(Offset 0x0614) */\n\n#define BIT_SHIFT_MACID_H_V1 0\n#define BIT_MASK_MACID_H_V1 0xffff\n#define BIT_MACID_H_V1(x) (((x) & BIT_MASK_MACID_H_V1) << BIT_SHIFT_MACID_H_V1)\n#define BITS_MACID_H_V1 (BIT_MASK_MACID_H_V1 << BIT_SHIFT_MACID_H_V1)\n#define BIT_CLEAR_MACID_H_V1(x) ((x) & (~BITS_MACID_H_V1))\n#define BIT_GET_MACID_H_V1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_MACID_H_V1) & BIT_MASK_MACID_H_V1)\n#define BIT_SET_MACID_H_V1(x, v) (BIT_CLEAR_MACID_H_V1(x) | BIT_MACID_H_V1(v))\n\n#define BIT_SHIFT_BSSID_H_V1 0\n#define BIT_MASK_BSSID_H_V1 0xffff\n#define BIT_BSSID_H_V1(x) (((x) & BIT_MASK_BSSID_H_V1) << BIT_SHIFT_BSSID_H_V1)\n#define BITS_BSSID_H_V1 (BIT_MASK_BSSID_H_V1 << BIT_SHIFT_BSSID_H_V1)\n#define BIT_CLEAR_BSSID_H_V1(x) ((x) & (~BITS_BSSID_H_V1))\n#define BIT_GET_BSSID_H_V1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BSSID_H_V1) & BIT_MASK_BSSID_H_V1)\n#define BIT_SET_BSSID_H_V1(x, v) (BIT_CLEAR_BSSID_H_V1(x) | BIT_BSSID_H_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BSSID\t\t\t\t(Offset 0x0618) */\n\n#define BIT_SHIFT_BSSID 0\n#define BIT_MASK_BSSID 0xffffffffffffL\n#define BIT_BSSID(x) (((x) & BIT_MASK_BSSID) << BIT_SHIFT_BSSID)\n#define BITS_BSSID (BIT_MASK_BSSID << BIT_SHIFT_BSSID)\n#define BIT_CLEAR_BSSID(x) ((x) & (~BITS_BSSID))\n#define BIT_GET_BSSID(x) (((x) >> BIT_SHIFT_BSSID) & BIT_MASK_BSSID)\n#define BIT_SET_BSSID(x, v) (BIT_CLEAR_BSSID(x) | BIT_BSSID(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BSSID\t\t\t\t(Offset 0x0618) */\n\n#define BIT_SHIFT_BSSID_V1 0\n#define BIT_MASK_BSSID_V1 0xffffffffL\n#define BIT_BSSID_V1(x) (((x) & BIT_MASK_BSSID_V1) << BIT_SHIFT_BSSID_V1)\n#define BITS_BSSID_V1 (BIT_MASK_BSSID_V1 << BIT_SHIFT_BSSID_V1)\n#define BIT_CLEAR_BSSID_V1(x) ((x) & (~BITS_BSSID_V1))\n#define BIT_GET_BSSID_V1(x) (((x) >> BIT_SHIFT_BSSID_V1) & BIT_MASK_BSSID_V1)\n#define BIT_SET_BSSID_V1(x, v) (BIT_CLEAR_BSSID_V1(x) | BIT_BSSID_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_BSSID_H\t\t\t\t(Offset 0x061C) */\n\n#define BIT_SHIFT_BSSID_H 0\n#define BIT_MASK_BSSID_H 0xffff\n#define BIT_BSSID_H(x) (((x) & BIT_MASK_BSSID_H) << BIT_SHIFT_BSSID_H)\n#define BITS_BSSID_H (BIT_MASK_BSSID_H << BIT_SHIFT_BSSID_H)\n#define BIT_CLEAR_BSSID_H(x) ((x) & (~BITS_BSSID_H))\n#define BIT_GET_BSSID_H(x) (((x) >> BIT_SHIFT_BSSID_H) & BIT_MASK_BSSID_H)\n#define BIT_SET_BSSID_H(x, v) (BIT_CLEAR_BSSID_H(x) | BIT_BSSID_H(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MAR\t\t\t\t\t(Offset 0x0620) */\n\n#define BIT_SHIFT_MAR 0\n#define BIT_MASK_MAR 0xffffffffffffffffL\n#define BIT_MAR(x) (((x) & BIT_MASK_MAR) << BIT_SHIFT_MAR)\n#define BITS_MAR (BIT_MASK_MAR << BIT_SHIFT_MAR)\n#define BIT_CLEAR_MAR(x) ((x) & (~BITS_MAR))\n#define BIT_GET_MAR(x) (((x) >> BIT_SHIFT_MAR) & BIT_MASK_MAR)\n#define BIT_SET_MAR(x, v) (BIT_CLEAR_MAR(x) | BIT_MAR(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MAR\t\t\t\t\t(Offset 0x0620) */\n\n#define BIT_SHIFT_MAR_V1 0\n#define BIT_MASK_MAR_V1 0xffffffffL\n#define BIT_MAR_V1(x) (((x) & BIT_MASK_MAR_V1) << BIT_SHIFT_MAR_V1)\n#define BITS_MAR_V1 (BIT_MASK_MAR_V1 << BIT_SHIFT_MAR_V1)\n#define BIT_CLEAR_MAR_V1(x) ((x) & (~BITS_MAR_V1))\n#define BIT_GET_MAR_V1(x) (((x) >> BIT_SHIFT_MAR_V1) & BIT_MASK_MAR_V1)\n#define BIT_SET_MAR_V1(x, v) (BIT_CLEAR_MAR_V1(x) | BIT_MAR_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_MAR_H\t\t\t\t(Offset 0x0624) */\n\n#define BIT_SHIFT_MAR_H 0\n#define BIT_MASK_MAR_H 0xffffffffL\n#define BIT_MAR_H(x) (((x) & BIT_MASK_MAR_H) << BIT_SHIFT_MAR_H)\n#define BITS_MAR_H (BIT_MASK_MAR_H << BIT_SHIFT_MAR_H)\n#define BIT_CLEAR_MAR_H(x) ((x) & (~BITS_MAR_H))\n#define BIT_GET_MAR_H(x) (((x) >> BIT_SHIFT_MAR_H) & BIT_MASK_MAR_H)\n#define BIT_SET_MAR_H(x, v) (BIT_CLEAR_MAR_H(x) | BIT_MAR_H(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MAR_H\t\t\t\t(Offset 0x0624) */\n\n#define BIT_SHIFT_MAR_H_V1 0\n#define BIT_MASK_MAR_H_V1 0xffffffffL\n#define BIT_MAR_H_V1(x) (((x) & BIT_MASK_MAR_H_V1) << BIT_SHIFT_MAR_H_V1)\n#define BITS_MAR_H_V1 (BIT_MASK_MAR_H_V1 << BIT_SHIFT_MAR_H_V1)\n#define BIT_CLEAR_MAR_H_V1(x) ((x) & (~BITS_MAR_H_V1))\n#define BIT_GET_MAR_H_V1(x) (((x) >> BIT_SHIFT_MAR_H_V1) & BIT_MASK_MAR_H_V1)\n#define BIT_SET_MAR_H_V1(x, v) (BIT_CLEAR_MAR_H_V1(x) | BIT_MAR_H_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MBIDCAMCFG_1\t\t\t(Offset 0x0628) */\n\n#define BIT_MBIDCAM_POLL BIT(31)\n#define BIT_MBIDCAM_WT_EN BIT(30)\n#define BIT_LSIC_TXOP_EN BIT(17)\n\n#define BIT_SHIFT_MBIDCAM_RWDATA_L 0\n#define BIT_MASK_MBIDCAM_RWDATA_L 0xffffffffL\n#define BIT_MBIDCAM_RWDATA_L(x)                                                \\\n\t(((x) & BIT_MASK_MBIDCAM_RWDATA_L) << BIT_SHIFT_MBIDCAM_RWDATA_L)\n#define BITS_MBIDCAM_RWDATA_L                                                  \\\n\t(BIT_MASK_MBIDCAM_RWDATA_L << BIT_SHIFT_MBIDCAM_RWDATA_L)\n#define BIT_CLEAR_MBIDCAM_RWDATA_L(x) ((x) & (~BITS_MBIDCAM_RWDATA_L))\n#define BIT_GET_MBIDCAM_RWDATA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L) & BIT_MASK_MBIDCAM_RWDATA_L)\n#define BIT_SET_MBIDCAM_RWDATA_L(x, v)                                         \\\n\t(BIT_CLEAR_MBIDCAM_RWDATA_L(x) | BIT_MBIDCAM_RWDATA_L(v))\n\n#define BIT_SHIFT_MBIDCAM_RWDATA_H 0\n#define BIT_MASK_MBIDCAM_RWDATA_H 0xffff\n#define BIT_MBIDCAM_RWDATA_H(x)                                                \\\n\t(((x) & BIT_MASK_MBIDCAM_RWDATA_H) << BIT_SHIFT_MBIDCAM_RWDATA_H)\n#define BITS_MBIDCAM_RWDATA_H                                                  \\\n\t(BIT_MASK_MBIDCAM_RWDATA_H << BIT_SHIFT_MBIDCAM_RWDATA_H)\n#define BIT_CLEAR_MBIDCAM_RWDATA_H(x) ((x) & (~BITS_MBIDCAM_RWDATA_H))\n#define BIT_GET_MBIDCAM_RWDATA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H) & BIT_MASK_MBIDCAM_RWDATA_H)\n#define BIT_SET_MBIDCAM_RWDATA_H(x, v)                                         \\\n\t(BIT_CLEAR_MBIDCAM_RWDATA_H(x) | BIT_MBIDCAM_RWDATA_H(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_MBIDCAM_CFG\t\t\t\t(Offset 0x062C) */\n\n#define BIT_MBIDCAM_RST_V1 BIT(29)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MBIDCAMCFG_2\t\t\t(Offset 0x062C) */\n\n#define BIT_SHIFT_MBIDCAM_ADDR_V1 24\n#define BIT_MASK_MBIDCAM_ADDR_V1 0x3f\n#define BIT_MBIDCAM_ADDR_V1(x)                                                 \\\n\t(((x) & BIT_MASK_MBIDCAM_ADDR_V1) << BIT_SHIFT_MBIDCAM_ADDR_V1)\n#define BITS_MBIDCAM_ADDR_V1                                                   \\\n\t(BIT_MASK_MBIDCAM_ADDR_V1 << BIT_SHIFT_MBIDCAM_ADDR_V1)\n#define BIT_CLEAR_MBIDCAM_ADDR_V1(x) ((x) & (~BITS_MBIDCAM_ADDR_V1))\n#define BIT_GET_MBIDCAM_ADDR_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_MBIDCAM_ADDR_V1) & BIT_MASK_MBIDCAM_ADDR_V1)\n#define BIT_SET_MBIDCAM_ADDR_V1(x, v)                                          \\\n\t(BIT_CLEAR_MBIDCAM_ADDR_V1(x) | BIT_MBIDCAM_ADDR_V1(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_MBIDCAMCFG_2\t\t\t(Offset 0x062C) */\n\n#define BIT_SHIFT_MBIDCAM_ADDR_V2 23\n#define BIT_MASK_MBIDCAM_ADDR_V2 0x7f\n#define BIT_MBIDCAM_ADDR_V2(x)                                                 \\\n\t(((x) & BIT_MASK_MBIDCAM_ADDR_V2) << BIT_SHIFT_MBIDCAM_ADDR_V2)\n#define BITS_MBIDCAM_ADDR_V2                                                   \\\n\t(BIT_MASK_MBIDCAM_ADDR_V2 << BIT_SHIFT_MBIDCAM_ADDR_V2)\n#define BIT_CLEAR_MBIDCAM_ADDR_V2(x) ((x) & (~BITS_MBIDCAM_ADDR_V2))\n#define BIT_GET_MBIDCAM_ADDR_V2(x)                                             \\\n\t(((x) >> BIT_SHIFT_MBIDCAM_ADDR_V2) & BIT_MASK_MBIDCAM_ADDR_V2)\n#define BIT_SET_MBIDCAM_ADDR_V2(x, v)                                          \\\n\t(BIT_CLEAR_MBIDCAM_ADDR_V2(x) | BIT_MBIDCAM_ADDR_V2(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_MBIDCAMCFG_2\t\t\t(Offset 0x062C) */\n\n#define BIT_MBIDCAM_RST BIT(19)\n#define BIT_MBIDCAM_VALID_V1 BIT(18)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_MBIDCAMCFG_2\t\t\t(Offset 0x062C) */\n\n#define BIT_REPEAT_MODE_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_WMAC_DEBUG_SEL\t\t\t(Offset 0x062C) */\n\n#define BIT_SHIFT_WMAC_ARB_DBG_SEL 3\n#define BIT_MASK_WMAC_ARB_DBG_SEL 0x3\n#define BIT_WMAC_ARB_DBG_SEL(x)                                                \\\n\t(((x) & BIT_MASK_WMAC_ARB_DBG_SEL) << BIT_SHIFT_WMAC_ARB_DBG_SEL)\n#define BITS_WMAC_ARB_DBG_SEL                                                  \\\n\t(BIT_MASK_WMAC_ARB_DBG_SEL << BIT_SHIFT_WMAC_ARB_DBG_SEL)\n#define BIT_CLEAR_WMAC_ARB_DBG_SEL(x) ((x) & (~BITS_WMAC_ARB_DBG_SEL))\n#define BIT_GET_WMAC_ARB_DBG_SEL(x)                                            \\\n\t(((x) >> BIT_SHIFT_WMAC_ARB_DBG_SEL) & BIT_MASK_WMAC_ARB_DBG_SEL)\n#define BIT_SET_WMAC_ARB_DBG_SEL(x, v)                                         \\\n\t(BIT_CLEAR_WMAC_ARB_DBG_SEL(x) | BIT_WMAC_ARB_DBG_SEL(v))\n\n#define BIT_WMAC_EXT_DBG_SEL BIT(2)\n\n#define BIT_SHIFT_WMAC_MU_DBGSEL_V1 0\n#define BIT_MASK_WMAC_MU_DBGSEL_V1 0x3\n#define BIT_WMAC_MU_DBGSEL_V1(x)                                               \\\n\t(((x) & BIT_MASK_WMAC_MU_DBGSEL_V1) << BIT_SHIFT_WMAC_MU_DBGSEL_V1)\n#define BITS_WMAC_MU_DBGSEL_V1                                                 \\\n\t(BIT_MASK_WMAC_MU_DBGSEL_V1 << BIT_SHIFT_WMAC_MU_DBGSEL_V1)\n#define BIT_CLEAR_WMAC_MU_DBGSEL_V1(x) ((x) & (~BITS_WMAC_MU_DBGSEL_V1))\n#define BIT_GET_WMAC_MU_DBGSEL_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_V1) & BIT_MASK_WMAC_MU_DBGSEL_V1)\n#define BIT_SET_WMAC_MU_DBGSEL_V1(x, v)                                        \\\n\t(BIT_CLEAR_WMAC_MU_DBGSEL_V1(x) | BIT_WMAC_MU_DBGSEL_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MCU_TEST_1\t\t\t\t(Offset 0x0630) */\n\n#define BIT_SHIFT_MCU_RSVD 0\n#define BIT_MASK_MCU_RSVD 0xffffffffL\n#define BIT_MCU_RSVD(x) (((x) & BIT_MASK_MCU_RSVD) << BIT_SHIFT_MCU_RSVD)\n#define BITS_MCU_RSVD (BIT_MASK_MCU_RSVD << BIT_SHIFT_MCU_RSVD)\n#define BIT_CLEAR_MCU_RSVD(x) ((x) & (~BITS_MCU_RSVD))\n#define BIT_GET_MCU_RSVD(x) (((x) >> BIT_SHIFT_MCU_RSVD) & BIT_MASK_MCU_RSVD)\n#define BIT_SET_MCU_RSVD(x, v) (BIT_CLEAR_MCU_RSVD(x) | BIT_MCU_RSVD(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_TCR_TSFT_OFS\t\t\t(Offset 0x0630) */\n\n#define BIT_SHIFT_WMAC_TCR_TSFT_OFS 0\n#define BIT_MASK_WMAC_TCR_TSFT_OFS 0xffff\n#define BIT_WMAC_TCR_TSFT_OFS(x)                                               \\\n\t(((x) & BIT_MASK_WMAC_TCR_TSFT_OFS) << BIT_SHIFT_WMAC_TCR_TSFT_OFS)\n#define BITS_WMAC_TCR_TSFT_OFS                                                 \\\n\t(BIT_MASK_WMAC_TCR_TSFT_OFS << BIT_SHIFT_WMAC_TCR_TSFT_OFS)\n#define BIT_CLEAR_WMAC_TCR_TSFT_OFS(x) ((x) & (~BITS_WMAC_TCR_TSFT_OFS))\n#define BIT_GET_WMAC_TCR_TSFT_OFS(x)                                           \\\n\t(((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS) & BIT_MASK_WMAC_TCR_TSFT_OFS)\n#define BIT_SET_WMAC_TCR_TSFT_OFS(x, v)                                        \\\n\t(BIT_CLEAR_WMAC_TCR_TSFT_OFS(x) | BIT_WMAC_TCR_TSFT_OFS(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_UDF_THSD\t\t\t\t(Offset 0x0632) */\n\n#define BIT_CSIRPT_LEN_BB_MORE_THAN_MAC BIT(23)\n#define BIT_CSI_CHKSUM_ERROR BIT(22)\n#define BIT_MACRX_ERR_4 BIT(20)\n#define BIT_MACRX_ERR_3 BIT(19)\n#define BIT_MACRX_ERR_2 BIT(18)\n\n#define BIT_SHIFT_WMAC_RESP_ANTD 12\n#define BIT_MASK_WMAC_RESP_ANTD 0xf\n#define BIT_WMAC_RESP_ANTD(x)                                                  \\\n\t(((x) & BIT_MASK_WMAC_RESP_ANTD) << BIT_SHIFT_WMAC_RESP_ANTD)\n#define BITS_WMAC_RESP_ANTD                                                    \\\n\t(BIT_MASK_WMAC_RESP_ANTD << BIT_SHIFT_WMAC_RESP_ANTD)\n#define BIT_CLEAR_WMAC_RESP_ANTD(x) ((x) & (~BITS_WMAC_RESP_ANTD))\n#define BIT_GET_WMAC_RESP_ANTD(x)                                              \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_ANTD) & BIT_MASK_WMAC_RESP_ANTD)\n#define BIT_SET_WMAC_RESP_ANTD(x, v)                                           \\\n\t(BIT_CLEAR_WMAC_RESP_ANTD(x) | BIT_WMAC_RESP_ANTD(v))\n\n#define BIT_SHIFT_WMAC_RESP_ANTC 8\n#define BIT_MASK_WMAC_RESP_ANTC 0xf\n#define BIT_WMAC_RESP_ANTC(x)                                                  \\\n\t(((x) & BIT_MASK_WMAC_RESP_ANTC) << BIT_SHIFT_WMAC_RESP_ANTC)\n#define BITS_WMAC_RESP_ANTC                                                    \\\n\t(BIT_MASK_WMAC_RESP_ANTC << BIT_SHIFT_WMAC_RESP_ANTC)\n#define BIT_CLEAR_WMAC_RESP_ANTC(x) ((x) & (~BITS_WMAC_RESP_ANTC))\n#define BIT_GET_WMAC_RESP_ANTC(x)                                              \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_ANTC) & BIT_MASK_WMAC_RESP_ANTC)\n#define BIT_SET_WMAC_RESP_ANTC(x, v)                                           \\\n\t(BIT_CLEAR_WMAC_RESP_ANTC(x) | BIT_WMAC_RESP_ANTC(v))\n\n#define BIT_UDF_THSD_V1 BIT(7)\n\n#define BIT_SHIFT_WMAC_RESP_ANTB 4\n#define BIT_MASK_WMAC_RESP_ANTB 0xf\n#define BIT_WMAC_RESP_ANTB(x)                                                  \\\n\t(((x) & BIT_MASK_WMAC_RESP_ANTB) << BIT_SHIFT_WMAC_RESP_ANTB)\n#define BITS_WMAC_RESP_ANTB                                                    \\\n\t(BIT_MASK_WMAC_RESP_ANTB << BIT_SHIFT_WMAC_RESP_ANTB)\n#define BIT_CLEAR_WMAC_RESP_ANTB(x) ((x) & (~BITS_WMAC_RESP_ANTB))\n#define BIT_GET_WMAC_RESP_ANTB(x)                                              \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_ANTB) & BIT_MASK_WMAC_RESP_ANTB)\n#define BIT_SET_WMAC_RESP_ANTB(x, v)                                           \\\n\t(BIT_CLEAR_WMAC_RESP_ANTB(x) | BIT_WMAC_RESP_ANTB(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_UDF_THSD\t\t\t\t(Offset 0x0632) */\n\n#define BIT_SHIFT_UDF_THSD 0\n#define BIT_MASK_UDF_THSD 0xff\n#define BIT_UDF_THSD(x) (((x) & BIT_MASK_UDF_THSD) << BIT_SHIFT_UDF_THSD)\n#define BITS_UDF_THSD (BIT_MASK_UDF_THSD << BIT_SHIFT_UDF_THSD)\n#define BIT_CLEAR_UDF_THSD(x) ((x) & (~BITS_UDF_THSD))\n#define BIT_GET_UDF_THSD(x) (((x) >> BIT_SHIFT_UDF_THSD) & BIT_MASK_UDF_THSD)\n#define BIT_SET_UDF_THSD(x, v) (BIT_CLEAR_UDF_THSD(x) | BIT_UDF_THSD(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_UDF_THSD\t\t\t\t(Offset 0x0632) */\n\n#define BIT_SHIFT_UDF_THSD_VALUE 0\n#define BIT_MASK_UDF_THSD_VALUE 0x7f\n#define BIT_UDF_THSD_VALUE(x)                                                  \\\n\t(((x) & BIT_MASK_UDF_THSD_VALUE) << BIT_SHIFT_UDF_THSD_VALUE)\n#define BITS_UDF_THSD_VALUE                                                    \\\n\t(BIT_MASK_UDF_THSD_VALUE << BIT_SHIFT_UDF_THSD_VALUE)\n#define BIT_CLEAR_UDF_THSD_VALUE(x) ((x) & (~BITS_UDF_THSD_VALUE))\n#define BIT_GET_UDF_THSD_VALUE(x)                                              \\\n\t(((x) >> BIT_SHIFT_UDF_THSD_VALUE) & BIT_MASK_UDF_THSD_VALUE)\n#define BIT_SET_UDF_THSD_VALUE(x, v)                                           \\\n\t(BIT_CLEAR_UDF_THSD_VALUE(x) | BIT_UDF_THSD_VALUE(v))\n\n#define BIT_SHIFT_WMAC_RESP_ANTA 0\n#define BIT_MASK_WMAC_RESP_ANTA 0xf\n#define BIT_WMAC_RESP_ANTA(x)                                                  \\\n\t(((x) & BIT_MASK_WMAC_RESP_ANTA) << BIT_SHIFT_WMAC_RESP_ANTA)\n#define BITS_WMAC_RESP_ANTA                                                    \\\n\t(BIT_MASK_WMAC_RESP_ANTA << BIT_SHIFT_WMAC_RESP_ANTA)\n#define BIT_CLEAR_WMAC_RESP_ANTA(x) ((x) & (~BITS_WMAC_RESP_ANTA))\n#define BIT_GET_WMAC_RESP_ANTA(x)                                              \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_ANTA) & BIT_MASK_WMAC_RESP_ANTA)\n#define BIT_SET_WMAC_RESP_ANTA(x, v)                                           \\\n\t(BIT_CLEAR_WMAC_RESP_ANTA(x) | BIT_WMAC_RESP_ANTA(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ZLD_NUM\t\t\t\t(Offset 0x0633) */\n\n#define BIT_SHIFT_ZLD_NUM 0\n#define BIT_MASK_ZLD_NUM 0xff\n#define BIT_ZLD_NUM(x) (((x) & BIT_MASK_ZLD_NUM) << BIT_SHIFT_ZLD_NUM)\n#define BITS_ZLD_NUM (BIT_MASK_ZLD_NUM << BIT_SHIFT_ZLD_NUM)\n#define BIT_CLEAR_ZLD_NUM(x) ((x) & (~BITS_ZLD_NUM))\n#define BIT_GET_ZLD_NUM(x) (((x) >> BIT_SHIFT_ZLD_NUM) & BIT_MASK_ZLD_NUM)\n#define BIT_SET_ZLD_NUM(x, v) (BIT_CLEAR_ZLD_NUM(x) | BIT_ZLD_NUM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MCU_TEST_2\t\t\t\t(Offset 0x0634) */\n\n#define BIT_SHIFT_MCU_RSVD_2 0\n#define BIT_MASK_MCU_RSVD_2 0xffffffffL\n#define BIT_MCU_RSVD_2(x) (((x) & BIT_MASK_MCU_RSVD_2) << BIT_SHIFT_MCU_RSVD_2)\n#define BITS_MCU_RSVD_2 (BIT_MASK_MCU_RSVD_2 << BIT_SHIFT_MCU_RSVD_2)\n#define BIT_CLEAR_MCU_RSVD_2(x) ((x) & (~BITS_MCU_RSVD_2))\n#define BIT_GET_MCU_RSVD_2(x)                                                  \\\n\t(((x) >> BIT_SHIFT_MCU_RSVD_2) & BIT_MASK_MCU_RSVD_2)\n#define BIT_SET_MCU_RSVD_2(x, v) (BIT_CLEAR_MCU_RSVD_2(x) | BIT_MCU_RSVD_2(v))\n\n#define BIT_SHIFT_WKFCAM_NUM 0\n#define BIT_MASK_WKFCAM_NUM 0x7f\n#define BIT_WKFCAM_NUM(x) (((x) & BIT_MASK_WKFCAM_NUM) << BIT_SHIFT_WKFCAM_NUM)\n#define BITS_WKFCAM_NUM (BIT_MASK_WKFCAM_NUM << BIT_SHIFT_WKFCAM_NUM)\n#define BIT_CLEAR_WKFCAM_NUM(x) ((x) & (~BITS_WKFCAM_NUM))\n#define BIT_GET_WKFCAM_NUM(x)                                                  \\\n\t(((x) >> BIT_SHIFT_WKFCAM_NUM) & BIT_MASK_WKFCAM_NUM)\n#define BIT_SET_WKFCAM_NUM(x, v) (BIT_CLEAR_WKFCAM_NUM(x) | BIT_WKFCAM_NUM(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_STMP_THSD\t\t\t\t(Offset 0x0634) */\n\n#define BIT_SHIFT_STMP_THSD 0\n#define BIT_MASK_STMP_THSD 0xff\n#define BIT_STMP_THSD(x) (((x) & BIT_MASK_STMP_THSD) << BIT_SHIFT_STMP_THSD)\n#define BITS_STMP_THSD (BIT_MASK_STMP_THSD << BIT_SHIFT_STMP_THSD)\n#define BIT_CLEAR_STMP_THSD(x) ((x) & (~BITS_STMP_THSD))\n#define BIT_GET_STMP_THSD(x) (((x) >> BIT_SHIFT_STMP_THSD) & BIT_MASK_STMP_THSD)\n#define BIT_SET_STMP_THSD(x, v) (BIT_CLEAR_STMP_THSD(x) | BIT_STMP_THSD(v))\n\n/* 2 REG_WMAC_TXTIMEOUT\t\t\t(Offset 0x0635) */\n\n#define BIT_SHIFT_WMAC_TXTIMEOUT 0\n#define BIT_MASK_WMAC_TXTIMEOUT 0xff\n#define BIT_WMAC_TXTIMEOUT(x)                                                  \\\n\t(((x) & BIT_MASK_WMAC_TXTIMEOUT) << BIT_SHIFT_WMAC_TXTIMEOUT)\n#define BITS_WMAC_TXTIMEOUT                                                    \\\n\t(BIT_MASK_WMAC_TXTIMEOUT << BIT_SHIFT_WMAC_TXTIMEOUT)\n#define BIT_CLEAR_WMAC_TXTIMEOUT(x) ((x) & (~BITS_WMAC_TXTIMEOUT))\n#define BIT_GET_WMAC_TXTIMEOUT(x)                                              \\\n\t(((x) >> BIT_SHIFT_WMAC_TXTIMEOUT) & BIT_MASK_WMAC_TXTIMEOUT)\n#define BIT_SET_WMAC_TXTIMEOUT(x, v)                                           \\\n\t(BIT_CLEAR_WMAC_TXTIMEOUT(x) | BIT_WMAC_TXTIMEOUT(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_MCU_TEST_2_V1\t\t\t(Offset 0x0636) */\n\n#define BIT_SHIFT_MCU_RSVD_2_V1 0\n#define BIT_MASK_MCU_RSVD_2_V1 0xffff\n#define BIT_MCU_RSVD_2_V1(x)                                                   \\\n\t(((x) & BIT_MASK_MCU_RSVD_2_V1) << BIT_SHIFT_MCU_RSVD_2_V1)\n#define BITS_MCU_RSVD_2_V1 (BIT_MASK_MCU_RSVD_2_V1 << BIT_SHIFT_MCU_RSVD_2_V1)\n#define BIT_CLEAR_MCU_RSVD_2_V1(x) ((x) & (~BITS_MCU_RSVD_2_V1))\n#define BIT_GET_MCU_RSVD_2_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_MCU_RSVD_2_V1) & BIT_MASK_MCU_RSVD_2_V1)\n#define BIT_SET_MCU_RSVD_2_V1(x, v)                                            \\\n\t(BIT_CLEAR_MCU_RSVD_2_V1(x) | BIT_MCU_RSVD_2_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_USTIME_EDCA\t\t\t\t(Offset 0x0638) */\n\n#define BIT_SHIFT_USTIME_EDCA 0\n#define BIT_MASK_USTIME_EDCA 0xff\n#define BIT_USTIME_EDCA(x)                                                     \\\n\t(((x) & BIT_MASK_USTIME_EDCA) << BIT_SHIFT_USTIME_EDCA)\n#define BITS_USTIME_EDCA (BIT_MASK_USTIME_EDCA << BIT_SHIFT_USTIME_EDCA)\n#define BIT_CLEAR_USTIME_EDCA(x) ((x) & (~BITS_USTIME_EDCA))\n#define BIT_GET_USTIME_EDCA(x)                                                 \\\n\t(((x) >> BIT_SHIFT_USTIME_EDCA) & BIT_MASK_USTIME_EDCA)\n#define BIT_SET_USTIME_EDCA(x, v)                                              \\\n\t(BIT_CLEAR_USTIME_EDCA(x) | BIT_USTIME_EDCA(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_USTIME_EDCA\t\t\t\t(Offset 0x0638) */\n\n#define BIT_SHIFT_USTIME 0\n#define BIT_MASK_USTIME 0xff\n#define BIT_USTIME(x) (((x) & BIT_MASK_USTIME) << BIT_SHIFT_USTIME)\n#define BITS_USTIME (BIT_MASK_USTIME << BIT_SHIFT_USTIME)\n#define BIT_CLEAR_USTIME(x) ((x) & (~BITS_USTIME))\n#define BIT_GET_USTIME(x) (((x) >> BIT_SHIFT_USTIME) & BIT_MASK_USTIME)\n#define BIT_SET_USTIME(x, v) (BIT_CLEAR_USTIME(x) | BIT_USTIME(v))\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_USTIME_EDCA\t\t\t\t(Offset 0x0638) */\n\n#define BIT_SHIFT_USTIME_EDCA_V1 0\n#define BIT_MASK_USTIME_EDCA_V1 0x1ff\n#define BIT_USTIME_EDCA_V1(x)                                                  \\\n\t(((x) & BIT_MASK_USTIME_EDCA_V1) << BIT_SHIFT_USTIME_EDCA_V1)\n#define BITS_USTIME_EDCA_V1                                                    \\\n\t(BIT_MASK_USTIME_EDCA_V1 << BIT_SHIFT_USTIME_EDCA_V1)\n#define BIT_CLEAR_USTIME_EDCA_V1(x) ((x) & (~BITS_USTIME_EDCA_V1))\n#define BIT_GET_USTIME_EDCA_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_USTIME_EDCA_V1) & BIT_MASK_USTIME_EDCA_V1)\n#define BIT_SET_USTIME_EDCA_V1(x, v)                                           \\\n\t(BIT_CLEAR_USTIME_EDCA_V1(x) | BIT_USTIME_EDCA_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ACKTO_CCK\t\t\t\t(Offset 0x0639) */\n\n#define BIT_SHIFT_ACKTO_CCK 0\n#define BIT_MASK_ACKTO_CCK 0xff\n#define BIT_ACKTO_CCK(x) (((x) & BIT_MASK_ACKTO_CCK) << BIT_SHIFT_ACKTO_CCK)\n#define BITS_ACKTO_CCK (BIT_MASK_ACKTO_CCK << BIT_SHIFT_ACKTO_CCK)\n#define BIT_CLEAR_ACKTO_CCK(x) ((x) & (~BITS_ACKTO_CCK))\n#define BIT_GET_ACKTO_CCK(x) (((x) >> BIT_SHIFT_ACKTO_CCK) & BIT_MASK_ACKTO_CCK)\n#define BIT_SET_ACKTO_CCK(x, v) (BIT_CLEAR_ACKTO_CCK(x) | BIT_ACKTO_CCK(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MAC_SPEC_SIFS\t\t\t(Offset 0x063A) */\n\n#define BIT_SHIFT_SPEC_SIFS_OFDM 8\n#define BIT_MASK_SPEC_SIFS_OFDM 0xff\n#define BIT_SPEC_SIFS_OFDM(x)                                                  \\\n\t(((x) & BIT_MASK_SPEC_SIFS_OFDM) << BIT_SHIFT_SPEC_SIFS_OFDM)\n#define BITS_SPEC_SIFS_OFDM                                                    \\\n\t(BIT_MASK_SPEC_SIFS_OFDM << BIT_SHIFT_SPEC_SIFS_OFDM)\n#define BIT_CLEAR_SPEC_SIFS_OFDM(x) ((x) & (~BITS_SPEC_SIFS_OFDM))\n#define BIT_GET_SPEC_SIFS_OFDM(x)                                              \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM) & BIT_MASK_SPEC_SIFS_OFDM)\n#define BIT_SET_SPEC_SIFS_OFDM(x, v)                                           \\\n\t(BIT_CLEAR_SPEC_SIFS_OFDM(x) | BIT_SPEC_SIFS_OFDM(v))\n\n#define BIT_SHIFT_SPEC_SIFS_CCK 0\n#define BIT_MASK_SPEC_SIFS_CCK 0xff\n#define BIT_SPEC_SIFS_CCK(x)                                                   \\\n\t(((x) & BIT_MASK_SPEC_SIFS_CCK) << BIT_SHIFT_SPEC_SIFS_CCK)\n#define BITS_SPEC_SIFS_CCK (BIT_MASK_SPEC_SIFS_CCK << BIT_SHIFT_SPEC_SIFS_CCK)\n#define BIT_CLEAR_SPEC_SIFS_CCK(x) ((x) & (~BITS_SPEC_SIFS_CCK))\n#define BIT_GET_SPEC_SIFS_CCK(x)                                               \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_CCK) & BIT_MASK_SPEC_SIFS_CCK)\n#define BIT_SET_SPEC_SIFS_CCK(x, v)                                            \\\n\t(BIT_CLEAR_SPEC_SIFS_CCK(x) | BIT_SPEC_SIFS_CCK(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RESP_SIFS_CCK\t\t\t(Offset 0x063C) */\n\n#define BIT_SHIFT_SIFS_R2T_CCK 8\n#define BIT_MASK_SIFS_R2T_CCK 0xff\n#define BIT_SIFS_R2T_CCK(x)                                                    \\\n\t(((x) & BIT_MASK_SIFS_R2T_CCK) << BIT_SHIFT_SIFS_R2T_CCK)\n#define BITS_SIFS_R2T_CCK (BIT_MASK_SIFS_R2T_CCK << BIT_SHIFT_SIFS_R2T_CCK)\n#define BIT_CLEAR_SIFS_R2T_CCK(x) ((x) & (~BITS_SIFS_R2T_CCK))\n#define BIT_GET_SIFS_R2T_CCK(x)                                                \\\n\t(((x) >> BIT_SHIFT_SIFS_R2T_CCK) & BIT_MASK_SIFS_R2T_CCK)\n#define BIT_SET_SIFS_R2T_CCK(x, v)                                             \\\n\t(BIT_CLEAR_SIFS_R2T_CCK(x) | BIT_SIFS_R2T_CCK(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RESP_SIFS_CCK\t\t\t(Offset 0x063C) */\n\n#define BIT_SHIFT_R2T_SIFS_CCK 8\n#define BIT_MASK_R2T_SIFS_CCK 0xff\n#define BIT_R2T_SIFS_CCK(x)                                                    \\\n\t(((x) & BIT_MASK_R2T_SIFS_CCK) << BIT_SHIFT_R2T_SIFS_CCK)\n#define BITS_R2T_SIFS_CCK (BIT_MASK_R2T_SIFS_CCK << BIT_SHIFT_R2T_SIFS_CCK)\n#define BIT_CLEAR_R2T_SIFS_CCK(x) ((x) & (~BITS_R2T_SIFS_CCK))\n#define BIT_GET_R2T_SIFS_CCK(x)                                                \\\n\t(((x) >> BIT_SHIFT_R2T_SIFS_CCK) & BIT_MASK_R2T_SIFS_CCK)\n#define BIT_SET_R2T_SIFS_CCK(x, v)                                             \\\n\t(BIT_CLEAR_R2T_SIFS_CCK(x) | BIT_R2T_SIFS_CCK(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RESP_SIFS_CCK\t\t\t(Offset 0x063C) */\n\n#define BIT_SHIFT_SIFS_T2T_CCK 0\n#define BIT_MASK_SIFS_T2T_CCK 0xff\n#define BIT_SIFS_T2T_CCK(x)                                                    \\\n\t(((x) & BIT_MASK_SIFS_T2T_CCK) << BIT_SHIFT_SIFS_T2T_CCK)\n#define BITS_SIFS_T2T_CCK (BIT_MASK_SIFS_T2T_CCK << BIT_SHIFT_SIFS_T2T_CCK)\n#define BIT_CLEAR_SIFS_T2T_CCK(x) ((x) & (~BITS_SIFS_T2T_CCK))\n#define BIT_GET_SIFS_T2T_CCK(x)                                                \\\n\t(((x) >> BIT_SHIFT_SIFS_T2T_CCK) & BIT_MASK_SIFS_T2T_CCK)\n#define BIT_SET_SIFS_T2T_CCK(x, v)                                             \\\n\t(BIT_CLEAR_SIFS_T2T_CCK(x) | BIT_SIFS_T2T_CCK(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RESP_SIFS_CCK\t\t\t(Offset 0x063C) */\n\n#define BIT_SHIFT_T2T_SIFS_CCK 0\n#define BIT_MASK_T2T_SIFS_CCK 0xff\n#define BIT_T2T_SIFS_CCK(x)                                                    \\\n\t(((x) & BIT_MASK_T2T_SIFS_CCK) << BIT_SHIFT_T2T_SIFS_CCK)\n#define BITS_T2T_SIFS_CCK (BIT_MASK_T2T_SIFS_CCK << BIT_SHIFT_T2T_SIFS_CCK)\n#define BIT_CLEAR_T2T_SIFS_CCK(x) ((x) & (~BITS_T2T_SIFS_CCK))\n#define BIT_GET_T2T_SIFS_CCK(x)                                                \\\n\t(((x) >> BIT_SHIFT_T2T_SIFS_CCK) & BIT_MASK_T2T_SIFS_CCK)\n#define BIT_SET_T2T_SIFS_CCK(x, v)                                             \\\n\t(BIT_CLEAR_T2T_SIFS_CCK(x) | BIT_T2T_SIFS_CCK(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RESP_SIFS_OFDM\t\t\t(Offset 0x063E) */\n\n#define BIT_SHIFT_SIFS_R2T_OFDM 8\n#define BIT_MASK_SIFS_R2T_OFDM 0xff\n#define BIT_SIFS_R2T_OFDM(x)                                                   \\\n\t(((x) & BIT_MASK_SIFS_R2T_OFDM) << BIT_SHIFT_SIFS_R2T_OFDM)\n#define BITS_SIFS_R2T_OFDM (BIT_MASK_SIFS_R2T_OFDM << BIT_SHIFT_SIFS_R2T_OFDM)\n#define BIT_CLEAR_SIFS_R2T_OFDM(x) ((x) & (~BITS_SIFS_R2T_OFDM))\n#define BIT_GET_SIFS_R2T_OFDM(x)                                               \\\n\t(((x) >> BIT_SHIFT_SIFS_R2T_OFDM) & BIT_MASK_SIFS_R2T_OFDM)\n#define BIT_SET_SIFS_R2T_OFDM(x, v)                                            \\\n\t(BIT_CLEAR_SIFS_R2T_OFDM(x) | BIT_SIFS_R2T_OFDM(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RESP_SIFS_OFDM\t\t\t(Offset 0x063E) */\n\n#define BIT_SHIFT_R2T_SIFS_OFDM 8\n#define BIT_MASK_R2T_SIFS_OFDM 0xff\n#define BIT_R2T_SIFS_OFDM(x)                                                   \\\n\t(((x) & BIT_MASK_R2T_SIFS_OFDM) << BIT_SHIFT_R2T_SIFS_OFDM)\n#define BITS_R2T_SIFS_OFDM (BIT_MASK_R2T_SIFS_OFDM << BIT_SHIFT_R2T_SIFS_OFDM)\n#define BIT_CLEAR_R2T_SIFS_OFDM(x) ((x) & (~BITS_R2T_SIFS_OFDM))\n#define BIT_GET_R2T_SIFS_OFDM(x)                                               \\\n\t(((x) >> BIT_SHIFT_R2T_SIFS_OFDM) & BIT_MASK_R2T_SIFS_OFDM)\n#define BIT_SET_R2T_SIFS_OFDM(x, v)                                            \\\n\t(BIT_CLEAR_R2T_SIFS_OFDM(x) | BIT_R2T_SIFS_OFDM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RESP_SIFS_OFDM\t\t\t(Offset 0x063E) */\n\n#define BIT_SHIFT_SIFS_T2T_OFDM 0\n#define BIT_MASK_SIFS_T2T_OFDM 0xff\n#define BIT_SIFS_T2T_OFDM(x)                                                   \\\n\t(((x) & BIT_MASK_SIFS_T2T_OFDM) << BIT_SHIFT_SIFS_T2T_OFDM)\n#define BITS_SIFS_T2T_OFDM (BIT_MASK_SIFS_T2T_OFDM << BIT_SHIFT_SIFS_T2T_OFDM)\n#define BIT_CLEAR_SIFS_T2T_OFDM(x) ((x) & (~BITS_SIFS_T2T_OFDM))\n#define BIT_GET_SIFS_T2T_OFDM(x)                                               \\\n\t(((x) >> BIT_SHIFT_SIFS_T2T_OFDM) & BIT_MASK_SIFS_T2T_OFDM)\n#define BIT_SET_SIFS_T2T_OFDM(x, v)                                            \\\n\t(BIT_CLEAR_SIFS_T2T_OFDM(x) | BIT_SIFS_T2T_OFDM(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RESP_SIFS_OFDM\t\t\t(Offset 0x063E) */\n\n#define BIT_SHIFT_T2T_SIFS_OFDM 0\n#define BIT_MASK_T2T_SIFS_OFDM 0xff\n#define BIT_T2T_SIFS_OFDM(x)                                                   \\\n\t(((x) & BIT_MASK_T2T_SIFS_OFDM) << BIT_SHIFT_T2T_SIFS_OFDM)\n#define BITS_T2T_SIFS_OFDM (BIT_MASK_T2T_SIFS_OFDM << BIT_SHIFT_T2T_SIFS_OFDM)\n#define BIT_CLEAR_T2T_SIFS_OFDM(x) ((x) & (~BITS_T2T_SIFS_OFDM))\n#define BIT_GET_T2T_SIFS_OFDM(x)                                               \\\n\t(((x) >> BIT_SHIFT_T2T_SIFS_OFDM) & BIT_MASK_T2T_SIFS_OFDM)\n#define BIT_SET_T2T_SIFS_OFDM(x, v)                                            \\\n\t(BIT_CLEAR_T2T_SIFS_OFDM(x) | BIT_T2T_SIFS_OFDM(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ACKTO\t\t\t\t(Offset 0x0640) */\n\n#define BIT_SHIFT_ACKTO 0\n#define BIT_MASK_ACKTO 0xff\n#define BIT_ACKTO(x) (((x) & BIT_MASK_ACKTO) << BIT_SHIFT_ACKTO)\n#define BITS_ACKTO (BIT_MASK_ACKTO << BIT_SHIFT_ACKTO)\n#define BIT_CLEAR_ACKTO(x) ((x) & (~BITS_ACKTO))\n#define BIT_GET_ACKTO(x) (((x) >> BIT_SHIFT_ACKTO) & BIT_MASK_ACKTO)\n#define BIT_SET_ACKTO(x, v) (BIT_CLEAR_ACKTO(x) | BIT_ACKTO(v))\n\n/* 2 REG_CTS2TO\t\t\t\t(Offset 0x0641) */\n\n#define BIT_SHIFT_CTS2TO 0\n#define BIT_MASK_CTS2TO 0xff\n#define BIT_CTS2TO(x) (((x) & BIT_MASK_CTS2TO) << BIT_SHIFT_CTS2TO)\n#define BITS_CTS2TO (BIT_MASK_CTS2TO << BIT_SHIFT_CTS2TO)\n#define BIT_CLEAR_CTS2TO(x) ((x) & (~BITS_CTS2TO))\n#define BIT_GET_CTS2TO(x) (((x) >> BIT_SHIFT_CTS2TO) & BIT_MASK_CTS2TO)\n#define BIT_SET_CTS2TO(x, v) (BIT_CLEAR_CTS2TO(x) | BIT_CTS2TO(v))\n\n/* 2 REG_EIFS\t\t\t\t(Offset 0x0642) */\n\n#define BIT_SHIFT_EIFS 0\n#define BIT_MASK_EIFS 0xffff\n#define BIT_EIFS(x) (((x) & BIT_MASK_EIFS) << BIT_SHIFT_EIFS)\n#define BITS_EIFS (BIT_MASK_EIFS << BIT_SHIFT_EIFS)\n#define BIT_CLEAR_EIFS(x) ((x) & (~BITS_EIFS))\n#define BIT_GET_EIFS(x) (((x) >> BIT_SHIFT_EIFS) & BIT_MASK_EIFS)\n#define BIT_SET_EIFS(x, v) (BIT_CLEAR_EIFS(x) | BIT_EIFS(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RPFM_MAP0\t\t\t\t(Offset 0x0644) */\n\n#define BIT_MGT_RPFM15EN BIT(15)\n#define BIT_MGT_RPFM14EN BIT(14)\n#define BIT_MGT_RPFM13EN BIT(13)\n#define BIT_MGT_RPFM12EN BIT(12)\n#define BIT_MGT_RPFM11EN BIT(11)\n#define BIT_MGT_RPFM10EN BIT(10)\n#define BIT_MGT_RPFM9EN BIT(9)\n#define BIT_MGT_RPFM8EN BIT(8)\n#define BIT_MGT_RPFM7EN BIT(7)\n#define BIT_MGT_RPFM6EN BIT(6)\n#define BIT_MGT_RPFM5EN BIT(5)\n#define BIT_MGT_RPFM4EN BIT(4)\n#define BIT_MGT_RPFM3EN BIT(3)\n#define BIT_MGT_RPFM2EN BIT(2)\n#define BIT_MGT_RPFM1EN BIT(1)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RPFM_MAP0\t\t\t\t(Offset 0x0644) */\n\n#define BIT_SHIFT_RPFM_MAP0 0\n#define BIT_MASK_RPFM_MAP0 0xffff\n#define BIT_RPFM_MAP0(x) (((x) & BIT_MASK_RPFM_MAP0) << BIT_SHIFT_RPFM_MAP0)\n#define BITS_RPFM_MAP0 (BIT_MASK_RPFM_MAP0 << BIT_SHIFT_RPFM_MAP0)\n#define BIT_CLEAR_RPFM_MAP0(x) ((x) & (~BITS_RPFM_MAP0))\n#define BIT_GET_RPFM_MAP0(x) (((x) >> BIT_SHIFT_RPFM_MAP0) & BIT_MASK_RPFM_MAP0)\n#define BIT_SET_RPFM_MAP0(x, v) (BIT_CLEAR_RPFM_MAP0(x) | BIT_RPFM_MAP0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RPFM_MAP0\t\t\t\t(Offset 0x0644) */\n\n#define BIT_MGT_RPFM0EN BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RPFM_MAP1_V1\t\t\t(Offset 0x0646) */\n\n#define BIT_DATA_RPFM15EN BIT(15)\n#define BIT_DATA_RPFM14EN BIT(14)\n#define BIT_DATA_RPFM13EN BIT(13)\n#define BIT_DATA_RPFM12EN BIT(12)\n#define BIT_DATA_RPFM11EN BIT(11)\n#define BIT_DATA_RPFM10EN BIT(10)\n#define BIT_DATA_RPFM9EN BIT(9)\n#define BIT_DATA_RPFM8EN BIT(8)\n#define BIT_DATA_RPFM7EN BIT(7)\n#define BIT_DATA_RPFM6EN BIT(6)\n#define BIT_DATA_RPFM5EN BIT(5)\n#define BIT_DATA_RPFM4EN BIT(4)\n#define BIT_DATA_RPFM3EN BIT(3)\n#define BIT_DATA_RPFM2EN BIT(2)\n#define BIT_DATA_RPFM1EN BIT(1)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RPFM_MAP1\t\t\t\t(Offset 0x0646) */\n\n#define BIT_SHIFT_RPFM_MAP1 0\n#define BIT_MASK_RPFM_MAP1 0xffff\n#define BIT_RPFM_MAP1(x) (((x) & BIT_MASK_RPFM_MAP1) << BIT_SHIFT_RPFM_MAP1)\n#define BITS_RPFM_MAP1 (BIT_MASK_RPFM_MAP1 << BIT_SHIFT_RPFM_MAP1)\n#define BIT_CLEAR_RPFM_MAP1(x) ((x) & (~BITS_RPFM_MAP1))\n#define BIT_GET_RPFM_MAP1(x) (((x) >> BIT_SHIFT_RPFM_MAP1) & BIT_MASK_RPFM_MAP1)\n#define BIT_SET_RPFM_MAP1(x, v) (BIT_CLEAR_RPFM_MAP1(x) | BIT_RPFM_MAP1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RPFM_MAP1_V1\t\t\t(Offset 0x0646) */\n\n#define BIT_DATA_RPFM0EN BIT(0)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RPFM_CAM_CMD\t\t\t(Offset 0x0648) */\n\n#define BIT_RPFM_CAM_POLLING BIT(31)\n#define BIT_RPFM_CAM_CLR BIT(30)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RPFM_CAM_CMD\t\t\t(Offset 0x0648) */\n\n#define BIT_RPFM_CAM_WR BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RPFM_CAM_CMD\t\t\t(Offset 0x0648) */\n\n#define BIT_RPFM_CAM_WE BIT(16)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RPFM_CAM_CMD\t\t\t(Offset 0x0648) */\n\n#define BIT_SHIFT_RPFM_CAM_ADDR 0\n#define BIT_MASK_RPFM_CAM_ADDR 0x7f\n#define BIT_RPFM_CAM_ADDR(x)                                                   \\\n\t(((x) & BIT_MASK_RPFM_CAM_ADDR) << BIT_SHIFT_RPFM_CAM_ADDR)\n#define BITS_RPFM_CAM_ADDR (BIT_MASK_RPFM_CAM_ADDR << BIT_SHIFT_RPFM_CAM_ADDR)\n#define BIT_CLEAR_RPFM_CAM_ADDR(x) ((x) & (~BITS_RPFM_CAM_ADDR))\n#define BIT_GET_RPFM_CAM_ADDR(x)                                               \\\n\t(((x) >> BIT_SHIFT_RPFM_CAM_ADDR) & BIT_MASK_RPFM_CAM_ADDR)\n#define BIT_SET_RPFM_CAM_ADDR(x, v)                                            \\\n\t(BIT_CLEAR_RPFM_CAM_ADDR(x) | BIT_RPFM_CAM_ADDR(v))\n\n/* 2 REG_RPFM_CAM_RWD\t\t\t(Offset 0x064C) */\n\n#define BIT_SHIFT_RPFM_CAM_RWD 0\n#define BIT_MASK_RPFM_CAM_RWD 0xffffffffL\n#define BIT_RPFM_CAM_RWD(x)                                                    \\\n\t(((x) & BIT_MASK_RPFM_CAM_RWD) << BIT_SHIFT_RPFM_CAM_RWD)\n#define BITS_RPFM_CAM_RWD (BIT_MASK_RPFM_CAM_RWD << BIT_SHIFT_RPFM_CAM_RWD)\n#define BIT_CLEAR_RPFM_CAM_RWD(x) ((x) & (~BITS_RPFM_CAM_RWD))\n#define BIT_GET_RPFM_CAM_RWD(x)                                                \\\n\t(((x) >> BIT_SHIFT_RPFM_CAM_RWD) & BIT_MASK_RPFM_CAM_RWD)\n#define BIT_SET_RPFM_CAM_RWD(x, v)                                             \\\n\t(BIT_CLEAR_RPFM_CAM_RWD(x) | BIT_RPFM_CAM_RWD(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_NAV_CTRL\t\t\t\t(Offset 0x0650) */\n\n#define BIT_SHIFT_NAV_UPPER 16\n#define BIT_MASK_NAV_UPPER 0xff\n#define BIT_NAV_UPPER(x) (((x) & BIT_MASK_NAV_UPPER) << BIT_SHIFT_NAV_UPPER)\n#define BITS_NAV_UPPER (BIT_MASK_NAV_UPPER << BIT_SHIFT_NAV_UPPER)\n#define BIT_CLEAR_NAV_UPPER(x) ((x) & (~BITS_NAV_UPPER))\n#define BIT_GET_NAV_UPPER(x) (((x) >> BIT_SHIFT_NAV_UPPER) & BIT_MASK_NAV_UPPER)\n#define BIT_SET_NAV_UPPER(x, v) (BIT_CLEAR_NAV_UPPER(x) | BIT_NAV_UPPER(v))\n\n#define BIT_SHIFT_RXMYRTS_NAV 8\n#define BIT_MASK_RXMYRTS_NAV 0xf\n#define BIT_RXMYRTS_NAV(x)                                                     \\\n\t(((x) & BIT_MASK_RXMYRTS_NAV) << BIT_SHIFT_RXMYRTS_NAV)\n#define BITS_RXMYRTS_NAV (BIT_MASK_RXMYRTS_NAV << BIT_SHIFT_RXMYRTS_NAV)\n#define BIT_CLEAR_RXMYRTS_NAV(x) ((x) & (~BITS_RXMYRTS_NAV))\n#define BIT_GET_RXMYRTS_NAV(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RXMYRTS_NAV) & BIT_MASK_RXMYRTS_NAV)\n#define BIT_SET_RXMYRTS_NAV(x, v)                                              \\\n\t(BIT_CLEAR_RXMYRTS_NAV(x) | BIT_RXMYRTS_NAV(v))\n\n#define BIT_SHIFT_RTSRST 0\n#define BIT_MASK_RTSRST 0xff\n#define BIT_RTSRST(x) (((x) & BIT_MASK_RTSRST) << BIT_SHIFT_RTSRST)\n#define BITS_RTSRST (BIT_MASK_RTSRST << BIT_SHIFT_RTSRST)\n#define BIT_CLEAR_RTSRST(x) ((x) & (~BITS_RTSRST))\n#define BIT_GET_RTSRST(x) (((x) >> BIT_SHIFT_RTSRST) & BIT_MASK_RTSRST)\n#define BIT_SET_RTSRST(x, v) (BIT_CLEAR_RTSRST(x) | BIT_RTSRST(v))\n\n/* 2 REG_BACAMCMD\t\t\t\t(Offset 0x0654) */\n\n#define BIT_BACAM_POLL BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BACAMCMD\t\t\t\t(Offset 0x0654) */\n\n#define BIT_BACAM_RST BIT(17)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BACAMCMD\t\t\t\t(Offset 0x0654) */\n\n#define BIT_BACAM_RW BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BACAMCMD\t\t\t\t(Offset 0x0654) */\n\n#define BIT_SHIFT_TXSBM 14\n#define BIT_MASK_TXSBM 0x3\n#define BIT_TXSBM(x) (((x) & BIT_MASK_TXSBM) << BIT_SHIFT_TXSBM)\n#define BITS_TXSBM (BIT_MASK_TXSBM << BIT_SHIFT_TXSBM)\n#define BIT_CLEAR_TXSBM(x) ((x) & (~BITS_TXSBM))\n#define BIT_GET_TXSBM(x) (((x) >> BIT_SHIFT_TXSBM) & BIT_MASK_TXSBM)\n#define BIT_SET_TXSBM(x, v) (BIT_CLEAR_TXSBM(x) | BIT_TXSBM(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_BACAMCMD\t\t\t\t(Offset 0x0654) */\n\n#define BIT_SHIFT_TXSBMPMOD 14\n#define BIT_MASK_TXSBMPMOD 0x3\n#define BIT_TXSBMPMOD(x) (((x) & BIT_MASK_TXSBMPMOD) << BIT_SHIFT_TXSBMPMOD)\n#define BITS_TXSBMPMOD (BIT_MASK_TXSBMPMOD << BIT_SHIFT_TXSBMPMOD)\n#define BIT_CLEAR_TXSBMPMOD(x) ((x) & (~BITS_TXSBMPMOD))\n#define BIT_GET_TXSBMPMOD(x) (((x) >> BIT_SHIFT_TXSBMPMOD) & BIT_MASK_TXSBMPMOD)\n#define BIT_SET_TXSBMPMOD(x, v) (BIT_CLEAR_TXSBMPMOD(x) | BIT_TXSBMPMOD(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BACAMCMD\t\t\t\t(Offset 0x0654) */\n\n#define BIT_SHIFT_BACAM_ADDR 0\n#define BIT_MASK_BACAM_ADDR 0x3f\n#define BIT_BACAM_ADDR(x) (((x) & BIT_MASK_BACAM_ADDR) << BIT_SHIFT_BACAM_ADDR)\n#define BITS_BACAM_ADDR (BIT_MASK_BACAM_ADDR << BIT_SHIFT_BACAM_ADDR)\n#define BIT_CLEAR_BACAM_ADDR(x) ((x) & (~BITS_BACAM_ADDR))\n#define BIT_GET_BACAM_ADDR(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BACAM_ADDR) & BIT_MASK_BACAM_ADDR)\n#define BIT_SET_BACAM_ADDR(x, v) (BIT_CLEAR_BACAM_ADDR(x) | BIT_BACAM_ADDR(v))\n\n#define BIT_SHIFT_BA_CONTENT_L 0\n#define BIT_MASK_BA_CONTENT_L 0xffffffffL\n#define BIT_BA_CONTENT_L(x)                                                    \\\n\t(((x) & BIT_MASK_BA_CONTENT_L) << BIT_SHIFT_BA_CONTENT_L)\n#define BITS_BA_CONTENT_L (BIT_MASK_BA_CONTENT_L << BIT_SHIFT_BA_CONTENT_L)\n#define BIT_CLEAR_BA_CONTENT_L(x) ((x) & (~BITS_BA_CONTENT_L))\n#define BIT_GET_BA_CONTENT_L(x)                                                \\\n\t(((x) >> BIT_SHIFT_BA_CONTENT_L) & BIT_MASK_BA_CONTENT_L)\n#define BIT_SET_BA_CONTENT_L(x, v)                                             \\\n\t(BIT_CLEAR_BA_CONTENT_L(x) | BIT_BA_CONTENT_L(v))\n\n#define BIT_SHIFT_LBDLY 0\n#define BIT_MASK_LBDLY 0x1f\n#define BIT_LBDLY(x) (((x) & BIT_MASK_LBDLY) << BIT_SHIFT_LBDLY)\n#define BITS_LBDLY (BIT_MASK_LBDLY << BIT_SHIFT_LBDLY)\n#define BIT_CLEAR_LBDLY(x) ((x) & (~BITS_LBDLY))\n#define BIT_GET_LBDLY(x) (((x) >> BIT_SHIFT_LBDLY) & BIT_MASK_LBDLY)\n#define BIT_SET_LBDLY(x, v) (BIT_CLEAR_LBDLY(x) | BIT_LBDLY(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_BITMAP_CMD\t\t\t\t(Offset 0x0661) */\n\n#define BIT_BACAM_RPMEN BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_BACAM_RPMEN\t\t\t(Offset 0x0661) */\n\n#define BIT_WMAC_BACAM_RPMEN BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TX_RX\t\t\t\t(Offset 0x0662) */\n\n#define BIT_SHIFT_RXPKT_TYPE 2\n#define BIT_MASK_RXPKT_TYPE 0x3f\n#define BIT_RXPKT_TYPE(x) (((x) & BIT_MASK_RXPKT_TYPE) << BIT_SHIFT_RXPKT_TYPE)\n#define BITS_RXPKT_TYPE (BIT_MASK_RXPKT_TYPE << BIT_SHIFT_RXPKT_TYPE)\n#define BIT_CLEAR_RXPKT_TYPE(x) ((x) & (~BITS_RXPKT_TYPE))\n#define BIT_GET_RXPKT_TYPE(x)                                                  \\\n\t(((x) >> BIT_SHIFT_RXPKT_TYPE) & BIT_MASK_RXPKT_TYPE)\n#define BIT_SET_RXPKT_TYPE(x, v) (BIT_CLEAR_RXPKT_TYPE(x) | BIT_RXPKT_TYPE(v))\n\n#define BIT_TXACT_IND BIT(1)\n#define BIT_RXACT_IND BIT(0)\n\n/* 2 REG_WMAC_BITMAP_CTL\t\t\t(Offset 0x0663) */\n\n#define BIT_BITMAP_VO BIT(7)\n#define BIT_BITMAP_VI BIT(6)\n#define BIT_BITMAP_BE BIT(5)\n#define BIT_BITMAP_BK BIT(4)\n\n#define BIT_SHIFT_BITMAP_CONDITION 2\n#define BIT_MASK_BITMAP_CONDITION 0x3\n#define BIT_BITMAP_CONDITION(x)                                                \\\n\t(((x) & BIT_MASK_BITMAP_CONDITION) << BIT_SHIFT_BITMAP_CONDITION)\n#define BITS_BITMAP_CONDITION                                                  \\\n\t(BIT_MASK_BITMAP_CONDITION << BIT_SHIFT_BITMAP_CONDITION)\n#define BIT_CLEAR_BITMAP_CONDITION(x) ((x) & (~BITS_BITMAP_CONDITION))\n#define BIT_GET_BITMAP_CONDITION(x)                                            \\\n\t(((x) >> BIT_SHIFT_BITMAP_CONDITION) & BIT_MASK_BITMAP_CONDITION)\n#define BIT_SET_BITMAP_CONDITION(x, v)                                         \\\n\t(BIT_CLEAR_BITMAP_CONDITION(x) | BIT_BITMAP_CONDITION(v))\n\n#define BIT_BITMAP_SSNBK_COUNTER_CLR BIT(1)\n#define BIT_BITMAP_FORCE BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXERR_RPT\t\t\t\t(Offset 0x0664) */\n\n#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0 28\n#define BIT_MASK_RXERR_RPT_SEL_V1_3_0 0xf\n#define BIT_RXERR_RPT_SEL_V1_3_0(x)                                            \\\n\t(((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0)                                 \\\n\t << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0)\n#define BITS_RXERR_RPT_SEL_V1_3_0                                              \\\n\t(BIT_MASK_RXERR_RPT_SEL_V1_3_0 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0)\n#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0(x) ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0))\n#define BIT_GET_RXERR_RPT_SEL_V1_3_0(x)                                        \\\n\t(((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) &                             \\\n\t BIT_MASK_RXERR_RPT_SEL_V1_3_0)\n#define BIT_SET_RXERR_RPT_SEL_V1_3_0(x, v)                                     \\\n\t(BIT_CLEAR_RXERR_RPT_SEL_V1_3_0(x) | BIT_RXERR_RPT_SEL_V1_3_0(v))\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXERR_RPT\t\t\t\t(Offset 0x0664) */\n\n#define BIT_SHIFT_RXERR_RPT_SEL 28\n#define BIT_MASK_RXERR_RPT_SEL 0xf\n#define BIT_RXERR_RPT_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_RXERR_RPT_SEL) << BIT_SHIFT_RXERR_RPT_SEL)\n#define BITS_RXERR_RPT_SEL (BIT_MASK_RXERR_RPT_SEL << BIT_SHIFT_RXERR_RPT_SEL)\n#define BIT_CLEAR_RXERR_RPT_SEL(x) ((x) & (~BITS_RXERR_RPT_SEL))\n#define BIT_GET_RXERR_RPT_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_RXERR_RPT_SEL) & BIT_MASK_RXERR_RPT_SEL)\n#define BIT_SET_RXERR_RPT_SEL(x, v)                                            \\\n\t(BIT_CLEAR_RXERR_RPT_SEL(x) | BIT_RXERR_RPT_SEL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXERR_RPT\t\t\t\t(Offset 0x0664) */\n\n#define BIT_RXERR_RPT_RST BIT(27)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXERR_RPT\t\t\t\t(Offset 0x0664) */\n\n#define BIT_RXERR_RPT_SEL_V1_4 BIT(26)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXERR_RPT\t\t\t\t(Offset 0x0664) */\n\n#define BIT_SHIFT_UD_SELECT_BSSID_2_1 24\n#define BIT_MASK_UD_SELECT_BSSID_2_1 0x3\n#define BIT_UD_SELECT_BSSID_2_1(x)                                             \\\n\t(((x) & BIT_MASK_UD_SELECT_BSSID_2_1) << BIT_SHIFT_UD_SELECT_BSSID_2_1)\n#define BITS_UD_SELECT_BSSID_2_1                                               \\\n\t(BIT_MASK_UD_SELECT_BSSID_2_1 << BIT_SHIFT_UD_SELECT_BSSID_2_1)\n#define BIT_CLEAR_UD_SELECT_BSSID_2_1(x) ((x) & (~BITS_UD_SELECT_BSSID_2_1))\n#define BIT_GET_UD_SELECT_BSSID_2_1(x)                                         \\\n\t(((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1) & BIT_MASK_UD_SELECT_BSSID_2_1)\n#define BIT_SET_UD_SELECT_BSSID_2_1(x, v)                                      \\\n\t(BIT_CLEAR_UD_SELECT_BSSID_2_1(x) | BIT_UD_SELECT_BSSID_2_1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXERR_RPT\t\t\t\t(Offset 0x0664) */\n\n#define BIT_W1S BIT(23)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXERR_RPT\t\t\t\t(Offset 0x0664) */\n\n#define BIT_UD_SELECT_BSSID BIT(22)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXERR_RPT\t\t\t\t(Offset 0x0664) */\n\n#define BIT_UD_SELECT_BSSID_0 BIT(22)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXERR_RPT\t\t\t\t(Offset 0x0664) */\n\n#define BIT_SHIFT_UD_SUB_TYPE 18\n#define BIT_MASK_UD_SUB_TYPE 0xf\n#define BIT_UD_SUB_TYPE(x)                                                     \\\n\t(((x) & BIT_MASK_UD_SUB_TYPE) << BIT_SHIFT_UD_SUB_TYPE)\n#define BITS_UD_SUB_TYPE (BIT_MASK_UD_SUB_TYPE << BIT_SHIFT_UD_SUB_TYPE)\n#define BIT_CLEAR_UD_SUB_TYPE(x) ((x) & (~BITS_UD_SUB_TYPE))\n#define BIT_GET_UD_SUB_TYPE(x)                                                 \\\n\t(((x) >> BIT_SHIFT_UD_SUB_TYPE) & BIT_MASK_UD_SUB_TYPE)\n#define BIT_SET_UD_SUB_TYPE(x, v)                                              \\\n\t(BIT_CLEAR_UD_SUB_TYPE(x) | BIT_UD_SUB_TYPE(v))\n\n#define BIT_SHIFT_UD_TYPE 16\n#define BIT_MASK_UD_TYPE 0x3\n#define BIT_UD_TYPE(x) (((x) & BIT_MASK_UD_TYPE) << BIT_SHIFT_UD_TYPE)\n#define BITS_UD_TYPE (BIT_MASK_UD_TYPE << BIT_SHIFT_UD_TYPE)\n#define BIT_CLEAR_UD_TYPE(x) ((x) & (~BITS_UD_TYPE))\n#define BIT_GET_UD_TYPE(x) (((x) >> BIT_SHIFT_UD_TYPE) & BIT_MASK_UD_TYPE)\n#define BIT_SET_UD_TYPE(x, v) (BIT_CLEAR_UD_TYPE(x) | BIT_UD_TYPE(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXERR_RPT\t\t\t\t(Offset 0x0664) */\n\n#define BIT_CTRLFLT5EN BIT(5)\n#define BIT_CTRLFLT4EN BIT(4)\n#define BIT_CTRLFLT3EN BIT(3)\n#define BIT_CTRLFLT2EN BIT(2)\n#define BIT_CTRLFLT1EN BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_RXERR_RPT\t\t\t\t(Offset 0x0664) */\n\n#define BIT_SHIFT_RPT_COUNTER 0\n#define BIT_MASK_RPT_COUNTER 0xffff\n#define BIT_RPT_COUNTER(x)                                                     \\\n\t(((x) & BIT_MASK_RPT_COUNTER) << BIT_SHIFT_RPT_COUNTER)\n#define BITS_RPT_COUNTER (BIT_MASK_RPT_COUNTER << BIT_SHIFT_RPT_COUNTER)\n#define BIT_CLEAR_RPT_COUNTER(x) ((x) & (~BITS_RPT_COUNTER))\n#define BIT_GET_RPT_COUNTER(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RPT_COUNTER) & BIT_MASK_RPT_COUNTER)\n#define BIT_SET_RPT_COUNTER(x, v)                                              \\\n\t(BIT_CLEAR_RPT_COUNTER(x) | BIT_RPT_COUNTER(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXERR_RPT\t\t\t\t(Offset 0x0664) */\n\n#define BIT_CTRLFLT0EN BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_RXBA_IGNOREA2 BIT(42)\n#define BIT_EN_SAVE_ALL_TXOPADDR BIT(41)\n#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV BIT(40)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_DIS_TXBA_AMPDUFCSERR BIT(39)\n#define BIT_DIS_TXBA_RXBARINFULL BIT(38)\n#define BIT_DIS_TXCFE_INFULL BIT(37)\n#define BIT_DIS_TXCTS_INFULL BIT(36)\n#define BIT_EN_TXACKBA_IN_TX_RDG BIT(35)\n#define BIT_EN_TXACKBA_IN_TXOP BIT(34)\n#define BIT_EN_TXCTS_IN_RXNAV BIT(33)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_EN_TXCTS_INTXOP BIT(32)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_BLK_EDCA_BBSLP BIT(31)\n#define BIT_BLK_EDCA_BBSBY BIT(30)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_ENABLE_STOP_UPDATE_NAV_V1 BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_ACKTO_BLOCK_SCH_EN BIT(27)\n#define BIT_EIFS_BLOCK_SCH_EN BIT(26)\n#define BIT_PLCPCHK_RST_EIFS BIT(25)\n#define BIT_CCA_RST_EIFS BIT(24)\n#define BIT_DIS_UPD_MYRXPKTNAV BIT(23)\n#define BIT_EARLY_TXBA BIT(22)\n\n#define BIT_SHIFT_RESP_CHNBUSY 20\n#define BIT_MASK_RESP_CHNBUSY 0x3\n#define BIT_RESP_CHNBUSY(x)                                                    \\\n\t(((x) & BIT_MASK_RESP_CHNBUSY) << BIT_SHIFT_RESP_CHNBUSY)\n#define BITS_RESP_CHNBUSY (BIT_MASK_RESP_CHNBUSY << BIT_SHIFT_RESP_CHNBUSY)\n#define BIT_CLEAR_RESP_CHNBUSY(x) ((x) & (~BITS_RESP_CHNBUSY))\n#define BIT_GET_RESP_CHNBUSY(x)                                                \\\n\t(((x) >> BIT_SHIFT_RESP_CHNBUSY) & BIT_MASK_RESP_CHNBUSY)\n#define BIT_SET_RESP_CHNBUSY(x, v)                                             \\\n\t(BIT_CLEAR_RESP_CHNBUSY(x) | BIT_RESP_CHNBUSY(v))\n\n#define BIT_RESP_DCTS_EN BIT(19)\n#define BIT_RESP_DCFE_EN BIT(18)\n#define BIT_RESP_SPLCPEN BIT(17)\n#define BIT_RESP_SGIEN BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_RESP_LDPC_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_MGTFLT15EN BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_DIS_RESP_ACKINCCA BIT(14)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_MGTFLT14EN BIT(14)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_DIS_RESP_CTSINCCA BIT(13)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER 10\n#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER 0x7\n#define BIT_R_WMAC_SECOND_CCA_TIMER(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER)                              \\\n\t << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER)\n#define BITS_R_WMAC_SECOND_CCA_TIMER                                           \\\n\t(BIT_MASK_R_WMAC_SECOND_CCA_TIMER << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER)\n#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER(x)                                   \\\n\t((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER))\n#define BIT_GET_R_WMAC_SECOND_CCA_TIMER(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) &                          \\\n\t BIT_MASK_R_WMAC_SECOND_CCA_TIMER)\n#define BIT_SET_R_WMAC_SECOND_CCA_TIMER(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER(x) | BIT_R_WMAC_SECOND_CCA_TIMER(v))\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_SHIFT_SECOND_CCA_CNT 10\n#define BIT_MASK_SECOND_CCA_CNT 0x7\n#define BIT_SECOND_CCA_CNT(x)                                                  \\\n\t(((x) & BIT_MASK_SECOND_CCA_CNT) << BIT_SHIFT_SECOND_CCA_CNT)\n#define BITS_SECOND_CCA_CNT                                                    \\\n\t(BIT_MASK_SECOND_CCA_CNT << BIT_SHIFT_SECOND_CCA_CNT)\n#define BIT_CLEAR_SECOND_CCA_CNT(x) ((x) & (~BITS_SECOND_CCA_CNT))\n#define BIT_GET_SECOND_CCA_CNT(x)                                              \\\n\t(((x) >> BIT_SHIFT_SECOND_CCA_CNT) & BIT_MASK_SECOND_CCA_CNT)\n#define BIT_SET_SECOND_CCA_CNT(x, v)                                           \\\n\t(BIT_CLEAR_SECOND_CCA_CNT(x) | BIT_SECOND_CCA_CNT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_SHIFT_RFMOD 7\n#define BIT_MASK_RFMOD 0x3\n#define BIT_RFMOD(x) (((x) & BIT_MASK_RFMOD) << BIT_SHIFT_RFMOD)\n#define BITS_RFMOD (BIT_MASK_RFMOD << BIT_SHIFT_RFMOD)\n#define BIT_CLEAR_RFMOD(x) ((x) & (~BITS_RFMOD))\n#define BIT_GET_RFMOD(x) (((x) >> BIT_SHIFT_RFMOD) & BIT_MASK_RFMOD)\n#define BIT_SET_RFMOD(x, v) (BIT_CLEAR_RFMOD(x) | BIT_RFMOD(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_MGTFLT7EN BIT(7)\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_SHIFT_RF_MOD 7\n#define BIT_MASK_RF_MOD 0x3\n#define BIT_RF_MOD(x) (((x) & BIT_MASK_RF_MOD) << BIT_SHIFT_RF_MOD)\n#define BITS_RF_MOD (BIT_MASK_RF_MOD << BIT_SHIFT_RF_MOD)\n#define BIT_CLEAR_RF_MOD(x) ((x) & (~BITS_RF_MOD))\n#define BIT_GET_RF_MOD(x) (((x) >> BIT_SHIFT_RF_MOD) & BIT_MASK_RF_MOD)\n#define BIT_SET_RF_MOD(x, v) (BIT_CLEAR_RF_MOD(x) | BIT_RF_MOD(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_MGTFLT6EN BIT(6)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_SHIFT_RESP_CTS_DYNBW_SEL 5\n#define BIT_MASK_RESP_CTS_DYNBW_SEL 0x3\n#define BIT_RESP_CTS_DYNBW_SEL(x)                                              \\\n\t(((x) & BIT_MASK_RESP_CTS_DYNBW_SEL) << BIT_SHIFT_RESP_CTS_DYNBW_SEL)\n#define BITS_RESP_CTS_DYNBW_SEL                                                \\\n\t(BIT_MASK_RESP_CTS_DYNBW_SEL << BIT_SHIFT_RESP_CTS_DYNBW_SEL)\n#define BIT_CLEAR_RESP_CTS_DYNBW_SEL(x) ((x) & (~BITS_RESP_CTS_DYNBW_SEL))\n#define BIT_GET_RESP_CTS_DYNBW_SEL(x)                                          \\\n\t(((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL) & BIT_MASK_RESP_CTS_DYNBW_SEL)\n#define BIT_SET_RESP_CTS_DYNBW_SEL(x, v)                                       \\\n\t(BIT_CLEAR_RESP_CTS_DYNBW_SEL(x) | BIT_RESP_CTS_DYNBW_SEL(v))\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL 5\n#define BIT_MASK_RESP_CTS_BW_DYNBW_SEL 0x3\n#define BIT_RESP_CTS_BW_DYNBW_SEL(x)                                           \\\n\t(((x) & BIT_MASK_RESP_CTS_BW_DYNBW_SEL)                                \\\n\t << BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL)\n#define BITS_RESP_CTS_BW_DYNBW_SEL                                             \\\n\t(BIT_MASK_RESP_CTS_BW_DYNBW_SEL << BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL)\n#define BIT_CLEAR_RESP_CTS_BW_DYNBW_SEL(x) ((x) & (~BITS_RESP_CTS_BW_DYNBW_SEL))\n#define BIT_GET_RESP_CTS_BW_DYNBW_SEL(x)                                       \\\n\t(((x) >> BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL) &                            \\\n\t BIT_MASK_RESP_CTS_BW_DYNBW_SEL)\n#define BIT_SET_RESP_CTS_BW_DYNBW_SEL(x, v)                                    \\\n\t(BIT_CLEAR_RESP_CTS_BW_DYNBW_SEL(x) | BIT_RESP_CTS_BW_DYNBW_SEL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_DLY_TX_WAIT_RXANTSEL BIT(4)\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_DELAY_TX_USE_RX_ANTSEL BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_TXRESP_BY_RXANTSEL BIT(3)\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_TX_USE_RX_ANTSEL BIT(3)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_RESP_EARLY_TXACK_RWEPTKIP BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL\t\t\t(Offset 0x0668) */\n\n#define BIT_SHIFT_ORIG_DCTS_CHK 0\n#define BIT_MASK_ORIG_DCTS_CHK 0x3\n#define BIT_ORIG_DCTS_CHK(x)                                                   \\\n\t(((x) & BIT_MASK_ORIG_DCTS_CHK) << BIT_SHIFT_ORIG_DCTS_CHK)\n#define BITS_ORIG_DCTS_CHK (BIT_MASK_ORIG_DCTS_CHK << BIT_SHIFT_ORIG_DCTS_CHK)\n#define BIT_CLEAR_ORIG_DCTS_CHK(x) ((x) & (~BITS_ORIG_DCTS_CHK))\n#define BIT_GET_ORIG_DCTS_CHK(x)                                               \\\n\t(((x) >> BIT_SHIFT_ORIG_DCTS_CHK) & BIT_MASK_ORIG_DCTS_CHK)\n#define BIT_SET_ORIG_DCTS_CHK(x, v)                                            \\\n\t(BIT_CLEAR_ORIG_DCTS_CHK(x) | BIT_ORIG_DCTS_CHK(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_TRXPTCL_CTL_H\t\t\t(Offset 0x066C) */\n\n#define BIT_RXBA_IGNOREA2_V1 BIT(10)\n#define BIT_EN_SAVE_ALL_TXOPADDR_V1 BIT(9)\n#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1 BIT(8)\n#define BIT_DIS_TXBA_AMPDUFCSERR_V1 BIT(7)\n#define BIT_DIS_TXBA_RXBARINFULL_V1 BIT(6)\n#define BIT_DIS_TXCFE_INFULL_V1 BIT(5)\n#define BIT_DIS_TXCTS_INFULL_V1 BIT(4)\n#define BIT_EN_TXACKBA_IN_TX_RDG_V1 BIT(3)\n#define BIT_EN_TXACKBA_IN_TXOP_V1 BIT(2)\n#define BIT_EN_TXCTS_IN_RXNAV_V1 BIT(1)\n#define BIT_EN_TXCTS_INTXOP_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CAMCMD\t\t\t\t(Offset 0x0670) */\n\n#define BIT_SECCAM_POLLING BIT(31)\n#define BIT_SECCAM_CLR BIT(30)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CAMCMD\t\t\t\t(Offset 0x0670) */\n\n#define BIT_MFBCAM_CLR BIT(29)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CAMCMD\t\t\t\t(Offset 0x0670) */\n\n#define BIT_SECCAM_WE BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CAMCMD\t\t\t\t(Offset 0x0670) */\n\n#define BIT_SHIFT_SECCAM_ADDR_V1 0\n#define BIT_MASK_SECCAM_ADDR_V1 0xff\n#define BIT_SECCAM_ADDR_V1(x)                                                  \\\n\t(((x) & BIT_MASK_SECCAM_ADDR_V1) << BIT_SHIFT_SECCAM_ADDR_V1)\n#define BITS_SECCAM_ADDR_V1                                                    \\\n\t(BIT_MASK_SECCAM_ADDR_V1 << BIT_SHIFT_SECCAM_ADDR_V1)\n#define BIT_CLEAR_SECCAM_ADDR_V1(x) ((x) & (~BITS_SECCAM_ADDR_V1))\n#define BIT_GET_SECCAM_ADDR_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_SECCAM_ADDR_V1) & BIT_MASK_SECCAM_ADDR_V1)\n#define BIT_SET_SECCAM_ADDR_V1(x, v)                                           \\\n\t(BIT_CLEAR_SECCAM_ADDR_V1(x) | BIT_SECCAM_ADDR_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CAMCMD\t\t\t\t(Offset 0x0670) */\n\n#define BIT_SHIFT_SECCAM_ADDR_V2 0\n#define BIT_MASK_SECCAM_ADDR_V2 0x3ff\n#define BIT_SECCAM_ADDR_V2(x)                                                  \\\n\t(((x) & BIT_MASK_SECCAM_ADDR_V2) << BIT_SHIFT_SECCAM_ADDR_V2)\n#define BITS_SECCAM_ADDR_V2                                                    \\\n\t(BIT_MASK_SECCAM_ADDR_V2 << BIT_SHIFT_SECCAM_ADDR_V2)\n#define BIT_CLEAR_SECCAM_ADDR_V2(x) ((x) & (~BITS_SECCAM_ADDR_V2))\n#define BIT_GET_SECCAM_ADDR_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_SECCAM_ADDR_V2) & BIT_MASK_SECCAM_ADDR_V2)\n#define BIT_SET_SECCAM_ADDR_V2(x, v)                                           \\\n\t(BIT_CLEAR_SECCAM_ADDR_V2(x) | BIT_SECCAM_ADDR_V2(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_CAMCMD\t\t\t\t(Offset 0x0670) */\n\n#define BIT_SHIFT_SECCAM_ADDR_V3 0\n#define BIT_MASK_SECCAM_ADDR_V3 0x1ff\n#define BIT_SECCAM_ADDR_V3(x)                                                  \\\n\t(((x) & BIT_MASK_SECCAM_ADDR_V3) << BIT_SHIFT_SECCAM_ADDR_V3)\n#define BITS_SECCAM_ADDR_V3                                                    \\\n\t(BIT_MASK_SECCAM_ADDR_V3 << BIT_SHIFT_SECCAM_ADDR_V3)\n#define BIT_CLEAR_SECCAM_ADDR_V3(x) ((x) & (~BITS_SECCAM_ADDR_V3))\n#define BIT_GET_SECCAM_ADDR_V3(x)                                              \\\n\t(((x) >> BIT_SHIFT_SECCAM_ADDR_V3) & BIT_MASK_SECCAM_ADDR_V3)\n#define BIT_SET_SECCAM_ADDR_V3(x, v)                                           \\\n\t(BIT_CLEAR_SECCAM_ADDR_V3(x) | BIT_SECCAM_ADDR_V3(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_CAMCMD\t\t\t\t(Offset 0x0670) */\n\n#define BIT_SHIFT_SECCAM_ADDR 0\n#define BIT_MASK_SECCAM_ADDR 0xff\n#define BIT_SECCAM_ADDR(x)                                                     \\\n\t(((x) & BIT_MASK_SECCAM_ADDR) << BIT_SHIFT_SECCAM_ADDR)\n#define BITS_SECCAM_ADDR (BIT_MASK_SECCAM_ADDR << BIT_SHIFT_SECCAM_ADDR)\n#define BIT_CLEAR_SECCAM_ADDR(x) ((x) & (~BITS_SECCAM_ADDR))\n#define BIT_GET_SECCAM_ADDR(x)                                                 \\\n\t(((x) >> BIT_SHIFT_SECCAM_ADDR) & BIT_MASK_SECCAM_ADDR)\n#define BIT_SET_SECCAM_ADDR(x, v)                                              \\\n\t(BIT_CLEAR_SECCAM_ADDR(x) | BIT_SECCAM_ADDR(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CAMWRITE\t\t\t\t(Offset 0x0674) */\n\n#define BIT_SHIFT_CAMW_DATA 0\n#define BIT_MASK_CAMW_DATA 0xffffffffL\n#define BIT_CAMW_DATA(x) (((x) & BIT_MASK_CAMW_DATA) << BIT_SHIFT_CAMW_DATA)\n#define BITS_CAMW_DATA (BIT_MASK_CAMW_DATA << BIT_SHIFT_CAMW_DATA)\n#define BIT_CLEAR_CAMW_DATA(x) ((x) & (~BITS_CAMW_DATA))\n#define BIT_GET_CAMW_DATA(x) (((x) >> BIT_SHIFT_CAMW_DATA) & BIT_MASK_CAMW_DATA)\n#define BIT_SET_CAMW_DATA(x, v) (BIT_CLEAR_CAMW_DATA(x) | BIT_CAMW_DATA(v))\n\n/* 2 REG_CAMREAD\t\t\t\t(Offset 0x0678) */\n\n#define BIT_SHIFT_CAMR_DATA 0\n#define BIT_MASK_CAMR_DATA 0xffffffffL\n#define BIT_CAMR_DATA(x) (((x) & BIT_MASK_CAMR_DATA) << BIT_SHIFT_CAMR_DATA)\n#define BITS_CAMR_DATA (BIT_MASK_CAMR_DATA << BIT_SHIFT_CAMR_DATA)\n#define BIT_CLEAR_CAMR_DATA(x) ((x) & (~BITS_CAMR_DATA))\n#define BIT_GET_CAMR_DATA(x) (((x) >> BIT_SHIFT_CAMR_DATA) & BIT_MASK_CAMR_DATA)\n#define BIT_SET_CAMR_DATA(x, v) (BIT_CLEAR_CAMR_DATA(x) | BIT_CAMR_DATA(v))\n\n/* 2 REG_CAMDBG\t\t\t\t(Offset 0x067C) */\n\n#define BIT_SECCAM_INFO BIT(31)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_CAMDBG\t\t\t\t(Offset 0x067C) */\n\n#define BIT_SEC_KEYFOUND_V1 BIT(19)\n\n#define BIT_SHIFT_CAMDBG_SEC_TYPE_V1 16\n#define BIT_MASK_CAMDBG_SEC_TYPE_V1 0x7\n#define BIT_CAMDBG_SEC_TYPE_V1(x)                                              \\\n\t(((x) & BIT_MASK_CAMDBG_SEC_TYPE_V1) << BIT_SHIFT_CAMDBG_SEC_TYPE_V1)\n#define BITS_CAMDBG_SEC_TYPE_V1                                                \\\n\t(BIT_MASK_CAMDBG_SEC_TYPE_V1 << BIT_SHIFT_CAMDBG_SEC_TYPE_V1)\n#define BIT_CLEAR_CAMDBG_SEC_TYPE_V1(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_V1))\n#define BIT_GET_CAMDBG_SEC_TYPE_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_V1) & BIT_MASK_CAMDBG_SEC_TYPE_V1)\n#define BIT_SET_CAMDBG_SEC_TYPE_V1(x, v)                                       \\\n\t(BIT_CLEAR_CAMDBG_SEC_TYPE_V1(x) | BIT_CAMDBG_SEC_TYPE_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CAMDBG\t\t\t\t(Offset 0x067C) */\n\n#define BIT_SEC_KEYFOUND BIT(15)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_CAMDBG\t\t\t\t(Offset 0x067C) */\n\n#define BIT_EXT_SECTYPE BIT(15)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_CAMDBG\t\t\t\t(Offset 0x067C) */\n\n#define BIT_CAMDBG_EXT_SEC_TYPE_V1 BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CAMDBG\t\t\t\t(Offset 0x067C) */\n\n#define BIT_SHIFT_CAMDBG_SEC_TYPE 12\n#define BIT_MASK_CAMDBG_SEC_TYPE 0x7\n#define BIT_CAMDBG_SEC_TYPE(x)                                                 \\\n\t(((x) & BIT_MASK_CAMDBG_SEC_TYPE) << BIT_SHIFT_CAMDBG_SEC_TYPE)\n#define BITS_CAMDBG_SEC_TYPE                                                   \\\n\t(BIT_MASK_CAMDBG_SEC_TYPE << BIT_SHIFT_CAMDBG_SEC_TYPE)\n#define BIT_CLEAR_CAMDBG_SEC_TYPE(x) ((x) & (~BITS_CAMDBG_SEC_TYPE))\n#define BIT_GET_CAMDBG_SEC_TYPE(x)                                             \\\n\t(((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE) & BIT_MASK_CAMDBG_SEC_TYPE)\n#define BIT_SET_CAMDBG_SEC_TYPE(x, v)                                          \\\n\t(BIT_CLEAR_CAMDBG_SEC_TYPE(x) | BIT_CAMDBG_SEC_TYPE(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_CAMDBG\t\t\t\t(Offset 0x067C) */\n\n#define BIT_CAMDBG_EXT_SEC_TYPE BIT(11)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CAMDBG\t\t\t\t(Offset 0x067C) */\n\n#define BIT_CAMDBG_EXT_SECTYPE BIT(11)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_CAMDBG\t\t\t\t(Offset 0x067C) */\n\n#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1 7\n#define BIT_MASK_CAMDBG_MIC_KEY_IDX_V1 0x7f\n#define BIT_CAMDBG_MIC_KEY_IDX_V1(x)                                           \\\n\t(((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_V1)                                \\\n\t << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1)\n#define BITS_CAMDBG_MIC_KEY_IDX_V1                                             \\\n\t(BIT_MASK_CAMDBG_MIC_KEY_IDX_V1 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1)\n#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_V1(x) ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_V1))\n#define BIT_GET_CAMDBG_MIC_KEY_IDX_V1(x)                                       \\\n\t(((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1) &                            \\\n\t BIT_MASK_CAMDBG_MIC_KEY_IDX_V1)\n#define BIT_SET_CAMDBG_MIC_KEY_IDX_V1(x, v)                                    \\\n\t(BIT_CLEAR_CAMDBG_MIC_KEY_IDX_V1(x) | BIT_CAMDBG_MIC_KEY_IDX_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_CAMDBG\t\t\t\t(Offset 0x067C) */\n\n#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V3 6\n#define BIT_MASK_CAMDBG_MIC_KEY_IDX_V3 0x3f\n#define BIT_CAMDBG_MIC_KEY_IDX_V3(x)                                           \\\n\t(((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_V3)                                \\\n\t << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V3)\n#define BITS_CAMDBG_MIC_KEY_IDX_V3                                             \\\n\t(BIT_MASK_CAMDBG_MIC_KEY_IDX_V3 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V3)\n#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_V3(x) ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_V3))\n#define BIT_GET_CAMDBG_MIC_KEY_IDX_V3(x)                                       \\\n\t(((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V3) &                            \\\n\t BIT_MASK_CAMDBG_MIC_KEY_IDX_V3)\n#define BIT_SET_CAMDBG_MIC_KEY_IDX_V3(x, v)                                    \\\n\t(BIT_CLEAR_CAMDBG_MIC_KEY_IDX_V3(x) | BIT_CAMDBG_MIC_KEY_IDX_V3(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_CAMDBG\t\t\t\t(Offset 0x067C) */\n\n#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX 5\n#define BIT_MASK_CAMDBG_MIC_KEY_IDX 0x1f\n#define BIT_CAMDBG_MIC_KEY_IDX(x)                                              \\\n\t(((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX)\n#define BITS_CAMDBG_MIC_KEY_IDX                                                \\\n\t(BIT_MASK_CAMDBG_MIC_KEY_IDX << BIT_SHIFT_CAMDBG_MIC_KEY_IDX)\n#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX(x) ((x) & (~BITS_CAMDBG_MIC_KEY_IDX))\n#define BIT_GET_CAMDBG_MIC_KEY_IDX(x)                                          \\\n\t(((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX) & BIT_MASK_CAMDBG_MIC_KEY_IDX)\n#define BIT_SET_CAMDBG_MIC_KEY_IDX(x, v)                                       \\\n\t(BIT_CLEAR_CAMDBG_MIC_KEY_IDX(x) | BIT_CAMDBG_MIC_KEY_IDX(v))\n\n#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX 0\n#define BIT_MASK_CAMDBG_SEC_KEY_IDX 0x1f\n#define BIT_CAMDBG_SEC_KEY_IDX(x)                                              \\\n\t(((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX)\n#define BITS_CAMDBG_SEC_KEY_IDX                                                \\\n\t(BIT_MASK_CAMDBG_SEC_KEY_IDX << BIT_SHIFT_CAMDBG_SEC_KEY_IDX)\n#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX(x) ((x) & (~BITS_CAMDBG_SEC_KEY_IDX))\n#define BIT_GET_CAMDBG_SEC_KEY_IDX(x)                                          \\\n\t(((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX) & BIT_MASK_CAMDBG_SEC_KEY_IDX)\n#define BIT_SET_CAMDBG_SEC_KEY_IDX(x, v)                                       \\\n\t(BIT_CLEAR_CAMDBG_SEC_KEY_IDX(x) | BIT_CAMDBG_SEC_KEY_IDX(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_CAMDBG\t\t\t\t(Offset 0x067C) */\n\n#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V2 0\n#define BIT_MASK_CAMDBG_SEC_KEY_IDX_V2 0x3f\n#define BIT_CAMDBG_SEC_KEY_IDX_V2(x)                                           \\\n\t(((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_V2)                                \\\n\t << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V2)\n#define BITS_CAMDBG_SEC_KEY_IDX_V2                                             \\\n\t(BIT_MASK_CAMDBG_SEC_KEY_IDX_V2 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V2)\n#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_V2(x) ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_V2))\n#define BIT_GET_CAMDBG_SEC_KEY_IDX_V2(x)                                       \\\n\t(((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V2) &                            \\\n\t BIT_MASK_CAMDBG_SEC_KEY_IDX_V2)\n#define BIT_SET_CAMDBG_SEC_KEY_IDX_V2(x, v)                                    \\\n\t(BIT_CLEAR_CAMDBG_SEC_KEY_IDX_V2(x) | BIT_CAMDBG_SEC_KEY_IDX_V2(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_CAMDBG\t\t\t\t(Offset 0x067C) */\n\n#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1 0\n#define BIT_MASK_CAMDBG_SEC_KEY_IDX_V1 0x7f\n#define BIT_CAMDBG_SEC_KEY_IDX_V1(x)                                           \\\n\t(((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_V1)                                \\\n\t << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1)\n#define BITS_CAMDBG_SEC_KEY_IDX_V1                                             \\\n\t(BIT_MASK_CAMDBG_SEC_KEY_IDX_V1 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1)\n#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_V1(x) ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_V1))\n#define BIT_GET_CAMDBG_SEC_KEY_IDX_V1(x)                                       \\\n\t(((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1) &                            \\\n\t BIT_MASK_CAMDBG_SEC_KEY_IDX_V1)\n#define BIT_SET_CAMDBG_SEC_KEY_IDX_V1(x, v)                                    \\\n\t(BIT_CLEAR_CAMDBG_SEC_KEY_IDX_V1(x) | BIT_CAMDBG_SEC_KEY_IDX_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SECCFG\t\t\t\t(Offset 0x0680) */\n\n#define BIT_RXDEC_BM_MGNT_V1 BIT(19)\n#define BIT_TXENC_BM_MGNT_V1 BIT(18)\n#define BIT_RXDEC_UNI_MGNT_V1 BIT(17)\n#define BIT_TXENC_UNI_MGNT_V1 BIT(16)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SECCFG\t\t\t\t(Offset 0x0680) */\n\n#define BIT_DIS_GCLK_WAPI BIT(15)\n#define BIT_DIS_GCLK_AES BIT(14)\n#define BIT_DIS_GCLK_TKIP BIT(13)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SECCFG\t\t\t\t(Offset 0x0680) */\n\n#define BIT_AES_SEL_QC_1 BIT(12)\n#define BIT_AES_SEL_QC_0 BIT(11)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_SECCFG\t\t\t\t(Offset 0x0680) */\n\n#define BIT_WMAC_CKECK_BMC BIT(9)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SECCFG\t\t\t\t(Offset 0x0680) */\n\n#define BIT_CHK_BMC BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_SECCFG\t\t\t\t(Offset 0x0680) */\n\n#define BIT_CHK_KEYID BIT(8)\n#define BIT_RXBCUSEDK BIT(7)\n#define BIT_TXBCUSEDK BIT(6)\n#define BIT_NOSKMC BIT(5)\n#define BIT_SKBYA2 BIT(4)\n#define BIT_RXDEC BIT(3)\n#define BIT_TXENC BIT(2)\n#define BIT_RXUHUSEDK BIT(1)\n#define BIT_TXUHUSEDK BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXFILTER_CATEGORY_1\t\t\t(Offset 0x0682) */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_1 0\n#define BIT_MASK_RXFILTER_CATEGORY_1 0xff\n#define BIT_RXFILTER_CATEGORY_1(x)                                             \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_1) << BIT_SHIFT_RXFILTER_CATEGORY_1)\n#define BITS_RXFILTER_CATEGORY_1                                               \\\n\t(BIT_MASK_RXFILTER_CATEGORY_1 << BIT_SHIFT_RXFILTER_CATEGORY_1)\n#define BIT_CLEAR_RXFILTER_CATEGORY_1(x) ((x) & (~BITS_RXFILTER_CATEGORY_1))\n#define BIT_GET_RXFILTER_CATEGORY_1(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1) & BIT_MASK_RXFILTER_CATEGORY_1)\n#define BIT_SET_RXFILTER_CATEGORY_1(x, v)                                      \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_1(x) | BIT_RXFILTER_CATEGORY_1(v))\n\n/* 2 REG_RXFILTER_ACTION_1\t\t\t(Offset 0x0683) */\n\n#define BIT_SHIFT_RXFILTER_ACTION_1 0\n#define BIT_MASK_RXFILTER_ACTION_1 0xff\n#define BIT_RXFILTER_ACTION_1(x)                                               \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_1) << BIT_SHIFT_RXFILTER_ACTION_1)\n#define BITS_RXFILTER_ACTION_1                                                 \\\n\t(BIT_MASK_RXFILTER_ACTION_1 << BIT_SHIFT_RXFILTER_ACTION_1)\n#define BIT_CLEAR_RXFILTER_ACTION_1(x) ((x) & (~BITS_RXFILTER_ACTION_1))\n#define BIT_GET_RXFILTER_ACTION_1(x)                                           \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_1) & BIT_MASK_RXFILTER_ACTION_1)\n#define BIT_SET_RXFILTER_ACTION_1(x, v)                                        \\\n\t(BIT_CLEAR_RXFILTER_ACTION_1(x) | BIT_RXFILTER_ACTION_1(v))\n\n/* 2 REG_RXFILTER_CATEGORY_2\t\t\t(Offset 0x0684) */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_2 0\n#define BIT_MASK_RXFILTER_CATEGORY_2 0xff\n#define BIT_RXFILTER_CATEGORY_2(x)                                             \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_2) << BIT_SHIFT_RXFILTER_CATEGORY_2)\n#define BITS_RXFILTER_CATEGORY_2                                               \\\n\t(BIT_MASK_RXFILTER_CATEGORY_2 << BIT_SHIFT_RXFILTER_CATEGORY_2)\n#define BIT_CLEAR_RXFILTER_CATEGORY_2(x) ((x) & (~BITS_RXFILTER_CATEGORY_2))\n#define BIT_GET_RXFILTER_CATEGORY_2(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2) & BIT_MASK_RXFILTER_CATEGORY_2)\n#define BIT_SET_RXFILTER_CATEGORY_2(x, v)                                      \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_2(x) | BIT_RXFILTER_CATEGORY_2(v))\n\n/* 2 REG_RXFILTER_ACTION_2\t\t\t(Offset 0x0685) */\n\n#define BIT_SHIFT_RXFILTER_ACTION_2 0\n#define BIT_MASK_RXFILTER_ACTION_2 0xff\n#define BIT_RXFILTER_ACTION_2(x)                                               \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_2) << BIT_SHIFT_RXFILTER_ACTION_2)\n#define BITS_RXFILTER_ACTION_2                                                 \\\n\t(BIT_MASK_RXFILTER_ACTION_2 << BIT_SHIFT_RXFILTER_ACTION_2)\n#define BIT_CLEAR_RXFILTER_ACTION_2(x) ((x) & (~BITS_RXFILTER_ACTION_2))\n#define BIT_GET_RXFILTER_ACTION_2(x)                                           \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_2) & BIT_MASK_RXFILTER_ACTION_2)\n#define BIT_SET_RXFILTER_ACTION_2(x, v)                                        \\\n\t(BIT_CLEAR_RXFILTER_ACTION_2(x) | BIT_RXFILTER_ACTION_2(v))\n\n/* 2 REG_RXFILTER_CATEGORY_3\t\t\t(Offset 0x0686) */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_3 0\n#define BIT_MASK_RXFILTER_CATEGORY_3 0xff\n#define BIT_RXFILTER_CATEGORY_3(x)                                             \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_3) << BIT_SHIFT_RXFILTER_CATEGORY_3)\n#define BITS_RXFILTER_CATEGORY_3                                               \\\n\t(BIT_MASK_RXFILTER_CATEGORY_3 << BIT_SHIFT_RXFILTER_CATEGORY_3)\n#define BIT_CLEAR_RXFILTER_CATEGORY_3(x) ((x) & (~BITS_RXFILTER_CATEGORY_3))\n#define BIT_GET_RXFILTER_CATEGORY_3(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3) & BIT_MASK_RXFILTER_CATEGORY_3)\n#define BIT_SET_RXFILTER_CATEGORY_3(x, v)                                      \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_3(x) | BIT_RXFILTER_CATEGORY_3(v))\n\n/* 2 REG_RXFILTER_ACTION_3\t\t\t(Offset 0x0687) */\n\n#define BIT_SHIFT_RXFILTER_ACTION_3 0\n#define BIT_MASK_RXFILTER_ACTION_3 0xff\n#define BIT_RXFILTER_ACTION_3(x)                                               \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_3) << BIT_SHIFT_RXFILTER_ACTION_3)\n#define BITS_RXFILTER_ACTION_3                                                 \\\n\t(BIT_MASK_RXFILTER_ACTION_3 << BIT_SHIFT_RXFILTER_ACTION_3)\n#define BIT_CLEAR_RXFILTER_ACTION_3(x) ((x) & (~BITS_RXFILTER_ACTION_3))\n#define BIT_GET_RXFILTER_ACTION_3(x)                                           \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_3) & BIT_MASK_RXFILTER_ACTION_3)\n#define BIT_SET_RXFILTER_ACTION_3(x, v)                                        \\\n\t(BIT_CLEAR_RXFILTER_ACTION_3(x) | BIT_RXFILTER_ACTION_3(v))\n\n/* 2 REG_RXFLTMAP3\t\t\t\t(Offset 0x0688) */\n\n#define BIT_MGTFLT15EN_FW BIT(15)\n#define BIT_MGTFLT14EN_FW BIT(14)\n#define BIT_MGTFLT13EN_FW BIT(13)\n#define BIT_MGTFLT12EN_FW BIT(12)\n#define BIT_MGTFLT11EN_FW BIT(11)\n#define BIT_MGTFLT10EN_FW BIT(10)\n#define BIT_MGTFLT9EN_FW BIT(9)\n#define BIT_MGTFLT8EN_FW BIT(8)\n#define BIT_MGTFLT7EN_FW BIT(7)\n#define BIT_MGTFLT6EN_FW BIT(6)\n#define BIT_MGTFLT5EN_FW BIT(5)\n#define BIT_MGTFLT4EN_FW BIT(4)\n#define BIT_MGTFLT3EN_FW BIT(3)\n#define BIT_MGTFLT2EN_FW BIT(2)\n#define BIT_MGTFLT1EN_FW BIT(1)\n#define BIT_MGTFLT0EN_FW BIT(0)\n\n/* 2 REG_RXFLTMAP4\t\t\t\t(Offset 0x068A) */\n\n#define BIT_CTRLFLT15EN_FW BIT(15)\n#define BIT_CTRLFLT14EN_FW BIT(14)\n#define BIT_CTRLFLT13EN_FW BIT(13)\n#define BIT_CTRLFLT12EN_FW BIT(12)\n#define BIT_CTRLFLT11EN_FW BIT(11)\n#define BIT_CTRLFLT10EN_FW BIT(10)\n#define BIT_CTRLFLT9EN_FW BIT(9)\n#define BIT_CTRLFLT8EN_FW BIT(8)\n#define BIT_CTRLFLT7EN_FW BIT(7)\n#define BIT_CTRLFLT6EN_FW BIT(6)\n#define BIT_CTRLFLT5EN_FW BIT(5)\n#define BIT_CTRLFLT4EN_FW BIT(4)\n#define BIT_CTRLFLT3EN_FW BIT(3)\n#define BIT_CTRLFLT2EN_FW BIT(2)\n#define BIT_CTRLFLT1EN_FW BIT(1)\n#define BIT_CTRLFLT0EN_FW BIT(0)\n\n/* 2 REG_RXFLTMAP5\t\t\t\t(Offset 0x068C) */\n\n#define BIT_DATAFLT15EN_FW BIT(15)\n#define BIT_DATAFLT14EN_FW BIT(14)\n#define BIT_DATAFLT13EN_FW BIT(13)\n#define BIT_DATAFLT12EN_FW BIT(12)\n#define BIT_DATAFLT11EN_FW BIT(11)\n#define BIT_DATAFLT10EN_FW BIT(10)\n#define BIT_DATAFLT9EN_FW BIT(9)\n#define BIT_DATAFLT8EN_FW BIT(8)\n#define BIT_DATAFLT7EN_FW BIT(7)\n#define BIT_DATAFLT6EN_FW BIT(6)\n#define BIT_DATAFLT5EN_FW BIT(5)\n#define BIT_DATAFLT4EN_FW BIT(4)\n#define BIT_DATAFLT3EN_FW BIT(3)\n#define BIT_DATAFLT2EN_FW BIT(2)\n#define BIT_DATAFLT1EN_FW BIT(1)\n#define BIT_DATAFLT0EN_FW BIT(0)\n\n/* 2 REG_RXFLTMAP6\t\t\t\t(Offset 0x068E) */\n\n#define BIT_ACTIONFLT15EN_FW BIT(15)\n#define BIT_ACTIONFLT14EN_FW BIT(14)\n#define BIT_ACTIONFLT13EN_FW BIT(13)\n#define BIT_ACTIONFLT12EN_FW BIT(12)\n#define BIT_ACTIONFLT11EN_FW BIT(11)\n#define BIT_ACTIONFLT10EN_FW BIT(10)\n#define BIT_ACTIONFLT9EN_FW BIT(9)\n#define BIT_ACTIONFLT8EN_FW BIT(8)\n#define BIT_ACTIONFLT7EN_FW BIT(7)\n#define BIT_ACTIONFLT6EN_FW BIT(6)\n#define BIT_ACTIONFLT5EN_FW BIT(5)\n#define BIT_ACTIONFLT4EN_FW BIT(4)\n#define BIT_ACTIONFLT3EN_FW BIT(3)\n#define BIT_ACTIONFLT2EN_FW BIT(2)\n#define BIT_ACTIONFLT1EN_FW BIT(1)\n#define BIT_ACTIONFLT0EN_FW BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WOW_CTRL\t\t\t\t(Offset 0x0690) */\n\n#define BIT_SHIFT_PSF_BSSIDSEL_B2B1 6\n#define BIT_MASK_PSF_BSSIDSEL_B2B1 0x3\n#define BIT_PSF_BSSIDSEL_B2B1(x)                                               \\\n\t(((x) & BIT_MASK_PSF_BSSIDSEL_B2B1) << BIT_SHIFT_PSF_BSSIDSEL_B2B1)\n#define BITS_PSF_BSSIDSEL_B2B1                                                 \\\n\t(BIT_MASK_PSF_BSSIDSEL_B2B1 << BIT_SHIFT_PSF_BSSIDSEL_B2B1)\n#define BIT_CLEAR_PSF_BSSIDSEL_B2B1(x) ((x) & (~BITS_PSF_BSSIDSEL_B2B1))\n#define BIT_GET_PSF_BSSIDSEL_B2B1(x)                                           \\\n\t(((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1) & BIT_MASK_PSF_BSSIDSEL_B2B1)\n#define BIT_SET_PSF_BSSIDSEL_B2B1(x, v)                                        \\\n\t(BIT_CLEAR_PSF_BSSIDSEL_B2B1(x) | BIT_PSF_BSSIDSEL_B2B1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WOW_CTRL\t\t\t\t(Offset 0x0690) */\n\n#define BIT_WOWHCI BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WOW_CTRL\t\t\t\t(Offset 0x0690) */\n\n#define BIT_PSF_BSSIDSEL BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WOW_CTRL\t\t\t\t(Offset 0x0690) */\n\n#define BIT_PSF_BSSIDSEL_B0 BIT(4)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WOW_CTRL\t\t\t\t(Offset 0x0690) */\n\n#define BIT_UWF BIT(3)\n#define BIT_MAGIC BIT(2)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WOW_CTRL\t\t\t\t(Offset 0x0690) */\n\n#define BIT_WOWEN BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WOW_CTRL\t\t\t\t(Offset 0x0690) */\n\n#define BIT_WFMSK BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WOW_CTRL\t\t\t\t(Offset 0x0690) */\n\n#define BIT_FORCE_WAKEUP BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_NAN_RX_TSF_FILTER\t\t\t(Offset 0x0691) */\n\n#define BIT_CHK_TSF_TA BIT(2)\n#define BIT_CHK_TSF_CBSSID BIT(1)\n#define BIT_CHK_TSF_EN BIT(0)\n\n/* 2 REG_PS_RX_INFO\t\t\t\t(Offset 0x0692) */\n\n#define BIT_WMAC_RESP_NONSTA1_DIS BIT(7)\n\n#define BIT_SHIFT_PORTSEL__PS_RX_INFO 5\n#define BIT_MASK_PORTSEL__PS_RX_INFO 0x7\n#define BIT_PORTSEL__PS_RX_INFO(x)                                             \\\n\t(((x) & BIT_MASK_PORTSEL__PS_RX_INFO) << BIT_SHIFT_PORTSEL__PS_RX_INFO)\n#define BITS_PORTSEL__PS_RX_INFO                                               \\\n\t(BIT_MASK_PORTSEL__PS_RX_INFO << BIT_SHIFT_PORTSEL__PS_RX_INFO)\n#define BIT_CLEAR_PORTSEL__PS_RX_INFO(x) ((x) & (~BITS_PORTSEL__PS_RX_INFO))\n#define BIT_GET_PORTSEL__PS_RX_INFO(x)                                         \\\n\t(((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO) & BIT_MASK_PORTSEL__PS_RX_INFO)\n#define BIT_SET_PORTSEL__PS_RX_INFO(x, v)                                      \\\n\t(BIT_CLEAR_PORTSEL__PS_RX_INFO(x) | BIT_PORTSEL__PS_RX_INFO(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PS_RX_INFO\t\t\t\t(Offset 0x0692) */\n\n#define BIT_RXCTRLIN0 BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PS_RX_INFO\t\t\t\t(Offset 0x0692) */\n\n#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY 4\n#define BIT_MASK_WMAC_TXMU_ACKPOLICY 0x3\n#define BIT_WMAC_TXMU_ACKPOLICY(x)                                             \\\n\t(((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY)\n#define BITS_WMAC_TXMU_ACKPOLICY                                               \\\n\t(BIT_MASK_WMAC_TXMU_ACKPOLICY << BIT_SHIFT_WMAC_TXMU_ACKPOLICY)\n#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY(x) ((x) & (~BITS_WMAC_TXMU_ACKPOLICY))\n#define BIT_GET_WMAC_TXMU_ACKPOLICY(x)                                         \\\n\t(((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY) & BIT_MASK_WMAC_TXMU_ACKPOLICY)\n#define BIT_SET_WMAC_TXMU_ACKPOLICY(x, v)                                      \\\n\t(BIT_CLEAR_WMAC_TXMU_ACKPOLICY(x) | BIT_WMAC_TXMU_ACKPOLICY(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PS_RX_INFO\t\t\t\t(Offset 0x0692) */\n\n#define BIT_RXMGTIN0 BIT(3)\n#define BIT_RXDATAIN2 BIT(2)\n#define BIT_RXDATAIN1 BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PS_RX_INFO\t\t\t\t(Offset 0x0692) */\n\n#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL 1\n#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL 0x7\n#define BIT_WMAC_MU_BFEE_PORT_SEL(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL)                                \\\n\t << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL)\n#define BITS_WMAC_MU_BFEE_PORT_SEL                                             \\\n\t(BIT_MASK_WMAC_MU_BFEE_PORT_SEL << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL)\n#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL(x) ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL))\n#define BIT_GET_WMAC_MU_BFEE_PORT_SEL(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) &                            \\\n\t BIT_MASK_WMAC_MU_BFEE_PORT_SEL)\n#define BIT_SET_WMAC_MU_BFEE_PORT_SEL(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL(x) | BIT_WMAC_MU_BFEE_PORT_SEL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_PS_RX_INFO\t\t\t\t(Offset 0x0692) */\n\n#define BIT_RXDATAIN0 BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PS_RX_INFO\t\t\t\t(Offset 0x0692) */\n\n#define BIT_WMAC_MU_BFEE_DIS BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMMPS_UAPSD_TID\t\t\t(Offset 0x0693) */\n\n#define BIT_SHIFT_DTIM_CNT 24\n#define BIT_MASK_DTIM_CNT 0xff\n#define BIT_DTIM_CNT(x) (((x) & BIT_MASK_DTIM_CNT) << BIT_SHIFT_DTIM_CNT)\n#define BITS_DTIM_CNT (BIT_MASK_DTIM_CNT << BIT_SHIFT_DTIM_CNT)\n#define BIT_CLEAR_DTIM_CNT(x) ((x) & (~BITS_DTIM_CNT))\n#define BIT_GET_DTIM_CNT(x) (((x) >> BIT_SHIFT_DTIM_CNT) & BIT_MASK_DTIM_CNT)\n#define BIT_SET_DTIM_CNT(x, v) (BIT_CLEAR_DTIM_CNT(x) | BIT_DTIM_CNT(v))\n\n#define BIT_CTRLFLT15EN BIT(15)\n#define BIT_DATAFLT15EN BIT(15)\n#define BIT_CTRLFLT14EN BIT(14)\n#define BIT_DATAFLT14EN BIT(14)\n#define BIT_MGTFLT13EN BIT(13)\n#define BIT_CTRLFLT13EN BIT(13)\n#define BIT_DATAFLT13EN BIT(13)\n#define BIT_MGTFLT12EN BIT(12)\n#define BIT_CTRLFLT12EN BIT(12)\n#define BIT_DATAFLT12EN BIT(12)\n#define BIT_MGTFLT11EN BIT(11)\n#define BIT_CTRLFLT11EN BIT(11)\n#define BIT_DATAFLT11EN BIT(11)\n#define BIT_MGTFLT10EN BIT(10)\n#define BIT_CTRLFLT10EN BIT(10)\n#define BIT_DATAFLT10EN BIT(10)\n#define BIT_MGTFLT9EN BIT(9)\n#define BIT_CTRLFLT9EN BIT(9)\n#define BIT_DATAFLT9EN BIT(9)\n#define BIT_MGTFLT8EN BIT(8)\n#define BIT_CTRLFLT8EN BIT(8)\n#define BIT_DATAFLT8EN BIT(8)\n#define BIT_WMMPS_UAPSD_TID7 BIT(7)\n#define BIT_CTRLFLT7EN BIT(7)\n#define BIT_DATAFLT7EN BIT(7)\n#define BIT_WMMPS_UAPSD_TID6 BIT(6)\n#define BIT_CTRLFLT6EN BIT(6)\n#define BIT_DATAFLT6EN BIT(6)\n#define BIT_WMMPS_UAPSD_TID5 BIT(5)\n#define BIT_MGTFLT5EN BIT(5)\n#define BIT_DATAFLT5EN BIT(5)\n#define BIT_WMMPS_UAPSD_TID4 BIT(4)\n#define BIT_MGTFLT4EN BIT(4)\n#define BIT_DATAFLT4EN BIT(4)\n#define BIT_WMMPS_UAPSD_TID3 BIT(3)\n#define BIT_MGTFLT3EN BIT(3)\n#define BIT_DATAFLT3EN BIT(3)\n#define BIT_WMMPS_UAPSD_TID2 BIT(2)\n#define BIT_MGTFLT2EN BIT(2)\n#define BIT_DATAFLT2EN BIT(2)\n#define BIT_WMMPS_UAPSD_TID1 BIT(1)\n#define BIT_MGTFLT1EN BIT(1)\n#define BIT_DATAFLT1EN BIT(1)\n#define BIT_WMMPS_UAPSD_TID0 BIT(0)\n#define BIT_MGTFLT0EN BIT(0)\n#define BIT_DATAFLT0EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LPNAV_CTRL\t\t\t\t(Offset 0x0694) */\n\n#define BIT_LPNAV_EN BIT(31)\n\n#define BIT_SHIFT_LPNAV_EARLY 16\n#define BIT_MASK_LPNAV_EARLY 0x7fff\n#define BIT_LPNAV_EARLY(x)                                                     \\\n\t(((x) & BIT_MASK_LPNAV_EARLY) << BIT_SHIFT_LPNAV_EARLY)\n#define BITS_LPNAV_EARLY (BIT_MASK_LPNAV_EARLY << BIT_SHIFT_LPNAV_EARLY)\n#define BIT_CLEAR_LPNAV_EARLY(x) ((x) & (~BITS_LPNAV_EARLY))\n#define BIT_GET_LPNAV_EARLY(x)                                                 \\\n\t(((x) >> BIT_SHIFT_LPNAV_EARLY) & BIT_MASK_LPNAV_EARLY)\n#define BIT_SET_LPNAV_EARLY(x, v)                                              \\\n\t(BIT_CLEAR_LPNAV_EARLY(x) | BIT_LPNAV_EARLY(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_LPNAV_CTRL\t\t\t\t(Offset 0x0694) */\n\n#define BIT_SHIFT_LPNAV_TH 0\n#define BIT_MASK_LPNAV_TH 0xffff\n#define BIT_LPNAV_TH(x) (((x) & BIT_MASK_LPNAV_TH) << BIT_SHIFT_LPNAV_TH)\n#define BITS_LPNAV_TH (BIT_MASK_LPNAV_TH << BIT_SHIFT_LPNAV_TH)\n#define BIT_CLEAR_LPNAV_TH(x) ((x) & (~BITS_LPNAV_TH))\n#define BIT_GET_LPNAV_TH(x) (((x) >> BIT_SHIFT_LPNAV_TH) & BIT_MASK_LPNAV_TH)\n#define BIT_SET_LPNAV_TH(x, v) (BIT_CLEAR_LPNAV_TH(x) | BIT_LPNAV_TH(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_LPNAV_CTRL\t\t\t\t(Offset 0x0694) */\n\n#define BIT_SHIFT_LPNAV_THR 0\n#define BIT_MASK_LPNAV_THR 0xffff\n#define BIT_LPNAV_THR(x) (((x) & BIT_MASK_LPNAV_THR) << BIT_SHIFT_LPNAV_THR)\n#define BITS_LPNAV_THR (BIT_MASK_LPNAV_THR << BIT_SHIFT_LPNAV_THR)\n#define BIT_CLEAR_LPNAV_THR(x) ((x) & (~BITS_LPNAV_THR))\n#define BIT_GET_LPNAV_THR(x) (((x) >> BIT_SHIFT_LPNAV_THR) & BIT_MASK_LPNAV_THR)\n#define BIT_SET_LPNAV_THR(x, v) (BIT_CLEAR_LPNAV_THR(x) | BIT_LPNAV_THR(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WKFMCAM_CMD\t\t\t\t(Offset 0x0698) */\n\n#define BIT_WKFCAM_POLLING_V1 BIT(31)\n#define BIT_WKFCAM_CLR_V1 BIT(30)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WKFMCAM_CMD\t\t\t\t(Offset 0x0698) */\n\n#define BIT_WKFCAM_WE BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WKFMCAM_CMD\t\t\t\t(Offset 0x0698) */\n\n#define BIT_SHIFT_WKFCAM_ADDR_V2 8\n#define BIT_MASK_WKFCAM_ADDR_V2 0xff\n#define BIT_WKFCAM_ADDR_V2(x)                                                  \\\n\t(((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2)\n#define BITS_WKFCAM_ADDR_V2                                                    \\\n\t(BIT_MASK_WKFCAM_ADDR_V2 << BIT_SHIFT_WKFCAM_ADDR_V2)\n#define BIT_CLEAR_WKFCAM_ADDR_V2(x) ((x) & (~BITS_WKFCAM_ADDR_V2))\n#define BIT_GET_WKFCAM_ADDR_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_WKFCAM_ADDR_V2) & BIT_MASK_WKFCAM_ADDR_V2)\n#define BIT_SET_WKFCAM_ADDR_V2(x, v)                                           \\\n\t(BIT_CLEAR_WKFCAM_ADDR_V2(x) | BIT_WKFCAM_ADDR_V2(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WKFMCAM_CMD\t\t\t\t(Offset 0x0698) */\n\n#define BIT_SHIFT_WKFCAM_NUM_V1 0\n#define BIT_MASK_WKFCAM_NUM_V1 0xff\n#define BIT_WKFCAM_NUM_V1(x)                                                   \\\n\t(((x) & BIT_MASK_WKFCAM_NUM_V1) << BIT_SHIFT_WKFCAM_NUM_V1)\n#define BITS_WKFCAM_NUM_V1 (BIT_MASK_WKFCAM_NUM_V1 << BIT_SHIFT_WKFCAM_NUM_V1)\n#define BIT_CLEAR_WKFCAM_NUM_V1(x) ((x) & (~BITS_WKFCAM_NUM_V1))\n#define BIT_GET_WKFCAM_NUM_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_WKFCAM_NUM_V1) & BIT_MASK_WKFCAM_NUM_V1)\n#define BIT_SET_WKFCAM_NUM_V1(x, v)                                            \\\n\t(BIT_CLEAR_WKFCAM_NUM_V1(x) | BIT_WKFCAM_NUM_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WKFMCAM_CMD\t\t\t\t(Offset 0x0698) */\n\n#define BIT_SHIFT_WKFCAM_CAM_NUM_V1 0\n#define BIT_MASK_WKFCAM_CAM_NUM_V1 0xff\n#define BIT_WKFCAM_CAM_NUM_V1(x)                                               \\\n\t(((x) & BIT_MASK_WKFCAM_CAM_NUM_V1) << BIT_SHIFT_WKFCAM_CAM_NUM_V1)\n#define BITS_WKFCAM_CAM_NUM_V1                                                 \\\n\t(BIT_MASK_WKFCAM_CAM_NUM_V1 << BIT_SHIFT_WKFCAM_CAM_NUM_V1)\n#define BIT_CLEAR_WKFCAM_CAM_NUM_V1(x) ((x) & (~BITS_WKFCAM_CAM_NUM_V1))\n#define BIT_GET_WKFCAM_CAM_NUM_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1) & BIT_MASK_WKFCAM_CAM_NUM_V1)\n#define BIT_SET_WKFCAM_CAM_NUM_V1(x, v)                                        \\\n\t(BIT_CLEAR_WKFCAM_CAM_NUM_V1(x) | BIT_WKFCAM_CAM_NUM_V1(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_WKFMCAM_CMD\t\t\t\t(Offset 0x0698) */\n\n#define BIT_SHIFT_WKFCAM_ADDR 0\n#define BIT_MASK_WKFCAM_ADDR 0x7f\n#define BIT_WKFCAM_ADDR(x)                                                     \\\n\t(((x) & BIT_MASK_WKFCAM_ADDR) << BIT_SHIFT_WKFCAM_ADDR)\n#define BITS_WKFCAM_ADDR (BIT_MASK_WKFCAM_ADDR << BIT_SHIFT_WKFCAM_ADDR)\n#define BIT_CLEAR_WKFCAM_ADDR(x) ((x) & (~BITS_WKFCAM_ADDR))\n#define BIT_GET_WKFCAM_ADDR(x)                                                 \\\n\t(((x) >> BIT_SHIFT_WKFCAM_ADDR) & BIT_MASK_WKFCAM_ADDR)\n#define BIT_SET_WKFCAM_ADDR(x, v)                                              \\\n\t(BIT_CLEAR_WKFCAM_ADDR(x) | BIT_WKFCAM_ADDR(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WKFMCAM_RWD\t\t\t\t(Offset 0x069C) */\n\n#define BIT_SHIFT_WKFMCAM_RWD 0\n#define BIT_MASK_WKFMCAM_RWD 0xffffffffL\n#define BIT_WKFMCAM_RWD(x)                                                     \\\n\t(((x) & BIT_MASK_WKFMCAM_RWD) << BIT_SHIFT_WKFMCAM_RWD)\n#define BITS_WKFMCAM_RWD (BIT_MASK_WKFMCAM_RWD << BIT_SHIFT_WKFMCAM_RWD)\n#define BIT_CLEAR_WKFMCAM_RWD(x) ((x) & (~BITS_WKFMCAM_RWD))\n#define BIT_GET_WKFMCAM_RWD(x)                                                 \\\n\t(((x) >> BIT_SHIFT_WKFMCAM_RWD) & BIT_MASK_WKFMCAM_RWD)\n#define BIT_SET_WKFMCAM_RWD(x, v)                                              \\\n\t(BIT_CLEAR_WKFMCAM_RWD(x) | BIT_WKFMCAM_RWD(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BCN_PSR_RPT\t\t\t\t(Offset 0x06A8) */\n\n#define BIT_SHIFT_DTIM_PERIOD 16\n#define BIT_MASK_DTIM_PERIOD 0xff\n#define BIT_DTIM_PERIOD(x)                                                     \\\n\t(((x) & BIT_MASK_DTIM_PERIOD) << BIT_SHIFT_DTIM_PERIOD)\n#define BITS_DTIM_PERIOD (BIT_MASK_DTIM_PERIOD << BIT_SHIFT_DTIM_PERIOD)\n#define BIT_CLEAR_DTIM_PERIOD(x) ((x) & (~BITS_DTIM_PERIOD))\n#define BIT_GET_DTIM_PERIOD(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD) & BIT_MASK_DTIM_PERIOD)\n#define BIT_SET_DTIM_PERIOD(x, v)                                              \\\n\t(BIT_CLEAR_DTIM_PERIOD(x) | BIT_DTIM_PERIOD(v))\n\n#define BIT_DTIM BIT(15)\n#define BIT_TIM BIT(14)\n\n#define BIT_SHIFT_PS_AID_0 0\n#define BIT_MASK_PS_AID_0 0x7ff\n#define BIT_PS_AID_0(x) (((x) & BIT_MASK_PS_AID_0) << BIT_SHIFT_PS_AID_0)\n#define BITS_PS_AID_0 (BIT_MASK_PS_AID_0 << BIT_SHIFT_PS_AID_0)\n#define BIT_CLEAR_PS_AID_0(x) ((x) & (~BITS_PS_AID_0))\n#define BIT_GET_PS_AID_0(x) (((x) >> BIT_SHIFT_PS_AID_0) & BIT_MASK_PS_AID_0)\n#define BIT_SET_PS_AID_0(x, v) (BIT_CLEAR_PS_AID_0(x) | BIT_PS_AID_0(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_FLC_RPC\t\t\t\t(Offset 0x06AC) */\n\n#define BIT_SHIFT_FLC_RPC 0\n#define BIT_MASK_FLC_RPC 0xff\n#define BIT_FLC_RPC(x) (((x) & BIT_MASK_FLC_RPC) << BIT_SHIFT_FLC_RPC)\n#define BITS_FLC_RPC (BIT_MASK_FLC_RPC << BIT_SHIFT_FLC_RPC)\n#define BIT_CLEAR_FLC_RPC(x) ((x) & (~BITS_FLC_RPC))\n#define BIT_GET_FLC_RPC(x) (((x) >> BIT_SHIFT_FLC_RPC) & BIT_MASK_FLC_RPC)\n#define BIT_SET_FLC_RPC(x, v) (BIT_CLEAR_FLC_RPC(x) | BIT_FLC_RPC(v))\n\n/* 2 REG_FLC_RPCT\t\t\t\t(Offset 0x06AD) */\n\n#define BIT_SHIFT_FLC_RPCT 0\n#define BIT_MASK_FLC_RPCT 0xff\n#define BIT_FLC_RPCT(x) (((x) & BIT_MASK_FLC_RPCT) << BIT_SHIFT_FLC_RPCT)\n#define BITS_FLC_RPCT (BIT_MASK_FLC_RPCT << BIT_SHIFT_FLC_RPCT)\n#define BIT_CLEAR_FLC_RPCT(x) ((x) & (~BITS_FLC_RPCT))\n#define BIT_GET_FLC_RPCT(x) (((x) >> BIT_SHIFT_FLC_RPCT) & BIT_MASK_FLC_RPCT)\n#define BIT_SET_FLC_RPCT(x, v) (BIT_CLEAR_FLC_RPCT(x) | BIT_FLC_RPCT(v))\n\n/* 2 REG_FLC_PTS\t\t\t\t(Offset 0x06AE) */\n\n#define BIT_CMF BIT(2)\n#define BIT_CCF BIT(1)\n#define BIT_CDF BIT(0)\n\n/* 2 REG_FLC_TRPC\t\t\t\t(Offset 0x06AF) */\n\n#define BIT_FLC_RPCT_V1 BIT(7)\n#define BIT_MODE BIT(6)\n\n#define BIT_SHIFT_TRPCD 0\n#define BIT_MASK_TRPCD 0x3f\n#define BIT_TRPCD(x) (((x) & BIT_MASK_TRPCD) << BIT_SHIFT_TRPCD)\n#define BITS_TRPCD (BIT_MASK_TRPCD << BIT_SHIFT_TRPCD)\n#define BIT_CLEAR_TRPCD(x) ((x) & (~BITS_TRPCD))\n#define BIT_GET_TRPCD(x) (((x) >> BIT_SHIFT_TRPCD) & BIT_MASK_TRPCD)\n#define BIT_SET_TRPCD(x, v) (BIT_CLEAR_TRPCD(x) | BIT_TRPCD(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXPKTMON_CTRL\t\t\t(Offset 0x06B0) */\n\n#define BIT_SHIFT_RXBKQPKT_SEQ 20\n#define BIT_MASK_RXBKQPKT_SEQ 0xf\n#define BIT_RXBKQPKT_SEQ(x)                                                    \\\n\t(((x) & BIT_MASK_RXBKQPKT_SEQ) << BIT_SHIFT_RXBKQPKT_SEQ)\n#define BITS_RXBKQPKT_SEQ (BIT_MASK_RXBKQPKT_SEQ << BIT_SHIFT_RXBKQPKT_SEQ)\n#define BIT_CLEAR_RXBKQPKT_SEQ(x) ((x) & (~BITS_RXBKQPKT_SEQ))\n#define BIT_GET_RXBKQPKT_SEQ(x)                                                \\\n\t(((x) >> BIT_SHIFT_RXBKQPKT_SEQ) & BIT_MASK_RXBKQPKT_SEQ)\n#define BIT_SET_RXBKQPKT_SEQ(x, v)                                             \\\n\t(BIT_CLEAR_RXBKQPKT_SEQ(x) | BIT_RXBKQPKT_SEQ(v))\n\n#define BIT_SHIFT_RXBEQPKT_SEQ 16\n#define BIT_MASK_RXBEQPKT_SEQ 0xf\n#define BIT_RXBEQPKT_SEQ(x)                                                    \\\n\t(((x) & BIT_MASK_RXBEQPKT_SEQ) << BIT_SHIFT_RXBEQPKT_SEQ)\n#define BITS_RXBEQPKT_SEQ (BIT_MASK_RXBEQPKT_SEQ << BIT_SHIFT_RXBEQPKT_SEQ)\n#define BIT_CLEAR_RXBEQPKT_SEQ(x) ((x) & (~BITS_RXBEQPKT_SEQ))\n#define BIT_GET_RXBEQPKT_SEQ(x)                                                \\\n\t(((x) >> BIT_SHIFT_RXBEQPKT_SEQ) & BIT_MASK_RXBEQPKT_SEQ)\n#define BIT_SET_RXBEQPKT_SEQ(x, v)                                             \\\n\t(BIT_CLEAR_RXBEQPKT_SEQ(x) | BIT_RXBEQPKT_SEQ(v))\n\n#define BIT_SHIFT_RXVIQPKT_SEQ 12\n#define BIT_MASK_RXVIQPKT_SEQ 0xf\n#define BIT_RXVIQPKT_SEQ(x)                                                    \\\n\t(((x) & BIT_MASK_RXVIQPKT_SEQ) << BIT_SHIFT_RXVIQPKT_SEQ)\n#define BITS_RXVIQPKT_SEQ (BIT_MASK_RXVIQPKT_SEQ << BIT_SHIFT_RXVIQPKT_SEQ)\n#define BIT_CLEAR_RXVIQPKT_SEQ(x) ((x) & (~BITS_RXVIQPKT_SEQ))\n#define BIT_GET_RXVIQPKT_SEQ(x)                                                \\\n\t(((x) >> BIT_SHIFT_RXVIQPKT_SEQ) & BIT_MASK_RXVIQPKT_SEQ)\n#define BIT_SET_RXVIQPKT_SEQ(x, v)                                             \\\n\t(BIT_CLEAR_RXVIQPKT_SEQ(x) | BIT_RXVIQPKT_SEQ(v))\n\n#define BIT_SHIFT_RXVOQPKT_SEQ 8\n#define BIT_MASK_RXVOQPKT_SEQ 0xf\n#define BIT_RXVOQPKT_SEQ(x)                                                    \\\n\t(((x) & BIT_MASK_RXVOQPKT_SEQ) << BIT_SHIFT_RXVOQPKT_SEQ)\n#define BITS_RXVOQPKT_SEQ (BIT_MASK_RXVOQPKT_SEQ << BIT_SHIFT_RXVOQPKT_SEQ)\n#define BIT_CLEAR_RXVOQPKT_SEQ(x) ((x) & (~BITS_RXVOQPKT_SEQ))\n#define BIT_GET_RXVOQPKT_SEQ(x)                                                \\\n\t(((x) >> BIT_SHIFT_RXVOQPKT_SEQ) & BIT_MASK_RXVOQPKT_SEQ)\n#define BIT_SET_RXVOQPKT_SEQ(x, v)                                             \\\n\t(BIT_CLEAR_RXVOQPKT_SEQ(x) | BIT_RXVOQPKT_SEQ(v))\n\n#define BIT_RXBKQPKT_ERR BIT(7)\n#define BIT_RXBEQPKT_ERR BIT(6)\n#define BIT_RXVIQPKT_ERR BIT(5)\n#define BIT_RXVOQPKT_ERR BIT(4)\n#define BIT_RXDMA_MON_EN BIT(2)\n#define BIT_RXPKT_MON_RST BIT(1)\n#define BIT_RXPKT_MON_EN BIT(0)\n\n/* 2 REG_STATE_MON\t\t\t\t(Offset 0x06B4) */\n\n#define BIT_EN_TXRPTBUF_CLK BIT(31)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_STATE_MON\t\t\t\t(Offset 0x06B4) */\n\n#define BIT_SHIFT_DMA_MON_EN 24\n#define BIT_MASK_DMA_MON_EN 0x1f\n#define BIT_DMA_MON_EN(x) (((x) & BIT_MASK_DMA_MON_EN) << BIT_SHIFT_DMA_MON_EN)\n#define BITS_DMA_MON_EN (BIT_MASK_DMA_MON_EN << BIT_SHIFT_DMA_MON_EN)\n#define BIT_CLEAR_DMA_MON_EN(x) ((x) & (~BITS_DMA_MON_EN))\n#define BIT_GET_DMA_MON_EN(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DMA_MON_EN) & BIT_MASK_DMA_MON_EN)\n#define BIT_SET_DMA_MON_EN(x, v) (BIT_CLEAR_DMA_MON_EN(x) | BIT_DMA_MON_EN(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_STATE_MON\t\t\t\t(Offset 0x06B4) */\n\n#define BIT_SHIFT_STATE_SEL 24\n#define BIT_MASK_STATE_SEL 0x1f\n#define BIT_STATE_SEL(x) (((x) & BIT_MASK_STATE_SEL) << BIT_SHIFT_STATE_SEL)\n#define BITS_STATE_SEL (BIT_MASK_STATE_SEL << BIT_SHIFT_STATE_SEL)\n#define BIT_CLEAR_STATE_SEL(x) ((x) & (~BITS_STATE_SEL))\n#define BIT_GET_STATE_SEL(x) (((x) >> BIT_SHIFT_STATE_SEL) & BIT_MASK_STATE_SEL)\n#define BIT_SET_STATE_SEL(x, v) (BIT_CLEAR_STATE_SEL(x) | BIT_STATE_SEL(v))\n\n#define BIT_MACRX_ERR_1 BIT(17)\n#define BIT_MACRX_ERR_0 BIT(16)\n#define BIT_DIS_INFOSRCH BIT(14)\n\n#define BIT_SHIFT_STATE_INFO 8\n#define BIT_MASK_STATE_INFO 0xff\n#define BIT_STATE_INFO(x) (((x) & BIT_MASK_STATE_INFO) << BIT_SHIFT_STATE_INFO)\n#define BITS_STATE_INFO (BIT_MASK_STATE_INFO << BIT_SHIFT_STATE_INFO)\n#define BIT_CLEAR_STATE_INFO(x) ((x) & (~BITS_STATE_INFO))\n#define BIT_GET_STATE_INFO(x)                                                  \\\n\t(((x) >> BIT_SHIFT_STATE_INFO) & BIT_MASK_STATE_INFO)\n#define BIT_SET_STATE_INFO(x, v) (BIT_CLEAR_STATE_INFO(x) | BIT_STATE_INFO(v))\n\n#define BIT_UPD_NXT_STATE BIT(7)\n#define BIT_MACTX_ERR_3 BIT(3)\n#define BIT_MACTX_ERR_2 BIT(2)\n#define BIT_MACTX_ERR_1 BIT(1)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_STATE_MON\t\t\t\t(Offset 0x06B4) */\n\n#define BIT_SHIFT_PKT_MON_EN 0\n#define BIT_MASK_PKT_MON_EN 0x7f\n#define BIT_PKT_MON_EN(x) (((x) & BIT_MASK_PKT_MON_EN) << BIT_SHIFT_PKT_MON_EN)\n#define BITS_PKT_MON_EN (BIT_MASK_PKT_MON_EN << BIT_SHIFT_PKT_MON_EN)\n#define BIT_CLEAR_PKT_MON_EN(x) ((x) & (~BITS_PKT_MON_EN))\n#define BIT_GET_PKT_MON_EN(x)                                                  \\\n\t(((x) >> BIT_SHIFT_PKT_MON_EN) & BIT_MASK_PKT_MON_EN)\n#define BIT_SET_PKT_MON_EN(x, v) (BIT_CLEAR_PKT_MON_EN(x) | BIT_PKT_MON_EN(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_STATE_MON\t\t\t\t(Offset 0x06B4) */\n\n#define BIT_SHIFT_CUR_STATE 0\n#define BIT_MASK_CUR_STATE 0x7f\n#define BIT_CUR_STATE(x) (((x) & BIT_MASK_CUR_STATE) << BIT_SHIFT_CUR_STATE)\n#define BITS_CUR_STATE (BIT_MASK_CUR_STATE << BIT_SHIFT_CUR_STATE)\n#define BIT_CLEAR_CUR_STATE(x) ((x) & (~BITS_CUR_STATE))\n#define BIT_GET_CUR_STATE(x) (((x) >> BIT_SHIFT_CUR_STATE) & BIT_MASK_CUR_STATE)\n#define BIT_SET_CUR_STATE(x, v) (BIT_CLEAR_CUR_STATE(x) | BIT_CUR_STATE(v))\n\n#define BIT_MACTX_ERR_0 BIT(0)\n\n#define BIT_SHIFT_INFO_ADDR_OFFSET 0\n#define BIT_MASK_INFO_ADDR_OFFSET 0x1fff\n#define BIT_INFO_ADDR_OFFSET(x)                                                \\\n\t(((x) & BIT_MASK_INFO_ADDR_OFFSET) << BIT_SHIFT_INFO_ADDR_OFFSET)\n#define BITS_INFO_ADDR_OFFSET                                                  \\\n\t(BIT_MASK_INFO_ADDR_OFFSET << BIT_SHIFT_INFO_ADDR_OFFSET)\n#define BIT_CLEAR_INFO_ADDR_OFFSET(x) ((x) & (~BITS_INFO_ADDR_OFFSET))\n#define BIT_GET_INFO_ADDR_OFFSET(x)                                            \\\n\t(((x) >> BIT_SHIFT_INFO_ADDR_OFFSET) & BIT_MASK_INFO_ADDR_OFFSET)\n#define BIT_SET_INFO_ADDR_OFFSET(x, v)                                         \\\n\t(BIT_CLEAR_INFO_ADDR_OFFSET(x) | BIT_INFO_ADDR_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_ERROR_MON\t\t\t\t(Offset 0x06B8) */\n\n#define BIT_BFM_RPTNUM_ERROR BIT(21)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ERROR_MON\t\t\t\t(Offset 0x06B8) */\n\n#define BIT_MACRX_ERR_5 BIT(21)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_ERROR_MON\t\t\t\t(Offset 0x06B8) */\n\n#define BIT_BFM_CHECKSUM_ERROR BIT(20)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ERROR_MON\t\t\t\t(Offset 0x06B8) */\n\n#define BIT_WMAC_PRETX_ERRHDL_EN BIT(15)\n#define BIT_MACTX_ERR_5 BIT(5)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BT_COEX_TABLE\t\t\t(Offset 0x06C0) */\n\n#define BIT_PRI_MASK_RX_RESP BIT(126)\n#define BIT_PRI_MASK_RXOFDM BIT(125)\n#define BIT_PRI_MASK_RXCCK BIT(124)\n#define BIT_PRI_MASK_CCK BIT(108)\n#define BIT_PRI_MASK_OFDM BIT(107)\n#define BIT_PRI_MASK_RTY BIT(106)\n#define BIT_OOB BIT(97)\n#define BIT_ANT_SEL BIT(96)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_BT_COEX_TABLE\t\t\t(Offset 0x06C0) */\n\n#define BIT_SHIFT_R_WMAC_BFINFO_20M_1 16\n#define BIT_MASK_R_WMAC_BFINFO_20M_1 0xfff\n#define BIT_R_WMAC_BFINFO_20M_1(x)                                             \\\n\t(((x) & BIT_MASK_R_WMAC_BFINFO_20M_1) << BIT_SHIFT_R_WMAC_BFINFO_20M_1)\n#define BITS_R_WMAC_BFINFO_20M_1                                               \\\n\t(BIT_MASK_R_WMAC_BFINFO_20M_1 << BIT_SHIFT_R_WMAC_BFINFO_20M_1)\n#define BIT_CLEAR_R_WMAC_BFINFO_20M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_1))\n#define BIT_GET_R_WMAC_BFINFO_20M_1(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1) & BIT_MASK_R_WMAC_BFINFO_20M_1)\n#define BIT_SET_R_WMAC_BFINFO_20M_1(x, v)                                      \\\n\t(BIT_CLEAR_R_WMAC_BFINFO_20M_1(x) | BIT_R_WMAC_BFINFO_20M_1(v))\n\n#define BIT_SHIFT_COEX_TABLE_1 0\n#define BIT_MASK_COEX_TABLE_1 0xffffffffL\n#define BIT_COEX_TABLE_1(x)                                                    \\\n\t(((x) & BIT_MASK_COEX_TABLE_1) << BIT_SHIFT_COEX_TABLE_1)\n#define BITS_COEX_TABLE_1 (BIT_MASK_COEX_TABLE_1 << BIT_SHIFT_COEX_TABLE_1)\n#define BIT_CLEAR_COEX_TABLE_1(x) ((x) & (~BITS_COEX_TABLE_1))\n#define BIT_GET_COEX_TABLE_1(x)                                                \\\n\t(((x) >> BIT_SHIFT_COEX_TABLE_1) & BIT_MASK_COEX_TABLE_1)\n#define BIT_SET_COEX_TABLE_1(x, v)                                             \\\n\t(BIT_CLEAR_COEX_TABLE_1(x) | BIT_COEX_TABLE_1(v))\n\n#define BIT_SHIFT_R_WMAC_BFINFO_20M_0 0\n#define BIT_MASK_R_WMAC_BFINFO_20M_0 0xfff\n#define BIT_R_WMAC_BFINFO_20M_0(x)                                             \\\n\t(((x) & BIT_MASK_R_WMAC_BFINFO_20M_0) << BIT_SHIFT_R_WMAC_BFINFO_20M_0)\n#define BITS_R_WMAC_BFINFO_20M_0                                               \\\n\t(BIT_MASK_R_WMAC_BFINFO_20M_0 << BIT_SHIFT_R_WMAC_BFINFO_20M_0)\n#define BIT_CLEAR_R_WMAC_BFINFO_20M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_0))\n#define BIT_GET_R_WMAC_BFINFO_20M_0(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0) & BIT_MASK_R_WMAC_BFINFO_20M_0)\n#define BIT_SET_R_WMAC_BFINFO_20M_0(x, v)                                      \\\n\t(BIT_CLEAR_R_WMAC_BFINFO_20M_0(x) | BIT_R_WMAC_BFINFO_20M_0(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BT_COEX_TABLE_H\t\t\t(Offset 0x06CC) */\n\n#define BIT_PRI_MASK_RX_RESP_V1 BIT(30)\n#define BIT_PRI_MASK_RXOFDM_V1 BIT(29)\n#define BIT_PRI_MASK_RXCCK_V1 BIT(28)\n#define BIT_PRI_MASK_CCK_V1 BIT(12)\n#define BIT_PRI_MASK_OFDM_V1 BIT(11)\n#define BIT_PRI_MASK_RTY_V1 BIT(10)\n#define BIT_OOB_V1 BIT(1)\n#define BIT_ANT_SEL_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXCMD_0\t\t\t\t(Offset 0x06D0) */\n\n#define BIT_RXCMD_EN BIT(31)\n\n#define BIT_SHIFT_RXCMD_INFO 0\n#define BIT_MASK_RXCMD_INFO 0x7fffffffL\n#define BIT_RXCMD_INFO(x) (((x) & BIT_MASK_RXCMD_INFO) << BIT_SHIFT_RXCMD_INFO)\n#define BITS_RXCMD_INFO (BIT_MASK_RXCMD_INFO << BIT_SHIFT_RXCMD_INFO)\n#define BIT_CLEAR_RXCMD_INFO(x) ((x) & (~BITS_RXCMD_INFO))\n#define BIT_GET_RXCMD_INFO(x)                                                  \\\n\t(((x) >> BIT_SHIFT_RXCMD_INFO) & BIT_MASK_RXCMD_INFO)\n#define BIT_SET_RXCMD_INFO(x, v) (BIT_CLEAR_RXCMD_INFO(x) | BIT_RXCMD_INFO(v))\n\n/* 2 REG_RXCMD_1\t\t\t\t(Offset 0x06D4) */\n\n#define BIT_TXUSER_ID1 BIT(25)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RXCMD_1\t\t\t\t(Offset 0x06D4) */\n\n#define BIT_SHIFT_CSI_RADDR_LATCH_V1 24\n#define BIT_MASK_CSI_RADDR_LATCH_V1 0x3f\n#define BIT_CSI_RADDR_LATCH_V1(x)                                              \\\n\t(((x) & BIT_MASK_CSI_RADDR_LATCH_V1) << BIT_SHIFT_CSI_RADDR_LATCH_V1)\n#define BITS_CSI_RADDR_LATCH_V1                                                \\\n\t(BIT_MASK_CSI_RADDR_LATCH_V1 << BIT_SHIFT_CSI_RADDR_LATCH_V1)\n#define BIT_CLEAR_CSI_RADDR_LATCH_V1(x) ((x) & (~BITS_CSI_RADDR_LATCH_V1))\n#define BIT_GET_CSI_RADDR_LATCH_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V1) & BIT_MASK_CSI_RADDR_LATCH_V1)\n#define BIT_SET_CSI_RADDR_LATCH_V1(x, v)                                       \\\n\t(BIT_CLEAR_CSI_RADDR_LATCH_V1(x) | BIT_CSI_RADDR_LATCH_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)\n\n/* 2 REG_RXCMD_1\t\t\t\t(Offset 0x06D4) */\n\n#define BIT_SHIFT_CSI_RADDR_LATCH 24\n#define BIT_MASK_CSI_RADDR_LATCH 0xff\n#define BIT_CSI_RADDR_LATCH(x)                                                 \\\n\t(((x) & BIT_MASK_CSI_RADDR_LATCH) << BIT_SHIFT_CSI_RADDR_LATCH)\n#define BITS_CSI_RADDR_LATCH                                                   \\\n\t(BIT_MASK_CSI_RADDR_LATCH << BIT_SHIFT_CSI_RADDR_LATCH)\n#define BIT_CLEAR_CSI_RADDR_LATCH(x) ((x) & (~BITS_CSI_RADDR_LATCH))\n#define BIT_GET_CSI_RADDR_LATCH(x)                                             \\\n\t(((x) >> BIT_SHIFT_CSI_RADDR_LATCH) & BIT_MASK_CSI_RADDR_LATCH)\n#define BIT_SET_CSI_RADDR_LATCH(x, v)                                          \\\n\t(BIT_CLEAR_CSI_RADDR_LATCH(x) | BIT_CSI_RADDR_LATCH(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXCMD_1\t\t\t\t(Offset 0x06D4) */\n\n#define BIT_SHIFT_AID1 16\n#define BIT_MASK_AID1 0x1ff\n#define BIT_AID1(x) (((x) & BIT_MASK_AID1) << BIT_SHIFT_AID1)\n#define BITS_AID1 (BIT_MASK_AID1 << BIT_SHIFT_AID1)\n#define BIT_CLEAR_AID1(x) ((x) & (~BITS_AID1))\n#define BIT_GET_AID1(x) (((x) >> BIT_SHIFT_AID1) & BIT_MASK_AID1)\n#define BIT_SET_AID1(x, v) (BIT_CLEAR_AID1(x) | BIT_AID1(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RXCMD_1\t\t\t\t(Offset 0x06D4) */\n\n#define BIT_SHIFT_CSI_WADDR_LATCH_V1 16\n#define BIT_MASK_CSI_WADDR_LATCH_V1 0x3f\n#define BIT_CSI_WADDR_LATCH_V1(x)                                              \\\n\t(((x) & BIT_MASK_CSI_WADDR_LATCH_V1) << BIT_SHIFT_CSI_WADDR_LATCH_V1)\n#define BITS_CSI_WADDR_LATCH_V1                                                \\\n\t(BIT_MASK_CSI_WADDR_LATCH_V1 << BIT_SHIFT_CSI_WADDR_LATCH_V1)\n#define BIT_CLEAR_CSI_WADDR_LATCH_V1(x) ((x) & (~BITS_CSI_WADDR_LATCH_V1))\n#define BIT_GET_CSI_WADDR_LATCH_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V1) & BIT_MASK_CSI_WADDR_LATCH_V1)\n#define BIT_SET_CSI_WADDR_LATCH_V1(x, v)                                       \\\n\t(BIT_CLEAR_CSI_WADDR_LATCH_V1(x) | BIT_CSI_WADDR_LATCH_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)\n\n/* 2 REG_RXCMD_1\t\t\t\t(Offset 0x06D4) */\n\n#define BIT_SHIFT_CSI_WADDR_LATCH 16\n#define BIT_MASK_CSI_WADDR_LATCH 0xff\n#define BIT_CSI_WADDR_LATCH(x)                                                 \\\n\t(((x) & BIT_MASK_CSI_WADDR_LATCH) << BIT_SHIFT_CSI_WADDR_LATCH)\n#define BITS_CSI_WADDR_LATCH                                                   \\\n\t(BIT_MASK_CSI_WADDR_LATCH << BIT_SHIFT_CSI_WADDR_LATCH)\n#define BIT_CLEAR_CSI_WADDR_LATCH(x) ((x) & (~BITS_CSI_WADDR_LATCH))\n#define BIT_GET_CSI_WADDR_LATCH(x)                                             \\\n\t(((x) >> BIT_SHIFT_CSI_WADDR_LATCH) & BIT_MASK_CSI_WADDR_LATCH)\n#define BIT_SET_CSI_WADDR_LATCH(x, v)                                          \\\n\t(BIT_CLEAR_CSI_WADDR_LATCH(x) | BIT_CSI_WADDR_LATCH(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXCMD_1\t\t\t\t(Offset 0x06D4) */\n\n#define BIT_TXUSER_ID0 BIT(9)\n\n#define BIT_SHIFT_RXCMD_PRD 0\n#define BIT_MASK_RXCMD_PRD 0xffff\n#define BIT_RXCMD_PRD(x) (((x) & BIT_MASK_RXCMD_PRD) << BIT_SHIFT_RXCMD_PRD)\n#define BITS_RXCMD_PRD (BIT_MASK_RXCMD_PRD << BIT_SHIFT_RXCMD_PRD)\n#define BIT_CLEAR_RXCMD_PRD(x) ((x) & (~BITS_RXCMD_PRD))\n#define BIT_GET_RXCMD_PRD(x) (((x) >> BIT_SHIFT_RXCMD_PRD) & BIT_MASK_RXCMD_PRD)\n#define BIT_SET_RXCMD_PRD(x, v) (BIT_CLEAR_RXCMD_PRD(x) | BIT_RXCMD_PRD(v))\n\n#define BIT_SHIFT_AID0 0\n#define BIT_MASK_AID0 0x1ff\n#define BIT_AID0(x) (((x) & BIT_MASK_AID0) << BIT_SHIFT_AID0)\n#define BITS_AID0 (BIT_MASK_AID0 << BIT_SHIFT_AID0)\n#define BIT_CLEAR_AID0(x) ((x) & (~BITS_AID0))\n#define BIT_GET_AID0(x) (((x) >> BIT_SHIFT_AID0) & BIT_MASK_AID0)\n#define BIT_SET_AID0(x, v) (BIT_CLEAR_AID0(x) | BIT_AID0(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RESP_TXINFO_CFG\t\t\t(Offset 0x06D8) */\n\n#define BIT_SHIFT_RESP_MFB 25\n#define BIT_MASK_RESP_MFB 0x7f\n#define BIT_RESP_MFB(x) (((x) & BIT_MASK_RESP_MFB) << BIT_SHIFT_RESP_MFB)\n#define BITS_RESP_MFB (BIT_MASK_RESP_MFB << BIT_SHIFT_RESP_MFB)\n#define BIT_CLEAR_RESP_MFB(x) ((x) & (~BITS_RESP_MFB))\n#define BIT_GET_RESP_MFB(x) (((x) >> BIT_SHIFT_RESP_MFB) & BIT_MASK_RESP_MFB)\n#define BIT_SET_RESP_MFB(x, v) (BIT_CLEAR_RESP_MFB(x) | BIT_RESP_MFB(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_RESP_TXINFO\t\t\t(Offset 0x06D8) */\n\n#define BIT_SHIFT_WMAC_RESP_MFB 25\n#define BIT_MASK_WMAC_RESP_MFB 0x7f\n#define BIT_WMAC_RESP_MFB(x)                                                   \\\n\t(((x) & BIT_MASK_WMAC_RESP_MFB) << BIT_SHIFT_WMAC_RESP_MFB)\n#define BITS_WMAC_RESP_MFB (BIT_MASK_WMAC_RESP_MFB << BIT_SHIFT_WMAC_RESP_MFB)\n#define BIT_CLEAR_WMAC_RESP_MFB(x) ((x) & (~BITS_WMAC_RESP_MFB))\n#define BIT_GET_WMAC_RESP_MFB(x)                                               \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_MFB) & BIT_MASK_WMAC_RESP_MFB)\n#define BIT_SET_WMAC_RESP_MFB(x, v)                                            \\\n\t(BIT_CLEAR_WMAC_RESP_MFB(x) | BIT_WMAC_RESP_MFB(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RESP_TXINFO_CFG\t\t\t(Offset 0x06D8) */\n\n#define BIT_SHIFT_ANTINF_SEL 23\n#define BIT_MASK_ANTINF_SEL 0x3\n#define BIT_ANTINF_SEL(x) (((x) & BIT_MASK_ANTINF_SEL) << BIT_SHIFT_ANTINF_SEL)\n#define BITS_ANTINF_SEL (BIT_MASK_ANTINF_SEL << BIT_SHIFT_ANTINF_SEL)\n#define BIT_CLEAR_ANTINF_SEL(x) ((x) & (~BITS_ANTINF_SEL))\n#define BIT_GET_ANTINF_SEL(x)                                                  \\\n\t(((x) >> BIT_SHIFT_ANTINF_SEL) & BIT_MASK_ANTINF_SEL)\n#define BIT_SET_ANTINF_SEL(x, v) (BIT_CLEAR_ANTINF_SEL(x) | BIT_ANTINF_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_RESP_TXINFO\t\t\t(Offset 0x06D8) */\n\n#define BIT_SHIFT_WMAC_ANTINF_SEL 23\n#define BIT_MASK_WMAC_ANTINF_SEL 0x3\n#define BIT_WMAC_ANTINF_SEL(x)                                                 \\\n\t(((x) & BIT_MASK_WMAC_ANTINF_SEL) << BIT_SHIFT_WMAC_ANTINF_SEL)\n#define BITS_WMAC_ANTINF_SEL                                                   \\\n\t(BIT_MASK_WMAC_ANTINF_SEL << BIT_SHIFT_WMAC_ANTINF_SEL)\n#define BIT_CLEAR_WMAC_ANTINF_SEL(x) ((x) & (~BITS_WMAC_ANTINF_SEL))\n#define BIT_GET_WMAC_ANTINF_SEL(x)                                             \\\n\t(((x) >> BIT_SHIFT_WMAC_ANTINF_SEL) & BIT_MASK_WMAC_ANTINF_SEL)\n#define BIT_SET_WMAC_ANTINF_SEL(x, v)                                          \\\n\t(BIT_CLEAR_WMAC_ANTINF_SEL(x) | BIT_WMAC_ANTINF_SEL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RESP_TXINFO_CFG\t\t\t(Offset 0x06D8) */\n\n#define BIT_SHIFT_ANTSEL_SEL 21\n#define BIT_MASK_ANTSEL_SEL 0x3\n#define BIT_ANTSEL_SEL(x) (((x) & BIT_MASK_ANTSEL_SEL) << BIT_SHIFT_ANTSEL_SEL)\n#define BITS_ANTSEL_SEL (BIT_MASK_ANTSEL_SEL << BIT_SHIFT_ANTSEL_SEL)\n#define BIT_CLEAR_ANTSEL_SEL(x) ((x) & (~BITS_ANTSEL_SEL))\n#define BIT_GET_ANTSEL_SEL(x)                                                  \\\n\t(((x) >> BIT_SHIFT_ANTSEL_SEL) & BIT_MASK_ANTSEL_SEL)\n#define BIT_SET_ANTSEL_SEL(x, v) (BIT_CLEAR_ANTSEL_SEL(x) | BIT_ANTSEL_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_RESP_TXINFO\t\t\t(Offset 0x06D8) */\n\n#define BIT_SHIFT_WMAC_ANTSEL_SEL 21\n#define BIT_MASK_WMAC_ANTSEL_SEL 0x3\n#define BIT_WMAC_ANTSEL_SEL(x)                                                 \\\n\t(((x) & BIT_MASK_WMAC_ANTSEL_SEL) << BIT_SHIFT_WMAC_ANTSEL_SEL)\n#define BITS_WMAC_ANTSEL_SEL                                                   \\\n\t(BIT_MASK_WMAC_ANTSEL_SEL << BIT_SHIFT_WMAC_ANTSEL_SEL)\n#define BIT_CLEAR_WMAC_ANTSEL_SEL(x) ((x) & (~BITS_WMAC_ANTSEL_SEL))\n#define BIT_GET_WMAC_ANTSEL_SEL(x)                                             \\\n\t(((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL) & BIT_MASK_WMAC_ANTSEL_SEL)\n#define BIT_SET_WMAC_ANTSEL_SEL(x, v)                                          \\\n\t(BIT_CLEAR_WMAC_ANTSEL_SEL(x) | BIT_WMAC_ANTSEL_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_WMAC_RESP_TXINFO\t\t\t(Offset 0x06D8) */\n\n#define BIT_SHIFT_R_WMAC_RESP_TXPOWER 18\n#define BIT_MASK_R_WMAC_RESP_TXPOWER 0x7\n#define BIT_R_WMAC_RESP_TXPOWER(x)                                             \\\n\t(((x) & BIT_MASK_R_WMAC_RESP_TXPOWER) << BIT_SHIFT_R_WMAC_RESP_TXPOWER)\n#define BITS_R_WMAC_RESP_TXPOWER                                               \\\n\t(BIT_MASK_R_WMAC_RESP_TXPOWER << BIT_SHIFT_R_WMAC_RESP_TXPOWER)\n#define BIT_CLEAR_R_WMAC_RESP_TXPOWER(x) ((x) & (~BITS_R_WMAC_RESP_TXPOWER))\n#define BIT_GET_R_WMAC_RESP_TXPOWER(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER) & BIT_MASK_R_WMAC_RESP_TXPOWER)\n#define BIT_SET_R_WMAC_RESP_TXPOWER(x, v)                                      \\\n\t(BIT_CLEAR_R_WMAC_RESP_TXPOWER(x) | BIT_R_WMAC_RESP_TXPOWER(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_RESP_TXINFO\t\t\t(Offset 0x06D8) */\n\n#define BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE 18\n#define BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE 0x3\n#define BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE(x)                                   \\\n\t(((x) & BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE)                        \\\n\t << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE)\n#define BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE                                     \\\n\t(BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE                                \\\n\t << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE)\n#define BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE(x)                             \\\n\t((x) & (~BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE))\n#define BIT_GET_WMAC_RESP_TXPOWER_OFFSET_TYPE(x)                               \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE) &                    \\\n\t BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE)\n#define BIT_SET_WMAC_RESP_TXPOWER_OFFSET_TYPE(x, v)                            \\\n\t(BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) |                          \\\n\t BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_RESP_TXINFO\t\t\t(Offset 0x06D8) */\n\n#define BIT_SHIFT_RESP_TXAGC_B 13\n#define BIT_MASK_RESP_TXAGC_B 0x1f\n#define BIT_RESP_TXAGC_B(x)                                                    \\\n\t(((x) & BIT_MASK_RESP_TXAGC_B) << BIT_SHIFT_RESP_TXAGC_B)\n#define BITS_RESP_TXAGC_B (BIT_MASK_RESP_TXAGC_B << BIT_SHIFT_RESP_TXAGC_B)\n#define BIT_CLEAR_RESP_TXAGC_B(x) ((x) & (~BITS_RESP_TXAGC_B))\n#define BIT_GET_RESP_TXAGC_B(x)                                                \\\n\t(((x) >> BIT_SHIFT_RESP_TXAGC_B) & BIT_MASK_RESP_TXAGC_B)\n#define BIT_SET_RESP_TXAGC_B(x, v)                                             \\\n\t(BIT_CLEAR_RESP_TXAGC_B(x) | BIT_RESP_TXAGC_B(v))\n\n#define BIT_SHIFT_RESP_TXAGC_A 8\n#define BIT_MASK_RESP_TXAGC_A 0x1f\n#define BIT_RESP_TXAGC_A(x)                                                    \\\n\t(((x) & BIT_MASK_RESP_TXAGC_A) << BIT_SHIFT_RESP_TXAGC_A)\n#define BITS_RESP_TXAGC_A (BIT_MASK_RESP_TXAGC_A << BIT_SHIFT_RESP_TXAGC_A)\n#define BIT_CLEAR_RESP_TXAGC_A(x) ((x) & (~BITS_RESP_TXAGC_A))\n#define BIT_GET_RESP_TXAGC_A(x)                                                \\\n\t(((x) >> BIT_SHIFT_RESP_TXAGC_A) & BIT_MASK_RESP_TXAGC_A)\n#define BIT_SET_RESP_TXAGC_A(x, v)                                             \\\n\t(BIT_CLEAR_RESP_TXAGC_A(x) | BIT_RESP_TXAGC_A(v))\n\n#define BIT_RESP_ANTSEL_B BIT(7)\n#define BIT_RESP_ANTSEL_A BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_RESP_TXINFO\t\t\t(Offset 0x06D8) */\n\n#define BIT_SHIFT_WMAC_RESP_TXANT_V1 6\n#define BIT_MASK_WMAC_RESP_TXANT_V1 0xfff\n#define BIT_WMAC_RESP_TXANT_V1(x)                                              \\\n\t(((x) & BIT_MASK_WMAC_RESP_TXANT_V1) << BIT_SHIFT_WMAC_RESP_TXANT_V1)\n#define BITS_WMAC_RESP_TXANT_V1                                                \\\n\t(BIT_MASK_WMAC_RESP_TXANT_V1 << BIT_SHIFT_WMAC_RESP_TXANT_V1)\n#define BIT_CLEAR_WMAC_RESP_TXANT_V1(x) ((x) & (~BITS_WMAC_RESP_TXANT_V1))\n#define BIT_GET_WMAC_RESP_TXANT_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_TXANT_V1) & BIT_MASK_WMAC_RESP_TXANT_V1)\n#define BIT_SET_WMAC_RESP_TXANT_V1(x, v)                                       \\\n\t(BIT_CLEAR_WMAC_RESP_TXANT_V1(x) | BIT_WMAC_RESP_TXANT_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_RESP_TXINFO\t\t\t(Offset 0x06D8) */\n\n#define BIT_SHIFT_RESP_TXANT_CCK 4\n#define BIT_MASK_RESP_TXANT_CCK 0x3\n#define BIT_RESP_TXANT_CCK(x)                                                  \\\n\t(((x) & BIT_MASK_RESP_TXANT_CCK) << BIT_SHIFT_RESP_TXANT_CCK)\n#define BITS_RESP_TXANT_CCK                                                    \\\n\t(BIT_MASK_RESP_TXANT_CCK << BIT_SHIFT_RESP_TXANT_CCK)\n#define BIT_CLEAR_RESP_TXANT_CCK(x) ((x) & (~BITS_RESP_TXANT_CCK))\n#define BIT_GET_RESP_TXANT_CCK(x)                                              \\\n\t(((x) >> BIT_SHIFT_RESP_TXANT_CCK) & BIT_MASK_RESP_TXANT_CCK)\n#define BIT_SET_RESP_TXANT_CCK(x, v)                                           \\\n\t(BIT_CLEAR_RESP_TXANT_CCK(x) | BIT_RESP_TXANT_CCK(v))\n\n#define BIT_SHIFT_RESP_TXANT_L 2\n#define BIT_MASK_RESP_TXANT_L 0x3\n#define BIT_RESP_TXANT_L(x)                                                    \\\n\t(((x) & BIT_MASK_RESP_TXANT_L) << BIT_SHIFT_RESP_TXANT_L)\n#define BITS_RESP_TXANT_L (BIT_MASK_RESP_TXANT_L << BIT_SHIFT_RESP_TXANT_L)\n#define BIT_CLEAR_RESP_TXANT_L(x) ((x) & (~BITS_RESP_TXANT_L))\n#define BIT_GET_RESP_TXANT_L(x)                                                \\\n\t(((x) >> BIT_SHIFT_RESP_TXANT_L) & BIT_MASK_RESP_TXANT_L)\n#define BIT_SET_RESP_TXANT_L(x, v)                                             \\\n\t(BIT_CLEAR_RESP_TXANT_L(x) | BIT_RESP_TXANT_L(v))\n\n#define BIT_SHIFT_RESP_TXANT_HT 0\n#define BIT_MASK_RESP_TXANT_HT 0x3\n#define BIT_RESP_TXANT_HT(x)                                                   \\\n\t(((x) & BIT_MASK_RESP_TXANT_HT) << BIT_SHIFT_RESP_TXANT_HT)\n#define BITS_RESP_TXANT_HT (BIT_MASK_RESP_TXANT_HT << BIT_SHIFT_RESP_TXANT_HT)\n#define BIT_CLEAR_RESP_TXANT_HT(x) ((x) & (~BITS_RESP_TXANT_HT))\n#define BIT_GET_RESP_TXANT_HT(x)                                               \\\n\t(((x) >> BIT_SHIFT_RESP_TXANT_HT) & BIT_MASK_RESP_TXANT_HT)\n#define BIT_SET_RESP_TXANT_HT(x, v)                                            \\\n\t(BIT_CLEAR_RESP_TXANT_HT(x) | BIT_RESP_TXANT_HT(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RESP_TXINFO_CFG\t\t\t(Offset 0x06D8) */\n\n#define BIT_SHIFT_RESP_TXANT 0\n#define BIT_MASK_RESP_TXANT 0x3ffff\n#define BIT_RESP_TXANT(x) (((x) & BIT_MASK_RESP_TXANT) << BIT_SHIFT_RESP_TXANT)\n#define BITS_RESP_TXANT (BIT_MASK_RESP_TXANT << BIT_SHIFT_RESP_TXANT)\n#define BIT_CLEAR_RESP_TXANT(x) ((x) & (~BITS_RESP_TXANT))\n#define BIT_GET_RESP_TXANT(x)                                                  \\\n\t(((x) >> BIT_SHIFT_RESP_TXANT) & BIT_MASK_RESP_TXANT)\n#define BIT_SET_RESP_TXANT(x, v) (BIT_CLEAR_RESP_TXANT(x) | BIT_RESP_TXANT(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_WMAC_RESP_TXINFO\t\t\t(Offset 0x06D8) */\n\n#define BIT_SHIFT_WMAC_RESP_TXANT 0\n#define BIT_MASK_WMAC_RESP_TXANT 0x3ffff\n#define BIT_WMAC_RESP_TXANT(x)                                                 \\\n\t(((x) & BIT_MASK_WMAC_RESP_TXANT) << BIT_SHIFT_WMAC_RESP_TXANT)\n#define BITS_WMAC_RESP_TXANT                                                   \\\n\t(BIT_MASK_WMAC_RESP_TXANT << BIT_SHIFT_WMAC_RESP_TXANT)\n#define BIT_CLEAR_WMAC_RESP_TXANT(x) ((x) & (~BITS_WMAC_RESP_TXANT))\n#define BIT_GET_WMAC_RESP_TXANT(x)                                             \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_TXANT) & BIT_MASK_WMAC_RESP_TXANT)\n#define BIT_SET_WMAC_RESP_TXANT(x, v)                                          \\\n\t(BIT_CLEAR_WMAC_RESP_TXANT(x) | BIT_WMAC_RESP_TXANT(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BBPSF_CTRL\t\t\t\t(Offset 0x06DC) */\n\n#define BIT_CTL_IDLE_CLR_CSI_RPT BIT(31)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BBPSF_CTRL\t\t\t\t(Offset 0x06DC) */\n\n#define BIT_WMAC_USE_NDPARATE BIT(30)\n\n#define BIT_SHIFT_WMAC_CSI_RATE 24\n#define BIT_MASK_WMAC_CSI_RATE 0x3f\n#define BIT_WMAC_CSI_RATE(x)                                                   \\\n\t(((x) & BIT_MASK_WMAC_CSI_RATE) << BIT_SHIFT_WMAC_CSI_RATE)\n#define BITS_WMAC_CSI_RATE (BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE)\n#define BIT_CLEAR_WMAC_CSI_RATE(x) ((x) & (~BITS_WMAC_CSI_RATE))\n#define BIT_GET_WMAC_CSI_RATE(x)                                               \\\n\t(((x) >> BIT_SHIFT_WMAC_CSI_RATE) & BIT_MASK_WMAC_CSI_RATE)\n#define BIT_SET_WMAC_CSI_RATE(x, v)                                            \\\n\t(BIT_CLEAR_WMAC_CSI_RATE(x) | BIT_WMAC_CSI_RATE(v))\n\n#define BIT_SHIFT_WMAC_RESP_TXRATE 16\n#define BIT_MASK_WMAC_RESP_TXRATE 0xff\n#define BIT_WMAC_RESP_TXRATE(x)                                                \\\n\t(((x) & BIT_MASK_WMAC_RESP_TXRATE) << BIT_SHIFT_WMAC_RESP_TXRATE)\n#define BITS_WMAC_RESP_TXRATE                                                  \\\n\t(BIT_MASK_WMAC_RESP_TXRATE << BIT_SHIFT_WMAC_RESP_TXRATE)\n#define BIT_CLEAR_WMAC_RESP_TXRATE(x) ((x) & (~BITS_WMAC_RESP_TXRATE))\n#define BIT_GET_WMAC_RESP_TXRATE(x)                                            \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_TXRATE) & BIT_MASK_WMAC_RESP_TXRATE)\n#define BIT_SET_WMAC_RESP_TXRATE(x, v)                                         \\\n\t(BIT_CLEAR_WMAC_RESP_TXRATE(x) | BIT_WMAC_RESP_TXRATE(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_BBPSF_CTRL\t\t\t\t(Offset 0x06DC) */\n\n#define BIT_WMAC_CSI_RATE_FORCE_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)\n\n/* 2 REG_BBPSF_CTRL\t\t\t\t(Offset 0x06DC) */\n\n#define BIT_CSI_FORCE_RATE_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_BBPSF_CTRL\t\t\t\t(Offset 0x06DC) */\n\n#define BIT_SHIFT_WMAC_CSI_RSC_FORCE 13\n#define BIT_MASK_WMAC_CSI_RSC_FORCE 0x3\n#define BIT_WMAC_CSI_RSC_FORCE(x)                                              \\\n\t(((x) & BIT_MASK_WMAC_CSI_RSC_FORCE) << BIT_SHIFT_WMAC_CSI_RSC_FORCE)\n#define BITS_WMAC_CSI_RSC_FORCE                                                \\\n\t(BIT_MASK_WMAC_CSI_RSC_FORCE << BIT_SHIFT_WMAC_CSI_RSC_FORCE)\n#define BIT_CLEAR_WMAC_CSI_RSC_FORCE(x) ((x) & (~BITS_WMAC_CSI_RSC_FORCE))\n#define BIT_GET_WMAC_CSI_RSC_FORCE(x)                                          \\\n\t(((x) >> BIT_SHIFT_WMAC_CSI_RSC_FORCE) & BIT_MASK_WMAC_CSI_RSC_FORCE)\n#define BIT_SET_WMAC_CSI_RSC_FORCE(x, v)                                       \\\n\t(BIT_CLEAR_WMAC_CSI_RSC_FORCE(x) | BIT_WMAC_CSI_RSC_FORCE(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BBPSF_CTRL\t\t\t\t(Offset 0x06DC) */\n\n#define BIT_SHIFT_CSI_RSC 13\n#define BIT_MASK_CSI_RSC 0x3\n#define BIT_CSI_RSC(x) (((x) & BIT_MASK_CSI_RSC) << BIT_SHIFT_CSI_RSC)\n#define BITS_CSI_RSC (BIT_MASK_CSI_RSC << BIT_SHIFT_CSI_RSC)\n#define BIT_CLEAR_CSI_RSC(x) ((x) & (~BITS_CSI_RSC))\n#define BIT_GET_CSI_RSC(x) (((x) >> BIT_SHIFT_CSI_RSC) & BIT_MASK_CSI_RSC)\n#define BIT_SET_CSI_RSC(x, v) (BIT_CLEAR_CSI_RSC(x) | BIT_CSI_RSC(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_BBPSF_CTRL\t\t\t\t(Offset 0x06DC) */\n\n#define BIT_WMAC_CSI_GID_SEL BIT(12)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BBPSF_CTRL\t\t\t\t(Offset 0x06DC) */\n\n#define BIT_CSI_GID_SEL BIT(12)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT)\n\n/* 2 REG_BBPSF_CTRL\t\t\t\t(Offset 0x06DC) */\n\n#define BIT_RDCSIMD_FLAG_TRIG_SEL BIT(11)\n#define BIT_NDPVLD_POS_RST_FFPTR_DIS_V1 BIT(10)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BBPSF_CTRL\t\t\t\t(Offset 0x06DC) */\n\n#define BIT_NDPVLD_PROTECT_RDRDY_DIS BIT(9)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_BBPSF_CTRL\t\t\t\t(Offset 0x06DC) */\n\n#define BIT_CSIRD_EMPTY_APPZERO BIT(8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BBPSF_CTRL\t\t\t\t(Offset 0x06DC) */\n\n#define BIT_RDCSI_EMPTY_APPZERO BIT(8)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_BBPSF_CTRL\t\t\t\t(Offset 0x06DC) */\n\n#define BIT_WMC_CSI_RATE_FB_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BBPSF_CTRL\t\t\t\t(Offset 0x06DC) */\n\n#define BIT_CSI_RATE_FB_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BBPSF_CTRL\t\t\t\t(Offset 0x06DC) */\n\n#define BIT_RXFIFO_WRPTR_WO_CHKSUM BIT(6)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_BBPSF_CTRL\t\t\t\t(Offset 0x06DC) */\n\n#define BIT_BBPSF_MPDUCHKEN BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_BBPSF_CTRL\t\t\t\t(Offset 0x06DC) */\n\n#define BIT_BBPSF_MHCHKEN BIT(4)\n#define BIT_BBPSF_ERRCHKEN BIT(3)\n\n#define BIT_SHIFT_BBPSF_ERRTHR 0\n#define BIT_MASK_BBPSF_ERRTHR 0x7\n#define BIT_BBPSF_ERRTHR(x)                                                    \\\n\t(((x) & BIT_MASK_BBPSF_ERRTHR) << BIT_SHIFT_BBPSF_ERRTHR)\n#define BITS_BBPSF_ERRTHR (BIT_MASK_BBPSF_ERRTHR << BIT_SHIFT_BBPSF_ERRTHR)\n#define BIT_CLEAR_BBPSF_ERRTHR(x) ((x) & (~BITS_BBPSF_ERRTHR))\n#define BIT_GET_BBPSF_ERRTHR(x)                                                \\\n\t(((x) >> BIT_SHIFT_BBPSF_ERRTHR) & BIT_MASK_BBPSF_ERRTHR)\n#define BIT_SET_BBPSF_ERRTHR(x, v)                                             \\\n\t(BIT_CLEAR_BBPSF_ERRTHR(x) | BIT_BBPSF_ERRTHR(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RESP_TXINFO_RATE\t\t\t(Offset 0x06DE) */\n\n#define BIT_CTL_IDLE_CLR_CSI_RPT_V1 BIT(15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_RESP_TXINFO_RATE\t\t\t(Offset 0x06DE) */\n\n#define BIT_USE_NDPARATE BIT(14)\n\n#define BIT_SHIFT_CSI_RATE 8\n#define BIT_MASK_CSI_RATE 0x3f\n#define BIT_CSI_RATE(x) (((x) & BIT_MASK_CSI_RATE) << BIT_SHIFT_CSI_RATE)\n#define BITS_CSI_RATE (BIT_MASK_CSI_RATE << BIT_SHIFT_CSI_RATE)\n#define BIT_CLEAR_CSI_RATE(x) ((x) & (~BITS_CSI_RATE))\n#define BIT_GET_CSI_RATE(x) (((x) >> BIT_SHIFT_CSI_RATE) & BIT_MASK_CSI_RATE)\n#define BIT_SET_CSI_RATE(x, v) (BIT_CLEAR_CSI_RATE(x) | BIT_CSI_RATE(v))\n\n#define BIT_SHIFT_RESP_TXRATE 0\n#define BIT_MASK_RESP_TXRATE 0xff\n#define BIT_RESP_TXRATE(x)                                                     \\\n\t(((x) & BIT_MASK_RESP_TXRATE) << BIT_SHIFT_RESP_TXRATE)\n#define BITS_RESP_TXRATE (BIT_MASK_RESP_TXRATE << BIT_SHIFT_RESP_TXRATE)\n#define BIT_CLEAR_RESP_TXRATE(x) ((x) & (~BITS_RESP_TXRATE))\n#define BIT_GET_RESP_TXRATE(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RESP_TXRATE) & BIT_MASK_RESP_TXRATE)\n#define BIT_SET_RESP_TXRATE(x, v)                                              \\\n\t(BIT_CLEAR_RESP_TXRATE(x) | BIT_RESP_TXRATE(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_P2P_RX_BCN_NOA\t\t\t(Offset 0x06E0) */\n\n#define BIT_NOA_PARSER_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_P2P_RX_BCN_NOA\t\t\t(Offset 0x06E0) */\n\n#define BIT_BSSID_SEL BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2P_RX_BCN_NOA\t\t\t(Offset 0x06E0) */\n\n#define BIT_SHIFT_BSSID_SEL_V1 12\n#define BIT_MASK_BSSID_SEL_V1 0x7\n#define BIT_BSSID_SEL_V1(x)                                                    \\\n\t(((x) & BIT_MASK_BSSID_SEL_V1) << BIT_SHIFT_BSSID_SEL_V1)\n#define BITS_BSSID_SEL_V1 (BIT_MASK_BSSID_SEL_V1 << BIT_SHIFT_BSSID_SEL_V1)\n#define BIT_CLEAR_BSSID_SEL_V1(x) ((x) & (~BITS_BSSID_SEL_V1))\n#define BIT_GET_BSSID_SEL_V1(x)                                                \\\n\t(((x) >> BIT_SHIFT_BSSID_SEL_V1) & BIT_MASK_BSSID_SEL_V1)\n#define BIT_SET_BSSID_SEL_V1(x, v)                                             \\\n\t(BIT_CLEAR_BSSID_SEL_V1(x) | BIT_BSSID_SEL_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_P2P_RX_BCN_NOA\t\t\t(Offset 0x06E0) */\n\n#define BIT_SHIFT_P2P_OUI_TYPE 0\n#define BIT_MASK_P2P_OUI_TYPE 0xff\n#define BIT_P2P_OUI_TYPE(x)                                                    \\\n\t(((x) & BIT_MASK_P2P_OUI_TYPE) << BIT_SHIFT_P2P_OUI_TYPE)\n#define BITS_P2P_OUI_TYPE (BIT_MASK_P2P_OUI_TYPE << BIT_SHIFT_P2P_OUI_TYPE)\n#define BIT_CLEAR_P2P_OUI_TYPE(x) ((x) & (~BITS_P2P_OUI_TYPE))\n#define BIT_GET_P2P_OUI_TYPE(x)                                                \\\n\t(((x) >> BIT_SHIFT_P2P_OUI_TYPE) & BIT_MASK_P2P_OUI_TYPE)\n#define BIT_SET_P2P_OUI_TYPE(x, v)                                             \\\n\t(BIT_CLEAR_P2P_OUI_TYPE(x) | BIT_P2P_OUI_TYPE(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_P2P_RX_BCN_NOA\t\t\t(Offset 0x06E0) */\n\n#define BIT_SHIFT_INFO_TXRPT_OFFSET_V1 0\n#define BIT_MASK_INFO_TXRPT_OFFSET_V1 0x1fff\n#define BIT_INFO_TXRPT_OFFSET_V1(x)                                            \\\n\t(((x) & BIT_MASK_INFO_TXRPT_OFFSET_V1)                                 \\\n\t << BIT_SHIFT_INFO_TXRPT_OFFSET_V1)\n#define BITS_INFO_TXRPT_OFFSET_V1                                              \\\n\t(BIT_MASK_INFO_TXRPT_OFFSET_V1 << BIT_SHIFT_INFO_TXRPT_OFFSET_V1)\n#define BIT_CLEAR_INFO_TXRPT_OFFSET_V1(x) ((x) & (~BITS_INFO_TXRPT_OFFSET_V1))\n#define BIT_GET_INFO_TXRPT_OFFSET_V1(x)                                        \\\n\t(((x) >> BIT_SHIFT_INFO_TXRPT_OFFSET_V1) &                             \\\n\t BIT_MASK_INFO_TXRPT_OFFSET_V1)\n#define BIT_SET_INFO_TXRPT_OFFSET_V1(x, v)                                     \\\n\t(BIT_CLEAR_INFO_TXRPT_OFFSET_V1(x) | BIT_INFO_TXRPT_OFFSET_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ASSOCIATED_BFMER0_INFO\t\t(Offset 0x06E4) */\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0 0xffffffffffffL\n#define BIT_R_WMAC_SOUNDING_RXADD_R0(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0)                             \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0)\n#define BITS_R_WMAC_SOUNDING_RXADD_R0                                          \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0                                     \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0(x)                                  \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) &                         \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R0)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0(x) |                               \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R0(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ASSOCIATED_BFMER0_INFO\t\t(Offset 0x06E4) */\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1 0xffffffffL\n#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1(x)                                     \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1)                          \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1)\n#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1                                       \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1                                  \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1(x)                               \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1(x)                                 \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1) &                      \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1(x, v)                              \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1(x) |                            \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R0_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_SOUNDING_CFG1\t\t\t(Offset 0x06E8) */\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H 0xffff\n#define BIT_R_WMAC_SOUNDING_RXADD_R0_H(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H)                           \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H)\n#define BITS_R_WMAC_SOUNDING_RXADD_R0_H                                        \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H                                   \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H(x)                                \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H) &                       \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H(x) |                             \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R0_H(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ASSOCIATED_BFMER0_INFO_H\t\t(Offset 0x06E8) */\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1 0xffff\n#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1(x)                                   \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1)                        \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1)\n#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1                                     \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1                                \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1(x)                             \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1(x)                               \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1) &                    \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1(x, v)                            \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) |                          \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ASSOCIATED_BFMER1_INFO\t\t(Offset 0x06EC) */\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1 0xffffffffffffL\n#define BIT_R_WMAC_SOUNDING_RXADD_R1(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1)                             \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1)\n#define BITS_R_WMAC_SOUNDING_RXADD_R1                                          \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1                                     \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1(x)                                  \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) &                         \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R1)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1(x) |                               \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_SOUNDING_CFG2\t\t\t(Offset 0x06EC) */\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V2 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V2 0xffffffffL\n#define BIT_R_WMAC_SOUNDING_RXADD_R1_V2(x)                                     \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V2)                          \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V2)\n#define BITS_R_WMAC_SOUNDING_RXADD_R1_V2                                       \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V2                                  \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V2)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V2(x)                               \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V2))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V2(x)                                 \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V2) &                      \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V2)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V2(x, v)                              \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V2(x) |                            \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R1_V2(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ASSOCIATED_BFMER1_INFO\t\t(Offset 0x06EC) */\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1 0xffffffffL\n#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1(x)                                     \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1)                          \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1)\n#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1                                       \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1                                  \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1(x)                               \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1(x)                                 \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1) &                      \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1(x, v)                              \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1(x) |                            \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R1_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_SOUNDING_CFG3\t\t\t(Offset 0x06F0) */\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V2 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V2 0xffff\n#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V2(x)                                   \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V2)                        \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V2)\n#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V2                                     \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V2                                \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V2)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V2(x)                             \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V2))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V2(x)                               \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V2) &                    \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V2)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V2(x, v)                            \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V2(x) |                          \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R1_H_V2(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ASSOCIATED_BFMER1_INFO_H\t\t(Offset 0x06F0) */\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1 0xffff\n#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1(x)                                   \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1)                        \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1)\n#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1                                     \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1                                \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1(x)                             \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1(x)                               \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1) &                    \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1(x, v)                            \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) |                          \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TX_CSI_RPT_PARAM_BW40\t\t(Offset 0x06F8) */\n\n#define BIT_SHIFT_R_WMAC_BFINFO_40M_1 13\n#define BIT_MASK_R_WMAC_BFINFO_40M_1 0x7fff\n#define BIT_R_WMAC_BFINFO_40M_1(x)                                             \\\n\t(((x) & BIT_MASK_R_WMAC_BFINFO_40M_1) << BIT_SHIFT_R_WMAC_BFINFO_40M_1)\n#define BITS_R_WMAC_BFINFO_40M_1                                               \\\n\t(BIT_MASK_R_WMAC_BFINFO_40M_1 << BIT_SHIFT_R_WMAC_BFINFO_40M_1)\n#define BIT_CLEAR_R_WMAC_BFINFO_40M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_40M_1))\n#define BIT_GET_R_WMAC_BFINFO_40M_1(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_1) & BIT_MASK_R_WMAC_BFINFO_40M_1)\n#define BIT_SET_R_WMAC_BFINFO_40M_1(x, v)                                      \\\n\t(BIT_CLEAR_R_WMAC_BFINFO_40M_1(x) | BIT_R_WMAC_BFINFO_40M_1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_ANTCD_INFO\t\t\t\t(Offset 0x06F8) */\n\n#define BIT_RESP_SMOOTH BIT(8)\n\n#define BIT_SHIFT_POWER_STAGE2_NORETRY 6\n#define BIT_MASK_POWER_STAGE2_NORETRY 0x3\n#define BIT_POWER_STAGE2_NORETRY(x)                                            \\\n\t(((x) & BIT_MASK_POWER_STAGE2_NORETRY)                                 \\\n\t << BIT_SHIFT_POWER_STAGE2_NORETRY)\n#define BITS_POWER_STAGE2_NORETRY                                              \\\n\t(BIT_MASK_POWER_STAGE2_NORETRY << BIT_SHIFT_POWER_STAGE2_NORETRY)\n#define BIT_CLEAR_POWER_STAGE2_NORETRY(x) ((x) & (~BITS_POWER_STAGE2_NORETRY))\n#define BIT_GET_POWER_STAGE2_NORETRY(x)                                        \\\n\t(((x) >> BIT_SHIFT_POWER_STAGE2_NORETRY) &                             \\\n\t BIT_MASK_POWER_STAGE2_NORETRY)\n#define BIT_SET_POWER_STAGE2_NORETRY(x, v)                                     \\\n\t(BIT_CLEAR_POWER_STAGE2_NORETRY(x) | BIT_POWER_STAGE2_NORETRY(v))\n\n#define BIT_SHIFT_POWER_STAGE1_NORETRY 4\n#define BIT_MASK_POWER_STAGE1_NORETRY 0x3\n#define BIT_POWER_STAGE1_NORETRY(x)                                            \\\n\t(((x) & BIT_MASK_POWER_STAGE1_NORETRY)                                 \\\n\t << BIT_SHIFT_POWER_STAGE1_NORETRY)\n#define BITS_POWER_STAGE1_NORETRY                                              \\\n\t(BIT_MASK_POWER_STAGE1_NORETRY << BIT_SHIFT_POWER_STAGE1_NORETRY)\n#define BIT_CLEAR_POWER_STAGE1_NORETRY(x) ((x) & (~BITS_POWER_STAGE1_NORETRY))\n#define BIT_GET_POWER_STAGE1_NORETRY(x)                                        \\\n\t(((x) >> BIT_SHIFT_POWER_STAGE1_NORETRY) &                             \\\n\t BIT_MASK_POWER_STAGE1_NORETRY)\n#define BIT_SET_POWER_STAGE1_NORETRY(x, v)                                     \\\n\t(BIT_CLEAR_POWER_STAGE1_NORETRY(x) | BIT_POWER_STAGE1_NORETRY(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TX_CSI_RPT_PARAM_BW40\t\t(Offset 0x06F8) */\n\n#define BIT_SHIFT_R_WMAC_BFINFO_40M_0 0\n#define BIT_MASK_R_WMAC_BFINFO_40M_0 0xfff\n#define BIT_R_WMAC_BFINFO_40M_0(x)                                             \\\n\t(((x) & BIT_MASK_R_WMAC_BFINFO_40M_0) << BIT_SHIFT_R_WMAC_BFINFO_40M_0)\n#define BITS_R_WMAC_BFINFO_40M_0                                               \\\n\t(BIT_MASK_R_WMAC_BFINFO_40M_0 << BIT_SHIFT_R_WMAC_BFINFO_40M_0)\n#define BIT_CLEAR_R_WMAC_BFINFO_40M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_40M_0))\n#define BIT_GET_R_WMAC_BFINFO_40M_0(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_0) & BIT_MASK_R_WMAC_BFINFO_40M_0)\n#define BIT_SET_R_WMAC_BFINFO_40M_0(x, v)                                      \\\n\t(BIT_CLEAR_R_WMAC_BFINFO_40M_0(x) | BIT_R_WMAC_BFINFO_40M_0(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_ANTCD_INFO\t\t\t\t(Offset 0x06F8) */\n\n#define BIT_SHIFT_RESP_ANTCD 0\n#define BIT_MASK_RESP_ANTCD 0xf\n#define BIT_RESP_ANTCD(x) (((x) & BIT_MASK_RESP_ANTCD) << BIT_SHIFT_RESP_ANTCD)\n#define BITS_RESP_ANTCD (BIT_MASK_RESP_ANTCD << BIT_SHIFT_RESP_ANTCD)\n#define BIT_CLEAR_RESP_ANTCD(x) ((x) & (~BITS_RESP_ANTCD))\n#define BIT_GET_RESP_ANTCD(x)                                                  \\\n\t(((x) >> BIT_SHIFT_RESP_ANTCD) & BIT_MASK_RESP_ANTCD)\n#define BIT_SET_RESP_ANTCD(x, v) (BIT_CLEAR_RESP_ANTCD(x) | BIT_RESP_ANTCD(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_TX_CSI_RPT_PARAM_BW40\t\t(Offset 0x06F8) */\n\n#define BIT_SHIFT_WMAC_RESP_ANTCD 0\n#define BIT_MASK_WMAC_RESP_ANTCD 0xf\n#define BIT_WMAC_RESP_ANTCD(x)                                                 \\\n\t(((x) & BIT_MASK_WMAC_RESP_ANTCD) << BIT_SHIFT_WMAC_RESP_ANTCD)\n#define BITS_WMAC_RESP_ANTCD                                                   \\\n\t(BIT_MASK_WMAC_RESP_ANTCD << BIT_SHIFT_WMAC_RESP_ANTCD)\n#define BIT_CLEAR_WMAC_RESP_ANTCD(x) ((x) & (~BITS_WMAC_RESP_ANTCD))\n#define BIT_GET_WMAC_RESP_ANTCD(x)                                             \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_ANTCD) & BIT_MASK_WMAC_RESP_ANTCD)\n#define BIT_SET_WMAC_RESP_ANTCD(x, v)                                          \\\n\t(BIT_CLEAR_WMAC_RESP_ANTCD(x) | BIT_WMAC_RESP_ANTCD(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_CSI_RRSR_V1\t\t\t\t(Offset 0x06FC) */\n\n#define BIT_WMAC_CSI_LDPC_EN BIT(29)\n#define BIT_WMAC_CSI_STBC_EN BIT(28)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TX_CSI_RPT_PARAM_BW80\t\t(Offset 0x06FC) */\n\n#define BIT_SHIFT_R_WMAC_BFINFO_80M_1 16\n#define BIT_MASK_R_WMAC_BFINFO_80M_1 0xfff\n#define BIT_R_WMAC_BFINFO_80M_1(x)                                             \\\n\t(((x) & BIT_MASK_R_WMAC_BFINFO_80M_1) << BIT_SHIFT_R_WMAC_BFINFO_80M_1)\n#define BITS_R_WMAC_BFINFO_80M_1                                               \\\n\t(BIT_MASK_R_WMAC_BFINFO_80M_1 << BIT_SHIFT_R_WMAC_BFINFO_80M_1)\n#define BIT_CLEAR_R_WMAC_BFINFO_80M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_80M_1))\n#define BIT_GET_R_WMAC_BFINFO_80M_1(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_1) & BIT_MASK_R_WMAC_BFINFO_80M_1)\n#define BIT_SET_R_WMAC_BFINFO_80M_1(x, v)                                      \\\n\t(BIT_CLEAR_R_WMAC_BFINFO_80M_1(x) | BIT_R_WMAC_BFINFO_80M_1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CSI_PTR\t\t\t\t(Offset 0x06FC) */\n\n#define BIT_SHIFT_CSI_RADDR_LATCH_V2 16\n#define BIT_MASK_CSI_RADDR_LATCH_V2 0xffff\n#define BIT_CSI_RADDR_LATCH_V2(x)                                              \\\n\t(((x) & BIT_MASK_CSI_RADDR_LATCH_V2) << BIT_SHIFT_CSI_RADDR_LATCH_V2)\n#define BITS_CSI_RADDR_LATCH_V2                                                \\\n\t(BIT_MASK_CSI_RADDR_LATCH_V2 << BIT_SHIFT_CSI_RADDR_LATCH_V2)\n#define BIT_CLEAR_CSI_RADDR_LATCH_V2(x) ((x) & (~BITS_CSI_RADDR_LATCH_V2))\n#define BIT_GET_CSI_RADDR_LATCH_V2(x)                                          \\\n\t(((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V2) & BIT_MASK_CSI_RADDR_LATCH_V2)\n#define BIT_SET_CSI_RADDR_LATCH_V2(x, v)                                       \\\n\t(BIT_CLEAR_CSI_RADDR_LATCH_V2(x) | BIT_CSI_RADDR_LATCH_V2(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_CSI_RRSR_V1\t\t\t\t(Offset 0x06FC) */\n\n#define BIT_SHIFT_WMAC_CSI_RRSC_BITMAP 4\n#define BIT_MASK_WMAC_CSI_RRSC_BITMAP 0xffffff\n#define BIT_WMAC_CSI_RRSC_BITMAP(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_CSI_RRSC_BITMAP)                                 \\\n\t << BIT_SHIFT_WMAC_CSI_RRSC_BITMAP)\n#define BITS_WMAC_CSI_RRSC_BITMAP                                              \\\n\t(BIT_MASK_WMAC_CSI_RRSC_BITMAP << BIT_SHIFT_WMAC_CSI_RRSC_BITMAP)\n#define BIT_CLEAR_WMAC_CSI_RRSC_BITMAP(x) ((x) & (~BITS_WMAC_CSI_RRSC_BITMAP))\n#define BIT_GET_WMAC_CSI_RRSC_BITMAP(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_CSI_RRSC_BITMAP) &                             \\\n\t BIT_MASK_WMAC_CSI_RRSC_BITMAP)\n#define BIT_SET_WMAC_CSI_RRSC_BITMAP(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_CSI_RRSC_BITMAP(x) | BIT_WMAC_CSI_RRSC_BITMAP(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_TX_CSI_RPT_PARAM_BW80\t\t(Offset 0x06FC) */\n\n#define BIT_SHIFT_R_WMAC_BFINFO_80M_0 0\n#define BIT_MASK_R_WMAC_BFINFO_80M_0 0xfff\n#define BIT_R_WMAC_BFINFO_80M_0(x)                                             \\\n\t(((x) & BIT_MASK_R_WMAC_BFINFO_80M_0) << BIT_SHIFT_R_WMAC_BFINFO_80M_0)\n#define BITS_R_WMAC_BFINFO_80M_0                                               \\\n\t(BIT_MASK_R_WMAC_BFINFO_80M_0 << BIT_SHIFT_R_WMAC_BFINFO_80M_0)\n#define BIT_CLEAR_R_WMAC_BFINFO_80M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_80M_0))\n#define BIT_GET_R_WMAC_BFINFO_80M_0(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_0) & BIT_MASK_R_WMAC_BFINFO_80M_0)\n#define BIT_SET_R_WMAC_BFINFO_80M_0(x, v)                                      \\\n\t(BIT_CLEAR_R_WMAC_BFINFO_80M_0(x) | BIT_R_WMAC_BFINFO_80M_0(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CSI_PTR\t\t\t\t(Offset 0x06FC) */\n\n#define BIT_SHIFT_CSI_WADDR_LATCH_V2 0\n#define BIT_MASK_CSI_WADDR_LATCH_V2 0xffff\n#define BIT_CSI_WADDR_LATCH_V2(x)                                              \\\n\t(((x) & BIT_MASK_CSI_WADDR_LATCH_V2) << BIT_SHIFT_CSI_WADDR_LATCH_V2)\n#define BITS_CSI_WADDR_LATCH_V2                                                \\\n\t(BIT_MASK_CSI_WADDR_LATCH_V2 << BIT_SHIFT_CSI_WADDR_LATCH_V2)\n#define BIT_CLEAR_CSI_WADDR_LATCH_V2(x) ((x) & (~BITS_CSI_WADDR_LATCH_V2))\n#define BIT_GET_CSI_WADDR_LATCH_V2(x)                                          \\\n\t(((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V2) & BIT_MASK_CSI_WADDR_LATCH_V2)\n#define BIT_SET_CSI_WADDR_LATCH_V2(x, v)                                       \\\n\t(BIT_CLEAR_CSI_WADDR_LATCH_V2(x) | BIT_CSI_WADDR_LATCH_V2(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_CSI_RRSR_V1\t\t\t\t(Offset 0x06FC) */\n\n#define BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH 0\n#define BIT_MASK_WMAC_CSI_OFDM_LEN_TH 0xf\n#define BIT_WMAC_CSI_OFDM_LEN_TH(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_CSI_OFDM_LEN_TH)                                 \\\n\t << BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH)\n#define BITS_WMAC_CSI_OFDM_LEN_TH                                              \\\n\t(BIT_MASK_WMAC_CSI_OFDM_LEN_TH << BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH)\n#define BIT_CLEAR_WMAC_CSI_OFDM_LEN_TH(x) ((x) & (~BITS_WMAC_CSI_OFDM_LEN_TH))\n#define BIT_GET_WMAC_CSI_OFDM_LEN_TH(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH) &                             \\\n\t BIT_MASK_WMAC_CSI_OFDM_LEN_TH)\n#define BIT_SET_WMAC_CSI_OFDM_LEN_TH(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_CSI_OFDM_LEN_TH(x) | BIT_WMAC_CSI_OFDM_LEN_TH(v))\n\n#define BIT_SHIFT_CSI_PARA_RDY_DLYCNT 0\n#define BIT_MASK_CSI_PARA_RDY_DLYCNT 0x1f\n#define BIT_CSI_PARA_RDY_DLYCNT(x)                                             \\\n\t(((x) & BIT_MASK_CSI_PARA_RDY_DLYCNT) << BIT_SHIFT_CSI_PARA_RDY_DLYCNT)\n#define BITS_CSI_PARA_RDY_DLYCNT                                               \\\n\t(BIT_MASK_CSI_PARA_RDY_DLYCNT << BIT_SHIFT_CSI_PARA_RDY_DLYCNT)\n#define BIT_CLEAR_CSI_PARA_RDY_DLYCNT(x) ((x) & (~BITS_CSI_PARA_RDY_DLYCNT))\n#define BIT_GET_CSI_PARA_RDY_DLYCNT(x)                                         \\\n\t(((x) >> BIT_SHIFT_CSI_PARA_RDY_DLYCNT) & BIT_MASK_CSI_PARA_RDY_DLYCNT)\n#define BIT_SET_CSI_PARA_RDY_DLYCNT(x, v)                                      \\\n\t(BIT_CLEAR_CSI_PARA_RDY_DLYCNT(x) | BIT_CSI_PARA_RDY_DLYCNT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n/* 2 REG_MACID1\t\t\t\t(Offset 0x0700) */\n\n#define BIT_SHIFT_MACID1 0\n#define BIT_MASK_MACID1 0xffffffffffffL\n#define BIT_MACID1(x) (((x) & BIT_MASK_MACID1) << BIT_SHIFT_MACID1)\n#define BITS_MACID1 (BIT_MASK_MACID1 << BIT_SHIFT_MACID1)\n#define BIT_CLEAR_MACID1(x) ((x) & (~BITS_MACID1))\n#define BIT_GET_MACID1(x) (((x) >> BIT_SHIFT_MACID1) & BIT_MASK_MACID1)\n#define BIT_SET_MACID1(x, v) (BIT_CLEAR_MACID1(x) | BIT_MACID1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MACID1\t\t\t\t(Offset 0x0700) */\n\n#define BIT_SHIFT_MACID1_0 0\n#define BIT_MASK_MACID1_0 0xffffffffL\n#define BIT_MACID1_0(x) (((x) & BIT_MASK_MACID1_0) << BIT_SHIFT_MACID1_0)\n#define BITS_MACID1_0 (BIT_MASK_MACID1_0 << BIT_SHIFT_MACID1_0)\n#define BIT_CLEAR_MACID1_0(x) ((x) & (~BITS_MACID1_0))\n#define BIT_GET_MACID1_0(x) (((x) >> BIT_SHIFT_MACID1_0) & BIT_MASK_MACID1_0)\n#define BIT_SET_MACID1_0(x, v) (BIT_CLEAR_MACID1_0(x) | BIT_MACID1_0(v))\n\n/* 2 REG_MACID1_1\t\t\t\t(Offset 0x0704) */\n\n#define BIT_SHIFT_MACID1_1 0\n#define BIT_MASK_MACID1_1 0xffff\n#define BIT_MACID1_1(x) (((x) & BIT_MASK_MACID1_1) << BIT_SHIFT_MACID1_1)\n#define BITS_MACID1_1 (BIT_MASK_MACID1_1 << BIT_SHIFT_MACID1_1)\n#define BIT_CLEAR_MACID1_1(x) ((x) & (~BITS_MACID1_1))\n#define BIT_GET_MACID1_1(x) (((x) >> BIT_SHIFT_MACID1_1) & BIT_MASK_MACID1_1)\n#define BIT_SET_MACID1_1(x, v) (BIT_CLEAR_MACID1_1(x) | BIT_MACID1_1(v))\n\n/* 2 REG_BSSID1\t\t\t\t(Offset 0x0708) */\n\n#define BIT_SHIFT_BSSID1_0 0\n#define BIT_MASK_BSSID1_0 0xffffffffL\n#define BIT_BSSID1_0(x) (((x) & BIT_MASK_BSSID1_0) << BIT_SHIFT_BSSID1_0)\n#define BITS_BSSID1_0 (BIT_MASK_BSSID1_0 << BIT_SHIFT_BSSID1_0)\n#define BIT_CLEAR_BSSID1_0(x) ((x) & (~BITS_BSSID1_0))\n#define BIT_GET_BSSID1_0(x) (((x) >> BIT_SHIFT_BSSID1_0) & BIT_MASK_BSSID1_0)\n#define BIT_SET_BSSID1_0(x, v) (BIT_CLEAR_BSSID1_0(x) | BIT_BSSID1_0(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_BSSID1\t\t\t\t(Offset 0x0708) */\n\n#define BIT_SHIFT_BSSID1 0\n#define BIT_MASK_BSSID1 0xffffffffffffL\n#define BIT_BSSID1(x) (((x) & BIT_MASK_BSSID1) << BIT_SHIFT_BSSID1)\n#define BITS_BSSID1 (BIT_MASK_BSSID1 << BIT_SHIFT_BSSID1)\n#define BIT_CLEAR_BSSID1(x) ((x) & (~BITS_BSSID1))\n#define BIT_GET_BSSID1(x) (((x) >> BIT_SHIFT_BSSID1) & BIT_MASK_BSSID1)\n#define BIT_SET_BSSID1(x, v) (BIT_CLEAR_BSSID1(x) | BIT_BSSID1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PCIE_CFG_FORCE_LINK_L\t\t(Offset 0x0709) */\n\n#define BIT_PCIE_CFG_FORCE_EN BIT(7)\n\n/* 2 REG_PCIE_CFG_FORCE_LINK_H\t\t(Offset 0x070A) */\n\n#define BIT_PCIE_CFG_TRXACT_DIS_IDLE_TIMER BIT(6)\n\n#define BIT_SHIFT_PCIE_CFG_LINK_STATE 0\n#define BIT_MASK_PCIE_CFG_LINK_STATE 0x3f\n#define BIT_PCIE_CFG_LINK_STATE(x)                                             \\\n\t(((x) & BIT_MASK_PCIE_CFG_LINK_STATE) << BIT_SHIFT_PCIE_CFG_LINK_STATE)\n#define BITS_PCIE_CFG_LINK_STATE                                               \\\n\t(BIT_MASK_PCIE_CFG_LINK_STATE << BIT_SHIFT_PCIE_CFG_LINK_STATE)\n#define BIT_CLEAR_PCIE_CFG_LINK_STATE(x) ((x) & (~BITS_PCIE_CFG_LINK_STATE))\n#define BIT_GET_PCIE_CFG_LINK_STATE(x)                                         \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_LINK_STATE) & BIT_MASK_PCIE_CFG_LINK_STATE)\n#define BIT_SET_PCIE_CFG_LINK_STATE(x, v)                                      \\\n\t(BIT_CLEAR_PCIE_CFG_LINK_STATE(x) | BIT_PCIE_CFG_LINK_STATE(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BSSID1_1\t\t\t\t(Offset 0x070C) */\n\n#define BIT_SHIFT_BSSID1_1 0\n#define BIT_MASK_BSSID1_1 0xffff\n#define BIT_BSSID1_1(x) (((x) & BIT_MASK_BSSID1_1) << BIT_SHIFT_BSSID1_1)\n#define BITS_BSSID1_1 (BIT_MASK_BSSID1_1 << BIT_SHIFT_BSSID1_1)\n#define BIT_CLEAR_BSSID1_1(x) ((x) & (~BITS_BSSID1_1))\n#define BIT_GET_BSSID1_1(x) (((x) >> BIT_SHIFT_BSSID1_1) & BIT_MASK_BSSID1_1)\n#define BIT_SET_BSSID1_1(x, v) (BIT_CLEAR_BSSID1_1(x) | BIT_BSSID1_1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY\t(Offset 0x070C) */\n\n#define BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY 0\n#define BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY 0xff\n#define BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x)                                  \\\n\t(((x) & BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY)                       \\\n\t << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY)\n#define BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY                                    \\\n\t(BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY                               \\\n\t << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY)\n#define BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x)                            \\\n\t((x) & (~BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY))\n#define BIT_GET_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x)                              \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY) &                   \\\n\t BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY)\n#define BIT_SET_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x, v)                           \\\n\t(BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) |                         \\\n\t BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY(v))\n\n/* 2 REG_PCIE_CFG_CX_NFTS\t\t\t(Offset 0x070D) */\n\n#define BIT_SHIFT_PCIE_CFG_CX_NFTS 0\n#define BIT_MASK_PCIE_CFG_CX_NFTS 0xff\n#define BIT_PCIE_CFG_CX_NFTS(x)                                                \\\n\t(((x) & BIT_MASK_PCIE_CFG_CX_NFTS) << BIT_SHIFT_PCIE_CFG_CX_NFTS)\n#define BITS_PCIE_CFG_CX_NFTS                                                  \\\n\t(BIT_MASK_PCIE_CFG_CX_NFTS << BIT_SHIFT_PCIE_CFG_CX_NFTS)\n#define BIT_CLEAR_PCIE_CFG_CX_NFTS(x) ((x) & (~BITS_PCIE_CFG_CX_NFTS))\n#define BIT_GET_PCIE_CFG_CX_NFTS(x)                                            \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_CX_NFTS) & BIT_MASK_PCIE_CFG_CX_NFTS)\n#define BIT_SET_PCIE_CFG_CX_NFTS(x, v)                                         \\\n\t(BIT_CLEAR_PCIE_CFG_CX_NFTS(x) | BIT_PCIE_CFG_CX_NFTS(v))\n\n/* 2 REG_PCIE_CFG_DEFAULT_ENTR_LATENCY\t(Offset 0x070F) */\n\n#define BIT_PCIE_CFG_REAL_EN_L0S BIT(7)\n#define BIT_PCIE_CFG_ENTER_ASPM BIT(6)\n\n#define BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY 3\n#define BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY 0x7\n#define BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x)                                \\\n\t(((x) & BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY)                     \\\n\t << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY)\n#define BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY                                  \\\n\t(BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY                             \\\n\t << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY)\n#define BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x)                          \\\n\t((x) & (~BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY))\n#define BIT_GET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x)                            \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) &                 \\\n\t BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY)\n#define BIT_SET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x, v)                         \\\n\t(BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) |                       \\\n\t BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(v))\n\n#define BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY 0\n#define BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY 0x7\n#define BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x)                               \\\n\t(((x) & BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY)                    \\\n\t << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY)\n#define BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY                                 \\\n\t(BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY                            \\\n\t << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY)\n#define BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x)                         \\\n\t((x) & (~BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY))\n#define BIT_GET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x)                           \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) &                \\\n\t BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY)\n#define BIT_SET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x, v)                        \\\n\t(BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) |                      \\\n\t BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_PSR_RPT1\t\t\t(Offset 0x0710) */\n\n#define BIT_SHIFT_DTIM_CNT1 24\n#define BIT_MASK_DTIM_CNT1 0xff\n#define BIT_DTIM_CNT1(x) (((x) & BIT_MASK_DTIM_CNT1) << BIT_SHIFT_DTIM_CNT1)\n#define BITS_DTIM_CNT1 (BIT_MASK_DTIM_CNT1 << BIT_SHIFT_DTIM_CNT1)\n#define BIT_CLEAR_DTIM_CNT1(x) ((x) & (~BITS_DTIM_CNT1))\n#define BIT_GET_DTIM_CNT1(x) (((x) >> BIT_SHIFT_DTIM_CNT1) & BIT_MASK_DTIM_CNT1)\n#define BIT_SET_DTIM_CNT1(x, v) (BIT_CLEAR_DTIM_CNT1(x) | BIT_DTIM_CNT1(v))\n\n#define BIT_SHIFT_DTIM_PERIOD1 16\n#define BIT_MASK_DTIM_PERIOD1 0xff\n#define BIT_DTIM_PERIOD1(x)                                                    \\\n\t(((x) & BIT_MASK_DTIM_PERIOD1) << BIT_SHIFT_DTIM_PERIOD1)\n#define BITS_DTIM_PERIOD1 (BIT_MASK_DTIM_PERIOD1 << BIT_SHIFT_DTIM_PERIOD1)\n#define BIT_CLEAR_DTIM_PERIOD1(x) ((x) & (~BITS_DTIM_PERIOD1))\n#define BIT_GET_DTIM_PERIOD1(x)                                                \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD1) & BIT_MASK_DTIM_PERIOD1)\n#define BIT_SET_DTIM_PERIOD1(x, v)                                             \\\n\t(BIT_CLEAR_DTIM_PERIOD1(x) | BIT_DTIM_PERIOD1(v))\n\n#define BIT_DTIM1 BIT(15)\n#define BIT_TIM1 BIT(14)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_PSR_RPT1\t\t\t(Offset 0x0710) */\n\n#define BIT_BCN_VALID_V2 BIT(13)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_PSR_RPT1\t\t\t(Offset 0x0710) */\n\n#define BIT_SHIFT_PS_AID_1 0\n#define BIT_MASK_PS_AID_1 0x7ff\n#define BIT_PS_AID_1(x) (((x) & BIT_MASK_PS_AID_1) << BIT_SHIFT_PS_AID_1)\n#define BITS_PS_AID_1 (BIT_MASK_PS_AID_1 << BIT_SHIFT_PS_AID_1)\n#define BIT_CLEAR_PS_AID_1(x) ((x) & (~BITS_PS_AID_1))\n#define BIT_GET_PS_AID_1(x) (((x) >> BIT_SHIFT_PS_AID_1) & BIT_MASK_PS_AID_1)\n#define BIT_SET_PS_AID_1(x, v) (BIT_CLEAR_PS_AID_1(x) | BIT_PS_AID_1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PCIE_CFG_L1_MISC_SEL\t\t(Offset 0x0711) */\n\n#define BIT_PCIE_CFG_L1_RIDLE_SEL BIT(6)\n#define BIT_PCIE_CFG_L1_TIMEOUT_SEL BIT(5)\n#define BIT_PCIE_CFG_L1_EIDLE_SEL BIT(4)\n\n#define BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE 0\n#define BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE 0xf\n#define BIT_PCIE_CFG_DEFAULT_LINK_RATE(x)                                      \\\n\t(((x) & BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE)                           \\\n\t << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE)\n#define BITS_PCIE_CFG_DEFAULT_LINK_RATE                                        \\\n\t(BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE                                   \\\n\t << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE)\n#define BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE(x)                                \\\n\t((x) & (~BITS_PCIE_CFG_DEFAULT_LINK_RATE))\n#define BIT_GET_PCIE_CFG_DEFAULT_LINK_RATE(x)                                  \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE) &                       \\\n\t BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE)\n#define BIT_SET_PCIE_CFG_DEFAULT_LINK_RATE(x, v)                               \\\n\t(BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE(x) |                             \\\n\t BIT_PCIE_CFG_DEFAULT_LINK_RATE(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_ASSOCIATED_BFMEE_SEL\t\t(Offset 0x0714) */\n\n#define BIT_SHIFT_RD_BF_SEL 29\n#define BIT_MASK_RD_BF_SEL 0x7\n#define BIT_RD_BF_SEL(x) (((x) & BIT_MASK_RD_BF_SEL) << BIT_SHIFT_RD_BF_SEL)\n#define BITS_RD_BF_SEL (BIT_MASK_RD_BF_SEL << BIT_SHIFT_RD_BF_SEL)\n#define BIT_CLEAR_RD_BF_SEL(x) ((x) & (~BITS_RD_BF_SEL))\n#define BIT_GET_RD_BF_SEL(x) (((x) >> BIT_SHIFT_RD_BF_SEL) & BIT_MASK_RD_BF_SEL)\n#define BIT_SET_RD_BF_SEL(x, v) (BIT_CLEAR_RD_BF_SEL(x) | BIT_RD_BF_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_SHIFT_NDP_RX_STANDBY_TIMER 24\n#define BIT_MASK_NDP_RX_STANDBY_TIMER 0xff\n#define BIT_NDP_RX_STANDBY_TIMER(x)                                            \\\n\t(((x) & BIT_MASK_NDP_RX_STANDBY_TIMER)                                 \\\n\t << BIT_SHIFT_NDP_RX_STANDBY_TIMER)\n#define BITS_NDP_RX_STANDBY_TIMER                                              \\\n\t(BIT_MASK_NDP_RX_STANDBY_TIMER << BIT_SHIFT_NDP_RX_STANDBY_TIMER)\n#define BIT_CLEAR_NDP_RX_STANDBY_TIMER(x) ((x) & (~BITS_NDP_RX_STANDBY_TIMER))\n#define BIT_GET_NDP_RX_STANDBY_TIMER(x)                                        \\\n\t(((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER) &                             \\\n\t BIT_MASK_NDP_RX_STANDBY_TIMER)\n#define BIT_SET_NDP_RX_STANDBY_TIMER(x, v)                                     \\\n\t(BIT_CLEAR_NDP_RX_STANDBY_TIMER(x) | BIT_NDP_RX_STANDBY_TIMER(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_R_WMAC_CHK_RPTPOLL_A2_DIS BIT(23)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_WMAC_CHK_RPTPOLL_A2_DIS BIT(23)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_R_WMAC_CHK_UCNDPA_A2_DIS BIT(22)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_WMAC_CHK_UCNDPA_A2_DIS BIT(22)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_ANTTRN_SWITCH BIT(19)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_SHIFT_CSI_RPT_OFFSET_HT 16\n#define BIT_MASK_CSI_RPT_OFFSET_HT 0xff\n#define BIT_CSI_RPT_OFFSET_HT(x)                                               \\\n\t(((x) & BIT_MASK_CSI_RPT_OFFSET_HT) << BIT_SHIFT_CSI_RPT_OFFSET_HT)\n#define BITS_CSI_RPT_OFFSET_HT                                                 \\\n\t(BIT_MASK_CSI_RPT_OFFSET_HT << BIT_SHIFT_CSI_RPT_OFFSET_HT)\n#define BIT_CLEAR_CSI_RPT_OFFSET_HT(x) ((x) & (~BITS_CSI_RPT_OFFSET_HT))\n#define BIT_GET_CSI_RPT_OFFSET_HT(x)                                           \\\n\t(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT) & BIT_MASK_CSI_RPT_OFFSET_HT)\n#define BIT_SET_CSI_RPT_OFFSET_HT(x, v)                                        \\\n\t(BIT_CLEAR_CSI_RPT_OFFSET_HT(x) | BIT_CSI_RPT_OFFSET_HT(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_SHIFT_CSI_RPT_OFFSET_HT_V1 16\n#define BIT_MASK_CSI_RPT_OFFSET_HT_V1 0x3f\n#define BIT_CSI_RPT_OFFSET_HT_V1(x)                                            \\\n\t(((x) & BIT_MASK_CSI_RPT_OFFSET_HT_V1)                                 \\\n\t << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1)\n#define BITS_CSI_RPT_OFFSET_HT_V1                                              \\\n\t(BIT_MASK_CSI_RPT_OFFSET_HT_V1 << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1)\n#define BIT_CLEAR_CSI_RPT_OFFSET_HT_V1(x) ((x) & (~BITS_CSI_RPT_OFFSET_HT_V1))\n#define BIT_GET_CSI_RPT_OFFSET_HT_V1(x)                                        \\\n\t(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_V1) &                             \\\n\t BIT_MASK_CSI_RPT_OFFSET_HT_V1)\n#define BIT_SET_CSI_RPT_OFFSET_HT_V1(x, v)                                     \\\n\t(BIT_CLEAR_CSI_RPT_OFFSET_HT_V1(x) | BIT_CSI_RPT_OFFSET_HT_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_R_WMAC_OFFSET_RPTPOLL_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_WMAC_OFFSET_RPTPOLL_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL BIT(15)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_R_WMAC_CSI_CHKSUM_DIS BIT(14)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_WMAC_CSI_CHKSUM_DIS BIT(14)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_NDPVLD_POS_RST_FFPTR_DIS BIT(14)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_SHIFT_R_WMAC_VHT_CATEGORY 8\n#define BIT_MASK_R_WMAC_VHT_CATEGORY 0xff\n#define BIT_R_WMAC_VHT_CATEGORY(x)                                             \\\n\t(((x) & BIT_MASK_R_WMAC_VHT_CATEGORY) << BIT_SHIFT_R_WMAC_VHT_CATEGORY)\n#define BITS_R_WMAC_VHT_CATEGORY                                               \\\n\t(BIT_MASK_R_WMAC_VHT_CATEGORY << BIT_SHIFT_R_WMAC_VHT_CATEGORY)\n#define BIT_CLEAR_R_WMAC_VHT_CATEGORY(x) ((x) & (~BITS_R_WMAC_VHT_CATEGORY))\n#define BIT_GET_R_WMAC_VHT_CATEGORY(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY) & BIT_MASK_R_WMAC_VHT_CATEGORY)\n#define BIT_SET_R_WMAC_VHT_CATEGORY(x, v)                                      \\\n\t(BIT_CLEAR_R_WMAC_VHT_CATEGORY(x) | BIT_R_WMAC_VHT_CATEGORY(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_SHIFT_CSI_RPT_OFFSET_VHT 8\n#define BIT_MASK_CSI_RPT_OFFSET_VHT 0xff\n#define BIT_CSI_RPT_OFFSET_VHT(x)                                              \\\n\t(((x) & BIT_MASK_CSI_RPT_OFFSET_VHT) << BIT_SHIFT_CSI_RPT_OFFSET_VHT)\n#define BITS_CSI_RPT_OFFSET_VHT                                                \\\n\t(BIT_MASK_CSI_RPT_OFFSET_VHT << BIT_SHIFT_CSI_RPT_OFFSET_VHT)\n#define BIT_CLEAR_CSI_RPT_OFFSET_VHT(x) ((x) & (~BITS_CSI_RPT_OFFSET_VHT))\n#define BIT_GET_CSI_RPT_OFFSET_VHT(x)                                          \\\n\t(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT) & BIT_MASK_CSI_RPT_OFFSET_VHT)\n#define BIT_SET_CSI_RPT_OFFSET_VHT(x, v)                                       \\\n\t(BIT_CLEAR_CSI_RPT_OFFSET_VHT(x) | BIT_CSI_RPT_OFFSET_VHT(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1 8\n#define BIT_MASK_R_WMAC_VHT_CATEGORY_V1 0x3f\n#define BIT_R_WMAC_VHT_CATEGORY_V1(x)                                          \\\n\t(((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_V1)                               \\\n\t << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1)\n#define BITS_R_WMAC_VHT_CATEGORY_V1                                            \\\n\t(BIT_MASK_R_WMAC_VHT_CATEGORY_V1 << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1)\n#define BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1(x)                                    \\\n\t((x) & (~BITS_R_WMAC_VHT_CATEGORY_V1))\n#define BIT_GET_R_WMAC_VHT_CATEGORY_V1(x)                                      \\\n\t(((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1) &                           \\\n\t BIT_MASK_R_WMAC_VHT_CATEGORY_V1)\n#define BIT_SET_R_WMAC_VHT_CATEGORY_V1(x, v)                                   \\\n\t(BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1(x) | BIT_R_WMAC_VHT_CATEGORY_V1(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1 8\n#define BIT_MASK_CSI_RPT_OFFSET_VHT_V1 0x3f\n#define BIT_CSI_RPT_OFFSET_VHT_V1(x)                                           \\\n\t(((x) & BIT_MASK_CSI_RPT_OFFSET_VHT_V1)                                \\\n\t << BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1)\n#define BITS_CSI_RPT_OFFSET_VHT_V1                                             \\\n\t(BIT_MASK_CSI_RPT_OFFSET_VHT_V1 << BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1)\n#define BIT_CLEAR_CSI_RPT_OFFSET_VHT_V1(x) ((x) & (~BITS_CSI_RPT_OFFSET_VHT_V1))\n#define BIT_GET_CSI_RPT_OFFSET_VHT_V1(x)                                       \\\n\t(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1) &                            \\\n\t BIT_MASK_CSI_RPT_OFFSET_VHT_V1)\n#define BIT_SET_CSI_RPT_OFFSET_VHT_V1(x, v)                                    \\\n\t(BIT_CLEAR_CSI_RPT_OFFSET_VHT_V1(x) | BIT_CSI_RPT_OFFSET_VHT_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1 8\n#define BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1 0x3f\n#define BIT_R_CSI_RPT_OFFSET_VHT_V1(x)                                         \\\n\t(((x) & BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1)                              \\\n\t << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1)\n#define BITS_R_CSI_RPT_OFFSET_VHT_V1                                           \\\n\t(BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1 << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1)\n#define BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1(x)                                   \\\n\t((x) & (~BITS_R_CSI_RPT_OFFSET_VHT_V1))\n#define BIT_GET_R_CSI_RPT_OFFSET_VHT_V1(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1) &                          \\\n\t BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1)\n#define BIT_SET_R_CSI_RPT_OFFSET_VHT_V1(x, v)                                  \\\n\t(BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1(x) | BIT_R_CSI_RPT_OFFSET_VHT_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_R_WMAC_USE_NSTS BIT(7)\n#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC BIT(6)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */\n\n#define BIT_PCIE_CFG_REAL_PTM_ENABLE BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC BIT(5)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */\n\n#define BIT_PCIE_CFG_REAL_EN_L1SUB BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SND_PTCL_CTRL\t\t\t(Offset 0x0718) */\n\n#define BIT_R_WMAC_BFPARAM_SEL BIT(4)\n#define BIT_R_WMAC_CSISEQ_SEL BIT(3)\n#define BIT_R_WMAC_CSI_WITHHTC_EN BIT(2)\n#define BIT_R_WMAC_HT_NDPA_EN BIT(1)\n#define BIT_R_WMAC_VHT_NDPA_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */\n\n#define BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM 0\n#define BIT_MASK_PCIE_CFG_MAX_FUNC_NUM 0x7\n#define BIT_PCIE_CFG_MAX_FUNC_NUM(x)                                           \\\n\t(((x) & BIT_MASK_PCIE_CFG_MAX_FUNC_NUM)                                \\\n\t << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM)\n#define BITS_PCIE_CFG_MAX_FUNC_NUM                                             \\\n\t(BIT_MASK_PCIE_CFG_MAX_FUNC_NUM << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM)\n#define BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM(x) ((x) & (~BITS_PCIE_CFG_MAX_FUNC_NUM))\n#define BIT_GET_PCIE_CFG_MAX_FUNC_NUM(x)                                       \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM) &                            \\\n\t BIT_MASK_PCIE_CFG_MAX_FUNC_NUM)\n#define BIT_SET_PCIE_CFG_MAX_FUNC_NUM(x, v)                                    \\\n\t(BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM(x) | BIT_PCIE_CFG_MAX_FUNC_NUM(v))\n\n/* 2 REG_PCIE_CFG_FORCE_CLKREQ_N_PAD\t\t(Offset 0x0719) */\n\n#define BIT_PCIE_CFG_REAL_EN_64BITS BIT(5)\n#define BIT_PCIE_CFG_REAL_EN_CLKREQ BIT(4)\n#define BIT_PCIE_CFG_REAL_EN_L1 BIT(3)\n#define BIT_PCIE_CFG_WAKE_N_EN BIT(2)\n#define BIT_PCIE_CFG_BYPASS_LTR_OPTION BIT(1)\n#define BIT_PCIE_CFG_FORCE_CLKREQ_N_PAD BIT(0)\n\n/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY (Offset 0x071A) */\n\n#define BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK 0\n#define BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK 0xff\n#define BIT_PCIE_CFG_TIMER_MOD_ACK_NAK(x)                                      \\\n\t(((x) & BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK)                           \\\n\t << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK)\n#define BITS_PCIE_CFG_TIMER_MOD_ACK_NAK                                        \\\n\t(BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK                                   \\\n\t << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK)\n#define BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK(x)                                \\\n\t((x) & (~BITS_PCIE_CFG_TIMER_MOD_ACK_NAK))\n#define BIT_GET_PCIE_CFG_TIMER_MOD_ACK_NAK(x)                                  \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK) &                       \\\n\t BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK)\n#define BIT_SET_PCIE_CFG_TIMER_MOD_ACK_NAK(x, v)                               \\\n\t(BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK(x) |                             \\\n\t BIT_PCIE_CFG_TIMER_MOD_ACK_NAK(v))\n\n/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG (Offset 0x071B) */\n\n#define BIT_PCIE_CFG_BYPASS_L1_SUBSTATE_OPTION BIT(7)\n\n#define BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR 5\n#define BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR 0x3\n#define BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x)                               \\\n\t(((x) & BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR)                    \\\n\t << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR)\n#define BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR                                 \\\n\t(BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR                            \\\n\t << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR)\n#define BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x)                         \\\n\t((x) & (~BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR))\n#define BIT_GET_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x)                           \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR) &                \\\n\t BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR)\n#define BIT_SET_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x, v)                        \\\n\t(BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) |                      \\\n\t BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR(v))\n\n#define BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER 0\n#define BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER 0x1f\n#define BIT_PCIE_CFG_UPDATE_FREQ_TIMER(x)                                      \\\n\t(((x) & BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER)                           \\\n\t << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER)\n#define BITS_PCIE_CFG_UPDATE_FREQ_TIMER                                        \\\n\t(BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER                                   \\\n\t << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER)\n#define BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER(x)                                \\\n\t((x) & (~BITS_PCIE_CFG_UPDATE_FREQ_TIMER))\n#define BIT_GET_PCIE_CFG_UPDATE_FREQ_TIMER(x)                                  \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER) &                       \\\n\t BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER)\n#define BIT_SET_PCIE_CFG_UPDATE_FREQ_TIMER(x, v)                               \\\n\t(BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER(x) |                             \\\n\t BIT_PCIE_CFG_UPDATE_FREQ_TIMER(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RX_CSI_RPT_INFO\t\t\t(Offset 0x071C) */\n\n#define BIT_WMAC_CHECK_SOUNDING_SEQ BIT(30)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_L\t(Offset 0x071C) */\n\n#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L 0\n#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L 0xff\n#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L(x)                                   \\\n\t(((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L)                        \\\n\t << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L)\n#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L                                     \\\n\t(BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L                                \\\n\t << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L)\n#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L(x)                             \\\n\t((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L))\n#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_L(x)                               \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L) &                    \\\n\t BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L)\n#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_L(x, v)                            \\\n\t(BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) |                          \\\n\t BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L(v))\n\n/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_H\t(Offset 0x071D) */\n\n#define BIT_PCIE_CFG_DISABLE_FC_WATCHDOG_TIMER BIT(7)\n\n#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H 0\n#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H 0x7\n#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H(x)                                   \\\n\t(((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H)                        \\\n\t << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H)\n#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H                                     \\\n\t(BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H                                \\\n\t << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H)\n#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H(x)                             \\\n\t((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H))\n#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_H(x)                               \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H) &                    \\\n\t BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H)\n#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_H(x, v)                            \\\n\t(BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) |                          \\\n\t BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_NS_ARP_CTRL\t\t\t\t(Offset 0x0720) */\n\n#define BIT_R_WMAC_NSARP_RSPEN BIT(15)\n#define BIT_R_WMAC_NSARP_RARP BIT(9)\n#define BIT_R_WMAC_NSARP_RIPV6 BIT(8)\n\n#define BIT_SHIFT_R_WMAC_NSARP_MODEN 6\n#define BIT_MASK_R_WMAC_NSARP_MODEN 0x3\n#define BIT_R_WMAC_NSARP_MODEN(x)                                              \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_MODEN) << BIT_SHIFT_R_WMAC_NSARP_MODEN)\n#define BITS_R_WMAC_NSARP_MODEN                                                \\\n\t(BIT_MASK_R_WMAC_NSARP_MODEN << BIT_SHIFT_R_WMAC_NSARP_MODEN)\n#define BIT_CLEAR_R_WMAC_NSARP_MODEN(x) ((x) & (~BITS_R_WMAC_NSARP_MODEN))\n#define BIT_GET_R_WMAC_NSARP_MODEN(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN) & BIT_MASK_R_WMAC_NSARP_MODEN)\n#define BIT_SET_R_WMAC_NSARP_MODEN(x, v)                                       \\\n\t(BIT_CLEAR_R_WMAC_NSARP_MODEN(x) | BIT_R_WMAC_NSARP_MODEN(v))\n\n#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP 4\n#define BIT_MASK_R_WMAC_NSARP_RSPFTP 0x3\n#define BIT_R_WMAC_NSARP_RSPFTP(x)                                             \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP)\n#define BITS_R_WMAC_NSARP_RSPFTP                                               \\\n\t(BIT_MASK_R_WMAC_NSARP_RSPFTP << BIT_SHIFT_R_WMAC_NSARP_RSPFTP)\n#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP(x) ((x) & (~BITS_R_WMAC_NSARP_RSPFTP))\n#define BIT_GET_R_WMAC_NSARP_RSPFTP(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP) & BIT_MASK_R_WMAC_NSARP_RSPFTP)\n#define BIT_SET_R_WMAC_NSARP_RSPFTP(x, v)                                      \\\n\t(BIT_CLEAR_R_WMAC_NSARP_RSPFTP(x) | BIT_R_WMAC_NSARP_RSPFTP(v))\n\n#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC 0\n#define BIT_MASK_R_WMAC_NSARP_RSPSEC 0xf\n#define BIT_R_WMAC_NSARP_RSPSEC(x)                                             \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC)\n#define BITS_R_WMAC_NSARP_RSPSEC                                               \\\n\t(BIT_MASK_R_WMAC_NSARP_RSPSEC << BIT_SHIFT_R_WMAC_NSARP_RSPSEC)\n#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC(x) ((x) & (~BITS_R_WMAC_NSARP_RSPSEC))\n#define BIT_GET_R_WMAC_NSARP_RSPSEC(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC) & BIT_MASK_R_WMAC_NSARP_RSPSEC)\n#define BIT_SET_R_WMAC_NSARP_RSPSEC(x, v)                                      \\\n\t(BIT_CLEAR_R_WMAC_NSARP_RSPSEC(x) | BIT_R_WMAC_NSARP_RSPSEC(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_NS_ARP_INFO\t\t\t\t(Offset 0x0724) */\n\n#define BIT_REQ_IS_MCNS BIT(23)\n#define BIT_REQ_IS_UCNS BIT(22)\n#define BIT_REQ_IS_USNS BIT(21)\n#define BIT_REQ_IS_ARP BIT(20)\n#define BIT_EXPRSP_MH_WITHQC BIT(19)\n\n#define BIT_SHIFT_EXPRSP_SECTYPE 16\n#define BIT_MASK_EXPRSP_SECTYPE 0x7\n#define BIT_EXPRSP_SECTYPE(x)                                                  \\\n\t(((x) & BIT_MASK_EXPRSP_SECTYPE) << BIT_SHIFT_EXPRSP_SECTYPE)\n#define BITS_EXPRSP_SECTYPE                                                    \\\n\t(BIT_MASK_EXPRSP_SECTYPE << BIT_SHIFT_EXPRSP_SECTYPE)\n#define BIT_CLEAR_EXPRSP_SECTYPE(x) ((x) & (~BITS_EXPRSP_SECTYPE))\n#define BIT_GET_EXPRSP_SECTYPE(x)                                              \\\n\t(((x) >> BIT_SHIFT_EXPRSP_SECTYPE) & BIT_MASK_EXPRSP_SECTYPE)\n#define BIT_SET_EXPRSP_SECTYPE(x, v)                                           \\\n\t(BIT_CLEAR_EXPRSP_SECTYPE(x) | BIT_EXPRSP_SECTYPE(v))\n\n#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0 8\n#define BIT_MASK_EXPRSP_CHKSM_7_TO_0 0xff\n#define BIT_EXPRSP_CHKSM_7_TO_0(x)                                             \\\n\t(((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0)\n#define BITS_EXPRSP_CHKSM_7_TO_0                                               \\\n\t(BIT_MASK_EXPRSP_CHKSM_7_TO_0 << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0)\n#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0(x) ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0))\n#define BIT_GET_EXPRSP_CHKSM_7_TO_0(x)                                         \\\n\t(((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) & BIT_MASK_EXPRSP_CHKSM_7_TO_0)\n#define BIT_SET_EXPRSP_CHKSM_7_TO_0(x, v)                                      \\\n\t(BIT_CLEAR_EXPRSP_CHKSM_7_TO_0(x) | BIT_EXPRSP_CHKSM_7_TO_0(v))\n\n#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8 0\n#define BIT_MASK_EXPRSP_CHKSM_15_TO_8 0xff\n#define BIT_EXPRSP_CHKSM_15_TO_8(x)                                            \\\n\t(((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8)                                 \\\n\t << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8)\n#define BITS_EXPRSP_CHKSM_15_TO_8                                              \\\n\t(BIT_MASK_EXPRSP_CHKSM_15_TO_8 << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8)\n#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8(x) ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8))\n#define BIT_GET_EXPRSP_CHKSM_15_TO_8(x)                                        \\\n\t(((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) &                             \\\n\t BIT_MASK_EXPRSP_CHKSM_15_TO_8)\n#define BIT_SET_EXPRSP_CHKSM_15_TO_8(x, v)                                     \\\n\t(BIT_CLEAR_EXPRSP_CHKSM_15_TO_8(x) | BIT_EXPRSP_CHKSM_15_TO_8(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PCIE_CFG_L1_UNIT_SEL\t\t(Offset 0x0724) */\n\n#define BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL 0\n#define BIT_MASK_PCIE_CFG_L1_UNIT_SEL 0xff\n#define BIT_PCIE_CFG_L1_UNIT_SEL(x)                                            \\\n\t(((x) & BIT_MASK_PCIE_CFG_L1_UNIT_SEL)                                 \\\n\t << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL)\n#define BITS_PCIE_CFG_L1_UNIT_SEL                                              \\\n\t(BIT_MASK_PCIE_CFG_L1_UNIT_SEL << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL)\n#define BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL(x) ((x) & (~BITS_PCIE_CFG_L1_UNIT_SEL))\n#define BIT_GET_PCIE_CFG_L1_UNIT_SEL(x)                                        \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL) &                             \\\n\t BIT_MASK_PCIE_CFG_L1_UNIT_SEL)\n#define BIT_SET_PCIE_CFG_L1_UNIT_SEL(x, v)                                     \\\n\t(BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL(x) | BIT_PCIE_CFG_L1_UNIT_SEL(v))\n\n/* 2 REG_PCIE_CFG_MIN_CLKREQ_SEL\t\t(Offset 0x0725) */\n\n#define BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL 0\n#define BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL 0xf\n#define BIT_PCIE_CFG_MIN_CLKREQ_SEL(x)                                         \\\n\t(((x) & BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL)                              \\\n\t << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL)\n#define BITS_PCIE_CFG_MIN_CLKREQ_SEL                                           \\\n\t(BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL)\n#define BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL(x)                                   \\\n\t((x) & (~BITS_PCIE_CFG_MIN_CLKREQ_SEL))\n#define BIT_GET_PCIE_CFG_MIN_CLKREQ_SEL(x)                                     \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL) &                          \\\n\t BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL)\n#define BIT_SET_PCIE_CFG_MIN_CLKREQ_SEL(x, v)                                  \\\n\t(BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL(x) | BIT_PCIE_CFG_MIN_CLKREQ_SEL(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BEAMFORMING_INFO_NSARP_V1\t\t(Offset 0x0728) */\n\n#define BIT_SHIFT_WMAC_ARPIP 0\n#define BIT_MASK_WMAC_ARPIP 0xffffffffL\n#define BIT_WMAC_ARPIP(x) (((x) & BIT_MASK_WMAC_ARPIP) << BIT_SHIFT_WMAC_ARPIP)\n#define BITS_WMAC_ARPIP (BIT_MASK_WMAC_ARPIP << BIT_SHIFT_WMAC_ARPIP)\n#define BIT_CLEAR_WMAC_ARPIP(x) ((x) & (~BITS_WMAC_ARPIP))\n#define BIT_GET_WMAC_ARPIP(x)                                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_ARPIP) & BIT_MASK_WMAC_ARPIP)\n#define BIT_SET_WMAC_ARPIP(x, v) (BIT_CLEAR_WMAC_ARPIP(x) | BIT_WMAC_ARPIP(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BEAMFORMING_INFO_NSARP\t\t(Offset 0x072C) */\n\n#define BIT_SHIFT_UPD_BFMEE_USERID 13\n#define BIT_MASK_UPD_BFMEE_USERID 0x7\n#define BIT_UPD_BFMEE_USERID(x)                                                \\\n\t(((x) & BIT_MASK_UPD_BFMEE_USERID) << BIT_SHIFT_UPD_BFMEE_USERID)\n#define BITS_UPD_BFMEE_USERID                                                  \\\n\t(BIT_MASK_UPD_BFMEE_USERID << BIT_SHIFT_UPD_BFMEE_USERID)\n#define BIT_CLEAR_UPD_BFMEE_USERID(x) ((x) & (~BITS_UPD_BFMEE_USERID))\n#define BIT_GET_UPD_BFMEE_USERID(x)                                            \\\n\t(((x) >> BIT_SHIFT_UPD_BFMEE_USERID) & BIT_MASK_UPD_BFMEE_USERID)\n#define BIT_SET_UPD_BFMEE_USERID(x, v)                                         \\\n\t(BIT_CLEAR_UPD_BFMEE_USERID(x) | BIT_UPD_BFMEE_USERID(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RX_CSI_RPT_INFO_V1\t\t\t(Offset 0x072C) */\n\n#define BIT_WRITE_USERID BIT(12)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BEAMFORMING_INFO_NSARP\t\t(Offset 0x072C) */\n\n#define BIT_UPD_BFMEE_FBTP BIT(12)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RX_CSI_RPT_INFO_V1\t\t\t(Offset 0x072C) */\n\n#define BIT_SHIFT_WRITE_BW 10\n#define BIT_MASK_WRITE_BW 0x3\n#define BIT_WRITE_BW(x) (((x) & BIT_MASK_WRITE_BW) << BIT_SHIFT_WRITE_BW)\n#define BITS_WRITE_BW (BIT_MASK_WRITE_BW << BIT_SHIFT_WRITE_BW)\n#define BIT_CLEAR_WRITE_BW(x) ((x) & (~BITS_WRITE_BW))\n#define BIT_GET_WRITE_BW(x) (((x) >> BIT_SHIFT_WRITE_BW) & BIT_MASK_WRITE_BW)\n#define BIT_SET_WRITE_BW(x, v) (BIT_CLEAR_WRITE_BW(x) | BIT_WRITE_BW(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_BEAMFORMING_INFO_NSARP\t\t(Offset 0x072C) */\n\n#define BIT_SHIFT_UPD_BFMEE_BW_V1 10\n#define BIT_MASK_UPD_BFMEE_BW_V1 0x3\n#define BIT_UPD_BFMEE_BW_V1(x)                                                 \\\n\t(((x) & BIT_MASK_UPD_BFMEE_BW_V1) << BIT_SHIFT_UPD_BFMEE_BW_V1)\n#define BITS_UPD_BFMEE_BW_V1                                                   \\\n\t(BIT_MASK_UPD_BFMEE_BW_V1 << BIT_SHIFT_UPD_BFMEE_BW_V1)\n#define BIT_CLEAR_UPD_BFMEE_BW_V1(x) ((x) & (~BITS_UPD_BFMEE_BW_V1))\n#define BIT_GET_UPD_BFMEE_BW_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_UPD_BFMEE_BW_V1) & BIT_MASK_UPD_BFMEE_BW_V1)\n#define BIT_SET_UPD_BFMEE_BW_V1(x, v)                                          \\\n\t(BIT_CLEAR_UPD_BFMEE_BW_V1(x) | BIT_UPD_BFMEE_BW_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RX_CSI_RPT_INFO_V1\t\t\t(Offset 0x072C) */\n\n#define BIT_SHIFT_WRITE_CB 8\n#define BIT_MASK_WRITE_CB 0x3\n#define BIT_WRITE_CB(x) (((x) & BIT_MASK_WRITE_CB) << BIT_SHIFT_WRITE_CB)\n#define BITS_WRITE_CB (BIT_MASK_WRITE_CB << BIT_SHIFT_WRITE_CB)\n#define BIT_CLEAR_WRITE_CB(x) ((x) & (~BITS_WRITE_CB))\n#define BIT_GET_WRITE_CB(x) (((x) >> BIT_SHIFT_WRITE_CB) & BIT_MASK_WRITE_CB)\n#define BIT_SET_WRITE_CB(x, v) (BIT_CLEAR_WRITE_CB(x) | BIT_WRITE_CB(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BEAMFORMING_INFO_NSARP\t\t(Offset 0x072C) */\n\n#define BIT_SHIFT_UPD_BFMEE_CB 8\n#define BIT_MASK_UPD_BFMEE_CB 0x3\n#define BIT_UPD_BFMEE_CB(x)                                                    \\\n\t(((x) & BIT_MASK_UPD_BFMEE_CB) << BIT_SHIFT_UPD_BFMEE_CB)\n#define BITS_UPD_BFMEE_CB (BIT_MASK_UPD_BFMEE_CB << BIT_SHIFT_UPD_BFMEE_CB)\n#define BIT_CLEAR_UPD_BFMEE_CB(x) ((x) & (~BITS_UPD_BFMEE_CB))\n#define BIT_GET_UPD_BFMEE_CB(x)                                                \\\n\t(((x) >> BIT_SHIFT_UPD_BFMEE_CB) & BIT_MASK_UPD_BFMEE_CB)\n#define BIT_SET_UPD_BFMEE_CB(x, v)                                             \\\n\t(BIT_CLEAR_UPD_BFMEE_CB(x) | BIT_UPD_BFMEE_CB(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RX_CSI_RPT_INFO_V1\t\t\t(Offset 0x072C) */\n\n#define BIT_SHIFT_WRITE_GROUPING 6\n#define BIT_MASK_WRITE_GROUPING 0x3\n#define BIT_WRITE_GROUPING(x)                                                  \\\n\t(((x) & BIT_MASK_WRITE_GROUPING) << BIT_SHIFT_WRITE_GROUPING)\n#define BITS_WRITE_GROUPING                                                    \\\n\t(BIT_MASK_WRITE_GROUPING << BIT_SHIFT_WRITE_GROUPING)\n#define BIT_CLEAR_WRITE_GROUPING(x) ((x) & (~BITS_WRITE_GROUPING))\n#define BIT_GET_WRITE_GROUPING(x)                                              \\\n\t(((x) >> BIT_SHIFT_WRITE_GROUPING) & BIT_MASK_WRITE_GROUPING)\n#define BIT_SET_WRITE_GROUPING(x, v)                                           \\\n\t(BIT_CLEAR_WRITE_GROUPING(x) | BIT_WRITE_GROUPING(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BEAMFORMING_INFO_NSARP\t\t(Offset 0x072C) */\n\n#define BIT_SHIFT_UPD_BFMEE_NG 6\n#define BIT_MASK_UPD_BFMEE_NG 0x3\n#define BIT_UPD_BFMEE_NG(x)                                                    \\\n\t(((x) & BIT_MASK_UPD_BFMEE_NG) << BIT_SHIFT_UPD_BFMEE_NG)\n#define BITS_UPD_BFMEE_NG (BIT_MASK_UPD_BFMEE_NG << BIT_SHIFT_UPD_BFMEE_NG)\n#define BIT_CLEAR_UPD_BFMEE_NG(x) ((x) & (~BITS_UPD_BFMEE_NG))\n#define BIT_GET_UPD_BFMEE_NG(x)                                                \\\n\t(((x) >> BIT_SHIFT_UPD_BFMEE_NG) & BIT_MASK_UPD_BFMEE_NG)\n#define BIT_SET_UPD_BFMEE_NG(x, v)                                             \\\n\t(BIT_CLEAR_UPD_BFMEE_NG(x) | BIT_UPD_BFMEE_NG(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RX_CSI_RPT_INFO_V1\t\t\t(Offset 0x072C) */\n\n#define BIT_SHIFT_WRITE_NR 3\n#define BIT_MASK_WRITE_NR 0x7\n#define BIT_WRITE_NR(x) (((x) & BIT_MASK_WRITE_NR) << BIT_SHIFT_WRITE_NR)\n#define BITS_WRITE_NR (BIT_MASK_WRITE_NR << BIT_SHIFT_WRITE_NR)\n#define BIT_CLEAR_WRITE_NR(x) ((x) & (~BITS_WRITE_NR))\n#define BIT_GET_WRITE_NR(x) (((x) >> BIT_SHIFT_WRITE_NR) & BIT_MASK_WRITE_NR)\n#define BIT_SET_WRITE_NR(x, v) (BIT_CLEAR_WRITE_NR(x) | BIT_WRITE_NR(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BEAMFORMING_INFO_NSARP\t\t(Offset 0x072C) */\n\n#define BIT_SHIFT_UPD_BFMEE_NR 3\n#define BIT_MASK_UPD_BFMEE_NR 0x7\n#define BIT_UPD_BFMEE_NR(x)                                                    \\\n\t(((x) & BIT_MASK_UPD_BFMEE_NR) << BIT_SHIFT_UPD_BFMEE_NR)\n#define BITS_UPD_BFMEE_NR (BIT_MASK_UPD_BFMEE_NR << BIT_SHIFT_UPD_BFMEE_NR)\n#define BIT_CLEAR_UPD_BFMEE_NR(x) ((x) & (~BITS_UPD_BFMEE_NR))\n#define BIT_GET_UPD_BFMEE_NR(x)                                                \\\n\t(((x) >> BIT_SHIFT_UPD_BFMEE_NR) & BIT_MASK_UPD_BFMEE_NR)\n#define BIT_SET_UPD_BFMEE_NR(x, v)                                             \\\n\t(BIT_CLEAR_UPD_BFMEE_NR(x) | BIT_UPD_BFMEE_NR(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RX_CSI_RPT_INFO_V1\t\t\t(Offset 0x072C) */\n\n#define BIT_SHIFT_WRITE_NC 0\n#define BIT_MASK_WRITE_NC 0x7\n#define BIT_WRITE_NC(x) (((x) & BIT_MASK_WRITE_NC) << BIT_SHIFT_WRITE_NC)\n#define BITS_WRITE_NC (BIT_MASK_WRITE_NC << BIT_SHIFT_WRITE_NC)\n#define BIT_CLEAR_WRITE_NC(x) ((x) & (~BITS_WRITE_NC))\n#define BIT_GET_WRITE_NC(x) (((x) >> BIT_SHIFT_WRITE_NC) & BIT_MASK_WRITE_NC)\n#define BIT_SET_WRITE_NC(x, v) (BIT_CLEAR_WRITE_NC(x) | BIT_WRITE_NC(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BEAMFORMING_INFO_NSARP\t\t(Offset 0x072C) */\n\n#define BIT_SHIFT_UPD_BFMEE_NC 0\n#define BIT_MASK_UPD_BFMEE_NC 0x7\n#define BIT_UPD_BFMEE_NC(x)                                                    \\\n\t(((x) & BIT_MASK_UPD_BFMEE_NC) << BIT_SHIFT_UPD_BFMEE_NC)\n#define BITS_UPD_BFMEE_NC (BIT_MASK_UPD_BFMEE_NC << BIT_SHIFT_UPD_BFMEE_NC)\n#define BIT_CLEAR_UPD_BFMEE_NC(x) ((x) & (~BITS_UPD_BFMEE_NC))\n#define BIT_GET_UPD_BFMEE_NC(x)                                                \\\n\t(((x) >> BIT_SHIFT_UPD_BFMEE_NC) & BIT_MASK_UPD_BFMEE_NC)\n#define BIT_SET_UPD_BFMEE_NC(x, v)                                             \\\n\t(BIT_CLEAR_UPD_BFMEE_NC(x) | BIT_UPD_BFMEE_NC(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_BEAMFORMING_INFO_NSARP\t\t(Offset 0x072C) */\n\n#define BIT_SHIFT_BEAMFORMING_INFO 0\n#define BIT_MASK_BEAMFORMING_INFO 0xffffffffL\n#define BIT_BEAMFORMING_INFO(x)                                                \\\n\t(((x) & BIT_MASK_BEAMFORMING_INFO) << BIT_SHIFT_BEAMFORMING_INFO)\n#define BITS_BEAMFORMING_INFO                                                  \\\n\t(BIT_MASK_BEAMFORMING_INFO << BIT_SHIFT_BEAMFORMING_INFO)\n#define BIT_CLEAR_BEAMFORMING_INFO(x) ((x) & (~BITS_BEAMFORMING_INFO))\n#define BIT_GET_BEAMFORMING_INFO(x)                                            \\\n\t(((x) >> BIT_SHIFT_BEAMFORMING_INFO) & BIT_MASK_BEAMFORMING_INFO)\n#define BIT_SET_BEAMFORMING_INFO(x, v)                                         \\\n\t(BIT_CLEAR_BEAMFORMING_INFO(x) | BIT_BEAMFORMING_INFO(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BEAMFORMING_INFO_NSARP\t\t(Offset 0x072C) */\n\n#define BIT_SHIFT_UPD_BFMEE_BW 0\n#define BIT_MASK_UPD_BFMEE_BW 0xfff\n#define BIT_UPD_BFMEE_BW(x)                                                    \\\n\t(((x) & BIT_MASK_UPD_BFMEE_BW) << BIT_SHIFT_UPD_BFMEE_BW)\n#define BITS_UPD_BFMEE_BW (BIT_MASK_UPD_BFMEE_BW << BIT_SHIFT_UPD_BFMEE_BW)\n#define BIT_CLEAR_UPD_BFMEE_BW(x) ((x) & (~BITS_UPD_BFMEE_BW))\n#define BIT_GET_UPD_BFMEE_BW(x)                                                \\\n\t(((x) >> BIT_SHIFT_UPD_BFMEE_BW) & BIT_MASK_UPD_BFMEE_BW)\n#define BIT_SET_UPD_BFMEE_BW(x, v)                                             \\\n\t(BIT_CLEAR_UPD_BFMEE_BW(x) | BIT_UPD_BFMEE_BW(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_IPV6\t\t\t\t(Offset 0x0730) */\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0 0xffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD_0(x)                                            \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0)                                 \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0)\n#define BITS_R_WMAC_IPV6_MYIPAD_0                                              \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD_0 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD_0(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) &                             \\\n\t BIT_MASK_R_WMAC_IPV6_MYIPAD_0)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD_0(x, v)                                     \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0(x) | BIT_R_WMAC_IPV6_MYIPAD_0(v))\n\n/* 2 REG_IPV6_1\t\t\t\t(Offset 0x0734) */\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1 0xffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD_1(x)                                            \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1)                                 \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1)\n#define BITS_R_WMAC_IPV6_MYIPAD_1                                              \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD_1 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD_1(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) &                             \\\n\t BIT_MASK_R_WMAC_IPV6_MYIPAD_1)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD_1(x, v)                                     \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1(x) | BIT_R_WMAC_IPV6_MYIPAD_1(v))\n\n/* 2 REG_IPV6_2\t\t\t\t(Offset 0x0738) */\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2 0xffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD_2(x)                                            \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2)                                 \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2)\n#define BITS_R_WMAC_IPV6_MYIPAD_2                                              \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD_2 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD_2(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) &                             \\\n\t BIT_MASK_R_WMAC_IPV6_MYIPAD_2)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD_2(x, v)                                     \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2(x) | BIT_R_WMAC_IPV6_MYIPAD_2(v))\n\n/* 2 REG_IPV6_3\t\t\t\t(Offset 0x073C) */\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3 0xffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD_3(x)                                            \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3)                                 \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3)\n#define BITS_R_WMAC_IPV6_MYIPAD_3                                              \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD_3 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD_3(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) &                             \\\n\t BIT_MASK_R_WMAC_IPV6_MYIPAD_3)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD_3(x, v)                                     \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3(x) | BIT_R_WMAC_IPV6_MYIPAD_3(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG\t\t(Offset 0x0750) */\n\n#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE 4\n#define BIT_MASK_R_WMAC_CTX_SUBTYPE 0xf\n#define BIT_R_WMAC_CTX_SUBTYPE(x)                                              \\\n\t(((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE)\n#define BITS_R_WMAC_CTX_SUBTYPE                                                \\\n\t(BIT_MASK_R_WMAC_CTX_SUBTYPE << BIT_SHIFT_R_WMAC_CTX_SUBTYPE)\n#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE(x) ((x) & (~BITS_R_WMAC_CTX_SUBTYPE))\n#define BIT_GET_R_WMAC_CTX_SUBTYPE(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE) & BIT_MASK_R_WMAC_CTX_SUBTYPE)\n#define BIT_SET_R_WMAC_CTX_SUBTYPE(x, v)                                       \\\n\t(BIT_CLEAR_R_WMAC_CTX_SUBTYPE(x) | BIT_R_WMAC_CTX_SUBTYPE(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG\t\t(Offset 0x0750) */\n\n#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE 0\n#define BIT_MASK_R_WMAC_RTX_SUBTYPE 0xf\n#define BIT_R_WMAC_RTX_SUBTYPE(x)                                              \\\n\t(((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE)\n#define BITS_R_WMAC_RTX_SUBTYPE                                                \\\n\t(BIT_MASK_R_WMAC_RTX_SUBTYPE << BIT_SHIFT_R_WMAC_RTX_SUBTYPE)\n#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE(x) ((x) & (~BITS_R_WMAC_RTX_SUBTYPE))\n#define BIT_GET_R_WMAC_RTX_SUBTYPE(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE) & BIT_MASK_R_WMAC_RTX_SUBTYPE)\n#define BIT_SET_R_WMAC_RTX_SUBTYPE(x, v)                                       \\\n\t(BIT_CLEAR_R_WMAC_RTX_SUBTYPE(x) | BIT_R_WMAC_RTX_SUBTYPE(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_SWAES_DIO_B63_B32\t\t(Offset 0x0754) */\n\n#define BIT_SHIFT_WMAC_SWAES_DIO_B63_B32 0\n#define BIT_MASK_WMAC_SWAES_DIO_B63_B32 0xffffffffL\n#define BIT_WMAC_SWAES_DIO_B63_B32(x)                                          \\\n\t(((x) & BIT_MASK_WMAC_SWAES_DIO_B63_B32)                               \\\n\t << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32)\n#define BITS_WMAC_SWAES_DIO_B63_B32                                            \\\n\t(BIT_MASK_WMAC_SWAES_DIO_B63_B32 << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32)\n#define BIT_CLEAR_WMAC_SWAES_DIO_B63_B32(x)                                    \\\n\t((x) & (~BITS_WMAC_SWAES_DIO_B63_B32))\n#define BIT_GET_WMAC_SWAES_DIO_B63_B32(x)                                      \\\n\t(((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B63_B32) &                           \\\n\t BIT_MASK_WMAC_SWAES_DIO_B63_B32)\n#define BIT_SET_WMAC_SWAES_DIO_B63_B32(x, v)                                   \\\n\t(BIT_CLEAR_WMAC_SWAES_DIO_B63_B32(x) | BIT_WMAC_SWAES_DIO_B63_B32(v))\n\n/* 2 REG_WMAC_SWAES_DIO_B95_B64\t\t(Offset 0x0758) */\n\n#define BIT_SHIFT_WMAC_SWAES_DIO_B95_B64 0\n#define BIT_MASK_WMAC_SWAES_DIO_B95_B64 0xffffffffL\n#define BIT_WMAC_SWAES_DIO_B95_B64(x)                                          \\\n\t(((x) & BIT_MASK_WMAC_SWAES_DIO_B95_B64)                               \\\n\t << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64)\n#define BITS_WMAC_SWAES_DIO_B95_B64                                            \\\n\t(BIT_MASK_WMAC_SWAES_DIO_B95_B64 << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64)\n#define BIT_CLEAR_WMAC_SWAES_DIO_B95_B64(x)                                    \\\n\t((x) & (~BITS_WMAC_SWAES_DIO_B95_B64))\n#define BIT_GET_WMAC_SWAES_DIO_B95_B64(x)                                      \\\n\t(((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B95_B64) &                           \\\n\t BIT_MASK_WMAC_SWAES_DIO_B95_B64)\n#define BIT_SET_WMAC_SWAES_DIO_B95_B64(x, v)                                   \\\n\t(BIT_CLEAR_WMAC_SWAES_DIO_B95_B64(x) | BIT_WMAC_SWAES_DIO_B95_B64(v))\n\n/* 2 REG_WMAC_SWAES_DIO_B127_B96\t\t(Offset 0x075C) */\n\n#define BIT_SHIFT_WMAC_SWAES_DIO_B127_B96 0\n#define BIT_MASK_WMAC_SWAES_DIO_B127_B96 0xffffffffL\n#define BIT_WMAC_SWAES_DIO_B127_B96(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_SWAES_DIO_B127_B96)                              \\\n\t << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96)\n#define BITS_WMAC_SWAES_DIO_B127_B96                                           \\\n\t(BIT_MASK_WMAC_SWAES_DIO_B127_B96 << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96)\n#define BIT_CLEAR_WMAC_SWAES_DIO_B127_B96(x)                                   \\\n\t((x) & (~BITS_WMAC_SWAES_DIO_B127_B96))\n#define BIT_GET_WMAC_SWAES_DIO_B127_B96(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B127_B96) &                          \\\n\t BIT_MASK_WMAC_SWAES_DIO_B127_B96)\n#define BIT_SET_WMAC_SWAES_DIO_B127_B96(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_SWAES_DIO_B127_B96(x) | BIT_WMAC_SWAES_DIO_B127_B96(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_WMAC_SWAES_CFG\t\t\t(Offset 0x0760) */\n\n#define BIT_SWAES_REQ BIT(7)\n#define BIT_CLR_SWAES_REQ BIT(6)\n#define BIT_R_WMAC_SWAES_WE BIT(3)\n#define BIT_R_WMAC_SWAES_SEL BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BT_COEX_V2\t\t\t\t(Offset 0x0762) */\n\n#define BIT_GNT_BT_POLARITY BIT(12)\n#define BIT_GNT_BT_BYPASS_PRIORITY BIT(8)\n\n#define BIT_SHIFT_TIMER 0\n#define BIT_MASK_TIMER 0xff\n#define BIT_TIMER(x) (((x) & BIT_MASK_TIMER) << BIT_SHIFT_TIMER)\n#define BITS_TIMER (BIT_MASK_TIMER << BIT_SHIFT_TIMER)\n#define BIT_CLEAR_TIMER(x) ((x) & (~BITS_TIMER))\n#define BIT_GET_TIMER(x) (((x) >> BIT_SHIFT_TIMER) & BIT_MASK_TIMER)\n#define BIT_SET_TIMER(x, v) (BIT_CLEAR_TIMER(x) | BIT_TIMER(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BT_COEX\t\t\t\t(Offset 0x0764) */\n\n#define BIT_R_GNT_BT_RFC_SW BIT(12)\n#define BIT_R_GNT_BT_RFC_SW_EN BIT(11)\n#define BIT_R_GNT_BT_BB_SW BIT(10)\n#define BIT_R_GNT_BT_BB_SW_EN BIT(9)\n#define BIT_R_BT_CNT_THREN BIT(8)\n\n#define BIT_SHIFT_R_BT_CNT_THR 0\n#define BIT_MASK_R_BT_CNT_THR 0xff\n#define BIT_R_BT_CNT_THR(x)                                                    \\\n\t(((x) & BIT_MASK_R_BT_CNT_THR) << BIT_SHIFT_R_BT_CNT_THR)\n#define BITS_R_BT_CNT_THR (BIT_MASK_R_BT_CNT_THR << BIT_SHIFT_R_BT_CNT_THR)\n#define BIT_CLEAR_R_BT_CNT_THR(x) ((x) & (~BITS_R_BT_CNT_THR))\n#define BIT_GET_R_BT_CNT_THR(x)                                                \\\n\t(((x) >> BIT_SHIFT_R_BT_CNT_THR) & BIT_MASK_R_BT_CNT_THR)\n#define BIT_SET_R_BT_CNT_THR(x, v)                                             \\\n\t(BIT_CLEAR_R_BT_CNT_THR(x) | BIT_R_BT_CNT_THR(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_WLAN_ACT_MASK_CTRL\t\t\t(Offset 0x0768) */\n\n#define BIT_WLRX_TER_BY_CTL BIT(43)\n#define BIT_WLRX_TER_BY_AD BIT(42)\n#define BIT_ANT_DIVERSITY_SEL BIT(41)\n#define BIT_ANTSEL_FOR_BT_CTRL_EN BIT(40)\n#define BIT_WLACT_LOW_GNTWL_EN BIT(34)\n#define BIT_WLACT_HIGH_GNTBT_EN BIT(33)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_WLAN_ACT_MASK_CTRL\t\t\t(Offset 0x0768) */\n\n#define BIT_NAV_UPPER_V1 BIT(32)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WLAN_ACT_MASK_CTRL\t\t\t(Offset 0x0768) */\n\n#define BIT_SHIFT_RXMYRTS_NAV_V1 8\n#define BIT_MASK_RXMYRTS_NAV_V1 0xff\n#define BIT_RXMYRTS_NAV_V1(x)                                                  \\\n\t(((x) & BIT_MASK_RXMYRTS_NAV_V1) << BIT_SHIFT_RXMYRTS_NAV_V1)\n#define BITS_RXMYRTS_NAV_V1                                                    \\\n\t(BIT_MASK_RXMYRTS_NAV_V1 << BIT_SHIFT_RXMYRTS_NAV_V1)\n#define BIT_CLEAR_RXMYRTS_NAV_V1(x) ((x) & (~BITS_RXMYRTS_NAV_V1))\n#define BIT_GET_RXMYRTS_NAV_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_RXMYRTS_NAV_V1) & BIT_MASK_RXMYRTS_NAV_V1)\n#define BIT_SET_RXMYRTS_NAV_V1(x, v)                                           \\\n\t(BIT_CLEAR_RXMYRTS_NAV_V1(x) | BIT_RXMYRTS_NAV_V1(v))\n\n#define BIT_SHIFT_RTSRST_V1 0\n#define BIT_MASK_RTSRST_V1 0xff\n#define BIT_RTSRST_V1(x) (((x) & BIT_MASK_RTSRST_V1) << BIT_SHIFT_RTSRST_V1)\n#define BITS_RTSRST_V1 (BIT_MASK_RTSRST_V1 << BIT_SHIFT_RTSRST_V1)\n#define BIT_CLEAR_RTSRST_V1(x) ((x) & (~BITS_RTSRST_V1))\n#define BIT_GET_RTSRST_V1(x) (((x) >> BIT_SHIFT_RTSRST_V1) & BIT_MASK_RTSRST_V1)\n#define BIT_SET_RTSRST_V1(x, v) (BIT_CLEAR_RTSRST_V1(x) | BIT_RTSRST_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WLAN_ACT_MASK_CTRL_1\t\t(Offset 0x076C) */\n\n#define BIT_WLRX_TER_BY_CTL_1 BIT(11)\n#define BIT_WLRX_TER_BY_AD_1 BIT(10)\n#define BIT_ANT_DIVERSITY_SEL_1 BIT(9)\n#define BIT_ANTSEL_FOR_BT_CTRL_EN_1 BIT(8)\n#define BIT_WLACT_LOW_GNTWL_EN_1 BIT(2)\n#define BIT_WLACT_HIGH_GNTBT_EN_1 BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WLAN_ACT_MASK_CTRL_1\t\t(Offset 0x076C) */\n\n#define BIT_NAV_UPPER_1_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL\t\t(Offset 0x076E) */\n\n#define BIT_SHIFT_BT_STAT_DELAY 12\n#define BIT_MASK_BT_STAT_DELAY 0xf\n#define BIT_BT_STAT_DELAY(x)                                                   \\\n\t(((x) & BIT_MASK_BT_STAT_DELAY) << BIT_SHIFT_BT_STAT_DELAY)\n#define BITS_BT_STAT_DELAY (BIT_MASK_BT_STAT_DELAY << BIT_SHIFT_BT_STAT_DELAY)\n#define BIT_CLEAR_BT_STAT_DELAY(x) ((x) & (~BITS_BT_STAT_DELAY))\n#define BIT_GET_BT_STAT_DELAY(x)                                               \\\n\t(((x) >> BIT_SHIFT_BT_STAT_DELAY) & BIT_MASK_BT_STAT_DELAY)\n#define BIT_SET_BT_STAT_DELAY(x, v)                                            \\\n\t(BIT_CLEAR_BT_STAT_DELAY(x) | BIT_BT_STAT_DELAY(v))\n\n#define BIT_SHIFT_BT_TRX_INIT_DETECT 8\n#define BIT_MASK_BT_TRX_INIT_DETECT 0xf\n#define BIT_BT_TRX_INIT_DETECT(x)                                              \\\n\t(((x) & BIT_MASK_BT_TRX_INIT_DETECT) << BIT_SHIFT_BT_TRX_INIT_DETECT)\n#define BITS_BT_TRX_INIT_DETECT                                                \\\n\t(BIT_MASK_BT_TRX_INIT_DETECT << BIT_SHIFT_BT_TRX_INIT_DETECT)\n#define BIT_CLEAR_BT_TRX_INIT_DETECT(x) ((x) & (~BITS_BT_TRX_INIT_DETECT))\n#define BIT_GET_BT_TRX_INIT_DETECT(x)                                          \\\n\t(((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT) & BIT_MASK_BT_TRX_INIT_DETECT)\n#define BIT_SET_BT_TRX_INIT_DETECT(x, v)                                       \\\n\t(BIT_CLEAR_BT_TRX_INIT_DETECT(x) | BIT_BT_TRX_INIT_DETECT(v))\n\n#define BIT_SHIFT_BT_PRI_DETECT_TO 4\n#define BIT_MASK_BT_PRI_DETECT_TO 0xf\n#define BIT_BT_PRI_DETECT_TO(x)                                                \\\n\t(((x) & BIT_MASK_BT_PRI_DETECT_TO) << BIT_SHIFT_BT_PRI_DETECT_TO)\n#define BITS_BT_PRI_DETECT_TO                                                  \\\n\t(BIT_MASK_BT_PRI_DETECT_TO << BIT_SHIFT_BT_PRI_DETECT_TO)\n#define BIT_CLEAR_BT_PRI_DETECT_TO(x) ((x) & (~BITS_BT_PRI_DETECT_TO))\n#define BIT_GET_BT_PRI_DETECT_TO(x)                                            \\\n\t(((x) >> BIT_SHIFT_BT_PRI_DETECT_TO) & BIT_MASK_BT_PRI_DETECT_TO)\n#define BIT_SET_BT_PRI_DETECT_TO(x, v)                                         \\\n\t(BIT_CLEAR_BT_PRI_DETECT_TO(x) | BIT_BT_PRI_DETECT_TO(v))\n\n#define BIT_R_GRANTALL_WLMASK BIT(3)\n#define BIT_STATIS_BT_EN BIT(2)\n#define BIT_WL_ACT_MASK_ENABLE BIT(1)\n#define BIT_ENHANCED_BT BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_BT_ACT_STATISTICS\t\t\t(Offset 0x0770) */\n\n#define BIT_SHIFT_STATIS_BT_LO_RX (48 & CPU_OPT_WIDTH)\n#define BIT_MASK_STATIS_BT_LO_RX 0xffff\n#define BIT_STATIS_BT_LO_RX(x)                                                 \\\n\t(((x) & BIT_MASK_STATIS_BT_LO_RX) << BIT_SHIFT_STATIS_BT_LO_RX)\n#define BITS_STATIS_BT_LO_RX                                                   \\\n\t(BIT_MASK_STATIS_BT_LO_RX << BIT_SHIFT_STATIS_BT_LO_RX)\n#define BIT_CLEAR_STATIS_BT_LO_RX(x) ((x) & (~BITS_STATIS_BT_LO_RX))\n#define BIT_GET_STATIS_BT_LO_RX(x)                                             \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_LO_RX) & BIT_MASK_STATIS_BT_LO_RX)\n#define BIT_SET_STATIS_BT_LO_RX(x, v)                                          \\\n\t(BIT_CLEAR_STATIS_BT_LO_RX(x) | BIT_STATIS_BT_LO_RX(v))\n\n#define BIT_SHIFT_STATIS_BT_LO_TX (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_STATIS_BT_LO_TX 0xffff\n#define BIT_STATIS_BT_LO_TX(x)                                                 \\\n\t(((x) & BIT_MASK_STATIS_BT_LO_TX) << BIT_SHIFT_STATIS_BT_LO_TX)\n#define BITS_STATIS_BT_LO_TX                                                   \\\n\t(BIT_MASK_STATIS_BT_LO_TX << BIT_SHIFT_STATIS_BT_LO_TX)\n#define BIT_CLEAR_STATIS_BT_LO_TX(x) ((x) & (~BITS_STATIS_BT_LO_TX))\n#define BIT_GET_STATIS_BT_LO_TX(x)                                             \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_LO_TX) & BIT_MASK_STATIS_BT_LO_TX)\n#define BIT_SET_STATIS_BT_LO_TX(x, v)                                          \\\n\t(BIT_CLEAR_STATIS_BT_LO_TX(x) | BIT_STATIS_BT_LO_TX(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BT_ACT_STATISTICS\t\t\t(Offset 0x0770) */\n\n#define BIT_SHIFT_STATIS_BT_HI_RX 16\n#define BIT_MASK_STATIS_BT_HI_RX 0xffff\n#define BIT_STATIS_BT_HI_RX(x)                                                 \\\n\t(((x) & BIT_MASK_STATIS_BT_HI_RX) << BIT_SHIFT_STATIS_BT_HI_RX)\n#define BITS_STATIS_BT_HI_RX                                                   \\\n\t(BIT_MASK_STATIS_BT_HI_RX << BIT_SHIFT_STATIS_BT_HI_RX)\n#define BIT_CLEAR_STATIS_BT_HI_RX(x) ((x) & (~BITS_STATIS_BT_HI_RX))\n#define BIT_GET_STATIS_BT_HI_RX(x)                                             \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_HI_RX) & BIT_MASK_STATIS_BT_HI_RX)\n#define BIT_SET_STATIS_BT_HI_RX(x, v)                                          \\\n\t(BIT_CLEAR_STATIS_BT_HI_RX(x) | BIT_STATIS_BT_HI_RX(v))\n\n#define BIT_SHIFT_STATIS_BT_HI_TX 0\n#define BIT_MASK_STATIS_BT_HI_TX 0xffff\n#define BIT_STATIS_BT_HI_TX(x)                                                 \\\n\t(((x) & BIT_MASK_STATIS_BT_HI_TX) << BIT_SHIFT_STATIS_BT_HI_TX)\n#define BITS_STATIS_BT_HI_TX                                                   \\\n\t(BIT_MASK_STATIS_BT_HI_TX << BIT_SHIFT_STATIS_BT_HI_TX)\n#define BIT_CLEAR_STATIS_BT_HI_TX(x) ((x) & (~BITS_STATIS_BT_HI_TX))\n#define BIT_GET_STATIS_BT_HI_TX(x)                                             \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_HI_TX) & BIT_MASK_STATIS_BT_HI_TX)\n#define BIT_SET_STATIS_BT_HI_TX(x, v)                                          \\\n\t(BIT_CLEAR_STATIS_BT_HI_TX(x) | BIT_STATIS_BT_HI_TX(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BT_ACT_STATISTICS_1\t\t\t(Offset 0x0774) */\n\n#define BIT_APPEND_MACID_IN_RESP_EN_1 BIT(18)\n#define BIT_ADDR2_MATCH_EN_1 BIT(17)\n\n#define BIT_SHIFT_STATIS_BT_LO_RX_1 16\n#define BIT_MASK_STATIS_BT_LO_RX_1 0xffff\n#define BIT_STATIS_BT_LO_RX_1(x)                                               \\\n\t(((x) & BIT_MASK_STATIS_BT_LO_RX_1) << BIT_SHIFT_STATIS_BT_LO_RX_1)\n#define BITS_STATIS_BT_LO_RX_1                                                 \\\n\t(BIT_MASK_STATIS_BT_LO_RX_1 << BIT_SHIFT_STATIS_BT_LO_RX_1)\n#define BIT_CLEAR_STATIS_BT_LO_RX_1(x) ((x) & (~BITS_STATIS_BT_LO_RX_1))\n#define BIT_GET_STATIS_BT_LO_RX_1(x)                                           \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1) & BIT_MASK_STATIS_BT_LO_RX_1)\n#define BIT_SET_STATIS_BT_LO_RX_1(x, v)                                        \\\n\t(BIT_CLEAR_STATIS_BT_LO_RX_1(x) | BIT_STATIS_BT_LO_RX_1(v))\n\n#define BIT_ANTTRN_EN_1 BIT(16)\n\n#define BIT_SHIFT_STATIS_BT_LO_TX_1 0\n#define BIT_MASK_STATIS_BT_LO_TX_1 0xffff\n#define BIT_STATIS_BT_LO_TX_1(x)                                               \\\n\t(((x) & BIT_MASK_STATIS_BT_LO_TX_1) << BIT_SHIFT_STATIS_BT_LO_TX_1)\n#define BITS_STATIS_BT_LO_TX_1                                                 \\\n\t(BIT_MASK_STATIS_BT_LO_TX_1 << BIT_SHIFT_STATIS_BT_LO_TX_1)\n#define BIT_CLEAR_STATIS_BT_LO_TX_1(x) ((x) & (~BITS_STATIS_BT_LO_TX_1))\n#define BIT_GET_STATIS_BT_LO_TX_1(x)                                           \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1) & BIT_MASK_STATIS_BT_LO_TX_1)\n#define BIT_SET_STATIS_BT_LO_TX_1(x, v)                                        \\\n\t(BIT_CLEAR_STATIS_BT_LO_TX_1(x) | BIT_STATIS_BT_LO_TX_1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BT_STATISTICS_CONTROL_REGISTER\t(Offset 0x0778) */\n\n#define BIT_SHIFT_R_BT_CMD_RPT 16\n#define BIT_MASK_R_BT_CMD_RPT 0xffff\n#define BIT_R_BT_CMD_RPT(x)                                                    \\\n\t(((x) & BIT_MASK_R_BT_CMD_RPT) << BIT_SHIFT_R_BT_CMD_RPT)\n#define BITS_R_BT_CMD_RPT (BIT_MASK_R_BT_CMD_RPT << BIT_SHIFT_R_BT_CMD_RPT)\n#define BIT_CLEAR_R_BT_CMD_RPT(x) ((x) & (~BITS_R_BT_CMD_RPT))\n#define BIT_GET_R_BT_CMD_RPT(x)                                                \\\n\t(((x) >> BIT_SHIFT_R_BT_CMD_RPT) & BIT_MASK_R_BT_CMD_RPT)\n#define BIT_SET_R_BT_CMD_RPT(x, v)                                             \\\n\t(BIT_CLEAR_R_BT_CMD_RPT(x) | BIT_R_BT_CMD_RPT(v))\n\n#define BIT_SHIFT_R_RPT_FROM_BT 8\n#define BIT_MASK_R_RPT_FROM_BT 0xff\n#define BIT_R_RPT_FROM_BT(x)                                                   \\\n\t(((x) & BIT_MASK_R_RPT_FROM_BT) << BIT_SHIFT_R_RPT_FROM_BT)\n#define BITS_R_RPT_FROM_BT (BIT_MASK_R_RPT_FROM_BT << BIT_SHIFT_R_RPT_FROM_BT)\n#define BIT_CLEAR_R_RPT_FROM_BT(x) ((x) & (~BITS_R_RPT_FROM_BT))\n#define BIT_GET_R_RPT_FROM_BT(x)                                               \\\n\t(((x) >> BIT_SHIFT_R_RPT_FROM_BT) & BIT_MASK_R_RPT_FROM_BT)\n#define BIT_SET_R_RPT_FROM_BT(x, v)                                            \\\n\t(BIT_CLEAR_R_RPT_FROM_BT(x) | BIT_R_RPT_FROM_BT(v))\n\n#define BIT_SHIFT_BT_HID_ISR_SET 6\n#define BIT_MASK_BT_HID_ISR_SET 0x3\n#define BIT_BT_HID_ISR_SET(x)                                                  \\\n\t(((x) & BIT_MASK_BT_HID_ISR_SET) << BIT_SHIFT_BT_HID_ISR_SET)\n#define BITS_BT_HID_ISR_SET                                                    \\\n\t(BIT_MASK_BT_HID_ISR_SET << BIT_SHIFT_BT_HID_ISR_SET)\n#define BIT_CLEAR_BT_HID_ISR_SET(x) ((x) & (~BITS_BT_HID_ISR_SET))\n#define BIT_GET_BT_HID_ISR_SET(x)                                              \\\n\t(((x) >> BIT_SHIFT_BT_HID_ISR_SET) & BIT_MASK_BT_HID_ISR_SET)\n#define BIT_SET_BT_HID_ISR_SET(x, v)                                           \\\n\t(BIT_CLEAR_BT_HID_ISR_SET(x) | BIT_BT_HID_ISR_SET(v))\n\n#define BIT_TDMA_BT_START_NOTIFY BIT(5)\n#define BIT_ENABLE_TDMA_FW_MODE BIT(4)\n#define BIT_ENABLE_PTA_TDMA_MODE BIT(3)\n#define BIT_ENABLE_COEXIST_TAB_IN_TDMA BIT(2)\n#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1)\n#define BIT_RTK_BT_ENABLE BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BT_STATUS_REPORT_REGISTER\t\t(Offset 0x077C) */\n\n#define BIT_SHIFT_BT_PROFILE 24\n#define BIT_MASK_BT_PROFILE 0xff\n#define BIT_BT_PROFILE(x) (((x) & BIT_MASK_BT_PROFILE) << BIT_SHIFT_BT_PROFILE)\n#define BITS_BT_PROFILE (BIT_MASK_BT_PROFILE << BIT_SHIFT_BT_PROFILE)\n#define BIT_CLEAR_BT_PROFILE(x) ((x) & (~BITS_BT_PROFILE))\n#define BIT_GET_BT_PROFILE(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BT_PROFILE) & BIT_MASK_BT_PROFILE)\n#define BIT_SET_BT_PROFILE(x, v) (BIT_CLEAR_BT_PROFILE(x) | BIT_BT_PROFILE(v))\n\n#define BIT_SHIFT_BT_POWER 16\n#define BIT_MASK_BT_POWER 0xff\n#define BIT_BT_POWER(x) (((x) & BIT_MASK_BT_POWER) << BIT_SHIFT_BT_POWER)\n#define BITS_BT_POWER (BIT_MASK_BT_POWER << BIT_SHIFT_BT_POWER)\n#define BIT_CLEAR_BT_POWER(x) ((x) & (~BITS_BT_POWER))\n#define BIT_GET_BT_POWER(x) (((x) >> BIT_SHIFT_BT_POWER) & BIT_MASK_BT_POWER)\n#define BIT_SET_BT_POWER(x, v) (BIT_CLEAR_BT_POWER(x) | BIT_BT_POWER(v))\n\n#define BIT_SHIFT_BT_PREDECT_STATUS 8\n#define BIT_MASK_BT_PREDECT_STATUS 0xff\n#define BIT_BT_PREDECT_STATUS(x)                                               \\\n\t(((x) & BIT_MASK_BT_PREDECT_STATUS) << BIT_SHIFT_BT_PREDECT_STATUS)\n#define BITS_BT_PREDECT_STATUS                                                 \\\n\t(BIT_MASK_BT_PREDECT_STATUS << BIT_SHIFT_BT_PREDECT_STATUS)\n#define BIT_CLEAR_BT_PREDECT_STATUS(x) ((x) & (~BITS_BT_PREDECT_STATUS))\n#define BIT_GET_BT_PREDECT_STATUS(x)                                           \\\n\t(((x) >> BIT_SHIFT_BT_PREDECT_STATUS) & BIT_MASK_BT_PREDECT_STATUS)\n#define BIT_SET_BT_PREDECT_STATUS(x, v)                                        \\\n\t(BIT_CLEAR_BT_PREDECT_STATUS(x) | BIT_BT_PREDECT_STATUS(v))\n\n#define BIT_SHIFT_BT_CMD_INFO 0\n#define BIT_MASK_BT_CMD_INFO 0xff\n#define BIT_BT_CMD_INFO(x)                                                     \\\n\t(((x) & BIT_MASK_BT_CMD_INFO) << BIT_SHIFT_BT_CMD_INFO)\n#define BITS_BT_CMD_INFO (BIT_MASK_BT_CMD_INFO << BIT_SHIFT_BT_CMD_INFO)\n#define BIT_CLEAR_BT_CMD_INFO(x) ((x) & (~BITS_BT_CMD_INFO))\n#define BIT_GET_BT_CMD_INFO(x)                                                 \\\n\t(((x) >> BIT_SHIFT_BT_CMD_INFO) & BIT_MASK_BT_CMD_INFO)\n#define BIT_SET_BT_CMD_INFO(x, v)                                              \\\n\t(BIT_CLEAR_BT_CMD_INFO(x) | BIT_BT_CMD_INFO(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER\t(Offset 0x0780) */\n\n#define BIT_EN_MAC_NULL_PKT_NOTIFY BIT(31)\n#define BIT_EN_WLAN_RPT_AND_BT_QUERY BIT(30)\n#define BIT_EN_BT_STSTUS_RPT BIT(29)\n#define BIT_EN_BT_POWER BIT(28)\n#define BIT_EN_BT_CHANNEL BIT(27)\n#define BIT_EN_BT_SLOT_CHANGE BIT(26)\n#define BIT_EN_BT_PROFILE_OR_HID BIT(25)\n#define BIT_WLAN_RPT_NOTIFY BIT(24)\n\n#define BIT_SHIFT_WLAN_RPT_DATA 16\n#define BIT_MASK_WLAN_RPT_DATA 0xff\n#define BIT_WLAN_RPT_DATA(x)                                                   \\\n\t(((x) & BIT_MASK_WLAN_RPT_DATA) << BIT_SHIFT_WLAN_RPT_DATA)\n#define BITS_WLAN_RPT_DATA (BIT_MASK_WLAN_RPT_DATA << BIT_SHIFT_WLAN_RPT_DATA)\n#define BIT_CLEAR_WLAN_RPT_DATA(x) ((x) & (~BITS_WLAN_RPT_DATA))\n#define BIT_GET_WLAN_RPT_DATA(x)                                               \\\n\t(((x) >> BIT_SHIFT_WLAN_RPT_DATA) & BIT_MASK_WLAN_RPT_DATA)\n#define BIT_SET_WLAN_RPT_DATA(x, v)                                            \\\n\t(BIT_CLEAR_WLAN_RPT_DATA(x) | BIT_WLAN_RPT_DATA(v))\n\n#define BIT_SHIFT_CMD_ID 8\n#define BIT_MASK_CMD_ID 0xff\n#define BIT_CMD_ID(x) (((x) & BIT_MASK_CMD_ID) << BIT_SHIFT_CMD_ID)\n#define BITS_CMD_ID (BIT_MASK_CMD_ID << BIT_SHIFT_CMD_ID)\n#define BIT_CLEAR_CMD_ID(x) ((x) & (~BITS_CMD_ID))\n#define BIT_GET_CMD_ID(x) (((x) >> BIT_SHIFT_CMD_ID) & BIT_MASK_CMD_ID)\n#define BIT_SET_CMD_ID(x, v) (BIT_CLEAR_CMD_ID(x) | BIT_CMD_ID(v))\n\n#define BIT_SHIFT_BT_DATA 0\n#define BIT_MASK_BT_DATA 0xff\n#define BIT_BT_DATA(x) (((x) & BIT_MASK_BT_DATA) << BIT_SHIFT_BT_DATA)\n#define BITS_BT_DATA (BIT_MASK_BT_DATA << BIT_SHIFT_BT_DATA)\n#define BIT_CLEAR_BT_DATA(x) ((x) & (~BITS_BT_DATA))\n#define BIT_GET_BT_DATA(x) (((x) >> BIT_SHIFT_BT_DATA) & BIT_MASK_BT_DATA)\n#define BIT_SET_BT_DATA(x, v) (BIT_CLEAR_BT_DATA(x) | BIT_BT_DATA(v))\n\n/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER (Offset 0x0784) */\n\n#define BIT_SHIFT_WLAN_RPT_TO 0\n#define BIT_MASK_WLAN_RPT_TO 0xff\n#define BIT_WLAN_RPT_TO(x)                                                     \\\n\t(((x) & BIT_MASK_WLAN_RPT_TO) << BIT_SHIFT_WLAN_RPT_TO)\n#define BITS_WLAN_RPT_TO (BIT_MASK_WLAN_RPT_TO << BIT_SHIFT_WLAN_RPT_TO)\n#define BIT_CLEAR_WLAN_RPT_TO(x) ((x) & (~BITS_WLAN_RPT_TO))\n#define BIT_GET_WLAN_RPT_TO(x)                                                 \\\n\t(((x) >> BIT_SHIFT_WLAN_RPT_TO) & BIT_MASK_WLAN_RPT_TO)\n#define BIT_SET_WLAN_RPT_TO(x, v)                                              \\\n\t(BIT_CLEAR_WLAN_RPT_TO(x) | BIT_WLAN_RPT_TO(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */\n\n#define BIT_SHIFT_ISOLATION_CHK_0 1\n#define BIT_MASK_ISOLATION_CHK_0 0x7fffff\n#define BIT_ISOLATION_CHK_0(x)                                                 \\\n\t(((x) & BIT_MASK_ISOLATION_CHK_0) << BIT_SHIFT_ISOLATION_CHK_0)\n#define BITS_ISOLATION_CHK_0                                                   \\\n\t(BIT_MASK_ISOLATION_CHK_0 << BIT_SHIFT_ISOLATION_CHK_0)\n#define BIT_CLEAR_ISOLATION_CHK_0(x) ((x) & (~BITS_ISOLATION_CHK_0))\n#define BIT_GET_ISOLATION_CHK_0(x)                                             \\\n\t(((x) >> BIT_SHIFT_ISOLATION_CHK_0) & BIT_MASK_ISOLATION_CHK_0)\n#define BIT_SET_ISOLATION_CHK_0(x, v)                                          \\\n\t(BIT_CLEAR_ISOLATION_CHK_0(x) | BIT_ISOLATION_CHK_0(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */\n\n#define BIT_SHIFT_ISOLATION_CHK 1\n#define BIT_MASK_ISOLATION_CHK 0x7fffffffffffffffffffL\n#define BIT_ISOLATION_CHK(x)                                                   \\\n\t(((x) & BIT_MASK_ISOLATION_CHK) << BIT_SHIFT_ISOLATION_CHK)\n#define BITS_ISOLATION_CHK (BIT_MASK_ISOLATION_CHK << BIT_SHIFT_ISOLATION_CHK)\n#define BIT_CLEAR_ISOLATION_CHK(x) ((x) & (~BITS_ISOLATION_CHK))\n#define BIT_GET_ISOLATION_CHK(x)                                               \\\n\t(((x) >> BIT_SHIFT_ISOLATION_CHK) & BIT_MASK_ISOLATION_CHK)\n#define BIT_SET_ISOLATION_CHK(x, v)                                            \\\n\t(BIT_CLEAR_ISOLATION_CHK(x) | BIT_ISOLATION_CHK(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */\n\n#define BIT_ISOLATION_EN BIT(0)\n\n#define BIT_SHIFT_R_CCK_LEN 0\n#define BIT_MASK_R_CCK_LEN 0xffff\n#define BIT_R_CCK_LEN(x) (((x) & BIT_MASK_R_CCK_LEN) << BIT_SHIFT_R_CCK_LEN)\n#define BITS_R_CCK_LEN (BIT_MASK_R_CCK_LEN << BIT_SHIFT_R_CCK_LEN)\n#define BIT_CLEAR_R_CCK_LEN(x) ((x) & (~BITS_R_CCK_LEN))\n#define BIT_GET_R_CCK_LEN(x) (((x) >> BIT_SHIFT_R_CCK_LEN) & BIT_MASK_R_CCK_LEN)\n#define BIT_SET_R_CCK_LEN(x, v) (BIT_CLEAR_R_CCK_LEN(x) | BIT_R_CCK_LEN(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 (Offset 0x0788) */\n\n#define BIT_SHIFT_ISOLATION_CHK_1 0\n#define BIT_MASK_ISOLATION_CHK_1 0xffffffffL\n#define BIT_ISOLATION_CHK_1(x)                                                 \\\n\t(((x) & BIT_MASK_ISOLATION_CHK_1) << BIT_SHIFT_ISOLATION_CHK_1)\n#define BITS_ISOLATION_CHK_1                                                   \\\n\t(BIT_MASK_ISOLATION_CHK_1 << BIT_SHIFT_ISOLATION_CHK_1)\n#define BIT_CLEAR_ISOLATION_CHK_1(x) ((x) & (~BITS_ISOLATION_CHK_1))\n#define BIT_GET_ISOLATION_CHK_1(x)                                             \\\n\t(((x) >> BIT_SHIFT_ISOLATION_CHK_1) & BIT_MASK_ISOLATION_CHK_1)\n#define BIT_SET_ISOLATION_CHK_1(x, v)                                          \\\n\t(BIT_CLEAR_ISOLATION_CHK_1(x) | BIT_ISOLATION_CHK_1(v))\n\n/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 (Offset 0x078C) */\n\n#define BIT_SHIFT_ISOLATION_CHK_2 0\n#define BIT_MASK_ISOLATION_CHK_2 0xffffff\n#define BIT_ISOLATION_CHK_2(x)                                                 \\\n\t(((x) & BIT_MASK_ISOLATION_CHK_2) << BIT_SHIFT_ISOLATION_CHK_2)\n#define BITS_ISOLATION_CHK_2                                                   \\\n\t(BIT_MASK_ISOLATION_CHK_2 << BIT_SHIFT_ISOLATION_CHK_2)\n#define BIT_CLEAR_ISOLATION_CHK_2(x) ((x) & (~BITS_ISOLATION_CHK_2))\n#define BIT_GET_ISOLATION_CHK_2(x)                                             \\\n\t(((x) >> BIT_SHIFT_ISOLATION_CHK_2) & BIT_MASK_ISOLATION_CHK_2)\n#define BIT_SET_ISOLATION_CHK_2(x, v)                                          \\\n\t(BIT_CLEAR_ISOLATION_CHK_2(x) | BIT_ISOLATION_CHK_2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BT_INTERRUPT_STATUS_REGISTER\t(Offset 0x078F) */\n\n#define BIT_BT_HID_ISR BIT(7)\n#define BIT_BT_QUERY_ISR BIT(6)\n#define BIT_MAC_NULL_PKT_NOTIFY_ISR BIT(5)\n#define BIT_WLAN_RPT_ISR BIT(4)\n#define BIT_BT_POWER_ISR BIT(3)\n#define BIT_BT_CHANNEL_ISR BIT(2)\n#define BIT_BT_SLOT_CHANGE_ISR BIT(1)\n#define BIT_BT_PROFILE_ISR BIT(0)\n\n/* 2 REG_BT_TDMA_TIME_REGISTER\t\t(Offset 0x0790) */\n\n#define BIT_SHIFT_BT_TIME 6\n#define BIT_MASK_BT_TIME 0x3ffffff\n#define BIT_BT_TIME(x) (((x) & BIT_MASK_BT_TIME) << BIT_SHIFT_BT_TIME)\n#define BITS_BT_TIME (BIT_MASK_BT_TIME << BIT_SHIFT_BT_TIME)\n#define BIT_CLEAR_BT_TIME(x) ((x) & (~BITS_BT_TIME))\n#define BIT_GET_BT_TIME(x) (((x) >> BIT_SHIFT_BT_TIME) & BIT_MASK_BT_TIME)\n#define BIT_SET_BT_TIME(x, v) (BIT_CLEAR_BT_TIME(x) | BIT_BT_TIME(v))\n\n#define BIT_SHIFT_BT_RPT_SAMPLE_RATE 0\n#define BIT_MASK_BT_RPT_SAMPLE_RATE 0x3f\n#define BIT_BT_RPT_SAMPLE_RATE(x)                                              \\\n\t(((x) & BIT_MASK_BT_RPT_SAMPLE_RATE) << BIT_SHIFT_BT_RPT_SAMPLE_RATE)\n#define BITS_BT_RPT_SAMPLE_RATE                                                \\\n\t(BIT_MASK_BT_RPT_SAMPLE_RATE << BIT_SHIFT_BT_RPT_SAMPLE_RATE)\n#define BIT_CLEAR_BT_RPT_SAMPLE_RATE(x) ((x) & (~BITS_BT_RPT_SAMPLE_RATE))\n#define BIT_GET_BT_RPT_SAMPLE_RATE(x)                                          \\\n\t(((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE) & BIT_MASK_BT_RPT_SAMPLE_RATE)\n#define BIT_SET_BT_RPT_SAMPLE_RATE(x, v)                                       \\\n\t(BIT_CLEAR_BT_RPT_SAMPLE_RATE(x) | BIT_BT_RPT_SAMPLE_RATE(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_BT_ACT_REGISTER\t\t\t(Offset 0x0794) */\n\n#define BIT_SHIFT_R_OFDM_LEN 26\n#define BIT_MASK_R_OFDM_LEN 0x3f\n#define BIT_R_OFDM_LEN(x) (((x) & BIT_MASK_R_OFDM_LEN) << BIT_SHIFT_R_OFDM_LEN)\n#define BITS_R_OFDM_LEN (BIT_MASK_R_OFDM_LEN << BIT_SHIFT_R_OFDM_LEN)\n#define BIT_CLEAR_R_OFDM_LEN(x) ((x) & (~BITS_R_OFDM_LEN))\n#define BIT_GET_R_OFDM_LEN(x)                                                  \\\n\t(((x) >> BIT_SHIFT_R_OFDM_LEN) & BIT_MASK_R_OFDM_LEN)\n#define BIT_SET_R_OFDM_LEN(x, v) (BIT_CLEAR_R_OFDM_LEN(x) | BIT_R_OFDM_LEN(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BT_ACT_REGISTER\t\t\t(Offset 0x0794) */\n\n#define BIT_SHIFT_BT_EISR_EN 16\n#define BIT_MASK_BT_EISR_EN 0xff\n#define BIT_BT_EISR_EN(x) (((x) & BIT_MASK_BT_EISR_EN) << BIT_SHIFT_BT_EISR_EN)\n#define BITS_BT_EISR_EN (BIT_MASK_BT_EISR_EN << BIT_SHIFT_BT_EISR_EN)\n#define BIT_CLEAR_BT_EISR_EN(x) ((x) & (~BITS_BT_EISR_EN))\n#define BIT_GET_BT_EISR_EN(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BT_EISR_EN) & BIT_MASK_BT_EISR_EN)\n#define BIT_SET_BT_EISR_EN(x, v) (BIT_CLEAR_BT_EISR_EN(x) | BIT_BT_EISR_EN(v))\n\n#define BIT_BT_ACT_FALLING_ISR BIT(10)\n#define BIT_BT_ACT_RISING_ISR BIT(9)\n#define BIT_TDMA_TO_ISR BIT(8)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_BT_ACT_REGISTER\t\t\t(Offset 0x0794) */\n\n#define BIT_SHIFT_BT_CH 0\n#define BIT_MASK_BT_CH 0xff\n#define BIT_BT_CH(x) (((x) & BIT_MASK_BT_CH) << BIT_SHIFT_BT_CH)\n#define BITS_BT_CH (BIT_MASK_BT_CH << BIT_SHIFT_BT_CH)\n#define BIT_CLEAR_BT_CH(x) ((x) & (~BITS_BT_CH))\n#define BIT_GET_BT_CH(x) (((x) >> BIT_SHIFT_BT_CH) & BIT_MASK_BT_CH)\n#define BIT_SET_BT_CH(x, v) (BIT_CLEAR_BT_CH(x) | BIT_BT_CH(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BT_ACT_REGISTER\t\t\t(Offset 0x0794) */\n\n#define BIT_SHIFT_BT_CH_V1 0\n#define BIT_MASK_BT_CH_V1 0x7f\n#define BIT_BT_CH_V1(x) (((x) & BIT_MASK_BT_CH_V1) << BIT_SHIFT_BT_CH_V1)\n#define BITS_BT_CH_V1 (BIT_MASK_BT_CH_V1 << BIT_SHIFT_BT_CH_V1)\n#define BIT_CLEAR_BT_CH_V1(x) ((x) & (~BITS_BT_CH_V1))\n#define BIT_GET_BT_CH_V1(x) (((x) >> BIT_SHIFT_BT_CH_V1) & BIT_MASK_BT_CH_V1)\n#define BIT_SET_BT_CH_V1(x, v) (BIT_CLEAR_BT_CH_V1(x) | BIT_BT_CH_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_OBFF_CTRL_BASIC\t\t\t(Offset 0x0798) */\n\n#define BIT_OBFF_EN_V1 BIT(31)\n\n#define BIT_SHIFT_OBFF_STATE_V1 28\n#define BIT_MASK_OBFF_STATE_V1 0x3\n#define BIT_OBFF_STATE_V1(x)                                                   \\\n\t(((x) & BIT_MASK_OBFF_STATE_V1) << BIT_SHIFT_OBFF_STATE_V1)\n#define BITS_OBFF_STATE_V1 (BIT_MASK_OBFF_STATE_V1 << BIT_SHIFT_OBFF_STATE_V1)\n#define BIT_CLEAR_OBFF_STATE_V1(x) ((x) & (~BITS_OBFF_STATE_V1))\n#define BIT_GET_OBFF_STATE_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_OBFF_STATE_V1) & BIT_MASK_OBFF_STATE_V1)\n#define BIT_SET_OBFF_STATE_V1(x, v)                                            \\\n\t(BIT_CLEAR_OBFF_STATE_V1(x) | BIT_OBFF_STATE_V1(v))\n\n#define BIT_OBFF_ACT_RXDMA_EN BIT(27)\n#define BIT_OBFF_BLOCK_INT_EN BIT(26)\n#define BIT_OBFF_AUTOACT_EN BIT(25)\n#define BIT_OBFF_AUTOIDLE_EN BIT(24)\n\n#define BIT_SHIFT_WAKE_MAX_PLS 20\n#define BIT_MASK_WAKE_MAX_PLS 0x7\n#define BIT_WAKE_MAX_PLS(x)                                                    \\\n\t(((x) & BIT_MASK_WAKE_MAX_PLS) << BIT_SHIFT_WAKE_MAX_PLS)\n#define BITS_WAKE_MAX_PLS (BIT_MASK_WAKE_MAX_PLS << BIT_SHIFT_WAKE_MAX_PLS)\n#define BIT_CLEAR_WAKE_MAX_PLS(x) ((x) & (~BITS_WAKE_MAX_PLS))\n#define BIT_GET_WAKE_MAX_PLS(x)                                                \\\n\t(((x) >> BIT_SHIFT_WAKE_MAX_PLS) & BIT_MASK_WAKE_MAX_PLS)\n#define BIT_SET_WAKE_MAX_PLS(x, v)                                             \\\n\t(BIT_CLEAR_WAKE_MAX_PLS(x) | BIT_WAKE_MAX_PLS(v))\n\n#define BIT_SHIFT_WAKE_MIN_PLS 16\n#define BIT_MASK_WAKE_MIN_PLS 0x7\n#define BIT_WAKE_MIN_PLS(x)                                                    \\\n\t(((x) & BIT_MASK_WAKE_MIN_PLS) << BIT_SHIFT_WAKE_MIN_PLS)\n#define BITS_WAKE_MIN_PLS (BIT_MASK_WAKE_MIN_PLS << BIT_SHIFT_WAKE_MIN_PLS)\n#define BIT_CLEAR_WAKE_MIN_PLS(x) ((x) & (~BITS_WAKE_MIN_PLS))\n#define BIT_GET_WAKE_MIN_PLS(x)                                                \\\n\t(((x) >> BIT_SHIFT_WAKE_MIN_PLS) & BIT_MASK_WAKE_MIN_PLS)\n#define BIT_SET_WAKE_MIN_PLS(x, v)                                             \\\n\t(BIT_CLEAR_WAKE_MIN_PLS(x) | BIT_WAKE_MIN_PLS(v))\n\n#define BIT_SHIFT_WAKE_MAX_F2F 12\n#define BIT_MASK_WAKE_MAX_F2F 0x7\n#define BIT_WAKE_MAX_F2F(x)                                                    \\\n\t(((x) & BIT_MASK_WAKE_MAX_F2F) << BIT_SHIFT_WAKE_MAX_F2F)\n#define BITS_WAKE_MAX_F2F (BIT_MASK_WAKE_MAX_F2F << BIT_SHIFT_WAKE_MAX_F2F)\n#define BIT_CLEAR_WAKE_MAX_F2F(x) ((x) & (~BITS_WAKE_MAX_F2F))\n#define BIT_GET_WAKE_MAX_F2F(x)                                                \\\n\t(((x) >> BIT_SHIFT_WAKE_MAX_F2F) & BIT_MASK_WAKE_MAX_F2F)\n#define BIT_SET_WAKE_MAX_F2F(x, v)                                             \\\n\t(BIT_CLEAR_WAKE_MAX_F2F(x) | BIT_WAKE_MAX_F2F(v))\n\n#define BIT_SHIFT_WAKE_MIN_F2F 8\n#define BIT_MASK_WAKE_MIN_F2F 0x7\n#define BIT_WAKE_MIN_F2F(x)                                                    \\\n\t(((x) & BIT_MASK_WAKE_MIN_F2F) << BIT_SHIFT_WAKE_MIN_F2F)\n#define BITS_WAKE_MIN_F2F (BIT_MASK_WAKE_MIN_F2F << BIT_SHIFT_WAKE_MIN_F2F)\n#define BIT_CLEAR_WAKE_MIN_F2F(x) ((x) & (~BITS_WAKE_MIN_F2F))\n#define BIT_GET_WAKE_MIN_F2F(x)                                                \\\n\t(((x) >> BIT_SHIFT_WAKE_MIN_F2F) & BIT_MASK_WAKE_MIN_F2F)\n#define BIT_SET_WAKE_MIN_F2F(x, v)                                             \\\n\t(BIT_CLEAR_WAKE_MIN_F2F(x) | BIT_WAKE_MIN_F2F(v))\n\n#define BIT_APP_CPU_ACT_V1 BIT(3)\n#define BIT_APP_OBFF_V1 BIT(2)\n#define BIT_APP_IDLE_V1 BIT(1)\n#define BIT_APP_INIT_V1 BIT(0)\n\n/* 2 REG_OBFF_CTRL2_TIMER\t\t\t(Offset 0x079C) */\n\n#define BIT_SHIFT_RX_HIGH_TIMER_IDX 24\n#define BIT_MASK_RX_HIGH_TIMER_IDX 0x7\n#define BIT_RX_HIGH_TIMER_IDX(x)                                               \\\n\t(((x) & BIT_MASK_RX_HIGH_TIMER_IDX) << BIT_SHIFT_RX_HIGH_TIMER_IDX)\n#define BITS_RX_HIGH_TIMER_IDX                                                 \\\n\t(BIT_MASK_RX_HIGH_TIMER_IDX << BIT_SHIFT_RX_HIGH_TIMER_IDX)\n#define BIT_CLEAR_RX_HIGH_TIMER_IDX(x) ((x) & (~BITS_RX_HIGH_TIMER_IDX))\n#define BIT_GET_RX_HIGH_TIMER_IDX(x)                                           \\\n\t(((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX) & BIT_MASK_RX_HIGH_TIMER_IDX)\n#define BIT_SET_RX_HIGH_TIMER_IDX(x, v)                                        \\\n\t(BIT_CLEAR_RX_HIGH_TIMER_IDX(x) | BIT_RX_HIGH_TIMER_IDX(v))\n\n#define BIT_SHIFT_RX_MED_TIMER_IDX 16\n#define BIT_MASK_RX_MED_TIMER_IDX 0x7\n#define BIT_RX_MED_TIMER_IDX(x)                                                \\\n\t(((x) & BIT_MASK_RX_MED_TIMER_IDX) << BIT_SHIFT_RX_MED_TIMER_IDX)\n#define BITS_RX_MED_TIMER_IDX                                                  \\\n\t(BIT_MASK_RX_MED_TIMER_IDX << BIT_SHIFT_RX_MED_TIMER_IDX)\n#define BIT_CLEAR_RX_MED_TIMER_IDX(x) ((x) & (~BITS_RX_MED_TIMER_IDX))\n#define BIT_GET_RX_MED_TIMER_IDX(x)                                            \\\n\t(((x) >> BIT_SHIFT_RX_MED_TIMER_IDX) & BIT_MASK_RX_MED_TIMER_IDX)\n#define BIT_SET_RX_MED_TIMER_IDX(x, v)                                         \\\n\t(BIT_CLEAR_RX_MED_TIMER_IDX(x) | BIT_RX_MED_TIMER_IDX(v))\n\n#define BIT_SHIFT_RX_LOW_TIMER_IDX 8\n#define BIT_MASK_RX_LOW_TIMER_IDX 0x7\n#define BIT_RX_LOW_TIMER_IDX(x)                                                \\\n\t(((x) & BIT_MASK_RX_LOW_TIMER_IDX) << BIT_SHIFT_RX_LOW_TIMER_IDX)\n#define BITS_RX_LOW_TIMER_IDX                                                  \\\n\t(BIT_MASK_RX_LOW_TIMER_IDX << BIT_SHIFT_RX_LOW_TIMER_IDX)\n#define BIT_CLEAR_RX_LOW_TIMER_IDX(x) ((x) & (~BITS_RX_LOW_TIMER_IDX))\n#define BIT_GET_RX_LOW_TIMER_IDX(x)                                            \\\n\t(((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX) & BIT_MASK_RX_LOW_TIMER_IDX)\n#define BIT_SET_RX_LOW_TIMER_IDX(x, v)                                         \\\n\t(BIT_CLEAR_RX_LOW_TIMER_IDX(x) | BIT_RX_LOW_TIMER_IDX(v))\n\n#define BIT_SHIFT_OBFF_INT_TIMER_IDX 0\n#define BIT_MASK_OBFF_INT_TIMER_IDX 0x7\n#define BIT_OBFF_INT_TIMER_IDX(x)                                              \\\n\t(((x) & BIT_MASK_OBFF_INT_TIMER_IDX) << BIT_SHIFT_OBFF_INT_TIMER_IDX)\n#define BITS_OBFF_INT_TIMER_IDX                                                \\\n\t(BIT_MASK_OBFF_INT_TIMER_IDX << BIT_SHIFT_OBFF_INT_TIMER_IDX)\n#define BIT_CLEAR_OBFF_INT_TIMER_IDX(x) ((x) & (~BITS_OBFF_INT_TIMER_IDX))\n#define BIT_GET_OBFF_INT_TIMER_IDX(x)                                          \\\n\t(((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX) & BIT_MASK_OBFF_INT_TIMER_IDX)\n#define BIT_SET_OBFF_INT_TIMER_IDX(x, v)                                       \\\n\t(BIT_CLEAR_OBFF_INT_TIMER_IDX(x) | BIT_OBFF_INT_TIMER_IDX(v))\n\n/* 2 REG_LTR_CTRL_BASIC\t\t\t(Offset 0x07A0) */\n\n#define BIT_LTR_EN_V1 BIT(31)\n#define BIT_LTR_HW_EN_V1 BIT(30)\n#define BIT_LRT_ACT_CTS_EN BIT(29)\n#define BIT_LTR_ACT_RXPKT_EN BIT(28)\n#define BIT_LTR_ACT_RXDMA_EN BIT(27)\n#define BIT_LTR_IDLE_NO_SNOOP BIT(26)\n#define BIT_SPDUP_MGTPKT BIT(25)\n#define BIT_RX_AGG_EN BIT(24)\n#define BIT_APP_LTR_ACT BIT(23)\n#define BIT_APP_LTR_IDLE BIT(22)\n\n#define BIT_SHIFT_HIGH_RATE_TRIG_SEL 20\n#define BIT_MASK_HIGH_RATE_TRIG_SEL 0x3\n#define BIT_HIGH_RATE_TRIG_SEL(x)                                              \\\n\t(((x) & BIT_MASK_HIGH_RATE_TRIG_SEL) << BIT_SHIFT_HIGH_RATE_TRIG_SEL)\n#define BITS_HIGH_RATE_TRIG_SEL                                                \\\n\t(BIT_MASK_HIGH_RATE_TRIG_SEL << BIT_SHIFT_HIGH_RATE_TRIG_SEL)\n#define BIT_CLEAR_HIGH_RATE_TRIG_SEL(x) ((x) & (~BITS_HIGH_RATE_TRIG_SEL))\n#define BIT_GET_HIGH_RATE_TRIG_SEL(x)                                          \\\n\t(((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL) & BIT_MASK_HIGH_RATE_TRIG_SEL)\n#define BIT_SET_HIGH_RATE_TRIG_SEL(x, v)                                       \\\n\t(BIT_CLEAR_HIGH_RATE_TRIG_SEL(x) | BIT_HIGH_RATE_TRIG_SEL(v))\n\n#define BIT_SHIFT_MED_RATE_TRIG_SEL 18\n#define BIT_MASK_MED_RATE_TRIG_SEL 0x3\n#define BIT_MED_RATE_TRIG_SEL(x)                                               \\\n\t(((x) & BIT_MASK_MED_RATE_TRIG_SEL) << BIT_SHIFT_MED_RATE_TRIG_SEL)\n#define BITS_MED_RATE_TRIG_SEL                                                 \\\n\t(BIT_MASK_MED_RATE_TRIG_SEL << BIT_SHIFT_MED_RATE_TRIG_SEL)\n#define BIT_CLEAR_MED_RATE_TRIG_SEL(x) ((x) & (~BITS_MED_RATE_TRIG_SEL))\n#define BIT_GET_MED_RATE_TRIG_SEL(x)                                           \\\n\t(((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL) & BIT_MASK_MED_RATE_TRIG_SEL)\n#define BIT_SET_MED_RATE_TRIG_SEL(x, v)                                        \\\n\t(BIT_CLEAR_MED_RATE_TRIG_SEL(x) | BIT_MED_RATE_TRIG_SEL(v))\n\n#define BIT_SHIFT_LOW_RATE_TRIG_SEL 16\n#define BIT_MASK_LOW_RATE_TRIG_SEL 0x3\n#define BIT_LOW_RATE_TRIG_SEL(x)                                               \\\n\t(((x) & BIT_MASK_LOW_RATE_TRIG_SEL) << BIT_SHIFT_LOW_RATE_TRIG_SEL)\n#define BITS_LOW_RATE_TRIG_SEL                                                 \\\n\t(BIT_MASK_LOW_RATE_TRIG_SEL << BIT_SHIFT_LOW_RATE_TRIG_SEL)\n#define BIT_CLEAR_LOW_RATE_TRIG_SEL(x) ((x) & (~BITS_LOW_RATE_TRIG_SEL))\n#define BIT_GET_LOW_RATE_TRIG_SEL(x)                                           \\\n\t(((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL) & BIT_MASK_LOW_RATE_TRIG_SEL)\n#define BIT_SET_LOW_RATE_TRIG_SEL(x, v)                                        \\\n\t(BIT_CLEAR_LOW_RATE_TRIG_SEL(x) | BIT_LOW_RATE_TRIG_SEL(v))\n\n#define BIT_SHIFT_HIGH_RATE_BD_IDX 8\n#define BIT_MASK_HIGH_RATE_BD_IDX 0x7f\n#define BIT_HIGH_RATE_BD_IDX(x)                                                \\\n\t(((x) & BIT_MASK_HIGH_RATE_BD_IDX) << BIT_SHIFT_HIGH_RATE_BD_IDX)\n#define BITS_HIGH_RATE_BD_IDX                                                  \\\n\t(BIT_MASK_HIGH_RATE_BD_IDX << BIT_SHIFT_HIGH_RATE_BD_IDX)\n#define BIT_CLEAR_HIGH_RATE_BD_IDX(x) ((x) & (~BITS_HIGH_RATE_BD_IDX))\n#define BIT_GET_HIGH_RATE_BD_IDX(x)                                            \\\n\t(((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX) & BIT_MASK_HIGH_RATE_BD_IDX)\n#define BIT_SET_HIGH_RATE_BD_IDX(x, v)                                         \\\n\t(BIT_CLEAR_HIGH_RATE_BD_IDX(x) | BIT_HIGH_RATE_BD_IDX(v))\n\n#define BIT_SHIFT_LOW_RATE_BD_IDX 0\n#define BIT_MASK_LOW_RATE_BD_IDX 0x7f\n#define BIT_LOW_RATE_BD_IDX(x)                                                 \\\n\t(((x) & BIT_MASK_LOW_RATE_BD_IDX) << BIT_SHIFT_LOW_RATE_BD_IDX)\n#define BITS_LOW_RATE_BD_IDX                                                   \\\n\t(BIT_MASK_LOW_RATE_BD_IDX << BIT_SHIFT_LOW_RATE_BD_IDX)\n#define BIT_CLEAR_LOW_RATE_BD_IDX(x) ((x) & (~BITS_LOW_RATE_BD_IDX))\n#define BIT_GET_LOW_RATE_BD_IDX(x)                                             \\\n\t(((x) >> BIT_SHIFT_LOW_RATE_BD_IDX) & BIT_MASK_LOW_RATE_BD_IDX)\n#define BIT_SET_LOW_RATE_BD_IDX(x, v)                                          \\\n\t(BIT_CLEAR_LOW_RATE_BD_IDX(x) | BIT_LOW_RATE_BD_IDX(v))\n\n/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD\t\t(Offset 0x07A4) */\n\n#define BIT_SHIFT_RX_EMPTY_TIMER_IDX 24\n#define BIT_MASK_RX_EMPTY_TIMER_IDX 0x7\n#define BIT_RX_EMPTY_TIMER_IDX(x)                                              \\\n\t(((x) & BIT_MASK_RX_EMPTY_TIMER_IDX) << BIT_SHIFT_RX_EMPTY_TIMER_IDX)\n#define BITS_RX_EMPTY_TIMER_IDX                                                \\\n\t(BIT_MASK_RX_EMPTY_TIMER_IDX << BIT_SHIFT_RX_EMPTY_TIMER_IDX)\n#define BIT_CLEAR_RX_EMPTY_TIMER_IDX(x) ((x) & (~BITS_RX_EMPTY_TIMER_IDX))\n#define BIT_GET_RX_EMPTY_TIMER_IDX(x)                                          \\\n\t(((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX) & BIT_MASK_RX_EMPTY_TIMER_IDX)\n#define BIT_SET_RX_EMPTY_TIMER_IDX(x, v)                                       \\\n\t(BIT_CLEAR_RX_EMPTY_TIMER_IDX(x) | BIT_RX_EMPTY_TIMER_IDX(v))\n\n#define BIT_SHIFT_RX_AFULL_TH_IDX 20\n#define BIT_MASK_RX_AFULL_TH_IDX 0x7\n#define BIT_RX_AFULL_TH_IDX(x)                                                 \\\n\t(((x) & BIT_MASK_RX_AFULL_TH_IDX) << BIT_SHIFT_RX_AFULL_TH_IDX)\n#define BITS_RX_AFULL_TH_IDX                                                   \\\n\t(BIT_MASK_RX_AFULL_TH_IDX << BIT_SHIFT_RX_AFULL_TH_IDX)\n#define BIT_CLEAR_RX_AFULL_TH_IDX(x) ((x) & (~BITS_RX_AFULL_TH_IDX))\n#define BIT_GET_RX_AFULL_TH_IDX(x)                                             \\\n\t(((x) >> BIT_SHIFT_RX_AFULL_TH_IDX) & BIT_MASK_RX_AFULL_TH_IDX)\n#define BIT_SET_RX_AFULL_TH_IDX(x, v)                                          \\\n\t(BIT_CLEAR_RX_AFULL_TH_IDX(x) | BIT_RX_AFULL_TH_IDX(v))\n\n#define BIT_SHIFT_RX_HIGH_TH_IDX 16\n#define BIT_MASK_RX_HIGH_TH_IDX 0x7\n#define BIT_RX_HIGH_TH_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_RX_HIGH_TH_IDX) << BIT_SHIFT_RX_HIGH_TH_IDX)\n#define BITS_RX_HIGH_TH_IDX                                                    \\\n\t(BIT_MASK_RX_HIGH_TH_IDX << BIT_SHIFT_RX_HIGH_TH_IDX)\n#define BIT_CLEAR_RX_HIGH_TH_IDX(x) ((x) & (~BITS_RX_HIGH_TH_IDX))\n#define BIT_GET_RX_HIGH_TH_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_RX_HIGH_TH_IDX) & BIT_MASK_RX_HIGH_TH_IDX)\n#define BIT_SET_RX_HIGH_TH_IDX(x, v)                                           \\\n\t(BIT_CLEAR_RX_HIGH_TH_IDX(x) | BIT_RX_HIGH_TH_IDX(v))\n\n#define BIT_SHIFT_RX_MED_TH_IDX 12\n#define BIT_MASK_RX_MED_TH_IDX 0x7\n#define BIT_RX_MED_TH_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_RX_MED_TH_IDX) << BIT_SHIFT_RX_MED_TH_IDX)\n#define BITS_RX_MED_TH_IDX (BIT_MASK_RX_MED_TH_IDX << BIT_SHIFT_RX_MED_TH_IDX)\n#define BIT_CLEAR_RX_MED_TH_IDX(x) ((x) & (~BITS_RX_MED_TH_IDX))\n#define BIT_GET_RX_MED_TH_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_RX_MED_TH_IDX) & BIT_MASK_RX_MED_TH_IDX)\n#define BIT_SET_RX_MED_TH_IDX(x, v)                                            \\\n\t(BIT_CLEAR_RX_MED_TH_IDX(x) | BIT_RX_MED_TH_IDX(v))\n\n#define BIT_SHIFT_RX_LOW_TH_IDX 8\n#define BIT_MASK_RX_LOW_TH_IDX 0x7\n#define BIT_RX_LOW_TH_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_RX_LOW_TH_IDX) << BIT_SHIFT_RX_LOW_TH_IDX)\n#define BITS_RX_LOW_TH_IDX (BIT_MASK_RX_LOW_TH_IDX << BIT_SHIFT_RX_LOW_TH_IDX)\n#define BIT_CLEAR_RX_LOW_TH_IDX(x) ((x) & (~BITS_RX_LOW_TH_IDX))\n#define BIT_GET_RX_LOW_TH_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_RX_LOW_TH_IDX) & BIT_MASK_RX_LOW_TH_IDX)\n#define BIT_SET_RX_LOW_TH_IDX(x, v)                                            \\\n\t(BIT_CLEAR_RX_LOW_TH_IDX(x) | BIT_RX_LOW_TH_IDX(v))\n\n#define BIT_SHIFT_LTR_SPACE_IDX 4\n#define BIT_MASK_LTR_SPACE_IDX 0x3\n#define BIT_LTR_SPACE_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_LTR_SPACE_IDX) << BIT_SHIFT_LTR_SPACE_IDX)\n#define BITS_LTR_SPACE_IDX (BIT_MASK_LTR_SPACE_IDX << BIT_SHIFT_LTR_SPACE_IDX)\n#define BIT_CLEAR_LTR_SPACE_IDX(x) ((x) & (~BITS_LTR_SPACE_IDX))\n#define BIT_GET_LTR_SPACE_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_LTR_SPACE_IDX) & BIT_MASK_LTR_SPACE_IDX)\n#define BIT_SET_LTR_SPACE_IDX(x, v)                                            \\\n\t(BIT_CLEAR_LTR_SPACE_IDX(x) | BIT_LTR_SPACE_IDX(v))\n\n#define BIT_SHIFT_LTR_IDLE_TIMER_IDX 0\n#define BIT_MASK_LTR_IDLE_TIMER_IDX 0x7\n#define BIT_LTR_IDLE_TIMER_IDX(x)                                              \\\n\t(((x) & BIT_MASK_LTR_IDLE_TIMER_IDX) << BIT_SHIFT_LTR_IDLE_TIMER_IDX)\n#define BITS_LTR_IDLE_TIMER_IDX                                                \\\n\t(BIT_MASK_LTR_IDLE_TIMER_IDX << BIT_SHIFT_LTR_IDLE_TIMER_IDX)\n#define BIT_CLEAR_LTR_IDLE_TIMER_IDX(x) ((x) & (~BITS_LTR_IDLE_TIMER_IDX))\n#define BIT_GET_LTR_IDLE_TIMER_IDX(x)                                          \\\n\t(((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX) & BIT_MASK_LTR_IDLE_TIMER_IDX)\n#define BIT_SET_LTR_IDLE_TIMER_IDX(x, v)                                       \\\n\t(BIT_CLEAR_LTR_IDLE_TIMER_IDX(x) | BIT_LTR_IDLE_TIMER_IDX(v))\n\n/* 2 REG_LTR_IDLE_LATENCY_V1\t\t\t(Offset 0x07A8) */\n\n#define BIT_SHIFT_LTR_IDLE_L 0\n#define BIT_MASK_LTR_IDLE_L 0xffffffffL\n#define BIT_LTR_IDLE_L(x) (((x) & BIT_MASK_LTR_IDLE_L) << BIT_SHIFT_LTR_IDLE_L)\n#define BITS_LTR_IDLE_L (BIT_MASK_LTR_IDLE_L << BIT_SHIFT_LTR_IDLE_L)\n#define BIT_CLEAR_LTR_IDLE_L(x) ((x) & (~BITS_LTR_IDLE_L))\n#define BIT_GET_LTR_IDLE_L(x)                                                  \\\n\t(((x) >> BIT_SHIFT_LTR_IDLE_L) & BIT_MASK_LTR_IDLE_L)\n#define BIT_SET_LTR_IDLE_L(x, v) (BIT_CLEAR_LTR_IDLE_L(x) | BIT_LTR_IDLE_L(v))\n\n/* 2 REG_LTR_ACTIVE_LATENCY_V1\t\t(Offset 0x07AC) */\n\n#define BIT_SHIFT_LTR_ACT_L 0\n#define BIT_MASK_LTR_ACT_L 0xffffffffL\n#define BIT_LTR_ACT_L(x) (((x) & BIT_MASK_LTR_ACT_L) << BIT_SHIFT_LTR_ACT_L)\n#define BITS_LTR_ACT_L (BIT_MASK_LTR_ACT_L << BIT_SHIFT_LTR_ACT_L)\n#define BIT_CLEAR_LTR_ACT_L(x) ((x) & (~BITS_LTR_ACT_L))\n#define BIT_GET_LTR_ACT_L(x) (((x) >> BIT_SHIFT_LTR_ACT_L) & BIT_MASK_LTR_ACT_L)\n#define BIT_SET_LTR_ACT_L(x, v) (BIT_CLEAR_LTR_ACT_L(x) | BIT_LTR_ACT_L(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_LTR_ACTIVE_LATENCY_V1\t\t(Offset 0x07AC) */\n\n#define BIT_SHIFT_ANT_ADDR2_1 0\n#define BIT_MASK_ANT_ADDR2_1 0xffffffffL\n#define BIT_ANT_ADDR2_1(x)                                                     \\\n\t(((x) & BIT_MASK_ANT_ADDR2_1) << BIT_SHIFT_ANT_ADDR2_1)\n#define BITS_ANT_ADDR2_1 (BIT_MASK_ANT_ADDR2_1 << BIT_SHIFT_ANT_ADDR2_1)\n#define BIT_CLEAR_ANT_ADDR2_1(x) ((x) & (~BITS_ANT_ADDR2_1))\n#define BIT_GET_ANT_ADDR2_1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ANT_ADDR2_1) & BIT_MASK_ANT_ADDR2_1)\n#define BIT_SET_ANT_ADDR2_1(x, v)                                              \\\n\t(BIT_CLEAR_ANT_ADDR2_1(x) | BIT_ANT_ADDR2_1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER\t(Offset 0x07B0) */\n\n#define BIT_APPEND_MACID_IN_RESP_EN BIT(50)\n#define BIT_ADDR2_MATCH_EN BIT(49)\n#define BIT_ANTTRN_EN BIT(48)\n\n#define BIT_SHIFT_TRAIN_STA_ADDR 0\n#define BIT_MASK_TRAIN_STA_ADDR 0xffffffffffffL\n#define BIT_TRAIN_STA_ADDR(x)                                                  \\\n\t(((x) & BIT_MASK_TRAIN_STA_ADDR) << BIT_SHIFT_TRAIN_STA_ADDR)\n#define BITS_TRAIN_STA_ADDR                                                    \\\n\t(BIT_MASK_TRAIN_STA_ADDR << BIT_SHIFT_TRAIN_STA_ADDR)\n#define BIT_CLEAR_TRAIN_STA_ADDR(x) ((x) & (~BITS_TRAIN_STA_ADDR))\n#define BIT_GET_TRAIN_STA_ADDR(x)                                              \\\n\t(((x) >> BIT_SHIFT_TRAIN_STA_ADDR) & BIT_MASK_TRAIN_STA_ADDR)\n#define BIT_SET_TRAIN_STA_ADDR(x, v)                                           \\\n\t(BIT_CLEAR_TRAIN_STA_ADDR(x) | BIT_TRAIN_STA_ADDR(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER\t(Offset 0x07B0) */\n\n#define BIT_SHIFT_TRAIN_STA_ADDR_0 0\n#define BIT_MASK_TRAIN_STA_ADDR_0 0xffffffffL\n#define BIT_TRAIN_STA_ADDR_0(x)                                                \\\n\t(((x) & BIT_MASK_TRAIN_STA_ADDR_0) << BIT_SHIFT_TRAIN_STA_ADDR_0)\n#define BITS_TRAIN_STA_ADDR_0                                                  \\\n\t(BIT_MASK_TRAIN_STA_ADDR_0 << BIT_SHIFT_TRAIN_STA_ADDR_0)\n#define BIT_CLEAR_TRAIN_STA_ADDR_0(x) ((x) & (~BITS_TRAIN_STA_ADDR_0))\n#define BIT_GET_TRAIN_STA_ADDR_0(x)                                            \\\n\t(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0) & BIT_MASK_TRAIN_STA_ADDR_0)\n#define BIT_SET_TRAIN_STA_ADDR_0(x, v)                                         \\\n\t(BIT_CLEAR_TRAIN_STA_ADDR_0(x) | BIT_TRAIN_STA_ADDR_0(v))\n\n/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 (Offset 0x07B4) */\n\n#define BIT_SHIFT_TRAIN_STA_ADDR_1 0\n#define BIT_MASK_TRAIN_STA_ADDR_1 0xffff\n#define BIT_TRAIN_STA_ADDR_1(x)                                                \\\n\t(((x) & BIT_MASK_TRAIN_STA_ADDR_1) << BIT_SHIFT_TRAIN_STA_ADDR_1)\n#define BITS_TRAIN_STA_ADDR_1                                                  \\\n\t(BIT_MASK_TRAIN_STA_ADDR_1 << BIT_SHIFT_TRAIN_STA_ADDR_1)\n#define BIT_CLEAR_TRAIN_STA_ADDR_1(x) ((x) & (~BITS_TRAIN_STA_ADDR_1))\n#define BIT_GET_TRAIN_STA_ADDR_1(x)                                            \\\n\t(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1) & BIT_MASK_TRAIN_STA_ADDR_1)\n#define BIT_SET_TRAIN_STA_ADDR_1(x, v)                                         \\\n\t(BIT_CLEAR_TRAIN_STA_ADDR_1(x) | BIT_TRAIN_STA_ADDR_1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SMART_ANT_CTRL\t\t\t(Offset 0x07B4) */\n\n#define BIT_SHIFT_ANT_ADDR2_2 0\n#define BIT_MASK_ANT_ADDR2_2 0xffff\n#define BIT_ANT_ADDR2_2(x)                                                     \\\n\t(((x) & BIT_MASK_ANT_ADDR2_2) << BIT_SHIFT_ANT_ADDR2_2)\n#define BITS_ANT_ADDR2_2 (BIT_MASK_ANT_ADDR2_2 << BIT_SHIFT_ANT_ADDR2_2)\n#define BIT_CLEAR_ANT_ADDR2_2(x) ((x) & (~BITS_ANT_ADDR2_2))\n#define BIT_GET_ANT_ADDR2_2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ANT_ADDR2_2) & BIT_MASK_ANT_ADDR2_2)\n#define BIT_SET_ANT_ADDR2_2(x, v)                                              \\\n\t(BIT_CLEAR_ANT_ADDR2_2(x) | BIT_ANT_ADDR2_2(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_PKTCNT_RWD\t\t\t(Offset 0x07B8) */\n\n#define BIT_SHIFT_PKTCNT_BSSIDMAP 4\n#define BIT_MASK_PKTCNT_BSSIDMAP 0xf\n#define BIT_PKTCNT_BSSIDMAP(x)                                                 \\\n\t(((x) & BIT_MASK_PKTCNT_BSSIDMAP) << BIT_SHIFT_PKTCNT_BSSIDMAP)\n#define BITS_PKTCNT_BSSIDMAP                                                   \\\n\t(BIT_MASK_PKTCNT_BSSIDMAP << BIT_SHIFT_PKTCNT_BSSIDMAP)\n#define BIT_CLEAR_PKTCNT_BSSIDMAP(x) ((x) & (~BITS_PKTCNT_BSSIDMAP))\n#define BIT_GET_PKTCNT_BSSIDMAP(x)                                             \\\n\t(((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP) & BIT_MASK_PKTCNT_BSSIDMAP)\n#define BIT_SET_PKTCNT_BSSIDMAP(x, v)                                          \\\n\t(BIT_CLEAR_PKTCNT_BSSIDMAP(x) | BIT_PKTCNT_BSSIDMAP(v))\n\n#define BIT_PKTCNT_CNTRST BIT(1)\n#define BIT_PKTCNT_CNTEN BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CONTROL_FRAME_REPORT\t\t(Offset 0x07B8) */\n\n#define BIT_SHIFT_CONTROL_FRAME_REPORT 0\n#define BIT_MASK_CONTROL_FRAME_REPORT 0xffffffffL\n#define BIT_CONTROL_FRAME_REPORT(x)                                            \\\n\t(((x) & BIT_MASK_CONTROL_FRAME_REPORT)                                 \\\n\t << BIT_SHIFT_CONTROL_FRAME_REPORT)\n#define BITS_CONTROL_FRAME_REPORT                                              \\\n\t(BIT_MASK_CONTROL_FRAME_REPORT << BIT_SHIFT_CONTROL_FRAME_REPORT)\n#define BIT_CLEAR_CONTROL_FRAME_REPORT(x) ((x) & (~BITS_CONTROL_FRAME_REPORT))\n#define BIT_GET_CONTROL_FRAME_REPORT(x)                                        \\\n\t(((x) >> BIT_SHIFT_CONTROL_FRAME_REPORT) &                             \\\n\t BIT_MASK_CONTROL_FRAME_REPORT)\n#define BIT_SET_CONTROL_FRAME_REPORT(x, v)                                     \\\n\t(BIT_CLEAR_CONTROL_FRAME_REPORT(x) | BIT_CONTROL_FRAME_REPORT(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_PKTCNT_CTRL\t\t\t(Offset 0x07BC) */\n\n#define BIT_WMAC_PKTCNT_TRST BIT(9)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CONTROL_FRAME_CNT_CTRL\t\t(Offset 0x07BC) */\n\n#define BIT_ALLCNTRST BIT(9)\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_PKTCNT_CTRL\t\t\t(Offset 0x07BC) */\n\n#define BIT_WMAC_PKTCNT_FEN BIT(8)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CONTROL_FRAME_CNT_CTRL\t\t(Offset 0x07BC) */\n\n#define BIT__ALLCNTEN BIT(8)\n\n#define BIT_SHIFT_ADDR 4\n#define BIT_MASK_ADDR 0xf\n#define BIT_ADDR(x) (((x) & BIT_MASK_ADDR) << BIT_SHIFT_ADDR)\n#define BITS_ADDR (BIT_MASK_ADDR << BIT_SHIFT_ADDR)\n#define BIT_CLEAR_ADDR(x) ((x) & (~BITS_ADDR))\n#define BIT_GET_ADDR(x) (((x) >> BIT_SHIFT_ADDR) & BIT_MASK_ADDR)\n#define BIT_SET_ADDR(x, v) (BIT_CLEAR_ADDR(x) | BIT_ADDR(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_WMAC_PKTCNT_CTRL\t\t\t(Offset 0x07BC) */\n\n#define BIT_SHIFT_WMAC_PKTCNT_CFGAD 0\n#define BIT_MASK_WMAC_PKTCNT_CFGAD 0xff\n#define BIT_WMAC_PKTCNT_CFGAD(x)                                               \\\n\t(((x) & BIT_MASK_WMAC_PKTCNT_CFGAD) << BIT_SHIFT_WMAC_PKTCNT_CFGAD)\n#define BITS_WMAC_PKTCNT_CFGAD                                                 \\\n\t(BIT_MASK_WMAC_PKTCNT_CFGAD << BIT_SHIFT_WMAC_PKTCNT_CFGAD)\n#define BIT_CLEAR_WMAC_PKTCNT_CFGAD(x) ((x) & (~BITS_WMAC_PKTCNT_CFGAD))\n#define BIT_GET_WMAC_PKTCNT_CFGAD(x)                                           \\\n\t(((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD) & BIT_MASK_WMAC_PKTCNT_CFGAD)\n#define BIT_SET_WMAC_PKTCNT_CFGAD(x, v)                                        \\\n\t(BIT_CLEAR_WMAC_PKTCNT_CFGAD(x) | BIT_WMAC_PKTCNT_CFGAD(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CONTROL_FRAME_CNT_CTRL\t\t(Offset 0x07BC) */\n\n#define BIT_SHIFT_CTRL_SEL 0\n#define BIT_MASK_CTRL_SEL 0xf\n#define BIT_CTRL_SEL(x) (((x) & BIT_MASK_CTRL_SEL) << BIT_SHIFT_CTRL_SEL)\n#define BITS_CTRL_SEL (BIT_MASK_CTRL_SEL << BIT_SHIFT_CTRL_SEL)\n#define BIT_CLEAR_CTRL_SEL(x) ((x) & (~BITS_CTRL_SEL))\n#define BIT_GET_CTRL_SEL(x) (((x) >> BIT_SHIFT_CTRL_SEL) & BIT_MASK_CTRL_SEL)\n#define BIT_SET_CTRL_SEL(x, v) (BIT_CLEAR_CTRL_SEL(x) | BIT_CTRL_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_IQ_DUMP\t\t\t\t(Offset 0x07C0) */\n\n#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC (64 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_WMAC_MATCH_REF_MAC 0xffffffffL\n#define BIT_R_WMAC_MATCH_REF_MAC(x)                                            \\\n\t(((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC)                                 \\\n\t << BIT_SHIFT_R_WMAC_MATCH_REF_MAC)\n#define BITS_R_WMAC_MATCH_REF_MAC                                              \\\n\t(BIT_MASK_R_WMAC_MATCH_REF_MAC << BIT_SHIFT_R_WMAC_MATCH_REF_MAC)\n#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC(x) ((x) & (~BITS_R_WMAC_MATCH_REF_MAC))\n#define BIT_GET_R_WMAC_MATCH_REF_MAC(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC) &                             \\\n\t BIT_MASK_R_WMAC_MATCH_REF_MAC)\n#define BIT_SET_R_WMAC_MATCH_REF_MAC(x, v)                                     \\\n\t(BIT_CLEAR_R_WMAC_MATCH_REF_MAC(x) | BIT_R_WMAC_MATCH_REF_MAC(v))\n\n#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH (56 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH 0xff\n#define BIT_R_WMAC_RXFIFO_FULL_TH(x)                                           \\\n\t(((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH)                                \\\n\t << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH)\n#define BITS_R_WMAC_RXFIFO_FULL_TH                                             \\\n\t(BIT_MASK_R_WMAC_RXFIFO_FULL_TH << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH)\n#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH(x) ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH))\n#define BIT_GET_R_WMAC_RXFIFO_FULL_TH(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) &                            \\\n\t BIT_MASK_R_WMAC_RXFIFO_FULL_TH)\n#define BIT_SET_R_WMAC_RXFIFO_FULL_TH(x, v)                                    \\\n\t(BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH(x) | BIT_R_WMAC_RXFIFO_FULL_TH(v))\n\n#define BIT_R_WMAC_SRCH_TXRPT_TYPE BIT(51)\n#define BIT_R_WMAC_NDP_RST BIT(50)\n#define BIT_R_WMAC_POWINT_EN BIT(49)\n#define BIT_R_WMAC_SRCH_TXRPT_PERPKT BIT(48)\n#define BIT_R_WMAC_SRCH_TXRPT_MID BIT(47)\n#define BIT_R_WMAC_PFIN_TOEN BIT(46)\n#define BIT_R_WMAC_FIL_SECERR BIT(45)\n#define BIT_R_WMAC_FIL_CTLPKTLEN BIT(44)\n#define BIT_R_WMAC_FIL_FCTYPE BIT(43)\n#define BIT_R_WMAC_FIL_FCPROVER BIT(42)\n#define BIT_R_WMAC_PHYSTS_SNIF BIT(41)\n#define BIT_R_WMAC_PHYSTS_PLCP BIT(40)\n#define BIT_R_MAC_TCR_VBONF_RD BIT(39)\n#define BIT_R_WMAC_TCR_MPAR_NDP BIT(38)\n#define BIT_R_WMAC_NDP_FILTER BIT(37)\n#define BIT_R_WMAC_RXLEN_SEL BIT(36)\n#define BIT_R_WMAC_RXLEN_SEL1 BIT(35)\n#define BIT_R_OFDM_FILTER BIT(34)\n#define BIT_R_WMAC_CHK_OFDM_LEN BIT(33)\n\n#define BIT_SHIFT_R_WMAC_MASK_LA_MAC (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_WMAC_MASK_LA_MAC 0xffffffffL\n#define BIT_R_WMAC_MASK_LA_MAC(x)                                              \\\n\t(((x) & BIT_MASK_R_WMAC_MASK_LA_MAC) << BIT_SHIFT_R_WMAC_MASK_LA_MAC)\n#define BITS_R_WMAC_MASK_LA_MAC                                                \\\n\t(BIT_MASK_R_WMAC_MASK_LA_MAC << BIT_SHIFT_R_WMAC_MASK_LA_MAC)\n#define BIT_CLEAR_R_WMAC_MASK_LA_MAC(x) ((x) & (~BITS_R_WMAC_MASK_LA_MAC))\n#define BIT_GET_R_WMAC_MASK_LA_MAC(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC) & BIT_MASK_R_WMAC_MASK_LA_MAC)\n#define BIT_SET_R_WMAC_MASK_LA_MAC(x, v)                                       \\\n\t(BIT_CLEAR_R_WMAC_MASK_LA_MAC(x) | BIT_R_WMAC_MASK_LA_MAC(v))\n\n#define BIT_R_WMAC_CHK_CCK_LEN BIT(32)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL\t(Offset 0x07C0) */\n\n#define BIT_LTECOEX_ACCESS_START BIT(31)\n#define BIT_LTECOEX_WRITE_MODE BIT(30)\n#define BIT_LTECOEX_READY_BIT BIT(29)\n\n#define BIT_SHIFT_WRITE_BYTE_EN 16\n#define BIT_MASK_WRITE_BYTE_EN 0xf\n#define BIT_WRITE_BYTE_EN(x)                                                   \\\n\t(((x) & BIT_MASK_WRITE_BYTE_EN) << BIT_SHIFT_WRITE_BYTE_EN)\n#define BITS_WRITE_BYTE_EN (BIT_MASK_WRITE_BYTE_EN << BIT_SHIFT_WRITE_BYTE_EN)\n#define BIT_CLEAR_WRITE_BYTE_EN(x) ((x) & (~BITS_WRITE_BYTE_EN))\n#define BIT_GET_WRITE_BYTE_EN(x)                                               \\\n\t(((x) >> BIT_SHIFT_WRITE_BYTE_EN) & BIT_MASK_WRITE_BYTE_EN)\n#define BIT_SET_WRITE_BYTE_EN(x, v)                                            \\\n\t(BIT_CLEAR_WRITE_BYTE_EN(x) | BIT_WRITE_BYTE_EN(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_IQ_DUMP\t\t\t\t(Offset 0x07C0) */\n\n#define BIT_SHIFT_DUMP_OK_ADDR 16\n#define BIT_MASK_DUMP_OK_ADDR 0xffff\n#define BIT_DUMP_OK_ADDR(x)                                                    \\\n\t(((x) & BIT_MASK_DUMP_OK_ADDR) << BIT_SHIFT_DUMP_OK_ADDR)\n#define BITS_DUMP_OK_ADDR (BIT_MASK_DUMP_OK_ADDR << BIT_SHIFT_DUMP_OK_ADDR)\n#define BIT_CLEAR_DUMP_OK_ADDR(x) ((x) & (~BITS_DUMP_OK_ADDR))\n#define BIT_GET_DUMP_OK_ADDR(x)                                                \\\n\t(((x) >> BIT_SHIFT_DUMP_OK_ADDR) & BIT_MASK_DUMP_OK_ADDR)\n#define BIT_SET_DUMP_OK_ADDR(x, v)                                             \\\n\t(BIT_CLEAR_DUMP_OK_ADDR(x) | BIT_DUMP_OK_ADDR(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_IQ_DUMP\t\t\t\t(Offset 0x07C0) */\n\n#define BIT_SHIFT_DUMP_OK_ADDR_V1 15\n#define BIT_MASK_DUMP_OK_ADDR_V1 0x1ffff\n#define BIT_DUMP_OK_ADDR_V1(x)                                                 \\\n\t(((x) & BIT_MASK_DUMP_OK_ADDR_V1) << BIT_SHIFT_DUMP_OK_ADDR_V1)\n#define BITS_DUMP_OK_ADDR_V1                                                   \\\n\t(BIT_MASK_DUMP_OK_ADDR_V1 << BIT_SHIFT_DUMP_OK_ADDR_V1)\n#define BIT_CLEAR_DUMP_OK_ADDR_V1(x) ((x) & (~BITS_DUMP_OK_ADDR_V1))\n#define BIT_GET_DUMP_OK_ADDR_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_DUMP_OK_ADDR_V1) & BIT_MASK_DUMP_OK_ADDR_V1)\n#define BIT_SET_DUMP_OK_ADDR_V1(x, v)                                          \\\n\t(BIT_CLEAR_DUMP_OK_ADDR_V1(x) | BIT_DUMP_OK_ADDR_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_IQ_DUMP\t\t\t\t(Offset 0x07C0) */\n\n#define BIT_MACDBG_TRIG_IQDUMP BIT(15)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_IQ_DUMP\t\t\t\t(Offset 0x07C0) */\n\n#define BIT_SHIFT_R_TRIG_TIME_SEL 8\n#define BIT_MASK_R_TRIG_TIME_SEL 0x7f\n#define BIT_R_TRIG_TIME_SEL(x)                                                 \\\n\t(((x) & BIT_MASK_R_TRIG_TIME_SEL) << BIT_SHIFT_R_TRIG_TIME_SEL)\n#define BITS_R_TRIG_TIME_SEL                                                   \\\n\t(BIT_MASK_R_TRIG_TIME_SEL << BIT_SHIFT_R_TRIG_TIME_SEL)\n#define BIT_CLEAR_R_TRIG_TIME_SEL(x) ((x) & (~BITS_R_TRIG_TIME_SEL))\n#define BIT_GET_R_TRIG_TIME_SEL(x)                                             \\\n\t(((x) >> BIT_SHIFT_R_TRIG_TIME_SEL) & BIT_MASK_R_TRIG_TIME_SEL)\n#define BIT_SET_R_TRIG_TIME_SEL(x, v)                                          \\\n\t(BIT_CLEAR_R_TRIG_TIME_SEL(x) | BIT_R_TRIG_TIME_SEL(v))\n\n#define BIT_SHIFT_R_MAC_TRIG_SEL 6\n#define BIT_MASK_R_MAC_TRIG_SEL 0x3\n#define BIT_R_MAC_TRIG_SEL(x)                                                  \\\n\t(((x) & BIT_MASK_R_MAC_TRIG_SEL) << BIT_SHIFT_R_MAC_TRIG_SEL)\n#define BITS_R_MAC_TRIG_SEL                                                    \\\n\t(BIT_MASK_R_MAC_TRIG_SEL << BIT_SHIFT_R_MAC_TRIG_SEL)\n#define BIT_CLEAR_R_MAC_TRIG_SEL(x) ((x) & (~BITS_R_MAC_TRIG_SEL))\n#define BIT_GET_R_MAC_TRIG_SEL(x)                                              \\\n\t(((x) >> BIT_SHIFT_R_MAC_TRIG_SEL) & BIT_MASK_R_MAC_TRIG_SEL)\n#define BIT_SET_R_MAC_TRIG_SEL(x, v)                                           \\\n\t(BIT_CLEAR_R_MAC_TRIG_SEL(x) | BIT_R_MAC_TRIG_SEL(v))\n\n#define BIT_MAC_TRIG_REG BIT(5)\n\n#define BIT_SHIFT_R_LEVEL_PULSE_SEL 3\n#define BIT_MASK_R_LEVEL_PULSE_SEL 0x3\n#define BIT_R_LEVEL_PULSE_SEL(x)                                               \\\n\t(((x) & BIT_MASK_R_LEVEL_PULSE_SEL) << BIT_SHIFT_R_LEVEL_PULSE_SEL)\n#define BITS_R_LEVEL_PULSE_SEL                                                 \\\n\t(BIT_MASK_R_LEVEL_PULSE_SEL << BIT_SHIFT_R_LEVEL_PULSE_SEL)\n#define BIT_CLEAR_R_LEVEL_PULSE_SEL(x) ((x) & (~BITS_R_LEVEL_PULSE_SEL))\n#define BIT_GET_R_LEVEL_PULSE_SEL(x)                                           \\\n\t(((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL) & BIT_MASK_R_LEVEL_PULSE_SEL)\n#define BIT_SET_R_LEVEL_PULSE_SEL(x, v)                                        \\\n\t(BIT_CLEAR_R_LEVEL_PULSE_SEL(x) | BIT_R_LEVEL_PULSE_SEL(v))\n\n#define BIT_EN_LA_MAC BIT(2)\n#define BIT_R_EN_IQDUMP BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL\t(Offset 0x07C0) */\n\n#define BIT_SHIFT_LTECOEX_REG_ADDR 0\n#define BIT_MASK_LTECOEX_REG_ADDR 0xffff\n#define BIT_LTECOEX_REG_ADDR(x)                                                \\\n\t(((x) & BIT_MASK_LTECOEX_REG_ADDR) << BIT_SHIFT_LTECOEX_REG_ADDR)\n#define BITS_LTECOEX_REG_ADDR                                                  \\\n\t(BIT_MASK_LTECOEX_REG_ADDR << BIT_SHIFT_LTECOEX_REG_ADDR)\n#define BIT_CLEAR_LTECOEX_REG_ADDR(x) ((x) & (~BITS_LTECOEX_REG_ADDR))\n#define BIT_GET_LTECOEX_REG_ADDR(x)                                            \\\n\t(((x) >> BIT_SHIFT_LTECOEX_REG_ADDR) & BIT_MASK_LTECOEX_REG_ADDR)\n#define BIT_SET_LTECOEX_REG_ADDR(x, v)                                         \\\n\t(BIT_CLEAR_LTECOEX_REG_ADDR(x) | BIT_LTECOEX_REG_ADDR(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_IQ_DUMP\t\t\t\t(Offset 0x07C0) */\n\n#define BIT_R_IQDATA_DUMP BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA (Offset 0x07C4) */\n\n#define BIT_SHIFT_LTECOEX_W_DATA 0\n#define BIT_MASK_LTECOEX_W_DATA 0xffffffffL\n#define BIT_LTECOEX_W_DATA(x)                                                  \\\n\t(((x) & BIT_MASK_LTECOEX_W_DATA) << BIT_SHIFT_LTECOEX_W_DATA)\n#define BITS_LTECOEX_W_DATA                                                    \\\n\t(BIT_MASK_LTECOEX_W_DATA << BIT_SHIFT_LTECOEX_W_DATA)\n#define BIT_CLEAR_LTECOEX_W_DATA(x) ((x) & (~BITS_LTECOEX_W_DATA))\n#define BIT_GET_LTECOEX_W_DATA(x)                                              \\\n\t(((x) >> BIT_SHIFT_LTECOEX_W_DATA) & BIT_MASK_LTECOEX_W_DATA)\n#define BIT_SET_LTECOEX_W_DATA(x, v)                                           \\\n\t(BIT_CLEAR_LTECOEX_W_DATA(x) | BIT_LTECOEX_W_DATA(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_IQ_DUMP_1\t\t\t\t(Offset 0x07C4) */\n\n#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1 0\n#define BIT_MASK_R_WMAC_MASK_LA_MAC_1 0xffffffffL\n#define BIT_R_WMAC_MASK_LA_MAC_1(x)                                            \\\n\t(((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1)                                 \\\n\t << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1)\n#define BITS_R_WMAC_MASK_LA_MAC_1                                              \\\n\t(BIT_MASK_R_WMAC_MASK_LA_MAC_1 << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1)\n#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1(x) ((x) & (~BITS_R_WMAC_MASK_LA_MAC_1))\n#define BIT_GET_R_WMAC_MASK_LA_MAC_1(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) &                             \\\n\t BIT_MASK_R_WMAC_MASK_LA_MAC_1)\n#define BIT_SET_R_WMAC_MASK_LA_MAC_1(x, v)                                     \\\n\t(BIT_CLEAR_R_WMAC_MASK_LA_MAC_1(x) | BIT_R_WMAC_MASK_LA_MAC_1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA (Offset 0x07C8) */\n\n#define BIT_SHIFT_LTECOEX_R_DATA 0\n#define BIT_MASK_LTECOEX_R_DATA 0xffffffffL\n#define BIT_LTECOEX_R_DATA(x)                                                  \\\n\t(((x) & BIT_MASK_LTECOEX_R_DATA) << BIT_SHIFT_LTECOEX_R_DATA)\n#define BITS_LTECOEX_R_DATA                                                    \\\n\t(BIT_MASK_LTECOEX_R_DATA << BIT_SHIFT_LTECOEX_R_DATA)\n#define BIT_CLEAR_LTECOEX_R_DATA(x) ((x) & (~BITS_LTECOEX_R_DATA))\n#define BIT_GET_LTECOEX_R_DATA(x)                                              \\\n\t(((x) >> BIT_SHIFT_LTECOEX_R_DATA) & BIT_MASK_LTECOEX_R_DATA)\n#define BIT_SET_LTECOEX_R_DATA(x, v)                                           \\\n\t(BIT_CLEAR_LTECOEX_R_DATA(x) | BIT_LTECOEX_R_DATA(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_IQ_DUMP_2\t\t\t\t(Offset 0x07C8) */\n\n#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2 0\n#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2 0xffffffffL\n#define BIT_R_WMAC_MATCH_REF_MAC_2(x)                                          \\\n\t(((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2)                               \\\n\t << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2)\n#define BITS_R_WMAC_MATCH_REF_MAC_2                                            \\\n\t(BIT_MASK_R_WMAC_MATCH_REF_MAC_2 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2)\n#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2(x)                                    \\\n\t((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2))\n#define BIT_GET_R_WMAC_MATCH_REF_MAC_2(x)                                      \\\n\t(((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) &                           \\\n\t BIT_MASK_R_WMAC_MATCH_REF_MAC_2)\n#define BIT_SET_R_WMAC_MATCH_REF_MAC_2(x, v)                                   \\\n\t(BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2(x) | BIT_R_WMAC_MATCH_REF_MAC_2(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WMAC_FTM_CTL\t\t\t(Offset 0x07CC) */\n\n#define BIT_SHIFT_RX_STOPRXDMA_RXPOINT 16\n#define BIT_MASK_RX_STOPRXDMA_RXPOINT 0xffff\n#define BIT_RX_STOPRXDMA_RXPOINT(x)                                            \\\n\t(((x) & BIT_MASK_RX_STOPRXDMA_RXPOINT)                                 \\\n\t << BIT_SHIFT_RX_STOPRXDMA_RXPOINT)\n#define BITS_RX_STOPRXDMA_RXPOINT                                              \\\n\t(BIT_MASK_RX_STOPRXDMA_RXPOINT << BIT_SHIFT_RX_STOPRXDMA_RXPOINT)\n#define BIT_CLEAR_RX_STOPRXDMA_RXPOINT(x) ((x) & (~BITS_RX_STOPRXDMA_RXPOINT))\n#define BIT_GET_RX_STOPRXDMA_RXPOINT(x)                                        \\\n\t(((x) >> BIT_SHIFT_RX_STOPRXDMA_RXPOINT) &                             \\\n\t BIT_MASK_RX_STOPRXDMA_RXPOINT)\n#define BIT_SET_RX_STOPRXDMA_RXPOINT(x, v)                                     \\\n\t(BIT_CLEAR_RX_STOPRXDMA_RXPOINT(x) | BIT_RX_STOPRXDMA_RXPOINT(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_FTM_CTL\t\t\t(Offset 0x07CC) */\n\n#define BIT_RXFTM_TXACK_SC BIT(6)\n#define BIT_RXFTM_TXACK_BW BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WMAC_FTM_CTL\t\t\t(Offset 0x07CC) */\n\n#define BIT_RXFTM_STOPRXDMAEN BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_FTM_CTL\t\t\t(Offset 0x07CC) */\n\n#define BIT_RXFTM_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_WMAC_FTM_CTL\t\t\t(Offset 0x07CC) */\n\n#define BIT_RXFTMREQ_STOPRXDMAEN BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_FTM_CTL\t\t\t(Offset 0x07CC) */\n\n#define BIT_RXFTMREQ_BYDRV BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_FTM_CTL\t\t\t(Offset 0x07CC) */\n\n#define BIT_RXFTMREQ_EN BIT(1)\n#define BIT_FTM_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_IQ_DUMP_EXT\t\t\t\t(Offset 0x07CF) */\n\n#define BIT_SHIFT_R_LA_MAC_TIMEOUT_UNIT_SEL 10\n#define BIT_MASK_R_LA_MAC_TIMEOUT_UNIT_SEL 0x3\n#define BIT_R_LA_MAC_TIMEOUT_UNIT_SEL(x)                                       \\\n\t(((x) & BIT_MASK_R_LA_MAC_TIMEOUT_UNIT_SEL)                            \\\n\t << BIT_SHIFT_R_LA_MAC_TIMEOUT_UNIT_SEL)\n#define BITS_R_LA_MAC_TIMEOUT_UNIT_SEL                                         \\\n\t(BIT_MASK_R_LA_MAC_TIMEOUT_UNIT_SEL                                    \\\n\t << BIT_SHIFT_R_LA_MAC_TIMEOUT_UNIT_SEL)\n#define BIT_CLEAR_R_LA_MAC_TIMEOUT_UNIT_SEL(x)                                 \\\n\t((x) & (~BITS_R_LA_MAC_TIMEOUT_UNIT_SEL))\n#define BIT_GET_R_LA_MAC_TIMEOUT_UNIT_SEL(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_LA_MAC_TIMEOUT_UNIT_SEL) &                        \\\n\t BIT_MASK_R_LA_MAC_TIMEOUT_UNIT_SEL)\n#define BIT_SET_R_LA_MAC_TIMEOUT_UNIT_SEL(x, v)                                \\\n\t(BIT_CLEAR_R_LA_MAC_TIMEOUT_UNIT_SEL(x) |                              \\\n\t BIT_R_LA_MAC_TIMEOUT_UNIT_SEL(v))\n\n#define BIT_SHIFT_R_LA_MAC_TIMEOUT_VALUE 4\n#define BIT_MASK_R_LA_MAC_TIMEOUT_VALUE 0x3f\n#define BIT_R_LA_MAC_TIMEOUT_VALUE(x)                                          \\\n\t(((x) & BIT_MASK_R_LA_MAC_TIMEOUT_VALUE)                               \\\n\t << BIT_SHIFT_R_LA_MAC_TIMEOUT_VALUE)\n#define BITS_R_LA_MAC_TIMEOUT_VALUE                                            \\\n\t(BIT_MASK_R_LA_MAC_TIMEOUT_VALUE << BIT_SHIFT_R_LA_MAC_TIMEOUT_VALUE)\n#define BIT_CLEAR_R_LA_MAC_TIMEOUT_VALUE(x)                                    \\\n\t((x) & (~BITS_R_LA_MAC_TIMEOUT_VALUE))\n#define BIT_GET_R_LA_MAC_TIMEOUT_VALUE(x)                                      \\\n\t(((x) >> BIT_SHIFT_R_LA_MAC_TIMEOUT_VALUE) &                           \\\n\t BIT_MASK_R_LA_MAC_TIMEOUT_VALUE)\n#define BIT_SET_R_LA_MAC_TIMEOUT_VALUE(x, v)                                   \\\n\t(BIT_CLEAR_R_LA_MAC_TIMEOUT_VALUE(x) | BIT_R_LA_MAC_TIMEOUT_VALUE(v))\n\n#define BIT_R_LEVEL_PULSE_SEL_EXTL BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_IQ_DUMP_EXT\t\t\t\t(Offset 0x07CF) */\n\n#define BIT_SHIFT_R_TIME_UNIT_SEL 0\n#define BIT_MASK_R_TIME_UNIT_SEL 0x7\n#define BIT_R_TIME_UNIT_SEL(x)                                                 \\\n\t(((x) & BIT_MASK_R_TIME_UNIT_SEL) << BIT_SHIFT_R_TIME_UNIT_SEL)\n#define BITS_R_TIME_UNIT_SEL                                                   \\\n\t(BIT_MASK_R_TIME_UNIT_SEL << BIT_SHIFT_R_TIME_UNIT_SEL)\n#define BIT_CLEAR_R_TIME_UNIT_SEL(x) ((x) & (~BITS_R_TIME_UNIT_SEL))\n#define BIT_GET_R_TIME_UNIT_SEL(x)                                             \\\n\t(((x) >> BIT_SHIFT_R_TIME_UNIT_SEL) & BIT_MASK_R_TIME_UNIT_SEL)\n#define BIT_SET_R_TIME_UNIT_SEL(x, v)                                          \\\n\t(BIT_CLEAR_R_TIME_UNIT_SEL(x) | BIT_R_TIME_UNIT_SEL(v))\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_OFDM_CCK_LEN_MASK\t\t\t(Offset 0x07D0) */\n\n#define BIT_MICICV_CLR BIT(86)\n#define BIT_MPDU_RDY_SET BIT(85)\n#define BIT_CLR_SEC_TYPE BIT(84)\n#define BIT_NEWPKT_IN BIT(83)\n#define BIT_FCS_END BIT(82)\n#define BIT_DEL_MESH_TYPE BIT(81)\n#define BIT_MASK_MESH_TYPE BIT(80)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_OPTION_FUNCTION_1\t\t(Offset 0x07D4) */\n\n#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1 24\n#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1 0xff\n#define BIT_R_WMAC_RXFIFO_FULL_TH_1(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1)                              \\\n\t << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1)\n#define BITS_R_WMAC_RXFIFO_FULL_TH_1                                           \\\n\t(BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1)\n#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1(x)                                   \\\n\t((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1))\n#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) &                          \\\n\t BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1)\n#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1(x) | BIT_R_WMAC_RXFIFO_FULL_TH_1(v))\n\n#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1 BIT(23)\n#define BIT_R_WMAC_RXRST_DLY_1 BIT(22)\n#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1 BIT(21)\n#define BIT_R_WMAC_SRCH_TXRPT_UA1_1 BIT(20)\n#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1 BIT(19)\n#define BIT_R_WMAC_NDP_RST_1 BIT(18)\n#define BIT_R_WMAC_POWINT_EN_1 BIT(17)\n#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1 BIT(16)\n#define BIT_R_WMAC_SRCH_TXRPT_MID_1 BIT(15)\n#define BIT_R_WMAC_PFIN_TOEN_1 BIT(14)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FA_FILTER1\t\t\t\t(Offset 0x07D4) */\n\n#define BIT_R_WMAC_FIL_SECERR_V1 BIT(13)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_OPTION_FUNCTION_1\t\t(Offset 0x07D4) */\n\n#define BIT_R_WMAC_FIL_SECERR_1 BIT(13)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FA_FILTER1\t\t\t\t(Offset 0x07D4) */\n\n#define BIT_R_WMAC_FIL_CTLPKTLEN_V1 BIT(12)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_OPTION_FUNCTION_1\t\t(Offset 0x07D4) */\n\n#define BIT_R_WMAC_FIL_CTLPKTLEN_1 BIT(12)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FA_FILTER1\t\t\t\t(Offset 0x07D4) */\n\n#define BIT_R_WMAC_FIL_FCTYPE_V1 BIT(11)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_OPTION_FUNCTION_1\t\t(Offset 0x07D4) */\n\n#define BIT_R_WMAC_FIL_FCTYPE_1 BIT(11)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FA_FILTER1\t\t\t\t(Offset 0x07D4) */\n\n#define BIT_R_WMAC_FIL_FCPROVER_V1 BIT(10)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_OPTION_FUNCTION_1\t\t(Offset 0x07D4) */\n\n#define BIT_R_WMAC_FIL_FCPROVER_1 BIT(10)\n#define BIT_R_WMAC_PHYSTS_SNIF_1 BIT(9)\n#define BIT_R_WMAC_PHYSTS_PLCP_1 BIT(8)\n#define BIT_R_MAC_TCR_VBONF_RD_1 BIT(7)\n#define BIT_R_WMAC_TCR_MPAR_NDP_1 BIT(6)\n#define BIT_R_WMAC_NDP_FILTER_1 BIT(5)\n#define BIT_R_WMAC_RXLEN_SEL_1 BIT(4)\n#define BIT_R_WMAC_RXLEN_SEL1_1 BIT(3)\n#define BIT_R_OFDM_FILTER_1 BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FA_FILTER1\t\t\t\t(Offset 0x07D4) */\n\n#define BIT_R_WMAC_CHK_OFDM_LEN_V1 BIT(1)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_OPTION_FUNCTION_1\t\t(Offset 0x07D4) */\n\n#define BIT_R_WMAC_CHK_OFDM_LEN_1 BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FA_FILTER1\t\t\t\t(Offset 0x07D4) */\n\n#define BIT_R_WMAC_CHK_CCK_LEN_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_OPTION_FUNCTION_1\t\t(Offset 0x07D4) */\n\n#define BIT_R_WMAC_CHK_CCK_LEN_1 BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FA_FILTER2\t\t\t\t(Offset 0x07D8) */\n\n#define BIT_DEL_MESH_TYPE_V1 BIT(17)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_OPTION_FUNCTION_2\t\t(Offset 0x07D8) */\n\n#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2 0\n#define BIT_MASK_R_WMAC_RX_FIL_LEN_2 0xffff\n#define BIT_R_WMAC_RX_FIL_LEN_2(x)                                             \\\n\t(((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2)\n#define BITS_R_WMAC_RX_FIL_LEN_2                                               \\\n\t(BIT_MASK_R_WMAC_RX_FIL_LEN_2 << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2)\n#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2(x) ((x) & (~BITS_R_WMAC_RX_FIL_LEN_2))\n#define BIT_GET_R_WMAC_RX_FIL_LEN_2(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) & BIT_MASK_R_WMAC_RX_FIL_LEN_2)\n#define BIT_SET_R_WMAC_RX_FIL_LEN_2(x, v)                                      \\\n\t(BIT_CLEAR_R_WMAC_RX_FIL_LEN_2(x) | BIT_R_WMAC_RX_FIL_LEN_2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RX_FILTER_FUNCTION\t\t\t(Offset 0x07DA) */\n\n#define BIT_R_WMAC_RXHANG_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RX_FILTER_FUNCTION\t\t\t(Offset 0x07DA) */\n\n#define BIT_RXHANG_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RX_FILTER_FUNCTION\t\t\t(Offset 0x07DA) */\n\n#define BIT_R_WMAC_MHRDDY_LATCH BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RX_FILTER_FUNCTION\t\t\t(Offset 0x07DA) */\n\n#define BIT_R_MHRDDY_CLR BIT(13)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RX_FILTER_FUNCTION\t\t\t(Offset 0x07DA) */\n\n#define BIT_R_WMAC_MHRDDY_CLR BIT(13)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RX_FILTER_FUNCTION\t\t\t(Offset 0x07DA) */\n\n#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1 BIT(12)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RX_FILTER_FUNCTION\t\t\t(Offset 0x07DA) */\n\n#define BIT_R_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RX_FILTER_FUNCTION\t\t\t(Offset 0x07DA) */\n\n#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RX_FILTER_FUNCTION\t\t\t(Offset 0x07DA) */\n\n#define BIT_R_CHK_DELIMIT_LEN BIT(10)\n#define BIT_R_REAPTER_ADDR_MATCH BIT(9)\n#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY BIT(8)\n#define BIT_R_LATCH_MACHRDY BIT(7)\n#define BIT_R_WMAC_RXFIL_REND BIT(6)\n#define BIT_R_WMAC_MPDURDY_CLR BIT(5)\n#define BIT_R_WMAC_CLRRXSEC BIT(4)\n#define BIT_R_WMAC_RXFIL_RDEL BIT(3)\n#define BIT_R_WMAC_RXFIL_FCSE BIT(2)\n#define BIT_R_WMAC_RXFIL_MESH_DEL BIT(1)\n#define BIT_R_WMAC_RXFIL_MASKM BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_NDP_SIG\t\t\t\t(Offset 0x07E0) */\n\n#define BIT_SHIFT_R_WMAC_TXNDP_SIGB 0\n#define BIT_MASK_R_WMAC_TXNDP_SIGB 0x1fffff\n#define BIT_R_WMAC_TXNDP_SIGB(x)                                               \\\n\t(((x) & BIT_MASK_R_WMAC_TXNDP_SIGB) << BIT_SHIFT_R_WMAC_TXNDP_SIGB)\n#define BITS_R_WMAC_TXNDP_SIGB                                                 \\\n\t(BIT_MASK_R_WMAC_TXNDP_SIGB << BIT_SHIFT_R_WMAC_TXNDP_SIGB)\n#define BIT_CLEAR_R_WMAC_TXNDP_SIGB(x) ((x) & (~BITS_R_WMAC_TXNDP_SIGB))\n#define BIT_GET_R_WMAC_TXNDP_SIGB(x)                                           \\\n\t(((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB) & BIT_MASK_R_WMAC_TXNDP_SIGB)\n#define BIT_SET_R_WMAC_TXNDP_SIGB(x, v)                                        \\\n\t(BIT_CLEAR_R_WMAC_TXNDP_SIGB(x) | BIT_R_WMAC_TXNDP_SIGB(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_TXCMD_INFO_FOR_RSP_PKT\t\t(Offset 0x07E4) */\n\n#define BIT_SHIFT_R_MAC_DEBUG (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_MAC_DEBUG 0xffffffffL\n#define BIT_R_MAC_DEBUG(x)                                                     \\\n\t(((x) & BIT_MASK_R_MAC_DEBUG) << BIT_SHIFT_R_MAC_DEBUG)\n#define BITS_R_MAC_DEBUG (BIT_MASK_R_MAC_DEBUG << BIT_SHIFT_R_MAC_DEBUG)\n#define BIT_CLEAR_R_MAC_DEBUG(x) ((x) & (~BITS_R_MAC_DEBUG))\n#define BIT_GET_R_MAC_DEBUG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_R_MAC_DEBUG) & BIT_MASK_R_MAC_DEBUG)\n#define BIT_SET_R_MAC_DEBUG(x, v)                                              \\\n\t(BIT_CLEAR_R_MAC_DEBUG(x) | BIT_R_MAC_DEBUG(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXCMD_INFO_FOR_RSP_PKT\t\t(Offset 0x07E4) */\n\n#define BIT_SHIFT_R_MAC_DBG_SHIFT 8\n#define BIT_MASK_R_MAC_DBG_SHIFT 0x7\n#define BIT_R_MAC_DBG_SHIFT(x)                                                 \\\n\t(((x) & BIT_MASK_R_MAC_DBG_SHIFT) << BIT_SHIFT_R_MAC_DBG_SHIFT)\n#define BITS_R_MAC_DBG_SHIFT                                                   \\\n\t(BIT_MASK_R_MAC_DBG_SHIFT << BIT_SHIFT_R_MAC_DBG_SHIFT)\n#define BIT_CLEAR_R_MAC_DBG_SHIFT(x) ((x) & (~BITS_R_MAC_DBG_SHIFT))\n#define BIT_GET_R_MAC_DBG_SHIFT(x)                                             \\\n\t(((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT) & BIT_MASK_R_MAC_DBG_SHIFT)\n#define BIT_SET_R_MAC_DBG_SHIFT(x, v)                                          \\\n\t(BIT_CLEAR_R_MAC_DBG_SHIFT(x) | BIT_R_MAC_DBG_SHIFT(v))\n\n#define BIT_SHIFT_R_MAC_DBG_SEL 0\n#define BIT_MASK_R_MAC_DBG_SEL 0x3\n#define BIT_R_MAC_DBG_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_R_MAC_DBG_SEL) << BIT_SHIFT_R_MAC_DBG_SEL)\n#define BITS_R_MAC_DBG_SEL (BIT_MASK_R_MAC_DBG_SEL << BIT_SHIFT_R_MAC_DBG_SEL)\n#define BIT_CLEAR_R_MAC_DBG_SEL(x) ((x) & (~BITS_R_MAC_DBG_SEL))\n#define BIT_GET_R_MAC_DBG_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_R_MAC_DBG_SEL) & BIT_MASK_R_MAC_DBG_SEL)\n#define BIT_SET_R_MAC_DBG_SEL(x, v)                                            \\\n\t(BIT_CLEAR_R_MAC_DBG_SEL(x) | BIT_R_MAC_DBG_SEL(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1\t\t(Offset 0x07E8) */\n\n#define BIT_SHIFT_R_MAC_DEBUG_1 0\n#define BIT_MASK_R_MAC_DEBUG_1 0xffffffffL\n#define BIT_R_MAC_DEBUG_1(x)                                                   \\\n\t(((x) & BIT_MASK_R_MAC_DEBUG_1) << BIT_SHIFT_R_MAC_DEBUG_1)\n#define BITS_R_MAC_DEBUG_1 (BIT_MASK_R_MAC_DEBUG_1 << BIT_SHIFT_R_MAC_DEBUG_1)\n#define BIT_CLEAR_R_MAC_DEBUG_1(x) ((x) & (~BITS_R_MAC_DEBUG_1))\n#define BIT_GET_R_MAC_DEBUG_1(x)                                               \\\n\t(((x) >> BIT_SHIFT_R_MAC_DEBUG_1) & BIT_MASK_R_MAC_DEBUG_1)\n#define BIT_SET_R_MAC_DEBUG_1(x, v)                                            \\\n\t(BIT_CLEAR_R_MAC_DEBUG_1(x) | BIT_R_MAC_DEBUG_1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WSEC_OPTION\t\t\t\t(Offset 0x07EC) */\n\n#define BIT_RXDEC_BM_MGNT BIT(22)\n#define BIT_TXENC_BM_MGNT BIT(21)\n#define BIT_RXDEC_UNI_MGNT BIT(20)\n#define BIT_TXENC_UNI_MGNT BIT(19)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SEC_OPT_V2\t\t\t\t(Offset 0x07EC) */\n\n#define BIT_MASK_IV BIT(18)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WSEC_OPTION\t\t\t\t(Offset 0x07EC) */\n\n#define BIT_WMAC_SEC_MASKIV BIT(18)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SEC_OPT_V2\t\t\t\t(Offset 0x07EC) */\n\n#define BIT_EIVL_ENDIAN BIT(17)\n#define BIT_EIVH_ENDIAN BIT(16)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WSEC_OPTION\t\t\t\t(Offset 0x07EC) */\n\n#define BIT_SHIFT_WMAC_SEC_PN_SEL 16\n#define BIT_MASK_WMAC_SEC_PN_SEL 0x3\n#define BIT_WMAC_SEC_PN_SEL(x)                                                 \\\n\t(((x) & BIT_MASK_WMAC_SEC_PN_SEL) << BIT_SHIFT_WMAC_SEC_PN_SEL)\n#define BITS_WMAC_SEC_PN_SEL                                                   \\\n\t(BIT_MASK_WMAC_SEC_PN_SEL << BIT_SHIFT_WMAC_SEC_PN_SEL)\n#define BIT_CLEAR_WMAC_SEC_PN_SEL(x) ((x) & (~BITS_WMAC_SEC_PN_SEL))\n#define BIT_GET_WMAC_SEC_PN_SEL(x)                                             \\\n\t(((x) >> BIT_SHIFT_WMAC_SEC_PN_SEL) & BIT_MASK_WMAC_SEC_PN_SEL)\n#define BIT_SET_WMAC_SEC_PN_SEL(x, v)                                          \\\n\t(BIT_CLEAR_WMAC_SEC_PN_SEL(x) | BIT_WMAC_SEC_PN_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WSEC_OPTION\t\t\t\t(Offset 0x07EC) */\n\n#define BIT_SHIFT_BT_TIME_CNT 0\n#define BIT_MASK_BT_TIME_CNT 0xff\n#define BIT_BT_TIME_CNT(x)                                                     \\\n\t(((x) & BIT_MASK_BT_TIME_CNT) << BIT_SHIFT_BT_TIME_CNT)\n#define BITS_BT_TIME_CNT (BIT_MASK_BT_TIME_CNT << BIT_SHIFT_BT_TIME_CNT)\n#define BIT_CLEAR_BT_TIME_CNT(x) ((x) & (~BITS_BT_TIME_CNT))\n#define BIT_GET_BT_TIME_CNT(x)                                                 \\\n\t(((x) >> BIT_SHIFT_BT_TIME_CNT) & BIT_MASK_BT_TIME_CNT)\n#define BIT_SET_BT_TIME_CNT(x, v)                                              \\\n\t(BIT_CLEAR_BT_TIME_CNT(x) | BIT_BT_TIME_CNT(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RTS_ADDRESS_0\t\t\t(Offset 0x07F0) */\n\n#define BIT_SHIFT_R_WMAC_RTS_ADDR0 0\n#define BIT_MASK_R_WMAC_RTS_ADDR0 0xffffffffffffL\n#define BIT_R_WMAC_RTS_ADDR0(x)                                                \\\n\t(((x) & BIT_MASK_R_WMAC_RTS_ADDR0) << BIT_SHIFT_R_WMAC_RTS_ADDR0)\n#define BITS_R_WMAC_RTS_ADDR0                                                  \\\n\t(BIT_MASK_R_WMAC_RTS_ADDR0 << BIT_SHIFT_R_WMAC_RTS_ADDR0)\n#define BIT_CLEAR_R_WMAC_RTS_ADDR0(x) ((x) & (~BITS_R_WMAC_RTS_ADDR0))\n#define BIT_GET_R_WMAC_RTS_ADDR0(x)                                            \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RTS_ADDR0) & BIT_MASK_R_WMAC_RTS_ADDR0)\n#define BIT_SET_R_WMAC_RTS_ADDR0(x, v)                                         \\\n\t(BIT_CLEAR_R_WMAC_RTS_ADDR0(x) | BIT_R_WMAC_RTS_ADDR0(v))\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RTS_ADDR0\t\t\t\t(Offset 0x07F0) */\n\n#define BIT_SHIFT_RTS_ADDR0 0\n#define BIT_MASK_RTS_ADDR0 0xffffffffffffL\n#define BIT_RTS_ADDR0(x) (((x) & BIT_MASK_RTS_ADDR0) << BIT_SHIFT_RTS_ADDR0)\n#define BITS_RTS_ADDR0 (BIT_MASK_RTS_ADDR0 << BIT_SHIFT_RTS_ADDR0)\n#define BIT_CLEAR_RTS_ADDR0(x) ((x) & (~BITS_RTS_ADDR0))\n#define BIT_GET_RTS_ADDR0(x) (((x) >> BIT_SHIFT_RTS_ADDR0) & BIT_MASK_RTS_ADDR0)\n#define BIT_SET_RTS_ADDR0(x, v) (BIT_CLEAR_RTS_ADDR0(x) | BIT_RTS_ADDR0(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RTS_ADDRESS_1\t\t\t(Offset 0x07F8) */\n\n#define BIT_SHIFT_R_WMAC_RTS_ADDR1 0\n#define BIT_MASK_R_WMAC_RTS_ADDR1 0xffffffffffffL\n#define BIT_R_WMAC_RTS_ADDR1(x)                                                \\\n\t(((x) & BIT_MASK_R_WMAC_RTS_ADDR1) << BIT_SHIFT_R_WMAC_RTS_ADDR1)\n#define BITS_R_WMAC_RTS_ADDR1                                                  \\\n\t(BIT_MASK_R_WMAC_RTS_ADDR1 << BIT_SHIFT_R_WMAC_RTS_ADDR1)\n#define BIT_CLEAR_R_WMAC_RTS_ADDR1(x) ((x) & (~BITS_R_WMAC_RTS_ADDR1))\n#define BIT_GET_R_WMAC_RTS_ADDR1(x)                                            \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RTS_ADDR1) & BIT_MASK_R_WMAC_RTS_ADDR1)\n#define BIT_SET_R_WMAC_RTS_ADDR1(x, v)                                         \\\n\t(BIT_CLEAR_R_WMAC_RTS_ADDR1(x) | BIT_R_WMAC_RTS_ADDR1(v))\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RTS_ADDR1\t\t\t\t(Offset 0x07F8) */\n\n#define BIT_SHIFT_RTS_ADDR1 0\n#define BIT_MASK_RTS_ADDR1 0xffffffffffffL\n#define BIT_RTS_ADDR1(x) (((x) & BIT_MASK_RTS_ADDR1) << BIT_SHIFT_RTS_ADDR1)\n#define BITS_RTS_ADDR1 (BIT_MASK_RTS_ADDR1 << BIT_SHIFT_RTS_ADDR1)\n#define BIT_CLEAR_RTS_ADDR1(x) ((x) & (~BITS_RTS_ADDR1))\n#define BIT_GET_RTS_ADDR1(x) (((x) >> BIT_SHIFT_RTS_ADDR1) & BIT_MASK_RTS_ADDR1)\n#define BIT_SET_RTS_ADDR1(x, v) (BIT_CLEAR_RTS_ADDR1(x) | BIT_RTS_ADDR1(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CFG3\t\t\t\t(Offset 0x1000) */\n\n#define BIT_FEN_BB_GLB_RSTN_V1 BIT(17)\n#define BIT_FEN_BBRSTB_V1 BIT(16)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_CFG3\t\t\t\t(Offset 0x1000) */\n\n#define BIT_PWC_MA33V BIT(15)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CFG3\t\t\t\t(Offset 0x1000) */\n\n#define BIT_PWC_EV25V_1 BIT(14)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SYS_CFG3\t\t\t\t(Offset 0x1000) */\n\n#define BIT_PWC_MA12V BIT(14)\n#define BIT_PWC_MD12V BIT(13)\n#define BIT_PWC_PD12V BIT(12)\n#define BIT_PWC_UD12V BIT(11)\n#define BIT_ISO_MA2MD BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_OCP_L BIT(31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_OCP_L_0 BIT(31)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_POWOCP_L BIT(30)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_CF_L_V2 28\n#define BIT_MASK_CF_L_V2 0x3\n#define BIT_CF_L_V2(x) (((x) & BIT_MASK_CF_L_V2) << BIT_SHIFT_CF_L_V2)\n#define BITS_CF_L_V2 (BIT_MASK_CF_L_V2 << BIT_SHIFT_CF_L_V2)\n#define BIT_CLEAR_CF_L_V2(x) ((x) & (~BITS_CF_L_V2))\n#define BIT_GET_CF_L_V2(x) (((x) >> BIT_SHIFT_CF_L_V2) & BIT_MASK_CF_L_V2)\n#define BIT_SET_CF_L_V2(x, v) (BIT_CLEAR_CF_L_V2(x) | BIT_CF_L_V2(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_CF_L_1_0 28\n#define BIT_MASK_CF_L_1_0 0x3\n#define BIT_CF_L_1_0(x) (((x) & BIT_MASK_CF_L_1_0) << BIT_SHIFT_CF_L_1_0)\n#define BITS_CF_L_1_0 (BIT_MASK_CF_L_1_0 << BIT_SHIFT_CF_L_1_0)\n#define BIT_CLEAR_CF_L_1_0(x) ((x) & (~BITS_CF_L_1_0))\n#define BIT_GET_CF_L_1_0(x) (((x) >> BIT_SHIFT_CF_L_1_0) & BIT_MASK_CF_L_1_0)\n#define BIT_SET_CF_L_1_0(x, v) (BIT_CLEAR_CF_L_1_0(x) | BIT_CF_L_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_CFC_L_V2 26\n#define BIT_MASK_CFC_L_V2 0x3\n#define BIT_CFC_L_V2(x) (((x) & BIT_MASK_CFC_L_V2) << BIT_SHIFT_CFC_L_V2)\n#define BITS_CFC_L_V2 (BIT_MASK_CFC_L_V2 << BIT_SHIFT_CFC_L_V2)\n#define BIT_CLEAR_CFC_L_V2(x) ((x) & (~BITS_CFC_L_V2))\n#define BIT_GET_CFC_L_V2(x) (((x) >> BIT_SHIFT_CFC_L_V2) & BIT_MASK_CFC_L_V2)\n#define BIT_SET_CFC_L_V2(x, v) (BIT_CLEAR_CFC_L_V2(x) | BIT_CFC_L_V2(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_CFC_L_1_0 26\n#define BIT_MASK_CFC_L_1_0 0x3\n#define BIT_CFC_L_1_0(x) (((x) & BIT_MASK_CFC_L_1_0) << BIT_SHIFT_CFC_L_1_0)\n#define BITS_CFC_L_1_0 (BIT_MASK_CFC_L_1_0 << BIT_SHIFT_CFC_L_1_0)\n#define BIT_CLEAR_CFC_L_1_0(x) ((x) & (~BITS_CFC_L_1_0))\n#define BIT_GET_CFC_L_1_0(x) (((x) >> BIT_SHIFT_CFC_L_1_0) & BIT_MASK_CFC_L_1_0)\n#define BIT_SET_CFC_L_1_0(x, v) (BIT_CLEAR_CFC_L_1_0(x) | BIT_CFC_L_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_R3_L_V2 24\n#define BIT_MASK_R3_L_V2 0x3\n#define BIT_R3_L_V2(x) (((x) & BIT_MASK_R3_L_V2) << BIT_SHIFT_R3_L_V2)\n#define BITS_R3_L_V2 (BIT_MASK_R3_L_V2 << BIT_SHIFT_R3_L_V2)\n#define BIT_CLEAR_R3_L_V2(x) ((x) & (~BITS_R3_L_V2))\n#define BIT_GET_R3_L_V2(x) (((x) >> BIT_SHIFT_R3_L_V2) & BIT_MASK_R3_L_V2)\n#define BIT_SET_R3_L_V2(x, v) (BIT_CLEAR_R3_L_V2(x) | BIT_R3_L_V2(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_R3_L_1_0 24\n#define BIT_MASK_R3_L_1_0 0x3\n#define BIT_R3_L_1_0(x) (((x) & BIT_MASK_R3_L_1_0) << BIT_SHIFT_R3_L_1_0)\n#define BITS_R3_L_1_0 (BIT_MASK_R3_L_1_0 << BIT_SHIFT_R3_L_1_0)\n#define BIT_CLEAR_R3_L_1_0(x) ((x) & (~BITS_R3_L_1_0))\n#define BIT_GET_R3_L_1_0(x) (((x) >> BIT_SHIFT_R3_L_1_0) & BIT_MASK_R3_L_1_0)\n#define BIT_SET_R3_L_1_0(x, v) (BIT_CLEAR_R3_L_1_0(x) | BIT_R3_L_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_R2_L 22\n#define BIT_MASK_R2_L 0x3\n#define BIT_R2_L(x) (((x) & BIT_MASK_R2_L) << BIT_SHIFT_R2_L)\n#define BITS_R2_L (BIT_MASK_R2_L << BIT_SHIFT_R2_L)\n#define BIT_CLEAR_R2_L(x) ((x) & (~BITS_R2_L))\n#define BIT_GET_R2_L(x) (((x) >> BIT_SHIFT_R2_L) & BIT_MASK_R2_L)\n#define BIT_SET_R2_L(x, v) (BIT_CLEAR_R2_L(x) | BIT_R2_L(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_R2_L_1_0 22\n#define BIT_MASK_R2_L_1_0 0x3\n#define BIT_R2_L_1_0(x) (((x) & BIT_MASK_R2_L_1_0) << BIT_SHIFT_R2_L_1_0)\n#define BITS_R2_L_1_0 (BIT_MASK_R2_L_1_0 << BIT_SHIFT_R2_L_1_0)\n#define BIT_CLEAR_R2_L_1_0(x) ((x) & (~BITS_R2_L_1_0))\n#define BIT_GET_R2_L_1_0(x) (((x) >> BIT_SHIFT_R2_L_1_0) & BIT_MASK_R2_L_1_0)\n#define BIT_SET_R2_L_1_0(x, v) (BIT_CLEAR_R2_L_1_0(x) | BIT_R2_L_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_R1_L 20\n#define BIT_MASK_R1_L 0x3\n#define BIT_R1_L(x) (((x) & BIT_MASK_R1_L) << BIT_SHIFT_R1_L)\n#define BITS_R1_L (BIT_MASK_R1_L << BIT_SHIFT_R1_L)\n#define BIT_CLEAR_R1_L(x) ((x) & (~BITS_R1_L))\n#define BIT_GET_R1_L(x) (((x) >> BIT_SHIFT_R1_L) & BIT_MASK_R1_L)\n#define BIT_SET_R1_L(x, v) (BIT_CLEAR_R1_L(x) | BIT_R1_L(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_R1_L_1_0 20\n#define BIT_MASK_R1_L_1_0 0x3\n#define BIT_R1_L_1_0(x) (((x) & BIT_MASK_R1_L_1_0) << BIT_SHIFT_R1_L_1_0)\n#define BITS_R1_L_1_0 (BIT_MASK_R1_L_1_0 << BIT_SHIFT_R1_L_1_0)\n#define BIT_CLEAR_R1_L_1_0(x) ((x) & (~BITS_R1_L_1_0))\n#define BIT_GET_R1_L_1_0(x) (((x) >> BIT_SHIFT_R1_L_1_0) & BIT_MASK_R1_L_1_0)\n#define BIT_SET_R1_L_1_0(x, v) (BIT_CLEAR_R1_L_1_0(x) | BIT_R1_L_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_C3_L 18\n#define BIT_MASK_C3_L 0x3\n#define BIT_C3_L(x) (((x) & BIT_MASK_C3_L) << BIT_SHIFT_C3_L)\n#define BITS_C3_L (BIT_MASK_C3_L << BIT_SHIFT_C3_L)\n#define BIT_CLEAR_C3_L(x) ((x) & (~BITS_C3_L))\n#define BIT_GET_C3_L(x) (((x) >> BIT_SHIFT_C3_L) & BIT_MASK_C3_L)\n#define BIT_SET_C3_L(x, v) (BIT_CLEAR_C3_L(x) | BIT_C3_L(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_C3_L_1_0 18\n#define BIT_MASK_C3_L_1_0 0x3\n#define BIT_C3_L_1_0(x) (((x) & BIT_MASK_C3_L_1_0) << BIT_SHIFT_C3_L_1_0)\n#define BITS_C3_L_1_0 (BIT_MASK_C3_L_1_0 << BIT_SHIFT_C3_L_1_0)\n#define BIT_CLEAR_C3_L_1_0(x) ((x) & (~BITS_C3_L_1_0))\n#define BIT_GET_C3_L_1_0(x) (((x) >> BIT_SHIFT_C3_L_1_0) & BIT_MASK_C3_L_1_0)\n#define BIT_SET_C3_L_1_0(x, v) (BIT_CLEAR_C3_L_1_0(x) | BIT_C3_L_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_C2_L 16\n#define BIT_MASK_C2_L 0x3\n#define BIT_C2_L(x) (((x) & BIT_MASK_C2_L) << BIT_SHIFT_C2_L)\n#define BITS_C2_L (BIT_MASK_C2_L << BIT_SHIFT_C2_L)\n#define BIT_CLEAR_C2_L(x) ((x) & (~BITS_C2_L))\n#define BIT_GET_C2_L(x) (((x) >> BIT_SHIFT_C2_L) & BIT_MASK_C2_L)\n#define BIT_SET_C2_L(x, v) (BIT_CLEAR_C2_L(x) | BIT_C2_L(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_C2_L_1_0 16\n#define BIT_MASK_C2_L_1_0 0x3\n#define BIT_C2_L_1_0(x) (((x) & BIT_MASK_C2_L_1_0) << BIT_SHIFT_C2_L_1_0)\n#define BITS_C2_L_1_0 (BIT_MASK_C2_L_1_0 << BIT_SHIFT_C2_L_1_0)\n#define BIT_CLEAR_C2_L_1_0(x) ((x) & (~BITS_C2_L_1_0))\n#define BIT_GET_C2_L_1_0(x) (((x) >> BIT_SHIFT_C2_L_1_0) & BIT_MASK_C2_L_1_0)\n#define BIT_SET_C2_L_1_0(x, v) (BIT_CLEAR_C2_L_1_0(x) | BIT_C2_L_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_C1_L_V2 14\n#define BIT_MASK_C1_L_V2 0x3\n#define BIT_C1_L_V2(x) (((x) & BIT_MASK_C1_L_V2) << BIT_SHIFT_C1_L_V2)\n#define BITS_C1_L_V2 (BIT_MASK_C1_L_V2 << BIT_SHIFT_C1_L_V2)\n#define BIT_CLEAR_C1_L_V2(x) ((x) & (~BITS_C1_L_V2))\n#define BIT_GET_C1_L_V2(x) (((x) >> BIT_SHIFT_C1_L_V2) & BIT_MASK_C1_L_V2)\n#define BIT_SET_C1_L_V2(x, v) (BIT_CLEAR_C1_L_V2(x) | BIT_C1_L_V2(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_C1_L_1_0 14\n#define BIT_MASK_C1_L_1_0 0x3\n#define BIT_C1_L_1_0(x) (((x) & BIT_MASK_C1_L_1_0) << BIT_SHIFT_C1_L_1_0)\n#define BITS_C1_L_1_0 (BIT_MASK_C1_L_1_0 << BIT_SHIFT_C1_L_1_0)\n#define BIT_CLEAR_C1_L_1_0(x) ((x) & (~BITS_C1_L_1_0))\n#define BIT_GET_C1_L_1_0(x) (((x) >> BIT_SHIFT_C1_L_1_0) & BIT_MASK_C1_L_1_0)\n#define BIT_SET_C1_L_1_0(x, v) (BIT_CLEAR_C1_L_1_0(x) | BIT_C1_L_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_REG_TYPE_L_V2 BIT(13)\n#define BIT_REG_PWM_L BIT(12)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_V15ADJ_L 9\n#define BIT_MASK_V15ADJ_L 0x7\n#define BIT_V15ADJ_L(x) (((x) & BIT_MASK_V15ADJ_L) << BIT_SHIFT_V15ADJ_L)\n#define BITS_V15ADJ_L (BIT_MASK_V15ADJ_L << BIT_SHIFT_V15ADJ_L)\n#define BIT_CLEAR_V15ADJ_L(x) ((x) & (~BITS_V15ADJ_L))\n#define BIT_GET_V15ADJ_L(x) (((x) >> BIT_SHIFT_V15ADJ_L) & BIT_MASK_V15ADJ_L)\n#define BIT_SET_V15ADJ_L(x, v) (BIT_CLEAR_V15ADJ_L(x) | BIT_V15ADJ_L(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_V15ADJ_L_2_0 9\n#define BIT_MASK_V15ADJ_L_2_0 0x7\n#define BIT_V15ADJ_L_2_0(x)                                                    \\\n\t(((x) & BIT_MASK_V15ADJ_L_2_0) << BIT_SHIFT_V15ADJ_L_2_0)\n#define BITS_V15ADJ_L_2_0 (BIT_MASK_V15ADJ_L_2_0 << BIT_SHIFT_V15ADJ_L_2_0)\n#define BIT_CLEAR_V15ADJ_L_2_0(x) ((x) & (~BITS_V15ADJ_L_2_0))\n#define BIT_GET_V15ADJ_L_2_0(x)                                                \\\n\t(((x) >> BIT_SHIFT_V15ADJ_L_2_0) & BIT_MASK_V15ADJ_L_2_0)\n#define BIT_SET_V15ADJ_L_2_0(x, v)                                             \\\n\t(BIT_CLEAR_V15ADJ_L_2_0(x) | BIT_V15ADJ_L_2_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_IN_L 6\n#define BIT_MASK_IN_L 0x7\n#define BIT_IN_L(x) (((x) & BIT_MASK_IN_L) << BIT_SHIFT_IN_L)\n#define BITS_IN_L (BIT_MASK_IN_L << BIT_SHIFT_IN_L)\n#define BIT_CLEAR_IN_L(x) ((x) & (~BITS_IN_L))\n#define BIT_GET_IN_L(x) (((x) >> BIT_SHIFT_IN_L) & BIT_MASK_IN_L)\n#define BIT_SET_IN_L(x, v) (BIT_CLEAR_IN_L(x) | BIT_IN_L(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_IN_L_2_0 6\n#define BIT_MASK_IN_L_2_0 0x7\n#define BIT_IN_L_2_0(x) (((x) & BIT_MASK_IN_L_2_0) << BIT_SHIFT_IN_L_2_0)\n#define BITS_IN_L_2_0 (BIT_MASK_IN_L_2_0 << BIT_SHIFT_IN_L_2_0)\n#define BIT_CLEAR_IN_L_2_0(x) ((x) & (~BITS_IN_L_2_0))\n#define BIT_GET_IN_L_2_0(x) (((x) >> BIT_SHIFT_IN_L_2_0) & BIT_MASK_IN_L_2_0)\n#define BIT_SET_IN_L_2_0(x, v) (BIT_CLEAR_IN_L_2_0(x) | BIT_IN_L_2_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_STD_L 4\n#define BIT_MASK_STD_L 0x3\n#define BIT_STD_L(x) (((x) & BIT_MASK_STD_L) << BIT_SHIFT_STD_L)\n#define BITS_STD_L (BIT_MASK_STD_L << BIT_SHIFT_STD_L)\n#define BIT_CLEAR_STD_L(x) ((x) & (~BITS_STD_L))\n#define BIT_GET_STD_L(x) (((x) >> BIT_SHIFT_STD_L) & BIT_MASK_STD_L)\n#define BIT_SET_STD_L(x, v) (BIT_CLEAR_STD_L(x) | BIT_STD_L(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_STD_L_1_0 4\n#define BIT_MASK_STD_L_1_0 0x3\n#define BIT_STD_L_1_0(x) (((x) & BIT_MASK_STD_L_1_0) << BIT_SHIFT_STD_L_1_0)\n#define BITS_STD_L_1_0 (BIT_MASK_STD_L_1_0 << BIT_SHIFT_STD_L_1_0)\n#define BIT_CLEAR_STD_L_1_0(x) ((x) & (~BITS_STD_L_1_0))\n#define BIT_GET_STD_L_1_0(x) (((x) >> BIT_SHIFT_STD_L_1_0) & BIT_MASK_STD_L_1_0)\n#define BIT_SET_STD_L_1_0(x, v) (BIT_CLEAR_STD_L_1_0(x) | BIT_STD_L_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_VOL_L 0\n#define BIT_MASK_VOL_L 0xf\n#define BIT_VOL_L(x) (((x) & BIT_MASK_VOL_L) << BIT_SHIFT_VOL_L)\n#define BITS_VOL_L (BIT_MASK_VOL_L << BIT_SHIFT_VOL_L)\n#define BIT_CLEAR_VOL_L(x) ((x) & (~BITS_VOL_L))\n#define BIT_GET_VOL_L(x) (((x) >> BIT_SHIFT_VOL_L) & BIT_MASK_VOL_L)\n#define BIT_SET_VOL_L(x, v) (BIT_CLEAR_VOL_L(x) | BIT_VOL_L(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_0\t\t\t(Offset 0x1010) */\n\n#define BIT_SHIFT_VOL_L_3_0 0\n#define BIT_MASK_VOL_L_3_0 0xf\n#define BIT_VOL_L_3_0(x) (((x) & BIT_MASK_VOL_L_3_0) << BIT_SHIFT_VOL_L_3_0)\n#define BITS_VOL_L_3_0 (BIT_MASK_VOL_L_3_0 << BIT_SHIFT_VOL_L_3_0)\n#define BIT_CLEAR_VOL_L_3_0(x) ((x) & (~BITS_VOL_L_3_0))\n#define BIT_GET_VOL_L_3_0(x) (((x) >> BIT_SHIFT_VOL_L_3_0) & BIT_MASK_VOL_L_3_0)\n#define BIT_SET_VOL_L_3_0(x, v) (BIT_CLEAR_VOL_L_3_0(x) | BIT_VOL_L_3_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_SHIFT_OCP_L_PFM 29\n#define BIT_MASK_OCP_L_PFM 0x7\n#define BIT_OCP_L_PFM(x) (((x) & BIT_MASK_OCP_L_PFM) << BIT_SHIFT_OCP_L_PFM)\n#define BITS_OCP_L_PFM (BIT_MASK_OCP_L_PFM << BIT_SHIFT_OCP_L_PFM)\n#define BIT_CLEAR_OCP_L_PFM(x) ((x) & (~BITS_OCP_L_PFM))\n#define BIT_GET_OCP_L_PFM(x) (((x) >> BIT_SHIFT_OCP_L_PFM) & BIT_MASK_OCP_L_PFM)\n#define BIT_SET_OCP_L_PFM(x, v) (BIT_CLEAR_OCP_L_PFM(x) | BIT_OCP_L_PFM(v))\n\n#define BIT_SHIFT_CFC_L_PFM 27\n#define BIT_MASK_CFC_L_PFM 0x3\n#define BIT_CFC_L_PFM(x) (((x) & BIT_MASK_CFC_L_PFM) << BIT_SHIFT_CFC_L_PFM)\n#define BITS_CFC_L_PFM (BIT_MASK_CFC_L_PFM << BIT_SHIFT_CFC_L_PFM)\n#define BIT_CLEAR_CFC_L_PFM(x) ((x) & (~BITS_CFC_L_PFM))\n#define BIT_GET_CFC_L_PFM(x) (((x) >> BIT_SHIFT_CFC_L_PFM) & BIT_MASK_CFC_L_PFM)\n#define BIT_SET_CFC_L_PFM(x, v) (BIT_CLEAR_CFC_L_PFM(x) | BIT_CFC_L_PFM(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_SHIFT_REG_FREQ_L_V1 20\n#define BIT_MASK_REG_FREQ_L_V1 0x7\n#define BIT_REG_FREQ_L_V1(x)                                                   \\\n\t(((x) & BIT_MASK_REG_FREQ_L_V1) << BIT_SHIFT_REG_FREQ_L_V1)\n#define BITS_REG_FREQ_L_V1 (BIT_MASK_REG_FREQ_L_V1 << BIT_SHIFT_REG_FREQ_L_V1)\n#define BIT_CLEAR_REG_FREQ_L_V1(x) ((x) & (~BITS_REG_FREQ_L_V1))\n#define BIT_GET_REG_FREQ_L_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_REG_FREQ_L_V1) & BIT_MASK_REG_FREQ_L_V1)\n#define BIT_SET_REG_FREQ_L_V1(x, v)                                            \\\n\t(BIT_CLEAR_REG_FREQ_L_V1(x) | BIT_REG_FREQ_L_V1(v))\n\n#define BIT_EN_DUTY BIT(19)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_SHIFT_REG_MODE_V2 17\n#define BIT_MASK_REG_MODE_V2 0x3\n#define BIT_REG_MODE_V2(x)                                                     \\\n\t(((x) & BIT_MASK_REG_MODE_V2) << BIT_SHIFT_REG_MODE_V2)\n#define BITS_REG_MODE_V2 (BIT_MASK_REG_MODE_V2 << BIT_SHIFT_REG_MODE_V2)\n#define BIT_CLEAR_REG_MODE_V2(x) ((x) & (~BITS_REG_MODE_V2))\n#define BIT_GET_REG_MODE_V2(x)                                                 \\\n\t(((x) >> BIT_SHIFT_REG_MODE_V2) & BIT_MASK_REG_MODE_V2)\n#define BIT_SET_REG_MODE_V2(x, v)                                              \\\n\t(BIT_CLEAR_REG_MODE_V2(x) | BIT_REG_MODE_V2(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_SHIFT_REG_MOS_HALF 17\n#define BIT_MASK_REG_MOS_HALF 0x3\n#define BIT_REG_MOS_HALF(x)                                                    \\\n\t(((x) & BIT_MASK_REG_MOS_HALF) << BIT_SHIFT_REG_MOS_HALF)\n#define BITS_REG_MOS_HALF (BIT_MASK_REG_MOS_HALF << BIT_SHIFT_REG_MOS_HALF)\n#define BIT_CLEAR_REG_MOS_HALF(x) ((x) & (~BITS_REG_MOS_HALF))\n#define BIT_GET_REG_MOS_HALF(x)                                                \\\n\t(((x) >> BIT_SHIFT_REG_MOS_HALF) & BIT_MASK_REG_MOS_HALF)\n#define BIT_SET_REG_MOS_HALF(x, v)                                             \\\n\t(BIT_CLEAR_REG_MOS_HALF(x) | BIT_REG_MOS_HALF(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_EN_SP BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_REG_AUTO_L_V2 BIT(15)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_REG_AUTO_L_V1 BIT(15)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_REG_LDOF_L_V2 BIT(14)\n#define BIT_REG_OCPS_L_V2 BIT(13)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_VO15_V1P05_H BIT(12)\n#define BIT_ARENB_L_V2 BIT(11)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_ARENB_L_V1 BIT(11)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_SHIFT_TBOX_L1_V2 9\n#define BIT_MASK_TBOX_L1_V2 0x3\n#define BIT_TBOX_L1_V2(x) (((x) & BIT_MASK_TBOX_L1_V2) << BIT_SHIFT_TBOX_L1_V2)\n#define BITS_TBOX_L1_V2 (BIT_MASK_TBOX_L1_V2 << BIT_SHIFT_TBOX_L1_V2)\n#define BIT_CLEAR_TBOX_L1_V2(x) ((x) & (~BITS_TBOX_L1_V2))\n#define BIT_GET_TBOX_L1_V2(x)                                                  \\\n\t(((x) >> BIT_SHIFT_TBOX_L1_V2) & BIT_MASK_TBOX_L1_V2)\n#define BIT_SET_TBOX_L1_V2(x, v) (BIT_CLEAR_TBOX_L1_V2(x) | BIT_TBOX_L1_V2(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_SHIFT_TBOX_L1_1_0 9\n#define BIT_MASK_TBOX_L1_1_0 0x3\n#define BIT_TBOX_L1_1_0(x)                                                     \\\n\t(((x) & BIT_MASK_TBOX_L1_1_0) << BIT_SHIFT_TBOX_L1_1_0)\n#define BITS_TBOX_L1_1_0 (BIT_MASK_TBOX_L1_1_0 << BIT_SHIFT_TBOX_L1_1_0)\n#define BIT_CLEAR_TBOX_L1_1_0(x) ((x) & (~BITS_TBOX_L1_1_0))\n#define BIT_GET_TBOX_L1_1_0(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TBOX_L1_1_0) & BIT_MASK_TBOX_L1_1_0)\n#define BIT_SET_TBOX_L1_1_0(x, v)                                              \\\n\t(BIT_CLEAR_TBOX_L1_1_0(x) | BIT_TBOX_L1_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_SHIFT_REG_DELAY_L 7\n#define BIT_MASK_REG_DELAY_L 0x3\n#define BIT_REG_DELAY_L(x)                                                     \\\n\t(((x) & BIT_MASK_REG_DELAY_L) << BIT_SHIFT_REG_DELAY_L)\n#define BITS_REG_DELAY_L (BIT_MASK_REG_DELAY_L << BIT_SHIFT_REG_DELAY_L)\n#define BIT_CLEAR_REG_DELAY_L(x) ((x) & (~BITS_REG_DELAY_L))\n#define BIT_GET_REG_DELAY_L(x)                                                 \\\n\t(((x) >> BIT_SHIFT_REG_DELAY_L) & BIT_MASK_REG_DELAY_L)\n#define BIT_SET_REG_DELAY_L(x, v)                                              \\\n\t(BIT_CLEAR_REG_DELAY_L(x) | BIT_REG_DELAY_L(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_SHIFT_REG_DELAY_L_1_0 7\n#define BIT_MASK_REG_DELAY_L_1_0 0x3\n#define BIT_REG_DELAY_L_1_0(x)                                                 \\\n\t(((x) & BIT_MASK_REG_DELAY_L_1_0) << BIT_SHIFT_REG_DELAY_L_1_0)\n#define BITS_REG_DELAY_L_1_0                                                   \\\n\t(BIT_MASK_REG_DELAY_L_1_0 << BIT_SHIFT_REG_DELAY_L_1_0)\n#define BIT_CLEAR_REG_DELAY_L_1_0(x) ((x) & (~BITS_REG_DELAY_L_1_0))\n#define BIT_GET_REG_DELAY_L_1_0(x)                                             \\\n\t(((x) >> BIT_SHIFT_REG_DELAY_L_1_0) & BIT_MASK_REG_DELAY_L_1_0)\n#define BIT_SET_REG_DELAY_L_1_0(x, v)                                          \\\n\t(BIT_CLEAR_REG_DELAY_L_1_0(x) | BIT_REG_DELAY_L_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_REG_CLAMP_D_L BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_REG_BYPASS_L_V2 BIT(5)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_REG_BYPASS_L_V1 BIT(5)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_REG_AUTOZCD_L BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_POW_ZCD_L_V2 BIT(3)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_POW_ZCD_L_V1 BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_REG_HALF_L BIT(2)\n\n#define BIT_SHIFT_OCP_L_V2 0\n#define BIT_MASK_OCP_L_V2 0x3\n#define BIT_OCP_L_V2(x) (((x) & BIT_MASK_OCP_L_V2) << BIT_SHIFT_OCP_L_V2)\n#define BITS_OCP_L_V2 (BIT_MASK_OCP_L_V2 << BIT_SHIFT_OCP_L_V2)\n#define BIT_CLEAR_OCP_L_V2(x) ((x) & (~BITS_OCP_L_V2))\n#define BIT_GET_OCP_L_V2(x) (((x) >> BIT_SHIFT_OCP_L_V2) & BIT_MASK_OCP_L_V2)\n#define BIT_SET_OCP_L_V2(x, v) (BIT_CLEAR_OCP_L_V2(x) | BIT_OCP_L_V2(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPARSW_MAC_1\t\t\t(Offset 0x1014) */\n\n#define BIT_SHIFT_OCP_L_2_1 0\n#define BIT_MASK_OCP_L_2_1 0x3\n#define BIT_OCP_L_2_1(x) (((x) & BIT_MASK_OCP_L_2_1) << BIT_SHIFT_OCP_L_2_1)\n#define BITS_OCP_L_2_1 (BIT_MASK_OCP_L_2_1 << BIT_SHIFT_OCP_L_2_1)\n#define BIT_CLEAR_OCP_L_2_1(x) ((x) & (~BITS_OCP_L_2_1))\n#define BIT_GET_OCP_L_2_1(x) (((x) >> BIT_SHIFT_OCP_L_2_1) & BIT_MASK_OCP_L_2_1)\n#define BIT_SET_OCP_L_2_1(x, v) (BIT_CLEAR_OCP_L_2_1(x) | BIT_OCP_L_2_1(v))\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_SHIFT_LPF_C2_1_0 30\n#define BIT_MASK_LPF_C2_1_0 0x3\n#define BIT_LPF_C2_1_0(x) (((x) & BIT_MASK_LPF_C2_1_0) << BIT_SHIFT_LPF_C2_1_0)\n#define BITS_LPF_C2_1_0 (BIT_MASK_LPF_C2_1_0 << BIT_SHIFT_LPF_C2_1_0)\n#define BIT_CLEAR_LPF_C2_1_0(x) ((x) & (~BITS_LPF_C2_1_0))\n#define BIT_GET_LPF_C2_1_0(x)                                                  \\\n\t(((x) >> BIT_SHIFT_LPF_C2_1_0) & BIT_MASK_LPF_C2_1_0)\n#define BIT_SET_LPF_C2_1_0(x, v) (BIT_CLEAR_LPF_C2_1_0(x) | BIT_LPF_C2_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_SHIFT_REG_LPF_R3 29\n#define BIT_MASK_REG_LPF_R3 0x7\n#define BIT_REG_LPF_R3(x) (((x) & BIT_MASK_REG_LPF_R3) << BIT_SHIFT_REG_LPF_R3)\n#define BITS_REG_LPF_R3 (BIT_MASK_REG_LPF_R3 << BIT_SHIFT_REG_LPF_R3)\n#define BIT_CLEAR_REG_LPF_R3(x) ((x) & (~BITS_REG_LPF_R3))\n#define BIT_GET_REG_LPF_R3(x)                                                  \\\n\t(((x) >> BIT_SHIFT_REG_LPF_R3) & BIT_MASK_REG_LPF_R3)\n#define BIT_SET_REG_LPF_R3(x, v) (BIT_CLEAR_REG_LPF_R3(x) | BIT_REG_LPF_R3(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_EN_XTAL_AAC_TRIG BIT(28)\n#define BIT_EN_XTAL_AAC BIT(27)\n#define BIT_EN_XTAL_AAC_DIGI BIT(26)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_SHIFT_REG_LPF_R2 24\n#define BIT_MASK_REG_LPF_R2 0x1f\n#define BIT_REG_LPF_R2(x) (((x) & BIT_MASK_REG_LPF_R2) << BIT_SHIFT_REG_LPF_R2)\n#define BITS_REG_LPF_R2 (BIT_MASK_REG_LPF_R2 << BIT_SHIFT_REG_LPF_R2)\n#define BIT_CLEAR_REG_LPF_R2(x) ((x) & (~BITS_REG_LPF_R2))\n#define BIT_GET_REG_LPF_R2(x)                                                  \\\n\t(((x) >> BIT_SHIFT_REG_LPF_R2) & BIT_MASK_REG_LPF_R2)\n#define BIT_SET_REG_LPF_R2(x, v) (BIT_CLEAR_REG_LPF_R2(x) | BIT_REG_LPF_R2(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_SHIFT_LPF_C1_5_0 24\n#define BIT_MASK_LPF_C1_5_0 0x3f\n#define BIT_LPF_C1_5_0(x) (((x) & BIT_MASK_LPF_C1_5_0) << BIT_SHIFT_LPF_C1_5_0)\n#define BITS_LPF_C1_5_0 (BIT_MASK_LPF_C1_5_0 << BIT_SHIFT_LPF_C1_5_0)\n#define BIT_CLEAR_LPF_C1_5_0(x) ((x) & (~BITS_LPF_C1_5_0))\n#define BIT_GET_LPF_C1_5_0(x)                                                  \\\n\t(((x) >> BIT_SHIFT_LPF_C1_5_0) & BIT_MASK_LPF_C1_5_0)\n#define BIT_SET_LPF_C1_5_0(x, v) (BIT_CLEAR_LPF_C1_5_0(x) | BIT_LPF_C1_5_0(v))\n\n#define BIT_LPF_TIEL BIT(23)\n#define BIT_LPF_TIEH BIT(22)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_SHIFT_REG_LPF_C3 21\n#define BIT_MASK_REG_LPF_C3 0x7\n#define BIT_REG_LPF_C3(x) (((x) & BIT_MASK_REG_LPF_C3) << BIT_SHIFT_REG_LPF_C3)\n#define BITS_REG_LPF_C3 (BIT_MASK_REG_LPF_C3 << BIT_SHIFT_REG_LPF_C3)\n#define BIT_CLEAR_REG_LPF_C3(x) ((x) & (~BITS_REG_LPF_C3))\n#define BIT_GET_REG_LPF_C3(x)                                                  \\\n\t(((x) >> BIT_SHIFT_REG_LPF_C3) & BIT_MASK_REG_LPF_C3)\n#define BIT_SET_REG_LPF_C3(x, v) (BIT_CLEAR_REG_LPF_C3(x) | BIT_REG_LPF_C3(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_SHIFT_LOCKDET_VREF_L_1_0 20\n#define BIT_MASK_LOCKDET_VREF_L_1_0 0x3\n#define BIT_LOCKDET_VREF_L_1_0(x)                                              \\\n\t(((x) & BIT_MASK_LOCKDET_VREF_L_1_0) << BIT_SHIFT_LOCKDET_VREF_L_1_0)\n#define BITS_LOCKDET_VREF_L_1_0                                                \\\n\t(BIT_MASK_LOCKDET_VREF_L_1_0 << BIT_SHIFT_LOCKDET_VREF_L_1_0)\n#define BIT_CLEAR_LOCKDET_VREF_L_1_0(x) ((x) & (~BITS_LOCKDET_VREF_L_1_0))\n#define BIT_GET_LOCKDET_VREF_L_1_0(x)                                          \\\n\t(((x) >> BIT_SHIFT_LOCKDET_VREF_L_1_0) & BIT_MASK_LOCKDET_VREF_L_1_0)\n#define BIT_SET_LOCKDET_VREF_L_1_0(x, v)                                       \\\n\t(BIT_CLEAR_LOCKDET_VREF_L_1_0(x) | BIT_LOCKDET_VREF_L_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_SHIFT_REG_LPF_C2 18\n#define BIT_MASK_REG_LPF_C2 0x7\n#define BIT_REG_LPF_C2(x) (((x) & BIT_MASK_REG_LPF_C2) << BIT_SHIFT_REG_LPF_C2)\n#define BITS_REG_LPF_C2 (BIT_MASK_REG_LPF_C2 << BIT_SHIFT_REG_LPF_C2)\n#define BIT_CLEAR_REG_LPF_C2(x) ((x) & (~BITS_REG_LPF_C2))\n#define BIT_GET_REG_LPF_C2(x)                                                  \\\n\t(((x) >> BIT_SHIFT_REG_LPF_C2) & BIT_MASK_REG_LPF_C2)\n#define BIT_SET_REG_LPF_C2(x, v) (BIT_CLEAR_REG_LPF_C2(x) | BIT_REG_LPF_C2(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_SHIFT_LOCKDET_VREF_H_1_0 18\n#define BIT_MASK_LOCKDET_VREF_H_1_0 0x3\n#define BIT_LOCKDET_VREF_H_1_0(x)                                              \\\n\t(((x) & BIT_MASK_LOCKDET_VREF_H_1_0) << BIT_SHIFT_LOCKDET_VREF_H_1_0)\n#define BITS_LOCKDET_VREF_H_1_0                                                \\\n\t(BIT_MASK_LOCKDET_VREF_H_1_0 << BIT_SHIFT_LOCKDET_VREF_H_1_0)\n#define BIT_CLEAR_LOCKDET_VREF_H_1_0(x) ((x) & (~BITS_LOCKDET_VREF_H_1_0))\n#define BIT_GET_LOCKDET_VREF_H_1_0(x)                                          \\\n\t(((x) >> BIT_SHIFT_LOCKDET_VREF_H_1_0) & BIT_MASK_LOCKDET_VREF_H_1_0)\n#define BIT_SET_LOCKDET_VREF_H_1_0(x, v)                                       \\\n\t(BIT_CLEAR_LOCKDET_VREF_H_1_0(x) | BIT_LOCKDET_VREF_H_1_0(v))\n\n#define BIT_SHIFT_LDO_SEL_1_0 16\n#define BIT_MASK_LDO_SEL_1_0 0x3\n#define BIT_LDO_SEL_1_0(x)                                                     \\\n\t(((x) & BIT_MASK_LDO_SEL_1_0) << BIT_SHIFT_LDO_SEL_1_0)\n#define BITS_LDO_SEL_1_0 (BIT_MASK_LDO_SEL_1_0 << BIT_SHIFT_LDO_SEL_1_0)\n#define BIT_CLEAR_LDO_SEL_1_0(x) ((x) & (~BITS_LDO_SEL_1_0))\n#define BIT_GET_LDO_SEL_1_0(x)                                                 \\\n\t(((x) >> BIT_SHIFT_LDO_SEL_1_0) & BIT_MASK_LDO_SEL_1_0)\n#define BIT_SET_LDO_SEL_1_0(x, v)                                              \\\n\t(BIT_CLEAR_LDO_SEL_1_0(x) | BIT_LDO_SEL_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_SHIFT_REG_LPF_C1 15\n#define BIT_MASK_REG_LPF_C1 0x7\n#define BIT_REG_LPF_C1(x) (((x) & BIT_MASK_REG_LPF_C1) << BIT_SHIFT_REG_LPF_C1)\n#define BITS_REG_LPF_C1 (BIT_MASK_REG_LPF_C1 << BIT_SHIFT_REG_LPF_C1)\n#define BIT_CLEAR_REG_LPF_C1(x) ((x) & (~BITS_REG_LPF_C1))\n#define BIT_GET_REG_LPF_C1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_REG_LPF_C1) & BIT_MASK_REG_LPF_C1)\n#define BIT_SET_REG_LPF_C1(x, v) (BIT_CLEAR_REG_LPF_C1(x) | BIT_REG_LPF_C1(v))\n\n#define BIT_SHIFT_REG_LDO_SEL_V1 13\n#define BIT_MASK_REG_LDO_SEL_V1 0x3\n#define BIT_REG_LDO_SEL_V1(x)                                                  \\\n\t(((x) & BIT_MASK_REG_LDO_SEL_V1) << BIT_SHIFT_REG_LDO_SEL_V1)\n#define BITS_REG_LDO_SEL_V1                                                    \\\n\t(BIT_MASK_REG_LDO_SEL_V1 << BIT_SHIFT_REG_LDO_SEL_V1)\n#define BIT_CLEAR_REG_LDO_SEL_V1(x) ((x) & (~BITS_REG_LDO_SEL_V1))\n#define BIT_GET_REG_LDO_SEL_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_REG_LDO_SEL_V1) & BIT_MASK_REG_LDO_SEL_V1)\n#define BIT_SET_REG_LDO_SEL_V1(x, v)                                           \\\n\t(BIT_CLEAR_REG_LDO_SEL_V1(x) | BIT_REG_LDO_SEL_V1(v))\n\n#define BIT_REG_CP_ICPX2 BIT(12)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_SHIFT_IOFFSET_5_0 10\n#define BIT_MASK_IOFFSET_5_0 0x3f\n#define BIT_IOFFSET_5_0(x)                                                     \\\n\t(((x) & BIT_MASK_IOFFSET_5_0) << BIT_SHIFT_IOFFSET_5_0)\n#define BITS_IOFFSET_5_0 (BIT_MASK_IOFFSET_5_0 << BIT_SHIFT_IOFFSET_5_0)\n#define BIT_CLEAR_IOFFSET_5_0(x) ((x) & (~BITS_IOFFSET_5_0))\n#define BIT_GET_IOFFSET_5_0(x)                                                 \\\n\t(((x) >> BIT_SHIFT_IOFFSET_5_0) & BIT_MASK_IOFFSET_5_0)\n#define BIT_SET_IOFFSET_5_0(x, v)                                              \\\n\t(BIT_CLEAR_IOFFSET_5_0(x) | BIT_IOFFSET_5_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_SHIFT_REG_CP_ICP_SEL_FAST 9\n#define BIT_MASK_REG_CP_ICP_SEL_FAST 0x7\n#define BIT_REG_CP_ICP_SEL_FAST(x)                                             \\\n\t(((x) & BIT_MASK_REG_CP_ICP_SEL_FAST) << BIT_SHIFT_REG_CP_ICP_SEL_FAST)\n#define BITS_REG_CP_ICP_SEL_FAST                                               \\\n\t(BIT_MASK_REG_CP_ICP_SEL_FAST << BIT_SHIFT_REG_CP_ICP_SEL_FAST)\n#define BIT_CLEAR_REG_CP_ICP_SEL_FAST(x) ((x) & (~BITS_REG_CP_ICP_SEL_FAST))\n#define BIT_GET_REG_CP_ICP_SEL_FAST(x)                                         \\\n\t(((x) >> BIT_SHIFT_REG_CP_ICP_SEL_FAST) & BIT_MASK_REG_CP_ICP_SEL_FAST)\n#define BIT_SET_REG_CP_ICP_SEL_FAST(x, v)                                      \\\n\t(BIT_CLEAR_REG_CP_ICP_SEL_FAST(x) | BIT_REG_CP_ICP_SEL_FAST(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_CP_ICPX2 BIT(9)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_GM_STEP BIT(7)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_SHIFT_REG_CP_ICP_SEL 6\n#define BIT_MASK_REG_CP_ICP_SEL 0x7\n#define BIT_REG_CP_ICP_SEL(x)                                                  \\\n\t(((x) & BIT_MASK_REG_CP_ICP_SEL) << BIT_SHIFT_REG_CP_ICP_SEL)\n#define BITS_REG_CP_ICP_SEL                                                    \\\n\t(BIT_MASK_REG_CP_ICP_SEL << BIT_SHIFT_REG_CP_ICP_SEL)\n#define BIT_CLEAR_REG_CP_ICP_SEL(x) ((x) & (~BITS_REG_CP_ICP_SEL))\n#define BIT_GET_REG_CP_ICP_SEL(x)                                              \\\n\t(((x) >> BIT_SHIFT_REG_CP_ICP_SEL) & BIT_MASK_REG_CP_ICP_SEL)\n#define BIT_SET_REG_CP_ICP_SEL(x, v)                                           \\\n\t(BIT_CLEAR_REG_CP_ICP_SEL(x) | BIT_REG_CP_ICP_SEL(v))\n\n#define BIT_SHIFT_REG_IB_PI 4\n#define BIT_MASK_REG_IB_PI 0x3\n#define BIT_REG_IB_PI(x) (((x) & BIT_MASK_REG_IB_PI) << BIT_SHIFT_REG_IB_PI)\n#define BITS_REG_IB_PI (BIT_MASK_REG_IB_PI << BIT_SHIFT_REG_IB_PI)\n#define BIT_CLEAR_REG_IB_PI(x) ((x) & (~BITS_REG_IB_PI))\n#define BIT_GET_REG_IB_PI(x) (((x) >> BIT_SHIFT_REG_IB_PI) & BIT_MASK_REG_IB_PI)\n#define BIT_SET_REG_IB_PI(x, v) (BIT_CLEAR_REG_IB_PI(x) | BIT_REG_IB_PI(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_SHIFT_CP_ICP_SEL_4_0 4\n#define BIT_MASK_CP_ICP_SEL_4_0 0x1f\n#define BIT_CP_ICP_SEL_4_0(x)                                                  \\\n\t(((x) & BIT_MASK_CP_ICP_SEL_4_0) << BIT_SHIFT_CP_ICP_SEL_4_0)\n#define BITS_CP_ICP_SEL_4_0                                                    \\\n\t(BIT_MASK_CP_ICP_SEL_4_0 << BIT_SHIFT_CP_ICP_SEL_4_0)\n#define BIT_CLEAR_CP_ICP_SEL_4_0(x) ((x) & (~BITS_CP_ICP_SEL_4_0))\n#define BIT_GET_CP_ICP_SEL_4_0(x)                                              \\\n\t(((x) >> BIT_SHIFT_CP_ICP_SEL_4_0) & BIT_MASK_CP_ICP_SEL_4_0)\n#define BIT_SET_CP_ICP_SEL_4_0(x, v)                                           \\\n\t(BIT_CLEAR_CP_ICP_SEL_4_0(x) | BIT_CP_ICP_SEL_4_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_LDO2PWRCUT BIT(3)\n#define BIT_VPULSE_LDO BIT(2)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_SHIFT_IB_PI_1_0 2\n#define BIT_MASK_IB_PI_1_0 0x3\n#define BIT_IB_PI_1_0(x) (((x) & BIT_MASK_IB_PI_1_0) << BIT_SHIFT_IB_PI_1_0)\n#define BITS_IB_PI_1_0 (BIT_MASK_IB_PI_1_0 << BIT_SHIFT_IB_PI_1_0)\n#define BIT_CLEAR_IB_PI_1_0(x) ((x) & (~BITS_IB_PI_1_0))\n#define BIT_GET_IB_PI_1_0(x) (((x) >> BIT_SHIFT_IB_PI_1_0) & BIT_MASK_IB_PI_1_0)\n#define BIT_SET_IB_PI_1_0(x, v) (BIT_CLEAR_IB_PI_1_0(x) | BIT_IB_PI_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_0\t\t\t(Offset 0x1018) */\n\n#define BIT_OFFSET_PLUS BIT(1)\n\n#define BIT_SHIFT_LDO_VSEL 0\n#define BIT_MASK_LDO_VSEL 0x3\n#define BIT_LDO_VSEL(x) (((x) & BIT_MASK_LDO_VSEL) << BIT_SHIFT_LDO_VSEL)\n#define BITS_LDO_VSEL (BIT_MASK_LDO_VSEL << BIT_SHIFT_LDO_VSEL)\n#define BIT_CLEAR_LDO_VSEL(x) ((x) & (~BITS_LDO_VSEL))\n#define BIT_GET_LDO_VSEL(x) (((x) >> BIT_SHIFT_LDO_VSEL) & BIT_MASK_LDO_VSEL)\n#define BIT_SET_LDO_VSEL(x, v) (BIT_CLEAR_LDO_VSEL(x) | BIT_LDO_VSEL(v))\n\n#define BIT_RESET_N BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_SHIFT_REG_CK_MON_SEL 29\n#define BIT_MASK_REG_CK_MON_SEL 0x7\n#define BIT_REG_CK_MON_SEL(x)                                                  \\\n\t(((x) & BIT_MASK_REG_CK_MON_SEL) << BIT_SHIFT_REG_CK_MON_SEL)\n#define BITS_REG_CK_MON_SEL                                                    \\\n\t(BIT_MASK_REG_CK_MON_SEL << BIT_SHIFT_REG_CK_MON_SEL)\n#define BIT_CLEAR_REG_CK_MON_SEL(x) ((x) & (~BITS_REG_CK_MON_SEL))\n#define BIT_GET_REG_CK_MON_SEL(x)                                              \\\n\t(((x) >> BIT_SHIFT_REG_CK_MON_SEL) & BIT_MASK_REG_CK_MON_SEL)\n#define BIT_SET_REG_CK_MON_SEL(x, v)                                           \\\n\t(BIT_CLEAR_REG_CK_MON_SEL(x) | BIT_REG_CK_MON_SEL(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_SHIFT_CKX_USB_IB_SEL 29\n#define BIT_MASK_CKX_USB_IB_SEL 0x7\n#define BIT_CKX_USB_IB_SEL(x)                                                  \\\n\t(((x) & BIT_MASK_CKX_USB_IB_SEL) << BIT_SHIFT_CKX_USB_IB_SEL)\n#define BITS_CKX_USB_IB_SEL                                                    \\\n\t(BIT_MASK_CKX_USB_IB_SEL << BIT_SHIFT_CKX_USB_IB_SEL)\n#define BIT_CLEAR_CKX_USB_IB_SEL(x) ((x) & (~BITS_CKX_USB_IB_SEL))\n#define BIT_GET_CKX_USB_IB_SEL(x)                                              \\\n\t(((x) >> BIT_SHIFT_CKX_USB_IB_SEL) & BIT_MASK_CKX_USB_IB_SEL)\n#define BIT_SET_CKX_USB_IB_SEL(x, v)                                           \\\n\t(BIT_CLEAR_CKX_USB_IB_SEL(x) | BIT_CKX_USB_IB_SEL(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_REG_CK_MON_EN BIT(28)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_PFD_DN_GATED BIT(28)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_REG_XTAL_FREQ_SEL BIT(27)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_PFD_UP_GATED BIT(27)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_REG_XTAL_EDGE_SEL BIT(26)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_PFD_RESET_GATED BIT(26)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_REG_VCO_KVCO BIT(25)\n#define BIT_REG_SDM_EDGE_SEL BIT(24)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_SHIFT_PFD_OUT_DRV_1_0 24\n#define BIT_MASK_PFD_OUT_DRV_1_0 0x3\n#define BIT_PFD_OUT_DRV_1_0(x)                                                 \\\n\t(((x) & BIT_MASK_PFD_OUT_DRV_1_0) << BIT_SHIFT_PFD_OUT_DRV_1_0)\n#define BITS_PFD_OUT_DRV_1_0                                                   \\\n\t(BIT_MASK_PFD_OUT_DRV_1_0 << BIT_SHIFT_PFD_OUT_DRV_1_0)\n#define BIT_CLEAR_PFD_OUT_DRV_1_0(x) ((x) & (~BITS_PFD_OUT_DRV_1_0))\n#define BIT_GET_PFD_OUT_DRV_1_0(x)                                             \\\n\t(((x) >> BIT_SHIFT_PFD_OUT_DRV_1_0) & BIT_MASK_PFD_OUT_DRV_1_0)\n#define BIT_SET_PFD_OUT_DRV_1_0(x, v)                                          \\\n\t(BIT_CLEAR_PFD_OUT_DRV_1_0(x) | BIT_PFD_OUT_DRV_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_REG_SDM_CK_SEL BIT(23)\n#define BIT_REG_SDM_CK_GATED BIT(22)\n#define BIT_REG_PFD_RESET_GATED BIT(21)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_SHIFT_LPF_TIEMID_2_0 20\n#define BIT_MASK_LPF_TIEMID_2_0 0x7\n#define BIT_LPF_TIEMID_2_0(x)                                                  \\\n\t(((x) & BIT_MASK_LPF_TIEMID_2_0) << BIT_SHIFT_LPF_TIEMID_2_0)\n#define BITS_LPF_TIEMID_2_0                                                    \\\n\t(BIT_MASK_LPF_TIEMID_2_0 << BIT_SHIFT_LPF_TIEMID_2_0)\n#define BIT_CLEAR_LPF_TIEMID_2_0(x) ((x) & (~BITS_LPF_TIEMID_2_0))\n#define BIT_GET_LPF_TIEMID_2_0(x)                                              \\\n\t(((x) >> BIT_SHIFT_LPF_TIEMID_2_0) & BIT_MASK_LPF_TIEMID_2_0)\n#define BIT_SET_LPF_TIEMID_2_0(x, v)                                           \\\n\t(BIT_CLEAR_LPF_TIEMID_2_0(x) | BIT_LPF_TIEMID_2_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_SHIFT_REG_LPF_R3_FAST 16\n#define BIT_MASK_REG_LPF_R3_FAST 0x1f\n#define BIT_REG_LPF_R3_FAST(x)                                                 \\\n\t(((x) & BIT_MASK_REG_LPF_R3_FAST) << BIT_SHIFT_REG_LPF_R3_FAST)\n#define BITS_REG_LPF_R3_FAST                                                   \\\n\t(BIT_MASK_REG_LPF_R3_FAST << BIT_SHIFT_REG_LPF_R3_FAST)\n#define BIT_CLEAR_REG_LPF_R3_FAST(x) ((x) & (~BITS_REG_LPF_R3_FAST))\n#define BIT_GET_REG_LPF_R3_FAST(x)                                             \\\n\t(((x) >> BIT_SHIFT_REG_LPF_R3_FAST) & BIT_MASK_REG_LPF_R3_FAST)\n#define BIT_SET_REG_LPF_R3_FAST(x, v)                                          \\\n\t(BIT_CLEAR_REG_LPF_R3_FAST(x) | BIT_REG_LPF_R3_FAST(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_SHIFT_LPF_R3_4_0 15\n#define BIT_MASK_LPF_R3_4_0 0x1f\n#define BIT_LPF_R3_4_0(x) (((x) & BIT_MASK_LPF_R3_4_0) << BIT_SHIFT_LPF_R3_4_0)\n#define BITS_LPF_R3_4_0 (BIT_MASK_LPF_R3_4_0 << BIT_SHIFT_LPF_R3_4_0)\n#define BIT_CLEAR_LPF_R3_4_0(x) ((x) & (~BITS_LPF_R3_4_0))\n#define BIT_GET_LPF_R3_4_0(x)                                                  \\\n\t(((x) >> BIT_SHIFT_LPF_R3_4_0) & BIT_MASK_LPF_R3_4_0)\n#define BIT_SET_LPF_R3_4_0(x, v) (BIT_CLEAR_LPF_R3_4_0(x) | BIT_LPF_R3_4_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_SHIFT_REG_LPF_R2_FAST 11\n#define BIT_MASK_REG_LPF_R2_FAST 0x1f\n#define BIT_REG_LPF_R2_FAST(x)                                                 \\\n\t(((x) & BIT_MASK_REG_LPF_R2_FAST) << BIT_SHIFT_REG_LPF_R2_FAST)\n#define BITS_REG_LPF_R2_FAST                                                   \\\n\t(BIT_MASK_REG_LPF_R2_FAST << BIT_SHIFT_REG_LPF_R2_FAST)\n#define BIT_CLEAR_REG_LPF_R2_FAST(x) ((x) & (~BITS_REG_LPF_R2_FAST))\n#define BIT_GET_REG_LPF_R2_FAST(x)                                             \\\n\t(((x) >> BIT_SHIFT_REG_LPF_R2_FAST) & BIT_MASK_REG_LPF_R2_FAST)\n#define BIT_SET_REG_LPF_R2_FAST(x, v)                                          \\\n\t(BIT_CLEAR_REG_LPF_R2_FAST(x) | BIT_REG_LPF_R2_FAST(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_SHIFT_LPF_R2_4_0 10\n#define BIT_MASK_LPF_R2_4_0 0x1f\n#define BIT_LPF_R2_4_0(x) (((x) & BIT_MASK_LPF_R2_4_0) << BIT_SHIFT_LPF_R2_4_0)\n#define BITS_LPF_R2_4_0 (BIT_MASK_LPF_R2_4_0 << BIT_SHIFT_LPF_R2_4_0)\n#define BIT_CLEAR_LPF_R2_4_0(x) ((x) & (~BITS_LPF_R2_4_0))\n#define BIT_GET_LPF_R2_4_0(x)                                                  \\\n\t(((x) >> BIT_SHIFT_LPF_R2_4_0) & BIT_MASK_LPF_R2_4_0)\n#define BIT_SET_LPF_R2_4_0(x, v) (BIT_CLEAR_LPF_R2_4_0(x) | BIT_LPF_R2_4_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_SHIFT_REG_LPF_C3_FAST 8\n#define BIT_MASK_REG_LPF_C3_FAST 0x7\n#define BIT_REG_LPF_C3_FAST(x)                                                 \\\n\t(((x) & BIT_MASK_REG_LPF_C3_FAST) << BIT_SHIFT_REG_LPF_C3_FAST)\n#define BITS_REG_LPF_C3_FAST                                                   \\\n\t(BIT_MASK_REG_LPF_C3_FAST << BIT_SHIFT_REG_LPF_C3_FAST)\n#define BIT_CLEAR_REG_LPF_C3_FAST(x) ((x) & (~BITS_REG_LPF_C3_FAST))\n#define BIT_GET_REG_LPF_C3_FAST(x)                                             \\\n\t(((x) >> BIT_SHIFT_REG_LPF_C3_FAST) & BIT_MASK_REG_LPF_C3_FAST)\n#define BIT_SET_REG_LPF_C3_FAST(x, v)                                          \\\n\t(BIT_CLEAR_REG_LPF_C3_FAST(x) | BIT_REG_LPF_C3_FAST(v))\n\n#define BIT_SHIFT_REG_LPF_C2_FAST 5\n#define BIT_MASK_REG_LPF_C2_FAST 0x7\n#define BIT_REG_LPF_C2_FAST(x)                                                 \\\n\t(((x) & BIT_MASK_REG_LPF_C2_FAST) << BIT_SHIFT_REG_LPF_C2_FAST)\n#define BITS_REG_LPF_C2_FAST                                                   \\\n\t(BIT_MASK_REG_LPF_C2_FAST << BIT_SHIFT_REG_LPF_C2_FAST)\n#define BIT_CLEAR_REG_LPF_C2_FAST(x) ((x) & (~BITS_REG_LPF_C2_FAST))\n#define BIT_GET_REG_LPF_C2_FAST(x)                                             \\\n\t(((x) >> BIT_SHIFT_REG_LPF_C2_FAST) & BIT_MASK_REG_LPF_C2_FAST)\n#define BIT_SET_REG_LPF_C2_FAST(x, v)                                          \\\n\t(BIT_CLEAR_REG_LPF_C2_FAST(x) | BIT_REG_LPF_C2_FAST(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_SHIFT_LPF_C3_5_0 4\n#define BIT_MASK_LPF_C3_5_0 0x3f\n#define BIT_LPF_C3_5_0(x) (((x) & BIT_MASK_LPF_C3_5_0) << BIT_SHIFT_LPF_C3_5_0)\n#define BITS_LPF_C3_5_0 (BIT_MASK_LPF_C3_5_0 << BIT_SHIFT_LPF_C3_5_0)\n#define BIT_CLEAR_LPF_C3_5_0(x) ((x) & (~BITS_LPF_C3_5_0))\n#define BIT_GET_LPF_C3_5_0(x)                                                  \\\n\t(((x) >> BIT_SHIFT_LPF_C3_5_0) & BIT_MASK_LPF_C3_5_0)\n#define BIT_SET_LPF_C3_5_0(x, v) (BIT_CLEAR_LPF_C3_5_0(x) | BIT_LPF_C3_5_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_SHIFT_REG_LPF_C1_FAST 2\n#define BIT_MASK_REG_LPF_C1_FAST 0x7\n#define BIT_REG_LPF_C1_FAST(x)                                                 \\\n\t(((x) & BIT_MASK_REG_LPF_C1_FAST) << BIT_SHIFT_REG_LPF_C1_FAST)\n#define BITS_REG_LPF_C1_FAST                                                   \\\n\t(BIT_MASK_REG_LPF_C1_FAST << BIT_SHIFT_REG_LPF_C1_FAST)\n#define BIT_CLEAR_REG_LPF_C1_FAST(x) ((x) & (~BITS_REG_LPF_C1_FAST))\n#define BIT_GET_REG_LPF_C1_FAST(x)                                             \\\n\t(((x) >> BIT_SHIFT_REG_LPF_C1_FAST) & BIT_MASK_REG_LPF_C1_FAST)\n#define BIT_SET_REG_LPF_C1_FAST(x, v)                                          \\\n\t(BIT_CLEAR_REG_LPF_C1_FAST(x) | BIT_REG_LPF_C1_FAST(v))\n\n#define BIT_SHIFT_REG_LPF_R3_V1 0\n#define BIT_MASK_REG_LPF_R3_V1 0x3\n#define BIT_REG_LPF_R3_V1(x)                                                   \\\n\t(((x) & BIT_MASK_REG_LPF_R3_V1) << BIT_SHIFT_REG_LPF_R3_V1)\n#define BITS_REG_LPF_R3_V1 (BIT_MASK_REG_LPF_R3_V1 << BIT_SHIFT_REG_LPF_R3_V1)\n#define BIT_CLEAR_REG_LPF_R3_V1(x) ((x) & (~BITS_REG_LPF_R3_V1))\n#define BIT_GET_REG_LPF_R3_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_REG_LPF_R3_V1) & BIT_MASK_REG_LPF_R3_V1)\n#define BIT_SET_REG_LPF_R3_V1(x, v)                                            \\\n\t(BIT_CLEAR_REG_LPF_R3_V1(x) | BIT_REG_LPF_R3_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_1\t\t\t(Offset 0x101C) */\n\n#define BIT_SHIFT_LPF_C2_5_2 0\n#define BIT_MASK_LPF_C2_5_2 0xf\n#define BIT_LPF_C2_5_2(x) (((x) & BIT_MASK_LPF_C2_5_2) << BIT_SHIFT_LPF_C2_5_2)\n#define BITS_LPF_C2_5_2 (BIT_MASK_LPF_C2_5_2 << BIT_SHIFT_LPF_C2_5_2)\n#define BIT_CLEAR_LPF_C2_5_2(x) ((x) & (~BITS_LPF_C2_5_2))\n#define BIT_GET_LPF_C2_5_2(x)                                                  \\\n\t(((x) >> BIT_SHIFT_LPF_C2_5_2) & BIT_MASK_LPF_C2_5_2)\n#define BIT_SET_LPF_C2_5_2(x, v) (BIT_CLEAR_LPF_C2_5_2(x) | BIT_LPF_C2_5_2(v))\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_CK_PHASE_SEL BIT(31)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_SHIFT_AGPIO_DRV_V1 30\n#define BIT_MASK_AGPIO_DRV_V1 0x3\n#define BIT_AGPIO_DRV_V1(x)                                                    \\\n\t(((x) & BIT_MASK_AGPIO_DRV_V1) << BIT_SHIFT_AGPIO_DRV_V1)\n#define BITS_AGPIO_DRV_V1 (BIT_MASK_AGPIO_DRV_V1 << BIT_SHIFT_AGPIO_DRV_V1)\n#define BIT_CLEAR_AGPIO_DRV_V1(x) ((x) & (~BITS_AGPIO_DRV_V1))\n#define BIT_GET_AGPIO_DRV_V1(x)                                                \\\n\t(((x) >> BIT_SHIFT_AGPIO_DRV_V1) & BIT_MASK_AGPIO_DRV_V1)\n#define BIT_SET_AGPIO_DRV_V1(x, v)                                             \\\n\t(BIT_CLEAR_AGPIO_DRV_V1(x) | BIT_AGPIO_DRV_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_CK960M_EN BIT(30)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_AGPIO_GPO_V1 BIT(29)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_CK640M_EN BIT(29)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_AGPIO_GPE_V1 BIT(28)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_CK240M_EN BIT(28)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_SEL_CLK BIT(27)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_SHIFT_CK_MON_SEL_2_0 25\n#define BIT_MASK_CK_MON_SEL_2_0 0x7\n#define BIT_CK_MON_SEL_2_0(x)                                                  \\\n\t(((x) & BIT_MASK_CK_MON_SEL_2_0) << BIT_SHIFT_CK_MON_SEL_2_0)\n#define BITS_CK_MON_SEL_2_0                                                    \\\n\t(BIT_MASK_CK_MON_SEL_2_0 << BIT_SHIFT_CK_MON_SEL_2_0)\n#define BIT_CLEAR_CK_MON_SEL_2_0(x) ((x) & (~BITS_CK_MON_SEL_2_0))\n#define BIT_GET_CK_MON_SEL_2_0(x)                                              \\\n\t(((x) >> BIT_SHIFT_CK_MON_SEL_2_0) & BIT_MASK_CK_MON_SEL_2_0)\n#define BIT_SET_CK_MON_SEL_2_0(x, v)                                           \\\n\t(BIT_CLEAR_CK_MON_SEL_2_0(x) | BIT_CK_MON_SEL_2_0(v))\n\n#define BIT_CK_MON_EN_V1 BIT(24)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_SHIFT_LS_XTAL_SEL 23\n#define BIT_MASK_LS_XTAL_SEL 0xf\n#define BIT_LS_XTAL_SEL(x)                                                     \\\n\t(((x) & BIT_MASK_LS_XTAL_SEL) << BIT_SHIFT_LS_XTAL_SEL)\n#define BITS_LS_XTAL_SEL (BIT_MASK_LS_XTAL_SEL << BIT_SHIFT_LS_XTAL_SEL)\n#define BIT_CLEAR_LS_XTAL_SEL(x) ((x) & (~BITS_LS_XTAL_SEL))\n#define BIT_GET_LS_XTAL_SEL(x)                                                 \\\n\t(((x) >> BIT_SHIFT_LS_XTAL_SEL) & BIT_MASK_LS_XTAL_SEL)\n#define BIT_SET_LS_XTAL_SEL(x, v)                                              \\\n\t(BIT_CLEAR_LS_XTAL_SEL(x) | BIT_LS_XTAL_SEL(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_XTAL_SOURCE_SEL BIT(23)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_LS_SDM_ORDER_V1 BIT(22)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_XTAL_FREQ_SEL BIT(22)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_LS_DELAY_PH BIT(21)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_XTAL_EDGE_SEL BIT(21)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_DIVIDER_SEL BIT(20)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_XTAL_BUF_SEL BIT(20)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_SHIFT_PCODE 15\n#define BIT_MASK_PCODE 0x1f\n#define BIT_PCODE(x) (((x) & BIT_MASK_PCODE) << BIT_SHIFT_PCODE)\n#define BITS_PCODE (BIT_MASK_PCODE << BIT_SHIFT_PCODE)\n#define BIT_CLEAR_PCODE(x) ((x) & (~BITS_PCODE))\n#define BIT_GET_PCODE(x) (((x) >> BIT_SHIFT_PCODE) & BIT_MASK_PCODE)\n#define BIT_SET_PCODE(x, v) (BIT_CLEAR_PCODE(x) | BIT_PCODE(v))\n\n#define BIT_SHIFT_NCODE 7\n#define BIT_MASK_NCODE 0xff\n#define BIT_NCODE(x) (((x) & BIT_MASK_NCODE) << BIT_SHIFT_NCODE)\n#define BITS_NCODE (BIT_MASK_NCODE << BIT_SHIFT_NCODE)\n#define BIT_CLEAR_NCODE(x) ((x) & (~BITS_NCODE))\n#define BIT_GET_NCODE(x) (((x) >> BIT_SHIFT_NCODE) & BIT_MASK_NCODE)\n#define BIT_SET_NCODE(x, v) (BIT_CLEAR_NCODE(x) | BIT_NCODE(v))\n\n#define BIT_REG_BEACON BIT(6)\n#define BIT_REG_MBIASE BIT(5)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_SHIFT_VCO_CV_7_0 4\n#define BIT_MASK_VCO_CV_7_0 0xff\n#define BIT_VCO_CV_7_0(x) (((x) & BIT_MASK_VCO_CV_7_0) << BIT_SHIFT_VCO_CV_7_0)\n#define BITS_VCO_CV_7_0 (BIT_MASK_VCO_CV_7_0 << BIT_SHIFT_VCO_CV_7_0)\n#define BIT_CLEAR_VCO_CV_7_0(x) ((x) & (~BITS_VCO_CV_7_0))\n#define BIT_GET_VCO_CV_7_0(x)                                                  \\\n\t(((x) >> BIT_SHIFT_VCO_CV_7_0) & BIT_MASK_VCO_CV_7_0)\n#define BIT_SET_VCO_CV_7_0(x, v) (BIT_CLEAR_VCO_CV_7_0(x) | BIT_VCO_CV_7_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_SHIFT_REG_FAST_SEL 3\n#define BIT_MASK_REG_FAST_SEL 0x3\n#define BIT_REG_FAST_SEL(x)                                                    \\\n\t(((x) & BIT_MASK_REG_FAST_SEL) << BIT_SHIFT_REG_FAST_SEL)\n#define BITS_REG_FAST_SEL (BIT_MASK_REG_FAST_SEL << BIT_SHIFT_REG_FAST_SEL)\n#define BIT_CLEAR_REG_FAST_SEL(x) ((x) & (~BITS_REG_FAST_SEL))\n#define BIT_GET_REG_FAST_SEL(x)                                                \\\n\t(((x) >> BIT_SHIFT_REG_FAST_SEL) & BIT_MASK_REG_FAST_SEL)\n#define BIT_SET_REG_FAST_SEL(x, v)                                             \\\n\t(BIT_CLEAR_REG_FAST_SEL(x) | BIT_REG_FAST_SEL(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_VCO_KVCO BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_REG_CK960M_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_SDM_EDGE_SEL BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_REG_CK320M_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_SDM_CK_SEL BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_REG_CK_5M_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_MAC_2\t\t\t(Offset 0x1020) */\n\n#define BIT_SDM_CK_GATED BIT(0)\n\n/* 2 REG_ANAPAR_MAC_3\t\t\t(Offset 0x1024) */\n\n#define BIT_SHIFT_LCK_WAIT_CYCLE_2_0 28\n#define BIT_MASK_LCK_WAIT_CYCLE_2_0 0x7\n#define BIT_LCK_WAIT_CYCLE_2_0(x)                                              \\\n\t(((x) & BIT_MASK_LCK_WAIT_CYCLE_2_0) << BIT_SHIFT_LCK_WAIT_CYCLE_2_0)\n#define BITS_LCK_WAIT_CYCLE_2_0                                                \\\n\t(BIT_MASK_LCK_WAIT_CYCLE_2_0 << BIT_SHIFT_LCK_WAIT_CYCLE_2_0)\n#define BIT_CLEAR_LCK_WAIT_CYCLE_2_0(x) ((x) & (~BITS_LCK_WAIT_CYCLE_2_0))\n#define BIT_GET_LCK_WAIT_CYCLE_2_0(x)                                          \\\n\t(((x) >> BIT_SHIFT_LCK_WAIT_CYCLE_2_0) & BIT_MASK_LCK_WAIT_CYCLE_2_0)\n#define BIT_SET_LCK_WAIT_CYCLE_2_0(x, v)                                       \\\n\t(BIT_CLEAR_LCK_WAIT_CYCLE_2_0(x) | BIT_LCK_WAIT_CYCLE_2_0(v))\n\n#define BIT_SHIFT_LCK_VCO_DIVISOR_1_0 26\n#define BIT_MASK_LCK_VCO_DIVISOR_1_0 0x3\n#define BIT_LCK_VCO_DIVISOR_1_0(x)                                             \\\n\t(((x) & BIT_MASK_LCK_VCO_DIVISOR_1_0) << BIT_SHIFT_LCK_VCO_DIVISOR_1_0)\n#define BITS_LCK_VCO_DIVISOR_1_0                                               \\\n\t(BIT_MASK_LCK_VCO_DIVISOR_1_0 << BIT_SHIFT_LCK_VCO_DIVISOR_1_0)\n#define BIT_CLEAR_LCK_VCO_DIVISOR_1_0(x) ((x) & (~BITS_LCK_VCO_DIVISOR_1_0))\n#define BIT_GET_LCK_VCO_DIVISOR_1_0(x)                                         \\\n\t(((x) >> BIT_SHIFT_LCK_VCO_DIVISOR_1_0) & BIT_MASK_LCK_VCO_DIVISOR_1_0)\n#define BIT_SET_LCK_VCO_DIVISOR_1_0(x, v)                                      \\\n\t(BIT_CLEAR_LCK_VCO_DIVISOR_1_0(x) | BIT_LCK_VCO_DIVISOR_1_0(v))\n\n#define BIT_SHIFT_LCK_SEARCH_MODE_1_0 24\n#define BIT_MASK_LCK_SEARCH_MODE_1_0 0x3\n#define BIT_LCK_SEARCH_MODE_1_0(x)                                             \\\n\t(((x) & BIT_MASK_LCK_SEARCH_MODE_1_0) << BIT_SHIFT_LCK_SEARCH_MODE_1_0)\n#define BITS_LCK_SEARCH_MODE_1_0                                               \\\n\t(BIT_MASK_LCK_SEARCH_MODE_1_0 << BIT_SHIFT_LCK_SEARCH_MODE_1_0)\n#define BIT_CLEAR_LCK_SEARCH_MODE_1_0(x) ((x) & (~BITS_LCK_SEARCH_MODE_1_0))\n#define BIT_GET_LCK_SEARCH_MODE_1_0(x)                                         \\\n\t(((x) >> BIT_SHIFT_LCK_SEARCH_MODE_1_0) & BIT_MASK_LCK_SEARCH_MODE_1_0)\n#define BIT_SET_LCK_SEARCH_MODE_1_0(x, v)                                      \\\n\t(BIT_CLEAR_LCK_SEARCH_MODE_1_0(x) | BIT_LCK_SEARCH_MODE_1_0(v))\n\n#define BIT_SHIFT_LS_CV_OFFSET_3_0 12\n#define BIT_MASK_LS_CV_OFFSET_3_0 0xf\n#define BIT_LS_CV_OFFSET_3_0(x)                                                \\\n\t(((x) & BIT_MASK_LS_CV_OFFSET_3_0) << BIT_SHIFT_LS_CV_OFFSET_3_0)\n#define BITS_LS_CV_OFFSET_3_0                                                  \\\n\t(BIT_MASK_LS_CV_OFFSET_3_0 << BIT_SHIFT_LS_CV_OFFSET_3_0)\n#define BIT_CLEAR_LS_CV_OFFSET_3_0(x) ((x) & (~BITS_LS_CV_OFFSET_3_0))\n#define BIT_GET_LS_CV_OFFSET_3_0(x)                                            \\\n\t(((x) >> BIT_SHIFT_LS_CV_OFFSET_3_0) & BIT_MASK_LS_CV_OFFSET_3_0)\n#define BIT_SET_LS_CV_OFFSET_3_0(x, v)                                         \\\n\t(BIT_CLEAR_LS_CV_OFFSET_3_0(x) | BIT_LS_CV_OFFSET_3_0(v))\n\n#define BIT_LS_EN_LC_CK40M BIT(11)\n#define BIT_LS__CV_MANUAL BIT(10)\n#define BIT_LS_PYPASS_PI BIT(9)\n#define BIT_MBIASE BIT(4)\n\n/* 2 REG_ANAPAR_MAC_4\t\t\t(Offset 0x1028) */\n\n#define BIT_LS_TIE_MID_MODE BIT(28)\n\n#define BIT_SHIFT_LS_SYNC_CYCLE_1_0 26\n#define BIT_MASK_LS_SYNC_CYCLE_1_0 0x3\n#define BIT_LS_SYNC_CYCLE_1_0(x)                                               \\\n\t(((x) & BIT_MASK_LS_SYNC_CYCLE_1_0) << BIT_SHIFT_LS_SYNC_CYCLE_1_0)\n#define BITS_LS_SYNC_CYCLE_1_0                                                 \\\n\t(BIT_MASK_LS_SYNC_CYCLE_1_0 << BIT_SHIFT_LS_SYNC_CYCLE_1_0)\n#define BIT_CLEAR_LS_SYNC_CYCLE_1_0(x) ((x) & (~BITS_LS_SYNC_CYCLE_1_0))\n#define BIT_GET_LS_SYNC_CYCLE_1_0(x)                                           \\\n\t(((x) >> BIT_SHIFT_LS_SYNC_CYCLE_1_0) & BIT_MASK_LS_SYNC_CYCLE_1_0)\n#define BIT_SET_LS_SYNC_CYCLE_1_0(x, v)                                        \\\n\t(BIT_CLEAR_LS_SYNC_CYCLE_1_0(x) | BIT_LS_SYNC_CYCLE_1_0(v))\n\n#define BIT_LS_SDM_ORDER BIT(25)\n#define BIT_LS_RST_LC_CAL BIT(14)\n#define BIT_LS_RSTB BIT(13)\n#define BIT_LS_POW_LC_CAL_PREP BIT(11)\n\n#define BIT_SHIFT_LCK_XTAL_DIVISOR_1_0 0\n#define BIT_MASK_LCK_XTAL_DIVISOR_1_0 0x3\n#define BIT_LCK_XTAL_DIVISOR_1_0(x)                                            \\\n\t(((x) & BIT_MASK_LCK_XTAL_DIVISOR_1_0)                                 \\\n\t << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0)\n#define BITS_LCK_XTAL_DIVISOR_1_0                                              \\\n\t(BIT_MASK_LCK_XTAL_DIVISOR_1_0 << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0)\n#define BIT_CLEAR_LCK_XTAL_DIVISOR_1_0(x) ((x) & (~BITS_LCK_XTAL_DIVISOR_1_0))\n#define BIT_GET_LCK_XTAL_DIVISOR_1_0(x)                                        \\\n\t(((x) >> BIT_SHIFT_LCK_XTAL_DIVISOR_1_0) &                             \\\n\t BIT_MASK_LCK_XTAL_DIVISOR_1_0)\n#define BIT_SET_LCK_XTAL_DIVISOR_1_0(x, v)                                     \\\n\t(BIT_CLEAR_LCK_XTAL_DIVISOR_1_0(x) | BIT_LCK_XTAL_DIVISOR_1_0(v))\n\n/* 2 REG_ANAPAR_MAC_5\t\t\t(Offset 0x102C) */\n\n#define BIT_SHIFT_LS_XTAL_SEL_3_0 0\n#define BIT_MASK_LS_XTAL_SEL_3_0 0xf\n#define BIT_LS_XTAL_SEL_3_0(x)                                                 \\\n\t(((x) & BIT_MASK_LS_XTAL_SEL_3_0) << BIT_SHIFT_LS_XTAL_SEL_3_0)\n#define BITS_LS_XTAL_SEL_3_0                                                   \\\n\t(BIT_MASK_LS_XTAL_SEL_3_0 << BIT_SHIFT_LS_XTAL_SEL_3_0)\n#define BIT_CLEAR_LS_XTAL_SEL_3_0(x) ((x) & (~BITS_LS_XTAL_SEL_3_0))\n#define BIT_GET_LS_XTAL_SEL_3_0(x)                                             \\\n\t(((x) >> BIT_SHIFT_LS_XTAL_SEL_3_0) & BIT_MASK_LS_XTAL_SEL_3_0)\n#define BIT_SET_LS_XTAL_SEL_3_0(x, v)                                          \\\n\t(BIT_CLEAR_LS_XTAL_SEL_3_0(x) | BIT_LS_XTAL_SEL_3_0(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SYS_CFG4\t\t\t\t(Offset 0x1034) */\n\n#define BIT_EF_CSER_1 BIT(26)\n#define BIT_SW_PG_EN_1 BIT(10)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_0\t\t\t(Offset 0x1040) */\n\n#define BIT_XTAL_SC_LPS BIT(31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_0\t\t\t(Offset 0x1040) */\n\n#define BIT_XTAL_DRV_RF1_0 BIT(31)\n#define BIT_XTAL_GATED_RF1N BIT(30)\n#define BIT_XTAL_GATED_RF1P BIT(29)\n#define BIT_XTAL_GM_SEP_V2 BIT(28)\n\n#define BIT_SHIFT_XTAL_LDO_1_0 26\n#define BIT_MASK_XTAL_LDO_1_0 0x3\n#define BIT_XTAL_LDO_1_0(x)                                                    \\\n\t(((x) & BIT_MASK_XTAL_LDO_1_0) << BIT_SHIFT_XTAL_LDO_1_0)\n#define BITS_XTAL_LDO_1_0 (BIT_MASK_XTAL_LDO_1_0 << BIT_SHIFT_XTAL_LDO_1_0)\n#define BIT_CLEAR_XTAL_LDO_1_0(x) ((x) & (~BITS_XTAL_LDO_1_0))\n#define BIT_GET_XTAL_LDO_1_0(x)                                                \\\n\t(((x) >> BIT_SHIFT_XTAL_LDO_1_0) & BIT_MASK_XTAL_LDO_1_0)\n#define BIT_SET_XTAL_LDO_1_0(x, v)                                             \\\n\t(BIT_CLEAR_XTAL_LDO_1_0(x) | BIT_XTAL_LDO_1_0(v))\n\n#define BIT_XQSEL_V1 BIT(25)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_0\t\t\t(Offset 0x1040) */\n\n#define BIT_SHIFT_XTAL_SC_INIT 24\n#define BIT_MASK_XTAL_SC_INIT 0x7f\n#define BIT_XTAL_SC_INIT(x)                                                    \\\n\t(((x) & BIT_MASK_XTAL_SC_INIT) << BIT_SHIFT_XTAL_SC_INIT)\n#define BITS_XTAL_SC_INIT (BIT_MASK_XTAL_SC_INIT << BIT_SHIFT_XTAL_SC_INIT)\n#define BIT_CLEAR_XTAL_SC_INIT(x) ((x) & (~BITS_XTAL_SC_INIT))\n#define BIT_GET_XTAL_SC_INIT(x)                                                \\\n\t(((x) >> BIT_SHIFT_XTAL_SC_INIT) & BIT_MASK_XTAL_SC_INIT)\n#define BIT_SET_XTAL_SC_INIT(x, v)                                             \\\n\t(BIT_CLEAR_XTAL_SC_INIT(x) | BIT_XTAL_SC_INIT(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_0\t\t\t(Offset 0x1040) */\n\n#define BIT_GATED_XTAL_OK0 BIT(24)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_0\t\t\t(Offset 0x1040) */\n\n#define BIT_SHIFT_XTAL_SC_XO 17\n#define BIT_MASK_XTAL_SC_XO 0x7f\n#define BIT_XTAL_SC_XO(x) (((x) & BIT_MASK_XTAL_SC_XO) << BIT_SHIFT_XTAL_SC_XO)\n#define BITS_XTAL_SC_XO (BIT_MASK_XTAL_SC_XO << BIT_SHIFT_XTAL_SC_XO)\n#define BIT_CLEAR_XTAL_SC_XO(x) ((x) & (~BITS_XTAL_SC_XO))\n#define BIT_GET_XTAL_SC_XO(x)                                                  \\\n\t(((x) >> BIT_SHIFT_XTAL_SC_XO) & BIT_MASK_XTAL_SC_XO)\n#define BIT_SET_XTAL_SC_XO(x, v) (BIT_CLEAR_XTAL_SC_XO(x) | BIT_XTAL_SC_XO(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_0\t\t\t(Offset 0x1040) */\n\n#define BIT_SHIFT_XTAL_SC_XO_6_0 17\n#define BIT_MASK_XTAL_SC_XO_6_0 0x7f\n#define BIT_XTAL_SC_XO_6_0(x)                                                  \\\n\t(((x) & BIT_MASK_XTAL_SC_XO_6_0) << BIT_SHIFT_XTAL_SC_XO_6_0)\n#define BITS_XTAL_SC_XO_6_0                                                    \\\n\t(BIT_MASK_XTAL_SC_XO_6_0 << BIT_SHIFT_XTAL_SC_XO_6_0)\n#define BIT_CLEAR_XTAL_SC_XO_6_0(x) ((x) & (~BITS_XTAL_SC_XO_6_0))\n#define BIT_GET_XTAL_SC_XO_6_0(x)                                              \\\n\t(((x) >> BIT_SHIFT_XTAL_SC_XO_6_0) & BIT_MASK_XTAL_SC_XO_6_0)\n#define BIT_SET_XTAL_SC_XO_6_0(x, v)                                           \\\n\t(BIT_CLEAR_XTAL_SC_XO_6_0(x) | BIT_XTAL_SC_XO_6_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_0\t\t\t(Offset 0x1040) */\n\n#define BIT_SHIFT_XTAL_SC_XI 10\n#define BIT_MASK_XTAL_SC_XI 0x7f\n#define BIT_XTAL_SC_XI(x) (((x) & BIT_MASK_XTAL_SC_XI) << BIT_SHIFT_XTAL_SC_XI)\n#define BITS_XTAL_SC_XI (BIT_MASK_XTAL_SC_XI << BIT_SHIFT_XTAL_SC_XI)\n#define BIT_CLEAR_XTAL_SC_XI(x) ((x) & (~BITS_XTAL_SC_XI))\n#define BIT_GET_XTAL_SC_XI(x)                                                  \\\n\t(((x) >> BIT_SHIFT_XTAL_SC_XI) & BIT_MASK_XTAL_SC_XI)\n#define BIT_SET_XTAL_SC_XI(x, v) (BIT_CLEAR_XTAL_SC_XI(x) | BIT_XTAL_SC_XI(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_0\t\t\t(Offset 0x1040) */\n\n#define BIT_SHIFT_XTAL_SC_XI_6_0 10\n#define BIT_MASK_XTAL_SC_XI_6_0 0x7f\n#define BIT_XTAL_SC_XI_6_0(x)                                                  \\\n\t(((x) & BIT_MASK_XTAL_SC_XI_6_0) << BIT_SHIFT_XTAL_SC_XI_6_0)\n#define BITS_XTAL_SC_XI_6_0                                                    \\\n\t(BIT_MASK_XTAL_SC_XI_6_0 << BIT_SHIFT_XTAL_SC_XI_6_0)\n#define BIT_CLEAR_XTAL_SC_XI_6_0(x) ((x) & (~BITS_XTAL_SC_XI_6_0))\n#define BIT_GET_XTAL_SC_XI_6_0(x)                                              \\\n\t(((x) >> BIT_SHIFT_XTAL_SC_XI_6_0) & BIT_MASK_XTAL_SC_XI_6_0)\n#define BIT_SET_XTAL_SC_XI_6_0(x, v)                                           \\\n\t(BIT_CLEAR_XTAL_SC_XI_6_0(x) | BIT_XTAL_SC_XI_6_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_0\t\t\t(Offset 0x1040) */\n\n#define BIT_SHIFT_XTAL_GMN_V3 5\n#define BIT_MASK_XTAL_GMN_V3 0x1f\n#define BIT_XTAL_GMN_V3(x)                                                     \\\n\t(((x) & BIT_MASK_XTAL_GMN_V3) << BIT_SHIFT_XTAL_GMN_V3)\n#define BITS_XTAL_GMN_V3 (BIT_MASK_XTAL_GMN_V3 << BIT_SHIFT_XTAL_GMN_V3)\n#define BIT_CLEAR_XTAL_GMN_V3(x) ((x) & (~BITS_XTAL_GMN_V3))\n#define BIT_GET_XTAL_GMN_V3(x)                                                 \\\n\t(((x) >> BIT_SHIFT_XTAL_GMN_V3) & BIT_MASK_XTAL_GMN_V3)\n#define BIT_SET_XTAL_GMN_V3(x, v)                                              \\\n\t(BIT_CLEAR_XTAL_GMN_V3(x) | BIT_XTAL_GMN_V3(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_0\t\t\t(Offset 0x1040) */\n\n#define BIT_SHIFT_XTAL_GMN_4_0 5\n#define BIT_MASK_XTAL_GMN_4_0 0x1f\n#define BIT_XTAL_GMN_4_0(x)                                                    \\\n\t(((x) & BIT_MASK_XTAL_GMN_4_0) << BIT_SHIFT_XTAL_GMN_4_0)\n#define BITS_XTAL_GMN_4_0 (BIT_MASK_XTAL_GMN_4_0 << BIT_SHIFT_XTAL_GMN_4_0)\n#define BIT_CLEAR_XTAL_GMN_4_0(x) ((x) & (~BITS_XTAL_GMN_4_0))\n#define BIT_GET_XTAL_GMN_4_0(x)                                                \\\n\t(((x) >> BIT_SHIFT_XTAL_GMN_4_0) & BIT_MASK_XTAL_GMN_4_0)\n#define BIT_SET_XTAL_GMN_4_0(x, v)                                             \\\n\t(BIT_CLEAR_XTAL_GMN_4_0(x) | BIT_XTAL_GMN_4_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_0\t\t\t(Offset 0x1040) */\n\n#define BIT_SHIFT_XTAL_GMP_V3 0\n#define BIT_MASK_XTAL_GMP_V3 0x1f\n#define BIT_XTAL_GMP_V3(x)                                                     \\\n\t(((x) & BIT_MASK_XTAL_GMP_V3) << BIT_SHIFT_XTAL_GMP_V3)\n#define BITS_XTAL_GMP_V3 (BIT_MASK_XTAL_GMP_V3 << BIT_SHIFT_XTAL_GMP_V3)\n#define BIT_CLEAR_XTAL_GMP_V3(x) ((x) & (~BITS_XTAL_GMP_V3))\n#define BIT_GET_XTAL_GMP_V3(x)                                                 \\\n\t(((x) >> BIT_SHIFT_XTAL_GMP_V3) & BIT_MASK_XTAL_GMP_V3)\n#define BIT_SET_XTAL_GMP_V3(x, v)                                              \\\n\t(BIT_CLEAR_XTAL_GMP_V3(x) | BIT_XTAL_GMP_V3(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_0\t\t\t(Offset 0x1040) */\n\n#define BIT_SHIFT_XTAL_GMP_4_0 0\n#define BIT_MASK_XTAL_GMP_4_0 0x1f\n#define BIT_XTAL_GMP_4_0(x)                                                    \\\n\t(((x) & BIT_MASK_XTAL_GMP_4_0) << BIT_SHIFT_XTAL_GMP_4_0)\n#define BITS_XTAL_GMP_4_0 (BIT_MASK_XTAL_GMP_4_0 << BIT_SHIFT_XTAL_GMP_4_0)\n#define BIT_CLEAR_XTAL_GMP_4_0(x) ((x) & (~BITS_XTAL_GMP_4_0))\n#define BIT_GET_XTAL_GMP_4_0(x)                                                \\\n\t(((x) >> BIT_SHIFT_XTAL_GMP_4_0) & BIT_MASK_XTAL_GMP_4_0)\n#define BIT_SET_XTAL_GMP_4_0(x, v)                                             \\\n\t(BIT_CLEAR_XTAL_GMP_4_0(x) | BIT_XTAL_GMP_4_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_XTAL_SEL_TOK_V1 BIT(31)\n#define BIT_XTAL_DELAY_DIGI_V2 BIT(30)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_SHIFT_XTAL_LDO_OK_1_0 30\n#define BIT_MASK_XTAL_LDO_OK_1_0 0x3\n#define BIT_XTAL_LDO_OK_1_0(x)                                                 \\\n\t(((x) & BIT_MASK_XTAL_LDO_OK_1_0) << BIT_SHIFT_XTAL_LDO_OK_1_0)\n#define BITS_XTAL_LDO_OK_1_0                                                   \\\n\t(BIT_MASK_XTAL_LDO_OK_1_0 << BIT_SHIFT_XTAL_LDO_OK_1_0)\n#define BIT_CLEAR_XTAL_LDO_OK_1_0(x) ((x) & (~BITS_XTAL_LDO_OK_1_0))\n#define BIT_GET_XTAL_LDO_OK_1_0(x)                                             \\\n\t(((x) >> BIT_SHIFT_XTAL_LDO_OK_1_0) & BIT_MASK_XTAL_LDO_OK_1_0)\n#define BIT_SET_XTAL_LDO_OK_1_0(x, v)                                          \\\n\t(BIT_CLEAR_XTAL_LDO_OK_1_0(x) | BIT_XTAL_LDO_OK_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_XTAL_DELAY_USB_V2 BIT(29)\n#define BIT_XTAL_DELAY_AFE_V2 BIT(28)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_SHIFT_XTAL_XORES_SEL_2_0 27\n#define BIT_MASK_XTAL_XORES_SEL_2_0 0x7\n#define BIT_XTAL_XORES_SEL_2_0(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_XORES_SEL_2_0) << BIT_SHIFT_XTAL_XORES_SEL_2_0)\n#define BITS_XTAL_XORES_SEL_2_0                                                \\\n\t(BIT_MASK_XTAL_XORES_SEL_2_0 << BIT_SHIFT_XTAL_XORES_SEL_2_0)\n#define BIT_CLEAR_XTAL_XORES_SEL_2_0(x) ((x) & (~BITS_XTAL_XORES_SEL_2_0))\n#define BIT_GET_XTAL_XORES_SEL_2_0(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_XORES_SEL_2_0) & BIT_MASK_XTAL_XORES_SEL_2_0)\n#define BIT_SET_XTAL_XORES_SEL_2_0(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_XORES_SEL_2_0(x) | BIT_XTAL_XORES_SEL_2_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_SHIFT_XTAL_DRV_DIGI_V2 26\n#define BIT_MASK_XTAL_DRV_DIGI_V2 0x3\n#define BIT_XTAL_DRV_DIGI_V2(x)                                                \\\n\t(((x) & BIT_MASK_XTAL_DRV_DIGI_V2) << BIT_SHIFT_XTAL_DRV_DIGI_V2)\n#define BITS_XTAL_DRV_DIGI_V2                                                  \\\n\t(BIT_MASK_XTAL_DRV_DIGI_V2 << BIT_SHIFT_XTAL_DRV_DIGI_V2)\n#define BIT_CLEAR_XTAL_DRV_DIGI_V2(x) ((x) & (~BITS_XTAL_DRV_DIGI_V2))\n#define BIT_GET_XTAL_DRV_DIGI_V2(x)                                            \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_DIGI_V2) & BIT_MASK_XTAL_DRV_DIGI_V2)\n#define BIT_SET_XTAL_DRV_DIGI_V2(x, v)                                         \\\n\t(BIT_CLEAR_XTAL_DRV_DIGI_V2(x) | BIT_XTAL_DRV_DIGI_V2(v))\n\n#define BIT_EN_XTAL_DRV_LPS BIT(25)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_SHIFT_XTAL_AAC_PK_SEL_1_0 25\n#define BIT_MASK_XTAL_AAC_PK_SEL_1_0 0x3\n#define BIT_XTAL_AAC_PK_SEL_1_0(x)                                             \\\n\t(((x) & BIT_MASK_XTAL_AAC_PK_SEL_1_0) << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0)\n#define BITS_XTAL_AAC_PK_SEL_1_0                                               \\\n\t(BIT_MASK_XTAL_AAC_PK_SEL_1_0 << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0)\n#define BIT_CLEAR_XTAL_AAC_PK_SEL_1_0(x) ((x) & (~BITS_XTAL_AAC_PK_SEL_1_0))\n#define BIT_GET_XTAL_AAC_PK_SEL_1_0(x)                                         \\\n\t(((x) >> BIT_SHIFT_XTAL_AAC_PK_SEL_1_0) & BIT_MASK_XTAL_AAC_PK_SEL_1_0)\n#define BIT_SET_XTAL_AAC_PK_SEL_1_0(x, v)                                      \\\n\t(BIT_CLEAR_XTAL_AAC_PK_SEL_1_0(x) | BIT_XTAL_AAC_PK_SEL_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_EN_XTAL_DRV_DIGI_V2 BIT(24)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_EN_XTAL_AAC_PKDET BIT(24)\n#define BIT_EN_XTAL_AAC_GM BIT(23)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_SHIFT_XTAL_DRV_USB 22\n#define BIT_MASK_XTAL_DRV_USB 0x3\n#define BIT_XTAL_DRV_USB(x)                                                    \\\n\t(((x) & BIT_MASK_XTAL_DRV_USB) << BIT_SHIFT_XTAL_DRV_USB)\n#define BITS_XTAL_DRV_USB (BIT_MASK_XTAL_DRV_USB << BIT_SHIFT_XTAL_DRV_USB)\n#define BIT_CLEAR_XTAL_DRV_USB(x) ((x) & (~BITS_XTAL_DRV_USB))\n#define BIT_GET_XTAL_DRV_USB(x)                                                \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_USB) & BIT_MASK_XTAL_DRV_USB)\n#define BIT_SET_XTAL_DRV_USB(x, v)                                             \\\n\t(BIT_CLEAR_XTAL_DRV_USB(x) | BIT_XTAL_DRV_USB(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_XTAL_LPMODE BIT(22)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_EN_XTAL_DRV_USB BIT(21)\n\n#define BIT_SHIFT_XTAL_DRV_AFE_V2 19\n#define BIT_MASK_XTAL_DRV_AFE_V2 0x3\n#define BIT_XTAL_DRV_AFE_V2(x)                                                 \\\n\t(((x) & BIT_MASK_XTAL_DRV_AFE_V2) << BIT_SHIFT_XTAL_DRV_AFE_V2)\n#define BITS_XTAL_DRV_AFE_V2                                                   \\\n\t(BIT_MASK_XTAL_DRV_AFE_V2 << BIT_SHIFT_XTAL_DRV_AFE_V2)\n#define BIT_CLEAR_XTAL_DRV_AFE_V2(x) ((x) & (~BITS_XTAL_DRV_AFE_V2))\n#define BIT_GET_XTAL_DRV_AFE_V2(x)                                             \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_AFE_V2) & BIT_MASK_XTAL_DRV_AFE_V2)\n#define BIT_SET_XTAL_DRV_AFE_V2(x, v)                                          \\\n\t(BIT_CLEAR_XTAL_DRV_AFE_V2(x) | BIT_XTAL_DRV_AFE_V2(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_SHIFT_XTAL_SEL_TOK_2_0 19\n#define BIT_MASK_XTAL_SEL_TOK_2_0 0x7\n#define BIT_XTAL_SEL_TOK_2_0(x)                                                \\\n\t(((x) & BIT_MASK_XTAL_SEL_TOK_2_0) << BIT_SHIFT_XTAL_SEL_TOK_2_0)\n#define BITS_XTAL_SEL_TOK_2_0                                                  \\\n\t(BIT_MASK_XTAL_SEL_TOK_2_0 << BIT_SHIFT_XTAL_SEL_TOK_2_0)\n#define BIT_CLEAR_XTAL_SEL_TOK_2_0(x) ((x) & (~BITS_XTAL_SEL_TOK_2_0))\n#define BIT_GET_XTAL_SEL_TOK_2_0(x)                                            \\\n\t(((x) >> BIT_SHIFT_XTAL_SEL_TOK_2_0) & BIT_MASK_XTAL_SEL_TOK_2_0)\n#define BIT_SET_XTAL_SEL_TOK_2_0(x, v)                                         \\\n\t(BIT_CLEAR_XTAL_SEL_TOK_2_0(x) | BIT_XTAL_SEL_TOK_2_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_EN_XTAL_DRV_AFE BIT(18)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_XQSEL_RF_AWAKE_V2 BIT(18)\n#define BIT_XQSEL_RF_INITIAL_V2 BIT(17)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_SHIFT_XTAL_DRV_RF2_V2 16\n#define BIT_MASK_XTAL_DRV_RF2_V2 0x3\n#define BIT_XTAL_DRV_RF2_V2(x)                                                 \\\n\t(((x) & BIT_MASK_XTAL_DRV_RF2_V2) << BIT_SHIFT_XTAL_DRV_RF2_V2)\n#define BITS_XTAL_DRV_RF2_V2                                                   \\\n\t(BIT_MASK_XTAL_DRV_RF2_V2 << BIT_SHIFT_XTAL_DRV_RF2_V2)\n#define BIT_CLEAR_XTAL_DRV_RF2_V2(x) ((x) & (~BITS_XTAL_DRV_RF2_V2))\n#define BIT_GET_XTAL_DRV_RF2_V2(x)                                             \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_RF2_V2) & BIT_MASK_XTAL_DRV_RF2_V2)\n#define BIT_SET_XTAL_DRV_RF2_V2(x, v)                                          \\\n\t(BIT_CLEAR_XTAL_DRV_RF2_V2(x) | BIT_XTAL_DRV_RF2_V2(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_XTAL_DELAY_USB_V1 BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_EN_XTAL_DRV_RF2 BIT(15)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_XTAL_DELAY_DIGI_V1 BIT(15)\n#define BIT_XTAL_DELAY_AFE_V1 BIT(14)\n#define BIT_XTAL_DRV_RF_LATCH_V3 BIT(13)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_EN_XTAL_DRV_RF1 BIT(12)\n#define BIT_XTAL_DRV_RF_LATCH_V4 BIT(11)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_SHIFT_XTAL_DRV_DIGI_1_0 11\n#define BIT_MASK_XTAL_DRV_DIGI_1_0 0x3\n#define BIT_XTAL_DRV_DIGI_1_0(x)                                               \\\n\t(((x) & BIT_MASK_XTAL_DRV_DIGI_1_0) << BIT_SHIFT_XTAL_DRV_DIGI_1_0)\n#define BITS_XTAL_DRV_DIGI_1_0                                                 \\\n\t(BIT_MASK_XTAL_DRV_DIGI_1_0 << BIT_SHIFT_XTAL_DRV_DIGI_1_0)\n#define BIT_CLEAR_XTAL_DRV_DIGI_1_0(x) ((x) & (~BITS_XTAL_DRV_DIGI_1_0))\n#define BIT_GET_XTAL_DRV_DIGI_1_0(x)                                           \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_DIGI_1_0) & BIT_MASK_XTAL_DRV_DIGI_1_0)\n#define BIT_SET_XTAL_DRV_DIGI_1_0(x, v)                                        \\\n\t(BIT_CLEAR_XTAL_DRV_DIGI_1_0(x) | BIT_XTAL_DRV_DIGI_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_XTAL_GM_SEP_V3 BIT(10)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_XTAL_GATED_DIGIN BIT(10)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_XQSEL_RF_AWAKE_V3 BIT(9)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_XTAL_GATED_DIGIP BIT(9)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_XQSEL_RF_INITIAL_V3 BIT(8)\n#define BIT_XQSEL_V2 BIT(7)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_SHIFT_XTAL_DRV_USB_1_0 7\n#define BIT_MASK_XTAL_DRV_USB_1_0 0x3\n#define BIT_XTAL_DRV_USB_1_0(x)                                                \\\n\t(((x) & BIT_MASK_XTAL_DRV_USB_1_0) << BIT_SHIFT_XTAL_DRV_USB_1_0)\n#define BITS_XTAL_DRV_USB_1_0                                                  \\\n\t(BIT_MASK_XTAL_DRV_USB_1_0 << BIT_SHIFT_XTAL_DRV_USB_1_0)\n#define BIT_CLEAR_XTAL_DRV_USB_1_0(x) ((x) & (~BITS_XTAL_DRV_USB_1_0))\n#define BIT_GET_XTAL_DRV_USB_1_0(x)                                            \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_USB_1_0) & BIT_MASK_XTAL_DRV_USB_1_0)\n#define BIT_SET_XTAL_DRV_USB_1_0(x, v)                                         \\\n\t(BIT_CLEAR_XTAL_DRV_USB_1_0(x) | BIT_XTAL_DRV_USB_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_GATED_XTAL_OK0_V2 BIT(6)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_XTAL_GATED_USBN BIT(6)\n#define BIT_XTAL_GATED_USBP BIT(5)\n\n#define BIT_SHIFT_XTAL_DRV_AFE_1_0 3\n#define BIT_MASK_XTAL_DRV_AFE_1_0 0x3\n#define BIT_XTAL_DRV_AFE_1_0(x)                                                \\\n\t(((x) & BIT_MASK_XTAL_DRV_AFE_1_0) << BIT_SHIFT_XTAL_DRV_AFE_1_0)\n#define BITS_XTAL_DRV_AFE_1_0                                                  \\\n\t(BIT_MASK_XTAL_DRV_AFE_1_0 << BIT_SHIFT_XTAL_DRV_AFE_1_0)\n#define BIT_CLEAR_XTAL_DRV_AFE_1_0(x) ((x) & (~BITS_XTAL_DRV_AFE_1_0))\n#define BIT_GET_XTAL_DRV_AFE_1_0(x)                                            \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_AFE_1_0) & BIT_MASK_XTAL_DRV_AFE_1_0)\n#define BIT_SET_XTAL_DRV_AFE_1_0(x, v)                                         \\\n\t(BIT_CLEAR_XTAL_DRV_AFE_1_0(x) | BIT_XTAL_DRV_AFE_1_0(v))\n\n#define BIT_XTAL_GATED_AFEN BIT(2)\n#define BIT_XTAL_GATED_AFEP BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_SHIFT_XTAL_SC_LPS_V2 0\n#define BIT_MASK_XTAL_SC_LPS_V2 0x3f\n#define BIT_XTAL_SC_LPS_V2(x)                                                  \\\n\t(((x) & BIT_MASK_XTAL_SC_LPS_V2) << BIT_SHIFT_XTAL_SC_LPS_V2)\n#define BITS_XTAL_SC_LPS_V2                                                    \\\n\t(BIT_MASK_XTAL_SC_LPS_V2 << BIT_SHIFT_XTAL_SC_LPS_V2)\n#define BIT_CLEAR_XTAL_SC_LPS_V2(x) ((x) & (~BITS_XTAL_SC_LPS_V2))\n#define BIT_GET_XTAL_SC_LPS_V2(x)                                              \\\n\t(((x) >> BIT_SHIFT_XTAL_SC_LPS_V2) & BIT_MASK_XTAL_SC_LPS_V2)\n#define BIT_SET_XTAL_SC_LPS_V2(x, v)                                           \\\n\t(BIT_CLEAR_XTAL_SC_LPS_V2(x) | BIT_XTAL_SC_LPS_V2(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_1\t\t\t(Offset 0x1044) */\n\n#define BIT_XTAL_DRV_RF1_1 BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_2\t\t\t(Offset 0x1048) */\n\n#define BIT_XTAL_AAC_CAP BIT(31)\n\n#define BIT_SHIFT_XTAL_PDSW 29\n#define BIT_MASK_XTAL_PDSW 0x3\n#define BIT_XTAL_PDSW(x) (((x) & BIT_MASK_XTAL_PDSW) << BIT_SHIFT_XTAL_PDSW)\n#define BITS_XTAL_PDSW (BIT_MASK_XTAL_PDSW << BIT_SHIFT_XTAL_PDSW)\n#define BIT_CLEAR_XTAL_PDSW(x) ((x) & (~BITS_XTAL_PDSW))\n#define BIT_GET_XTAL_PDSW(x) (((x) >> BIT_SHIFT_XTAL_PDSW) & BIT_MASK_XTAL_PDSW)\n#define BIT_SET_XTAL_PDSW(x, v) (BIT_CLEAR_XTAL_PDSW(x) | BIT_XTAL_PDSW(v))\n\n#define BIT_SHIFT_XTAL_LPS_BUF_VB 27\n#define BIT_MASK_XTAL_LPS_BUF_VB 0x3\n#define BIT_XTAL_LPS_BUF_VB(x)                                                 \\\n\t(((x) & BIT_MASK_XTAL_LPS_BUF_VB) << BIT_SHIFT_XTAL_LPS_BUF_VB)\n#define BITS_XTAL_LPS_BUF_VB                                                   \\\n\t(BIT_MASK_XTAL_LPS_BUF_VB << BIT_SHIFT_XTAL_LPS_BUF_VB)\n#define BIT_CLEAR_XTAL_LPS_BUF_VB(x) ((x) & (~BITS_XTAL_LPS_BUF_VB))\n#define BIT_GET_XTAL_LPS_BUF_VB(x)                                             \\\n\t(((x) >> BIT_SHIFT_XTAL_LPS_BUF_VB) & BIT_MASK_XTAL_LPS_BUF_VB)\n#define BIT_SET_XTAL_LPS_BUF_VB(x, v)                                          \\\n\t(BIT_CLEAR_XTAL_LPS_BUF_VB(x) | BIT_XTAL_LPS_BUF_VB(v))\n\n#define BIT_XTAL_PDCK_MANU BIT(26)\n#define BIT_XTAL_PDCK_OK_MANU BIT(25)\n\n#define BIT_SHIFT_XTAL_VREF_SEL 20\n#define BIT_MASK_XTAL_VREF_SEL 0x1f\n#define BIT_XTAL_VREF_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_XTAL_VREF_SEL) << BIT_SHIFT_XTAL_VREF_SEL)\n#define BITS_XTAL_VREF_SEL (BIT_MASK_XTAL_VREF_SEL << BIT_SHIFT_XTAL_VREF_SEL)\n#define BIT_CLEAR_XTAL_VREF_SEL(x) ((x) & (~BITS_XTAL_VREF_SEL))\n#define BIT_GET_XTAL_VREF_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_XTAL_VREF_SEL) & BIT_MASK_XTAL_VREF_SEL)\n#define BIT_SET_XTAL_VREF_SEL(x, v)                                            \\\n\t(BIT_CLEAR_XTAL_VREF_SEL(x) | BIT_XTAL_VREF_SEL(v))\n\n#define BIT_EN_XTAL_PDCK_VREF BIT(19)\n#define BIT_XTAL_SEL_PWR_V1 BIT(18)\n#define BIT_XTAL_LPS_DIVISOR BIT(17)\n#define BIT_XTAL_CKDIGI_SEL BIT(16)\n#define BIT_EN_XTAL_LPS_CLK BIT(15)\n#define BIT_EN_XTAL_SCHMITT BIT(14)\n#define BIT_XTAL_PK_SEL_OFFSET BIT(13)\n\n#define BIT_SHIFT_XTAL_MANU_PK_SEL 11\n#define BIT_MASK_XTAL_MANU_PK_SEL 0x3\n#define BIT_XTAL_MANU_PK_SEL(x)                                                \\\n\t(((x) & BIT_MASK_XTAL_MANU_PK_SEL) << BIT_SHIFT_XTAL_MANU_PK_SEL)\n#define BITS_XTAL_MANU_PK_SEL                                                  \\\n\t(BIT_MASK_XTAL_MANU_PK_SEL << BIT_SHIFT_XTAL_MANU_PK_SEL)\n#define BIT_CLEAR_XTAL_MANU_PK_SEL(x) ((x) & (~BITS_XTAL_MANU_PK_SEL))\n#define BIT_GET_XTAL_MANU_PK_SEL(x)                                            \\\n\t(((x) >> BIT_SHIFT_XTAL_MANU_PK_SEL) & BIT_MASK_XTAL_MANU_PK_SEL)\n#define BIT_SET_XTAL_MANU_PK_SEL(x, v)                                         \\\n\t(BIT_CLEAR_XTAL_MANU_PK_SEL(x) | BIT_XTAL_MANU_PK_SEL(v))\n\n#define BIT_XTAL_AACK_PK_MANU BIT(10)\n#define BIT_EN_XTAL_AAC_PKDET_V1 BIT(9)\n#define BIT_EN_XTAL_AAC_GM_V1 BIT(8)\n#define BIT_XTAL_LDO_OPVB_SEL BIT(7)\n\n#define BIT_SHIFT_XTAL_DUMMY_V1 7\n#define BIT_MASK_XTAL_DUMMY_V1 0x3f\n#define BIT_XTAL_DUMMY_V1(x)                                                   \\\n\t(((x) & BIT_MASK_XTAL_DUMMY_V1) << BIT_SHIFT_XTAL_DUMMY_V1)\n#define BITS_XTAL_DUMMY_V1 (BIT_MASK_XTAL_DUMMY_V1 << BIT_SHIFT_XTAL_DUMMY_V1)\n#define BIT_CLEAR_XTAL_DUMMY_V1(x) ((x) & (~BITS_XTAL_DUMMY_V1))\n#define BIT_GET_XTAL_DUMMY_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_XTAL_DUMMY_V1) & BIT_MASK_XTAL_DUMMY_V1)\n#define BIT_SET_XTAL_DUMMY_V1(x, v)                                            \\\n\t(BIT_CLEAR_XTAL_DUMMY_V1(x) | BIT_XTAL_DUMMY_V1(v))\n\n#define BIT_XTAL_LDO_NC BIT(6)\n#define BIT_XTAL_EN_LNBUF BIT(6)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_2\t\t\t(Offset 0x1048) */\n\n#define BIT_XTAL_DRV_RF2_LATCH BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_2\t\t\t(Offset 0x1048) */\n\n#define BIT_XTAL__AAC_TIE_MID BIT(5)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_2\t\t\t(Offset 0x1048) */\n\n#define BIT_SHIFT_XTAL_DRV_RF2_1_0 4\n#define BIT_MASK_XTAL_DRV_RF2_1_0 0x3\n#define BIT_XTAL_DRV_RF2_1_0(x)                                                \\\n\t(((x) & BIT_MASK_XTAL_DRV_RF2_1_0) << BIT_SHIFT_XTAL_DRV_RF2_1_0)\n#define BITS_XTAL_DRV_RF2_1_0                                                  \\\n\t(BIT_MASK_XTAL_DRV_RF2_1_0 << BIT_SHIFT_XTAL_DRV_RF2_1_0)\n#define BIT_CLEAR_XTAL_DRV_RF2_1_0(x) ((x) & (~BITS_XTAL_DRV_RF2_1_0))\n#define BIT_GET_XTAL_DRV_RF2_1_0(x)                                            \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_RF2_1_0) & BIT_MASK_XTAL_DRV_RF2_1_0)\n#define BIT_SET_XTAL_DRV_RF2_1_0(x, v)                                         \\\n\t(BIT_CLEAR_XTAL_DRV_RF2_1_0(x) | BIT_XTAL_DRV_RF2_1_0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_2\t\t\t(Offset 0x1048) */\n\n#define BIT_SHIFT_XTAL_LDO_VREF_V2 3\n#define BIT_MASK_XTAL_LDO_VREF_V2 0x7\n#define BIT_XTAL_LDO_VREF_V2(x)                                                \\\n\t(((x) & BIT_MASK_XTAL_LDO_VREF_V2) << BIT_SHIFT_XTAL_LDO_VREF_V2)\n#define BITS_XTAL_LDO_VREF_V2                                                  \\\n\t(BIT_MASK_XTAL_LDO_VREF_V2 << BIT_SHIFT_XTAL_LDO_VREF_V2)\n#define BIT_CLEAR_XTAL_LDO_VREF_V2(x) ((x) & (~BITS_XTAL_LDO_VREF_V2))\n#define BIT_GET_XTAL_LDO_VREF_V2(x)                                            \\\n\t(((x) >> BIT_SHIFT_XTAL_LDO_VREF_V2) & BIT_MASK_XTAL_LDO_VREF_V2)\n#define BIT_SET_XTAL_LDO_VREF_V2(x, v)                                         \\\n\t(BIT_CLEAR_XTAL_LDO_VREF_V2(x) | BIT_XTAL_LDO_VREF_V2(v))\n\n#define BIT_SHIFT_XTAL_AAC_OPCUR 3\n#define BIT_MASK_XTAL_AAC_OPCUR 0x3\n#define BIT_XTAL_AAC_OPCUR(x)                                                  \\\n\t(((x) & BIT_MASK_XTAL_AAC_OPCUR) << BIT_SHIFT_XTAL_AAC_OPCUR)\n#define BITS_XTAL_AAC_OPCUR                                                    \\\n\t(BIT_MASK_XTAL_AAC_OPCUR << BIT_SHIFT_XTAL_AAC_OPCUR)\n#define BIT_CLEAR_XTAL_AAC_OPCUR(x) ((x) & (~BITS_XTAL_AAC_OPCUR))\n#define BIT_GET_XTAL_AAC_OPCUR(x)                                              \\\n\t(((x) >> BIT_SHIFT_XTAL_AAC_OPCUR) & BIT_MASK_XTAL_AAC_OPCUR)\n#define BIT_SET_XTAL_AAC_OPCUR(x, v)                                           \\\n\t(BIT_CLEAR_XTAL_AAC_OPCUR(x) | BIT_XTAL_AAC_OPCUR(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_2\t\t\t(Offset 0x1048) */\n\n#define BIT_XTAL_GATED_RF2N BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_2\t\t\t(Offset 0x1048) */\n\n#define BIT_XTAL_LPMODE_V1 BIT(2)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_2\t\t\t(Offset 0x1048) */\n\n#define BIT_XTAL_GATED_RF2P BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_2\t\t\t(Offset 0x1048) */\n\n#define BIT_SHIFT_XTAL_AAC_IOFFSET 1\n#define BIT_MASK_XTAL_AAC_IOFFSET 0x3\n#define BIT_XTAL_AAC_IOFFSET(x)                                                \\\n\t(((x) & BIT_MASK_XTAL_AAC_IOFFSET) << BIT_SHIFT_XTAL_AAC_IOFFSET)\n#define BITS_XTAL_AAC_IOFFSET                                                  \\\n\t(BIT_MASK_XTAL_AAC_IOFFSET << BIT_SHIFT_XTAL_AAC_IOFFSET)\n#define BIT_CLEAR_XTAL_AAC_IOFFSET(x) ((x) & (~BITS_XTAL_AAC_IOFFSET))\n#define BIT_GET_XTAL_AAC_IOFFSET(x)                                            \\\n\t(((x) >> BIT_SHIFT_XTAL_AAC_IOFFSET) & BIT_MASK_XTAL_AAC_IOFFSET)\n#define BIT_SET_XTAL_AAC_IOFFSET(x, v)                                         \\\n\t(BIT_CLEAR_XTAL_AAC_IOFFSET(x) | BIT_XTAL_AAC_IOFFSET(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_2\t\t\t(Offset 0x1048) */\n\n#define BIT_XTAL_LDO_DI BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_2\t\t\t(Offset 0x1048) */\n\n#define BIT_SHIFT_XTAL_SEL_TOK_V3 0\n#define BIT_MASK_XTAL_SEL_TOK_V3 0x3\n#define BIT_XTAL_SEL_TOK_V3(x)                                                 \\\n\t(((x) & BIT_MASK_XTAL_SEL_TOK_V3) << BIT_SHIFT_XTAL_SEL_TOK_V3)\n#define BITS_XTAL_SEL_TOK_V3                                                   \\\n\t(BIT_MASK_XTAL_SEL_TOK_V3 << BIT_SHIFT_XTAL_SEL_TOK_V3)\n#define BIT_CLEAR_XTAL_SEL_TOK_V3(x) ((x) & (~BITS_XTAL_SEL_TOK_V3))\n#define BIT_GET_XTAL_SEL_TOK_V3(x)                                             \\\n\t(((x) >> BIT_SHIFT_XTAL_SEL_TOK_V3) & BIT_MASK_XTAL_SEL_TOK_V3)\n#define BIT_SET_XTAL_SEL_TOK_V3(x, v)                                          \\\n\t(BIT_CLEAR_XTAL_SEL_TOK_V3(x) | BIT_XTAL_SEL_TOK_V3(v))\n\n#define BIT_XTAL_AAC_CAP_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_2\t\t\t(Offset 0x1048) */\n\n#define BIT_XTAL_SEL_PWR BIT(0)\n\n/* 2 REG_ANAPAR_XTAL_AAC\t\t\t(Offset 0x104C) */\n\n#define BIT_SHIFT_GM_MANUAL_4_0 21\n#define BIT_MASK_GM_MANUAL_4_0 0x1f\n#define BIT_GM_MANUAL_4_0(x)                                                   \\\n\t(((x) & BIT_MASK_GM_MANUAL_4_0) << BIT_SHIFT_GM_MANUAL_4_0)\n#define BITS_GM_MANUAL_4_0 (BIT_MASK_GM_MANUAL_4_0 << BIT_SHIFT_GM_MANUAL_4_0)\n#define BIT_CLEAR_GM_MANUAL_4_0(x) ((x) & (~BITS_GM_MANUAL_4_0))\n#define BIT_GET_GM_MANUAL_4_0(x)                                               \\\n\t(((x) >> BIT_SHIFT_GM_MANUAL_4_0) & BIT_MASK_GM_MANUAL_4_0)\n#define BIT_SET_GM_MANUAL_4_0(x, v)                                            \\\n\t(BIT_CLEAR_GM_MANUAL_4_0(x) | BIT_GM_MANUAL_4_0(v))\n\n#define BIT_SHIFT_GM_STUP_4_0 16\n#define BIT_MASK_GM_STUP_4_0 0x1f\n#define BIT_GM_STUP_4_0(x)                                                     \\\n\t(((x) & BIT_MASK_GM_STUP_4_0) << BIT_SHIFT_GM_STUP_4_0)\n#define BITS_GM_STUP_4_0 (BIT_MASK_GM_STUP_4_0 << BIT_SHIFT_GM_STUP_4_0)\n#define BIT_CLEAR_GM_STUP_4_0(x) ((x) & (~BITS_GM_STUP_4_0))\n#define BIT_GET_GM_STUP_4_0(x)                                                 \\\n\t(((x) >> BIT_SHIFT_GM_STUP_4_0) & BIT_MASK_GM_STUP_4_0)\n#define BIT_SET_GM_STUP_4_0(x, v)                                              \\\n\t(BIT_CLEAR_GM_STUP_4_0(x) | BIT_GM_STUP_4_0(v))\n\n#define BIT_SHIFT_XTAL_CK_SET_2_0 13\n#define BIT_MASK_XTAL_CK_SET_2_0 0x7\n#define BIT_XTAL_CK_SET_2_0(x)                                                 \\\n\t(((x) & BIT_MASK_XTAL_CK_SET_2_0) << BIT_SHIFT_XTAL_CK_SET_2_0)\n#define BITS_XTAL_CK_SET_2_0                                                   \\\n\t(BIT_MASK_XTAL_CK_SET_2_0 << BIT_SHIFT_XTAL_CK_SET_2_0)\n#define BIT_CLEAR_XTAL_CK_SET_2_0(x) ((x) & (~BITS_XTAL_CK_SET_2_0))\n#define BIT_GET_XTAL_CK_SET_2_0(x)                                             \\\n\t(((x) >> BIT_SHIFT_XTAL_CK_SET_2_0) & BIT_MASK_XTAL_CK_SET_2_0)\n#define BIT_SET_XTAL_CK_SET_2_0(x, v)                                          \\\n\t(BIT_CLEAR_XTAL_CK_SET_2_0(x) | BIT_XTAL_CK_SET_2_0(v))\n\n#define BIT_SHIFT_GM_INIT_4_0 8\n#define BIT_MASK_GM_INIT_4_0 0x1f\n#define BIT_GM_INIT_4_0(x)                                                     \\\n\t(((x) & BIT_MASK_GM_INIT_4_0) << BIT_SHIFT_GM_INIT_4_0)\n#define BITS_GM_INIT_4_0 (BIT_MASK_GM_INIT_4_0 << BIT_SHIFT_GM_INIT_4_0)\n#define BIT_CLEAR_GM_INIT_4_0(x) ((x) & (~BITS_GM_INIT_4_0))\n#define BIT_GET_GM_INIT_4_0(x)                                                 \\\n\t(((x) >> BIT_SHIFT_GM_INIT_4_0) & BIT_MASK_GM_INIT_4_0)\n#define BIT_SET_GM_INIT_4_0(x, v)                                              \\\n\t(BIT_CLEAR_GM_INIT_4_0(x) | BIT_GM_INIT_4_0(v))\n\n#define BIT_SHIFT_XAAC_GM_OFFSET_4_0 2\n#define BIT_MASK_XAAC_GM_OFFSET_4_0 0x1f\n#define BIT_XAAC_GM_OFFSET_4_0(x)                                              \\\n\t(((x) & BIT_MASK_XAAC_GM_OFFSET_4_0) << BIT_SHIFT_XAAC_GM_OFFSET_4_0)\n#define BITS_XAAC_GM_OFFSET_4_0                                                \\\n\t(BIT_MASK_XAAC_GM_OFFSET_4_0 << BIT_SHIFT_XAAC_GM_OFFSET_4_0)\n#define BIT_CLEAR_XAAC_GM_OFFSET_4_0(x) ((x) & (~BITS_XAAC_GM_OFFSET_4_0))\n#define BIT_GET_XAAC_GM_OFFSET_4_0(x)                                          \\\n\t(((x) >> BIT_SHIFT_XAAC_GM_OFFSET_4_0) & BIT_MASK_XAAC_GM_OFFSET_4_0)\n#define BIT_SET_XAAC_GM_OFFSET_4_0(x, v)                                       \\\n\t(BIT_CLEAR_XAAC_GM_OFFSET_4_0(x) | BIT_XAAC_GM_OFFSET_4_0(v))\n\n/* 2 REG_ANAPAR_XTAL_R_ONLY\t\t\t(Offset 0x1050) */\n\n#define BIT_XTAL_PKDET_OUT BIT(6)\n\n#define BIT_SHIFT_XTAL_GM_AAC_4_0 1\n#define BIT_MASK_XTAL_GM_AAC_4_0 0x1f\n#define BIT_XTAL_GM_AAC_4_0(x)                                                 \\\n\t(((x) & BIT_MASK_XTAL_GM_AAC_4_0) << BIT_SHIFT_XTAL_GM_AAC_4_0)\n#define BITS_XTAL_GM_AAC_4_0                                                   \\\n\t(BIT_MASK_XTAL_GM_AAC_4_0 << BIT_SHIFT_XTAL_GM_AAC_4_0)\n#define BIT_CLEAR_XTAL_GM_AAC_4_0(x) ((x) & (~BITS_XTAL_GM_AAC_4_0))\n#define BIT_GET_XTAL_GM_AAC_4_0(x)                                             \\\n\t(((x) >> BIT_SHIFT_XTAL_GM_AAC_4_0) & BIT_MASK_XTAL_GM_AAC_4_0)\n#define BIT_SET_XTAL_GM_AAC_4_0(x, v)                                          \\\n\t(BIT_CLEAR_XTAL_GM_AAC_4_0(x) | BIT_XTAL_GM_AAC_4_0(v))\n\n#define BIT_XAAC_READY BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_AACK_0\t\t\t(Offset 0x1054) */\n\n#define BIT_XAAC_LPOW BIT(31)\n\n#define BIT_SHIFT_AAC_MODE 29\n#define BIT_MASK_AAC_MODE 0x3\n#define BIT_AAC_MODE(x) (((x) & BIT_MASK_AAC_MODE) << BIT_SHIFT_AAC_MODE)\n#define BITS_AAC_MODE (BIT_MASK_AAC_MODE << BIT_SHIFT_AAC_MODE)\n#define BIT_CLEAR_AAC_MODE(x) ((x) & (~BITS_AAC_MODE))\n#define BIT_GET_AAC_MODE(x) (((x) >> BIT_SHIFT_AAC_MODE) & BIT_MASK_AAC_MODE)\n#define BIT_SET_AAC_MODE(x, v) (BIT_CLEAR_AAC_MODE(x) | BIT_AAC_MODE(v))\n\n#define BIT_SHIFT_GM_MANUAL 21\n#define BIT_MASK_GM_MANUAL 0x1f\n#define BIT_GM_MANUAL(x) (((x) & BIT_MASK_GM_MANUAL) << BIT_SHIFT_GM_MANUAL)\n#define BITS_GM_MANUAL (BIT_MASK_GM_MANUAL << BIT_SHIFT_GM_MANUAL)\n#define BIT_CLEAR_GM_MANUAL(x) ((x) & (~BITS_GM_MANUAL))\n#define BIT_GET_GM_MANUAL(x) (((x) >> BIT_SHIFT_GM_MANUAL) & BIT_MASK_GM_MANUAL)\n#define BIT_SET_GM_MANUAL(x, v) (BIT_CLEAR_GM_MANUAL(x) | BIT_GM_MANUAL(v))\n\n#define BIT_SHIFT_XTAL_LDO_LPS 21\n#define BIT_MASK_XTAL_LDO_LPS 0x7\n#define BIT_XTAL_LDO_LPS(x)                                                    \\\n\t(((x) & BIT_MASK_XTAL_LDO_LPS) << BIT_SHIFT_XTAL_LDO_LPS)\n#define BITS_XTAL_LDO_LPS (BIT_MASK_XTAL_LDO_LPS << BIT_SHIFT_XTAL_LDO_LPS)\n#define BIT_CLEAR_XTAL_LDO_LPS(x) ((x) & (~BITS_XTAL_LDO_LPS))\n#define BIT_GET_XTAL_LDO_LPS(x)                                                \\\n\t(((x) >> BIT_SHIFT_XTAL_LDO_LPS) & BIT_MASK_XTAL_LDO_LPS)\n#define BIT_SET_XTAL_LDO_LPS(x, v)                                             \\\n\t(BIT_CLEAR_XTAL_LDO_LPS(x) | BIT_XTAL_LDO_LPS(v))\n\n#define BIT_SHIFT_GM_STUP 16\n#define BIT_MASK_GM_STUP 0x1f\n#define BIT_GM_STUP(x) (((x) & BIT_MASK_GM_STUP) << BIT_SHIFT_GM_STUP)\n#define BITS_GM_STUP (BIT_MASK_GM_STUP << BIT_SHIFT_GM_STUP)\n#define BIT_CLEAR_GM_STUP(x) ((x) & (~BITS_GM_STUP))\n#define BIT_GET_GM_STUP(x) (((x) >> BIT_SHIFT_GM_STUP) & BIT_MASK_GM_STUP)\n#define BIT_SET_GM_STUP(x, v) (BIT_CLEAR_GM_STUP(x) | BIT_GM_STUP(v))\n\n#define BIT_SHIFT_XTAL_WAIT_CYC 15\n#define BIT_MASK_XTAL_WAIT_CYC 0x3f\n#define BIT_XTAL_WAIT_CYC(x)                                                   \\\n\t(((x) & BIT_MASK_XTAL_WAIT_CYC) << BIT_SHIFT_XTAL_WAIT_CYC)\n#define BITS_XTAL_WAIT_CYC (BIT_MASK_XTAL_WAIT_CYC << BIT_SHIFT_XTAL_WAIT_CYC)\n#define BIT_CLEAR_XTAL_WAIT_CYC(x) ((x) & (~BITS_XTAL_WAIT_CYC))\n#define BIT_GET_XTAL_WAIT_CYC(x)                                               \\\n\t(((x) >> BIT_SHIFT_XTAL_WAIT_CYC) & BIT_MASK_XTAL_WAIT_CYC)\n#define BIT_SET_XTAL_WAIT_CYC(x, v)                                            \\\n\t(BIT_CLEAR_XTAL_WAIT_CYC(x) | BIT_XTAL_WAIT_CYC(v))\n\n#define BIT_SHIFT_XTAL_CK_SET 13\n#define BIT_MASK_XTAL_CK_SET 0x7\n#define BIT_XTAL_CK_SET(x)                                                     \\\n\t(((x) & BIT_MASK_XTAL_CK_SET) << BIT_SHIFT_XTAL_CK_SET)\n#define BITS_XTAL_CK_SET (BIT_MASK_XTAL_CK_SET << BIT_SHIFT_XTAL_CK_SET)\n#define BIT_CLEAR_XTAL_CK_SET(x) ((x) & (~BITS_XTAL_CK_SET))\n#define BIT_GET_XTAL_CK_SET(x)                                                 \\\n\t(((x) >> BIT_SHIFT_XTAL_CK_SET) & BIT_MASK_XTAL_CK_SET)\n#define BIT_SET_XTAL_CK_SET(x, v)                                              \\\n\t(BIT_CLEAR_XTAL_CK_SET(x) | BIT_XTAL_CK_SET(v))\n\n#define BIT_SHIFT_XTAL_LDO_OK 12\n#define BIT_MASK_XTAL_LDO_OK 0x7\n#define BIT_XTAL_LDO_OK(x)                                                     \\\n\t(((x) & BIT_MASK_XTAL_LDO_OK) << BIT_SHIFT_XTAL_LDO_OK)\n#define BITS_XTAL_LDO_OK (BIT_MASK_XTAL_LDO_OK << BIT_SHIFT_XTAL_LDO_OK)\n#define BIT_CLEAR_XTAL_LDO_OK(x) ((x) & (~BITS_XTAL_LDO_OK))\n#define BIT_GET_XTAL_LDO_OK(x)                                                 \\\n\t(((x) >> BIT_SHIFT_XTAL_LDO_OK) & BIT_MASK_XTAL_LDO_OK)\n#define BIT_SET_XTAL_LDO_OK(x, v)                                              \\\n\t(BIT_CLEAR_XTAL_LDO_OK(x) | BIT_XTAL_LDO_OK(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CPHY_LDO\t\t\t\t(Offset 0x1054) */\n\n#define BIT_SHIFT_CPHY_LDO_PD 12\n#define BIT_MASK_CPHY_LDO_PD 0x3\n#define BIT_CPHY_LDO_PD(x)                                                     \\\n\t(((x) & BIT_MASK_CPHY_LDO_PD) << BIT_SHIFT_CPHY_LDO_PD)\n#define BITS_CPHY_LDO_PD (BIT_MASK_CPHY_LDO_PD << BIT_SHIFT_CPHY_LDO_PD)\n#define BIT_CLEAR_CPHY_LDO_PD(x) ((x) & (~BITS_CPHY_LDO_PD))\n#define BIT_GET_CPHY_LDO_PD(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CPHY_LDO_PD) & BIT_MASK_CPHY_LDO_PD)\n#define BIT_SET_CPHY_LDO_PD(x, v)                                              \\\n\t(BIT_CLEAR_CPHY_LDO_PD(x) | BIT_CPHY_LDO_PD(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_AACK_0\t\t\t(Offset 0x1054) */\n\n#define BIT_XTAL_MD_LPOW BIT(11)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CPHY_LDO\t\t\t\t(Offset 0x1054) */\n\n#define BIT_SHIFT_CPHY_LDO_SR 10\n#define BIT_MASK_CPHY_LDO_SR 0x3\n#define BIT_CPHY_LDO_SR(x)                                                     \\\n\t(((x) & BIT_MASK_CPHY_LDO_SR) << BIT_SHIFT_CPHY_LDO_SR)\n#define BITS_CPHY_LDO_SR (BIT_MASK_CPHY_LDO_SR << BIT_SHIFT_CPHY_LDO_SR)\n#define BIT_CLEAR_CPHY_LDO_SR(x) ((x) & (~BITS_CPHY_LDO_SR))\n#define BIT_GET_CPHY_LDO_SR(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CPHY_LDO_SR) & BIT_MASK_CPHY_LDO_SR)\n#define BIT_SET_CPHY_LDO_SR(x, v)                                              \\\n\t(BIT_CLEAR_CPHY_LDO_SR(x) | BIT_CPHY_LDO_SR(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_AACK_0\t\t\t(Offset 0x1054) */\n\n#define BIT_SHIFT_XTAL_OV_RATIO 9\n#define BIT_MASK_XTAL_OV_RATIO 0x3\n#define BIT_XTAL_OV_RATIO(x)                                                   \\\n\t(((x) & BIT_MASK_XTAL_OV_RATIO) << BIT_SHIFT_XTAL_OV_RATIO)\n#define BITS_XTAL_OV_RATIO (BIT_MASK_XTAL_OV_RATIO << BIT_SHIFT_XTAL_OV_RATIO)\n#define BIT_CLEAR_XTAL_OV_RATIO(x) ((x) & (~BITS_XTAL_OV_RATIO))\n#define BIT_GET_XTAL_OV_RATIO(x)                                               \\\n\t(((x) >> BIT_SHIFT_XTAL_OV_RATIO) & BIT_MASK_XTAL_OV_RATIO)\n#define BIT_SET_XTAL_OV_RATIO(x, v)                                            \\\n\t(BIT_CLEAR_XTAL_OV_RATIO(x) | BIT_XTAL_OV_RATIO(v))\n\n#define BIT_SHIFT_GM_INIT 8\n#define BIT_MASK_GM_INIT 0x1f\n#define BIT_GM_INIT(x) (((x) & BIT_MASK_GM_INIT) << BIT_SHIFT_GM_INIT)\n#define BITS_GM_INIT (BIT_MASK_GM_INIT << BIT_SHIFT_GM_INIT)\n#define BIT_CLEAR_GM_INIT(x) ((x) & (~BITS_GM_INIT))\n#define BIT_GET_GM_INIT(x) (((x) >> BIT_SHIFT_GM_INIT) & BIT_MASK_GM_INIT)\n#define BIT_SET_GM_INIT(x, v) (BIT_CLEAR_GM_INIT(x) | BIT_GM_INIT(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CPHY_LDO\t\t\t\t(Offset 0x1054) */\n\n#define BIT_SHIFT_CPHY_LDO_TUNEREF 8\n#define BIT_MASK_CPHY_LDO_TUNEREF 0x3\n#define BIT_CPHY_LDO_TUNEREF(x)                                                \\\n\t(((x) & BIT_MASK_CPHY_LDO_TUNEREF) << BIT_SHIFT_CPHY_LDO_TUNEREF)\n#define BITS_CPHY_LDO_TUNEREF                                                  \\\n\t(BIT_MASK_CPHY_LDO_TUNEREF << BIT_SHIFT_CPHY_LDO_TUNEREF)\n#define BIT_CLEAR_CPHY_LDO_TUNEREF(x) ((x) & (~BITS_CPHY_LDO_TUNEREF))\n#define BIT_GET_CPHY_LDO_TUNEREF(x)                                            \\\n\t(((x) >> BIT_SHIFT_CPHY_LDO_TUNEREF) & BIT_MASK_CPHY_LDO_TUNEREF)\n#define BIT_SET_CPHY_LDO_TUNEREF(x, v)                                         \\\n\t(BIT_CLEAR_CPHY_LDO_TUNEREF(x) | BIT_CPHY_LDO_TUNEREF(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_AACK_0\t\t\t(Offset 0x1054) */\n\n#define BIT_SHIFT_XTAL_OV_UNIT 6\n#define BIT_MASK_XTAL_OV_UNIT 0x7\n#define BIT_XTAL_OV_UNIT(x)                                                    \\\n\t(((x) & BIT_MASK_XTAL_OV_UNIT) << BIT_SHIFT_XTAL_OV_UNIT)\n#define BITS_XTAL_OV_UNIT (BIT_MASK_XTAL_OV_UNIT << BIT_SHIFT_XTAL_OV_UNIT)\n#define BIT_CLEAR_XTAL_OV_UNIT(x) ((x) & (~BITS_XTAL_OV_UNIT))\n#define BIT_GET_XTAL_OV_UNIT(x)                                                \\\n\t(((x) >> BIT_SHIFT_XTAL_OV_UNIT) & BIT_MASK_XTAL_OV_UNIT)\n#define BIT_SET_XTAL_OV_UNIT(x, v)                                             \\\n\t(BIT_CLEAR_XTAL_OV_UNIT(x) | BIT_XTAL_OV_UNIT(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CPHY_LDO\t\t\t\t(Offset 0x1054) */\n\n#define BIT_SHIFT_CPHY_LDO_TUNE_VO 5\n#define BIT_MASK_CPHY_LDO_TUNE_VO 0x7\n#define BIT_CPHY_LDO_TUNE_VO(x)                                                \\\n\t(((x) & BIT_MASK_CPHY_LDO_TUNE_VO) << BIT_SHIFT_CPHY_LDO_TUNE_VO)\n#define BITS_CPHY_LDO_TUNE_VO                                                  \\\n\t(BIT_MASK_CPHY_LDO_TUNE_VO << BIT_SHIFT_CPHY_LDO_TUNE_VO)\n#define BIT_CLEAR_CPHY_LDO_TUNE_VO(x) ((x) & (~BITS_CPHY_LDO_TUNE_VO))\n#define BIT_GET_CPHY_LDO_TUNE_VO(x)                                            \\\n\t(((x) >> BIT_SHIFT_CPHY_LDO_TUNE_VO) & BIT_MASK_CPHY_LDO_TUNE_VO)\n#define BIT_SET_CPHY_LDO_TUNE_VO(x, v)                                         \\\n\t(BIT_CLEAR_CPHY_LDO_TUNE_VO(x) | BIT_CPHY_LDO_TUNE_VO(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_AACK_0\t\t\t(Offset 0x1054) */\n\n#define BIT_SHIFT_XTAL_MODE_MANUAL 4\n#define BIT_MASK_XTAL_MODE_MANUAL 0x3\n#define BIT_XTAL_MODE_MANUAL(x)                                                \\\n\t(((x) & BIT_MASK_XTAL_MODE_MANUAL) << BIT_SHIFT_XTAL_MODE_MANUAL)\n#define BITS_XTAL_MODE_MANUAL                                                  \\\n\t(BIT_MASK_XTAL_MODE_MANUAL << BIT_SHIFT_XTAL_MODE_MANUAL)\n#define BIT_CLEAR_XTAL_MODE_MANUAL(x) ((x) & (~BITS_XTAL_MODE_MANUAL))\n#define BIT_GET_XTAL_MODE_MANUAL(x)                                            \\\n\t(((x) >> BIT_SHIFT_XTAL_MODE_MANUAL) & BIT_MASK_XTAL_MODE_MANUAL)\n#define BIT_SET_XTAL_MODE_MANUAL(x, v)                                         \\\n\t(BIT_CLEAR_XTAL_MODE_MANUAL(x) | BIT_XTAL_MODE_MANUAL(v))\n\n#define BIT_SHIFT_PK_END_AR 3\n#define BIT_MASK_PK_END_AR 0x3\n#define BIT_PK_END_AR(x) (((x) & BIT_MASK_PK_END_AR) << BIT_SHIFT_PK_END_AR)\n#define BITS_PK_END_AR (BIT_MASK_PK_END_AR << BIT_SHIFT_PK_END_AR)\n#define BIT_CLEAR_PK_END_AR(x) ((x) & (~BITS_PK_END_AR))\n#define BIT_GET_PK_END_AR(x) (((x) >> BIT_SHIFT_PK_END_AR) & BIT_MASK_PK_END_AR)\n#define BIT_SET_PK_END_AR(x, v) (BIT_CLEAR_PK_END_AR(x) | BIT_PK_END_AR(v))\n\n#define BIT_XTAL_MANU_SEL BIT(3)\n\n#define BIT_SHIFT_XAAC_GM_OFFSET 2\n#define BIT_MASK_XAAC_GM_OFFSET 0x1f\n#define BIT_XAAC_GM_OFFSET(x)                                                  \\\n\t(((x) & BIT_MASK_XAAC_GM_OFFSET) << BIT_SHIFT_XAAC_GM_OFFSET)\n#define BITS_XAAC_GM_OFFSET                                                    \\\n\t(BIT_MASK_XAAC_GM_OFFSET << BIT_SHIFT_XAAC_GM_OFFSET)\n#define BIT_CLEAR_XAAC_GM_OFFSET(x) ((x) & (~BITS_XAAC_GM_OFFSET))\n#define BIT_GET_XAAC_GM_OFFSET(x)                                              \\\n\t(((x) >> BIT_SHIFT_XAAC_GM_OFFSET) & BIT_MASK_XAAC_GM_OFFSET)\n#define BIT_SET_XAAC_GM_OFFSET(x, v)                                           \\\n\t(BIT_CLEAR_XAAC_GM_OFFSET(x) | BIT_XAAC_GM_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CPHY_LDO\t\t\t\t(Offset 0x1054) */\n\n#define BIT_SHIFT_CPHY_LDO_OCP_VTH 2\n#define BIT_MASK_CPHY_LDO_OCP_VTH 0x7\n#define BIT_CPHY_LDO_OCP_VTH(x)                                                \\\n\t(((x) & BIT_MASK_CPHY_LDO_OCP_VTH) << BIT_SHIFT_CPHY_LDO_OCP_VTH)\n#define BITS_CPHY_LDO_OCP_VTH                                                  \\\n\t(BIT_MASK_CPHY_LDO_OCP_VTH << BIT_SHIFT_CPHY_LDO_OCP_VTH)\n#define BIT_CLEAR_CPHY_LDO_OCP_VTH(x) ((x) & (~BITS_CPHY_LDO_OCP_VTH))\n#define BIT_GET_CPHY_LDO_OCP_VTH(x)                                            \\\n\t(((x) >> BIT_SHIFT_CPHY_LDO_OCP_VTH) & BIT_MASK_CPHY_LDO_OCP_VTH)\n#define BIT_SET_CPHY_LDO_OCP_VTH(x, v)                                         \\\n\t(BIT_CLEAR_CPHY_LDO_OCP_VTH(x) | BIT_CPHY_LDO_OCP_VTH(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_ANAPAR_XTAL_AACK_0\t\t\t(Offset 0x1054) */\n\n#define BIT_SHIFT_PK_START_AR 1\n#define BIT_MASK_PK_START_AR 0x3\n#define BIT_PK_START_AR(x)                                                     \\\n\t(((x) & BIT_MASK_PK_START_AR) << BIT_SHIFT_PK_START_AR)\n#define BITS_PK_START_AR (BIT_MASK_PK_START_AR << BIT_SHIFT_PK_START_AR)\n#define BIT_CLEAR_PK_START_AR(x) ((x) & (~BITS_PK_START_AR))\n#define BIT_GET_PK_START_AR(x)                                                 \\\n\t(((x) >> BIT_SHIFT_PK_START_AR) & BIT_MASK_PK_START_AR)\n#define BIT_SET_PK_START_AR(x, v)                                              \\\n\t(BIT_CLEAR_PK_START_AR(x) | BIT_PK_START_AR(v))\n\n#define BIT_XTAL_MODE BIT(1)\n#define BIT_XAAC_LUT_MANUAL_EN BIT(0)\n#define BIT_RESET_N_DECODER BIT(0)\n\n#endif\n\n#if (HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WLRF1\t\t\t\t(Offset 0x00EC) */\n#define BIT_XAAC_READY_V1\t\t\t\tBIT(7)\n#define BIT_SHIFT_XAAC_PK_SEL\t\t\t\t5\n#define BIT_MASK_XAAC_PK_SEL\t\t\t\t0x3\n#define BIT_XAAC_PK_SEL(x)                                                     \\\n\t(((x) & BIT_MASK_XAAC_PK_SEL) << BIT_SHIFT_XAAC_PK_SEL)\n#define BITS_XAAC_PK_SEL (BIT_MASK_XAAC_PK_SEL << BIT_SHIFT_XAAC_PK_SEL)\n#define BIT_CLEAR_XAAC_PK_SEL(x) ((x) & (~BITS_XAAC_PK_SEL))\n#define BIT_GET_XAAC_PK_SEL(x)                                                 \\\n\t(((x) >> BIT_SHIFT_XAAC_PK_SEL) & BIT_MASK_XAAC_PK_SEL)\n#define BIT_SET_XAAC_PK_SEL(x, v)                                              \\\n\t(BIT_CLEAR_XAAC_PK_SEL(x) | BIT_XAAC_PK_SEL(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CPHY_LDO\t\t\t\t(Offset 0x1054) */\n\n#define BIT_SHIFT_VREF_LDO_OK 0\n#define BIT_MASK_VREF_LDO_OK 0x3\n#define BIT_VREF_LDO_OK(x)                                                     \\\n\t(((x) & BIT_MASK_VREF_LDO_OK) << BIT_SHIFT_VREF_LDO_OK)\n#define BITS_VREF_LDO_OK (BIT_MASK_VREF_LDO_OK << BIT_SHIFT_VREF_LDO_OK)\n#define BIT_CLEAR_VREF_LDO_OK(x) ((x) & (~BITS_VREF_LDO_OK))\n#define BIT_GET_VREF_LDO_OK(x)                                                 \\\n\t(((x) >> BIT_SHIFT_VREF_LDO_OK) & BIT_MASK_VREF_LDO_OK)\n#define BIT_SET_VREF_LDO_OK(x, v)                                              \\\n\t(BIT_CLEAR_VREF_LDO_OK(x) | BIT_VREF_LDO_OK(v))\n\n/* 2 REG_CPHY_BG\t\t\t\t(Offset 0x1058) */\n\n#define BIT_TXBCN_OK_PORT4 BIT(31)\n#define BIT_ATIMEND_PORT4 BIT(31)\n#define BIT_TXBCN_OK_PORT3 BIT(30)\n#define BIT_ATIMEND_PORT3 BIT(30)\n#define BIT_TXBCN_OK_PORT2 BIT(29)\n#define BIT_ATIMEND_PORT2 BIT(29)\n#define BIT_TXBCN_OK_PORT1 BIT(28)\n#define BIT_ATIMEND_PORT1 BIT(28)\n#define BIT_TXBCN15OK BIT(23)\n#define BIT_BCNDMAINT15 BIT(23)\n#define BIT_ATIMEND15 BIT(23)\n#define BIT_TXBCN14OK BIT(22)\n#define BIT_BCNDMAINT14 BIT(22)\n#define BIT_ATIMEND14 BIT(22)\n#define BIT_TXBCN13OK BIT(21)\n#define BIT_BCNDMAINT13 BIT(21)\n#define BIT_ATIMEND13 BIT(21)\n#define BIT_TXBCN12OK BIT(20)\n#define BIT_BCNDMAINT12 BIT(20)\n#define BIT_ATIMEND12 BIT(20)\n#define BIT_TXBCN11OK BIT(19)\n#define BIT_BCNDMAINT11 BIT(19)\n#define BIT_ATIMEND11 BIT(19)\n#define BIT_TXBCN10OK BIT(18)\n#define BIT_BCNDMAINT10 BIT(18)\n#define BIT_ATIMEND10 BIT(18)\n#define BIT_TXBCN9OK BIT(17)\n#define BIT_BCNDMAINT9 BIT(17)\n#define BIT_ATIMEND9 BIT(17)\n#define BIT_TXBCN8OK BIT(16)\n#define BIT_BCNDMAINT8 BIT(16)\n#define BIT_ATIMEND8 BIT(16)\n#define BIT_BCNDERR_PORT4 BIT(15)\n#define BIT_BCNDERR_PORT3 BIT(14)\n#define BIT_BCNDERR_PORT2 BIT(13)\n#define BIT_BCNDERR_PORT1 BIT(12)\n#define BIT_TXBCN15ERR BIT(7)\n#define BIT_BCNDERR15 BIT(7)\n#define BIT_TXBCN14ERR BIT(6)\n#define BIT_BCNDERR14 BIT(6)\n#define BIT_TXBCN13ERR BIT(5)\n#define BIT_BCNDERR13 BIT(5)\n#define BIT_PS_TIMER_EARLY_INT_5 BIT(5)\n#define BIT_TXBCN12ERR BIT(4)\n#define BIT_BCNDERR12 BIT(4)\n#define BIT_PS_TIMER_EARLY_INT_4 BIT(4)\n#define BIT_TXBCN11ERR BIT(3)\n#define BIT_BCNDERR11 BIT(3)\n#define BIT_PS_TIMER_EARLY_INT_3 BIT(3)\n#define BIT_TXBCN10ERR BIT(2)\n#define BIT_BCNDERR10 BIT(2)\n#define BIT_PS_TIMER_EARLY_INT_2 BIT(2)\n#define BIT_TXBCN9ERR BIT(1)\n#define BIT_BCNDERR9 BIT(1)\n#define BIT_PS_TIMER_EARLY_INT_1 BIT(1)\n\n#define BIT_SHIFT_BG 0\n#define BIT_MASK_BG 0x7\n#define BIT_BG(x) (((x) & BIT_MASK_BG) << BIT_SHIFT_BG)\n#define BITS_BG (BIT_MASK_BG << BIT_SHIFT_BG)\n#define BIT_CLEAR_BG(x) ((x) & (~BITS_BG))\n#define BIT_GET_BG(x) (((x) >> BIT_SHIFT_BG) & BIT_MASK_BG)\n#define BIT_SET_BG(x, v) (BIT_CLEAR_BG(x) | BIT_BG(v))\n\n#define BIT_TXBCN8ERR BIT(0)\n#define BIT_BCNDERR8 BIT(0)\n#define BIT_PS_TIMER_EARLY_INT_0 BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SYS_CFG5\t\t\t\t(Offset 0x1070) */\n\n#define BIT_LPS_STATUS BIT(3)\n#define BIT_HCI_TXDMA_BUSY BIT(2)\n#define BIT_HCI_TXDMA_ALLOW BIT(1)\n#define BIT_FW_CTRL_HCI_TXDMA_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n/* 2 REG_REGU_32K_1\t\t\t\t(Offset 0x1078) */\n\n#define BIT_OUT_SEL BIT(26)\n\n#define BIT_SHIFT_FREQ_SEL 24\n#define BIT_MASK_FREQ_SEL 0x3\n#define BIT_FREQ_SEL(x) (((x) & BIT_MASK_FREQ_SEL) << BIT_SHIFT_FREQ_SEL)\n#define BITS_FREQ_SEL (BIT_MASK_FREQ_SEL << BIT_SHIFT_FREQ_SEL)\n#define BIT_CLEAR_FREQ_SEL(x) ((x) & (~BITS_FREQ_SEL))\n#define BIT_GET_FREQ_SEL(x) (((x) >> BIT_SHIFT_FREQ_SEL) & BIT_MASK_FREQ_SEL)\n#define BIT_SET_FREQ_SEL(x, v) (BIT_CLEAR_FREQ_SEL(x) | BIT_FREQ_SEL(v))\n\n#define BIT_SHIFT_CLKGEN0 16\n#define BIT_MASK_CLKGEN0 0xff\n#define BIT_CLKGEN0(x) (((x) & BIT_MASK_CLKGEN0) << BIT_SHIFT_CLKGEN0)\n#define BITS_CLKGEN0 (BIT_MASK_CLKGEN0 << BIT_SHIFT_CLKGEN0)\n#define BIT_CLEAR_CLKGEN0(x) ((x) & (~BITS_CLKGEN0))\n#define BIT_GET_CLKGEN0(x) (((x) >> BIT_SHIFT_CLKGEN0) & BIT_MASK_CLKGEN0)\n#define BIT_SET_CLKGEN0(x, v) (BIT_CLEAR_CLKGEN0(x) | BIT_CLKGEN0(v))\n\n#define BIT_SHIFT_TEMP_COMP 12\n#define BIT_MASK_TEMP_COMP 0xf\n#define BIT_TEMP_COMP(x) (((x) & BIT_MASK_TEMP_COMP) << BIT_SHIFT_TEMP_COMP)\n#define BITS_TEMP_COMP (BIT_MASK_TEMP_COMP << BIT_SHIFT_TEMP_COMP)\n#define BIT_CLEAR_TEMP_COMP(x) ((x) & (~BITS_TEMP_COMP))\n#define BIT_GET_TEMP_COMP(x) (((x) >> BIT_SHIFT_TEMP_COMP) & BIT_MASK_TEMP_COMP)\n#define BIT_SET_TEMP_COMP(x, v) (BIT_CLEAR_TEMP_COMP(x) | BIT_TEMP_COMP(v))\n\n#define BIT_SHIFT_LDO_V18ADJ 8\n#define BIT_MASK_LDO_V18ADJ 0xf\n#define BIT_LDO_V18ADJ(x) (((x) & BIT_MASK_LDO_V18ADJ) << BIT_SHIFT_LDO_V18ADJ)\n#define BITS_LDO_V18ADJ (BIT_MASK_LDO_V18ADJ << BIT_SHIFT_LDO_V18ADJ)\n#define BIT_CLEAR_LDO_V18ADJ(x) ((x) & (~BITS_LDO_V18ADJ))\n#define BIT_GET_LDO_V18ADJ(x)                                                  \\\n\t(((x) >> BIT_SHIFT_LDO_V18ADJ) & BIT_MASK_LDO_V18ADJ)\n#define BIT_SET_LDO_V18ADJ(x, v) (BIT_CLEAR_LDO_V18ADJ(x) | BIT_LDO_V18ADJ(v))\n\n#define BIT_SHIFT_COMP_LOAD_CUR 5\n#define BIT_MASK_COMP_LOAD_CUR 0x3\n#define BIT_COMP_LOAD_CUR(x)                                                   \\\n\t(((x) & BIT_MASK_COMP_LOAD_CUR) << BIT_SHIFT_COMP_LOAD_CUR)\n#define BITS_COMP_LOAD_CUR (BIT_MASK_COMP_LOAD_CUR << BIT_SHIFT_COMP_LOAD_CUR)\n#define BIT_CLEAR_COMP_LOAD_CUR(x) ((x) & (~BITS_COMP_LOAD_CUR))\n#define BIT_GET_COMP_LOAD_CUR(x)                                               \\\n\t(((x) >> BIT_SHIFT_COMP_LOAD_CUR) & BIT_MASK_COMP_LOAD_CUR)\n#define BIT_SET_COMP_LOAD_CUR(x, v)                                            \\\n\t(BIT_CLEAR_COMP_LOAD_CUR(x) | BIT_COMP_LOAD_CUR(v))\n\n#define BIT_SHIFT_COMP_LATCH_CUR 3\n#define BIT_MASK_COMP_LATCH_CUR 0x3\n#define BIT_COMP_LATCH_CUR(x)                                                  \\\n\t(((x) & BIT_MASK_COMP_LATCH_CUR) << BIT_SHIFT_COMP_LATCH_CUR)\n#define BITS_COMP_LATCH_CUR                                                    \\\n\t(BIT_MASK_COMP_LATCH_CUR << BIT_SHIFT_COMP_LATCH_CUR)\n#define BIT_CLEAR_COMP_LATCH_CUR(x) ((x) & (~BITS_COMP_LATCH_CUR))\n#define BIT_GET_COMP_LATCH_CUR(x)                                              \\\n\t(((x) >> BIT_SHIFT_COMP_LATCH_CUR) & BIT_MASK_COMP_LATCH_CUR)\n#define BIT_SET_COMP_LATCH_CUR(x, v)                                           \\\n\t(BIT_CLEAR_COMP_LATCH_CUR(x) | BIT_COMP_LATCH_CUR(v))\n\n#define BIT_SHIFT_COMP_GM_CUR 1\n#define BIT_MASK_COMP_GM_CUR 0x3\n#define BIT_COMP_GM_CUR(x)                                                     \\\n\t(((x) & BIT_MASK_COMP_GM_CUR) << BIT_SHIFT_COMP_GM_CUR)\n#define BITS_COMP_GM_CUR (BIT_MASK_COMP_GM_CUR << BIT_SHIFT_COMP_GM_CUR)\n#define BIT_CLEAR_COMP_GM_CUR(x) ((x) & (~BITS_COMP_GM_CUR))\n#define BIT_GET_COMP_GM_CUR(x)                                                 \\\n\t(((x) >> BIT_SHIFT_COMP_GM_CUR) & BIT_MASK_COMP_GM_CUR)\n#define BIT_SET_COMP_GM_CUR(x, v)                                              \\\n\t(BIT_CLEAR_COMP_GM_CUR(x) | BIT_COMP_GM_CUR(v))\n\n/* 2 REG_REGU_32K_2\t\t\t\t(Offset 0x107C) */\n\n#define BIT_SEL_RCAL_SOURCE BIT(16)\n\n#define BIT_SHIFT_RCAL 0\n#define BIT_MASK_RCAL 0x3f\n#define BIT_RCAL(x) (((x) & BIT_MASK_RCAL) << BIT_SHIFT_RCAL)\n#define BITS_RCAL (BIT_MASK_RCAL << BIT_SHIFT_RCAL)\n#define BIT_CLEAR_RCAL(x) ((x) & (~BITS_RCAL))\n#define BIT_GET_RCAL(x) (((x) >> BIT_SHIFT_RCAL) & BIT_MASK_RCAL)\n#define BIT_SET_RCAL(x, v) (BIT_CLEAR_RCAL(x) | BIT_RCAL(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CPU_DMEM_CON\t\t\t(Offset 0x1080) */\n\n#define BIT_SCH_PHY_TXOP_SIFS_INT BIT(23)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CPU_DMEM_CON\t\t\t(Offset 0x1080) */\n\n#define BIT_WDT_AUTO_MODE BIT(22)\n#define BIT_WDT_PLATFORM_EN BIT(21)\n#define BIT_WDT_CPU_EN BIT(20)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CPU_DMEM_CON\t\t\t(Offset 0x1080) */\n\n#define BIT_WDT_OPT_IOWRAPPER BIT(19)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CPU_DMEM_CON\t\t\t(Offset 0x1080) */\n\n#define BIT_ANA_PORT_IDLE BIT(18)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_CPU_DMEM_CON\t\t\t(Offset 0x1080) */\n\n#define BIT_TEST_EPHY_BY_REG BIT(17)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CPU_DMEM_CON\t\t\t(Offset 0x1080) */\n\n#define BIT_MAC_PORT_IDLE BIT(17)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_CPU_DMEM_CON\t\t\t(Offset 0x1080) */\n\n#define BIT_SYM_FEN_WLPLT BIT(16)\n#define BIT_TEST_UPHY_BY_REG BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CPU_DMEM_CON\t\t\t(Offset 0x1080) */\n\n#define BIT_WL_PLATFORM_RST BIT(16)\n#define BIT_WL_SECURITY_CLK BIT(15)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CPU_DMEM_CON\t\t\t(Offset 0x1080) */\n\n#define BIT_DDMA_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_CPU_DMEM_CON\t\t\t(Offset 0x1080) */\n\n#define BIT_UPHY_SLB_HW_PRD BIT(7)\n#define BIT_UPHY_FS_SLB_OK BIT(6)\n#define BIT_UPHY_HS_SLB_OK BIT(5)\n#define BIT_UPHY_SLB_CMD BIT(4)\n#define BIT_UPHY_SLB_FAIL BIT(3)\n#define BIT_UPHY_SLB_DONE BIT(2)\n#define BIT_UPHY_FORCE_SLB BIT(1)\n\n#define BIT_SHIFT_SYM_CPU_DMEN_CON 0\n#define BIT_MASK_SYM_CPU_DMEN_CON 0xff\n#define BIT_SYM_CPU_DMEN_CON(x)                                                \\\n\t(((x) & BIT_MASK_SYM_CPU_DMEN_CON) << BIT_SHIFT_SYM_CPU_DMEN_CON)\n#define BITS_SYM_CPU_DMEN_CON                                                  \\\n\t(BIT_MASK_SYM_CPU_DMEN_CON << BIT_SHIFT_SYM_CPU_DMEN_CON)\n#define BIT_CLEAR_SYM_CPU_DMEN_CON(x) ((x) & (~BITS_SYM_CPU_DMEN_CON))\n#define BIT_GET_SYM_CPU_DMEN_CON(x)                                            \\\n\t(((x) >> BIT_SHIFT_SYM_CPU_DMEN_CON) & BIT_MASK_SYM_CPU_DMEN_CON)\n#define BIT_SET_SYM_CPU_DMEN_CON(x, v)                                         \\\n\t(BIT_CLEAR_SYM_CPU_DMEN_CON(x) | BIT_SYM_CPU_DMEN_CON(v))\n\n#define BIT_UPHY_SLB_HS BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CPU_DMEM_CON\t\t\t(Offset 0x1080) */\n\n#define BIT_SHIFT_CPU_DMEM_CON 0\n#define BIT_MASK_CPU_DMEM_CON 0xff\n#define BIT_CPU_DMEM_CON(x)                                                    \\\n\t(((x) & BIT_MASK_CPU_DMEM_CON) << BIT_SHIFT_CPU_DMEM_CON)\n#define BITS_CPU_DMEM_CON (BIT_MASK_CPU_DMEM_CON << BIT_SHIFT_CPU_DMEM_CON)\n#define BIT_CLEAR_CPU_DMEM_CON(x) ((x) & (~BITS_CPU_DMEM_CON))\n#define BIT_GET_CPU_DMEM_CON(x)                                                \\\n\t(((x) >> BIT_SHIFT_CPU_DMEM_CON) & BIT_MASK_CPU_DMEM_CON)\n#define BIT_SET_CPU_DMEM_CON(x, v)                                             \\\n\t(BIT_CLEAR_CPU_DMEM_CON(x) | BIT_CPU_DMEM_CON(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BOOT_REASON\t\t\t\t(Offset 0x1088) */\n\n#define BIT_SHIFT_BOOT_REASON_V1 0\n#define BIT_MASK_BOOT_REASON_V1 0x7\n#define BIT_BOOT_REASON_V1(x)                                                  \\\n\t(((x) & BIT_MASK_BOOT_REASON_V1) << BIT_SHIFT_BOOT_REASON_V1)\n#define BITS_BOOT_REASON_V1                                                    \\\n\t(BIT_MASK_BOOT_REASON_V1 << BIT_SHIFT_BOOT_REASON_V1)\n#define BIT_CLEAR_BOOT_REASON_V1(x) ((x) & (~BITS_BOOT_REASON_V1))\n#define BIT_GET_BOOT_REASON_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_BOOT_REASON_V1) & BIT_MASK_BOOT_REASON_V1)\n#define BIT_SET_BOOT_REASON_V1(x, v)                                           \\\n\t(BIT_CLEAR_BOOT_REASON_V1(x) | BIT_BOOT_REASON_V1(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HIMR4\t\t\t\t(Offset 0x1090) */\n\n#define BIT_ATIM_END_INT16_MSK BIT(32)\n#define BIT_ATIM_END_INT15_MSK BIT(31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATA_CPU_CTL0\t\t\t(Offset 0x1090) */\n\n#define BIT_DATA_FW_READY BIT(31)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HIMR4\t\t\t\t(Offset 0x1090) */\n\n#define BIT_ATIM_END_INT14_MSK BIT(30)\n#define BIT_ATIM_END_INT13_MSK BIT(29)\n#define BIT_ATIM_END_INT12_MSK BIT(28)\n#define BIT_ATIM_END_INT11_MSK BIT(27)\n#define BIT_ATIM_END_INT10_MSK BIT(26)\n#define BIT_ATIM_END_INT9_MSK BIT(25)\n#define BIT_ATIM_END_INT8_MSK BIT(24)\n#define BIT_TX_BCN_ERR_INT15_MSK BIT(23)\n#define BIT_TX_BCN_ERR_INT14_MSK BIT(22)\n#define BIT_TX_BCN_ERR_INT13_MSK BIT(21)\n#define BIT_TX_BCN_ERR_INT12_MSK BIT(20)\n#define BIT_TX_BCN_ERR_INT11_MSK BIT(19)\n#define BIT_TX_BCN_ERR_INT10_MSK BIT(18)\n#define BIT_TX_BCN_ERR_INT9_MSK BIT(17)\n#define BIT_TX_BCN_ERR_INT8_MSK BIT(16)\n#define BIT_TX_BCN_OK_INT15_MSK BIT(15)\n#define BIT_TX_BCN_OK_INT14_MSK BIT(14)\n#define BIT_TX_BCN_OK_INT13_MSK BIT(13)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATA_CPU_CTL0\t\t\t(Offset 0x1090) */\n\n#define BIT_WDT_SYS_RST BIT(13)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HIMR4\t\t\t\t(Offset 0x1090) */\n\n#define BIT_TX_BCN_OK_INT12_MSK BIT(12)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATA_CPU_CTL0\t\t\t(Offset 0x1090) */\n\n#define BIT_WDT_ENABLE BIT(12)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HIMR4\t\t\t\t(Offset 0x1090) */\n\n#define BIT_TX_BCN_OK_INT11_MSK BIT(11)\n#define BIT_TX_BCN_OK_INT10_MSK BIT(10)\n#define BIT_TX_BCN_OK_INT9_MSK BIT(9)\n#define BIT_TX_BCN_OK_INT8_MSK BIT(8)\n#define BIT_BCN_DMA_INT15_MSK BIT(7)\n#define BIT_BCN_DMA_INT14_MSK BIT(6)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATA_CPU_CTL0\t\t\t(Offset 0x1090) */\n\n#define BIT_SHIFT_BOOT_SEL 6\n#define BIT_MASK_BOOT_SEL 0x3\n#define BIT_BOOT_SEL(x) (((x) & BIT_MASK_BOOT_SEL) << BIT_SHIFT_BOOT_SEL)\n#define BITS_BOOT_SEL (BIT_MASK_BOOT_SEL << BIT_SHIFT_BOOT_SEL)\n#define BIT_CLEAR_BOOT_SEL(x) ((x) & (~BITS_BOOT_SEL))\n#define BIT_GET_BOOT_SEL(x) (((x) >> BIT_SHIFT_BOOT_SEL) & BIT_MASK_BOOT_SEL)\n#define BIT_SET_BOOT_SEL(x, v) (BIT_CLEAR_BOOT_SEL(x) | BIT_BOOT_SEL(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HIMR4\t\t\t\t(Offset 0x1090) */\n\n#define BIT_BCN_DMA_INT13_MSK BIT(5)\n#define BIT_BCN_DMA_INT12_MSK BIT(4)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATA_CPU_CTL0\t\t\t(Offset 0x1090) */\n\n#define BIT_CLK_SEL BIT(4)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HIMR4\t\t\t\t(Offset 0x1090) */\n\n#define BIT_BCN_DMA_INT11_MSK BIT(3)\n#define BIT_BCN_DMA_INT10_MSK BIT(2)\n#define BIT_BCN_DMA_INT9_MSK BIT(1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATA_CPU_CTL0\t\t\t(Offset 0x1090) */\n\n#define BIT_DATA_PLATFORM_RST BIT(1)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HIMR4\t\t\t\t(Offset 0x1090) */\n\n#define BIT_BCN_DMA_INT8_MSK BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATA_CPU_CTL0\t\t\t(Offset 0x1090) */\n\n#define BIT_DATA_CPU_RST BIT(0)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HISR4\t\t\t\t(Offset 0x1094) */\n\n#define BIT_TX_BCN_ERR_INT15 BIT(23)\n#define BIT_TX_BCN_ERR_INT14 BIT(22)\n#define BIT_TX_BCN_ERR_INT13 BIT(21)\n#define BIT_TX_BCN_ERR_INT12 BIT(20)\n#define BIT_TX_BCN_ERR_INT11 BIT(19)\n#define BIT_TX_BCN_ERR_INT10 BIT(18)\n#define BIT_TX_BCN_ERR_INT9 BIT(17)\n#define BIT_TX_BCN_ERR_INT8 BIT(16)\n#define BIT_TX_BCN_OK_INT15 BIT(15)\n#define BIT_TX_BCN_OK_INT14 BIT(14)\n#define BIT_TX_BCN_OK_INT13 BIT(13)\n#define BIT_TX_BCN_OK_INT12 BIT(12)\n#define BIT_TX_BCN_OK_INT11 BIT(11)\n#define BIT_TX_BCN_OK_INT10 BIT(10)\n#define BIT_TX_BCN_OK_INT9 BIT(9)\n#define BIT_TX_BCN_OK_INT8 BIT(8)\n#define BIT_BCN_DMA_INT15 BIT(7)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATA_CPU_CTL1\t\t\t(Offset 0x1094) */\n\n#define BIT_HOST_INTERFACE_IO_PATH BIT(7)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HISR4\t\t\t\t(Offset 0x1094) */\n\n#define BIT_BCN_DMA_INT14 BIT(6)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATA_CPU_CTL1\t\t\t(Offset 0x1094) */\n\n#define BIT_EN_TXDMA_OFLD BIT(6)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HISR4\t\t\t\t(Offset 0x1094) */\n\n#define BIT_BCN_DMA_INT13 BIT(5)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATA_CPU_CTL1\t\t\t(Offset 0x1094) */\n\n#define BIT_EN_RXDMA_OFLD BIT(5)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HISR4\t\t\t\t(Offset 0x1094) */\n\n#define BIT_BCN_DMA_INT12 BIT(4)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATA_CPU_CTL1\t\t\t(Offset 0x1094) */\n\n#define BIT_EN_HCI_DMA_TX BIT(4)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HISR4\t\t\t\t(Offset 0x1094) */\n\n#define BIT_BCN_DMA_INT11 BIT(3)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATA_CPU_CTL1\t\t\t(Offset 0x1094) */\n\n#define BIT_EN_HCI_DMA_RX BIT(3)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HISR4\t\t\t\t(Offset 0x1094) */\n\n#define BIT_BCN_DMA_INT10 BIT(2)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATA_CPU_CTL1\t\t\t(Offset 0x1094) */\n\n#define BIT_EN_AXI_DMA_TX BIT(2)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HISR4\t\t\t\t(Offset 0x1094) */\n\n#define BIT_BCN_DMA_INT9 BIT(1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATA_CPU_CTL1\t\t\t(Offset 0x1094) */\n\n#define BIT_EN_AXI_DMA_RX BIT(1)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HISR4\t\t\t\t(Offset 0x1094) */\n\n#define BIT_BCN_DMA_INT8 BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DATA_CPU_CTL1\t\t\t(Offset 0x1094) */\n\n#define BIT_EN_PKT_ENG BIT(0)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HIMR5\t\t\t\t(Offset 0x1098) */\n\n#define BIT_BCN_QDMA_ERR_INT15_MSK BIT(7)\n#define BIT_BCN_QDMA_ERR_INT14_MSK BIT(6)\n#define BIT_BCN_QDMA_ERR_INT13_MSK BIT(5)\n#define BIT_BCN_QDMA_ERR_INT12_MSK BIT(4)\n#define BIT_BCN_QDMA_ERR_INT11_MSK BIT(3)\n#define BIT_BCN_QDMA_ERR_INT10_MSK BIT(2)\n#define BIT_BCN_QDMA_ERR_INT9_MSK BIT(1)\n#define BIT_BCN_QDMA_ERR_INT8_MSK BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXDMA_STOP_HIMR\t\t\t(Offset 0x1098) */\n\n#define BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK 0\n#define BIT_MASK_NTH_TXDMA_STOP_INT_MSK 0x1ffff\n#define BIT_NTH_TXDMA_STOP_INT_MSK(x)                                          \\\n\t(((x) & BIT_MASK_NTH_TXDMA_STOP_INT_MSK)                               \\\n\t << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK)\n#define BITS_NTH_TXDMA_STOP_INT_MSK                                            \\\n\t(BIT_MASK_NTH_TXDMA_STOP_INT_MSK << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK)\n#define BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK(x)                                    \\\n\t((x) & (~BITS_NTH_TXDMA_STOP_INT_MSK))\n#define BIT_GET_NTH_TXDMA_STOP_INT_MSK(x)                                      \\\n\t(((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK) &                           \\\n\t BIT_MASK_NTH_TXDMA_STOP_INT_MSK)\n#define BIT_SET_NTH_TXDMA_STOP_INT_MSK(x, v)                                   \\\n\t(BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK(x) | BIT_NTH_TXDMA_STOP_INT_MSK(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HISR5\t\t\t\t(Offset 0x109C) */\n\n#define BIT_BCN_QDMA_ERR_INT15 BIT(7)\n#define BIT_BCN_QDMA_ERR_INT14 BIT(6)\n#define BIT_BCN_QDMA_ERR_INT13 BIT(5)\n#define BIT_BCN_QDMA_ERR_INT12 BIT(4)\n#define BIT_BCN_QDMA_ERR_INT11 BIT(3)\n#define BIT_BCN_QDMA_ERR_INT10 BIT(2)\n#define BIT_BCN_QDMA_ERR_INT9 BIT(1)\n#define BIT_BCN_QDMA_ERR_INT8 BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXDMA_STOP_HISR\t\t\t(Offset 0x109C) */\n\n#define BIT_SHIFT_NTH_TXDMA_STOP_INT 0\n#define BIT_MASK_NTH_TXDMA_STOP_INT 0x1ffff\n#define BIT_NTH_TXDMA_STOP_INT(x)                                              \\\n\t(((x) & BIT_MASK_NTH_TXDMA_STOP_INT) << BIT_SHIFT_NTH_TXDMA_STOP_INT)\n#define BITS_NTH_TXDMA_STOP_INT                                                \\\n\t(BIT_MASK_NTH_TXDMA_STOP_INT << BIT_SHIFT_NTH_TXDMA_STOP_INT)\n#define BIT_CLEAR_NTH_TXDMA_STOP_INT(x) ((x) & (~BITS_NTH_TXDMA_STOP_INT))\n#define BIT_GET_NTH_TXDMA_STOP_INT(x)                                          \\\n\t(((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT) & BIT_MASK_NTH_TXDMA_STOP_INT)\n#define BIT_SET_NTH_TXDMA_STOP_INT(x, v)                                       \\\n\t(BIT_CLEAR_NTH_TXDMA_STOP_INT(x) | BIT_NTH_TXDMA_STOP_INT(v))\n\n/* 2 REG_TXDMA_START_HIMR\t\t\t(Offset 0x10A0) */\n\n#define BIT_SHIFT_NTH_TXDMA_START_INT_MSK 0\n#define BIT_MASK_NTH_TXDMA_START_INT_MSK 0x1ffff\n#define BIT_NTH_TXDMA_START_INT_MSK(x)                                         \\\n\t(((x) & BIT_MASK_NTH_TXDMA_START_INT_MSK)                              \\\n\t << BIT_SHIFT_NTH_TXDMA_START_INT_MSK)\n#define BITS_NTH_TXDMA_START_INT_MSK                                           \\\n\t(BIT_MASK_NTH_TXDMA_START_INT_MSK << BIT_SHIFT_NTH_TXDMA_START_INT_MSK)\n#define BIT_CLEAR_NTH_TXDMA_START_INT_MSK(x)                                   \\\n\t((x) & (~BITS_NTH_TXDMA_START_INT_MSK))\n#define BIT_GET_NTH_TXDMA_START_INT_MSK(x)                                     \\\n\t(((x) >> BIT_SHIFT_NTH_TXDMA_START_INT_MSK) &                          \\\n\t BIT_MASK_NTH_TXDMA_START_INT_MSK)\n#define BIT_SET_NTH_TXDMA_START_INT_MSK(x, v)                                  \\\n\t(BIT_CLEAR_NTH_TXDMA_START_INT_MSK(x) | BIT_NTH_TXDMA_START_INT_MSK(v))\n\n/* 2 REG_TXDMA_START_HISR\t\t\t(Offset 0x10A4) */\n\n#define BIT_SHIFT_NTH_TXDMA_START_INT 0\n#define BIT_MASK_NTH_TXDMA_START_INT 0x1ffff\n#define BIT_NTH_TXDMA_START_INT(x)                                             \\\n\t(((x) & BIT_MASK_NTH_TXDMA_START_INT) << BIT_SHIFT_NTH_TXDMA_START_INT)\n#define BITS_NTH_TXDMA_START_INT                                               \\\n\t(BIT_MASK_NTH_TXDMA_START_INT << BIT_SHIFT_NTH_TXDMA_START_INT)\n#define BIT_CLEAR_NTH_TXDMA_START_INT(x) ((x) & (~BITS_NTH_TXDMA_START_INT))\n#define BIT_GET_NTH_TXDMA_START_INT(x)                                         \\\n\t(((x) >> BIT_SHIFT_NTH_TXDMA_START_INT) & BIT_MASK_NTH_TXDMA_START_INT)\n#define BIT_SET_NTH_TXDMA_START_INT(x, v)                                      \\\n\t(BIT_CLEAR_NTH_TXDMA_START_INT(x) | BIT_NTH_TXDMA_START_INT(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_NFC_PAD_CTRL\t\t\t(Offset 0x10A8) */\n\n#define BIT_SYM_NFC_PAD_SEL BIT(19)\n#define BIT_SYM_NFC_PAD_SHDN BIT(18)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_NFCPAD_CTRL\t\t\t\t(Offset 0x10A8) */\n\n#define BIT_PAD_SHUTDW BIT(18)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_NFC_PAD_CTRL\t\t\t(Offset 0x10A8) */\n\n#define BIT_SYM_NFC_PAD_E2 BIT(17)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_NFCPAD_CTRL\t\t\t\t(Offset 0x10A8) */\n\n#define BIT_SYSON_NFC_PAD BIT(17)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_NFC_PAD_CTRL\t\t\t(Offset 0x10A8) */\n\n#define BIT_SYM_NFC_INTPL BIT(16)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_NFCPAD_CTRL\t\t\t\t(Offset 0x10A8) */\n\n#define BIT_NFC_INT_PAD_CTRL BIT(16)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_NFC_PAD_CTRL\t\t\t(Offset 0x10A8) */\n\n#define BIT_SYM_NFC_RFDIS_PULL BIT(15)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_NFCPAD_CTRL\t\t\t\t(Offset 0x10A8) */\n\n#define BIT_NFC_RFDIS_PAD_CTRL BIT(15)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_NFC_PAD_CTRL\t\t\t(Offset 0x10A8) */\n\n#define BIT_SYM_NFC_CLK_PULL BIT(14)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_NFCPAD_CTRL\t\t\t\t(Offset 0x10A8) */\n\n#define BIT_NFC_CLK_PAD_CTRL BIT(14)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_NFC_PAD_CTRL\t\t\t(Offset 0x10A8) */\n\n#define BIT_SYM_NFC_DATA_PULL BIT(13)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_NFCPAD_CTRL\t\t\t\t(Offset 0x10A8) */\n\n#define BIT_NFC_DATA_PAD_CTRL BIT(13)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_NFC_PAD_CTRL\t\t\t(Offset 0x10A8) */\n\n#define BIT_SYM_NFC_PAD_PULL_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_NFCPAD_CTRL\t\t\t\t(Offset 0x10A8) */\n\n#define BIT_NFC_PAD_PULL_CTRL BIT(12)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_NFC_PAD_CTRL\t\t\t(Offset 0x10A8) */\n\n#define BIT_SYM_NFC_INT_E BIT(11)\n#define BIT_SYM_NFC_RFDIS_E BIT(10)\n#define BIT_SYM_NFC_CLK_E BIT(9)\n#define BIT_SYM_NFC_DATA_E BIT(8)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_NFCPAD_CTRL\t\t\t\t(Offset 0x10A8) */\n\n#define BIT_SHIFT_NFCPAD_IO_SEL 8\n#define BIT_MASK_NFCPAD_IO_SEL 0xf\n#define BIT_NFCPAD_IO_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_NFCPAD_IO_SEL) << BIT_SHIFT_NFCPAD_IO_SEL)\n#define BITS_NFCPAD_IO_SEL (BIT_MASK_NFCPAD_IO_SEL << BIT_SHIFT_NFCPAD_IO_SEL)\n#define BIT_CLEAR_NFCPAD_IO_SEL(x) ((x) & (~BITS_NFCPAD_IO_SEL))\n#define BIT_GET_NFCPAD_IO_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_NFCPAD_IO_SEL) & BIT_MASK_NFCPAD_IO_SEL)\n#define BIT_SET_NFCPAD_IO_SEL(x, v)                                            \\\n\t(BIT_CLEAR_NFCPAD_IO_SEL(x) | BIT_NFCPAD_IO_SEL(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_NFC_PAD_CTRL\t\t\t(Offset 0x10A8) */\n\n#define BIT_SYM_NFC_INT BIT(7)\n#define BIT_SYM_NFC_RFDIS BIT(6)\n#define BIT_SYM_NFC_CLK BIT(5)\n#define BIT_SYM_NFC_DATA BIT(4)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_NFCPAD_CTRL\t\t\t\t(Offset 0x10A8) */\n\n#define BIT_SHIFT_NFCPAD_OUT 4\n#define BIT_MASK_NFCPAD_OUT 0xf\n#define BIT_NFCPAD_OUT(x) (((x) & BIT_MASK_NFCPAD_OUT) << BIT_SHIFT_NFCPAD_OUT)\n#define BITS_NFCPAD_OUT (BIT_MASK_NFCPAD_OUT << BIT_SHIFT_NFCPAD_OUT)\n#define BIT_CLEAR_NFCPAD_OUT(x) ((x) & (~BITS_NFCPAD_OUT))\n#define BIT_GET_NFCPAD_OUT(x)                                                  \\\n\t(((x) >> BIT_SHIFT_NFCPAD_OUT) & BIT_MASK_NFCPAD_OUT)\n#define BIT_SET_NFCPAD_OUT(x, v) (BIT_CLEAR_NFCPAD_OUT(x) | BIT_NFCPAD_OUT(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_NFC_PAD_CTRL\t\t\t(Offset 0x10A8) */\n\n#define BIT_SYM_NFC_INT_I BIT(3)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_NFCPAD_CTRL\t\t\t\t(Offset 0x10A8) */\n\n#define BIT_SHIFT_NFCPAD_IN 0\n#define BIT_MASK_NFCPAD_IN 0xf\n#define BIT_NFCPAD_IN(x) (((x) & BIT_MASK_NFCPAD_IN) << BIT_SHIFT_NFCPAD_IN)\n#define BITS_NFCPAD_IN (BIT_MASK_NFCPAD_IN << BIT_SHIFT_NFCPAD_IN)\n#define BIT_CLEAR_NFCPAD_IN(x) ((x) & (~BITS_NFCPAD_IN))\n#define BIT_GET_NFCPAD_IN(x) (((x) >> BIT_SHIFT_NFCPAD_IN) & BIT_MASK_NFCPAD_IN)\n#define BIT_SET_NFCPAD_IN(x, v) (BIT_CLEAR_NFCPAD_IN(x) | BIT_NFCPAD_IN(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR2\t\t\t\t(Offset 0x10B0) */\n\n#define BIT_BCNDMAINT_P4_MSK BIT(31)\n#define BIT_BCNDMAINT_P4 BIT(31)\n#define BIT_BCNDMAINT_P3_MSK BIT(30)\n#define BIT_BCNDMAINT_P3 BIT(30)\n#define BIT_BCNDMAINT_P2_MSK BIT(29)\n#define BIT_BCNDMAINT_P2 BIT(29)\n#define BIT_BCNDMAINT_P1_MSK BIT(28)\n#define BIT_BCNDMAINT_P1 BIT(28)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR2\t\t\t\t(Offset 0x10B0) */\n\n#define BIT_SCH_PHY_TXOP_SIFS_INT_MSK BIT(23)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR2\t\t\t\t(Offset 0x10B0) */\n\n#define BIT_ATIMEND7_MSK BIT(22)\n#define BIT_ATIMEND7 BIT(22)\n#define BIT_ATIMEND6_MSK BIT(21)\n#define BIT_ATIMEND6 BIT(21)\n#define BIT_ATIMEND5_MSK BIT(20)\n#define BIT_ATIMEND5 BIT(20)\n#define BIT_ATIMEND4_MSK BIT(19)\n#define BIT_ATIMEND4 BIT(19)\n#define BIT_ATIMEND3_MSK BIT(18)\n#define BIT_ATIMEND3 BIT(18)\n#define BIT_ATIMEND2_MSK BIT(17)\n#define BIT_ATIMEND2 BIT(17)\n#define BIT_ATIMEND1_MSK BIT(16)\n#define BIT_ATIMEND1 BIT(16)\n#define BIT_TXBCN7OK_MSK BIT(14)\n#define BIT_TXBCN7OK BIT(14)\n#define BIT_TXBCN6OK_MSK BIT(13)\n#define BIT_TXBCN6OK BIT(13)\n#define BIT_TXBCN5OK_MSK BIT(12)\n#define BIT_TXBCN5OK BIT(12)\n#define BIT_TXBCN4OK_MSK BIT(11)\n#define BIT_TXBCN4OK BIT(11)\n#define BIT_TXBCN3OK_MSK BIT(10)\n#define BIT_TXBCN3OK BIT(10)\n#define BIT_TXBCN2OK_MSK BIT(9)\n#define BIT_TXBCN2OK BIT(9)\n#define BIT_TXBCN1OK_MSK_V1 BIT(8)\n#define BIT_TXBCN1OK BIT(8)\n#define BIT_TXBCN7ERR_MSK BIT(6)\n#define BIT_TXBCN7ERR BIT(6)\n#define BIT_TXBCN6ERR_MSK BIT(5)\n#define BIT_TXBCN6ERR BIT(5)\n#define BIT_TXBCN5ERR_MSK BIT(4)\n#define BIT_TXBCN5ERR BIT(4)\n#define BIT_TXBCN4ERR_MSK BIT(3)\n#define BIT_TXBCN4ERR BIT(3)\n#define BIT_TXBCN3ERR_MSK BIT(2)\n#define BIT_TXBCN3ERR BIT(2)\n#define BIT_TXBCN2ERR_MSK BIT(1)\n#define BIT_TXBCN2ERR BIT(1)\n#define BIT_TXBCN1ERR_MSK_V1 BIT(0)\n#define BIT_TXBCN1ERR BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_GTINT12 BIT(24)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_GTINT12_MSK BIT(24)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_GTINT11 BIT(23)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_GTINT11_MSK BIT(23)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_GTINT10 BIT(22)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_GTINT10_MSK BIT(22)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_GTINT9 BIT(21)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_GTINT9_MSK BIT(21)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_RX_DESC_BUF_FULL BIT(20)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_RX_DESC_BUF_FULL_MSK BIT(20)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_CPHY_LDO_OCP_DET_INT BIT(19)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_CPHY_LDO_OCP_DET_INT_MSK BIT(19)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_WDT_PLATFORM_INT_MSK BIT(18)\n#define BIT_WDT_PLATFORM_INT BIT(18)\n#define BIT_WDT_CPU_INT_MSK BIT(17)\n#define BIT_WDT_CPU_INT BIT(17)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_SETH2CDOK_MASK BIT(16)\n#define BIT_SETH2CDOK BIT(16)\n#define BIT_H2C_CMD_FULL_MASK BIT(15)\n#define BIT_H2C_CMD_FULL BIT(15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_PWR_INT_127_MASK BIT(14)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_PKT_TRANS_ERR BIT(14)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_PKT_TRANS_ERR_MASK BIT(14)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK BIT(13)\n#define BIT_TXSHORTCUT_TXDESUPDATEOK BIT(13)\n#define BIT_TXSHORTCUT_BKUPDATEOK_MASK BIT(12)\n#define BIT_TXSHORTCUT_BKUPDATEOK BIT(12)\n#define BIT_TXSHORTCUT_BEUPDATEOK_MASK BIT(11)\n#define BIT_TXSHORTCUT_BEUPDATEOK BIT(11)\n#define BIT_TXSHORTCUT_VIUPDATEOK_MAS BIT(10)\n#define BIT_TXSHORTCUT_VIUPDATEOK BIT(10)\n#define BIT_TXSHORTCUT_VOUPDATEOK_MASK BIT(9)\n#define BIT_TXSHORTCUT_VOUPDATEOK BIT(9)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_PWR_INT_127_MASK_V1 BIT(8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_SEARCH_FAIL BIT(8)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_SEARCH_FAIL_MSK BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_PWR_INT_126TO96_MASK BIT(7)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_PWR_INT_127TO96 BIT(7)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_PWR_INT_127TO96_MASK BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_PWR_INT_95TO64_MASK BIT(6)\n#define BIT_PWR_INT_95TO64 BIT(6)\n#define BIT_PWR_INT_63TO32_MASK BIT(5)\n#define BIT_PWR_INT_63TO32 BIT(5)\n#define BIT_PWR_INT_31TO0_MASK BIT(4)\n#define BIT_PWR_INT_31TO0 BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_RX_DMA_STUCK_MSK BIT(3)\n#define BIT_RX_DMA_STUCK BIT(3)\n#define BIT_TX_DMA_STUCK_MSK BIT(2)\n#define BIT_TX_DMA_STUCK BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HIMR3\t\t\t\t(Offset 0x10B8) */\n\n#define BIT_DDMA0_LP_INT_MSK BIT(1)\n#define BIT_DDMA0_LP_INT BIT(1)\n#define BIT_DDMA0_HP_INT_MSK BIT(0)\n#define BIT_DDMA0_HP_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HISR3\t\t\t\t(Offset 0x10BC) */\n\n#define BIT_PWR_INT_127 BIT(14)\n#define BIT_PWR_INT_127_V1 BIT(8)\n#define BIT_PWR_INT_126TO96 BIT(7)\n#define BIT_ECRC_EN_V1 BIT(7)\n#define BIT_MDIO_RFLAG_V1 BIT(6)\n#define BIT_MDIO_WFLAG_V1 BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SW_MDIO\t\t\t\t(Offset 0x10C0) */\n\n#define BIT_WLDSS_RST_N_0 BIT(27)\n#define BIT_WLDSS_RST_N_1 BIT(27)\n#define BIT_WLDSS_RST_N_2 BIT(27)\n#define BIT_WLDSS_ENCLK_0 BIT(26)\n#define BIT_WLDSS_ENCLK_1 BIT(26)\n#define BIT_WLDSS_ENCLK_2 BIT(26)\n#define BIT_WLDSS_SPEED_EN_0 BIT(25)\n#define BIT_WLDSS_SPEED_EN_1 BIT(25)\n#define BIT_WLDSS_SPEED_EN_2 BIT(25)\n#define BIT_WLDSS_WIRE_SEL_0 BIT(24)\n#define BIT_WLDSS_WIRE_SEL_1 BIT(24)\n#define BIT_WLDSS_WIRE_SEL_2 BIT(24)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SW_MDIO\t\t\t\t(Offset 0x10C0) */\n\n#define BIT_DIS_TIMEOUT_IO BIT(24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SW_MDIO\t\t\t\t(Offset 0x10C0) */\n\n#define BIT_WLDSS_READY_0 BIT(21)\n#define BIT_WLDSS_READY_1 BIT(21)\n#define BIT_WLDSS_READY_2 BIT(21)\n\n#define BIT_SHIFT_WLDSS_RO_SEL_0 20\n#define BIT_MASK_WLDSS_RO_SEL_0 0x7\n#define BIT_WLDSS_RO_SEL_0(x)                                                  \\\n\t(((x) & BIT_MASK_WLDSS_RO_SEL_0) << BIT_SHIFT_WLDSS_RO_SEL_0)\n#define BITS_WLDSS_RO_SEL_0                                                    \\\n\t(BIT_MASK_WLDSS_RO_SEL_0 << BIT_SHIFT_WLDSS_RO_SEL_0)\n#define BIT_CLEAR_WLDSS_RO_SEL_0(x) ((x) & (~BITS_WLDSS_RO_SEL_0))\n#define BIT_GET_WLDSS_RO_SEL_0(x)                                              \\\n\t(((x) >> BIT_SHIFT_WLDSS_RO_SEL_0) & BIT_MASK_WLDSS_RO_SEL_0)\n#define BIT_SET_WLDSS_RO_SEL_0(x, v)                                           \\\n\t(BIT_CLEAR_WLDSS_RO_SEL_0(x) | BIT_WLDSS_RO_SEL_0(v))\n\n#define BIT_WLDSS_WSORT_GO_0 BIT(20)\n\n#define BIT_SHIFT_WLDSS_RO_SEL_1 20\n#define BIT_MASK_WLDSS_RO_SEL_1 0x7\n#define BIT_WLDSS_RO_SEL_1(x)                                                  \\\n\t(((x) & BIT_MASK_WLDSS_RO_SEL_1) << BIT_SHIFT_WLDSS_RO_SEL_1)\n#define BITS_WLDSS_RO_SEL_1                                                    \\\n\t(BIT_MASK_WLDSS_RO_SEL_1 << BIT_SHIFT_WLDSS_RO_SEL_1)\n#define BIT_CLEAR_WLDSS_RO_SEL_1(x) ((x) & (~BITS_WLDSS_RO_SEL_1))\n#define BIT_GET_WLDSS_RO_SEL_1(x)                                              \\\n\t(((x) >> BIT_SHIFT_WLDSS_RO_SEL_1) & BIT_MASK_WLDSS_RO_SEL_1)\n#define BIT_SET_WLDSS_RO_SEL_1(x, v)                                           \\\n\t(BIT_CLEAR_WLDSS_RO_SEL_1(x) | BIT_WLDSS_RO_SEL_1(v))\n\n#define BIT_WLDSS_WSORT_GO_1 BIT(20)\n\n#define BIT_SHIFT_WLDSS_RO_SEL_2 20\n#define BIT_MASK_WLDSS_RO_SEL_2 0x7\n#define BIT_WLDSS_RO_SEL_2(x)                                                  \\\n\t(((x) & BIT_MASK_WLDSS_RO_SEL_2) << BIT_SHIFT_WLDSS_RO_SEL_2)\n#define BITS_WLDSS_RO_SEL_2                                                    \\\n\t(BIT_MASK_WLDSS_RO_SEL_2 << BIT_SHIFT_WLDSS_RO_SEL_2)\n#define BIT_CLEAR_WLDSS_RO_SEL_2(x) ((x) & (~BITS_WLDSS_RO_SEL_2))\n#define BIT_GET_WLDSS_RO_SEL_2(x)                                              \\\n\t(((x) >> BIT_SHIFT_WLDSS_RO_SEL_2) & BIT_MASK_WLDSS_RO_SEL_2)\n#define BIT_SET_WLDSS_RO_SEL_2(x, v)                                           \\\n\t(BIT_CLEAR_WLDSS_RO_SEL_2(x) | BIT_WLDSS_RO_SEL_2(v))\n\n#define BIT_WLDSS_WSORT_GO_2 BIT(20)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SW_MDIO\t\t\t\t(Offset 0x10C0) */\n\n#define BIT_SUS_PL BIT(18)\n#define BIT_SOP_ESUS BIT(17)\n#define BIT_SOP_DLDO BIT(16)\n#define BIT_R_OCP_ST_CLR BIT(8)\n#define BIT_SW_USB3_MD_SEL BIT(5)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_SW_MDIO\t\t\t\t(Offset 0x10C0) */\n\n#define BIT_SYM_SW_PCIE_MDSL_V1 BIT(4)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SW_MDIO\t\t\t\t(Offset 0x10C0) */\n\n#define BIT_SW_PCIE_MD_SEL BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SW_MDIO\t\t\t\t(Offset 0x10C0) */\n\n#define BIT_SYM_SW_PCIE_MDSL BIT(3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_SW_MDIO\t\t\t\t(Offset 0x10C0) */\n\n#define BIT_SYM_SW_PCIE_MDCK BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SW_MDIO\t\t\t\t(Offset 0x10C0) */\n\n#define BIT_SW_MDCK BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_SW_MDIO\t\t\t\t(Offset 0x10C0) */\n\n#define BIT_SYM_SW_PCIE_MDI BIT(1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SW_MDIO\t\t\t\t(Offset 0x10C0) */\n\n#define BIT_SW_MDI BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n/* 2 REG_SW_MDIO\t\t\t\t(Offset 0x10C0) */\n\n#define BIT_SYM_SW_PCIE_MDO BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_SW_MDIO\t\t\t\t(Offset 0x10C0) */\n\n#define BIT_SHIFT_WLDSS_DATA_IN_0 0\n#define BIT_MASK_WLDSS_DATA_IN_0 0xfffff\n#define BIT_WLDSS_DATA_IN_0(x)                                                 \\\n\t(((x) & BIT_MASK_WLDSS_DATA_IN_0) << BIT_SHIFT_WLDSS_DATA_IN_0)\n#define BITS_WLDSS_DATA_IN_0                                                   \\\n\t(BIT_MASK_WLDSS_DATA_IN_0 << BIT_SHIFT_WLDSS_DATA_IN_0)\n#define BIT_CLEAR_WLDSS_DATA_IN_0(x) ((x) & (~BITS_WLDSS_DATA_IN_0))\n#define BIT_GET_WLDSS_DATA_IN_0(x)                                             \\\n\t(((x) >> BIT_SHIFT_WLDSS_DATA_IN_0) & BIT_MASK_WLDSS_DATA_IN_0)\n#define BIT_SET_WLDSS_DATA_IN_0(x, v)                                          \\\n\t(BIT_CLEAR_WLDSS_DATA_IN_0(x) | BIT_WLDSS_DATA_IN_0(v))\n\n#define BIT_SHIFT_WLDSS_COUNT_OUT_0 0\n#define BIT_MASK_WLDSS_COUNT_OUT_0 0xfffff\n#define BIT_WLDSS_COUNT_OUT_0(x)                                               \\\n\t(((x) & BIT_MASK_WLDSS_COUNT_OUT_0) << BIT_SHIFT_WLDSS_COUNT_OUT_0)\n#define BITS_WLDSS_COUNT_OUT_0                                                 \\\n\t(BIT_MASK_WLDSS_COUNT_OUT_0 << BIT_SHIFT_WLDSS_COUNT_OUT_0)\n#define BIT_CLEAR_WLDSS_COUNT_OUT_0(x) ((x) & (~BITS_WLDSS_COUNT_OUT_0))\n#define BIT_GET_WLDSS_COUNT_OUT_0(x)                                           \\\n\t(((x) >> BIT_SHIFT_WLDSS_COUNT_OUT_0) & BIT_MASK_WLDSS_COUNT_OUT_0)\n#define BIT_SET_WLDSS_COUNT_OUT_0(x, v)                                        \\\n\t(BIT_CLEAR_WLDSS_COUNT_OUT_0(x) | BIT_WLDSS_COUNT_OUT_0(v))\n\n#define BIT_SHIFT_WLDSS_DATA_IN_1 0\n#define BIT_MASK_WLDSS_DATA_IN_1 0xfffff\n#define BIT_WLDSS_DATA_IN_1(x)                                                 \\\n\t(((x) & BIT_MASK_WLDSS_DATA_IN_1) << BIT_SHIFT_WLDSS_DATA_IN_1)\n#define BITS_WLDSS_DATA_IN_1                                                   \\\n\t(BIT_MASK_WLDSS_DATA_IN_1 << BIT_SHIFT_WLDSS_DATA_IN_1)\n#define BIT_CLEAR_WLDSS_DATA_IN_1(x) ((x) & (~BITS_WLDSS_DATA_IN_1))\n#define BIT_GET_WLDSS_DATA_IN_1(x)                                             \\\n\t(((x) >> BIT_SHIFT_WLDSS_DATA_IN_1) & BIT_MASK_WLDSS_DATA_IN_1)\n#define BIT_SET_WLDSS_DATA_IN_1(x, v)                                          \\\n\t(BIT_CLEAR_WLDSS_DATA_IN_1(x) | BIT_WLDSS_DATA_IN_1(v))\n\n#define BIT_SHIFT_WLDSS_COUNT_OUT_1 0\n#define BIT_MASK_WLDSS_COUNT_OUT_1 0xfffff\n#define BIT_WLDSS_COUNT_OUT_1(x)                                               \\\n\t(((x) & BIT_MASK_WLDSS_COUNT_OUT_1) << BIT_SHIFT_WLDSS_COUNT_OUT_1)\n#define BITS_WLDSS_COUNT_OUT_1                                                 \\\n\t(BIT_MASK_WLDSS_COUNT_OUT_1 << BIT_SHIFT_WLDSS_COUNT_OUT_1)\n#define BIT_CLEAR_WLDSS_COUNT_OUT_1(x) ((x) & (~BITS_WLDSS_COUNT_OUT_1))\n#define BIT_GET_WLDSS_COUNT_OUT_1(x)                                           \\\n\t(((x) >> BIT_SHIFT_WLDSS_COUNT_OUT_1) & BIT_MASK_WLDSS_COUNT_OUT_1)\n#define BIT_SET_WLDSS_COUNT_OUT_1(x, v)                                        \\\n\t(BIT_CLEAR_WLDSS_COUNT_OUT_1(x) | BIT_WLDSS_COUNT_OUT_1(v))\n\n#define BIT_SHIFT_WLDSS_DATA_IN_2 0\n#define BIT_MASK_WLDSS_DATA_IN_2 0xfffff\n#define BIT_WLDSS_DATA_IN_2(x)                                                 \\\n\t(((x) & BIT_MASK_WLDSS_DATA_IN_2) << BIT_SHIFT_WLDSS_DATA_IN_2)\n#define BITS_WLDSS_DATA_IN_2                                                   \\\n\t(BIT_MASK_WLDSS_DATA_IN_2 << BIT_SHIFT_WLDSS_DATA_IN_2)\n#define BIT_CLEAR_WLDSS_DATA_IN_2(x) ((x) & (~BITS_WLDSS_DATA_IN_2))\n#define BIT_GET_WLDSS_DATA_IN_2(x)                                             \\\n\t(((x) >> BIT_SHIFT_WLDSS_DATA_IN_2) & BIT_MASK_WLDSS_DATA_IN_2)\n#define BIT_SET_WLDSS_DATA_IN_2(x, v)                                          \\\n\t(BIT_CLEAR_WLDSS_DATA_IN_2(x) | BIT_WLDSS_DATA_IN_2(v))\n\n#define BIT_SHIFT_WLDSS_COUNT_OUT_2 0\n#define BIT_MASK_WLDSS_COUNT_OUT_2 0xfffff\n#define BIT_WLDSS_COUNT_OUT_2(x)                                               \\\n\t(((x) & BIT_MASK_WLDSS_COUNT_OUT_2) << BIT_SHIFT_WLDSS_COUNT_OUT_2)\n#define BITS_WLDSS_COUNT_OUT_2                                                 \\\n\t(BIT_MASK_WLDSS_COUNT_OUT_2 << BIT_SHIFT_WLDSS_COUNT_OUT_2)\n#define BIT_CLEAR_WLDSS_COUNT_OUT_2(x) ((x) & (~BITS_WLDSS_COUNT_OUT_2))\n#define BIT_GET_WLDSS_COUNT_OUT_2(x)                                           \\\n\t(((x) >> BIT_SHIFT_WLDSS_COUNT_OUT_2) & BIT_MASK_WLDSS_COUNT_OUT_2)\n#define BIT_SET_WLDSS_COUNT_OUT_2(x, v)                                        \\\n\t(BIT_CLEAR_WLDSS_COUNT_OUT_2(x) | BIT_WLDSS_COUNT_OUT_2(v))\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_SW_MDIO\t\t\t\t(Offset 0x10C0) */\n\n#define BIT_MDO BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_SW_FLUSH\t\t\t\t(Offset 0x10C4) */\n\n#define BIT_FLUSH_HOLDN_EN BIT(25)\n#define BIT_FLUSH_WR_EN BIT(24)\n#define BIT_SW_FLASH_CONTROL BIT(23)\n#define BIT_SW_FLASH_WEN_E BIT(19)\n#define BIT_SW_FLASH_HOLDN_E BIT(18)\n#define BIT_SW_FLASH_SO_E BIT(17)\n#define BIT_SW_FLASH_SI_E BIT(16)\n#define BIT_SW_FLASH_SK_O BIT(13)\n#define BIT_SW_FLASH_CEN_O BIT(12)\n#define BIT_SW_FLASH_WEN_O BIT(11)\n#define BIT_SW_FLASH_HOLDN_O BIT(10)\n#define BIT_SW_FLASH_SO_O BIT(9)\n#define BIT_SW_FLASH_SI_O BIT(8)\n#define BIT_SW_FLASH_WEN_I BIT(3)\n#define BIT_SW_FLASH_HOLDN_I BIT(2)\n#define BIT_SW_FLASH_SO_I BIT(1)\n#define BIT_SW_FLASH_SI_I BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR_7\t\t\t\t(Offset 0x10C8) */\n\n#define BIT_DATA_CPU_WDT_INT_MSK BIT(31)\n#define BIT_OFLD_TXDMA_ERR_MSK BIT(30)\n#define BIT_OFLD_TXDMA_FULL_MSK BIT(29)\n#define BIT_OFLD_RXDMA_OVR_MSK BIT(28)\n#define BIT_OFLD_RXDMA_ERR_MSK BIT(27)\n#define BIT_OFLD_RXDMA_DES_UA_MSK BIT(26)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DBG_GPIO_BMUX\t\t\t(Offset 0x10C8) */\n\n#define BIT_SHIFT_WL_DSS_CLKEN_BACKDOOR 24\n#define BIT_MASK_WL_DSS_CLKEN_BACKDOOR 0x3\n#define BIT_WL_DSS_CLKEN_BACKDOOR(x)                                           \\\n\t(((x) & BIT_MASK_WL_DSS_CLKEN_BACKDOOR)                                \\\n\t << BIT_SHIFT_WL_DSS_CLKEN_BACKDOOR)\n#define BITS_WL_DSS_CLKEN_BACKDOOR                                             \\\n\t(BIT_MASK_WL_DSS_CLKEN_BACKDOOR << BIT_SHIFT_WL_DSS_CLKEN_BACKDOOR)\n#define BIT_CLEAR_WL_DSS_CLKEN_BACKDOOR(x) ((x) & (~BITS_WL_DSS_CLKEN_BACKDOOR))\n#define BIT_GET_WL_DSS_CLKEN_BACKDOOR(x)                                       \\\n\t(((x) >> BIT_SHIFT_WL_DSS_CLKEN_BACKDOOR) &                            \\\n\t BIT_MASK_WL_DSS_CLKEN_BACKDOOR)\n#define BIT_SET_WL_DSS_CLKEN_BACKDOOR(x, v)                                    \\\n\t(BIT_CLEAR_WL_DSS_CLKEN_BACKDOOR(x) | BIT_WL_DSS_CLKEN_BACKDOOR(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DBG_GPIO_BMUX\t\t\t(Offset 0x10C8) */\n\n#define BIT_SHIFT_DBG_GPIO_BMUX_7 21\n#define BIT_MASK_DBG_GPIO_BMUX_7 0x7\n#define BIT_DBG_GPIO_BMUX_7(x)                                                 \\\n\t(((x) & BIT_MASK_DBG_GPIO_BMUX_7) << BIT_SHIFT_DBG_GPIO_BMUX_7)\n#define BITS_DBG_GPIO_BMUX_7                                                   \\\n\t(BIT_MASK_DBG_GPIO_BMUX_7 << BIT_SHIFT_DBG_GPIO_BMUX_7)\n#define BIT_CLEAR_DBG_GPIO_BMUX_7(x) ((x) & (~BITS_DBG_GPIO_BMUX_7))\n#define BIT_GET_DBG_GPIO_BMUX_7(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_7) & BIT_MASK_DBG_GPIO_BMUX_7)\n#define BIT_SET_DBG_GPIO_BMUX_7(x, v)                                          \\\n\t(BIT_CLEAR_DBG_GPIO_BMUX_7(x) | BIT_DBG_GPIO_BMUX_7(v))\n\n#define BIT_SHIFT_DBG_GPIO_BMUX_6 18\n#define BIT_MASK_DBG_GPIO_BMUX_6 0x7\n#define BIT_DBG_GPIO_BMUX_6(x)                                                 \\\n\t(((x) & BIT_MASK_DBG_GPIO_BMUX_6) << BIT_SHIFT_DBG_GPIO_BMUX_6)\n#define BITS_DBG_GPIO_BMUX_6                                                   \\\n\t(BIT_MASK_DBG_GPIO_BMUX_6 << BIT_SHIFT_DBG_GPIO_BMUX_6)\n#define BIT_CLEAR_DBG_GPIO_BMUX_6(x) ((x) & (~BITS_DBG_GPIO_BMUX_6))\n#define BIT_GET_DBG_GPIO_BMUX_6(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_6) & BIT_MASK_DBG_GPIO_BMUX_6)\n#define BIT_SET_DBG_GPIO_BMUX_6(x, v)                                          \\\n\t(BIT_CLEAR_DBG_GPIO_BMUX_6(x) | BIT_DBG_GPIO_BMUX_6(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR_7\t\t\t\t(Offset 0x10C8) */\n\n#define BIT_TXDMAOK_CHANNEL_16_MSK BIT(16)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DBG_GPIO_BMUX\t\t\t(Offset 0x10C8) */\n\n#define BIT_SHIFT_DBG_GPIO_BMUX_5 15\n#define BIT_MASK_DBG_GPIO_BMUX_5 0x7\n#define BIT_DBG_GPIO_BMUX_5(x)                                                 \\\n\t(((x) & BIT_MASK_DBG_GPIO_BMUX_5) << BIT_SHIFT_DBG_GPIO_BMUX_5)\n#define BITS_DBG_GPIO_BMUX_5                                                   \\\n\t(BIT_MASK_DBG_GPIO_BMUX_5 << BIT_SHIFT_DBG_GPIO_BMUX_5)\n#define BIT_CLEAR_DBG_GPIO_BMUX_5(x) ((x) & (~BITS_DBG_GPIO_BMUX_5))\n#define BIT_GET_DBG_GPIO_BMUX_5(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_5) & BIT_MASK_DBG_GPIO_BMUX_5)\n#define BIT_SET_DBG_GPIO_BMUX_5(x, v)                                          \\\n\t(BIT_CLEAR_DBG_GPIO_BMUX_5(x) | BIT_DBG_GPIO_BMUX_5(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR_7\t\t\t\t(Offset 0x10C8) */\n\n#define BIT_TXDMAOK_CHANNEL_13_MSK BIT(13)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DBG_GPIO_BMUX\t\t\t(Offset 0x10C8) */\n\n#define BIT_SHIFT_DBG_GPIO_BMUX_4 12\n#define BIT_MASK_DBG_GPIO_BMUX_4 0x7\n#define BIT_DBG_GPIO_BMUX_4(x)                                                 \\\n\t(((x) & BIT_MASK_DBG_GPIO_BMUX_4) << BIT_SHIFT_DBG_GPIO_BMUX_4)\n#define BITS_DBG_GPIO_BMUX_4                                                   \\\n\t(BIT_MASK_DBG_GPIO_BMUX_4 << BIT_SHIFT_DBG_GPIO_BMUX_4)\n#define BIT_CLEAR_DBG_GPIO_BMUX_4(x) ((x) & (~BITS_DBG_GPIO_BMUX_4))\n#define BIT_GET_DBG_GPIO_BMUX_4(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_4) & BIT_MASK_DBG_GPIO_BMUX_4)\n#define BIT_SET_DBG_GPIO_BMUX_4(x, v)                                          \\\n\t(BIT_CLEAR_DBG_GPIO_BMUX_4(x) | BIT_DBG_GPIO_BMUX_4(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR_7\t\t\t\t(Offset 0x10C8) */\n\n#define BIT_TXDMAOK_CHANNEL_12_MSK BIT(12)\n#define BIT_TXDMAOK_CHANNEL_11_MSK BIT(11)\n#define BIT_TXDMAOK_CHANNEL_10_MSK BIT(10)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DBG_GPIO_BMUX\t\t\t(Offset 0x10C8) */\n\n#define BIT_SHIFT_DBG_GPIO_BMUX_3 9\n#define BIT_MASK_DBG_GPIO_BMUX_3 0x7\n#define BIT_DBG_GPIO_BMUX_3(x)                                                 \\\n\t(((x) & BIT_MASK_DBG_GPIO_BMUX_3) << BIT_SHIFT_DBG_GPIO_BMUX_3)\n#define BITS_DBG_GPIO_BMUX_3                                                   \\\n\t(BIT_MASK_DBG_GPIO_BMUX_3 << BIT_SHIFT_DBG_GPIO_BMUX_3)\n#define BIT_CLEAR_DBG_GPIO_BMUX_3(x) ((x) & (~BITS_DBG_GPIO_BMUX_3))\n#define BIT_GET_DBG_GPIO_BMUX_3(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_3) & BIT_MASK_DBG_GPIO_BMUX_3)\n#define BIT_SET_DBG_GPIO_BMUX_3(x, v)                                          \\\n\t(BIT_CLEAR_DBG_GPIO_BMUX_3(x) | BIT_DBG_GPIO_BMUX_3(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR_7\t\t\t\t(Offset 0x10C8) */\n\n#define BIT_TXDMAOK_CHANNEL_9_MSK BIT(9)\n#define BIT_TXDMAOK_CHANNEL_8_MSK BIT(8)\n#define BIT_TXDMAOK_CHANNEL_7_MSK BIT(7)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DBG_GPIO_BMUX\t\t\t(Offset 0x10C8) */\n\n#define BIT_SHIFT_DBG_GPIO_BMUX_2 6\n#define BIT_MASK_DBG_GPIO_BMUX_2 0x7\n#define BIT_DBG_GPIO_BMUX_2(x)                                                 \\\n\t(((x) & BIT_MASK_DBG_GPIO_BMUX_2) << BIT_SHIFT_DBG_GPIO_BMUX_2)\n#define BITS_DBG_GPIO_BMUX_2                                                   \\\n\t(BIT_MASK_DBG_GPIO_BMUX_2 << BIT_SHIFT_DBG_GPIO_BMUX_2)\n#define BIT_CLEAR_DBG_GPIO_BMUX_2(x) ((x) & (~BITS_DBG_GPIO_BMUX_2))\n#define BIT_GET_DBG_GPIO_BMUX_2(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_2) & BIT_MASK_DBG_GPIO_BMUX_2)\n#define BIT_SET_DBG_GPIO_BMUX_2(x, v)                                          \\\n\t(BIT_CLEAR_DBG_GPIO_BMUX_2(x) | BIT_DBG_GPIO_BMUX_2(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIMR_7\t\t\t\t(Offset 0x10C8) */\n\n#define BIT_TXDMAOK_CHANNEL_6_MSK BIT(6)\n#define BIT_TXDMAOK_CHANNEL_5_MSK BIT(5)\n#define BIT_TXDMAOK_CHANNEL_4_MSK BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DBG_GPIO_BMUX\t\t\t(Offset 0x10C8) */\n\n#define BIT_SHIFT_DBG_GPIO_BMUX_1 3\n#define BIT_MASK_DBG_GPIO_BMUX_1 0x7\n#define BIT_DBG_GPIO_BMUX_1(x)                                                 \\\n\t(((x) & BIT_MASK_DBG_GPIO_BMUX_1) << BIT_SHIFT_DBG_GPIO_BMUX_1)\n#define BITS_DBG_GPIO_BMUX_1                                                   \\\n\t(BIT_MASK_DBG_GPIO_BMUX_1 << BIT_SHIFT_DBG_GPIO_BMUX_1)\n#define BIT_CLEAR_DBG_GPIO_BMUX_1(x) ((x) & (~BITS_DBG_GPIO_BMUX_1))\n#define BIT_GET_DBG_GPIO_BMUX_1(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_1) & BIT_MASK_DBG_GPIO_BMUX_1)\n#define BIT_SET_DBG_GPIO_BMUX_1(x, v)                                          \\\n\t(BIT_CLEAR_DBG_GPIO_BMUX_1(x) | BIT_DBG_GPIO_BMUX_1(v))\n\n#define BIT_SHIFT_DBG_GPIO_BMUX_0 0\n#define BIT_MASK_DBG_GPIO_BMUX_0 0x7\n#define BIT_DBG_GPIO_BMUX_0(x)                                                 \\\n\t(((x) & BIT_MASK_DBG_GPIO_BMUX_0) << BIT_SHIFT_DBG_GPIO_BMUX_0)\n#define BITS_DBG_GPIO_BMUX_0                                                   \\\n\t(BIT_MASK_DBG_GPIO_BMUX_0 << BIT_SHIFT_DBG_GPIO_BMUX_0)\n#define BIT_CLEAR_DBG_GPIO_BMUX_0(x) ((x) & (~BITS_DBG_GPIO_BMUX_0))\n#define BIT_GET_DBG_GPIO_BMUX_0(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_0) & BIT_MASK_DBG_GPIO_BMUX_0)\n#define BIT_SET_DBG_GPIO_BMUX_0(x, v)                                          \\\n\t(BIT_CLEAR_DBG_GPIO_BMUX_0(x) | BIT_DBG_GPIO_BMUX_0(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HISR_7\t\t\t\t(Offset 0x10CC) */\n\n#define BIT_DATA_CPU_WDT_INT BIT(31)\n#define BIT_OFLD_TXDMA_ERR BIT(30)\n#define BIT_OFLD_TXDMA_FULL BIT(29)\n#define BIT_OFLD_RXDMA_OVR BIT(28)\n#define BIT_OFLD_RXDMA_ERR BIT(27)\n#define BIT_OFLD_RXDMA_DES_UA BIT(26)\n#define BIT_TXDMAOK_CHANNEL_16 BIT(16)\n#define BIT_TXDMAOK_CHANNEL_13 BIT(13)\n#define BIT_TXDMAOK_CHANNEL_12 BIT(12)\n#define BIT_TXDMAOK_CHANNEL_11 BIT(11)\n#define BIT_TXDMAOK_CHANNEL_10 BIT(10)\n#define BIT_TXDMAOK_CHANNEL_9 BIT(9)\n#define BIT_TXDMAOK_CHANNEL_8 BIT(8)\n#define BIT_TXDMAOK_CHANNEL_7 BIT(7)\n#define BIT_TXDMAOK_CHANNEL_6 BIT(6)\n#define BIT_TXDMAOK_CHANNEL_5 BIT(5)\n#define BIT_TXDMAOK_CHANNEL_4 BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FPGA_TAG\t\t\t\t(Offset 0x10CC) */\n\n#define BIT_SHIFT_FPGA_TAG 0\n#define BIT_MASK_FPGA_TAG 0xffffffffL\n#define BIT_FPGA_TAG(x) (((x) & BIT_MASK_FPGA_TAG) << BIT_SHIFT_FPGA_TAG)\n#define BITS_FPGA_TAG (BIT_MASK_FPGA_TAG << BIT_SHIFT_FPGA_TAG)\n#define BIT_CLEAR_FPGA_TAG(x) ((x) & (~BITS_FPGA_TAG))\n#define BIT_GET_FPGA_TAG(x) (((x) >> BIT_SHIFT_FPGA_TAG) & BIT_MASK_FPGA_TAG)\n#define BIT_SET_FPGA_TAG(x, v) (BIT_CLEAR_FPGA_TAG(x) | BIT_FPGA_TAG(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_WL_DSS_CTRL0\t\t\t(Offset 0x10D0) */\n\n#define BIT_SHIFT_WL_DSS_DBG0_5_0 26\n#define BIT_MASK_WL_DSS_DBG0_5_0 0x3f\n#define BIT_WL_DSS_DBG0_5_0(x)                                                 \\\n\t(((x) & BIT_MASK_WL_DSS_DBG0_5_0) << BIT_SHIFT_WL_DSS_DBG0_5_0)\n#define BITS_WL_DSS_DBG0_5_0                                                   \\\n\t(BIT_MASK_WL_DSS_DBG0_5_0 << BIT_SHIFT_WL_DSS_DBG0_5_0)\n#define BIT_CLEAR_WL_DSS_DBG0_5_0(x) ((x) & (~BITS_WL_DSS_DBG0_5_0))\n#define BIT_GET_WL_DSS_DBG0_5_0(x)                                             \\\n\t(((x) >> BIT_SHIFT_WL_DSS_DBG0_5_0) & BIT_MASK_WL_DSS_DBG0_5_0)\n#define BIT_SET_WL_DSS_DBG0_5_0(x, v)                                          \\\n\t(BIT_CLEAR_WL_DSS_DBG0_5_0(x) | BIT_WL_DSS_DBG0_5_0(v))\n\n#define BIT_SHIFT_WL_DSS_DATA_IN_V1 5\n#define BIT_MASK_WL_DSS_DATA_IN_V1 0xfffff\n#define BIT_WL_DSS_DATA_IN_V1(x)                                               \\\n\t(((x) & BIT_MASK_WL_DSS_DATA_IN_V1) << BIT_SHIFT_WL_DSS_DATA_IN_V1)\n#define BITS_WL_DSS_DATA_IN_V1                                                 \\\n\t(BIT_MASK_WL_DSS_DATA_IN_V1 << BIT_SHIFT_WL_DSS_DATA_IN_V1)\n#define BIT_CLEAR_WL_DSS_DATA_IN_V1(x) ((x) & (~BITS_WL_DSS_DATA_IN_V1))\n#define BIT_GET_WL_DSS_DATA_IN_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_WL_DSS_DATA_IN_V1) & BIT_MASK_WL_DSS_DATA_IN_V1)\n#define BIT_SET_WL_DSS_DATA_IN_V1(x, v)                                        \\\n\t(BIT_CLEAR_WL_DSS_DATA_IN_V1(x) | BIT_WL_DSS_DATA_IN_V1(v))\n\n#define BIT_WL_DSS_WIRE_SEL_V1 BIT(4)\n\n#define BIT_SHIFT_WL_DSS_RO_SEL_V1 1\n#define BIT_MASK_WL_DSS_RO_SEL_V1 0x7\n#define BIT_WL_DSS_RO_SEL_V1(x)                                                \\\n\t(((x) & BIT_MASK_WL_DSS_RO_SEL_V1) << BIT_SHIFT_WL_DSS_RO_SEL_V1)\n#define BITS_WL_DSS_RO_SEL_V1                                                  \\\n\t(BIT_MASK_WL_DSS_RO_SEL_V1 << BIT_SHIFT_WL_DSS_RO_SEL_V1)\n#define BIT_CLEAR_WL_DSS_RO_SEL_V1(x) ((x) & (~BITS_WL_DSS_RO_SEL_V1))\n#define BIT_GET_WL_DSS_RO_SEL_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_WL_DSS_RO_SEL_V1) & BIT_MASK_WL_DSS_RO_SEL_V1)\n#define BIT_SET_WL_DSS_RO_SEL_V1(x, v)                                         \\\n\t(BIT_CLEAR_WL_DSS_RO_SEL_V1(x) | BIT_WL_DSS_RO_SEL_V1(v))\n\n#define BIT_WL_DSS_RSTN_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_H2C_PKT_READADDR\t\t\t(Offset 0x10D0) */\n\n#define BIT_SHIFT_H2C_PKT_READADDR 0\n#define BIT_MASK_H2C_PKT_READADDR 0x3ffff\n#define BIT_H2C_PKT_READADDR(x)                                                \\\n\t(((x) & BIT_MASK_H2C_PKT_READADDR) << BIT_SHIFT_H2C_PKT_READADDR)\n#define BITS_H2C_PKT_READADDR                                                  \\\n\t(BIT_MASK_H2C_PKT_READADDR << BIT_SHIFT_H2C_PKT_READADDR)\n#define BIT_CLEAR_H2C_PKT_READADDR(x) ((x) & (~BITS_H2C_PKT_READADDR))\n#define BIT_GET_H2C_PKT_READADDR(x)                                            \\\n\t(((x) >> BIT_SHIFT_H2C_PKT_READADDR) & BIT_MASK_H2C_PKT_READADDR)\n#define BIT_SET_H2C_PKT_READADDR(x, v)                                         \\\n\t(BIT_CLEAR_H2C_PKT_READADDR(x) | BIT_H2C_PKT_READADDR(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_WL_DSS_STATUS0\t\t\t(Offset 0x10D4) */\n\n#define BIT_SHIFT_WL_DSS_DBG0_15_6 22\n#define BIT_MASK_WL_DSS_DBG0_15_6 0x3ff\n#define BIT_WL_DSS_DBG0_15_6(x)                                                \\\n\t(((x) & BIT_MASK_WL_DSS_DBG0_15_6) << BIT_SHIFT_WL_DSS_DBG0_15_6)\n#define BITS_WL_DSS_DBG0_15_6                                                  \\\n\t(BIT_MASK_WL_DSS_DBG0_15_6 << BIT_SHIFT_WL_DSS_DBG0_15_6)\n#define BIT_CLEAR_WL_DSS_DBG0_15_6(x) ((x) & (~BITS_WL_DSS_DBG0_15_6))\n#define BIT_GET_WL_DSS_DBG0_15_6(x)                                            \\\n\t(((x) >> BIT_SHIFT_WL_DSS_DBG0_15_6) & BIT_MASK_WL_DSS_DBG0_15_6)\n#define BIT_SET_WL_DSS_DBG0_15_6(x, v)                                         \\\n\t(BIT_CLEAR_WL_DSS_DBG0_15_6(x) | BIT_WL_DSS_DBG0_15_6(v))\n\n#define BIT_WL_DSS_WSORT_GO_V1 BIT(21)\n#define BIT_WL_DSS_READY_V1 BIT(20)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_H2C_PKT_WRITEADDR\t\t\t(Offset 0x10D4) */\n\n#define BIT_SHIFT_H2C_PKT_WRITEADDR 0\n#define BIT_MASK_H2C_PKT_WRITEADDR 0x3ffff\n#define BIT_H2C_PKT_WRITEADDR(x)                                               \\\n\t(((x) & BIT_MASK_H2C_PKT_WRITEADDR) << BIT_SHIFT_H2C_PKT_WRITEADDR)\n#define BITS_H2C_PKT_WRITEADDR                                                 \\\n\t(BIT_MASK_H2C_PKT_WRITEADDR << BIT_SHIFT_H2C_PKT_WRITEADDR)\n#define BIT_CLEAR_H2C_PKT_WRITEADDR(x) ((x) & (~BITS_H2C_PKT_WRITEADDR))\n#define BIT_GET_H2C_PKT_WRITEADDR(x)                                           \\\n\t(((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_PKT_WRITEADDR)\n#define BIT_SET_H2C_PKT_WRITEADDR(x, v)                                        \\\n\t(BIT_CLEAR_H2C_PKT_WRITEADDR(x) | BIT_H2C_PKT_WRITEADDR(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_WL_DSS_CTRL1\t\t\t(Offset 0x10D8) */\n\n#define BIT_SHIFT_WL_DSS_DBG1_5_0 26\n#define BIT_MASK_WL_DSS_DBG1_5_0 0x3f\n#define BIT_WL_DSS_DBG1_5_0(x)                                                 \\\n\t(((x) & BIT_MASK_WL_DSS_DBG1_5_0) << BIT_SHIFT_WL_DSS_DBG1_5_0)\n#define BITS_WL_DSS_DBG1_5_0                                                   \\\n\t(BIT_MASK_WL_DSS_DBG1_5_0 << BIT_SHIFT_WL_DSS_DBG1_5_0)\n#define BIT_CLEAR_WL_DSS_DBG1_5_0(x) ((x) & (~BITS_WL_DSS_DBG1_5_0))\n#define BIT_GET_WL_DSS_DBG1_5_0(x)                                             \\\n\t(((x) >> BIT_SHIFT_WL_DSS_DBG1_5_0) & BIT_MASK_WL_DSS_DBG1_5_0)\n#define BIT_SET_WL_DSS_DBG1_5_0(x, v)                                          \\\n\t(BIT_CLEAR_WL_DSS_DBG1_5_0(x) | BIT_WL_DSS_DBG1_5_0(v))\n\n#define BIT_WL_DSS_SPEED_EN1 BIT(25)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_WL_DSS_CTRL1\t\t\t(Offset 0x10D8) */\n\n#define BIT_WL_DSS_WIRE_SEL BIT(24)\n\n#define BIT_SHIFT_WL_DSS_RO_SEL 20\n#define BIT_MASK_WL_DSS_RO_SEL 0x7\n#define BIT_WL_DSS_RO_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_WL_DSS_RO_SEL) << BIT_SHIFT_WL_DSS_RO_SEL)\n#define BITS_WL_DSS_RO_SEL (BIT_MASK_WL_DSS_RO_SEL << BIT_SHIFT_WL_DSS_RO_SEL)\n#define BIT_CLEAR_WL_DSS_RO_SEL(x) ((x) & (~BITS_WL_DSS_RO_SEL))\n#define BIT_GET_WL_DSS_RO_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_WL_DSS_RO_SEL) & BIT_MASK_WL_DSS_RO_SEL)\n#define BIT_SET_WL_DSS_RO_SEL(x, v)                                            \\\n\t(BIT_CLEAR_WL_DSS_RO_SEL(x) | BIT_WL_DSS_RO_SEL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MEM_PWR_CRTL\t\t\t(Offset 0x10D8) */\n\n#define BIT_MEM_BB_SD BIT(17)\n#define BIT_MEM_BB_DS BIT(16)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MEM_PWR_CRTL\t\t\t(Offset 0x10D8) */\n\n#define BIT_MEM_DENG_LS BIT(13)\n#define BIT_MEM_DENG_DS BIT(12)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MEM_PWR_CRTL\t\t\t(Offset 0x10D8) */\n\n#define BIT_MEM_BT_DS BIT(10)\n#define BIT_MEM_SDIO_LS BIT(9)\n#define BIT_MEM_SDIO_DS BIT(8)\n#define BIT_MEM_USB_LS BIT(7)\n#define BIT_MEM_USB_DS BIT(6)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_WL_DSS_CTRL1\t\t\t(Offset 0x10D8) */\n\n#define BIT_SHIFT_WL_DSS_DATA_IN1 5\n#define BIT_MASK_WL_DSS_DATA_IN1 0xfffff\n#define BIT_WL_DSS_DATA_IN1(x)                                                 \\\n\t(((x) & BIT_MASK_WL_DSS_DATA_IN1) << BIT_SHIFT_WL_DSS_DATA_IN1)\n#define BITS_WL_DSS_DATA_IN1                                                   \\\n\t(BIT_MASK_WL_DSS_DATA_IN1 << BIT_SHIFT_WL_DSS_DATA_IN1)\n#define BIT_CLEAR_WL_DSS_DATA_IN1(x) ((x) & (~BITS_WL_DSS_DATA_IN1))\n#define BIT_GET_WL_DSS_DATA_IN1(x)                                             \\\n\t(((x) >> BIT_SHIFT_WL_DSS_DATA_IN1) & BIT_MASK_WL_DSS_DATA_IN1)\n#define BIT_SET_WL_DSS_DATA_IN1(x, v)                                          \\\n\t(BIT_CLEAR_WL_DSS_DATA_IN1(x) | BIT_WL_DSS_DATA_IN1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MEM_PWR_CRTL\t\t\t(Offset 0x10D8) */\n\n#define BIT_MEM_PCI_LS BIT(5)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_WL_DSS_CTRL1\t\t\t(Offset 0x10D8) */\n\n#define BIT_WL_DSS_WIRE_SEL1 BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MEM_PWR_CRTL\t\t\t(Offset 0x10D8) */\n\n#define BIT_MEM_PCI_DS BIT(4)\n#define BIT_MEM_WLMAC_LS BIT(3)\n#define BIT_MEM_WLMAC_DS BIT(2)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_WL_DSS_CTRL1\t\t\t(Offset 0x10D8) */\n\n#define BIT_SHIFT_WL_DSS_RO_SEL1 1\n#define BIT_MASK_WL_DSS_RO_SEL1 0x7\n#define BIT_WL_DSS_RO_SEL1(x)                                                  \\\n\t(((x) & BIT_MASK_WL_DSS_RO_SEL1) << BIT_SHIFT_WL_DSS_RO_SEL1)\n#define BITS_WL_DSS_RO_SEL1                                                    \\\n\t(BIT_MASK_WL_DSS_RO_SEL1 << BIT_SHIFT_WL_DSS_RO_SEL1)\n#define BIT_CLEAR_WL_DSS_RO_SEL1(x) ((x) & (~BITS_WL_DSS_RO_SEL1))\n#define BIT_GET_WL_DSS_RO_SEL1(x)                                              \\\n\t(((x) >> BIT_SHIFT_WL_DSS_RO_SEL1) & BIT_MASK_WL_DSS_RO_SEL1)\n#define BIT_SET_WL_DSS_RO_SEL1(x, v)                                           \\\n\t(BIT_CLEAR_WL_DSS_RO_SEL1(x) | BIT_WL_DSS_RO_SEL1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MEM_PWR_CRTL\t\t\t(Offset 0x10D8) */\n\n#define BIT_MEM_WLMCU_LS BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_WL_DSS_CTRL1\t\t\t(Offset 0x10D8) */\n\n#define BIT_SHIFT_WL_DSS_DATA_IN 0\n#define BIT_MASK_WL_DSS_DATA_IN 0xfffff\n#define BIT_WL_DSS_DATA_IN(x)                                                  \\\n\t(((x) & BIT_MASK_WL_DSS_DATA_IN) << BIT_SHIFT_WL_DSS_DATA_IN)\n#define BITS_WL_DSS_DATA_IN                                                    \\\n\t(BIT_MASK_WL_DSS_DATA_IN << BIT_SHIFT_WL_DSS_DATA_IN)\n#define BIT_CLEAR_WL_DSS_DATA_IN(x) ((x) & (~BITS_WL_DSS_DATA_IN))\n#define BIT_GET_WL_DSS_DATA_IN(x)                                              \\\n\t(((x) >> BIT_SHIFT_WL_DSS_DATA_IN) & BIT_MASK_WL_DSS_DATA_IN)\n#define BIT_SET_WL_DSS_DATA_IN(x, v)                                           \\\n\t(BIT_CLEAR_WL_DSS_DATA_IN(x) | BIT_WL_DSS_DATA_IN(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_WL_DSS_CTRL1\t\t\t(Offset 0x10D8) */\n\n#define BIT_WL_DSS_RSTN1 BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MEM_PWR_CRTL\t\t\t(Offset 0x10D8) */\n\n#define BIT_MEM_WLMCU_DS BIT(0)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_WL_DSS_STATUS1\t\t\t(Offset 0x10DC) */\n\n#define BIT_SHIFT_WL_DSS_DBG1_15_6 22\n#define BIT_MASK_WL_DSS_DBG1_15_6 0x3ff\n#define BIT_WL_DSS_DBG1_15_6(x)                                                \\\n\t(((x) & BIT_MASK_WL_DSS_DBG1_15_6) << BIT_SHIFT_WL_DSS_DBG1_15_6)\n#define BITS_WL_DSS_DBG1_15_6                                                  \\\n\t(BIT_MASK_WL_DSS_DBG1_15_6 << BIT_SHIFT_WL_DSS_DBG1_15_6)\n#define BIT_CLEAR_WL_DSS_DBG1_15_6(x) ((x) & (~BITS_WL_DSS_DBG1_15_6))\n#define BIT_GET_WL_DSS_DBG1_15_6(x)                                            \\\n\t(((x) >> BIT_SHIFT_WL_DSS_DBG1_15_6) & BIT_MASK_WL_DSS_DBG1_15_6)\n#define BIT_SET_WL_DSS_DBG1_15_6(x, v)                                         \\\n\t(BIT_CLEAR_WL_DSS_DBG1_15_6(x) | BIT_WL_DSS_DBG1_15_6(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_WL_DSS_STATUS1\t\t\t(Offset 0x10DC) */\n\n#define BIT_WL_DSS_READY BIT(21)\n#define BIT_WL_DSS_WSORT_GO BIT(20)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FW_DRV_HANDSHAKE\t\t\t(Offset 0x10DC) */\n\n#define BIT_SHIFT_FW_DRV_HANDSHAKE 0\n#define BIT_MASK_FW_DRV_HANDSHAKE 0xffffffffL\n#define BIT_FW_DRV_HANDSHAKE(x)                                                \\\n\t(((x) & BIT_MASK_FW_DRV_HANDSHAKE) << BIT_SHIFT_FW_DRV_HANDSHAKE)\n#define BITS_FW_DRV_HANDSHAKE                                                  \\\n\t(BIT_MASK_FW_DRV_HANDSHAKE << BIT_SHIFT_FW_DRV_HANDSHAKE)\n#define BIT_CLEAR_FW_DRV_HANDSHAKE(x) ((x) & (~BITS_FW_DRV_HANDSHAKE))\n#define BIT_GET_FW_DRV_HANDSHAKE(x)                                            \\\n\t(((x) >> BIT_SHIFT_FW_DRV_HANDSHAKE) & BIT_MASK_FW_DRV_HANDSHAKE)\n#define BIT_SET_FW_DRV_HANDSHAKE(x, v)                                         \\\n\t(BIT_CLEAR_FW_DRV_HANDSHAKE(x) | BIT_FW_DRV_HANDSHAKE(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_FW_DBG0\t\t\t\t(Offset 0x10E0) */\n\n#define BIT_SHIFT_FW_DBG0 0\n#define BIT_MASK_FW_DBG0 0xffffffffL\n#define BIT_FW_DBG0(x) (((x) & BIT_MASK_FW_DBG0) << BIT_SHIFT_FW_DBG0)\n#define BITS_FW_DBG0 (BIT_MASK_FW_DBG0 << BIT_SHIFT_FW_DBG0)\n#define BIT_CLEAR_FW_DBG0(x) ((x) & (~BITS_FW_DBG0))\n#define BIT_GET_FW_DBG0(x) (((x) >> BIT_SHIFT_FW_DBG0) & BIT_MASK_FW_DBG0)\n#define BIT_SET_FW_DBG0(x, v) (BIT_CLEAR_FW_DBG0(x) | BIT_FW_DBG0(v))\n\n/* 2 REG_FW_DBG1\t\t\t\t(Offset 0x10E4) */\n\n#define BIT_SHIFT_FW_DBG1 0\n#define BIT_MASK_FW_DBG1 0xffffffffL\n#define BIT_FW_DBG1(x) (((x) & BIT_MASK_FW_DBG1) << BIT_SHIFT_FW_DBG1)\n#define BITS_FW_DBG1 (BIT_MASK_FW_DBG1 << BIT_SHIFT_FW_DBG1)\n#define BIT_CLEAR_FW_DBG1(x) ((x) & (~BITS_FW_DBG1))\n#define BIT_GET_FW_DBG1(x) (((x) >> BIT_SHIFT_FW_DBG1) & BIT_MASK_FW_DBG1)\n#define BIT_SET_FW_DBG1(x, v) (BIT_CLEAR_FW_DBG1(x) | BIT_FW_DBG1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_FW_DBG2\t\t\t\t(Offset 0x10E8) */\n\n#define BIT_SHIFT_FW_DBG2 0\n#define BIT_MASK_FW_DBG2 0xffffffffL\n#define BIT_FW_DBG2(x) (((x) & BIT_MASK_FW_DBG2) << BIT_SHIFT_FW_DBG2)\n#define BITS_FW_DBG2 (BIT_MASK_FW_DBG2 << BIT_SHIFT_FW_DBG2)\n#define BIT_CLEAR_FW_DBG2(x) ((x) & (~BITS_FW_DBG2))\n#define BIT_GET_FW_DBG2(x) (((x) >> BIT_SHIFT_FW_DBG2) & BIT_MASK_FW_DBG2)\n#define BIT_SET_FW_DBG2(x, v) (BIT_CLEAR_FW_DBG2(x) | BIT_FW_DBG2(v))\n\n/* 2 REG_FW_DBG3\t\t\t\t(Offset 0x10EC) */\n\n#define BIT_SHIFT_FW_DBG3 0\n#define BIT_MASK_FW_DBG3 0xffffffffL\n#define BIT_FW_DBG3(x) (((x) & BIT_MASK_FW_DBG3) << BIT_SHIFT_FW_DBG3)\n#define BITS_FW_DBG3 (BIT_MASK_FW_DBG3 << BIT_SHIFT_FW_DBG3)\n#define BIT_CLEAR_FW_DBG3(x) ((x) & (~BITS_FW_DBG3))\n#define BIT_GET_FW_DBG3(x) (((x) >> BIT_SHIFT_FW_DBG3) & BIT_MASK_FW_DBG3)\n#define BIT_SET_FW_DBG3(x, v) (BIT_CLEAR_FW_DBG3(x) | BIT_FW_DBG3(v))\n\n/* 2 REG_FW_DBG4\t\t\t\t(Offset 0x10F0) */\n\n#define BIT_SHIFT_FW_DBG4 0\n#define BIT_MASK_FW_DBG4 0xffffffffL\n#define BIT_FW_DBG4(x) (((x) & BIT_MASK_FW_DBG4) << BIT_SHIFT_FW_DBG4)\n#define BITS_FW_DBG4 (BIT_MASK_FW_DBG4 << BIT_SHIFT_FW_DBG4)\n#define BIT_CLEAR_FW_DBG4(x) ((x) & (~BITS_FW_DBG4))\n#define BIT_GET_FW_DBG4(x) (((x) >> BIT_SHIFT_FW_DBG4) & BIT_MASK_FW_DBG4)\n#define BIT_SET_FW_DBG4(x, v) (BIT_CLEAR_FW_DBG4(x) | BIT_FW_DBG4(v))\n\n/* 2 REG_FW_DBG5\t\t\t\t(Offset 0x10F4) */\n\n#define BIT_SHIFT_FW_DBG5 0\n#define BIT_MASK_FW_DBG5 0xffffffffL\n#define BIT_FW_DBG5(x) (((x) & BIT_MASK_FW_DBG5) << BIT_SHIFT_FW_DBG5)\n#define BITS_FW_DBG5 (BIT_MASK_FW_DBG5 << BIT_SHIFT_FW_DBG5)\n#define BIT_CLEAR_FW_DBG5(x) ((x) & (~BITS_FW_DBG5))\n#define BIT_GET_FW_DBG5(x) (((x) >> BIT_SHIFT_FW_DBG5) & BIT_MASK_FW_DBG5)\n#define BIT_SET_FW_DBG5(x, v) (BIT_CLEAR_FW_DBG5(x) | BIT_FW_DBG5(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FW_DBG6\t\t\t\t(Offset 0x10F8) */\n\n#define BIT_SHIFT_FW_DBG6 0\n#define BIT_MASK_FW_DBG6 0xffffffffL\n#define BIT_FW_DBG6(x) (((x) & BIT_MASK_FW_DBG6) << BIT_SHIFT_FW_DBG6)\n#define BITS_FW_DBG6 (BIT_MASK_FW_DBG6 << BIT_SHIFT_FW_DBG6)\n#define BIT_CLEAR_FW_DBG6(x) ((x) & (~BITS_FW_DBG6))\n#define BIT_GET_FW_DBG6(x) (((x) >> BIT_SHIFT_FW_DBG6) & BIT_MASK_FW_DBG6)\n#define BIT_SET_FW_DBG6(x, v) (BIT_CLEAR_FW_DBG6(x) | BIT_FW_DBG6(v))\n\n/* 2 REG_FW_DBG7\t\t\t\t(Offset 0x10FC) */\n\n#define BIT_SHIFT_FW_DBG7 0\n#define BIT_MASK_FW_DBG7 0xffffffffL\n#define BIT_FW_DBG7(x) (((x) & BIT_MASK_FW_DBG7) << BIT_SHIFT_FW_DBG7)\n#define BITS_FW_DBG7 (BIT_MASK_FW_DBG7 << BIT_SHIFT_FW_DBG7)\n#define BIT_CLEAR_FW_DBG7(x) ((x) & (~BITS_FW_DBG7))\n#define BIT_GET_FW_DBG7(x) (((x) >> BIT_SHIFT_FW_DBG7) & BIT_MASK_FW_DBG7)\n#define BIT_SET_FW_DBG7(x, v) (BIT_CLEAR_FW_DBG7(x) | BIT_FW_DBG7(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CR_EXT\t\t\t\t(Offset 0x1100) */\n\n#define BIT_SHIFT_PHY_REQ_DELAY 24\n#define BIT_MASK_PHY_REQ_DELAY 0xf\n#define BIT_PHY_REQ_DELAY(x)                                                   \\\n\t(((x) & BIT_MASK_PHY_REQ_DELAY) << BIT_SHIFT_PHY_REQ_DELAY)\n#define BITS_PHY_REQ_DELAY (BIT_MASK_PHY_REQ_DELAY << BIT_SHIFT_PHY_REQ_DELAY)\n#define BIT_CLEAR_PHY_REQ_DELAY(x) ((x) & (~BITS_PHY_REQ_DELAY))\n#define BIT_GET_PHY_REQ_DELAY(x)                                               \\\n\t(((x) >> BIT_SHIFT_PHY_REQ_DELAY) & BIT_MASK_PHY_REQ_DELAY)\n#define BIT_SET_PHY_REQ_DELAY(x, v)                                            \\\n\t(BIT_CLEAR_PHY_REQ_DELAY(x) | BIT_PHY_REQ_DELAY(v))\n\n#define BIT_SPD_DOWN BIT(16)\n\n#define BIT_SHIFT_NETYPE4 4\n#define BIT_MASK_NETYPE4 0x3\n#define BIT_NETYPE4(x) (((x) & BIT_MASK_NETYPE4) << BIT_SHIFT_NETYPE4)\n#define BITS_NETYPE4 (BIT_MASK_NETYPE4 << BIT_SHIFT_NETYPE4)\n#define BIT_CLEAR_NETYPE4(x) ((x) & (~BITS_NETYPE4))\n#define BIT_GET_NETYPE4(x) (((x) >> BIT_SHIFT_NETYPE4) & BIT_MASK_NETYPE4)\n#define BIT_SET_NETYPE4(x, v) (BIT_CLEAR_NETYPE4(x) | BIT_NETYPE4(v))\n\n#define BIT_SHIFT_NETYPE3 2\n#define BIT_MASK_NETYPE3 0x3\n#define BIT_NETYPE3(x) (((x) & BIT_MASK_NETYPE3) << BIT_SHIFT_NETYPE3)\n#define BITS_NETYPE3 (BIT_MASK_NETYPE3 << BIT_SHIFT_NETYPE3)\n#define BIT_CLEAR_NETYPE3(x) ((x) & (~BITS_NETYPE3))\n#define BIT_GET_NETYPE3(x) (((x) >> BIT_SHIFT_NETYPE3) & BIT_MASK_NETYPE3)\n#define BIT_SET_NETYPE3(x, v) (BIT_CLEAR_NETYPE3(x) | BIT_NETYPE3(v))\n\n#define BIT_SHIFT_NETYPE2 0\n#define BIT_MASK_NETYPE2 0x3\n#define BIT_NETYPE2(x) (((x) & BIT_MASK_NETYPE2) << BIT_SHIFT_NETYPE2)\n#define BITS_NETYPE2 (BIT_MASK_NETYPE2 << BIT_SHIFT_NETYPE2)\n#define BIT_CLEAR_NETYPE2(x) ((x) & (~BITS_NETYPE2))\n#define BIT_GET_NETYPE2(x) (((x) >> BIT_SHIFT_NETYPE2) & BIT_MASK_NETYPE2)\n#define BIT_SET_NETYPE2(x, v) (BIT_CLEAR_NETYPE2(x) | BIT_NETYPE2(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TC9_CTRL\t\t\t\t(Offset 0x1104) */\n\n#define BIT_TC9INT_EN BIT(26)\n#define BIT_TC9MODE BIT(25)\n#define BIT_TC9EN BIT(24)\n\n#define BIT_SHIFT_TC9DATA 0\n#define BIT_MASK_TC9DATA 0xffffff\n#define BIT_TC9DATA(x) (((x) & BIT_MASK_TC9DATA) << BIT_SHIFT_TC9DATA)\n#define BITS_TC9DATA (BIT_MASK_TC9DATA << BIT_SHIFT_TC9DATA)\n#define BIT_CLEAR_TC9DATA(x) ((x) & (~BITS_TC9DATA))\n#define BIT_GET_TC9DATA(x) (((x) >> BIT_SHIFT_TC9DATA) & BIT_MASK_TC9DATA)\n#define BIT_SET_TC9DATA(x, v) (BIT_CLEAR_TC9DATA(x) | BIT_TC9DATA(v))\n\n/* 2 REG_TC10_CTRL\t\t\t\t(Offset 0x1108) */\n\n#define BIT_TC10INT_EN BIT(26)\n#define BIT_TC10MODE BIT(25)\n#define BIT_TC10EN BIT(24)\n\n#define BIT_SHIFT_TC10DATA 0\n#define BIT_MASK_TC10DATA 0xffffff\n#define BIT_TC10DATA(x) (((x) & BIT_MASK_TC10DATA) << BIT_SHIFT_TC10DATA)\n#define BITS_TC10DATA (BIT_MASK_TC10DATA << BIT_SHIFT_TC10DATA)\n#define BIT_CLEAR_TC10DATA(x) ((x) & (~BITS_TC10DATA))\n#define BIT_GET_TC10DATA(x) (((x) >> BIT_SHIFT_TC10DATA) & BIT_MASK_TC10DATA)\n#define BIT_SET_TC10DATA(x, v) (BIT_CLEAR_TC10DATA(x) | BIT_TC10DATA(v))\n\n/* 2 REG_TC11_CTRL\t\t\t\t(Offset 0x110C) */\n\n#define BIT_TC11INT_EN BIT(26)\n#define BIT_TC11MODE BIT(25)\n#define BIT_TC11EN BIT(24)\n\n#define BIT_SHIFT_TC11DATA 0\n#define BIT_MASK_TC11DATA 0xffffff\n#define BIT_TC11DATA(x) (((x) & BIT_MASK_TC11DATA) << BIT_SHIFT_TC11DATA)\n#define BITS_TC11DATA (BIT_MASK_TC11DATA << BIT_SHIFT_TC11DATA)\n#define BIT_CLEAR_TC11DATA(x) ((x) & (~BITS_TC11DATA))\n#define BIT_GET_TC11DATA(x) (((x) >> BIT_SHIFT_TC11DATA) & BIT_MASK_TC11DATA)\n#define BIT_SET_TC11DATA(x, v) (BIT_CLEAR_TC11DATA(x) | BIT_TC11DATA(v))\n\n/* 2 REG_TC12_CTRL\t\t\t\t(Offset 0x1110) */\n\n#define BIT_TC12INT_EN BIT(26)\n#define BIT_TC12MODE BIT(25)\n#define BIT_TC12EN BIT(24)\n#define BIT_P2P_PWROFF_NOA2_ERLY_INT BIT(22)\n#define BIT_P2P_PWROFF_NOA1_ERLY_INT BIT(21)\n#define BIT_P2P_PWROFF_NOA0_ERLY_INT BIT(20)\n\n#define BIT_SHIFT_TC12DATA 0\n#define BIT_MASK_TC12DATA 0xffffff\n#define BIT_TC12DATA(x) (((x) & BIT_MASK_TC12DATA) << BIT_SHIFT_TC12DATA)\n#define BITS_TC12DATA (BIT_MASK_TC12DATA << BIT_SHIFT_TC12DATA)\n#define BIT_CLEAR_TC12DATA(x) ((x) & (~BITS_TC12DATA))\n#define BIT_GET_TC12DATA(x) (((x) >> BIT_SHIFT_TC12DATA) & BIT_MASK_TC12DATA)\n#define BIT_SET_TC12DATA(x, v) (BIT_CLEAR_TC12DATA(x) | BIT_TC12DATA(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FWFF\t\t\t\t(Offset 0x1114) */\n\n#define BIT_SHIFT_PKTNUM_TH 24\n#define BIT_MASK_PKTNUM_TH 0xff\n#define BIT_PKTNUM_TH(x) (((x) & BIT_MASK_PKTNUM_TH) << BIT_SHIFT_PKTNUM_TH)\n#define BITS_PKTNUM_TH (BIT_MASK_PKTNUM_TH << BIT_SHIFT_PKTNUM_TH)\n#define BIT_CLEAR_PKTNUM_TH(x) ((x) & (~BITS_PKTNUM_TH))\n#define BIT_GET_PKTNUM_TH(x) (((x) >> BIT_SHIFT_PKTNUM_TH) & BIT_MASK_PKTNUM_TH)\n#define BIT_SET_PKTNUM_TH(x, v) (BIT_CLEAR_PKTNUM_TH(x) | BIT_PKTNUM_TH(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWFF\t\t\t\t(Offset 0x1114) */\n\n#define BIT_SHIFT_PKTNUM_TH_V1 24\n#define BIT_MASK_PKTNUM_TH_V1 0xff\n#define BIT_PKTNUM_TH_V1(x)                                                    \\\n\t(((x) & BIT_MASK_PKTNUM_TH_V1) << BIT_SHIFT_PKTNUM_TH_V1)\n#define BITS_PKTNUM_TH_V1 (BIT_MASK_PKTNUM_TH_V1 << BIT_SHIFT_PKTNUM_TH_V1)\n#define BIT_CLEAR_PKTNUM_TH_V1(x) ((x) & (~BITS_PKTNUM_TH_V1))\n#define BIT_GET_PKTNUM_TH_V1(x)                                                \\\n\t(((x) >> BIT_SHIFT_PKTNUM_TH_V1) & BIT_MASK_PKTNUM_TH_V1)\n#define BIT_SET_PKTNUM_TH_V1(x, v)                                             \\\n\t(BIT_CLEAR_PKTNUM_TH_V1(x) | BIT_PKTNUM_TH_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FWFF\t\t\t\t(Offset 0x1114) */\n\n#define BIT_SHIFT_TIMER_TH 16\n#define BIT_MASK_TIMER_TH 0xff\n#define BIT_TIMER_TH(x) (((x) & BIT_MASK_TIMER_TH) << BIT_SHIFT_TIMER_TH)\n#define BITS_TIMER_TH (BIT_MASK_TIMER_TH << BIT_SHIFT_TIMER_TH)\n#define BIT_CLEAR_TIMER_TH(x) ((x) & (~BITS_TIMER_TH))\n#define BIT_GET_TIMER_TH(x) (((x) >> BIT_SHIFT_TIMER_TH) & BIT_MASK_TIMER_TH)\n#define BIT_SET_TIMER_TH(x, v) (BIT_CLEAR_TIMER_TH(x) | BIT_TIMER_TH(v))\n\n#define BIT_SHIFT_RXPKT1ENADDR 0\n#define BIT_MASK_RXPKT1ENADDR 0xffff\n#define BIT_RXPKT1ENADDR(x)                                                    \\\n\t(((x) & BIT_MASK_RXPKT1ENADDR) << BIT_SHIFT_RXPKT1ENADDR)\n#define BITS_RXPKT1ENADDR (BIT_MASK_RXPKT1ENADDR << BIT_SHIFT_RXPKT1ENADDR)\n#define BIT_CLEAR_RXPKT1ENADDR(x) ((x) & (~BITS_RXPKT1ENADDR))\n#define BIT_GET_RXPKT1ENADDR(x)                                                \\\n\t(((x) >> BIT_SHIFT_RXPKT1ENADDR) & BIT_MASK_RXPKT1ENADDR)\n#define BIT_SET_RXPKT1ENADDR(x, v)                                             \\\n\t(BIT_CLEAR_RXPKT1ENADDR(x) | BIT_RXPKT1ENADDR(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE2IMR\t\t\t\t(Offset 0x1120) */\n\n#define BIT__FE4ISR__IND_MSK BIT(29)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE2IMR\t\t\t\t(Offset 0x1120) */\n\n#define BIT_FS_TXSC_DESC_DONE_INT_EN BIT(28)\n#define BIT_FS_TXSC_BKDONE_INT_EN BIT(27)\n#define BIT_FS_TXSC_BEDONE_INT_EN BIT(26)\n#define BIT_FS_TXSC_VIDONE_INT_EN BIT(25)\n#define BIT_FS_TXSC_VODONE_INT_EN BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE2IMR\t\t\t\t(Offset 0x1120) */\n\n#define BIT_FS_ATIM_MB7_INT_EN BIT(23)\n#define BIT_FS_ATIM_MB6_INT_EN BIT(22)\n#define BIT_FS_ATIM_MB5_INT_EN BIT(21)\n#define BIT_FS_ATIM_MB4_INT_EN BIT(20)\n#define BIT_FS_ATIM_MB3_INT_EN BIT(19)\n#define BIT_FS_ATIM_MB2_INT_EN BIT(18)\n#define BIT_FS_ATIM_MB1_INT_EN BIT(17)\n#define BIT_FS_ATIM_MB0_INT_EN BIT(16)\n#define BIT_FS_TBTT4INT_EN BIT(11)\n#define BIT_FS_TBTT3INT_EN BIT(10)\n#define BIT_FS_TBTT2INT_EN BIT(9)\n#define BIT_FS_TBTT1INT_EN BIT(8)\n#define BIT_FS_TBTT0_MB7INT_EN BIT(7)\n#define BIT_FS_TBTT0_MB6INT_EN BIT(6)\n#define BIT_FS_TBTT0_MB5INT_EN BIT(5)\n#define BIT_FS_TBTT0_MB4INT_EN BIT(4)\n#define BIT_FS_TBTT0_MB3INT_EN BIT(3)\n#define BIT_FS_TBTT0_MB2INT_EN BIT(2)\n#define BIT_FS_TBTT0_MB1INT_EN BIT(1)\n#define BIT_FS_TBTT0_INT_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE2ISR\t\t\t\t(Offset 0x1124) */\n\n#define BIT__FE4ISR__IND_INT BIT(29)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE2ISR\t\t\t\t(Offset 0x1124) */\n\n#define BIT_FS_TXSC_DESC_DONE_INT BIT(28)\n#define BIT_FS_TXSC_BKDONE_INT BIT(27)\n#define BIT_FS_TXSC_BEDONE_INT BIT(26)\n#define BIT_FS_TXSC_VIDONE_INT BIT(25)\n#define BIT_FS_TXSC_VODONE_INT BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE2ISR\t\t\t\t(Offset 0x1124) */\n\n#define BIT_FS_ATIM_MB7_INT BIT(23)\n#define BIT_FS_ATIM_MB6_INT BIT(22)\n#define BIT_FS_ATIM_MB5_INT BIT(21)\n#define BIT_FS_ATIM_MB4_INT BIT(20)\n#define BIT_FS_ATIM_MB3_INT BIT(19)\n#define BIT_FS_ATIM_MB2_INT BIT(18)\n#define BIT_FS_ATIM_MB1_INT BIT(17)\n#define BIT_FS_ATIM_MB0_INT BIT(16)\n#define BIT_FS_TBTT4INT BIT(11)\n#define BIT_FS_TBTT3INT BIT(10)\n#define BIT_FS_TBTT2INT BIT(9)\n#define BIT_FS_TBTT1INT BIT(8)\n#define BIT_FS_TBTT0_MB7INT BIT(7)\n#define BIT_FS_TBTT0_MB6INT BIT(6)\n#define BIT_FS_TBTT0_MB5INT BIT(5)\n#define BIT_FS_TBTT0_MB4INT BIT(4)\n#define BIT_FS_TBTT0_MB3INT BIT(3)\n#define BIT_FS_TBTT0_MB2INT BIT(2)\n#define BIT_FS_TBTT0_MB1INT BIT(1)\n#define BIT_FS_TBTT0_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE3IMR\t\t\t\t(Offset 0x1128) */\n\n#define BIT_FS_BCNELY4_AGGR_INT_EN BIT(31)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE3IMR\t\t\t\t(Offset 0x1128) */\n\n#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN BIT(31)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE3IMR\t\t\t\t(Offset 0x1128) */\n\n#define BIT_FS_BCNELY3_AGGR_INT_EN BIT(30)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE3IMR\t\t\t\t(Offset 0x1128) */\n\n#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN BIT(30)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE3IMR\t\t\t\t(Offset 0x1128) */\n\n#define BIT_FS_BCNELY2_AGGR_INT_EN BIT(29)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE3IMR\t\t\t\t(Offset 0x1128) */\n\n#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN BIT(29)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE3IMR\t\t\t\t(Offset 0x1128) */\n\n#define BIT_FS_BCNELY1_AGGR_INT_EN BIT(28)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE3IMR\t\t\t\t(Offset 0x1128) */\n\n#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN BIT(28)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE3IMR\t\t\t\t(Offset 0x1128) */\n\n#define BIT_FS_BCNDMA4_INT_EN BIT(27)\n#define BIT_FS_BCNDMA3_INT_EN BIT(26)\n#define BIT_FS_BCNDMA2_INT_EN BIT(25)\n#define BIT_FS_BCNDMA1_INT_EN BIT(24)\n#define BIT_FS_BCNDMA0_MB7_INT_EN BIT(23)\n#define BIT_FS_BCNDMA0_MB6_INT_EN BIT(22)\n#define BIT_FS_BCNDMA0_MB5_INT_EN BIT(21)\n#define BIT_FS_BCNDMA0_MB4_INT_EN BIT(20)\n#define BIT_FS_BCNDMA0_MB3_INT_EN BIT(19)\n#define BIT_FS_BCNDMA0_MB2_INT_EN BIT(18)\n#define BIT_FS_BCNDMA0_MB1_INT_EN BIT(17)\n#define BIT_FS_BCNDMA0_INT_EN BIT(16)\n#define BIT_FS_MTI_BCNIVLEAR_INT__EN BIT(15)\n#define BIT_FS_BCNERLY4_INT_EN BIT(11)\n#define BIT_FS_BCNERLY3_INT_EN BIT(10)\n#define BIT_FS_BCNERLY2_INT_EN BIT(9)\n#define BIT_FS_BCNERLY1_INT_EN BIT(8)\n#define BIT_FS_BCNERLY0_MB7INT_EN BIT(7)\n#define BIT_FS_BCNERLY0_MB6INT_EN BIT(6)\n#define BIT_FS_BCNERLY0_MB5INT_EN BIT(5)\n#define BIT_FS_BCNERLY0_MB4INT_EN BIT(4)\n#define BIT_FS_BCNERLY0_MB3INT_EN BIT(3)\n#define BIT_FS_BCNERLY0_MB2INT_EN BIT(2)\n#define BIT_FS_BCNERLY0_MB1INT_EN BIT(1)\n#define BIT_FS_BCNERLY0_INT_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE3ISR\t\t\t\t(Offset 0x112C) */\n\n#define BIT_FS_BCNELY4_AGGR_INT BIT(31)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE3ISR\t\t\t\t(Offset 0x112C) */\n\n#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT BIT(31)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE3ISR\t\t\t\t(Offset 0x112C) */\n\n#define BIT_FS_BCNELY3_AGGR_INT BIT(30)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE3ISR\t\t\t\t(Offset 0x112C) */\n\n#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT BIT(30)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE3ISR\t\t\t\t(Offset 0x112C) */\n\n#define BIT_FS_BCNELY2_AGGR_INT BIT(29)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE3ISR\t\t\t\t(Offset 0x112C) */\n\n#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT BIT(29)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE3ISR\t\t\t\t(Offset 0x112C) */\n\n#define BIT_FS_BCNELY1_AGGR_INT BIT(28)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE3ISR\t\t\t\t(Offset 0x112C) */\n\n#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT BIT(28)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE3ISR\t\t\t\t(Offset 0x112C) */\n\n#define BIT_FS_BCNDMA4_INT BIT(27)\n#define BIT_FS_BCNDMA3_INT BIT(26)\n#define BIT_FS_BCNDMA2_INT BIT(25)\n#define BIT_FS_BCNDMA1_INT BIT(24)\n#define BIT_FS_BCNDMA0_MB7_INT BIT(23)\n#define BIT_FS_BCNDMA0_MB6_INT BIT(22)\n#define BIT_FS_BCNDMA0_MB5_INT BIT(21)\n#define BIT_FS_BCNDMA0_MB4_INT BIT(20)\n#define BIT_FS_BCNDMA0_MB3_INT BIT(19)\n#define BIT_FS_BCNDMA0_MB2_INT BIT(18)\n#define BIT_FS_BCNDMA0_MB1_INT BIT(17)\n#define BIT_FS_BCNDMA0_INT BIT(16)\n#define BIT_FS_MTI_BCNIVLEAR_INT BIT(15)\n#define BIT_FS_BCNERLY4_INT BIT(11)\n#define BIT_FS_BCNERLY3_INT BIT(10)\n#define BIT_FS_BCNERLY2_INT BIT(9)\n#define BIT_FS_BCNERLY1_INT BIT(8)\n#define BIT_FS_BCNERLY0_MB7INT BIT(7)\n#define BIT_FS_BCNERLY0_MB6INT BIT(6)\n#define BIT_FS_BCNERLY0_MB5INT BIT(5)\n#define BIT_FS_BCNERLY0_MB4INT BIT(4)\n#define BIT_FS_BCNERLY0_MB3INT BIT(3)\n#define BIT_FS_BCNERLY0_MB2INT BIT(2)\n#define BIT_FS_BCNERLY0_MB1INT BIT(1)\n#define BIT_FS_BCNERLY0_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT4_PKTIN_INT_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI3_TXPKTIN_INT_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT3_PKTIN_INT_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI2_TXPKTIN_INT_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT2_PKTIN_INT_EN BIT(17)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI1_TXPKTIN_INT_EN BIT(17)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT1_PKTIN_INT_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI0_TXPKTIN_INT_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT4_RXUCMD0_OK_INT_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI3_RX_UMD0_INT_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT4_RXUCMD1_OK_INT_EN BIT(14)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI3_RX_UMD1_INT_EN BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT4_RXBCMD0_OK_INT_EN BIT(13)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI3_RX_BMD0_INT_EN BIT(13)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT4_RXBCMD1_OK_INT_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI3_RX_BMD1_INT_EN BIT(12)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT3_RXUCMD0_OK_INT_EN BIT(11)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI2_RX_UMD0_INT_EN BIT(11)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT3_RXUCMD1_OK_INT_EN BIT(10)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI2_RX_UMD1_INT_EN BIT(10)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT3_RXBCMD0_OK_INT_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI2_RX_BMD0_INT_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT3_RXBCMD1_OK_INT_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI2_RX_BMD1_INT_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT2_RXUCMD0_OK_INT_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI1_RX_UMD0_INT_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT2_RXUCMD1_OK_INT_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI1_RX_UMD1_INT_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT2_RXBCMD0_OK_INT_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI1_RX_BMD0_INT_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT2_RXBCMD1_OK_INT_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI1_RX_BMD1_INT_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT1_RXUCMD0_OK_INT_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI0_RX_UMD0_INT_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT1_RXUCMD1_OK_INT_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI0_RX_UMD1_INT_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_DMEM1_WPTR_UPDATE_INT_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT1_RXBCMD0_OK_INT_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI0_RX_BMD0_INT_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_PORT1_RXBCMD1_OK_INT_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4IMR\t\t\t\t(Offset 0x1130) */\n\n#define BIT_FS_CLI0_RX_BMD1_INT_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT4_PKTIN_INT BIT(19)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI3_TXPKTIN_INT BIT(19)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT3_PKTIN_INT BIT(18)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI2_TXPKTIN_INT BIT(18)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT2_PKTIN_INT BIT(17)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI1_TXPKTIN_INT BIT(17)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT1_PKTIN_INT BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI0_TXPKTIN_INT BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT4_RXUCMD0_OK_INT BIT(15)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI3_RX_UMD0_INT BIT(15)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT4_RXUCMD1_OK_INT BIT(14)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI3_RX_UMD1_INT BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT4_RXBCMD0_OK_INT BIT(13)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI3_RX_BMD0_INT BIT(13)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT4_RXBCMD1_OK_INT BIT(12)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI3_RX_BMD1_INT BIT(12)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT3_RXUCMD0_OK_INT BIT(11)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI2_RX_UMD0_INT BIT(11)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT3_RXUCMD1_OK_INT BIT(10)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI2_RX_UMD1_INT BIT(10)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT3_RXBCMD0_OK_INT BIT(9)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI2_RX_BMD0_INT BIT(9)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT3_RXBCMD1_OK_INT BIT(8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI2_RX_BMD1_INT BIT(8)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT2_RXUCMD0_OK_INT BIT(7)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI1_RX_UMD0_INT BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT2_RXUCMD1_OK_INT BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI1_RX_UMD1_INT BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT2_RXBCMD0_OK_INT BIT(5)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI1_RX_BMD0_INT BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT2_RXBCMD1_OK_INT BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI1_RX_BMD1_INT BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT1_RXUCMD0_OK_INT BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI0_RX_UMD0_INT BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT1_RXUCMD1_OK_INT BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI0_RX_UMD1_INT BIT(2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_DMEM1_WPTR_UPDATE_INT BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT1_RXBCMD0_OK_INT BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI0_RX_BMD0_INT BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_PORT1_RXBCMD1_OK_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FE4ISR\t\t\t\t(Offset 0x1134) */\n\n#define BIT_FS_CLI0_RX_BMD1_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1IMR\t\t\t\t(Offset 0x1138) */\n\n#define BIT__FT2ISR__IND_MSK BIT(30)\n#define BIT_FTM_PTT_INT_EN BIT(29)\n#define BIT_RXFTMREQ_INT_EN BIT(28)\n#define BIT_RXFTM_INT_EN BIT(27)\n#define BIT_TXFTM_INT_EN BIT(26)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1IMR\t\t\t\t(Offset 0x1138) */\n\n#define BIT_FS_H2C_CMD_OK_INT_EN BIT(25)\n#define BIT_FS_H2C_CMD_FULL_INT_EN BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1IMR\t\t\t\t(Offset 0x1138) */\n\n#define BIT_FS_MACID_PWRCHANGE5_INT_EN BIT(23)\n#define BIT_FS_MACID_PWRCHANGE4_INT_EN BIT(22)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FT1IMR\t\t\t\t(Offset 0x1138) */\n\n#define BIT_FS_MACID_SEARCH_FAIL_INT_EN BIT(22)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1IMR\t\t\t\t(Offset 0x1138) */\n\n#define BIT_FS_MACID_PWRCHANGE3_INT_EN BIT(21)\n#define BIT_FS_MACID_PWRCHANGE2_INT_EN BIT(20)\n#define BIT_FS_MACID_PWRCHANGE1_INT_EN BIT(19)\n#define BIT_FS_MACID_PWRCHANGE0_INT_EN BIT(18)\n#define BIT_FS_CTWEND2_INT_EN BIT(17)\n#define BIT_FS_CTWEND1_INT_EN BIT(16)\n#define BIT_FS_CTWEND0_INT_EN BIT(15)\n#define BIT_FS_TX_NULL1_INT_EN BIT(14)\n#define BIT_FS_TX_NULL0_INT_EN BIT(13)\n#define BIT_FS_TSF_BIT32_TOGGLE_EN BIT(12)\n#define BIT_FS_P2P_RFON2_INT_EN BIT(11)\n#define BIT_FS_P2P_RFOFF2_INT_EN BIT(10)\n#define BIT_FS_P2P_RFON1_INT_EN BIT(9)\n#define BIT_FS_P2P_RFOFF1_INT_EN BIT(8)\n#define BIT_FS_P2P_RFON0_INT_EN BIT(7)\n#define BIT_FS_P2P_RFOFF0_INT_EN BIT(6)\n#define BIT_FS_RX_UAPSDMD1_EN BIT(5)\n#define BIT_FS_RX_UAPSDMD0_EN BIT(4)\n#define BIT_FS_TRIGGER_PKT_EN BIT(3)\n#define BIT_FS_EOSP_INT_EN BIT(2)\n#define BIT_FS_RPWM2_INT_EN BIT(1)\n#define BIT_FS_RPWM_INT_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT__FT2ISR__IND_INT BIT(30)\n#define BIT_FTM_PTT_INT BIT(29)\n#define BIT_RXFTMREQ_INT BIT(28)\n#define BIT_RXFTM_INT BIT(27)\n#define BIT_TXFTM_INT BIT(26)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_H2C_CMD_OK_INT BIT(25)\n#define BIT_FS_H2C_CMD_FULL_INT BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_MACID_PWRCHANGE5_INT BIT(23)\n#define BIT_FS_MACID_PWRCHANGE4_INT BIT(22)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_MACID_SEARCH_FAIL_INT BIT(22)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_MACID_PWRCHANGE3_INT BIT(21)\n#define BIT_FS_MACID_PWRCHANGE2_INT BIT(20)\n#define BIT_FS_MACID_PWRCHANGE1_INT BIT(19)\n#define BIT_FS_MACID_PWRCHANGE0_INT BIT(18)\n#define BIT_FS_CTWEND2_INT BIT(17)\n#define BIT_FS_CTWEND1_INT BIT(16)\n#define BIT_FS_CTWEND0_INT BIT(15)\n#define BIT_FS_TX_NULL1_INT BIT(14)\n#define BIT_FS_TX_NULL0_INT BIT(13)\n#define BIT_FS_TSF_BIT32_TOGGLE_INT BIT(12)\n#define BIT_FS_P2P_RFON2_INT BIT(11)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_TXBCNOK_PORT4_INT_EN BIT(11)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_P2P_RFOFF2_INT BIT(10)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_TXBCNOK_PORT3_INT_EN BIT(10)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_P2P_RFON1_INT BIT(9)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_TXBCNOK_PORT2_INT_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_P2P_RFOFF1_INT BIT(8)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_TXBCNOK_PORT1_INT_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_P2P_RFON0_INT BIT(7)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_TXBCNERR_PORT4_INT_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_P2P_RFOFF0_INT BIT(6)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_TXBCNERR_PORT3_INT_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_RX_UAPSDMD1_INT BIT(5)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_TXBCNERR_PORT2_INT_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_RX_UAPSDMD0_INT BIT(4)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_TXBCNERR_PORT1_INT_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_TRIGGER_PKT_INT BIT(3)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_ATIM_PORT4_INT_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_EOSP_INT BIT(2)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_ATIM_PORT3_INT_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_RPWM2_INT BIT(1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_ATIM_PORT2_INT_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_RPWM_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FT1ISR\t\t\t\t(Offset 0x113C) */\n\n#define BIT_FS_ATIM_PORT1_INT_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SPWR0\t\t\t\t(Offset 0x1140) */\n\n#define BIT_SHIFT_MID_31TO0 0\n#define BIT_MASK_MID_31TO0 0xffffffffL\n#define BIT_MID_31TO0(x) (((x) & BIT_MASK_MID_31TO0) << BIT_SHIFT_MID_31TO0)\n#define BITS_MID_31TO0 (BIT_MASK_MID_31TO0 << BIT_SHIFT_MID_31TO0)\n#define BIT_CLEAR_MID_31TO0(x) ((x) & (~BITS_MID_31TO0))\n#define BIT_GET_MID_31TO0(x) (((x) >> BIT_SHIFT_MID_31TO0) & BIT_MASK_MID_31TO0)\n#define BIT_SET_MID_31TO0(x, v) (BIT_CLEAR_MID_31TO0(x) | BIT_MID_31TO0(v))\n\n/* 2 REG_SPWR1\t\t\t\t(Offset 0x1144) */\n\n#define BIT_SHIFT_MID_63TO32 0\n#define BIT_MASK_MID_63TO32 0xffffffffL\n#define BIT_MID_63TO32(x) (((x) & BIT_MASK_MID_63TO32) << BIT_SHIFT_MID_63TO32)\n#define BITS_MID_63TO32 (BIT_MASK_MID_63TO32 << BIT_SHIFT_MID_63TO32)\n#define BIT_CLEAR_MID_63TO32(x) ((x) & (~BITS_MID_63TO32))\n#define BIT_GET_MID_63TO32(x)                                                  \\\n\t(((x) >> BIT_SHIFT_MID_63TO32) & BIT_MASK_MID_63TO32)\n#define BIT_SET_MID_63TO32(x, v) (BIT_CLEAR_MID_63TO32(x) | BIT_MID_63TO32(v))\n\n/* 2 REG_SPWR2\t\t\t\t(Offset 0x1148) */\n\n#define BIT_SHIFT_MID_95O64 0\n#define BIT_MASK_MID_95O64 0xffffffffL\n#define BIT_MID_95O64(x) (((x) & BIT_MASK_MID_95O64) << BIT_SHIFT_MID_95O64)\n#define BITS_MID_95O64 (BIT_MASK_MID_95O64 << BIT_SHIFT_MID_95O64)\n#define BIT_CLEAR_MID_95O64(x) ((x) & (~BITS_MID_95O64))\n#define BIT_GET_MID_95O64(x) (((x) >> BIT_SHIFT_MID_95O64) & BIT_MASK_MID_95O64)\n#define BIT_SET_MID_95O64(x, v) (BIT_CLEAR_MID_95O64(x) | BIT_MID_95O64(v))\n\n/* 2 REG_SPWR3\t\t\t\t(Offset 0x114C) */\n\n#define BIT_SHIFT_MID_127TO96 0\n#define BIT_MASK_MID_127TO96 0xffffffffL\n#define BIT_MID_127TO96(x)                                                     \\\n\t(((x) & BIT_MASK_MID_127TO96) << BIT_SHIFT_MID_127TO96)\n#define BITS_MID_127TO96 (BIT_MASK_MID_127TO96 << BIT_SHIFT_MID_127TO96)\n#define BIT_CLEAR_MID_127TO96(x) ((x) & (~BITS_MID_127TO96))\n#define BIT_GET_MID_127TO96(x)                                                 \\\n\t(((x) >> BIT_SHIFT_MID_127TO96) & BIT_MASK_MID_127TO96)\n#define BIT_SET_MID_127TO96(x, v)                                              \\\n\t(BIT_CLEAR_MID_127TO96(x) | BIT_MID_127TO96(v))\n\n/* 2 REG_POWSEQ\t\t\t\t(Offset 0x1150) */\n\n#define BIT_SHIFT_REF_MID 0\n#define BIT_MASK_REF_MID 0x7f\n#define BIT_REF_MID(x) (((x) & BIT_MASK_REF_MID) << BIT_SHIFT_REF_MID)\n#define BITS_REF_MID (BIT_MASK_REF_MID << BIT_SHIFT_REF_MID)\n#define BIT_CLEAR_REF_MID(x) ((x) & (~BITS_REF_MID))\n#define BIT_GET_REF_MID(x) (((x) >> BIT_SHIFT_REF_MID) & BIT_MASK_REF_MID)\n#define BIT_SET_REF_MID(x, v) (BIT_CLEAR_REF_MID(x) | BIT_REF_MID(v))\n\n/* 2 REG_TC7_CTRL_V1\t\t\t\t(Offset 0x1158) */\n\n#define BIT_TC7INT_EN BIT(26)\n#define BIT_TC7MODE BIT(25)\n#define BIT_TC7EN BIT(24)\n\n#define BIT_SHIFT_TC7DATA 0\n#define BIT_MASK_TC7DATA 0xffffff\n#define BIT_TC7DATA(x) (((x) & BIT_MASK_TC7DATA) << BIT_SHIFT_TC7DATA)\n#define BITS_TC7DATA (BIT_MASK_TC7DATA << BIT_SHIFT_TC7DATA)\n#define BIT_CLEAR_TC7DATA(x) ((x) & (~BITS_TC7DATA))\n#define BIT_GET_TC7DATA(x) (((x) >> BIT_SHIFT_TC7DATA) & BIT_MASK_TC7DATA)\n#define BIT_SET_TC7DATA(x, v) (BIT_CLEAR_TC7DATA(x) | BIT_TC7DATA(v))\n\n/* 2 REG_TC8_CTRL_V1\t\t\t\t(Offset 0x115C) */\n\n#define BIT_TC8INT_EN BIT(26)\n#define BIT_TC8MODE BIT(25)\n#define BIT_TC8EN BIT(24)\n\n#define BIT_SHIFT_TC8DATA 0\n#define BIT_MASK_TC8DATA 0xffffff\n#define BIT_TC8DATA(x) (((x) & BIT_MASK_TC8DATA) << BIT_SHIFT_TC8DATA)\n#define BITS_TC8DATA (BIT_MASK_TC8DATA << BIT_SHIFT_TC8DATA)\n#define BIT_CLEAR_TC8DATA(x) ((x) & (~BITS_TC8DATA))\n#define BIT_GET_TC8DATA(x) (((x) >> BIT_SHIFT_TC8DATA) & BIT_MASK_TC8DATA)\n#define BIT_SET_TC8DATA(x, v) (BIT_CLEAR_TC8DATA(x) | BIT_TC8DATA(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3\t(Offset 0x1160) */\n\n#define BIT_SHIFT_PORT3_RXBCN_TBTT_INTERVAL 24\n#define BIT_MASK_PORT3_RXBCN_TBTT_INTERVAL 0xff\n#define BIT_PORT3_RXBCN_TBTT_INTERVAL(x)                                       \\\n\t(((x) & BIT_MASK_PORT3_RXBCN_TBTT_INTERVAL)                            \\\n\t << BIT_SHIFT_PORT3_RXBCN_TBTT_INTERVAL)\n#define BITS_PORT3_RXBCN_TBTT_INTERVAL                                         \\\n\t(BIT_MASK_PORT3_RXBCN_TBTT_INTERVAL                                    \\\n\t << BIT_SHIFT_PORT3_RXBCN_TBTT_INTERVAL)\n#define BIT_CLEAR_PORT3_RXBCN_TBTT_INTERVAL(x)                                 \\\n\t((x) & (~BITS_PORT3_RXBCN_TBTT_INTERVAL))\n#define BIT_GET_PORT3_RXBCN_TBTT_INTERVAL(x)                                   \\\n\t(((x) >> BIT_SHIFT_PORT3_RXBCN_TBTT_INTERVAL) &                        \\\n\t BIT_MASK_PORT3_RXBCN_TBTT_INTERVAL)\n#define BIT_SET_PORT3_RXBCN_TBTT_INTERVAL(x, v)                                \\\n\t(BIT_CLEAR_PORT3_RXBCN_TBTT_INTERVAL(x) |                              \\\n\t BIT_PORT3_RXBCN_TBTT_INTERVAL(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RX_BCN_TBTT_ITVL0\t\t\t(Offset 0x1160) */\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2 24\n#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2 0xff\n#define BIT_RX_BCN_TBTT_ITVL_CLIENT2(x)                                        \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2)                             \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2)\n#define BITS_RX_BCN_TBTT_ITVL_CLIENT2                                          \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2                                     \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2(x)                                  \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2))\n#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2(x)                                    \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2) &                         \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2)\n#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2(x, v)                                 \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2(x) |                               \\\n\t BIT_RX_BCN_TBTT_ITVL_CLIENT2(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3\t(Offset 0x1160) */\n\n#define BIT_SHIFT_PORT2_RXBCN_TBTT_INTERVAL 16\n#define BIT_MASK_PORT2_RXBCN_TBTT_INTERVAL 0xff\n#define BIT_PORT2_RXBCN_TBTT_INTERVAL(x)                                       \\\n\t(((x) & BIT_MASK_PORT2_RXBCN_TBTT_INTERVAL)                            \\\n\t << BIT_SHIFT_PORT2_RXBCN_TBTT_INTERVAL)\n#define BITS_PORT2_RXBCN_TBTT_INTERVAL                                         \\\n\t(BIT_MASK_PORT2_RXBCN_TBTT_INTERVAL                                    \\\n\t << BIT_SHIFT_PORT2_RXBCN_TBTT_INTERVAL)\n#define BIT_CLEAR_PORT2_RXBCN_TBTT_INTERVAL(x)                                 \\\n\t((x) & (~BITS_PORT2_RXBCN_TBTT_INTERVAL))\n#define BIT_GET_PORT2_RXBCN_TBTT_INTERVAL(x)                                   \\\n\t(((x) >> BIT_SHIFT_PORT2_RXBCN_TBTT_INTERVAL) &                        \\\n\t BIT_MASK_PORT2_RXBCN_TBTT_INTERVAL)\n#define BIT_SET_PORT2_RXBCN_TBTT_INTERVAL(x, v)                                \\\n\t(BIT_CLEAR_PORT2_RXBCN_TBTT_INTERVAL(x) |                              \\\n\t BIT_PORT2_RXBCN_TBTT_INTERVAL(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RX_BCN_TBTT_ITVL0\t\t\t(Offset 0x1160) */\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1 16\n#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1 0xff\n#define BIT_RX_BCN_TBTT_ITVL_CLIENT1(x)                                        \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1)                             \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1)\n#define BITS_RX_BCN_TBTT_ITVL_CLIENT1                                          \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1                                     \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1(x)                                  \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1))\n#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1(x)                                    \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1) &                         \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1)\n#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1(x, v)                                 \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1(x) |                               \\\n\t BIT_RX_BCN_TBTT_ITVL_CLIENT1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3\t(Offset 0x1160) */\n\n#define BIT_SHIFT_PORT1_RXBCN_TBTT_INTERVAL 8\n#define BIT_MASK_PORT1_RXBCN_TBTT_INTERVAL 0xff\n#define BIT_PORT1_RXBCN_TBTT_INTERVAL(x)                                       \\\n\t(((x) & BIT_MASK_PORT1_RXBCN_TBTT_INTERVAL)                            \\\n\t << BIT_SHIFT_PORT1_RXBCN_TBTT_INTERVAL)\n#define BITS_PORT1_RXBCN_TBTT_INTERVAL                                         \\\n\t(BIT_MASK_PORT1_RXBCN_TBTT_INTERVAL                                    \\\n\t << BIT_SHIFT_PORT1_RXBCN_TBTT_INTERVAL)\n#define BIT_CLEAR_PORT1_RXBCN_TBTT_INTERVAL(x)                                 \\\n\t((x) & (~BITS_PORT1_RXBCN_TBTT_INTERVAL))\n#define BIT_GET_PORT1_RXBCN_TBTT_INTERVAL(x)                                   \\\n\t(((x) >> BIT_SHIFT_PORT1_RXBCN_TBTT_INTERVAL) &                        \\\n\t BIT_MASK_PORT1_RXBCN_TBTT_INTERVAL)\n#define BIT_SET_PORT1_RXBCN_TBTT_INTERVAL(x, v)                                \\\n\t(BIT_CLEAR_PORT1_RXBCN_TBTT_INTERVAL(x) |                              \\\n\t BIT_PORT1_RXBCN_TBTT_INTERVAL(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RX_BCN_TBTT_ITVL0\t\t\t(Offset 0x1160) */\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0 8\n#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0 0xff\n#define BIT_RX_BCN_TBTT_ITVL_CLIENT0(x)                                        \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0)                             \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0)\n#define BITS_RX_BCN_TBTT_ITVL_CLIENT0                                          \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0                                     \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0(x)                                  \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0))\n#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0(x)                                    \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0) &                         \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0)\n#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0(x, v)                                 \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0(x) |                               \\\n\t BIT_RX_BCN_TBTT_ITVL_CLIENT0(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3\t(Offset 0x1160) */\n\n#define BIT_SHIFT_PORT0_RXBCN_TBTT_INTERVAL 0\n#define BIT_MASK_PORT0_RXBCN_TBTT_INTERVAL 0xff\n#define BIT_PORT0_RXBCN_TBTT_INTERVAL(x)                                       \\\n\t(((x) & BIT_MASK_PORT0_RXBCN_TBTT_INTERVAL)                            \\\n\t << BIT_SHIFT_PORT0_RXBCN_TBTT_INTERVAL)\n#define BITS_PORT0_RXBCN_TBTT_INTERVAL                                         \\\n\t(BIT_MASK_PORT0_RXBCN_TBTT_INTERVAL                                    \\\n\t << BIT_SHIFT_PORT0_RXBCN_TBTT_INTERVAL)\n#define BIT_CLEAR_PORT0_RXBCN_TBTT_INTERVAL(x)                                 \\\n\t((x) & (~BITS_PORT0_RXBCN_TBTT_INTERVAL))\n#define BIT_GET_PORT0_RXBCN_TBTT_INTERVAL(x)                                   \\\n\t(((x) >> BIT_SHIFT_PORT0_RXBCN_TBTT_INTERVAL) &                        \\\n\t BIT_MASK_PORT0_RXBCN_TBTT_INTERVAL)\n#define BIT_SET_PORT0_RXBCN_TBTT_INTERVAL(x, v)                                \\\n\t(BIT_CLEAR_PORT0_RXBCN_TBTT_INTERVAL(x) |                              \\\n\t BIT_PORT0_RXBCN_TBTT_INTERVAL(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RX_BCN_TBTT_ITVL0\t\t\t(Offset 0x1160) */\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0 0\n#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0 0xff\n#define BIT_RX_BCN_TBTT_ITVL_PORT0(x)                                          \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0)                               \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0)\n#define BITS_RX_BCN_TBTT_ITVL_PORT0                                            \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_PORT0 << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0(x)                                    \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0))\n#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0(x)                                      \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0) &                           \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_PORT0)\n#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0(x, v)                                   \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0(x) | BIT_RX_BCN_TBTT_ITVL_PORT0(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_RXBCN_TBTT_INTERVAL_PORT4\t\t(Offset 0x1164) */\n\n#define BIT_SHIFT_PORT4_RXBCN_TBTT_INTERVAL 0\n#define BIT_MASK_PORT4_RXBCN_TBTT_INTERVAL 0xff\n#define BIT_PORT4_RXBCN_TBTT_INTERVAL(x)                                       \\\n\t(((x) & BIT_MASK_PORT4_RXBCN_TBTT_INTERVAL)                            \\\n\t << BIT_SHIFT_PORT4_RXBCN_TBTT_INTERVAL)\n#define BITS_PORT4_RXBCN_TBTT_INTERVAL                                         \\\n\t(BIT_MASK_PORT4_RXBCN_TBTT_INTERVAL                                    \\\n\t << BIT_SHIFT_PORT4_RXBCN_TBTT_INTERVAL)\n#define BIT_CLEAR_PORT4_RXBCN_TBTT_INTERVAL(x)                                 \\\n\t((x) & (~BITS_PORT4_RXBCN_TBTT_INTERVAL))\n#define BIT_GET_PORT4_RXBCN_TBTT_INTERVAL(x)                                   \\\n\t(((x) >> BIT_SHIFT_PORT4_RXBCN_TBTT_INTERVAL) &                        \\\n\t BIT_MASK_PORT4_RXBCN_TBTT_INTERVAL)\n#define BIT_SET_PORT4_RXBCN_TBTT_INTERVAL(x, v)                                \\\n\t(BIT_CLEAR_PORT4_RXBCN_TBTT_INTERVAL(x) |                              \\\n\t BIT_PORT4_RXBCN_TBTT_INTERVAL(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RX_BCN_TBTT_ITVL1\t\t\t(Offset 0x1164) */\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3 0\n#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3 0xff\n#define BIT_RX_BCN_TBTT_ITVL_CLIENT3(x)                                        \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3)                             \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3)\n#define BITS_RX_BCN_TBTT_ITVL_CLIENT3                                          \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3                                     \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3(x)                                  \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3))\n#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3(x)                                    \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3) &                         \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3)\n#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3(x, v)                                 \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3(x) |                               \\\n\t BIT_RX_BCN_TBTT_ITVL_CLIENT3(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FWIMR1\t\t\t\t(Offset 0x1168) */\n\n#define BIT_FS_ATIM_MB15_INT_EN BIT(31)\n#define BIT_FS_ATIM_MB14_INT_EN BIT(30)\n#define BIT_FS_ATIM_MB13_INT_EN BIT(29)\n#define BIT_FS_ATIM_MB12_INT_EN BIT(28)\n#define BIT_FS_ATIM_MB11_INT_EN BIT(27)\n#define BIT_FS_ATIM_MB10_INT_EN BIT(26)\n#define BIT_FS_ATIM_MB9_INT_EN BIT(25)\n#define BIT_FS_ATIM_MB8_INT_EN BIT(24)\n#define BIT_FS_TXBCNERR_MB15_INT_EN BIT(23)\n#define BIT_FS_TXBCNERR_MB14_INT_EN BIT(22)\n#define BIT_FS_TXBCNERR_MB13_INT_EN BIT(21)\n#define BIT_FS_TXBCNERR_MB12_INT_EN BIT(20)\n#define BIT_FS_TXBCNERR_MB11_INT_EN BIT(19)\n#define BIT_FS_TXBCNERR_MB10_INT_EN BIT(18)\n#define BIT_FS_TXBCNERR_MB9_INT_EN BIT(17)\n#define BIT_FS_TXBCNERR_MB8_INT_EN BIT(16)\n#define BIT_FS_TXBCNOK_MB15_INT_EN BIT(15)\n#define BIT_FS_TXBCNOK_MB14_INT_EN BIT(14)\n#define BIT_FS_TXBCNOK_MB13_INT_EN BIT(13)\n#define BIT_FS_TXBCNOK_MB12_INT_EN BIT(12)\n#define BIT_FS_TXBCNOK_MB11_INT_EN BIT(11)\n#define BIT_FS_TXBCNOK_MB10_INT_EN BIT(10)\n#define BIT_FS_TXBCNOK_MB9_INT_EN BIT(9)\n#define BIT_FS_TXBCNOK_MB8_INT_EN BIT(8)\n#define BIT_FS_BCNERLY0_MB15INT_EN BIT(7)\n#define BIT_FS_BCNERLY0_MB14INT_EN BIT(6)\n#define BIT_FS_BCNERLY0_MB13INT_EN BIT(5)\n#define BIT_FS_BCNERLY0_MB12INT_EN BIT(4)\n#define BIT_FS_BCNERLY0_MB11INT_EN BIT(3)\n#define BIT_FS_BCNERLY0_MB10INT_EN BIT(2)\n#define BIT_FS_BCNERLY0_MB9INT_EN BIT(1)\n#define BIT_FS_BCNERLY0_MB8INT_EN BIT(0)\n\n/* 2 REG_FWISR1\t\t\t\t(Offset 0x116C) */\n\n#define BIT_FS_ATIM_MB15_INT BIT(31)\n#define BIT_FS_ATIM_MB14_INT BIT(30)\n#define BIT_FS_ATIM_MB13_INT BIT(29)\n#define BIT_FS_ATIM_MB12_INT BIT(28)\n#define BIT_FS_ATIM_MB11_INT BIT(27)\n#define BIT_FS_ATIM_MB10_INT BIT(26)\n#define BIT_FS_ATIM_MB9_INT BIT(25)\n#define BIT_FS_ATIM_MB8_INT BIT(24)\n#define BIT_FS_TXBCNERR_MB15_INT BIT(23)\n#define BIT_FS_TXBCNERR_MB14_INT BIT(22)\n#define BIT_FS_TXBCNERR_MB13_INT BIT(21)\n#define BIT_FS_TXBCNERR_MB12_INT BIT(20)\n#define BIT_FS_TXBCNERR_MB11_INT BIT(19)\n#define BIT_FS_TXBCNERR_MB10_INT BIT(18)\n#define BIT_FS_TXBCNERR_MB9_INT BIT(17)\n#define BIT_FS_TXBCNERR_MB8_INT BIT(16)\n#define BIT_FS_TXBCNOK_MB15_INT BIT(15)\n#define BIT_FS_TXBCNOK_MB14_INT BIT(14)\n#define BIT_FS_TXBCNOK_MB13_INT BIT(13)\n#define BIT_FS_TXBCNOK_MB12_INT BIT(12)\n#define BIT_FS_TXBCNOK_MB11_INT BIT(11)\n#define BIT_FS_TXBCNOK_MB10_INT BIT(10)\n#define BIT_FS_TXBCNOK_MB9_INT BIT(9)\n#define BIT_FS_TXBCNOK_MB8_INT BIT(8)\n#define BIT_FS_BCNERLY0_MB15INT BIT(7)\n#define BIT_FS_BCNERLY0_MB14INT BIT(6)\n#define BIT_FS_BCNERLY0_MB13INT BIT(5)\n#define BIT_FS_BCNERLY0_MB12INT BIT(4)\n#define BIT_FS_BCNERLY0_MB11INT BIT(3)\n#define BIT_FS_BCNERLY0_MB10INT BIT(2)\n#define BIT_FS_BCNERLY0_MB9INT BIT(1)\n#define BIT_FS_BCNERLY0_MB8INT BIT(0)\n\n/* 2 REG_FWIMR2\t\t\t\t(Offset 0x1170) */\n\n#define BIT_FS_BCNDMA0_MB15_INT_EN BIT(15)\n#define BIT_FS_BCNDMA0_MB14_INT_EN BIT(14)\n#define BIT_FS_BCNDMA0_MB13_INT_EN BIT(13)\n#define BIT_FS_BCNDMA0_MB12_INT_EN BIT(12)\n#define BIT_FS_BCNDMA0_MB11_INT_EN BIT(11)\n#define BIT_FS_BCNDMA0_MB10_INT_EN BIT(10)\n#define BIT_FS_BCNDMA0_MB9_INT_EN BIT(9)\n#define BIT_FS_BCNDMA0_MB8_INT_EN BIT(8)\n#define BIT_FS_TBTT0_MB15INT_EN BIT(7)\n#define BIT_FS_TBTT0_MB14INT_EN BIT(6)\n#define BIT_FS_TBTT0_MB13INT_EN BIT(5)\n#define BIT_FS_TBTT0_MB12INT_EN BIT(4)\n#define BIT_FS_TBTT0_MB11INT_EN BIT(3)\n#define BIT_FS_TBTT0_MB10INT_EN BIT(2)\n#define BIT_FS_TBTT0_MB9INT_EN BIT(1)\n#define BIT_FS_TBTT0_MB8INT_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_IO_WRAP_ERR_FLAG\t\t\t(Offset 0x1170) */\n\n#define BIT_IO_WRAP_ERR BIT(0)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FWISR2\t\t\t\t(Offset 0x1174) */\n\n#define BIT_FS_BCNDMA0_MB15_INT BIT(15)\n#define BIT_FS_BCNDMA0_MB14_INT BIT(14)\n#define BIT_FS_BCNDMA0_MB13_INT BIT(13)\n#define BIT_FS_BCNDMA0_MB12_INT BIT(12)\n#define BIT_FS_BCNDMA0_MB11_INT BIT(11)\n#define BIT_FS_BCNDMA0_MB10_INT BIT(10)\n#define BIT_FS_BCNDMA0_MB9_INT BIT(9)\n#define BIT_FS_BCNDMA0_MB8_INT BIT(8)\n#define BIT_FS_TBTT0_MB15INT BIT(7)\n#define BIT_FS_TBTT0_MB14INT BIT(6)\n#define BIT_FS_TBTT0_MB13INT BIT(5)\n#define BIT_FS_TBTT0_MB12INT BIT(4)\n#define BIT_FS_TBTT0_MB11INT BIT(3)\n#define BIT_FS_TBTT0_MB10INT BIT(2)\n#define BIT_FS_TBTT0_MB9INT BIT(1)\n#define BIT_FS_TBTT0_MB8INT BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FWISR3\t\t\t\t(Offset 0x117C) */\n\n#define BIT_FS_TXBCNOK_PORT4_INT BIT(11)\n#define BIT_FS_TXBCNOK_PORT3_INT BIT(10)\n#define BIT_FS_TXBCNOK_PORT2_INT BIT(9)\n#define BIT_FS_TXBCNOK_PORT1_INT BIT(8)\n#define BIT_FS_TXBCNERR_PORT4_INT BIT(7)\n#define BIT_FS_TXBCNERR_PORT3_INT BIT(6)\n#define BIT_FS_TXBCNERR_PORT2_INT BIT(5)\n#define BIT_FS_TXBCNERR_PORT1_INT BIT(4)\n#define BIT_FS_ATIM_PORT4_INT BIT(3)\n#define BIT_FS_ATIM_PORT3_INT BIT(2)\n#define BIT_FS_ATIM_PORT2_INT BIT(1)\n#define BIT_FS_ATIM_PORT1_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SPEED_SENSOR\t\t\t(Offset 0x1180) */\n\n#define BIT_DSS_1_RST_N BIT(31)\n#define BIT_DSS_1_SPEED_EN BIT(30)\n#define BIT_DSS_1_WIRE_SEL BIT(29)\n#define BIT_DSS_ENCLK BIT(28)\n\n#define BIT_SHIFT_DSS_1_RO_SEL 24\n#define BIT_MASK_DSS_1_RO_SEL 0x7\n#define BIT_DSS_1_RO_SEL(x)                                                    \\\n\t(((x) & BIT_MASK_DSS_1_RO_SEL) << BIT_SHIFT_DSS_1_RO_SEL)\n#define BITS_DSS_1_RO_SEL (BIT_MASK_DSS_1_RO_SEL << BIT_SHIFT_DSS_1_RO_SEL)\n#define BIT_CLEAR_DSS_1_RO_SEL(x) ((x) & (~BITS_DSS_1_RO_SEL))\n#define BIT_GET_DSS_1_RO_SEL(x)                                                \\\n\t(((x) >> BIT_SHIFT_DSS_1_RO_SEL) & BIT_MASK_DSS_1_RO_SEL)\n#define BIT_SET_DSS_1_RO_SEL(x, v)                                             \\\n\t(BIT_CLEAR_DSS_1_RO_SEL(x) | BIT_DSS_1_RO_SEL(v))\n\n#define BIT_SHIFT_DSS_1_DATA_IN 0\n#define BIT_MASK_DSS_1_DATA_IN 0xfffff\n#define BIT_DSS_1_DATA_IN(x)                                                   \\\n\t(((x) & BIT_MASK_DSS_1_DATA_IN) << BIT_SHIFT_DSS_1_DATA_IN)\n#define BITS_DSS_1_DATA_IN (BIT_MASK_DSS_1_DATA_IN << BIT_SHIFT_DSS_1_DATA_IN)\n#define BIT_CLEAR_DSS_1_DATA_IN(x) ((x) & (~BITS_DSS_1_DATA_IN))\n#define BIT_GET_DSS_1_DATA_IN(x)                                               \\\n\t(((x) >> BIT_SHIFT_DSS_1_DATA_IN) & BIT_MASK_DSS_1_DATA_IN)\n#define BIT_SET_DSS_1_DATA_IN(x, v)                                            \\\n\t(BIT_CLEAR_DSS_1_DATA_IN(x) | BIT_DSS_1_DATA_IN(v))\n\n/* 2 REG_SPEED_SENSOR1\t\t\t(Offset 0x1184) */\n\n#define BIT_DSS_1_READY BIT(31)\n#define BIT_DSS_1_WSORT_GO BIT(30)\n\n#define BIT_SHIFT_DSS_1_COUNT_OUT 0\n#define BIT_MASK_DSS_1_COUNT_OUT 0xfffff\n#define BIT_DSS_1_COUNT_OUT(x)                                                 \\\n\t(((x) & BIT_MASK_DSS_1_COUNT_OUT) << BIT_SHIFT_DSS_1_COUNT_OUT)\n#define BITS_DSS_1_COUNT_OUT                                                   \\\n\t(BIT_MASK_DSS_1_COUNT_OUT << BIT_SHIFT_DSS_1_COUNT_OUT)\n#define BIT_CLEAR_DSS_1_COUNT_OUT(x) ((x) & (~BITS_DSS_1_COUNT_OUT))\n#define BIT_GET_DSS_1_COUNT_OUT(x)                                             \\\n\t(((x) >> BIT_SHIFT_DSS_1_COUNT_OUT) & BIT_MASK_DSS_1_COUNT_OUT)\n#define BIT_SET_DSS_1_COUNT_OUT(x, v)                                          \\\n\t(BIT_CLEAR_DSS_1_COUNT_OUT(x) | BIT_DSS_1_COUNT_OUT(v))\n\n/* 2 REG_SPEED_SENSOR2\t\t\t(Offset 0x1188) */\n\n#define BIT_DSS_2_RST_N BIT(31)\n#define BIT_DSS_2_SPEED_EN BIT(30)\n#define BIT_DSS_2_WIRE_SEL BIT(29)\n\n#define BIT_SHIFT_DSS_2_RO_SEL 24\n#define BIT_MASK_DSS_2_RO_SEL 0x7\n#define BIT_DSS_2_RO_SEL(x)                                                    \\\n\t(((x) & BIT_MASK_DSS_2_RO_SEL) << BIT_SHIFT_DSS_2_RO_SEL)\n#define BITS_DSS_2_RO_SEL (BIT_MASK_DSS_2_RO_SEL << BIT_SHIFT_DSS_2_RO_SEL)\n#define BIT_CLEAR_DSS_2_RO_SEL(x) ((x) & (~BITS_DSS_2_RO_SEL))\n#define BIT_GET_DSS_2_RO_SEL(x)                                                \\\n\t(((x) >> BIT_SHIFT_DSS_2_RO_SEL) & BIT_MASK_DSS_2_RO_SEL)\n#define BIT_SET_DSS_2_RO_SEL(x, v)                                             \\\n\t(BIT_CLEAR_DSS_2_RO_SEL(x) | BIT_DSS_2_RO_SEL(v))\n\n#define BIT_SHIFT_DSS_2_DATA_IN 0\n#define BIT_MASK_DSS_2_DATA_IN 0xfffff\n#define BIT_DSS_2_DATA_IN(x)                                                   \\\n\t(((x) & BIT_MASK_DSS_2_DATA_IN) << BIT_SHIFT_DSS_2_DATA_IN)\n#define BITS_DSS_2_DATA_IN (BIT_MASK_DSS_2_DATA_IN << BIT_SHIFT_DSS_2_DATA_IN)\n#define BIT_CLEAR_DSS_2_DATA_IN(x) ((x) & (~BITS_DSS_2_DATA_IN))\n#define BIT_GET_DSS_2_DATA_IN(x)                                               \\\n\t(((x) >> BIT_SHIFT_DSS_2_DATA_IN) & BIT_MASK_DSS_2_DATA_IN)\n#define BIT_SET_DSS_2_DATA_IN(x, v)                                            \\\n\t(BIT_CLEAR_DSS_2_DATA_IN(x) | BIT_DSS_2_DATA_IN(v))\n\n/* 2 REG_SPEED_SENSOR3\t\t\t(Offset 0x118C) */\n\n#define BIT_DSS_2_READY BIT(31)\n#define BIT_DSS_2_WSORT_GO BIT(30)\n\n#define BIT_SHIFT_DSS_2_COUNT_OUT 0\n#define BIT_MASK_DSS_2_COUNT_OUT 0xfffff\n#define BIT_DSS_2_COUNT_OUT(x)                                                 \\\n\t(((x) & BIT_MASK_DSS_2_COUNT_OUT) << BIT_SHIFT_DSS_2_COUNT_OUT)\n#define BITS_DSS_2_COUNT_OUT                                                   \\\n\t(BIT_MASK_DSS_2_COUNT_OUT << BIT_SHIFT_DSS_2_COUNT_OUT)\n#define BIT_CLEAR_DSS_2_COUNT_OUT(x) ((x) & (~BITS_DSS_2_COUNT_OUT))\n#define BIT_GET_DSS_2_COUNT_OUT(x)                                             \\\n\t(((x) >> BIT_SHIFT_DSS_2_COUNT_OUT) & BIT_MASK_DSS_2_COUNT_OUT)\n#define BIT_SET_DSS_2_COUNT_OUT(x, v)                                          \\\n\t(BIT_CLEAR_DSS_2_COUNT_OUT(x) | BIT_DSS_2_COUNT_OUT(v))\n\n/* 2 REG_SPEED_SENSOR4\t\t\t(Offset 0x1190) */\n\n#define BIT_DSS_3_RST_N BIT(31)\n#define BIT_DSS_3_SPEED_EN BIT(30)\n#define BIT_DSS_3_WIRE_SEL BIT(29)\n\n#define BIT_SHIFT_DSS_3_RO_SEL 24\n#define BIT_MASK_DSS_3_RO_SEL 0x7\n#define BIT_DSS_3_RO_SEL(x)                                                    \\\n\t(((x) & BIT_MASK_DSS_3_RO_SEL) << BIT_SHIFT_DSS_3_RO_SEL)\n#define BITS_DSS_3_RO_SEL (BIT_MASK_DSS_3_RO_SEL << BIT_SHIFT_DSS_3_RO_SEL)\n#define BIT_CLEAR_DSS_3_RO_SEL(x) ((x) & (~BITS_DSS_3_RO_SEL))\n#define BIT_GET_DSS_3_RO_SEL(x)                                                \\\n\t(((x) >> BIT_SHIFT_DSS_3_RO_SEL) & BIT_MASK_DSS_3_RO_SEL)\n#define BIT_SET_DSS_3_RO_SEL(x, v)                                             \\\n\t(BIT_CLEAR_DSS_3_RO_SEL(x) | BIT_DSS_3_RO_SEL(v))\n\n#define BIT_SHIFT_DSS_3_DATA_IN 0\n#define BIT_MASK_DSS_3_DATA_IN 0xfffff\n#define BIT_DSS_3_DATA_IN(x)                                                   \\\n\t(((x) & BIT_MASK_DSS_3_DATA_IN) << BIT_SHIFT_DSS_3_DATA_IN)\n#define BITS_DSS_3_DATA_IN (BIT_MASK_DSS_3_DATA_IN << BIT_SHIFT_DSS_3_DATA_IN)\n#define BIT_CLEAR_DSS_3_DATA_IN(x) ((x) & (~BITS_DSS_3_DATA_IN))\n#define BIT_GET_DSS_3_DATA_IN(x)                                               \\\n\t(((x) >> BIT_SHIFT_DSS_3_DATA_IN) & BIT_MASK_DSS_3_DATA_IN)\n#define BIT_SET_DSS_3_DATA_IN(x, v)                                            \\\n\t(BIT_CLEAR_DSS_3_DATA_IN(x) | BIT_DSS_3_DATA_IN(v))\n\n/* 2 REG_SPEED_SENSOR5\t\t\t(Offset 0x1194) */\n\n#define BIT_DSS_3_READY BIT(31)\n#define BIT_DSS_3_WSORT_GO BIT(30)\n\n#define BIT_SHIFT_DSS_3_COUNT_OUT 0\n#define BIT_MASK_DSS_3_COUNT_OUT 0xfffff\n#define BIT_DSS_3_COUNT_OUT(x)                                                 \\\n\t(((x) & BIT_MASK_DSS_3_COUNT_OUT) << BIT_SHIFT_DSS_3_COUNT_OUT)\n#define BITS_DSS_3_COUNT_OUT                                                   \\\n\t(BIT_MASK_DSS_3_COUNT_OUT << BIT_SHIFT_DSS_3_COUNT_OUT)\n#define BIT_CLEAR_DSS_3_COUNT_OUT(x) ((x) & (~BITS_DSS_3_COUNT_OUT))\n#define BIT_GET_DSS_3_COUNT_OUT(x)                                             \\\n\t(((x) >> BIT_SHIFT_DSS_3_COUNT_OUT) & BIT_MASK_DSS_3_COUNT_OUT)\n#define BIT_SET_DSS_3_COUNT_OUT(x, v)                                          \\\n\t(BIT_CLEAR_DSS_3_COUNT_OUT(x) | BIT_DSS_3_COUNT_OUT(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_RXPKTBUF_1_MAX_ADDR\t\t\t(Offset 0x1198) */\n\n#define BIT_SHIFT_RXPKTBUF_SIZE 30\n#define BIT_MASK_RXPKTBUF_SIZE 0x3\n#define BIT_RXPKTBUF_SIZE(x)                                                   \\\n\t(((x) & BIT_MASK_RXPKTBUF_SIZE) << BIT_SHIFT_RXPKTBUF_SIZE)\n#define BITS_RXPKTBUF_SIZE (BIT_MASK_RXPKTBUF_SIZE << BIT_SHIFT_RXPKTBUF_SIZE)\n#define BIT_CLEAR_RXPKTBUF_SIZE(x) ((x) & (~BITS_RXPKTBUF_SIZE))\n#define BIT_GET_RXPKTBUF_SIZE(x)                                               \\\n\t(((x) >> BIT_SHIFT_RXPKTBUF_SIZE) & BIT_MASK_RXPKTBUF_SIZE)\n#define BIT_SET_RXPKTBUF_SIZE(x, v)                                            \\\n\t(BIT_CLEAR_RXPKTBUF_SIZE(x) | BIT_RXPKTBUF_SIZE(v))\n\n#define BIT_RXPKTBUF_DBG_SEL BIT(29)\n\n#define BIT_SHIFT_RXPKTBUF_1_MAX_ADDR 0\n#define BIT_MASK_RXPKTBUF_1_MAX_ADDR 0x3ffff\n#define BIT_RXPKTBUF_1_MAX_ADDR(x)                                             \\\n\t(((x) & BIT_MASK_RXPKTBUF_1_MAX_ADDR) << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR)\n#define BITS_RXPKTBUF_1_MAX_ADDR                                               \\\n\t(BIT_MASK_RXPKTBUF_1_MAX_ADDR << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR)\n#define BIT_CLEAR_RXPKTBUF_1_MAX_ADDR(x) ((x) & (~BITS_RXPKTBUF_1_MAX_ADDR))\n#define BIT_GET_RXPKTBUF_1_MAX_ADDR(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXPKTBUF_1_MAX_ADDR) & BIT_MASK_RXPKTBUF_1_MAX_ADDR)\n#define BIT_SET_RXPKTBUF_1_MAX_ADDR(x, v)                                      \\\n\t(BIT_CLEAR_RXPKTBUF_1_MAX_ADDR(x) | BIT_RXPKTBUF_1_MAX_ADDR(v))\n\n/* 2 REG_RXFWBUF_1_MAX_ADDR\t\t\t(Offset 0x119C) */\n\n#define BIT_SHIFT_RXFWBUF_1_MAX_ADDR 0\n#define BIT_MASK_RXFWBUF_1_MAX_ADDR 0xffff\n#define BIT_RXFWBUF_1_MAX_ADDR(x)                                              \\\n\t(((x) & BIT_MASK_RXFWBUF_1_MAX_ADDR) << BIT_SHIFT_RXFWBUF_1_MAX_ADDR)\n#define BITS_RXFWBUF_1_MAX_ADDR                                                \\\n\t(BIT_MASK_RXFWBUF_1_MAX_ADDR << BIT_SHIFT_RXFWBUF_1_MAX_ADDR)\n#define BIT_CLEAR_RXFWBUF_1_MAX_ADDR(x) ((x) & (~BITS_RXFWBUF_1_MAX_ADDR))\n#define BIT_GET_RXFWBUF_1_MAX_ADDR(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXFWBUF_1_MAX_ADDR) & BIT_MASK_RXFWBUF_1_MAX_ADDR)\n#define BIT_SET_RXFWBUF_1_MAX_ADDR(x, v)                                       \\\n\t(BIT_CLEAR_RXFWBUF_1_MAX_ADDR(x) | BIT_RXFWBUF_1_MAX_ADDR(v))\n\n/* 2 REG_RXPKTBUF_1_READ\t\t\t(Offset 0x11A4) */\n\n#define BIT_SHIFT_RXPKTBUF_1_READ 0\n#define BIT_MASK_RXPKTBUF_1_READ 0x3ffff\n#define BIT_RXPKTBUF_1_READ(x)                                                 \\\n\t(((x) & BIT_MASK_RXPKTBUF_1_READ) << BIT_SHIFT_RXPKTBUF_1_READ)\n#define BITS_RXPKTBUF_1_READ                                                   \\\n\t(BIT_MASK_RXPKTBUF_1_READ << BIT_SHIFT_RXPKTBUF_1_READ)\n#define BIT_CLEAR_RXPKTBUF_1_READ(x) ((x) & (~BITS_RXPKTBUF_1_READ))\n#define BIT_GET_RXPKTBUF_1_READ(x)                                             \\\n\t(((x) >> BIT_SHIFT_RXPKTBUF_1_READ) & BIT_MASK_RXPKTBUF_1_READ)\n#define BIT_SET_RXPKTBUF_1_READ(x, v)                                          \\\n\t(BIT_CLEAR_RXPKTBUF_1_READ(x) | BIT_RXPKTBUF_1_READ(v))\n\n/* 2 REG_RXPKTBUF_1_WRITE\t\t\t(Offset 0x11A8) */\n\n#define BIT_SHIFT_R_OQT_DBG_SEL 16\n#define BIT_MASK_R_OQT_DBG_SEL 0xff\n#define BIT_R_OQT_DBG_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_R_OQT_DBG_SEL) << BIT_SHIFT_R_OQT_DBG_SEL)\n#define BITS_R_OQT_DBG_SEL (BIT_MASK_R_OQT_DBG_SEL << BIT_SHIFT_R_OQT_DBG_SEL)\n#define BIT_CLEAR_R_OQT_DBG_SEL(x) ((x) & (~BITS_R_OQT_DBG_SEL))\n#define BIT_GET_R_OQT_DBG_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_R_OQT_DBG_SEL) & BIT_MASK_R_OQT_DBG_SEL)\n#define BIT_SET_R_OQT_DBG_SEL(x, v)                                            \\\n\t(BIT_CLEAR_R_OQT_DBG_SEL(x) | BIT_R_OQT_DBG_SEL(v))\n\n#define BIT_SHIFT_R_TXPKTBF_DBG_SEL 8\n#define BIT_MASK_R_TXPKTBF_DBG_SEL 0x7\n#define BIT_R_TXPKTBF_DBG_SEL(x)                                               \\\n\t(((x) & BIT_MASK_R_TXPKTBF_DBG_SEL) << BIT_SHIFT_R_TXPKTBF_DBG_SEL)\n#define BITS_R_TXPKTBF_DBG_SEL                                                 \\\n\t(BIT_MASK_R_TXPKTBF_DBG_SEL << BIT_SHIFT_R_TXPKTBF_DBG_SEL)\n#define BIT_CLEAR_R_TXPKTBF_DBG_SEL(x) ((x) & (~BITS_R_TXPKTBF_DBG_SEL))\n#define BIT_GET_R_TXPKTBF_DBG_SEL(x)                                           \\\n\t(((x) >> BIT_SHIFT_R_TXPKTBF_DBG_SEL) & BIT_MASK_R_TXPKTBF_DBG_SEL)\n#define BIT_SET_R_TXPKTBF_DBG_SEL(x, v)                                        \\\n\t(BIT_CLEAR_R_TXPKTBF_DBG_SEL(x) | BIT_R_TXPKTBF_DBG_SEL(v))\n\n#define BIT_SHIFT_R_RXPKT_DBG_SEL 6\n#define BIT_MASK_R_RXPKT_DBG_SEL 0x3\n#define BIT_R_RXPKT_DBG_SEL(x)                                                 \\\n\t(((x) & BIT_MASK_R_RXPKT_DBG_SEL) << BIT_SHIFT_R_RXPKT_DBG_SEL)\n#define BITS_R_RXPKT_DBG_SEL                                                   \\\n\t(BIT_MASK_R_RXPKT_DBG_SEL << BIT_SHIFT_R_RXPKT_DBG_SEL)\n#define BIT_CLEAR_R_RXPKT_DBG_SEL(x) ((x) & (~BITS_R_RXPKT_DBG_SEL))\n#define BIT_GET_R_RXPKT_DBG_SEL(x)                                             \\\n\t(((x) >> BIT_SHIFT_R_RXPKT_DBG_SEL) & BIT_MASK_R_RXPKT_DBG_SEL)\n#define BIT_SET_R_RXPKT_DBG_SEL(x, v)                                          \\\n\t(BIT_CLEAR_R_RXPKT_DBG_SEL(x) | BIT_R_RXPKT_DBG_SEL(v))\n\n#define BIT_SHIFT_RXPKTBUF_1_WRITE 0\n#define BIT_MASK_RXPKTBUF_1_WRITE 0x3ffff\n#define BIT_RXPKTBUF_1_WRITE(x)                                                \\\n\t(((x) & BIT_MASK_RXPKTBUF_1_WRITE) << BIT_SHIFT_RXPKTBUF_1_WRITE)\n#define BITS_RXPKTBUF_1_WRITE                                                  \\\n\t(BIT_MASK_RXPKTBUF_1_WRITE << BIT_SHIFT_RXPKTBUF_1_WRITE)\n#define BIT_CLEAR_RXPKTBUF_1_WRITE(x) ((x) & (~BITS_RXPKTBUF_1_WRITE))\n#define BIT_GET_RXPKTBUF_1_WRITE(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXPKTBUF_1_WRITE) & BIT_MASK_RXPKTBUF_1_WRITE)\n#define BIT_SET_RXPKTBUF_1_WRITE(x, v)                                         \\\n\t(BIT_CLEAR_RXPKTBUF_1_WRITE(x) | BIT_RXPKTBUF_1_WRITE(v))\n\n#define BIT_SHIFT_R_RXPKTBF_DBG_SEL 0\n#define BIT_MASK_R_RXPKTBF_DBG_SEL 0x3\n#define BIT_R_RXPKTBF_DBG_SEL(x)                                               \\\n\t(((x) & BIT_MASK_R_RXPKTBF_DBG_SEL) << BIT_SHIFT_R_RXPKTBF_DBG_SEL)\n#define BITS_R_RXPKTBF_DBG_SEL                                                 \\\n\t(BIT_MASK_R_RXPKTBF_DBG_SEL << BIT_SHIFT_R_RXPKTBF_DBG_SEL)\n#define BIT_CLEAR_R_RXPKTBF_DBG_SEL(x) ((x) & (~BITS_R_RXPKTBF_DBG_SEL))\n#define BIT_GET_R_RXPKTBF_DBG_SEL(x)                                           \\\n\t(((x) >> BIT_SHIFT_R_RXPKTBF_DBG_SEL) & BIT_MASK_R_RXPKTBF_DBG_SEL)\n#define BIT_SET_R_RXPKTBF_DBG_SEL(x, v)                                        \\\n\t(BIT_CLEAR_R_RXPKTBF_DBG_SEL(x) | BIT_R_RXPKTBF_DBG_SEL(v))\n\n/* 2 REG_RFE_CTRL_PAD_E2\t\t\t(Offset 0x11B0) */\n\n#define BIT_RFE_CTRL_ANTSW_E2 BIT(16)\n#define BIT_RFE_CTRL_PIN15_E2 BIT(15)\n#define BIT_RFE_CTRL_PIN14_E2 BIT(14)\n#define BIT_RFE_CTRL_PIN13_E2 BIT(13)\n#define BIT_RFE_CTRL_PIN12_E2 BIT(12)\n#define BIT_RFE_CTRL_PIN11_E2 BIT(11)\n#define BIT_RFE_CTRL_PIN10_E2 BIT(10)\n#define BIT_RFE_CTRL_PIN9_E2 BIT(9)\n#define BIT_RFE_CTRL_PIN8_E2 BIT(8)\n#define BIT_RFE_CTRL_PIN7_E2 BIT(7)\n#define BIT_RFE_CTRL_PIN6_E2 BIT(6)\n#define BIT_RFE_CTRL_PIN5_E2 BIT(5)\n#define BIT_RFE_CTRL_PIN4_E2 BIT(4)\n#define BIT_RFE_CTRL_PIN3_E2 BIT(3)\n#define BIT_RFE_CTRL_PIN2_E2 BIT(2)\n#define BIT_RFE_CTRL_PIN1_E2 BIT(1)\n#define BIT_RFE_CTRL_PIN0_E2 BIT(0)\n\n/* 2 REG_RFE_CTRL_PAD_SR\t\t\t(Offset 0x11B4) */\n\n#define BIT_RFE_CTRL_ANTSW_SR BIT(16)\n#define BIT_RFE_CTRL_PIN15_SR BIT(15)\n#define BIT_RFE_CTRL_PIN14_SR BIT(14)\n#define BIT_RFE_CTRL_PIN13_SR BIT(13)\n#define BIT_RFE_CTRL_PIN12_SR BIT(12)\n#define BIT_RFE_CTRL_PIN11_SR BIT(11)\n#define BIT_RFE_CTRL_PIN10_SR BIT(10)\n#define BIT_RFE_CTRL_PIN9_SR BIT(9)\n#define BIT_RFE_CTRL_PIN8_SR BIT(8)\n#define BIT_RFE_CTRL_PIN7_SR BIT(7)\n#define BIT_RFE_CTRL_PIN6_SR BIT(6)\n#define BIT_RFE_CTRL_PIN5_SR BIT(5)\n#define BIT_RFE_CTRL_PIN4_SR BIT(4)\n#define BIT_RFE_CTRL_PIN3_SR BIT(3)\n#define BIT_RFE_CTRL_PIN2_SR BIT(2)\n#define BIT_RFE_CTRL_PIN1_SR BIT(1)\n#define BIT_RFE_CTRL_PIN0_SR BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_EXT_QUEUE_REG\t\t\t(Offset 0x11C0) */\n\n#define BIT_SHIFT_PCIE_PRIORITY_SEL 0\n#define BIT_MASK_PCIE_PRIORITY_SEL 0x3\n#define BIT_PCIE_PRIORITY_SEL(x)                                               \\\n\t(((x) & BIT_MASK_PCIE_PRIORITY_SEL) << BIT_SHIFT_PCIE_PRIORITY_SEL)\n#define BITS_PCIE_PRIORITY_SEL                                                 \\\n\t(BIT_MASK_PCIE_PRIORITY_SEL << BIT_SHIFT_PCIE_PRIORITY_SEL)\n#define BIT_CLEAR_PCIE_PRIORITY_SEL(x) ((x) & (~BITS_PCIE_PRIORITY_SEL))\n#define BIT_GET_PCIE_PRIORITY_SEL(x)                                           \\\n\t(((x) >> BIT_SHIFT_PCIE_PRIORITY_SEL) & BIT_MASK_PCIE_PRIORITY_SEL)\n#define BIT_SET_PCIE_PRIORITY_SEL(x, v)                                        \\\n\t(BIT_CLEAR_PCIE_PRIORITY_SEL(x) | BIT_PCIE_PRIORITY_SEL(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_H2C_PRIORITY_SEL\t\t\t(Offset 0x11C0) */\n\n#define BIT_SHIFT_H2C_PRIORITY_SEL 0\n#define BIT_MASK_H2C_PRIORITY_SEL 0x3\n#define BIT_H2C_PRIORITY_SEL(x)                                                \\\n\t(((x) & BIT_MASK_H2C_PRIORITY_SEL) << BIT_SHIFT_H2C_PRIORITY_SEL)\n#define BITS_H2C_PRIORITY_SEL                                                  \\\n\t(BIT_MASK_H2C_PRIORITY_SEL << BIT_SHIFT_H2C_PRIORITY_SEL)\n#define BIT_CLEAR_H2C_PRIORITY_SEL(x) ((x) & (~BITS_H2C_PRIORITY_SEL))\n#define BIT_GET_H2C_PRIORITY_SEL(x)                                            \\\n\t(((x) >> BIT_SHIFT_H2C_PRIORITY_SEL) & BIT_MASK_H2C_PRIORITY_SEL)\n#define BIT_SET_H2C_PRIORITY_SEL(x, v)                                         \\\n\t(BIT_CLEAR_H2C_PRIORITY_SEL(x) | BIT_H2C_PRIORITY_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_COUNTER_CONTROL\t\t\t(Offset 0x11C4) */\n\n#define BIT_EN_USB_CNT BIT(5)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_COUNTER_CTRL\t\t\t(Offset 0x11C4) */\n\n#define BIT_USB_COUNT_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_COUNTER_CONTROL\t\t\t(Offset 0x11C4) */\n\n#define BIT_EN_PCIE_CNT BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_COUNTER_CTRL\t\t\t(Offset 0x11C4) */\n\n#define BIT_PCIE_COUNT_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_COUNTER_CONTROL\t\t\t(Offset 0x11C4) */\n\n#define BIT_RQPN_CNT BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_COUNTER_CTRL\t\t\t(Offset 0x11C4) */\n\n#define BIT_RQPN_COUNT_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_COUNTER_CONTROL\t\t\t(Offset 0x11C4) */\n\n#define BIT_RDE_CNT BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_COUNTER_CTRL\t\t\t(Offset 0x11C4) */\n\n#define BIT_RDE_COUNT_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_COUNTER_CONTROL\t\t\t(Offset 0x11C4) */\n\n#define BIT_TDE_CNT BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_COUNTER_CTRL\t\t\t(Offset 0x11C4) */\n\n#define BIT_TDE_COUNT_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_COUNTER_CONTROL\t\t\t(Offset 0x11C4) */\n\n#define BIT_DIS_CNT BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_COUNTER_CTRL\t\t\t(Offset 0x11C4) */\n\n#define BIT_DISABLE_COUNTER BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_COUNTER_TH\t\t\t\t(Offset 0x11C8) */\n\n#define BIT_CNT_ALL_MACID BIT(31)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_COUNTER_THRESHOLD\t\t\t(Offset 0x11C8) */\n\n#define BIT_SEL_ALL_MACID BIT(31)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_COUNTER_TH\t\t\t\t(Offset 0x11C8) */\n\n#define BIT_SHIFT_CNT_MACID 24\n#define BIT_MASK_CNT_MACID 0x7f\n#define BIT_CNT_MACID(x) (((x) & BIT_MASK_CNT_MACID) << BIT_SHIFT_CNT_MACID)\n#define BITS_CNT_MACID (BIT_MASK_CNT_MACID << BIT_SHIFT_CNT_MACID)\n#define BIT_CLEAR_CNT_MACID(x) ((x) & (~BITS_CNT_MACID))\n#define BIT_GET_CNT_MACID(x) (((x) >> BIT_SHIFT_CNT_MACID) & BIT_MASK_CNT_MACID)\n#define BIT_SET_CNT_MACID(x, v) (BIT_CLEAR_CNT_MACID(x) | BIT_CNT_MACID(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_COUNTER_THRESHOLD\t\t\t(Offset 0x11C8) */\n\n#define BIT_SHIFT_COUNTER_MACID 24\n#define BIT_MASK_COUNTER_MACID 0x7f\n#define BIT_COUNTER_MACID(x)                                                   \\\n\t(((x) & BIT_MASK_COUNTER_MACID) << BIT_SHIFT_COUNTER_MACID)\n#define BITS_COUNTER_MACID (BIT_MASK_COUNTER_MACID << BIT_SHIFT_COUNTER_MACID)\n#define BIT_CLEAR_COUNTER_MACID(x) ((x) & (~BITS_COUNTER_MACID))\n#define BIT_GET_COUNTER_MACID(x)                                               \\\n\t(((x) >> BIT_SHIFT_COUNTER_MACID) & BIT_MASK_COUNTER_MACID)\n#define BIT_SET_COUNTER_MACID(x, v)                                            \\\n\t(BIT_CLEAR_COUNTER_MACID(x) | BIT_COUNTER_MACID(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_COUNTER_SET\t\t\t\t(Offset 0x11CC) */\n\n#define BIT_RTS_RST BIT(24)\n#define BIT_PTCL_RST BIT(23)\n#define BIT_SCH_RST BIT(22)\n#define BIT_EDCA_RST BIT(21)\n#define BIT_RQPN_RST BIT(20)\n#define BIT_USB_RST BIT(19)\n#define BIT_PCIE_RST BIT(18)\n#define BIT_RXDMA_RST BIT(17)\n#define BIT_TXDMA_RST BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_COUNTER_SET\t\t\t\t(Offset 0x11CC) */\n\n#define BIT_SHIFT_REQUEST_RESET 16\n#define BIT_MASK_REQUEST_RESET 0xffff\n#define BIT_REQUEST_RESET(x)                                                   \\\n\t(((x) & BIT_MASK_REQUEST_RESET) << BIT_SHIFT_REQUEST_RESET)\n#define BITS_REQUEST_RESET (BIT_MASK_REQUEST_RESET << BIT_SHIFT_REQUEST_RESET)\n#define BIT_CLEAR_REQUEST_RESET(x) ((x) & (~BITS_REQUEST_RESET))\n#define BIT_GET_REQUEST_RESET(x)                                               \\\n\t(((x) >> BIT_SHIFT_REQUEST_RESET) & BIT_MASK_REQUEST_RESET)\n#define BIT_SET_REQUEST_RESET(x, v)                                            \\\n\t(BIT_CLEAR_REQUEST_RESET(x) | BIT_REQUEST_RESET(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_COUNTER_SET\t\t\t\t(Offset 0x11CC) */\n\n#define BIT_EN_RTS_START BIT(8)\n#define BIT_EN_PTCL_START BIT(7)\n#define BIT_EN_SCH_START BIT(6)\n#define BIT_EN_EDCA_START BIT(5)\n#define BIT_EN_RQPN_START BIT(4)\n#define BIT_EN_USB_START BIT(3)\n#define BIT_EN_PCIE_START BIT(2)\n#define BIT_EN_RXDMA_START BIT(1)\n#define BIT_EN_TXDMA_START BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_COUNTER_SET\t\t\t\t(Offset 0x11CC) */\n\n#define BIT_SHIFT_REQUEST_START 0\n#define BIT_MASK_REQUEST_START 0xffff\n#define BIT_REQUEST_START(x)                                                   \\\n\t(((x) & BIT_MASK_REQUEST_START) << BIT_SHIFT_REQUEST_START)\n#define BITS_REQUEST_START (BIT_MASK_REQUEST_START << BIT_SHIFT_REQUEST_START)\n#define BIT_CLEAR_REQUEST_START(x) ((x) & (~BITS_REQUEST_START))\n#define BIT_GET_REQUEST_START(x)                                               \\\n\t(((x) >> BIT_SHIFT_REQUEST_START) & BIT_MASK_REQUEST_START)\n#define BIT_SET_REQUEST_START(x, v)                                            \\\n\t(BIT_CLEAR_REQUEST_START(x) | BIT_REQUEST_START(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_COUNTER_OVERFLOW\t\t\t(Offset 0x11D0) */\n\n#define BIT_RTS_OVF BIT(8)\n#define BIT_PTCL_OVF BIT(7)\n#define BIT_SCH_OVF BIT(6)\n#define BIT_EDCA_OVF BIT(5)\n#define BIT_RQPN_OVF BIT(4)\n#define BIT_USB_OVF BIT(3)\n#define BIT_PCIE_OVF BIT(2)\n#define BIT_RXDMA_OVF BIT(1)\n#define BIT_TXDMA_OVF BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_COUNTER_OVERFLOW\t\t\t(Offset 0x11D0) */\n\n#define BIT_SHIFT_CNT_OVF_REG 0\n#define BIT_MASK_CNT_OVF_REG 0xffff\n#define BIT_CNT_OVF_REG(x)                                                     \\\n\t(((x) & BIT_MASK_CNT_OVF_REG) << BIT_SHIFT_CNT_OVF_REG)\n#define BITS_CNT_OVF_REG (BIT_MASK_CNT_OVF_REG << BIT_SHIFT_CNT_OVF_REG)\n#define BIT_CLEAR_CNT_OVF_REG(x) ((x) & (~BITS_CNT_OVF_REG))\n#define BIT_GET_CNT_OVF_REG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CNT_OVF_REG) & BIT_MASK_CNT_OVF_REG)\n#define BIT_SET_CNT_OVF_REG(x, v)                                              \\\n\t(BIT_CLEAR_CNT_OVF_REG(x) | BIT_CNT_OVF_REG(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_TDE_LEN_TH\t\t\t\t(Offset 0x11D4) */\n\n#define BIT_SHIFT_TXDMA_LEN_TH0 16\n#define BIT_MASK_TXDMA_LEN_TH0 0xffff\n#define BIT_TXDMA_LEN_TH0(x)                                                   \\\n\t(((x) & BIT_MASK_TXDMA_LEN_TH0) << BIT_SHIFT_TXDMA_LEN_TH0)\n#define BITS_TXDMA_LEN_TH0 (BIT_MASK_TXDMA_LEN_TH0 << BIT_SHIFT_TXDMA_LEN_TH0)\n#define BIT_CLEAR_TXDMA_LEN_TH0(x) ((x) & (~BITS_TXDMA_LEN_TH0))\n#define BIT_GET_TXDMA_LEN_TH0(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXDMA_LEN_TH0) & BIT_MASK_TXDMA_LEN_TH0)\n#define BIT_SET_TXDMA_LEN_TH0(x, v)                                            \\\n\t(BIT_CLEAR_TXDMA_LEN_TH0(x) | BIT_TXDMA_LEN_TH0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXDMA_LEN_THRESHOLD\t\t\t(Offset 0x11D4) */\n\n#define BIT_SHIFT_TDE_LEN_TH1 16\n#define BIT_MASK_TDE_LEN_TH1 0xffff\n#define BIT_TDE_LEN_TH1(x)                                                     \\\n\t(((x) & BIT_MASK_TDE_LEN_TH1) << BIT_SHIFT_TDE_LEN_TH1)\n#define BITS_TDE_LEN_TH1 (BIT_MASK_TDE_LEN_TH1 << BIT_SHIFT_TDE_LEN_TH1)\n#define BIT_CLEAR_TDE_LEN_TH1(x) ((x) & (~BITS_TDE_LEN_TH1))\n#define BIT_GET_TDE_LEN_TH1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TDE_LEN_TH1) & BIT_MASK_TDE_LEN_TH1)\n#define BIT_SET_TDE_LEN_TH1(x, v)                                              \\\n\t(BIT_CLEAR_TDE_LEN_TH1(x) | BIT_TDE_LEN_TH1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_TDE_LEN_TH\t\t\t\t(Offset 0x11D4) */\n\n#define BIT_SHIFT_TXDMA_LEN_TH1 0\n#define BIT_MASK_TXDMA_LEN_TH1 0xffff\n#define BIT_TXDMA_LEN_TH1(x)                                                   \\\n\t(((x) & BIT_MASK_TXDMA_LEN_TH1) << BIT_SHIFT_TXDMA_LEN_TH1)\n#define BITS_TXDMA_LEN_TH1 (BIT_MASK_TXDMA_LEN_TH1 << BIT_SHIFT_TXDMA_LEN_TH1)\n#define BIT_CLEAR_TXDMA_LEN_TH1(x) ((x) & (~BITS_TXDMA_LEN_TH1))\n#define BIT_GET_TXDMA_LEN_TH1(x)                                               \\\n\t(((x) >> BIT_SHIFT_TXDMA_LEN_TH1) & BIT_MASK_TXDMA_LEN_TH1)\n#define BIT_SET_TXDMA_LEN_TH1(x, v)                                            \\\n\t(BIT_CLEAR_TXDMA_LEN_TH1(x) | BIT_TXDMA_LEN_TH1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TXDMA_LEN_THRESHOLD\t\t\t(Offset 0x11D4) */\n\n#define BIT_SHIFT_TDE_LEN_TH0 0\n#define BIT_MASK_TDE_LEN_TH0 0xffff\n#define BIT_TDE_LEN_TH0(x)                                                     \\\n\t(((x) & BIT_MASK_TDE_LEN_TH0) << BIT_SHIFT_TDE_LEN_TH0)\n#define BITS_TDE_LEN_TH0 (BIT_MASK_TDE_LEN_TH0 << BIT_SHIFT_TDE_LEN_TH0)\n#define BIT_CLEAR_TDE_LEN_TH0(x) ((x) & (~BITS_TDE_LEN_TH0))\n#define BIT_GET_TDE_LEN_TH0(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TDE_LEN_TH0) & BIT_MASK_TDE_LEN_TH0)\n#define BIT_SET_TDE_LEN_TH0(x, v)                                              \\\n\t(BIT_CLEAR_TDE_LEN_TH0(x) | BIT_TDE_LEN_TH0(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RDE_LEN_TH\t\t\t\t(Offset 0x11D8) */\n\n#define BIT_SHIFT_RXDMA_LEN_TH0 16\n#define BIT_MASK_RXDMA_LEN_TH0 0xffff\n#define BIT_RXDMA_LEN_TH0(x)                                                   \\\n\t(((x) & BIT_MASK_RXDMA_LEN_TH0) << BIT_SHIFT_RXDMA_LEN_TH0)\n#define BITS_RXDMA_LEN_TH0 (BIT_MASK_RXDMA_LEN_TH0 << BIT_SHIFT_RXDMA_LEN_TH0)\n#define BIT_CLEAR_RXDMA_LEN_TH0(x) ((x) & (~BITS_RXDMA_LEN_TH0))\n#define BIT_GET_RXDMA_LEN_TH0(x)                                               \\\n\t(((x) >> BIT_SHIFT_RXDMA_LEN_TH0) & BIT_MASK_RXDMA_LEN_TH0)\n#define BIT_SET_RXDMA_LEN_TH0(x, v)                                            \\\n\t(BIT_CLEAR_RXDMA_LEN_TH0(x) | BIT_RXDMA_LEN_TH0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXDMA_LEN_THRESHOLD\t\t\t(Offset 0x11D8) */\n\n#define BIT_SHIFT_RDE_LEN_TH1 16\n#define BIT_MASK_RDE_LEN_TH1 0xffff\n#define BIT_RDE_LEN_TH1(x)                                                     \\\n\t(((x) & BIT_MASK_RDE_LEN_TH1) << BIT_SHIFT_RDE_LEN_TH1)\n#define BITS_RDE_LEN_TH1 (BIT_MASK_RDE_LEN_TH1 << BIT_SHIFT_RDE_LEN_TH1)\n#define BIT_CLEAR_RDE_LEN_TH1(x) ((x) & (~BITS_RDE_LEN_TH1))\n#define BIT_GET_RDE_LEN_TH1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RDE_LEN_TH1) & BIT_MASK_RDE_LEN_TH1)\n#define BIT_SET_RDE_LEN_TH1(x, v)                                              \\\n\t(BIT_CLEAR_RDE_LEN_TH1(x) | BIT_RDE_LEN_TH1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_RDE_LEN_TH\t\t\t\t(Offset 0x11D8) */\n\n#define BIT_SHIFT_RXDMA_LEN_TH1 0\n#define BIT_MASK_RXDMA_LEN_TH1 0xffff\n#define BIT_RXDMA_LEN_TH1(x)                                                   \\\n\t(((x) & BIT_MASK_RXDMA_LEN_TH1) << BIT_SHIFT_RXDMA_LEN_TH1)\n#define BITS_RXDMA_LEN_TH1 (BIT_MASK_RXDMA_LEN_TH1 << BIT_SHIFT_RXDMA_LEN_TH1)\n#define BIT_CLEAR_RXDMA_LEN_TH1(x) ((x) & (~BITS_RXDMA_LEN_TH1))\n#define BIT_GET_RXDMA_LEN_TH1(x)                                               \\\n\t(((x) >> BIT_SHIFT_RXDMA_LEN_TH1) & BIT_MASK_RXDMA_LEN_TH1)\n#define BIT_SET_RXDMA_LEN_TH1(x, v)                                            \\\n\t(BIT_CLEAR_RXDMA_LEN_TH1(x) | BIT_RXDMA_LEN_TH1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXDMA_LEN_THRESHOLD\t\t\t(Offset 0x11D8) */\n\n#define BIT_SHIFT_RDE_LEN_TH0 0\n#define BIT_MASK_RDE_LEN_TH0 0xffff\n#define BIT_RDE_LEN_TH0(x)                                                     \\\n\t(((x) & BIT_MASK_RDE_LEN_TH0) << BIT_SHIFT_RDE_LEN_TH0)\n#define BITS_RDE_LEN_TH0 (BIT_MASK_RDE_LEN_TH0 << BIT_SHIFT_RDE_LEN_TH0)\n#define BIT_CLEAR_RDE_LEN_TH0(x) ((x) & (~BITS_RDE_LEN_TH0))\n#define BIT_GET_RDE_LEN_TH0(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RDE_LEN_TH0) & BIT_MASK_RDE_LEN_TH0)\n#define BIT_SET_RDE_LEN_TH0(x, v)                                              \\\n\t(BIT_CLEAR_RDE_LEN_TH0(x) | BIT_RDE_LEN_TH0(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PCIE_EXEC_TIME\t\t\t(Offset 0x11DC) */\n\n#define BIT_SHIFT_COUNTER_INTERVAL_SEL 16\n#define BIT_MASK_COUNTER_INTERVAL_SEL 0x3\n#define BIT_COUNTER_INTERVAL_SEL(x)                                            \\\n\t(((x) & BIT_MASK_COUNTER_INTERVAL_SEL)                                 \\\n\t << BIT_SHIFT_COUNTER_INTERVAL_SEL)\n#define BITS_COUNTER_INTERVAL_SEL                                              \\\n\t(BIT_MASK_COUNTER_INTERVAL_SEL << BIT_SHIFT_COUNTER_INTERVAL_SEL)\n#define BIT_CLEAR_COUNTER_INTERVAL_SEL(x) ((x) & (~BITS_COUNTER_INTERVAL_SEL))\n#define BIT_GET_COUNTER_INTERVAL_SEL(x)                                        \\\n\t(((x) >> BIT_SHIFT_COUNTER_INTERVAL_SEL) &                             \\\n\t BIT_MASK_COUNTER_INTERVAL_SEL)\n#define BIT_SET_COUNTER_INTERVAL_SEL(x, v)                                     \\\n\t(BIT_CLEAR_COUNTER_INTERVAL_SEL(x) | BIT_COUNTER_INTERVAL_SEL(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PCIE_EXEC_TIME_THRESHOLD\t\t(Offset 0x11DC) */\n\n#define BIT_SHIFT_COUNT_INT_SEL 16\n#define BIT_MASK_COUNT_INT_SEL 0x3\n#define BIT_COUNT_INT_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_COUNT_INT_SEL) << BIT_SHIFT_COUNT_INT_SEL)\n#define BITS_COUNT_INT_SEL (BIT_MASK_COUNT_INT_SEL << BIT_SHIFT_COUNT_INT_SEL)\n#define BIT_CLEAR_COUNT_INT_SEL(x) ((x) & (~BITS_COUNT_INT_SEL))\n#define BIT_GET_COUNT_INT_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_COUNT_INT_SEL) & BIT_MASK_COUNT_INT_SEL)\n#define BIT_SET_COUNT_INT_SEL(x, v)                                            \\\n\t(BIT_CLEAR_COUNT_INT_SEL(x) | BIT_COUNT_INT_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n/* 2 REG_PCIE_EXEC_TIME\t\t\t(Offset 0x11DC) */\n\n#define BIT_SHIFT_PCIE_TRANS_DATA_TH1 0\n#define BIT_MASK_PCIE_TRANS_DATA_TH1 0xffff\n#define BIT_PCIE_TRANS_DATA_TH1(x)                                             \\\n\t(((x) & BIT_MASK_PCIE_TRANS_DATA_TH1) << BIT_SHIFT_PCIE_TRANS_DATA_TH1)\n#define BITS_PCIE_TRANS_DATA_TH1                                               \\\n\t(BIT_MASK_PCIE_TRANS_DATA_TH1 << BIT_SHIFT_PCIE_TRANS_DATA_TH1)\n#define BIT_CLEAR_PCIE_TRANS_DATA_TH1(x) ((x) & (~BITS_PCIE_TRANS_DATA_TH1))\n#define BIT_GET_PCIE_TRANS_DATA_TH1(x)                                         \\\n\t(((x) >> BIT_SHIFT_PCIE_TRANS_DATA_TH1) & BIT_MASK_PCIE_TRANS_DATA_TH1)\n#define BIT_SET_PCIE_TRANS_DATA_TH1(x, v)                                      \\\n\t(BIT_CLEAR_PCIE_TRANS_DATA_TH1(x) | BIT_PCIE_TRANS_DATA_TH1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PCIE_EXEC_TIME_THRESHOLD\t\t(Offset 0x11DC) */\n\n#define BIT_SHIFT_EXEC_TIME_TH 0\n#define BIT_MASK_EXEC_TIME_TH 0xffff\n#define BIT_EXEC_TIME_TH(x)                                                    \\\n\t(((x) & BIT_MASK_EXEC_TIME_TH) << BIT_SHIFT_EXEC_TIME_TH)\n#define BITS_EXEC_TIME_TH (BIT_MASK_EXEC_TIME_TH << BIT_SHIFT_EXEC_TIME_TH)\n#define BIT_CLEAR_EXEC_TIME_TH(x) ((x) & (~BITS_EXEC_TIME_TH))\n#define BIT_GET_EXEC_TIME_TH(x)                                                \\\n\t(((x) >> BIT_SHIFT_EXEC_TIME_TH) & BIT_MASK_EXEC_TIME_TH)\n#define BIT_SET_EXEC_TIME_TH(x, v)                                             \\\n\t(BIT_CLEAR_EXEC_TIME_TH(x) | BIT_EXEC_TIME_TH(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_EN BIT(31)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI3_RX_UAPSDMD1_EN BIT(31)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_EN BIT(30)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI3_RX_UAPSDMD0_EN BIT(30)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT4_TRIPKT_OK_INT_EN BIT(29)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI3_TRIGGER_PKT_EN BIT(29)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT4_RX_EOSP_OK_INT_EN BIT(28)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI3_EOSP_INT_EN BIT(28)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_EN BIT(27)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI2_RX_UAPSDMD1_EN BIT(27)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_EN BIT(26)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI2_RX_UAPSDMD0_EN BIT(26)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT3_TRIPKT_OK_INT_EN BIT(25)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI2_TRIGGER_PKT_EN BIT(25)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT3_RX_EOSP_OK_INT_EN BIT(24)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI2_EOSP_INT_EN BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_EN BIT(23)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI1_RX_UAPSDMD1_EN BIT(23)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_EN BIT(22)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI1_RX_UAPSDMD0_EN BIT(22)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT2_TRIPKT_OK_INT_EN BIT(21)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI1_TRIGGER_PKT_EN BIT(21)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT2_RX_EOSP_OK_INT_EN BIT(20)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI1_EOSP_INT_EN BIT(20)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI0_RX_UAPSDMD1_EN BIT(19)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI0_RX_UAPSDMD0_EN BIT(18)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT1_TRIPKT_OK_INT_EN BIT(17)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI0_TRIGGER_PKT_EN BIT(17)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT1_RX_EOSP_OK_INT_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI0_EOSP_INT_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN BIT(8)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT4_TX_NULL1_DONE_INT_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI3_TX_NULL1_INT_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT4_TX_NULL0_DONE_INT_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI3_TX_NULL0_INT_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT3_TX_NULL1_DONE_INT_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI2_TX_NULL1_INT_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT3_TX_NULL0_DONE_INT_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI2_TX_NULL0_INT_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT2_TX_NULL1_DONE_INT_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI1_TX_NULL1_INT_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT2_TX_NULL0_DONE_INT_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI1_TX_NULL0_INT_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT1_TX_NULL1_DONE_INT_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI0_TX_NULL1_INT_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_PORT1_TX_NULL0_DONE_INT_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2IMR\t\t\t\t(Offset 0x11E0) */\n\n#define BIT_FS_CLI0_TX_NULL0_INT_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT BIT(31)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI3_RX_UAPSDMD1_INT BIT(31)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT BIT(30)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI3_RX_UAPSDMD0_INT BIT(30)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT4_TRIPKT_OK_INT BIT(29)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI3_TRIGGER_PKT_INT BIT(29)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT4_RX_EOSP_OK_INT BIT(28)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI3_EOSP_INT BIT(28)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT BIT(27)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI2_RX_UAPSDMD1_INT BIT(27)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT BIT(26)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI2_RX_UAPSDMD0_INT BIT(26)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT3_TRIPKT_OK_INT BIT(25)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI2_TRIGGER_PKT_INT BIT(25)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT3_RX_EOSP_OK_INT BIT(24)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI2_EOSP_INT BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT BIT(23)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI1_RX_UAPSDMD1_INT BIT(23)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT BIT(22)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI1_RX_UAPSDMD0_INT BIT(22)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT2_TRIPKT_OK_INT BIT(21)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI1_TRIGGER_PKT_INT BIT(21)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT2_RX_EOSP_OK_INT BIT(20)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI1_EOSP_INT BIT(20)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT BIT(19)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI0_RX_UAPSDMD1_INT BIT(19)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT BIT(18)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI0_RX_UAPSDMD0_INT BIT(18)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT1_TRIPKT_OK_INT BIT(17)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI0_TRIGGER_PKT_INT BIT(17)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT1_RX_EOSP_OK_INT BIT(16)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI0_EOSP_INT BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT BIT(9)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT BIT(9)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT BIT(8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT BIT(8)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT4_TX_NULL1_DONE_INT BIT(7)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI3_TX_NULL1_INT BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT4_TX_NULL0_DONE_INT BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI3_TX_NULL0_INT BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT3_TX_NULL1_DONE_INT BIT(5)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI2_TX_NULL1_INT BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT3_TX_NULL0_DONE_INT BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI2_TX_NULL0_INT BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT2_TX_NULL1_DONE_INT BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI1_TX_NULL1_INT BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT2_TX_NULL0_DONE_INT BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI1_TX_NULL0_INT BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT1_TX_NULL1_DONE_INT BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI0_TX_NULL1_INT BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_PORT1_TX_NULL0_DONE_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FT2ISR\t\t\t\t(Offset 0x11E4) */\n\n#define BIT_FS_CLI0_TX_NULL0_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MSG2\t\t\t\t(Offset 0x11F0) */\n\n#define BIT_SHIFT_FW_MSG2 0\n#define BIT_MASK_FW_MSG2 0xffffffffL\n#define BIT_FW_MSG2(x) (((x) & BIT_MASK_FW_MSG2) << BIT_SHIFT_FW_MSG2)\n#define BITS_FW_MSG2 (BIT_MASK_FW_MSG2 << BIT_SHIFT_FW_MSG2)\n#define BIT_CLEAR_FW_MSG2(x) ((x) & (~BITS_FW_MSG2))\n#define BIT_GET_FW_MSG2(x) (((x) >> BIT_SHIFT_FW_MSG2) & BIT_MASK_FW_MSG2)\n#define BIT_SET_FW_MSG2(x, v) (BIT_CLEAR_FW_MSG2(x) | BIT_FW_MSG2(v))\n\n/* 2 REG_MSG3\t\t\t\t(Offset 0x11F4) */\n\n#define BIT_SHIFT_FW_MSG3 0\n#define BIT_MASK_FW_MSG3 0xffffffffL\n#define BIT_FW_MSG3(x) (((x) & BIT_MASK_FW_MSG3) << BIT_SHIFT_FW_MSG3)\n#define BITS_FW_MSG3 (BIT_MASK_FW_MSG3 << BIT_SHIFT_FW_MSG3)\n#define BIT_CLEAR_FW_MSG3(x) ((x) & (~BITS_FW_MSG3))\n#define BIT_GET_FW_MSG3(x) (((x) >> BIT_SHIFT_FW_MSG3) & BIT_MASK_FW_MSG3)\n#define BIT_SET_FW_MSG3(x, v) (BIT_CLEAR_FW_MSG3(x) | BIT_FW_MSG3(v))\n\n/* 2 REG_MSG4\t\t\t\t(Offset 0x11F8) */\n\n#define BIT_SHIFT_FW_MSG4 0\n#define BIT_MASK_FW_MSG4 0xffffffffL\n#define BIT_FW_MSG4(x) (((x) & BIT_MASK_FW_MSG4) << BIT_SHIFT_FW_MSG4)\n#define BITS_FW_MSG4 (BIT_MASK_FW_MSG4 << BIT_SHIFT_FW_MSG4)\n#define BIT_CLEAR_FW_MSG4(x) ((x) & (~BITS_FW_MSG4))\n#define BIT_GET_FW_MSG4(x) (((x) >> BIT_SHIFT_FW_MSG4) & BIT_MASK_FW_MSG4)\n#define BIT_SET_FW_MSG4(x, v) (BIT_CLEAR_FW_MSG4(x) | BIT_FW_MSG4(v))\n\n/* 2 REG_MSG5\t\t\t\t(Offset 0x11FC) */\n\n#define BIT_SHIFT_FW_MSG5 0\n#define BIT_MASK_FW_MSG5 0xffffffffL\n#define BIT_FW_MSG5(x) (((x) & BIT_MASK_FW_MSG5) << BIT_SHIFT_FW_MSG5)\n#define BITS_FW_MSG5 (BIT_MASK_FW_MSG5 << BIT_SHIFT_FW_MSG5)\n#define BIT_CLEAR_FW_MSG5(x) ((x) & (~BITS_FW_MSG5))\n#define BIT_GET_FW_MSG5(x) (((x) >> BIT_SHIFT_FW_MSG5) & BIT_MASK_FW_MSG5)\n#define BIT_SET_FW_MSG5(x, v) (BIT_CLEAR_FW_MSG5(x) | BIT_FW_MSG5(v))\n\n/* 2 REG_DDMA_CH0SA\t\t\t\t(Offset 0x1200) */\n\n#define BIT_SHIFT_DDMACH0_SA 0\n#define BIT_MASK_DDMACH0_SA 0xffffffffL\n#define BIT_DDMACH0_SA(x) (((x) & BIT_MASK_DDMACH0_SA) << BIT_SHIFT_DDMACH0_SA)\n#define BITS_DDMACH0_SA (BIT_MASK_DDMACH0_SA << BIT_SHIFT_DDMACH0_SA)\n#define BIT_CLEAR_DDMACH0_SA(x) ((x) & (~BITS_DDMACH0_SA))\n#define BIT_GET_DDMACH0_SA(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DDMACH0_SA) & BIT_MASK_DDMACH0_SA)\n#define BIT_SET_DDMACH0_SA(x, v) (BIT_CLEAR_DDMACH0_SA(x) | BIT_DDMACH0_SA(v))\n\n/* 2 REG_DDMA_CH0DA\t\t\t\t(Offset 0x1204) */\n\n#define BIT_SHIFT_DDMACH0_DA 0\n#define BIT_MASK_DDMACH0_DA 0xffffffffL\n#define BIT_DDMACH0_DA(x) (((x) & BIT_MASK_DDMACH0_DA) << BIT_SHIFT_DDMACH0_DA)\n#define BITS_DDMACH0_DA (BIT_MASK_DDMACH0_DA << BIT_SHIFT_DDMACH0_DA)\n#define BIT_CLEAR_DDMACH0_DA(x) ((x) & (~BITS_DDMACH0_DA))\n#define BIT_GET_DDMACH0_DA(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DDMACH0_DA) & BIT_MASK_DDMACH0_DA)\n#define BIT_SET_DDMACH0_DA(x, v) (BIT_CLEAR_DDMACH0_DA(x) | BIT_DDMACH0_DA(v))\n\n/* 2 REG_DDMA_CH0CTRL\t\t\t(Offset 0x1208) */\n\n#define BIT_DDMACH0_OWN BIT(31)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DDMA_CH0CTRL\t\t\t(Offset 0x1208) */\n\n#define BIT_DDMACH0_IDMEM_ERR BIT(30)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DDMA_CH0CTRL\t\t\t(Offset 0x1208) */\n\n#define BIT_DDMACH0_ERR_MON BIT(30)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DDMA_CH0CTRL\t\t\t(Offset 0x1208) */\n\n#define BIT_DDMACH0_CHKSUM_EN BIT(29)\n#define BIT_DDMACH0_DA_W_DISABLE BIT(28)\n#define BIT_DDMACH0_CHKSUM_STS BIT(27)\n#define BIT_DDMACH0_DDMA_MODE BIT(26)\n#define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25)\n#define BIT_DDMACH0_CHKSUM_CONT BIT(24)\n\n#define BIT_SHIFT_DDMACH0_DLEN 0\n#define BIT_MASK_DDMACH0_DLEN 0x3ffff\n#define BIT_DDMACH0_DLEN(x)                                                    \\\n\t(((x) & BIT_MASK_DDMACH0_DLEN) << BIT_SHIFT_DDMACH0_DLEN)\n#define BITS_DDMACH0_DLEN (BIT_MASK_DDMACH0_DLEN << BIT_SHIFT_DDMACH0_DLEN)\n#define BIT_CLEAR_DDMACH0_DLEN(x) ((x) & (~BITS_DDMACH0_DLEN))\n#define BIT_GET_DDMACH0_DLEN(x)                                                \\\n\t(((x) >> BIT_SHIFT_DDMACH0_DLEN) & BIT_MASK_DDMACH0_DLEN)\n#define BIT_SET_DDMACH0_DLEN(x, v)                                             \\\n\t(BIT_CLEAR_DDMACH0_DLEN(x) | BIT_DDMACH0_DLEN(v))\n\n/* 2 REG_DDMA_CH1SA\t\t\t\t(Offset 0x1210) */\n\n#define BIT_SHIFT_DDMACH1_SA 0\n#define BIT_MASK_DDMACH1_SA 0xffffffffL\n#define BIT_DDMACH1_SA(x) (((x) & BIT_MASK_DDMACH1_SA) << BIT_SHIFT_DDMACH1_SA)\n#define BITS_DDMACH1_SA (BIT_MASK_DDMACH1_SA << BIT_SHIFT_DDMACH1_SA)\n#define BIT_CLEAR_DDMACH1_SA(x) ((x) & (~BITS_DDMACH1_SA))\n#define BIT_GET_DDMACH1_SA(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DDMACH1_SA) & BIT_MASK_DDMACH1_SA)\n#define BIT_SET_DDMACH1_SA(x, v) (BIT_CLEAR_DDMACH1_SA(x) | BIT_DDMACH1_SA(v))\n\n/* 2 REG_DDMA_CH1DA\t\t\t\t(Offset 0x1214) */\n\n#define BIT_SHIFT_DDMACH1_DA 0\n#define BIT_MASK_DDMACH1_DA 0xffffffffL\n#define BIT_DDMACH1_DA(x) (((x) & BIT_MASK_DDMACH1_DA) << BIT_SHIFT_DDMACH1_DA)\n#define BITS_DDMACH1_DA (BIT_MASK_DDMACH1_DA << BIT_SHIFT_DDMACH1_DA)\n#define BIT_CLEAR_DDMACH1_DA(x) ((x) & (~BITS_DDMACH1_DA))\n#define BIT_GET_DDMACH1_DA(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DDMACH1_DA) & BIT_MASK_DDMACH1_DA)\n#define BIT_SET_DDMACH1_DA(x, v) (BIT_CLEAR_DDMACH1_DA(x) | BIT_DDMACH1_DA(v))\n\n/* 2 REG_DDMA_CH1CTRL\t\t\t(Offset 0x1218) */\n\n#define BIT_DDMACH1_OWN BIT(31)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DDMA_CH1CTRL\t\t\t(Offset 0x1218) */\n\n#define BIT_DDMACH1_IDMEM_ERR BIT(30)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DDMA_CH1CTRL\t\t\t(Offset 0x1218) */\n\n#define BIT_DDMACH1_ERR_MON BIT(30)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DDMA_CH1CTRL\t\t\t(Offset 0x1218) */\n\n#define BIT_DDMACH1_CHKSUM_EN BIT(29)\n#define BIT_DDMACH1_DA_W_DISABLE BIT(28)\n#define BIT_DDMACH1_CHKSUM_STS BIT(27)\n#define BIT_DDMACH1_DDMA_MODE BIT(26)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_DDMA_CH1CTRL\t\t\t(Offset 0x1218) */\n\n#define BIT_DDMACH1_RESET_CHKSUM_STS BIT(25)\n#define BIT_DDMACH1_CHKSUM_CONT BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DDMA_CH1CTRL\t\t\t(Offset 0x1218) */\n\n#define BIT_SHIFT_DDMACH1_DLEN 0\n#define BIT_MASK_DDMACH1_DLEN 0x3ffff\n#define BIT_DDMACH1_DLEN(x)                                                    \\\n\t(((x) & BIT_MASK_DDMACH1_DLEN) << BIT_SHIFT_DDMACH1_DLEN)\n#define BITS_DDMACH1_DLEN (BIT_MASK_DDMACH1_DLEN << BIT_SHIFT_DDMACH1_DLEN)\n#define BIT_CLEAR_DDMACH1_DLEN(x) ((x) & (~BITS_DDMACH1_DLEN))\n#define BIT_GET_DDMACH1_DLEN(x)                                                \\\n\t(((x) >> BIT_SHIFT_DDMACH1_DLEN) & BIT_MASK_DDMACH1_DLEN)\n#define BIT_SET_DDMACH1_DLEN(x, v)                                             \\\n\t(BIT_CLEAR_DDMACH1_DLEN(x) | BIT_DDMACH1_DLEN(v))\n\n/* 2 REG_DDMA_CH2SA\t\t\t\t(Offset 0x1220) */\n\n#define BIT_SHIFT_DDMACH2_SA 0\n#define BIT_MASK_DDMACH2_SA 0xffffffffL\n#define BIT_DDMACH2_SA(x) (((x) & BIT_MASK_DDMACH2_SA) << BIT_SHIFT_DDMACH2_SA)\n#define BITS_DDMACH2_SA (BIT_MASK_DDMACH2_SA << BIT_SHIFT_DDMACH2_SA)\n#define BIT_CLEAR_DDMACH2_SA(x) ((x) & (~BITS_DDMACH2_SA))\n#define BIT_GET_DDMACH2_SA(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DDMACH2_SA) & BIT_MASK_DDMACH2_SA)\n#define BIT_SET_DDMACH2_SA(x, v) (BIT_CLEAR_DDMACH2_SA(x) | BIT_DDMACH2_SA(v))\n\n/* 2 REG_DDMA_CH2DA\t\t\t\t(Offset 0x1224) */\n\n#define BIT_SHIFT_DDMACH2_DA 0\n#define BIT_MASK_DDMACH2_DA 0xffffffffL\n#define BIT_DDMACH2_DA(x) (((x) & BIT_MASK_DDMACH2_DA) << BIT_SHIFT_DDMACH2_DA)\n#define BITS_DDMACH2_DA (BIT_MASK_DDMACH2_DA << BIT_SHIFT_DDMACH2_DA)\n#define BIT_CLEAR_DDMACH2_DA(x) ((x) & (~BITS_DDMACH2_DA))\n#define BIT_GET_DDMACH2_DA(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DDMACH2_DA) & BIT_MASK_DDMACH2_DA)\n#define BIT_SET_DDMACH2_DA(x, v) (BIT_CLEAR_DDMACH2_DA(x) | BIT_DDMACH2_DA(v))\n\n/* 2 REG_DDMA_CH2CTRL\t\t\t(Offset 0x1228) */\n\n#define BIT_DDMACH2_OWN BIT(31)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DDMA_CH2CTRL\t\t\t(Offset 0x1228) */\n\n#define BIT_DDMACH2_IDMEM_ERR BIT(30)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DDMA_CH2CTRL\t\t\t(Offset 0x1228) */\n\n#define BIT_DDMACH2_ERR_MON BIT(30)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DDMA_CH2CTRL\t\t\t(Offset 0x1228) */\n\n#define BIT_DDMACH2_CHKSUM_EN BIT(29)\n#define BIT_DDMACH2_DA_W_DISABLE BIT(28)\n#define BIT_DDMACH2_CHKSUM_STS BIT(27)\n#define BIT_DDMACH2_DDMA_MODE BIT(26)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_DDMA_CH2CTRL\t\t\t(Offset 0x1228) */\n\n#define BIT_DDMACH2_RESET_CHKSUM_STS BIT(25)\n#define BIT_DDMACH2_CHKSUM_CONT BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DDMA_CH2CTRL\t\t\t(Offset 0x1228) */\n\n#define BIT_SHIFT_DDMACH2_DLEN 0\n#define BIT_MASK_DDMACH2_DLEN 0x3ffff\n#define BIT_DDMACH2_DLEN(x)                                                    \\\n\t(((x) & BIT_MASK_DDMACH2_DLEN) << BIT_SHIFT_DDMACH2_DLEN)\n#define BITS_DDMACH2_DLEN (BIT_MASK_DDMACH2_DLEN << BIT_SHIFT_DDMACH2_DLEN)\n#define BIT_CLEAR_DDMACH2_DLEN(x) ((x) & (~BITS_DDMACH2_DLEN))\n#define BIT_GET_DDMACH2_DLEN(x)                                                \\\n\t(((x) >> BIT_SHIFT_DDMACH2_DLEN) & BIT_MASK_DDMACH2_DLEN)\n#define BIT_SET_DDMACH2_DLEN(x, v)                                             \\\n\t(BIT_CLEAR_DDMACH2_DLEN(x) | BIT_DDMACH2_DLEN(v))\n\n/* 2 REG_DDMA_CH3SA\t\t\t\t(Offset 0x1230) */\n\n#define BIT_SHIFT_DDMACH3_SA 0\n#define BIT_MASK_DDMACH3_SA 0xffffffffL\n#define BIT_DDMACH3_SA(x) (((x) & BIT_MASK_DDMACH3_SA) << BIT_SHIFT_DDMACH3_SA)\n#define BITS_DDMACH3_SA (BIT_MASK_DDMACH3_SA << BIT_SHIFT_DDMACH3_SA)\n#define BIT_CLEAR_DDMACH3_SA(x) ((x) & (~BITS_DDMACH3_SA))\n#define BIT_GET_DDMACH3_SA(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DDMACH3_SA) & BIT_MASK_DDMACH3_SA)\n#define BIT_SET_DDMACH3_SA(x, v) (BIT_CLEAR_DDMACH3_SA(x) | BIT_DDMACH3_SA(v))\n\n/* 2 REG_DDMA_CH3DA\t\t\t\t(Offset 0x1234) */\n\n#define BIT_SHIFT_DDMACH3_DA 0\n#define BIT_MASK_DDMACH3_DA 0xffffffffL\n#define BIT_DDMACH3_DA(x) (((x) & BIT_MASK_DDMACH3_DA) << BIT_SHIFT_DDMACH3_DA)\n#define BITS_DDMACH3_DA (BIT_MASK_DDMACH3_DA << BIT_SHIFT_DDMACH3_DA)\n#define BIT_CLEAR_DDMACH3_DA(x) ((x) & (~BITS_DDMACH3_DA))\n#define BIT_GET_DDMACH3_DA(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DDMACH3_DA) & BIT_MASK_DDMACH3_DA)\n#define BIT_SET_DDMACH3_DA(x, v) (BIT_CLEAR_DDMACH3_DA(x) | BIT_DDMACH3_DA(v))\n\n/* 2 REG_DDMA_CH3CTRL\t\t\t(Offset 0x1238) */\n\n#define BIT_DDMACH3_OWN BIT(31)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DDMA_CH3CTRL\t\t\t(Offset 0x1238) */\n\n#define BIT_DDMACH3_IDMEM_ERR BIT(30)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DDMA_CH3CTRL\t\t\t(Offset 0x1238) */\n\n#define BIT_DDMACH3_ERR_MON BIT(30)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DDMA_CH3CTRL\t\t\t(Offset 0x1238) */\n\n#define BIT_DDMACH3_CHKSUM_EN BIT(29)\n#define BIT_DDMACH3_DA_W_DISABLE BIT(28)\n#define BIT_DDMACH3_CHKSUM_STS BIT(27)\n#define BIT_DDMACH3_DDMA_MODE BIT(26)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_DDMA_CH3CTRL\t\t\t(Offset 0x1238) */\n\n#define BIT_DDMACH3_RESET_CHKSUM_STS BIT(25)\n#define BIT_DDMACH3_CHKSUM_CONT BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DDMA_CH3CTRL\t\t\t(Offset 0x1238) */\n\n#define BIT_SHIFT_DDMACH3_DLEN 0\n#define BIT_MASK_DDMACH3_DLEN 0x3ffff\n#define BIT_DDMACH3_DLEN(x)                                                    \\\n\t(((x) & BIT_MASK_DDMACH3_DLEN) << BIT_SHIFT_DDMACH3_DLEN)\n#define BITS_DDMACH3_DLEN (BIT_MASK_DDMACH3_DLEN << BIT_SHIFT_DDMACH3_DLEN)\n#define BIT_CLEAR_DDMACH3_DLEN(x) ((x) & (~BITS_DDMACH3_DLEN))\n#define BIT_GET_DDMACH3_DLEN(x)                                                \\\n\t(((x) >> BIT_SHIFT_DDMACH3_DLEN) & BIT_MASK_DDMACH3_DLEN)\n#define BIT_SET_DDMACH3_DLEN(x, v)                                             \\\n\t(BIT_CLEAR_DDMACH3_DLEN(x) | BIT_DDMACH3_DLEN(v))\n\n/* 2 REG_DDMA_CH4SA\t\t\t\t(Offset 0x1240) */\n\n#define BIT_SHIFT_DDMACH4_SA 0\n#define BIT_MASK_DDMACH4_SA 0xffffffffL\n#define BIT_DDMACH4_SA(x) (((x) & BIT_MASK_DDMACH4_SA) << BIT_SHIFT_DDMACH4_SA)\n#define BITS_DDMACH4_SA (BIT_MASK_DDMACH4_SA << BIT_SHIFT_DDMACH4_SA)\n#define BIT_CLEAR_DDMACH4_SA(x) ((x) & (~BITS_DDMACH4_SA))\n#define BIT_GET_DDMACH4_SA(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DDMACH4_SA) & BIT_MASK_DDMACH4_SA)\n#define BIT_SET_DDMACH4_SA(x, v) (BIT_CLEAR_DDMACH4_SA(x) | BIT_DDMACH4_SA(v))\n\n/* 2 REG_DDMA_CH4DA\t\t\t\t(Offset 0x1244) */\n\n#define BIT_SHIFT_DDMACH4_DA 0\n#define BIT_MASK_DDMACH4_DA 0xffffffffL\n#define BIT_DDMACH4_DA(x) (((x) & BIT_MASK_DDMACH4_DA) << BIT_SHIFT_DDMACH4_DA)\n#define BITS_DDMACH4_DA (BIT_MASK_DDMACH4_DA << BIT_SHIFT_DDMACH4_DA)\n#define BIT_CLEAR_DDMACH4_DA(x) ((x) & (~BITS_DDMACH4_DA))\n#define BIT_GET_DDMACH4_DA(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DDMACH4_DA) & BIT_MASK_DDMACH4_DA)\n#define BIT_SET_DDMACH4_DA(x, v) (BIT_CLEAR_DDMACH4_DA(x) | BIT_DDMACH4_DA(v))\n\n/* 2 REG_DDMA_CH4CTRL\t\t\t(Offset 0x1248) */\n\n#define BIT_DDMACH4_OWN BIT(31)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DDMA_CH4CTRL\t\t\t(Offset 0x1248) */\n\n#define BIT_DDMACH4_IDMEM_ERR BIT(30)\n#define BIT_DDMACH5_IDMEM_ERR BIT(30)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_DDMA_CH4CTRL\t\t\t(Offset 0x1248) */\n\n#define BIT_DDMACH4_ERR_MON BIT(30)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DDMA_CH4CTRL\t\t\t(Offset 0x1248) */\n\n#define BIT_DDMACH4_CHKSUM_EN BIT(29)\n#define BIT_DDMACH4_DA_W_DISABLE BIT(28)\n#define BIT_DDMACH4_CHKSUM_STS BIT(27)\n#define BIT_DDMACH4_DDMA_MODE BIT(26)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_DDMA_CH4CTRL\t\t\t(Offset 0x1248) */\n\n#define BIT_DDMACH4_RESET_CHKSUM_STS BIT(25)\n#define BIT_DDMACH5_RESET_CHKSUM_STS BIT(25)\n#define BIT_DDMACH4_CHKSUM_CONT BIT(24)\n#define BIT_DDMACH5_CHKSUM_CONT BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DDMA_CH4CTRL\t\t\t(Offset 0x1248) */\n\n#define BIT_SHIFT_DDMACH4_DLEN 0\n#define BIT_MASK_DDMACH4_DLEN 0x3ffff\n#define BIT_DDMACH4_DLEN(x)                                                    \\\n\t(((x) & BIT_MASK_DDMACH4_DLEN) << BIT_SHIFT_DDMACH4_DLEN)\n#define BITS_DDMACH4_DLEN (BIT_MASK_DDMACH4_DLEN << BIT_SHIFT_DDMACH4_DLEN)\n#define BIT_CLEAR_DDMACH4_DLEN(x) ((x) & (~BITS_DDMACH4_DLEN))\n#define BIT_GET_DDMACH4_DLEN(x)                                                \\\n\t(((x) >> BIT_SHIFT_DDMACH4_DLEN) & BIT_MASK_DDMACH4_DLEN)\n#define BIT_SET_DDMACH4_DLEN(x, v)                                             \\\n\t(BIT_CLEAR_DDMACH4_DLEN(x) | BIT_DDMACH4_DLEN(v))\n\n/* 2 REG_DDMA_CH5SA\t\t\t\t(Offset 0x1250) */\n\n#define BIT_SHIFT_DDMACH5_SA 0\n#define BIT_MASK_DDMACH5_SA 0xffffffffL\n#define BIT_DDMACH5_SA(x) (((x) & BIT_MASK_DDMACH5_SA) << BIT_SHIFT_DDMACH5_SA)\n#define BITS_DDMACH5_SA (BIT_MASK_DDMACH5_SA << BIT_SHIFT_DDMACH5_SA)\n#define BIT_CLEAR_DDMACH5_SA(x) ((x) & (~BITS_DDMACH5_SA))\n#define BIT_GET_DDMACH5_SA(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DDMACH5_SA) & BIT_MASK_DDMACH5_SA)\n#define BIT_SET_DDMACH5_SA(x, v) (BIT_CLEAR_DDMACH5_SA(x) | BIT_DDMACH5_SA(v))\n\n/* 2 REG_DDMA_CH5DA\t\t\t\t(Offset 0x1254) */\n\n#define BIT_DDMACH5_OWN BIT(31)\n#define BIT_DDMACH5_CHKSUM_EN BIT(29)\n#define BIT_DDMACH5_DA_W_DISABLE BIT(28)\n#define BIT_DDMACH5_CHKSUM_STS BIT(27)\n#define BIT_DDMACH5_DDMA_MODE BIT(26)\n\n#define BIT_SHIFT_DDMACH5_DA 0\n#define BIT_MASK_DDMACH5_DA 0xffffffffL\n#define BIT_DDMACH5_DA(x) (((x) & BIT_MASK_DDMACH5_DA) << BIT_SHIFT_DDMACH5_DA)\n#define BITS_DDMACH5_DA (BIT_MASK_DDMACH5_DA << BIT_SHIFT_DDMACH5_DA)\n#define BIT_CLEAR_DDMACH5_DA(x) ((x) & (~BITS_DDMACH5_DA))\n#define BIT_GET_DDMACH5_DA(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DDMACH5_DA) & BIT_MASK_DDMACH5_DA)\n#define BIT_SET_DDMACH5_DA(x, v) (BIT_CLEAR_DDMACH5_DA(x) | BIT_DDMACH5_DA(v))\n\n#define BIT_SHIFT_DDMACH5_DLEN 0\n#define BIT_MASK_DDMACH5_DLEN 0x3ffff\n#define BIT_DDMACH5_DLEN(x)                                                    \\\n\t(((x) & BIT_MASK_DDMACH5_DLEN) << BIT_SHIFT_DDMACH5_DLEN)\n#define BITS_DDMACH5_DLEN (BIT_MASK_DDMACH5_DLEN << BIT_SHIFT_DDMACH5_DLEN)\n#define BIT_CLEAR_DDMACH5_DLEN(x) ((x) & (~BITS_DDMACH5_DLEN))\n#define BIT_GET_DDMACH5_DLEN(x)                                                \\\n\t(((x) >> BIT_SHIFT_DDMACH5_DLEN) & BIT_MASK_DDMACH5_DLEN)\n#define BIT_SET_DDMACH5_DLEN(x, v)                                             \\\n\t(BIT_CLEAR_DDMACH5_DLEN(x) | BIT_DDMACH5_DLEN(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_REG_DDMA_CH5CTRL\t\t\t(Offset 0x1258) */\n\n#define BIT_DDMACH5_ERR_MON BIT(30)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DDMA_INT_MSK\t\t\t(Offset 0x12E0) */\n\n#define BIT_DDMACH5_MSK BIT(5)\n#define BIT_DDMACH4_MSK BIT(4)\n#define BIT_DDMACH3_MSK BIT(3)\n#define BIT_DDMACH2_MSK BIT(2)\n#define BIT_DDMACH1_MSK BIT(1)\n#define BIT_DDMACH0_MSK BIT(0)\n\n/* 2 REG_DDMA_CHSTATUS\t\t\t(Offset 0x12E8) */\n\n#define BIT_DDMACH5_BUSY BIT(5)\n#define BIT_DDMACH4_BUSY BIT(4)\n#define BIT_DDMACH3_BUSY BIT(3)\n#define BIT_DDMACH2_BUSY BIT(2)\n#define BIT_DDMACH1_BUSY BIT(1)\n#define BIT_DDMACH0_BUSY BIT(0)\n\n/* 2 REG_DDMA_CHKSUM\t\t\t\t(Offset 0x12F0) */\n\n#define BIT_SHIFT_IDDMA0_CHKSUM 0\n#define BIT_MASK_IDDMA0_CHKSUM 0xffff\n#define BIT_IDDMA0_CHKSUM(x)                                                   \\\n\t(((x) & BIT_MASK_IDDMA0_CHKSUM) << BIT_SHIFT_IDDMA0_CHKSUM)\n#define BITS_IDDMA0_CHKSUM (BIT_MASK_IDDMA0_CHKSUM << BIT_SHIFT_IDDMA0_CHKSUM)\n#define BIT_CLEAR_IDDMA0_CHKSUM(x) ((x) & (~BITS_IDDMA0_CHKSUM))\n#define BIT_GET_IDDMA0_CHKSUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_IDDMA0_CHKSUM) & BIT_MASK_IDDMA0_CHKSUM)\n#define BIT_SET_IDDMA0_CHKSUM(x, v)                                            \\\n\t(BIT_CLEAR_IDDMA0_CHKSUM(x) | BIT_IDDMA0_CHKSUM(v))\n\n/* 2 REG_DDMA_MONITOR\t\t\t(Offset 0x12FC) */\n\n#define BIT_IDDMA0_PERMU_UNDERFLOW BIT(14)\n#define BIT_IDDMA0_FIFO_UNDERFLOW BIT(13)\n#define BIT_IDDMA0_FIFO_OVERFLOW BIT(12)\n#define BIT_CH5_ERR BIT(5)\n#define BIT_CH4_ERR BIT(4)\n#define BIT_CH3_ERR BIT(3)\n#define BIT_CH2_ERR BIT(2)\n#define BIT_CH1_ERR BIT(1)\n#define BIT_CH0_ERR BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_STC_INT_CS\t\t\t\t(Offset 0x1300) */\n\n#define BIT_STC_INT_EN BIT(31)\n#define BIT_STC_INT_GRP_EN BIT(31)\n\n#define BIT_SHIFT_STC_INT_FLAG 16\n#define BIT_MASK_STC_INT_FLAG 0xff\n#define BIT_STC_INT_FLAG(x)                                                    \\\n\t(((x) & BIT_MASK_STC_INT_FLAG) << BIT_SHIFT_STC_INT_FLAG)\n#define BITS_STC_INT_FLAG (BIT_MASK_STC_INT_FLAG << BIT_SHIFT_STC_INT_FLAG)\n#define BIT_CLEAR_STC_INT_FLAG(x) ((x) & (~BITS_STC_INT_FLAG))\n#define BIT_GET_STC_INT_FLAG(x)                                                \\\n\t(((x) >> BIT_SHIFT_STC_INT_FLAG) & BIT_MASK_STC_INT_FLAG)\n#define BIT_SET_STC_INT_FLAG(x, v)                                             \\\n\t(BIT_CLEAR_STC_INT_FLAG(x) | BIT_STC_INT_FLAG(v))\n\n#define BIT_SHIFT_STC_INT_IDX 8\n#define BIT_MASK_STC_INT_IDX 0x7\n#define BIT_STC_INT_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_STC_INT_IDX) << BIT_SHIFT_STC_INT_IDX)\n#define BITS_STC_INT_IDX (BIT_MASK_STC_INT_IDX << BIT_SHIFT_STC_INT_IDX)\n#define BIT_CLEAR_STC_INT_IDX(x) ((x) & (~BITS_STC_INT_IDX))\n#define BIT_GET_STC_INT_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_STC_INT_IDX) & BIT_MASK_STC_INT_IDX)\n#define BIT_SET_STC_INT_IDX(x, v)                                              \\\n\t(BIT_CLEAR_STC_INT_IDX(x) | BIT_STC_INT_IDX(v))\n\n#define BIT_SHIFT_STC_INT_EXPECT_LS 8\n#define BIT_MASK_STC_INT_EXPECT_LS 0x3f\n#define BIT_STC_INT_EXPECT_LS(x)                                               \\\n\t(((x) & BIT_MASK_STC_INT_EXPECT_LS) << BIT_SHIFT_STC_INT_EXPECT_LS)\n#define BITS_STC_INT_EXPECT_LS                                                 \\\n\t(BIT_MASK_STC_INT_EXPECT_LS << BIT_SHIFT_STC_INT_EXPECT_LS)\n#define BIT_CLEAR_STC_INT_EXPECT_LS(x) ((x) & (~BITS_STC_INT_EXPECT_LS))\n#define BIT_GET_STC_INT_EXPECT_LS(x)                                           \\\n\t(((x) >> BIT_SHIFT_STC_INT_EXPECT_LS) & BIT_MASK_STC_INT_EXPECT_LS)\n#define BIT_SET_STC_INT_EXPECT_LS(x, v)                                        \\\n\t(BIT_CLEAR_STC_INT_EXPECT_LS(x) | BIT_STC_INT_EXPECT_LS(v))\n\n#define BIT_SHIFT_STC_INT_REALTIME_CS 0\n#define BIT_MASK_STC_INT_REALTIME_CS 0x3f\n#define BIT_STC_INT_REALTIME_CS(x)                                             \\\n\t(((x) & BIT_MASK_STC_INT_REALTIME_CS) << BIT_SHIFT_STC_INT_REALTIME_CS)\n#define BITS_STC_INT_REALTIME_CS                                               \\\n\t(BIT_MASK_STC_INT_REALTIME_CS << BIT_SHIFT_STC_INT_REALTIME_CS)\n#define BIT_CLEAR_STC_INT_REALTIME_CS(x) ((x) & (~BITS_STC_INT_REALTIME_CS))\n#define BIT_GET_STC_INT_REALTIME_CS(x)                                         \\\n\t(((x) >> BIT_SHIFT_STC_INT_REALTIME_CS) & BIT_MASK_STC_INT_REALTIME_CS)\n#define BIT_SET_STC_INT_REALTIME_CS(x, v)                                      \\\n\t(BIT_CLEAR_STC_INT_REALTIME_CS(x) | BIT_STC_INT_REALTIME_CS(v))\n\n#define BIT_SHIFT_STC_INT_EXPECT_CS 0\n#define BIT_MASK_STC_INT_EXPECT_CS 0x3f\n#define BIT_STC_INT_EXPECT_CS(x)                                               \\\n\t(((x) & BIT_MASK_STC_INT_EXPECT_CS) << BIT_SHIFT_STC_INT_EXPECT_CS)\n#define BITS_STC_INT_EXPECT_CS                                                 \\\n\t(BIT_MASK_STC_INT_EXPECT_CS << BIT_SHIFT_STC_INT_EXPECT_CS)\n#define BIT_CLEAR_STC_INT_EXPECT_CS(x) ((x) & (~BITS_STC_INT_EXPECT_CS))\n#define BIT_GET_STC_INT_EXPECT_CS(x)                                           \\\n\t(((x) >> BIT_SHIFT_STC_INT_EXPECT_CS) & BIT_MASK_STC_INT_EXPECT_CS)\n#define BIT_SET_STC_INT_EXPECT_CS(x, v)                                        \\\n\t(BIT_CLEAR_STC_INT_EXPECT_CS(x) | BIT_STC_INT_EXPECT_CS(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH4_ACH5_TXBD_NUM\t\t\t(Offset 0x130C) */\n\n#define BIT_PCIE_ACH5_FLAG BIT(30)\n\n#define BIT_SHIFT_ACH5_DESC_MODE 28\n#define BIT_MASK_ACH5_DESC_MODE 0x3\n#define BIT_ACH5_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_ACH5_DESC_MODE) << BIT_SHIFT_ACH5_DESC_MODE)\n#define BITS_ACH5_DESC_MODE                                                    \\\n\t(BIT_MASK_ACH5_DESC_MODE << BIT_SHIFT_ACH5_DESC_MODE)\n#define BIT_CLEAR_ACH5_DESC_MODE(x) ((x) & (~BITS_ACH5_DESC_MODE))\n#define BIT_GET_ACH5_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_ACH5_DESC_MODE) & BIT_MASK_ACH5_DESC_MODE)\n#define BIT_SET_ACH5_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_ACH5_DESC_MODE(x) | BIT_ACH5_DESC_MODE(v))\n\n#define BIT_SHIFT_ACH5_DESC_NUM 16\n#define BIT_MASK_ACH5_DESC_NUM 0xfff\n#define BIT_ACH5_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_ACH5_DESC_NUM) << BIT_SHIFT_ACH5_DESC_NUM)\n#define BITS_ACH5_DESC_NUM (BIT_MASK_ACH5_DESC_NUM << BIT_SHIFT_ACH5_DESC_NUM)\n#define BIT_CLEAR_ACH5_DESC_NUM(x) ((x) & (~BITS_ACH5_DESC_NUM))\n#define BIT_GET_ACH5_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH5_DESC_NUM) & BIT_MASK_ACH5_DESC_NUM)\n#define BIT_SET_ACH5_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_ACH5_DESC_NUM(x) | BIT_ACH5_DESC_NUM(v))\n\n#define BIT_PCIE_ACH4_FLAG BIT(14)\n\n#define BIT_SHIFT_ACH4_DESC_MODE 12\n#define BIT_MASK_ACH4_DESC_MODE 0x3\n#define BIT_ACH4_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_ACH4_DESC_MODE) << BIT_SHIFT_ACH4_DESC_MODE)\n#define BITS_ACH4_DESC_MODE                                                    \\\n\t(BIT_MASK_ACH4_DESC_MODE << BIT_SHIFT_ACH4_DESC_MODE)\n#define BIT_CLEAR_ACH4_DESC_MODE(x) ((x) & (~BITS_ACH4_DESC_MODE))\n#define BIT_GET_ACH4_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_ACH4_DESC_MODE) & BIT_MASK_ACH4_DESC_MODE)\n#define BIT_SET_ACH4_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_ACH4_DESC_MODE(x) | BIT_ACH4_DESC_MODE(v))\n\n#define BIT_SHIFT_ACH4_DESC_NUM 0\n#define BIT_MASK_ACH4_DESC_NUM 0xfff\n#define BIT_ACH4_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_ACH4_DESC_NUM) << BIT_SHIFT_ACH4_DESC_NUM)\n#define BITS_ACH4_DESC_NUM (BIT_MASK_ACH4_DESC_NUM << BIT_SHIFT_ACH4_DESC_NUM)\n#define BIT_CLEAR_ACH4_DESC_NUM(x) ((x) & (~BITS_ACH4_DESC_NUM))\n#define BIT_GET_ACH4_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH4_DESC_NUM) & BIT_MASK_ACH4_DESC_NUM)\n#define BIT_SET_ACH4_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_ACH4_DESC_NUM(x) | BIT_ACH4_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_CMU_DLY_CTRL\t\t\t(Offset 0x1310) */\n\n#define BIT_CMU_DLY_EN BIT(31)\n#define BIT_CMU_DLY_MODE BIT(30)\n\n#define BIT_SHIFT_CMU_DLY_PRE_DIV 0\n#define BIT_MASK_CMU_DLY_PRE_DIV 0xff\n#define BIT_CMU_DLY_PRE_DIV(x)                                                 \\\n\t(((x) & BIT_MASK_CMU_DLY_PRE_DIV) << BIT_SHIFT_CMU_DLY_PRE_DIV)\n#define BITS_CMU_DLY_PRE_DIV                                                   \\\n\t(BIT_MASK_CMU_DLY_PRE_DIV << BIT_SHIFT_CMU_DLY_PRE_DIV)\n#define BIT_CLEAR_CMU_DLY_PRE_DIV(x) ((x) & (~BITS_CMU_DLY_PRE_DIV))\n#define BIT_GET_CMU_DLY_PRE_DIV(x)                                             \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV) & BIT_MASK_CMU_DLY_PRE_DIV)\n#define BIT_SET_CMU_DLY_PRE_DIV(x, v)                                          \\\n\t(BIT_CLEAR_CMU_DLY_PRE_DIV(x) | BIT_CMU_DLY_PRE_DIV(v))\n\n/* 2 REG_CMU_DLY_CFG\t\t\t\t(Offset 0x1314) */\n\n#define BIT_SHIFT_CMU_DLY_LTR_A2I 24\n#define BIT_MASK_CMU_DLY_LTR_A2I 0xff\n#define BIT_CMU_DLY_LTR_A2I(x)                                                 \\\n\t(((x) & BIT_MASK_CMU_DLY_LTR_A2I) << BIT_SHIFT_CMU_DLY_LTR_A2I)\n#define BITS_CMU_DLY_LTR_A2I                                                   \\\n\t(BIT_MASK_CMU_DLY_LTR_A2I << BIT_SHIFT_CMU_DLY_LTR_A2I)\n#define BIT_CLEAR_CMU_DLY_LTR_A2I(x) ((x) & (~BITS_CMU_DLY_LTR_A2I))\n#define BIT_GET_CMU_DLY_LTR_A2I(x)                                             \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I) & BIT_MASK_CMU_DLY_LTR_A2I)\n#define BIT_SET_CMU_DLY_LTR_A2I(x, v)                                          \\\n\t(BIT_CLEAR_CMU_DLY_LTR_A2I(x) | BIT_CMU_DLY_LTR_A2I(v))\n\n#define BIT_SHIFT_CMU_DLY_LTR_I2A 16\n#define BIT_MASK_CMU_DLY_LTR_I2A 0xff\n#define BIT_CMU_DLY_LTR_I2A(x)                                                 \\\n\t(((x) & BIT_MASK_CMU_DLY_LTR_I2A) << BIT_SHIFT_CMU_DLY_LTR_I2A)\n#define BITS_CMU_DLY_LTR_I2A                                                   \\\n\t(BIT_MASK_CMU_DLY_LTR_I2A << BIT_SHIFT_CMU_DLY_LTR_I2A)\n#define BIT_CLEAR_CMU_DLY_LTR_I2A(x) ((x) & (~BITS_CMU_DLY_LTR_I2A))\n#define BIT_GET_CMU_DLY_LTR_I2A(x)                                             \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A) & BIT_MASK_CMU_DLY_LTR_I2A)\n#define BIT_SET_CMU_DLY_LTR_I2A(x, v)                                          \\\n\t(BIT_CLEAR_CMU_DLY_LTR_I2A(x) | BIT_CMU_DLY_LTR_I2A(v))\n\n#define BIT_SHIFT_CMU_DLY_LTR_IDLE 8\n#define BIT_MASK_CMU_DLY_LTR_IDLE 0xff\n#define BIT_CMU_DLY_LTR_IDLE(x)                                                \\\n\t(((x) & BIT_MASK_CMU_DLY_LTR_IDLE) << BIT_SHIFT_CMU_DLY_LTR_IDLE)\n#define BITS_CMU_DLY_LTR_IDLE                                                  \\\n\t(BIT_MASK_CMU_DLY_LTR_IDLE << BIT_SHIFT_CMU_DLY_LTR_IDLE)\n#define BIT_CLEAR_CMU_DLY_LTR_IDLE(x) ((x) & (~BITS_CMU_DLY_LTR_IDLE))\n#define BIT_GET_CMU_DLY_LTR_IDLE(x)                                            \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE) & BIT_MASK_CMU_DLY_LTR_IDLE)\n#define BIT_SET_CMU_DLY_LTR_IDLE(x, v)                                         \\\n\t(BIT_CLEAR_CMU_DLY_LTR_IDLE(x) | BIT_CMU_DLY_LTR_IDLE(v))\n\n#define BIT_SHIFT_CMU_DLY_LTR_ACT 0\n#define BIT_MASK_CMU_DLY_LTR_ACT 0xff\n#define BIT_CMU_DLY_LTR_ACT(x)                                                 \\\n\t(((x) & BIT_MASK_CMU_DLY_LTR_ACT) << BIT_SHIFT_CMU_DLY_LTR_ACT)\n#define BITS_CMU_DLY_LTR_ACT                                                   \\\n\t(BIT_MASK_CMU_DLY_LTR_ACT << BIT_SHIFT_CMU_DLY_LTR_ACT)\n#define BIT_CLEAR_CMU_DLY_LTR_ACT(x) ((x) & (~BITS_CMU_DLY_LTR_ACT))\n#define BIT_GET_CMU_DLY_LTR_ACT(x)                                             \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT) & BIT_MASK_CMU_DLY_LTR_ACT)\n#define BIT_SET_CMU_DLY_LTR_ACT(x, v)                                          \\\n\t(BIT_CLEAR_CMU_DLY_LTR_ACT(x) | BIT_CMU_DLY_LTR_ACT(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FWCMDQ_TXBD_IDX\t\t\t(Offset 0x1318) */\n\n#define BIT_SHIFT_FWCMDQ_HW_IDX 16\n#define BIT_MASK_FWCMDQ_HW_IDX 0xfff\n#define BIT_FWCMDQ_HW_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_FWCMDQ_HW_IDX) << BIT_SHIFT_FWCMDQ_HW_IDX)\n#define BITS_FWCMDQ_HW_IDX (BIT_MASK_FWCMDQ_HW_IDX << BIT_SHIFT_FWCMDQ_HW_IDX)\n#define BIT_CLEAR_FWCMDQ_HW_IDX(x) ((x) & (~BITS_FWCMDQ_HW_IDX))\n#define BIT_GET_FWCMDQ_HW_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_HW_IDX) & BIT_MASK_FWCMDQ_HW_IDX)\n#define BIT_SET_FWCMDQ_HW_IDX(x, v)                                            \\\n\t(BIT_CLEAR_FWCMDQ_HW_IDX(x) | BIT_FWCMDQ_HW_IDX(v))\n\n#define BIT_SHIFT_FWCMDQ_HOST_IDX 0\n#define BIT_MASK_FWCMDQ_HOST_IDX 0xfff\n#define BIT_FWCMDQ_HOST_IDX(x)                                                 \\\n\t(((x) & BIT_MASK_FWCMDQ_HOST_IDX) << BIT_SHIFT_FWCMDQ_HOST_IDX)\n#define BITS_FWCMDQ_HOST_IDX                                                   \\\n\t(BIT_MASK_FWCMDQ_HOST_IDX << BIT_SHIFT_FWCMDQ_HOST_IDX)\n#define BIT_CLEAR_FWCMDQ_HOST_IDX(x) ((x) & (~BITS_FWCMDQ_HOST_IDX))\n#define BIT_GET_FWCMDQ_HOST_IDX(x)                                             \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_HOST_IDX) & BIT_MASK_FWCMDQ_HOST_IDX)\n#define BIT_SET_FWCMDQ_HOST_IDX(x, v)                                          \\\n\t(BIT_CLEAR_FWCMDQ_HOST_IDX(x) | BIT_FWCMDQ_HOST_IDX(v))\n\n/* 2 REG_P0HI8Q_TXBD_IDX\t\t\t(Offset 0x131C) */\n\n#define BIT_SHIFT_P0HI8Q_HW_IDX 16\n#define BIT_MASK_P0HI8Q_HW_IDX 0xfff\n#define BIT_P0HI8Q_HW_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_P0HI8Q_HW_IDX) << BIT_SHIFT_P0HI8Q_HW_IDX)\n#define BITS_P0HI8Q_HW_IDX (BIT_MASK_P0HI8Q_HW_IDX << BIT_SHIFT_P0HI8Q_HW_IDX)\n#define BIT_CLEAR_P0HI8Q_HW_IDX(x) ((x) & (~BITS_P0HI8Q_HW_IDX))\n#define BIT_GET_P0HI8Q_HW_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_P0HI8Q_HW_IDX) & BIT_MASK_P0HI8Q_HW_IDX)\n#define BIT_SET_P0HI8Q_HW_IDX(x, v)                                            \\\n\t(BIT_CLEAR_P0HI8Q_HW_IDX(x) | BIT_P0HI8Q_HW_IDX(v))\n\n#define BIT_SHIFT_P0HI8Q_HOST_IDX 0\n#define BIT_MASK_P0HI8Q_HOST_IDX 0xfff\n#define BIT_P0HI8Q_HOST_IDX(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI8Q_HOST_IDX) << BIT_SHIFT_P0HI8Q_HOST_IDX)\n#define BITS_P0HI8Q_HOST_IDX                                                   \\\n\t(BIT_MASK_P0HI8Q_HOST_IDX << BIT_SHIFT_P0HI8Q_HOST_IDX)\n#define BIT_CLEAR_P0HI8Q_HOST_IDX(x) ((x) & (~BITS_P0HI8Q_HOST_IDX))\n#define BIT_GET_P0HI8Q_HOST_IDX(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI8Q_HOST_IDX) & BIT_MASK_P0HI8Q_HOST_IDX)\n#define BIT_SET_P0HI8Q_HOST_IDX(x, v)                                          \\\n\t(BIT_CLEAR_P0HI8Q_HOST_IDX(x) | BIT_P0HI8Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_H2CQ_TXBD_DESA\t\t\t(Offset 0x1320) */\n\n#define BIT_SHIFT_H2CQ_TXBD_DESA 0\n#define BIT_MASK_H2CQ_TXBD_DESA 0xffffffffffffffffL\n#define BIT_H2CQ_TXBD_DESA(x)                                                  \\\n\t(((x) & BIT_MASK_H2CQ_TXBD_DESA) << BIT_SHIFT_H2CQ_TXBD_DESA)\n#define BITS_H2CQ_TXBD_DESA                                                    \\\n\t(BIT_MASK_H2CQ_TXBD_DESA << BIT_SHIFT_H2CQ_TXBD_DESA)\n#define BIT_CLEAR_H2CQ_TXBD_DESA(x) ((x) & (~BITS_H2CQ_TXBD_DESA))\n#define BIT_GET_H2CQ_TXBD_DESA(x)                                              \\\n\t(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA) & BIT_MASK_H2CQ_TXBD_DESA)\n#define BIT_SET_H2CQ_TXBD_DESA(x, v)                                           \\\n\t(BIT_CLEAR_H2CQ_TXBD_DESA(x) | BIT_H2CQ_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_H2CQ_TXBD_DESA_L\t\t\t(Offset 0x1320) */\n\n#define BIT_SHIFT_H2CQ_TXBD_DESA_L 0\n#define BIT_MASK_H2CQ_TXBD_DESA_L 0xffffffffL\n#define BIT_H2CQ_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_H2CQ_TXBD_DESA_L) << BIT_SHIFT_H2CQ_TXBD_DESA_L)\n#define BITS_H2CQ_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_H2CQ_TXBD_DESA_L << BIT_SHIFT_H2CQ_TXBD_DESA_L)\n#define BIT_CLEAR_H2CQ_TXBD_DESA_L(x) ((x) & (~BITS_H2CQ_TXBD_DESA_L))\n#define BIT_GET_H2CQ_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_L) & BIT_MASK_H2CQ_TXBD_DESA_L)\n#define BIT_SET_H2CQ_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_H2CQ_TXBD_DESA_L(x) | BIT_H2CQ_TXBD_DESA_L(v))\n\n/* 2 REG_H2CQ_TXBD_DESA_H\t\t\t(Offset 0x1324) */\n\n#define BIT_SHIFT_H2CQ_TXBD_DESA_H 0\n#define BIT_MASK_H2CQ_TXBD_DESA_H 0xffffffffL\n#define BIT_H2CQ_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_H2CQ_TXBD_DESA_H) << BIT_SHIFT_H2CQ_TXBD_DESA_H)\n#define BITS_H2CQ_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_H2CQ_TXBD_DESA_H << BIT_SHIFT_H2CQ_TXBD_DESA_H)\n#define BIT_CLEAR_H2CQ_TXBD_DESA_H(x) ((x) & (~BITS_H2CQ_TXBD_DESA_H))\n#define BIT_GET_H2CQ_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_H) & BIT_MASK_H2CQ_TXBD_DESA_H)\n#define BIT_SET_H2CQ_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_H2CQ_TXBD_DESA_H(x) | BIT_H2CQ_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_H2CQ_TXBD_NUM\t\t\t(Offset 0x1328) */\n\n#define BIT_PCIE_H2CQ_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_H2CQ_TXBD_NUM\t\t\t(Offset 0x1328) */\n\n#define BIT_HCI_H2CQ_FLAG BIT(14)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_H2CQ_TXBD_NUM\t\t\t(Offset 0x1328) */\n\n#define BIT_SHIFT_H2CQ_DESC_MODE 12\n#define BIT_MASK_H2CQ_DESC_MODE 0x3\n#define BIT_H2CQ_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_H2CQ_DESC_MODE) << BIT_SHIFT_H2CQ_DESC_MODE)\n#define BITS_H2CQ_DESC_MODE                                                    \\\n\t(BIT_MASK_H2CQ_DESC_MODE << BIT_SHIFT_H2CQ_DESC_MODE)\n#define BIT_CLEAR_H2CQ_DESC_MODE(x) ((x) & (~BITS_H2CQ_DESC_MODE))\n#define BIT_GET_H2CQ_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_H2CQ_DESC_MODE) & BIT_MASK_H2CQ_DESC_MODE)\n#define BIT_SET_H2CQ_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_H2CQ_DESC_MODE(x) | BIT_H2CQ_DESC_MODE(v))\n\n#define BIT_SHIFT_H2CQ_DESC_NUM 0\n#define BIT_MASK_H2CQ_DESC_NUM 0xfff\n#define BIT_H2CQ_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_H2CQ_DESC_NUM) << BIT_SHIFT_H2CQ_DESC_NUM)\n#define BITS_H2CQ_DESC_NUM (BIT_MASK_H2CQ_DESC_NUM << BIT_SHIFT_H2CQ_DESC_NUM)\n#define BIT_CLEAR_H2CQ_DESC_NUM(x) ((x) & (~BITS_H2CQ_DESC_NUM))\n#define BIT_GET_H2CQ_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_H2CQ_DESC_NUM) & BIT_MASK_H2CQ_DESC_NUM)\n#define BIT_SET_H2CQ_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_H2CQ_DESC_NUM(x) | BIT_H2CQ_DESC_NUM(v))\n\n/* 2 REG_H2CQ_TXBD_IDX\t\t\t(Offset 0x132C) */\n\n#define BIT_SHIFT_H2CQ_HW_IDX 16\n#define BIT_MASK_H2CQ_HW_IDX 0xfff\n#define BIT_H2CQ_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_H2CQ_HW_IDX) << BIT_SHIFT_H2CQ_HW_IDX)\n#define BITS_H2CQ_HW_IDX (BIT_MASK_H2CQ_HW_IDX << BIT_SHIFT_H2CQ_HW_IDX)\n#define BIT_CLEAR_H2CQ_HW_IDX(x) ((x) & (~BITS_H2CQ_HW_IDX))\n#define BIT_GET_H2CQ_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_H2CQ_HW_IDX) & BIT_MASK_H2CQ_HW_IDX)\n#define BIT_SET_H2CQ_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_H2CQ_HW_IDX(x) | BIT_H2CQ_HW_IDX(v))\n\n#define BIT_SHIFT_H2CQ_HOST_IDX 0\n#define BIT_MASK_H2CQ_HOST_IDX 0xfff\n#define BIT_H2CQ_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_H2CQ_HOST_IDX) << BIT_SHIFT_H2CQ_HOST_IDX)\n#define BITS_H2CQ_HOST_IDX (BIT_MASK_H2CQ_HOST_IDX << BIT_SHIFT_H2CQ_HOST_IDX)\n#define BIT_CLEAR_H2CQ_HOST_IDX(x) ((x) & (~BITS_H2CQ_HOST_IDX))\n#define BIT_GET_H2CQ_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_H2CQ_HOST_IDX) & BIT_MASK_H2CQ_HOST_IDX)\n#define BIT_SET_H2CQ_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_H2CQ_HOST_IDX(x) | BIT_H2CQ_HOST_IDX(v))\n\n/* 2 REG_H2CQ_CSR\t\t\t\t(Offset 0x1330) */\n\n#define BIT_H2CQ_FULL BIT(31)\n#define BIT_CLR_H2CQ_HOST_IDX BIT(16)\n#define BIT_CLR_H2CQ_HW_IDX BIT(8)\n#define BIT_STOP_H2CQ BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI9Q_TXBD_IDX\t\t\t(Offset 0x1334) */\n\n#define BIT_SHIFT_P0HI9Q_HW_IDX 16\n#define BIT_MASK_P0HI9Q_HW_IDX 0xfff\n#define BIT_P0HI9Q_HW_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_P0HI9Q_HW_IDX) << BIT_SHIFT_P0HI9Q_HW_IDX)\n#define BITS_P0HI9Q_HW_IDX (BIT_MASK_P0HI9Q_HW_IDX << BIT_SHIFT_P0HI9Q_HW_IDX)\n#define BIT_CLEAR_P0HI9Q_HW_IDX(x) ((x) & (~BITS_P0HI9Q_HW_IDX))\n#define BIT_GET_P0HI9Q_HW_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_P0HI9Q_HW_IDX) & BIT_MASK_P0HI9Q_HW_IDX)\n#define BIT_SET_P0HI9Q_HW_IDX(x, v)                                            \\\n\t(BIT_CLEAR_P0HI9Q_HW_IDX(x) | BIT_P0HI9Q_HW_IDX(v))\n\n#define BIT_SHIFT_P0HI9Q_HOST_IDX 0\n#define BIT_MASK_P0HI9Q_HOST_IDX 0xfff\n#define BIT_P0HI9Q_HOST_IDX(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI9Q_HOST_IDX) << BIT_SHIFT_P0HI9Q_HOST_IDX)\n#define BITS_P0HI9Q_HOST_IDX                                                   \\\n\t(BIT_MASK_P0HI9Q_HOST_IDX << BIT_SHIFT_P0HI9Q_HOST_IDX)\n#define BIT_CLEAR_P0HI9Q_HOST_IDX(x) ((x) & (~BITS_P0HI9Q_HOST_IDX))\n#define BIT_GET_P0HI9Q_HOST_IDX(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI9Q_HOST_IDX) & BIT_MASK_P0HI9Q_HOST_IDX)\n#define BIT_SET_P0HI9Q_HOST_IDX(x, v)                                          \\\n\t(BIT_CLEAR_P0HI9Q_HOST_IDX(x) | BIT_P0HI9Q_HOST_IDX(v))\n\n/* 2 REG_P0HI10Q_TXBD_IDX\t\t\t(Offset 0x1338) */\n\n#define BIT_SHIFT_P0HI10Q_HW_IDX 16\n#define BIT_MASK_P0HI10Q_HW_IDX 0xfff\n#define BIT_P0HI10Q_HW_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_P0HI10Q_HW_IDX) << BIT_SHIFT_P0HI10Q_HW_IDX)\n#define BITS_P0HI10Q_HW_IDX                                                    \\\n\t(BIT_MASK_P0HI10Q_HW_IDX << BIT_SHIFT_P0HI10Q_HW_IDX)\n#define BIT_CLEAR_P0HI10Q_HW_IDX(x) ((x) & (~BITS_P0HI10Q_HW_IDX))\n#define BIT_GET_P0HI10Q_HW_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_P0HI10Q_HW_IDX) & BIT_MASK_P0HI10Q_HW_IDX)\n#define BIT_SET_P0HI10Q_HW_IDX(x, v)                                           \\\n\t(BIT_CLEAR_P0HI10Q_HW_IDX(x) | BIT_P0HI10Q_HW_IDX(v))\n\n#define BIT_SHIFT_P0HI10Q_HOST_IDX 0\n#define BIT_MASK_P0HI10Q_HOST_IDX 0xfff\n#define BIT_P0HI10Q_HOST_IDX(x)                                                \\\n\t(((x) & BIT_MASK_P0HI10Q_HOST_IDX) << BIT_SHIFT_P0HI10Q_HOST_IDX)\n#define BITS_P0HI10Q_HOST_IDX                                                  \\\n\t(BIT_MASK_P0HI10Q_HOST_IDX << BIT_SHIFT_P0HI10Q_HOST_IDX)\n#define BIT_CLEAR_P0HI10Q_HOST_IDX(x) ((x) & (~BITS_P0HI10Q_HOST_IDX))\n#define BIT_GET_P0HI10Q_HOST_IDX(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI10Q_HOST_IDX) & BIT_MASK_P0HI10Q_HOST_IDX)\n#define BIT_SET_P0HI10Q_HOST_IDX(x, v)                                         \\\n\t(BIT_CLEAR_P0HI10Q_HOST_IDX(x) | BIT_P0HI10Q_HOST_IDX(v))\n\n/* 2 REG_P0HI11Q_TXBD_IDX\t\t\t(Offset 0x133C) */\n\n#define BIT_SHIFT_P0HI11Q_HW_IDX 16\n#define BIT_MASK_P0HI11Q_HW_IDX 0xfff\n#define BIT_P0HI11Q_HW_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_P0HI11Q_HW_IDX) << BIT_SHIFT_P0HI11Q_HW_IDX)\n#define BITS_P0HI11Q_HW_IDX                                                    \\\n\t(BIT_MASK_P0HI11Q_HW_IDX << BIT_SHIFT_P0HI11Q_HW_IDX)\n#define BIT_CLEAR_P0HI11Q_HW_IDX(x) ((x) & (~BITS_P0HI11Q_HW_IDX))\n#define BIT_GET_P0HI11Q_HW_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_P0HI11Q_HW_IDX) & BIT_MASK_P0HI11Q_HW_IDX)\n#define BIT_SET_P0HI11Q_HW_IDX(x, v)                                           \\\n\t(BIT_CLEAR_P0HI11Q_HW_IDX(x) | BIT_P0HI11Q_HW_IDX(v))\n\n#define BIT_SHIFT_P0HI11Q_HOST_IDX 0\n#define BIT_MASK_P0HI11Q_HOST_IDX 0xfff\n#define BIT_P0HI11Q_HOST_IDX(x)                                                \\\n\t(((x) & BIT_MASK_P0HI11Q_HOST_IDX) << BIT_SHIFT_P0HI11Q_HOST_IDX)\n#define BITS_P0HI11Q_HOST_IDX                                                  \\\n\t(BIT_MASK_P0HI11Q_HOST_IDX << BIT_SHIFT_P0HI11Q_HOST_IDX)\n#define BIT_CLEAR_P0HI11Q_HOST_IDX(x) ((x) & (~BITS_P0HI11Q_HOST_IDX))\n#define BIT_GET_P0HI11Q_HOST_IDX(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI11Q_HOST_IDX) & BIT_MASK_P0HI11Q_HOST_IDX)\n#define BIT_SET_P0HI11Q_HOST_IDX(x, v)                                         \\\n\t(BIT_CLEAR_P0HI11Q_HOST_IDX(x) | BIT_P0HI11Q_HOST_IDX(v))\n\n/* 2 REG_P0HI12Q_TXBD_IDX\t\t\t(Offset 0x1340) */\n\n#define BIT_SHIFT_P0HI12Q_HW_IDX 16\n#define BIT_MASK_P0HI12Q_HW_IDX 0xfff\n#define BIT_P0HI12Q_HW_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_P0HI12Q_HW_IDX) << BIT_SHIFT_P0HI12Q_HW_IDX)\n#define BITS_P0HI12Q_HW_IDX                                                    \\\n\t(BIT_MASK_P0HI12Q_HW_IDX << BIT_SHIFT_P0HI12Q_HW_IDX)\n#define BIT_CLEAR_P0HI12Q_HW_IDX(x) ((x) & (~BITS_P0HI12Q_HW_IDX))\n#define BIT_GET_P0HI12Q_HW_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_P0HI12Q_HW_IDX) & BIT_MASK_P0HI12Q_HW_IDX)\n#define BIT_SET_P0HI12Q_HW_IDX(x, v)                                           \\\n\t(BIT_CLEAR_P0HI12Q_HW_IDX(x) | BIT_P0HI12Q_HW_IDX(v))\n\n#define BIT_SHIFT_P0HI12Q_HOST_IDX 0\n#define BIT_MASK_P0HI12Q_HOST_IDX 0xfff\n#define BIT_P0HI12Q_HOST_IDX(x)                                                \\\n\t(((x) & BIT_MASK_P0HI12Q_HOST_IDX) << BIT_SHIFT_P0HI12Q_HOST_IDX)\n#define BITS_P0HI12Q_HOST_IDX                                                  \\\n\t(BIT_MASK_P0HI12Q_HOST_IDX << BIT_SHIFT_P0HI12Q_HOST_IDX)\n#define BIT_CLEAR_P0HI12Q_HOST_IDX(x) ((x) & (~BITS_P0HI12Q_HOST_IDX))\n#define BIT_GET_P0HI12Q_HOST_IDX(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI12Q_HOST_IDX) & BIT_MASK_P0HI12Q_HOST_IDX)\n#define BIT_SET_P0HI12Q_HOST_IDX(x, v)                                         \\\n\t(BIT_CLEAR_P0HI12Q_HOST_IDX(x) | BIT_P0HI12Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_CPL_BUFFER_MONITOR\t\t\t(Offset 0x1344) */\n\n#define BIT_TXQFULL_FLAG BIT(19)\n\n#define BIT_SHIFT_RELAX_ORDERING_ATTR 17\n#define BIT_MASK_RELAX_ORDERING_ATTR 0x3\n#define BIT_RELAX_ORDERING_ATTR(x)                                             \\\n\t(((x) & BIT_MASK_RELAX_ORDERING_ATTR) << BIT_SHIFT_RELAX_ORDERING_ATTR)\n#define BITS_RELAX_ORDERING_ATTR                                               \\\n\t(BIT_MASK_RELAX_ORDERING_ATTR << BIT_SHIFT_RELAX_ORDERING_ATTR)\n#define BIT_CLEAR_RELAX_ORDERING_ATTR(x) ((x) & (~BITS_RELAX_ORDERING_ATTR))\n#define BIT_GET_RELAX_ORDERING_ATTR(x)                                         \\\n\t(((x) >> BIT_SHIFT_RELAX_ORDERING_ATTR) & BIT_MASK_RELAX_ORDERING_ATTR)\n#define BIT_SET_RELAX_ORDERING_ATTR(x, v)                                      \\\n\t(BIT_CLEAR_RELAX_ORDERING_ATTR(x) | BIT_RELAX_ORDERING_ATTR(v))\n\n#define BIT_CLR_QD_CPL_MIN_REMAIN BIT(16)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI13Q_TXBD_IDX\t\t\t(Offset 0x1344) */\n\n#define BIT_SHIFT_P0HI13Q_HW_IDX 16\n#define BIT_MASK_P0HI13Q_HW_IDX 0xfff\n#define BIT_P0HI13Q_HW_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_P0HI13Q_HW_IDX) << BIT_SHIFT_P0HI13Q_HW_IDX)\n#define BITS_P0HI13Q_HW_IDX                                                    \\\n\t(BIT_MASK_P0HI13Q_HW_IDX << BIT_SHIFT_P0HI13Q_HW_IDX)\n#define BIT_CLEAR_P0HI13Q_HW_IDX(x) ((x) & (~BITS_P0HI13Q_HW_IDX))\n#define BIT_GET_P0HI13Q_HW_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_P0HI13Q_HW_IDX) & BIT_MASK_P0HI13Q_HW_IDX)\n#define BIT_SET_P0HI13Q_HW_IDX(x, v)                                           \\\n\t(BIT_CLEAR_P0HI13Q_HW_IDX(x) | BIT_P0HI13Q_HW_IDX(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_CPL_BUFFER_MONITOR\t\t\t(Offset 0x1344) */\n\n#define BIT_SHIFT_QD_CPL_MIN_REMAIN_ADDR 8\n#define BIT_MASK_QD_CPL_MIN_REMAIN_ADDR 0xff\n#define BIT_QD_CPL_MIN_REMAIN_ADDR(x)                                          \\\n\t(((x) & BIT_MASK_QD_CPL_MIN_REMAIN_ADDR)                               \\\n\t << BIT_SHIFT_QD_CPL_MIN_REMAIN_ADDR)\n#define BITS_QD_CPL_MIN_REMAIN_ADDR                                            \\\n\t(BIT_MASK_QD_CPL_MIN_REMAIN_ADDR << BIT_SHIFT_QD_CPL_MIN_REMAIN_ADDR)\n#define BIT_CLEAR_QD_CPL_MIN_REMAIN_ADDR(x)                                    \\\n\t((x) & (~BITS_QD_CPL_MIN_REMAIN_ADDR))\n#define BIT_GET_QD_CPL_MIN_REMAIN_ADDR(x)                                      \\\n\t(((x) >> BIT_SHIFT_QD_CPL_MIN_REMAIN_ADDR) &                           \\\n\t BIT_MASK_QD_CPL_MIN_REMAIN_ADDR)\n#define BIT_SET_QD_CPL_MIN_REMAIN_ADDR(x, v)                                   \\\n\t(BIT_CLEAR_QD_CPL_MIN_REMAIN_ADDR(x) | BIT_QD_CPL_MIN_REMAIN_ADDR(v))\n\n#define BIT_SHIFT_QD_CPL_CUR_REMAIN_ADDR 0\n#define BIT_MASK_QD_CPL_CUR_REMAIN_ADDR 0xff\n#define BIT_QD_CPL_CUR_REMAIN_ADDR(x)                                          \\\n\t(((x) & BIT_MASK_QD_CPL_CUR_REMAIN_ADDR)                               \\\n\t << BIT_SHIFT_QD_CPL_CUR_REMAIN_ADDR)\n#define BITS_QD_CPL_CUR_REMAIN_ADDR                                            \\\n\t(BIT_MASK_QD_CPL_CUR_REMAIN_ADDR << BIT_SHIFT_QD_CPL_CUR_REMAIN_ADDR)\n#define BIT_CLEAR_QD_CPL_CUR_REMAIN_ADDR(x)                                    \\\n\t((x) & (~BITS_QD_CPL_CUR_REMAIN_ADDR))\n#define BIT_GET_QD_CPL_CUR_REMAIN_ADDR(x)                                      \\\n\t(((x) >> BIT_SHIFT_QD_CPL_CUR_REMAIN_ADDR) &                           \\\n\t BIT_MASK_QD_CPL_CUR_REMAIN_ADDR)\n#define BIT_SET_QD_CPL_CUR_REMAIN_ADDR(x, v)                                   \\\n\t(BIT_CLEAR_QD_CPL_CUR_REMAIN_ADDR(x) | BIT_QD_CPL_CUR_REMAIN_ADDR(v))\n\n#define BIT_SHIFT_PTM_LOCAL_CLOCK 0\n#define BIT_MASK_PTM_LOCAL_CLOCK 0xffffffffL\n#define BIT_PTM_LOCAL_CLOCK(x)                                                 \\\n\t(((x) & BIT_MASK_PTM_LOCAL_CLOCK) << BIT_SHIFT_PTM_LOCAL_CLOCK)\n#define BITS_PTM_LOCAL_CLOCK                                                   \\\n\t(BIT_MASK_PTM_LOCAL_CLOCK << BIT_SHIFT_PTM_LOCAL_CLOCK)\n#define BIT_CLEAR_PTM_LOCAL_CLOCK(x) ((x) & (~BITS_PTM_LOCAL_CLOCK))\n#define BIT_GET_PTM_LOCAL_CLOCK(x)                                             \\\n\t(((x) >> BIT_SHIFT_PTM_LOCAL_CLOCK) & BIT_MASK_PTM_LOCAL_CLOCK)\n#define BIT_SET_PTM_LOCAL_CLOCK(x, v)                                          \\\n\t(BIT_CLEAR_PTM_LOCAL_CLOCK(x) | BIT_PTM_LOCAL_CLOCK(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI13Q_TXBD_IDX\t\t\t(Offset 0x1344) */\n\n#define BIT_SHIFT_P0HI13Q_HOST_IDX 0\n#define BIT_MASK_P0HI13Q_HOST_IDX 0xfff\n#define BIT_P0HI13Q_HOST_IDX(x)                                                \\\n\t(((x) & BIT_MASK_P0HI13Q_HOST_IDX) << BIT_SHIFT_P0HI13Q_HOST_IDX)\n#define BITS_P0HI13Q_HOST_IDX                                                  \\\n\t(BIT_MASK_P0HI13Q_HOST_IDX << BIT_SHIFT_P0HI13Q_HOST_IDX)\n#define BIT_CLEAR_P0HI13Q_HOST_IDX(x) ((x) & (~BITS_P0HI13Q_HOST_IDX))\n#define BIT_GET_P0HI13Q_HOST_IDX(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI13Q_HOST_IDX) & BIT_MASK_P0HI13Q_HOST_IDX)\n#define BIT_SET_P0HI13Q_HOST_IDX(x, v)                                         \\\n\t(BIT_CLEAR_P0HI13Q_HOST_IDX(x) | BIT_P0HI13Q_HOST_IDX(v))\n\n/* 2 REG_P0HI14Q_TXBD_IDX\t\t\t(Offset 0x1348) */\n\n#define BIT_SHIFT_P0HI14Q_HW_IDX 16\n#define BIT_MASK_P0HI14Q_HW_IDX 0xfff\n#define BIT_P0HI14Q_HW_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_P0HI14Q_HW_IDX) << BIT_SHIFT_P0HI14Q_HW_IDX)\n#define BITS_P0HI14Q_HW_IDX                                                    \\\n\t(BIT_MASK_P0HI14Q_HW_IDX << BIT_SHIFT_P0HI14Q_HW_IDX)\n#define BIT_CLEAR_P0HI14Q_HW_IDX(x) ((x) & (~BITS_P0HI14Q_HW_IDX))\n#define BIT_GET_P0HI14Q_HW_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_P0HI14Q_HW_IDX) & BIT_MASK_P0HI14Q_HW_IDX)\n#define BIT_SET_P0HI14Q_HW_IDX(x, v)                                           \\\n\t(BIT_CLEAR_P0HI14Q_HW_IDX(x) | BIT_P0HI14Q_HW_IDX(v))\n\n#define BIT_SHIFT_P0HI14Q_HOST_IDX 0\n#define BIT_MASK_P0HI14Q_HOST_IDX 0xfff\n#define BIT_P0HI14Q_HOST_IDX(x)                                                \\\n\t(((x) & BIT_MASK_P0HI14Q_HOST_IDX) << BIT_SHIFT_P0HI14Q_HOST_IDX)\n#define BITS_P0HI14Q_HOST_IDX                                                  \\\n\t(BIT_MASK_P0HI14Q_HOST_IDX << BIT_SHIFT_P0HI14Q_HOST_IDX)\n#define BIT_CLEAR_P0HI14Q_HOST_IDX(x) ((x) & (~BITS_P0HI14Q_HOST_IDX))\n#define BIT_GET_P0HI14Q_HOST_IDX(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI14Q_HOST_IDX) & BIT_MASK_P0HI14Q_HOST_IDX)\n#define BIT_SET_P0HI14Q_HOST_IDX(x, v)                                         \\\n\t(BIT_CLEAR_P0HI14Q_HOST_IDX(x) | BIT_P0HI14Q_HOST_IDX(v))\n\n/* 2 REG_P0HI15Q_TXBD_IDX\t\t\t(Offset 0x134C) */\n\n#define BIT_SHIFT_P0HI15Q_HW_IDX 16\n#define BIT_MASK_P0HI15Q_HW_IDX 0xfff\n#define BIT_P0HI15Q_HW_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_P0HI15Q_HW_IDX) << BIT_SHIFT_P0HI15Q_HW_IDX)\n#define BITS_P0HI15Q_HW_IDX                                                    \\\n\t(BIT_MASK_P0HI15Q_HW_IDX << BIT_SHIFT_P0HI15Q_HW_IDX)\n#define BIT_CLEAR_P0HI15Q_HW_IDX(x) ((x) & (~BITS_P0HI15Q_HW_IDX))\n#define BIT_GET_P0HI15Q_HW_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_P0HI15Q_HW_IDX) & BIT_MASK_P0HI15Q_HW_IDX)\n#define BIT_SET_P0HI15Q_HW_IDX(x, v)                                           \\\n\t(BIT_CLEAR_P0HI15Q_HW_IDX(x) | BIT_P0HI15Q_HW_IDX(v))\n\n#define BIT_SHIFT_P0HI15Q_HOST_IDX 0\n#define BIT_MASK_P0HI15Q_HOST_IDX 0xfff\n#define BIT_P0HI15Q_HOST_IDX(x)                                                \\\n\t(((x) & BIT_MASK_P0HI15Q_HOST_IDX) << BIT_SHIFT_P0HI15Q_HOST_IDX)\n#define BITS_P0HI15Q_HOST_IDX                                                  \\\n\t(BIT_MASK_P0HI15Q_HOST_IDX << BIT_SHIFT_P0HI15Q_HOST_IDX)\n#define BIT_CLEAR_P0HI15Q_HOST_IDX(x) ((x) & (~BITS_P0HI15Q_HOST_IDX))\n#define BIT_GET_P0HI15Q_HOST_IDX(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI15Q_HOST_IDX) & BIT_MASK_P0HI15Q_HOST_IDX)\n#define BIT_SET_P0HI15Q_HOST_IDX(x, v)                                         \\\n\t(BIT_CLEAR_P0HI15Q_HOST_IDX(x) | BIT_P0HI15Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AXI_EXCEPT_CS\t\t\t(Offset 0x1350) */\n\n#define BIT_AXI_RXDMA_TIMEOUT_RE BIT(21)\n#define BIT_AXI_TXDMA_TIMEOUT_RE BIT(20)\n#define BIT_AXI_DECERR_W_RE BIT(19)\n#define BIT_AXI_DECERR_R_RE BIT(18)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_CHANGE_PCIE_SPEED\t\t\t(Offset 0x1350) */\n\n#define BIT_CHANGE_PCIE_SPEED BIT(18)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AXI_EXCEPT_CS\t\t\t(Offset 0x1350) */\n\n#define BIT_AXI_SLVERR_W_RE BIT(17)\n#define BIT_AXI_SLVERR_R_RE BIT(16)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_CHANGE_PCIE_SPEED\t\t\t(Offset 0x1350) */\n\n#define BIT_SHIFT_GEN1_GEN2 16\n#define BIT_MASK_GEN1_GEN2 0x3\n#define BIT_GEN1_GEN2(x) (((x) & BIT_MASK_GEN1_GEN2) << BIT_SHIFT_GEN1_GEN2)\n#define BITS_GEN1_GEN2 (BIT_MASK_GEN1_GEN2 << BIT_SHIFT_GEN1_GEN2)\n#define BIT_CLEAR_GEN1_GEN2(x) ((x) & (~BITS_GEN1_GEN2))\n#define BIT_GET_GEN1_GEN2(x) (((x) >> BIT_SHIFT_GEN1_GEN2) & BIT_MASK_GEN1_GEN2)\n#define BIT_SET_GEN1_GEN2(x, v) (BIT_CLEAR_GEN1_GEN2(x) | BIT_GEN1_GEN2(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AXI_EXCEPT_CS\t\t\t(Offset 0x1350) */\n\n#define BIT_AXI_RXDMA_TIMEOUT_IE BIT(13)\n#define BIT_AXI_TXDMA_TIMEOUT_IE BIT(12)\n#define BIT_AXI_DECERR_W_IE BIT(11)\n#define BIT_AXI_DECERR_R_IE BIT(10)\n#define BIT_AXI_SLVERR_W_IE BIT(9)\n#define BIT_AXI_SLVERR_R_IE BIT(8)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_CHANGE_PCIE_SPEED\t\t\t(Offset 0x1350) */\n\n#define BIT_SHIFT_RXDMA_ERROR_COUNTER 8\n#define BIT_MASK_RXDMA_ERROR_COUNTER 0xff\n#define BIT_RXDMA_ERROR_COUNTER(x)                                             \\\n\t(((x) & BIT_MASK_RXDMA_ERROR_COUNTER) << BIT_SHIFT_RXDMA_ERROR_COUNTER)\n#define BITS_RXDMA_ERROR_COUNTER                                               \\\n\t(BIT_MASK_RXDMA_ERROR_COUNTER << BIT_SHIFT_RXDMA_ERROR_COUNTER)\n#define BIT_CLEAR_RXDMA_ERROR_COUNTER(x) ((x) & (~BITS_RXDMA_ERROR_COUNTER))\n#define BIT_GET_RXDMA_ERROR_COUNTER(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXDMA_ERROR_COUNTER) & BIT_MASK_RXDMA_ERROR_COUNTER)\n#define BIT_SET_RXDMA_ERROR_COUNTER(x, v)                                      \\\n\t(BIT_CLEAR_RXDMA_ERROR_COUNTER(x) | BIT_RXDMA_ERROR_COUNTER(v))\n\n#define BIT_TXDMA_ERROR_HANDLE_STATUS BIT(7)\n#define BIT_TXDMA_ERROR_PULSE BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AXI_EXCEPT_CS\t\t\t(Offset 0x1350) */\n\n#define BIT_AXI_RXDMA_TIMEOUT_FLAG BIT(5)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_CHANGE_PCIE_SPEED\t\t\t(Offset 0x1350) */\n\n#define BIT_TXDMA_STUCK_ERROR_HANDLE_ENABLE BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AXI_EXCEPT_CS\t\t\t(Offset 0x1350) */\n\n#define BIT_AXI_TXDMA_TIMEOUT_FLAG BIT(4)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_CHANGE_PCIE_SPEED\t\t\t(Offset 0x1350) */\n\n#define BIT_TXDMA_RETURN_ERROR_ENABLE BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AXI_EXCEPT_CS\t\t\t(Offset 0x1350) */\n\n#define BIT_AXI_DECERR_W_FLAG BIT(3)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_CHANGE_PCIE_SPEED\t\t\t(Offset 0x1350) */\n\n#define BIT_RXDMA_ERROR_HANDLE_STATUS BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AXI_EXCEPT_CS\t\t\t(Offset 0x1350) */\n\n#define BIT_AXI_DECERR_R_FLAG BIT(2)\n#define BIT_AXI_SLVERR_W_FLAG BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_TSFT_PTM_DIFF\t\t\t(Offset 0x1350) */\n\n#define BIT_SHIFT_TSFT_PTM_DIFF 0\n#define BIT_MASK_TSFT_PTM_DIFF 0xffffffffL\n#define BIT_TSFT_PTM_DIFF(x)                                                   \\\n\t(((x) & BIT_MASK_TSFT_PTM_DIFF) << BIT_SHIFT_TSFT_PTM_DIFF)\n#define BITS_TSFT_PTM_DIFF (BIT_MASK_TSFT_PTM_DIFF << BIT_SHIFT_TSFT_PTM_DIFF)\n#define BIT_CLEAR_TSFT_PTM_DIFF(x) ((x) & (~BITS_TSFT_PTM_DIFF))\n#define BIT_GET_TSFT_PTM_DIFF(x)                                               \\\n\t(((x) >> BIT_SHIFT_TSFT_PTM_DIFF) & BIT_MASK_TSFT_PTM_DIFF)\n#define BIT_SET_TSFT_PTM_DIFF(x, v)                                            \\\n\t(BIT_CLEAR_TSFT_PTM_DIFF(x) | BIT_TSFT_PTM_DIFF(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AXI_EXCEPT_CS\t\t\t(Offset 0x1350) */\n\n#define BIT_AXI_SLVERR_R_FLAG BIT(0)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_CHANGE_PCIE_SPEED\t\t\t(Offset 0x1350) */\n\n#define BIT_SHIFT_AUTO_HANG_RELEASE 0\n#define BIT_MASK_AUTO_HANG_RELEASE 0x7\n#define BIT_AUTO_HANG_RELEASE(x)                                               \\\n\t(((x) & BIT_MASK_AUTO_HANG_RELEASE) << BIT_SHIFT_AUTO_HANG_RELEASE)\n#define BITS_AUTO_HANG_RELEASE                                                 \\\n\t(BIT_MASK_AUTO_HANG_RELEASE << BIT_SHIFT_AUTO_HANG_RELEASE)\n#define BIT_CLEAR_AUTO_HANG_RELEASE(x) ((x) & (~BITS_AUTO_HANG_RELEASE))\n#define BIT_GET_AUTO_HANG_RELEASE(x)                                           \\\n\t(((x) >> BIT_SHIFT_AUTO_HANG_RELEASE) & BIT_MASK_AUTO_HANG_RELEASE)\n#define BIT_SET_AUTO_HANG_RELEASE(x, v)                                        \\\n\t(BIT_CLEAR_AUTO_HANG_RELEASE(x) | BIT_AUTO_HANG_RELEASE(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AXI_EXCEPT_TIME\t\t\t(Offset 0x1354) */\n\n#define BIT_SHIFT_AXI_RECOVERY_TIME 24\n#define BIT_MASK_AXI_RECOVERY_TIME 0xff\n#define BIT_AXI_RECOVERY_TIME(x)                                               \\\n\t(((x) & BIT_MASK_AXI_RECOVERY_TIME) << BIT_SHIFT_AXI_RECOVERY_TIME)\n#define BITS_AXI_RECOVERY_TIME                                                 \\\n\t(BIT_MASK_AXI_RECOVERY_TIME << BIT_SHIFT_AXI_RECOVERY_TIME)\n#define BIT_CLEAR_AXI_RECOVERY_TIME(x) ((x) & (~BITS_AXI_RECOVERY_TIME))\n#define BIT_GET_AXI_RECOVERY_TIME(x)                                           \\\n\t(((x) >> BIT_SHIFT_AXI_RECOVERY_TIME) & BIT_MASK_AXI_RECOVERY_TIME)\n#define BIT_SET_AXI_RECOVERY_TIME(x, v)                                        \\\n\t(BIT_CLEAR_AXI_RECOVERY_TIME(x) | BIT_AXI_RECOVERY_TIME(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_PTM_CTRL_STATUS\t\t\t(Offset 0x1354) */\n\n#define BIT_BCNQ2_EMPTY BIT(23)\n#define BIT_BCNQ1_EMPTY BIT(22)\n#define BIT_BCNQ0_EMPTY BIT(21)\n#define BIT_EVTQ_EMPTY BIT(20)\n#define BIT_MGQ_CPU_EMPTY_V2 BIT(19)\n#define BIT_BCNQ_EMPTY_V2 BIT(18)\n#define BIT_HQQ_EMPTY_V2 BIT(17)\n\n#define BIT_SHIFT_TAIL_PKT_V1 16\n#define BIT_MASK_TAIL_PKT_V1 0xff\n#define BIT_TAIL_PKT_V1(x)                                                     \\\n\t(((x) & BIT_MASK_TAIL_PKT_V1) << BIT_SHIFT_TAIL_PKT_V1)\n#define BITS_TAIL_PKT_V1 (BIT_MASK_TAIL_PKT_V1 << BIT_SHIFT_TAIL_PKT_V1)\n#define BIT_CLEAR_TAIL_PKT_V1(x) ((x) & (~BITS_TAIL_PKT_V1))\n#define BIT_GET_TAIL_PKT_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_V1) & BIT_MASK_TAIL_PKT_V1)\n#define BIT_SET_TAIL_PKT_V1(x, v)                                              \\\n\t(BIT_CLEAR_TAIL_PKT_V1(x) | BIT_TAIL_PKT_V1(v))\n\n#define BIT_MQQ_EMPTY_V3 BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AXI_EXCEPT_TIME\t\t\t(Offset 0x1354) */\n\n#define BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL 12\n#define BIT_MASK_AXI_RXDMA_TIMEOUT_VAL 0xfff\n#define BIT_AXI_RXDMA_TIMEOUT_VAL(x)                                           \\\n\t(((x) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL)                                \\\n\t << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL)\n#define BITS_AXI_RXDMA_TIMEOUT_VAL                                             \\\n\t(BIT_MASK_AXI_RXDMA_TIMEOUT_VAL << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL)\n#define BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL(x) ((x) & (~BITS_AXI_RXDMA_TIMEOUT_VAL))\n#define BIT_GET_AXI_RXDMA_TIMEOUT_VAL(x)                                       \\\n\t(((x) >> BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL) &                            \\\n\t BIT_MASK_AXI_RXDMA_TIMEOUT_VAL)\n#define BIT_SET_AXI_RXDMA_TIMEOUT_VAL(x, v)                                    \\\n\t(BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL(x) | BIT_AXI_RXDMA_TIMEOUT_VAL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_PTM_CTRL_STATUS\t\t\t(Offset 0x1354) */\n\n#define BIT_SHIFT_PKT_NUM_V1 8\n#define BIT_MASK_PKT_NUM_V1 0xff\n#define BIT_PKT_NUM_V1(x) (((x) & BIT_MASK_PKT_NUM_V1) << BIT_SHIFT_PKT_NUM_V1)\n#define BITS_PKT_NUM_V1 (BIT_MASK_PKT_NUM_V1 << BIT_SHIFT_PKT_NUM_V1)\n#define BIT_CLEAR_PKT_NUM_V1(x) ((x) & (~BITS_PKT_NUM_V1))\n#define BIT_GET_PKT_NUM_V1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_V1) & BIT_MASK_PKT_NUM_V1)\n#define BIT_SET_PKT_NUM_V1(x, v) (BIT_CLEAR_PKT_NUM_V1(x) | BIT_PKT_NUM_V1(v))\n\n#define BIT_SHIFT_QUEUEAC_V1 8\n#define BIT_MASK_QUEUEAC_V1 0x3\n#define BIT_QUEUEAC_V1(x) (((x) & BIT_MASK_QUEUEAC_V1) << BIT_SHIFT_QUEUEAC_V1)\n#define BITS_QUEUEAC_V1 (BIT_MASK_QUEUEAC_V1 << BIT_SHIFT_QUEUEAC_V1)\n#define BIT_CLEAR_QUEUEAC_V1(x) ((x) & (~BITS_QUEUEAC_V1))\n#define BIT_GET_QUEUEAC_V1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_V1) & BIT_MASK_QUEUEAC_V1)\n#define BIT_SET_QUEUEAC_V1(x, v) (BIT_CLEAR_QUEUEAC_V1(x) | BIT_QUEUEAC_V1(v))\n\n#define BIT_SHIFT_ACQ_STOP 5\n#define BIT_MASK_ACQ_STOP 0xffff\n#define BIT_ACQ_STOP(x) (((x) & BIT_MASK_ACQ_STOP) << BIT_SHIFT_ACQ_STOP)\n#define BITS_ACQ_STOP (BIT_MASK_ACQ_STOP << BIT_SHIFT_ACQ_STOP)\n#define BIT_CLEAR_ACQ_STOP(x) ((x) & (~BITS_ACQ_STOP))\n#define BIT_GET_ACQ_STOP(x) (((x) >> BIT_SHIFT_ACQ_STOP) & BIT_MASK_ACQ_STOP)\n#define BIT_SET_ACQ_STOP(x, v) (BIT_CLEAR_ACQ_STOP(x) | BIT_ACQ_STOP(v))\n\n#define BIT_SHIFT_TSFT_PORT_SEL 3\n#define BIT_MASK_TSFT_PORT_SEL 0x3\n#define BIT_TSFT_PORT_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_TSFT_PORT_SEL) << BIT_SHIFT_TSFT_PORT_SEL)\n#define BITS_TSFT_PORT_SEL (BIT_MASK_TSFT_PORT_SEL << BIT_SHIFT_TSFT_PORT_SEL)\n#define BIT_CLEAR_TSFT_PORT_SEL(x) ((x) & (~BITS_TSFT_PORT_SEL))\n#define BIT_GET_TSFT_PORT_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_TSFT_PORT_SEL) & BIT_MASK_TSFT_PORT_SEL)\n#define BIT_SET_TSFT_PORT_SEL(x, v)                                            \\\n\t(BIT_CLEAR_TSFT_PORT_SEL(x) | BIT_TSFT_PORT_SEL(v))\n\n#define BIT_PTM_CONTEXT_VALID BIT(2)\n#define BIT_PTM_MANUL_UPDATE BIT(1)\n#define BIT_PTM_AUTO_UPDATE BIT(0)\n\n#define BIT_SHIFT_HEAD_PKT_V1 0\n#define BIT_MASK_HEAD_PKT_V1 0xff\n#define BIT_HEAD_PKT_V1(x)                                                     \\\n\t(((x) & BIT_MASK_HEAD_PKT_V1) << BIT_SHIFT_HEAD_PKT_V1)\n#define BITS_HEAD_PKT_V1 (BIT_MASK_HEAD_PKT_V1 << BIT_SHIFT_HEAD_PKT_V1)\n#define BIT_CLEAR_HEAD_PKT_V1(x) ((x) & (~BITS_HEAD_PKT_V1))\n#define BIT_GET_HEAD_PKT_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_V1) & BIT_MASK_HEAD_PKT_V1)\n#define BIT_SET_HEAD_PKT_V1(x, v)                                              \\\n\t(BIT_CLEAR_HEAD_PKT_V1(x) | BIT_HEAD_PKT_V1(v))\n\n#define BIT_SHIFT_QUEUEMACID_V1 0\n#define BIT_MASK_QUEUEMACID_V1 0x7f\n#define BIT_QUEUEMACID_V1(x)                                                   \\\n\t(((x) & BIT_MASK_QUEUEMACID_V1) << BIT_SHIFT_QUEUEMACID_V1)\n#define BITS_QUEUEMACID_V1 (BIT_MASK_QUEUEMACID_V1 << BIT_SHIFT_QUEUEMACID_V1)\n#define BIT_CLEAR_QUEUEMACID_V1(x) ((x) & (~BITS_QUEUEMACID_V1))\n#define BIT_GET_QUEUEMACID_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_V1) & BIT_MASK_QUEUEMACID_V1)\n#define BIT_SET_QUEUEMACID_V1(x, v)                                            \\\n\t(BIT_CLEAR_QUEUEMACID_V1(x) | BIT_QUEUEMACID_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_AXI_EXCEPT_TIME\t\t\t(Offset 0x1354) */\n\n#define BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL 0\n#define BIT_MASK_AXI_TXDMA_TIMEOUT_VAL 0xfff\n#define BIT_AXI_TXDMA_TIMEOUT_VAL(x)                                           \\\n\t(((x) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL)                                \\\n\t << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL)\n#define BITS_AXI_TXDMA_TIMEOUT_VAL                                             \\\n\t(BIT_MASK_AXI_TXDMA_TIMEOUT_VAL << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL)\n#define BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL(x) ((x) & (~BITS_AXI_TXDMA_TIMEOUT_VAL))\n#define BIT_GET_AXI_TXDMA_TIMEOUT_VAL(x)                                       \\\n\t(((x) >> BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL) &                            \\\n\t BIT_MASK_AXI_TXDMA_TIMEOUT_VAL)\n#define BIT_SET_AXI_TXDMA_TIMEOUT_VAL(x, v)                                    \\\n\t(BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL(x) | BIT_AXI_TXDMA_TIMEOUT_VAL(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DEBUG_STATE1\t\t\t(Offset 0x1354) */\n\n#define BIT_SHIFT_DEBUG_STATE1 0\n#define BIT_MASK_DEBUG_STATE1 0xffffffffL\n#define BIT_DEBUG_STATE1(x)                                                    \\\n\t(((x) & BIT_MASK_DEBUG_STATE1) << BIT_SHIFT_DEBUG_STATE1)\n#define BITS_DEBUG_STATE1 (BIT_MASK_DEBUG_STATE1 << BIT_SHIFT_DEBUG_STATE1)\n#define BIT_CLEAR_DEBUG_STATE1(x) ((x) & (~BITS_DEBUG_STATE1))\n#define BIT_GET_DEBUG_STATE1(x)                                                \\\n\t(((x) >> BIT_SHIFT_DEBUG_STATE1) & BIT_MASK_DEBUG_STATE1)\n#define BIT_SET_DEBUG_STATE1(x, v)                                             \\\n\t(BIT_CLEAR_DEBUG_STATE1(x) | BIT_DEBUG_STATE1(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI8Q_TXBD_IDX\t\t\t(Offset 0x1358) */\n\n#define BIT_SHIFT_HI8Q_HW_IDX 16\n#define BIT_MASK_HI8Q_HW_IDX 0xfff\n#define BIT_HI8Q_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_HI8Q_HW_IDX) << BIT_SHIFT_HI8Q_HW_IDX)\n#define BITS_HI8Q_HW_IDX (BIT_MASK_HI8Q_HW_IDX << BIT_SHIFT_HI8Q_HW_IDX)\n#define BIT_CLEAR_HI8Q_HW_IDX(x) ((x) & (~BITS_HI8Q_HW_IDX))\n#define BIT_GET_HI8Q_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HI8Q_HW_IDX) & BIT_MASK_HI8Q_HW_IDX)\n#define BIT_SET_HI8Q_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_HI8Q_HW_IDX(x) | BIT_HI8Q_HW_IDX(v))\n\n#define BIT_SHIFT_HI8Q_HOST_IDX 0\n#define BIT_MASK_HI8Q_HOST_IDX 0xfff\n#define BIT_HI8Q_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_HI8Q_HOST_IDX) << BIT_SHIFT_HI8Q_HOST_IDX)\n#define BITS_HI8Q_HOST_IDX (BIT_MASK_HI8Q_HOST_IDX << BIT_SHIFT_HI8Q_HOST_IDX)\n#define BIT_CLEAR_HI8Q_HOST_IDX(x) ((x) & (~BITS_HI8Q_HOST_IDX))\n#define BIT_GET_HI8Q_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI8Q_HOST_IDX) & BIT_MASK_HI8Q_HOST_IDX)\n#define BIT_SET_HI8Q_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_HI8Q_HOST_IDX(x) | BIT_HI8Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DEBUG_STATE2\t\t\t(Offset 0x1358) */\n\n#define BIT_SHIFT_DEBUG_STATE2 0\n#define BIT_MASK_DEBUG_STATE2 0xffffffffL\n#define BIT_DEBUG_STATE2(x)                                                    \\\n\t(((x) & BIT_MASK_DEBUG_STATE2) << BIT_SHIFT_DEBUG_STATE2)\n#define BITS_DEBUG_STATE2 (BIT_MASK_DEBUG_STATE2 << BIT_SHIFT_DEBUG_STATE2)\n#define BIT_CLEAR_DEBUG_STATE2(x) ((x) & (~BITS_DEBUG_STATE2))\n#define BIT_GET_DEBUG_STATE2(x)                                                \\\n\t(((x) >> BIT_SHIFT_DEBUG_STATE2) & BIT_MASK_DEBUG_STATE2)\n#define BIT_SET_DEBUG_STATE2(x, v)                                             \\\n\t(BIT_CLEAR_DEBUG_STATE2(x) | BIT_DEBUG_STATE2(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI9Q_TXBD_IDX\t\t\t(Offset 0x135C) */\n\n#define BIT_SHIFT_HI9Q_HW_IDX 16\n#define BIT_MASK_HI9Q_HW_IDX 0xfff\n#define BIT_HI9Q_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_HI9Q_HW_IDX) << BIT_SHIFT_HI9Q_HW_IDX)\n#define BITS_HI9Q_HW_IDX (BIT_MASK_HI9Q_HW_IDX << BIT_SHIFT_HI9Q_HW_IDX)\n#define BIT_CLEAR_HI9Q_HW_IDX(x) ((x) & (~BITS_HI9Q_HW_IDX))\n#define BIT_GET_HI9Q_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HI9Q_HW_IDX) & BIT_MASK_HI9Q_HW_IDX)\n#define BIT_SET_HI9Q_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_HI9Q_HW_IDX(x) | BIT_HI9Q_HW_IDX(v))\n\n#define BIT_SHIFT_HI9Q_HOST_IDX 0\n#define BIT_MASK_HI9Q_HOST_IDX 0xfff\n#define BIT_HI9Q_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_HI9Q_HOST_IDX) << BIT_SHIFT_HI9Q_HOST_IDX)\n#define BITS_HI9Q_HOST_IDX (BIT_MASK_HI9Q_HOST_IDX << BIT_SHIFT_HI9Q_HOST_IDX)\n#define BIT_CLEAR_HI9Q_HOST_IDX(x) ((x) & (~BITS_HI9Q_HOST_IDX))\n#define BIT_GET_HI9Q_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI9Q_HOST_IDX) & BIT_MASK_HI9Q_HOST_IDX)\n#define BIT_SET_HI9Q_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_HI9Q_HOST_IDX(x) | BIT_HI9Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_DEBUG_STATE3\t\t\t(Offset 0x135C) */\n\n#define BIT_SHIFT_DEBUG_STATE3 0\n#define BIT_MASK_DEBUG_STATE3 0xffffffffL\n#define BIT_DEBUG_STATE3(x)                                                    \\\n\t(((x) & BIT_MASK_DEBUG_STATE3) << BIT_SHIFT_DEBUG_STATE3)\n#define BITS_DEBUG_STATE3 (BIT_MASK_DEBUG_STATE3 << BIT_SHIFT_DEBUG_STATE3)\n#define BIT_CLEAR_DEBUG_STATE3(x) ((x) & (~BITS_DEBUG_STATE3))\n#define BIT_GET_DEBUG_STATE3(x)                                                \\\n\t(((x) >> BIT_SHIFT_DEBUG_STATE3) & BIT_MASK_DEBUG_STATE3)\n#define BIT_SET_DEBUG_STATE3(x, v)                                             \\\n\t(BIT_CLEAR_DEBUG_STATE3(x) | BIT_DEBUG_STATE3(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI10Q_TXBD_IDX\t\t\t(Offset 0x1360) */\n\n#define BIT_SHIFT_HI10Q_HW_IDX 16\n#define BIT_MASK_HI10Q_HW_IDX 0xfff\n#define BIT_HI10Q_HW_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_HI10Q_HW_IDX) << BIT_SHIFT_HI10Q_HW_IDX)\n#define BITS_HI10Q_HW_IDX (BIT_MASK_HI10Q_HW_IDX << BIT_SHIFT_HI10Q_HW_IDX)\n#define BIT_CLEAR_HI10Q_HW_IDX(x) ((x) & (~BITS_HI10Q_HW_IDX))\n#define BIT_GET_HI10Q_HW_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_HI10Q_HW_IDX) & BIT_MASK_HI10Q_HW_IDX)\n#define BIT_SET_HI10Q_HW_IDX(x, v)                                             \\\n\t(BIT_CLEAR_HI10Q_HW_IDX(x) | BIT_HI10Q_HW_IDX(v))\n\n#define BIT_SHIFT_HI10Q_HOST_IDX 0\n#define BIT_MASK_HI10Q_HOST_IDX 0xfff\n#define BIT_HI10Q_HOST_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_HI10Q_HOST_IDX) << BIT_SHIFT_HI10Q_HOST_IDX)\n#define BITS_HI10Q_HOST_IDX                                                    \\\n\t(BIT_MASK_HI10Q_HOST_IDX << BIT_SHIFT_HI10Q_HOST_IDX)\n#define BIT_CLEAR_HI10Q_HOST_IDX(x) ((x) & (~BITS_HI10Q_HOST_IDX))\n#define BIT_GET_HI10Q_HOST_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI10Q_HOST_IDX) & BIT_MASK_HI10Q_HOST_IDX)\n#define BIT_SET_HI10Q_HOST_IDX(x, v)                                           \\\n\t(BIT_CLEAR_HI10Q_HOST_IDX(x) | BIT_HI10Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH5_TXBD_DESA_L\t\t\t(Offset 0x1360) */\n\n#define BIT_SHIFT_ACH5_TXBD_DESA_L 0\n#define BIT_MASK_ACH5_TXBD_DESA_L 0xffffffffL\n#define BIT_ACH5_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_ACH5_TXBD_DESA_L) << BIT_SHIFT_ACH5_TXBD_DESA_L)\n#define BITS_ACH5_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_ACH5_TXBD_DESA_L << BIT_SHIFT_ACH5_TXBD_DESA_L)\n#define BIT_CLEAR_ACH5_TXBD_DESA_L(x) ((x) & (~BITS_ACH5_TXBD_DESA_L))\n#define BIT_GET_ACH5_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH5_TXBD_DESA_L) & BIT_MASK_ACH5_TXBD_DESA_L)\n#define BIT_SET_ACH5_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_ACH5_TXBD_DESA_L(x) | BIT_ACH5_TXBD_DESA_L(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI11Q_TXBD_IDX\t\t\t(Offset 0x1364) */\n\n#define BIT_SHIFT_HI11Q_HW_IDX 16\n#define BIT_MASK_HI11Q_HW_IDX 0xfff\n#define BIT_HI11Q_HW_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_HI11Q_HW_IDX) << BIT_SHIFT_HI11Q_HW_IDX)\n#define BITS_HI11Q_HW_IDX (BIT_MASK_HI11Q_HW_IDX << BIT_SHIFT_HI11Q_HW_IDX)\n#define BIT_CLEAR_HI11Q_HW_IDX(x) ((x) & (~BITS_HI11Q_HW_IDX))\n#define BIT_GET_HI11Q_HW_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_HI11Q_HW_IDX) & BIT_MASK_HI11Q_HW_IDX)\n#define BIT_SET_HI11Q_HW_IDX(x, v)                                             \\\n\t(BIT_CLEAR_HI11Q_HW_IDX(x) | BIT_HI11Q_HW_IDX(v))\n\n#define BIT_SHIFT_HI11Q_HOST_IDX 0\n#define BIT_MASK_HI11Q_HOST_IDX 0xfff\n#define BIT_HI11Q_HOST_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_HI11Q_HOST_IDX) << BIT_SHIFT_HI11Q_HOST_IDX)\n#define BITS_HI11Q_HOST_IDX                                                    \\\n\t(BIT_MASK_HI11Q_HOST_IDX << BIT_SHIFT_HI11Q_HOST_IDX)\n#define BIT_CLEAR_HI11Q_HOST_IDX(x) ((x) & (~BITS_HI11Q_HOST_IDX))\n#define BIT_GET_HI11Q_HOST_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI11Q_HOST_IDX) & BIT_MASK_HI11Q_HOST_IDX)\n#define BIT_SET_HI11Q_HOST_IDX(x, v)                                           \\\n\t(BIT_CLEAR_HI11Q_HOST_IDX(x) | BIT_HI11Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH5_TXBD_DESA_H\t\t\t(Offset 0x1364) */\n\n#define BIT_SHIFT_ACH5_TXBD_DESA_H 0\n#define BIT_MASK_ACH5_TXBD_DESA_H 0xffffffffL\n#define BIT_ACH5_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_ACH5_TXBD_DESA_H) << BIT_SHIFT_ACH5_TXBD_DESA_H)\n#define BITS_ACH5_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_ACH5_TXBD_DESA_H << BIT_SHIFT_ACH5_TXBD_DESA_H)\n#define BIT_CLEAR_ACH5_TXBD_DESA_H(x) ((x) & (~BITS_ACH5_TXBD_DESA_H))\n#define BIT_GET_ACH5_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH5_TXBD_DESA_H) & BIT_MASK_ACH5_TXBD_DESA_H)\n#define BIT_SET_ACH5_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_ACH5_TXBD_DESA_H(x) | BIT_ACH5_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI12Q_TXBD_IDX\t\t\t(Offset 0x1368) */\n\n#define BIT_SHIFT_HI12Q_HW_IDX 16\n#define BIT_MASK_HI12Q_HW_IDX 0xfff\n#define BIT_HI12Q_HW_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_HI12Q_HW_IDX) << BIT_SHIFT_HI12Q_HW_IDX)\n#define BITS_HI12Q_HW_IDX (BIT_MASK_HI12Q_HW_IDX << BIT_SHIFT_HI12Q_HW_IDX)\n#define BIT_CLEAR_HI12Q_HW_IDX(x) ((x) & (~BITS_HI12Q_HW_IDX))\n#define BIT_GET_HI12Q_HW_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_HI12Q_HW_IDX) & BIT_MASK_HI12Q_HW_IDX)\n#define BIT_SET_HI12Q_HW_IDX(x, v)                                             \\\n\t(BIT_CLEAR_HI12Q_HW_IDX(x) | BIT_HI12Q_HW_IDX(v))\n\n#define BIT_SHIFT_HI12Q_HOST_IDX 0\n#define BIT_MASK_HI12Q_HOST_IDX 0xfff\n#define BIT_HI12Q_HOST_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_HI12Q_HOST_IDX) << BIT_SHIFT_HI12Q_HOST_IDX)\n#define BITS_HI12Q_HOST_IDX                                                    \\\n\t(BIT_MASK_HI12Q_HOST_IDX << BIT_SHIFT_HI12Q_HOST_IDX)\n#define BIT_CLEAR_HI12Q_HOST_IDX(x) ((x) & (~BITS_HI12Q_HOST_IDX))\n#define BIT_GET_HI12Q_HOST_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI12Q_HOST_IDX) & BIT_MASK_HI12Q_HOST_IDX)\n#define BIT_SET_HI12Q_HOST_IDX(x, v)                                           \\\n\t(BIT_CLEAR_HI12Q_HOST_IDX(x) | BIT_HI12Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH6_TXBD_DESA_L\t\t\t(Offset 0x1368) */\n\n#define BIT_SHIFT_ACH6_TXBD_DESA_L 0\n#define BIT_MASK_ACH6_TXBD_DESA_L 0xffffffffL\n#define BIT_ACH6_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_ACH6_TXBD_DESA_L) << BIT_SHIFT_ACH6_TXBD_DESA_L)\n#define BITS_ACH6_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_ACH6_TXBD_DESA_L << BIT_SHIFT_ACH6_TXBD_DESA_L)\n#define BIT_CLEAR_ACH6_TXBD_DESA_L(x) ((x) & (~BITS_ACH6_TXBD_DESA_L))\n#define BIT_GET_ACH6_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH6_TXBD_DESA_L) & BIT_MASK_ACH6_TXBD_DESA_L)\n#define BIT_SET_ACH6_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_ACH6_TXBD_DESA_L(x) | BIT_ACH6_TXBD_DESA_L(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI13Q_TXBD_IDX\t\t\t(Offset 0x136C) */\n\n#define BIT_SHIFT_HI13Q_HW_IDX 16\n#define BIT_MASK_HI13Q_HW_IDX 0xfff\n#define BIT_HI13Q_HW_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_HI13Q_HW_IDX) << BIT_SHIFT_HI13Q_HW_IDX)\n#define BITS_HI13Q_HW_IDX (BIT_MASK_HI13Q_HW_IDX << BIT_SHIFT_HI13Q_HW_IDX)\n#define BIT_CLEAR_HI13Q_HW_IDX(x) ((x) & (~BITS_HI13Q_HW_IDX))\n#define BIT_GET_HI13Q_HW_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_HI13Q_HW_IDX) & BIT_MASK_HI13Q_HW_IDX)\n#define BIT_SET_HI13Q_HW_IDX(x, v)                                             \\\n\t(BIT_CLEAR_HI13Q_HW_IDX(x) | BIT_HI13Q_HW_IDX(v))\n\n#define BIT_SHIFT_HI13Q_HOST_IDX 0\n#define BIT_MASK_HI13Q_HOST_IDX 0xfff\n#define BIT_HI13Q_HOST_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_HI13Q_HOST_IDX) << BIT_SHIFT_HI13Q_HOST_IDX)\n#define BITS_HI13Q_HOST_IDX                                                    \\\n\t(BIT_MASK_HI13Q_HOST_IDX << BIT_SHIFT_HI13Q_HOST_IDX)\n#define BIT_CLEAR_HI13Q_HOST_IDX(x) ((x) & (~BITS_HI13Q_HOST_IDX))\n#define BIT_GET_HI13Q_HOST_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI13Q_HOST_IDX) & BIT_MASK_HI13Q_HOST_IDX)\n#define BIT_SET_HI13Q_HOST_IDX(x, v)                                           \\\n\t(BIT_CLEAR_HI13Q_HOST_IDX(x) | BIT_HI13Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH6_TXBD_DESA_H\t\t\t(Offset 0x136C) */\n\n#define BIT_SHIFT_ACH6_TXBD_DESA_H 0\n#define BIT_MASK_ACH6_TXBD_DESA_H 0xffffffffL\n#define BIT_ACH6_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_ACH6_TXBD_DESA_H) << BIT_SHIFT_ACH6_TXBD_DESA_H)\n#define BITS_ACH6_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_ACH6_TXBD_DESA_H << BIT_SHIFT_ACH6_TXBD_DESA_H)\n#define BIT_CLEAR_ACH6_TXBD_DESA_H(x) ((x) & (~BITS_ACH6_TXBD_DESA_H))\n#define BIT_GET_ACH6_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH6_TXBD_DESA_H) & BIT_MASK_ACH6_TXBD_DESA_H)\n#define BIT_SET_ACH6_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_ACH6_TXBD_DESA_H(x) | BIT_ACH6_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI14Q_TXBD_IDX\t\t\t(Offset 0x1370) */\n\n#define BIT_SHIFT_HI14Q_HW_IDX 16\n#define BIT_MASK_HI14Q_HW_IDX 0xfff\n#define BIT_HI14Q_HW_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_HI14Q_HW_IDX) << BIT_SHIFT_HI14Q_HW_IDX)\n#define BITS_HI14Q_HW_IDX (BIT_MASK_HI14Q_HW_IDX << BIT_SHIFT_HI14Q_HW_IDX)\n#define BIT_CLEAR_HI14Q_HW_IDX(x) ((x) & (~BITS_HI14Q_HW_IDX))\n#define BIT_GET_HI14Q_HW_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_HI14Q_HW_IDX) & BIT_MASK_HI14Q_HW_IDX)\n#define BIT_SET_HI14Q_HW_IDX(x, v)                                             \\\n\t(BIT_CLEAR_HI14Q_HW_IDX(x) | BIT_HI14Q_HW_IDX(v))\n\n#define BIT_SHIFT_HI14Q_HOST_IDX 0\n#define BIT_MASK_HI14Q_HOST_IDX 0xfff\n#define BIT_HI14Q_HOST_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_HI14Q_HOST_IDX) << BIT_SHIFT_HI14Q_HOST_IDX)\n#define BITS_HI14Q_HOST_IDX                                                    \\\n\t(BIT_MASK_HI14Q_HOST_IDX << BIT_SHIFT_HI14Q_HOST_IDX)\n#define BIT_CLEAR_HI14Q_HOST_IDX(x) ((x) & (~BITS_HI14Q_HOST_IDX))\n#define BIT_GET_HI14Q_HOST_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI14Q_HOST_IDX) & BIT_MASK_HI14Q_HOST_IDX)\n#define BIT_SET_HI14Q_HOST_IDX(x, v)                                           \\\n\t(BIT_CLEAR_HI14Q_HOST_IDX(x) | BIT_HI14Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH7_TXBD_DESA_L\t\t\t(Offset 0x1370) */\n\n#define BIT_SHIFT_ACH7_TXBD_DESA_L 0\n#define BIT_MASK_ACH7_TXBD_DESA_L 0xffffffffL\n#define BIT_ACH7_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_ACH7_TXBD_DESA_L) << BIT_SHIFT_ACH7_TXBD_DESA_L)\n#define BITS_ACH7_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_ACH7_TXBD_DESA_L << BIT_SHIFT_ACH7_TXBD_DESA_L)\n#define BIT_CLEAR_ACH7_TXBD_DESA_L(x) ((x) & (~BITS_ACH7_TXBD_DESA_L))\n#define BIT_GET_ACH7_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH7_TXBD_DESA_L) & BIT_MASK_ACH7_TXBD_DESA_L)\n#define BIT_SET_ACH7_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_ACH7_TXBD_DESA_L(x) | BIT_ACH7_TXBD_DESA_L(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI15Q_TXBD_IDX\t\t\t(Offset 0x1374) */\n\n#define BIT_SHIFT_HI15Q_HW_IDX 16\n#define BIT_MASK_HI15Q_HW_IDX 0xfff\n#define BIT_HI15Q_HW_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_HI15Q_HW_IDX) << BIT_SHIFT_HI15Q_HW_IDX)\n#define BITS_HI15Q_HW_IDX (BIT_MASK_HI15Q_HW_IDX << BIT_SHIFT_HI15Q_HW_IDX)\n#define BIT_CLEAR_HI15Q_HW_IDX(x) ((x) & (~BITS_HI15Q_HW_IDX))\n#define BIT_GET_HI15Q_HW_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_HI15Q_HW_IDX) & BIT_MASK_HI15Q_HW_IDX)\n#define BIT_SET_HI15Q_HW_IDX(x, v)                                             \\\n\t(BIT_CLEAR_HI15Q_HW_IDX(x) | BIT_HI15Q_HW_IDX(v))\n\n#define BIT_SHIFT_HI15Q_HOST_IDX 0\n#define BIT_MASK_HI15Q_HOST_IDX 0xfff\n#define BIT_HI15Q_HOST_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_HI15Q_HOST_IDX) << BIT_SHIFT_HI15Q_HOST_IDX)\n#define BITS_HI15Q_HOST_IDX                                                    \\\n\t(BIT_MASK_HI15Q_HOST_IDX << BIT_SHIFT_HI15Q_HOST_IDX)\n#define BIT_CLEAR_HI15Q_HOST_IDX(x) ((x) & (~BITS_HI15Q_HOST_IDX))\n#define BIT_GET_HI15Q_HOST_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI15Q_HOST_IDX) & BIT_MASK_HI15Q_HOST_IDX)\n#define BIT_SET_HI15Q_HOST_IDX(x, v)                                           \\\n\t(BIT_CLEAR_HI15Q_HOST_IDX(x) | BIT_HI15Q_HOST_IDX(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH7_TXBD_DESA_H\t\t\t(Offset 0x1374) */\n\n#define BIT_SHIFT_ACH7_TXBD_DESA_H 0\n#define BIT_MASK_ACH7_TXBD_DESA_H 0xffffffffL\n#define BIT_ACH7_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_ACH7_TXBD_DESA_H) << BIT_SHIFT_ACH7_TXBD_DESA_H)\n#define BITS_ACH7_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_ACH7_TXBD_DESA_H << BIT_SHIFT_ACH7_TXBD_DESA_H)\n#define BIT_CLEAR_ACH7_TXBD_DESA_H(x) ((x) & (~BITS_ACH7_TXBD_DESA_H))\n#define BIT_GET_ACH7_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH7_TXBD_DESA_H) & BIT_MASK_ACH7_TXBD_DESA_H)\n#define BIT_SET_ACH7_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_ACH7_TXBD_DESA_H(x) | BIT_ACH7_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI8Q_TXBD_DESA\t\t\t(Offset 0x1378) */\n\n#define BIT_SHIFT_HI8Q_TXBD_DESA 0\n#define BIT_MASK_HI8Q_TXBD_DESA 0xffffffffffffffffL\n#define BIT_HI8Q_TXBD_DESA(x)                                                  \\\n\t(((x) & BIT_MASK_HI8Q_TXBD_DESA) << BIT_SHIFT_HI8Q_TXBD_DESA)\n#define BITS_HI8Q_TXBD_DESA                                                    \\\n\t(BIT_MASK_HI8Q_TXBD_DESA << BIT_SHIFT_HI8Q_TXBD_DESA)\n#define BIT_CLEAR_HI8Q_TXBD_DESA(x) ((x) & (~BITS_HI8Q_TXBD_DESA))\n#define BIT_GET_HI8Q_TXBD_DESA(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI8Q_TXBD_DESA) & BIT_MASK_HI8Q_TXBD_DESA)\n#define BIT_SET_HI8Q_TXBD_DESA(x, v)                                           \\\n\t(BIT_CLEAR_HI8Q_TXBD_DESA(x) | BIT_HI8Q_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH8_TXBD_DESA_L\t\t\t(Offset 0x1378) */\n\n#define BIT_SHIFT_ACH8_TXBD_DESA_L 0\n#define BIT_MASK_ACH8_TXBD_DESA_L 0xffffffffL\n#define BIT_ACH8_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_ACH8_TXBD_DESA_L) << BIT_SHIFT_ACH8_TXBD_DESA_L)\n#define BITS_ACH8_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_ACH8_TXBD_DESA_L << BIT_SHIFT_ACH8_TXBD_DESA_L)\n#define BIT_CLEAR_ACH8_TXBD_DESA_L(x) ((x) & (~BITS_ACH8_TXBD_DESA_L))\n#define BIT_GET_ACH8_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH8_TXBD_DESA_L) & BIT_MASK_ACH8_TXBD_DESA_L)\n#define BIT_SET_ACH8_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_ACH8_TXBD_DESA_L(x) | BIT_ACH8_TXBD_DESA_L(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CHNL_DMA_CFG_V1\t\t\t(Offset 0x137C) */\n\n#define BIT_TXHCI_EN_V1 BIT(26)\n#define BIT_TXHCI_IDLE_V1 BIT(25)\n#define BIT_DMA_PRI_EN_V1 BIT(24)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH8_TXBD_DESA_H\t\t\t(Offset 0x137C) */\n\n#define BIT_SHIFT_ACH8_TXBD_DESA_H 0\n#define BIT_MASK_ACH8_TXBD_DESA_H 0xffffffffL\n#define BIT_ACH8_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_ACH8_TXBD_DESA_H) << BIT_SHIFT_ACH8_TXBD_DESA_H)\n#define BITS_ACH8_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_ACH8_TXBD_DESA_H << BIT_SHIFT_ACH8_TXBD_DESA_H)\n#define BIT_CLEAR_ACH8_TXBD_DESA_H(x) ((x) & (~BITS_ACH8_TXBD_DESA_H))\n#define BIT_GET_ACH8_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH8_TXBD_DESA_H) & BIT_MASK_ACH8_TXBD_DESA_H)\n#define BIT_SET_ACH8_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_ACH8_TXBD_DESA_H(x) | BIT_ACH8_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI9Q_TXBD_DESA\t\t\t(Offset 0x1380) */\n\n#define BIT_SHIFT_HI9Q_TXBD_DESA 0\n#define BIT_MASK_HI9Q_TXBD_DESA 0xffffffffffffffffL\n#define BIT_HI9Q_TXBD_DESA(x)                                                  \\\n\t(((x) & BIT_MASK_HI9Q_TXBD_DESA) << BIT_SHIFT_HI9Q_TXBD_DESA)\n#define BITS_HI9Q_TXBD_DESA                                                    \\\n\t(BIT_MASK_HI9Q_TXBD_DESA << BIT_SHIFT_HI9Q_TXBD_DESA)\n#define BIT_CLEAR_HI9Q_TXBD_DESA(x) ((x) & (~BITS_HI9Q_TXBD_DESA))\n#define BIT_GET_HI9Q_TXBD_DESA(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI9Q_TXBD_DESA) & BIT_MASK_HI9Q_TXBD_DESA)\n#define BIT_SET_HI9Q_TXBD_DESA(x, v)                                           \\\n\t(BIT_CLEAR_HI9Q_TXBD_DESA(x) | BIT_HI9Q_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH9_TXBD_DESA_L\t\t\t(Offset 0x1380) */\n\n#define BIT_SHIFT_ACH9_TXBD_DESA_L 0\n#define BIT_MASK_ACH9_TXBD_DESA_L 0xffffffffL\n#define BIT_ACH9_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_ACH9_TXBD_DESA_L) << BIT_SHIFT_ACH9_TXBD_DESA_L)\n#define BITS_ACH9_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_ACH9_TXBD_DESA_L << BIT_SHIFT_ACH9_TXBD_DESA_L)\n#define BIT_CLEAR_ACH9_TXBD_DESA_L(x) ((x) & (~BITS_ACH9_TXBD_DESA_L))\n#define BIT_GET_ACH9_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH9_TXBD_DESA_L) & BIT_MASK_ACH9_TXBD_DESA_L)\n#define BIT_SET_ACH9_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_ACH9_TXBD_DESA_L(x) | BIT_ACH9_TXBD_DESA_L(v))\n\n/* 2 REG_ACH9_TXBD_DESA_H\t\t\t(Offset 0x1384) */\n\n#define BIT_SHIFT_ACH9_TXBD_DESA_H 0\n#define BIT_MASK_ACH9_TXBD_DESA_H 0xffffffffL\n#define BIT_ACH9_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_ACH9_TXBD_DESA_H) << BIT_SHIFT_ACH9_TXBD_DESA_H)\n#define BITS_ACH9_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_ACH9_TXBD_DESA_H << BIT_SHIFT_ACH9_TXBD_DESA_H)\n#define BIT_CLEAR_ACH9_TXBD_DESA_H(x) ((x) & (~BITS_ACH9_TXBD_DESA_H))\n#define BIT_GET_ACH9_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH9_TXBD_DESA_H) & BIT_MASK_ACH9_TXBD_DESA_H)\n#define BIT_SET_ACH9_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_ACH9_TXBD_DESA_H(x) | BIT_ACH9_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI10Q_TXBD_DESA\t\t\t(Offset 0x1388) */\n\n#define BIT_SHIFT_HI10Q_TXBD_DESA 0\n#define BIT_MASK_HI10Q_TXBD_DESA 0xffffffffffffffffL\n#define BIT_HI10Q_TXBD_DESA(x)                                                 \\\n\t(((x) & BIT_MASK_HI10Q_TXBD_DESA) << BIT_SHIFT_HI10Q_TXBD_DESA)\n#define BITS_HI10Q_TXBD_DESA                                                   \\\n\t(BIT_MASK_HI10Q_TXBD_DESA << BIT_SHIFT_HI10Q_TXBD_DESA)\n#define BIT_CLEAR_HI10Q_TXBD_DESA(x) ((x) & (~BITS_HI10Q_TXBD_DESA))\n#define BIT_GET_HI10Q_TXBD_DESA(x)                                             \\\n\t(((x) >> BIT_SHIFT_HI10Q_TXBD_DESA) & BIT_MASK_HI10Q_TXBD_DESA)\n#define BIT_SET_HI10Q_TXBD_DESA(x, v)                                          \\\n\t(BIT_CLEAR_HI10Q_TXBD_DESA(x) | BIT_HI10Q_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH10_TXBD_DESA_L\t\t\t(Offset 0x1388) */\n\n#define BIT_SHIFT_ACH10_TXBD_DESA_L 0\n#define BIT_MASK_ACH10_TXBD_DESA_L 0xffffffffL\n#define BIT_ACH10_TXBD_DESA_L(x)                                               \\\n\t(((x) & BIT_MASK_ACH10_TXBD_DESA_L) << BIT_SHIFT_ACH10_TXBD_DESA_L)\n#define BITS_ACH10_TXBD_DESA_L                                                 \\\n\t(BIT_MASK_ACH10_TXBD_DESA_L << BIT_SHIFT_ACH10_TXBD_DESA_L)\n#define BIT_CLEAR_ACH10_TXBD_DESA_L(x) ((x) & (~BITS_ACH10_TXBD_DESA_L))\n#define BIT_GET_ACH10_TXBD_DESA_L(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH10_TXBD_DESA_L) & BIT_MASK_ACH10_TXBD_DESA_L)\n#define BIT_SET_ACH10_TXBD_DESA_L(x, v)                                        \\\n\t(BIT_CLEAR_ACH10_TXBD_DESA_L(x) | BIT_ACH10_TXBD_DESA_L(v))\n\n/* 2 REG_ACH10_TXBD_DESA_H\t\t\t(Offset 0x138C) */\n\n#define BIT_SHIFT_ACH10_TXBD_DESA_H 0\n#define BIT_MASK_ACH10_TXBD_DESA_H 0xffffffffL\n#define BIT_ACH10_TXBD_DESA_H(x)                                               \\\n\t(((x) & BIT_MASK_ACH10_TXBD_DESA_H) << BIT_SHIFT_ACH10_TXBD_DESA_H)\n#define BITS_ACH10_TXBD_DESA_H                                                 \\\n\t(BIT_MASK_ACH10_TXBD_DESA_H << BIT_SHIFT_ACH10_TXBD_DESA_H)\n#define BIT_CLEAR_ACH10_TXBD_DESA_H(x) ((x) & (~BITS_ACH10_TXBD_DESA_H))\n#define BIT_GET_ACH10_TXBD_DESA_H(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH10_TXBD_DESA_H) & BIT_MASK_ACH10_TXBD_DESA_H)\n#define BIT_SET_ACH10_TXBD_DESA_H(x, v)                                        \\\n\t(BIT_CLEAR_ACH10_TXBD_DESA_H(x) | BIT_ACH10_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI11Q_TXBD_DESA\t\t\t(Offset 0x1390) */\n\n#define BIT_SHIFT_HI11Q_TXBD_DESA 0\n#define BIT_MASK_HI11Q_TXBD_DESA 0xffffffffffffffffL\n#define BIT_HI11Q_TXBD_DESA(x)                                                 \\\n\t(((x) & BIT_MASK_HI11Q_TXBD_DESA) << BIT_SHIFT_HI11Q_TXBD_DESA)\n#define BITS_HI11Q_TXBD_DESA                                                   \\\n\t(BIT_MASK_HI11Q_TXBD_DESA << BIT_SHIFT_HI11Q_TXBD_DESA)\n#define BIT_CLEAR_HI11Q_TXBD_DESA(x) ((x) & (~BITS_HI11Q_TXBD_DESA))\n#define BIT_GET_HI11Q_TXBD_DESA(x)                                             \\\n\t(((x) >> BIT_SHIFT_HI11Q_TXBD_DESA) & BIT_MASK_HI11Q_TXBD_DESA)\n#define BIT_SET_HI11Q_TXBD_DESA(x, v)                                          \\\n\t(BIT_CLEAR_HI11Q_TXBD_DESA(x) | BIT_HI11Q_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH11_TXBD_DESA_L\t\t\t(Offset 0x1390) */\n\n#define BIT_SHIFT_ACH11_TXBD_DESA_L 0\n#define BIT_MASK_ACH11_TXBD_DESA_L 0xffffffffL\n#define BIT_ACH11_TXBD_DESA_L(x)                                               \\\n\t(((x) & BIT_MASK_ACH11_TXBD_DESA_L) << BIT_SHIFT_ACH11_TXBD_DESA_L)\n#define BITS_ACH11_TXBD_DESA_L                                                 \\\n\t(BIT_MASK_ACH11_TXBD_DESA_L << BIT_SHIFT_ACH11_TXBD_DESA_L)\n#define BIT_CLEAR_ACH11_TXBD_DESA_L(x) ((x) & (~BITS_ACH11_TXBD_DESA_L))\n#define BIT_GET_ACH11_TXBD_DESA_L(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH11_TXBD_DESA_L) & BIT_MASK_ACH11_TXBD_DESA_L)\n#define BIT_SET_ACH11_TXBD_DESA_L(x, v)                                        \\\n\t(BIT_CLEAR_ACH11_TXBD_DESA_L(x) | BIT_ACH11_TXBD_DESA_L(v))\n\n/* 2 REG_ACH11_TXBD_DESA_H\t\t\t(Offset 0x1394) */\n\n#define BIT_SHIFT_ACH11_TXBD_DESA_H 0\n#define BIT_MASK_ACH11_TXBD_DESA_H 0xffffffffL\n#define BIT_ACH11_TXBD_DESA_H(x)                                               \\\n\t(((x) & BIT_MASK_ACH11_TXBD_DESA_H) << BIT_SHIFT_ACH11_TXBD_DESA_H)\n#define BITS_ACH11_TXBD_DESA_H                                                 \\\n\t(BIT_MASK_ACH11_TXBD_DESA_H << BIT_SHIFT_ACH11_TXBD_DESA_H)\n#define BIT_CLEAR_ACH11_TXBD_DESA_H(x) ((x) & (~BITS_ACH11_TXBD_DESA_H))\n#define BIT_GET_ACH11_TXBD_DESA_H(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH11_TXBD_DESA_H) & BIT_MASK_ACH11_TXBD_DESA_H)\n#define BIT_SET_ACH11_TXBD_DESA_H(x, v)                                        \\\n\t(BIT_CLEAR_ACH11_TXBD_DESA_H(x) | BIT_ACH11_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI12Q_TXBD_DESA\t\t\t(Offset 0x1398) */\n\n#define BIT_SHIFT_HI12Q_TXBD_DESA 0\n#define BIT_MASK_HI12Q_TXBD_DESA 0xffffffffffffffffL\n#define BIT_HI12Q_TXBD_DESA(x)                                                 \\\n\t(((x) & BIT_MASK_HI12Q_TXBD_DESA) << BIT_SHIFT_HI12Q_TXBD_DESA)\n#define BITS_HI12Q_TXBD_DESA                                                   \\\n\t(BIT_MASK_HI12Q_TXBD_DESA << BIT_SHIFT_HI12Q_TXBD_DESA)\n#define BIT_CLEAR_HI12Q_TXBD_DESA(x) ((x) & (~BITS_HI12Q_TXBD_DESA))\n#define BIT_GET_HI12Q_TXBD_DESA(x)                                             \\\n\t(((x) >> BIT_SHIFT_HI12Q_TXBD_DESA) & BIT_MASK_HI12Q_TXBD_DESA)\n#define BIT_SET_HI12Q_TXBD_DESA(x, v)                                          \\\n\t(BIT_CLEAR_HI12Q_TXBD_DESA(x) | BIT_HI12Q_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH12_TXBD_DESA_L\t\t\t(Offset 0x1398) */\n\n#define BIT_SHIFT_ACH12_TXBD_DESA_L 0\n#define BIT_MASK_ACH12_TXBD_DESA_L 0xffffffffL\n#define BIT_ACH12_TXBD_DESA_L(x)                                               \\\n\t(((x) & BIT_MASK_ACH12_TXBD_DESA_L) << BIT_SHIFT_ACH12_TXBD_DESA_L)\n#define BITS_ACH12_TXBD_DESA_L                                                 \\\n\t(BIT_MASK_ACH12_TXBD_DESA_L << BIT_SHIFT_ACH12_TXBD_DESA_L)\n#define BIT_CLEAR_ACH12_TXBD_DESA_L(x) ((x) & (~BITS_ACH12_TXBD_DESA_L))\n#define BIT_GET_ACH12_TXBD_DESA_L(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH12_TXBD_DESA_L) & BIT_MASK_ACH12_TXBD_DESA_L)\n#define BIT_SET_ACH12_TXBD_DESA_L(x, v)                                        \\\n\t(BIT_CLEAR_ACH12_TXBD_DESA_L(x) | BIT_ACH12_TXBD_DESA_L(v))\n\n/* 2 REG_ACH12_TXBD_DESA_H\t\t\t(Offset 0x139C) */\n\n#define BIT_SHIFT_ACH12_TXBD_DESA_H 0\n#define BIT_MASK_ACH12_TXBD_DESA_H 0xffffffffL\n#define BIT_ACH12_TXBD_DESA_H(x)                                               \\\n\t(((x) & BIT_MASK_ACH12_TXBD_DESA_H) << BIT_SHIFT_ACH12_TXBD_DESA_H)\n#define BITS_ACH12_TXBD_DESA_H                                                 \\\n\t(BIT_MASK_ACH12_TXBD_DESA_H << BIT_SHIFT_ACH12_TXBD_DESA_H)\n#define BIT_CLEAR_ACH12_TXBD_DESA_H(x) ((x) & (~BITS_ACH12_TXBD_DESA_H))\n#define BIT_GET_ACH12_TXBD_DESA_H(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH12_TXBD_DESA_H) & BIT_MASK_ACH12_TXBD_DESA_H)\n#define BIT_SET_ACH12_TXBD_DESA_H(x, v)                                        \\\n\t(BIT_CLEAR_ACH12_TXBD_DESA_H(x) | BIT_ACH12_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI13Q_TXBD_DESA\t\t\t(Offset 0x13A0) */\n\n#define BIT_SHIFT_HI13Q_TXBD_DESA 0\n#define BIT_MASK_HI13Q_TXBD_DESA 0xffffffffffffffffL\n#define BIT_HI13Q_TXBD_DESA(x)                                                 \\\n\t(((x) & BIT_MASK_HI13Q_TXBD_DESA) << BIT_SHIFT_HI13Q_TXBD_DESA)\n#define BITS_HI13Q_TXBD_DESA                                                   \\\n\t(BIT_MASK_HI13Q_TXBD_DESA << BIT_SHIFT_HI13Q_TXBD_DESA)\n#define BIT_CLEAR_HI13Q_TXBD_DESA(x) ((x) & (~BITS_HI13Q_TXBD_DESA))\n#define BIT_GET_HI13Q_TXBD_DESA(x)                                             \\\n\t(((x) >> BIT_SHIFT_HI13Q_TXBD_DESA) & BIT_MASK_HI13Q_TXBD_DESA)\n#define BIT_SET_HI13Q_TXBD_DESA(x, v)                                          \\\n\t(BIT_CLEAR_HI13Q_TXBD_DESA(x) | BIT_HI13Q_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH13_TXBD_DESA_L\t\t\t(Offset 0x13A0) */\n\n#define BIT_SHIFT_ACH13_TXBD_DESA_L 0\n#define BIT_MASK_ACH13_TXBD_DESA_L 0xffffffffL\n#define BIT_ACH13_TXBD_DESA_L(x)                                               \\\n\t(((x) & BIT_MASK_ACH13_TXBD_DESA_L) << BIT_SHIFT_ACH13_TXBD_DESA_L)\n#define BITS_ACH13_TXBD_DESA_L                                                 \\\n\t(BIT_MASK_ACH13_TXBD_DESA_L << BIT_SHIFT_ACH13_TXBD_DESA_L)\n#define BIT_CLEAR_ACH13_TXBD_DESA_L(x) ((x) & (~BITS_ACH13_TXBD_DESA_L))\n#define BIT_GET_ACH13_TXBD_DESA_L(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH13_TXBD_DESA_L) & BIT_MASK_ACH13_TXBD_DESA_L)\n#define BIT_SET_ACH13_TXBD_DESA_L(x, v)                                        \\\n\t(BIT_CLEAR_ACH13_TXBD_DESA_L(x) | BIT_ACH13_TXBD_DESA_L(v))\n\n/* 2 REG_ACH13_TXBD_DESA_H\t\t\t(Offset 0x13A4) */\n\n#define BIT_SHIFT_ACH13_TXBD_DESA_H 0\n#define BIT_MASK_ACH13_TXBD_DESA_H 0xffffffffL\n#define BIT_ACH13_TXBD_DESA_H(x)                                               \\\n\t(((x) & BIT_MASK_ACH13_TXBD_DESA_H) << BIT_SHIFT_ACH13_TXBD_DESA_H)\n#define BITS_ACH13_TXBD_DESA_H                                                 \\\n\t(BIT_MASK_ACH13_TXBD_DESA_H << BIT_SHIFT_ACH13_TXBD_DESA_H)\n#define BIT_CLEAR_ACH13_TXBD_DESA_H(x) ((x) & (~BITS_ACH13_TXBD_DESA_H))\n#define BIT_GET_ACH13_TXBD_DESA_H(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH13_TXBD_DESA_H) & BIT_MASK_ACH13_TXBD_DESA_H)\n#define BIT_SET_ACH13_TXBD_DESA_H(x, v)                                        \\\n\t(BIT_CLEAR_ACH13_TXBD_DESA_H(x) | BIT_ACH13_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI14Q_TXBD_DESA\t\t\t(Offset 0x13A8) */\n\n#define BIT_SHIFT_HI14Q_TXBD_DESA 0\n#define BIT_MASK_HI14Q_TXBD_DESA 0xffffffffffffffffL\n#define BIT_HI14Q_TXBD_DESA(x)                                                 \\\n\t(((x) & BIT_MASK_HI14Q_TXBD_DESA) << BIT_SHIFT_HI14Q_TXBD_DESA)\n#define BITS_HI14Q_TXBD_DESA                                                   \\\n\t(BIT_MASK_HI14Q_TXBD_DESA << BIT_SHIFT_HI14Q_TXBD_DESA)\n#define BIT_CLEAR_HI14Q_TXBD_DESA(x) ((x) & (~BITS_HI14Q_TXBD_DESA))\n#define BIT_GET_HI14Q_TXBD_DESA(x)                                             \\\n\t(((x) >> BIT_SHIFT_HI14Q_TXBD_DESA) & BIT_MASK_HI14Q_TXBD_DESA)\n#define BIT_SET_HI14Q_TXBD_DESA(x, v)                                          \\\n\t(BIT_CLEAR_HI14Q_TXBD_DESA(x) | BIT_HI14Q_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HI0Q_TXBD_DESA_L\t\t\t(Offset 0x13A8) */\n\n#define BIT_SHIFT_HI0Q_TXBD_DESA_L 0\n#define BIT_MASK_HI0Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI0Q_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_HI0Q_TXBD_DESA_L) << BIT_SHIFT_HI0Q_TXBD_DESA_L)\n#define BITS_HI0Q_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_HI0Q_TXBD_DESA_L << BIT_SHIFT_HI0Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI0Q_TXBD_DESA_L(x) ((x) & (~BITS_HI0Q_TXBD_DESA_L))\n#define BIT_GET_HI0Q_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_L) & BIT_MASK_HI0Q_TXBD_DESA_L)\n#define BIT_SET_HI0Q_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_HI0Q_TXBD_DESA_L(x) | BIT_HI0Q_TXBD_DESA_L(v))\n\n/* 2 REG_HI0Q_TXBD_DESA_H\t\t\t(Offset 0x13AC) */\n\n#define BIT_SHIFT_HI0Q_TXBD_DESA_H 0\n#define BIT_MASK_HI0Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI0Q_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_HI0Q_TXBD_DESA_H) << BIT_SHIFT_HI0Q_TXBD_DESA_H)\n#define BITS_HI0Q_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_HI0Q_TXBD_DESA_H << BIT_SHIFT_HI0Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI0Q_TXBD_DESA_H(x) ((x) & (~BITS_HI0Q_TXBD_DESA_H))\n#define BIT_GET_HI0Q_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_H) & BIT_MASK_HI0Q_TXBD_DESA_H)\n#define BIT_SET_HI0Q_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_HI0Q_TXBD_DESA_H(x) | BIT_HI0Q_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI15Q_TXBD_DESA\t\t\t(Offset 0x13B0) */\n\n#define BIT_SHIFT_HI15Q_TXBD_DESA 0\n#define BIT_MASK_HI15Q_TXBD_DESA 0xffffffffffffffffL\n#define BIT_HI15Q_TXBD_DESA(x)                                                 \\\n\t(((x) & BIT_MASK_HI15Q_TXBD_DESA) << BIT_SHIFT_HI15Q_TXBD_DESA)\n#define BITS_HI15Q_TXBD_DESA                                                   \\\n\t(BIT_MASK_HI15Q_TXBD_DESA << BIT_SHIFT_HI15Q_TXBD_DESA)\n#define BIT_CLEAR_HI15Q_TXBD_DESA(x) ((x) & (~BITS_HI15Q_TXBD_DESA))\n#define BIT_GET_HI15Q_TXBD_DESA(x)                                             \\\n\t(((x) >> BIT_SHIFT_HI15Q_TXBD_DESA) & BIT_MASK_HI15Q_TXBD_DESA)\n#define BIT_SET_HI15Q_TXBD_DESA(x, v)                                          \\\n\t(BIT_CLEAR_HI15Q_TXBD_DESA(x) | BIT_HI15Q_TXBD_DESA(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HI1Q_TXBD_DESA_L\t\t\t(Offset 0x13B0) */\n\n#define BIT_SHIFT_HI1Q_TXBD_DESA_L 0\n#define BIT_MASK_HI1Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI1Q_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_HI1Q_TXBD_DESA_L) << BIT_SHIFT_HI1Q_TXBD_DESA_L)\n#define BITS_HI1Q_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_HI1Q_TXBD_DESA_L << BIT_SHIFT_HI1Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI1Q_TXBD_DESA_L(x) ((x) & (~BITS_HI1Q_TXBD_DESA_L))\n#define BIT_GET_HI1Q_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_L) & BIT_MASK_HI1Q_TXBD_DESA_L)\n#define BIT_SET_HI1Q_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_HI1Q_TXBD_DESA_L(x) | BIT_HI1Q_TXBD_DESA_L(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PCIE_HISR0_V1\t\t\t(Offset 0x13B4) */\n\n#define BIT_PRE_TX_ERR_INT BIT(31)\n#define BIT_HISR1_IND BIT(11)\n#define BIT_TXDMAOK_CHANNEL15 BIT(7)\n#define BIT_TXDMAOK_CHANNEL14 BIT(6)\n#define BIT_TXDMAOK_CHANNEL3 BIT(5)\n#define BIT_TXDMAOK_CHANNEL2 BIT(4)\n#define BIT_TXDMAOK_CHANNEL1 BIT(3)\n#define BIT_TXDMAOK_CHANNEL0 BIT(2)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HI1Q_TXBD_DESA_H\t\t\t(Offset 0x13B4) */\n\n#define BIT_SHIFT_HI1Q_TXBD_DESA_H 0\n#define BIT_MASK_HI1Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI1Q_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_HI1Q_TXBD_DESA_H) << BIT_SHIFT_HI1Q_TXBD_DESA_H)\n#define BITS_HI1Q_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_HI1Q_TXBD_DESA_H << BIT_SHIFT_HI1Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI1Q_TXBD_DESA_H(x) ((x) & (~BITS_HI1Q_TXBD_DESA_H))\n#define BIT_GET_HI1Q_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_H) & BIT_MASK_HI1Q_TXBD_DESA_H)\n#define BIT_SET_HI1Q_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_HI1Q_TXBD_DESA_H(x) | BIT_HI1Q_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI8Q_TXBD_NUM\t\t\t(Offset 0x13B8) */\n\n#define BIT_HI8Q_FLAG BIT(14)\n\n#define BIT_SHIFT_HI8Q_DESC_MODE 12\n#define BIT_MASK_HI8Q_DESC_MODE 0x3\n#define BIT_HI8Q_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_HI8Q_DESC_MODE) << BIT_SHIFT_HI8Q_DESC_MODE)\n#define BITS_HI8Q_DESC_MODE                                                    \\\n\t(BIT_MASK_HI8Q_DESC_MODE << BIT_SHIFT_HI8Q_DESC_MODE)\n#define BIT_CLEAR_HI8Q_DESC_MODE(x) ((x) & (~BITS_HI8Q_DESC_MODE))\n#define BIT_GET_HI8Q_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI8Q_DESC_MODE) & BIT_MASK_HI8Q_DESC_MODE)\n#define BIT_SET_HI8Q_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_HI8Q_DESC_MODE(x) | BIT_HI8Q_DESC_MODE(v))\n\n#define BIT_SHIFT_HI8Q_DESC_NUM 0\n#define BIT_MASK_HI8Q_DESC_NUM 0xfff\n#define BIT_HI8Q_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_HI8Q_DESC_NUM) << BIT_SHIFT_HI8Q_DESC_NUM)\n#define BITS_HI8Q_DESC_NUM (BIT_MASK_HI8Q_DESC_NUM << BIT_SHIFT_HI8Q_DESC_NUM)\n#define BIT_CLEAR_HI8Q_DESC_NUM(x) ((x) & (~BITS_HI8Q_DESC_NUM))\n#define BIT_GET_HI8Q_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI8Q_DESC_NUM) & BIT_MASK_HI8Q_DESC_NUM)\n#define BIT_SET_HI8Q_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_HI8Q_DESC_NUM(x) | BIT_HI8Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HI2Q_TXBD_DESA_L\t\t\t(Offset 0x13B8) */\n\n#define BIT_SHIFT_HI2Q_TXBD_DESA_L 0\n#define BIT_MASK_HI2Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI2Q_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_HI2Q_TXBD_DESA_L) << BIT_SHIFT_HI2Q_TXBD_DESA_L)\n#define BITS_HI2Q_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_HI2Q_TXBD_DESA_L << BIT_SHIFT_HI2Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI2Q_TXBD_DESA_L(x) ((x) & (~BITS_HI2Q_TXBD_DESA_L))\n#define BIT_GET_HI2Q_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_L) & BIT_MASK_HI2Q_TXBD_DESA_L)\n#define BIT_SET_HI2Q_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_HI2Q_TXBD_DESA_L(x) | BIT_HI2Q_TXBD_DESA_L(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI9Q_TXBD_NUM\t\t\t(Offset 0x13BA) */\n\n#define BIT_HI9Q_FLAG BIT(14)\n\n#define BIT_SHIFT_HI9Q_DESC_MODE 12\n#define BIT_MASK_HI9Q_DESC_MODE 0x3\n#define BIT_HI9Q_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_HI9Q_DESC_MODE) << BIT_SHIFT_HI9Q_DESC_MODE)\n#define BITS_HI9Q_DESC_MODE                                                    \\\n\t(BIT_MASK_HI9Q_DESC_MODE << BIT_SHIFT_HI9Q_DESC_MODE)\n#define BIT_CLEAR_HI9Q_DESC_MODE(x) ((x) & (~BITS_HI9Q_DESC_MODE))\n#define BIT_GET_HI9Q_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI9Q_DESC_MODE) & BIT_MASK_HI9Q_DESC_MODE)\n#define BIT_SET_HI9Q_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_HI9Q_DESC_MODE(x) | BIT_HI9Q_DESC_MODE(v))\n\n#define BIT_SHIFT_HI9Q_DESC_NUM 0\n#define BIT_MASK_HI9Q_DESC_NUM 0xfff\n#define BIT_HI9Q_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_HI9Q_DESC_NUM) << BIT_SHIFT_HI9Q_DESC_NUM)\n#define BITS_HI9Q_DESC_NUM (BIT_MASK_HI9Q_DESC_NUM << BIT_SHIFT_HI9Q_DESC_NUM)\n#define BIT_CLEAR_HI9Q_DESC_NUM(x) ((x) & (~BITS_HI9Q_DESC_NUM))\n#define BIT_GET_HI9Q_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_HI9Q_DESC_NUM) & BIT_MASK_HI9Q_DESC_NUM)\n#define BIT_SET_HI9Q_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_HI9Q_DESC_NUM(x) | BIT_HI9Q_DESC_NUM(v))\n\n/* 2 REG_HI10Q_TXBD_NUM\t\t\t(Offset 0x13BC) */\n\n#define BIT_HI10Q_FLAG BIT(14)\n\n#define BIT_SHIFT_HI10Q_DESC_MODE 12\n#define BIT_MASK_HI10Q_DESC_MODE 0x3\n#define BIT_HI10Q_DESC_MODE(x)                                                 \\\n\t(((x) & BIT_MASK_HI10Q_DESC_MODE) << BIT_SHIFT_HI10Q_DESC_MODE)\n#define BITS_HI10Q_DESC_MODE                                                   \\\n\t(BIT_MASK_HI10Q_DESC_MODE << BIT_SHIFT_HI10Q_DESC_MODE)\n#define BIT_CLEAR_HI10Q_DESC_MODE(x) ((x) & (~BITS_HI10Q_DESC_MODE))\n#define BIT_GET_HI10Q_DESC_MODE(x)                                             \\\n\t(((x) >> BIT_SHIFT_HI10Q_DESC_MODE) & BIT_MASK_HI10Q_DESC_MODE)\n#define BIT_SET_HI10Q_DESC_MODE(x, v)                                          \\\n\t(BIT_CLEAR_HI10Q_DESC_MODE(x) | BIT_HI10Q_DESC_MODE(v))\n\n#define BIT_SHIFT_HI10Q_DESC_NUM 0\n#define BIT_MASK_HI10Q_DESC_NUM 0xfff\n#define BIT_HI10Q_DESC_NUM(x)                                                  \\\n\t(((x) & BIT_MASK_HI10Q_DESC_NUM) << BIT_SHIFT_HI10Q_DESC_NUM)\n#define BITS_HI10Q_DESC_NUM                                                    \\\n\t(BIT_MASK_HI10Q_DESC_NUM << BIT_SHIFT_HI10Q_DESC_NUM)\n#define BIT_CLEAR_HI10Q_DESC_NUM(x) ((x) & (~BITS_HI10Q_DESC_NUM))\n#define BIT_GET_HI10Q_DESC_NUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI10Q_DESC_NUM) & BIT_MASK_HI10Q_DESC_NUM)\n#define BIT_SET_HI10Q_DESC_NUM(x, v)                                           \\\n\t(BIT_CLEAR_HI10Q_DESC_NUM(x) | BIT_HI10Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HI2Q_TXBD_DESA_H\t\t\t(Offset 0x13BC) */\n\n#define BIT_SHIFT_HI2Q_TXBD_DESA_H 0\n#define BIT_MASK_HI2Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI2Q_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_HI2Q_TXBD_DESA_H) << BIT_SHIFT_HI2Q_TXBD_DESA_H)\n#define BITS_HI2Q_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_HI2Q_TXBD_DESA_H << BIT_SHIFT_HI2Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI2Q_TXBD_DESA_H(x) ((x) & (~BITS_HI2Q_TXBD_DESA_H))\n#define BIT_GET_HI2Q_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_H) & BIT_MASK_HI2Q_TXBD_DESA_H)\n#define BIT_SET_HI2Q_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_HI2Q_TXBD_DESA_H(x) | BIT_HI2Q_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI11Q_TXBD_NUM\t\t\t(Offset 0x13BE) */\n\n#define BIT_HI11Q_FLAG BIT(14)\n\n#define BIT_SHIFT_HI11Q_DESC_MODE 12\n#define BIT_MASK_HI11Q_DESC_MODE 0x3\n#define BIT_HI11Q_DESC_MODE(x)                                                 \\\n\t(((x) & BIT_MASK_HI11Q_DESC_MODE) << BIT_SHIFT_HI11Q_DESC_MODE)\n#define BITS_HI11Q_DESC_MODE                                                   \\\n\t(BIT_MASK_HI11Q_DESC_MODE << BIT_SHIFT_HI11Q_DESC_MODE)\n#define BIT_CLEAR_HI11Q_DESC_MODE(x) ((x) & (~BITS_HI11Q_DESC_MODE))\n#define BIT_GET_HI11Q_DESC_MODE(x)                                             \\\n\t(((x) >> BIT_SHIFT_HI11Q_DESC_MODE) & BIT_MASK_HI11Q_DESC_MODE)\n#define BIT_SET_HI11Q_DESC_MODE(x, v)                                          \\\n\t(BIT_CLEAR_HI11Q_DESC_MODE(x) | BIT_HI11Q_DESC_MODE(v))\n\n#define BIT_SHIFT_HI11Q_DESC_NUM 0\n#define BIT_MASK_HI11Q_DESC_NUM 0xfff\n#define BIT_HI11Q_DESC_NUM(x)                                                  \\\n\t(((x) & BIT_MASK_HI11Q_DESC_NUM) << BIT_SHIFT_HI11Q_DESC_NUM)\n#define BITS_HI11Q_DESC_NUM                                                    \\\n\t(BIT_MASK_HI11Q_DESC_NUM << BIT_SHIFT_HI11Q_DESC_NUM)\n#define BIT_CLEAR_HI11Q_DESC_NUM(x) ((x) & (~BITS_HI11Q_DESC_NUM))\n#define BIT_GET_HI11Q_DESC_NUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI11Q_DESC_NUM) & BIT_MASK_HI11Q_DESC_NUM)\n#define BIT_SET_HI11Q_DESC_NUM(x, v)                                           \\\n\t(BIT_CLEAR_HI11Q_DESC_NUM(x) | BIT_HI11Q_DESC_NUM(v))\n\n/* 2 REG_HI12Q_TXBD_NUM\t\t\t(Offset 0x13C0) */\n\n#define BIT_HI12Q_FLAG BIT(14)\n\n#define BIT_SHIFT_HI12Q_DESC_MODE 12\n#define BIT_MASK_HI12Q_DESC_MODE 0x3\n#define BIT_HI12Q_DESC_MODE(x)                                                 \\\n\t(((x) & BIT_MASK_HI12Q_DESC_MODE) << BIT_SHIFT_HI12Q_DESC_MODE)\n#define BITS_HI12Q_DESC_MODE                                                   \\\n\t(BIT_MASK_HI12Q_DESC_MODE << BIT_SHIFT_HI12Q_DESC_MODE)\n#define BIT_CLEAR_HI12Q_DESC_MODE(x) ((x) & (~BITS_HI12Q_DESC_MODE))\n#define BIT_GET_HI12Q_DESC_MODE(x)                                             \\\n\t(((x) >> BIT_SHIFT_HI12Q_DESC_MODE) & BIT_MASK_HI12Q_DESC_MODE)\n#define BIT_SET_HI12Q_DESC_MODE(x, v)                                          \\\n\t(BIT_CLEAR_HI12Q_DESC_MODE(x) | BIT_HI12Q_DESC_MODE(v))\n\n#define BIT_SHIFT_HI12Q_DESC_NUM 0\n#define BIT_MASK_HI12Q_DESC_NUM 0xfff\n#define BIT_HI12Q_DESC_NUM(x)                                                  \\\n\t(((x) & BIT_MASK_HI12Q_DESC_NUM) << BIT_SHIFT_HI12Q_DESC_NUM)\n#define BITS_HI12Q_DESC_NUM                                                    \\\n\t(BIT_MASK_HI12Q_DESC_NUM << BIT_SHIFT_HI12Q_DESC_NUM)\n#define BIT_CLEAR_HI12Q_DESC_NUM(x) ((x) & (~BITS_HI12Q_DESC_NUM))\n#define BIT_GET_HI12Q_DESC_NUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI12Q_DESC_NUM) & BIT_MASK_HI12Q_DESC_NUM)\n#define BIT_SET_HI12Q_DESC_NUM(x, v)                                           \\\n\t(BIT_CLEAR_HI12Q_DESC_NUM(x) | BIT_HI12Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HI3Q_TXBD_DESA_L\t\t\t(Offset 0x13C0) */\n\n#define BIT_SHIFT_HI3Q_TXBD_DESA_L 0\n#define BIT_MASK_HI3Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI3Q_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_HI3Q_TXBD_DESA_L) << BIT_SHIFT_HI3Q_TXBD_DESA_L)\n#define BITS_HI3Q_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_HI3Q_TXBD_DESA_L << BIT_SHIFT_HI3Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI3Q_TXBD_DESA_L(x) ((x) & (~BITS_HI3Q_TXBD_DESA_L))\n#define BIT_GET_HI3Q_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_L) & BIT_MASK_HI3Q_TXBD_DESA_L)\n#define BIT_SET_HI3Q_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_HI3Q_TXBD_DESA_L(x) | BIT_HI3Q_TXBD_DESA_L(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI13Q_TXBD_NUM\t\t\t(Offset 0x13C2) */\n\n#define BIT_HI13Q_FLAG BIT(14)\n\n#define BIT_SHIFT_HI13Q_DESC_MODE 12\n#define BIT_MASK_HI13Q_DESC_MODE 0x3\n#define BIT_HI13Q_DESC_MODE(x)                                                 \\\n\t(((x) & BIT_MASK_HI13Q_DESC_MODE) << BIT_SHIFT_HI13Q_DESC_MODE)\n#define BITS_HI13Q_DESC_MODE                                                   \\\n\t(BIT_MASK_HI13Q_DESC_MODE << BIT_SHIFT_HI13Q_DESC_MODE)\n#define BIT_CLEAR_HI13Q_DESC_MODE(x) ((x) & (~BITS_HI13Q_DESC_MODE))\n#define BIT_GET_HI13Q_DESC_MODE(x)                                             \\\n\t(((x) >> BIT_SHIFT_HI13Q_DESC_MODE) & BIT_MASK_HI13Q_DESC_MODE)\n#define BIT_SET_HI13Q_DESC_MODE(x, v)                                          \\\n\t(BIT_CLEAR_HI13Q_DESC_MODE(x) | BIT_HI13Q_DESC_MODE(v))\n\n#define BIT_SHIFT_HI13Q_DESC_NUM 0\n#define BIT_MASK_HI13Q_DESC_NUM 0xfff\n#define BIT_HI13Q_DESC_NUM(x)                                                  \\\n\t(((x) & BIT_MASK_HI13Q_DESC_NUM) << BIT_SHIFT_HI13Q_DESC_NUM)\n#define BITS_HI13Q_DESC_NUM                                                    \\\n\t(BIT_MASK_HI13Q_DESC_NUM << BIT_SHIFT_HI13Q_DESC_NUM)\n#define BIT_CLEAR_HI13Q_DESC_NUM(x) ((x) & (~BITS_HI13Q_DESC_NUM))\n#define BIT_GET_HI13Q_DESC_NUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI13Q_DESC_NUM) & BIT_MASK_HI13Q_DESC_NUM)\n#define BIT_SET_HI13Q_DESC_NUM(x, v)                                           \\\n\t(BIT_CLEAR_HI13Q_DESC_NUM(x) | BIT_HI13Q_DESC_NUM(v))\n\n/* 2 REG_HI14Q_TXBD_NUM\t\t\t(Offset 0x13C4) */\n\n#define BIT_HI14Q_FLAG BIT(14)\n\n#define BIT_SHIFT_HI14Q_DESC_MODE 12\n#define BIT_MASK_HI14Q_DESC_MODE 0x3\n#define BIT_HI14Q_DESC_MODE(x)                                                 \\\n\t(((x) & BIT_MASK_HI14Q_DESC_MODE) << BIT_SHIFT_HI14Q_DESC_MODE)\n#define BITS_HI14Q_DESC_MODE                                                   \\\n\t(BIT_MASK_HI14Q_DESC_MODE << BIT_SHIFT_HI14Q_DESC_MODE)\n#define BIT_CLEAR_HI14Q_DESC_MODE(x) ((x) & (~BITS_HI14Q_DESC_MODE))\n#define BIT_GET_HI14Q_DESC_MODE(x)                                             \\\n\t(((x) >> BIT_SHIFT_HI14Q_DESC_MODE) & BIT_MASK_HI14Q_DESC_MODE)\n#define BIT_SET_HI14Q_DESC_MODE(x, v)                                          \\\n\t(BIT_CLEAR_HI14Q_DESC_MODE(x) | BIT_HI14Q_DESC_MODE(v))\n\n#define BIT_SHIFT_HI14Q_DESC_NUM 0\n#define BIT_MASK_HI14Q_DESC_NUM 0xfff\n#define BIT_HI14Q_DESC_NUM(x)                                                  \\\n\t(((x) & BIT_MASK_HI14Q_DESC_NUM) << BIT_SHIFT_HI14Q_DESC_NUM)\n#define BITS_HI14Q_DESC_NUM                                                    \\\n\t(BIT_MASK_HI14Q_DESC_NUM << BIT_SHIFT_HI14Q_DESC_NUM)\n#define BIT_CLEAR_HI14Q_DESC_NUM(x) ((x) & (~BITS_HI14Q_DESC_NUM))\n#define BIT_GET_HI14Q_DESC_NUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI14Q_DESC_NUM) & BIT_MASK_HI14Q_DESC_NUM)\n#define BIT_SET_HI14Q_DESC_NUM(x, v)                                           \\\n\t(BIT_CLEAR_HI14Q_DESC_NUM(x) | BIT_HI14Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HI3Q_TXBD_DESA_H\t\t\t(Offset 0x13C4) */\n\n#define BIT_SHIFT_HI3Q_TXBD_DESA_H 0\n#define BIT_MASK_HI3Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI3Q_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_HI3Q_TXBD_DESA_H) << BIT_SHIFT_HI3Q_TXBD_DESA_H)\n#define BITS_HI3Q_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_HI3Q_TXBD_DESA_H << BIT_SHIFT_HI3Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI3Q_TXBD_DESA_H(x) ((x) & (~BITS_HI3Q_TXBD_DESA_H))\n#define BIT_GET_HI3Q_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_H) & BIT_MASK_HI3Q_TXBD_DESA_H)\n#define BIT_SET_HI3Q_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_HI3Q_TXBD_DESA_H(x) | BIT_HI3Q_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_HI15Q_TXBD_NUM\t\t\t(Offset 0x13C6) */\n\n#define BIT_HI15Q_FLAG BIT(14)\n\n#define BIT_SHIFT_HI15Q_DESC_MODE 12\n#define BIT_MASK_HI15Q_DESC_MODE 0x3\n#define BIT_HI15Q_DESC_MODE(x)                                                 \\\n\t(((x) & BIT_MASK_HI15Q_DESC_MODE) << BIT_SHIFT_HI15Q_DESC_MODE)\n#define BITS_HI15Q_DESC_MODE                                                   \\\n\t(BIT_MASK_HI15Q_DESC_MODE << BIT_SHIFT_HI15Q_DESC_MODE)\n#define BIT_CLEAR_HI15Q_DESC_MODE(x) ((x) & (~BITS_HI15Q_DESC_MODE))\n#define BIT_GET_HI15Q_DESC_MODE(x)                                             \\\n\t(((x) >> BIT_SHIFT_HI15Q_DESC_MODE) & BIT_MASK_HI15Q_DESC_MODE)\n#define BIT_SET_HI15Q_DESC_MODE(x, v)                                          \\\n\t(BIT_CLEAR_HI15Q_DESC_MODE(x) | BIT_HI15Q_DESC_MODE(v))\n\n#define BIT_SHIFT_HI15Q_DESC_NUM 0\n#define BIT_MASK_HI15Q_DESC_NUM 0xfff\n#define BIT_HI15Q_DESC_NUM(x)                                                  \\\n\t(((x) & BIT_MASK_HI15Q_DESC_NUM) << BIT_SHIFT_HI15Q_DESC_NUM)\n#define BITS_HI15Q_DESC_NUM                                                    \\\n\t(BIT_MASK_HI15Q_DESC_NUM << BIT_SHIFT_HI15Q_DESC_NUM)\n#define BIT_CLEAR_HI15Q_DESC_NUM(x) ((x) & (~BITS_HI15Q_DESC_NUM))\n#define BIT_GET_HI15Q_DESC_NUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_HI15Q_DESC_NUM) & BIT_MASK_HI15Q_DESC_NUM)\n#define BIT_SET_HI15Q_DESC_NUM(x, v)                                           \\\n\t(BIT_CLEAR_HI15Q_DESC_NUM(x) | BIT_HI15Q_DESC_NUM(v))\n\n/* 2 REG_HIQ_DMA_STOP\t\t\t(Offset 0x13C8) */\n\n#define BIT_STOP_HI15Q BIT(7)\n#define BIT_STOP_HI14Q BIT(6)\n#define BIT_STOP_HI13Q BIT(5)\n#define BIT_STOP_HI12Q BIT(4)\n#define BIT_STOP_HI11Q BIT(3)\n#define BIT_STOP_HI10Q BIT(2)\n#define BIT_STOP_HI9Q BIT(1)\n#define BIT_STOP_HI8Q BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HI4Q_TXBD_DESA_L\t\t\t(Offset 0x13C8) */\n\n#define BIT_SHIFT_HI4Q_TXBD_DESA_L 0\n#define BIT_MASK_HI4Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI4Q_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_HI4Q_TXBD_DESA_L) << BIT_SHIFT_HI4Q_TXBD_DESA_L)\n#define BITS_HI4Q_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_HI4Q_TXBD_DESA_L << BIT_SHIFT_HI4Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI4Q_TXBD_DESA_L(x) ((x) & (~BITS_HI4Q_TXBD_DESA_L))\n#define BIT_GET_HI4Q_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_L) & BIT_MASK_HI4Q_TXBD_DESA_L)\n#define BIT_SET_HI4Q_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_HI4Q_TXBD_DESA_L(x) | BIT_HI4Q_TXBD_DESA_L(v))\n\n/* 2 REG_HI4Q_TXBD_DESA_H\t\t\t(Offset 0x13CC) */\n\n#define BIT_SHIFT_HI4Q_TXBD_DESA_H 0\n#define BIT_MASK_HI4Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI4Q_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_HI4Q_TXBD_DESA_H) << BIT_SHIFT_HI4Q_TXBD_DESA_H)\n#define BITS_HI4Q_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_HI4Q_TXBD_DESA_H << BIT_SHIFT_HI4Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI4Q_TXBD_DESA_H(x) ((x) & (~BITS_HI4Q_TXBD_DESA_H))\n#define BIT_GET_HI4Q_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_H) & BIT_MASK_HI4Q_TXBD_DESA_H)\n#define BIT_SET_HI4Q_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_HI4Q_TXBD_DESA_H(x) | BIT_HI4Q_TXBD_DESA_H(v))\n\n/* 2 REG_HI5Q_TXBD_DESA_L\t\t\t(Offset 0x13D0) */\n\n#define BIT_SHIFT_HI5Q_TXBD_DESA_L 0\n#define BIT_MASK_HI5Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI5Q_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_HI5Q_TXBD_DESA_L) << BIT_SHIFT_HI5Q_TXBD_DESA_L)\n#define BITS_HI5Q_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_HI5Q_TXBD_DESA_L << BIT_SHIFT_HI5Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI5Q_TXBD_DESA_L(x) ((x) & (~BITS_HI5Q_TXBD_DESA_L))\n#define BIT_GET_HI5Q_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_L) & BIT_MASK_HI5Q_TXBD_DESA_L)\n#define BIT_SET_HI5Q_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_HI5Q_TXBD_DESA_L(x) | BIT_HI5Q_TXBD_DESA_L(v))\n\n/* 2 REG_HI5Q_TXBD_DESA_H\t\t\t(Offset 0x13D4) */\n\n#define BIT_SHIFT_HI5Q_TXBD_DESA_H 0\n#define BIT_MASK_HI5Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI5Q_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_HI5Q_TXBD_DESA_H) << BIT_SHIFT_HI5Q_TXBD_DESA_H)\n#define BITS_HI5Q_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_HI5Q_TXBD_DESA_H << BIT_SHIFT_HI5Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI5Q_TXBD_DESA_H(x) ((x) & (~BITS_HI5Q_TXBD_DESA_H))\n#define BIT_GET_HI5Q_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_H) & BIT_MASK_HI5Q_TXBD_DESA_H)\n#define BIT_SET_HI5Q_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_HI5Q_TXBD_DESA_H(x) | BIT_HI5Q_TXBD_DESA_H(v))\n\n/* 2 REG_HI6Q_TXBD_DESA_L\t\t\t(Offset 0x13D8) */\n\n#define BIT_SHIFT_HI6Q_TXBD_DESA_L 0\n#define BIT_MASK_HI6Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI6Q_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_HI6Q_TXBD_DESA_L) << BIT_SHIFT_HI6Q_TXBD_DESA_L)\n#define BITS_HI6Q_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_HI6Q_TXBD_DESA_L << BIT_SHIFT_HI6Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI6Q_TXBD_DESA_L(x) ((x) & (~BITS_HI6Q_TXBD_DESA_L))\n#define BIT_GET_HI6Q_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_L) & BIT_MASK_HI6Q_TXBD_DESA_L)\n#define BIT_SET_HI6Q_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_HI6Q_TXBD_DESA_L(x) | BIT_HI6Q_TXBD_DESA_L(v))\n\n/* 2 REG_HI6Q_TXBD_DESA_H\t\t\t(Offset 0x13DC) */\n\n#define BIT_SHIFT_HI6Q_TXBD_DESA_H 0\n#define BIT_MASK_HI6Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI6Q_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_HI6Q_TXBD_DESA_H) << BIT_SHIFT_HI6Q_TXBD_DESA_H)\n#define BITS_HI6Q_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_HI6Q_TXBD_DESA_H << BIT_SHIFT_HI6Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI6Q_TXBD_DESA_H(x) ((x) & (~BITS_HI6Q_TXBD_DESA_H))\n#define BIT_GET_HI6Q_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_H) & BIT_MASK_HI6Q_TXBD_DESA_H)\n#define BIT_SET_HI6Q_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_HI6Q_TXBD_DESA_H(x) | BIT_HI6Q_TXBD_DESA_H(v))\n\n/* 2 REG_HI7Q_TXBD_DESA_L\t\t\t(Offset 0x13E0) */\n\n#define BIT_SHIFT_HI7Q_TXBD_DESA_L 0\n#define BIT_MASK_HI7Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI7Q_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_HI7Q_TXBD_DESA_L) << BIT_SHIFT_HI7Q_TXBD_DESA_L)\n#define BITS_HI7Q_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_HI7Q_TXBD_DESA_L << BIT_SHIFT_HI7Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI7Q_TXBD_DESA_L(x) ((x) & (~BITS_HI7Q_TXBD_DESA_L))\n#define BIT_GET_HI7Q_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_L) & BIT_MASK_HI7Q_TXBD_DESA_L)\n#define BIT_SET_HI7Q_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_HI7Q_TXBD_DESA_L(x) | BIT_HI7Q_TXBD_DESA_L(v))\n\n/* 2 REG_HI7Q_TXBD_DESA_H\t\t\t(Offset 0x13E4) */\n\n#define BIT_SHIFT_HI7Q_TXBD_DESA_H 0\n#define BIT_MASK_HI7Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI7Q_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_HI7Q_TXBD_DESA_H) << BIT_SHIFT_HI7Q_TXBD_DESA_H)\n#define BITS_HI7Q_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_HI7Q_TXBD_DESA_H << BIT_SHIFT_HI7Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI7Q_TXBD_DESA_H(x) ((x) & (~BITS_HI7Q_TXBD_DESA_H))\n#define BIT_GET_HI7Q_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_H) & BIT_MASK_HI7Q_TXBD_DESA_H)\n#define BIT_SET_HI7Q_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_HI7Q_TXBD_DESA_H(x) | BIT_HI7Q_TXBD_DESA_H(v))\n\n/* 2 REG_ACH8_ACH9_TXBD_NUM\t\t\t(Offset 0x13E8) */\n\n#define BIT_PCIE_ACH9_FLAG BIT(30)\n\n#define BIT_SHIFT_ACH9_DESC_MODE 28\n#define BIT_MASK_ACH9_DESC_MODE 0x3\n#define BIT_ACH9_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_ACH9_DESC_MODE) << BIT_SHIFT_ACH9_DESC_MODE)\n#define BITS_ACH9_DESC_MODE                                                    \\\n\t(BIT_MASK_ACH9_DESC_MODE << BIT_SHIFT_ACH9_DESC_MODE)\n#define BIT_CLEAR_ACH9_DESC_MODE(x) ((x) & (~BITS_ACH9_DESC_MODE))\n#define BIT_GET_ACH9_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_ACH9_DESC_MODE) & BIT_MASK_ACH9_DESC_MODE)\n#define BIT_SET_ACH9_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_ACH9_DESC_MODE(x) | BIT_ACH9_DESC_MODE(v))\n\n#define BIT_SHIFT_ACH9_DESC_NUM 16\n#define BIT_MASK_ACH9_DESC_NUM 0xfff\n#define BIT_ACH9_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_ACH9_DESC_NUM) << BIT_SHIFT_ACH9_DESC_NUM)\n#define BITS_ACH9_DESC_NUM (BIT_MASK_ACH9_DESC_NUM << BIT_SHIFT_ACH9_DESC_NUM)\n#define BIT_CLEAR_ACH9_DESC_NUM(x) ((x) & (~BITS_ACH9_DESC_NUM))\n#define BIT_GET_ACH9_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH9_DESC_NUM) & BIT_MASK_ACH9_DESC_NUM)\n#define BIT_SET_ACH9_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_ACH9_DESC_NUM(x) | BIT_ACH9_DESC_NUM(v))\n\n#define BIT_PCIE_ACH8_FLAG BIT(14)\n\n#define BIT_SHIFT_ACH8_DESC_MODE 12\n#define BIT_MASK_ACH8_DESC_MODE 0x3\n#define BIT_ACH8_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_ACH8_DESC_MODE) << BIT_SHIFT_ACH8_DESC_MODE)\n#define BITS_ACH8_DESC_MODE                                                    \\\n\t(BIT_MASK_ACH8_DESC_MODE << BIT_SHIFT_ACH8_DESC_MODE)\n#define BIT_CLEAR_ACH8_DESC_MODE(x) ((x) & (~BITS_ACH8_DESC_MODE))\n#define BIT_GET_ACH8_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_ACH8_DESC_MODE) & BIT_MASK_ACH8_DESC_MODE)\n#define BIT_SET_ACH8_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_ACH8_DESC_MODE(x) | BIT_ACH8_DESC_MODE(v))\n\n#define BIT_SHIFT_ACH8_DESC_NUM 0\n#define BIT_MASK_ACH8_DESC_NUM 0xfff\n#define BIT_ACH8_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_ACH8_DESC_NUM) << BIT_SHIFT_ACH8_DESC_NUM)\n#define BITS_ACH8_DESC_NUM (BIT_MASK_ACH8_DESC_NUM << BIT_SHIFT_ACH8_DESC_NUM)\n#define BIT_CLEAR_ACH8_DESC_NUM(x) ((x) & (~BITS_ACH8_DESC_NUM))\n#define BIT_GET_ACH8_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH8_DESC_NUM) & BIT_MASK_ACH8_DESC_NUM)\n#define BIT_SET_ACH8_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_ACH8_DESC_NUM(x) | BIT_ACH8_DESC_NUM(v))\n\n/* 2 REG_ACH10_ACH11_TXBD_NUM\t\t(Offset 0x13EC) */\n\n#define BIT_PCIE_ACH11_FLAG BIT(30)\n\n#define BIT_SHIFT_ACH11_DESC_MODE 28\n#define BIT_MASK_ACH11_DESC_MODE 0x3\n#define BIT_ACH11_DESC_MODE(x)                                                 \\\n\t(((x) & BIT_MASK_ACH11_DESC_MODE) << BIT_SHIFT_ACH11_DESC_MODE)\n#define BITS_ACH11_DESC_MODE                                                   \\\n\t(BIT_MASK_ACH11_DESC_MODE << BIT_SHIFT_ACH11_DESC_MODE)\n#define BIT_CLEAR_ACH11_DESC_MODE(x) ((x) & (~BITS_ACH11_DESC_MODE))\n#define BIT_GET_ACH11_DESC_MODE(x)                                             \\\n\t(((x) >> BIT_SHIFT_ACH11_DESC_MODE) & BIT_MASK_ACH11_DESC_MODE)\n#define BIT_SET_ACH11_DESC_MODE(x, v)                                          \\\n\t(BIT_CLEAR_ACH11_DESC_MODE(x) | BIT_ACH11_DESC_MODE(v))\n\n#define BIT_SHIFT_ACH11_DESC_NUM 16\n#define BIT_MASK_ACH11_DESC_NUM 0xfff\n#define BIT_ACH11_DESC_NUM(x)                                                  \\\n\t(((x) & BIT_MASK_ACH11_DESC_NUM) << BIT_SHIFT_ACH11_DESC_NUM)\n#define BITS_ACH11_DESC_NUM                                                    \\\n\t(BIT_MASK_ACH11_DESC_NUM << BIT_SHIFT_ACH11_DESC_NUM)\n#define BIT_CLEAR_ACH11_DESC_NUM(x) ((x) & (~BITS_ACH11_DESC_NUM))\n#define BIT_GET_ACH11_DESC_NUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_ACH11_DESC_NUM) & BIT_MASK_ACH11_DESC_NUM)\n#define BIT_SET_ACH11_DESC_NUM(x, v)                                           \\\n\t(BIT_CLEAR_ACH11_DESC_NUM(x) | BIT_ACH11_DESC_NUM(v))\n\n#define BIT_PCIE_ACH10_FLAG BIT(14)\n\n#define BIT_SHIFT_ACH10_DESC_MODE 12\n#define BIT_MASK_ACH10_DESC_MODE 0x3\n#define BIT_ACH10_DESC_MODE(x)                                                 \\\n\t(((x) & BIT_MASK_ACH10_DESC_MODE) << BIT_SHIFT_ACH10_DESC_MODE)\n#define BITS_ACH10_DESC_MODE                                                   \\\n\t(BIT_MASK_ACH10_DESC_MODE << BIT_SHIFT_ACH10_DESC_MODE)\n#define BIT_CLEAR_ACH10_DESC_MODE(x) ((x) & (~BITS_ACH10_DESC_MODE))\n#define BIT_GET_ACH10_DESC_MODE(x)                                             \\\n\t(((x) >> BIT_SHIFT_ACH10_DESC_MODE) & BIT_MASK_ACH10_DESC_MODE)\n#define BIT_SET_ACH10_DESC_MODE(x, v)                                          \\\n\t(BIT_CLEAR_ACH10_DESC_MODE(x) | BIT_ACH10_DESC_MODE(v))\n\n#define BIT_SHIFT_ACH10_DESC_NUM 0\n#define BIT_MASK_ACH10_DESC_NUM 0xfff\n#define BIT_ACH10_DESC_NUM(x)                                                  \\\n\t(((x) & BIT_MASK_ACH10_DESC_NUM) << BIT_SHIFT_ACH10_DESC_NUM)\n#define BITS_ACH10_DESC_NUM                                                    \\\n\t(BIT_MASK_ACH10_DESC_NUM << BIT_SHIFT_ACH10_DESC_NUM)\n#define BIT_CLEAR_ACH10_DESC_NUM(x) ((x) & (~BITS_ACH10_DESC_NUM))\n#define BIT_GET_ACH10_DESC_NUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_ACH10_DESC_NUM) & BIT_MASK_ACH10_DESC_NUM)\n#define BIT_SET_ACH10_DESC_NUM(x, v)                                           \\\n\t(BIT_CLEAR_ACH10_DESC_NUM(x) | BIT_ACH10_DESC_NUM(v))\n\n/* 2 REG_ACH12_ACH13_TXBD_NUM\t\t(Offset 0x13F0) */\n\n#define BIT_PCIE_ACH13_FLAG BIT(30)\n\n#define BIT_SHIFT_ACH13_DESC_MODE 28\n#define BIT_MASK_ACH13_DESC_MODE 0x3\n#define BIT_ACH13_DESC_MODE(x)                                                 \\\n\t(((x) & BIT_MASK_ACH13_DESC_MODE) << BIT_SHIFT_ACH13_DESC_MODE)\n#define BITS_ACH13_DESC_MODE                                                   \\\n\t(BIT_MASK_ACH13_DESC_MODE << BIT_SHIFT_ACH13_DESC_MODE)\n#define BIT_CLEAR_ACH13_DESC_MODE(x) ((x) & (~BITS_ACH13_DESC_MODE))\n#define BIT_GET_ACH13_DESC_MODE(x)                                             \\\n\t(((x) >> BIT_SHIFT_ACH13_DESC_MODE) & BIT_MASK_ACH13_DESC_MODE)\n#define BIT_SET_ACH13_DESC_MODE(x, v)                                          \\\n\t(BIT_CLEAR_ACH13_DESC_MODE(x) | BIT_ACH13_DESC_MODE(v))\n\n#define BIT_SHIFT_ACH13_DESC_NUM 16\n#define BIT_MASK_ACH13_DESC_NUM 0xfff\n#define BIT_ACH13_DESC_NUM(x)                                                  \\\n\t(((x) & BIT_MASK_ACH13_DESC_NUM) << BIT_SHIFT_ACH13_DESC_NUM)\n#define BITS_ACH13_DESC_NUM                                                    \\\n\t(BIT_MASK_ACH13_DESC_NUM << BIT_SHIFT_ACH13_DESC_NUM)\n#define BIT_CLEAR_ACH13_DESC_NUM(x) ((x) & (~BITS_ACH13_DESC_NUM))\n#define BIT_GET_ACH13_DESC_NUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_ACH13_DESC_NUM) & BIT_MASK_ACH13_DESC_NUM)\n#define BIT_SET_ACH13_DESC_NUM(x, v)                                           \\\n\t(BIT_CLEAR_ACH13_DESC_NUM(x) | BIT_ACH13_DESC_NUM(v))\n\n#define BIT_PCIE_ACH12_FLAG BIT(14)\n\n#define BIT_SHIFT_ACH12_DESC_MODE 12\n#define BIT_MASK_ACH12_DESC_MODE 0x3\n#define BIT_ACH12_DESC_MODE(x)                                                 \\\n\t(((x) & BIT_MASK_ACH12_DESC_MODE) << BIT_SHIFT_ACH12_DESC_MODE)\n#define BITS_ACH12_DESC_MODE                                                   \\\n\t(BIT_MASK_ACH12_DESC_MODE << BIT_SHIFT_ACH12_DESC_MODE)\n#define BIT_CLEAR_ACH12_DESC_MODE(x) ((x) & (~BITS_ACH12_DESC_MODE))\n#define BIT_GET_ACH12_DESC_MODE(x)                                             \\\n\t(((x) >> BIT_SHIFT_ACH12_DESC_MODE) & BIT_MASK_ACH12_DESC_MODE)\n#define BIT_SET_ACH12_DESC_MODE(x, v)                                          \\\n\t(BIT_CLEAR_ACH12_DESC_MODE(x) | BIT_ACH12_DESC_MODE(v))\n\n#define BIT_SHIFT_ACH12_DESC_NUM 0\n#define BIT_MASK_ACH12_DESC_NUM 0xfff\n#define BIT_ACH12_DESC_NUM(x)                                                  \\\n\t(((x) & BIT_MASK_ACH12_DESC_NUM) << BIT_SHIFT_ACH12_DESC_NUM)\n#define BITS_ACH12_DESC_NUM                                                    \\\n\t(BIT_MASK_ACH12_DESC_NUM << BIT_SHIFT_ACH12_DESC_NUM)\n#define BIT_CLEAR_ACH12_DESC_NUM(x) ((x) & (~BITS_ACH12_DESC_NUM))\n#define BIT_GET_ACH12_DESC_NUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_ACH12_DESC_NUM) & BIT_MASK_ACH12_DESC_NUM)\n#define BIT_SET_ACH12_DESC_NUM(x, v)                                           \\\n\t(BIT_CLEAR_ACH12_DESC_NUM(x) | BIT_ACH12_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_OLD_DEHANG\t\t\t\t(Offset 0x13F4) */\n\n#define BIT_OLD_DEHANG BIT(1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_ACH4_TXBD_DESA_L\t\t\t(Offset 0x13F8) */\n\n#define BIT_SHIFT_ACH4_TXBD_DESA_L 0\n#define BIT_MASK_ACH4_TXBD_DESA_L 0xffffffffL\n#define BIT_ACH4_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_ACH4_TXBD_DESA_L) << BIT_SHIFT_ACH4_TXBD_DESA_L)\n#define BITS_ACH4_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_ACH4_TXBD_DESA_L << BIT_SHIFT_ACH4_TXBD_DESA_L)\n#define BIT_CLEAR_ACH4_TXBD_DESA_L(x) ((x) & (~BITS_ACH4_TXBD_DESA_L))\n#define BIT_GET_ACH4_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH4_TXBD_DESA_L) & BIT_MASK_ACH4_TXBD_DESA_L)\n#define BIT_SET_ACH4_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_ACH4_TXBD_DESA_L(x) | BIT_ACH4_TXBD_DESA_L(v))\n\n/* 2 REG_ACH4_TXBD_DESA_H\t\t\t(Offset 0x13FC) */\n\n#define BIT_SHIFT_ACH4_TXBD_DESA_H 0\n#define BIT_MASK_ACH4_TXBD_DESA_H 0xffffffffL\n#define BIT_ACH4_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_ACH4_TXBD_DESA_H) << BIT_SHIFT_ACH4_TXBD_DESA_H)\n#define BITS_ACH4_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_ACH4_TXBD_DESA_H << BIT_SHIFT_ACH4_TXBD_DESA_H)\n#define BIT_CLEAR_ACH4_TXBD_DESA_H(x) ((x) & (~BITS_ACH4_TXBD_DESA_H))\n#define BIT_GET_ACH4_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_ACH4_TXBD_DESA_H) & BIT_MASK_ACH4_TXBD_DESA_H)\n#define BIT_SET_ACH4_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_ACH4_TXBD_DESA_H(x) | BIT_ACH4_TXBD_DESA_H(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q0_Q1_INFO\t\t\t\t(Offset 0x1400) */\n\n#define BIT_SHIFT_AC1_PKT_INFO 16\n#define BIT_MASK_AC1_PKT_INFO 0xfff\n#define BIT_AC1_PKT_INFO(x)                                                    \\\n\t(((x) & BIT_MASK_AC1_PKT_INFO) << BIT_SHIFT_AC1_PKT_INFO)\n#define BITS_AC1_PKT_INFO (BIT_MASK_AC1_PKT_INFO << BIT_SHIFT_AC1_PKT_INFO)\n#define BIT_CLEAR_AC1_PKT_INFO(x) ((x) & (~BITS_AC1_PKT_INFO))\n#define BIT_GET_AC1_PKT_INFO(x)                                                \\\n\t(((x) >> BIT_SHIFT_AC1_PKT_INFO) & BIT_MASK_AC1_PKT_INFO)\n#define BIT_SET_AC1_PKT_INFO(x, v)                                             \\\n\t(BIT_CLEAR_AC1_PKT_INFO(x) | BIT_AC1_PKT_INFO(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MU_OFFSET\t\t\t\t(Offset 0x1400) */\n\n#define BIT_SHIFT_MU_RATETABLE_OFFSET 16\n#define BIT_MASK_MU_RATETABLE_OFFSET 0x1ff\n#define BIT_MU_RATETABLE_OFFSET(x)                                             \\\n\t(((x) & BIT_MASK_MU_RATETABLE_OFFSET) << BIT_SHIFT_MU_RATETABLE_OFFSET)\n#define BITS_MU_RATETABLE_OFFSET                                               \\\n\t(BIT_MASK_MU_RATETABLE_OFFSET << BIT_SHIFT_MU_RATETABLE_OFFSET)\n#define BIT_CLEAR_MU_RATETABLE_OFFSET(x) ((x) & (~BITS_MU_RATETABLE_OFFSET))\n#define BIT_GET_MU_RATETABLE_OFFSET(x)                                         \\\n\t(((x) >> BIT_SHIFT_MU_RATETABLE_OFFSET) & BIT_MASK_MU_RATETABLE_OFFSET)\n#define BIT_SET_MU_RATETABLE_OFFSET(x, v)                                      \\\n\t(BIT_CLEAR_MU_RATETABLE_OFFSET(x) | BIT_MU_RATETABLE_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q0_Q1_INFO\t\t\t\t(Offset 0x1400) */\n\n#define BIT_SHIFT_AC0_PKT_INFO 0\n#define BIT_MASK_AC0_PKT_INFO 0xfff\n#define BIT_AC0_PKT_INFO(x)                                                    \\\n\t(((x) & BIT_MASK_AC0_PKT_INFO) << BIT_SHIFT_AC0_PKT_INFO)\n#define BITS_AC0_PKT_INFO (BIT_MASK_AC0_PKT_INFO << BIT_SHIFT_AC0_PKT_INFO)\n#define BIT_CLEAR_AC0_PKT_INFO(x) ((x) & (~BITS_AC0_PKT_INFO))\n#define BIT_GET_AC0_PKT_INFO(x)                                                \\\n\t(((x) >> BIT_SHIFT_AC0_PKT_INFO) & BIT_MASK_AC0_PKT_INFO)\n#define BIT_SET_AC0_PKT_INFO(x, v)                                             \\\n\t(BIT_CLEAR_AC0_PKT_INFO(x) | BIT_AC0_PKT_INFO(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_ARFR6\t\t\t\t(Offset 0x1400) */\n\n#define BIT_SHIFT_ARFRL6 0\n#define BIT_MASK_ARFRL6 0xffffffffL\n#define BIT_ARFRL6(x) (((x) & BIT_MASK_ARFRL6) << BIT_SHIFT_ARFRL6)\n#define BITS_ARFRL6 (BIT_MASK_ARFRL6 << BIT_SHIFT_ARFRL6)\n#define BIT_CLEAR_ARFRL6(x) ((x) & (~BITS_ARFRL6))\n#define BIT_GET_ARFRL6(x) (((x) >> BIT_SHIFT_ARFRL6) & BIT_MASK_ARFRL6)\n#define BIT_SET_ARFRL6(x, v) (BIT_CLEAR_ARFRL6(x) | BIT_ARFRL6(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_ARFR6\t\t\t\t(Offset 0x1400) */\n\n#define BIT_SHIFT_ARFR6_V1 0\n#define BIT_MASK_ARFR6_V1 0xffffffffffffffffL\n#define BIT_ARFR6_V1(x) (((x) & BIT_MASK_ARFR6_V1) << BIT_SHIFT_ARFR6_V1)\n#define BITS_ARFR6_V1 (BIT_MASK_ARFR6_V1 << BIT_SHIFT_ARFR6_V1)\n#define BIT_CLEAR_ARFR6_V1(x) ((x) & (~BITS_ARFR6_V1))\n#define BIT_GET_ARFR6_V1(x) (((x) >> BIT_SHIFT_ARFR6_V1) & BIT_MASK_ARFR6_V1)\n#define BIT_SET_ARFR6_V1(x, v) (BIT_CLEAR_ARFR6_V1(x) | BIT_ARFR6_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MU_OFFSET\t\t\t\t(Offset 0x1400) */\n\n#define BIT_SHIFT_MU_SCORETABLE_OFFSET 0\n#define BIT_MASK_MU_SCORETABLE_OFFSET 0x1ff\n#define BIT_MU_SCORETABLE_OFFSET(x)                                            \\\n\t(((x) & BIT_MASK_MU_SCORETABLE_OFFSET)                                 \\\n\t << BIT_SHIFT_MU_SCORETABLE_OFFSET)\n#define BITS_MU_SCORETABLE_OFFSET                                              \\\n\t(BIT_MASK_MU_SCORETABLE_OFFSET << BIT_SHIFT_MU_SCORETABLE_OFFSET)\n#define BIT_CLEAR_MU_SCORETABLE_OFFSET(x) ((x) & (~BITS_MU_SCORETABLE_OFFSET))\n#define BIT_GET_MU_SCORETABLE_OFFSET(x)                                        \\\n\t(((x) >> BIT_SHIFT_MU_SCORETABLE_OFFSET) &                             \\\n\t BIT_MASK_MU_SCORETABLE_OFFSET)\n#define BIT_SET_MU_SCORETABLE_OFFSET(x, v)                                     \\\n\t(BIT_CLEAR_MU_SCORETABLE_OFFSET(x) | BIT_MU_SCORETABLE_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q2_Q3_INFO\t\t\t\t(Offset 0x1404) */\n\n#define BIT_SHIFT_AC3_PKT_INFO 16\n#define BIT_MASK_AC3_PKT_INFO 0xfff\n#define BIT_AC3_PKT_INFO(x)                                                    \\\n\t(((x) & BIT_MASK_AC3_PKT_INFO) << BIT_SHIFT_AC3_PKT_INFO)\n#define BITS_AC3_PKT_INFO (BIT_MASK_AC3_PKT_INFO << BIT_SHIFT_AC3_PKT_INFO)\n#define BIT_CLEAR_AC3_PKT_INFO(x) ((x) & (~BITS_AC3_PKT_INFO))\n#define BIT_GET_AC3_PKT_INFO(x)                                                \\\n\t(((x) >> BIT_SHIFT_AC3_PKT_INFO) & BIT_MASK_AC3_PKT_INFO)\n#define BIT_SET_AC3_PKT_INFO(x, v)                                             \\\n\t(BIT_CLEAR_AC3_PKT_INFO(x) | BIT_AC3_PKT_INFO(v))\n\n#define BIT_SHIFT_AC2_PKT_INFO 0\n#define BIT_MASK_AC2_PKT_INFO 0xfff\n#define BIT_AC2_PKT_INFO(x)                                                    \\\n\t(((x) & BIT_MASK_AC2_PKT_INFO) << BIT_SHIFT_AC2_PKT_INFO)\n#define BITS_AC2_PKT_INFO (BIT_MASK_AC2_PKT_INFO << BIT_SHIFT_AC2_PKT_INFO)\n#define BIT_CLEAR_AC2_PKT_INFO(x) ((x) & (~BITS_AC2_PKT_INFO))\n#define BIT_GET_AC2_PKT_INFO(x)                                                \\\n\t(((x) >> BIT_SHIFT_AC2_PKT_INFO) & BIT_MASK_AC2_PKT_INFO)\n#define BIT_SET_AC2_PKT_INFO(x, v)                                             \\\n\t(BIT_CLEAR_AC2_PKT_INFO(x) | BIT_AC2_PKT_INFO(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_ARFRH6\t\t\t\t(Offset 0x1404) */\n\n#define BIT_SHIFT_ARFRH6 0\n#define BIT_MASK_ARFRH6 0xffffffffL\n#define BIT_ARFRH6(x) (((x) & BIT_MASK_ARFRH6) << BIT_SHIFT_ARFRH6)\n#define BITS_ARFRH6 (BIT_MASK_ARFRH6 << BIT_SHIFT_ARFRH6)\n#define BIT_CLEAR_ARFRH6(x) ((x) & (~BITS_ARFRH6))\n#define BIT_GET_ARFRH6(x) (((x) >> BIT_SHIFT_ARFRH6) & BIT_MASK_ARFRH6)\n#define BIT_SET_ARFRH6(x, v) (BIT_CLEAR_ARFRH6(x) | BIT_ARFRH6(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q4_Q5_INFO\t\t\t\t(Offset 0x1408) */\n\n#define BIT_SHIFT_AC5_PKT_INFO 16\n#define BIT_MASK_AC5_PKT_INFO 0xfff\n#define BIT_AC5_PKT_INFO(x)                                                    \\\n\t(((x) & BIT_MASK_AC5_PKT_INFO) << BIT_SHIFT_AC5_PKT_INFO)\n#define BITS_AC5_PKT_INFO (BIT_MASK_AC5_PKT_INFO << BIT_SHIFT_AC5_PKT_INFO)\n#define BIT_CLEAR_AC5_PKT_INFO(x) ((x) & (~BITS_AC5_PKT_INFO))\n#define BIT_GET_AC5_PKT_INFO(x)                                                \\\n\t(((x) >> BIT_SHIFT_AC5_PKT_INFO) & BIT_MASK_AC5_PKT_INFO)\n#define BIT_SET_AC5_PKT_INFO(x, v)                                             \\\n\t(BIT_CLEAR_AC5_PKT_INFO(x) | BIT_AC5_PKT_INFO(v))\n\n#define BIT_SHIFT_AC4_PKT_INFO 0\n#define BIT_MASK_AC4_PKT_INFO 0xfff\n#define BIT_AC4_PKT_INFO(x)                                                    \\\n\t(((x) & BIT_MASK_AC4_PKT_INFO) << BIT_SHIFT_AC4_PKT_INFO)\n#define BITS_AC4_PKT_INFO (BIT_MASK_AC4_PKT_INFO << BIT_SHIFT_AC4_PKT_INFO)\n#define BIT_CLEAR_AC4_PKT_INFO(x) ((x) & (~BITS_AC4_PKT_INFO))\n#define BIT_GET_AC4_PKT_INFO(x)                                                \\\n\t(((x) >> BIT_SHIFT_AC4_PKT_INFO) & BIT_MASK_AC4_PKT_INFO)\n#define BIT_SET_AC4_PKT_INFO(x, v)                                             \\\n\t(BIT_CLEAR_AC4_PKT_INFO(x) | BIT_AC4_PKT_INFO(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_ARFR7\t\t\t\t(Offset 0x1408) */\n\n#define BIT_SHIFT_ARFRL7 0\n#define BIT_MASK_ARFRL7 0xffffffffL\n#define BIT_ARFRL7(x) (((x) & BIT_MASK_ARFRL7) << BIT_SHIFT_ARFRL7)\n#define BITS_ARFRL7 (BIT_MASK_ARFRL7 << BIT_SHIFT_ARFRL7)\n#define BIT_CLEAR_ARFRL7(x) ((x) & (~BITS_ARFRL7))\n#define BIT_GET_ARFRL7(x) (((x) >> BIT_SHIFT_ARFRL7) & BIT_MASK_ARFRL7)\n#define BIT_SET_ARFRL7(x, v) (BIT_CLEAR_ARFRL7(x) | BIT_ARFRL7(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_ARFR7\t\t\t\t(Offset 0x1408) */\n\n#define BIT_SHIFT_ARFR7_V1 0\n#define BIT_MASK_ARFR7_V1 0xffffffffffffffffL\n#define BIT_ARFR7_V1(x) (((x) & BIT_MASK_ARFR7_V1) << BIT_SHIFT_ARFR7_V1)\n#define BITS_ARFR7_V1 (BIT_MASK_ARFR7_V1 << BIT_SHIFT_ARFR7_V1)\n#define BIT_CLEAR_ARFR7_V1(x) ((x) & (~BITS_ARFR7_V1))\n#define BIT_GET_ARFR7_V1(x) (((x) >> BIT_SHIFT_ARFR7_V1) & BIT_MASK_ARFR7_V1)\n#define BIT_SET_ARFR7_V1(x, v) (BIT_CLEAR_ARFR7_V1(x) | BIT_ARFR7_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_Q6_Q7_INFO\t\t\t\t(Offset 0x140C) */\n\n#define BIT_SHIFT_AC7_PKT_INFO 16\n#define BIT_MASK_AC7_PKT_INFO 0xfff\n#define BIT_AC7_PKT_INFO(x)                                                    \\\n\t(((x) & BIT_MASK_AC7_PKT_INFO) << BIT_SHIFT_AC7_PKT_INFO)\n#define BITS_AC7_PKT_INFO (BIT_MASK_AC7_PKT_INFO << BIT_SHIFT_AC7_PKT_INFO)\n#define BIT_CLEAR_AC7_PKT_INFO(x) ((x) & (~BITS_AC7_PKT_INFO))\n#define BIT_GET_AC7_PKT_INFO(x)                                                \\\n\t(((x) >> BIT_SHIFT_AC7_PKT_INFO) & BIT_MASK_AC7_PKT_INFO)\n#define BIT_SET_AC7_PKT_INFO(x, v)                                             \\\n\t(BIT_CLEAR_AC7_PKT_INFO(x) | BIT_AC7_PKT_INFO(v))\n\n#define BIT_SHIFT_AC6_PKT_INFO 0\n#define BIT_MASK_AC6_PKT_INFO 0xfff\n#define BIT_AC6_PKT_INFO(x)                                                    \\\n\t(((x) & BIT_MASK_AC6_PKT_INFO) << BIT_SHIFT_AC6_PKT_INFO)\n#define BITS_AC6_PKT_INFO (BIT_MASK_AC6_PKT_INFO << BIT_SHIFT_AC6_PKT_INFO)\n#define BIT_CLEAR_AC6_PKT_INFO(x) ((x) & (~BITS_AC6_PKT_INFO))\n#define BIT_GET_AC6_PKT_INFO(x)                                                \\\n\t(((x) >> BIT_SHIFT_AC6_PKT_INFO) & BIT_MASK_AC6_PKT_INFO)\n#define BIT_SET_AC6_PKT_INFO(x, v)                                             \\\n\t(BIT_CLEAR_AC6_PKT_INFO(x) | BIT_AC6_PKT_INFO(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_ARFRH7\t\t\t\t(Offset 0x140C) */\n\n#define BIT_SHIFT_ARFRH7 0\n#define BIT_MASK_ARFRH7 0xffffffffL\n#define BIT_ARFRH7(x) (((x) & BIT_MASK_ARFRH7) << BIT_SHIFT_ARFRH7)\n#define BITS_ARFRH7 (BIT_MASK_ARFRH7 << BIT_SHIFT_ARFRH7)\n#define BIT_CLEAR_ARFRH7(x) ((x) & (~BITS_ARFRH7))\n#define BIT_GET_ARFRH7(x) (((x) >> BIT_SHIFT_ARFRH7) & BIT_MASK_ARFRH7)\n#define BIT_SET_ARFRH7(x, v) (BIT_CLEAR_ARFRH7(x) | BIT_ARFRH7(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MGQ_HIQ_INFO\t\t\t(Offset 0x1410) */\n\n#define BIT_SHIFT_HIQ_PKT_INFO 16\n#define BIT_MASK_HIQ_PKT_INFO 0xfff\n#define BIT_HIQ_PKT_INFO(x)                                                    \\\n\t(((x) & BIT_MASK_HIQ_PKT_INFO) << BIT_SHIFT_HIQ_PKT_INFO)\n#define BITS_HIQ_PKT_INFO (BIT_MASK_HIQ_PKT_INFO << BIT_SHIFT_HIQ_PKT_INFO)\n#define BIT_CLEAR_HIQ_PKT_INFO(x) ((x) & (~BITS_HIQ_PKT_INFO))\n#define BIT_GET_HIQ_PKT_INFO(x)                                                \\\n\t(((x) >> BIT_SHIFT_HIQ_PKT_INFO) & BIT_MASK_HIQ_PKT_INFO)\n#define BIT_SET_HIQ_PKT_INFO(x, v)                                             \\\n\t(BIT_CLEAR_HIQ_PKT_INFO(x) | BIT_HIQ_PKT_INFO(v))\n\n#define BIT_SHIFT_MGQ_PKT_INFO 0\n#define BIT_MASK_MGQ_PKT_INFO 0xfff\n#define BIT_MGQ_PKT_INFO(x)                                                    \\\n\t(((x) & BIT_MASK_MGQ_PKT_INFO) << BIT_SHIFT_MGQ_PKT_INFO)\n#define BITS_MGQ_PKT_INFO (BIT_MASK_MGQ_PKT_INFO << BIT_SHIFT_MGQ_PKT_INFO)\n#define BIT_CLEAR_MGQ_PKT_INFO(x) ((x) & (~BITS_MGQ_PKT_INFO))\n#define BIT_GET_MGQ_PKT_INFO(x)                                                \\\n\t(((x) >> BIT_SHIFT_MGQ_PKT_INFO) & BIT_MASK_MGQ_PKT_INFO)\n#define BIT_SET_MGQ_PKT_INFO(x, v)                                             \\\n\t(BIT_CLEAR_MGQ_PKT_INFO(x) | BIT_MGQ_PKT_INFO(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_ARFR8\t\t\t\t(Offset 0x1410) */\n\n#define BIT_SHIFT_ARFRL8 0\n#define BIT_MASK_ARFRL8 0xffffffffL\n#define BIT_ARFRL8(x) (((x) & BIT_MASK_ARFRL8) << BIT_SHIFT_ARFRL8)\n#define BITS_ARFRL8 (BIT_MASK_ARFRL8 << BIT_SHIFT_ARFRL8)\n#define BIT_CLEAR_ARFRL8(x) ((x) & (~BITS_ARFRL8))\n#define BIT_GET_ARFRL8(x) (((x) >> BIT_SHIFT_ARFRL8) & BIT_MASK_ARFRL8)\n#define BIT_SET_ARFRL8(x, v) (BIT_CLEAR_ARFRL8(x) | BIT_ARFRL8(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_ARFR8\t\t\t\t(Offset 0x1410) */\n\n#define BIT_SHIFT_ARFR8_V1 0\n#define BIT_MASK_ARFR8_V1 0xffffffffffffffffL\n#define BIT_ARFR8_V1(x) (((x) & BIT_MASK_ARFR8_V1) << BIT_SHIFT_ARFR8_V1)\n#define BITS_ARFR8_V1 (BIT_MASK_ARFR8_V1 << BIT_SHIFT_ARFR8_V1)\n#define BIT_CLEAR_ARFR8_V1(x) ((x) & (~BITS_ARFR8_V1))\n#define BIT_GET_ARFR8_V1(x) (((x) >> BIT_SHIFT_ARFR8_V1) & BIT_MASK_ARFR8_V1)\n#define BIT_SET_ARFR8_V1(x, v) (BIT_CLEAR_ARFR8_V1(x) | BIT_ARFR8_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_CMDQ_BCNQ_INFO\t\t\t(Offset 0x1414) */\n\n#define BIT_SHIFT_BCNQ_PKT_INFO_V1 16\n#define BIT_MASK_BCNQ_PKT_INFO_V1 0xfff\n#define BIT_BCNQ_PKT_INFO_V1(x)                                                \\\n\t(((x) & BIT_MASK_BCNQ_PKT_INFO_V1) << BIT_SHIFT_BCNQ_PKT_INFO_V1)\n#define BITS_BCNQ_PKT_INFO_V1                                                  \\\n\t(BIT_MASK_BCNQ_PKT_INFO_V1 << BIT_SHIFT_BCNQ_PKT_INFO_V1)\n#define BIT_CLEAR_BCNQ_PKT_INFO_V1(x) ((x) & (~BITS_BCNQ_PKT_INFO_V1))\n#define BIT_GET_BCNQ_PKT_INFO_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_BCNQ_PKT_INFO_V1) & BIT_MASK_BCNQ_PKT_INFO_V1)\n#define BIT_SET_BCNQ_PKT_INFO_V1(x, v)                                         \\\n\t(BIT_CLEAR_BCNQ_PKT_INFO_V1(x) | BIT_BCNQ_PKT_INFO_V1(v))\n\n#define BIT_SHIFT_BCNERR_PORT_SEL 16\n#define BIT_MASK_BCNERR_PORT_SEL 0x7\n#define BIT_BCNERR_PORT_SEL(x)                                                 \\\n\t(((x) & BIT_MASK_BCNERR_PORT_SEL) << BIT_SHIFT_BCNERR_PORT_SEL)\n#define BITS_BCNERR_PORT_SEL                                                   \\\n\t(BIT_MASK_BCNERR_PORT_SEL << BIT_SHIFT_BCNERR_PORT_SEL)\n#define BIT_CLEAR_BCNERR_PORT_SEL(x) ((x) & (~BITS_BCNERR_PORT_SEL))\n#define BIT_GET_BCNERR_PORT_SEL(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNERR_PORT_SEL) & BIT_MASK_BCNERR_PORT_SEL)\n#define BIT_SET_BCNERR_PORT_SEL(x, v)                                          \\\n\t(BIT_CLEAR_BCNERR_PORT_SEL(x) | BIT_BCNERR_PORT_SEL(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CMDQ_BCNQ_INFO\t\t\t(Offset 0x1414) */\n\n#define BIT_SHIFT_CMDQ_PKT_INFO 16\n#define BIT_MASK_CMDQ_PKT_INFO 0xfff\n#define BIT_CMDQ_PKT_INFO(x)                                                   \\\n\t(((x) & BIT_MASK_CMDQ_PKT_INFO) << BIT_SHIFT_CMDQ_PKT_INFO)\n#define BITS_CMDQ_PKT_INFO (BIT_MASK_CMDQ_PKT_INFO << BIT_SHIFT_CMDQ_PKT_INFO)\n#define BIT_CLEAR_CMDQ_PKT_INFO(x) ((x) & (~BITS_CMDQ_PKT_INFO))\n#define BIT_GET_CMDQ_PKT_INFO(x)                                               \\\n\t(((x) >> BIT_SHIFT_CMDQ_PKT_INFO) & BIT_MASK_CMDQ_PKT_INFO)\n#define BIT_SET_CMDQ_PKT_INFO(x, v)                                            \\\n\t(BIT_CLEAR_CMDQ_PKT_INFO(x) | BIT_CMDQ_PKT_INFO(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/* 2 REG_CMDQ_BCNQ_INFO\t\t\t(Offset 0x1414) */\n\n#define BIT_SHIFT_CMDQ_PKT_INFO_V1 0\n#define BIT_MASK_CMDQ_PKT_INFO_V1 0xfff\n#define BIT_CMDQ_PKT_INFO_V1(x)                                                \\\n\t(((x) & BIT_MASK_CMDQ_PKT_INFO_V1) << BIT_SHIFT_CMDQ_PKT_INFO_V1)\n#define BITS_CMDQ_PKT_INFO_V1                                                  \\\n\t(BIT_MASK_CMDQ_PKT_INFO_V1 << BIT_SHIFT_CMDQ_PKT_INFO_V1)\n#define BIT_CLEAR_CMDQ_PKT_INFO_V1(x) ((x) & (~BITS_CMDQ_PKT_INFO_V1))\n#define BIT_GET_CMDQ_PKT_INFO_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_CMDQ_PKT_INFO_V1) & BIT_MASK_CMDQ_PKT_INFO_V1)\n#define BIT_SET_CMDQ_PKT_INFO_V1(x, v)                                         \\\n\t(BIT_CLEAR_CMDQ_PKT_INFO_V1(x) | BIT_CMDQ_PKT_INFO_V1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_ARFRH8\t\t\t\t(Offset 0x1414) */\n\n#define BIT_SHIFT_ARFRH8 0\n#define BIT_MASK_ARFRH8 0xffffffffL\n#define BIT_ARFRH8(x) (((x) & BIT_MASK_ARFRH8) << BIT_SHIFT_ARFRH8)\n#define BITS_ARFRH8 (BIT_MASK_ARFRH8 << BIT_SHIFT_ARFRH8)\n#define BIT_CLEAR_ARFRH8(x) ((x) & (~BITS_ARFRH8))\n#define BIT_GET_ARFRH8(x) (((x) >> BIT_SHIFT_ARFRH8) & BIT_MASK_ARFRH8)\n#define BIT_SET_ARFRH8(x, v) (BIT_CLEAR_ARFRH8(x) | BIT_ARFRH8(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CMDQ_BCNQ_INFO\t\t\t(Offset 0x1414) */\n\n#define BIT_SHIFT_BCNQ_PKT_INFO 0\n#define BIT_MASK_BCNQ_PKT_INFO 0xfff\n#define BIT_BCNQ_PKT_INFO(x)                                                   \\\n\t(((x) & BIT_MASK_BCNQ_PKT_INFO) << BIT_SHIFT_BCNQ_PKT_INFO)\n#define BITS_BCNQ_PKT_INFO (BIT_MASK_BCNQ_PKT_INFO << BIT_SHIFT_BCNQ_PKT_INFO)\n#define BIT_CLEAR_BCNQ_PKT_INFO(x) ((x) & (~BITS_BCNQ_PKT_INFO))\n#define BIT_GET_BCNQ_PKT_INFO(x)                                               \\\n\t(((x) >> BIT_SHIFT_BCNQ_PKT_INFO) & BIT_MASK_BCNQ_PKT_INFO)\n#define BIT_SET_BCNQ_PKT_INFO(x, v)                                            \\\n\t(BIT_CLEAR_BCNQ_PKT_INFO(x) | BIT_BCNQ_PKT_INFO(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_LOOPBACK_OPTION\t\t\t(Offset 0x1420) */\n\n#define BIT_LOOPACK_FAST_EDCA_EN BIT(24)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_USEREG_SETTING\t\t\t(Offset 0x1420) */\n\n#define BIT_NDPA_USEREG BIT(21)\n\n#define BIT_SHIFT_RETRY_USEREG 19\n#define BIT_MASK_RETRY_USEREG 0x3\n#define BIT_RETRY_USEREG(x)                                                    \\\n\t(((x) & BIT_MASK_RETRY_USEREG) << BIT_SHIFT_RETRY_USEREG)\n#define BITS_RETRY_USEREG (BIT_MASK_RETRY_USEREG << BIT_SHIFT_RETRY_USEREG)\n#define BIT_CLEAR_RETRY_USEREG(x) ((x) & (~BITS_RETRY_USEREG))\n#define BIT_GET_RETRY_USEREG(x)                                                \\\n\t(((x) >> BIT_SHIFT_RETRY_USEREG) & BIT_MASK_RETRY_USEREG)\n#define BIT_SET_RETRY_USEREG(x, v)                                             \\\n\t(BIT_CLEAR_RETRY_USEREG(x) | BIT_RETRY_USEREG(v))\n\n#define BIT_SHIFT_TRYPKT_USEREG 17\n#define BIT_MASK_TRYPKT_USEREG 0x3\n#define BIT_TRYPKT_USEREG(x)                                                   \\\n\t(((x) & BIT_MASK_TRYPKT_USEREG) << BIT_SHIFT_TRYPKT_USEREG)\n#define BITS_TRYPKT_USEREG (BIT_MASK_TRYPKT_USEREG << BIT_SHIFT_TRYPKT_USEREG)\n#define BIT_CLEAR_TRYPKT_USEREG(x) ((x) & (~BITS_TRYPKT_USEREG))\n#define BIT_GET_TRYPKT_USEREG(x)                                               \\\n\t(((x) >> BIT_SHIFT_TRYPKT_USEREG) & BIT_MASK_TRYPKT_USEREG)\n#define BIT_SET_TRYPKT_USEREG(x, v)                                            \\\n\t(BIT_CLEAR_TRYPKT_USEREG(x) | BIT_TRYPKT_USEREG(v))\n\n#define BIT_CTLPKT_USEREG BIT(16)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_AESIV_SETTING\t\t\t(Offset 0x1424) */\n\n#define BIT_SHIFT_AESIV_OFFSET 0\n#define BIT_MASK_AESIV_OFFSET 0xfff\n#define BIT_AESIV_OFFSET(x)                                                    \\\n\t(((x) & BIT_MASK_AESIV_OFFSET) << BIT_SHIFT_AESIV_OFFSET)\n#define BITS_AESIV_OFFSET (BIT_MASK_AESIV_OFFSET << BIT_SHIFT_AESIV_OFFSET)\n#define BIT_CLEAR_AESIV_OFFSET(x) ((x) & (~BITS_AESIV_OFFSET))\n#define BIT_GET_AESIV_OFFSET(x)                                                \\\n\t(((x) >> BIT_SHIFT_AESIV_OFFSET) & BIT_MASK_AESIV_OFFSET)\n#define BIT_SET_AESIV_OFFSET(x, v)                                             \\\n\t(BIT_CLEAR_AESIV_OFFSET(x) | BIT_AESIV_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BF0_TIME_SETTING\t\t\t(Offset 0x1428) */\n\n#define BIT_BF0_TIMER_SET BIT(31)\n#define BIT_BF0_TIMER_CLR BIT(30)\n#define BIT_BF0_UPDATE_EN BIT(29)\n#define BIT_BF0_TIMER_EN BIT(28)\n\n#define BIT_SHIFT_BF0_PRETIME_OVER 16\n#define BIT_MASK_BF0_PRETIME_OVER 0xfff\n#define BIT_BF0_PRETIME_OVER(x)                                                \\\n\t(((x) & BIT_MASK_BF0_PRETIME_OVER) << BIT_SHIFT_BF0_PRETIME_OVER)\n#define BITS_BF0_PRETIME_OVER                                                  \\\n\t(BIT_MASK_BF0_PRETIME_OVER << BIT_SHIFT_BF0_PRETIME_OVER)\n#define BIT_CLEAR_BF0_PRETIME_OVER(x) ((x) & (~BITS_BF0_PRETIME_OVER))\n#define BIT_GET_BF0_PRETIME_OVER(x)                                            \\\n\t(((x) >> BIT_SHIFT_BF0_PRETIME_OVER) & BIT_MASK_BF0_PRETIME_OVER)\n#define BIT_SET_BF0_PRETIME_OVER(x, v)                                         \\\n\t(BIT_CLEAR_BF0_PRETIME_OVER(x) | BIT_BF0_PRETIME_OVER(v))\n\n#define BIT_SHIFT_BF0_LIFETIME 0\n#define BIT_MASK_BF0_LIFETIME 0xffff\n#define BIT_BF0_LIFETIME(x)                                                    \\\n\t(((x) & BIT_MASK_BF0_LIFETIME) << BIT_SHIFT_BF0_LIFETIME)\n#define BITS_BF0_LIFETIME (BIT_MASK_BF0_LIFETIME << BIT_SHIFT_BF0_LIFETIME)\n#define BIT_CLEAR_BF0_LIFETIME(x) ((x) & (~BITS_BF0_LIFETIME))\n#define BIT_GET_BF0_LIFETIME(x)                                                \\\n\t(((x) >> BIT_SHIFT_BF0_LIFETIME) & BIT_MASK_BF0_LIFETIME)\n#define BIT_SET_BF0_LIFETIME(x, v)                                             \\\n\t(BIT_CLEAR_BF0_LIFETIME(x) | BIT_BF0_LIFETIME(v))\n\n/* 2 REG_BF1_TIME_SETTING\t\t\t(Offset 0x142C) */\n\n#define BIT_BF1_TIMER_SET BIT(31)\n#define BIT_BF1_TIMER_CLR BIT(30)\n#define BIT_BF1_UPDATE_EN BIT(29)\n#define BIT_BF1_TIMER_EN BIT(28)\n\n#define BIT_SHIFT_BF1_PRETIME_OVER 16\n#define BIT_MASK_BF1_PRETIME_OVER 0xfff\n#define BIT_BF1_PRETIME_OVER(x)                                                \\\n\t(((x) & BIT_MASK_BF1_PRETIME_OVER) << BIT_SHIFT_BF1_PRETIME_OVER)\n#define BITS_BF1_PRETIME_OVER                                                  \\\n\t(BIT_MASK_BF1_PRETIME_OVER << BIT_SHIFT_BF1_PRETIME_OVER)\n#define BIT_CLEAR_BF1_PRETIME_OVER(x) ((x) & (~BITS_BF1_PRETIME_OVER))\n#define BIT_GET_BF1_PRETIME_OVER(x)                                            \\\n\t(((x) >> BIT_SHIFT_BF1_PRETIME_OVER) & BIT_MASK_BF1_PRETIME_OVER)\n#define BIT_SET_BF1_PRETIME_OVER(x, v)                                         \\\n\t(BIT_CLEAR_BF1_PRETIME_OVER(x) | BIT_BF1_PRETIME_OVER(v))\n\n#define BIT_SHIFT_BF1_LIFETIME 0\n#define BIT_MASK_BF1_LIFETIME 0xffff\n#define BIT_BF1_LIFETIME(x)                                                    \\\n\t(((x) & BIT_MASK_BF1_LIFETIME) << BIT_SHIFT_BF1_LIFETIME)\n#define BITS_BF1_LIFETIME (BIT_MASK_BF1_LIFETIME << BIT_SHIFT_BF1_LIFETIME)\n#define BIT_CLEAR_BF1_LIFETIME(x) ((x) & (~BITS_BF1_LIFETIME))\n#define BIT_GET_BF1_LIFETIME(x)                                                \\\n\t(((x) >> BIT_SHIFT_BF1_LIFETIME) & BIT_MASK_BF1_LIFETIME)\n#define BIT_SET_BF1_LIFETIME(x, v)                                             \\\n\t(BIT_CLEAR_BF1_LIFETIME(x) | BIT_BF1_LIFETIME(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BF_TIMEOUT_EN\t\t\t(Offset 0x1430) */\n\n#define BIT_EN_VHT_LDPC BIT(9)\n#define BIT_EN_HT_LDPC BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BF_TIMEOUT_EN\t\t\t(Offset 0x1430) */\n\n#define BIT_BF1_TIMEOUT_EN BIT(1)\n#define BIT_BF0_TIMEOUT_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MACID_RELEASE0\t\t\t(Offset 0x1434) */\n\n#define BIT_SHIFT_MACID31_0_RELEASE 0\n#define BIT_MASK_MACID31_0_RELEASE 0xffffffffL\n#define BIT_MACID31_0_RELEASE(x)                                               \\\n\t(((x) & BIT_MASK_MACID31_0_RELEASE) << BIT_SHIFT_MACID31_0_RELEASE)\n#define BITS_MACID31_0_RELEASE                                                 \\\n\t(BIT_MASK_MACID31_0_RELEASE << BIT_SHIFT_MACID31_0_RELEASE)\n#define BIT_CLEAR_MACID31_0_RELEASE(x) ((x) & (~BITS_MACID31_0_RELEASE))\n#define BIT_GET_MACID31_0_RELEASE(x)                                           \\\n\t(((x) >> BIT_SHIFT_MACID31_0_RELEASE) & BIT_MASK_MACID31_0_RELEASE)\n#define BIT_SET_MACID31_0_RELEASE(x, v)                                        \\\n\t(BIT_CLEAR_MACID31_0_RELEASE(x) | BIT_MACID31_0_RELEASE(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MACID_RELEASE_INFO\t\t\t(Offset 0x1434) */\n\n#define BIT_SHIFT_MACID_RELEASE_INFO 0\n#define BIT_MASK_MACID_RELEASE_INFO 0xffffffffL\n#define BIT_MACID_RELEASE_INFO(x)                                              \\\n\t(((x) & BIT_MASK_MACID_RELEASE_INFO) << BIT_SHIFT_MACID_RELEASE_INFO)\n#define BITS_MACID_RELEASE_INFO                                                \\\n\t(BIT_MASK_MACID_RELEASE_INFO << BIT_SHIFT_MACID_RELEASE_INFO)\n#define BIT_CLEAR_MACID_RELEASE_INFO(x) ((x) & (~BITS_MACID_RELEASE_INFO))\n#define BIT_GET_MACID_RELEASE_INFO(x)                                          \\\n\t(((x) >> BIT_SHIFT_MACID_RELEASE_INFO) & BIT_MASK_MACID_RELEASE_INFO)\n#define BIT_SET_MACID_RELEASE_INFO(x, v)                                       \\\n\t(BIT_CLEAR_MACID_RELEASE_INFO(x) | BIT_MACID_RELEASE_INFO(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MACID_RELEASE1\t\t\t(Offset 0x1438) */\n\n#define BIT_SHIFT_MACID63_32_RELEASE 0\n#define BIT_MASK_MACID63_32_RELEASE 0xffffffffL\n#define BIT_MACID63_32_RELEASE(x)                                              \\\n\t(((x) & BIT_MASK_MACID63_32_RELEASE) << BIT_SHIFT_MACID63_32_RELEASE)\n#define BITS_MACID63_32_RELEASE                                                \\\n\t(BIT_MASK_MACID63_32_RELEASE << BIT_SHIFT_MACID63_32_RELEASE)\n#define BIT_CLEAR_MACID63_32_RELEASE(x) ((x) & (~BITS_MACID63_32_RELEASE))\n#define BIT_GET_MACID63_32_RELEASE(x)                                          \\\n\t(((x) >> BIT_SHIFT_MACID63_32_RELEASE) & BIT_MASK_MACID63_32_RELEASE)\n#define BIT_SET_MACID63_32_RELEASE(x, v)                                       \\\n\t(BIT_CLEAR_MACID63_32_RELEASE(x) | BIT_MACID63_32_RELEASE(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MACID_RELEASE_SUCCESS_INFO\t\t(Offset 0x1438) */\n\n#define BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO 0\n#define BIT_MASK_MACID_RELEASE_SUCCESS_INFO 0xffffffffL\n#define BIT_MACID_RELEASE_SUCCESS_INFO(x)                                      \\\n\t(((x) & BIT_MASK_MACID_RELEASE_SUCCESS_INFO)                           \\\n\t << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO)\n#define BITS_MACID_RELEASE_SUCCESS_INFO                                        \\\n\t(BIT_MASK_MACID_RELEASE_SUCCESS_INFO                                   \\\n\t << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO)\n#define BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO(x)                                \\\n\t((x) & (~BITS_MACID_RELEASE_SUCCESS_INFO))\n#define BIT_GET_MACID_RELEASE_SUCCESS_INFO(x)                                  \\\n\t(((x) >> BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO) &                       \\\n\t BIT_MASK_MACID_RELEASE_SUCCESS_INFO)\n#define BIT_SET_MACID_RELEASE_SUCCESS_INFO(x, v)                               \\\n\t(BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO(x) |                             \\\n\t BIT_MACID_RELEASE_SUCCESS_INFO(v))\n\n/* 2 REG_MACID_RELEASE_CTRL\t\t\t(Offset 0x143C) */\n\n#define BIT_SHIFT_MACID_RELEASE_SEL 24\n#define BIT_MASK_MACID_RELEASE_SEL 0x7\n#define BIT_MACID_RELEASE_SEL(x)                                               \\\n\t(((x) & BIT_MASK_MACID_RELEASE_SEL) << BIT_SHIFT_MACID_RELEASE_SEL)\n#define BITS_MACID_RELEASE_SEL                                                 \\\n\t(BIT_MASK_MACID_RELEASE_SEL << BIT_SHIFT_MACID_RELEASE_SEL)\n#define BIT_CLEAR_MACID_RELEASE_SEL(x) ((x) & (~BITS_MACID_RELEASE_SEL))\n#define BIT_GET_MACID_RELEASE_SEL(x)                                           \\\n\t(((x) >> BIT_SHIFT_MACID_RELEASE_SEL) & BIT_MASK_MACID_RELEASE_SEL)\n#define BIT_SET_MACID_RELEASE_SEL(x, v)                                        \\\n\t(BIT_CLEAR_MACID_RELEASE_SEL(x) | BIT_MACID_RELEASE_SEL(v))\n\n#define BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET 16\n#define BIT_MASK_MACID_RELEASE_CLEAR_OFFSET 0xff\n#define BIT_MACID_RELEASE_CLEAR_OFFSET(x)                                      \\\n\t(((x) & BIT_MASK_MACID_RELEASE_CLEAR_OFFSET)                           \\\n\t << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET)\n#define BITS_MACID_RELEASE_CLEAR_OFFSET                                        \\\n\t(BIT_MASK_MACID_RELEASE_CLEAR_OFFSET                                   \\\n\t << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET)\n#define BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET(x)                                \\\n\t((x) & (~BITS_MACID_RELEASE_CLEAR_OFFSET))\n#define BIT_GET_MACID_RELEASE_CLEAR_OFFSET(x)                                  \\\n\t(((x) >> BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET) &                       \\\n\t BIT_MASK_MACID_RELEASE_CLEAR_OFFSET)\n#define BIT_SET_MACID_RELEASE_CLEAR_OFFSET(x, v)                               \\\n\t(BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET(x) |                             \\\n\t BIT_MACID_RELEASE_CLEAR_OFFSET(v))\n\n#define BIT_MACID_RELEASE_VALUE BIT(8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MACID_RELEASE2\t\t\t(Offset 0x143C) */\n\n#define BIT_SHIFT_MACID95_64_RELEASE 0\n#define BIT_MASK_MACID95_64_RELEASE 0xffffffffL\n#define BIT_MACID95_64_RELEASE(x)                                              \\\n\t(((x) & BIT_MASK_MACID95_64_RELEASE) << BIT_SHIFT_MACID95_64_RELEASE)\n#define BITS_MACID95_64_RELEASE                                                \\\n\t(BIT_MASK_MACID95_64_RELEASE << BIT_SHIFT_MACID95_64_RELEASE)\n#define BIT_CLEAR_MACID95_64_RELEASE(x) ((x) & (~BITS_MACID95_64_RELEASE))\n#define BIT_GET_MACID95_64_RELEASE(x)                                          \\\n\t(((x) >> BIT_SHIFT_MACID95_64_RELEASE) & BIT_MASK_MACID95_64_RELEASE)\n#define BIT_SET_MACID95_64_RELEASE(x, v)                                       \\\n\t(BIT_CLEAR_MACID95_64_RELEASE(x) | BIT_MACID95_64_RELEASE(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MACID_RELEASE_CTRL\t\t\t(Offset 0x143C) */\n\n#define BIT_SHIFT_MACID_RELEASE_OFFSET 0\n#define BIT_MASK_MACID_RELEASE_OFFSET 0xff\n#define BIT_MACID_RELEASE_OFFSET(x)                                            \\\n\t(((x) & BIT_MASK_MACID_RELEASE_OFFSET)                                 \\\n\t << BIT_SHIFT_MACID_RELEASE_OFFSET)\n#define BITS_MACID_RELEASE_OFFSET                                              \\\n\t(BIT_MASK_MACID_RELEASE_OFFSET << BIT_SHIFT_MACID_RELEASE_OFFSET)\n#define BIT_CLEAR_MACID_RELEASE_OFFSET(x) ((x) & (~BITS_MACID_RELEASE_OFFSET))\n#define BIT_GET_MACID_RELEASE_OFFSET(x)                                        \\\n\t(((x) >> BIT_SHIFT_MACID_RELEASE_OFFSET) &                             \\\n\t BIT_MASK_MACID_RELEASE_OFFSET)\n#define BIT_SET_MACID_RELEASE_OFFSET(x, v)                                     \\\n\t(BIT_CLEAR_MACID_RELEASE_OFFSET(x) | BIT_MACID_RELEASE_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MACID_RELEASE3\t\t\t(Offset 0x1440) */\n\n#define BIT_SHIFT_MACID127_96_RELEASE 0\n#define BIT_MASK_MACID127_96_RELEASE 0xffffffffL\n#define BIT_MACID127_96_RELEASE(x)                                             \\\n\t(((x) & BIT_MASK_MACID127_96_RELEASE) << BIT_SHIFT_MACID127_96_RELEASE)\n#define BITS_MACID127_96_RELEASE                                               \\\n\t(BIT_MASK_MACID127_96_RELEASE << BIT_SHIFT_MACID127_96_RELEASE)\n#define BIT_CLEAR_MACID127_96_RELEASE(x) ((x) & (~BITS_MACID127_96_RELEASE))\n#define BIT_GET_MACID127_96_RELEASE(x)                                         \\\n\t(((x) >> BIT_SHIFT_MACID127_96_RELEASE) & BIT_MASK_MACID127_96_RELEASE)\n#define BIT_SET_MACID127_96_RELEASE(x, v)                                      \\\n\t(BIT_CLEAR_MACID127_96_RELEASE(x) | BIT_MACID127_96_RELEASE(v))\n\n/* 2 REG_MACID_RELEASE_SETTING\t\t(Offset 0x1444) */\n\n#define BIT_MACID_VALUE BIT(7)\n\n#define BIT_SHIFT_MACID_OFFSET 0\n#define BIT_MASK_MACID_OFFSET 0x7f\n#define BIT_MACID_OFFSET(x)                                                    \\\n\t(((x) & BIT_MASK_MACID_OFFSET) << BIT_SHIFT_MACID_OFFSET)\n#define BITS_MACID_OFFSET (BIT_MASK_MACID_OFFSET << BIT_SHIFT_MACID_OFFSET)\n#define BIT_CLEAR_MACID_OFFSET(x) ((x) & (~BITS_MACID_OFFSET))\n#define BIT_GET_MACID_OFFSET(x)                                                \\\n\t(((x) >> BIT_SHIFT_MACID_OFFSET) & BIT_MASK_MACID_OFFSET)\n#define BIT_SET_MACID_OFFSET(x, v)                                             \\\n\t(BIT_CLEAR_MACID_OFFSET(x) | BIT_MACID_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FAST_EDCA_VOVI_SETTING\t\t(Offset 0x1448) */\n\n#define BIT_SHIFT_VI_FAST_EDCA_TO 24\n#define BIT_MASK_VI_FAST_EDCA_TO 0xff\n#define BIT_VI_FAST_EDCA_TO(x)                                                 \\\n\t(((x) & BIT_MASK_VI_FAST_EDCA_TO) << BIT_SHIFT_VI_FAST_EDCA_TO)\n#define BITS_VI_FAST_EDCA_TO                                                   \\\n\t(BIT_MASK_VI_FAST_EDCA_TO << BIT_SHIFT_VI_FAST_EDCA_TO)\n#define BIT_CLEAR_VI_FAST_EDCA_TO(x) ((x) & (~BITS_VI_FAST_EDCA_TO))\n#define BIT_GET_VI_FAST_EDCA_TO(x)                                             \\\n\t(((x) >> BIT_SHIFT_VI_FAST_EDCA_TO) & BIT_MASK_VI_FAST_EDCA_TO)\n#define BIT_SET_VI_FAST_EDCA_TO(x, v)                                          \\\n\t(BIT_CLEAR_VI_FAST_EDCA_TO(x) | BIT_VI_FAST_EDCA_TO(v))\n\n#define BIT_VI_THRESHOLD_SEL BIT(23)\n\n#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH 16\n#define BIT_MASK_VI_FAST_EDCA_PKT_TH 0x7f\n#define BIT_VI_FAST_EDCA_PKT_TH(x)                                             \\\n\t(((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH)\n#define BITS_VI_FAST_EDCA_PKT_TH                                               \\\n\t(BIT_MASK_VI_FAST_EDCA_PKT_TH << BIT_SHIFT_VI_FAST_EDCA_PKT_TH)\n#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_VI_FAST_EDCA_PKT_TH))\n#define BIT_GET_VI_FAST_EDCA_PKT_TH(x)                                         \\\n\t(((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH) & BIT_MASK_VI_FAST_EDCA_PKT_TH)\n#define BIT_SET_VI_FAST_EDCA_PKT_TH(x, v)                                      \\\n\t(BIT_CLEAR_VI_FAST_EDCA_PKT_TH(x) | BIT_VI_FAST_EDCA_PKT_TH(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FAST_EDCA_VOVI_SETTING\t\t(Offset 0x1448) */\n\n#define BIT_SHIFT_VO_FAST_EDCA_TO 8\n#define BIT_MASK_VO_FAST_EDCA_TO 0xff\n#define BIT_VO_FAST_EDCA_TO(x)                                                 \\\n\t(((x) & BIT_MASK_VO_FAST_EDCA_TO) << BIT_SHIFT_VO_FAST_EDCA_TO)\n#define BITS_VO_FAST_EDCA_TO                                                   \\\n\t(BIT_MASK_VO_FAST_EDCA_TO << BIT_SHIFT_VO_FAST_EDCA_TO)\n#define BIT_CLEAR_VO_FAST_EDCA_TO(x) ((x) & (~BITS_VO_FAST_EDCA_TO))\n#define BIT_GET_VO_FAST_EDCA_TO(x)                                             \\\n\t(((x) >> BIT_SHIFT_VO_FAST_EDCA_TO) & BIT_MASK_VO_FAST_EDCA_TO)\n#define BIT_SET_VO_FAST_EDCA_TO(x, v)                                          \\\n\t(BIT_CLEAR_VO_FAST_EDCA_TO(x) | BIT_VO_FAST_EDCA_TO(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FAST_EDCA_VOVI_SETTING\t\t(Offset 0x1448) */\n\n#define BIT_VO_THRESHOLD_SEL BIT(7)\n\n#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH 0\n#define BIT_MASK_VO_FAST_EDCA_PKT_TH 0x7f\n#define BIT_VO_FAST_EDCA_PKT_TH(x)                                             \\\n\t(((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH)\n#define BITS_VO_FAST_EDCA_PKT_TH                                               \\\n\t(BIT_MASK_VO_FAST_EDCA_PKT_TH << BIT_SHIFT_VO_FAST_EDCA_PKT_TH)\n#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_VO_FAST_EDCA_PKT_TH))\n#define BIT_GET_VO_FAST_EDCA_PKT_TH(x)                                         \\\n\t(((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH) & BIT_MASK_VO_FAST_EDCA_PKT_TH)\n#define BIT_SET_VO_FAST_EDCA_PKT_TH(x, v)                                      \\\n\t(BIT_CLEAR_VO_FAST_EDCA_PKT_TH(x) | BIT_VO_FAST_EDCA_PKT_TH(v))\n\n/* 2 REG_FAST_EDCA_BEBK_SETTING\t\t(Offset 0x144C) */\n\n#define BIT_SHIFT_BK_FAST_EDCA_TO 24\n#define BIT_MASK_BK_FAST_EDCA_TO 0xff\n#define BIT_BK_FAST_EDCA_TO(x)                                                 \\\n\t(((x) & BIT_MASK_BK_FAST_EDCA_TO) << BIT_SHIFT_BK_FAST_EDCA_TO)\n#define BITS_BK_FAST_EDCA_TO                                                   \\\n\t(BIT_MASK_BK_FAST_EDCA_TO << BIT_SHIFT_BK_FAST_EDCA_TO)\n#define BIT_CLEAR_BK_FAST_EDCA_TO(x) ((x) & (~BITS_BK_FAST_EDCA_TO))\n#define BIT_GET_BK_FAST_EDCA_TO(x)                                             \\\n\t(((x) >> BIT_SHIFT_BK_FAST_EDCA_TO) & BIT_MASK_BK_FAST_EDCA_TO)\n#define BIT_SET_BK_FAST_EDCA_TO(x, v)                                          \\\n\t(BIT_CLEAR_BK_FAST_EDCA_TO(x) | BIT_BK_FAST_EDCA_TO(v))\n\n#define BIT_BK_THRESHOLD_SEL BIT(23)\n\n#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH 16\n#define BIT_MASK_BK_FAST_EDCA_PKT_TH 0x7f\n#define BIT_BK_FAST_EDCA_PKT_TH(x)                                             \\\n\t(((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH)\n#define BITS_BK_FAST_EDCA_PKT_TH                                               \\\n\t(BIT_MASK_BK_FAST_EDCA_PKT_TH << BIT_SHIFT_BK_FAST_EDCA_PKT_TH)\n#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_BK_FAST_EDCA_PKT_TH))\n#define BIT_GET_BK_FAST_EDCA_PKT_TH(x)                                         \\\n\t(((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH) & BIT_MASK_BK_FAST_EDCA_PKT_TH)\n#define BIT_SET_BK_FAST_EDCA_PKT_TH(x, v)                                      \\\n\t(BIT_CLEAR_BK_FAST_EDCA_PKT_TH(x) | BIT_BK_FAST_EDCA_PKT_TH(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FAST_EDCA_BEBK_SETTING\t\t(Offset 0x144C) */\n\n#define BIT_SHIFT_BE_FAST_EDCA_TO 8\n#define BIT_MASK_BE_FAST_EDCA_TO 0xff\n#define BIT_BE_FAST_EDCA_TO(x)                                                 \\\n\t(((x) & BIT_MASK_BE_FAST_EDCA_TO) << BIT_SHIFT_BE_FAST_EDCA_TO)\n#define BITS_BE_FAST_EDCA_TO                                                   \\\n\t(BIT_MASK_BE_FAST_EDCA_TO << BIT_SHIFT_BE_FAST_EDCA_TO)\n#define BIT_CLEAR_BE_FAST_EDCA_TO(x) ((x) & (~BITS_BE_FAST_EDCA_TO))\n#define BIT_GET_BE_FAST_EDCA_TO(x)                                             \\\n\t(((x) >> BIT_SHIFT_BE_FAST_EDCA_TO) & BIT_MASK_BE_FAST_EDCA_TO)\n#define BIT_SET_BE_FAST_EDCA_TO(x, v)                                          \\\n\t(BIT_CLEAR_BE_FAST_EDCA_TO(x) | BIT_BE_FAST_EDCA_TO(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_FAST_EDCA_BEBK_SETTING\t\t(Offset 0x144C) */\n\n#define BIT_BE_THRESHOLD_SEL BIT(7)\n\n#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH 0\n#define BIT_MASK_BE_FAST_EDCA_PKT_TH 0x7f\n#define BIT_BE_FAST_EDCA_PKT_TH(x)                                             \\\n\t(((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH)\n#define BITS_BE_FAST_EDCA_PKT_TH                                               \\\n\t(BIT_MASK_BE_FAST_EDCA_PKT_TH << BIT_SHIFT_BE_FAST_EDCA_PKT_TH)\n#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_BE_FAST_EDCA_PKT_TH))\n#define BIT_GET_BE_FAST_EDCA_PKT_TH(x)                                         \\\n\t(((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH) & BIT_MASK_BE_FAST_EDCA_PKT_TH)\n#define BIT_SET_BE_FAST_EDCA_PKT_TH(x, v)                                      \\\n\t(BIT_CLEAR_BE_FAST_EDCA_PKT_TH(x) | BIT_BE_FAST_EDCA_PKT_TH(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MACID_DROP0\t\t\t\t(Offset 0x1450) */\n\n#define BIT_SHIFT_MACID31_0_DROP 0\n#define BIT_MASK_MACID31_0_DROP 0xffffffffL\n#define BIT_MACID31_0_DROP(x)                                                  \\\n\t(((x) & BIT_MASK_MACID31_0_DROP) << BIT_SHIFT_MACID31_0_DROP)\n#define BITS_MACID31_0_DROP                                                    \\\n\t(BIT_MASK_MACID31_0_DROP << BIT_SHIFT_MACID31_0_DROP)\n#define BIT_CLEAR_MACID31_0_DROP(x) ((x) & (~BITS_MACID31_0_DROP))\n#define BIT_GET_MACID31_0_DROP(x)                                              \\\n\t(((x) >> BIT_SHIFT_MACID31_0_DROP) & BIT_MASK_MACID31_0_DROP)\n#define BIT_SET_MACID31_0_DROP(x, v)                                           \\\n\t(BIT_CLEAR_MACID31_0_DROP(x) | BIT_MACID31_0_DROP(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MACID_DROP_INFO\t\t\t(Offset 0x1450) */\n\n#define BIT_SHIFT_MACID_DROP_INFO 0\n#define BIT_MASK_MACID_DROP_INFO 0xffffffffL\n#define BIT_MACID_DROP_INFO(x)                                                 \\\n\t(((x) & BIT_MASK_MACID_DROP_INFO) << BIT_SHIFT_MACID_DROP_INFO)\n#define BITS_MACID_DROP_INFO                                                   \\\n\t(BIT_MASK_MACID_DROP_INFO << BIT_SHIFT_MACID_DROP_INFO)\n#define BIT_CLEAR_MACID_DROP_INFO(x) ((x) & (~BITS_MACID_DROP_INFO))\n#define BIT_GET_MACID_DROP_INFO(x)                                             \\\n\t(((x) >> BIT_SHIFT_MACID_DROP_INFO) & BIT_MASK_MACID_DROP_INFO)\n#define BIT_SET_MACID_DROP_INFO(x, v)                                          \\\n\t(BIT_CLEAR_MACID_DROP_INFO(x) | BIT_MACID_DROP_INFO(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MACID_DROP1\t\t\t\t(Offset 0x1454) */\n\n#define BIT_SHIFT_MACID63_32_DROP 0\n#define BIT_MASK_MACID63_32_DROP 0xffffffffL\n#define BIT_MACID63_32_DROP(x)                                                 \\\n\t(((x) & BIT_MASK_MACID63_32_DROP) << BIT_SHIFT_MACID63_32_DROP)\n#define BITS_MACID63_32_DROP                                                   \\\n\t(BIT_MASK_MACID63_32_DROP << BIT_SHIFT_MACID63_32_DROP)\n#define BIT_CLEAR_MACID63_32_DROP(x) ((x) & (~BITS_MACID63_32_DROP))\n#define BIT_GET_MACID63_32_DROP(x)                                             \\\n\t(((x) >> BIT_SHIFT_MACID63_32_DROP) & BIT_MASK_MACID63_32_DROP)\n#define BIT_SET_MACID63_32_DROP(x, v)                                          \\\n\t(BIT_CLEAR_MACID63_32_DROP(x) | BIT_MACID63_32_DROP(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MACID_DROP_CTRL\t\t\t(Offset 0x1454) */\n\n#define BIT_SHIFT_MACID_DROP_SEL 0\n#define BIT_MASK_MACID_DROP_SEL 0x7\n#define BIT_MACID_DROP_SEL(x)                                                  \\\n\t(((x) & BIT_MASK_MACID_DROP_SEL) << BIT_SHIFT_MACID_DROP_SEL)\n#define BITS_MACID_DROP_SEL                                                    \\\n\t(BIT_MASK_MACID_DROP_SEL << BIT_SHIFT_MACID_DROP_SEL)\n#define BIT_CLEAR_MACID_DROP_SEL(x) ((x) & (~BITS_MACID_DROP_SEL))\n#define BIT_GET_MACID_DROP_SEL(x)                                              \\\n\t(((x) >> BIT_SHIFT_MACID_DROP_SEL) & BIT_MASK_MACID_DROP_SEL)\n#define BIT_SET_MACID_DROP_SEL(x, v)                                           \\\n\t(BIT_CLEAR_MACID_DROP_SEL(x) | BIT_MACID_DROP_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MACID_DROP2\t\t\t\t(Offset 0x1458) */\n\n#define BIT_SHIFT_MACID95_64_DROP 0\n#define BIT_MASK_MACID95_64_DROP 0xffffffffL\n#define BIT_MACID95_64_DROP(x)                                                 \\\n\t(((x) & BIT_MASK_MACID95_64_DROP) << BIT_SHIFT_MACID95_64_DROP)\n#define BITS_MACID95_64_DROP                                                   \\\n\t(BIT_MASK_MACID95_64_DROP << BIT_SHIFT_MACID95_64_DROP)\n#define BIT_CLEAR_MACID95_64_DROP(x) ((x) & (~BITS_MACID95_64_DROP))\n#define BIT_GET_MACID95_64_DROP(x)                                             \\\n\t(((x) >> BIT_SHIFT_MACID95_64_DROP) & BIT_MASK_MACID95_64_DROP)\n#define BIT_SET_MACID95_64_DROP(x, v)                                          \\\n\t(BIT_CLEAR_MACID95_64_DROP(x) | BIT_MACID95_64_DROP(v))\n\n/* 2 REG_MACID_DROP3\t\t\t\t(Offset 0x145C) */\n\n#define BIT_SHIFT_MACID127_96_DROP 0\n#define BIT_MASK_MACID127_96_DROP 0xffffffffL\n#define BIT_MACID127_96_DROP(x)                                                \\\n\t(((x) & BIT_MASK_MACID127_96_DROP) << BIT_SHIFT_MACID127_96_DROP)\n#define BITS_MACID127_96_DROP                                                  \\\n\t(BIT_MASK_MACID127_96_DROP << BIT_SHIFT_MACID127_96_DROP)\n#define BIT_CLEAR_MACID127_96_DROP(x) ((x) & (~BITS_MACID127_96_DROP))\n#define BIT_GET_MACID127_96_DROP(x)                                            \\\n\t(((x) >> BIT_SHIFT_MACID127_96_DROP) & BIT_MASK_MACID127_96_DROP)\n#define BIT_SET_MACID127_96_DROP(x, v)                                         \\\n\t(BIT_CLEAR_MACID127_96_DROP(x) | BIT_MACID127_96_DROP(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_1\t\t(Offset 0x1464) */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_1(x)                                       \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1)                            \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1)\n#define BITS_R_MACID_RELEASE_SUCCESS_1                                         \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_1                                    \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1(x)                                 \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_1(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) &                        \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_1)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_1(x, v)                                \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1(x) |                              \\\n\t BIT_R_MACID_RELEASE_SUCCESS_1(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_3\t\t(Offset 0x146C) */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_3(x)                                       \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3)                            \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3)\n#define BITS_R_MACID_RELEASE_SUCCESS_3                                         \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_3                                    \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3(x)                                 \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_3(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) &                        \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_3)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_3(x, v)                                \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3(x) |                              \\\n\t BIT_R_MACID_RELEASE_SUCCESS_3(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_MGG_FIFO_CRTL\t\t\t(Offset 0x1470) */\n\n#define BIT_R_MGG_FIFO_EN BIT(31)\n\n#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE 28\n#define BIT_MASK_R_MGG_FIFO_PG_SIZE 0x7\n#define BIT_R_MGG_FIFO_PG_SIZE(x)                                              \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE)\n#define BITS_R_MGG_FIFO_PG_SIZE                                                \\\n\t(BIT_MASK_R_MGG_FIFO_PG_SIZE << BIT_SHIFT_R_MGG_FIFO_PG_SIZE)\n#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE(x) ((x) & (~BITS_R_MGG_FIFO_PG_SIZE))\n#define BIT_GET_R_MGG_FIFO_PG_SIZE(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE) & BIT_MASK_R_MGG_FIFO_PG_SIZE)\n#define BIT_SET_R_MGG_FIFO_PG_SIZE(x, v)                                       \\\n\t(BIT_CLEAR_R_MGG_FIFO_PG_SIZE(x) | BIT_R_MGG_FIFO_PG_SIZE(v))\n\n#define BIT_SHIFT_R_MGG_FIFO_START_PG 16\n#define BIT_MASK_R_MGG_FIFO_START_PG 0xfff\n#define BIT_R_MGG_FIFO_START_PG(x)                                             \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_START_PG) << BIT_SHIFT_R_MGG_FIFO_START_PG)\n#define BITS_R_MGG_FIFO_START_PG                                               \\\n\t(BIT_MASK_R_MGG_FIFO_START_PG << BIT_SHIFT_R_MGG_FIFO_START_PG)\n#define BIT_CLEAR_R_MGG_FIFO_START_PG(x) ((x) & (~BITS_R_MGG_FIFO_START_PG))\n#define BIT_GET_R_MGG_FIFO_START_PG(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG) & BIT_MASK_R_MGG_FIFO_START_PG)\n#define BIT_SET_R_MGG_FIFO_START_PG(x, v)                                      \\\n\t(BIT_CLEAR_R_MGG_FIFO_START_PG(x) | BIT_R_MGG_FIFO_START_PG(v))\n\n#define BIT_SHIFT_R_MGG_FIFO_SIZE 14\n#define BIT_MASK_R_MGG_FIFO_SIZE 0x3\n#define BIT_R_MGG_FIFO_SIZE(x)                                                 \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_SIZE) << BIT_SHIFT_R_MGG_FIFO_SIZE)\n#define BITS_R_MGG_FIFO_SIZE                                                   \\\n\t(BIT_MASK_R_MGG_FIFO_SIZE << BIT_SHIFT_R_MGG_FIFO_SIZE)\n#define BIT_CLEAR_R_MGG_FIFO_SIZE(x) ((x) & (~BITS_R_MGG_FIFO_SIZE))\n#define BIT_GET_R_MGG_FIFO_SIZE(x)                                             \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE) & BIT_MASK_R_MGG_FIFO_SIZE)\n#define BIT_SET_R_MGG_FIFO_SIZE(x, v)                                          \\\n\t(BIT_CLEAR_R_MGG_FIFO_SIZE(x) | BIT_R_MGG_FIFO_SIZE(v))\n\n#define BIT_R_MGG_FIFO_PAUSE BIT(13)\n\n#define BIT_SHIFT_R_MGG_FIFO_RPTR 8\n#define BIT_MASK_R_MGG_FIFO_RPTR 0x1f\n#define BIT_R_MGG_FIFO_RPTR(x)                                                 \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_RPTR) << BIT_SHIFT_R_MGG_FIFO_RPTR)\n#define BITS_R_MGG_FIFO_RPTR                                                   \\\n\t(BIT_MASK_R_MGG_FIFO_RPTR << BIT_SHIFT_R_MGG_FIFO_RPTR)\n#define BIT_CLEAR_R_MGG_FIFO_RPTR(x) ((x) & (~BITS_R_MGG_FIFO_RPTR))\n#define BIT_GET_R_MGG_FIFO_RPTR(x)                                             \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR) & BIT_MASK_R_MGG_FIFO_RPTR)\n#define BIT_SET_R_MGG_FIFO_RPTR(x, v)                                          \\\n\t(BIT_CLEAR_R_MGG_FIFO_RPTR(x) | BIT_R_MGG_FIFO_RPTR(v))\n\n#define BIT_R_MGG_FIFO_OV BIT(7)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MGQ_FIFO_WRITE_POINTER\t\t(Offset 0x1470) */\n\n#define BIT_MGQ_FIFO_OV BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_MGG_FIFO_CRTL\t\t\t(Offset 0x1470) */\n\n#define BIT_R_MGG_FIFO_WPTR_ERROR BIT(6)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MGQ_FIFO_WRITE_POINTER\t\t(Offset 0x1470) */\n\n#define BIT_MGQ_FIFO_WPTR_ERROR BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_MGG_FIFO_CRTL\t\t\t(Offset 0x1470) */\n\n#define BIT_R_EN_CPU_LIFETIME BIT(5)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MGQ_FIFO_WRITE_POINTER\t\t(Offset 0x1470) */\n\n#define BIT_EN_MGQ_FIFO_LIFETIME BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_MGG_FIFO_CRTL\t\t\t(Offset 0x1470) */\n\n#define BIT_SHIFT_R_MGG_FIFO_WPTR 0\n#define BIT_MASK_R_MGG_FIFO_WPTR 0x1f\n#define BIT_R_MGG_FIFO_WPTR(x)                                                 \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_WPTR) << BIT_SHIFT_R_MGG_FIFO_WPTR)\n#define BITS_R_MGG_FIFO_WPTR                                                   \\\n\t(BIT_MASK_R_MGG_FIFO_WPTR << BIT_SHIFT_R_MGG_FIFO_WPTR)\n#define BIT_CLEAR_R_MGG_FIFO_WPTR(x) ((x) & (~BITS_R_MGG_FIFO_WPTR))\n#define BIT_GET_R_MGG_FIFO_WPTR(x)                                             \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR) & BIT_MASK_R_MGG_FIFO_WPTR)\n#define BIT_SET_R_MGG_FIFO_WPTR(x, v)                                          \\\n\t(BIT_CLEAR_R_MGG_FIFO_WPTR(x) | BIT_R_MGG_FIFO_WPTR(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MGQ_FIFO_WRITE_POINTER\t\t(Offset 0x1470) */\n\n#define BIT_SHIFT_MGQ_FIFO_WPTR 0\n#define BIT_MASK_MGQ_FIFO_WPTR 0x1f\n#define BIT_MGQ_FIFO_WPTR(x)                                                   \\\n\t(((x) & BIT_MASK_MGQ_FIFO_WPTR) << BIT_SHIFT_MGQ_FIFO_WPTR)\n#define BITS_MGQ_FIFO_WPTR (BIT_MASK_MGQ_FIFO_WPTR << BIT_SHIFT_MGQ_FIFO_WPTR)\n#define BIT_CLEAR_MGQ_FIFO_WPTR(x) ((x) & (~BITS_MGQ_FIFO_WPTR))\n#define BIT_GET_MGQ_FIFO_WPTR(x)                                               \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_WPTR) & BIT_MASK_MGQ_FIFO_WPTR)\n#define BIT_SET_MGQ_FIFO_WPTR(x, v)                                            \\\n\t(BIT_CLEAR_MGQ_FIFO_WPTR(x) | BIT_MGQ_FIFO_WPTR(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MGQ_FIFO_ENABLE\t\t\t(Offset 0x1472) */\n\n#define BIT_MGQ_FIFO_EN BIT(15)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MGQ_FIFO_ENABLE\t\t\t(Offset 0x1472) */\n\n#define BIT_MGQ_FIFO_EN_V1 BIT(15)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MGQ_FIFO_READ_POINTER\t\t(Offset 0x1472) */\n\n#define BIT_SHIFT_MGQ_FIFO_SIZE 14\n#define BIT_MASK_MGQ_FIFO_SIZE 0x3\n#define BIT_MGQ_FIFO_SIZE(x)                                                   \\\n\t(((x) & BIT_MASK_MGQ_FIFO_SIZE) << BIT_SHIFT_MGQ_FIFO_SIZE)\n#define BITS_MGQ_FIFO_SIZE (BIT_MASK_MGQ_FIFO_SIZE << BIT_SHIFT_MGQ_FIFO_SIZE)\n#define BIT_CLEAR_MGQ_FIFO_SIZE(x) ((x) & (~BITS_MGQ_FIFO_SIZE))\n#define BIT_GET_MGQ_FIFO_SIZE(x)                                               \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_SIZE) & BIT_MASK_MGQ_FIFO_SIZE)\n#define BIT_SET_MGQ_FIFO_SIZE(x, v)                                            \\\n\t(BIT_CLEAR_MGQ_FIFO_SIZE(x) | BIT_MGQ_FIFO_SIZE(v))\n\n#define BIT_MGQ_FIFO_PAUSE BIT(13)\n\n#define BIT_SHIFT_MGQ_FIFO_PG_SIZE 12\n#define BIT_MASK_MGQ_FIFO_PG_SIZE 0x7\n#define BIT_MGQ_FIFO_PG_SIZE(x)                                                \\\n\t(((x) & BIT_MASK_MGQ_FIFO_PG_SIZE) << BIT_SHIFT_MGQ_FIFO_PG_SIZE)\n#define BITS_MGQ_FIFO_PG_SIZE                                                  \\\n\t(BIT_MASK_MGQ_FIFO_PG_SIZE << BIT_SHIFT_MGQ_FIFO_PG_SIZE)\n#define BIT_CLEAR_MGQ_FIFO_PG_SIZE(x) ((x) & (~BITS_MGQ_FIFO_PG_SIZE))\n#define BIT_GET_MGQ_FIFO_PG_SIZE(x)                                            \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE) & BIT_MASK_MGQ_FIFO_PG_SIZE)\n#define BIT_SET_MGQ_FIFO_PG_SIZE(x, v)                                         \\\n\t(BIT_CLEAR_MGQ_FIFO_PG_SIZE(x) | BIT_MGQ_FIFO_PG_SIZE(v))\n\n#define BIT_SHIFT_MGQ_FIFO_RPTR 8\n#define BIT_MASK_MGQ_FIFO_RPTR 0x1f\n#define BIT_MGQ_FIFO_RPTR(x)                                                   \\\n\t(((x) & BIT_MASK_MGQ_FIFO_RPTR) << BIT_SHIFT_MGQ_FIFO_RPTR)\n#define BITS_MGQ_FIFO_RPTR (BIT_MASK_MGQ_FIFO_RPTR << BIT_SHIFT_MGQ_FIFO_RPTR)\n#define BIT_CLEAR_MGQ_FIFO_RPTR(x) ((x) & (~BITS_MGQ_FIFO_RPTR))\n#define BIT_GET_MGQ_FIFO_RPTR(x)                                               \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_RPTR) & BIT_MASK_MGQ_FIFO_RPTR)\n#define BIT_SET_MGQ_FIFO_RPTR(x, v)                                            \\\n\t(BIT_CLEAR_MGQ_FIFO_RPTR(x) | BIT_MGQ_FIFO_RPTR(v))\n\n#define BIT_SHIFT_MGQ_FIFO_START_PG 0\n#define BIT_MASK_MGQ_FIFO_START_PG 0xfff\n#define BIT_MGQ_FIFO_START_PG(x)                                               \\\n\t(((x) & BIT_MASK_MGQ_FIFO_START_PG) << BIT_SHIFT_MGQ_FIFO_START_PG)\n#define BITS_MGQ_FIFO_START_PG                                                 \\\n\t(BIT_MASK_MGQ_FIFO_START_PG << BIT_SHIFT_MGQ_FIFO_START_PG)\n#define BIT_CLEAR_MGQ_FIFO_START_PG(x) ((x) & (~BITS_MGQ_FIFO_START_PG))\n#define BIT_GET_MGQ_FIFO_START_PG(x)                                           \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_START_PG) & BIT_MASK_MGQ_FIFO_START_PG)\n#define BIT_SET_MGQ_FIFO_START_PG(x, v)                                        \\\n\t(BIT_CLEAR_MGQ_FIFO_START_PG(x) | BIT_MGQ_FIFO_START_PG(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_MGG_FIFO_INT\t\t\t(Offset 0x1474) */\n\n#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG 16\n#define BIT_MASK_R_MGG_FIFO_INT_FLAG 0xffff\n#define BIT_R_MGG_FIFO_INT_FLAG(x)                                             \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG)\n#define BITS_R_MGG_FIFO_INT_FLAG                                               \\\n\t(BIT_MASK_R_MGG_FIFO_INT_FLAG << BIT_SHIFT_R_MGG_FIFO_INT_FLAG)\n#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG(x) ((x) & (~BITS_R_MGG_FIFO_INT_FLAG))\n#define BIT_GET_R_MGG_FIFO_INT_FLAG(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG) & BIT_MASK_R_MGG_FIFO_INT_FLAG)\n#define BIT_SET_R_MGG_FIFO_INT_FLAG(x, v)                                      \\\n\t(BIT_CLEAR_R_MGG_FIFO_INT_FLAG(x) | BIT_R_MGG_FIFO_INT_FLAG(v))\n\n#define BIT_SHIFT_R_MGG_FIFO_INT_MASK 0\n#define BIT_MASK_R_MGG_FIFO_INT_MASK 0xffff\n#define BIT_R_MGG_FIFO_INT_MASK(x)                                             \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_INT_MASK) << BIT_SHIFT_R_MGG_FIFO_INT_MASK)\n#define BITS_R_MGG_FIFO_INT_MASK                                               \\\n\t(BIT_MASK_R_MGG_FIFO_INT_MASK << BIT_SHIFT_R_MGG_FIFO_INT_MASK)\n#define BIT_CLEAR_R_MGG_FIFO_INT_MASK(x) ((x) & (~BITS_R_MGG_FIFO_INT_MASK))\n#define BIT_GET_R_MGG_FIFO_INT_MASK(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK) & BIT_MASK_R_MGG_FIFO_INT_MASK)\n#define BIT_SET_R_MGG_FIFO_INT_MASK(x, v)                                      \\\n\t(BIT_CLEAR_R_MGG_FIFO_INT_MASK(x) | BIT_R_MGG_FIFO_INT_MASK(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK\t\t(Offset 0x1474) */\n\n#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK 0\n#define BIT_MASK_MGQ_FIFO_REL_INT_MASK 0xffff\n#define BIT_MGQ_FIFO_REL_INT_MASK(x)                                           \\\n\t(((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK)                                \\\n\t << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK)\n#define BITS_MGQ_FIFO_REL_INT_MASK                                             \\\n\t(BIT_MASK_MGQ_FIFO_REL_INT_MASK << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK)\n#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK(x) ((x) & (~BITS_MGQ_FIFO_REL_INT_MASK))\n#define BIT_GET_MGQ_FIFO_REL_INT_MASK(x)                                       \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK) &                            \\\n\t BIT_MASK_MGQ_FIFO_REL_INT_MASK)\n#define BIT_SET_MGQ_FIFO_REL_INT_MASK(x, v)                                    \\\n\t(BIT_CLEAR_MGQ_FIFO_REL_INT_MASK(x) | BIT_MGQ_FIFO_REL_INT_MASK(v))\n\n/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG\t\t(Offset 0x1476) */\n\n#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG 0\n#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG 0xffff\n#define BIT_MGQ_FIFO_REL_INT_FLAG(x)                                           \\\n\t(((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG)                                \\\n\t << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG)\n#define BITS_MGQ_FIFO_REL_INT_FLAG                                             \\\n\t(BIT_MASK_MGQ_FIFO_REL_INT_FLAG << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG)\n#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG(x) ((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG))\n#define BIT_GET_MGQ_FIFO_REL_INT_FLAG(x)                                       \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG) &                            \\\n\t BIT_MASK_MGQ_FIFO_REL_INT_FLAG)\n#define BIT_SET_MGQ_FIFO_REL_INT_FLAG(x, v)                                    \\\n\t(BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG(x) | BIT_MGQ_FIFO_REL_INT_FLAG(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_MGG_FIFO_LIFETIME\t\t\t(Offset 0x1478) */\n\n#define BIT_SHIFT_R_MGG_FIFO_LIFETIME 16\n#define BIT_MASK_R_MGG_FIFO_LIFETIME 0xffff\n#define BIT_R_MGG_FIFO_LIFETIME(x)                                             \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_LIFETIME) << BIT_SHIFT_R_MGG_FIFO_LIFETIME)\n#define BITS_R_MGG_FIFO_LIFETIME                                               \\\n\t(BIT_MASK_R_MGG_FIFO_LIFETIME << BIT_SHIFT_R_MGG_FIFO_LIFETIME)\n#define BIT_CLEAR_R_MGG_FIFO_LIFETIME(x) ((x) & (~BITS_R_MGG_FIFO_LIFETIME))\n#define BIT_GET_R_MGG_FIFO_LIFETIME(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME) & BIT_MASK_R_MGG_FIFO_LIFETIME)\n#define BIT_SET_R_MGG_FIFO_LIFETIME(x, v)                                      \\\n\t(BIT_CLEAR_R_MGG_FIFO_LIFETIME(x) | BIT_R_MGG_FIFO_LIFETIME(v))\n\n#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP 0\n#define BIT_MASK_R_MGG_FIFO_VALID_MAP 0xffff\n#define BIT_R_MGG_FIFO_VALID_MAP(x)                                            \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP)                                 \\\n\t << BIT_SHIFT_R_MGG_FIFO_VALID_MAP)\n#define BITS_R_MGG_FIFO_VALID_MAP                                              \\\n\t(BIT_MASK_R_MGG_FIFO_VALID_MAP << BIT_SHIFT_R_MGG_FIFO_VALID_MAP)\n#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP(x) ((x) & (~BITS_R_MGG_FIFO_VALID_MAP))\n#define BIT_GET_R_MGG_FIFO_VALID_MAP(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP) &                             \\\n\t BIT_MASK_R_MGG_FIFO_VALID_MAP)\n#define BIT_SET_R_MGG_FIFO_VALID_MAP(x, v)                                     \\\n\t(BIT_CLEAR_R_MGG_FIFO_VALID_MAP(x) | BIT_R_MGG_FIFO_VALID_MAP(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MGQ_FIFO_VALID_MAP\t\t\t(Offset 0x1478) */\n\n#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP 0\n#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP 0xffff\n#define BIT_MGQ_FIFO_PKT_VALID_MAP(x)                                          \\\n\t(((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP)                               \\\n\t << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP)\n#define BITS_MGQ_FIFO_PKT_VALID_MAP                                            \\\n\t(BIT_MASK_MGQ_FIFO_PKT_VALID_MAP << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP)\n#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP(x)                                    \\\n\t((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP))\n#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP(x)                                      \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP) &                           \\\n\t BIT_MASK_MGQ_FIFO_PKT_VALID_MAP)\n#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP(x, v)                                   \\\n\t(BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP(x) | BIT_MGQ_FIFO_PKT_VALID_MAP(v))\n\n/* 2 REG_MGQ_FIFO_LIFETIME\t\t\t(Offset 0x147A) */\n\n#define BIT_RPT_VALID BIT(13)\n\n#define BIT_SHIFT_MGQ_FIFO_LIFETIME 0\n#define BIT_MASK_MGQ_FIFO_LIFETIME 0xffff\n#define BIT_MGQ_FIFO_LIFETIME(x)                                               \\\n\t(((x) & BIT_MASK_MGQ_FIFO_LIFETIME) << BIT_SHIFT_MGQ_FIFO_LIFETIME)\n#define BITS_MGQ_FIFO_LIFETIME                                                 \\\n\t(BIT_MASK_MGQ_FIFO_LIFETIME << BIT_SHIFT_MGQ_FIFO_LIFETIME)\n#define BIT_CLEAR_MGQ_FIFO_LIFETIME(x) ((x) & (~BITS_MGQ_FIFO_LIFETIME))\n#define BIT_GET_MGQ_FIFO_LIFETIME(x)                                           \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME) & BIT_MASK_MGQ_FIFO_LIFETIME)\n#define BIT_SET_MGQ_FIFO_LIFETIME(x, v)                                        \\\n\t(BIT_CLEAR_MGQ_FIFO_LIFETIME(x) | BIT_MGQ_FIFO_LIFETIME(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET (Offset 0x147C) */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x7f\n#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x)                            \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)                 \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)\n#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET                              \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET                         \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x)                      \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x)                        \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) &             \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x, v)                     \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) |                   \\\n\t BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PKT_TRANS\t\t\t\t(Offset 0x1480) */\n\n#define BIT_SHIFT_IE_DESC_OFFSET 16\n#define BIT_MASK_IE_DESC_OFFSET 0x1ff\n#define BIT_IE_DESC_OFFSET(x)                                                  \\\n\t(((x) & BIT_MASK_IE_DESC_OFFSET) << BIT_SHIFT_IE_DESC_OFFSET)\n#define BITS_IE_DESC_OFFSET                                                    \\\n\t(BIT_MASK_IE_DESC_OFFSET << BIT_SHIFT_IE_DESC_OFFSET)\n#define BIT_CLEAR_IE_DESC_OFFSET(x) ((x) & (~BITS_IE_DESC_OFFSET))\n#define BIT_GET_IE_DESC_OFFSET(x)                                              \\\n\t(((x) >> BIT_SHIFT_IE_DESC_OFFSET) & BIT_MASK_IE_DESC_OFFSET)\n#define BIT_SET_IE_DESC_OFFSET(x, v)                                           \\\n\t(BIT_CLEAR_IE_DESC_OFFSET(x) | BIT_IE_DESC_OFFSET(v))\n\n#define BIT_DIS_FWCMD_PATH_ERRCHK BIT(13)\n#define BIT_MAC_HDR_CONVERT_EN BIT(12)\n#define BIT_TXDESC_TRANS_EN BIT(8)\n#define BIT_PKT_TRANS_ERRINT_EN BIT(7)\n\n#define BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL 4\n#define BIT_MASK_PKT_TRANS_ERR_MACID_SEL 0x3\n#define BIT_PKT_TRANS_ERR_MACID_SEL(x)                                         \\\n\t(((x) & BIT_MASK_PKT_TRANS_ERR_MACID_SEL)                              \\\n\t << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL)\n#define BITS_PKT_TRANS_ERR_MACID_SEL                                           \\\n\t(BIT_MASK_PKT_TRANS_ERR_MACID_SEL << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL)\n#define BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL(x)                                   \\\n\t((x) & (~BITS_PKT_TRANS_ERR_MACID_SEL))\n#define BIT_GET_PKT_TRANS_ERR_MACID_SEL(x)                                     \\\n\t(((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL) &                          \\\n\t BIT_MASK_PKT_TRANS_ERR_MACID_SEL)\n#define BIT_SET_PKT_TRANS_ERR_MACID_SEL(x, v)                                  \\\n\t(BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL(x) | BIT_PKT_TRANS_ERR_MACID_SEL(v))\n\n#define BIT_PKT_TRANS_IEINIT_ERR BIT(3)\n#define BIT_PKT_TRANS_IENUM_ERR BIT(2)\n#define BIT_PKT_TRANS_IECNT_ERR1 BIT(1)\n#define BIT_PKT_TRANS_IECNT_ERR0 BIT(0)\n\n/* 2 REG_SHCUT_LLC_ETH_TYPE1\t\t\t(Offset 0x1488) */\n\n#define BIT_SHIFT_SHCUT_MHDR_OFFSET 16\n#define BIT_MASK_SHCUT_MHDR_OFFSET 0x1ff\n#define BIT_SHCUT_MHDR_OFFSET(x)                                               \\\n\t(((x) & BIT_MASK_SHCUT_MHDR_OFFSET) << BIT_SHIFT_SHCUT_MHDR_OFFSET)\n#define BITS_SHCUT_MHDR_OFFSET                                                 \\\n\t(BIT_MASK_SHCUT_MHDR_OFFSET << BIT_SHIFT_SHCUT_MHDR_OFFSET)\n#define BIT_CLEAR_SHCUT_MHDR_OFFSET(x) ((x) & (~BITS_SHCUT_MHDR_OFFSET))\n#define BIT_GET_SHCUT_MHDR_OFFSET(x)                                           \\\n\t(((x) >> BIT_SHIFT_SHCUT_MHDR_OFFSET) & BIT_MASK_SHCUT_MHDR_OFFSET)\n#define BIT_SET_SHCUT_MHDR_OFFSET(x, v)                                        \\\n\t(BIT_CLEAR_SHCUT_MHDR_OFFSET(x) | BIT_SHCUT_MHDR_OFFSET(v))\n\n#define BIT_SHIFT_PKT_TRANS_ERR_MACID 0\n#define BIT_MASK_PKT_TRANS_ERR_MACID 0xffffffffL\n#define BIT_PKT_TRANS_ERR_MACID(x)                                             \\\n\t(((x) & BIT_MASK_PKT_TRANS_ERR_MACID) << BIT_SHIFT_PKT_TRANS_ERR_MACID)\n#define BITS_PKT_TRANS_ERR_MACID                                               \\\n\t(BIT_MASK_PKT_TRANS_ERR_MACID << BIT_SHIFT_PKT_TRANS_ERR_MACID)\n#define BIT_CLEAR_PKT_TRANS_ERR_MACID(x) ((x) & (~BITS_PKT_TRANS_ERR_MACID))\n#define BIT_GET_PKT_TRANS_ERR_MACID(x)                                         \\\n\t(((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID) & BIT_MASK_PKT_TRANS_ERR_MACID)\n#define BIT_SET_PKT_TRANS_ERR_MACID(x, v)                                      \\\n\t(BIT_CLEAR_PKT_TRANS_ERR_MACID(x) | BIT_PKT_TRANS_ERR_MACID(v))\n\n/* 2 REG_FWCMDQ_CTRL\t\t\t\t(Offset 0x14A0) */\n\n#define BIT_FW_RELEASEPKT_POLLING BIT(31)\n\n#define BIT_SHIFT_FWCMDQ_RELEASE_HEAD 16\n#define BIT_MASK_FWCMDQ_RELEASE_HEAD 0xfff\n#define BIT_FWCMDQ_RELEASE_HEAD(x)                                             \\\n\t(((x) & BIT_MASK_FWCMDQ_RELEASE_HEAD) << BIT_SHIFT_FWCMDQ_RELEASE_HEAD)\n#define BITS_FWCMDQ_RELEASE_HEAD                                               \\\n\t(BIT_MASK_FWCMDQ_RELEASE_HEAD << BIT_SHIFT_FWCMDQ_RELEASE_HEAD)\n#define BIT_CLEAR_FWCMDQ_RELEASE_HEAD(x) ((x) & (~BITS_FWCMDQ_RELEASE_HEAD))\n#define BIT_GET_FWCMDQ_RELEASE_HEAD(x)                                         \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_RELEASE_HEAD) & BIT_MASK_FWCMDQ_RELEASE_HEAD)\n#define BIT_SET_FWCMDQ_RELEASE_HEAD(x, v)                                      \\\n\t(BIT_CLEAR_FWCMDQ_RELEASE_HEAD(x) | BIT_FWCMDQ_RELEASE_HEAD(v))\n\n#define BIT_FW_GETPKTT_POLLING BIT(15)\n\n#define BIT_SHIFT_FWCMDQ_H 0\n#define BIT_MASK_FWCMDQ_H 0xfff\n#define BIT_FWCMDQ_H(x) (((x) & BIT_MASK_FWCMDQ_H) << BIT_SHIFT_FWCMDQ_H)\n#define BITS_FWCMDQ_H (BIT_MASK_FWCMDQ_H << BIT_SHIFT_FWCMDQ_H)\n#define BIT_CLEAR_FWCMDQ_H(x) ((x) & (~BITS_FWCMDQ_H))\n#define BIT_GET_FWCMDQ_H(x) (((x) >> BIT_SHIFT_FWCMDQ_H) & BIT_MASK_FWCMDQ_H)\n#define BIT_SET_FWCMDQ_H(x, v) (BIT_CLEAR_FWCMDQ_H(x) | BIT_FWCMDQ_H(v))\n\n/* 2 REG_FWCMDQ_PAGE\t\t\t\t(Offset 0x14A4) */\n\n#define BIT_SHIFT_FWCMDQ_TOTAL_PAGE 16\n#define BIT_MASK_FWCMDQ_TOTAL_PAGE 0xfff\n#define BIT_FWCMDQ_TOTAL_PAGE(x)                                               \\\n\t(((x) & BIT_MASK_FWCMDQ_TOTAL_PAGE) << BIT_SHIFT_FWCMDQ_TOTAL_PAGE)\n#define BITS_FWCMDQ_TOTAL_PAGE                                                 \\\n\t(BIT_MASK_FWCMDQ_TOTAL_PAGE << BIT_SHIFT_FWCMDQ_TOTAL_PAGE)\n#define BIT_CLEAR_FWCMDQ_TOTAL_PAGE(x) ((x) & (~BITS_FWCMDQ_TOTAL_PAGE))\n#define BIT_GET_FWCMDQ_TOTAL_PAGE(x)                                           \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PAGE) & BIT_MASK_FWCMDQ_TOTAL_PAGE)\n#define BIT_SET_FWCMDQ_TOTAL_PAGE(x, v)                                        \\\n\t(BIT_CLEAR_FWCMDQ_TOTAL_PAGE(x) | BIT_FWCMDQ_TOTAL_PAGE(v))\n\n#define BIT_SHIFT_FWCMDQ_QUEUE_PAGE 0\n#define BIT_MASK_FWCMDQ_QUEUE_PAGE 0xfff\n#define BIT_FWCMDQ_QUEUE_PAGE(x)                                               \\\n\t(((x) & BIT_MASK_FWCMDQ_QUEUE_PAGE) << BIT_SHIFT_FWCMDQ_QUEUE_PAGE)\n#define BITS_FWCMDQ_QUEUE_PAGE                                                 \\\n\t(BIT_MASK_FWCMDQ_QUEUE_PAGE << BIT_SHIFT_FWCMDQ_QUEUE_PAGE)\n#define BIT_CLEAR_FWCMDQ_QUEUE_PAGE(x) ((x) & (~BITS_FWCMDQ_QUEUE_PAGE))\n#define BIT_GET_FWCMDQ_QUEUE_PAGE(x)                                           \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PAGE) & BIT_MASK_FWCMDQ_QUEUE_PAGE)\n#define BIT_SET_FWCMDQ_QUEUE_PAGE(x, v)                                        \\\n\t(BIT_CLEAR_FWCMDQ_QUEUE_PAGE(x) | BIT_FWCMDQ_QUEUE_PAGE(v))\n\n/* 2 REG_FWCMDQ_INFO\t\t\t\t(Offset 0x14A8) */\n\n#define BIT_FWCMD_READY BIT(31)\n#define BIT_FWCMDQ_OVERFLOW BIT(30)\n#define BIT_FWCMDQ_UNDERFLOW BIT(29)\n#define BIT_FWCMDQ_RELEASE_MISS BIT(28)\n\n#define BIT_SHIFT_FWCMDQ_TOTAL_PKT 16\n#define BIT_MASK_FWCMDQ_TOTAL_PKT 0xfff\n#define BIT_FWCMDQ_TOTAL_PKT(x)                                                \\\n\t(((x) & BIT_MASK_FWCMDQ_TOTAL_PKT) << BIT_SHIFT_FWCMDQ_TOTAL_PKT)\n#define BITS_FWCMDQ_TOTAL_PKT                                                  \\\n\t(BIT_MASK_FWCMDQ_TOTAL_PKT << BIT_SHIFT_FWCMDQ_TOTAL_PKT)\n#define BIT_CLEAR_FWCMDQ_TOTAL_PKT(x) ((x) & (~BITS_FWCMDQ_TOTAL_PKT))\n#define BIT_GET_FWCMDQ_TOTAL_PKT(x)                                            \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PKT) & BIT_MASK_FWCMDQ_TOTAL_PKT)\n#define BIT_SET_FWCMDQ_TOTAL_PKT(x, v)                                         \\\n\t(BIT_CLEAR_FWCMDQ_TOTAL_PKT(x) | BIT_FWCMDQ_TOTAL_PKT(v))\n\n#define BIT_SHIFT_FWCMDQ_QUEUE_PKT 0\n#define BIT_MASK_FWCMDQ_QUEUE_PKT 0xfff\n#define BIT_FWCMDQ_QUEUE_PKT(x)                                                \\\n\t(((x) & BIT_MASK_FWCMDQ_QUEUE_PKT) << BIT_SHIFT_FWCMDQ_QUEUE_PKT)\n#define BITS_FWCMDQ_QUEUE_PKT                                                  \\\n\t(BIT_MASK_FWCMDQ_QUEUE_PKT << BIT_SHIFT_FWCMDQ_QUEUE_PKT)\n#define BIT_CLEAR_FWCMDQ_QUEUE_PKT(x) ((x) & (~BITS_FWCMDQ_QUEUE_PKT))\n#define BIT_GET_FWCMDQ_QUEUE_PKT(x)                                            \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PKT) & BIT_MASK_FWCMDQ_QUEUE_PKT)\n#define BIT_SET_FWCMDQ_QUEUE_PKT(x, v)                                         \\\n\t(BIT_CLEAR_FWCMDQ_QUEUE_PKT(x) | BIT_FWCMDQ_QUEUE_PKT(v))\n\n/* 2 REG_FWCMDQ_HOLD_PKTNUM\t\t\t(Offset 0x14AC) */\n\n#define BIT_SHIFT_FWCMDQ_HOLD__PKTNUM 0\n#define BIT_MASK_FWCMDQ_HOLD__PKTNUM 0xfff\n#define BIT_FWCMDQ_HOLD__PKTNUM(x)                                             \\\n\t(((x) & BIT_MASK_FWCMDQ_HOLD__PKTNUM) << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM)\n#define BITS_FWCMDQ_HOLD__PKTNUM                                               \\\n\t(BIT_MASK_FWCMDQ_HOLD__PKTNUM << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM)\n#define BIT_CLEAR_FWCMDQ_HOLD__PKTNUM(x) ((x) & (~BITS_FWCMDQ_HOLD__PKTNUM))\n#define BIT_GET_FWCMDQ_HOLD__PKTNUM(x)                                         \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_HOLD__PKTNUM) & BIT_MASK_FWCMDQ_HOLD__PKTNUM)\n#define BIT_SET_FWCMDQ_HOLD__PKTNUM(x, v)                                      \\\n\t(BIT_CLEAR_FWCMDQ_HOLD__PKTNUM(x) | BIT_FWCMDQ_HOLD__PKTNUM(v))\n\n/* 2 REG_MU_TX_CTRL\t\t\t\t(Offset 0x14C0) */\n\n#define BIT_SEARCH_DONE_RDY BIT(31)\n#define BIT_MU_EN BIT(30)\n#define BIT_MU_SECONDARY_WAITMODE_EN BIT(29)\n#define BIT_MU_BB_SCORE_EN BIT(28)\n#define BIT_MU_SECONDARY_ANT_COUNT_EN BIT(27)\n#define BIT_MUARB_SEARCH_ERR_EN BIT(26)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MU_TX_CTL\t\t\t\t(Offset 0x14C0) */\n\n#define BIT_R_MU_P1_WAIT_STATE_EN BIT(16)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MU_TX_CTRL\t\t\t\t(Offset 0x14C0) */\n\n#define BIT_SHIFT_DIS_SU_TXBF 16\n#define BIT_MASK_DIS_SU_TXBF 0x3f\n#define BIT_DIS_SU_TXBF(x)                                                     \\\n\t(((x) & BIT_MASK_DIS_SU_TXBF) << BIT_SHIFT_DIS_SU_TXBF)\n#define BITS_DIS_SU_TXBF (BIT_MASK_DIS_SU_TXBF << BIT_SHIFT_DIS_SU_TXBF)\n#define BIT_CLEAR_DIS_SU_TXBF(x) ((x) & (~BITS_DIS_SU_TXBF))\n#define BIT_GET_DIS_SU_TXBF(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DIS_SU_TXBF) & BIT_MASK_DIS_SU_TXBF)\n#define BIT_SET_DIS_SU_TXBF(x, v)                                              \\\n\t(BIT_CLEAR_DIS_SU_TXBF(x) | BIT_DIS_SU_TXBF(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MU_TX_CTL\t\t\t\t(Offset 0x14C0) */\n\n#define BIT_SHIFT_R_MU_RL 12\n#define BIT_MASK_R_MU_RL 0xf\n#define BIT_R_MU_RL(x) (((x) & BIT_MASK_R_MU_RL) << BIT_SHIFT_R_MU_RL)\n#define BITS_R_MU_RL (BIT_MASK_R_MU_RL << BIT_SHIFT_R_MU_RL)\n#define BIT_CLEAR_R_MU_RL(x) ((x) & (~BITS_R_MU_RL))\n#define BIT_GET_R_MU_RL(x) (((x) >> BIT_SHIFT_R_MU_RL) & BIT_MASK_R_MU_RL)\n#define BIT_SET_R_MU_RL(x, v) (BIT_CLEAR_R_MU_RL(x) | BIT_R_MU_RL(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MU_TX_CTRL\t\t\t\t(Offset 0x14C0) */\n\n#define BIT_SHIFT_MU_RL 12\n#define BIT_MASK_MU_RL 0xf\n#define BIT_MU_RL(x) (((x) & BIT_MASK_MU_RL) << BIT_SHIFT_MU_RL)\n#define BITS_MU_RL (BIT_MASK_MU_RL << BIT_SHIFT_MU_RL)\n#define BIT_CLEAR_MU_RL(x) ((x) & (~BITS_MU_RL))\n#define BIT_GET_MU_RL(x) (((x) >> BIT_SHIFT_MU_RL) & BIT_MASK_MU_RL)\n#define BIT_SET_MU_RL(x, v) (BIT_CLEAR_MU_RL(x) | BIT_MU_RL(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MU_TX_CTL\t\t\t\t(Offset 0x14C0) */\n\n#define BIT_R_FORCE_P1_RATEDOWN BIT(11)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MU_TX_CTL\t\t\t\t(Offset 0x14C0) */\n\n#define BIT_SHIFT_R_MU_TAB_SEL 8\n#define BIT_MASK_R_MU_TAB_SEL 0x7\n#define BIT_R_MU_TAB_SEL(x)                                                    \\\n\t(((x) & BIT_MASK_R_MU_TAB_SEL) << BIT_SHIFT_R_MU_TAB_SEL)\n#define BITS_R_MU_TAB_SEL (BIT_MASK_R_MU_TAB_SEL << BIT_SHIFT_R_MU_TAB_SEL)\n#define BIT_CLEAR_R_MU_TAB_SEL(x) ((x) & (~BITS_R_MU_TAB_SEL))\n#define BIT_GET_R_MU_TAB_SEL(x)                                                \\\n\t(((x) >> BIT_SHIFT_R_MU_TAB_SEL) & BIT_MASK_R_MU_TAB_SEL)\n#define BIT_SET_R_MU_TAB_SEL(x, v)                                             \\\n\t(BIT_CLEAR_R_MU_TAB_SEL(x) | BIT_R_MU_TAB_SEL(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MU_TX_CTRL\t\t\t\t(Offset 0x14C0) */\n\n#define BIT_SHIFT_MU_TAB_SEL 8\n#define BIT_MASK_MU_TAB_SEL 0xf\n#define BIT_MU_TAB_SEL(x) (((x) & BIT_MASK_MU_TAB_SEL) << BIT_SHIFT_MU_TAB_SEL)\n#define BITS_MU_TAB_SEL (BIT_MASK_MU_TAB_SEL << BIT_SHIFT_MU_TAB_SEL)\n#define BIT_CLEAR_MU_TAB_SEL(x) ((x) & (~BITS_MU_TAB_SEL))\n#define BIT_GET_MU_TAB_SEL(x)                                                  \\\n\t(((x) >> BIT_SHIFT_MU_TAB_SEL) & BIT_MASK_MU_TAB_SEL)\n#define BIT_SET_MU_TAB_SEL(x, v) (BIT_CLEAR_MU_TAB_SEL(x) | BIT_MU_TAB_SEL(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MU_TX_CTL\t\t\t\t(Offset 0x14C0) */\n\n#define BIT_R_EN_MU_MIMO BIT(7)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MU_TX_CTL\t\t\t\t(Offset 0x14C0) */\n\n#define BIT_R_EN_REVERS_GTAB BIT(6)\n\n#define BIT_SHIFT_R_MU_TABLE_VALID 0\n#define BIT_MASK_R_MU_TABLE_VALID 0x3f\n#define BIT_R_MU_TABLE_VALID(x)                                                \\\n\t(((x) & BIT_MASK_R_MU_TABLE_VALID) << BIT_SHIFT_R_MU_TABLE_VALID)\n#define BITS_R_MU_TABLE_VALID                                                  \\\n\t(BIT_MASK_R_MU_TABLE_VALID << BIT_SHIFT_R_MU_TABLE_VALID)\n#define BIT_CLEAR_R_MU_TABLE_VALID(x) ((x) & (~BITS_R_MU_TABLE_VALID))\n#define BIT_GET_R_MU_TABLE_VALID(x)                                            \\\n\t(((x) >> BIT_SHIFT_R_MU_TABLE_VALID) & BIT_MASK_R_MU_TABLE_VALID)\n#define BIT_SET_R_MU_TABLE_VALID(x, v)                                         \\\n\t(BIT_CLEAR_R_MU_TABLE_VALID(x) | BIT_R_MU_TABLE_VALID(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MU_TX_CTRL\t\t\t\t(Offset 0x14C0) */\n\n#define BIT_SHIFT_MU_TAB_VALID 0\n#define BIT_MASK_MU_TAB_VALID 0x3f\n#define BIT_MU_TAB_VALID(x)                                                    \\\n\t(((x) & BIT_MASK_MU_TAB_VALID) << BIT_SHIFT_MU_TAB_VALID)\n#define BITS_MU_TAB_VALID (BIT_MASK_MU_TAB_VALID << BIT_SHIFT_MU_TAB_VALID)\n#define BIT_CLEAR_MU_TAB_VALID(x) ((x) & (~BITS_MU_TAB_VALID))\n#define BIT_GET_MU_TAB_VALID(x)                                                \\\n\t(((x) >> BIT_SHIFT_MU_TAB_VALID) & BIT_MASK_MU_TAB_VALID)\n#define BIT_SET_MU_TAB_VALID(x, v)                                             \\\n\t(BIT_CLEAR_MU_TAB_VALID(x) | BIT_MU_TAB_VALID(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MU_STA_GID_VLD\t\t\t(Offset 0x14C4) */\n\n#define BIT_SHIFT_R_MU_STA_GTAB_VALID 0\n#define BIT_MASK_R_MU_STA_GTAB_VALID 0xffffffffL\n#define BIT_R_MU_STA_GTAB_VALID(x)                                             \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_VALID) << BIT_SHIFT_R_MU_STA_GTAB_VALID)\n#define BITS_R_MU_STA_GTAB_VALID                                               \\\n\t(BIT_MASK_R_MU_STA_GTAB_VALID << BIT_SHIFT_R_MU_STA_GTAB_VALID)\n#define BIT_CLEAR_R_MU_STA_GTAB_VALID(x) ((x) & (~BITS_R_MU_STA_GTAB_VALID))\n#define BIT_GET_R_MU_STA_GTAB_VALID(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID) & BIT_MASK_R_MU_STA_GTAB_VALID)\n#define BIT_SET_R_MU_STA_GTAB_VALID(x, v)                                      \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_VALID(x) | BIT_R_MU_STA_GTAB_VALID(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MU_STA_GID_VLD\t\t\t(Offset 0x14C4) */\n\n#define BIT_SHIFT_MU_STA_GTAB_VALID 0\n#define BIT_MASK_MU_STA_GTAB_VALID 0xffffffffL\n#define BIT_MU_STA_GTAB_VALID(x)                                               \\\n\t(((x) & BIT_MASK_MU_STA_GTAB_VALID) << BIT_SHIFT_MU_STA_GTAB_VALID)\n#define BITS_MU_STA_GTAB_VALID                                                 \\\n\t(BIT_MASK_MU_STA_GTAB_VALID << BIT_SHIFT_MU_STA_GTAB_VALID)\n#define BIT_CLEAR_MU_STA_GTAB_VALID(x) ((x) & (~BITS_MU_STA_GTAB_VALID))\n#define BIT_GET_MU_STA_GTAB_VALID(x)                                           \\\n\t(((x) >> BIT_SHIFT_MU_STA_GTAB_VALID) & BIT_MASK_MU_STA_GTAB_VALID)\n#define BIT_SET_MU_STA_GTAB_VALID(x, v)                                        \\\n\t(BIT_CLEAR_MU_STA_GTAB_VALID(x) | BIT_MU_STA_GTAB_VALID(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MU_STA_USER_POS_INFO\t\t(Offset 0x14C8) */\n\n#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_L 0\n#define BIT_MASK_R_MU_STA_GTAB_POSITION_L 0xffffffffL\n#define BIT_R_MU_STA_GTAB_POSITION_L(x)                                        \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_L)                             \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L)\n#define BITS_R_MU_STA_GTAB_POSITION_L                                          \\\n\t(BIT_MASK_R_MU_STA_GTAB_POSITION_L                                     \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L)\n#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_L(x)                                  \\\n\t((x) & (~BITS_R_MU_STA_GTAB_POSITION_L))\n#define BIT_GET_R_MU_STA_GTAB_POSITION_L(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_L) &                         \\\n\t BIT_MASK_R_MU_STA_GTAB_POSITION_L)\n#define BIT_SET_R_MU_STA_GTAB_POSITION_L(x, v)                                 \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_POSITION_L(x) |                               \\\n\t BIT_R_MU_STA_GTAB_POSITION_L(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MU_STA_USER_POS_INFO\t\t(Offset 0x14C8) */\n\n#define BIT_SHIFT_MU_STA_GTAB_POSITION_L 0\n#define BIT_MASK_MU_STA_GTAB_POSITION_L 0xffffffffL\n#define BIT_MU_STA_GTAB_POSITION_L(x)                                          \\\n\t(((x) & BIT_MASK_MU_STA_GTAB_POSITION_L)                               \\\n\t << BIT_SHIFT_MU_STA_GTAB_POSITION_L)\n#define BITS_MU_STA_GTAB_POSITION_L                                            \\\n\t(BIT_MASK_MU_STA_GTAB_POSITION_L << BIT_SHIFT_MU_STA_GTAB_POSITION_L)\n#define BIT_CLEAR_MU_STA_GTAB_POSITION_L(x)                                    \\\n\t((x) & (~BITS_MU_STA_GTAB_POSITION_L))\n#define BIT_GET_MU_STA_GTAB_POSITION_L(x)                                      \\\n\t(((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_L) &                           \\\n\t BIT_MASK_MU_STA_GTAB_POSITION_L)\n#define BIT_SET_MU_STA_GTAB_POSITION_L(x, v)                                   \\\n\t(BIT_CLEAR_MU_STA_GTAB_POSITION_L(x) | BIT_MU_STA_GTAB_POSITION_L(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MU_STA_USER_POS_INFO_H\t\t(Offset 0x14CC) */\n\n#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_H 0\n#define BIT_MASK_R_MU_STA_GTAB_POSITION_H 0xffffffffL\n#define BIT_R_MU_STA_GTAB_POSITION_H(x)                                        \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_H)                             \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H)\n#define BITS_R_MU_STA_GTAB_POSITION_H                                          \\\n\t(BIT_MASK_R_MU_STA_GTAB_POSITION_H                                     \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H)\n#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_H(x)                                  \\\n\t((x) & (~BITS_R_MU_STA_GTAB_POSITION_H))\n#define BIT_GET_R_MU_STA_GTAB_POSITION_H(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_H) &                         \\\n\t BIT_MASK_R_MU_STA_GTAB_POSITION_H)\n#define BIT_SET_R_MU_STA_GTAB_POSITION_H(x, v)                                 \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_POSITION_H(x) |                               \\\n\t BIT_R_MU_STA_GTAB_POSITION_H(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MU_STA_USER_POS_INFO_H\t\t(Offset 0x14CC) */\n\n#define BIT_SHIFT_MU_STA_GTAB_POSITION_H 0\n#define BIT_MASK_MU_STA_GTAB_POSITION_H 0xffffffffL\n#define BIT_MU_STA_GTAB_POSITION_H(x)                                          \\\n\t(((x) & BIT_MASK_MU_STA_GTAB_POSITION_H)                               \\\n\t << BIT_SHIFT_MU_STA_GTAB_POSITION_H)\n#define BITS_MU_STA_GTAB_POSITION_H                                            \\\n\t(BIT_MASK_MU_STA_GTAB_POSITION_H << BIT_SHIFT_MU_STA_GTAB_POSITION_H)\n#define BIT_CLEAR_MU_STA_GTAB_POSITION_H(x)                                    \\\n\t((x) & (~BITS_MU_STA_GTAB_POSITION_H))\n#define BIT_GET_MU_STA_GTAB_POSITION_H(x)                                      \\\n\t(((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_H) &                           \\\n\t BIT_MASK_MU_STA_GTAB_POSITION_H)\n#define BIT_SET_MU_STA_GTAB_POSITION_H(x, v)                                   \\\n\t(BIT_CLEAR_MU_STA_GTAB_POSITION_H(x) | BIT_MU_STA_GTAB_POSITION_H(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MU_TRX_DBG_CNT\t\t\t(Offset 0x14D0) */\n\n#define BIT_MU_DNGCNT_RST BIT(20)\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_MU_TRX_DBG_CNT\t\t\t(Offset 0x14D0) */\n\n#define BIT_SHIFT_MU_DBGCNT_SEL 16\n#define BIT_MASK_MU_DBGCNT_SEL 0xf\n#define BIT_MU_DBGCNT_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_MU_DBGCNT_SEL) << BIT_SHIFT_MU_DBGCNT_SEL)\n#define BITS_MU_DBGCNT_SEL (BIT_MASK_MU_DBGCNT_SEL << BIT_SHIFT_MU_DBGCNT_SEL)\n#define BIT_CLEAR_MU_DBGCNT_SEL(x) ((x) & (~BITS_MU_DBGCNT_SEL))\n#define BIT_GET_MU_DBGCNT_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_MU_DBGCNT_SEL) & BIT_MASK_MU_DBGCNT_SEL)\n#define BIT_SET_MU_DBGCNT_SEL(x, v)                                            \\\n\t(BIT_CLEAR_MU_DBGCNT_SEL(x) | BIT_MU_DBGCNT_SEL(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CHNL_INFO_CTRL\t\t\t(Offset 0x14D0) */\n\n#define BIT_CHNL_REF_RXNAV BIT(7)\n#define BIT_CHNL_REF_VBON BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_CHNL_INFO_CTRL\t\t\t(Offset 0x14D0) */\n\n#define BIT_CHNL_REF_EDCCA BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CHNL_INFO_CTRL\t\t\t(Offset 0x14D0) */\n\n#define BIT_CHNL_REF_CCA BIT(4)\n#define BIT_MACTX_ERR_4 BIT(4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CHNL_INFO_CTRL\t\t\t(Offset 0x14D0) */\n\n#define BIT_RST_CHNL_BUSY BIT(3)\n#define BIT_RST_CHNL_IDLE BIT(2)\n#define BIT_CHNL_INFO_RST BIT(1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CHNL_INFO_CTRL\t\t\t(Offset 0x14D0) */\n\n#define BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD 1\n#define BIT_MASK_VHTHT_MIMO_CTRL_FIELD 0xffffff\n#define BIT_VHTHT_MIMO_CTRL_FIELD(x)                                           \\\n\t(((x) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD)                                \\\n\t << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD)\n#define BITS_VHTHT_MIMO_CTRL_FIELD                                             \\\n\t(BIT_MASK_VHTHT_MIMO_CTRL_FIELD << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD)\n#define BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD(x) ((x) & (~BITS_VHTHT_MIMO_CTRL_FIELD))\n#define BIT_GET_VHTHT_MIMO_CTRL_FIELD(x)                                       \\\n\t(((x) >> BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD) &                            \\\n\t BIT_MASK_VHTHT_MIMO_CTRL_FIELD)\n#define BIT_SET_VHTHT_MIMO_CTRL_FIELD(x, v)                                    \\\n\t(BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD(x) | BIT_VHTHT_MIMO_CTRL_FIELD(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CHNL_INFO_CTRL\t\t\t(Offset 0x14D0) */\n\n#define BIT_ATM_AIRTIME_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CHNL_INFO_CTRL\t\t\t(Offset 0x14D0) */\n\n#define BIT_CSI_INTERRUPT_STATUS BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MU_TRX_DBG_CNT\t\t\t(Offset 0x14D0) */\n\n#define BIT_SHIFT_MU_DNGCNT 0\n#define BIT_MASK_MU_DNGCNT 0xffff\n#define BIT_MU_DNGCNT(x) (((x) & BIT_MASK_MU_DNGCNT) << BIT_SHIFT_MU_DNGCNT)\n#define BITS_MU_DNGCNT (BIT_MASK_MU_DNGCNT << BIT_SHIFT_MU_DNGCNT)\n#define BIT_CLEAR_MU_DNGCNT(x) ((x) & (~BITS_MU_DNGCNT))\n#define BIT_GET_MU_DNGCNT(x) (((x) >> BIT_SHIFT_MU_DNGCNT) & BIT_MASK_MU_DNGCNT)\n#define BIT_SET_MU_DNGCNT(x, v) (BIT_CLEAR_MU_DNGCNT(x) | BIT_MU_DNGCNT(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CHNL_BUSY_TIME\t\t\t(Offset 0x14D8) */\n\n#define BIT_SHIFT_CHNL_BUSY_TIME 0\n#define BIT_MASK_CHNL_BUSY_TIME 0xffffffffL\n#define BIT_CHNL_BUSY_TIME(x)                                                  \\\n\t(((x) & BIT_MASK_CHNL_BUSY_TIME) << BIT_SHIFT_CHNL_BUSY_TIME)\n#define BITS_CHNL_BUSY_TIME                                                    \\\n\t(BIT_MASK_CHNL_BUSY_TIME << BIT_SHIFT_CHNL_BUSY_TIME)\n#define BIT_CLEAR_CHNL_BUSY_TIME(x) ((x) & (~BITS_CHNL_BUSY_TIME))\n#define BIT_GET_CHNL_BUSY_TIME(x)                                              \\\n\t(((x) >> BIT_SHIFT_CHNL_BUSY_TIME) & BIT_MASK_CHNL_BUSY_TIME)\n#define BIT_SET_CHNL_BUSY_TIME(x, v)                                           \\\n\t(BIT_CLEAR_CHNL_BUSY_TIME(x) | BIT_CHNL_BUSY_TIME(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MU_TRX_DBG_CNT_V1\t\t\t(Offset 0x14DC) */\n\n#define BIT_FORCE_SND_STS_EN BIT(31)\n\n#define BIT_SHIFT_SND_STS_VALUE 24\n#define BIT_MASK_SND_STS_VALUE 0x3f\n#define BIT_SND_STS_VALUE(x)                                                   \\\n\t(((x) & BIT_MASK_SND_STS_VALUE) << BIT_SHIFT_SND_STS_VALUE)\n#define BITS_SND_STS_VALUE (BIT_MASK_SND_STS_VALUE << BIT_SHIFT_SND_STS_VALUE)\n#define BIT_CLEAR_SND_STS_VALUE(x) ((x) & (~BITS_SND_STS_VALUE))\n#define BIT_GET_SND_STS_VALUE(x)                                               \\\n\t(((x) >> BIT_SHIFT_SND_STS_VALUE) & BIT_MASK_SND_STS_VALUE)\n#define BIT_SET_SND_STS_VALUE(x, v)                                            \\\n\t(BIT_CLEAR_SND_STS_VALUE(x) | BIT_SND_STS_VALUE(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MU_TRX_DBG_CNT_V1\t\t\t(Offset 0x14DC) */\n\n#define BIT_SHIFT_MU_DNGCNT_SEL 16\n#define BIT_MASK_MU_DNGCNT_SEL 0xf\n#define BIT_MU_DNGCNT_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_MU_DNGCNT_SEL) << BIT_SHIFT_MU_DNGCNT_SEL)\n#define BITS_MU_DNGCNT_SEL (BIT_MASK_MU_DNGCNT_SEL << BIT_SHIFT_MU_DNGCNT_SEL)\n#define BIT_CLEAR_MU_DNGCNT_SEL(x) ((x) & (~BITS_MU_DNGCNT_SEL))\n#define BIT_GET_MU_DNGCNT_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_MU_DNGCNT_SEL) & BIT_MASK_MU_DNGCNT_SEL)\n#define BIT_SET_MU_DNGCNT_SEL(x, v)                                            \\\n\t(BIT_CLEAR_MU_DNGCNT_SEL(x) | BIT_MU_DNGCNT_SEL(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n/* 2 REG_SU_DURATION\t\t\t\t(Offset 0x14F0) */\n\n#define BIT_SHIFT_SU_DURATION 0\n#define BIT_MASK_SU_DURATION 0xffff\n#define BIT_SU_DURATION(x)                                                     \\\n\t(((x) & BIT_MASK_SU_DURATION) << BIT_SHIFT_SU_DURATION)\n#define BITS_SU_DURATION (BIT_MASK_SU_DURATION << BIT_SHIFT_SU_DURATION)\n#define BIT_CLEAR_SU_DURATION(x) ((x) & (~BITS_SU_DURATION))\n#define BIT_GET_SU_DURATION(x)                                                 \\\n\t(((x) >> BIT_SHIFT_SU_DURATION) & BIT_MASK_SU_DURATION)\n#define BIT_SET_SU_DURATION(x, v)                                              \\\n\t(BIT_CLEAR_SU_DURATION(x) | BIT_SU_DURATION(v))\n\n/* 2 REG_MU_DURATION\t\t\t\t(Offset 0x14F2) */\n\n#define BIT_SHIFT_MU_DURATION 0\n#define BIT_MASK_MU_DURATION 0xffff\n#define BIT_MU_DURATION(x)                                                     \\\n\t(((x) & BIT_MASK_MU_DURATION) << BIT_SHIFT_MU_DURATION)\n#define BITS_MU_DURATION (BIT_MASK_MU_DURATION << BIT_SHIFT_MU_DURATION)\n#define BIT_CLEAR_MU_DURATION(x) ((x) & (~BITS_MU_DURATION))\n#define BIT_GET_MU_DURATION(x)                                                 \\\n\t(((x) >> BIT_SHIFT_MU_DURATION) & BIT_MASK_MU_DURATION)\n#define BIT_SET_MU_DURATION(x, v)                                              \\\n\t(BIT_CLEAR_MU_DURATION(x) | BIT_MU_DURATION(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_SWPS_CTRL\t\t\t\t(Offset 0x14F4) */\n\n#define BIT_SHIFT_SWPS_PKT_TH_V1 16\n#define BIT_MASK_SWPS_PKT_TH_V1 0xffff\n#define BIT_SWPS_PKT_TH_V1(x)                                                  \\\n\t(((x) & BIT_MASK_SWPS_PKT_TH_V1) << BIT_SHIFT_SWPS_PKT_TH_V1)\n#define BITS_SWPS_PKT_TH_V1                                                    \\\n\t(BIT_MASK_SWPS_PKT_TH_V1 << BIT_SHIFT_SWPS_PKT_TH_V1)\n#define BIT_CLEAR_SWPS_PKT_TH_V1(x) ((x) & (~BITS_SWPS_PKT_TH_V1))\n#define BIT_GET_SWPS_PKT_TH_V1(x)                                              \\\n\t(((x) >> BIT_SHIFT_SWPS_PKT_TH_V1) & BIT_MASK_SWPS_PKT_TH_V1)\n#define BIT_SET_SWPS_PKT_TH_V1(x, v)                                           \\\n\t(BIT_CLEAR_SWPS_PKT_TH_V1(x) | BIT_SWPS_PKT_TH_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SWPS_CTRL\t\t\t\t(Offset 0x14F4) */\n\n#define BIT_SHIFT_SWPS_RPT_LENGTH 8\n#define BIT_MASK_SWPS_RPT_LENGTH 0x7f\n#define BIT_SWPS_RPT_LENGTH(x)                                                 \\\n\t(((x) & BIT_MASK_SWPS_RPT_LENGTH) << BIT_SHIFT_SWPS_RPT_LENGTH)\n#define BITS_SWPS_RPT_LENGTH                                                   \\\n\t(BIT_MASK_SWPS_RPT_LENGTH << BIT_SHIFT_SWPS_RPT_LENGTH)\n#define BIT_CLEAR_SWPS_RPT_LENGTH(x) ((x) & (~BITS_SWPS_RPT_LENGTH))\n#define BIT_GET_SWPS_RPT_LENGTH(x)                                             \\\n\t(((x) >> BIT_SHIFT_SWPS_RPT_LENGTH) & BIT_MASK_SWPS_RPT_LENGTH)\n#define BIT_SET_SWPS_RPT_LENGTH(x, v)                                          \\\n\t(BIT_CLEAR_SWPS_RPT_LENGTH(x) | BIT_SWPS_RPT_LENGTH(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SWPS_CTRL\t\t\t\t(Offset 0x14F4) */\n\n#define BIT_SHIFT_MACID_SWPS_EN_SEL 2\n#define BIT_MASK_MACID_SWPS_EN_SEL 0x3\n#define BIT_MACID_SWPS_EN_SEL(x)                                               \\\n\t(((x) & BIT_MASK_MACID_SWPS_EN_SEL) << BIT_SHIFT_MACID_SWPS_EN_SEL)\n#define BITS_MACID_SWPS_EN_SEL                                                 \\\n\t(BIT_MASK_MACID_SWPS_EN_SEL << BIT_SHIFT_MACID_SWPS_EN_SEL)\n#define BIT_CLEAR_MACID_SWPS_EN_SEL(x) ((x) & (~BITS_MACID_SWPS_EN_SEL))\n#define BIT_GET_MACID_SWPS_EN_SEL(x)                                           \\\n\t(((x) >> BIT_SHIFT_MACID_SWPS_EN_SEL) & BIT_MASK_MACID_SWPS_EN_SEL)\n#define BIT_SET_MACID_SWPS_EN_SEL(x, v)                                        \\\n\t(BIT_CLEAR_MACID_SWPS_EN_SEL(x) | BIT_MACID_SWPS_EN_SEL(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_SWPS_CTRL\t\t\t\t(Offset 0x14F4) */\n\n#define BIT_MACID_SWPS_EN_SEL_V1 BIT(2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SWPS_CTRL\t\t\t\t(Offset 0x14F4) */\n\n#define BIT_SWPS_MANUALL_POLLING BIT(1)\n#define BIT_SWPS_EN BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n/* 2 REG_HW_NDPA_RTY_LIMIT\t\t\t(Offset 0x14F4) */\n\n#define BIT_SHIFT_HW_NDPA_RTY_LIMIT 0\n#define BIT_MASK_HW_NDPA_RTY_LIMIT 0xf\n#define BIT_HW_NDPA_RTY_LIMIT(x)                                               \\\n\t(((x) & BIT_MASK_HW_NDPA_RTY_LIMIT) << BIT_SHIFT_HW_NDPA_RTY_LIMIT)\n#define BITS_HW_NDPA_RTY_LIMIT                                                 \\\n\t(BIT_MASK_HW_NDPA_RTY_LIMIT << BIT_SHIFT_HW_NDPA_RTY_LIMIT)\n#define BIT_CLEAR_HW_NDPA_RTY_LIMIT(x) ((x) & (~BITS_HW_NDPA_RTY_LIMIT))\n#define BIT_GET_HW_NDPA_RTY_LIMIT(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_NDPA_RTY_LIMIT) & BIT_MASK_HW_NDPA_RTY_LIMIT)\n#define BIT_SET_HW_NDPA_RTY_LIMIT(x, v)                                        \\\n\t(BIT_CLEAR_HW_NDPA_RTY_LIMIT(x) | BIT_HW_NDPA_RTY_LIMIT(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT)\n\n/* 2 REG_MACID_SWPS_EN\t\t\t(Offset 0x14FC) */\n\n#define BIT_SHIFT_MACID_SWPS_EN 0\n#define BIT_MASK_MACID_SWPS_EN 0xffffffffL\n#define BIT_MACID_SWPS_EN(x)                                                   \\\n\t(((x) & BIT_MASK_MACID_SWPS_EN) << BIT_SHIFT_MACID_SWPS_EN)\n#define BITS_MACID_SWPS_EN (BIT_MASK_MACID_SWPS_EN << BIT_SHIFT_MACID_SWPS_EN)\n#define BIT_CLEAR_MACID_SWPS_EN(x) ((x) & (~BITS_MACID_SWPS_EN))\n#define BIT_GET_MACID_SWPS_EN(x)                                               \\\n\t(((x) >> BIT_SHIFT_MACID_SWPS_EN) & BIT_MASK_MACID_SWPS_EN)\n#define BIT_SET_MACID_SWPS_EN(x, v)                                            \\\n\t(BIT_CLEAR_MACID_SWPS_EN(x) | BIT_MACID_SWPS_EN(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PORT_CTRL_SEL\t\t\t(Offset 0x1500) */\n\n#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1 4\n#define BIT_MASK_BCN_TIMER_SEL_FWRD_V1 0x7\n#define BIT_BCN_TIMER_SEL_FWRD_V1(x)                                           \\\n\t(((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_V1)                                \\\n\t << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1)\n#define BITS_BCN_TIMER_SEL_FWRD_V1                                             \\\n\t(BIT_MASK_BCN_TIMER_SEL_FWRD_V1 << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1)\n#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1(x) ((x) & (~BITS_BCN_TIMER_SEL_FWRD_V1))\n#define BIT_GET_BCN_TIMER_SEL_FWRD_V1(x)                                       \\\n\t(((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1) &                            \\\n\t BIT_MASK_BCN_TIMER_SEL_FWRD_V1)\n#define BIT_SET_BCN_TIMER_SEL_FWRD_V1(x, v)                                    \\\n\t(BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1(x) | BIT_BCN_TIMER_SEL_FWRD_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CPUMGQ_TX_TIMER\t\t\t(Offset 0x1500) */\n\n#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1 0\n#define BIT_MASK_CPUMGQ_TX_TIMER_V1 0xffffffffL\n#define BIT_CPUMGQ_TX_TIMER_V1(x)                                              \\\n\t(((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1)\n#define BITS_CPUMGQ_TX_TIMER_V1                                                \\\n\t(BIT_MASK_CPUMGQ_TX_TIMER_V1 << BIT_SHIFT_CPUMGQ_TX_TIMER_V1)\n#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_V1))\n#define BIT_GET_CPUMGQ_TX_TIMER_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1) & BIT_MASK_CPUMGQ_TX_TIMER_V1)\n#define BIT_SET_CPUMGQ_TX_TIMER_V1(x, v)                                       \\\n\t(BIT_CLEAR_CPUMGQ_TX_TIMER_V1(x) | BIT_CPUMGQ_TX_TIMER_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_PORT_CTRL_SEL\t\t\t(Offset 0x1500) */\n\n#define BIT_SHIFT_PORT_CTRL_SEL 0\n#define BIT_MASK_PORT_CTRL_SEL 0x7\n#define BIT_PORT_CTRL_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_PORT_CTRL_SEL) << BIT_SHIFT_PORT_CTRL_SEL)\n#define BITS_PORT_CTRL_SEL (BIT_MASK_PORT_CTRL_SEL << BIT_SHIFT_PORT_CTRL_SEL)\n#define BIT_CLEAR_PORT_CTRL_SEL(x) ((x) & (~BITS_PORT_CTRL_SEL))\n#define BIT_GET_PORT_CTRL_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_PORT_CTRL_SEL) & BIT_MASK_PORT_CTRL_SEL)\n#define BIT_SET_PORT_CTRL_SEL(x, v)                                            \\\n\t(BIT_CLEAR_PORT_CTRL_SEL(x) | BIT_PORT_CTRL_SEL(v))\n\n/* 2 REG_PORT_CTRL_CFG\t\t\t(Offset 0x1501) */\n\n#define BIT_BCNERR_CNT_EN_V1 BIT(11)\n#define BIT_DIS_TRX_CAL_BCN_V1 BIT(10)\n#define BIT_DIS_TX_CAL_TBTT_V1 BIT(9)\n#define BIT_BCN_AGGRESSION_V1 BIT(8)\n#define BIT_TSFTR_RST_V1 BIT(7)\n#define BIT_EN_TXBCN_RPT_V1 BIT(5)\n#define BIT_EN_PORT_FUNCTION BIT(3)\n#define BIT_EN_RXBCN_RPT BIT(2)\n\n/* 2 REG_TBTT_PROHIBIT_CFG\t\t\t(Offset 0x1504) */\n\n#define BIT_MASK_PROHIBIT BIT(23)\n\n#define BIT_SHIFT_TBTT_HOLD_TIME 8\n#define BIT_MASK_TBTT_HOLD_TIME 0xfff\n#define BIT_TBTT_HOLD_TIME(x)                                                  \\\n\t(((x) & BIT_MASK_TBTT_HOLD_TIME) << BIT_SHIFT_TBTT_HOLD_TIME)\n#define BITS_TBTT_HOLD_TIME                                                    \\\n\t(BIT_MASK_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME)\n#define BIT_CLEAR_TBTT_HOLD_TIME(x) ((x) & (~BITS_TBTT_HOLD_TIME))\n#define BIT_GET_TBTT_HOLD_TIME(x)                                              \\\n\t(((x) >> BIT_SHIFT_TBTT_HOLD_TIME) & BIT_MASK_TBTT_HOLD_TIME)\n#define BIT_SET_TBTT_HOLD_TIME(x, v)                                           \\\n\t(BIT_CLEAR_TBTT_HOLD_TIME(x) | BIT_TBTT_HOLD_TIME(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PS_TIMER_A\t\t\t\t(Offset 0x1504) */\n\n#define BIT_SHIFT_PS_TIMER_A_V1 0\n#define BIT_MASK_PS_TIMER_A_V1 0xffffffffL\n#define BIT_PS_TIMER_A_V1(x)                                                   \\\n\t(((x) & BIT_MASK_PS_TIMER_A_V1) << BIT_SHIFT_PS_TIMER_A_V1)\n#define BITS_PS_TIMER_A_V1 (BIT_MASK_PS_TIMER_A_V1 << BIT_SHIFT_PS_TIMER_A_V1)\n#define BIT_CLEAR_PS_TIMER_A_V1(x) ((x) & (~BITS_PS_TIMER_A_V1))\n#define BIT_GET_PS_TIMER_A_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_A_V1) & BIT_MASK_PS_TIMER_A_V1)\n#define BIT_SET_PS_TIMER_A_V1(x, v)                                            \\\n\t(BIT_CLEAR_PS_TIMER_A_V1(x) | BIT_PS_TIMER_A_V1(v))\n\n/* 2 REG_PS_TIMER_B\t\t\t\t(Offset 0x1508) */\n\n#define BIT_SHIFT_PS_TIMER_B_V1 0\n#define BIT_MASK_PS_TIMER_B_V1 0xffffffffL\n#define BIT_PS_TIMER_B_V1(x)                                                   \\\n\t(((x) & BIT_MASK_PS_TIMER_B_V1) << BIT_SHIFT_PS_TIMER_B_V1)\n#define BITS_PS_TIMER_B_V1 (BIT_MASK_PS_TIMER_B_V1 << BIT_SHIFT_PS_TIMER_B_V1)\n#define BIT_CLEAR_PS_TIMER_B_V1(x) ((x) & (~BITS_PS_TIMER_B_V1))\n#define BIT_GET_PS_TIMER_B_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_B_V1) & BIT_MASK_PS_TIMER_B_V1)\n#define BIT_SET_PS_TIMER_B_V1(x, v)                                            \\\n\t(BIT_CLEAR_PS_TIMER_B_V1(x) | BIT_PS_TIMER_B_V1(v))\n\n/* 2 REG_PS_TIMER_C\t\t\t\t(Offset 0x150C) */\n\n#define BIT_SHIFT_PS_TIMER_C_V1 0\n#define BIT_MASK_PS_TIMER_C_V1 0xffffffffL\n#define BIT_PS_TIMER_C_V1(x)                                                   \\\n\t(((x) & BIT_MASK_PS_TIMER_C_V1) << BIT_SHIFT_PS_TIMER_C_V1)\n#define BITS_PS_TIMER_C_V1 (BIT_MASK_PS_TIMER_C_V1 << BIT_SHIFT_PS_TIMER_C_V1)\n#define BIT_CLEAR_PS_TIMER_C_V1(x) ((x) & (~BITS_PS_TIMER_C_V1))\n#define BIT_GET_PS_TIMER_C_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_C_V1) & BIT_MASK_PS_TIMER_C_V1)\n#define BIT_SET_PS_TIMER_C_V1(x, v)                                            \\\n\t(BIT_CLEAR_PS_TIMER_C_V1(x) | BIT_PS_TIMER_C_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TSFTR_SYNC_OFFSET_CFG\t\t(Offset 0x150C) */\n\n#define BIT_SHIFT_TSFTR_SNC_OFFSET_V1 0\n#define BIT_MASK_TSFTR_SNC_OFFSET_V1 0xffffff\n#define BIT_TSFTR_SNC_OFFSET_V1(x)                                             \\\n\t(((x) & BIT_MASK_TSFTR_SNC_OFFSET_V1) << BIT_SHIFT_TSFTR_SNC_OFFSET_V1)\n#define BITS_TSFTR_SNC_OFFSET_V1                                               \\\n\t(BIT_MASK_TSFTR_SNC_OFFSET_V1 << BIT_SHIFT_TSFTR_SNC_OFFSET_V1)\n#define BIT_CLEAR_TSFTR_SNC_OFFSET_V1(x) ((x) & (~BITS_TSFTR_SNC_OFFSET_V1))\n#define BIT_GET_TSFTR_SNC_OFFSET_V1(x)                                         \\\n\t(((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_V1) & BIT_MASK_TSFTR_SNC_OFFSET_V1)\n#define BIT_SET_TSFTR_SNC_OFFSET_V1(x, v)                                      \\\n\t(BIT_CLEAR_TSFTR_SNC_OFFSET_V1(x) | BIT_TSFTR_SNC_OFFSET_V1(v))\n\n/* 2 REG_TSFTR_SYNC_CTRL_CFG\t\t\t(Offset 0x150F) */\n\n#define BIT_SYNC_TSF_NOW_V1 BIT(5)\n#define BIT_SYNC_TSF_ONCE BIT(4)\n#define BIT_SYNC_TSF_AUTO BIT(3)\n\n#define BIT_SHIFT_SYNC_PORT_SEL 0\n#define BIT_MASK_SYNC_PORT_SEL 0x7\n#define BIT_SYNC_PORT_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_SYNC_PORT_SEL) << BIT_SHIFT_SYNC_PORT_SEL)\n#define BITS_SYNC_PORT_SEL (BIT_MASK_SYNC_PORT_SEL << BIT_SHIFT_SYNC_PORT_SEL)\n#define BIT_CLEAR_SYNC_PORT_SEL(x) ((x) & (~BITS_SYNC_PORT_SEL))\n#define BIT_GET_SYNC_PORT_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_SYNC_PORT_SEL) & BIT_MASK_SYNC_PORT_SEL)\n#define BIT_SET_SYNC_PORT_SEL(x, v)                                            \\\n\t(BIT_CLEAR_SYNC_PORT_SEL(x) | BIT_SYNC_PORT_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL\t(Offset 0x1510) */\n\n#define BIT_CPUMGQ_TIMER_EN BIT(31)\n#define BIT_CPUMGQ_TX_EN BIT(28)\n\n#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL 24\n#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL 0x7\n#define BIT_CPUMGQ_TIMER_TSF_SEL(x)                                            \\\n\t(((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL)                                 \\\n\t << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL)\n#define BITS_CPUMGQ_TIMER_TSF_SEL                                              \\\n\t(BIT_MASK_CPUMGQ_TIMER_TSF_SEL << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL)\n#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL(x) ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL))\n#define BIT_GET_CPUMGQ_TIMER_TSF_SEL(x)                                        \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) &                             \\\n\t BIT_MASK_CPUMGQ_TIMER_TSF_SEL)\n#define BIT_SET_CPUMGQ_TIMER_TSF_SEL(x, v)                                     \\\n\t(BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL(x) | BIT_CPUMGQ_TIMER_TSF_SEL(v))\n\n#define BIT_PS_TIMER_C_EN BIT(23)\n\n#define BIT_SHIFT_PS_TIMER_C_TSF_SEL 16\n#define BIT_MASK_PS_TIMER_C_TSF_SEL 0x7\n#define BIT_PS_TIMER_C_TSF_SEL(x)                                              \\\n\t(((x) & BIT_MASK_PS_TIMER_C_TSF_SEL) << BIT_SHIFT_PS_TIMER_C_TSF_SEL)\n#define BITS_PS_TIMER_C_TSF_SEL                                                \\\n\t(BIT_MASK_PS_TIMER_C_TSF_SEL << BIT_SHIFT_PS_TIMER_C_TSF_SEL)\n#define BIT_CLEAR_PS_TIMER_C_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_C_TSF_SEL))\n#define BIT_GET_PS_TIMER_C_TSF_SEL(x)                                          \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL) & BIT_MASK_PS_TIMER_C_TSF_SEL)\n#define BIT_SET_PS_TIMER_C_TSF_SEL(x, v)                                       \\\n\t(BIT_CLEAR_PS_TIMER_C_TSF_SEL(x) | BIT_PS_TIMER_C_TSF_SEL(v))\n\n#define BIT_PS_TIMER_B_EN BIT(15)\n\n#define BIT_SHIFT_PS_TIMER_B_TSF_SEL 8\n#define BIT_MASK_PS_TIMER_B_TSF_SEL 0x7\n#define BIT_PS_TIMER_B_TSF_SEL(x)                                              \\\n\t(((x) & BIT_MASK_PS_TIMER_B_TSF_SEL) << BIT_SHIFT_PS_TIMER_B_TSF_SEL)\n#define BITS_PS_TIMER_B_TSF_SEL                                                \\\n\t(BIT_MASK_PS_TIMER_B_TSF_SEL << BIT_SHIFT_PS_TIMER_B_TSF_SEL)\n#define BIT_CLEAR_PS_TIMER_B_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_B_TSF_SEL))\n#define BIT_GET_PS_TIMER_B_TSF_SEL(x)                                          \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL) & BIT_MASK_PS_TIMER_B_TSF_SEL)\n#define BIT_SET_PS_TIMER_B_TSF_SEL(x, v)                                       \\\n\t(BIT_CLEAR_PS_TIMER_B_TSF_SEL(x) | BIT_PS_TIMER_B_TSF_SEL(v))\n\n#define BIT_PS_TIMER_A_EN BIT(7)\n\n#define BIT_SHIFT_PS_TIMER_A_TSF_SEL 0\n#define BIT_MASK_PS_TIMER_A_TSF_SEL 0x7\n#define BIT_PS_TIMER_A_TSF_SEL(x)                                              \\\n\t(((x) & BIT_MASK_PS_TIMER_A_TSF_SEL) << BIT_SHIFT_PS_TIMER_A_TSF_SEL)\n#define BITS_PS_TIMER_A_TSF_SEL                                                \\\n\t(BIT_MASK_PS_TIMER_A_TSF_SEL << BIT_SHIFT_PS_TIMER_A_TSF_SEL)\n#define BIT_CLEAR_PS_TIMER_A_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_A_TSF_SEL))\n#define BIT_GET_PS_TIMER_A_TSF_SEL(x)                                          \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL) & BIT_MASK_PS_TIMER_A_TSF_SEL)\n#define BIT_SET_PS_TIMER_A_TSF_SEL(x, v)                                       \\\n\t(BIT_CLEAR_PS_TIMER_A_TSF_SEL(x) | BIT_PS_TIMER_A_TSF_SEL(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_BCN_SPACE_CFG\t\t\t(Offset 0x1510) */\n\n#define BIT_SHIFT_BCN_SPACE 0\n#define BIT_MASK_BCN_SPACE 0xffff\n#define BIT_BCN_SPACE(x) (((x) & BIT_MASK_BCN_SPACE) << BIT_SHIFT_BCN_SPACE)\n#define BITS_BCN_SPACE (BIT_MASK_BCN_SPACE << BIT_SHIFT_BCN_SPACE)\n#define BIT_CLEAR_BCN_SPACE(x) ((x) & (~BITS_BCN_SPACE))\n#define BIT_GET_BCN_SPACE(x) (((x) >> BIT_SHIFT_BCN_SPACE) & BIT_MASK_BCN_SPACE)\n#define BIT_SET_BCN_SPACE(x, v) (BIT_CLEAR_BCN_SPACE(x) | BIT_BCN_SPACE(v))\n\n/* 2 REG_EARLY_INT_ADJUST_CFG\t\t(Offset 0x1512) */\n\n#define BIT_SHIFT_EARLY_INT_ADJUST 0\n#define BIT_MASK_EARLY_INT_ADJUST 0xffff\n#define BIT_EARLY_INT_ADJUST(x)                                                \\\n\t(((x) & BIT_MASK_EARLY_INT_ADJUST) << BIT_SHIFT_EARLY_INT_ADJUST)\n#define BITS_EARLY_INT_ADJUST                                                  \\\n\t(BIT_MASK_EARLY_INT_ADJUST << BIT_SHIFT_EARLY_INT_ADJUST)\n#define BIT_CLEAR_EARLY_INT_ADJUST(x) ((x) & (~BITS_EARLY_INT_ADJUST))\n#define BIT_GET_EARLY_INT_ADJUST(x)                                            \\\n\t(((x) >> BIT_SHIFT_EARLY_INT_ADJUST) & BIT_MASK_EARLY_INT_ADJUST)\n#define BIT_SET_EARLY_INT_ADJUST(x, v)                                         \\\n\t(BIT_CLEAR_EARLY_INT_ADJUST(x) | BIT_EARLY_INT_ADJUST(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CPUMGQ_TX_TIMER_EARLY\t\t(Offset 0x1514) */\n\n#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY 0\n#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY 0xff\n#define BIT_CPUMGQ_TX_TIMER_EARLY(x)                                           \\\n\t(((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY)                                \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY)\n#define BITS_CPUMGQ_TX_TIMER_EARLY                                             \\\n\t(BIT_MASK_CPUMGQ_TX_TIMER_EARLY << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY)\n#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY))\n#define BIT_GET_CPUMGQ_TX_TIMER_EARLY(x)                                       \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) &                            \\\n\t BIT_MASK_CPUMGQ_TX_TIMER_EARLY)\n#define BIT_SET_CPUMGQ_TX_TIMER_EARLY(x, v)                                    \\\n\t(BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY(x) | BIT_CPUMGQ_TX_TIMER_EARLY(v))\n\n/* 2 REG_PS_TIMER_A_EARLY\t\t\t(Offset 0x1515) */\n\n#define BIT_SHIFT_PS_TIMER_A_EARLY 0\n#define BIT_MASK_PS_TIMER_A_EARLY 0xff\n#define BIT_PS_TIMER_A_EARLY(x)                                                \\\n\t(((x) & BIT_MASK_PS_TIMER_A_EARLY) << BIT_SHIFT_PS_TIMER_A_EARLY)\n#define BITS_PS_TIMER_A_EARLY                                                  \\\n\t(BIT_MASK_PS_TIMER_A_EARLY << BIT_SHIFT_PS_TIMER_A_EARLY)\n#define BIT_CLEAR_PS_TIMER_A_EARLY(x) ((x) & (~BITS_PS_TIMER_A_EARLY))\n#define BIT_GET_PS_TIMER_A_EARLY(x)                                            \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_A_EARLY) & BIT_MASK_PS_TIMER_A_EARLY)\n#define BIT_SET_PS_TIMER_A_EARLY(x, v)                                         \\\n\t(BIT_CLEAR_PS_TIMER_A_EARLY(x) | BIT_PS_TIMER_A_EARLY(v))\n\n/* 2 REG_PS_TIMER_B_EARLY\t\t\t(Offset 0x1516) */\n\n#define BIT_SHIFT_PS_TIMER_B_EARLY 0\n#define BIT_MASK_PS_TIMER_B_EARLY 0xff\n#define BIT_PS_TIMER_B_EARLY(x)                                                \\\n\t(((x) & BIT_MASK_PS_TIMER_B_EARLY) << BIT_SHIFT_PS_TIMER_B_EARLY)\n#define BITS_PS_TIMER_B_EARLY                                                  \\\n\t(BIT_MASK_PS_TIMER_B_EARLY << BIT_SHIFT_PS_TIMER_B_EARLY)\n#define BIT_CLEAR_PS_TIMER_B_EARLY(x) ((x) & (~BITS_PS_TIMER_B_EARLY))\n#define BIT_GET_PS_TIMER_B_EARLY(x)                                            \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_B_EARLY) & BIT_MASK_PS_TIMER_B_EARLY)\n#define BIT_SET_PS_TIMER_B_EARLY(x, v)                                         \\\n\t(BIT_CLEAR_PS_TIMER_B_EARLY(x) | BIT_PS_TIMER_B_EARLY(v))\n\n/* 2 REG_PS_TIMER_C_EARLY\t\t\t(Offset 0x1517) */\n\n#define BIT_SHIFT_PS_TIMER_C_EARLY 0\n#define BIT_MASK_PS_TIMER_C_EARLY 0xff\n#define BIT_PS_TIMER_C_EARLY(x)                                                \\\n\t(((x) & BIT_MASK_PS_TIMER_C_EARLY) << BIT_SHIFT_PS_TIMER_C_EARLY)\n#define BITS_PS_TIMER_C_EARLY                                                  \\\n\t(BIT_MASK_PS_TIMER_C_EARLY << BIT_SHIFT_PS_TIMER_C_EARLY)\n#define BIT_CLEAR_PS_TIMER_C_EARLY(x) ((x) & (~BITS_PS_TIMER_C_EARLY))\n#define BIT_GET_PS_TIMER_C_EARLY(x)                                            \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_C_EARLY) & BIT_MASK_PS_TIMER_C_EARLY)\n#define BIT_SET_PS_TIMER_C_EARLY(x, v)                                         \\\n\t(BIT_CLEAR_PS_TIMER_C_EARLY(x) | BIT_PS_TIMER_C_EARLY(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_CPUMGQ_PARAMETER\t\t\t(Offset 0x1518) */\n\n#define BIT_STOP_CPUMGQ BIT(16)\n\n#define BIT_SHIFT_CPUMGQ_PARAMETER 0\n#define BIT_MASK_CPUMGQ_PARAMETER 0xffff\n#define BIT_CPUMGQ_PARAMETER(x)                                                \\\n\t(((x) & BIT_MASK_CPUMGQ_PARAMETER) << BIT_SHIFT_CPUMGQ_PARAMETER)\n#define BITS_CPUMGQ_PARAMETER                                                  \\\n\t(BIT_MASK_CPUMGQ_PARAMETER << BIT_SHIFT_CPUMGQ_PARAMETER)\n#define BIT_CLEAR_CPUMGQ_PARAMETER(x) ((x) & (~BITS_CPUMGQ_PARAMETER))\n#define BIT_GET_CPUMGQ_PARAMETER(x)                                            \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_PARAMETER) & BIT_MASK_CPUMGQ_PARAMETER)\n#define BIT_SET_CPUMGQ_PARAMETER(x, v)                                         \\\n\t(BIT_CLEAR_CPUMGQ_PARAMETER(x) | BIT_CPUMGQ_PARAMETER(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SW_TBTT_TSF_INFO\t\t\t(Offset 0x151C) */\n\n#define BIT_SHIFT_SW_TBTT_TSF_INFO 0\n#define BIT_MASK_SW_TBTT_TSF_INFO 0xffffffffL\n#define BIT_SW_TBTT_TSF_INFO(x)                                                \\\n\t(((x) & BIT_MASK_SW_TBTT_TSF_INFO) << BIT_SHIFT_SW_TBTT_TSF_INFO)\n#define BITS_SW_TBTT_TSF_INFO                                                  \\\n\t(BIT_MASK_SW_TBTT_TSF_INFO << BIT_SHIFT_SW_TBTT_TSF_INFO)\n#define BIT_CLEAR_SW_TBTT_TSF_INFO(x) ((x) & (~BITS_SW_TBTT_TSF_INFO))\n#define BIT_GET_SW_TBTT_TSF_INFO(x)                                            \\\n\t(((x) >> BIT_SHIFT_SW_TBTT_TSF_INFO) & BIT_MASK_SW_TBTT_TSF_INFO)\n#define BIT_SET_SW_TBTT_TSF_INFO(x, v)                                         \\\n\t(BIT_CLEAR_SW_TBTT_TSF_INFO(x) | BIT_SW_TBTT_TSF_INFO(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_TSF_SYN_CTRL0\t\t\t(Offset 0x1520) */\n\n#define BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0_V1 16\n#define BIT_MASK_TSF_SYNC_INTERVAL_PORT0_V1 0xffff\n#define BIT_TSF_SYNC_INTERVAL_PORT0_V1(x)                                      \\\n\t(((x) & BIT_MASK_TSF_SYNC_INTERVAL_PORT0_V1)                           \\\n\t << BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0_V1)\n#define BITS_TSF_SYNC_INTERVAL_PORT0_V1                                        \\\n\t(BIT_MASK_TSF_SYNC_INTERVAL_PORT0_V1                                   \\\n\t << BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0_V1)\n#define BIT_CLEAR_TSF_SYNC_INTERVAL_PORT0_V1(x)                                \\\n\t((x) & (~BITS_TSF_SYNC_INTERVAL_PORT0_V1))\n#define BIT_GET_TSF_SYNC_INTERVAL_PORT0_V1(x)                                  \\\n\t(((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0_V1) &                       \\\n\t BIT_MASK_TSF_SYNC_INTERVAL_PORT0_V1)\n#define BIT_SET_TSF_SYNC_INTERVAL_PORT0_V1(x, v)                               \\\n\t(BIT_CLEAR_TSF_SYNC_INTERVAL_PORT0_V1(x) |                             \\\n\t BIT_TSF_SYNC_INTERVAL_PORT0_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TSF_SYNC_ADJ\t\t\t(Offset 0x1520) */\n\n#define BIT_SHIFT_R_P0_TSFT_ADJ_VAL 16\n#define BIT_MASK_R_P0_TSFT_ADJ_VAL 0xffff\n#define BIT_R_P0_TSFT_ADJ_VAL(x)                                               \\\n\t(((x) & BIT_MASK_R_P0_TSFT_ADJ_VAL) << BIT_SHIFT_R_P0_TSFT_ADJ_VAL)\n#define BITS_R_P0_TSFT_ADJ_VAL                                                 \\\n\t(BIT_MASK_R_P0_TSFT_ADJ_VAL << BIT_SHIFT_R_P0_TSFT_ADJ_VAL)\n#define BIT_CLEAR_R_P0_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_P0_TSFT_ADJ_VAL))\n#define BIT_GET_R_P0_TSFT_ADJ_VAL(x)                                           \\\n\t(((x) >> BIT_SHIFT_R_P0_TSFT_ADJ_VAL) & BIT_MASK_R_P0_TSFT_ADJ_VAL)\n#define BIT_SET_R_P0_TSFT_ADJ_VAL(x, v)                                        \\\n\t(BIT_CLEAR_R_P0_TSFT_ADJ_VAL(x) | BIT_R_P0_TSFT_ADJ_VAL(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_TSF_SYN_CTRL0\t\t\t(Offset 0x1520) */\n\n#define BIT_TSF_SYNC_SIGNAL_V1 BIT(8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TSF_SYNC_ADJ\t\t\t(Offset 0x1520) */\n\n#define BIT_R_X_COMP_Y_OVER BIT(8)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TSF_SYN_CTRL0\t\t\t(Offset 0x1520) */\n\n#define BIT_TSF_SYNC_COMPARE_POLLING BIT(7)\n#define BIT_TSF_SYNC_POLLING BIT(6)\n\n#define BIT_SHIFT_TSF_SYNC_DUT 3\n#define BIT_MASK_TSF_SYNC_DUT 0x7\n#define BIT_TSF_SYNC_DUT(x)                                                    \\\n\t(((x) & BIT_MASK_TSF_SYNC_DUT) << BIT_SHIFT_TSF_SYNC_DUT)\n#define BITS_TSF_SYNC_DUT (BIT_MASK_TSF_SYNC_DUT << BIT_SHIFT_TSF_SYNC_DUT)\n#define BIT_CLEAR_TSF_SYNC_DUT(x) ((x) & (~BITS_TSF_SYNC_DUT))\n#define BIT_GET_TSF_SYNC_DUT(x)                                                \\\n\t(((x) >> BIT_SHIFT_TSF_SYNC_DUT) & BIT_MASK_TSF_SYNC_DUT)\n#define BIT_SET_TSF_SYNC_DUT(x, v)                                             \\\n\t(BIT_CLEAR_TSF_SYNC_DUT(x) | BIT_TSF_SYNC_DUT(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TSF_SYNC_ADJ\t\t\t(Offset 0x1520) */\n\n#define BIT_SHIFT_R_X_SYNC_SEL 3\n#define BIT_MASK_R_X_SYNC_SEL 0x7\n#define BIT_R_X_SYNC_SEL(x)                                                    \\\n\t(((x) & BIT_MASK_R_X_SYNC_SEL) << BIT_SHIFT_R_X_SYNC_SEL)\n#define BITS_R_X_SYNC_SEL (BIT_MASK_R_X_SYNC_SEL << BIT_SHIFT_R_X_SYNC_SEL)\n#define BIT_CLEAR_R_X_SYNC_SEL(x) ((x) & (~BITS_R_X_SYNC_SEL))\n#define BIT_GET_R_X_SYNC_SEL(x)                                                \\\n\t(((x) >> BIT_SHIFT_R_X_SYNC_SEL) & BIT_MASK_R_X_SYNC_SEL)\n#define BIT_SET_R_X_SYNC_SEL(x, v)                                             \\\n\t(BIT_CLEAR_R_X_SYNC_SEL(x) | BIT_R_X_SYNC_SEL(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TSF_SYN_CTRL0\t\t\t(Offset 0x1520) */\n\n#define BIT_SHIFT_TSF_SYNC_SOURCE 0\n#define BIT_MASK_TSF_SYNC_SOURCE 0x7\n#define BIT_TSF_SYNC_SOURCE(x)                                                 \\\n\t(((x) & BIT_MASK_TSF_SYNC_SOURCE) << BIT_SHIFT_TSF_SYNC_SOURCE)\n#define BITS_TSF_SYNC_SOURCE                                                   \\\n\t(BIT_MASK_TSF_SYNC_SOURCE << BIT_SHIFT_TSF_SYNC_SOURCE)\n#define BIT_CLEAR_TSF_SYNC_SOURCE(x) ((x) & (~BITS_TSF_SYNC_SOURCE))\n#define BIT_GET_TSF_SYNC_SOURCE(x)                                             \\\n\t(((x) >> BIT_SHIFT_TSF_SYNC_SOURCE) & BIT_MASK_TSF_SYNC_SOURCE)\n#define BIT_SET_TSF_SYNC_SOURCE(x, v)                                          \\\n\t(BIT_CLEAR_TSF_SYNC_SOURCE(x) | BIT_TSF_SYNC_SOURCE(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TSF_SYNC_ADJ\t\t\t(Offset 0x1520) */\n\n#define BIT_SHIFT_R_SYNC_Y_SEL 0\n#define BIT_MASK_R_SYNC_Y_SEL 0x7\n#define BIT_R_SYNC_Y_SEL(x)                                                    \\\n\t(((x) & BIT_MASK_R_SYNC_Y_SEL) << BIT_SHIFT_R_SYNC_Y_SEL)\n#define BITS_R_SYNC_Y_SEL (BIT_MASK_R_SYNC_Y_SEL << BIT_SHIFT_R_SYNC_Y_SEL)\n#define BIT_CLEAR_R_SYNC_Y_SEL(x) ((x) & (~BITS_R_SYNC_Y_SEL))\n#define BIT_GET_R_SYNC_Y_SEL(x)                                                \\\n\t(((x) >> BIT_SHIFT_R_SYNC_Y_SEL) & BIT_MASK_R_SYNC_Y_SEL)\n#define BIT_SET_R_SYNC_Y_SEL(x, v)                                             \\\n\t(BIT_CLEAR_R_SYNC_Y_SEL(x) | BIT_R_SYNC_Y_SEL(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TSFTR_LOW\t\t\t\t(Offset 0x1520) */\n\n#define BIT_SHIFT_TSF_TIMER_LOW 0\n#define BIT_MASK_TSF_TIMER_LOW 0xffffffffL\n#define BIT_TSF_TIMER_LOW(x)                                                   \\\n\t(((x) & BIT_MASK_TSF_TIMER_LOW) << BIT_SHIFT_TSF_TIMER_LOW)\n#define BITS_TSF_TIMER_LOW (BIT_MASK_TSF_TIMER_LOW << BIT_SHIFT_TSF_TIMER_LOW)\n#define BIT_CLEAR_TSF_TIMER_LOW(x) ((x) & (~BITS_TSF_TIMER_LOW))\n#define BIT_GET_TSF_TIMER_LOW(x)                                               \\\n\t(((x) >> BIT_SHIFT_TSF_TIMER_LOW) & BIT_MASK_TSF_TIMER_LOW)\n#define BIT_SET_TSF_TIMER_LOW(x, v)                                            \\\n\t(BIT_CLEAR_TSF_TIMER_LOW(x) | BIT_TSF_TIMER_LOW(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TSF_SYN_OFFSET0\t\t\t(Offset 0x1522) */\n\n#define BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0 0\n#define BIT_MASK_TSF_SYNC_INTERVAL_PORT0 0xffff\n#define BIT_TSF_SYNC_INTERVAL_PORT0(x)                                         \\\n\t(((x) & BIT_MASK_TSF_SYNC_INTERVAL_PORT0)                              \\\n\t << BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0)\n#define BITS_TSF_SYNC_INTERVAL_PORT0                                           \\\n\t(BIT_MASK_TSF_SYNC_INTERVAL_PORT0 << BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0)\n#define BIT_CLEAR_TSF_SYNC_INTERVAL_PORT0(x)                                   \\\n\t((x) & (~BITS_TSF_SYNC_INTERVAL_PORT0))\n#define BIT_GET_TSF_SYNC_INTERVAL_PORT0(x)                                     \\\n\t(((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0) &                          \\\n\t BIT_MASK_TSF_SYNC_INTERVAL_PORT0)\n#define BIT_SET_TSF_SYNC_INTERVAL_PORT0(x, v)                                  \\\n\t(BIT_CLEAR_TSF_SYNC_INTERVAL_PORT0(x) | BIT_TSF_SYNC_INTERVAL_PORT0(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TSF_SYN_OFFSET1\t\t\t(Offset 0x1524) */\n\n#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1 16\n#define BIT_MASK_TSF_SYNC_INTERVAL_CLI1 0xffff\n#define BIT_TSF_SYNC_INTERVAL_CLI1(x)                                          \\\n\t(((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI1)                               \\\n\t << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1)\n#define BITS_TSF_SYNC_INTERVAL_CLI1                                            \\\n\t(BIT_MASK_TSF_SYNC_INTERVAL_CLI1 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1)\n#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI1(x)                                    \\\n\t((x) & (~BITS_TSF_SYNC_INTERVAL_CLI1))\n#define BIT_GET_TSF_SYNC_INTERVAL_CLI1(x)                                      \\\n\t(((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1) &                           \\\n\t BIT_MASK_TSF_SYNC_INTERVAL_CLI1)\n#define BIT_SET_TSF_SYNC_INTERVAL_CLI1(x, v)                                   \\\n\t(BIT_CLEAR_TSF_SYNC_INTERVAL_CLI1(x) | BIT_TSF_SYNC_INTERVAL_CLI1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TSF_ADJ_VLAUE\t\t\t(Offset 0x1524) */\n\n#define BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL 16\n#define BIT_MASK_R_CLI1_TSFT_ADJ_VAL 0xffff\n#define BIT_R_CLI1_TSFT_ADJ_VAL(x)                                             \\\n\t(((x) & BIT_MASK_R_CLI1_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL)\n#define BITS_R_CLI1_TSFT_ADJ_VAL                                               \\\n\t(BIT_MASK_R_CLI1_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL)\n#define BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI1_TSFT_ADJ_VAL))\n#define BIT_GET_R_CLI1_TSFT_ADJ_VAL(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL) & BIT_MASK_R_CLI1_TSFT_ADJ_VAL)\n#define BIT_SET_R_CLI1_TSFT_ADJ_VAL(x, v)                                      \\\n\t(BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL(x) | BIT_R_CLI1_TSFT_ADJ_VAL(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TSF_SYN_OFFSET1\t\t\t(Offset 0x1524) */\n\n#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0 0\n#define BIT_MASK_TSF_SYNC_INTERVAL_CLI0 0xffff\n#define BIT_TSF_SYNC_INTERVAL_CLI0(x)                                          \\\n\t(((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI0)                               \\\n\t << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0)\n#define BITS_TSF_SYNC_INTERVAL_CLI0                                            \\\n\t(BIT_MASK_TSF_SYNC_INTERVAL_CLI0 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0)\n#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI0(x)                                    \\\n\t((x) & (~BITS_TSF_SYNC_INTERVAL_CLI0))\n#define BIT_GET_TSF_SYNC_INTERVAL_CLI0(x)                                      \\\n\t(((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0) &                           \\\n\t BIT_MASK_TSF_SYNC_INTERVAL_CLI0)\n#define BIT_SET_TSF_SYNC_INTERVAL_CLI0(x, v)                                   \\\n\t(BIT_CLEAR_TSF_SYNC_INTERVAL_CLI0(x) | BIT_TSF_SYNC_INTERVAL_CLI0(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TSF_ADJ_VLAUE\t\t\t(Offset 0x1524) */\n\n#define BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL 0\n#define BIT_MASK_R_CLI0_TSFT_ADJ_VAL 0xffff\n#define BIT_R_CLI0_TSFT_ADJ_VAL(x)                                             \\\n\t(((x) & BIT_MASK_R_CLI0_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL)\n#define BITS_R_CLI0_TSFT_ADJ_VAL                                               \\\n\t(BIT_MASK_R_CLI0_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL)\n#define BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI0_TSFT_ADJ_VAL))\n#define BIT_GET_R_CLI0_TSFT_ADJ_VAL(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL) & BIT_MASK_R_CLI0_TSFT_ADJ_VAL)\n#define BIT_SET_R_CLI0_TSFT_ADJ_VAL(x, v)                                      \\\n\t(BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL(x) | BIT_R_CLI0_TSFT_ADJ_VAL(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TSFTR_HIGH\t\t\t\t(Offset 0x1524) */\n\n#define BIT_SHIFT_TSF_TIMER_HIGH 0\n#define BIT_MASK_TSF_TIMER_HIGH 0xffffffffL\n#define BIT_TSF_TIMER_HIGH(x)                                                  \\\n\t(((x) & BIT_MASK_TSF_TIMER_HIGH) << BIT_SHIFT_TSF_TIMER_HIGH)\n#define BITS_TSF_TIMER_HIGH                                                    \\\n\t(BIT_MASK_TSF_TIMER_HIGH << BIT_SHIFT_TSF_TIMER_HIGH)\n#define BIT_CLEAR_TSF_TIMER_HIGH(x) ((x) & (~BITS_TSF_TIMER_HIGH))\n#define BIT_GET_TSF_TIMER_HIGH(x)                                              \\\n\t(((x) >> BIT_SHIFT_TSF_TIMER_HIGH) & BIT_MASK_TSF_TIMER_HIGH)\n#define BIT_SET_TSF_TIMER_HIGH(x, v)                                           \\\n\t(BIT_CLEAR_TSF_TIMER_HIGH(x) | BIT_TSF_TIMER_HIGH(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TSF_SYN_OFFSET2\t\t\t(Offset 0x1528) */\n\n#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3 16\n#define BIT_MASK_TSF_SYNC_INTERVAL_CLI3 0xffff\n#define BIT_TSF_SYNC_INTERVAL_CLI3(x)                                          \\\n\t(((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI3)                               \\\n\t << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3)\n#define BITS_TSF_SYNC_INTERVAL_CLI3                                            \\\n\t(BIT_MASK_TSF_SYNC_INTERVAL_CLI3 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3)\n#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI3(x)                                    \\\n\t((x) & (~BITS_TSF_SYNC_INTERVAL_CLI3))\n#define BIT_GET_TSF_SYNC_INTERVAL_CLI3(x)                                      \\\n\t(((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3) &                           \\\n\t BIT_MASK_TSF_SYNC_INTERVAL_CLI3)\n#define BIT_SET_TSF_SYNC_INTERVAL_CLI3(x, v)                                   \\\n\t(BIT_CLEAR_TSF_SYNC_INTERVAL_CLI3(x) | BIT_TSF_SYNC_INTERVAL_CLI3(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TSF_ADJ_VLAUE_2\t\t\t(Offset 0x1528) */\n\n#define BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL 16\n#define BIT_MASK_R_CLI3_TSFT_ADJ_VAL 0xffff\n#define BIT_R_CLI3_TSFT_ADJ_VAL(x)                                             \\\n\t(((x) & BIT_MASK_R_CLI3_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL)\n#define BITS_R_CLI3_TSFT_ADJ_VAL                                               \\\n\t(BIT_MASK_R_CLI3_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL)\n#define BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI3_TSFT_ADJ_VAL))\n#define BIT_GET_R_CLI3_TSFT_ADJ_VAL(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL) & BIT_MASK_R_CLI3_TSFT_ADJ_VAL)\n#define BIT_SET_R_CLI3_TSFT_ADJ_VAL(x, v)                                      \\\n\t(BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL(x) | BIT_R_CLI3_TSFT_ADJ_VAL(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TSF_SYN_OFFSET2\t\t\t(Offset 0x1528) */\n\n#define BIT_WMAC_20MHZBW BIT(2)\n\n#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2 0\n#define BIT_MASK_TSF_SYNC_INTERVAL_CLI2 0xffff\n#define BIT_TSF_SYNC_INTERVAL_CLI2(x)                                          \\\n\t(((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI2)                               \\\n\t << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2)\n#define BITS_TSF_SYNC_INTERVAL_CLI2                                            \\\n\t(BIT_MASK_TSF_SYNC_INTERVAL_CLI2 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2)\n#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI2(x)                                    \\\n\t((x) & (~BITS_TSF_SYNC_INTERVAL_CLI2))\n#define BIT_GET_TSF_SYNC_INTERVAL_CLI2(x)                                      \\\n\t(((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2) &                           \\\n\t BIT_MASK_TSF_SYNC_INTERVAL_CLI2)\n#define BIT_SET_TSF_SYNC_INTERVAL_CLI2(x, v)                                   \\\n\t(BIT_CLEAR_TSF_SYNC_INTERVAL_CLI2(x) | BIT_TSF_SYNC_INTERVAL_CLI2(v))\n\n#define BIT_WMAC_M11J BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TSF_ADJ_VLAUE_2\t\t\t(Offset 0x1528) */\n\n#define BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL 0\n#define BIT_MASK_R_CLI2_TSFT_ADJ_VAL 0xffff\n#define BIT_R_CLI2_TSFT_ADJ_VAL(x)                                             \\\n\t(((x) & BIT_MASK_R_CLI2_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL)\n#define BITS_R_CLI2_TSFT_ADJ_VAL                                               \\\n\t(BIT_MASK_R_CLI2_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL)\n#define BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI2_TSFT_ADJ_VAL))\n#define BIT_GET_R_CLI2_TSFT_ADJ_VAL(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL) & BIT_MASK_R_CLI2_TSFT_ADJ_VAL)\n#define BIT_SET_R_CLI2_TSFT_ADJ_VAL(x, v)                                      \\\n\t(BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL(x) | BIT_R_CLI2_TSFT_ADJ_VAL(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_BCN_ERR_CNT_MAC\t\t\t(Offset 0x1528) */\n\n#define BIT_SHIFT_BCN_ERR_CNT_MAC 0\n#define BIT_MASK_BCN_ERR_CNT_MAC 0xff\n#define BIT_BCN_ERR_CNT_MAC(x)                                                 \\\n\t(((x) & BIT_MASK_BCN_ERR_CNT_MAC) << BIT_SHIFT_BCN_ERR_CNT_MAC)\n#define BITS_BCN_ERR_CNT_MAC                                                   \\\n\t(BIT_MASK_BCN_ERR_CNT_MAC << BIT_SHIFT_BCN_ERR_CNT_MAC)\n#define BIT_CLEAR_BCN_ERR_CNT_MAC(x) ((x) & (~BITS_BCN_ERR_CNT_MAC))\n#define BIT_GET_BCN_ERR_CNT_MAC(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCN_ERR_CNT_MAC) & BIT_MASK_BCN_ERR_CNT_MAC)\n#define BIT_SET_BCN_ERR_CNT_MAC(x, v)                                          \\\n\t(BIT_CLEAR_BCN_ERR_CNT_MAC(x) | BIT_BCN_ERR_CNT_MAC(v))\n\n/* 2 REG_BCN_ERR_CNT_EDCCA\t\t\t(Offset 0x1529) */\n\n#define BIT_SHIFT_BCN_ERR_CNT_EDCCA 0\n#define BIT_MASK_BCN_ERR_CNT_EDCCA 0xff\n#define BIT_BCN_ERR_CNT_EDCCA(x)                                               \\\n\t(((x) & BIT_MASK_BCN_ERR_CNT_EDCCA) << BIT_SHIFT_BCN_ERR_CNT_EDCCA)\n#define BITS_BCN_ERR_CNT_EDCCA                                                 \\\n\t(BIT_MASK_BCN_ERR_CNT_EDCCA << BIT_SHIFT_BCN_ERR_CNT_EDCCA)\n#define BIT_CLEAR_BCN_ERR_CNT_EDCCA(x) ((x) & (~BITS_BCN_ERR_CNT_EDCCA))\n#define BIT_GET_BCN_ERR_CNT_EDCCA(x)                                           \\\n\t(((x) >> BIT_SHIFT_BCN_ERR_CNT_EDCCA) & BIT_MASK_BCN_ERR_CNT_EDCCA)\n#define BIT_SET_BCN_ERR_CNT_EDCCA(x, v)                                        \\\n\t(BIT_CLEAR_BCN_ERR_CNT_EDCCA(x) | BIT_BCN_ERR_CNT_EDCCA(v))\n\n/* 2 REG_BCN_ERR_CNT_CCA\t\t\t(Offset 0x152A) */\n\n#define BIT_SHIFT_BCN_ERR_CNT_CCA 0\n#define BIT_MASK_BCN_ERR_CNT_CCA 0xff\n#define BIT_BCN_ERR_CNT_CCA(x)                                                 \\\n\t(((x) & BIT_MASK_BCN_ERR_CNT_CCA) << BIT_SHIFT_BCN_ERR_CNT_CCA)\n#define BITS_BCN_ERR_CNT_CCA                                                   \\\n\t(BIT_MASK_BCN_ERR_CNT_CCA << BIT_SHIFT_BCN_ERR_CNT_CCA)\n#define BIT_CLEAR_BCN_ERR_CNT_CCA(x) ((x) & (~BITS_BCN_ERR_CNT_CCA))\n#define BIT_GET_BCN_ERR_CNT_CCA(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCN_ERR_CNT_CCA) & BIT_MASK_BCN_ERR_CNT_CCA)\n#define BIT_SET_BCN_ERR_CNT_CCA(x, v)                                          \\\n\t(BIT_CLEAR_BCN_ERR_CNT_CCA(x) | BIT_BCN_ERR_CNT_CCA(v))\n\n/* 2 REG_BCN_ERR_CNT_INVALID\t\t\t(Offset 0x152B) */\n\n#define BIT_SHIFT_BCN_ERR_CNT_INVALID 0\n#define BIT_MASK_BCN_ERR_CNT_INVALID 0xff\n#define BIT_BCN_ERR_CNT_INVALID(x)                                             \\\n\t(((x) & BIT_MASK_BCN_ERR_CNT_INVALID) << BIT_SHIFT_BCN_ERR_CNT_INVALID)\n#define BITS_BCN_ERR_CNT_INVALID                                               \\\n\t(BIT_MASK_BCN_ERR_CNT_INVALID << BIT_SHIFT_BCN_ERR_CNT_INVALID)\n#define BIT_CLEAR_BCN_ERR_CNT_INVALID(x) ((x) & (~BITS_BCN_ERR_CNT_INVALID))\n#define BIT_GET_BCN_ERR_CNT_INVALID(x)                                         \\\n\t(((x) >> BIT_SHIFT_BCN_ERR_CNT_INVALID) & BIT_MASK_BCN_ERR_CNT_INVALID)\n#define BIT_SET_BCN_ERR_CNT_INVALID(x, v)                                      \\\n\t(BIT_CLEAR_BCN_ERR_CNT_INVALID(x) | BIT_BCN_ERR_CNT_INVALID(v))\n\n/* 2 REG_BCN_ERR_CNT_OTHERS\t\t\t(Offset 0x152C) */\n\n#define BIT_SHIFT_BCN_ERR_CNT_OTHERS 0\n#define BIT_MASK_BCN_ERR_CNT_OTHERS 0xff\n#define BIT_BCN_ERR_CNT_OTHERS(x)                                              \\\n\t(((x) & BIT_MASK_BCN_ERR_CNT_OTHERS) << BIT_SHIFT_BCN_ERR_CNT_OTHERS)\n#define BITS_BCN_ERR_CNT_OTHERS                                                \\\n\t(BIT_MASK_BCN_ERR_CNT_OTHERS << BIT_SHIFT_BCN_ERR_CNT_OTHERS)\n#define BIT_CLEAR_BCN_ERR_CNT_OTHERS(x) ((x) & (~BITS_BCN_ERR_CNT_OTHERS))\n#define BIT_GET_BCN_ERR_CNT_OTHERS(x)                                          \\\n\t(((x) >> BIT_SHIFT_BCN_ERR_CNT_OTHERS) & BIT_MASK_BCN_ERR_CNT_OTHERS)\n#define BIT_SET_BCN_ERR_CNT_OTHERS(x, v)                                       \\\n\t(BIT_CLEAR_BCN_ERR_CNT_OTHERS(x) | BIT_BCN_ERR_CNT_OTHERS(v))\n\n/* 2 REG_RX_BCN_TIMER\t\t\t(Offset 0x152D) */\n\n#define BIT_SHIFT_RX_BCN_TIMER 0\n#define BIT_MASK_RX_BCN_TIMER 0xffff\n#define BIT_RX_BCN_TIMER(x)                                                    \\\n\t(((x) & BIT_MASK_RX_BCN_TIMER) << BIT_SHIFT_RX_BCN_TIMER)\n#define BITS_RX_BCN_TIMER (BIT_MASK_RX_BCN_TIMER << BIT_SHIFT_RX_BCN_TIMER)\n#define BIT_CLEAR_RX_BCN_TIMER(x) ((x) & (~BITS_RX_BCN_TIMER))\n#define BIT_GET_RX_BCN_TIMER(x)                                                \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TIMER) & BIT_MASK_RX_BCN_TIMER)\n#define BIT_SET_RX_BCN_TIMER(x, v)                                             \\\n\t(BIT_CLEAR_RX_BCN_TIMER(x) | BIT_RX_BCN_TIMER(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_TSF_SYN_COMPARE_VALUE_L\t\t(Offset 0x1530) */\n\n#define BIT_SHIFT_TSF_SYN_COMPARE_VALUE_L 0\n#define BIT_MASK_TSF_SYN_COMPARE_VALUE_L 0xffffffffL\n#define BIT_TSF_SYN_COMPARE_VALUE_L(x)                                         \\\n\t(((x) & BIT_MASK_TSF_SYN_COMPARE_VALUE_L)                              \\\n\t << BIT_SHIFT_TSF_SYN_COMPARE_VALUE_L)\n#define BITS_TSF_SYN_COMPARE_VALUE_L                                           \\\n\t(BIT_MASK_TSF_SYN_COMPARE_VALUE_L << BIT_SHIFT_TSF_SYN_COMPARE_VALUE_L)\n#define BIT_CLEAR_TSF_SYN_COMPARE_VALUE_L(x)                                   \\\n\t((x) & (~BITS_TSF_SYN_COMPARE_VALUE_L))\n#define BIT_GET_TSF_SYN_COMPARE_VALUE_L(x)                                     \\\n\t(((x) >> BIT_SHIFT_TSF_SYN_COMPARE_VALUE_L) &                          \\\n\t BIT_MASK_TSF_SYN_COMPARE_VALUE_L)\n#define BIT_SET_TSF_SYN_COMPARE_VALUE_L(x, v)                                  \\\n\t(BIT_CLEAR_TSF_SYN_COMPARE_VALUE_L(x) | BIT_TSF_SYN_COMPARE_VALUE_L(v))\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_TSF_SYN_COMPARE_VALUE\t\t(Offset 0x1530) */\n\n#define BIT_SHIFT_TSF_SYN_COMPARE_VALUE 0\n#define BIT_MASK_TSF_SYN_COMPARE_VALUE 0xffffffffffffffffL\n#define BIT_TSF_SYN_COMPARE_VALUE(x)                                           \\\n\t(((x) & BIT_MASK_TSF_SYN_COMPARE_VALUE)                                \\\n\t << BIT_SHIFT_TSF_SYN_COMPARE_VALUE)\n#define BITS_TSF_SYN_COMPARE_VALUE                                             \\\n\t(BIT_MASK_TSF_SYN_COMPARE_VALUE << BIT_SHIFT_TSF_SYN_COMPARE_VALUE)\n#define BIT_CLEAR_TSF_SYN_COMPARE_VALUE(x) ((x) & (~BITS_TSF_SYN_COMPARE_VALUE))\n#define BIT_GET_TSF_SYN_COMPARE_VALUE(x)                                       \\\n\t(((x) >> BIT_SHIFT_TSF_SYN_COMPARE_VALUE) &                            \\\n\t BIT_MASK_TSF_SYN_COMPARE_VALUE)\n#define BIT_SET_TSF_SYN_COMPARE_VALUE(x, v)                                    \\\n\t(BIT_CLEAR_TSF_SYN_COMPARE_VALUE(x) | BIT_TSF_SYN_COMPARE_VALUE(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_TSF_SYN_COMPARE_VALUE_H\t\t(Offset 0x1534) */\n\n#define BIT_SHIFT_TSF_SYN_COMPARE_VALUE_H 0\n#define BIT_MASK_TSF_SYN_COMPARE_VALUE_H 0xffffffffL\n#define BIT_TSF_SYN_COMPARE_VALUE_H(x)                                         \\\n\t(((x) & BIT_MASK_TSF_SYN_COMPARE_VALUE_H)                              \\\n\t << BIT_SHIFT_TSF_SYN_COMPARE_VALUE_H)\n#define BITS_TSF_SYN_COMPARE_VALUE_H                                           \\\n\t(BIT_MASK_TSF_SYN_COMPARE_VALUE_H << BIT_SHIFT_TSF_SYN_COMPARE_VALUE_H)\n#define BIT_CLEAR_TSF_SYN_COMPARE_VALUE_H(x)                                   \\\n\t((x) & (~BITS_TSF_SYN_COMPARE_VALUE_H))\n#define BIT_GET_TSF_SYN_COMPARE_VALUE_H(x)                                     \\\n\t(((x) >> BIT_SHIFT_TSF_SYN_COMPARE_VALUE_H) &                          \\\n\t BIT_MASK_TSF_SYN_COMPARE_VALUE_H)\n#define BIT_SET_TSF_SYN_COMPARE_VALUE_H(x, v)                                  \\\n\t(BIT_CLEAR_TSF_SYN_COMPARE_VALUE_H(x) | BIT_TSF_SYN_COMPARE_VALUE_H(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SUB_BCN_SPACE\t\t\t(Offset 0x1534) */\n\n#define BIT_SHIFT_SUB_BCN_SPACE_V2 0\n#define BIT_MASK_SUB_BCN_SPACE_V2 0xff\n#define BIT_SUB_BCN_SPACE_V2(x)                                                \\\n\t(((x) & BIT_MASK_SUB_BCN_SPACE_V2) << BIT_SHIFT_SUB_BCN_SPACE_V2)\n#define BITS_SUB_BCN_SPACE_V2                                                  \\\n\t(BIT_MASK_SUB_BCN_SPACE_V2 << BIT_SHIFT_SUB_BCN_SPACE_V2)\n#define BIT_CLEAR_SUB_BCN_SPACE_V2(x) ((x) & (~BITS_SUB_BCN_SPACE_V2))\n#define BIT_GET_SUB_BCN_SPACE_V2(x)                                            \\\n\t(((x) >> BIT_SHIFT_SUB_BCN_SPACE_V2) & BIT_MASK_SUB_BCN_SPACE_V2)\n#define BIT_SET_SUB_BCN_SPACE_V2(x, v)                                         \\\n\t(BIT_CLEAR_SUB_BCN_SPACE_V2(x) | BIT_SUB_BCN_SPACE_V2(v))\n\n/* 2 REG_MBID_NUM_V1\t\t\t\t(Offset 0x1535) */\n\n#define BIT_SHIFT_BCN_ERR_PORT_SEL 4\n#define BIT_MASK_BCN_ERR_PORT_SEL 0xf\n#define BIT_BCN_ERR_PORT_SEL(x)                                                \\\n\t(((x) & BIT_MASK_BCN_ERR_PORT_SEL) << BIT_SHIFT_BCN_ERR_PORT_SEL)\n#define BITS_BCN_ERR_PORT_SEL                                                  \\\n\t(BIT_MASK_BCN_ERR_PORT_SEL << BIT_SHIFT_BCN_ERR_PORT_SEL)\n#define BIT_CLEAR_BCN_ERR_PORT_SEL(x) ((x) & (~BITS_BCN_ERR_PORT_SEL))\n#define BIT_GET_BCN_ERR_PORT_SEL(x)                                            \\\n\t(((x) >> BIT_SHIFT_BCN_ERR_PORT_SEL) & BIT_MASK_BCN_ERR_PORT_SEL)\n#define BIT_SET_BCN_ERR_PORT_SEL(x, v)                                         \\\n\t(BIT_CLEAR_BCN_ERR_PORT_SEL(x) | BIT_BCN_ERR_PORT_SEL(v))\n\n#define BIT_SHIFT_MBID_BCN_NUM_V1 0\n#define BIT_MASK_MBID_BCN_NUM_V1 0xf\n#define BIT_MBID_BCN_NUM_V1(x)                                                 \\\n\t(((x) & BIT_MASK_MBID_BCN_NUM_V1) << BIT_SHIFT_MBID_BCN_NUM_V1)\n#define BITS_MBID_BCN_NUM_V1                                                   \\\n\t(BIT_MASK_MBID_BCN_NUM_V1 << BIT_SHIFT_MBID_BCN_NUM_V1)\n#define BIT_CLEAR_MBID_BCN_NUM_V1(x) ((x) & (~BITS_MBID_BCN_NUM_V1))\n#define BIT_GET_MBID_BCN_NUM_V1(x)                                             \\\n\t(((x) >> BIT_SHIFT_MBID_BCN_NUM_V1) & BIT_MASK_MBID_BCN_NUM_V1)\n#define BIT_SET_MBID_BCN_NUM_V1(x, v)                                          \\\n\t(BIT_CLEAR_MBID_BCN_NUM_V1(x) | BIT_MBID_BCN_NUM_V1(v))\n\n/* 2 REG_MBSSID_CTRL_V1\t\t\t(Offset 0x1536) */\n\n#define BIT_MBID_BCNQ15_EN BIT(15)\n#define BIT_MBID_BCNQ14_EN BIT(14)\n#define BIT_MBID_BCNQ13_EN BIT(13)\n#define BIT_MBID_BCNQ12_EN BIT(12)\n#define BIT_MBID_BCNQ11_EN BIT(11)\n#define BIT_MBID_BCNQ10_EN BIT(10)\n#define BIT_MBID_BCNQ9_EN BIT(9)\n#define BIT_MBID_BCNQ8_EN BIT(8)\n\n/* 2 REG_BW_CFG\t\t\t\t(Offset 0x1539) */\n\n#define BIT_SLEEP_32K_EN BIT(3)\n#define BIT_DIS_MARK_TSF_US_V1 BIT(2)\n\n/* 2 REG_ATIMWND_CFG\t\t\t\t(Offset 0x153A) */\n\n#define BIT_SHIFT_ATIMWND_V1 0\n#define BIT_MASK_ATIMWND_V1 0xff\n#define BIT_ATIMWND_V1(x) (((x) & BIT_MASK_ATIMWND_V1) << BIT_SHIFT_ATIMWND_V1)\n#define BITS_ATIMWND_V1 (BIT_MASK_ATIMWND_V1 << BIT_SHIFT_ATIMWND_V1)\n#define BIT_CLEAR_ATIMWND_V1(x) ((x) & (~BITS_ATIMWND_V1))\n#define BIT_GET_ATIMWND_V1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_ATIMWND_V1) & BIT_MASK_ATIMWND_V1)\n#define BIT_SET_ATIMWND_V1(x, v) (BIT_CLEAR_ATIMWND_V1(x) | BIT_ATIMWND_V1(v))\n\n/* 2 REG_DTIM_COUNTER_CFG\t\t\t(Offset 0x153B) */\n\n#define BIT_SHIFT_DTIM_COUNT 0\n#define BIT_MASK_DTIM_COUNT 0xff\n#define BIT_DTIM_COUNT(x) (((x) & BIT_MASK_DTIM_COUNT) << BIT_SHIFT_DTIM_COUNT)\n#define BITS_DTIM_COUNT (BIT_MASK_DTIM_COUNT << BIT_SHIFT_DTIM_COUNT)\n#define BIT_CLEAR_DTIM_COUNT(x) ((x) & (~BITS_DTIM_COUNT))\n#define BIT_GET_DTIM_COUNT(x)                                                  \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT) & BIT_MASK_DTIM_COUNT)\n#define BIT_SET_DTIM_COUNT(x, v) (BIT_CLEAR_DTIM_COUNT(x) | BIT_DTIM_COUNT(v))\n\n/* 2 REG_ATIM_DTIM_CTRL_SEL\t\t\t(Offset 0x153C) */\n\n#define BIT_DTIM_BYPASS_V1 BIT(7)\n\n#define BIT_SHIFT_ATIM_DTIM_SEL 0\n#define BIT_MASK_ATIM_DTIM_SEL 0x1f\n#define BIT_ATIM_DTIM_SEL(x)                                                   \\\n\t(((x) & BIT_MASK_ATIM_DTIM_SEL) << BIT_SHIFT_ATIM_DTIM_SEL)\n#define BITS_ATIM_DTIM_SEL (BIT_MASK_ATIM_DTIM_SEL << BIT_SHIFT_ATIM_DTIM_SEL)\n#define BIT_CLEAR_ATIM_DTIM_SEL(x) ((x) & (~BITS_ATIM_DTIM_SEL))\n#define BIT_GET_ATIM_DTIM_SEL(x)                                               \\\n\t(((x) >> BIT_SHIFT_ATIM_DTIM_SEL) & BIT_MASK_ATIM_DTIM_SEL)\n#define BIT_SET_ATIM_DTIM_SEL(x, v)                                            \\\n\t(BIT_CLEAR_ATIM_DTIM_SEL(x) | BIT_ATIM_DTIM_SEL(v))\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n/* 2 REG_ATIMUGT_V1\t\t\t\t(Offset 0x153D) */\n\n#define BIT_SHIFT_ATIM_URGENT 0\n#define BIT_MASK_ATIM_URGENT 0xff\n#define BIT_ATIM_URGENT(x)                                                     \\\n\t(((x) & BIT_MASK_ATIM_URGENT) << BIT_SHIFT_ATIM_URGENT)\n#define BITS_ATIM_URGENT (BIT_MASK_ATIM_URGENT << BIT_SHIFT_ATIM_URGENT)\n#define BIT_CLEAR_ATIM_URGENT(x) ((x) & (~BITS_ATIM_URGENT))\n#define BIT_GET_ATIM_URGENT(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ATIM_URGENT) & BIT_MASK_ATIM_URGENT)\n#define BIT_SET_ATIM_URGENT(x, v)                                              \\\n\t(BIT_CLEAR_ATIM_URGENT(x) | BIT_ATIM_URGENT(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DIS_ATIM_V1\t\t\t\t(Offset 0x1540) */\n\n#define BIT_DIS_ATIM_P4 BIT(19)\n#define BIT_DIS_ATIM_P3 BIT(18)\n#define BIT_DIS_ATIM_P2 BIT(17)\n#define BIT_DIS_ATIM_P1 BIT(16)\n#define BIT_DIS_ATIM_VAP15 BIT(15)\n#define BIT_DIS_ATIM_VAP14 BIT(14)\n#define BIT_DIS_ATIM_VAP13 BIT(13)\n#define BIT_DIS_ATIM_VAP12 BIT(12)\n#define BIT_DIS_ATIM_VAP11 BIT(11)\n#define BIT_DIS_ATIM_VAP10 BIT(10)\n#define BIT_DIS_ATIM_VAP9 BIT(9)\n#define BIT_DIS_ATIM_VAP8 BIT(8)\n#define BIT_DIS_ATIM_ROOT_P0 BIT(0)\n\n/* 2 REG_HIQ_NO_LMT_EN_V1\t\t\t(Offset 0x1544) */\n\n#define BIT_HIQ_NO_LMT_EN_P4 BIT(19)\n#define BIT_HIQ_NO_LMT_EN_P3 BIT(18)\n#define BIT_HIQ_NO_LMT_EN_P2 BIT(17)\n#define BIT_HIQ_NO_LMT_EN_P1 BIT(16)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIQ_NO_LMT_EN_V1\t\t\t(Offset 0x1544) */\n\n#define BIT_HIQ_NO_LMT_EN_VAP15 BIT(15)\n#define BIT_HIQ_NO_LMT_EN_VAP14 BIT(14)\n#define BIT_HIQ_NO_LMT_EN_VAP13 BIT(13)\n#define BIT_HIQ_NO_LMT_EN_VAP12 BIT(12)\n#define BIT_HIQ_NO_LMT_EN_VAP11 BIT(11)\n#define BIT_HIQ_NO_LMT_EN_VAP10 BIT(10)\n#define BIT_HIQ_NO_LMT_EN_VAP9 BIT(9)\n#define BIT_HIQ_NO_LMT_EN_VAP8 BIT(8)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_HIQ_NO_LMT_EN_V1\t\t\t(Offset 0x1544) */\n\n#define BIT_HIQ_NO_LMT_EN_ROOT_P0 BIT(0)\n\n/* 2 REG_P2PPS_CTRL_V1\t\t\t(Offset 0x1548) */\n\n#define BIT_P2P_PWR_RST1_V2 BIT(15)\n#define BIT_P2P_PWR_RST0_V2 BIT(14)\n#define BIT_EN_TSFBIT32_RST_P2P_V1 BIT(13)\n\n#define BIT_SHIFT_NOA_UNIT0_SEL_V1 8\n#define BIT_MASK_NOA_UNIT0_SEL_V1 0x7\n#define BIT_NOA_UNIT0_SEL_V1(x)                                                \\\n\t(((x) & BIT_MASK_NOA_UNIT0_SEL_V1) << BIT_SHIFT_NOA_UNIT0_SEL_V1)\n#define BITS_NOA_UNIT0_SEL_V1                                                  \\\n\t(BIT_MASK_NOA_UNIT0_SEL_V1 << BIT_SHIFT_NOA_UNIT0_SEL_V1)\n#define BIT_CLEAR_NOA_UNIT0_SEL_V1(x) ((x) & (~BITS_NOA_UNIT0_SEL_V1))\n#define BIT_GET_NOA_UNIT0_SEL_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT0_SEL_V1) & BIT_MASK_NOA_UNIT0_SEL_V1)\n#define BIT_SET_NOA_UNIT0_SEL_V1(x, v)                                         \\\n\t(BIT_CLEAR_NOA_UNIT0_SEL_V1(x) | BIT_NOA_UNIT0_SEL_V1(v))\n\n#define BIT_P2P_CTW_ALLSTASLEEP_V1 BIT(7)\n#define BIT_P2P_OFF_DISTX_EN_V1 BIT(6)\n#define BIT_PWR_MGT_EN_V1 BIT(5)\n#define BIT_P2P_NOA1_EN_V1 BIT(2)\n#define BIT_P2P_NOA0_EN_V1 BIT(1)\n\n/* 2 REG_P2PPS1_CTRL_V1\t\t\t(Offset 0x154C) */\n\n#define BIT_P2P1_PWR_RST1_V2 BIT(15)\n#define BIT_P2P1_PWR_RST0_V2 BIT(14)\n#define BIT_EN_TSFBIT32_RST_P2P1_V1 BIT(13)\n\n#define BIT_SHIFT_NOA_UNIT1_SEL_V1 8\n#define BIT_MASK_NOA_UNIT1_SEL_V1 0x7\n#define BIT_NOA_UNIT1_SEL_V1(x)                                                \\\n\t(((x) & BIT_MASK_NOA_UNIT1_SEL_V1) << BIT_SHIFT_NOA_UNIT1_SEL_V1)\n#define BITS_NOA_UNIT1_SEL_V1                                                  \\\n\t(BIT_MASK_NOA_UNIT1_SEL_V1 << BIT_SHIFT_NOA_UNIT1_SEL_V1)\n#define BIT_CLEAR_NOA_UNIT1_SEL_V1(x) ((x) & (~BITS_NOA_UNIT1_SEL_V1))\n#define BIT_GET_NOA_UNIT1_SEL_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT1_SEL_V1) & BIT_MASK_NOA_UNIT1_SEL_V1)\n#define BIT_SET_NOA_UNIT1_SEL_V1(x, v)                                         \\\n\t(BIT_CLEAR_NOA_UNIT1_SEL_V1(x) | BIT_NOA_UNIT1_SEL_V1(v))\n\n#define BIT_P2P1_CTW_ALLSTASLEEP_V1 BIT(7)\n#define BIT_P2P1_PWR_MGT_EN_V1 BIT(5)\n#define BIT_P2P1_NOA1_EN_V1 BIT(2)\n#define BIT_P2P1_NOA0_EN_V1 BIT(1)\n\n/* 2 REG_P2PPS1_SPEC_STATE_V1\t\t(Offset 0x154E) */\n\n#define BIT_P2P1_SPEC_POWER_STATEP BIT(7)\n#define BIT_P2P1_SPEC_BEACON_AREA_ON BIT(5)\n\n/* 2 REG_P2PPS2_CTRL_V1\t\t\t(Offset 0x1550) */\n\n#define BIT_P2P2_PWR_RST1_V2 BIT(15)\n#define BIT_P2P2_PWR_RST0_V2 BIT(14)\n#define BIT_EN_TSFBIT32_RST_P2P2_V1 BIT(13)\n\n#define BIT_SHIFT_NOA_UNIT2_SEL_V1 8\n#define BIT_MASK_NOA_UNIT2_SEL_V1 0x7\n#define BIT_NOA_UNIT2_SEL_V1(x)                                                \\\n\t(((x) & BIT_MASK_NOA_UNIT2_SEL_V1) << BIT_SHIFT_NOA_UNIT2_SEL_V1)\n#define BITS_NOA_UNIT2_SEL_V1                                                  \\\n\t(BIT_MASK_NOA_UNIT2_SEL_V1 << BIT_SHIFT_NOA_UNIT2_SEL_V1)\n#define BIT_CLEAR_NOA_UNIT2_SEL_V1(x) ((x) & (~BITS_NOA_UNIT2_SEL_V1))\n#define BIT_GET_NOA_UNIT2_SEL_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT2_SEL_V1) & BIT_MASK_NOA_UNIT2_SEL_V1)\n#define BIT_SET_NOA_UNIT2_SEL_V1(x, v)                                         \\\n\t(BIT_CLEAR_NOA_UNIT2_SEL_V1(x) | BIT_NOA_UNIT2_SEL_V1(v))\n\n#define BIT_P2P2_CTW_ALLSTASLEEP_V1 BIT(7)\n#define BIT_P2P2_OFF_DISTX_EN_V1 BIT(6)\n#define BIT_P2P2_PWR_MGT_EN_V1 BIT(5)\n#define BIT_P2P2_NOA1_EN_V1 BIT(2)\n#define BIT_P2P2_NOA0_EN_V1 BIT(1)\n\n/* 2 REG_P2PPS2_SPEC_STATE_V1\t\t(Offset 0x1552) */\n\n#define BIT_P2P2_SPEC_POWER_STATEP BIT(7)\n#define BIT_P2P2_SPEC_BEACON_AREA_ON BIT(5)\n\n/* 2 REG_CHG_POWER_BCN_AREA\t\t\t(Offset 0x1556) */\n\n#define BIT_CHG_POWER_BCN_AREA BIT(0)\n\n/* 2 REG_NOA_SEL\t\t\t\t(Offset 0x1557) */\n\n#define BIT_SHIFT_NOA_SEL_V1 0\n#define BIT_MASK_NOA_SEL_V1 0x7\n#define BIT_NOA_SEL_V1(x) (((x) & BIT_MASK_NOA_SEL_V1) << BIT_SHIFT_NOA_SEL_V1)\n#define BITS_NOA_SEL_V1 (BIT_MASK_NOA_SEL_V1 << BIT_SHIFT_NOA_SEL_V1)\n#define BIT_CLEAR_NOA_SEL_V1(x) ((x) & (~BITS_NOA_SEL_V1))\n#define BIT_GET_NOA_SEL_V1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_NOA_SEL_V1) & BIT_MASK_NOA_SEL_V1)\n#define BIT_SET_NOA_SEL_V1(x, v) (BIT_CLEAR_NOA_SEL_V1(x) | BIT_NOA_SEL_V1(v))\n\n/* 2 REG_NOA_PARAM_3_V1\t\t\t(Offset 0x1564) */\n\n#define BIT_SHIFT_NOA_COUNT_V2 0\n#define BIT_MASK_NOA_COUNT_V2 0xffffffffL\n#define BIT_NOA_COUNT_V2(x)                                                    \\\n\t(((x) & BIT_MASK_NOA_COUNT_V2) << BIT_SHIFT_NOA_COUNT_V2)\n#define BITS_NOA_COUNT_V2 (BIT_MASK_NOA_COUNT_V2 << BIT_SHIFT_NOA_COUNT_V2)\n#define BIT_CLEAR_NOA_COUNT_V2(x) ((x) & (~BITS_NOA_COUNT_V2))\n#define BIT_GET_NOA_COUNT_V2(x)                                                \\\n\t(((x) >> BIT_SHIFT_NOA_COUNT_V2) & BIT_MASK_NOA_COUNT_V2)\n#define BIT_SET_NOA_COUNT_V2(x, v)                                             \\\n\t(BIT_CLEAR_NOA_COUNT_V2(x) | BIT_NOA_COUNT_V2(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_P2PPS_HW_AUTO_PAUSE_CTRL\t\t(Offset 0x156C) */\n\n#define BIT_P2PPS_NOA_STOP_TX_HANG BIT(31)\n#define BIT_P2PPS_MACID_PAUSE_EN BIT(11)\n#define BIT_P2PPS__MGQ_PAUSE BIT(10)\n#define BIT_P2PPS__HIQ_PAUSE BIT(9)\n#define BIT_P2PPS__BCNQ_PAUSE BIT(8)\n\n#define BIT_SHIFT_P2PPS_MACID_PAUSE 0\n#define BIT_MASK_P2PPS_MACID_PAUSE 0xff\n#define BIT_P2PPS_MACID_PAUSE(x)                                               \\\n\t(((x) & BIT_MASK_P2PPS_MACID_PAUSE) << BIT_SHIFT_P2PPS_MACID_PAUSE)\n#define BITS_P2PPS_MACID_PAUSE                                                 \\\n\t(BIT_MASK_P2PPS_MACID_PAUSE << BIT_SHIFT_P2PPS_MACID_PAUSE)\n#define BIT_CLEAR_P2PPS_MACID_PAUSE(x) ((x) & (~BITS_P2PPS_MACID_PAUSE))\n#define BIT_GET_P2PPS_MACID_PAUSE(x)                                           \\\n\t(((x) >> BIT_SHIFT_P2PPS_MACID_PAUSE) & BIT_MASK_P2PPS_MACID_PAUSE)\n#define BIT_SET_P2PPS_MACID_PAUSE(x, v)                                        \\\n\t(BIT_CLEAR_P2PPS_MACID_PAUSE(x) | BIT_P2PPS_MACID_PAUSE(v))\n\n/* 2 REG_P2PPS1_HW_AUTO_PAUSE_CTRL\t\t(Offset 0x1570) */\n\n#define BIT_P2PPS1_NOA_STOP_TX_HANG BIT(31)\n#define BIT_P2PPS1_MACID_PAUSE_EN BIT(11)\n#define BIT_P2PPS1__MGQ_PAUSE BIT(10)\n#define BIT_P2PPS1__HIQ_PAUSE BIT(9)\n#define BIT_P2PPS1__BCNQ_PAUSE BIT(8)\n\n#define BIT_SHIFT_P2PPS1_MACID_PAUSE 0\n#define BIT_MASK_P2PPS1_MACID_PAUSE 0xff\n#define BIT_P2PPS1_MACID_PAUSE(x)                                              \\\n\t(((x) & BIT_MASK_P2PPS1_MACID_PAUSE) << BIT_SHIFT_P2PPS1_MACID_PAUSE)\n#define BITS_P2PPS1_MACID_PAUSE                                                \\\n\t(BIT_MASK_P2PPS1_MACID_PAUSE << BIT_SHIFT_P2PPS1_MACID_PAUSE)\n#define BIT_CLEAR_P2PPS1_MACID_PAUSE(x) ((x) & (~BITS_P2PPS1_MACID_PAUSE))\n#define BIT_GET_P2PPS1_MACID_PAUSE(x)                                          \\\n\t(((x) >> BIT_SHIFT_P2PPS1_MACID_PAUSE) & BIT_MASK_P2PPS1_MACID_PAUSE)\n#define BIT_SET_P2PPS1_MACID_PAUSE(x, v)                                       \\\n\t(BIT_CLEAR_P2PPS1_MACID_PAUSE(x) | BIT_P2PPS1_MACID_PAUSE(v))\n\n/* 2 REG_P2PPS2_HW_AUTO_PAUSE_CTRL\t\t(Offset 0x1574) */\n\n#define BIT_P2PPS2_NOA_STOP_TX_HANG BIT(31)\n#define BIT_P2PPS2_MACID_PAUSE_EN BIT(11)\n#define BIT_P2PPS2__MGQ_PAUSE BIT(10)\n#define BIT_P2PPS2__HIQ_PAUSE BIT(9)\n#define BIT_P2PPS2__BCNQ_PAUSE BIT(8)\n\n#define BIT_SHIFT_P2PPS2_MACID_PAUSE 0\n#define BIT_MASK_P2PPS2_MACID_PAUSE 0xff\n#define BIT_P2PPS2_MACID_PAUSE(x)                                              \\\n\t(((x) & BIT_MASK_P2PPS2_MACID_PAUSE) << BIT_SHIFT_P2PPS2_MACID_PAUSE)\n#define BITS_P2PPS2_MACID_PAUSE                                                \\\n\t(BIT_MASK_P2PPS2_MACID_PAUSE << BIT_SHIFT_P2PPS2_MACID_PAUSE)\n#define BIT_CLEAR_P2PPS2_MACID_PAUSE(x) ((x) & (~BITS_P2PPS2_MACID_PAUSE))\n#define BIT_GET_P2PPS2_MACID_PAUSE(x)                                          \\\n\t(((x) >> BIT_SHIFT_P2PPS2_MACID_PAUSE) & BIT_MASK_P2PPS2_MACID_PAUSE)\n#define BIT_SET_P2PPS2_MACID_PAUSE(x, v)                                       \\\n\t(BIT_CLEAR_P2PPS2_MACID_PAUSE(x) | BIT_P2PPS2_MACID_PAUSE(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_RX_TBTT_SHIFT\t\t\t(Offset 0x1578) */\n\n#define BIT_SHIFT_RX_TBTT_SHIFT_SEL 24\n#define BIT_MASK_RX_TBTT_SHIFT_SEL 0x7\n#define BIT_RX_TBTT_SHIFT_SEL(x)                                               \\\n\t(((x) & BIT_MASK_RX_TBTT_SHIFT_SEL) << BIT_SHIFT_RX_TBTT_SHIFT_SEL)\n#define BITS_RX_TBTT_SHIFT_SEL                                                 \\\n\t(BIT_MASK_RX_TBTT_SHIFT_SEL << BIT_SHIFT_RX_TBTT_SHIFT_SEL)\n#define BIT_CLEAR_RX_TBTT_SHIFT_SEL(x) ((x) & (~BITS_RX_TBTT_SHIFT_SEL))\n#define BIT_GET_RX_TBTT_SHIFT_SEL(x)                                           \\\n\t(((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL) & BIT_MASK_RX_TBTT_SHIFT_SEL)\n#define BIT_SET_RX_TBTT_SHIFT_SEL(x, v)                                        \\\n\t(BIT_CLEAR_RX_TBTT_SHIFT_SEL(x) | BIT_RX_TBTT_SHIFT_SEL(v))\n\n#define BIT_RX_TBTT_SHIFT_RW_FLAG BIT(15)\n\n#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET 0\n#define BIT_MASK_RX_TBTT_SHIFT_OFFSET 0xfff\n#define BIT_RX_TBTT_SHIFT_OFFSET(x)                                            \\\n\t(((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET)                                 \\\n\t << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET)\n#define BITS_RX_TBTT_SHIFT_OFFSET                                              \\\n\t(BIT_MASK_RX_TBTT_SHIFT_OFFSET << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET)\n#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET(x) ((x) & (~BITS_RX_TBTT_SHIFT_OFFSET))\n#define BIT_GET_RX_TBTT_SHIFT_OFFSET(x)                                        \\\n\t(((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET) &                             \\\n\t BIT_MASK_RX_TBTT_SHIFT_OFFSET)\n#define BIT_SET_RX_TBTT_SHIFT_OFFSET(x, v)                                     \\\n\t(BIT_CLEAR_RX_TBTT_SHIFT_OFFSET(x) | BIT_RX_TBTT_SHIFT_OFFSET(v))\n\n/* 2 REG_FREERUN_CNT_LOW\t\t\t(Offset 0x1580) */\n\n#define BIT_SHIFT_FREERUN_CNT_LOW 0\n#define BIT_MASK_FREERUN_CNT_LOW 0xffffffffL\n#define BIT_FREERUN_CNT_LOW(x)                                                 \\\n\t(((x) & BIT_MASK_FREERUN_CNT_LOW) << BIT_SHIFT_FREERUN_CNT_LOW)\n#define BITS_FREERUN_CNT_LOW                                                   \\\n\t(BIT_MASK_FREERUN_CNT_LOW << BIT_SHIFT_FREERUN_CNT_LOW)\n#define BIT_CLEAR_FREERUN_CNT_LOW(x) ((x) & (~BITS_FREERUN_CNT_LOW))\n#define BIT_GET_FREERUN_CNT_LOW(x)                                             \\\n\t(((x) >> BIT_SHIFT_FREERUN_CNT_LOW) & BIT_MASK_FREERUN_CNT_LOW)\n#define BIT_SET_FREERUN_CNT_LOW(x, v)                                          \\\n\t(BIT_CLEAR_FREERUN_CNT_LOW(x) | BIT_FREERUN_CNT_LOW(v))\n\n/* 2 REG_FREERUN_CNT_HIGH\t\t\t(Offset 0x1584) */\n\n#define BIT_SHIFT_FREERUN_CNT_HIGH 0\n#define BIT_MASK_FREERUN_CNT_HIGH 0xffffffffL\n#define BIT_FREERUN_CNT_HIGH(x)                                                \\\n\t(((x) & BIT_MASK_FREERUN_CNT_HIGH) << BIT_SHIFT_FREERUN_CNT_HIGH)\n#define BITS_FREERUN_CNT_HIGH                                                  \\\n\t(BIT_MASK_FREERUN_CNT_HIGH << BIT_SHIFT_FREERUN_CNT_HIGH)\n#define BIT_CLEAR_FREERUN_CNT_HIGH(x) ((x) & (~BITS_FREERUN_CNT_HIGH))\n#define BIT_GET_FREERUN_CNT_HIGH(x)                                            \\\n\t(((x) >> BIT_SHIFT_FREERUN_CNT_HIGH) & BIT_MASK_FREERUN_CNT_HIGH)\n#define BIT_SET_FREERUN_CNT_HIGH(x, v)                                         \\\n\t(BIT_CLEAR_FREERUN_CNT_HIGH(x) | BIT_FREERUN_CNT_HIGH(v))\n\n/* 2 REG_PS_TIMER_0\t\t\t\t(Offset 0x158C) */\n\n#define BIT_SHIFT_PS_TIMER_0 0\n#define BIT_MASK_PS_TIMER_0 0xffffffffL\n#define BIT_PS_TIMER_0(x) (((x) & BIT_MASK_PS_TIMER_0) << BIT_SHIFT_PS_TIMER_0)\n#define BITS_PS_TIMER_0 (BIT_MASK_PS_TIMER_0 << BIT_SHIFT_PS_TIMER_0)\n#define BIT_CLEAR_PS_TIMER_0(x) ((x) & (~BITS_PS_TIMER_0))\n#define BIT_GET_PS_TIMER_0(x)                                                  \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_0) & BIT_MASK_PS_TIMER_0)\n#define BIT_SET_PS_TIMER_0(x, v) (BIT_CLEAR_PS_TIMER_0(x) | BIT_PS_TIMER_0(v))\n\n/* 2 REG_PS_TIMER_1\t\t\t\t(Offset 0x1590) */\n\n#define BIT_SHIFT_PS_TIMER_1 0\n#define BIT_MASK_PS_TIMER_1 0xffffffffL\n#define BIT_PS_TIMER_1(x) (((x) & BIT_MASK_PS_TIMER_1) << BIT_SHIFT_PS_TIMER_1)\n#define BITS_PS_TIMER_1 (BIT_MASK_PS_TIMER_1 << BIT_SHIFT_PS_TIMER_1)\n#define BIT_CLEAR_PS_TIMER_1(x) ((x) & (~BITS_PS_TIMER_1))\n#define BIT_GET_PS_TIMER_1(x)                                                  \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_1) & BIT_MASK_PS_TIMER_1)\n#define BIT_SET_PS_TIMER_1(x, v) (BIT_CLEAR_PS_TIMER_1(x) | BIT_PS_TIMER_1(v))\n\n/* 2 REG_PS_TIMER_2\t\t\t\t(Offset 0x1594) */\n\n#define BIT_SHIFT_PS_TIMER_2 0\n#define BIT_MASK_PS_TIMER_2 0xffffffffL\n#define BIT_PS_TIMER_2(x) (((x) & BIT_MASK_PS_TIMER_2) << BIT_SHIFT_PS_TIMER_2)\n#define BITS_PS_TIMER_2 (BIT_MASK_PS_TIMER_2 << BIT_SHIFT_PS_TIMER_2)\n#define BIT_CLEAR_PS_TIMER_2(x) ((x) & (~BITS_PS_TIMER_2))\n#define BIT_GET_PS_TIMER_2(x)                                                  \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_2) & BIT_MASK_PS_TIMER_2)\n#define BIT_SET_PS_TIMER_2(x, v) (BIT_CLEAR_PS_TIMER_2(x) | BIT_PS_TIMER_2(v))\n\n/* 2 REG_PS_TIMER_3\t\t\t\t(Offset 0x1598) */\n\n#define BIT_SHIFT_PS_TIMER_3 0\n#define BIT_MASK_PS_TIMER_3 0xffffffffL\n#define BIT_PS_TIMER_3(x) (((x) & BIT_MASK_PS_TIMER_3) << BIT_SHIFT_PS_TIMER_3)\n#define BITS_PS_TIMER_3 (BIT_MASK_PS_TIMER_3 << BIT_SHIFT_PS_TIMER_3)\n#define BIT_CLEAR_PS_TIMER_3(x) ((x) & (~BITS_PS_TIMER_3))\n#define BIT_GET_PS_TIMER_3(x)                                                  \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_3) & BIT_MASK_PS_TIMER_3)\n#define BIT_SET_PS_TIMER_3(x, v) (BIT_CLEAR_PS_TIMER_3(x) | BIT_PS_TIMER_3(v))\n\n/* 2 REG_PS_TIMER_4\t\t\t\t(Offset 0x159C) */\n\n#define BIT_SHIFT_PS_TIMER_4 0\n#define BIT_MASK_PS_TIMER_4 0xffffffffL\n#define BIT_PS_TIMER_4(x) (((x) & BIT_MASK_PS_TIMER_4) << BIT_SHIFT_PS_TIMER_4)\n#define BITS_PS_TIMER_4 (BIT_MASK_PS_TIMER_4 << BIT_SHIFT_PS_TIMER_4)\n#define BIT_CLEAR_PS_TIMER_4(x) ((x) & (~BITS_PS_TIMER_4))\n#define BIT_GET_PS_TIMER_4(x)                                                  \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_4) & BIT_MASK_PS_TIMER_4)\n#define BIT_SET_PS_TIMER_4(x, v) (BIT_CLEAR_PS_TIMER_4(x) | BIT_PS_TIMER_4(v))\n\n/* 2 REG_PS_TIMER_5\t\t\t\t(Offset 0x15A0) */\n\n#define BIT_SHIFT_PS_TIMER_5 0\n#define BIT_MASK_PS_TIMER_5 0xffffffffL\n#define BIT_PS_TIMER_5(x) (((x) & BIT_MASK_PS_TIMER_5) << BIT_SHIFT_PS_TIMER_5)\n#define BITS_PS_TIMER_5 (BIT_MASK_PS_TIMER_5 << BIT_SHIFT_PS_TIMER_5)\n#define BIT_CLEAR_PS_TIMER_5(x) ((x) & (~BITS_PS_TIMER_5))\n#define BIT_GET_PS_TIMER_5(x)                                                  \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_5) & BIT_MASK_PS_TIMER_5)\n#define BIT_SET_PS_TIMER_5(x, v) (BIT_CLEAR_PS_TIMER_5(x) | BIT_PS_TIMER_5(v))\n\n/* 2 REG_PS_TIMER_01_CTRL\t\t\t(Offset 0x15A4) */\n\n#define BIT_SHIFT_PS_TIMER_1_EARLY_TIME 24\n#define BIT_MASK_PS_TIMER_1_EARLY_TIME 0xff\n#define BIT_PS_TIMER_1_EARLY_TIME(x)                                           \\\n\t(((x) & BIT_MASK_PS_TIMER_1_EARLY_TIME)                                \\\n\t << BIT_SHIFT_PS_TIMER_1_EARLY_TIME)\n#define BITS_PS_TIMER_1_EARLY_TIME                                             \\\n\t(BIT_MASK_PS_TIMER_1_EARLY_TIME << BIT_SHIFT_PS_TIMER_1_EARLY_TIME)\n#define BIT_CLEAR_PS_TIMER_1_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_1_EARLY_TIME))\n#define BIT_GET_PS_TIMER_1_EARLY_TIME(x)                                       \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_1_EARLY_TIME) &                            \\\n\t BIT_MASK_PS_TIMER_1_EARLY_TIME)\n#define BIT_SET_PS_TIMER_1_EARLY_TIME(x, v)                                    \\\n\t(BIT_CLEAR_PS_TIMER_1_EARLY_TIME(x) | BIT_PS_TIMER_1_EARLY_TIME(v))\n\n#define BIT_PS_TIMER_1_EN BIT(23)\n\n#define BIT_SHIFT_PS_TIMER_1_TSF_SEL 16\n#define BIT_MASK_PS_TIMER_1_TSF_SEL 0x7\n#define BIT_PS_TIMER_1_TSF_SEL(x)                                              \\\n\t(((x) & BIT_MASK_PS_TIMER_1_TSF_SEL) << BIT_SHIFT_PS_TIMER_1_TSF_SEL)\n#define BITS_PS_TIMER_1_TSF_SEL                                                \\\n\t(BIT_MASK_PS_TIMER_1_TSF_SEL << BIT_SHIFT_PS_TIMER_1_TSF_SEL)\n#define BIT_CLEAR_PS_TIMER_1_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_1_TSF_SEL))\n#define BIT_GET_PS_TIMER_1_TSF_SEL(x)                                          \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_1_TSF_SEL) & BIT_MASK_PS_TIMER_1_TSF_SEL)\n#define BIT_SET_PS_TIMER_1_TSF_SEL(x, v)                                       \\\n\t(BIT_CLEAR_PS_TIMER_1_TSF_SEL(x) | BIT_PS_TIMER_1_TSF_SEL(v))\n\n#define BIT_SHIFT_PS_TIMER_0_EARLY_TIME 8\n#define BIT_MASK_PS_TIMER_0_EARLY_TIME 0xff\n#define BIT_PS_TIMER_0_EARLY_TIME(x)                                           \\\n\t(((x) & BIT_MASK_PS_TIMER_0_EARLY_TIME)                                \\\n\t << BIT_SHIFT_PS_TIMER_0_EARLY_TIME)\n#define BITS_PS_TIMER_0_EARLY_TIME                                             \\\n\t(BIT_MASK_PS_TIMER_0_EARLY_TIME << BIT_SHIFT_PS_TIMER_0_EARLY_TIME)\n#define BIT_CLEAR_PS_TIMER_0_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_0_EARLY_TIME))\n#define BIT_GET_PS_TIMER_0_EARLY_TIME(x)                                       \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_0_EARLY_TIME) &                            \\\n\t BIT_MASK_PS_TIMER_0_EARLY_TIME)\n#define BIT_SET_PS_TIMER_0_EARLY_TIME(x, v)                                    \\\n\t(BIT_CLEAR_PS_TIMER_0_EARLY_TIME(x) | BIT_PS_TIMER_0_EARLY_TIME(v))\n\n#define BIT_PS_TIMER_0_EN BIT(7)\n\n#define BIT_SHIFT_PS_TIMER_0_TSF_SEL 0\n#define BIT_MASK_PS_TIMER_0_TSF_SEL 0x7\n#define BIT_PS_TIMER_0_TSF_SEL(x)                                              \\\n\t(((x) & BIT_MASK_PS_TIMER_0_TSF_SEL) << BIT_SHIFT_PS_TIMER_0_TSF_SEL)\n#define BITS_PS_TIMER_0_TSF_SEL                                                \\\n\t(BIT_MASK_PS_TIMER_0_TSF_SEL << BIT_SHIFT_PS_TIMER_0_TSF_SEL)\n#define BIT_CLEAR_PS_TIMER_0_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_0_TSF_SEL))\n#define BIT_GET_PS_TIMER_0_TSF_SEL(x)                                          \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_0_TSF_SEL) & BIT_MASK_PS_TIMER_0_TSF_SEL)\n#define BIT_SET_PS_TIMER_0_TSF_SEL(x, v)                                       \\\n\t(BIT_CLEAR_PS_TIMER_0_TSF_SEL(x) | BIT_PS_TIMER_0_TSF_SEL(v))\n\n/* 2 REG_PS_TIMER_23_CTRL\t\t\t(Offset 0x15A8) */\n\n#define BIT_SHIFT_PS_TIMER_3_EARLY_TIME 24\n#define BIT_MASK_PS_TIMER_3_EARLY_TIME 0xff\n#define BIT_PS_TIMER_3_EARLY_TIME(x)                                           \\\n\t(((x) & BIT_MASK_PS_TIMER_3_EARLY_TIME)                                \\\n\t << BIT_SHIFT_PS_TIMER_3_EARLY_TIME)\n#define BITS_PS_TIMER_3_EARLY_TIME                                             \\\n\t(BIT_MASK_PS_TIMER_3_EARLY_TIME << BIT_SHIFT_PS_TIMER_3_EARLY_TIME)\n#define BIT_CLEAR_PS_TIMER_3_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_3_EARLY_TIME))\n#define BIT_GET_PS_TIMER_3_EARLY_TIME(x)                                       \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_3_EARLY_TIME) &                            \\\n\t BIT_MASK_PS_TIMER_3_EARLY_TIME)\n#define BIT_SET_PS_TIMER_3_EARLY_TIME(x, v)                                    \\\n\t(BIT_CLEAR_PS_TIMER_3_EARLY_TIME(x) | BIT_PS_TIMER_3_EARLY_TIME(v))\n\n#define BIT_PS_TIMER_3_EN BIT(23)\n\n#define BIT_SHIFT_PS_TIMER_3_TSF_SEL 16\n#define BIT_MASK_PS_TIMER_3_TSF_SEL 0x7\n#define BIT_PS_TIMER_3_TSF_SEL(x)                                              \\\n\t(((x) & BIT_MASK_PS_TIMER_3_TSF_SEL) << BIT_SHIFT_PS_TIMER_3_TSF_SEL)\n#define BITS_PS_TIMER_3_TSF_SEL                                                \\\n\t(BIT_MASK_PS_TIMER_3_TSF_SEL << BIT_SHIFT_PS_TIMER_3_TSF_SEL)\n#define BIT_CLEAR_PS_TIMER_3_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_3_TSF_SEL))\n#define BIT_GET_PS_TIMER_3_TSF_SEL(x)                                          \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_3_TSF_SEL) & BIT_MASK_PS_TIMER_3_TSF_SEL)\n#define BIT_SET_PS_TIMER_3_TSF_SEL(x, v)                                       \\\n\t(BIT_CLEAR_PS_TIMER_3_TSF_SEL(x) | BIT_PS_TIMER_3_TSF_SEL(v))\n\n#define BIT_SHIFT_PS_TIMER_2_EARLY_TIME 8\n#define BIT_MASK_PS_TIMER_2_EARLY_TIME 0xff\n#define BIT_PS_TIMER_2_EARLY_TIME(x)                                           \\\n\t(((x) & BIT_MASK_PS_TIMER_2_EARLY_TIME)                                \\\n\t << BIT_SHIFT_PS_TIMER_2_EARLY_TIME)\n#define BITS_PS_TIMER_2_EARLY_TIME                                             \\\n\t(BIT_MASK_PS_TIMER_2_EARLY_TIME << BIT_SHIFT_PS_TIMER_2_EARLY_TIME)\n#define BIT_CLEAR_PS_TIMER_2_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_2_EARLY_TIME))\n#define BIT_GET_PS_TIMER_2_EARLY_TIME(x)                                       \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_2_EARLY_TIME) &                            \\\n\t BIT_MASK_PS_TIMER_2_EARLY_TIME)\n#define BIT_SET_PS_TIMER_2_EARLY_TIME(x, v)                                    \\\n\t(BIT_CLEAR_PS_TIMER_2_EARLY_TIME(x) | BIT_PS_TIMER_2_EARLY_TIME(v))\n\n#define BIT_PS_TIMER_2_EN BIT(7)\n\n#define BIT_SHIFT_PS_TIMER_2_TSF_SEL 0\n#define BIT_MASK_PS_TIMER_2_TSF_SEL 0x7\n#define BIT_PS_TIMER_2_TSF_SEL(x)                                              \\\n\t(((x) & BIT_MASK_PS_TIMER_2_TSF_SEL) << BIT_SHIFT_PS_TIMER_2_TSF_SEL)\n#define BITS_PS_TIMER_2_TSF_SEL                                                \\\n\t(BIT_MASK_PS_TIMER_2_TSF_SEL << BIT_SHIFT_PS_TIMER_2_TSF_SEL)\n#define BIT_CLEAR_PS_TIMER_2_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_2_TSF_SEL))\n#define BIT_GET_PS_TIMER_2_TSF_SEL(x)                                          \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_2_TSF_SEL) & BIT_MASK_PS_TIMER_2_TSF_SEL)\n#define BIT_SET_PS_TIMER_2_TSF_SEL(x, v)                                       \\\n\t(BIT_CLEAR_PS_TIMER_2_TSF_SEL(x) | BIT_PS_TIMER_2_TSF_SEL(v))\n\n/* 2 REG_PS_TIMER_45_CTRL\t\t\t(Offset 0x15AC) */\n\n#define BIT_SHIFT_PS_TIMER_5_EARLY_TIME 24\n#define BIT_MASK_PS_TIMER_5_EARLY_TIME 0xff\n#define BIT_PS_TIMER_5_EARLY_TIME(x)                                           \\\n\t(((x) & BIT_MASK_PS_TIMER_5_EARLY_TIME)                                \\\n\t << BIT_SHIFT_PS_TIMER_5_EARLY_TIME)\n#define BITS_PS_TIMER_5_EARLY_TIME                                             \\\n\t(BIT_MASK_PS_TIMER_5_EARLY_TIME << BIT_SHIFT_PS_TIMER_5_EARLY_TIME)\n#define BIT_CLEAR_PS_TIMER_5_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_5_EARLY_TIME))\n#define BIT_GET_PS_TIMER_5_EARLY_TIME(x)                                       \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_5_EARLY_TIME) &                            \\\n\t BIT_MASK_PS_TIMER_5_EARLY_TIME)\n#define BIT_SET_PS_TIMER_5_EARLY_TIME(x, v)                                    \\\n\t(BIT_CLEAR_PS_TIMER_5_EARLY_TIME(x) | BIT_PS_TIMER_5_EARLY_TIME(v))\n\n#define BIT_PS_TIMER_5_EN BIT(23)\n\n#define BIT_SHIFT_PS_TIMER_5_TSF_SEL 16\n#define BIT_MASK_PS_TIMER_5_TSF_SEL 0x7\n#define BIT_PS_TIMER_5_TSF_SEL(x)                                              \\\n\t(((x) & BIT_MASK_PS_TIMER_5_TSF_SEL) << BIT_SHIFT_PS_TIMER_5_TSF_SEL)\n#define BITS_PS_TIMER_5_TSF_SEL                                                \\\n\t(BIT_MASK_PS_TIMER_5_TSF_SEL << BIT_SHIFT_PS_TIMER_5_TSF_SEL)\n#define BIT_CLEAR_PS_TIMER_5_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_5_TSF_SEL))\n#define BIT_GET_PS_TIMER_5_TSF_SEL(x)                                          \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_5_TSF_SEL) & BIT_MASK_PS_TIMER_5_TSF_SEL)\n#define BIT_SET_PS_TIMER_5_TSF_SEL(x, v)                                       \\\n\t(BIT_CLEAR_PS_TIMER_5_TSF_SEL(x) | BIT_PS_TIMER_5_TSF_SEL(v))\n\n#define BIT_SHIFT_PS_TIMER_4_EARLY_TIME 8\n#define BIT_MASK_PS_TIMER_4_EARLY_TIME 0xff\n#define BIT_PS_TIMER_4_EARLY_TIME(x)                                           \\\n\t(((x) & BIT_MASK_PS_TIMER_4_EARLY_TIME)                                \\\n\t << BIT_SHIFT_PS_TIMER_4_EARLY_TIME)\n#define BITS_PS_TIMER_4_EARLY_TIME                                             \\\n\t(BIT_MASK_PS_TIMER_4_EARLY_TIME << BIT_SHIFT_PS_TIMER_4_EARLY_TIME)\n#define BIT_CLEAR_PS_TIMER_4_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_4_EARLY_TIME))\n#define BIT_GET_PS_TIMER_4_EARLY_TIME(x)                                       \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_4_EARLY_TIME) &                            \\\n\t BIT_MASK_PS_TIMER_4_EARLY_TIME)\n#define BIT_SET_PS_TIMER_4_EARLY_TIME(x, v)                                    \\\n\t(BIT_CLEAR_PS_TIMER_4_EARLY_TIME(x) | BIT_PS_TIMER_4_EARLY_TIME(v))\n\n#define BIT_PS_TIMER_4_EN BIT(7)\n\n#define BIT_SHIFT_PS_TIMER_4_TSF_SEL 0\n#define BIT_MASK_PS_TIMER_4_TSF_SEL 0x7\n#define BIT_PS_TIMER_4_TSF_SEL(x)                                              \\\n\t(((x) & BIT_MASK_PS_TIMER_4_TSF_SEL) << BIT_SHIFT_PS_TIMER_4_TSF_SEL)\n#define BITS_PS_TIMER_4_TSF_SEL                                                \\\n\t(BIT_MASK_PS_TIMER_4_TSF_SEL << BIT_SHIFT_PS_TIMER_4_TSF_SEL)\n#define BIT_CLEAR_PS_TIMER_4_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_4_TSF_SEL))\n#define BIT_GET_PS_TIMER_4_TSF_SEL(x)                                          \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_4_TSF_SEL) & BIT_MASK_PS_TIMER_4_TSF_SEL)\n#define BIT_SET_PS_TIMER_4_TSF_SEL(x, v)                                       \\\n\t(BIT_CLEAR_PS_TIMER_4_TSF_SEL(x) | BIT_PS_TIMER_4_TSF_SEL(v))\n\n/* 2 REG_CPUMGQ_FREERUN_TIMER_CTRL\t\t(Offset 0x15B0) */\n\n#define BIT_FREECNT_RST_V1 BIT(23)\n#define BIT_EN_FREECNT_V1 BIT(16)\n\n#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1 8\n#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1 0xff\n#define BIT_CPUMGQ_TX_TIMER_EARLY_V1(x)                                        \\\n\t(((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1)                             \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1)\n#define BITS_CPUMGQ_TX_TIMER_EARLY_V1                                          \\\n\t(BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1                                     \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1)\n#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1(x)                                  \\\n\t((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_V1))\n#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_V1(x)                                    \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1) &                         \\\n\t BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1)\n#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_V1(x, v)                                 \\\n\t(BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1(x) |                               \\\n\t BIT_CPUMGQ_TX_TIMER_EARLY_V1(v))\n\n#define BIT_CPUMGQ_TIMER_EN_V1 BIT(7)\n#define BIT_CPUMGQ_DROP_BY_HOLDTIME BIT(5)\n#define BIT_CPUMGQ_TX_EN_V1 BIT(4)\n\n#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1 0\n#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1 0x7\n#define BIT_CPUMGQ_TIMER_TSF_SEL_V1(x)                                         \\\n\t(((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1)                              \\\n\t << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1)\n#define BITS_CPUMGQ_TIMER_TSF_SEL_V1                                           \\\n\t(BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1)\n#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1(x)                                   \\\n\t((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_V1))\n#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_V1(x)                                     \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1) &                          \\\n\t BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1)\n#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_V1(x, v)                                  \\\n\t(BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1(x) | BIT_CPUMGQ_TIMER_TSF_SEL_V1(v))\n\n/* 2 REG_CPUMGQ_PROHIBIT\t\t\t(Offset 0x15B4) */\n\n#define BIT_SHIFT_CPUMGQ_HOLD_TIME 8\n#define BIT_MASK_CPUMGQ_HOLD_TIME 0xfff\n#define BIT_CPUMGQ_HOLD_TIME(x)                                                \\\n\t(((x) & BIT_MASK_CPUMGQ_HOLD_TIME) << BIT_SHIFT_CPUMGQ_HOLD_TIME)\n#define BITS_CPUMGQ_HOLD_TIME                                                  \\\n\t(BIT_MASK_CPUMGQ_HOLD_TIME << BIT_SHIFT_CPUMGQ_HOLD_TIME)\n#define BIT_CLEAR_CPUMGQ_HOLD_TIME(x) ((x) & (~BITS_CPUMGQ_HOLD_TIME))\n#define BIT_GET_CPUMGQ_HOLD_TIME(x)                                            \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_HOLD_TIME) & BIT_MASK_CPUMGQ_HOLD_TIME)\n#define BIT_SET_CPUMGQ_HOLD_TIME(x, v)                                         \\\n\t(BIT_CLEAR_CPUMGQ_HOLD_TIME(x) | BIT_CPUMGQ_HOLD_TIME(v))\n\n#define BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP 0\n#define BIT_MASK_CPUMGQ_PROHIBIT_SETUP 0xf\n#define BIT_CPUMGQ_PROHIBIT_SETUP(x)                                           \\\n\t(((x) & BIT_MASK_CPUMGQ_PROHIBIT_SETUP)                                \\\n\t << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP)\n#define BITS_CPUMGQ_PROHIBIT_SETUP                                             \\\n\t(BIT_MASK_CPUMGQ_PROHIBIT_SETUP << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP)\n#define BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP(x) ((x) & (~BITS_CPUMGQ_PROHIBIT_SETUP))\n#define BIT_GET_CPUMGQ_PROHIBIT_SETUP(x)                                       \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP) &                            \\\n\t BIT_MASK_CPUMGQ_PROHIBIT_SETUP)\n#define BIT_SET_CPUMGQ_PROHIBIT_SETUP(x, v)                                    \\\n\t(BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP(x) | BIT_CPUMGQ_PROHIBIT_SETUP(v))\n\n/* 2 REG_TIMER_COMPARE\t\t\t(Offset 0x15C0) */\n\n#define BIT_COMP_TRIGGER BIT(7)\n\n#define BIT_SHIFT_Y_COMP 4\n#define BIT_MASK_Y_COMP 0x7\n#define BIT_Y_COMP(x) (((x) & BIT_MASK_Y_COMP) << BIT_SHIFT_Y_COMP)\n#define BITS_Y_COMP (BIT_MASK_Y_COMP << BIT_SHIFT_Y_COMP)\n#define BIT_CLEAR_Y_COMP(x) ((x) & (~BITS_Y_COMP))\n#define BIT_GET_Y_COMP(x) (((x) >> BIT_SHIFT_Y_COMP) & BIT_MASK_Y_COMP)\n#define BIT_SET_Y_COMP(x, v) (BIT_CLEAR_Y_COMP(x) | BIT_Y_COMP(v))\n\n#define BIT_X_COMP_Y_OVERFLOW BIT(3)\n\n#define BIT_SHIFT_X_COMP 0\n#define BIT_MASK_X_COMP 0x7\n#define BIT_X_COMP(x) (((x) & BIT_MASK_X_COMP) << BIT_SHIFT_X_COMP)\n#define BITS_X_COMP (BIT_MASK_X_COMP << BIT_SHIFT_X_COMP)\n#define BIT_CLEAR_X_COMP(x) ((x) & (~BITS_X_COMP))\n#define BIT_GET_X_COMP(x) (((x) >> BIT_SHIFT_X_COMP) & BIT_MASK_X_COMP)\n#define BIT_SET_X_COMP(x, v) (BIT_CLEAR_X_COMP(x) | BIT_X_COMP(v))\n\n/* 2 REG_TIMER_COMPARE_VALUE_LOW\t\t(Offset 0x15C4) */\n\n#define BIT_SHIFT_COMP_VALUE_LOW 0\n#define BIT_MASK_COMP_VALUE_LOW 0xffffffffL\n#define BIT_COMP_VALUE_LOW(x)                                                  \\\n\t(((x) & BIT_MASK_COMP_VALUE_LOW) << BIT_SHIFT_COMP_VALUE_LOW)\n#define BITS_COMP_VALUE_LOW                                                    \\\n\t(BIT_MASK_COMP_VALUE_LOW << BIT_SHIFT_COMP_VALUE_LOW)\n#define BIT_CLEAR_COMP_VALUE_LOW(x) ((x) & (~BITS_COMP_VALUE_LOW))\n#define BIT_GET_COMP_VALUE_LOW(x)                                              \\\n\t(((x) >> BIT_SHIFT_COMP_VALUE_LOW) & BIT_MASK_COMP_VALUE_LOW)\n#define BIT_SET_COMP_VALUE_LOW(x, v)                                           \\\n\t(BIT_CLEAR_COMP_VALUE_LOW(x) | BIT_COMP_VALUE_LOW(v))\n\n/* 2 REG_TIMER_COMPARE_VALUE_HIGH\t\t(Offset 0x15C8) */\n\n#define BIT_SHIFT_COMP_VALUE_HIGH 0\n#define BIT_MASK_COMP_VALUE_HIGH 0xffffffffL\n#define BIT_COMP_VALUE_HIGH(x)                                                 \\\n\t(((x) & BIT_MASK_COMP_VALUE_HIGH) << BIT_SHIFT_COMP_VALUE_HIGH)\n#define BITS_COMP_VALUE_HIGH                                                   \\\n\t(BIT_MASK_COMP_VALUE_HIGH << BIT_SHIFT_COMP_VALUE_HIGH)\n#define BIT_CLEAR_COMP_VALUE_HIGH(x) ((x) & (~BITS_COMP_VALUE_HIGH))\n#define BIT_GET_COMP_VALUE_HIGH(x)                                             \\\n\t(((x) >> BIT_SHIFT_COMP_VALUE_HIGH) & BIT_MASK_COMP_VALUE_HIGH)\n#define BIT_SET_COMP_VALUE_HIGH(x, v)                                          \\\n\t(BIT_CLEAR_COMP_VALUE_HIGH(x) | BIT_COMP_VALUE_HIGH(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_SCHEDULER_COUNTER\t\t\t(Offset 0x15D0) */\n\n#define BIT_SHIFT_SCHEDULER_COUNTER 16\n#define BIT_MASK_SCHEDULER_COUNTER 0xffff\n#define BIT_SCHEDULER_COUNTER(x)                                               \\\n\t(((x) & BIT_MASK_SCHEDULER_COUNTER) << BIT_SHIFT_SCHEDULER_COUNTER)\n#define BITS_SCHEDULER_COUNTER                                                 \\\n\t(BIT_MASK_SCHEDULER_COUNTER << BIT_SHIFT_SCHEDULER_COUNTER)\n#define BIT_CLEAR_SCHEDULER_COUNTER(x) ((x) & (~BITS_SCHEDULER_COUNTER))\n#define BIT_GET_SCHEDULER_COUNTER(x)                                           \\\n\t(((x) >> BIT_SHIFT_SCHEDULER_COUNTER) & BIT_MASK_SCHEDULER_COUNTER)\n#define BIT_SET_SCHEDULER_COUNTER(x, v)                                        \\\n\t(BIT_CLEAR_SCHEDULER_COUNTER(x) | BIT_SCHEDULER_COUNTER(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SCHEDULER_COUNTER\t\t\t(Offset 0x15D0) */\n\n#define BIT_SHIFT__SCHEDULER_COUNTER 16\n#define BIT_MASK__SCHEDULER_COUNTER 0xffff\n#define BIT__SCHEDULER_COUNTER(x)                                              \\\n\t(((x) & BIT_MASK__SCHEDULER_COUNTER) << BIT_SHIFT__SCHEDULER_COUNTER)\n#define BITS__SCHEDULER_COUNTER                                                \\\n\t(BIT_MASK__SCHEDULER_COUNTER << BIT_SHIFT__SCHEDULER_COUNTER)\n#define BIT_CLEAR__SCHEDULER_COUNTER(x) ((x) & (~BITS__SCHEDULER_COUNTER))\n#define BIT_GET__SCHEDULER_COUNTER(x)                                          \\\n\t(((x) >> BIT_SHIFT__SCHEDULER_COUNTER) & BIT_MASK__SCHEDULER_COUNTER)\n#define BIT_SET__SCHEDULER_COUNTER(x, v)                                       \\\n\t(BIT_CLEAR__SCHEDULER_COUNTER(x) | BIT__SCHEDULER_COUNTER(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n/* 2 REG_SCHEDULER_COUNTER\t\t\t(Offset 0x15D0) */\n\n#define BIT_SCHEDULER_COUNTER_RST BIT(8)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SCHEDULER_COUNTER\t\t\t(Offset 0x15D0) */\n\n#define BIT__SCHEDULER_COUNTER_RST BIT(8)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_SCHEDULER_COUNTER\t\t\t(Offset 0x15D0) */\n\n#define BIT_SHIFT_SCHEDULER_COUNTER_SEL 0\n#define BIT_MASK_SCHEDULER_COUNTER_SEL 0xff\n#define BIT_SCHEDULER_COUNTER_SEL(x)                                           \\\n\t(((x) & BIT_MASK_SCHEDULER_COUNTER_SEL)                                \\\n\t << BIT_SHIFT_SCHEDULER_COUNTER_SEL)\n#define BITS_SCHEDULER_COUNTER_SEL                                             \\\n\t(BIT_MASK_SCHEDULER_COUNTER_SEL << BIT_SHIFT_SCHEDULER_COUNTER_SEL)\n#define BIT_CLEAR_SCHEDULER_COUNTER_SEL(x) ((x) & (~BITS_SCHEDULER_COUNTER_SEL))\n#define BIT_GET_SCHEDULER_COUNTER_SEL(x)                                       \\\n\t(((x) >> BIT_SHIFT_SCHEDULER_COUNTER_SEL) &                            \\\n\t BIT_MASK_SCHEDULER_COUNTER_SEL)\n#define BIT_SET_SCHEDULER_COUNTER_SEL(x, v)                                    \\\n\t(BIT_CLEAR_SCHEDULER_COUNTER_SEL(x) | BIT_SCHEDULER_COUNTER_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BCN_PSR_RPT2\t\t\t(Offset 0x1600) */\n\n#define BIT_SHIFT_DTIM_CNT2 24\n#define BIT_MASK_DTIM_CNT2 0xff\n#define BIT_DTIM_CNT2(x) (((x) & BIT_MASK_DTIM_CNT2) << BIT_SHIFT_DTIM_CNT2)\n#define BITS_DTIM_CNT2 (BIT_MASK_DTIM_CNT2 << BIT_SHIFT_DTIM_CNT2)\n#define BIT_CLEAR_DTIM_CNT2(x) ((x) & (~BITS_DTIM_CNT2))\n#define BIT_GET_DTIM_CNT2(x) (((x) >> BIT_SHIFT_DTIM_CNT2) & BIT_MASK_DTIM_CNT2)\n#define BIT_SET_DTIM_CNT2(x, v) (BIT_CLEAR_DTIM_CNT2(x) | BIT_DTIM_CNT2(v))\n\n#define BIT_SHIFT_DTIM_PERIOD2 16\n#define BIT_MASK_DTIM_PERIOD2 0xff\n#define BIT_DTIM_PERIOD2(x)                                                    \\\n\t(((x) & BIT_MASK_DTIM_PERIOD2) << BIT_SHIFT_DTIM_PERIOD2)\n#define BITS_DTIM_PERIOD2 (BIT_MASK_DTIM_PERIOD2 << BIT_SHIFT_DTIM_PERIOD2)\n#define BIT_CLEAR_DTIM_PERIOD2(x) ((x) & (~BITS_DTIM_PERIOD2))\n#define BIT_GET_DTIM_PERIOD2(x)                                                \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD2) & BIT_MASK_DTIM_PERIOD2)\n#define BIT_SET_DTIM_PERIOD2(x, v)                                             \\\n\t(BIT_CLEAR_DTIM_PERIOD2(x) | BIT_DTIM_PERIOD2(v))\n\n#define BIT_DTIM2 BIT(15)\n#define BIT_TIM2 BIT(14)\n\n#define BIT_SHIFT_PS_AID_2 0\n#define BIT_MASK_PS_AID_2 0x7ff\n#define BIT_PS_AID_2(x) (((x) & BIT_MASK_PS_AID_2) << BIT_SHIFT_PS_AID_2)\n#define BITS_PS_AID_2 (BIT_MASK_PS_AID_2 << BIT_SHIFT_PS_AID_2)\n#define BIT_CLEAR_PS_AID_2(x) ((x) & (~BITS_PS_AID_2))\n#define BIT_GET_PS_AID_2(x) (((x) >> BIT_SHIFT_PS_AID_2) & BIT_MASK_PS_AID_2)\n#define BIT_SET_PS_AID_2(x, v) (BIT_CLEAR_PS_AID_2(x) | BIT_PS_AID_2(v))\n\n/* 2 REG_BCN_PSR_RPT3\t\t\t(Offset 0x1604) */\n\n#define BIT_SHIFT_DTIM_CNT3 24\n#define BIT_MASK_DTIM_CNT3 0xff\n#define BIT_DTIM_CNT3(x) (((x) & BIT_MASK_DTIM_CNT3) << BIT_SHIFT_DTIM_CNT3)\n#define BITS_DTIM_CNT3 (BIT_MASK_DTIM_CNT3 << BIT_SHIFT_DTIM_CNT3)\n#define BIT_CLEAR_DTIM_CNT3(x) ((x) & (~BITS_DTIM_CNT3))\n#define BIT_GET_DTIM_CNT3(x) (((x) >> BIT_SHIFT_DTIM_CNT3) & BIT_MASK_DTIM_CNT3)\n#define BIT_SET_DTIM_CNT3(x, v) (BIT_CLEAR_DTIM_CNT3(x) | BIT_DTIM_CNT3(v))\n\n#define BIT_SHIFT_DTIM_PERIOD3 16\n#define BIT_MASK_DTIM_PERIOD3 0xff\n#define BIT_DTIM_PERIOD3(x)                                                    \\\n\t(((x) & BIT_MASK_DTIM_PERIOD3) << BIT_SHIFT_DTIM_PERIOD3)\n#define BITS_DTIM_PERIOD3 (BIT_MASK_DTIM_PERIOD3 << BIT_SHIFT_DTIM_PERIOD3)\n#define BIT_CLEAR_DTIM_PERIOD3(x) ((x) & (~BITS_DTIM_PERIOD3))\n#define BIT_GET_DTIM_PERIOD3(x)                                                \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD3) & BIT_MASK_DTIM_PERIOD3)\n#define BIT_SET_DTIM_PERIOD3(x, v)                                             \\\n\t(BIT_CLEAR_DTIM_PERIOD3(x) | BIT_DTIM_PERIOD3(v))\n\n#define BIT_DTIM3 BIT(15)\n#define BIT_TIM3 BIT(14)\n\n#define BIT_SHIFT_PS_AID_3 0\n#define BIT_MASK_PS_AID_3 0x7ff\n#define BIT_PS_AID_3(x) (((x) & BIT_MASK_PS_AID_3) << BIT_SHIFT_PS_AID_3)\n#define BITS_PS_AID_3 (BIT_MASK_PS_AID_3 << BIT_SHIFT_PS_AID_3)\n#define BIT_CLEAR_PS_AID_3(x) ((x) & (~BITS_PS_AID_3))\n#define BIT_GET_PS_AID_3(x) (((x) >> BIT_SHIFT_PS_AID_3) & BIT_MASK_PS_AID_3)\n#define BIT_SET_PS_AID_3(x, v) (BIT_CLEAR_PS_AID_3(x) | BIT_PS_AID_3(v))\n\n/* 2 REG_BCN_PSR_RPT4\t\t\t(Offset 0x1608) */\n\n#define BIT_SHIFT_DTIM_CNT4 24\n#define BIT_MASK_DTIM_CNT4 0xff\n#define BIT_DTIM_CNT4(x) (((x) & BIT_MASK_DTIM_CNT4) << BIT_SHIFT_DTIM_CNT4)\n#define BITS_DTIM_CNT4 (BIT_MASK_DTIM_CNT4 << BIT_SHIFT_DTIM_CNT4)\n#define BIT_CLEAR_DTIM_CNT4(x) ((x) & (~BITS_DTIM_CNT4))\n#define BIT_GET_DTIM_CNT4(x) (((x) >> BIT_SHIFT_DTIM_CNT4) & BIT_MASK_DTIM_CNT4)\n#define BIT_SET_DTIM_CNT4(x, v) (BIT_CLEAR_DTIM_CNT4(x) | BIT_DTIM_CNT4(v))\n\n#define BIT_SHIFT_DTIM_PERIOD4 16\n#define BIT_MASK_DTIM_PERIOD4 0xff\n#define BIT_DTIM_PERIOD4(x)                                                    \\\n\t(((x) & BIT_MASK_DTIM_PERIOD4) << BIT_SHIFT_DTIM_PERIOD4)\n#define BITS_DTIM_PERIOD4 (BIT_MASK_DTIM_PERIOD4 << BIT_SHIFT_DTIM_PERIOD4)\n#define BIT_CLEAR_DTIM_PERIOD4(x) ((x) & (~BITS_DTIM_PERIOD4))\n#define BIT_GET_DTIM_PERIOD4(x)                                                \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD4) & BIT_MASK_DTIM_PERIOD4)\n#define BIT_SET_DTIM_PERIOD4(x, v)                                             \\\n\t(BIT_CLEAR_DTIM_PERIOD4(x) | BIT_DTIM_PERIOD4(v))\n\n#define BIT_DTIM4 BIT(15)\n#define BIT_TIM4 BIT(14)\n\n#define BIT_SHIFT_PS_AID_4 0\n#define BIT_MASK_PS_AID_4 0x7ff\n#define BIT_PS_AID_4(x) (((x) & BIT_MASK_PS_AID_4) << BIT_SHIFT_PS_AID_4)\n#define BITS_PS_AID_4 (BIT_MASK_PS_AID_4 << BIT_SHIFT_PS_AID_4)\n#define BIT_CLEAR_PS_AID_4(x) ((x) & (~BITS_PS_AID_4))\n#define BIT_GET_PS_AID_4(x) (((x) >> BIT_SHIFT_PS_AID_4) & BIT_MASK_PS_AID_4)\n#define BIT_SET_PS_AID_4(x, v) (BIT_CLEAR_PS_AID_4(x) | BIT_PS_AID_4(v))\n\n/* 2 REG_A1_ADDR_MASK\t\t\t(Offset 0x160C) */\n\n#define BIT_SHIFT_A1_ADDR_MASK 0\n#define BIT_MASK_A1_ADDR_MASK 0xffffffffL\n#define BIT_A1_ADDR_MASK(x)                                                    \\\n\t(((x) & BIT_MASK_A1_ADDR_MASK) << BIT_SHIFT_A1_ADDR_MASK)\n#define BITS_A1_ADDR_MASK (BIT_MASK_A1_ADDR_MASK << BIT_SHIFT_A1_ADDR_MASK)\n#define BIT_CLEAR_A1_ADDR_MASK(x) ((x) & (~BITS_A1_ADDR_MASK))\n#define BIT_GET_A1_ADDR_MASK(x)                                                \\\n\t(((x) >> BIT_SHIFT_A1_ADDR_MASK) & BIT_MASK_A1_ADDR_MASK)\n#define BIT_SET_A1_ADDR_MASK(x, v)                                             \\\n\t(BIT_CLEAR_A1_ADDR_MASK(x) | BIT_A1_ADDR_MASK(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_RXPSF_CTRL\t\t\t\t(Offset 0x1610) */\n\n#define BIT_RXGCK_FIFOTHR_EN BIT(28)\n\n#define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26\n#define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3\n#define BIT_RXGCK_VHT_FIFOTHR(x)                                               \\\n\t(((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR)\n#define BITS_RXGCK_VHT_FIFOTHR                                                 \\\n\t(BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR)\n#define BIT_CLEAR_RXGCK_VHT_FIFOTHR(x) ((x) & (~BITS_RXGCK_VHT_FIFOTHR))\n#define BIT_GET_RXGCK_VHT_FIFOTHR(x)                                           \\\n\t(((x) >> BIT_SHIFT_RXGCK_VHT_FIFOTHR) & BIT_MASK_RXGCK_VHT_FIFOTHR)\n#define BIT_SET_RXGCK_VHT_FIFOTHR(x, v)                                        \\\n\t(BIT_CLEAR_RXGCK_VHT_FIFOTHR(x) | BIT_RXGCK_VHT_FIFOTHR(v))\n\n#define BIT_SHIFT_RXGCK_HT_FIFOTHR 24\n#define BIT_MASK_RXGCK_HT_FIFOTHR 0x3\n#define BIT_RXGCK_HT_FIFOTHR(x)                                                \\\n\t(((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR)\n#define BITS_RXGCK_HT_FIFOTHR                                                  \\\n\t(BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR)\n#define BIT_CLEAR_RXGCK_HT_FIFOTHR(x) ((x) & (~BITS_RXGCK_HT_FIFOTHR))\n#define BIT_GET_RXGCK_HT_FIFOTHR(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXGCK_HT_FIFOTHR) & BIT_MASK_RXGCK_HT_FIFOTHR)\n#define BIT_SET_RXGCK_HT_FIFOTHR(x, v)                                         \\\n\t(BIT_CLEAR_RXGCK_HT_FIFOTHR(x) | BIT_RXGCK_HT_FIFOTHR(v))\n\n#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22\n#define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3\n#define BIT_RXGCK_OFDM_FIFOTHR(x)                                              \\\n\t(((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)\n#define BITS_RXGCK_OFDM_FIFOTHR                                                \\\n\t(BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)\n#define BIT_CLEAR_RXGCK_OFDM_FIFOTHR(x) ((x) & (~BITS_RXGCK_OFDM_FIFOTHR))\n#define BIT_GET_RXGCK_OFDM_FIFOTHR(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXGCK_OFDM_FIFOTHR) & BIT_MASK_RXGCK_OFDM_FIFOTHR)\n#define BIT_SET_RXGCK_OFDM_FIFOTHR(x, v)                                       \\\n\t(BIT_CLEAR_RXGCK_OFDM_FIFOTHR(x) | BIT_RXGCK_OFDM_FIFOTHR(v))\n\n#define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20\n#define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3\n#define BIT_RXGCK_CCK_FIFOTHR(x)                                               \\\n\t(((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR)\n#define BITS_RXGCK_CCK_FIFOTHR                                                 \\\n\t(BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR)\n#define BIT_CLEAR_RXGCK_CCK_FIFOTHR(x) ((x) & (~BITS_RXGCK_CCK_FIFOTHR))\n#define BIT_GET_RXGCK_CCK_FIFOTHR(x)                                           \\\n\t(((x) >> BIT_SHIFT_RXGCK_CCK_FIFOTHR) & BIT_MASK_RXGCK_CCK_FIFOTHR)\n#define BIT_SET_RXGCK_CCK_FIFOTHR(x, v)                                        \\\n\t(BIT_CLEAR_RXGCK_CCK_FIFOTHR(x) | BIT_RXGCK_CCK_FIFOTHR(v))\n\n#define BIT_SHIFT_RXGCK_ENTRY_DELAY 17\n#define BIT_MASK_RXGCK_ENTRY_DELAY 0x7\n#define BIT_RXGCK_ENTRY_DELAY(x)                                               \\\n\t(((x) & BIT_MASK_RXGCK_ENTRY_DELAY) << BIT_SHIFT_RXGCK_ENTRY_DELAY)\n#define BITS_RXGCK_ENTRY_DELAY                                                 \\\n\t(BIT_MASK_RXGCK_ENTRY_DELAY << BIT_SHIFT_RXGCK_ENTRY_DELAY)\n#define BIT_CLEAR_RXGCK_ENTRY_DELAY(x) ((x) & (~BITS_RXGCK_ENTRY_DELAY))\n#define BIT_GET_RXGCK_ENTRY_DELAY(x)                                           \\\n\t(((x) >> BIT_SHIFT_RXGCK_ENTRY_DELAY) & BIT_MASK_RXGCK_ENTRY_DELAY)\n#define BIT_SET_RXGCK_ENTRY_DELAY(x, v)                                        \\\n\t(BIT_CLEAR_RXGCK_ENTRY_DELAY(x) | BIT_RXGCK_ENTRY_DELAY(v))\n\n#define BIT_RXGCK_OFDMCCA_EN BIT(16)\n\n#define BIT_SHIFT_RXPSF_PKTLENTHR 13\n#define BIT_MASK_RXPSF_PKTLENTHR 0x7\n#define BIT_RXPSF_PKTLENTHR(x)                                                 \\\n\t(((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR)\n#define BITS_RXPSF_PKTLENTHR                                                   \\\n\t(BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR)\n#define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR))\n#define BIT_GET_RXPSF_PKTLENTHR(x)                                             \\\n\t(((x) >> BIT_SHIFT_RXPSF_PKTLENTHR) & BIT_MASK_RXPSF_PKTLENTHR)\n#define BIT_SET_RXPSF_PKTLENTHR(x, v)                                          \\\n\t(BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v))\n\n#define BIT_RXPSF_CTRLEN BIT(12)\n#define BIT_RXPSF_VHTCHKEN BIT(11)\n#define BIT_RXPSF_HTCHKEN BIT(10)\n#define BIT_RXPSF_OFDMCHKEN BIT(9)\n#define BIT_RXPSF_CCKCHKEN BIT(8)\n#define BIT_RXPSF_OFDMRST BIT(7)\n#define BIT_RXPSF_CCKRST BIT(6)\n#define BIT_RXPSF_MHCHKEN BIT(5)\n#define BIT_RXPSF_CONT_ERRCHKEN BIT(4)\n#define BIT_RXPSF_ALL_ERRCHKEN BIT(3)\n\n#define BIT_SHIFT_RXPSF_ERRTHR 0\n#define BIT_MASK_RXPSF_ERRTHR 0x7\n#define BIT_RXPSF_ERRTHR(x)                                                    \\\n\t(((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR)\n#define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR)\n#define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR))\n#define BIT_GET_RXPSF_ERRTHR(x)                                                \\\n\t(((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR)\n#define BIT_SET_RXPSF_ERRTHR(x, v)                                             \\\n\t(BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v))\n\n/* 2 REG_RXPSF_TYPE_CTRL\t\t\t(Offset 0x1614) */\n\n#define BIT_RXPSF_DATA15EN BIT(31)\n#define BIT_RXPSF_DATA14EN BIT(30)\n#define BIT_RXPSF_DATA13EN BIT(29)\n#define BIT_RXPSF_DATA12EN BIT(28)\n#define BIT_RXPSF_DATA11EN BIT(27)\n#define BIT_RXPSF_DATA10EN BIT(26)\n#define BIT_RXPSF_DATA9EN BIT(25)\n#define BIT_RXPSF_DATA8EN BIT(24)\n#define BIT_RXPSF_DATA7EN BIT(23)\n#define BIT_RXPSF_DATA6EN BIT(22)\n#define BIT_RXPSF_DATA5EN BIT(21)\n#define BIT_RXPSF_DATA4EN BIT(20)\n#define BIT_RXPSF_DATA3EN BIT(19)\n#define BIT_RXPSF_DATA2EN BIT(18)\n#define BIT_RXPSF_DATA1EN BIT(17)\n#define BIT_RXPSF_DATA0EN BIT(16)\n#define BIT_RXPSF_MGT15EN BIT(15)\n#define BIT_RXPSF_MGT14EN BIT(14)\n#define BIT_RXPSF_MGT13EN BIT(13)\n#define BIT_RXPSF_MGT12EN BIT(12)\n#define BIT_RXPSF_MGT11EN BIT(11)\n#define BIT_RXPSF_MGT10EN BIT(10)\n#define BIT_RXPSF_MGT9EN BIT(9)\n#define BIT_RXPSF_MGT8EN BIT(8)\n#define BIT_RXPSF_MGT7EN BIT(7)\n#define BIT_RXPSF_MGT6EN BIT(6)\n#define BIT_RXPSF_MGT5EN BIT(5)\n#define BIT_RXPSF_MGT4EN BIT(4)\n#define BIT_RXPSF_MGT3EN BIT(3)\n#define BIT_RXPSF_MGT2EN BIT(2)\n#define BIT_RXPSF_MGT1EN BIT(1)\n#define BIT_RXPSF_MGT0EN BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CAM_ACCESS_CTRL\t\t\t(Offset 0x1618) */\n\n#define BIT_INDIRECT_ERR BIT(6)\n#define BIT_DIRECT_ERR BIT(5)\n#define BIT_DIR_ACCESS_EN_RX_BA BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CAM_ACCESS_CTRL\t\t\t(Offset 0x1618) */\n\n#define BIT_DIR_ACCESS_EN_MBSSIDCAM BIT(3)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CAM_ACCESS_CTRL\t\t\t(Offset 0x1618) */\n\n#define BIT_DIR_ACCESS_EN_ADDRCAM BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CAM_ACCESS_CTRL\t\t\t(Offset 0x1618) */\n\n#define BIT_DIR_ACCESS_EN_KEY BIT(2)\n#define BIT_DIR_ACCESS_EN_WOWLAN BIT(1)\n#define BIT_DIR_ACCESS_EN_FW_FILTER BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CUT_AMSDU_CTRL\t\t\t(Offset 0x161C) */\n\n#define BIT__CUT_AMSDU_CHKLEN_EN BIT(31)\n#define BIT_EN_CUT_AMSDU BIT(30)\n\n#define BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH 16\n#define BIT_MASK_CUT_AMSDU_CHKLEN_L_TH 0xff\n#define BIT_CUT_AMSDU_CHKLEN_L_TH(x)                                           \\\n\t(((x) & BIT_MASK_CUT_AMSDU_CHKLEN_L_TH)                                \\\n\t << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH)\n#define BITS_CUT_AMSDU_CHKLEN_L_TH                                             \\\n\t(BIT_MASK_CUT_AMSDU_CHKLEN_L_TH << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH)\n#define BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH(x) ((x) & (~BITS_CUT_AMSDU_CHKLEN_L_TH))\n#define BIT_GET_CUT_AMSDU_CHKLEN_L_TH(x)                                       \\\n\t(((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH) &                            \\\n\t BIT_MASK_CUT_AMSDU_CHKLEN_L_TH)\n#define BIT_SET_CUT_AMSDU_CHKLEN_L_TH(x, v)                                    \\\n\t(BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH(x) | BIT_CUT_AMSDU_CHKLEN_L_TH(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_HT_SND_REF_RATE\t\t\t(Offset 0x161C) */\n\n#define BIT_SHIFT_WMAC_HT_CSI_RATE 0\n#define BIT_MASK_WMAC_HT_CSI_RATE 0x3f\n#define BIT_WMAC_HT_CSI_RATE(x)                                                \\\n\t(((x) & BIT_MASK_WMAC_HT_CSI_RATE) << BIT_SHIFT_WMAC_HT_CSI_RATE)\n#define BITS_WMAC_HT_CSI_RATE                                                  \\\n\t(BIT_MASK_WMAC_HT_CSI_RATE << BIT_SHIFT_WMAC_HT_CSI_RATE)\n#define BIT_CLEAR_WMAC_HT_CSI_RATE(x) ((x) & (~BITS_WMAC_HT_CSI_RATE))\n#define BIT_GET_WMAC_HT_CSI_RATE(x)                                            \\\n\t(((x) >> BIT_SHIFT_WMAC_HT_CSI_RATE) & BIT_MASK_WMAC_HT_CSI_RATE)\n#define BIT_SET_WMAC_HT_CSI_RATE(x, v)                                         \\\n\t(BIT_CLEAR_WMAC_HT_CSI_RATE(x) | BIT_WMAC_HT_CSI_RATE(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_CUT_AMSDU_CTRL\t\t\t(Offset 0x161C) */\n\n#define BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH 0\n#define BIT_MASK_CUT_AMSDU_CHKLEN_H_TH 0xffff\n#define BIT_CUT_AMSDU_CHKLEN_H_TH(x)                                           \\\n\t(((x) & BIT_MASK_CUT_AMSDU_CHKLEN_H_TH)                                \\\n\t << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH)\n#define BITS_CUT_AMSDU_CHKLEN_H_TH                                             \\\n\t(BIT_MASK_CUT_AMSDU_CHKLEN_H_TH << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH)\n#define BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH(x) ((x) & (~BITS_CUT_AMSDU_CHKLEN_H_TH))\n#define BIT_GET_CUT_AMSDU_CHKLEN_H_TH(x)                                       \\\n\t(((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH) &                            \\\n\t BIT_MASK_CUT_AMSDU_CHKLEN_H_TH)\n#define BIT_SET_CUT_AMSDU_CHKLEN_H_TH(x, v)                                    \\\n\t(BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH(x) | BIT_CUT_AMSDU_CHKLEN_H_TH(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_MACID2\t\t\t\t(Offset 0x1620) */\n\n#define BIT_SHIFT_MACID2 0\n#define BIT_MASK_MACID2 0xffffffffffffL\n#define BIT_MACID2(x) (((x) & BIT_MASK_MACID2) << BIT_SHIFT_MACID2)\n#define BITS_MACID2 (BIT_MASK_MACID2 << BIT_SHIFT_MACID2)\n#define BIT_CLEAR_MACID2(x) ((x) & (~BITS_MACID2))\n#define BIT_GET_MACID2(x) (((x) >> BIT_SHIFT_MACID2) & BIT_MASK_MACID2)\n#define BIT_SET_MACID2(x, v) (BIT_CLEAR_MACID2(x) | BIT_MACID2(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MACID2\t\t\t\t(Offset 0x1620) */\n\n#define BIT_SHIFT_MACID2_V1 0\n#define BIT_MASK_MACID2_V1 0xffffffffL\n#define BIT_MACID2_V1(x) (((x) & BIT_MASK_MACID2_V1) << BIT_SHIFT_MACID2_V1)\n#define BITS_MACID2_V1 (BIT_MASK_MACID2_V1 << BIT_SHIFT_MACID2_V1)\n#define BIT_CLEAR_MACID2_V1(x) ((x) & (~BITS_MACID2_V1))\n#define BIT_GET_MACID2_V1(x) (((x) >> BIT_SHIFT_MACID2_V1) & BIT_MASK_MACID2_V1)\n#define BIT_SET_MACID2_V1(x, v) (BIT_CLEAR_MACID2_V1(x) | BIT_MACID2_V1(v))\n\n/* 2 REG_MACID2_H\t\t\t\t(Offset 0x1624) */\n\n#define BIT_SHIFT_MACID2_H_V1 0\n#define BIT_MASK_MACID2_H_V1 0xffff\n#define BIT_MACID2_H_V1(x)                                                     \\\n\t(((x) & BIT_MASK_MACID2_H_V1) << BIT_SHIFT_MACID2_H_V1)\n#define BITS_MACID2_H_V1 (BIT_MASK_MACID2_H_V1 << BIT_SHIFT_MACID2_H_V1)\n#define BIT_CLEAR_MACID2_H_V1(x) ((x) & (~BITS_MACID2_H_V1))\n#define BIT_GET_MACID2_H_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_MACID2_H_V1) & BIT_MASK_MACID2_H_V1)\n#define BIT_SET_MACID2_H_V1(x, v)                                              \\\n\t(BIT_CLEAR_MACID2_H_V1(x) | BIT_MACID2_H_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_BSSID2\t\t\t\t(Offset 0x1628) */\n\n#define BIT_SHIFT_BSSID2 0\n#define BIT_MASK_BSSID2 0xffffffffffffL\n#define BIT_BSSID2(x) (((x) & BIT_MASK_BSSID2) << BIT_SHIFT_BSSID2)\n#define BITS_BSSID2 (BIT_MASK_BSSID2 << BIT_SHIFT_BSSID2)\n#define BIT_CLEAR_BSSID2(x) ((x) & (~BITS_BSSID2))\n#define BIT_GET_BSSID2(x) (((x) >> BIT_SHIFT_BSSID2) & BIT_MASK_BSSID2)\n#define BIT_SET_BSSID2(x, v) (BIT_CLEAR_BSSID2(x) | BIT_BSSID2(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BSSID2\t\t\t\t(Offset 0x1628) */\n\n#define BIT_SHIFT_BSSID2_V1 0\n#define BIT_MASK_BSSID2_V1 0xffffffffL\n#define BIT_BSSID2_V1(x) (((x) & BIT_MASK_BSSID2_V1) << BIT_SHIFT_BSSID2_V1)\n#define BITS_BSSID2_V1 (BIT_MASK_BSSID2_V1 << BIT_SHIFT_BSSID2_V1)\n#define BIT_CLEAR_BSSID2_V1(x) ((x) & (~BITS_BSSID2_V1))\n#define BIT_GET_BSSID2_V1(x) (((x) >> BIT_SHIFT_BSSID2_V1) & BIT_MASK_BSSID2_V1)\n#define BIT_SET_BSSID2_V1(x, v) (BIT_CLEAR_BSSID2_V1(x) | BIT_BSSID2_V1(v))\n\n/* 2 REG_BSSID2_H\t\t\t\t(Offset 0x162C) */\n\n#define BIT_SHIFT_BSSID2_H_V1 0\n#define BIT_MASK_BSSID2_H_V1 0xffff\n#define BIT_BSSID2_H_V1(x)                                                     \\\n\t(((x) & BIT_MASK_BSSID2_H_V1) << BIT_SHIFT_BSSID2_H_V1)\n#define BITS_BSSID2_H_V1 (BIT_MASK_BSSID2_H_V1 << BIT_SHIFT_BSSID2_H_V1)\n#define BIT_CLEAR_BSSID2_H_V1(x) ((x) & (~BITS_BSSID2_H_V1))\n#define BIT_GET_BSSID2_H_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_BSSID2_H_V1) & BIT_MASK_BSSID2_H_V1)\n#define BIT_SET_BSSID2_H_V1(x, v)                                              \\\n\t(BIT_CLEAR_BSSID2_H_V1(x) | BIT_BSSID2_H_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_MACID3\t\t\t\t(Offset 0x1630) */\n\n#define BIT_SHIFT_MACID3 0\n#define BIT_MASK_MACID3 0xffffffffffffL\n#define BIT_MACID3(x) (((x) & BIT_MASK_MACID3) << BIT_SHIFT_MACID3)\n#define BITS_MACID3 (BIT_MASK_MACID3 << BIT_SHIFT_MACID3)\n#define BIT_CLEAR_MACID3(x) ((x) & (~BITS_MACID3))\n#define BIT_GET_MACID3(x) (((x) >> BIT_SHIFT_MACID3) & BIT_MASK_MACID3)\n#define BIT_SET_MACID3(x, v) (BIT_CLEAR_MACID3(x) | BIT_MACID3(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MACID3\t\t\t\t(Offset 0x1630) */\n\n#define BIT_SHIFT_MACID3_V1 0\n#define BIT_MASK_MACID3_V1 0xffffffffL\n#define BIT_MACID3_V1(x) (((x) & BIT_MASK_MACID3_V1) << BIT_SHIFT_MACID3_V1)\n#define BITS_MACID3_V1 (BIT_MASK_MACID3_V1 << BIT_SHIFT_MACID3_V1)\n#define BIT_CLEAR_MACID3_V1(x) ((x) & (~BITS_MACID3_V1))\n#define BIT_GET_MACID3_V1(x) (((x) >> BIT_SHIFT_MACID3_V1) & BIT_MASK_MACID3_V1)\n#define BIT_SET_MACID3_V1(x, v) (BIT_CLEAR_MACID3_V1(x) | BIT_MACID3_V1(v))\n\n/* 2 REG_MACID3_H\t\t\t\t(Offset 0x1634) */\n\n#define BIT_SHIFT_MACID3_H_V1 0\n#define BIT_MASK_MACID3_H_V1 0xffff\n#define BIT_MACID3_H_V1(x)                                                     \\\n\t(((x) & BIT_MASK_MACID3_H_V1) << BIT_SHIFT_MACID3_H_V1)\n#define BITS_MACID3_H_V1 (BIT_MASK_MACID3_H_V1 << BIT_SHIFT_MACID3_H_V1)\n#define BIT_CLEAR_MACID3_H_V1(x) ((x) & (~BITS_MACID3_H_V1))\n#define BIT_GET_MACID3_H_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_MACID3_H_V1) & BIT_MASK_MACID3_H_V1)\n#define BIT_SET_MACID3_H_V1(x, v)                                              \\\n\t(BIT_CLEAR_MACID3_H_V1(x) | BIT_MACID3_H_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_BSSID3\t\t\t\t(Offset 0x1638) */\n\n#define BIT_SHIFT_BSSID3 0\n#define BIT_MASK_BSSID3 0xffffffffffffL\n#define BIT_BSSID3(x) (((x) & BIT_MASK_BSSID3) << BIT_SHIFT_BSSID3)\n#define BITS_BSSID3 (BIT_MASK_BSSID3 << BIT_SHIFT_BSSID3)\n#define BIT_CLEAR_BSSID3(x) ((x) & (~BITS_BSSID3))\n#define BIT_GET_BSSID3(x) (((x) >> BIT_SHIFT_BSSID3) & BIT_MASK_BSSID3)\n#define BIT_SET_BSSID3(x, v) (BIT_CLEAR_BSSID3(x) | BIT_BSSID3(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BSSID3\t\t\t\t(Offset 0x1638) */\n\n#define BIT_SHIFT_BSSID3_V1 0\n#define BIT_MASK_BSSID3_V1 0xffffffffL\n#define BIT_BSSID3_V1(x) (((x) & BIT_MASK_BSSID3_V1) << BIT_SHIFT_BSSID3_V1)\n#define BITS_BSSID3_V1 (BIT_MASK_BSSID3_V1 << BIT_SHIFT_BSSID3_V1)\n#define BIT_CLEAR_BSSID3_V1(x) ((x) & (~BITS_BSSID3_V1))\n#define BIT_GET_BSSID3_V1(x) (((x) >> BIT_SHIFT_BSSID3_V1) & BIT_MASK_BSSID3_V1)\n#define BIT_SET_BSSID3_V1(x, v) (BIT_CLEAR_BSSID3_V1(x) | BIT_BSSID3_V1(v))\n\n/* 2 REG_BSSID3_H\t\t\t\t(Offset 0x163C) */\n\n#define BIT_SHIFT_BSSID3_H_V1 0\n#define BIT_MASK_BSSID3_H_V1 0xffff\n#define BIT_BSSID3_H_V1(x)                                                     \\\n\t(((x) & BIT_MASK_BSSID3_H_V1) << BIT_SHIFT_BSSID3_H_V1)\n#define BITS_BSSID3_H_V1 (BIT_MASK_BSSID3_H_V1 << BIT_SHIFT_BSSID3_H_V1)\n#define BIT_CLEAR_BSSID3_H_V1(x) ((x) & (~BITS_BSSID3_H_V1))\n#define BIT_GET_BSSID3_H_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_BSSID3_H_V1) & BIT_MASK_BSSID3_H_V1)\n#define BIT_SET_BSSID3_H_V1(x, v)                                              \\\n\t(BIT_CLEAR_BSSID3_H_V1(x) | BIT_BSSID3_H_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_MACID4\t\t\t\t(Offset 0x1640) */\n\n#define BIT_SHIFT_MACID4 0\n#define BIT_MASK_MACID4 0xffffffffffffL\n#define BIT_MACID4(x) (((x) & BIT_MASK_MACID4) << BIT_SHIFT_MACID4)\n#define BITS_MACID4 (BIT_MASK_MACID4 << BIT_SHIFT_MACID4)\n#define BIT_CLEAR_MACID4(x) ((x) & (~BITS_MACID4))\n#define BIT_GET_MACID4(x) (((x) >> BIT_SHIFT_MACID4) & BIT_MASK_MACID4)\n#define BIT_SET_MACID4(x, v) (BIT_CLEAR_MACID4(x) | BIT_MACID4(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MACID4\t\t\t\t(Offset 0x1640) */\n\n#define BIT_SHIFT_MACID4_V1 0\n#define BIT_MASK_MACID4_V1 0xffffffffL\n#define BIT_MACID4_V1(x) (((x) & BIT_MASK_MACID4_V1) << BIT_SHIFT_MACID4_V1)\n#define BITS_MACID4_V1 (BIT_MASK_MACID4_V1 << BIT_SHIFT_MACID4_V1)\n#define BIT_CLEAR_MACID4_V1(x) ((x) & (~BITS_MACID4_V1))\n#define BIT_GET_MACID4_V1(x) (((x) >> BIT_SHIFT_MACID4_V1) & BIT_MASK_MACID4_V1)\n#define BIT_SET_MACID4_V1(x, v) (BIT_CLEAR_MACID4_V1(x) | BIT_MACID4_V1(v))\n\n/* 2 REG_MACID4_H\t\t\t\t(Offset 0x1644) */\n\n#define BIT_SHIFT_MACID4_H_V1 0\n#define BIT_MASK_MACID4_H_V1 0xffff\n#define BIT_MACID4_H_V1(x)                                                     \\\n\t(((x) & BIT_MASK_MACID4_H_V1) << BIT_SHIFT_MACID4_H_V1)\n#define BITS_MACID4_H_V1 (BIT_MASK_MACID4_H_V1 << BIT_SHIFT_MACID4_H_V1)\n#define BIT_CLEAR_MACID4_H_V1(x) ((x) & (~BITS_MACID4_H_V1))\n#define BIT_GET_MACID4_H_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_MACID4_H_V1) & BIT_MASK_MACID4_H_V1)\n#define BIT_SET_MACID4_H_V1(x, v)                                              \\\n\t(BIT_CLEAR_MACID4_H_V1(x) | BIT_MACID4_H_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_BSSID4\t\t\t\t(Offset 0x1648) */\n\n#define BIT_SHIFT_BSSID4 0\n#define BIT_MASK_BSSID4 0xffffffffffffL\n#define BIT_BSSID4(x) (((x) & BIT_MASK_BSSID4) << BIT_SHIFT_BSSID4)\n#define BITS_BSSID4 (BIT_MASK_BSSID4 << BIT_SHIFT_BSSID4)\n#define BIT_CLEAR_BSSID4(x) ((x) & (~BITS_BSSID4))\n#define BIT_GET_BSSID4(x) (((x) >> BIT_SHIFT_BSSID4) & BIT_MASK_BSSID4)\n#define BIT_SET_BSSID4(x, v) (BIT_CLEAR_BSSID4(x) | BIT_BSSID4(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_BSSID4\t\t\t\t(Offset 0x1648) */\n\n#define BIT_SHIFT_BSSID4_V1 0\n#define BIT_MASK_BSSID4_V1 0xffffffffL\n#define BIT_BSSID4_V1(x) (((x) & BIT_MASK_BSSID4_V1) << BIT_SHIFT_BSSID4_V1)\n#define BITS_BSSID4_V1 (BIT_MASK_BSSID4_V1 << BIT_SHIFT_BSSID4_V1)\n#define BIT_CLEAR_BSSID4_V1(x) ((x) & (~BITS_BSSID4_V1))\n#define BIT_GET_BSSID4_V1(x) (((x) >> BIT_SHIFT_BSSID4_V1) & BIT_MASK_BSSID4_V1)\n#define BIT_SET_BSSID4_V1(x, v) (BIT_CLEAR_BSSID4_V1(x) | BIT_BSSID4_V1(v))\n\n/* 2 REG_BSSID4_H\t\t\t\t(Offset 0x164C) */\n\n#define BIT_SHIFT_BSSID4_H_V1 0\n#define BIT_MASK_BSSID4_H_V1 0xffff\n#define BIT_BSSID4_H_V1(x)                                                     \\\n\t(((x) & BIT_MASK_BSSID4_H_V1) << BIT_SHIFT_BSSID4_H_V1)\n#define BITS_BSSID4_H_V1 (BIT_MASK_BSSID4_H_V1 << BIT_SHIFT_BSSID4_H_V1)\n#define BIT_CLEAR_BSSID4_H_V1(x) ((x) & (~BITS_BSSID4_H_V1))\n#define BIT_GET_BSSID4_H_V1(x)                                                 \\\n\t(((x) >> BIT_SHIFT_BSSID4_H_V1) & BIT_MASK_BSSID4_H_V1)\n#define BIT_SET_BSSID4_H_V1(x, v)                                              \\\n\t(BIT_CLEAR_BSSID4_H_V1(x) | BIT_BSSID4_H_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_NOA_REPORT\t\t\t\t(Offset 0x1650) */\n\n#define BIT_SHIFT_NOA_RPT 0\n#define BIT_MASK_NOA_RPT 0xffffffffL\n#define BIT_NOA_RPT(x) (((x) & BIT_MASK_NOA_RPT) << BIT_SHIFT_NOA_RPT)\n#define BITS_NOA_RPT (BIT_MASK_NOA_RPT << BIT_SHIFT_NOA_RPT)\n#define BIT_CLEAR_NOA_RPT(x) ((x) & (~BITS_NOA_RPT))\n#define BIT_GET_NOA_RPT(x) (((x) >> BIT_SHIFT_NOA_RPT) & BIT_MASK_NOA_RPT)\n#define BIT_SET_NOA_RPT(x, v) (BIT_CLEAR_NOA_RPT(x) | BIT_NOA_RPT(v))\n\n/* 2 REG_NOA_REPORT_1\t\t\t(Offset 0x1654) */\n\n#define BIT_SHIFT_NOA_RPT_1 0\n#define BIT_MASK_NOA_RPT_1 0xffffffffL\n#define BIT_NOA_RPT_1(x) (((x) & BIT_MASK_NOA_RPT_1) << BIT_SHIFT_NOA_RPT_1)\n#define BITS_NOA_RPT_1 (BIT_MASK_NOA_RPT_1 << BIT_SHIFT_NOA_RPT_1)\n#define BIT_CLEAR_NOA_RPT_1(x) ((x) & (~BITS_NOA_RPT_1))\n#define BIT_GET_NOA_RPT_1(x) (((x) >> BIT_SHIFT_NOA_RPT_1) & BIT_MASK_NOA_RPT_1)\n#define BIT_SET_NOA_RPT_1(x, v) (BIT_CLEAR_NOA_RPT_1(x) | BIT_NOA_RPT_1(v))\n\n/* 2 REG_NOA_REPORT_2\t\t\t(Offset 0x1658) */\n\n#define BIT_SHIFT_NOA_RPT_2 0\n#define BIT_MASK_NOA_RPT_2 0xffffffffL\n#define BIT_NOA_RPT_2(x) (((x) & BIT_MASK_NOA_RPT_2) << BIT_SHIFT_NOA_RPT_2)\n#define BITS_NOA_RPT_2 (BIT_MASK_NOA_RPT_2 << BIT_SHIFT_NOA_RPT_2)\n#define BIT_CLEAR_NOA_RPT_2(x) ((x) & (~BITS_NOA_RPT_2))\n#define BIT_GET_NOA_RPT_2(x) (((x) >> BIT_SHIFT_NOA_RPT_2) & BIT_MASK_NOA_RPT_2)\n#define BIT_SET_NOA_RPT_2(x, v) (BIT_CLEAR_NOA_RPT_2(x) | BIT_NOA_RPT_2(v))\n\n/* 2 REG_NOA_REPORT_3\t\t\t(Offset 0x165C) */\n\n#define BIT_SHIFT_NOA_RPT_3 0\n#define BIT_MASK_NOA_RPT_3 0xff\n#define BIT_NOA_RPT_3(x) (((x) & BIT_MASK_NOA_RPT_3) << BIT_SHIFT_NOA_RPT_3)\n#define BITS_NOA_RPT_3 (BIT_MASK_NOA_RPT_3 << BIT_SHIFT_NOA_RPT_3)\n#define BIT_CLEAR_NOA_RPT_3(x) ((x) & (~BITS_NOA_RPT_3))\n#define BIT_GET_NOA_RPT_3(x) (((x) >> BIT_SHIFT_NOA_RPT_3) & BIT_MASK_NOA_RPT_3)\n#define BIT_SET_NOA_RPT_3(x, v) (BIT_CLEAR_NOA_RPT_3(x) | BIT_NOA_RPT_3(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PWRBIT_SETTING\t\t\t(Offset 0x1660) */\n\n#define BIT_CLI3_WMAC_TCRPWRMGT_HWCTL_EN BIT(15)\n#define BIT_CLI3_WMAC_TCRPWRMGT_HWDATA_EN BIT(14)\n#define BIT_CLI3_WMAC_TCRPWRMGT_HWACT_EN BIT(13)\n#define BIT_CLI3_PWR_ST_V1 BIT(12)\n#define BIT_CLI2_WMAC_TCRPWRMGT_HWCTL_EN BIT(11)\n#define BIT_CLI2_WMAC_TCRPWRMGT_HWDATA_EN BIT(10)\n#define BIT_CLI2_WMAC_TCRPWRMGT_HWACT_EN BIT(9)\n#define BIT_CLI2_PWR_ST_V1 BIT(8)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_PWRBIT_SETTING\t\t\t(Offset 0x1660) */\n\n#define BIT_CLI3_PWRBIT_OW_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PWRBIT_SETTING\t\t\t(Offset 0x1660) */\n\n#define BIT_CLI1_WMAC_TCRPWRMGT_HWCTL_EN BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_PWRBIT_SETTING\t\t\t(Offset 0x1660) */\n\n#define BIT_CLI3_PWR_ST BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PWRBIT_SETTING\t\t\t(Offset 0x1660) */\n\n#define BIT_CLI1_WMAC_TCRPWRMGT_HWDATA_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_PWRBIT_SETTING\t\t\t(Offset 0x1660) */\n\n#define BIT_CLI2_PWRBIT_OW_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PWRBIT_SETTING\t\t\t(Offset 0x1660) */\n\n#define BIT_CLI1_WMAC_TCRPWRMGT_HWACT_EN BIT(5)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_PWRBIT_SETTING\t\t\t(Offset 0x1660) */\n\n#define BIT_CLI2_PWR_ST BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PWRBIT_SETTING\t\t\t(Offset 0x1660) */\n\n#define BIT_CLI1_PWR_ST_V1 BIT(4)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_PWRBIT_SETTING\t\t\t(Offset 0x1660) */\n\n#define BIT_CLI1_PWRBIT_OW_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PWRBIT_SETTING\t\t\t(Offset 0x1660) */\n\n#define BIT_CLI0_WMAC_TCRPWRMGT_HWCTL_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_PWRBIT_SETTING\t\t\t(Offset 0x1660) */\n\n#define BIT_CLI1_PWR_ST BIT(2)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PWRBIT_SETTING\t\t\t(Offset 0x1660) */\n\n#define BIT_CLI0_WMAC_TCRPWRMGT_HWDATA_EN BIT(2)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_PWRBIT_SETTING\t\t\t(Offset 0x1660) */\n\n#define BIT_CLI0_PWRBIT_OW_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PWRBIT_SETTING\t\t\t(Offset 0x1660) */\n\n#define BIT_CLI0_WMAC_TCRPWRMGT_HWACT_EN BIT(1)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_PWRBIT_SETTING\t\t\t(Offset 0x1660) */\n\n#define BIT_CLI0_PWR_ST BIT(0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PWRBIT_SETTING\t\t\t(Offset 0x1660) */\n\n#define BIT_CLI0_PWR_ST_V1 BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_GENERAL_OPTION\t\t\t(Offset 0x1664) */\n\n#define BIT_FIX_MSDU_TAIL_WR BIT(12)\n#define BIT_FIX_MSDU_SHIFT BIT(11)\n\n#endif\n\n#if (HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GENERAL_OPTION\t\t\t(Offset 0x1664) */\n\n#define BIT_WMAC_RXRST_NDP_TIMEOUT BIT(11)\n#define BIT_WMAC_NDP_STANDBY_WAIT_RXEND BIT(10)\n#define BIT_DUMMY_FCS_READY_MASK_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GENERAL_OPTION\t\t\t(Offset 0x1664) */\n\n#define BIT_RXFIFO_GNT_CUT BIT(8)\n\n#endif\n\n#if (HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GENERAL_OPTION\t\t\t(Offset 0x1664) */\n\n#define BIT_DUMMY_RXD_FCS_ERROR_MASK_EN_V1 BIT(7)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GENERAL_OPTION\t\t\t(Offset 0x1664) */\n\n#define BIT_WMAC_EXT_DBG_SEL_V1 BIT(6)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GENERAL_OPTION\t\t\t(Offset 0x1664) */\n\n#define BIT_WMAC_FIX_FIRST_MPDU_WITH_PHYSTS BIT(5)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GENERAL_OPTION\t\t\t(Offset 0x1664) */\n\n#define BIT_RX_DMA_BYPASS_CHECK_DATABYPASS_CHECK_DATA BIT(4)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_GENERAL_OPTION\t\t\t(Offset 0x1664) */\n\n#define BIT_DUMMY_RXD_FCS_ERROR_MASK_EN BIT(4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GENERAL_OPTION\t\t\t(Offset 0x1664) */\n\n#define BIT_RX_DMA_BYPASS_CHECK_MGTBIT_RX_DMA_BYPASS_CHECK_MGT BIT(3)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_GENERAL_OPTION\t\t\t(Offset 0x1664) */\n\n#define BIT_PATTERN_MATCH_FIX_EN BIT(3)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_GENERAL_OPTION\t\t\t(Offset 0x1664) */\n\n#define BIT_TXSERV_FIELD_SEL BIT(2)\n#define BIT_RXVHT_LEN_SEL BIT(1)\n#define BIT_RXMIC_PROTECT_EN BIT(0)\n\n#define BIT_SHIFT_WMAC_MULBK_PAGE_SIZE 0\n#define BIT_MASK_WMAC_MULBK_PAGE_SIZE 0xff\n#define BIT_WMAC_MULBK_PAGE_SIZE(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_MULBK_PAGE_SIZE)                                 \\\n\t << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE)\n#define BITS_WMAC_MULBK_PAGE_SIZE                                              \\\n\t(BIT_MASK_WMAC_MULBK_PAGE_SIZE << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE)\n#define BIT_CLEAR_WMAC_MULBK_PAGE_SIZE(x) ((x) & (~BITS_WMAC_MULBK_PAGE_SIZE))\n#define BIT_GET_WMAC_MULBK_PAGE_SIZE(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_MULBK_PAGE_SIZE) &                             \\\n\t BIT_MASK_WMAC_MULBK_PAGE_SIZE)\n#define BIT_SET_WMAC_MULBK_PAGE_SIZE(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_MULBK_PAGE_SIZE(x) | BIT_WMAC_MULBK_PAGE_SIZE(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_FWPHYFF_RCR\t\t\t\t(Offset 0x1668) */\n\n#define BIT_RCR2_AAMSDU BIT(25)\n#define BIT_RCR2_CBSSID_BCN BIT(24)\n#define BIT_RCR2_ACRC32 BIT(23)\n#define BIT_RCR2_TA_BCN BIT(22)\n#define BIT_RCR2_CBSSID_DATA BIT(21)\n#define BIT_RCR2_ADD3 BIT(20)\n#define BIT_RCR2_AB BIT(19)\n#define BIT_RCR2_AM BIT(18)\n#define BIT_RCR2_APM BIT(17)\n#define BIT_RCR2_AAP BIT(16)\n#define BIT_RCR1_AAMSDU BIT(9)\n#define BIT_RCR1_CBSSID_BCN BIT(8)\n#define BIT_RCR1_ACRC32 BIT(7)\n#define BIT_RCR1_TA_BCN BIT(6)\n#define BIT_RCR1_CBSSID_DATA BIT(5)\n#define BIT_RCR1_ADD3 BIT(4)\n#define BIT_RCR1_AB BIT(3)\n#define BIT_RCR1_AM BIT(2)\n#define BIT_RCR1_APM BIT(1)\n#define BIT_RCR1_AAP BIT(0)\n\n/* 2 REG_ADDRCAM_WRITE_CONTENT\t\t(Offset 0x166C) */\n\n#define BIT_SHIFT_ADDRCAM_WDATA 0\n#define BIT_MASK_ADDRCAM_WDATA 0xffffffffL\n#define BIT_ADDRCAM_WDATA(x)                                                   \\\n\t(((x) & BIT_MASK_ADDRCAM_WDATA) << BIT_SHIFT_ADDRCAM_WDATA)\n#define BITS_ADDRCAM_WDATA (BIT_MASK_ADDRCAM_WDATA << BIT_SHIFT_ADDRCAM_WDATA)\n#define BIT_CLEAR_ADDRCAM_WDATA(x) ((x) & (~BITS_ADDRCAM_WDATA))\n#define BIT_GET_ADDRCAM_WDATA(x)                                               \\\n\t(((x) >> BIT_SHIFT_ADDRCAM_WDATA) & BIT_MASK_ADDRCAM_WDATA)\n#define BIT_SET_ADDRCAM_WDATA(x, v)                                            \\\n\t(BIT_CLEAR_ADDRCAM_WDATA(x) | BIT_ADDRCAM_WDATA(v))\n\n/* 2 REG_ADDRCAM_READ_CONTENT\t\t(Offset 0x1670) */\n\n#define BIT_SHIFT_ADDRCAM_RDATA 0\n#define BIT_MASK_ADDRCAM_RDATA 0xffffffffL\n#define BIT_ADDRCAM_RDATA(x)                                                   \\\n\t(((x) & BIT_MASK_ADDRCAM_RDATA) << BIT_SHIFT_ADDRCAM_RDATA)\n#define BITS_ADDRCAM_RDATA (BIT_MASK_ADDRCAM_RDATA << BIT_SHIFT_ADDRCAM_RDATA)\n#define BIT_CLEAR_ADDRCAM_RDATA(x) ((x) & (~BITS_ADDRCAM_RDATA))\n#define BIT_GET_ADDRCAM_RDATA(x)                                               \\\n\t(((x) >> BIT_SHIFT_ADDRCAM_RDATA) & BIT_MASK_ADDRCAM_RDATA)\n#define BIT_SET_ADDRCAM_RDATA(x, v)                                            \\\n\t(BIT_CLEAR_ADDRCAM_RDATA(x) | BIT_ADDRCAM_RDATA(v))\n\n/* 2 REG_ADDRCAM_CFG\t\t\t\t(Offset 0x1674) */\n\n#define BIT_ADDRCAM_POLL BIT(31)\n#define BIT__ADDRCAM_WT_EN BIT(30)\n#define BIT_CLRADDRCAM BIT(29)\n\n#define BIT_SHIFT__ADDRCAM_ADDR 8\n#define BIT_MASK__ADDRCAM_ADDR 0x3ff\n#define BIT__ADDRCAM_ADDR(x)                                                   \\\n\t(((x) & BIT_MASK__ADDRCAM_ADDR) << BIT_SHIFT__ADDRCAM_ADDR)\n#define BITS__ADDRCAM_ADDR (BIT_MASK__ADDRCAM_ADDR << BIT_SHIFT__ADDRCAM_ADDR)\n#define BIT_CLEAR__ADDRCAM_ADDR(x) ((x) & (~BITS__ADDRCAM_ADDR))\n#define BIT_GET__ADDRCAM_ADDR(x)                                               \\\n\t(((x) >> BIT_SHIFT__ADDRCAM_ADDR) & BIT_MASK__ADDRCAM_ADDR)\n#define BIT_SET__ADDRCAM_ADDR(x, v)                                            \\\n\t(BIT_CLEAR__ADDRCAM_ADDR(x) | BIT__ADDRCAM_ADDR(v))\n\n#define BIT_SHIFT_ADDRCAM_RANGE 0\n#define BIT_MASK_ADDRCAM_RANGE 0x7f\n#define BIT_ADDRCAM_RANGE(x)                                                   \\\n\t(((x) & BIT_MASK_ADDRCAM_RANGE) << BIT_SHIFT_ADDRCAM_RANGE)\n#define BITS_ADDRCAM_RANGE (BIT_MASK_ADDRCAM_RANGE << BIT_SHIFT_ADDRCAM_RANGE)\n#define BIT_CLEAR_ADDRCAM_RANGE(x) ((x) & (~BITS_ADDRCAM_RANGE))\n#define BIT_GET_ADDRCAM_RANGE(x)                                               \\\n\t(((x) >> BIT_SHIFT_ADDRCAM_RANGE) & BIT_MASK_ADDRCAM_RANGE)\n#define BIT_SET_ADDRCAM_RANGE(x, v)                                            \\\n\t(BIT_CLEAR_ADDRCAM_RANGE(x) | BIT_ADDRCAM_RANGE(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CSI_RRSR\t\t\t\t(Offset 0x1678) */\n\n#define BIT_CSI_LDPC_EN BIT(29)\n#define BIT_CSI_STBC_EN BIT(28)\n\n#define BIT_SHIFT_CSI_RRSC_BITMAP 4\n#define BIT_MASK_CSI_RRSC_BITMAP 0xffffff\n#define BIT_CSI_RRSC_BITMAP(x)                                                 \\\n\t(((x) & BIT_MASK_CSI_RRSC_BITMAP) << BIT_SHIFT_CSI_RRSC_BITMAP)\n#define BITS_CSI_RRSC_BITMAP                                                   \\\n\t(BIT_MASK_CSI_RRSC_BITMAP << BIT_SHIFT_CSI_RRSC_BITMAP)\n#define BIT_CLEAR_CSI_RRSC_BITMAP(x) ((x) & (~BITS_CSI_RRSC_BITMAP))\n#define BIT_GET_CSI_RRSC_BITMAP(x)                                             \\\n\t(((x) >> BIT_SHIFT_CSI_RRSC_BITMAP) & BIT_MASK_CSI_RRSC_BITMAP)\n#define BIT_SET_CSI_RRSC_BITMAP(x, v)                                          \\\n\t(BIT_CLEAR_CSI_RRSC_BITMAP(x) | BIT_CSI_RRSC_BITMAP(v))\n\n#define BIT_SHIFT_OFDM_LEN_TH 0\n#define BIT_MASK_OFDM_LEN_TH 0xf\n#define BIT_OFDM_LEN_TH(x)                                                     \\\n\t(((x) & BIT_MASK_OFDM_LEN_TH) << BIT_SHIFT_OFDM_LEN_TH)\n#define BITS_OFDM_LEN_TH (BIT_MASK_OFDM_LEN_TH << BIT_SHIFT_OFDM_LEN_TH)\n#define BIT_CLEAR_OFDM_LEN_TH(x) ((x) & (~BITS_OFDM_LEN_TH))\n#define BIT_GET_OFDM_LEN_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_OFDM_LEN_TH) & BIT_MASK_OFDM_LEN_TH)\n#define BIT_SET_OFDM_LEN_TH(x, v)                                              \\\n\t(BIT_CLEAR_OFDM_LEN_TH(x) | BIT_OFDM_LEN_TH(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_WMAC_MU_BF_OPTION\t\t\t(Offset 0x167C) */\n\n#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_MU_BF_OPTION\t\t\t(Offset 0x167C) */\n\n#define BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_PAUSE_BB_CLR_TH\t\t(Offset 0x167D) */\n\n#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH 0\n#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH 0xff\n#define BIT_WMAC_PAUSE_BB_CLR_TH(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH)                                 \\\n\t << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH)\n#define BITS_WMAC_PAUSE_BB_CLR_TH                                              \\\n\t(BIT_MASK_WMAC_PAUSE_BB_CLR_TH << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH)\n#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH(x) ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH))\n#define BIT_GET_WMAC_PAUSE_BB_CLR_TH(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) &                             \\\n\t BIT_MASK_WMAC_PAUSE_BB_CLR_TH)\n#define BIT_SET_WMAC_PAUSE_BB_CLR_TH(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH(x) | BIT_WMAC_PAUSE_BB_CLR_TH(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_WMAC_MU_ARB\t\t\t\t(Offset 0x167E) */\n\n#define BIT_WMAC_ARB_HW_ADAPT_EN BIT(7)\n#define BIT_WMAC_ARB_SW_EN BIT(6)\n\n#define BIT_SHIFT_WMAC_ARB_SW_STATE 0\n#define BIT_MASK_WMAC_ARB_SW_STATE 0x3f\n#define BIT_WMAC_ARB_SW_STATE(x)                                               \\\n\t(((x) & BIT_MASK_WMAC_ARB_SW_STATE) << BIT_SHIFT_WMAC_ARB_SW_STATE)\n#define BITS_WMAC_ARB_SW_STATE                                                 \\\n\t(BIT_MASK_WMAC_ARB_SW_STATE << BIT_SHIFT_WMAC_ARB_SW_STATE)\n#define BIT_CLEAR_WMAC_ARB_SW_STATE(x) ((x) & (~BITS_WMAC_ARB_SW_STATE))\n#define BIT_GET_WMAC_ARB_SW_STATE(x)                                           \\\n\t(((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE) & BIT_MASK_WMAC_ARB_SW_STATE)\n#define BIT_SET_WMAC_ARB_SW_STATE(x, v)                                        \\\n\t(BIT_CLEAR_WMAC_ARB_SW_STATE(x) | BIT_WMAC_ARB_SW_STATE(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_WMAC_MU_OPTION\t\t\t(Offset 0x167F) */\n\n#define BIT_NOCHK_BFPOLL_BMP BIT(7)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT)\n\n/* 2 REG_WMAC_MU_OPTION\t\t\t(Offset 0x167F) */\n\n#define BIT_SHIFT_WMAC_MU_DBGSEL 5\n#define BIT_MASK_WMAC_MU_DBGSEL 0x3\n#define BIT_WMAC_MU_DBGSEL(x)                                                  \\\n\t(((x) & BIT_MASK_WMAC_MU_DBGSEL) << BIT_SHIFT_WMAC_MU_DBGSEL)\n#define BITS_WMAC_MU_DBGSEL                                                    \\\n\t(BIT_MASK_WMAC_MU_DBGSEL << BIT_SHIFT_WMAC_MU_DBGSEL)\n#define BIT_CLEAR_WMAC_MU_DBGSEL(x) ((x) & (~BITS_WMAC_MU_DBGSEL))\n#define BIT_GET_WMAC_MU_DBGSEL(x)                                              \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_DBGSEL) & BIT_MASK_WMAC_MU_DBGSEL)\n#define BIT_SET_WMAC_MU_DBGSEL(x, v)                                           \\\n\t(BIT_CLEAR_WMAC_MU_DBGSEL(x) | BIT_WMAC_MU_DBGSEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_WMAC_MU_OPTION\t\t\t(Offset 0x167F) */\n\n#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT 0\n#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT 0x1f\n#define BIT_WMAC_MU_CPRD_TIMEOUT(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT)                                 \\\n\t << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT)\n#define BITS_WMAC_MU_CPRD_TIMEOUT                                              \\\n\t(BIT_MASK_WMAC_MU_CPRD_TIMEOUT << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT)\n#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT(x) ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT))\n#define BIT_GET_WMAC_MU_CPRD_TIMEOUT(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) &                             \\\n\t BIT_MASK_WMAC_MU_CPRD_TIMEOUT)\n#define BIT_SET_WMAC_MU_CPRD_TIMEOUT(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT(x) | BIT_WMAC_MU_CPRD_TIMEOUT(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_MU_BF_CTL\t\t\t(Offset 0x1680) */\n\n#define BIT_WMAC_INVLD_BFPRT_CHK BIT(15)\n#define BIT_WMAC_RETXBFRPTSEQ_UPD BIT(14)\n\n#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL 12\n#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL 0x3\n#define BIT_WMAC_MU_BFRPTSEG_SEL(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL)                                 \\\n\t << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL)\n#define BITS_WMAC_MU_BFRPTSEG_SEL                                              \\\n\t(BIT_MASK_WMAC_MU_BFRPTSEG_SEL << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL)\n#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL(x) ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL))\n#define BIT_GET_WMAC_MU_BFRPTSEG_SEL(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) &                             \\\n\t BIT_MASK_WMAC_MU_BFRPTSEG_SEL)\n#define BIT_SET_WMAC_MU_BFRPTSEG_SEL(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL(x) | BIT_WMAC_MU_BFRPTSEG_SEL(v))\n\n#define BIT_SHIFT_WMAC_MU_BF_MYAID 0\n#define BIT_MASK_WMAC_MU_BF_MYAID 0xfff\n#define BIT_WMAC_MU_BF_MYAID(x)                                                \\\n\t(((x) & BIT_MASK_WMAC_MU_BF_MYAID) << BIT_SHIFT_WMAC_MU_BF_MYAID)\n#define BITS_WMAC_MU_BF_MYAID                                                  \\\n\t(BIT_MASK_WMAC_MU_BF_MYAID << BIT_SHIFT_WMAC_MU_BF_MYAID)\n#define BIT_CLEAR_WMAC_MU_BF_MYAID(x) ((x) & (~BITS_WMAC_MU_BF_MYAID))\n#define BIT_GET_WMAC_MU_BF_MYAID(x)                                            \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID) & BIT_MASK_WMAC_MU_BF_MYAID)\n#define BIT_SET_WMAC_MU_BF_MYAID(x, v)                                         \\\n\t(BIT_CLEAR_WMAC_MU_BF_MYAID(x) | BIT_WMAC_MU_BF_MYAID(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_MU_BFRPT_PARA\t\t\t(Offset 0x1682) */\n\n#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1 13\n#define BIT_MASK_BFRPT_PARA_USERID_SEL_V1 0x7\n#define BIT_BFRPT_PARA_USERID_SEL_V1(x)                                        \\\n\t(((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1)                             \\\n\t << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1)\n#define BITS_BFRPT_PARA_USERID_SEL_V1                                          \\\n\t(BIT_MASK_BFRPT_PARA_USERID_SEL_V1                                     \\\n\t << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1)\n#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1(x)                                  \\\n\t((x) & (~BITS_BFRPT_PARA_USERID_SEL_V1))\n#define BIT_GET_BFRPT_PARA_USERID_SEL_V1(x)                                    \\\n\t(((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1) &                         \\\n\t BIT_MASK_BFRPT_PARA_USERID_SEL_V1)\n#define BIT_SET_BFRPT_PARA_USERID_SEL_V1(x, v)                                 \\\n\t(BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1(x) |                               \\\n\t BIT_BFRPT_PARA_USERID_SEL_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)\n\n/* 2 REG_WMAC_MU_BFRPT_PARA\t\t\t(Offset 0x1682) */\n\n#define BIT_SHIFT_BFRPT_PARA_USERID_SEL 12\n#define BIT_MASK_BFRPT_PARA_USERID_SEL 0x7\n#define BIT_BFRPT_PARA_USERID_SEL(x)                                           \\\n\t(((x) & BIT_MASK_BFRPT_PARA_USERID_SEL)                                \\\n\t << BIT_SHIFT_BFRPT_PARA_USERID_SEL)\n#define BITS_BFRPT_PARA_USERID_SEL                                             \\\n\t(BIT_MASK_BFRPT_PARA_USERID_SEL << BIT_SHIFT_BFRPT_PARA_USERID_SEL)\n#define BIT_CLEAR_BFRPT_PARA_USERID_SEL(x) ((x) & (~BITS_BFRPT_PARA_USERID_SEL))\n#define BIT_GET_BFRPT_PARA_USERID_SEL(x)                                       \\\n\t(((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL) &                            \\\n\t BIT_MASK_BFRPT_PARA_USERID_SEL)\n#define BIT_SET_BFRPT_PARA_USERID_SEL(x, v)                                    \\\n\t(BIT_CLEAR_BFRPT_PARA_USERID_SEL(x) | BIT_BFRPT_PARA_USERID_SEL(v))\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/* 2 REG_WMAC_MU_BFRPT_PARA\t\t\t(Offset 0x1682) */\n\n#define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL 12\n#define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL 0x7\n#define BIT_BIT_BFRPT_PARA_USERID_SEL(x)                                       \\\n\t(((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL)                            \\\n\t << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL)\n#define BITS_BIT_BFRPT_PARA_USERID_SEL                                         \\\n\t(BIT_MASK_BIT_BFRPT_PARA_USERID_SEL                                    \\\n\t << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL)\n#define BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL(x)                                 \\\n\t((x) & (~BITS_BIT_BFRPT_PARA_USERID_SEL))\n#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL(x)                                   \\\n\t(((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) &                        \\\n\t BIT_MASK_BIT_BFRPT_PARA_USERID_SEL)\n#define BIT_SET_BIT_BFRPT_PARA_USERID_SEL(x, v)                                \\\n\t(BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL(x) |                              \\\n\t BIT_BIT_BFRPT_PARA_USERID_SEL(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_WMAC_MU_BFRPT_PARA\t\t\t(Offset 0x1682) */\n\n#define BIT_SHIFT_BFRPT_PARA 0\n#define BIT_MASK_BFRPT_PARA 0xfff\n#define BIT_BFRPT_PARA(x) (((x) & BIT_MASK_BFRPT_PARA) << BIT_SHIFT_BFRPT_PARA)\n#define BITS_BFRPT_PARA (BIT_MASK_BFRPT_PARA << BIT_SHIFT_BFRPT_PARA)\n#define BIT_CLEAR_BFRPT_PARA(x) ((x) & (~BITS_BFRPT_PARA))\n#define BIT_GET_BFRPT_PARA(x)                                                  \\\n\t(((x) >> BIT_SHIFT_BFRPT_PARA) & BIT_MASK_BFRPT_PARA)\n#define BIT_SET_BFRPT_PARA(x, v) (BIT_CLEAR_BFRPT_PARA(x) | BIT_BFRPT_PARA(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_MU_BFRPT_PARA\t\t\t(Offset 0x1682) */\n\n#define BIT_SHIFT_BFRPT_PARA_V1 0\n#define BIT_MASK_BFRPT_PARA_V1 0x1fff\n#define BIT_BFRPT_PARA_V1(x)                                                   \\\n\t(((x) & BIT_MASK_BFRPT_PARA_V1) << BIT_SHIFT_BFRPT_PARA_V1)\n#define BITS_BFRPT_PARA_V1 (BIT_MASK_BFRPT_PARA_V1 << BIT_SHIFT_BFRPT_PARA_V1)\n#define BIT_CLEAR_BFRPT_PARA_V1(x) ((x) & (~BITS_BFRPT_PARA_V1))\n#define BIT_GET_BFRPT_PARA_V1(x)                                               \\\n\t(((x) >> BIT_SHIFT_BFRPT_PARA_V1) & BIT_MASK_BFRPT_PARA_V1)\n#define BIT_SET_BFRPT_PARA_V1(x, v)                                            \\\n\t(BIT_CLEAR_BFRPT_PARA_V1(x) | BIT_BFRPT_PARA_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2\t\t(Offset 0x1684) */\n\n#define BIT_STATUS_BFEE2 BIT(10)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2\t\t(Offset 0x1684) */\n\n#define BIT_WMAC_MU_BFEE2_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2\t\t(Offset 0x1684) */\n\n#define BIT_WMAC_MU_BFEE2_USER_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2\t\t(Offset 0x1684) */\n\n#define BIT_SHIFT_WMAC_MU_BFEE2_AID 0\n#define BIT_MASK_WMAC_MU_BFEE2_AID 0x1ff\n#define BIT_WMAC_MU_BFEE2_AID(x)                                               \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE2_AID) << BIT_SHIFT_WMAC_MU_BFEE2_AID)\n#define BITS_WMAC_MU_BFEE2_AID                                                 \\\n\t(BIT_MASK_WMAC_MU_BFEE2_AID << BIT_SHIFT_WMAC_MU_BFEE2_AID)\n#define BIT_CLEAR_WMAC_MU_BFEE2_AID(x) ((x) & (~BITS_WMAC_MU_BFEE2_AID))\n#define BIT_GET_WMAC_MU_BFEE2_AID(x)                                           \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID) & BIT_MASK_WMAC_MU_BFEE2_AID)\n#define BIT_SET_WMAC_MU_BFEE2_AID(x, v)                                        \\\n\t(BIT_CLEAR_WMAC_MU_BFEE2_AID(x) | BIT_WMAC_MU_BFEE2_AID(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3\t\t(Offset 0x1686) */\n\n#define BIT_STATUS_BFEE3 BIT(10)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3\t\t(Offset 0x1686) */\n\n#define BIT_WMAC_MU_BFEE3_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3\t\t(Offset 0x1686) */\n\n#define BIT_WMAC_MU_BFEE3_USER_EN BIT(9)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3\t\t(Offset 0x1686) */\n\n#define BIT_SHIFT_WMAC_MU_BFEE3_AID 0\n#define BIT_MASK_WMAC_MU_BFEE3_AID 0x1ff\n#define BIT_WMAC_MU_BFEE3_AID(x)                                               \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE3_AID) << BIT_SHIFT_WMAC_MU_BFEE3_AID)\n#define BITS_WMAC_MU_BFEE3_AID                                                 \\\n\t(BIT_MASK_WMAC_MU_BFEE3_AID << BIT_SHIFT_WMAC_MU_BFEE3_AID)\n#define BIT_CLEAR_WMAC_MU_BFEE3_AID(x) ((x) & (~BITS_WMAC_MU_BFEE3_AID))\n#define BIT_GET_WMAC_MU_BFEE3_AID(x)                                           \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID) & BIT_MASK_WMAC_MU_BFEE3_AID)\n#define BIT_SET_WMAC_MU_BFEE3_AID(x, v)                                        \\\n\t(BIT_CLEAR_WMAC_MU_BFEE3_AID(x) | BIT_WMAC_MU_BFEE3_AID(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4\t\t(Offset 0x1688) */\n\n#define BIT_STATUS_BFEE4 BIT(10)\n#define BIT_WMAC_MU_BFEE4_EN BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE4_AID 0\n#define BIT_MASK_WMAC_MU_BFEE4_AID 0x1ff\n#define BIT_WMAC_MU_BFEE4_AID(x)                                               \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE4_AID) << BIT_SHIFT_WMAC_MU_BFEE4_AID)\n#define BITS_WMAC_MU_BFEE4_AID                                                 \\\n\t(BIT_MASK_WMAC_MU_BFEE4_AID << BIT_SHIFT_WMAC_MU_BFEE4_AID)\n#define BIT_CLEAR_WMAC_MU_BFEE4_AID(x) ((x) & (~BITS_WMAC_MU_BFEE4_AID))\n#define BIT_GET_WMAC_MU_BFEE4_AID(x)                                           \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID) & BIT_MASK_WMAC_MU_BFEE4_AID)\n#define BIT_SET_WMAC_MU_BFEE4_AID(x, v)                                        \\\n\t(BIT_CLEAR_WMAC_MU_BFEE4_AID(x) | BIT_WMAC_MU_BFEE4_AID(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5\t\t(Offset 0x168A) */\n\n#define BIT_STATUS_BFEE5 BIT(10)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5\t\t(Offset 0x168A) */\n\n#define BIT_BIT_STATUS_BFEE5 BIT(10)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5\t\t(Offset 0x168A) */\n\n#define BIT_WMAC_MU_BFEE5_EN BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE5_AID 0\n#define BIT_MASK_WMAC_MU_BFEE5_AID 0x1ff\n#define BIT_WMAC_MU_BFEE5_AID(x)                                               \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE5_AID) << BIT_SHIFT_WMAC_MU_BFEE5_AID)\n#define BITS_WMAC_MU_BFEE5_AID                                                 \\\n\t(BIT_MASK_WMAC_MU_BFEE5_AID << BIT_SHIFT_WMAC_MU_BFEE5_AID)\n#define BIT_CLEAR_WMAC_MU_BFEE5_AID(x) ((x) & (~BITS_WMAC_MU_BFEE5_AID))\n#define BIT_GET_WMAC_MU_BFEE5_AID(x)                                           \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID) & BIT_MASK_WMAC_MU_BFEE5_AID)\n#define BIT_SET_WMAC_MU_BFEE5_AID(x, v)                                        \\\n\t(BIT_CLEAR_WMAC_MU_BFEE5_AID(x) | BIT_WMAC_MU_BFEE5_AID(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6\t\t(Offset 0x168C) */\n\n#define BIT_STATUS_BFEE6 BIT(10)\n#define BIT_WMAC_MU_BFEE6_EN BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE6_AID 0\n#define BIT_MASK_WMAC_MU_BFEE6_AID 0x1ff\n#define BIT_WMAC_MU_BFEE6_AID(x)                                               \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE6_AID) << BIT_SHIFT_WMAC_MU_BFEE6_AID)\n#define BITS_WMAC_MU_BFEE6_AID                                                 \\\n\t(BIT_MASK_WMAC_MU_BFEE6_AID << BIT_SHIFT_WMAC_MU_BFEE6_AID)\n#define BIT_CLEAR_WMAC_MU_BFEE6_AID(x) ((x) & (~BITS_WMAC_MU_BFEE6_AID))\n#define BIT_GET_WMAC_MU_BFEE6_AID(x)                                           \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID) & BIT_MASK_WMAC_MU_BFEE6_AID)\n#define BIT_SET_WMAC_MU_BFEE6_AID(x, v)                                        \\\n\t(BIT_CLEAR_WMAC_MU_BFEE6_AID(x) | BIT_WMAC_MU_BFEE6_AID(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7\t\t(Offset 0x168E) */\n\n#define BIT_BIT_STATUS_BFEE4 BIT(10)\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7\t\t(Offset 0x168E) */\n\n#define BIT_STATUS_BFEE7 BIT(10)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7\t\t(Offset 0x168E) */\n\n#define BIT_WMAC_MU_BFEE7_EN BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE7_AID 0\n#define BIT_MASK_WMAC_MU_BFEE7_AID 0x1ff\n#define BIT_WMAC_MU_BFEE7_AID(x)                                               \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE7_AID) << BIT_SHIFT_WMAC_MU_BFEE7_AID)\n#define BITS_WMAC_MU_BFEE7_AID                                                 \\\n\t(BIT_MASK_WMAC_MU_BFEE7_AID << BIT_SHIFT_WMAC_MU_BFEE7_AID)\n#define BIT_CLEAR_WMAC_MU_BFEE7_AID(x) ((x) & (~BITS_WMAC_MU_BFEE7_AID))\n#define BIT_GET_WMAC_MU_BFEE7_AID(x)                                           \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID) & BIT_MASK_WMAC_MU_BFEE7_AID)\n#define BIT_SET_WMAC_MU_BFEE7_AID(x, v)                                        \\\n\t(BIT_CLEAR_WMAC_MU_BFEE7_AID(x) | BIT_WMAC_MU_BFEE7_AID(v))\n\n/* 2 REG_WMAC_BB_STOP_RX_COUNTER\t\t(Offset 0x1690) */\n\n#define BIT_RST_ALL_COUNTER BIT(31)\n\n#define BIT_SHIFT_ABORT_RX_VBON_COUNTER 16\n#define BIT_MASK_ABORT_RX_VBON_COUNTER 0xff\n#define BIT_ABORT_RX_VBON_COUNTER(x)                                           \\\n\t(((x) & BIT_MASK_ABORT_RX_VBON_COUNTER)                                \\\n\t << BIT_SHIFT_ABORT_RX_VBON_COUNTER)\n#define BITS_ABORT_RX_VBON_COUNTER                                             \\\n\t(BIT_MASK_ABORT_RX_VBON_COUNTER << BIT_SHIFT_ABORT_RX_VBON_COUNTER)\n#define BIT_CLEAR_ABORT_RX_VBON_COUNTER(x) ((x) & (~BITS_ABORT_RX_VBON_COUNTER))\n#define BIT_GET_ABORT_RX_VBON_COUNTER(x)                                       \\\n\t(((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER) &                            \\\n\t BIT_MASK_ABORT_RX_VBON_COUNTER)\n#define BIT_SET_ABORT_RX_VBON_COUNTER(x, v)                                    \\\n\t(BIT_CLEAR_ABORT_RX_VBON_COUNTER(x) | BIT_ABORT_RX_VBON_COUNTER(v))\n\n#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER 8\n#define BIT_MASK_ABORT_RX_RDRDY_COUNTER 0xff\n#define BIT_ABORT_RX_RDRDY_COUNTER(x)                                          \\\n\t(((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER)                               \\\n\t << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER)\n#define BITS_ABORT_RX_RDRDY_COUNTER                                            \\\n\t(BIT_MASK_ABORT_RX_RDRDY_COUNTER << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER)\n#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER(x)                                    \\\n\t((x) & (~BITS_ABORT_RX_RDRDY_COUNTER))\n#define BIT_GET_ABORT_RX_RDRDY_COUNTER(x)                                      \\\n\t(((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) &                           \\\n\t BIT_MASK_ABORT_RX_RDRDY_COUNTER)\n#define BIT_SET_ABORT_RX_RDRDY_COUNTER(x, v)                                   \\\n\t(BIT_CLEAR_ABORT_RX_RDRDY_COUNTER(x) | BIT_ABORT_RX_RDRDY_COUNTER(v))\n\n#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER 0\n#define BIT_MASK_VBON_EARLY_FALLING_COUNTER 0xff\n#define BIT_VBON_EARLY_FALLING_COUNTER(x)                                      \\\n\t(((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER)                           \\\n\t << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER)\n#define BITS_VBON_EARLY_FALLING_COUNTER                                        \\\n\t(BIT_MASK_VBON_EARLY_FALLING_COUNTER                                   \\\n\t << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER)\n#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER(x)                                \\\n\t((x) & (~BITS_VBON_EARLY_FALLING_COUNTER))\n#define BIT_GET_VBON_EARLY_FALLING_COUNTER(x)                                  \\\n\t(((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) &                       \\\n\t BIT_MASK_VBON_EARLY_FALLING_COUNTER)\n#define BIT_SET_VBON_EARLY_FALLING_COUNTER(x, v)                               \\\n\t(BIT_CLEAR_VBON_EARLY_FALLING_COUNTER(x) |                             \\\n\t BIT_VBON_EARLY_FALLING_COUNTER(v))\n\n/* 2 REG_WMAC_PLCP_MONITOR\t\t\t(Offset 0x1694) */\n\n#define BIT_WMAC_PLCP_TRX_SEL BIT(31)\n\n#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL 28\n#define BIT_MASK_WMAC_PLCP_RDSIG_SEL 0x7\n#define BIT_WMAC_PLCP_RDSIG_SEL(x)                                             \\\n\t(((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL)\n#define BITS_WMAC_PLCP_RDSIG_SEL                                               \\\n\t(BIT_MASK_WMAC_PLCP_RDSIG_SEL << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL)\n#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL))\n#define BIT_GET_WMAC_PLCP_RDSIG_SEL(x)                                         \\\n\t(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) & BIT_MASK_WMAC_PLCP_RDSIG_SEL)\n#define BIT_SET_WMAC_PLCP_RDSIG_SEL(x, v)                                      \\\n\t(BIT_CLEAR_WMAC_PLCP_RDSIG_SEL(x) | BIT_WMAC_PLCP_RDSIG_SEL(v))\n\n#define BIT_SHIFT_WMAC_RATE_IDX 24\n#define BIT_MASK_WMAC_RATE_IDX 0xf\n#define BIT_WMAC_RATE_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_WMAC_RATE_IDX) << BIT_SHIFT_WMAC_RATE_IDX)\n#define BITS_WMAC_RATE_IDX (BIT_MASK_WMAC_RATE_IDX << BIT_SHIFT_WMAC_RATE_IDX)\n#define BIT_CLEAR_WMAC_RATE_IDX(x) ((x) & (~BITS_WMAC_RATE_IDX))\n#define BIT_GET_WMAC_RATE_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_WMAC_RATE_IDX) & BIT_MASK_WMAC_RATE_IDX)\n#define BIT_SET_WMAC_RATE_IDX(x, v)                                            \\\n\t(BIT_CLEAR_WMAC_RATE_IDX(x) | BIT_WMAC_RATE_IDX(v))\n\n#define BIT_SHIFT_WMAC_PLCP_RDSIG 0\n#define BIT_MASK_WMAC_PLCP_RDSIG 0xffffff\n#define BIT_WMAC_PLCP_RDSIG(x)                                                 \\\n\t(((x) & BIT_MASK_WMAC_PLCP_RDSIG) << BIT_SHIFT_WMAC_PLCP_RDSIG)\n#define BITS_WMAC_PLCP_RDSIG                                                   \\\n\t(BIT_MASK_WMAC_PLCP_RDSIG << BIT_SHIFT_WMAC_PLCP_RDSIG)\n#define BIT_CLEAR_WMAC_PLCP_RDSIG(x) ((x) & (~BITS_WMAC_PLCP_RDSIG))\n#define BIT_GET_WMAC_PLCP_RDSIG(x)                                             \\\n\t(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG) & BIT_MASK_WMAC_PLCP_RDSIG)\n#define BIT_SET_WMAC_PLCP_RDSIG(x, v)                                          \\\n\t(BIT_CLEAR_WMAC_PLCP_RDSIG(x) | BIT_WMAC_PLCP_RDSIG(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_PLCP_MONITOR_MUTX\t\t(Offset 0x1698) */\n\n#define BIT_WMAC_MUTX_IDX BIT(24)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_WMAC_DEBUG_PORT\t\t\t(Offset 0x1698) */\n\n#define BIT_SHIFT_WMAC_DEBUG_PORT 0\n#define BIT_MASK_WMAC_DEBUG_PORT 0xffffffffL\n#define BIT_WMAC_DEBUG_PORT(x)                                                 \\\n\t(((x) & BIT_MASK_WMAC_DEBUG_PORT) << BIT_SHIFT_WMAC_DEBUG_PORT)\n#define BITS_WMAC_DEBUG_PORT                                                   \\\n\t(BIT_MASK_WMAC_DEBUG_PORT << BIT_SHIFT_WMAC_DEBUG_PORT)\n#define BIT_CLEAR_WMAC_DEBUG_PORT(x) ((x) & (~BITS_WMAC_DEBUG_PORT))\n#define BIT_GET_WMAC_DEBUG_PORT(x)                                             \\\n\t(((x) >> BIT_SHIFT_WMAC_DEBUG_PORT) & BIT_MASK_WMAC_DEBUG_PORT)\n#define BIT_SET_WMAC_DEBUG_PORT(x, v)                                          \\\n\t(BIT_CLEAR_WMAC_DEBUG_PORT(x) | BIT_WMAC_DEBUG_PORT(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WMAC_CSIDMA_CFG\t\t\t(Offset 0x169C) */\n\n#define BIT_SHIFT_CSI_SEG_SIZE 16\n#define BIT_MASK_CSI_SEG_SIZE 0xfff\n#define BIT_CSI_SEG_SIZE(x)                                                    \\\n\t(((x) & BIT_MASK_CSI_SEG_SIZE) << BIT_SHIFT_CSI_SEG_SIZE)\n#define BITS_CSI_SEG_SIZE (BIT_MASK_CSI_SEG_SIZE << BIT_SHIFT_CSI_SEG_SIZE)\n#define BIT_CLEAR_CSI_SEG_SIZE(x) ((x) & (~BITS_CSI_SEG_SIZE))\n#define BIT_GET_CSI_SEG_SIZE(x)                                                \\\n\t(((x) >> BIT_SHIFT_CSI_SEG_SIZE) & BIT_MASK_CSI_SEG_SIZE)\n#define BIT_SET_CSI_SEG_SIZE(x, v)                                             \\\n\t(BIT_CLEAR_CSI_SEG_SIZE(x) | BIT_CSI_SEG_SIZE(v))\n\n#define BIT_SHIFT_CSI_START_PAGE 0\n#define BIT_MASK_CSI_START_PAGE 0xfff\n#define BIT_CSI_START_PAGE(x)                                                  \\\n\t(((x) & BIT_MASK_CSI_START_PAGE) << BIT_SHIFT_CSI_START_PAGE)\n#define BITS_CSI_START_PAGE                                                    \\\n\t(BIT_MASK_CSI_START_PAGE << BIT_SHIFT_CSI_START_PAGE)\n#define BIT_CLEAR_CSI_START_PAGE(x) ((x) & (~BITS_CSI_START_PAGE))\n#define BIT_GET_CSI_START_PAGE(x)                                              \\\n\t(((x) >> BIT_SHIFT_CSI_START_PAGE) & BIT_MASK_CSI_START_PAGE)\n#define BIT_SET_CSI_START_PAGE(x, v)                                           \\\n\t(BIT_CLEAR_CSI_START_PAGE(x) | BIT_CSI_START_PAGE(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_TRANSMIT_ADDRSS_0\t\t\t(Offset 0x16A0) */\n\n#define BIT_SHIFT_TA0 0\n#define BIT_MASK_TA0 0xffffffffffffL\n#define BIT_TA0(x) (((x) & BIT_MASK_TA0) << BIT_SHIFT_TA0)\n#define BITS_TA0 (BIT_MASK_TA0 << BIT_SHIFT_TA0)\n#define BIT_CLEAR_TA0(x) ((x) & (~BITS_TA0))\n#define BIT_GET_TA0(x) (((x) >> BIT_SHIFT_TA0) & BIT_MASK_TA0)\n#define BIT_SET_TA0(x, v) (BIT_CLEAR_TA0(x) | BIT_TA0(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TRANSMIT_ADDRSS_0\t\t\t(Offset 0x16A0) */\n\n#define BIT_SHIFT_TA0_V1 0\n#define BIT_MASK_TA0_V1 0xffffffffL\n#define BIT_TA0_V1(x) (((x) & BIT_MASK_TA0_V1) << BIT_SHIFT_TA0_V1)\n#define BITS_TA0_V1 (BIT_MASK_TA0_V1 << BIT_SHIFT_TA0_V1)\n#define BIT_CLEAR_TA0_V1(x) ((x) & (~BITS_TA0_V1))\n#define BIT_GET_TA0_V1(x) (((x) >> BIT_SHIFT_TA0_V1) & BIT_MASK_TA0_V1)\n#define BIT_SET_TA0_V1(x, v) (BIT_CLEAR_TA0_V1(x) | BIT_TA0_V1(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_0_H\t\t\t(Offset 0x16A4) */\n\n#define BIT_SHIFT_TA0_H_V1 0\n#define BIT_MASK_TA0_H_V1 0xffff\n#define BIT_TA0_H_V1(x) (((x) & BIT_MASK_TA0_H_V1) << BIT_SHIFT_TA0_H_V1)\n#define BITS_TA0_H_V1 (BIT_MASK_TA0_H_V1 << BIT_SHIFT_TA0_H_V1)\n#define BIT_CLEAR_TA0_H_V1(x) ((x) & (~BITS_TA0_H_V1))\n#define BIT_GET_TA0_H_V1(x) (((x) >> BIT_SHIFT_TA0_H_V1) & BIT_MASK_TA0_H_V1)\n#define BIT_SET_TA0_H_V1(x, v) (BIT_CLEAR_TA0_H_V1(x) | BIT_TA0_H_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_TRANSMIT_ADDRSS_1\t\t\t(Offset 0x16A8) */\n\n#define BIT_SHIFT_TA1 0\n#define BIT_MASK_TA1 0xffffffffffffL\n#define BIT_TA1(x) (((x) & BIT_MASK_TA1) << BIT_SHIFT_TA1)\n#define BITS_TA1 (BIT_MASK_TA1 << BIT_SHIFT_TA1)\n#define BIT_CLEAR_TA1(x) ((x) & (~BITS_TA1))\n#define BIT_GET_TA1(x) (((x) >> BIT_SHIFT_TA1) & BIT_MASK_TA1)\n#define BIT_SET_TA1(x, v) (BIT_CLEAR_TA1(x) | BIT_TA1(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TRANSMIT_ADDRSS_1\t\t\t(Offset 0x16A8) */\n\n#define BIT_SHIFT_TA1_V1 0\n#define BIT_MASK_TA1_V1 0xffffffffL\n#define BIT_TA1_V1(x) (((x) & BIT_MASK_TA1_V1) << BIT_SHIFT_TA1_V1)\n#define BITS_TA1_V1 (BIT_MASK_TA1_V1 << BIT_SHIFT_TA1_V1)\n#define BIT_CLEAR_TA1_V1(x) ((x) & (~BITS_TA1_V1))\n#define BIT_GET_TA1_V1(x) (((x) >> BIT_SHIFT_TA1_V1) & BIT_MASK_TA1_V1)\n#define BIT_SET_TA1_V1(x, v) (BIT_CLEAR_TA1_V1(x) | BIT_TA1_V1(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_1_H\t\t\t(Offset 0x16AC) */\n\n#define BIT_SHIFT_TA1_H_V1 0\n#define BIT_MASK_TA1_H_V1 0xffff\n#define BIT_TA1_H_V1(x) (((x) & BIT_MASK_TA1_H_V1) << BIT_SHIFT_TA1_H_V1)\n#define BITS_TA1_H_V1 (BIT_MASK_TA1_H_V1 << BIT_SHIFT_TA1_H_V1)\n#define BIT_CLEAR_TA1_H_V1(x) ((x) & (~BITS_TA1_H_V1))\n#define BIT_GET_TA1_H_V1(x) (((x) >> BIT_SHIFT_TA1_H_V1) & BIT_MASK_TA1_H_V1)\n#define BIT_SET_TA1_H_V1(x, v) (BIT_CLEAR_TA1_H_V1(x) | BIT_TA1_H_V1(v))\n\n#define BIT_SHIFT_TA2_V1 0\n#define BIT_MASK_TA2_V1 0xffffffffL\n#define BIT_TA2_V1(x) (((x) & BIT_MASK_TA2_V1) << BIT_SHIFT_TA2_V1)\n#define BITS_TA2_V1 (BIT_MASK_TA2_V1 << BIT_SHIFT_TA2_V1)\n#define BIT_CLEAR_TA2_V1(x) ((x) & (~BITS_TA2_V1))\n#define BIT_GET_TA2_V1(x) (((x) >> BIT_SHIFT_TA2_V1) & BIT_MASK_TA2_V1)\n#define BIT_SET_TA2_V1(x, v) (BIT_CLEAR_TA2_V1(x) | BIT_TA2_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_TRANSMIT_ADDRSS_2\t\t\t(Offset 0x16B0) */\n\n#define BIT_SHIFT_TA2 0\n#define BIT_MASK_TA2 0xffffffffffffL\n#define BIT_TA2(x) (((x) & BIT_MASK_TA2) << BIT_SHIFT_TA2)\n#define BITS_TA2 (BIT_MASK_TA2 << BIT_SHIFT_TA2)\n#define BIT_CLEAR_TA2(x) ((x) & (~BITS_TA2))\n#define BIT_GET_TA2(x) (((x) >> BIT_SHIFT_TA2) & BIT_MASK_TA2)\n#define BIT_SET_TA2(x, v) (BIT_CLEAR_TA2(x) | BIT_TA2(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TRANSMIT_ADDRSS_2_H\t\t\t(Offset 0x16B4) */\n\n#define BIT_SHIFT_TA2_H_V1 0\n#define BIT_MASK_TA2_H_V1 0xffff\n#define BIT_TA2_H_V1(x) (((x) & BIT_MASK_TA2_H_V1) << BIT_SHIFT_TA2_H_V1)\n#define BITS_TA2_H_V1 (BIT_MASK_TA2_H_V1 << BIT_SHIFT_TA2_H_V1)\n#define BIT_CLEAR_TA2_H_V1(x) ((x) & (~BITS_TA2_H_V1))\n#define BIT_GET_TA2_H_V1(x) (((x) >> BIT_SHIFT_TA2_H_V1) & BIT_MASK_TA2_H_V1)\n#define BIT_SET_TA2_H_V1(x, v) (BIT_CLEAR_TA2_H_V1(x) | BIT_TA2_H_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_TRANSMIT_ADDRSS_3\t\t\t(Offset 0x16B8) */\n\n#define BIT_SHIFT_TA3 0\n#define BIT_MASK_TA3 0xffffffffffffL\n#define BIT_TA3(x) (((x) & BIT_MASK_TA3) << BIT_SHIFT_TA3)\n#define BITS_TA3 (BIT_MASK_TA3 << BIT_SHIFT_TA3)\n#define BIT_CLEAR_TA3(x) ((x) & (~BITS_TA3))\n#define BIT_GET_TA3(x) (((x) >> BIT_SHIFT_TA3) & BIT_MASK_TA3)\n#define BIT_SET_TA3(x, v) (BIT_CLEAR_TA3(x) | BIT_TA3(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TRANSMIT_ADDRSS_3_H\t\t\t(Offset 0x16BC) */\n\n#define BIT_SHIFT_TA3_H_V1 0\n#define BIT_MASK_TA3_H_V1 0xffff\n#define BIT_TA3_H_V1(x) (((x) & BIT_MASK_TA3_H_V1) << BIT_SHIFT_TA3_H_V1)\n#define BITS_TA3_H_V1 (BIT_MASK_TA3_H_V1 << BIT_SHIFT_TA3_H_V1)\n#define BIT_CLEAR_TA3_H_V1(x) ((x) & (~BITS_TA3_H_V1))\n#define BIT_GET_TA3_H_V1(x) (((x) >> BIT_SHIFT_TA3_H_V1) & BIT_MASK_TA3_H_V1)\n#define BIT_SET_TA3_H_V1(x, v) (BIT_CLEAR_TA3_H_V1(x) | BIT_TA3_H_V1(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n/* 2 REG_TRANSMIT_ADDRSS_4\t\t\t(Offset 0x16C0) */\n\n#define BIT_R_WMAC_RX_SYNCFIFO_SYNC BIT(55)\n#define BIT_R_WMAC_RXRST_DLY BIT(54)\n#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP BIT(53)\n#define BIT_R_WMAC_SRCH_TXRPT_UA1 BIT(52)\n\n#define BIT_SHIFT_TA4 0\n#define BIT_MASK_TA4 0xffffffffffffL\n#define BIT_TA4(x) (((x) & BIT_MASK_TA4) << BIT_SHIFT_TA4)\n#define BITS_TA4 (BIT_MASK_TA4 << BIT_SHIFT_TA4)\n#define BIT_CLEAR_TA4(x) ((x) & (~BITS_TA4))\n#define BIT_GET_TA4(x) (((x) >> BIT_SHIFT_TA4) & BIT_MASK_TA4)\n#define BIT_SET_TA4(x, v) (BIT_CLEAR_TA4(x) | BIT_TA4(v))\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_TRANSMIT_ADDRSS_4\t\t\t(Offset 0x16C0) */\n\n#define BIT_SHIFT_TA4_V1 0\n#define BIT_MASK_TA4_V1 0xffffffffL\n#define BIT_TA4_V1(x) (((x) & BIT_MASK_TA4_V1) << BIT_SHIFT_TA4_V1)\n#define BITS_TA4_V1 (BIT_MASK_TA4_V1 << BIT_SHIFT_TA4_V1)\n#define BIT_CLEAR_TA4_V1(x) ((x) & (~BITS_TA4_V1))\n#define BIT_GET_TA4_V1(x) (((x) >> BIT_SHIFT_TA4_V1) & BIT_MASK_TA4_V1)\n#define BIT_SET_TA4_V1(x, v) (BIT_CLEAR_TA4_V1(x) | BIT_TA4_V1(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_4_H\t\t\t(Offset 0x16C4) */\n\n#define BIT_SHIFT_TA4_H_V1 0\n#define BIT_MASK_TA4_H_V1 0xffff\n#define BIT_TA4_H_V1(x) (((x) & BIT_MASK_TA4_H_V1) << BIT_SHIFT_TA4_H_V1)\n#define BITS_TA4_H_V1 (BIT_MASK_TA4_H_V1 << BIT_SHIFT_TA4_H_V1)\n#define BIT_CLEAR_TA4_H_V1(x) ((x) & (~BITS_TA4_H_V1))\n#define BIT_GET_TA4_H_V1(x) (((x) >> BIT_SHIFT_TA4_H_V1) & BIT_MASK_TA4_H_V1)\n#define BIT_SET_TA4_H_V1(x, v) (BIT_CLEAR_TA4_H_V1(x) | BIT_TA4_H_V1(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n/* 2 REG_SND_AID12\t\t\t\t(Offset 0x16D0) */\n\n#define BIT_SHIFT_USERID_SEL 12\n#define BIT_MASK_USERID_SEL 0x7\n#define BIT_USERID_SEL(x) (((x) & BIT_MASK_USERID_SEL) << BIT_SHIFT_USERID_SEL)\n#define BITS_USERID_SEL (BIT_MASK_USERID_SEL << BIT_SHIFT_USERID_SEL)\n#define BIT_CLEAR_USERID_SEL(x) ((x) & (~BITS_USERID_SEL))\n#define BIT_GET_USERID_SEL(x)                                                  \\\n\t(((x) >> BIT_SHIFT_USERID_SEL) & BIT_MASK_USERID_SEL)\n#define BIT_SET_USERID_SEL(x, v) (BIT_CLEAR_USERID_SEL(x) | BIT_USERID_SEL(v))\n\n#define BIT_SHIFT_USERID_AID12 0\n#define BIT_MASK_USERID_AID12 0xfff\n#define BIT_USERID_AID12(x)                                                    \\\n\t(((x) & BIT_MASK_USERID_AID12) << BIT_SHIFT_USERID_AID12)\n#define BITS_USERID_AID12 (BIT_MASK_USERID_AID12 << BIT_SHIFT_USERID_AID12)\n#define BIT_CLEAR_USERID_AID12(x) ((x) & (~BITS_USERID_AID12))\n#define BIT_GET_USERID_AID12(x)                                                \\\n\t(((x) >> BIT_SHIFT_USERID_AID12) & BIT_MASK_USERID_AID12)\n#define BIT_SET_USERID_AID12(x, v)                                             \\\n\t(BIT_CLEAR_USERID_AID12(x) | BIT_USERID_AID12(v))\n\n/* 2 REG_SND_PKT_INFO\t\t\t(Offset 0x16D2) */\n\n#define BIT_SND_FROM_DS BIT(7)\n#define BIT_SND_TO_DS BIT(6)\n\n#define BIT_SHIFT_SND_TOKEN 0\n#define BIT_MASK_SND_TOKEN 0x3f\n#define BIT_SND_TOKEN(x) (((x) & BIT_MASK_SND_TOKEN) << BIT_SHIFT_SND_TOKEN)\n#define BITS_SND_TOKEN (BIT_MASK_SND_TOKEN << BIT_SHIFT_SND_TOKEN)\n#define BIT_CLEAR_SND_TOKEN(x) ((x) & (~BITS_SND_TOKEN))\n#define BIT_GET_SND_TOKEN(x) (((x) >> BIT_SHIFT_SND_TOKEN) & BIT_MASK_SND_TOKEN)\n#define BIT_SET_SND_TOKEN(x, v) (BIT_CLEAR_SND_TOKEN(x) | BIT_SND_TOKEN(v))\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 (Offset 0x1700) */\n\n#define BIT_LTECOEX_ACCESS_START_V1 BIT(31)\n#define BIT_LTECOEX_WRITE_MODE_V1 BIT(30)\n#define BIT_LTECOEX_READY_BIT_V1 BIT(29)\n\n#define BIT_SHIFT_WRITE_BYTE_EN_V1 16\n#define BIT_MASK_WRITE_BYTE_EN_V1 0xf\n#define BIT_WRITE_BYTE_EN_V1(x)                                                \\\n\t(((x) & BIT_MASK_WRITE_BYTE_EN_V1) << BIT_SHIFT_WRITE_BYTE_EN_V1)\n#define BITS_WRITE_BYTE_EN_V1                                                  \\\n\t(BIT_MASK_WRITE_BYTE_EN_V1 << BIT_SHIFT_WRITE_BYTE_EN_V1)\n#define BIT_CLEAR_WRITE_BYTE_EN_V1(x) ((x) & (~BITS_WRITE_BYTE_EN_V1))\n#define BIT_GET_WRITE_BYTE_EN_V1(x)                                            \\\n\t(((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1) & BIT_MASK_WRITE_BYTE_EN_V1)\n#define BIT_SET_WRITE_BYTE_EN_V1(x, v)                                         \\\n\t(BIT_CLEAR_WRITE_BYTE_EN_V1(x) | BIT_WRITE_BYTE_EN_V1(v))\n\n#define BIT_SHIFT_LTECOEX_REG_ADDR_V1 0\n#define BIT_MASK_LTECOEX_REG_ADDR_V1 0xffff\n#define BIT_LTECOEX_REG_ADDR_V1(x)                                             \\\n\t(((x) & BIT_MASK_LTECOEX_REG_ADDR_V1) << BIT_SHIFT_LTECOEX_REG_ADDR_V1)\n#define BITS_LTECOEX_REG_ADDR_V1                                               \\\n\t(BIT_MASK_LTECOEX_REG_ADDR_V1 << BIT_SHIFT_LTECOEX_REG_ADDR_V1)\n#define BIT_CLEAR_LTECOEX_REG_ADDR_V1(x) ((x) & (~BITS_LTECOEX_REG_ADDR_V1))\n#define BIT_GET_LTECOEX_REG_ADDR_V1(x)                                         \\\n\t(((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1) & BIT_MASK_LTECOEX_REG_ADDR_V1)\n#define BIT_SET_LTECOEX_REG_ADDR_V1(x, v)                                      \\\n\t(BIT_CLEAR_LTECOEX_REG_ADDR_V1(x) | BIT_LTECOEX_REG_ADDR_V1(v))\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 (Offset 0x1704) */\n\n#define BIT_SHIFT_LTECOEX_W_DATA_V1 0\n#define BIT_MASK_LTECOEX_W_DATA_V1 0xffffffffL\n#define BIT_LTECOEX_W_DATA_V1(x)                                               \\\n\t(((x) & BIT_MASK_LTECOEX_W_DATA_V1) << BIT_SHIFT_LTECOEX_W_DATA_V1)\n#define BITS_LTECOEX_W_DATA_V1                                                 \\\n\t(BIT_MASK_LTECOEX_W_DATA_V1 << BIT_SHIFT_LTECOEX_W_DATA_V1)\n#define BIT_CLEAR_LTECOEX_W_DATA_V1(x) ((x) & (~BITS_LTECOEX_W_DATA_V1))\n#define BIT_GET_LTECOEX_W_DATA_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1) & BIT_MASK_LTECOEX_W_DATA_V1)\n#define BIT_SET_LTECOEX_W_DATA_V1(x, v)                                        \\\n\t(BIT_CLEAR_LTECOEX_W_DATA_V1(x) | BIT_LTECOEX_W_DATA_V1(v))\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 (Offset 0x1708) */\n\n#define BIT_SHIFT_LTECOEX_R_DATA_V1 0\n#define BIT_MASK_LTECOEX_R_DATA_V1 0xffffffffL\n#define BIT_LTECOEX_R_DATA_V1(x)                                               \\\n\t(((x) & BIT_MASK_LTECOEX_R_DATA_V1) << BIT_SHIFT_LTECOEX_R_DATA_V1)\n#define BITS_LTECOEX_R_DATA_V1                                                 \\\n\t(BIT_MASK_LTECOEX_R_DATA_V1 << BIT_SHIFT_LTECOEX_R_DATA_V1)\n#define BIT_CLEAR_LTECOEX_R_DATA_V1(x) ((x) & (~BITS_LTECOEX_R_DATA_V1))\n#define BIT_GET_LTECOEX_R_DATA_V1(x)                                           \\\n\t(((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1) & BIT_MASK_LTECOEX_R_DATA_V1)\n#define BIT_SET_LTECOEX_R_DATA_V1(x, v)                                        \\\n\t(BIT_CLEAR_LTECOEX_R_DATA_V1(x) | BIT_LTECOEX_R_DATA_V1(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_DMA_RQPN_INFO_0\t\t\t(Offset 0x2200) */\n\n#define BIT_SHIFT_CH0_AVAL_PG 16\n#define BIT_MASK_CH0_AVAL_PG 0xfff\n#define BIT_CH0_AVAL_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH0_AVAL_PG) << BIT_SHIFT_CH0_AVAL_PG)\n#define BITS_CH0_AVAL_PG (BIT_MASK_CH0_AVAL_PG << BIT_SHIFT_CH0_AVAL_PG)\n#define BIT_CLEAR_CH0_AVAL_PG(x) ((x) & (~BITS_CH0_AVAL_PG))\n#define BIT_GET_CH0_AVAL_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH0_AVAL_PG) & BIT_MASK_CH0_AVAL_PG)\n#define BIT_SET_CH0_AVAL_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH0_AVAL_PG(x) | BIT_CH0_AVAL_PG(v))\n\n#define BIT_SHIFT_CH0_RSVD_PG 0\n#define BIT_MASK_CH0_RSVD_PG 0xfff\n#define BIT_CH0_RSVD_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH0_RSVD_PG) << BIT_SHIFT_CH0_RSVD_PG)\n#define BITS_CH0_RSVD_PG (BIT_MASK_CH0_RSVD_PG << BIT_SHIFT_CH0_RSVD_PG)\n#define BIT_CLEAR_CH0_RSVD_PG(x) ((x) & (~BITS_CH0_RSVD_PG))\n#define BIT_GET_CH0_RSVD_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH0_RSVD_PG) & BIT_MASK_CH0_RSVD_PG)\n#define BIT_SET_CH0_RSVD_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH0_RSVD_PG(x) | BIT_CH0_RSVD_PG(v))\n\n/* 2 REG_DMA_RQPN_INFO_1\t\t\t(Offset 0x2204) */\n\n#define BIT_SHIFT_CH1_AVAL_PG 16\n#define BIT_MASK_CH1_AVAL_PG 0xfff\n#define BIT_CH1_AVAL_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH1_AVAL_PG) << BIT_SHIFT_CH1_AVAL_PG)\n#define BITS_CH1_AVAL_PG (BIT_MASK_CH1_AVAL_PG << BIT_SHIFT_CH1_AVAL_PG)\n#define BIT_CLEAR_CH1_AVAL_PG(x) ((x) & (~BITS_CH1_AVAL_PG))\n#define BIT_GET_CH1_AVAL_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH1_AVAL_PG) & BIT_MASK_CH1_AVAL_PG)\n#define BIT_SET_CH1_AVAL_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH1_AVAL_PG(x) | BIT_CH1_AVAL_PG(v))\n\n#define BIT_SHIFT_CH1_RSVD_PG 0\n#define BIT_MASK_CH1_RSVD_PG 0xfff\n#define BIT_CH1_RSVD_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH1_RSVD_PG) << BIT_SHIFT_CH1_RSVD_PG)\n#define BITS_CH1_RSVD_PG (BIT_MASK_CH1_RSVD_PG << BIT_SHIFT_CH1_RSVD_PG)\n#define BIT_CLEAR_CH1_RSVD_PG(x) ((x) & (~BITS_CH1_RSVD_PG))\n#define BIT_GET_CH1_RSVD_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH1_RSVD_PG) & BIT_MASK_CH1_RSVD_PG)\n#define BIT_SET_CH1_RSVD_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH1_RSVD_PG(x) | BIT_CH1_RSVD_PG(v))\n\n/* 2 REG_DMA_RQPN_INFO_2\t\t\t(Offset 0x2208) */\n\n#define BIT_SHIFT_CH2_AVAL_PG 16\n#define BIT_MASK_CH2_AVAL_PG 0xfff\n#define BIT_CH2_AVAL_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH2_AVAL_PG) << BIT_SHIFT_CH2_AVAL_PG)\n#define BITS_CH2_AVAL_PG (BIT_MASK_CH2_AVAL_PG << BIT_SHIFT_CH2_AVAL_PG)\n#define BIT_CLEAR_CH2_AVAL_PG(x) ((x) & (~BITS_CH2_AVAL_PG))\n#define BIT_GET_CH2_AVAL_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH2_AVAL_PG) & BIT_MASK_CH2_AVAL_PG)\n#define BIT_SET_CH2_AVAL_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH2_AVAL_PG(x) | BIT_CH2_AVAL_PG(v))\n\n#define BIT_SHIFT_CH2_RSVD_PG 0\n#define BIT_MASK_CH2_RSVD_PG 0xfff\n#define BIT_CH2_RSVD_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH2_RSVD_PG) << BIT_SHIFT_CH2_RSVD_PG)\n#define BITS_CH2_RSVD_PG (BIT_MASK_CH2_RSVD_PG << BIT_SHIFT_CH2_RSVD_PG)\n#define BIT_CLEAR_CH2_RSVD_PG(x) ((x) & (~BITS_CH2_RSVD_PG))\n#define BIT_GET_CH2_RSVD_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH2_RSVD_PG) & BIT_MASK_CH2_RSVD_PG)\n#define BIT_SET_CH2_RSVD_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH2_RSVD_PG(x) | BIT_CH2_RSVD_PG(v))\n\n/* 2 REG_DMA_RQPN_INFO_3\t\t\t(Offset 0x220C) */\n\n#define BIT_SHIFT_CH3_AVAL_PG 16\n#define BIT_MASK_CH3_AVAL_PG 0xfff\n#define BIT_CH3_AVAL_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH3_AVAL_PG) << BIT_SHIFT_CH3_AVAL_PG)\n#define BITS_CH3_AVAL_PG (BIT_MASK_CH3_AVAL_PG << BIT_SHIFT_CH3_AVAL_PG)\n#define BIT_CLEAR_CH3_AVAL_PG(x) ((x) & (~BITS_CH3_AVAL_PG))\n#define BIT_GET_CH3_AVAL_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH3_AVAL_PG) & BIT_MASK_CH3_AVAL_PG)\n#define BIT_SET_CH3_AVAL_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH3_AVAL_PG(x) | BIT_CH3_AVAL_PG(v))\n\n#define BIT_SHIFT_CH3_RSVD_PG 0\n#define BIT_MASK_CH3_RSVD_PG 0xfff\n#define BIT_CH3_RSVD_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH3_RSVD_PG) << BIT_SHIFT_CH3_RSVD_PG)\n#define BITS_CH3_RSVD_PG (BIT_MASK_CH3_RSVD_PG << BIT_SHIFT_CH3_RSVD_PG)\n#define BIT_CLEAR_CH3_RSVD_PG(x) ((x) & (~BITS_CH3_RSVD_PG))\n#define BIT_GET_CH3_RSVD_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH3_RSVD_PG) & BIT_MASK_CH3_RSVD_PG)\n#define BIT_SET_CH3_RSVD_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH3_RSVD_PG(x) | BIT_CH3_RSVD_PG(v))\n\n/* 2 REG_DMA_RQPN_INFO_4\t\t\t(Offset 0x2210) */\n\n#define BIT_SHIFT_CH4_AVAL_PG 16\n#define BIT_MASK_CH4_AVAL_PG 0xfff\n#define BIT_CH4_AVAL_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH4_AVAL_PG) << BIT_SHIFT_CH4_AVAL_PG)\n#define BITS_CH4_AVAL_PG (BIT_MASK_CH4_AVAL_PG << BIT_SHIFT_CH4_AVAL_PG)\n#define BIT_CLEAR_CH4_AVAL_PG(x) ((x) & (~BITS_CH4_AVAL_PG))\n#define BIT_GET_CH4_AVAL_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH4_AVAL_PG) & BIT_MASK_CH4_AVAL_PG)\n#define BIT_SET_CH4_AVAL_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH4_AVAL_PG(x) | BIT_CH4_AVAL_PG(v))\n\n#define BIT_SHIFT_CH4_RSVD_PG 0\n#define BIT_MASK_CH4_RSVD_PG 0xfff\n#define BIT_CH4_RSVD_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH4_RSVD_PG) << BIT_SHIFT_CH4_RSVD_PG)\n#define BITS_CH4_RSVD_PG (BIT_MASK_CH4_RSVD_PG << BIT_SHIFT_CH4_RSVD_PG)\n#define BIT_CLEAR_CH4_RSVD_PG(x) ((x) & (~BITS_CH4_RSVD_PG))\n#define BIT_GET_CH4_RSVD_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH4_RSVD_PG) & BIT_MASK_CH4_RSVD_PG)\n#define BIT_SET_CH4_RSVD_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH4_RSVD_PG(x) | BIT_CH4_RSVD_PG(v))\n\n/* 2 REG_DMA_RQPN_INFO_5\t\t\t(Offset 0x2214) */\n\n#define BIT_SHIFT_CH5_AVAL_PG 16\n#define BIT_MASK_CH5_AVAL_PG 0xfff\n#define BIT_CH5_AVAL_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH5_AVAL_PG) << BIT_SHIFT_CH5_AVAL_PG)\n#define BITS_CH5_AVAL_PG (BIT_MASK_CH5_AVAL_PG << BIT_SHIFT_CH5_AVAL_PG)\n#define BIT_CLEAR_CH5_AVAL_PG(x) ((x) & (~BITS_CH5_AVAL_PG))\n#define BIT_GET_CH5_AVAL_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH5_AVAL_PG) & BIT_MASK_CH5_AVAL_PG)\n#define BIT_SET_CH5_AVAL_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH5_AVAL_PG(x) | BIT_CH5_AVAL_PG(v))\n\n#define BIT_SHIFT_CH5_RSVD_PG 0\n#define BIT_MASK_CH5_RSVD_PG 0xfff\n#define BIT_CH5_RSVD_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH5_RSVD_PG) << BIT_SHIFT_CH5_RSVD_PG)\n#define BITS_CH5_RSVD_PG (BIT_MASK_CH5_RSVD_PG << BIT_SHIFT_CH5_RSVD_PG)\n#define BIT_CLEAR_CH5_RSVD_PG(x) ((x) & (~BITS_CH5_RSVD_PG))\n#define BIT_GET_CH5_RSVD_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH5_RSVD_PG) & BIT_MASK_CH5_RSVD_PG)\n#define BIT_SET_CH5_RSVD_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH5_RSVD_PG(x) | BIT_CH5_RSVD_PG(v))\n\n/* 2 REG_DMA_RQPN_INFO_6\t\t\t(Offset 0x2218) */\n\n#define BIT_SHIFT_CH6_AVAL_PG 16\n#define BIT_MASK_CH6_AVAL_PG 0xfff\n#define BIT_CH6_AVAL_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH6_AVAL_PG) << BIT_SHIFT_CH6_AVAL_PG)\n#define BITS_CH6_AVAL_PG (BIT_MASK_CH6_AVAL_PG << BIT_SHIFT_CH6_AVAL_PG)\n#define BIT_CLEAR_CH6_AVAL_PG(x) ((x) & (~BITS_CH6_AVAL_PG))\n#define BIT_GET_CH6_AVAL_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH6_AVAL_PG) & BIT_MASK_CH6_AVAL_PG)\n#define BIT_SET_CH6_AVAL_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH6_AVAL_PG(x) | BIT_CH6_AVAL_PG(v))\n\n#define BIT_SHIFT_CH6_RSVD_PG 0\n#define BIT_MASK_CH6_RSVD_PG 0xfff\n#define BIT_CH6_RSVD_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH6_RSVD_PG) << BIT_SHIFT_CH6_RSVD_PG)\n#define BITS_CH6_RSVD_PG (BIT_MASK_CH6_RSVD_PG << BIT_SHIFT_CH6_RSVD_PG)\n#define BIT_CLEAR_CH6_RSVD_PG(x) ((x) & (~BITS_CH6_RSVD_PG))\n#define BIT_GET_CH6_RSVD_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH6_RSVD_PG) & BIT_MASK_CH6_RSVD_PG)\n#define BIT_SET_CH6_RSVD_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH6_RSVD_PG(x) | BIT_CH6_RSVD_PG(v))\n\n/* 2 REG_DMA_RQPN_INFO_7\t\t\t(Offset 0x221C) */\n\n#define BIT_SHIFT_CH7_AVAL_PG 16\n#define BIT_MASK_CH7_AVAL_PG 0xfff\n#define BIT_CH7_AVAL_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH7_AVAL_PG) << BIT_SHIFT_CH7_AVAL_PG)\n#define BITS_CH7_AVAL_PG (BIT_MASK_CH7_AVAL_PG << BIT_SHIFT_CH7_AVAL_PG)\n#define BIT_CLEAR_CH7_AVAL_PG(x) ((x) & (~BITS_CH7_AVAL_PG))\n#define BIT_GET_CH7_AVAL_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH7_AVAL_PG) & BIT_MASK_CH7_AVAL_PG)\n#define BIT_SET_CH7_AVAL_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH7_AVAL_PG(x) | BIT_CH7_AVAL_PG(v))\n\n#define BIT_SHIFT_CH7_RSVD_PG 0\n#define BIT_MASK_CH7_RSVD_PG 0xfff\n#define BIT_CH7_RSVD_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH7_RSVD_PG) << BIT_SHIFT_CH7_RSVD_PG)\n#define BITS_CH7_RSVD_PG (BIT_MASK_CH7_RSVD_PG << BIT_SHIFT_CH7_RSVD_PG)\n#define BIT_CLEAR_CH7_RSVD_PG(x) ((x) & (~BITS_CH7_RSVD_PG))\n#define BIT_GET_CH7_RSVD_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH7_RSVD_PG) & BIT_MASK_CH7_RSVD_PG)\n#define BIT_SET_CH7_RSVD_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH7_RSVD_PG(x) | BIT_CH7_RSVD_PG(v))\n\n/* 2 REG_DMA_RQPN_INFO_8\t\t\t(Offset 0x2220) */\n\n#define BIT_SHIFT_CH8_AVAL_PG 16\n#define BIT_MASK_CH8_AVAL_PG 0xfff\n#define BIT_CH8_AVAL_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH8_AVAL_PG) << BIT_SHIFT_CH8_AVAL_PG)\n#define BITS_CH8_AVAL_PG (BIT_MASK_CH8_AVAL_PG << BIT_SHIFT_CH8_AVAL_PG)\n#define BIT_CLEAR_CH8_AVAL_PG(x) ((x) & (~BITS_CH8_AVAL_PG))\n#define BIT_GET_CH8_AVAL_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH8_AVAL_PG) & BIT_MASK_CH8_AVAL_PG)\n#define BIT_SET_CH8_AVAL_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH8_AVAL_PG(x) | BIT_CH8_AVAL_PG(v))\n\n#define BIT_SHIFT_CH8_RSVD_PG 0\n#define BIT_MASK_CH8_RSVD_PG 0xfff\n#define BIT_CH8_RSVD_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH8_RSVD_PG) << BIT_SHIFT_CH8_RSVD_PG)\n#define BITS_CH8_RSVD_PG (BIT_MASK_CH8_RSVD_PG << BIT_SHIFT_CH8_RSVD_PG)\n#define BIT_CLEAR_CH8_RSVD_PG(x) ((x) & (~BITS_CH8_RSVD_PG))\n#define BIT_GET_CH8_RSVD_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH8_RSVD_PG) & BIT_MASK_CH8_RSVD_PG)\n#define BIT_SET_CH8_RSVD_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH8_RSVD_PG(x) | BIT_CH8_RSVD_PG(v))\n\n/* 2 REG_DMA_RQPN_INFO_9\t\t\t(Offset 0x2224) */\n\n#define BIT_SHIFT_CH9_AVAL_PG 16\n#define BIT_MASK_CH9_AVAL_PG 0xfff\n#define BIT_CH9_AVAL_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH9_AVAL_PG) << BIT_SHIFT_CH9_AVAL_PG)\n#define BITS_CH9_AVAL_PG (BIT_MASK_CH9_AVAL_PG << BIT_SHIFT_CH9_AVAL_PG)\n#define BIT_CLEAR_CH9_AVAL_PG(x) ((x) & (~BITS_CH9_AVAL_PG))\n#define BIT_GET_CH9_AVAL_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH9_AVAL_PG) & BIT_MASK_CH9_AVAL_PG)\n#define BIT_SET_CH9_AVAL_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH9_AVAL_PG(x) | BIT_CH9_AVAL_PG(v))\n\n#define BIT_SHIFT_CH9_RSVD_PG 0\n#define BIT_MASK_CH9_RSVD_PG 0xfff\n#define BIT_CH9_RSVD_PG(x)                                                     \\\n\t(((x) & BIT_MASK_CH9_RSVD_PG) << BIT_SHIFT_CH9_RSVD_PG)\n#define BITS_CH9_RSVD_PG (BIT_MASK_CH9_RSVD_PG << BIT_SHIFT_CH9_RSVD_PG)\n#define BIT_CLEAR_CH9_RSVD_PG(x) ((x) & (~BITS_CH9_RSVD_PG))\n#define BIT_GET_CH9_RSVD_PG(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH9_RSVD_PG) & BIT_MASK_CH9_RSVD_PG)\n#define BIT_SET_CH9_RSVD_PG(x, v)                                              \\\n\t(BIT_CLEAR_CH9_RSVD_PG(x) | BIT_CH9_RSVD_PG(v))\n\n/* 2 REG_DMA_RQPN_INFO_10\t\t\t(Offset 0x2228) */\n\n#define BIT_SHIFT_CH10_AVAL_PG 16\n#define BIT_MASK_CH10_AVAL_PG 0xfff\n#define BIT_CH10_AVAL_PG(x)                                                    \\\n\t(((x) & BIT_MASK_CH10_AVAL_PG) << BIT_SHIFT_CH10_AVAL_PG)\n#define BITS_CH10_AVAL_PG (BIT_MASK_CH10_AVAL_PG << BIT_SHIFT_CH10_AVAL_PG)\n#define BIT_CLEAR_CH10_AVAL_PG(x) ((x) & (~BITS_CH10_AVAL_PG))\n#define BIT_GET_CH10_AVAL_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH10_AVAL_PG) & BIT_MASK_CH10_AVAL_PG)\n#define BIT_SET_CH10_AVAL_PG(x, v)                                             \\\n\t(BIT_CLEAR_CH10_AVAL_PG(x) | BIT_CH10_AVAL_PG(v))\n\n#define BIT_SHIFT_CH10_RSVD_PG 0\n#define BIT_MASK_CH10_RSVD_PG 0xfff\n#define BIT_CH10_RSVD_PG(x)                                                    \\\n\t(((x) & BIT_MASK_CH10_RSVD_PG) << BIT_SHIFT_CH10_RSVD_PG)\n#define BITS_CH10_RSVD_PG (BIT_MASK_CH10_RSVD_PG << BIT_SHIFT_CH10_RSVD_PG)\n#define BIT_CLEAR_CH10_RSVD_PG(x) ((x) & (~BITS_CH10_RSVD_PG))\n#define BIT_GET_CH10_RSVD_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH10_RSVD_PG) & BIT_MASK_CH10_RSVD_PG)\n#define BIT_SET_CH10_RSVD_PG(x, v)                                             \\\n\t(BIT_CLEAR_CH10_RSVD_PG(x) | BIT_CH10_RSVD_PG(v))\n\n/* 2 REG_DMA_RQPN_INFO_11\t\t\t(Offset 0x222C) */\n\n#define BIT_SHIFT_CH11_AVAL_PG 16\n#define BIT_MASK_CH11_AVAL_PG 0xfff\n#define BIT_CH11_AVAL_PG(x)                                                    \\\n\t(((x) & BIT_MASK_CH11_AVAL_PG) << BIT_SHIFT_CH11_AVAL_PG)\n#define BITS_CH11_AVAL_PG (BIT_MASK_CH11_AVAL_PG << BIT_SHIFT_CH11_AVAL_PG)\n#define BIT_CLEAR_CH11_AVAL_PG(x) ((x) & (~BITS_CH11_AVAL_PG))\n#define BIT_GET_CH11_AVAL_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH11_AVAL_PG) & BIT_MASK_CH11_AVAL_PG)\n#define BIT_SET_CH11_AVAL_PG(x, v)                                             \\\n\t(BIT_CLEAR_CH11_AVAL_PG(x) | BIT_CH11_AVAL_PG(v))\n\n#define BIT_SHIFT_CH11_RSVD_PG 0\n#define BIT_MASK_CH11_RSVD_PG 0xfff\n#define BIT_CH11_RSVD_PG(x)                                                    \\\n\t(((x) & BIT_MASK_CH11_RSVD_PG) << BIT_SHIFT_CH11_RSVD_PG)\n#define BITS_CH11_RSVD_PG (BIT_MASK_CH11_RSVD_PG << BIT_SHIFT_CH11_RSVD_PG)\n#define BIT_CLEAR_CH11_RSVD_PG(x) ((x) & (~BITS_CH11_RSVD_PG))\n#define BIT_GET_CH11_RSVD_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH11_RSVD_PG) & BIT_MASK_CH11_RSVD_PG)\n#define BIT_SET_CH11_RSVD_PG(x, v)                                             \\\n\t(BIT_CLEAR_CH11_RSVD_PG(x) | BIT_CH11_RSVD_PG(v))\n\n/* 2 REG_DMA_RQPN_INFO_12\t\t\t(Offset 0x2230) */\n\n#define BIT_SHIFT_CH12_AVAL_PG 16\n#define BIT_MASK_CH12_AVAL_PG 0xfff\n#define BIT_CH12_AVAL_PG(x)                                                    \\\n\t(((x) & BIT_MASK_CH12_AVAL_PG) << BIT_SHIFT_CH12_AVAL_PG)\n#define BITS_CH12_AVAL_PG (BIT_MASK_CH12_AVAL_PG << BIT_SHIFT_CH12_AVAL_PG)\n#define BIT_CLEAR_CH12_AVAL_PG(x) ((x) & (~BITS_CH12_AVAL_PG))\n#define BIT_GET_CH12_AVAL_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH12_AVAL_PG) & BIT_MASK_CH12_AVAL_PG)\n#define BIT_SET_CH12_AVAL_PG(x, v)                                             \\\n\t(BIT_CLEAR_CH12_AVAL_PG(x) | BIT_CH12_AVAL_PG(v))\n\n#define BIT_SHIFT_CH12_RSVD_PG 0\n#define BIT_MASK_CH12_RSVD_PG 0xfff\n#define BIT_CH12_RSVD_PG(x)                                                    \\\n\t(((x) & BIT_MASK_CH12_RSVD_PG) << BIT_SHIFT_CH12_RSVD_PG)\n#define BITS_CH12_RSVD_PG (BIT_MASK_CH12_RSVD_PG << BIT_SHIFT_CH12_RSVD_PG)\n#define BIT_CLEAR_CH12_RSVD_PG(x) ((x) & (~BITS_CH12_RSVD_PG))\n#define BIT_GET_CH12_RSVD_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH12_RSVD_PG) & BIT_MASK_CH12_RSVD_PG)\n#define BIT_SET_CH12_RSVD_PG(x, v)                                             \\\n\t(BIT_CLEAR_CH12_RSVD_PG(x) | BIT_CH12_RSVD_PG(v))\n\n/* 2 REG_DMA_RQPN_INFO_13\t\t\t(Offset 0x2234) */\n\n#define BIT_SHIFT_CH13_AVAL_PG 16\n#define BIT_MASK_CH13_AVAL_PG 0xfff\n#define BIT_CH13_AVAL_PG(x)                                                    \\\n\t(((x) & BIT_MASK_CH13_AVAL_PG) << BIT_SHIFT_CH13_AVAL_PG)\n#define BITS_CH13_AVAL_PG (BIT_MASK_CH13_AVAL_PG << BIT_SHIFT_CH13_AVAL_PG)\n#define BIT_CLEAR_CH13_AVAL_PG(x) ((x) & (~BITS_CH13_AVAL_PG))\n#define BIT_GET_CH13_AVAL_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH13_AVAL_PG) & BIT_MASK_CH13_AVAL_PG)\n#define BIT_SET_CH13_AVAL_PG(x, v)                                             \\\n\t(BIT_CLEAR_CH13_AVAL_PG(x) | BIT_CH13_AVAL_PG(v))\n\n#define BIT_SHIFT_CH13_RSVD_PG 0\n#define BIT_MASK_CH13_RSVD_PG 0xfff\n#define BIT_CH13_RSVD_PG(x)                                                    \\\n\t(((x) & BIT_MASK_CH13_RSVD_PG) << BIT_SHIFT_CH13_RSVD_PG)\n#define BITS_CH13_RSVD_PG (BIT_MASK_CH13_RSVD_PG << BIT_SHIFT_CH13_RSVD_PG)\n#define BIT_CLEAR_CH13_RSVD_PG(x) ((x) & (~BITS_CH13_RSVD_PG))\n#define BIT_GET_CH13_RSVD_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH13_RSVD_PG) & BIT_MASK_CH13_RSVD_PG)\n#define BIT_SET_CH13_RSVD_PG(x, v)                                             \\\n\t(BIT_CLEAR_CH13_RSVD_PG(x) | BIT_CH13_RSVD_PG(v))\n\n/* 2 REG_DMA_RQPN_INFO_14\t\t\t(Offset 0x2238) */\n\n#define BIT_SHIFT_CH14_AVAL_PG 16\n#define BIT_MASK_CH14_AVAL_PG 0xfff\n#define BIT_CH14_AVAL_PG(x)                                                    \\\n\t(((x) & BIT_MASK_CH14_AVAL_PG) << BIT_SHIFT_CH14_AVAL_PG)\n#define BITS_CH14_AVAL_PG (BIT_MASK_CH14_AVAL_PG << BIT_SHIFT_CH14_AVAL_PG)\n#define BIT_CLEAR_CH14_AVAL_PG(x) ((x) & (~BITS_CH14_AVAL_PG))\n#define BIT_GET_CH14_AVAL_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH14_AVAL_PG) & BIT_MASK_CH14_AVAL_PG)\n#define BIT_SET_CH14_AVAL_PG(x, v)                                             \\\n\t(BIT_CLEAR_CH14_AVAL_PG(x) | BIT_CH14_AVAL_PG(v))\n\n#define BIT_SHIFT_CH14_RSVD_PG 0\n#define BIT_MASK_CH14_RSVD_PG 0xfff\n#define BIT_CH14_RSVD_PG(x)                                                    \\\n\t(((x) & BIT_MASK_CH14_RSVD_PG) << BIT_SHIFT_CH14_RSVD_PG)\n#define BITS_CH14_RSVD_PG (BIT_MASK_CH14_RSVD_PG << BIT_SHIFT_CH14_RSVD_PG)\n#define BIT_CLEAR_CH14_RSVD_PG(x) ((x) & (~BITS_CH14_RSVD_PG))\n#define BIT_GET_CH14_RSVD_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH14_RSVD_PG) & BIT_MASK_CH14_RSVD_PG)\n#define BIT_SET_CH14_RSVD_PG(x, v)                                             \\\n\t(BIT_CLEAR_CH14_RSVD_PG(x) | BIT_CH14_RSVD_PG(v))\n\n/* 2 REG_DMA_RQPN_INFO_15\t\t\t(Offset 0x223C) */\n\n#define BIT_SHIFT_CH15_AVAL_PG 16\n#define BIT_MASK_CH15_AVAL_PG 0xfff\n#define BIT_CH15_AVAL_PG(x)                                                    \\\n\t(((x) & BIT_MASK_CH15_AVAL_PG) << BIT_SHIFT_CH15_AVAL_PG)\n#define BITS_CH15_AVAL_PG (BIT_MASK_CH15_AVAL_PG << BIT_SHIFT_CH15_AVAL_PG)\n#define BIT_CLEAR_CH15_AVAL_PG(x) ((x) & (~BITS_CH15_AVAL_PG))\n#define BIT_GET_CH15_AVAL_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH15_AVAL_PG) & BIT_MASK_CH15_AVAL_PG)\n#define BIT_SET_CH15_AVAL_PG(x, v)                                             \\\n\t(BIT_CLEAR_CH15_AVAL_PG(x) | BIT_CH15_AVAL_PG(v))\n\n#define BIT_SHIFT_CH15_RSVD_PG 0\n#define BIT_MASK_CH15_RSVD_PG 0xfff\n#define BIT_CH15_RSVD_PG(x)                                                    \\\n\t(((x) & BIT_MASK_CH15_RSVD_PG) << BIT_SHIFT_CH15_RSVD_PG)\n#define BITS_CH15_RSVD_PG (BIT_MASK_CH15_RSVD_PG << BIT_SHIFT_CH15_RSVD_PG)\n#define BIT_CLEAR_CH15_RSVD_PG(x) ((x) & (~BITS_CH15_RSVD_PG))\n#define BIT_GET_CH15_RSVD_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH15_RSVD_PG) & BIT_MASK_CH15_RSVD_PG)\n#define BIT_SET_CH15_RSVD_PG(x, v)                                             \\\n\t(BIT_CLEAR_CH15_RSVD_PG(x) | BIT_CH15_RSVD_PG(v))\n\n/* 2 REG_DMA_RQPN_INFO_16\t\t\t(Offset 0x2240) */\n\n#define BIT_SHIFT_CH16_AVAL_PG 16\n#define BIT_MASK_CH16_AVAL_PG 0xfff\n#define BIT_CH16_AVAL_PG(x)                                                    \\\n\t(((x) & BIT_MASK_CH16_AVAL_PG) << BIT_SHIFT_CH16_AVAL_PG)\n#define BITS_CH16_AVAL_PG (BIT_MASK_CH16_AVAL_PG << BIT_SHIFT_CH16_AVAL_PG)\n#define BIT_CLEAR_CH16_AVAL_PG(x) ((x) & (~BITS_CH16_AVAL_PG))\n#define BIT_GET_CH16_AVAL_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH16_AVAL_PG) & BIT_MASK_CH16_AVAL_PG)\n#define BIT_SET_CH16_AVAL_PG(x, v)                                             \\\n\t(BIT_CLEAR_CH16_AVAL_PG(x) | BIT_CH16_AVAL_PG(v))\n\n#define BIT_SHIFT_CH16_RSVD_PG 0\n#define BIT_MASK_CH16_RSVD_PG 0xfff\n#define BIT_CH16_RSVD_PG(x)                                                    \\\n\t(((x) & BIT_MASK_CH16_RSVD_PG) << BIT_SHIFT_CH16_RSVD_PG)\n#define BITS_CH16_RSVD_PG (BIT_MASK_CH16_RSVD_PG << BIT_SHIFT_CH16_RSVD_PG)\n#define BIT_CLEAR_CH16_RSVD_PG(x) ((x) & (~BITS_CH16_RSVD_PG))\n#define BIT_GET_CH16_RSVD_PG(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH16_RSVD_PG) & BIT_MASK_CH16_RSVD_PG)\n#define BIT_SET_CH16_RSVD_PG(x, v)                                             \\\n\t(BIT_CLEAR_CH16_RSVD_PG(x) | BIT_CH16_RSVD_PG(v))\n\n/* 2 REG_HWAMSDU_CTL1\t\t\t(Offset 0x2250) */\n\n#define BIT_SHIFT_HWAMSDU_PKTNUM 8\n#define BIT_MASK_HWAMSDU_PKTNUM 0x3f\n#define BIT_HWAMSDU_PKTNUM(x)                                                  \\\n\t(((x) & BIT_MASK_HWAMSDU_PKTNUM) << BIT_SHIFT_HWAMSDU_PKTNUM)\n#define BITS_HWAMSDU_PKTNUM                                                    \\\n\t(BIT_MASK_HWAMSDU_PKTNUM << BIT_SHIFT_HWAMSDU_PKTNUM)\n#define BIT_CLEAR_HWAMSDU_PKTNUM(x) ((x) & (~BITS_HWAMSDU_PKTNUM))\n#define BIT_GET_HWAMSDU_PKTNUM(x)                                              \\\n\t(((x) >> BIT_SHIFT_HWAMSDU_PKTNUM) & BIT_MASK_HWAMSDU_PKTNUM)\n#define BIT_SET_HWAMSDU_PKTNUM(x, v)                                           \\\n\t(BIT_CLEAR_HWAMSDU_PKTNUM(x) | BIT_HWAMSDU_PKTNUM(v))\n\n#define BIT_HWAMSDU_BUSY BIT(7)\n#define BIT_SINGLE_AMSDU BIT(2)\n#define BIT_HWAMSDU_PADDING_MODE BIT(1)\n#define BIT_HWAMSDU_EN BIT(0)\n\n/* 2 REG_HWAMSDU_CTL2\t\t\t(Offset 0x2254) */\n\n#define BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT 16\n#define BIT_MASK_HWAMSDU_AMSDU_TIMEOUT 0xffff\n#define BIT_HWAMSDU_AMSDU_TIMEOUT(x)                                           \\\n\t(((x) & BIT_MASK_HWAMSDU_AMSDU_TIMEOUT)                                \\\n\t << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT)\n#define BITS_HWAMSDU_AMSDU_TIMEOUT                                             \\\n\t(BIT_MASK_HWAMSDU_AMSDU_TIMEOUT << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT)\n#define BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT(x) ((x) & (~BITS_HWAMSDU_AMSDU_TIMEOUT))\n#define BIT_GET_HWAMSDU_AMSDU_TIMEOUT(x)                                       \\\n\t(((x) >> BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT) &                            \\\n\t BIT_MASK_HWAMSDU_AMSDU_TIMEOUT)\n#define BIT_SET_HWAMSDU_AMSDU_TIMEOUT(x, v)                                    \\\n\t(BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT(x) | BIT_HWAMSDU_AMSDU_TIMEOUT(v))\n\n#define BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT 0\n#define BIT_MASK_HWAMSDU_MSDU_TIMEOUT 0xffff\n#define BIT_HWAMSDU_MSDU_TIMEOUT(x)                                            \\\n\t(((x) & BIT_MASK_HWAMSDU_MSDU_TIMEOUT)                                 \\\n\t << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT)\n#define BITS_HWAMSDU_MSDU_TIMEOUT                                              \\\n\t(BIT_MASK_HWAMSDU_MSDU_TIMEOUT << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT)\n#define BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT(x) ((x) & (~BITS_HWAMSDU_MSDU_TIMEOUT))\n#define BIT_GET_HWAMSDU_MSDU_TIMEOUT(x)                                        \\\n\t(((x) >> BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT) &                             \\\n\t BIT_MASK_HWAMSDU_MSDU_TIMEOUT)\n#define BIT_SET_HWAMSDU_MSDU_TIMEOUT(x, v)                                     \\\n\t(BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT(x) | BIT_HWAMSDU_MSDU_TIMEOUT(v))\n\n/* 2 REG_HI8Q_TXBD_DESA_L\t\t\t(Offset 0x2300) */\n\n#define BIT_SHIFT_HI8Q_TXBD_DESA_L 0\n#define BIT_MASK_HI8Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI8Q_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_HI8Q_TXBD_DESA_L) << BIT_SHIFT_HI8Q_TXBD_DESA_L)\n#define BITS_HI8Q_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_HI8Q_TXBD_DESA_L << BIT_SHIFT_HI8Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI8Q_TXBD_DESA_L(x) ((x) & (~BITS_HI8Q_TXBD_DESA_L))\n#define BIT_GET_HI8Q_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_L) & BIT_MASK_HI8Q_TXBD_DESA_L)\n#define BIT_SET_HI8Q_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_HI8Q_TXBD_DESA_L(x) | BIT_HI8Q_TXBD_DESA_L(v))\n\n/* 2 REG_HI8Q_TXBD_DESA_H\t\t\t(Offset 0x2304) */\n\n#define BIT_SHIFT_HI8Q_TXBD_DESA_H 0\n#define BIT_MASK_HI8Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI8Q_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_HI8Q_TXBD_DESA_H) << BIT_SHIFT_HI8Q_TXBD_DESA_H)\n#define BITS_HI8Q_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_HI8Q_TXBD_DESA_H << BIT_SHIFT_HI8Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI8Q_TXBD_DESA_H(x) ((x) & (~BITS_HI8Q_TXBD_DESA_H))\n#define BIT_GET_HI8Q_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_H) & BIT_MASK_HI8Q_TXBD_DESA_H)\n#define BIT_SET_HI8Q_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_HI8Q_TXBD_DESA_H(x) | BIT_HI8Q_TXBD_DESA_H(v))\n\n/* 2 REG_HI9Q_TXBD_DESA_L\t\t\t(Offset 0x2308) */\n\n#define BIT_SHIFT_HI9Q_TXBD_DESA_L 0\n#define BIT_MASK_HI9Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI9Q_TXBD_DESA_L(x)                                                \\\n\t(((x) & BIT_MASK_HI9Q_TXBD_DESA_L) << BIT_SHIFT_HI9Q_TXBD_DESA_L)\n#define BITS_HI9Q_TXBD_DESA_L                                                  \\\n\t(BIT_MASK_HI9Q_TXBD_DESA_L << BIT_SHIFT_HI9Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI9Q_TXBD_DESA_L(x) ((x) & (~BITS_HI9Q_TXBD_DESA_L))\n#define BIT_GET_HI9Q_TXBD_DESA_L(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_L) & BIT_MASK_HI9Q_TXBD_DESA_L)\n#define BIT_SET_HI9Q_TXBD_DESA_L(x, v)                                         \\\n\t(BIT_CLEAR_HI9Q_TXBD_DESA_L(x) | BIT_HI9Q_TXBD_DESA_L(v))\n\n/* 2 REG_HI9Q_TXBD_DESA_H\t\t\t(Offset 0x230C) */\n\n#define BIT_SHIFT_HI9Q_TXBD_DESA_H 0\n#define BIT_MASK_HI9Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI9Q_TXBD_DESA_H(x)                                                \\\n\t(((x) & BIT_MASK_HI9Q_TXBD_DESA_H) << BIT_SHIFT_HI9Q_TXBD_DESA_H)\n#define BITS_HI9Q_TXBD_DESA_H                                                  \\\n\t(BIT_MASK_HI9Q_TXBD_DESA_H << BIT_SHIFT_HI9Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI9Q_TXBD_DESA_H(x) ((x) & (~BITS_HI9Q_TXBD_DESA_H))\n#define BIT_GET_HI9Q_TXBD_DESA_H(x)                                            \\\n\t(((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_H) & BIT_MASK_HI9Q_TXBD_DESA_H)\n#define BIT_SET_HI9Q_TXBD_DESA_H(x, v)                                         \\\n\t(BIT_CLEAR_HI9Q_TXBD_DESA_H(x) | BIT_HI9Q_TXBD_DESA_H(v))\n\n/* 2 REG_HI10Q_TXBD_DESA_L\t\t\t(Offset 0x2310) */\n\n#define BIT_SHIFT_HI10Q_TXBD_DESA_L 0\n#define BIT_MASK_HI10Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI10Q_TXBD_DESA_L(x)                                               \\\n\t(((x) & BIT_MASK_HI10Q_TXBD_DESA_L) << BIT_SHIFT_HI10Q_TXBD_DESA_L)\n#define BITS_HI10Q_TXBD_DESA_L                                                 \\\n\t(BIT_MASK_HI10Q_TXBD_DESA_L << BIT_SHIFT_HI10Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI10Q_TXBD_DESA_L(x) ((x) & (~BITS_HI10Q_TXBD_DESA_L))\n#define BIT_GET_HI10Q_TXBD_DESA_L(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_L) & BIT_MASK_HI10Q_TXBD_DESA_L)\n#define BIT_SET_HI10Q_TXBD_DESA_L(x, v)                                        \\\n\t(BIT_CLEAR_HI10Q_TXBD_DESA_L(x) | BIT_HI10Q_TXBD_DESA_L(v))\n\n/* 2 REG_HI10Q_TXBD_DESA_H\t\t\t(Offset 0x2314) */\n\n#define BIT_SHIFT_HI10Q_TXBD_DESA_H 0\n#define BIT_MASK_HI10Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI10Q_TXBD_DESA_H(x)                                               \\\n\t(((x) & BIT_MASK_HI10Q_TXBD_DESA_H) << BIT_SHIFT_HI10Q_TXBD_DESA_H)\n#define BITS_HI10Q_TXBD_DESA_H                                                 \\\n\t(BIT_MASK_HI10Q_TXBD_DESA_H << BIT_SHIFT_HI10Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI10Q_TXBD_DESA_H(x) ((x) & (~BITS_HI10Q_TXBD_DESA_H))\n#define BIT_GET_HI10Q_TXBD_DESA_H(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_H) & BIT_MASK_HI10Q_TXBD_DESA_H)\n#define BIT_SET_HI10Q_TXBD_DESA_H(x, v)                                        \\\n\t(BIT_CLEAR_HI10Q_TXBD_DESA_H(x) | BIT_HI10Q_TXBD_DESA_H(v))\n\n/* 2 REG_HI11Q_TXBD_DESA_L\t\t\t(Offset 0x2318) */\n\n#define BIT_SHIFT_HI11Q_TXBD_DESA_L 0\n#define BIT_MASK_HI11Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI11Q_TXBD_DESA_L(x)                                               \\\n\t(((x) & BIT_MASK_HI11Q_TXBD_DESA_L) << BIT_SHIFT_HI11Q_TXBD_DESA_L)\n#define BITS_HI11Q_TXBD_DESA_L                                                 \\\n\t(BIT_MASK_HI11Q_TXBD_DESA_L << BIT_SHIFT_HI11Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI11Q_TXBD_DESA_L(x) ((x) & (~BITS_HI11Q_TXBD_DESA_L))\n#define BIT_GET_HI11Q_TXBD_DESA_L(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_L) & BIT_MASK_HI11Q_TXBD_DESA_L)\n#define BIT_SET_HI11Q_TXBD_DESA_L(x, v)                                        \\\n\t(BIT_CLEAR_HI11Q_TXBD_DESA_L(x) | BIT_HI11Q_TXBD_DESA_L(v))\n\n/* 2 REG_HI11Q_TXBD_DESA_H\t\t\t(Offset 0x231C) */\n\n#define BIT_SHIFT_HI11Q_TXBD_DESA_H 0\n#define BIT_MASK_HI11Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI11Q_TXBD_DESA_H(x)                                               \\\n\t(((x) & BIT_MASK_HI11Q_TXBD_DESA_H) << BIT_SHIFT_HI11Q_TXBD_DESA_H)\n#define BITS_HI11Q_TXBD_DESA_H                                                 \\\n\t(BIT_MASK_HI11Q_TXBD_DESA_H << BIT_SHIFT_HI11Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI11Q_TXBD_DESA_H(x) ((x) & (~BITS_HI11Q_TXBD_DESA_H))\n#define BIT_GET_HI11Q_TXBD_DESA_H(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_H) & BIT_MASK_HI11Q_TXBD_DESA_H)\n#define BIT_SET_HI11Q_TXBD_DESA_H(x, v)                                        \\\n\t(BIT_CLEAR_HI11Q_TXBD_DESA_H(x) | BIT_HI11Q_TXBD_DESA_H(v))\n\n/* 2 REG_HI12Q_TXBD_DESA_L\t\t\t(Offset 0x2320) */\n\n#define BIT_SHIFT_HI12Q_TXBD_DESA_L 0\n#define BIT_MASK_HI12Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI12Q_TXBD_DESA_L(x)                                               \\\n\t(((x) & BIT_MASK_HI12Q_TXBD_DESA_L) << BIT_SHIFT_HI12Q_TXBD_DESA_L)\n#define BITS_HI12Q_TXBD_DESA_L                                                 \\\n\t(BIT_MASK_HI12Q_TXBD_DESA_L << BIT_SHIFT_HI12Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI12Q_TXBD_DESA_L(x) ((x) & (~BITS_HI12Q_TXBD_DESA_L))\n#define BIT_GET_HI12Q_TXBD_DESA_L(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_L) & BIT_MASK_HI12Q_TXBD_DESA_L)\n#define BIT_SET_HI12Q_TXBD_DESA_L(x, v)                                        \\\n\t(BIT_CLEAR_HI12Q_TXBD_DESA_L(x) | BIT_HI12Q_TXBD_DESA_L(v))\n\n/* 2 REG_HI12Q_TXBD_DESA_H\t\t\t(Offset 0x2324) */\n\n#define BIT_SHIFT_HI12Q_TXBD_DESA_H 0\n#define BIT_MASK_HI12Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI12Q_TXBD_DESA_H(x)                                               \\\n\t(((x) & BIT_MASK_HI12Q_TXBD_DESA_H) << BIT_SHIFT_HI12Q_TXBD_DESA_H)\n#define BITS_HI12Q_TXBD_DESA_H                                                 \\\n\t(BIT_MASK_HI12Q_TXBD_DESA_H << BIT_SHIFT_HI12Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI12Q_TXBD_DESA_H(x) ((x) & (~BITS_HI12Q_TXBD_DESA_H))\n#define BIT_GET_HI12Q_TXBD_DESA_H(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_H) & BIT_MASK_HI12Q_TXBD_DESA_H)\n#define BIT_SET_HI12Q_TXBD_DESA_H(x, v)                                        \\\n\t(BIT_CLEAR_HI12Q_TXBD_DESA_H(x) | BIT_HI12Q_TXBD_DESA_H(v))\n\n/* 2 REG_HI13Q_TXBD_DESA_L\t\t\t(Offset 0x2328) */\n\n#define BIT_SHIFT_HI13Q_TXBD_DESA_L 0\n#define BIT_MASK_HI13Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI13Q_TXBD_DESA_L(x)                                               \\\n\t(((x) & BIT_MASK_HI13Q_TXBD_DESA_L) << BIT_SHIFT_HI13Q_TXBD_DESA_L)\n#define BITS_HI13Q_TXBD_DESA_L                                                 \\\n\t(BIT_MASK_HI13Q_TXBD_DESA_L << BIT_SHIFT_HI13Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI13Q_TXBD_DESA_L(x) ((x) & (~BITS_HI13Q_TXBD_DESA_L))\n#define BIT_GET_HI13Q_TXBD_DESA_L(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_L) & BIT_MASK_HI13Q_TXBD_DESA_L)\n#define BIT_SET_HI13Q_TXBD_DESA_L(x, v)                                        \\\n\t(BIT_CLEAR_HI13Q_TXBD_DESA_L(x) | BIT_HI13Q_TXBD_DESA_L(v))\n\n/* 2 REG_HI13Q_TXBD_DESA_H\t\t\t(Offset 0x232C) */\n\n#define BIT_SHIFT_HI13Q_TXBD_DESA_H 0\n#define BIT_MASK_HI13Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI13Q_TXBD_DESA_H(x)                                               \\\n\t(((x) & BIT_MASK_HI13Q_TXBD_DESA_H) << BIT_SHIFT_HI13Q_TXBD_DESA_H)\n#define BITS_HI13Q_TXBD_DESA_H                                                 \\\n\t(BIT_MASK_HI13Q_TXBD_DESA_H << BIT_SHIFT_HI13Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI13Q_TXBD_DESA_H(x) ((x) & (~BITS_HI13Q_TXBD_DESA_H))\n#define BIT_GET_HI13Q_TXBD_DESA_H(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_H) & BIT_MASK_HI13Q_TXBD_DESA_H)\n#define BIT_SET_HI13Q_TXBD_DESA_H(x, v)                                        \\\n\t(BIT_CLEAR_HI13Q_TXBD_DESA_H(x) | BIT_HI13Q_TXBD_DESA_H(v))\n\n/* 2 REG_HI14Q_TXBD_DESA_L\t\t\t(Offset 0x2330) */\n\n#define BIT_SHIFT_HI14Q_TXBD_DESA_L 0\n#define BIT_MASK_HI14Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI14Q_TXBD_DESA_L(x)                                               \\\n\t(((x) & BIT_MASK_HI14Q_TXBD_DESA_L) << BIT_SHIFT_HI14Q_TXBD_DESA_L)\n#define BITS_HI14Q_TXBD_DESA_L                                                 \\\n\t(BIT_MASK_HI14Q_TXBD_DESA_L << BIT_SHIFT_HI14Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI14Q_TXBD_DESA_L(x) ((x) & (~BITS_HI14Q_TXBD_DESA_L))\n#define BIT_GET_HI14Q_TXBD_DESA_L(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_L) & BIT_MASK_HI14Q_TXBD_DESA_L)\n#define BIT_SET_HI14Q_TXBD_DESA_L(x, v)                                        \\\n\t(BIT_CLEAR_HI14Q_TXBD_DESA_L(x) | BIT_HI14Q_TXBD_DESA_L(v))\n\n/* 2 REG_HI14Q_TXBD_DESA_H\t\t\t(Offset 0x2334) */\n\n#define BIT_SHIFT_HI14Q_TXBD_DESA_H 0\n#define BIT_MASK_HI14Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI14Q_TXBD_DESA_H(x)                                               \\\n\t(((x) & BIT_MASK_HI14Q_TXBD_DESA_H) << BIT_SHIFT_HI14Q_TXBD_DESA_H)\n#define BITS_HI14Q_TXBD_DESA_H                                                 \\\n\t(BIT_MASK_HI14Q_TXBD_DESA_H << BIT_SHIFT_HI14Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI14Q_TXBD_DESA_H(x) ((x) & (~BITS_HI14Q_TXBD_DESA_H))\n#define BIT_GET_HI14Q_TXBD_DESA_H(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_H) & BIT_MASK_HI14Q_TXBD_DESA_H)\n#define BIT_SET_HI14Q_TXBD_DESA_H(x, v)                                        \\\n\t(BIT_CLEAR_HI14Q_TXBD_DESA_H(x) | BIT_HI14Q_TXBD_DESA_H(v))\n\n/* 2 REG_HI15Q_TXBD_DESA_L\t\t\t(Offset 0x2338) */\n\n#define BIT_SHIFT_HI15Q_TXBD_DESA_L 0\n#define BIT_MASK_HI15Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI15Q_TXBD_DESA_L(x)                                               \\\n\t(((x) & BIT_MASK_HI15Q_TXBD_DESA_L) << BIT_SHIFT_HI15Q_TXBD_DESA_L)\n#define BITS_HI15Q_TXBD_DESA_L                                                 \\\n\t(BIT_MASK_HI15Q_TXBD_DESA_L << BIT_SHIFT_HI15Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI15Q_TXBD_DESA_L(x) ((x) & (~BITS_HI15Q_TXBD_DESA_L))\n#define BIT_GET_HI15Q_TXBD_DESA_L(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_L) & BIT_MASK_HI15Q_TXBD_DESA_L)\n#define BIT_SET_HI15Q_TXBD_DESA_L(x, v)                                        \\\n\t(BIT_CLEAR_HI15Q_TXBD_DESA_L(x) | BIT_HI15Q_TXBD_DESA_L(v))\n\n/* 2 REG_HI15Q_TXBD_DESA_H\t\t\t(Offset 0x233C) */\n\n#define BIT_SHIFT_HI15Q_TXBD_DESA_H 0\n#define BIT_MASK_HI15Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI15Q_TXBD_DESA_H(x)                                               \\\n\t(((x) & BIT_MASK_HI15Q_TXBD_DESA_H) << BIT_SHIFT_HI15Q_TXBD_DESA_H)\n#define BITS_HI15Q_TXBD_DESA_H                                                 \\\n\t(BIT_MASK_HI15Q_TXBD_DESA_H << BIT_SHIFT_HI15Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI15Q_TXBD_DESA_H(x) ((x) & (~BITS_HI15Q_TXBD_DESA_H))\n#define BIT_GET_HI15Q_TXBD_DESA_H(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_H) & BIT_MASK_HI15Q_TXBD_DESA_H)\n#define BIT_SET_HI15Q_TXBD_DESA_H(x, v)                                        \\\n\t(BIT_CLEAR_HI15Q_TXBD_DESA_H(x) | BIT_HI15Q_TXBD_DESA_H(v))\n\n/* 2 REG_HI16Q_TXBD_DESA_L\t\t\t(Offset 0x2340) */\n\n#define BIT_SHIFT_HI16Q_TXBD_DESA_L 0\n#define BIT_MASK_HI16Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI16Q_TXBD_DESA_L(x)                                               \\\n\t(((x) & BIT_MASK_HI16Q_TXBD_DESA_L) << BIT_SHIFT_HI16Q_TXBD_DESA_L)\n#define BITS_HI16Q_TXBD_DESA_L                                                 \\\n\t(BIT_MASK_HI16Q_TXBD_DESA_L << BIT_SHIFT_HI16Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI16Q_TXBD_DESA_L(x) ((x) & (~BITS_HI16Q_TXBD_DESA_L))\n#define BIT_GET_HI16Q_TXBD_DESA_L(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_L) & BIT_MASK_HI16Q_TXBD_DESA_L)\n#define BIT_SET_HI16Q_TXBD_DESA_L(x, v)                                        \\\n\t(BIT_CLEAR_HI16Q_TXBD_DESA_L(x) | BIT_HI16Q_TXBD_DESA_L(v))\n\n/* 2 REG_HI16Q_TXBD_DESA_H\t\t\t(Offset 0x2344) */\n\n#define BIT_SHIFT_HI16Q_TXBD_DESA_H 0\n#define BIT_MASK_HI16Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI16Q_TXBD_DESA_H(x)                                               \\\n\t(((x) & BIT_MASK_HI16Q_TXBD_DESA_H) << BIT_SHIFT_HI16Q_TXBD_DESA_H)\n#define BITS_HI16Q_TXBD_DESA_H                                                 \\\n\t(BIT_MASK_HI16Q_TXBD_DESA_H << BIT_SHIFT_HI16Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI16Q_TXBD_DESA_H(x) ((x) & (~BITS_HI16Q_TXBD_DESA_H))\n#define BIT_GET_HI16Q_TXBD_DESA_H(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_H) & BIT_MASK_HI16Q_TXBD_DESA_H)\n#define BIT_SET_HI16Q_TXBD_DESA_H(x, v)                                        \\\n\t(BIT_CLEAR_HI16Q_TXBD_DESA_H(x) | BIT_HI16Q_TXBD_DESA_H(v))\n\n/* 2 REG_HI17Q_TXBD_DESA_L\t\t\t(Offset 0x2348) */\n\n#define BIT_SHIFT_HI17Q_TXBD_DESA_L 0\n#define BIT_MASK_HI17Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI17Q_TXBD_DESA_L(x)                                               \\\n\t(((x) & BIT_MASK_HI17Q_TXBD_DESA_L) << BIT_SHIFT_HI17Q_TXBD_DESA_L)\n#define BITS_HI17Q_TXBD_DESA_L                                                 \\\n\t(BIT_MASK_HI17Q_TXBD_DESA_L << BIT_SHIFT_HI17Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI17Q_TXBD_DESA_L(x) ((x) & (~BITS_HI17Q_TXBD_DESA_L))\n#define BIT_GET_HI17Q_TXBD_DESA_L(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_L) & BIT_MASK_HI17Q_TXBD_DESA_L)\n#define BIT_SET_HI17Q_TXBD_DESA_L(x, v)                                        \\\n\t(BIT_CLEAR_HI17Q_TXBD_DESA_L(x) | BIT_HI17Q_TXBD_DESA_L(v))\n\n/* 2 REG_HI17Q_TXBD_DESA_H\t\t\t(Offset 0x234C) */\n\n#define BIT_SHIFT_HI17Q_TXBD_DESA_H 0\n#define BIT_MASK_HI17Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI17Q_TXBD_DESA_H(x)                                               \\\n\t(((x) & BIT_MASK_HI17Q_TXBD_DESA_H) << BIT_SHIFT_HI17Q_TXBD_DESA_H)\n#define BITS_HI17Q_TXBD_DESA_H                                                 \\\n\t(BIT_MASK_HI17Q_TXBD_DESA_H << BIT_SHIFT_HI17Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI17Q_TXBD_DESA_H(x) ((x) & (~BITS_HI17Q_TXBD_DESA_H))\n#define BIT_GET_HI17Q_TXBD_DESA_H(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_H) & BIT_MASK_HI17Q_TXBD_DESA_H)\n#define BIT_SET_HI17Q_TXBD_DESA_H(x, v)                                        \\\n\t(BIT_CLEAR_HI17Q_TXBD_DESA_H(x) | BIT_HI17Q_TXBD_DESA_H(v))\n\n/* 2 REG_HI18Q_TXBD_DESA_L\t\t\t(Offset 0x2350) */\n\n#define BIT_SHIFT_HI18Q_TXBD_DESA_L 0\n#define BIT_MASK_HI18Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI18Q_TXBD_DESA_L(x)                                               \\\n\t(((x) & BIT_MASK_HI18Q_TXBD_DESA_L) << BIT_SHIFT_HI18Q_TXBD_DESA_L)\n#define BITS_HI18Q_TXBD_DESA_L                                                 \\\n\t(BIT_MASK_HI18Q_TXBD_DESA_L << BIT_SHIFT_HI18Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI18Q_TXBD_DESA_L(x) ((x) & (~BITS_HI18Q_TXBD_DESA_L))\n#define BIT_GET_HI18Q_TXBD_DESA_L(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_L) & BIT_MASK_HI18Q_TXBD_DESA_L)\n#define BIT_SET_HI18Q_TXBD_DESA_L(x, v)                                        \\\n\t(BIT_CLEAR_HI18Q_TXBD_DESA_L(x) | BIT_HI18Q_TXBD_DESA_L(v))\n\n/* 2 REG_HI18Q_TXBD_DESA_H\t\t\t(Offset 0x2354) */\n\n#define BIT_SHIFT_HI18Q_TXBD_DESA_H 0\n#define BIT_MASK_HI18Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI18Q_TXBD_DESA_H(x)                                               \\\n\t(((x) & BIT_MASK_HI18Q_TXBD_DESA_H) << BIT_SHIFT_HI18Q_TXBD_DESA_H)\n#define BITS_HI18Q_TXBD_DESA_H                                                 \\\n\t(BIT_MASK_HI18Q_TXBD_DESA_H << BIT_SHIFT_HI18Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI18Q_TXBD_DESA_H(x) ((x) & (~BITS_HI18Q_TXBD_DESA_H))\n#define BIT_GET_HI18Q_TXBD_DESA_H(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_H) & BIT_MASK_HI18Q_TXBD_DESA_H)\n#define BIT_SET_HI18Q_TXBD_DESA_H(x, v)                                        \\\n\t(BIT_CLEAR_HI18Q_TXBD_DESA_H(x) | BIT_HI18Q_TXBD_DESA_H(v))\n\n/* 2 REG_HI19Q_TXBD_DESA_L\t\t\t(Offset 0x2358) */\n\n#define BIT_SHIFT_HI19Q_TXBD_DESA_L 0\n#define BIT_MASK_HI19Q_TXBD_DESA_L 0xffffffffL\n#define BIT_HI19Q_TXBD_DESA_L(x)                                               \\\n\t(((x) & BIT_MASK_HI19Q_TXBD_DESA_L) << BIT_SHIFT_HI19Q_TXBD_DESA_L)\n#define BITS_HI19Q_TXBD_DESA_L                                                 \\\n\t(BIT_MASK_HI19Q_TXBD_DESA_L << BIT_SHIFT_HI19Q_TXBD_DESA_L)\n#define BIT_CLEAR_HI19Q_TXBD_DESA_L(x) ((x) & (~BITS_HI19Q_TXBD_DESA_L))\n#define BIT_GET_HI19Q_TXBD_DESA_L(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_L) & BIT_MASK_HI19Q_TXBD_DESA_L)\n#define BIT_SET_HI19Q_TXBD_DESA_L(x, v)                                        \\\n\t(BIT_CLEAR_HI19Q_TXBD_DESA_L(x) | BIT_HI19Q_TXBD_DESA_L(v))\n\n/* 2 REG_HI19Q_TXBD_DESA_H\t\t\t(Offset 0x235C) */\n\n#define BIT_CLR_P0HI19Q_HW_IDX BIT(25)\n#define BIT_CLR_P0HI18Q_HW_IDX BIT(24)\n#define BIT_CLR_P0HI17Q_HW_IDX BIT(23)\n#define BIT_CLR_P0HI16Q_HW_IDX BIT(22)\n#define BIT_CLR_P0HI19Q_HOST_IDX BIT(9)\n#define BIT_CLR_P0HI18Q_HOST_IDX BIT(8)\n#define BIT_CLR_P0HI17Q_HOST_IDX BIT(7)\n#define BIT_CLR_P0HI16Q_HOST_IDX BIT(6)\n\n#define BIT_SHIFT_HI19Q_TXBD_DESA_H 0\n#define BIT_MASK_HI19Q_TXBD_DESA_H 0xffffffffL\n#define BIT_HI19Q_TXBD_DESA_H(x)                                               \\\n\t(((x) & BIT_MASK_HI19Q_TXBD_DESA_H) << BIT_SHIFT_HI19Q_TXBD_DESA_H)\n#define BITS_HI19Q_TXBD_DESA_H                                                 \\\n\t(BIT_MASK_HI19Q_TXBD_DESA_H << BIT_SHIFT_HI19Q_TXBD_DESA_H)\n#define BIT_CLEAR_HI19Q_TXBD_DESA_H(x) ((x) & (~BITS_HI19Q_TXBD_DESA_H))\n#define BIT_GET_HI19Q_TXBD_DESA_H(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_H) & BIT_MASK_HI19Q_TXBD_DESA_H)\n#define BIT_SET_HI19Q_TXBD_DESA_H(x, v)                                        \\\n\t(BIT_CLEAR_HI19Q_TXBD_DESA_H(x) | BIT_HI19Q_TXBD_DESA_H(v))\n\n/* 2 REG_P0HI16Q_TXBD_IDX\t\t\t(Offset 0x2370) */\n\n#define BIT_SHIFT_P0HI16Q_HW_IDX 16\n#define BIT_MASK_P0HI16Q_HW_IDX 0xfff\n#define BIT_P0HI16Q_HW_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_P0HI16Q_HW_IDX) << BIT_SHIFT_P0HI16Q_HW_IDX)\n#define BITS_P0HI16Q_HW_IDX                                                    \\\n\t(BIT_MASK_P0HI16Q_HW_IDX << BIT_SHIFT_P0HI16Q_HW_IDX)\n#define BIT_CLEAR_P0HI16Q_HW_IDX(x) ((x) & (~BITS_P0HI16Q_HW_IDX))\n#define BIT_GET_P0HI16Q_HW_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_P0HI16Q_HW_IDX) & BIT_MASK_P0HI16Q_HW_IDX)\n#define BIT_SET_P0HI16Q_HW_IDX(x, v)                                           \\\n\t(BIT_CLEAR_P0HI16Q_HW_IDX(x) | BIT_P0HI16Q_HW_IDX(v))\n\n#define BIT_SHIFT_P0HI16Q_HOST_IDX 0\n#define BIT_MASK_P0HI16Q_HOST_IDX 0xfff\n#define BIT_P0HI16Q_HOST_IDX(x)                                                \\\n\t(((x) & BIT_MASK_P0HI16Q_HOST_IDX) << BIT_SHIFT_P0HI16Q_HOST_IDX)\n#define BITS_P0HI16Q_HOST_IDX                                                  \\\n\t(BIT_MASK_P0HI16Q_HOST_IDX << BIT_SHIFT_P0HI16Q_HOST_IDX)\n#define BIT_CLEAR_P0HI16Q_HOST_IDX(x) ((x) & (~BITS_P0HI16Q_HOST_IDX))\n#define BIT_GET_P0HI16Q_HOST_IDX(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI16Q_HOST_IDX) & BIT_MASK_P0HI16Q_HOST_IDX)\n#define BIT_SET_P0HI16Q_HOST_IDX(x, v)                                         \\\n\t(BIT_CLEAR_P0HI16Q_HOST_IDX(x) | BIT_P0HI16Q_HOST_IDX(v))\n\n/* 2 REG_P0HI17Q_TXBD_IDX\t\t\t(Offset 0x2374) */\n\n#define BIT_SHIFT_P0HI17Q_HW_IDX 16\n#define BIT_MASK_P0HI17Q_HW_IDX 0xfff\n#define BIT_P0HI17Q_HW_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_P0HI17Q_HW_IDX) << BIT_SHIFT_P0HI17Q_HW_IDX)\n#define BITS_P0HI17Q_HW_IDX                                                    \\\n\t(BIT_MASK_P0HI17Q_HW_IDX << BIT_SHIFT_P0HI17Q_HW_IDX)\n#define BIT_CLEAR_P0HI17Q_HW_IDX(x) ((x) & (~BITS_P0HI17Q_HW_IDX))\n#define BIT_GET_P0HI17Q_HW_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_P0HI17Q_HW_IDX) & BIT_MASK_P0HI17Q_HW_IDX)\n#define BIT_SET_P0HI17Q_HW_IDX(x, v)                                           \\\n\t(BIT_CLEAR_P0HI17Q_HW_IDX(x) | BIT_P0HI17Q_HW_IDX(v))\n\n#define BIT_SHIFT_P0HI17Q_HOST_IDX 0\n#define BIT_MASK_P0HI17Q_HOST_IDX 0xfff\n#define BIT_P0HI17Q_HOST_IDX(x)                                                \\\n\t(((x) & BIT_MASK_P0HI17Q_HOST_IDX) << BIT_SHIFT_P0HI17Q_HOST_IDX)\n#define BITS_P0HI17Q_HOST_IDX                                                  \\\n\t(BIT_MASK_P0HI17Q_HOST_IDX << BIT_SHIFT_P0HI17Q_HOST_IDX)\n#define BIT_CLEAR_P0HI17Q_HOST_IDX(x) ((x) & (~BITS_P0HI17Q_HOST_IDX))\n#define BIT_GET_P0HI17Q_HOST_IDX(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI17Q_HOST_IDX) & BIT_MASK_P0HI17Q_HOST_IDX)\n#define BIT_SET_P0HI17Q_HOST_IDX(x, v)                                         \\\n\t(BIT_CLEAR_P0HI17Q_HOST_IDX(x) | BIT_P0HI17Q_HOST_IDX(v))\n\n/* 2 REG_P0HI18Q_TXBD_IDX\t\t\t(Offset 0x2378) */\n\n#define BIT_SHIFT_P0HI18Q_HW_IDX 16\n#define BIT_MASK_P0HI18Q_HW_IDX 0xfff\n#define BIT_P0HI18Q_HW_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_P0HI18Q_HW_IDX) << BIT_SHIFT_P0HI18Q_HW_IDX)\n#define BITS_P0HI18Q_HW_IDX                                                    \\\n\t(BIT_MASK_P0HI18Q_HW_IDX << BIT_SHIFT_P0HI18Q_HW_IDX)\n#define BIT_CLEAR_P0HI18Q_HW_IDX(x) ((x) & (~BITS_P0HI18Q_HW_IDX))\n#define BIT_GET_P0HI18Q_HW_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_P0HI18Q_HW_IDX) & BIT_MASK_P0HI18Q_HW_IDX)\n#define BIT_SET_P0HI18Q_HW_IDX(x, v)                                           \\\n\t(BIT_CLEAR_P0HI18Q_HW_IDX(x) | BIT_P0HI18Q_HW_IDX(v))\n\n#define BIT_SHIFT_P0HI18Q_HOST_IDX 0\n#define BIT_MASK_P0HI18Q_HOST_IDX 0xfff\n#define BIT_P0HI18Q_HOST_IDX(x)                                                \\\n\t(((x) & BIT_MASK_P0HI18Q_HOST_IDX) << BIT_SHIFT_P0HI18Q_HOST_IDX)\n#define BITS_P0HI18Q_HOST_IDX                                                  \\\n\t(BIT_MASK_P0HI18Q_HOST_IDX << BIT_SHIFT_P0HI18Q_HOST_IDX)\n#define BIT_CLEAR_P0HI18Q_HOST_IDX(x) ((x) & (~BITS_P0HI18Q_HOST_IDX))\n#define BIT_GET_P0HI18Q_HOST_IDX(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI18Q_HOST_IDX) & BIT_MASK_P0HI18Q_HOST_IDX)\n#define BIT_SET_P0HI18Q_HOST_IDX(x, v)                                         \\\n\t(BIT_CLEAR_P0HI18Q_HOST_IDX(x) | BIT_P0HI18Q_HOST_IDX(v))\n\n/* 2 REG_P0HI19Q_TXBD_IDX\t\t\t(Offset 0x237C) */\n\n#define BIT_SHIFT_P0HI19Q_HW_IDX 16\n#define BIT_MASK_P0HI19Q_HW_IDX 0xfff\n#define BIT_P0HI19Q_HW_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_P0HI19Q_HW_IDX) << BIT_SHIFT_P0HI19Q_HW_IDX)\n#define BITS_P0HI19Q_HW_IDX                                                    \\\n\t(BIT_MASK_P0HI19Q_HW_IDX << BIT_SHIFT_P0HI19Q_HW_IDX)\n#define BIT_CLEAR_P0HI19Q_HW_IDX(x) ((x) & (~BITS_P0HI19Q_HW_IDX))\n#define BIT_GET_P0HI19Q_HW_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_P0HI19Q_HW_IDX) & BIT_MASK_P0HI19Q_HW_IDX)\n#define BIT_SET_P0HI19Q_HW_IDX(x, v)                                           \\\n\t(BIT_CLEAR_P0HI19Q_HW_IDX(x) | BIT_P0HI19Q_HW_IDX(v))\n\n#define BIT_SHIFT_P0HI19Q_HOST_IDX 0\n#define BIT_MASK_P0HI19Q_HOST_IDX 0xfff\n#define BIT_P0HI19Q_HOST_IDX(x)                                                \\\n\t(((x) & BIT_MASK_P0HI19Q_HOST_IDX) << BIT_SHIFT_P0HI19Q_HOST_IDX)\n#define BITS_P0HI19Q_HOST_IDX                                                  \\\n\t(BIT_MASK_P0HI19Q_HOST_IDX << BIT_SHIFT_P0HI19Q_HOST_IDX)\n#define BIT_CLEAR_P0HI19Q_HOST_IDX(x) ((x) & (~BITS_P0HI19Q_HOST_IDX))\n#define BIT_GET_P0HI19Q_HOST_IDX(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI19Q_HOST_IDX) & BIT_MASK_P0HI19Q_HOST_IDX)\n#define BIT_SET_P0HI19Q_HOST_IDX(x, v)                                         \\\n\t(BIT_CLEAR_P0HI19Q_HOST_IDX(x) | BIT_P0HI19Q_HOST_IDX(v))\n\n/* 2 REG_P0HI16Q_HI17Q_TXBD_NUM\t\t(Offset 0x2380) */\n\n#define BIT_P0HI17Q_FLAG BIT(30)\n\n#define BIT_SHIFT_P0HI17Q_DESC_MODE 28\n#define BIT_MASK_P0HI17Q_DESC_MODE 0x3\n#define BIT_P0HI17Q_DESC_MODE(x)                                               \\\n\t(((x) & BIT_MASK_P0HI17Q_DESC_MODE) << BIT_SHIFT_P0HI17Q_DESC_MODE)\n#define BITS_P0HI17Q_DESC_MODE                                                 \\\n\t(BIT_MASK_P0HI17Q_DESC_MODE << BIT_SHIFT_P0HI17Q_DESC_MODE)\n#define BIT_CLEAR_P0HI17Q_DESC_MODE(x) ((x) & (~BITS_P0HI17Q_DESC_MODE))\n#define BIT_GET_P0HI17Q_DESC_MODE(x)                                           \\\n\t(((x) >> BIT_SHIFT_P0HI17Q_DESC_MODE) & BIT_MASK_P0HI17Q_DESC_MODE)\n#define BIT_SET_P0HI17Q_DESC_MODE(x, v)                                        \\\n\t(BIT_CLEAR_P0HI17Q_DESC_MODE(x) | BIT_P0HI17Q_DESC_MODE(v))\n\n#define BIT_SHIFT_P0HI17Q_DESC_NUM 16\n#define BIT_MASK_P0HI17Q_DESC_NUM 0xfff\n#define BIT_P0HI17Q_DESC_NUM(x)                                                \\\n\t(((x) & BIT_MASK_P0HI17Q_DESC_NUM) << BIT_SHIFT_P0HI17Q_DESC_NUM)\n#define BITS_P0HI17Q_DESC_NUM                                                  \\\n\t(BIT_MASK_P0HI17Q_DESC_NUM << BIT_SHIFT_P0HI17Q_DESC_NUM)\n#define BIT_CLEAR_P0HI17Q_DESC_NUM(x) ((x) & (~BITS_P0HI17Q_DESC_NUM))\n#define BIT_GET_P0HI17Q_DESC_NUM(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI17Q_DESC_NUM) & BIT_MASK_P0HI17Q_DESC_NUM)\n#define BIT_SET_P0HI17Q_DESC_NUM(x, v)                                         \\\n\t(BIT_CLEAR_P0HI17Q_DESC_NUM(x) | BIT_P0HI17Q_DESC_NUM(v))\n\n#define BIT_P0HI16Q_FLAG BIT(14)\n\n#define BIT_SHIFT_P0HI16Q_DESC_MODE 12\n#define BIT_MASK_P0HI16Q_DESC_MODE 0x3\n#define BIT_P0HI16Q_DESC_MODE(x)                                               \\\n\t(((x) & BIT_MASK_P0HI16Q_DESC_MODE) << BIT_SHIFT_P0HI16Q_DESC_MODE)\n#define BITS_P0HI16Q_DESC_MODE                                                 \\\n\t(BIT_MASK_P0HI16Q_DESC_MODE << BIT_SHIFT_P0HI16Q_DESC_MODE)\n#define BIT_CLEAR_P0HI16Q_DESC_MODE(x) ((x) & (~BITS_P0HI16Q_DESC_MODE))\n#define BIT_GET_P0HI16Q_DESC_MODE(x)                                           \\\n\t(((x) >> BIT_SHIFT_P0HI16Q_DESC_MODE) & BIT_MASK_P0HI16Q_DESC_MODE)\n#define BIT_SET_P0HI16Q_DESC_MODE(x, v)                                        \\\n\t(BIT_CLEAR_P0HI16Q_DESC_MODE(x) | BIT_P0HI16Q_DESC_MODE(v))\n\n#define BIT_SHIFT_P0HI16Q_DESC_NUM 0\n#define BIT_MASK_P0HI16Q_DESC_NUM 0xfff\n#define BIT_P0HI16Q_DESC_NUM(x)                                                \\\n\t(((x) & BIT_MASK_P0HI16Q_DESC_NUM) << BIT_SHIFT_P0HI16Q_DESC_NUM)\n#define BITS_P0HI16Q_DESC_NUM                                                  \\\n\t(BIT_MASK_P0HI16Q_DESC_NUM << BIT_SHIFT_P0HI16Q_DESC_NUM)\n#define BIT_CLEAR_P0HI16Q_DESC_NUM(x) ((x) & (~BITS_P0HI16Q_DESC_NUM))\n#define BIT_GET_P0HI16Q_DESC_NUM(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI16Q_DESC_NUM) & BIT_MASK_P0HI16Q_DESC_NUM)\n#define BIT_SET_P0HI16Q_DESC_NUM(x, v)                                         \\\n\t(BIT_CLEAR_P0HI16Q_DESC_NUM(x) | BIT_P0HI16Q_DESC_NUM(v))\n\n/* 2 REG_P0HI18Q_HI19Q_TXBD_NUM\t\t(Offset 0x2384) */\n\n#define BIT_P0HI19Q_FLAG BIT(30)\n\n#define BIT_SHIFT_P0HI19Q_DESC_MODE 28\n#define BIT_MASK_P0HI19Q_DESC_MODE 0x3\n#define BIT_P0HI19Q_DESC_MODE(x)                                               \\\n\t(((x) & BIT_MASK_P0HI19Q_DESC_MODE) << BIT_SHIFT_P0HI19Q_DESC_MODE)\n#define BITS_P0HI19Q_DESC_MODE                                                 \\\n\t(BIT_MASK_P0HI19Q_DESC_MODE << BIT_SHIFT_P0HI19Q_DESC_MODE)\n#define BIT_CLEAR_P0HI19Q_DESC_MODE(x) ((x) & (~BITS_P0HI19Q_DESC_MODE))\n#define BIT_GET_P0HI19Q_DESC_MODE(x)                                           \\\n\t(((x) >> BIT_SHIFT_P0HI19Q_DESC_MODE) & BIT_MASK_P0HI19Q_DESC_MODE)\n#define BIT_SET_P0HI19Q_DESC_MODE(x, v)                                        \\\n\t(BIT_CLEAR_P0HI19Q_DESC_MODE(x) | BIT_P0HI19Q_DESC_MODE(v))\n\n#define BIT_SHIFT_P0HI19Q_DESC_NUM 16\n#define BIT_MASK_P0HI19Q_DESC_NUM 0xfff\n#define BIT_P0HI19Q_DESC_NUM(x)                                                \\\n\t(((x) & BIT_MASK_P0HI19Q_DESC_NUM) << BIT_SHIFT_P0HI19Q_DESC_NUM)\n#define BITS_P0HI19Q_DESC_NUM                                                  \\\n\t(BIT_MASK_P0HI19Q_DESC_NUM << BIT_SHIFT_P0HI19Q_DESC_NUM)\n#define BIT_CLEAR_P0HI19Q_DESC_NUM(x) ((x) & (~BITS_P0HI19Q_DESC_NUM))\n#define BIT_GET_P0HI19Q_DESC_NUM(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI19Q_DESC_NUM) & BIT_MASK_P0HI19Q_DESC_NUM)\n#define BIT_SET_P0HI19Q_DESC_NUM(x, v)                                         \\\n\t(BIT_CLEAR_P0HI19Q_DESC_NUM(x) | BIT_P0HI19Q_DESC_NUM(v))\n\n#define BIT_P0HI18Q_FLAG BIT(14)\n\n#define BIT_SHIFT_P0HI18Q_DESC_MODE 12\n#define BIT_MASK_P0HI18Q_DESC_MODE 0x3\n#define BIT_P0HI18Q_DESC_MODE(x)                                               \\\n\t(((x) & BIT_MASK_P0HI18Q_DESC_MODE) << BIT_SHIFT_P0HI18Q_DESC_MODE)\n#define BITS_P0HI18Q_DESC_MODE                                                 \\\n\t(BIT_MASK_P0HI18Q_DESC_MODE << BIT_SHIFT_P0HI18Q_DESC_MODE)\n#define BIT_CLEAR_P0HI18Q_DESC_MODE(x) ((x) & (~BITS_P0HI18Q_DESC_MODE))\n#define BIT_GET_P0HI18Q_DESC_MODE(x)                                           \\\n\t(((x) >> BIT_SHIFT_P0HI18Q_DESC_MODE) & BIT_MASK_P0HI18Q_DESC_MODE)\n#define BIT_SET_P0HI18Q_DESC_MODE(x, v)                                        \\\n\t(BIT_CLEAR_P0HI18Q_DESC_MODE(x) | BIT_P0HI18Q_DESC_MODE(v))\n\n#define BIT_SHIFT_P0HI18Q_DESC_NUM 0\n#define BIT_MASK_P0HI18Q_DESC_NUM 0xfff\n#define BIT_P0HI18Q_DESC_NUM(x)                                                \\\n\t(((x) & BIT_MASK_P0HI18Q_DESC_NUM) << BIT_SHIFT_P0HI18Q_DESC_NUM)\n#define BITS_P0HI18Q_DESC_NUM                                                  \\\n\t(BIT_MASK_P0HI18Q_DESC_NUM << BIT_SHIFT_P0HI18Q_DESC_NUM)\n#define BIT_CLEAR_P0HI18Q_DESC_NUM(x) ((x) & (~BITS_P0HI18Q_DESC_NUM))\n#define BIT_GET_P0HI18Q_DESC_NUM(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI18Q_DESC_NUM) & BIT_MASK_P0HI18Q_DESC_NUM)\n#define BIT_SET_P0HI18Q_DESC_NUM(x, v)                                         \\\n\t(BIT_CLEAR_P0HI18Q_DESC_NUM(x) | BIT_P0HI18Q_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_PCIE_HISR1\t\t\t\t(Offset 0x23BC) */\n\n#define BIT_CPU_MGQ_EARLY_INT BIT(6)\n#define BIT_PSTIMER_5 BIT(4)\n#define BIT_PSTIMER_4 BIT(3)\n#define BIT_PSTIMER_3 BIT(2)\n#define BIT_BB_STOPRX_INT BIT(0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_P0HI8Q_HI9Q_TXBD_NUM\t\t(Offset 0x23C0) */\n\n#define BIT_P0HI9Q_FLAG BIT(30)\n\n#define BIT_SHIFT_P0HI9Q_DESC_MODE 28\n#define BIT_MASK_P0HI9Q_DESC_MODE 0x3\n#define BIT_P0HI9Q_DESC_MODE(x)                                                \\\n\t(((x) & BIT_MASK_P0HI9Q_DESC_MODE) << BIT_SHIFT_P0HI9Q_DESC_MODE)\n#define BITS_P0HI9Q_DESC_MODE                                                  \\\n\t(BIT_MASK_P0HI9Q_DESC_MODE << BIT_SHIFT_P0HI9Q_DESC_MODE)\n#define BIT_CLEAR_P0HI9Q_DESC_MODE(x) ((x) & (~BITS_P0HI9Q_DESC_MODE))\n#define BIT_GET_P0HI9Q_DESC_MODE(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI9Q_DESC_MODE) & BIT_MASK_P0HI9Q_DESC_MODE)\n#define BIT_SET_P0HI9Q_DESC_MODE(x, v)                                         \\\n\t(BIT_CLEAR_P0HI9Q_DESC_MODE(x) | BIT_P0HI9Q_DESC_MODE(v))\n\n#define BIT_SHIFT_P0HI9Q_DESC_NUM 16\n#define BIT_MASK_P0HI9Q_DESC_NUM 0xfff\n#define BIT_P0HI9Q_DESC_NUM(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI9Q_DESC_NUM) << BIT_SHIFT_P0HI9Q_DESC_NUM)\n#define BITS_P0HI9Q_DESC_NUM                                                   \\\n\t(BIT_MASK_P0HI9Q_DESC_NUM << BIT_SHIFT_P0HI9Q_DESC_NUM)\n#define BIT_CLEAR_P0HI9Q_DESC_NUM(x) ((x) & (~BITS_P0HI9Q_DESC_NUM))\n#define BIT_GET_P0HI9Q_DESC_NUM(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI9Q_DESC_NUM) & BIT_MASK_P0HI9Q_DESC_NUM)\n#define BIT_SET_P0HI9Q_DESC_NUM(x, v)                                          \\\n\t(BIT_CLEAR_P0HI9Q_DESC_NUM(x) | BIT_P0HI9Q_DESC_NUM(v))\n\n#define BIT_P0HI8Q_FLAG BIT(14)\n\n#define BIT_SHIFT_P0HI8Q_DESC_MODE 12\n#define BIT_MASK_P0HI8Q_DESC_MODE 0x3\n#define BIT_P0HI8Q_DESC_MODE(x)                                                \\\n\t(((x) & BIT_MASK_P0HI8Q_DESC_MODE) << BIT_SHIFT_P0HI8Q_DESC_MODE)\n#define BITS_P0HI8Q_DESC_MODE                                                  \\\n\t(BIT_MASK_P0HI8Q_DESC_MODE << BIT_SHIFT_P0HI8Q_DESC_MODE)\n#define BIT_CLEAR_P0HI8Q_DESC_MODE(x) ((x) & (~BITS_P0HI8Q_DESC_MODE))\n#define BIT_GET_P0HI8Q_DESC_MODE(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI8Q_DESC_MODE) & BIT_MASK_P0HI8Q_DESC_MODE)\n#define BIT_SET_P0HI8Q_DESC_MODE(x, v)                                         \\\n\t(BIT_CLEAR_P0HI8Q_DESC_MODE(x) | BIT_P0HI8Q_DESC_MODE(v))\n\n#define BIT_SHIFT_P0HI8Q_DESC_NUM 0\n#define BIT_MASK_P0HI8Q_DESC_NUM 0xfff\n#define BIT_P0HI8Q_DESC_NUM(x)                                                 \\\n\t(((x) & BIT_MASK_P0HI8Q_DESC_NUM) << BIT_SHIFT_P0HI8Q_DESC_NUM)\n#define BITS_P0HI8Q_DESC_NUM                                                   \\\n\t(BIT_MASK_P0HI8Q_DESC_NUM << BIT_SHIFT_P0HI8Q_DESC_NUM)\n#define BIT_CLEAR_P0HI8Q_DESC_NUM(x) ((x) & (~BITS_P0HI8Q_DESC_NUM))\n#define BIT_GET_P0HI8Q_DESC_NUM(x)                                             \\\n\t(((x) >> BIT_SHIFT_P0HI8Q_DESC_NUM) & BIT_MASK_P0HI8Q_DESC_NUM)\n#define BIT_SET_P0HI8Q_DESC_NUM(x, v)                                          \\\n\t(BIT_CLEAR_P0HI8Q_DESC_NUM(x) | BIT_P0HI8Q_DESC_NUM(v))\n\n/* 2 REG_P0HI10Q_HI11Q_TXBD_NUM\t\t(Offset 0x23C4) */\n\n#define BIT_P0HI11Q_FLAG BIT(30)\n\n#define BIT_SHIFT_P0HI11Q_DESC_MODE 28\n#define BIT_MASK_P0HI11Q_DESC_MODE 0x3\n#define BIT_P0HI11Q_DESC_MODE(x)                                               \\\n\t(((x) & BIT_MASK_P0HI11Q_DESC_MODE) << BIT_SHIFT_P0HI11Q_DESC_MODE)\n#define BITS_P0HI11Q_DESC_MODE                                                 \\\n\t(BIT_MASK_P0HI11Q_DESC_MODE << BIT_SHIFT_P0HI11Q_DESC_MODE)\n#define BIT_CLEAR_P0HI11Q_DESC_MODE(x) ((x) & (~BITS_P0HI11Q_DESC_MODE))\n#define BIT_GET_P0HI11Q_DESC_MODE(x)                                           \\\n\t(((x) >> BIT_SHIFT_P0HI11Q_DESC_MODE) & BIT_MASK_P0HI11Q_DESC_MODE)\n#define BIT_SET_P0HI11Q_DESC_MODE(x, v)                                        \\\n\t(BIT_CLEAR_P0HI11Q_DESC_MODE(x) | BIT_P0HI11Q_DESC_MODE(v))\n\n#define BIT_SHIFT_P0HI11Q_DESC_NUM 16\n#define BIT_MASK_P0HI11Q_DESC_NUM 0xfff\n#define BIT_P0HI11Q_DESC_NUM(x)                                                \\\n\t(((x) & BIT_MASK_P0HI11Q_DESC_NUM) << BIT_SHIFT_P0HI11Q_DESC_NUM)\n#define BITS_P0HI11Q_DESC_NUM                                                  \\\n\t(BIT_MASK_P0HI11Q_DESC_NUM << BIT_SHIFT_P0HI11Q_DESC_NUM)\n#define BIT_CLEAR_P0HI11Q_DESC_NUM(x) ((x) & (~BITS_P0HI11Q_DESC_NUM))\n#define BIT_GET_P0HI11Q_DESC_NUM(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI11Q_DESC_NUM) & BIT_MASK_P0HI11Q_DESC_NUM)\n#define BIT_SET_P0HI11Q_DESC_NUM(x, v)                                         \\\n\t(BIT_CLEAR_P0HI11Q_DESC_NUM(x) | BIT_P0HI11Q_DESC_NUM(v))\n\n#define BIT_P0HI10Q_FLAG BIT(14)\n\n#define BIT_SHIFT_P0HI10Q_DESC_MODE 12\n#define BIT_MASK_P0HI10Q_DESC_MODE 0x3\n#define BIT_P0HI10Q_DESC_MODE(x)                                               \\\n\t(((x) & BIT_MASK_P0HI10Q_DESC_MODE) << BIT_SHIFT_P0HI10Q_DESC_MODE)\n#define BITS_P0HI10Q_DESC_MODE                                                 \\\n\t(BIT_MASK_P0HI10Q_DESC_MODE << BIT_SHIFT_P0HI10Q_DESC_MODE)\n#define BIT_CLEAR_P0HI10Q_DESC_MODE(x) ((x) & (~BITS_P0HI10Q_DESC_MODE))\n#define BIT_GET_P0HI10Q_DESC_MODE(x)                                           \\\n\t(((x) >> BIT_SHIFT_P0HI10Q_DESC_MODE) & BIT_MASK_P0HI10Q_DESC_MODE)\n#define BIT_SET_P0HI10Q_DESC_MODE(x, v)                                        \\\n\t(BIT_CLEAR_P0HI10Q_DESC_MODE(x) | BIT_P0HI10Q_DESC_MODE(v))\n\n#define BIT_SHIFT_P0HI10Q_DESC_NUM 0\n#define BIT_MASK_P0HI10Q_DESC_NUM 0xfff\n#define BIT_P0HI10Q_DESC_NUM(x)                                                \\\n\t(((x) & BIT_MASK_P0HI10Q_DESC_NUM) << BIT_SHIFT_P0HI10Q_DESC_NUM)\n#define BITS_P0HI10Q_DESC_NUM                                                  \\\n\t(BIT_MASK_P0HI10Q_DESC_NUM << BIT_SHIFT_P0HI10Q_DESC_NUM)\n#define BIT_CLEAR_P0HI10Q_DESC_NUM(x) ((x) & (~BITS_P0HI10Q_DESC_NUM))\n#define BIT_GET_P0HI10Q_DESC_NUM(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI10Q_DESC_NUM) & BIT_MASK_P0HI10Q_DESC_NUM)\n#define BIT_SET_P0HI10Q_DESC_NUM(x, v)                                         \\\n\t(BIT_CLEAR_P0HI10Q_DESC_NUM(x) | BIT_P0HI10Q_DESC_NUM(v))\n\n/* 2 REG_P0HI12Q_HI13Q_TXBD_NUM\t\t(Offset 0x23C8) */\n\n#define BIT_P0HI13Q_FLAG BIT(30)\n\n#define BIT_SHIFT_P0HI13Q_DESC_MODE 28\n#define BIT_MASK_P0HI13Q_DESC_MODE 0x3\n#define BIT_P0HI13Q_DESC_MODE(x)                                               \\\n\t(((x) & BIT_MASK_P0HI13Q_DESC_MODE) << BIT_SHIFT_P0HI13Q_DESC_MODE)\n#define BITS_P0HI13Q_DESC_MODE                                                 \\\n\t(BIT_MASK_P0HI13Q_DESC_MODE << BIT_SHIFT_P0HI13Q_DESC_MODE)\n#define BIT_CLEAR_P0HI13Q_DESC_MODE(x) ((x) & (~BITS_P0HI13Q_DESC_MODE))\n#define BIT_GET_P0HI13Q_DESC_MODE(x)                                           \\\n\t(((x) >> BIT_SHIFT_P0HI13Q_DESC_MODE) & BIT_MASK_P0HI13Q_DESC_MODE)\n#define BIT_SET_P0HI13Q_DESC_MODE(x, v)                                        \\\n\t(BIT_CLEAR_P0HI13Q_DESC_MODE(x) | BIT_P0HI13Q_DESC_MODE(v))\n\n#define BIT_SHIFT_P0HI13Q_DESC_NUM 16\n#define BIT_MASK_P0HI13Q_DESC_NUM 0xfff\n#define BIT_P0HI13Q_DESC_NUM(x)                                                \\\n\t(((x) & BIT_MASK_P0HI13Q_DESC_NUM) << BIT_SHIFT_P0HI13Q_DESC_NUM)\n#define BITS_P0HI13Q_DESC_NUM                                                  \\\n\t(BIT_MASK_P0HI13Q_DESC_NUM << BIT_SHIFT_P0HI13Q_DESC_NUM)\n#define BIT_CLEAR_P0HI13Q_DESC_NUM(x) ((x) & (~BITS_P0HI13Q_DESC_NUM))\n#define BIT_GET_P0HI13Q_DESC_NUM(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI13Q_DESC_NUM) & BIT_MASK_P0HI13Q_DESC_NUM)\n#define BIT_SET_P0HI13Q_DESC_NUM(x, v)                                         \\\n\t(BIT_CLEAR_P0HI13Q_DESC_NUM(x) | BIT_P0HI13Q_DESC_NUM(v))\n\n#define BIT_P0HI12Q_FLAG BIT(14)\n\n#define BIT_SHIFT_P0HI12Q_DESC_MODE 12\n#define BIT_MASK_P0HI12Q_DESC_MODE 0x3\n#define BIT_P0HI12Q_DESC_MODE(x)                                               \\\n\t(((x) & BIT_MASK_P0HI12Q_DESC_MODE) << BIT_SHIFT_P0HI12Q_DESC_MODE)\n#define BITS_P0HI12Q_DESC_MODE                                                 \\\n\t(BIT_MASK_P0HI12Q_DESC_MODE << BIT_SHIFT_P0HI12Q_DESC_MODE)\n#define BIT_CLEAR_P0HI12Q_DESC_MODE(x) ((x) & (~BITS_P0HI12Q_DESC_MODE))\n#define BIT_GET_P0HI12Q_DESC_MODE(x)                                           \\\n\t(((x) >> BIT_SHIFT_P0HI12Q_DESC_MODE) & BIT_MASK_P0HI12Q_DESC_MODE)\n#define BIT_SET_P0HI12Q_DESC_MODE(x, v)                                        \\\n\t(BIT_CLEAR_P0HI12Q_DESC_MODE(x) | BIT_P0HI12Q_DESC_MODE(v))\n\n#define BIT_SHIFT_P0HI12Q_DESC_NUM 0\n#define BIT_MASK_P0HI12Q_DESC_NUM 0xfff\n#define BIT_P0HI12Q_DESC_NUM(x)                                                \\\n\t(((x) & BIT_MASK_P0HI12Q_DESC_NUM) << BIT_SHIFT_P0HI12Q_DESC_NUM)\n#define BITS_P0HI12Q_DESC_NUM                                                  \\\n\t(BIT_MASK_P0HI12Q_DESC_NUM << BIT_SHIFT_P0HI12Q_DESC_NUM)\n#define BIT_CLEAR_P0HI12Q_DESC_NUM(x) ((x) & (~BITS_P0HI12Q_DESC_NUM))\n#define BIT_GET_P0HI12Q_DESC_NUM(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI12Q_DESC_NUM) & BIT_MASK_P0HI12Q_DESC_NUM)\n#define BIT_SET_P0HI12Q_DESC_NUM(x, v)                                         \\\n\t(BIT_CLEAR_P0HI12Q_DESC_NUM(x) | BIT_P0HI12Q_DESC_NUM(v))\n\n/* 2 REG_P0HI14Q_HI15Q_TXBD_NUM\t\t(Offset 0x23CC) */\n\n#define BIT_P0HI15Q_FLAG BIT(30)\n\n#define BIT_SHIFT_P0HI15Q_DESC_MODE 28\n#define BIT_MASK_P0HI15Q_DESC_MODE 0x3\n#define BIT_P0HI15Q_DESC_MODE(x)                                               \\\n\t(((x) & BIT_MASK_P0HI15Q_DESC_MODE) << BIT_SHIFT_P0HI15Q_DESC_MODE)\n#define BITS_P0HI15Q_DESC_MODE                                                 \\\n\t(BIT_MASK_P0HI15Q_DESC_MODE << BIT_SHIFT_P0HI15Q_DESC_MODE)\n#define BIT_CLEAR_P0HI15Q_DESC_MODE(x) ((x) & (~BITS_P0HI15Q_DESC_MODE))\n#define BIT_GET_P0HI15Q_DESC_MODE(x)                                           \\\n\t(((x) >> BIT_SHIFT_P0HI15Q_DESC_MODE) & BIT_MASK_P0HI15Q_DESC_MODE)\n#define BIT_SET_P0HI15Q_DESC_MODE(x, v)                                        \\\n\t(BIT_CLEAR_P0HI15Q_DESC_MODE(x) | BIT_P0HI15Q_DESC_MODE(v))\n\n#define BIT_SHIFT_P0HI15Q_DESC_NUM 16\n#define BIT_MASK_P0HI15Q_DESC_NUM 0xfff\n#define BIT_P0HI15Q_DESC_NUM(x)                                                \\\n\t(((x) & BIT_MASK_P0HI15Q_DESC_NUM) << BIT_SHIFT_P0HI15Q_DESC_NUM)\n#define BITS_P0HI15Q_DESC_NUM                                                  \\\n\t(BIT_MASK_P0HI15Q_DESC_NUM << BIT_SHIFT_P0HI15Q_DESC_NUM)\n#define BIT_CLEAR_P0HI15Q_DESC_NUM(x) ((x) & (~BITS_P0HI15Q_DESC_NUM))\n#define BIT_GET_P0HI15Q_DESC_NUM(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI15Q_DESC_NUM) & BIT_MASK_P0HI15Q_DESC_NUM)\n#define BIT_SET_P0HI15Q_DESC_NUM(x, v)                                         \\\n\t(BIT_CLEAR_P0HI15Q_DESC_NUM(x) | BIT_P0HI15Q_DESC_NUM(v))\n\n#define BIT_P0HI14Q_FLAG BIT(14)\n\n#define BIT_SHIFT_P0HI14Q_DESC_MODE 12\n#define BIT_MASK_P0HI14Q_DESC_MODE 0x3\n#define BIT_P0HI14Q_DESC_MODE(x)                                               \\\n\t(((x) & BIT_MASK_P0HI14Q_DESC_MODE) << BIT_SHIFT_P0HI14Q_DESC_MODE)\n#define BITS_P0HI14Q_DESC_MODE                                                 \\\n\t(BIT_MASK_P0HI14Q_DESC_MODE << BIT_SHIFT_P0HI14Q_DESC_MODE)\n#define BIT_CLEAR_P0HI14Q_DESC_MODE(x) ((x) & (~BITS_P0HI14Q_DESC_MODE))\n#define BIT_GET_P0HI14Q_DESC_MODE(x)                                           \\\n\t(((x) >> BIT_SHIFT_P0HI14Q_DESC_MODE) & BIT_MASK_P0HI14Q_DESC_MODE)\n#define BIT_SET_P0HI14Q_DESC_MODE(x, v)                                        \\\n\t(BIT_CLEAR_P0HI14Q_DESC_MODE(x) | BIT_P0HI14Q_DESC_MODE(v))\n\n#define BIT_SHIFT_P0HI14Q_DESC_NUM 0\n#define BIT_MASK_P0HI14Q_DESC_NUM 0xfff\n#define BIT_P0HI14Q_DESC_NUM(x)                                                \\\n\t(((x) & BIT_MASK_P0HI14Q_DESC_NUM) << BIT_SHIFT_P0HI14Q_DESC_NUM)\n#define BITS_P0HI14Q_DESC_NUM                                                  \\\n\t(BIT_MASK_P0HI14Q_DESC_NUM << BIT_SHIFT_P0HI14Q_DESC_NUM)\n#define BIT_CLEAR_P0HI14Q_DESC_NUM(x) ((x) & (~BITS_P0HI14Q_DESC_NUM))\n#define BIT_GET_P0HI14Q_DESC_NUM(x)                                            \\\n\t(((x) >> BIT_SHIFT_P0HI14Q_DESC_NUM) & BIT_MASK_P0HI14Q_DESC_NUM)\n#define BIT_SET_P0HI14Q_DESC_NUM(x, v)                                         \\\n\t(BIT_CLEAR_P0HI14Q_DESC_NUM(x) | BIT_P0HI14Q_DESC_NUM(v))\n\n/* 2 REG_ACH6_ACH7_TXBD_NUM\t\t\t(Offset 0x23F0) */\n\n#define BIT_PCIE_ACH7_FLAG BIT(30)\n\n#define BIT_SHIFT_ACH7_DESC_MODE 28\n#define BIT_MASK_ACH7_DESC_MODE 0x3\n#define BIT_ACH7_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_ACH7_DESC_MODE) << BIT_SHIFT_ACH7_DESC_MODE)\n#define BITS_ACH7_DESC_MODE                                                    \\\n\t(BIT_MASK_ACH7_DESC_MODE << BIT_SHIFT_ACH7_DESC_MODE)\n#define BIT_CLEAR_ACH7_DESC_MODE(x) ((x) & (~BITS_ACH7_DESC_MODE))\n#define BIT_GET_ACH7_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_ACH7_DESC_MODE) & BIT_MASK_ACH7_DESC_MODE)\n#define BIT_SET_ACH7_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_ACH7_DESC_MODE(x) | BIT_ACH7_DESC_MODE(v))\n\n#define BIT_SHIFT_ACH7_DESC_NUM 16\n#define BIT_MASK_ACH7_DESC_NUM 0xfff\n#define BIT_ACH7_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_ACH7_DESC_NUM) << BIT_SHIFT_ACH7_DESC_NUM)\n#define BITS_ACH7_DESC_NUM (BIT_MASK_ACH7_DESC_NUM << BIT_SHIFT_ACH7_DESC_NUM)\n#define BIT_CLEAR_ACH7_DESC_NUM(x) ((x) & (~BITS_ACH7_DESC_NUM))\n#define BIT_GET_ACH7_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH7_DESC_NUM) & BIT_MASK_ACH7_DESC_NUM)\n#define BIT_SET_ACH7_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_ACH7_DESC_NUM(x) | BIT_ACH7_DESC_NUM(v))\n\n#define BIT_PCIE_ACH6_FLAG BIT(14)\n\n#define BIT_SHIFT_ACH6_DESC_MODE 12\n#define BIT_MASK_ACH6_DESC_MODE 0x3\n#define BIT_ACH6_DESC_MODE(x)                                                  \\\n\t(((x) & BIT_MASK_ACH6_DESC_MODE) << BIT_SHIFT_ACH6_DESC_MODE)\n#define BITS_ACH6_DESC_MODE                                                    \\\n\t(BIT_MASK_ACH6_DESC_MODE << BIT_SHIFT_ACH6_DESC_MODE)\n#define BIT_CLEAR_ACH6_DESC_MODE(x) ((x) & (~BITS_ACH6_DESC_MODE))\n#define BIT_GET_ACH6_DESC_MODE(x)                                              \\\n\t(((x) >> BIT_SHIFT_ACH6_DESC_MODE) & BIT_MASK_ACH6_DESC_MODE)\n#define BIT_SET_ACH6_DESC_MODE(x, v)                                           \\\n\t(BIT_CLEAR_ACH6_DESC_MODE(x) | BIT_ACH6_DESC_MODE(v))\n\n#define BIT_SHIFT_ACH6_DESC_NUM 0\n#define BIT_MASK_ACH6_DESC_NUM 0xfff\n#define BIT_ACH6_DESC_NUM(x)                                                   \\\n\t(((x) & BIT_MASK_ACH6_DESC_NUM) << BIT_SHIFT_ACH6_DESC_NUM)\n#define BITS_ACH6_DESC_NUM (BIT_MASK_ACH6_DESC_NUM << BIT_SHIFT_ACH6_DESC_NUM)\n#define BIT_CLEAR_ACH6_DESC_NUM(x) ((x) & (~BITS_ACH6_DESC_NUM))\n#define BIT_GET_ACH6_DESC_NUM(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH6_DESC_NUM) & BIT_MASK_ACH6_DESC_NUM)\n#define BIT_SET_ACH6_DESC_NUM(x, v)                                            \\\n\t(BIT_CLEAR_ACH6_DESC_NUM(x) | BIT_ACH6_DESC_NUM(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_FAST_EDCA_VOVI_SETTING_V1\t\t(Offset 0x2448) */\n\n#define BIT_SHIFT_VO_FAST_EDCA_TO_V1 0\n#define BIT_MASK_VO_FAST_EDCA_TO_V1 0xffff\n#define BIT_VO_FAST_EDCA_TO_V1(x)                                              \\\n\t(((x) & BIT_MASK_VO_FAST_EDCA_TO_V1) << BIT_SHIFT_VO_FAST_EDCA_TO_V1)\n#define BITS_VO_FAST_EDCA_TO_V1                                                \\\n\t(BIT_MASK_VO_FAST_EDCA_TO_V1 << BIT_SHIFT_VO_FAST_EDCA_TO_V1)\n#define BIT_CLEAR_VO_FAST_EDCA_TO_V1(x) ((x) & (~BITS_VO_FAST_EDCA_TO_V1))\n#define BIT_GET_VO_FAST_EDCA_TO_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_V1) & BIT_MASK_VO_FAST_EDCA_TO_V1)\n#define BIT_SET_VO_FAST_EDCA_TO_V1(x, v)                                       \\\n\t(BIT_CLEAR_VO_FAST_EDCA_TO_V1(x) | BIT_VO_FAST_EDCA_TO_V1(v))\n\n/* 2 REG_FAST_EDCA_BEBK_SETTING_V1\t\t(Offset 0x244C) */\n\n#define BIT_SHIFT_BE_FAST_EDCA_TO_V1 0\n#define BIT_MASK_BE_FAST_EDCA_TO_V1 0xffff\n#define BIT_BE_FAST_EDCA_TO_V1(x)                                              \\\n\t(((x) & BIT_MASK_BE_FAST_EDCA_TO_V1) << BIT_SHIFT_BE_FAST_EDCA_TO_V1)\n#define BITS_BE_FAST_EDCA_TO_V1                                                \\\n\t(BIT_MASK_BE_FAST_EDCA_TO_V1 << BIT_SHIFT_BE_FAST_EDCA_TO_V1)\n#define BIT_CLEAR_BE_FAST_EDCA_TO_V1(x) ((x) & (~BITS_BE_FAST_EDCA_TO_V1))\n#define BIT_GET_BE_FAST_EDCA_TO_V1(x)                                          \\\n\t(((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_V1) & BIT_MASK_BE_FAST_EDCA_TO_V1)\n#define BIT_SET_BE_FAST_EDCA_TO_V1(x, v)                                       \\\n\t(BIT_CLEAR_BE_FAST_EDCA_TO_V1(x) | BIT_BE_FAST_EDCA_TO_V1(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_0_V1\t(Offset 0x2460) */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_0(x)                                       \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0)                            \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0)\n#define BITS_R_MACID_RELEASE_SUCCESS_0                                         \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_0                                    \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0(x)                                 \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_0(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) &                        \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_0)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_0(x, v)                                \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0(x) |                              \\\n\t BIT_R_MACID_RELEASE_SUCCESS_0(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_2_V1\t(Offset 0x2468) */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_2(x)                                       \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2)                            \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2)\n#define BITS_R_MACID_RELEASE_SUCCESS_2                                         \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_2                                    \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2(x)                                 \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_2(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) &                        \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_2)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_2(x, v)                                \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2(x) |                              \\\n\t BIT_R_MACID_RELEASE_SUCCESS_2(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/* 2 REG_NAN_INFO0\t\t\t\t(Offset 0x2480) */\n\n#define BIT_SHIFT_NAN_INFO0 0\n#define BIT_MASK_NAN_INFO0 0xffffffffL\n#define BIT_NAN_INFO0(x) (((x) & BIT_MASK_NAN_INFO0) << BIT_SHIFT_NAN_INFO0)\n#define BITS_NAN_INFO0 (BIT_MASK_NAN_INFO0 << BIT_SHIFT_NAN_INFO0)\n#define BIT_CLEAR_NAN_INFO0(x) ((x) & (~BITS_NAN_INFO0))\n#define BIT_GET_NAN_INFO0(x) (((x) >> BIT_SHIFT_NAN_INFO0) & BIT_MASK_NAN_INFO0)\n#define BIT_SET_NAN_INFO0(x, v) (BIT_CLEAR_NAN_INFO0(x) | BIT_NAN_INFO0(v))\n\n/* 2 REG_NAN_INFO1\t\t\t\t(Offset 0x2484) */\n\n#define BIT_SHIFT_NAN_INFO1 0\n#define BIT_MASK_NAN_INFO1 0xffffffffL\n#define BIT_NAN_INFO1(x) (((x) & BIT_MASK_NAN_INFO1) << BIT_SHIFT_NAN_INFO1)\n#define BITS_NAN_INFO1 (BIT_MASK_NAN_INFO1 << BIT_SHIFT_NAN_INFO1)\n#define BIT_CLEAR_NAN_INFO1(x) ((x) & (~BITS_NAN_INFO1))\n#define BIT_GET_NAN_INFO1(x) (((x) >> BIT_SHIFT_NAN_INFO1) & BIT_MASK_NAN_INFO1)\n#define BIT_SET_NAN_INFO1(x, v) (BIT_CLEAR_NAN_INFO1(x) | BIT_NAN_INFO1(v))\n\n/* 2 REG_NAN_INFO2\t\t\t\t(Offset 0x2488) */\n\n#define BIT_SHIFT_NAN_INFO2 0\n#define BIT_MASK_NAN_INFO2 0xffffffffL\n#define BIT_NAN_INFO2(x) (((x) & BIT_MASK_NAN_INFO2) << BIT_SHIFT_NAN_INFO2)\n#define BITS_NAN_INFO2 (BIT_MASK_NAN_INFO2 << BIT_SHIFT_NAN_INFO2)\n#define BIT_CLEAR_NAN_INFO2(x) ((x) & (~BITS_NAN_INFO2))\n#define BIT_GET_NAN_INFO2(x) (((x) >> BIT_SHIFT_NAN_INFO2) & BIT_MASK_NAN_INFO2)\n#define BIT_SET_NAN_INFO2(x, v) (BIT_CLEAR_NAN_INFO2(x) | BIT_NAN_INFO2(v))\n\n/* 2 REG_NAN_INFO3\t\t\t\t(Offset 0x248C) */\n\n#define BIT_SHIFT_NAN_INFO3 0\n#define BIT_MASK_NAN_INFO3 0xffffffffL\n#define BIT_NAN_INFO3(x) (((x) & BIT_MASK_NAN_INFO3) << BIT_SHIFT_NAN_INFO3)\n#define BITS_NAN_INFO3 (BIT_MASK_NAN_INFO3 << BIT_SHIFT_NAN_INFO3)\n#define BIT_CLEAR_NAN_INFO3(x) ((x) & (~BITS_NAN_INFO3))\n#define BIT_GET_NAN_INFO3(x) (((x) >> BIT_SHIFT_NAN_INFO3) & BIT_MASK_NAN_INFO3)\n#define BIT_SET_NAN_INFO3(x, v) (BIT_CLEAR_NAN_INFO3(x) | BIT_NAN_INFO3(v))\n\n/* 2 REG_NAN_INFO4\t\t\t\t(Offset 0x2490) */\n\n#define BIT_SHIFT_NAN_INFO4 0\n#define BIT_MASK_NAN_INFO4 0xffffffffL\n#define BIT_NAN_INFO4(x) (((x) & BIT_MASK_NAN_INFO4) << BIT_SHIFT_NAN_INFO4)\n#define BITS_NAN_INFO4 (BIT_MASK_NAN_INFO4 << BIT_SHIFT_NAN_INFO4)\n#define BIT_CLEAR_NAN_INFO4(x) ((x) & (~BITS_NAN_INFO4))\n#define BIT_GET_NAN_INFO4(x) (((x) >> BIT_SHIFT_NAN_INFO4) & BIT_MASK_NAN_INFO4)\n#define BIT_SET_NAN_INFO4(x, v) (BIT_CLEAR_NAN_INFO4(x) | BIT_NAN_INFO4(v))\n\n/* 2 REG_NAN_INFO5\t\t\t\t(Offset 0x2494) */\n\n#define BIT_SHIFT_NAN_INFO5 0\n#define BIT_MASK_NAN_INFO5 0xffffffffL\n#define BIT_NAN_INFO5(x) (((x) & BIT_MASK_NAN_INFO5) << BIT_SHIFT_NAN_INFO5)\n#define BITS_NAN_INFO5 (BIT_MASK_NAN_INFO5 << BIT_SHIFT_NAN_INFO5)\n#define BIT_CLEAR_NAN_INFO5(x) ((x) & (~BITS_NAN_INFO5))\n#define BIT_GET_NAN_INFO5(x) (((x) >> BIT_SHIFT_NAN_INFO5) & BIT_MASK_NAN_INFO5)\n#define BIT_SET_NAN_INFO5(x, v) (BIT_CLEAR_NAN_INFO5(x) | BIT_NAN_INFO5(v))\n\n/* 2 REG_NAN_INFO6\t\t\t\t(Offset 0x2498) */\n\n#define BIT_SHIFT_NAN_INFO6 0\n#define BIT_MASK_NAN_INFO6 0xffffffffL\n#define BIT_NAN_INFO6(x) (((x) & BIT_MASK_NAN_INFO6) << BIT_SHIFT_NAN_INFO6)\n#define BITS_NAN_INFO6 (BIT_MASK_NAN_INFO6 << BIT_SHIFT_NAN_INFO6)\n#define BIT_CLEAR_NAN_INFO6(x) ((x) & (~BITS_NAN_INFO6))\n#define BIT_GET_NAN_INFO6(x) (((x) >> BIT_SHIFT_NAN_INFO6) & BIT_MASK_NAN_INFO6)\n#define BIT_SET_NAN_INFO6(x, v) (BIT_CLEAR_NAN_INFO6(x) | BIT_NAN_INFO6(v))\n\n/* 2 REG_NAN_INFO7\t\t\t\t(Offset 0x249C) */\n\n#define BIT_SHIFT_NAN_INFO7 0\n#define BIT_MASK_NAN_INFO7 0xffffffffL\n#define BIT_NAN_INFO7(x) (((x) & BIT_MASK_NAN_INFO7) << BIT_SHIFT_NAN_INFO7)\n#define BITS_NAN_INFO7 (BIT_MASK_NAN_INFO7 << BIT_SHIFT_NAN_INFO7)\n#define BIT_CLEAR_NAN_INFO7(x) ((x) & (~BITS_NAN_INFO7))\n#define BIT_GET_NAN_INFO7(x) (((x) >> BIT_SHIFT_NAN_INFO7) & BIT_MASK_NAN_INFO7)\n#define BIT_SET_NAN_INFO7(x, v) (BIT_CLEAR_NAN_INFO7(x) | BIT_NAN_INFO7(v))\n\n/* 2 REG_NAN_INFO8\t\t\t\t(Offset 0x24A0) */\n\n#define BIT_SHIFT_NAN_INFO8 0\n#define BIT_MASK_NAN_INFO8 0xffffffffL\n#define BIT_NAN_INFO8(x) (((x) & BIT_MASK_NAN_INFO8) << BIT_SHIFT_NAN_INFO8)\n#define BITS_NAN_INFO8 (BIT_MASK_NAN_INFO8 << BIT_SHIFT_NAN_INFO8)\n#define BIT_CLEAR_NAN_INFO8(x) ((x) & (~BITS_NAN_INFO8))\n#define BIT_GET_NAN_INFO8(x) (((x) >> BIT_SHIFT_NAN_INFO8) & BIT_MASK_NAN_INFO8)\n#define BIT_SET_NAN_INFO8(x, v) (BIT_CLEAR_NAN_INFO8(x) | BIT_NAN_INFO8(v))\n\n/* 2 REG_NAN_INFO9\t\t\t\t(Offset 0x24A4) */\n\n#define BIT_SHIFT_NAN_INFO9 0\n#define BIT_MASK_NAN_INFO9 0xffffffffL\n#define BIT_NAN_INFO9(x) (((x) & BIT_MASK_NAN_INFO9) << BIT_SHIFT_NAN_INFO9)\n#define BITS_NAN_INFO9 (BIT_MASK_NAN_INFO9 << BIT_SHIFT_NAN_INFO9)\n#define BIT_CLEAR_NAN_INFO9(x) ((x) & (~BITS_NAN_INFO9))\n#define BIT_GET_NAN_INFO9(x) (((x) >> BIT_SHIFT_NAN_INFO9) & BIT_MASK_NAN_INFO9)\n#define BIT_SET_NAN_INFO9(x, v) (BIT_CLEAR_NAN_INFO9(x) | BIT_NAN_INFO9(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CHNL_INFO_CTRL_V1\t\t\t(Offset 0x24D0) */\n\n#define BIT_CHNL_REF_EDCA BIT(5)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n/* 2 REG_CHNL_IDLE_TIME_V1\t\t\t(Offset 0x24D4) */\n\n#define BIT_SHIFT_CHNL_IDLE_TIME 0\n#define BIT_MASK_CHNL_IDLE_TIME 0xffffffffL\n#define BIT_CHNL_IDLE_TIME(x)                                                  \\\n\t(((x) & BIT_MASK_CHNL_IDLE_TIME) << BIT_SHIFT_CHNL_IDLE_TIME)\n#define BITS_CHNL_IDLE_TIME                                                    \\\n\t(BIT_MASK_CHNL_IDLE_TIME << BIT_SHIFT_CHNL_IDLE_TIME)\n#define BIT_CLEAR_CHNL_IDLE_TIME(x) ((x) & (~BITS_CHNL_IDLE_TIME))\n#define BIT_GET_CHNL_IDLE_TIME(x)                                              \\\n\t(((x) >> BIT_SHIFT_CHNL_IDLE_TIME) & BIT_MASK_CHNL_IDLE_TIME)\n#define BIT_SET_CHNL_IDLE_TIME(x, v)                                           \\\n\t(BIT_CLEAR_CHNL_IDLE_TIME(x) | BIT_CHNL_IDLE_TIME(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SWPS_PKT_TH_V1\t\t\t(Offset 0x24F6) */\n\n#define BIT_SHIFT_SWPS_PKT_TH 0\n#define BIT_MASK_SWPS_PKT_TH 0xffff\n#define BIT_SWPS_PKT_TH(x)                                                     \\\n\t(((x) & BIT_MASK_SWPS_PKT_TH) << BIT_SHIFT_SWPS_PKT_TH)\n#define BITS_SWPS_PKT_TH (BIT_MASK_SWPS_PKT_TH << BIT_SHIFT_SWPS_PKT_TH)\n#define BIT_CLEAR_SWPS_PKT_TH(x) ((x) & (~BITS_SWPS_PKT_TH))\n#define BIT_GET_SWPS_PKT_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_SWPS_PKT_TH) & BIT_MASK_SWPS_PKT_TH)\n#define BIT_SET_SWPS_PKT_TH(x, v)                                              \\\n\t(BIT_CLEAR_SWPS_PKT_TH(x) | BIT_SWPS_PKT_TH(v))\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT)\n\n/* 2 REG_SWPS_TIME_TH_V1\t\t\t(Offset 0x24F8) */\n\n#define BIT_SHIFT_SWPS_PSTIME_TH 16\n#define BIT_MASK_SWPS_PSTIME_TH 0xffff\n#define BIT_SWPS_PSTIME_TH(x)                                                  \\\n\t(((x) & BIT_MASK_SWPS_PSTIME_TH) << BIT_SHIFT_SWPS_PSTIME_TH)\n#define BITS_SWPS_PSTIME_TH                                                    \\\n\t(BIT_MASK_SWPS_PSTIME_TH << BIT_SHIFT_SWPS_PSTIME_TH)\n#define BIT_CLEAR_SWPS_PSTIME_TH(x) ((x) & (~BITS_SWPS_PSTIME_TH))\n#define BIT_GET_SWPS_PSTIME_TH(x)                                              \\\n\t(((x) >> BIT_SHIFT_SWPS_PSTIME_TH) & BIT_MASK_SWPS_PSTIME_TH)\n#define BIT_SET_SWPS_PSTIME_TH(x, v)                                           \\\n\t(BIT_CLEAR_SWPS_PSTIME_TH(x) | BIT_SWPS_PSTIME_TH(v))\n\n#define BIT_SHIFT_SWPS_TIME_TH 0\n#define BIT_MASK_SWPS_TIME_TH 0xffff\n#define BIT_SWPS_TIME_TH(x)                                                    \\\n\t(((x) & BIT_MASK_SWPS_TIME_TH) << BIT_SHIFT_SWPS_TIME_TH)\n#define BITS_SWPS_TIME_TH (BIT_MASK_SWPS_TIME_TH << BIT_SHIFT_SWPS_TIME_TH)\n#define BIT_CLEAR_SWPS_TIME_TH(x) ((x) & (~BITS_SWPS_TIME_TH))\n#define BIT_GET_SWPS_TIME_TH(x)                                                \\\n\t(((x) >> BIT_SHIFT_SWPS_TIME_TH) & BIT_MASK_SWPS_TIME_TH)\n#define BIT_SET_SWPS_TIME_TH(x, v)                                             \\\n\t(BIT_CLEAR_SWPS_TIME_TH(x) | BIT_SWPS_TIME_TH(v))\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/* 2 REG_TXPAGE_INT_CTRL_0\t\t\t(Offset 0x3200) */\n\n#define BIT_CH0_INT_EN BIT(31)\n\n#define BIT_SHIFT_CH0_HIGH_TH 16\n#define BIT_MASK_CH0_HIGH_TH 0xfff\n#define BIT_CH0_HIGH_TH(x)                                                     \\\n\t(((x) & BIT_MASK_CH0_HIGH_TH) << BIT_SHIFT_CH0_HIGH_TH)\n#define BITS_CH0_HIGH_TH (BIT_MASK_CH0_HIGH_TH << BIT_SHIFT_CH0_HIGH_TH)\n#define BIT_CLEAR_CH0_HIGH_TH(x) ((x) & (~BITS_CH0_HIGH_TH))\n#define BIT_GET_CH0_HIGH_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH0_HIGH_TH) & BIT_MASK_CH0_HIGH_TH)\n#define BIT_SET_CH0_HIGH_TH(x, v)                                              \\\n\t(BIT_CLEAR_CH0_HIGH_TH(x) | BIT_CH0_HIGH_TH(v))\n\n#define BIT_SHIFT_CH0_LOW_TH 0\n#define BIT_MASK_CH0_LOW_TH 0xfff\n#define BIT_CH0_LOW_TH(x) (((x) & BIT_MASK_CH0_LOW_TH) << BIT_SHIFT_CH0_LOW_TH)\n#define BITS_CH0_LOW_TH (BIT_MASK_CH0_LOW_TH << BIT_SHIFT_CH0_LOW_TH)\n#define BIT_CLEAR_CH0_LOW_TH(x) ((x) & (~BITS_CH0_LOW_TH))\n#define BIT_GET_CH0_LOW_TH(x)                                                  \\\n\t(((x) >> BIT_SHIFT_CH0_LOW_TH) & BIT_MASK_CH0_LOW_TH)\n#define BIT_SET_CH0_LOW_TH(x, v) (BIT_CLEAR_CH0_LOW_TH(x) | BIT_CH0_LOW_TH(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_1\t\t\t(Offset 0x3204) */\n\n#define BIT_CH1_INT_EN BIT(31)\n\n#define BIT_SHIFT_CH1_HIGH_TH 16\n#define BIT_MASK_CH1_HIGH_TH 0xfff\n#define BIT_CH1_HIGH_TH(x)                                                     \\\n\t(((x) & BIT_MASK_CH1_HIGH_TH) << BIT_SHIFT_CH1_HIGH_TH)\n#define BITS_CH1_HIGH_TH (BIT_MASK_CH1_HIGH_TH << BIT_SHIFT_CH1_HIGH_TH)\n#define BIT_CLEAR_CH1_HIGH_TH(x) ((x) & (~BITS_CH1_HIGH_TH))\n#define BIT_GET_CH1_HIGH_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH1_HIGH_TH) & BIT_MASK_CH1_HIGH_TH)\n#define BIT_SET_CH1_HIGH_TH(x, v)                                              \\\n\t(BIT_CLEAR_CH1_HIGH_TH(x) | BIT_CH1_HIGH_TH(v))\n\n#define BIT_SHIFT_CH1_LOW_TH 0\n#define BIT_MASK_CH1_LOW_TH 0xfff\n#define BIT_CH1_LOW_TH(x) (((x) & BIT_MASK_CH1_LOW_TH) << BIT_SHIFT_CH1_LOW_TH)\n#define BITS_CH1_LOW_TH (BIT_MASK_CH1_LOW_TH << BIT_SHIFT_CH1_LOW_TH)\n#define BIT_CLEAR_CH1_LOW_TH(x) ((x) & (~BITS_CH1_LOW_TH))\n#define BIT_GET_CH1_LOW_TH(x)                                                  \\\n\t(((x) >> BIT_SHIFT_CH1_LOW_TH) & BIT_MASK_CH1_LOW_TH)\n#define BIT_SET_CH1_LOW_TH(x, v) (BIT_CLEAR_CH1_LOW_TH(x) | BIT_CH1_LOW_TH(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_2\t\t\t(Offset 0x3208) */\n\n#define BIT_CH2_INT_EN BIT(31)\n\n#define BIT_SHIFT_CH2_HIGH_TH 16\n#define BIT_MASK_CH2_HIGH_TH 0xfff\n#define BIT_CH2_HIGH_TH(x)                                                     \\\n\t(((x) & BIT_MASK_CH2_HIGH_TH) << BIT_SHIFT_CH2_HIGH_TH)\n#define BITS_CH2_HIGH_TH (BIT_MASK_CH2_HIGH_TH << BIT_SHIFT_CH2_HIGH_TH)\n#define BIT_CLEAR_CH2_HIGH_TH(x) ((x) & (~BITS_CH2_HIGH_TH))\n#define BIT_GET_CH2_HIGH_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH2_HIGH_TH) & BIT_MASK_CH2_HIGH_TH)\n#define BIT_SET_CH2_HIGH_TH(x, v)                                              \\\n\t(BIT_CLEAR_CH2_HIGH_TH(x) | BIT_CH2_HIGH_TH(v))\n\n#define BIT_SHIFT_CH2_LOW_TH 0\n#define BIT_MASK_CH2_LOW_TH 0xfff\n#define BIT_CH2_LOW_TH(x) (((x) & BIT_MASK_CH2_LOW_TH) << BIT_SHIFT_CH2_LOW_TH)\n#define BITS_CH2_LOW_TH (BIT_MASK_CH2_LOW_TH << BIT_SHIFT_CH2_LOW_TH)\n#define BIT_CLEAR_CH2_LOW_TH(x) ((x) & (~BITS_CH2_LOW_TH))\n#define BIT_GET_CH2_LOW_TH(x)                                                  \\\n\t(((x) >> BIT_SHIFT_CH2_LOW_TH) & BIT_MASK_CH2_LOW_TH)\n#define BIT_SET_CH2_LOW_TH(x, v) (BIT_CLEAR_CH2_LOW_TH(x) | BIT_CH2_LOW_TH(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_3\t\t\t(Offset 0x320C) */\n\n#define BIT_CH3_INT_EN BIT(31)\n\n#define BIT_SHIFT_CH3_HIGH_TH 16\n#define BIT_MASK_CH3_HIGH_TH 0xfff\n#define BIT_CH3_HIGH_TH(x)                                                     \\\n\t(((x) & BIT_MASK_CH3_HIGH_TH) << BIT_SHIFT_CH3_HIGH_TH)\n#define BITS_CH3_HIGH_TH (BIT_MASK_CH3_HIGH_TH << BIT_SHIFT_CH3_HIGH_TH)\n#define BIT_CLEAR_CH3_HIGH_TH(x) ((x) & (~BITS_CH3_HIGH_TH))\n#define BIT_GET_CH3_HIGH_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH3_HIGH_TH) & BIT_MASK_CH3_HIGH_TH)\n#define BIT_SET_CH3_HIGH_TH(x, v)                                              \\\n\t(BIT_CLEAR_CH3_HIGH_TH(x) | BIT_CH3_HIGH_TH(v))\n\n#define BIT_SHIFT_CH3_LOW_TH 0\n#define BIT_MASK_CH3_LOW_TH 0xfff\n#define BIT_CH3_LOW_TH(x) (((x) & BIT_MASK_CH3_LOW_TH) << BIT_SHIFT_CH3_LOW_TH)\n#define BITS_CH3_LOW_TH (BIT_MASK_CH3_LOW_TH << BIT_SHIFT_CH3_LOW_TH)\n#define BIT_CLEAR_CH3_LOW_TH(x) ((x) & (~BITS_CH3_LOW_TH))\n#define BIT_GET_CH3_LOW_TH(x)                                                  \\\n\t(((x) >> BIT_SHIFT_CH3_LOW_TH) & BIT_MASK_CH3_LOW_TH)\n#define BIT_SET_CH3_LOW_TH(x, v) (BIT_CLEAR_CH3_LOW_TH(x) | BIT_CH3_LOW_TH(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_4\t\t\t(Offset 0x3210) */\n\n#define BIT_CH4_INT_EN BIT(31)\n\n#define BIT_SHIFT_CH4_HIGH_TH 16\n#define BIT_MASK_CH4_HIGH_TH 0xfff\n#define BIT_CH4_HIGH_TH(x)                                                     \\\n\t(((x) & BIT_MASK_CH4_HIGH_TH) << BIT_SHIFT_CH4_HIGH_TH)\n#define BITS_CH4_HIGH_TH (BIT_MASK_CH4_HIGH_TH << BIT_SHIFT_CH4_HIGH_TH)\n#define BIT_CLEAR_CH4_HIGH_TH(x) ((x) & (~BITS_CH4_HIGH_TH))\n#define BIT_GET_CH4_HIGH_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH4_HIGH_TH) & BIT_MASK_CH4_HIGH_TH)\n#define BIT_SET_CH4_HIGH_TH(x, v)                                              \\\n\t(BIT_CLEAR_CH4_HIGH_TH(x) | BIT_CH4_HIGH_TH(v))\n\n#define BIT_SHIFT_CH4_LOW_TH 0\n#define BIT_MASK_CH4_LOW_TH 0xfff\n#define BIT_CH4_LOW_TH(x) (((x) & BIT_MASK_CH4_LOW_TH) << BIT_SHIFT_CH4_LOW_TH)\n#define BITS_CH4_LOW_TH (BIT_MASK_CH4_LOW_TH << BIT_SHIFT_CH4_LOW_TH)\n#define BIT_CLEAR_CH4_LOW_TH(x) ((x) & (~BITS_CH4_LOW_TH))\n#define BIT_GET_CH4_LOW_TH(x)                                                  \\\n\t(((x) >> BIT_SHIFT_CH4_LOW_TH) & BIT_MASK_CH4_LOW_TH)\n#define BIT_SET_CH4_LOW_TH(x, v) (BIT_CLEAR_CH4_LOW_TH(x) | BIT_CH4_LOW_TH(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_5\t\t\t(Offset 0x3214) */\n\n#define BIT_CH5_INT_EN BIT(31)\n\n#define BIT_SHIFT_CH5_HIGH_TH 16\n#define BIT_MASK_CH5_HIGH_TH 0xfff\n#define BIT_CH5_HIGH_TH(x)                                                     \\\n\t(((x) & BIT_MASK_CH5_HIGH_TH) << BIT_SHIFT_CH5_HIGH_TH)\n#define BITS_CH5_HIGH_TH (BIT_MASK_CH5_HIGH_TH << BIT_SHIFT_CH5_HIGH_TH)\n#define BIT_CLEAR_CH5_HIGH_TH(x) ((x) & (~BITS_CH5_HIGH_TH))\n#define BIT_GET_CH5_HIGH_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH5_HIGH_TH) & BIT_MASK_CH5_HIGH_TH)\n#define BIT_SET_CH5_HIGH_TH(x, v)                                              \\\n\t(BIT_CLEAR_CH5_HIGH_TH(x) | BIT_CH5_HIGH_TH(v))\n\n#define BIT_SHIFT_CH5_LOW_TH 0\n#define BIT_MASK_CH5_LOW_TH 0xfff\n#define BIT_CH5_LOW_TH(x) (((x) & BIT_MASK_CH5_LOW_TH) << BIT_SHIFT_CH5_LOW_TH)\n#define BITS_CH5_LOW_TH (BIT_MASK_CH5_LOW_TH << BIT_SHIFT_CH5_LOW_TH)\n#define BIT_CLEAR_CH5_LOW_TH(x) ((x) & (~BITS_CH5_LOW_TH))\n#define BIT_GET_CH5_LOW_TH(x)                                                  \\\n\t(((x) >> BIT_SHIFT_CH5_LOW_TH) & BIT_MASK_CH5_LOW_TH)\n#define BIT_SET_CH5_LOW_TH(x, v) (BIT_CLEAR_CH5_LOW_TH(x) | BIT_CH5_LOW_TH(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_6\t\t\t(Offset 0x3218) */\n\n#define BIT_CH6_INT_EN BIT(31)\n\n#define BIT_SHIFT_CH6_HIGH_TH 16\n#define BIT_MASK_CH6_HIGH_TH 0xfff\n#define BIT_CH6_HIGH_TH(x)                                                     \\\n\t(((x) & BIT_MASK_CH6_HIGH_TH) << BIT_SHIFT_CH6_HIGH_TH)\n#define BITS_CH6_HIGH_TH (BIT_MASK_CH6_HIGH_TH << BIT_SHIFT_CH6_HIGH_TH)\n#define BIT_CLEAR_CH6_HIGH_TH(x) ((x) & (~BITS_CH6_HIGH_TH))\n#define BIT_GET_CH6_HIGH_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH6_HIGH_TH) & BIT_MASK_CH6_HIGH_TH)\n#define BIT_SET_CH6_HIGH_TH(x, v)                                              \\\n\t(BIT_CLEAR_CH6_HIGH_TH(x) | BIT_CH6_HIGH_TH(v))\n\n#define BIT_SHIFT_CH6_LOW_TH 0\n#define BIT_MASK_CH6_LOW_TH 0xfff\n#define BIT_CH6_LOW_TH(x) (((x) & BIT_MASK_CH6_LOW_TH) << BIT_SHIFT_CH6_LOW_TH)\n#define BITS_CH6_LOW_TH (BIT_MASK_CH6_LOW_TH << BIT_SHIFT_CH6_LOW_TH)\n#define BIT_CLEAR_CH6_LOW_TH(x) ((x) & (~BITS_CH6_LOW_TH))\n#define BIT_GET_CH6_LOW_TH(x)                                                  \\\n\t(((x) >> BIT_SHIFT_CH6_LOW_TH) & BIT_MASK_CH6_LOW_TH)\n#define BIT_SET_CH6_LOW_TH(x, v) (BIT_CLEAR_CH6_LOW_TH(x) | BIT_CH6_LOW_TH(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_7\t\t\t(Offset 0x321C) */\n\n#define BIT_CH7_INT_EN BIT(31)\n\n#define BIT_SHIFT_CH7_HIGH_TH 16\n#define BIT_MASK_CH7_HIGH_TH 0xfff\n#define BIT_CH7_HIGH_TH(x)                                                     \\\n\t(((x) & BIT_MASK_CH7_HIGH_TH) << BIT_SHIFT_CH7_HIGH_TH)\n#define BITS_CH7_HIGH_TH (BIT_MASK_CH7_HIGH_TH << BIT_SHIFT_CH7_HIGH_TH)\n#define BIT_CLEAR_CH7_HIGH_TH(x) ((x) & (~BITS_CH7_HIGH_TH))\n#define BIT_GET_CH7_HIGH_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH7_HIGH_TH) & BIT_MASK_CH7_HIGH_TH)\n#define BIT_SET_CH7_HIGH_TH(x, v)                                              \\\n\t(BIT_CLEAR_CH7_HIGH_TH(x) | BIT_CH7_HIGH_TH(v))\n\n#define BIT_SHIFT_CH7_LOW_TH 0\n#define BIT_MASK_CH7_LOW_TH 0xfff\n#define BIT_CH7_LOW_TH(x) (((x) & BIT_MASK_CH7_LOW_TH) << BIT_SHIFT_CH7_LOW_TH)\n#define BITS_CH7_LOW_TH (BIT_MASK_CH7_LOW_TH << BIT_SHIFT_CH7_LOW_TH)\n#define BIT_CLEAR_CH7_LOW_TH(x) ((x) & (~BITS_CH7_LOW_TH))\n#define BIT_GET_CH7_LOW_TH(x)                                                  \\\n\t(((x) >> BIT_SHIFT_CH7_LOW_TH) & BIT_MASK_CH7_LOW_TH)\n#define BIT_SET_CH7_LOW_TH(x, v) (BIT_CLEAR_CH7_LOW_TH(x) | BIT_CH7_LOW_TH(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_8\t\t\t(Offset 0x3220) */\n\n#define BIT_CH8_INT_EN BIT(31)\n\n#define BIT_SHIFT_CH8_HIGH_TH 16\n#define BIT_MASK_CH8_HIGH_TH 0xfff\n#define BIT_CH8_HIGH_TH(x)                                                     \\\n\t(((x) & BIT_MASK_CH8_HIGH_TH) << BIT_SHIFT_CH8_HIGH_TH)\n#define BITS_CH8_HIGH_TH (BIT_MASK_CH8_HIGH_TH << BIT_SHIFT_CH8_HIGH_TH)\n#define BIT_CLEAR_CH8_HIGH_TH(x) ((x) & (~BITS_CH8_HIGH_TH))\n#define BIT_GET_CH8_HIGH_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH8_HIGH_TH) & BIT_MASK_CH8_HIGH_TH)\n#define BIT_SET_CH8_HIGH_TH(x, v)                                              \\\n\t(BIT_CLEAR_CH8_HIGH_TH(x) | BIT_CH8_HIGH_TH(v))\n\n#define BIT_SHIFT_CH8_LOW_TH 0\n#define BIT_MASK_CH8_LOW_TH 0xfff\n#define BIT_CH8_LOW_TH(x) (((x) & BIT_MASK_CH8_LOW_TH) << BIT_SHIFT_CH8_LOW_TH)\n#define BITS_CH8_LOW_TH (BIT_MASK_CH8_LOW_TH << BIT_SHIFT_CH8_LOW_TH)\n#define BIT_CLEAR_CH8_LOW_TH(x) ((x) & (~BITS_CH8_LOW_TH))\n#define BIT_GET_CH8_LOW_TH(x)                                                  \\\n\t(((x) >> BIT_SHIFT_CH8_LOW_TH) & BIT_MASK_CH8_LOW_TH)\n#define BIT_SET_CH8_LOW_TH(x, v) (BIT_CLEAR_CH8_LOW_TH(x) | BIT_CH8_LOW_TH(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_9\t\t\t(Offset 0x3224) */\n\n#define BIT_CH9_INT_EN BIT(31)\n\n#define BIT_SHIFT_CH9_HIGH_TH 16\n#define BIT_MASK_CH9_HIGH_TH 0xfff\n#define BIT_CH9_HIGH_TH(x)                                                     \\\n\t(((x) & BIT_MASK_CH9_HIGH_TH) << BIT_SHIFT_CH9_HIGH_TH)\n#define BITS_CH9_HIGH_TH (BIT_MASK_CH9_HIGH_TH << BIT_SHIFT_CH9_HIGH_TH)\n#define BIT_CLEAR_CH9_HIGH_TH(x) ((x) & (~BITS_CH9_HIGH_TH))\n#define BIT_GET_CH9_HIGH_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH9_HIGH_TH) & BIT_MASK_CH9_HIGH_TH)\n#define BIT_SET_CH9_HIGH_TH(x, v)                                              \\\n\t(BIT_CLEAR_CH9_HIGH_TH(x) | BIT_CH9_HIGH_TH(v))\n\n#define BIT_SHIFT_CH9_LOW_TH 0\n#define BIT_MASK_CH9_LOW_TH 0xfff\n#define BIT_CH9_LOW_TH(x) (((x) & BIT_MASK_CH9_LOW_TH) << BIT_SHIFT_CH9_LOW_TH)\n#define BITS_CH9_LOW_TH (BIT_MASK_CH9_LOW_TH << BIT_SHIFT_CH9_LOW_TH)\n#define BIT_CLEAR_CH9_LOW_TH(x) ((x) & (~BITS_CH9_LOW_TH))\n#define BIT_GET_CH9_LOW_TH(x)                                                  \\\n\t(((x) >> BIT_SHIFT_CH9_LOW_TH) & BIT_MASK_CH9_LOW_TH)\n#define BIT_SET_CH9_LOW_TH(x, v) (BIT_CLEAR_CH9_LOW_TH(x) | BIT_CH9_LOW_TH(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_10\t\t\t(Offset 0x3228) */\n\n#define BIT_CH10_INT_EN BIT(31)\n\n#define BIT_SHIFT_CH10_HIGH_TH 16\n#define BIT_MASK_CH10_HIGH_TH 0xfff\n#define BIT_CH10_HIGH_TH(x)                                                    \\\n\t(((x) & BIT_MASK_CH10_HIGH_TH) << BIT_SHIFT_CH10_HIGH_TH)\n#define BITS_CH10_HIGH_TH (BIT_MASK_CH10_HIGH_TH << BIT_SHIFT_CH10_HIGH_TH)\n#define BIT_CLEAR_CH10_HIGH_TH(x) ((x) & (~BITS_CH10_HIGH_TH))\n#define BIT_GET_CH10_HIGH_TH(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH10_HIGH_TH) & BIT_MASK_CH10_HIGH_TH)\n#define BIT_SET_CH10_HIGH_TH(x, v)                                             \\\n\t(BIT_CLEAR_CH10_HIGH_TH(x) | BIT_CH10_HIGH_TH(v))\n\n#define BIT_SHIFT_CH10_LOW_TH 0\n#define BIT_MASK_CH10_LOW_TH 0xfff\n#define BIT_CH10_LOW_TH(x)                                                     \\\n\t(((x) & BIT_MASK_CH10_LOW_TH) << BIT_SHIFT_CH10_LOW_TH)\n#define BITS_CH10_LOW_TH (BIT_MASK_CH10_LOW_TH << BIT_SHIFT_CH10_LOW_TH)\n#define BIT_CLEAR_CH10_LOW_TH(x) ((x) & (~BITS_CH10_LOW_TH))\n#define BIT_GET_CH10_LOW_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH10_LOW_TH) & BIT_MASK_CH10_LOW_TH)\n#define BIT_SET_CH10_LOW_TH(x, v)                                              \\\n\t(BIT_CLEAR_CH10_LOW_TH(x) | BIT_CH10_LOW_TH(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_11\t\t\t(Offset 0x322C) */\n\n#define BIT_CH11_INT_EN BIT(31)\n\n#define BIT_SHIFT_CH11_HIGH_TH 16\n#define BIT_MASK_CH11_HIGH_TH 0xfff\n#define BIT_CH11_HIGH_TH(x)                                                    \\\n\t(((x) & BIT_MASK_CH11_HIGH_TH) << BIT_SHIFT_CH11_HIGH_TH)\n#define BITS_CH11_HIGH_TH (BIT_MASK_CH11_HIGH_TH << BIT_SHIFT_CH11_HIGH_TH)\n#define BIT_CLEAR_CH11_HIGH_TH(x) ((x) & (~BITS_CH11_HIGH_TH))\n#define BIT_GET_CH11_HIGH_TH(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH11_HIGH_TH) & BIT_MASK_CH11_HIGH_TH)\n#define BIT_SET_CH11_HIGH_TH(x, v)                                             \\\n\t(BIT_CLEAR_CH11_HIGH_TH(x) | BIT_CH11_HIGH_TH(v))\n\n#define BIT_SHIFT_CH11_LOW_TH 0\n#define BIT_MASK_CH11_LOW_TH 0xfff\n#define BIT_CH11_LOW_TH(x)                                                     \\\n\t(((x) & BIT_MASK_CH11_LOW_TH) << BIT_SHIFT_CH11_LOW_TH)\n#define BITS_CH11_LOW_TH (BIT_MASK_CH11_LOW_TH << BIT_SHIFT_CH11_LOW_TH)\n#define BIT_CLEAR_CH11_LOW_TH(x) ((x) & (~BITS_CH11_LOW_TH))\n#define BIT_GET_CH11_LOW_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH11_LOW_TH) & BIT_MASK_CH11_LOW_TH)\n#define BIT_SET_CH11_LOW_TH(x, v)                                              \\\n\t(BIT_CLEAR_CH11_LOW_TH(x) | BIT_CH11_LOW_TH(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_12\t\t\t(Offset 0x3230) */\n\n#define BIT_CH12_INT_EN BIT(31)\n\n#define BIT_SHIFT_CH12_HIGH_TH 16\n#define BIT_MASK_CH12_HIGH_TH 0xfff\n#define BIT_CH12_HIGH_TH(x)                                                    \\\n\t(((x) & BIT_MASK_CH12_HIGH_TH) << BIT_SHIFT_CH12_HIGH_TH)\n#define BITS_CH12_HIGH_TH (BIT_MASK_CH12_HIGH_TH << BIT_SHIFT_CH12_HIGH_TH)\n#define BIT_CLEAR_CH12_HIGH_TH(x) ((x) & (~BITS_CH12_HIGH_TH))\n#define BIT_GET_CH12_HIGH_TH(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH12_HIGH_TH) & BIT_MASK_CH12_HIGH_TH)\n#define BIT_SET_CH12_HIGH_TH(x, v)                                             \\\n\t(BIT_CLEAR_CH12_HIGH_TH(x) | BIT_CH12_HIGH_TH(v))\n\n#define BIT_SHIFT_CH12_LOW_TH 0\n#define BIT_MASK_CH12_LOW_TH 0xfff\n#define BIT_CH12_LOW_TH(x)                                                     \\\n\t(((x) & BIT_MASK_CH12_LOW_TH) << BIT_SHIFT_CH12_LOW_TH)\n#define BITS_CH12_LOW_TH (BIT_MASK_CH12_LOW_TH << BIT_SHIFT_CH12_LOW_TH)\n#define BIT_CLEAR_CH12_LOW_TH(x) ((x) & (~BITS_CH12_LOW_TH))\n#define BIT_GET_CH12_LOW_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH12_LOW_TH) & BIT_MASK_CH12_LOW_TH)\n#define BIT_SET_CH12_LOW_TH(x, v)                                              \\\n\t(BIT_CLEAR_CH12_LOW_TH(x) | BIT_CH12_LOW_TH(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_13\t\t\t(Offset 0x3234) */\n\n#define BIT_CH13_INT_EN BIT(31)\n\n#define BIT_SHIFT_CH13_HIGH_TH 16\n#define BIT_MASK_CH13_HIGH_TH 0xfff\n#define BIT_CH13_HIGH_TH(x)                                                    \\\n\t(((x) & BIT_MASK_CH13_HIGH_TH) << BIT_SHIFT_CH13_HIGH_TH)\n#define BITS_CH13_HIGH_TH (BIT_MASK_CH13_HIGH_TH << BIT_SHIFT_CH13_HIGH_TH)\n#define BIT_CLEAR_CH13_HIGH_TH(x) ((x) & (~BITS_CH13_HIGH_TH))\n#define BIT_GET_CH13_HIGH_TH(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH13_HIGH_TH) & BIT_MASK_CH13_HIGH_TH)\n#define BIT_SET_CH13_HIGH_TH(x, v)                                             \\\n\t(BIT_CLEAR_CH13_HIGH_TH(x) | BIT_CH13_HIGH_TH(v))\n\n#define BIT_SHIFT_CH13_LOW_TH 0\n#define BIT_MASK_CH13_LOW_TH 0xfff\n#define BIT_CH13_LOW_TH(x)                                                     \\\n\t(((x) & BIT_MASK_CH13_LOW_TH) << BIT_SHIFT_CH13_LOW_TH)\n#define BITS_CH13_LOW_TH (BIT_MASK_CH13_LOW_TH << BIT_SHIFT_CH13_LOW_TH)\n#define BIT_CLEAR_CH13_LOW_TH(x) ((x) & (~BITS_CH13_LOW_TH))\n#define BIT_GET_CH13_LOW_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH13_LOW_TH) & BIT_MASK_CH13_LOW_TH)\n#define BIT_SET_CH13_LOW_TH(x, v)                                              \\\n\t(BIT_CLEAR_CH13_LOW_TH(x) | BIT_CH13_LOW_TH(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_14\t\t\t(Offset 0x3238) */\n\n#define BIT_CH14_INT_EN BIT(31)\n\n#define BIT_SHIFT_CH14_HIGH_TH 16\n#define BIT_MASK_CH14_HIGH_TH 0xfff\n#define BIT_CH14_HIGH_TH(x)                                                    \\\n\t(((x) & BIT_MASK_CH14_HIGH_TH) << BIT_SHIFT_CH14_HIGH_TH)\n#define BITS_CH14_HIGH_TH (BIT_MASK_CH14_HIGH_TH << BIT_SHIFT_CH14_HIGH_TH)\n#define BIT_CLEAR_CH14_HIGH_TH(x) ((x) & (~BITS_CH14_HIGH_TH))\n#define BIT_GET_CH14_HIGH_TH(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH14_HIGH_TH) & BIT_MASK_CH14_HIGH_TH)\n#define BIT_SET_CH14_HIGH_TH(x, v)                                             \\\n\t(BIT_CLEAR_CH14_HIGH_TH(x) | BIT_CH14_HIGH_TH(v))\n\n#define BIT_SHIFT_CH14_LOW_TH 0\n#define BIT_MASK_CH14_LOW_TH 0xfff\n#define BIT_CH14_LOW_TH(x)                                                     \\\n\t(((x) & BIT_MASK_CH14_LOW_TH) << BIT_SHIFT_CH14_LOW_TH)\n#define BITS_CH14_LOW_TH (BIT_MASK_CH14_LOW_TH << BIT_SHIFT_CH14_LOW_TH)\n#define BIT_CLEAR_CH14_LOW_TH(x) ((x) & (~BITS_CH14_LOW_TH))\n#define BIT_GET_CH14_LOW_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH14_LOW_TH) & BIT_MASK_CH14_LOW_TH)\n#define BIT_SET_CH14_LOW_TH(x, v)                                              \\\n\t(BIT_CLEAR_CH14_LOW_TH(x) | BIT_CH14_LOW_TH(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_15\t\t\t(Offset 0x323C) */\n\n#define BIT_CH15_INT_EN BIT(31)\n\n#define BIT_SHIFT_CH15_HIGH_TH 16\n#define BIT_MASK_CH15_HIGH_TH 0xfff\n#define BIT_CH15_HIGH_TH(x)                                                    \\\n\t(((x) & BIT_MASK_CH15_HIGH_TH) << BIT_SHIFT_CH15_HIGH_TH)\n#define BITS_CH15_HIGH_TH (BIT_MASK_CH15_HIGH_TH << BIT_SHIFT_CH15_HIGH_TH)\n#define BIT_CLEAR_CH15_HIGH_TH(x) ((x) & (~BITS_CH15_HIGH_TH))\n#define BIT_GET_CH15_HIGH_TH(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH15_HIGH_TH) & BIT_MASK_CH15_HIGH_TH)\n#define BIT_SET_CH15_HIGH_TH(x, v)                                             \\\n\t(BIT_CLEAR_CH15_HIGH_TH(x) | BIT_CH15_HIGH_TH(v))\n\n#define BIT_SHIFT_CH15_LOW_TH 0\n#define BIT_MASK_CH15_LOW_TH 0xfff\n#define BIT_CH15_LOW_TH(x)                                                     \\\n\t(((x) & BIT_MASK_CH15_LOW_TH) << BIT_SHIFT_CH15_LOW_TH)\n#define BITS_CH15_LOW_TH (BIT_MASK_CH15_LOW_TH << BIT_SHIFT_CH15_LOW_TH)\n#define BIT_CLEAR_CH15_LOW_TH(x) ((x) & (~BITS_CH15_LOW_TH))\n#define BIT_GET_CH15_LOW_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH15_LOW_TH) & BIT_MASK_CH15_LOW_TH)\n#define BIT_SET_CH15_LOW_TH(x, v)                                              \\\n\t(BIT_CLEAR_CH15_LOW_TH(x) | BIT_CH15_LOW_TH(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_16\t\t\t(Offset 0x3240) */\n\n#define BIT_CH16_INT_EN BIT(31)\n\n#define BIT_SHIFT_CH16_HIGH_TH 16\n#define BIT_MASK_CH16_HIGH_TH 0xfff\n#define BIT_CH16_HIGH_TH(x)                                                    \\\n\t(((x) & BIT_MASK_CH16_HIGH_TH) << BIT_SHIFT_CH16_HIGH_TH)\n#define BITS_CH16_HIGH_TH (BIT_MASK_CH16_HIGH_TH << BIT_SHIFT_CH16_HIGH_TH)\n#define BIT_CLEAR_CH16_HIGH_TH(x) ((x) & (~BITS_CH16_HIGH_TH))\n#define BIT_GET_CH16_HIGH_TH(x)                                                \\\n\t(((x) >> BIT_SHIFT_CH16_HIGH_TH) & BIT_MASK_CH16_HIGH_TH)\n#define BIT_SET_CH16_HIGH_TH(x, v)                                             \\\n\t(BIT_CLEAR_CH16_HIGH_TH(x) | BIT_CH16_HIGH_TH(v))\n\n#define BIT_SHIFT_CH16_LOW_TH 0\n#define BIT_MASK_CH16_LOW_TH 0xfff\n#define BIT_CH16_LOW_TH(x)                                                     \\\n\t(((x) & BIT_MASK_CH16_LOW_TH) << BIT_SHIFT_CH16_LOW_TH)\n#define BITS_CH16_LOW_TH (BIT_MASK_CH16_LOW_TH << BIT_SHIFT_CH16_LOW_TH)\n#define BIT_CLEAR_CH16_LOW_TH(x) ((x) & (~BITS_CH16_LOW_TH))\n#define BIT_GET_CH16_LOW_TH(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CH16_LOW_TH) & BIT_MASK_CH16_LOW_TH)\n#define BIT_SET_CH16_LOW_TH(x, v)                                              \\\n\t(BIT_CLEAR_CH16_LOW_TH(x) | BIT_CH16_LOW_TH(v))\n\n/* 2 REG_ACH4_TXBD_IDX\t\t\t(Offset 0x3340) */\n\n#define BIT_SHIFT_ACH4_HW_IDX 16\n#define BIT_MASK_ACH4_HW_IDX 0xfff\n#define BIT_ACH4_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_ACH4_HW_IDX) << BIT_SHIFT_ACH4_HW_IDX)\n#define BITS_ACH4_HW_IDX (BIT_MASK_ACH4_HW_IDX << BIT_SHIFT_ACH4_HW_IDX)\n#define BIT_CLEAR_ACH4_HW_IDX(x) ((x) & (~BITS_ACH4_HW_IDX))\n#define BIT_GET_ACH4_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ACH4_HW_IDX) & BIT_MASK_ACH4_HW_IDX)\n#define BIT_SET_ACH4_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_ACH4_HW_IDX(x) | BIT_ACH4_HW_IDX(v))\n\n#define BIT_SHIFT_ACH4_HOST_IDX 0\n#define BIT_MASK_ACH4_HOST_IDX 0xfff\n#define BIT_ACH4_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_ACH4_HOST_IDX) << BIT_SHIFT_ACH4_HOST_IDX)\n#define BITS_ACH4_HOST_IDX (BIT_MASK_ACH4_HOST_IDX << BIT_SHIFT_ACH4_HOST_IDX)\n#define BIT_CLEAR_ACH4_HOST_IDX(x) ((x) & (~BITS_ACH4_HOST_IDX))\n#define BIT_GET_ACH4_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH4_HOST_IDX) & BIT_MASK_ACH4_HOST_IDX)\n#define BIT_SET_ACH4_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_ACH4_HOST_IDX(x) | BIT_ACH4_HOST_IDX(v))\n\n/* 2 REG_ACH5_TXBD_IDX\t\t\t(Offset 0x3344) */\n\n#define BIT_SHIFT_ACH5_HW_IDX 16\n#define BIT_MASK_ACH5_HW_IDX 0xfff\n#define BIT_ACH5_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_ACH5_HW_IDX) << BIT_SHIFT_ACH5_HW_IDX)\n#define BITS_ACH5_HW_IDX (BIT_MASK_ACH5_HW_IDX << BIT_SHIFT_ACH5_HW_IDX)\n#define BIT_CLEAR_ACH5_HW_IDX(x) ((x) & (~BITS_ACH5_HW_IDX))\n#define BIT_GET_ACH5_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ACH5_HW_IDX) & BIT_MASK_ACH5_HW_IDX)\n#define BIT_SET_ACH5_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_ACH5_HW_IDX(x) | BIT_ACH5_HW_IDX(v))\n\n#define BIT_SHIFT_ACH5_HOST_IDX 0\n#define BIT_MASK_ACH5_HOST_IDX 0xfff\n#define BIT_ACH5_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_ACH5_HOST_IDX) << BIT_SHIFT_ACH5_HOST_IDX)\n#define BITS_ACH5_HOST_IDX (BIT_MASK_ACH5_HOST_IDX << BIT_SHIFT_ACH5_HOST_IDX)\n#define BIT_CLEAR_ACH5_HOST_IDX(x) ((x) & (~BITS_ACH5_HOST_IDX))\n#define BIT_GET_ACH5_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH5_HOST_IDX) & BIT_MASK_ACH5_HOST_IDX)\n#define BIT_SET_ACH5_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_ACH5_HOST_IDX(x) | BIT_ACH5_HOST_IDX(v))\n\n/* 2 REG_ACH6_TXBD_IDX\t\t\t(Offset 0x3348) */\n\n#define BIT_SHIFT_ACH6_HW_IDX 16\n#define BIT_MASK_ACH6_HW_IDX 0xfff\n#define BIT_ACH6_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_ACH6_HW_IDX) << BIT_SHIFT_ACH6_HW_IDX)\n#define BITS_ACH6_HW_IDX (BIT_MASK_ACH6_HW_IDX << BIT_SHIFT_ACH6_HW_IDX)\n#define BIT_CLEAR_ACH6_HW_IDX(x) ((x) & (~BITS_ACH6_HW_IDX))\n#define BIT_GET_ACH6_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ACH6_HW_IDX) & BIT_MASK_ACH6_HW_IDX)\n#define BIT_SET_ACH6_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_ACH6_HW_IDX(x) | BIT_ACH6_HW_IDX(v))\n\n#define BIT_SHIFT_ACH6_HOST_IDX 0\n#define BIT_MASK_ACH6_HOST_IDX 0xfff\n#define BIT_ACH6_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_ACH6_HOST_IDX) << BIT_SHIFT_ACH6_HOST_IDX)\n#define BITS_ACH6_HOST_IDX (BIT_MASK_ACH6_HOST_IDX << BIT_SHIFT_ACH6_HOST_IDX)\n#define BIT_CLEAR_ACH6_HOST_IDX(x) ((x) & (~BITS_ACH6_HOST_IDX))\n#define BIT_GET_ACH6_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH6_HOST_IDX) & BIT_MASK_ACH6_HOST_IDX)\n#define BIT_SET_ACH6_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_ACH6_HOST_IDX(x) | BIT_ACH6_HOST_IDX(v))\n\n/* 2 REG_ACH7_TXBD_IDX\t\t\t(Offset 0x334C) */\n\n#define BIT_SHIFT_ACH7_HW_IDX 16\n#define BIT_MASK_ACH7_HW_IDX 0xfff\n#define BIT_ACH7_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_ACH7_HW_IDX) << BIT_SHIFT_ACH7_HW_IDX)\n#define BITS_ACH7_HW_IDX (BIT_MASK_ACH7_HW_IDX << BIT_SHIFT_ACH7_HW_IDX)\n#define BIT_CLEAR_ACH7_HW_IDX(x) ((x) & (~BITS_ACH7_HW_IDX))\n#define BIT_GET_ACH7_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ACH7_HW_IDX) & BIT_MASK_ACH7_HW_IDX)\n#define BIT_SET_ACH7_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_ACH7_HW_IDX(x) | BIT_ACH7_HW_IDX(v))\n\n#define BIT_SHIFT_ACH7_HOST_IDX 0\n#define BIT_MASK_ACH7_HOST_IDX 0xfff\n#define BIT_ACH7_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_ACH7_HOST_IDX) << BIT_SHIFT_ACH7_HOST_IDX)\n#define BITS_ACH7_HOST_IDX (BIT_MASK_ACH7_HOST_IDX << BIT_SHIFT_ACH7_HOST_IDX)\n#define BIT_CLEAR_ACH7_HOST_IDX(x) ((x) & (~BITS_ACH7_HOST_IDX))\n#define BIT_GET_ACH7_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH7_HOST_IDX) & BIT_MASK_ACH7_HOST_IDX)\n#define BIT_SET_ACH7_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_ACH7_HOST_IDX(x) | BIT_ACH7_HOST_IDX(v))\n\n/* 2 REG_ACH8_TXBD_IDX\t\t\t(Offset 0x3350) */\n\n#define BIT_SHIFT_ACH8_HW_IDX 16\n#define BIT_MASK_ACH8_HW_IDX 0xfff\n#define BIT_ACH8_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_ACH8_HW_IDX) << BIT_SHIFT_ACH8_HW_IDX)\n#define BITS_ACH8_HW_IDX (BIT_MASK_ACH8_HW_IDX << BIT_SHIFT_ACH8_HW_IDX)\n#define BIT_CLEAR_ACH8_HW_IDX(x) ((x) & (~BITS_ACH8_HW_IDX))\n#define BIT_GET_ACH8_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ACH8_HW_IDX) & BIT_MASK_ACH8_HW_IDX)\n#define BIT_SET_ACH8_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_ACH8_HW_IDX(x) | BIT_ACH8_HW_IDX(v))\n\n#define BIT_SHIFT_ACH8_HOST_IDX 0\n#define BIT_MASK_ACH8_HOST_IDX 0xfff\n#define BIT_ACH8_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_ACH8_HOST_IDX) << BIT_SHIFT_ACH8_HOST_IDX)\n#define BITS_ACH8_HOST_IDX (BIT_MASK_ACH8_HOST_IDX << BIT_SHIFT_ACH8_HOST_IDX)\n#define BIT_CLEAR_ACH8_HOST_IDX(x) ((x) & (~BITS_ACH8_HOST_IDX))\n#define BIT_GET_ACH8_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH8_HOST_IDX) & BIT_MASK_ACH8_HOST_IDX)\n#define BIT_SET_ACH8_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_ACH8_HOST_IDX(x) | BIT_ACH8_HOST_IDX(v))\n\n/* 2 REG_ACH9_TXBD_IDX\t\t\t(Offset 0x3354) */\n\n#define BIT_SHIFT_ACH9_HW_IDX 16\n#define BIT_MASK_ACH9_HW_IDX 0xfff\n#define BIT_ACH9_HW_IDX(x)                                                     \\\n\t(((x) & BIT_MASK_ACH9_HW_IDX) << BIT_SHIFT_ACH9_HW_IDX)\n#define BITS_ACH9_HW_IDX (BIT_MASK_ACH9_HW_IDX << BIT_SHIFT_ACH9_HW_IDX)\n#define BIT_CLEAR_ACH9_HW_IDX(x) ((x) & (~BITS_ACH9_HW_IDX))\n#define BIT_GET_ACH9_HW_IDX(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ACH9_HW_IDX) & BIT_MASK_ACH9_HW_IDX)\n#define BIT_SET_ACH9_HW_IDX(x, v)                                              \\\n\t(BIT_CLEAR_ACH9_HW_IDX(x) | BIT_ACH9_HW_IDX(v))\n\n#define BIT_SHIFT_ACH9_HOST_IDX 0\n#define BIT_MASK_ACH9_HOST_IDX 0xfff\n#define BIT_ACH9_HOST_IDX(x)                                                   \\\n\t(((x) & BIT_MASK_ACH9_HOST_IDX) << BIT_SHIFT_ACH9_HOST_IDX)\n#define BITS_ACH9_HOST_IDX (BIT_MASK_ACH9_HOST_IDX << BIT_SHIFT_ACH9_HOST_IDX)\n#define BIT_CLEAR_ACH9_HOST_IDX(x) ((x) & (~BITS_ACH9_HOST_IDX))\n#define BIT_GET_ACH9_HOST_IDX(x)                                               \\\n\t(((x) >> BIT_SHIFT_ACH9_HOST_IDX) & BIT_MASK_ACH9_HOST_IDX)\n#define BIT_SET_ACH9_HOST_IDX(x, v)                                            \\\n\t(BIT_CLEAR_ACH9_HOST_IDX(x) | BIT_ACH9_HOST_IDX(v))\n\n/* 2 REG_ACH10_TXBD_IDX\t\t\t(Offset 0x3358) */\n\n#define BIT_SHIFT_ACH10_HW_IDX 16\n#define BIT_MASK_ACH10_HW_IDX 0xfff\n#define BIT_ACH10_HW_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_ACH10_HW_IDX) << BIT_SHIFT_ACH10_HW_IDX)\n#define BITS_ACH10_HW_IDX (BIT_MASK_ACH10_HW_IDX << BIT_SHIFT_ACH10_HW_IDX)\n#define BIT_CLEAR_ACH10_HW_IDX(x) ((x) & (~BITS_ACH10_HW_IDX))\n#define BIT_GET_ACH10_HW_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_ACH10_HW_IDX) & BIT_MASK_ACH10_HW_IDX)\n#define BIT_SET_ACH10_HW_IDX(x, v)                                             \\\n\t(BIT_CLEAR_ACH10_HW_IDX(x) | BIT_ACH10_HW_IDX(v))\n\n#define BIT_SHIFT_ACH10_HOST_IDX 0\n#define BIT_MASK_ACH10_HOST_IDX 0xfff\n#define BIT_ACH10_HOST_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_ACH10_HOST_IDX) << BIT_SHIFT_ACH10_HOST_IDX)\n#define BITS_ACH10_HOST_IDX                                                    \\\n\t(BIT_MASK_ACH10_HOST_IDX << BIT_SHIFT_ACH10_HOST_IDX)\n#define BIT_CLEAR_ACH10_HOST_IDX(x) ((x) & (~BITS_ACH10_HOST_IDX))\n#define BIT_GET_ACH10_HOST_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_ACH10_HOST_IDX) & BIT_MASK_ACH10_HOST_IDX)\n#define BIT_SET_ACH10_HOST_IDX(x, v)                                           \\\n\t(BIT_CLEAR_ACH10_HOST_IDX(x) | BIT_ACH10_HOST_IDX(v))\n\n/* 2 REG_ACH11_TXBD_IDX\t\t\t(Offset 0x335C) */\n\n#define BIT_SHIFT_ACH11_HW_IDX 16\n#define BIT_MASK_ACH11_HW_IDX 0xfff\n#define BIT_ACH11_HW_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_ACH11_HW_IDX) << BIT_SHIFT_ACH11_HW_IDX)\n#define BITS_ACH11_HW_IDX (BIT_MASK_ACH11_HW_IDX << BIT_SHIFT_ACH11_HW_IDX)\n#define BIT_CLEAR_ACH11_HW_IDX(x) ((x) & (~BITS_ACH11_HW_IDX))\n#define BIT_GET_ACH11_HW_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_ACH11_HW_IDX) & BIT_MASK_ACH11_HW_IDX)\n#define BIT_SET_ACH11_HW_IDX(x, v)                                             \\\n\t(BIT_CLEAR_ACH11_HW_IDX(x) | BIT_ACH11_HW_IDX(v))\n\n#define BIT_SHIFT_ACH11_HOST_IDX 0\n#define BIT_MASK_ACH11_HOST_IDX 0xfff\n#define BIT_ACH11_HOST_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_ACH11_HOST_IDX) << BIT_SHIFT_ACH11_HOST_IDX)\n#define BITS_ACH11_HOST_IDX                                                    \\\n\t(BIT_MASK_ACH11_HOST_IDX << BIT_SHIFT_ACH11_HOST_IDX)\n#define BIT_CLEAR_ACH11_HOST_IDX(x) ((x) & (~BITS_ACH11_HOST_IDX))\n#define BIT_GET_ACH11_HOST_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_ACH11_HOST_IDX) & BIT_MASK_ACH11_HOST_IDX)\n#define BIT_SET_ACH11_HOST_IDX(x, v)                                           \\\n\t(BIT_CLEAR_ACH11_HOST_IDX(x) | BIT_ACH11_HOST_IDX(v))\n\n/* 2 REG_ACH12_TXBD_IDX\t\t\t(Offset 0x3360) */\n\n#define BIT_SHIFT_ACH12_HW_IDX 16\n#define BIT_MASK_ACH12_HW_IDX 0xfff\n#define BIT_ACH12_HW_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_ACH12_HW_IDX) << BIT_SHIFT_ACH12_HW_IDX)\n#define BITS_ACH12_HW_IDX (BIT_MASK_ACH12_HW_IDX << BIT_SHIFT_ACH12_HW_IDX)\n#define BIT_CLEAR_ACH12_HW_IDX(x) ((x) & (~BITS_ACH12_HW_IDX))\n#define BIT_GET_ACH12_HW_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_ACH12_HW_IDX) & BIT_MASK_ACH12_HW_IDX)\n#define BIT_SET_ACH12_HW_IDX(x, v)                                             \\\n\t(BIT_CLEAR_ACH12_HW_IDX(x) | BIT_ACH12_HW_IDX(v))\n\n#define BIT_SHIFT_ACH12_HOST_IDX 0\n#define BIT_MASK_ACH12_HOST_IDX 0xfff\n#define BIT_ACH12_HOST_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_ACH12_HOST_IDX) << BIT_SHIFT_ACH12_HOST_IDX)\n#define BITS_ACH12_HOST_IDX                                                    \\\n\t(BIT_MASK_ACH12_HOST_IDX << BIT_SHIFT_ACH12_HOST_IDX)\n#define BIT_CLEAR_ACH12_HOST_IDX(x) ((x) & (~BITS_ACH12_HOST_IDX))\n#define BIT_GET_ACH12_HOST_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_ACH12_HOST_IDX) & BIT_MASK_ACH12_HOST_IDX)\n#define BIT_SET_ACH12_HOST_IDX(x, v)                                           \\\n\t(BIT_CLEAR_ACH12_HOST_IDX(x) | BIT_ACH12_HOST_IDX(v))\n\n/* 2 REG_ACH13_TXBD_IDX\t\t\t(Offset 0x3364) */\n\n#define BIT_SHIFT_ACH13_HW_IDX 16\n#define BIT_MASK_ACH13_HW_IDX 0xfff\n#define BIT_ACH13_HW_IDX(x)                                                    \\\n\t(((x) & BIT_MASK_ACH13_HW_IDX) << BIT_SHIFT_ACH13_HW_IDX)\n#define BITS_ACH13_HW_IDX (BIT_MASK_ACH13_HW_IDX << BIT_SHIFT_ACH13_HW_IDX)\n#define BIT_CLEAR_ACH13_HW_IDX(x) ((x) & (~BITS_ACH13_HW_IDX))\n#define BIT_GET_ACH13_HW_IDX(x)                                                \\\n\t(((x) >> BIT_SHIFT_ACH13_HW_IDX) & BIT_MASK_ACH13_HW_IDX)\n#define BIT_SET_ACH13_HW_IDX(x, v)                                             \\\n\t(BIT_CLEAR_ACH13_HW_IDX(x) | BIT_ACH13_HW_IDX(v))\n\n#define BIT_SHIFT_ACH13_HOST_IDX 0\n#define BIT_MASK_ACH13_HOST_IDX 0xfff\n#define BIT_ACH13_HOST_IDX(x)                                                  \\\n\t(((x) & BIT_MASK_ACH13_HOST_IDX) << BIT_SHIFT_ACH13_HOST_IDX)\n#define BITS_ACH13_HOST_IDX                                                    \\\n\t(BIT_MASK_ACH13_HOST_IDX << BIT_SHIFT_ACH13_HOST_IDX)\n#define BIT_CLEAR_ACH13_HOST_IDX(x) ((x) & (~BITS_ACH13_HOST_IDX))\n#define BIT_GET_ACH13_HOST_IDX(x)                                              \\\n\t(((x) >> BIT_SHIFT_ACH13_HOST_IDX) & BIT_MASK_ACH13_HOST_IDX)\n#define BIT_SET_ACH13_HOST_IDX(x, v)                                           \\\n\t(BIT_CLEAR_ACH13_HOST_IDX(x) | BIT_ACH13_HOST_IDX(v))\n\n/* 2 REG_AC_CHANNEL0_WEIGHT\t\t\t(Offset 0x3368) */\n\n#define BIT_SHIFT_AC_CHANNEL0_WEIGHT 0\n#define BIT_MASK_AC_CHANNEL0_WEIGHT 0xff\n#define BIT_AC_CHANNEL0_WEIGHT(x)                                              \\\n\t(((x) & BIT_MASK_AC_CHANNEL0_WEIGHT) << BIT_SHIFT_AC_CHANNEL0_WEIGHT)\n#define BITS_AC_CHANNEL0_WEIGHT                                                \\\n\t(BIT_MASK_AC_CHANNEL0_WEIGHT << BIT_SHIFT_AC_CHANNEL0_WEIGHT)\n#define BIT_CLEAR_AC_CHANNEL0_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL0_WEIGHT))\n#define BIT_GET_AC_CHANNEL0_WEIGHT(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL0_WEIGHT) & BIT_MASK_AC_CHANNEL0_WEIGHT)\n#define BIT_SET_AC_CHANNEL0_WEIGHT(x, v)                                       \\\n\t(BIT_CLEAR_AC_CHANNEL0_WEIGHT(x) | BIT_AC_CHANNEL0_WEIGHT(v))\n\n/* 2 REG_AC_CHANNEL1_WEIGHT\t\t\t(Offset 0x3369) */\n\n#define BIT_SHIFT_AC_CHANNEL1_WEIGHT 0\n#define BIT_MASK_AC_CHANNEL1_WEIGHT 0xff\n#define BIT_AC_CHANNEL1_WEIGHT(x)                                              \\\n\t(((x) & BIT_MASK_AC_CHANNEL1_WEIGHT) << BIT_SHIFT_AC_CHANNEL1_WEIGHT)\n#define BITS_AC_CHANNEL1_WEIGHT                                                \\\n\t(BIT_MASK_AC_CHANNEL1_WEIGHT << BIT_SHIFT_AC_CHANNEL1_WEIGHT)\n#define BIT_CLEAR_AC_CHANNEL1_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL1_WEIGHT))\n#define BIT_GET_AC_CHANNEL1_WEIGHT(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL1_WEIGHT) & BIT_MASK_AC_CHANNEL1_WEIGHT)\n#define BIT_SET_AC_CHANNEL1_WEIGHT(x, v)                                       \\\n\t(BIT_CLEAR_AC_CHANNEL1_WEIGHT(x) | BIT_AC_CHANNEL1_WEIGHT(v))\n\n/* 2 REG_AC_CHANNEL2_WEIGHT\t\t\t(Offset 0x336A) */\n\n#define BIT_SHIFT_AC_CHANNEL2_WEIGHT 0\n#define BIT_MASK_AC_CHANNEL2_WEIGHT 0xff\n#define BIT_AC_CHANNEL2_WEIGHT(x)                                              \\\n\t(((x) & BIT_MASK_AC_CHANNEL2_WEIGHT) << BIT_SHIFT_AC_CHANNEL2_WEIGHT)\n#define BITS_AC_CHANNEL2_WEIGHT                                                \\\n\t(BIT_MASK_AC_CHANNEL2_WEIGHT << BIT_SHIFT_AC_CHANNEL2_WEIGHT)\n#define BIT_CLEAR_AC_CHANNEL2_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL2_WEIGHT))\n#define BIT_GET_AC_CHANNEL2_WEIGHT(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL2_WEIGHT) & BIT_MASK_AC_CHANNEL2_WEIGHT)\n#define BIT_SET_AC_CHANNEL2_WEIGHT(x, v)                                       \\\n\t(BIT_CLEAR_AC_CHANNEL2_WEIGHT(x) | BIT_AC_CHANNEL2_WEIGHT(v))\n\n/* 2 REG_AC_CHANNEL3_WEIGHT\t\t\t(Offset 0x336B) */\n\n#define BIT_SHIFT_AC_CHANNEL3_WEIGHT 0\n#define BIT_MASK_AC_CHANNEL3_WEIGHT 0xff\n#define BIT_AC_CHANNEL3_WEIGHT(x)                                              \\\n\t(((x) & BIT_MASK_AC_CHANNEL3_WEIGHT) << BIT_SHIFT_AC_CHANNEL3_WEIGHT)\n#define BITS_AC_CHANNEL3_WEIGHT                                                \\\n\t(BIT_MASK_AC_CHANNEL3_WEIGHT << BIT_SHIFT_AC_CHANNEL3_WEIGHT)\n#define BIT_CLEAR_AC_CHANNEL3_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL3_WEIGHT))\n#define BIT_GET_AC_CHANNEL3_WEIGHT(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL3_WEIGHT) & BIT_MASK_AC_CHANNEL3_WEIGHT)\n#define BIT_SET_AC_CHANNEL3_WEIGHT(x, v)                                       \\\n\t(BIT_CLEAR_AC_CHANNEL3_WEIGHT(x) | BIT_AC_CHANNEL3_WEIGHT(v))\n\n/* 2 REG_AC_CHANNEL4_WEIGHT\t\t\t(Offset 0x336C) */\n\n#define BIT_SHIFT_AC_CHANNEL4_WEIGHT 0\n#define BIT_MASK_AC_CHANNEL4_WEIGHT 0xff\n#define BIT_AC_CHANNEL4_WEIGHT(x)                                              \\\n\t(((x) & BIT_MASK_AC_CHANNEL4_WEIGHT) << BIT_SHIFT_AC_CHANNEL4_WEIGHT)\n#define BITS_AC_CHANNEL4_WEIGHT                                                \\\n\t(BIT_MASK_AC_CHANNEL4_WEIGHT << BIT_SHIFT_AC_CHANNEL4_WEIGHT)\n#define BIT_CLEAR_AC_CHANNEL4_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL4_WEIGHT))\n#define BIT_GET_AC_CHANNEL4_WEIGHT(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL4_WEIGHT) & BIT_MASK_AC_CHANNEL4_WEIGHT)\n#define BIT_SET_AC_CHANNEL4_WEIGHT(x, v)                                       \\\n\t(BIT_CLEAR_AC_CHANNEL4_WEIGHT(x) | BIT_AC_CHANNEL4_WEIGHT(v))\n\n/* 2 REG_AC_CHANNEL5_WEIGHT\t\t\t(Offset 0x336D) */\n\n#define BIT_SHIFT_AC_CHANNEL5_WEIGHT 0\n#define BIT_MASK_AC_CHANNEL5_WEIGHT 0xff\n#define BIT_AC_CHANNEL5_WEIGHT(x)                                              \\\n\t(((x) & BIT_MASK_AC_CHANNEL5_WEIGHT) << BIT_SHIFT_AC_CHANNEL5_WEIGHT)\n#define BITS_AC_CHANNEL5_WEIGHT                                                \\\n\t(BIT_MASK_AC_CHANNEL5_WEIGHT << BIT_SHIFT_AC_CHANNEL5_WEIGHT)\n#define BIT_CLEAR_AC_CHANNEL5_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL5_WEIGHT))\n#define BIT_GET_AC_CHANNEL5_WEIGHT(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL5_WEIGHT) & BIT_MASK_AC_CHANNEL5_WEIGHT)\n#define BIT_SET_AC_CHANNEL5_WEIGHT(x, v)                                       \\\n\t(BIT_CLEAR_AC_CHANNEL5_WEIGHT(x) | BIT_AC_CHANNEL5_WEIGHT(v))\n\n/* 2 REG_AC_CHANNEL6_WEIGHT\t\t\t(Offset 0x336E) */\n\n#define BIT_SHIFT_AC_CHANNEL6_WEIGHT 0\n#define BIT_MASK_AC_CHANNEL6_WEIGHT 0xff\n#define BIT_AC_CHANNEL6_WEIGHT(x)                                              \\\n\t(((x) & BIT_MASK_AC_CHANNEL6_WEIGHT) << BIT_SHIFT_AC_CHANNEL6_WEIGHT)\n#define BITS_AC_CHANNEL6_WEIGHT                                                \\\n\t(BIT_MASK_AC_CHANNEL6_WEIGHT << BIT_SHIFT_AC_CHANNEL6_WEIGHT)\n#define BIT_CLEAR_AC_CHANNEL6_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL6_WEIGHT))\n#define BIT_GET_AC_CHANNEL6_WEIGHT(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL6_WEIGHT) & BIT_MASK_AC_CHANNEL6_WEIGHT)\n#define BIT_SET_AC_CHANNEL6_WEIGHT(x, v)                                       \\\n\t(BIT_CLEAR_AC_CHANNEL6_WEIGHT(x) | BIT_AC_CHANNEL6_WEIGHT(v))\n\n/* 2 REG_AC_CHANNEL7_WEIGHT\t\t\t(Offset 0x336F) */\n\n#define BIT_SHIFT_AC_CHANNEL7_WEIGHT 0\n#define BIT_MASK_AC_CHANNEL7_WEIGHT 0xff\n#define BIT_AC_CHANNEL7_WEIGHT(x)                                              \\\n\t(((x) & BIT_MASK_AC_CHANNEL7_WEIGHT) << BIT_SHIFT_AC_CHANNEL7_WEIGHT)\n#define BITS_AC_CHANNEL7_WEIGHT                                                \\\n\t(BIT_MASK_AC_CHANNEL7_WEIGHT << BIT_SHIFT_AC_CHANNEL7_WEIGHT)\n#define BIT_CLEAR_AC_CHANNEL7_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL7_WEIGHT))\n#define BIT_GET_AC_CHANNEL7_WEIGHT(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL7_WEIGHT) & BIT_MASK_AC_CHANNEL7_WEIGHT)\n#define BIT_SET_AC_CHANNEL7_WEIGHT(x, v)                                       \\\n\t(BIT_CLEAR_AC_CHANNEL7_WEIGHT(x) | BIT_AC_CHANNEL7_WEIGHT(v))\n\n/* 2 REG_AC_CHANNEL8_WEIGHT\t\t\t(Offset 0x3370) */\n\n#define BIT_SHIFT_AC_CHANNEL8_WEIGHT 0\n#define BIT_MASK_AC_CHANNEL8_WEIGHT 0xff\n#define BIT_AC_CHANNEL8_WEIGHT(x)                                              \\\n\t(((x) & BIT_MASK_AC_CHANNEL8_WEIGHT) << BIT_SHIFT_AC_CHANNEL8_WEIGHT)\n#define BITS_AC_CHANNEL8_WEIGHT                                                \\\n\t(BIT_MASK_AC_CHANNEL8_WEIGHT << BIT_SHIFT_AC_CHANNEL8_WEIGHT)\n#define BIT_CLEAR_AC_CHANNEL8_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL8_WEIGHT))\n#define BIT_GET_AC_CHANNEL8_WEIGHT(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL8_WEIGHT) & BIT_MASK_AC_CHANNEL8_WEIGHT)\n#define BIT_SET_AC_CHANNEL8_WEIGHT(x, v)                                       \\\n\t(BIT_CLEAR_AC_CHANNEL8_WEIGHT(x) | BIT_AC_CHANNEL8_WEIGHT(v))\n\n/* 2 REG_AC_CHANNEL9_WEIGHT\t\t\t(Offset 0x3371) */\n\n#define BIT_SHIFT_AC_CHANNEL9_WEIGHT 0\n#define BIT_MASK_AC_CHANNEL9_WEIGHT 0xff\n#define BIT_AC_CHANNEL9_WEIGHT(x)                                              \\\n\t(((x) & BIT_MASK_AC_CHANNEL9_WEIGHT) << BIT_SHIFT_AC_CHANNEL9_WEIGHT)\n#define BITS_AC_CHANNEL9_WEIGHT                                                \\\n\t(BIT_MASK_AC_CHANNEL9_WEIGHT << BIT_SHIFT_AC_CHANNEL9_WEIGHT)\n#define BIT_CLEAR_AC_CHANNEL9_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL9_WEIGHT))\n#define BIT_GET_AC_CHANNEL9_WEIGHT(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL9_WEIGHT) & BIT_MASK_AC_CHANNEL9_WEIGHT)\n#define BIT_SET_AC_CHANNEL9_WEIGHT(x, v)                                       \\\n\t(BIT_CLEAR_AC_CHANNEL9_WEIGHT(x) | BIT_AC_CHANNEL9_WEIGHT(v))\n\n/* 2 REG_AC_CHANNEL10_WEIGHT\t\t\t(Offset 0x3372) */\n\n#define BIT_SHIFT_AC_CHANNEL10_WEIGHT 0\n#define BIT_MASK_AC_CHANNEL10_WEIGHT 0xff\n#define BIT_AC_CHANNEL10_WEIGHT(x)                                             \\\n\t(((x) & BIT_MASK_AC_CHANNEL10_WEIGHT) << BIT_SHIFT_AC_CHANNEL10_WEIGHT)\n#define BITS_AC_CHANNEL10_WEIGHT                                               \\\n\t(BIT_MASK_AC_CHANNEL10_WEIGHT << BIT_SHIFT_AC_CHANNEL10_WEIGHT)\n#define BIT_CLEAR_AC_CHANNEL10_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL10_WEIGHT))\n#define BIT_GET_AC_CHANNEL10_WEIGHT(x)                                         \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL10_WEIGHT) & BIT_MASK_AC_CHANNEL10_WEIGHT)\n#define BIT_SET_AC_CHANNEL10_WEIGHT(x, v)                                      \\\n\t(BIT_CLEAR_AC_CHANNEL10_WEIGHT(x) | BIT_AC_CHANNEL10_WEIGHT(v))\n\n/* 2 REG_AC_CHANNEL11_WEIGHT\t\t\t(Offset 0x3373) */\n\n#define BIT_SHIFT_AC_CHANNEL11_WEIGHT 0\n#define BIT_MASK_AC_CHANNEL11_WEIGHT 0xff\n#define BIT_AC_CHANNEL11_WEIGHT(x)                                             \\\n\t(((x) & BIT_MASK_AC_CHANNEL11_WEIGHT) << BIT_SHIFT_AC_CHANNEL11_WEIGHT)\n#define BITS_AC_CHANNEL11_WEIGHT                                               \\\n\t(BIT_MASK_AC_CHANNEL11_WEIGHT << BIT_SHIFT_AC_CHANNEL11_WEIGHT)\n#define BIT_CLEAR_AC_CHANNEL11_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL11_WEIGHT))\n#define BIT_GET_AC_CHANNEL11_WEIGHT(x)                                         \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL11_WEIGHT) & BIT_MASK_AC_CHANNEL11_WEIGHT)\n#define BIT_SET_AC_CHANNEL11_WEIGHT(x, v)                                      \\\n\t(BIT_CLEAR_AC_CHANNEL11_WEIGHT(x) | BIT_AC_CHANNEL11_WEIGHT(v))\n\n/* 2 REG_AC_CHANNEL12_WEIGHT\t\t\t(Offset 0x3374) */\n\n#define BIT_SHIFT_AC_CHANNEL12_WEIGHT 0\n#define BIT_MASK_AC_CHANNEL12_WEIGHT 0xff\n#define BIT_AC_CHANNEL12_WEIGHT(x)                                             \\\n\t(((x) & BIT_MASK_AC_CHANNEL12_WEIGHT) << BIT_SHIFT_AC_CHANNEL12_WEIGHT)\n#define BITS_AC_CHANNEL12_WEIGHT                                               \\\n\t(BIT_MASK_AC_CHANNEL12_WEIGHT << BIT_SHIFT_AC_CHANNEL12_WEIGHT)\n#define BIT_CLEAR_AC_CHANNEL12_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL12_WEIGHT))\n#define BIT_GET_AC_CHANNEL12_WEIGHT(x)                                         \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL12_WEIGHT) & BIT_MASK_AC_CHANNEL12_WEIGHT)\n#define BIT_SET_AC_CHANNEL12_WEIGHT(x, v)                                      \\\n\t(BIT_CLEAR_AC_CHANNEL12_WEIGHT(x) | BIT_AC_CHANNEL12_WEIGHT(v))\n\n/* 2 REG_AC_CHANNEL13_WEIGHT\t\t\t(Offset 0x3375) */\n\n#define BIT_SHIFT_AC_CHANNEL13_WEIGHT 0\n#define BIT_MASK_AC_CHANNEL13_WEIGHT 0xff\n#define BIT_AC_CHANNEL13_WEIGHT(x)                                             \\\n\t(((x) & BIT_MASK_AC_CHANNEL13_WEIGHT) << BIT_SHIFT_AC_CHANNEL13_WEIGHT)\n#define BITS_AC_CHANNEL13_WEIGHT                                               \\\n\t(BIT_MASK_AC_CHANNEL13_WEIGHT << BIT_SHIFT_AC_CHANNEL13_WEIGHT)\n#define BIT_CLEAR_AC_CHANNEL13_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL13_WEIGHT))\n#define BIT_GET_AC_CHANNEL13_WEIGHT(x)                                         \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL13_WEIGHT) & BIT_MASK_AC_CHANNEL13_WEIGHT)\n#define BIT_SET_AC_CHANNEL13_WEIGHT(x, v)                                      \\\n\t(BIT_CLEAR_AC_CHANNEL13_WEIGHT(x) | BIT_AC_CHANNEL13_WEIGHT(v))\n\n#endif\n\n#endif /* __RTL_WLAN_BITDEF_H__ */\n"
  },
  {
    "path": "hal/halmac/halmac_bit_8197f.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef __INC_HALMAC_BIT_8197F_H\n#define __INC_HALMAC_BIT_8197F_H\n\n#define CPU_OPT_WIDTH 0x1F\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_SYS_ISO_CTRL_8197F */\n#define BIT_PWC_EV12V_8197F BIT(15)\n#define BIT_PWC_EV25V_8197F BIT(14)\n#define BIT_PA33V_EN_8197F BIT(13)\n#define BIT_PA12V_EN_8197F BIT(12)\n#define BIT_UA33V_EN_8197F BIT(11)\n#define BIT_UA12V_EN_8197F BIT(10)\n#define BIT_ISO_RFDIO_8197F BIT(9)\n#define BIT_ISO_EB2CORE_8197F BIT(8)\n#define BIT_ISO_DIOE_8197F BIT(7)\n#define BIT_ISO_WLPON2PP_8197F BIT(6)\n#define BIT_ISO_IP2MAC_WA2PP_8197F BIT(5)\n#define BIT_ISO_PD2CORE_8197F BIT(4)\n#define BIT_ISO_PA2PCIE_8197F BIT(3)\n#define BIT_ISO_UD2CORE_8197F BIT(2)\n#define BIT_ISO_UA2USB_8197F BIT(1)\n#define BIT_ISO_WD2PP_8197F BIT(0)\n\n/* 2 REG_SYS_FUNC_EN_8197F */\n#define BIT_FEN_MREGEN_8197F BIT(15)\n#define BIT_FEN_HWPDN_8197F BIT(14)\n#define BIT_EN_25_1_8197F BIT(13)\n#define BIT_FEN_ELDR_8197F BIT(12)\n#define BIT_FEN_DCORE_8197F BIT(11)\n#define BIT_FEN_CPUEN_8197F BIT(10)\n#define BIT_FEN_DIOE_8197F BIT(9)\n#define BIT_FEN_PCIED_8197F BIT(8)\n#define BIT_FEN_PPLL_8197F BIT(7)\n#define BIT_FEN_PCIEA_8197F BIT(6)\n#define BIT_FEN_DIO_PCIE_8197F BIT(5)\n#define BIT_FEN_USBD_8197F BIT(4)\n#define BIT_FEN_UPLL_8197F BIT(3)\n#define BIT_FEN_USBA_8197F BIT(2)\n#define BIT_FEN_BB_GLB_RSTN_8197F BIT(1)\n#define BIT_FEN_BBRSTB_8197F BIT(0)\n\n/* 2 REG_SYS_PW_CTRL_8197F */\n#define BIT_SOP_EABM_8197F BIT(31)\n#define BIT_SOP_ACKF_8197F BIT(30)\n#define BIT_SOP_ERCK_8197F BIT(29)\n#define BIT_SOP_ESWR_8197F BIT(28)\n#define BIT_SOP_PWMM_8197F BIT(27)\n#define BIT_SOP_EECK_8197F BIT(26)\n#define BIT_SOP_EXTL_8197F BIT(24)\n#define BIT_SYM_OP_RING_12M_8197F BIT(22)\n#define BIT_ROP_SWPR_8197F BIT(21)\n#define BIT_DIS_HW_LPLDM_8197F BIT(20)\n#define BIT_OPT_SWRST_WLMCU_8197F BIT(19)\n#define BIT_RDY_SYSPWR_8197F BIT(17)\n#define BIT_EN_WLON_8197F BIT(16)\n#define BIT_APDM_HPDN_8197F BIT(15)\n#define BIT_AFSM_PCIE_SUS_EN_8197F BIT(12)\n#define BIT_AFSM_WLSUS_EN_8197F BIT(11)\n#define BIT_APFM_SWLPS_8197F BIT(10)\n#define BIT_APFM_OFFMAC_8197F BIT(9)\n#define BIT_APFN_ONMAC_8197F BIT(8)\n#define BIT_CHIP_PDN_EN_8197F BIT(7)\n#define BIT_RDY_MACDIS_8197F BIT(6)\n#define BIT_RING_CLK_12M_EN_8197F BIT(4)\n#define BIT_PFM_WOWL_8197F BIT(3)\n#define BIT_PFM_LDKP_8197F BIT(2)\n#define BIT_WL_HCI_ALD_8197F BIT(1)\n#define BIT_PFM_LDALL_8197F BIT(0)\n\n/* 2 REG_SYS_CLK_CTRL_8197F */\n#define BIT_LDO_DUMMY_8197F BIT(15)\n#define BIT_CPU_CLK_EN_8197F BIT(14)\n#define BIT_SYMREG_CLK_EN_8197F BIT(13)\n#define BIT_HCI_CLK_EN_8197F BIT(12)\n#define BIT_MAC_CLK_EN_8197F BIT(11)\n#define BIT_SEC_CLK_EN_8197F BIT(10)\n#define BIT_PHY_SSC_RSTB_8197F BIT(9)\n#define BIT_EXT_32K_EN_8197F BIT(8)\n#define BIT_WL_CLK_TEST_8197F BIT(7)\n#define BIT_OP_SPS_PWM_EN_8197F BIT(6)\n#define BIT_LOADER_CLK_EN_8197F BIT(5)\n#define BIT_MACSLP_8197F BIT(4)\n#define BIT_WAKEPAD_EN_8197F BIT(3)\n#define BIT_ROMD16V_EN_8197F BIT(2)\n#define BIT_CKANA12M_EN_8197F BIT(1)\n#define BIT_CNTD16V_EN_8197F BIT(0)\n\n/* 2 REG_SYS_EEPROM_CTRL_8197F */\n\n#define BIT_SHIFT_VPDIDX_8197F 8\n#define BIT_MASK_VPDIDX_8197F 0xff\n#define BIT_VPDIDX_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_VPDIDX_8197F) << BIT_SHIFT_VPDIDX_8197F)\n#define BITS_VPDIDX_8197F (BIT_MASK_VPDIDX_8197F << BIT_SHIFT_VPDIDX_8197F)\n#define BIT_CLEAR_VPDIDX_8197F(x) ((x) & (~BITS_VPDIDX_8197F))\n#define BIT_GET_VPDIDX_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_VPDIDX_8197F) & BIT_MASK_VPDIDX_8197F)\n#define BIT_SET_VPDIDX_8197F(x, v)                                             \\\n\t(BIT_CLEAR_VPDIDX_8197F(x) | BIT_VPDIDX_8197F(v))\n\n#define BIT_SHIFT_EEM1_0_8197F 6\n#define BIT_MASK_EEM1_0_8197F 0x3\n#define BIT_EEM1_0_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_EEM1_0_8197F) << BIT_SHIFT_EEM1_0_8197F)\n#define BITS_EEM1_0_8197F (BIT_MASK_EEM1_0_8197F << BIT_SHIFT_EEM1_0_8197F)\n#define BIT_CLEAR_EEM1_0_8197F(x) ((x) & (~BITS_EEM1_0_8197F))\n#define BIT_GET_EEM1_0_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_EEM1_0_8197F) & BIT_MASK_EEM1_0_8197F)\n#define BIT_SET_EEM1_0_8197F(x, v)                                             \\\n\t(BIT_CLEAR_EEM1_0_8197F(x) | BIT_EEM1_0_8197F(v))\n\n#define BIT_AUTOLOAD_SUS_8197F BIT(5)\n#define BIT_EERPOMSEL_8197F BIT(4)\n#define BIT_EECS_V1_8197F BIT(3)\n#define BIT_EESK_V1_8197F BIT(2)\n#define BIT_EEDI_V1_8197F BIT(1)\n#define BIT_EEDO_V1_8197F BIT(0)\n\n/* 2 REG_EE_VPD_8197F */\n\n#define BIT_SHIFT_VPD_DATA_8197F 0\n#define BIT_MASK_VPD_DATA_8197F 0xffffffffL\n#define BIT_VPD_DATA_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_VPD_DATA_8197F) << BIT_SHIFT_VPD_DATA_8197F)\n#define BITS_VPD_DATA_8197F                                                    \\\n\t(BIT_MASK_VPD_DATA_8197F << BIT_SHIFT_VPD_DATA_8197F)\n#define BIT_CLEAR_VPD_DATA_8197F(x) ((x) & (~BITS_VPD_DATA_8197F))\n#define BIT_GET_VPD_DATA_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_VPD_DATA_8197F) & BIT_MASK_VPD_DATA_8197F)\n#define BIT_SET_VPD_DATA_8197F(x, v)                                           \\\n\t(BIT_CLEAR_VPD_DATA_8197F(x) | BIT_VPD_DATA_8197F(v))\n\n/* 2 REG_SYS_SWR_CTRL1_8197F */\n#define BIT_SW18_C2_BIT0_8197F BIT(31)\n\n#define BIT_SHIFT_SW18_C1_8197F 29\n#define BIT_MASK_SW18_C1_8197F 0x3\n#define BIT_SW18_C1_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_SW18_C1_8197F) << BIT_SHIFT_SW18_C1_8197F)\n#define BITS_SW18_C1_8197F (BIT_MASK_SW18_C1_8197F << BIT_SHIFT_SW18_C1_8197F)\n#define BIT_CLEAR_SW18_C1_8197F(x) ((x) & (~BITS_SW18_C1_8197F))\n#define BIT_GET_SW18_C1_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_SW18_C1_8197F) & BIT_MASK_SW18_C1_8197F)\n#define BIT_SET_SW18_C1_8197F(x, v)                                            \\\n\t(BIT_CLEAR_SW18_C1_8197F(x) | BIT_SW18_C1_8197F(v))\n\n#define BIT_SHIFT_REG_FREQ_L_8197F 25\n#define BIT_MASK_REG_FREQ_L_8197F 0x7\n#define BIT_REG_FREQ_L_8197F(x)                                                \\\n\t(((x) & BIT_MASK_REG_FREQ_L_8197F) << BIT_SHIFT_REG_FREQ_L_8197F)\n#define BITS_REG_FREQ_L_8197F                                                  \\\n\t(BIT_MASK_REG_FREQ_L_8197F << BIT_SHIFT_REG_FREQ_L_8197F)\n#define BIT_CLEAR_REG_FREQ_L_8197F(x) ((x) & (~BITS_REG_FREQ_L_8197F))\n#define BIT_GET_REG_FREQ_L_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_REG_FREQ_L_8197F) & BIT_MASK_REG_FREQ_L_8197F)\n#define BIT_SET_REG_FREQ_L_8197F(x, v)                                         \\\n\t(BIT_CLEAR_REG_FREQ_L_8197F(x) | BIT_REG_FREQ_L_8197F(v))\n\n#define BIT_REG_EN_DUTY_8197F BIT(24)\n\n#define BIT_SHIFT_REG_MODE_8197F 22\n#define BIT_MASK_REG_MODE_8197F 0x3\n#define BIT_REG_MODE_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_REG_MODE_8197F) << BIT_SHIFT_REG_MODE_8197F)\n#define BITS_REG_MODE_8197F                                                    \\\n\t(BIT_MASK_REG_MODE_8197F << BIT_SHIFT_REG_MODE_8197F)\n#define BIT_CLEAR_REG_MODE_8197F(x) ((x) & (~BITS_REG_MODE_8197F))\n#define BIT_GET_REG_MODE_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_REG_MODE_8197F) & BIT_MASK_REG_MODE_8197F)\n#define BIT_SET_REG_MODE_8197F(x, v)                                           \\\n\t(BIT_CLEAR_REG_MODE_8197F(x) | BIT_REG_MODE_8197F(v))\n\n#define BIT_REG_EN_SP_8197F BIT(21)\n#define BIT_REG_AUTO_L_8197F BIT(20)\n#define BIT_SW18_SELD_BIT0_8197F BIT(19)\n#define BIT_SW18_POWOCP_8197F BIT(18)\n\n#define BIT_SHIFT_SW18_OCP_8197F 15\n#define BIT_MASK_SW18_OCP_8197F 0x7\n#define BIT_SW18_OCP_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_SW18_OCP_8197F) << BIT_SHIFT_SW18_OCP_8197F)\n#define BITS_SW18_OCP_8197F                                                    \\\n\t(BIT_MASK_SW18_OCP_8197F << BIT_SHIFT_SW18_OCP_8197F)\n#define BIT_CLEAR_SW18_OCP_8197F(x) ((x) & (~BITS_SW18_OCP_8197F))\n#define BIT_GET_SW18_OCP_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_SW18_OCP_8197F) & BIT_MASK_SW18_OCP_8197F)\n#define BIT_SET_SW18_OCP_8197F(x, v)                                           \\\n\t(BIT_CLEAR_SW18_OCP_8197F(x) | BIT_SW18_OCP_8197F(v))\n\n#define BIT_SHIFT_CF_L_BIT0_TO_1_8197F 13\n#define BIT_MASK_CF_L_BIT0_TO_1_8197F 0x3\n#define BIT_CF_L_BIT0_TO_1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_CF_L_BIT0_TO_1_8197F)                                 \\\n\t << BIT_SHIFT_CF_L_BIT0_TO_1_8197F)\n#define BITS_CF_L_BIT0_TO_1_8197F                                              \\\n\t(BIT_MASK_CF_L_BIT0_TO_1_8197F << BIT_SHIFT_CF_L_BIT0_TO_1_8197F)\n#define BIT_CLEAR_CF_L_BIT0_TO_1_8197F(x) ((x) & (~BITS_CF_L_BIT0_TO_1_8197F))\n#define BIT_GET_CF_L_BIT0_TO_1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_CF_L_BIT0_TO_1_8197F) &                             \\\n\t BIT_MASK_CF_L_BIT0_TO_1_8197F)\n#define BIT_SET_CF_L_BIT0_TO_1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_CF_L_BIT0_TO_1_8197F(x) | BIT_CF_L_BIT0_TO_1_8197F(v))\n\n#define BIT_SW18_FPWM_8197F BIT(11)\n#define BIT_SW18_SWEN_8197F BIT(9)\n#define BIT_SW18_LDEN_8197F BIT(8)\n#define BIT_MAC_ID_EN_8197F BIT(7)\n#define BIT_WL_CTRL_XTAL_CADJ_8197F BIT(6)\n#define BIT_AFE_BGEN_8197F BIT(0)\n\n/* 2 REG_SYS_SWR_CTRL2_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_SYS_SWR_CTRL3_8197F */\n#define BIT_SPS18_OCP_DIS_8197F BIT(31)\n\n#define BIT_SHIFT_SPS18_OCP_TH_8197F 16\n#define BIT_MASK_SPS18_OCP_TH_8197F 0x7fff\n#define BIT_SPS18_OCP_TH_8197F(x)                                              \\\n\t(((x) & BIT_MASK_SPS18_OCP_TH_8197F) << BIT_SHIFT_SPS18_OCP_TH_8197F)\n#define BITS_SPS18_OCP_TH_8197F                                                \\\n\t(BIT_MASK_SPS18_OCP_TH_8197F << BIT_SHIFT_SPS18_OCP_TH_8197F)\n#define BIT_CLEAR_SPS18_OCP_TH_8197F(x) ((x) & (~BITS_SPS18_OCP_TH_8197F))\n#define BIT_GET_SPS18_OCP_TH_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_SPS18_OCP_TH_8197F) & BIT_MASK_SPS18_OCP_TH_8197F)\n#define BIT_SET_SPS18_OCP_TH_8197F(x, v)                                       \\\n\t(BIT_CLEAR_SPS18_OCP_TH_8197F(x) | BIT_SPS18_OCP_TH_8197F(v))\n\n#define BIT_SHIFT_OCP_WINDOW_8197F 0\n#define BIT_MASK_OCP_WINDOW_8197F 0xffff\n#define BIT_OCP_WINDOW_8197F(x)                                                \\\n\t(((x) & BIT_MASK_OCP_WINDOW_8197F) << BIT_SHIFT_OCP_WINDOW_8197F)\n#define BITS_OCP_WINDOW_8197F                                                  \\\n\t(BIT_MASK_OCP_WINDOW_8197F << BIT_SHIFT_OCP_WINDOW_8197F)\n#define BIT_CLEAR_OCP_WINDOW_8197F(x) ((x) & (~BITS_OCP_WINDOW_8197F))\n#define BIT_GET_OCP_WINDOW_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_OCP_WINDOW_8197F) & BIT_MASK_OCP_WINDOW_8197F)\n#define BIT_SET_OCP_WINDOW_8197F(x, v)                                         \\\n\t(BIT_CLEAR_OCP_WINDOW_8197F(x) | BIT_OCP_WINDOW_8197F(v))\n\n/* 2 REG_RSV_CTRL_8197F */\n#define BIT_HREG_DBG_8197F BIT(23)\n#define BIT_WLMCUIOIF_8197F BIT(8)\n#define BIT_LOCK_ALL_EN_8197F BIT(7)\n#define BIT_R_DIS_PRST_8197F BIT(6)\n#define BIT_WLOCK_1C_B6_8197F BIT(5)\n#define BIT_WLOCK_40_8197F BIT(4)\n#define BIT_WLOCK_08_8197F BIT(3)\n#define BIT_WLOCK_04_8197F BIT(2)\n#define BIT_WLOCK_00_8197F BIT(1)\n#define BIT_WLOCK_ALL_8197F BIT(0)\n\n/* 2 REG_RF0_CTRL_8197F */\n#define BIT_RF0_SDMRSTB_8197F BIT(2)\n#define BIT_RF0_RSTB_8197F BIT(1)\n#define BIT_RF0_EN_8197F BIT(0)\n\n/* 2 REG_AFE_LDO_CTRL_8197F */\n\n#define BIT_SHIFT_LPLDH12_RSV_8197F 29\n#define BIT_MASK_LPLDH12_RSV_8197F 0x7\n#define BIT_LPLDH12_RSV_8197F(x)                                               \\\n\t(((x) & BIT_MASK_LPLDH12_RSV_8197F) << BIT_SHIFT_LPLDH12_RSV_8197F)\n#define BITS_LPLDH12_RSV_8197F                                                 \\\n\t(BIT_MASK_LPLDH12_RSV_8197F << BIT_SHIFT_LPLDH12_RSV_8197F)\n#define BIT_CLEAR_LPLDH12_RSV_8197F(x) ((x) & (~BITS_LPLDH12_RSV_8197F))\n#define BIT_GET_LPLDH12_RSV_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_LPLDH12_RSV_8197F) & BIT_MASK_LPLDH12_RSV_8197F)\n#define BIT_SET_LPLDH12_RSV_8197F(x, v)                                        \\\n\t(BIT_CLEAR_LPLDH12_RSV_8197F(x) | BIT_LPLDH12_RSV_8197F(v))\n\n#define BIT_LPLDH12_SLP_8197F BIT(28)\n\n#define BIT_SHIFT_LPLDH12_VADJ_8197F 24\n#define BIT_MASK_LPLDH12_VADJ_8197F 0xf\n#define BIT_LPLDH12_VADJ_8197F(x)                                              \\\n\t(((x) & BIT_MASK_LPLDH12_VADJ_8197F) << BIT_SHIFT_LPLDH12_VADJ_8197F)\n#define BITS_LPLDH12_VADJ_8197F                                                \\\n\t(BIT_MASK_LPLDH12_VADJ_8197F << BIT_SHIFT_LPLDH12_VADJ_8197F)\n#define BIT_CLEAR_LPLDH12_VADJ_8197F(x) ((x) & (~BITS_LPLDH12_VADJ_8197F))\n#define BIT_GET_LPLDH12_VADJ_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_LPLDH12_VADJ_8197F) & BIT_MASK_LPLDH12_VADJ_8197F)\n#define BIT_SET_LPLDH12_VADJ_8197F(x, v)                                       \\\n\t(BIT_CLEAR_LPLDH12_VADJ_8197F(x) | BIT_LPLDH12_VADJ_8197F(v))\n\n#define BIT_LDH12_EN_8197F BIT(16)\n#define BIT_POW_REGU_P1_8197F BIT(10)\n#define BIT_LDOV12W_EN_8197F BIT(8)\n#define BIT_EX_XTAL_DRV_DIGI_8197F BIT(7)\n#define BIT_EX_XTAL_DRV_USB_8197F BIT(6)\n#define BIT_EX_XTAL_DRV_AFE_8197F BIT(5)\n#define BIT_EX_XTAL_DRV_RF2_8197F BIT(4)\n#define BIT_EX_XTAL_DRV_RF1_8197F BIT(3)\n#define BIT_POW_REGU_P0_8197F BIT(2)\n\n/* 2 REG_NOT_VALID_8197F */\n#define BIT_POW_PLL_LDO_8197F BIT(0)\n\n/* 2 REG_AFE_CTRL1_8197F */\n#define BIT_AGPIO_GPE_8197F BIT(31)\n\n#define BIT_SHIFT_XTAL_CAP_XI_8197F 25\n#define BIT_MASK_XTAL_CAP_XI_8197F 0x3f\n#define BIT_XTAL_CAP_XI_8197F(x)                                               \\\n\t(((x) & BIT_MASK_XTAL_CAP_XI_8197F) << BIT_SHIFT_XTAL_CAP_XI_8197F)\n#define BITS_XTAL_CAP_XI_8197F                                                 \\\n\t(BIT_MASK_XTAL_CAP_XI_8197F << BIT_SHIFT_XTAL_CAP_XI_8197F)\n#define BIT_CLEAR_XTAL_CAP_XI_8197F(x) ((x) & (~BITS_XTAL_CAP_XI_8197F))\n#define BIT_GET_XTAL_CAP_XI_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_XTAL_CAP_XI_8197F) & BIT_MASK_XTAL_CAP_XI_8197F)\n#define BIT_SET_XTAL_CAP_XI_8197F(x, v)                                        \\\n\t(BIT_CLEAR_XTAL_CAP_XI_8197F(x) | BIT_XTAL_CAP_XI_8197F(v))\n\n#define BIT_SHIFT_XTAL_DRV_DIGI_8197F 23\n#define BIT_MASK_XTAL_DRV_DIGI_8197F 0x3\n#define BIT_XTAL_DRV_DIGI_8197F(x)                                             \\\n\t(((x) & BIT_MASK_XTAL_DRV_DIGI_8197F) << BIT_SHIFT_XTAL_DRV_DIGI_8197F)\n#define BITS_XTAL_DRV_DIGI_8197F                                               \\\n\t(BIT_MASK_XTAL_DRV_DIGI_8197F << BIT_SHIFT_XTAL_DRV_DIGI_8197F)\n#define BIT_CLEAR_XTAL_DRV_DIGI_8197F(x) ((x) & (~BITS_XTAL_DRV_DIGI_8197F))\n#define BIT_GET_XTAL_DRV_DIGI_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8197F) & BIT_MASK_XTAL_DRV_DIGI_8197F)\n#define BIT_SET_XTAL_DRV_DIGI_8197F(x, v)                                      \\\n\t(BIT_CLEAR_XTAL_DRV_DIGI_8197F(x) | BIT_XTAL_DRV_DIGI_8197F(v))\n\n#define BIT_XTAL_DRV_USB_BIT1_8197F BIT(22)\n\n#define BIT_SHIFT_MAC_CLK_SEL_8197F 20\n#define BIT_MASK_MAC_CLK_SEL_8197F 0x3\n#define BIT_MAC_CLK_SEL_8197F(x)                                               \\\n\t(((x) & BIT_MASK_MAC_CLK_SEL_8197F) << BIT_SHIFT_MAC_CLK_SEL_8197F)\n#define BITS_MAC_CLK_SEL_8197F                                                 \\\n\t(BIT_MASK_MAC_CLK_SEL_8197F << BIT_SHIFT_MAC_CLK_SEL_8197F)\n#define BIT_CLEAR_MAC_CLK_SEL_8197F(x) ((x) & (~BITS_MAC_CLK_SEL_8197F))\n#define BIT_GET_MAC_CLK_SEL_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_MAC_CLK_SEL_8197F) & BIT_MASK_MAC_CLK_SEL_8197F)\n#define BIT_SET_MAC_CLK_SEL_8197F(x, v)                                        \\\n\t(BIT_CLEAR_MAC_CLK_SEL_8197F(x) | BIT_MAC_CLK_SEL_8197F(v))\n\n#define BIT_XTAL_DRV_USB_BIT0_8197F BIT(19)\n\n#define BIT_SHIFT_XTAL_DRV_AFE_8197F 17\n#define BIT_MASK_XTAL_DRV_AFE_8197F 0x3\n#define BIT_XTAL_DRV_AFE_8197F(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_DRV_AFE_8197F) << BIT_SHIFT_XTAL_DRV_AFE_8197F)\n#define BITS_XTAL_DRV_AFE_8197F                                                \\\n\t(BIT_MASK_XTAL_DRV_AFE_8197F << BIT_SHIFT_XTAL_DRV_AFE_8197F)\n#define BIT_CLEAR_XTAL_DRV_AFE_8197F(x) ((x) & (~BITS_XTAL_DRV_AFE_8197F))\n#define BIT_GET_XTAL_DRV_AFE_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_AFE_8197F) & BIT_MASK_XTAL_DRV_AFE_8197F)\n#define BIT_SET_XTAL_DRV_AFE_8197F(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_DRV_AFE_8197F(x) | BIT_XTAL_DRV_AFE_8197F(v))\n\n#define BIT_SHIFT_XTAL_DRV_RF2_8197F 15\n#define BIT_MASK_XTAL_DRV_RF2_8197F 0x3\n#define BIT_XTAL_DRV_RF2_8197F(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_DRV_RF2_8197F) << BIT_SHIFT_XTAL_DRV_RF2_8197F)\n#define BITS_XTAL_DRV_RF2_8197F                                                \\\n\t(BIT_MASK_XTAL_DRV_RF2_8197F << BIT_SHIFT_XTAL_DRV_RF2_8197F)\n#define BIT_CLEAR_XTAL_DRV_RF2_8197F(x) ((x) & (~BITS_XTAL_DRV_RF2_8197F))\n#define BIT_GET_XTAL_DRV_RF2_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_RF2_8197F) & BIT_MASK_XTAL_DRV_RF2_8197F)\n#define BIT_SET_XTAL_DRV_RF2_8197F(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_DRV_RF2_8197F(x) | BIT_XTAL_DRV_RF2_8197F(v))\n\n#define BIT_SHIFT_XTAL_DRV_RF1_8197F 13\n#define BIT_MASK_XTAL_DRV_RF1_8197F 0x3\n#define BIT_XTAL_DRV_RF1_8197F(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_DRV_RF1_8197F) << BIT_SHIFT_XTAL_DRV_RF1_8197F)\n#define BITS_XTAL_DRV_RF1_8197F                                                \\\n\t(BIT_MASK_XTAL_DRV_RF1_8197F << BIT_SHIFT_XTAL_DRV_RF1_8197F)\n#define BIT_CLEAR_XTAL_DRV_RF1_8197F(x) ((x) & (~BITS_XTAL_DRV_RF1_8197F))\n#define BIT_GET_XTAL_DRV_RF1_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_RF1_8197F) & BIT_MASK_XTAL_DRV_RF1_8197F)\n#define BIT_SET_XTAL_DRV_RF1_8197F(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_DRV_RF1_8197F(x) | BIT_XTAL_DRV_RF1_8197F(v))\n\n#define BIT_XTAL_DELAY_DIGI_8197F BIT(12)\n#define BIT_XTAL_DELAY_USB_8197F BIT(11)\n#define BIT_XTAL_DELAY_AFE_8197F BIT(10)\n#define BIT_XTAL_LP_V1_8197F BIT(9)\n#define BIT_XTAL_GM_SEP_V1_8197F BIT(8)\n#define BIT_XTAL_LDO_VREF_V1_8197F BIT(7)\n#define BIT_XTAL_XQSEL_RF_8197F BIT(6)\n#define BIT_XTAL_XQSEL_8197F BIT(5)\n\n#define BIT_SHIFT_XTAL_GMN_V1_8197F 3\n#define BIT_MASK_XTAL_GMN_V1_8197F 0x3\n#define BIT_XTAL_GMN_V1_8197F(x)                                               \\\n\t(((x) & BIT_MASK_XTAL_GMN_V1_8197F) << BIT_SHIFT_XTAL_GMN_V1_8197F)\n#define BITS_XTAL_GMN_V1_8197F                                                 \\\n\t(BIT_MASK_XTAL_GMN_V1_8197F << BIT_SHIFT_XTAL_GMN_V1_8197F)\n#define BIT_CLEAR_XTAL_GMN_V1_8197F(x) ((x) & (~BITS_XTAL_GMN_V1_8197F))\n#define BIT_GET_XTAL_GMN_V1_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_XTAL_GMN_V1_8197F) & BIT_MASK_XTAL_GMN_V1_8197F)\n#define BIT_SET_XTAL_GMN_V1_8197F(x, v)                                        \\\n\t(BIT_CLEAR_XTAL_GMN_V1_8197F(x) | BIT_XTAL_GMN_V1_8197F(v))\n\n#define BIT_SHIFT_XTAL_GMP_V1_8197F 1\n#define BIT_MASK_XTAL_GMP_V1_8197F 0x3\n#define BIT_XTAL_GMP_V1_8197F(x)                                               \\\n\t(((x) & BIT_MASK_XTAL_GMP_V1_8197F) << BIT_SHIFT_XTAL_GMP_V1_8197F)\n#define BITS_XTAL_GMP_V1_8197F                                                 \\\n\t(BIT_MASK_XTAL_GMP_V1_8197F << BIT_SHIFT_XTAL_GMP_V1_8197F)\n#define BIT_CLEAR_XTAL_GMP_V1_8197F(x) ((x) & (~BITS_XTAL_GMP_V1_8197F))\n#define BIT_GET_XTAL_GMP_V1_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_XTAL_GMP_V1_8197F) & BIT_MASK_XTAL_GMP_V1_8197F)\n#define BIT_SET_XTAL_GMP_V1_8197F(x, v)                                        \\\n\t(BIT_CLEAR_XTAL_GMP_V1_8197F(x) | BIT_XTAL_GMP_V1_8197F(v))\n\n#define BIT_XTAL_EN_8197F BIT(0)\n\n/* 2 REG_AFE_CTRL2_8197F */\n\n#define BIT_SHIFT_RS_SET_V2_8197F 26\n#define BIT_MASK_RS_SET_V2_8197F 0x7\n#define BIT_RS_SET_V2_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_RS_SET_V2_8197F) << BIT_SHIFT_RS_SET_V2_8197F)\n#define BITS_RS_SET_V2_8197F                                                   \\\n\t(BIT_MASK_RS_SET_V2_8197F << BIT_SHIFT_RS_SET_V2_8197F)\n#define BIT_CLEAR_RS_SET_V2_8197F(x) ((x) & (~BITS_RS_SET_V2_8197F))\n#define BIT_GET_RS_SET_V2_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_RS_SET_V2_8197F) & BIT_MASK_RS_SET_V2_8197F)\n#define BIT_SET_RS_SET_V2_8197F(x, v)                                          \\\n\t(BIT_CLEAR_RS_SET_V2_8197F(x) | BIT_RS_SET_V2_8197F(v))\n\n#define BIT_SHIFT_CP_BIAS_V2_8197F 18\n#define BIT_MASK_CP_BIAS_V2_8197F 0x7\n#define BIT_CP_BIAS_V2_8197F(x)                                                \\\n\t(((x) & BIT_MASK_CP_BIAS_V2_8197F) << BIT_SHIFT_CP_BIAS_V2_8197F)\n#define BITS_CP_BIAS_V2_8197F                                                  \\\n\t(BIT_MASK_CP_BIAS_V2_8197F << BIT_SHIFT_CP_BIAS_V2_8197F)\n#define BIT_CLEAR_CP_BIAS_V2_8197F(x) ((x) & (~BITS_CP_BIAS_V2_8197F))\n#define BIT_GET_CP_BIAS_V2_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_CP_BIAS_V2_8197F) & BIT_MASK_CP_BIAS_V2_8197F)\n#define BIT_SET_CP_BIAS_V2_8197F(x, v)                                         \\\n\t(BIT_CLEAR_CP_BIAS_V2_8197F(x) | BIT_CP_BIAS_V2_8197F(v))\n\n#define BIT_FREF_SEL_8197F BIT(16)\n\n#define BIT_SHIFT_MCCO_V2_8197F 14\n#define BIT_MASK_MCCO_V2_8197F 0x3\n#define BIT_MCCO_V2_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_MCCO_V2_8197F) << BIT_SHIFT_MCCO_V2_8197F)\n#define BITS_MCCO_V2_8197F (BIT_MASK_MCCO_V2_8197F << BIT_SHIFT_MCCO_V2_8197F)\n#define BIT_CLEAR_MCCO_V2_8197F(x) ((x) & (~BITS_MCCO_V2_8197F))\n#define BIT_GET_MCCO_V2_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_MCCO_V2_8197F) & BIT_MASK_MCCO_V2_8197F)\n#define BIT_SET_MCCO_V2_8197F(x, v)                                            \\\n\t(BIT_CLEAR_MCCO_V2_8197F(x) | BIT_MCCO_V2_8197F(v))\n\n#define BIT_SHIFT_CK320_EN_8197F 12\n#define BIT_MASK_CK320_EN_8197F 0x3\n#define BIT_CK320_EN_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_CK320_EN_8197F) << BIT_SHIFT_CK320_EN_8197F)\n#define BITS_CK320_EN_8197F                                                    \\\n\t(BIT_MASK_CK320_EN_8197F << BIT_SHIFT_CK320_EN_8197F)\n#define BIT_CLEAR_CK320_EN_8197F(x) ((x) & (~BITS_CK320_EN_8197F))\n#define BIT_GET_CK320_EN_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_CK320_EN_8197F) & BIT_MASK_CK320_EN_8197F)\n#define BIT_SET_CK320_EN_8197F(x, v)                                           \\\n\t(BIT_CLEAR_CK320_EN_8197F(x) | BIT_CK320_EN_8197F(v))\n\n#define BIT_AGPIO_GPO_8197F BIT(9)\n\n#define BIT_SHIFT_AGPIO_DRV_8197F 7\n#define BIT_MASK_AGPIO_DRV_8197F 0x3\n#define BIT_AGPIO_DRV_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_AGPIO_DRV_8197F) << BIT_SHIFT_AGPIO_DRV_8197F)\n#define BITS_AGPIO_DRV_8197F                                                   \\\n\t(BIT_MASK_AGPIO_DRV_8197F << BIT_SHIFT_AGPIO_DRV_8197F)\n#define BIT_CLEAR_AGPIO_DRV_8197F(x) ((x) & (~BITS_AGPIO_DRV_8197F))\n#define BIT_GET_AGPIO_DRV_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_AGPIO_DRV_8197F) & BIT_MASK_AGPIO_DRV_8197F)\n#define BIT_SET_AGPIO_DRV_8197F(x, v)                                          \\\n\t(BIT_CLEAR_AGPIO_DRV_8197F(x) | BIT_AGPIO_DRV_8197F(v))\n\n#define BIT_SHIFT_XTAL_CAP_XO_8197F 1\n#define BIT_MASK_XTAL_CAP_XO_8197F 0x3f\n#define BIT_XTAL_CAP_XO_8197F(x)                                               \\\n\t(((x) & BIT_MASK_XTAL_CAP_XO_8197F) << BIT_SHIFT_XTAL_CAP_XO_8197F)\n#define BITS_XTAL_CAP_XO_8197F                                                 \\\n\t(BIT_MASK_XTAL_CAP_XO_8197F << BIT_SHIFT_XTAL_CAP_XO_8197F)\n#define BIT_CLEAR_XTAL_CAP_XO_8197F(x) ((x) & (~BITS_XTAL_CAP_XO_8197F))\n#define BIT_GET_XTAL_CAP_XO_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_XTAL_CAP_XO_8197F) & BIT_MASK_XTAL_CAP_XO_8197F)\n#define BIT_SET_XTAL_CAP_XO_8197F(x, v)                                        \\\n\t(BIT_CLEAR_XTAL_CAP_XO_8197F(x) | BIT_XTAL_CAP_XO_8197F(v))\n\n#define BIT_POW_PLL_8197F BIT(0)\n\n/* 2 REG_AFE_CTRL3_8197F */\n\n#define BIT_SHIFT_PS_V2_8197F 7\n#define BIT_MASK_PS_V2_8197F 0x7\n#define BIT_PS_V2_8197F(x)                                                     \\\n\t(((x) & BIT_MASK_PS_V2_8197F) << BIT_SHIFT_PS_V2_8197F)\n#define BITS_PS_V2_8197F (BIT_MASK_PS_V2_8197F << BIT_SHIFT_PS_V2_8197F)\n#define BIT_CLEAR_PS_V2_8197F(x) ((x) & (~BITS_PS_V2_8197F))\n#define BIT_GET_PS_V2_8197F(x)                                                 \\\n\t(((x) >> BIT_SHIFT_PS_V2_8197F) & BIT_MASK_PS_V2_8197F)\n#define BIT_SET_PS_V2_8197F(x, v)                                              \\\n\t(BIT_CLEAR_PS_V2_8197F(x) | BIT_PS_V2_8197F(v))\n\n#define BIT_PSEN_8197F BIT(6)\n#define BIT_DOGENB_8197F BIT(5)\n\n/* 2 REG_EFUSE_CTRL_8197F */\n#define BIT_EF_FLAG_8197F BIT(31)\n\n#define BIT_SHIFT_EF_PGPD_8197F 28\n#define BIT_MASK_EF_PGPD_8197F 0x7\n#define BIT_EF_PGPD_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_EF_PGPD_8197F) << BIT_SHIFT_EF_PGPD_8197F)\n#define BITS_EF_PGPD_8197F (BIT_MASK_EF_PGPD_8197F << BIT_SHIFT_EF_PGPD_8197F)\n#define BIT_CLEAR_EF_PGPD_8197F(x) ((x) & (~BITS_EF_PGPD_8197F))\n#define BIT_GET_EF_PGPD_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_PGPD_8197F) & BIT_MASK_EF_PGPD_8197F)\n#define BIT_SET_EF_PGPD_8197F(x, v)                                            \\\n\t(BIT_CLEAR_EF_PGPD_8197F(x) | BIT_EF_PGPD_8197F(v))\n\n#define BIT_SHIFT_EF_RDT_8197F 24\n#define BIT_MASK_EF_RDT_8197F 0xf\n#define BIT_EF_RDT_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_EF_RDT_8197F) << BIT_SHIFT_EF_RDT_8197F)\n#define BITS_EF_RDT_8197F (BIT_MASK_EF_RDT_8197F << BIT_SHIFT_EF_RDT_8197F)\n#define BIT_CLEAR_EF_RDT_8197F(x) ((x) & (~BITS_EF_RDT_8197F))\n#define BIT_GET_EF_RDT_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_EF_RDT_8197F) & BIT_MASK_EF_RDT_8197F)\n#define BIT_SET_EF_RDT_8197F(x, v)                                             \\\n\t(BIT_CLEAR_EF_RDT_8197F(x) | BIT_EF_RDT_8197F(v))\n\n#define BIT_SHIFT_EF_PGTS_8197F 20\n#define BIT_MASK_EF_PGTS_8197F 0xf\n#define BIT_EF_PGTS_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_EF_PGTS_8197F) << BIT_SHIFT_EF_PGTS_8197F)\n#define BITS_EF_PGTS_8197F (BIT_MASK_EF_PGTS_8197F << BIT_SHIFT_EF_PGTS_8197F)\n#define BIT_CLEAR_EF_PGTS_8197F(x) ((x) & (~BITS_EF_PGTS_8197F))\n#define BIT_GET_EF_PGTS_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_PGTS_8197F) & BIT_MASK_EF_PGTS_8197F)\n#define BIT_SET_EF_PGTS_8197F(x, v)                                            \\\n\t(BIT_CLEAR_EF_PGTS_8197F(x) | BIT_EF_PGTS_8197F(v))\n\n#define BIT_EF_PDWN_8197F BIT(19)\n#define BIT_EF_ALDEN_8197F BIT(18)\n\n#define BIT_SHIFT_EF_ADDR_8197F 8\n#define BIT_MASK_EF_ADDR_8197F 0x3ff\n#define BIT_EF_ADDR_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_EF_ADDR_8197F) << BIT_SHIFT_EF_ADDR_8197F)\n#define BITS_EF_ADDR_8197F (BIT_MASK_EF_ADDR_8197F << BIT_SHIFT_EF_ADDR_8197F)\n#define BIT_CLEAR_EF_ADDR_8197F(x) ((x) & (~BITS_EF_ADDR_8197F))\n#define BIT_GET_EF_ADDR_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_ADDR_8197F) & BIT_MASK_EF_ADDR_8197F)\n#define BIT_SET_EF_ADDR_8197F(x, v)                                            \\\n\t(BIT_CLEAR_EF_ADDR_8197F(x) | BIT_EF_ADDR_8197F(v))\n\n#define BIT_SHIFT_EF_DATA_8197F 0\n#define BIT_MASK_EF_DATA_8197F 0xff\n#define BIT_EF_DATA_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_EF_DATA_8197F) << BIT_SHIFT_EF_DATA_8197F)\n#define BITS_EF_DATA_8197F (BIT_MASK_EF_DATA_8197F << BIT_SHIFT_EF_DATA_8197F)\n#define BIT_CLEAR_EF_DATA_8197F(x) ((x) & (~BITS_EF_DATA_8197F))\n#define BIT_GET_EF_DATA_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_DATA_8197F) & BIT_MASK_EF_DATA_8197F)\n#define BIT_SET_EF_DATA_8197F(x, v)                                            \\\n\t(BIT_CLEAR_EF_DATA_8197F(x) | BIT_EF_DATA_8197F(v))\n\n/* 2 REG_LDO_EFUSE_CTRL_8197F */\n#define BIT_LDOE25_EN_8197F BIT(31)\n\n#define BIT_SHIFT_LDOE25_V12ADJ_L_8197F 27\n#define BIT_MASK_LDOE25_V12ADJ_L_8197F 0xf\n#define BIT_LDOE25_V12ADJ_L_8197F(x)                                           \\\n\t(((x) & BIT_MASK_LDOE25_V12ADJ_L_8197F)                                \\\n\t << BIT_SHIFT_LDOE25_V12ADJ_L_8197F)\n#define BITS_LDOE25_V12ADJ_L_8197F                                             \\\n\t(BIT_MASK_LDOE25_V12ADJ_L_8197F << BIT_SHIFT_LDOE25_V12ADJ_L_8197F)\n#define BIT_CLEAR_LDOE25_V12ADJ_L_8197F(x) ((x) & (~BITS_LDOE25_V12ADJ_L_8197F))\n#define BIT_GET_LDOE25_V12ADJ_L_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8197F) &                            \\\n\t BIT_MASK_LDOE25_V12ADJ_L_8197F)\n#define BIT_SET_LDOE25_V12ADJ_L_8197F(x, v)                                    \\\n\t(BIT_CLEAR_LDOE25_V12ADJ_L_8197F(x) | BIT_LDOE25_V12ADJ_L_8197F(v))\n\n#define BIT_SHIFT_EF_SCAN_START_V1_8197F 16\n#define BIT_MASK_EF_SCAN_START_V1_8197F 0x3ff\n#define BIT_EF_SCAN_START_V1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_EF_SCAN_START_V1_8197F)                               \\\n\t << BIT_SHIFT_EF_SCAN_START_V1_8197F)\n#define BITS_EF_SCAN_START_V1_8197F                                            \\\n\t(BIT_MASK_EF_SCAN_START_V1_8197F << BIT_SHIFT_EF_SCAN_START_V1_8197F)\n#define BIT_CLEAR_EF_SCAN_START_V1_8197F(x)                                    \\\n\t((x) & (~BITS_EF_SCAN_START_V1_8197F))\n#define BIT_GET_EF_SCAN_START_V1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_EF_SCAN_START_V1_8197F) &                           \\\n\t BIT_MASK_EF_SCAN_START_V1_8197F)\n#define BIT_SET_EF_SCAN_START_V1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_EF_SCAN_START_V1_8197F(x) | BIT_EF_SCAN_START_V1_8197F(v))\n\n#define BIT_SHIFT_EF_SCAN_END_8197F 12\n#define BIT_MASK_EF_SCAN_END_8197F 0xf\n#define BIT_EF_SCAN_END_8197F(x)                                               \\\n\t(((x) & BIT_MASK_EF_SCAN_END_8197F) << BIT_SHIFT_EF_SCAN_END_8197F)\n#define BITS_EF_SCAN_END_8197F                                                 \\\n\t(BIT_MASK_EF_SCAN_END_8197F << BIT_SHIFT_EF_SCAN_END_8197F)\n#define BIT_CLEAR_EF_SCAN_END_8197F(x) ((x) & (~BITS_EF_SCAN_END_8197F))\n#define BIT_GET_EF_SCAN_END_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_EF_SCAN_END_8197F) & BIT_MASK_EF_SCAN_END_8197F)\n#define BIT_SET_EF_SCAN_END_8197F(x, v)                                        \\\n\t(BIT_CLEAR_EF_SCAN_END_8197F(x) | BIT_EF_SCAN_END_8197F(v))\n\n#define BIT_SHIFT_EF_CELL_SEL_8197F 8\n#define BIT_MASK_EF_CELL_SEL_8197F 0x3\n#define BIT_EF_CELL_SEL_8197F(x)                                               \\\n\t(((x) & BIT_MASK_EF_CELL_SEL_8197F) << BIT_SHIFT_EF_CELL_SEL_8197F)\n#define BITS_EF_CELL_SEL_8197F                                                 \\\n\t(BIT_MASK_EF_CELL_SEL_8197F << BIT_SHIFT_EF_CELL_SEL_8197F)\n#define BIT_CLEAR_EF_CELL_SEL_8197F(x) ((x) & (~BITS_EF_CELL_SEL_8197F))\n#define BIT_GET_EF_CELL_SEL_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_EF_CELL_SEL_8197F) & BIT_MASK_EF_CELL_SEL_8197F)\n#define BIT_SET_EF_CELL_SEL_8197F(x, v)                                        \\\n\t(BIT_CLEAR_EF_CELL_SEL_8197F(x) | BIT_EF_CELL_SEL_8197F(v))\n\n#define BIT_EF_TRPT_8197F BIT(7)\n\n#define BIT_SHIFT_EF_TTHD_8197F 0\n#define BIT_MASK_EF_TTHD_8197F 0x7f\n#define BIT_EF_TTHD_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_EF_TTHD_8197F) << BIT_SHIFT_EF_TTHD_8197F)\n#define BITS_EF_TTHD_8197F (BIT_MASK_EF_TTHD_8197F << BIT_SHIFT_EF_TTHD_8197F)\n#define BIT_CLEAR_EF_TTHD_8197F(x) ((x) & (~BITS_EF_TTHD_8197F))\n#define BIT_GET_EF_TTHD_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_TTHD_8197F) & BIT_MASK_EF_TTHD_8197F)\n#define BIT_SET_EF_TTHD_8197F(x, v)                                            \\\n\t(BIT_CLEAR_EF_TTHD_8197F(x) | BIT_EF_TTHD_8197F(v))\n\n/* 2 REG_PWR_OPTION_CTRL_8197F */\n\n#define BIT_SHIFT_DBG_SEL_V1_8197F 16\n#define BIT_MASK_DBG_SEL_V1_8197F 0xff\n#define BIT_DBG_SEL_V1_8197F(x)                                                \\\n\t(((x) & BIT_MASK_DBG_SEL_V1_8197F) << BIT_SHIFT_DBG_SEL_V1_8197F)\n#define BITS_DBG_SEL_V1_8197F                                                  \\\n\t(BIT_MASK_DBG_SEL_V1_8197F << BIT_SHIFT_DBG_SEL_V1_8197F)\n#define BIT_CLEAR_DBG_SEL_V1_8197F(x) ((x) & (~BITS_DBG_SEL_V1_8197F))\n#define BIT_GET_DBG_SEL_V1_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_DBG_SEL_V1_8197F) & BIT_MASK_DBG_SEL_V1_8197F)\n#define BIT_SET_DBG_SEL_V1_8197F(x, v)                                         \\\n\t(BIT_CLEAR_DBG_SEL_V1_8197F(x) | BIT_DBG_SEL_V1_8197F(v))\n\n#define BIT_SHIFT_DBG_SEL_BYTE_8197F 14\n#define BIT_MASK_DBG_SEL_BYTE_8197F 0x3\n#define BIT_DBG_SEL_BYTE_8197F(x)                                              \\\n\t(((x) & BIT_MASK_DBG_SEL_BYTE_8197F) << BIT_SHIFT_DBG_SEL_BYTE_8197F)\n#define BITS_DBG_SEL_BYTE_8197F                                                \\\n\t(BIT_MASK_DBG_SEL_BYTE_8197F << BIT_SHIFT_DBG_SEL_BYTE_8197F)\n#define BIT_CLEAR_DBG_SEL_BYTE_8197F(x) ((x) & (~BITS_DBG_SEL_BYTE_8197F))\n#define BIT_GET_DBG_SEL_BYTE_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_DBG_SEL_BYTE_8197F) & BIT_MASK_DBG_SEL_BYTE_8197F)\n#define BIT_SET_DBG_SEL_BYTE_8197F(x, v)                                       \\\n\t(BIT_CLEAR_DBG_SEL_BYTE_8197F(x) | BIT_DBG_SEL_BYTE_8197F(v))\n\n#define BIT_SHIFT_STD_L1_V1_8197F 12\n#define BIT_MASK_STD_L1_V1_8197F 0x3\n#define BIT_STD_L1_V1_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_STD_L1_V1_8197F) << BIT_SHIFT_STD_L1_V1_8197F)\n#define BITS_STD_L1_V1_8197F                                                   \\\n\t(BIT_MASK_STD_L1_V1_8197F << BIT_SHIFT_STD_L1_V1_8197F)\n#define BIT_CLEAR_STD_L1_V1_8197F(x) ((x) & (~BITS_STD_L1_V1_8197F))\n#define BIT_GET_STD_L1_V1_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_STD_L1_V1_8197F) & BIT_MASK_STD_L1_V1_8197F)\n#define BIT_SET_STD_L1_V1_8197F(x, v)                                          \\\n\t(BIT_CLEAR_STD_L1_V1_8197F(x) | BIT_STD_L1_V1_8197F(v))\n\n#define BIT_SYSON_DBG_PAD_E2_8197F BIT(11)\n#define BIT_SYSON_LED_PAD_E2_8197F BIT(10)\n#define BIT_SYSON_GPEE_PAD_E2_8197F BIT(9)\n#define BIT_SYSON_PCI_PAD_E2_8197F BIT(8)\n#define BIT_AUTO_SW_LDO_VOL_EN_8197F BIT(7)\n\n#define BIT_SHIFT_SYSON_SPS0WWV_WT_8197F 4\n#define BIT_MASK_SYSON_SPS0WWV_WT_8197F 0x3\n#define BIT_SYSON_SPS0WWV_WT_8197F(x)                                          \\\n\t(((x) & BIT_MASK_SYSON_SPS0WWV_WT_8197F)                               \\\n\t << BIT_SHIFT_SYSON_SPS0WWV_WT_8197F)\n#define BITS_SYSON_SPS0WWV_WT_8197F                                            \\\n\t(BIT_MASK_SYSON_SPS0WWV_WT_8197F << BIT_SHIFT_SYSON_SPS0WWV_WT_8197F)\n#define BIT_CLEAR_SYSON_SPS0WWV_WT_8197F(x)                                    \\\n\t((x) & (~BITS_SYSON_SPS0WWV_WT_8197F))\n#define BIT_GET_SYSON_SPS0WWV_WT_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) &                           \\\n\t BIT_MASK_SYSON_SPS0WWV_WT_8197F)\n#define BIT_SET_SYSON_SPS0WWV_WT_8197F(x, v)                                   \\\n\t(BIT_CLEAR_SYSON_SPS0WWV_WT_8197F(x) | BIT_SYSON_SPS0WWV_WT_8197F(v))\n\n#define BIT_SHIFT_SYSON_SPS0LDO_WT_8197F 2\n#define BIT_MASK_SYSON_SPS0LDO_WT_8197F 0x3\n#define BIT_SYSON_SPS0LDO_WT_8197F(x)                                          \\\n\t(((x) & BIT_MASK_SYSON_SPS0LDO_WT_8197F)                               \\\n\t << BIT_SHIFT_SYSON_SPS0LDO_WT_8197F)\n#define BITS_SYSON_SPS0LDO_WT_8197F                                            \\\n\t(BIT_MASK_SYSON_SPS0LDO_WT_8197F << BIT_SHIFT_SYSON_SPS0LDO_WT_8197F)\n#define BIT_CLEAR_SYSON_SPS0LDO_WT_8197F(x)                                    \\\n\t((x) & (~BITS_SYSON_SPS0LDO_WT_8197F))\n#define BIT_GET_SYSON_SPS0LDO_WT_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) &                           \\\n\t BIT_MASK_SYSON_SPS0LDO_WT_8197F)\n#define BIT_SET_SYSON_SPS0LDO_WT_8197F(x, v)                                   \\\n\t(BIT_CLEAR_SYSON_SPS0LDO_WT_8197F(x) | BIT_SYSON_SPS0LDO_WT_8197F(v))\n\n#define BIT_SHIFT_SYSON_RCLK_SCALE_8197F 0\n#define BIT_MASK_SYSON_RCLK_SCALE_8197F 0x3\n#define BIT_SYSON_RCLK_SCALE_8197F(x)                                          \\\n\t(((x) & BIT_MASK_SYSON_RCLK_SCALE_8197F)                               \\\n\t << BIT_SHIFT_SYSON_RCLK_SCALE_8197F)\n#define BITS_SYSON_RCLK_SCALE_8197F                                            \\\n\t(BIT_MASK_SYSON_RCLK_SCALE_8197F << BIT_SHIFT_SYSON_RCLK_SCALE_8197F)\n#define BIT_CLEAR_SYSON_RCLK_SCALE_8197F(x)                                    \\\n\t((x) & (~BITS_SYSON_RCLK_SCALE_8197F))\n#define BIT_GET_SYSON_RCLK_SCALE_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8197F) &                           \\\n\t BIT_MASK_SYSON_RCLK_SCALE_8197F)\n#define BIT_SET_SYSON_RCLK_SCALE_8197F(x, v)                                   \\\n\t(BIT_CLEAR_SYSON_RCLK_SCALE_8197F(x) | BIT_SYSON_RCLK_SCALE_8197F(v))\n\n/* 2 REG_CAL_TIMER_8197F */\n\n#define BIT_SHIFT_MATCH_CNT_8197F 8\n#define BIT_MASK_MATCH_CNT_8197F 0xff\n#define BIT_MATCH_CNT_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_MATCH_CNT_8197F) << BIT_SHIFT_MATCH_CNT_8197F)\n#define BITS_MATCH_CNT_8197F                                                   \\\n\t(BIT_MASK_MATCH_CNT_8197F << BIT_SHIFT_MATCH_CNT_8197F)\n#define BIT_CLEAR_MATCH_CNT_8197F(x) ((x) & (~BITS_MATCH_CNT_8197F))\n#define BIT_GET_MATCH_CNT_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_MATCH_CNT_8197F) & BIT_MASK_MATCH_CNT_8197F)\n#define BIT_SET_MATCH_CNT_8197F(x, v)                                          \\\n\t(BIT_CLEAR_MATCH_CNT_8197F(x) | BIT_MATCH_CNT_8197F(v))\n\n#define BIT_SHIFT_CAL_SCAL_8197F 0\n#define BIT_MASK_CAL_SCAL_8197F 0xff\n#define BIT_CAL_SCAL_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_CAL_SCAL_8197F) << BIT_SHIFT_CAL_SCAL_8197F)\n#define BITS_CAL_SCAL_8197F                                                    \\\n\t(BIT_MASK_CAL_SCAL_8197F << BIT_SHIFT_CAL_SCAL_8197F)\n#define BIT_CLEAR_CAL_SCAL_8197F(x) ((x) & (~BITS_CAL_SCAL_8197F))\n#define BIT_GET_CAL_SCAL_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_CAL_SCAL_8197F) & BIT_MASK_CAL_SCAL_8197F)\n#define BIT_SET_CAL_SCAL_8197F(x, v)                                           \\\n\t(BIT_CLEAR_CAL_SCAL_8197F(x) | BIT_CAL_SCAL_8197F(v))\n\n/* 2 REG_ACLK_MON_8197F */\n\n#define BIT_SHIFT_RCLK_MON_8197F 5\n#define BIT_MASK_RCLK_MON_8197F 0x7ff\n#define BIT_RCLK_MON_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_RCLK_MON_8197F) << BIT_SHIFT_RCLK_MON_8197F)\n#define BITS_RCLK_MON_8197F                                                    \\\n\t(BIT_MASK_RCLK_MON_8197F << BIT_SHIFT_RCLK_MON_8197F)\n#define BIT_CLEAR_RCLK_MON_8197F(x) ((x) & (~BITS_RCLK_MON_8197F))\n#define BIT_GET_RCLK_MON_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_RCLK_MON_8197F) & BIT_MASK_RCLK_MON_8197F)\n#define BIT_SET_RCLK_MON_8197F(x, v)                                           \\\n\t(BIT_CLEAR_RCLK_MON_8197F(x) | BIT_RCLK_MON_8197F(v))\n\n#define BIT_CAL_EN_8197F BIT(4)\n\n#define BIT_SHIFT_DPSTU_8197F 2\n#define BIT_MASK_DPSTU_8197F 0x3\n#define BIT_DPSTU_8197F(x)                                                     \\\n\t(((x) & BIT_MASK_DPSTU_8197F) << BIT_SHIFT_DPSTU_8197F)\n#define BITS_DPSTU_8197F (BIT_MASK_DPSTU_8197F << BIT_SHIFT_DPSTU_8197F)\n#define BIT_CLEAR_DPSTU_8197F(x) ((x) & (~BITS_DPSTU_8197F))\n#define BIT_GET_DPSTU_8197F(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DPSTU_8197F) & BIT_MASK_DPSTU_8197F)\n#define BIT_SET_DPSTU_8197F(x, v)                                              \\\n\t(BIT_CLEAR_DPSTU_8197F(x) | BIT_DPSTU_8197F(v))\n\n#define BIT_SUS_16X_8197F BIT(1)\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_GPIO_MUXCFG_8197F */\n#define BIT_SIC_LOWEST_PRIORITY_8197F BIT(28)\n\n#define BIT_SHIFT_PIN_USECASE_8197F 24\n#define BIT_MASK_PIN_USECASE_8197F 0xf\n#define BIT_PIN_USECASE_8197F(x)                                               \\\n\t(((x) & BIT_MASK_PIN_USECASE_8197F) << BIT_SHIFT_PIN_USECASE_8197F)\n#define BITS_PIN_USECASE_8197F                                                 \\\n\t(BIT_MASK_PIN_USECASE_8197F << BIT_SHIFT_PIN_USECASE_8197F)\n#define BIT_CLEAR_PIN_USECASE_8197F(x) ((x) & (~BITS_PIN_USECASE_8197F))\n#define BIT_GET_PIN_USECASE_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_PIN_USECASE_8197F) & BIT_MASK_PIN_USECASE_8197F)\n#define BIT_SET_PIN_USECASE_8197F(x, v)                                        \\\n\t(BIT_CLEAR_PIN_USECASE_8197F(x) | BIT_PIN_USECASE_8197F(v))\n\n#define BIT_FSPI_EN_8197F BIT(19)\n#define BIT_WL_RTS_EXT_32K_SEL_8197F BIT(18)\n#define BIT_WLGP_SPI_EN_8197F BIT(16)\n#define BIT_SIC_LBK_8197F BIT(15)\n#define BIT_ENHTP_8197F BIT(14)\n#define BIT_WLPHY_DBG_EN_8197F BIT(13)\n#define BIT_ENSIC_8197F BIT(12)\n#define BIT_SIC_SWRST_8197F BIT(11)\n#define BIT_PO_WIFI_PTA_PINS_8197F BIT(10)\n#define BIT_BTCOEX_MBOX_EN_8197F BIT(9)\n#define BIT_ENUART_8197F BIT(8)\n\n#define BIT_SHIFT_BTMODE_8197F 6\n#define BIT_MASK_BTMODE_8197F 0x3\n#define BIT_BTMODE_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_BTMODE_8197F) << BIT_SHIFT_BTMODE_8197F)\n#define BITS_BTMODE_8197F (BIT_MASK_BTMODE_8197F << BIT_SHIFT_BTMODE_8197F)\n#define BIT_CLEAR_BTMODE_8197F(x) ((x) & (~BITS_BTMODE_8197F))\n#define BIT_GET_BTMODE_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_BTMODE_8197F) & BIT_MASK_BTMODE_8197F)\n#define BIT_SET_BTMODE_8197F(x, v)                                             \\\n\t(BIT_CLEAR_BTMODE_8197F(x) | BIT_BTMODE_8197F(v))\n\n#define BIT_ENBT_8197F BIT(5)\n#define BIT_EROM_EN_8197F BIT(4)\n#define BIT_WLRFE_6_7_EN_8197F BIT(3)\n#define BIT_WLRFE_4_5_EN_8197F BIT(2)\n\n#define BIT_SHIFT_GPIOSEL_8197F 0\n#define BIT_MASK_GPIOSEL_8197F 0x3\n#define BIT_GPIOSEL_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_GPIOSEL_8197F) << BIT_SHIFT_GPIOSEL_8197F)\n#define BITS_GPIOSEL_8197F (BIT_MASK_GPIOSEL_8197F << BIT_SHIFT_GPIOSEL_8197F)\n#define BIT_CLEAR_GPIOSEL_8197F(x) ((x) & (~BITS_GPIOSEL_8197F))\n#define BIT_GET_GPIOSEL_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_GPIOSEL_8197F) & BIT_MASK_GPIOSEL_8197F)\n#define BIT_SET_GPIOSEL_8197F(x, v)                                            \\\n\t(BIT_CLEAR_GPIOSEL_8197F(x) | BIT_GPIOSEL_8197F(v))\n\n/* 2 REG_GPIO_PIN_CTRL_8197F */\n\n#define BIT_SHIFT_GPIO_MOD_7_TO_0_8197F 24\n#define BIT_MASK_GPIO_MOD_7_TO_0_8197F 0xff\n#define BIT_GPIO_MOD_7_TO_0_8197F(x)                                           \\\n\t(((x) & BIT_MASK_GPIO_MOD_7_TO_0_8197F)                                \\\n\t << BIT_SHIFT_GPIO_MOD_7_TO_0_8197F)\n#define BITS_GPIO_MOD_7_TO_0_8197F                                             \\\n\t(BIT_MASK_GPIO_MOD_7_TO_0_8197F << BIT_SHIFT_GPIO_MOD_7_TO_0_8197F)\n#define BIT_CLEAR_GPIO_MOD_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8197F))\n#define BIT_GET_GPIO_MOD_7_TO_0_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) &                            \\\n\t BIT_MASK_GPIO_MOD_7_TO_0_8197F)\n#define BIT_SET_GPIO_MOD_7_TO_0_8197F(x, v)                                    \\\n\t(BIT_CLEAR_GPIO_MOD_7_TO_0_8197F(x) | BIT_GPIO_MOD_7_TO_0_8197F(v))\n\n#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F 16\n#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F 0xff\n#define BIT_GPIO_IO_SEL_7_TO_0_8197F(x)                                        \\\n\t(((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F)                             \\\n\t << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F)\n#define BITS_GPIO_IO_SEL_7_TO_0_8197F                                          \\\n\t(BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F                                     \\\n\t << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F)\n#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8197F(x)                                  \\\n\t((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8197F))\n#define BIT_GET_GPIO_IO_SEL_7_TO_0_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) &                         \\\n\t BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F)\n#define BIT_SET_GPIO_IO_SEL_7_TO_0_8197F(x, v)                                 \\\n\t(BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8197F(x) |                               \\\n\t BIT_GPIO_IO_SEL_7_TO_0_8197F(v))\n\n#define BIT_SHIFT_GPIO_OUT_7_TO_0_8197F 8\n#define BIT_MASK_GPIO_OUT_7_TO_0_8197F 0xff\n#define BIT_GPIO_OUT_7_TO_0_8197F(x)                                           \\\n\t(((x) & BIT_MASK_GPIO_OUT_7_TO_0_8197F)                                \\\n\t << BIT_SHIFT_GPIO_OUT_7_TO_0_8197F)\n#define BITS_GPIO_OUT_7_TO_0_8197F                                             \\\n\t(BIT_MASK_GPIO_OUT_7_TO_0_8197F << BIT_SHIFT_GPIO_OUT_7_TO_0_8197F)\n#define BIT_CLEAR_GPIO_OUT_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8197F))\n#define BIT_GET_GPIO_OUT_7_TO_0_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) &                            \\\n\t BIT_MASK_GPIO_OUT_7_TO_0_8197F)\n#define BIT_SET_GPIO_OUT_7_TO_0_8197F(x, v)                                    \\\n\t(BIT_CLEAR_GPIO_OUT_7_TO_0_8197F(x) | BIT_GPIO_OUT_7_TO_0_8197F(v))\n\n#define BIT_SHIFT_GPIO_IN_7_TO_0_8197F 0\n#define BIT_MASK_GPIO_IN_7_TO_0_8197F 0xff\n#define BIT_GPIO_IN_7_TO_0_8197F(x)                                            \\\n\t(((x) & BIT_MASK_GPIO_IN_7_TO_0_8197F)                                 \\\n\t << BIT_SHIFT_GPIO_IN_7_TO_0_8197F)\n#define BITS_GPIO_IN_7_TO_0_8197F                                              \\\n\t(BIT_MASK_GPIO_IN_7_TO_0_8197F << BIT_SHIFT_GPIO_IN_7_TO_0_8197F)\n#define BIT_CLEAR_GPIO_IN_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8197F))\n#define BIT_GET_GPIO_IN_7_TO_0_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8197F) &                             \\\n\t BIT_MASK_GPIO_IN_7_TO_0_8197F)\n#define BIT_SET_GPIO_IN_7_TO_0_8197F(x, v)                                     \\\n\t(BIT_CLEAR_GPIO_IN_7_TO_0_8197F(x) | BIT_GPIO_IN_7_TO_0_8197F(v))\n\n/* 2 REG_GPIO_INTM_8197F */\n\n#define BIT_SHIFT_MUXDBG_SEL_8197F 30\n#define BIT_MASK_MUXDBG_SEL_8197F 0x3\n#define BIT_MUXDBG_SEL_8197F(x)                                                \\\n\t(((x) & BIT_MASK_MUXDBG_SEL_8197F) << BIT_SHIFT_MUXDBG_SEL_8197F)\n#define BITS_MUXDBG_SEL_8197F                                                  \\\n\t(BIT_MASK_MUXDBG_SEL_8197F << BIT_SHIFT_MUXDBG_SEL_8197F)\n#define BIT_CLEAR_MUXDBG_SEL_8197F(x) ((x) & (~BITS_MUXDBG_SEL_8197F))\n#define BIT_GET_MUXDBG_SEL_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_MUXDBG_SEL_8197F) & BIT_MASK_MUXDBG_SEL_8197F)\n#define BIT_SET_MUXDBG_SEL_8197F(x, v)                                         \\\n\t(BIT_CLEAR_MUXDBG_SEL_8197F(x) | BIT_MUXDBG_SEL_8197F(v))\n\n#define BIT_EXTWOL_SEL_8197F BIT(17)\n#define BIT_EXTWOL_EN_8197F BIT(16)\n#define BIT_GPIOF_INT_MD_8197F BIT(15)\n#define BIT_GPIOE_INT_MD_8197F BIT(14)\n#define BIT_GPIOD_INT_MD_8197F BIT(13)\n#define BIT_GPIOC_INT_MD_8197F BIT(12)\n#define BIT_GPIOB_INT_MD_8197F BIT(11)\n#define BIT_GPIOA_INT_MD_8197F BIT(10)\n#define BIT_GPIO9_INT_MD_8197F BIT(9)\n#define BIT_GPIO8_INT_MD_8197F BIT(8)\n#define BIT_GPIO7_INT_MD_8197F BIT(7)\n#define BIT_GPIO6_INT_MD_8197F BIT(6)\n#define BIT_GPIO5_INT_MD_8197F BIT(5)\n#define BIT_GPIO4_INT_MD_8197F BIT(4)\n#define BIT_GPIO3_INT_MD_8197F BIT(3)\n#define BIT_GPIO2_INT_MD_8197F BIT(2)\n#define BIT_GPIO1_INT_MD_8197F BIT(1)\n#define BIT_GPIO0_INT_MD_8197F BIT(0)\n\n/* 2 REG_LED_CFG_8197F */\n#define BIT_LNAON_SEL_EN_8197F BIT(26)\n#define BIT_PAPE_SEL_EN_8197F BIT(25)\n#define BIT_DPDT_WLBT_SEL_8197F BIT(24)\n#define BIT_DPDT_SEL_EN_8197F BIT(23)\n#define BIT_LED2DIS_V1_8197F BIT(22)\n#define BIT_LED2EN_8197F BIT(21)\n#define BIT_LED2PL_8197F BIT(20)\n#define BIT_LED2SV_8197F BIT(19)\n\n#define BIT_SHIFT_LED2CM_8197F 16\n#define BIT_MASK_LED2CM_8197F 0x7\n#define BIT_LED2CM_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_LED2CM_8197F) << BIT_SHIFT_LED2CM_8197F)\n#define BITS_LED2CM_8197F (BIT_MASK_LED2CM_8197F << BIT_SHIFT_LED2CM_8197F)\n#define BIT_CLEAR_LED2CM_8197F(x) ((x) & (~BITS_LED2CM_8197F))\n#define BIT_GET_LED2CM_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_LED2CM_8197F) & BIT_MASK_LED2CM_8197F)\n#define BIT_SET_LED2CM_8197F(x, v)                                             \\\n\t(BIT_CLEAR_LED2CM_8197F(x) | BIT_LED2CM_8197F(v))\n\n#define BIT_LED1DIS_8197F BIT(15)\n#define BIT_LED1PL_8197F BIT(12)\n#define BIT_LED1SV_8197F BIT(11)\n\n#define BIT_SHIFT_LED1CM_8197F 8\n#define BIT_MASK_LED1CM_8197F 0x7\n#define BIT_LED1CM_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_LED1CM_8197F) << BIT_SHIFT_LED1CM_8197F)\n#define BITS_LED1CM_8197F (BIT_MASK_LED1CM_8197F << BIT_SHIFT_LED1CM_8197F)\n#define BIT_CLEAR_LED1CM_8197F(x) ((x) & (~BITS_LED1CM_8197F))\n#define BIT_GET_LED1CM_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_LED1CM_8197F) & BIT_MASK_LED1CM_8197F)\n#define BIT_SET_LED1CM_8197F(x, v)                                             \\\n\t(BIT_CLEAR_LED1CM_8197F(x) | BIT_LED1CM_8197F(v))\n\n#define BIT_LED0DIS_8197F BIT(7)\n\n#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F 5\n#define BIT_MASK_AFE_LDO_SWR_CHECK_8197F 0x3\n#define BIT_AFE_LDO_SWR_CHECK_8197F(x)                                         \\\n\t(((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8197F)                              \\\n\t << BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F)\n#define BITS_AFE_LDO_SWR_CHECK_8197F                                           \\\n\t(BIT_MASK_AFE_LDO_SWR_CHECK_8197F << BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F)\n#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8197F(x)                                   \\\n\t((x) & (~BITS_AFE_LDO_SWR_CHECK_8197F))\n#define BIT_GET_AFE_LDO_SWR_CHECK_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) &                          \\\n\t BIT_MASK_AFE_LDO_SWR_CHECK_8197F)\n#define BIT_SET_AFE_LDO_SWR_CHECK_8197F(x, v)                                  \\\n\t(BIT_CLEAR_AFE_LDO_SWR_CHECK_8197F(x) | BIT_AFE_LDO_SWR_CHECK_8197F(v))\n\n#define BIT_LED0PL_8197F BIT(4)\n#define BIT_LED0SV_8197F BIT(3)\n\n#define BIT_SHIFT_LED0CM_8197F 0\n#define BIT_MASK_LED0CM_8197F 0x7\n#define BIT_LED0CM_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_LED0CM_8197F) << BIT_SHIFT_LED0CM_8197F)\n#define BITS_LED0CM_8197F (BIT_MASK_LED0CM_8197F << BIT_SHIFT_LED0CM_8197F)\n#define BIT_CLEAR_LED0CM_8197F(x) ((x) & (~BITS_LED0CM_8197F))\n#define BIT_GET_LED0CM_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_LED0CM_8197F) & BIT_MASK_LED0CM_8197F)\n#define BIT_SET_LED0CM_8197F(x, v)                                             \\\n\t(BIT_CLEAR_LED0CM_8197F(x) | BIT_LED0CM_8197F(v))\n\n/* 2 REG_FSIMR_8197F */\n#define BIT_FS_PDNINT_EN_8197F BIT(31)\n#define BIT_FS_SPS_OCP_INT_EN_8197F BIT(29)\n#define BIT_FS_PWMERR_INT_EN_8197F BIT(28)\n#define BIT_FS_GPIOF_INT_EN_8197F BIT(27)\n#define BIT_FS_GPIOE_INT_EN_8197F BIT(26)\n#define BIT_FS_GPIOD_INT_EN_8197F BIT(25)\n#define BIT_FS_GPIOC_INT_EN_8197F BIT(24)\n#define BIT_FS_GPIOB_INT_EN_8197F BIT(23)\n#define BIT_FS_GPIOA_INT_EN_8197F BIT(22)\n#define BIT_FS_GPIO9_INT_EN_8197F BIT(21)\n#define BIT_FS_GPIO8_INT_EN_8197F BIT(20)\n#define BIT_FS_GPIO7_INT_EN_8197F BIT(19)\n#define BIT_FS_GPIO6_INT_EN_8197F BIT(18)\n#define BIT_FS_GPIO5_INT_EN_8197F BIT(17)\n#define BIT_FS_GPIO4_INT_EN_8197F BIT(16)\n#define BIT_FS_GPIO3_INT_EN_8197F BIT(15)\n#define BIT_FS_GPIO2_INT_EN_8197F BIT(14)\n#define BIT_FS_GPIO1_INT_EN_8197F BIT(13)\n#define BIT_FS_GPIO0_INT_EN_8197F BIT(12)\n#define BIT_FS_HCI_SUS_EN_8197F BIT(11)\n#define BIT_FS_HCI_RES_EN_8197F BIT(10)\n#define BIT_FS_HCI_RESET_EN_8197F BIT(9)\n#define BIT_AXI_EXCEPT_FINT_EN_8197F BIT(8)\n#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8197F BIT(7)\n#define BIT_ACT2RECOVERY_INT_EN_V1_8197F BIT(6)\n#define BIT_FS_TRPC_TO_INT_EN_8197F BIT(5)\n#define BIT_FS_RPC_O_T_INT_EN_8197F BIT(4)\n#define BIT_FS_32K_LEAVE_SETTING_MAK_8197F BIT(3)\n#define BIT_FS_32K_ENTER_SETTING_MAK_8197F BIT(2)\n#define BIT_FS_USB_LPMRSM_MSK_8197F BIT(1)\n#define BIT_FS_USB_LPMINT_MSK_8197F BIT(0)\n\n/* 2 REG_FSISR_8197F */\n#define BIT_FS_PDNINT_8197F BIT(31)\n#define BIT_FS_SPS_OCP_INT_8197F BIT(29)\n#define BIT_FS_PWMERR_INT_8197F BIT(28)\n#define BIT_FS_GPIOF_INT_8197F BIT(27)\n#define BIT_FS_GPIOE_INT_8197F BIT(26)\n#define BIT_FS_GPIOD_INT_8197F BIT(25)\n#define BIT_FS_GPIOC_INT_8197F BIT(24)\n#define BIT_FS_GPIOB_INT_8197F BIT(23)\n#define BIT_FS_GPIOA_INT_8197F BIT(22)\n#define BIT_FS_GPIO9_INT_8197F BIT(21)\n#define BIT_FS_GPIO8_INT_8197F BIT(20)\n#define BIT_FS_GPIO7_INT_8197F BIT(19)\n#define BIT_FS_GPIO6_INT_8197F BIT(18)\n#define BIT_FS_GPIO5_INT_8197F BIT(17)\n#define BIT_FS_GPIO4_INT_8197F BIT(16)\n#define BIT_FS_GPIO3_INT_8197F BIT(15)\n#define BIT_FS_GPIO2_INT_8197F BIT(14)\n#define BIT_FS_GPIO1_INT_8197F BIT(13)\n#define BIT_FS_GPIO0_INT_8197F BIT(12)\n#define BIT_FS_HCI_SUS_INT_8197F BIT(11)\n#define BIT_FS_HCI_RES_INT_8197F BIT(10)\n#define BIT_FS_HCI_RESET_INT_8197F BIT(9)\n#define BIT_AXI_EXCEPT_FINT_8197F BIT(8)\n#define BIT_FS_BTON_STS_UPDATE_INT_8197F BIT(7)\n#define BIT_ACT2RECOVERY_INT_V1_8197F BIT(6)\n#define BIT_FS_TRPC_TO_INT_INT_8197F BIT(5)\n#define BIT_FS_RPC_O_T_INT_INT_8197F BIT(4)\n#define BIT_FS_32K_LEAVE_SETTING_INT_8197F BIT(3)\n#define BIT_FS_32K_ENTER_SETTING_INT_8197F BIT(2)\n#define BIT_FS_USB_LPMRSM_INT_8197F BIT(1)\n#define BIT_FS_USB_LPMINT_INT_8197F BIT(0)\n\n/* 2 REG_HSIMR_8197F */\n#define BIT_GPIOF_INT_EN_8197F BIT(31)\n#define BIT_GPIOE_INT_EN_8197F BIT(30)\n#define BIT_GPIOD_INT_EN_8197F BIT(29)\n#define BIT_GPIOC_INT_EN_8197F BIT(28)\n#define BIT_GPIOB_INT_EN_8197F BIT(27)\n#define BIT_GPIOA_INT_EN_8197F BIT(26)\n#define BIT_GPIO9_INT_EN_8197F BIT(25)\n#define BIT_GPIO8_INT_EN_8197F BIT(24)\n#define BIT_GPIO7_INT_EN_8197F BIT(23)\n#define BIT_GPIO6_INT_EN_8197F BIT(22)\n#define BIT_GPIO5_INT_EN_8197F BIT(21)\n#define BIT_GPIO4_INT_EN_8197F BIT(20)\n#define BIT_GPIO3_INT_EN_8197F BIT(19)\n#define BIT_GPIO2_INT_EN_8197F BIT(18)\n#define BIT_GPIO1_INT_EN_8197F BIT(17)\n#define BIT_GPIO0_INT_EN_8197F BIT(16)\n#define BIT_AXI_EXCEPT_HINT_EN_8197F BIT(9)\n#define BIT_PDNINT_EN_V2_8197F BIT(8)\n#define BIT_PDNINT_EN_V1_8197F BIT(7)\n#define BIT_RON_INT_EN_V1_8197F BIT(6)\n#define BIT_SPS_OCP_INT_EN_V1_8197F BIT(5)\n#define BIT_GPIO15_0_INT_EN_V1_8197F BIT(0)\n\n/* 2 REG_HSISR_8197F */\n#define BIT_GPIOF_INT_8197F BIT(31)\n#define BIT_GPIOE_INT_8197F BIT(30)\n#define BIT_GPIOD_INT_8197F BIT(29)\n#define BIT_GPIOC_INT_8197F BIT(28)\n#define BIT_GPIOB_INT_8197F BIT(27)\n#define BIT_GPIOA_INT_8197F BIT(26)\n#define BIT_GPIO9_INT_8197F BIT(25)\n#define BIT_GPIO8_INT_8197F BIT(24)\n#define BIT_GPIO7_INT_8197F BIT(23)\n#define BIT_GPIO6_INT_8197F BIT(22)\n#define BIT_GPIO5_INT_8197F BIT(21)\n#define BIT_GPIO4_INT_8197F BIT(20)\n#define BIT_GPIO3_INT_8197F BIT(19)\n#define BIT_GPIO2_INT_8197F BIT(18)\n#define BIT_GPIO1_INT_8197F BIT(17)\n#define BIT_GPIO0_INT_8197F BIT(16)\n#define BIT_AXI_EXCEPT_HINT_8197F BIT(8)\n#define BIT_PDNINT_V1_8197F BIT(7)\n#define BIT_RON_INT_V1_8197F BIT(6)\n#define BIT_SPS_OCP_INT_V1_8197F BIT(5)\n#define BIT_GPIO15_0_INT_V1_8197F BIT(0)\n\n/* 2 REG_GPIO_EXT_CTRL_8197F */\n\n#define BIT_SHIFT_GPIO_MOD_15_TO_8_8197F 24\n#define BIT_MASK_GPIO_MOD_15_TO_8_8197F 0xff\n#define BIT_GPIO_MOD_15_TO_8_8197F(x)                                          \\\n\t(((x) & BIT_MASK_GPIO_MOD_15_TO_8_8197F)                               \\\n\t << BIT_SHIFT_GPIO_MOD_15_TO_8_8197F)\n#define BITS_GPIO_MOD_15_TO_8_8197F                                            \\\n\t(BIT_MASK_GPIO_MOD_15_TO_8_8197F << BIT_SHIFT_GPIO_MOD_15_TO_8_8197F)\n#define BIT_CLEAR_GPIO_MOD_15_TO_8_8197F(x)                                    \\\n\t((x) & (~BITS_GPIO_MOD_15_TO_8_8197F))\n#define BIT_GET_GPIO_MOD_15_TO_8_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) &                           \\\n\t BIT_MASK_GPIO_MOD_15_TO_8_8197F)\n#define BIT_SET_GPIO_MOD_15_TO_8_8197F(x, v)                                   \\\n\t(BIT_CLEAR_GPIO_MOD_15_TO_8_8197F(x) | BIT_GPIO_MOD_15_TO_8_8197F(v))\n\n#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F 16\n#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F 0xff\n#define BIT_GPIO_IO_SEL_15_TO_8_8197F(x)                                       \\\n\t(((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F)                            \\\n\t << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F)\n#define BITS_GPIO_IO_SEL_15_TO_8_8197F                                         \\\n\t(BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F                                    \\\n\t << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F)\n#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8197F(x)                                 \\\n\t((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8197F))\n#define BIT_GET_GPIO_IO_SEL_15_TO_8_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) &                        \\\n\t BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F)\n#define BIT_SET_GPIO_IO_SEL_15_TO_8_8197F(x, v)                                \\\n\t(BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8197F(x) |                              \\\n\t BIT_GPIO_IO_SEL_15_TO_8_8197F(v))\n\n#define BIT_SHIFT_GPIO_OUT_15_TO_8_8197F 8\n#define BIT_MASK_GPIO_OUT_15_TO_8_8197F 0xff\n#define BIT_GPIO_OUT_15_TO_8_8197F(x)                                          \\\n\t(((x) & BIT_MASK_GPIO_OUT_15_TO_8_8197F)                               \\\n\t << BIT_SHIFT_GPIO_OUT_15_TO_8_8197F)\n#define BITS_GPIO_OUT_15_TO_8_8197F                                            \\\n\t(BIT_MASK_GPIO_OUT_15_TO_8_8197F << BIT_SHIFT_GPIO_OUT_15_TO_8_8197F)\n#define BIT_CLEAR_GPIO_OUT_15_TO_8_8197F(x)                                    \\\n\t((x) & (~BITS_GPIO_OUT_15_TO_8_8197F))\n#define BIT_GET_GPIO_OUT_15_TO_8_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) &                           \\\n\t BIT_MASK_GPIO_OUT_15_TO_8_8197F)\n#define BIT_SET_GPIO_OUT_15_TO_8_8197F(x, v)                                   \\\n\t(BIT_CLEAR_GPIO_OUT_15_TO_8_8197F(x) | BIT_GPIO_OUT_15_TO_8_8197F(v))\n\n#define BIT_SHIFT_GPIO_IN_15_TO_8_8197F 0\n#define BIT_MASK_GPIO_IN_15_TO_8_8197F 0xff\n#define BIT_GPIO_IN_15_TO_8_8197F(x)                                           \\\n\t(((x) & BIT_MASK_GPIO_IN_15_TO_8_8197F)                                \\\n\t << BIT_SHIFT_GPIO_IN_15_TO_8_8197F)\n#define BITS_GPIO_IN_15_TO_8_8197F                                             \\\n\t(BIT_MASK_GPIO_IN_15_TO_8_8197F << BIT_SHIFT_GPIO_IN_15_TO_8_8197F)\n#define BIT_CLEAR_GPIO_IN_15_TO_8_8197F(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8197F))\n#define BIT_GET_GPIO_IN_15_TO_8_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8197F) &                            \\\n\t BIT_MASK_GPIO_IN_15_TO_8_8197F)\n#define BIT_SET_GPIO_IN_15_TO_8_8197F(x, v)                                    \\\n\t(BIT_CLEAR_GPIO_IN_15_TO_8_8197F(x) | BIT_GPIO_IN_15_TO_8_8197F(v))\n\n/* 2 REG_PAD_CTRL1_8197F */\n#define BIT_PAPE_WLBT_SEL_8197F BIT(29)\n#define BIT_LNAON_WLBT_SEL_8197F BIT(28)\n#define BIT_BTGP_GPG3_FEN_8197F BIT(26)\n#define BIT_BTGP_GPG2_FEN_8197F BIT(25)\n#define BIT_BTGP_JTAG_EN_8197F BIT(24)\n#define BIT_XTAL_CLK_EXTARNAL_EN_8197F BIT(23)\n#define BIT_BTGP_UART0_EN_8197F BIT(22)\n#define BIT_BTGP_UART1_EN_8197F BIT(21)\n#define BIT_BTGP_SPI_EN_8197F BIT(20)\n#define BIT_BTGP_GPIO_E2_8197F BIT(19)\n#define BIT_BTGP_GPIO_EN_8197F BIT(18)\n\n#define BIT_SHIFT_BTGP_GPIO_SL_8197F 16\n#define BIT_MASK_BTGP_GPIO_SL_8197F 0x3\n#define BIT_BTGP_GPIO_SL_8197F(x)                                              \\\n\t(((x) & BIT_MASK_BTGP_GPIO_SL_8197F) << BIT_SHIFT_BTGP_GPIO_SL_8197F)\n#define BITS_BTGP_GPIO_SL_8197F                                                \\\n\t(BIT_MASK_BTGP_GPIO_SL_8197F << BIT_SHIFT_BTGP_GPIO_SL_8197F)\n#define BIT_CLEAR_BTGP_GPIO_SL_8197F(x) ((x) & (~BITS_BTGP_GPIO_SL_8197F))\n#define BIT_GET_BTGP_GPIO_SL_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_BTGP_GPIO_SL_8197F) & BIT_MASK_BTGP_GPIO_SL_8197F)\n#define BIT_SET_BTGP_GPIO_SL_8197F(x, v)                                       \\\n\t(BIT_CLEAR_BTGP_GPIO_SL_8197F(x) | BIT_BTGP_GPIO_SL_8197F(v))\n\n#define BIT_PAD_SDIO_SR_8197F BIT(14)\n#define BIT_GPIO14_OUTPUT_PL_8197F BIT(13)\n#define BIT_HOST_WAKE_PAD_PULL_EN_8197F BIT(12)\n#define BIT_HOST_WAKE_PAD_SL_8197F BIT(11)\n#define BIT_PAD_LNAON_SR_8197F BIT(10)\n#define BIT_PAD_LNAON_E2_8197F BIT(9)\n#define BIT_SW_LNAON_G_SEL_DATA_8197F BIT(8)\n#define BIT_SW_LNAON_A_SEL_DATA_8197F BIT(7)\n#define BIT_PAD_PAPE_SR_8197F BIT(6)\n#define BIT_PAD_PAPE_E2_8197F BIT(5)\n#define BIT_SW_PAPE_G_SEL_DATA_8197F BIT(4)\n#define BIT_SW_PAPE_A_SEL_DATA_8197F BIT(3)\n#define BIT_PAD_DPDT_SR_8197F BIT(2)\n#define BIT_PAD_DPDT_PAD_E2_8197F BIT(1)\n#define BIT_SW_DPDT_SEL_DATA_8197F BIT(0)\n\n/* 2 REG_WL_BT_PWR_CTRL_8197F */\n#define BIT_ISO_BD2PP_8197F BIT(31)\n#define BIT_LDOV12B_EN_8197F BIT(30)\n#define BIT_CKEN_BTGPS_8197F BIT(29)\n#define BIT_FEN_BTGPS_8197F BIT(28)\n#define BIT_BTCPU_BOOTSEL_8197F BIT(27)\n#define BIT_SPI_SPEEDUP_8197F BIT(26)\n#define BIT_DEVWAKE_PAD_TYPE_SEL_8197F BIT(24)\n#define BIT_CLKREQ_PAD_TYPE_SEL_8197F BIT(23)\n#define BIT_ISO_BTPON2PP_8197F BIT(22)\n#define BIT_BT_HWROF_EN_8197F BIT(19)\n#define BIT_BT_FUNC_EN_8197F BIT(18)\n#define BIT_BT_HWPDN_SL_8197F BIT(17)\n#define BIT_BT_DISN_EN_8197F BIT(16)\n#define BIT_BT_PDN_PULL_EN_8197F BIT(15)\n#define BIT_WL_PDN_PULL_EN_8197F BIT(14)\n#define BIT_EXTERNAL_REQUEST_PL_8197F BIT(13)\n#define BIT_GPIO0_2_3_PULL_LOW_EN_8197F BIT(12)\n#define BIT_ISO_BA2PP_8197F BIT(11)\n#define BIT_BT_AFE_LDO_EN_8197F BIT(10)\n#define BIT_BT_AFE_PLL_EN_8197F BIT(9)\n#define BIT_BT_DIG_CLK_EN_8197F BIT(8)\n#define BIT_WL_DRV_EXIST_IDX_8197F BIT(5)\n#define BIT_DOP_EHPAD_8197F BIT(4)\n#define BIT_WL_HWROF_EN_8197F BIT(3)\n#define BIT_WL_FUNC_EN_8197F BIT(2)\n#define BIT_WL_HWPDN_SL_8197F BIT(1)\n#define BIT_WL_HWPDN_EN_8197F BIT(0)\n\n/* 2 REG_SDM_DEBUG_8197F */\n\n#define BIT_SHIFT_WLCLK_PHASE_8197F 0\n#define BIT_MASK_WLCLK_PHASE_8197F 0x1f\n#define BIT_WLCLK_PHASE_8197F(x)                                               \\\n\t(((x) & BIT_MASK_WLCLK_PHASE_8197F) << BIT_SHIFT_WLCLK_PHASE_8197F)\n#define BITS_WLCLK_PHASE_8197F                                                 \\\n\t(BIT_MASK_WLCLK_PHASE_8197F << BIT_SHIFT_WLCLK_PHASE_8197F)\n#define BIT_CLEAR_WLCLK_PHASE_8197F(x) ((x) & (~BITS_WLCLK_PHASE_8197F))\n#define BIT_GET_WLCLK_PHASE_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_WLCLK_PHASE_8197F) & BIT_MASK_WLCLK_PHASE_8197F)\n#define BIT_SET_WLCLK_PHASE_8197F(x, v)                                        \\\n\t(BIT_CLEAR_WLCLK_PHASE_8197F(x) | BIT_WLCLK_PHASE_8197F(v))\n\n/* 2 REG_SYS_SDIO_CTRL_8197F */\n#define BIT_DBG_GNT_WL_BT_8197F BIT(27)\n#define BIT_LTE_MUX_CTRL_PATH_8197F BIT(26)\n#define BIT_SDIO_INT_POLARITY_8197F BIT(19)\n#define BIT_SDIO_INT_8197F BIT(18)\n#define BIT_SDIO_OFF_EN_8197F BIT(17)\n#define BIT_SDIO_ON_EN_8197F BIT(16)\n\n/* 2 REG_HCI_OPT_CTRL_8197F */\n#define BIT_USB_HOST_PWR_OFF_EN_8197F BIT(12)\n#define BIT_SYM_LPS_BLOCK_EN_8197F BIT(11)\n#define BIT_USB_LPM_ACT_EN_8197F BIT(10)\n#define BIT_USB_LPM_NY_8197F BIT(9)\n#define BIT_USB_SUS_DIS_8197F BIT(8)\n\n#define BIT_SHIFT_SDIO_PAD_E_8197F 5\n#define BIT_MASK_SDIO_PAD_E_8197F 0x7\n#define BIT_SDIO_PAD_E_8197F(x)                                                \\\n\t(((x) & BIT_MASK_SDIO_PAD_E_8197F) << BIT_SHIFT_SDIO_PAD_E_8197F)\n#define BITS_SDIO_PAD_E_8197F                                                  \\\n\t(BIT_MASK_SDIO_PAD_E_8197F << BIT_SHIFT_SDIO_PAD_E_8197F)\n#define BIT_CLEAR_SDIO_PAD_E_8197F(x) ((x) & (~BITS_SDIO_PAD_E_8197F))\n#define BIT_GET_SDIO_PAD_E_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_SDIO_PAD_E_8197F) & BIT_MASK_SDIO_PAD_E_8197F)\n#define BIT_SET_SDIO_PAD_E_8197F(x, v)                                         \\\n\t(BIT_CLEAR_SDIO_PAD_E_8197F(x) | BIT_SDIO_PAD_E_8197F(v))\n\n#define BIT_USB_LPPLL_EN_8197F BIT(4)\n#define BIT_ROP_SW15_8197F BIT(2)\n#define BIT_PCI_CKRDY_OPT_8197F BIT(1)\n#define BIT_PCI_VAUX_EN_8197F BIT(0)\n\n/* 2 REG_AFE_CTRL4_8197F */\n#define BIT_RF1_SDMRSTB_8197F BIT(26)\n#define BIT_RF1_RSTB_8197F BIT(25)\n#define BIT_RF1_EN_8197F BIT(24)\n\n#define BIT_SHIFT_XTAL_LDO_8197F 20\n#define BIT_MASK_XTAL_LDO_8197F 0x7\n#define BIT_XTAL_LDO_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_XTAL_LDO_8197F) << BIT_SHIFT_XTAL_LDO_8197F)\n#define BITS_XTAL_LDO_8197F                                                    \\\n\t(BIT_MASK_XTAL_LDO_8197F << BIT_SHIFT_XTAL_LDO_8197F)\n#define BIT_CLEAR_XTAL_LDO_8197F(x) ((x) & (~BITS_XTAL_LDO_8197F))\n#define BIT_GET_XTAL_LDO_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_XTAL_LDO_8197F) & BIT_MASK_XTAL_LDO_8197F)\n#define BIT_SET_XTAL_LDO_8197F(x, v)                                           \\\n\t(BIT_CLEAR_XTAL_LDO_8197F(x) | BIT_XTAL_LDO_8197F(v))\n\n#define BIT_ADC_CK_SYNC_EN_8197F BIT(16)\n\n/* 2 REG_LDO_SWR_CTRL_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_MCUFW_CTRL_8197F */\n\n#define BIT_SHIFT_RPWM_8197F 24\n#define BIT_MASK_RPWM_8197F 0xff\n#define BIT_RPWM_8197F(x) (((x) & BIT_MASK_RPWM_8197F) << BIT_SHIFT_RPWM_8197F)\n#define BITS_RPWM_8197F (BIT_MASK_RPWM_8197F << BIT_SHIFT_RPWM_8197F)\n#define BIT_CLEAR_RPWM_8197F(x) ((x) & (~BITS_RPWM_8197F))\n#define BIT_GET_RPWM_8197F(x)                                                  \\\n\t(((x) >> BIT_SHIFT_RPWM_8197F) & BIT_MASK_RPWM_8197F)\n#define BIT_SET_RPWM_8197F(x, v) (BIT_CLEAR_RPWM_8197F(x) | BIT_RPWM_8197F(v))\n\n#define BIT_CPRST_8197F BIT(23)\n#define BIT_ANA_PORT_EN_8197F BIT(22)\n#define BIT_MAC_PORT_EN_8197F BIT(21)\n#define BIT_BOOT_FSPI_EN_8197F BIT(20)\n#define BIT_ROM_DLEN_8197F BIT(19)\n\n#define BIT_SHIFT_ROM_PGE_8197F 16\n#define BIT_MASK_ROM_PGE_8197F 0x7\n#define BIT_ROM_PGE_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_ROM_PGE_8197F) << BIT_SHIFT_ROM_PGE_8197F)\n#define BITS_ROM_PGE_8197F (BIT_MASK_ROM_PGE_8197F << BIT_SHIFT_ROM_PGE_8197F)\n#define BIT_CLEAR_ROM_PGE_8197F(x) ((x) & (~BITS_ROM_PGE_8197F))\n#define BIT_GET_ROM_PGE_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_ROM_PGE_8197F) & BIT_MASK_ROM_PGE_8197F)\n#define BIT_SET_ROM_PGE_8197F(x, v)                                            \\\n\t(BIT_CLEAR_ROM_PGE_8197F(x) | BIT_ROM_PGE_8197F(v))\n\n#define BIT_FW_INIT_RDY_8197F BIT(15)\n#define BIT_FW_DW_RDY_8197F BIT(14)\n\n#define BIT_SHIFT_CPU_CLK_SEL_8197F 12\n#define BIT_MASK_CPU_CLK_SEL_8197F 0x3\n#define BIT_CPU_CLK_SEL_8197F(x)                                               \\\n\t(((x) & BIT_MASK_CPU_CLK_SEL_8197F) << BIT_SHIFT_CPU_CLK_SEL_8197F)\n#define BITS_CPU_CLK_SEL_8197F                                                 \\\n\t(BIT_MASK_CPU_CLK_SEL_8197F << BIT_SHIFT_CPU_CLK_SEL_8197F)\n#define BIT_CLEAR_CPU_CLK_SEL_8197F(x) ((x) & (~BITS_CPU_CLK_SEL_8197F))\n#define BIT_GET_CPU_CLK_SEL_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_CPU_CLK_SEL_8197F) & BIT_MASK_CPU_CLK_SEL_8197F)\n#define BIT_SET_CPU_CLK_SEL_8197F(x, v)                                        \\\n\t(BIT_CLEAR_CPU_CLK_SEL_8197F(x) | BIT_CPU_CLK_SEL_8197F(v))\n\n#define BIT_CCLK_CHG_MASK_8197F BIT(11)\n#define BIT_FW_INIT_RDY_V1_8197F BIT(10)\n#define BIT_R_8051_SPD_8197F BIT(9)\n#define BIT_MCU_CLK_EN_8197F BIT(8)\n#define BIT_RAM_DL_SEL_8197F BIT(7)\n#define BIT_WINTINI_RDY_8197F BIT(6)\n#define BIT_RF_INIT_RDY_8197F BIT(5)\n#define BIT_BB_INIT_RDY_8197F BIT(4)\n#define BIT_MAC_INIT_RDY_8197F BIT(3)\n#define BIT_MCU_FWDL_RDY_8197F BIT(1)\n#define BIT_MCU_FWDL_EN_8197F BIT(0)\n\n/* 2 REG_MCU_TST_CFG_8197F */\n\n#define BIT_SHIFT_LBKTST_8197F 0\n#define BIT_MASK_LBKTST_8197F 0xffff\n#define BIT_LBKTST_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_LBKTST_8197F) << BIT_SHIFT_LBKTST_8197F)\n#define BITS_LBKTST_8197F (BIT_MASK_LBKTST_8197F << BIT_SHIFT_LBKTST_8197F)\n#define BIT_CLEAR_LBKTST_8197F(x) ((x) & (~BITS_LBKTST_8197F))\n#define BIT_GET_LBKTST_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_LBKTST_8197F) & BIT_MASK_LBKTST_8197F)\n#define BIT_SET_LBKTST_8197F(x, v)                                             \\\n\t(BIT_CLEAR_LBKTST_8197F(x) | BIT_LBKTST_8197F(v))\n\n/* 2 REG_HMEBOX_E0_E1_8197F */\n\n#define BIT_SHIFT_HOST_MSG_E1_8197F 16\n#define BIT_MASK_HOST_MSG_E1_8197F 0xffff\n#define BIT_HOST_MSG_E1_8197F(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E1_8197F) << BIT_SHIFT_HOST_MSG_E1_8197F)\n#define BITS_HOST_MSG_E1_8197F                                                 \\\n\t(BIT_MASK_HOST_MSG_E1_8197F << BIT_SHIFT_HOST_MSG_E1_8197F)\n#define BIT_CLEAR_HOST_MSG_E1_8197F(x) ((x) & (~BITS_HOST_MSG_E1_8197F))\n#define BIT_GET_HOST_MSG_E1_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E1_8197F) & BIT_MASK_HOST_MSG_E1_8197F)\n#define BIT_SET_HOST_MSG_E1_8197F(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E1_8197F(x) | BIT_HOST_MSG_E1_8197F(v))\n\n#define BIT_SHIFT_HOST_MSG_E0_8197F 0\n#define BIT_MASK_HOST_MSG_E0_8197F 0xffff\n#define BIT_HOST_MSG_E0_8197F(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E0_8197F) << BIT_SHIFT_HOST_MSG_E0_8197F)\n#define BITS_HOST_MSG_E0_8197F                                                 \\\n\t(BIT_MASK_HOST_MSG_E0_8197F << BIT_SHIFT_HOST_MSG_E0_8197F)\n#define BIT_CLEAR_HOST_MSG_E0_8197F(x) ((x) & (~BITS_HOST_MSG_E0_8197F))\n#define BIT_GET_HOST_MSG_E0_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E0_8197F) & BIT_MASK_HOST_MSG_E0_8197F)\n#define BIT_SET_HOST_MSG_E0_8197F(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E0_8197F(x) | BIT_HOST_MSG_E0_8197F(v))\n\n/* 2 REG_HMEBOX_E2_E3_8197F */\n\n#define BIT_SHIFT_HOST_MSG_E3_8197F 16\n#define BIT_MASK_HOST_MSG_E3_8197F 0xffff\n#define BIT_HOST_MSG_E3_8197F(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E3_8197F) << BIT_SHIFT_HOST_MSG_E3_8197F)\n#define BITS_HOST_MSG_E3_8197F                                                 \\\n\t(BIT_MASK_HOST_MSG_E3_8197F << BIT_SHIFT_HOST_MSG_E3_8197F)\n#define BIT_CLEAR_HOST_MSG_E3_8197F(x) ((x) & (~BITS_HOST_MSG_E3_8197F))\n#define BIT_GET_HOST_MSG_E3_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E3_8197F) & BIT_MASK_HOST_MSG_E3_8197F)\n#define BIT_SET_HOST_MSG_E3_8197F(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E3_8197F(x) | BIT_HOST_MSG_E3_8197F(v))\n\n#define BIT_SHIFT_HOST_MSG_E2_8197F 0\n#define BIT_MASK_HOST_MSG_E2_8197F 0xffff\n#define BIT_HOST_MSG_E2_8197F(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E2_8197F) << BIT_SHIFT_HOST_MSG_E2_8197F)\n#define BITS_HOST_MSG_E2_8197F                                                 \\\n\t(BIT_MASK_HOST_MSG_E2_8197F << BIT_SHIFT_HOST_MSG_E2_8197F)\n#define BIT_CLEAR_HOST_MSG_E2_8197F(x) ((x) & (~BITS_HOST_MSG_E2_8197F))\n#define BIT_GET_HOST_MSG_E2_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E2_8197F) & BIT_MASK_HOST_MSG_E2_8197F)\n#define BIT_SET_HOST_MSG_E2_8197F(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E2_8197F(x) | BIT_HOST_MSG_E2_8197F(v))\n\n/* 2 REG_WLLPS_CTRL_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_AFE_CTRL5_8197F */\n#define BIT_BB_DBG_SEL_AFE_SDM_V3_8197F BIT(31)\n#define BIT_ORDER_SDM_8197F BIT(30)\n#define BIT_RFE_SEL_SDM_8197F BIT(29)\n\n#define BIT_SHIFT_REF_SEL_8197F 25\n#define BIT_MASK_REF_SEL_8197F 0xf\n#define BIT_REF_SEL_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_REF_SEL_8197F) << BIT_SHIFT_REF_SEL_8197F)\n#define BITS_REF_SEL_8197F (BIT_MASK_REF_SEL_8197F << BIT_SHIFT_REF_SEL_8197F)\n#define BIT_CLEAR_REF_SEL_8197F(x) ((x) & (~BITS_REF_SEL_8197F))\n#define BIT_GET_REF_SEL_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_REF_SEL_8197F) & BIT_MASK_REF_SEL_8197F)\n#define BIT_SET_REF_SEL_8197F(x, v)                                            \\\n\t(BIT_CLEAR_REF_SEL_8197F(x) | BIT_REF_SEL_8197F(v))\n\n#define BIT_SHIFT_F0F_SDM_V2_8197F 12\n#define BIT_MASK_F0F_SDM_V2_8197F 0x1fff\n#define BIT_F0F_SDM_V2_8197F(x)                                                \\\n\t(((x) & BIT_MASK_F0F_SDM_V2_8197F) << BIT_SHIFT_F0F_SDM_V2_8197F)\n#define BITS_F0F_SDM_V2_8197F                                                  \\\n\t(BIT_MASK_F0F_SDM_V2_8197F << BIT_SHIFT_F0F_SDM_V2_8197F)\n#define BIT_CLEAR_F0F_SDM_V2_8197F(x) ((x) & (~BITS_F0F_SDM_V2_8197F))\n#define BIT_GET_F0F_SDM_V2_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_F0F_SDM_V2_8197F) & BIT_MASK_F0F_SDM_V2_8197F)\n#define BIT_SET_F0F_SDM_V2_8197F(x, v)                                         \\\n\t(BIT_CLEAR_F0F_SDM_V2_8197F(x) | BIT_F0F_SDM_V2_8197F(v))\n\n#define BIT_SHIFT_F0N_SDM_V2_8197F 9\n#define BIT_MASK_F0N_SDM_V2_8197F 0x7\n#define BIT_F0N_SDM_V2_8197F(x)                                                \\\n\t(((x) & BIT_MASK_F0N_SDM_V2_8197F) << BIT_SHIFT_F0N_SDM_V2_8197F)\n#define BITS_F0N_SDM_V2_8197F                                                  \\\n\t(BIT_MASK_F0N_SDM_V2_8197F << BIT_SHIFT_F0N_SDM_V2_8197F)\n#define BIT_CLEAR_F0N_SDM_V2_8197F(x) ((x) & (~BITS_F0N_SDM_V2_8197F))\n#define BIT_GET_F0N_SDM_V2_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_F0N_SDM_V2_8197F) & BIT_MASK_F0N_SDM_V2_8197F)\n#define BIT_SET_F0N_SDM_V2_8197F(x, v)                                         \\\n\t(BIT_CLEAR_F0N_SDM_V2_8197F(x) | BIT_F0N_SDM_V2_8197F(v))\n\n#define BIT_SHIFT_DIVN_SDM_V2_8197F 3\n#define BIT_MASK_DIVN_SDM_V2_8197F 0x3f\n#define BIT_DIVN_SDM_V2_8197F(x)                                               \\\n\t(((x) & BIT_MASK_DIVN_SDM_V2_8197F) << BIT_SHIFT_DIVN_SDM_V2_8197F)\n#define BITS_DIVN_SDM_V2_8197F                                                 \\\n\t(BIT_MASK_DIVN_SDM_V2_8197F << BIT_SHIFT_DIVN_SDM_V2_8197F)\n#define BIT_CLEAR_DIVN_SDM_V2_8197F(x) ((x) & (~BITS_DIVN_SDM_V2_8197F))\n#define BIT_GET_DIVN_SDM_V2_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_DIVN_SDM_V2_8197F) & BIT_MASK_DIVN_SDM_V2_8197F)\n#define BIT_SET_DIVN_SDM_V2_8197F(x, v)                                        \\\n\t(BIT_CLEAR_DIVN_SDM_V2_8197F(x) | BIT_DIVN_SDM_V2_8197F(v))\n\n#define BIT_SHIFT_DITHER_SDM_V2_8197F 0\n#define BIT_MASK_DITHER_SDM_V2_8197F 0x7\n#define BIT_DITHER_SDM_V2_8197F(x)                                             \\\n\t(((x) & BIT_MASK_DITHER_SDM_V2_8197F) << BIT_SHIFT_DITHER_SDM_V2_8197F)\n#define BITS_DITHER_SDM_V2_8197F                                               \\\n\t(BIT_MASK_DITHER_SDM_V2_8197F << BIT_SHIFT_DITHER_SDM_V2_8197F)\n#define BIT_CLEAR_DITHER_SDM_V2_8197F(x) ((x) & (~BITS_DITHER_SDM_V2_8197F))\n#define BIT_GET_DITHER_SDM_V2_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_DITHER_SDM_V2_8197F) & BIT_MASK_DITHER_SDM_V2_8197F)\n#define BIT_SET_DITHER_SDM_V2_8197F(x, v)                                      \\\n\t(BIT_CLEAR_DITHER_SDM_V2_8197F(x) | BIT_DITHER_SDM_V2_8197F(v))\n\n/* 2 REG_GPIO_DEBOUNCE_CTRL_8197F */\n#define BIT_WLGP_DBC1EN_8197F BIT(15)\n\n#define BIT_SHIFT_WLGP_DBC1_8197F 8\n#define BIT_MASK_WLGP_DBC1_8197F 0xf\n#define BIT_WLGP_DBC1_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_WLGP_DBC1_8197F) << BIT_SHIFT_WLGP_DBC1_8197F)\n#define BITS_WLGP_DBC1_8197F                                                   \\\n\t(BIT_MASK_WLGP_DBC1_8197F << BIT_SHIFT_WLGP_DBC1_8197F)\n#define BIT_CLEAR_WLGP_DBC1_8197F(x) ((x) & (~BITS_WLGP_DBC1_8197F))\n#define BIT_GET_WLGP_DBC1_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_WLGP_DBC1_8197F) & BIT_MASK_WLGP_DBC1_8197F)\n#define BIT_SET_WLGP_DBC1_8197F(x, v)                                          \\\n\t(BIT_CLEAR_WLGP_DBC1_8197F(x) | BIT_WLGP_DBC1_8197F(v))\n\n#define BIT_WLGP_DBC0EN_8197F BIT(7)\n\n#define BIT_SHIFT_WLGP_DBC0_8197F 0\n#define BIT_MASK_WLGP_DBC0_8197F 0xf\n#define BIT_WLGP_DBC0_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_WLGP_DBC0_8197F) << BIT_SHIFT_WLGP_DBC0_8197F)\n#define BITS_WLGP_DBC0_8197F                                                   \\\n\t(BIT_MASK_WLGP_DBC0_8197F << BIT_SHIFT_WLGP_DBC0_8197F)\n#define BIT_CLEAR_WLGP_DBC0_8197F(x) ((x) & (~BITS_WLGP_DBC0_8197F))\n#define BIT_GET_WLGP_DBC0_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_WLGP_DBC0_8197F) & BIT_MASK_WLGP_DBC0_8197F)\n#define BIT_SET_WLGP_DBC0_8197F(x, v)                                          \\\n\t(BIT_CLEAR_WLGP_DBC0_8197F(x) | BIT_WLGP_DBC0_8197F(v))\n\n/* 2 REG_RPWM2_8197F */\n\n#define BIT_SHIFT_RPWM2_8197F 16\n#define BIT_MASK_RPWM2_8197F 0xffff\n#define BIT_RPWM2_8197F(x)                                                     \\\n\t(((x) & BIT_MASK_RPWM2_8197F) << BIT_SHIFT_RPWM2_8197F)\n#define BITS_RPWM2_8197F (BIT_MASK_RPWM2_8197F << BIT_SHIFT_RPWM2_8197F)\n#define BIT_CLEAR_RPWM2_8197F(x) ((x) & (~BITS_RPWM2_8197F))\n#define BIT_GET_RPWM2_8197F(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RPWM2_8197F) & BIT_MASK_RPWM2_8197F)\n#define BIT_SET_RPWM2_8197F(x, v)                                              \\\n\t(BIT_CLEAR_RPWM2_8197F(x) | BIT_RPWM2_8197F(v))\n\n/* 2 REG_SYSON_FSM_MON_8197F */\n\n#define BIT_SHIFT_FSM_MON_SEL_8197F 24\n#define BIT_MASK_FSM_MON_SEL_8197F 0x7\n#define BIT_FSM_MON_SEL_8197F(x)                                               \\\n\t(((x) & BIT_MASK_FSM_MON_SEL_8197F) << BIT_SHIFT_FSM_MON_SEL_8197F)\n#define BITS_FSM_MON_SEL_8197F                                                 \\\n\t(BIT_MASK_FSM_MON_SEL_8197F << BIT_SHIFT_FSM_MON_SEL_8197F)\n#define BIT_CLEAR_FSM_MON_SEL_8197F(x) ((x) & (~BITS_FSM_MON_SEL_8197F))\n#define BIT_GET_FSM_MON_SEL_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_FSM_MON_SEL_8197F) & BIT_MASK_FSM_MON_SEL_8197F)\n#define BIT_SET_FSM_MON_SEL_8197F(x, v)                                        \\\n\t(BIT_CLEAR_FSM_MON_SEL_8197F(x) | BIT_FSM_MON_SEL_8197F(v))\n\n#define BIT_DOP_ELDO_8197F BIT(23)\n#define BIT_FSM_MON_UPD_8197F BIT(15)\n\n#define BIT_SHIFT_FSM_PAR_8197F 0\n#define BIT_MASK_FSM_PAR_8197F 0x7fff\n#define BIT_FSM_PAR_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_FSM_PAR_8197F) << BIT_SHIFT_FSM_PAR_8197F)\n#define BITS_FSM_PAR_8197F (BIT_MASK_FSM_PAR_8197F << BIT_SHIFT_FSM_PAR_8197F)\n#define BIT_CLEAR_FSM_PAR_8197F(x) ((x) & (~BITS_FSM_PAR_8197F))\n#define BIT_GET_FSM_PAR_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_FSM_PAR_8197F) & BIT_MASK_FSM_PAR_8197F)\n#define BIT_SET_FSM_PAR_8197F(x, v)                                            \\\n\t(BIT_CLEAR_FSM_PAR_8197F(x) | BIT_FSM_PAR_8197F(v))\n\n/* 2 REG_AFE_CTRL6_8197F */\n\n#define BIT_SHIFT_TSFT_SEL_V1_8197F 0\n#define BIT_MASK_TSFT_SEL_V1_8197F 0x7\n#define BIT_TSFT_SEL_V1_8197F(x)                                               \\\n\t(((x) & BIT_MASK_TSFT_SEL_V1_8197F) << BIT_SHIFT_TSFT_SEL_V1_8197F)\n#define BITS_TSFT_SEL_V1_8197F                                                 \\\n\t(BIT_MASK_TSFT_SEL_V1_8197F << BIT_SHIFT_TSFT_SEL_V1_8197F)\n#define BIT_CLEAR_TSFT_SEL_V1_8197F(x) ((x) & (~BITS_TSFT_SEL_V1_8197F))\n#define BIT_GET_TSFT_SEL_V1_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_TSFT_SEL_V1_8197F) & BIT_MASK_TSFT_SEL_V1_8197F)\n#define BIT_SET_TSFT_SEL_V1_8197F(x, v)                                        \\\n\t(BIT_CLEAR_TSFT_SEL_V1_8197F(x) | BIT_TSFT_SEL_V1_8197F(v))\n\n/* 2 REG_PMC_DBG_CTRL1_8197F */\n#define BIT_BT_INT_EN_8197F BIT(31)\n\n#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F 16\n#define BIT_MASK_RD_WR_WIFI_BT_INFO_8197F 0x7fff\n#define BIT_RD_WR_WIFI_BT_INFO_8197F(x)                                        \\\n\t(((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8197F)                             \\\n\t << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F)\n#define BITS_RD_WR_WIFI_BT_INFO_8197F                                          \\\n\t(BIT_MASK_RD_WR_WIFI_BT_INFO_8197F                                     \\\n\t << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F)\n#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8197F(x)                                  \\\n\t((x) & (~BITS_RD_WR_WIFI_BT_INFO_8197F))\n#define BIT_GET_RD_WR_WIFI_BT_INFO_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) &                         \\\n\t BIT_MASK_RD_WR_WIFI_BT_INFO_8197F)\n#define BIT_SET_RD_WR_WIFI_BT_INFO_8197F(x, v)                                 \\\n\t(BIT_CLEAR_RD_WR_WIFI_BT_INFO_8197F(x) |                               \\\n\t BIT_RD_WR_WIFI_BT_INFO_8197F(v))\n\n#define BIT_PMC_WR_OVF_8197F BIT(8)\n\n#define BIT_SHIFT_WLPMC_ERRINT_8197F 0\n#define BIT_MASK_WLPMC_ERRINT_8197F 0xff\n#define BIT_WLPMC_ERRINT_8197F(x)                                              \\\n\t(((x) & BIT_MASK_WLPMC_ERRINT_8197F) << BIT_SHIFT_WLPMC_ERRINT_8197F)\n#define BITS_WLPMC_ERRINT_8197F                                                \\\n\t(BIT_MASK_WLPMC_ERRINT_8197F << BIT_SHIFT_WLPMC_ERRINT_8197F)\n#define BIT_CLEAR_WLPMC_ERRINT_8197F(x) ((x) & (~BITS_WLPMC_ERRINT_8197F))\n#define BIT_GET_WLPMC_ERRINT_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_WLPMC_ERRINT_8197F) & BIT_MASK_WLPMC_ERRINT_8197F)\n#define BIT_SET_WLPMC_ERRINT_8197F(x, v)                                       \\\n\t(BIT_CLEAR_WLPMC_ERRINT_8197F(x) | BIT_WLPMC_ERRINT_8197F(v))\n\n/* 2 REG_AFE_CTRL7_8197F */\n\n#define BIT_SHIFT_SEL_V_8197F 30\n#define BIT_MASK_SEL_V_8197F 0x3\n#define BIT_SEL_V_8197F(x)                                                     \\\n\t(((x) & BIT_MASK_SEL_V_8197F) << BIT_SHIFT_SEL_V_8197F)\n#define BITS_SEL_V_8197F (BIT_MASK_SEL_V_8197F << BIT_SHIFT_SEL_V_8197F)\n#define BIT_CLEAR_SEL_V_8197F(x) ((x) & (~BITS_SEL_V_8197F))\n#define BIT_GET_SEL_V_8197F(x)                                                 \\\n\t(((x) >> BIT_SHIFT_SEL_V_8197F) & BIT_MASK_SEL_V_8197F)\n#define BIT_SET_SEL_V_8197F(x, v)                                              \\\n\t(BIT_CLEAR_SEL_V_8197F(x) | BIT_SEL_V_8197F(v))\n\n#define BIT_SEL_LDO_PC_8197F BIT(29)\n\n#define BIT_SHIFT_CK_MON_SEL_V2_8197F 26\n#define BIT_MASK_CK_MON_SEL_V2_8197F 0x7\n#define BIT_CK_MON_SEL_V2_8197F(x)                                             \\\n\t(((x) & BIT_MASK_CK_MON_SEL_V2_8197F) << BIT_SHIFT_CK_MON_SEL_V2_8197F)\n#define BITS_CK_MON_SEL_V2_8197F                                               \\\n\t(BIT_MASK_CK_MON_SEL_V2_8197F << BIT_SHIFT_CK_MON_SEL_V2_8197F)\n#define BIT_CLEAR_CK_MON_SEL_V2_8197F(x) ((x) & (~BITS_CK_MON_SEL_V2_8197F))\n#define BIT_GET_CK_MON_SEL_V2_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_CK_MON_SEL_V2_8197F) & BIT_MASK_CK_MON_SEL_V2_8197F)\n#define BIT_SET_CK_MON_SEL_V2_8197F(x, v)                                      \\\n\t(BIT_CLEAR_CK_MON_SEL_V2_8197F(x) | BIT_CK_MON_SEL_V2_8197F(v))\n\n#define BIT_CK_MON_EN_8197F BIT(25)\n#define BIT_FREF_EDGE_8197F BIT(24)\n#define BIT_CK320M_EN_8197F BIT(23)\n#define BIT_CK_5M_EN_8197F BIT(22)\n#define BIT_TESTEN_8197F BIT(21)\n\n/* 2 REG_HIMR0_8197F */\n#define BIT_TIMEOUT_INTERRUPT2_MASK_8197F BIT(31)\n#define BIT_TIMEOUT_INTERRUTP1_MASK_8197F BIT(30)\n#define BIT_PSTIMEOUT_MSK_8197F BIT(29)\n#define BIT_GTINT4_MSK_8197F BIT(28)\n#define BIT_GTINT3_MSK_8197F BIT(27)\n#define BIT_TXBCN0ERR_MSK_8197F BIT(26)\n#define BIT_TXBCN0OK_MSK_8197F BIT(25)\n#define BIT_TSF_BIT32_TOGGLE_MSK_8197F BIT(24)\n#define BIT_BCNDMAINT0_MSK_8197F BIT(20)\n#define BIT_BCNDERR0_MSK_8197F BIT(16)\n#define BIT_HSISR_IND_ON_INT_MSK_8197F BIT(15)\n#define BIT_HISR3_IND_INT_MSK_8197F BIT(14)\n#define BIT_HISR2_IND_INT_MSK_8197F BIT(13)\n#define BIT_CTWEND_MSK_8197F BIT(12)\n#define BIT_HISR1_IND_MSK_8197F BIT(11)\n#define BIT_C2HCMD_MSK_8197F BIT(10)\n#define BIT_CPWM2_MSK_8197F BIT(9)\n#define BIT_CPWM_MSK_8197F BIT(8)\n#define BIT_HIGHDOK_MSK_8197F BIT(7)\n#define BIT_MGTDOK_MSK_8197F BIT(6)\n#define BIT_BKDOK_MSK_8197F BIT(5)\n#define BIT_BEDOK_MSK_8197F BIT(4)\n#define BIT_VIDOK_MSK_8197F BIT(3)\n#define BIT_VODOK_MSK_8197F BIT(2)\n#define BIT_RDU_MSK_8197F BIT(1)\n#define BIT_RXOK_MSK_8197F BIT(0)\n\n/* 2 REG_HISR0_8197F */\n#define BIT_PSTIMEOUT2_8197F BIT(31)\n#define BIT_PSTIMEOUT1_8197F BIT(30)\n#define BIT_PSTIMEOUT_8197F BIT(29)\n#define BIT_GTINT4_8197F BIT(28)\n#define BIT_GTINT3_8197F BIT(27)\n#define BIT_TXBCN0ERR_8197F BIT(26)\n#define BIT_TXBCN0OK_8197F BIT(25)\n#define BIT_TSF_BIT32_TOGGLE_8197F BIT(24)\n#define BIT_BCNDMAINT0_8197F BIT(20)\n#define BIT_BCNDERR0_8197F BIT(16)\n#define BIT_HSISR_IND_ON_INT_8197F BIT(15)\n#define BIT_HISR3_IND_INT_8197F BIT(14)\n#define BIT_HISR2_IND_INT_8197F BIT(13)\n#define BIT_CTWEND_8197F BIT(12)\n#define BIT_HISR1_IND_INT_8197F BIT(11)\n#define BIT_C2HCMD_8197F BIT(10)\n#define BIT_CPWM2_8197F BIT(9)\n#define BIT_CPWM_8197F BIT(8)\n#define BIT_HIGHDOK_8197F BIT(7)\n#define BIT_MGTDOK_8197F BIT(6)\n#define BIT_BKDOK_8197F BIT(5)\n#define BIT_BEDOK_8197F BIT(4)\n#define BIT_VIDOK_8197F BIT(3)\n#define BIT_VODOK_8197F BIT(2)\n#define BIT_RDU_8197F BIT(1)\n#define BIT_RXOK_8197F BIT(0)\n\n/* 2 REG_HIMR1_8197F */\n#define BIT_BTON_STS_UPDATE_MSK_8197F BIT(29)\n#define BIT_MCU_ERR_MASK_8197F BIT(28)\n#define BIT_BCNDMAINT7__MSK_8197F BIT(27)\n#define BIT_BCNDMAINT6__MSK_8197F BIT(26)\n#define BIT_BCNDMAINT5__MSK_8197F BIT(25)\n#define BIT_BCNDMAINT4__MSK_8197F BIT(24)\n#define BIT_BCNDMAINT3_MSK_8197F BIT(23)\n#define BIT_BCNDMAINT2_MSK_8197F BIT(22)\n#define BIT_BCNDMAINT1_MSK_8197F BIT(21)\n#define BIT_BCNDERR7_MSK_8197F BIT(20)\n#define BIT_BCNDERR6_MSK_8197F BIT(19)\n#define BIT_BCNDERR5_MSK_8197F BIT(18)\n#define BIT_BCNDERR4_MSK_8197F BIT(17)\n#define BIT_BCNDERR3_MSK_8197F BIT(16)\n#define BIT_BCNDERR2_MSK_8197F BIT(15)\n#define BIT_BCNDERR1_MSK_8197F BIT(14)\n#define BIT_ATIMEND_E_MSK_8197F BIT(13)\n#define BIT_ATIMEND__MSK_8197F BIT(12)\n#define BIT_TXERR_MSK_8197F BIT(11)\n#define BIT_RXERR_MSK_8197F BIT(10)\n#define BIT_TXFOVW_MSK_8197F BIT(9)\n#define BIT_FOVW_MSK_8197F BIT(8)\n\n/* 2 REG_HISR1_8197F */\n#define BIT_BTON_STS_UPDATE_INT_8197F BIT(29)\n#define BIT_MCU_ERR_8197F BIT(28)\n#define BIT_BCNDMAINT7_8197F BIT(27)\n#define BIT_BCNDMAINT6_8197F BIT(26)\n#define BIT_BCNDMAINT5_8197F BIT(25)\n#define BIT_BCNDMAINT4_8197F BIT(24)\n#define BIT_BCNDMAINT3_8197F BIT(23)\n#define BIT_BCNDMAINT2_8197F BIT(22)\n#define BIT_BCNDMAINT1_8197F BIT(21)\n#define BIT_BCNDERR7_8197F BIT(20)\n#define BIT_BCNDERR6_8197F BIT(19)\n#define BIT_BCNDERR5_8197F BIT(18)\n#define BIT_BCNDERR4_8197F BIT(17)\n#define BIT_BCNDERR3_8197F BIT(16)\n#define BIT_BCNDERR2_8197F BIT(15)\n#define BIT_BCNDERR1_8197F BIT(14)\n#define BIT_ATIMEND_E_8197F BIT(13)\n#define BIT_ATIMEND_8197F BIT(12)\n#define BIT_TXERR_INT_8197F BIT(11)\n#define BIT_RXERR_INT_8197F BIT(10)\n#define BIT_TXFOVW_8197F BIT(9)\n#define BIT_FOVW_8197F BIT(8)\n\n/* 2 REG_DBG_PORT_SEL_8197F */\n\n#define BIT_SHIFT_DEBUG_ST_8197F 0\n#define BIT_MASK_DEBUG_ST_8197F 0xffffffffL\n#define BIT_DEBUG_ST_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_DEBUG_ST_8197F) << BIT_SHIFT_DEBUG_ST_8197F)\n#define BITS_DEBUG_ST_8197F                                                    \\\n\t(BIT_MASK_DEBUG_ST_8197F << BIT_SHIFT_DEBUG_ST_8197F)\n#define BIT_CLEAR_DEBUG_ST_8197F(x) ((x) & (~BITS_DEBUG_ST_8197F))\n#define BIT_GET_DEBUG_ST_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_DEBUG_ST_8197F) & BIT_MASK_DEBUG_ST_8197F)\n#define BIT_SET_DEBUG_ST_8197F(x, v)                                           \\\n\t(BIT_CLEAR_DEBUG_ST_8197F(x) | BIT_DEBUG_ST_8197F(v))\n\n/* 2 REG_PAD_CTRL2_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n#define BIT_LD_B12V_EN_V1_8197F BIT(7)\n#define BIT_EECS_IOSEL_V1_8197F BIT(6)\n#define BIT_EECS_DATA_O_V1_8197F BIT(5)\n#define BIT_EECS_DATA_I_V1_8197F BIT(4)\n#define BIT_EESK_IOSEL_V1_8197F BIT(2)\n#define BIT_EESK_DATA_O_V1_8197F BIT(1)\n#define BIT_EESK_DATA_I_V1_8197F BIT(0)\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_PMC_DBG_CTRL2_8197F */\n\n#define BIT_SHIFT_EFUSE_BURN_GNT_8197F 24\n#define BIT_MASK_EFUSE_BURN_GNT_8197F 0xff\n#define BIT_EFUSE_BURN_GNT_8197F(x)                                            \\\n\t(((x) & BIT_MASK_EFUSE_BURN_GNT_8197F)                                 \\\n\t << BIT_SHIFT_EFUSE_BURN_GNT_8197F)\n#define BITS_EFUSE_BURN_GNT_8197F                                              \\\n\t(BIT_MASK_EFUSE_BURN_GNT_8197F << BIT_SHIFT_EFUSE_BURN_GNT_8197F)\n#define BIT_CLEAR_EFUSE_BURN_GNT_8197F(x) ((x) & (~BITS_EFUSE_BURN_GNT_8197F))\n#define BIT_GET_EFUSE_BURN_GNT_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8197F) &                             \\\n\t BIT_MASK_EFUSE_BURN_GNT_8197F)\n#define BIT_SET_EFUSE_BURN_GNT_8197F(x, v)                                     \\\n\t(BIT_CLEAR_EFUSE_BURN_GNT_8197F(x) | BIT_EFUSE_BURN_GNT_8197F(v))\n\n#define BIT_STOP_WL_PMC_8197F BIT(9)\n#define BIT_STOP_SYM_PMC_8197F BIT(8)\n#define BIT_REG_RST_WLPMC_8197F BIT(5)\n#define BIT_REG_RST_PD12N_8197F BIT(4)\n#define BIT_SYSON_DIS_WLREG_WRMSK_8197F BIT(3)\n#define BIT_SYSON_DIS_PMCREG_WRMSK_8197F BIT(2)\n\n#define BIT_SHIFT_SYSON_REG_ARB_8197F 0\n#define BIT_MASK_SYSON_REG_ARB_8197F 0x3\n#define BIT_SYSON_REG_ARB_8197F(x)                                             \\\n\t(((x) & BIT_MASK_SYSON_REG_ARB_8197F) << BIT_SHIFT_SYSON_REG_ARB_8197F)\n#define BITS_SYSON_REG_ARB_8197F                                               \\\n\t(BIT_MASK_SYSON_REG_ARB_8197F << BIT_SHIFT_SYSON_REG_ARB_8197F)\n#define BIT_CLEAR_SYSON_REG_ARB_8197F(x) ((x) & (~BITS_SYSON_REG_ARB_8197F))\n#define BIT_GET_SYSON_REG_ARB_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_SYSON_REG_ARB_8197F) & BIT_MASK_SYSON_REG_ARB_8197F)\n#define BIT_SET_SYSON_REG_ARB_8197F(x, v)                                      \\\n\t(BIT_CLEAR_SYSON_REG_ARB_8197F(x) | BIT_SYSON_REG_ARB_8197F(v))\n\n/* 2 REG_BIST_CTRL_8197F */\n#define BIT_BIST_USB_DIS_8197F BIT(27)\n#define BIT_BIST_PCI_DIS_8197F BIT(26)\n#define BIT_BIST_BT_DIS_8197F BIT(25)\n#define BIT_BIST_WL_DIS_8197F BIT(24)\n\n#define BIT_SHIFT_BIST_RPT_SEL_8197F 16\n#define BIT_MASK_BIST_RPT_SEL_8197F 0xf\n#define BIT_BIST_RPT_SEL_8197F(x)                                              \\\n\t(((x) & BIT_MASK_BIST_RPT_SEL_8197F) << BIT_SHIFT_BIST_RPT_SEL_8197F)\n#define BITS_BIST_RPT_SEL_8197F                                                \\\n\t(BIT_MASK_BIST_RPT_SEL_8197F << BIT_SHIFT_BIST_RPT_SEL_8197F)\n#define BIT_CLEAR_BIST_RPT_SEL_8197F(x) ((x) & (~BITS_BIST_RPT_SEL_8197F))\n#define BIT_GET_BIST_RPT_SEL_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_BIST_RPT_SEL_8197F) & BIT_MASK_BIST_RPT_SEL_8197F)\n#define BIT_SET_BIST_RPT_SEL_8197F(x, v)                                       \\\n\t(BIT_CLEAR_BIST_RPT_SEL_8197F(x) | BIT_BIST_RPT_SEL_8197F(v))\n\n#define BIT_BIST_RESUME_PS_8197F BIT(4)\n#define BIT_BIST_RESUME_8197F BIT(3)\n#define BIT_BIST_NORMAL_8197F BIT(2)\n#define BIT_BIST_RSTN_8197F BIT(1)\n#define BIT_BIST_CLK_EN_8197F BIT(0)\n\n/* 2 REG_BIST_RPT_8197F */\n\n#define BIT_SHIFT_MBIST_REPORT_8197F 0\n#define BIT_MASK_MBIST_REPORT_8197F 0xffffffffL\n#define BIT_MBIST_REPORT_8197F(x)                                              \\\n\t(((x) & BIT_MASK_MBIST_REPORT_8197F) << BIT_SHIFT_MBIST_REPORT_8197F)\n#define BITS_MBIST_REPORT_8197F                                                \\\n\t(BIT_MASK_MBIST_REPORT_8197F << BIT_SHIFT_MBIST_REPORT_8197F)\n#define BIT_CLEAR_MBIST_REPORT_8197F(x) ((x) & (~BITS_MBIST_REPORT_8197F))\n#define BIT_GET_MBIST_REPORT_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_MBIST_REPORT_8197F) & BIT_MASK_MBIST_REPORT_8197F)\n#define BIT_SET_MBIST_REPORT_8197F(x, v)                                       \\\n\t(BIT_CLEAR_MBIST_REPORT_8197F(x) | BIT_MBIST_REPORT_8197F(v))\n\n/* 2 REG_MEM_CTRL_8197F */\n#define BIT_UMEM_RME_8197F BIT(31)\n\n#define BIT_SHIFT_BT_SPRAM_8197F 28\n#define BIT_MASK_BT_SPRAM_8197F 0x3\n#define BIT_BT_SPRAM_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_BT_SPRAM_8197F) << BIT_SHIFT_BT_SPRAM_8197F)\n#define BITS_BT_SPRAM_8197F                                                    \\\n\t(BIT_MASK_BT_SPRAM_8197F << BIT_SHIFT_BT_SPRAM_8197F)\n#define BIT_CLEAR_BT_SPRAM_8197F(x) ((x) & (~BITS_BT_SPRAM_8197F))\n#define BIT_GET_BT_SPRAM_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_BT_SPRAM_8197F) & BIT_MASK_BT_SPRAM_8197F)\n#define BIT_SET_BT_SPRAM_8197F(x, v)                                           \\\n\t(BIT_CLEAR_BT_SPRAM_8197F(x) | BIT_BT_SPRAM_8197F(v))\n\n#define BIT_SHIFT_BT_ROM_8197F 24\n#define BIT_MASK_BT_ROM_8197F 0xf\n#define BIT_BT_ROM_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_BT_ROM_8197F) << BIT_SHIFT_BT_ROM_8197F)\n#define BITS_BT_ROM_8197F (BIT_MASK_BT_ROM_8197F << BIT_SHIFT_BT_ROM_8197F)\n#define BIT_CLEAR_BT_ROM_8197F(x) ((x) & (~BITS_BT_ROM_8197F))\n#define BIT_GET_BT_ROM_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_BT_ROM_8197F) & BIT_MASK_BT_ROM_8197F)\n#define BIT_SET_BT_ROM_8197F(x, v)                                             \\\n\t(BIT_CLEAR_BT_ROM_8197F(x) | BIT_BT_ROM_8197F(v))\n\n#define BIT_SHIFT_PCI_DPRAM_8197F 10\n#define BIT_MASK_PCI_DPRAM_8197F 0x3\n#define BIT_PCI_DPRAM_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_PCI_DPRAM_8197F) << BIT_SHIFT_PCI_DPRAM_8197F)\n#define BITS_PCI_DPRAM_8197F                                                   \\\n\t(BIT_MASK_PCI_DPRAM_8197F << BIT_SHIFT_PCI_DPRAM_8197F)\n#define BIT_CLEAR_PCI_DPRAM_8197F(x) ((x) & (~BITS_PCI_DPRAM_8197F))\n#define BIT_GET_PCI_DPRAM_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_PCI_DPRAM_8197F) & BIT_MASK_PCI_DPRAM_8197F)\n#define BIT_SET_PCI_DPRAM_8197F(x, v)                                          \\\n\t(BIT_CLEAR_PCI_DPRAM_8197F(x) | BIT_PCI_DPRAM_8197F(v))\n\n#define BIT_SHIFT_PCI_SPRAM_8197F 8\n#define BIT_MASK_PCI_SPRAM_8197F 0x3\n#define BIT_PCI_SPRAM_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_PCI_SPRAM_8197F) << BIT_SHIFT_PCI_SPRAM_8197F)\n#define BITS_PCI_SPRAM_8197F                                                   \\\n\t(BIT_MASK_PCI_SPRAM_8197F << BIT_SHIFT_PCI_SPRAM_8197F)\n#define BIT_CLEAR_PCI_SPRAM_8197F(x) ((x) & (~BITS_PCI_SPRAM_8197F))\n#define BIT_GET_PCI_SPRAM_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_PCI_SPRAM_8197F) & BIT_MASK_PCI_SPRAM_8197F)\n#define BIT_SET_PCI_SPRAM_8197F(x, v)                                          \\\n\t(BIT_CLEAR_PCI_SPRAM_8197F(x) | BIT_PCI_SPRAM_8197F(v))\n\n#define BIT_SHIFT_USB_SPRAM_8197F 6\n#define BIT_MASK_USB_SPRAM_8197F 0x3\n#define BIT_USB_SPRAM_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_USB_SPRAM_8197F) << BIT_SHIFT_USB_SPRAM_8197F)\n#define BITS_USB_SPRAM_8197F                                                   \\\n\t(BIT_MASK_USB_SPRAM_8197F << BIT_SHIFT_USB_SPRAM_8197F)\n#define BIT_CLEAR_USB_SPRAM_8197F(x) ((x) & (~BITS_USB_SPRAM_8197F))\n#define BIT_GET_USB_SPRAM_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_USB_SPRAM_8197F) & BIT_MASK_USB_SPRAM_8197F)\n#define BIT_SET_USB_SPRAM_8197F(x, v)                                          \\\n\t(BIT_CLEAR_USB_SPRAM_8197F(x) | BIT_USB_SPRAM_8197F(v))\n\n#define BIT_SHIFT_USB_SPRF_8197F 4\n#define BIT_MASK_USB_SPRF_8197F 0x3\n#define BIT_USB_SPRF_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_USB_SPRF_8197F) << BIT_SHIFT_USB_SPRF_8197F)\n#define BITS_USB_SPRF_8197F                                                    \\\n\t(BIT_MASK_USB_SPRF_8197F << BIT_SHIFT_USB_SPRF_8197F)\n#define BIT_CLEAR_USB_SPRF_8197F(x) ((x) & (~BITS_USB_SPRF_8197F))\n#define BIT_GET_USB_SPRF_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_USB_SPRF_8197F) & BIT_MASK_USB_SPRF_8197F)\n#define BIT_SET_USB_SPRF_8197F(x, v)                                           \\\n\t(BIT_CLEAR_USB_SPRF_8197F(x) | BIT_USB_SPRF_8197F(v))\n\n#define BIT_SHIFT_MCU_ROM_8197F 0\n#define BIT_MASK_MCU_ROM_8197F 0xf\n#define BIT_MCU_ROM_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_MCU_ROM_8197F) << BIT_SHIFT_MCU_ROM_8197F)\n#define BITS_MCU_ROM_8197F (BIT_MASK_MCU_ROM_8197F << BIT_SHIFT_MCU_ROM_8197F)\n#define BIT_CLEAR_MCU_ROM_8197F(x) ((x) & (~BITS_MCU_ROM_8197F))\n#define BIT_GET_MCU_ROM_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_MCU_ROM_8197F) & BIT_MASK_MCU_ROM_8197F)\n#define BIT_SET_MCU_ROM_8197F(x, v)                                            \\\n\t(BIT_CLEAR_MCU_ROM_8197F(x) | BIT_MCU_ROM_8197F(v))\n\n/* 2 REG_AFE_CTRL8_8197F */\n\n#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F 26\n#define BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F 0x7\n#define BIT_BB_DBG_SEL_AFE_SDM_V4_8197F(x)                                     \\\n\t(((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F)                          \\\n\t << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F)\n#define BITS_BB_DBG_SEL_AFE_SDM_V4_8197F                                       \\\n\t(BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F                                  \\\n\t << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F)\n#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4_8197F(x)                               \\\n\t((x) & (~BITS_BB_DBG_SEL_AFE_SDM_V4_8197F))\n#define BIT_GET_BB_DBG_SEL_AFE_SDM_V4_8197F(x)                                 \\\n\t(((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) &                      \\\n\t BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F)\n#define BIT_SET_BB_DBG_SEL_AFE_SDM_V4_8197F(x, v)                              \\\n\t(BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4_8197F(x) |                            \\\n\t BIT_BB_DBG_SEL_AFE_SDM_V4_8197F(v))\n\n#define BIT_SYN_AGPIO_8197F BIT(20)\n\n#define BIT_SHIFT_XTAL_SEL_TOK_V2_8197F 0\n#define BIT_MASK_XTAL_SEL_TOK_V2_8197F 0x7\n#define BIT_XTAL_SEL_TOK_V2_8197F(x)                                           \\\n\t(((x) & BIT_MASK_XTAL_SEL_TOK_V2_8197F)                                \\\n\t << BIT_SHIFT_XTAL_SEL_TOK_V2_8197F)\n#define BITS_XTAL_SEL_TOK_V2_8197F                                             \\\n\t(BIT_MASK_XTAL_SEL_TOK_V2_8197F << BIT_SHIFT_XTAL_SEL_TOK_V2_8197F)\n#define BIT_CLEAR_XTAL_SEL_TOK_V2_8197F(x) ((x) & (~BITS_XTAL_SEL_TOK_V2_8197F))\n#define BIT_GET_XTAL_SEL_TOK_V2_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) &                            \\\n\t BIT_MASK_XTAL_SEL_TOK_V2_8197F)\n#define BIT_SET_XTAL_SEL_TOK_V2_8197F(x, v)                                    \\\n\t(BIT_CLEAR_XTAL_SEL_TOK_V2_8197F(x) | BIT_XTAL_SEL_TOK_V2_8197F(v))\n\n/* 2 REG_USB_SIE_INTF_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_PCIE_MIO_INTF_8197F */\n#define BIT_PCIE_MIO_BYIOREG_8197F BIT(13)\n#define BIT_PCIE_MIO_RE_8197F BIT(12)\n\n#define BIT_SHIFT_PCIE_MIO_WE_8197F 8\n#define BIT_MASK_PCIE_MIO_WE_8197F 0xf\n#define BIT_PCIE_MIO_WE_8197F(x)                                               \\\n\t(((x) & BIT_MASK_PCIE_MIO_WE_8197F) << BIT_SHIFT_PCIE_MIO_WE_8197F)\n#define BITS_PCIE_MIO_WE_8197F                                                 \\\n\t(BIT_MASK_PCIE_MIO_WE_8197F << BIT_SHIFT_PCIE_MIO_WE_8197F)\n#define BIT_CLEAR_PCIE_MIO_WE_8197F(x) ((x) & (~BITS_PCIE_MIO_WE_8197F))\n#define BIT_GET_PCIE_MIO_WE_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_WE_8197F) & BIT_MASK_PCIE_MIO_WE_8197F)\n#define BIT_SET_PCIE_MIO_WE_8197F(x, v)                                        \\\n\t(BIT_CLEAR_PCIE_MIO_WE_8197F(x) | BIT_PCIE_MIO_WE_8197F(v))\n\n#define BIT_SHIFT_PCIE_MIO_ADDR_8197F 0\n#define BIT_MASK_PCIE_MIO_ADDR_8197F 0xff\n#define BIT_PCIE_MIO_ADDR_8197F(x)                                             \\\n\t(((x) & BIT_MASK_PCIE_MIO_ADDR_8197F) << BIT_SHIFT_PCIE_MIO_ADDR_8197F)\n#define BITS_PCIE_MIO_ADDR_8197F                                               \\\n\t(BIT_MASK_PCIE_MIO_ADDR_8197F << BIT_SHIFT_PCIE_MIO_ADDR_8197F)\n#define BIT_CLEAR_PCIE_MIO_ADDR_8197F(x) ((x) & (~BITS_PCIE_MIO_ADDR_8197F))\n#define BIT_GET_PCIE_MIO_ADDR_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8197F) & BIT_MASK_PCIE_MIO_ADDR_8197F)\n#define BIT_SET_PCIE_MIO_ADDR_8197F(x, v)                                      \\\n\t(BIT_CLEAR_PCIE_MIO_ADDR_8197F(x) | BIT_PCIE_MIO_ADDR_8197F(v))\n\n/* 2 REG_PCIE_MIO_INTD_8197F */\n\n#define BIT_SHIFT_PCIE_MIO_DATA_8197F 0\n#define BIT_MASK_PCIE_MIO_DATA_8197F 0xffffffffL\n#define BIT_PCIE_MIO_DATA_8197F(x)                                             \\\n\t(((x) & BIT_MASK_PCIE_MIO_DATA_8197F) << BIT_SHIFT_PCIE_MIO_DATA_8197F)\n#define BITS_PCIE_MIO_DATA_8197F                                               \\\n\t(BIT_MASK_PCIE_MIO_DATA_8197F << BIT_SHIFT_PCIE_MIO_DATA_8197F)\n#define BIT_CLEAR_PCIE_MIO_DATA_8197F(x) ((x) & (~BITS_PCIE_MIO_DATA_8197F))\n#define BIT_GET_PCIE_MIO_DATA_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_DATA_8197F) & BIT_MASK_PCIE_MIO_DATA_8197F)\n#define BIT_SET_PCIE_MIO_DATA_8197F(x, v)                                      \\\n\t(BIT_CLEAR_PCIE_MIO_DATA_8197F(x) | BIT_PCIE_MIO_DATA_8197F(v))\n\n/* 2 REG_WLRF1_8197F */\n\n/* 2 REG_SYS_CFG1_8197F */\n\n#define BIT_SHIFT_TRP_ICFG_8197F 28\n#define BIT_MASK_TRP_ICFG_8197F 0xf\n#define BIT_TRP_ICFG_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_TRP_ICFG_8197F) << BIT_SHIFT_TRP_ICFG_8197F)\n#define BITS_TRP_ICFG_8197F                                                    \\\n\t(BIT_MASK_TRP_ICFG_8197F << BIT_SHIFT_TRP_ICFG_8197F)\n#define BIT_CLEAR_TRP_ICFG_8197F(x) ((x) & (~BITS_TRP_ICFG_8197F))\n#define BIT_GET_TRP_ICFG_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_TRP_ICFG_8197F) & BIT_MASK_TRP_ICFG_8197F)\n#define BIT_SET_TRP_ICFG_8197F(x, v)                                           \\\n\t(BIT_CLEAR_TRP_ICFG_8197F(x) | BIT_TRP_ICFG_8197F(v))\n\n#define BIT_RF_TYPE_ID_8197F BIT(27)\n#define BIT_BD_HCI_SEL_8197F BIT(26)\n#define BIT_BD_PKG_SEL_8197F BIT(25)\n#define BIT_SPSLDO_SEL_8197F BIT(24)\n#define BIT_RTL_ID_8197F BIT(23)\n#define BIT_PAD_HWPD_IDN_8197F BIT(22)\n#define BIT_TESTMODE_8197F BIT(20)\n\n#define BIT_SHIFT_VENDOR_ID_8197F 16\n#define BIT_MASK_VENDOR_ID_8197F 0xf\n#define BIT_VENDOR_ID_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_VENDOR_ID_8197F) << BIT_SHIFT_VENDOR_ID_8197F)\n#define BITS_VENDOR_ID_8197F                                                   \\\n\t(BIT_MASK_VENDOR_ID_8197F << BIT_SHIFT_VENDOR_ID_8197F)\n#define BIT_CLEAR_VENDOR_ID_8197F(x) ((x) & (~BITS_VENDOR_ID_8197F))\n#define BIT_GET_VENDOR_ID_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_VENDOR_ID_8197F) & BIT_MASK_VENDOR_ID_8197F)\n#define BIT_SET_VENDOR_ID_8197F(x, v)                                          \\\n\t(BIT_CLEAR_VENDOR_ID_8197F(x) | BIT_VENDOR_ID_8197F(v))\n\n#define BIT_SHIFT_CHIP_VER_8197F 12\n#define BIT_MASK_CHIP_VER_8197F 0xf\n#define BIT_CHIP_VER_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_CHIP_VER_8197F) << BIT_SHIFT_CHIP_VER_8197F)\n#define BITS_CHIP_VER_8197F                                                    \\\n\t(BIT_MASK_CHIP_VER_8197F << BIT_SHIFT_CHIP_VER_8197F)\n#define BIT_CLEAR_CHIP_VER_8197F(x) ((x) & (~BITS_CHIP_VER_8197F))\n#define BIT_GET_CHIP_VER_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_CHIP_VER_8197F) & BIT_MASK_CHIP_VER_8197F)\n#define BIT_SET_CHIP_VER_8197F(x, v)                                           \\\n\t(BIT_CLEAR_CHIP_VER_8197F(x) | BIT_CHIP_VER_8197F(v))\n\n#define BIT_BD_MAC1_8197F BIT(10)\n#define BIT_BD_MAC2_8197F BIT(9)\n#define BIT_SIC_IDLE_8197F BIT(8)\n#define BIT_SW_OFFLOAD_EN_8197F BIT(7)\n#define BIT_OCP_SHUTDN_8197F BIT(6)\n#define BIT_V15_VLD_8197F BIT(5)\n#define BIT_PCIRSTB_8197F BIT(4)\n#define BIT_PCLK_VLD_8197F BIT(3)\n#define BIT_UCLK_VLD_8197F BIT(2)\n#define BIT_ACLK_VLD_8197F BIT(1)\n#define BIT_XCLK_VLD_8197F BIT(0)\n\n/* 2 REG_SYS_STATUS1_8197F */\n\n#define BIT_SHIFT_RF_RL_ID_8197F 28\n#define BIT_MASK_RF_RL_ID_8197F 0xf\n#define BIT_RF_RL_ID_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_RF_RL_ID_8197F) << BIT_SHIFT_RF_RL_ID_8197F)\n#define BITS_RF_RL_ID_8197F                                                    \\\n\t(BIT_MASK_RF_RL_ID_8197F << BIT_SHIFT_RF_RL_ID_8197F)\n#define BIT_CLEAR_RF_RL_ID_8197F(x) ((x) & (~BITS_RF_RL_ID_8197F))\n#define BIT_GET_RF_RL_ID_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_RF_RL_ID_8197F) & BIT_MASK_RF_RL_ID_8197F)\n#define BIT_SET_RF_RL_ID_8197F(x, v)                                           \\\n\t(BIT_CLEAR_RF_RL_ID_8197F(x) | BIT_RF_RL_ID_8197F(v))\n\n#define BIT_HPHY_ICFG_8197F BIT(19)\n\n#define BIT_SHIFT_SEL_0XC0_8197F 16\n#define BIT_MASK_SEL_0XC0_8197F 0x3\n#define BIT_SEL_0XC0_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_SEL_0XC0_8197F) << BIT_SHIFT_SEL_0XC0_8197F)\n#define BITS_SEL_0XC0_8197F                                                    \\\n\t(BIT_MASK_SEL_0XC0_8197F << BIT_SHIFT_SEL_0XC0_8197F)\n#define BIT_CLEAR_SEL_0XC0_8197F(x) ((x) & (~BITS_SEL_0XC0_8197F))\n#define BIT_GET_SEL_0XC0_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_SEL_0XC0_8197F) & BIT_MASK_SEL_0XC0_8197F)\n#define BIT_SET_SEL_0XC0_8197F(x, v)                                           \\\n\t(BIT_CLEAR_SEL_0XC0_8197F(x) | BIT_SEL_0XC0_8197F(v))\n\n#define BIT_USB_OPERATION_MODE_8197F BIT(10)\n#define BIT_BT_PDN_8197F BIT(9)\n#define BIT_AUTO_WLPON_8197F BIT(8)\n#define BIT_WL_MODE_8197F BIT(7)\n#define BIT_PKG_SEL_HCI_8197F BIT(6)\n\n#define BIT_SHIFT_HCI_SEL_8197F 4\n#define BIT_MASK_HCI_SEL_8197F 0x3\n#define BIT_HCI_SEL_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_HCI_SEL_8197F) << BIT_SHIFT_HCI_SEL_8197F)\n#define BITS_HCI_SEL_8197F (BIT_MASK_HCI_SEL_8197F << BIT_SHIFT_HCI_SEL_8197F)\n#define BIT_CLEAR_HCI_SEL_8197F(x) ((x) & (~BITS_HCI_SEL_8197F))\n#define BIT_GET_HCI_SEL_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_HCI_SEL_8197F) & BIT_MASK_HCI_SEL_8197F)\n#define BIT_SET_HCI_SEL_8197F(x, v)                                            \\\n\t(BIT_CLEAR_HCI_SEL_8197F(x) | BIT_HCI_SEL_8197F(v))\n\n#define BIT_SHIFT_PAD_HCI_SEL_8197F 2\n#define BIT_MASK_PAD_HCI_SEL_8197F 0x3\n#define BIT_PAD_HCI_SEL_8197F(x)                                               \\\n\t(((x) & BIT_MASK_PAD_HCI_SEL_8197F) << BIT_SHIFT_PAD_HCI_SEL_8197F)\n#define BITS_PAD_HCI_SEL_8197F                                                 \\\n\t(BIT_MASK_PAD_HCI_SEL_8197F << BIT_SHIFT_PAD_HCI_SEL_8197F)\n#define BIT_CLEAR_PAD_HCI_SEL_8197F(x) ((x) & (~BITS_PAD_HCI_SEL_8197F))\n#define BIT_GET_PAD_HCI_SEL_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_PAD_HCI_SEL_8197F) & BIT_MASK_PAD_HCI_SEL_8197F)\n#define BIT_SET_PAD_HCI_SEL_8197F(x, v)                                        \\\n\t(BIT_CLEAR_PAD_HCI_SEL_8197F(x) | BIT_PAD_HCI_SEL_8197F(v))\n\n#define BIT_SHIFT_EFS_HCI_SEL_8197F 0\n#define BIT_MASK_EFS_HCI_SEL_8197F 0x3\n#define BIT_EFS_HCI_SEL_8197F(x)                                               \\\n\t(((x) & BIT_MASK_EFS_HCI_SEL_8197F) << BIT_SHIFT_EFS_HCI_SEL_8197F)\n#define BITS_EFS_HCI_SEL_8197F                                                 \\\n\t(BIT_MASK_EFS_HCI_SEL_8197F << BIT_SHIFT_EFS_HCI_SEL_8197F)\n#define BIT_CLEAR_EFS_HCI_SEL_8197F(x) ((x) & (~BITS_EFS_HCI_SEL_8197F))\n#define BIT_GET_EFS_HCI_SEL_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_EFS_HCI_SEL_8197F) & BIT_MASK_EFS_HCI_SEL_8197F)\n#define BIT_SET_EFS_HCI_SEL_8197F(x, v)                                        \\\n\t(BIT_CLEAR_EFS_HCI_SEL_8197F(x) | BIT_EFS_HCI_SEL_8197F(v))\n\n/* 2 REG_SYS_STATUS2_8197F */\n#define BIT_SIO_ALDN_8197F BIT(19)\n#define BIT_USB_ALDN_8197F BIT(18)\n#define BIT_PCI_ALDN_8197F BIT(17)\n#define BIT_SYS_ALDN_8197F BIT(16)\n\n#define BIT_SHIFT_EPVID1_8197F 8\n#define BIT_MASK_EPVID1_8197F 0xff\n#define BIT_EPVID1_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_EPVID1_8197F) << BIT_SHIFT_EPVID1_8197F)\n#define BITS_EPVID1_8197F (BIT_MASK_EPVID1_8197F << BIT_SHIFT_EPVID1_8197F)\n#define BIT_CLEAR_EPVID1_8197F(x) ((x) & (~BITS_EPVID1_8197F))\n#define BIT_GET_EPVID1_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_EPVID1_8197F) & BIT_MASK_EPVID1_8197F)\n#define BIT_SET_EPVID1_8197F(x, v)                                             \\\n\t(BIT_CLEAR_EPVID1_8197F(x) | BIT_EPVID1_8197F(v))\n\n#define BIT_SHIFT_EPVID0_8197F 0\n#define BIT_MASK_EPVID0_8197F 0xff\n#define BIT_EPVID0_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_EPVID0_8197F) << BIT_SHIFT_EPVID0_8197F)\n#define BITS_EPVID0_8197F (BIT_MASK_EPVID0_8197F << BIT_SHIFT_EPVID0_8197F)\n#define BIT_CLEAR_EPVID0_8197F(x) ((x) & (~BITS_EPVID0_8197F))\n#define BIT_GET_EPVID0_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_EPVID0_8197F) & BIT_MASK_EPVID0_8197F)\n#define BIT_SET_EPVID0_8197F(x, v)                                             \\\n\t(BIT_CLEAR_EPVID0_8197F(x) | BIT_EPVID0_8197F(v))\n\n/* 2 REG_SYS_CFG2_8197F */\n\n#define BIT_SHIFT_HW_ID_8197F 0\n#define BIT_MASK_HW_ID_8197F 0xff\n#define BIT_HW_ID_8197F(x)                                                     \\\n\t(((x) & BIT_MASK_HW_ID_8197F) << BIT_SHIFT_HW_ID_8197F)\n#define BITS_HW_ID_8197F (BIT_MASK_HW_ID_8197F << BIT_SHIFT_HW_ID_8197F)\n#define BIT_CLEAR_HW_ID_8197F(x) ((x) & (~BITS_HW_ID_8197F))\n#define BIT_GET_HW_ID_8197F(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HW_ID_8197F) & BIT_MASK_HW_ID_8197F)\n#define BIT_SET_HW_ID_8197F(x, v)                                              \\\n\t(BIT_CLEAR_HW_ID_8197F(x) | BIT_HW_ID_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_SYS_CFG3_8197F */\n\n/* 2 REG_SYS_CFG4_8197F */\n\n/* 2 REG_CPU_DMEM_CON_8197F */\n#define BIT_ANA_PORT_IDLE_8197F BIT(18)\n#define BIT_MAC_PORT_IDLE_8197F BIT(17)\n#define BIT_WL_PLATFORM_RST_8197F BIT(16)\n#define BIT_WL_SECURITY_CLK_8197F BIT(15)\n\n#define BIT_SHIFT_CPU_DMEM_CON_8197F 0\n#define BIT_MASK_CPU_DMEM_CON_8197F 0xff\n#define BIT_CPU_DMEM_CON_8197F(x)                                              \\\n\t(((x) & BIT_MASK_CPU_DMEM_CON_8197F) << BIT_SHIFT_CPU_DMEM_CON_8197F)\n#define BITS_CPU_DMEM_CON_8197F                                                \\\n\t(BIT_MASK_CPU_DMEM_CON_8197F << BIT_SHIFT_CPU_DMEM_CON_8197F)\n#define BIT_CLEAR_CPU_DMEM_CON_8197F(x) ((x) & (~BITS_CPU_DMEM_CON_8197F))\n#define BIT_GET_CPU_DMEM_CON_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_CPU_DMEM_CON_8197F) & BIT_MASK_CPU_DMEM_CON_8197F)\n#define BIT_SET_CPU_DMEM_CON_8197F(x, v)                                       \\\n\t(BIT_CLEAR_CPU_DMEM_CON_8197F(x) | BIT_CPU_DMEM_CON_8197F(v))\n\n/* 2 REG_HIMR2_8197F */\n#define BIT_BCNDMAINT_P4_MSK_8197F BIT(31)\n#define BIT_BCNDMAINT_P3_MSK_8197F BIT(30)\n#define BIT_BCNDMAINT_P2_MSK_8197F BIT(29)\n#define BIT_BCNDMAINT_P1_MSK_8197F BIT(28)\n#define BIT_ATIMEND7_MSK_8197F BIT(22)\n#define BIT_ATIMEND6_MSK_8197F BIT(21)\n#define BIT_ATIMEND5_MSK_8197F BIT(20)\n#define BIT_ATIMEND4_MSK_8197F BIT(19)\n#define BIT_ATIMEND3_MSK_8197F BIT(18)\n#define BIT_ATIMEND2_MSK_8197F BIT(17)\n#define BIT_ATIMEND1_MSK_8197F BIT(16)\n#define BIT_TXBCN7OK_MSK_8197F BIT(14)\n#define BIT_TXBCN6OK_MSK_8197F BIT(13)\n#define BIT_TXBCN5OK_MSK_8197F BIT(12)\n#define BIT_TXBCN4OK_MSK_8197F BIT(11)\n#define BIT_TXBCN3OK_MSK_8197F BIT(10)\n#define BIT_TXBCN2OK_MSK_8197F BIT(9)\n#define BIT_TXBCN1OK_MSK_V1_8197F BIT(8)\n#define BIT_TXBCN7ERR_MSK_8197F BIT(6)\n#define BIT_TXBCN6ERR_MSK_8197F BIT(5)\n#define BIT_TXBCN5ERR_MSK_8197F BIT(4)\n#define BIT_TXBCN4ERR_MSK_8197F BIT(3)\n#define BIT_TXBCN3ERR_MSK_8197F BIT(2)\n#define BIT_TXBCN2ERR_MSK_8197F BIT(1)\n#define BIT_TXBCN1ERR_MSK_V1_8197F BIT(0)\n\n/* 2 REG_HISR2_8197F */\n#define BIT_BCNDMAINT_P4_8197F BIT(31)\n#define BIT_BCNDMAINT_P3_8197F BIT(30)\n#define BIT_BCNDMAINT_P2_8197F BIT(29)\n#define BIT_BCNDMAINT_P1_8197F BIT(28)\n#define BIT_ATIMEND7_8197F BIT(22)\n#define BIT_ATIMEND6_8197F BIT(21)\n#define BIT_ATIMEND5_8197F BIT(20)\n#define BIT_ATIMEND4_8197F BIT(19)\n#define BIT_ATIMEND3_8197F BIT(18)\n#define BIT_ATIMEND2_8197F BIT(17)\n#define BIT_ATIMEND1_8197F BIT(16)\n#define BIT_TXBCN7OK_8197F BIT(14)\n#define BIT_TXBCN6OK_8197F BIT(13)\n#define BIT_TXBCN5OK_8197F BIT(12)\n#define BIT_TXBCN4OK_8197F BIT(11)\n#define BIT_TXBCN3OK_8197F BIT(10)\n#define BIT_TXBCN2OK_8197F BIT(9)\n#define BIT_TXBCN1OK_8197F BIT(8)\n#define BIT_TXBCN7ERR_8197F BIT(6)\n#define BIT_TXBCN6ERR_8197F BIT(5)\n#define BIT_TXBCN5ERR_8197F BIT(4)\n#define BIT_TXBCN4ERR_8197F BIT(3)\n#define BIT_TXBCN3ERR_8197F BIT(2)\n#define BIT_TXBCN2ERR_8197F BIT(1)\n#define BIT_TXBCN1ERR_8197F BIT(0)\n\n/* 2 REG_HIMR3_8197F */\n#define BIT_SETH2CDOK_MASK_8197F BIT(16)\n#define BIT_H2C_CMD_FULL_MASK_8197F BIT(15)\n#define BIT_PWR_INT_127_MASK_8197F BIT(14)\n#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8197F BIT(13)\n#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8197F BIT(12)\n#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8197F BIT(11)\n#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8197F BIT(10)\n#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8197F BIT(9)\n#define BIT_PWR_INT_127_MASK_V1_8197F BIT(8)\n#define BIT_PWR_INT_126TO96_MASK_8197F BIT(7)\n#define BIT_PWR_INT_95TO64_MASK_8197F BIT(6)\n#define BIT_PWR_INT_63TO32_MASK_8197F BIT(5)\n#define BIT_PWR_INT_31TO0_MASK_8197F BIT(4)\n#define BIT_DDMA0_LP_INT_MSK_8197F BIT(1)\n#define BIT_DDMA0_HP_INT_MSK_8197F BIT(0)\n\n/* 2 REG_HISR3_8197F */\n#define BIT_SETH2CDOK_8197F BIT(16)\n#define BIT_H2C_CMD_FULL_8197F BIT(15)\n#define BIT_PWR_INT_127_8197F BIT(14)\n#define BIT_TXSHORTCUT_TXDESUPDATEOK_8197F BIT(13)\n#define BIT_TXSHORTCUT_BKUPDATEOK_8197F BIT(12)\n#define BIT_TXSHORTCUT_BEUPDATEOK_8197F BIT(11)\n#define BIT_TXSHORTCUT_VIUPDATEOK_8197F BIT(10)\n#define BIT_TXSHORTCUT_VOUPDATEOK_8197F BIT(9)\n#define BIT_PWR_INT_127_V1_8197F BIT(8)\n#define BIT_PWR_INT_126TO96_8197F BIT(7)\n#define BIT_PWR_INT_95TO64_8197F BIT(6)\n#define BIT_PWR_INT_63TO32_8197F BIT(5)\n#define BIT_PWR_INT_31TO0_8197F BIT(4)\n#define BIT_DDMA0_LP_INT_8197F BIT(1)\n#define BIT_DDMA0_HP_INT_8197F BIT(0)\n\n/* 2 REG_SW_MDIO_8197F */\n\n/* 2 REG_SW_FLUSH_8197F */\n#define BIT_FLUSH_HOLDN_EN_8197F BIT(25)\n#define BIT_FLUSH_WR_EN_8197F BIT(24)\n#define BIT_SW_FLASH_CONTROL_8197F BIT(23)\n#define BIT_SW_FLASH_WEN_E_8197F BIT(19)\n#define BIT_SW_FLASH_HOLDN_E_8197F BIT(18)\n#define BIT_SW_FLASH_SO_E_8197F BIT(17)\n#define BIT_SW_FLASH_SI_E_8197F BIT(16)\n#define BIT_SW_FLASH_SK_O_8197F BIT(13)\n#define BIT_SW_FLASH_CEN_O_8197F BIT(12)\n#define BIT_SW_FLASH_WEN_O_8197F BIT(11)\n#define BIT_SW_FLASH_HOLDN_O_8197F BIT(10)\n#define BIT_SW_FLASH_SO_O_8197F BIT(9)\n#define BIT_SW_FLASH_SI_O_8197F BIT(8)\n#define BIT_SW_FLASH_WEN_I_8197F BIT(3)\n#define BIT_SW_FLASH_HOLDN_I_8197F BIT(2)\n#define BIT_SW_FLASH_SO_I_8197F BIT(1)\n#define BIT_SW_FLASH_SI_I_8197F BIT(0)\n\n/* 2 REG_DBG_GPIO_BMUX_8197F */\n\n#define BIT_SHIFT_DBG_GPIO_BMUX_7_8197F 21\n#define BIT_MASK_DBG_GPIO_BMUX_7_8197F 0x7\n#define BIT_DBG_GPIO_BMUX_7_8197F(x)                                           \\\n\t(((x) & BIT_MASK_DBG_GPIO_BMUX_7_8197F)                                \\\n\t << BIT_SHIFT_DBG_GPIO_BMUX_7_8197F)\n#define BITS_DBG_GPIO_BMUX_7_8197F                                             \\\n\t(BIT_MASK_DBG_GPIO_BMUX_7_8197F << BIT_SHIFT_DBG_GPIO_BMUX_7_8197F)\n#define BIT_CLEAR_DBG_GPIO_BMUX_7_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_7_8197F))\n#define BIT_GET_DBG_GPIO_BMUX_7_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) &                            \\\n\t BIT_MASK_DBG_GPIO_BMUX_7_8197F)\n#define BIT_SET_DBG_GPIO_BMUX_7_8197F(x, v)                                    \\\n\t(BIT_CLEAR_DBG_GPIO_BMUX_7_8197F(x) | BIT_DBG_GPIO_BMUX_7_8197F(v))\n\n#define BIT_SHIFT_DBG_GPIO_BMUX_6_8197F 18\n#define BIT_MASK_DBG_GPIO_BMUX_6_8197F 0x7\n#define BIT_DBG_GPIO_BMUX_6_8197F(x)                                           \\\n\t(((x) & BIT_MASK_DBG_GPIO_BMUX_6_8197F)                                \\\n\t << BIT_SHIFT_DBG_GPIO_BMUX_6_8197F)\n#define BITS_DBG_GPIO_BMUX_6_8197F                                             \\\n\t(BIT_MASK_DBG_GPIO_BMUX_6_8197F << BIT_SHIFT_DBG_GPIO_BMUX_6_8197F)\n#define BIT_CLEAR_DBG_GPIO_BMUX_6_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_6_8197F))\n#define BIT_GET_DBG_GPIO_BMUX_6_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) &                            \\\n\t BIT_MASK_DBG_GPIO_BMUX_6_8197F)\n#define BIT_SET_DBG_GPIO_BMUX_6_8197F(x, v)                                    \\\n\t(BIT_CLEAR_DBG_GPIO_BMUX_6_8197F(x) | BIT_DBG_GPIO_BMUX_6_8197F(v))\n\n#define BIT_SHIFT_DBG_GPIO_BMUX_5_8197F 15\n#define BIT_MASK_DBG_GPIO_BMUX_5_8197F 0x7\n#define BIT_DBG_GPIO_BMUX_5_8197F(x)                                           \\\n\t(((x) & BIT_MASK_DBG_GPIO_BMUX_5_8197F)                                \\\n\t << BIT_SHIFT_DBG_GPIO_BMUX_5_8197F)\n#define BITS_DBG_GPIO_BMUX_5_8197F                                             \\\n\t(BIT_MASK_DBG_GPIO_BMUX_5_8197F << BIT_SHIFT_DBG_GPIO_BMUX_5_8197F)\n#define BIT_CLEAR_DBG_GPIO_BMUX_5_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_5_8197F))\n#define BIT_GET_DBG_GPIO_BMUX_5_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) &                            \\\n\t BIT_MASK_DBG_GPIO_BMUX_5_8197F)\n#define BIT_SET_DBG_GPIO_BMUX_5_8197F(x, v)                                    \\\n\t(BIT_CLEAR_DBG_GPIO_BMUX_5_8197F(x) | BIT_DBG_GPIO_BMUX_5_8197F(v))\n\n#define BIT_SHIFT_DBG_GPIO_BMUX_4_8197F 12\n#define BIT_MASK_DBG_GPIO_BMUX_4_8197F 0x7\n#define BIT_DBG_GPIO_BMUX_4_8197F(x)                                           \\\n\t(((x) & BIT_MASK_DBG_GPIO_BMUX_4_8197F)                                \\\n\t << BIT_SHIFT_DBG_GPIO_BMUX_4_8197F)\n#define BITS_DBG_GPIO_BMUX_4_8197F                                             \\\n\t(BIT_MASK_DBG_GPIO_BMUX_4_8197F << BIT_SHIFT_DBG_GPIO_BMUX_4_8197F)\n#define BIT_CLEAR_DBG_GPIO_BMUX_4_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_4_8197F))\n#define BIT_GET_DBG_GPIO_BMUX_4_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) &                            \\\n\t BIT_MASK_DBG_GPIO_BMUX_4_8197F)\n#define BIT_SET_DBG_GPIO_BMUX_4_8197F(x, v)                                    \\\n\t(BIT_CLEAR_DBG_GPIO_BMUX_4_8197F(x) | BIT_DBG_GPIO_BMUX_4_8197F(v))\n\n#define BIT_SHIFT_DBG_GPIO_BMUX_3_8197F 9\n#define BIT_MASK_DBG_GPIO_BMUX_3_8197F 0x7\n#define BIT_DBG_GPIO_BMUX_3_8197F(x)                                           \\\n\t(((x) & BIT_MASK_DBG_GPIO_BMUX_3_8197F)                                \\\n\t << BIT_SHIFT_DBG_GPIO_BMUX_3_8197F)\n#define BITS_DBG_GPIO_BMUX_3_8197F                                             \\\n\t(BIT_MASK_DBG_GPIO_BMUX_3_8197F << BIT_SHIFT_DBG_GPIO_BMUX_3_8197F)\n#define BIT_CLEAR_DBG_GPIO_BMUX_3_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_3_8197F))\n#define BIT_GET_DBG_GPIO_BMUX_3_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) &                            \\\n\t BIT_MASK_DBG_GPIO_BMUX_3_8197F)\n#define BIT_SET_DBG_GPIO_BMUX_3_8197F(x, v)                                    \\\n\t(BIT_CLEAR_DBG_GPIO_BMUX_3_8197F(x) | BIT_DBG_GPIO_BMUX_3_8197F(v))\n\n#define BIT_SHIFT_DBG_GPIO_BMUX_2_8197F 6\n#define BIT_MASK_DBG_GPIO_BMUX_2_8197F 0x7\n#define BIT_DBG_GPIO_BMUX_2_8197F(x)                                           \\\n\t(((x) & BIT_MASK_DBG_GPIO_BMUX_2_8197F)                                \\\n\t << BIT_SHIFT_DBG_GPIO_BMUX_2_8197F)\n#define BITS_DBG_GPIO_BMUX_2_8197F                                             \\\n\t(BIT_MASK_DBG_GPIO_BMUX_2_8197F << BIT_SHIFT_DBG_GPIO_BMUX_2_8197F)\n#define BIT_CLEAR_DBG_GPIO_BMUX_2_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_2_8197F))\n#define BIT_GET_DBG_GPIO_BMUX_2_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) &                            \\\n\t BIT_MASK_DBG_GPIO_BMUX_2_8197F)\n#define BIT_SET_DBG_GPIO_BMUX_2_8197F(x, v)                                    \\\n\t(BIT_CLEAR_DBG_GPIO_BMUX_2_8197F(x) | BIT_DBG_GPIO_BMUX_2_8197F(v))\n\n#define BIT_SHIFT_DBG_GPIO_BMUX_1_8197F 3\n#define BIT_MASK_DBG_GPIO_BMUX_1_8197F 0x7\n#define BIT_DBG_GPIO_BMUX_1_8197F(x)                                           \\\n\t(((x) & BIT_MASK_DBG_GPIO_BMUX_1_8197F)                                \\\n\t << BIT_SHIFT_DBG_GPIO_BMUX_1_8197F)\n#define BITS_DBG_GPIO_BMUX_1_8197F                                             \\\n\t(BIT_MASK_DBG_GPIO_BMUX_1_8197F << BIT_SHIFT_DBG_GPIO_BMUX_1_8197F)\n#define BIT_CLEAR_DBG_GPIO_BMUX_1_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_1_8197F))\n#define BIT_GET_DBG_GPIO_BMUX_1_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) &                            \\\n\t BIT_MASK_DBG_GPIO_BMUX_1_8197F)\n#define BIT_SET_DBG_GPIO_BMUX_1_8197F(x, v)                                    \\\n\t(BIT_CLEAR_DBG_GPIO_BMUX_1_8197F(x) | BIT_DBG_GPIO_BMUX_1_8197F(v))\n\n#define BIT_SHIFT_DBG_GPIO_BMUX_0_8197F 0\n#define BIT_MASK_DBG_GPIO_BMUX_0_8197F 0x7\n#define BIT_DBG_GPIO_BMUX_0_8197F(x)                                           \\\n\t(((x) & BIT_MASK_DBG_GPIO_BMUX_0_8197F)                                \\\n\t << BIT_SHIFT_DBG_GPIO_BMUX_0_8197F)\n#define BITS_DBG_GPIO_BMUX_0_8197F                                             \\\n\t(BIT_MASK_DBG_GPIO_BMUX_0_8197F << BIT_SHIFT_DBG_GPIO_BMUX_0_8197F)\n#define BIT_CLEAR_DBG_GPIO_BMUX_0_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_0_8197F))\n#define BIT_GET_DBG_GPIO_BMUX_0_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) &                            \\\n\t BIT_MASK_DBG_GPIO_BMUX_0_8197F)\n#define BIT_SET_DBG_GPIO_BMUX_0_8197F(x, v)                                    \\\n\t(BIT_CLEAR_DBG_GPIO_BMUX_0_8197F(x) | BIT_DBG_GPIO_BMUX_0_8197F(v))\n\n/* 2 REG_FPGA_TAG_8197F (NO USE IN ASIC) */\n\n#define BIT_SHIFT_FPGA_TAG_8197F 0\n#define BIT_MASK_FPGA_TAG_8197F 0xffffffffL\n#define BIT_FPGA_TAG_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_FPGA_TAG_8197F) << BIT_SHIFT_FPGA_TAG_8197F)\n#define BITS_FPGA_TAG_8197F                                                    \\\n\t(BIT_MASK_FPGA_TAG_8197F << BIT_SHIFT_FPGA_TAG_8197F)\n#define BIT_CLEAR_FPGA_TAG_8197F(x) ((x) & (~BITS_FPGA_TAG_8197F))\n#define BIT_GET_FPGA_TAG_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_FPGA_TAG_8197F) & BIT_MASK_FPGA_TAG_8197F)\n#define BIT_SET_FPGA_TAG_8197F(x, v)                                           \\\n\t(BIT_CLEAR_FPGA_TAG_8197F(x) | BIT_FPGA_TAG_8197F(v))\n\n/* 2 REG_WL_DSS_CTRL0_8197F */\n#define BIT_WL_DSS_RSTN_8197F BIT(27)\n#define BIT_WL_DSS_EN_CLK_8197F BIT(26)\n#define BIT_WL_DSS_SPEED_EN_8197F BIT(25)\n\n#define BIT_SHIFT_WL_DSS_COUNT_OUT_8197F 0\n#define BIT_MASK_WL_DSS_COUNT_OUT_8197F 0xfffff\n#define BIT_WL_DSS_COUNT_OUT_8197F(x)                                          \\\n\t(((x) & BIT_MASK_WL_DSS_COUNT_OUT_8197F)                               \\\n\t << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F)\n#define BITS_WL_DSS_COUNT_OUT_8197F                                            \\\n\t(BIT_MASK_WL_DSS_COUNT_OUT_8197F << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F)\n#define BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x)                                    \\\n\t((x) & (~BITS_WL_DSS_COUNT_OUT_8197F))\n#define BIT_GET_WL_DSS_COUNT_OUT_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) &                           \\\n\t BIT_MASK_WL_DSS_COUNT_OUT_8197F)\n#define BIT_SET_WL_DSS_COUNT_OUT_8197F(x, v)                                   \\\n\t(BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) | BIT_WL_DSS_COUNT_OUT_8197F(v))\n\n/* 2 REG_WL_DSS_CTRL1_8197F */\n#define BIT_WL_DSS_RSTN_8197F BIT(27)\n#define BIT_WL_DSS_EN_CLK_8197F BIT(26)\n#define BIT_WL_DSS_SPEED_EN_8197F BIT(25)\n#define BIT_WL_DSS_WIRE_SEL_8197F BIT(24)\n\n#define BIT_SHIFT_WL_DSS_RO_SEL_8197F 20\n#define BIT_MASK_WL_DSS_RO_SEL_8197F 0x7\n#define BIT_WL_DSS_RO_SEL_8197F(x)                                             \\\n\t(((x) & BIT_MASK_WL_DSS_RO_SEL_8197F) << BIT_SHIFT_WL_DSS_RO_SEL_8197F)\n#define BITS_WL_DSS_RO_SEL_8197F                                               \\\n\t(BIT_MASK_WL_DSS_RO_SEL_8197F << BIT_SHIFT_WL_DSS_RO_SEL_8197F)\n#define BIT_CLEAR_WL_DSS_RO_SEL_8197F(x) ((x) & (~BITS_WL_DSS_RO_SEL_8197F))\n#define BIT_GET_WL_DSS_RO_SEL_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_WL_DSS_RO_SEL_8197F) & BIT_MASK_WL_DSS_RO_SEL_8197F)\n#define BIT_SET_WL_DSS_RO_SEL_8197F(x, v)                                      \\\n\t(BIT_CLEAR_WL_DSS_RO_SEL_8197F(x) | BIT_WL_DSS_RO_SEL_8197F(v))\n\n#define BIT_SHIFT_WL_DSS_DATA_IN_8197F 0\n#define BIT_MASK_WL_DSS_DATA_IN_8197F 0xfffff\n#define BIT_WL_DSS_DATA_IN_8197F(x)                                            \\\n\t(((x) & BIT_MASK_WL_DSS_DATA_IN_8197F)                                 \\\n\t << BIT_SHIFT_WL_DSS_DATA_IN_8197F)\n#define BITS_WL_DSS_DATA_IN_8197F                                              \\\n\t(BIT_MASK_WL_DSS_DATA_IN_8197F << BIT_SHIFT_WL_DSS_DATA_IN_8197F)\n#define BIT_CLEAR_WL_DSS_DATA_IN_8197F(x) ((x) & (~BITS_WL_DSS_DATA_IN_8197F))\n#define BIT_GET_WL_DSS_DATA_IN_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_WL_DSS_DATA_IN_8197F) &                             \\\n\t BIT_MASK_WL_DSS_DATA_IN_8197F)\n#define BIT_SET_WL_DSS_DATA_IN_8197F(x, v)                                     \\\n\t(BIT_CLEAR_WL_DSS_DATA_IN_8197F(x) | BIT_WL_DSS_DATA_IN_8197F(v))\n\n/* 2 REG_WL_DSS_STATUS1_8197F */\n#define BIT_WL_DSS_READY_8197F BIT(21)\n#define BIT_WL_DSS_WSORT_GO_8197F BIT(20)\n\n#define BIT_SHIFT_WL_DSS_COUNT_OUT_8197F 0\n#define BIT_MASK_WL_DSS_COUNT_OUT_8197F 0xfffff\n#define BIT_WL_DSS_COUNT_OUT_8197F(x)                                          \\\n\t(((x) & BIT_MASK_WL_DSS_COUNT_OUT_8197F)                               \\\n\t << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F)\n#define BITS_WL_DSS_COUNT_OUT_8197F                                            \\\n\t(BIT_MASK_WL_DSS_COUNT_OUT_8197F << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F)\n#define BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x)                                    \\\n\t((x) & (~BITS_WL_DSS_COUNT_OUT_8197F))\n#define BIT_GET_WL_DSS_COUNT_OUT_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) &                           \\\n\t BIT_MASK_WL_DSS_COUNT_OUT_8197F)\n#define BIT_SET_WL_DSS_COUNT_OUT_8197F(x, v)                                   \\\n\t(BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) | BIT_WL_DSS_COUNT_OUT_8197F(v))\n\n/* 2 REG_FW_DBG0_8197F */\n\n#define BIT_SHIFT_FW_DBG0_8197F 0\n#define BIT_MASK_FW_DBG0_8197F 0xffffffffL\n#define BIT_FW_DBG0_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG0_8197F) << BIT_SHIFT_FW_DBG0_8197F)\n#define BITS_FW_DBG0_8197F (BIT_MASK_FW_DBG0_8197F << BIT_SHIFT_FW_DBG0_8197F)\n#define BIT_CLEAR_FW_DBG0_8197F(x) ((x) & (~BITS_FW_DBG0_8197F))\n#define BIT_GET_FW_DBG0_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG0_8197F) & BIT_MASK_FW_DBG0_8197F)\n#define BIT_SET_FW_DBG0_8197F(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG0_8197F(x) | BIT_FW_DBG0_8197F(v))\n\n/* 2 REG_FW_DBG1_8197F */\n\n#define BIT_SHIFT_FW_DBG1_8197F 0\n#define BIT_MASK_FW_DBG1_8197F 0xffffffffL\n#define BIT_FW_DBG1_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG1_8197F) << BIT_SHIFT_FW_DBG1_8197F)\n#define BITS_FW_DBG1_8197F (BIT_MASK_FW_DBG1_8197F << BIT_SHIFT_FW_DBG1_8197F)\n#define BIT_CLEAR_FW_DBG1_8197F(x) ((x) & (~BITS_FW_DBG1_8197F))\n#define BIT_GET_FW_DBG1_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG1_8197F) & BIT_MASK_FW_DBG1_8197F)\n#define BIT_SET_FW_DBG1_8197F(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG1_8197F(x) | BIT_FW_DBG1_8197F(v))\n\n/* 2 REG_FW_DBG2_8197F */\n\n#define BIT_SHIFT_FW_DBG2_8197F 0\n#define BIT_MASK_FW_DBG2_8197F 0xffffffffL\n#define BIT_FW_DBG2_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG2_8197F) << BIT_SHIFT_FW_DBG2_8197F)\n#define BITS_FW_DBG2_8197F (BIT_MASK_FW_DBG2_8197F << BIT_SHIFT_FW_DBG2_8197F)\n#define BIT_CLEAR_FW_DBG2_8197F(x) ((x) & (~BITS_FW_DBG2_8197F))\n#define BIT_GET_FW_DBG2_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG2_8197F) & BIT_MASK_FW_DBG2_8197F)\n#define BIT_SET_FW_DBG2_8197F(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG2_8197F(x) | BIT_FW_DBG2_8197F(v))\n\n/* 2 REG_FW_DBG3_8197F */\n\n#define BIT_SHIFT_FW_DBG3_8197F 0\n#define BIT_MASK_FW_DBG3_8197F 0xffffffffL\n#define BIT_FW_DBG3_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG3_8197F) << BIT_SHIFT_FW_DBG3_8197F)\n#define BITS_FW_DBG3_8197F (BIT_MASK_FW_DBG3_8197F << BIT_SHIFT_FW_DBG3_8197F)\n#define BIT_CLEAR_FW_DBG3_8197F(x) ((x) & (~BITS_FW_DBG3_8197F))\n#define BIT_GET_FW_DBG3_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG3_8197F) & BIT_MASK_FW_DBG3_8197F)\n#define BIT_SET_FW_DBG3_8197F(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG3_8197F(x) | BIT_FW_DBG3_8197F(v))\n\n/* 2 REG_FW_DBG4_8197F */\n\n#define BIT_SHIFT_FW_DBG4_8197F 0\n#define BIT_MASK_FW_DBG4_8197F 0xffffffffL\n#define BIT_FW_DBG4_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG4_8197F) << BIT_SHIFT_FW_DBG4_8197F)\n#define BITS_FW_DBG4_8197F (BIT_MASK_FW_DBG4_8197F << BIT_SHIFT_FW_DBG4_8197F)\n#define BIT_CLEAR_FW_DBG4_8197F(x) ((x) & (~BITS_FW_DBG4_8197F))\n#define BIT_GET_FW_DBG4_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG4_8197F) & BIT_MASK_FW_DBG4_8197F)\n#define BIT_SET_FW_DBG4_8197F(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG4_8197F(x) | BIT_FW_DBG4_8197F(v))\n\n/* 2 REG_FW_DBG5_8197F */\n\n#define BIT_SHIFT_FW_DBG5_8197F 0\n#define BIT_MASK_FW_DBG5_8197F 0xffffffffL\n#define BIT_FW_DBG5_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG5_8197F) << BIT_SHIFT_FW_DBG5_8197F)\n#define BITS_FW_DBG5_8197F (BIT_MASK_FW_DBG5_8197F << BIT_SHIFT_FW_DBG5_8197F)\n#define BIT_CLEAR_FW_DBG5_8197F(x) ((x) & (~BITS_FW_DBG5_8197F))\n#define BIT_GET_FW_DBG5_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG5_8197F) & BIT_MASK_FW_DBG5_8197F)\n#define BIT_SET_FW_DBG5_8197F(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG5_8197F(x) | BIT_FW_DBG5_8197F(v))\n\n/* 2 REG_FW_DBG6_8197F */\n\n#define BIT_SHIFT_FW_DBG6_8197F 0\n#define BIT_MASK_FW_DBG6_8197F 0xffffffffL\n#define BIT_FW_DBG6_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG6_8197F) << BIT_SHIFT_FW_DBG6_8197F)\n#define BITS_FW_DBG6_8197F (BIT_MASK_FW_DBG6_8197F << BIT_SHIFT_FW_DBG6_8197F)\n#define BIT_CLEAR_FW_DBG6_8197F(x) ((x) & (~BITS_FW_DBG6_8197F))\n#define BIT_GET_FW_DBG6_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG6_8197F) & BIT_MASK_FW_DBG6_8197F)\n#define BIT_SET_FW_DBG6_8197F(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG6_8197F(x) | BIT_FW_DBG6_8197F(v))\n\n/* 2 REG_FW_DBG7_8197F */\n\n#define BIT_SHIFT_FW_DBG7_8197F 0\n#define BIT_MASK_FW_DBG7_8197F 0xffffffffL\n#define BIT_FW_DBG7_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG7_8197F) << BIT_SHIFT_FW_DBG7_8197F)\n#define BITS_FW_DBG7_8197F (BIT_MASK_FW_DBG7_8197F << BIT_SHIFT_FW_DBG7_8197F)\n#define BIT_CLEAR_FW_DBG7_8197F(x) ((x) & (~BITS_FW_DBG7_8197F))\n#define BIT_GET_FW_DBG7_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG7_8197F) & BIT_MASK_FW_DBG7_8197F)\n#define BIT_SET_FW_DBG7_8197F(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG7_8197F(x) | BIT_FW_DBG7_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_CR_8197F (ENABLE FUNCTION REGISTER) */\n#define BIT_MACIO_TIMEOUT_EN_8197F BIT(29)\n\n#define BIT_SHIFT_LBMODE_8197F 24\n#define BIT_MASK_LBMODE_8197F 0x1f\n#define BIT_LBMODE_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_LBMODE_8197F) << BIT_SHIFT_LBMODE_8197F)\n#define BITS_LBMODE_8197F (BIT_MASK_LBMODE_8197F << BIT_SHIFT_LBMODE_8197F)\n#define BIT_CLEAR_LBMODE_8197F(x) ((x) & (~BITS_LBMODE_8197F))\n#define BIT_GET_LBMODE_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_LBMODE_8197F) & BIT_MASK_LBMODE_8197F)\n#define BIT_SET_LBMODE_8197F(x, v)                                             \\\n\t(BIT_CLEAR_LBMODE_8197F(x) | BIT_LBMODE_8197F(v))\n\n#define BIT_SHIFT_NETYPE1_8197F 18\n#define BIT_MASK_NETYPE1_8197F 0x3\n#define BIT_NETYPE1_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE1_8197F) << BIT_SHIFT_NETYPE1_8197F)\n#define BITS_NETYPE1_8197F (BIT_MASK_NETYPE1_8197F << BIT_SHIFT_NETYPE1_8197F)\n#define BIT_CLEAR_NETYPE1_8197F(x) ((x) & (~BITS_NETYPE1_8197F))\n#define BIT_GET_NETYPE1_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE1_8197F) & BIT_MASK_NETYPE1_8197F)\n#define BIT_SET_NETYPE1_8197F(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE1_8197F(x) | BIT_NETYPE1_8197F(v))\n\n#define BIT_SHIFT_NETYPE0_8197F 16\n#define BIT_MASK_NETYPE0_8197F 0x3\n#define BIT_NETYPE0_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE0_8197F) << BIT_SHIFT_NETYPE0_8197F)\n#define BITS_NETYPE0_8197F (BIT_MASK_NETYPE0_8197F << BIT_SHIFT_NETYPE0_8197F)\n#define BIT_CLEAR_NETYPE0_8197F(x) ((x) & (~BITS_NETYPE0_8197F))\n#define BIT_GET_NETYPE0_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE0_8197F) & BIT_MASK_NETYPE0_8197F)\n#define BIT_SET_NETYPE0_8197F(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE0_8197F(x) | BIT_NETYPE0_8197F(v))\n\n#define BIT_STAT_FUNC_RST_8197F BIT(13)\n#define BIT_I2C_MAILBOX_EN_8197F BIT(12)\n#define BIT_SHCUT_EN_8197F BIT(11)\n#define BIT_32K_CAL_TMR_EN_8197F BIT(10)\n#define BIT_MAC_SEC_EN_8197F BIT(9)\n#define BIT_ENSWBCN_8197F BIT(8)\n#define BIT_MACRXEN_8197F BIT(7)\n#define BIT_MACTXEN_8197F BIT(6)\n#define BIT_SCHEDULE_EN_8197F BIT(5)\n#define BIT_PROTOCOL_EN_8197F BIT(4)\n#define BIT_RXDMA_EN_8197F BIT(3)\n#define BIT_TXDMA_EN_8197F BIT(2)\n#define BIT_HCI_RXDMA_EN_8197F BIT(1)\n#define BIT_HCI_TXDMA_EN_8197F BIT(0)\n\n/* 2 REG_TSF_CLK_STATE_8197F */\n#define BIT_TSF_CLK_STABLE_8197F BIT(15)\n\n/* 2 REG_TXDMA_PQ_MAP_8197F */\n\n#define BIT_SHIFT_TXDMA_HIQ_MAP_8197F 14\n#define BIT_MASK_TXDMA_HIQ_MAP_8197F 0x3\n#define BIT_TXDMA_HIQ_MAP_8197F(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_HIQ_MAP_8197F) << BIT_SHIFT_TXDMA_HIQ_MAP_8197F)\n#define BITS_TXDMA_HIQ_MAP_8197F                                               \\\n\t(BIT_MASK_TXDMA_HIQ_MAP_8197F << BIT_SHIFT_TXDMA_HIQ_MAP_8197F)\n#define BIT_CLEAR_TXDMA_HIQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8197F))\n#define BIT_GET_TXDMA_HIQ_MAP_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8197F) & BIT_MASK_TXDMA_HIQ_MAP_8197F)\n#define BIT_SET_TXDMA_HIQ_MAP_8197F(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_HIQ_MAP_8197F(x) | BIT_TXDMA_HIQ_MAP_8197F(v))\n\n#define BIT_SHIFT_TXDMA_MGQ_MAP_8197F 12\n#define BIT_MASK_TXDMA_MGQ_MAP_8197F 0x3\n#define BIT_TXDMA_MGQ_MAP_8197F(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_MGQ_MAP_8197F) << BIT_SHIFT_TXDMA_MGQ_MAP_8197F)\n#define BITS_TXDMA_MGQ_MAP_8197F                                               \\\n\t(BIT_MASK_TXDMA_MGQ_MAP_8197F << BIT_SHIFT_TXDMA_MGQ_MAP_8197F)\n#define BIT_CLEAR_TXDMA_MGQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8197F))\n#define BIT_GET_TXDMA_MGQ_MAP_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8197F) & BIT_MASK_TXDMA_MGQ_MAP_8197F)\n#define BIT_SET_TXDMA_MGQ_MAP_8197F(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_MGQ_MAP_8197F(x) | BIT_TXDMA_MGQ_MAP_8197F(v))\n\n#define BIT_SHIFT_TXDMA_BKQ_MAP_8197F 10\n#define BIT_MASK_TXDMA_BKQ_MAP_8197F 0x3\n#define BIT_TXDMA_BKQ_MAP_8197F(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_BKQ_MAP_8197F) << BIT_SHIFT_TXDMA_BKQ_MAP_8197F)\n#define BITS_TXDMA_BKQ_MAP_8197F                                               \\\n\t(BIT_MASK_TXDMA_BKQ_MAP_8197F << BIT_SHIFT_TXDMA_BKQ_MAP_8197F)\n#define BIT_CLEAR_TXDMA_BKQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8197F))\n#define BIT_GET_TXDMA_BKQ_MAP_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8197F) & BIT_MASK_TXDMA_BKQ_MAP_8197F)\n#define BIT_SET_TXDMA_BKQ_MAP_8197F(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_BKQ_MAP_8197F(x) | BIT_TXDMA_BKQ_MAP_8197F(v))\n\n#define BIT_SHIFT_TXDMA_BEQ_MAP_8197F 8\n#define BIT_MASK_TXDMA_BEQ_MAP_8197F 0x3\n#define BIT_TXDMA_BEQ_MAP_8197F(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_BEQ_MAP_8197F) << BIT_SHIFT_TXDMA_BEQ_MAP_8197F)\n#define BITS_TXDMA_BEQ_MAP_8197F                                               \\\n\t(BIT_MASK_TXDMA_BEQ_MAP_8197F << BIT_SHIFT_TXDMA_BEQ_MAP_8197F)\n#define BIT_CLEAR_TXDMA_BEQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8197F))\n#define BIT_GET_TXDMA_BEQ_MAP_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8197F) & BIT_MASK_TXDMA_BEQ_MAP_8197F)\n#define BIT_SET_TXDMA_BEQ_MAP_8197F(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_BEQ_MAP_8197F(x) | BIT_TXDMA_BEQ_MAP_8197F(v))\n\n#define BIT_SHIFT_TXDMA_VIQ_MAP_8197F 6\n#define BIT_MASK_TXDMA_VIQ_MAP_8197F 0x3\n#define BIT_TXDMA_VIQ_MAP_8197F(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_VIQ_MAP_8197F) << BIT_SHIFT_TXDMA_VIQ_MAP_8197F)\n#define BITS_TXDMA_VIQ_MAP_8197F                                               \\\n\t(BIT_MASK_TXDMA_VIQ_MAP_8197F << BIT_SHIFT_TXDMA_VIQ_MAP_8197F)\n#define BIT_CLEAR_TXDMA_VIQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8197F))\n#define BIT_GET_TXDMA_VIQ_MAP_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8197F) & BIT_MASK_TXDMA_VIQ_MAP_8197F)\n#define BIT_SET_TXDMA_VIQ_MAP_8197F(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_VIQ_MAP_8197F(x) | BIT_TXDMA_VIQ_MAP_8197F(v))\n\n#define BIT_SHIFT_TXDMA_VOQ_MAP_8197F 4\n#define BIT_MASK_TXDMA_VOQ_MAP_8197F 0x3\n#define BIT_TXDMA_VOQ_MAP_8197F(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_VOQ_MAP_8197F) << BIT_SHIFT_TXDMA_VOQ_MAP_8197F)\n#define BITS_TXDMA_VOQ_MAP_8197F                                               \\\n\t(BIT_MASK_TXDMA_VOQ_MAP_8197F << BIT_SHIFT_TXDMA_VOQ_MAP_8197F)\n#define BIT_CLEAR_TXDMA_VOQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8197F))\n#define BIT_GET_TXDMA_VOQ_MAP_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8197F) & BIT_MASK_TXDMA_VOQ_MAP_8197F)\n#define BIT_SET_TXDMA_VOQ_MAP_8197F(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_VOQ_MAP_8197F(x) | BIT_TXDMA_VOQ_MAP_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n#define BIT_RXDMA_AGG_EN_8197F BIT(2)\n#define BIT_RXSHFT_EN_8197F BIT(1)\n#define BIT_RXDMA_ARBBW_EN_8197F BIT(0)\n\n/* 2 REG_TRXFF_BNDY_8197F */\n\n#define BIT_SHIFT_RXFFOVFL_RSV_V2_8197F 8\n#define BIT_MASK_RXFFOVFL_RSV_V2_8197F 0xf\n#define BIT_RXFFOVFL_RSV_V2_8197F(x)                                           \\\n\t(((x) & BIT_MASK_RXFFOVFL_RSV_V2_8197F)                                \\\n\t << BIT_SHIFT_RXFFOVFL_RSV_V2_8197F)\n#define BITS_RXFFOVFL_RSV_V2_8197F                                             \\\n\t(BIT_MASK_RXFFOVFL_RSV_V2_8197F << BIT_SHIFT_RXFFOVFL_RSV_V2_8197F)\n#define BIT_CLEAR_RXFFOVFL_RSV_V2_8197F(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8197F))\n#define BIT_GET_RXFFOVFL_RSV_V2_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) &                            \\\n\t BIT_MASK_RXFFOVFL_RSV_V2_8197F)\n#define BIT_SET_RXFFOVFL_RSV_V2_8197F(x, v)                                    \\\n\t(BIT_CLEAR_RXFFOVFL_RSV_V2_8197F(x) | BIT_RXFFOVFL_RSV_V2_8197F(v))\n\n#define BIT_SHIFT_TXPKTBUF_PGBNDY_8197F 0\n#define BIT_MASK_TXPKTBUF_PGBNDY_8197F 0xff\n#define BIT_TXPKTBUF_PGBNDY_8197F(x)                                           \\\n\t(((x) & BIT_MASK_TXPKTBUF_PGBNDY_8197F)                                \\\n\t << BIT_SHIFT_TXPKTBUF_PGBNDY_8197F)\n#define BITS_TXPKTBUF_PGBNDY_8197F                                             \\\n\t(BIT_MASK_TXPKTBUF_PGBNDY_8197F << BIT_SHIFT_TXPKTBUF_PGBNDY_8197F)\n#define BIT_CLEAR_TXPKTBUF_PGBNDY_8197F(x) ((x) & (~BITS_TXPKTBUF_PGBNDY_8197F))\n#define BIT_GET_TXPKTBUF_PGBNDY_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) &                            \\\n\t BIT_MASK_TXPKTBUF_PGBNDY_8197F)\n#define BIT_SET_TXPKTBUF_PGBNDY_8197F(x, v)                                    \\\n\t(BIT_CLEAR_TXPKTBUF_PGBNDY_8197F(x) | BIT_TXPKTBUF_PGBNDY_8197F(v))\n\n/* 2 REG_PTA_I2C_MBOX_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n#define BIT_SHIFT_I2C_M_STATUS_8197F 8\n#define BIT_MASK_I2C_M_STATUS_8197F 0xf\n#define BIT_I2C_M_STATUS_8197F(x)                                              \\\n\t(((x) & BIT_MASK_I2C_M_STATUS_8197F) << BIT_SHIFT_I2C_M_STATUS_8197F)\n#define BITS_I2C_M_STATUS_8197F                                                \\\n\t(BIT_MASK_I2C_M_STATUS_8197F << BIT_SHIFT_I2C_M_STATUS_8197F)\n#define BIT_CLEAR_I2C_M_STATUS_8197F(x) ((x) & (~BITS_I2C_M_STATUS_8197F))\n#define BIT_GET_I2C_M_STATUS_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_I2C_M_STATUS_8197F) & BIT_MASK_I2C_M_STATUS_8197F)\n#define BIT_SET_I2C_M_STATUS_8197F(x, v)                                       \\\n\t(BIT_CLEAR_I2C_M_STATUS_8197F(x) | BIT_I2C_M_STATUS_8197F(v))\n\n#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F 4\n#define BIT_MASK_I2C_M_BUS_GNT_FW_8197F 0x7\n#define BIT_I2C_M_BUS_GNT_FW_8197F(x)                                          \\\n\t(((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8197F)                               \\\n\t << BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F)\n#define BITS_I2C_M_BUS_GNT_FW_8197F                                            \\\n\t(BIT_MASK_I2C_M_BUS_GNT_FW_8197F << BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F)\n#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8197F(x)                                    \\\n\t((x) & (~BITS_I2C_M_BUS_GNT_FW_8197F))\n#define BIT_GET_I2C_M_BUS_GNT_FW_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) &                           \\\n\t BIT_MASK_I2C_M_BUS_GNT_FW_8197F)\n#define BIT_SET_I2C_M_BUS_GNT_FW_8197F(x, v)                                   \\\n\t(BIT_CLEAR_I2C_M_BUS_GNT_FW_8197F(x) | BIT_I2C_M_BUS_GNT_FW_8197F(v))\n\n#define BIT_I2C_M_GNT_FW_8197F BIT(3)\n\n#define BIT_SHIFT_I2C_M_SPEED_8197F 1\n#define BIT_MASK_I2C_M_SPEED_8197F 0x3\n#define BIT_I2C_M_SPEED_8197F(x)                                               \\\n\t(((x) & BIT_MASK_I2C_M_SPEED_8197F) << BIT_SHIFT_I2C_M_SPEED_8197F)\n#define BITS_I2C_M_SPEED_8197F                                                 \\\n\t(BIT_MASK_I2C_M_SPEED_8197F << BIT_SHIFT_I2C_M_SPEED_8197F)\n#define BIT_CLEAR_I2C_M_SPEED_8197F(x) ((x) & (~BITS_I2C_M_SPEED_8197F))\n#define BIT_GET_I2C_M_SPEED_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_I2C_M_SPEED_8197F) & BIT_MASK_I2C_M_SPEED_8197F)\n#define BIT_SET_I2C_M_SPEED_8197F(x, v)                                        \\\n\t(BIT_CLEAR_I2C_M_SPEED_8197F(x) | BIT_I2C_M_SPEED_8197F(v))\n\n#define BIT_I2C_M_UNLOCK_8197F BIT(0)\n\n/* 2 REG_RXFF_BNDY_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n#define BIT_SHIFT_RXFF0_BNDY_V2_8197F 0\n#define BIT_MASK_RXFF0_BNDY_V2_8197F 0x3ffff\n#define BIT_RXFF0_BNDY_V2_8197F(x)                                             \\\n\t(((x) & BIT_MASK_RXFF0_BNDY_V2_8197F) << BIT_SHIFT_RXFF0_BNDY_V2_8197F)\n#define BITS_RXFF0_BNDY_V2_8197F                                               \\\n\t(BIT_MASK_RXFF0_BNDY_V2_8197F << BIT_SHIFT_RXFF0_BNDY_V2_8197F)\n#define BIT_CLEAR_RXFF0_BNDY_V2_8197F(x) ((x) & (~BITS_RXFF0_BNDY_V2_8197F))\n#define BIT_GET_RXFF0_BNDY_V2_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8197F) & BIT_MASK_RXFF0_BNDY_V2_8197F)\n#define BIT_SET_RXFF0_BNDY_V2_8197F(x, v)                                      \\\n\t(BIT_CLEAR_RXFF0_BNDY_V2_8197F(x) | BIT_RXFF0_BNDY_V2_8197F(v))\n\n/* 2 REG_FE1IMR_8197F */\n#define BIT_BB_STOP_RX_INT_EN_8197F BIT(29)\n#define BIT_FS_RXDMA2_DONE_INT_EN_8197F BIT(28)\n#define BIT_FS_RXDONE3_INT_EN_8197F BIT(27)\n#define BIT_FS_RXDONE2_INT_EN_8197F BIT(26)\n#define BIT_FS_RX_BCN_P4_INT_EN_8197F BIT(25)\n#define BIT_FS_RX_BCN_P3_INT_EN_8197F BIT(24)\n#define BIT_FS_RX_BCN_P2_INT_EN_8197F BIT(23)\n#define BIT_FS_RX_BCN_P1_INT_EN_8197F BIT(22)\n#define BIT_FS_RX_BCN_P0_INT_EN_8197F BIT(21)\n#define BIT_FS_RX_UMD0_INT_EN_8197F BIT(20)\n#define BIT_FS_RX_UMD1_INT_EN_8197F BIT(19)\n#define BIT_FS_RX_BMD0_INT_EN_8197F BIT(18)\n#define BIT_FS_RX_BMD1_INT_EN_8197F BIT(17)\n#define BIT_FS_RXDONE_INT_EN_8197F BIT(16)\n#define BIT_FS_WWLAN_INT_EN_8197F BIT(15)\n#define BIT_FS_SOUND_DONE_INT_EN_8197F BIT(14)\n#define BIT_FS_LP_STBY_INT_EN_8197F BIT(13)\n#define BIT_FS_TRL_MTR_INT_EN_8197F BIT(12)\n#define BIT_FS_BF1_PRETO_INT_EN_8197F BIT(11)\n#define BIT_FS_BF0_PRETO_INT_EN_8197F BIT(10)\n#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8197F BIT(9)\n#define BIT_FS_LTE_COEX_EN_8197F BIT(6)\n#define BIT_FS_WLACTOFF_INT_EN_8197F BIT(5)\n#define BIT_FS_WLACTON_INT_EN_8197F BIT(4)\n#define BIT_FS_BTCMD_INT_EN_8197F BIT(3)\n#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8197F BIT(2)\n#define BIT_FS_TRPC_TO_INT_EN_V1_8197F BIT(1)\n#define BIT_FS_RPC_O_T_INT_EN_V1_8197F BIT(0)\n\n/* 2 REG_FE1ISR_8197F */\n#define BIT_BB_STOP_RX_INT_8197F BIT(29)\n#define BIT_FS_RXDMA2_DONE_INT_8197F BIT(28)\n#define BIT_FS_RXDONE3_INT_8197F BIT(27)\n#define BIT_FS_RXDONE2_INT_8197F BIT(26)\n#define BIT_FS_RX_BCN_P4_INT_8197F BIT(25)\n#define BIT_FS_RX_BCN_P3_INT_8197F BIT(24)\n#define BIT_FS_RX_BCN_P2_INT_8197F BIT(23)\n#define BIT_FS_RX_BCN_P1_INT_8197F BIT(22)\n#define BIT_FS_RX_BCN_P0_INT_8197F BIT(21)\n#define BIT_FS_RX_UMD0_INT_8197F BIT(20)\n#define BIT_FS_RX_UMD1_INT_8197F BIT(19)\n#define BIT_FS_RX_BMD0_INT_8197F BIT(18)\n#define BIT_FS_RX_BMD1_INT_8197F BIT(17)\n#define BIT_FS_RXDONE_INT_8197F BIT(16)\n#define BIT_FS_WWLAN_INT_8197F BIT(15)\n#define BIT_FS_SOUND_DONE_INT_8197F BIT(14)\n#define BIT_FS_LP_STBY_INT_8197F BIT(13)\n#define BIT_FS_TRL_MTR_INT_8197F BIT(12)\n#define BIT_FS_BF1_PRETO_INT_8197F BIT(11)\n#define BIT_FS_BF0_PRETO_INT_8197F BIT(10)\n#define BIT_FS_PTCL_RELEASE_MACID_INT_8197F BIT(9)\n#define BIT_FS_LTE_COEX_INT_8197F BIT(6)\n#define BIT_FS_WLACTOFF_INT_8197F BIT(5)\n#define BIT_FS_WLACTON_INT_8197F BIT(4)\n#define BIT_FS_BCN_RX_INT_INT_8197F BIT(3)\n#define BIT_FS_MAILBOX_TO_I2C_INT_8197F BIT(2)\n#define BIT_FS_TRPC_TO_INT_8197F BIT(1)\n#define BIT_FS_RPC_O_T_INT_8197F BIT(0)\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_CPWM_8197F */\n#define BIT_CPWM_TOGGLING_8197F BIT(31)\n\n#define BIT_SHIFT_CPWM_MOD_8197F 24\n#define BIT_MASK_CPWM_MOD_8197F 0x7f\n#define BIT_CPWM_MOD_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_CPWM_MOD_8197F) << BIT_SHIFT_CPWM_MOD_8197F)\n#define BITS_CPWM_MOD_8197F                                                    \\\n\t(BIT_MASK_CPWM_MOD_8197F << BIT_SHIFT_CPWM_MOD_8197F)\n#define BIT_CLEAR_CPWM_MOD_8197F(x) ((x) & (~BITS_CPWM_MOD_8197F))\n#define BIT_GET_CPWM_MOD_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_CPWM_MOD_8197F) & BIT_MASK_CPWM_MOD_8197F)\n#define BIT_SET_CPWM_MOD_8197F(x, v)                                           \\\n\t(BIT_CLEAR_CPWM_MOD_8197F(x) | BIT_CPWM_MOD_8197F(v))\n\n/* 2 REG_FWIMR_8197F */\n#define BIT_FS_TXBCNOK_MB7_INT_EN_8197F BIT(31)\n#define BIT_FS_TXBCNOK_MB6_INT_EN_8197F BIT(30)\n#define BIT_FS_TXBCNOK_MB5_INT_EN_8197F BIT(29)\n#define BIT_FS_TXBCNOK_MB4_INT_EN_8197F BIT(28)\n#define BIT_FS_TXBCNOK_MB3_INT_EN_8197F BIT(27)\n#define BIT_FS_TXBCNOK_MB2_INT_EN_8197F BIT(26)\n#define BIT_FS_TXBCNOK_MB1_INT_EN_8197F BIT(25)\n#define BIT_FS_TXBCNOK_MB0_INT_EN_8197F BIT(24)\n#define BIT_FS_TXBCNERR_MB7_INT_EN_8197F BIT(23)\n#define BIT_FS_TXBCNERR_MB6_INT_EN_8197F BIT(22)\n#define BIT_FS_TXBCNERR_MB5_INT_EN_8197F BIT(21)\n#define BIT_FS_TXBCNERR_MB4_INT_EN_8197F BIT(20)\n#define BIT_FS_TXBCNERR_MB3_INT_EN_8197F BIT(19)\n#define BIT_FS_TXBCNERR_MB2_INT_EN_8197F BIT(18)\n#define BIT_FS_TXBCNERR_MB1_INT_EN_8197F BIT(17)\n#define BIT_FS_TXBCNERR_MB0_INT_EN_8197F BIT(16)\n#define BIT_CPUMGN_POLLED_PKT_DONE_INT_EN_8197F BIT(15)\n#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8197F BIT(13)\n#define BIT_FS_MGNTQFF_TO_INT_EN_8197F BIT(12)\n#define BIT_FS_DDMA1_LP_INT_ENBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_EN_8197F      \\\n\tBIT(11)\n#define BIT_FS_DDMA1_HP_INT_EN_8197F BIT(10)\n#define BIT_FS_DDMA0_LP_INT_EN_8197F BIT(9)\n#define BIT_FS_DDMA0_HP_INT_EN_8197F BIT(8)\n#define BIT_FS_TRXRPT_INT_EN_8197F BIT(7)\n#define BIT_FS_C2H_W_READY_INT_EN_8197F BIT(6)\n#define BIT_FS_HRCV_INT_EN_8197F BIT(5)\n#define BIT_FS_H2CCMD_INT_EN_8197F BIT(4)\n#define BIT_FS_TXPKTIN_INT_EN_8197F BIT(3)\n#define BIT_FS_ERRORHDL_INT_EN_8197F BIT(2)\n#define BIT_FS_TXCCX_INT_EN_8197F BIT(1)\n#define BIT_FS_TXCLOSE_INT_EN_8197F BIT(0)\n\n/* 2 REG_FWISR_8197F */\n#define BIT_FS_TXBCNOK_MB7_INT_8197F BIT(31)\n#define BIT_FS_TXBCNOK_MB6_INT_8197F BIT(30)\n#define BIT_FS_TXBCNOK_MB5_INT_8197F BIT(29)\n#define BIT_FS_TXBCNOK_MB4_INT_8197F BIT(28)\n#define BIT_FS_TXBCNOK_MB3_INT_8197F BIT(27)\n#define BIT_FS_TXBCNOK_MB2_INT_8197F BIT(26)\n#define BIT_FS_TXBCNOK_MB1_INT_8197F BIT(25)\n#define BIT_FS_TXBCNOK_MB0_INT_8197F BIT(24)\n#define BIT_FS_TXBCNERR_MB7_INT_8197F BIT(23)\n#define BIT_FS_TXBCNERR_MB6_INT_8197F BIT(22)\n#define BIT_FS_TXBCNERR_MB5_INT_8197F BIT(21)\n#define BIT_FS_TXBCNERR_MB4_INT_8197F BIT(20)\n#define BIT_FS_TXBCNERR_MB3_INT_8197F BIT(19)\n#define BIT_FS_TXBCNERR_MB2_INT_8197F BIT(18)\n#define BIT_FS_TXBCNERR_MB1_INT_8197F BIT(17)\n#define BIT_FS_TXBCNERR_MB0_INT_8197F BIT(16)\n#define BIT_CPUMGN_POLLED_PKT_DONE_INT_8197F BIT(15)\n#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8197F BIT(13)\n#define BIT_FS_MGNTQFF_TO_INT_8197F BIT(12)\n#define BIT_FS_DDMA1_LP_INTBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_8197F BIT(11)\n#define BIT_FS_DDMA1_HP_INT_8197F BIT(10)\n#define BIT_FS_DDMA0_LP_INT_8197F BIT(9)\n#define BIT_FS_DDMA0_HP_INT_8197F BIT(8)\n#define BIT_FS_TRXRPT_INT_8197F BIT(7)\n#define BIT_FS_C2H_W_READY_INT_8197F BIT(6)\n#define BIT_FS_HRCV_INT_8197F BIT(5)\n#define BIT_FS_H2CCMD_INT_8197F BIT(4)\n#define BIT_FS_TXPKTIN_INT_8197F BIT(3)\n#define BIT_FS_ERRORHDL_INT_8197F BIT(2)\n#define BIT_FS_TXCCX_INT_8197F BIT(1)\n#define BIT_FS_TXCLOSE_INT_8197F BIT(0)\n\n/* 2 REG_FTIMR_8197F */\n#define BIT_PS_TIMER_C_EARLY_INT_EN_8197F BIT(23)\n#define BIT_PS_TIMER_B_EARLY_INT_EN_8197F BIT(22)\n#define BIT_PS_TIMER_A_EARLY_INT_EN_8197F BIT(21)\n#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8197F BIT(20)\n#define BIT_PS_TIMER_C_INT_EN_8197F BIT(19)\n#define BIT_PS_TIMER_B_INT_EN_8197F BIT(18)\n#define BIT_PS_TIMER_A_INT_EN_8197F BIT(17)\n#define BIT_CPUMGQ_TX_TIMER_INT_EN_8197F BIT(16)\n#define BIT_FS_PS_TIMEOUT2_EN_8197F BIT(15)\n#define BIT_FS_PS_TIMEOUT1_EN_8197F BIT(14)\n#define BIT_FS_PS_TIMEOUT0_EN_8197F BIT(13)\n#define BIT_FS_GTINT8_EN_8197F BIT(8)\n#define BIT_FS_GTINT7_EN_8197F BIT(7)\n#define BIT_FS_GTINT6_EN_8197F BIT(6)\n#define BIT_FS_GTINT5_EN_8197F BIT(5)\n#define BIT_FS_GTINT4_EN_8197F BIT(4)\n#define BIT_FS_GTINT3_EN_8197F BIT(3)\n#define BIT_FS_GTINT2_EN_8197F BIT(2)\n#define BIT_FS_GTINT1_EN_8197F BIT(1)\n#define BIT_FS_GTINT0_EN_8197F BIT(0)\n\n/* 2 REG_FTISR_8197F */\n#define BIT_PS_TIMER_C_EARLY__INT_8197F BIT(23)\n#define BIT_PS_TIMER_B_EARLY__INT_8197F BIT(22)\n#define BIT_PS_TIMER_A_EARLY__INT_8197F BIT(21)\n#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8197F BIT(20)\n#define BIT_PS_TIMER_C_INT_8197F BIT(19)\n#define BIT_PS_TIMER_B_INT_8197F BIT(18)\n#define BIT_PS_TIMER_A_INT_8197F BIT(17)\n#define BIT_CPUMGQ_TX_TIMER_INT_8197F BIT(16)\n#define BIT_FS_PS_TIMEOUT2_INT_8197F BIT(15)\n#define BIT_FS_PS_TIMEOUT1_INT_8197F BIT(14)\n#define BIT_FS_PS_TIMEOUT0_INT_8197F BIT(13)\n#define BIT_FS_GTINT8_INT_8197F BIT(8)\n#define BIT_FS_GTINT7_INT_8197F BIT(7)\n#define BIT_FS_GTINT6_INT_8197F BIT(6)\n#define BIT_FS_GTINT5_INT_8197F BIT(5)\n#define BIT_FS_GTINT4_INT_8197F BIT(4)\n#define BIT_FS_GTINT3_INT_8197F BIT(3)\n#define BIT_FS_GTINT2_INT_8197F BIT(2)\n#define BIT_FS_GTINT1_INT_8197F BIT(1)\n#define BIT_FS_GTINT0_INT_8197F BIT(0)\n\n/* 2 REG_PKTBUF_DBG_CTRL_8197F */\n\n#define BIT_SHIFT_PKTBUF_WRITE_EN_8197F 24\n#define BIT_MASK_PKTBUF_WRITE_EN_8197F 0xff\n#define BIT_PKTBUF_WRITE_EN_8197F(x)                                           \\\n\t(((x) & BIT_MASK_PKTBUF_WRITE_EN_8197F)                                \\\n\t << BIT_SHIFT_PKTBUF_WRITE_EN_8197F)\n#define BITS_PKTBUF_WRITE_EN_8197F                                             \\\n\t(BIT_MASK_PKTBUF_WRITE_EN_8197F << BIT_SHIFT_PKTBUF_WRITE_EN_8197F)\n#define BIT_CLEAR_PKTBUF_WRITE_EN_8197F(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8197F))\n#define BIT_GET_PKTBUF_WRITE_EN_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8197F) &                            \\\n\t BIT_MASK_PKTBUF_WRITE_EN_8197F)\n#define BIT_SET_PKTBUF_WRITE_EN_8197F(x, v)                                    \\\n\t(BIT_CLEAR_PKTBUF_WRITE_EN_8197F(x) | BIT_PKTBUF_WRITE_EN_8197F(v))\n\n#define BIT_TXRPTBUF_DBG_8197F BIT(23)\n\n/* 2 REG_NOT_VALID_8197F */\n#define BIT_TXPKTBUF_DBG_V2_8197F BIT(20)\n#define BIT_RXPKTBUF_DBG_8197F BIT(16)\n\n#define BIT_SHIFT_PKTBUF_DBG_ADDR_8197F 0\n#define BIT_MASK_PKTBUF_DBG_ADDR_8197F 0x1fff\n#define BIT_PKTBUF_DBG_ADDR_8197F(x)                                           \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_ADDR_8197F)                                \\\n\t << BIT_SHIFT_PKTBUF_DBG_ADDR_8197F)\n#define BITS_PKTBUF_DBG_ADDR_8197F                                             \\\n\t(BIT_MASK_PKTBUF_DBG_ADDR_8197F << BIT_SHIFT_PKTBUF_DBG_ADDR_8197F)\n#define BIT_CLEAR_PKTBUF_DBG_ADDR_8197F(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8197F))\n#define BIT_GET_PKTBUF_DBG_ADDR_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) &                            \\\n\t BIT_MASK_PKTBUF_DBG_ADDR_8197F)\n#define BIT_SET_PKTBUF_DBG_ADDR_8197F(x, v)                                    \\\n\t(BIT_CLEAR_PKTBUF_DBG_ADDR_8197F(x) | BIT_PKTBUF_DBG_ADDR_8197F(v))\n\n/* 2 REG_PKTBUF_DBG_DATA_L_8197F */\n\n#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F 0\n#define BIT_MASK_PKTBUF_DBG_DATA_L_8197F 0xffffffffL\n#define BIT_PKTBUF_DBG_DATA_L_8197F(x)                                         \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8197F)                              \\\n\t << BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F)\n#define BITS_PKTBUF_DBG_DATA_L_8197F                                           \\\n\t(BIT_MASK_PKTBUF_DBG_DATA_L_8197F << BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F)\n#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8197F(x)                                   \\\n\t((x) & (~BITS_PKTBUF_DBG_DATA_L_8197F))\n#define BIT_GET_PKTBUF_DBG_DATA_L_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) &                          \\\n\t BIT_MASK_PKTBUF_DBG_DATA_L_8197F)\n#define BIT_SET_PKTBUF_DBG_DATA_L_8197F(x, v)                                  \\\n\t(BIT_CLEAR_PKTBUF_DBG_DATA_L_8197F(x) | BIT_PKTBUF_DBG_DATA_L_8197F(v))\n\n/* 2 REG_PKTBUF_DBG_DATA_H_8197F */\n\n#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F 0\n#define BIT_MASK_PKTBUF_DBG_DATA_H_8197F 0xffffffffL\n#define BIT_PKTBUF_DBG_DATA_H_8197F(x)                                         \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8197F)                              \\\n\t << BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F)\n#define BITS_PKTBUF_DBG_DATA_H_8197F                                           \\\n\t(BIT_MASK_PKTBUF_DBG_DATA_H_8197F << BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F)\n#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8197F(x)                                   \\\n\t((x) & (~BITS_PKTBUF_DBG_DATA_H_8197F))\n#define BIT_GET_PKTBUF_DBG_DATA_H_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) &                          \\\n\t BIT_MASK_PKTBUF_DBG_DATA_H_8197F)\n#define BIT_SET_PKTBUF_DBG_DATA_H_8197F(x, v)                                  \\\n\t(BIT_CLEAR_PKTBUF_DBG_DATA_H_8197F(x) | BIT_PKTBUF_DBG_DATA_H_8197F(v))\n\n/* 2 REG_CPWM2_8197F */\n\n#define BIT_SHIFT_L0S_TO_RCVY_NUM_8197F 16\n#define BIT_MASK_L0S_TO_RCVY_NUM_8197F 0xff\n#define BIT_L0S_TO_RCVY_NUM_8197F(x)                                           \\\n\t(((x) & BIT_MASK_L0S_TO_RCVY_NUM_8197F)                                \\\n\t << BIT_SHIFT_L0S_TO_RCVY_NUM_8197F)\n#define BITS_L0S_TO_RCVY_NUM_8197F                                             \\\n\t(BIT_MASK_L0S_TO_RCVY_NUM_8197F << BIT_SHIFT_L0S_TO_RCVY_NUM_8197F)\n#define BIT_CLEAR_L0S_TO_RCVY_NUM_8197F(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8197F))\n#define BIT_GET_L0S_TO_RCVY_NUM_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) &                            \\\n\t BIT_MASK_L0S_TO_RCVY_NUM_8197F)\n#define BIT_SET_L0S_TO_RCVY_NUM_8197F(x, v)                                    \\\n\t(BIT_CLEAR_L0S_TO_RCVY_NUM_8197F(x) | BIT_L0S_TO_RCVY_NUM_8197F(v))\n\n#define BIT_CPWM2_TOGGLING_8197F BIT(15)\n\n#define BIT_SHIFT_CPWM2_MOD_8197F 0\n#define BIT_MASK_CPWM2_MOD_8197F 0x7fff\n#define BIT_CPWM2_MOD_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_CPWM2_MOD_8197F) << BIT_SHIFT_CPWM2_MOD_8197F)\n#define BITS_CPWM2_MOD_8197F                                                   \\\n\t(BIT_MASK_CPWM2_MOD_8197F << BIT_SHIFT_CPWM2_MOD_8197F)\n#define BIT_CLEAR_CPWM2_MOD_8197F(x) ((x) & (~BITS_CPWM2_MOD_8197F))\n#define BIT_GET_CPWM2_MOD_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_CPWM2_MOD_8197F) & BIT_MASK_CPWM2_MOD_8197F)\n#define BIT_SET_CPWM2_MOD_8197F(x, v)                                          \\\n\t(BIT_CLEAR_CPWM2_MOD_8197F(x) | BIT_CPWM2_MOD_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_TC0_CTRL_8197F */\n#define BIT_TC0INT_EN_8197F BIT(26)\n#define BIT_TC0MODE_8197F BIT(25)\n#define BIT_TC0EN_8197F BIT(24)\n\n#define BIT_SHIFT_TC0DATA_8197F 0\n#define BIT_MASK_TC0DATA_8197F 0xffffff\n#define BIT_TC0DATA_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_TC0DATA_8197F) << BIT_SHIFT_TC0DATA_8197F)\n#define BITS_TC0DATA_8197F (BIT_MASK_TC0DATA_8197F << BIT_SHIFT_TC0DATA_8197F)\n#define BIT_CLEAR_TC0DATA_8197F(x) ((x) & (~BITS_TC0DATA_8197F))\n#define BIT_GET_TC0DATA_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC0DATA_8197F) & BIT_MASK_TC0DATA_8197F)\n#define BIT_SET_TC0DATA_8197F(x, v)                                            \\\n\t(BIT_CLEAR_TC0DATA_8197F(x) | BIT_TC0DATA_8197F(v))\n\n/* 2 REG_TC1_CTRL_8197F */\n#define BIT_TC1INT_EN_8197F BIT(26)\n#define BIT_TC1MODE_8197F BIT(25)\n#define BIT_TC1EN_8197F BIT(24)\n\n#define BIT_SHIFT_TC1DATA_8197F 0\n#define BIT_MASK_TC1DATA_8197F 0xffffff\n#define BIT_TC1DATA_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_TC1DATA_8197F) << BIT_SHIFT_TC1DATA_8197F)\n#define BITS_TC1DATA_8197F (BIT_MASK_TC1DATA_8197F << BIT_SHIFT_TC1DATA_8197F)\n#define BIT_CLEAR_TC1DATA_8197F(x) ((x) & (~BITS_TC1DATA_8197F))\n#define BIT_GET_TC1DATA_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC1DATA_8197F) & BIT_MASK_TC1DATA_8197F)\n#define BIT_SET_TC1DATA_8197F(x, v)                                            \\\n\t(BIT_CLEAR_TC1DATA_8197F(x) | BIT_TC1DATA_8197F(v))\n\n/* 2 REG_TC2_CTRL_8197F */\n#define BIT_TC2INT_EN_8197F BIT(26)\n#define BIT_TC2MODE_8197F BIT(25)\n#define BIT_TC2EN_8197F BIT(24)\n\n#define BIT_SHIFT_TC2DATA_8197F 0\n#define BIT_MASK_TC2DATA_8197F 0xffffff\n#define BIT_TC2DATA_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_TC2DATA_8197F) << BIT_SHIFT_TC2DATA_8197F)\n#define BITS_TC2DATA_8197F (BIT_MASK_TC2DATA_8197F << BIT_SHIFT_TC2DATA_8197F)\n#define BIT_CLEAR_TC2DATA_8197F(x) ((x) & (~BITS_TC2DATA_8197F))\n#define BIT_GET_TC2DATA_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC2DATA_8197F) & BIT_MASK_TC2DATA_8197F)\n#define BIT_SET_TC2DATA_8197F(x, v)                                            \\\n\t(BIT_CLEAR_TC2DATA_8197F(x) | BIT_TC2DATA_8197F(v))\n\n/* 2 REG_TC3_CTRL_8197F */\n#define BIT_TC3INT_EN_8197F BIT(26)\n#define BIT_TC3MODE_8197F BIT(25)\n#define BIT_TC3EN_8197F BIT(24)\n\n#define BIT_SHIFT_TC3DATA_8197F 0\n#define BIT_MASK_TC3DATA_8197F 0xffffff\n#define BIT_TC3DATA_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_TC3DATA_8197F) << BIT_SHIFT_TC3DATA_8197F)\n#define BITS_TC3DATA_8197F (BIT_MASK_TC3DATA_8197F << BIT_SHIFT_TC3DATA_8197F)\n#define BIT_CLEAR_TC3DATA_8197F(x) ((x) & (~BITS_TC3DATA_8197F))\n#define BIT_GET_TC3DATA_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC3DATA_8197F) & BIT_MASK_TC3DATA_8197F)\n#define BIT_SET_TC3DATA_8197F(x, v)                                            \\\n\t(BIT_CLEAR_TC3DATA_8197F(x) | BIT_TC3DATA_8197F(v))\n\n/* 2 REG_TC4_CTRL_8197F */\n#define BIT_TC4INT_EN_8197F BIT(26)\n#define BIT_TC4MODE_8197F BIT(25)\n#define BIT_TC4EN_8197F BIT(24)\n\n#define BIT_SHIFT_TC4DATA_8197F 0\n#define BIT_MASK_TC4DATA_8197F 0xffffff\n#define BIT_TC4DATA_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_TC4DATA_8197F) << BIT_SHIFT_TC4DATA_8197F)\n#define BITS_TC4DATA_8197F (BIT_MASK_TC4DATA_8197F << BIT_SHIFT_TC4DATA_8197F)\n#define BIT_CLEAR_TC4DATA_8197F(x) ((x) & (~BITS_TC4DATA_8197F))\n#define BIT_GET_TC4DATA_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC4DATA_8197F) & BIT_MASK_TC4DATA_8197F)\n#define BIT_SET_TC4DATA_8197F(x, v)                                            \\\n\t(BIT_CLEAR_TC4DATA_8197F(x) | BIT_TC4DATA_8197F(v))\n\n/* 2 REG_TCUNIT_BASE_8197F */\n\n#define BIT_SHIFT_TCUNIT_BASE_8197F 0\n#define BIT_MASK_TCUNIT_BASE_8197F 0x3fff\n#define BIT_TCUNIT_BASE_8197F(x)                                               \\\n\t(((x) & BIT_MASK_TCUNIT_BASE_8197F) << BIT_SHIFT_TCUNIT_BASE_8197F)\n#define BITS_TCUNIT_BASE_8197F                                                 \\\n\t(BIT_MASK_TCUNIT_BASE_8197F << BIT_SHIFT_TCUNIT_BASE_8197F)\n#define BIT_CLEAR_TCUNIT_BASE_8197F(x) ((x) & (~BITS_TCUNIT_BASE_8197F))\n#define BIT_GET_TCUNIT_BASE_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_TCUNIT_BASE_8197F) & BIT_MASK_TCUNIT_BASE_8197F)\n#define BIT_SET_TCUNIT_BASE_8197F(x, v)                                        \\\n\t(BIT_CLEAR_TCUNIT_BASE_8197F(x) | BIT_TCUNIT_BASE_8197F(v))\n\n/* 2 REG_TC5_CTRL_8197F */\n#define BIT_TC5INT_EN_8197F BIT(26)\n#define BIT_TC5MODE_8197F BIT(25)\n#define BIT_TC5EN_8197F BIT(24)\n\n#define BIT_SHIFT_TC5DATA_8197F 0\n#define BIT_MASK_TC5DATA_8197F 0xffffff\n#define BIT_TC5DATA_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_TC5DATA_8197F) << BIT_SHIFT_TC5DATA_8197F)\n#define BITS_TC5DATA_8197F (BIT_MASK_TC5DATA_8197F << BIT_SHIFT_TC5DATA_8197F)\n#define BIT_CLEAR_TC5DATA_8197F(x) ((x) & (~BITS_TC5DATA_8197F))\n#define BIT_GET_TC5DATA_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC5DATA_8197F) & BIT_MASK_TC5DATA_8197F)\n#define BIT_SET_TC5DATA_8197F(x, v)                                            \\\n\t(BIT_CLEAR_TC5DATA_8197F(x) | BIT_TC5DATA_8197F(v))\n\n/* 2 REG_TC6_CTRL_8197F */\n#define BIT_TC6INT_EN_8197F BIT(26)\n#define BIT_TC6MODE_8197F BIT(25)\n#define BIT_TC6EN_8197F BIT(24)\n\n#define BIT_SHIFT_TC6DATA_8197F 0\n#define BIT_MASK_TC6DATA_8197F 0xffffff\n#define BIT_TC6DATA_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_TC6DATA_8197F) << BIT_SHIFT_TC6DATA_8197F)\n#define BITS_TC6DATA_8197F (BIT_MASK_TC6DATA_8197F << BIT_SHIFT_TC6DATA_8197F)\n#define BIT_CLEAR_TC6DATA_8197F(x) ((x) & (~BITS_TC6DATA_8197F))\n#define BIT_GET_TC6DATA_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC6DATA_8197F) & BIT_MASK_TC6DATA_8197F)\n#define BIT_SET_TC6DATA_8197F(x, v)                                            \\\n\t(BIT_CLEAR_TC6DATA_8197F(x) | BIT_TC6DATA_8197F(v))\n\n/* 2 REG_MBIST_FAIL_8197F */\n\n#define BIT_SHIFT_8051_MBIST_FAIL_8197F 26\n#define BIT_MASK_8051_MBIST_FAIL_8197F 0x7\n#define BIT_8051_MBIST_FAIL_8197F(x)                                           \\\n\t(((x) & BIT_MASK_8051_MBIST_FAIL_8197F)                                \\\n\t << BIT_SHIFT_8051_MBIST_FAIL_8197F)\n#define BITS_8051_MBIST_FAIL_8197F                                             \\\n\t(BIT_MASK_8051_MBIST_FAIL_8197F << BIT_SHIFT_8051_MBIST_FAIL_8197F)\n#define BIT_CLEAR_8051_MBIST_FAIL_8197F(x) ((x) & (~BITS_8051_MBIST_FAIL_8197F))\n#define BIT_GET_8051_MBIST_FAIL_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_FAIL_8197F) &                            \\\n\t BIT_MASK_8051_MBIST_FAIL_8197F)\n#define BIT_SET_8051_MBIST_FAIL_8197F(x, v)                                    \\\n\t(BIT_CLEAR_8051_MBIST_FAIL_8197F(x) | BIT_8051_MBIST_FAIL_8197F(v))\n\n#define BIT_SHIFT_USB_MBIST_FAIL_8197F 24\n#define BIT_MASK_USB_MBIST_FAIL_8197F 0x3\n#define BIT_USB_MBIST_FAIL_8197F(x)                                            \\\n\t(((x) & BIT_MASK_USB_MBIST_FAIL_8197F)                                 \\\n\t << BIT_SHIFT_USB_MBIST_FAIL_8197F)\n#define BITS_USB_MBIST_FAIL_8197F                                              \\\n\t(BIT_MASK_USB_MBIST_FAIL_8197F << BIT_SHIFT_USB_MBIST_FAIL_8197F)\n#define BIT_CLEAR_USB_MBIST_FAIL_8197F(x) ((x) & (~BITS_USB_MBIST_FAIL_8197F))\n#define BIT_GET_USB_MBIST_FAIL_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_FAIL_8197F) &                             \\\n\t BIT_MASK_USB_MBIST_FAIL_8197F)\n#define BIT_SET_USB_MBIST_FAIL_8197F(x, v)                                     \\\n\t(BIT_CLEAR_USB_MBIST_FAIL_8197F(x) | BIT_USB_MBIST_FAIL_8197F(v))\n\n#define BIT_SHIFT_PCIE_MBIST_FAIL_8197F 16\n#define BIT_MASK_PCIE_MBIST_FAIL_8197F 0x3f\n#define BIT_PCIE_MBIST_FAIL_8197F(x)                                           \\\n\t(((x) & BIT_MASK_PCIE_MBIST_FAIL_8197F)                                \\\n\t << BIT_SHIFT_PCIE_MBIST_FAIL_8197F)\n#define BITS_PCIE_MBIST_FAIL_8197F                                             \\\n\t(BIT_MASK_PCIE_MBIST_FAIL_8197F << BIT_SHIFT_PCIE_MBIST_FAIL_8197F)\n#define BIT_CLEAR_PCIE_MBIST_FAIL_8197F(x) ((x) & (~BITS_PCIE_MBIST_FAIL_8197F))\n#define BIT_GET_PCIE_MBIST_FAIL_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8197F) &                            \\\n\t BIT_MASK_PCIE_MBIST_FAIL_8197F)\n#define BIT_SET_PCIE_MBIST_FAIL_8197F(x, v)                                    \\\n\t(BIT_CLEAR_PCIE_MBIST_FAIL_8197F(x) | BIT_PCIE_MBIST_FAIL_8197F(v))\n\n#define BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F 0\n#define BIT_MASK_MAC_MBIST_FAIL_DRF_8197F 0x3ffff\n#define BIT_MAC_MBIST_FAIL_DRF_8197F(x)                                        \\\n\t(((x) & BIT_MASK_MAC_MBIST_FAIL_DRF_8197F)                             \\\n\t << BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F)\n#define BITS_MAC_MBIST_FAIL_DRF_8197F                                          \\\n\t(BIT_MASK_MAC_MBIST_FAIL_DRF_8197F                                     \\\n\t << BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F)\n#define BIT_CLEAR_MAC_MBIST_FAIL_DRF_8197F(x)                                  \\\n\t((x) & (~BITS_MAC_MBIST_FAIL_DRF_8197F))\n#define BIT_GET_MAC_MBIST_FAIL_DRF_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) &                         \\\n\t BIT_MASK_MAC_MBIST_FAIL_DRF_8197F)\n#define BIT_SET_MAC_MBIST_FAIL_DRF_8197F(x, v)                                 \\\n\t(BIT_CLEAR_MAC_MBIST_FAIL_DRF_8197F(x) |                               \\\n\t BIT_MAC_MBIST_FAIL_DRF_8197F(v))\n\n/* 2 REG_MBIST_START_PAUSE_8197F */\n\n#define BIT_SHIFT_8051_MBIST_START_PAUSE_8197F 26\n#define BIT_MASK_8051_MBIST_START_PAUSE_8197F 0x7\n#define BIT_8051_MBIST_START_PAUSE_8197F(x)                                    \\\n\t(((x) & BIT_MASK_8051_MBIST_START_PAUSE_8197F)                         \\\n\t << BIT_SHIFT_8051_MBIST_START_PAUSE_8197F)\n#define BITS_8051_MBIST_START_PAUSE_8197F                                      \\\n\t(BIT_MASK_8051_MBIST_START_PAUSE_8197F                                 \\\n\t << BIT_SHIFT_8051_MBIST_START_PAUSE_8197F)\n#define BIT_CLEAR_8051_MBIST_START_PAUSE_8197F(x)                              \\\n\t((x) & (~BITS_8051_MBIST_START_PAUSE_8197F))\n#define BIT_GET_8051_MBIST_START_PAUSE_8197F(x)                                \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) &                     \\\n\t BIT_MASK_8051_MBIST_START_PAUSE_8197F)\n#define BIT_SET_8051_MBIST_START_PAUSE_8197F(x, v)                             \\\n\t(BIT_CLEAR_8051_MBIST_START_PAUSE_8197F(x) |                           \\\n\t BIT_8051_MBIST_START_PAUSE_8197F(v))\n\n#define BIT_SHIFT_USB_MBIST_START_PAUSE_8197F 24\n#define BIT_MASK_USB_MBIST_START_PAUSE_8197F 0x3\n#define BIT_USB_MBIST_START_PAUSE_8197F(x)                                     \\\n\t(((x) & BIT_MASK_USB_MBIST_START_PAUSE_8197F)                          \\\n\t << BIT_SHIFT_USB_MBIST_START_PAUSE_8197F)\n#define BITS_USB_MBIST_START_PAUSE_8197F                                       \\\n\t(BIT_MASK_USB_MBIST_START_PAUSE_8197F                                  \\\n\t << BIT_SHIFT_USB_MBIST_START_PAUSE_8197F)\n#define BIT_CLEAR_USB_MBIST_START_PAUSE_8197F(x)                               \\\n\t((x) & (~BITS_USB_MBIST_START_PAUSE_8197F))\n#define BIT_GET_USB_MBIST_START_PAUSE_8197F(x)                                 \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) &                      \\\n\t BIT_MASK_USB_MBIST_START_PAUSE_8197F)\n#define BIT_SET_USB_MBIST_START_PAUSE_8197F(x, v)                              \\\n\t(BIT_CLEAR_USB_MBIST_START_PAUSE_8197F(x) |                            \\\n\t BIT_USB_MBIST_START_PAUSE_8197F(v))\n\n#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F 16\n#define BIT_MASK_PCIE_MBIST_START_PAUSE_8197F 0x3f\n#define BIT_PCIE_MBIST_START_PAUSE_8197F(x)                                    \\\n\t(((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8197F)                         \\\n\t << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F)\n#define BITS_PCIE_MBIST_START_PAUSE_8197F                                      \\\n\t(BIT_MASK_PCIE_MBIST_START_PAUSE_8197F                                 \\\n\t << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F)\n#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_8197F(x)                              \\\n\t((x) & (~BITS_PCIE_MBIST_START_PAUSE_8197F))\n#define BIT_GET_PCIE_MBIST_START_PAUSE_8197F(x)                                \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) &                     \\\n\t BIT_MASK_PCIE_MBIST_START_PAUSE_8197F)\n#define BIT_SET_PCIE_MBIST_START_PAUSE_8197F(x, v)                             \\\n\t(BIT_CLEAR_PCIE_MBIST_START_PAUSE_8197F(x) |                           \\\n\t BIT_PCIE_MBIST_START_PAUSE_8197F(v))\n\n#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F 0\n#define BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F 0x3ffff\n#define BIT_MAC_MBIST_START_PAUSE_V1_8197F(x)                                  \\\n\t(((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F)                       \\\n\t << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F)\n#define BITS_MAC_MBIST_START_PAUSE_V1_8197F                                    \\\n\t(BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F                               \\\n\t << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F)\n#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8197F(x)                            \\\n\t((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8197F))\n#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8197F(x)                              \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) &                   \\\n\t BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F)\n#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8197F(x, v)                           \\\n\t(BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8197F(x) |                         \\\n\t BIT_MAC_MBIST_START_PAUSE_V1_8197F(v))\n\n/* 2 REG_MBIST_DONE_8197F */\n\n#define BIT_SHIFT_8051_MBIST_DONE_8197F 26\n#define BIT_MASK_8051_MBIST_DONE_8197F 0x7\n#define BIT_8051_MBIST_DONE_8197F(x)                                           \\\n\t(((x) & BIT_MASK_8051_MBIST_DONE_8197F)                                \\\n\t << BIT_SHIFT_8051_MBIST_DONE_8197F)\n#define BITS_8051_MBIST_DONE_8197F                                             \\\n\t(BIT_MASK_8051_MBIST_DONE_8197F << BIT_SHIFT_8051_MBIST_DONE_8197F)\n#define BIT_CLEAR_8051_MBIST_DONE_8197F(x) ((x) & (~BITS_8051_MBIST_DONE_8197F))\n#define BIT_GET_8051_MBIST_DONE_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_DONE_8197F) &                            \\\n\t BIT_MASK_8051_MBIST_DONE_8197F)\n#define BIT_SET_8051_MBIST_DONE_8197F(x, v)                                    \\\n\t(BIT_CLEAR_8051_MBIST_DONE_8197F(x) | BIT_8051_MBIST_DONE_8197F(v))\n\n#define BIT_SHIFT_USB_MBIST_DONE_8197F 24\n#define BIT_MASK_USB_MBIST_DONE_8197F 0x3\n#define BIT_USB_MBIST_DONE_8197F(x)                                            \\\n\t(((x) & BIT_MASK_USB_MBIST_DONE_8197F)                                 \\\n\t << BIT_SHIFT_USB_MBIST_DONE_8197F)\n#define BITS_USB_MBIST_DONE_8197F                                              \\\n\t(BIT_MASK_USB_MBIST_DONE_8197F << BIT_SHIFT_USB_MBIST_DONE_8197F)\n#define BIT_CLEAR_USB_MBIST_DONE_8197F(x) ((x) & (~BITS_USB_MBIST_DONE_8197F))\n#define BIT_GET_USB_MBIST_DONE_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_DONE_8197F) &                             \\\n\t BIT_MASK_USB_MBIST_DONE_8197F)\n#define BIT_SET_USB_MBIST_DONE_8197F(x, v)                                     \\\n\t(BIT_CLEAR_USB_MBIST_DONE_8197F(x) | BIT_USB_MBIST_DONE_8197F(v))\n\n#define BIT_SHIFT_PCIE_MBIST_DONE_8197F 16\n#define BIT_MASK_PCIE_MBIST_DONE_8197F 0x3f\n#define BIT_PCIE_MBIST_DONE_8197F(x)                                           \\\n\t(((x) & BIT_MASK_PCIE_MBIST_DONE_8197F)                                \\\n\t << BIT_SHIFT_PCIE_MBIST_DONE_8197F)\n#define BITS_PCIE_MBIST_DONE_8197F                                             \\\n\t(BIT_MASK_PCIE_MBIST_DONE_8197F << BIT_SHIFT_PCIE_MBIST_DONE_8197F)\n#define BIT_CLEAR_PCIE_MBIST_DONE_8197F(x) ((x) & (~BITS_PCIE_MBIST_DONE_8197F))\n#define BIT_GET_PCIE_MBIST_DONE_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8197F) &                            \\\n\t BIT_MASK_PCIE_MBIST_DONE_8197F)\n#define BIT_SET_PCIE_MBIST_DONE_8197F(x, v)                                    \\\n\t(BIT_CLEAR_PCIE_MBIST_DONE_8197F(x) | BIT_PCIE_MBIST_DONE_8197F(v))\n\n#define BIT_SHIFT_MAC_MBIST_DONE_V1_8197F 0\n#define BIT_MASK_MAC_MBIST_DONE_V1_8197F 0x3ffff\n#define BIT_MAC_MBIST_DONE_V1_8197F(x)                                         \\\n\t(((x) & BIT_MASK_MAC_MBIST_DONE_V1_8197F)                              \\\n\t << BIT_SHIFT_MAC_MBIST_DONE_V1_8197F)\n#define BITS_MAC_MBIST_DONE_V1_8197F                                           \\\n\t(BIT_MASK_MAC_MBIST_DONE_V1_8197F << BIT_SHIFT_MAC_MBIST_DONE_V1_8197F)\n#define BIT_CLEAR_MAC_MBIST_DONE_V1_8197F(x)                                   \\\n\t((x) & (~BITS_MAC_MBIST_DONE_V1_8197F))\n#define BIT_GET_MAC_MBIST_DONE_V1_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) &                          \\\n\t BIT_MASK_MAC_MBIST_DONE_V1_8197F)\n#define BIT_SET_MAC_MBIST_DONE_V1_8197F(x, v)                                  \\\n\t(BIT_CLEAR_MAC_MBIST_DONE_V1_8197F(x) | BIT_MAC_MBIST_DONE_V1_8197F(v))\n\n/* 2 REG_MBIST_FAIL_NRML_8197F */\n\n#define BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F 0\n#define BIT_MASK_MBIST_FAIL_NRML_V1_8197F 0x3ffff\n#define BIT_MBIST_FAIL_NRML_V1_8197F(x)                                        \\\n\t(((x) & BIT_MASK_MBIST_FAIL_NRML_V1_8197F)                             \\\n\t << BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F)\n#define BITS_MBIST_FAIL_NRML_V1_8197F                                          \\\n\t(BIT_MASK_MBIST_FAIL_NRML_V1_8197F                                     \\\n\t << BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F)\n#define BIT_CLEAR_MBIST_FAIL_NRML_V1_8197F(x)                                  \\\n\t((x) & (~BITS_MBIST_FAIL_NRML_V1_8197F))\n#define BIT_GET_MBIST_FAIL_NRML_V1_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) &                         \\\n\t BIT_MASK_MBIST_FAIL_NRML_V1_8197F)\n#define BIT_SET_MBIST_FAIL_NRML_V1_8197F(x, v)                                 \\\n\t(BIT_CLEAR_MBIST_FAIL_NRML_V1_8197F(x) |                               \\\n\t BIT_MBIST_FAIL_NRML_V1_8197F(v))\n\n/* 2 REG_AES_DECRPT_DATA_8197F */\n\n#define BIT_SHIFT_IPS_CFG_ADDR_8197F 0\n#define BIT_MASK_IPS_CFG_ADDR_8197F 0xff\n#define BIT_IPS_CFG_ADDR_8197F(x)                                              \\\n\t(((x) & BIT_MASK_IPS_CFG_ADDR_8197F) << BIT_SHIFT_IPS_CFG_ADDR_8197F)\n#define BITS_IPS_CFG_ADDR_8197F                                                \\\n\t(BIT_MASK_IPS_CFG_ADDR_8197F << BIT_SHIFT_IPS_CFG_ADDR_8197F)\n#define BIT_CLEAR_IPS_CFG_ADDR_8197F(x) ((x) & (~BITS_IPS_CFG_ADDR_8197F))\n#define BIT_GET_IPS_CFG_ADDR_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_IPS_CFG_ADDR_8197F) & BIT_MASK_IPS_CFG_ADDR_8197F)\n#define BIT_SET_IPS_CFG_ADDR_8197F(x, v)                                       \\\n\t(BIT_CLEAR_IPS_CFG_ADDR_8197F(x) | BIT_IPS_CFG_ADDR_8197F(v))\n\n/* 2 REG_AES_DECRPT_CFG_8197F */\n\n#define BIT_SHIFT_IPS_CFG_DATA_8197F 0\n#define BIT_MASK_IPS_CFG_DATA_8197F 0xffffffffL\n#define BIT_IPS_CFG_DATA_8197F(x)                                              \\\n\t(((x) & BIT_MASK_IPS_CFG_DATA_8197F) << BIT_SHIFT_IPS_CFG_DATA_8197F)\n#define BITS_IPS_CFG_DATA_8197F                                                \\\n\t(BIT_MASK_IPS_CFG_DATA_8197F << BIT_SHIFT_IPS_CFG_DATA_8197F)\n#define BIT_CLEAR_IPS_CFG_DATA_8197F(x) ((x) & (~BITS_IPS_CFG_DATA_8197F))\n#define BIT_GET_IPS_CFG_DATA_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_IPS_CFG_DATA_8197F) & BIT_MASK_IPS_CFG_DATA_8197F)\n#define BIT_SET_IPS_CFG_DATA_8197F(x, v)                                       \\\n\t(BIT_CLEAR_IPS_CFG_DATA_8197F(x) | BIT_IPS_CFG_DATA_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_MACCLKFRQ_8197F */\n\n#define BIT_SHIFT_MACCLK_FREQ_LOW32_8197F 0\n#define BIT_MASK_MACCLK_FREQ_LOW32_8197F 0xffffffffL\n#define BIT_MACCLK_FREQ_LOW32_8197F(x)                                         \\\n\t(((x) & BIT_MASK_MACCLK_FREQ_LOW32_8197F)                              \\\n\t << BIT_SHIFT_MACCLK_FREQ_LOW32_8197F)\n#define BITS_MACCLK_FREQ_LOW32_8197F                                           \\\n\t(BIT_MASK_MACCLK_FREQ_LOW32_8197F << BIT_SHIFT_MACCLK_FREQ_LOW32_8197F)\n#define BIT_CLEAR_MACCLK_FREQ_LOW32_8197F(x)                                   \\\n\t((x) & (~BITS_MACCLK_FREQ_LOW32_8197F))\n#define BIT_GET_MACCLK_FREQ_LOW32_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) &                          \\\n\t BIT_MASK_MACCLK_FREQ_LOW32_8197F)\n#define BIT_SET_MACCLK_FREQ_LOW32_8197F(x, v)                                  \\\n\t(BIT_CLEAR_MACCLK_FREQ_LOW32_8197F(x) | BIT_MACCLK_FREQ_LOW32_8197F(v))\n\n/* 2 REG_TMETER_8197F */\n\n#define BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F 0\n#define BIT_MASK_MACCLK_FREQ_HIGH10_8197F 0x3ff\n#define BIT_MACCLK_FREQ_HIGH10_8197F(x)                                        \\\n\t(((x) & BIT_MASK_MACCLK_FREQ_HIGH10_8197F)                             \\\n\t << BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F)\n#define BITS_MACCLK_FREQ_HIGH10_8197F                                          \\\n\t(BIT_MASK_MACCLK_FREQ_HIGH10_8197F                                     \\\n\t << BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F)\n#define BIT_CLEAR_MACCLK_FREQ_HIGH10_8197F(x)                                  \\\n\t((x) & (~BITS_MACCLK_FREQ_HIGH10_8197F))\n#define BIT_GET_MACCLK_FREQ_HIGH10_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) &                         \\\n\t BIT_MASK_MACCLK_FREQ_HIGH10_8197F)\n#define BIT_SET_MACCLK_FREQ_HIGH10_8197F(x, v)                                 \\\n\t(BIT_CLEAR_MACCLK_FREQ_HIGH10_8197F(x) |                               \\\n\t BIT_MACCLK_FREQ_HIGH10_8197F(v))\n\n/* 2 REG_OSC_32K_CTRL_8197F */\n#define BIT_32K_CLK_OUT_RDY_8197F BIT(12)\n\n#define BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F 8\n#define BIT_MASK_MONITOR_CYCLE_LOG2_8197F 0xf\n#define BIT_MONITOR_CYCLE_LOG2_8197F(x)                                        \\\n\t(((x) & BIT_MASK_MONITOR_CYCLE_LOG2_8197F)                             \\\n\t << BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F)\n#define BITS_MONITOR_CYCLE_LOG2_8197F                                          \\\n\t(BIT_MASK_MONITOR_CYCLE_LOG2_8197F                                     \\\n\t << BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F)\n#define BIT_CLEAR_MONITOR_CYCLE_LOG2_8197F(x)                                  \\\n\t((x) & (~BITS_MONITOR_CYCLE_LOG2_8197F))\n#define BIT_GET_MONITOR_CYCLE_LOG2_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) &                         \\\n\t BIT_MASK_MONITOR_CYCLE_LOG2_8197F)\n#define BIT_SET_MONITOR_CYCLE_LOG2_8197F(x, v)                                 \\\n\t(BIT_CLEAR_MONITOR_CYCLE_LOG2_8197F(x) |                               \\\n\t BIT_MONITOR_CYCLE_LOG2_8197F(v))\n\n/* 2 REG_32K_CAL_REG1_8197F */\n\n#define BIT_SHIFT_FREQVALUE_UNREGCLK_8197F 8\n#define BIT_MASK_FREQVALUE_UNREGCLK_8197F 0xffffff\n#define BIT_FREQVALUE_UNREGCLK_8197F(x)                                        \\\n\t(((x) & BIT_MASK_FREQVALUE_UNREGCLK_8197F)                             \\\n\t << BIT_SHIFT_FREQVALUE_UNREGCLK_8197F)\n#define BITS_FREQVALUE_UNREGCLK_8197F                                          \\\n\t(BIT_MASK_FREQVALUE_UNREGCLK_8197F                                     \\\n\t << BIT_SHIFT_FREQVALUE_UNREGCLK_8197F)\n#define BIT_CLEAR_FREQVALUE_UNREGCLK_8197F(x)                                  \\\n\t((x) & (~BITS_FREQVALUE_UNREGCLK_8197F))\n#define BIT_GET_FREQVALUE_UNREGCLK_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) &                         \\\n\t BIT_MASK_FREQVALUE_UNREGCLK_8197F)\n#define BIT_SET_FREQVALUE_UNREGCLK_8197F(x, v)                                 \\\n\t(BIT_CLEAR_FREQVALUE_UNREGCLK_8197F(x) |                               \\\n\t BIT_FREQVALUE_UNREGCLK_8197F(v))\n\n#define BIT_CAL32K_DBGMOD_8197F BIT(7)\n\n#define BIT_SHIFT_NCO_THRS_8197F 0\n#define BIT_MASK_NCO_THRS_8197F 0x7f\n#define BIT_NCO_THRS_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_NCO_THRS_8197F) << BIT_SHIFT_NCO_THRS_8197F)\n#define BITS_NCO_THRS_8197F                                                    \\\n\t(BIT_MASK_NCO_THRS_8197F << BIT_SHIFT_NCO_THRS_8197F)\n#define BIT_CLEAR_NCO_THRS_8197F(x) ((x) & (~BITS_NCO_THRS_8197F))\n#define BIT_GET_NCO_THRS_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_NCO_THRS_8197F) & BIT_MASK_NCO_THRS_8197F)\n#define BIT_SET_NCO_THRS_8197F(x, v)                                           \\\n\t(BIT_CLEAR_NCO_THRS_8197F(x) | BIT_NCO_THRS_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_C2HEVT_8197F */\n\n#define BIT_SHIFT_C2HEVT_MSG_8197F 0\n#define BIT_MASK_C2HEVT_MSG_8197F 0xffffffffffffffffffffffffffffffffL\n#define BIT_C2HEVT_MSG_8197F(x)                                                \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_8197F) << BIT_SHIFT_C2HEVT_MSG_8197F)\n#define BITS_C2HEVT_MSG_8197F                                                  \\\n\t(BIT_MASK_C2HEVT_MSG_8197F << BIT_SHIFT_C2HEVT_MSG_8197F)\n#define BIT_CLEAR_C2HEVT_MSG_8197F(x) ((x) & (~BITS_C2HEVT_MSG_8197F))\n#define BIT_GET_C2HEVT_MSG_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_8197F) & BIT_MASK_C2HEVT_MSG_8197F)\n#define BIT_SET_C2HEVT_MSG_8197F(x, v)                                         \\\n\t(BIT_CLEAR_C2HEVT_MSG_8197F(x) | BIT_C2HEVT_MSG_8197F(v))\n\n/* 2 REG_SW_DEFINED_PAGE1_8197F */\n\n#define BIT_SHIFT_SW_DEFINED_PAGE1_8197F 0\n#define BIT_MASK_SW_DEFINED_PAGE1_8197F 0xffffffffffffffffL\n#define BIT_SW_DEFINED_PAGE1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_SW_DEFINED_PAGE1_8197F)                               \\\n\t << BIT_SHIFT_SW_DEFINED_PAGE1_8197F)\n#define BITS_SW_DEFINED_PAGE1_8197F                                            \\\n\t(BIT_MASK_SW_DEFINED_PAGE1_8197F << BIT_SHIFT_SW_DEFINED_PAGE1_8197F)\n#define BIT_CLEAR_SW_DEFINED_PAGE1_8197F(x)                                    \\\n\t((x) & (~BITS_SW_DEFINED_PAGE1_8197F))\n#define BIT_GET_SW_DEFINED_PAGE1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8197F) &                           \\\n\t BIT_MASK_SW_DEFINED_PAGE1_8197F)\n#define BIT_SET_SW_DEFINED_PAGE1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_SW_DEFINED_PAGE1_8197F(x) | BIT_SW_DEFINED_PAGE1_8197F(v))\n\n/* 2 REG_MCUTST_I_8197F */\n\n#define BIT_SHIFT_MCUDMSG_I_8197F 0\n#define BIT_MASK_MCUDMSG_I_8197F 0xffffffffL\n#define BIT_MCUDMSG_I_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_MCUDMSG_I_8197F) << BIT_SHIFT_MCUDMSG_I_8197F)\n#define BITS_MCUDMSG_I_8197F                                                   \\\n\t(BIT_MASK_MCUDMSG_I_8197F << BIT_SHIFT_MCUDMSG_I_8197F)\n#define BIT_CLEAR_MCUDMSG_I_8197F(x) ((x) & (~BITS_MCUDMSG_I_8197F))\n#define BIT_GET_MCUDMSG_I_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_MCUDMSG_I_8197F) & BIT_MASK_MCUDMSG_I_8197F)\n#define BIT_SET_MCUDMSG_I_8197F(x, v)                                          \\\n\t(BIT_CLEAR_MCUDMSG_I_8197F(x) | BIT_MCUDMSG_I_8197F(v))\n\n/* 2 REG_MCUTST_II_8197F */\n\n#define BIT_SHIFT_MCUDMSG_II_8197F 0\n#define BIT_MASK_MCUDMSG_II_8197F 0xffffffffL\n#define BIT_MCUDMSG_II_8197F(x)                                                \\\n\t(((x) & BIT_MASK_MCUDMSG_II_8197F) << BIT_SHIFT_MCUDMSG_II_8197F)\n#define BITS_MCUDMSG_II_8197F                                                  \\\n\t(BIT_MASK_MCUDMSG_II_8197F << BIT_SHIFT_MCUDMSG_II_8197F)\n#define BIT_CLEAR_MCUDMSG_II_8197F(x) ((x) & (~BITS_MCUDMSG_II_8197F))\n#define BIT_GET_MCUDMSG_II_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_MCUDMSG_II_8197F) & BIT_MASK_MCUDMSG_II_8197F)\n#define BIT_SET_MCUDMSG_II_8197F(x, v)                                         \\\n\t(BIT_CLEAR_MCUDMSG_II_8197F(x) | BIT_MCUDMSG_II_8197F(v))\n\n/* 2 REG_FMETHR_8197F */\n#define BIT_FMSG_INT_8197F BIT(31)\n\n#define BIT_SHIFT_FW_MSG_8197F 0\n#define BIT_MASK_FW_MSG_8197F 0xffffffffL\n#define BIT_FW_MSG_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_FW_MSG_8197F) << BIT_SHIFT_FW_MSG_8197F)\n#define BITS_FW_MSG_8197F (BIT_MASK_FW_MSG_8197F << BIT_SHIFT_FW_MSG_8197F)\n#define BIT_CLEAR_FW_MSG_8197F(x) ((x) & (~BITS_FW_MSG_8197F))\n#define BIT_GET_FW_MSG_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_FW_MSG_8197F) & BIT_MASK_FW_MSG_8197F)\n#define BIT_SET_FW_MSG_8197F(x, v)                                             \\\n\t(BIT_CLEAR_FW_MSG_8197F(x) | BIT_FW_MSG_8197F(v))\n\n/* 2 REG_HMETFR_8197F */\n\n#define BIT_SHIFT_HRCV_MSG_8197F 24\n#define BIT_MASK_HRCV_MSG_8197F 0xff\n#define BIT_HRCV_MSG_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_HRCV_MSG_8197F) << BIT_SHIFT_HRCV_MSG_8197F)\n#define BITS_HRCV_MSG_8197F                                                    \\\n\t(BIT_MASK_HRCV_MSG_8197F << BIT_SHIFT_HRCV_MSG_8197F)\n#define BIT_CLEAR_HRCV_MSG_8197F(x) ((x) & (~BITS_HRCV_MSG_8197F))\n#define BIT_GET_HRCV_MSG_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_HRCV_MSG_8197F) & BIT_MASK_HRCV_MSG_8197F)\n#define BIT_SET_HRCV_MSG_8197F(x, v)                                           \\\n\t(BIT_CLEAR_HRCV_MSG_8197F(x) | BIT_HRCV_MSG_8197F(v))\n\n#define BIT_INT_BOX3_8197F BIT(3)\n#define BIT_INT_BOX2_8197F BIT(2)\n#define BIT_INT_BOX1_8197F BIT(1)\n#define BIT_INT_BOX0_8197F BIT(0)\n\n/* 2 REG_HMEBOX0_8197F */\n\n#define BIT_SHIFT_HOST_MSG_0_8197F 0\n#define BIT_MASK_HOST_MSG_0_8197F 0xffffffffL\n#define BIT_HOST_MSG_0_8197F(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_0_8197F) << BIT_SHIFT_HOST_MSG_0_8197F)\n#define BITS_HOST_MSG_0_8197F                                                  \\\n\t(BIT_MASK_HOST_MSG_0_8197F << BIT_SHIFT_HOST_MSG_0_8197F)\n#define BIT_CLEAR_HOST_MSG_0_8197F(x) ((x) & (~BITS_HOST_MSG_0_8197F))\n#define BIT_GET_HOST_MSG_0_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_0_8197F) & BIT_MASK_HOST_MSG_0_8197F)\n#define BIT_SET_HOST_MSG_0_8197F(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_0_8197F(x) | BIT_HOST_MSG_0_8197F(v))\n\n/* 2 REG_HMEBOX1_8197F */\n\n#define BIT_SHIFT_HOST_MSG_1_8197F 0\n#define BIT_MASK_HOST_MSG_1_8197F 0xffffffffL\n#define BIT_HOST_MSG_1_8197F(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_1_8197F) << BIT_SHIFT_HOST_MSG_1_8197F)\n#define BITS_HOST_MSG_1_8197F                                                  \\\n\t(BIT_MASK_HOST_MSG_1_8197F << BIT_SHIFT_HOST_MSG_1_8197F)\n#define BIT_CLEAR_HOST_MSG_1_8197F(x) ((x) & (~BITS_HOST_MSG_1_8197F))\n#define BIT_GET_HOST_MSG_1_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_1_8197F) & BIT_MASK_HOST_MSG_1_8197F)\n#define BIT_SET_HOST_MSG_1_8197F(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_1_8197F(x) | BIT_HOST_MSG_1_8197F(v))\n\n/* 2 REG_HMEBOX2_8197F */\n\n#define BIT_SHIFT_HOST_MSG_2_8197F 0\n#define BIT_MASK_HOST_MSG_2_8197F 0xffffffffL\n#define BIT_HOST_MSG_2_8197F(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_2_8197F) << BIT_SHIFT_HOST_MSG_2_8197F)\n#define BITS_HOST_MSG_2_8197F                                                  \\\n\t(BIT_MASK_HOST_MSG_2_8197F << BIT_SHIFT_HOST_MSG_2_8197F)\n#define BIT_CLEAR_HOST_MSG_2_8197F(x) ((x) & (~BITS_HOST_MSG_2_8197F))\n#define BIT_GET_HOST_MSG_2_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_2_8197F) & BIT_MASK_HOST_MSG_2_8197F)\n#define BIT_SET_HOST_MSG_2_8197F(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_2_8197F(x) | BIT_HOST_MSG_2_8197F(v))\n\n/* 2 REG_HMEBOX3_8197F */\n\n#define BIT_SHIFT_HOST_MSG_3_8197F 0\n#define BIT_MASK_HOST_MSG_3_8197F 0xffffffffL\n#define BIT_HOST_MSG_3_8197F(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_3_8197F) << BIT_SHIFT_HOST_MSG_3_8197F)\n#define BITS_HOST_MSG_3_8197F                                                  \\\n\t(BIT_MASK_HOST_MSG_3_8197F << BIT_SHIFT_HOST_MSG_3_8197F)\n#define BIT_CLEAR_HOST_MSG_3_8197F(x) ((x) & (~BITS_HOST_MSG_3_8197F))\n#define BIT_GET_HOST_MSG_3_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_3_8197F) & BIT_MASK_HOST_MSG_3_8197F)\n#define BIT_SET_HOST_MSG_3_8197F(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_3_8197F(x) | BIT_HOST_MSG_3_8197F(v))\n\n/* 2 REG_LLT_INIT_8197F */\n\n#define BIT_SHIFT_LLTE_RWM_8197F 30\n#define BIT_MASK_LLTE_RWM_8197F 0x3\n#define BIT_LLTE_RWM_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_LLTE_RWM_8197F) << BIT_SHIFT_LLTE_RWM_8197F)\n#define BITS_LLTE_RWM_8197F                                                    \\\n\t(BIT_MASK_LLTE_RWM_8197F << BIT_SHIFT_LLTE_RWM_8197F)\n#define BIT_CLEAR_LLTE_RWM_8197F(x) ((x) & (~BITS_LLTE_RWM_8197F))\n#define BIT_GET_LLTE_RWM_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_LLTE_RWM_8197F) & BIT_MASK_LLTE_RWM_8197F)\n#define BIT_SET_LLTE_RWM_8197F(x, v)                                           \\\n\t(BIT_CLEAR_LLTE_RWM_8197F(x) | BIT_LLTE_RWM_8197F(v))\n\n#define BIT_SHIFT_LLTINI_PDATA_V1_8197F 16\n#define BIT_MASK_LLTINI_PDATA_V1_8197F 0xfff\n#define BIT_LLTINI_PDATA_V1_8197F(x)                                           \\\n\t(((x) & BIT_MASK_LLTINI_PDATA_V1_8197F)                                \\\n\t << BIT_SHIFT_LLTINI_PDATA_V1_8197F)\n#define BITS_LLTINI_PDATA_V1_8197F                                             \\\n\t(BIT_MASK_LLTINI_PDATA_V1_8197F << BIT_SHIFT_LLTINI_PDATA_V1_8197F)\n#define BIT_CLEAR_LLTINI_PDATA_V1_8197F(x) ((x) & (~BITS_LLTINI_PDATA_V1_8197F))\n#define BIT_GET_LLTINI_PDATA_V1_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8197F) &                            \\\n\t BIT_MASK_LLTINI_PDATA_V1_8197F)\n#define BIT_SET_LLTINI_PDATA_V1_8197F(x, v)                                    \\\n\t(BIT_CLEAR_LLTINI_PDATA_V1_8197F(x) | BIT_LLTINI_PDATA_V1_8197F(v))\n\n#define BIT_SHIFT_LLTINI_HDATA_V1_8197F 0\n#define BIT_MASK_LLTINI_HDATA_V1_8197F 0xfff\n#define BIT_LLTINI_HDATA_V1_8197F(x)                                           \\\n\t(((x) & BIT_MASK_LLTINI_HDATA_V1_8197F)                                \\\n\t << BIT_SHIFT_LLTINI_HDATA_V1_8197F)\n#define BITS_LLTINI_HDATA_V1_8197F                                             \\\n\t(BIT_MASK_LLTINI_HDATA_V1_8197F << BIT_SHIFT_LLTINI_HDATA_V1_8197F)\n#define BIT_CLEAR_LLTINI_HDATA_V1_8197F(x) ((x) & (~BITS_LLTINI_HDATA_V1_8197F))\n#define BIT_GET_LLTINI_HDATA_V1_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8197F) &                            \\\n\t BIT_MASK_LLTINI_HDATA_V1_8197F)\n#define BIT_SET_LLTINI_HDATA_V1_8197F(x, v)                                    \\\n\t(BIT_CLEAR_LLTINI_HDATA_V1_8197F(x) | BIT_LLTINI_HDATA_V1_8197F(v))\n\n/* 2 REG_LLT_INIT_ADDR_8197F */\n\n#define BIT_SHIFT_LLTINI_ADDR_V1_8197F 0\n#define BIT_MASK_LLTINI_ADDR_V1_8197F 0xfff\n#define BIT_LLTINI_ADDR_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_LLTINI_ADDR_V1_8197F)                                 \\\n\t << BIT_SHIFT_LLTINI_ADDR_V1_8197F)\n#define BITS_LLTINI_ADDR_V1_8197F                                              \\\n\t(BIT_MASK_LLTINI_ADDR_V1_8197F << BIT_SHIFT_LLTINI_ADDR_V1_8197F)\n#define BIT_CLEAR_LLTINI_ADDR_V1_8197F(x) ((x) & (~BITS_LLTINI_ADDR_V1_8197F))\n#define BIT_GET_LLTINI_ADDR_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8197F) &                             \\\n\t BIT_MASK_LLTINI_ADDR_V1_8197F)\n#define BIT_SET_LLTINI_ADDR_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_LLTINI_ADDR_V1_8197F(x) | BIT_LLTINI_ADDR_V1_8197F(v))\n\n/* 2 REG_BB_ACCESS_CTRL_8197F */\n\n#define BIT_SHIFT_BB_WRITE_READ_8197F 30\n#define BIT_MASK_BB_WRITE_READ_8197F 0x3\n#define BIT_BB_WRITE_READ_8197F(x)                                             \\\n\t(((x) & BIT_MASK_BB_WRITE_READ_8197F) << BIT_SHIFT_BB_WRITE_READ_8197F)\n#define BITS_BB_WRITE_READ_8197F                                               \\\n\t(BIT_MASK_BB_WRITE_READ_8197F << BIT_SHIFT_BB_WRITE_READ_8197F)\n#define BIT_CLEAR_BB_WRITE_READ_8197F(x) ((x) & (~BITS_BB_WRITE_READ_8197F))\n#define BIT_GET_BB_WRITE_READ_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_BB_WRITE_READ_8197F) & BIT_MASK_BB_WRITE_READ_8197F)\n#define BIT_SET_BB_WRITE_READ_8197F(x, v)                                      \\\n\t(BIT_CLEAR_BB_WRITE_READ_8197F(x) | BIT_BB_WRITE_READ_8197F(v))\n\n#define BIT_SHIFT_BB_WRITE_EN_V1_8197F 16\n#define BIT_MASK_BB_WRITE_EN_V1_8197F 0xf\n#define BIT_BB_WRITE_EN_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_BB_WRITE_EN_V1_8197F)                                 \\\n\t << BIT_SHIFT_BB_WRITE_EN_V1_8197F)\n#define BITS_BB_WRITE_EN_V1_8197F                                              \\\n\t(BIT_MASK_BB_WRITE_EN_V1_8197F << BIT_SHIFT_BB_WRITE_EN_V1_8197F)\n#define BIT_CLEAR_BB_WRITE_EN_V1_8197F(x) ((x) & (~BITS_BB_WRITE_EN_V1_8197F))\n#define BIT_GET_BB_WRITE_EN_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_BB_WRITE_EN_V1_8197F) &                             \\\n\t BIT_MASK_BB_WRITE_EN_V1_8197F)\n#define BIT_SET_BB_WRITE_EN_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_BB_WRITE_EN_V1_8197F(x) | BIT_BB_WRITE_EN_V1_8197F(v))\n\n#define BIT_SHIFT_BB_ADDR_V1_8197F 2\n#define BIT_MASK_BB_ADDR_V1_8197F 0xfff\n#define BIT_BB_ADDR_V1_8197F(x)                                                \\\n\t(((x) & BIT_MASK_BB_ADDR_V1_8197F) << BIT_SHIFT_BB_ADDR_V1_8197F)\n#define BITS_BB_ADDR_V1_8197F                                                  \\\n\t(BIT_MASK_BB_ADDR_V1_8197F << BIT_SHIFT_BB_ADDR_V1_8197F)\n#define BIT_CLEAR_BB_ADDR_V1_8197F(x) ((x) & (~BITS_BB_ADDR_V1_8197F))\n#define BIT_GET_BB_ADDR_V1_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_BB_ADDR_V1_8197F) & BIT_MASK_BB_ADDR_V1_8197F)\n#define BIT_SET_BB_ADDR_V1_8197F(x, v)                                         \\\n\t(BIT_CLEAR_BB_ADDR_V1_8197F(x) | BIT_BB_ADDR_V1_8197F(v))\n\n#define BIT_BB_ERRACC_8197F BIT(0)\n\n/* 2 REG_BB_ACCESS_DATA_8197F */\n\n#define BIT_SHIFT_BB_DATA_8197F 0\n#define BIT_MASK_BB_DATA_8197F 0xffffffffL\n#define BIT_BB_DATA_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_BB_DATA_8197F) << BIT_SHIFT_BB_DATA_8197F)\n#define BITS_BB_DATA_8197F (BIT_MASK_BB_DATA_8197F << BIT_SHIFT_BB_DATA_8197F)\n#define BIT_CLEAR_BB_DATA_8197F(x) ((x) & (~BITS_BB_DATA_8197F))\n#define BIT_GET_BB_DATA_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_BB_DATA_8197F) & BIT_MASK_BB_DATA_8197F)\n#define BIT_SET_BB_DATA_8197F(x, v)                                            \\\n\t(BIT_CLEAR_BB_DATA_8197F(x) | BIT_BB_DATA_8197F(v))\n\n/* 2 REG_HMEBOX_E0_8197F */\n\n#define BIT_SHIFT_HMEBOX_E0_8197F 0\n#define BIT_MASK_HMEBOX_E0_8197F 0xffffffffL\n#define BIT_HMEBOX_E0_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E0_8197F) << BIT_SHIFT_HMEBOX_E0_8197F)\n#define BITS_HMEBOX_E0_8197F                                                   \\\n\t(BIT_MASK_HMEBOX_E0_8197F << BIT_SHIFT_HMEBOX_E0_8197F)\n#define BIT_CLEAR_HMEBOX_E0_8197F(x) ((x) & (~BITS_HMEBOX_E0_8197F))\n#define BIT_GET_HMEBOX_E0_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E0_8197F) & BIT_MASK_HMEBOX_E0_8197F)\n#define BIT_SET_HMEBOX_E0_8197F(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E0_8197F(x) | BIT_HMEBOX_E0_8197F(v))\n\n/* 2 REG_HMEBOX_E1_8197F */\n\n#define BIT_SHIFT_HMEBOX_E1_8197F 0\n#define BIT_MASK_HMEBOX_E1_8197F 0xffffffffL\n#define BIT_HMEBOX_E1_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E1_8197F) << BIT_SHIFT_HMEBOX_E1_8197F)\n#define BITS_HMEBOX_E1_8197F                                                   \\\n\t(BIT_MASK_HMEBOX_E1_8197F << BIT_SHIFT_HMEBOX_E1_8197F)\n#define BIT_CLEAR_HMEBOX_E1_8197F(x) ((x) & (~BITS_HMEBOX_E1_8197F))\n#define BIT_GET_HMEBOX_E1_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E1_8197F) & BIT_MASK_HMEBOX_E1_8197F)\n#define BIT_SET_HMEBOX_E1_8197F(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E1_8197F(x) | BIT_HMEBOX_E1_8197F(v))\n\n/* 2 REG_HMEBOX_E2_8197F */\n\n#define BIT_SHIFT_HMEBOX_E2_8197F 0\n#define BIT_MASK_HMEBOX_E2_8197F 0xffffffffL\n#define BIT_HMEBOX_E2_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E2_8197F) << BIT_SHIFT_HMEBOX_E2_8197F)\n#define BITS_HMEBOX_E2_8197F                                                   \\\n\t(BIT_MASK_HMEBOX_E2_8197F << BIT_SHIFT_HMEBOX_E2_8197F)\n#define BIT_CLEAR_HMEBOX_E2_8197F(x) ((x) & (~BITS_HMEBOX_E2_8197F))\n#define BIT_GET_HMEBOX_E2_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E2_8197F) & BIT_MASK_HMEBOX_E2_8197F)\n#define BIT_SET_HMEBOX_E2_8197F(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E2_8197F(x) | BIT_HMEBOX_E2_8197F(v))\n\n/* 2 REG_HMEBOX_E3_8197F */\n\n#define BIT_SHIFT_HMEBOX_E3_8197F 0\n#define BIT_MASK_HMEBOX_E3_8197F 0xffffffffL\n#define BIT_HMEBOX_E3_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E3_8197F) << BIT_SHIFT_HMEBOX_E3_8197F)\n#define BITS_HMEBOX_E3_8197F                                                   \\\n\t(BIT_MASK_HMEBOX_E3_8197F << BIT_SHIFT_HMEBOX_E3_8197F)\n#define BIT_CLEAR_HMEBOX_E3_8197F(x) ((x) & (~BITS_HMEBOX_E3_8197F))\n#define BIT_GET_HMEBOX_E3_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E3_8197F) & BIT_MASK_HMEBOX_E3_8197F)\n#define BIT_SET_HMEBOX_E3_8197F(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E3_8197F(x) | BIT_HMEBOX_E3_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_CR_EXT_8197F */\n\n#define BIT_SHIFT_PHY_REQ_DELAY_8197F 24\n#define BIT_MASK_PHY_REQ_DELAY_8197F 0xf\n#define BIT_PHY_REQ_DELAY_8197F(x)                                             \\\n\t(((x) & BIT_MASK_PHY_REQ_DELAY_8197F) << BIT_SHIFT_PHY_REQ_DELAY_8197F)\n#define BITS_PHY_REQ_DELAY_8197F                                               \\\n\t(BIT_MASK_PHY_REQ_DELAY_8197F << BIT_SHIFT_PHY_REQ_DELAY_8197F)\n#define BIT_CLEAR_PHY_REQ_DELAY_8197F(x) ((x) & (~BITS_PHY_REQ_DELAY_8197F))\n#define BIT_GET_PHY_REQ_DELAY_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_PHY_REQ_DELAY_8197F) & BIT_MASK_PHY_REQ_DELAY_8197F)\n#define BIT_SET_PHY_REQ_DELAY_8197F(x, v)                                      \\\n\t(BIT_CLEAR_PHY_REQ_DELAY_8197F(x) | BIT_PHY_REQ_DELAY_8197F(v))\n\n#define BIT_SPD_DOWN_8197F BIT(16)\n\n#define BIT_SHIFT_NETYPE4_8197F 4\n#define BIT_MASK_NETYPE4_8197F 0x3\n#define BIT_NETYPE4_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE4_8197F) << BIT_SHIFT_NETYPE4_8197F)\n#define BITS_NETYPE4_8197F (BIT_MASK_NETYPE4_8197F << BIT_SHIFT_NETYPE4_8197F)\n#define BIT_CLEAR_NETYPE4_8197F(x) ((x) & (~BITS_NETYPE4_8197F))\n#define BIT_GET_NETYPE4_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE4_8197F) & BIT_MASK_NETYPE4_8197F)\n#define BIT_SET_NETYPE4_8197F(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE4_8197F(x) | BIT_NETYPE4_8197F(v))\n\n#define BIT_SHIFT_NETYPE3_8197F 2\n#define BIT_MASK_NETYPE3_8197F 0x3\n#define BIT_NETYPE3_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE3_8197F) << BIT_SHIFT_NETYPE3_8197F)\n#define BITS_NETYPE3_8197F (BIT_MASK_NETYPE3_8197F << BIT_SHIFT_NETYPE3_8197F)\n#define BIT_CLEAR_NETYPE3_8197F(x) ((x) & (~BITS_NETYPE3_8197F))\n#define BIT_GET_NETYPE3_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE3_8197F) & BIT_MASK_NETYPE3_8197F)\n#define BIT_SET_NETYPE3_8197F(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE3_8197F(x) | BIT_NETYPE3_8197F(v))\n\n#define BIT_SHIFT_NETYPE2_8197F 0\n#define BIT_MASK_NETYPE2_8197F 0x3\n#define BIT_NETYPE2_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE2_8197F) << BIT_SHIFT_NETYPE2_8197F)\n#define BITS_NETYPE2_8197F (BIT_MASK_NETYPE2_8197F << BIT_SHIFT_NETYPE2_8197F)\n#define BIT_CLEAR_NETYPE2_8197F(x) ((x) & (~BITS_NETYPE2_8197F))\n#define BIT_GET_NETYPE2_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE2_8197F) & BIT_MASK_NETYPE2_8197F)\n#define BIT_SET_NETYPE2_8197F(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE2_8197F(x) | BIT_NETYPE2_8197F(v))\n\n/* 2 REG_FWFF_8197F */\n\n#define BIT_SHIFT_PKTNUM_TH_8197F 24\n#define BIT_MASK_PKTNUM_TH_8197F 0xff\n#define BIT_PKTNUM_TH_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_PKTNUM_TH_8197F) << BIT_SHIFT_PKTNUM_TH_8197F)\n#define BITS_PKTNUM_TH_8197F                                                   \\\n\t(BIT_MASK_PKTNUM_TH_8197F << BIT_SHIFT_PKTNUM_TH_8197F)\n#define BIT_CLEAR_PKTNUM_TH_8197F(x) ((x) & (~BITS_PKTNUM_TH_8197F))\n#define BIT_GET_PKTNUM_TH_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_PKTNUM_TH_8197F) & BIT_MASK_PKTNUM_TH_8197F)\n#define BIT_SET_PKTNUM_TH_8197F(x, v)                                          \\\n\t(BIT_CLEAR_PKTNUM_TH_8197F(x) | BIT_PKTNUM_TH_8197F(v))\n\n#define BIT_SHIFT_TIMER_TH_8197F 16\n#define BIT_MASK_TIMER_TH_8197F 0xff\n#define BIT_TIMER_TH_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_TIMER_TH_8197F) << BIT_SHIFT_TIMER_TH_8197F)\n#define BITS_TIMER_TH_8197F                                                    \\\n\t(BIT_MASK_TIMER_TH_8197F << BIT_SHIFT_TIMER_TH_8197F)\n#define BIT_CLEAR_TIMER_TH_8197F(x) ((x) & (~BITS_TIMER_TH_8197F))\n#define BIT_GET_TIMER_TH_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_TIMER_TH_8197F) & BIT_MASK_TIMER_TH_8197F)\n#define BIT_SET_TIMER_TH_8197F(x, v)                                           \\\n\t(BIT_CLEAR_TIMER_TH_8197F(x) | BIT_TIMER_TH_8197F(v))\n\n#define BIT_SHIFT_RXPKT1ENADDR_8197F 0\n#define BIT_MASK_RXPKT1ENADDR_8197F 0xffff\n#define BIT_RXPKT1ENADDR_8197F(x)                                              \\\n\t(((x) & BIT_MASK_RXPKT1ENADDR_8197F) << BIT_SHIFT_RXPKT1ENADDR_8197F)\n#define BITS_RXPKT1ENADDR_8197F                                                \\\n\t(BIT_MASK_RXPKT1ENADDR_8197F << BIT_SHIFT_RXPKT1ENADDR_8197F)\n#define BIT_CLEAR_RXPKT1ENADDR_8197F(x) ((x) & (~BITS_RXPKT1ENADDR_8197F))\n#define BIT_GET_RXPKT1ENADDR_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXPKT1ENADDR_8197F) & BIT_MASK_RXPKT1ENADDR_8197F)\n#define BIT_SET_RXPKT1ENADDR_8197F(x, v)                                       \\\n\t(BIT_CLEAR_RXPKT1ENADDR_8197F(x) | BIT_RXPKT1ENADDR_8197F(v))\n\n/* 2 REG_RXFF_PTR_V1_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n#define BIT_SHIFT_RXFF0_RDPTR_V2_8197F 0\n#define BIT_MASK_RXFF0_RDPTR_V2_8197F 0x3ffff\n#define BIT_RXFF0_RDPTR_V2_8197F(x)                                            \\\n\t(((x) & BIT_MASK_RXFF0_RDPTR_V2_8197F)                                 \\\n\t << BIT_SHIFT_RXFF0_RDPTR_V2_8197F)\n#define BITS_RXFF0_RDPTR_V2_8197F                                              \\\n\t(BIT_MASK_RXFF0_RDPTR_V2_8197F << BIT_SHIFT_RXFF0_RDPTR_V2_8197F)\n#define BIT_CLEAR_RXFF0_RDPTR_V2_8197F(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8197F))\n#define BIT_GET_RXFF0_RDPTR_V2_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8197F) &                             \\\n\t BIT_MASK_RXFF0_RDPTR_V2_8197F)\n#define BIT_SET_RXFF0_RDPTR_V2_8197F(x, v)                                     \\\n\t(BIT_CLEAR_RXFF0_RDPTR_V2_8197F(x) | BIT_RXFF0_RDPTR_V2_8197F(v))\n\n/* 2 REG_RXFF_WTR_V1_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n#define BIT_SHIFT_RXFF0_WTPTR_V2_8197F 0\n#define BIT_MASK_RXFF0_WTPTR_V2_8197F 0x3ffff\n#define BIT_RXFF0_WTPTR_V2_8197F(x)                                            \\\n\t(((x) & BIT_MASK_RXFF0_WTPTR_V2_8197F)                                 \\\n\t << BIT_SHIFT_RXFF0_WTPTR_V2_8197F)\n#define BITS_RXFF0_WTPTR_V2_8197F                                              \\\n\t(BIT_MASK_RXFF0_WTPTR_V2_8197F << BIT_SHIFT_RXFF0_WTPTR_V2_8197F)\n#define BIT_CLEAR_RXFF0_WTPTR_V2_8197F(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8197F))\n#define BIT_GET_RXFF0_WTPTR_V2_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8197F) &                             \\\n\t BIT_MASK_RXFF0_WTPTR_V2_8197F)\n#define BIT_SET_RXFF0_WTPTR_V2_8197F(x, v)                                     \\\n\t(BIT_CLEAR_RXFF0_WTPTR_V2_8197F(x) | BIT_RXFF0_WTPTR_V2_8197F(v))\n\n/* 2 REG_FE2IMR_8197F */\n#define BIT_FS_TXSC_DESC_DONE_INT_EN_8197F BIT(28)\n#define BIT_FS_TXSC_BKDONE_INT_EN_8197F BIT(27)\n#define BIT_FS_TXSC_BEDONE_INT_EN_8197F BIT(26)\n#define BIT_FS_TXSC_VIDONE_INT_EN_8197F BIT(25)\n#define BIT_FS_TXSC_VODONE_INT_EN_8197F BIT(24)\n#define BIT_FS_ATIM_MB7_INT_EN_8197F BIT(23)\n#define BIT_FS_ATIM_MB6_INT_EN_8197F BIT(22)\n#define BIT_FS_ATIM_MB5_INT_EN_8197F BIT(21)\n#define BIT_FS_ATIM_MB4_INT_EN_8197F BIT(20)\n#define BIT_FS_ATIM_MB3_INT_EN_8197F BIT(19)\n#define BIT_FS_ATIM_MB2_INT_EN_8197F BIT(18)\n#define BIT_FS_ATIM_MB1_INT_EN_8197F BIT(17)\n#define BIT_FS_ATIM_MB0_INT_EN_8197F BIT(16)\n#define BIT_FS_TBTT4INT_EN_8197F BIT(11)\n#define BIT_FS_TBTT3INT_EN_8197F BIT(10)\n#define BIT_FS_TBTT2INT_EN_8197F BIT(9)\n#define BIT_FS_TBTT1INT_EN_8197F BIT(8)\n#define BIT_FS_TBTT0_MB7INT_EN_8197F BIT(7)\n#define BIT_FS_TBTT0_MB6INT_EN_8197F BIT(6)\n#define BIT_FS_TBTT0_MB5INT_EN_8197F BIT(5)\n#define BIT_FS_TBTT0_MB4INT_EN_8197F BIT(4)\n#define BIT_FS_TBTT0_MB3INT_EN_8197F BIT(3)\n#define BIT_FS_TBTT0_MB2INT_EN_8197F BIT(2)\n#define BIT_FS_TBTT0_MB1INT_EN_8197F BIT(1)\n#define BIT_FS_TBTT0_INT_EN_8197F BIT(0)\n\n/* 2 REG_FE2ISR_8197F */\n#define BIT_FS_TXSC_DESC_DONE_INT_8197F BIT(28)\n#define BIT_FS_TXSC_BKDONE_INT_8197F BIT(27)\n#define BIT_FS_TXSC_BEDONE_INT_8197F BIT(26)\n#define BIT_FS_TXSC_VIDONE_INT_8197F BIT(25)\n#define BIT_FS_TXSC_VODONE_INT_8197F BIT(24)\n#define BIT_FS_ATIM_MB7_INT_8197F BIT(23)\n#define BIT_FS_ATIM_MB6_INT_8197F BIT(22)\n#define BIT_FS_ATIM_MB5_INT_8197F BIT(21)\n#define BIT_FS_ATIM_MB4_INT_8197F BIT(20)\n#define BIT_FS_ATIM_MB3_INT_8197F BIT(19)\n#define BIT_FS_ATIM_MB2_INT_8197F BIT(18)\n#define BIT_FS_ATIM_MB1_INT_8197F BIT(17)\n#define BIT_FS_ATIM_MB0_INT_8197F BIT(16)\n#define BIT_FS_TBTT4INT_8197F BIT(11)\n#define BIT_FS_TBTT3INT_8197F BIT(10)\n#define BIT_FS_TBTT2INT_8197F BIT(9)\n#define BIT_FS_TBTT1INT_8197F BIT(8)\n#define BIT_FS_TBTT0_MB7INT_8197F BIT(7)\n#define BIT_FS_TBTT0_MB6INT_8197F BIT(6)\n#define BIT_FS_TBTT0_MB5INT_8197F BIT(5)\n#define BIT_FS_TBTT0_MB4INT_8197F BIT(4)\n#define BIT_FS_TBTT0_MB3INT_8197F BIT(3)\n#define BIT_FS_TBTT0_MB2INT_8197F BIT(2)\n#define BIT_FS_TBTT0_MB1INT_8197F BIT(1)\n#define BIT_FS_TBTT0_INT_8197F BIT(0)\n\n/* 2 REG_FE3IMR_8197F */\n#define BIT_FS_BCNELY4_AGGR_INT_EN_8197F BIT(31)\n#define BIT_FS_BCNELY3_AGGR_INT_EN_8197F BIT(30)\n#define BIT_FS_BCNELY2_AGGR_INT_EN_8197F BIT(29)\n#define BIT_FS_BCNELY1_AGGR_INT_EN_8197F BIT(28)\n#define BIT_FS_BCNDMA4_INT_EN_8197F BIT(27)\n#define BIT_FS_BCNDMA3_INT_EN_8197F BIT(26)\n#define BIT_FS_BCNDMA2_INT_EN_8197F BIT(25)\n#define BIT_FS_BCNDMA1_INT_EN_8197F BIT(24)\n#define BIT_FS_BCNDMA0_MB7_INT_EN_8197F BIT(23)\n#define BIT_FS_BCNDMA0_MB6_INT_EN_8197F BIT(22)\n#define BIT_FS_BCNDMA0_MB5_INT_EN_8197F BIT(21)\n#define BIT_FS_BCNDMA0_MB4_INT_EN_8197F BIT(20)\n#define BIT_FS_BCNDMA0_MB3_INT_EN_8197F BIT(19)\n#define BIT_FS_BCNDMA0_MB2_INT_EN_8197F BIT(18)\n#define BIT_FS_BCNDMA0_MB1_INT_EN_8197F BIT(17)\n#define BIT_FS_BCNDMA0_INT_EN_8197F BIT(16)\n#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8197F BIT(15)\n#define BIT_FS_BCNERLY4_INT_EN_8197F BIT(11)\n#define BIT_FS_BCNERLY3_INT_EN_8197F BIT(10)\n#define BIT_FS_BCNERLY2_INT_EN_8197F BIT(9)\n#define BIT_FS_BCNERLY1_INT_EN_8197F BIT(8)\n#define BIT_FS_BCNERLY0_MB7INT_EN_8197F BIT(7)\n#define BIT_FS_BCNERLY0_MB6INT_EN_8197F BIT(6)\n#define BIT_FS_BCNERLY0_MB5INT_EN_8197F BIT(5)\n#define BIT_FS_BCNERLY0_MB4INT_EN_8197F BIT(4)\n#define BIT_FS_BCNERLY0_MB3INT_EN_8197F BIT(3)\n#define BIT_FS_BCNERLY0_MB2INT_EN_8197F BIT(2)\n#define BIT_FS_BCNERLY0_MB1INT_EN_8197F BIT(1)\n#define BIT_FS_BCNERLY0_INT_EN_8197F BIT(0)\n\n/* 2 REG_FE3ISR_8197F */\n#define BIT_FS_BCNELY4_AGGR_INT_8197F BIT(31)\n#define BIT_FS_BCNELY3_AGGR_INT_8197F BIT(30)\n#define BIT_FS_BCNELY2_AGGR_INT_8197F BIT(29)\n#define BIT_FS_BCNELY1_AGGR_INT_8197F BIT(28)\n#define BIT_FS_BCNDMA4_INT_8197F BIT(27)\n#define BIT_FS_BCNDMA3_INT_8197F BIT(26)\n#define BIT_FS_BCNDMA2_INT_8197F BIT(25)\n#define BIT_FS_BCNDMA1_INT_8197F BIT(24)\n#define BIT_FS_BCNDMA0_MB7_INT_8197F BIT(23)\n#define BIT_FS_BCNDMA0_MB6_INT_8197F BIT(22)\n#define BIT_FS_BCNDMA0_MB5_INT_8197F BIT(21)\n#define BIT_FS_BCNDMA0_MB4_INT_8197F BIT(20)\n#define BIT_FS_BCNDMA0_MB3_INT_8197F BIT(19)\n#define BIT_FS_BCNDMA0_MB2_INT_8197F BIT(18)\n#define BIT_FS_BCNDMA0_MB1_INT_8197F BIT(17)\n#define BIT_FS_BCNDMA0_INT_8197F BIT(16)\n#define BIT_FS_MTI_BCNIVLEAR_INT_8197F BIT(15)\n#define BIT_FS_BCNERLY4_INT_8197F BIT(11)\n#define BIT_FS_BCNERLY3_INT_8197F BIT(10)\n#define BIT_FS_BCNERLY2_INT_8197F BIT(9)\n#define BIT_FS_BCNERLY1_INT_8197F BIT(8)\n#define BIT_FS_BCNERLY0_MB7INT_8197F BIT(7)\n#define BIT_FS_BCNERLY0_MB6INT_8197F BIT(6)\n#define BIT_FS_BCNERLY0_MB5INT_8197F BIT(5)\n#define BIT_FS_BCNERLY0_MB4INT_8197F BIT(4)\n#define BIT_FS_BCNERLY0_MB3INT_8197F BIT(3)\n#define BIT_FS_BCNERLY0_MB2INT_8197F BIT(2)\n#define BIT_FS_BCNERLY0_MB1INT_8197F BIT(1)\n#define BIT_FS_BCNERLY0_INT_8197F BIT(0)\n\n/* 2 REG_FE4IMR_8197F */\n#define BIT_PORT4_PKTIN_INT_EN_8197F BIT(19)\n#define BIT_PORT3_PKTIN_INT_EN_8197F BIT(18)\n#define BIT_PORT2_PKTIN_INT_EN_8197F BIT(17)\n#define BIT_PORT1_PKTIN_INT_EN_8197F BIT(16)\n#define BIT_PORT4_RXUCMD0_OK_INT_EN_8197F BIT(15)\n#define BIT_PORT4_RXUCMD1_OK_INT_EN_8197F BIT(14)\n#define BIT_PORT4_RXBCMD0_OK_INT_EN_8197F BIT(13)\n#define BIT_PORT4_RXBCMD1_OK_INT_EN_8197F BIT(12)\n#define BIT_PORT3_RXUCMD0_OK_INT_EN_8197F BIT(11)\n#define BIT_PORT3_RXUCMD1_OK_INT_EN_8197F BIT(10)\n#define BIT_PORT3_RXBCMD0_OK_INT_EN_8197F BIT(9)\n#define BIT_PORT3_RXBCMD1_OK_INT_EN_8197F BIT(8)\n#define BIT_PORT2_RXUCMD0_OK_INT_EN_8197F BIT(7)\n#define BIT_PORT2_RXUCMD1_OK_INT_EN_8197F BIT(6)\n#define BIT_PORT2_RXBCMD0_OK_INT_EN_8197F BIT(5)\n#define BIT_PORT2_RXBCMD1_OK_INT_EN_8197F BIT(4)\n#define BIT_PORT1_RXUCMD0_OK_INT_EN_8197F BIT(3)\n#define BIT_PORT1_RXUCMD1_OK_INT_EN_8197F BIT(2)\n#define BIT_PORT1_RXBCMD0_OK_INT_EN_8197F BIT(1)\n#define BIT_PORT1_RXBCMD1_OK_INT_EN_8197F BIT(0)\n\n/* 2 REG_FE4ISR_8197F */\n#define BIT_PORT4_PKTIN_INT_8197F BIT(19)\n#define BIT_PORT3_PKTIN_INT_8197F BIT(18)\n#define BIT_PORT2_PKTIN_INT_8197F BIT(17)\n#define BIT_PORT1_PKTIN_INT_8197F BIT(16)\n#define BIT_PORT4_RXUCMD0_OK_INT_8197F BIT(15)\n#define BIT_PORT4_RXUCMD1_OK_INT_8197F BIT(14)\n#define BIT_PORT4_RXBCMD0_OK_INT_8197F BIT(13)\n#define BIT_PORT4_RXBCMD1_OK_INT_8197F BIT(12)\n#define BIT_PORT3_RXUCMD0_OK_INT_8197F BIT(11)\n#define BIT_PORT3_RXUCMD1_OK_INT_8197F BIT(10)\n#define BIT_PORT3_RXBCMD0_OK_INT_8197F BIT(9)\n#define BIT_PORT3_RXBCMD1_OK_INT_8197F BIT(8)\n#define BIT_PORT2_RXUCMD0_OK_INT_8197F BIT(7)\n#define BIT_PORT2_RXUCMD1_OK_INT_8197F BIT(6)\n#define BIT_PORT2_RXBCMD0_OK_INT_8197F BIT(5)\n#define BIT_PORT2_RXBCMD1_OK_INT_8197F BIT(4)\n#define BIT_PORT1_RXUCMD0_OK_INT_8197F BIT(3)\n#define BIT_PORT1_RXUCMD1_OK_INT_8197F BIT(2)\n#define BIT_PORT1_RXBCMD0_OK_INT_8197F BIT(1)\n#define BIT_PORT1_RXBCMD1_OK_INT_8197F BIT(0)\n\n/* 2 REG_FT1IMR_8197F */\n#define BIT__FT2ISR__IND_MSK_8197F BIT(30)\n#define BIT_FTM_PTT_INT_EN_8197F BIT(29)\n#define BIT_RXFTMREQ_INT_EN_8197F BIT(28)\n#define BIT_RXFTM_INT_EN_8197F BIT(27)\n#define BIT_TXFTM_INT_EN_8197F BIT(26)\n#define BIT_FS_H2C_CMD_OK_INT_EN_8197F BIT(25)\n#define BIT_FS_H2C_CMD_FULL_INT_EN_8197F BIT(24)\n#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8197F BIT(23)\n#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8197F BIT(22)\n#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8197F BIT(21)\n#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8197F BIT(20)\n#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8197F BIT(19)\n#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8197F BIT(18)\n#define BIT_FS_CTWEND2_INT_EN_8197F BIT(17)\n#define BIT_FS_CTWEND1_INT_EN_8197F BIT(16)\n#define BIT_FS_CTWEND0_INT_EN_8197F BIT(15)\n#define BIT_FS_TX_NULL1_INT_EN_8197F BIT(14)\n#define BIT_FS_TX_NULL0_INT_EN_8197F BIT(13)\n#define BIT_FS_TSF_BIT32_TOGGLE_EN_8197F BIT(12)\n#define BIT_FS_P2P_RFON2_INT_EN_8197F BIT(11)\n#define BIT_FS_P2P_RFOFF2_INT_EN_8197F BIT(10)\n#define BIT_FS_P2P_RFON1_INT_EN_8197F BIT(9)\n#define BIT_FS_P2P_RFOFF1_INT_EN_8197F BIT(8)\n#define BIT_FS_P2P_RFON0_INT_EN_8197F BIT(7)\n#define BIT_FS_P2P_RFOFF0_INT_EN_8197F BIT(6)\n#define BIT_FS_RX_UAPSDMD1_EN_8197F BIT(5)\n#define BIT_FS_RX_UAPSDMD0_EN_8197F BIT(4)\n#define BIT_FS_TRIGGER_PKT_EN_8197F BIT(3)\n#define BIT_FS_EOSP_INT_EN_8197F BIT(2)\n#define BIT_FS_RPWM2_INT_EN_8197F BIT(1)\n#define BIT_FS_RPWM_INT_EN_8197F BIT(0)\n\n/* 2 REG_FT1ISR_8197F */\n#define BIT__FT2ISR__IND_INT_8197F BIT(30)\n#define BIT_FTM_PTT_INT_8197F BIT(29)\n#define BIT_RXFTMREQ_INT_8197F BIT(28)\n#define BIT_RXFTM_INT_8197F BIT(27)\n#define BIT_TXFTM_INT_8197F BIT(26)\n#define BIT_FS_H2C_CMD_OK_INT_8197F BIT(25)\n#define BIT_FS_H2C_CMD_FULL_INT_8197F BIT(24)\n#define BIT_FS_MACID_PWRCHANGE5_INT_8197F BIT(23)\n#define BIT_FS_MACID_PWRCHANGE4_INT_8197F BIT(22)\n#define BIT_FS_MACID_PWRCHANGE3_INT_8197F BIT(21)\n#define BIT_FS_MACID_PWRCHANGE2_INT_8197F BIT(20)\n#define BIT_FS_MACID_PWRCHANGE1_INT_8197F BIT(19)\n#define BIT_FS_MACID_PWRCHANGE0_INT_8197F BIT(18)\n#define BIT_FS_CTWEND2_INT_8197F BIT(17)\n#define BIT_FS_CTWEND1_INT_8197F BIT(16)\n#define BIT_FS_CTWEND0_INT_8197F BIT(15)\n#define BIT_FS_TX_NULL1_INT_8197F BIT(14)\n#define BIT_FS_TX_NULL0_INT_8197F BIT(13)\n#define BIT_FS_TSF_BIT32_TOGGLE_INT_8197F BIT(12)\n#define BIT_FS_P2P_RFON2_INT_8197F BIT(11)\n#define BIT_FS_P2P_RFOFF2_INT_8197F BIT(10)\n#define BIT_FS_P2P_RFON1_INT_8197F BIT(9)\n#define BIT_FS_P2P_RFOFF1_INT_8197F BIT(8)\n#define BIT_FS_P2P_RFON0_INT_8197F BIT(7)\n#define BIT_FS_P2P_RFOFF0_INT_8197F BIT(6)\n#define BIT_FS_RX_UAPSDMD1_INT_8197F BIT(5)\n#define BIT_FS_RX_UAPSDMD0_INT_8197F BIT(4)\n#define BIT_FS_TRIGGER_PKT_INT_8197F BIT(3)\n#define BIT_FS_EOSP_INT_8197F BIT(2)\n#define BIT_FS_RPWM2_INT_8197F BIT(1)\n#define BIT_FS_RPWM_INT_8197F BIT(0)\n\n/* 2 REG_SPWR0_8197F */\n\n#define BIT_SHIFT_MID_31TO0_8197F 0\n#define BIT_MASK_MID_31TO0_8197F 0xffffffffL\n#define BIT_MID_31TO0_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_MID_31TO0_8197F) << BIT_SHIFT_MID_31TO0_8197F)\n#define BITS_MID_31TO0_8197F                                                   \\\n\t(BIT_MASK_MID_31TO0_8197F << BIT_SHIFT_MID_31TO0_8197F)\n#define BIT_CLEAR_MID_31TO0_8197F(x) ((x) & (~BITS_MID_31TO0_8197F))\n#define BIT_GET_MID_31TO0_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_MID_31TO0_8197F) & BIT_MASK_MID_31TO0_8197F)\n#define BIT_SET_MID_31TO0_8197F(x, v)                                          \\\n\t(BIT_CLEAR_MID_31TO0_8197F(x) | BIT_MID_31TO0_8197F(v))\n\n/* 2 REG_SPWR1_8197F */\n\n#define BIT_SHIFT_MID_63TO32_8197F 0\n#define BIT_MASK_MID_63TO32_8197F 0xffffffffL\n#define BIT_MID_63TO32_8197F(x)                                                \\\n\t(((x) & BIT_MASK_MID_63TO32_8197F) << BIT_SHIFT_MID_63TO32_8197F)\n#define BITS_MID_63TO32_8197F                                                  \\\n\t(BIT_MASK_MID_63TO32_8197F << BIT_SHIFT_MID_63TO32_8197F)\n#define BIT_CLEAR_MID_63TO32_8197F(x) ((x) & (~BITS_MID_63TO32_8197F))\n#define BIT_GET_MID_63TO32_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_MID_63TO32_8197F) & BIT_MASK_MID_63TO32_8197F)\n#define BIT_SET_MID_63TO32_8197F(x, v)                                         \\\n\t(BIT_CLEAR_MID_63TO32_8197F(x) | BIT_MID_63TO32_8197F(v))\n\n/* 2 REG_SPWR2_8197F */\n\n#define BIT_SHIFT_MID_95O64_8197F 0\n#define BIT_MASK_MID_95O64_8197F 0xffffffffL\n#define BIT_MID_95O64_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_MID_95O64_8197F) << BIT_SHIFT_MID_95O64_8197F)\n#define BITS_MID_95O64_8197F                                                   \\\n\t(BIT_MASK_MID_95O64_8197F << BIT_SHIFT_MID_95O64_8197F)\n#define BIT_CLEAR_MID_95O64_8197F(x) ((x) & (~BITS_MID_95O64_8197F))\n#define BIT_GET_MID_95O64_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_MID_95O64_8197F) & BIT_MASK_MID_95O64_8197F)\n#define BIT_SET_MID_95O64_8197F(x, v)                                          \\\n\t(BIT_CLEAR_MID_95O64_8197F(x) | BIT_MID_95O64_8197F(v))\n\n/* 2 REG_SPWR3_8197F */\n\n#define BIT_SHIFT_MID_127TO96_8197F 0\n#define BIT_MASK_MID_127TO96_8197F 0xffffffffL\n#define BIT_MID_127TO96_8197F(x)                                               \\\n\t(((x) & BIT_MASK_MID_127TO96_8197F) << BIT_SHIFT_MID_127TO96_8197F)\n#define BITS_MID_127TO96_8197F                                                 \\\n\t(BIT_MASK_MID_127TO96_8197F << BIT_SHIFT_MID_127TO96_8197F)\n#define BIT_CLEAR_MID_127TO96_8197F(x) ((x) & (~BITS_MID_127TO96_8197F))\n#define BIT_GET_MID_127TO96_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_MID_127TO96_8197F) & BIT_MASK_MID_127TO96_8197F)\n#define BIT_SET_MID_127TO96_8197F(x, v)                                        \\\n\t(BIT_CLEAR_MID_127TO96_8197F(x) | BIT_MID_127TO96_8197F(v))\n\n/* 2 REG_POWSEQ_8197F */\n\n#define BIT_SHIFT_SEQNUM_MID_8197F 16\n#define BIT_MASK_SEQNUM_MID_8197F 0xffff\n#define BIT_SEQNUM_MID_8197F(x)                                                \\\n\t(((x) & BIT_MASK_SEQNUM_MID_8197F) << BIT_SHIFT_SEQNUM_MID_8197F)\n#define BITS_SEQNUM_MID_8197F                                                  \\\n\t(BIT_MASK_SEQNUM_MID_8197F << BIT_SHIFT_SEQNUM_MID_8197F)\n#define BIT_CLEAR_SEQNUM_MID_8197F(x) ((x) & (~BITS_SEQNUM_MID_8197F))\n#define BIT_GET_SEQNUM_MID_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_SEQNUM_MID_8197F) & BIT_MASK_SEQNUM_MID_8197F)\n#define BIT_SET_SEQNUM_MID_8197F(x, v)                                         \\\n\t(BIT_CLEAR_SEQNUM_MID_8197F(x) | BIT_SEQNUM_MID_8197F(v))\n\n#define BIT_SHIFT_REF_MID_8197F 0\n#define BIT_MASK_REF_MID_8197F 0x7f\n#define BIT_REF_MID_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_REF_MID_8197F) << BIT_SHIFT_REF_MID_8197F)\n#define BITS_REF_MID_8197F (BIT_MASK_REF_MID_8197F << BIT_SHIFT_REF_MID_8197F)\n#define BIT_CLEAR_REF_MID_8197F(x) ((x) & (~BITS_REF_MID_8197F))\n#define BIT_GET_REF_MID_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_REF_MID_8197F) & BIT_MASK_REF_MID_8197F)\n#define BIT_SET_REF_MID_8197F(x, v)                                            \\\n\t(BIT_CLEAR_REF_MID_8197F(x) | BIT_REF_MID_8197F(v))\n\n/* 2 REG_TC7_CTRL_V1_8197F */\n#define BIT_TC7INT_EN_8197F BIT(26)\n#define BIT_TC7MODE_8197F BIT(25)\n#define BIT_TC7EN_8197F BIT(24)\n\n#define BIT_SHIFT_TC7DATA_8197F 0\n#define BIT_MASK_TC7DATA_8197F 0xffffff\n#define BIT_TC7DATA_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_TC7DATA_8197F) << BIT_SHIFT_TC7DATA_8197F)\n#define BITS_TC7DATA_8197F (BIT_MASK_TC7DATA_8197F << BIT_SHIFT_TC7DATA_8197F)\n#define BIT_CLEAR_TC7DATA_8197F(x) ((x) & (~BITS_TC7DATA_8197F))\n#define BIT_GET_TC7DATA_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC7DATA_8197F) & BIT_MASK_TC7DATA_8197F)\n#define BIT_SET_TC7DATA_8197F(x, v)                                            \\\n\t(BIT_CLEAR_TC7DATA_8197F(x) | BIT_TC7DATA_8197F(v))\n\n/* 2 REG_TC8_CTRL_V1_8197F */\n#define BIT_TC8INT_EN_8197F BIT(26)\n#define BIT_TC8MODE_8197F BIT(25)\n#define BIT_TC8EN_8197F BIT(24)\n\n#define BIT_SHIFT_TC8DATA_8197F 0\n#define BIT_MASK_TC8DATA_8197F 0xffffff\n#define BIT_TC8DATA_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_TC8DATA_8197F) << BIT_SHIFT_TC8DATA_8197F)\n#define BITS_TC8DATA_8197F (BIT_MASK_TC8DATA_8197F << BIT_SHIFT_TC8DATA_8197F)\n#define BIT_CLEAR_TC8DATA_8197F(x) ((x) & (~BITS_TC8DATA_8197F))\n#define BIT_GET_TC8DATA_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC8DATA_8197F) & BIT_MASK_TC8DATA_8197F)\n#define BIT_SET_TC8DATA_8197F(x, v)                                            \\\n\t(BIT_CLEAR_TC8DATA_8197F(x) | BIT_TC8DATA_8197F(v))\n\n/* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3_8197F */\n\n/* 2 REG_RXBCN_TBTT_INTERVAL_PORT4_8197F */\n\n/* 2 REG_EXT_QUEUE_REG_8197F */\n\n#define BIT_SHIFT_PCIE_PRIORITY_SEL_8197F 0\n#define BIT_MASK_PCIE_PRIORITY_SEL_8197F 0x3\n#define BIT_PCIE_PRIORITY_SEL_8197F(x)                                         \\\n\t(((x) & BIT_MASK_PCIE_PRIORITY_SEL_8197F)                              \\\n\t << BIT_SHIFT_PCIE_PRIORITY_SEL_8197F)\n#define BITS_PCIE_PRIORITY_SEL_8197F                                           \\\n\t(BIT_MASK_PCIE_PRIORITY_SEL_8197F << BIT_SHIFT_PCIE_PRIORITY_SEL_8197F)\n#define BIT_CLEAR_PCIE_PRIORITY_SEL_8197F(x)                                   \\\n\t((x) & (~BITS_PCIE_PRIORITY_SEL_8197F))\n#define BIT_GET_PCIE_PRIORITY_SEL_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) &                          \\\n\t BIT_MASK_PCIE_PRIORITY_SEL_8197F)\n#define BIT_SET_PCIE_PRIORITY_SEL_8197F(x, v)                                  \\\n\t(BIT_CLEAR_PCIE_PRIORITY_SEL_8197F(x) | BIT_PCIE_PRIORITY_SEL_8197F(v))\n\n/* 2 REG_COUNTER_CONTROL_8197F */\n\n#define BIT_SHIFT_COUNTER_BASE_8197F 16\n#define BIT_MASK_COUNTER_BASE_8197F 0x1fff\n#define BIT_COUNTER_BASE_8197F(x)                                              \\\n\t(((x) & BIT_MASK_COUNTER_BASE_8197F) << BIT_SHIFT_COUNTER_BASE_8197F)\n#define BITS_COUNTER_BASE_8197F                                                \\\n\t(BIT_MASK_COUNTER_BASE_8197F << BIT_SHIFT_COUNTER_BASE_8197F)\n#define BIT_CLEAR_COUNTER_BASE_8197F(x) ((x) & (~BITS_COUNTER_BASE_8197F))\n#define BIT_GET_COUNTER_BASE_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_COUNTER_BASE_8197F) & BIT_MASK_COUNTER_BASE_8197F)\n#define BIT_SET_COUNTER_BASE_8197F(x, v)                                       \\\n\t(BIT_CLEAR_COUNTER_BASE_8197F(x) | BIT_COUNTER_BASE_8197F(v))\n\n#define BIT_EN_RTS_REQ_8197F BIT(9)\n#define BIT_EN_EDCA_REQ_8197F BIT(8)\n#define BIT_EN_PTCL_REQ_8197F BIT(7)\n#define BIT_EN_SCH_REQ_8197F BIT(6)\n#define BIT_EN_USB_CNT_8197F BIT(5)\n#define BIT_EN_PCIE_CNT_8197F BIT(4)\n#define BIT_RQPN_CNT_8197F BIT(3)\n#define BIT_RDE_CNT_8197F BIT(2)\n#define BIT_TDE_CNT_8197F BIT(1)\n#define BIT_DIS_CNT_8197F BIT(0)\n\n/* 2 REG_COUNTER_TH_8197F */\n#define BIT_CNT_ALL_MACID_8197F BIT(31)\n\n#define BIT_SHIFT_CNT_MACID_8197F 24\n#define BIT_MASK_CNT_MACID_8197F 0x7f\n#define BIT_CNT_MACID_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_CNT_MACID_8197F) << BIT_SHIFT_CNT_MACID_8197F)\n#define BITS_CNT_MACID_8197F                                                   \\\n\t(BIT_MASK_CNT_MACID_8197F << BIT_SHIFT_CNT_MACID_8197F)\n#define BIT_CLEAR_CNT_MACID_8197F(x) ((x) & (~BITS_CNT_MACID_8197F))\n#define BIT_GET_CNT_MACID_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_CNT_MACID_8197F) & BIT_MASK_CNT_MACID_8197F)\n#define BIT_SET_CNT_MACID_8197F(x, v)                                          \\\n\t(BIT_CLEAR_CNT_MACID_8197F(x) | BIT_CNT_MACID_8197F(v))\n\n#define BIT_SHIFT_AGG_VALUE2_8197F 16\n#define BIT_MASK_AGG_VALUE2_8197F 0x7f\n#define BIT_AGG_VALUE2_8197F(x)                                                \\\n\t(((x) & BIT_MASK_AGG_VALUE2_8197F) << BIT_SHIFT_AGG_VALUE2_8197F)\n#define BITS_AGG_VALUE2_8197F                                                  \\\n\t(BIT_MASK_AGG_VALUE2_8197F << BIT_SHIFT_AGG_VALUE2_8197F)\n#define BIT_CLEAR_AGG_VALUE2_8197F(x) ((x) & (~BITS_AGG_VALUE2_8197F))\n#define BIT_GET_AGG_VALUE2_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_AGG_VALUE2_8197F) & BIT_MASK_AGG_VALUE2_8197F)\n#define BIT_SET_AGG_VALUE2_8197F(x, v)                                         \\\n\t(BIT_CLEAR_AGG_VALUE2_8197F(x) | BIT_AGG_VALUE2_8197F(v))\n\n#define BIT_SHIFT_AGG_VALUE1_8197F 8\n#define BIT_MASK_AGG_VALUE1_8197F 0x7f\n#define BIT_AGG_VALUE1_8197F(x)                                                \\\n\t(((x) & BIT_MASK_AGG_VALUE1_8197F) << BIT_SHIFT_AGG_VALUE1_8197F)\n#define BITS_AGG_VALUE1_8197F                                                  \\\n\t(BIT_MASK_AGG_VALUE1_8197F << BIT_SHIFT_AGG_VALUE1_8197F)\n#define BIT_CLEAR_AGG_VALUE1_8197F(x) ((x) & (~BITS_AGG_VALUE1_8197F))\n#define BIT_GET_AGG_VALUE1_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_AGG_VALUE1_8197F) & BIT_MASK_AGG_VALUE1_8197F)\n#define BIT_SET_AGG_VALUE1_8197F(x, v)                                         \\\n\t(BIT_CLEAR_AGG_VALUE1_8197F(x) | BIT_AGG_VALUE1_8197F(v))\n\n#define BIT_SHIFT_AGG_VALUE0_8197F 0\n#define BIT_MASK_AGG_VALUE0_8197F 0x7f\n#define BIT_AGG_VALUE0_8197F(x)                                                \\\n\t(((x) & BIT_MASK_AGG_VALUE0_8197F) << BIT_SHIFT_AGG_VALUE0_8197F)\n#define BITS_AGG_VALUE0_8197F                                                  \\\n\t(BIT_MASK_AGG_VALUE0_8197F << BIT_SHIFT_AGG_VALUE0_8197F)\n#define BIT_CLEAR_AGG_VALUE0_8197F(x) ((x) & (~BITS_AGG_VALUE0_8197F))\n#define BIT_GET_AGG_VALUE0_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_AGG_VALUE0_8197F) & BIT_MASK_AGG_VALUE0_8197F)\n#define BIT_SET_AGG_VALUE0_8197F(x, v)                                         \\\n\t(BIT_CLEAR_AGG_VALUE0_8197F(x) | BIT_AGG_VALUE0_8197F(v))\n\n/* 2 REG_COUNTER_SET_8197F */\n#define BIT_RTS_RST_8197F BIT(24)\n#define BIT_PTCL_RST_8197F BIT(23)\n#define BIT_SCH_RST_8197F BIT(22)\n#define BIT_EDCA_RST_8197F BIT(21)\n#define BIT_RQPN_RST_8197F BIT(20)\n#define BIT_USB_RST_8197F BIT(19)\n#define BIT_PCIE_RST_8197F BIT(18)\n#define BIT_RXDMA_RST_8197F BIT(17)\n#define BIT_TXDMA_RST_8197F BIT(16)\n#define BIT_EN_RTS_START_8197F BIT(8)\n#define BIT_EN_PTCL_START_8197F BIT(7)\n#define BIT_EN_SCH_START_8197F BIT(6)\n#define BIT_EN_EDCA_START_8197F BIT(5)\n#define BIT_EN_RQPN_START_8197F BIT(4)\n#define BIT_EN_USB_START_8197F BIT(3)\n#define BIT_EN_PCIE_START_8197F BIT(2)\n#define BIT_EN_RXDMA_START_8197F BIT(1)\n#define BIT_EN_TXDMA_START_8197F BIT(0)\n\n/* 2 REG_COUNTER_OVERFLOW_8197F */\n#define BIT_RTS_OVF_8197F BIT(8)\n#define BIT_PTCL_OVF_8197F BIT(7)\n#define BIT_SCH_OVF_8197F BIT(6)\n#define BIT_EDCA_OVF_8197F BIT(5)\n#define BIT_RQPN_OVF_8197F BIT(4)\n#define BIT_USB_OVF_8197F BIT(3)\n#define BIT_PCIE_OVF_8197F BIT(2)\n#define BIT_RXDMA_OVF_8197F BIT(1)\n#define BIT_TXDMA_OVF_8197F BIT(0)\n\n/* 2 REG_TDE_LEN_TH_8197F */\n\n#define BIT_SHIFT_TXDMA_LEN_TH0_8197F 16\n#define BIT_MASK_TXDMA_LEN_TH0_8197F 0xffff\n#define BIT_TXDMA_LEN_TH0_8197F(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_LEN_TH0_8197F) << BIT_SHIFT_TXDMA_LEN_TH0_8197F)\n#define BITS_TXDMA_LEN_TH0_8197F                                               \\\n\t(BIT_MASK_TXDMA_LEN_TH0_8197F << BIT_SHIFT_TXDMA_LEN_TH0_8197F)\n#define BIT_CLEAR_TXDMA_LEN_TH0_8197F(x) ((x) & (~BITS_TXDMA_LEN_TH0_8197F))\n#define BIT_GET_TXDMA_LEN_TH0_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_LEN_TH0_8197F) & BIT_MASK_TXDMA_LEN_TH0_8197F)\n#define BIT_SET_TXDMA_LEN_TH0_8197F(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_LEN_TH0_8197F(x) | BIT_TXDMA_LEN_TH0_8197F(v))\n\n#define BIT_SHIFT_TXDMA_LEN_TH1_8197F 0\n#define BIT_MASK_TXDMA_LEN_TH1_8197F 0xffff\n#define BIT_TXDMA_LEN_TH1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_LEN_TH1_8197F) << BIT_SHIFT_TXDMA_LEN_TH1_8197F)\n#define BITS_TXDMA_LEN_TH1_8197F                                               \\\n\t(BIT_MASK_TXDMA_LEN_TH1_8197F << BIT_SHIFT_TXDMA_LEN_TH1_8197F)\n#define BIT_CLEAR_TXDMA_LEN_TH1_8197F(x) ((x) & (~BITS_TXDMA_LEN_TH1_8197F))\n#define BIT_GET_TXDMA_LEN_TH1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_LEN_TH1_8197F) & BIT_MASK_TXDMA_LEN_TH1_8197F)\n#define BIT_SET_TXDMA_LEN_TH1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_LEN_TH1_8197F(x) | BIT_TXDMA_LEN_TH1_8197F(v))\n\n/* 2 REG_RDE_LEN_TH_8197F */\n\n#define BIT_SHIFT_RXDMA_LEN_TH0_8197F 16\n#define BIT_MASK_RXDMA_LEN_TH0_8197F 0xffff\n#define BIT_RXDMA_LEN_TH0_8197F(x)                                             \\\n\t(((x) & BIT_MASK_RXDMA_LEN_TH0_8197F) << BIT_SHIFT_RXDMA_LEN_TH0_8197F)\n#define BITS_RXDMA_LEN_TH0_8197F                                               \\\n\t(BIT_MASK_RXDMA_LEN_TH0_8197F << BIT_SHIFT_RXDMA_LEN_TH0_8197F)\n#define BIT_CLEAR_RXDMA_LEN_TH0_8197F(x) ((x) & (~BITS_RXDMA_LEN_TH0_8197F))\n#define BIT_GET_RXDMA_LEN_TH0_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXDMA_LEN_TH0_8197F) & BIT_MASK_RXDMA_LEN_TH0_8197F)\n#define BIT_SET_RXDMA_LEN_TH0_8197F(x, v)                                      \\\n\t(BIT_CLEAR_RXDMA_LEN_TH0_8197F(x) | BIT_RXDMA_LEN_TH0_8197F(v))\n\n#define BIT_SHIFT_RXDMA_LEN_TH1_8197F 0\n#define BIT_MASK_RXDMA_LEN_TH1_8197F 0xffff\n#define BIT_RXDMA_LEN_TH1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_RXDMA_LEN_TH1_8197F) << BIT_SHIFT_RXDMA_LEN_TH1_8197F)\n#define BITS_RXDMA_LEN_TH1_8197F                                               \\\n\t(BIT_MASK_RXDMA_LEN_TH1_8197F << BIT_SHIFT_RXDMA_LEN_TH1_8197F)\n#define BIT_CLEAR_RXDMA_LEN_TH1_8197F(x) ((x) & (~BITS_RXDMA_LEN_TH1_8197F))\n#define BIT_GET_RXDMA_LEN_TH1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXDMA_LEN_TH1_8197F) & BIT_MASK_RXDMA_LEN_TH1_8197F)\n#define BIT_SET_RXDMA_LEN_TH1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_RXDMA_LEN_TH1_8197F(x) | BIT_RXDMA_LEN_TH1_8197F(v))\n\n/* 2 REG_PCIE_EXEC_TIME_8197F */\n\n#define BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F 16\n#define BIT_MASK_COUNTER_INTERVAL_SEL_8197F 0x3\n#define BIT_COUNTER_INTERVAL_SEL_8197F(x)                                      \\\n\t(((x) & BIT_MASK_COUNTER_INTERVAL_SEL_8197F)                           \\\n\t << BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F)\n#define BITS_COUNTER_INTERVAL_SEL_8197F                                        \\\n\t(BIT_MASK_COUNTER_INTERVAL_SEL_8197F                                   \\\n\t << BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F)\n#define BIT_CLEAR_COUNTER_INTERVAL_SEL_8197F(x)                                \\\n\t((x) & (~BITS_COUNTER_INTERVAL_SEL_8197F))\n#define BIT_GET_COUNTER_INTERVAL_SEL_8197F(x)                                  \\\n\t(((x) >> BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) &                       \\\n\t BIT_MASK_COUNTER_INTERVAL_SEL_8197F)\n#define BIT_SET_COUNTER_INTERVAL_SEL_8197F(x, v)                               \\\n\t(BIT_CLEAR_COUNTER_INTERVAL_SEL_8197F(x) |                             \\\n\t BIT_COUNTER_INTERVAL_SEL_8197F(v))\n\n#define BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F 0\n#define BIT_MASK_PCIE_TRANS_DATA_TH1_8197F 0xffff\n#define BIT_PCIE_TRANS_DATA_TH1_8197F(x)                                       \\\n\t(((x) & BIT_MASK_PCIE_TRANS_DATA_TH1_8197F)                            \\\n\t << BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F)\n#define BITS_PCIE_TRANS_DATA_TH1_8197F                                         \\\n\t(BIT_MASK_PCIE_TRANS_DATA_TH1_8197F                                    \\\n\t << BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F)\n#define BIT_CLEAR_PCIE_TRANS_DATA_TH1_8197F(x)                                 \\\n\t((x) & (~BITS_PCIE_TRANS_DATA_TH1_8197F))\n#define BIT_GET_PCIE_TRANS_DATA_TH1_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) &                        \\\n\t BIT_MASK_PCIE_TRANS_DATA_TH1_8197F)\n#define BIT_SET_PCIE_TRANS_DATA_TH1_8197F(x, v)                                \\\n\t(BIT_CLEAR_PCIE_TRANS_DATA_TH1_8197F(x) |                              \\\n\t BIT_PCIE_TRANS_DATA_TH1_8197F(v))\n\n/* 2 REG_FT2IMR_8197F */\n#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(31)\n#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_EN_8197F BIT(30)\n#define BIT_PORT4_TRIPKT_OK_INT_EN_8197F BIT(29)\n#define BIT_PORT4_RX_EOSP_OK_INT_EN_8197F BIT(28)\n#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(27)\n#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_EN_8197F BIT(26)\n#define BIT_PORT3_TRIPKT_OK_INT_EN_8197F BIT(25)\n#define BIT_PORT3_RX_EOSP_OK_INT_EN_8197F BIT(24)\n#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(23)\n#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_EN_8197F BIT(22)\n#define BIT_PORT2_TRIPKT_OK_INT_EN_8197F BIT(21)\n#define BIT_PORT2_RX_EOSP_OK_INT_EN_8197F BIT(20)\n#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(19)\n#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_EN_8197F BIT(18)\n#define BIT_PORT1_TRIPKT_OK_INT_EN_8197F BIT(17)\n#define BIT_PORT1_RX_EOSP_OK_INT_EN_8197F BIT(16)\n#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT_EN_8197F BIT(9)\n#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT_EN_8197F BIT(8)\n#define BIT_PORT4_TX_NULL1_DONE_INT_EN_8197F BIT(7)\n#define BIT_PORT4_TX_NULL0_DONE_INT_EN_8197F BIT(6)\n#define BIT_PORT3_TX_NULL1_DONE_INT_EN_8197F BIT(5)\n#define BIT_PORT3_TX_NULL0_DONE_INT_EN_8197F BIT(4)\n#define BIT_PORT2_TX_NULL1_DONE_INT_EN_8197F BIT(3)\n#define BIT_PORT2_TX_NULL0_DONE_INT_EN_8197F BIT(2)\n#define BIT_PORT1_TX_NULL1_DONE_INT_EN_8197F BIT(1)\n#define BIT_PORT1_TX_NULL0_DONE_INT_EN_8197F BIT(0)\n\n/* 2 REG_FT2ISR_8197F */\n#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_8197F BIT(31)\n#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_8197F BIT(30)\n#define BIT_PORT4_TRIPKT_OK_INT_8197F BIT(29)\n#define BIT_PORT4_RX_EOSP_OK_INT_8197F BIT(28)\n#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_8197F BIT(27)\n#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_8197F BIT(26)\n#define BIT_PORT3_TRIPKT_OK_INT_8197F BIT(25)\n#define BIT_PORT3_RX_EOSP_OK_INT_8197F BIT(24)\n#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_8197F BIT(23)\n#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_8197F BIT(22)\n#define BIT_PORT2_TRIPKT_OK_INT_8197F BIT(21)\n#define BIT_PORT2_RX_EOSP_OK_INT_8197F BIT(20)\n#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_8197F BIT(19)\n#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_8197F BIT(18)\n#define BIT_PORT1_TRIPKT_OK_INT_8197F BIT(17)\n#define BIT_PORT1_RX_EOSP_OK_INT_8197F BIT(16)\n#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT_8197F BIT(9)\n#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT_8197F BIT(8)\n#define BIT_PORT4_TX_NULL1_DONE_INT_8197F BIT(7)\n#define BIT_PORT4_TX_NULL0_DONE_INT_8197F BIT(6)\n#define BIT_PORT3_TX_NULL1_DONE_INT_8197F BIT(5)\n#define BIT_PORT3_TX_NULL0_DONE_INT_8197F BIT(4)\n#define BIT_PORT2_TX_NULL1_DONE_INT_8197F BIT(3)\n#define BIT_PORT2_TX_NULL0_DONE_INT_8197F BIT(2)\n#define BIT_PORT1_TX_NULL1_DONE_INT_8197F BIT(1)\n#define BIT_PORT1_TX_NULL0_DONE_INT_8197F BIT(0)\n\n/* 2 REG_MSG2_8197F */\n\n#define BIT_SHIFT_FW_MSG2_8197F 0\n#define BIT_MASK_FW_MSG2_8197F 0xffffffffL\n#define BIT_FW_MSG2_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG2_8197F) << BIT_SHIFT_FW_MSG2_8197F)\n#define BITS_FW_MSG2_8197F (BIT_MASK_FW_MSG2_8197F << BIT_SHIFT_FW_MSG2_8197F)\n#define BIT_CLEAR_FW_MSG2_8197F(x) ((x) & (~BITS_FW_MSG2_8197F))\n#define BIT_GET_FW_MSG2_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG2_8197F) & BIT_MASK_FW_MSG2_8197F)\n#define BIT_SET_FW_MSG2_8197F(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG2_8197F(x) | BIT_FW_MSG2_8197F(v))\n\n/* 2 REG_MSG3_8197F */\n\n#define BIT_SHIFT_FW_MSG3_8197F 0\n#define BIT_MASK_FW_MSG3_8197F 0xffffffffL\n#define BIT_FW_MSG3_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG3_8197F) << BIT_SHIFT_FW_MSG3_8197F)\n#define BITS_FW_MSG3_8197F (BIT_MASK_FW_MSG3_8197F << BIT_SHIFT_FW_MSG3_8197F)\n#define BIT_CLEAR_FW_MSG3_8197F(x) ((x) & (~BITS_FW_MSG3_8197F))\n#define BIT_GET_FW_MSG3_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG3_8197F) & BIT_MASK_FW_MSG3_8197F)\n#define BIT_SET_FW_MSG3_8197F(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG3_8197F(x) | BIT_FW_MSG3_8197F(v))\n\n/* 2 REG_MSG4_8197F */\n\n#define BIT_SHIFT_FW_MSG4_8197F 0\n#define BIT_MASK_FW_MSG4_8197F 0xffffffffL\n#define BIT_FW_MSG4_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG4_8197F) << BIT_SHIFT_FW_MSG4_8197F)\n#define BITS_FW_MSG4_8197F (BIT_MASK_FW_MSG4_8197F << BIT_SHIFT_FW_MSG4_8197F)\n#define BIT_CLEAR_FW_MSG4_8197F(x) ((x) & (~BITS_FW_MSG4_8197F))\n#define BIT_GET_FW_MSG4_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG4_8197F) & BIT_MASK_FW_MSG4_8197F)\n#define BIT_SET_FW_MSG4_8197F(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG4_8197F(x) | BIT_FW_MSG4_8197F(v))\n\n/* 2 REG_MSG5_8197F */\n\n#define BIT_SHIFT_FW_MSG5_8197F 0\n#define BIT_MASK_FW_MSG5_8197F 0xffffffffL\n#define BIT_FW_MSG5_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG5_8197F) << BIT_SHIFT_FW_MSG5_8197F)\n#define BITS_FW_MSG5_8197F (BIT_MASK_FW_MSG5_8197F << BIT_SHIFT_FW_MSG5_8197F)\n#define BIT_CLEAR_FW_MSG5_8197F(x) ((x) & (~BITS_FW_MSG5_8197F))\n#define BIT_GET_FW_MSG5_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG5_8197F) & BIT_MASK_FW_MSG5_8197F)\n#define BIT_SET_FW_MSG5_8197F(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG5_8197F(x) | BIT_FW_MSG5_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_FIFOPAGE_CTRL_1_8197F */\n\n#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F 16\n#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F 0xff\n#define BIT_TX_OQT_HE_FREE_SPACE_V1_8197F(x)                                   \\\n\t(((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F)                        \\\n\t << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F)\n#define BITS_TX_OQT_HE_FREE_SPACE_V1_8197F                                     \\\n\t(BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F                                \\\n\t << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F)\n#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8197F(x)                             \\\n\t((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8197F))\n#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8197F(x)                               \\\n\t(((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) &                    \\\n\t BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F)\n#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8197F(x, v)                            \\\n\t(BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8197F(x) |                          \\\n\t BIT_TX_OQT_HE_FREE_SPACE_V1_8197F(v))\n\n#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F 0\n#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F 0xff\n#define BIT_TX_OQT_NL_FREE_SPACE_V1_8197F(x)                                   \\\n\t(((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F)                        \\\n\t << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F)\n#define BITS_TX_OQT_NL_FREE_SPACE_V1_8197F                                     \\\n\t(BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F                                \\\n\t << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F)\n#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8197F(x)                             \\\n\t((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8197F))\n#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8197F(x)                               \\\n\t(((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) &                    \\\n\t BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F)\n#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8197F(x, v)                            \\\n\t(BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8197F(x) |                          \\\n\t BIT_TX_OQT_NL_FREE_SPACE_V1_8197F(v))\n\n/* 2 REG_FIFOPAGE_CTRL_2_8197F */\n#define BIT_BCN_VALID_1_V1_8197F BIT(31)\n\n#define BIT_SHIFT_BCN_HEAD_1_V1_8197F 16\n#define BIT_MASK_BCN_HEAD_1_V1_8197F 0xfff\n#define BIT_BCN_HEAD_1_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_BCN_HEAD_1_V1_8197F) << BIT_SHIFT_BCN_HEAD_1_V1_8197F)\n#define BITS_BCN_HEAD_1_V1_8197F                                               \\\n\t(BIT_MASK_BCN_HEAD_1_V1_8197F << BIT_SHIFT_BCN_HEAD_1_V1_8197F)\n#define BIT_CLEAR_BCN_HEAD_1_V1_8197F(x) ((x) & (~BITS_BCN_HEAD_1_V1_8197F))\n#define BIT_GET_BCN_HEAD_1_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8197F) & BIT_MASK_BCN_HEAD_1_V1_8197F)\n#define BIT_SET_BCN_HEAD_1_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_BCN_HEAD_1_V1_8197F(x) | BIT_BCN_HEAD_1_V1_8197F(v))\n\n#define BIT_BCN_VALID_V1_8197F BIT(15)\n\n#define BIT_SHIFT_BCN_HEAD_V1_8197F 0\n#define BIT_MASK_BCN_HEAD_V1_8197F 0xfff\n#define BIT_BCN_HEAD_V1_8197F(x)                                               \\\n\t(((x) & BIT_MASK_BCN_HEAD_V1_8197F) << BIT_SHIFT_BCN_HEAD_V1_8197F)\n#define BITS_BCN_HEAD_V1_8197F                                                 \\\n\t(BIT_MASK_BCN_HEAD_V1_8197F << BIT_SHIFT_BCN_HEAD_V1_8197F)\n#define BIT_CLEAR_BCN_HEAD_V1_8197F(x) ((x) & (~BITS_BCN_HEAD_V1_8197F))\n#define BIT_GET_BCN_HEAD_V1_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_BCN_HEAD_V1_8197F) & BIT_MASK_BCN_HEAD_V1_8197F)\n#define BIT_SET_BCN_HEAD_V1_8197F(x, v)                                        \\\n\t(BIT_CLEAR_BCN_HEAD_V1_8197F(x) | BIT_BCN_HEAD_V1_8197F(v))\n\n/* 2 REG_AUTO_LLT_V1_8197F */\n\n#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F 24\n#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F 0xff\n#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x)                            \\\n\t(((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F)                 \\\n\t << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F)\n#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F                              \\\n\t(BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F                         \\\n\t << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F)\n#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x)                      \\\n\t((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F))\n#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x)                        \\\n\t(((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) &             \\\n\t BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F)\n#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x, v)                     \\\n\t(BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) |                   \\\n\t BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(v))\n\n#define BIT_SHIFT_LLT_FREE_PAGE_V1_8197F 8\n#define BIT_MASK_LLT_FREE_PAGE_V1_8197F 0xffff\n#define BIT_LLT_FREE_PAGE_V1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_LLT_FREE_PAGE_V1_8197F)                               \\\n\t << BIT_SHIFT_LLT_FREE_PAGE_V1_8197F)\n#define BITS_LLT_FREE_PAGE_V1_8197F                                            \\\n\t(BIT_MASK_LLT_FREE_PAGE_V1_8197F << BIT_SHIFT_LLT_FREE_PAGE_V1_8197F)\n#define BIT_CLEAR_LLT_FREE_PAGE_V1_8197F(x)                                    \\\n\t((x) & (~BITS_LLT_FREE_PAGE_V1_8197F))\n#define BIT_GET_LLT_FREE_PAGE_V1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) &                           \\\n\t BIT_MASK_LLT_FREE_PAGE_V1_8197F)\n#define BIT_SET_LLT_FREE_PAGE_V1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_LLT_FREE_PAGE_V1_8197F(x) | BIT_LLT_FREE_PAGE_V1_8197F(v))\n\n#define BIT_SHIFT_BLK_DESC_NUM_8197F 4\n#define BIT_MASK_BLK_DESC_NUM_8197F 0xf\n#define BIT_BLK_DESC_NUM_8197F(x)                                              \\\n\t(((x) & BIT_MASK_BLK_DESC_NUM_8197F) << BIT_SHIFT_BLK_DESC_NUM_8197F)\n#define BITS_BLK_DESC_NUM_8197F                                                \\\n\t(BIT_MASK_BLK_DESC_NUM_8197F << BIT_SHIFT_BLK_DESC_NUM_8197F)\n#define BIT_CLEAR_BLK_DESC_NUM_8197F(x) ((x) & (~BITS_BLK_DESC_NUM_8197F))\n#define BIT_GET_BLK_DESC_NUM_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_BLK_DESC_NUM_8197F) & BIT_MASK_BLK_DESC_NUM_8197F)\n#define BIT_SET_BLK_DESC_NUM_8197F(x, v)                                       \\\n\t(BIT_CLEAR_BLK_DESC_NUM_8197F(x) | BIT_BLK_DESC_NUM_8197F(v))\n\n#define BIT_R_BCN_HEAD_SEL_8197F BIT(3)\n#define BIT_R_EN_BCN_SW_HEAD_SEL_8197F BIT(2)\n#define BIT_LLT_DBG_SEL_8197F BIT(1)\n#define BIT_AUTO_INIT_LLT_V1_8197F BIT(0)\n\n/* 2 REG_TXDMA_OFFSET_CHK_8197F */\n#define BIT_EM_CHKSUM_FIN_8197F BIT(31)\n#define BIT_EMN_PCIE_DMA_MOD_8197F BIT(30)\n#define BIT_EN_TXQUE_CLR_8197F BIT(29)\n#define BIT_EN_PCIE_FIFO_MODE_8197F BIT(28)\n\n#define BIT_SHIFT_PG_UNDER_TH_V1_8197F 16\n#define BIT_MASK_PG_UNDER_TH_V1_8197F 0xfff\n#define BIT_PG_UNDER_TH_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_PG_UNDER_TH_V1_8197F)                                 \\\n\t << BIT_SHIFT_PG_UNDER_TH_V1_8197F)\n#define BITS_PG_UNDER_TH_V1_8197F                                              \\\n\t(BIT_MASK_PG_UNDER_TH_V1_8197F << BIT_SHIFT_PG_UNDER_TH_V1_8197F)\n#define BIT_CLEAR_PG_UNDER_TH_V1_8197F(x) ((x) & (~BITS_PG_UNDER_TH_V1_8197F))\n#define BIT_GET_PG_UNDER_TH_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8197F) &                             \\\n\t BIT_MASK_PG_UNDER_TH_V1_8197F)\n#define BIT_SET_PG_UNDER_TH_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_PG_UNDER_TH_V1_8197F(x) | BIT_PG_UNDER_TH_V1_8197F(v))\n\n#define BIT_EN_RESET_RESTORE_H2C_8197F BIT(15)\n#define BIT_SDIO_TDE_FINISH_8197F BIT(14)\n#define BIT_SDIO_TXDESC_CHKSUM_EN_8197F BIT(13)\n#define BIT_RST_RDPTR_8197F BIT(12)\n#define BIT_RST_WRPTR_8197F BIT(11)\n#define BIT_CHK_PG_TH_EN_8197F BIT(10)\n#define BIT_DROP_DATA_EN_8197F BIT(9)\n#define BIT_CHECK_OFFSET_EN_8197F BIT(8)\n\n#define BIT_SHIFT_CHECK_OFFSET_8197F 0\n#define BIT_MASK_CHECK_OFFSET_8197F 0xff\n#define BIT_CHECK_OFFSET_8197F(x)                                              \\\n\t(((x) & BIT_MASK_CHECK_OFFSET_8197F) << BIT_SHIFT_CHECK_OFFSET_8197F)\n#define BITS_CHECK_OFFSET_8197F                                                \\\n\t(BIT_MASK_CHECK_OFFSET_8197F << BIT_SHIFT_CHECK_OFFSET_8197F)\n#define BIT_CLEAR_CHECK_OFFSET_8197F(x) ((x) & (~BITS_CHECK_OFFSET_8197F))\n#define BIT_GET_CHECK_OFFSET_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_CHECK_OFFSET_8197F) & BIT_MASK_CHECK_OFFSET_8197F)\n#define BIT_SET_CHECK_OFFSET_8197F(x, v)                                       \\\n\t(BIT_CLEAR_CHECK_OFFSET_8197F(x) | BIT_CHECK_OFFSET_8197F(v))\n\n/* 2 REG_TXDMA_STATUS_8197F */\n#define BIT_HI_OQT_UDN_8197F BIT(17)\n#define BIT_HI_OQT_OVF_8197F BIT(16)\n#define BIT_PAYLOAD_CHKSUM_ERR_8197F BIT(15)\n#define BIT_PAYLOAD_UDN_8197F BIT(14)\n#define BIT_PAYLOAD_OVF_8197F BIT(13)\n#define BIT_DSC_CHKSUM_FAIL_8197F BIT(12)\n#define BIT_UNKNOWN_QSEL_8197F BIT(11)\n#define BIT_EP_QSEL_DIFF_8197F BIT(10)\n#define BIT_TX_OFFS_UNMATCH_8197F BIT(9)\n#define BIT_TXOQT_UDN_8197F BIT(8)\n#define BIT_TXOQT_OVF_8197F BIT(7)\n#define BIT_TXDMA_SFF_UDN_8197F BIT(6)\n#define BIT_TXDMA_SFF_OVF_8197F BIT(5)\n#define BIT_LLT_NULL_PG_8197F BIT(4)\n#define BIT_PAGE_UDN_8197F BIT(3)\n#define BIT_PAGE_OVF_8197F BIT(2)\n#define BIT_TXFF_PG_UDN_8197F BIT(1)\n#define BIT_TXFF_PG_OVF_8197F BIT(0)\n\n/* 2 REG_TX_DMA_DBG_8197F */\n\n/* 2 REG_TQPNT1_8197F */\n\n#define BIT_SHIFT_HPQ_HIGH_TH_V1_8197F 16\n#define BIT_MASK_HPQ_HIGH_TH_V1_8197F 0xfff\n#define BIT_HPQ_HIGH_TH_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HPQ_HIGH_TH_V1_8197F)                                 \\\n\t << BIT_SHIFT_HPQ_HIGH_TH_V1_8197F)\n#define BITS_HPQ_HIGH_TH_V1_8197F                                              \\\n\t(BIT_MASK_HPQ_HIGH_TH_V1_8197F << BIT_SHIFT_HPQ_HIGH_TH_V1_8197F)\n#define BIT_CLEAR_HPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8197F))\n#define BIT_GET_HPQ_HIGH_TH_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) &                             \\\n\t BIT_MASK_HPQ_HIGH_TH_V1_8197F)\n#define BIT_SET_HPQ_HIGH_TH_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HPQ_HIGH_TH_V1_8197F(x) | BIT_HPQ_HIGH_TH_V1_8197F(v))\n\n#define BIT_SHIFT_HPQ_LOW_TH_V1_8197F 0\n#define BIT_MASK_HPQ_LOW_TH_V1_8197F 0xfff\n#define BIT_HPQ_LOW_TH_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HPQ_LOW_TH_V1_8197F) << BIT_SHIFT_HPQ_LOW_TH_V1_8197F)\n#define BITS_HPQ_LOW_TH_V1_8197F                                               \\\n\t(BIT_MASK_HPQ_LOW_TH_V1_8197F << BIT_SHIFT_HPQ_LOW_TH_V1_8197F)\n#define BIT_CLEAR_HPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8197F))\n#define BIT_GET_HPQ_LOW_TH_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8197F) & BIT_MASK_HPQ_LOW_TH_V1_8197F)\n#define BIT_SET_HPQ_LOW_TH_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HPQ_LOW_TH_V1_8197F(x) | BIT_HPQ_LOW_TH_V1_8197F(v))\n\n/* 2 REG_TQPNT2_8197F */\n\n#define BIT_SHIFT_NPQ_HIGH_TH_V1_8197F 16\n#define BIT_MASK_NPQ_HIGH_TH_V1_8197F 0xfff\n#define BIT_NPQ_HIGH_TH_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_NPQ_HIGH_TH_V1_8197F)                                 \\\n\t << BIT_SHIFT_NPQ_HIGH_TH_V1_8197F)\n#define BITS_NPQ_HIGH_TH_V1_8197F                                              \\\n\t(BIT_MASK_NPQ_HIGH_TH_V1_8197F << BIT_SHIFT_NPQ_HIGH_TH_V1_8197F)\n#define BIT_CLEAR_NPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8197F))\n#define BIT_GET_NPQ_HIGH_TH_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) &                             \\\n\t BIT_MASK_NPQ_HIGH_TH_V1_8197F)\n#define BIT_SET_NPQ_HIGH_TH_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_NPQ_HIGH_TH_V1_8197F(x) | BIT_NPQ_HIGH_TH_V1_8197F(v))\n\n#define BIT_SHIFT_NPQ_LOW_TH_V1_8197F 0\n#define BIT_MASK_NPQ_LOW_TH_V1_8197F 0xfff\n#define BIT_NPQ_LOW_TH_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_NPQ_LOW_TH_V1_8197F) << BIT_SHIFT_NPQ_LOW_TH_V1_8197F)\n#define BITS_NPQ_LOW_TH_V1_8197F                                               \\\n\t(BIT_MASK_NPQ_LOW_TH_V1_8197F << BIT_SHIFT_NPQ_LOW_TH_V1_8197F)\n#define BIT_CLEAR_NPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8197F))\n#define BIT_GET_NPQ_LOW_TH_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8197F) & BIT_MASK_NPQ_LOW_TH_V1_8197F)\n#define BIT_SET_NPQ_LOW_TH_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_NPQ_LOW_TH_V1_8197F(x) | BIT_NPQ_LOW_TH_V1_8197F(v))\n\n/* 2 REG_TQPNT3_8197F */\n\n#define BIT_SHIFT_LPQ_HIGH_TH_V1_8197F 16\n#define BIT_MASK_LPQ_HIGH_TH_V1_8197F 0xfff\n#define BIT_LPQ_HIGH_TH_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_LPQ_HIGH_TH_V1_8197F)                                 \\\n\t << BIT_SHIFT_LPQ_HIGH_TH_V1_8197F)\n#define BITS_LPQ_HIGH_TH_V1_8197F                                              \\\n\t(BIT_MASK_LPQ_HIGH_TH_V1_8197F << BIT_SHIFT_LPQ_HIGH_TH_V1_8197F)\n#define BIT_CLEAR_LPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8197F))\n#define BIT_GET_LPQ_HIGH_TH_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) &                             \\\n\t BIT_MASK_LPQ_HIGH_TH_V1_8197F)\n#define BIT_SET_LPQ_HIGH_TH_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_LPQ_HIGH_TH_V1_8197F(x) | BIT_LPQ_HIGH_TH_V1_8197F(v))\n\n#define BIT_SHIFT_LPQ_LOW_TH_V1_8197F 0\n#define BIT_MASK_LPQ_LOW_TH_V1_8197F 0xfff\n#define BIT_LPQ_LOW_TH_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_LPQ_LOW_TH_V1_8197F) << BIT_SHIFT_LPQ_LOW_TH_V1_8197F)\n#define BITS_LPQ_LOW_TH_V1_8197F                                               \\\n\t(BIT_MASK_LPQ_LOW_TH_V1_8197F << BIT_SHIFT_LPQ_LOW_TH_V1_8197F)\n#define BIT_CLEAR_LPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8197F))\n#define BIT_GET_LPQ_LOW_TH_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8197F) & BIT_MASK_LPQ_LOW_TH_V1_8197F)\n#define BIT_SET_LPQ_LOW_TH_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_LPQ_LOW_TH_V1_8197F(x) | BIT_LPQ_LOW_TH_V1_8197F(v))\n\n/* 2 REG_TQPNT4_8197F */\n\n#define BIT_SHIFT_EXQ_HIGH_TH_V1_8197F 16\n#define BIT_MASK_EXQ_HIGH_TH_V1_8197F 0xfff\n#define BIT_EXQ_HIGH_TH_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_EXQ_HIGH_TH_V1_8197F)                                 \\\n\t << BIT_SHIFT_EXQ_HIGH_TH_V1_8197F)\n#define BITS_EXQ_HIGH_TH_V1_8197F                                              \\\n\t(BIT_MASK_EXQ_HIGH_TH_V1_8197F << BIT_SHIFT_EXQ_HIGH_TH_V1_8197F)\n#define BIT_CLEAR_EXQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8197F))\n#define BIT_GET_EXQ_HIGH_TH_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) &                             \\\n\t BIT_MASK_EXQ_HIGH_TH_V1_8197F)\n#define BIT_SET_EXQ_HIGH_TH_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_EXQ_HIGH_TH_V1_8197F(x) | BIT_EXQ_HIGH_TH_V1_8197F(v))\n\n#define BIT_SHIFT_EXQ_LOW_TH_V1_8197F 0\n#define BIT_MASK_EXQ_LOW_TH_V1_8197F 0xfff\n#define BIT_EXQ_LOW_TH_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_EXQ_LOW_TH_V1_8197F) << BIT_SHIFT_EXQ_LOW_TH_V1_8197F)\n#define BITS_EXQ_LOW_TH_V1_8197F                                               \\\n\t(BIT_MASK_EXQ_LOW_TH_V1_8197F << BIT_SHIFT_EXQ_LOW_TH_V1_8197F)\n#define BIT_CLEAR_EXQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8197F))\n#define BIT_GET_EXQ_LOW_TH_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8197F) & BIT_MASK_EXQ_LOW_TH_V1_8197F)\n#define BIT_SET_EXQ_LOW_TH_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_EXQ_LOW_TH_V1_8197F(x) | BIT_EXQ_LOW_TH_V1_8197F(v))\n\n/* 2 REG_RQPN_CTRL_1_8197F */\n\n#define BIT_SHIFT_TXPKTNUM_H_8197F 16\n#define BIT_MASK_TXPKTNUM_H_8197F 0xffff\n#define BIT_TXPKTNUM_H_8197F(x)                                                \\\n\t(((x) & BIT_MASK_TXPKTNUM_H_8197F) << BIT_SHIFT_TXPKTNUM_H_8197F)\n#define BITS_TXPKTNUM_H_8197F                                                  \\\n\t(BIT_MASK_TXPKTNUM_H_8197F << BIT_SHIFT_TXPKTNUM_H_8197F)\n#define BIT_CLEAR_TXPKTNUM_H_8197F(x) ((x) & (~BITS_TXPKTNUM_H_8197F))\n#define BIT_GET_TXPKTNUM_H_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_H_8197F) & BIT_MASK_TXPKTNUM_H_8197F)\n#define BIT_SET_TXPKTNUM_H_8197F(x, v)                                         \\\n\t(BIT_CLEAR_TXPKTNUM_H_8197F(x) | BIT_TXPKTNUM_H_8197F(v))\n\n#define BIT_SHIFT_TXPKTNUM_H_V1_8197F 0\n#define BIT_MASK_TXPKTNUM_H_V1_8197F 0xffff\n#define BIT_TXPKTNUM_H_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_TXPKTNUM_H_V1_8197F) << BIT_SHIFT_TXPKTNUM_H_V1_8197F)\n#define BITS_TXPKTNUM_H_V1_8197F                                               \\\n\t(BIT_MASK_TXPKTNUM_H_V1_8197F << BIT_SHIFT_TXPKTNUM_H_V1_8197F)\n#define BIT_CLEAR_TXPKTNUM_H_V1_8197F(x) ((x) & (~BITS_TXPKTNUM_H_V1_8197F))\n#define BIT_GET_TXPKTNUM_H_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_H_V1_8197F) & BIT_MASK_TXPKTNUM_H_V1_8197F)\n#define BIT_SET_TXPKTNUM_H_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_TXPKTNUM_H_V1_8197F(x) | BIT_TXPKTNUM_H_V1_8197F(v))\n\n/* 2 REG_RQPN_CTRL_2_8197F */\n#define BIT_LD_RQPN_8197F BIT(31)\n#define BIT_EXQ_PUBLIC_DIS_V1_8197F BIT(19)\n#define BIT_NPQ_PUBLIC_DIS_V1_8197F BIT(18)\n#define BIT_LPQ_PUBLIC_DIS_V1_8197F BIT(17)\n#define BIT_HPQ_PUBLIC_DIS_V1_8197F BIT(16)\n\n/* 2 REG_FIFOPAGE_INFO_1_8197F */\n\n#define BIT_SHIFT_HPQ_AVAL_PG_V1_8197F 16\n#define BIT_MASK_HPQ_AVAL_PG_V1_8197F 0xfff\n#define BIT_HPQ_AVAL_PG_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HPQ_AVAL_PG_V1_8197F)                                 \\\n\t << BIT_SHIFT_HPQ_AVAL_PG_V1_8197F)\n#define BITS_HPQ_AVAL_PG_V1_8197F                                              \\\n\t(BIT_MASK_HPQ_AVAL_PG_V1_8197F << BIT_SHIFT_HPQ_AVAL_PG_V1_8197F)\n#define BIT_CLEAR_HPQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8197F))\n#define BIT_GET_HPQ_AVAL_PG_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) &                             \\\n\t BIT_MASK_HPQ_AVAL_PG_V1_8197F)\n#define BIT_SET_HPQ_AVAL_PG_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HPQ_AVAL_PG_V1_8197F(x) | BIT_HPQ_AVAL_PG_V1_8197F(v))\n\n#define BIT_SHIFT_HPQ_V1_8197F 0\n#define BIT_MASK_HPQ_V1_8197F 0xfff\n#define BIT_HPQ_V1_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_HPQ_V1_8197F) << BIT_SHIFT_HPQ_V1_8197F)\n#define BITS_HPQ_V1_8197F (BIT_MASK_HPQ_V1_8197F << BIT_SHIFT_HPQ_V1_8197F)\n#define BIT_CLEAR_HPQ_V1_8197F(x) ((x) & (~BITS_HPQ_V1_8197F))\n#define BIT_GET_HPQ_V1_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_HPQ_V1_8197F) & BIT_MASK_HPQ_V1_8197F)\n#define BIT_SET_HPQ_V1_8197F(x, v)                                             \\\n\t(BIT_CLEAR_HPQ_V1_8197F(x) | BIT_HPQ_V1_8197F(v))\n\n/* 2 REG_FIFOPAGE_INFO_2_8197F */\n\n#define BIT_SHIFT_LPQ_AVAL_PG_V1_8197F 16\n#define BIT_MASK_LPQ_AVAL_PG_V1_8197F 0xfff\n#define BIT_LPQ_AVAL_PG_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_LPQ_AVAL_PG_V1_8197F)                                 \\\n\t << BIT_SHIFT_LPQ_AVAL_PG_V1_8197F)\n#define BITS_LPQ_AVAL_PG_V1_8197F                                              \\\n\t(BIT_MASK_LPQ_AVAL_PG_V1_8197F << BIT_SHIFT_LPQ_AVAL_PG_V1_8197F)\n#define BIT_CLEAR_LPQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8197F))\n#define BIT_GET_LPQ_AVAL_PG_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) &                             \\\n\t BIT_MASK_LPQ_AVAL_PG_V1_8197F)\n#define BIT_SET_LPQ_AVAL_PG_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_LPQ_AVAL_PG_V1_8197F(x) | BIT_LPQ_AVAL_PG_V1_8197F(v))\n\n#define BIT_SHIFT_LPQ_V1_8197F 0\n#define BIT_MASK_LPQ_V1_8197F 0xfff\n#define BIT_LPQ_V1_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_LPQ_V1_8197F) << BIT_SHIFT_LPQ_V1_8197F)\n#define BITS_LPQ_V1_8197F (BIT_MASK_LPQ_V1_8197F << BIT_SHIFT_LPQ_V1_8197F)\n#define BIT_CLEAR_LPQ_V1_8197F(x) ((x) & (~BITS_LPQ_V1_8197F))\n#define BIT_GET_LPQ_V1_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_LPQ_V1_8197F) & BIT_MASK_LPQ_V1_8197F)\n#define BIT_SET_LPQ_V1_8197F(x, v)                                             \\\n\t(BIT_CLEAR_LPQ_V1_8197F(x) | BIT_LPQ_V1_8197F(v))\n\n/* 2 REG_FIFOPAGE_INFO_3_8197F */\n\n#define BIT_SHIFT_NPQ_AVAL_PG_V1_8197F 16\n#define BIT_MASK_NPQ_AVAL_PG_V1_8197F 0xfff\n#define BIT_NPQ_AVAL_PG_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_NPQ_AVAL_PG_V1_8197F)                                 \\\n\t << BIT_SHIFT_NPQ_AVAL_PG_V1_8197F)\n#define BITS_NPQ_AVAL_PG_V1_8197F                                              \\\n\t(BIT_MASK_NPQ_AVAL_PG_V1_8197F << BIT_SHIFT_NPQ_AVAL_PG_V1_8197F)\n#define BIT_CLEAR_NPQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8197F))\n#define BIT_GET_NPQ_AVAL_PG_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8197F) &                             \\\n\t BIT_MASK_NPQ_AVAL_PG_V1_8197F)\n#define BIT_SET_NPQ_AVAL_PG_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_NPQ_AVAL_PG_V1_8197F(x) | BIT_NPQ_AVAL_PG_V1_8197F(v))\n\n#define BIT_SHIFT_NPQ_V1_8197F 0\n#define BIT_MASK_NPQ_V1_8197F 0xfff\n#define BIT_NPQ_V1_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_NPQ_V1_8197F) << BIT_SHIFT_NPQ_V1_8197F)\n#define BITS_NPQ_V1_8197F (BIT_MASK_NPQ_V1_8197F << BIT_SHIFT_NPQ_V1_8197F)\n#define BIT_CLEAR_NPQ_V1_8197F(x) ((x) & (~BITS_NPQ_V1_8197F))\n#define BIT_GET_NPQ_V1_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_NPQ_V1_8197F) & BIT_MASK_NPQ_V1_8197F)\n#define BIT_SET_NPQ_V1_8197F(x, v)                                             \\\n\t(BIT_CLEAR_NPQ_V1_8197F(x) | BIT_NPQ_V1_8197F(v))\n\n/* 2 REG_FIFOPAGE_INFO_4_8197F */\n\n#define BIT_SHIFT_EXQ_AVAL_PG_V1_8197F 16\n#define BIT_MASK_EXQ_AVAL_PG_V1_8197F 0xfff\n#define BIT_EXQ_AVAL_PG_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_EXQ_AVAL_PG_V1_8197F)                                 \\\n\t << BIT_SHIFT_EXQ_AVAL_PG_V1_8197F)\n#define BITS_EXQ_AVAL_PG_V1_8197F                                              \\\n\t(BIT_MASK_EXQ_AVAL_PG_V1_8197F << BIT_SHIFT_EXQ_AVAL_PG_V1_8197F)\n#define BIT_CLEAR_EXQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8197F))\n#define BIT_GET_EXQ_AVAL_PG_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) &                             \\\n\t BIT_MASK_EXQ_AVAL_PG_V1_8197F)\n#define BIT_SET_EXQ_AVAL_PG_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_EXQ_AVAL_PG_V1_8197F(x) | BIT_EXQ_AVAL_PG_V1_8197F(v))\n\n#define BIT_SHIFT_EXQ_V1_8197F 0\n#define BIT_MASK_EXQ_V1_8197F 0xfff\n#define BIT_EXQ_V1_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_EXQ_V1_8197F) << BIT_SHIFT_EXQ_V1_8197F)\n#define BITS_EXQ_V1_8197F (BIT_MASK_EXQ_V1_8197F << BIT_SHIFT_EXQ_V1_8197F)\n#define BIT_CLEAR_EXQ_V1_8197F(x) ((x) & (~BITS_EXQ_V1_8197F))\n#define BIT_GET_EXQ_V1_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_EXQ_V1_8197F) & BIT_MASK_EXQ_V1_8197F)\n#define BIT_SET_EXQ_V1_8197F(x, v)                                             \\\n\t(BIT_CLEAR_EXQ_V1_8197F(x) | BIT_EXQ_V1_8197F(v))\n\n/* 2 REG_FIFOPAGE_INFO_5_8197F */\n\n#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F 16\n#define BIT_MASK_PUBQ_AVAL_PG_V1_8197F 0xfff\n#define BIT_PUBQ_AVAL_PG_V1_8197F(x)                                           \\\n\t(((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8197F)                                \\\n\t << BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F)\n#define BITS_PUBQ_AVAL_PG_V1_8197F                                             \\\n\t(BIT_MASK_PUBQ_AVAL_PG_V1_8197F << BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F)\n#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8197F))\n#define BIT_GET_PUBQ_AVAL_PG_V1_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) &                            \\\n\t BIT_MASK_PUBQ_AVAL_PG_V1_8197F)\n#define BIT_SET_PUBQ_AVAL_PG_V1_8197F(x, v)                                    \\\n\t(BIT_CLEAR_PUBQ_AVAL_PG_V1_8197F(x) | BIT_PUBQ_AVAL_PG_V1_8197F(v))\n\n#define BIT_SHIFT_PUBQ_V1_8197F 0\n#define BIT_MASK_PUBQ_V1_8197F 0xfff\n#define BIT_PUBQ_V1_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_PUBQ_V1_8197F) << BIT_SHIFT_PUBQ_V1_8197F)\n#define BITS_PUBQ_V1_8197F (BIT_MASK_PUBQ_V1_8197F << BIT_SHIFT_PUBQ_V1_8197F)\n#define BIT_CLEAR_PUBQ_V1_8197F(x) ((x) & (~BITS_PUBQ_V1_8197F))\n#define BIT_GET_PUBQ_V1_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_PUBQ_V1_8197F) & BIT_MASK_PUBQ_V1_8197F)\n#define BIT_SET_PUBQ_V1_8197F(x, v)                                            \\\n\t(BIT_CLEAR_PUBQ_V1_8197F(x) | BIT_PUBQ_V1_8197F(v))\n\n/* 2 REG_H2C_HEAD_8197F */\n\n#define BIT_SHIFT_H2C_HEAD_8197F 0\n#define BIT_MASK_H2C_HEAD_8197F 0x3ffff\n#define BIT_H2C_HEAD_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_H2C_HEAD_8197F) << BIT_SHIFT_H2C_HEAD_8197F)\n#define BITS_H2C_HEAD_8197F                                                    \\\n\t(BIT_MASK_H2C_HEAD_8197F << BIT_SHIFT_H2C_HEAD_8197F)\n#define BIT_CLEAR_H2C_HEAD_8197F(x) ((x) & (~BITS_H2C_HEAD_8197F))\n#define BIT_GET_H2C_HEAD_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_H2C_HEAD_8197F) & BIT_MASK_H2C_HEAD_8197F)\n#define BIT_SET_H2C_HEAD_8197F(x, v)                                           \\\n\t(BIT_CLEAR_H2C_HEAD_8197F(x) | BIT_H2C_HEAD_8197F(v))\n\n/* 2 REG_H2C_TAIL_8197F */\n\n#define BIT_SHIFT_H2C_TAIL_8197F 0\n#define BIT_MASK_H2C_TAIL_8197F 0x3ffff\n#define BIT_H2C_TAIL_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_H2C_TAIL_8197F) << BIT_SHIFT_H2C_TAIL_8197F)\n#define BITS_H2C_TAIL_8197F                                                    \\\n\t(BIT_MASK_H2C_TAIL_8197F << BIT_SHIFT_H2C_TAIL_8197F)\n#define BIT_CLEAR_H2C_TAIL_8197F(x) ((x) & (~BITS_H2C_TAIL_8197F))\n#define BIT_GET_H2C_TAIL_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_H2C_TAIL_8197F) & BIT_MASK_H2C_TAIL_8197F)\n#define BIT_SET_H2C_TAIL_8197F(x, v)                                           \\\n\t(BIT_CLEAR_H2C_TAIL_8197F(x) | BIT_H2C_TAIL_8197F(v))\n\n/* 2 REG_H2C_READ_ADDR_8197F */\n\n#define BIT_SHIFT_H2C_READ_ADDR_8197F 0\n#define BIT_MASK_H2C_READ_ADDR_8197F 0x3ffff\n#define BIT_H2C_READ_ADDR_8197F(x)                                             \\\n\t(((x) & BIT_MASK_H2C_READ_ADDR_8197F) << BIT_SHIFT_H2C_READ_ADDR_8197F)\n#define BITS_H2C_READ_ADDR_8197F                                               \\\n\t(BIT_MASK_H2C_READ_ADDR_8197F << BIT_SHIFT_H2C_READ_ADDR_8197F)\n#define BIT_CLEAR_H2C_READ_ADDR_8197F(x) ((x) & (~BITS_H2C_READ_ADDR_8197F))\n#define BIT_GET_H2C_READ_ADDR_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_H2C_READ_ADDR_8197F) & BIT_MASK_H2C_READ_ADDR_8197F)\n#define BIT_SET_H2C_READ_ADDR_8197F(x, v)                                      \\\n\t(BIT_CLEAR_H2C_READ_ADDR_8197F(x) | BIT_H2C_READ_ADDR_8197F(v))\n\n/* 2 REG_H2C_WR_ADDR_8197F */\n\n#define BIT_SHIFT_H2C_WR_ADDR_8197F 0\n#define BIT_MASK_H2C_WR_ADDR_8197F 0x3ffff\n#define BIT_H2C_WR_ADDR_8197F(x)                                               \\\n\t(((x) & BIT_MASK_H2C_WR_ADDR_8197F) << BIT_SHIFT_H2C_WR_ADDR_8197F)\n#define BITS_H2C_WR_ADDR_8197F                                                 \\\n\t(BIT_MASK_H2C_WR_ADDR_8197F << BIT_SHIFT_H2C_WR_ADDR_8197F)\n#define BIT_CLEAR_H2C_WR_ADDR_8197F(x) ((x) & (~BITS_H2C_WR_ADDR_8197F))\n#define BIT_GET_H2C_WR_ADDR_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_H2C_WR_ADDR_8197F) & BIT_MASK_H2C_WR_ADDR_8197F)\n#define BIT_SET_H2C_WR_ADDR_8197F(x, v)                                        \\\n\t(BIT_CLEAR_H2C_WR_ADDR_8197F(x) | BIT_H2C_WR_ADDR_8197F(v))\n\n/* 2 REG_H2C_INFO_8197F */\n#define BIT_EXQ_EN_PUBLIC_LIMIT_8197F BIT(11)\n#define BIT_NPQ_EN_PUBLIC_LIMIT_8197F BIT(10)\n#define BIT_LPQ_EN_PUBLIC_LIMIT_8197F BIT(9)\n#define BIT_HPQ_EN_PUBLIC_LIMIT_8197F BIT(8)\n#define BIT_H2C_SPACE_VLD_8197F BIT(3)\n#define BIT_H2C_WR_ADDR_RST_8197F BIT(2)\n\n#define BIT_SHIFT_H2C_LEN_SEL_8197F 0\n#define BIT_MASK_H2C_LEN_SEL_8197F 0x3\n#define BIT_H2C_LEN_SEL_8197F(x)                                               \\\n\t(((x) & BIT_MASK_H2C_LEN_SEL_8197F) << BIT_SHIFT_H2C_LEN_SEL_8197F)\n#define BITS_H2C_LEN_SEL_8197F                                                 \\\n\t(BIT_MASK_H2C_LEN_SEL_8197F << BIT_SHIFT_H2C_LEN_SEL_8197F)\n#define BIT_CLEAR_H2C_LEN_SEL_8197F(x) ((x) & (~BITS_H2C_LEN_SEL_8197F))\n#define BIT_GET_H2C_LEN_SEL_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_H2C_LEN_SEL_8197F) & BIT_MASK_H2C_LEN_SEL_8197F)\n#define BIT_SET_H2C_LEN_SEL_8197F(x, v)                                        \\\n\t(BIT_CLEAR_H2C_LEN_SEL_8197F(x) | BIT_H2C_LEN_SEL_8197F(v))\n\n#define BIT_SHIFT_VI_PUB_LIMIT_8197F 16\n#define BIT_MASK_VI_PUB_LIMIT_8197F 0xfff\n#define BIT_VI_PUB_LIMIT_8197F(x)                                              \\\n\t(((x) & BIT_MASK_VI_PUB_LIMIT_8197F) << BIT_SHIFT_VI_PUB_LIMIT_8197F)\n#define BITS_VI_PUB_LIMIT_8197F                                                \\\n\t(BIT_MASK_VI_PUB_LIMIT_8197F << BIT_SHIFT_VI_PUB_LIMIT_8197F)\n#define BIT_CLEAR_VI_PUB_LIMIT_8197F(x) ((x) & (~BITS_VI_PUB_LIMIT_8197F))\n#define BIT_GET_VI_PUB_LIMIT_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_VI_PUB_LIMIT_8197F) & BIT_MASK_VI_PUB_LIMIT_8197F)\n#define BIT_SET_VI_PUB_LIMIT_8197F(x, v)                                       \\\n\t(BIT_CLEAR_VI_PUB_LIMIT_8197F(x) | BIT_VI_PUB_LIMIT_8197F(v))\n\n#define BIT_SHIFT_VO_PUB_LIMIT_8197F 0\n#define BIT_MASK_VO_PUB_LIMIT_8197F 0xfff\n#define BIT_VO_PUB_LIMIT_8197F(x)                                              \\\n\t(((x) & BIT_MASK_VO_PUB_LIMIT_8197F) << BIT_SHIFT_VO_PUB_LIMIT_8197F)\n#define BITS_VO_PUB_LIMIT_8197F                                                \\\n\t(BIT_MASK_VO_PUB_LIMIT_8197F << BIT_SHIFT_VO_PUB_LIMIT_8197F)\n#define BIT_CLEAR_VO_PUB_LIMIT_8197F(x) ((x) & (~BITS_VO_PUB_LIMIT_8197F))\n#define BIT_GET_VO_PUB_LIMIT_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_VO_PUB_LIMIT_8197F) & BIT_MASK_VO_PUB_LIMIT_8197F)\n#define BIT_SET_VO_PUB_LIMIT_8197F(x, v)                                       \\\n\t(BIT_CLEAR_VO_PUB_LIMIT_8197F(x) | BIT_VO_PUB_LIMIT_8197F(v))\n\n#define BIT_SHIFT_BK_PUB_LIMIT_8197F 16\n#define BIT_MASK_BK_PUB_LIMIT_8197F 0xfff\n#define BIT_BK_PUB_LIMIT_8197F(x)                                              \\\n\t(((x) & BIT_MASK_BK_PUB_LIMIT_8197F) << BIT_SHIFT_BK_PUB_LIMIT_8197F)\n#define BITS_BK_PUB_LIMIT_8197F                                                \\\n\t(BIT_MASK_BK_PUB_LIMIT_8197F << BIT_SHIFT_BK_PUB_LIMIT_8197F)\n#define BIT_CLEAR_BK_PUB_LIMIT_8197F(x) ((x) & (~BITS_BK_PUB_LIMIT_8197F))\n#define BIT_GET_BK_PUB_LIMIT_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_BK_PUB_LIMIT_8197F) & BIT_MASK_BK_PUB_LIMIT_8197F)\n#define BIT_SET_BK_PUB_LIMIT_8197F(x, v)                                       \\\n\t(BIT_CLEAR_BK_PUB_LIMIT_8197F(x) | BIT_BK_PUB_LIMIT_8197F(v))\n\n#define BIT_SHIFT_BE_PUB_LIMIT_8197F 0\n#define BIT_MASK_BE_PUB_LIMIT_8197F 0xfff\n#define BIT_BE_PUB_LIMIT_8197F(x)                                              \\\n\t(((x) & BIT_MASK_BE_PUB_LIMIT_8197F) << BIT_SHIFT_BE_PUB_LIMIT_8197F)\n#define BITS_BE_PUB_LIMIT_8197F                                                \\\n\t(BIT_MASK_BE_PUB_LIMIT_8197F << BIT_SHIFT_BE_PUB_LIMIT_8197F)\n#define BIT_CLEAR_BE_PUB_LIMIT_8197F(x) ((x) & (~BITS_BE_PUB_LIMIT_8197F))\n#define BIT_GET_BE_PUB_LIMIT_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_BE_PUB_LIMIT_8197F) & BIT_MASK_BE_PUB_LIMIT_8197F)\n#define BIT_SET_BE_PUB_LIMIT_8197F(x, v)                                       \\\n\t(BIT_CLEAR_BE_PUB_LIMIT_8197F(x) | BIT_BE_PUB_LIMIT_8197F(v))\n\n/* 2 REG_RXDMA_AGG_PG_TH_8197F */\n#define BIT_DMA_STORE_MODE_8197F BIT(31)\n#define BIT_EN_FW_ADD_8197F BIT(30)\n#define BIT_EN_PRE_CALC_8197F BIT(29)\n#define BIT_RXAGG_SW_EN_8197F BIT(28)\n\n#define BIT_SHIFT_PKT_NUM_WOL_8197F 16\n#define BIT_MASK_PKT_NUM_WOL_8197F 0xff\n#define BIT_PKT_NUM_WOL_8197F(x)                                               \\\n\t(((x) & BIT_MASK_PKT_NUM_WOL_8197F) << BIT_SHIFT_PKT_NUM_WOL_8197F)\n#define BITS_PKT_NUM_WOL_8197F                                                 \\\n\t(BIT_MASK_PKT_NUM_WOL_8197F << BIT_SHIFT_PKT_NUM_WOL_8197F)\n#define BIT_CLEAR_PKT_NUM_WOL_8197F(x) ((x) & (~BITS_PKT_NUM_WOL_8197F))\n#define BIT_GET_PKT_NUM_WOL_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_WOL_8197F) & BIT_MASK_PKT_NUM_WOL_8197F)\n#define BIT_SET_PKT_NUM_WOL_8197F(x, v)                                        \\\n\t(BIT_CLEAR_PKT_NUM_WOL_8197F(x) | BIT_PKT_NUM_WOL_8197F(v))\n\n#define BIT_SHIFT_DMA_AGG_TO_V1_8197F 8\n#define BIT_MASK_DMA_AGG_TO_V1_8197F 0xff\n#define BIT_DMA_AGG_TO_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_DMA_AGG_TO_V1_8197F) << BIT_SHIFT_DMA_AGG_TO_V1_8197F)\n#define BITS_DMA_AGG_TO_V1_8197F                                               \\\n\t(BIT_MASK_DMA_AGG_TO_V1_8197F << BIT_SHIFT_DMA_AGG_TO_V1_8197F)\n#define BIT_CLEAR_DMA_AGG_TO_V1_8197F(x) ((x) & (~BITS_DMA_AGG_TO_V1_8197F))\n#define BIT_GET_DMA_AGG_TO_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8197F) & BIT_MASK_DMA_AGG_TO_V1_8197F)\n#define BIT_SET_DMA_AGG_TO_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_DMA_AGG_TO_V1_8197F(x) | BIT_DMA_AGG_TO_V1_8197F(v))\n\n#define BIT_SHIFT_RXDMA_AGG_PG_TH_8197F 0\n#define BIT_MASK_RXDMA_AGG_PG_TH_8197F 0xff\n#define BIT_RXDMA_AGG_PG_TH_8197F(x)                                           \\\n\t(((x) & BIT_MASK_RXDMA_AGG_PG_TH_8197F)                                \\\n\t << BIT_SHIFT_RXDMA_AGG_PG_TH_8197F)\n#define BITS_RXDMA_AGG_PG_TH_8197F                                             \\\n\t(BIT_MASK_RXDMA_AGG_PG_TH_8197F << BIT_SHIFT_RXDMA_AGG_PG_TH_8197F)\n#define BIT_CLEAR_RXDMA_AGG_PG_TH_8197F(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8197F))\n#define BIT_GET_RXDMA_AGG_PG_TH_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) &                            \\\n\t BIT_MASK_RXDMA_AGG_PG_TH_8197F)\n#define BIT_SET_RXDMA_AGG_PG_TH_8197F(x, v)                                    \\\n\t(BIT_CLEAR_RXDMA_AGG_PG_TH_8197F(x) | BIT_RXDMA_AGG_PG_TH_8197F(v))\n\n/* 2 REG_RXPKT_NUM_8197F */\n\n#define BIT_SHIFT_RXPKT_NUM_8197F 24\n#define BIT_MASK_RXPKT_NUM_8197F 0xff\n#define BIT_RXPKT_NUM_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_RXPKT_NUM_8197F) << BIT_SHIFT_RXPKT_NUM_8197F)\n#define BITS_RXPKT_NUM_8197F                                                   \\\n\t(BIT_MASK_RXPKT_NUM_8197F << BIT_SHIFT_RXPKT_NUM_8197F)\n#define BIT_CLEAR_RXPKT_NUM_8197F(x) ((x) & (~BITS_RXPKT_NUM_8197F))\n#define BIT_GET_RXPKT_NUM_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_RXPKT_NUM_8197F) & BIT_MASK_RXPKT_NUM_8197F)\n#define BIT_SET_RXPKT_NUM_8197F(x, v)                                          \\\n\t(BIT_CLEAR_RXPKT_NUM_8197F(x) | BIT_RXPKT_NUM_8197F(v))\n\n#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F 20\n#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F 0xf\n#define BIT_FW_UPD_RDPTR19_TO_16_8197F(x)                                      \\\n\t(((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F)                           \\\n\t << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F)\n#define BITS_FW_UPD_RDPTR19_TO_16_8197F                                        \\\n\t(BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F                                   \\\n\t << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F)\n#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8197F(x)                                \\\n\t((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8197F))\n#define BIT_GET_FW_UPD_RDPTR19_TO_16_8197F(x)                                  \\\n\t(((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) &                       \\\n\t BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F)\n#define BIT_SET_FW_UPD_RDPTR19_TO_16_8197F(x, v)                               \\\n\t(BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8197F(x) |                             \\\n\t BIT_FW_UPD_RDPTR19_TO_16_8197F(v))\n\n#define BIT_RXDMA_REQ_8197F BIT(19)\n#define BIT_RW_RELEASE_EN_8197F BIT(18)\n#define BIT_RXDMA_IDLE_8197F BIT(17)\n#define BIT_RXPKT_RELEASE_POLL_8197F BIT(16)\n\n#define BIT_SHIFT_FW_UPD_RDPTR_8197F 0\n#define BIT_MASK_FW_UPD_RDPTR_8197F 0xffff\n#define BIT_FW_UPD_RDPTR_8197F(x)                                              \\\n\t(((x) & BIT_MASK_FW_UPD_RDPTR_8197F) << BIT_SHIFT_FW_UPD_RDPTR_8197F)\n#define BITS_FW_UPD_RDPTR_8197F                                                \\\n\t(BIT_MASK_FW_UPD_RDPTR_8197F << BIT_SHIFT_FW_UPD_RDPTR_8197F)\n#define BIT_CLEAR_FW_UPD_RDPTR_8197F(x) ((x) & (~BITS_FW_UPD_RDPTR_8197F))\n#define BIT_GET_FW_UPD_RDPTR_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_FW_UPD_RDPTR_8197F) & BIT_MASK_FW_UPD_RDPTR_8197F)\n#define BIT_SET_FW_UPD_RDPTR_8197F(x, v)                                       \\\n\t(BIT_CLEAR_FW_UPD_RDPTR_8197F(x) | BIT_FW_UPD_RDPTR_8197F(v))\n\n/* 2 REG_RXDMA_STATUS_8197F */\n#define BIT_FC2H_PKT_OVERFLOW_8197F BIT(8)\n#define BIT_C2H_PKT_OVF_8197F BIT(7)\n#define BIT_AGG_CONFGI_ISSUE_8197F BIT(6)\n#define BIT_FW_POLL_ISSUE_8197F BIT(5)\n#define BIT_RX_DATA_UDN_8197F BIT(4)\n#define BIT_RX_SFF_UDN_8197F BIT(3)\n#define BIT_RX_SFF_OVF_8197F BIT(2)\n#define BIT_RXPKT_OVF_8197F BIT(0)\n\n/* 2 REG_RXDMA_DPR_8197F */\n\n#define BIT_SHIFT_RDE_DEBUG_8197F 0\n#define BIT_MASK_RDE_DEBUG_8197F 0xffffffffL\n#define BIT_RDE_DEBUG_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_RDE_DEBUG_8197F) << BIT_SHIFT_RDE_DEBUG_8197F)\n#define BITS_RDE_DEBUG_8197F                                                   \\\n\t(BIT_MASK_RDE_DEBUG_8197F << BIT_SHIFT_RDE_DEBUG_8197F)\n#define BIT_CLEAR_RDE_DEBUG_8197F(x) ((x) & (~BITS_RDE_DEBUG_8197F))\n#define BIT_GET_RDE_DEBUG_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_RDE_DEBUG_8197F) & BIT_MASK_RDE_DEBUG_8197F)\n#define BIT_SET_RDE_DEBUG_8197F(x, v)                                          \\\n\t(BIT_CLEAR_RDE_DEBUG_8197F(x) | BIT_RDE_DEBUG_8197F(v))\n\n/* 2 REG_RXDMA_MODE_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n#define BIT_EN_SPD_8197F BIT(6)\n\n#define BIT_SHIFT_BURST_SIZE_8197F 4\n#define BIT_MASK_BURST_SIZE_8197F 0x3\n#define BIT_BURST_SIZE_8197F(x)                                                \\\n\t(((x) & BIT_MASK_BURST_SIZE_8197F) << BIT_SHIFT_BURST_SIZE_8197F)\n#define BITS_BURST_SIZE_8197F                                                  \\\n\t(BIT_MASK_BURST_SIZE_8197F << BIT_SHIFT_BURST_SIZE_8197F)\n#define BIT_CLEAR_BURST_SIZE_8197F(x) ((x) & (~BITS_BURST_SIZE_8197F))\n#define BIT_GET_BURST_SIZE_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_BURST_SIZE_8197F) & BIT_MASK_BURST_SIZE_8197F)\n#define BIT_SET_BURST_SIZE_8197F(x, v)                                         \\\n\t(BIT_CLEAR_BURST_SIZE_8197F(x) | BIT_BURST_SIZE_8197F(v))\n\n#define BIT_SHIFT_BURST_CNT_8197F 2\n#define BIT_MASK_BURST_CNT_8197F 0x3\n#define BIT_BURST_CNT_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_BURST_CNT_8197F) << BIT_SHIFT_BURST_CNT_8197F)\n#define BITS_BURST_CNT_8197F                                                   \\\n\t(BIT_MASK_BURST_CNT_8197F << BIT_SHIFT_BURST_CNT_8197F)\n#define BIT_CLEAR_BURST_CNT_8197F(x) ((x) & (~BITS_BURST_CNT_8197F))\n#define BIT_GET_BURST_CNT_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_BURST_CNT_8197F) & BIT_MASK_BURST_CNT_8197F)\n#define BIT_SET_BURST_CNT_8197F(x, v)                                          \\\n\t(BIT_CLEAR_BURST_CNT_8197F(x) | BIT_BURST_CNT_8197F(v))\n\n#define BIT_DMA_MODE_8197F BIT(1)\n\n/* 2 REG_C2H_PKT_8197F */\n\n#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F 24\n#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F 0xf\n#define BIT_R_C2H_STR_ADDR_16_TO_19_8197F(x)                                   \\\n\t(((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F)                        \\\n\t << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F)\n#define BITS_R_C2H_STR_ADDR_16_TO_19_8197F                                     \\\n\t(BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F                                \\\n\t << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F)\n#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8197F(x)                             \\\n\t((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8197F))\n#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8197F(x)                               \\\n\t(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) &                    \\\n\t BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F)\n#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8197F(x, v)                            \\\n\t(BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8197F(x) |                          \\\n\t BIT_R_C2H_STR_ADDR_16_TO_19_8197F(v))\n\n#define BIT_R_C2H_PKT_REQ_8197F BIT(16)\n\n#define BIT_SHIFT_R_C2H_STR_ADDR_8197F 0\n#define BIT_MASK_R_C2H_STR_ADDR_8197F 0xffff\n#define BIT_R_C2H_STR_ADDR_8197F(x)                                            \\\n\t(((x) & BIT_MASK_R_C2H_STR_ADDR_8197F)                                 \\\n\t << BIT_SHIFT_R_C2H_STR_ADDR_8197F)\n#define BITS_R_C2H_STR_ADDR_8197F                                              \\\n\t(BIT_MASK_R_C2H_STR_ADDR_8197F << BIT_SHIFT_R_C2H_STR_ADDR_8197F)\n#define BIT_CLEAR_R_C2H_STR_ADDR_8197F(x) ((x) & (~BITS_R_C2H_STR_ADDR_8197F))\n#define BIT_GET_R_C2H_STR_ADDR_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8197F) &                             \\\n\t BIT_MASK_R_C2H_STR_ADDR_8197F)\n#define BIT_SET_R_C2H_STR_ADDR_8197F(x, v)                                     \\\n\t(BIT_CLEAR_R_C2H_STR_ADDR_8197F(x) | BIT_R_C2H_STR_ADDR_8197F(v))\n\n/* 2 REG_FWFF_C2H_8197F */\n\n#define BIT_SHIFT_C2H_DMA_ADDR_8197F 0\n#define BIT_MASK_C2H_DMA_ADDR_8197F 0x3ffff\n#define BIT_C2H_DMA_ADDR_8197F(x)                                              \\\n\t(((x) & BIT_MASK_C2H_DMA_ADDR_8197F) << BIT_SHIFT_C2H_DMA_ADDR_8197F)\n#define BITS_C2H_DMA_ADDR_8197F                                                \\\n\t(BIT_MASK_C2H_DMA_ADDR_8197F << BIT_SHIFT_C2H_DMA_ADDR_8197F)\n#define BIT_CLEAR_C2H_DMA_ADDR_8197F(x) ((x) & (~BITS_C2H_DMA_ADDR_8197F))\n#define BIT_GET_C2H_DMA_ADDR_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_C2H_DMA_ADDR_8197F) & BIT_MASK_C2H_DMA_ADDR_8197F)\n#define BIT_SET_C2H_DMA_ADDR_8197F(x, v)                                       \\\n\t(BIT_CLEAR_C2H_DMA_ADDR_8197F(x) | BIT_C2H_DMA_ADDR_8197F(v))\n\n/* 2 REG_FWFF_CTRL_8197F */\n#define BIT_FWFF_DMAPKT_REQ_8197F BIT(31)\n\n#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F 16\n#define BIT_MASK_FWFF_DMA_PKT_NUM_8197F 0xff\n#define BIT_FWFF_DMA_PKT_NUM_8197F(x)                                          \\\n\t(((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8197F)                               \\\n\t << BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F)\n#define BITS_FWFF_DMA_PKT_NUM_8197F                                            \\\n\t(BIT_MASK_FWFF_DMA_PKT_NUM_8197F << BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F)\n#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8197F(x)                                    \\\n\t((x) & (~BITS_FWFF_DMA_PKT_NUM_8197F))\n#define BIT_GET_FWFF_DMA_PKT_NUM_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) &                           \\\n\t BIT_MASK_FWFF_DMA_PKT_NUM_8197F)\n#define BIT_SET_FWFF_DMA_PKT_NUM_8197F(x, v)                                   \\\n\t(BIT_CLEAR_FWFF_DMA_PKT_NUM_8197F(x) | BIT_FWFF_DMA_PKT_NUM_8197F(v))\n\n#define BIT_SHIFT_FWFF_STR_ADDR_8197F 0\n#define BIT_MASK_FWFF_STR_ADDR_8197F 0xffff\n#define BIT_FWFF_STR_ADDR_8197F(x)                                             \\\n\t(((x) & BIT_MASK_FWFF_STR_ADDR_8197F) << BIT_SHIFT_FWFF_STR_ADDR_8197F)\n#define BITS_FWFF_STR_ADDR_8197F                                               \\\n\t(BIT_MASK_FWFF_STR_ADDR_8197F << BIT_SHIFT_FWFF_STR_ADDR_8197F)\n#define BIT_CLEAR_FWFF_STR_ADDR_8197F(x) ((x) & (~BITS_FWFF_STR_ADDR_8197F))\n#define BIT_GET_FWFF_STR_ADDR_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_FWFF_STR_ADDR_8197F) & BIT_MASK_FWFF_STR_ADDR_8197F)\n#define BIT_SET_FWFF_STR_ADDR_8197F(x, v)                                      \\\n\t(BIT_CLEAR_FWFF_STR_ADDR_8197F(x) | BIT_FWFF_STR_ADDR_8197F(v))\n\n/* 2 REG_FWFF_PKT_INFO_8197F */\n\n#define BIT_SHIFT_FWFF_PKT_QUEUED_8197F 16\n#define BIT_MASK_FWFF_PKT_QUEUED_8197F 0xff\n#define BIT_FWFF_PKT_QUEUED_8197F(x)                                           \\\n\t(((x) & BIT_MASK_FWFF_PKT_QUEUED_8197F)                                \\\n\t << BIT_SHIFT_FWFF_PKT_QUEUED_8197F)\n#define BITS_FWFF_PKT_QUEUED_8197F                                             \\\n\t(BIT_MASK_FWFF_PKT_QUEUED_8197F << BIT_SHIFT_FWFF_PKT_QUEUED_8197F)\n#define BIT_CLEAR_FWFF_PKT_QUEUED_8197F(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8197F))\n#define BIT_GET_FWFF_PKT_QUEUED_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8197F) &                            \\\n\t BIT_MASK_FWFF_PKT_QUEUED_8197F)\n#define BIT_SET_FWFF_PKT_QUEUED_8197F(x, v)                                    \\\n\t(BIT_CLEAR_FWFF_PKT_QUEUED_8197F(x) | BIT_FWFF_PKT_QUEUED_8197F(v))\n\n#define BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F 0\n#define BIT_MASK_FWFF_PKT_STR_ADDR_8197F 0xffff\n#define BIT_FWFF_PKT_STR_ADDR_8197F(x)                                         \\\n\t(((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8197F)                              \\\n\t << BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F)\n#define BITS_FWFF_PKT_STR_ADDR_8197F                                           \\\n\t(BIT_MASK_FWFF_PKT_STR_ADDR_8197F << BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F)\n#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8197F(x)                                   \\\n\t((x) & (~BITS_FWFF_PKT_STR_ADDR_8197F))\n#define BIT_GET_FWFF_PKT_STR_ADDR_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) &                          \\\n\t BIT_MASK_FWFF_PKT_STR_ADDR_8197F)\n#define BIT_SET_FWFF_PKT_STR_ADDR_8197F(x, v)                                  \\\n\t(BIT_CLEAR_FWFF_PKT_STR_ADDR_8197F(x) | BIT_FWFF_PKT_STR_ADDR_8197F(v))\n\n/* 2 REG_FC2H_INFO_8197F */\n#define BIT_FC2H_PKT_REQ_8197F BIT(16)\n\n#define BIT_SHIFT_FC2H_STR_ADDR_8197F 0\n#define BIT_MASK_FC2H_STR_ADDR_8197F 0xffff\n#define BIT_FC2H_STR_ADDR_8197F(x)                                             \\\n\t(((x) & BIT_MASK_FC2H_STR_ADDR_8197F) << BIT_SHIFT_FC2H_STR_ADDR_8197F)\n#define BITS_FC2H_STR_ADDR_8197F                                               \\\n\t(BIT_MASK_FC2H_STR_ADDR_8197F << BIT_SHIFT_FC2H_STR_ADDR_8197F)\n#define BIT_CLEAR_FC2H_STR_ADDR_8197F(x) ((x) & (~BITS_FC2H_STR_ADDR_8197F))\n#define BIT_GET_FC2H_STR_ADDR_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_FC2H_STR_ADDR_8197F) & BIT_MASK_FC2H_STR_ADDR_8197F)\n#define BIT_SET_FC2H_STR_ADDR_8197F(x, v)                                      \\\n\t(BIT_CLEAR_FC2H_STR_ADDR_8197F(x) | BIT_FC2H_STR_ADDR_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_DDMA_CH0SA_8197F */\n\n#define BIT_SHIFT_DDMACH0_SA_8197F 0\n#define BIT_MASK_DDMACH0_SA_8197F 0xffffffffL\n#define BIT_DDMACH0_SA_8197F(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH0_SA_8197F) << BIT_SHIFT_DDMACH0_SA_8197F)\n#define BITS_DDMACH0_SA_8197F                                                  \\\n\t(BIT_MASK_DDMACH0_SA_8197F << BIT_SHIFT_DDMACH0_SA_8197F)\n#define BIT_CLEAR_DDMACH0_SA_8197F(x) ((x) & (~BITS_DDMACH0_SA_8197F))\n#define BIT_GET_DDMACH0_SA_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH0_SA_8197F) & BIT_MASK_DDMACH0_SA_8197F)\n#define BIT_SET_DDMACH0_SA_8197F(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH0_SA_8197F(x) | BIT_DDMACH0_SA_8197F(v))\n\n/* 2 REG_DDMA_CH0DA_8197F */\n\n#define BIT_SHIFT_DDMACH0_DA_8197F 0\n#define BIT_MASK_DDMACH0_DA_8197F 0xffffffffL\n#define BIT_DDMACH0_DA_8197F(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH0_DA_8197F) << BIT_SHIFT_DDMACH0_DA_8197F)\n#define BITS_DDMACH0_DA_8197F                                                  \\\n\t(BIT_MASK_DDMACH0_DA_8197F << BIT_SHIFT_DDMACH0_DA_8197F)\n#define BIT_CLEAR_DDMACH0_DA_8197F(x) ((x) & (~BITS_DDMACH0_DA_8197F))\n#define BIT_GET_DDMACH0_DA_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH0_DA_8197F) & BIT_MASK_DDMACH0_DA_8197F)\n#define BIT_SET_DDMACH0_DA_8197F(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH0_DA_8197F(x) | BIT_DDMACH0_DA_8197F(v))\n\n/* 2 REG_DDMA_CH0CTRL_8197F */\n#define BIT_DDMACH0_OWN_8197F BIT(31)\n#define BIT_DDMACH0_CHKSUM_EN_8197F BIT(29)\n#define BIT_DDMACH0_DA_W_DISABLE_8197F BIT(28)\n#define BIT_DDMACH0_CHKSUM_STS_8197F BIT(27)\n#define BIT_DDMACH0_DDMA_MODE_8197F BIT(26)\n#define BIT_DDMACH0_RESET_CHKSUM_STS_8197F BIT(25)\n#define BIT_DDMACH0_CHKSUM_CONT_8197F BIT(24)\n\n#define BIT_SHIFT_DDMACH0_DLEN_8197F 0\n#define BIT_MASK_DDMACH0_DLEN_8197F 0x3ffff\n#define BIT_DDMACH0_DLEN_8197F(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH0_DLEN_8197F) << BIT_SHIFT_DDMACH0_DLEN_8197F)\n#define BITS_DDMACH0_DLEN_8197F                                                \\\n\t(BIT_MASK_DDMACH0_DLEN_8197F << BIT_SHIFT_DDMACH0_DLEN_8197F)\n#define BIT_CLEAR_DDMACH0_DLEN_8197F(x) ((x) & (~BITS_DDMACH0_DLEN_8197F))\n#define BIT_GET_DDMACH0_DLEN_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH0_DLEN_8197F) & BIT_MASK_DDMACH0_DLEN_8197F)\n#define BIT_SET_DDMACH0_DLEN_8197F(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH0_DLEN_8197F(x) | BIT_DDMACH0_DLEN_8197F(v))\n\n/* 2 REG_DDMA_CH1SA_8197F */\n\n#define BIT_SHIFT_DDMACH1_SA_8197F 0\n#define BIT_MASK_DDMACH1_SA_8197F 0xffffffffL\n#define BIT_DDMACH1_SA_8197F(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH1_SA_8197F) << BIT_SHIFT_DDMACH1_SA_8197F)\n#define BITS_DDMACH1_SA_8197F                                                  \\\n\t(BIT_MASK_DDMACH1_SA_8197F << BIT_SHIFT_DDMACH1_SA_8197F)\n#define BIT_CLEAR_DDMACH1_SA_8197F(x) ((x) & (~BITS_DDMACH1_SA_8197F))\n#define BIT_GET_DDMACH1_SA_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH1_SA_8197F) & BIT_MASK_DDMACH1_SA_8197F)\n#define BIT_SET_DDMACH1_SA_8197F(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH1_SA_8197F(x) | BIT_DDMACH1_SA_8197F(v))\n\n/* 2 REG_DDMA_CH1DA_8197F */\n\n#define BIT_SHIFT_DDMACH1_DA_8197F 0\n#define BIT_MASK_DDMACH1_DA_8197F 0xffffffffL\n#define BIT_DDMACH1_DA_8197F(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH1_DA_8197F) << BIT_SHIFT_DDMACH1_DA_8197F)\n#define BITS_DDMACH1_DA_8197F                                                  \\\n\t(BIT_MASK_DDMACH1_DA_8197F << BIT_SHIFT_DDMACH1_DA_8197F)\n#define BIT_CLEAR_DDMACH1_DA_8197F(x) ((x) & (~BITS_DDMACH1_DA_8197F))\n#define BIT_GET_DDMACH1_DA_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH1_DA_8197F) & BIT_MASK_DDMACH1_DA_8197F)\n#define BIT_SET_DDMACH1_DA_8197F(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH1_DA_8197F(x) | BIT_DDMACH1_DA_8197F(v))\n\n/* 2 REG_DDMA_CH1CTRL_8197F */\n#define BIT_DDMACH1_OWN_8197F BIT(31)\n#define BIT_DDMACH1_CHKSUM_EN_8197F BIT(29)\n#define BIT_DDMACH1_DA_W_DISABLE_8197F BIT(28)\n#define BIT_DDMACH1_CHKSUM_STS_8197F BIT(27)\n#define BIT_DDMACH1_DDMA_MODE_8197F BIT(26)\n#define BIT_DDMACH1_RESET_CHKSUM_STS_8197F BIT(25)\n#define BIT_DDMACH1_CHKSUM_CONT_8197F BIT(24)\n\n#define BIT_SHIFT_DDMACH1_DLEN_8197F 0\n#define BIT_MASK_DDMACH1_DLEN_8197F 0x3ffff\n#define BIT_DDMACH1_DLEN_8197F(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH1_DLEN_8197F) << BIT_SHIFT_DDMACH1_DLEN_8197F)\n#define BITS_DDMACH1_DLEN_8197F                                                \\\n\t(BIT_MASK_DDMACH1_DLEN_8197F << BIT_SHIFT_DDMACH1_DLEN_8197F)\n#define BIT_CLEAR_DDMACH1_DLEN_8197F(x) ((x) & (~BITS_DDMACH1_DLEN_8197F))\n#define BIT_GET_DDMACH1_DLEN_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH1_DLEN_8197F) & BIT_MASK_DDMACH1_DLEN_8197F)\n#define BIT_SET_DDMACH1_DLEN_8197F(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH1_DLEN_8197F(x) | BIT_DDMACH1_DLEN_8197F(v))\n\n/* 2 REG_DDMA_CH2SA_8197F */\n\n#define BIT_SHIFT_DDMACH2_SA_8197F 0\n#define BIT_MASK_DDMACH2_SA_8197F 0xffffffffL\n#define BIT_DDMACH2_SA_8197F(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH2_SA_8197F) << BIT_SHIFT_DDMACH2_SA_8197F)\n#define BITS_DDMACH2_SA_8197F                                                  \\\n\t(BIT_MASK_DDMACH2_SA_8197F << BIT_SHIFT_DDMACH2_SA_8197F)\n#define BIT_CLEAR_DDMACH2_SA_8197F(x) ((x) & (~BITS_DDMACH2_SA_8197F))\n#define BIT_GET_DDMACH2_SA_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH2_SA_8197F) & BIT_MASK_DDMACH2_SA_8197F)\n#define BIT_SET_DDMACH2_SA_8197F(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH2_SA_8197F(x) | BIT_DDMACH2_SA_8197F(v))\n\n/* 2 REG_DDMA_CH2DA_8197F */\n\n#define BIT_SHIFT_DDMACH2_DA_8197F 0\n#define BIT_MASK_DDMACH2_DA_8197F 0xffffffffL\n#define BIT_DDMACH2_DA_8197F(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH2_DA_8197F) << BIT_SHIFT_DDMACH2_DA_8197F)\n#define BITS_DDMACH2_DA_8197F                                                  \\\n\t(BIT_MASK_DDMACH2_DA_8197F << BIT_SHIFT_DDMACH2_DA_8197F)\n#define BIT_CLEAR_DDMACH2_DA_8197F(x) ((x) & (~BITS_DDMACH2_DA_8197F))\n#define BIT_GET_DDMACH2_DA_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH2_DA_8197F) & BIT_MASK_DDMACH2_DA_8197F)\n#define BIT_SET_DDMACH2_DA_8197F(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH2_DA_8197F(x) | BIT_DDMACH2_DA_8197F(v))\n\n/* 2 REG_DDMA_CH2CTRL_8197F */\n#define BIT_DDMACH2_OWN_8197F BIT(31)\n#define BIT_DDMACH2_CHKSUM_EN_8197F BIT(29)\n#define BIT_DDMACH2_DA_W_DISABLE_8197F BIT(28)\n#define BIT_DDMACH2_CHKSUM_STS_8197F BIT(27)\n#define BIT_DDMACH2_DDMA_MODE_8197F BIT(26)\n#define BIT_DDMACH2_RESET_CHKSUM_STS_8197F BIT(25)\n#define BIT_DDMACH2_CHKSUM_CONT_8197F BIT(24)\n\n#define BIT_SHIFT_DDMACH2_DLEN_8197F 0\n#define BIT_MASK_DDMACH2_DLEN_8197F 0x3ffff\n#define BIT_DDMACH2_DLEN_8197F(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH2_DLEN_8197F) << BIT_SHIFT_DDMACH2_DLEN_8197F)\n#define BITS_DDMACH2_DLEN_8197F                                                \\\n\t(BIT_MASK_DDMACH2_DLEN_8197F << BIT_SHIFT_DDMACH2_DLEN_8197F)\n#define BIT_CLEAR_DDMACH2_DLEN_8197F(x) ((x) & (~BITS_DDMACH2_DLEN_8197F))\n#define BIT_GET_DDMACH2_DLEN_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH2_DLEN_8197F) & BIT_MASK_DDMACH2_DLEN_8197F)\n#define BIT_SET_DDMACH2_DLEN_8197F(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH2_DLEN_8197F(x) | BIT_DDMACH2_DLEN_8197F(v))\n\n/* 2 REG_DDMA_CH3SA_8197F */\n\n#define BIT_SHIFT_DDMACH3_SA_8197F 0\n#define BIT_MASK_DDMACH3_SA_8197F 0xffffffffL\n#define BIT_DDMACH3_SA_8197F(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH3_SA_8197F) << BIT_SHIFT_DDMACH3_SA_8197F)\n#define BITS_DDMACH3_SA_8197F                                                  \\\n\t(BIT_MASK_DDMACH3_SA_8197F << BIT_SHIFT_DDMACH3_SA_8197F)\n#define BIT_CLEAR_DDMACH3_SA_8197F(x) ((x) & (~BITS_DDMACH3_SA_8197F))\n#define BIT_GET_DDMACH3_SA_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH3_SA_8197F) & BIT_MASK_DDMACH3_SA_8197F)\n#define BIT_SET_DDMACH3_SA_8197F(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH3_SA_8197F(x) | BIT_DDMACH3_SA_8197F(v))\n\n/* 2 REG_DDMA_CH3DA_8197F */\n\n#define BIT_SHIFT_DDMACH3_DA_8197F 0\n#define BIT_MASK_DDMACH3_DA_8197F 0xffffffffL\n#define BIT_DDMACH3_DA_8197F(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH3_DA_8197F) << BIT_SHIFT_DDMACH3_DA_8197F)\n#define BITS_DDMACH3_DA_8197F                                                  \\\n\t(BIT_MASK_DDMACH3_DA_8197F << BIT_SHIFT_DDMACH3_DA_8197F)\n#define BIT_CLEAR_DDMACH3_DA_8197F(x) ((x) & (~BITS_DDMACH3_DA_8197F))\n#define BIT_GET_DDMACH3_DA_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH3_DA_8197F) & BIT_MASK_DDMACH3_DA_8197F)\n#define BIT_SET_DDMACH3_DA_8197F(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH3_DA_8197F(x) | BIT_DDMACH3_DA_8197F(v))\n\n/* 2 REG_DDMA_CH3CTRL_8197F */\n#define BIT_DDMACH3_OWN_8197F BIT(31)\n#define BIT_DDMACH3_CHKSUM_EN_8197F BIT(29)\n#define BIT_DDMACH3_DA_W_DISABLE_8197F BIT(28)\n#define BIT_DDMACH3_CHKSUM_STS_8197F BIT(27)\n#define BIT_DDMACH3_DDMA_MODE_8197F BIT(26)\n#define BIT_DDMACH3_RESET_CHKSUM_STS_8197F BIT(25)\n#define BIT_DDMACH3_CHKSUM_CONT_8197F BIT(24)\n\n#define BIT_SHIFT_DDMACH3_DLEN_8197F 0\n#define BIT_MASK_DDMACH3_DLEN_8197F 0x3ffff\n#define BIT_DDMACH3_DLEN_8197F(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH3_DLEN_8197F) << BIT_SHIFT_DDMACH3_DLEN_8197F)\n#define BITS_DDMACH3_DLEN_8197F                                                \\\n\t(BIT_MASK_DDMACH3_DLEN_8197F << BIT_SHIFT_DDMACH3_DLEN_8197F)\n#define BIT_CLEAR_DDMACH3_DLEN_8197F(x) ((x) & (~BITS_DDMACH3_DLEN_8197F))\n#define BIT_GET_DDMACH3_DLEN_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH3_DLEN_8197F) & BIT_MASK_DDMACH3_DLEN_8197F)\n#define BIT_SET_DDMACH3_DLEN_8197F(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH3_DLEN_8197F(x) | BIT_DDMACH3_DLEN_8197F(v))\n\n/* 2 REG_DDMA_CH4SA_8197F */\n\n#define BIT_SHIFT_DDMACH4_SA_8197F 0\n#define BIT_MASK_DDMACH4_SA_8197F 0xffffffffL\n#define BIT_DDMACH4_SA_8197F(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH4_SA_8197F) << BIT_SHIFT_DDMACH4_SA_8197F)\n#define BITS_DDMACH4_SA_8197F                                                  \\\n\t(BIT_MASK_DDMACH4_SA_8197F << BIT_SHIFT_DDMACH4_SA_8197F)\n#define BIT_CLEAR_DDMACH4_SA_8197F(x) ((x) & (~BITS_DDMACH4_SA_8197F))\n#define BIT_GET_DDMACH4_SA_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH4_SA_8197F) & BIT_MASK_DDMACH4_SA_8197F)\n#define BIT_SET_DDMACH4_SA_8197F(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH4_SA_8197F(x) | BIT_DDMACH4_SA_8197F(v))\n\n/* 2 REG_DDMA_CH4DA_8197F */\n\n#define BIT_SHIFT_DDMACH4_DA_8197F 0\n#define BIT_MASK_DDMACH4_DA_8197F 0xffffffffL\n#define BIT_DDMACH4_DA_8197F(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH4_DA_8197F) << BIT_SHIFT_DDMACH4_DA_8197F)\n#define BITS_DDMACH4_DA_8197F                                                  \\\n\t(BIT_MASK_DDMACH4_DA_8197F << BIT_SHIFT_DDMACH4_DA_8197F)\n#define BIT_CLEAR_DDMACH4_DA_8197F(x) ((x) & (~BITS_DDMACH4_DA_8197F))\n#define BIT_GET_DDMACH4_DA_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH4_DA_8197F) & BIT_MASK_DDMACH4_DA_8197F)\n#define BIT_SET_DDMACH4_DA_8197F(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH4_DA_8197F(x) | BIT_DDMACH4_DA_8197F(v))\n\n/* 2 REG_DDMA_CH4CTRL_8197F */\n#define BIT_DDMACH4_OWN_8197F BIT(31)\n#define BIT_DDMACH4_CHKSUM_EN_8197F BIT(29)\n#define BIT_DDMACH4_DA_W_DISABLE_8197F BIT(28)\n#define BIT_DDMACH4_CHKSUM_STS_8197F BIT(27)\n#define BIT_DDMACH4_DDMA_MODE_8197F BIT(26)\n#define BIT_DDMACH4_RESET_CHKSUM_STS_8197F BIT(25)\n#define BIT_DDMACH4_CHKSUM_CONT_8197F BIT(24)\n\n#define BIT_SHIFT_DDMACH4_DLEN_8197F 0\n#define BIT_MASK_DDMACH4_DLEN_8197F 0x3ffff\n#define BIT_DDMACH4_DLEN_8197F(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH4_DLEN_8197F) << BIT_SHIFT_DDMACH4_DLEN_8197F)\n#define BITS_DDMACH4_DLEN_8197F                                                \\\n\t(BIT_MASK_DDMACH4_DLEN_8197F << BIT_SHIFT_DDMACH4_DLEN_8197F)\n#define BIT_CLEAR_DDMACH4_DLEN_8197F(x) ((x) & (~BITS_DDMACH4_DLEN_8197F))\n#define BIT_GET_DDMACH4_DLEN_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH4_DLEN_8197F) & BIT_MASK_DDMACH4_DLEN_8197F)\n#define BIT_SET_DDMACH4_DLEN_8197F(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH4_DLEN_8197F(x) | BIT_DDMACH4_DLEN_8197F(v))\n\n/* 2 REG_DDMA_CH5SA_8197F */\n\n#define BIT_SHIFT_DDMACH5_SA_8197F 0\n#define BIT_MASK_DDMACH5_SA_8197F 0xffffffffL\n#define BIT_DDMACH5_SA_8197F(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH5_SA_8197F) << BIT_SHIFT_DDMACH5_SA_8197F)\n#define BITS_DDMACH5_SA_8197F                                                  \\\n\t(BIT_MASK_DDMACH5_SA_8197F << BIT_SHIFT_DDMACH5_SA_8197F)\n#define BIT_CLEAR_DDMACH5_SA_8197F(x) ((x) & (~BITS_DDMACH5_SA_8197F))\n#define BIT_GET_DDMACH5_SA_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH5_SA_8197F) & BIT_MASK_DDMACH5_SA_8197F)\n#define BIT_SET_DDMACH5_SA_8197F(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH5_SA_8197F(x) | BIT_DDMACH5_SA_8197F(v))\n\n/* 2 REG_DDMA_CH5DA_8197F */\n\n#define BIT_SHIFT_DDMACH5_DA_8197F 0\n#define BIT_MASK_DDMACH5_DA_8197F 0xffffffffL\n#define BIT_DDMACH5_DA_8197F(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH5_DA_8197F) << BIT_SHIFT_DDMACH5_DA_8197F)\n#define BITS_DDMACH5_DA_8197F                                                  \\\n\t(BIT_MASK_DDMACH5_DA_8197F << BIT_SHIFT_DDMACH5_DA_8197F)\n#define BIT_CLEAR_DDMACH5_DA_8197F(x) ((x) & (~BITS_DDMACH5_DA_8197F))\n#define BIT_GET_DDMACH5_DA_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH5_DA_8197F) & BIT_MASK_DDMACH5_DA_8197F)\n#define BIT_SET_DDMACH5_DA_8197F(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH5_DA_8197F(x) | BIT_DDMACH5_DA_8197F(v))\n\n/* 2 REG_REG_DDMA_CH5CTRL_8197F */\n#define BIT_DDMACH5_OWN_8197F BIT(31)\n#define BIT_DDMACH5_CHKSUM_EN_8197F BIT(29)\n#define BIT_DDMACH5_DA_W_DISABLE_8197F BIT(28)\n#define BIT_DDMACH5_CHKSUM_STS_8197F BIT(27)\n#define BIT_DDMACH5_DDMA_MODE_8197F BIT(26)\n#define BIT_DDMACH5_RESET_CHKSUM_STS_8197F BIT(25)\n#define BIT_DDMACH5_CHKSUM_CONT_8197F BIT(24)\n\n#define BIT_SHIFT_DDMACH5_DLEN_8197F 0\n#define BIT_MASK_DDMACH5_DLEN_8197F 0x3ffff\n#define BIT_DDMACH5_DLEN_8197F(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH5_DLEN_8197F) << BIT_SHIFT_DDMACH5_DLEN_8197F)\n#define BITS_DDMACH5_DLEN_8197F                                                \\\n\t(BIT_MASK_DDMACH5_DLEN_8197F << BIT_SHIFT_DDMACH5_DLEN_8197F)\n#define BIT_CLEAR_DDMACH5_DLEN_8197F(x) ((x) & (~BITS_DDMACH5_DLEN_8197F))\n#define BIT_GET_DDMACH5_DLEN_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH5_DLEN_8197F) & BIT_MASK_DDMACH5_DLEN_8197F)\n#define BIT_SET_DDMACH5_DLEN_8197F(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH5_DLEN_8197F(x) | BIT_DDMACH5_DLEN_8197F(v))\n\n/* 2 REG_DDMA_INT_MSK_8197F */\n#define BIT_DDMACH5_MSK_8197F BIT(5)\n#define BIT_DDMACH4_MSK_8197F BIT(4)\n#define BIT_DDMACH3_MSK_8197F BIT(3)\n#define BIT_DDMACH2_MSK_8197F BIT(2)\n#define BIT_DDMACH1_MSK_8197F BIT(1)\n#define BIT_DDMACH0_MSK_8197F BIT(0)\n\n/* 2 REG_DDMA_CHSTATUS_8197F */\n#define BIT_DDMACH5_BUSY_8197F BIT(5)\n#define BIT_DDMACH4_BUSY_8197F BIT(4)\n#define BIT_DDMACH3_BUSY_8197F BIT(3)\n#define BIT_DDMACH2_BUSY_8197F BIT(2)\n#define BIT_DDMACH1_BUSY_8197F BIT(1)\n#define BIT_DDMACH0_BUSY_8197F BIT(0)\n\n/* 2 REG_DDMA_CHKSUM_8197F */\n\n#define BIT_SHIFT_IDDMA0_CHKSUM_8197F 0\n#define BIT_MASK_IDDMA0_CHKSUM_8197F 0xffff\n#define BIT_IDDMA0_CHKSUM_8197F(x)                                             \\\n\t(((x) & BIT_MASK_IDDMA0_CHKSUM_8197F) << BIT_SHIFT_IDDMA0_CHKSUM_8197F)\n#define BITS_IDDMA0_CHKSUM_8197F                                               \\\n\t(BIT_MASK_IDDMA0_CHKSUM_8197F << BIT_SHIFT_IDDMA0_CHKSUM_8197F)\n#define BIT_CLEAR_IDDMA0_CHKSUM_8197F(x) ((x) & (~BITS_IDDMA0_CHKSUM_8197F))\n#define BIT_GET_IDDMA0_CHKSUM_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8197F) & BIT_MASK_IDDMA0_CHKSUM_8197F)\n#define BIT_SET_IDDMA0_CHKSUM_8197F(x, v)                                      \\\n\t(BIT_CLEAR_IDDMA0_CHKSUM_8197F(x) | BIT_IDDMA0_CHKSUM_8197F(v))\n\n/* 2 REG_DDMA_MONITOR_8197F */\n#define BIT_IDDMA0_PERMU_UNDERFLOW_8197F BIT(14)\n#define BIT_IDDMA0_FIFO_UNDERFLOW_8197F BIT(13)\n#define BIT_IDDMA0_FIFO_OVERFLOW_8197F BIT(12)\n#define BIT_CH5_ERR_8197F BIT(5)\n#define BIT_CH4_ERR_8197F BIT(4)\n#define BIT_CH3_ERR_8197F BIT(3)\n#define BIT_CH2_ERR_8197F BIT(2)\n#define BIT_CH1_ERR_8197F BIT(1)\n#define BIT_CH0_ERR_8197F BIT(0)\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_HCI_CTRL_8197F */\n#define BIT_HCIIO_PERSTB_SEL_8197F BIT(31)\n\n#define BIT_SHIFT_HCI_MAX_RXDMA_8197F 28\n#define BIT_MASK_HCI_MAX_RXDMA_8197F 0x7\n#define BIT_HCI_MAX_RXDMA_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HCI_MAX_RXDMA_8197F) << BIT_SHIFT_HCI_MAX_RXDMA_8197F)\n#define BITS_HCI_MAX_RXDMA_8197F                                               \\\n\t(BIT_MASK_HCI_MAX_RXDMA_8197F << BIT_SHIFT_HCI_MAX_RXDMA_8197F)\n#define BIT_CLEAR_HCI_MAX_RXDMA_8197F(x) ((x) & (~BITS_HCI_MAX_RXDMA_8197F))\n#define BIT_GET_HCI_MAX_RXDMA_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HCI_MAX_RXDMA_8197F) & BIT_MASK_HCI_MAX_RXDMA_8197F)\n#define BIT_SET_HCI_MAX_RXDMA_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HCI_MAX_RXDMA_8197F(x) | BIT_HCI_MAX_RXDMA_8197F(v))\n\n#define BIT_MULRW_8197F BIT(27)\n\n#define BIT_SHIFT_HCI_MAX_TXDMA_8197F 24\n#define BIT_MASK_HCI_MAX_TXDMA_8197F 0x7\n#define BIT_HCI_MAX_TXDMA_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HCI_MAX_TXDMA_8197F) << BIT_SHIFT_HCI_MAX_TXDMA_8197F)\n#define BITS_HCI_MAX_TXDMA_8197F                                               \\\n\t(BIT_MASK_HCI_MAX_TXDMA_8197F << BIT_SHIFT_HCI_MAX_TXDMA_8197F)\n#define BIT_CLEAR_HCI_MAX_TXDMA_8197F(x) ((x) & (~BITS_HCI_MAX_TXDMA_8197F))\n#define BIT_GET_HCI_MAX_TXDMA_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HCI_MAX_TXDMA_8197F) & BIT_MASK_HCI_MAX_TXDMA_8197F)\n#define BIT_SET_HCI_MAX_TXDMA_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HCI_MAX_TXDMA_8197F(x) | BIT_HCI_MAX_TXDMA_8197F(v))\n\n#define BIT_EN_CPL_TIMEOUT_PS_8197F BIT(22)\n#define BIT_REG_TXDMA_FAIL_PS_8197F BIT(21)\n#define BIT_HCI_RST_TRXDMA_INTF_8197F BIT(20)\n#define BIT_EN_HWENTR_L1_8197F BIT(19)\n#define BIT_EN_ADV_CLKGATE_8197F BIT(18)\n#define BIT_HCI_EN_SWENT_L23_8197F BIT(17)\n#define BIT_HCI_EN_HWEXT_L1_8197F BIT(16)\n#define BIT_RX_CLOSE_EN_8197F BIT(15)\n#define BIT_STOP_BCNQ_8197F BIT(14)\n#define BIT_STOP_MGQ_8197F BIT(13)\n#define BIT_STOP_VOQ_8197F BIT(12)\n#define BIT_STOP_VIQ_8197F BIT(11)\n#define BIT_STOP_BEQ_8197F BIT(10)\n#define BIT_STOP_BKQ_8197F BIT(9)\n#define BIT_STOP_RXQ_8197F BIT(8)\n#define BIT_STOP_HI7Q_8197F BIT(7)\n#define BIT_STOP_HI6Q_8197F BIT(6)\n#define BIT_STOP_HI5Q_8197F BIT(5)\n#define BIT_STOP_HI4Q_8197F BIT(4)\n#define BIT_STOP_HI3Q_8197F BIT(3)\n#define BIT_STOP_HI2Q_8197F BIT(2)\n#define BIT_STOP_HI1Q_8197F BIT(1)\n#define BIT_STOP_HI0Q_8197F BIT(0)\n\n/* 2 REG_INT_MIG_8197F */\n\n#define BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F 28\n#define BIT_MASK_TXTTIMER_MATCH_NUM_8197F 0xf\n#define BIT_TXTTIMER_MATCH_NUM_8197F(x)                                        \\\n\t(((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8197F)                             \\\n\t << BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F)\n#define BITS_TXTTIMER_MATCH_NUM_8197F                                          \\\n\t(BIT_MASK_TXTTIMER_MATCH_NUM_8197F                                     \\\n\t << BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F)\n#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8197F(x)                                  \\\n\t((x) & (~BITS_TXTTIMER_MATCH_NUM_8197F))\n#define BIT_GET_TXTTIMER_MATCH_NUM_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) &                         \\\n\t BIT_MASK_TXTTIMER_MATCH_NUM_8197F)\n#define BIT_SET_TXTTIMER_MATCH_NUM_8197F(x, v)                                 \\\n\t(BIT_CLEAR_TXTTIMER_MATCH_NUM_8197F(x) |                               \\\n\t BIT_TXTTIMER_MATCH_NUM_8197F(v))\n\n#define BIT_SHIFT_TXPKT_NUM_MATCH_8197F 24\n#define BIT_MASK_TXPKT_NUM_MATCH_8197F 0xf\n#define BIT_TXPKT_NUM_MATCH_8197F(x)                                           \\\n\t(((x) & BIT_MASK_TXPKT_NUM_MATCH_8197F)                                \\\n\t << BIT_SHIFT_TXPKT_NUM_MATCH_8197F)\n#define BITS_TXPKT_NUM_MATCH_8197F                                             \\\n\t(BIT_MASK_TXPKT_NUM_MATCH_8197F << BIT_SHIFT_TXPKT_NUM_MATCH_8197F)\n#define BIT_CLEAR_TXPKT_NUM_MATCH_8197F(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8197F))\n#define BIT_GET_TXPKT_NUM_MATCH_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8197F) &                            \\\n\t BIT_MASK_TXPKT_NUM_MATCH_8197F)\n#define BIT_SET_TXPKT_NUM_MATCH_8197F(x, v)                                    \\\n\t(BIT_CLEAR_TXPKT_NUM_MATCH_8197F(x) | BIT_TXPKT_NUM_MATCH_8197F(v))\n\n#define BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F 20\n#define BIT_MASK_RXTTIMER_MATCH_NUM_8197F 0xf\n#define BIT_RXTTIMER_MATCH_NUM_8197F(x)                                        \\\n\t(((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8197F)                             \\\n\t << BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F)\n#define BITS_RXTTIMER_MATCH_NUM_8197F                                          \\\n\t(BIT_MASK_RXTTIMER_MATCH_NUM_8197F                                     \\\n\t << BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F)\n#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8197F(x)                                  \\\n\t((x) & (~BITS_RXTTIMER_MATCH_NUM_8197F))\n#define BIT_GET_RXTTIMER_MATCH_NUM_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) &                         \\\n\t BIT_MASK_RXTTIMER_MATCH_NUM_8197F)\n#define BIT_SET_RXTTIMER_MATCH_NUM_8197F(x, v)                                 \\\n\t(BIT_CLEAR_RXTTIMER_MATCH_NUM_8197F(x) |                               \\\n\t BIT_RXTTIMER_MATCH_NUM_8197F(v))\n\n#define BIT_SHIFT_RXPKT_NUM_MATCH_8197F 16\n#define BIT_MASK_RXPKT_NUM_MATCH_8197F 0xf\n#define BIT_RXPKT_NUM_MATCH_8197F(x)                                           \\\n\t(((x) & BIT_MASK_RXPKT_NUM_MATCH_8197F)                                \\\n\t << BIT_SHIFT_RXPKT_NUM_MATCH_8197F)\n#define BITS_RXPKT_NUM_MATCH_8197F                                             \\\n\t(BIT_MASK_RXPKT_NUM_MATCH_8197F << BIT_SHIFT_RXPKT_NUM_MATCH_8197F)\n#define BIT_CLEAR_RXPKT_NUM_MATCH_8197F(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8197F))\n#define BIT_GET_RXPKT_NUM_MATCH_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8197F) &                            \\\n\t BIT_MASK_RXPKT_NUM_MATCH_8197F)\n#define BIT_SET_RXPKT_NUM_MATCH_8197F(x, v)                                    \\\n\t(BIT_CLEAR_RXPKT_NUM_MATCH_8197F(x) | BIT_RXPKT_NUM_MATCH_8197F(v))\n\n#define BIT_SHIFT_MIGRATE_TIMER_8197F 0\n#define BIT_MASK_MIGRATE_TIMER_8197F 0xffff\n#define BIT_MIGRATE_TIMER_8197F(x)                                             \\\n\t(((x) & BIT_MASK_MIGRATE_TIMER_8197F) << BIT_SHIFT_MIGRATE_TIMER_8197F)\n#define BITS_MIGRATE_TIMER_8197F                                               \\\n\t(BIT_MASK_MIGRATE_TIMER_8197F << BIT_SHIFT_MIGRATE_TIMER_8197F)\n#define BIT_CLEAR_MIGRATE_TIMER_8197F(x) ((x) & (~BITS_MIGRATE_TIMER_8197F))\n#define BIT_GET_MIGRATE_TIMER_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_MIGRATE_TIMER_8197F) & BIT_MASK_MIGRATE_TIMER_8197F)\n#define BIT_SET_MIGRATE_TIMER_8197F(x, v)                                      \\\n\t(BIT_CLEAR_MIGRATE_TIMER_8197F(x) | BIT_MIGRATE_TIMER_8197F(v))\n\n/* 2 REG_BCNQ_TXBD_DESA_8197F */\n\n#define BIT_SHIFT_BCNQ_TXBD_DESA_8197F 0\n#define BIT_MASK_BCNQ_TXBD_DESA_8197F 0xffffffffffffffffL\n#define BIT_BCNQ_TXBD_DESA_8197F(x)                                            \\\n\t(((x) & BIT_MASK_BCNQ_TXBD_DESA_8197F)                                 \\\n\t << BIT_SHIFT_BCNQ_TXBD_DESA_8197F)\n#define BITS_BCNQ_TXBD_DESA_8197F                                              \\\n\t(BIT_MASK_BCNQ_TXBD_DESA_8197F << BIT_SHIFT_BCNQ_TXBD_DESA_8197F)\n#define BIT_CLEAR_BCNQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8197F))\n#define BIT_GET_BCNQ_TXBD_DESA_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8197F) &                             \\\n\t BIT_MASK_BCNQ_TXBD_DESA_8197F)\n#define BIT_SET_BCNQ_TXBD_DESA_8197F(x, v)                                     \\\n\t(BIT_CLEAR_BCNQ_TXBD_DESA_8197F(x) | BIT_BCNQ_TXBD_DESA_8197F(v))\n\n/* 2 REG_MGQ_TXBD_DESA_8197F */\n\n#define BIT_SHIFT_MGQ_TXBD_DESA_8197F 0\n#define BIT_MASK_MGQ_TXBD_DESA_8197F 0xffffffffffffffffL\n#define BIT_MGQ_TXBD_DESA_8197F(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_TXBD_DESA_8197F) << BIT_SHIFT_MGQ_TXBD_DESA_8197F)\n#define BITS_MGQ_TXBD_DESA_8197F                                               \\\n\t(BIT_MASK_MGQ_TXBD_DESA_8197F << BIT_SHIFT_MGQ_TXBD_DESA_8197F)\n#define BIT_CLEAR_MGQ_TXBD_DESA_8197F(x) ((x) & (~BITS_MGQ_TXBD_DESA_8197F))\n#define BIT_GET_MGQ_TXBD_DESA_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8197F) & BIT_MASK_MGQ_TXBD_DESA_8197F)\n#define BIT_SET_MGQ_TXBD_DESA_8197F(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_TXBD_DESA_8197F(x) | BIT_MGQ_TXBD_DESA_8197F(v))\n\n/* 2 REG_VOQ_TXBD_DESA_8197F */\n\n#define BIT_SHIFT_VOQ_TXBD_DESA_8197F 0\n#define BIT_MASK_VOQ_TXBD_DESA_8197F 0xffffffffffffffffL\n#define BIT_VOQ_TXBD_DESA_8197F(x)                                             \\\n\t(((x) & BIT_MASK_VOQ_TXBD_DESA_8197F) << BIT_SHIFT_VOQ_TXBD_DESA_8197F)\n#define BITS_VOQ_TXBD_DESA_8197F                                               \\\n\t(BIT_MASK_VOQ_TXBD_DESA_8197F << BIT_SHIFT_VOQ_TXBD_DESA_8197F)\n#define BIT_CLEAR_VOQ_TXBD_DESA_8197F(x) ((x) & (~BITS_VOQ_TXBD_DESA_8197F))\n#define BIT_GET_VOQ_TXBD_DESA_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8197F) & BIT_MASK_VOQ_TXBD_DESA_8197F)\n#define BIT_SET_VOQ_TXBD_DESA_8197F(x, v)                                      \\\n\t(BIT_CLEAR_VOQ_TXBD_DESA_8197F(x) | BIT_VOQ_TXBD_DESA_8197F(v))\n\n/* 2 REG_VIQ_TXBD_DESA_8197F */\n\n#define BIT_SHIFT_VIQ_TXBD_DESA_8197F 0\n#define BIT_MASK_VIQ_TXBD_DESA_8197F 0xffffffffffffffffL\n#define BIT_VIQ_TXBD_DESA_8197F(x)                                             \\\n\t(((x) & BIT_MASK_VIQ_TXBD_DESA_8197F) << BIT_SHIFT_VIQ_TXBD_DESA_8197F)\n#define BITS_VIQ_TXBD_DESA_8197F                                               \\\n\t(BIT_MASK_VIQ_TXBD_DESA_8197F << BIT_SHIFT_VIQ_TXBD_DESA_8197F)\n#define BIT_CLEAR_VIQ_TXBD_DESA_8197F(x) ((x) & (~BITS_VIQ_TXBD_DESA_8197F))\n#define BIT_GET_VIQ_TXBD_DESA_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8197F) & BIT_MASK_VIQ_TXBD_DESA_8197F)\n#define BIT_SET_VIQ_TXBD_DESA_8197F(x, v)                                      \\\n\t(BIT_CLEAR_VIQ_TXBD_DESA_8197F(x) | BIT_VIQ_TXBD_DESA_8197F(v))\n\n/* 2 REG_BEQ_TXBD_DESA_8197F */\n\n#define BIT_SHIFT_BEQ_TXBD_DESA_8197F 0\n#define BIT_MASK_BEQ_TXBD_DESA_8197F 0xffffffffffffffffL\n#define BIT_BEQ_TXBD_DESA_8197F(x)                                             \\\n\t(((x) & BIT_MASK_BEQ_TXBD_DESA_8197F) << BIT_SHIFT_BEQ_TXBD_DESA_8197F)\n#define BITS_BEQ_TXBD_DESA_8197F                                               \\\n\t(BIT_MASK_BEQ_TXBD_DESA_8197F << BIT_SHIFT_BEQ_TXBD_DESA_8197F)\n#define BIT_CLEAR_BEQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BEQ_TXBD_DESA_8197F))\n#define BIT_GET_BEQ_TXBD_DESA_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8197F) & BIT_MASK_BEQ_TXBD_DESA_8197F)\n#define BIT_SET_BEQ_TXBD_DESA_8197F(x, v)                                      \\\n\t(BIT_CLEAR_BEQ_TXBD_DESA_8197F(x) | BIT_BEQ_TXBD_DESA_8197F(v))\n\n/* 2 REG_BKQ_TXBD_DESA_8197F */\n\n#define BIT_SHIFT_BKQ_TXBD_DESA_8197F 0\n#define BIT_MASK_BKQ_TXBD_DESA_8197F 0xffffffffffffffffL\n#define BIT_BKQ_TXBD_DESA_8197F(x)                                             \\\n\t(((x) & BIT_MASK_BKQ_TXBD_DESA_8197F) << BIT_SHIFT_BKQ_TXBD_DESA_8197F)\n#define BITS_BKQ_TXBD_DESA_8197F                                               \\\n\t(BIT_MASK_BKQ_TXBD_DESA_8197F << BIT_SHIFT_BKQ_TXBD_DESA_8197F)\n#define BIT_CLEAR_BKQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BKQ_TXBD_DESA_8197F))\n#define BIT_GET_BKQ_TXBD_DESA_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8197F) & BIT_MASK_BKQ_TXBD_DESA_8197F)\n#define BIT_SET_BKQ_TXBD_DESA_8197F(x, v)                                      \\\n\t(BIT_CLEAR_BKQ_TXBD_DESA_8197F(x) | BIT_BKQ_TXBD_DESA_8197F(v))\n\n/* 2 REG_RXQ_RXBD_DESA_8197F */\n\n#define BIT_SHIFT_RXQ_RXBD_DESA_8197F 0\n#define BIT_MASK_RXQ_RXBD_DESA_8197F 0xffffffffffffffffL\n#define BIT_RXQ_RXBD_DESA_8197F(x)                                             \\\n\t(((x) & BIT_MASK_RXQ_RXBD_DESA_8197F) << BIT_SHIFT_RXQ_RXBD_DESA_8197F)\n#define BITS_RXQ_RXBD_DESA_8197F                                               \\\n\t(BIT_MASK_RXQ_RXBD_DESA_8197F << BIT_SHIFT_RXQ_RXBD_DESA_8197F)\n#define BIT_CLEAR_RXQ_RXBD_DESA_8197F(x) ((x) & (~BITS_RXQ_RXBD_DESA_8197F))\n#define BIT_GET_RXQ_RXBD_DESA_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8197F) & BIT_MASK_RXQ_RXBD_DESA_8197F)\n#define BIT_SET_RXQ_RXBD_DESA_8197F(x, v)                                      \\\n\t(BIT_CLEAR_RXQ_RXBD_DESA_8197F(x) | BIT_RXQ_RXBD_DESA_8197F(v))\n\n/* 2 REG_HI0Q_TXBD_DESA_8197F */\n\n#define BIT_SHIFT_HI0Q_TXBD_DESA_8197F 0\n#define BIT_MASK_HI0Q_TXBD_DESA_8197F 0xffffffffffffffffL\n#define BIT_HI0Q_TXBD_DESA_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HI0Q_TXBD_DESA_8197F)                                 \\\n\t << BIT_SHIFT_HI0Q_TXBD_DESA_8197F)\n#define BITS_HI0Q_TXBD_DESA_8197F                                              \\\n\t(BIT_MASK_HI0Q_TXBD_DESA_8197F << BIT_SHIFT_HI0Q_TXBD_DESA_8197F)\n#define BIT_CLEAR_HI0Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8197F))\n#define BIT_GET_HI0Q_TXBD_DESA_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8197F) &                             \\\n\t BIT_MASK_HI0Q_TXBD_DESA_8197F)\n#define BIT_SET_HI0Q_TXBD_DESA_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HI0Q_TXBD_DESA_8197F(x) | BIT_HI0Q_TXBD_DESA_8197F(v))\n\n/* 2 REG_HI1Q_TXBD_DESA_8197F */\n\n#define BIT_SHIFT_HI1Q_TXBD_DESA_8197F 0\n#define BIT_MASK_HI1Q_TXBD_DESA_8197F 0xffffffffffffffffL\n#define BIT_HI1Q_TXBD_DESA_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HI1Q_TXBD_DESA_8197F)                                 \\\n\t << BIT_SHIFT_HI1Q_TXBD_DESA_8197F)\n#define BITS_HI1Q_TXBD_DESA_8197F                                              \\\n\t(BIT_MASK_HI1Q_TXBD_DESA_8197F << BIT_SHIFT_HI1Q_TXBD_DESA_8197F)\n#define BIT_CLEAR_HI1Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8197F))\n#define BIT_GET_HI1Q_TXBD_DESA_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8197F) &                             \\\n\t BIT_MASK_HI1Q_TXBD_DESA_8197F)\n#define BIT_SET_HI1Q_TXBD_DESA_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HI1Q_TXBD_DESA_8197F(x) | BIT_HI1Q_TXBD_DESA_8197F(v))\n\n/* 2 REG_HI2Q_TXBD_DESA_8197F */\n\n#define BIT_SHIFT_HI2Q_TXBD_DESA_8197F 0\n#define BIT_MASK_HI2Q_TXBD_DESA_8197F 0xffffffffffffffffL\n#define BIT_HI2Q_TXBD_DESA_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HI2Q_TXBD_DESA_8197F)                                 \\\n\t << BIT_SHIFT_HI2Q_TXBD_DESA_8197F)\n#define BITS_HI2Q_TXBD_DESA_8197F                                              \\\n\t(BIT_MASK_HI2Q_TXBD_DESA_8197F << BIT_SHIFT_HI2Q_TXBD_DESA_8197F)\n#define BIT_CLEAR_HI2Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8197F))\n#define BIT_GET_HI2Q_TXBD_DESA_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8197F) &                             \\\n\t BIT_MASK_HI2Q_TXBD_DESA_8197F)\n#define BIT_SET_HI2Q_TXBD_DESA_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HI2Q_TXBD_DESA_8197F(x) | BIT_HI2Q_TXBD_DESA_8197F(v))\n\n/* 2 REG_HI3Q_TXBD_DESA_8197F */\n\n#define BIT_SHIFT_HI3Q_TXBD_DESA_8197F 0\n#define BIT_MASK_HI3Q_TXBD_DESA_8197F 0xffffffffffffffffL\n#define BIT_HI3Q_TXBD_DESA_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HI3Q_TXBD_DESA_8197F)                                 \\\n\t << BIT_SHIFT_HI3Q_TXBD_DESA_8197F)\n#define BITS_HI3Q_TXBD_DESA_8197F                                              \\\n\t(BIT_MASK_HI3Q_TXBD_DESA_8197F << BIT_SHIFT_HI3Q_TXBD_DESA_8197F)\n#define BIT_CLEAR_HI3Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8197F))\n#define BIT_GET_HI3Q_TXBD_DESA_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8197F) &                             \\\n\t BIT_MASK_HI3Q_TXBD_DESA_8197F)\n#define BIT_SET_HI3Q_TXBD_DESA_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HI3Q_TXBD_DESA_8197F(x) | BIT_HI3Q_TXBD_DESA_8197F(v))\n\n/* 2 REG_HI4Q_TXBD_DESA_8197F */\n\n#define BIT_SHIFT_HI4Q_TXBD_DESA_8197F 0\n#define BIT_MASK_HI4Q_TXBD_DESA_8197F 0xffffffffffffffffL\n#define BIT_HI4Q_TXBD_DESA_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HI4Q_TXBD_DESA_8197F)                                 \\\n\t << BIT_SHIFT_HI4Q_TXBD_DESA_8197F)\n#define BITS_HI4Q_TXBD_DESA_8197F                                              \\\n\t(BIT_MASK_HI4Q_TXBD_DESA_8197F << BIT_SHIFT_HI4Q_TXBD_DESA_8197F)\n#define BIT_CLEAR_HI4Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8197F))\n#define BIT_GET_HI4Q_TXBD_DESA_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8197F) &                             \\\n\t BIT_MASK_HI4Q_TXBD_DESA_8197F)\n#define BIT_SET_HI4Q_TXBD_DESA_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HI4Q_TXBD_DESA_8197F(x) | BIT_HI4Q_TXBD_DESA_8197F(v))\n\n/* 2 REG_HI5Q_TXBD_DESA_8197F */\n\n#define BIT_SHIFT_HI5Q_TXBD_DESA_8197F 0\n#define BIT_MASK_HI5Q_TXBD_DESA_8197F 0xffffffffffffffffL\n#define BIT_HI5Q_TXBD_DESA_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HI5Q_TXBD_DESA_8197F)                                 \\\n\t << BIT_SHIFT_HI5Q_TXBD_DESA_8197F)\n#define BITS_HI5Q_TXBD_DESA_8197F                                              \\\n\t(BIT_MASK_HI5Q_TXBD_DESA_8197F << BIT_SHIFT_HI5Q_TXBD_DESA_8197F)\n#define BIT_CLEAR_HI5Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8197F))\n#define BIT_GET_HI5Q_TXBD_DESA_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8197F) &                             \\\n\t BIT_MASK_HI5Q_TXBD_DESA_8197F)\n#define BIT_SET_HI5Q_TXBD_DESA_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HI5Q_TXBD_DESA_8197F(x) | BIT_HI5Q_TXBD_DESA_8197F(v))\n\n/* 2 REG_HI6Q_TXBD_DESA_8197F */\n\n#define BIT_SHIFT_HI6Q_TXBD_DESA_8197F 0\n#define BIT_MASK_HI6Q_TXBD_DESA_8197F 0xffffffffffffffffL\n#define BIT_HI6Q_TXBD_DESA_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HI6Q_TXBD_DESA_8197F)                                 \\\n\t << BIT_SHIFT_HI6Q_TXBD_DESA_8197F)\n#define BITS_HI6Q_TXBD_DESA_8197F                                              \\\n\t(BIT_MASK_HI6Q_TXBD_DESA_8197F << BIT_SHIFT_HI6Q_TXBD_DESA_8197F)\n#define BIT_CLEAR_HI6Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8197F))\n#define BIT_GET_HI6Q_TXBD_DESA_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8197F) &                             \\\n\t BIT_MASK_HI6Q_TXBD_DESA_8197F)\n#define BIT_SET_HI6Q_TXBD_DESA_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HI6Q_TXBD_DESA_8197F(x) | BIT_HI6Q_TXBD_DESA_8197F(v))\n\n/* 2 REG_HI7Q_TXBD_DESA_8197F */\n\n#define BIT_SHIFT_HI7Q_TXBD_DESA_8197F 0\n#define BIT_MASK_HI7Q_TXBD_DESA_8197F 0xffffffffffffffffL\n#define BIT_HI7Q_TXBD_DESA_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HI7Q_TXBD_DESA_8197F)                                 \\\n\t << BIT_SHIFT_HI7Q_TXBD_DESA_8197F)\n#define BITS_HI7Q_TXBD_DESA_8197F                                              \\\n\t(BIT_MASK_HI7Q_TXBD_DESA_8197F << BIT_SHIFT_HI7Q_TXBD_DESA_8197F)\n#define BIT_CLEAR_HI7Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8197F))\n#define BIT_GET_HI7Q_TXBD_DESA_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8197F) &                             \\\n\t BIT_MASK_HI7Q_TXBD_DESA_8197F)\n#define BIT_SET_HI7Q_TXBD_DESA_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HI7Q_TXBD_DESA_8197F(x) | BIT_HI7Q_TXBD_DESA_8197F(v))\n\n/* 2 REG_MGQ_TXBD_NUM_8197F */\n#define BIT_HCI_MGQ_FLAG_8197F BIT(14)\n\n#define BIT_SHIFT_MGQ_DESC_MODE_8197F 12\n#define BIT_MASK_MGQ_DESC_MODE_8197F 0x3\n#define BIT_MGQ_DESC_MODE_8197F(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_DESC_MODE_8197F) << BIT_SHIFT_MGQ_DESC_MODE_8197F)\n#define BITS_MGQ_DESC_MODE_8197F                                               \\\n\t(BIT_MASK_MGQ_DESC_MODE_8197F << BIT_SHIFT_MGQ_DESC_MODE_8197F)\n#define BIT_CLEAR_MGQ_DESC_MODE_8197F(x) ((x) & (~BITS_MGQ_DESC_MODE_8197F))\n#define BIT_GET_MGQ_DESC_MODE_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_DESC_MODE_8197F) & BIT_MASK_MGQ_DESC_MODE_8197F)\n#define BIT_SET_MGQ_DESC_MODE_8197F(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_DESC_MODE_8197F(x) | BIT_MGQ_DESC_MODE_8197F(v))\n\n#define BIT_SHIFT_MGQ_DESC_NUM_8197F 0\n#define BIT_MASK_MGQ_DESC_NUM_8197F 0xfff\n#define BIT_MGQ_DESC_NUM_8197F(x)                                              \\\n\t(((x) & BIT_MASK_MGQ_DESC_NUM_8197F) << BIT_SHIFT_MGQ_DESC_NUM_8197F)\n#define BITS_MGQ_DESC_NUM_8197F                                                \\\n\t(BIT_MASK_MGQ_DESC_NUM_8197F << BIT_SHIFT_MGQ_DESC_NUM_8197F)\n#define BIT_CLEAR_MGQ_DESC_NUM_8197F(x) ((x) & (~BITS_MGQ_DESC_NUM_8197F))\n#define BIT_GET_MGQ_DESC_NUM_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_MGQ_DESC_NUM_8197F) & BIT_MASK_MGQ_DESC_NUM_8197F)\n#define BIT_SET_MGQ_DESC_NUM_8197F(x, v)                                       \\\n\t(BIT_CLEAR_MGQ_DESC_NUM_8197F(x) | BIT_MGQ_DESC_NUM_8197F(v))\n\n/* 2 REG_RX_RXBD_NUM_8197F */\n#define BIT_SYS_32_64_8197F BIT(15)\n\n#define BIT_SHIFT_BCNQ_DESC_MODE_8197F 13\n#define BIT_MASK_BCNQ_DESC_MODE_8197F 0x3\n#define BIT_BCNQ_DESC_MODE_8197F(x)                                            \\\n\t(((x) & BIT_MASK_BCNQ_DESC_MODE_8197F)                                 \\\n\t << BIT_SHIFT_BCNQ_DESC_MODE_8197F)\n#define BITS_BCNQ_DESC_MODE_8197F                                              \\\n\t(BIT_MASK_BCNQ_DESC_MODE_8197F << BIT_SHIFT_BCNQ_DESC_MODE_8197F)\n#define BIT_CLEAR_BCNQ_DESC_MODE_8197F(x) ((x) & (~BITS_BCNQ_DESC_MODE_8197F))\n#define BIT_GET_BCNQ_DESC_MODE_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8197F) &                             \\\n\t BIT_MASK_BCNQ_DESC_MODE_8197F)\n#define BIT_SET_BCNQ_DESC_MODE_8197F(x, v)                                     \\\n\t(BIT_CLEAR_BCNQ_DESC_MODE_8197F(x) | BIT_BCNQ_DESC_MODE_8197F(v))\n\n#define BIT_HCI_BCNQ_FLAG_8197F BIT(12)\n\n#define BIT_SHIFT_RXQ_DESC_NUM_8197F 0\n#define BIT_MASK_RXQ_DESC_NUM_8197F 0xfff\n#define BIT_RXQ_DESC_NUM_8197F(x)                                              \\\n\t(((x) & BIT_MASK_RXQ_DESC_NUM_8197F) << BIT_SHIFT_RXQ_DESC_NUM_8197F)\n#define BITS_RXQ_DESC_NUM_8197F                                                \\\n\t(BIT_MASK_RXQ_DESC_NUM_8197F << BIT_SHIFT_RXQ_DESC_NUM_8197F)\n#define BIT_CLEAR_RXQ_DESC_NUM_8197F(x) ((x) & (~BITS_RXQ_DESC_NUM_8197F))\n#define BIT_GET_RXQ_DESC_NUM_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXQ_DESC_NUM_8197F) & BIT_MASK_RXQ_DESC_NUM_8197F)\n#define BIT_SET_RXQ_DESC_NUM_8197F(x, v)                                       \\\n\t(BIT_CLEAR_RXQ_DESC_NUM_8197F(x) | BIT_RXQ_DESC_NUM_8197F(v))\n\n/* 2 REG_VOQ_TXBD_NUM_8197F */\n#define BIT_HCI_VOQ_FLAG_8197F BIT(14)\n\n#define BIT_SHIFT_VOQ_DESC_MODE_8197F 12\n#define BIT_MASK_VOQ_DESC_MODE_8197F 0x3\n#define BIT_VOQ_DESC_MODE_8197F(x)                                             \\\n\t(((x) & BIT_MASK_VOQ_DESC_MODE_8197F) << BIT_SHIFT_VOQ_DESC_MODE_8197F)\n#define BITS_VOQ_DESC_MODE_8197F                                               \\\n\t(BIT_MASK_VOQ_DESC_MODE_8197F << BIT_SHIFT_VOQ_DESC_MODE_8197F)\n#define BIT_CLEAR_VOQ_DESC_MODE_8197F(x) ((x) & (~BITS_VOQ_DESC_MODE_8197F))\n#define BIT_GET_VOQ_DESC_MODE_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_VOQ_DESC_MODE_8197F) & BIT_MASK_VOQ_DESC_MODE_8197F)\n#define BIT_SET_VOQ_DESC_MODE_8197F(x, v)                                      \\\n\t(BIT_CLEAR_VOQ_DESC_MODE_8197F(x) | BIT_VOQ_DESC_MODE_8197F(v))\n\n#define BIT_SHIFT_VOQ_DESC_NUM_8197F 0\n#define BIT_MASK_VOQ_DESC_NUM_8197F 0xfff\n#define BIT_VOQ_DESC_NUM_8197F(x)                                              \\\n\t(((x) & BIT_MASK_VOQ_DESC_NUM_8197F) << BIT_SHIFT_VOQ_DESC_NUM_8197F)\n#define BITS_VOQ_DESC_NUM_8197F                                                \\\n\t(BIT_MASK_VOQ_DESC_NUM_8197F << BIT_SHIFT_VOQ_DESC_NUM_8197F)\n#define BIT_CLEAR_VOQ_DESC_NUM_8197F(x) ((x) & (~BITS_VOQ_DESC_NUM_8197F))\n#define BIT_GET_VOQ_DESC_NUM_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_VOQ_DESC_NUM_8197F) & BIT_MASK_VOQ_DESC_NUM_8197F)\n#define BIT_SET_VOQ_DESC_NUM_8197F(x, v)                                       \\\n\t(BIT_CLEAR_VOQ_DESC_NUM_8197F(x) | BIT_VOQ_DESC_NUM_8197F(v))\n\n/* 2 REG_VIQ_TXBD_NUM_8197F */\n#define BIT_HCI_VIQ_FLAG_8197F BIT(14)\n\n#define BIT_SHIFT_VIQ_DESC_MODE_8197F 12\n#define BIT_MASK_VIQ_DESC_MODE_8197F 0x3\n#define BIT_VIQ_DESC_MODE_8197F(x)                                             \\\n\t(((x) & BIT_MASK_VIQ_DESC_MODE_8197F) << BIT_SHIFT_VIQ_DESC_MODE_8197F)\n#define BITS_VIQ_DESC_MODE_8197F                                               \\\n\t(BIT_MASK_VIQ_DESC_MODE_8197F << BIT_SHIFT_VIQ_DESC_MODE_8197F)\n#define BIT_CLEAR_VIQ_DESC_MODE_8197F(x) ((x) & (~BITS_VIQ_DESC_MODE_8197F))\n#define BIT_GET_VIQ_DESC_MODE_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_VIQ_DESC_MODE_8197F) & BIT_MASK_VIQ_DESC_MODE_8197F)\n#define BIT_SET_VIQ_DESC_MODE_8197F(x, v)                                      \\\n\t(BIT_CLEAR_VIQ_DESC_MODE_8197F(x) | BIT_VIQ_DESC_MODE_8197F(v))\n\n#define BIT_SHIFT_VIQ_DESC_NUM_8197F 0\n#define BIT_MASK_VIQ_DESC_NUM_8197F 0xfff\n#define BIT_VIQ_DESC_NUM_8197F(x)                                              \\\n\t(((x) & BIT_MASK_VIQ_DESC_NUM_8197F) << BIT_SHIFT_VIQ_DESC_NUM_8197F)\n#define BITS_VIQ_DESC_NUM_8197F                                                \\\n\t(BIT_MASK_VIQ_DESC_NUM_8197F << BIT_SHIFT_VIQ_DESC_NUM_8197F)\n#define BIT_CLEAR_VIQ_DESC_NUM_8197F(x) ((x) & (~BITS_VIQ_DESC_NUM_8197F))\n#define BIT_GET_VIQ_DESC_NUM_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_VIQ_DESC_NUM_8197F) & BIT_MASK_VIQ_DESC_NUM_8197F)\n#define BIT_SET_VIQ_DESC_NUM_8197F(x, v)                                       \\\n\t(BIT_CLEAR_VIQ_DESC_NUM_8197F(x) | BIT_VIQ_DESC_NUM_8197F(v))\n\n/* 2 REG_BEQ_TXBD_NUM_8197F */\n#define BIT_HCI_BEQ_FLAG_8197F BIT(14)\n\n#define BIT_SHIFT_BEQ_DESC_MODE_8197F 12\n#define BIT_MASK_BEQ_DESC_MODE_8197F 0x3\n#define BIT_BEQ_DESC_MODE_8197F(x)                                             \\\n\t(((x) & BIT_MASK_BEQ_DESC_MODE_8197F) << BIT_SHIFT_BEQ_DESC_MODE_8197F)\n#define BITS_BEQ_DESC_MODE_8197F                                               \\\n\t(BIT_MASK_BEQ_DESC_MODE_8197F << BIT_SHIFT_BEQ_DESC_MODE_8197F)\n#define BIT_CLEAR_BEQ_DESC_MODE_8197F(x) ((x) & (~BITS_BEQ_DESC_MODE_8197F))\n#define BIT_GET_BEQ_DESC_MODE_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_BEQ_DESC_MODE_8197F) & BIT_MASK_BEQ_DESC_MODE_8197F)\n#define BIT_SET_BEQ_DESC_MODE_8197F(x, v)                                      \\\n\t(BIT_CLEAR_BEQ_DESC_MODE_8197F(x) | BIT_BEQ_DESC_MODE_8197F(v))\n\n#define BIT_SHIFT_BEQ_DESC_NUM_8197F 0\n#define BIT_MASK_BEQ_DESC_NUM_8197F 0xfff\n#define BIT_BEQ_DESC_NUM_8197F(x)                                              \\\n\t(((x) & BIT_MASK_BEQ_DESC_NUM_8197F) << BIT_SHIFT_BEQ_DESC_NUM_8197F)\n#define BITS_BEQ_DESC_NUM_8197F                                                \\\n\t(BIT_MASK_BEQ_DESC_NUM_8197F << BIT_SHIFT_BEQ_DESC_NUM_8197F)\n#define BIT_CLEAR_BEQ_DESC_NUM_8197F(x) ((x) & (~BITS_BEQ_DESC_NUM_8197F))\n#define BIT_GET_BEQ_DESC_NUM_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_BEQ_DESC_NUM_8197F) & BIT_MASK_BEQ_DESC_NUM_8197F)\n#define BIT_SET_BEQ_DESC_NUM_8197F(x, v)                                       \\\n\t(BIT_CLEAR_BEQ_DESC_NUM_8197F(x) | BIT_BEQ_DESC_NUM_8197F(v))\n\n/* 2 REG_BKQ_TXBD_NUM_8197F */\n#define BIT_HCI_BKQ_FLAG_8197F BIT(14)\n\n#define BIT_SHIFT_BKQ_DESC_MODE_8197F 12\n#define BIT_MASK_BKQ_DESC_MODE_8197F 0x3\n#define BIT_BKQ_DESC_MODE_8197F(x)                                             \\\n\t(((x) & BIT_MASK_BKQ_DESC_MODE_8197F) << BIT_SHIFT_BKQ_DESC_MODE_8197F)\n#define BITS_BKQ_DESC_MODE_8197F                                               \\\n\t(BIT_MASK_BKQ_DESC_MODE_8197F << BIT_SHIFT_BKQ_DESC_MODE_8197F)\n#define BIT_CLEAR_BKQ_DESC_MODE_8197F(x) ((x) & (~BITS_BKQ_DESC_MODE_8197F))\n#define BIT_GET_BKQ_DESC_MODE_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_BKQ_DESC_MODE_8197F) & BIT_MASK_BKQ_DESC_MODE_8197F)\n#define BIT_SET_BKQ_DESC_MODE_8197F(x, v)                                      \\\n\t(BIT_CLEAR_BKQ_DESC_MODE_8197F(x) | BIT_BKQ_DESC_MODE_8197F(v))\n\n#define BIT_SHIFT_BKQ_DESC_NUM_8197F 0\n#define BIT_MASK_BKQ_DESC_NUM_8197F 0xfff\n#define BIT_BKQ_DESC_NUM_8197F(x)                                              \\\n\t(((x) & BIT_MASK_BKQ_DESC_NUM_8197F) << BIT_SHIFT_BKQ_DESC_NUM_8197F)\n#define BITS_BKQ_DESC_NUM_8197F                                                \\\n\t(BIT_MASK_BKQ_DESC_NUM_8197F << BIT_SHIFT_BKQ_DESC_NUM_8197F)\n#define BIT_CLEAR_BKQ_DESC_NUM_8197F(x) ((x) & (~BITS_BKQ_DESC_NUM_8197F))\n#define BIT_GET_BKQ_DESC_NUM_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_BKQ_DESC_NUM_8197F) & BIT_MASK_BKQ_DESC_NUM_8197F)\n#define BIT_SET_BKQ_DESC_NUM_8197F(x, v)                                       \\\n\t(BIT_CLEAR_BKQ_DESC_NUM_8197F(x) | BIT_BKQ_DESC_NUM_8197F(v))\n\n/* 2 REG_HI0Q_TXBD_NUM_8197F */\n#define BIT_HI0Q_FLAG_8197F BIT(14)\n\n#define BIT_SHIFT_HI0Q_DESC_MODE_8197F 12\n#define BIT_MASK_HI0Q_DESC_MODE_8197F 0x3\n#define BIT_HI0Q_DESC_MODE_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HI0Q_DESC_MODE_8197F)                                 \\\n\t << BIT_SHIFT_HI0Q_DESC_MODE_8197F)\n#define BITS_HI0Q_DESC_MODE_8197F                                              \\\n\t(BIT_MASK_HI0Q_DESC_MODE_8197F << BIT_SHIFT_HI0Q_DESC_MODE_8197F)\n#define BIT_CLEAR_HI0Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI0Q_DESC_MODE_8197F))\n#define BIT_GET_HI0Q_DESC_MODE_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8197F) &                             \\\n\t BIT_MASK_HI0Q_DESC_MODE_8197F)\n#define BIT_SET_HI0Q_DESC_MODE_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HI0Q_DESC_MODE_8197F(x) | BIT_HI0Q_DESC_MODE_8197F(v))\n\n#define BIT_SHIFT_HI0Q_DESC_NUM_8197F 0\n#define BIT_MASK_HI0Q_DESC_NUM_8197F 0xfff\n#define BIT_HI0Q_DESC_NUM_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HI0Q_DESC_NUM_8197F) << BIT_SHIFT_HI0Q_DESC_NUM_8197F)\n#define BITS_HI0Q_DESC_NUM_8197F                                               \\\n\t(BIT_MASK_HI0Q_DESC_NUM_8197F << BIT_SHIFT_HI0Q_DESC_NUM_8197F)\n#define BIT_CLEAR_HI0Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI0Q_DESC_NUM_8197F))\n#define BIT_GET_HI0Q_DESC_NUM_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8197F) & BIT_MASK_HI0Q_DESC_NUM_8197F)\n#define BIT_SET_HI0Q_DESC_NUM_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HI0Q_DESC_NUM_8197F(x) | BIT_HI0Q_DESC_NUM_8197F(v))\n\n/* 2 REG_HI1Q_TXBD_NUM_8197F */\n#define BIT_HI1Q_FLAG_8197F BIT(14)\n\n#define BIT_SHIFT_HI1Q_DESC_MODE_8197F 12\n#define BIT_MASK_HI1Q_DESC_MODE_8197F 0x3\n#define BIT_HI1Q_DESC_MODE_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HI1Q_DESC_MODE_8197F)                                 \\\n\t << BIT_SHIFT_HI1Q_DESC_MODE_8197F)\n#define BITS_HI1Q_DESC_MODE_8197F                                              \\\n\t(BIT_MASK_HI1Q_DESC_MODE_8197F << BIT_SHIFT_HI1Q_DESC_MODE_8197F)\n#define BIT_CLEAR_HI1Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI1Q_DESC_MODE_8197F))\n#define BIT_GET_HI1Q_DESC_MODE_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8197F) &                             \\\n\t BIT_MASK_HI1Q_DESC_MODE_8197F)\n#define BIT_SET_HI1Q_DESC_MODE_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HI1Q_DESC_MODE_8197F(x) | BIT_HI1Q_DESC_MODE_8197F(v))\n\n#define BIT_SHIFT_HI1Q_DESC_NUM_8197F 0\n#define BIT_MASK_HI1Q_DESC_NUM_8197F 0xfff\n#define BIT_HI1Q_DESC_NUM_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HI1Q_DESC_NUM_8197F) << BIT_SHIFT_HI1Q_DESC_NUM_8197F)\n#define BITS_HI1Q_DESC_NUM_8197F                                               \\\n\t(BIT_MASK_HI1Q_DESC_NUM_8197F << BIT_SHIFT_HI1Q_DESC_NUM_8197F)\n#define BIT_CLEAR_HI1Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI1Q_DESC_NUM_8197F))\n#define BIT_GET_HI1Q_DESC_NUM_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8197F) & BIT_MASK_HI1Q_DESC_NUM_8197F)\n#define BIT_SET_HI1Q_DESC_NUM_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HI1Q_DESC_NUM_8197F(x) | BIT_HI1Q_DESC_NUM_8197F(v))\n\n/* 2 REG_HI2Q_TXBD_NUM_8197F */\n#define BIT_HI2Q_FLAG_8197F BIT(14)\n\n#define BIT_SHIFT_HI2Q_DESC_MODE_8197F 12\n#define BIT_MASK_HI2Q_DESC_MODE_8197F 0x3\n#define BIT_HI2Q_DESC_MODE_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HI2Q_DESC_MODE_8197F)                                 \\\n\t << BIT_SHIFT_HI2Q_DESC_MODE_8197F)\n#define BITS_HI2Q_DESC_MODE_8197F                                              \\\n\t(BIT_MASK_HI2Q_DESC_MODE_8197F << BIT_SHIFT_HI2Q_DESC_MODE_8197F)\n#define BIT_CLEAR_HI2Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI2Q_DESC_MODE_8197F))\n#define BIT_GET_HI2Q_DESC_MODE_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8197F) &                             \\\n\t BIT_MASK_HI2Q_DESC_MODE_8197F)\n#define BIT_SET_HI2Q_DESC_MODE_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HI2Q_DESC_MODE_8197F(x) | BIT_HI2Q_DESC_MODE_8197F(v))\n\n#define BIT_SHIFT_HI2Q_DESC_NUM_8197F 0\n#define BIT_MASK_HI2Q_DESC_NUM_8197F 0xfff\n#define BIT_HI2Q_DESC_NUM_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HI2Q_DESC_NUM_8197F) << BIT_SHIFT_HI2Q_DESC_NUM_8197F)\n#define BITS_HI2Q_DESC_NUM_8197F                                               \\\n\t(BIT_MASK_HI2Q_DESC_NUM_8197F << BIT_SHIFT_HI2Q_DESC_NUM_8197F)\n#define BIT_CLEAR_HI2Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI2Q_DESC_NUM_8197F))\n#define BIT_GET_HI2Q_DESC_NUM_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8197F) & BIT_MASK_HI2Q_DESC_NUM_8197F)\n#define BIT_SET_HI2Q_DESC_NUM_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HI2Q_DESC_NUM_8197F(x) | BIT_HI2Q_DESC_NUM_8197F(v))\n\n/* 2 REG_HI3Q_TXBD_NUM_8197F */\n#define BIT_HI3Q_FLAG_8197F BIT(14)\n\n#define BIT_SHIFT_HI3Q_DESC_MODE_8197F 12\n#define BIT_MASK_HI3Q_DESC_MODE_8197F 0x3\n#define BIT_HI3Q_DESC_MODE_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HI3Q_DESC_MODE_8197F)                                 \\\n\t << BIT_SHIFT_HI3Q_DESC_MODE_8197F)\n#define BITS_HI3Q_DESC_MODE_8197F                                              \\\n\t(BIT_MASK_HI3Q_DESC_MODE_8197F << BIT_SHIFT_HI3Q_DESC_MODE_8197F)\n#define BIT_CLEAR_HI3Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI3Q_DESC_MODE_8197F))\n#define BIT_GET_HI3Q_DESC_MODE_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8197F) &                             \\\n\t BIT_MASK_HI3Q_DESC_MODE_8197F)\n#define BIT_SET_HI3Q_DESC_MODE_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HI3Q_DESC_MODE_8197F(x) | BIT_HI3Q_DESC_MODE_8197F(v))\n\n#define BIT_SHIFT_HI3Q_DESC_NUM_8197F 0\n#define BIT_MASK_HI3Q_DESC_NUM_8197F 0xfff\n#define BIT_HI3Q_DESC_NUM_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HI3Q_DESC_NUM_8197F) << BIT_SHIFT_HI3Q_DESC_NUM_8197F)\n#define BITS_HI3Q_DESC_NUM_8197F                                               \\\n\t(BIT_MASK_HI3Q_DESC_NUM_8197F << BIT_SHIFT_HI3Q_DESC_NUM_8197F)\n#define BIT_CLEAR_HI3Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI3Q_DESC_NUM_8197F))\n#define BIT_GET_HI3Q_DESC_NUM_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8197F) & BIT_MASK_HI3Q_DESC_NUM_8197F)\n#define BIT_SET_HI3Q_DESC_NUM_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HI3Q_DESC_NUM_8197F(x) | BIT_HI3Q_DESC_NUM_8197F(v))\n\n/* 2 REG_HI4Q_TXBD_NUM_8197F */\n#define BIT_HI4Q_FLAG_8197F BIT(14)\n\n#define BIT_SHIFT_HI4Q_DESC_MODE_8197F 12\n#define BIT_MASK_HI4Q_DESC_MODE_8197F 0x3\n#define BIT_HI4Q_DESC_MODE_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HI4Q_DESC_MODE_8197F)                                 \\\n\t << BIT_SHIFT_HI4Q_DESC_MODE_8197F)\n#define BITS_HI4Q_DESC_MODE_8197F                                              \\\n\t(BIT_MASK_HI4Q_DESC_MODE_8197F << BIT_SHIFT_HI4Q_DESC_MODE_8197F)\n#define BIT_CLEAR_HI4Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI4Q_DESC_MODE_8197F))\n#define BIT_GET_HI4Q_DESC_MODE_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8197F) &                             \\\n\t BIT_MASK_HI4Q_DESC_MODE_8197F)\n#define BIT_SET_HI4Q_DESC_MODE_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HI4Q_DESC_MODE_8197F(x) | BIT_HI4Q_DESC_MODE_8197F(v))\n\n#define BIT_SHIFT_HI4Q_DESC_NUM_8197F 0\n#define BIT_MASK_HI4Q_DESC_NUM_8197F 0xfff\n#define BIT_HI4Q_DESC_NUM_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HI4Q_DESC_NUM_8197F) << BIT_SHIFT_HI4Q_DESC_NUM_8197F)\n#define BITS_HI4Q_DESC_NUM_8197F                                               \\\n\t(BIT_MASK_HI4Q_DESC_NUM_8197F << BIT_SHIFT_HI4Q_DESC_NUM_8197F)\n#define BIT_CLEAR_HI4Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI4Q_DESC_NUM_8197F))\n#define BIT_GET_HI4Q_DESC_NUM_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8197F) & BIT_MASK_HI4Q_DESC_NUM_8197F)\n#define BIT_SET_HI4Q_DESC_NUM_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HI4Q_DESC_NUM_8197F(x) | BIT_HI4Q_DESC_NUM_8197F(v))\n\n/* 2 REG_HI5Q_TXBD_NUM_8197F */\n#define BIT_HI5Q_FLAG_8197F BIT(14)\n\n#define BIT_SHIFT_HI5Q_DESC_MODE_8197F 12\n#define BIT_MASK_HI5Q_DESC_MODE_8197F 0x3\n#define BIT_HI5Q_DESC_MODE_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HI5Q_DESC_MODE_8197F)                                 \\\n\t << BIT_SHIFT_HI5Q_DESC_MODE_8197F)\n#define BITS_HI5Q_DESC_MODE_8197F                                              \\\n\t(BIT_MASK_HI5Q_DESC_MODE_8197F << BIT_SHIFT_HI5Q_DESC_MODE_8197F)\n#define BIT_CLEAR_HI5Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI5Q_DESC_MODE_8197F))\n#define BIT_GET_HI5Q_DESC_MODE_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8197F) &                             \\\n\t BIT_MASK_HI5Q_DESC_MODE_8197F)\n#define BIT_SET_HI5Q_DESC_MODE_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HI5Q_DESC_MODE_8197F(x) | BIT_HI5Q_DESC_MODE_8197F(v))\n\n#define BIT_SHIFT_HI5Q_DESC_NUM_8197F 0\n#define BIT_MASK_HI5Q_DESC_NUM_8197F 0xfff\n#define BIT_HI5Q_DESC_NUM_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HI5Q_DESC_NUM_8197F) << BIT_SHIFT_HI5Q_DESC_NUM_8197F)\n#define BITS_HI5Q_DESC_NUM_8197F                                               \\\n\t(BIT_MASK_HI5Q_DESC_NUM_8197F << BIT_SHIFT_HI5Q_DESC_NUM_8197F)\n#define BIT_CLEAR_HI5Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI5Q_DESC_NUM_8197F))\n#define BIT_GET_HI5Q_DESC_NUM_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8197F) & BIT_MASK_HI5Q_DESC_NUM_8197F)\n#define BIT_SET_HI5Q_DESC_NUM_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HI5Q_DESC_NUM_8197F(x) | BIT_HI5Q_DESC_NUM_8197F(v))\n\n/* 2 REG_HI6Q_TXBD_NUM_8197F */\n#define BIT_HI6Q_FLAG_8197F BIT(14)\n\n#define BIT_SHIFT_HI6Q_DESC_MODE_8197F 12\n#define BIT_MASK_HI6Q_DESC_MODE_8197F 0x3\n#define BIT_HI6Q_DESC_MODE_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HI6Q_DESC_MODE_8197F)                                 \\\n\t << BIT_SHIFT_HI6Q_DESC_MODE_8197F)\n#define BITS_HI6Q_DESC_MODE_8197F                                              \\\n\t(BIT_MASK_HI6Q_DESC_MODE_8197F << BIT_SHIFT_HI6Q_DESC_MODE_8197F)\n#define BIT_CLEAR_HI6Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI6Q_DESC_MODE_8197F))\n#define BIT_GET_HI6Q_DESC_MODE_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8197F) &                             \\\n\t BIT_MASK_HI6Q_DESC_MODE_8197F)\n#define BIT_SET_HI6Q_DESC_MODE_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HI6Q_DESC_MODE_8197F(x) | BIT_HI6Q_DESC_MODE_8197F(v))\n\n#define BIT_SHIFT_HI6Q_DESC_NUM_8197F 0\n#define BIT_MASK_HI6Q_DESC_NUM_8197F 0xfff\n#define BIT_HI6Q_DESC_NUM_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HI6Q_DESC_NUM_8197F) << BIT_SHIFT_HI6Q_DESC_NUM_8197F)\n#define BITS_HI6Q_DESC_NUM_8197F                                               \\\n\t(BIT_MASK_HI6Q_DESC_NUM_8197F << BIT_SHIFT_HI6Q_DESC_NUM_8197F)\n#define BIT_CLEAR_HI6Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI6Q_DESC_NUM_8197F))\n#define BIT_GET_HI6Q_DESC_NUM_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8197F) & BIT_MASK_HI6Q_DESC_NUM_8197F)\n#define BIT_SET_HI6Q_DESC_NUM_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HI6Q_DESC_NUM_8197F(x) | BIT_HI6Q_DESC_NUM_8197F(v))\n\n/* 2 REG_HI7Q_TXBD_NUM_8197F */\n#define BIT_HI7Q_FLAG_8197F BIT(14)\n\n#define BIT_SHIFT_HI7Q_DESC_MODE_8197F 12\n#define BIT_MASK_HI7Q_DESC_MODE_8197F 0x3\n#define BIT_HI7Q_DESC_MODE_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HI7Q_DESC_MODE_8197F)                                 \\\n\t << BIT_SHIFT_HI7Q_DESC_MODE_8197F)\n#define BITS_HI7Q_DESC_MODE_8197F                                              \\\n\t(BIT_MASK_HI7Q_DESC_MODE_8197F << BIT_SHIFT_HI7Q_DESC_MODE_8197F)\n#define BIT_CLEAR_HI7Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI7Q_DESC_MODE_8197F))\n#define BIT_GET_HI7Q_DESC_MODE_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8197F) &                             \\\n\t BIT_MASK_HI7Q_DESC_MODE_8197F)\n#define BIT_SET_HI7Q_DESC_MODE_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HI7Q_DESC_MODE_8197F(x) | BIT_HI7Q_DESC_MODE_8197F(v))\n\n#define BIT_SHIFT_HI7Q_DESC_NUM_8197F 0\n#define BIT_MASK_HI7Q_DESC_NUM_8197F 0xfff\n#define BIT_HI7Q_DESC_NUM_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HI7Q_DESC_NUM_8197F) << BIT_SHIFT_HI7Q_DESC_NUM_8197F)\n#define BITS_HI7Q_DESC_NUM_8197F                                               \\\n\t(BIT_MASK_HI7Q_DESC_NUM_8197F << BIT_SHIFT_HI7Q_DESC_NUM_8197F)\n#define BIT_CLEAR_HI7Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI7Q_DESC_NUM_8197F))\n#define BIT_GET_HI7Q_DESC_NUM_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8197F) & BIT_MASK_HI7Q_DESC_NUM_8197F)\n#define BIT_SET_HI7Q_DESC_NUM_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HI7Q_DESC_NUM_8197F(x) | BIT_HI7Q_DESC_NUM_8197F(v))\n\n/* 2 REG_TSFTIMER_HCI_8197F */\n\n#define BIT_SHIFT_TSFT2_HCI_8197F 16\n#define BIT_MASK_TSFT2_HCI_8197F 0xffff\n#define BIT_TSFT2_HCI_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_TSFT2_HCI_8197F) << BIT_SHIFT_TSFT2_HCI_8197F)\n#define BITS_TSFT2_HCI_8197F                                                   \\\n\t(BIT_MASK_TSFT2_HCI_8197F << BIT_SHIFT_TSFT2_HCI_8197F)\n#define BIT_CLEAR_TSFT2_HCI_8197F(x) ((x) & (~BITS_TSFT2_HCI_8197F))\n#define BIT_GET_TSFT2_HCI_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_TSFT2_HCI_8197F) & BIT_MASK_TSFT2_HCI_8197F)\n#define BIT_SET_TSFT2_HCI_8197F(x, v)                                          \\\n\t(BIT_CLEAR_TSFT2_HCI_8197F(x) | BIT_TSFT2_HCI_8197F(v))\n\n#define BIT_SHIFT_TSFT1_HCI_8197F 0\n#define BIT_MASK_TSFT1_HCI_8197F 0xffff\n#define BIT_TSFT1_HCI_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_TSFT1_HCI_8197F) << BIT_SHIFT_TSFT1_HCI_8197F)\n#define BITS_TSFT1_HCI_8197F                                                   \\\n\t(BIT_MASK_TSFT1_HCI_8197F << BIT_SHIFT_TSFT1_HCI_8197F)\n#define BIT_CLEAR_TSFT1_HCI_8197F(x) ((x) & (~BITS_TSFT1_HCI_8197F))\n#define BIT_GET_TSFT1_HCI_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_TSFT1_HCI_8197F) & BIT_MASK_TSFT1_HCI_8197F)\n#define BIT_SET_TSFT1_HCI_8197F(x, v)                                          \\\n\t(BIT_CLEAR_TSFT1_HCI_8197F(x) | BIT_TSFT1_HCI_8197F(v))\n\n/* 2 REG_BD_RWPTR_CLR_8197F */\n#define BIT_CLR_HI7Q_HW_IDX_8197F BIT(29)\n#define BIT_CLR_HI6Q_HW_IDX_8197F BIT(28)\n#define BIT_CLR_HI5Q_HW_IDX_8197F BIT(27)\n#define BIT_CLR_HI4Q_HW_IDX_8197F BIT(26)\n#define BIT_CLR_HI3Q_HW_IDX_8197F BIT(25)\n#define BIT_CLR_HI2Q_HW_IDX_8197F BIT(24)\n#define BIT_CLR_HI1Q_HW_IDX_8197F BIT(23)\n#define BIT_CLR_HI0Q_HW_IDX_8197F BIT(22)\n#define BIT_CLR_BKQ_HW_IDX_8197F BIT(21)\n#define BIT_CLR_BEQ_HW_IDX_8197F BIT(20)\n#define BIT_CLR_VIQ_HW_IDX_8197F BIT(19)\n#define BIT_CLR_VOQ_HW_IDX_8197F BIT(18)\n#define BIT_CLR_MGQ_HW_IDX_8197F BIT(17)\n#define BIT_CLR_RXQ_HW_IDX_8197F BIT(16)\n#define BIT_CLR_HI7Q_HOST_IDX_8197F BIT(13)\n#define BIT_CLR_HI6Q_HOST_IDX_8197F BIT(12)\n#define BIT_CLR_HI5Q_HOST_IDX_8197F BIT(11)\n#define BIT_CLR_HI4Q_HOST_IDX_8197F BIT(10)\n#define BIT_CLR_HI3Q_HOST_IDX_8197F BIT(9)\n#define BIT_CLR_HI2Q_HOST_IDX_8197F BIT(8)\n#define BIT_CLR_HI1Q_HOST_IDX_8197F BIT(7)\n#define BIT_CLR_HI0Q_HOST_IDX_8197F BIT(6)\n#define BIT_CLR_BKQ_HOST_IDX_8197F BIT(5)\n#define BIT_CLR_BEQ_HOST_IDX_8197F BIT(4)\n#define BIT_CLR_VIQ_HOST_IDX_8197F BIT(3)\n#define BIT_CLR_VOQ_HOST_IDX_8197F BIT(2)\n#define BIT_CLR_MGQ_HOST_IDX_8197F BIT(1)\n#define BIT_CLR_RXQ_HOST_IDX_8197F BIT(0)\n\n/* 2 REG_VOQ_TXBD_IDX_8197F */\n\n#define BIT_SHIFT_VOQ_HW_IDX_8197F 16\n#define BIT_MASK_VOQ_HW_IDX_8197F 0xfff\n#define BIT_VOQ_HW_IDX_8197F(x)                                                \\\n\t(((x) & BIT_MASK_VOQ_HW_IDX_8197F) << BIT_SHIFT_VOQ_HW_IDX_8197F)\n#define BITS_VOQ_HW_IDX_8197F                                                  \\\n\t(BIT_MASK_VOQ_HW_IDX_8197F << BIT_SHIFT_VOQ_HW_IDX_8197F)\n#define BIT_CLEAR_VOQ_HW_IDX_8197F(x) ((x) & (~BITS_VOQ_HW_IDX_8197F))\n#define BIT_GET_VOQ_HW_IDX_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_VOQ_HW_IDX_8197F) & BIT_MASK_VOQ_HW_IDX_8197F)\n#define BIT_SET_VOQ_HW_IDX_8197F(x, v)                                         \\\n\t(BIT_CLEAR_VOQ_HW_IDX_8197F(x) | BIT_VOQ_HW_IDX_8197F(v))\n\n#define BIT_SHIFT_VOQ_HOST_IDX_8197F 0\n#define BIT_MASK_VOQ_HOST_IDX_8197F 0xfff\n#define BIT_VOQ_HOST_IDX_8197F(x)                                              \\\n\t(((x) & BIT_MASK_VOQ_HOST_IDX_8197F) << BIT_SHIFT_VOQ_HOST_IDX_8197F)\n#define BITS_VOQ_HOST_IDX_8197F                                                \\\n\t(BIT_MASK_VOQ_HOST_IDX_8197F << BIT_SHIFT_VOQ_HOST_IDX_8197F)\n#define BIT_CLEAR_VOQ_HOST_IDX_8197F(x) ((x) & (~BITS_VOQ_HOST_IDX_8197F))\n#define BIT_GET_VOQ_HOST_IDX_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_VOQ_HOST_IDX_8197F) & BIT_MASK_VOQ_HOST_IDX_8197F)\n#define BIT_SET_VOQ_HOST_IDX_8197F(x, v)                                       \\\n\t(BIT_CLEAR_VOQ_HOST_IDX_8197F(x) | BIT_VOQ_HOST_IDX_8197F(v))\n\n/* 2 REG_VIQ_TXBD_IDX_8197F */\n\n#define BIT_SHIFT_VIQ_HW_IDX_8197F 16\n#define BIT_MASK_VIQ_HW_IDX_8197F 0xfff\n#define BIT_VIQ_HW_IDX_8197F(x)                                                \\\n\t(((x) & BIT_MASK_VIQ_HW_IDX_8197F) << BIT_SHIFT_VIQ_HW_IDX_8197F)\n#define BITS_VIQ_HW_IDX_8197F                                                  \\\n\t(BIT_MASK_VIQ_HW_IDX_8197F << BIT_SHIFT_VIQ_HW_IDX_8197F)\n#define BIT_CLEAR_VIQ_HW_IDX_8197F(x) ((x) & (~BITS_VIQ_HW_IDX_8197F))\n#define BIT_GET_VIQ_HW_IDX_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_VIQ_HW_IDX_8197F) & BIT_MASK_VIQ_HW_IDX_8197F)\n#define BIT_SET_VIQ_HW_IDX_8197F(x, v)                                         \\\n\t(BIT_CLEAR_VIQ_HW_IDX_8197F(x) | BIT_VIQ_HW_IDX_8197F(v))\n\n#define BIT_SHIFT_VIQ_HOST_IDX_8197F 0\n#define BIT_MASK_VIQ_HOST_IDX_8197F 0xfff\n#define BIT_VIQ_HOST_IDX_8197F(x)                                              \\\n\t(((x) & BIT_MASK_VIQ_HOST_IDX_8197F) << BIT_SHIFT_VIQ_HOST_IDX_8197F)\n#define BITS_VIQ_HOST_IDX_8197F                                                \\\n\t(BIT_MASK_VIQ_HOST_IDX_8197F << BIT_SHIFT_VIQ_HOST_IDX_8197F)\n#define BIT_CLEAR_VIQ_HOST_IDX_8197F(x) ((x) & (~BITS_VIQ_HOST_IDX_8197F))\n#define BIT_GET_VIQ_HOST_IDX_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_VIQ_HOST_IDX_8197F) & BIT_MASK_VIQ_HOST_IDX_8197F)\n#define BIT_SET_VIQ_HOST_IDX_8197F(x, v)                                       \\\n\t(BIT_CLEAR_VIQ_HOST_IDX_8197F(x) | BIT_VIQ_HOST_IDX_8197F(v))\n\n/* 2 REG_BEQ_TXBD_IDX_8197F */\n\n#define BIT_SHIFT_BEQ_HW_IDX_8197F 16\n#define BIT_MASK_BEQ_HW_IDX_8197F 0xfff\n#define BIT_BEQ_HW_IDX_8197F(x)                                                \\\n\t(((x) & BIT_MASK_BEQ_HW_IDX_8197F) << BIT_SHIFT_BEQ_HW_IDX_8197F)\n#define BITS_BEQ_HW_IDX_8197F                                                  \\\n\t(BIT_MASK_BEQ_HW_IDX_8197F << BIT_SHIFT_BEQ_HW_IDX_8197F)\n#define BIT_CLEAR_BEQ_HW_IDX_8197F(x) ((x) & (~BITS_BEQ_HW_IDX_8197F))\n#define BIT_GET_BEQ_HW_IDX_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_BEQ_HW_IDX_8197F) & BIT_MASK_BEQ_HW_IDX_8197F)\n#define BIT_SET_BEQ_HW_IDX_8197F(x, v)                                         \\\n\t(BIT_CLEAR_BEQ_HW_IDX_8197F(x) | BIT_BEQ_HW_IDX_8197F(v))\n\n#define BIT_SHIFT_BEQ_HOST_IDX_8197F 0\n#define BIT_MASK_BEQ_HOST_IDX_8197F 0xfff\n#define BIT_BEQ_HOST_IDX_8197F(x)                                              \\\n\t(((x) & BIT_MASK_BEQ_HOST_IDX_8197F) << BIT_SHIFT_BEQ_HOST_IDX_8197F)\n#define BITS_BEQ_HOST_IDX_8197F                                                \\\n\t(BIT_MASK_BEQ_HOST_IDX_8197F << BIT_SHIFT_BEQ_HOST_IDX_8197F)\n#define BIT_CLEAR_BEQ_HOST_IDX_8197F(x) ((x) & (~BITS_BEQ_HOST_IDX_8197F))\n#define BIT_GET_BEQ_HOST_IDX_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_BEQ_HOST_IDX_8197F) & BIT_MASK_BEQ_HOST_IDX_8197F)\n#define BIT_SET_BEQ_HOST_IDX_8197F(x, v)                                       \\\n\t(BIT_CLEAR_BEQ_HOST_IDX_8197F(x) | BIT_BEQ_HOST_IDX_8197F(v))\n\n/* 2 REG_BKQ_TXBD_IDX_8197F */\n\n#define BIT_SHIFT_BKQ_HW_IDX_8197F 16\n#define BIT_MASK_BKQ_HW_IDX_8197F 0xfff\n#define BIT_BKQ_HW_IDX_8197F(x)                                                \\\n\t(((x) & BIT_MASK_BKQ_HW_IDX_8197F) << BIT_SHIFT_BKQ_HW_IDX_8197F)\n#define BITS_BKQ_HW_IDX_8197F                                                  \\\n\t(BIT_MASK_BKQ_HW_IDX_8197F << BIT_SHIFT_BKQ_HW_IDX_8197F)\n#define BIT_CLEAR_BKQ_HW_IDX_8197F(x) ((x) & (~BITS_BKQ_HW_IDX_8197F))\n#define BIT_GET_BKQ_HW_IDX_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_BKQ_HW_IDX_8197F) & BIT_MASK_BKQ_HW_IDX_8197F)\n#define BIT_SET_BKQ_HW_IDX_8197F(x, v)                                         \\\n\t(BIT_CLEAR_BKQ_HW_IDX_8197F(x) | BIT_BKQ_HW_IDX_8197F(v))\n\n#define BIT_SHIFT_BKQ_HOST_IDX_8197F 0\n#define BIT_MASK_BKQ_HOST_IDX_8197F 0xfff\n#define BIT_BKQ_HOST_IDX_8197F(x)                                              \\\n\t(((x) & BIT_MASK_BKQ_HOST_IDX_8197F) << BIT_SHIFT_BKQ_HOST_IDX_8197F)\n#define BITS_BKQ_HOST_IDX_8197F                                                \\\n\t(BIT_MASK_BKQ_HOST_IDX_8197F << BIT_SHIFT_BKQ_HOST_IDX_8197F)\n#define BIT_CLEAR_BKQ_HOST_IDX_8197F(x) ((x) & (~BITS_BKQ_HOST_IDX_8197F))\n#define BIT_GET_BKQ_HOST_IDX_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_BKQ_HOST_IDX_8197F) & BIT_MASK_BKQ_HOST_IDX_8197F)\n#define BIT_SET_BKQ_HOST_IDX_8197F(x, v)                                       \\\n\t(BIT_CLEAR_BKQ_HOST_IDX_8197F(x) | BIT_BKQ_HOST_IDX_8197F(v))\n\n/* 2 REG_MGQ_TXBD_IDX_8197F */\n\n#define BIT_SHIFT_MGQ_HW_IDX_8197F 16\n#define BIT_MASK_MGQ_HW_IDX_8197F 0xfff\n#define BIT_MGQ_HW_IDX_8197F(x)                                                \\\n\t(((x) & BIT_MASK_MGQ_HW_IDX_8197F) << BIT_SHIFT_MGQ_HW_IDX_8197F)\n#define BITS_MGQ_HW_IDX_8197F                                                  \\\n\t(BIT_MASK_MGQ_HW_IDX_8197F << BIT_SHIFT_MGQ_HW_IDX_8197F)\n#define BIT_CLEAR_MGQ_HW_IDX_8197F(x) ((x) & (~BITS_MGQ_HW_IDX_8197F))\n#define BIT_GET_MGQ_HW_IDX_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_MGQ_HW_IDX_8197F) & BIT_MASK_MGQ_HW_IDX_8197F)\n#define BIT_SET_MGQ_HW_IDX_8197F(x, v)                                         \\\n\t(BIT_CLEAR_MGQ_HW_IDX_8197F(x) | BIT_MGQ_HW_IDX_8197F(v))\n\n#define BIT_SHIFT_MGQ_HOST_IDX_8197F 0\n#define BIT_MASK_MGQ_HOST_IDX_8197F 0xfff\n#define BIT_MGQ_HOST_IDX_8197F(x)                                              \\\n\t(((x) & BIT_MASK_MGQ_HOST_IDX_8197F) << BIT_SHIFT_MGQ_HOST_IDX_8197F)\n#define BITS_MGQ_HOST_IDX_8197F                                                \\\n\t(BIT_MASK_MGQ_HOST_IDX_8197F << BIT_SHIFT_MGQ_HOST_IDX_8197F)\n#define BIT_CLEAR_MGQ_HOST_IDX_8197F(x) ((x) & (~BITS_MGQ_HOST_IDX_8197F))\n#define BIT_GET_MGQ_HOST_IDX_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_MGQ_HOST_IDX_8197F) & BIT_MASK_MGQ_HOST_IDX_8197F)\n#define BIT_SET_MGQ_HOST_IDX_8197F(x, v)                                       \\\n\t(BIT_CLEAR_MGQ_HOST_IDX_8197F(x) | BIT_MGQ_HOST_IDX_8197F(v))\n\n/* 2 REG_RXQ_RXBD_IDX_8197F */\n\n#define BIT_SHIFT_RXQ_HW_IDX_8197F 16\n#define BIT_MASK_RXQ_HW_IDX_8197F 0xfff\n#define BIT_RXQ_HW_IDX_8197F(x)                                                \\\n\t(((x) & BIT_MASK_RXQ_HW_IDX_8197F) << BIT_SHIFT_RXQ_HW_IDX_8197F)\n#define BITS_RXQ_HW_IDX_8197F                                                  \\\n\t(BIT_MASK_RXQ_HW_IDX_8197F << BIT_SHIFT_RXQ_HW_IDX_8197F)\n#define BIT_CLEAR_RXQ_HW_IDX_8197F(x) ((x) & (~BITS_RXQ_HW_IDX_8197F))\n#define BIT_GET_RXQ_HW_IDX_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXQ_HW_IDX_8197F) & BIT_MASK_RXQ_HW_IDX_8197F)\n#define BIT_SET_RXQ_HW_IDX_8197F(x, v)                                         \\\n\t(BIT_CLEAR_RXQ_HW_IDX_8197F(x) | BIT_RXQ_HW_IDX_8197F(v))\n\n#define BIT_SHIFT_RXQ_HOST_IDX_8197F 0\n#define BIT_MASK_RXQ_HOST_IDX_8197F 0xfff\n#define BIT_RXQ_HOST_IDX_8197F(x)                                              \\\n\t(((x) & BIT_MASK_RXQ_HOST_IDX_8197F) << BIT_SHIFT_RXQ_HOST_IDX_8197F)\n#define BITS_RXQ_HOST_IDX_8197F                                                \\\n\t(BIT_MASK_RXQ_HOST_IDX_8197F << BIT_SHIFT_RXQ_HOST_IDX_8197F)\n#define BIT_CLEAR_RXQ_HOST_IDX_8197F(x) ((x) & (~BITS_RXQ_HOST_IDX_8197F))\n#define BIT_GET_RXQ_HOST_IDX_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXQ_HOST_IDX_8197F) & BIT_MASK_RXQ_HOST_IDX_8197F)\n#define BIT_SET_RXQ_HOST_IDX_8197F(x, v)                                       \\\n\t(BIT_CLEAR_RXQ_HOST_IDX_8197F(x) | BIT_RXQ_HOST_IDX_8197F(v))\n\n/* 2 REG_HI0Q_TXBD_IDX_8197F */\n\n#define BIT_SHIFT_HI0Q_HW_IDX_8197F 16\n#define BIT_MASK_HI0Q_HW_IDX_8197F 0xfff\n#define BIT_HI0Q_HW_IDX_8197F(x)                                               \\\n\t(((x) & BIT_MASK_HI0Q_HW_IDX_8197F) << BIT_SHIFT_HI0Q_HW_IDX_8197F)\n#define BITS_HI0Q_HW_IDX_8197F                                                 \\\n\t(BIT_MASK_HI0Q_HW_IDX_8197F << BIT_SHIFT_HI0Q_HW_IDX_8197F)\n#define BIT_CLEAR_HI0Q_HW_IDX_8197F(x) ((x) & (~BITS_HI0Q_HW_IDX_8197F))\n#define BIT_GET_HI0Q_HW_IDX_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI0Q_HW_IDX_8197F) & BIT_MASK_HI0Q_HW_IDX_8197F)\n#define BIT_SET_HI0Q_HW_IDX_8197F(x, v)                                        \\\n\t(BIT_CLEAR_HI0Q_HW_IDX_8197F(x) | BIT_HI0Q_HW_IDX_8197F(v))\n\n#define BIT_SHIFT_HI0Q_HOST_IDX_8197F 0\n#define BIT_MASK_HI0Q_HOST_IDX_8197F 0xfff\n#define BIT_HI0Q_HOST_IDX_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HI0Q_HOST_IDX_8197F) << BIT_SHIFT_HI0Q_HOST_IDX_8197F)\n#define BITS_HI0Q_HOST_IDX_8197F                                               \\\n\t(BIT_MASK_HI0Q_HOST_IDX_8197F << BIT_SHIFT_HI0Q_HOST_IDX_8197F)\n#define BIT_CLEAR_HI0Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI0Q_HOST_IDX_8197F))\n#define BIT_GET_HI0Q_HOST_IDX_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8197F) & BIT_MASK_HI0Q_HOST_IDX_8197F)\n#define BIT_SET_HI0Q_HOST_IDX_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HI0Q_HOST_IDX_8197F(x) | BIT_HI0Q_HOST_IDX_8197F(v))\n\n/* 2 REG_HI1Q_TXBD_IDX_8197F */\n\n#define BIT_SHIFT_HI1Q_HW_IDX_8197F 16\n#define BIT_MASK_HI1Q_HW_IDX_8197F 0xfff\n#define BIT_HI1Q_HW_IDX_8197F(x)                                               \\\n\t(((x) & BIT_MASK_HI1Q_HW_IDX_8197F) << BIT_SHIFT_HI1Q_HW_IDX_8197F)\n#define BITS_HI1Q_HW_IDX_8197F                                                 \\\n\t(BIT_MASK_HI1Q_HW_IDX_8197F << BIT_SHIFT_HI1Q_HW_IDX_8197F)\n#define BIT_CLEAR_HI1Q_HW_IDX_8197F(x) ((x) & (~BITS_HI1Q_HW_IDX_8197F))\n#define BIT_GET_HI1Q_HW_IDX_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI1Q_HW_IDX_8197F) & BIT_MASK_HI1Q_HW_IDX_8197F)\n#define BIT_SET_HI1Q_HW_IDX_8197F(x, v)                                        \\\n\t(BIT_CLEAR_HI1Q_HW_IDX_8197F(x) | BIT_HI1Q_HW_IDX_8197F(v))\n\n#define BIT_SHIFT_HI1Q_HOST_IDX_8197F 0\n#define BIT_MASK_HI1Q_HOST_IDX_8197F 0xfff\n#define BIT_HI1Q_HOST_IDX_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HI1Q_HOST_IDX_8197F) << BIT_SHIFT_HI1Q_HOST_IDX_8197F)\n#define BITS_HI1Q_HOST_IDX_8197F                                               \\\n\t(BIT_MASK_HI1Q_HOST_IDX_8197F << BIT_SHIFT_HI1Q_HOST_IDX_8197F)\n#define BIT_CLEAR_HI1Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI1Q_HOST_IDX_8197F))\n#define BIT_GET_HI1Q_HOST_IDX_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8197F) & BIT_MASK_HI1Q_HOST_IDX_8197F)\n#define BIT_SET_HI1Q_HOST_IDX_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HI1Q_HOST_IDX_8197F(x) | BIT_HI1Q_HOST_IDX_8197F(v))\n\n/* 2 REG_HI2Q_TXBD_IDX_8197F */\n\n#define BIT_SHIFT_HI2Q_HW_IDX_8197F 16\n#define BIT_MASK_HI2Q_HW_IDX_8197F 0xfff\n#define BIT_HI2Q_HW_IDX_8197F(x)                                               \\\n\t(((x) & BIT_MASK_HI2Q_HW_IDX_8197F) << BIT_SHIFT_HI2Q_HW_IDX_8197F)\n#define BITS_HI2Q_HW_IDX_8197F                                                 \\\n\t(BIT_MASK_HI2Q_HW_IDX_8197F << BIT_SHIFT_HI2Q_HW_IDX_8197F)\n#define BIT_CLEAR_HI2Q_HW_IDX_8197F(x) ((x) & (~BITS_HI2Q_HW_IDX_8197F))\n#define BIT_GET_HI2Q_HW_IDX_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI2Q_HW_IDX_8197F) & BIT_MASK_HI2Q_HW_IDX_8197F)\n#define BIT_SET_HI2Q_HW_IDX_8197F(x, v)                                        \\\n\t(BIT_CLEAR_HI2Q_HW_IDX_8197F(x) | BIT_HI2Q_HW_IDX_8197F(v))\n\n#define BIT_SHIFT_HI2Q_HOST_IDX_8197F 0\n#define BIT_MASK_HI2Q_HOST_IDX_8197F 0xfff\n#define BIT_HI2Q_HOST_IDX_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HI2Q_HOST_IDX_8197F) << BIT_SHIFT_HI2Q_HOST_IDX_8197F)\n#define BITS_HI2Q_HOST_IDX_8197F                                               \\\n\t(BIT_MASK_HI2Q_HOST_IDX_8197F << BIT_SHIFT_HI2Q_HOST_IDX_8197F)\n#define BIT_CLEAR_HI2Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI2Q_HOST_IDX_8197F))\n#define BIT_GET_HI2Q_HOST_IDX_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8197F) & BIT_MASK_HI2Q_HOST_IDX_8197F)\n#define BIT_SET_HI2Q_HOST_IDX_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HI2Q_HOST_IDX_8197F(x) | BIT_HI2Q_HOST_IDX_8197F(v))\n\n/* 2 REG_HI3Q_TXBD_IDX_8197F */\n\n#define BIT_SHIFT_HI3Q_HW_IDX_8197F 16\n#define BIT_MASK_HI3Q_HW_IDX_8197F 0xfff\n#define BIT_HI3Q_HW_IDX_8197F(x)                                               \\\n\t(((x) & BIT_MASK_HI3Q_HW_IDX_8197F) << BIT_SHIFT_HI3Q_HW_IDX_8197F)\n#define BITS_HI3Q_HW_IDX_8197F                                                 \\\n\t(BIT_MASK_HI3Q_HW_IDX_8197F << BIT_SHIFT_HI3Q_HW_IDX_8197F)\n#define BIT_CLEAR_HI3Q_HW_IDX_8197F(x) ((x) & (~BITS_HI3Q_HW_IDX_8197F))\n#define BIT_GET_HI3Q_HW_IDX_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI3Q_HW_IDX_8197F) & BIT_MASK_HI3Q_HW_IDX_8197F)\n#define BIT_SET_HI3Q_HW_IDX_8197F(x, v)                                        \\\n\t(BIT_CLEAR_HI3Q_HW_IDX_8197F(x) | BIT_HI3Q_HW_IDX_8197F(v))\n\n#define BIT_SHIFT_HI3Q_HOST_IDX_8197F 0\n#define BIT_MASK_HI3Q_HOST_IDX_8197F 0xfff\n#define BIT_HI3Q_HOST_IDX_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HI3Q_HOST_IDX_8197F) << BIT_SHIFT_HI3Q_HOST_IDX_8197F)\n#define BITS_HI3Q_HOST_IDX_8197F                                               \\\n\t(BIT_MASK_HI3Q_HOST_IDX_8197F << BIT_SHIFT_HI3Q_HOST_IDX_8197F)\n#define BIT_CLEAR_HI3Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI3Q_HOST_IDX_8197F))\n#define BIT_GET_HI3Q_HOST_IDX_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8197F) & BIT_MASK_HI3Q_HOST_IDX_8197F)\n#define BIT_SET_HI3Q_HOST_IDX_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HI3Q_HOST_IDX_8197F(x) | BIT_HI3Q_HOST_IDX_8197F(v))\n\n/* 2 REG_HI4Q_TXBD_IDX_8197F */\n\n#define BIT_SHIFT_HI4Q_HW_IDX_8197F 16\n#define BIT_MASK_HI4Q_HW_IDX_8197F 0xfff\n#define BIT_HI4Q_HW_IDX_8197F(x)                                               \\\n\t(((x) & BIT_MASK_HI4Q_HW_IDX_8197F) << BIT_SHIFT_HI4Q_HW_IDX_8197F)\n#define BITS_HI4Q_HW_IDX_8197F                                                 \\\n\t(BIT_MASK_HI4Q_HW_IDX_8197F << BIT_SHIFT_HI4Q_HW_IDX_8197F)\n#define BIT_CLEAR_HI4Q_HW_IDX_8197F(x) ((x) & (~BITS_HI4Q_HW_IDX_8197F))\n#define BIT_GET_HI4Q_HW_IDX_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI4Q_HW_IDX_8197F) & BIT_MASK_HI4Q_HW_IDX_8197F)\n#define BIT_SET_HI4Q_HW_IDX_8197F(x, v)                                        \\\n\t(BIT_CLEAR_HI4Q_HW_IDX_8197F(x) | BIT_HI4Q_HW_IDX_8197F(v))\n\n#define BIT_SHIFT_HI4Q_HOST_IDX_8197F 0\n#define BIT_MASK_HI4Q_HOST_IDX_8197F 0xfff\n#define BIT_HI4Q_HOST_IDX_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HI4Q_HOST_IDX_8197F) << BIT_SHIFT_HI4Q_HOST_IDX_8197F)\n#define BITS_HI4Q_HOST_IDX_8197F                                               \\\n\t(BIT_MASK_HI4Q_HOST_IDX_8197F << BIT_SHIFT_HI4Q_HOST_IDX_8197F)\n#define BIT_CLEAR_HI4Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI4Q_HOST_IDX_8197F))\n#define BIT_GET_HI4Q_HOST_IDX_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8197F) & BIT_MASK_HI4Q_HOST_IDX_8197F)\n#define BIT_SET_HI4Q_HOST_IDX_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HI4Q_HOST_IDX_8197F(x) | BIT_HI4Q_HOST_IDX_8197F(v))\n\n/* 2 REG_HI5Q_TXBD_IDX_8197F */\n\n#define BIT_SHIFT_HI5Q_HW_IDX_8197F 16\n#define BIT_MASK_HI5Q_HW_IDX_8197F 0xfff\n#define BIT_HI5Q_HW_IDX_8197F(x)                                               \\\n\t(((x) & BIT_MASK_HI5Q_HW_IDX_8197F) << BIT_SHIFT_HI5Q_HW_IDX_8197F)\n#define BITS_HI5Q_HW_IDX_8197F                                                 \\\n\t(BIT_MASK_HI5Q_HW_IDX_8197F << BIT_SHIFT_HI5Q_HW_IDX_8197F)\n#define BIT_CLEAR_HI5Q_HW_IDX_8197F(x) ((x) & (~BITS_HI5Q_HW_IDX_8197F))\n#define BIT_GET_HI5Q_HW_IDX_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI5Q_HW_IDX_8197F) & BIT_MASK_HI5Q_HW_IDX_8197F)\n#define BIT_SET_HI5Q_HW_IDX_8197F(x, v)                                        \\\n\t(BIT_CLEAR_HI5Q_HW_IDX_8197F(x) | BIT_HI5Q_HW_IDX_8197F(v))\n\n#define BIT_SHIFT_HI5Q_HOST_IDX_8197F 0\n#define BIT_MASK_HI5Q_HOST_IDX_8197F 0xfff\n#define BIT_HI5Q_HOST_IDX_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HI5Q_HOST_IDX_8197F) << BIT_SHIFT_HI5Q_HOST_IDX_8197F)\n#define BITS_HI5Q_HOST_IDX_8197F                                               \\\n\t(BIT_MASK_HI5Q_HOST_IDX_8197F << BIT_SHIFT_HI5Q_HOST_IDX_8197F)\n#define BIT_CLEAR_HI5Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI5Q_HOST_IDX_8197F))\n#define BIT_GET_HI5Q_HOST_IDX_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8197F) & BIT_MASK_HI5Q_HOST_IDX_8197F)\n#define BIT_SET_HI5Q_HOST_IDX_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HI5Q_HOST_IDX_8197F(x) | BIT_HI5Q_HOST_IDX_8197F(v))\n\n/* 2 REG_HI6Q_TXBD_IDX_8197F */\n\n#define BIT_SHIFT_HI6Q_HW_IDX_8197F 16\n#define BIT_MASK_HI6Q_HW_IDX_8197F 0xfff\n#define BIT_HI6Q_HW_IDX_8197F(x)                                               \\\n\t(((x) & BIT_MASK_HI6Q_HW_IDX_8197F) << BIT_SHIFT_HI6Q_HW_IDX_8197F)\n#define BITS_HI6Q_HW_IDX_8197F                                                 \\\n\t(BIT_MASK_HI6Q_HW_IDX_8197F << BIT_SHIFT_HI6Q_HW_IDX_8197F)\n#define BIT_CLEAR_HI6Q_HW_IDX_8197F(x) ((x) & (~BITS_HI6Q_HW_IDX_8197F))\n#define BIT_GET_HI6Q_HW_IDX_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI6Q_HW_IDX_8197F) & BIT_MASK_HI6Q_HW_IDX_8197F)\n#define BIT_SET_HI6Q_HW_IDX_8197F(x, v)                                        \\\n\t(BIT_CLEAR_HI6Q_HW_IDX_8197F(x) | BIT_HI6Q_HW_IDX_8197F(v))\n\n#define BIT_SHIFT_HI6Q_HOST_IDX_8197F 0\n#define BIT_MASK_HI6Q_HOST_IDX_8197F 0xfff\n#define BIT_HI6Q_HOST_IDX_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HI6Q_HOST_IDX_8197F) << BIT_SHIFT_HI6Q_HOST_IDX_8197F)\n#define BITS_HI6Q_HOST_IDX_8197F                                               \\\n\t(BIT_MASK_HI6Q_HOST_IDX_8197F << BIT_SHIFT_HI6Q_HOST_IDX_8197F)\n#define BIT_CLEAR_HI6Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI6Q_HOST_IDX_8197F))\n#define BIT_GET_HI6Q_HOST_IDX_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8197F) & BIT_MASK_HI6Q_HOST_IDX_8197F)\n#define BIT_SET_HI6Q_HOST_IDX_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HI6Q_HOST_IDX_8197F(x) | BIT_HI6Q_HOST_IDX_8197F(v))\n\n/* 2 REG_HI7Q_TXBD_IDX_8197F */\n\n#define BIT_SHIFT_HI7Q_HW_IDX_8197F 16\n#define BIT_MASK_HI7Q_HW_IDX_8197F 0xfff\n#define BIT_HI7Q_HW_IDX_8197F(x)                                               \\\n\t(((x) & BIT_MASK_HI7Q_HW_IDX_8197F) << BIT_SHIFT_HI7Q_HW_IDX_8197F)\n#define BITS_HI7Q_HW_IDX_8197F                                                 \\\n\t(BIT_MASK_HI7Q_HW_IDX_8197F << BIT_SHIFT_HI7Q_HW_IDX_8197F)\n#define BIT_CLEAR_HI7Q_HW_IDX_8197F(x) ((x) & (~BITS_HI7Q_HW_IDX_8197F))\n#define BIT_GET_HI7Q_HW_IDX_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI7Q_HW_IDX_8197F) & BIT_MASK_HI7Q_HW_IDX_8197F)\n#define BIT_SET_HI7Q_HW_IDX_8197F(x, v)                                        \\\n\t(BIT_CLEAR_HI7Q_HW_IDX_8197F(x) | BIT_HI7Q_HW_IDX_8197F(v))\n\n#define BIT_SHIFT_HI7Q_HOST_IDX_8197F 0\n#define BIT_MASK_HI7Q_HOST_IDX_8197F 0xfff\n#define BIT_HI7Q_HOST_IDX_8197F(x)                                             \\\n\t(((x) & BIT_MASK_HI7Q_HOST_IDX_8197F) << BIT_SHIFT_HI7Q_HOST_IDX_8197F)\n#define BITS_HI7Q_HOST_IDX_8197F                                               \\\n\t(BIT_MASK_HI7Q_HOST_IDX_8197F << BIT_SHIFT_HI7Q_HOST_IDX_8197F)\n#define BIT_CLEAR_HI7Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI7Q_HOST_IDX_8197F))\n#define BIT_GET_HI7Q_HOST_IDX_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8197F) & BIT_MASK_HI7Q_HOST_IDX_8197F)\n#define BIT_SET_HI7Q_HOST_IDX_8197F(x, v)                                      \\\n\t(BIT_CLEAR_HI7Q_HOST_IDX_8197F(x) | BIT_HI7Q_HOST_IDX_8197F(v))\n\n/* 2 REG_DBG_SEL_V1_8197F */\n\n#define BIT_SHIFT_DBG_SEL_8197F 0\n#define BIT_MASK_DBG_SEL_8197F 0xff\n#define BIT_DBG_SEL_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_DBG_SEL_8197F) << BIT_SHIFT_DBG_SEL_8197F)\n#define BITS_DBG_SEL_8197F (BIT_MASK_DBG_SEL_8197F << BIT_SHIFT_DBG_SEL_8197F)\n#define BIT_CLEAR_DBG_SEL_8197F(x) ((x) & (~BITS_DBG_SEL_8197F))\n#define BIT_GET_DBG_SEL_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_DBG_SEL_8197F) & BIT_MASK_DBG_SEL_8197F)\n#define BIT_SET_DBG_SEL_8197F(x, v)                                            \\\n\t(BIT_CLEAR_DBG_SEL_8197F(x) | BIT_DBG_SEL_8197F(v))\n\n/* 2 REG_HCI_HRPWM1_V1_8197F */\n\n#define BIT_SHIFT_HCI_HRPWM_8197F 0\n#define BIT_MASK_HCI_HRPWM_8197F 0xff\n#define BIT_HCI_HRPWM_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_HCI_HRPWM_8197F) << BIT_SHIFT_HCI_HRPWM_8197F)\n#define BITS_HCI_HRPWM_8197F                                                   \\\n\t(BIT_MASK_HCI_HRPWM_8197F << BIT_SHIFT_HCI_HRPWM_8197F)\n#define BIT_CLEAR_HCI_HRPWM_8197F(x) ((x) & (~BITS_HCI_HRPWM_8197F))\n#define BIT_GET_HCI_HRPWM_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_HCI_HRPWM_8197F) & BIT_MASK_HCI_HRPWM_8197F)\n#define BIT_SET_HCI_HRPWM_8197F(x, v)                                          \\\n\t(BIT_CLEAR_HCI_HRPWM_8197F(x) | BIT_HCI_HRPWM_8197F(v))\n\n/* 2 REG_HCI_HCPWM1_V1_8197F */\n\n#define BIT_SHIFT_HCI_HCPWM_8197F 0\n#define BIT_MASK_HCI_HCPWM_8197F 0xff\n#define BIT_HCI_HCPWM_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_HCI_HCPWM_8197F) << BIT_SHIFT_HCI_HCPWM_8197F)\n#define BITS_HCI_HCPWM_8197F                                                   \\\n\t(BIT_MASK_HCI_HCPWM_8197F << BIT_SHIFT_HCI_HCPWM_8197F)\n#define BIT_CLEAR_HCI_HCPWM_8197F(x) ((x) & (~BITS_HCI_HCPWM_8197F))\n#define BIT_GET_HCI_HCPWM_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_HCI_HCPWM_8197F) & BIT_MASK_HCI_HCPWM_8197F)\n#define BIT_SET_HCI_HCPWM_8197F(x, v)                                          \\\n\t(BIT_CLEAR_HCI_HCPWM_8197F(x) | BIT_HCI_HCPWM_8197F(v))\n\n/* 2 REG_HCI_CTRL2_8197F */\n#define BIT_DIS_TXDMA_PRE_8197F BIT(7)\n#define BIT_DIS_RXDMA_PRE_8197F BIT(6)\n\n#define BIT_SHIFT_HPS_CLKR_HCI_8197F 4\n#define BIT_MASK_HPS_CLKR_HCI_8197F 0x3\n#define BIT_HPS_CLKR_HCI_8197F(x)                                              \\\n\t(((x) & BIT_MASK_HPS_CLKR_HCI_8197F) << BIT_SHIFT_HPS_CLKR_HCI_8197F)\n#define BITS_HPS_CLKR_HCI_8197F                                                \\\n\t(BIT_MASK_HPS_CLKR_HCI_8197F << BIT_SHIFT_HPS_CLKR_HCI_8197F)\n#define BIT_CLEAR_HPS_CLKR_HCI_8197F(x) ((x) & (~BITS_HPS_CLKR_HCI_8197F))\n#define BIT_GET_HPS_CLKR_HCI_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_HPS_CLKR_HCI_8197F) & BIT_MASK_HPS_CLKR_HCI_8197F)\n#define BIT_SET_HPS_CLKR_HCI_8197F(x, v)                                       \\\n\t(BIT_CLEAR_HPS_CLKR_HCI_8197F(x) | BIT_HPS_CLKR_HCI_8197F(v))\n\n#define BIT_HCI_INT_8197F BIT(3)\n#define BIT_TXFLAG_EXIT_L1_EN_8197F BIT(2)\n#define BIT_EN_RXDMA_ALIGN_V1_8197F BIT(1)\n#define BIT_EN_TXDMA_ALIGN_V1_8197F BIT(0)\n\n/* 2 REG_HCI_HRPWM2_V1_8197F */\n\n#define BIT_SHIFT_HCI_HRPWM2_8197F 0\n#define BIT_MASK_HCI_HRPWM2_8197F 0xffff\n#define BIT_HCI_HRPWM2_8197F(x)                                                \\\n\t(((x) & BIT_MASK_HCI_HRPWM2_8197F) << BIT_SHIFT_HCI_HRPWM2_8197F)\n#define BITS_HCI_HRPWM2_8197F                                                  \\\n\t(BIT_MASK_HCI_HRPWM2_8197F << BIT_SHIFT_HCI_HRPWM2_8197F)\n#define BIT_CLEAR_HCI_HRPWM2_8197F(x) ((x) & (~BITS_HCI_HRPWM2_8197F))\n#define BIT_GET_HCI_HRPWM2_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_HCI_HRPWM2_8197F) & BIT_MASK_HCI_HRPWM2_8197F)\n#define BIT_SET_HCI_HRPWM2_8197F(x, v)                                         \\\n\t(BIT_CLEAR_HCI_HRPWM2_8197F(x) | BIT_HCI_HRPWM2_8197F(v))\n\n/* 2 REG_HCI_HCPWM2_V1_8197F */\n\n#define BIT_SHIFT_HCI_HCPWM2_8197F 0\n#define BIT_MASK_HCI_HCPWM2_8197F 0xffff\n#define BIT_HCI_HCPWM2_8197F(x)                                                \\\n\t(((x) & BIT_MASK_HCI_HCPWM2_8197F) << BIT_SHIFT_HCI_HCPWM2_8197F)\n#define BITS_HCI_HCPWM2_8197F                                                  \\\n\t(BIT_MASK_HCI_HCPWM2_8197F << BIT_SHIFT_HCI_HCPWM2_8197F)\n#define BIT_CLEAR_HCI_HCPWM2_8197F(x) ((x) & (~BITS_HCI_HCPWM2_8197F))\n#define BIT_GET_HCI_HCPWM2_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_HCI_HCPWM2_8197F) & BIT_MASK_HCI_HCPWM2_8197F)\n#define BIT_SET_HCI_HCPWM2_8197F(x, v)                                         \\\n\t(BIT_CLEAR_HCI_HCPWM2_8197F(x) | BIT_HCI_HCPWM2_8197F(v))\n\n/* 2 REG_HCI_H2C_MSG_V1_8197F */\n\n#define BIT_SHIFT_DRV2FW_INFO_8197F 0\n#define BIT_MASK_DRV2FW_INFO_8197F 0xffffffffL\n#define BIT_DRV2FW_INFO_8197F(x)                                               \\\n\t(((x) & BIT_MASK_DRV2FW_INFO_8197F) << BIT_SHIFT_DRV2FW_INFO_8197F)\n#define BITS_DRV2FW_INFO_8197F                                                 \\\n\t(BIT_MASK_DRV2FW_INFO_8197F << BIT_SHIFT_DRV2FW_INFO_8197F)\n#define BIT_CLEAR_DRV2FW_INFO_8197F(x) ((x) & (~BITS_DRV2FW_INFO_8197F))\n#define BIT_GET_DRV2FW_INFO_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_DRV2FW_INFO_8197F) & BIT_MASK_DRV2FW_INFO_8197F)\n#define BIT_SET_DRV2FW_INFO_8197F(x, v)                                        \\\n\t(BIT_CLEAR_DRV2FW_INFO_8197F(x) | BIT_DRV2FW_INFO_8197F(v))\n\n/* 2 REG_HCI_C2H_MSG_V1_8197F */\n\n#define BIT_SHIFT_HCI_C2H_MSG_8197F 0\n#define BIT_MASK_HCI_C2H_MSG_8197F 0xffffffffL\n#define BIT_HCI_C2H_MSG_8197F(x)                                               \\\n\t(((x) & BIT_MASK_HCI_C2H_MSG_8197F) << BIT_SHIFT_HCI_C2H_MSG_8197F)\n#define BITS_HCI_C2H_MSG_8197F                                                 \\\n\t(BIT_MASK_HCI_C2H_MSG_8197F << BIT_SHIFT_HCI_C2H_MSG_8197F)\n#define BIT_CLEAR_HCI_C2H_MSG_8197F(x) ((x) & (~BITS_HCI_C2H_MSG_8197F))\n#define BIT_GET_HCI_C2H_MSG_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_HCI_C2H_MSG_8197F) & BIT_MASK_HCI_C2H_MSG_8197F)\n#define BIT_SET_HCI_C2H_MSG_8197F(x, v)                                        \\\n\t(BIT_CLEAR_HCI_C2H_MSG_8197F(x) | BIT_HCI_C2H_MSG_8197F(v))\n\n/* 2 REG_DBI_WDATA_V1_8197F */\n\n#define BIT_SHIFT_DBI_WDATA_8197F 0\n#define BIT_MASK_DBI_WDATA_8197F 0xffffffffL\n#define BIT_DBI_WDATA_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_DBI_WDATA_8197F) << BIT_SHIFT_DBI_WDATA_8197F)\n#define BITS_DBI_WDATA_8197F                                                   \\\n\t(BIT_MASK_DBI_WDATA_8197F << BIT_SHIFT_DBI_WDATA_8197F)\n#define BIT_CLEAR_DBI_WDATA_8197F(x) ((x) & (~BITS_DBI_WDATA_8197F))\n#define BIT_GET_DBI_WDATA_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBI_WDATA_8197F) & BIT_MASK_DBI_WDATA_8197F)\n#define BIT_SET_DBI_WDATA_8197F(x, v)                                          \\\n\t(BIT_CLEAR_DBI_WDATA_8197F(x) | BIT_DBI_WDATA_8197F(v))\n\n/* 2 REG_DBI_RDATA_V1_8197F */\n\n#define BIT_SHIFT_DBI_RDATA_8197F 0\n#define BIT_MASK_DBI_RDATA_8197F 0xffffffffL\n#define BIT_DBI_RDATA_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_DBI_RDATA_8197F) << BIT_SHIFT_DBI_RDATA_8197F)\n#define BITS_DBI_RDATA_8197F                                                   \\\n\t(BIT_MASK_DBI_RDATA_8197F << BIT_SHIFT_DBI_RDATA_8197F)\n#define BIT_CLEAR_DBI_RDATA_8197F(x) ((x) & (~BITS_DBI_RDATA_8197F))\n#define BIT_GET_DBI_RDATA_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBI_RDATA_8197F) & BIT_MASK_DBI_RDATA_8197F)\n#define BIT_SET_DBI_RDATA_8197F(x, v)                                          \\\n\t(BIT_CLEAR_DBI_RDATA_8197F(x) | BIT_DBI_RDATA_8197F(v))\n\n/* 2 REG_STUCK_FLAG_V1_8197F */\n#define BIT_EN_STUCK_DBG_8197F BIT(26)\n#define BIT_RX_STUCK_8197F BIT(25)\n#define BIT_TX_STUCK_8197F BIT(24)\n#define BIT_DBI_RFLAG_8197F BIT(17)\n#define BIT_DBI_WFLAG_8197F BIT(16)\n\n#define BIT_SHIFT_DBI_WREN_8197F 12\n#define BIT_MASK_DBI_WREN_8197F 0xf\n#define BIT_DBI_WREN_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_DBI_WREN_8197F) << BIT_SHIFT_DBI_WREN_8197F)\n#define BITS_DBI_WREN_8197F                                                    \\\n\t(BIT_MASK_DBI_WREN_8197F << BIT_SHIFT_DBI_WREN_8197F)\n#define BIT_CLEAR_DBI_WREN_8197F(x) ((x) & (~BITS_DBI_WREN_8197F))\n#define BIT_GET_DBI_WREN_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_DBI_WREN_8197F) & BIT_MASK_DBI_WREN_8197F)\n#define BIT_SET_DBI_WREN_8197F(x, v)                                           \\\n\t(BIT_CLEAR_DBI_WREN_8197F(x) | BIT_DBI_WREN_8197F(v))\n\n#define BIT_SHIFT_DBI_ADDR_8197F 0\n#define BIT_MASK_DBI_ADDR_8197F 0xfff\n#define BIT_DBI_ADDR_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_DBI_ADDR_8197F) << BIT_SHIFT_DBI_ADDR_8197F)\n#define BITS_DBI_ADDR_8197F                                                    \\\n\t(BIT_MASK_DBI_ADDR_8197F << BIT_SHIFT_DBI_ADDR_8197F)\n#define BIT_CLEAR_DBI_ADDR_8197F(x) ((x) & (~BITS_DBI_ADDR_8197F))\n#define BIT_GET_DBI_ADDR_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_DBI_ADDR_8197F) & BIT_MASK_DBI_ADDR_8197F)\n#define BIT_SET_DBI_ADDR_8197F(x, v)                                           \\\n\t(BIT_CLEAR_DBI_ADDR_8197F(x) | BIT_DBI_ADDR_8197F(v))\n\n/* 2 REG_MDIO_V1_8197F */\n\n#define BIT_SHIFT_MDIO_RDATA_8197F 16\n#define BIT_MASK_MDIO_RDATA_8197F 0xffff\n#define BIT_MDIO_RDATA_8197F(x)                                                \\\n\t(((x) & BIT_MASK_MDIO_RDATA_8197F) << BIT_SHIFT_MDIO_RDATA_8197F)\n#define BITS_MDIO_RDATA_8197F                                                  \\\n\t(BIT_MASK_MDIO_RDATA_8197F << BIT_SHIFT_MDIO_RDATA_8197F)\n#define BIT_CLEAR_MDIO_RDATA_8197F(x) ((x) & (~BITS_MDIO_RDATA_8197F))\n#define BIT_GET_MDIO_RDATA_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_MDIO_RDATA_8197F) & BIT_MASK_MDIO_RDATA_8197F)\n#define BIT_SET_MDIO_RDATA_8197F(x, v)                                         \\\n\t(BIT_CLEAR_MDIO_RDATA_8197F(x) | BIT_MDIO_RDATA_8197F(v))\n\n#define BIT_SHIFT_MDIO_WDATA_8197F 0\n#define BIT_MASK_MDIO_WDATA_8197F 0xffff\n#define BIT_MDIO_WDATA_8197F(x)                                                \\\n\t(((x) & BIT_MASK_MDIO_WDATA_8197F) << BIT_SHIFT_MDIO_WDATA_8197F)\n#define BITS_MDIO_WDATA_8197F                                                  \\\n\t(BIT_MASK_MDIO_WDATA_8197F << BIT_SHIFT_MDIO_WDATA_8197F)\n#define BIT_CLEAR_MDIO_WDATA_8197F(x) ((x) & (~BITS_MDIO_WDATA_8197F))\n#define BIT_GET_MDIO_WDATA_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_MDIO_WDATA_8197F) & BIT_MASK_MDIO_WDATA_8197F)\n#define BIT_SET_MDIO_WDATA_8197F(x, v)                                         \\\n\t(BIT_CLEAR_MDIO_WDATA_8197F(x) | BIT_MDIO_WDATA_8197F(v))\n\n/* 2 REG_WDT_CFG_8197F */\n\n#define BIT_SHIFT_MDIO_PHY_ADDR_8197F 24\n#define BIT_MASK_MDIO_PHY_ADDR_8197F 0x1f\n#define BIT_MDIO_PHY_ADDR_8197F(x)                                             \\\n\t(((x) & BIT_MASK_MDIO_PHY_ADDR_8197F) << BIT_SHIFT_MDIO_PHY_ADDR_8197F)\n#define BITS_MDIO_PHY_ADDR_8197F                                               \\\n\t(BIT_MASK_MDIO_PHY_ADDR_8197F << BIT_SHIFT_MDIO_PHY_ADDR_8197F)\n#define BIT_CLEAR_MDIO_PHY_ADDR_8197F(x) ((x) & (~BITS_MDIO_PHY_ADDR_8197F))\n#define BIT_GET_MDIO_PHY_ADDR_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8197F) & BIT_MASK_MDIO_PHY_ADDR_8197F)\n#define BIT_SET_MDIO_PHY_ADDR_8197F(x, v)                                      \\\n\t(BIT_CLEAR_MDIO_PHY_ADDR_8197F(x) | BIT_MDIO_PHY_ADDR_8197F(v))\n\n#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F 10\n#define BIT_MASK_WATCH_DOG_RECORD_V1_8197F 0x3fff\n#define BIT_WATCH_DOG_RECORD_V1_8197F(x)                                       \\\n\t(((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8197F)                            \\\n\t << BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F)\n#define BITS_WATCH_DOG_RECORD_V1_8197F                                         \\\n\t(BIT_MASK_WATCH_DOG_RECORD_V1_8197F                                    \\\n\t << BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F)\n#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8197F(x)                                 \\\n\t((x) & (~BITS_WATCH_DOG_RECORD_V1_8197F))\n#define BIT_GET_WATCH_DOG_RECORD_V1_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) &                        \\\n\t BIT_MASK_WATCH_DOG_RECORD_V1_8197F)\n#define BIT_SET_WATCH_DOG_RECORD_V1_8197F(x, v)                                \\\n\t(BIT_CLEAR_WATCH_DOG_RECORD_V1_8197F(x) |                              \\\n\t BIT_WATCH_DOG_RECORD_V1_8197F(v))\n\n#define BIT_R_IO_TIMEOUT_FLAG_V1_8197F BIT(9)\n#define BIT_EN_WATCH_DOG_V1_8197F BIT(8)\n#define BIT_ECRC_EN_V1_8197F BIT(7)\n#define BIT_MDIO_RFLAG_V1_8197F BIT(6)\n#define BIT_MDIO_WFLAG_V1_8197F BIT(5)\n\n#define BIT_SHIFT_MDIO_REG_ADDR_8197F 0\n#define BIT_MASK_MDIO_REG_ADDR_8197F 0x1f\n#define BIT_MDIO_REG_ADDR_8197F(x)                                             \\\n\t(((x) & BIT_MASK_MDIO_REG_ADDR_8197F) << BIT_SHIFT_MDIO_REG_ADDR_8197F)\n#define BITS_MDIO_REG_ADDR_8197F                                               \\\n\t(BIT_MASK_MDIO_REG_ADDR_8197F << BIT_SHIFT_MDIO_REG_ADDR_8197F)\n#define BIT_CLEAR_MDIO_REG_ADDR_8197F(x) ((x) & (~BITS_MDIO_REG_ADDR_8197F))\n#define BIT_GET_MDIO_REG_ADDR_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_MDIO_REG_ADDR_8197F) & BIT_MASK_MDIO_REG_ADDR_8197F)\n#define BIT_SET_MDIO_REG_ADDR_8197F(x, v)                                      \\\n\t(BIT_CLEAR_MDIO_REG_ADDR_8197F(x) | BIT_MDIO_REG_ADDR_8197F(v))\n\n/* 2 REG_HCI_MIX_CFG_8197F */\n#define BIT_RXRST_BACKDOOR_8197F BIT(31)\n#define BIT_TXRST_BACKDOOR_8197F BIT(30)\n#define BIT_RXIDX_RSTB_8197F BIT(29)\n#define BIT_TXIDX_RSTB_8197F BIT(28)\n#define BIT_DROP_NEXT_RXPKT_8197F BIT(27)\n#define BIT_SHORT_CORE_RST_SEL_8197F BIT(26)\n#define BIT_EXCEPT_RESUME_EN_8197F BIT(25)\n#define BIT_EXCEPT_RESUME_FLAG_8197F BIT(24)\n#define BIT_ALIGN_MTU_8197F BIT(23)\n#define BIT_HOST_GEN2_SUPPORT_8197F BIT(20)\n\n#define BIT_SHIFT_TXDMA_ERR_FLAG_8197F 16\n#define BIT_MASK_TXDMA_ERR_FLAG_8197F 0xf\n#define BIT_TXDMA_ERR_FLAG_8197F(x)                                            \\\n\t(((x) & BIT_MASK_TXDMA_ERR_FLAG_8197F)                                 \\\n\t << BIT_SHIFT_TXDMA_ERR_FLAG_8197F)\n#define BITS_TXDMA_ERR_FLAG_8197F                                              \\\n\t(BIT_MASK_TXDMA_ERR_FLAG_8197F << BIT_SHIFT_TXDMA_ERR_FLAG_8197F)\n#define BIT_CLEAR_TXDMA_ERR_FLAG_8197F(x) ((x) & (~BITS_TXDMA_ERR_FLAG_8197F))\n#define BIT_GET_TXDMA_ERR_FLAG_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8197F) &                             \\\n\t BIT_MASK_TXDMA_ERR_FLAG_8197F)\n#define BIT_SET_TXDMA_ERR_FLAG_8197F(x, v)                                     \\\n\t(BIT_CLEAR_TXDMA_ERR_FLAG_8197F(x) | BIT_TXDMA_ERR_FLAG_8197F(v))\n\n#define BIT_SHIFT_EARLY_MODE_SEL_8197F 12\n#define BIT_MASK_EARLY_MODE_SEL_8197F 0xf\n#define BIT_EARLY_MODE_SEL_8197F(x)                                            \\\n\t(((x) & BIT_MASK_EARLY_MODE_SEL_8197F)                                 \\\n\t << BIT_SHIFT_EARLY_MODE_SEL_8197F)\n#define BITS_EARLY_MODE_SEL_8197F                                              \\\n\t(BIT_MASK_EARLY_MODE_SEL_8197F << BIT_SHIFT_EARLY_MODE_SEL_8197F)\n#define BIT_CLEAR_EARLY_MODE_SEL_8197F(x) ((x) & (~BITS_EARLY_MODE_SEL_8197F))\n#define BIT_GET_EARLY_MODE_SEL_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_EARLY_MODE_SEL_8197F) &                             \\\n\t BIT_MASK_EARLY_MODE_SEL_8197F)\n#define BIT_SET_EARLY_MODE_SEL_8197F(x, v)                                     \\\n\t(BIT_CLEAR_EARLY_MODE_SEL_8197F(x) | BIT_EARLY_MODE_SEL_8197F(v))\n\n#define BIT_EPHY_RX50_EN_8197F BIT(11)\n\n#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F 8\n#define BIT_MASK_MSI_TIMEOUT_ID_V1_8197F 0x7\n#define BIT_MSI_TIMEOUT_ID_V1_8197F(x)                                         \\\n\t(((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8197F)                              \\\n\t << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F)\n#define BITS_MSI_TIMEOUT_ID_V1_8197F                                           \\\n\t(BIT_MASK_MSI_TIMEOUT_ID_V1_8197F << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F)\n#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8197F(x)                                   \\\n\t((x) & (~BITS_MSI_TIMEOUT_ID_V1_8197F))\n#define BIT_GET_MSI_TIMEOUT_ID_V1_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) &                          \\\n\t BIT_MASK_MSI_TIMEOUT_ID_V1_8197F)\n#define BIT_SET_MSI_TIMEOUT_ID_V1_8197F(x, v)                                  \\\n\t(BIT_CLEAR_MSI_TIMEOUT_ID_V1_8197F(x) | BIT_MSI_TIMEOUT_ID_V1_8197F(v))\n\n#define BIT_RADDR_RD_8197F BIT(7)\n#define BIT_EN_MUL_TAG_8197F BIT(6)\n#define BIT_EN_EARLY_MODE_8197F BIT(5)\n#define BIT_L0S_LINK_OFF_8197F BIT(4)\n#define BIT_ACT_LINK_OFF_8197F BIT(3)\n\n/* 2 REG_STC_INT_CS_8197F(HCI STATE CHANGE INTERRUPT CONTROL AND STATUS) */\n#define BIT_STC_INT_EN_8197F BIT(31)\n\n#define BIT_SHIFT_STC_INT_FLAG_8197F 16\n#define BIT_MASK_STC_INT_FLAG_8197F 0xff\n#define BIT_STC_INT_FLAG_8197F(x)                                              \\\n\t(((x) & BIT_MASK_STC_INT_FLAG_8197F) << BIT_SHIFT_STC_INT_FLAG_8197F)\n#define BITS_STC_INT_FLAG_8197F                                                \\\n\t(BIT_MASK_STC_INT_FLAG_8197F << BIT_SHIFT_STC_INT_FLAG_8197F)\n#define BIT_CLEAR_STC_INT_FLAG_8197F(x) ((x) & (~BITS_STC_INT_FLAG_8197F))\n#define BIT_GET_STC_INT_FLAG_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_STC_INT_FLAG_8197F) & BIT_MASK_STC_INT_FLAG_8197F)\n#define BIT_SET_STC_INT_FLAG_8197F(x, v)                                       \\\n\t(BIT_CLEAR_STC_INT_FLAG_8197F(x) | BIT_STC_INT_FLAG_8197F(v))\n\n#define BIT_SHIFT_STC_INT_IDX_8197F 8\n#define BIT_MASK_STC_INT_IDX_8197F 0x7\n#define BIT_STC_INT_IDX_8197F(x)                                               \\\n\t(((x) & BIT_MASK_STC_INT_IDX_8197F) << BIT_SHIFT_STC_INT_IDX_8197F)\n#define BITS_STC_INT_IDX_8197F                                                 \\\n\t(BIT_MASK_STC_INT_IDX_8197F << BIT_SHIFT_STC_INT_IDX_8197F)\n#define BIT_CLEAR_STC_INT_IDX_8197F(x) ((x) & (~BITS_STC_INT_IDX_8197F))\n#define BIT_GET_STC_INT_IDX_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_STC_INT_IDX_8197F) & BIT_MASK_STC_INT_IDX_8197F)\n#define BIT_SET_STC_INT_IDX_8197F(x, v)                                        \\\n\t(BIT_CLEAR_STC_INT_IDX_8197F(x) | BIT_STC_INT_IDX_8197F(v))\n\n#define BIT_SHIFT_STC_INT_REALTIME_CS_8197F 0\n#define BIT_MASK_STC_INT_REALTIME_CS_8197F 0x3f\n#define BIT_STC_INT_REALTIME_CS_8197F(x)                                       \\\n\t(((x) & BIT_MASK_STC_INT_REALTIME_CS_8197F)                            \\\n\t << BIT_SHIFT_STC_INT_REALTIME_CS_8197F)\n#define BITS_STC_INT_REALTIME_CS_8197F                                         \\\n\t(BIT_MASK_STC_INT_REALTIME_CS_8197F                                    \\\n\t << BIT_SHIFT_STC_INT_REALTIME_CS_8197F)\n#define BIT_CLEAR_STC_INT_REALTIME_CS_8197F(x)                                 \\\n\t((x) & (~BITS_STC_INT_REALTIME_CS_8197F))\n#define BIT_GET_STC_INT_REALTIME_CS_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8197F) &                        \\\n\t BIT_MASK_STC_INT_REALTIME_CS_8197F)\n#define BIT_SET_STC_INT_REALTIME_CS_8197F(x, v)                                \\\n\t(BIT_CLEAR_STC_INT_REALTIME_CS_8197F(x) |                              \\\n\t BIT_STC_INT_REALTIME_CS_8197F(v))\n\n/* 2 REG_ST_INT_CFG_8197F(HCI STATE CHANGE INTERRUPT CONFIGURATION) */\n#define BIT_STC_INT_GRP_EN_8197F BIT(31)\n\n#define BIT_SHIFT_STC_INT_EXPECT_LS_8197F 8\n#define BIT_MASK_STC_INT_EXPECT_LS_8197F 0x3f\n#define BIT_STC_INT_EXPECT_LS_8197F(x)                                         \\\n\t(((x) & BIT_MASK_STC_INT_EXPECT_LS_8197F)                              \\\n\t << BIT_SHIFT_STC_INT_EXPECT_LS_8197F)\n#define BITS_STC_INT_EXPECT_LS_8197F                                           \\\n\t(BIT_MASK_STC_INT_EXPECT_LS_8197F << BIT_SHIFT_STC_INT_EXPECT_LS_8197F)\n#define BIT_CLEAR_STC_INT_EXPECT_LS_8197F(x)                                   \\\n\t((x) & (~BITS_STC_INT_EXPECT_LS_8197F))\n#define BIT_GET_STC_INT_EXPECT_LS_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8197F) &                          \\\n\t BIT_MASK_STC_INT_EXPECT_LS_8197F)\n#define BIT_SET_STC_INT_EXPECT_LS_8197F(x, v)                                  \\\n\t(BIT_CLEAR_STC_INT_EXPECT_LS_8197F(x) | BIT_STC_INT_EXPECT_LS_8197F(v))\n\n#define BIT_SHIFT_STC_INT_EXPECT_CS_8197F 0\n#define BIT_MASK_STC_INT_EXPECT_CS_8197F 0x3f\n#define BIT_STC_INT_EXPECT_CS_8197F(x)                                         \\\n\t(((x) & BIT_MASK_STC_INT_EXPECT_CS_8197F)                              \\\n\t << BIT_SHIFT_STC_INT_EXPECT_CS_8197F)\n#define BITS_STC_INT_EXPECT_CS_8197F                                           \\\n\t(BIT_MASK_STC_INT_EXPECT_CS_8197F << BIT_SHIFT_STC_INT_EXPECT_CS_8197F)\n#define BIT_CLEAR_STC_INT_EXPECT_CS_8197F(x)                                   \\\n\t((x) & (~BITS_STC_INT_EXPECT_CS_8197F))\n#define BIT_GET_STC_INT_EXPECT_CS_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8197F) &                          \\\n\t BIT_MASK_STC_INT_EXPECT_CS_8197F)\n#define BIT_SET_STC_INT_EXPECT_CS_8197F(x, v)                                  \\\n\t(BIT_CLEAR_STC_INT_EXPECT_CS_8197F(x) | BIT_STC_INT_EXPECT_CS_8197F(v))\n\n/* 2 REG_CMU_DLY_CTRL_8197F(HCI PHY CLOCK MGT UNIT DELAY CONTROL ) */\n#define BIT_CMU_DLY_EN_8197F BIT(31)\n#define BIT_CMU_DLY_MODE_8197F BIT(30)\n\n#define BIT_SHIFT_CMU_DLY_PRE_DIV_8197F 0\n#define BIT_MASK_CMU_DLY_PRE_DIV_8197F 0xff\n#define BIT_CMU_DLY_PRE_DIV_8197F(x)                                           \\\n\t(((x) & BIT_MASK_CMU_DLY_PRE_DIV_8197F)                                \\\n\t << BIT_SHIFT_CMU_DLY_PRE_DIV_8197F)\n#define BITS_CMU_DLY_PRE_DIV_8197F                                             \\\n\t(BIT_MASK_CMU_DLY_PRE_DIV_8197F << BIT_SHIFT_CMU_DLY_PRE_DIV_8197F)\n#define BIT_CLEAR_CMU_DLY_PRE_DIV_8197F(x) ((x) & (~BITS_CMU_DLY_PRE_DIV_8197F))\n#define BIT_GET_CMU_DLY_PRE_DIV_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) &                            \\\n\t BIT_MASK_CMU_DLY_PRE_DIV_8197F)\n#define BIT_SET_CMU_DLY_PRE_DIV_8197F(x, v)                                    \\\n\t(BIT_CLEAR_CMU_DLY_PRE_DIV_8197F(x) | BIT_CMU_DLY_PRE_DIV_8197F(v))\n\n/* 2 REG_CMU_DLY_CFG_8197F(HCI PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */\n\n#define BIT_SHIFT_CMU_DLY_LTR_A2I_8197F 24\n#define BIT_MASK_CMU_DLY_LTR_A2I_8197F 0xff\n#define BIT_CMU_DLY_LTR_A2I_8197F(x)                                           \\\n\t(((x) & BIT_MASK_CMU_DLY_LTR_A2I_8197F)                                \\\n\t << BIT_SHIFT_CMU_DLY_LTR_A2I_8197F)\n#define BITS_CMU_DLY_LTR_A2I_8197F                                             \\\n\t(BIT_MASK_CMU_DLY_LTR_A2I_8197F << BIT_SHIFT_CMU_DLY_LTR_A2I_8197F)\n#define BIT_CLEAR_CMU_DLY_LTR_A2I_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_A2I_8197F))\n#define BIT_GET_CMU_DLY_LTR_A2I_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) &                            \\\n\t BIT_MASK_CMU_DLY_LTR_A2I_8197F)\n#define BIT_SET_CMU_DLY_LTR_A2I_8197F(x, v)                                    \\\n\t(BIT_CLEAR_CMU_DLY_LTR_A2I_8197F(x) | BIT_CMU_DLY_LTR_A2I_8197F(v))\n\n#define BIT_SHIFT_CMU_DLY_LTR_I2A_8197F 16\n#define BIT_MASK_CMU_DLY_LTR_I2A_8197F 0xff\n#define BIT_CMU_DLY_LTR_I2A_8197F(x)                                           \\\n\t(((x) & BIT_MASK_CMU_DLY_LTR_I2A_8197F)                                \\\n\t << BIT_SHIFT_CMU_DLY_LTR_I2A_8197F)\n#define BITS_CMU_DLY_LTR_I2A_8197F                                             \\\n\t(BIT_MASK_CMU_DLY_LTR_I2A_8197F << BIT_SHIFT_CMU_DLY_LTR_I2A_8197F)\n#define BIT_CLEAR_CMU_DLY_LTR_I2A_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_I2A_8197F))\n#define BIT_GET_CMU_DLY_LTR_I2A_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) &                            \\\n\t BIT_MASK_CMU_DLY_LTR_I2A_8197F)\n#define BIT_SET_CMU_DLY_LTR_I2A_8197F(x, v)                                    \\\n\t(BIT_CLEAR_CMU_DLY_LTR_I2A_8197F(x) | BIT_CMU_DLY_LTR_I2A_8197F(v))\n\n#define BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F 8\n#define BIT_MASK_CMU_DLY_LTR_IDLE_8197F 0xff\n#define BIT_CMU_DLY_LTR_IDLE_8197F(x)                                          \\\n\t(((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8197F)                               \\\n\t << BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F)\n#define BITS_CMU_DLY_LTR_IDLE_8197F                                            \\\n\t(BIT_MASK_CMU_DLY_LTR_IDLE_8197F << BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F)\n#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8197F(x)                                    \\\n\t((x) & (~BITS_CMU_DLY_LTR_IDLE_8197F))\n#define BIT_GET_CMU_DLY_LTR_IDLE_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) &                           \\\n\t BIT_MASK_CMU_DLY_LTR_IDLE_8197F)\n#define BIT_SET_CMU_DLY_LTR_IDLE_8197F(x, v)                                   \\\n\t(BIT_CLEAR_CMU_DLY_LTR_IDLE_8197F(x) | BIT_CMU_DLY_LTR_IDLE_8197F(v))\n\n#define BIT_SHIFT_CMU_DLY_LTR_ACT_8197F 0\n#define BIT_MASK_CMU_DLY_LTR_ACT_8197F 0xff\n#define BIT_CMU_DLY_LTR_ACT_8197F(x)                                           \\\n\t(((x) & BIT_MASK_CMU_DLY_LTR_ACT_8197F)                                \\\n\t << BIT_SHIFT_CMU_DLY_LTR_ACT_8197F)\n#define BITS_CMU_DLY_LTR_ACT_8197F                                             \\\n\t(BIT_MASK_CMU_DLY_LTR_ACT_8197F << BIT_SHIFT_CMU_DLY_LTR_ACT_8197F)\n#define BIT_CLEAR_CMU_DLY_LTR_ACT_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_ACT_8197F))\n#define BIT_GET_CMU_DLY_LTR_ACT_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) &                            \\\n\t BIT_MASK_CMU_DLY_LTR_ACT_8197F)\n#define BIT_SET_CMU_DLY_LTR_ACT_8197F(x, v)                                    \\\n\t(BIT_CLEAR_CMU_DLY_LTR_ACT_8197F(x) | BIT_CMU_DLY_LTR_ACT_8197F(v))\n\n/* 2 REG_H2CQ_TXBD_DESA_8197F */\n\n#define BIT_SHIFT_H2CQ_TXBD_DESA_8197F 0\n#define BIT_MASK_H2CQ_TXBD_DESA_8197F 0xffffffffffffffffL\n#define BIT_H2CQ_TXBD_DESA_8197F(x)                                            \\\n\t(((x) & BIT_MASK_H2CQ_TXBD_DESA_8197F)                                 \\\n\t << BIT_SHIFT_H2CQ_TXBD_DESA_8197F)\n#define BITS_H2CQ_TXBD_DESA_8197F                                              \\\n\t(BIT_MASK_H2CQ_TXBD_DESA_8197F << BIT_SHIFT_H2CQ_TXBD_DESA_8197F)\n#define BIT_CLEAR_H2CQ_TXBD_DESA_8197F(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8197F))\n#define BIT_GET_H2CQ_TXBD_DESA_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8197F) &                             \\\n\t BIT_MASK_H2CQ_TXBD_DESA_8197F)\n#define BIT_SET_H2CQ_TXBD_DESA_8197F(x, v)                                     \\\n\t(BIT_CLEAR_H2CQ_TXBD_DESA_8197F(x) | BIT_H2CQ_TXBD_DESA_8197F(v))\n\n/* 2 REG_H2CQ_TXBD_NUM_8197F */\n#define BIT_HCI_H2CQ_FLAG_8197F BIT(14)\n\n#define BIT_SHIFT_H2CQ_DESC_MODE_8197F 12\n#define BIT_MASK_H2CQ_DESC_MODE_8197F 0x3\n#define BIT_H2CQ_DESC_MODE_8197F(x)                                            \\\n\t(((x) & BIT_MASK_H2CQ_DESC_MODE_8197F)                                 \\\n\t << BIT_SHIFT_H2CQ_DESC_MODE_8197F)\n#define BITS_H2CQ_DESC_MODE_8197F                                              \\\n\t(BIT_MASK_H2CQ_DESC_MODE_8197F << BIT_SHIFT_H2CQ_DESC_MODE_8197F)\n#define BIT_CLEAR_H2CQ_DESC_MODE_8197F(x) ((x) & (~BITS_H2CQ_DESC_MODE_8197F))\n#define BIT_GET_H2CQ_DESC_MODE_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8197F) &                             \\\n\t BIT_MASK_H2CQ_DESC_MODE_8197F)\n#define BIT_SET_H2CQ_DESC_MODE_8197F(x, v)                                     \\\n\t(BIT_CLEAR_H2CQ_DESC_MODE_8197F(x) | BIT_H2CQ_DESC_MODE_8197F(v))\n\n#define BIT_SHIFT_H2CQ_DESC_NUM_8197F 0\n#define BIT_MASK_H2CQ_DESC_NUM_8197F 0xfff\n#define BIT_H2CQ_DESC_NUM_8197F(x)                                             \\\n\t(((x) & BIT_MASK_H2CQ_DESC_NUM_8197F) << BIT_SHIFT_H2CQ_DESC_NUM_8197F)\n#define BITS_H2CQ_DESC_NUM_8197F                                               \\\n\t(BIT_MASK_H2CQ_DESC_NUM_8197F << BIT_SHIFT_H2CQ_DESC_NUM_8197F)\n#define BIT_CLEAR_H2CQ_DESC_NUM_8197F(x) ((x) & (~BITS_H2CQ_DESC_NUM_8197F))\n#define BIT_GET_H2CQ_DESC_NUM_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8197F) & BIT_MASK_H2CQ_DESC_NUM_8197F)\n#define BIT_SET_H2CQ_DESC_NUM_8197F(x, v)                                      \\\n\t(BIT_CLEAR_H2CQ_DESC_NUM_8197F(x) | BIT_H2CQ_DESC_NUM_8197F(v))\n\n/* 2 REG_H2CQ_TXBD_IDX_8197F */\n\n#define BIT_SHIFT_H2CQ_HW_IDX_8197F 16\n#define BIT_MASK_H2CQ_HW_IDX_8197F 0xfff\n#define BIT_H2CQ_HW_IDX_8197F(x)                                               \\\n\t(((x) & BIT_MASK_H2CQ_HW_IDX_8197F) << BIT_SHIFT_H2CQ_HW_IDX_8197F)\n#define BITS_H2CQ_HW_IDX_8197F                                                 \\\n\t(BIT_MASK_H2CQ_HW_IDX_8197F << BIT_SHIFT_H2CQ_HW_IDX_8197F)\n#define BIT_CLEAR_H2CQ_HW_IDX_8197F(x) ((x) & (~BITS_H2CQ_HW_IDX_8197F))\n#define BIT_GET_H2CQ_HW_IDX_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_H2CQ_HW_IDX_8197F) & BIT_MASK_H2CQ_HW_IDX_8197F)\n#define BIT_SET_H2CQ_HW_IDX_8197F(x, v)                                        \\\n\t(BIT_CLEAR_H2CQ_HW_IDX_8197F(x) | BIT_H2CQ_HW_IDX_8197F(v))\n\n#define BIT_SHIFT_H2CQ_HOST_IDX_8197F 0\n#define BIT_MASK_H2CQ_HOST_IDX_8197F 0xfff\n#define BIT_H2CQ_HOST_IDX_8197F(x)                                             \\\n\t(((x) & BIT_MASK_H2CQ_HOST_IDX_8197F) << BIT_SHIFT_H2CQ_HOST_IDX_8197F)\n#define BITS_H2CQ_HOST_IDX_8197F                                               \\\n\t(BIT_MASK_H2CQ_HOST_IDX_8197F << BIT_SHIFT_H2CQ_HOST_IDX_8197F)\n#define BIT_CLEAR_H2CQ_HOST_IDX_8197F(x) ((x) & (~BITS_H2CQ_HOST_IDX_8197F))\n#define BIT_GET_H2CQ_HOST_IDX_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8197F) & BIT_MASK_H2CQ_HOST_IDX_8197F)\n#define BIT_SET_H2CQ_HOST_IDX_8197F(x, v)                                      \\\n\t(BIT_CLEAR_H2CQ_HOST_IDX_8197F(x) | BIT_H2CQ_HOST_IDX_8197F(v))\n\n/* 2 REG_H2CQ_CSR_8197F[31:0] (H2CQ CONTROL AND STATUS) */\n#define BIT_H2CQ_FULL_8197F BIT(31)\n#define BIT_CLR_H2CQ_HOST_IDX_8197F BIT(16)\n#define BIT_CLR_H2CQ_HW_IDX_8197F BIT(8)\n#define BIT_STOP_H2CQ_8197F BIT(0)\n\n/* 2 REG_AXI_EXCEPT_CS_8197F[31:0]\t(AXI EXCEPTION CONTROL AND STATUS) */\n#define BIT_AXI_RXDMA_TIMEOUT_RE_8197F BIT(21)\n#define BIT_AXI_TXDMA_TIMEOUT_RE_8197F BIT(20)\n#define BIT_AXI_DECERR_W_RE_8197F BIT(19)\n#define BIT_AXI_DECERR_R_RE_8197F BIT(18)\n#define BIT_AXI_SLVERR_W_RE_8197F BIT(17)\n#define BIT_AXI_SLVERR_R_RE_8197F BIT(16)\n#define BIT_AXI_RXDMA_TIMEOUT_IE_8197F BIT(13)\n#define BIT_AXI_TXDMA_TIMEOUT_IE_8197F BIT(12)\n#define BIT_AXI_DECERR_W_IE_8197F BIT(11)\n#define BIT_AXI_DECERR_R_IE_8197F BIT(10)\n#define BIT_AXI_SLVERR_W_IE_8197F BIT(9)\n#define BIT_AXI_SLVERR_R_IE_8197F BIT(8)\n#define BIT_AXI_RXDMA_TIMEOUT_FLAG_8197F BIT(5)\n#define BIT_AXI_TXDMA_TIMEOUT_FLAG_8197F BIT(4)\n#define BIT_AXI_DECERR_W_FLAG_8197F BIT(3)\n#define BIT_AXI_DECERR_R_FLAG_8197F BIT(2)\n#define BIT_AXI_SLVERR_W_FLAG_8197F BIT(1)\n#define BIT_AXI_SLVERR_R_FLAG_8197F BIT(0)\n\n/* 2 REG_AXI_EXCEPT_TIME_8197F[31:0]\t(AXI EXCEPTION TIME CONTROL) */\n\n#define BIT_SHIFT_AXI_RECOVERY_TIME_8197F 24\n#define BIT_MASK_AXI_RECOVERY_TIME_8197F 0xff\n#define BIT_AXI_RECOVERY_TIME_8197F(x)                                         \\\n\t(((x) & BIT_MASK_AXI_RECOVERY_TIME_8197F)                              \\\n\t << BIT_SHIFT_AXI_RECOVERY_TIME_8197F)\n#define BITS_AXI_RECOVERY_TIME_8197F                                           \\\n\t(BIT_MASK_AXI_RECOVERY_TIME_8197F << BIT_SHIFT_AXI_RECOVERY_TIME_8197F)\n#define BIT_CLEAR_AXI_RECOVERY_TIME_8197F(x)                                   \\\n\t((x) & (~BITS_AXI_RECOVERY_TIME_8197F))\n#define BIT_GET_AXI_RECOVERY_TIME_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_AXI_RECOVERY_TIME_8197F) &                          \\\n\t BIT_MASK_AXI_RECOVERY_TIME_8197F)\n#define BIT_SET_AXI_RECOVERY_TIME_8197F(x, v)                                  \\\n\t(BIT_CLEAR_AXI_RECOVERY_TIME_8197F(x) | BIT_AXI_RECOVERY_TIME_8197F(v))\n\n#define BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F 12\n#define BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F 0xfff\n#define BIT_AXI_RXDMA_TIMEOUT_VAL_8197F(x)                                     \\\n\t(((x) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F)                          \\\n\t << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F)\n#define BITS_AXI_RXDMA_TIMEOUT_VAL_8197F                                       \\\n\t(BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F                                  \\\n\t << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F)\n#define BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL_8197F(x)                               \\\n\t((x) & (~BITS_AXI_RXDMA_TIMEOUT_VAL_8197F))\n#define BIT_GET_AXI_RXDMA_TIMEOUT_VAL_8197F(x)                                 \\\n\t(((x) >> BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) &                      \\\n\t BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F)\n#define BIT_SET_AXI_RXDMA_TIMEOUT_VAL_8197F(x, v)                              \\\n\t(BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL_8197F(x) |                            \\\n\t BIT_AXI_RXDMA_TIMEOUT_VAL_8197F(v))\n\n#define BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F 0\n#define BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F 0xfff\n#define BIT_AXI_TXDMA_TIMEOUT_VAL_8197F(x)                                     \\\n\t(((x) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F)                          \\\n\t << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F)\n#define BITS_AXI_TXDMA_TIMEOUT_VAL_8197F                                       \\\n\t(BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F                                  \\\n\t << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F)\n#define BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL_8197F(x)                               \\\n\t((x) & (~BITS_AXI_TXDMA_TIMEOUT_VAL_8197F))\n#define BIT_GET_AXI_TXDMA_TIMEOUT_VAL_8197F(x)                                 \\\n\t(((x) >> BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) &                      \\\n\t BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F)\n#define BIT_SET_AXI_TXDMA_TIMEOUT_VAL_8197F(x, v)                              \\\n\t(BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL_8197F(x) |                            \\\n\t BIT_AXI_TXDMA_TIMEOUT_VAL_8197F(v))\n\n/* 2 REG_Q0_INFO_8197F */\n\n#define BIT_SHIFT_QUEUEMACID_Q0_V1_8197F 25\n#define BIT_MASK_QUEUEMACID_Q0_V1_8197F 0x7f\n#define BIT_QUEUEMACID_Q0_V1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q0_V1_8197F)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q0_V1_8197F)\n#define BITS_QUEUEMACID_Q0_V1_8197F                                            \\\n\t(BIT_MASK_QUEUEMACID_Q0_V1_8197F << BIT_SHIFT_QUEUEMACID_Q0_V1_8197F)\n#define BIT_CLEAR_QUEUEMACID_Q0_V1_8197F(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q0_V1_8197F))\n#define BIT_GET_QUEUEMACID_Q0_V1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) &                           \\\n\t BIT_MASK_QUEUEMACID_Q0_V1_8197F)\n#define BIT_SET_QUEUEMACID_Q0_V1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q0_V1_8197F(x) | BIT_QUEUEMACID_Q0_V1_8197F(v))\n\n#define BIT_SHIFT_QUEUEAC_Q0_V1_8197F 23\n#define BIT_MASK_QUEUEAC_Q0_V1_8197F 0x3\n#define BIT_QUEUEAC_Q0_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q0_V1_8197F) << BIT_SHIFT_QUEUEAC_Q0_V1_8197F)\n#define BITS_QUEUEAC_Q0_V1_8197F                                               \\\n\t(BIT_MASK_QUEUEAC_Q0_V1_8197F << BIT_SHIFT_QUEUEAC_Q0_V1_8197F)\n#define BIT_CLEAR_QUEUEAC_Q0_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8197F))\n#define BIT_GET_QUEUEAC_Q0_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8197F) & BIT_MASK_QUEUEAC_Q0_V1_8197F)\n#define BIT_SET_QUEUEAC_Q0_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q0_V1_8197F(x) | BIT_QUEUEAC_Q0_V1_8197F(v))\n\n#define BIT_TIDEMPTY_Q0_V1_8197F BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q0_V2_8197F 11\n#define BIT_MASK_TAIL_PKT_Q0_V2_8197F 0x7ff\n#define BIT_TAIL_PKT_Q0_V2_8197F(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q0_V2_8197F)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q0_V2_8197F)\n#define BITS_TAIL_PKT_Q0_V2_8197F                                              \\\n\t(BIT_MASK_TAIL_PKT_Q0_V2_8197F << BIT_SHIFT_TAIL_PKT_Q0_V2_8197F)\n#define BIT_CLEAR_TAIL_PKT_Q0_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8197F))\n#define BIT_GET_TAIL_PKT_Q0_V2_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) &                             \\\n\t BIT_MASK_TAIL_PKT_Q0_V2_8197F)\n#define BIT_SET_TAIL_PKT_Q0_V2_8197F(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q0_V2_8197F(x) | BIT_TAIL_PKT_Q0_V2_8197F(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q0_V1_8197F 0\n#define BIT_MASK_HEAD_PKT_Q0_V1_8197F 0x7ff\n#define BIT_HEAD_PKT_Q0_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q0_V1_8197F)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q0_V1_8197F)\n#define BITS_HEAD_PKT_Q0_V1_8197F                                              \\\n\t(BIT_MASK_HEAD_PKT_Q0_V1_8197F << BIT_SHIFT_HEAD_PKT_Q0_V1_8197F)\n#define BIT_CLEAR_HEAD_PKT_Q0_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8197F))\n#define BIT_GET_HEAD_PKT_Q0_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) &                             \\\n\t BIT_MASK_HEAD_PKT_Q0_V1_8197F)\n#define BIT_SET_HEAD_PKT_Q0_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q0_V1_8197F(x) | BIT_HEAD_PKT_Q0_V1_8197F(v))\n\n/* 2 REG_Q1_INFO_8197F */\n\n#define BIT_SHIFT_QUEUEMACID_Q1_V1_8197F 25\n#define BIT_MASK_QUEUEMACID_Q1_V1_8197F 0x7f\n#define BIT_QUEUEMACID_Q1_V1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q1_V1_8197F)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q1_V1_8197F)\n#define BITS_QUEUEMACID_Q1_V1_8197F                                            \\\n\t(BIT_MASK_QUEUEMACID_Q1_V1_8197F << BIT_SHIFT_QUEUEMACID_Q1_V1_8197F)\n#define BIT_CLEAR_QUEUEMACID_Q1_V1_8197F(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q1_V1_8197F))\n#define BIT_GET_QUEUEMACID_Q1_V1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) &                           \\\n\t BIT_MASK_QUEUEMACID_Q1_V1_8197F)\n#define BIT_SET_QUEUEMACID_Q1_V1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q1_V1_8197F(x) | BIT_QUEUEMACID_Q1_V1_8197F(v))\n\n#define BIT_SHIFT_QUEUEAC_Q1_V1_8197F 23\n#define BIT_MASK_QUEUEAC_Q1_V1_8197F 0x3\n#define BIT_QUEUEAC_Q1_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q1_V1_8197F) << BIT_SHIFT_QUEUEAC_Q1_V1_8197F)\n#define BITS_QUEUEAC_Q1_V1_8197F                                               \\\n\t(BIT_MASK_QUEUEAC_Q1_V1_8197F << BIT_SHIFT_QUEUEAC_Q1_V1_8197F)\n#define BIT_CLEAR_QUEUEAC_Q1_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8197F))\n#define BIT_GET_QUEUEAC_Q1_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8197F) & BIT_MASK_QUEUEAC_Q1_V1_8197F)\n#define BIT_SET_QUEUEAC_Q1_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q1_V1_8197F(x) | BIT_QUEUEAC_Q1_V1_8197F(v))\n\n#define BIT_TIDEMPTY_Q1_V1_8197F BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q1_V2_8197F 11\n#define BIT_MASK_TAIL_PKT_Q1_V2_8197F 0x7ff\n#define BIT_TAIL_PKT_Q1_V2_8197F(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q1_V2_8197F)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q1_V2_8197F)\n#define BITS_TAIL_PKT_Q1_V2_8197F                                              \\\n\t(BIT_MASK_TAIL_PKT_Q1_V2_8197F << BIT_SHIFT_TAIL_PKT_Q1_V2_8197F)\n#define BIT_CLEAR_TAIL_PKT_Q1_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8197F))\n#define BIT_GET_TAIL_PKT_Q1_V2_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) &                             \\\n\t BIT_MASK_TAIL_PKT_Q1_V2_8197F)\n#define BIT_SET_TAIL_PKT_Q1_V2_8197F(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q1_V2_8197F(x) | BIT_TAIL_PKT_Q1_V2_8197F(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q1_V1_8197F 0\n#define BIT_MASK_HEAD_PKT_Q1_V1_8197F 0x7ff\n#define BIT_HEAD_PKT_Q1_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q1_V1_8197F)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q1_V1_8197F)\n#define BITS_HEAD_PKT_Q1_V1_8197F                                              \\\n\t(BIT_MASK_HEAD_PKT_Q1_V1_8197F << BIT_SHIFT_HEAD_PKT_Q1_V1_8197F)\n#define BIT_CLEAR_HEAD_PKT_Q1_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8197F))\n#define BIT_GET_HEAD_PKT_Q1_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) &                             \\\n\t BIT_MASK_HEAD_PKT_Q1_V1_8197F)\n#define BIT_SET_HEAD_PKT_Q1_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q1_V1_8197F(x) | BIT_HEAD_PKT_Q1_V1_8197F(v))\n\n/* 2 REG_Q2_INFO_8197F */\n\n#define BIT_SHIFT_QUEUEMACID_Q2_V1_8197F 25\n#define BIT_MASK_QUEUEMACID_Q2_V1_8197F 0x7f\n#define BIT_QUEUEMACID_Q2_V1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q2_V1_8197F)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q2_V1_8197F)\n#define BITS_QUEUEMACID_Q2_V1_8197F                                            \\\n\t(BIT_MASK_QUEUEMACID_Q2_V1_8197F << BIT_SHIFT_QUEUEMACID_Q2_V1_8197F)\n#define BIT_CLEAR_QUEUEMACID_Q2_V1_8197F(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q2_V1_8197F))\n#define BIT_GET_QUEUEMACID_Q2_V1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) &                           \\\n\t BIT_MASK_QUEUEMACID_Q2_V1_8197F)\n#define BIT_SET_QUEUEMACID_Q2_V1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q2_V1_8197F(x) | BIT_QUEUEMACID_Q2_V1_8197F(v))\n\n#define BIT_SHIFT_QUEUEAC_Q2_V1_8197F 23\n#define BIT_MASK_QUEUEAC_Q2_V1_8197F 0x3\n#define BIT_QUEUEAC_Q2_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q2_V1_8197F) << BIT_SHIFT_QUEUEAC_Q2_V1_8197F)\n#define BITS_QUEUEAC_Q2_V1_8197F                                               \\\n\t(BIT_MASK_QUEUEAC_Q2_V1_8197F << BIT_SHIFT_QUEUEAC_Q2_V1_8197F)\n#define BIT_CLEAR_QUEUEAC_Q2_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8197F))\n#define BIT_GET_QUEUEAC_Q2_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8197F) & BIT_MASK_QUEUEAC_Q2_V1_8197F)\n#define BIT_SET_QUEUEAC_Q2_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q2_V1_8197F(x) | BIT_QUEUEAC_Q2_V1_8197F(v))\n\n#define BIT_TIDEMPTY_Q2_V1_8197F BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q2_V2_8197F 11\n#define BIT_MASK_TAIL_PKT_Q2_V2_8197F 0x7ff\n#define BIT_TAIL_PKT_Q2_V2_8197F(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q2_V2_8197F)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q2_V2_8197F)\n#define BITS_TAIL_PKT_Q2_V2_8197F                                              \\\n\t(BIT_MASK_TAIL_PKT_Q2_V2_8197F << BIT_SHIFT_TAIL_PKT_Q2_V2_8197F)\n#define BIT_CLEAR_TAIL_PKT_Q2_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8197F))\n#define BIT_GET_TAIL_PKT_Q2_V2_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) &                             \\\n\t BIT_MASK_TAIL_PKT_Q2_V2_8197F)\n#define BIT_SET_TAIL_PKT_Q2_V2_8197F(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q2_V2_8197F(x) | BIT_TAIL_PKT_Q2_V2_8197F(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q2_V1_8197F 0\n#define BIT_MASK_HEAD_PKT_Q2_V1_8197F 0x7ff\n#define BIT_HEAD_PKT_Q2_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q2_V1_8197F)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q2_V1_8197F)\n#define BITS_HEAD_PKT_Q2_V1_8197F                                              \\\n\t(BIT_MASK_HEAD_PKT_Q2_V1_8197F << BIT_SHIFT_HEAD_PKT_Q2_V1_8197F)\n#define BIT_CLEAR_HEAD_PKT_Q2_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8197F))\n#define BIT_GET_HEAD_PKT_Q2_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) &                             \\\n\t BIT_MASK_HEAD_PKT_Q2_V1_8197F)\n#define BIT_SET_HEAD_PKT_Q2_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q2_V1_8197F(x) | BIT_HEAD_PKT_Q2_V1_8197F(v))\n\n/* 2 REG_Q3_INFO_8197F */\n\n#define BIT_SHIFT_QUEUEMACID_Q3_V1_8197F 25\n#define BIT_MASK_QUEUEMACID_Q3_V1_8197F 0x7f\n#define BIT_QUEUEMACID_Q3_V1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q3_V1_8197F)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q3_V1_8197F)\n#define BITS_QUEUEMACID_Q3_V1_8197F                                            \\\n\t(BIT_MASK_QUEUEMACID_Q3_V1_8197F << BIT_SHIFT_QUEUEMACID_Q3_V1_8197F)\n#define BIT_CLEAR_QUEUEMACID_Q3_V1_8197F(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q3_V1_8197F))\n#define BIT_GET_QUEUEMACID_Q3_V1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) &                           \\\n\t BIT_MASK_QUEUEMACID_Q3_V1_8197F)\n#define BIT_SET_QUEUEMACID_Q3_V1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q3_V1_8197F(x) | BIT_QUEUEMACID_Q3_V1_8197F(v))\n\n#define BIT_SHIFT_QUEUEAC_Q3_V1_8197F 23\n#define BIT_MASK_QUEUEAC_Q3_V1_8197F 0x3\n#define BIT_QUEUEAC_Q3_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q3_V1_8197F) << BIT_SHIFT_QUEUEAC_Q3_V1_8197F)\n#define BITS_QUEUEAC_Q3_V1_8197F                                               \\\n\t(BIT_MASK_QUEUEAC_Q3_V1_8197F << BIT_SHIFT_QUEUEAC_Q3_V1_8197F)\n#define BIT_CLEAR_QUEUEAC_Q3_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8197F))\n#define BIT_GET_QUEUEAC_Q3_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8197F) & BIT_MASK_QUEUEAC_Q3_V1_8197F)\n#define BIT_SET_QUEUEAC_Q3_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q3_V1_8197F(x) | BIT_QUEUEAC_Q3_V1_8197F(v))\n\n#define BIT_TIDEMPTY_Q3_V1_8197F BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q3_V2_8197F 11\n#define BIT_MASK_TAIL_PKT_Q3_V2_8197F 0x7ff\n#define BIT_TAIL_PKT_Q3_V2_8197F(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q3_V2_8197F)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q3_V2_8197F)\n#define BITS_TAIL_PKT_Q3_V2_8197F                                              \\\n\t(BIT_MASK_TAIL_PKT_Q3_V2_8197F << BIT_SHIFT_TAIL_PKT_Q3_V2_8197F)\n#define BIT_CLEAR_TAIL_PKT_Q3_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8197F))\n#define BIT_GET_TAIL_PKT_Q3_V2_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) &                             \\\n\t BIT_MASK_TAIL_PKT_Q3_V2_8197F)\n#define BIT_SET_TAIL_PKT_Q3_V2_8197F(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q3_V2_8197F(x) | BIT_TAIL_PKT_Q3_V2_8197F(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q3_V1_8197F 0\n#define BIT_MASK_HEAD_PKT_Q3_V1_8197F 0x7ff\n#define BIT_HEAD_PKT_Q3_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q3_V1_8197F)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q3_V1_8197F)\n#define BITS_HEAD_PKT_Q3_V1_8197F                                              \\\n\t(BIT_MASK_HEAD_PKT_Q3_V1_8197F << BIT_SHIFT_HEAD_PKT_Q3_V1_8197F)\n#define BIT_CLEAR_HEAD_PKT_Q3_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8197F))\n#define BIT_GET_HEAD_PKT_Q3_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) &                             \\\n\t BIT_MASK_HEAD_PKT_Q3_V1_8197F)\n#define BIT_SET_HEAD_PKT_Q3_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q3_V1_8197F(x) | BIT_HEAD_PKT_Q3_V1_8197F(v))\n\n/* 2 REG_MGQ_INFO_8197F */\n\n#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F 25\n#define BIT_MASK_QUEUEMACID_MGQ_V1_8197F 0x7f\n#define BIT_QUEUEMACID_MGQ_V1_8197F(x)                                         \\\n\t(((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8197F)                              \\\n\t << BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F)\n#define BITS_QUEUEMACID_MGQ_V1_8197F                                           \\\n\t(BIT_MASK_QUEUEMACID_MGQ_V1_8197F << BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F)\n#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8197F(x)                                   \\\n\t((x) & (~BITS_QUEUEMACID_MGQ_V1_8197F))\n#define BIT_GET_QUEUEMACID_MGQ_V1_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) &                          \\\n\t BIT_MASK_QUEUEMACID_MGQ_V1_8197F)\n#define BIT_SET_QUEUEMACID_MGQ_V1_8197F(x, v)                                  \\\n\t(BIT_CLEAR_QUEUEMACID_MGQ_V1_8197F(x) | BIT_QUEUEMACID_MGQ_V1_8197F(v))\n\n#define BIT_SHIFT_QUEUEAC_MGQ_V1_8197F 23\n#define BIT_MASK_QUEUEAC_MGQ_V1_8197F 0x3\n#define BIT_QUEUEAC_MGQ_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_QUEUEAC_MGQ_V1_8197F)                                 \\\n\t << BIT_SHIFT_QUEUEAC_MGQ_V1_8197F)\n#define BITS_QUEUEAC_MGQ_V1_8197F                                              \\\n\t(BIT_MASK_QUEUEAC_MGQ_V1_8197F << BIT_SHIFT_QUEUEAC_MGQ_V1_8197F)\n#define BIT_CLEAR_QUEUEAC_MGQ_V1_8197F(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8197F))\n#define BIT_GET_QUEUEAC_MGQ_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) &                             \\\n\t BIT_MASK_QUEUEAC_MGQ_V1_8197F)\n#define BIT_SET_QUEUEAC_MGQ_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_QUEUEAC_MGQ_V1_8197F(x) | BIT_QUEUEAC_MGQ_V1_8197F(v))\n\n#define BIT_TIDEMPTY_MGQ_V1_8197F BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F 11\n#define BIT_MASK_TAIL_PKT_MGQ_V2_8197F 0x7ff\n#define BIT_TAIL_PKT_MGQ_V2_8197F(x)                                           \\\n\t(((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8197F)                                \\\n\t << BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F)\n#define BITS_TAIL_PKT_MGQ_V2_8197F                                             \\\n\t(BIT_MASK_TAIL_PKT_MGQ_V2_8197F << BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F)\n#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8197F))\n#define BIT_GET_TAIL_PKT_MGQ_V2_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) &                            \\\n\t BIT_MASK_TAIL_PKT_MGQ_V2_8197F)\n#define BIT_SET_TAIL_PKT_MGQ_V2_8197F(x, v)                                    \\\n\t(BIT_CLEAR_TAIL_PKT_MGQ_V2_8197F(x) | BIT_TAIL_PKT_MGQ_V2_8197F(v))\n\n#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F 0\n#define BIT_MASK_HEAD_PKT_MGQ_V1_8197F 0x7ff\n#define BIT_HEAD_PKT_MGQ_V1_8197F(x)                                           \\\n\t(((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8197F)                                \\\n\t << BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F)\n#define BITS_HEAD_PKT_MGQ_V1_8197F                                             \\\n\t(BIT_MASK_HEAD_PKT_MGQ_V1_8197F << BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F)\n#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8197F))\n#define BIT_GET_HEAD_PKT_MGQ_V1_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) &                            \\\n\t BIT_MASK_HEAD_PKT_MGQ_V1_8197F)\n#define BIT_SET_HEAD_PKT_MGQ_V1_8197F(x, v)                                    \\\n\t(BIT_CLEAR_HEAD_PKT_MGQ_V1_8197F(x) | BIT_HEAD_PKT_MGQ_V1_8197F(v))\n\n/* 2 REG_HIQ_INFO_8197F */\n\n#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F 25\n#define BIT_MASK_QUEUEMACID_HIQ_V1_8197F 0x7f\n#define BIT_QUEUEMACID_HIQ_V1_8197F(x)                                         \\\n\t(((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8197F)                              \\\n\t << BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F)\n#define BITS_QUEUEMACID_HIQ_V1_8197F                                           \\\n\t(BIT_MASK_QUEUEMACID_HIQ_V1_8197F << BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F)\n#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8197F(x)                                   \\\n\t((x) & (~BITS_QUEUEMACID_HIQ_V1_8197F))\n#define BIT_GET_QUEUEMACID_HIQ_V1_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) &                          \\\n\t BIT_MASK_QUEUEMACID_HIQ_V1_8197F)\n#define BIT_SET_QUEUEMACID_HIQ_V1_8197F(x, v)                                  \\\n\t(BIT_CLEAR_QUEUEMACID_HIQ_V1_8197F(x) | BIT_QUEUEMACID_HIQ_V1_8197F(v))\n\n#define BIT_SHIFT_QUEUEAC_HIQ_V1_8197F 23\n#define BIT_MASK_QUEUEAC_HIQ_V1_8197F 0x3\n#define BIT_QUEUEAC_HIQ_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_QUEUEAC_HIQ_V1_8197F)                                 \\\n\t << BIT_SHIFT_QUEUEAC_HIQ_V1_8197F)\n#define BITS_QUEUEAC_HIQ_V1_8197F                                              \\\n\t(BIT_MASK_QUEUEAC_HIQ_V1_8197F << BIT_SHIFT_QUEUEAC_HIQ_V1_8197F)\n#define BIT_CLEAR_QUEUEAC_HIQ_V1_8197F(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8197F))\n#define BIT_GET_QUEUEAC_HIQ_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) &                             \\\n\t BIT_MASK_QUEUEAC_HIQ_V1_8197F)\n#define BIT_SET_QUEUEAC_HIQ_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_QUEUEAC_HIQ_V1_8197F(x) | BIT_QUEUEAC_HIQ_V1_8197F(v))\n\n#define BIT_TIDEMPTY_HIQ_V1_8197F BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F 11\n#define BIT_MASK_TAIL_PKT_HIQ_V2_8197F 0x7ff\n#define BIT_TAIL_PKT_HIQ_V2_8197F(x)                                           \\\n\t(((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8197F)                                \\\n\t << BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F)\n#define BITS_TAIL_PKT_HIQ_V2_8197F                                             \\\n\t(BIT_MASK_TAIL_PKT_HIQ_V2_8197F << BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F)\n#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8197F))\n#define BIT_GET_TAIL_PKT_HIQ_V2_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) &                            \\\n\t BIT_MASK_TAIL_PKT_HIQ_V2_8197F)\n#define BIT_SET_TAIL_PKT_HIQ_V2_8197F(x, v)                                    \\\n\t(BIT_CLEAR_TAIL_PKT_HIQ_V2_8197F(x) | BIT_TAIL_PKT_HIQ_V2_8197F(v))\n\n#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F 0\n#define BIT_MASK_HEAD_PKT_HIQ_V1_8197F 0x7ff\n#define BIT_HEAD_PKT_HIQ_V1_8197F(x)                                           \\\n\t(((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8197F)                                \\\n\t << BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F)\n#define BITS_HEAD_PKT_HIQ_V1_8197F                                             \\\n\t(BIT_MASK_HEAD_PKT_HIQ_V1_8197F << BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F)\n#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8197F))\n#define BIT_GET_HEAD_PKT_HIQ_V1_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) &                            \\\n\t BIT_MASK_HEAD_PKT_HIQ_V1_8197F)\n#define BIT_SET_HEAD_PKT_HIQ_V1_8197F(x, v)                                    \\\n\t(BIT_CLEAR_HEAD_PKT_HIQ_V1_8197F(x) | BIT_HEAD_PKT_HIQ_V1_8197F(v))\n\n/* 2 REG_BCNQ_INFO_8197F */\n\n#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F 0\n#define BIT_MASK_BCNQ_HEAD_PG_V1_8197F 0xfff\n#define BIT_BCNQ_HEAD_PG_V1_8197F(x)                                           \\\n\t(((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8197F)                                \\\n\t << BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F)\n#define BITS_BCNQ_HEAD_PG_V1_8197F                                             \\\n\t(BIT_MASK_BCNQ_HEAD_PG_V1_8197F << BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F)\n#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8197F(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8197F))\n#define BIT_GET_BCNQ_HEAD_PG_V1_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) &                            \\\n\t BIT_MASK_BCNQ_HEAD_PG_V1_8197F)\n#define BIT_SET_BCNQ_HEAD_PG_V1_8197F(x, v)                                    \\\n\t(BIT_CLEAR_BCNQ_HEAD_PG_V1_8197F(x) | BIT_BCNQ_HEAD_PG_V1_8197F(v))\n\n/* 2 REG_TXPKT_EMPTY_8197F */\n#define BIT_BCNQ_EMPTY_8197F BIT(11)\n#define BIT_HQQ_EMPTY_8197F BIT(10)\n#define BIT_MQQ_EMPTY_8197F BIT(9)\n#define BIT_MGQ_CPU_EMPTY_8197F BIT(8)\n#define BIT_AC7Q_EMPTY_8197F BIT(7)\n#define BIT_AC6Q_EMPTY_8197F BIT(6)\n#define BIT_AC5Q_EMPTY_8197F BIT(5)\n#define BIT_AC4Q_EMPTY_8197F BIT(4)\n#define BIT_AC3Q_EMPTY_8197F BIT(3)\n#define BIT_AC2Q_EMPTY_8197F BIT(2)\n#define BIT_AC1Q_EMPTY_8197F BIT(1)\n#define BIT_AC0Q_EMPTY_8197F BIT(0)\n\n/* 2 REG_CPU_MGQ_INFO_8197F */\n#define BIT_BCN1_POLL_8197F BIT(30)\n#define BIT_CPUMGT_POLL_8197F BIT(29)\n#define BIT_BCN_POLL_8197F BIT(28)\n#define BIT_CPUMGQ_FW_NUM_V1_8197F BIT(12)\n\n#define BIT_SHIFT_FW_FREE_TAIL_V1_8197F 0\n#define BIT_MASK_FW_FREE_TAIL_V1_8197F 0xfff\n#define BIT_FW_FREE_TAIL_V1_8197F(x)                                           \\\n\t(((x) & BIT_MASK_FW_FREE_TAIL_V1_8197F)                                \\\n\t << BIT_SHIFT_FW_FREE_TAIL_V1_8197F)\n#define BITS_FW_FREE_TAIL_V1_8197F                                             \\\n\t(BIT_MASK_FW_FREE_TAIL_V1_8197F << BIT_SHIFT_FW_FREE_TAIL_V1_8197F)\n#define BIT_CLEAR_FW_FREE_TAIL_V1_8197F(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8197F))\n#define BIT_GET_FW_FREE_TAIL_V1_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8197F) &                            \\\n\t BIT_MASK_FW_FREE_TAIL_V1_8197F)\n#define BIT_SET_FW_FREE_TAIL_V1_8197F(x, v)                                    \\\n\t(BIT_CLEAR_FW_FREE_TAIL_V1_8197F(x) | BIT_FW_FREE_TAIL_V1_8197F(v))\n\n/* 2 REG_FWHW_TXQ_CTRL_8197F */\n#define BIT_RTS_LIMIT_IN_OFDM_8197F BIT(23)\n#define BIT_EN_BCNQ_DL_8197F BIT(22)\n#define BIT_EN_RD_RESP_NAV_BK_8197F BIT(21)\n#define BIT_EN_WR_FREE_TAIL_8197F BIT(20)\n\n#define BIT_SHIFT_EN_QUEUE_RPT_8197F 8\n#define BIT_MASK_EN_QUEUE_RPT_8197F 0xff\n#define BIT_EN_QUEUE_RPT_8197F(x)                                              \\\n\t(((x) & BIT_MASK_EN_QUEUE_RPT_8197F) << BIT_SHIFT_EN_QUEUE_RPT_8197F)\n#define BITS_EN_QUEUE_RPT_8197F                                                \\\n\t(BIT_MASK_EN_QUEUE_RPT_8197F << BIT_SHIFT_EN_QUEUE_RPT_8197F)\n#define BIT_CLEAR_EN_QUEUE_RPT_8197F(x) ((x) & (~BITS_EN_QUEUE_RPT_8197F))\n#define BIT_GET_EN_QUEUE_RPT_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_EN_QUEUE_RPT_8197F) & BIT_MASK_EN_QUEUE_RPT_8197F)\n#define BIT_SET_EN_QUEUE_RPT_8197F(x, v)                                       \\\n\t(BIT_CLEAR_EN_QUEUE_RPT_8197F(x) | BIT_EN_QUEUE_RPT_8197F(v))\n\n#define BIT_EN_RTY_BK_8197F BIT(7)\n#define BIT_EN_USE_INI_RAT_8197F BIT(6)\n#define BIT_EN_RTS_NAV_BK_8197F BIT(5)\n#define BIT_DIS_SSN_CHECK_8197F BIT(4)\n#define BIT_MACID_MATCH_RTS_8197F BIT(3)\n#define BIT_EN_BCN_TRXRPT_V1_8197F BIT(2)\n#define BIT_R_EN_FTMRPT_8197F BIT(1)\n#define BIT_R_BMC_NAV_PROTECT_8197F BIT(0)\n\n/* 2 REG_NOT_VALID_8197F */\n#define BIT__R_EN_RTY_BK_COD_8197F BIT(2)\n\n#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F 0\n#define BIT_MASK__R_DATA_FALLBACK_SEL_8197F 0x3\n#define BIT__R_DATA_FALLBACK_SEL_8197F(x)                                      \\\n\t(((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8197F)                           \\\n\t << BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F)\n#define BITS__R_DATA_FALLBACK_SEL_8197F                                        \\\n\t(BIT_MASK__R_DATA_FALLBACK_SEL_8197F                                   \\\n\t << BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F)\n#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8197F(x)                                \\\n\t((x) & (~BITS__R_DATA_FALLBACK_SEL_8197F))\n#define BIT_GET__R_DATA_FALLBACK_SEL_8197F(x)                                  \\\n\t(((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) &                       \\\n\t BIT_MASK__R_DATA_FALLBACK_SEL_8197F)\n#define BIT_SET__R_DATA_FALLBACK_SEL_8197F(x, v)                               \\\n\t(BIT_CLEAR__R_DATA_FALLBACK_SEL_8197F(x) |                             \\\n\t BIT__R_DATA_FALLBACK_SEL_8197F(v))\n\n/* 2 REG_BCNQ_BDNY_V1_8197F */\n\n#define BIT_SHIFT_BCNQ_PGBNDY_V1_8197F 0\n#define BIT_MASK_BCNQ_PGBNDY_V1_8197F 0xfff\n#define BIT_BCNQ_PGBNDY_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_BCNQ_PGBNDY_V1_8197F)                                 \\\n\t << BIT_SHIFT_BCNQ_PGBNDY_V1_8197F)\n#define BITS_BCNQ_PGBNDY_V1_8197F                                              \\\n\t(BIT_MASK_BCNQ_PGBNDY_V1_8197F << BIT_SHIFT_BCNQ_PGBNDY_V1_8197F)\n#define BIT_CLEAR_BCNQ_PGBNDY_V1_8197F(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8197F))\n#define BIT_GET_BCNQ_PGBNDY_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) &                             \\\n\t BIT_MASK_BCNQ_PGBNDY_V1_8197F)\n#define BIT_SET_BCNQ_PGBNDY_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_BCNQ_PGBNDY_V1_8197F(x) | BIT_BCNQ_PGBNDY_V1_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_LIFETIME_EN_8197F */\n#define BIT_BT_INT_CPU_8197F BIT(7)\n#define BIT_BT_INT_PTA_8197F BIT(6)\n#define BIT_EN_CTRL_RTYBIT_8197F BIT(4)\n#define BIT_LIFETIME_BK_EN_8197F BIT(3)\n#define BIT_LIFETIME_BE_EN_8197F BIT(2)\n#define BIT_LIFETIME_VI_EN_8197F BIT(1)\n#define BIT_LIFETIME_VO_EN_8197F BIT(0)\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_SPEC_SIFS_8197F */\n\n#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F 8\n#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F 0xff\n#define BIT_SPEC_SIFS_OFDM_PTCL_8197F(x)                                       \\\n\t(((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F)                            \\\n\t << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F)\n#define BITS_SPEC_SIFS_OFDM_PTCL_8197F                                         \\\n\t(BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F                                    \\\n\t << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F)\n#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8197F(x)                                 \\\n\t((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8197F))\n#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) &                        \\\n\t BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F)\n#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8197F(x, v)                                \\\n\t(BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8197F(x) |                              \\\n\t BIT_SPEC_SIFS_OFDM_PTCL_8197F(v))\n\n#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F 0\n#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F 0xff\n#define BIT_SPEC_SIFS_CCK_PTCL_8197F(x)                                        \\\n\t(((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F)                             \\\n\t << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F)\n#define BITS_SPEC_SIFS_CCK_PTCL_8197F                                          \\\n\t(BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F                                     \\\n\t << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F)\n#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8197F(x)                                  \\\n\t((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8197F))\n#define BIT_GET_SPEC_SIFS_CCK_PTCL_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) &                         \\\n\t BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F)\n#define BIT_SET_SPEC_SIFS_CCK_PTCL_8197F(x, v)                                 \\\n\t(BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8197F(x) |                               \\\n\t BIT_SPEC_SIFS_CCK_PTCL_8197F(v))\n\n/* 2 REG_RETRY_LIMIT_8197F */\n\n#define BIT_SHIFT_SRL_8197F 8\n#define BIT_MASK_SRL_8197F 0x3f\n#define BIT_SRL_8197F(x) (((x) & BIT_MASK_SRL_8197F) << BIT_SHIFT_SRL_8197F)\n#define BITS_SRL_8197F (BIT_MASK_SRL_8197F << BIT_SHIFT_SRL_8197F)\n#define BIT_CLEAR_SRL_8197F(x) ((x) & (~BITS_SRL_8197F))\n#define BIT_GET_SRL_8197F(x) (((x) >> BIT_SHIFT_SRL_8197F) & BIT_MASK_SRL_8197F)\n#define BIT_SET_SRL_8197F(x, v) (BIT_CLEAR_SRL_8197F(x) | BIT_SRL_8197F(v))\n\n#define BIT_SHIFT_LRL_8197F 0\n#define BIT_MASK_LRL_8197F 0x3f\n#define BIT_LRL_8197F(x) (((x) & BIT_MASK_LRL_8197F) << BIT_SHIFT_LRL_8197F)\n#define BITS_LRL_8197F (BIT_MASK_LRL_8197F << BIT_SHIFT_LRL_8197F)\n#define BIT_CLEAR_LRL_8197F(x) ((x) & (~BITS_LRL_8197F))\n#define BIT_GET_LRL_8197F(x) (((x) >> BIT_SHIFT_LRL_8197F) & BIT_MASK_LRL_8197F)\n#define BIT_SET_LRL_8197F(x, v) (BIT_CLEAR_LRL_8197F(x) | BIT_LRL_8197F(v))\n\n/* 2 REG_TXBF_CTRL_8197F */\n#define BIT_R_ENABLE_NDPA_8197F BIT(31)\n#define BIT_USE_NDPA_PARAMETER_8197F BIT(30)\n#define BIT_R_PROP_TXBF_8197F BIT(29)\n#define BIT_R_EN_NDPA_INT_8197F BIT(28)\n#define BIT_R_TXBF1_80M_8197F BIT(27)\n#define BIT_R_TXBF1_40M_8197F BIT(26)\n#define BIT_R_TXBF1_20M_8197F BIT(25)\n\n#define BIT_SHIFT_R_TXBF1_AID_8197F 16\n#define BIT_MASK_R_TXBF1_AID_8197F 0x1ff\n#define BIT_R_TXBF1_AID_8197F(x)                                               \\\n\t(((x) & BIT_MASK_R_TXBF1_AID_8197F) << BIT_SHIFT_R_TXBF1_AID_8197F)\n#define BITS_R_TXBF1_AID_8197F                                                 \\\n\t(BIT_MASK_R_TXBF1_AID_8197F << BIT_SHIFT_R_TXBF1_AID_8197F)\n#define BIT_CLEAR_R_TXBF1_AID_8197F(x) ((x) & (~BITS_R_TXBF1_AID_8197F))\n#define BIT_GET_R_TXBF1_AID_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_R_TXBF1_AID_8197F) & BIT_MASK_R_TXBF1_AID_8197F)\n#define BIT_SET_R_TXBF1_AID_8197F(x, v)                                        \\\n\t(BIT_CLEAR_R_TXBF1_AID_8197F(x) | BIT_R_TXBF1_AID_8197F(v))\n\n#define BIT_DIS_NDP_BFEN_8197F BIT(15)\n#define BIT_R_TXBCN_NOBLOCK_NDP_8197F BIT(14)\n#define BIT_R_TXBF0_80M_8197F BIT(11)\n#define BIT_R_TXBF0_40M_8197F BIT(10)\n#define BIT_R_TXBF0_20M_8197F BIT(9)\n\n#define BIT_SHIFT_R_TXBF0_AID_8197F 0\n#define BIT_MASK_R_TXBF0_AID_8197F 0x1ff\n#define BIT_R_TXBF0_AID_8197F(x)                                               \\\n\t(((x) & BIT_MASK_R_TXBF0_AID_8197F) << BIT_SHIFT_R_TXBF0_AID_8197F)\n#define BITS_R_TXBF0_AID_8197F                                                 \\\n\t(BIT_MASK_R_TXBF0_AID_8197F << BIT_SHIFT_R_TXBF0_AID_8197F)\n#define BIT_CLEAR_R_TXBF0_AID_8197F(x) ((x) & (~BITS_R_TXBF0_AID_8197F))\n#define BIT_GET_R_TXBF0_AID_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_R_TXBF0_AID_8197F) & BIT_MASK_R_TXBF0_AID_8197F)\n#define BIT_SET_R_TXBF0_AID_8197F(x, v)                                        \\\n\t(BIT_CLEAR_R_TXBF0_AID_8197F(x) | BIT_R_TXBF0_AID_8197F(v))\n\n/* 2 REG_DARFRC_8197F */\n\n#define BIT_SHIFT_DARF_RC8_V2_8197F (56 & CPU_OPT_WIDTH)\n#define BIT_MASK_DARF_RC8_V2_8197F 0x3f\n#define BIT_DARF_RC8_V2_8197F(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC8_V2_8197F) << BIT_SHIFT_DARF_RC8_V2_8197F)\n#define BITS_DARF_RC8_V2_8197F                                                 \\\n\t(BIT_MASK_DARF_RC8_V2_8197F << BIT_SHIFT_DARF_RC8_V2_8197F)\n#define BIT_CLEAR_DARF_RC8_V2_8197F(x) ((x) & (~BITS_DARF_RC8_V2_8197F))\n#define BIT_GET_DARF_RC8_V2_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC8_V2_8197F) & BIT_MASK_DARF_RC8_V2_8197F)\n#define BIT_SET_DARF_RC8_V2_8197F(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC8_V2_8197F(x) | BIT_DARF_RC8_V2_8197F(v))\n\n#define BIT_SHIFT_DARF_RC7_V2_8197F (48 & CPU_OPT_WIDTH)\n#define BIT_MASK_DARF_RC7_V2_8197F 0x3f\n#define BIT_DARF_RC7_V2_8197F(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC7_V2_8197F) << BIT_SHIFT_DARF_RC7_V2_8197F)\n#define BITS_DARF_RC7_V2_8197F                                                 \\\n\t(BIT_MASK_DARF_RC7_V2_8197F << BIT_SHIFT_DARF_RC7_V2_8197F)\n#define BIT_CLEAR_DARF_RC7_V2_8197F(x) ((x) & (~BITS_DARF_RC7_V2_8197F))\n#define BIT_GET_DARF_RC7_V2_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC7_V2_8197F) & BIT_MASK_DARF_RC7_V2_8197F)\n#define BIT_SET_DARF_RC7_V2_8197F(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC7_V2_8197F(x) | BIT_DARF_RC7_V2_8197F(v))\n\n#define BIT_SHIFT_DARF_RC6_V2_8197F (40 & CPU_OPT_WIDTH)\n#define BIT_MASK_DARF_RC6_V2_8197F 0x3f\n#define BIT_DARF_RC6_V2_8197F(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC6_V2_8197F) << BIT_SHIFT_DARF_RC6_V2_8197F)\n#define BITS_DARF_RC6_V2_8197F                                                 \\\n\t(BIT_MASK_DARF_RC6_V2_8197F << BIT_SHIFT_DARF_RC6_V2_8197F)\n#define BIT_CLEAR_DARF_RC6_V2_8197F(x) ((x) & (~BITS_DARF_RC6_V2_8197F))\n#define BIT_GET_DARF_RC6_V2_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC6_V2_8197F) & BIT_MASK_DARF_RC6_V2_8197F)\n#define BIT_SET_DARF_RC6_V2_8197F(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC6_V2_8197F(x) | BIT_DARF_RC6_V2_8197F(v))\n\n#define BIT_SHIFT_DARF_RC5_V2_8197F (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_DARF_RC5_V2_8197F 0x3f\n#define BIT_DARF_RC5_V2_8197F(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC5_V2_8197F) << BIT_SHIFT_DARF_RC5_V2_8197F)\n#define BITS_DARF_RC5_V2_8197F                                                 \\\n\t(BIT_MASK_DARF_RC5_V2_8197F << BIT_SHIFT_DARF_RC5_V2_8197F)\n#define BIT_CLEAR_DARF_RC5_V2_8197F(x) ((x) & (~BITS_DARF_RC5_V2_8197F))\n#define BIT_GET_DARF_RC5_V2_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC5_V2_8197F) & BIT_MASK_DARF_RC5_V2_8197F)\n#define BIT_SET_DARF_RC5_V2_8197F(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC5_V2_8197F(x) | BIT_DARF_RC5_V2_8197F(v))\n\n#define BIT_SHIFT_DARF_RC4_V1_8197F 24\n#define BIT_MASK_DARF_RC4_V1_8197F 0x3f\n#define BIT_DARF_RC4_V1_8197F(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC4_V1_8197F) << BIT_SHIFT_DARF_RC4_V1_8197F)\n#define BITS_DARF_RC4_V1_8197F                                                 \\\n\t(BIT_MASK_DARF_RC4_V1_8197F << BIT_SHIFT_DARF_RC4_V1_8197F)\n#define BIT_CLEAR_DARF_RC4_V1_8197F(x) ((x) & (~BITS_DARF_RC4_V1_8197F))\n#define BIT_GET_DARF_RC4_V1_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC4_V1_8197F) & BIT_MASK_DARF_RC4_V1_8197F)\n#define BIT_SET_DARF_RC4_V1_8197F(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC4_V1_8197F(x) | BIT_DARF_RC4_V1_8197F(v))\n\n#define BIT_SHIFT_DARF_RC3_V1_8197F 16\n#define BIT_MASK_DARF_RC3_V1_8197F 0x3f\n#define BIT_DARF_RC3_V1_8197F(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC3_V1_8197F) << BIT_SHIFT_DARF_RC3_V1_8197F)\n#define BITS_DARF_RC3_V1_8197F                                                 \\\n\t(BIT_MASK_DARF_RC3_V1_8197F << BIT_SHIFT_DARF_RC3_V1_8197F)\n#define BIT_CLEAR_DARF_RC3_V1_8197F(x) ((x) & (~BITS_DARF_RC3_V1_8197F))\n#define BIT_GET_DARF_RC3_V1_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC3_V1_8197F) & BIT_MASK_DARF_RC3_V1_8197F)\n#define BIT_SET_DARF_RC3_V1_8197F(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC3_V1_8197F(x) | BIT_DARF_RC3_V1_8197F(v))\n\n#define BIT_SHIFT_DARF_RC2_V1_8197F 8\n#define BIT_MASK_DARF_RC2_V1_8197F 0x3f\n#define BIT_DARF_RC2_V1_8197F(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC2_V1_8197F) << BIT_SHIFT_DARF_RC2_V1_8197F)\n#define BITS_DARF_RC2_V1_8197F                                                 \\\n\t(BIT_MASK_DARF_RC2_V1_8197F << BIT_SHIFT_DARF_RC2_V1_8197F)\n#define BIT_CLEAR_DARF_RC2_V1_8197F(x) ((x) & (~BITS_DARF_RC2_V1_8197F))\n#define BIT_GET_DARF_RC2_V1_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC2_V1_8197F) & BIT_MASK_DARF_RC2_V1_8197F)\n#define BIT_SET_DARF_RC2_V1_8197F(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC2_V1_8197F(x) | BIT_DARF_RC2_V1_8197F(v))\n\n#define BIT_SHIFT_DARF_RC1_V1_8197F 0\n#define BIT_MASK_DARF_RC1_V1_8197F 0x3f\n#define BIT_DARF_RC1_V1_8197F(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC1_V1_8197F) << BIT_SHIFT_DARF_RC1_V1_8197F)\n#define BITS_DARF_RC1_V1_8197F                                                 \\\n\t(BIT_MASK_DARF_RC1_V1_8197F << BIT_SHIFT_DARF_RC1_V1_8197F)\n#define BIT_CLEAR_DARF_RC1_V1_8197F(x) ((x) & (~BITS_DARF_RC1_V1_8197F))\n#define BIT_GET_DARF_RC1_V1_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC1_V1_8197F) & BIT_MASK_DARF_RC1_V1_8197F)\n#define BIT_SET_DARF_RC1_V1_8197F(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC1_V1_8197F(x) | BIT_DARF_RC1_V1_8197F(v))\n\n/* 2 REG_RARFRC_8197F */\n\n#define BIT_SHIFT_RARF_RC8_8197F (56 & CPU_OPT_WIDTH)\n#define BIT_MASK_RARF_RC8_8197F 0x1f\n#define BIT_RARF_RC8_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC8_8197F) << BIT_SHIFT_RARF_RC8_8197F)\n#define BITS_RARF_RC8_8197F                                                    \\\n\t(BIT_MASK_RARF_RC8_8197F << BIT_SHIFT_RARF_RC8_8197F)\n#define BIT_CLEAR_RARF_RC8_8197F(x) ((x) & (~BITS_RARF_RC8_8197F))\n#define BIT_GET_RARF_RC8_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC8_8197F) & BIT_MASK_RARF_RC8_8197F)\n#define BIT_SET_RARF_RC8_8197F(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC8_8197F(x) | BIT_RARF_RC8_8197F(v))\n\n#define BIT_SHIFT_RARF_RC7_8197F (48 & CPU_OPT_WIDTH)\n#define BIT_MASK_RARF_RC7_8197F 0x1f\n#define BIT_RARF_RC7_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC7_8197F) << BIT_SHIFT_RARF_RC7_8197F)\n#define BITS_RARF_RC7_8197F                                                    \\\n\t(BIT_MASK_RARF_RC7_8197F << BIT_SHIFT_RARF_RC7_8197F)\n#define BIT_CLEAR_RARF_RC7_8197F(x) ((x) & (~BITS_RARF_RC7_8197F))\n#define BIT_GET_RARF_RC7_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC7_8197F) & BIT_MASK_RARF_RC7_8197F)\n#define BIT_SET_RARF_RC7_8197F(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC7_8197F(x) | BIT_RARF_RC7_8197F(v))\n\n#define BIT_SHIFT_RARF_RC6_8197F (40 & CPU_OPT_WIDTH)\n#define BIT_MASK_RARF_RC6_8197F 0x1f\n#define BIT_RARF_RC6_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC6_8197F) << BIT_SHIFT_RARF_RC6_8197F)\n#define BITS_RARF_RC6_8197F                                                    \\\n\t(BIT_MASK_RARF_RC6_8197F << BIT_SHIFT_RARF_RC6_8197F)\n#define BIT_CLEAR_RARF_RC6_8197F(x) ((x) & (~BITS_RARF_RC6_8197F))\n#define BIT_GET_RARF_RC6_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC6_8197F) & BIT_MASK_RARF_RC6_8197F)\n#define BIT_SET_RARF_RC6_8197F(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC6_8197F(x) | BIT_RARF_RC6_8197F(v))\n\n#define BIT_SHIFT_RARF_RC5_8197F (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_RARF_RC5_8197F 0x1f\n#define BIT_RARF_RC5_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC5_8197F) << BIT_SHIFT_RARF_RC5_8197F)\n#define BITS_RARF_RC5_8197F                                                    \\\n\t(BIT_MASK_RARF_RC5_8197F << BIT_SHIFT_RARF_RC5_8197F)\n#define BIT_CLEAR_RARF_RC5_8197F(x) ((x) & (~BITS_RARF_RC5_8197F))\n#define BIT_GET_RARF_RC5_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC5_8197F) & BIT_MASK_RARF_RC5_8197F)\n#define BIT_SET_RARF_RC5_8197F(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC5_8197F(x) | BIT_RARF_RC5_8197F(v))\n\n#define BIT_SHIFT_RARF_RC4_8197F 24\n#define BIT_MASK_RARF_RC4_8197F 0x1f\n#define BIT_RARF_RC4_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC4_8197F) << BIT_SHIFT_RARF_RC4_8197F)\n#define BITS_RARF_RC4_8197F                                                    \\\n\t(BIT_MASK_RARF_RC4_8197F << BIT_SHIFT_RARF_RC4_8197F)\n#define BIT_CLEAR_RARF_RC4_8197F(x) ((x) & (~BITS_RARF_RC4_8197F))\n#define BIT_GET_RARF_RC4_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC4_8197F) & BIT_MASK_RARF_RC4_8197F)\n#define BIT_SET_RARF_RC4_8197F(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC4_8197F(x) | BIT_RARF_RC4_8197F(v))\n\n#define BIT_SHIFT_RARF_RC3_8197F 16\n#define BIT_MASK_RARF_RC3_8197F 0x1f\n#define BIT_RARF_RC3_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC3_8197F) << BIT_SHIFT_RARF_RC3_8197F)\n#define BITS_RARF_RC3_8197F                                                    \\\n\t(BIT_MASK_RARF_RC3_8197F << BIT_SHIFT_RARF_RC3_8197F)\n#define BIT_CLEAR_RARF_RC3_8197F(x) ((x) & (~BITS_RARF_RC3_8197F))\n#define BIT_GET_RARF_RC3_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC3_8197F) & BIT_MASK_RARF_RC3_8197F)\n#define BIT_SET_RARF_RC3_8197F(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC3_8197F(x) | BIT_RARF_RC3_8197F(v))\n\n#define BIT_SHIFT_RARF_RC2_8197F 8\n#define BIT_MASK_RARF_RC2_8197F 0x1f\n#define BIT_RARF_RC2_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC2_8197F) << BIT_SHIFT_RARF_RC2_8197F)\n#define BITS_RARF_RC2_8197F                                                    \\\n\t(BIT_MASK_RARF_RC2_8197F << BIT_SHIFT_RARF_RC2_8197F)\n#define BIT_CLEAR_RARF_RC2_8197F(x) ((x) & (~BITS_RARF_RC2_8197F))\n#define BIT_GET_RARF_RC2_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC2_8197F) & BIT_MASK_RARF_RC2_8197F)\n#define BIT_SET_RARF_RC2_8197F(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC2_8197F(x) | BIT_RARF_RC2_8197F(v))\n\n#define BIT_SHIFT_RARF_RC1_8197F 0\n#define BIT_MASK_RARF_RC1_8197F 0x1f\n#define BIT_RARF_RC1_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC1_8197F) << BIT_SHIFT_RARF_RC1_8197F)\n#define BITS_RARF_RC1_8197F                                                    \\\n\t(BIT_MASK_RARF_RC1_8197F << BIT_SHIFT_RARF_RC1_8197F)\n#define BIT_CLEAR_RARF_RC1_8197F(x) ((x) & (~BITS_RARF_RC1_8197F))\n#define BIT_GET_RARF_RC1_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC1_8197F) & BIT_MASK_RARF_RC1_8197F)\n#define BIT_SET_RARF_RC1_8197F(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC1_8197F(x) | BIT_RARF_RC1_8197F(v))\n\n/* 2 REG_RRSR_8197F */\n#define BIT_EN_VHTBW_FALL_8197F BIT(31)\n#define BIT_EN_HTBW_FALL_8197F BIT(30)\n\n#define BIT_SHIFT_RRSR_RSC_8197F 21\n#define BIT_MASK_RRSR_RSC_8197F 0x3\n#define BIT_RRSR_RSC_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_RRSR_RSC_8197F) << BIT_SHIFT_RRSR_RSC_8197F)\n#define BITS_RRSR_RSC_8197F                                                    \\\n\t(BIT_MASK_RRSR_RSC_8197F << BIT_SHIFT_RRSR_RSC_8197F)\n#define BIT_CLEAR_RRSR_RSC_8197F(x) ((x) & (~BITS_RRSR_RSC_8197F))\n#define BIT_GET_RRSR_RSC_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_RRSR_RSC_8197F) & BIT_MASK_RRSR_RSC_8197F)\n#define BIT_SET_RRSR_RSC_8197F(x, v)                                           \\\n\t(BIT_CLEAR_RRSR_RSC_8197F(x) | BIT_RRSR_RSC_8197F(v))\n\n#define BIT_RRSR_BW_8197F BIT(20)\n\n#define BIT_SHIFT_RRSC_BITMAP_8197F 0\n#define BIT_MASK_RRSC_BITMAP_8197F 0xfffff\n#define BIT_RRSC_BITMAP_8197F(x)                                               \\\n\t(((x) & BIT_MASK_RRSC_BITMAP_8197F) << BIT_SHIFT_RRSC_BITMAP_8197F)\n#define BITS_RRSC_BITMAP_8197F                                                 \\\n\t(BIT_MASK_RRSC_BITMAP_8197F << BIT_SHIFT_RRSC_BITMAP_8197F)\n#define BIT_CLEAR_RRSC_BITMAP_8197F(x) ((x) & (~BITS_RRSC_BITMAP_8197F))\n#define BIT_GET_RRSC_BITMAP_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_RRSC_BITMAP_8197F) & BIT_MASK_RRSC_BITMAP_8197F)\n#define BIT_SET_RRSC_BITMAP_8197F(x, v)                                        \\\n\t(BIT_CLEAR_RRSC_BITMAP_8197F(x) | BIT_RRSC_BITMAP_8197F(v))\n\n/* 2 REG_ARFR0_8197F */\n\n#define BIT_SHIFT_ARFR0_V1_8197F 0\n#define BIT_MASK_ARFR0_V1_8197F 0xffffffffffffffffL\n#define BIT_ARFR0_V1_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_ARFR0_V1_8197F) << BIT_SHIFT_ARFR0_V1_8197F)\n#define BITS_ARFR0_V1_8197F                                                    \\\n\t(BIT_MASK_ARFR0_V1_8197F << BIT_SHIFT_ARFR0_V1_8197F)\n#define BIT_CLEAR_ARFR0_V1_8197F(x) ((x) & (~BITS_ARFR0_V1_8197F))\n#define BIT_GET_ARFR0_V1_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_ARFR0_V1_8197F) & BIT_MASK_ARFR0_V1_8197F)\n#define BIT_SET_ARFR0_V1_8197F(x, v)                                           \\\n\t(BIT_CLEAR_ARFR0_V1_8197F(x) | BIT_ARFR0_V1_8197F(v))\n\n/* 2 REG_ARFR1_V1_8197F */\n\n#define BIT_SHIFT_ARFR1_V1_8197F 0\n#define BIT_MASK_ARFR1_V1_8197F 0xffffffffffffffffL\n#define BIT_ARFR1_V1_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_ARFR1_V1_8197F) << BIT_SHIFT_ARFR1_V1_8197F)\n#define BITS_ARFR1_V1_8197F                                                    \\\n\t(BIT_MASK_ARFR1_V1_8197F << BIT_SHIFT_ARFR1_V1_8197F)\n#define BIT_CLEAR_ARFR1_V1_8197F(x) ((x) & (~BITS_ARFR1_V1_8197F))\n#define BIT_GET_ARFR1_V1_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_ARFR1_V1_8197F) & BIT_MASK_ARFR1_V1_8197F)\n#define BIT_SET_ARFR1_V1_8197F(x, v)                                           \\\n\t(BIT_CLEAR_ARFR1_V1_8197F(x) | BIT_ARFR1_V1_8197F(v))\n\n/* 2 REG_CCK_CHECK_8197F */\n#define BIT_CHECK_CCK_EN_8197F BIT(7)\n#define BIT_EN_BCN_PKT_REL_8197F BIT(6)\n#define BIT_BCN_PORT_SEL_8197F BIT(5)\n#define BIT_MOREDATA_BYPASS_8197F BIT(4)\n#define BIT_EN_CLR_CMD_REL_BCN_PKT_8197F BIT(3)\n#define BIT_R_EN_SET_MOREDATA_8197F BIT(2)\n#define BIT__R_DIS_CLEAR_MACID_RELEASE_8197F BIT(1)\n#define BIT__R_MACID_RELEASE_EN_8197F BIT(0)\n\n/* 2 REG_AMPDU_MAX_TIME_V1_8197F */\n\n#define BIT_SHIFT_AMPDU_MAX_TIME_8197F 0\n#define BIT_MASK_AMPDU_MAX_TIME_8197F 0xff\n#define BIT_AMPDU_MAX_TIME_8197F(x)                                            \\\n\t(((x) & BIT_MASK_AMPDU_MAX_TIME_8197F)                                 \\\n\t << BIT_SHIFT_AMPDU_MAX_TIME_8197F)\n#define BITS_AMPDU_MAX_TIME_8197F                                              \\\n\t(BIT_MASK_AMPDU_MAX_TIME_8197F << BIT_SHIFT_AMPDU_MAX_TIME_8197F)\n#define BIT_CLEAR_AMPDU_MAX_TIME_8197F(x) ((x) & (~BITS_AMPDU_MAX_TIME_8197F))\n#define BIT_GET_AMPDU_MAX_TIME_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8197F) &                             \\\n\t BIT_MASK_AMPDU_MAX_TIME_8197F)\n#define BIT_SET_AMPDU_MAX_TIME_8197F(x, v)                                     \\\n\t(BIT_CLEAR_AMPDU_MAX_TIME_8197F(x) | BIT_AMPDU_MAX_TIME_8197F(v))\n\n/* 2 REG_BCNQ1_BDNY_V1_8197F */\n\n#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F 0\n#define BIT_MASK_BCNQ1_PGBNDY_V1_8197F 0xfff\n#define BIT_BCNQ1_PGBNDY_V1_8197F(x)                                           \\\n\t(((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8197F)                                \\\n\t << BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F)\n#define BITS_BCNQ1_PGBNDY_V1_8197F                                             \\\n\t(BIT_MASK_BCNQ1_PGBNDY_V1_8197F << BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F)\n#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8197F(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8197F))\n#define BIT_GET_BCNQ1_PGBNDY_V1_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) &                            \\\n\t BIT_MASK_BCNQ1_PGBNDY_V1_8197F)\n#define BIT_SET_BCNQ1_PGBNDY_V1_8197F(x, v)                                    \\\n\t(BIT_CLEAR_BCNQ1_PGBNDY_V1_8197F(x) | BIT_BCNQ1_PGBNDY_V1_8197F(v))\n\n/* 2 REG_AMPDU_MAX_LENGTH_8197F */\n\n#define BIT_SHIFT_AMPDU_MAX_LENGTH_8197F 0\n#define BIT_MASK_AMPDU_MAX_LENGTH_8197F 0xffffffffL\n#define BIT_AMPDU_MAX_LENGTH_8197F(x)                                          \\\n\t(((x) & BIT_MASK_AMPDU_MAX_LENGTH_8197F)                               \\\n\t << BIT_SHIFT_AMPDU_MAX_LENGTH_8197F)\n#define BITS_AMPDU_MAX_LENGTH_8197F                                            \\\n\t(BIT_MASK_AMPDU_MAX_LENGTH_8197F << BIT_SHIFT_AMPDU_MAX_LENGTH_8197F)\n#define BIT_CLEAR_AMPDU_MAX_LENGTH_8197F(x)                                    \\\n\t((x) & (~BITS_AMPDU_MAX_LENGTH_8197F))\n#define BIT_GET_AMPDU_MAX_LENGTH_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) &                           \\\n\t BIT_MASK_AMPDU_MAX_LENGTH_8197F)\n#define BIT_SET_AMPDU_MAX_LENGTH_8197F(x, v)                                   \\\n\t(BIT_CLEAR_AMPDU_MAX_LENGTH_8197F(x) | BIT_AMPDU_MAX_LENGTH_8197F(v))\n\n/* 2 REG_ACQ_STOP_8197F */\n#define BIT_AC7Q_STOP_8197F BIT(7)\n#define BIT_AC6Q_STOP_8197F BIT(6)\n#define BIT_AC5Q_STOP_8197F BIT(5)\n#define BIT_AC4Q_STOP_8197F BIT(4)\n#define BIT_AC3Q_STOP_8197F BIT(3)\n#define BIT_AC2Q_STOP_8197F BIT(2)\n#define BIT_AC1Q_STOP_8197F BIT(1)\n#define BIT_AC0Q_STOP_8197F BIT(0)\n\n/* 2 REG_NDPA_RATE_8197F */\n\n#define BIT_SHIFT_R_NDPA_RATE_V1_8197F 0\n#define BIT_MASK_R_NDPA_RATE_V1_8197F 0xff\n#define BIT_R_NDPA_RATE_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_R_NDPA_RATE_V1_8197F)                                 \\\n\t << BIT_SHIFT_R_NDPA_RATE_V1_8197F)\n#define BITS_R_NDPA_RATE_V1_8197F                                              \\\n\t(BIT_MASK_R_NDPA_RATE_V1_8197F << BIT_SHIFT_R_NDPA_RATE_V1_8197F)\n#define BIT_CLEAR_R_NDPA_RATE_V1_8197F(x) ((x) & (~BITS_R_NDPA_RATE_V1_8197F))\n#define BIT_GET_R_NDPA_RATE_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8197F) &                             \\\n\t BIT_MASK_R_NDPA_RATE_V1_8197F)\n#define BIT_SET_R_NDPA_RATE_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_R_NDPA_RATE_V1_8197F(x) | BIT_R_NDPA_RATE_V1_8197F(v))\n\n/* 2 REG_TX_HANG_CTRL_8197F */\n#define BIT_R_EN_GNT_BT_AWAKE_8197F BIT(3)\n#define BIT_EN_EOF_V1_8197F BIT(2)\n#define BIT_DIS_OQT_BLOCK_8197F BIT(1)\n#define BIT_SEARCH_QUEUE_EN_8197F BIT(0)\n\n/* 2 REG_NDPA_OPT_CTRL_8197F */\n#define BIT_R_DIS_MACID_RELEASE_RTY_8197F BIT(5)\n\n#define BIT_SHIFT_BW_SIGTA_8197F 3\n#define BIT_MASK_BW_SIGTA_8197F 0x3\n#define BIT_BW_SIGTA_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_BW_SIGTA_8197F) << BIT_SHIFT_BW_SIGTA_8197F)\n#define BITS_BW_SIGTA_8197F                                                    \\\n\t(BIT_MASK_BW_SIGTA_8197F << BIT_SHIFT_BW_SIGTA_8197F)\n#define BIT_CLEAR_BW_SIGTA_8197F(x) ((x) & (~BITS_BW_SIGTA_8197F))\n#define BIT_GET_BW_SIGTA_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_BW_SIGTA_8197F) & BIT_MASK_BW_SIGTA_8197F)\n#define BIT_SET_BW_SIGTA_8197F(x, v)                                           \\\n\t(BIT_CLEAR_BW_SIGTA_8197F(x) | BIT_BW_SIGTA_8197F(v))\n\n#define BIT_EN_BAR_SIGTA_8197F BIT(2)\n\n#define BIT_SHIFT_R_NDPA_BW_8197F 0\n#define BIT_MASK_R_NDPA_BW_8197F 0x3\n#define BIT_R_NDPA_BW_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_R_NDPA_BW_8197F) << BIT_SHIFT_R_NDPA_BW_8197F)\n#define BITS_R_NDPA_BW_8197F                                                   \\\n\t(BIT_MASK_R_NDPA_BW_8197F << BIT_SHIFT_R_NDPA_BW_8197F)\n#define BIT_CLEAR_R_NDPA_BW_8197F(x) ((x) & (~BITS_R_NDPA_BW_8197F))\n#define BIT_GET_R_NDPA_BW_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_R_NDPA_BW_8197F) & BIT_MASK_R_NDPA_BW_8197F)\n#define BIT_SET_R_NDPA_BW_8197F(x, v)                                          \\\n\t(BIT_CLEAR_R_NDPA_BW_8197F(x) | BIT_R_NDPA_BW_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_RD_RESP_PKT_TH_8197F */\n\n#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F 0\n#define BIT_MASK_RD_RESP_PKT_TH_V1_8197F 0x3f\n#define BIT_RD_RESP_PKT_TH_V1_8197F(x)                                         \\\n\t(((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8197F)                              \\\n\t << BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F)\n#define BITS_RD_RESP_PKT_TH_V1_8197F                                           \\\n\t(BIT_MASK_RD_RESP_PKT_TH_V1_8197F << BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F)\n#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8197F(x)                                   \\\n\t((x) & (~BITS_RD_RESP_PKT_TH_V1_8197F))\n#define BIT_GET_RD_RESP_PKT_TH_V1_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) &                          \\\n\t BIT_MASK_RD_RESP_PKT_TH_V1_8197F)\n#define BIT_SET_RD_RESP_PKT_TH_V1_8197F(x, v)                                  \\\n\t(BIT_CLEAR_RD_RESP_PKT_TH_V1_8197F(x) | BIT_RD_RESP_PKT_TH_V1_8197F(v))\n\n/* 2 REG_CMDQ_INFO_8197F */\n\n#define BIT_SHIFT_PKT_NUM_8197F 23\n#define BIT_MASK_PKT_NUM_8197F 0x1ff\n#define BIT_PKT_NUM_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_PKT_NUM_8197F) << BIT_SHIFT_PKT_NUM_8197F)\n#define BITS_PKT_NUM_8197F (BIT_MASK_PKT_NUM_8197F << BIT_SHIFT_PKT_NUM_8197F)\n#define BIT_CLEAR_PKT_NUM_8197F(x) ((x) & (~BITS_PKT_NUM_8197F))\n#define BIT_GET_PKT_NUM_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_8197F) & BIT_MASK_PKT_NUM_8197F)\n#define BIT_SET_PKT_NUM_8197F(x, v)                                            \\\n\t(BIT_CLEAR_PKT_NUM_8197F(x) | BIT_PKT_NUM_8197F(v))\n\n#define BIT_TIDEMPTY_CMDQ_V1_8197F BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F 11\n#define BIT_MASK_TAIL_PKT_CMDQ_V2_8197F 0x7ff\n#define BIT_TAIL_PKT_CMDQ_V2_8197F(x)                                          \\\n\t(((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8197F)                               \\\n\t << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F)\n#define BITS_TAIL_PKT_CMDQ_V2_8197F                                            \\\n\t(BIT_MASK_TAIL_PKT_CMDQ_V2_8197F << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F)\n#define BIT_CLEAR_TAIL_PKT_CMDQ_V2_8197F(x)                                    \\\n\t((x) & (~BITS_TAIL_PKT_CMDQ_V2_8197F))\n#define BIT_GET_TAIL_PKT_CMDQ_V2_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) &                           \\\n\t BIT_MASK_TAIL_PKT_CMDQ_V2_8197F)\n#define BIT_SET_TAIL_PKT_CMDQ_V2_8197F(x, v)                                   \\\n\t(BIT_CLEAR_TAIL_PKT_CMDQ_V2_8197F(x) | BIT_TAIL_PKT_CMDQ_V2_8197F(v))\n\n#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F 0\n#define BIT_MASK_HEAD_PKT_CMDQ_V1_8197F 0x7ff\n#define BIT_HEAD_PKT_CMDQ_V1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8197F)                               \\\n\t << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F)\n#define BITS_HEAD_PKT_CMDQ_V1_8197F                                            \\\n\t(BIT_MASK_HEAD_PKT_CMDQ_V1_8197F << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F)\n#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8197F(x)                                    \\\n\t((x) & (~BITS_HEAD_PKT_CMDQ_V1_8197F))\n#define BIT_GET_HEAD_PKT_CMDQ_V1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) &                           \\\n\t BIT_MASK_HEAD_PKT_CMDQ_V1_8197F)\n#define BIT_SET_HEAD_PKT_CMDQ_V1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_HEAD_PKT_CMDQ_V1_8197F(x) | BIT_HEAD_PKT_CMDQ_V1_8197F(v))\n\n/* 2 REG_Q4_INFO_8197F */\n\n#define BIT_SHIFT_QUEUEMACID_Q4_V1_8197F 25\n#define BIT_MASK_QUEUEMACID_Q4_V1_8197F 0x7f\n#define BIT_QUEUEMACID_Q4_V1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q4_V1_8197F)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q4_V1_8197F)\n#define BITS_QUEUEMACID_Q4_V1_8197F                                            \\\n\t(BIT_MASK_QUEUEMACID_Q4_V1_8197F << BIT_SHIFT_QUEUEMACID_Q4_V1_8197F)\n#define BIT_CLEAR_QUEUEMACID_Q4_V1_8197F(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q4_V1_8197F))\n#define BIT_GET_QUEUEMACID_Q4_V1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) &                           \\\n\t BIT_MASK_QUEUEMACID_Q4_V1_8197F)\n#define BIT_SET_QUEUEMACID_Q4_V1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q4_V1_8197F(x) | BIT_QUEUEMACID_Q4_V1_8197F(v))\n\n#define BIT_SHIFT_QUEUEAC_Q4_V1_8197F 23\n#define BIT_MASK_QUEUEAC_Q4_V1_8197F 0x3\n#define BIT_QUEUEAC_Q4_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q4_V1_8197F) << BIT_SHIFT_QUEUEAC_Q4_V1_8197F)\n#define BITS_QUEUEAC_Q4_V1_8197F                                               \\\n\t(BIT_MASK_QUEUEAC_Q4_V1_8197F << BIT_SHIFT_QUEUEAC_Q4_V1_8197F)\n#define BIT_CLEAR_QUEUEAC_Q4_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8197F))\n#define BIT_GET_QUEUEAC_Q4_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8197F) & BIT_MASK_QUEUEAC_Q4_V1_8197F)\n#define BIT_SET_QUEUEAC_Q4_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q4_V1_8197F(x) | BIT_QUEUEAC_Q4_V1_8197F(v))\n\n#define BIT_TIDEMPTY_Q4_V1_8197F BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q4_V2_8197F 11\n#define BIT_MASK_TAIL_PKT_Q4_V2_8197F 0x7ff\n#define BIT_TAIL_PKT_Q4_V2_8197F(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q4_V2_8197F)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q4_V2_8197F)\n#define BITS_TAIL_PKT_Q4_V2_8197F                                              \\\n\t(BIT_MASK_TAIL_PKT_Q4_V2_8197F << BIT_SHIFT_TAIL_PKT_Q4_V2_8197F)\n#define BIT_CLEAR_TAIL_PKT_Q4_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8197F))\n#define BIT_GET_TAIL_PKT_Q4_V2_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) &                             \\\n\t BIT_MASK_TAIL_PKT_Q4_V2_8197F)\n#define BIT_SET_TAIL_PKT_Q4_V2_8197F(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q4_V2_8197F(x) | BIT_TAIL_PKT_Q4_V2_8197F(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q4_V1_8197F 0\n#define BIT_MASK_HEAD_PKT_Q4_V1_8197F 0x7ff\n#define BIT_HEAD_PKT_Q4_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q4_V1_8197F)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q4_V1_8197F)\n#define BITS_HEAD_PKT_Q4_V1_8197F                                              \\\n\t(BIT_MASK_HEAD_PKT_Q4_V1_8197F << BIT_SHIFT_HEAD_PKT_Q4_V1_8197F)\n#define BIT_CLEAR_HEAD_PKT_Q4_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8197F))\n#define BIT_GET_HEAD_PKT_Q4_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) &                             \\\n\t BIT_MASK_HEAD_PKT_Q4_V1_8197F)\n#define BIT_SET_HEAD_PKT_Q4_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q4_V1_8197F(x) | BIT_HEAD_PKT_Q4_V1_8197F(v))\n\n/* 2 REG_Q5_INFO_8197F */\n\n#define BIT_SHIFT_QUEUEMACID_Q5_V1_8197F 25\n#define BIT_MASK_QUEUEMACID_Q5_V1_8197F 0x7f\n#define BIT_QUEUEMACID_Q5_V1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q5_V1_8197F)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q5_V1_8197F)\n#define BITS_QUEUEMACID_Q5_V1_8197F                                            \\\n\t(BIT_MASK_QUEUEMACID_Q5_V1_8197F << BIT_SHIFT_QUEUEMACID_Q5_V1_8197F)\n#define BIT_CLEAR_QUEUEMACID_Q5_V1_8197F(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q5_V1_8197F))\n#define BIT_GET_QUEUEMACID_Q5_V1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) &                           \\\n\t BIT_MASK_QUEUEMACID_Q5_V1_8197F)\n#define BIT_SET_QUEUEMACID_Q5_V1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q5_V1_8197F(x) | BIT_QUEUEMACID_Q5_V1_8197F(v))\n\n#define BIT_SHIFT_QUEUEAC_Q5_V1_8197F 23\n#define BIT_MASK_QUEUEAC_Q5_V1_8197F 0x3\n#define BIT_QUEUEAC_Q5_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q5_V1_8197F) << BIT_SHIFT_QUEUEAC_Q5_V1_8197F)\n#define BITS_QUEUEAC_Q5_V1_8197F                                               \\\n\t(BIT_MASK_QUEUEAC_Q5_V1_8197F << BIT_SHIFT_QUEUEAC_Q5_V1_8197F)\n#define BIT_CLEAR_QUEUEAC_Q5_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8197F))\n#define BIT_GET_QUEUEAC_Q5_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8197F) & BIT_MASK_QUEUEAC_Q5_V1_8197F)\n#define BIT_SET_QUEUEAC_Q5_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q5_V1_8197F(x) | BIT_QUEUEAC_Q5_V1_8197F(v))\n\n#define BIT_TIDEMPTY_Q5_V1_8197F BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q5_V2_8197F 11\n#define BIT_MASK_TAIL_PKT_Q5_V2_8197F 0x7ff\n#define BIT_TAIL_PKT_Q5_V2_8197F(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q5_V2_8197F)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q5_V2_8197F)\n#define BITS_TAIL_PKT_Q5_V2_8197F                                              \\\n\t(BIT_MASK_TAIL_PKT_Q5_V2_8197F << BIT_SHIFT_TAIL_PKT_Q5_V2_8197F)\n#define BIT_CLEAR_TAIL_PKT_Q5_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8197F))\n#define BIT_GET_TAIL_PKT_Q5_V2_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) &                             \\\n\t BIT_MASK_TAIL_PKT_Q5_V2_8197F)\n#define BIT_SET_TAIL_PKT_Q5_V2_8197F(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q5_V2_8197F(x) | BIT_TAIL_PKT_Q5_V2_8197F(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q5_V1_8197F 0\n#define BIT_MASK_HEAD_PKT_Q5_V1_8197F 0x7ff\n#define BIT_HEAD_PKT_Q5_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q5_V1_8197F)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q5_V1_8197F)\n#define BITS_HEAD_PKT_Q5_V1_8197F                                              \\\n\t(BIT_MASK_HEAD_PKT_Q5_V1_8197F << BIT_SHIFT_HEAD_PKT_Q5_V1_8197F)\n#define BIT_CLEAR_HEAD_PKT_Q5_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8197F))\n#define BIT_GET_HEAD_PKT_Q5_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) &                             \\\n\t BIT_MASK_HEAD_PKT_Q5_V1_8197F)\n#define BIT_SET_HEAD_PKT_Q5_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q5_V1_8197F(x) | BIT_HEAD_PKT_Q5_V1_8197F(v))\n\n/* 2 REG_Q6_INFO_8197F */\n\n#define BIT_SHIFT_QUEUEMACID_Q6_V1_8197F 25\n#define BIT_MASK_QUEUEMACID_Q6_V1_8197F 0x7f\n#define BIT_QUEUEMACID_Q6_V1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q6_V1_8197F)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q6_V1_8197F)\n#define BITS_QUEUEMACID_Q6_V1_8197F                                            \\\n\t(BIT_MASK_QUEUEMACID_Q6_V1_8197F << BIT_SHIFT_QUEUEMACID_Q6_V1_8197F)\n#define BIT_CLEAR_QUEUEMACID_Q6_V1_8197F(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q6_V1_8197F))\n#define BIT_GET_QUEUEMACID_Q6_V1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) &                           \\\n\t BIT_MASK_QUEUEMACID_Q6_V1_8197F)\n#define BIT_SET_QUEUEMACID_Q6_V1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q6_V1_8197F(x) | BIT_QUEUEMACID_Q6_V1_8197F(v))\n\n#define BIT_SHIFT_QUEUEAC_Q6_V1_8197F 23\n#define BIT_MASK_QUEUEAC_Q6_V1_8197F 0x3\n#define BIT_QUEUEAC_Q6_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q6_V1_8197F) << BIT_SHIFT_QUEUEAC_Q6_V1_8197F)\n#define BITS_QUEUEAC_Q6_V1_8197F                                               \\\n\t(BIT_MASK_QUEUEAC_Q6_V1_8197F << BIT_SHIFT_QUEUEAC_Q6_V1_8197F)\n#define BIT_CLEAR_QUEUEAC_Q6_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8197F))\n#define BIT_GET_QUEUEAC_Q6_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8197F) & BIT_MASK_QUEUEAC_Q6_V1_8197F)\n#define BIT_SET_QUEUEAC_Q6_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q6_V1_8197F(x) | BIT_QUEUEAC_Q6_V1_8197F(v))\n\n#define BIT_TIDEMPTY_Q6_V1_8197F BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q6_V2_8197F 11\n#define BIT_MASK_TAIL_PKT_Q6_V2_8197F 0x7ff\n#define BIT_TAIL_PKT_Q6_V2_8197F(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q6_V2_8197F)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q6_V2_8197F)\n#define BITS_TAIL_PKT_Q6_V2_8197F                                              \\\n\t(BIT_MASK_TAIL_PKT_Q6_V2_8197F << BIT_SHIFT_TAIL_PKT_Q6_V2_8197F)\n#define BIT_CLEAR_TAIL_PKT_Q6_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8197F))\n#define BIT_GET_TAIL_PKT_Q6_V2_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) &                             \\\n\t BIT_MASK_TAIL_PKT_Q6_V2_8197F)\n#define BIT_SET_TAIL_PKT_Q6_V2_8197F(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q6_V2_8197F(x) | BIT_TAIL_PKT_Q6_V2_8197F(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q6_V1_8197F 0\n#define BIT_MASK_HEAD_PKT_Q6_V1_8197F 0x7ff\n#define BIT_HEAD_PKT_Q6_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q6_V1_8197F)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q6_V1_8197F)\n#define BITS_HEAD_PKT_Q6_V1_8197F                                              \\\n\t(BIT_MASK_HEAD_PKT_Q6_V1_8197F << BIT_SHIFT_HEAD_PKT_Q6_V1_8197F)\n#define BIT_CLEAR_HEAD_PKT_Q6_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8197F))\n#define BIT_GET_HEAD_PKT_Q6_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) &                             \\\n\t BIT_MASK_HEAD_PKT_Q6_V1_8197F)\n#define BIT_SET_HEAD_PKT_Q6_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q6_V1_8197F(x) | BIT_HEAD_PKT_Q6_V1_8197F(v))\n\n/* 2 REG_Q7_INFO_8197F */\n\n#define BIT_SHIFT_QUEUEMACID_Q7_V1_8197F 25\n#define BIT_MASK_QUEUEMACID_Q7_V1_8197F 0x7f\n#define BIT_QUEUEMACID_Q7_V1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q7_V1_8197F)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q7_V1_8197F)\n#define BITS_QUEUEMACID_Q7_V1_8197F                                            \\\n\t(BIT_MASK_QUEUEMACID_Q7_V1_8197F << BIT_SHIFT_QUEUEMACID_Q7_V1_8197F)\n#define BIT_CLEAR_QUEUEMACID_Q7_V1_8197F(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q7_V1_8197F))\n#define BIT_GET_QUEUEMACID_Q7_V1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) &                           \\\n\t BIT_MASK_QUEUEMACID_Q7_V1_8197F)\n#define BIT_SET_QUEUEMACID_Q7_V1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q7_V1_8197F(x) | BIT_QUEUEMACID_Q7_V1_8197F(v))\n\n#define BIT_SHIFT_QUEUEAC_Q7_V1_8197F 23\n#define BIT_MASK_QUEUEAC_Q7_V1_8197F 0x3\n#define BIT_QUEUEAC_Q7_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q7_V1_8197F) << BIT_SHIFT_QUEUEAC_Q7_V1_8197F)\n#define BITS_QUEUEAC_Q7_V1_8197F                                               \\\n\t(BIT_MASK_QUEUEAC_Q7_V1_8197F << BIT_SHIFT_QUEUEAC_Q7_V1_8197F)\n#define BIT_CLEAR_QUEUEAC_Q7_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8197F))\n#define BIT_GET_QUEUEAC_Q7_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8197F) & BIT_MASK_QUEUEAC_Q7_V1_8197F)\n#define BIT_SET_QUEUEAC_Q7_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q7_V1_8197F(x) | BIT_QUEUEAC_Q7_V1_8197F(v))\n\n#define BIT_TIDEMPTY_Q7_V1_8197F BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q7_V2_8197F 11\n#define BIT_MASK_TAIL_PKT_Q7_V2_8197F 0x7ff\n#define BIT_TAIL_PKT_Q7_V2_8197F(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q7_V2_8197F)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q7_V2_8197F)\n#define BITS_TAIL_PKT_Q7_V2_8197F                                              \\\n\t(BIT_MASK_TAIL_PKT_Q7_V2_8197F << BIT_SHIFT_TAIL_PKT_Q7_V2_8197F)\n#define BIT_CLEAR_TAIL_PKT_Q7_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8197F))\n#define BIT_GET_TAIL_PKT_Q7_V2_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) &                             \\\n\t BIT_MASK_TAIL_PKT_Q7_V2_8197F)\n#define BIT_SET_TAIL_PKT_Q7_V2_8197F(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q7_V2_8197F(x) | BIT_TAIL_PKT_Q7_V2_8197F(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q7_V1_8197F 0\n#define BIT_MASK_HEAD_PKT_Q7_V1_8197F 0x7ff\n#define BIT_HEAD_PKT_Q7_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q7_V1_8197F)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q7_V1_8197F)\n#define BITS_HEAD_PKT_Q7_V1_8197F                                              \\\n\t(BIT_MASK_HEAD_PKT_Q7_V1_8197F << BIT_SHIFT_HEAD_PKT_Q7_V1_8197F)\n#define BIT_CLEAR_HEAD_PKT_Q7_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8197F))\n#define BIT_GET_HEAD_PKT_Q7_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) &                             \\\n\t BIT_MASK_HEAD_PKT_Q7_V1_8197F)\n#define BIT_SET_HEAD_PKT_Q7_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q7_V1_8197F(x) | BIT_HEAD_PKT_Q7_V1_8197F(v))\n\n/* 2 REG_WMAC_LBK_BUF_HD_V1_8197F */\n\n#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F 0\n#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F 0xfff\n#define BIT_WMAC_LBK_BUF_HEAD_V1_8197F(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F)                           \\\n\t << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F)\n#define BITS_WMAC_LBK_BUF_HEAD_V1_8197F                                        \\\n\t(BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F                                   \\\n\t << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F)\n#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8197F(x)                                \\\n\t((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8197F))\n#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8197F(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) &                       \\\n\t BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F)\n#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8197F(x, v)                               \\\n\t(BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8197F(x) |                             \\\n\t BIT_WMAC_LBK_BUF_HEAD_V1_8197F(v))\n\n/* 2 REG_MGQ_BDNY_V1_8197F */\n\n#define BIT_SHIFT_MGQ_PGBNDY_V1_8197F 0\n#define BIT_MASK_MGQ_PGBNDY_V1_8197F 0xfff\n#define BIT_MGQ_PGBNDY_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_PGBNDY_V1_8197F) << BIT_SHIFT_MGQ_PGBNDY_V1_8197F)\n#define BITS_MGQ_PGBNDY_V1_8197F                                               \\\n\t(BIT_MASK_MGQ_PGBNDY_V1_8197F << BIT_SHIFT_MGQ_PGBNDY_V1_8197F)\n#define BIT_CLEAR_MGQ_PGBNDY_V1_8197F(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8197F))\n#define BIT_GET_MGQ_PGBNDY_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8197F) & BIT_MASK_MGQ_PGBNDY_V1_8197F)\n#define BIT_SET_MGQ_PGBNDY_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_PGBNDY_V1_8197F(x) | BIT_MGQ_PGBNDY_V1_8197F(v))\n\n/* 2 REG_TXRPT_CTRL_8197F */\n\n#define BIT_SHIFT_TRXRPT_TIMER_TH_8197F 24\n#define BIT_MASK_TRXRPT_TIMER_TH_8197F 0xff\n#define BIT_TRXRPT_TIMER_TH_8197F(x)                                           \\\n\t(((x) & BIT_MASK_TRXRPT_TIMER_TH_8197F)                                \\\n\t << BIT_SHIFT_TRXRPT_TIMER_TH_8197F)\n#define BITS_TRXRPT_TIMER_TH_8197F                                             \\\n\t(BIT_MASK_TRXRPT_TIMER_TH_8197F << BIT_SHIFT_TRXRPT_TIMER_TH_8197F)\n#define BIT_CLEAR_TRXRPT_TIMER_TH_8197F(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8197F))\n#define BIT_GET_TRXRPT_TIMER_TH_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8197F) &                            \\\n\t BIT_MASK_TRXRPT_TIMER_TH_8197F)\n#define BIT_SET_TRXRPT_TIMER_TH_8197F(x, v)                                    \\\n\t(BIT_CLEAR_TRXRPT_TIMER_TH_8197F(x) | BIT_TRXRPT_TIMER_TH_8197F(v))\n\n#define BIT_SHIFT_TRXRPT_LEN_TH_8197F 16\n#define BIT_MASK_TRXRPT_LEN_TH_8197F 0xff\n#define BIT_TRXRPT_LEN_TH_8197F(x)                                             \\\n\t(((x) & BIT_MASK_TRXRPT_LEN_TH_8197F) << BIT_SHIFT_TRXRPT_LEN_TH_8197F)\n#define BITS_TRXRPT_LEN_TH_8197F                                               \\\n\t(BIT_MASK_TRXRPT_LEN_TH_8197F << BIT_SHIFT_TRXRPT_LEN_TH_8197F)\n#define BIT_CLEAR_TRXRPT_LEN_TH_8197F(x) ((x) & (~BITS_TRXRPT_LEN_TH_8197F))\n#define BIT_GET_TRXRPT_LEN_TH_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8197F) & BIT_MASK_TRXRPT_LEN_TH_8197F)\n#define BIT_SET_TRXRPT_LEN_TH_8197F(x, v)                                      \\\n\t(BIT_CLEAR_TRXRPT_LEN_TH_8197F(x) | BIT_TRXRPT_LEN_TH_8197F(v))\n\n#define BIT_SHIFT_TRXRPT_READ_PTR_8197F 8\n#define BIT_MASK_TRXRPT_READ_PTR_8197F 0xff\n#define BIT_TRXRPT_READ_PTR_8197F(x)                                           \\\n\t(((x) & BIT_MASK_TRXRPT_READ_PTR_8197F)                                \\\n\t << BIT_SHIFT_TRXRPT_READ_PTR_8197F)\n#define BITS_TRXRPT_READ_PTR_8197F                                             \\\n\t(BIT_MASK_TRXRPT_READ_PTR_8197F << BIT_SHIFT_TRXRPT_READ_PTR_8197F)\n#define BIT_CLEAR_TRXRPT_READ_PTR_8197F(x) ((x) & (~BITS_TRXRPT_READ_PTR_8197F))\n#define BIT_GET_TRXRPT_READ_PTR_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8197F) &                            \\\n\t BIT_MASK_TRXRPT_READ_PTR_8197F)\n#define BIT_SET_TRXRPT_READ_PTR_8197F(x, v)                                    \\\n\t(BIT_CLEAR_TRXRPT_READ_PTR_8197F(x) | BIT_TRXRPT_READ_PTR_8197F(v))\n\n#define BIT_SHIFT_TRXRPT_WRITE_PTR_8197F 0\n#define BIT_MASK_TRXRPT_WRITE_PTR_8197F 0xff\n#define BIT_TRXRPT_WRITE_PTR_8197F(x)                                          \\\n\t(((x) & BIT_MASK_TRXRPT_WRITE_PTR_8197F)                               \\\n\t << BIT_SHIFT_TRXRPT_WRITE_PTR_8197F)\n#define BITS_TRXRPT_WRITE_PTR_8197F                                            \\\n\t(BIT_MASK_TRXRPT_WRITE_PTR_8197F << BIT_SHIFT_TRXRPT_WRITE_PTR_8197F)\n#define BIT_CLEAR_TRXRPT_WRITE_PTR_8197F(x)                                    \\\n\t((x) & (~BITS_TRXRPT_WRITE_PTR_8197F))\n#define BIT_GET_TRXRPT_WRITE_PTR_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) &                           \\\n\t BIT_MASK_TRXRPT_WRITE_PTR_8197F)\n#define BIT_SET_TRXRPT_WRITE_PTR_8197F(x, v)                                   \\\n\t(BIT_CLEAR_TRXRPT_WRITE_PTR_8197F(x) | BIT_TRXRPT_WRITE_PTR_8197F(v))\n\n/* 2 REG_INIRTS_RATE_SEL_8197F */\n#define BIT_LEAG_RTS_BW_DUP_8197F BIT(5)\n\n/* 2 REG_BASIC_CFEND_RATE_8197F */\n\n#define BIT_SHIFT_BASIC_CFEND_RATE_8197F 0\n#define BIT_MASK_BASIC_CFEND_RATE_8197F 0x1f\n#define BIT_BASIC_CFEND_RATE_8197F(x)                                          \\\n\t(((x) & BIT_MASK_BASIC_CFEND_RATE_8197F)                               \\\n\t << BIT_SHIFT_BASIC_CFEND_RATE_8197F)\n#define BITS_BASIC_CFEND_RATE_8197F                                            \\\n\t(BIT_MASK_BASIC_CFEND_RATE_8197F << BIT_SHIFT_BASIC_CFEND_RATE_8197F)\n#define BIT_CLEAR_BASIC_CFEND_RATE_8197F(x)                                    \\\n\t((x) & (~BITS_BASIC_CFEND_RATE_8197F))\n#define BIT_GET_BASIC_CFEND_RATE_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8197F) &                           \\\n\t BIT_MASK_BASIC_CFEND_RATE_8197F)\n#define BIT_SET_BASIC_CFEND_RATE_8197F(x, v)                                   \\\n\t(BIT_CLEAR_BASIC_CFEND_RATE_8197F(x) | BIT_BASIC_CFEND_RATE_8197F(v))\n\n/* 2 REG_STBC_CFEND_RATE_8197F */\n\n#define BIT_SHIFT_STBC_CFEND_RATE_8197F 0\n#define BIT_MASK_STBC_CFEND_RATE_8197F 0x1f\n#define BIT_STBC_CFEND_RATE_8197F(x)                                           \\\n\t(((x) & BIT_MASK_STBC_CFEND_RATE_8197F)                                \\\n\t << BIT_SHIFT_STBC_CFEND_RATE_8197F)\n#define BITS_STBC_CFEND_RATE_8197F                                             \\\n\t(BIT_MASK_STBC_CFEND_RATE_8197F << BIT_SHIFT_STBC_CFEND_RATE_8197F)\n#define BIT_CLEAR_STBC_CFEND_RATE_8197F(x) ((x) & (~BITS_STBC_CFEND_RATE_8197F))\n#define BIT_GET_STBC_CFEND_RATE_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_STBC_CFEND_RATE_8197F) &                            \\\n\t BIT_MASK_STBC_CFEND_RATE_8197F)\n#define BIT_SET_STBC_CFEND_RATE_8197F(x, v)                                    \\\n\t(BIT_CLEAR_STBC_CFEND_RATE_8197F(x) | BIT_STBC_CFEND_RATE_8197F(v))\n\n/* 2 REG_DATA_SC_8197F */\n\n#define BIT_SHIFT_TXSC_40M_8197F 4\n#define BIT_MASK_TXSC_40M_8197F 0xf\n#define BIT_TXSC_40M_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_TXSC_40M_8197F) << BIT_SHIFT_TXSC_40M_8197F)\n#define BITS_TXSC_40M_8197F                                                    \\\n\t(BIT_MASK_TXSC_40M_8197F << BIT_SHIFT_TXSC_40M_8197F)\n#define BIT_CLEAR_TXSC_40M_8197F(x) ((x) & (~BITS_TXSC_40M_8197F))\n#define BIT_GET_TXSC_40M_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXSC_40M_8197F) & BIT_MASK_TXSC_40M_8197F)\n#define BIT_SET_TXSC_40M_8197F(x, v)                                           \\\n\t(BIT_CLEAR_TXSC_40M_8197F(x) | BIT_TXSC_40M_8197F(v))\n\n#define BIT_SHIFT_TXSC_20M_8197F 0\n#define BIT_MASK_TXSC_20M_8197F 0xf\n#define BIT_TXSC_20M_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_TXSC_20M_8197F) << BIT_SHIFT_TXSC_20M_8197F)\n#define BITS_TXSC_20M_8197F                                                    \\\n\t(BIT_MASK_TXSC_20M_8197F << BIT_SHIFT_TXSC_20M_8197F)\n#define BIT_CLEAR_TXSC_20M_8197F(x) ((x) & (~BITS_TXSC_20M_8197F))\n#define BIT_GET_TXSC_20M_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXSC_20M_8197F) & BIT_MASK_TXSC_20M_8197F)\n#define BIT_SET_TXSC_20M_8197F(x, v)                                           \\\n\t(BIT_CLEAR_TXSC_20M_8197F(x) | BIT_TXSC_20M_8197F(v))\n\n/* 2 REG_MACID_SLEEP3_8197F */\n\n#define BIT_SHIFT_MACID127_96_PKTSLEEP_8197F 0\n#define BIT_MASK_MACID127_96_PKTSLEEP_8197F 0xffffffffL\n#define BIT_MACID127_96_PKTSLEEP_8197F(x)                                      \\\n\t(((x) & BIT_MASK_MACID127_96_PKTSLEEP_8197F)                           \\\n\t << BIT_SHIFT_MACID127_96_PKTSLEEP_8197F)\n#define BITS_MACID127_96_PKTSLEEP_8197F                                        \\\n\t(BIT_MASK_MACID127_96_PKTSLEEP_8197F                                   \\\n\t << BIT_SHIFT_MACID127_96_PKTSLEEP_8197F)\n#define BIT_CLEAR_MACID127_96_PKTSLEEP_8197F(x)                                \\\n\t((x) & (~BITS_MACID127_96_PKTSLEEP_8197F))\n#define BIT_GET_MACID127_96_PKTSLEEP_8197F(x)                                  \\\n\t(((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) &                       \\\n\t BIT_MASK_MACID127_96_PKTSLEEP_8197F)\n#define BIT_SET_MACID127_96_PKTSLEEP_8197F(x, v)                               \\\n\t(BIT_CLEAR_MACID127_96_PKTSLEEP_8197F(x) |                             \\\n\t BIT_MACID127_96_PKTSLEEP_8197F(v))\n\n/* 2 REG_MACID_SLEEP1_8197F */\n\n#define BIT_SHIFT_MACID63_32_PKTSLEEP_8197F 0\n#define BIT_MASK_MACID63_32_PKTSLEEP_8197F 0xffffffffL\n#define BIT_MACID63_32_PKTSLEEP_8197F(x)                                       \\\n\t(((x) & BIT_MASK_MACID63_32_PKTSLEEP_8197F)                            \\\n\t << BIT_SHIFT_MACID63_32_PKTSLEEP_8197F)\n#define BITS_MACID63_32_PKTSLEEP_8197F                                         \\\n\t(BIT_MASK_MACID63_32_PKTSLEEP_8197F                                    \\\n\t << BIT_SHIFT_MACID63_32_PKTSLEEP_8197F)\n#define BIT_CLEAR_MACID63_32_PKTSLEEP_8197F(x)                                 \\\n\t((x) & (~BITS_MACID63_32_PKTSLEEP_8197F))\n#define BIT_GET_MACID63_32_PKTSLEEP_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) &                        \\\n\t BIT_MASK_MACID63_32_PKTSLEEP_8197F)\n#define BIT_SET_MACID63_32_PKTSLEEP_8197F(x, v)                                \\\n\t(BIT_CLEAR_MACID63_32_PKTSLEEP_8197F(x) |                              \\\n\t BIT_MACID63_32_PKTSLEEP_8197F(v))\n\n/* 2 REG_ARFR2_V1_8197F */\n\n#define BIT_SHIFT_ARFR2_V1_8197F 0\n#define BIT_MASK_ARFR2_V1_8197F 0xffffffffffffffffL\n#define BIT_ARFR2_V1_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_ARFR2_V1_8197F) << BIT_SHIFT_ARFR2_V1_8197F)\n#define BITS_ARFR2_V1_8197F                                                    \\\n\t(BIT_MASK_ARFR2_V1_8197F << BIT_SHIFT_ARFR2_V1_8197F)\n#define BIT_CLEAR_ARFR2_V1_8197F(x) ((x) & (~BITS_ARFR2_V1_8197F))\n#define BIT_GET_ARFR2_V1_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_ARFR2_V1_8197F) & BIT_MASK_ARFR2_V1_8197F)\n#define BIT_SET_ARFR2_V1_8197F(x, v)                                           \\\n\t(BIT_CLEAR_ARFR2_V1_8197F(x) | BIT_ARFR2_V1_8197F(v))\n\n/* 2 REG_ARFR3_V1_8197F */\n\n#define BIT_SHIFT_ARFR3_V1_8197F 0\n#define BIT_MASK_ARFR3_V1_8197F 0xffffffffffffffffL\n#define BIT_ARFR3_V1_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_ARFR3_V1_8197F) << BIT_SHIFT_ARFR3_V1_8197F)\n#define BITS_ARFR3_V1_8197F                                                    \\\n\t(BIT_MASK_ARFR3_V1_8197F << BIT_SHIFT_ARFR3_V1_8197F)\n#define BIT_CLEAR_ARFR3_V1_8197F(x) ((x) & (~BITS_ARFR3_V1_8197F))\n#define BIT_GET_ARFR3_V1_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_ARFR3_V1_8197F) & BIT_MASK_ARFR3_V1_8197F)\n#define BIT_SET_ARFR3_V1_8197F(x, v)                                           \\\n\t(BIT_CLEAR_ARFR3_V1_8197F(x) | BIT_ARFR3_V1_8197F(v))\n\n/* 2 REG_ARFR4_8197F */\n\n#define BIT_SHIFT_ARFR4_8197F 0\n#define BIT_MASK_ARFR4_8197F 0xffffffffffffffffL\n#define BIT_ARFR4_8197F(x)                                                     \\\n\t(((x) & BIT_MASK_ARFR4_8197F) << BIT_SHIFT_ARFR4_8197F)\n#define BITS_ARFR4_8197F (BIT_MASK_ARFR4_8197F << BIT_SHIFT_ARFR4_8197F)\n#define BIT_CLEAR_ARFR4_8197F(x) ((x) & (~BITS_ARFR4_8197F))\n#define BIT_GET_ARFR4_8197F(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ARFR4_8197F) & BIT_MASK_ARFR4_8197F)\n#define BIT_SET_ARFR4_8197F(x, v)                                              \\\n\t(BIT_CLEAR_ARFR4_8197F(x) | BIT_ARFR4_8197F(v))\n\n/* 2 REG_ARFR5_8197F */\n\n#define BIT_SHIFT_ARFR5_8197F 0\n#define BIT_MASK_ARFR5_8197F 0xffffffffffffffffL\n#define BIT_ARFR5_8197F(x)                                                     \\\n\t(((x) & BIT_MASK_ARFR5_8197F) << BIT_SHIFT_ARFR5_8197F)\n#define BITS_ARFR5_8197F (BIT_MASK_ARFR5_8197F << BIT_SHIFT_ARFR5_8197F)\n#define BIT_CLEAR_ARFR5_8197F(x) ((x) & (~BITS_ARFR5_8197F))\n#define BIT_GET_ARFR5_8197F(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ARFR5_8197F) & BIT_MASK_ARFR5_8197F)\n#define BIT_SET_ARFR5_8197F(x, v)                                              \\\n\t(BIT_CLEAR_ARFR5_8197F(x) | BIT_ARFR5_8197F(v))\n\n/* 2 REG_TXRPT_START_OFFSET_8197F */\n#define BIT_SHCUT_PARSE_DASA_8197F BIT(25)\n#define BIT_SHCUT_BYPASS_8197F BIT(24)\n#define BIT__R_RPTFIFO_1K_8197F BIT(16)\n\n#define BIT_SHIFT_MACID_CTRL_OFFSET_8197F 8\n#define BIT_MASK_MACID_CTRL_OFFSET_8197F 0xff\n#define BIT_MACID_CTRL_OFFSET_8197F(x)                                         \\\n\t(((x) & BIT_MASK_MACID_CTRL_OFFSET_8197F)                              \\\n\t << BIT_SHIFT_MACID_CTRL_OFFSET_8197F)\n#define BITS_MACID_CTRL_OFFSET_8197F                                           \\\n\t(BIT_MASK_MACID_CTRL_OFFSET_8197F << BIT_SHIFT_MACID_CTRL_OFFSET_8197F)\n#define BIT_CLEAR_MACID_CTRL_OFFSET_8197F(x)                                   \\\n\t((x) & (~BITS_MACID_CTRL_OFFSET_8197F))\n#define BIT_GET_MACID_CTRL_OFFSET_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8197F) &                          \\\n\t BIT_MASK_MACID_CTRL_OFFSET_8197F)\n#define BIT_SET_MACID_CTRL_OFFSET_8197F(x, v)                                  \\\n\t(BIT_CLEAR_MACID_CTRL_OFFSET_8197F(x) | BIT_MACID_CTRL_OFFSET_8197F(v))\n\n#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F 0\n#define BIT_MASK_AMPDU_TXRPT_OFFSET_8197F 0xff\n#define BIT_AMPDU_TXRPT_OFFSET_8197F(x)                                        \\\n\t(((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8197F)                             \\\n\t << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F)\n#define BITS_AMPDU_TXRPT_OFFSET_8197F                                          \\\n\t(BIT_MASK_AMPDU_TXRPT_OFFSET_8197F                                     \\\n\t << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F)\n#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8197F(x)                                  \\\n\t((x) & (~BITS_AMPDU_TXRPT_OFFSET_8197F))\n#define BIT_GET_AMPDU_TXRPT_OFFSET_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) &                         \\\n\t BIT_MASK_AMPDU_TXRPT_OFFSET_8197F)\n#define BIT_SET_AMPDU_TXRPT_OFFSET_8197F(x, v)                                 \\\n\t(BIT_CLEAR_AMPDU_TXRPT_OFFSET_8197F(x) |                               \\\n\t BIT_AMPDU_TXRPT_OFFSET_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_POWER_STAGE1_8197F */\n#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8197F BIT(31)\n#define BIT_PTA_WL_PRI_MASK_BCNQ_8197F BIT(30)\n#define BIT_PTA_WL_PRI_MASK_HIQ_8197F BIT(29)\n#define BIT_PTA_WL_PRI_MASK_MGQ_8197F BIT(28)\n#define BIT_PTA_WL_PRI_MASK_BK_8197F BIT(27)\n#define BIT_PTA_WL_PRI_MASK_BE_8197F BIT(26)\n#define BIT_PTA_WL_PRI_MASK_VI_8197F BIT(25)\n#define BIT_PTA_WL_PRI_MASK_VO_8197F BIT(24)\n\n#define BIT_SHIFT_POWER_STAGE1_8197F 0\n#define BIT_MASK_POWER_STAGE1_8197F 0xffffff\n#define BIT_POWER_STAGE1_8197F(x)                                              \\\n\t(((x) & BIT_MASK_POWER_STAGE1_8197F) << BIT_SHIFT_POWER_STAGE1_8197F)\n#define BITS_POWER_STAGE1_8197F                                                \\\n\t(BIT_MASK_POWER_STAGE1_8197F << BIT_SHIFT_POWER_STAGE1_8197F)\n#define BIT_CLEAR_POWER_STAGE1_8197F(x) ((x) & (~BITS_POWER_STAGE1_8197F))\n#define BIT_GET_POWER_STAGE1_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_POWER_STAGE1_8197F) & BIT_MASK_POWER_STAGE1_8197F)\n#define BIT_SET_POWER_STAGE1_8197F(x, v)                                       \\\n\t(BIT_CLEAR_POWER_STAGE1_8197F(x) | BIT_POWER_STAGE1_8197F(v))\n\n/* 2 REG_POWER_STAGE2_8197F */\n#define BIT__R_CTRL_PKT_POW_ADJ_8197F BIT(24)\n\n#define BIT_SHIFT_POWER_STAGE2_8197F 0\n#define BIT_MASK_POWER_STAGE2_8197F 0xffffff\n#define BIT_POWER_STAGE2_8197F(x)                                              \\\n\t(((x) & BIT_MASK_POWER_STAGE2_8197F) << BIT_SHIFT_POWER_STAGE2_8197F)\n#define BITS_POWER_STAGE2_8197F                                                \\\n\t(BIT_MASK_POWER_STAGE2_8197F << BIT_SHIFT_POWER_STAGE2_8197F)\n#define BIT_CLEAR_POWER_STAGE2_8197F(x) ((x) & (~BITS_POWER_STAGE2_8197F))\n#define BIT_GET_POWER_STAGE2_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_POWER_STAGE2_8197F) & BIT_MASK_POWER_STAGE2_8197F)\n#define BIT_SET_POWER_STAGE2_8197F(x, v)                                       \\\n\t(BIT_CLEAR_POWER_STAGE2_8197F(x) | BIT_POWER_STAGE2_8197F(v))\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8197F */\n\n#define BIT_SHIFT_PAD_NUM_THRES_8197F 24\n#define BIT_MASK_PAD_NUM_THRES_8197F 0x3f\n#define BIT_PAD_NUM_THRES_8197F(x)                                             \\\n\t(((x) & BIT_MASK_PAD_NUM_THRES_8197F) << BIT_SHIFT_PAD_NUM_THRES_8197F)\n#define BITS_PAD_NUM_THRES_8197F                                               \\\n\t(BIT_MASK_PAD_NUM_THRES_8197F << BIT_SHIFT_PAD_NUM_THRES_8197F)\n#define BIT_CLEAR_PAD_NUM_THRES_8197F(x) ((x) & (~BITS_PAD_NUM_THRES_8197F))\n#define BIT_GET_PAD_NUM_THRES_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_PAD_NUM_THRES_8197F) & BIT_MASK_PAD_NUM_THRES_8197F)\n#define BIT_SET_PAD_NUM_THRES_8197F(x, v)                                      \\\n\t(BIT_CLEAR_PAD_NUM_THRES_8197F(x) | BIT_PAD_NUM_THRES_8197F(v))\n\n#define BIT_R_DMA_THIS_QUEUE_BK_8197F BIT(23)\n#define BIT_R_DMA_THIS_QUEUE_BE_8197F BIT(22)\n#define BIT_R_DMA_THIS_QUEUE_VI_8197F BIT(21)\n#define BIT_R_DMA_THIS_QUEUE_VO_8197F BIT(20)\n\n#define BIT_SHIFT_R_TOTAL_LEN_TH_8197F 8\n#define BIT_MASK_R_TOTAL_LEN_TH_8197F 0xfff\n#define BIT_R_TOTAL_LEN_TH_8197F(x)                                            \\\n\t(((x) & BIT_MASK_R_TOTAL_LEN_TH_8197F)                                 \\\n\t << BIT_SHIFT_R_TOTAL_LEN_TH_8197F)\n#define BITS_R_TOTAL_LEN_TH_8197F                                              \\\n\t(BIT_MASK_R_TOTAL_LEN_TH_8197F << BIT_SHIFT_R_TOTAL_LEN_TH_8197F)\n#define BIT_CLEAR_R_TOTAL_LEN_TH_8197F(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8197F))\n#define BIT_GET_R_TOTAL_LEN_TH_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8197F) &                             \\\n\t BIT_MASK_R_TOTAL_LEN_TH_8197F)\n#define BIT_SET_R_TOTAL_LEN_TH_8197F(x, v)                                     \\\n\t(BIT_CLEAR_R_TOTAL_LEN_TH_8197F(x) | BIT_R_TOTAL_LEN_TH_8197F(v))\n\n#define BIT_EN_NEW_EARLY_8197F BIT(7)\n#define BIT_PRE_TX_CMD_8197F BIT(6)\n\n#define BIT_SHIFT_NUM_SCL_EN_8197F 4\n#define BIT_MASK_NUM_SCL_EN_8197F 0x3\n#define BIT_NUM_SCL_EN_8197F(x)                                                \\\n\t(((x) & BIT_MASK_NUM_SCL_EN_8197F) << BIT_SHIFT_NUM_SCL_EN_8197F)\n#define BITS_NUM_SCL_EN_8197F                                                  \\\n\t(BIT_MASK_NUM_SCL_EN_8197F << BIT_SHIFT_NUM_SCL_EN_8197F)\n#define BIT_CLEAR_NUM_SCL_EN_8197F(x) ((x) & (~BITS_NUM_SCL_EN_8197F))\n#define BIT_GET_NUM_SCL_EN_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_NUM_SCL_EN_8197F) & BIT_MASK_NUM_SCL_EN_8197F)\n#define BIT_SET_NUM_SCL_EN_8197F(x, v)                                         \\\n\t(BIT_CLEAR_NUM_SCL_EN_8197F(x) | BIT_NUM_SCL_EN_8197F(v))\n\n#define BIT_BK_EN_8197F BIT(3)\n#define BIT_BE_EN_8197F BIT(2)\n#define BIT_VI_EN_8197F BIT(1)\n#define BIT_VO_EN_8197F BIT(0)\n\n/* 2 REG_PKT_LIFE_TIME_8197F */\n\n#define BIT_SHIFT_PKT_LIFTIME_BEBK_8197F 16\n#define BIT_MASK_PKT_LIFTIME_BEBK_8197F 0xffff\n#define BIT_PKT_LIFTIME_BEBK_8197F(x)                                          \\\n\t(((x) & BIT_MASK_PKT_LIFTIME_BEBK_8197F)                               \\\n\t << BIT_SHIFT_PKT_LIFTIME_BEBK_8197F)\n#define BITS_PKT_LIFTIME_BEBK_8197F                                            \\\n\t(BIT_MASK_PKT_LIFTIME_BEBK_8197F << BIT_SHIFT_PKT_LIFTIME_BEBK_8197F)\n#define BIT_CLEAR_PKT_LIFTIME_BEBK_8197F(x)                                    \\\n\t((x) & (~BITS_PKT_LIFTIME_BEBK_8197F))\n#define BIT_GET_PKT_LIFTIME_BEBK_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) &                           \\\n\t BIT_MASK_PKT_LIFTIME_BEBK_8197F)\n#define BIT_SET_PKT_LIFTIME_BEBK_8197F(x, v)                                   \\\n\t(BIT_CLEAR_PKT_LIFTIME_BEBK_8197F(x) | BIT_PKT_LIFTIME_BEBK_8197F(v))\n\n#define BIT_SHIFT_PKT_LIFTIME_VOVI_8197F 0\n#define BIT_MASK_PKT_LIFTIME_VOVI_8197F 0xffff\n#define BIT_PKT_LIFTIME_VOVI_8197F(x)                                          \\\n\t(((x) & BIT_MASK_PKT_LIFTIME_VOVI_8197F)                               \\\n\t << BIT_SHIFT_PKT_LIFTIME_VOVI_8197F)\n#define BITS_PKT_LIFTIME_VOVI_8197F                                            \\\n\t(BIT_MASK_PKT_LIFTIME_VOVI_8197F << BIT_SHIFT_PKT_LIFTIME_VOVI_8197F)\n#define BIT_CLEAR_PKT_LIFTIME_VOVI_8197F(x)                                    \\\n\t((x) & (~BITS_PKT_LIFTIME_VOVI_8197F))\n#define BIT_GET_PKT_LIFTIME_VOVI_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) &                           \\\n\t BIT_MASK_PKT_LIFTIME_VOVI_8197F)\n#define BIT_SET_PKT_LIFTIME_VOVI_8197F(x, v)                                   \\\n\t(BIT_CLEAR_PKT_LIFTIME_VOVI_8197F(x) | BIT_PKT_LIFTIME_VOVI_8197F(v))\n\n/* 2 REG_STBC_SETTING_8197F */\n\n#define BIT_SHIFT_CDEND_TXTIME_L_8197F 4\n#define BIT_MASK_CDEND_TXTIME_L_8197F 0xf\n#define BIT_CDEND_TXTIME_L_8197F(x)                                            \\\n\t(((x) & BIT_MASK_CDEND_TXTIME_L_8197F)                                 \\\n\t << BIT_SHIFT_CDEND_TXTIME_L_8197F)\n#define BITS_CDEND_TXTIME_L_8197F                                              \\\n\t(BIT_MASK_CDEND_TXTIME_L_8197F << BIT_SHIFT_CDEND_TXTIME_L_8197F)\n#define BIT_CLEAR_CDEND_TXTIME_L_8197F(x) ((x) & (~BITS_CDEND_TXTIME_L_8197F))\n#define BIT_GET_CDEND_TXTIME_L_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_CDEND_TXTIME_L_8197F) &                             \\\n\t BIT_MASK_CDEND_TXTIME_L_8197F)\n#define BIT_SET_CDEND_TXTIME_L_8197F(x, v)                                     \\\n\t(BIT_CLEAR_CDEND_TXTIME_L_8197F(x) | BIT_CDEND_TXTIME_L_8197F(v))\n\n#define BIT_SHIFT_NESS_8197F 2\n#define BIT_MASK_NESS_8197F 0x3\n#define BIT_NESS_8197F(x) (((x) & BIT_MASK_NESS_8197F) << BIT_SHIFT_NESS_8197F)\n#define BITS_NESS_8197F (BIT_MASK_NESS_8197F << BIT_SHIFT_NESS_8197F)\n#define BIT_CLEAR_NESS_8197F(x) ((x) & (~BITS_NESS_8197F))\n#define BIT_GET_NESS_8197F(x)                                                  \\\n\t(((x) >> BIT_SHIFT_NESS_8197F) & BIT_MASK_NESS_8197F)\n#define BIT_SET_NESS_8197F(x, v) (BIT_CLEAR_NESS_8197F(x) | BIT_NESS_8197F(v))\n\n#define BIT_SHIFT_STBC_CFEND_8197F 0\n#define BIT_MASK_STBC_CFEND_8197F 0x3\n#define BIT_STBC_CFEND_8197F(x)                                                \\\n\t(((x) & BIT_MASK_STBC_CFEND_8197F) << BIT_SHIFT_STBC_CFEND_8197F)\n#define BITS_STBC_CFEND_8197F                                                  \\\n\t(BIT_MASK_STBC_CFEND_8197F << BIT_SHIFT_STBC_CFEND_8197F)\n#define BIT_CLEAR_STBC_CFEND_8197F(x) ((x) & (~BITS_STBC_CFEND_8197F))\n#define BIT_GET_STBC_CFEND_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_STBC_CFEND_8197F) & BIT_MASK_STBC_CFEND_8197F)\n#define BIT_SET_STBC_CFEND_8197F(x, v)                                         \\\n\t(BIT_CLEAR_STBC_CFEND_8197F(x) | BIT_STBC_CFEND_8197F(v))\n\n/* 2 REG_STBC_SETTING2_8197F */\n\n#define BIT_SHIFT_CDEND_TXTIME_H_8197F 0\n#define BIT_MASK_CDEND_TXTIME_H_8197F 0x1f\n#define BIT_CDEND_TXTIME_H_8197F(x)                                            \\\n\t(((x) & BIT_MASK_CDEND_TXTIME_H_8197F)                                 \\\n\t << BIT_SHIFT_CDEND_TXTIME_H_8197F)\n#define BITS_CDEND_TXTIME_H_8197F                                              \\\n\t(BIT_MASK_CDEND_TXTIME_H_8197F << BIT_SHIFT_CDEND_TXTIME_H_8197F)\n#define BIT_CLEAR_CDEND_TXTIME_H_8197F(x) ((x) & (~BITS_CDEND_TXTIME_H_8197F))\n#define BIT_GET_CDEND_TXTIME_H_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_CDEND_TXTIME_H_8197F) &                             \\\n\t BIT_MASK_CDEND_TXTIME_H_8197F)\n#define BIT_SET_CDEND_TXTIME_H_8197F(x, v)                                     \\\n\t(BIT_CLEAR_CDEND_TXTIME_H_8197F(x) | BIT_CDEND_TXTIME_H_8197F(v))\n\n/* 2 REG_QUEUE_CTRL_8197F */\n#define BIT_PTA_EDCCA_EN_8197F BIT(5)\n#define BIT_PTA_WL_TX_EN_8197F BIT(4)\n#define BIT_R_USE_DATA_BW_8197F BIT(3)\n#define BIT_TRI_PKT_INT_MODE1_8197F BIT(2)\n#define BIT_TRI_PKT_INT_MODE0_8197F BIT(1)\n#define BIT_ACQ_MODE_SEL_8197F BIT(0)\n\n/* 2 REG_SINGLE_AMPDU_CTRL_8197F */\n#define BIT_EN_SINGLE_APMDU_8197F BIT(7)\n\n/* 2 REG_PROT_MODE_CTRL_8197F */\n\n#define BIT_SHIFT_RTS_MAX_AGG_NUM_8197F 24\n#define BIT_MASK_RTS_MAX_AGG_NUM_8197F 0x3f\n#define BIT_RTS_MAX_AGG_NUM_8197F(x)                                           \\\n\t(((x) & BIT_MASK_RTS_MAX_AGG_NUM_8197F)                                \\\n\t << BIT_SHIFT_RTS_MAX_AGG_NUM_8197F)\n#define BITS_RTS_MAX_AGG_NUM_8197F                                             \\\n\t(BIT_MASK_RTS_MAX_AGG_NUM_8197F << BIT_SHIFT_RTS_MAX_AGG_NUM_8197F)\n#define BIT_CLEAR_RTS_MAX_AGG_NUM_8197F(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8197F))\n#define BIT_GET_RTS_MAX_AGG_NUM_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) &                            \\\n\t BIT_MASK_RTS_MAX_AGG_NUM_8197F)\n#define BIT_SET_RTS_MAX_AGG_NUM_8197F(x, v)                                    \\\n\t(BIT_CLEAR_RTS_MAX_AGG_NUM_8197F(x) | BIT_RTS_MAX_AGG_NUM_8197F(v))\n\n#define BIT_SHIFT_MAX_AGG_NUM_8197F 16\n#define BIT_MASK_MAX_AGG_NUM_8197F 0x3f\n#define BIT_MAX_AGG_NUM_8197F(x)                                               \\\n\t(((x) & BIT_MASK_MAX_AGG_NUM_8197F) << BIT_SHIFT_MAX_AGG_NUM_8197F)\n#define BITS_MAX_AGG_NUM_8197F                                                 \\\n\t(BIT_MASK_MAX_AGG_NUM_8197F << BIT_SHIFT_MAX_AGG_NUM_8197F)\n#define BIT_CLEAR_MAX_AGG_NUM_8197F(x) ((x) & (~BITS_MAX_AGG_NUM_8197F))\n#define BIT_GET_MAX_AGG_NUM_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_MAX_AGG_NUM_8197F) & BIT_MASK_MAX_AGG_NUM_8197F)\n#define BIT_SET_MAX_AGG_NUM_8197F(x, v)                                        \\\n\t(BIT_CLEAR_MAX_AGG_NUM_8197F(x) | BIT_MAX_AGG_NUM_8197F(v))\n\n#define BIT_SHIFT_RTS_TXTIME_TH_8197F 8\n#define BIT_MASK_RTS_TXTIME_TH_8197F 0xff\n#define BIT_RTS_TXTIME_TH_8197F(x)                                             \\\n\t(((x) & BIT_MASK_RTS_TXTIME_TH_8197F) << BIT_SHIFT_RTS_TXTIME_TH_8197F)\n#define BITS_RTS_TXTIME_TH_8197F                                               \\\n\t(BIT_MASK_RTS_TXTIME_TH_8197F << BIT_SHIFT_RTS_TXTIME_TH_8197F)\n#define BIT_CLEAR_RTS_TXTIME_TH_8197F(x) ((x) & (~BITS_RTS_TXTIME_TH_8197F))\n#define BIT_GET_RTS_TXTIME_TH_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_RTS_TXTIME_TH_8197F) & BIT_MASK_RTS_TXTIME_TH_8197F)\n#define BIT_SET_RTS_TXTIME_TH_8197F(x, v)                                      \\\n\t(BIT_CLEAR_RTS_TXTIME_TH_8197F(x) | BIT_RTS_TXTIME_TH_8197F(v))\n\n#define BIT_SHIFT_RTS_LEN_TH_8197F 0\n#define BIT_MASK_RTS_LEN_TH_8197F 0xff\n#define BIT_RTS_LEN_TH_8197F(x)                                                \\\n\t(((x) & BIT_MASK_RTS_LEN_TH_8197F) << BIT_SHIFT_RTS_LEN_TH_8197F)\n#define BITS_RTS_LEN_TH_8197F                                                  \\\n\t(BIT_MASK_RTS_LEN_TH_8197F << BIT_SHIFT_RTS_LEN_TH_8197F)\n#define BIT_CLEAR_RTS_LEN_TH_8197F(x) ((x) & (~BITS_RTS_LEN_TH_8197F))\n#define BIT_GET_RTS_LEN_TH_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_RTS_LEN_TH_8197F) & BIT_MASK_RTS_LEN_TH_8197F)\n#define BIT_SET_RTS_LEN_TH_8197F(x, v)                                         \\\n\t(BIT_CLEAR_RTS_LEN_TH_8197F(x) | BIT_RTS_LEN_TH_8197F(v))\n\n/* 2 REG_BAR_MODE_CTRL_8197F */\n\n#define BIT_SHIFT_BAR_RTY_LMT_8197F 16\n#define BIT_MASK_BAR_RTY_LMT_8197F 0x3\n#define BIT_BAR_RTY_LMT_8197F(x)                                               \\\n\t(((x) & BIT_MASK_BAR_RTY_LMT_8197F) << BIT_SHIFT_BAR_RTY_LMT_8197F)\n#define BITS_BAR_RTY_LMT_8197F                                                 \\\n\t(BIT_MASK_BAR_RTY_LMT_8197F << BIT_SHIFT_BAR_RTY_LMT_8197F)\n#define BIT_CLEAR_BAR_RTY_LMT_8197F(x) ((x) & (~BITS_BAR_RTY_LMT_8197F))\n#define BIT_GET_BAR_RTY_LMT_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_BAR_RTY_LMT_8197F) & BIT_MASK_BAR_RTY_LMT_8197F)\n#define BIT_SET_BAR_RTY_LMT_8197F(x, v)                                        \\\n\t(BIT_CLEAR_BAR_RTY_LMT_8197F(x) | BIT_BAR_RTY_LMT_8197F(v))\n\n#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F 8\n#define BIT_MASK_BAR_PKT_TXTIME_TH_8197F 0xff\n#define BIT_BAR_PKT_TXTIME_TH_8197F(x)                                         \\\n\t(((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8197F)                              \\\n\t << BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F)\n#define BITS_BAR_PKT_TXTIME_TH_8197F                                           \\\n\t(BIT_MASK_BAR_PKT_TXTIME_TH_8197F << BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F)\n#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8197F(x)                                   \\\n\t((x) & (~BITS_BAR_PKT_TXTIME_TH_8197F))\n#define BIT_GET_BAR_PKT_TXTIME_TH_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) &                          \\\n\t BIT_MASK_BAR_PKT_TXTIME_TH_8197F)\n#define BIT_SET_BAR_PKT_TXTIME_TH_8197F(x, v)                                  \\\n\t(BIT_CLEAR_BAR_PKT_TXTIME_TH_8197F(x) | BIT_BAR_PKT_TXTIME_TH_8197F(v))\n\n#define BIT_BAR_EN_V1_8197F BIT(6)\n\n#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F 0\n#define BIT_MASK_BAR_PKTNUM_TH_V1_8197F 0x3f\n#define BIT_BAR_PKTNUM_TH_V1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8197F)                               \\\n\t << BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F)\n#define BITS_BAR_PKTNUM_TH_V1_8197F                                            \\\n\t(BIT_MASK_BAR_PKTNUM_TH_V1_8197F << BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F)\n#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8197F(x)                                    \\\n\t((x) & (~BITS_BAR_PKTNUM_TH_V1_8197F))\n#define BIT_GET_BAR_PKTNUM_TH_V1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) &                           \\\n\t BIT_MASK_BAR_PKTNUM_TH_V1_8197F)\n#define BIT_SET_BAR_PKTNUM_TH_V1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_BAR_PKTNUM_TH_V1_8197F(x) | BIT_BAR_PKTNUM_TH_V1_8197F(v))\n\n/* 2 REG_RA_TRY_RATE_AGG_LMT_8197F */\n\n#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F 0\n#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F 0x3f\n#define BIT_RA_TRY_RATE_AGG_LMT_V1_8197F(x)                                    \\\n\t(((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F)                         \\\n\t << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F)\n#define BITS_RA_TRY_RATE_AGG_LMT_V1_8197F                                      \\\n\t(BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F                                 \\\n\t << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F)\n#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8197F(x)                              \\\n\t((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8197F))\n#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8197F(x)                                \\\n\t(((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) &                     \\\n\t BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F)\n#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8197F(x, v)                             \\\n\t(BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8197F(x) |                           \\\n\t BIT_RA_TRY_RATE_AGG_LMT_V1_8197F(v))\n\n/* 2 REG_MACID_SLEEP2_8197F */\n\n#define BIT_SHIFT_MACID95_64PKTSLEEP_8197F 0\n#define BIT_MASK_MACID95_64PKTSLEEP_8197F 0xffffffffL\n#define BIT_MACID95_64PKTSLEEP_8197F(x)                                        \\\n\t(((x) & BIT_MASK_MACID95_64PKTSLEEP_8197F)                             \\\n\t << BIT_SHIFT_MACID95_64PKTSLEEP_8197F)\n#define BITS_MACID95_64PKTSLEEP_8197F                                          \\\n\t(BIT_MASK_MACID95_64PKTSLEEP_8197F                                     \\\n\t << BIT_SHIFT_MACID95_64PKTSLEEP_8197F)\n#define BIT_CLEAR_MACID95_64PKTSLEEP_8197F(x)                                  \\\n\t((x) & (~BITS_MACID95_64PKTSLEEP_8197F))\n#define BIT_GET_MACID95_64PKTSLEEP_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8197F) &                         \\\n\t BIT_MASK_MACID95_64PKTSLEEP_8197F)\n#define BIT_SET_MACID95_64PKTSLEEP_8197F(x, v)                                 \\\n\t(BIT_CLEAR_MACID95_64PKTSLEEP_8197F(x) |                               \\\n\t BIT_MACID95_64PKTSLEEP_8197F(v))\n\n/* 2 REG_MACID_SLEEP_8197F */\n\n#define BIT_SHIFT_MACID31_0_PKTSLEEP_8197F 0\n#define BIT_MASK_MACID31_0_PKTSLEEP_8197F 0xffffffffL\n#define BIT_MACID31_0_PKTSLEEP_8197F(x)                                        \\\n\t(((x) & BIT_MASK_MACID31_0_PKTSLEEP_8197F)                             \\\n\t << BIT_SHIFT_MACID31_0_PKTSLEEP_8197F)\n#define BITS_MACID31_0_PKTSLEEP_8197F                                          \\\n\t(BIT_MASK_MACID31_0_PKTSLEEP_8197F                                     \\\n\t << BIT_SHIFT_MACID31_0_PKTSLEEP_8197F)\n#define BIT_CLEAR_MACID31_0_PKTSLEEP_8197F(x)                                  \\\n\t((x) & (~BITS_MACID31_0_PKTSLEEP_8197F))\n#define BIT_GET_MACID31_0_PKTSLEEP_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) &                         \\\n\t BIT_MASK_MACID31_0_PKTSLEEP_8197F)\n#define BIT_SET_MACID31_0_PKTSLEEP_8197F(x, v)                                 \\\n\t(BIT_CLEAR_MACID31_0_PKTSLEEP_8197F(x) |                               \\\n\t BIT_MACID31_0_PKTSLEEP_8197F(v))\n\n/* 2 REG_HW_SEQ0_8197F */\n\n#define BIT_SHIFT_HW_SSN_SEQ0_8197F 0\n#define BIT_MASK_HW_SSN_SEQ0_8197F 0xfff\n#define BIT_HW_SSN_SEQ0_8197F(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ0_8197F) << BIT_SHIFT_HW_SSN_SEQ0_8197F)\n#define BITS_HW_SSN_SEQ0_8197F                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ0_8197F << BIT_SHIFT_HW_SSN_SEQ0_8197F)\n#define BIT_CLEAR_HW_SSN_SEQ0_8197F(x) ((x) & (~BITS_HW_SSN_SEQ0_8197F))\n#define BIT_GET_HW_SSN_SEQ0_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ0_8197F) & BIT_MASK_HW_SSN_SEQ0_8197F)\n#define BIT_SET_HW_SSN_SEQ0_8197F(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ0_8197F(x) | BIT_HW_SSN_SEQ0_8197F(v))\n\n/* 2 REG_HW_SEQ1_8197F */\n\n#define BIT_SHIFT_HW_SSN_SEQ1_8197F 0\n#define BIT_MASK_HW_SSN_SEQ1_8197F 0xfff\n#define BIT_HW_SSN_SEQ1_8197F(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ1_8197F) << BIT_SHIFT_HW_SSN_SEQ1_8197F)\n#define BITS_HW_SSN_SEQ1_8197F                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ1_8197F << BIT_SHIFT_HW_SSN_SEQ1_8197F)\n#define BIT_CLEAR_HW_SSN_SEQ1_8197F(x) ((x) & (~BITS_HW_SSN_SEQ1_8197F))\n#define BIT_GET_HW_SSN_SEQ1_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ1_8197F) & BIT_MASK_HW_SSN_SEQ1_8197F)\n#define BIT_SET_HW_SSN_SEQ1_8197F(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ1_8197F(x) | BIT_HW_SSN_SEQ1_8197F(v))\n\n/* 2 REG_HW_SEQ2_8197F */\n\n#define BIT_SHIFT_HW_SSN_SEQ2_8197F 0\n#define BIT_MASK_HW_SSN_SEQ2_8197F 0xfff\n#define BIT_HW_SSN_SEQ2_8197F(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ2_8197F) << BIT_SHIFT_HW_SSN_SEQ2_8197F)\n#define BITS_HW_SSN_SEQ2_8197F                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ2_8197F << BIT_SHIFT_HW_SSN_SEQ2_8197F)\n#define BIT_CLEAR_HW_SSN_SEQ2_8197F(x) ((x) & (~BITS_HW_SSN_SEQ2_8197F))\n#define BIT_GET_HW_SSN_SEQ2_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ2_8197F) & BIT_MASK_HW_SSN_SEQ2_8197F)\n#define BIT_SET_HW_SSN_SEQ2_8197F(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ2_8197F(x) | BIT_HW_SSN_SEQ2_8197F(v))\n\n/* 2 REG_HW_SEQ3_8197F */\n\n#define BIT_SHIFT_CSI_HWSSN_SEL_8197F 12\n#define BIT_MASK_CSI_HWSSN_SEL_8197F 0x3\n#define BIT_CSI_HWSSN_SEL_8197F(x)                                             \\\n\t(((x) & BIT_MASK_CSI_HWSSN_SEL_8197F) << BIT_SHIFT_CSI_HWSSN_SEL_8197F)\n#define BITS_CSI_HWSSN_SEL_8197F                                               \\\n\t(BIT_MASK_CSI_HWSSN_SEL_8197F << BIT_SHIFT_CSI_HWSSN_SEL_8197F)\n#define BIT_CLEAR_CSI_HWSSN_SEL_8197F(x) ((x) & (~BITS_CSI_HWSSN_SEL_8197F))\n#define BIT_GET_CSI_HWSSN_SEL_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_CSI_HWSSN_SEL_8197F) & BIT_MASK_CSI_HWSSN_SEL_8197F)\n#define BIT_SET_CSI_HWSSN_SEL_8197F(x, v)                                      \\\n\t(BIT_CLEAR_CSI_HWSSN_SEL_8197F(x) | BIT_CSI_HWSSN_SEL_8197F(v))\n\n#define BIT_SHIFT_HW_SSN_SEQ3_8197F 0\n#define BIT_MASK_HW_SSN_SEQ3_8197F 0xfff\n#define BIT_HW_SSN_SEQ3_8197F(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ3_8197F) << BIT_SHIFT_HW_SSN_SEQ3_8197F)\n#define BITS_HW_SSN_SEQ3_8197F                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ3_8197F << BIT_SHIFT_HW_SSN_SEQ3_8197F)\n#define BIT_CLEAR_HW_SSN_SEQ3_8197F(x) ((x) & (~BITS_HW_SSN_SEQ3_8197F))\n#define BIT_GET_HW_SSN_SEQ3_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ3_8197F) & BIT_MASK_HW_SSN_SEQ3_8197F)\n#define BIT_SET_HW_SSN_SEQ3_8197F(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ3_8197F(x) | BIT_HW_SSN_SEQ3_8197F(v))\n\n/* 2 REG_NULL_PKT_STATUS_V1_8197F */\n\n#define BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F 2\n#define BIT_MASK_PTCL_TOTAL_PG_V1_8197F 0x1fff\n#define BIT_PTCL_TOTAL_PG_V1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_PTCL_TOTAL_PG_V1_8197F)                               \\\n\t << BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F)\n#define BITS_PTCL_TOTAL_PG_V1_8197F                                            \\\n\t(BIT_MASK_PTCL_TOTAL_PG_V1_8197F << BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F)\n#define BIT_CLEAR_PTCL_TOTAL_PG_V1_8197F(x)                                    \\\n\t((x) & (~BITS_PTCL_TOTAL_PG_V1_8197F))\n#define BIT_GET_PTCL_TOTAL_PG_V1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) &                           \\\n\t BIT_MASK_PTCL_TOTAL_PG_V1_8197F)\n#define BIT_SET_PTCL_TOTAL_PG_V1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_PTCL_TOTAL_PG_V1_8197F(x) | BIT_PTCL_TOTAL_PG_V1_8197F(v))\n\n#define BIT_TX_NULL_1_8197F BIT(1)\n#define BIT_TX_NULL_0_8197F BIT(0)\n\n/* 2 REG_PTCL_ERR_STATUS_8197F */\n#define BIT_PTCL_RATE_TABLE_INVALID_8197F BIT(7)\n#define BIT_FTM_T2R_ERROR_8197F BIT(6)\n#define BIT_PTCL_ERR0_8197F BIT(5)\n#define BIT_PTCL_ERR1_8197F BIT(4)\n#define BIT_PTCL_ERR2_8197F BIT(3)\n#define BIT_PTCL_ERR3_8197F BIT(2)\n#define BIT_PTCL_ERR4_8197F BIT(1)\n#define BIT_PTCL_ERR5_8197F BIT(0)\n\n/* 2 REG_NULL_PKT_STATUS_EXTEND_8197F */\n#define BIT_CLI3_TX_NULL_1_8197F BIT(7)\n#define BIT_CLI3_TX_NULL_0_8197F BIT(6)\n#define BIT_CLI2_TX_NULL_1_8197F BIT(5)\n#define BIT_CLI2_TX_NULL_0_8197F BIT(4)\n#define BIT_CLI1_TX_NULL_1_8197F BIT(3)\n#define BIT_CLI1_TX_NULL_0_8197F BIT(2)\n#define BIT_CLI0_TX_NULL_1_8197F BIT(1)\n#define BIT_CLI0_TX_NULL_0_8197F BIT(0)\n\n/* 2 REG_VIDEO_ENHANCEMENT_FUN_8197F */\n#define BIT_VIDEO_JUST_DROP_8197F BIT(1)\n#define BIT_VIDEO_ENHANCEMENT_FUN_EN_8197F BIT(0)\n\n/* 2 REG_BT_POLLUTE_PKT_CNT_8197F */\n\n#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F 0\n#define BIT_MASK_BT_POLLUTE_PKT_CNT_8197F 0xffff\n#define BIT_BT_POLLUTE_PKT_CNT_8197F(x)                                        \\\n\t(((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8197F)                             \\\n\t << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F)\n#define BITS_BT_POLLUTE_PKT_CNT_8197F                                          \\\n\t(BIT_MASK_BT_POLLUTE_PKT_CNT_8197F                                     \\\n\t << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F)\n#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8197F(x)                                  \\\n\t((x) & (~BITS_BT_POLLUTE_PKT_CNT_8197F))\n#define BIT_GET_BT_POLLUTE_PKT_CNT_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) &                         \\\n\t BIT_MASK_BT_POLLUTE_PKT_CNT_8197F)\n#define BIT_SET_BT_POLLUTE_PKT_CNT_8197F(x, v)                                 \\\n\t(BIT_CLEAR_BT_POLLUTE_PKT_CNT_8197F(x) |                               \\\n\t BIT_BT_POLLUTE_PKT_CNT_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_PTCL_DBG_8197F */\n\n#define BIT_SHIFT_PTCL_DBG_8197F 0\n#define BIT_MASK_PTCL_DBG_8197F 0xffffffffL\n#define BIT_PTCL_DBG_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_PTCL_DBG_8197F) << BIT_SHIFT_PTCL_DBG_8197F)\n#define BITS_PTCL_DBG_8197F                                                    \\\n\t(BIT_MASK_PTCL_DBG_8197F << BIT_SHIFT_PTCL_DBG_8197F)\n#define BIT_CLEAR_PTCL_DBG_8197F(x) ((x) & (~BITS_PTCL_DBG_8197F))\n#define BIT_GET_PTCL_DBG_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_PTCL_DBG_8197F) & BIT_MASK_PTCL_DBG_8197F)\n#define BIT_SET_PTCL_DBG_8197F(x, v)                                           \\\n\t(BIT_CLEAR_PTCL_DBG_8197F(x) | BIT_PTCL_DBG_8197F(v))\n\n/* 2 REG_TXOP_EXTRA_CTRL_8197F */\n#define BIT_TXOP_EFFICIENCY_EN_8197F BIT(0)\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_CPUMGQ_TIMER_CTRL2_8197F */\n\n#define BIT_SHIFT_TRI_HEAD_ADDR_8197F 16\n#define BIT_MASK_TRI_HEAD_ADDR_8197F 0xfff\n#define BIT_TRI_HEAD_ADDR_8197F(x)                                             \\\n\t(((x) & BIT_MASK_TRI_HEAD_ADDR_8197F) << BIT_SHIFT_TRI_HEAD_ADDR_8197F)\n#define BITS_TRI_HEAD_ADDR_8197F                                               \\\n\t(BIT_MASK_TRI_HEAD_ADDR_8197F << BIT_SHIFT_TRI_HEAD_ADDR_8197F)\n#define BIT_CLEAR_TRI_HEAD_ADDR_8197F(x) ((x) & (~BITS_TRI_HEAD_ADDR_8197F))\n#define BIT_GET_TRI_HEAD_ADDR_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8197F) & BIT_MASK_TRI_HEAD_ADDR_8197F)\n#define BIT_SET_TRI_HEAD_ADDR_8197F(x, v)                                      \\\n\t(BIT_CLEAR_TRI_HEAD_ADDR_8197F(x) | BIT_TRI_HEAD_ADDR_8197F(v))\n\n#define BIT_DROP_TH_EN_8197F BIT(8)\n\n#define BIT_SHIFT_DROP_TH_8197F 0\n#define BIT_MASK_DROP_TH_8197F 0xff\n#define BIT_DROP_TH_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_DROP_TH_8197F) << BIT_SHIFT_DROP_TH_8197F)\n#define BITS_DROP_TH_8197F (BIT_MASK_DROP_TH_8197F << BIT_SHIFT_DROP_TH_8197F)\n#define BIT_CLEAR_DROP_TH_8197F(x) ((x) & (~BITS_DROP_TH_8197F))\n#define BIT_GET_DROP_TH_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_DROP_TH_8197F) & BIT_MASK_DROP_TH_8197F)\n#define BIT_SET_DROP_TH_8197F(x, v)                                            \\\n\t(BIT_CLEAR_DROP_TH_8197F(x) | BIT_DROP_TH_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_DUMMY_PAGE4_8197F */\n#define BIT_MOREDATA_CTRL2_EN_V2_8197F BIT(19)\n#define BIT_MOREDATA_CTRL1_EN_V2_8197F BIT(18)\n#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_8197F BIT(16)\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_Q0_Q1_INFO_8197F */\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31)\n\n#define BIT_SHIFT_GTAB_ID_8197F 28\n#define BIT_MASK_GTAB_ID_8197F 0x7\n#define BIT_GTAB_ID_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F)\n#define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F)\n#define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F))\n#define BIT_GET_GTAB_ID_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F)\n#define BIT_SET_GTAB_ID_8197F(x, v)                                            \\\n\t(BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v))\n\n#define BIT_SHIFT_AC1_PKT_INFO_8197F 16\n#define BIT_MASK_AC1_PKT_INFO_8197F 0xfff\n#define BIT_AC1_PKT_INFO_8197F(x)                                              \\\n\t(((x) & BIT_MASK_AC1_PKT_INFO_8197F) << BIT_SHIFT_AC1_PKT_INFO_8197F)\n#define BITS_AC1_PKT_INFO_8197F                                                \\\n\t(BIT_MASK_AC1_PKT_INFO_8197F << BIT_SHIFT_AC1_PKT_INFO_8197F)\n#define BIT_CLEAR_AC1_PKT_INFO_8197F(x) ((x) & (~BITS_AC1_PKT_INFO_8197F))\n#define BIT_GET_AC1_PKT_INFO_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC1_PKT_INFO_8197F) & BIT_MASK_AC1_PKT_INFO_8197F)\n#define BIT_SET_AC1_PKT_INFO_8197F(x, v)                                       \\\n\t(BIT_CLEAR_AC1_PKT_INFO_8197F(x) | BIT_AC1_PKT_INFO_8197F(v))\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15)\n\n#define BIT_SHIFT_GTAB_ID_V1_8197F 12\n#define BIT_MASK_GTAB_ID_V1_8197F 0x7\n#define BIT_GTAB_ID_V1_8197F(x)                                                \\\n\t(((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F)\n#define BITS_GTAB_ID_V1_8197F                                                  \\\n\t(BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F)\n#define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F))\n#define BIT_GET_GTAB_ID_V1_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F)\n#define BIT_SET_GTAB_ID_V1_8197F(x, v)                                         \\\n\t(BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v))\n\n#define BIT_SHIFT_AC0_PKT_INFO_8197F 0\n#define BIT_MASK_AC0_PKT_INFO_8197F 0xfff\n#define BIT_AC0_PKT_INFO_8197F(x)                                              \\\n\t(((x) & BIT_MASK_AC0_PKT_INFO_8197F) << BIT_SHIFT_AC0_PKT_INFO_8197F)\n#define BITS_AC0_PKT_INFO_8197F                                                \\\n\t(BIT_MASK_AC0_PKT_INFO_8197F << BIT_SHIFT_AC0_PKT_INFO_8197F)\n#define BIT_CLEAR_AC0_PKT_INFO_8197F(x) ((x) & (~BITS_AC0_PKT_INFO_8197F))\n#define BIT_GET_AC0_PKT_INFO_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC0_PKT_INFO_8197F) & BIT_MASK_AC0_PKT_INFO_8197F)\n#define BIT_SET_AC0_PKT_INFO_8197F(x, v)                                       \\\n\t(BIT_CLEAR_AC0_PKT_INFO_8197F(x) | BIT_AC0_PKT_INFO_8197F(v))\n\n/* 2 REG_Q2_Q3_INFO_8197F */\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31)\n\n#define BIT_SHIFT_GTAB_ID_8197F 28\n#define BIT_MASK_GTAB_ID_8197F 0x7\n#define BIT_GTAB_ID_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F)\n#define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F)\n#define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F))\n#define BIT_GET_GTAB_ID_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F)\n#define BIT_SET_GTAB_ID_8197F(x, v)                                            \\\n\t(BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v))\n\n#define BIT_SHIFT_AC3_PKT_INFO_8197F 16\n#define BIT_MASK_AC3_PKT_INFO_8197F 0xfff\n#define BIT_AC3_PKT_INFO_8197F(x)                                              \\\n\t(((x) & BIT_MASK_AC3_PKT_INFO_8197F) << BIT_SHIFT_AC3_PKT_INFO_8197F)\n#define BITS_AC3_PKT_INFO_8197F                                                \\\n\t(BIT_MASK_AC3_PKT_INFO_8197F << BIT_SHIFT_AC3_PKT_INFO_8197F)\n#define BIT_CLEAR_AC3_PKT_INFO_8197F(x) ((x) & (~BITS_AC3_PKT_INFO_8197F))\n#define BIT_GET_AC3_PKT_INFO_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC3_PKT_INFO_8197F) & BIT_MASK_AC3_PKT_INFO_8197F)\n#define BIT_SET_AC3_PKT_INFO_8197F(x, v)                                       \\\n\t(BIT_CLEAR_AC3_PKT_INFO_8197F(x) | BIT_AC3_PKT_INFO_8197F(v))\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15)\n\n#define BIT_SHIFT_GTAB_ID_V1_8197F 12\n#define BIT_MASK_GTAB_ID_V1_8197F 0x7\n#define BIT_GTAB_ID_V1_8197F(x)                                                \\\n\t(((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F)\n#define BITS_GTAB_ID_V1_8197F                                                  \\\n\t(BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F)\n#define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F))\n#define BIT_GET_GTAB_ID_V1_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F)\n#define BIT_SET_GTAB_ID_V1_8197F(x, v)                                         \\\n\t(BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v))\n\n#define BIT_SHIFT_AC2_PKT_INFO_8197F 0\n#define BIT_MASK_AC2_PKT_INFO_8197F 0xfff\n#define BIT_AC2_PKT_INFO_8197F(x)                                              \\\n\t(((x) & BIT_MASK_AC2_PKT_INFO_8197F) << BIT_SHIFT_AC2_PKT_INFO_8197F)\n#define BITS_AC2_PKT_INFO_8197F                                                \\\n\t(BIT_MASK_AC2_PKT_INFO_8197F << BIT_SHIFT_AC2_PKT_INFO_8197F)\n#define BIT_CLEAR_AC2_PKT_INFO_8197F(x) ((x) & (~BITS_AC2_PKT_INFO_8197F))\n#define BIT_GET_AC2_PKT_INFO_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC2_PKT_INFO_8197F) & BIT_MASK_AC2_PKT_INFO_8197F)\n#define BIT_SET_AC2_PKT_INFO_8197F(x, v)                                       \\\n\t(BIT_CLEAR_AC2_PKT_INFO_8197F(x) | BIT_AC2_PKT_INFO_8197F(v))\n\n/* 2 REG_Q4_Q5_INFO_8197F */\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31)\n\n#define BIT_SHIFT_GTAB_ID_8197F 28\n#define BIT_MASK_GTAB_ID_8197F 0x7\n#define BIT_GTAB_ID_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F)\n#define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F)\n#define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F))\n#define BIT_GET_GTAB_ID_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F)\n#define BIT_SET_GTAB_ID_8197F(x, v)                                            \\\n\t(BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v))\n\n#define BIT_SHIFT_AC5_PKT_INFO_8197F 16\n#define BIT_MASK_AC5_PKT_INFO_8197F 0xfff\n#define BIT_AC5_PKT_INFO_8197F(x)                                              \\\n\t(((x) & BIT_MASK_AC5_PKT_INFO_8197F) << BIT_SHIFT_AC5_PKT_INFO_8197F)\n#define BITS_AC5_PKT_INFO_8197F                                                \\\n\t(BIT_MASK_AC5_PKT_INFO_8197F << BIT_SHIFT_AC5_PKT_INFO_8197F)\n#define BIT_CLEAR_AC5_PKT_INFO_8197F(x) ((x) & (~BITS_AC5_PKT_INFO_8197F))\n#define BIT_GET_AC5_PKT_INFO_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC5_PKT_INFO_8197F) & BIT_MASK_AC5_PKT_INFO_8197F)\n#define BIT_SET_AC5_PKT_INFO_8197F(x, v)                                       \\\n\t(BIT_CLEAR_AC5_PKT_INFO_8197F(x) | BIT_AC5_PKT_INFO_8197F(v))\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15)\n\n#define BIT_SHIFT_GTAB_ID_V1_8197F 12\n#define BIT_MASK_GTAB_ID_V1_8197F 0x7\n#define BIT_GTAB_ID_V1_8197F(x)                                                \\\n\t(((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F)\n#define BITS_GTAB_ID_V1_8197F                                                  \\\n\t(BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F)\n#define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F))\n#define BIT_GET_GTAB_ID_V1_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F)\n#define BIT_SET_GTAB_ID_V1_8197F(x, v)                                         \\\n\t(BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v))\n\n#define BIT_SHIFT_AC4_PKT_INFO_8197F 0\n#define BIT_MASK_AC4_PKT_INFO_8197F 0xfff\n#define BIT_AC4_PKT_INFO_8197F(x)                                              \\\n\t(((x) & BIT_MASK_AC4_PKT_INFO_8197F) << BIT_SHIFT_AC4_PKT_INFO_8197F)\n#define BITS_AC4_PKT_INFO_8197F                                                \\\n\t(BIT_MASK_AC4_PKT_INFO_8197F << BIT_SHIFT_AC4_PKT_INFO_8197F)\n#define BIT_CLEAR_AC4_PKT_INFO_8197F(x) ((x) & (~BITS_AC4_PKT_INFO_8197F))\n#define BIT_GET_AC4_PKT_INFO_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC4_PKT_INFO_8197F) & BIT_MASK_AC4_PKT_INFO_8197F)\n#define BIT_SET_AC4_PKT_INFO_8197F(x, v)                                       \\\n\t(BIT_CLEAR_AC4_PKT_INFO_8197F(x) | BIT_AC4_PKT_INFO_8197F(v))\n\n/* 2 REG_Q6_Q7_INFO_8197F */\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31)\n\n#define BIT_SHIFT_GTAB_ID_8197F 28\n#define BIT_MASK_GTAB_ID_8197F 0x7\n#define BIT_GTAB_ID_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F)\n#define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F)\n#define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F))\n#define BIT_GET_GTAB_ID_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F)\n#define BIT_SET_GTAB_ID_8197F(x, v)                                            \\\n\t(BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v))\n\n#define BIT_SHIFT_AC7_PKT_INFO_8197F 16\n#define BIT_MASK_AC7_PKT_INFO_8197F 0xfff\n#define BIT_AC7_PKT_INFO_8197F(x)                                              \\\n\t(((x) & BIT_MASK_AC7_PKT_INFO_8197F) << BIT_SHIFT_AC7_PKT_INFO_8197F)\n#define BITS_AC7_PKT_INFO_8197F                                                \\\n\t(BIT_MASK_AC7_PKT_INFO_8197F << BIT_SHIFT_AC7_PKT_INFO_8197F)\n#define BIT_CLEAR_AC7_PKT_INFO_8197F(x) ((x) & (~BITS_AC7_PKT_INFO_8197F))\n#define BIT_GET_AC7_PKT_INFO_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC7_PKT_INFO_8197F) & BIT_MASK_AC7_PKT_INFO_8197F)\n#define BIT_SET_AC7_PKT_INFO_8197F(x, v)                                       \\\n\t(BIT_CLEAR_AC7_PKT_INFO_8197F(x) | BIT_AC7_PKT_INFO_8197F(v))\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15)\n\n#define BIT_SHIFT_GTAB_ID_V1_8197F 12\n#define BIT_MASK_GTAB_ID_V1_8197F 0x7\n#define BIT_GTAB_ID_V1_8197F(x)                                                \\\n\t(((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F)\n#define BITS_GTAB_ID_V1_8197F                                                  \\\n\t(BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F)\n#define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F))\n#define BIT_GET_GTAB_ID_V1_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F)\n#define BIT_SET_GTAB_ID_V1_8197F(x, v)                                         \\\n\t(BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v))\n\n#define BIT_SHIFT_AC6_PKT_INFO_8197F 0\n#define BIT_MASK_AC6_PKT_INFO_8197F 0xfff\n#define BIT_AC6_PKT_INFO_8197F(x)                                              \\\n\t(((x) & BIT_MASK_AC6_PKT_INFO_8197F) << BIT_SHIFT_AC6_PKT_INFO_8197F)\n#define BITS_AC6_PKT_INFO_8197F                                                \\\n\t(BIT_MASK_AC6_PKT_INFO_8197F << BIT_SHIFT_AC6_PKT_INFO_8197F)\n#define BIT_CLEAR_AC6_PKT_INFO_8197F(x) ((x) & (~BITS_AC6_PKT_INFO_8197F))\n#define BIT_GET_AC6_PKT_INFO_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC6_PKT_INFO_8197F) & BIT_MASK_AC6_PKT_INFO_8197F)\n#define BIT_SET_AC6_PKT_INFO_8197F(x, v)                                       \\\n\t(BIT_CLEAR_AC6_PKT_INFO_8197F(x) | BIT_AC6_PKT_INFO_8197F(v))\n\n/* 2 REG_MGQ_HIQ_INFO_8197F */\n\n#define BIT_SHIFT_HIQ_PKT_INFO_8197F 16\n#define BIT_MASK_HIQ_PKT_INFO_8197F 0xfff\n#define BIT_HIQ_PKT_INFO_8197F(x)                                              \\\n\t(((x) & BIT_MASK_HIQ_PKT_INFO_8197F) << BIT_SHIFT_HIQ_PKT_INFO_8197F)\n#define BITS_HIQ_PKT_INFO_8197F                                                \\\n\t(BIT_MASK_HIQ_PKT_INFO_8197F << BIT_SHIFT_HIQ_PKT_INFO_8197F)\n#define BIT_CLEAR_HIQ_PKT_INFO_8197F(x) ((x) & (~BITS_HIQ_PKT_INFO_8197F))\n#define BIT_GET_HIQ_PKT_INFO_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_HIQ_PKT_INFO_8197F) & BIT_MASK_HIQ_PKT_INFO_8197F)\n#define BIT_SET_HIQ_PKT_INFO_8197F(x, v)                                       \\\n\t(BIT_CLEAR_HIQ_PKT_INFO_8197F(x) | BIT_HIQ_PKT_INFO_8197F(v))\n\n#define BIT_SHIFT_MGQ_PKT_INFO_8197F 0\n#define BIT_MASK_MGQ_PKT_INFO_8197F 0xfff\n#define BIT_MGQ_PKT_INFO_8197F(x)                                              \\\n\t(((x) & BIT_MASK_MGQ_PKT_INFO_8197F) << BIT_SHIFT_MGQ_PKT_INFO_8197F)\n#define BITS_MGQ_PKT_INFO_8197F                                                \\\n\t(BIT_MASK_MGQ_PKT_INFO_8197F << BIT_SHIFT_MGQ_PKT_INFO_8197F)\n#define BIT_CLEAR_MGQ_PKT_INFO_8197F(x) ((x) & (~BITS_MGQ_PKT_INFO_8197F))\n#define BIT_GET_MGQ_PKT_INFO_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_MGQ_PKT_INFO_8197F) & BIT_MASK_MGQ_PKT_INFO_8197F)\n#define BIT_SET_MGQ_PKT_INFO_8197F(x, v)                                       \\\n\t(BIT_CLEAR_MGQ_PKT_INFO_8197F(x) | BIT_MGQ_PKT_INFO_8197F(v))\n\n/* 2 REG_CMDQ_BCNQ_INFO_8197F */\n\n#define BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F 16\n#define BIT_MASK_BCNQ_PKT_INFO_V1_8197F 0xfff\n#define BIT_BCNQ_PKT_INFO_V1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_BCNQ_PKT_INFO_V1_8197F)                               \\\n\t << BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F)\n#define BITS_BCNQ_PKT_INFO_V1_8197F                                            \\\n\t(BIT_MASK_BCNQ_PKT_INFO_V1_8197F << BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F)\n#define BIT_CLEAR_BCNQ_PKT_INFO_V1_8197F(x)                                    \\\n\t((x) & (~BITS_BCNQ_PKT_INFO_V1_8197F))\n#define BIT_GET_BCNQ_PKT_INFO_V1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) &                           \\\n\t BIT_MASK_BCNQ_PKT_INFO_V1_8197F)\n#define BIT_SET_BCNQ_PKT_INFO_V1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_BCNQ_PKT_INFO_V1_8197F(x) | BIT_BCNQ_PKT_INFO_V1_8197F(v))\n\n#define BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F 0\n#define BIT_MASK_CMDQ_PKT_INFO_V1_8197F 0xfff\n#define BIT_CMDQ_PKT_INFO_V1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_CMDQ_PKT_INFO_V1_8197F)                               \\\n\t << BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F)\n#define BITS_CMDQ_PKT_INFO_V1_8197F                                            \\\n\t(BIT_MASK_CMDQ_PKT_INFO_V1_8197F << BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F)\n#define BIT_CLEAR_CMDQ_PKT_INFO_V1_8197F(x)                                    \\\n\t((x) & (~BITS_CMDQ_PKT_INFO_V1_8197F))\n#define BIT_GET_CMDQ_PKT_INFO_V1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) &                           \\\n\t BIT_MASK_CMDQ_PKT_INFO_V1_8197F)\n#define BIT_SET_CMDQ_PKT_INFO_V1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_CMDQ_PKT_INFO_V1_8197F(x) | BIT_CMDQ_PKT_INFO_V1_8197F(v))\n\n/* 2 REG_USEREG_SETTING_8197F */\n#define BIT_NDPA_USEREG_8197F BIT(21)\n\n#define BIT_SHIFT_RETRY_USEREG_8197F 19\n#define BIT_MASK_RETRY_USEREG_8197F 0x3\n#define BIT_RETRY_USEREG_8197F(x)                                              \\\n\t(((x) & BIT_MASK_RETRY_USEREG_8197F) << BIT_SHIFT_RETRY_USEREG_8197F)\n#define BITS_RETRY_USEREG_8197F                                                \\\n\t(BIT_MASK_RETRY_USEREG_8197F << BIT_SHIFT_RETRY_USEREG_8197F)\n#define BIT_CLEAR_RETRY_USEREG_8197F(x) ((x) & (~BITS_RETRY_USEREG_8197F))\n#define BIT_GET_RETRY_USEREG_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_RETRY_USEREG_8197F) & BIT_MASK_RETRY_USEREG_8197F)\n#define BIT_SET_RETRY_USEREG_8197F(x, v)                                       \\\n\t(BIT_CLEAR_RETRY_USEREG_8197F(x) | BIT_RETRY_USEREG_8197F(v))\n\n#define BIT_SHIFT_TRYPKT_USEREG_8197F 17\n#define BIT_MASK_TRYPKT_USEREG_8197F 0x3\n#define BIT_TRYPKT_USEREG_8197F(x)                                             \\\n\t(((x) & BIT_MASK_TRYPKT_USEREG_8197F) << BIT_SHIFT_TRYPKT_USEREG_8197F)\n#define BITS_TRYPKT_USEREG_8197F                                               \\\n\t(BIT_MASK_TRYPKT_USEREG_8197F << BIT_SHIFT_TRYPKT_USEREG_8197F)\n#define BIT_CLEAR_TRYPKT_USEREG_8197F(x) ((x) & (~BITS_TRYPKT_USEREG_8197F))\n#define BIT_GET_TRYPKT_USEREG_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_TRYPKT_USEREG_8197F) & BIT_MASK_TRYPKT_USEREG_8197F)\n#define BIT_SET_TRYPKT_USEREG_8197F(x, v)                                      \\\n\t(BIT_CLEAR_TRYPKT_USEREG_8197F(x) | BIT_TRYPKT_USEREG_8197F(v))\n\n#define BIT_CTLPKT_USEREG_8197F BIT(16)\n\n/* 2 REG_AESIV_SETTING_8197F */\n\n#define BIT_SHIFT_AESIV_OFFSET_8197F 0\n#define BIT_MASK_AESIV_OFFSET_8197F 0xfff\n#define BIT_AESIV_OFFSET_8197F(x)                                              \\\n\t(((x) & BIT_MASK_AESIV_OFFSET_8197F) << BIT_SHIFT_AESIV_OFFSET_8197F)\n#define BITS_AESIV_OFFSET_8197F                                                \\\n\t(BIT_MASK_AESIV_OFFSET_8197F << BIT_SHIFT_AESIV_OFFSET_8197F)\n#define BIT_CLEAR_AESIV_OFFSET_8197F(x) ((x) & (~BITS_AESIV_OFFSET_8197F))\n#define BIT_GET_AESIV_OFFSET_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_AESIV_OFFSET_8197F) & BIT_MASK_AESIV_OFFSET_8197F)\n#define BIT_SET_AESIV_OFFSET_8197F(x, v)                                       \\\n\t(BIT_CLEAR_AESIV_OFFSET_8197F(x) | BIT_AESIV_OFFSET_8197F(v))\n\n/* 2 REG_BF0_TIME_SETTING_8197F */\n#define BIT_BF0_TIMER_SET_8197F BIT(31)\n#define BIT_BF0_TIMER_CLR_8197F BIT(30)\n#define BIT_BF0_UPDATE_EN_8197F BIT(29)\n#define BIT_BF0_TIMER_EN_8197F BIT(28)\n\n#define BIT_SHIFT_BF0_PRETIME_OVER_8197F 16\n#define BIT_MASK_BF0_PRETIME_OVER_8197F 0xfff\n#define BIT_BF0_PRETIME_OVER_8197F(x)                                          \\\n\t(((x) & BIT_MASK_BF0_PRETIME_OVER_8197F)                               \\\n\t << BIT_SHIFT_BF0_PRETIME_OVER_8197F)\n#define BITS_BF0_PRETIME_OVER_8197F                                            \\\n\t(BIT_MASK_BF0_PRETIME_OVER_8197F << BIT_SHIFT_BF0_PRETIME_OVER_8197F)\n#define BIT_CLEAR_BF0_PRETIME_OVER_8197F(x)                                    \\\n\t((x) & (~BITS_BF0_PRETIME_OVER_8197F))\n#define BIT_GET_BF0_PRETIME_OVER_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8197F) &                           \\\n\t BIT_MASK_BF0_PRETIME_OVER_8197F)\n#define BIT_SET_BF0_PRETIME_OVER_8197F(x, v)                                   \\\n\t(BIT_CLEAR_BF0_PRETIME_OVER_8197F(x) | BIT_BF0_PRETIME_OVER_8197F(v))\n\n#define BIT_SHIFT_BF0_LIFETIME_8197F 0\n#define BIT_MASK_BF0_LIFETIME_8197F 0xffff\n#define BIT_BF0_LIFETIME_8197F(x)                                              \\\n\t(((x) & BIT_MASK_BF0_LIFETIME_8197F) << BIT_SHIFT_BF0_LIFETIME_8197F)\n#define BITS_BF0_LIFETIME_8197F                                                \\\n\t(BIT_MASK_BF0_LIFETIME_8197F << BIT_SHIFT_BF0_LIFETIME_8197F)\n#define BIT_CLEAR_BF0_LIFETIME_8197F(x) ((x) & (~BITS_BF0_LIFETIME_8197F))\n#define BIT_GET_BF0_LIFETIME_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_BF0_LIFETIME_8197F) & BIT_MASK_BF0_LIFETIME_8197F)\n#define BIT_SET_BF0_LIFETIME_8197F(x, v)                                       \\\n\t(BIT_CLEAR_BF0_LIFETIME_8197F(x) | BIT_BF0_LIFETIME_8197F(v))\n\n/* 2 REG_BF1_TIME_SETTING_8197F */\n#define BIT_BF1_TIMER_SET_8197F BIT(31)\n#define BIT_BF1_TIMER_CLR_8197F BIT(30)\n#define BIT_BF1_UPDATE_EN_8197F BIT(29)\n#define BIT_BF1_TIMER_EN_8197F BIT(28)\n\n#define BIT_SHIFT_BF1_PRETIME_OVER_8197F 16\n#define BIT_MASK_BF1_PRETIME_OVER_8197F 0xfff\n#define BIT_BF1_PRETIME_OVER_8197F(x)                                          \\\n\t(((x) & BIT_MASK_BF1_PRETIME_OVER_8197F)                               \\\n\t << BIT_SHIFT_BF1_PRETIME_OVER_8197F)\n#define BITS_BF1_PRETIME_OVER_8197F                                            \\\n\t(BIT_MASK_BF1_PRETIME_OVER_8197F << BIT_SHIFT_BF1_PRETIME_OVER_8197F)\n#define BIT_CLEAR_BF1_PRETIME_OVER_8197F(x)                                    \\\n\t((x) & (~BITS_BF1_PRETIME_OVER_8197F))\n#define BIT_GET_BF1_PRETIME_OVER_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8197F) &                           \\\n\t BIT_MASK_BF1_PRETIME_OVER_8197F)\n#define BIT_SET_BF1_PRETIME_OVER_8197F(x, v)                                   \\\n\t(BIT_CLEAR_BF1_PRETIME_OVER_8197F(x) | BIT_BF1_PRETIME_OVER_8197F(v))\n\n#define BIT_SHIFT_BF1_LIFETIME_8197F 0\n#define BIT_MASK_BF1_LIFETIME_8197F 0xffff\n#define BIT_BF1_LIFETIME_8197F(x)                                              \\\n\t(((x) & BIT_MASK_BF1_LIFETIME_8197F) << BIT_SHIFT_BF1_LIFETIME_8197F)\n#define BITS_BF1_LIFETIME_8197F                                                \\\n\t(BIT_MASK_BF1_LIFETIME_8197F << BIT_SHIFT_BF1_LIFETIME_8197F)\n#define BIT_CLEAR_BF1_LIFETIME_8197F(x) ((x) & (~BITS_BF1_LIFETIME_8197F))\n#define BIT_GET_BF1_LIFETIME_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_BF1_LIFETIME_8197F) & BIT_MASK_BF1_LIFETIME_8197F)\n#define BIT_SET_BF1_LIFETIME_8197F(x, v)                                       \\\n\t(BIT_CLEAR_BF1_LIFETIME_8197F(x) | BIT_BF1_LIFETIME_8197F(v))\n\n/* 2 REG_BF_TIMEOUT_EN_8197F */\n#define BIT_EN_VHT_LDPC_8197F BIT(9)\n#define BIT_EN_HT_LDPC_8197F BIT(8)\n#define BIT_BF1_TIMEOUT_EN_8197F BIT(1)\n#define BIT_BF0_TIMEOUT_EN_8197F BIT(0)\n\n/* 2 REG_MACID_RELEASE0_8197F */\n\n#define BIT_SHIFT_MACID31_0_RELEASE_8197F 0\n#define BIT_MASK_MACID31_0_RELEASE_8197F 0xffffffffL\n#define BIT_MACID31_0_RELEASE_8197F(x)                                         \\\n\t(((x) & BIT_MASK_MACID31_0_RELEASE_8197F)                              \\\n\t << BIT_SHIFT_MACID31_0_RELEASE_8197F)\n#define BITS_MACID31_0_RELEASE_8197F                                           \\\n\t(BIT_MASK_MACID31_0_RELEASE_8197F << BIT_SHIFT_MACID31_0_RELEASE_8197F)\n#define BIT_CLEAR_MACID31_0_RELEASE_8197F(x)                                   \\\n\t((x) & (~BITS_MACID31_0_RELEASE_8197F))\n#define BIT_GET_MACID31_0_RELEASE_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_MACID31_0_RELEASE_8197F) &                          \\\n\t BIT_MASK_MACID31_0_RELEASE_8197F)\n#define BIT_SET_MACID31_0_RELEASE_8197F(x, v)                                  \\\n\t(BIT_CLEAR_MACID31_0_RELEASE_8197F(x) | BIT_MACID31_0_RELEASE_8197F(v))\n\n/* 2 REG_MACID_RELEASE1_8197F */\n\n#define BIT_SHIFT_MACID63_32_RELEASE_8197F 0\n#define BIT_MASK_MACID63_32_RELEASE_8197F 0xffffffffL\n#define BIT_MACID63_32_RELEASE_8197F(x)                                        \\\n\t(((x) & BIT_MASK_MACID63_32_RELEASE_8197F)                             \\\n\t << BIT_SHIFT_MACID63_32_RELEASE_8197F)\n#define BITS_MACID63_32_RELEASE_8197F                                          \\\n\t(BIT_MASK_MACID63_32_RELEASE_8197F                                     \\\n\t << BIT_SHIFT_MACID63_32_RELEASE_8197F)\n#define BIT_CLEAR_MACID63_32_RELEASE_8197F(x)                                  \\\n\t((x) & (~BITS_MACID63_32_RELEASE_8197F))\n#define BIT_GET_MACID63_32_RELEASE_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACID63_32_RELEASE_8197F) &                         \\\n\t BIT_MASK_MACID63_32_RELEASE_8197F)\n#define BIT_SET_MACID63_32_RELEASE_8197F(x, v)                                 \\\n\t(BIT_CLEAR_MACID63_32_RELEASE_8197F(x) |                               \\\n\t BIT_MACID63_32_RELEASE_8197F(v))\n\n/* 2 REG_MACID_RELEASE2_8197F */\n\n#define BIT_SHIFT_MACID95_64_RELEASE_8197F 0\n#define BIT_MASK_MACID95_64_RELEASE_8197F 0xffffffffL\n#define BIT_MACID95_64_RELEASE_8197F(x)                                        \\\n\t(((x) & BIT_MASK_MACID95_64_RELEASE_8197F)                             \\\n\t << BIT_SHIFT_MACID95_64_RELEASE_8197F)\n#define BITS_MACID95_64_RELEASE_8197F                                          \\\n\t(BIT_MASK_MACID95_64_RELEASE_8197F                                     \\\n\t << BIT_SHIFT_MACID95_64_RELEASE_8197F)\n#define BIT_CLEAR_MACID95_64_RELEASE_8197F(x)                                  \\\n\t((x) & (~BITS_MACID95_64_RELEASE_8197F))\n#define BIT_GET_MACID95_64_RELEASE_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACID95_64_RELEASE_8197F) &                         \\\n\t BIT_MASK_MACID95_64_RELEASE_8197F)\n#define BIT_SET_MACID95_64_RELEASE_8197F(x, v)                                 \\\n\t(BIT_CLEAR_MACID95_64_RELEASE_8197F(x) |                               \\\n\t BIT_MACID95_64_RELEASE_8197F(v))\n\n/* 2 REG_MACID_RELEASE3_8197F */\n\n#define BIT_SHIFT_MACID127_96_RELEASE_8197F 0\n#define BIT_MASK_MACID127_96_RELEASE_8197F 0xffffffffL\n#define BIT_MACID127_96_RELEASE_8197F(x)                                       \\\n\t(((x) & BIT_MASK_MACID127_96_RELEASE_8197F)                            \\\n\t << BIT_SHIFT_MACID127_96_RELEASE_8197F)\n#define BITS_MACID127_96_RELEASE_8197F                                         \\\n\t(BIT_MASK_MACID127_96_RELEASE_8197F                                    \\\n\t << BIT_SHIFT_MACID127_96_RELEASE_8197F)\n#define BIT_CLEAR_MACID127_96_RELEASE_8197F(x)                                 \\\n\t((x) & (~BITS_MACID127_96_RELEASE_8197F))\n#define BIT_GET_MACID127_96_RELEASE_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_MACID127_96_RELEASE_8197F) &                        \\\n\t BIT_MASK_MACID127_96_RELEASE_8197F)\n#define BIT_SET_MACID127_96_RELEASE_8197F(x, v)                                \\\n\t(BIT_CLEAR_MACID127_96_RELEASE_8197F(x) |                              \\\n\t BIT_MACID127_96_RELEASE_8197F(v))\n\n/* 2 REG_MACID_RELEASE_SETTING_8197F */\n#define BIT_MACID_VALUE_8197F BIT(7)\n\n#define BIT_SHIFT_MACID_OFFSET_8197F 0\n#define BIT_MASK_MACID_OFFSET_8197F 0x7f\n#define BIT_MACID_OFFSET_8197F(x)                                              \\\n\t(((x) & BIT_MASK_MACID_OFFSET_8197F) << BIT_SHIFT_MACID_OFFSET_8197F)\n#define BITS_MACID_OFFSET_8197F                                                \\\n\t(BIT_MASK_MACID_OFFSET_8197F << BIT_SHIFT_MACID_OFFSET_8197F)\n#define BIT_CLEAR_MACID_OFFSET_8197F(x) ((x) & (~BITS_MACID_OFFSET_8197F))\n#define BIT_GET_MACID_OFFSET_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_MACID_OFFSET_8197F) & BIT_MASK_MACID_OFFSET_8197F)\n#define BIT_SET_MACID_OFFSET_8197F(x, v)                                       \\\n\t(BIT_CLEAR_MACID_OFFSET_8197F(x) | BIT_MACID_OFFSET_8197F(v))\n\n/* 2 REG_FAST_EDCA_VOVI_SETTING_8197F */\n\n#define BIT_SHIFT_VI_FAST_EDCA_TO_8197F 24\n#define BIT_MASK_VI_FAST_EDCA_TO_8197F 0xff\n#define BIT_VI_FAST_EDCA_TO_8197F(x)                                           \\\n\t(((x) & BIT_MASK_VI_FAST_EDCA_TO_8197F)                                \\\n\t << BIT_SHIFT_VI_FAST_EDCA_TO_8197F)\n#define BITS_VI_FAST_EDCA_TO_8197F                                             \\\n\t(BIT_MASK_VI_FAST_EDCA_TO_8197F << BIT_SHIFT_VI_FAST_EDCA_TO_8197F)\n#define BIT_CLEAR_VI_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8197F))\n#define BIT_GET_VI_FAST_EDCA_TO_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8197F) &                            \\\n\t BIT_MASK_VI_FAST_EDCA_TO_8197F)\n#define BIT_SET_VI_FAST_EDCA_TO_8197F(x, v)                                    \\\n\t(BIT_CLEAR_VI_FAST_EDCA_TO_8197F(x) | BIT_VI_FAST_EDCA_TO_8197F(v))\n\n#define BIT_VI_THRESHOLD_SEL_8197F BIT(23)\n\n#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F 16\n#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F 0x7f\n#define BIT_VI_FAST_EDCA_PKT_TH_8197F(x)                                       \\\n\t(((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F)                            \\\n\t << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F)\n#define BITS_VI_FAST_EDCA_PKT_TH_8197F                                         \\\n\t(BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F                                    \\\n\t << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F)\n#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8197F(x)                                 \\\n\t((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8197F))\n#define BIT_GET_VI_FAST_EDCA_PKT_TH_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) &                        \\\n\t BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F)\n#define BIT_SET_VI_FAST_EDCA_PKT_TH_8197F(x, v)                                \\\n\t(BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8197F(x) |                              \\\n\t BIT_VI_FAST_EDCA_PKT_TH_8197F(v))\n\n#define BIT_SHIFT_VO_FAST_EDCA_TO_8197F 8\n#define BIT_MASK_VO_FAST_EDCA_TO_8197F 0xff\n#define BIT_VO_FAST_EDCA_TO_8197F(x)                                           \\\n\t(((x) & BIT_MASK_VO_FAST_EDCA_TO_8197F)                                \\\n\t << BIT_SHIFT_VO_FAST_EDCA_TO_8197F)\n#define BITS_VO_FAST_EDCA_TO_8197F                                             \\\n\t(BIT_MASK_VO_FAST_EDCA_TO_8197F << BIT_SHIFT_VO_FAST_EDCA_TO_8197F)\n#define BIT_CLEAR_VO_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8197F))\n#define BIT_GET_VO_FAST_EDCA_TO_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8197F) &                            \\\n\t BIT_MASK_VO_FAST_EDCA_TO_8197F)\n#define BIT_SET_VO_FAST_EDCA_TO_8197F(x, v)                                    \\\n\t(BIT_CLEAR_VO_FAST_EDCA_TO_8197F(x) | BIT_VO_FAST_EDCA_TO_8197F(v))\n\n#define BIT_VO_THRESHOLD_SEL_8197F BIT(7)\n\n#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F 0\n#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F 0x7f\n#define BIT_VO_FAST_EDCA_PKT_TH_8197F(x)                                       \\\n\t(((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F)                            \\\n\t << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F)\n#define BITS_VO_FAST_EDCA_PKT_TH_8197F                                         \\\n\t(BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F                                    \\\n\t << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F)\n#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8197F(x)                                 \\\n\t((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8197F))\n#define BIT_GET_VO_FAST_EDCA_PKT_TH_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) &                        \\\n\t BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F)\n#define BIT_SET_VO_FAST_EDCA_PKT_TH_8197F(x, v)                                \\\n\t(BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8197F(x) |                              \\\n\t BIT_VO_FAST_EDCA_PKT_TH_8197F(v))\n\n/* 2 REG_FAST_EDCA_BEBK_SETTING_8197F */\n\n#define BIT_SHIFT_BK_FAST_EDCA_TO_8197F 24\n#define BIT_MASK_BK_FAST_EDCA_TO_8197F 0xff\n#define BIT_BK_FAST_EDCA_TO_8197F(x)                                           \\\n\t(((x) & BIT_MASK_BK_FAST_EDCA_TO_8197F)                                \\\n\t << BIT_SHIFT_BK_FAST_EDCA_TO_8197F)\n#define BITS_BK_FAST_EDCA_TO_8197F                                             \\\n\t(BIT_MASK_BK_FAST_EDCA_TO_8197F << BIT_SHIFT_BK_FAST_EDCA_TO_8197F)\n#define BIT_CLEAR_BK_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8197F))\n#define BIT_GET_BK_FAST_EDCA_TO_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8197F) &                            \\\n\t BIT_MASK_BK_FAST_EDCA_TO_8197F)\n#define BIT_SET_BK_FAST_EDCA_TO_8197F(x, v)                                    \\\n\t(BIT_CLEAR_BK_FAST_EDCA_TO_8197F(x) | BIT_BK_FAST_EDCA_TO_8197F(v))\n\n#define BIT_BK_THRESHOLD_SEL_8197F BIT(23)\n\n#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F 16\n#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F 0x7f\n#define BIT_BK_FAST_EDCA_PKT_TH_8197F(x)                                       \\\n\t(((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F)                            \\\n\t << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F)\n#define BITS_BK_FAST_EDCA_PKT_TH_8197F                                         \\\n\t(BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F                                    \\\n\t << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F)\n#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8197F(x)                                 \\\n\t((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8197F))\n#define BIT_GET_BK_FAST_EDCA_PKT_TH_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) &                        \\\n\t BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F)\n#define BIT_SET_BK_FAST_EDCA_PKT_TH_8197F(x, v)                                \\\n\t(BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8197F(x) |                              \\\n\t BIT_BK_FAST_EDCA_PKT_TH_8197F(v))\n\n#define BIT_SHIFT_BE_FAST_EDCA_TO_8197F 8\n#define BIT_MASK_BE_FAST_EDCA_TO_8197F 0xff\n#define BIT_BE_FAST_EDCA_TO_8197F(x)                                           \\\n\t(((x) & BIT_MASK_BE_FAST_EDCA_TO_8197F)                                \\\n\t << BIT_SHIFT_BE_FAST_EDCA_TO_8197F)\n#define BITS_BE_FAST_EDCA_TO_8197F                                             \\\n\t(BIT_MASK_BE_FAST_EDCA_TO_8197F << BIT_SHIFT_BE_FAST_EDCA_TO_8197F)\n#define BIT_CLEAR_BE_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8197F))\n#define BIT_GET_BE_FAST_EDCA_TO_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8197F) &                            \\\n\t BIT_MASK_BE_FAST_EDCA_TO_8197F)\n#define BIT_SET_BE_FAST_EDCA_TO_8197F(x, v)                                    \\\n\t(BIT_CLEAR_BE_FAST_EDCA_TO_8197F(x) | BIT_BE_FAST_EDCA_TO_8197F(v))\n\n#define BIT_BE_THRESHOLD_SEL_8197F BIT(7)\n\n#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F 0\n#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F 0x7f\n#define BIT_BE_FAST_EDCA_PKT_TH_8197F(x)                                       \\\n\t(((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F)                            \\\n\t << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F)\n#define BITS_BE_FAST_EDCA_PKT_TH_8197F                                         \\\n\t(BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F                                    \\\n\t << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F)\n#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8197F(x)                                 \\\n\t((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8197F))\n#define BIT_GET_BE_FAST_EDCA_PKT_TH_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) &                        \\\n\t BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F)\n#define BIT_SET_BE_FAST_EDCA_PKT_TH_8197F(x, v)                                \\\n\t(BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8197F(x) |                              \\\n\t BIT_BE_FAST_EDCA_PKT_TH_8197F(v))\n\n/* 2 REG_MACID_DROP0_8197F */\n\n#define BIT_SHIFT_MACID31_0_DROP_8197F 0\n#define BIT_MASK_MACID31_0_DROP_8197F 0xffffffffL\n#define BIT_MACID31_0_DROP_8197F(x)                                            \\\n\t(((x) & BIT_MASK_MACID31_0_DROP_8197F)                                 \\\n\t << BIT_SHIFT_MACID31_0_DROP_8197F)\n#define BITS_MACID31_0_DROP_8197F                                              \\\n\t(BIT_MASK_MACID31_0_DROP_8197F << BIT_SHIFT_MACID31_0_DROP_8197F)\n#define BIT_CLEAR_MACID31_0_DROP_8197F(x) ((x) & (~BITS_MACID31_0_DROP_8197F))\n#define BIT_GET_MACID31_0_DROP_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_MACID31_0_DROP_8197F) &                             \\\n\t BIT_MASK_MACID31_0_DROP_8197F)\n#define BIT_SET_MACID31_0_DROP_8197F(x, v)                                     \\\n\t(BIT_CLEAR_MACID31_0_DROP_8197F(x) | BIT_MACID31_0_DROP_8197F(v))\n\n/* 2 REG_MACID_DROP1_8197F */\n\n#define BIT_SHIFT_MACID63_32_DROP_8197F 0\n#define BIT_MASK_MACID63_32_DROP_8197F 0xffffffffL\n#define BIT_MACID63_32_DROP_8197F(x)                                           \\\n\t(((x) & BIT_MASK_MACID63_32_DROP_8197F)                                \\\n\t << BIT_SHIFT_MACID63_32_DROP_8197F)\n#define BITS_MACID63_32_DROP_8197F                                             \\\n\t(BIT_MASK_MACID63_32_DROP_8197F << BIT_SHIFT_MACID63_32_DROP_8197F)\n#define BIT_CLEAR_MACID63_32_DROP_8197F(x) ((x) & (~BITS_MACID63_32_DROP_8197F))\n#define BIT_GET_MACID63_32_DROP_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_MACID63_32_DROP_8197F) &                            \\\n\t BIT_MASK_MACID63_32_DROP_8197F)\n#define BIT_SET_MACID63_32_DROP_8197F(x, v)                                    \\\n\t(BIT_CLEAR_MACID63_32_DROP_8197F(x) | BIT_MACID63_32_DROP_8197F(v))\n\n/* 2 REG_MACID_DROP2_8197F */\n\n#define BIT_SHIFT_MACID95_64_DROP_8197F 0\n#define BIT_MASK_MACID95_64_DROP_8197F 0xffffffffL\n#define BIT_MACID95_64_DROP_8197F(x)                                           \\\n\t(((x) & BIT_MASK_MACID95_64_DROP_8197F)                                \\\n\t << BIT_SHIFT_MACID95_64_DROP_8197F)\n#define BITS_MACID95_64_DROP_8197F                                             \\\n\t(BIT_MASK_MACID95_64_DROP_8197F << BIT_SHIFT_MACID95_64_DROP_8197F)\n#define BIT_CLEAR_MACID95_64_DROP_8197F(x) ((x) & (~BITS_MACID95_64_DROP_8197F))\n#define BIT_GET_MACID95_64_DROP_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_MACID95_64_DROP_8197F) &                            \\\n\t BIT_MASK_MACID95_64_DROP_8197F)\n#define BIT_SET_MACID95_64_DROP_8197F(x, v)                                    \\\n\t(BIT_CLEAR_MACID95_64_DROP_8197F(x) | BIT_MACID95_64_DROP_8197F(v))\n\n/* 2 REG_MACID_DROP3_8197F */\n\n#define BIT_SHIFT_MACID127_96_DROP_8197F 0\n#define BIT_MASK_MACID127_96_DROP_8197F 0xffffffffL\n#define BIT_MACID127_96_DROP_8197F(x)                                          \\\n\t(((x) & BIT_MASK_MACID127_96_DROP_8197F)                               \\\n\t << BIT_SHIFT_MACID127_96_DROP_8197F)\n#define BITS_MACID127_96_DROP_8197F                                            \\\n\t(BIT_MASK_MACID127_96_DROP_8197F << BIT_SHIFT_MACID127_96_DROP_8197F)\n#define BIT_CLEAR_MACID127_96_DROP_8197F(x)                                    \\\n\t((x) & (~BITS_MACID127_96_DROP_8197F))\n#define BIT_GET_MACID127_96_DROP_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_MACID127_96_DROP_8197F) &                           \\\n\t BIT_MASK_MACID127_96_DROP_8197F)\n#define BIT_SET_MACID127_96_DROP_8197F(x, v)                                   \\\n\t(BIT_CLEAR_MACID127_96_DROP_8197F(x) | BIT_MACID127_96_DROP_8197F(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8197F */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_0_8197F(x)                                 \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F)                      \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F)\n#define BITS_R_MACID_RELEASE_SUCCESS_0_8197F                                   \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F                              \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8197F(x)                           \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8197F))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8197F(x)                             \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) &                  \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8197F(x, v)                          \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8197F(x) |                        \\\n\t BIT_R_MACID_RELEASE_SUCCESS_0_8197F(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8197F */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_1_8197F(x)                                 \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F)                      \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F)\n#define BITS_R_MACID_RELEASE_SUCCESS_1_8197F                                   \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F                              \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8197F(x)                           \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8197F))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8197F(x)                             \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) &                  \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8197F(x, v)                          \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8197F(x) |                        \\\n\t BIT_R_MACID_RELEASE_SUCCESS_1_8197F(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8197F */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_2_8197F(x)                                 \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F)                      \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F)\n#define BITS_R_MACID_RELEASE_SUCCESS_2_8197F                                   \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F                              \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8197F(x)                           \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8197F))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8197F(x)                             \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) &                  \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8197F(x, v)                          \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8197F(x) |                        \\\n\t BIT_R_MACID_RELEASE_SUCCESS_2_8197F(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8197F */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_3_8197F(x)                                 \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F)                      \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F)\n#define BITS_R_MACID_RELEASE_SUCCESS_3_8197F                                   \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F                              \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8197F(x)                           \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8197F))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8197F(x)                             \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) &                  \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8197F(x, v)                          \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8197F(x) |                        \\\n\t BIT_R_MACID_RELEASE_SUCCESS_3_8197F(v))\n\n/* 2 REG_MGG_FIFO_CRTL_8197F */\n#define BIT_R_MGG_FIFO_EN_8197F BIT(31)\n\n#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F 28\n#define BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F 0x7\n#define BIT_R_MGG_FIFO_PG_SIZE_8197F(x)                                        \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F)                             \\\n\t << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F)\n#define BITS_R_MGG_FIFO_PG_SIZE_8197F                                          \\\n\t(BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F                                     \\\n\t << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F)\n#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8197F(x)                                  \\\n\t((x) & (~BITS_R_MGG_FIFO_PG_SIZE_8197F))\n#define BIT_GET_R_MGG_FIFO_PG_SIZE_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) &                         \\\n\t BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F)\n#define BIT_SET_R_MGG_FIFO_PG_SIZE_8197F(x, v)                                 \\\n\t(BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8197F(x) |                               \\\n\t BIT_R_MGG_FIFO_PG_SIZE_8197F(v))\n\n#define BIT_SHIFT_R_MGG_FIFO_START_PG_8197F 16\n#define BIT_MASK_R_MGG_FIFO_START_PG_8197F 0xfff\n#define BIT_R_MGG_FIFO_START_PG_8197F(x)                                       \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_START_PG_8197F)                            \\\n\t << BIT_SHIFT_R_MGG_FIFO_START_PG_8197F)\n#define BITS_R_MGG_FIFO_START_PG_8197F                                         \\\n\t(BIT_MASK_R_MGG_FIFO_START_PG_8197F                                    \\\n\t << BIT_SHIFT_R_MGG_FIFO_START_PG_8197F)\n#define BIT_CLEAR_R_MGG_FIFO_START_PG_8197F(x)                                 \\\n\t((x) & (~BITS_R_MGG_FIFO_START_PG_8197F))\n#define BIT_GET_R_MGG_FIFO_START_PG_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) &                        \\\n\t BIT_MASK_R_MGG_FIFO_START_PG_8197F)\n#define BIT_SET_R_MGG_FIFO_START_PG_8197F(x, v)                                \\\n\t(BIT_CLEAR_R_MGG_FIFO_START_PG_8197F(x) |                              \\\n\t BIT_R_MGG_FIFO_START_PG_8197F(v))\n\n#define BIT_SHIFT_R_MGG_FIFO_SIZE_8197F 14\n#define BIT_MASK_R_MGG_FIFO_SIZE_8197F 0x3\n#define BIT_R_MGG_FIFO_SIZE_8197F(x)                                           \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_SIZE_8197F)                                \\\n\t << BIT_SHIFT_R_MGG_FIFO_SIZE_8197F)\n#define BITS_R_MGG_FIFO_SIZE_8197F                                             \\\n\t(BIT_MASK_R_MGG_FIFO_SIZE_8197F << BIT_SHIFT_R_MGG_FIFO_SIZE_8197F)\n#define BIT_CLEAR_R_MGG_FIFO_SIZE_8197F(x) ((x) & (~BITS_R_MGG_FIFO_SIZE_8197F))\n#define BIT_GET_R_MGG_FIFO_SIZE_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) &                            \\\n\t BIT_MASK_R_MGG_FIFO_SIZE_8197F)\n#define BIT_SET_R_MGG_FIFO_SIZE_8197F(x, v)                                    \\\n\t(BIT_CLEAR_R_MGG_FIFO_SIZE_8197F(x) | BIT_R_MGG_FIFO_SIZE_8197F(v))\n\n#define BIT_R_MGG_FIFO_PAUSE_8197F BIT(13)\n\n#define BIT_SHIFT_R_MGG_FIFO_RPTR_8197F 8\n#define BIT_MASK_R_MGG_FIFO_RPTR_8197F 0x1f\n#define BIT_R_MGG_FIFO_RPTR_8197F(x)                                           \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_RPTR_8197F)                                \\\n\t << BIT_SHIFT_R_MGG_FIFO_RPTR_8197F)\n#define BITS_R_MGG_FIFO_RPTR_8197F                                             \\\n\t(BIT_MASK_R_MGG_FIFO_RPTR_8197F << BIT_SHIFT_R_MGG_FIFO_RPTR_8197F)\n#define BIT_CLEAR_R_MGG_FIFO_RPTR_8197F(x) ((x) & (~BITS_R_MGG_FIFO_RPTR_8197F))\n#define BIT_GET_R_MGG_FIFO_RPTR_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) &                            \\\n\t BIT_MASK_R_MGG_FIFO_RPTR_8197F)\n#define BIT_SET_R_MGG_FIFO_RPTR_8197F(x, v)                                    \\\n\t(BIT_CLEAR_R_MGG_FIFO_RPTR_8197F(x) | BIT_R_MGG_FIFO_RPTR_8197F(v))\n\n#define BIT_R_MGG_FIFO_OV_8197F BIT(7)\n#define BIT_R_MGG_FIFO_WPTR_ERROR_8197F BIT(6)\n#define BIT_R_EN_CPU_LIFETIME_8197F BIT(5)\n\n#define BIT_SHIFT_R_MGG_FIFO_WPTR_8197F 0\n#define BIT_MASK_R_MGG_FIFO_WPTR_8197F 0x1f\n#define BIT_R_MGG_FIFO_WPTR_8197F(x)                                           \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_WPTR_8197F)                                \\\n\t << BIT_SHIFT_R_MGG_FIFO_WPTR_8197F)\n#define BITS_R_MGG_FIFO_WPTR_8197F                                             \\\n\t(BIT_MASK_R_MGG_FIFO_WPTR_8197F << BIT_SHIFT_R_MGG_FIFO_WPTR_8197F)\n#define BIT_CLEAR_R_MGG_FIFO_WPTR_8197F(x) ((x) & (~BITS_R_MGG_FIFO_WPTR_8197F))\n#define BIT_GET_R_MGG_FIFO_WPTR_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) &                            \\\n\t BIT_MASK_R_MGG_FIFO_WPTR_8197F)\n#define BIT_SET_R_MGG_FIFO_WPTR_8197F(x, v)                                    \\\n\t(BIT_CLEAR_R_MGG_FIFO_WPTR_8197F(x) | BIT_R_MGG_FIFO_WPTR_8197F(v))\n\n/* 2 REG_MGG_FIFO_INT_8197F */\n\n#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F 16\n#define BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F 0xffff\n#define BIT_R_MGG_FIFO_INT_FLAG_8197F(x)                                       \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F)                            \\\n\t << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F)\n#define BITS_R_MGG_FIFO_INT_FLAG_8197F                                         \\\n\t(BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F                                    \\\n\t << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F)\n#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8197F(x)                                 \\\n\t((x) & (~BITS_R_MGG_FIFO_INT_FLAG_8197F))\n#define BIT_GET_R_MGG_FIFO_INT_FLAG_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) &                        \\\n\t BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F)\n#define BIT_SET_R_MGG_FIFO_INT_FLAG_8197F(x, v)                                \\\n\t(BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8197F(x) |                              \\\n\t BIT_R_MGG_FIFO_INT_FLAG_8197F(v))\n\n#define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F 0\n#define BIT_MASK_R_MGG_FIFO_INT_MASK_8197F 0xffff\n#define BIT_R_MGG_FIFO_INT_MASK_8197F(x)                                       \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8197F)                            \\\n\t << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F)\n#define BITS_R_MGG_FIFO_INT_MASK_8197F                                         \\\n\t(BIT_MASK_R_MGG_FIFO_INT_MASK_8197F                                    \\\n\t << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F)\n#define BIT_CLEAR_R_MGG_FIFO_INT_MASK_8197F(x)                                 \\\n\t((x) & (~BITS_R_MGG_FIFO_INT_MASK_8197F))\n#define BIT_GET_R_MGG_FIFO_INT_MASK_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) &                        \\\n\t BIT_MASK_R_MGG_FIFO_INT_MASK_8197F)\n#define BIT_SET_R_MGG_FIFO_INT_MASK_8197F(x, v)                                \\\n\t(BIT_CLEAR_R_MGG_FIFO_INT_MASK_8197F(x) |                              \\\n\t BIT_R_MGG_FIFO_INT_MASK_8197F(v))\n\n/* 2 REG_MGG_FIFO_LIFETIME_8197F */\n\n#define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F 16\n#define BIT_MASK_R_MGG_FIFO_LIFETIME_8197F 0xffff\n#define BIT_R_MGG_FIFO_LIFETIME_8197F(x)                                       \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8197F)                            \\\n\t << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F)\n#define BITS_R_MGG_FIFO_LIFETIME_8197F                                         \\\n\t(BIT_MASK_R_MGG_FIFO_LIFETIME_8197F                                    \\\n\t << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F)\n#define BIT_CLEAR_R_MGG_FIFO_LIFETIME_8197F(x)                                 \\\n\t((x) & (~BITS_R_MGG_FIFO_LIFETIME_8197F))\n#define BIT_GET_R_MGG_FIFO_LIFETIME_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) &                        \\\n\t BIT_MASK_R_MGG_FIFO_LIFETIME_8197F)\n#define BIT_SET_R_MGG_FIFO_LIFETIME_8197F(x, v)                                \\\n\t(BIT_CLEAR_R_MGG_FIFO_LIFETIME_8197F(x) |                              \\\n\t BIT_R_MGG_FIFO_LIFETIME_8197F(v))\n\n#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F 0\n#define BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F 0xffff\n#define BIT_R_MGG_FIFO_VALID_MAP_8197F(x)                                      \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F)                           \\\n\t << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F)\n#define BITS_R_MGG_FIFO_VALID_MAP_8197F                                        \\\n\t(BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F                                   \\\n\t << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F)\n#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8197F(x)                                \\\n\t((x) & (~BITS_R_MGG_FIFO_VALID_MAP_8197F))\n#define BIT_GET_R_MGG_FIFO_VALID_MAP_8197F(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) &                       \\\n\t BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F)\n#define BIT_SET_R_MGG_FIFO_VALID_MAP_8197F(x, v)                               \\\n\t(BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8197F(x) |                             \\\n\t BIT_R_MGG_FIFO_VALID_MAP_8197F(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0x7f\n#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x)                      \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F)           \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F)\n#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F                        \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F                   \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x)                \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x)                  \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) &       \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x, v)               \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) |             \\\n\t BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(v))\n\n/* 2 REG_SHCUT_SETTING_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_SHCUT_LLC_ETH_TYPE0_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_SHCUT_LLC_ETH_TYPE1_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_SHCUT_LLC_OUI0_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_SHCUT_LLC_OUI1_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_SHCUT_LLC_OUI2_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_SHCUT_LLC_OUI3_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_CHNL_INFO_CTRL_8197F */\n#define BIT_CHNL_REF_RXNAV_8197F BIT(7)\n#define BIT_CHNL_REF_VBON_8197F BIT(6)\n#define BIT_CHNL_REF_EDCCA_8197F BIT(5)\n#define BIT_RST_CHNL_BUSY_8197F BIT(3)\n#define BIT_RST_CHNL_IDLE_8197F BIT(2)\n#define BIT_CHNL_INFO_RST_8197F BIT(1)\n#define BIT_ATM_AIRTIME_EN_8197F BIT(0)\n\n/* 2 REG_CHNL_IDLE_TIME_8197F */\n\n#define BIT_SHIFT_CHNL_IDLE_TIME_8197F 0\n#define BIT_MASK_CHNL_IDLE_TIME_8197F 0xffffffffL\n#define BIT_CHNL_IDLE_TIME_8197F(x)                                            \\\n\t(((x) & BIT_MASK_CHNL_IDLE_TIME_8197F)                                 \\\n\t << BIT_SHIFT_CHNL_IDLE_TIME_8197F)\n#define BITS_CHNL_IDLE_TIME_8197F                                              \\\n\t(BIT_MASK_CHNL_IDLE_TIME_8197F << BIT_SHIFT_CHNL_IDLE_TIME_8197F)\n#define BIT_CLEAR_CHNL_IDLE_TIME_8197F(x) ((x) & (~BITS_CHNL_IDLE_TIME_8197F))\n#define BIT_GET_CHNL_IDLE_TIME_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8197F) &                             \\\n\t BIT_MASK_CHNL_IDLE_TIME_8197F)\n#define BIT_SET_CHNL_IDLE_TIME_8197F(x, v)                                     \\\n\t(BIT_CLEAR_CHNL_IDLE_TIME_8197F(x) | BIT_CHNL_IDLE_TIME_8197F(v))\n\n/* 2 REG_CHNL_BUSY_TIME_8197F */\n\n#define BIT_SHIFT_CHNL_BUSY_TIME_8197F 0\n#define BIT_MASK_CHNL_BUSY_TIME_8197F 0xffffffffL\n#define BIT_CHNL_BUSY_TIME_8197F(x)                                            \\\n\t(((x) & BIT_MASK_CHNL_BUSY_TIME_8197F)                                 \\\n\t << BIT_SHIFT_CHNL_BUSY_TIME_8197F)\n#define BITS_CHNL_BUSY_TIME_8197F                                              \\\n\t(BIT_MASK_CHNL_BUSY_TIME_8197F << BIT_SHIFT_CHNL_BUSY_TIME_8197F)\n#define BIT_CLEAR_CHNL_BUSY_TIME_8197F(x) ((x) & (~BITS_CHNL_BUSY_TIME_8197F))\n#define BIT_GET_CHNL_BUSY_TIME_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8197F) &                             \\\n\t BIT_MASK_CHNL_BUSY_TIME_8197F)\n#define BIT_SET_CHNL_BUSY_TIME_8197F(x, v)                                     \\\n\t(BIT_CLEAR_CHNL_BUSY_TIME_8197F(x) | BIT_CHNL_BUSY_TIME_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_EDCA_VO_PARAM_8197F */\n\n#define BIT_SHIFT_TXOPLIMIT_8197F 16\n#define BIT_MASK_TXOPLIMIT_8197F 0x7ff\n#define BIT_TXOPLIMIT_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F)\n#define BITS_TXOPLIMIT_8197F                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F)\n#define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F))\n#define BIT_GET_TXOPLIMIT_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F)\n#define BIT_SET_TXOPLIMIT_8197F(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v))\n\n#define BIT_SHIFT_CW_8197F 8\n#define BIT_MASK_CW_8197F 0xff\n#define BIT_CW_8197F(x) (((x) & BIT_MASK_CW_8197F) << BIT_SHIFT_CW_8197F)\n#define BITS_CW_8197F (BIT_MASK_CW_8197F << BIT_SHIFT_CW_8197F)\n#define BIT_CLEAR_CW_8197F(x) ((x) & (~BITS_CW_8197F))\n#define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F)\n#define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v))\n\n#define BIT_SHIFT_AIFS_8197F 0\n#define BIT_MASK_AIFS_8197F 0xff\n#define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F)\n#define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F)\n#define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F))\n#define BIT_GET_AIFS_8197F(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F)\n#define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v))\n\n/* 2 REG_EDCA_VI_PARAM_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n#define BIT_SHIFT_TXOPLIMIT_8197F 16\n#define BIT_MASK_TXOPLIMIT_8197F 0x7ff\n#define BIT_TXOPLIMIT_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F)\n#define BITS_TXOPLIMIT_8197F                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F)\n#define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F))\n#define BIT_GET_TXOPLIMIT_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F)\n#define BIT_SET_TXOPLIMIT_8197F(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v))\n\n#define BIT_SHIFT_CW_8197F 8\n#define BIT_MASK_CW_8197F 0xff\n#define BIT_CW_8197F(x) (((x) & BIT_MASK_CW_8197F) << BIT_SHIFT_CW_8197F)\n#define BITS_CW_8197F (BIT_MASK_CW_8197F << BIT_SHIFT_CW_8197F)\n#define BIT_CLEAR_CW_8197F(x) ((x) & (~BITS_CW_8197F))\n#define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F)\n#define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v))\n\n#define BIT_SHIFT_AIFS_8197F 0\n#define BIT_MASK_AIFS_8197F 0xff\n#define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F)\n#define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F)\n#define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F))\n#define BIT_GET_AIFS_8197F(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F)\n#define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v))\n\n/* 2 REG_EDCA_BE_PARAM_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n#define BIT_SHIFT_TXOPLIMIT_8197F 16\n#define BIT_MASK_TXOPLIMIT_8197F 0x7ff\n#define BIT_TXOPLIMIT_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F)\n#define BITS_TXOPLIMIT_8197F                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F)\n#define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F))\n#define BIT_GET_TXOPLIMIT_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F)\n#define BIT_SET_TXOPLIMIT_8197F(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v))\n\n#define BIT_SHIFT_CW_8197F 8\n#define BIT_MASK_CW_8197F 0xff\n#define BIT_CW_8197F(x) (((x) & BIT_MASK_CW_8197F) << BIT_SHIFT_CW_8197F)\n#define BITS_CW_8197F (BIT_MASK_CW_8197F << BIT_SHIFT_CW_8197F)\n#define BIT_CLEAR_CW_8197F(x) ((x) & (~BITS_CW_8197F))\n#define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F)\n#define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v))\n\n#define BIT_SHIFT_AIFS_8197F 0\n#define BIT_MASK_AIFS_8197F 0xff\n#define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F)\n#define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F)\n#define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F))\n#define BIT_GET_AIFS_8197F(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F)\n#define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v))\n\n/* 2 REG_EDCA_BK_PARAM_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n#define BIT_SHIFT_TXOPLIMIT_8197F 16\n#define BIT_MASK_TXOPLIMIT_8197F 0x7ff\n#define BIT_TXOPLIMIT_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F)\n#define BITS_TXOPLIMIT_8197F                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F)\n#define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F))\n#define BIT_GET_TXOPLIMIT_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F)\n#define BIT_SET_TXOPLIMIT_8197F(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v))\n\n#define BIT_SHIFT_CW_8197F 8\n#define BIT_MASK_CW_8197F 0xff\n#define BIT_CW_8197F(x) (((x) & BIT_MASK_CW_8197F) << BIT_SHIFT_CW_8197F)\n#define BITS_CW_8197F (BIT_MASK_CW_8197F << BIT_SHIFT_CW_8197F)\n#define BIT_CLEAR_CW_8197F(x) ((x) & (~BITS_CW_8197F))\n#define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F)\n#define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v))\n\n#define BIT_SHIFT_AIFS_8197F 0\n#define BIT_MASK_AIFS_8197F 0xff\n#define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F)\n#define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F)\n#define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F))\n#define BIT_GET_AIFS_8197F(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F)\n#define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v))\n\n/* 2 REG_BCNTCFG_8197F */\n\n#define BIT_SHIFT_BCNCW_MAX_8197F 12\n#define BIT_MASK_BCNCW_MAX_8197F 0xf\n#define BIT_BCNCW_MAX_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_BCNCW_MAX_8197F) << BIT_SHIFT_BCNCW_MAX_8197F)\n#define BITS_BCNCW_MAX_8197F                                                   \\\n\t(BIT_MASK_BCNCW_MAX_8197F << BIT_SHIFT_BCNCW_MAX_8197F)\n#define BIT_CLEAR_BCNCW_MAX_8197F(x) ((x) & (~BITS_BCNCW_MAX_8197F))\n#define BIT_GET_BCNCW_MAX_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNCW_MAX_8197F) & BIT_MASK_BCNCW_MAX_8197F)\n#define BIT_SET_BCNCW_MAX_8197F(x, v)                                          \\\n\t(BIT_CLEAR_BCNCW_MAX_8197F(x) | BIT_BCNCW_MAX_8197F(v))\n\n#define BIT_SHIFT_BCNCW_MIN_8197F 8\n#define BIT_MASK_BCNCW_MIN_8197F 0xf\n#define BIT_BCNCW_MIN_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_BCNCW_MIN_8197F) << BIT_SHIFT_BCNCW_MIN_8197F)\n#define BITS_BCNCW_MIN_8197F                                                   \\\n\t(BIT_MASK_BCNCW_MIN_8197F << BIT_SHIFT_BCNCW_MIN_8197F)\n#define BIT_CLEAR_BCNCW_MIN_8197F(x) ((x) & (~BITS_BCNCW_MIN_8197F))\n#define BIT_GET_BCNCW_MIN_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNCW_MIN_8197F) & BIT_MASK_BCNCW_MIN_8197F)\n#define BIT_SET_BCNCW_MIN_8197F(x, v)                                          \\\n\t(BIT_CLEAR_BCNCW_MIN_8197F(x) | BIT_BCNCW_MIN_8197F(v))\n\n#define BIT_SHIFT_BCNIFS_8197F 0\n#define BIT_MASK_BCNIFS_8197F 0xff\n#define BIT_BCNIFS_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_BCNIFS_8197F) << BIT_SHIFT_BCNIFS_8197F)\n#define BITS_BCNIFS_8197F (BIT_MASK_BCNIFS_8197F << BIT_SHIFT_BCNIFS_8197F)\n#define BIT_CLEAR_BCNIFS_8197F(x) ((x) & (~BITS_BCNIFS_8197F))\n#define BIT_GET_BCNIFS_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_BCNIFS_8197F) & BIT_MASK_BCNIFS_8197F)\n#define BIT_SET_BCNIFS_8197F(x, v)                                             \\\n\t(BIT_CLEAR_BCNIFS_8197F(x) | BIT_BCNIFS_8197F(v))\n\n/* 2 REG_PIFS_8197F */\n\n#define BIT_SHIFT_PIFS_8197F 0\n#define BIT_MASK_PIFS_8197F 0xff\n#define BIT_PIFS_8197F(x) (((x) & BIT_MASK_PIFS_8197F) << BIT_SHIFT_PIFS_8197F)\n#define BITS_PIFS_8197F (BIT_MASK_PIFS_8197F << BIT_SHIFT_PIFS_8197F)\n#define BIT_CLEAR_PIFS_8197F(x) ((x) & (~BITS_PIFS_8197F))\n#define BIT_GET_PIFS_8197F(x)                                                  \\\n\t(((x) >> BIT_SHIFT_PIFS_8197F) & BIT_MASK_PIFS_8197F)\n#define BIT_SET_PIFS_8197F(x, v) (BIT_CLEAR_PIFS_8197F(x) | BIT_PIFS_8197F(v))\n\n/* 2 REG_RDG_PIFS_8197F */\n\n#define BIT_SHIFT_RDG_PIFS_8197F 0\n#define BIT_MASK_RDG_PIFS_8197F 0xff\n#define BIT_RDG_PIFS_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_RDG_PIFS_8197F) << BIT_SHIFT_RDG_PIFS_8197F)\n#define BITS_RDG_PIFS_8197F                                                    \\\n\t(BIT_MASK_RDG_PIFS_8197F << BIT_SHIFT_RDG_PIFS_8197F)\n#define BIT_CLEAR_RDG_PIFS_8197F(x) ((x) & (~BITS_RDG_PIFS_8197F))\n#define BIT_GET_RDG_PIFS_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_RDG_PIFS_8197F) & BIT_MASK_RDG_PIFS_8197F)\n#define BIT_SET_RDG_PIFS_8197F(x, v)                                           \\\n\t(BIT_CLEAR_RDG_PIFS_8197F(x) | BIT_RDG_PIFS_8197F(v))\n\n/* 2 REG_SIFS_8197F */\n\n#define BIT_SHIFT_SIFS_OFDM_TRX_8197F 24\n#define BIT_MASK_SIFS_OFDM_TRX_8197F 0xff\n#define BIT_SIFS_OFDM_TRX_8197F(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_OFDM_TRX_8197F) << BIT_SHIFT_SIFS_OFDM_TRX_8197F)\n#define BITS_SIFS_OFDM_TRX_8197F                                               \\\n\t(BIT_MASK_SIFS_OFDM_TRX_8197F << BIT_SHIFT_SIFS_OFDM_TRX_8197F)\n#define BIT_CLEAR_SIFS_OFDM_TRX_8197F(x) ((x) & (~BITS_SIFS_OFDM_TRX_8197F))\n#define BIT_GET_SIFS_OFDM_TRX_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8197F) & BIT_MASK_SIFS_OFDM_TRX_8197F)\n#define BIT_SET_SIFS_OFDM_TRX_8197F(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_OFDM_TRX_8197F(x) | BIT_SIFS_OFDM_TRX_8197F(v))\n\n#define BIT_SHIFT_SIFS_CCK_TRX_8197F 16\n#define BIT_MASK_SIFS_CCK_TRX_8197F 0xff\n#define BIT_SIFS_CCK_TRX_8197F(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_CCK_TRX_8197F) << BIT_SHIFT_SIFS_CCK_TRX_8197F)\n#define BITS_SIFS_CCK_TRX_8197F                                                \\\n\t(BIT_MASK_SIFS_CCK_TRX_8197F << BIT_SHIFT_SIFS_CCK_TRX_8197F)\n#define BIT_CLEAR_SIFS_CCK_TRX_8197F(x) ((x) & (~BITS_SIFS_CCK_TRX_8197F))\n#define BIT_GET_SIFS_CCK_TRX_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_CCK_TRX_8197F) & BIT_MASK_SIFS_CCK_TRX_8197F)\n#define BIT_SET_SIFS_CCK_TRX_8197F(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_CCK_TRX_8197F(x) | BIT_SIFS_CCK_TRX_8197F(v))\n\n#define BIT_SHIFT_SIFS_OFDM_CTX_8197F 8\n#define BIT_MASK_SIFS_OFDM_CTX_8197F 0xff\n#define BIT_SIFS_OFDM_CTX_8197F(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_OFDM_CTX_8197F) << BIT_SHIFT_SIFS_OFDM_CTX_8197F)\n#define BITS_SIFS_OFDM_CTX_8197F                                               \\\n\t(BIT_MASK_SIFS_OFDM_CTX_8197F << BIT_SHIFT_SIFS_OFDM_CTX_8197F)\n#define BIT_CLEAR_SIFS_OFDM_CTX_8197F(x) ((x) & (~BITS_SIFS_OFDM_CTX_8197F))\n#define BIT_GET_SIFS_OFDM_CTX_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8197F) & BIT_MASK_SIFS_OFDM_CTX_8197F)\n#define BIT_SET_SIFS_OFDM_CTX_8197F(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_OFDM_CTX_8197F(x) | BIT_SIFS_OFDM_CTX_8197F(v))\n\n#define BIT_SHIFT_SIFS_CCK_CTX_8197F 0\n#define BIT_MASK_SIFS_CCK_CTX_8197F 0xff\n#define BIT_SIFS_CCK_CTX_8197F(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_CCK_CTX_8197F) << BIT_SHIFT_SIFS_CCK_CTX_8197F)\n#define BITS_SIFS_CCK_CTX_8197F                                                \\\n\t(BIT_MASK_SIFS_CCK_CTX_8197F << BIT_SHIFT_SIFS_CCK_CTX_8197F)\n#define BIT_CLEAR_SIFS_CCK_CTX_8197F(x) ((x) & (~BITS_SIFS_CCK_CTX_8197F))\n#define BIT_GET_SIFS_CCK_CTX_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_CCK_CTX_8197F) & BIT_MASK_SIFS_CCK_CTX_8197F)\n#define BIT_SET_SIFS_CCK_CTX_8197F(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_CCK_CTX_8197F(x) | BIT_SIFS_CCK_CTX_8197F(v))\n\n/* 2 REG_TSFTR_SYN_OFFSET_8197F */\n\n#define BIT_SHIFT_TSFTR_SNC_OFFSET_8197F 0\n#define BIT_MASK_TSFTR_SNC_OFFSET_8197F 0xffff\n#define BIT_TSFTR_SNC_OFFSET_8197F(x)                                          \\\n\t(((x) & BIT_MASK_TSFTR_SNC_OFFSET_8197F)                               \\\n\t << BIT_SHIFT_TSFTR_SNC_OFFSET_8197F)\n#define BITS_TSFTR_SNC_OFFSET_8197F                                            \\\n\t(BIT_MASK_TSFTR_SNC_OFFSET_8197F << BIT_SHIFT_TSFTR_SNC_OFFSET_8197F)\n#define BIT_CLEAR_TSFTR_SNC_OFFSET_8197F(x)                                    \\\n\t((x) & (~BITS_TSFTR_SNC_OFFSET_8197F))\n#define BIT_GET_TSFTR_SNC_OFFSET_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) &                           \\\n\t BIT_MASK_TSFTR_SNC_OFFSET_8197F)\n#define BIT_SET_TSFTR_SNC_OFFSET_8197F(x, v)                                   \\\n\t(BIT_CLEAR_TSFTR_SNC_OFFSET_8197F(x) | BIT_TSFTR_SNC_OFFSET_8197F(v))\n\n/* 2 REG_AGGR_BREAK_TIME_8197F */\n\n#define BIT_SHIFT_AGGR_BK_TIME_8197F 0\n#define BIT_MASK_AGGR_BK_TIME_8197F 0xff\n#define BIT_AGGR_BK_TIME_8197F(x)                                              \\\n\t(((x) & BIT_MASK_AGGR_BK_TIME_8197F) << BIT_SHIFT_AGGR_BK_TIME_8197F)\n#define BITS_AGGR_BK_TIME_8197F                                                \\\n\t(BIT_MASK_AGGR_BK_TIME_8197F << BIT_SHIFT_AGGR_BK_TIME_8197F)\n#define BIT_CLEAR_AGGR_BK_TIME_8197F(x) ((x) & (~BITS_AGGR_BK_TIME_8197F))\n#define BIT_GET_AGGR_BK_TIME_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_AGGR_BK_TIME_8197F) & BIT_MASK_AGGR_BK_TIME_8197F)\n#define BIT_SET_AGGR_BK_TIME_8197F(x, v)                                       \\\n\t(BIT_CLEAR_AGGR_BK_TIME_8197F(x) | BIT_AGGR_BK_TIME_8197F(v))\n\n/* 2 REG_SLOT_8197F */\n\n#define BIT_SHIFT_SLOT_8197F 0\n#define BIT_MASK_SLOT_8197F 0xff\n#define BIT_SLOT_8197F(x) (((x) & BIT_MASK_SLOT_8197F) << BIT_SHIFT_SLOT_8197F)\n#define BITS_SLOT_8197F (BIT_MASK_SLOT_8197F << BIT_SHIFT_SLOT_8197F)\n#define BIT_CLEAR_SLOT_8197F(x) ((x) & (~BITS_SLOT_8197F))\n#define BIT_GET_SLOT_8197F(x)                                                  \\\n\t(((x) >> BIT_SHIFT_SLOT_8197F) & BIT_MASK_SLOT_8197F)\n#define BIT_SET_SLOT_8197F(x, v) (BIT_CLEAR_SLOT_8197F(x) | BIT_SLOT_8197F(v))\n\n/* 2 REG_TX_PTCL_CTRL_8197F */\n#define BIT_DIS_EDCCA_8197F BIT(15)\n#define BIT_DIS_CCA_8197F BIT(14)\n#define BIT_LSIG_TXOP_TXCMD_NAV_8197F BIT(13)\n#define BIT_SIFS_BK_EN_8197F BIT(12)\n\n#define BIT_SHIFT_TXQ_NAV_MSK_8197F 8\n#define BIT_MASK_TXQ_NAV_MSK_8197F 0xf\n#define BIT_TXQ_NAV_MSK_8197F(x)                                               \\\n\t(((x) & BIT_MASK_TXQ_NAV_MSK_8197F) << BIT_SHIFT_TXQ_NAV_MSK_8197F)\n#define BITS_TXQ_NAV_MSK_8197F                                                 \\\n\t(BIT_MASK_TXQ_NAV_MSK_8197F << BIT_SHIFT_TXQ_NAV_MSK_8197F)\n#define BIT_CLEAR_TXQ_NAV_MSK_8197F(x) ((x) & (~BITS_TXQ_NAV_MSK_8197F))\n#define BIT_GET_TXQ_NAV_MSK_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_TXQ_NAV_MSK_8197F) & BIT_MASK_TXQ_NAV_MSK_8197F)\n#define BIT_SET_TXQ_NAV_MSK_8197F(x, v)                                        \\\n\t(BIT_CLEAR_TXQ_NAV_MSK_8197F(x) | BIT_TXQ_NAV_MSK_8197F(v))\n\n#define BIT_DIS_CW_8197F BIT(7)\n#define BIT_NAV_END_TXOP_8197F BIT(6)\n#define BIT_RDG_END_TXOP_8197F BIT(5)\n#define BIT_AC_INBCN_HOLD_8197F BIT(4)\n#define BIT_MGTQ_TXOP_EN_8197F BIT(3)\n#define BIT_MGTQ_RTSMF_EN_8197F BIT(2)\n#define BIT_HIQ_RTSMF_EN_8197F BIT(1)\n#define BIT_BCN_RTSMF_EN_8197F BIT(0)\n\n/* 2 REG_TXPAUSE_8197F */\n#define BIT_STOP_BCN_HI_MGT_8197F BIT(7)\n#define BIT_MAC_STOPBCNQ_8197F BIT(6)\n#define BIT_MAC_STOPHIQ_8197F BIT(5)\n#define BIT_MAC_STOPMGQ_8197F BIT(4)\n#define BIT_MAC_STOPBK_8197F BIT(3)\n#define BIT_MAC_STOPBE_8197F BIT(2)\n#define BIT_MAC_STOPVI_8197F BIT(1)\n#define BIT_MAC_STOPVO_8197F BIT(0)\n\n/* 2 REG_DIS_TXREQ_CLR_8197F */\n#define BIT_DIS_BT_CCA_8197F BIT(7)\n#define BIT_DIS_TXREQ_CLR_CPUMGQ_8197F BIT(6)\n#define BIT_DIS_TXREQ_CLR_HI_8197F BIT(5)\n#define BIT_DIS_TXREQ_CLR_MGQ_8197F BIT(4)\n#define BIT_DIS_TXREQ_CLR_VO_8197F BIT(3)\n#define BIT_DIS_TXREQ_CLR_VI_8197F BIT(2)\n#define BIT_DIS_TXREQ_CLR_BE_8197F BIT(1)\n#define BIT_DIS_TXREQ_CLR_BK_8197F BIT(0)\n\n/* 2 REG_RD_CTRL_8197F */\n#define BIT_EN_CLR_TXREQ_INCCA_8197F BIT(15)\n#define BIT_DIS_TX_OVER_BCNQ_8197F BIT(14)\n#define BIT_EN_BCNERR_INCCA_8197F BIT(13)\n#define BIT_EN_BCNERR_INEDCCA_8197F BIT(12)\n#define BIT_EDCCA_MSK_CNTDOWN_EN_8197F BIT(11)\n#define BIT_DIS_TXOP_CFE_8197F BIT(10)\n#define BIT_DIS_LSIG_CFE_8197F BIT(9)\n#define BIT_DIS_STBC_CFE_8197F BIT(8)\n#define BIT_BKQ_RD_INIT_EN_8197F BIT(7)\n#define BIT_BEQ_RD_INIT_EN_8197F BIT(6)\n#define BIT_VIQ_RD_INIT_EN_8197F BIT(5)\n#define BIT_VOQ_RD_INIT_EN_8197F BIT(4)\n#define BIT_BKQ_RD_RESP_EN_8197F BIT(3)\n#define BIT_BEQ_RD_RESP_EN_8197F BIT(2)\n#define BIT_VIQ_RD_RESP_EN_8197F BIT(1)\n#define BIT_VOQ_RD_RESP_EN_8197F BIT(0)\n\n/* 2 REG_MBSSID_CTRL_8197F */\n#define BIT_MBID_BCNQ7_EN_8197F BIT(7)\n#define BIT_MBID_BCNQ6_EN_8197F BIT(6)\n#define BIT_MBID_BCNQ5_EN_8197F BIT(5)\n#define BIT_MBID_BCNQ4_EN_8197F BIT(4)\n#define BIT_MBID_BCNQ3_EN_8197F BIT(3)\n#define BIT_MBID_BCNQ2_EN_8197F BIT(2)\n#define BIT_MBID_BCNQ1_EN_8197F BIT(1)\n#define BIT_MBID_BCNQ0_EN_8197F BIT(0)\n\n/* 2 REG_P2PPS_CTRL_8197F */\n#define BIT_P2P_CTW_ALLSTASLEEP_8197F BIT(7)\n#define BIT_P2P_OFF_DISTX_EN_8197F BIT(6)\n#define BIT_PWR_MGT_EN_8197F BIT(5)\n#define BIT_P2P_NOA1_EN_8197F BIT(2)\n#define BIT_P2P_NOA0_EN_8197F BIT(1)\n\n/* 2 REG_PKT_LIFETIME_CTRL_8197F */\n#define BIT_EN_TBTT_AREA_FOR_BB_8197F BIT(23)\n#define BIT_EN_BKF_CLR_TXREQ_8197F BIT(22)\n#define BIT_EN_TSFBIT32_RST_P2P_8197F BIT(21)\n#define BIT_EN_BCN_TX_BTCCA_8197F BIT(20)\n#define BIT_DIS_PKT_TX_ATIM_8197F BIT(19)\n#define BIT_DIS_BCN_DIS_CTN_8197F BIT(18)\n#define BIT_EN_NAVEND_RST_TXOP_8197F BIT(17)\n#define BIT_EN_FILTER_CCA_8197F BIT(16)\n\n#define BIT_SHIFT_CCA_FILTER_THRS_8197F 8\n#define BIT_MASK_CCA_FILTER_THRS_8197F 0xff\n#define BIT_CCA_FILTER_THRS_8197F(x)                                           \\\n\t(((x) & BIT_MASK_CCA_FILTER_THRS_8197F)                                \\\n\t << BIT_SHIFT_CCA_FILTER_THRS_8197F)\n#define BITS_CCA_FILTER_THRS_8197F                                             \\\n\t(BIT_MASK_CCA_FILTER_THRS_8197F << BIT_SHIFT_CCA_FILTER_THRS_8197F)\n#define BIT_CLEAR_CCA_FILTER_THRS_8197F(x) ((x) & (~BITS_CCA_FILTER_THRS_8197F))\n#define BIT_GET_CCA_FILTER_THRS_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_CCA_FILTER_THRS_8197F) &                            \\\n\t BIT_MASK_CCA_FILTER_THRS_8197F)\n#define BIT_SET_CCA_FILTER_THRS_8197F(x, v)                                    \\\n\t(BIT_CLEAR_CCA_FILTER_THRS_8197F(x) | BIT_CCA_FILTER_THRS_8197F(v))\n\n#define BIT_SHIFT_EDCCA_THRS_8197F 0\n#define BIT_MASK_EDCCA_THRS_8197F 0xff\n#define BIT_EDCCA_THRS_8197F(x)                                                \\\n\t(((x) & BIT_MASK_EDCCA_THRS_8197F) << BIT_SHIFT_EDCCA_THRS_8197F)\n#define BITS_EDCCA_THRS_8197F                                                  \\\n\t(BIT_MASK_EDCCA_THRS_8197F << BIT_SHIFT_EDCCA_THRS_8197F)\n#define BIT_CLEAR_EDCCA_THRS_8197F(x) ((x) & (~BITS_EDCCA_THRS_8197F))\n#define BIT_GET_EDCCA_THRS_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_EDCCA_THRS_8197F) & BIT_MASK_EDCCA_THRS_8197F)\n#define BIT_SET_EDCCA_THRS_8197F(x, v)                                         \\\n\t(BIT_CLEAR_EDCCA_THRS_8197F(x) | BIT_EDCCA_THRS_8197F(v))\n\n/* 2 REG_P2PPS_SPEC_STATE_8197F */\n#define BIT_SPEC_POWER_STATE_8197F BIT(7)\n#define BIT_SPEC_CTWINDOW_ON_8197F BIT(6)\n#define BIT_SPEC_BEACON_AREA_ON_8197F BIT(5)\n#define BIT_SPEC_CTWIN_EARLY_DISTX_8197F BIT(4)\n#define BIT_SPEC_NOA1_OFF_PERIOD_8197F BIT(3)\n#define BIT_SPEC_FORCE_DOZE1_8197F BIT(2)\n#define BIT_SPEC_NOA0_OFF_PERIOD_8197F BIT(1)\n#define BIT_SPEC_FORCE_DOZE0_8197F BIT(0)\n\n/* 2 REG_NOT_VALID_8197F */\n\n#define BIT_SHIFT_P2PON_DIS_TXTIME_8197F 0\n#define BIT_MASK_P2PON_DIS_TXTIME_8197F 0xff\n#define BIT_P2PON_DIS_TXTIME_8197F(x)                                          \\\n\t(((x) & BIT_MASK_P2PON_DIS_TXTIME_8197F)                               \\\n\t << BIT_SHIFT_P2PON_DIS_TXTIME_8197F)\n#define BITS_P2PON_DIS_TXTIME_8197F                                            \\\n\t(BIT_MASK_P2PON_DIS_TXTIME_8197F << BIT_SHIFT_P2PON_DIS_TXTIME_8197F)\n#define BIT_CLEAR_P2PON_DIS_TXTIME_8197F(x)                                    \\\n\t((x) & (~BITS_P2PON_DIS_TXTIME_8197F))\n#define BIT_GET_P2PON_DIS_TXTIME_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8197F) &                           \\\n\t BIT_MASK_P2PON_DIS_TXTIME_8197F)\n#define BIT_SET_P2PON_DIS_TXTIME_8197F(x, v)                                   \\\n\t(BIT_CLEAR_P2PON_DIS_TXTIME_8197F(x) | BIT_P2PON_DIS_TXTIME_8197F(v))\n\n/* 2 REG_QUEUE_INCOL_THR_8197F */\n\n#define BIT_SHIFT_BK_QUEUE_THR_8197F 24\n#define BIT_MASK_BK_QUEUE_THR_8197F 0xff\n#define BIT_BK_QUEUE_THR_8197F(x)                                              \\\n\t(((x) & BIT_MASK_BK_QUEUE_THR_8197F) << BIT_SHIFT_BK_QUEUE_THR_8197F)\n#define BITS_BK_QUEUE_THR_8197F                                                \\\n\t(BIT_MASK_BK_QUEUE_THR_8197F << BIT_SHIFT_BK_QUEUE_THR_8197F)\n#define BIT_CLEAR_BK_QUEUE_THR_8197F(x) ((x) & (~BITS_BK_QUEUE_THR_8197F))\n#define BIT_GET_BK_QUEUE_THR_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_BK_QUEUE_THR_8197F) & BIT_MASK_BK_QUEUE_THR_8197F)\n#define BIT_SET_BK_QUEUE_THR_8197F(x, v)                                       \\\n\t(BIT_CLEAR_BK_QUEUE_THR_8197F(x) | BIT_BK_QUEUE_THR_8197F(v))\n\n#define BIT_SHIFT_BE_QUEUE_THR_8197F 16\n#define BIT_MASK_BE_QUEUE_THR_8197F 0xff\n#define BIT_BE_QUEUE_THR_8197F(x)                                              \\\n\t(((x) & BIT_MASK_BE_QUEUE_THR_8197F) << BIT_SHIFT_BE_QUEUE_THR_8197F)\n#define BITS_BE_QUEUE_THR_8197F                                                \\\n\t(BIT_MASK_BE_QUEUE_THR_8197F << BIT_SHIFT_BE_QUEUE_THR_8197F)\n#define BIT_CLEAR_BE_QUEUE_THR_8197F(x) ((x) & (~BITS_BE_QUEUE_THR_8197F))\n#define BIT_GET_BE_QUEUE_THR_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_BE_QUEUE_THR_8197F) & BIT_MASK_BE_QUEUE_THR_8197F)\n#define BIT_SET_BE_QUEUE_THR_8197F(x, v)                                       \\\n\t(BIT_CLEAR_BE_QUEUE_THR_8197F(x) | BIT_BE_QUEUE_THR_8197F(v))\n\n#define BIT_SHIFT_VI_QUEUE_THR_8197F 8\n#define BIT_MASK_VI_QUEUE_THR_8197F 0xff\n#define BIT_VI_QUEUE_THR_8197F(x)                                              \\\n\t(((x) & BIT_MASK_VI_QUEUE_THR_8197F) << BIT_SHIFT_VI_QUEUE_THR_8197F)\n#define BITS_VI_QUEUE_THR_8197F                                                \\\n\t(BIT_MASK_VI_QUEUE_THR_8197F << BIT_SHIFT_VI_QUEUE_THR_8197F)\n#define BIT_CLEAR_VI_QUEUE_THR_8197F(x) ((x) & (~BITS_VI_QUEUE_THR_8197F))\n#define BIT_GET_VI_QUEUE_THR_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_VI_QUEUE_THR_8197F) & BIT_MASK_VI_QUEUE_THR_8197F)\n#define BIT_SET_VI_QUEUE_THR_8197F(x, v)                                       \\\n\t(BIT_CLEAR_VI_QUEUE_THR_8197F(x) | BIT_VI_QUEUE_THR_8197F(v))\n\n#define BIT_SHIFT_VO_QUEUE_THR_8197F 0\n#define BIT_MASK_VO_QUEUE_THR_8197F 0xff\n#define BIT_VO_QUEUE_THR_8197F(x)                                              \\\n\t(((x) & BIT_MASK_VO_QUEUE_THR_8197F) << BIT_SHIFT_VO_QUEUE_THR_8197F)\n#define BITS_VO_QUEUE_THR_8197F                                                \\\n\t(BIT_MASK_VO_QUEUE_THR_8197F << BIT_SHIFT_VO_QUEUE_THR_8197F)\n#define BIT_CLEAR_VO_QUEUE_THR_8197F(x) ((x) & (~BITS_VO_QUEUE_THR_8197F))\n#define BIT_GET_VO_QUEUE_THR_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_VO_QUEUE_THR_8197F) & BIT_MASK_VO_QUEUE_THR_8197F)\n#define BIT_SET_VO_QUEUE_THR_8197F(x, v)                                       \\\n\t(BIT_CLEAR_VO_QUEUE_THR_8197F(x) | BIT_VO_QUEUE_THR_8197F(v))\n\n/* 2 REG_QUEUE_INCOL_EN_8197F */\n#define BIT_QUEUE_INCOL_EN_8197F BIT(16)\n\n#define BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F 12\n#define BIT_MASK_BK_TRIGGER_NUM_V1_8197F 0xf\n#define BIT_BK_TRIGGER_NUM_V1_8197F(x)                                         \\\n\t(((x) & BIT_MASK_BK_TRIGGER_NUM_V1_8197F)                              \\\n\t << BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F)\n#define BITS_BK_TRIGGER_NUM_V1_8197F                                           \\\n\t(BIT_MASK_BK_TRIGGER_NUM_V1_8197F << BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F)\n#define BIT_CLEAR_BK_TRIGGER_NUM_V1_8197F(x)                                   \\\n\t((x) & (~BITS_BK_TRIGGER_NUM_V1_8197F))\n#define BIT_GET_BK_TRIGGER_NUM_V1_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) &                          \\\n\t BIT_MASK_BK_TRIGGER_NUM_V1_8197F)\n#define BIT_SET_BK_TRIGGER_NUM_V1_8197F(x, v)                                  \\\n\t(BIT_CLEAR_BK_TRIGGER_NUM_V1_8197F(x) | BIT_BK_TRIGGER_NUM_V1_8197F(v))\n\n#define BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F 8\n#define BIT_MASK_BE_TRIGGER_NUM_V1_8197F 0xf\n#define BIT_BE_TRIGGER_NUM_V1_8197F(x)                                         \\\n\t(((x) & BIT_MASK_BE_TRIGGER_NUM_V1_8197F)                              \\\n\t << BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F)\n#define BITS_BE_TRIGGER_NUM_V1_8197F                                           \\\n\t(BIT_MASK_BE_TRIGGER_NUM_V1_8197F << BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F)\n#define BIT_CLEAR_BE_TRIGGER_NUM_V1_8197F(x)                                   \\\n\t((x) & (~BITS_BE_TRIGGER_NUM_V1_8197F))\n#define BIT_GET_BE_TRIGGER_NUM_V1_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) &                          \\\n\t BIT_MASK_BE_TRIGGER_NUM_V1_8197F)\n#define BIT_SET_BE_TRIGGER_NUM_V1_8197F(x, v)                                  \\\n\t(BIT_CLEAR_BE_TRIGGER_NUM_V1_8197F(x) | BIT_BE_TRIGGER_NUM_V1_8197F(v))\n\n#define BIT_SHIFT_VI_TRIGGER_NUM_8197F 4\n#define BIT_MASK_VI_TRIGGER_NUM_8197F 0xf\n#define BIT_VI_TRIGGER_NUM_8197F(x)                                            \\\n\t(((x) & BIT_MASK_VI_TRIGGER_NUM_8197F)                                 \\\n\t << BIT_SHIFT_VI_TRIGGER_NUM_8197F)\n#define BITS_VI_TRIGGER_NUM_8197F                                              \\\n\t(BIT_MASK_VI_TRIGGER_NUM_8197F << BIT_SHIFT_VI_TRIGGER_NUM_8197F)\n#define BIT_CLEAR_VI_TRIGGER_NUM_8197F(x) ((x) & (~BITS_VI_TRIGGER_NUM_8197F))\n#define BIT_GET_VI_TRIGGER_NUM_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8197F) &                             \\\n\t BIT_MASK_VI_TRIGGER_NUM_8197F)\n#define BIT_SET_VI_TRIGGER_NUM_8197F(x, v)                                     \\\n\t(BIT_CLEAR_VI_TRIGGER_NUM_8197F(x) | BIT_VI_TRIGGER_NUM_8197F(v))\n\n#define BIT_SHIFT_VO_TRIGGER_NUM_8197F 0\n#define BIT_MASK_VO_TRIGGER_NUM_8197F 0xf\n#define BIT_VO_TRIGGER_NUM_8197F(x)                                            \\\n\t(((x) & BIT_MASK_VO_TRIGGER_NUM_8197F)                                 \\\n\t << BIT_SHIFT_VO_TRIGGER_NUM_8197F)\n#define BITS_VO_TRIGGER_NUM_8197F                                              \\\n\t(BIT_MASK_VO_TRIGGER_NUM_8197F << BIT_SHIFT_VO_TRIGGER_NUM_8197F)\n#define BIT_CLEAR_VO_TRIGGER_NUM_8197F(x) ((x) & (~BITS_VO_TRIGGER_NUM_8197F))\n#define BIT_GET_VO_TRIGGER_NUM_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8197F) &                             \\\n\t BIT_MASK_VO_TRIGGER_NUM_8197F)\n#define BIT_SET_VO_TRIGGER_NUM_8197F(x, v)                                     \\\n\t(BIT_CLEAR_VO_TRIGGER_NUM_8197F(x) | BIT_VO_TRIGGER_NUM_8197F(v))\n\n/* 2 REG_TBTT_PROHIBIT_8197F */\n\n#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F 8\n#define BIT_MASK_TBTT_HOLD_TIME_AP_8197F 0xfff\n#define BIT_TBTT_HOLD_TIME_AP_8197F(x)                                         \\\n\t(((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8197F)                              \\\n\t << BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F)\n#define BITS_TBTT_HOLD_TIME_AP_8197F                                           \\\n\t(BIT_MASK_TBTT_HOLD_TIME_AP_8197F << BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F)\n#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8197F(x)                                   \\\n\t((x) & (~BITS_TBTT_HOLD_TIME_AP_8197F))\n#define BIT_GET_TBTT_HOLD_TIME_AP_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) &                          \\\n\t BIT_MASK_TBTT_HOLD_TIME_AP_8197F)\n#define BIT_SET_TBTT_HOLD_TIME_AP_8197F(x, v)                                  \\\n\t(BIT_CLEAR_TBTT_HOLD_TIME_AP_8197F(x) | BIT_TBTT_HOLD_TIME_AP_8197F(v))\n\n#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F 0\n#define BIT_MASK_TBTT_PROHIBIT_SETUP_8197F 0xf\n#define BIT_TBTT_PROHIBIT_SETUP_8197F(x)                                       \\\n\t(((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8197F)                            \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F)\n#define BITS_TBTT_PROHIBIT_SETUP_8197F                                         \\\n\t(BIT_MASK_TBTT_PROHIBIT_SETUP_8197F                                    \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F)\n#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8197F(x)                                 \\\n\t((x) & (~BITS_TBTT_PROHIBIT_SETUP_8197F))\n#define BIT_GET_TBTT_PROHIBIT_SETUP_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) &                        \\\n\t BIT_MASK_TBTT_PROHIBIT_SETUP_8197F)\n#define BIT_SET_TBTT_PROHIBIT_SETUP_8197F(x, v)                                \\\n\t(BIT_CLEAR_TBTT_PROHIBIT_SETUP_8197F(x) |                              \\\n\t BIT_TBTT_PROHIBIT_SETUP_8197F(v))\n\n/* 2 REG_P2PPS_STATE_8197F */\n#define BIT_POWER_STATE_8197F BIT(7)\n#define BIT_CTWINDOW_ON_8197F BIT(6)\n#define BIT_BEACON_AREA_ON_8197F BIT(5)\n#define BIT_CTWIN_EARLY_DISTX_8197F BIT(4)\n#define BIT_NOA1_OFF_PERIOD_8197F BIT(3)\n#define BIT_FORCE_DOZE1_8197F BIT(2)\n#define BIT_NOA0_OFF_PERIOD_8197F BIT(1)\n#define BIT_FORCE_DOZE0_8197F BIT(0)\n\n/* 2 REG_RD_NAV_NXT_8197F */\n\n#define BIT_SHIFT_RD_NAV_PROT_NXT_8197F 0\n#define BIT_MASK_RD_NAV_PROT_NXT_8197F 0xffff\n#define BIT_RD_NAV_PROT_NXT_8197F(x)                                           \\\n\t(((x) & BIT_MASK_RD_NAV_PROT_NXT_8197F)                                \\\n\t << BIT_SHIFT_RD_NAV_PROT_NXT_8197F)\n#define BITS_RD_NAV_PROT_NXT_8197F                                             \\\n\t(BIT_MASK_RD_NAV_PROT_NXT_8197F << BIT_SHIFT_RD_NAV_PROT_NXT_8197F)\n#define BIT_CLEAR_RD_NAV_PROT_NXT_8197F(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8197F))\n#define BIT_GET_RD_NAV_PROT_NXT_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8197F) &                            \\\n\t BIT_MASK_RD_NAV_PROT_NXT_8197F)\n#define BIT_SET_RD_NAV_PROT_NXT_8197F(x, v)                                    \\\n\t(BIT_CLEAR_RD_NAV_PROT_NXT_8197F(x) | BIT_RD_NAV_PROT_NXT_8197F(v))\n\n/* 2 REG_NAV_PROT_LEN_8197F */\n\n#define BIT_SHIFT_NAV_PROT_LEN_8197F 0\n#define BIT_MASK_NAV_PROT_LEN_8197F 0xffff\n#define BIT_NAV_PROT_LEN_8197F(x)                                              \\\n\t(((x) & BIT_MASK_NAV_PROT_LEN_8197F) << BIT_SHIFT_NAV_PROT_LEN_8197F)\n#define BITS_NAV_PROT_LEN_8197F                                                \\\n\t(BIT_MASK_NAV_PROT_LEN_8197F << BIT_SHIFT_NAV_PROT_LEN_8197F)\n#define BIT_CLEAR_NAV_PROT_LEN_8197F(x) ((x) & (~BITS_NAV_PROT_LEN_8197F))\n#define BIT_GET_NAV_PROT_LEN_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_NAV_PROT_LEN_8197F) & BIT_MASK_NAV_PROT_LEN_8197F)\n#define BIT_SET_NAV_PROT_LEN_8197F(x, v)                                       \\\n\t(BIT_CLEAR_NAV_PROT_LEN_8197F(x) | BIT_NAV_PROT_LEN_8197F(v))\n\n/* 2 REG_FTM_CTRL_8197F */\n\n#define BIT_SHIFT_FTM_TSF_R2T_PORT_8197F 22\n#define BIT_MASK_FTM_TSF_R2T_PORT_8197F 0x7\n#define BIT_FTM_TSF_R2T_PORT_8197F(x)                                          \\\n\t(((x) & BIT_MASK_FTM_TSF_R2T_PORT_8197F)                               \\\n\t << BIT_SHIFT_FTM_TSF_R2T_PORT_8197F)\n#define BITS_FTM_TSF_R2T_PORT_8197F                                            \\\n\t(BIT_MASK_FTM_TSF_R2T_PORT_8197F << BIT_SHIFT_FTM_TSF_R2T_PORT_8197F)\n#define BIT_CLEAR_FTM_TSF_R2T_PORT_8197F(x)                                    \\\n\t((x) & (~BITS_FTM_TSF_R2T_PORT_8197F))\n#define BIT_GET_FTM_TSF_R2T_PORT_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) &                           \\\n\t BIT_MASK_FTM_TSF_R2T_PORT_8197F)\n#define BIT_SET_FTM_TSF_R2T_PORT_8197F(x, v)                                   \\\n\t(BIT_CLEAR_FTM_TSF_R2T_PORT_8197F(x) | BIT_FTM_TSF_R2T_PORT_8197F(v))\n\n#define BIT_SHIFT_FTM_TSF_T2R_PORT_8197F 19\n#define BIT_MASK_FTM_TSF_T2R_PORT_8197F 0x7\n#define BIT_FTM_TSF_T2R_PORT_8197F(x)                                          \\\n\t(((x) & BIT_MASK_FTM_TSF_T2R_PORT_8197F)                               \\\n\t << BIT_SHIFT_FTM_TSF_T2R_PORT_8197F)\n#define BITS_FTM_TSF_T2R_PORT_8197F                                            \\\n\t(BIT_MASK_FTM_TSF_T2R_PORT_8197F << BIT_SHIFT_FTM_TSF_T2R_PORT_8197F)\n#define BIT_CLEAR_FTM_TSF_T2R_PORT_8197F(x)                                    \\\n\t((x) & (~BITS_FTM_TSF_T2R_PORT_8197F))\n#define BIT_GET_FTM_TSF_T2R_PORT_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) &                           \\\n\t BIT_MASK_FTM_TSF_T2R_PORT_8197F)\n#define BIT_SET_FTM_TSF_T2R_PORT_8197F(x, v)                                   \\\n\t(BIT_CLEAR_FTM_TSF_T2R_PORT_8197F(x) | BIT_FTM_TSF_T2R_PORT_8197F(v))\n\n#define BIT_SHIFT_FTM_PTT_PORT_8197F 16\n#define BIT_MASK_FTM_PTT_PORT_8197F 0x7\n#define BIT_FTM_PTT_PORT_8197F(x)                                              \\\n\t(((x) & BIT_MASK_FTM_PTT_PORT_8197F) << BIT_SHIFT_FTM_PTT_PORT_8197F)\n#define BITS_FTM_PTT_PORT_8197F                                                \\\n\t(BIT_MASK_FTM_PTT_PORT_8197F << BIT_SHIFT_FTM_PTT_PORT_8197F)\n#define BIT_CLEAR_FTM_PTT_PORT_8197F(x) ((x) & (~BITS_FTM_PTT_PORT_8197F))\n#define BIT_GET_FTM_PTT_PORT_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_FTM_PTT_PORT_8197F) & BIT_MASK_FTM_PTT_PORT_8197F)\n#define BIT_SET_FTM_PTT_PORT_8197F(x, v)                                       \\\n\t(BIT_CLEAR_FTM_PTT_PORT_8197F(x) | BIT_FTM_PTT_PORT_8197F(v))\n\n#define BIT_SHIFT_FTM_PTT_8197F 0\n#define BIT_MASK_FTM_PTT_8197F 0xffff\n#define BIT_FTM_PTT_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_FTM_PTT_8197F) << BIT_SHIFT_FTM_PTT_8197F)\n#define BITS_FTM_PTT_8197F (BIT_MASK_FTM_PTT_8197F << BIT_SHIFT_FTM_PTT_8197F)\n#define BIT_CLEAR_FTM_PTT_8197F(x) ((x) & (~BITS_FTM_PTT_8197F))\n#define BIT_GET_FTM_PTT_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_FTM_PTT_8197F) & BIT_MASK_FTM_PTT_8197F)\n#define BIT_SET_FTM_PTT_8197F(x, v)                                            \\\n\t(BIT_CLEAR_FTM_PTT_8197F(x) | BIT_FTM_PTT_8197F(v))\n\n/* 2 REG_FTM_TSF_CNT_8197F */\n\n#define BIT_SHIFT_FTM_TSF_R2T_8197F 16\n#define BIT_MASK_FTM_TSF_R2T_8197F 0xffff\n#define BIT_FTM_TSF_R2T_8197F(x)                                               \\\n\t(((x) & BIT_MASK_FTM_TSF_R2T_8197F) << BIT_SHIFT_FTM_TSF_R2T_8197F)\n#define BITS_FTM_TSF_R2T_8197F                                                 \\\n\t(BIT_MASK_FTM_TSF_R2T_8197F << BIT_SHIFT_FTM_TSF_R2T_8197F)\n#define BIT_CLEAR_FTM_TSF_R2T_8197F(x) ((x) & (~BITS_FTM_TSF_R2T_8197F))\n#define BIT_GET_FTM_TSF_R2T_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_FTM_TSF_R2T_8197F) & BIT_MASK_FTM_TSF_R2T_8197F)\n#define BIT_SET_FTM_TSF_R2T_8197F(x, v)                                        \\\n\t(BIT_CLEAR_FTM_TSF_R2T_8197F(x) | BIT_FTM_TSF_R2T_8197F(v))\n\n#define BIT_SHIFT_FTM_TSF_T2R_8197F 0\n#define BIT_MASK_FTM_TSF_T2R_8197F 0xffff\n#define BIT_FTM_TSF_T2R_8197F(x)                                               \\\n\t(((x) & BIT_MASK_FTM_TSF_T2R_8197F) << BIT_SHIFT_FTM_TSF_T2R_8197F)\n#define BITS_FTM_TSF_T2R_8197F                                                 \\\n\t(BIT_MASK_FTM_TSF_T2R_8197F << BIT_SHIFT_FTM_TSF_T2R_8197F)\n#define BIT_CLEAR_FTM_TSF_T2R_8197F(x) ((x) & (~BITS_FTM_TSF_T2R_8197F))\n#define BIT_GET_FTM_TSF_T2R_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_FTM_TSF_T2R_8197F) & BIT_MASK_FTM_TSF_T2R_8197F)\n#define BIT_SET_FTM_TSF_T2R_8197F(x, v)                                        \\\n\t(BIT_CLEAR_FTM_TSF_T2R_8197F(x) | BIT_FTM_TSF_T2R_8197F(v))\n\n/* 2 REG_BCN_CTRL_8197F */\n#define BIT_DIS_RX_BSSID_FIT_8197F BIT(6)\n#define BIT_P0_EN_TXBCN_RPT_8197F BIT(5)\n#define BIT_DIS_TSF_UDT_8197F BIT(4)\n#define BIT_EN_BCN_FUNCTION_8197F BIT(3)\n#define BIT_P0_EN_RXBCN_RPT_8197F BIT(2)\n#define BIT_EN_P2P_CTWINDOW_8197F BIT(1)\n#define BIT_EN_P2P_BCNQ_AREA_8197F BIT(0)\n\n/* 2 REG_BCN_CTRL_CLINT0_8197F */\n#define BIT_CLI0_DIS_RX_BSSID_FIT_8197F BIT(6)\n#define BIT_CLI0_DIS_TSF_UDT_8197F BIT(4)\n#define BIT_CLI0_EN_BCN_FUNCTION_8197F BIT(3)\n#define BIT_CLI0_EN_RXBCN_RPT_8197F BIT(2)\n#define BIT_CLI0_ENP2P_CTWINDOW_8197F BIT(1)\n#define BIT_CLI0_ENP2P_BCNQ_AREA_8197F BIT(0)\n\n/* 2 REG_MBID_NUM_8197F */\n#define BIT_EN_PRE_DL_BEACON_8197F BIT(3)\n\n#define BIT_SHIFT_MBID_BCN_NUM_8197F 0\n#define BIT_MASK_MBID_BCN_NUM_8197F 0x7\n#define BIT_MBID_BCN_NUM_8197F(x)                                              \\\n\t(((x) & BIT_MASK_MBID_BCN_NUM_8197F) << BIT_SHIFT_MBID_BCN_NUM_8197F)\n#define BITS_MBID_BCN_NUM_8197F                                                \\\n\t(BIT_MASK_MBID_BCN_NUM_8197F << BIT_SHIFT_MBID_BCN_NUM_8197F)\n#define BIT_CLEAR_MBID_BCN_NUM_8197F(x) ((x) & (~BITS_MBID_BCN_NUM_8197F))\n#define BIT_GET_MBID_BCN_NUM_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_MBID_BCN_NUM_8197F) & BIT_MASK_MBID_BCN_NUM_8197F)\n#define BIT_SET_MBID_BCN_NUM_8197F(x, v)                                       \\\n\t(BIT_CLEAR_MBID_BCN_NUM_8197F(x) | BIT_MBID_BCN_NUM_8197F(v))\n\n/* 2 REG_DUAL_TSF_RST_8197F */\n#define BIT_FREECNT_RST_8197F BIT(5)\n#define BIT_TSFTR_CLI3_RST_8197F BIT(4)\n#define BIT_TSFTR_CLI2_RST_8197F BIT(3)\n#define BIT_TSFTR_CLI1_RST_8197F BIT(2)\n#define BIT_TSFTR_CLI0_RST_8197F BIT(1)\n#define BIT_TSFTR_RST_8197F BIT(0)\n\n/* 2 REG_MBSSID_BCN_SPACE_8197F */\n\n#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F 28\n#define BIT_MASK_BCN_TIMER_SEL_FWRD_8197F 0x7\n#define BIT_BCN_TIMER_SEL_FWRD_8197F(x)                                        \\\n\t(((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8197F)                             \\\n\t << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F)\n#define BITS_BCN_TIMER_SEL_FWRD_8197F                                          \\\n\t(BIT_MASK_BCN_TIMER_SEL_FWRD_8197F                                     \\\n\t << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F)\n#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8197F(x)                                  \\\n\t((x) & (~BITS_BCN_TIMER_SEL_FWRD_8197F))\n#define BIT_GET_BCN_TIMER_SEL_FWRD_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) &                         \\\n\t BIT_MASK_BCN_TIMER_SEL_FWRD_8197F)\n#define BIT_SET_BCN_TIMER_SEL_FWRD_8197F(x, v)                                 \\\n\t(BIT_CLEAR_BCN_TIMER_SEL_FWRD_8197F(x) |                               \\\n\t BIT_BCN_TIMER_SEL_FWRD_8197F(v))\n\n#define BIT_SHIFT_BCN_SPACE_CLINT0_8197F 16\n#define BIT_MASK_BCN_SPACE_CLINT0_8197F 0xfff\n#define BIT_BCN_SPACE_CLINT0_8197F(x)                                          \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT0_8197F)                               \\\n\t << BIT_SHIFT_BCN_SPACE_CLINT0_8197F)\n#define BITS_BCN_SPACE_CLINT0_8197F                                            \\\n\t(BIT_MASK_BCN_SPACE_CLINT0_8197F << BIT_SHIFT_BCN_SPACE_CLINT0_8197F)\n#define BIT_CLEAR_BCN_SPACE_CLINT0_8197F(x)                                    \\\n\t((x) & (~BITS_BCN_SPACE_CLINT0_8197F))\n#define BIT_GET_BCN_SPACE_CLINT0_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8197F) &                           \\\n\t BIT_MASK_BCN_SPACE_CLINT0_8197F)\n#define BIT_SET_BCN_SPACE_CLINT0_8197F(x, v)                                   \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT0_8197F(x) | BIT_BCN_SPACE_CLINT0_8197F(v))\n\n#define BIT_SHIFT_BCN_SPACE0_8197F 0\n#define BIT_MASK_BCN_SPACE0_8197F 0xffff\n#define BIT_BCN_SPACE0_8197F(x)                                                \\\n\t(((x) & BIT_MASK_BCN_SPACE0_8197F) << BIT_SHIFT_BCN_SPACE0_8197F)\n#define BITS_BCN_SPACE0_8197F                                                  \\\n\t(BIT_MASK_BCN_SPACE0_8197F << BIT_SHIFT_BCN_SPACE0_8197F)\n#define BIT_CLEAR_BCN_SPACE0_8197F(x) ((x) & (~BITS_BCN_SPACE0_8197F))\n#define BIT_GET_BCN_SPACE0_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE0_8197F) & BIT_MASK_BCN_SPACE0_8197F)\n#define BIT_SET_BCN_SPACE0_8197F(x, v)                                         \\\n\t(BIT_CLEAR_BCN_SPACE0_8197F(x) | BIT_BCN_SPACE0_8197F(v))\n\n/* 2 REG_DRVERLYINT_8197F */\n\n#define BIT_SHIFT_DRVERLYITV_8197F 0\n#define BIT_MASK_DRVERLYITV_8197F 0xff\n#define BIT_DRVERLYITV_8197F(x)                                                \\\n\t(((x) & BIT_MASK_DRVERLYITV_8197F) << BIT_SHIFT_DRVERLYITV_8197F)\n#define BITS_DRVERLYITV_8197F                                                  \\\n\t(BIT_MASK_DRVERLYITV_8197F << BIT_SHIFT_DRVERLYITV_8197F)\n#define BIT_CLEAR_DRVERLYITV_8197F(x) ((x) & (~BITS_DRVERLYITV_8197F))\n#define BIT_GET_DRVERLYITV_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_DRVERLYITV_8197F) & BIT_MASK_DRVERLYITV_8197F)\n#define BIT_SET_DRVERLYITV_8197F(x, v)                                         \\\n\t(BIT_CLEAR_DRVERLYITV_8197F(x) | BIT_DRVERLYITV_8197F(v))\n\n/* 2 REG_BCNDMATIM_8197F */\n\n#define BIT_SHIFT_BCNDMATIM_8197F 0\n#define BIT_MASK_BCNDMATIM_8197F 0xff\n#define BIT_BCNDMATIM_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_BCNDMATIM_8197F) << BIT_SHIFT_BCNDMATIM_8197F)\n#define BITS_BCNDMATIM_8197F                                                   \\\n\t(BIT_MASK_BCNDMATIM_8197F << BIT_SHIFT_BCNDMATIM_8197F)\n#define BIT_CLEAR_BCNDMATIM_8197F(x) ((x) & (~BITS_BCNDMATIM_8197F))\n#define BIT_GET_BCNDMATIM_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNDMATIM_8197F) & BIT_MASK_BCNDMATIM_8197F)\n#define BIT_SET_BCNDMATIM_8197F(x, v)                                          \\\n\t(BIT_CLEAR_BCNDMATIM_8197F(x) | BIT_BCNDMATIM_8197F(v))\n\n/* 2 REG_ATIMWND_8197F */\n\n#define BIT_SHIFT_ATIMWND0_8197F 0\n#define BIT_MASK_ATIMWND0_8197F 0xffff\n#define BIT_ATIMWND0_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND0_8197F) << BIT_SHIFT_ATIMWND0_8197F)\n#define BITS_ATIMWND0_8197F                                                    \\\n\t(BIT_MASK_ATIMWND0_8197F << BIT_SHIFT_ATIMWND0_8197F)\n#define BIT_CLEAR_ATIMWND0_8197F(x) ((x) & (~BITS_ATIMWND0_8197F))\n#define BIT_GET_ATIMWND0_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND0_8197F) & BIT_MASK_ATIMWND0_8197F)\n#define BIT_SET_ATIMWND0_8197F(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND0_8197F(x) | BIT_ATIMWND0_8197F(v))\n\n/* 2 REG_USTIME_TSF_8197F */\n\n#define BIT_SHIFT_USTIME_TSF_V1_8197F 0\n#define BIT_MASK_USTIME_TSF_V1_8197F 0xff\n#define BIT_USTIME_TSF_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_USTIME_TSF_V1_8197F) << BIT_SHIFT_USTIME_TSF_V1_8197F)\n#define BITS_USTIME_TSF_V1_8197F                                               \\\n\t(BIT_MASK_USTIME_TSF_V1_8197F << BIT_SHIFT_USTIME_TSF_V1_8197F)\n#define BIT_CLEAR_USTIME_TSF_V1_8197F(x) ((x) & (~BITS_USTIME_TSF_V1_8197F))\n#define BIT_GET_USTIME_TSF_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_USTIME_TSF_V1_8197F) & BIT_MASK_USTIME_TSF_V1_8197F)\n#define BIT_SET_USTIME_TSF_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_USTIME_TSF_V1_8197F(x) | BIT_USTIME_TSF_V1_8197F(v))\n\n/* 2 REG_BCN_MAX_ERR_8197F */\n\n#define BIT_SHIFT_BCN_MAX_ERR_8197F 0\n#define BIT_MASK_BCN_MAX_ERR_8197F 0xff\n#define BIT_BCN_MAX_ERR_8197F(x)                                               \\\n\t(((x) & BIT_MASK_BCN_MAX_ERR_8197F) << BIT_SHIFT_BCN_MAX_ERR_8197F)\n#define BITS_BCN_MAX_ERR_8197F                                                 \\\n\t(BIT_MASK_BCN_MAX_ERR_8197F << BIT_SHIFT_BCN_MAX_ERR_8197F)\n#define BIT_CLEAR_BCN_MAX_ERR_8197F(x) ((x) & (~BITS_BCN_MAX_ERR_8197F))\n#define BIT_GET_BCN_MAX_ERR_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_BCN_MAX_ERR_8197F) & BIT_MASK_BCN_MAX_ERR_8197F)\n#define BIT_SET_BCN_MAX_ERR_8197F(x, v)                                        \\\n\t(BIT_CLEAR_BCN_MAX_ERR_8197F(x) | BIT_BCN_MAX_ERR_8197F(v))\n\n/* 2 REG_RXTSF_OFFSET_CCK_8197F */\n\n#define BIT_SHIFT_CCK_RXTSF_OFFSET_8197F 0\n#define BIT_MASK_CCK_RXTSF_OFFSET_8197F 0xff\n#define BIT_CCK_RXTSF_OFFSET_8197F(x)                                          \\\n\t(((x) & BIT_MASK_CCK_RXTSF_OFFSET_8197F)                               \\\n\t << BIT_SHIFT_CCK_RXTSF_OFFSET_8197F)\n#define BITS_CCK_RXTSF_OFFSET_8197F                                            \\\n\t(BIT_MASK_CCK_RXTSF_OFFSET_8197F << BIT_SHIFT_CCK_RXTSF_OFFSET_8197F)\n#define BIT_CLEAR_CCK_RXTSF_OFFSET_8197F(x)                                    \\\n\t((x) & (~BITS_CCK_RXTSF_OFFSET_8197F))\n#define BIT_GET_CCK_RXTSF_OFFSET_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) &                           \\\n\t BIT_MASK_CCK_RXTSF_OFFSET_8197F)\n#define BIT_SET_CCK_RXTSF_OFFSET_8197F(x, v)                                   \\\n\t(BIT_CLEAR_CCK_RXTSF_OFFSET_8197F(x) | BIT_CCK_RXTSF_OFFSET_8197F(v))\n\n/* 2 REG_RXTSF_OFFSET_OFDM_8197F */\n\n#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F 0\n#define BIT_MASK_OFDM_RXTSF_OFFSET_8197F 0xff\n#define BIT_OFDM_RXTSF_OFFSET_8197F(x)                                         \\\n\t(((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8197F)                              \\\n\t << BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F)\n#define BITS_OFDM_RXTSF_OFFSET_8197F                                           \\\n\t(BIT_MASK_OFDM_RXTSF_OFFSET_8197F << BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F)\n#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8197F(x)                                   \\\n\t((x) & (~BITS_OFDM_RXTSF_OFFSET_8197F))\n#define BIT_GET_OFDM_RXTSF_OFFSET_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) &                          \\\n\t BIT_MASK_OFDM_RXTSF_OFFSET_8197F)\n#define BIT_SET_OFDM_RXTSF_OFFSET_8197F(x, v)                                  \\\n\t(BIT_CLEAR_OFDM_RXTSF_OFFSET_8197F(x) | BIT_OFDM_RXTSF_OFFSET_8197F(v))\n\n/* 2 REG_TSFTR_8197F */\n\n#define BIT_SHIFT_TSF_TIMER_8197F 0\n#define BIT_MASK_TSF_TIMER_8197F 0xffffffffffffffffL\n#define BIT_TSF_TIMER_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_TSF_TIMER_8197F) << BIT_SHIFT_TSF_TIMER_8197F)\n#define BITS_TSF_TIMER_8197F                                                   \\\n\t(BIT_MASK_TSF_TIMER_8197F << BIT_SHIFT_TSF_TIMER_8197F)\n#define BIT_CLEAR_TSF_TIMER_8197F(x) ((x) & (~BITS_TSF_TIMER_8197F))\n#define BIT_GET_TSF_TIMER_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_TSF_TIMER_8197F) & BIT_MASK_TSF_TIMER_8197F)\n#define BIT_SET_TSF_TIMER_8197F(x, v)                                          \\\n\t(BIT_CLEAR_TSF_TIMER_8197F(x) | BIT_TSF_TIMER_8197F(v))\n\n/* 2 REG_FREERUN_CNT_8197F */\n\n#define BIT_SHIFT_FREERUN_CNT_8197F 0\n#define BIT_MASK_FREERUN_CNT_8197F 0xffffffffffffffffL\n#define BIT_FREERUN_CNT_8197F(x)                                               \\\n\t(((x) & BIT_MASK_FREERUN_CNT_8197F) << BIT_SHIFT_FREERUN_CNT_8197F)\n#define BITS_FREERUN_CNT_8197F                                                 \\\n\t(BIT_MASK_FREERUN_CNT_8197F << BIT_SHIFT_FREERUN_CNT_8197F)\n#define BIT_CLEAR_FREERUN_CNT_8197F(x) ((x) & (~BITS_FREERUN_CNT_8197F))\n#define BIT_GET_FREERUN_CNT_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_FREERUN_CNT_8197F) & BIT_MASK_FREERUN_CNT_8197F)\n#define BIT_SET_FREERUN_CNT_8197F(x, v)                                        \\\n\t(BIT_CLEAR_FREERUN_CNT_8197F(x) | BIT_FREERUN_CNT_8197F(v))\n\n/* 2 REG_ATIMWND1_8197F */\n\n#define BIT_SHIFT_ATIMWND1_V1_8197F 0\n#define BIT_MASK_ATIMWND1_V1_8197F 0xff\n#define BIT_ATIMWND1_V1_8197F(x)                                               \\\n\t(((x) & BIT_MASK_ATIMWND1_V1_8197F) << BIT_SHIFT_ATIMWND1_V1_8197F)\n#define BITS_ATIMWND1_V1_8197F                                                 \\\n\t(BIT_MASK_ATIMWND1_V1_8197F << BIT_SHIFT_ATIMWND1_V1_8197F)\n#define BIT_CLEAR_ATIMWND1_V1_8197F(x) ((x) & (~BITS_ATIMWND1_V1_8197F))\n#define BIT_GET_ATIMWND1_V1_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_ATIMWND1_V1_8197F) & BIT_MASK_ATIMWND1_V1_8197F)\n#define BIT_SET_ATIMWND1_V1_8197F(x, v)                                        \\\n\t(BIT_CLEAR_ATIMWND1_V1_8197F(x) | BIT_ATIMWND1_V1_8197F(v))\n\n/* 2 REG_TBTT_PROHIBIT_INFRA_8197F */\n\n#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F 0\n#define BIT_MASK_TBTT_PROHIBIT_INFRA_8197F 0xff\n#define BIT_TBTT_PROHIBIT_INFRA_8197F(x)                                       \\\n\t(((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8197F)                            \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F)\n#define BITS_TBTT_PROHIBIT_INFRA_8197F                                         \\\n\t(BIT_MASK_TBTT_PROHIBIT_INFRA_8197F                                    \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F)\n#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8197F(x)                                 \\\n\t((x) & (~BITS_TBTT_PROHIBIT_INFRA_8197F))\n#define BIT_GET_TBTT_PROHIBIT_INFRA_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) &                        \\\n\t BIT_MASK_TBTT_PROHIBIT_INFRA_8197F)\n#define BIT_SET_TBTT_PROHIBIT_INFRA_8197F(x, v)                                \\\n\t(BIT_CLEAR_TBTT_PROHIBIT_INFRA_8197F(x) |                              \\\n\t BIT_TBTT_PROHIBIT_INFRA_8197F(v))\n\n/* 2 REG_CTWND_8197F */\n\n#define BIT_SHIFT_CTWND_8197F 0\n#define BIT_MASK_CTWND_8197F 0xff\n#define BIT_CTWND_8197F(x)                                                     \\\n\t(((x) & BIT_MASK_CTWND_8197F) << BIT_SHIFT_CTWND_8197F)\n#define BITS_CTWND_8197F (BIT_MASK_CTWND_8197F << BIT_SHIFT_CTWND_8197F)\n#define BIT_CLEAR_CTWND_8197F(x) ((x) & (~BITS_CTWND_8197F))\n#define BIT_GET_CTWND_8197F(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CTWND_8197F) & BIT_MASK_CTWND_8197F)\n#define BIT_SET_CTWND_8197F(x, v)                                              \\\n\t(BIT_CLEAR_CTWND_8197F(x) | BIT_CTWND_8197F(v))\n\n/* 2 REG_BCNIVLCUNT_8197F */\n\n#define BIT_SHIFT_BCNIVLCUNT_8197F 0\n#define BIT_MASK_BCNIVLCUNT_8197F 0x7f\n#define BIT_BCNIVLCUNT_8197F(x)                                                \\\n\t(((x) & BIT_MASK_BCNIVLCUNT_8197F) << BIT_SHIFT_BCNIVLCUNT_8197F)\n#define BITS_BCNIVLCUNT_8197F                                                  \\\n\t(BIT_MASK_BCNIVLCUNT_8197F << BIT_SHIFT_BCNIVLCUNT_8197F)\n#define BIT_CLEAR_BCNIVLCUNT_8197F(x) ((x) & (~BITS_BCNIVLCUNT_8197F))\n#define BIT_GET_BCNIVLCUNT_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_BCNIVLCUNT_8197F) & BIT_MASK_BCNIVLCUNT_8197F)\n#define BIT_SET_BCNIVLCUNT_8197F(x, v)                                         \\\n\t(BIT_CLEAR_BCNIVLCUNT_8197F(x) | BIT_BCNIVLCUNT_8197F(v))\n\n/* 2 REG_BCNDROPCTRL_8197F */\n#define BIT_BEACON_DROP_EN_8197F BIT(7)\n\n#define BIT_SHIFT_BEACON_DROP_IVL_8197F 0\n#define BIT_MASK_BEACON_DROP_IVL_8197F 0x7f\n#define BIT_BEACON_DROP_IVL_8197F(x)                                           \\\n\t(((x) & BIT_MASK_BEACON_DROP_IVL_8197F)                                \\\n\t << BIT_SHIFT_BEACON_DROP_IVL_8197F)\n#define BITS_BEACON_DROP_IVL_8197F                                             \\\n\t(BIT_MASK_BEACON_DROP_IVL_8197F << BIT_SHIFT_BEACON_DROP_IVL_8197F)\n#define BIT_CLEAR_BEACON_DROP_IVL_8197F(x) ((x) & (~BITS_BEACON_DROP_IVL_8197F))\n#define BIT_GET_BEACON_DROP_IVL_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_BEACON_DROP_IVL_8197F) &                            \\\n\t BIT_MASK_BEACON_DROP_IVL_8197F)\n#define BIT_SET_BEACON_DROP_IVL_8197F(x, v)                                    \\\n\t(BIT_CLEAR_BEACON_DROP_IVL_8197F(x) | BIT_BEACON_DROP_IVL_8197F(v))\n\n/* 2 REG_HGQ_TIMEOUT_PERIOD_8197F */\n\n#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F 0\n#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F 0xff\n#define BIT_HGQ_TIMEOUT_PERIOD_8197F(x)                                        \\\n\t(((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F)                             \\\n\t << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F)\n#define BITS_HGQ_TIMEOUT_PERIOD_8197F                                          \\\n\t(BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F                                     \\\n\t << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F)\n#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8197F(x)                                  \\\n\t((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8197F))\n#define BIT_GET_HGQ_TIMEOUT_PERIOD_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) &                         \\\n\t BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F)\n#define BIT_SET_HGQ_TIMEOUT_PERIOD_8197F(x, v)                                 \\\n\t(BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8197F(x) |                               \\\n\t BIT_HGQ_TIMEOUT_PERIOD_8197F(v))\n\n/* 2 REG_TXCMD_TIMEOUT_PERIOD_8197F */\n\n#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F 0\n#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F 0xff\n#define BIT_TXCMD_TIMEOUT_PERIOD_8197F(x)                                      \\\n\t(((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F)                           \\\n\t << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F)\n#define BITS_TXCMD_TIMEOUT_PERIOD_8197F                                        \\\n\t(BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F                                   \\\n\t << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F)\n#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8197F(x)                                \\\n\t((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8197F))\n#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8197F(x)                                  \\\n\t(((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) &                       \\\n\t BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F)\n#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8197F(x, v)                               \\\n\t(BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8197F(x) |                             \\\n\t BIT_TXCMD_TIMEOUT_PERIOD_8197F(v))\n\n/* 2 REG_MISC_CTRL_8197F */\n#define BIT_DIS_MARK_TSF_US_8197F BIT(7)\n#define BIT_EN_TSFAUTO_SYNC_8197F BIT(6)\n#define BIT_DIS_TRX_CAL_BCN_8197F BIT(5)\n#define BIT_DIS_TX_CAL_TBTT_8197F BIT(4)\n#define BIT_EN_FREECNT_8197F BIT(3)\n#define BIT_BCN_AGGRESSION_8197F BIT(2)\n\n#define BIT_SHIFT_DIS_SECONDARY_CCA_8197F 0\n#define BIT_MASK_DIS_SECONDARY_CCA_8197F 0x3\n#define BIT_DIS_SECONDARY_CCA_8197F(x)                                         \\\n\t(((x) & BIT_MASK_DIS_SECONDARY_CCA_8197F)                              \\\n\t << BIT_SHIFT_DIS_SECONDARY_CCA_8197F)\n#define BITS_DIS_SECONDARY_CCA_8197F                                           \\\n\t(BIT_MASK_DIS_SECONDARY_CCA_8197F << BIT_SHIFT_DIS_SECONDARY_CCA_8197F)\n#define BIT_CLEAR_DIS_SECONDARY_CCA_8197F(x)                                   \\\n\t((x) & (~BITS_DIS_SECONDARY_CCA_8197F))\n#define BIT_GET_DIS_SECONDARY_CCA_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8197F) &                          \\\n\t BIT_MASK_DIS_SECONDARY_CCA_8197F)\n#define BIT_SET_DIS_SECONDARY_CCA_8197F(x, v)                                  \\\n\t(BIT_CLEAR_DIS_SECONDARY_CCA_8197F(x) | BIT_DIS_SECONDARY_CCA_8197F(v))\n\n/* 2 REG_BCN_CTRL_CLINT1_8197F */\n#define BIT_CLI1_DIS_RX_BSSID_FIT_8197F BIT(6)\n#define BIT_CLI1_DIS_TSF_UDT_8197F BIT(4)\n#define BIT_CLI1_EN_BCN_FUNCTION_8197F BIT(3)\n#define BIT_CLI1_EN_RXBCN_RPT_8197F BIT(2)\n#define BIT_CLI1_ENP2P_CTWINDOW_8197F BIT(1)\n#define BIT_CLI1_ENP2P_BCNQ_AREA_8197F BIT(0)\n\n/* 2 REG_BCN_CTRL_CLINT2_8197F */\n#define BIT_CLI2_DIS_RX_BSSID_FIT_8197F BIT(6)\n#define BIT_CLI2_DIS_TSF_UDT_8197F BIT(4)\n#define BIT_CLI2_EN_BCN_FUNCTION_8197F BIT(3)\n#define BIT_CLI2_EN_RXBCN_RPT_8197F BIT(2)\n#define BIT_CLI2_ENP2P_CTWINDOW_8197F BIT(1)\n#define BIT_CLI2_ENP2P_BCNQ_AREA_8197F BIT(0)\n\n/* 2 REG_BCN_CTRL_CLINT3_8197F */\n#define BIT_CLI3_DIS_RX_BSSID_FIT_8197F BIT(6)\n#define BIT_CLI3_DIS_TSF_UDT_8197F BIT(4)\n#define BIT_CLI3_EN_BCN_FUNCTION_8197F BIT(3)\n#define BIT_CLI3_EN_RXBCN_RPT_8197F BIT(2)\n#define BIT_CLI3_ENP2P_CTWINDOW_8197F BIT(1)\n#define BIT_CLI3_ENP2P_BCNQ_AREA_8197F BIT(0)\n\n/* 2 REG_EXTEND_CTRL_8197F */\n#define BIT_EN_TSFBIT32_RST_P2P2_8197F BIT(5)\n#define BIT_EN_TSFBIT32_RST_P2P1_8197F BIT(4)\n\n#define BIT_SHIFT_PORT_SEL_8197F 0\n#define BIT_MASK_PORT_SEL_8197F 0x7\n#define BIT_PORT_SEL_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_PORT_SEL_8197F) << BIT_SHIFT_PORT_SEL_8197F)\n#define BITS_PORT_SEL_8197F                                                    \\\n\t(BIT_MASK_PORT_SEL_8197F << BIT_SHIFT_PORT_SEL_8197F)\n#define BIT_CLEAR_PORT_SEL_8197F(x) ((x) & (~BITS_PORT_SEL_8197F))\n#define BIT_GET_PORT_SEL_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_PORT_SEL_8197F) & BIT_MASK_PORT_SEL_8197F)\n#define BIT_SET_PORT_SEL_8197F(x, v)                                           \\\n\t(BIT_CLEAR_PORT_SEL_8197F(x) | BIT_PORT_SEL_8197F(v))\n\n/* 2 REG_P2PPS1_SPEC_STATE_8197F */\n#define BIT_P2P1_SPEC_POWER_STATE_8197F BIT(7)\n#define BIT_P2P1_SPEC_CTWINDOW_ON_8197F BIT(6)\n#define BIT_P2P1_SPEC_BCN_AREA_ON_8197F BIT(5)\n#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8197F BIT(4)\n#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8197F BIT(3)\n#define BIT_P2P1_SPEC_FORCE_DOZE1_8197F BIT(2)\n#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8197F BIT(1)\n#define BIT_P2P1_SPEC_FORCE_DOZE0_8197F BIT(0)\n\n/* 2 REG_P2PPS1_STATE_8197F */\n#define BIT_P2P1_POWER_STATE_8197F BIT(7)\n#define BIT_P2P1_CTWINDOW_ON_8197F BIT(6)\n#define BIT_P2P1_BEACON_AREA_ON_8197F BIT(5)\n#define BIT_P2P1_CTWIN_EARLY_DISTX_8197F BIT(4)\n#define BIT_P2P1_NOA1_OFF_PERIOD_8197F BIT(3)\n#define BIT_P2P1_FORCE_DOZE1_8197F BIT(2)\n#define BIT_P2P1_NOA0_OFF_PERIOD_8197F BIT(1)\n#define BIT_P2P1_FORCE_DOZE0_8197F BIT(0)\n\n/* 2 REG_P2PPS2_SPEC_STATE_8197F */\n#define BIT_P2P2_SPEC_POWER_STATE_8197F BIT(7)\n#define BIT_P2P2_SPEC_CTWINDOW_ON_8197F BIT(6)\n#define BIT_P2P2_SPEC_BCN_AREA_ON_8197F BIT(5)\n#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8197F BIT(4)\n#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8197F BIT(3)\n#define BIT_P2P2_SPEC_FORCE_DOZE1_8197F BIT(2)\n#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8197F BIT(1)\n#define BIT_P2P2_SPEC_FORCE_DOZE0_8197F BIT(0)\n\n/* 2 REG_P2PPS2_STATE_8197F */\n#define BIT_P2P2_POWER_STATE_8197F BIT(7)\n#define BIT_P2P2_CTWINDOW_ON_8197F BIT(6)\n#define BIT_P2P2_BEACON_AREA_ON_8197F BIT(5)\n#define BIT_P2P2_CTWIN_EARLY_DISTX_8197F BIT(4)\n#define BIT_P2P2_NOA1_OFF_PERIOD_8197F BIT(3)\n#define BIT_P2P2_FORCE_DOZE1_8197F BIT(2)\n#define BIT_P2P2_NOA0_OFF_PERIOD_8197F BIT(1)\n#define BIT_P2P2_FORCE_DOZE0_8197F BIT(0)\n\n/* 2 REG_PS_TIMER0_8197F */\n\n#define BIT_SHIFT_PSTIMER0_INT_8197F 5\n#define BIT_MASK_PSTIMER0_INT_8197F 0x7ffffff\n#define BIT_PSTIMER0_INT_8197F(x)                                              \\\n\t(((x) & BIT_MASK_PSTIMER0_INT_8197F) << BIT_SHIFT_PSTIMER0_INT_8197F)\n#define BITS_PSTIMER0_INT_8197F                                                \\\n\t(BIT_MASK_PSTIMER0_INT_8197F << BIT_SHIFT_PSTIMER0_INT_8197F)\n#define BIT_CLEAR_PSTIMER0_INT_8197F(x) ((x) & (~BITS_PSTIMER0_INT_8197F))\n#define BIT_GET_PSTIMER0_INT_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_PSTIMER0_INT_8197F) & BIT_MASK_PSTIMER0_INT_8197F)\n#define BIT_SET_PSTIMER0_INT_8197F(x, v)                                       \\\n\t(BIT_CLEAR_PSTIMER0_INT_8197F(x) | BIT_PSTIMER0_INT_8197F(v))\n\n/* 2 REG_PS_TIMER1_8197F */\n\n#define BIT_SHIFT_PSTIMER1_INT_8197F 5\n#define BIT_MASK_PSTIMER1_INT_8197F 0x7ffffff\n#define BIT_PSTIMER1_INT_8197F(x)                                              \\\n\t(((x) & BIT_MASK_PSTIMER1_INT_8197F) << BIT_SHIFT_PSTIMER1_INT_8197F)\n#define BITS_PSTIMER1_INT_8197F                                                \\\n\t(BIT_MASK_PSTIMER1_INT_8197F << BIT_SHIFT_PSTIMER1_INT_8197F)\n#define BIT_CLEAR_PSTIMER1_INT_8197F(x) ((x) & (~BITS_PSTIMER1_INT_8197F))\n#define BIT_GET_PSTIMER1_INT_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_PSTIMER1_INT_8197F) & BIT_MASK_PSTIMER1_INT_8197F)\n#define BIT_SET_PSTIMER1_INT_8197F(x, v)                                       \\\n\t(BIT_CLEAR_PSTIMER1_INT_8197F(x) | BIT_PSTIMER1_INT_8197F(v))\n\n/* 2 REG_PS_TIMER2_8197F */\n\n#define BIT_SHIFT_PSTIMER2_INT_8197F 5\n#define BIT_MASK_PSTIMER2_INT_8197F 0x7ffffff\n#define BIT_PSTIMER2_INT_8197F(x)                                              \\\n\t(((x) & BIT_MASK_PSTIMER2_INT_8197F) << BIT_SHIFT_PSTIMER2_INT_8197F)\n#define BITS_PSTIMER2_INT_8197F                                                \\\n\t(BIT_MASK_PSTIMER2_INT_8197F << BIT_SHIFT_PSTIMER2_INT_8197F)\n#define BIT_CLEAR_PSTIMER2_INT_8197F(x) ((x) & (~BITS_PSTIMER2_INT_8197F))\n#define BIT_GET_PSTIMER2_INT_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_PSTIMER2_INT_8197F) & BIT_MASK_PSTIMER2_INT_8197F)\n#define BIT_SET_PSTIMER2_INT_8197F(x, v)                                       \\\n\t(BIT_CLEAR_PSTIMER2_INT_8197F(x) | BIT_PSTIMER2_INT_8197F(v))\n\n/* 2 REG_TBTT_CTN_AREA_8197F */\n\n#define BIT_SHIFT_TBTT_CTN_AREA_8197F 0\n#define BIT_MASK_TBTT_CTN_AREA_8197F 0xff\n#define BIT_TBTT_CTN_AREA_8197F(x)                                             \\\n\t(((x) & BIT_MASK_TBTT_CTN_AREA_8197F) << BIT_SHIFT_TBTT_CTN_AREA_8197F)\n#define BITS_TBTT_CTN_AREA_8197F                                               \\\n\t(BIT_MASK_TBTT_CTN_AREA_8197F << BIT_SHIFT_TBTT_CTN_AREA_8197F)\n#define BIT_CLEAR_TBTT_CTN_AREA_8197F(x) ((x) & (~BITS_TBTT_CTN_AREA_8197F))\n#define BIT_GET_TBTT_CTN_AREA_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_TBTT_CTN_AREA_8197F) & BIT_MASK_TBTT_CTN_AREA_8197F)\n#define BIT_SET_TBTT_CTN_AREA_8197F(x, v)                                      \\\n\t(BIT_CLEAR_TBTT_CTN_AREA_8197F(x) | BIT_TBTT_CTN_AREA_8197F(v))\n\n/* 2 REG_FORCE_BCN_IFS_8197F */\n\n#define BIT_SHIFT_FORCE_BCN_IFS_8197F 0\n#define BIT_MASK_FORCE_BCN_IFS_8197F 0xff\n#define BIT_FORCE_BCN_IFS_8197F(x)                                             \\\n\t(((x) & BIT_MASK_FORCE_BCN_IFS_8197F) << BIT_SHIFT_FORCE_BCN_IFS_8197F)\n#define BITS_FORCE_BCN_IFS_8197F                                               \\\n\t(BIT_MASK_FORCE_BCN_IFS_8197F << BIT_SHIFT_FORCE_BCN_IFS_8197F)\n#define BIT_CLEAR_FORCE_BCN_IFS_8197F(x) ((x) & (~BITS_FORCE_BCN_IFS_8197F))\n#define BIT_GET_FORCE_BCN_IFS_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_FORCE_BCN_IFS_8197F) & BIT_MASK_FORCE_BCN_IFS_8197F)\n#define BIT_SET_FORCE_BCN_IFS_8197F(x, v)                                      \\\n\t(BIT_CLEAR_FORCE_BCN_IFS_8197F(x) | BIT_FORCE_BCN_IFS_8197F(v))\n\n/* 2 REG_TXOP_MIN_8197F */\n#define BIT_NAV_BLK_HGQ_8197F BIT(15)\n#define BIT_NAV_BLK_MGQ_8197F BIT(14)\n\n#define BIT_SHIFT_TXOP_MIN_8197F 0\n#define BIT_MASK_TXOP_MIN_8197F 0x3fff\n#define BIT_TXOP_MIN_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_TXOP_MIN_8197F) << BIT_SHIFT_TXOP_MIN_8197F)\n#define BITS_TXOP_MIN_8197F                                                    \\\n\t(BIT_MASK_TXOP_MIN_8197F << BIT_SHIFT_TXOP_MIN_8197F)\n#define BIT_CLEAR_TXOP_MIN_8197F(x) ((x) & (~BITS_TXOP_MIN_8197F))\n#define BIT_GET_TXOP_MIN_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXOP_MIN_8197F) & BIT_MASK_TXOP_MIN_8197F)\n#define BIT_SET_TXOP_MIN_8197F(x, v)                                           \\\n\t(BIT_CLEAR_TXOP_MIN_8197F(x) | BIT_TXOP_MIN_8197F(v))\n\n/* 2 REG_PRE_BKF_TIME_8197F */\n\n#define BIT_SHIFT_PRE_BKF_TIME_8197F 0\n#define BIT_MASK_PRE_BKF_TIME_8197F 0xff\n#define BIT_PRE_BKF_TIME_8197F(x)                                              \\\n\t(((x) & BIT_MASK_PRE_BKF_TIME_8197F) << BIT_SHIFT_PRE_BKF_TIME_8197F)\n#define BITS_PRE_BKF_TIME_8197F                                                \\\n\t(BIT_MASK_PRE_BKF_TIME_8197F << BIT_SHIFT_PRE_BKF_TIME_8197F)\n#define BIT_CLEAR_PRE_BKF_TIME_8197F(x) ((x) & (~BITS_PRE_BKF_TIME_8197F))\n#define BIT_GET_PRE_BKF_TIME_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_PRE_BKF_TIME_8197F) & BIT_MASK_PRE_BKF_TIME_8197F)\n#define BIT_SET_PRE_BKF_TIME_8197F(x, v)                                       \\\n\t(BIT_CLEAR_PRE_BKF_TIME_8197F(x) | BIT_PRE_BKF_TIME_8197F(v))\n\n/* 2 REG_CROSS_TXOP_CTRL_8197F */\n#define BIT_DTIM_BYPASS_8197F BIT(2)\n#define BIT_RTS_NAV_TXOP_8197F BIT(1)\n#define BIT_NOT_CROSS_TXOP_8197F BIT(0)\n\n/* 2 REG_TBTT_INT_SHIFT_CLI0_8197F */\n#define BIT_TBTT_INT_SHIFT_DIR_CLI0_8197F BIT(7)\n\n#define BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F 0\n#define BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F 0x7f\n#define BIT_TBTT_INT_SHIFT_CLI0_8197F(x)                                       \\\n\t(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F)                            \\\n\t << BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F)\n#define BITS_TBTT_INT_SHIFT_CLI0_8197F                                         \\\n\t(BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F                                    \\\n\t << BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F)\n#define BIT_CLEAR_TBTT_INT_SHIFT_CLI0_8197F(x)                                 \\\n\t((x) & (~BITS_TBTT_INT_SHIFT_CLI0_8197F))\n#define BIT_GET_TBTT_INT_SHIFT_CLI0_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) &                        \\\n\t BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F)\n#define BIT_SET_TBTT_INT_SHIFT_CLI0_8197F(x, v)                                \\\n\t(BIT_CLEAR_TBTT_INT_SHIFT_CLI0_8197F(x) |                              \\\n\t BIT_TBTT_INT_SHIFT_CLI0_8197F(v))\n\n/* 2 REG_TBTT_INT_SHIFT_CLI1_8197F */\n#define BIT_TBTT_INT_SHIFT_DIR_CLI1_8197F BIT(7)\n\n#define BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F 0\n#define BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F 0x7f\n#define BIT_TBTT_INT_SHIFT_CLI1_8197F(x)                                       \\\n\t(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F)                            \\\n\t << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F)\n#define BITS_TBTT_INT_SHIFT_CLI1_8197F                                         \\\n\t(BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F                                    \\\n\t << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F)\n#define BIT_CLEAR_TBTT_INT_SHIFT_CLI1_8197F(x)                                 \\\n\t((x) & (~BITS_TBTT_INT_SHIFT_CLI1_8197F))\n#define BIT_GET_TBTT_INT_SHIFT_CLI1_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) &                        \\\n\t BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F)\n#define BIT_SET_TBTT_INT_SHIFT_CLI1_8197F(x, v)                                \\\n\t(BIT_CLEAR_TBTT_INT_SHIFT_CLI1_8197F(x) |                              \\\n\t BIT_TBTT_INT_SHIFT_CLI1_8197F(v))\n\n/* 2 REG_TBTT_INT_SHIFT_CLI2_8197F */\n#define BIT_TBTT_INT_SHIFT_DIR_CLI2_8197F BIT(7)\n\n#define BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F 0\n#define BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F 0x7f\n#define BIT_TBTT_INT_SHIFT_CLI2_8197F(x)                                       \\\n\t(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F)                            \\\n\t << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F)\n#define BITS_TBTT_INT_SHIFT_CLI2_8197F                                         \\\n\t(BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F                                    \\\n\t << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F)\n#define BIT_CLEAR_TBTT_INT_SHIFT_CLI2_8197F(x)                                 \\\n\t((x) & (~BITS_TBTT_INT_SHIFT_CLI2_8197F))\n#define BIT_GET_TBTT_INT_SHIFT_CLI2_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) &                        \\\n\t BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F)\n#define BIT_SET_TBTT_INT_SHIFT_CLI2_8197F(x, v)                                \\\n\t(BIT_CLEAR_TBTT_INT_SHIFT_CLI2_8197F(x) |                              \\\n\t BIT_TBTT_INT_SHIFT_CLI2_8197F(v))\n\n/* 2 REG_TBTT_INT_SHIFT_CLI3_8197F */\n#define BIT_TBTT_INT_SHIFT_DIR_CLI3_8197F BIT(7)\n\n#define BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F 0\n#define BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F 0x7f\n#define BIT_TBTT_INT_SHIFT_CLI3_8197F(x)                                       \\\n\t(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F)                            \\\n\t << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F)\n#define BITS_TBTT_INT_SHIFT_CLI3_8197F                                         \\\n\t(BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F                                    \\\n\t << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F)\n#define BIT_CLEAR_TBTT_INT_SHIFT_CLI3_8197F(x)                                 \\\n\t((x) & (~BITS_TBTT_INT_SHIFT_CLI3_8197F))\n#define BIT_GET_TBTT_INT_SHIFT_CLI3_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) &                        \\\n\t BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F)\n#define BIT_SET_TBTT_INT_SHIFT_CLI3_8197F(x, v)                                \\\n\t(BIT_CLEAR_TBTT_INT_SHIFT_CLI3_8197F(x) |                              \\\n\t BIT_TBTT_INT_SHIFT_CLI3_8197F(v))\n\n/* 2 REG_TBTT_INT_SHIFT_ENABLE_8197F */\n#define BIT_EN_TBTT_RTY_8197F BIT(1)\n#define BIT_TBTT_INT_SHIFT_ENABLE_8197F BIT(0)\n\n/* 2 REG_ATIMWND2_8197F */\n\n#define BIT_SHIFT_ATIMWND2_8197F 0\n#define BIT_MASK_ATIMWND2_8197F 0xff\n#define BIT_ATIMWND2_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND2_8197F) << BIT_SHIFT_ATIMWND2_8197F)\n#define BITS_ATIMWND2_8197F                                                    \\\n\t(BIT_MASK_ATIMWND2_8197F << BIT_SHIFT_ATIMWND2_8197F)\n#define BIT_CLEAR_ATIMWND2_8197F(x) ((x) & (~BITS_ATIMWND2_8197F))\n#define BIT_GET_ATIMWND2_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND2_8197F) & BIT_MASK_ATIMWND2_8197F)\n#define BIT_SET_ATIMWND2_8197F(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND2_8197F(x) | BIT_ATIMWND2_8197F(v))\n\n/* 2 REG_ATIMWND3_8197F */\n\n#define BIT_SHIFT_ATIMWND3_8197F 0\n#define BIT_MASK_ATIMWND3_8197F 0xff\n#define BIT_ATIMWND3_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND3_8197F) << BIT_SHIFT_ATIMWND3_8197F)\n#define BITS_ATIMWND3_8197F                                                    \\\n\t(BIT_MASK_ATIMWND3_8197F << BIT_SHIFT_ATIMWND3_8197F)\n#define BIT_CLEAR_ATIMWND3_8197F(x) ((x) & (~BITS_ATIMWND3_8197F))\n#define BIT_GET_ATIMWND3_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND3_8197F) & BIT_MASK_ATIMWND3_8197F)\n#define BIT_SET_ATIMWND3_8197F(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND3_8197F(x) | BIT_ATIMWND3_8197F(v))\n\n/* 2 REG_ATIMWND4_8197F */\n\n#define BIT_SHIFT_ATIMWND4_8197F 0\n#define BIT_MASK_ATIMWND4_8197F 0xff\n#define BIT_ATIMWND4_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND4_8197F) << BIT_SHIFT_ATIMWND4_8197F)\n#define BITS_ATIMWND4_8197F                                                    \\\n\t(BIT_MASK_ATIMWND4_8197F << BIT_SHIFT_ATIMWND4_8197F)\n#define BIT_CLEAR_ATIMWND4_8197F(x) ((x) & (~BITS_ATIMWND4_8197F))\n#define BIT_GET_ATIMWND4_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND4_8197F) & BIT_MASK_ATIMWND4_8197F)\n#define BIT_SET_ATIMWND4_8197F(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND4_8197F(x) | BIT_ATIMWND4_8197F(v))\n\n/* 2 REG_ATIMWND5_8197F */\n\n#define BIT_SHIFT_ATIMWND5_8197F 0\n#define BIT_MASK_ATIMWND5_8197F 0xff\n#define BIT_ATIMWND5_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND5_8197F) << BIT_SHIFT_ATIMWND5_8197F)\n#define BITS_ATIMWND5_8197F                                                    \\\n\t(BIT_MASK_ATIMWND5_8197F << BIT_SHIFT_ATIMWND5_8197F)\n#define BIT_CLEAR_ATIMWND5_8197F(x) ((x) & (~BITS_ATIMWND5_8197F))\n#define BIT_GET_ATIMWND5_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND5_8197F) & BIT_MASK_ATIMWND5_8197F)\n#define BIT_SET_ATIMWND5_8197F(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND5_8197F(x) | BIT_ATIMWND5_8197F(v))\n\n/* 2 REG_ATIMWND6_8197F */\n\n#define BIT_SHIFT_ATIMWND6_8197F 0\n#define BIT_MASK_ATIMWND6_8197F 0xff\n#define BIT_ATIMWND6_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND6_8197F) << BIT_SHIFT_ATIMWND6_8197F)\n#define BITS_ATIMWND6_8197F                                                    \\\n\t(BIT_MASK_ATIMWND6_8197F << BIT_SHIFT_ATIMWND6_8197F)\n#define BIT_CLEAR_ATIMWND6_8197F(x) ((x) & (~BITS_ATIMWND6_8197F))\n#define BIT_GET_ATIMWND6_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND6_8197F) & BIT_MASK_ATIMWND6_8197F)\n#define BIT_SET_ATIMWND6_8197F(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND6_8197F(x) | BIT_ATIMWND6_8197F(v))\n\n/* 2 REG_ATIMWND7_8197F */\n\n#define BIT_SHIFT_ATIMWND7_8197F 0\n#define BIT_MASK_ATIMWND7_8197F 0xff\n#define BIT_ATIMWND7_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND7_8197F) << BIT_SHIFT_ATIMWND7_8197F)\n#define BITS_ATIMWND7_8197F                                                    \\\n\t(BIT_MASK_ATIMWND7_8197F << BIT_SHIFT_ATIMWND7_8197F)\n#define BIT_CLEAR_ATIMWND7_8197F(x) ((x) & (~BITS_ATIMWND7_8197F))\n#define BIT_GET_ATIMWND7_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND7_8197F) & BIT_MASK_ATIMWND7_8197F)\n#define BIT_SET_ATIMWND7_8197F(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND7_8197F(x) | BIT_ATIMWND7_8197F(v))\n\n/* 2 REG_ATIMUGT_8197F */\n\n#define BIT_SHIFT_ATIM_URGENT_8197F 0\n#define BIT_MASK_ATIM_URGENT_8197F 0xff\n#define BIT_ATIM_URGENT_8197F(x)                                               \\\n\t(((x) & BIT_MASK_ATIM_URGENT_8197F) << BIT_SHIFT_ATIM_URGENT_8197F)\n#define BITS_ATIM_URGENT_8197F                                                 \\\n\t(BIT_MASK_ATIM_URGENT_8197F << BIT_SHIFT_ATIM_URGENT_8197F)\n#define BIT_CLEAR_ATIM_URGENT_8197F(x) ((x) & (~BITS_ATIM_URGENT_8197F))\n#define BIT_GET_ATIM_URGENT_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_ATIM_URGENT_8197F) & BIT_MASK_ATIM_URGENT_8197F)\n#define BIT_SET_ATIM_URGENT_8197F(x, v)                                        \\\n\t(BIT_CLEAR_ATIM_URGENT_8197F(x) | BIT_ATIM_URGENT_8197F(v))\n\n/* 2 REG_HIQ_NO_LMT_EN_8197F */\n#define BIT_HIQ_NO_LMT_EN_VAP7_8197F BIT(7)\n#define BIT_HIQ_NO_LMT_EN_VAP6_8197F BIT(6)\n#define BIT_HIQ_NO_LMT_EN_VAP5_8197F BIT(5)\n#define BIT_HIQ_NO_LMT_EN_VAP4_8197F BIT(4)\n#define BIT_HIQ_NO_LMT_EN_VAP3_8197F BIT(3)\n#define BIT_HIQ_NO_LMT_EN_VAP2_8197F BIT(2)\n#define BIT_HIQ_NO_LMT_EN_VAP1_8197F BIT(1)\n#define BIT_HIQ_NO_LMT_EN_ROOT_8197F BIT(0)\n\n/* 2 REG_DTIM_COUNTER_ROOT_8197F */\n\n#define BIT_SHIFT_DTIM_COUNT_ROOT_8197F 0\n#define BIT_MASK_DTIM_COUNT_ROOT_8197F 0xff\n#define BIT_DTIM_COUNT_ROOT_8197F(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_ROOT_8197F)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_ROOT_8197F)\n#define BITS_DTIM_COUNT_ROOT_8197F                                             \\\n\t(BIT_MASK_DTIM_COUNT_ROOT_8197F << BIT_SHIFT_DTIM_COUNT_ROOT_8197F)\n#define BIT_CLEAR_DTIM_COUNT_ROOT_8197F(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8197F))\n#define BIT_GET_DTIM_COUNT_ROOT_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8197F) &                            \\\n\t BIT_MASK_DTIM_COUNT_ROOT_8197F)\n#define BIT_SET_DTIM_COUNT_ROOT_8197F(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_ROOT_8197F(x) | BIT_DTIM_COUNT_ROOT_8197F(v))\n\n/* 2 REG_DTIM_COUNTER_VAP1_8197F */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP1_8197F 0\n#define BIT_MASK_DTIM_COUNT_VAP1_8197F 0xff\n#define BIT_DTIM_COUNT_VAP1_8197F(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP1_8197F)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP1_8197F)\n#define BITS_DTIM_COUNT_VAP1_8197F                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP1_8197F << BIT_SHIFT_DTIM_COUNT_VAP1_8197F)\n#define BIT_CLEAR_DTIM_COUNT_VAP1_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8197F))\n#define BIT_GET_DTIM_COUNT_VAP1_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8197F) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP1_8197F)\n#define BIT_SET_DTIM_COUNT_VAP1_8197F(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP1_8197F(x) | BIT_DTIM_COUNT_VAP1_8197F(v))\n\n/* 2 REG_DTIM_COUNTER_VAP2_8197F */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP2_8197F 0\n#define BIT_MASK_DTIM_COUNT_VAP2_8197F 0xff\n#define BIT_DTIM_COUNT_VAP2_8197F(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP2_8197F)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP2_8197F)\n#define BITS_DTIM_COUNT_VAP2_8197F                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP2_8197F << BIT_SHIFT_DTIM_COUNT_VAP2_8197F)\n#define BIT_CLEAR_DTIM_COUNT_VAP2_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8197F))\n#define BIT_GET_DTIM_COUNT_VAP2_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8197F) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP2_8197F)\n#define BIT_SET_DTIM_COUNT_VAP2_8197F(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP2_8197F(x) | BIT_DTIM_COUNT_VAP2_8197F(v))\n\n/* 2 REG_DTIM_COUNTER_VAP3_8197F */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP3_8197F 0\n#define BIT_MASK_DTIM_COUNT_VAP3_8197F 0xff\n#define BIT_DTIM_COUNT_VAP3_8197F(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP3_8197F)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP3_8197F)\n#define BITS_DTIM_COUNT_VAP3_8197F                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP3_8197F << BIT_SHIFT_DTIM_COUNT_VAP3_8197F)\n#define BIT_CLEAR_DTIM_COUNT_VAP3_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8197F))\n#define BIT_GET_DTIM_COUNT_VAP3_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8197F) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP3_8197F)\n#define BIT_SET_DTIM_COUNT_VAP3_8197F(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP3_8197F(x) | BIT_DTIM_COUNT_VAP3_8197F(v))\n\n/* 2 REG_DTIM_COUNTER_VAP4_8197F */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP4_8197F 0\n#define BIT_MASK_DTIM_COUNT_VAP4_8197F 0xff\n#define BIT_DTIM_COUNT_VAP4_8197F(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP4_8197F)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP4_8197F)\n#define BITS_DTIM_COUNT_VAP4_8197F                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP4_8197F << BIT_SHIFT_DTIM_COUNT_VAP4_8197F)\n#define BIT_CLEAR_DTIM_COUNT_VAP4_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8197F))\n#define BIT_GET_DTIM_COUNT_VAP4_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8197F) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP4_8197F)\n#define BIT_SET_DTIM_COUNT_VAP4_8197F(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP4_8197F(x) | BIT_DTIM_COUNT_VAP4_8197F(v))\n\n/* 2 REG_DTIM_COUNTER_VAP5_8197F */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP5_8197F 0\n#define BIT_MASK_DTIM_COUNT_VAP5_8197F 0xff\n#define BIT_DTIM_COUNT_VAP5_8197F(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP5_8197F)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP5_8197F)\n#define BITS_DTIM_COUNT_VAP5_8197F                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP5_8197F << BIT_SHIFT_DTIM_COUNT_VAP5_8197F)\n#define BIT_CLEAR_DTIM_COUNT_VAP5_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8197F))\n#define BIT_GET_DTIM_COUNT_VAP5_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8197F) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP5_8197F)\n#define BIT_SET_DTIM_COUNT_VAP5_8197F(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP5_8197F(x) | BIT_DTIM_COUNT_VAP5_8197F(v))\n\n/* 2 REG_DTIM_COUNTER_VAP6_8197F */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP6_8197F 0\n#define BIT_MASK_DTIM_COUNT_VAP6_8197F 0xff\n#define BIT_DTIM_COUNT_VAP6_8197F(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP6_8197F)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP6_8197F)\n#define BITS_DTIM_COUNT_VAP6_8197F                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP6_8197F << BIT_SHIFT_DTIM_COUNT_VAP6_8197F)\n#define BIT_CLEAR_DTIM_COUNT_VAP6_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8197F))\n#define BIT_GET_DTIM_COUNT_VAP6_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8197F) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP6_8197F)\n#define BIT_SET_DTIM_COUNT_VAP6_8197F(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP6_8197F(x) | BIT_DTIM_COUNT_VAP6_8197F(v))\n\n/* 2 REG_DTIM_COUNTER_VAP7_8197F */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP7_8197F 0\n#define BIT_MASK_DTIM_COUNT_VAP7_8197F 0xff\n#define BIT_DTIM_COUNT_VAP7_8197F(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP7_8197F)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP7_8197F)\n#define BITS_DTIM_COUNT_VAP7_8197F                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP7_8197F << BIT_SHIFT_DTIM_COUNT_VAP7_8197F)\n#define BIT_CLEAR_DTIM_COUNT_VAP7_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8197F))\n#define BIT_GET_DTIM_COUNT_VAP7_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8197F) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP7_8197F)\n#define BIT_SET_DTIM_COUNT_VAP7_8197F(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP7_8197F(x) | BIT_DTIM_COUNT_VAP7_8197F(v))\n\n/* 2 REG_DIS_ATIM_8197F */\n#define BIT_DIS_ATIM_VAP7_8197F BIT(7)\n#define BIT_DIS_ATIM_VAP6_8197F BIT(6)\n#define BIT_DIS_ATIM_VAP5_8197F BIT(5)\n#define BIT_DIS_ATIM_VAP4_8197F BIT(4)\n#define BIT_DIS_ATIM_VAP3_8197F BIT(3)\n#define BIT_DIS_ATIM_VAP2_8197F BIT(2)\n#define BIT_DIS_ATIM_VAP1_8197F BIT(1)\n#define BIT_DIS_ATIM_ROOT_8197F BIT(0)\n\n/* 2 REG_EARLY_128US_8197F */\n\n#define BIT_SHIFT_TSFT_SEL_TIMER1_8197F 3\n#define BIT_MASK_TSFT_SEL_TIMER1_8197F 0x7\n#define BIT_TSFT_SEL_TIMER1_8197F(x)                                           \\\n\t(((x) & BIT_MASK_TSFT_SEL_TIMER1_8197F)                                \\\n\t << BIT_SHIFT_TSFT_SEL_TIMER1_8197F)\n#define BITS_TSFT_SEL_TIMER1_8197F                                             \\\n\t(BIT_MASK_TSFT_SEL_TIMER1_8197F << BIT_SHIFT_TSFT_SEL_TIMER1_8197F)\n#define BIT_CLEAR_TSFT_SEL_TIMER1_8197F(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8197F))\n#define BIT_GET_TSFT_SEL_TIMER1_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8197F) &                            \\\n\t BIT_MASK_TSFT_SEL_TIMER1_8197F)\n#define BIT_SET_TSFT_SEL_TIMER1_8197F(x, v)                                    \\\n\t(BIT_CLEAR_TSFT_SEL_TIMER1_8197F(x) | BIT_TSFT_SEL_TIMER1_8197F(v))\n\n#define BIT_SHIFT_EARLY_128US_8197F 0\n#define BIT_MASK_EARLY_128US_8197F 0x7\n#define BIT_EARLY_128US_8197F(x)                                               \\\n\t(((x) & BIT_MASK_EARLY_128US_8197F) << BIT_SHIFT_EARLY_128US_8197F)\n#define BITS_EARLY_128US_8197F                                                 \\\n\t(BIT_MASK_EARLY_128US_8197F << BIT_SHIFT_EARLY_128US_8197F)\n#define BIT_CLEAR_EARLY_128US_8197F(x) ((x) & (~BITS_EARLY_128US_8197F))\n#define BIT_GET_EARLY_128US_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_EARLY_128US_8197F) & BIT_MASK_EARLY_128US_8197F)\n#define BIT_SET_EARLY_128US_8197F(x, v)                                        \\\n\t(BIT_CLEAR_EARLY_128US_8197F(x) | BIT_EARLY_128US_8197F(v))\n\n/* 2 REG_P2PPS1_CTRL_8197F */\n#define BIT_P2P1_CTW_ALLSTASLEEP_8197F BIT(7)\n#define BIT_P2P1_OFF_DISTX_EN_8197F BIT(6)\n#define BIT_P2P1_PWR_MGT_EN_8197F BIT(5)\n#define BIT_P2P1_NOA1_EN_8197F BIT(2)\n#define BIT_P2P1_NOA0_EN_8197F BIT(1)\n\n/* 2 REG_P2PPS2_CTRL_8197F */\n#define BIT_P2P2_CTW_ALLSTASLEEP_8197F BIT(7)\n#define BIT_P2P2_OFF_DISTX_EN_8197F BIT(6)\n#define BIT_P2P2_PWR_MGT_EN_8197F BIT(5)\n#define BIT_P2P2_NOA1_EN_8197F BIT(2)\n#define BIT_P2P2_NOA0_EN_8197F BIT(1)\n\n/* 2 REG_TIMER0_SRC_SEL_8197F */\n\n#define BIT_SHIFT_SYNC_CLI_SEL_8197F 4\n#define BIT_MASK_SYNC_CLI_SEL_8197F 0x7\n#define BIT_SYNC_CLI_SEL_8197F(x)                                              \\\n\t(((x) & BIT_MASK_SYNC_CLI_SEL_8197F) << BIT_SHIFT_SYNC_CLI_SEL_8197F)\n#define BITS_SYNC_CLI_SEL_8197F                                                \\\n\t(BIT_MASK_SYNC_CLI_SEL_8197F << BIT_SHIFT_SYNC_CLI_SEL_8197F)\n#define BIT_CLEAR_SYNC_CLI_SEL_8197F(x) ((x) & (~BITS_SYNC_CLI_SEL_8197F))\n#define BIT_GET_SYNC_CLI_SEL_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_SYNC_CLI_SEL_8197F) & BIT_MASK_SYNC_CLI_SEL_8197F)\n#define BIT_SET_SYNC_CLI_SEL_8197F(x, v)                                       \\\n\t(BIT_CLEAR_SYNC_CLI_SEL_8197F(x) | BIT_SYNC_CLI_SEL_8197F(v))\n\n#define BIT_SHIFT_TSFT_SEL_TIMER0_8197F 0\n#define BIT_MASK_TSFT_SEL_TIMER0_8197F 0x7\n#define BIT_TSFT_SEL_TIMER0_8197F(x)                                           \\\n\t(((x) & BIT_MASK_TSFT_SEL_TIMER0_8197F)                                \\\n\t << BIT_SHIFT_TSFT_SEL_TIMER0_8197F)\n#define BITS_TSFT_SEL_TIMER0_8197F                                             \\\n\t(BIT_MASK_TSFT_SEL_TIMER0_8197F << BIT_SHIFT_TSFT_SEL_TIMER0_8197F)\n#define BIT_CLEAR_TSFT_SEL_TIMER0_8197F(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8197F))\n#define BIT_GET_TSFT_SEL_TIMER0_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8197F) &                            \\\n\t BIT_MASK_TSFT_SEL_TIMER0_8197F)\n#define BIT_SET_TSFT_SEL_TIMER0_8197F(x, v)                                    \\\n\t(BIT_CLEAR_TSFT_SEL_TIMER0_8197F(x) | BIT_TSFT_SEL_TIMER0_8197F(v))\n\n/* 2 REG_NOA_UNIT_SEL_8197F */\n\n#define BIT_SHIFT_NOA_UNIT2_SEL_8197F 8\n#define BIT_MASK_NOA_UNIT2_SEL_8197F 0x7\n#define BIT_NOA_UNIT2_SEL_8197F(x)                                             \\\n\t(((x) & BIT_MASK_NOA_UNIT2_SEL_8197F) << BIT_SHIFT_NOA_UNIT2_SEL_8197F)\n#define BITS_NOA_UNIT2_SEL_8197F                                               \\\n\t(BIT_MASK_NOA_UNIT2_SEL_8197F << BIT_SHIFT_NOA_UNIT2_SEL_8197F)\n#define BIT_CLEAR_NOA_UNIT2_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT2_SEL_8197F))\n#define BIT_GET_NOA_UNIT2_SEL_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8197F) & BIT_MASK_NOA_UNIT2_SEL_8197F)\n#define BIT_SET_NOA_UNIT2_SEL_8197F(x, v)                                      \\\n\t(BIT_CLEAR_NOA_UNIT2_SEL_8197F(x) | BIT_NOA_UNIT2_SEL_8197F(v))\n\n#define BIT_SHIFT_NOA_UNIT1_SEL_8197F 4\n#define BIT_MASK_NOA_UNIT1_SEL_8197F 0x7\n#define BIT_NOA_UNIT1_SEL_8197F(x)                                             \\\n\t(((x) & BIT_MASK_NOA_UNIT1_SEL_8197F) << BIT_SHIFT_NOA_UNIT1_SEL_8197F)\n#define BITS_NOA_UNIT1_SEL_8197F                                               \\\n\t(BIT_MASK_NOA_UNIT1_SEL_8197F << BIT_SHIFT_NOA_UNIT1_SEL_8197F)\n#define BIT_CLEAR_NOA_UNIT1_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT1_SEL_8197F))\n#define BIT_GET_NOA_UNIT1_SEL_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8197F) & BIT_MASK_NOA_UNIT1_SEL_8197F)\n#define BIT_SET_NOA_UNIT1_SEL_8197F(x, v)                                      \\\n\t(BIT_CLEAR_NOA_UNIT1_SEL_8197F(x) | BIT_NOA_UNIT1_SEL_8197F(v))\n\n#define BIT_SHIFT_NOA_UNIT0_SEL_8197F 0\n#define BIT_MASK_NOA_UNIT0_SEL_8197F 0x7\n#define BIT_NOA_UNIT0_SEL_8197F(x)                                             \\\n\t(((x) & BIT_MASK_NOA_UNIT0_SEL_8197F) << BIT_SHIFT_NOA_UNIT0_SEL_8197F)\n#define BITS_NOA_UNIT0_SEL_8197F                                               \\\n\t(BIT_MASK_NOA_UNIT0_SEL_8197F << BIT_SHIFT_NOA_UNIT0_SEL_8197F)\n#define BIT_CLEAR_NOA_UNIT0_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT0_SEL_8197F))\n#define BIT_GET_NOA_UNIT0_SEL_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8197F) & BIT_MASK_NOA_UNIT0_SEL_8197F)\n#define BIT_SET_NOA_UNIT0_SEL_8197F(x, v)                                      \\\n\t(BIT_CLEAR_NOA_UNIT0_SEL_8197F(x) | BIT_NOA_UNIT0_SEL_8197F(v))\n\n/* 2 REG_P2POFF_DIS_TXTIME_8197F */\n\n#define BIT_SHIFT_P2POFF_DIS_TXTIME_8197F 0\n#define BIT_MASK_P2POFF_DIS_TXTIME_8197F 0xff\n#define BIT_P2POFF_DIS_TXTIME_8197F(x)                                         \\\n\t(((x) & BIT_MASK_P2POFF_DIS_TXTIME_8197F)                              \\\n\t << BIT_SHIFT_P2POFF_DIS_TXTIME_8197F)\n#define BITS_P2POFF_DIS_TXTIME_8197F                                           \\\n\t(BIT_MASK_P2POFF_DIS_TXTIME_8197F << BIT_SHIFT_P2POFF_DIS_TXTIME_8197F)\n#define BIT_CLEAR_P2POFF_DIS_TXTIME_8197F(x)                                   \\\n\t((x) & (~BITS_P2POFF_DIS_TXTIME_8197F))\n#define BIT_GET_P2POFF_DIS_TXTIME_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) &                          \\\n\t BIT_MASK_P2POFF_DIS_TXTIME_8197F)\n#define BIT_SET_P2POFF_DIS_TXTIME_8197F(x, v)                                  \\\n\t(BIT_CLEAR_P2POFF_DIS_TXTIME_8197F(x) | BIT_P2POFF_DIS_TXTIME_8197F(v))\n\n/* 2 REG_MBSSID_BCN_SPACE2_8197F */\n\n#define BIT_SHIFT_BCN_SPACE_CLINT2_8197F 16\n#define BIT_MASK_BCN_SPACE_CLINT2_8197F 0xfff\n#define BIT_BCN_SPACE_CLINT2_8197F(x)                                          \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT2_8197F)                               \\\n\t << BIT_SHIFT_BCN_SPACE_CLINT2_8197F)\n#define BITS_BCN_SPACE_CLINT2_8197F                                            \\\n\t(BIT_MASK_BCN_SPACE_CLINT2_8197F << BIT_SHIFT_BCN_SPACE_CLINT2_8197F)\n#define BIT_CLEAR_BCN_SPACE_CLINT2_8197F(x)                                    \\\n\t((x) & (~BITS_BCN_SPACE_CLINT2_8197F))\n#define BIT_GET_BCN_SPACE_CLINT2_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8197F) &                           \\\n\t BIT_MASK_BCN_SPACE_CLINT2_8197F)\n#define BIT_SET_BCN_SPACE_CLINT2_8197F(x, v)                                   \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT2_8197F(x) | BIT_BCN_SPACE_CLINT2_8197F(v))\n\n#define BIT_SHIFT_BCN_SPACE_CLINT1_8197F 0\n#define BIT_MASK_BCN_SPACE_CLINT1_8197F 0xfff\n#define BIT_BCN_SPACE_CLINT1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT1_8197F)                               \\\n\t << BIT_SHIFT_BCN_SPACE_CLINT1_8197F)\n#define BITS_BCN_SPACE_CLINT1_8197F                                            \\\n\t(BIT_MASK_BCN_SPACE_CLINT1_8197F << BIT_SHIFT_BCN_SPACE_CLINT1_8197F)\n#define BIT_CLEAR_BCN_SPACE_CLINT1_8197F(x)                                    \\\n\t((x) & (~BITS_BCN_SPACE_CLINT1_8197F))\n#define BIT_GET_BCN_SPACE_CLINT1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8197F) &                           \\\n\t BIT_MASK_BCN_SPACE_CLINT1_8197F)\n#define BIT_SET_BCN_SPACE_CLINT1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT1_8197F(x) | BIT_BCN_SPACE_CLINT1_8197F(v))\n\n/* 2 REG_MBSSID_BCN_SPACE3_8197F */\n\n#define BIT_SHIFT_SUB_BCN_SPACE_8197F 16\n#define BIT_MASK_SUB_BCN_SPACE_8197F 0xff\n#define BIT_SUB_BCN_SPACE_8197F(x)                                             \\\n\t(((x) & BIT_MASK_SUB_BCN_SPACE_8197F) << BIT_SHIFT_SUB_BCN_SPACE_8197F)\n#define BITS_SUB_BCN_SPACE_8197F                                               \\\n\t(BIT_MASK_SUB_BCN_SPACE_8197F << BIT_SHIFT_SUB_BCN_SPACE_8197F)\n#define BIT_CLEAR_SUB_BCN_SPACE_8197F(x) ((x) & (~BITS_SUB_BCN_SPACE_8197F))\n#define BIT_GET_SUB_BCN_SPACE_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_SUB_BCN_SPACE_8197F) & BIT_MASK_SUB_BCN_SPACE_8197F)\n#define BIT_SET_SUB_BCN_SPACE_8197F(x, v)                                      \\\n\t(BIT_CLEAR_SUB_BCN_SPACE_8197F(x) | BIT_SUB_BCN_SPACE_8197F(v))\n\n#define BIT_SHIFT_BCN_SPACE_CLINT3_8197F 0\n#define BIT_MASK_BCN_SPACE_CLINT3_8197F 0xfff\n#define BIT_BCN_SPACE_CLINT3_8197F(x)                                          \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT3_8197F)                               \\\n\t << BIT_SHIFT_BCN_SPACE_CLINT3_8197F)\n#define BITS_BCN_SPACE_CLINT3_8197F                                            \\\n\t(BIT_MASK_BCN_SPACE_CLINT3_8197F << BIT_SHIFT_BCN_SPACE_CLINT3_8197F)\n#define BIT_CLEAR_BCN_SPACE_CLINT3_8197F(x)                                    \\\n\t((x) & (~BITS_BCN_SPACE_CLINT3_8197F))\n#define BIT_GET_BCN_SPACE_CLINT3_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8197F) &                           \\\n\t BIT_MASK_BCN_SPACE_CLINT3_8197F)\n#define BIT_SET_BCN_SPACE_CLINT3_8197F(x, v)                                   \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT3_8197F(x) | BIT_BCN_SPACE_CLINT3_8197F(v))\n\n/* 2 REG_ACMHWCTRL_8197F */\n#define BIT_BEQ_ACM_STATUS_8197F BIT(7)\n#define BIT_VIQ_ACM_STATUS_8197F BIT(6)\n#define BIT_VOQ_ACM_STATUS_8197F BIT(5)\n#define BIT_BEQ_ACM_EN_8197F BIT(3)\n#define BIT_VIQ_ACM_EN_8197F BIT(2)\n#define BIT_VOQ_ACM_EN_8197F BIT(1)\n#define BIT_ACMHWEN_8197F BIT(0)\n\n/* 2 REG_ACMRSTCTRL_8197F */\n#define BIT_BE_ACM_RESET_USED_TIME_8197F BIT(2)\n#define BIT_VI_ACM_RESET_USED_TIME_8197F BIT(1)\n#define BIT_VO_ACM_RESET_USED_TIME_8197F BIT(0)\n\n/* 2 REG_ACMAVG_8197F */\n\n#define BIT_SHIFT_AVGPERIOD_8197F 0\n#define BIT_MASK_AVGPERIOD_8197F 0xffff\n#define BIT_AVGPERIOD_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_AVGPERIOD_8197F) << BIT_SHIFT_AVGPERIOD_8197F)\n#define BITS_AVGPERIOD_8197F                                                   \\\n\t(BIT_MASK_AVGPERIOD_8197F << BIT_SHIFT_AVGPERIOD_8197F)\n#define BIT_CLEAR_AVGPERIOD_8197F(x) ((x) & (~BITS_AVGPERIOD_8197F))\n#define BIT_GET_AVGPERIOD_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_AVGPERIOD_8197F) & BIT_MASK_AVGPERIOD_8197F)\n#define BIT_SET_AVGPERIOD_8197F(x, v)                                          \\\n\t(BIT_CLEAR_AVGPERIOD_8197F(x) | BIT_AVGPERIOD_8197F(v))\n\n/* 2 REG_VO_ADMTIME_8197F */\n\n#define BIT_SHIFT_VO_ADMITTED_TIME_8197F 0\n#define BIT_MASK_VO_ADMITTED_TIME_8197F 0xffff\n#define BIT_VO_ADMITTED_TIME_8197F(x)                                          \\\n\t(((x) & BIT_MASK_VO_ADMITTED_TIME_8197F)                               \\\n\t << BIT_SHIFT_VO_ADMITTED_TIME_8197F)\n#define BITS_VO_ADMITTED_TIME_8197F                                            \\\n\t(BIT_MASK_VO_ADMITTED_TIME_8197F << BIT_SHIFT_VO_ADMITTED_TIME_8197F)\n#define BIT_CLEAR_VO_ADMITTED_TIME_8197F(x)                                    \\\n\t((x) & (~BITS_VO_ADMITTED_TIME_8197F))\n#define BIT_GET_VO_ADMITTED_TIME_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8197F) &                           \\\n\t BIT_MASK_VO_ADMITTED_TIME_8197F)\n#define BIT_SET_VO_ADMITTED_TIME_8197F(x, v)                                   \\\n\t(BIT_CLEAR_VO_ADMITTED_TIME_8197F(x) | BIT_VO_ADMITTED_TIME_8197F(v))\n\n/* 2 REG_VI_ADMTIME_8197F */\n\n#define BIT_SHIFT_VI_ADMITTED_TIME_8197F 0\n#define BIT_MASK_VI_ADMITTED_TIME_8197F 0xffff\n#define BIT_VI_ADMITTED_TIME_8197F(x)                                          \\\n\t(((x) & BIT_MASK_VI_ADMITTED_TIME_8197F)                               \\\n\t << BIT_SHIFT_VI_ADMITTED_TIME_8197F)\n#define BITS_VI_ADMITTED_TIME_8197F                                            \\\n\t(BIT_MASK_VI_ADMITTED_TIME_8197F << BIT_SHIFT_VI_ADMITTED_TIME_8197F)\n#define BIT_CLEAR_VI_ADMITTED_TIME_8197F(x)                                    \\\n\t((x) & (~BITS_VI_ADMITTED_TIME_8197F))\n#define BIT_GET_VI_ADMITTED_TIME_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8197F) &                           \\\n\t BIT_MASK_VI_ADMITTED_TIME_8197F)\n#define BIT_SET_VI_ADMITTED_TIME_8197F(x, v)                                   \\\n\t(BIT_CLEAR_VI_ADMITTED_TIME_8197F(x) | BIT_VI_ADMITTED_TIME_8197F(v))\n\n/* 2 REG_BE_ADMTIME_8197F */\n\n#define BIT_SHIFT_BE_ADMITTED_TIME_8197F 0\n#define BIT_MASK_BE_ADMITTED_TIME_8197F 0xffff\n#define BIT_BE_ADMITTED_TIME_8197F(x)                                          \\\n\t(((x) & BIT_MASK_BE_ADMITTED_TIME_8197F)                               \\\n\t << BIT_SHIFT_BE_ADMITTED_TIME_8197F)\n#define BITS_BE_ADMITTED_TIME_8197F                                            \\\n\t(BIT_MASK_BE_ADMITTED_TIME_8197F << BIT_SHIFT_BE_ADMITTED_TIME_8197F)\n#define BIT_CLEAR_BE_ADMITTED_TIME_8197F(x)                                    \\\n\t((x) & (~BITS_BE_ADMITTED_TIME_8197F))\n#define BIT_GET_BE_ADMITTED_TIME_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8197F) &                           \\\n\t BIT_MASK_BE_ADMITTED_TIME_8197F)\n#define BIT_SET_BE_ADMITTED_TIME_8197F(x, v)                                   \\\n\t(BIT_CLEAR_BE_ADMITTED_TIME_8197F(x) | BIT_BE_ADMITTED_TIME_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n#define BIT_CHANGE_POW_BCN_AREA_8197F BIT(9)\n\n/* 2 REG_EDCA_RANDOM_GEN_8197F */\n\n#define BIT_SHIFT_RANDOM_GEN_8197F 0\n#define BIT_MASK_RANDOM_GEN_8197F 0xffffff\n#define BIT_RANDOM_GEN_8197F(x)                                                \\\n\t(((x) & BIT_MASK_RANDOM_GEN_8197F) << BIT_SHIFT_RANDOM_GEN_8197F)\n#define BITS_RANDOM_GEN_8197F                                                  \\\n\t(BIT_MASK_RANDOM_GEN_8197F << BIT_SHIFT_RANDOM_GEN_8197F)\n#define BIT_CLEAR_RANDOM_GEN_8197F(x) ((x) & (~BITS_RANDOM_GEN_8197F))\n#define BIT_GET_RANDOM_GEN_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_RANDOM_GEN_8197F) & BIT_MASK_RANDOM_GEN_8197F)\n#define BIT_SET_RANDOM_GEN_8197F(x, v)                                         \\\n\t(BIT_CLEAR_RANDOM_GEN_8197F(x) | BIT_RANDOM_GEN_8197F(v))\n\n/* 2 REG_TXCMD_NOA_SEL_8197F */\n\n#define BIT_SHIFT_NOA_SEL_V2_8197F 4\n#define BIT_MASK_NOA_SEL_V2_8197F 0x7\n#define BIT_NOA_SEL_V2_8197F(x)                                                \\\n\t(((x) & BIT_MASK_NOA_SEL_V2_8197F) << BIT_SHIFT_NOA_SEL_V2_8197F)\n#define BITS_NOA_SEL_V2_8197F                                                  \\\n\t(BIT_MASK_NOA_SEL_V2_8197F << BIT_SHIFT_NOA_SEL_V2_8197F)\n#define BIT_CLEAR_NOA_SEL_V2_8197F(x) ((x) & (~BITS_NOA_SEL_V2_8197F))\n#define BIT_GET_NOA_SEL_V2_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_NOA_SEL_V2_8197F) & BIT_MASK_NOA_SEL_V2_8197F)\n#define BIT_SET_NOA_SEL_V2_8197F(x, v)                                         \\\n\t(BIT_CLEAR_NOA_SEL_V2_8197F(x) | BIT_NOA_SEL_V2_8197F(v))\n\n#define BIT_SHIFT_TXCMD_SEG_SEL_8197F 0\n#define BIT_MASK_TXCMD_SEG_SEL_8197F 0xf\n#define BIT_TXCMD_SEG_SEL_8197F(x)                                             \\\n\t(((x) & BIT_MASK_TXCMD_SEG_SEL_8197F) << BIT_SHIFT_TXCMD_SEG_SEL_8197F)\n#define BITS_TXCMD_SEG_SEL_8197F                                               \\\n\t(BIT_MASK_TXCMD_SEG_SEL_8197F << BIT_SHIFT_TXCMD_SEG_SEL_8197F)\n#define BIT_CLEAR_TXCMD_SEG_SEL_8197F(x) ((x) & (~BITS_TXCMD_SEG_SEL_8197F))\n#define BIT_GET_TXCMD_SEG_SEL_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8197F) & BIT_MASK_TXCMD_SEG_SEL_8197F)\n#define BIT_SET_TXCMD_SEG_SEL_8197F(x, v)                                      \\\n\t(BIT_CLEAR_TXCMD_SEG_SEL_8197F(x) | BIT_TXCMD_SEG_SEL_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n#define BIT_BCNERR_CNT_EN_8197F BIT(20)\n\n#define BIT_SHIFT_BCNERR_PORT_SEL_8197F 16\n#define BIT_MASK_BCNERR_PORT_SEL_8197F 0x7\n#define BIT_BCNERR_PORT_SEL_8197F(x)                                           \\\n\t(((x) & BIT_MASK_BCNERR_PORT_SEL_8197F)                                \\\n\t << BIT_SHIFT_BCNERR_PORT_SEL_8197F)\n#define BITS_BCNERR_PORT_SEL_8197F                                             \\\n\t(BIT_MASK_BCNERR_PORT_SEL_8197F << BIT_SHIFT_BCNERR_PORT_SEL_8197F)\n#define BIT_CLEAR_BCNERR_PORT_SEL_8197F(x) ((x) & (~BITS_BCNERR_PORT_SEL_8197F))\n#define BIT_GET_BCNERR_PORT_SEL_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_BCNERR_PORT_SEL_8197F) &                            \\\n\t BIT_MASK_BCNERR_PORT_SEL_8197F)\n#define BIT_SET_BCNERR_PORT_SEL_8197F(x, v)                                    \\\n\t(BIT_CLEAR_BCNERR_PORT_SEL_8197F(x) | BIT_BCNERR_PORT_SEL_8197F(v))\n\n#define BIT_SHIFT_TXPAUSE1_8197F 8\n#define BIT_MASK_TXPAUSE1_8197F 0xff\n#define BIT_TXPAUSE1_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_TXPAUSE1_8197F) << BIT_SHIFT_TXPAUSE1_8197F)\n#define BITS_TXPAUSE1_8197F                                                    \\\n\t(BIT_MASK_TXPAUSE1_8197F << BIT_SHIFT_TXPAUSE1_8197F)\n#define BIT_CLEAR_TXPAUSE1_8197F(x) ((x) & (~BITS_TXPAUSE1_8197F))\n#define BIT_GET_TXPAUSE1_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXPAUSE1_8197F) & BIT_MASK_TXPAUSE1_8197F)\n#define BIT_SET_TXPAUSE1_8197F(x, v)                                           \\\n\t(BIT_CLEAR_TXPAUSE1_8197F(x) | BIT_TXPAUSE1_8197F(v))\n\n#define BIT_SHIFT_BW_CFG_8197F 0\n#define BIT_MASK_BW_CFG_8197F 0x3\n#define BIT_BW_CFG_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_BW_CFG_8197F) << BIT_SHIFT_BW_CFG_8197F)\n#define BITS_BW_CFG_8197F (BIT_MASK_BW_CFG_8197F << BIT_SHIFT_BW_CFG_8197F)\n#define BIT_CLEAR_BW_CFG_8197F(x) ((x) & (~BITS_BW_CFG_8197F))\n#define BIT_GET_BW_CFG_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_BW_CFG_8197F) & BIT_MASK_BW_CFG_8197F)\n#define BIT_SET_BW_CFG_8197F(x, v)                                             \\\n\t(BIT_CLEAR_BW_CFG_8197F(x) | BIT_BW_CFG_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n#define BIT_SHIFT_RXBCN_TIMER_8197F 16\n#define BIT_MASK_RXBCN_TIMER_8197F 0xffff\n#define BIT_RXBCN_TIMER_8197F(x)                                               \\\n\t(((x) & BIT_MASK_RXBCN_TIMER_8197F) << BIT_SHIFT_RXBCN_TIMER_8197F)\n#define BITS_RXBCN_TIMER_8197F                                                 \\\n\t(BIT_MASK_RXBCN_TIMER_8197F << BIT_SHIFT_RXBCN_TIMER_8197F)\n#define BIT_CLEAR_RXBCN_TIMER_8197F(x) ((x) & (~BITS_RXBCN_TIMER_8197F))\n#define BIT_GET_RXBCN_TIMER_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_RXBCN_TIMER_8197F) & BIT_MASK_RXBCN_TIMER_8197F)\n#define BIT_SET_RXBCN_TIMER_8197F(x, v)                                        \\\n\t(BIT_CLEAR_RXBCN_TIMER_8197F(x) | BIT_RXBCN_TIMER_8197F(v))\n\n#define BIT_SHIFT_BCN_ELY_ADJ_8197F 0\n#define BIT_MASK_BCN_ELY_ADJ_8197F 0xffff\n#define BIT_BCN_ELY_ADJ_8197F(x)                                               \\\n\t(((x) & BIT_MASK_BCN_ELY_ADJ_8197F) << BIT_SHIFT_BCN_ELY_ADJ_8197F)\n#define BITS_BCN_ELY_ADJ_8197F                                                 \\\n\t(BIT_MASK_BCN_ELY_ADJ_8197F << BIT_SHIFT_BCN_ELY_ADJ_8197F)\n#define BIT_CLEAR_BCN_ELY_ADJ_8197F(x) ((x) & (~BITS_BCN_ELY_ADJ_8197F))\n#define BIT_GET_BCN_ELY_ADJ_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_BCN_ELY_ADJ_8197F) & BIT_MASK_BCN_ELY_ADJ_8197F)\n#define BIT_SET_BCN_ELY_ADJ_8197F(x, v)                                        \\\n\t(BIT_CLEAR_BCN_ELY_ADJ_8197F(x) | BIT_BCN_ELY_ADJ_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n#define BIT_SHIFT_BCNERR_CNT_OTHERS_8197F 24\n#define BIT_MASK_BCNERR_CNT_OTHERS_8197F 0xff\n#define BIT_BCNERR_CNT_OTHERS_8197F(x)                                         \\\n\t(((x) & BIT_MASK_BCNERR_CNT_OTHERS_8197F)                              \\\n\t << BIT_SHIFT_BCNERR_CNT_OTHERS_8197F)\n#define BITS_BCNERR_CNT_OTHERS_8197F                                           \\\n\t(BIT_MASK_BCNERR_CNT_OTHERS_8197F << BIT_SHIFT_BCNERR_CNT_OTHERS_8197F)\n#define BIT_CLEAR_BCNERR_CNT_OTHERS_8197F(x)                                   \\\n\t((x) & (~BITS_BCNERR_CNT_OTHERS_8197F))\n#define BIT_GET_BCNERR_CNT_OTHERS_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) &                          \\\n\t BIT_MASK_BCNERR_CNT_OTHERS_8197F)\n#define BIT_SET_BCNERR_CNT_OTHERS_8197F(x, v)                                  \\\n\t(BIT_CLEAR_BCNERR_CNT_OTHERS_8197F(x) | BIT_BCNERR_CNT_OTHERS_8197F(v))\n\n#define BIT_SHIFT_BCNERR_CNT_INVALID_8197F 16\n#define BIT_MASK_BCNERR_CNT_INVALID_8197F 0xff\n#define BIT_BCNERR_CNT_INVALID_8197F(x)                                        \\\n\t(((x) & BIT_MASK_BCNERR_CNT_INVALID_8197F)                             \\\n\t << BIT_SHIFT_BCNERR_CNT_INVALID_8197F)\n#define BITS_BCNERR_CNT_INVALID_8197F                                          \\\n\t(BIT_MASK_BCNERR_CNT_INVALID_8197F                                     \\\n\t << BIT_SHIFT_BCNERR_CNT_INVALID_8197F)\n#define BIT_CLEAR_BCNERR_CNT_INVALID_8197F(x)                                  \\\n\t((x) & (~BITS_BCNERR_CNT_INVALID_8197F))\n#define BIT_GET_BCNERR_CNT_INVALID_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_BCNERR_CNT_INVALID_8197F) &                         \\\n\t BIT_MASK_BCNERR_CNT_INVALID_8197F)\n#define BIT_SET_BCNERR_CNT_INVALID_8197F(x, v)                                 \\\n\t(BIT_CLEAR_BCNERR_CNT_INVALID_8197F(x) |                               \\\n\t BIT_BCNERR_CNT_INVALID_8197F(v))\n\n#define BIT_SHIFT_BCNERR_CNT_MAC_8197F 8\n#define BIT_MASK_BCNERR_CNT_MAC_8197F 0xff\n#define BIT_BCNERR_CNT_MAC_8197F(x)                                            \\\n\t(((x) & BIT_MASK_BCNERR_CNT_MAC_8197F)                                 \\\n\t << BIT_SHIFT_BCNERR_CNT_MAC_8197F)\n#define BITS_BCNERR_CNT_MAC_8197F                                              \\\n\t(BIT_MASK_BCNERR_CNT_MAC_8197F << BIT_SHIFT_BCNERR_CNT_MAC_8197F)\n#define BIT_CLEAR_BCNERR_CNT_MAC_8197F(x) ((x) & (~BITS_BCNERR_CNT_MAC_8197F))\n#define BIT_GET_BCNERR_CNT_MAC_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNERR_CNT_MAC_8197F) &                             \\\n\t BIT_MASK_BCNERR_CNT_MAC_8197F)\n#define BIT_SET_BCNERR_CNT_MAC_8197F(x, v)                                     \\\n\t(BIT_CLEAR_BCNERR_CNT_MAC_8197F(x) | BIT_BCNERR_CNT_MAC_8197F(v))\n\n#define BIT_SHIFT_BCNERR_CNT_CCA_8197F 0\n#define BIT_MASK_BCNERR_CNT_CCA_8197F 0xff\n#define BIT_BCNERR_CNT_CCA_8197F(x)                                            \\\n\t(((x) & BIT_MASK_BCNERR_CNT_CCA_8197F)                                 \\\n\t << BIT_SHIFT_BCNERR_CNT_CCA_8197F)\n#define BITS_BCNERR_CNT_CCA_8197F                                              \\\n\t(BIT_MASK_BCNERR_CNT_CCA_8197F << BIT_SHIFT_BCNERR_CNT_CCA_8197F)\n#define BIT_CLEAR_BCNERR_CNT_CCA_8197F(x) ((x) & (~BITS_BCNERR_CNT_CCA_8197F))\n#define BIT_GET_BCNERR_CNT_CCA_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNERR_CNT_CCA_8197F) &                             \\\n\t BIT_MASK_BCNERR_CNT_CCA_8197F)\n#define BIT_SET_BCNERR_CNT_CCA_8197F(x, v)                                     \\\n\t(BIT_CLEAR_BCNERR_CNT_CCA_8197F(x) | BIT_BCNERR_CNT_CCA_8197F(v))\n\n/* 2 REG_NOA_PARAM_8197F */\n\n#define BIT_SHIFT_NOA_COUNT_8197F (96 & CPU_OPT_WIDTH)\n#define BIT_MASK_NOA_COUNT_8197F 0xff\n#define BIT_NOA_COUNT_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_NOA_COUNT_8197F) << BIT_SHIFT_NOA_COUNT_8197F)\n#define BITS_NOA_COUNT_8197F                                                   \\\n\t(BIT_MASK_NOA_COUNT_8197F << BIT_SHIFT_NOA_COUNT_8197F)\n#define BIT_CLEAR_NOA_COUNT_8197F(x) ((x) & (~BITS_NOA_COUNT_8197F))\n#define BIT_GET_NOA_COUNT_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_NOA_COUNT_8197F) & BIT_MASK_NOA_COUNT_8197F)\n#define BIT_SET_NOA_COUNT_8197F(x, v)                                          \\\n\t(BIT_CLEAR_NOA_COUNT_8197F(x) | BIT_NOA_COUNT_8197F(v))\n\n#define BIT_SHIFT_NOA_START_TIME_8197F (64 & CPU_OPT_WIDTH)\n#define BIT_MASK_NOA_START_TIME_8197F 0xffffffffL\n#define BIT_NOA_START_TIME_8197F(x)                                            \\\n\t(((x) & BIT_MASK_NOA_START_TIME_8197F)                                 \\\n\t << BIT_SHIFT_NOA_START_TIME_8197F)\n#define BITS_NOA_START_TIME_8197F                                              \\\n\t(BIT_MASK_NOA_START_TIME_8197F << BIT_SHIFT_NOA_START_TIME_8197F)\n#define BIT_CLEAR_NOA_START_TIME_8197F(x) ((x) & (~BITS_NOA_START_TIME_8197F))\n#define BIT_GET_NOA_START_TIME_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_NOA_START_TIME_8197F) &                             \\\n\t BIT_MASK_NOA_START_TIME_8197F)\n#define BIT_SET_NOA_START_TIME_8197F(x, v)                                     \\\n\t(BIT_CLEAR_NOA_START_TIME_8197F(x) | BIT_NOA_START_TIME_8197F(v))\n\n#define BIT_SHIFT_NOA_INTERVAL_8197F (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_NOA_INTERVAL_8197F 0xffffffffL\n#define BIT_NOA_INTERVAL_8197F(x)                                              \\\n\t(((x) & BIT_MASK_NOA_INTERVAL_8197F) << BIT_SHIFT_NOA_INTERVAL_8197F)\n#define BITS_NOA_INTERVAL_8197F                                                \\\n\t(BIT_MASK_NOA_INTERVAL_8197F << BIT_SHIFT_NOA_INTERVAL_8197F)\n#define BIT_CLEAR_NOA_INTERVAL_8197F(x) ((x) & (~BITS_NOA_INTERVAL_8197F))\n#define BIT_GET_NOA_INTERVAL_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_NOA_INTERVAL_8197F) & BIT_MASK_NOA_INTERVAL_8197F)\n#define BIT_SET_NOA_INTERVAL_8197F(x, v)                                       \\\n\t(BIT_CLEAR_NOA_INTERVAL_8197F(x) | BIT_NOA_INTERVAL_8197F(v))\n\n#define BIT_SHIFT_NOA_DURATION_8197F 0\n#define BIT_MASK_NOA_DURATION_8197F 0xffffffffL\n#define BIT_NOA_DURATION_8197F(x)                                              \\\n\t(((x) & BIT_MASK_NOA_DURATION_8197F) << BIT_SHIFT_NOA_DURATION_8197F)\n#define BITS_NOA_DURATION_8197F                                                \\\n\t(BIT_MASK_NOA_DURATION_8197F << BIT_SHIFT_NOA_DURATION_8197F)\n#define BIT_CLEAR_NOA_DURATION_8197F(x) ((x) & (~BITS_NOA_DURATION_8197F))\n#define BIT_GET_NOA_DURATION_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_NOA_DURATION_8197F) & BIT_MASK_NOA_DURATION_8197F)\n#define BIT_SET_NOA_DURATION_8197F(x, v)                                       \\\n\t(BIT_CLEAR_NOA_DURATION_8197F(x) | BIT_NOA_DURATION_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_P2P_RST_8197F */\n#define BIT_P2P2_PWR_RST1_8197F BIT(5)\n#define BIT_P2P2_PWR_RST0_8197F BIT(4)\n#define BIT_P2P1_PWR_RST1_8197F BIT(3)\n#define BIT_P2P1_PWR_RST0_8197F BIT(2)\n#define BIT_P2P_PWR_RST1_V1_8197F BIT(1)\n#define BIT_P2P_PWR_RST0_V1_8197F BIT(0)\n\n/* 2 REG_SCHEDULER_RST_8197F */\n#define BIT_SYNC_TSF_NOW_8197F BIT(2)\n#define BIT_SYNC_CLI_8197F BIT(1)\n#define BIT_SCHEDULER_RST_V1_8197F BIT(0)\n\n/* 2 REG_SCH_TXCMD_8197F */\n\n#define BIT_SHIFT_SCH_TXCMD_8197F 0\n#define BIT_MASK_SCH_TXCMD_8197F 0xffffffffL\n#define BIT_SCH_TXCMD_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_SCH_TXCMD_8197F) << BIT_SHIFT_SCH_TXCMD_8197F)\n#define BITS_SCH_TXCMD_8197F                                                   \\\n\t(BIT_MASK_SCH_TXCMD_8197F << BIT_SHIFT_SCH_TXCMD_8197F)\n#define BIT_CLEAR_SCH_TXCMD_8197F(x) ((x) & (~BITS_SCH_TXCMD_8197F))\n#define BIT_GET_SCH_TXCMD_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_SCH_TXCMD_8197F) & BIT_MASK_SCH_TXCMD_8197F)\n#define BIT_SET_SCH_TXCMD_8197F(x, v)                                          \\\n\t(BIT_CLEAR_SCH_TXCMD_8197F(x) | BIT_SCH_TXCMD_8197F(v))\n\n/* 2 REG_PAGE5_DUMMY_8197F */\n\n/* 2 REG_CPUMGQ_TX_TIMER_8197F */\n\n#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F 0\n#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F 0xffffffffL\n#define BIT_CPUMGQ_TX_TIMER_V1_8197F(x)                                        \\\n\t(((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F)                             \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F)\n#define BITS_CPUMGQ_TX_TIMER_V1_8197F                                          \\\n\t(BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F                                     \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F)\n#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8197F(x)                                  \\\n\t((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8197F))\n#define BIT_GET_CPUMGQ_TX_TIMER_V1_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) &                         \\\n\t BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F)\n#define BIT_SET_CPUMGQ_TX_TIMER_V1_8197F(x, v)                                 \\\n\t(BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8197F(x) |                               \\\n\t BIT_CPUMGQ_TX_TIMER_V1_8197F(v))\n\n/* 2 REG_PS_TIMER_A_8197F */\n\n#define BIT_SHIFT_PS_TIMER_A_V1_8197F 0\n#define BIT_MASK_PS_TIMER_A_V1_8197F 0xffffffffL\n#define BIT_PS_TIMER_A_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_PS_TIMER_A_V1_8197F) << BIT_SHIFT_PS_TIMER_A_V1_8197F)\n#define BITS_PS_TIMER_A_V1_8197F                                               \\\n\t(BIT_MASK_PS_TIMER_A_V1_8197F << BIT_SHIFT_PS_TIMER_A_V1_8197F)\n#define BIT_CLEAR_PS_TIMER_A_V1_8197F(x) ((x) & (~BITS_PS_TIMER_A_V1_8197F))\n#define BIT_GET_PS_TIMER_A_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_A_V1_8197F) & BIT_MASK_PS_TIMER_A_V1_8197F)\n#define BIT_SET_PS_TIMER_A_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_PS_TIMER_A_V1_8197F(x) | BIT_PS_TIMER_A_V1_8197F(v))\n\n/* 2 REG_PS_TIMER_B_8197F */\n\n#define BIT_SHIFT_PS_TIMER_B_V1_8197F 0\n#define BIT_MASK_PS_TIMER_B_V1_8197F 0xffffffffL\n#define BIT_PS_TIMER_B_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_PS_TIMER_B_V1_8197F) << BIT_SHIFT_PS_TIMER_B_V1_8197F)\n#define BITS_PS_TIMER_B_V1_8197F                                               \\\n\t(BIT_MASK_PS_TIMER_B_V1_8197F << BIT_SHIFT_PS_TIMER_B_V1_8197F)\n#define BIT_CLEAR_PS_TIMER_B_V1_8197F(x) ((x) & (~BITS_PS_TIMER_B_V1_8197F))\n#define BIT_GET_PS_TIMER_B_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_B_V1_8197F) & BIT_MASK_PS_TIMER_B_V1_8197F)\n#define BIT_SET_PS_TIMER_B_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_PS_TIMER_B_V1_8197F(x) | BIT_PS_TIMER_B_V1_8197F(v))\n\n/* 2 REG_PS_TIMER_C_8197F */\n\n#define BIT_SHIFT_PS_TIMER_C_V1_8197F 0\n#define BIT_MASK_PS_TIMER_C_V1_8197F 0xffffffffL\n#define BIT_PS_TIMER_C_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_PS_TIMER_C_V1_8197F) << BIT_SHIFT_PS_TIMER_C_V1_8197F)\n#define BITS_PS_TIMER_C_V1_8197F                                               \\\n\t(BIT_MASK_PS_TIMER_C_V1_8197F << BIT_SHIFT_PS_TIMER_C_V1_8197F)\n#define BIT_CLEAR_PS_TIMER_C_V1_8197F(x) ((x) & (~BITS_PS_TIMER_C_V1_8197F))\n#define BIT_GET_PS_TIMER_C_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_C_V1_8197F) & BIT_MASK_PS_TIMER_C_V1_8197F)\n#define BIT_SET_PS_TIMER_C_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_PS_TIMER_C_V1_8197F(x) | BIT_PS_TIMER_C_V1_8197F(v))\n\n/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8197F */\n#define BIT_CPUMGQ_TIMER_EN_8197F BIT(31)\n#define BIT_CPUMGQ_TX_EN_8197F BIT(28)\n\n#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F 24\n#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F 0x7\n#define BIT_CPUMGQ_TIMER_TSF_SEL_8197F(x)                                      \\\n\t(((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F)                           \\\n\t << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F)\n#define BITS_CPUMGQ_TIMER_TSF_SEL_8197F                                        \\\n\t(BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F                                   \\\n\t << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F)\n#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8197F(x)                                \\\n\t((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8197F))\n#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8197F(x)                                  \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) &                       \\\n\t BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F)\n#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8197F(x, v)                               \\\n\t(BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8197F(x) |                             \\\n\t BIT_CPUMGQ_TIMER_TSF_SEL_8197F(v))\n\n#define BIT_PS_TIMER_C_EN_8197F BIT(23)\n\n#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F 16\n#define BIT_MASK_PS_TIMER_C_TSF_SEL_8197F 0x7\n#define BIT_PS_TIMER_C_TSF_SEL_8197F(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8197F)                             \\\n\t << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F)\n#define BITS_PS_TIMER_C_TSF_SEL_8197F                                          \\\n\t(BIT_MASK_PS_TIMER_C_TSF_SEL_8197F                                     \\\n\t << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F)\n#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8197F(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_C_TSF_SEL_8197F))\n#define BIT_GET_PS_TIMER_C_TSF_SEL_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) &                         \\\n\t BIT_MASK_PS_TIMER_C_TSF_SEL_8197F)\n#define BIT_SET_PS_TIMER_C_TSF_SEL_8197F(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_C_TSF_SEL_8197F(x) |                               \\\n\t BIT_PS_TIMER_C_TSF_SEL_8197F(v))\n\n#define BIT_PS_TIMER_B_EN_8197F BIT(15)\n\n#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F 8\n#define BIT_MASK_PS_TIMER_B_TSF_SEL_8197F 0x7\n#define BIT_PS_TIMER_B_TSF_SEL_8197F(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8197F)                             \\\n\t << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F)\n#define BITS_PS_TIMER_B_TSF_SEL_8197F                                          \\\n\t(BIT_MASK_PS_TIMER_B_TSF_SEL_8197F                                     \\\n\t << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F)\n#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8197F(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_B_TSF_SEL_8197F))\n#define BIT_GET_PS_TIMER_B_TSF_SEL_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) &                         \\\n\t BIT_MASK_PS_TIMER_B_TSF_SEL_8197F)\n#define BIT_SET_PS_TIMER_B_TSF_SEL_8197F(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_B_TSF_SEL_8197F(x) |                               \\\n\t BIT_PS_TIMER_B_TSF_SEL_8197F(v))\n\n#define BIT_PS_TIMER_A_EN_8197F BIT(7)\n\n#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F 0\n#define BIT_MASK_PS_TIMER_A_TSF_SEL_8197F 0x7\n#define BIT_PS_TIMER_A_TSF_SEL_8197F(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8197F)                             \\\n\t << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F)\n#define BITS_PS_TIMER_A_TSF_SEL_8197F                                          \\\n\t(BIT_MASK_PS_TIMER_A_TSF_SEL_8197F                                     \\\n\t << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F)\n#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8197F(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_A_TSF_SEL_8197F))\n#define BIT_GET_PS_TIMER_A_TSF_SEL_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) &                         \\\n\t BIT_MASK_PS_TIMER_A_TSF_SEL_8197F)\n#define BIT_SET_PS_TIMER_A_TSF_SEL_8197F(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_A_TSF_SEL_8197F(x) |                               \\\n\t BIT_PS_TIMER_A_TSF_SEL_8197F(v))\n\n/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8197F */\n\n#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F 0\n#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F 0xff\n#define BIT_CPUMGQ_TX_TIMER_EARLY_8197F(x)                                     \\\n\t(((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F)                          \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F)\n#define BITS_CPUMGQ_TX_TIMER_EARLY_8197F                                       \\\n\t(BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F                                  \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F)\n#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8197F(x)                               \\\n\t((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8197F))\n#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8197F(x)                                 \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) &                      \\\n\t BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F)\n#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8197F(x, v)                              \\\n\t(BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8197F(x) |                            \\\n\t BIT_CPUMGQ_TX_TIMER_EARLY_8197F(v))\n\n/* 2 REG_PS_TIMER_A_EARLY_8197F */\n\n#define BIT_SHIFT_PS_TIMER_A_EARLY_8197F 0\n#define BIT_MASK_PS_TIMER_A_EARLY_8197F 0xff\n#define BIT_PS_TIMER_A_EARLY_8197F(x)                                          \\\n\t(((x) & BIT_MASK_PS_TIMER_A_EARLY_8197F)                               \\\n\t << BIT_SHIFT_PS_TIMER_A_EARLY_8197F)\n#define BITS_PS_TIMER_A_EARLY_8197F                                            \\\n\t(BIT_MASK_PS_TIMER_A_EARLY_8197F << BIT_SHIFT_PS_TIMER_A_EARLY_8197F)\n#define BIT_CLEAR_PS_TIMER_A_EARLY_8197F(x)                                    \\\n\t((x) & (~BITS_PS_TIMER_A_EARLY_8197F))\n#define BIT_GET_PS_TIMER_A_EARLY_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8197F) &                           \\\n\t BIT_MASK_PS_TIMER_A_EARLY_8197F)\n#define BIT_SET_PS_TIMER_A_EARLY_8197F(x, v)                                   \\\n\t(BIT_CLEAR_PS_TIMER_A_EARLY_8197F(x) | BIT_PS_TIMER_A_EARLY_8197F(v))\n\n/* 2 REG_PS_TIMER_B_EARLY_8197F */\n\n#define BIT_SHIFT_PS_TIMER_B_EARLY_8197F 0\n#define BIT_MASK_PS_TIMER_B_EARLY_8197F 0xff\n#define BIT_PS_TIMER_B_EARLY_8197F(x)                                          \\\n\t(((x) & BIT_MASK_PS_TIMER_B_EARLY_8197F)                               \\\n\t << BIT_SHIFT_PS_TIMER_B_EARLY_8197F)\n#define BITS_PS_TIMER_B_EARLY_8197F                                            \\\n\t(BIT_MASK_PS_TIMER_B_EARLY_8197F << BIT_SHIFT_PS_TIMER_B_EARLY_8197F)\n#define BIT_CLEAR_PS_TIMER_B_EARLY_8197F(x)                                    \\\n\t((x) & (~BITS_PS_TIMER_B_EARLY_8197F))\n#define BIT_GET_PS_TIMER_B_EARLY_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8197F) &                           \\\n\t BIT_MASK_PS_TIMER_B_EARLY_8197F)\n#define BIT_SET_PS_TIMER_B_EARLY_8197F(x, v)                                   \\\n\t(BIT_CLEAR_PS_TIMER_B_EARLY_8197F(x) | BIT_PS_TIMER_B_EARLY_8197F(v))\n\n/* 2 REG_PS_TIMER_C_EARLY_8197F */\n\n#define BIT_SHIFT_PS_TIMER_C_EARLY_8197F 0\n#define BIT_MASK_PS_TIMER_C_EARLY_8197F 0xff\n#define BIT_PS_TIMER_C_EARLY_8197F(x)                                          \\\n\t(((x) & BIT_MASK_PS_TIMER_C_EARLY_8197F)                               \\\n\t << BIT_SHIFT_PS_TIMER_C_EARLY_8197F)\n#define BITS_PS_TIMER_C_EARLY_8197F                                            \\\n\t(BIT_MASK_PS_TIMER_C_EARLY_8197F << BIT_SHIFT_PS_TIMER_C_EARLY_8197F)\n#define BIT_CLEAR_PS_TIMER_C_EARLY_8197F(x)                                    \\\n\t((x) & (~BITS_PS_TIMER_C_EARLY_8197F))\n#define BIT_GET_PS_TIMER_C_EARLY_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8197F) &                           \\\n\t BIT_MASK_PS_TIMER_C_EARLY_8197F)\n#define BIT_SET_PS_TIMER_C_EARLY_8197F(x, v)                                   \\\n\t(BIT_CLEAR_PS_TIMER_C_EARLY_8197F(x) | BIT_PS_TIMER_C_EARLY_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n#define BIT_STOP_CPUMGQ_8197F BIT(16)\n\n#define BIT_SHIFT_CPUMGQ_PARAMETER_8197F 0\n#define BIT_MASK_CPUMGQ_PARAMETER_8197F 0xffff\n#define BIT_CPUMGQ_PARAMETER_8197F(x)                                          \\\n\t(((x) & BIT_MASK_CPUMGQ_PARAMETER_8197F)                               \\\n\t << BIT_SHIFT_CPUMGQ_PARAMETER_8197F)\n#define BITS_CPUMGQ_PARAMETER_8197F                                            \\\n\t(BIT_MASK_CPUMGQ_PARAMETER_8197F << BIT_SHIFT_CPUMGQ_PARAMETER_8197F)\n#define BIT_CLEAR_CPUMGQ_PARAMETER_8197F(x)                                    \\\n\t((x) & (~BITS_CPUMGQ_PARAMETER_8197F))\n#define BIT_GET_CPUMGQ_PARAMETER_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_PARAMETER_8197F) &                           \\\n\t BIT_MASK_CPUMGQ_PARAMETER_8197F)\n#define BIT_SET_CPUMGQ_PARAMETER_8197F(x, v)                                   \\\n\t(BIT_CLEAR_CPUMGQ_PARAMETER_8197F(x) | BIT_CPUMGQ_PARAMETER_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_BWOPMODE_8197F (BW OPERATION MODE REGISTER) */\n\n/* 2 REG_WMAC_FWPKT_CR_8197F */\n#define BIT_FWEN_8197F BIT(7)\n#define BIT_PHYSTS_PKT_CTRL_8197F BIT(6)\n#define BIT_APPHDR_MIDSRCH_FAIL_8197F BIT(4)\n#define BIT_FWPARSING_EN_8197F BIT(3)\n\n#define BIT_SHIFT_APPEND_MHDR_LEN_8197F 0\n#define BIT_MASK_APPEND_MHDR_LEN_8197F 0x7\n#define BIT_APPEND_MHDR_LEN_8197F(x)                                           \\\n\t(((x) & BIT_MASK_APPEND_MHDR_LEN_8197F)                                \\\n\t << BIT_SHIFT_APPEND_MHDR_LEN_8197F)\n#define BITS_APPEND_MHDR_LEN_8197F                                             \\\n\t(BIT_MASK_APPEND_MHDR_LEN_8197F << BIT_SHIFT_APPEND_MHDR_LEN_8197F)\n#define BIT_CLEAR_APPEND_MHDR_LEN_8197F(x) ((x) & (~BITS_APPEND_MHDR_LEN_8197F))\n#define BIT_GET_APPEND_MHDR_LEN_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8197F) &                            \\\n\t BIT_MASK_APPEND_MHDR_LEN_8197F)\n#define BIT_SET_APPEND_MHDR_LEN_8197F(x, v)                                    \\\n\t(BIT_CLEAR_APPEND_MHDR_LEN_8197F(x) | BIT_APPEND_MHDR_LEN_8197F(v))\n\n/* 2 REG_WMAC_CR_8197F (WMAC CR AND APSD CONTROL REGISTER) */\n#define BIT_APSDOFF_8197F BIT(6)\n#define BIT_IC_MACPHY_M_8197F BIT(0)\n\n/* 2 REG_TCR_8197F (TRANSMISSION CONFIGURATION REGISTER) */\n#define BIT_WMAC_EN_RTS_ADDR_8197F BIT(31)\n#define BIT_WMAC_DISABLE_CCK_8197F BIT(30)\n#define BIT_WMAC_RAW_LEN_8197F BIT(29)\n#define BIT_WMAC_NOTX_IN_RXNDP_8197F BIT(28)\n#define BIT_WMAC_EN_EOF_8197F BIT(27)\n#define BIT_WMAC_BF_SEL_8197F BIT(26)\n#define BIT_WMAC_ANTMODE_SEL_8197F BIT(25)\n#define BIT_WMAC_TCRPWRMGT_HWCTL_8197F BIT(24)\n#define BIT_WMAC_SMOOTH_VAL_8197F BIT(23)\n#define BIT_UNDERFLOWEN_CMPLEN_SEL_8197F BIT(21)\n#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8197F BIT(20)\n#define BIT_WMAC_TCR_EN_20MST_8197F BIT(19)\n#define BIT_WMAC_DIS_SIGTA_8197F BIT(18)\n#define BIT_WMAC_DIS_A2B0_8197F BIT(17)\n#define BIT_WMAC_MSK_SIGBCRC_8197F BIT(16)\n#define BIT_WMAC_TCR_ERRSTEN_3_8197F BIT(15)\n#define BIT_WMAC_TCR_ERRSTEN_2_8197F BIT(14)\n#define BIT_WMAC_TCR_ERRSTEN_1_8197F BIT(13)\n#define BIT_WMAC_TCR_ERRSTEN_0_8197F BIT(12)\n#define BIT_WMAC_TCR_TXSK_PERPKT_8197F BIT(11)\n#define BIT_ICV_8197F BIT(10)\n#define BIT_CFEND_FORMAT_8197F BIT(9)\n#define BIT_CRC_8197F BIT(8)\n#define BIT_PWRBIT_OW_EN_8197F BIT(7)\n#define BIT_PWR_ST_8197F BIT(6)\n#define BIT_WMAC_TCR_UPD_TIMIE_8197F BIT(5)\n#define BIT_WMAC_TCR_UPD_HGQMD_8197F BIT(4)\n#define BIT_VHTSIGA1_TXPS_8197F BIT(3)\n#define BIT_PAD_SEL_8197F BIT(2)\n#define BIT_DIS_GCLK_8197F BIT(1)\n\n/* 2 REG_RCR_8197F (RECEIVE CONFIGURATION REGISTER) */\n#define BIT_APP_FCS_8197F BIT(31)\n#define BIT_APP_MIC_8197F BIT(30)\n#define BIT_APP_ICV_8197F BIT(29)\n#define BIT_APP_PHYSTS_8197F BIT(28)\n#define BIT_APP_BASSN_8197F BIT(27)\n#define BIT_VHT_DACK_8197F BIT(26)\n#define BIT_TCPOFLD_EN_8197F BIT(25)\n#define BIT_ENMBID_8197F BIT(24)\n#define BIT_LSIGEN_8197F BIT(23)\n#define BIT_MFBEN_8197F BIT(22)\n#define BIT_DISCHKPPDLLEN_8197F BIT(21)\n#define BIT_PKTCTL_DLEN_8197F BIT(20)\n#define BIT_TIM_PARSER_EN_8197F BIT(18)\n#define BIT_BC_MD_EN_8197F BIT(17)\n#define BIT_UC_MD_EN_8197F BIT(16)\n#define BIT_RXSK_PERPKT_8197F BIT(15)\n#define BIT_HTC_LOC_CTRL_8197F BIT(14)\n#define BIT_TA_BCN_8197F BIT(11)\n#define BIT_DISDECMYPKT_8197F BIT(10)\n#define BIT_AICV_8197F BIT(9)\n#define BIT_ACRC32_8197F BIT(8)\n#define BIT_CBSSID_BCN_8197F BIT(7)\n#define BIT_CBSSID_DATA_8197F BIT(6)\n#define BIT_APWRMGT_8197F BIT(5)\n#define BIT_ADD3_8197F BIT(4)\n#define BIT_AB_8197F BIT(3)\n#define BIT_AM_8197F BIT(2)\n#define BIT_APM_8197F BIT(1)\n#define BIT_AAP_8197F BIT(0)\n\n/* 2 REG_RX_DRVINFO_SZ_8197F (RX DRIVER INFO SIZE REGISTER) */\n#define BIT_APP_PHYSTS_PER_SUBMPDU_8197F BIT(7)\n#define BIT_APP_MH_SHIFT_VAL_8197F BIT(6)\n#define BIT_WMAC_ENSHIFT_8197F BIT(5)\n\n#define BIT_SHIFT_DRVINFO_SZ_V1_8197F 0\n#define BIT_MASK_DRVINFO_SZ_V1_8197F 0xf\n#define BIT_DRVINFO_SZ_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_DRVINFO_SZ_V1_8197F) << BIT_SHIFT_DRVINFO_SZ_V1_8197F)\n#define BITS_DRVINFO_SZ_V1_8197F                                               \\\n\t(BIT_MASK_DRVINFO_SZ_V1_8197F << BIT_SHIFT_DRVINFO_SZ_V1_8197F)\n#define BIT_CLEAR_DRVINFO_SZ_V1_8197F(x) ((x) & (~BITS_DRVINFO_SZ_V1_8197F))\n#define BIT_GET_DRVINFO_SZ_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8197F) & BIT_MASK_DRVINFO_SZ_V1_8197F)\n#define BIT_SET_DRVINFO_SZ_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_DRVINFO_SZ_V1_8197F(x) | BIT_DRVINFO_SZ_V1_8197F(v))\n\n/* 2 REG_RX_DLK_TIME_8197F (RX DEADLOCK TIME REGISTER) */\n\n#define BIT_SHIFT_RX_DLK_TIME_8197F 0\n#define BIT_MASK_RX_DLK_TIME_8197F 0xff\n#define BIT_RX_DLK_TIME_8197F(x)                                               \\\n\t(((x) & BIT_MASK_RX_DLK_TIME_8197F) << BIT_SHIFT_RX_DLK_TIME_8197F)\n#define BITS_RX_DLK_TIME_8197F                                                 \\\n\t(BIT_MASK_RX_DLK_TIME_8197F << BIT_SHIFT_RX_DLK_TIME_8197F)\n#define BIT_CLEAR_RX_DLK_TIME_8197F(x) ((x) & (~BITS_RX_DLK_TIME_8197F))\n#define BIT_GET_RX_DLK_TIME_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_RX_DLK_TIME_8197F) & BIT_MASK_RX_DLK_TIME_8197F)\n#define BIT_SET_RX_DLK_TIME_8197F(x, v)                                        \\\n\t(BIT_CLEAR_RX_DLK_TIME_8197F(x) | BIT_RX_DLK_TIME_8197F(v))\n\n/* 2 REG_RX_PKT_LIMIT_8197F (RX PACKET LENGTH LIMIT REGISTER) */\n\n#define BIT_SHIFT_RXPKTLMT_8197F 0\n#define BIT_MASK_RXPKTLMT_8197F 0x3f\n#define BIT_RXPKTLMT_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_RXPKTLMT_8197F) << BIT_SHIFT_RXPKTLMT_8197F)\n#define BITS_RXPKTLMT_8197F                                                    \\\n\t(BIT_MASK_RXPKTLMT_8197F << BIT_SHIFT_RXPKTLMT_8197F)\n#define BIT_CLEAR_RXPKTLMT_8197F(x) ((x) & (~BITS_RXPKTLMT_8197F))\n#define BIT_GET_RXPKTLMT_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_RXPKTLMT_8197F) & BIT_MASK_RXPKTLMT_8197F)\n#define BIT_SET_RXPKTLMT_8197F(x, v)                                           \\\n\t(BIT_CLEAR_RXPKTLMT_8197F(x) | BIT_RXPKTLMT_8197F(v))\n\n/* 2 REG_MACID_8197F (MAC ID REGISTER) */\n\n#define BIT_SHIFT_MACID_8197F 0\n#define BIT_MASK_MACID_8197F 0xffffffffffffL\n#define BIT_MACID_8197F(x)                                                     \\\n\t(((x) & BIT_MASK_MACID_8197F) << BIT_SHIFT_MACID_8197F)\n#define BITS_MACID_8197F (BIT_MASK_MACID_8197F << BIT_SHIFT_MACID_8197F)\n#define BIT_CLEAR_MACID_8197F(x) ((x) & (~BITS_MACID_8197F))\n#define BIT_GET_MACID_8197F(x)                                                 \\\n\t(((x) >> BIT_SHIFT_MACID_8197F) & BIT_MASK_MACID_8197F)\n#define BIT_SET_MACID_8197F(x, v)                                              \\\n\t(BIT_CLEAR_MACID_8197F(x) | BIT_MACID_8197F(v))\n\n/* 2 REG_BSSID_8197F (BSSID REGISTER) */\n\n#define BIT_SHIFT_BSSID_8197F 0\n#define BIT_MASK_BSSID_8197F 0xffffffffffffL\n#define BIT_BSSID_8197F(x)                                                     \\\n\t(((x) & BIT_MASK_BSSID_8197F) << BIT_SHIFT_BSSID_8197F)\n#define BITS_BSSID_8197F (BIT_MASK_BSSID_8197F << BIT_SHIFT_BSSID_8197F)\n#define BIT_CLEAR_BSSID_8197F(x) ((x) & (~BITS_BSSID_8197F))\n#define BIT_GET_BSSID_8197F(x)                                                 \\\n\t(((x) >> BIT_SHIFT_BSSID_8197F) & BIT_MASK_BSSID_8197F)\n#define BIT_SET_BSSID_8197F(x, v)                                              \\\n\t(BIT_CLEAR_BSSID_8197F(x) | BIT_BSSID_8197F(v))\n\n/* 2 REG_MAR_8197F (MULTICAST ADDRESS REGISTER) */\n\n#define BIT_SHIFT_MAR_8197F 0\n#define BIT_MASK_MAR_8197F 0xffffffffffffffffL\n#define BIT_MAR_8197F(x) (((x) & BIT_MASK_MAR_8197F) << BIT_SHIFT_MAR_8197F)\n#define BITS_MAR_8197F (BIT_MASK_MAR_8197F << BIT_SHIFT_MAR_8197F)\n#define BIT_CLEAR_MAR_8197F(x) ((x) & (~BITS_MAR_8197F))\n#define BIT_GET_MAR_8197F(x) (((x) >> BIT_SHIFT_MAR_8197F) & BIT_MASK_MAR_8197F)\n#define BIT_SET_MAR_8197F(x, v) (BIT_CLEAR_MAR_8197F(x) | BIT_MAR_8197F(v))\n\n/* 2 REG_MBIDCAMCFG_1_8197F (MBSSID CAM CONFIGURATION REGISTER) */\n\n#define BIT_SHIFT_MBIDCAM_RWDATA_L_8197F 0\n#define BIT_MASK_MBIDCAM_RWDATA_L_8197F 0xffffffffL\n#define BIT_MBIDCAM_RWDATA_L_8197F(x)                                          \\\n\t(((x) & BIT_MASK_MBIDCAM_RWDATA_L_8197F)                               \\\n\t << BIT_SHIFT_MBIDCAM_RWDATA_L_8197F)\n#define BITS_MBIDCAM_RWDATA_L_8197F                                            \\\n\t(BIT_MASK_MBIDCAM_RWDATA_L_8197F << BIT_SHIFT_MBIDCAM_RWDATA_L_8197F)\n#define BIT_CLEAR_MBIDCAM_RWDATA_L_8197F(x)                                    \\\n\t((x) & (~BITS_MBIDCAM_RWDATA_L_8197F))\n#define BIT_GET_MBIDCAM_RWDATA_L_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) &                           \\\n\t BIT_MASK_MBIDCAM_RWDATA_L_8197F)\n#define BIT_SET_MBIDCAM_RWDATA_L_8197F(x, v)                                   \\\n\t(BIT_CLEAR_MBIDCAM_RWDATA_L_8197F(x) | BIT_MBIDCAM_RWDATA_L_8197F(v))\n\n/* 2 REG_MBIDCAMCFG_2_8197F (MBSSID CAM CONFIGURATION REGISTER) */\n#define BIT_MBIDCAM_POLL_8197F BIT(31)\n#define BIT_MBIDCAM_WT_EN_8197F BIT(30)\n\n#define BIT_SHIFT_MBIDCAM_ADDR_V1_8197F 24\n#define BIT_MASK_MBIDCAM_ADDR_V1_8197F 0x3f\n#define BIT_MBIDCAM_ADDR_V1_8197F(x)                                           \\\n\t(((x) & BIT_MASK_MBIDCAM_ADDR_V1_8197F)                                \\\n\t << BIT_SHIFT_MBIDCAM_ADDR_V1_8197F)\n#define BITS_MBIDCAM_ADDR_V1_8197F                                             \\\n\t(BIT_MASK_MBIDCAM_ADDR_V1_8197F << BIT_SHIFT_MBIDCAM_ADDR_V1_8197F)\n#define BIT_CLEAR_MBIDCAM_ADDR_V1_8197F(x) ((x) & (~BITS_MBIDCAM_ADDR_V1_8197F))\n#define BIT_GET_MBIDCAM_ADDR_V1_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_MBIDCAM_ADDR_V1_8197F) &                            \\\n\t BIT_MASK_MBIDCAM_ADDR_V1_8197F)\n#define BIT_SET_MBIDCAM_ADDR_V1_8197F(x, v)                                    \\\n\t(BIT_CLEAR_MBIDCAM_ADDR_V1_8197F(x) | BIT_MBIDCAM_ADDR_V1_8197F(v))\n\n#define BIT_MBIDCAM_VALID_8197F BIT(23)\n#define BIT_LSIC_TXOP_EN_8197F BIT(17)\n#define BIT_REPEAT_MODE_EN_8197F BIT(16)\n\n#define BIT_SHIFT_MBIDCAM_RWDATA_H_8197F 0\n#define BIT_MASK_MBIDCAM_RWDATA_H_8197F 0xffff\n#define BIT_MBIDCAM_RWDATA_H_8197F(x)                                          \\\n\t(((x) & BIT_MASK_MBIDCAM_RWDATA_H_8197F)                               \\\n\t << BIT_SHIFT_MBIDCAM_RWDATA_H_8197F)\n#define BITS_MBIDCAM_RWDATA_H_8197F                                            \\\n\t(BIT_MASK_MBIDCAM_RWDATA_H_8197F << BIT_SHIFT_MBIDCAM_RWDATA_H_8197F)\n#define BIT_CLEAR_MBIDCAM_RWDATA_H_8197F(x)                                    \\\n\t((x) & (~BITS_MBIDCAM_RWDATA_H_8197F))\n#define BIT_GET_MBIDCAM_RWDATA_H_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) &                           \\\n\t BIT_MASK_MBIDCAM_RWDATA_H_8197F)\n#define BIT_SET_MBIDCAM_RWDATA_H_8197F(x, v)                                   \\\n\t(BIT_CLEAR_MBIDCAM_RWDATA_H_8197F(x) | BIT_MBIDCAM_RWDATA_H_8197F(v))\n\n/* 2 REG_ZLD_NUM_8197F */\n\n#define BIT_SHIFT_ZLD_NUM_8197F 0\n#define BIT_MASK_ZLD_NUM_8197F 0xff\n#define BIT_ZLD_NUM_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_ZLD_NUM_8197F) << BIT_SHIFT_ZLD_NUM_8197F)\n#define BITS_ZLD_NUM_8197F (BIT_MASK_ZLD_NUM_8197F << BIT_SHIFT_ZLD_NUM_8197F)\n#define BIT_CLEAR_ZLD_NUM_8197F(x) ((x) & (~BITS_ZLD_NUM_8197F))\n#define BIT_GET_ZLD_NUM_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_ZLD_NUM_8197F) & BIT_MASK_ZLD_NUM_8197F)\n#define BIT_SET_ZLD_NUM_8197F(x, v)                                            \\\n\t(BIT_CLEAR_ZLD_NUM_8197F(x) | BIT_ZLD_NUM_8197F(v))\n\n/* 2 REG_UDF_THSD_8197F */\n\n#define BIT_SHIFT_UDF_THSD_8197F 0\n#define BIT_MASK_UDF_THSD_8197F 0xff\n#define BIT_UDF_THSD_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_UDF_THSD_8197F) << BIT_SHIFT_UDF_THSD_8197F)\n#define BITS_UDF_THSD_8197F                                                    \\\n\t(BIT_MASK_UDF_THSD_8197F << BIT_SHIFT_UDF_THSD_8197F)\n#define BIT_CLEAR_UDF_THSD_8197F(x) ((x) & (~BITS_UDF_THSD_8197F))\n#define BIT_GET_UDF_THSD_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_UDF_THSD_8197F) & BIT_MASK_UDF_THSD_8197F)\n#define BIT_SET_UDF_THSD_8197F(x, v)                                           \\\n\t(BIT_CLEAR_UDF_THSD_8197F(x) | BIT_UDF_THSD_8197F(v))\n\n/* 2 REG_WMAC_TCR_TSFT_OFS_8197F */\n\n#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F 0\n#define BIT_MASK_WMAC_TCR_TSFT_OFS_8197F 0xffff\n#define BIT_WMAC_TCR_TSFT_OFS_8197F(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8197F)                              \\\n\t << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F)\n#define BITS_WMAC_TCR_TSFT_OFS_8197F                                           \\\n\t(BIT_MASK_WMAC_TCR_TSFT_OFS_8197F << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F)\n#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8197F(x)                                   \\\n\t((x) & (~BITS_WMAC_TCR_TSFT_OFS_8197F))\n#define BIT_GET_WMAC_TCR_TSFT_OFS_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) &                          \\\n\t BIT_MASK_WMAC_TCR_TSFT_OFS_8197F)\n#define BIT_SET_WMAC_TCR_TSFT_OFS_8197F(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_TCR_TSFT_OFS_8197F(x) | BIT_WMAC_TCR_TSFT_OFS_8197F(v))\n\n/* 2 REG_MCU_TEST_2_V1_8197F */\n\n#define BIT_SHIFT_MCU_RSVD_2_V1_8197F 0\n#define BIT_MASK_MCU_RSVD_2_V1_8197F 0xffff\n#define BIT_MCU_RSVD_2_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_MCU_RSVD_2_V1_8197F) << BIT_SHIFT_MCU_RSVD_2_V1_8197F)\n#define BITS_MCU_RSVD_2_V1_8197F                                               \\\n\t(BIT_MASK_MCU_RSVD_2_V1_8197F << BIT_SHIFT_MCU_RSVD_2_V1_8197F)\n#define BIT_CLEAR_MCU_RSVD_2_V1_8197F(x) ((x) & (~BITS_MCU_RSVD_2_V1_8197F))\n#define BIT_GET_MCU_RSVD_2_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8197F) & BIT_MASK_MCU_RSVD_2_V1_8197F)\n#define BIT_SET_MCU_RSVD_2_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_MCU_RSVD_2_V1_8197F(x) | BIT_MCU_RSVD_2_V1_8197F(v))\n\n/* 2 REG_WMAC_TXTIMEOUT_8197F */\n\n#define BIT_SHIFT_WMAC_TXTIMEOUT_8197F 0\n#define BIT_MASK_WMAC_TXTIMEOUT_8197F 0xff\n#define BIT_WMAC_TXTIMEOUT_8197F(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_TXTIMEOUT_8197F)                                 \\\n\t << BIT_SHIFT_WMAC_TXTIMEOUT_8197F)\n#define BITS_WMAC_TXTIMEOUT_8197F                                              \\\n\t(BIT_MASK_WMAC_TXTIMEOUT_8197F << BIT_SHIFT_WMAC_TXTIMEOUT_8197F)\n#define BIT_CLEAR_WMAC_TXTIMEOUT_8197F(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8197F))\n#define BIT_GET_WMAC_TXTIMEOUT_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8197F) &                             \\\n\t BIT_MASK_WMAC_TXTIMEOUT_8197F)\n#define BIT_SET_WMAC_TXTIMEOUT_8197F(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_TXTIMEOUT_8197F(x) | BIT_WMAC_TXTIMEOUT_8197F(v))\n\n/* 2 REG_STMP_THSD_8197F */\n\n#define BIT_SHIFT_STMP_THSD_8197F 0\n#define BIT_MASK_STMP_THSD_8197F 0xff\n#define BIT_STMP_THSD_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_STMP_THSD_8197F) << BIT_SHIFT_STMP_THSD_8197F)\n#define BITS_STMP_THSD_8197F                                                   \\\n\t(BIT_MASK_STMP_THSD_8197F << BIT_SHIFT_STMP_THSD_8197F)\n#define BIT_CLEAR_STMP_THSD_8197F(x) ((x) & (~BITS_STMP_THSD_8197F))\n#define BIT_GET_STMP_THSD_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_STMP_THSD_8197F) & BIT_MASK_STMP_THSD_8197F)\n#define BIT_SET_STMP_THSD_8197F(x, v)                                          \\\n\t(BIT_CLEAR_STMP_THSD_8197F(x) | BIT_STMP_THSD_8197F(v))\n\n/* 2 REG_MAC_SPEC_SIFS_8197F (SPECIFICATION SIFS REGISTER) */\n\n#define BIT_SHIFT_SPEC_SIFS_OFDM_8197F 8\n#define BIT_MASK_SPEC_SIFS_OFDM_8197F 0xff\n#define BIT_SPEC_SIFS_OFDM_8197F(x)                                            \\\n\t(((x) & BIT_MASK_SPEC_SIFS_OFDM_8197F)                                 \\\n\t << BIT_SHIFT_SPEC_SIFS_OFDM_8197F)\n#define BITS_SPEC_SIFS_OFDM_8197F                                              \\\n\t(BIT_MASK_SPEC_SIFS_OFDM_8197F << BIT_SHIFT_SPEC_SIFS_OFDM_8197F)\n#define BIT_CLEAR_SPEC_SIFS_OFDM_8197F(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8197F))\n#define BIT_GET_SPEC_SIFS_OFDM_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8197F) &                             \\\n\t BIT_MASK_SPEC_SIFS_OFDM_8197F)\n#define BIT_SET_SPEC_SIFS_OFDM_8197F(x, v)                                     \\\n\t(BIT_CLEAR_SPEC_SIFS_OFDM_8197F(x) | BIT_SPEC_SIFS_OFDM_8197F(v))\n\n#define BIT_SHIFT_SPEC_SIFS_CCK_8197F 0\n#define BIT_MASK_SPEC_SIFS_CCK_8197F 0xff\n#define BIT_SPEC_SIFS_CCK_8197F(x)                                             \\\n\t(((x) & BIT_MASK_SPEC_SIFS_CCK_8197F) << BIT_SHIFT_SPEC_SIFS_CCK_8197F)\n#define BITS_SPEC_SIFS_CCK_8197F                                               \\\n\t(BIT_MASK_SPEC_SIFS_CCK_8197F << BIT_SHIFT_SPEC_SIFS_CCK_8197F)\n#define BIT_CLEAR_SPEC_SIFS_CCK_8197F(x) ((x) & (~BITS_SPEC_SIFS_CCK_8197F))\n#define BIT_GET_SPEC_SIFS_CCK_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8197F) & BIT_MASK_SPEC_SIFS_CCK_8197F)\n#define BIT_SET_SPEC_SIFS_CCK_8197F(x, v)                                      \\\n\t(BIT_CLEAR_SPEC_SIFS_CCK_8197F(x) | BIT_SPEC_SIFS_CCK_8197F(v))\n\n/* 2 REG_USTIME_EDCA_8197F (US TIME TUNING FOR EDCA REGISTER) */\n\n#define BIT_SHIFT_USTIME_EDCA_8197F 0\n#define BIT_MASK_USTIME_EDCA_8197F 0xff\n#define BIT_USTIME_EDCA_8197F(x)                                               \\\n\t(((x) & BIT_MASK_USTIME_EDCA_8197F) << BIT_SHIFT_USTIME_EDCA_8197F)\n#define BITS_USTIME_EDCA_8197F                                                 \\\n\t(BIT_MASK_USTIME_EDCA_8197F << BIT_SHIFT_USTIME_EDCA_8197F)\n#define BIT_CLEAR_USTIME_EDCA_8197F(x) ((x) & (~BITS_USTIME_EDCA_8197F))\n#define BIT_GET_USTIME_EDCA_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_USTIME_EDCA_8197F) & BIT_MASK_USTIME_EDCA_8197F)\n#define BIT_SET_USTIME_EDCA_8197F(x, v)                                        \\\n\t(BIT_CLEAR_USTIME_EDCA_8197F(x) | BIT_USTIME_EDCA_8197F(v))\n\n/* 2 REG_RESP_SIFS_OFDM_8197F (RESPONSE SIFS FOR OFDM REGISTER) */\n\n#define BIT_SHIFT_SIFS_R2T_OFDM_8197F 8\n#define BIT_MASK_SIFS_R2T_OFDM_8197F 0xff\n#define BIT_SIFS_R2T_OFDM_8197F(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_R2T_OFDM_8197F) << BIT_SHIFT_SIFS_R2T_OFDM_8197F)\n#define BITS_SIFS_R2T_OFDM_8197F                                               \\\n\t(BIT_MASK_SIFS_R2T_OFDM_8197F << BIT_SHIFT_SIFS_R2T_OFDM_8197F)\n#define BIT_CLEAR_SIFS_R2T_OFDM_8197F(x) ((x) & (~BITS_SIFS_R2T_OFDM_8197F))\n#define BIT_GET_SIFS_R2T_OFDM_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8197F) & BIT_MASK_SIFS_R2T_OFDM_8197F)\n#define BIT_SET_SIFS_R2T_OFDM_8197F(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_R2T_OFDM_8197F(x) | BIT_SIFS_R2T_OFDM_8197F(v))\n\n#define BIT_SHIFT_SIFS_T2T_OFDM_8197F 0\n#define BIT_MASK_SIFS_T2T_OFDM_8197F 0xff\n#define BIT_SIFS_T2T_OFDM_8197F(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_T2T_OFDM_8197F) << BIT_SHIFT_SIFS_T2T_OFDM_8197F)\n#define BITS_SIFS_T2T_OFDM_8197F                                               \\\n\t(BIT_MASK_SIFS_T2T_OFDM_8197F << BIT_SHIFT_SIFS_T2T_OFDM_8197F)\n#define BIT_CLEAR_SIFS_T2T_OFDM_8197F(x) ((x) & (~BITS_SIFS_T2T_OFDM_8197F))\n#define BIT_GET_SIFS_T2T_OFDM_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8197F) & BIT_MASK_SIFS_T2T_OFDM_8197F)\n#define BIT_SET_SIFS_T2T_OFDM_8197F(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_T2T_OFDM_8197F(x) | BIT_SIFS_T2T_OFDM_8197F(v))\n\n/* 2 REG_RESP_SIFS_CCK_8197F (RESPONSE SIFS FOR CCK REGISTER) */\n\n#define BIT_SHIFT_SIFS_R2T_CCK_8197F 8\n#define BIT_MASK_SIFS_R2T_CCK_8197F 0xff\n#define BIT_SIFS_R2T_CCK_8197F(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_R2T_CCK_8197F) << BIT_SHIFT_SIFS_R2T_CCK_8197F)\n#define BITS_SIFS_R2T_CCK_8197F                                                \\\n\t(BIT_MASK_SIFS_R2T_CCK_8197F << BIT_SHIFT_SIFS_R2T_CCK_8197F)\n#define BIT_CLEAR_SIFS_R2T_CCK_8197F(x) ((x) & (~BITS_SIFS_R2T_CCK_8197F))\n#define BIT_GET_SIFS_R2T_CCK_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_R2T_CCK_8197F) & BIT_MASK_SIFS_R2T_CCK_8197F)\n#define BIT_SET_SIFS_R2T_CCK_8197F(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_R2T_CCK_8197F(x) | BIT_SIFS_R2T_CCK_8197F(v))\n\n#define BIT_SHIFT_SIFS_T2T_CCK_8197F 0\n#define BIT_MASK_SIFS_T2T_CCK_8197F 0xff\n#define BIT_SIFS_T2T_CCK_8197F(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_T2T_CCK_8197F) << BIT_SHIFT_SIFS_T2T_CCK_8197F)\n#define BITS_SIFS_T2T_CCK_8197F                                                \\\n\t(BIT_MASK_SIFS_T2T_CCK_8197F << BIT_SHIFT_SIFS_T2T_CCK_8197F)\n#define BIT_CLEAR_SIFS_T2T_CCK_8197F(x) ((x) & (~BITS_SIFS_T2T_CCK_8197F))\n#define BIT_GET_SIFS_T2T_CCK_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_T2T_CCK_8197F) & BIT_MASK_SIFS_T2T_CCK_8197F)\n#define BIT_SET_SIFS_T2T_CCK_8197F(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_T2T_CCK_8197F(x) | BIT_SIFS_T2T_CCK_8197F(v))\n\n/* 2 REG_EIFS_8197F (EIFS REGISTER) */\n\n#define BIT_SHIFT_EIFS_8197F 0\n#define BIT_MASK_EIFS_8197F 0xffff\n#define BIT_EIFS_8197F(x) (((x) & BIT_MASK_EIFS_8197F) << BIT_SHIFT_EIFS_8197F)\n#define BITS_EIFS_8197F (BIT_MASK_EIFS_8197F << BIT_SHIFT_EIFS_8197F)\n#define BIT_CLEAR_EIFS_8197F(x) ((x) & (~BITS_EIFS_8197F))\n#define BIT_GET_EIFS_8197F(x)                                                  \\\n\t(((x) >> BIT_SHIFT_EIFS_8197F) & BIT_MASK_EIFS_8197F)\n#define BIT_SET_EIFS_8197F(x, v) (BIT_CLEAR_EIFS_8197F(x) | BIT_EIFS_8197F(v))\n\n/* 2 REG_CTS2TO_8197F (CTS2 TIMEOUT REGISTER) */\n\n#define BIT_SHIFT_CTS2TO_8197F 0\n#define BIT_MASK_CTS2TO_8197F 0xff\n#define BIT_CTS2TO_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_CTS2TO_8197F) << BIT_SHIFT_CTS2TO_8197F)\n#define BITS_CTS2TO_8197F (BIT_MASK_CTS2TO_8197F << BIT_SHIFT_CTS2TO_8197F)\n#define BIT_CLEAR_CTS2TO_8197F(x) ((x) & (~BITS_CTS2TO_8197F))\n#define BIT_GET_CTS2TO_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_CTS2TO_8197F) & BIT_MASK_CTS2TO_8197F)\n#define BIT_SET_CTS2TO_8197F(x, v)                                             \\\n\t(BIT_CLEAR_CTS2TO_8197F(x) | BIT_CTS2TO_8197F(v))\n\n/* 2 REG_ACKTO_8197F (ACK TIMEOUT REGISTER) */\n\n#define BIT_SHIFT_ACKTO_8197F 0\n#define BIT_MASK_ACKTO_8197F 0xff\n#define BIT_ACKTO_8197F(x)                                                     \\\n\t(((x) & BIT_MASK_ACKTO_8197F) << BIT_SHIFT_ACKTO_8197F)\n#define BITS_ACKTO_8197F (BIT_MASK_ACKTO_8197F << BIT_SHIFT_ACKTO_8197F)\n#define BIT_CLEAR_ACKTO_8197F(x) ((x) & (~BITS_ACKTO_8197F))\n#define BIT_GET_ACKTO_8197F(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ACKTO_8197F) & BIT_MASK_ACKTO_8197F)\n#define BIT_SET_ACKTO_8197F(x, v)                                              \\\n\t(BIT_CLEAR_ACKTO_8197F(x) | BIT_ACKTO_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NAV_CTRL_8197F (NAV CONTROL REGISTER) */\n\n#define BIT_SHIFT_NAV_UPPER_8197F 16\n#define BIT_MASK_NAV_UPPER_8197F 0xff\n#define BIT_NAV_UPPER_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_NAV_UPPER_8197F) << BIT_SHIFT_NAV_UPPER_8197F)\n#define BITS_NAV_UPPER_8197F                                                   \\\n\t(BIT_MASK_NAV_UPPER_8197F << BIT_SHIFT_NAV_UPPER_8197F)\n#define BIT_CLEAR_NAV_UPPER_8197F(x) ((x) & (~BITS_NAV_UPPER_8197F))\n#define BIT_GET_NAV_UPPER_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_NAV_UPPER_8197F) & BIT_MASK_NAV_UPPER_8197F)\n#define BIT_SET_NAV_UPPER_8197F(x, v)                                          \\\n\t(BIT_CLEAR_NAV_UPPER_8197F(x) | BIT_NAV_UPPER_8197F(v))\n\n#define BIT_SHIFT_RXMYRTS_NAV_8197F 8\n#define BIT_MASK_RXMYRTS_NAV_8197F 0xf\n#define BIT_RXMYRTS_NAV_8197F(x)                                               \\\n\t(((x) & BIT_MASK_RXMYRTS_NAV_8197F) << BIT_SHIFT_RXMYRTS_NAV_8197F)\n#define BITS_RXMYRTS_NAV_8197F                                                 \\\n\t(BIT_MASK_RXMYRTS_NAV_8197F << BIT_SHIFT_RXMYRTS_NAV_8197F)\n#define BIT_CLEAR_RXMYRTS_NAV_8197F(x) ((x) & (~BITS_RXMYRTS_NAV_8197F))\n#define BIT_GET_RXMYRTS_NAV_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_RXMYRTS_NAV_8197F) & BIT_MASK_RXMYRTS_NAV_8197F)\n#define BIT_SET_RXMYRTS_NAV_8197F(x, v)                                        \\\n\t(BIT_CLEAR_RXMYRTS_NAV_8197F(x) | BIT_RXMYRTS_NAV_8197F(v))\n\n#define BIT_SHIFT_RTSRST_8197F 0\n#define BIT_MASK_RTSRST_8197F 0xff\n#define BIT_RTSRST_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_RTSRST_8197F) << BIT_SHIFT_RTSRST_8197F)\n#define BITS_RTSRST_8197F (BIT_MASK_RTSRST_8197F << BIT_SHIFT_RTSRST_8197F)\n#define BIT_CLEAR_RTSRST_8197F(x) ((x) & (~BITS_RTSRST_8197F))\n#define BIT_GET_RTSRST_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_RTSRST_8197F) & BIT_MASK_RTSRST_8197F)\n#define BIT_SET_RTSRST_8197F(x, v)                                             \\\n\t(BIT_CLEAR_RTSRST_8197F(x) | BIT_RTSRST_8197F(v))\n\n/* 2 REG_BACAMCMD_8197F (BLOCK ACK CAM COMMAND REGISTER) */\n#define BIT_BACAM_POLL_8197F BIT(31)\n#define BIT_BACAM_RST_8197F BIT(17)\n#define BIT_BACAM_RW_8197F BIT(16)\n\n#define BIT_SHIFT_TXSBM_8197F 14\n#define BIT_MASK_TXSBM_8197F 0x3\n#define BIT_TXSBM_8197F(x)                                                     \\\n\t(((x) & BIT_MASK_TXSBM_8197F) << BIT_SHIFT_TXSBM_8197F)\n#define BITS_TXSBM_8197F (BIT_MASK_TXSBM_8197F << BIT_SHIFT_TXSBM_8197F)\n#define BIT_CLEAR_TXSBM_8197F(x) ((x) & (~BITS_TXSBM_8197F))\n#define BIT_GET_TXSBM_8197F(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TXSBM_8197F) & BIT_MASK_TXSBM_8197F)\n#define BIT_SET_TXSBM_8197F(x, v)                                              \\\n\t(BIT_CLEAR_TXSBM_8197F(x) | BIT_TXSBM_8197F(v))\n\n#define BIT_SHIFT_BACAM_ADDR_8197F 0\n#define BIT_MASK_BACAM_ADDR_8197F 0x3f\n#define BIT_BACAM_ADDR_8197F(x)                                                \\\n\t(((x) & BIT_MASK_BACAM_ADDR_8197F) << BIT_SHIFT_BACAM_ADDR_8197F)\n#define BITS_BACAM_ADDR_8197F                                                  \\\n\t(BIT_MASK_BACAM_ADDR_8197F << BIT_SHIFT_BACAM_ADDR_8197F)\n#define BIT_CLEAR_BACAM_ADDR_8197F(x) ((x) & (~BITS_BACAM_ADDR_8197F))\n#define BIT_GET_BACAM_ADDR_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_BACAM_ADDR_8197F) & BIT_MASK_BACAM_ADDR_8197F)\n#define BIT_SET_BACAM_ADDR_8197F(x, v)                                         \\\n\t(BIT_CLEAR_BACAM_ADDR_8197F(x) | BIT_BACAM_ADDR_8197F(v))\n\n/* 2 REG_BACAMCONTENT_8197F (BLOCK ACK CAM CONTENT REGISTER) */\n\n#define BIT_SHIFT_BA_CONTENT_H_8197F (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_BA_CONTENT_H_8197F 0xffffffffL\n#define BIT_BA_CONTENT_H_8197F(x)                                              \\\n\t(((x) & BIT_MASK_BA_CONTENT_H_8197F) << BIT_SHIFT_BA_CONTENT_H_8197F)\n#define BITS_BA_CONTENT_H_8197F                                                \\\n\t(BIT_MASK_BA_CONTENT_H_8197F << BIT_SHIFT_BA_CONTENT_H_8197F)\n#define BIT_CLEAR_BA_CONTENT_H_8197F(x) ((x) & (~BITS_BA_CONTENT_H_8197F))\n#define BIT_GET_BA_CONTENT_H_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_BA_CONTENT_H_8197F) & BIT_MASK_BA_CONTENT_H_8197F)\n#define BIT_SET_BA_CONTENT_H_8197F(x, v)                                       \\\n\t(BIT_CLEAR_BA_CONTENT_H_8197F(x) | BIT_BA_CONTENT_H_8197F(v))\n\n#define BIT_SHIFT_BA_CONTENT_L_8197F 0\n#define BIT_MASK_BA_CONTENT_L_8197F 0xffffffffL\n#define BIT_BA_CONTENT_L_8197F(x)                                              \\\n\t(((x) & BIT_MASK_BA_CONTENT_L_8197F) << BIT_SHIFT_BA_CONTENT_L_8197F)\n#define BITS_BA_CONTENT_L_8197F                                                \\\n\t(BIT_MASK_BA_CONTENT_L_8197F << BIT_SHIFT_BA_CONTENT_L_8197F)\n#define BIT_CLEAR_BA_CONTENT_L_8197F(x) ((x) & (~BITS_BA_CONTENT_L_8197F))\n#define BIT_GET_BA_CONTENT_L_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_BA_CONTENT_L_8197F) & BIT_MASK_BA_CONTENT_L_8197F)\n#define BIT_SET_BA_CONTENT_L_8197F(x, v)                                       \\\n\t(BIT_CLEAR_BA_CONTENT_L_8197F(x) | BIT_BA_CONTENT_L_8197F(v))\n\n/* 2 REG_WMAC_BITMAP_CTL_8197F */\n#define BIT_BITMAP_VO_8197F BIT(7)\n#define BIT_BITMAP_VI_8197F BIT(6)\n#define BIT_BITMAP_BE_8197F BIT(5)\n#define BIT_BITMAP_BK_8197F BIT(4)\n\n#define BIT_SHIFT_BITMAP_CONDITION_8197F 2\n#define BIT_MASK_BITMAP_CONDITION_8197F 0x3\n#define BIT_BITMAP_CONDITION_8197F(x)                                          \\\n\t(((x) & BIT_MASK_BITMAP_CONDITION_8197F)                               \\\n\t << BIT_SHIFT_BITMAP_CONDITION_8197F)\n#define BITS_BITMAP_CONDITION_8197F                                            \\\n\t(BIT_MASK_BITMAP_CONDITION_8197F << BIT_SHIFT_BITMAP_CONDITION_8197F)\n#define BIT_CLEAR_BITMAP_CONDITION_8197F(x)                                    \\\n\t((x) & (~BITS_BITMAP_CONDITION_8197F))\n#define BIT_GET_BITMAP_CONDITION_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_BITMAP_CONDITION_8197F) &                           \\\n\t BIT_MASK_BITMAP_CONDITION_8197F)\n#define BIT_SET_BITMAP_CONDITION_8197F(x, v)                                   \\\n\t(BIT_CLEAR_BITMAP_CONDITION_8197F(x) | BIT_BITMAP_CONDITION_8197F(v))\n\n#define BIT_BITMAP_SSNBK_COUNTER_CLR_8197F BIT(1)\n#define BIT_BITMAP_FORCE_8197F BIT(0)\n\n/* 2 REG_NOT_VALID_8197F */\n\n#define BIT_SHIFT_RXPKT_TYPE_8197F 2\n#define BIT_MASK_RXPKT_TYPE_8197F 0x3f\n#define BIT_RXPKT_TYPE_8197F(x)                                                \\\n\t(((x) & BIT_MASK_RXPKT_TYPE_8197F) << BIT_SHIFT_RXPKT_TYPE_8197F)\n#define BITS_RXPKT_TYPE_8197F                                                  \\\n\t(BIT_MASK_RXPKT_TYPE_8197F << BIT_SHIFT_RXPKT_TYPE_8197F)\n#define BIT_CLEAR_RXPKT_TYPE_8197F(x) ((x) & (~BITS_RXPKT_TYPE_8197F))\n#define BIT_GET_RXPKT_TYPE_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXPKT_TYPE_8197F) & BIT_MASK_RXPKT_TYPE_8197F)\n#define BIT_SET_RXPKT_TYPE_8197F(x, v)                                         \\\n\t(BIT_CLEAR_RXPKT_TYPE_8197F(x) | BIT_RXPKT_TYPE_8197F(v))\n\n#define BIT_TXACT_IND_8197F BIT(1)\n#define BIT_RXACT_IND_8197F BIT(0)\n\n/* 2 REG_WMAC_BACAM_RPMEN_8197F */\n\n#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F 2\n#define BIT_MASK_BITMAP_SSNBK_COUNTER_8197F 0x3f\n#define BIT_BITMAP_SSNBK_COUNTER_8197F(x)                                      \\\n\t(((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8197F)                           \\\n\t << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F)\n#define BITS_BITMAP_SSNBK_COUNTER_8197F                                        \\\n\t(BIT_MASK_BITMAP_SSNBK_COUNTER_8197F                                   \\\n\t << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F)\n#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8197F(x)                                \\\n\t((x) & (~BITS_BITMAP_SSNBK_COUNTER_8197F))\n#define BIT_GET_BITMAP_SSNBK_COUNTER_8197F(x)                                  \\\n\t(((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) &                       \\\n\t BIT_MASK_BITMAP_SSNBK_COUNTER_8197F)\n#define BIT_SET_BITMAP_SSNBK_COUNTER_8197F(x, v)                               \\\n\t(BIT_CLEAR_BITMAP_SSNBK_COUNTER_8197F(x) |                             \\\n\t BIT_BITMAP_SSNBK_COUNTER_8197F(v))\n\n#define BIT_BITMAP_EN_8197F BIT(1)\n#define BIT_WMAC_BACAM_RPMEN_8197F BIT(0)\n\n/* 2 REG_LBDLY_8197F (LOOPBACK DELAY REGISTER) */\n\n#define BIT_SHIFT_LBDLY_8197F 0\n#define BIT_MASK_LBDLY_8197F 0x1f\n#define BIT_LBDLY_8197F(x)                                                     \\\n\t(((x) & BIT_MASK_LBDLY_8197F) << BIT_SHIFT_LBDLY_8197F)\n#define BITS_LBDLY_8197F (BIT_MASK_LBDLY_8197F << BIT_SHIFT_LBDLY_8197F)\n#define BIT_CLEAR_LBDLY_8197F(x) ((x) & (~BITS_LBDLY_8197F))\n#define BIT_GET_LBDLY_8197F(x)                                                 \\\n\t(((x) >> BIT_SHIFT_LBDLY_8197F) & BIT_MASK_LBDLY_8197F)\n#define BIT_SET_LBDLY_8197F(x, v)                                              \\\n\t(BIT_CLEAR_LBDLY_8197F(x) | BIT_LBDLY_8197F(v))\n\n/* 2 REG_RXERR_RPT_8197F (RX ERROR REPORT REGISTER) */\n\n#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F 28\n#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F 0xf\n#define BIT_RXERR_RPT_SEL_V1_3_0_8197F(x)                                      \\\n\t(((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F)                           \\\n\t << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F)\n#define BITS_RXERR_RPT_SEL_V1_3_0_8197F                                        \\\n\t(BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F                                   \\\n\t << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F)\n#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8197F(x)                                \\\n\t((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8197F))\n#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8197F(x)                                  \\\n\t(((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) &                       \\\n\t BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F)\n#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8197F(x, v)                               \\\n\t(BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8197F(x) |                             \\\n\t BIT_RXERR_RPT_SEL_V1_3_0_8197F(v))\n\n#define BIT_RXERR_RPT_RST_8197F BIT(27)\n#define BIT_RXERR_RPT_SEL_V1_4_8197F BIT(26)\n\n#define BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F 24\n#define BIT_MASK_UD_SELECT_BSSID_2_1_8197F 0x3\n#define BIT_UD_SELECT_BSSID_2_1_8197F(x)                                       \\\n\t(((x) & BIT_MASK_UD_SELECT_BSSID_2_1_8197F)                            \\\n\t << BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F)\n#define BITS_UD_SELECT_BSSID_2_1_8197F                                         \\\n\t(BIT_MASK_UD_SELECT_BSSID_2_1_8197F                                    \\\n\t << BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F)\n#define BIT_CLEAR_UD_SELECT_BSSID_2_1_8197F(x)                                 \\\n\t((x) & (~BITS_UD_SELECT_BSSID_2_1_8197F))\n#define BIT_GET_UD_SELECT_BSSID_2_1_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) &                        \\\n\t BIT_MASK_UD_SELECT_BSSID_2_1_8197F)\n#define BIT_SET_UD_SELECT_BSSID_2_1_8197F(x, v)                                \\\n\t(BIT_CLEAR_UD_SELECT_BSSID_2_1_8197F(x) |                              \\\n\t BIT_UD_SELECT_BSSID_2_1_8197F(v))\n\n#define BIT_W1S_8197F BIT(23)\n#define BIT_UD_SELECT_BSSID_0_8197F BIT(22)\n\n#define BIT_SHIFT_UD_SUB_TYPE_8197F 18\n#define BIT_MASK_UD_SUB_TYPE_8197F 0xf\n#define BIT_UD_SUB_TYPE_8197F(x)                                               \\\n\t(((x) & BIT_MASK_UD_SUB_TYPE_8197F) << BIT_SHIFT_UD_SUB_TYPE_8197F)\n#define BITS_UD_SUB_TYPE_8197F                                                 \\\n\t(BIT_MASK_UD_SUB_TYPE_8197F << BIT_SHIFT_UD_SUB_TYPE_8197F)\n#define BIT_CLEAR_UD_SUB_TYPE_8197F(x) ((x) & (~BITS_UD_SUB_TYPE_8197F))\n#define BIT_GET_UD_SUB_TYPE_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_UD_SUB_TYPE_8197F) & BIT_MASK_UD_SUB_TYPE_8197F)\n#define BIT_SET_UD_SUB_TYPE_8197F(x, v)                                        \\\n\t(BIT_CLEAR_UD_SUB_TYPE_8197F(x) | BIT_UD_SUB_TYPE_8197F(v))\n\n#define BIT_SHIFT_UD_TYPE_8197F 16\n#define BIT_MASK_UD_TYPE_8197F 0x3\n#define BIT_UD_TYPE_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_UD_TYPE_8197F) << BIT_SHIFT_UD_TYPE_8197F)\n#define BITS_UD_TYPE_8197F (BIT_MASK_UD_TYPE_8197F << BIT_SHIFT_UD_TYPE_8197F)\n#define BIT_CLEAR_UD_TYPE_8197F(x) ((x) & (~BITS_UD_TYPE_8197F))\n#define BIT_GET_UD_TYPE_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_UD_TYPE_8197F) & BIT_MASK_UD_TYPE_8197F)\n#define BIT_SET_UD_TYPE_8197F(x, v)                                            \\\n\t(BIT_CLEAR_UD_TYPE_8197F(x) | BIT_UD_TYPE_8197F(v))\n\n#define BIT_SHIFT_RPT_COUNTER_8197F 0\n#define BIT_MASK_RPT_COUNTER_8197F 0xffff\n#define BIT_RPT_COUNTER_8197F(x)                                               \\\n\t(((x) & BIT_MASK_RPT_COUNTER_8197F) << BIT_SHIFT_RPT_COUNTER_8197F)\n#define BITS_RPT_COUNTER_8197F                                                 \\\n\t(BIT_MASK_RPT_COUNTER_8197F << BIT_SHIFT_RPT_COUNTER_8197F)\n#define BIT_CLEAR_RPT_COUNTER_8197F(x) ((x) & (~BITS_RPT_COUNTER_8197F))\n#define BIT_GET_RPT_COUNTER_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_RPT_COUNTER_8197F) & BIT_MASK_RPT_COUNTER_8197F)\n#define BIT_SET_RPT_COUNTER_8197F(x, v)                                        \\\n\t(BIT_CLEAR_RPT_COUNTER_8197F(x) | BIT_RPT_COUNTER_8197F(v))\n\n/* 2 REG_WMAC_TRXPTCL_CTL_8197F (WMAC TX/RX PROTOCOL CONTROL REGISTER) */\n\n#define BIT_SHIFT_ACKBA_TYPSEL_8197F (60 & CPU_OPT_WIDTH)\n#define BIT_MASK_ACKBA_TYPSEL_8197F 0xf\n#define BIT_ACKBA_TYPSEL_8197F(x)                                              \\\n\t(((x) & BIT_MASK_ACKBA_TYPSEL_8197F) << BIT_SHIFT_ACKBA_TYPSEL_8197F)\n#define BITS_ACKBA_TYPSEL_8197F                                                \\\n\t(BIT_MASK_ACKBA_TYPSEL_8197F << BIT_SHIFT_ACKBA_TYPSEL_8197F)\n#define BIT_CLEAR_ACKBA_TYPSEL_8197F(x) ((x) & (~BITS_ACKBA_TYPSEL_8197F))\n#define BIT_GET_ACKBA_TYPSEL_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_ACKBA_TYPSEL_8197F) & BIT_MASK_ACKBA_TYPSEL_8197F)\n#define BIT_SET_ACKBA_TYPSEL_8197F(x, v)                                       \\\n\t(BIT_CLEAR_ACKBA_TYPSEL_8197F(x) | BIT_ACKBA_TYPSEL_8197F(v))\n\n#define BIT_SHIFT_ACKBA_ACKPCHK_8197F (56 & CPU_OPT_WIDTH)\n#define BIT_MASK_ACKBA_ACKPCHK_8197F 0xf\n#define BIT_ACKBA_ACKPCHK_8197F(x)                                             \\\n\t(((x) & BIT_MASK_ACKBA_ACKPCHK_8197F) << BIT_SHIFT_ACKBA_ACKPCHK_8197F)\n#define BITS_ACKBA_ACKPCHK_8197F                                               \\\n\t(BIT_MASK_ACKBA_ACKPCHK_8197F << BIT_SHIFT_ACKBA_ACKPCHK_8197F)\n#define BIT_CLEAR_ACKBA_ACKPCHK_8197F(x) ((x) & (~BITS_ACKBA_ACKPCHK_8197F))\n#define BIT_GET_ACKBA_ACKPCHK_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8197F) & BIT_MASK_ACKBA_ACKPCHK_8197F)\n#define BIT_SET_ACKBA_ACKPCHK_8197F(x, v)                                      \\\n\t(BIT_CLEAR_ACKBA_ACKPCHK_8197F(x) | BIT_ACKBA_ACKPCHK_8197F(v))\n\n#define BIT_SHIFT_ACKBAR_TYPESEL_8197F (48 & CPU_OPT_WIDTH)\n#define BIT_MASK_ACKBAR_TYPESEL_8197F 0xff\n#define BIT_ACKBAR_TYPESEL_8197F(x)                                            \\\n\t(((x) & BIT_MASK_ACKBAR_TYPESEL_8197F)                                 \\\n\t << BIT_SHIFT_ACKBAR_TYPESEL_8197F)\n#define BITS_ACKBAR_TYPESEL_8197F                                              \\\n\t(BIT_MASK_ACKBAR_TYPESEL_8197F << BIT_SHIFT_ACKBAR_TYPESEL_8197F)\n#define BIT_CLEAR_ACKBAR_TYPESEL_8197F(x) ((x) & (~BITS_ACKBAR_TYPESEL_8197F))\n#define BIT_GET_ACKBAR_TYPESEL_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8197F) &                             \\\n\t BIT_MASK_ACKBAR_TYPESEL_8197F)\n#define BIT_SET_ACKBAR_TYPESEL_8197F(x, v)                                     \\\n\t(BIT_CLEAR_ACKBAR_TYPESEL_8197F(x) | BIT_ACKBAR_TYPESEL_8197F(v))\n\n#define BIT_SHIFT_ACKBAR_ACKPCHK_8197F (44 & CPU_OPT_WIDTH)\n#define BIT_MASK_ACKBAR_ACKPCHK_8197F 0xf\n#define BIT_ACKBAR_ACKPCHK_8197F(x)                                            \\\n\t(((x) & BIT_MASK_ACKBAR_ACKPCHK_8197F)                                 \\\n\t << BIT_SHIFT_ACKBAR_ACKPCHK_8197F)\n#define BITS_ACKBAR_ACKPCHK_8197F                                              \\\n\t(BIT_MASK_ACKBAR_ACKPCHK_8197F << BIT_SHIFT_ACKBAR_ACKPCHK_8197F)\n#define BIT_CLEAR_ACKBAR_ACKPCHK_8197F(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8197F))\n#define BIT_GET_ACKBAR_ACKPCHK_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8197F) &                             \\\n\t BIT_MASK_ACKBAR_ACKPCHK_8197F)\n#define BIT_SET_ACKBAR_ACKPCHK_8197F(x, v)                                     \\\n\t(BIT_CLEAR_ACKBAR_ACKPCHK_8197F(x) | BIT_ACKBAR_ACKPCHK_8197F(v))\n\n#define BIT_RXBA_IGNOREA2_8197F BIT(42)\n#define BIT_EN_SAVE_ALL_TXOPADDR_8197F BIT(41)\n#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_8197F BIT(40)\n#define BIT_DIS_TXBA_AMPDUFCSERR_8197F BIT(39)\n#define BIT_DIS_TXBA_RXBARINFULL_8197F BIT(38)\n#define BIT_DIS_TXCFE_INFULL_8197F BIT(37)\n#define BIT_DIS_TXCTS_INFULL_8197F BIT(36)\n#define BIT_EN_TXACKBA_IN_TX_RDG_8197F BIT(35)\n#define BIT_EN_TXACKBA_IN_TXOP_8197F BIT(34)\n#define BIT_EN_TXCTS_IN_RXNAV_8197F BIT(33)\n#define BIT_EN_TXCTS_INTXOP_8197F BIT(32)\n#define BIT_BLK_EDCA_BBSLP_8197F BIT(31)\n#define BIT_BLK_EDCA_BBSBY_8197F BIT(30)\n#define BIT_ACKTO_BLOCK_SCH_EN_8197F BIT(27)\n#define BIT_EIFS_BLOCK_SCH_EN_8197F BIT(26)\n#define BIT_PLCPCHK_RST_EIFS_8197F BIT(25)\n#define BIT_CCA_RST_EIFS_8197F BIT(24)\n#define BIT_DIS_UPD_MYRXPKTNAV_8197F BIT(23)\n#define BIT_EARLY_TXBA_8197F BIT(22)\n\n#define BIT_SHIFT_RESP_CHNBUSY_8197F 20\n#define BIT_MASK_RESP_CHNBUSY_8197F 0x3\n#define BIT_RESP_CHNBUSY_8197F(x)                                              \\\n\t(((x) & BIT_MASK_RESP_CHNBUSY_8197F) << BIT_SHIFT_RESP_CHNBUSY_8197F)\n#define BITS_RESP_CHNBUSY_8197F                                                \\\n\t(BIT_MASK_RESP_CHNBUSY_8197F << BIT_SHIFT_RESP_CHNBUSY_8197F)\n#define BIT_CLEAR_RESP_CHNBUSY_8197F(x) ((x) & (~BITS_RESP_CHNBUSY_8197F))\n#define BIT_GET_RESP_CHNBUSY_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_RESP_CHNBUSY_8197F) & BIT_MASK_RESP_CHNBUSY_8197F)\n#define BIT_SET_RESP_CHNBUSY_8197F(x, v)                                       \\\n\t(BIT_CLEAR_RESP_CHNBUSY_8197F(x) | BIT_RESP_CHNBUSY_8197F(v))\n\n#define BIT_RESP_DCTS_EN_8197F BIT(19)\n#define BIT_RESP_DCFE_EN_8197F BIT(18)\n#define BIT_RESP_SPLCPEN_8197F BIT(17)\n#define BIT_RESP_SGIEN_8197F BIT(16)\n#define BIT_RESP_LDPC_EN_8197F BIT(15)\n#define BIT_DIS_RESP_ACKINCCA_8197F BIT(14)\n#define BIT_DIS_RESP_CTSINCCA_8197F BIT(13)\n\n#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F 10\n#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F 0x7\n#define BIT_R_WMAC_SECOND_CCA_TIMER_8197F(x)                                   \\\n\t(((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F)                        \\\n\t << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F)\n#define BITS_R_WMAC_SECOND_CCA_TIMER_8197F                                     \\\n\t(BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F                                \\\n\t << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F)\n#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8197F(x)                             \\\n\t((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8197F))\n#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8197F(x)                               \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) &                    \\\n\t BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F)\n#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8197F(x, v)                            \\\n\t(BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8197F(x) |                          \\\n\t BIT_R_WMAC_SECOND_CCA_TIMER_8197F(v))\n\n#define BIT_SHIFT_RFMOD_8197F 7\n#define BIT_MASK_RFMOD_8197F 0x3\n#define BIT_RFMOD_8197F(x)                                                     \\\n\t(((x) & BIT_MASK_RFMOD_8197F) << BIT_SHIFT_RFMOD_8197F)\n#define BITS_RFMOD_8197F (BIT_MASK_RFMOD_8197F << BIT_SHIFT_RFMOD_8197F)\n#define BIT_CLEAR_RFMOD_8197F(x) ((x) & (~BITS_RFMOD_8197F))\n#define BIT_GET_RFMOD_8197F(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RFMOD_8197F) & BIT_MASK_RFMOD_8197F)\n#define BIT_SET_RFMOD_8197F(x, v)                                              \\\n\t(BIT_CLEAR_RFMOD_8197F(x) | BIT_RFMOD_8197F(v))\n\n#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F 5\n#define BIT_MASK_RESP_CTS_DYNBW_SEL_8197F 0x3\n#define BIT_RESP_CTS_DYNBW_SEL_8197F(x)                                        \\\n\t(((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8197F)                             \\\n\t << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F)\n#define BITS_RESP_CTS_DYNBW_SEL_8197F                                          \\\n\t(BIT_MASK_RESP_CTS_DYNBW_SEL_8197F                                     \\\n\t << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F)\n#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8197F(x)                                  \\\n\t((x) & (~BITS_RESP_CTS_DYNBW_SEL_8197F))\n#define BIT_GET_RESP_CTS_DYNBW_SEL_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) &                         \\\n\t BIT_MASK_RESP_CTS_DYNBW_SEL_8197F)\n#define BIT_SET_RESP_CTS_DYNBW_SEL_8197F(x, v)                                 \\\n\t(BIT_CLEAR_RESP_CTS_DYNBW_SEL_8197F(x) |                               \\\n\t BIT_RESP_CTS_DYNBW_SEL_8197F(v))\n\n#define BIT_DLY_TX_WAIT_RXANTSEL_8197F BIT(4)\n#define BIT_TXRESP_BY_RXANTSEL_8197F BIT(3)\n\n#define BIT_SHIFT_ORIG_DCTS_CHK_8197F 0\n#define BIT_MASK_ORIG_DCTS_CHK_8197F 0x3\n#define BIT_ORIG_DCTS_CHK_8197F(x)                                             \\\n\t(((x) & BIT_MASK_ORIG_DCTS_CHK_8197F) << BIT_SHIFT_ORIG_DCTS_CHK_8197F)\n#define BITS_ORIG_DCTS_CHK_8197F                                               \\\n\t(BIT_MASK_ORIG_DCTS_CHK_8197F << BIT_SHIFT_ORIG_DCTS_CHK_8197F)\n#define BIT_CLEAR_ORIG_DCTS_CHK_8197F(x) ((x) & (~BITS_ORIG_DCTS_CHK_8197F))\n#define BIT_GET_ORIG_DCTS_CHK_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8197F) & BIT_MASK_ORIG_DCTS_CHK_8197F)\n#define BIT_SET_ORIG_DCTS_CHK_8197F(x, v)                                      \\\n\t(BIT_CLEAR_ORIG_DCTS_CHK_8197F(x) | BIT_ORIG_DCTS_CHK_8197F(v))\n\n/* 2 REG_CAMCMD_8197F (CAM COMMAND REGISTER) */\n#define BIT_SECCAM_POLLING_8197F BIT(31)\n#define BIT_SECCAM_CLR_8197F BIT(30)\n#define BIT_MFBCAM_CLR_8197F BIT(29)\n#define BIT_SECCAM_WE_8197F BIT(16)\n\n#define BIT_SHIFT_SECCAM_ADDR_V2_8197F 0\n#define BIT_MASK_SECCAM_ADDR_V2_8197F 0x3ff\n#define BIT_SECCAM_ADDR_V2_8197F(x)                                            \\\n\t(((x) & BIT_MASK_SECCAM_ADDR_V2_8197F)                                 \\\n\t << BIT_SHIFT_SECCAM_ADDR_V2_8197F)\n#define BITS_SECCAM_ADDR_V2_8197F                                              \\\n\t(BIT_MASK_SECCAM_ADDR_V2_8197F << BIT_SHIFT_SECCAM_ADDR_V2_8197F)\n#define BIT_CLEAR_SECCAM_ADDR_V2_8197F(x) ((x) & (~BITS_SECCAM_ADDR_V2_8197F))\n#define BIT_GET_SECCAM_ADDR_V2_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8197F) &                             \\\n\t BIT_MASK_SECCAM_ADDR_V2_8197F)\n#define BIT_SET_SECCAM_ADDR_V2_8197F(x, v)                                     \\\n\t(BIT_CLEAR_SECCAM_ADDR_V2_8197F(x) | BIT_SECCAM_ADDR_V2_8197F(v))\n\n/* 2 REG_CAMWRITE_8197F (CAM WRITE REGISTER) */\n\n#define BIT_SHIFT_CAMW_DATA_8197F 0\n#define BIT_MASK_CAMW_DATA_8197F 0xffffffffL\n#define BIT_CAMW_DATA_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_CAMW_DATA_8197F) << BIT_SHIFT_CAMW_DATA_8197F)\n#define BITS_CAMW_DATA_8197F                                                   \\\n\t(BIT_MASK_CAMW_DATA_8197F << BIT_SHIFT_CAMW_DATA_8197F)\n#define BIT_CLEAR_CAMW_DATA_8197F(x) ((x) & (~BITS_CAMW_DATA_8197F))\n#define BIT_GET_CAMW_DATA_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_CAMW_DATA_8197F) & BIT_MASK_CAMW_DATA_8197F)\n#define BIT_SET_CAMW_DATA_8197F(x, v)                                          \\\n\t(BIT_CLEAR_CAMW_DATA_8197F(x) | BIT_CAMW_DATA_8197F(v))\n\n/* 2 REG_CAMREAD_8197F (CAM READ REGISTER) */\n\n#define BIT_SHIFT_CAMR_DATA_8197F 0\n#define BIT_MASK_CAMR_DATA_8197F 0xffffffffL\n#define BIT_CAMR_DATA_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_CAMR_DATA_8197F) << BIT_SHIFT_CAMR_DATA_8197F)\n#define BITS_CAMR_DATA_8197F                                                   \\\n\t(BIT_MASK_CAMR_DATA_8197F << BIT_SHIFT_CAMR_DATA_8197F)\n#define BIT_CLEAR_CAMR_DATA_8197F(x) ((x) & (~BITS_CAMR_DATA_8197F))\n#define BIT_GET_CAMR_DATA_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_CAMR_DATA_8197F) & BIT_MASK_CAMR_DATA_8197F)\n#define BIT_SET_CAMR_DATA_8197F(x, v)                                          \\\n\t(BIT_CLEAR_CAMR_DATA_8197F(x) | BIT_CAMR_DATA_8197F(v))\n\n/* 2 REG_CAMDBG_8197F (CAM DEBUG REGISTER) */\n#define BIT_SECCAM_INFO_8197F BIT(31)\n#define BIT_SEC_KEYFOUND_8197F BIT(15)\n\n#define BIT_SHIFT_CAMDBG_SEC_TYPE_8197F 12\n#define BIT_MASK_CAMDBG_SEC_TYPE_8197F 0x7\n#define BIT_CAMDBG_SEC_TYPE_8197F(x)                                           \\\n\t(((x) & BIT_MASK_CAMDBG_SEC_TYPE_8197F)                                \\\n\t << BIT_SHIFT_CAMDBG_SEC_TYPE_8197F)\n#define BITS_CAMDBG_SEC_TYPE_8197F                                             \\\n\t(BIT_MASK_CAMDBG_SEC_TYPE_8197F << BIT_SHIFT_CAMDBG_SEC_TYPE_8197F)\n#define BIT_CLEAR_CAMDBG_SEC_TYPE_8197F(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8197F))\n#define BIT_GET_CAMDBG_SEC_TYPE_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) &                            \\\n\t BIT_MASK_CAMDBG_SEC_TYPE_8197F)\n#define BIT_SET_CAMDBG_SEC_TYPE_8197F(x, v)                                    \\\n\t(BIT_CLEAR_CAMDBG_SEC_TYPE_8197F(x) | BIT_CAMDBG_SEC_TYPE_8197F(v))\n\n#define BIT_CAMDBG_EXT_SEC_TYPE_8197F BIT(11)\n\n#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F 5\n#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F 0x1f\n#define BIT_CAMDBG_MIC_KEY_IDX_8197F(x)                                        \\\n\t(((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F)                             \\\n\t << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F)\n#define BITS_CAMDBG_MIC_KEY_IDX_8197F                                          \\\n\t(BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F                                     \\\n\t << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F)\n#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8197F(x)                                  \\\n\t((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8197F))\n#define BIT_GET_CAMDBG_MIC_KEY_IDX_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) &                         \\\n\t BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F)\n#define BIT_SET_CAMDBG_MIC_KEY_IDX_8197F(x, v)                                 \\\n\t(BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8197F(x) |                               \\\n\t BIT_CAMDBG_MIC_KEY_IDX_8197F(v))\n\n#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F 0\n#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F 0x1f\n#define BIT_CAMDBG_SEC_KEY_IDX_8197F(x)                                        \\\n\t(((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F)                             \\\n\t << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F)\n#define BITS_CAMDBG_SEC_KEY_IDX_8197F                                          \\\n\t(BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F                                     \\\n\t << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F)\n#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8197F(x)                                  \\\n\t((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8197F))\n#define BIT_GET_CAMDBG_SEC_KEY_IDX_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) &                         \\\n\t BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F)\n#define BIT_SET_CAMDBG_SEC_KEY_IDX_8197F(x, v)                                 \\\n\t(BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8197F(x) |                               \\\n\t BIT_CAMDBG_SEC_KEY_IDX_8197F(v))\n\n/* 2 REG_RXFILTER_ACTION_1_8197F */\n\n#define BIT_SHIFT_RXFILTER_ACTION_1_8197F 0\n#define BIT_MASK_RXFILTER_ACTION_1_8197F 0xff\n#define BIT_RXFILTER_ACTION_1_8197F(x)                                         \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_1_8197F)                              \\\n\t << BIT_SHIFT_RXFILTER_ACTION_1_8197F)\n#define BITS_RXFILTER_ACTION_1_8197F                                           \\\n\t(BIT_MASK_RXFILTER_ACTION_1_8197F << BIT_SHIFT_RXFILTER_ACTION_1_8197F)\n#define BIT_CLEAR_RXFILTER_ACTION_1_8197F(x)                                   \\\n\t((x) & (~BITS_RXFILTER_ACTION_1_8197F))\n#define BIT_GET_RXFILTER_ACTION_1_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8197F) &                          \\\n\t BIT_MASK_RXFILTER_ACTION_1_8197F)\n#define BIT_SET_RXFILTER_ACTION_1_8197F(x, v)                                  \\\n\t(BIT_CLEAR_RXFILTER_ACTION_1_8197F(x) | BIT_RXFILTER_ACTION_1_8197F(v))\n\n/* 2 REG_RXFILTER_CATEGORY_1_8197F */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_1_8197F 0\n#define BIT_MASK_RXFILTER_CATEGORY_1_8197F 0xff\n#define BIT_RXFILTER_CATEGORY_1_8197F(x)                                       \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_1_8197F)                            \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_1_8197F)\n#define BITS_RXFILTER_CATEGORY_1_8197F                                         \\\n\t(BIT_MASK_RXFILTER_CATEGORY_1_8197F                                    \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_1_8197F)\n#define BIT_CLEAR_RXFILTER_CATEGORY_1_8197F(x)                                 \\\n\t((x) & (~BITS_RXFILTER_CATEGORY_1_8197F))\n#define BIT_GET_RXFILTER_CATEGORY_1_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) &                        \\\n\t BIT_MASK_RXFILTER_CATEGORY_1_8197F)\n#define BIT_SET_RXFILTER_CATEGORY_1_8197F(x, v)                                \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_1_8197F(x) |                              \\\n\t BIT_RXFILTER_CATEGORY_1_8197F(v))\n\n/* 2 REG_SECCFG_8197F (SECURITY CONFIGURATION REGISTER) */\n#define BIT_DIS_GCLK_WAPI_8197F BIT(15)\n#define BIT_DIS_GCLK_AES_8197F BIT(14)\n#define BIT_DIS_GCLK_TKIP_8197F BIT(13)\n#define BIT_AES_SEL_QC_1_8197F BIT(12)\n#define BIT_AES_SEL_QC_0_8197F BIT(11)\n#define BIT_WMAC_CKECK_BMC_8197F BIT(9)\n#define BIT_CHK_KEYID_8197F BIT(8)\n#define BIT_RXBCUSEDK_8197F BIT(7)\n#define BIT_TXBCUSEDK_8197F BIT(6)\n#define BIT_NOSKMC_8197F BIT(5)\n#define BIT_SKBYA2_8197F BIT(4)\n#define BIT_RXDEC_8197F BIT(3)\n#define BIT_TXENC_8197F BIT(2)\n#define BIT_RXUHUSEDK_8197F BIT(1)\n#define BIT_TXUHUSEDK_8197F BIT(0)\n\n/* 2 REG_RXFILTER_ACTION_3_8197F */\n\n#define BIT_SHIFT_RXFILTER_ACTION_3_8197F 0\n#define BIT_MASK_RXFILTER_ACTION_3_8197F 0xff\n#define BIT_RXFILTER_ACTION_3_8197F(x)                                         \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_3_8197F)                              \\\n\t << BIT_SHIFT_RXFILTER_ACTION_3_8197F)\n#define BITS_RXFILTER_ACTION_3_8197F                                           \\\n\t(BIT_MASK_RXFILTER_ACTION_3_8197F << BIT_SHIFT_RXFILTER_ACTION_3_8197F)\n#define BIT_CLEAR_RXFILTER_ACTION_3_8197F(x)                                   \\\n\t((x) & (~BITS_RXFILTER_ACTION_3_8197F))\n#define BIT_GET_RXFILTER_ACTION_3_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8197F) &                          \\\n\t BIT_MASK_RXFILTER_ACTION_3_8197F)\n#define BIT_SET_RXFILTER_ACTION_3_8197F(x, v)                                  \\\n\t(BIT_CLEAR_RXFILTER_ACTION_3_8197F(x) | BIT_RXFILTER_ACTION_3_8197F(v))\n\n/* 2 REG_RXFILTER_CATEGORY_3_8197F */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_3_8197F 0\n#define BIT_MASK_RXFILTER_CATEGORY_3_8197F 0xff\n#define BIT_RXFILTER_CATEGORY_3_8197F(x)                                       \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_3_8197F)                            \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_3_8197F)\n#define BITS_RXFILTER_CATEGORY_3_8197F                                         \\\n\t(BIT_MASK_RXFILTER_CATEGORY_3_8197F                                    \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_3_8197F)\n#define BIT_CLEAR_RXFILTER_CATEGORY_3_8197F(x)                                 \\\n\t((x) & (~BITS_RXFILTER_CATEGORY_3_8197F))\n#define BIT_GET_RXFILTER_CATEGORY_3_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) &                        \\\n\t BIT_MASK_RXFILTER_CATEGORY_3_8197F)\n#define BIT_SET_RXFILTER_CATEGORY_3_8197F(x, v)                                \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_3_8197F(x) |                              \\\n\t BIT_RXFILTER_CATEGORY_3_8197F(v))\n\n/* 2 REG_RXFILTER_ACTION_2_8197F */\n\n#define BIT_SHIFT_RXFILTER_ACTION_2_8197F 0\n#define BIT_MASK_RXFILTER_ACTION_2_8197F 0xff\n#define BIT_RXFILTER_ACTION_2_8197F(x)                                         \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_2_8197F)                              \\\n\t << BIT_SHIFT_RXFILTER_ACTION_2_8197F)\n#define BITS_RXFILTER_ACTION_2_8197F                                           \\\n\t(BIT_MASK_RXFILTER_ACTION_2_8197F << BIT_SHIFT_RXFILTER_ACTION_2_8197F)\n#define BIT_CLEAR_RXFILTER_ACTION_2_8197F(x)                                   \\\n\t((x) & (~BITS_RXFILTER_ACTION_2_8197F))\n#define BIT_GET_RXFILTER_ACTION_2_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8197F) &                          \\\n\t BIT_MASK_RXFILTER_ACTION_2_8197F)\n#define BIT_SET_RXFILTER_ACTION_2_8197F(x, v)                                  \\\n\t(BIT_CLEAR_RXFILTER_ACTION_2_8197F(x) | BIT_RXFILTER_ACTION_2_8197F(v))\n\n/* 2 REG_RXFILTER_CATEGORY_2_8197F */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_2_8197F 0\n#define BIT_MASK_RXFILTER_CATEGORY_2_8197F 0xff\n#define BIT_RXFILTER_CATEGORY_2_8197F(x)                                       \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_2_8197F)                            \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_2_8197F)\n#define BITS_RXFILTER_CATEGORY_2_8197F                                         \\\n\t(BIT_MASK_RXFILTER_CATEGORY_2_8197F                                    \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_2_8197F)\n#define BIT_CLEAR_RXFILTER_CATEGORY_2_8197F(x)                                 \\\n\t((x) & (~BITS_RXFILTER_CATEGORY_2_8197F))\n#define BIT_GET_RXFILTER_CATEGORY_2_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) &                        \\\n\t BIT_MASK_RXFILTER_CATEGORY_2_8197F)\n#define BIT_SET_RXFILTER_CATEGORY_2_8197F(x, v)                                \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_2_8197F(x) |                              \\\n\t BIT_RXFILTER_CATEGORY_2_8197F(v))\n\n/* 2 REG_RXFLTMAP4_8197F (RX FILTER MAP GROUP 4) */\n#define BIT_CTRLFLT15EN_FW_8197F BIT(15)\n#define BIT_CTRLFLT14EN_FW_8197F BIT(14)\n#define BIT_CTRLFLT13EN_FW_8197F BIT(13)\n#define BIT_CTRLFLT12EN_FW_8197F BIT(12)\n#define BIT_CTRLFLT11EN_FW_8197F BIT(11)\n#define BIT_CTRLFLT10EN_FW_8197F BIT(10)\n#define BIT_CTRLFLT9EN_FW_8197F BIT(9)\n#define BIT_CTRLFLT8EN_FW_8197F BIT(8)\n#define BIT_CTRLFLT7EN_FW_8197F BIT(7)\n#define BIT_CTRLFLT6EN_FW_8197F BIT(6)\n#define BIT_CTRLFLT5EN_FW_8197F BIT(5)\n#define BIT_CTRLFLT4EN_FW_8197F BIT(4)\n#define BIT_CTRLFLT3EN_FW_8197F BIT(3)\n#define BIT_CTRLFLT2EN_FW_8197F BIT(2)\n#define BIT_CTRLFLT1EN_FW_8197F BIT(1)\n#define BIT_CTRLFLT0EN_FW_8197F BIT(0)\n\n/* 2 REG_RXFLTMAP3_8197F (RX FILTER MAP GROUP 3) */\n#define BIT_MGTFLT15EN_FW_8197F BIT(15)\n#define BIT_MGTFLT14EN_FW_8197F BIT(14)\n#define BIT_MGTFLT13EN_FW_8197F BIT(13)\n#define BIT_MGTFLT12EN_FW_8197F BIT(12)\n#define BIT_MGTFLT11EN_FW_8197F BIT(11)\n#define BIT_MGTFLT10EN_FW_8197F BIT(10)\n#define BIT_MGTFLT9EN_FW_8197F BIT(9)\n#define BIT_MGTFLT8EN_FW_8197F BIT(8)\n#define BIT_MGTFLT7EN_FW_8197F BIT(7)\n#define BIT_MGTFLT6EN_FW_8197F BIT(6)\n#define BIT_MGTFLT5EN_FW_8197F BIT(5)\n#define BIT_MGTFLT4EN_FW_8197F BIT(4)\n#define BIT_MGTFLT3EN_FW_8197F BIT(3)\n#define BIT_MGTFLT2EN_FW_8197F BIT(2)\n#define BIT_MGTFLT1EN_FW_8197F BIT(1)\n#define BIT_MGTFLT0EN_FW_8197F BIT(0)\n\n/* 2 REG_RXFLTMAP6_8197F (RX FILTER MAP GROUP 3) */\n#define BIT_ACTIONFLT15EN_FW_8197F BIT(15)\n#define BIT_ACTIONFLT14EN_FW_8197F BIT(14)\n#define BIT_ACTIONFLT13EN_FW_8197F BIT(13)\n#define BIT_ACTIONFLT12EN_FW_8197F BIT(12)\n#define BIT_ACTIONFLT11EN_FW_8197F BIT(11)\n#define BIT_ACTIONFLT10EN_FW_8197F BIT(10)\n#define BIT_ACTIONFLT9EN_FW_8197F BIT(9)\n#define BIT_ACTIONFLT8EN_FW_8197F BIT(8)\n#define BIT_ACTIONFLT7EN_FW_8197F BIT(7)\n#define BIT_ACTIONFLT6EN_FW_8197F BIT(6)\n#define BIT_ACTIONFLT5EN_FW_8197F BIT(5)\n#define BIT_ACTIONFLT4EN_FW_8197F BIT(4)\n#define BIT_ACTIONFLT3EN_FW_8197F BIT(3)\n#define BIT_ACTIONFLT2EN_FW_8197F BIT(2)\n#define BIT_ACTIONFLT1EN_FW_8197F BIT(1)\n#define BIT_ACTIONFLT0EN_FW_8197F BIT(0)\n\n/* 2 REG_RXFLTMAP5_8197F (RX FILTER MAP GROUP 3) */\n#define BIT_DATAFLT15EN_FW_8197F BIT(15)\n#define BIT_DATAFLT14EN_FW_8197F BIT(14)\n#define BIT_DATAFLT13EN_FW_8197F BIT(13)\n#define BIT_DATAFLT12EN_FW_8197F BIT(12)\n#define BIT_DATAFLT11EN_FW_8197F BIT(11)\n#define BIT_DATAFLT10EN_FW_8197F BIT(10)\n#define BIT_DATAFLT9EN_FW_8197F BIT(9)\n#define BIT_DATAFLT8EN_FW_8197F BIT(8)\n#define BIT_DATAFLT7EN_FW_8197F BIT(7)\n#define BIT_DATAFLT6EN_FW_8197F BIT(6)\n#define BIT_DATAFLT5EN_FW_8197F BIT(5)\n#define BIT_DATAFLT4EN_FW_8197F BIT(4)\n#define BIT_DATAFLT3EN_FW_8197F BIT(3)\n#define BIT_DATAFLT2EN_FW_8197F BIT(2)\n#define BIT_DATAFLT1EN_FW_8197F BIT(1)\n#define BIT_DATAFLT0EN_FW_8197F BIT(0)\n\n/* 2 REG_WMMPS_UAPSD_TID_8197F (WMM POWER SAVE UAPSD TID REGISTER) */\n#define BIT_WMMPS_UAPSD_TID7_8197F BIT(7)\n#define BIT_WMMPS_UAPSD_TID6_8197F BIT(6)\n#define BIT_WMMPS_UAPSD_TID5_8197F BIT(5)\n#define BIT_WMMPS_UAPSD_TID4_8197F BIT(4)\n#define BIT_WMMPS_UAPSD_TID3_8197F BIT(3)\n#define BIT_WMMPS_UAPSD_TID2_8197F BIT(2)\n#define BIT_WMMPS_UAPSD_TID1_8197F BIT(1)\n#define BIT_WMMPS_UAPSD_TID0_8197F BIT(0)\n\n/* 2 REG_PS_RX_INFO_8197F (POWER SAVE RX INFORMATION REGISTER) */\n\n#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F 5\n#define BIT_MASK_PORTSEL__PS_RX_INFO_8197F 0x7\n#define BIT_PORTSEL__PS_RX_INFO_8197F(x)                                       \\\n\t(((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8197F)                            \\\n\t << BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F)\n#define BITS_PORTSEL__PS_RX_INFO_8197F                                         \\\n\t(BIT_MASK_PORTSEL__PS_RX_INFO_8197F                                    \\\n\t << BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F)\n#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8197F(x)                                 \\\n\t((x) & (~BITS_PORTSEL__PS_RX_INFO_8197F))\n#define BIT_GET_PORTSEL__PS_RX_INFO_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) &                        \\\n\t BIT_MASK_PORTSEL__PS_RX_INFO_8197F)\n#define BIT_SET_PORTSEL__PS_RX_INFO_8197F(x, v)                                \\\n\t(BIT_CLEAR_PORTSEL__PS_RX_INFO_8197F(x) |                              \\\n\t BIT_PORTSEL__PS_RX_INFO_8197F(v))\n\n#define BIT_RXCTRLIN0_8197F BIT(4)\n#define BIT_RXMGTIN0_8197F BIT(3)\n#define BIT_RXDATAIN2_8197F BIT(2)\n#define BIT_RXDATAIN1_8197F BIT(1)\n#define BIT_RXDATAIN0_8197F BIT(0)\n\n/* 2 REG_NOT_VALID_8197F */\n#define BIT_CHK_TSF_TA_8197F BIT(2)\n#define BIT_CHK_TSF_CBSSID_8197F BIT(1)\n#define BIT_CHK_TSF_EN_8197F BIT(0)\n\n/* 2 REG_WOW_CTRL_8197F (WAKE ON WLAN CONTROL REGISTER) */\n\n#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F 6\n#define BIT_MASK_PSF_BSSIDSEL_B2B1_8197F 0x3\n#define BIT_PSF_BSSIDSEL_B2B1_8197F(x)                                         \\\n\t(((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8197F)                              \\\n\t << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F)\n#define BITS_PSF_BSSIDSEL_B2B1_8197F                                           \\\n\t(BIT_MASK_PSF_BSSIDSEL_B2B1_8197F << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F)\n#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8197F(x)                                   \\\n\t((x) & (~BITS_PSF_BSSIDSEL_B2B1_8197F))\n#define BIT_GET_PSF_BSSIDSEL_B2B1_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) &                          \\\n\t BIT_MASK_PSF_BSSIDSEL_B2B1_8197F)\n#define BIT_SET_PSF_BSSIDSEL_B2B1_8197F(x, v)                                  \\\n\t(BIT_CLEAR_PSF_BSSIDSEL_B2B1_8197F(x) | BIT_PSF_BSSIDSEL_B2B1_8197F(v))\n\n#define BIT_WOWHCI_8197F BIT(5)\n#define BIT_PSF_BSSIDSEL_B0_8197F BIT(4)\n#define BIT_UWF_8197F BIT(3)\n#define BIT_MAGIC_8197F BIT(2)\n#define BIT_WOWEN_8197F BIT(1)\n#define BIT_FORCE_WAKEUP_8197F BIT(0)\n\n/* 2 REG_LPNAV_CTRL_8197F (LOW POWER NAV CONTROL REGISTER) */\n#define BIT_LPNAV_EN_8197F BIT(31)\n\n#define BIT_SHIFT_LPNAV_EARLY_8197F 16\n#define BIT_MASK_LPNAV_EARLY_8197F 0x7fff\n#define BIT_LPNAV_EARLY_8197F(x)                                               \\\n\t(((x) & BIT_MASK_LPNAV_EARLY_8197F) << BIT_SHIFT_LPNAV_EARLY_8197F)\n#define BITS_LPNAV_EARLY_8197F                                                 \\\n\t(BIT_MASK_LPNAV_EARLY_8197F << BIT_SHIFT_LPNAV_EARLY_8197F)\n#define BIT_CLEAR_LPNAV_EARLY_8197F(x) ((x) & (~BITS_LPNAV_EARLY_8197F))\n#define BIT_GET_LPNAV_EARLY_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_LPNAV_EARLY_8197F) & BIT_MASK_LPNAV_EARLY_8197F)\n#define BIT_SET_LPNAV_EARLY_8197F(x, v)                                        \\\n\t(BIT_CLEAR_LPNAV_EARLY_8197F(x) | BIT_LPNAV_EARLY_8197F(v))\n\n#define BIT_SHIFT_LPNAV_TH_8197F 0\n#define BIT_MASK_LPNAV_TH_8197F 0xffff\n#define BIT_LPNAV_TH_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_LPNAV_TH_8197F) << BIT_SHIFT_LPNAV_TH_8197F)\n#define BITS_LPNAV_TH_8197F                                                    \\\n\t(BIT_MASK_LPNAV_TH_8197F << BIT_SHIFT_LPNAV_TH_8197F)\n#define BIT_CLEAR_LPNAV_TH_8197F(x) ((x) & (~BITS_LPNAV_TH_8197F))\n#define BIT_GET_LPNAV_TH_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_LPNAV_TH_8197F) & BIT_MASK_LPNAV_TH_8197F)\n#define BIT_SET_LPNAV_TH_8197F(x, v)                                           \\\n\t(BIT_CLEAR_LPNAV_TH_8197F(x) | BIT_LPNAV_TH_8197F(v))\n\n/* 2 REG_WKFMCAM_CMD_8197F (WAKEUP FRAME CAM COMMAND REGISTER) */\n#define BIT_WKFCAM_POLLING_V1_8197F BIT(31)\n#define BIT_WKFCAM_CLR_V1_8197F BIT(30)\n#define BIT_WKFCAM_WE_8197F BIT(16)\n\n#define BIT_SHIFT_WKFCAM_ADDR_V2_8197F 8\n#define BIT_MASK_WKFCAM_ADDR_V2_8197F 0xff\n#define BIT_WKFCAM_ADDR_V2_8197F(x)                                            \\\n\t(((x) & BIT_MASK_WKFCAM_ADDR_V2_8197F)                                 \\\n\t << BIT_SHIFT_WKFCAM_ADDR_V2_8197F)\n#define BITS_WKFCAM_ADDR_V2_8197F                                              \\\n\t(BIT_MASK_WKFCAM_ADDR_V2_8197F << BIT_SHIFT_WKFCAM_ADDR_V2_8197F)\n#define BIT_CLEAR_WKFCAM_ADDR_V2_8197F(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8197F))\n#define BIT_GET_WKFCAM_ADDR_V2_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8197F) &                             \\\n\t BIT_MASK_WKFCAM_ADDR_V2_8197F)\n#define BIT_SET_WKFCAM_ADDR_V2_8197F(x, v)                                     \\\n\t(BIT_CLEAR_WKFCAM_ADDR_V2_8197F(x) | BIT_WKFCAM_ADDR_V2_8197F(v))\n\n#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F 0\n#define BIT_MASK_WKFCAM_CAM_NUM_V1_8197F 0xff\n#define BIT_WKFCAM_CAM_NUM_V1_8197F(x)                                         \\\n\t(((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8197F)                              \\\n\t << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F)\n#define BITS_WKFCAM_CAM_NUM_V1_8197F                                           \\\n\t(BIT_MASK_WKFCAM_CAM_NUM_V1_8197F << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F)\n#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8197F(x)                                   \\\n\t((x) & (~BITS_WKFCAM_CAM_NUM_V1_8197F))\n#define BIT_GET_WKFCAM_CAM_NUM_V1_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) &                          \\\n\t BIT_MASK_WKFCAM_CAM_NUM_V1_8197F)\n#define BIT_SET_WKFCAM_CAM_NUM_V1_8197F(x, v)                                  \\\n\t(BIT_CLEAR_WKFCAM_CAM_NUM_V1_8197F(x) | BIT_WKFCAM_CAM_NUM_V1_8197F(v))\n\n/* 2 REG_WKFMCAM_RWD_8197F (WAKEUP FRAME READ/WRITE DATA) */\n\n#define BIT_SHIFT_WKFMCAM_RWD_8197F 0\n#define BIT_MASK_WKFMCAM_RWD_8197F 0xffffffffL\n#define BIT_WKFMCAM_RWD_8197F(x)                                               \\\n\t(((x) & BIT_MASK_WKFMCAM_RWD_8197F) << BIT_SHIFT_WKFMCAM_RWD_8197F)\n#define BITS_WKFMCAM_RWD_8197F                                                 \\\n\t(BIT_MASK_WKFMCAM_RWD_8197F << BIT_SHIFT_WKFMCAM_RWD_8197F)\n#define BIT_CLEAR_WKFMCAM_RWD_8197F(x) ((x) & (~BITS_WKFMCAM_RWD_8197F))\n#define BIT_GET_WKFMCAM_RWD_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_WKFMCAM_RWD_8197F) & BIT_MASK_WKFMCAM_RWD_8197F)\n#define BIT_SET_WKFMCAM_RWD_8197F(x, v)                                        \\\n\t(BIT_CLEAR_WKFMCAM_RWD_8197F(x) | BIT_WKFMCAM_RWD_8197F(v))\n\n/* 2 REG_RXFLTMAP1_8197F (RX FILTER MAP GROUP 1) */\n#define BIT_CTRLFLT15EN_8197F BIT(15)\n#define BIT_CTRLFLT14EN_8197F BIT(14)\n#define BIT_CTRLFLT13EN_8197F BIT(13)\n#define BIT_CTRLFLT12EN_8197F BIT(12)\n#define BIT_CTRLFLT11EN_8197F BIT(11)\n#define BIT_CTRLFLT10EN_8197F BIT(10)\n#define BIT_CTRLFLT9EN_8197F BIT(9)\n#define BIT_CTRLFLT8EN_8197F BIT(8)\n#define BIT_CTRLFLT7EN_8197F BIT(7)\n#define BIT_CTRLFLT6EN_8197F BIT(6)\n#define BIT_CTRLFLT5EN_8197F BIT(5)\n#define BIT_CTRLFLT4EN_8197F BIT(4)\n#define BIT_CTRLFLT3EN_8197F BIT(3)\n#define BIT_CTRLFLT2EN_8197F BIT(2)\n#define BIT_CTRLFLT1EN_8197F BIT(1)\n#define BIT_CTRLFLT0EN_8197F BIT(0)\n\n/* 2 REG_RXFLTMAP0_8197F (RX FILTER MAP GROUP 0) */\n#define BIT_MGTFLT15EN_8197F BIT(15)\n#define BIT_MGTFLT14EN_8197F BIT(14)\n#define BIT_MGTFLT13EN_8197F BIT(13)\n#define BIT_MGTFLT12EN_8197F BIT(12)\n#define BIT_MGTFLT11EN_8197F BIT(11)\n#define BIT_MGTFLT10EN_8197F BIT(10)\n#define BIT_MGTFLT9EN_8197F BIT(9)\n#define BIT_MGTFLT8EN_8197F BIT(8)\n#define BIT_MGTFLT7EN_8197F BIT(7)\n#define BIT_MGTFLT6EN_8197F BIT(6)\n#define BIT_MGTFLT5EN_8197F BIT(5)\n#define BIT_MGTFLT4EN_8197F BIT(4)\n#define BIT_MGTFLT3EN_8197F BIT(3)\n#define BIT_MGTFLT2EN_8197F BIT(2)\n#define BIT_MGTFLT1EN_8197F BIT(1)\n#define BIT_MGTFLT0EN_8197F BIT(0)\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_RXFLTMAP_8197F (RX FILTER MAP GROUP 2) */\n#define BIT_DATAFLT15EN_8197F BIT(15)\n#define BIT_DATAFLT14EN_8197F BIT(14)\n#define BIT_DATAFLT13EN_8197F BIT(13)\n#define BIT_DATAFLT12EN_8197F BIT(12)\n#define BIT_DATAFLT11EN_8197F BIT(11)\n#define BIT_DATAFLT10EN_8197F BIT(10)\n#define BIT_DATAFLT9EN_8197F BIT(9)\n#define BIT_DATAFLT8EN_8197F BIT(8)\n#define BIT_DATAFLT7EN_8197F BIT(7)\n#define BIT_DATAFLT6EN_8197F BIT(6)\n#define BIT_DATAFLT5EN_8197F BIT(5)\n#define BIT_DATAFLT4EN_8197F BIT(4)\n#define BIT_DATAFLT3EN_8197F BIT(3)\n#define BIT_DATAFLT2EN_8197F BIT(2)\n#define BIT_DATAFLT1EN_8197F BIT(1)\n#define BIT_DATAFLT0EN_8197F BIT(0)\n\n/* 2 REG_BCN_PSR_RPT_8197F (BEACON PARSER REPORT REGISTER) */\n\n#define BIT_SHIFT_DTIM_CNT_8197F 24\n#define BIT_MASK_DTIM_CNT_8197F 0xff\n#define BIT_DTIM_CNT_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_DTIM_CNT_8197F) << BIT_SHIFT_DTIM_CNT_8197F)\n#define BITS_DTIM_CNT_8197F                                                    \\\n\t(BIT_MASK_DTIM_CNT_8197F << BIT_SHIFT_DTIM_CNT_8197F)\n#define BIT_CLEAR_DTIM_CNT_8197F(x) ((x) & (~BITS_DTIM_CNT_8197F))\n#define BIT_GET_DTIM_CNT_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT_8197F) & BIT_MASK_DTIM_CNT_8197F)\n#define BIT_SET_DTIM_CNT_8197F(x, v)                                           \\\n\t(BIT_CLEAR_DTIM_CNT_8197F(x) | BIT_DTIM_CNT_8197F(v))\n\n#define BIT_SHIFT_DTIM_PERIOD_8197F 16\n#define BIT_MASK_DTIM_PERIOD_8197F 0xff\n#define BIT_DTIM_PERIOD_8197F(x)                                               \\\n\t(((x) & BIT_MASK_DTIM_PERIOD_8197F) << BIT_SHIFT_DTIM_PERIOD_8197F)\n#define BITS_DTIM_PERIOD_8197F                                                 \\\n\t(BIT_MASK_DTIM_PERIOD_8197F << BIT_SHIFT_DTIM_PERIOD_8197F)\n#define BIT_CLEAR_DTIM_PERIOD_8197F(x) ((x) & (~BITS_DTIM_PERIOD_8197F))\n#define BIT_GET_DTIM_PERIOD_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD_8197F) & BIT_MASK_DTIM_PERIOD_8197F)\n#define BIT_SET_DTIM_PERIOD_8197F(x, v)                                        \\\n\t(BIT_CLEAR_DTIM_PERIOD_8197F(x) | BIT_DTIM_PERIOD_8197F(v))\n\n#define BIT_DTIM_8197F BIT(15)\n#define BIT_TIM_8197F BIT(14)\n\n#define BIT_SHIFT_PS_AID_0_8197F 0\n#define BIT_MASK_PS_AID_0_8197F 0x7ff\n#define BIT_PS_AID_0_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_0_8197F) << BIT_SHIFT_PS_AID_0_8197F)\n#define BITS_PS_AID_0_8197F                                                    \\\n\t(BIT_MASK_PS_AID_0_8197F << BIT_SHIFT_PS_AID_0_8197F)\n#define BIT_CLEAR_PS_AID_0_8197F(x) ((x) & (~BITS_PS_AID_0_8197F))\n#define BIT_GET_PS_AID_0_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_0_8197F) & BIT_MASK_PS_AID_0_8197F)\n#define BIT_SET_PS_AID_0_8197F(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_0_8197F(x) | BIT_PS_AID_0_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n#define BIT_FLC_RPCT_V1_8197F BIT(7)\n#define BIT_MODE_8197F BIT(6)\n\n#define BIT_SHIFT_TRPCD_8197F 0\n#define BIT_MASK_TRPCD_8197F 0x3f\n#define BIT_TRPCD_8197F(x)                                                     \\\n\t(((x) & BIT_MASK_TRPCD_8197F) << BIT_SHIFT_TRPCD_8197F)\n#define BITS_TRPCD_8197F (BIT_MASK_TRPCD_8197F << BIT_SHIFT_TRPCD_8197F)\n#define BIT_CLEAR_TRPCD_8197F(x) ((x) & (~BITS_TRPCD_8197F))\n#define BIT_GET_TRPCD_8197F(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TRPCD_8197F) & BIT_MASK_TRPCD_8197F)\n#define BIT_SET_TRPCD_8197F(x, v)                                              \\\n\t(BIT_CLEAR_TRPCD_8197F(x) | BIT_TRPCD_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n#define BIT_CMF_8197F BIT(2)\n#define BIT_CCF_8197F BIT(1)\n#define BIT_CDF_8197F BIT(0)\n\n/* 2 REG_NOT_VALID_8197F */\n\n#define BIT_SHIFT_FLC_RPCT_8197F 0\n#define BIT_MASK_FLC_RPCT_8197F 0xff\n#define BIT_FLC_RPCT_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_FLC_RPCT_8197F) << BIT_SHIFT_FLC_RPCT_8197F)\n#define BITS_FLC_RPCT_8197F                                                    \\\n\t(BIT_MASK_FLC_RPCT_8197F << BIT_SHIFT_FLC_RPCT_8197F)\n#define BIT_CLEAR_FLC_RPCT_8197F(x) ((x) & (~BITS_FLC_RPCT_8197F))\n#define BIT_GET_FLC_RPCT_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_FLC_RPCT_8197F) & BIT_MASK_FLC_RPCT_8197F)\n#define BIT_SET_FLC_RPCT_8197F(x, v)                                           \\\n\t(BIT_CLEAR_FLC_RPCT_8197F(x) | BIT_FLC_RPCT_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n#define BIT_SHIFT_FLC_RPC_8197F 0\n#define BIT_MASK_FLC_RPC_8197F 0xff\n#define BIT_FLC_RPC_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_FLC_RPC_8197F) << BIT_SHIFT_FLC_RPC_8197F)\n#define BITS_FLC_RPC_8197F (BIT_MASK_FLC_RPC_8197F << BIT_SHIFT_FLC_RPC_8197F)\n#define BIT_CLEAR_FLC_RPC_8197F(x) ((x) & (~BITS_FLC_RPC_8197F))\n#define BIT_GET_FLC_RPC_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_FLC_RPC_8197F) & BIT_MASK_FLC_RPC_8197F)\n#define BIT_SET_FLC_RPC_8197F(x, v)                                            \\\n\t(BIT_CLEAR_FLC_RPC_8197F(x) | BIT_FLC_RPC_8197F(v))\n\n/* 2 REG_RXPKTMON_CTRL_8197F */\n\n#define BIT_SHIFT_RXBKQPKT_SEQ_8197F 20\n#define BIT_MASK_RXBKQPKT_SEQ_8197F 0xf\n#define BIT_RXBKQPKT_SEQ_8197F(x)                                              \\\n\t(((x) & BIT_MASK_RXBKQPKT_SEQ_8197F) << BIT_SHIFT_RXBKQPKT_SEQ_8197F)\n#define BITS_RXBKQPKT_SEQ_8197F                                                \\\n\t(BIT_MASK_RXBKQPKT_SEQ_8197F << BIT_SHIFT_RXBKQPKT_SEQ_8197F)\n#define BIT_CLEAR_RXBKQPKT_SEQ_8197F(x) ((x) & (~BITS_RXBKQPKT_SEQ_8197F))\n#define BIT_GET_RXBKQPKT_SEQ_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8197F) & BIT_MASK_RXBKQPKT_SEQ_8197F)\n#define BIT_SET_RXBKQPKT_SEQ_8197F(x, v)                                       \\\n\t(BIT_CLEAR_RXBKQPKT_SEQ_8197F(x) | BIT_RXBKQPKT_SEQ_8197F(v))\n\n#define BIT_SHIFT_RXBEQPKT_SEQ_8197F 16\n#define BIT_MASK_RXBEQPKT_SEQ_8197F 0xf\n#define BIT_RXBEQPKT_SEQ_8197F(x)                                              \\\n\t(((x) & BIT_MASK_RXBEQPKT_SEQ_8197F) << BIT_SHIFT_RXBEQPKT_SEQ_8197F)\n#define BITS_RXBEQPKT_SEQ_8197F                                                \\\n\t(BIT_MASK_RXBEQPKT_SEQ_8197F << BIT_SHIFT_RXBEQPKT_SEQ_8197F)\n#define BIT_CLEAR_RXBEQPKT_SEQ_8197F(x) ((x) & (~BITS_RXBEQPKT_SEQ_8197F))\n#define BIT_GET_RXBEQPKT_SEQ_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8197F) & BIT_MASK_RXBEQPKT_SEQ_8197F)\n#define BIT_SET_RXBEQPKT_SEQ_8197F(x, v)                                       \\\n\t(BIT_CLEAR_RXBEQPKT_SEQ_8197F(x) | BIT_RXBEQPKT_SEQ_8197F(v))\n\n#define BIT_SHIFT_RXVIQPKT_SEQ_8197F 12\n#define BIT_MASK_RXVIQPKT_SEQ_8197F 0xf\n#define BIT_RXVIQPKT_SEQ_8197F(x)                                              \\\n\t(((x) & BIT_MASK_RXVIQPKT_SEQ_8197F) << BIT_SHIFT_RXVIQPKT_SEQ_8197F)\n#define BITS_RXVIQPKT_SEQ_8197F                                                \\\n\t(BIT_MASK_RXVIQPKT_SEQ_8197F << BIT_SHIFT_RXVIQPKT_SEQ_8197F)\n#define BIT_CLEAR_RXVIQPKT_SEQ_8197F(x) ((x) & (~BITS_RXVIQPKT_SEQ_8197F))\n#define BIT_GET_RXVIQPKT_SEQ_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8197F) & BIT_MASK_RXVIQPKT_SEQ_8197F)\n#define BIT_SET_RXVIQPKT_SEQ_8197F(x, v)                                       \\\n\t(BIT_CLEAR_RXVIQPKT_SEQ_8197F(x) | BIT_RXVIQPKT_SEQ_8197F(v))\n\n#define BIT_SHIFT_RXVOQPKT_SEQ_8197F 8\n#define BIT_MASK_RXVOQPKT_SEQ_8197F 0xf\n#define BIT_RXVOQPKT_SEQ_8197F(x)                                              \\\n\t(((x) & BIT_MASK_RXVOQPKT_SEQ_8197F) << BIT_SHIFT_RXVOQPKT_SEQ_8197F)\n#define BITS_RXVOQPKT_SEQ_8197F                                                \\\n\t(BIT_MASK_RXVOQPKT_SEQ_8197F << BIT_SHIFT_RXVOQPKT_SEQ_8197F)\n#define BIT_CLEAR_RXVOQPKT_SEQ_8197F(x) ((x) & (~BITS_RXVOQPKT_SEQ_8197F))\n#define BIT_GET_RXVOQPKT_SEQ_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8197F) & BIT_MASK_RXVOQPKT_SEQ_8197F)\n#define BIT_SET_RXVOQPKT_SEQ_8197F(x, v)                                       \\\n\t(BIT_CLEAR_RXVOQPKT_SEQ_8197F(x) | BIT_RXVOQPKT_SEQ_8197F(v))\n\n#define BIT_RXBKQPKT_ERR_8197F BIT(7)\n#define BIT_RXBEQPKT_ERR_8197F BIT(6)\n#define BIT_RXVIQPKT_ERR_8197F BIT(5)\n#define BIT_RXVOQPKT_ERR_8197F BIT(4)\n#define BIT_RXDMA_MON_EN_8197F BIT(2)\n#define BIT_RXPKT_MON_RST_8197F BIT(1)\n#define BIT_RXPKT_MON_EN_8197F BIT(0)\n\n/* 2 REG_STATE_MON_8197F */\n\n#define BIT_SHIFT_STATE_SEL_8197F 24\n#define BIT_MASK_STATE_SEL_8197F 0x1f\n#define BIT_STATE_SEL_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_STATE_SEL_8197F) << BIT_SHIFT_STATE_SEL_8197F)\n#define BITS_STATE_SEL_8197F                                                   \\\n\t(BIT_MASK_STATE_SEL_8197F << BIT_SHIFT_STATE_SEL_8197F)\n#define BIT_CLEAR_STATE_SEL_8197F(x) ((x) & (~BITS_STATE_SEL_8197F))\n#define BIT_GET_STATE_SEL_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_STATE_SEL_8197F) & BIT_MASK_STATE_SEL_8197F)\n#define BIT_SET_STATE_SEL_8197F(x, v)                                          \\\n\t(BIT_CLEAR_STATE_SEL_8197F(x) | BIT_STATE_SEL_8197F(v))\n\n#define BIT_SHIFT_STATE_INFO_8197F 8\n#define BIT_MASK_STATE_INFO_8197F 0xff\n#define BIT_STATE_INFO_8197F(x)                                                \\\n\t(((x) & BIT_MASK_STATE_INFO_8197F) << BIT_SHIFT_STATE_INFO_8197F)\n#define BITS_STATE_INFO_8197F                                                  \\\n\t(BIT_MASK_STATE_INFO_8197F << BIT_SHIFT_STATE_INFO_8197F)\n#define BIT_CLEAR_STATE_INFO_8197F(x) ((x) & (~BITS_STATE_INFO_8197F))\n#define BIT_GET_STATE_INFO_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_STATE_INFO_8197F) & BIT_MASK_STATE_INFO_8197F)\n#define BIT_SET_STATE_INFO_8197F(x, v)                                         \\\n\t(BIT_CLEAR_STATE_INFO_8197F(x) | BIT_STATE_INFO_8197F(v))\n\n#define BIT_UPD_NXT_STATE_8197F BIT(7)\n\n#define BIT_SHIFT_CUR_STATE_8197F 0\n#define BIT_MASK_CUR_STATE_8197F 0x7f\n#define BIT_CUR_STATE_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_CUR_STATE_8197F) << BIT_SHIFT_CUR_STATE_8197F)\n#define BITS_CUR_STATE_8197F                                                   \\\n\t(BIT_MASK_CUR_STATE_8197F << BIT_SHIFT_CUR_STATE_8197F)\n#define BIT_CLEAR_CUR_STATE_8197F(x) ((x) & (~BITS_CUR_STATE_8197F))\n#define BIT_GET_CUR_STATE_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_CUR_STATE_8197F) & BIT_MASK_CUR_STATE_8197F)\n#define BIT_SET_CUR_STATE_8197F(x, v)                                          \\\n\t(BIT_CLEAR_CUR_STATE_8197F(x) | BIT_CUR_STATE_8197F(v))\n\n/* 2 REG_ERROR_MON_8197F */\n#define BIT_MACRX_ERR_1_8197F BIT(17)\n#define BIT_MACRX_ERR_0_8197F BIT(16)\n#define BIT_MACTX_ERR_3_8197F BIT(3)\n#define BIT_MACTX_ERR_2_8197F BIT(2)\n#define BIT_MACTX_ERR_1_8197F BIT(1)\n#define BIT_MACTX_ERR_0_8197F BIT(0)\n\n/* 2 REG_SEARCH_MACID_8197F */\n#define BIT_EN_TXRPTBUF_CLK_8197F BIT(31)\n\n#define BIT_SHIFT_INFO_INDEX_OFFSET_8197F 16\n#define BIT_MASK_INFO_INDEX_OFFSET_8197F 0x1fff\n#define BIT_INFO_INDEX_OFFSET_8197F(x)                                         \\\n\t(((x) & BIT_MASK_INFO_INDEX_OFFSET_8197F)                              \\\n\t << BIT_SHIFT_INFO_INDEX_OFFSET_8197F)\n#define BITS_INFO_INDEX_OFFSET_8197F                                           \\\n\t(BIT_MASK_INFO_INDEX_OFFSET_8197F << BIT_SHIFT_INFO_INDEX_OFFSET_8197F)\n#define BIT_CLEAR_INFO_INDEX_OFFSET_8197F(x)                                   \\\n\t((x) & (~BITS_INFO_INDEX_OFFSET_8197F))\n#define BIT_GET_INFO_INDEX_OFFSET_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8197F) &                          \\\n\t BIT_MASK_INFO_INDEX_OFFSET_8197F)\n#define BIT_SET_INFO_INDEX_OFFSET_8197F(x, v)                                  \\\n\t(BIT_CLEAR_INFO_INDEX_OFFSET_8197F(x) | BIT_INFO_INDEX_OFFSET_8197F(v))\n\n#define BIT_DIS_INFOSRCH_8197F BIT(14)\n#define BIT_DISABLE_B0_8197F BIT(13)\n\n#define BIT_SHIFT_INFO_ADDR_OFFSET_8197F 0\n#define BIT_MASK_INFO_ADDR_OFFSET_8197F 0x1fff\n#define BIT_INFO_ADDR_OFFSET_8197F(x)                                          \\\n\t(((x) & BIT_MASK_INFO_ADDR_OFFSET_8197F)                               \\\n\t << BIT_SHIFT_INFO_ADDR_OFFSET_8197F)\n#define BITS_INFO_ADDR_OFFSET_8197F                                            \\\n\t(BIT_MASK_INFO_ADDR_OFFSET_8197F << BIT_SHIFT_INFO_ADDR_OFFSET_8197F)\n#define BIT_CLEAR_INFO_ADDR_OFFSET_8197F(x)                                    \\\n\t((x) & (~BITS_INFO_ADDR_OFFSET_8197F))\n#define BIT_GET_INFO_ADDR_OFFSET_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8197F) &                           \\\n\t BIT_MASK_INFO_ADDR_OFFSET_8197F)\n#define BIT_SET_INFO_ADDR_OFFSET_8197F(x, v)                                   \\\n\t(BIT_CLEAR_INFO_ADDR_OFFSET_8197F(x) | BIT_INFO_ADDR_OFFSET_8197F(v))\n\n/* 2 REG_BT_COEX_TABLE_8197F (BT-COEXISTENCE CONTROL REGISTER) */\n#define BIT_PRI_MASK_RX_RESP_8197F BIT(126)\n#define BIT_PRI_MASK_RXOFDM_8197F BIT(125)\n#define BIT_PRI_MASK_RXCCK_8197F BIT(124)\n\n#define BIT_SHIFT_PRI_MASK_TXAC_8197F (117 & CPU_OPT_WIDTH)\n#define BIT_MASK_PRI_MASK_TXAC_8197F 0x7f\n#define BIT_PRI_MASK_TXAC_8197F(x)                                             \\\n\t(((x) & BIT_MASK_PRI_MASK_TXAC_8197F) << BIT_SHIFT_PRI_MASK_TXAC_8197F)\n#define BITS_PRI_MASK_TXAC_8197F                                               \\\n\t(BIT_MASK_PRI_MASK_TXAC_8197F << BIT_SHIFT_PRI_MASK_TXAC_8197F)\n#define BIT_CLEAR_PRI_MASK_TXAC_8197F(x) ((x) & (~BITS_PRI_MASK_TXAC_8197F))\n#define BIT_GET_PRI_MASK_TXAC_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_TXAC_8197F) & BIT_MASK_PRI_MASK_TXAC_8197F)\n#define BIT_SET_PRI_MASK_TXAC_8197F(x, v)                                      \\\n\t(BIT_CLEAR_PRI_MASK_TXAC_8197F(x) | BIT_PRI_MASK_TXAC_8197F(v))\n\n#define BIT_SHIFT_PRI_MASK_NAV_8197F (109 & CPU_OPT_WIDTH)\n#define BIT_MASK_PRI_MASK_NAV_8197F 0xff\n#define BIT_PRI_MASK_NAV_8197F(x)                                              \\\n\t(((x) & BIT_MASK_PRI_MASK_NAV_8197F) << BIT_SHIFT_PRI_MASK_NAV_8197F)\n#define BITS_PRI_MASK_NAV_8197F                                                \\\n\t(BIT_MASK_PRI_MASK_NAV_8197F << BIT_SHIFT_PRI_MASK_NAV_8197F)\n#define BIT_CLEAR_PRI_MASK_NAV_8197F(x) ((x) & (~BITS_PRI_MASK_NAV_8197F))\n#define BIT_GET_PRI_MASK_NAV_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_NAV_8197F) & BIT_MASK_PRI_MASK_NAV_8197F)\n#define BIT_SET_PRI_MASK_NAV_8197F(x, v)                                       \\\n\t(BIT_CLEAR_PRI_MASK_NAV_8197F(x) | BIT_PRI_MASK_NAV_8197F(v))\n\n#define BIT_PRI_MASK_CCK_8197F BIT(108)\n#define BIT_PRI_MASK_OFDM_8197F BIT(107)\n#define BIT_PRI_MASK_RTY_8197F BIT(106)\n\n#define BIT_SHIFT_PRI_MASK_NUM_8197F (102 & CPU_OPT_WIDTH)\n#define BIT_MASK_PRI_MASK_NUM_8197F 0xf\n#define BIT_PRI_MASK_NUM_8197F(x)                                              \\\n\t(((x) & BIT_MASK_PRI_MASK_NUM_8197F) << BIT_SHIFT_PRI_MASK_NUM_8197F)\n#define BITS_PRI_MASK_NUM_8197F                                                \\\n\t(BIT_MASK_PRI_MASK_NUM_8197F << BIT_SHIFT_PRI_MASK_NUM_8197F)\n#define BIT_CLEAR_PRI_MASK_NUM_8197F(x) ((x) & (~BITS_PRI_MASK_NUM_8197F))\n#define BIT_GET_PRI_MASK_NUM_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_NUM_8197F) & BIT_MASK_PRI_MASK_NUM_8197F)\n#define BIT_SET_PRI_MASK_NUM_8197F(x, v)                                       \\\n\t(BIT_CLEAR_PRI_MASK_NUM_8197F(x) | BIT_PRI_MASK_NUM_8197F(v))\n\n#define BIT_SHIFT_PRI_MASK_TYPE_8197F (98 & CPU_OPT_WIDTH)\n#define BIT_MASK_PRI_MASK_TYPE_8197F 0xf\n#define BIT_PRI_MASK_TYPE_8197F(x)                                             \\\n\t(((x) & BIT_MASK_PRI_MASK_TYPE_8197F) << BIT_SHIFT_PRI_MASK_TYPE_8197F)\n#define BITS_PRI_MASK_TYPE_8197F                                               \\\n\t(BIT_MASK_PRI_MASK_TYPE_8197F << BIT_SHIFT_PRI_MASK_TYPE_8197F)\n#define BIT_CLEAR_PRI_MASK_TYPE_8197F(x) ((x) & (~BITS_PRI_MASK_TYPE_8197F))\n#define BIT_GET_PRI_MASK_TYPE_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_TYPE_8197F) & BIT_MASK_PRI_MASK_TYPE_8197F)\n#define BIT_SET_PRI_MASK_TYPE_8197F(x, v)                                      \\\n\t(BIT_CLEAR_PRI_MASK_TYPE_8197F(x) | BIT_PRI_MASK_TYPE_8197F(v))\n\n#define BIT_OOB_8197F BIT(97)\n#define BIT_ANT_SEL_8197F BIT(96)\n\n#define BIT_SHIFT_BREAK_TABLE_2_8197F (80 & CPU_OPT_WIDTH)\n#define BIT_MASK_BREAK_TABLE_2_8197F 0xffff\n#define BIT_BREAK_TABLE_2_8197F(x)                                             \\\n\t(((x) & BIT_MASK_BREAK_TABLE_2_8197F) << BIT_SHIFT_BREAK_TABLE_2_8197F)\n#define BITS_BREAK_TABLE_2_8197F                                               \\\n\t(BIT_MASK_BREAK_TABLE_2_8197F << BIT_SHIFT_BREAK_TABLE_2_8197F)\n#define BIT_CLEAR_BREAK_TABLE_2_8197F(x) ((x) & (~BITS_BREAK_TABLE_2_8197F))\n#define BIT_GET_BREAK_TABLE_2_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_BREAK_TABLE_2_8197F) & BIT_MASK_BREAK_TABLE_2_8197F)\n#define BIT_SET_BREAK_TABLE_2_8197F(x, v)                                      \\\n\t(BIT_CLEAR_BREAK_TABLE_2_8197F(x) | BIT_BREAK_TABLE_2_8197F(v))\n\n#define BIT_SHIFT_BREAK_TABLE_1_8197F (64 & CPU_OPT_WIDTH)\n#define BIT_MASK_BREAK_TABLE_1_8197F 0xffff\n#define BIT_BREAK_TABLE_1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_BREAK_TABLE_1_8197F) << BIT_SHIFT_BREAK_TABLE_1_8197F)\n#define BITS_BREAK_TABLE_1_8197F                                               \\\n\t(BIT_MASK_BREAK_TABLE_1_8197F << BIT_SHIFT_BREAK_TABLE_1_8197F)\n#define BIT_CLEAR_BREAK_TABLE_1_8197F(x) ((x) & (~BITS_BREAK_TABLE_1_8197F))\n#define BIT_GET_BREAK_TABLE_1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_BREAK_TABLE_1_8197F) & BIT_MASK_BREAK_TABLE_1_8197F)\n#define BIT_SET_BREAK_TABLE_1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_BREAK_TABLE_1_8197F(x) | BIT_BREAK_TABLE_1_8197F(v))\n\n#define BIT_SHIFT_COEX_TABLE_2_8197F (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_COEX_TABLE_2_8197F 0xffffffffL\n#define BIT_COEX_TABLE_2_8197F(x)                                              \\\n\t(((x) & BIT_MASK_COEX_TABLE_2_8197F) << BIT_SHIFT_COEX_TABLE_2_8197F)\n#define BITS_COEX_TABLE_2_8197F                                                \\\n\t(BIT_MASK_COEX_TABLE_2_8197F << BIT_SHIFT_COEX_TABLE_2_8197F)\n#define BIT_CLEAR_COEX_TABLE_2_8197F(x) ((x) & (~BITS_COEX_TABLE_2_8197F))\n#define BIT_GET_COEX_TABLE_2_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_COEX_TABLE_2_8197F) & BIT_MASK_COEX_TABLE_2_8197F)\n#define BIT_SET_COEX_TABLE_2_8197F(x, v)                                       \\\n\t(BIT_CLEAR_COEX_TABLE_2_8197F(x) | BIT_COEX_TABLE_2_8197F(v))\n\n#define BIT_SHIFT_COEX_TABLE_1_8197F 0\n#define BIT_MASK_COEX_TABLE_1_8197F 0xffffffffL\n#define BIT_COEX_TABLE_1_8197F(x)                                              \\\n\t(((x) & BIT_MASK_COEX_TABLE_1_8197F) << BIT_SHIFT_COEX_TABLE_1_8197F)\n#define BITS_COEX_TABLE_1_8197F                                                \\\n\t(BIT_MASK_COEX_TABLE_1_8197F << BIT_SHIFT_COEX_TABLE_1_8197F)\n#define BIT_CLEAR_COEX_TABLE_1_8197F(x) ((x) & (~BITS_COEX_TABLE_1_8197F))\n#define BIT_GET_COEX_TABLE_1_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_COEX_TABLE_1_8197F) & BIT_MASK_COEX_TABLE_1_8197F)\n#define BIT_SET_COEX_TABLE_1_8197F(x, v)                                       \\\n\t(BIT_CLEAR_COEX_TABLE_1_8197F(x) | BIT_COEX_TABLE_1_8197F(v))\n\n/* 2 REG_RXCMD_0_8197F */\n#define BIT_RXCMD_EN_8197F BIT(31)\n\n#define BIT_SHIFT_RXCMD_INFO_8197F 0\n#define BIT_MASK_RXCMD_INFO_8197F 0x7fffffffL\n#define BIT_RXCMD_INFO_8197F(x)                                                \\\n\t(((x) & BIT_MASK_RXCMD_INFO_8197F) << BIT_SHIFT_RXCMD_INFO_8197F)\n#define BITS_RXCMD_INFO_8197F                                                  \\\n\t(BIT_MASK_RXCMD_INFO_8197F << BIT_SHIFT_RXCMD_INFO_8197F)\n#define BIT_CLEAR_RXCMD_INFO_8197F(x) ((x) & (~BITS_RXCMD_INFO_8197F))\n#define BIT_GET_RXCMD_INFO_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXCMD_INFO_8197F) & BIT_MASK_RXCMD_INFO_8197F)\n#define BIT_SET_RXCMD_INFO_8197F(x, v)                                         \\\n\t(BIT_CLEAR_RXCMD_INFO_8197F(x) | BIT_RXCMD_INFO_8197F(v))\n\n/* 2 REG_RXCMD_1_8197F */\n\n#define BIT_SHIFT_RXCMD_PRD_8197F 0\n#define BIT_MASK_RXCMD_PRD_8197F 0xffff\n#define BIT_RXCMD_PRD_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_RXCMD_PRD_8197F) << BIT_SHIFT_RXCMD_PRD_8197F)\n#define BITS_RXCMD_PRD_8197F                                                   \\\n\t(BIT_MASK_RXCMD_PRD_8197F << BIT_SHIFT_RXCMD_PRD_8197F)\n#define BIT_CLEAR_RXCMD_PRD_8197F(x) ((x) & (~BITS_RXCMD_PRD_8197F))\n#define BIT_GET_RXCMD_PRD_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_RXCMD_PRD_8197F) & BIT_MASK_RXCMD_PRD_8197F)\n#define BIT_SET_RXCMD_PRD_8197F(x, v)                                          \\\n\t(BIT_CLEAR_RXCMD_PRD_8197F(x) | BIT_RXCMD_PRD_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_WMAC_RESP_TXINFO_8197F (RESPONSE TXINFO REGISTER) */\n\n#define BIT_SHIFT_WMAC_RESP_MFB_8197F 25\n#define BIT_MASK_WMAC_RESP_MFB_8197F 0x7f\n#define BIT_WMAC_RESP_MFB_8197F(x)                                             \\\n\t(((x) & BIT_MASK_WMAC_RESP_MFB_8197F) << BIT_SHIFT_WMAC_RESP_MFB_8197F)\n#define BITS_WMAC_RESP_MFB_8197F                                               \\\n\t(BIT_MASK_WMAC_RESP_MFB_8197F << BIT_SHIFT_WMAC_RESP_MFB_8197F)\n#define BIT_CLEAR_WMAC_RESP_MFB_8197F(x) ((x) & (~BITS_WMAC_RESP_MFB_8197F))\n#define BIT_GET_WMAC_RESP_MFB_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_MFB_8197F) & BIT_MASK_WMAC_RESP_MFB_8197F)\n#define BIT_SET_WMAC_RESP_MFB_8197F(x, v)                                      \\\n\t(BIT_CLEAR_WMAC_RESP_MFB_8197F(x) | BIT_WMAC_RESP_MFB_8197F(v))\n\n#define BIT_SHIFT_WMAC_ANTINF_SEL_8197F 23\n#define BIT_MASK_WMAC_ANTINF_SEL_8197F 0x3\n#define BIT_WMAC_ANTINF_SEL_8197F(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_ANTINF_SEL_8197F)                                \\\n\t << BIT_SHIFT_WMAC_ANTINF_SEL_8197F)\n#define BITS_WMAC_ANTINF_SEL_8197F                                             \\\n\t(BIT_MASK_WMAC_ANTINF_SEL_8197F << BIT_SHIFT_WMAC_ANTINF_SEL_8197F)\n#define BIT_CLEAR_WMAC_ANTINF_SEL_8197F(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8197F))\n#define BIT_GET_WMAC_ANTINF_SEL_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8197F) &                            \\\n\t BIT_MASK_WMAC_ANTINF_SEL_8197F)\n#define BIT_SET_WMAC_ANTINF_SEL_8197F(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_ANTINF_SEL_8197F(x) | BIT_WMAC_ANTINF_SEL_8197F(v))\n\n#define BIT_SHIFT_WMAC_ANTSEL_SEL_8197F 21\n#define BIT_MASK_WMAC_ANTSEL_SEL_8197F 0x3\n#define BIT_WMAC_ANTSEL_SEL_8197F(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_ANTSEL_SEL_8197F)                                \\\n\t << BIT_SHIFT_WMAC_ANTSEL_SEL_8197F)\n#define BITS_WMAC_ANTSEL_SEL_8197F                                             \\\n\t(BIT_MASK_WMAC_ANTSEL_SEL_8197F << BIT_SHIFT_WMAC_ANTSEL_SEL_8197F)\n#define BIT_CLEAR_WMAC_ANTSEL_SEL_8197F(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8197F))\n#define BIT_GET_WMAC_ANTSEL_SEL_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) &                            \\\n\t BIT_MASK_WMAC_ANTSEL_SEL_8197F)\n#define BIT_SET_WMAC_ANTSEL_SEL_8197F(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_ANTSEL_SEL_8197F(x) | BIT_WMAC_ANTSEL_SEL_8197F(v))\n\n#define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F 18\n#define BIT_MASK_R_WMAC_RESP_TXPOWER_8197F 0x7\n#define BIT_R_WMAC_RESP_TXPOWER_8197F(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8197F)                            \\\n\t << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F)\n#define BITS_R_WMAC_RESP_TXPOWER_8197F                                         \\\n\t(BIT_MASK_R_WMAC_RESP_TXPOWER_8197F                                    \\\n\t << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F)\n#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8197F(x)                                 \\\n\t((x) & (~BITS_R_WMAC_RESP_TXPOWER_8197F))\n#define BIT_GET_R_WMAC_RESP_TXPOWER_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) &                        \\\n\t BIT_MASK_R_WMAC_RESP_TXPOWER_8197F)\n#define BIT_SET_R_WMAC_RESP_TXPOWER_8197F(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_RESP_TXPOWER_8197F(x) |                              \\\n\t BIT_R_WMAC_RESP_TXPOWER_8197F(v))\n\n#define BIT_SHIFT_WMAC_RESP_TXANT_8197F 0\n#define BIT_MASK_WMAC_RESP_TXANT_8197F 0x3ffff\n#define BIT_WMAC_RESP_TXANT_8197F(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_RESP_TXANT_8197F)                                \\\n\t << BIT_SHIFT_WMAC_RESP_TXANT_8197F)\n#define BITS_WMAC_RESP_TXANT_8197F                                             \\\n\t(BIT_MASK_WMAC_RESP_TXANT_8197F << BIT_SHIFT_WMAC_RESP_TXANT_8197F)\n#define BIT_CLEAR_WMAC_RESP_TXANT_8197F(x) ((x) & (~BITS_WMAC_RESP_TXANT_8197F))\n#define BIT_GET_WMAC_RESP_TXANT_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8197F) &                            \\\n\t BIT_MASK_WMAC_RESP_TXANT_8197F)\n#define BIT_SET_WMAC_RESP_TXANT_8197F(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_RESP_TXANT_8197F(x) | BIT_WMAC_RESP_TXANT_8197F(v))\n\n/* 2 REG_BBPSF_CTRL_8197F */\n#define BIT_CTL_IDLE_CLR_CSI_RPT_8197F BIT(31)\n#define BIT_WMAC_USE_NDPARATE_8197F BIT(30)\n\n#define BIT_SHIFT_WMAC_CSI_RATE_8197F 24\n#define BIT_MASK_WMAC_CSI_RATE_8197F 0x3f\n#define BIT_WMAC_CSI_RATE_8197F(x)                                             \\\n\t(((x) & BIT_MASK_WMAC_CSI_RATE_8197F) << BIT_SHIFT_WMAC_CSI_RATE_8197F)\n#define BITS_WMAC_CSI_RATE_8197F                                               \\\n\t(BIT_MASK_WMAC_CSI_RATE_8197F << BIT_SHIFT_WMAC_CSI_RATE_8197F)\n#define BIT_CLEAR_WMAC_CSI_RATE_8197F(x) ((x) & (~BITS_WMAC_CSI_RATE_8197F))\n#define BIT_GET_WMAC_CSI_RATE_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_WMAC_CSI_RATE_8197F) & BIT_MASK_WMAC_CSI_RATE_8197F)\n#define BIT_SET_WMAC_CSI_RATE_8197F(x, v)                                      \\\n\t(BIT_CLEAR_WMAC_CSI_RATE_8197F(x) | BIT_WMAC_CSI_RATE_8197F(v))\n\n#define BIT_SHIFT_WMAC_RESP_TXRATE_8197F 16\n#define BIT_MASK_WMAC_RESP_TXRATE_8197F 0xff\n#define BIT_WMAC_RESP_TXRATE_8197F(x)                                          \\\n\t(((x) & BIT_MASK_WMAC_RESP_TXRATE_8197F)                               \\\n\t << BIT_SHIFT_WMAC_RESP_TXRATE_8197F)\n#define BITS_WMAC_RESP_TXRATE_8197F                                            \\\n\t(BIT_MASK_WMAC_RESP_TXRATE_8197F << BIT_SHIFT_WMAC_RESP_TXRATE_8197F)\n#define BIT_CLEAR_WMAC_RESP_TXRATE_8197F(x)                                    \\\n\t((x) & (~BITS_WMAC_RESP_TXRATE_8197F))\n#define BIT_GET_WMAC_RESP_TXRATE_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8197F) &                           \\\n\t BIT_MASK_WMAC_RESP_TXRATE_8197F)\n#define BIT_SET_WMAC_RESP_TXRATE_8197F(x, v)                                   \\\n\t(BIT_CLEAR_WMAC_RESP_TXRATE_8197F(x) | BIT_WMAC_RESP_TXRATE_8197F(v))\n\n#define BIT_BBPSF_MPDUCHKEN_8197F BIT(5)\n#define BIT_BBPSF_MHCHKEN_8197F BIT(4)\n#define BIT_BBPSF_ERRCHKEN_8197F BIT(3)\n\n#define BIT_SHIFT_BBPSF_ERRTHR_8197F 0\n#define BIT_MASK_BBPSF_ERRTHR_8197F 0x7\n#define BIT_BBPSF_ERRTHR_8197F(x)                                              \\\n\t(((x) & BIT_MASK_BBPSF_ERRTHR_8197F) << BIT_SHIFT_BBPSF_ERRTHR_8197F)\n#define BITS_BBPSF_ERRTHR_8197F                                                \\\n\t(BIT_MASK_BBPSF_ERRTHR_8197F << BIT_SHIFT_BBPSF_ERRTHR_8197F)\n#define BIT_CLEAR_BBPSF_ERRTHR_8197F(x) ((x) & (~BITS_BBPSF_ERRTHR_8197F))\n#define BIT_GET_BBPSF_ERRTHR_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_BBPSF_ERRTHR_8197F) & BIT_MASK_BBPSF_ERRTHR_8197F)\n#define BIT_SET_BBPSF_ERRTHR_8197F(x, v)                                       \\\n\t(BIT_CLEAR_BBPSF_ERRTHR_8197F(x) | BIT_BBPSF_ERRTHR_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_P2P_RX_BCN_NOA_8197F (P2P RX BEACON NOA REGISTER) */\n#define BIT_NOA_PARSER_EN_8197F BIT(15)\n\n#define BIT_SHIFT_BSSID_SEL_V1_8197F 12\n#define BIT_MASK_BSSID_SEL_V1_8197F 0x7\n#define BIT_BSSID_SEL_V1_8197F(x)                                              \\\n\t(((x) & BIT_MASK_BSSID_SEL_V1_8197F) << BIT_SHIFT_BSSID_SEL_V1_8197F)\n#define BITS_BSSID_SEL_V1_8197F                                                \\\n\t(BIT_MASK_BSSID_SEL_V1_8197F << BIT_SHIFT_BSSID_SEL_V1_8197F)\n#define BIT_CLEAR_BSSID_SEL_V1_8197F(x) ((x) & (~BITS_BSSID_SEL_V1_8197F))\n#define BIT_GET_BSSID_SEL_V1_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_BSSID_SEL_V1_8197F) & BIT_MASK_BSSID_SEL_V1_8197F)\n#define BIT_SET_BSSID_SEL_V1_8197F(x, v)                                       \\\n\t(BIT_CLEAR_BSSID_SEL_V1_8197F(x) | BIT_BSSID_SEL_V1_8197F(v))\n\n#define BIT_SHIFT_P2P_OUI_TYPE_8197F 0\n#define BIT_MASK_P2P_OUI_TYPE_8197F 0xff\n#define BIT_P2P_OUI_TYPE_8197F(x)                                              \\\n\t(((x) & BIT_MASK_P2P_OUI_TYPE_8197F) << BIT_SHIFT_P2P_OUI_TYPE_8197F)\n#define BITS_P2P_OUI_TYPE_8197F                                                \\\n\t(BIT_MASK_P2P_OUI_TYPE_8197F << BIT_SHIFT_P2P_OUI_TYPE_8197F)\n#define BIT_CLEAR_P2P_OUI_TYPE_8197F(x) ((x) & (~BITS_P2P_OUI_TYPE_8197F))\n#define BIT_GET_P2P_OUI_TYPE_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_P2P_OUI_TYPE_8197F) & BIT_MASK_P2P_OUI_TYPE_8197F)\n#define BIT_SET_P2P_OUI_TYPE_8197F(x, v)                                       \\\n\t(BIT_CLEAR_P2P_OUI_TYPE_8197F(x) | BIT_P2P_OUI_TYPE_8197F(v))\n\n/* 2 REG_ASSOCIATED_BFMER0_INFO_8197F (ASSOCIATED BEAMFORMER0 INFO REGISTER) */\n\n#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F (48 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_WMAC_TXCSI_AID0_8197F 0x1ff\n#define BIT_R_WMAC_TXCSI_AID0_8197F(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8197F)                              \\\n\t << BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F)\n#define BITS_R_WMAC_TXCSI_AID0_8197F                                           \\\n\t(BIT_MASK_R_WMAC_TXCSI_AID0_8197F << BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F)\n#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8197F(x)                                   \\\n\t((x) & (~BITS_R_WMAC_TXCSI_AID0_8197F))\n#define BIT_GET_R_WMAC_TXCSI_AID0_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) &                          \\\n\t BIT_MASK_R_WMAC_TXCSI_AID0_8197F)\n#define BIT_SET_R_WMAC_TXCSI_AID0_8197F(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_TXCSI_AID0_8197F(x) | BIT_R_WMAC_TXCSI_AID0_8197F(v))\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F 0xffffffffffffL\n#define BIT_R_WMAC_SOUNDING_RXADD_R0_8197F(x)                                  \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F)                       \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F)\n#define BITS_R_WMAC_SOUNDING_RXADD_R0_8197F                                    \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F                               \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8197F(x)                            \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_8197F))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8197F(x)                              \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) &                   \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_8197F(x, v)                           \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8197F(x) |                         \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R0_8197F(v))\n\n/* 2 REG_ASSOCIATED_BFMER1_INFO_8197F (ASSOCIATED BEAMFORMER1 INFO REGISTER) */\n\n#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F (48 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_WMAC_TXCSI_AID1_8197F 0x1ff\n#define BIT_R_WMAC_TXCSI_AID1_8197F(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8197F)                              \\\n\t << BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F)\n#define BITS_R_WMAC_TXCSI_AID1_8197F                                           \\\n\t(BIT_MASK_R_WMAC_TXCSI_AID1_8197F << BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F)\n#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8197F(x)                                   \\\n\t((x) & (~BITS_R_WMAC_TXCSI_AID1_8197F))\n#define BIT_GET_R_WMAC_TXCSI_AID1_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) &                          \\\n\t BIT_MASK_R_WMAC_TXCSI_AID1_8197F)\n#define BIT_SET_R_WMAC_TXCSI_AID1_8197F(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_TXCSI_AID1_8197F(x) | BIT_R_WMAC_TXCSI_AID1_8197F(v))\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F 0xffffffffffffL\n#define BIT_R_WMAC_SOUNDING_RXADD_R1_8197F(x)                                  \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F)                       \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F)\n#define BITS_R_WMAC_SOUNDING_RXADD_R1_8197F                                    \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F                               \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8197F(x)                            \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_8197F))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8197F(x)                              \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) &                   \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_8197F(x, v)                           \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8197F(x) |                         \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R1_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_TX_CSI_RPT_PARAM_BW20_8197F (TX CSI REPORT PARAMETER_BW20 REGISTER) */\n\n#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F 16\n#define BIT_MASK_R_WMAC_BFINFO_20M_1_8197F 0xfff\n#define BIT_R_WMAC_BFINFO_20M_1_8197F(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8197F)                            \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F)\n#define BITS_R_WMAC_BFINFO_20M_1_8197F                                         \\\n\t(BIT_MASK_R_WMAC_BFINFO_20M_1_8197F                                    \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F)\n#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8197F(x)                                 \\\n\t((x) & (~BITS_R_WMAC_BFINFO_20M_1_8197F))\n#define BIT_GET_R_WMAC_BFINFO_20M_1_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) &                        \\\n\t BIT_MASK_R_WMAC_BFINFO_20M_1_8197F)\n#define BIT_SET_R_WMAC_BFINFO_20M_1_8197F(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_BFINFO_20M_1_8197F(x) |                              \\\n\t BIT_R_WMAC_BFINFO_20M_1_8197F(v))\n\n#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F 0\n#define BIT_MASK_R_WMAC_BFINFO_20M_0_8197F 0xfff\n#define BIT_R_WMAC_BFINFO_20M_0_8197F(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8197F)                            \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F)\n#define BITS_R_WMAC_BFINFO_20M_0_8197F                                         \\\n\t(BIT_MASK_R_WMAC_BFINFO_20M_0_8197F                                    \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F)\n#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8197F(x)                                 \\\n\t((x) & (~BITS_R_WMAC_BFINFO_20M_0_8197F))\n#define BIT_GET_R_WMAC_BFINFO_20M_0_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) &                        \\\n\t BIT_MASK_R_WMAC_BFINFO_20M_0_8197F)\n#define BIT_SET_R_WMAC_BFINFO_20M_0_8197F(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_BFINFO_20M_0_8197F(x) |                              \\\n\t BIT_R_WMAC_BFINFO_20M_0_8197F(v))\n\n/* 2 REG_TX_CSI_RPT_PARAM_BW40_8197F (TX CSI REPORT PARAMETER_BW40 REGISTER) */\n\n#define BIT_SHIFT_WMAC_RESP_ANTCD_8197F 0\n#define BIT_MASK_WMAC_RESP_ANTCD_8197F 0xf\n#define BIT_WMAC_RESP_ANTCD_8197F(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_RESP_ANTCD_8197F)                                \\\n\t << BIT_SHIFT_WMAC_RESP_ANTCD_8197F)\n#define BITS_WMAC_RESP_ANTCD_8197F                                             \\\n\t(BIT_MASK_WMAC_RESP_ANTCD_8197F << BIT_SHIFT_WMAC_RESP_ANTCD_8197F)\n#define BIT_CLEAR_WMAC_RESP_ANTCD_8197F(x) ((x) & (~BITS_WMAC_RESP_ANTCD_8197F))\n#define BIT_GET_WMAC_RESP_ANTCD_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8197F) &                            \\\n\t BIT_MASK_WMAC_RESP_ANTCD_8197F)\n#define BIT_SET_WMAC_RESP_ANTCD_8197F(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_RESP_ANTCD_8197F(x) | BIT_WMAC_RESP_ANTCD_8197F(v))\n\n/* 2 REG_TX_CSI_RPT_PARAM_BW80_8197F (TX CSI REPORT PARAMETER_BW80 REGISTER) */\n\n/* 2 REG_BCN_PSR_RPT2_8197F (BEACON PARSER REPORT REGISTER2) */\n\n#define BIT_SHIFT_DTIM_CNT2_8197F 24\n#define BIT_MASK_DTIM_CNT2_8197F 0xff\n#define BIT_DTIM_CNT2_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT2_8197F) << BIT_SHIFT_DTIM_CNT2_8197F)\n#define BITS_DTIM_CNT2_8197F                                                   \\\n\t(BIT_MASK_DTIM_CNT2_8197F << BIT_SHIFT_DTIM_CNT2_8197F)\n#define BIT_CLEAR_DTIM_CNT2_8197F(x) ((x) & (~BITS_DTIM_CNT2_8197F))\n#define BIT_GET_DTIM_CNT2_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT2_8197F) & BIT_MASK_DTIM_CNT2_8197F)\n#define BIT_SET_DTIM_CNT2_8197F(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT2_8197F(x) | BIT_DTIM_CNT2_8197F(v))\n\n#define BIT_SHIFT_DTIM_PERIOD2_8197F 16\n#define BIT_MASK_DTIM_PERIOD2_8197F 0xff\n#define BIT_DTIM_PERIOD2_8197F(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD2_8197F) << BIT_SHIFT_DTIM_PERIOD2_8197F)\n#define BITS_DTIM_PERIOD2_8197F                                                \\\n\t(BIT_MASK_DTIM_PERIOD2_8197F << BIT_SHIFT_DTIM_PERIOD2_8197F)\n#define BIT_CLEAR_DTIM_PERIOD2_8197F(x) ((x) & (~BITS_DTIM_PERIOD2_8197F))\n#define BIT_GET_DTIM_PERIOD2_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD2_8197F) & BIT_MASK_DTIM_PERIOD2_8197F)\n#define BIT_SET_DTIM_PERIOD2_8197F(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD2_8197F(x) | BIT_DTIM_PERIOD2_8197F(v))\n\n#define BIT_DTIM2_8197F BIT(15)\n#define BIT_TIM2_8197F BIT(14)\n\n#define BIT_SHIFT_PS_AID_2_8197F 0\n#define BIT_MASK_PS_AID_2_8197F 0x7ff\n#define BIT_PS_AID_2_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_2_8197F) << BIT_SHIFT_PS_AID_2_8197F)\n#define BITS_PS_AID_2_8197F                                                    \\\n\t(BIT_MASK_PS_AID_2_8197F << BIT_SHIFT_PS_AID_2_8197F)\n#define BIT_CLEAR_PS_AID_2_8197F(x) ((x) & (~BITS_PS_AID_2_8197F))\n#define BIT_GET_PS_AID_2_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_2_8197F) & BIT_MASK_PS_AID_2_8197F)\n#define BIT_SET_PS_AID_2_8197F(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_2_8197F(x) | BIT_PS_AID_2_8197F(v))\n\n/* 2 REG_BCN_PSR_RPT3_8197F (BEACON PARSER REPORT REGISTER3) */\n\n#define BIT_SHIFT_DTIM_CNT3_8197F 24\n#define BIT_MASK_DTIM_CNT3_8197F 0xff\n#define BIT_DTIM_CNT3_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT3_8197F) << BIT_SHIFT_DTIM_CNT3_8197F)\n#define BITS_DTIM_CNT3_8197F                                                   \\\n\t(BIT_MASK_DTIM_CNT3_8197F << BIT_SHIFT_DTIM_CNT3_8197F)\n#define BIT_CLEAR_DTIM_CNT3_8197F(x) ((x) & (~BITS_DTIM_CNT3_8197F))\n#define BIT_GET_DTIM_CNT3_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT3_8197F) & BIT_MASK_DTIM_CNT3_8197F)\n#define BIT_SET_DTIM_CNT3_8197F(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT3_8197F(x) | BIT_DTIM_CNT3_8197F(v))\n\n#define BIT_SHIFT_DTIM_PERIOD3_8197F 16\n#define BIT_MASK_DTIM_PERIOD3_8197F 0xff\n#define BIT_DTIM_PERIOD3_8197F(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD3_8197F) << BIT_SHIFT_DTIM_PERIOD3_8197F)\n#define BITS_DTIM_PERIOD3_8197F                                                \\\n\t(BIT_MASK_DTIM_PERIOD3_8197F << BIT_SHIFT_DTIM_PERIOD3_8197F)\n#define BIT_CLEAR_DTIM_PERIOD3_8197F(x) ((x) & (~BITS_DTIM_PERIOD3_8197F))\n#define BIT_GET_DTIM_PERIOD3_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD3_8197F) & BIT_MASK_DTIM_PERIOD3_8197F)\n#define BIT_SET_DTIM_PERIOD3_8197F(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD3_8197F(x) | BIT_DTIM_PERIOD3_8197F(v))\n\n#define BIT_DTIM3_8197F BIT(15)\n#define BIT_TIM3_8197F BIT(14)\n\n#define BIT_SHIFT_PS_AID_3_8197F 0\n#define BIT_MASK_PS_AID_3_8197F 0x7ff\n#define BIT_PS_AID_3_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_3_8197F) << BIT_SHIFT_PS_AID_3_8197F)\n#define BITS_PS_AID_3_8197F                                                    \\\n\t(BIT_MASK_PS_AID_3_8197F << BIT_SHIFT_PS_AID_3_8197F)\n#define BIT_CLEAR_PS_AID_3_8197F(x) ((x) & (~BITS_PS_AID_3_8197F))\n#define BIT_GET_PS_AID_3_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_3_8197F) & BIT_MASK_PS_AID_3_8197F)\n#define BIT_SET_PS_AID_3_8197F(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_3_8197F(x) | BIT_PS_AID_3_8197F(v))\n\n/* 2 REG_BCN_PSR_RPT4_8197F (BEACON PARSER REPORT REGISTER4) */\n\n#define BIT_SHIFT_DTIM_CNT4_8197F 24\n#define BIT_MASK_DTIM_CNT4_8197F 0xff\n#define BIT_DTIM_CNT4_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT4_8197F) << BIT_SHIFT_DTIM_CNT4_8197F)\n#define BITS_DTIM_CNT4_8197F                                                   \\\n\t(BIT_MASK_DTIM_CNT4_8197F << BIT_SHIFT_DTIM_CNT4_8197F)\n#define BIT_CLEAR_DTIM_CNT4_8197F(x) ((x) & (~BITS_DTIM_CNT4_8197F))\n#define BIT_GET_DTIM_CNT4_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT4_8197F) & BIT_MASK_DTIM_CNT4_8197F)\n#define BIT_SET_DTIM_CNT4_8197F(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT4_8197F(x) | BIT_DTIM_CNT4_8197F(v))\n\n#define BIT_SHIFT_DTIM_PERIOD4_8197F 16\n#define BIT_MASK_DTIM_PERIOD4_8197F 0xff\n#define BIT_DTIM_PERIOD4_8197F(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD4_8197F) << BIT_SHIFT_DTIM_PERIOD4_8197F)\n#define BITS_DTIM_PERIOD4_8197F                                                \\\n\t(BIT_MASK_DTIM_PERIOD4_8197F << BIT_SHIFT_DTIM_PERIOD4_8197F)\n#define BIT_CLEAR_DTIM_PERIOD4_8197F(x) ((x) & (~BITS_DTIM_PERIOD4_8197F))\n#define BIT_GET_DTIM_PERIOD4_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD4_8197F) & BIT_MASK_DTIM_PERIOD4_8197F)\n#define BIT_SET_DTIM_PERIOD4_8197F(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD4_8197F(x) | BIT_DTIM_PERIOD4_8197F(v))\n\n#define BIT_DTIM4_8197F BIT(15)\n#define BIT_TIM4_8197F BIT(14)\n\n#define BIT_SHIFT_PS_AID_4_8197F 0\n#define BIT_MASK_PS_AID_4_8197F 0x7ff\n#define BIT_PS_AID_4_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_4_8197F) << BIT_SHIFT_PS_AID_4_8197F)\n#define BITS_PS_AID_4_8197F                                                    \\\n\t(BIT_MASK_PS_AID_4_8197F << BIT_SHIFT_PS_AID_4_8197F)\n#define BIT_CLEAR_PS_AID_4_8197F(x) ((x) & (~BITS_PS_AID_4_8197F))\n#define BIT_GET_PS_AID_4_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_4_8197F) & BIT_MASK_PS_AID_4_8197F)\n#define BIT_SET_PS_AID_4_8197F(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_4_8197F(x) | BIT_PS_AID_4_8197F(v))\n\n/* 2 REG_A1_ADDR_MASK_8197F (A1 ADDR MASK REGISTER) */\n\n#define BIT_SHIFT_A1_ADDR_MASK_8197F 0\n#define BIT_MASK_A1_ADDR_MASK_8197F 0xffffffffL\n#define BIT_A1_ADDR_MASK_8197F(x)                                              \\\n\t(((x) & BIT_MASK_A1_ADDR_MASK_8197F) << BIT_SHIFT_A1_ADDR_MASK_8197F)\n#define BITS_A1_ADDR_MASK_8197F                                                \\\n\t(BIT_MASK_A1_ADDR_MASK_8197F << BIT_SHIFT_A1_ADDR_MASK_8197F)\n#define BIT_CLEAR_A1_ADDR_MASK_8197F(x) ((x) & (~BITS_A1_ADDR_MASK_8197F))\n#define BIT_GET_A1_ADDR_MASK_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_A1_ADDR_MASK_8197F) & BIT_MASK_A1_ADDR_MASK_8197F)\n#define BIT_SET_A1_ADDR_MASK_8197F(x, v)                                       \\\n\t(BIT_CLEAR_A1_ADDR_MASK_8197F(x) | BIT_A1_ADDR_MASK_8197F(v))\n\n/* 2 REG_MACID2_8197F (MAC ID2 REGISTER) */\n\n#define BIT_SHIFT_MACID2_8197F 0\n#define BIT_MASK_MACID2_8197F 0xffffffffffffL\n#define BIT_MACID2_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_MACID2_8197F) << BIT_SHIFT_MACID2_8197F)\n#define BITS_MACID2_8197F (BIT_MASK_MACID2_8197F << BIT_SHIFT_MACID2_8197F)\n#define BIT_CLEAR_MACID2_8197F(x) ((x) & (~BITS_MACID2_8197F))\n#define BIT_GET_MACID2_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_MACID2_8197F) & BIT_MASK_MACID2_8197F)\n#define BIT_SET_MACID2_8197F(x, v)                                             \\\n\t(BIT_CLEAR_MACID2_8197F(x) | BIT_MACID2_8197F(v))\n\n/* 2 REG_BSSID2_8197F (BSSID2 REGISTER) */\n\n#define BIT_SHIFT_BSSID2_8197F 0\n#define BIT_MASK_BSSID2_8197F 0xffffffffffffL\n#define BIT_BSSID2_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_BSSID2_8197F) << BIT_SHIFT_BSSID2_8197F)\n#define BITS_BSSID2_8197F (BIT_MASK_BSSID2_8197F << BIT_SHIFT_BSSID2_8197F)\n#define BIT_CLEAR_BSSID2_8197F(x) ((x) & (~BITS_BSSID2_8197F))\n#define BIT_GET_BSSID2_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_BSSID2_8197F) & BIT_MASK_BSSID2_8197F)\n#define BIT_SET_BSSID2_8197F(x, v)                                             \\\n\t(BIT_CLEAR_BSSID2_8197F(x) | BIT_BSSID2_8197F(v))\n\n/* 2 REG_MACID3_8197F (MAC ID3 REGISTER) */\n\n#define BIT_SHIFT_MACID3_8197F 0\n#define BIT_MASK_MACID3_8197F 0xffffffffffffL\n#define BIT_MACID3_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_MACID3_8197F) << BIT_SHIFT_MACID3_8197F)\n#define BITS_MACID3_8197F (BIT_MASK_MACID3_8197F << BIT_SHIFT_MACID3_8197F)\n#define BIT_CLEAR_MACID3_8197F(x) ((x) & (~BITS_MACID3_8197F))\n#define BIT_GET_MACID3_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_MACID3_8197F) & BIT_MASK_MACID3_8197F)\n#define BIT_SET_MACID3_8197F(x, v)                                             \\\n\t(BIT_CLEAR_MACID3_8197F(x) | BIT_MACID3_8197F(v))\n\n/* 2 REG_BSSID3_8197F (BSSID3 REGISTER) */\n\n#define BIT_SHIFT_BSSID3_8197F 0\n#define BIT_MASK_BSSID3_8197F 0xffffffffffffL\n#define BIT_BSSID3_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_BSSID3_8197F) << BIT_SHIFT_BSSID3_8197F)\n#define BITS_BSSID3_8197F (BIT_MASK_BSSID3_8197F << BIT_SHIFT_BSSID3_8197F)\n#define BIT_CLEAR_BSSID3_8197F(x) ((x) & (~BITS_BSSID3_8197F))\n#define BIT_GET_BSSID3_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_BSSID3_8197F) & BIT_MASK_BSSID3_8197F)\n#define BIT_SET_BSSID3_8197F(x, v)                                             \\\n\t(BIT_CLEAR_BSSID3_8197F(x) | BIT_BSSID3_8197F(v))\n\n/* 2 REG_MACID4_8197F (MAC ID4 REGISTER) */\n\n#define BIT_SHIFT_MACID4_8197F 0\n#define BIT_MASK_MACID4_8197F 0xffffffffffffL\n#define BIT_MACID4_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_MACID4_8197F) << BIT_SHIFT_MACID4_8197F)\n#define BITS_MACID4_8197F (BIT_MASK_MACID4_8197F << BIT_SHIFT_MACID4_8197F)\n#define BIT_CLEAR_MACID4_8197F(x) ((x) & (~BITS_MACID4_8197F))\n#define BIT_GET_MACID4_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_MACID4_8197F) & BIT_MASK_MACID4_8197F)\n#define BIT_SET_MACID4_8197F(x, v)                                             \\\n\t(BIT_CLEAR_MACID4_8197F(x) | BIT_MACID4_8197F(v))\n\n/* 2 REG_BSSID4_8197F (BSSID4 REGISTER) */\n\n#define BIT_SHIFT_BSSID4_8197F 0\n#define BIT_MASK_BSSID4_8197F 0xffffffffffffL\n#define BIT_BSSID4_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_BSSID4_8197F) << BIT_SHIFT_BSSID4_8197F)\n#define BITS_BSSID4_8197F (BIT_MASK_BSSID4_8197F << BIT_SHIFT_BSSID4_8197F)\n#define BIT_CLEAR_BSSID4_8197F(x) ((x) & (~BITS_BSSID4_8197F))\n#define BIT_GET_BSSID4_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_BSSID4_8197F) & BIT_MASK_BSSID4_8197F)\n#define BIT_SET_BSSID4_8197F(x, v)                                             \\\n\t(BIT_CLEAR_BSSID4_8197F(x) | BIT_BSSID4_8197F(v))\n\n/* 2 REG_NOA_REPORT_8197F */\n\n/* 2 REG_PWRBIT_SETTING_8197F */\n#define BIT_CLI3_PWRBIT_OW_EN_8197F BIT(7)\n#define BIT_CLI3_PWR_ST_8197F BIT(6)\n#define BIT_CLI2_PWRBIT_OW_EN_8197F BIT(5)\n#define BIT_CLI2_PWR_ST_8197F BIT(4)\n#define BIT_CLI1_PWRBIT_OW_EN_8197F BIT(3)\n#define BIT_CLI1_PWR_ST_8197F BIT(2)\n#define BIT_CLI0_PWRBIT_OW_EN_8197F BIT(1)\n#define BIT_CLI0_PWR_ST_8197F BIT(0)\n\n/* 2 REG_WMAC_MU_BF_OPTION_8197F */\n#define BIT_WMAC_RESP_NONSTA1_DIS_8197F BIT(7)\n#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN_8197F BIT(6)\n\n#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F 4\n#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F 0x3\n#define BIT_WMAC_TXMU_ACKPOLICY_8197F(x)                                       \\\n\t(((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F)                            \\\n\t << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F)\n#define BITS_WMAC_TXMU_ACKPOLICY_8197F                                         \\\n\t(BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F                                    \\\n\t << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F)\n#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8197F(x)                                 \\\n\t((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8197F))\n#define BIT_GET_WMAC_TXMU_ACKPOLICY_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) &                        \\\n\t BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F)\n#define BIT_SET_WMAC_TXMU_ACKPOLICY_8197F(x, v)                                \\\n\t(BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8197F(x) |                              \\\n\t BIT_WMAC_TXMU_ACKPOLICY_8197F(v))\n\n#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F 1\n#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F 0x7\n#define BIT_WMAC_MU_BFEE_PORT_SEL_8197F(x)                                     \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F)                          \\\n\t << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F)\n#define BITS_WMAC_MU_BFEE_PORT_SEL_8197F                                       \\\n\t(BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F                                  \\\n\t << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F)\n#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8197F(x)                               \\\n\t((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8197F))\n#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8197F(x)                                 \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) &                      \\\n\t BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F)\n#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8197F(x, v)                              \\\n\t(BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8197F(x) |                            \\\n\t BIT_WMAC_MU_BFEE_PORT_SEL_8197F(v))\n\n#define BIT_WMAC_MU_BFEE_DIS_8197F BIT(0)\n\n/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8197F */\n\n#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F 0\n#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F 0xff\n#define BIT_WMAC_PAUSE_BB_CLR_TH_8197F(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F)                           \\\n\t << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F)\n#define BITS_WMAC_PAUSE_BB_CLR_TH_8197F                                        \\\n\t(BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F                                   \\\n\t << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F)\n#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8197F(x)                                \\\n\t((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8197F))\n#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8197F(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) &                       \\\n\t BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F)\n#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8197F(x, v)                               \\\n\t(BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8197F(x) |                             \\\n\t BIT_WMAC_PAUSE_BB_CLR_TH_8197F(v))\n\n/* 2 REG_WMAC_MU_ARB_8197F */\n#define BIT_WMAC_ARB_HW_ADAPT_EN_8197F BIT(7)\n#define BIT_WMAC_ARB_SW_EN_8197F BIT(6)\n\n#define BIT_SHIFT_WMAC_ARB_SW_STATE_8197F 0\n#define BIT_MASK_WMAC_ARB_SW_STATE_8197F 0x3f\n#define BIT_WMAC_ARB_SW_STATE_8197F(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_ARB_SW_STATE_8197F)                              \\\n\t << BIT_SHIFT_WMAC_ARB_SW_STATE_8197F)\n#define BITS_WMAC_ARB_SW_STATE_8197F                                           \\\n\t(BIT_MASK_WMAC_ARB_SW_STATE_8197F << BIT_SHIFT_WMAC_ARB_SW_STATE_8197F)\n#define BIT_CLEAR_WMAC_ARB_SW_STATE_8197F(x)                                   \\\n\t((x) & (~BITS_WMAC_ARB_SW_STATE_8197F))\n#define BIT_GET_WMAC_ARB_SW_STATE_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) &                          \\\n\t BIT_MASK_WMAC_ARB_SW_STATE_8197F)\n#define BIT_SET_WMAC_ARB_SW_STATE_8197F(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_ARB_SW_STATE_8197F(x) | BIT_WMAC_ARB_SW_STATE_8197F(v))\n\n/* 2 REG_WMAC_MU_OPTION_8197F */\n\n#define BIT_SHIFT_WMAC_MU_DBGSEL_8197F 5\n#define BIT_MASK_WMAC_MU_DBGSEL_8197F 0x3\n#define BIT_WMAC_MU_DBGSEL_8197F(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_MU_DBGSEL_8197F)                                 \\\n\t << BIT_SHIFT_WMAC_MU_DBGSEL_8197F)\n#define BITS_WMAC_MU_DBGSEL_8197F                                              \\\n\t(BIT_MASK_WMAC_MU_DBGSEL_8197F << BIT_SHIFT_WMAC_MU_DBGSEL_8197F)\n#define BIT_CLEAR_WMAC_MU_DBGSEL_8197F(x) ((x) & (~BITS_WMAC_MU_DBGSEL_8197F))\n#define BIT_GET_WMAC_MU_DBGSEL_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8197F) &                             \\\n\t BIT_MASK_WMAC_MU_DBGSEL_8197F)\n#define BIT_SET_WMAC_MU_DBGSEL_8197F(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_MU_DBGSEL_8197F(x) | BIT_WMAC_MU_DBGSEL_8197F(v))\n\n#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F 0\n#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F 0x1f\n#define BIT_WMAC_MU_CPRD_TIMEOUT_8197F(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F)                           \\\n\t << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F)\n#define BITS_WMAC_MU_CPRD_TIMEOUT_8197F                                        \\\n\t(BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F                                   \\\n\t << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F)\n#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8197F(x)                                \\\n\t((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8197F))\n#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8197F(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) &                       \\\n\t BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F)\n#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8197F(x, v)                               \\\n\t(BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8197F(x) |                             \\\n\t BIT_WMAC_MU_CPRD_TIMEOUT_8197F(v))\n\n/* 2 REG_WMAC_MU_BF_CTL_8197F */\n#define BIT_WMAC_INVLD_BFPRT_CHK_8197F BIT(15)\n#define BIT_WMAC_RETXBFRPTSEQ_UPD_8197F BIT(14)\n\n#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F 12\n#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F 0x3\n#define BIT_WMAC_MU_BFRPTSEG_SEL_8197F(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F)                           \\\n\t << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F)\n#define BITS_WMAC_MU_BFRPTSEG_SEL_8197F                                        \\\n\t(BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F                                   \\\n\t << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F)\n#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8197F(x)                                \\\n\t((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8197F))\n#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8197F(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) &                       \\\n\t BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F)\n#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8197F(x, v)                               \\\n\t(BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8197F(x) |                             \\\n\t BIT_WMAC_MU_BFRPTSEG_SEL_8197F(v))\n\n#define BIT_SHIFT_WMAC_MU_BF_MYAID_8197F 0\n#define BIT_MASK_WMAC_MU_BF_MYAID_8197F 0xfff\n#define BIT_WMAC_MU_BF_MYAID_8197F(x)                                          \\\n\t(((x) & BIT_MASK_WMAC_MU_BF_MYAID_8197F)                               \\\n\t << BIT_SHIFT_WMAC_MU_BF_MYAID_8197F)\n#define BITS_WMAC_MU_BF_MYAID_8197F                                            \\\n\t(BIT_MASK_WMAC_MU_BF_MYAID_8197F << BIT_SHIFT_WMAC_MU_BF_MYAID_8197F)\n#define BIT_CLEAR_WMAC_MU_BF_MYAID_8197F(x)                                    \\\n\t((x) & (~BITS_WMAC_MU_BF_MYAID_8197F))\n#define BIT_GET_WMAC_MU_BF_MYAID_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) &                           \\\n\t BIT_MASK_WMAC_MU_BF_MYAID_8197F)\n#define BIT_SET_WMAC_MU_BF_MYAID_8197F(x, v)                                   \\\n\t(BIT_CLEAR_WMAC_MU_BF_MYAID_8197F(x) | BIT_WMAC_MU_BF_MYAID_8197F(v))\n\n/* 2 REG_WMAC_MU_BFRPT_PARA_8197F */\n\n#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F 12\n#define BIT_MASK_BFRPT_PARA_USERID_SEL_8197F 0x7\n#define BIT_BFRPT_PARA_USERID_SEL_8197F(x)                                     \\\n\t(((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8197F)                          \\\n\t << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F)\n#define BITS_BFRPT_PARA_USERID_SEL_8197F                                       \\\n\t(BIT_MASK_BFRPT_PARA_USERID_SEL_8197F                                  \\\n\t << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F)\n#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_8197F(x)                               \\\n\t((x) & (~BITS_BFRPT_PARA_USERID_SEL_8197F))\n#define BIT_GET_BFRPT_PARA_USERID_SEL_8197F(x)                                 \\\n\t(((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) &                      \\\n\t BIT_MASK_BFRPT_PARA_USERID_SEL_8197F)\n#define BIT_SET_BFRPT_PARA_USERID_SEL_8197F(x, v)                              \\\n\t(BIT_CLEAR_BFRPT_PARA_USERID_SEL_8197F(x) |                            \\\n\t BIT_BFRPT_PARA_USERID_SEL_8197F(v))\n\n#define BIT_SHIFT_BFRPT_PARA_8197F 0\n#define BIT_MASK_BFRPT_PARA_8197F 0xfff\n#define BIT_BFRPT_PARA_8197F(x)                                                \\\n\t(((x) & BIT_MASK_BFRPT_PARA_8197F) << BIT_SHIFT_BFRPT_PARA_8197F)\n#define BITS_BFRPT_PARA_8197F                                                  \\\n\t(BIT_MASK_BFRPT_PARA_8197F << BIT_SHIFT_BFRPT_PARA_8197F)\n#define BIT_CLEAR_BFRPT_PARA_8197F(x) ((x) & (~BITS_BFRPT_PARA_8197F))\n#define BIT_GET_BFRPT_PARA_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_BFRPT_PARA_8197F) & BIT_MASK_BFRPT_PARA_8197F)\n#define BIT_SET_BFRPT_PARA_8197F(x, v)                                         \\\n\t(BIT_CLEAR_BFRPT_PARA_8197F(x) | BIT_BFRPT_PARA_8197F(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8197F */\n#define BIT_STATUS_BFEE2_8197F BIT(10)\n#define BIT_WMAC_MU_BFEE2_EN_8197F BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F 0\n#define BIT_MASK_WMAC_MU_BFEE2_AID_8197F 0x1ff\n#define BIT_WMAC_MU_BFEE2_AID_8197F(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8197F)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F)\n#define BITS_WMAC_MU_BFEE2_AID_8197F                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE2_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F)\n#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8197F(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE2_AID_8197F))\n#define BIT_GET_WMAC_MU_BFEE2_AID_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE2_AID_8197F)\n#define BIT_SET_WMAC_MU_BFEE2_AID_8197F(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE2_AID_8197F(x) | BIT_WMAC_MU_BFEE2_AID_8197F(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8197F */\n#define BIT_STATUS_BFEE3_8197F BIT(10)\n#define BIT_WMAC_MU_BFEE3_EN_8197F BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F 0\n#define BIT_MASK_WMAC_MU_BFEE3_AID_8197F 0x1ff\n#define BIT_WMAC_MU_BFEE3_AID_8197F(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8197F)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F)\n#define BITS_WMAC_MU_BFEE3_AID_8197F                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE3_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F)\n#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8197F(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE3_AID_8197F))\n#define BIT_GET_WMAC_MU_BFEE3_AID_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE3_AID_8197F)\n#define BIT_SET_WMAC_MU_BFEE3_AID_8197F(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE3_AID_8197F(x) | BIT_WMAC_MU_BFEE3_AID_8197F(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8197F */\n#define BIT_STATUS_BFEE4_8197F BIT(10)\n#define BIT_WMAC_MU_BFEE4_EN_8197F BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F 0\n#define BIT_MASK_WMAC_MU_BFEE4_AID_8197F 0x1ff\n#define BIT_WMAC_MU_BFEE4_AID_8197F(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8197F)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F)\n#define BITS_WMAC_MU_BFEE4_AID_8197F                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE4_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F)\n#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8197F(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE4_AID_8197F))\n#define BIT_GET_WMAC_MU_BFEE4_AID_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE4_AID_8197F)\n#define BIT_SET_WMAC_MU_BFEE4_AID_8197F(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE4_AID_8197F(x) | BIT_WMAC_MU_BFEE4_AID_8197F(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8197F */\n#define BIT_STATUS_BFEE5_8197F BIT(10)\n#define BIT_WMAC_MU_BFEE5_EN_8197F BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F 0\n#define BIT_MASK_WMAC_MU_BFEE5_AID_8197F 0x1ff\n#define BIT_WMAC_MU_BFEE5_AID_8197F(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8197F)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F)\n#define BITS_WMAC_MU_BFEE5_AID_8197F                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE5_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F)\n#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8197F(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE5_AID_8197F))\n#define BIT_GET_WMAC_MU_BFEE5_AID_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE5_AID_8197F)\n#define BIT_SET_WMAC_MU_BFEE5_AID_8197F(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE5_AID_8197F(x) | BIT_WMAC_MU_BFEE5_AID_8197F(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8197F */\n#define BIT_STATUS_BFEE6_8197F BIT(10)\n#define BIT_WMAC_MU_BFEE6_EN_8197F BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F 0\n#define BIT_MASK_WMAC_MU_BFEE6_AID_8197F 0x1ff\n#define BIT_WMAC_MU_BFEE6_AID_8197F(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8197F)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F)\n#define BITS_WMAC_MU_BFEE6_AID_8197F                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE6_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F)\n#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8197F(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE6_AID_8197F))\n#define BIT_GET_WMAC_MU_BFEE6_AID_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE6_AID_8197F)\n#define BIT_SET_WMAC_MU_BFEE6_AID_8197F(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE6_AID_8197F(x) | BIT_WMAC_MU_BFEE6_AID_8197F(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8197F */\n#define BIT_BIT_STATUS_BFEE4_8197F BIT(10)\n#define BIT_WMAC_MU_BFEE7_EN_8197F BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F 0\n#define BIT_MASK_WMAC_MU_BFEE7_AID_8197F 0x1ff\n#define BIT_WMAC_MU_BFEE7_AID_8197F(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8197F)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F)\n#define BITS_WMAC_MU_BFEE7_AID_8197F                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE7_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F)\n#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8197F(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE7_AID_8197F))\n#define BIT_GET_WMAC_MU_BFEE7_AID_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE7_AID_8197F)\n#define BIT_SET_WMAC_MU_BFEE7_AID_8197F(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE7_AID_8197F(x) | BIT_WMAC_MU_BFEE7_AID_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n#define BIT_RST_ALL_COUNTER_8197F BIT(31)\n\n#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F 16\n#define BIT_MASK_ABORT_RX_VBON_COUNTER_8197F 0xff\n#define BIT_ABORT_RX_VBON_COUNTER_8197F(x)                                     \\\n\t(((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8197F)                          \\\n\t << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F)\n#define BITS_ABORT_RX_VBON_COUNTER_8197F                                       \\\n\t(BIT_MASK_ABORT_RX_VBON_COUNTER_8197F                                  \\\n\t << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F)\n#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8197F(x)                               \\\n\t((x) & (~BITS_ABORT_RX_VBON_COUNTER_8197F))\n#define BIT_GET_ABORT_RX_VBON_COUNTER_8197F(x)                                 \\\n\t(((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) &                      \\\n\t BIT_MASK_ABORT_RX_VBON_COUNTER_8197F)\n#define BIT_SET_ABORT_RX_VBON_COUNTER_8197F(x, v)                              \\\n\t(BIT_CLEAR_ABORT_RX_VBON_COUNTER_8197F(x) |                            \\\n\t BIT_ABORT_RX_VBON_COUNTER_8197F(v))\n\n#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F 8\n#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F 0xff\n#define BIT_ABORT_RX_RDRDY_COUNTER_8197F(x)                                    \\\n\t(((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F)                         \\\n\t << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F)\n#define BITS_ABORT_RX_RDRDY_COUNTER_8197F                                      \\\n\t(BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F                                 \\\n\t << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F)\n#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8197F(x)                              \\\n\t((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8197F))\n#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8197F(x)                                \\\n\t(((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) &                     \\\n\t BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F)\n#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8197F(x, v)                             \\\n\t(BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8197F(x) |                           \\\n\t BIT_ABORT_RX_RDRDY_COUNTER_8197F(v))\n\n#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F 0\n#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F 0xff\n#define BIT_VBON_EARLY_FALLING_COUNTER_8197F(x)                                \\\n\t(((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F)                     \\\n\t << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F)\n#define BITS_VBON_EARLY_FALLING_COUNTER_8197F                                  \\\n\t(BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F                             \\\n\t << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F)\n#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8197F(x)                          \\\n\t((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8197F))\n#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8197F(x)                            \\\n\t(((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) &                 \\\n\t BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F)\n#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8197F(x, v)                         \\\n\t(BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8197F(x) |                       \\\n\t BIT_VBON_EARLY_FALLING_COUNTER_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n#define BIT_WMAC_PLCP_TRX_SEL_8197F BIT(31)\n\n#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F 28\n#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F 0x7\n#define BIT_WMAC_PLCP_RDSIG_SEL_8197F(x)                                       \\\n\t(((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F)                            \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F)\n#define BITS_WMAC_PLCP_RDSIG_SEL_8197F                                         \\\n\t(BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F                                    \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F)\n#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8197F(x)                                 \\\n\t((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8197F))\n#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) &                        \\\n\t BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F)\n#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8197F(x, v)                                \\\n\t(BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8197F(x) |                              \\\n\t BIT_WMAC_PLCP_RDSIG_SEL_8197F(v))\n\n#define BIT_SHIFT_WMAC_RATE_IDX_8197F 24\n#define BIT_MASK_WMAC_RATE_IDX_8197F 0xf\n#define BIT_WMAC_RATE_IDX_8197F(x)                                             \\\n\t(((x) & BIT_MASK_WMAC_RATE_IDX_8197F) << BIT_SHIFT_WMAC_RATE_IDX_8197F)\n#define BITS_WMAC_RATE_IDX_8197F                                               \\\n\t(BIT_MASK_WMAC_RATE_IDX_8197F << BIT_SHIFT_WMAC_RATE_IDX_8197F)\n#define BIT_CLEAR_WMAC_RATE_IDX_8197F(x) ((x) & (~BITS_WMAC_RATE_IDX_8197F))\n#define BIT_GET_WMAC_RATE_IDX_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_WMAC_RATE_IDX_8197F) & BIT_MASK_WMAC_RATE_IDX_8197F)\n#define BIT_SET_WMAC_RATE_IDX_8197F(x, v)                                      \\\n\t(BIT_CLEAR_WMAC_RATE_IDX_8197F(x) | BIT_WMAC_RATE_IDX_8197F(v))\n\n#define BIT_SHIFT_WMAC_PLCP_RDSIG_8197F 0\n#define BIT_MASK_WMAC_PLCP_RDSIG_8197F 0xffffff\n#define BIT_WMAC_PLCP_RDSIG_8197F(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_PLCP_RDSIG_8197F)                                \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_8197F)\n#define BITS_WMAC_PLCP_RDSIG_8197F                                             \\\n\t(BIT_MASK_WMAC_PLCP_RDSIG_8197F << BIT_SHIFT_WMAC_PLCP_RDSIG_8197F)\n#define BIT_CLEAR_WMAC_PLCP_RDSIG_8197F(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8197F))\n#define BIT_GET_WMAC_PLCP_RDSIG_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) &                            \\\n\t BIT_MASK_WMAC_PLCP_RDSIG_8197F)\n#define BIT_SET_WMAC_PLCP_RDSIG_8197F(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_PLCP_RDSIG_8197F(x) | BIT_WMAC_PLCP_RDSIG_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_TRANSMIT_ADDRSS_0_8197F (TA0 REGISTER) */\n\n#define BIT_SHIFT_TA0_8197F 0\n#define BIT_MASK_TA0_8197F 0xffffffffffffL\n#define BIT_TA0_8197F(x) (((x) & BIT_MASK_TA0_8197F) << BIT_SHIFT_TA0_8197F)\n#define BITS_TA0_8197F (BIT_MASK_TA0_8197F << BIT_SHIFT_TA0_8197F)\n#define BIT_CLEAR_TA0_8197F(x) ((x) & (~BITS_TA0_8197F))\n#define BIT_GET_TA0_8197F(x) (((x) >> BIT_SHIFT_TA0_8197F) & BIT_MASK_TA0_8197F)\n#define BIT_SET_TA0_8197F(x, v) (BIT_CLEAR_TA0_8197F(x) | BIT_TA0_8197F(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_1_8197F (TA1 REGISTER) */\n\n#define BIT_SHIFT_TA1_8197F 0\n#define BIT_MASK_TA1_8197F 0xffffffffffffL\n#define BIT_TA1_8197F(x) (((x) & BIT_MASK_TA1_8197F) << BIT_SHIFT_TA1_8197F)\n#define BITS_TA1_8197F (BIT_MASK_TA1_8197F << BIT_SHIFT_TA1_8197F)\n#define BIT_CLEAR_TA1_8197F(x) ((x) & (~BITS_TA1_8197F))\n#define BIT_GET_TA1_8197F(x) (((x) >> BIT_SHIFT_TA1_8197F) & BIT_MASK_TA1_8197F)\n#define BIT_SET_TA1_8197F(x, v) (BIT_CLEAR_TA1_8197F(x) | BIT_TA1_8197F(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_2_8197F (TA2 REGISTER) */\n\n#define BIT_SHIFT_TA2_8197F 0\n#define BIT_MASK_TA2_8197F 0xffffffffffffL\n#define BIT_TA2_8197F(x) (((x) & BIT_MASK_TA2_8197F) << BIT_SHIFT_TA2_8197F)\n#define BITS_TA2_8197F (BIT_MASK_TA2_8197F << BIT_SHIFT_TA2_8197F)\n#define BIT_CLEAR_TA2_8197F(x) ((x) & (~BITS_TA2_8197F))\n#define BIT_GET_TA2_8197F(x) (((x) >> BIT_SHIFT_TA2_8197F) & BIT_MASK_TA2_8197F)\n#define BIT_SET_TA2_8197F(x, v) (BIT_CLEAR_TA2_8197F(x) | BIT_TA2_8197F(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_3_8197F (TA3 REGISTER) */\n\n#define BIT_SHIFT_TA3_8197F 0\n#define BIT_MASK_TA3_8197F 0xffffffffffffL\n#define BIT_TA3_8197F(x) (((x) & BIT_MASK_TA3_8197F) << BIT_SHIFT_TA3_8197F)\n#define BITS_TA3_8197F (BIT_MASK_TA3_8197F << BIT_SHIFT_TA3_8197F)\n#define BIT_CLEAR_TA3_8197F(x) ((x) & (~BITS_TA3_8197F))\n#define BIT_GET_TA3_8197F(x) (((x) >> BIT_SHIFT_TA3_8197F) & BIT_MASK_TA3_8197F)\n#define BIT_SET_TA3_8197F(x, v) (BIT_CLEAR_TA3_8197F(x) | BIT_TA3_8197F(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_4_8197F (TA4 REGISTER) */\n\n#define BIT_SHIFT_TA4_8197F 0\n#define BIT_MASK_TA4_8197F 0xffffffffffffL\n#define BIT_TA4_8197F(x) (((x) & BIT_MASK_TA4_8197F) << BIT_SHIFT_TA4_8197F)\n#define BITS_TA4_8197F (BIT_MASK_TA4_8197F << BIT_SHIFT_TA4_8197F)\n#define BIT_CLEAR_TA4_8197F(x) ((x) & (~BITS_TA4_8197F))\n#define BIT_GET_TA4_8197F(x) (((x) >> BIT_SHIFT_TA4_8197F) & BIT_MASK_TA4_8197F)\n#define BIT_SET_TA4_8197F(x, v) (BIT_CLEAR_TA4_8197F(x) | BIT_TA4_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_MACID1_8197F */\n\n#define BIT_SHIFT_MACID1_8197F 0\n#define BIT_MASK_MACID1_8197F 0xffffffffffffL\n#define BIT_MACID1_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_MACID1_8197F) << BIT_SHIFT_MACID1_8197F)\n#define BITS_MACID1_8197F (BIT_MASK_MACID1_8197F << BIT_SHIFT_MACID1_8197F)\n#define BIT_CLEAR_MACID1_8197F(x) ((x) & (~BITS_MACID1_8197F))\n#define BIT_GET_MACID1_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_MACID1_8197F) & BIT_MASK_MACID1_8197F)\n#define BIT_SET_MACID1_8197F(x, v)                                             \\\n\t(BIT_CLEAR_MACID1_8197F(x) | BIT_MACID1_8197F(v))\n\n/* 2 REG_BSSID1_8197F */\n\n#define BIT_SHIFT_BSSID1_8197F 0\n#define BIT_MASK_BSSID1_8197F 0xffffffffffffL\n#define BIT_BSSID1_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_BSSID1_8197F) << BIT_SHIFT_BSSID1_8197F)\n#define BITS_BSSID1_8197F (BIT_MASK_BSSID1_8197F << BIT_SHIFT_BSSID1_8197F)\n#define BIT_CLEAR_BSSID1_8197F(x) ((x) & (~BITS_BSSID1_8197F))\n#define BIT_GET_BSSID1_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_BSSID1_8197F) & BIT_MASK_BSSID1_8197F)\n#define BIT_SET_BSSID1_8197F(x, v)                                             \\\n\t(BIT_CLEAR_BSSID1_8197F(x) | BIT_BSSID1_8197F(v))\n\n/* 2 REG_BCN_PSR_RPT1_8197F */\n\n#define BIT_SHIFT_DTIM_CNT1_8197F 24\n#define BIT_MASK_DTIM_CNT1_8197F 0xff\n#define BIT_DTIM_CNT1_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT1_8197F) << BIT_SHIFT_DTIM_CNT1_8197F)\n#define BITS_DTIM_CNT1_8197F                                                   \\\n\t(BIT_MASK_DTIM_CNT1_8197F << BIT_SHIFT_DTIM_CNT1_8197F)\n#define BIT_CLEAR_DTIM_CNT1_8197F(x) ((x) & (~BITS_DTIM_CNT1_8197F))\n#define BIT_GET_DTIM_CNT1_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT1_8197F) & BIT_MASK_DTIM_CNT1_8197F)\n#define BIT_SET_DTIM_CNT1_8197F(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT1_8197F(x) | BIT_DTIM_CNT1_8197F(v))\n\n#define BIT_SHIFT_DTIM_PERIOD1_8197F 16\n#define BIT_MASK_DTIM_PERIOD1_8197F 0xff\n#define BIT_DTIM_PERIOD1_8197F(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD1_8197F) << BIT_SHIFT_DTIM_PERIOD1_8197F)\n#define BITS_DTIM_PERIOD1_8197F                                                \\\n\t(BIT_MASK_DTIM_PERIOD1_8197F << BIT_SHIFT_DTIM_PERIOD1_8197F)\n#define BIT_CLEAR_DTIM_PERIOD1_8197F(x) ((x) & (~BITS_DTIM_PERIOD1_8197F))\n#define BIT_GET_DTIM_PERIOD1_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD1_8197F) & BIT_MASK_DTIM_PERIOD1_8197F)\n#define BIT_SET_DTIM_PERIOD1_8197F(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD1_8197F(x) | BIT_DTIM_PERIOD1_8197F(v))\n\n#define BIT_DTIM1_8197F BIT(15)\n#define BIT_TIM1_8197F BIT(14)\n\n#define BIT_SHIFT_PS_AID_1_8197F 0\n#define BIT_MASK_PS_AID_1_8197F 0x7ff\n#define BIT_PS_AID_1_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_1_8197F) << BIT_SHIFT_PS_AID_1_8197F)\n#define BITS_PS_AID_1_8197F                                                    \\\n\t(BIT_MASK_PS_AID_1_8197F << BIT_SHIFT_PS_AID_1_8197F)\n#define BIT_CLEAR_PS_AID_1_8197F(x) ((x) & (~BITS_PS_AID_1_8197F))\n#define BIT_GET_PS_AID_1_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_1_8197F) & BIT_MASK_PS_AID_1_8197F)\n#define BIT_SET_PS_AID_1_8197F(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_1_8197F(x) | BIT_PS_AID_1_8197F(v))\n\n/* 2 REG_ASSOCIATED_BFMEE_SEL_8197F */\n#define BIT_TXUSER_ID1_8197F BIT(25)\n\n#define BIT_SHIFT_AID1_8197F 16\n#define BIT_MASK_AID1_8197F 0x1ff\n#define BIT_AID1_8197F(x) (((x) & BIT_MASK_AID1_8197F) << BIT_SHIFT_AID1_8197F)\n#define BITS_AID1_8197F (BIT_MASK_AID1_8197F << BIT_SHIFT_AID1_8197F)\n#define BIT_CLEAR_AID1_8197F(x) ((x) & (~BITS_AID1_8197F))\n#define BIT_GET_AID1_8197F(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AID1_8197F) & BIT_MASK_AID1_8197F)\n#define BIT_SET_AID1_8197F(x, v) (BIT_CLEAR_AID1_8197F(x) | BIT_AID1_8197F(v))\n\n#define BIT_TXUSER_ID0_8197F BIT(9)\n\n#define BIT_SHIFT_AID0_8197F 0\n#define BIT_MASK_AID0_8197F 0x1ff\n#define BIT_AID0_8197F(x) (((x) & BIT_MASK_AID0_8197F) << BIT_SHIFT_AID0_8197F)\n#define BITS_AID0_8197F (BIT_MASK_AID0_8197F << BIT_SHIFT_AID0_8197F)\n#define BIT_CLEAR_AID0_8197F(x) ((x) & (~BITS_AID0_8197F))\n#define BIT_GET_AID0_8197F(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AID0_8197F) & BIT_MASK_AID0_8197F)\n#define BIT_SET_AID0_8197F(x, v) (BIT_CLEAR_AID0_8197F(x) | BIT_AID0_8197F(v))\n\n/* 2 REG_SND_PTCL_CTRL_8197F */\n\n#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F 24\n#define BIT_MASK_NDP_RX_STANDBY_TIMER_8197F 0xff\n#define BIT_NDP_RX_STANDBY_TIMER_8197F(x)                                      \\\n\t(((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8197F)                           \\\n\t << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F)\n#define BITS_NDP_RX_STANDBY_TIMER_8197F                                        \\\n\t(BIT_MASK_NDP_RX_STANDBY_TIMER_8197F                                   \\\n\t << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F)\n#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8197F(x)                                \\\n\t((x) & (~BITS_NDP_RX_STANDBY_TIMER_8197F))\n#define BIT_GET_NDP_RX_STANDBY_TIMER_8197F(x)                                  \\\n\t(((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) &                       \\\n\t BIT_MASK_NDP_RX_STANDBY_TIMER_8197F)\n#define BIT_SET_NDP_RX_STANDBY_TIMER_8197F(x, v)                               \\\n\t(BIT_CLEAR_NDP_RX_STANDBY_TIMER_8197F(x) |                             \\\n\t BIT_NDP_RX_STANDBY_TIMER_8197F(v))\n\n#define BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F 16\n#define BIT_MASK_CSI_RPT_OFFSET_HT_8197F 0xff\n#define BIT_CSI_RPT_OFFSET_HT_8197F(x)                                         \\\n\t(((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8197F)                              \\\n\t << BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F)\n#define BITS_CSI_RPT_OFFSET_HT_8197F                                           \\\n\t(BIT_MASK_CSI_RPT_OFFSET_HT_8197F << BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F)\n#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8197F(x)                                   \\\n\t((x) & (~BITS_CSI_RPT_OFFSET_HT_8197F))\n#define BIT_GET_CSI_RPT_OFFSET_HT_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) &                          \\\n\t BIT_MASK_CSI_RPT_OFFSET_HT_8197F)\n#define BIT_SET_CSI_RPT_OFFSET_HT_8197F(x, v)                                  \\\n\t(BIT_CLEAR_CSI_RPT_OFFSET_HT_8197F(x) | BIT_CSI_RPT_OFFSET_HT_8197F(v))\n\n#define BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F 8\n#define BIT_MASK_CSI_RPT_OFFSET_VHT_8197F 0xff\n#define BIT_CSI_RPT_OFFSET_VHT_8197F(x)                                        \\\n\t(((x) & BIT_MASK_CSI_RPT_OFFSET_VHT_8197F)                             \\\n\t << BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F)\n#define BITS_CSI_RPT_OFFSET_VHT_8197F                                          \\\n\t(BIT_MASK_CSI_RPT_OFFSET_VHT_8197F                                     \\\n\t << BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F)\n#define BIT_CLEAR_CSI_RPT_OFFSET_VHT_8197F(x)                                  \\\n\t((x) & (~BITS_CSI_RPT_OFFSET_VHT_8197F))\n#define BIT_GET_CSI_RPT_OFFSET_VHT_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) &                         \\\n\t BIT_MASK_CSI_RPT_OFFSET_VHT_8197F)\n#define BIT_SET_CSI_RPT_OFFSET_VHT_8197F(x, v)                                 \\\n\t(BIT_CLEAR_CSI_RPT_OFFSET_VHT_8197F(x) |                               \\\n\t BIT_CSI_RPT_OFFSET_VHT_8197F(v))\n\n#define BIT_R_WMAC_USE_NSTS_8197F BIT(7)\n#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8197F BIT(6)\n#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8197F BIT(5)\n#define BIT_R_WMAC_BFPARAM_SEL_8197F BIT(4)\n#define BIT_R_WMAC_CSISEQ_SEL_8197F BIT(3)\n#define BIT_R_WMAC_CSI_WITHHTC_EN_8197F BIT(2)\n#define BIT_R_WMAC_HT_NDPA_EN_8197F BIT(1)\n#define BIT_R_WMAC_VHT_NDPA_EN_8197F BIT(0)\n\n/* 2 REG_RX_CSI_RPT_INFO_8197F */\n\n/* 2 REG_NS_ARP_CTRL_8197F */\n#define BIT_R_WMAC_NSARP_RSPEN_8197F BIT(15)\n#define BIT_R_WMAC_NSARP_RARP_8197F BIT(9)\n#define BIT_R_WMAC_NSARP_RIPV6_8197F BIT(8)\n\n#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F 6\n#define BIT_MASK_R_WMAC_NSARP_MODEN_8197F 0x3\n#define BIT_R_WMAC_NSARP_MODEN_8197F(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8197F)                             \\\n\t << BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F)\n#define BITS_R_WMAC_NSARP_MODEN_8197F                                          \\\n\t(BIT_MASK_R_WMAC_NSARP_MODEN_8197F                                     \\\n\t << BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F)\n#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8197F(x)                                  \\\n\t((x) & (~BITS_R_WMAC_NSARP_MODEN_8197F))\n#define BIT_GET_R_WMAC_NSARP_MODEN_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) &                         \\\n\t BIT_MASK_R_WMAC_NSARP_MODEN_8197F)\n#define BIT_SET_R_WMAC_NSARP_MODEN_8197F(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_NSARP_MODEN_8197F(x) |                               \\\n\t BIT_R_WMAC_NSARP_MODEN_8197F(v))\n\n#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F 4\n#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F 0x3\n#define BIT_R_WMAC_NSARP_RSPFTP_8197F(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F)                            \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F)\n#define BITS_R_WMAC_NSARP_RSPFTP_8197F                                         \\\n\t(BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F                                    \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F)\n#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8197F(x)                                 \\\n\t((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8197F))\n#define BIT_GET_R_WMAC_NSARP_RSPFTP_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) &                        \\\n\t BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F)\n#define BIT_SET_R_WMAC_NSARP_RSPFTP_8197F(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8197F(x) |                              \\\n\t BIT_R_WMAC_NSARP_RSPFTP_8197F(v))\n\n#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F 0\n#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F 0xf\n#define BIT_R_WMAC_NSARP_RSPSEC_8197F(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F)                            \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F)\n#define BITS_R_WMAC_NSARP_RSPSEC_8197F                                         \\\n\t(BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F                                    \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F)\n#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8197F(x)                                 \\\n\t((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8197F))\n#define BIT_GET_R_WMAC_NSARP_RSPSEC_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) &                        \\\n\t BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F)\n#define BIT_SET_R_WMAC_NSARP_RSPSEC_8197F(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8197F(x) |                              \\\n\t BIT_R_WMAC_NSARP_RSPSEC_8197F(v))\n\n/* 2 REG_NS_ARP_INFO_8197F */\n\n/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8197F */\n\n/* 2 REG_BEAMFORMING_INFO_NSARP_8197F */\n\n/* 2 REG_NOT_VALID_8197F */\n\n/* 2 REG_RSVD_0X740_8197F */\n\n/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8197F */\n\n#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F 4\n#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F 0xf\n#define BIT_R_WMAC_CTX_SUBTYPE_8197F(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F)                             \\\n\t << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F)\n#define BITS_R_WMAC_CTX_SUBTYPE_8197F                                          \\\n\t(BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F                                     \\\n\t << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F)\n#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8197F(x)                                  \\\n\t((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8197F))\n#define BIT_GET_R_WMAC_CTX_SUBTYPE_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) &                         \\\n\t BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F)\n#define BIT_SET_R_WMAC_CTX_SUBTYPE_8197F(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8197F(x) |                               \\\n\t BIT_R_WMAC_CTX_SUBTYPE_8197F(v))\n\n#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F 0\n#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F 0xf\n#define BIT_R_WMAC_RTX_SUBTYPE_8197F(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F)                             \\\n\t << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F)\n#define BITS_R_WMAC_RTX_SUBTYPE_8197F                                          \\\n\t(BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F                                     \\\n\t << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F)\n#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8197F(x)                                  \\\n\t((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8197F))\n#define BIT_GET_R_WMAC_RTX_SUBTYPE_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) &                         \\\n\t BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F)\n#define BIT_SET_R_WMAC_RTX_SUBTYPE_8197F(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8197F(x) |                               \\\n\t BIT_R_WMAC_RTX_SUBTYPE_8197F(v))\n\n/* 2 REG_WMAC_SWAES_CFG_8197F */\n\n/* 2 REG_BT_COEX_V2_8197F */\n#define BIT_GNT_BT_POLARITY_8197F BIT(12)\n#define BIT_GNT_BT_BYPASS_PRIORITY_8197F BIT(8)\n\n#define BIT_SHIFT_TIMER_8197F 0\n#define BIT_MASK_TIMER_8197F 0xff\n#define BIT_TIMER_8197F(x)                                                     \\\n\t(((x) & BIT_MASK_TIMER_8197F) << BIT_SHIFT_TIMER_8197F)\n#define BITS_TIMER_8197F (BIT_MASK_TIMER_8197F << BIT_SHIFT_TIMER_8197F)\n#define BIT_CLEAR_TIMER_8197F(x) ((x) & (~BITS_TIMER_8197F))\n#define BIT_GET_TIMER_8197F(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TIMER_8197F) & BIT_MASK_TIMER_8197F)\n#define BIT_SET_TIMER_8197F(x, v)                                              \\\n\t(BIT_CLEAR_TIMER_8197F(x) | BIT_TIMER_8197F(v))\n\n/* 2 REG_BT_COEX_8197F */\n#define BIT_R_GNT_BT_RFC_SW_8197F BIT(12)\n#define BIT_R_GNT_BT_RFC_SW_EN_8197F BIT(11)\n#define BIT_R_GNT_BT_BB_SW_8197F BIT(10)\n#define BIT_R_GNT_BT_BB_SW_EN_8197F BIT(9)\n#define BIT_R_BT_CNT_THREN_8197F BIT(8)\n\n#define BIT_SHIFT_R_BT_CNT_THR_8197F 0\n#define BIT_MASK_R_BT_CNT_THR_8197F 0xff\n#define BIT_R_BT_CNT_THR_8197F(x)                                              \\\n\t(((x) & BIT_MASK_R_BT_CNT_THR_8197F) << BIT_SHIFT_R_BT_CNT_THR_8197F)\n#define BITS_R_BT_CNT_THR_8197F                                                \\\n\t(BIT_MASK_R_BT_CNT_THR_8197F << BIT_SHIFT_R_BT_CNT_THR_8197F)\n#define BIT_CLEAR_R_BT_CNT_THR_8197F(x) ((x) & (~BITS_R_BT_CNT_THR_8197F))\n#define BIT_GET_R_BT_CNT_THR_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_BT_CNT_THR_8197F) & BIT_MASK_R_BT_CNT_THR_8197F)\n#define BIT_SET_R_BT_CNT_THR_8197F(x, v)                                       \\\n\t(BIT_CLEAR_R_BT_CNT_THR_8197F(x) | BIT_R_BT_CNT_THR_8197F(v))\n\n/* 2 REG_WLAN_ACT_MASK_CTRL_8197F */\n#define BIT_WLRX_TER_BY_CTL_8197F BIT(43)\n#define BIT_WLRX_TER_BY_AD_8197F BIT(42)\n#define BIT_ANT_DIVERSITY_SEL_8197F BIT(41)\n#define BIT_ANTSEL_FOR_BT_CTRL_EN_8197F BIT(40)\n#define BIT_WLACT_LOW_GNTWL_EN_8197F BIT(34)\n#define BIT_WLACT_HIGH_GNTBT_EN_8197F BIT(33)\n\n#define BIT_SHIFT_RXMYRTS_NAV_V1_8197F 8\n#define BIT_MASK_RXMYRTS_NAV_V1_8197F 0xff\n#define BIT_RXMYRTS_NAV_V1_8197F(x)                                            \\\n\t(((x) & BIT_MASK_RXMYRTS_NAV_V1_8197F)                                 \\\n\t << BIT_SHIFT_RXMYRTS_NAV_V1_8197F)\n#define BITS_RXMYRTS_NAV_V1_8197F                                              \\\n\t(BIT_MASK_RXMYRTS_NAV_V1_8197F << BIT_SHIFT_RXMYRTS_NAV_V1_8197F)\n#define BIT_CLEAR_RXMYRTS_NAV_V1_8197F(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8197F))\n#define BIT_GET_RXMYRTS_NAV_V1_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8197F) &                             \\\n\t BIT_MASK_RXMYRTS_NAV_V1_8197F)\n#define BIT_SET_RXMYRTS_NAV_V1_8197F(x, v)                                     \\\n\t(BIT_CLEAR_RXMYRTS_NAV_V1_8197F(x) | BIT_RXMYRTS_NAV_V1_8197F(v))\n\n#define BIT_SHIFT_RTSRST_V1_8197F 0\n#define BIT_MASK_RTSRST_V1_8197F 0xff\n#define BIT_RTSRST_V1_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_RTSRST_V1_8197F) << BIT_SHIFT_RTSRST_V1_8197F)\n#define BITS_RTSRST_V1_8197F                                                   \\\n\t(BIT_MASK_RTSRST_V1_8197F << BIT_SHIFT_RTSRST_V1_8197F)\n#define BIT_CLEAR_RTSRST_V1_8197F(x) ((x) & (~BITS_RTSRST_V1_8197F))\n#define BIT_GET_RTSRST_V1_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_RTSRST_V1_8197F) & BIT_MASK_RTSRST_V1_8197F)\n#define BIT_SET_RTSRST_V1_8197F(x, v)                                          \\\n\t(BIT_CLEAR_RTSRST_V1_8197F(x) | BIT_RTSRST_V1_8197F(v))\n\n/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8197F */\n\n#define BIT_SHIFT_BT_STAT_DELAY_8197F 12\n#define BIT_MASK_BT_STAT_DELAY_8197F 0xf\n#define BIT_BT_STAT_DELAY_8197F(x)                                             \\\n\t(((x) & BIT_MASK_BT_STAT_DELAY_8197F) << BIT_SHIFT_BT_STAT_DELAY_8197F)\n#define BITS_BT_STAT_DELAY_8197F                                               \\\n\t(BIT_MASK_BT_STAT_DELAY_8197F << BIT_SHIFT_BT_STAT_DELAY_8197F)\n#define BIT_CLEAR_BT_STAT_DELAY_8197F(x) ((x) & (~BITS_BT_STAT_DELAY_8197F))\n#define BIT_GET_BT_STAT_DELAY_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_BT_STAT_DELAY_8197F) & BIT_MASK_BT_STAT_DELAY_8197F)\n#define BIT_SET_BT_STAT_DELAY_8197F(x, v)                                      \\\n\t(BIT_CLEAR_BT_STAT_DELAY_8197F(x) | BIT_BT_STAT_DELAY_8197F(v))\n\n#define BIT_SHIFT_BT_TRX_INIT_DETECT_8197F 8\n#define BIT_MASK_BT_TRX_INIT_DETECT_8197F 0xf\n#define BIT_BT_TRX_INIT_DETECT_8197F(x)                                        \\\n\t(((x) & BIT_MASK_BT_TRX_INIT_DETECT_8197F)                             \\\n\t << BIT_SHIFT_BT_TRX_INIT_DETECT_8197F)\n#define BITS_BT_TRX_INIT_DETECT_8197F                                          \\\n\t(BIT_MASK_BT_TRX_INIT_DETECT_8197F                                     \\\n\t << BIT_SHIFT_BT_TRX_INIT_DETECT_8197F)\n#define BIT_CLEAR_BT_TRX_INIT_DETECT_8197F(x)                                  \\\n\t((x) & (~BITS_BT_TRX_INIT_DETECT_8197F))\n#define BIT_GET_BT_TRX_INIT_DETECT_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) &                         \\\n\t BIT_MASK_BT_TRX_INIT_DETECT_8197F)\n#define BIT_SET_BT_TRX_INIT_DETECT_8197F(x, v)                                 \\\n\t(BIT_CLEAR_BT_TRX_INIT_DETECT_8197F(x) |                               \\\n\t BIT_BT_TRX_INIT_DETECT_8197F(v))\n\n#define BIT_SHIFT_BT_PRI_DETECT_TO_8197F 4\n#define BIT_MASK_BT_PRI_DETECT_TO_8197F 0xf\n#define BIT_BT_PRI_DETECT_TO_8197F(x)                                          \\\n\t(((x) & BIT_MASK_BT_PRI_DETECT_TO_8197F)                               \\\n\t << BIT_SHIFT_BT_PRI_DETECT_TO_8197F)\n#define BITS_BT_PRI_DETECT_TO_8197F                                            \\\n\t(BIT_MASK_BT_PRI_DETECT_TO_8197F << BIT_SHIFT_BT_PRI_DETECT_TO_8197F)\n#define BIT_CLEAR_BT_PRI_DETECT_TO_8197F(x)                                    \\\n\t((x) & (~BITS_BT_PRI_DETECT_TO_8197F))\n#define BIT_GET_BT_PRI_DETECT_TO_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8197F) &                           \\\n\t BIT_MASK_BT_PRI_DETECT_TO_8197F)\n#define BIT_SET_BT_PRI_DETECT_TO_8197F(x, v)                                   \\\n\t(BIT_CLEAR_BT_PRI_DETECT_TO_8197F(x) | BIT_BT_PRI_DETECT_TO_8197F(v))\n\n#define BIT_R_GRANTALL_WLMASK_8197F BIT(3)\n#define BIT_STATIS_BT_EN_8197F BIT(2)\n#define BIT_WL_ACT_MASK_ENABLE_8197F BIT(1)\n#define BIT_ENHANCED_BT_8197F BIT(0)\n\n/* 2 REG_BT_ACT_STATISTICS_8197F */\n\n#define BIT_SHIFT_STATIS_BT_LO_RX_8197F (48 & CPU_OPT_WIDTH)\n#define BIT_MASK_STATIS_BT_LO_RX_8197F 0xffff\n#define BIT_STATIS_BT_LO_RX_8197F(x)                                           \\\n\t(((x) & BIT_MASK_STATIS_BT_LO_RX_8197F)                                \\\n\t << BIT_SHIFT_STATIS_BT_LO_RX_8197F)\n#define BITS_STATIS_BT_LO_RX_8197F                                             \\\n\t(BIT_MASK_STATIS_BT_LO_RX_8197F << BIT_SHIFT_STATIS_BT_LO_RX_8197F)\n#define BIT_CLEAR_STATIS_BT_LO_RX_8197F(x) ((x) & (~BITS_STATIS_BT_LO_RX_8197F))\n#define BIT_GET_STATIS_BT_LO_RX_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8197F) &                            \\\n\t BIT_MASK_STATIS_BT_LO_RX_8197F)\n#define BIT_SET_STATIS_BT_LO_RX_8197F(x, v)                                    \\\n\t(BIT_CLEAR_STATIS_BT_LO_RX_8197F(x) | BIT_STATIS_BT_LO_RX_8197F(v))\n\n#define BIT_SHIFT_STATIS_BT_LO_TX_8197F (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_STATIS_BT_LO_TX_8197F 0xffff\n#define BIT_STATIS_BT_LO_TX_8197F(x)                                           \\\n\t(((x) & BIT_MASK_STATIS_BT_LO_TX_8197F)                                \\\n\t << BIT_SHIFT_STATIS_BT_LO_TX_8197F)\n#define BITS_STATIS_BT_LO_TX_8197F                                             \\\n\t(BIT_MASK_STATIS_BT_LO_TX_8197F << BIT_SHIFT_STATIS_BT_LO_TX_8197F)\n#define BIT_CLEAR_STATIS_BT_LO_TX_8197F(x) ((x) & (~BITS_STATIS_BT_LO_TX_8197F))\n#define BIT_GET_STATIS_BT_LO_TX_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8197F) &                            \\\n\t BIT_MASK_STATIS_BT_LO_TX_8197F)\n#define BIT_SET_STATIS_BT_LO_TX_8197F(x, v)                                    \\\n\t(BIT_CLEAR_STATIS_BT_LO_TX_8197F(x) | BIT_STATIS_BT_LO_TX_8197F(v))\n\n#define BIT_SHIFT_STATIS_BT_HI_RX_8197F 16\n#define BIT_MASK_STATIS_BT_HI_RX_8197F 0xffff\n#define BIT_STATIS_BT_HI_RX_8197F(x)                                           \\\n\t(((x) & BIT_MASK_STATIS_BT_HI_RX_8197F)                                \\\n\t << BIT_SHIFT_STATIS_BT_HI_RX_8197F)\n#define BITS_STATIS_BT_HI_RX_8197F                                             \\\n\t(BIT_MASK_STATIS_BT_HI_RX_8197F << BIT_SHIFT_STATIS_BT_HI_RX_8197F)\n#define BIT_CLEAR_STATIS_BT_HI_RX_8197F(x) ((x) & (~BITS_STATIS_BT_HI_RX_8197F))\n#define BIT_GET_STATIS_BT_HI_RX_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8197F) &                            \\\n\t BIT_MASK_STATIS_BT_HI_RX_8197F)\n#define BIT_SET_STATIS_BT_HI_RX_8197F(x, v)                                    \\\n\t(BIT_CLEAR_STATIS_BT_HI_RX_8197F(x) | BIT_STATIS_BT_HI_RX_8197F(v))\n\n#define BIT_SHIFT_STATIS_BT_HI_TX_8197F 0\n#define BIT_MASK_STATIS_BT_HI_TX_8197F 0xffff\n#define BIT_STATIS_BT_HI_TX_8197F(x)                                           \\\n\t(((x) & BIT_MASK_STATIS_BT_HI_TX_8197F)                                \\\n\t << BIT_SHIFT_STATIS_BT_HI_TX_8197F)\n#define BITS_STATIS_BT_HI_TX_8197F                                             \\\n\t(BIT_MASK_STATIS_BT_HI_TX_8197F << BIT_SHIFT_STATIS_BT_HI_TX_8197F)\n#define BIT_CLEAR_STATIS_BT_HI_TX_8197F(x) ((x) & (~BITS_STATIS_BT_HI_TX_8197F))\n#define BIT_GET_STATIS_BT_HI_TX_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8197F) &                            \\\n\t BIT_MASK_STATIS_BT_HI_TX_8197F)\n#define BIT_SET_STATIS_BT_HI_TX_8197F(x, v)                                    \\\n\t(BIT_CLEAR_STATIS_BT_HI_TX_8197F(x) | BIT_STATIS_BT_HI_TX_8197F(v))\n\n/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8197F */\n\n#define BIT_SHIFT_R_BT_CMD_RPT_8197F 16\n#define BIT_MASK_R_BT_CMD_RPT_8197F 0xffff\n#define BIT_R_BT_CMD_RPT_8197F(x)                                              \\\n\t(((x) & BIT_MASK_R_BT_CMD_RPT_8197F) << BIT_SHIFT_R_BT_CMD_RPT_8197F)\n#define BITS_R_BT_CMD_RPT_8197F                                                \\\n\t(BIT_MASK_R_BT_CMD_RPT_8197F << BIT_SHIFT_R_BT_CMD_RPT_8197F)\n#define BIT_CLEAR_R_BT_CMD_RPT_8197F(x) ((x) & (~BITS_R_BT_CMD_RPT_8197F))\n#define BIT_GET_R_BT_CMD_RPT_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_BT_CMD_RPT_8197F) & BIT_MASK_R_BT_CMD_RPT_8197F)\n#define BIT_SET_R_BT_CMD_RPT_8197F(x, v)                                       \\\n\t(BIT_CLEAR_R_BT_CMD_RPT_8197F(x) | BIT_R_BT_CMD_RPT_8197F(v))\n\n#define BIT_SHIFT_R_RPT_FROM_BT_8197F 8\n#define BIT_MASK_R_RPT_FROM_BT_8197F 0xff\n#define BIT_R_RPT_FROM_BT_8197F(x)                                             \\\n\t(((x) & BIT_MASK_R_RPT_FROM_BT_8197F) << BIT_SHIFT_R_RPT_FROM_BT_8197F)\n#define BITS_R_RPT_FROM_BT_8197F                                               \\\n\t(BIT_MASK_R_RPT_FROM_BT_8197F << BIT_SHIFT_R_RPT_FROM_BT_8197F)\n#define BIT_CLEAR_R_RPT_FROM_BT_8197F(x) ((x) & (~BITS_R_RPT_FROM_BT_8197F))\n#define BIT_GET_R_RPT_FROM_BT_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_RPT_FROM_BT_8197F) & BIT_MASK_R_RPT_FROM_BT_8197F)\n#define BIT_SET_R_RPT_FROM_BT_8197F(x, v)                                      \\\n\t(BIT_CLEAR_R_RPT_FROM_BT_8197F(x) | BIT_R_RPT_FROM_BT_8197F(v))\n\n#define BIT_SHIFT_BT_HID_ISR_SET_8197F 6\n#define BIT_MASK_BT_HID_ISR_SET_8197F 0x3\n#define BIT_BT_HID_ISR_SET_8197F(x)                                            \\\n\t(((x) & BIT_MASK_BT_HID_ISR_SET_8197F)                                 \\\n\t << BIT_SHIFT_BT_HID_ISR_SET_8197F)\n#define BITS_BT_HID_ISR_SET_8197F                                              \\\n\t(BIT_MASK_BT_HID_ISR_SET_8197F << BIT_SHIFT_BT_HID_ISR_SET_8197F)\n#define BIT_CLEAR_BT_HID_ISR_SET_8197F(x) ((x) & (~BITS_BT_HID_ISR_SET_8197F))\n#define BIT_GET_BT_HID_ISR_SET_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_BT_HID_ISR_SET_8197F) &                             \\\n\t BIT_MASK_BT_HID_ISR_SET_8197F)\n#define BIT_SET_BT_HID_ISR_SET_8197F(x, v)                                     \\\n\t(BIT_CLEAR_BT_HID_ISR_SET_8197F(x) | BIT_BT_HID_ISR_SET_8197F(v))\n\n#define BIT_TDMA_BT_START_NOTIFY_8197F BIT(5)\n#define BIT_ENABLE_TDMA_FW_MODE_8197F BIT(4)\n#define BIT_ENABLE_PTA_TDMA_MODE_8197F BIT(3)\n#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8197F BIT(2)\n#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8197F BIT(1)\n#define BIT_RTK_BT_ENABLE_8197F BIT(0)\n\n/* 2 REG_BT_STATUS_REPORT_REGISTER_8197F */\n\n#define BIT_SHIFT_BT_PROFILE_8197F 24\n#define BIT_MASK_BT_PROFILE_8197F 0xff\n#define BIT_BT_PROFILE_8197F(x)                                                \\\n\t(((x) & BIT_MASK_BT_PROFILE_8197F) << BIT_SHIFT_BT_PROFILE_8197F)\n#define BITS_BT_PROFILE_8197F                                                  \\\n\t(BIT_MASK_BT_PROFILE_8197F << BIT_SHIFT_BT_PROFILE_8197F)\n#define BIT_CLEAR_BT_PROFILE_8197F(x) ((x) & (~BITS_BT_PROFILE_8197F))\n#define BIT_GET_BT_PROFILE_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_BT_PROFILE_8197F) & BIT_MASK_BT_PROFILE_8197F)\n#define BIT_SET_BT_PROFILE_8197F(x, v)                                         \\\n\t(BIT_CLEAR_BT_PROFILE_8197F(x) | BIT_BT_PROFILE_8197F(v))\n\n#define BIT_SHIFT_BT_POWER_8197F 16\n#define BIT_MASK_BT_POWER_8197F 0xff\n#define BIT_BT_POWER_8197F(x)                                                  \\\n\t(((x) & BIT_MASK_BT_POWER_8197F) << BIT_SHIFT_BT_POWER_8197F)\n#define BITS_BT_POWER_8197F                                                    \\\n\t(BIT_MASK_BT_POWER_8197F << BIT_SHIFT_BT_POWER_8197F)\n#define BIT_CLEAR_BT_POWER_8197F(x) ((x) & (~BITS_BT_POWER_8197F))\n#define BIT_GET_BT_POWER_8197F(x)                                              \\\n\t(((x) >> BIT_SHIFT_BT_POWER_8197F) & BIT_MASK_BT_POWER_8197F)\n#define BIT_SET_BT_POWER_8197F(x, v)                                           \\\n\t(BIT_CLEAR_BT_POWER_8197F(x) | BIT_BT_POWER_8197F(v))\n\n#define BIT_SHIFT_BT_PREDECT_STATUS_8197F 8\n#define BIT_MASK_BT_PREDECT_STATUS_8197F 0xff\n#define BIT_BT_PREDECT_STATUS_8197F(x)                                         \\\n\t(((x) & BIT_MASK_BT_PREDECT_STATUS_8197F)                              \\\n\t << BIT_SHIFT_BT_PREDECT_STATUS_8197F)\n#define BITS_BT_PREDECT_STATUS_8197F                                           \\\n\t(BIT_MASK_BT_PREDECT_STATUS_8197F << BIT_SHIFT_BT_PREDECT_STATUS_8197F)\n#define BIT_CLEAR_BT_PREDECT_STATUS_8197F(x)                                   \\\n\t((x) & (~BITS_BT_PREDECT_STATUS_8197F))\n#define BIT_GET_BT_PREDECT_STATUS_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8197F) &                          \\\n\t BIT_MASK_BT_PREDECT_STATUS_8197F)\n#define BIT_SET_BT_PREDECT_STATUS_8197F(x, v)                                  \\\n\t(BIT_CLEAR_BT_PREDECT_STATUS_8197F(x) | BIT_BT_PREDECT_STATUS_8197F(v))\n\n#define BIT_SHIFT_BT_CMD_INFO_8197F 0\n#define BIT_MASK_BT_CMD_INFO_8197F 0xff\n#define BIT_BT_CMD_INFO_8197F(x)                                               \\\n\t(((x) & BIT_MASK_BT_CMD_INFO_8197F) << BIT_SHIFT_BT_CMD_INFO_8197F)\n#define BITS_BT_CMD_INFO_8197F                                                 \\\n\t(BIT_MASK_BT_CMD_INFO_8197F << BIT_SHIFT_BT_CMD_INFO_8197F)\n#define BIT_CLEAR_BT_CMD_INFO_8197F(x) ((x) & (~BITS_BT_CMD_INFO_8197F))\n#define BIT_GET_BT_CMD_INFO_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_BT_CMD_INFO_8197F) & BIT_MASK_BT_CMD_INFO_8197F)\n#define BIT_SET_BT_CMD_INFO_8197F(x, v)                                        \\\n\t(BIT_CLEAR_BT_CMD_INFO_8197F(x) | BIT_BT_CMD_INFO_8197F(v))\n\n/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8197F */\n#define BIT_EN_MAC_NULL_PKT_NOTIFY_8197F BIT(31)\n#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8197F BIT(30)\n#define BIT_EN_BT_STSTUS_RPT_8197F BIT(29)\n#define BIT_EN_BT_POWER_8197F BIT(28)\n#define BIT_EN_BT_CHANNEL_8197F BIT(27)\n#define BIT_EN_BT_SLOT_CHANGE_8197F BIT(26)\n#define BIT_EN_BT_PROFILE_OR_HID_8197F BIT(25)\n#define BIT_WLAN_RPT_NOTIFY_8197F BIT(24)\n\n#define BIT_SHIFT_WLAN_RPT_DATA_8197F 16\n#define BIT_MASK_WLAN_RPT_DATA_8197F 0xff\n#define BIT_WLAN_RPT_DATA_8197F(x)                                             \\\n\t(((x) & BIT_MASK_WLAN_RPT_DATA_8197F) << BIT_SHIFT_WLAN_RPT_DATA_8197F)\n#define BITS_WLAN_RPT_DATA_8197F                                               \\\n\t(BIT_MASK_WLAN_RPT_DATA_8197F << BIT_SHIFT_WLAN_RPT_DATA_8197F)\n#define BIT_CLEAR_WLAN_RPT_DATA_8197F(x) ((x) & (~BITS_WLAN_RPT_DATA_8197F))\n#define BIT_GET_WLAN_RPT_DATA_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_WLAN_RPT_DATA_8197F) & BIT_MASK_WLAN_RPT_DATA_8197F)\n#define BIT_SET_WLAN_RPT_DATA_8197F(x, v)                                      \\\n\t(BIT_CLEAR_WLAN_RPT_DATA_8197F(x) | BIT_WLAN_RPT_DATA_8197F(v))\n\n#define BIT_SHIFT_CMD_ID_8197F 8\n#define BIT_MASK_CMD_ID_8197F 0xff\n#define BIT_CMD_ID_8197F(x)                                                    \\\n\t(((x) & BIT_MASK_CMD_ID_8197F) << BIT_SHIFT_CMD_ID_8197F)\n#define BITS_CMD_ID_8197F (BIT_MASK_CMD_ID_8197F << BIT_SHIFT_CMD_ID_8197F)\n#define BIT_CLEAR_CMD_ID_8197F(x) ((x) & (~BITS_CMD_ID_8197F))\n#define BIT_GET_CMD_ID_8197F(x)                                                \\\n\t(((x) >> BIT_SHIFT_CMD_ID_8197F) & BIT_MASK_CMD_ID_8197F)\n#define BIT_SET_CMD_ID_8197F(x, v)                                             \\\n\t(BIT_CLEAR_CMD_ID_8197F(x) | BIT_CMD_ID_8197F(v))\n\n#define BIT_SHIFT_BT_DATA_8197F 0\n#define BIT_MASK_BT_DATA_8197F 0xff\n#define BIT_BT_DATA_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_BT_DATA_8197F) << BIT_SHIFT_BT_DATA_8197F)\n#define BITS_BT_DATA_8197F (BIT_MASK_BT_DATA_8197F << BIT_SHIFT_BT_DATA_8197F)\n#define BIT_CLEAR_BT_DATA_8197F(x) ((x) & (~BITS_BT_DATA_8197F))\n#define BIT_GET_BT_DATA_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_BT_DATA_8197F) & BIT_MASK_BT_DATA_8197F)\n#define BIT_SET_BT_DATA_8197F(x, v)                                            \\\n\t(BIT_CLEAR_BT_DATA_8197F(x) | BIT_BT_DATA_8197F(v))\n\n/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8197F */\n\n#define BIT_SHIFT_WLAN_RPT_TO_8197F 0\n#define BIT_MASK_WLAN_RPT_TO_8197F 0xff\n#define BIT_WLAN_RPT_TO_8197F(x)                                               \\\n\t(((x) & BIT_MASK_WLAN_RPT_TO_8197F) << BIT_SHIFT_WLAN_RPT_TO_8197F)\n#define BITS_WLAN_RPT_TO_8197F                                                 \\\n\t(BIT_MASK_WLAN_RPT_TO_8197F << BIT_SHIFT_WLAN_RPT_TO_8197F)\n#define BIT_CLEAR_WLAN_RPT_TO_8197F(x) ((x) & (~BITS_WLAN_RPT_TO_8197F))\n#define BIT_GET_WLAN_RPT_TO_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_WLAN_RPT_TO_8197F) & BIT_MASK_WLAN_RPT_TO_8197F)\n#define BIT_SET_WLAN_RPT_TO_8197F(x, v)                                        \\\n\t(BIT_CLEAR_WLAN_RPT_TO_8197F(x) | BIT_WLAN_RPT_TO_8197F(v))\n\n/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8197F */\n\n#define BIT_SHIFT_ISOLATION_CHK_8197F 1\n#define BIT_MASK_ISOLATION_CHK_8197F 0x7fffffffffffffffffffL\n#define BIT_ISOLATION_CHK_8197F(x)                                             \\\n\t(((x) & BIT_MASK_ISOLATION_CHK_8197F) << BIT_SHIFT_ISOLATION_CHK_8197F)\n#define BITS_ISOLATION_CHK_8197F                                               \\\n\t(BIT_MASK_ISOLATION_CHK_8197F << BIT_SHIFT_ISOLATION_CHK_8197F)\n#define BIT_CLEAR_ISOLATION_CHK_8197F(x) ((x) & (~BITS_ISOLATION_CHK_8197F))\n#define BIT_GET_ISOLATION_CHK_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_ISOLATION_CHK_8197F) & BIT_MASK_ISOLATION_CHK_8197F)\n#define BIT_SET_ISOLATION_CHK_8197F(x, v)                                      \\\n\t(BIT_CLEAR_ISOLATION_CHK_8197F(x) | BIT_ISOLATION_CHK_8197F(v))\n\n#define BIT_ISOLATION_EN_8197F BIT(0)\n\n/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8197F */\n#define BIT_BT_HID_ISR_8197F BIT(7)\n#define BIT_BT_QUERY_ISR_8197F BIT(6)\n#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8197F BIT(5)\n#define BIT_WLAN_RPT_ISR_8197F BIT(4)\n#define BIT_BT_POWER_ISR_8197F BIT(3)\n#define BIT_BT_CHANNEL_ISR_8197F BIT(2)\n#define BIT_BT_SLOT_CHANGE_ISR_8197F BIT(1)\n#define BIT_BT_PROFILE_ISR_8197F BIT(0)\n\n/* 2 REG_BT_TDMA_TIME_REGISTER_8197F */\n\n#define BIT_SHIFT_BT_TIME_8197F 6\n#define BIT_MASK_BT_TIME_8197F 0x3ffffff\n#define BIT_BT_TIME_8197F(x)                                                   \\\n\t(((x) & BIT_MASK_BT_TIME_8197F) << BIT_SHIFT_BT_TIME_8197F)\n#define BITS_BT_TIME_8197F (BIT_MASK_BT_TIME_8197F << BIT_SHIFT_BT_TIME_8197F)\n#define BIT_CLEAR_BT_TIME_8197F(x) ((x) & (~BITS_BT_TIME_8197F))\n#define BIT_GET_BT_TIME_8197F(x)                                               \\\n\t(((x) >> BIT_SHIFT_BT_TIME_8197F) & BIT_MASK_BT_TIME_8197F)\n#define BIT_SET_BT_TIME_8197F(x, v)                                            \\\n\t(BIT_CLEAR_BT_TIME_8197F(x) | BIT_BT_TIME_8197F(v))\n\n#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F 0\n#define BIT_MASK_BT_RPT_SAMPLE_RATE_8197F 0x3f\n#define BIT_BT_RPT_SAMPLE_RATE_8197F(x)                                        \\\n\t(((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8197F)                             \\\n\t << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F)\n#define BITS_BT_RPT_SAMPLE_RATE_8197F                                          \\\n\t(BIT_MASK_BT_RPT_SAMPLE_RATE_8197F                                     \\\n\t << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F)\n#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8197F(x)                                  \\\n\t((x) & (~BITS_BT_RPT_SAMPLE_RATE_8197F))\n#define BIT_GET_BT_RPT_SAMPLE_RATE_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) &                         \\\n\t BIT_MASK_BT_RPT_SAMPLE_RATE_8197F)\n#define BIT_SET_BT_RPT_SAMPLE_RATE_8197F(x, v)                                 \\\n\t(BIT_CLEAR_BT_RPT_SAMPLE_RATE_8197F(x) |                               \\\n\t BIT_BT_RPT_SAMPLE_RATE_8197F(v))\n\n/* 2 REG_BT_ACT_REGISTER_8197F */\n\n#define BIT_SHIFT_BT_EISR_EN_8197F 16\n#define BIT_MASK_BT_EISR_EN_8197F 0xff\n#define BIT_BT_EISR_EN_8197F(x)                                                \\\n\t(((x) & BIT_MASK_BT_EISR_EN_8197F) << BIT_SHIFT_BT_EISR_EN_8197F)\n#define BITS_BT_EISR_EN_8197F                                                  \\\n\t(BIT_MASK_BT_EISR_EN_8197F << BIT_SHIFT_BT_EISR_EN_8197F)\n#define BIT_CLEAR_BT_EISR_EN_8197F(x) ((x) & (~BITS_BT_EISR_EN_8197F))\n#define BIT_GET_BT_EISR_EN_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_BT_EISR_EN_8197F) & BIT_MASK_BT_EISR_EN_8197F)\n#define BIT_SET_BT_EISR_EN_8197F(x, v)                                         \\\n\t(BIT_CLEAR_BT_EISR_EN_8197F(x) | BIT_BT_EISR_EN_8197F(v))\n\n#define BIT_BT_ACT_FALLING_ISR_8197F BIT(10)\n#define BIT_BT_ACT_RISING_ISR_8197F BIT(9)\n#define BIT_TDMA_TO_ISR_8197F BIT(8)\n\n#define BIT_SHIFT_BT_CH_8197F 0\n#define BIT_MASK_BT_CH_8197F 0xff\n#define BIT_BT_CH_8197F(x)                                                     \\\n\t(((x) & BIT_MASK_BT_CH_8197F) << BIT_SHIFT_BT_CH_8197F)\n#define BITS_BT_CH_8197F (BIT_MASK_BT_CH_8197F << BIT_SHIFT_BT_CH_8197F)\n#define BIT_CLEAR_BT_CH_8197F(x) ((x) & (~BITS_BT_CH_8197F))\n#define BIT_GET_BT_CH_8197F(x)                                                 \\\n\t(((x) >> BIT_SHIFT_BT_CH_8197F) & BIT_MASK_BT_CH_8197F)\n#define BIT_SET_BT_CH_8197F(x, v)                                              \\\n\t(BIT_CLEAR_BT_CH_8197F(x) | BIT_BT_CH_8197F(v))\n\n/* 2 REG_OBFF_CTRL_BASIC_8197F */\n#define BIT_OBFF_EN_V1_8197F BIT(31)\n\n#define BIT_SHIFT_OBFF_STATE_V1_8197F 28\n#define BIT_MASK_OBFF_STATE_V1_8197F 0x3\n#define BIT_OBFF_STATE_V1_8197F(x)                                             \\\n\t(((x) & BIT_MASK_OBFF_STATE_V1_8197F) << BIT_SHIFT_OBFF_STATE_V1_8197F)\n#define BITS_OBFF_STATE_V1_8197F                                               \\\n\t(BIT_MASK_OBFF_STATE_V1_8197F << BIT_SHIFT_OBFF_STATE_V1_8197F)\n#define BIT_CLEAR_OBFF_STATE_V1_8197F(x) ((x) & (~BITS_OBFF_STATE_V1_8197F))\n#define BIT_GET_OBFF_STATE_V1_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_OBFF_STATE_V1_8197F) & BIT_MASK_OBFF_STATE_V1_8197F)\n#define BIT_SET_OBFF_STATE_V1_8197F(x, v)                                      \\\n\t(BIT_CLEAR_OBFF_STATE_V1_8197F(x) | BIT_OBFF_STATE_V1_8197F(v))\n\n#define BIT_OBFF_ACT_RXDMA_EN_8197F BIT(27)\n#define BIT_OBFF_BLOCK_INT_EN_8197F BIT(26)\n#define BIT_OBFF_AUTOACT_EN_8197F BIT(25)\n#define BIT_OBFF_AUTOIDLE_EN_8197F BIT(24)\n\n#define BIT_SHIFT_WAKE_MAX_PLS_8197F 20\n#define BIT_MASK_WAKE_MAX_PLS_8197F 0x7\n#define BIT_WAKE_MAX_PLS_8197F(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MAX_PLS_8197F) << BIT_SHIFT_WAKE_MAX_PLS_8197F)\n#define BITS_WAKE_MAX_PLS_8197F                                                \\\n\t(BIT_MASK_WAKE_MAX_PLS_8197F << BIT_SHIFT_WAKE_MAX_PLS_8197F)\n#define BIT_CLEAR_WAKE_MAX_PLS_8197F(x) ((x) & (~BITS_WAKE_MAX_PLS_8197F))\n#define BIT_GET_WAKE_MAX_PLS_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MAX_PLS_8197F) & BIT_MASK_WAKE_MAX_PLS_8197F)\n#define BIT_SET_WAKE_MAX_PLS_8197F(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MAX_PLS_8197F(x) | BIT_WAKE_MAX_PLS_8197F(v))\n\n#define BIT_SHIFT_WAKE_MIN_PLS_8197F 16\n#define BIT_MASK_WAKE_MIN_PLS_8197F 0x7\n#define BIT_WAKE_MIN_PLS_8197F(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MIN_PLS_8197F) << BIT_SHIFT_WAKE_MIN_PLS_8197F)\n#define BITS_WAKE_MIN_PLS_8197F                                                \\\n\t(BIT_MASK_WAKE_MIN_PLS_8197F << BIT_SHIFT_WAKE_MIN_PLS_8197F)\n#define BIT_CLEAR_WAKE_MIN_PLS_8197F(x) ((x) & (~BITS_WAKE_MIN_PLS_8197F))\n#define BIT_GET_WAKE_MIN_PLS_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MIN_PLS_8197F) & BIT_MASK_WAKE_MIN_PLS_8197F)\n#define BIT_SET_WAKE_MIN_PLS_8197F(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MIN_PLS_8197F(x) | BIT_WAKE_MIN_PLS_8197F(v))\n\n#define BIT_SHIFT_WAKE_MAX_F2F_8197F 12\n#define BIT_MASK_WAKE_MAX_F2F_8197F 0x7\n#define BIT_WAKE_MAX_F2F_8197F(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MAX_F2F_8197F) << BIT_SHIFT_WAKE_MAX_F2F_8197F)\n#define BITS_WAKE_MAX_F2F_8197F                                                \\\n\t(BIT_MASK_WAKE_MAX_F2F_8197F << BIT_SHIFT_WAKE_MAX_F2F_8197F)\n#define BIT_CLEAR_WAKE_MAX_F2F_8197F(x) ((x) & (~BITS_WAKE_MAX_F2F_8197F))\n#define BIT_GET_WAKE_MAX_F2F_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MAX_F2F_8197F) & BIT_MASK_WAKE_MAX_F2F_8197F)\n#define BIT_SET_WAKE_MAX_F2F_8197F(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MAX_F2F_8197F(x) | BIT_WAKE_MAX_F2F_8197F(v))\n\n#define BIT_SHIFT_WAKE_MIN_F2F_8197F 8\n#define BIT_MASK_WAKE_MIN_F2F_8197F 0x7\n#define BIT_WAKE_MIN_F2F_8197F(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MIN_F2F_8197F) << BIT_SHIFT_WAKE_MIN_F2F_8197F)\n#define BITS_WAKE_MIN_F2F_8197F                                                \\\n\t(BIT_MASK_WAKE_MIN_F2F_8197F << BIT_SHIFT_WAKE_MIN_F2F_8197F)\n#define BIT_CLEAR_WAKE_MIN_F2F_8197F(x) ((x) & (~BITS_WAKE_MIN_F2F_8197F))\n#define BIT_GET_WAKE_MIN_F2F_8197F(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MIN_F2F_8197F) & BIT_MASK_WAKE_MIN_F2F_8197F)\n#define BIT_SET_WAKE_MIN_F2F_8197F(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MIN_F2F_8197F(x) | BIT_WAKE_MIN_F2F_8197F(v))\n\n#define BIT_APP_CPU_ACT_V1_8197F BIT(3)\n#define BIT_APP_OBFF_V1_8197F BIT(2)\n#define BIT_APP_IDLE_V1_8197F BIT(1)\n#define BIT_APP_INIT_V1_8197F BIT(0)\n\n/* 2 REG_OBFF_CTRL2_TIMER_8197F */\n\n#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F 24\n#define BIT_MASK_RX_HIGH_TIMER_IDX_8197F 0x7\n#define BIT_RX_HIGH_TIMER_IDX_8197F(x)                                         \\\n\t(((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8197F)                              \\\n\t << BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F)\n#define BITS_RX_HIGH_TIMER_IDX_8197F                                           \\\n\t(BIT_MASK_RX_HIGH_TIMER_IDX_8197F << BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F)\n#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8197F(x)                                   \\\n\t((x) & (~BITS_RX_HIGH_TIMER_IDX_8197F))\n#define BIT_GET_RX_HIGH_TIMER_IDX_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) &                          \\\n\t BIT_MASK_RX_HIGH_TIMER_IDX_8197F)\n#define BIT_SET_RX_HIGH_TIMER_IDX_8197F(x, v)                                  \\\n\t(BIT_CLEAR_RX_HIGH_TIMER_IDX_8197F(x) | BIT_RX_HIGH_TIMER_IDX_8197F(v))\n\n#define BIT_SHIFT_RX_MED_TIMER_IDX_8197F 16\n#define BIT_MASK_RX_MED_TIMER_IDX_8197F 0x7\n#define BIT_RX_MED_TIMER_IDX_8197F(x)                                          \\\n\t(((x) & BIT_MASK_RX_MED_TIMER_IDX_8197F)                               \\\n\t << BIT_SHIFT_RX_MED_TIMER_IDX_8197F)\n#define BITS_RX_MED_TIMER_IDX_8197F                                            \\\n\t(BIT_MASK_RX_MED_TIMER_IDX_8197F << BIT_SHIFT_RX_MED_TIMER_IDX_8197F)\n#define BIT_CLEAR_RX_MED_TIMER_IDX_8197F(x)                                    \\\n\t((x) & (~BITS_RX_MED_TIMER_IDX_8197F))\n#define BIT_GET_RX_MED_TIMER_IDX_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8197F) &                           \\\n\t BIT_MASK_RX_MED_TIMER_IDX_8197F)\n#define BIT_SET_RX_MED_TIMER_IDX_8197F(x, v)                                   \\\n\t(BIT_CLEAR_RX_MED_TIMER_IDX_8197F(x) | BIT_RX_MED_TIMER_IDX_8197F(v))\n\n#define BIT_SHIFT_RX_LOW_TIMER_IDX_8197F 8\n#define BIT_MASK_RX_LOW_TIMER_IDX_8197F 0x7\n#define BIT_RX_LOW_TIMER_IDX_8197F(x)                                          \\\n\t(((x) & BIT_MASK_RX_LOW_TIMER_IDX_8197F)                               \\\n\t << BIT_SHIFT_RX_LOW_TIMER_IDX_8197F)\n#define BITS_RX_LOW_TIMER_IDX_8197F                                            \\\n\t(BIT_MASK_RX_LOW_TIMER_IDX_8197F << BIT_SHIFT_RX_LOW_TIMER_IDX_8197F)\n#define BIT_CLEAR_RX_LOW_TIMER_IDX_8197F(x)                                    \\\n\t((x) & (~BITS_RX_LOW_TIMER_IDX_8197F))\n#define BIT_GET_RX_LOW_TIMER_IDX_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) &                           \\\n\t BIT_MASK_RX_LOW_TIMER_IDX_8197F)\n#define BIT_SET_RX_LOW_TIMER_IDX_8197F(x, v)                                   \\\n\t(BIT_CLEAR_RX_LOW_TIMER_IDX_8197F(x) | BIT_RX_LOW_TIMER_IDX_8197F(v))\n\n#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F 0\n#define BIT_MASK_OBFF_INT_TIMER_IDX_8197F 0x7\n#define BIT_OBFF_INT_TIMER_IDX_8197F(x)                                        \\\n\t(((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8197F)                             \\\n\t << BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F)\n#define BITS_OBFF_INT_TIMER_IDX_8197F                                          \\\n\t(BIT_MASK_OBFF_INT_TIMER_IDX_8197F                                     \\\n\t << BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F)\n#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8197F(x)                                  \\\n\t((x) & (~BITS_OBFF_INT_TIMER_IDX_8197F))\n#define BIT_GET_OBFF_INT_TIMER_IDX_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) &                         \\\n\t BIT_MASK_OBFF_INT_TIMER_IDX_8197F)\n#define BIT_SET_OBFF_INT_TIMER_IDX_8197F(x, v)                                 \\\n\t(BIT_CLEAR_OBFF_INT_TIMER_IDX_8197F(x) |                               \\\n\t BIT_OBFF_INT_TIMER_IDX_8197F(v))\n\n/* 2 REG_LTR_CTRL_BASIC_8197F */\n#define BIT_LTR_EN_V1_8197F BIT(31)\n#define BIT_LTR_HW_EN_V1_8197F BIT(30)\n#define BIT_LRT_ACT_CTS_EN_8197F BIT(29)\n#define BIT_LTR_ACT_RXPKT_EN_8197F BIT(28)\n#define BIT_LTR_ACT_RXDMA_EN_8197F BIT(27)\n#define BIT_LTR_IDLE_NO_SNOOP_8197F BIT(26)\n#define BIT_SPDUP_MGTPKT_8197F BIT(25)\n#define BIT_RX_AGG_EN_8197F BIT(24)\n#define BIT_APP_LTR_ACT_8197F BIT(23)\n#define BIT_APP_LTR_IDLE_8197F BIT(22)\n\n#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F 20\n#define BIT_MASK_HIGH_RATE_TRIG_SEL_8197F 0x3\n#define BIT_HIGH_RATE_TRIG_SEL_8197F(x)                                        \\\n\t(((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8197F)                             \\\n\t << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F)\n#define BITS_HIGH_RATE_TRIG_SEL_8197F                                          \\\n\t(BIT_MASK_HIGH_RATE_TRIG_SEL_8197F                                     \\\n\t << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F)\n#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8197F(x)                                  \\\n\t((x) & (~BITS_HIGH_RATE_TRIG_SEL_8197F))\n#define BIT_GET_HIGH_RATE_TRIG_SEL_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) &                         \\\n\t BIT_MASK_HIGH_RATE_TRIG_SEL_8197F)\n#define BIT_SET_HIGH_RATE_TRIG_SEL_8197F(x, v)                                 \\\n\t(BIT_CLEAR_HIGH_RATE_TRIG_SEL_8197F(x) |                               \\\n\t BIT_HIGH_RATE_TRIG_SEL_8197F(v))\n\n#define BIT_SHIFT_MED_RATE_TRIG_SEL_8197F 18\n#define BIT_MASK_MED_RATE_TRIG_SEL_8197F 0x3\n#define BIT_MED_RATE_TRIG_SEL_8197F(x)                                         \\\n\t(((x) & BIT_MASK_MED_RATE_TRIG_SEL_8197F)                              \\\n\t << BIT_SHIFT_MED_RATE_TRIG_SEL_8197F)\n#define BITS_MED_RATE_TRIG_SEL_8197F                                           \\\n\t(BIT_MASK_MED_RATE_TRIG_SEL_8197F << BIT_SHIFT_MED_RATE_TRIG_SEL_8197F)\n#define BIT_CLEAR_MED_RATE_TRIG_SEL_8197F(x)                                   \\\n\t((x) & (~BITS_MED_RATE_TRIG_SEL_8197F))\n#define BIT_GET_MED_RATE_TRIG_SEL_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) &                          \\\n\t BIT_MASK_MED_RATE_TRIG_SEL_8197F)\n#define BIT_SET_MED_RATE_TRIG_SEL_8197F(x, v)                                  \\\n\t(BIT_CLEAR_MED_RATE_TRIG_SEL_8197F(x) | BIT_MED_RATE_TRIG_SEL_8197F(v))\n\n#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F 16\n#define BIT_MASK_LOW_RATE_TRIG_SEL_8197F 0x3\n#define BIT_LOW_RATE_TRIG_SEL_8197F(x)                                         \\\n\t(((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8197F)                              \\\n\t << BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F)\n#define BITS_LOW_RATE_TRIG_SEL_8197F                                           \\\n\t(BIT_MASK_LOW_RATE_TRIG_SEL_8197F << BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F)\n#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8197F(x)                                   \\\n\t((x) & (~BITS_LOW_RATE_TRIG_SEL_8197F))\n#define BIT_GET_LOW_RATE_TRIG_SEL_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) &                          \\\n\t BIT_MASK_LOW_RATE_TRIG_SEL_8197F)\n#define BIT_SET_LOW_RATE_TRIG_SEL_8197F(x, v)                                  \\\n\t(BIT_CLEAR_LOW_RATE_TRIG_SEL_8197F(x) | BIT_LOW_RATE_TRIG_SEL_8197F(v))\n\n#define BIT_SHIFT_HIGH_RATE_BD_IDX_8197F 8\n#define BIT_MASK_HIGH_RATE_BD_IDX_8197F 0x7f\n#define BIT_HIGH_RATE_BD_IDX_8197F(x)                                          \\\n\t(((x) & BIT_MASK_HIGH_RATE_BD_IDX_8197F)                               \\\n\t << BIT_SHIFT_HIGH_RATE_BD_IDX_8197F)\n#define BITS_HIGH_RATE_BD_IDX_8197F                                            \\\n\t(BIT_MASK_HIGH_RATE_BD_IDX_8197F << BIT_SHIFT_HIGH_RATE_BD_IDX_8197F)\n#define BIT_CLEAR_HIGH_RATE_BD_IDX_8197F(x)                                    \\\n\t((x) & (~BITS_HIGH_RATE_BD_IDX_8197F))\n#define BIT_GET_HIGH_RATE_BD_IDX_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) &                           \\\n\t BIT_MASK_HIGH_RATE_BD_IDX_8197F)\n#define BIT_SET_HIGH_RATE_BD_IDX_8197F(x, v)                                   \\\n\t(BIT_CLEAR_HIGH_RATE_BD_IDX_8197F(x) | BIT_HIGH_RATE_BD_IDX_8197F(v))\n\n#define BIT_SHIFT_LOW_RATE_BD_IDX_8197F 0\n#define BIT_MASK_LOW_RATE_BD_IDX_8197F 0x7f\n#define BIT_LOW_RATE_BD_IDX_8197F(x)                                           \\\n\t(((x) & BIT_MASK_LOW_RATE_BD_IDX_8197F)                                \\\n\t << BIT_SHIFT_LOW_RATE_BD_IDX_8197F)\n#define BITS_LOW_RATE_BD_IDX_8197F                                             \\\n\t(BIT_MASK_LOW_RATE_BD_IDX_8197F << BIT_SHIFT_LOW_RATE_BD_IDX_8197F)\n#define BIT_CLEAR_LOW_RATE_BD_IDX_8197F(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8197F))\n#define BIT_GET_LOW_RATE_BD_IDX_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8197F) &                            \\\n\t BIT_MASK_LOW_RATE_BD_IDX_8197F)\n#define BIT_SET_LOW_RATE_BD_IDX_8197F(x, v)                                    \\\n\t(BIT_CLEAR_LOW_RATE_BD_IDX_8197F(x) | BIT_LOW_RATE_BD_IDX_8197F(v))\n\n/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8197F */\n\n#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F 24\n#define BIT_MASK_RX_EMPTY_TIMER_IDX_8197F 0x7\n#define BIT_RX_EMPTY_TIMER_IDX_8197F(x)                                        \\\n\t(((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8197F)                             \\\n\t << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F)\n#define BITS_RX_EMPTY_TIMER_IDX_8197F                                          \\\n\t(BIT_MASK_RX_EMPTY_TIMER_IDX_8197F                                     \\\n\t << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F)\n#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8197F(x)                                  \\\n\t((x) & (~BITS_RX_EMPTY_TIMER_IDX_8197F))\n#define BIT_GET_RX_EMPTY_TIMER_IDX_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) &                         \\\n\t BIT_MASK_RX_EMPTY_TIMER_IDX_8197F)\n#define BIT_SET_RX_EMPTY_TIMER_IDX_8197F(x, v)                                 \\\n\t(BIT_CLEAR_RX_EMPTY_TIMER_IDX_8197F(x) |                               \\\n\t BIT_RX_EMPTY_TIMER_IDX_8197F(v))\n\n#define BIT_SHIFT_RX_AFULL_TH_IDX_8197F 20\n#define BIT_MASK_RX_AFULL_TH_IDX_8197F 0x7\n#define BIT_RX_AFULL_TH_IDX_8197F(x)                                           \\\n\t(((x) & BIT_MASK_RX_AFULL_TH_IDX_8197F)                                \\\n\t << BIT_SHIFT_RX_AFULL_TH_IDX_8197F)\n#define BITS_RX_AFULL_TH_IDX_8197F                                             \\\n\t(BIT_MASK_RX_AFULL_TH_IDX_8197F << BIT_SHIFT_RX_AFULL_TH_IDX_8197F)\n#define BIT_CLEAR_RX_AFULL_TH_IDX_8197F(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8197F))\n#define BIT_GET_RX_AFULL_TH_IDX_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8197F) &                            \\\n\t BIT_MASK_RX_AFULL_TH_IDX_8197F)\n#define BIT_SET_RX_AFULL_TH_IDX_8197F(x, v)                                    \\\n\t(BIT_CLEAR_RX_AFULL_TH_IDX_8197F(x) | BIT_RX_AFULL_TH_IDX_8197F(v))\n\n#define BIT_SHIFT_RX_HIGH_TH_IDX_8197F 16\n#define BIT_MASK_RX_HIGH_TH_IDX_8197F 0x7\n#define BIT_RX_HIGH_TH_IDX_8197F(x)                                            \\\n\t(((x) & BIT_MASK_RX_HIGH_TH_IDX_8197F)                                 \\\n\t << BIT_SHIFT_RX_HIGH_TH_IDX_8197F)\n#define BITS_RX_HIGH_TH_IDX_8197F                                              \\\n\t(BIT_MASK_RX_HIGH_TH_IDX_8197F << BIT_SHIFT_RX_HIGH_TH_IDX_8197F)\n#define BIT_CLEAR_RX_HIGH_TH_IDX_8197F(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8197F))\n#define BIT_GET_RX_HIGH_TH_IDX_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8197F) &                             \\\n\t BIT_MASK_RX_HIGH_TH_IDX_8197F)\n#define BIT_SET_RX_HIGH_TH_IDX_8197F(x, v)                                     \\\n\t(BIT_CLEAR_RX_HIGH_TH_IDX_8197F(x) | BIT_RX_HIGH_TH_IDX_8197F(v))\n\n#define BIT_SHIFT_RX_MED_TH_IDX_8197F 12\n#define BIT_MASK_RX_MED_TH_IDX_8197F 0x7\n#define BIT_RX_MED_TH_IDX_8197F(x)                                             \\\n\t(((x) & BIT_MASK_RX_MED_TH_IDX_8197F) << BIT_SHIFT_RX_MED_TH_IDX_8197F)\n#define BITS_RX_MED_TH_IDX_8197F                                               \\\n\t(BIT_MASK_RX_MED_TH_IDX_8197F << BIT_SHIFT_RX_MED_TH_IDX_8197F)\n#define BIT_CLEAR_RX_MED_TH_IDX_8197F(x) ((x) & (~BITS_RX_MED_TH_IDX_8197F))\n#define BIT_GET_RX_MED_TH_IDX_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_RX_MED_TH_IDX_8197F) & BIT_MASK_RX_MED_TH_IDX_8197F)\n#define BIT_SET_RX_MED_TH_IDX_8197F(x, v)                                      \\\n\t(BIT_CLEAR_RX_MED_TH_IDX_8197F(x) | BIT_RX_MED_TH_IDX_8197F(v))\n\n#define BIT_SHIFT_RX_LOW_TH_IDX_8197F 8\n#define BIT_MASK_RX_LOW_TH_IDX_8197F 0x7\n#define BIT_RX_LOW_TH_IDX_8197F(x)                                             \\\n\t(((x) & BIT_MASK_RX_LOW_TH_IDX_8197F) << BIT_SHIFT_RX_LOW_TH_IDX_8197F)\n#define BITS_RX_LOW_TH_IDX_8197F                                               \\\n\t(BIT_MASK_RX_LOW_TH_IDX_8197F << BIT_SHIFT_RX_LOW_TH_IDX_8197F)\n#define BIT_CLEAR_RX_LOW_TH_IDX_8197F(x) ((x) & (~BITS_RX_LOW_TH_IDX_8197F))\n#define BIT_GET_RX_LOW_TH_IDX_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8197F) & BIT_MASK_RX_LOW_TH_IDX_8197F)\n#define BIT_SET_RX_LOW_TH_IDX_8197F(x, v)                                      \\\n\t(BIT_CLEAR_RX_LOW_TH_IDX_8197F(x) | BIT_RX_LOW_TH_IDX_8197F(v))\n\n#define BIT_SHIFT_LTR_SPACE_IDX_8197F 4\n#define BIT_MASK_LTR_SPACE_IDX_8197F 0x3\n#define BIT_LTR_SPACE_IDX_8197F(x)                                             \\\n\t(((x) & BIT_MASK_LTR_SPACE_IDX_8197F) << BIT_SHIFT_LTR_SPACE_IDX_8197F)\n#define BITS_LTR_SPACE_IDX_8197F                                               \\\n\t(BIT_MASK_LTR_SPACE_IDX_8197F << BIT_SHIFT_LTR_SPACE_IDX_8197F)\n#define BIT_CLEAR_LTR_SPACE_IDX_8197F(x) ((x) & (~BITS_LTR_SPACE_IDX_8197F))\n#define BIT_GET_LTR_SPACE_IDX_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_LTR_SPACE_IDX_8197F) & BIT_MASK_LTR_SPACE_IDX_8197F)\n#define BIT_SET_LTR_SPACE_IDX_8197F(x, v)                                      \\\n\t(BIT_CLEAR_LTR_SPACE_IDX_8197F(x) | BIT_LTR_SPACE_IDX_8197F(v))\n\n#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F 0\n#define BIT_MASK_LTR_IDLE_TIMER_IDX_8197F 0x7\n#define BIT_LTR_IDLE_TIMER_IDX_8197F(x)                                        \\\n\t(((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8197F)                             \\\n\t << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F)\n#define BITS_LTR_IDLE_TIMER_IDX_8197F                                          \\\n\t(BIT_MASK_LTR_IDLE_TIMER_IDX_8197F                                     \\\n\t << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F)\n#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8197F(x)                                  \\\n\t((x) & (~BITS_LTR_IDLE_TIMER_IDX_8197F))\n#define BIT_GET_LTR_IDLE_TIMER_IDX_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) &                         \\\n\t BIT_MASK_LTR_IDLE_TIMER_IDX_8197F)\n#define BIT_SET_LTR_IDLE_TIMER_IDX_8197F(x, v)                                 \\\n\t(BIT_CLEAR_LTR_IDLE_TIMER_IDX_8197F(x) |                               \\\n\t BIT_LTR_IDLE_TIMER_IDX_8197F(v))\n\n/* 2 REG_LTR_IDLE_LATENCY_V1_8197F */\n\n#define BIT_SHIFT_LTR_IDLE_L_8197F 0\n#define BIT_MASK_LTR_IDLE_L_8197F 0xffffffffL\n#define BIT_LTR_IDLE_L_8197F(x)                                                \\\n\t(((x) & BIT_MASK_LTR_IDLE_L_8197F) << BIT_SHIFT_LTR_IDLE_L_8197F)\n#define BITS_LTR_IDLE_L_8197F                                                  \\\n\t(BIT_MASK_LTR_IDLE_L_8197F << BIT_SHIFT_LTR_IDLE_L_8197F)\n#define BIT_CLEAR_LTR_IDLE_L_8197F(x) ((x) & (~BITS_LTR_IDLE_L_8197F))\n#define BIT_GET_LTR_IDLE_L_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_LTR_IDLE_L_8197F) & BIT_MASK_LTR_IDLE_L_8197F)\n#define BIT_SET_LTR_IDLE_L_8197F(x, v)                                         \\\n\t(BIT_CLEAR_LTR_IDLE_L_8197F(x) | BIT_LTR_IDLE_L_8197F(v))\n\n/* 2 REG_LTR_ACTIVE_LATENCY_V1_8197F */\n\n#define BIT_SHIFT_LTR_ACT_L_8197F 0\n#define BIT_MASK_LTR_ACT_L_8197F 0xffffffffL\n#define BIT_LTR_ACT_L_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_LTR_ACT_L_8197F) << BIT_SHIFT_LTR_ACT_L_8197F)\n#define BITS_LTR_ACT_L_8197F                                                   \\\n\t(BIT_MASK_LTR_ACT_L_8197F << BIT_SHIFT_LTR_ACT_L_8197F)\n#define BIT_CLEAR_LTR_ACT_L_8197F(x) ((x) & (~BITS_LTR_ACT_L_8197F))\n#define BIT_GET_LTR_ACT_L_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_LTR_ACT_L_8197F) & BIT_MASK_LTR_ACT_L_8197F)\n#define BIT_SET_LTR_ACT_L_8197F(x, v)                                          \\\n\t(BIT_CLEAR_LTR_ACT_L_8197F(x) | BIT_LTR_ACT_L_8197F(v))\n\n/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8197F */\n#define BIT_APPEND_MACID_IN_RESP_EN_8197F BIT(50)\n#define BIT_ADDR2_MATCH_EN_8197F BIT(49)\n#define BIT_ANTTRN_EN_8197F BIT(48)\n\n#define BIT_SHIFT_TRAIN_STA_ADDR_8197F 0\n#define BIT_MASK_TRAIN_STA_ADDR_8197F 0xffffffffffffL\n#define BIT_TRAIN_STA_ADDR_8197F(x)                                            \\\n\t(((x) & BIT_MASK_TRAIN_STA_ADDR_8197F)                                 \\\n\t << BIT_SHIFT_TRAIN_STA_ADDR_8197F)\n#define BITS_TRAIN_STA_ADDR_8197F                                              \\\n\t(BIT_MASK_TRAIN_STA_ADDR_8197F << BIT_SHIFT_TRAIN_STA_ADDR_8197F)\n#define BIT_CLEAR_TRAIN_STA_ADDR_8197F(x) ((x) & (~BITS_TRAIN_STA_ADDR_8197F))\n#define BIT_GET_TRAIN_STA_ADDR_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8197F) &                             \\\n\t BIT_MASK_TRAIN_STA_ADDR_8197F)\n#define BIT_SET_TRAIN_STA_ADDR_8197F(x, v)                                     \\\n\t(BIT_CLEAR_TRAIN_STA_ADDR_8197F(x) | BIT_TRAIN_STA_ADDR_8197F(v))\n\n/* 2 REG_RSVD_0X7B4_8197F */\n\n/* 2 REG_WMAC_PKTCNT_RWD_8197F */\n\n#define BIT_SHIFT_PKTCNT_BSSIDMAP_8197F 4\n#define BIT_MASK_PKTCNT_BSSIDMAP_8197F 0xf\n#define BIT_PKTCNT_BSSIDMAP_8197F(x)                                           \\\n\t(((x) & BIT_MASK_PKTCNT_BSSIDMAP_8197F)                                \\\n\t << BIT_SHIFT_PKTCNT_BSSIDMAP_8197F)\n#define BITS_PKTCNT_BSSIDMAP_8197F                                             \\\n\t(BIT_MASK_PKTCNT_BSSIDMAP_8197F << BIT_SHIFT_PKTCNT_BSSIDMAP_8197F)\n#define BIT_CLEAR_PKTCNT_BSSIDMAP_8197F(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8197F))\n#define BIT_GET_PKTCNT_BSSIDMAP_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) &                            \\\n\t BIT_MASK_PKTCNT_BSSIDMAP_8197F)\n#define BIT_SET_PKTCNT_BSSIDMAP_8197F(x, v)                                    \\\n\t(BIT_CLEAR_PKTCNT_BSSIDMAP_8197F(x) | BIT_PKTCNT_BSSIDMAP_8197F(v))\n\n#define BIT_PKTCNT_CNTRST_8197F BIT(1)\n#define BIT_PKTCNT_CNTEN_8197F BIT(0)\n\n/* 2 REG_WMAC_PKTCNT_CTRL_8197F */\n#define BIT_WMAC_PKTCNT_TRST_8197F BIT(9)\n#define BIT_WMAC_PKTCNT_FEN_8197F BIT(8)\n\n#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F 0\n#define BIT_MASK_WMAC_PKTCNT_CFGAD_8197F 0xff\n#define BIT_WMAC_PKTCNT_CFGAD_8197F(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8197F)                              \\\n\t << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F)\n#define BITS_WMAC_PKTCNT_CFGAD_8197F                                           \\\n\t(BIT_MASK_WMAC_PKTCNT_CFGAD_8197F << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F)\n#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8197F(x)                                   \\\n\t((x) & (~BITS_WMAC_PKTCNT_CFGAD_8197F))\n#define BIT_GET_WMAC_PKTCNT_CFGAD_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) &                          \\\n\t BIT_MASK_WMAC_PKTCNT_CFGAD_8197F)\n#define BIT_SET_WMAC_PKTCNT_CFGAD_8197F(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_PKTCNT_CFGAD_8197F(x) | BIT_WMAC_PKTCNT_CFGAD_8197F(v))\n\n/* 2 REG_IQ_DUMP_8197F */\n\n#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F (64 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F 0xffffffffL\n#define BIT_R_WMAC_MATCH_REF_MAC_8197F(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F)                           \\\n\t << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F)\n#define BITS_R_WMAC_MATCH_REF_MAC_8197F                                        \\\n\t(BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F                                   \\\n\t << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F)\n#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8197F(x)                                \\\n\t((x) & (~BITS_R_WMAC_MATCH_REF_MAC_8197F))\n#define BIT_GET_R_WMAC_MATCH_REF_MAC_8197F(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) &                       \\\n\t BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F)\n#define BIT_SET_R_WMAC_MATCH_REF_MAC_8197F(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8197F(x) |                             \\\n\t BIT_R_WMAC_MATCH_REF_MAC_8197F(v))\n\n#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_WMAC_MASK_LA_MAC_8197F 0xffffffffL\n#define BIT_R_WMAC_MASK_LA_MAC_8197F(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8197F)                             \\\n\t << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F)\n#define BITS_R_WMAC_MASK_LA_MAC_8197F                                          \\\n\t(BIT_MASK_R_WMAC_MASK_LA_MAC_8197F                                     \\\n\t << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F)\n#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x)                                  \\\n\t((x) & (~BITS_R_WMAC_MASK_LA_MAC_8197F))\n#define BIT_GET_R_WMAC_MASK_LA_MAC_8197F(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) &                         \\\n\t BIT_MASK_R_WMAC_MASK_LA_MAC_8197F)\n#define BIT_SET_R_WMAC_MASK_LA_MAC_8197F(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x) |                               \\\n\t BIT_R_WMAC_MASK_LA_MAC_8197F(v))\n\n#define BIT_SHIFT_DUMP_OK_ADDR_V1_8197F 15\n#define BIT_MASK_DUMP_OK_ADDR_V1_8197F 0x1ffff\n#define BIT_DUMP_OK_ADDR_V1_8197F(x)                                           \\\n\t(((x) & BIT_MASK_DUMP_OK_ADDR_V1_8197F)                                \\\n\t << BIT_SHIFT_DUMP_OK_ADDR_V1_8197F)\n#define BITS_DUMP_OK_ADDR_V1_8197F                                             \\\n\t(BIT_MASK_DUMP_OK_ADDR_V1_8197F << BIT_SHIFT_DUMP_OK_ADDR_V1_8197F)\n#define BIT_CLEAR_DUMP_OK_ADDR_V1_8197F(x) ((x) & (~BITS_DUMP_OK_ADDR_V1_8197F))\n#define BIT_GET_DUMP_OK_ADDR_V1_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_DUMP_OK_ADDR_V1_8197F) &                            \\\n\t BIT_MASK_DUMP_OK_ADDR_V1_8197F)\n#define BIT_SET_DUMP_OK_ADDR_V1_8197F(x, v)                                    \\\n\t(BIT_CLEAR_DUMP_OK_ADDR_V1_8197F(x) | BIT_DUMP_OK_ADDR_V1_8197F(v))\n\n#define BIT_SHIFT_R_TRIG_TIME_SEL_8197F 8\n#define BIT_MASK_R_TRIG_TIME_SEL_8197F 0x7f\n#define BIT_R_TRIG_TIME_SEL_8197F(x)                                           \\\n\t(((x) & BIT_MASK_R_TRIG_TIME_SEL_8197F)                                \\\n\t << BIT_SHIFT_R_TRIG_TIME_SEL_8197F)\n#define BITS_R_TRIG_TIME_SEL_8197F                                             \\\n\t(BIT_MASK_R_TRIG_TIME_SEL_8197F << BIT_SHIFT_R_TRIG_TIME_SEL_8197F)\n#define BIT_CLEAR_R_TRIG_TIME_SEL_8197F(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8197F))\n#define BIT_GET_R_TRIG_TIME_SEL_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8197F) &                            \\\n\t BIT_MASK_R_TRIG_TIME_SEL_8197F)\n#define BIT_SET_R_TRIG_TIME_SEL_8197F(x, v)                                    \\\n\t(BIT_CLEAR_R_TRIG_TIME_SEL_8197F(x) | BIT_R_TRIG_TIME_SEL_8197F(v))\n\n#define BIT_SHIFT_R_MAC_TRIG_SEL_8197F 6\n#define BIT_MASK_R_MAC_TRIG_SEL_8197F 0x3\n#define BIT_R_MAC_TRIG_SEL_8197F(x)                                            \\\n\t(((x) & BIT_MASK_R_MAC_TRIG_SEL_8197F)                                 \\\n\t << BIT_SHIFT_R_MAC_TRIG_SEL_8197F)\n#define BITS_R_MAC_TRIG_SEL_8197F                                              \\\n\t(BIT_MASK_R_MAC_TRIG_SEL_8197F << BIT_SHIFT_R_MAC_TRIG_SEL_8197F)\n#define BIT_CLEAR_R_MAC_TRIG_SEL_8197F(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8197F))\n#define BIT_GET_R_MAC_TRIG_SEL_8197F(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8197F) &                             \\\n\t BIT_MASK_R_MAC_TRIG_SEL_8197F)\n#define BIT_SET_R_MAC_TRIG_SEL_8197F(x, v)                                     \\\n\t(BIT_CLEAR_R_MAC_TRIG_SEL_8197F(x) | BIT_R_MAC_TRIG_SEL_8197F(v))\n\n#define BIT_MAC_TRIG_REG_8197F BIT(5)\n\n#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F 3\n#define BIT_MASK_R_LEVEL_PULSE_SEL_8197F 0x3\n#define BIT_R_LEVEL_PULSE_SEL_8197F(x)                                         \\\n\t(((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8197F)                              \\\n\t << BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F)\n#define BITS_R_LEVEL_PULSE_SEL_8197F                                           \\\n\t(BIT_MASK_R_LEVEL_PULSE_SEL_8197F << BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F)\n#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8197F(x)                                   \\\n\t((x) & (~BITS_R_LEVEL_PULSE_SEL_8197F))\n#define BIT_GET_R_LEVEL_PULSE_SEL_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) &                          \\\n\t BIT_MASK_R_LEVEL_PULSE_SEL_8197F)\n#define BIT_SET_R_LEVEL_PULSE_SEL_8197F(x, v)                                  \\\n\t(BIT_CLEAR_R_LEVEL_PULSE_SEL_8197F(x) | BIT_R_LEVEL_PULSE_SEL_8197F(v))\n\n#define BIT_EN_LA_MAC_8197F BIT(2)\n#define BIT_R_EN_IQDUMP_8197F BIT(1)\n#define BIT_R_IQDATA_DUMP_8197F BIT(0)\n\n/* 2 REG_WMAC_FTM_CTL_8197F */\n#define BIT_RXFTM_TXACK_SC_8197F BIT(6)\n#define BIT_RXFTM_TXACK_BW_8197F BIT(5)\n#define BIT_RXFTM_EN_8197F BIT(3)\n#define BIT_RXFTMREQ_BYDRV_8197F BIT(2)\n#define BIT_RXFTMREQ_EN_8197F BIT(1)\n#define BIT_FTM_EN_8197F BIT(0)\n\n/* 2 REG_IQ_DUMP_EXT_8197F */\n\n#define BIT_SHIFT_R_TIME_UNIT_SEL_8197F 0\n#define BIT_MASK_R_TIME_UNIT_SEL_8197F 0x7\n#define BIT_R_TIME_UNIT_SEL_8197F(x)                                           \\\n\t(((x) & BIT_MASK_R_TIME_UNIT_SEL_8197F)                                \\\n\t << BIT_SHIFT_R_TIME_UNIT_SEL_8197F)\n#define BITS_R_TIME_UNIT_SEL_8197F                                             \\\n\t(BIT_MASK_R_TIME_UNIT_SEL_8197F << BIT_SHIFT_R_TIME_UNIT_SEL_8197F)\n#define BIT_CLEAR_R_TIME_UNIT_SEL_8197F(x) ((x) & (~BITS_R_TIME_UNIT_SEL_8197F))\n#define BIT_GET_R_TIME_UNIT_SEL_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_TIME_UNIT_SEL_8197F) &                            \\\n\t BIT_MASK_R_TIME_UNIT_SEL_8197F)\n#define BIT_SET_R_TIME_UNIT_SEL_8197F(x, v)                                    \\\n\t(BIT_CLEAR_R_TIME_UNIT_SEL_8197F(x) | BIT_R_TIME_UNIT_SEL_8197F(v))\n\n/* 2 REG_OFDM_CCK_LEN_MASK_8197F */\n\n#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F (64 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_WMAC_RX_FIL_LEN_8197F 0xffff\n#define BIT_R_WMAC_RX_FIL_LEN_8197F(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8197F)                              \\\n\t << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F)\n#define BITS_R_WMAC_RX_FIL_LEN_8197F                                           \\\n\t(BIT_MASK_R_WMAC_RX_FIL_LEN_8197F << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F)\n#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_8197F(x)                                   \\\n\t((x) & (~BITS_R_WMAC_RX_FIL_LEN_8197F))\n#define BIT_GET_R_WMAC_RX_FIL_LEN_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) &                          \\\n\t BIT_MASK_R_WMAC_RX_FIL_LEN_8197F)\n#define BIT_SET_R_WMAC_RX_FIL_LEN_8197F(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_RX_FIL_LEN_8197F(x) | BIT_R_WMAC_RX_FIL_LEN_8197F(v))\n\n#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F (56 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F 0xff\n#define BIT_R_WMAC_RXFIFO_FULL_TH_8197F(x)                                     \\\n\t(((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F)                          \\\n\t << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F)\n#define BITS_R_WMAC_RXFIFO_FULL_TH_8197F                                       \\\n\t(BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F                                  \\\n\t << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F)\n#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8197F(x)                               \\\n\t((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_8197F))\n#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8197F(x)                                 \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) &                      \\\n\t BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F)\n#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_8197F(x, v)                              \\\n\t(BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8197F(x) |                            \\\n\t BIT_R_WMAC_RXFIFO_FULL_TH_8197F(v))\n\n#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_8197F BIT(55)\n#define BIT_R_WMAC_RXRST_DLY_8197F BIT(54)\n#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_8197F BIT(53)\n#define BIT_R_WMAC_SRCH_TXRPT_UA1_8197F BIT(52)\n#define BIT_R_WMAC_SRCH_TXRPT_TYPE_8197F BIT(51)\n#define BIT_R_WMAC_NDP_RST_8197F BIT(50)\n#define BIT_R_WMAC_POWINT_EN_8197F BIT(49)\n#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_8197F BIT(48)\n#define BIT_R_WMAC_SRCH_TXRPT_MID_8197F BIT(47)\n#define BIT_R_WMAC_PFIN_TOEN_8197F BIT(46)\n#define BIT_R_WMAC_FIL_SECERR_8197F BIT(45)\n#define BIT_R_WMAC_FIL_CTLPKTLEN_8197F BIT(44)\n#define BIT_R_WMAC_FIL_FCTYPE_8197F BIT(43)\n#define BIT_R_WMAC_FIL_FCPROVER_8197F BIT(42)\n#define BIT_R_WMAC_PHYSTS_SNIF_8197F BIT(41)\n#define BIT_R_WMAC_PHYSTS_PLCP_8197F BIT(40)\n#define BIT_R_MAC_TCR_VBONF_RD_8197F BIT(39)\n#define BIT_R_WMAC_TCR_MPAR_NDP_8197F BIT(38)\n#define BIT_R_WMAC_NDP_FILTER_8197F BIT(37)\n#define BIT_R_WMAC_RXLEN_SEL_8197F BIT(36)\n#define BIT_R_WMAC_RXLEN_SEL1_8197F BIT(35)\n#define BIT_R_OFDM_FILTER_8197F BIT(34)\n#define BIT_R_WMAC_CHK_OFDM_LEN_8197F BIT(33)\n#define BIT_R_WMAC_CHK_CCK_LEN_8197F BIT(32)\n\n#define BIT_SHIFT_R_OFDM_LEN_8197F 26\n#define BIT_MASK_R_OFDM_LEN_8197F 0x3f\n#define BIT_R_OFDM_LEN_8197F(x)                                                \\\n\t(((x) & BIT_MASK_R_OFDM_LEN_8197F) << BIT_SHIFT_R_OFDM_LEN_8197F)\n#define BITS_R_OFDM_LEN_8197F                                                  \\\n\t(BIT_MASK_R_OFDM_LEN_8197F << BIT_SHIFT_R_OFDM_LEN_8197F)\n#define BIT_CLEAR_R_OFDM_LEN_8197F(x) ((x) & (~BITS_R_OFDM_LEN_8197F))\n#define BIT_GET_R_OFDM_LEN_8197F(x)                                            \\\n\t(((x) >> BIT_SHIFT_R_OFDM_LEN_8197F) & BIT_MASK_R_OFDM_LEN_8197F)\n#define BIT_SET_R_OFDM_LEN_8197F(x, v)                                         \\\n\t(BIT_CLEAR_R_OFDM_LEN_8197F(x) | BIT_R_OFDM_LEN_8197F(v))\n\n#define BIT_SHIFT_R_CCK_LEN_8197F 0\n#define BIT_MASK_R_CCK_LEN_8197F 0xffff\n#define BIT_R_CCK_LEN_8197F(x)                                                 \\\n\t(((x) & BIT_MASK_R_CCK_LEN_8197F) << BIT_SHIFT_R_CCK_LEN_8197F)\n#define BITS_R_CCK_LEN_8197F                                                   \\\n\t(BIT_MASK_R_CCK_LEN_8197F << BIT_SHIFT_R_CCK_LEN_8197F)\n#define BIT_CLEAR_R_CCK_LEN_8197F(x) ((x) & (~BITS_R_CCK_LEN_8197F))\n#define BIT_GET_R_CCK_LEN_8197F(x)                                             \\\n\t(((x) >> BIT_SHIFT_R_CCK_LEN_8197F) & BIT_MASK_R_CCK_LEN_8197F)\n#define BIT_SET_R_CCK_LEN_8197F(x, v)                                          \\\n\t(BIT_CLEAR_R_CCK_LEN_8197F(x) | BIT_R_CCK_LEN_8197F(v))\n\n/* 2 REG_RX_FILTER_FUNCTION_8197F */\n#define BIT_R_WMAC_RXHANG_EN_8197F BIT(15)\n#define BIT_R_WMAC_MHRDDY_LATCH_8197F BIT(14)\n#define BIT_R_MHRDDY_CLR_8197F BIT(13)\n#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8197F BIT(12)\n#define BIT_R_WMAC_DIS_VHT_PLCP_CHK_MU_8197F BIT(11)\n#define BIT_R_CHK_DELIMIT_LEN_8197F BIT(10)\n#define BIT_R_REAPTER_ADDR_MATCH_8197F BIT(9)\n#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8197F BIT(8)\n#define BIT_R_LATCH_MACHRDY_8197F BIT(7)\n#define BIT_R_WMAC_RXFIL_REND_8197F BIT(6)\n#define BIT_R_WMAC_MPDURDY_CLR_8197F BIT(5)\n#define BIT_R_WMAC_CLRRXSEC_8197F BIT(4)\n#define BIT_R_WMAC_RXFIL_RDEL_8197F BIT(3)\n#define BIT_R_WMAC_RXFIL_FCSE_8197F BIT(2)\n#define BIT_R_WMAC_RXFIL_MESH_DEL_8197F BIT(1)\n#define BIT_R_WMAC_RXFIL_MASKM_8197F BIT(0)\n\n/* 2 REG_NDP_SIG_8197F */\n\n#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F 0\n#define BIT_MASK_R_WMAC_TXNDP_SIGB_8197F 0x1fffff\n#define BIT_R_WMAC_TXNDP_SIGB_8197F(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8197F)                              \\\n\t << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F)\n#define BITS_R_WMAC_TXNDP_SIGB_8197F                                           \\\n\t(BIT_MASK_R_WMAC_TXNDP_SIGB_8197F << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F)\n#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8197F(x)                                   \\\n\t((x) & (~BITS_R_WMAC_TXNDP_SIGB_8197F))\n#define BIT_GET_R_WMAC_TXNDP_SIGB_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) &                          \\\n\t BIT_MASK_R_WMAC_TXNDP_SIGB_8197F)\n#define BIT_SET_R_WMAC_TXNDP_SIGB_8197F(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_TXNDP_SIGB_8197F(x) | BIT_R_WMAC_TXNDP_SIGB_8197F(v))\n\n/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8197F */\n\n#define BIT_SHIFT_R_MAC_DEBUG_8197F (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_MAC_DEBUG_8197F 0xffffffffL\n#define BIT_R_MAC_DEBUG_8197F(x)                                               \\\n\t(((x) & BIT_MASK_R_MAC_DEBUG_8197F) << BIT_SHIFT_R_MAC_DEBUG_8197F)\n#define BITS_R_MAC_DEBUG_8197F                                                 \\\n\t(BIT_MASK_R_MAC_DEBUG_8197F << BIT_SHIFT_R_MAC_DEBUG_8197F)\n#define BIT_CLEAR_R_MAC_DEBUG_8197F(x) ((x) & (~BITS_R_MAC_DEBUG_8197F))\n#define BIT_GET_R_MAC_DEBUG_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_R_MAC_DEBUG_8197F) & BIT_MASK_R_MAC_DEBUG_8197F)\n#define BIT_SET_R_MAC_DEBUG_8197F(x, v)                                        \\\n\t(BIT_CLEAR_R_MAC_DEBUG_8197F(x) | BIT_R_MAC_DEBUG_8197F(v))\n\n#define BIT_SHIFT_R_MAC_DBG_SHIFT_8197F 8\n#define BIT_MASK_R_MAC_DBG_SHIFT_8197F 0x7\n#define BIT_R_MAC_DBG_SHIFT_8197F(x)                                           \\\n\t(((x) & BIT_MASK_R_MAC_DBG_SHIFT_8197F)                                \\\n\t << BIT_SHIFT_R_MAC_DBG_SHIFT_8197F)\n#define BITS_R_MAC_DBG_SHIFT_8197F                                             \\\n\t(BIT_MASK_R_MAC_DBG_SHIFT_8197F << BIT_SHIFT_R_MAC_DBG_SHIFT_8197F)\n#define BIT_CLEAR_R_MAC_DBG_SHIFT_8197F(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8197F))\n#define BIT_GET_R_MAC_DBG_SHIFT_8197F(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) &                            \\\n\t BIT_MASK_R_MAC_DBG_SHIFT_8197F)\n#define BIT_SET_R_MAC_DBG_SHIFT_8197F(x, v)                                    \\\n\t(BIT_CLEAR_R_MAC_DBG_SHIFT_8197F(x) | BIT_R_MAC_DBG_SHIFT_8197F(v))\n\n#define BIT_SHIFT_R_MAC_DBG_SEL_8197F 0\n#define BIT_MASK_R_MAC_DBG_SEL_8197F 0x3\n#define BIT_R_MAC_DBG_SEL_8197F(x)                                             \\\n\t(((x) & BIT_MASK_R_MAC_DBG_SEL_8197F) << BIT_SHIFT_R_MAC_DBG_SEL_8197F)\n#define BITS_R_MAC_DBG_SEL_8197F                                               \\\n\t(BIT_MASK_R_MAC_DBG_SEL_8197F << BIT_SHIFT_R_MAC_DBG_SEL_8197F)\n#define BIT_CLEAR_R_MAC_DBG_SEL_8197F(x) ((x) & (~BITS_R_MAC_DBG_SEL_8197F))\n#define BIT_GET_R_MAC_DBG_SEL_8197F(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8197F) & BIT_MASK_R_MAC_DBG_SEL_8197F)\n#define BIT_SET_R_MAC_DBG_SEL_8197F(x, v)                                      \\\n\t(BIT_CLEAR_R_MAC_DBG_SEL_8197F(x) | BIT_R_MAC_DBG_SEL_8197F(v))\n\n/* 2 REG_SEC_OPT_V2_8197F */\n#define BIT_MASK_IV_8197F BIT(18)\n#define BIT_EIVL_ENDIAN_8197F BIT(17)\n#define BIT_EIVH_ENDIAN_8197F BIT(16)\n\n#define BIT_SHIFT_BT_TIME_CNT_8197F 0\n#define BIT_MASK_BT_TIME_CNT_8197F 0xff\n#define BIT_BT_TIME_CNT_8197F(x)                                               \\\n\t(((x) & BIT_MASK_BT_TIME_CNT_8197F) << BIT_SHIFT_BT_TIME_CNT_8197F)\n#define BITS_BT_TIME_CNT_8197F                                                 \\\n\t(BIT_MASK_BT_TIME_CNT_8197F << BIT_SHIFT_BT_TIME_CNT_8197F)\n#define BIT_CLEAR_BT_TIME_CNT_8197F(x) ((x) & (~BITS_BT_TIME_CNT_8197F))\n#define BIT_GET_BT_TIME_CNT_8197F(x)                                           \\\n\t(((x) >> BIT_SHIFT_BT_TIME_CNT_8197F) & BIT_MASK_BT_TIME_CNT_8197F)\n#define BIT_SET_BT_TIME_CNT_8197F(x, v)                                        \\\n\t(BIT_CLEAR_BT_TIME_CNT_8197F(x) | BIT_BT_TIME_CNT_8197F(v))\n\n/* 2 REG_RTS_ADDRESS_0_8197F */\n\n/* 2 REG_RTS_ADDRESS_1_8197F */\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8197F */\n#define BIT_LTECOEX_ACCESS_START_V1_8197F BIT(31)\n#define BIT_LTECOEX_WRITE_MODE_V1_8197F BIT(30)\n#define BIT_LTECOEX_READY_BIT_V1_8197F BIT(29)\n\n#define BIT_SHIFT_WRITE_BYTE_EN_V1_8197F 16\n#define BIT_MASK_WRITE_BYTE_EN_V1_8197F 0xf\n#define BIT_WRITE_BYTE_EN_V1_8197F(x)                                          \\\n\t(((x) & BIT_MASK_WRITE_BYTE_EN_V1_8197F)                               \\\n\t << BIT_SHIFT_WRITE_BYTE_EN_V1_8197F)\n#define BITS_WRITE_BYTE_EN_V1_8197F                                            \\\n\t(BIT_MASK_WRITE_BYTE_EN_V1_8197F << BIT_SHIFT_WRITE_BYTE_EN_V1_8197F)\n#define BIT_CLEAR_WRITE_BYTE_EN_V1_8197F(x)                                    \\\n\t((x) & (~BITS_WRITE_BYTE_EN_V1_8197F))\n#define BIT_GET_WRITE_BYTE_EN_V1_8197F(x)                                      \\\n\t(((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8197F) &                           \\\n\t BIT_MASK_WRITE_BYTE_EN_V1_8197F)\n#define BIT_SET_WRITE_BYTE_EN_V1_8197F(x, v)                                   \\\n\t(BIT_CLEAR_WRITE_BYTE_EN_V1_8197F(x) | BIT_WRITE_BYTE_EN_V1_8197F(v))\n\n#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8197F 0\n#define BIT_MASK_LTECOEX_REG_ADDR_V1_8197F 0xffff\n#define BIT_LTECOEX_REG_ADDR_V1_8197F(x)                                       \\\n\t(((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8197F)                            \\\n\t << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8197F)\n#define BITS_LTECOEX_REG_ADDR_V1_8197F                                         \\\n\t(BIT_MASK_LTECOEX_REG_ADDR_V1_8197F                                    \\\n\t << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8197F)\n#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8197F(x)                                 \\\n\t((x) & (~BITS_LTECOEX_REG_ADDR_V1_8197F))\n#define BIT_GET_LTECOEX_REG_ADDR_V1_8197F(x)                                   \\\n\t(((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8197F) &                        \\\n\t BIT_MASK_LTECOEX_REG_ADDR_V1_8197F)\n#define BIT_SET_LTECOEX_REG_ADDR_V1_8197F(x, v)                                \\\n\t(BIT_CLEAR_LTECOEX_REG_ADDR_V1_8197F(x) |                              \\\n\t BIT_LTECOEX_REG_ADDR_V1_8197F(v))\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8197F */\n\n#define BIT_SHIFT_LTECOEX_W_DATA_V1_8197F 0\n#define BIT_MASK_LTECOEX_W_DATA_V1_8197F 0xffffffffL\n#define BIT_LTECOEX_W_DATA_V1_8197F(x)                                         \\\n\t(((x) & BIT_MASK_LTECOEX_W_DATA_V1_8197F)                              \\\n\t << BIT_SHIFT_LTECOEX_W_DATA_V1_8197F)\n#define BITS_LTECOEX_W_DATA_V1_8197F                                           \\\n\t(BIT_MASK_LTECOEX_W_DATA_V1_8197F << BIT_SHIFT_LTECOEX_W_DATA_V1_8197F)\n#define BIT_CLEAR_LTECOEX_W_DATA_V1_8197F(x)                                   \\\n\t((x) & (~BITS_LTECOEX_W_DATA_V1_8197F))\n#define BIT_GET_LTECOEX_W_DATA_V1_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8197F) &                          \\\n\t BIT_MASK_LTECOEX_W_DATA_V1_8197F)\n#define BIT_SET_LTECOEX_W_DATA_V1_8197F(x, v)                                  \\\n\t(BIT_CLEAR_LTECOEX_W_DATA_V1_8197F(x) | BIT_LTECOEX_W_DATA_V1_8197F(v))\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8197F */\n\n#define BIT_SHIFT_LTECOEX_R_DATA_V1_8197F 0\n#define BIT_MASK_LTECOEX_R_DATA_V1_8197F 0xffffffffL\n#define BIT_LTECOEX_R_DATA_V1_8197F(x)                                         \\\n\t(((x) & BIT_MASK_LTECOEX_R_DATA_V1_8197F)                              \\\n\t << BIT_SHIFT_LTECOEX_R_DATA_V1_8197F)\n#define BITS_LTECOEX_R_DATA_V1_8197F                                           \\\n\t(BIT_MASK_LTECOEX_R_DATA_V1_8197F << BIT_SHIFT_LTECOEX_R_DATA_V1_8197F)\n#define BIT_CLEAR_LTECOEX_R_DATA_V1_8197F(x)                                   \\\n\t((x) & (~BITS_LTECOEX_R_DATA_V1_8197F))\n#define BIT_GET_LTECOEX_R_DATA_V1_8197F(x)                                     \\\n\t(((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8197F) &                          \\\n\t BIT_MASK_LTECOEX_R_DATA_V1_8197F)\n#define BIT_SET_LTECOEX_R_DATA_V1_8197F(x, v)                                  \\\n\t(BIT_CLEAR_LTECOEX_R_DATA_V1_8197F(x) | BIT_LTECOEX_R_DATA_V1_8197F(v))\n\n/* 2 REG_NOT_VALID_8197F */\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_bit_8814b.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef __INC_HALMAC_BIT_8814B_H\n#define __INC_HALMAC_BIT_8814B_H\n\n#define CPU_OPT_WIDTH 0x1F\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_SYS_ISO_CTRL_8814B */\n#define BIT_PWC_EV12V_8814B BIT(15)\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_PA33V_EN_8814B BIT(13)\n#define BIT_PA12V_EN_8814B BIT(12)\n#define BIT_UA33V_EN_8814B BIT(11)\n#define BIT_UA12V_EN_8814B BIT(10)\n#define BIT_ISO_RFDIO_8814B BIT(9)\n#define BIT_ISO_EB2CORE_8814B BIT(8)\n#define BIT_ISO_DIOE_8814B BIT(7)\n#define BIT_ISO_WLPON2PP_8814B BIT(6)\n#define BIT_ISO_IP2MAC_WA2PP_8814B BIT(5)\n#define BIT_ISO_PD2CORE_8814B BIT(4)\n#define BIT_ISO_PA2PCIE_8814B BIT(3)\n#define BIT_ISO_UD2CORE_8814B BIT(2)\n#define BIT_ISO_UA2USB_8814B BIT(1)\n#define BIT_ISO_WD2PP_8814B BIT(0)\n\n/* 2 REG_SYS_FUNC_EN_8814B */\n#define BIT_FEN_MREGEN_8814B BIT(15)\n#define BIT_FEN_HWPDN_8814B BIT(14)\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_FEN_ELDR_8814B BIT(12)\n#define BIT_FEN_DCORE_8814B BIT(11)\n#define BIT_FEN_CPUEN_8814B BIT(10)\n#define BIT_FEN_DIOE_8814B BIT(9)\n#define BIT_FEN_PCIED_8814B BIT(8)\n#define BIT_FEN_PPLL_8814B BIT(7)\n#define BIT_FEN_PCIEA_8814B BIT(6)\n#define BIT_FEN_DIO_PCIE_8814B BIT(5)\n#define BIT_FEN_USBD_8814B BIT(4)\n#define BIT_FEN_UPLL_8814B BIT(3)\n#define BIT_FEN_USBA_8814B BIT(2)\n#define BIT_FEN_BB_GLB_RSTN_8814B BIT(1)\n#define BIT_FEN_BBRSTB_8814B BIT(0)\n\n/* 2 REG_SYS_PW_CTRL_8814B */\n#define BIT_SOP_EABM_8814B BIT(31)\n#define BIT_SOP_ACKF_8814B BIT(30)\n#define BIT_SOP_ERCK_8814B BIT(29)\n#define BIT_SOP_ESWR_8814B BIT(28)\n#define BIT_SOP_PWMM_8814B BIT(27)\n#define BIT_SOP_EECK_8814B BIT(26)\n#define BIT_SOP_EXTL_8814B BIT(24)\n#define BIT_SYM_OP_RING_12M_8814B BIT(22)\n#define BIT_ROP_SWPR_8814B BIT(21)\n#define BIT_DIS_HW_LPLDM_8814B BIT(20)\n#define BIT_OPT_SWRST_WLMCU_8814B BIT(19)\n#define BIT_RDY_SYSPWR_8814B BIT(17)\n#define BIT_EN_WLON_8814B BIT(16)\n#define BIT_APDM_HPDN_8814B BIT(15)\n#define BIT_AFSM_PCIE_SUS_EN_8814B BIT(12)\n#define BIT_AFSM_WLSUS_EN_8814B BIT(11)\n#define BIT_APFM_SWLPS_8814B BIT(10)\n#define BIT_APFM_OFFMAC_8814B BIT(9)\n#define BIT_APFN_ONMAC_8814B BIT(8)\n#define BIT_CHIP_PDN_EN_8814B BIT(7)\n#define BIT_RDY_MACDIS_8814B BIT(6)\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_PFM_WOWL_8814B BIT(3)\n#define BIT_PFM_LDKP_8814B BIT(2)\n#define BIT_WL_HCI_ALD_8814B BIT(1)\n#define BIT_PFM_LDALL_8814B BIT(0)\n\n/* 2 REG_SYS_CLK_CTRL_8814B */\n#define BIT_DATA_CPU_CLK_EN_8814B BIT(15)\n#define BIT_CPU_CLK_EN_8814B BIT(14)\n#define BIT_SYMREG_CLK_EN_8814B BIT(13)\n#define BIT_HCI_CLK_EN_8814B BIT(12)\n#define BIT_MAC_CLK_EN_8814B BIT(11)\n#define BIT_SEC_CLK_EN_8814B BIT(10)\n#define BIT_PHY_SSC_RSTB_8814B BIT(9)\n#define BIT_EXT_32K_EN_8814B BIT(8)\n#define BIT_WL_CLK_TEST_8814B BIT(7)\n#define BIT_OP_SPS_PWM_EN_8814B BIT(6)\n#define BIT_LOADER_CLK_EN_8814B BIT(5)\n#define BIT_MACSLP_8814B BIT(4)\n#define BIT_WAKEPAD_EN_8814B BIT(3)\n#define BIT_ROMD16V_EN_8814B BIT(2)\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_CNTD16V_EN_8814B BIT(0)\n\n/* 2 REG_SYS_EEPROM_CTRL_8814B */\n\n#define BIT_SHIFT_VPDIDX_8814B 8\n#define BIT_MASK_VPDIDX_8814B 0xff\n#define BIT_VPDIDX_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_VPDIDX_8814B) << BIT_SHIFT_VPDIDX_8814B)\n#define BITS_VPDIDX_8814B (BIT_MASK_VPDIDX_8814B << BIT_SHIFT_VPDIDX_8814B)\n#define BIT_CLEAR_VPDIDX_8814B(x) ((x) & (~BITS_VPDIDX_8814B))\n#define BIT_GET_VPDIDX_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_VPDIDX_8814B) & BIT_MASK_VPDIDX_8814B)\n#define BIT_SET_VPDIDX_8814B(x, v)                                             \\\n\t(BIT_CLEAR_VPDIDX_8814B(x) | BIT_VPDIDX_8814B(v))\n\n#define BIT_SHIFT_EEM1_0_8814B 6\n#define BIT_MASK_EEM1_0_8814B 0x3\n#define BIT_EEM1_0_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_EEM1_0_8814B) << BIT_SHIFT_EEM1_0_8814B)\n#define BITS_EEM1_0_8814B (BIT_MASK_EEM1_0_8814B << BIT_SHIFT_EEM1_0_8814B)\n#define BIT_CLEAR_EEM1_0_8814B(x) ((x) & (~BITS_EEM1_0_8814B))\n#define BIT_GET_EEM1_0_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_EEM1_0_8814B) & BIT_MASK_EEM1_0_8814B)\n#define BIT_SET_EEM1_0_8814B(x, v)                                             \\\n\t(BIT_CLEAR_EEM1_0_8814B(x) | BIT_EEM1_0_8814B(v))\n\n#define BIT_AUTOLOAD_SUS_8814B BIT(5)\n#define BIT_EERPOMSEL_8814B BIT(4)\n#define BIT_EECS_V1_8814B BIT(3)\n#define BIT_EESK_V1_8814B BIT(2)\n#define BIT_EEDI_V1_8814B BIT(1)\n#define BIT_EEDO_V1_8814B BIT(0)\n\n/* 2 REG_EE_VPD_8814B */\n\n#define BIT_SHIFT_VPD_DATA_8814B 0\n#define BIT_MASK_VPD_DATA_8814B 0xffffffffL\n#define BIT_VPD_DATA_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_VPD_DATA_8814B) << BIT_SHIFT_VPD_DATA_8814B)\n#define BITS_VPD_DATA_8814B                                                    \\\n\t(BIT_MASK_VPD_DATA_8814B << BIT_SHIFT_VPD_DATA_8814B)\n#define BIT_CLEAR_VPD_DATA_8814B(x) ((x) & (~BITS_VPD_DATA_8814B))\n#define BIT_GET_VPD_DATA_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_VPD_DATA_8814B) & BIT_MASK_VPD_DATA_8814B)\n#define BIT_SET_VPD_DATA_8814B(x, v)                                           \\\n\t(BIT_CLEAR_VPD_DATA_8814B(x) | BIT_VPD_DATA_8814B(v))\n\n/* 2 REG_SYS_SWR_CTRL1_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_CTRL_SPS_PWM_FREQ_8814B BIT(10)\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_DISABLE_OPEN_SPS_LDO_8814B BIT(8)\n#define BIT_MAC_ID_EN_8814B BIT(7)\n#define BIT_WL_CTRL_XTAL_CADJ_8814B BIT(6)\n#define BIT_AFE_BGEN_PCIE_OP_8814B BIT(2)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_SYS_SWR_CTRL2_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_SYS_SWR_CTRL3_8814B */\n#define BIT_SPS18_OCP_DIS_8814B BIT(31)\n\n#define BIT_SHIFT_SPS18_OCP_TH_8814B 16\n#define BIT_MASK_SPS18_OCP_TH_8814B 0x7fff\n#define BIT_SPS18_OCP_TH_8814B(x)                                              \\\n\t(((x) & BIT_MASK_SPS18_OCP_TH_8814B) << BIT_SHIFT_SPS18_OCP_TH_8814B)\n#define BITS_SPS18_OCP_TH_8814B                                                \\\n\t(BIT_MASK_SPS18_OCP_TH_8814B << BIT_SHIFT_SPS18_OCP_TH_8814B)\n#define BIT_CLEAR_SPS18_OCP_TH_8814B(x) ((x) & (~BITS_SPS18_OCP_TH_8814B))\n#define BIT_GET_SPS18_OCP_TH_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SPS18_OCP_TH_8814B) & BIT_MASK_SPS18_OCP_TH_8814B)\n#define BIT_SET_SPS18_OCP_TH_8814B(x, v)                                       \\\n\t(BIT_CLEAR_SPS18_OCP_TH_8814B(x) | BIT_SPS18_OCP_TH_8814B(v))\n\n#define BIT_SHIFT_OCP_WINDOW_8814B 0\n#define BIT_MASK_OCP_WINDOW_8814B 0xffff\n#define BIT_OCP_WINDOW_8814B(x)                                                \\\n\t(((x) & BIT_MASK_OCP_WINDOW_8814B) << BIT_SHIFT_OCP_WINDOW_8814B)\n#define BITS_OCP_WINDOW_8814B                                                  \\\n\t(BIT_MASK_OCP_WINDOW_8814B << BIT_SHIFT_OCP_WINDOW_8814B)\n#define BIT_CLEAR_OCP_WINDOW_8814B(x) ((x) & (~BITS_OCP_WINDOW_8814B))\n#define BIT_GET_OCP_WINDOW_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_OCP_WINDOW_8814B) & BIT_MASK_OCP_WINDOW_8814B)\n#define BIT_SET_OCP_WINDOW_8814B(x, v)                                         \\\n\t(BIT_CLEAR_OCP_WINDOW_8814B(x) | BIT_OCP_WINDOW_8814B(v))\n\n/* 2 REG_RSV_CTRL_8814B */\n\n#define BIT_SHIFT_HREG_DBG_V1_8814B 12\n#define BIT_MASK_HREG_DBG_V1_8814B 0xfff\n#define BIT_HREG_DBG_V1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_HREG_DBG_V1_8814B) << BIT_SHIFT_HREG_DBG_V1_8814B)\n#define BITS_HREG_DBG_V1_8814B                                                 \\\n\t(BIT_MASK_HREG_DBG_V1_8814B << BIT_SHIFT_HREG_DBG_V1_8814B)\n#define BIT_CLEAR_HREG_DBG_V1_8814B(x) ((x) & (~BITS_HREG_DBG_V1_8814B))\n#define BIT_GET_HREG_DBG_V1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HREG_DBG_V1_8814B) & BIT_MASK_HREG_DBG_V1_8814B)\n#define BIT_SET_HREG_DBG_V1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_HREG_DBG_V1_8814B(x) | BIT_HREG_DBG_V1_8814B(v))\n\n#define BIT_WLMCUIOIF_8814B BIT(8)\n#define BIT_LOCK_ALL_EN_8814B BIT(7)\n#define BIT_R_DIS_PRST_8814B BIT(6)\n#define BIT_WLOCK_1C_B6_8814B BIT(5)\n#define BIT_WLOCK_40_8814B BIT(4)\n#define BIT_WLOCK_08_8814B BIT(3)\n#define BIT_WLOCK_04_8814B BIT(2)\n#define BIT_WLOCK_00_8814B BIT(1)\n#define BIT_WLOCK_ALL_8814B BIT(0)\n\n/* 2 REG_RF_CTRL_8814B */\n#define BIT_RF_SDMRSTB_8814B BIT(2)\n#define BIT_RF_RSTB_8814B BIT(1)\n#define BIT_RF_EN_8814B BIT(0)\n\n/* 2 REG_AFE_LDO_CTRL_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_CPHY_LDO_CL_EN_8814B BIT(19)\n#define BIT_CPHY_LDO_OK_8814B BIT(18)\n#define BIT_PCIE_CALIB_EN_8814B BIT(17)\n#define BIT_LDH12_EN_8814B BIT(16)\n#define BIT_DATA_CPU_PWC_8814B BIT(15)\n#define BIT_WLBBOFF_BIG_PWC_EN_8814B BIT(14)\n#define BIT_WLBBOFF_SMALL_PWC_EN_8814B BIT(13)\n#define BIT_WLMACOFF_BIG_PWC_EN_8814B BIT(12)\n#define BIT_WLPON_PWC_EN_8814B BIT(11)\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_LDOV12W_EN_8814B BIT(8)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_AFE_CTRL1_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_MAC_CLK_SEL_8814B 20\n#define BIT_MASK_MAC_CLK_SEL_8814B 0x3\n#define BIT_MAC_CLK_SEL_8814B(x)                                               \\\n\t(((x) & BIT_MASK_MAC_CLK_SEL_8814B) << BIT_SHIFT_MAC_CLK_SEL_8814B)\n#define BITS_MAC_CLK_SEL_8814B                                                 \\\n\t(BIT_MASK_MAC_CLK_SEL_8814B << BIT_SHIFT_MAC_CLK_SEL_8814B)\n#define BIT_CLEAR_MAC_CLK_SEL_8814B(x) ((x) & (~BITS_MAC_CLK_SEL_8814B))\n#define BIT_GET_MAC_CLK_SEL_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_MAC_CLK_SEL_8814B) & BIT_MASK_MAC_CLK_SEL_8814B)\n#define BIT_SET_MAC_CLK_SEL_8814B(x, v)                                        \\\n\t(BIT_CLEAR_MAC_CLK_SEL_8814B(x) | BIT_MAC_CLK_SEL_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_ANAPARSW_POW_MAC_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_ENB_LDO_DIODE_L_8814B BIT(3)\n#define BIT_POW_LDO15_8814B BIT(2)\n#define BIT_POW_SW_8814B BIT(1)\n#define BIT_POW_LDO14_8814B BIT(0)\n\n/* 2 REG_ANAPARLDO_POW_MAC_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_LDOE25_POW_L_8814B BIT(0)\n\n/* 2 REG_ANAPAR_POW_MAC_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_POW_PC_LDO3_8814B BIT(5)\n#define BIT_POW_PC_LDO2_8814B BIT(4)\n#define BIT_POW_PC_LDO1_8814B BIT(3)\n#define BIT_POW_PC_LDO0_8814B BIT(2)\n#define BIT_POW_PLL_V1_8814B BIT(1)\n#define BIT_POW_POWER_CUT_8814B BIT(0)\n\n/* 2 REG_ANAPAR_POW_XTAL_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_POW_XTAL_8814B BIT(1)\n#define BIT_POW_BG_8814B BIT(0)\n\n/* 2 REG_ANAPARLDO_MAC_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_EFUSE_CTRL_8814B */\n#define BIT_EF_FLAG_8814B BIT(31)\n\n#define BIT_SHIFT_EF_PGPD_8814B 28\n#define BIT_MASK_EF_PGPD_8814B 0x7\n#define BIT_EF_PGPD_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_EF_PGPD_8814B) << BIT_SHIFT_EF_PGPD_8814B)\n#define BITS_EF_PGPD_8814B (BIT_MASK_EF_PGPD_8814B << BIT_SHIFT_EF_PGPD_8814B)\n#define BIT_CLEAR_EF_PGPD_8814B(x) ((x) & (~BITS_EF_PGPD_8814B))\n#define BIT_GET_EF_PGPD_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_PGPD_8814B) & BIT_MASK_EF_PGPD_8814B)\n#define BIT_SET_EF_PGPD_8814B(x, v)                                            \\\n\t(BIT_CLEAR_EF_PGPD_8814B(x) | BIT_EF_PGPD_8814B(v))\n\n#define BIT_SHIFT_EF_RDT_8814B 24\n#define BIT_MASK_EF_RDT_8814B 0xf\n#define BIT_EF_RDT_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_EF_RDT_8814B) << BIT_SHIFT_EF_RDT_8814B)\n#define BITS_EF_RDT_8814B (BIT_MASK_EF_RDT_8814B << BIT_SHIFT_EF_RDT_8814B)\n#define BIT_CLEAR_EF_RDT_8814B(x) ((x) & (~BITS_EF_RDT_8814B))\n#define BIT_GET_EF_RDT_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_EF_RDT_8814B) & BIT_MASK_EF_RDT_8814B)\n#define BIT_SET_EF_RDT_8814B(x, v)                                             \\\n\t(BIT_CLEAR_EF_RDT_8814B(x) | BIT_EF_RDT_8814B(v))\n\n#define BIT_SHIFT_EF_PGTS_8814B 20\n#define BIT_MASK_EF_PGTS_8814B 0xf\n#define BIT_EF_PGTS_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_EF_PGTS_8814B) << BIT_SHIFT_EF_PGTS_8814B)\n#define BITS_EF_PGTS_8814B (BIT_MASK_EF_PGTS_8814B << BIT_SHIFT_EF_PGTS_8814B)\n#define BIT_CLEAR_EF_PGTS_8814B(x) ((x) & (~BITS_EF_PGTS_8814B))\n#define BIT_GET_EF_PGTS_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_PGTS_8814B) & BIT_MASK_EF_PGTS_8814B)\n#define BIT_SET_EF_PGTS_8814B(x, v)                                            \\\n\t(BIT_CLEAR_EF_PGTS_8814B(x) | BIT_EF_PGTS_8814B(v))\n\n#define BIT_EF_PDWN_8814B BIT(19)\n#define BIT_EF_ALDEN_8814B BIT(18)\n\n#define BIT_SHIFT_EF_ADDR_8814B 8\n#define BIT_MASK_EF_ADDR_8814B 0x3ff\n#define BIT_EF_ADDR_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_EF_ADDR_8814B) << BIT_SHIFT_EF_ADDR_8814B)\n#define BITS_EF_ADDR_8814B (BIT_MASK_EF_ADDR_8814B << BIT_SHIFT_EF_ADDR_8814B)\n#define BIT_CLEAR_EF_ADDR_8814B(x) ((x) & (~BITS_EF_ADDR_8814B))\n#define BIT_GET_EF_ADDR_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_ADDR_8814B) & BIT_MASK_EF_ADDR_8814B)\n#define BIT_SET_EF_ADDR_8814B(x, v)                                            \\\n\t(BIT_CLEAR_EF_ADDR_8814B(x) | BIT_EF_ADDR_8814B(v))\n\n#define BIT_SHIFT_EF_DATA_8814B 0\n#define BIT_MASK_EF_DATA_8814B 0xff\n#define BIT_EF_DATA_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_EF_DATA_8814B) << BIT_SHIFT_EF_DATA_8814B)\n#define BITS_EF_DATA_8814B (BIT_MASK_EF_DATA_8814B << BIT_SHIFT_EF_DATA_8814B)\n#define BIT_CLEAR_EF_DATA_8814B(x) ((x) & (~BITS_EF_DATA_8814B))\n#define BIT_GET_EF_DATA_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_DATA_8814B) & BIT_MASK_EF_DATA_8814B)\n#define BIT_SET_EF_DATA_8814B(x, v)                                            \\\n\t(BIT_CLEAR_EF_DATA_8814B(x) | BIT_EF_DATA_8814B(v))\n\n/* 2 REG_LDO_EFUSE_CTRL_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_EF_CRES_SEL_8814B BIT(26)\n\n#define BIT_SHIFT_EF_SCAN_START_V1_8814B 16\n#define BIT_MASK_EF_SCAN_START_V1_8814B 0x3ff\n#define BIT_EF_SCAN_START_V1_8814B(x)                                          \\\n\t(((x) & BIT_MASK_EF_SCAN_START_V1_8814B)                               \\\n\t << BIT_SHIFT_EF_SCAN_START_V1_8814B)\n#define BITS_EF_SCAN_START_V1_8814B                                            \\\n\t(BIT_MASK_EF_SCAN_START_V1_8814B << BIT_SHIFT_EF_SCAN_START_V1_8814B)\n#define BIT_CLEAR_EF_SCAN_START_V1_8814B(x)                                    \\\n\t((x) & (~BITS_EF_SCAN_START_V1_8814B))\n#define BIT_GET_EF_SCAN_START_V1_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_EF_SCAN_START_V1_8814B) &                           \\\n\t BIT_MASK_EF_SCAN_START_V1_8814B)\n#define BIT_SET_EF_SCAN_START_V1_8814B(x, v)                                   \\\n\t(BIT_CLEAR_EF_SCAN_START_V1_8814B(x) | BIT_EF_SCAN_START_V1_8814B(v))\n\n#define BIT_SHIFT_EF_SCAN_END_8814B 12\n#define BIT_MASK_EF_SCAN_END_8814B 0xf\n#define BIT_EF_SCAN_END_8814B(x)                                               \\\n\t(((x) & BIT_MASK_EF_SCAN_END_8814B) << BIT_SHIFT_EF_SCAN_END_8814B)\n#define BITS_EF_SCAN_END_8814B                                                 \\\n\t(BIT_MASK_EF_SCAN_END_8814B << BIT_SHIFT_EF_SCAN_END_8814B)\n#define BIT_CLEAR_EF_SCAN_END_8814B(x) ((x) & (~BITS_EF_SCAN_END_8814B))\n#define BIT_GET_EF_SCAN_END_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_EF_SCAN_END_8814B) & BIT_MASK_EF_SCAN_END_8814B)\n#define BIT_SET_EF_SCAN_END_8814B(x, v)                                        \\\n\t(BIT_CLEAR_EF_SCAN_END_8814B(x) | BIT_EF_SCAN_END_8814B(v))\n\n#define BIT_EF_PD_DIS_8814B BIT(11)\n\n#define BIT_SHIFT_EF_CELL_SEL_8814B 8\n#define BIT_MASK_EF_CELL_SEL_8814B 0x3\n#define BIT_EF_CELL_SEL_8814B(x)                                               \\\n\t(((x) & BIT_MASK_EF_CELL_SEL_8814B) << BIT_SHIFT_EF_CELL_SEL_8814B)\n#define BITS_EF_CELL_SEL_8814B                                                 \\\n\t(BIT_MASK_EF_CELL_SEL_8814B << BIT_SHIFT_EF_CELL_SEL_8814B)\n#define BIT_CLEAR_EF_CELL_SEL_8814B(x) ((x) & (~BITS_EF_CELL_SEL_8814B))\n#define BIT_GET_EF_CELL_SEL_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_EF_CELL_SEL_8814B) & BIT_MASK_EF_CELL_SEL_8814B)\n#define BIT_SET_EF_CELL_SEL_8814B(x, v)                                        \\\n\t(BIT_CLEAR_EF_CELL_SEL_8814B(x) | BIT_EF_CELL_SEL_8814B(v))\n\n#define BIT_EF_TRPT_8814B BIT(7)\n\n#define BIT_SHIFT_EF_TTHD_8814B 0\n#define BIT_MASK_EF_TTHD_8814B 0x7f\n#define BIT_EF_TTHD_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_EF_TTHD_8814B) << BIT_SHIFT_EF_TTHD_8814B)\n#define BITS_EF_TTHD_8814B (BIT_MASK_EF_TTHD_8814B << BIT_SHIFT_EF_TTHD_8814B)\n#define BIT_CLEAR_EF_TTHD_8814B(x) ((x) & (~BITS_EF_TTHD_8814B))\n#define BIT_GET_EF_TTHD_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_TTHD_8814B) & BIT_MASK_EF_TTHD_8814B)\n#define BIT_SET_EF_TTHD_8814B(x, v)                                            \\\n\t(BIT_CLEAR_EF_TTHD_8814B(x) | BIT_EF_TTHD_8814B(v))\n\n/* 2 REG_PWR_OPTION_CTRL_8814B */\n\n#define BIT_SHIFT_DBG_SEL_V1_8814B 16\n#define BIT_MASK_DBG_SEL_V1_8814B 0xff\n#define BIT_DBG_SEL_V1_8814B(x)                                                \\\n\t(((x) & BIT_MASK_DBG_SEL_V1_8814B) << BIT_SHIFT_DBG_SEL_V1_8814B)\n#define BITS_DBG_SEL_V1_8814B                                                  \\\n\t(BIT_MASK_DBG_SEL_V1_8814B << BIT_SHIFT_DBG_SEL_V1_8814B)\n#define BIT_CLEAR_DBG_SEL_V1_8814B(x) ((x) & (~BITS_DBG_SEL_V1_8814B))\n#define BIT_GET_DBG_SEL_V1_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DBG_SEL_V1_8814B) & BIT_MASK_DBG_SEL_V1_8814B)\n#define BIT_SET_DBG_SEL_V1_8814B(x, v)                                         \\\n\t(BIT_CLEAR_DBG_SEL_V1_8814B(x) | BIT_DBG_SEL_V1_8814B(v))\n\n#define BIT_SHIFT_DBG_SEL_BYTE_8814B 14\n#define BIT_MASK_DBG_SEL_BYTE_8814B 0x3\n#define BIT_DBG_SEL_BYTE_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DBG_SEL_BYTE_8814B) << BIT_SHIFT_DBG_SEL_BYTE_8814B)\n#define BITS_DBG_SEL_BYTE_8814B                                                \\\n\t(BIT_MASK_DBG_SEL_BYTE_8814B << BIT_SHIFT_DBG_SEL_BYTE_8814B)\n#define BIT_CLEAR_DBG_SEL_BYTE_8814B(x) ((x) & (~BITS_DBG_SEL_BYTE_8814B))\n#define BIT_GET_DBG_SEL_BYTE_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DBG_SEL_BYTE_8814B) & BIT_MASK_DBG_SEL_BYTE_8814B)\n#define BIT_SET_DBG_SEL_BYTE_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DBG_SEL_BYTE_8814B(x) | BIT_DBG_SEL_BYTE_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_SYSON_DBG_PAD_E2_8814B BIT(11)\n#define BIT_SYSON_LED_PAD_E2_8814B BIT(10)\n#define BIT_SYSON_GPEE_PAD_E2_8814B BIT(9)\n#define BIT_SYSON_PCI_PAD_E2_8814B BIT(8)\n#define BIT_AUTO_SW_LDO_VOL_EN_8814B BIT(7)\n\n#define BIT_SHIFT_SYSON_SPS0WWV_WT_8814B 4\n#define BIT_MASK_SYSON_SPS0WWV_WT_8814B 0x3\n#define BIT_SYSON_SPS0WWV_WT_8814B(x)                                          \\\n\t(((x) & BIT_MASK_SYSON_SPS0WWV_WT_8814B)                               \\\n\t << BIT_SHIFT_SYSON_SPS0WWV_WT_8814B)\n#define BITS_SYSON_SPS0WWV_WT_8814B                                            \\\n\t(BIT_MASK_SYSON_SPS0WWV_WT_8814B << BIT_SHIFT_SYSON_SPS0WWV_WT_8814B)\n#define BIT_CLEAR_SYSON_SPS0WWV_WT_8814B(x)                                    \\\n\t((x) & (~BITS_SYSON_SPS0WWV_WT_8814B))\n#define BIT_GET_SYSON_SPS0WWV_WT_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8814B) &                           \\\n\t BIT_MASK_SYSON_SPS0WWV_WT_8814B)\n#define BIT_SET_SYSON_SPS0WWV_WT_8814B(x, v)                                   \\\n\t(BIT_CLEAR_SYSON_SPS0WWV_WT_8814B(x) | BIT_SYSON_SPS0WWV_WT_8814B(v))\n\n#define BIT_SHIFT_SYSON_SPS0LDO_WT_8814B 2\n#define BIT_MASK_SYSON_SPS0LDO_WT_8814B 0x3\n#define BIT_SYSON_SPS0LDO_WT_8814B(x)                                          \\\n\t(((x) & BIT_MASK_SYSON_SPS0LDO_WT_8814B)                               \\\n\t << BIT_SHIFT_SYSON_SPS0LDO_WT_8814B)\n#define BITS_SYSON_SPS0LDO_WT_8814B                                            \\\n\t(BIT_MASK_SYSON_SPS0LDO_WT_8814B << BIT_SHIFT_SYSON_SPS0LDO_WT_8814B)\n#define BIT_CLEAR_SYSON_SPS0LDO_WT_8814B(x)                                    \\\n\t((x) & (~BITS_SYSON_SPS0LDO_WT_8814B))\n#define BIT_GET_SYSON_SPS0LDO_WT_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8814B) &                           \\\n\t BIT_MASK_SYSON_SPS0LDO_WT_8814B)\n#define BIT_SET_SYSON_SPS0LDO_WT_8814B(x, v)                                   \\\n\t(BIT_CLEAR_SYSON_SPS0LDO_WT_8814B(x) | BIT_SYSON_SPS0LDO_WT_8814B(v))\n\n#define BIT_SHIFT_SYSON_RCLK_SCALE_8814B 0\n#define BIT_MASK_SYSON_RCLK_SCALE_8814B 0x3\n#define BIT_SYSON_RCLK_SCALE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_SYSON_RCLK_SCALE_8814B)                               \\\n\t << BIT_SHIFT_SYSON_RCLK_SCALE_8814B)\n#define BITS_SYSON_RCLK_SCALE_8814B                                            \\\n\t(BIT_MASK_SYSON_RCLK_SCALE_8814B << BIT_SHIFT_SYSON_RCLK_SCALE_8814B)\n#define BIT_CLEAR_SYSON_RCLK_SCALE_8814B(x)                                    \\\n\t((x) & (~BITS_SYSON_RCLK_SCALE_8814B))\n#define BIT_GET_SYSON_RCLK_SCALE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8814B) &                           \\\n\t BIT_MASK_SYSON_RCLK_SCALE_8814B)\n#define BIT_SET_SYSON_RCLK_SCALE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_SYSON_RCLK_SCALE_8814B(x) | BIT_SYSON_RCLK_SCALE_8814B(v))\n\n/* 2 REG_CAL_TIMER_8814B */\n\n#define BIT_SHIFT_MATCH_CNT_8814B 8\n#define BIT_MASK_MATCH_CNT_8814B 0xff\n#define BIT_MATCH_CNT_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_MATCH_CNT_8814B) << BIT_SHIFT_MATCH_CNT_8814B)\n#define BITS_MATCH_CNT_8814B                                                   \\\n\t(BIT_MASK_MATCH_CNT_8814B << BIT_SHIFT_MATCH_CNT_8814B)\n#define BIT_CLEAR_MATCH_CNT_8814B(x) ((x) & (~BITS_MATCH_CNT_8814B))\n#define BIT_GET_MATCH_CNT_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_MATCH_CNT_8814B) & BIT_MASK_MATCH_CNT_8814B)\n#define BIT_SET_MATCH_CNT_8814B(x, v)                                          \\\n\t(BIT_CLEAR_MATCH_CNT_8814B(x) | BIT_MATCH_CNT_8814B(v))\n\n#define BIT_SHIFT_CAL_SCAL_8814B 0\n#define BIT_MASK_CAL_SCAL_8814B 0xff\n#define BIT_CAL_SCAL_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_CAL_SCAL_8814B) << BIT_SHIFT_CAL_SCAL_8814B)\n#define BITS_CAL_SCAL_8814B                                                    \\\n\t(BIT_MASK_CAL_SCAL_8814B << BIT_SHIFT_CAL_SCAL_8814B)\n#define BIT_CLEAR_CAL_SCAL_8814B(x) ((x) & (~BITS_CAL_SCAL_8814B))\n#define BIT_GET_CAL_SCAL_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_CAL_SCAL_8814B) & BIT_MASK_CAL_SCAL_8814B)\n#define BIT_SET_CAL_SCAL_8814B(x, v)                                           \\\n\t(BIT_CLEAR_CAL_SCAL_8814B(x) | BIT_CAL_SCAL_8814B(v))\n\n/* 2 REG_ACLK_MON_8814B */\n\n#define BIT_SHIFT_RCLK_MON_8814B 5\n#define BIT_MASK_RCLK_MON_8814B 0x7ff\n#define BIT_RCLK_MON_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_RCLK_MON_8814B) << BIT_SHIFT_RCLK_MON_8814B)\n#define BITS_RCLK_MON_8814B                                                    \\\n\t(BIT_MASK_RCLK_MON_8814B << BIT_SHIFT_RCLK_MON_8814B)\n#define BIT_CLEAR_RCLK_MON_8814B(x) ((x) & (~BITS_RCLK_MON_8814B))\n#define BIT_GET_RCLK_MON_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RCLK_MON_8814B) & BIT_MASK_RCLK_MON_8814B)\n#define BIT_SET_RCLK_MON_8814B(x, v)                                           \\\n\t(BIT_CLEAR_RCLK_MON_8814B(x) | BIT_RCLK_MON_8814B(v))\n\n#define BIT_CAL_EN_8814B BIT(4)\n\n#define BIT_SHIFT_DPSTU_8814B 2\n#define BIT_MASK_DPSTU_8814B 0x3\n#define BIT_DPSTU_8814B(x)                                                     \\\n\t(((x) & BIT_MASK_DPSTU_8814B) << BIT_SHIFT_DPSTU_8814B)\n#define BITS_DPSTU_8814B (BIT_MASK_DPSTU_8814B << BIT_SHIFT_DPSTU_8814B)\n#define BIT_CLEAR_DPSTU_8814B(x) ((x) & (~BITS_DPSTU_8814B))\n#define BIT_GET_DPSTU_8814B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DPSTU_8814B) & BIT_MASK_DPSTU_8814B)\n#define BIT_SET_DPSTU_8814B(x, v)                                              \\\n\t(BIT_CLEAR_DPSTU_8814B(x) | BIT_DPSTU_8814B(v))\n\n#define BIT_SUS_16X_8814B BIT(1)\n\n/* 2 REG_GPIO_MUXCFG_8814B */\n#define BIT_EN_DATACPU_GPIO2_8814B BIT(24)\n#define BIT_EN_DATACPU_GPIO_8814B BIT(23)\n#define BIT_EN_DATACPU_UART_8814B BIT(22)\n#define BIT_DATACPU_FSPI_EN_8814B BIT(21)\n#define BIT_EN_GPIO8_UART_OUT_8814B BIT(20)\n#define BIT_FSPI_EN_8814B BIT(19)\n#define BIT_WL_RTS_EXT_32K_SEL_8814B BIT(18)\n#define BIT_WLGP_SPI_EN_8814B BIT(16)\n#define BIT_SIC_LBK_8814B BIT(15)\n#define BIT_ENHTP_8814B BIT(14)\n#define BIT_ENSIC_8814B BIT(12)\n#define BIT_SIC_SWRST_8814B BIT(11)\n#define BIT_PO_WIFI_PTA_PINS_8814B BIT(10)\n#define BIT_PO_BT_PTA_PINS_8814B BIT(9)\n#define BIT_ENUART_8814B BIT(8)\n\n#define BIT_SHIFT_BTMODE_8814B 6\n#define BIT_MASK_BTMODE_8814B 0x3\n#define BIT_BTMODE_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_BTMODE_8814B) << BIT_SHIFT_BTMODE_8814B)\n#define BITS_BTMODE_8814B (BIT_MASK_BTMODE_8814B << BIT_SHIFT_BTMODE_8814B)\n#define BIT_CLEAR_BTMODE_8814B(x) ((x) & (~BITS_BTMODE_8814B))\n#define BIT_GET_BTMODE_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_BTMODE_8814B) & BIT_MASK_BTMODE_8814B)\n#define BIT_SET_BTMODE_8814B(x, v)                                             \\\n\t(BIT_CLEAR_BTMODE_8814B(x) | BIT_BTMODE_8814B(v))\n\n#define BIT_ENBT_8814B BIT(5)\n#define BIT_EROM_EN_8814B BIT(4)\n#define BIT_WLRFE_6_7_EN_8814B BIT(3)\n#define BIT_WLRFE_4_5_EN_8814B BIT(2)\n\n#define BIT_SHIFT_GPIOSEL_8814B 0\n#define BIT_MASK_GPIOSEL_8814B 0x3\n#define BIT_GPIOSEL_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_GPIOSEL_8814B) << BIT_SHIFT_GPIOSEL_8814B)\n#define BITS_GPIOSEL_8814B (BIT_MASK_GPIOSEL_8814B << BIT_SHIFT_GPIOSEL_8814B)\n#define BIT_CLEAR_GPIOSEL_8814B(x) ((x) & (~BITS_GPIOSEL_8814B))\n#define BIT_GET_GPIOSEL_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_GPIOSEL_8814B) & BIT_MASK_GPIOSEL_8814B)\n#define BIT_SET_GPIOSEL_8814B(x, v)                                            \\\n\t(BIT_CLEAR_GPIOSEL_8814B(x) | BIT_GPIOSEL_8814B(v))\n\n/* 2 REG_GPIO_PIN_CTRL_8814B */\n\n#define BIT_SHIFT_GPIO_MOD_7_TO_0_8814B 24\n#define BIT_MASK_GPIO_MOD_7_TO_0_8814B 0xff\n#define BIT_GPIO_MOD_7_TO_0_8814B(x)                                           \\\n\t(((x) & BIT_MASK_GPIO_MOD_7_TO_0_8814B)                                \\\n\t << BIT_SHIFT_GPIO_MOD_7_TO_0_8814B)\n#define BITS_GPIO_MOD_7_TO_0_8814B                                             \\\n\t(BIT_MASK_GPIO_MOD_7_TO_0_8814B << BIT_SHIFT_GPIO_MOD_7_TO_0_8814B)\n#define BIT_CLEAR_GPIO_MOD_7_TO_0_8814B(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8814B))\n#define BIT_GET_GPIO_MOD_7_TO_0_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8814B) &                            \\\n\t BIT_MASK_GPIO_MOD_7_TO_0_8814B)\n#define BIT_SET_GPIO_MOD_7_TO_0_8814B(x, v)                                    \\\n\t(BIT_CLEAR_GPIO_MOD_7_TO_0_8814B(x) | BIT_GPIO_MOD_7_TO_0_8814B(v))\n\n#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B 16\n#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B 0xff\n#define BIT_GPIO_IO_SEL_7_TO_0_8814B(x)                                        \\\n\t(((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B)                             \\\n\t << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B)\n#define BITS_GPIO_IO_SEL_7_TO_0_8814B                                          \\\n\t(BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B                                     \\\n\t << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B)\n#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8814B(x)                                  \\\n\t((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8814B))\n#define BIT_GET_GPIO_IO_SEL_7_TO_0_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B) &                         \\\n\t BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B)\n#define BIT_SET_GPIO_IO_SEL_7_TO_0_8814B(x, v)                                 \\\n\t(BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8814B(x) |                               \\\n\t BIT_GPIO_IO_SEL_7_TO_0_8814B(v))\n\n#define BIT_SHIFT_GPIO_OUT_7_TO_0_8814B 8\n#define BIT_MASK_GPIO_OUT_7_TO_0_8814B 0xff\n#define BIT_GPIO_OUT_7_TO_0_8814B(x)                                           \\\n\t(((x) & BIT_MASK_GPIO_OUT_7_TO_0_8814B)                                \\\n\t << BIT_SHIFT_GPIO_OUT_7_TO_0_8814B)\n#define BITS_GPIO_OUT_7_TO_0_8814B                                             \\\n\t(BIT_MASK_GPIO_OUT_7_TO_0_8814B << BIT_SHIFT_GPIO_OUT_7_TO_0_8814B)\n#define BIT_CLEAR_GPIO_OUT_7_TO_0_8814B(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8814B))\n#define BIT_GET_GPIO_OUT_7_TO_0_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8814B) &                            \\\n\t BIT_MASK_GPIO_OUT_7_TO_0_8814B)\n#define BIT_SET_GPIO_OUT_7_TO_0_8814B(x, v)                                    \\\n\t(BIT_CLEAR_GPIO_OUT_7_TO_0_8814B(x) | BIT_GPIO_OUT_7_TO_0_8814B(v))\n\n#define BIT_SHIFT_GPIO_IN_7_TO_0_8814B 0\n#define BIT_MASK_GPIO_IN_7_TO_0_8814B 0xff\n#define BIT_GPIO_IN_7_TO_0_8814B(x)                                            \\\n\t(((x) & BIT_MASK_GPIO_IN_7_TO_0_8814B)                                 \\\n\t << BIT_SHIFT_GPIO_IN_7_TO_0_8814B)\n#define BITS_GPIO_IN_7_TO_0_8814B                                              \\\n\t(BIT_MASK_GPIO_IN_7_TO_0_8814B << BIT_SHIFT_GPIO_IN_7_TO_0_8814B)\n#define BIT_CLEAR_GPIO_IN_7_TO_0_8814B(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8814B))\n#define BIT_GET_GPIO_IN_7_TO_0_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8814B) &                             \\\n\t BIT_MASK_GPIO_IN_7_TO_0_8814B)\n#define BIT_SET_GPIO_IN_7_TO_0_8814B(x, v)                                     \\\n\t(BIT_CLEAR_GPIO_IN_7_TO_0_8814B(x) | BIT_GPIO_IN_7_TO_0_8814B(v))\n\n/* 2 REG_GPIO_INTM_8814B */\n\n#define BIT_SHIFT_MUXDBG_SEL_8814B 30\n#define BIT_MASK_MUXDBG_SEL_8814B 0x3\n#define BIT_MUXDBG_SEL_8814B(x)                                                \\\n\t(((x) & BIT_MASK_MUXDBG_SEL_8814B) << BIT_SHIFT_MUXDBG_SEL_8814B)\n#define BITS_MUXDBG_SEL_8814B                                                  \\\n\t(BIT_MASK_MUXDBG_SEL_8814B << BIT_SHIFT_MUXDBG_SEL_8814B)\n#define BIT_CLEAR_MUXDBG_SEL_8814B(x) ((x) & (~BITS_MUXDBG_SEL_8814B))\n#define BIT_GET_MUXDBG_SEL_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_MUXDBG_SEL_8814B) & BIT_MASK_MUXDBG_SEL_8814B)\n#define BIT_SET_MUXDBG_SEL_8814B(x, v)                                         \\\n\t(BIT_CLEAR_MUXDBG_SEL_8814B(x) | BIT_MUXDBG_SEL_8814B(v))\n\n#define BIT_EXTWOL_SEL_8814B BIT(17)\n#define BIT_EXTWOL_EN_8814B BIT(16)\n#define BIT_GPIOF_INT_MD_8814B BIT(15)\n#define BIT_GPIOE_INT_MD_8814B BIT(14)\n#define BIT_GPIOD_INT_MD_8814B BIT(13)\n#define BIT_GPIOF_INT_MD_8814B BIT(15)\n#define BIT_GPIOE_INT_MD_8814B BIT(14)\n#define BIT_GPIOD_INT_MD_8814B BIT(13)\n#define BIT_GPIOC_INT_MD_8814B BIT(12)\n#define BIT_GPIOB_INT_MD_8814B BIT(11)\n#define BIT_GPIOA_INT_MD_8814B BIT(10)\n#define BIT_GPIO9_INT_MD_8814B BIT(9)\n#define BIT_GPIO8_INT_MD_8814B BIT(8)\n#define BIT_GPIO7_INT_MD_8814B BIT(7)\n#define BIT_GPIO6_INT_MD_8814B BIT(6)\n#define BIT_GPIO5_INT_MD_8814B BIT(5)\n#define BIT_GPIO4_INT_MD_8814B BIT(4)\n#define BIT_GPIO3_INT_MD_8814B BIT(3)\n#define BIT_GPIO2_INT_MD_8814B BIT(2)\n#define BIT_GPIO1_INT_MD_8814B BIT(1)\n#define BIT_GPIO0_INT_MD_8814B BIT(0)\n\n/* 2 REG_LED_CFG_8814B */\n#define BIT_GPIO3_WL_CTRL_EN_8814B BIT(27)\n#define BIT_LNAON_SEL_EN_8814B BIT(26)\n#define BIT_PAPE_SEL_EN_8814B BIT(25)\n#define BIT_DPDT_WLBT_SEL_8814B BIT(24)\n#define BIT_DPDT_SEL_EN_8814B BIT(23)\n#define BIT_GPIO13_14_WL_CTRL_EN_8814B BIT(22)\n#define BIT_LED2DIS_8814B BIT(21)\n#define BIT_LED2PL_8814B BIT(20)\n#define BIT_LED2SV_8814B BIT(19)\n\n#define BIT_SHIFT_LED2CM_8814B 16\n#define BIT_MASK_LED2CM_8814B 0x7\n#define BIT_LED2CM_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_LED2CM_8814B) << BIT_SHIFT_LED2CM_8814B)\n#define BITS_LED2CM_8814B (BIT_MASK_LED2CM_8814B << BIT_SHIFT_LED2CM_8814B)\n#define BIT_CLEAR_LED2CM_8814B(x) ((x) & (~BITS_LED2CM_8814B))\n#define BIT_GET_LED2CM_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_LED2CM_8814B) & BIT_MASK_LED2CM_8814B)\n#define BIT_SET_LED2CM_8814B(x, v)                                             \\\n\t(BIT_CLEAR_LED2CM_8814B(x) | BIT_LED2CM_8814B(v))\n\n#define BIT_LED1DIS_8814B BIT(15)\n#define BIT_LED1PL_8814B BIT(12)\n#define BIT_LED1SV_8814B BIT(11)\n\n#define BIT_SHIFT_LED1CM_8814B 8\n#define BIT_MASK_LED1CM_8814B 0x7\n#define BIT_LED1CM_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_LED1CM_8814B) << BIT_SHIFT_LED1CM_8814B)\n#define BITS_LED1CM_8814B (BIT_MASK_LED1CM_8814B << BIT_SHIFT_LED1CM_8814B)\n#define BIT_CLEAR_LED1CM_8814B(x) ((x) & (~BITS_LED1CM_8814B))\n#define BIT_GET_LED1CM_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_LED1CM_8814B) & BIT_MASK_LED1CM_8814B)\n#define BIT_SET_LED1CM_8814B(x, v)                                             \\\n\t(BIT_CLEAR_LED1CM_8814B(x) | BIT_LED1CM_8814B(v))\n\n#define BIT_LED0DIS_8814B BIT(7)\n\n#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B 5\n#define BIT_MASK_AFE_LDO_SWR_CHECK_8814B 0x3\n#define BIT_AFE_LDO_SWR_CHECK_8814B(x)                                         \\\n\t(((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8814B)                              \\\n\t << BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B)\n#define BITS_AFE_LDO_SWR_CHECK_8814B                                           \\\n\t(BIT_MASK_AFE_LDO_SWR_CHECK_8814B << BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B)\n#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8814B(x)                                   \\\n\t((x) & (~BITS_AFE_LDO_SWR_CHECK_8814B))\n#define BIT_GET_AFE_LDO_SWR_CHECK_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B) &                          \\\n\t BIT_MASK_AFE_LDO_SWR_CHECK_8814B)\n#define BIT_SET_AFE_LDO_SWR_CHECK_8814B(x, v)                                  \\\n\t(BIT_CLEAR_AFE_LDO_SWR_CHECK_8814B(x) | BIT_AFE_LDO_SWR_CHECK_8814B(v))\n\n#define BIT_LED0PL_8814B BIT(4)\n#define BIT_LED0SV_8814B BIT(3)\n\n#define BIT_SHIFT_LED0CM_8814B 0\n#define BIT_MASK_LED0CM_8814B 0x7\n#define BIT_LED0CM_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_LED0CM_8814B) << BIT_SHIFT_LED0CM_8814B)\n#define BITS_LED0CM_8814B (BIT_MASK_LED0CM_8814B << BIT_SHIFT_LED0CM_8814B)\n#define BIT_CLEAR_LED0CM_8814B(x) ((x) & (~BITS_LED0CM_8814B))\n#define BIT_GET_LED0CM_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_LED0CM_8814B) & BIT_MASK_LED0CM_8814B)\n#define BIT_SET_LED0CM_8814B(x, v)                                             \\\n\t(BIT_CLEAR_LED0CM_8814B(x) | BIT_LED0CM_8814B(v))\n\n/* 2 REG_FSIMR_8814B */\n#define BIT_FS_PDNINT_EN_8814B BIT(31)\n#define BIT_NFC_INT_PAD_EN_8814B BIT(30)\n#define BIT_FS_SPS_OCP_INT_EN_8814B BIT(29)\n#define BIT_FS_PWMERR_INT_EN_8814B BIT(28)\n#define BIT_FS_GPIOF_INT_EN_8814B BIT(27)\n#define BIT_FS_GPIOE_INT_EN_8814B BIT(26)\n#define BIT_FS_GPIOD_INT_EN_8814B BIT(25)\n#define BIT_FS_GPIOC_INT_EN_8814B BIT(24)\n#define BIT_FS_GPIOB_INT_EN_8814B BIT(23)\n#define BIT_FS_GPIOA_INT_EN_8814B BIT(22)\n#define BIT_FS_GPIO9_INT_EN_8814B BIT(21)\n#define BIT_FS_GPIO8_INT_EN_8814B BIT(20)\n#define BIT_FS_GPIO7_INT_EN_8814B BIT(19)\n#define BIT_FS_GPIO6_INT_EN_8814B BIT(18)\n#define BIT_FS_GPIO5_INT_EN_8814B BIT(17)\n#define BIT_FS_GPIO4_INT_EN_8814B BIT(16)\n#define BIT_FS_GPIO3_INT_EN_8814B BIT(15)\n#define BIT_FS_GPIO2_INT_EN_8814B BIT(14)\n#define BIT_FS_GPIO1_INT_EN_8814B BIT(13)\n#define BIT_FS_GPIO0_INT_EN_8814B BIT(12)\n#define BIT_FS_HCI_SUS_EN_8814B BIT(11)\n#define BIT_FS_HCI_RES_EN_8814B BIT(10)\n#define BIT_FS_HCI_RESET_EN_8814B BIT(9)\n#define BIT_USB_SCSI_CMD_EN_8814B BIT(8)\n#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8814B BIT(7)\n#define BIT_ACT2RECOVERY_INT_EN_V1_8814B BIT(6)\n#define BIT_GEN1GEN2_SWITCH_8814B BIT(5)\n#define BIT_HCI_TXDMA_REQ_HIMR_8814B BIT(4)\n#define BIT_FS_32K_LEAVE_SETTING_MAK_8814B BIT(3)\n#define BIT_FS_32K_ENTER_SETTING_MAK_8814B BIT(2)\n#define BIT_FS_USB_LPMRSM_MSK_8814B BIT(1)\n#define BIT_FS_USB_LPMINT_MSK_8814B BIT(0)\n\n/* 2 REG_FSISR_8814B */\n#define BIT_FS_PDNINT_8814B BIT(31)\n#define BIT_FS_SPS_OCP_INT_8814B BIT(29)\n#define BIT_FS_PWMERR_INT_8814B BIT(28)\n#define BIT_FS_GPIOF_INT_8814B BIT(27)\n#define BIT_FS_GPIOE_INT_8814B BIT(26)\n#define BIT_FS_GPIOD_INT_8814B BIT(25)\n#define BIT_FS_GPIOC_INT_8814B BIT(24)\n#define BIT_FS_GPIOB_INT_8814B BIT(23)\n#define BIT_FS_GPIOA_INT_8814B BIT(22)\n#define BIT_FS_GPIO9_INT_8814B BIT(21)\n#define BIT_FS_GPIO8_INT_8814B BIT(20)\n#define BIT_FS_GPIO7_INT_8814B BIT(19)\n#define BIT_FS_GPIO6_INT_8814B BIT(18)\n#define BIT_FS_GPIO5_INT_8814B BIT(17)\n#define BIT_FS_GPIO4_INT_8814B BIT(16)\n#define BIT_FS_GPIO3_INT_8814B BIT(15)\n#define BIT_FS_GPIO2_INT_8814B BIT(14)\n#define BIT_FS_GPIO1_INT_8814B BIT(13)\n#define BIT_FS_GPIO0_INT_8814B BIT(12)\n#define BIT_FS_HCI_SUS_INT_8814B BIT(11)\n#define BIT_FS_HCI_RES_INT_8814B BIT(10)\n#define BIT_FS_HCI_RESET_INT_8814B BIT(9)\n#define BIT_USB_SCSI_CMD_INT_8814B BIT(8)\n#define BIT_FS_BTON_STS_UPDATE_INT_8814B BIT(7)\n#define BIT_ACT2RECOVERY_8814B BIT(6)\n#define BIT_GEN1GEN2_SWITCH_8814B BIT(5)\n#define BIT_HCI_TXDMA_REQ_HISR_8814B BIT(4)\n#define BIT_FS_32K_LEAVE_SETTING_INT_8814B BIT(3)\n#define BIT_FS_32K_ENTER_SETTING_INT_8814B BIT(2)\n#define BIT_FS_USB_LPMRSM_INT_8814B BIT(1)\n#define BIT_FS_USB_LPMINT_INT_8814B BIT(0)\n\n/* 2 REG_HSIMR_8814B */\n#define BIT_GPIOF_INT_EN_8814B BIT(31)\n#define BIT_GPIOE_INT_EN_8814B BIT(30)\n#define BIT_GPIOD_INT_EN_8814B BIT(29)\n#define BIT_GPIOC_INT_EN_8814B BIT(28)\n#define BIT_GPIOB_INT_EN_8814B BIT(27)\n#define BIT_GPIOA_INT_EN_8814B BIT(26)\n#define BIT_GPIO9_INT_EN_8814B BIT(25)\n#define BIT_GPIO8_INT_EN_8814B BIT(24)\n#define BIT_GPIO7_INT_EN_8814B BIT(23)\n#define BIT_GPIO6_INT_EN_8814B BIT(22)\n#define BIT_GPIO5_INT_EN_8814B BIT(21)\n#define BIT_GPIO4_INT_EN_8814B BIT(20)\n#define BIT_GPIO3_INT_EN_8814B BIT(19)\n#define BIT_GPIO2_INT_EN_V1_8814B BIT(18)\n#define BIT_GPIO1_INT_EN_8814B BIT(17)\n#define BIT_GPIO0_INT_EN_8814B BIT(16)\n#define BIT_PDNINT_EN_8814B BIT(7)\n#define BIT_RON_INT_EN_8814B BIT(6)\n#define BIT_SPS_OCP_INT_EN_8814B BIT(5)\n#define BIT_GPIO15_0_INT_EN_8814B BIT(0)\n\n/* 2 REG_HSISR_8814B */\n#define BIT_GPIOF_INT_8814B BIT(31)\n#define BIT_GPIOE_INT_8814B BIT(30)\n#define BIT_GPIOD_INT_8814B BIT(29)\n#define BIT_GPIOC_INT_8814B BIT(28)\n#define BIT_GPIOB_INT_8814B BIT(27)\n#define BIT_GPIOA_INT_8814B BIT(26)\n#define BIT_GPIO9_INT_8814B BIT(25)\n#define BIT_GPIO8_INT_8814B BIT(24)\n#define BIT_GPIO7_INT_8814B BIT(23)\n#define BIT_GPIO6_INT_8814B BIT(22)\n#define BIT_GPIO5_INT_8814B BIT(21)\n#define BIT_GPIO4_INT_8814B BIT(20)\n#define BIT_GPIO3_INT_8814B BIT(19)\n#define BIT_GPIO2_INT_V1_8814B BIT(18)\n#define BIT_GPIO1_INT_8814B BIT(17)\n#define BIT_GPIO0_INT_8814B BIT(16)\n#define BIT_PDNINT_8814B BIT(7)\n#define BIT_RON_INT_8814B BIT(6)\n#define BIT_SPS_OCP_INT_8814B BIT(5)\n#define BIT_GPIO15_0_INT_8814B BIT(0)\n\n/* 2 REG_GPIO_EXT_CTRL_8814B */\n\n#define BIT_SHIFT_GPIO_MOD_15_TO_8_8814B 24\n#define BIT_MASK_GPIO_MOD_15_TO_8_8814B 0xff\n#define BIT_GPIO_MOD_15_TO_8_8814B(x)                                          \\\n\t(((x) & BIT_MASK_GPIO_MOD_15_TO_8_8814B)                               \\\n\t << BIT_SHIFT_GPIO_MOD_15_TO_8_8814B)\n#define BITS_GPIO_MOD_15_TO_8_8814B                                            \\\n\t(BIT_MASK_GPIO_MOD_15_TO_8_8814B << BIT_SHIFT_GPIO_MOD_15_TO_8_8814B)\n#define BIT_CLEAR_GPIO_MOD_15_TO_8_8814B(x)                                    \\\n\t((x) & (~BITS_GPIO_MOD_15_TO_8_8814B))\n#define BIT_GET_GPIO_MOD_15_TO_8_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8814B) &                           \\\n\t BIT_MASK_GPIO_MOD_15_TO_8_8814B)\n#define BIT_SET_GPIO_MOD_15_TO_8_8814B(x, v)                                   \\\n\t(BIT_CLEAR_GPIO_MOD_15_TO_8_8814B(x) | BIT_GPIO_MOD_15_TO_8_8814B(v))\n\n#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B 16\n#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B 0xff\n#define BIT_GPIO_IO_SEL_15_TO_8_8814B(x)                                       \\\n\t(((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B)                            \\\n\t << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B)\n#define BITS_GPIO_IO_SEL_15_TO_8_8814B                                         \\\n\t(BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B                                    \\\n\t << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B)\n#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8814B(x)                                 \\\n\t((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8814B))\n#define BIT_GET_GPIO_IO_SEL_15_TO_8_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B) &                        \\\n\t BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B)\n#define BIT_SET_GPIO_IO_SEL_15_TO_8_8814B(x, v)                                \\\n\t(BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8814B(x) |                              \\\n\t BIT_GPIO_IO_SEL_15_TO_8_8814B(v))\n\n#define BIT_SHIFT_GPIO_OUT_15_TO_8_8814B 8\n#define BIT_MASK_GPIO_OUT_15_TO_8_8814B 0xff\n#define BIT_GPIO_OUT_15_TO_8_8814B(x)                                          \\\n\t(((x) & BIT_MASK_GPIO_OUT_15_TO_8_8814B)                               \\\n\t << BIT_SHIFT_GPIO_OUT_15_TO_8_8814B)\n#define BITS_GPIO_OUT_15_TO_8_8814B                                            \\\n\t(BIT_MASK_GPIO_OUT_15_TO_8_8814B << BIT_SHIFT_GPIO_OUT_15_TO_8_8814B)\n#define BIT_CLEAR_GPIO_OUT_15_TO_8_8814B(x)                                    \\\n\t((x) & (~BITS_GPIO_OUT_15_TO_8_8814B))\n#define BIT_GET_GPIO_OUT_15_TO_8_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8814B) &                           \\\n\t BIT_MASK_GPIO_OUT_15_TO_8_8814B)\n#define BIT_SET_GPIO_OUT_15_TO_8_8814B(x, v)                                   \\\n\t(BIT_CLEAR_GPIO_OUT_15_TO_8_8814B(x) | BIT_GPIO_OUT_15_TO_8_8814B(v))\n\n#define BIT_SHIFT_GPIO_IN_15_TO_8_8814B 0\n#define BIT_MASK_GPIO_IN_15_TO_8_8814B 0xff\n#define BIT_GPIO_IN_15_TO_8_8814B(x)                                           \\\n\t(((x) & BIT_MASK_GPIO_IN_15_TO_8_8814B)                                \\\n\t << BIT_SHIFT_GPIO_IN_15_TO_8_8814B)\n#define BITS_GPIO_IN_15_TO_8_8814B                                             \\\n\t(BIT_MASK_GPIO_IN_15_TO_8_8814B << BIT_SHIFT_GPIO_IN_15_TO_8_8814B)\n#define BIT_CLEAR_GPIO_IN_15_TO_8_8814B(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8814B))\n#define BIT_GET_GPIO_IN_15_TO_8_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8814B) &                            \\\n\t BIT_MASK_GPIO_IN_15_TO_8_8814B)\n#define BIT_SET_GPIO_IN_15_TO_8_8814B(x, v)                                    \\\n\t(BIT_CLEAR_GPIO_IN_15_TO_8_8814B(x) | BIT_GPIO_IN_15_TO_8_8814B(v))\n\n/* 2 REG_PAD_CTRL1_8814B */\n#define BIT_DATA_CPU_JTAG_8814B BIT(30)\n#define BIT_PAPE_WLBT_SEL_8814B BIT(29)\n#define BIT_LNAON_WLBT_SEL_8814B BIT(28)\n#define BIT_BTGP_GPG3_FEN_8814B BIT(26)\n#define BIT_BTGP_GPG2_FEN_8814B BIT(25)\n#define BIT_BTGP_JTAG_EN_8814B BIT(24)\n#define BIT_XTAL_CLK_EXTARNAL_EN_8814B BIT(23)\n#define BIT_BTGP_UART0_EN_8814B BIT(22)\n#define BIT_BTGP_UART1_EN_8814B BIT(21)\n#define BIT_BTGP_SPI_EN_8814B BIT(20)\n#define BIT_BTGP_GPIO_E2_8814B BIT(19)\n#define BIT_BTGP_GPIO_EN_8814B BIT(18)\n\n#define BIT_SHIFT_BTGP_GPIO_SL_8814B 16\n#define BIT_MASK_BTGP_GPIO_SL_8814B 0x3\n#define BIT_BTGP_GPIO_SL_8814B(x)                                              \\\n\t(((x) & BIT_MASK_BTGP_GPIO_SL_8814B) << BIT_SHIFT_BTGP_GPIO_SL_8814B)\n#define BITS_BTGP_GPIO_SL_8814B                                                \\\n\t(BIT_MASK_BTGP_GPIO_SL_8814B << BIT_SHIFT_BTGP_GPIO_SL_8814B)\n#define BIT_CLEAR_BTGP_GPIO_SL_8814B(x) ((x) & (~BITS_BTGP_GPIO_SL_8814B))\n#define BIT_GET_BTGP_GPIO_SL_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BTGP_GPIO_SL_8814B) & BIT_MASK_BTGP_GPIO_SL_8814B)\n#define BIT_SET_BTGP_GPIO_SL_8814B(x, v)                                       \\\n\t(BIT_CLEAR_BTGP_GPIO_SL_8814B(x) | BIT_BTGP_GPIO_SL_8814B(v))\n\n#define BIT_WL_JTAG_8814B BIT(15)\n#define BIT_PAD_SDIO_SR_8814B BIT(14)\n#define BIT_GPIO14_OUTPUT_PL_8814B BIT(13)\n#define BIT_HOST_WAKE_PAD_PULL_EN_8814B BIT(12)\n#define BIT_HOST_WAKE_PAD_SL_8814B BIT(11)\n#define BIT_SW_LNAON_G_SEL_DATA_8814B BIT(8)\n#define BIT_SW_LNAON_A_SEL_DATA_8814B BIT(7)\n#define BIT_SW_PAPE_G_SEL_DATA_8814B BIT(4)\n#define BIT_SW_PAPE_A_SEL_DATA_8814B BIT(3)\n#define BIT_SW_DPDT_SEL_DATA_8814B BIT(0)\n\n/* 2 REG_WL_BT_PWR_CTRL_8814B */\n#define BIT_ISO_BD2PP_8814B BIT(31)\n#define BIT_LDOV12B_EN_8814B BIT(30)\n#define BIT_CKEN_BTGPS_8814B BIT(29)\n#define BIT_FEN_BTGPS_8814B BIT(28)\n#define BIT_BTCPU_BOOTSEL_8814B BIT(27)\n#define BIT_SPI_SPEEDUP_8814B BIT(26)\n#define BIT_BT_SUS_8814B BIT(25)\n#define BIT_DEVWAKE_PAD_TYPE_SEL_8814B BIT(24)\n#define BIT_CLKREQ_PAD_TYPE_SEL_8814B BIT(23)\n#define BIT_ISO_BTPON2PP_8814B BIT(22)\n#define BIT_BTCOEX_CMD_8814B BIT(21)\n#define BIT_BT_UART_INTF_8814B BIT(20)\n#define BIT_BT_HWROF_EN_8814B BIT(19)\n#define BIT_BT_FUNC_EN_8814B BIT(18)\n#define BIT_BT_HWPDN_SL_8814B BIT(17)\n#define BIT_BT_DISN_EN_8814B BIT(16)\n#define BIT_BT_PDN_PULL_EN_8814B BIT(15)\n#define BIT_WL_PDN_PULL_EN_8814B BIT(14)\n#define BIT_EXTERNAL_REQUEST_PL_8814B BIT(13)\n#define BIT_GPIO0_2_3_PULL_LOW_EN_8814B BIT(12)\n#define BIT_ISO_BA2PP_8814B BIT(11)\n#define BIT_BT_AFE_LDO_EN_8814B BIT(10)\n#define BIT_BT_AFE_PLL_EN_8814B BIT(9)\n#define BIT_BT_DIG_CLK_EN_8814B BIT(8)\n#define BIT_UART_BRIDGE_8814B BIT(7)\n#define BIT_OSC32K_CTRL_SEL_8814B BIT(6)\n#define BIT_WL_DRV_EXIST_IDX_8814B BIT(5)\n#define BIT_DOP_EHPAD_8814B BIT(4)\n#define BIT_WL_HWROF_EN_8814B BIT(3)\n#define BIT_WL_FUNC_EN_8814B BIT(2)\n#define BIT_WL_HWPDN_SL_8814B BIT(1)\n#define BIT_WL_HWPDN_EN_8814B BIT(0)\n\n/* 2 REG_SDM_DEBUG_8814B */\n#define BIT_BT_WAKE_DEV_EN_V1_8814B BIT(19)\n#define BIT_BT_WAKE_HST_EN_V1_8814B BIT(18)\n#define BIT_BT_WAKE_HST_PL_V1_8814B BIT(17)\n#define BIT_BT_CLKREQ_EN_V1_8814B BIT(16)\n\n#define BIT_SHIFT_WLCLK_PHASE_8814B 0\n#define BIT_MASK_WLCLK_PHASE_8814B 0x1f\n#define BIT_WLCLK_PHASE_8814B(x)                                               \\\n\t(((x) & BIT_MASK_WLCLK_PHASE_8814B) << BIT_SHIFT_WLCLK_PHASE_8814B)\n#define BITS_WLCLK_PHASE_8814B                                                 \\\n\t(BIT_MASK_WLCLK_PHASE_8814B << BIT_SHIFT_WLCLK_PHASE_8814B)\n#define BIT_CLEAR_WLCLK_PHASE_8814B(x) ((x) & (~BITS_WLCLK_PHASE_8814B))\n#define BIT_GET_WLCLK_PHASE_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_WLCLK_PHASE_8814B) & BIT_MASK_WLCLK_PHASE_8814B)\n#define BIT_SET_WLCLK_PHASE_8814B(x, v)                                        \\\n\t(BIT_CLEAR_WLCLK_PHASE_8814B(x) | BIT_WLCLK_PHASE_8814B(v))\n\n/* 2 REG_SYS_SDIO_CTRL_8814B */\n#define BIT_DBG_GNT_WL_BT_8814B BIT(27)\n#define BIT_LTE_MUX_CTRL_PATH_8814B BIT(26)\n#define BIT_LTE_COEX_UART_8814B BIT(25)\n#define BIT_3W_LTE_WL_GPIO_8814B BIT(24)\n#define BIT_SDIO_INT_POLARITY_8814B BIT(19)\n#define BIT_SDIO_INT_8814B BIT(18)\n#define BIT_SDIO_OFF_EN_8814B BIT(17)\n#define BIT_SDIO_ON_EN_8814B BIT(16)\n#define BIT_PCIE_WAIT_TIMEOUT_EVENT_8814B BIT(10)\n#define BIT_PCIE_WAIT_TIME_8814B BIT(9)\n#define BIT_MPCIE_REFCLK_XTAL_SEL_8814B BIT(8)\n#define BIT_BT_CLKREQ_EN_8814B BIT(6)\n\n#define BIT_SHIFT_USB_CKREF_CML_R_8814B 4\n#define BIT_MASK_USB_CKREF_CML_R_8814B 0x3\n#define BIT_USB_CKREF_CML_R_8814B(x)                                           \\\n\t(((x) & BIT_MASK_USB_CKREF_CML_R_8814B)                                \\\n\t << BIT_SHIFT_USB_CKREF_CML_R_8814B)\n#define BITS_USB_CKREF_CML_R_8814B                                             \\\n\t(BIT_MASK_USB_CKREF_CML_R_8814B << BIT_SHIFT_USB_CKREF_CML_R_8814B)\n#define BIT_CLEAR_USB_CKREF_CML_R_8814B(x) ((x) & (~BITS_USB_CKREF_CML_R_8814B))\n#define BIT_GET_USB_CKREF_CML_R_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_USB_CKREF_CML_R_8814B) &                            \\\n\t BIT_MASK_USB_CKREF_CML_R_8814B)\n#define BIT_SET_USB_CKREF_CML_R_8814B(x, v)                                    \\\n\t(BIT_CLEAR_USB_CKREF_CML_R_8814B(x) | BIT_USB_CKREF_CML_R_8814B(v))\n\n#define BIT_SHIFT_USB_CKREF_D2S_I_8814B 2\n#define BIT_MASK_USB_CKREF_D2S_I_8814B 0x3\n#define BIT_USB_CKREF_D2S_I_8814B(x)                                           \\\n\t(((x) & BIT_MASK_USB_CKREF_D2S_I_8814B)                                \\\n\t << BIT_SHIFT_USB_CKREF_D2S_I_8814B)\n#define BITS_USB_CKREF_D2S_I_8814B                                             \\\n\t(BIT_MASK_USB_CKREF_D2S_I_8814B << BIT_SHIFT_USB_CKREF_D2S_I_8814B)\n#define BIT_CLEAR_USB_CKREF_D2S_I_8814B(x) ((x) & (~BITS_USB_CKREF_D2S_I_8814B))\n#define BIT_GET_USB_CKREF_D2S_I_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_USB_CKREF_D2S_I_8814B) &                            \\\n\t BIT_MASK_USB_CKREF_D2S_I_8814B)\n#define BIT_SET_USB_CKREF_D2S_I_8814B(x, v)                                    \\\n\t(BIT_CLEAR_USB_CKREF_D2S_I_8814B(x) | BIT_USB_CKREF_D2S_I_8814B(v))\n\n#define BIT_RES_USB_MASS_STORAGE_DESC_8814B BIT(1)\n#define BIT_USB_WAIT_TIME_8814B BIT(0)\n\n/* 2 REG_HCI_OPT_CTRL_8814B */\n\n#define BIT_SHIFT_TSFT_SEL_8814B 29\n#define BIT_MASK_TSFT_SEL_8814B 0x7\n#define BIT_TSFT_SEL_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_TSFT_SEL_8814B) << BIT_SHIFT_TSFT_SEL_8814B)\n#define BITS_TSFT_SEL_8814B                                                    \\\n\t(BIT_MASK_TSFT_SEL_8814B << BIT_SHIFT_TSFT_SEL_8814B)\n#define BIT_CLEAR_TSFT_SEL_8814B(x) ((x) & (~BITS_TSFT_SEL_8814B))\n#define BIT_GET_TSFT_SEL_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TSFT_SEL_8814B) & BIT_MASK_TSFT_SEL_8814B)\n#define BIT_SET_TSFT_SEL_8814B(x, v)                                           \\\n\t(BIT_CLEAR_TSFT_SEL_8814B(x) | BIT_TSFT_SEL_8814B(v))\n\n#define BIT_TSFT_BAND_SEL_8814B BIT(28)\n#define BIT_USB_HOST_PWR_OFF_EN_8814B BIT(12)\n#define BIT_SYM_LPS_BLOCK_EN_8814B BIT(11)\n#define BIT_USB_LPM_ACT_EN_8814B BIT(10)\n#define BIT_USB_LPM_NY_8814B BIT(9)\n#define BIT_USB_SUS_DIS_8814B BIT(8)\n\n#define BIT_SHIFT_SDIO_PAD_E_8814B 5\n#define BIT_MASK_SDIO_PAD_E_8814B 0x7\n#define BIT_SDIO_PAD_E_8814B(x)                                                \\\n\t(((x) & BIT_MASK_SDIO_PAD_E_8814B) << BIT_SHIFT_SDIO_PAD_E_8814B)\n#define BITS_SDIO_PAD_E_8814B                                                  \\\n\t(BIT_MASK_SDIO_PAD_E_8814B << BIT_SHIFT_SDIO_PAD_E_8814B)\n#define BIT_CLEAR_SDIO_PAD_E_8814B(x) ((x) & (~BITS_SDIO_PAD_E_8814B))\n#define BIT_GET_SDIO_PAD_E_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_SDIO_PAD_E_8814B) & BIT_MASK_SDIO_PAD_E_8814B)\n#define BIT_SET_SDIO_PAD_E_8814B(x, v)                                         \\\n\t(BIT_CLEAR_SDIO_PAD_E_8814B(x) | BIT_SDIO_PAD_E_8814B(v))\n\n#define BIT_USB_LPPLL_EN_8814B BIT(4)\n#define BIT_ROP_SW15_8814B BIT(2)\n#define BIT_PCI_CKRDY_OPT_8814B BIT(1)\n#define BIT_PCI_VAUX_EN_8814B BIT(0)\n\n/* 2 REG_AFE_CTRL4_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_LDO_SWR_CTRL_8814B */\n#define BIT_ZCD_HW_AUTO_EN_8814B BIT(27)\n#define BIT_ZCD_REGSEL_8814B BIT(26)\n\n#define BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B 21\n#define BIT_MASK_AUTO_ZCD_IN_CODE_8814B 0x1f\n#define BIT_AUTO_ZCD_IN_CODE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8814B)                               \\\n\t << BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B)\n#define BITS_AUTO_ZCD_IN_CODE_8814B                                            \\\n\t(BIT_MASK_AUTO_ZCD_IN_CODE_8814B << BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B)\n#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8814B(x)                                    \\\n\t((x) & (~BITS_AUTO_ZCD_IN_CODE_8814B))\n#define BIT_GET_AUTO_ZCD_IN_CODE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B) &                           \\\n\t BIT_MASK_AUTO_ZCD_IN_CODE_8814B)\n#define BIT_SET_AUTO_ZCD_IN_CODE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_AUTO_ZCD_IN_CODE_8814B(x) | BIT_AUTO_ZCD_IN_CODE_8814B(v))\n\n#define BIT_SHIFT_ZCD_CODE_IN_L_8814B 16\n#define BIT_MASK_ZCD_CODE_IN_L_8814B 0x1f\n#define BIT_ZCD_CODE_IN_L_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ZCD_CODE_IN_L_8814B) << BIT_SHIFT_ZCD_CODE_IN_L_8814B)\n#define BITS_ZCD_CODE_IN_L_8814B                                               \\\n\t(BIT_MASK_ZCD_CODE_IN_L_8814B << BIT_SHIFT_ZCD_CODE_IN_L_8814B)\n#define BIT_CLEAR_ZCD_CODE_IN_L_8814B(x) ((x) & (~BITS_ZCD_CODE_IN_L_8814B))\n#define BIT_GET_ZCD_CODE_IN_L_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8814B) & BIT_MASK_ZCD_CODE_IN_L_8814B)\n#define BIT_SET_ZCD_CODE_IN_L_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ZCD_CODE_IN_L_8814B(x) | BIT_ZCD_CODE_IN_L_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_MCUFW_CTRL_8814B */\n\n#define BIT_SHIFT_RPWM_8814B 24\n#define BIT_MASK_RPWM_8814B 0xff\n#define BIT_RPWM_8814B(x) (((x) & BIT_MASK_RPWM_8814B) << BIT_SHIFT_RPWM_8814B)\n#define BITS_RPWM_8814B (BIT_MASK_RPWM_8814B << BIT_SHIFT_RPWM_8814B)\n#define BIT_CLEAR_RPWM_8814B(x) ((x) & (~BITS_RPWM_8814B))\n#define BIT_GET_RPWM_8814B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_RPWM_8814B) & BIT_MASK_RPWM_8814B)\n#define BIT_SET_RPWM_8814B(x, v) (BIT_CLEAR_RPWM_8814B(x) | BIT_RPWM_8814B(v))\n\n#define BIT_ANA_PORT_EN_8814B BIT(22)\n#define BIT_MAC_PORT_EN_8814B BIT(21)\n#define BIT_BOOT_FSPI_EN_8814B BIT(20)\n#define BIT_ROM_DLEN_8814B BIT(19)\n\n#define BIT_SHIFT_ROM_PGE_8814B 16\n#define BIT_MASK_ROM_PGE_8814B 0x7\n#define BIT_ROM_PGE_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_ROM_PGE_8814B) << BIT_SHIFT_ROM_PGE_8814B)\n#define BITS_ROM_PGE_8814B (BIT_MASK_ROM_PGE_8814B << BIT_SHIFT_ROM_PGE_8814B)\n#define BIT_CLEAR_ROM_PGE_8814B(x) ((x) & (~BITS_ROM_PGE_8814B))\n#define BIT_GET_ROM_PGE_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_ROM_PGE_8814B) & BIT_MASK_ROM_PGE_8814B)\n#define BIT_SET_ROM_PGE_8814B(x, v)                                            \\\n\t(BIT_CLEAR_ROM_PGE_8814B(x) | BIT_ROM_PGE_8814B(v))\n\n#define BIT_FW_INIT_RDY_8814B BIT(15)\n#define BIT_FW_DW_RDY_8814B BIT(14)\n\n#define BIT_SHIFT_CPU_CLK_SEL_8814B 12\n#define BIT_MASK_CPU_CLK_SEL_8814B 0x3\n#define BIT_CPU_CLK_SEL_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CPU_CLK_SEL_8814B) << BIT_SHIFT_CPU_CLK_SEL_8814B)\n#define BITS_CPU_CLK_SEL_8814B                                                 \\\n\t(BIT_MASK_CPU_CLK_SEL_8814B << BIT_SHIFT_CPU_CLK_SEL_8814B)\n#define BIT_CLEAR_CPU_CLK_SEL_8814B(x) ((x) & (~BITS_CPU_CLK_SEL_8814B))\n#define BIT_GET_CPU_CLK_SEL_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CPU_CLK_SEL_8814B) & BIT_MASK_CPU_CLK_SEL_8814B)\n#define BIT_SET_CPU_CLK_SEL_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CPU_CLK_SEL_8814B(x) | BIT_CPU_CLK_SEL_8814B(v))\n\n#define BIT_CCLK_CHG_MASK_8814B BIT(11)\n#define BIT_EMEM__TXBUF_CHKSUM_OK_8814B BIT(10)\n#define BIT_EMEM_TXBUF_DW_RDY_8814B BIT(9)\n#define BIT_EMEM_CHKSUM_OK_8814B BIT(8)\n#define BIT_EMEM_DW_OK_8814B BIT(7)\n#define BIT_DMEM_CHKSUM_OK_8814B BIT(6)\n#define BIT_DMEM_DW_OK_8814B BIT(5)\n#define BIT_IMEM_CHKSUM_OK_8814B BIT(4)\n#define BIT_IMEM_DW_OK_8814B BIT(3)\n#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK_8814B BIT(2)\n#define BIT_IMEM_BOOT_LOAD_DW_OK_8814B BIT(1)\n#define BIT_MCUFWDL_EN_8814B BIT(0)\n\n/* 2 REG_MCU_TST_CFG_8814B */\n\n#define BIT_SHIFT_C2H_MSG_8814B 0\n#define BIT_MASK_C2H_MSG_8814B 0xffff\n#define BIT_C2H_MSG_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_C2H_MSG_8814B) << BIT_SHIFT_C2H_MSG_8814B)\n#define BITS_C2H_MSG_8814B (BIT_MASK_C2H_MSG_8814B << BIT_SHIFT_C2H_MSG_8814B)\n#define BIT_CLEAR_C2H_MSG_8814B(x) ((x) & (~BITS_C2H_MSG_8814B))\n#define BIT_GET_C2H_MSG_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_C2H_MSG_8814B) & BIT_MASK_C2H_MSG_8814B)\n#define BIT_SET_C2H_MSG_8814B(x, v)                                            \\\n\t(BIT_CLEAR_C2H_MSG_8814B(x) | BIT_C2H_MSG_8814B(v))\n\n/* 2 REG_HMEBOX_E0_E1_8814B */\n\n#define BIT_SHIFT_HOST_MSG_E1_8814B 16\n#define BIT_MASK_HOST_MSG_E1_8814B 0xffff\n#define BIT_HOST_MSG_E1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E1_8814B) << BIT_SHIFT_HOST_MSG_E1_8814B)\n#define BITS_HOST_MSG_E1_8814B                                                 \\\n\t(BIT_MASK_HOST_MSG_E1_8814B << BIT_SHIFT_HOST_MSG_E1_8814B)\n#define BIT_CLEAR_HOST_MSG_E1_8814B(x) ((x) & (~BITS_HOST_MSG_E1_8814B))\n#define BIT_GET_HOST_MSG_E1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E1_8814B) & BIT_MASK_HOST_MSG_E1_8814B)\n#define BIT_SET_HOST_MSG_E1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E1_8814B(x) | BIT_HOST_MSG_E1_8814B(v))\n\n#define BIT_SHIFT_HOST_MSG_E0_8814B 0\n#define BIT_MASK_HOST_MSG_E0_8814B 0xffff\n#define BIT_HOST_MSG_E0_8814B(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E0_8814B) << BIT_SHIFT_HOST_MSG_E0_8814B)\n#define BITS_HOST_MSG_E0_8814B                                                 \\\n\t(BIT_MASK_HOST_MSG_E0_8814B << BIT_SHIFT_HOST_MSG_E0_8814B)\n#define BIT_CLEAR_HOST_MSG_E0_8814B(x) ((x) & (~BITS_HOST_MSG_E0_8814B))\n#define BIT_GET_HOST_MSG_E0_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E0_8814B) & BIT_MASK_HOST_MSG_E0_8814B)\n#define BIT_SET_HOST_MSG_E0_8814B(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E0_8814B(x) | BIT_HOST_MSG_E0_8814B(v))\n\n/* 2 REG_HMEBOX_E2_E3_8814B */\n\n#define BIT_SHIFT_HOST_MSG_E3_8814B 16\n#define BIT_MASK_HOST_MSG_E3_8814B 0xffff\n#define BIT_HOST_MSG_E3_8814B(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E3_8814B) << BIT_SHIFT_HOST_MSG_E3_8814B)\n#define BITS_HOST_MSG_E3_8814B                                                 \\\n\t(BIT_MASK_HOST_MSG_E3_8814B << BIT_SHIFT_HOST_MSG_E3_8814B)\n#define BIT_CLEAR_HOST_MSG_E3_8814B(x) ((x) & (~BITS_HOST_MSG_E3_8814B))\n#define BIT_GET_HOST_MSG_E3_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E3_8814B) & BIT_MASK_HOST_MSG_E3_8814B)\n#define BIT_SET_HOST_MSG_E3_8814B(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E3_8814B(x) | BIT_HOST_MSG_E3_8814B(v))\n\n#define BIT_SHIFT_HOST_MSG_E2_8814B 0\n#define BIT_MASK_HOST_MSG_E2_8814B 0xffff\n#define BIT_HOST_MSG_E2_8814B(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E2_8814B) << BIT_SHIFT_HOST_MSG_E2_8814B)\n#define BITS_HOST_MSG_E2_8814B                                                 \\\n\t(BIT_MASK_HOST_MSG_E2_8814B << BIT_SHIFT_HOST_MSG_E2_8814B)\n#define BIT_CLEAR_HOST_MSG_E2_8814B(x) ((x) & (~BITS_HOST_MSG_E2_8814B))\n#define BIT_GET_HOST_MSG_E2_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E2_8814B) & BIT_MASK_HOST_MSG_E2_8814B)\n#define BIT_SET_HOST_MSG_E2_8814B(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E2_8814B(x) | BIT_HOST_MSG_E2_8814B(v))\n\n/* 2 REG_WLLPS_CTRL_8814B */\n#define BIT_WLLPSOP_EABM_8814B BIT(31)\n#define BIT_WLLPSOP_ACKF_8814B BIT(30)\n#define BIT_WLLPSOP_DLDM_8814B BIT(29)\n#define BIT_WLLPSOP_ESWR_8814B BIT(28)\n#define BIT_WLLPSOP_PWMM_8814B BIT(27)\n#define BIT_WLLPSOP_EECK_8814B BIT(26)\n#define BIT_WLLPSOP_WLMACOFF_8814B BIT(25)\n#define BIT_WLLPSOP_EXTAL_8814B BIT(24)\n#define BIT_WL_SYNPON_VOLTSPDN_8814B BIT(23)\n#define BIT_WLLPSOP_WLBBOFF_8814B BIT(22)\n#define BIT_WLLPSOP_WLMEM_DS_8814B BIT(21)\n\n#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B 12\n#define BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B 0xf\n#define BIT_LPLDH12_VADJ_STEP_DN_8814B(x)                                      \\\n\t(((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B)                           \\\n\t << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B)\n#define BITS_LPLDH12_VADJ_STEP_DN_8814B                                        \\\n\t(BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B                                   \\\n\t << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B)\n#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8814B(x)                                \\\n\t((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8814B))\n#define BIT_GET_LPLDH12_VADJ_STEP_DN_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B) &                       \\\n\t BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B)\n#define BIT_SET_LPLDH12_VADJ_STEP_DN_8814B(x, v)                               \\\n\t(BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8814B(x) |                             \\\n\t BIT_LPLDH12_VADJ_STEP_DN_8814B(v))\n\n#define BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B 8\n#define BIT_MASK_V15ADJ_L1_STEP_DN_8814B 0x7\n#define BIT_V15ADJ_L1_STEP_DN_8814B(x)                                         \\\n\t(((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8814B)                              \\\n\t << BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B)\n#define BITS_V15ADJ_L1_STEP_DN_8814B                                           \\\n\t(BIT_MASK_V15ADJ_L1_STEP_DN_8814B << BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B)\n#define BIT_CLEAR_V15ADJ_L1_STEP_DN_8814B(x)                                   \\\n\t((x) & (~BITS_V15ADJ_L1_STEP_DN_8814B))\n#define BIT_GET_V15ADJ_L1_STEP_DN_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B) &                          \\\n\t BIT_MASK_V15ADJ_L1_STEP_DN_8814B)\n#define BIT_SET_V15ADJ_L1_STEP_DN_8814B(x, v)                                  \\\n\t(BIT_CLEAR_V15ADJ_L1_STEP_DN_8814B(x) | BIT_V15ADJ_L1_STEP_DN_8814B(v))\n\n#define BIT_REGU_32K_CLK_EN_8814B BIT(1)\n#define BIT_WL_LPS_EN_8814B BIT(0)\n\n/* 2 REG_AFE_CTRL5_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_GPIO_DEBOUNCE_CTRL_8814B */\n#define BIT_WLGP_DBC1EN_8814B BIT(15)\n\n#define BIT_SHIFT_WLGP_DBC1_8814B 8\n#define BIT_MASK_WLGP_DBC1_8814B 0xf\n#define BIT_WLGP_DBC1_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_WLGP_DBC1_8814B) << BIT_SHIFT_WLGP_DBC1_8814B)\n#define BITS_WLGP_DBC1_8814B                                                   \\\n\t(BIT_MASK_WLGP_DBC1_8814B << BIT_SHIFT_WLGP_DBC1_8814B)\n#define BIT_CLEAR_WLGP_DBC1_8814B(x) ((x) & (~BITS_WLGP_DBC1_8814B))\n#define BIT_GET_WLGP_DBC1_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_WLGP_DBC1_8814B) & BIT_MASK_WLGP_DBC1_8814B)\n#define BIT_SET_WLGP_DBC1_8814B(x, v)                                          \\\n\t(BIT_CLEAR_WLGP_DBC1_8814B(x) | BIT_WLGP_DBC1_8814B(v))\n\n#define BIT_WLGP_DBC0EN_8814B BIT(7)\n\n#define BIT_SHIFT_WLGP_DBC0_8814B 0\n#define BIT_MASK_WLGP_DBC0_8814B 0xf\n#define BIT_WLGP_DBC0_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_WLGP_DBC0_8814B) << BIT_SHIFT_WLGP_DBC0_8814B)\n#define BITS_WLGP_DBC0_8814B                                                   \\\n\t(BIT_MASK_WLGP_DBC0_8814B << BIT_SHIFT_WLGP_DBC0_8814B)\n#define BIT_CLEAR_WLGP_DBC0_8814B(x) ((x) & (~BITS_WLGP_DBC0_8814B))\n#define BIT_GET_WLGP_DBC0_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_WLGP_DBC0_8814B) & BIT_MASK_WLGP_DBC0_8814B)\n#define BIT_SET_WLGP_DBC0_8814B(x, v)                                          \\\n\t(BIT_CLEAR_WLGP_DBC0_8814B(x) | BIT_WLGP_DBC0_8814B(v))\n\n/* 2 REG_RPWM2_8814B */\n\n#define BIT_SHIFT_RPWM2_8814B 16\n#define BIT_MASK_RPWM2_8814B 0xffff\n#define BIT_RPWM2_8814B(x)                                                     \\\n\t(((x) & BIT_MASK_RPWM2_8814B) << BIT_SHIFT_RPWM2_8814B)\n#define BITS_RPWM2_8814B (BIT_MASK_RPWM2_8814B << BIT_SHIFT_RPWM2_8814B)\n#define BIT_CLEAR_RPWM2_8814B(x) ((x) & (~BITS_RPWM2_8814B))\n#define BIT_GET_RPWM2_8814B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RPWM2_8814B) & BIT_MASK_RPWM2_8814B)\n#define BIT_SET_RPWM2_8814B(x, v)                                              \\\n\t(BIT_CLEAR_RPWM2_8814B(x) | BIT_RPWM2_8814B(v))\n\n/* 2 REG_SYSON_FSM_MON_8814B */\n\n#define BIT_SHIFT_FSM_MON_SEL_8814B 24\n#define BIT_MASK_FSM_MON_SEL_8814B 0x7\n#define BIT_FSM_MON_SEL_8814B(x)                                               \\\n\t(((x) & BIT_MASK_FSM_MON_SEL_8814B) << BIT_SHIFT_FSM_MON_SEL_8814B)\n#define BITS_FSM_MON_SEL_8814B                                                 \\\n\t(BIT_MASK_FSM_MON_SEL_8814B << BIT_SHIFT_FSM_MON_SEL_8814B)\n#define BIT_CLEAR_FSM_MON_SEL_8814B(x) ((x) & (~BITS_FSM_MON_SEL_8814B))\n#define BIT_GET_FSM_MON_SEL_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_FSM_MON_SEL_8814B) & BIT_MASK_FSM_MON_SEL_8814B)\n#define BIT_SET_FSM_MON_SEL_8814B(x, v)                                        \\\n\t(BIT_CLEAR_FSM_MON_SEL_8814B(x) | BIT_FSM_MON_SEL_8814B(v))\n\n#define BIT_DOP_ELDO_8814B BIT(23)\n#define BIT_FSM_MON_UPD_8814B BIT(15)\n\n#define BIT_SHIFT_FSM_PAR_8814B 0\n#define BIT_MASK_FSM_PAR_8814B 0x7fff\n#define BIT_FSM_PAR_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_FSM_PAR_8814B) << BIT_SHIFT_FSM_PAR_8814B)\n#define BITS_FSM_PAR_8814B (BIT_MASK_FSM_PAR_8814B << BIT_SHIFT_FSM_PAR_8814B)\n#define BIT_CLEAR_FSM_PAR_8814B(x) ((x) & (~BITS_FSM_PAR_8814B))\n#define BIT_GET_FSM_PAR_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FSM_PAR_8814B) & BIT_MASK_FSM_PAR_8814B)\n#define BIT_SET_FSM_PAR_8814B(x, v)                                            \\\n\t(BIT_CLEAR_FSM_PAR_8814B(x) | BIT_FSM_PAR_8814B(v))\n\n/* 2 REG_AFE_CTRL6_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_PMC_DBG_CTRL1_8814B */\n#define BIT_BT_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B 16\n#define BIT_MASK_RD_WR_WIFI_BT_INFO_8814B 0x7fff\n#define BIT_RD_WR_WIFI_BT_INFO_8814B(x)                                        \\\n\t(((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8814B)                             \\\n\t << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B)\n#define BITS_RD_WR_WIFI_BT_INFO_8814B                                          \\\n\t(BIT_MASK_RD_WR_WIFI_BT_INFO_8814B                                     \\\n\t << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B)\n#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8814B(x)                                  \\\n\t((x) & (~BITS_RD_WR_WIFI_BT_INFO_8814B))\n#define BIT_GET_RD_WR_WIFI_BT_INFO_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B) &                         \\\n\t BIT_MASK_RD_WR_WIFI_BT_INFO_8814B)\n#define BIT_SET_RD_WR_WIFI_BT_INFO_8814B(x, v)                                 \\\n\t(BIT_CLEAR_RD_WR_WIFI_BT_INFO_8814B(x) |                               \\\n\t BIT_RD_WR_WIFI_BT_INFO_8814B(v))\n\n#define BIT_PMC_WR_OVF_8814B BIT(8)\n\n#define BIT_SHIFT_WLPMC_ERRINT_8814B 0\n#define BIT_MASK_WLPMC_ERRINT_8814B 0xff\n#define BIT_WLPMC_ERRINT_8814B(x)                                              \\\n\t(((x) & BIT_MASK_WLPMC_ERRINT_8814B) << BIT_SHIFT_WLPMC_ERRINT_8814B)\n#define BITS_WLPMC_ERRINT_8814B                                                \\\n\t(BIT_MASK_WLPMC_ERRINT_8814B << BIT_SHIFT_WLPMC_ERRINT_8814B)\n#define BIT_CLEAR_WLPMC_ERRINT_8814B(x) ((x) & (~BITS_WLPMC_ERRINT_8814B))\n#define BIT_GET_WLPMC_ERRINT_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_WLPMC_ERRINT_8814B) & BIT_MASK_WLPMC_ERRINT_8814B)\n#define BIT_SET_WLPMC_ERRINT_8814B(x, v)                                       \\\n\t(BIT_CLEAR_WLPMC_ERRINT_8814B(x) | BIT_WLPMC_ERRINT_8814B(v))\n\n/* 2 REG_AFE_CTRL7_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_HIMR0_8814B */\n#define BIT_PSTIMER_2_MSK_8814B BIT(31)\n#define BIT_PSTIMER_1_MSK_8814B BIT(30)\n#define BIT_PSTIMER_0_MSK_8814B BIT(29)\n#define BIT_GTINT4_MSK_8814B BIT(28)\n#define BIT_GTINT3_MSK_8814B BIT(27)\n#define BIT_TXBCN0ERR_MSK_8814B BIT(26)\n#define BIT_TXBCN0OK_MSK_8814B BIT(25)\n#define BIT_TSF_BIT32_TOGGLE_MSK_8814B BIT(24)\n#define BIT_TXDMA_START_INT_MSK_8814B BIT(23)\n#define BIT_TXDMA_STOP_INT_MSK_8814B BIT(22)\n#define BIT_HISR7_IND_MSK_8814B BIT(21)\n#define BIT_BCNDMAINT0_MSK_8814B BIT(20)\n#define BIT_HISR6_IND_MSK_8814B BIT(19)\n#define BIT_HISR5_IND_MSK_8814B BIT(18)\n#define BIT_HISR4_IND_MSK_8814B BIT(17)\n#define BIT_BCNDERR0_MSK_8814B BIT(16)\n#define BIT_HSISR_IND_ON_INT_MSK_8814B BIT(15)\n#define BIT_HISR3_IND_MSK_8814B BIT(14)\n#define BIT_HISR2_IND_MSK_8814B BIT(13)\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_HISR1_IND_MSK_8814B BIT(11)\n#define BIT_C2HCMD_MSK_8814B BIT(10)\n#define BIT_CPWM2_MSK_8814B BIT(9)\n#define BIT_CPWM_MSK_8814B BIT(8)\n#define BIT_TXDMAOK_CHANNEL15_MSK_8814B BIT(7)\n#define BIT_TXDMAOK_CHANNEL14_MSK_8814B BIT(6)\n#define BIT_TXDMAOK_CHANNEL3_MSK_8814B BIT(5)\n#define BIT_TXDMAOK_CHANNEL2_MSK_8814B BIT(4)\n#define BIT_TXDMAOK_CHANNEL1_MSK_8814B BIT(3)\n#define BIT_TXDMAOK_CHANNEL0_MSK_8814B BIT(2)\n#define BIT_RDU_MSK_8814B BIT(1)\n#define BIT_RXOK_MSK_8814B BIT(0)\n\n/* 2 REG_HISR0_8814B */\n#define BIT_PSTIMER_2_8814B BIT(31)\n#define BIT_PSTIMER_1_8814B BIT(30)\n#define BIT_PSTIMER_0_8814B BIT(29)\n#define BIT_GTINT4_8814B BIT(28)\n#define BIT_GTINT3_8814B BIT(27)\n#define BIT_TXBCN0ERR_8814B BIT(26)\n#define BIT_TXBCN0OK_8814B BIT(25)\n#define BIT_TSF_BIT32_TOGGLE_8814B BIT(24)\n#define BIT_TXDMA_START_INT_8814B BIT(23)\n#define BIT_TXDMA_STOP_INT_8814B BIT(22)\n#define BIT_HISR7_IND_8814B BIT(21)\n#define BIT_BCNDMAINT0_8814B BIT(20)\n#define BIT_HISR6_IND_8814B BIT(19)\n#define BIT_HISR5_IND_8814B BIT(18)\n#define BIT_HISR4_IND_8814B BIT(17)\n#define BIT_BCNDERR0_8814B BIT(16)\n#define BIT_HSISR_IND_ON_INT_8814B BIT(15)\n#define BIT_HISR3_IND_8814B BIT(14)\n#define BIT_HISR2_IND_8814B BIT(13)\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_HISR1_IND_8814B BIT(11)\n#define BIT_C2HCMD_8814B BIT(10)\n#define BIT_CPWM2_8814B BIT(9)\n#define BIT_CPWM_8814B BIT(8)\n#define BIT_TXDMAOK_CHANNEL15_8814B BIT(7)\n#define BIT_TXDMAOK_CHANNEL14_8814B BIT(6)\n#define BIT_TXDMAOK_CHANNEL3_8814B BIT(5)\n#define BIT_TXDMAOK_CHANNEL2_8814B BIT(4)\n#define BIT_TXDMAOK_CHANNEL1_8814B BIT(3)\n#define BIT_TXDMAOK_CHANNEL0_8814B BIT(2)\n#define BIT_RDU_8814B BIT(1)\n#define BIT_RXOK_8814B BIT(0)\n\n/* 2 REG_HIMR1_8814B */\n#define BIT_PRE_TX_ERR_INT_MSK_8814B BIT(31)\n#define BIT_TXFIFO_TH_INT_8814B BIT(30)\n#define BIT_BTON_STS_UPDATE_MASK_8814B BIT(29)\n#define BIT_BCNDMAINT7__MSK_8814B BIT(27)\n#define BIT_BCNDMAINT6__MSK_8814B BIT(26)\n#define BIT_BCNDMAINT5__MSK_8814B BIT(25)\n#define BIT_BCNDMAINT4__MSK_8814B BIT(24)\n#define BIT_BCNDMAINT3_MSK_8814B BIT(23)\n#define BIT_BCNDMAINT2_MSK_8814B BIT(22)\n#define BIT_BCNDMAINT1_MSK_8814B BIT(21)\n#define BIT_BCNDERR7_MSK_8814B BIT(20)\n#define BIT_BCNDERR6_MSK_8814B BIT(19)\n#define BIT_BCNDERR5_MSK_8814B BIT(18)\n#define BIT_BCNDERR4_MSK_8814B BIT(17)\n#define BIT_BCNDERR3_MSK_8814B BIT(16)\n#define BIT_BCNDERR2_MSK_8814B BIT(15)\n#define BIT_BCNDERR1_MSK_8814B BIT(14)\n#define BIT_ATIMEND__MSK_8814B BIT(12)\n#define BIT_TXERR_MSK_8814B BIT(11)\n#define BIT_RXERR_MSK_8814B BIT(10)\n#define BIT_TXFOVW_MSK_8814B BIT(9)\n#define BIT_FOVW_MSK_8814B BIT(8)\n#define BIT_CPU_MGQ_EARLY_INT_MSK_8814B BIT(6)\n#define BIT_CPU_MGQ_TXDONE_MSK_8814B BIT(5)\n#define BIT_PSTIMER_5_MSK_8814B BIT(4)\n#define BIT_PSTIMER_4_MSK_8814B BIT(3)\n#define BIT_PSTIMER_3_MSK_8814B BIT(2)\n#define BIT_CPUMGQ_TX_TIMER_MSK_8814B BIT(1)\n#define BIT_BB_STOPRX_INT_MSK_8814B BIT(0)\n\n/* 2 REG_HISR1_8814B */\n#define BIT_PRE_TX_ERR_INT_8814B BIT(31)\n#define BIT_TXFIFO_TH_INT_8814B BIT(30)\n#define BIT_BTON_STS_UPDATE_INT_8814B BIT(29)\n#define BIT_BCNDMAINT7_8814B BIT(27)\n#define BIT_BCNDMAINT6_8814B BIT(26)\n#define BIT_BCNDMAINT5_8814B BIT(25)\n#define BIT_BCNDMAINT4_8814B BIT(24)\n#define BIT_BCNDMAINT3_8814B BIT(23)\n#define BIT_BCNDMAINT2_8814B BIT(22)\n#define BIT_BCNDMAINT1_8814B BIT(21)\n#define BIT_BCNDERR7_8814B BIT(20)\n#define BIT_BCNDERR6_8814B BIT(19)\n#define BIT_BCNDERR5_8814B BIT(18)\n#define BIT_BCNDERR4_8814B BIT(17)\n#define BIT_BCNDERR3_8814B BIT(16)\n#define BIT_BCNDERR2_8814B BIT(15)\n#define BIT_BCNDERR1_8814B BIT(14)\n#define BIT_ATIMEND_8814B BIT(12)\n#define BIT_TXERR_INT_8814B BIT(11)\n#define BIT_RXERR_INT_8814B BIT(10)\n#define BIT_TXFOVW_8814B BIT(9)\n#define BIT_FOVW_8814B BIT(8)\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_CPU_MGQ_EARLY_INT_8814B BIT(6)\n#define BIT_CPU_MGQ_TXDONE_8814B BIT(5)\n#define BIT_PSTIMER_5_8814B BIT(4)\n#define BIT_PSTIMER_4_8814B BIT(3)\n#define BIT_PSTIMER_3_8814B BIT(2)\n#define BIT_CPUMGQ_TX_TIMER_8814B BIT(1)\n#define BIT_BB_STOPRX_INT_8814B BIT(0)\n\n/* 2 REG_DBG_PORT_SEL_8814B */\n\n#define BIT_SHIFT_DEBUG_ST_8814B 0\n#define BIT_MASK_DEBUG_ST_8814B 0xffffffffL\n#define BIT_DEBUG_ST_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_DEBUG_ST_8814B) << BIT_SHIFT_DEBUG_ST_8814B)\n#define BITS_DEBUG_ST_8814B                                                    \\\n\t(BIT_MASK_DEBUG_ST_8814B << BIT_SHIFT_DEBUG_ST_8814B)\n#define BIT_CLEAR_DEBUG_ST_8814B(x) ((x) & (~BITS_DEBUG_ST_8814B))\n#define BIT_GET_DEBUG_ST_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_DEBUG_ST_8814B) & BIT_MASK_DEBUG_ST_8814B)\n#define BIT_SET_DEBUG_ST_8814B(x, v)                                           \\\n\t(BIT_CLEAR_DEBUG_ST_8814B(x) | BIT_DEBUG_ST_8814B(v))\n\n/* 2 REG_PAD_CTRL2_8814B */\n#define BIT_USB3_USB2_TRANSITION_8814B BIT(20)\n\n#define BIT_SHIFT_USB23_SW_MODE_V1_8814B 18\n#define BIT_MASK_USB23_SW_MODE_V1_8814B 0x3\n#define BIT_USB23_SW_MODE_V1_8814B(x)                                          \\\n\t(((x) & BIT_MASK_USB23_SW_MODE_V1_8814B)                               \\\n\t << BIT_SHIFT_USB23_SW_MODE_V1_8814B)\n#define BITS_USB23_SW_MODE_V1_8814B                                            \\\n\t(BIT_MASK_USB23_SW_MODE_V1_8814B << BIT_SHIFT_USB23_SW_MODE_V1_8814B)\n#define BIT_CLEAR_USB23_SW_MODE_V1_8814B(x)                                    \\\n\t((x) & (~BITS_USB23_SW_MODE_V1_8814B))\n#define BIT_GET_USB23_SW_MODE_V1_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8814B) &                           \\\n\t BIT_MASK_USB23_SW_MODE_V1_8814B)\n#define BIT_SET_USB23_SW_MODE_V1_8814B(x, v)                                   \\\n\t(BIT_CLEAR_USB23_SW_MODE_V1_8814B(x) | BIT_USB23_SW_MODE_V1_8814B(v))\n\n#define BIT_NO_PDN_CHIPOFF_V1_8814B BIT(17)\n#define BIT_RSM_EN_V1_8814B BIT(16)\n\n#define BIT_SHIFT_MATCH_CNT_8814B 8\n#define BIT_MASK_MATCH_CNT_8814B 0xff\n#define BIT_MATCH_CNT_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_MATCH_CNT_8814B) << BIT_SHIFT_MATCH_CNT_8814B)\n#define BITS_MATCH_CNT_8814B                                                   \\\n\t(BIT_MASK_MATCH_CNT_8814B << BIT_SHIFT_MATCH_CNT_8814B)\n#define BIT_CLEAR_MATCH_CNT_8814B(x) ((x) & (~BITS_MATCH_CNT_8814B))\n#define BIT_GET_MATCH_CNT_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_MATCH_CNT_8814B) & BIT_MASK_MATCH_CNT_8814B)\n#define BIT_SET_MATCH_CNT_8814B(x, v)                                          \\\n\t(BIT_CLEAR_MATCH_CNT_8814B(x) | BIT_MATCH_CNT_8814B(v))\n\n#define BIT_LD_B12V_EN_8814B BIT(7)\n#define BIT_EECS_IOSEL_V1_8814B BIT(6)\n#define BIT_EECS_DATA_O_V1_8814B BIT(5)\n#define BIT_EECS_DATA_I_V1_8814B BIT(4)\n#define BIT_EESK_IOSEL_V1_8814B BIT(2)\n#define BIT_EESK_DATA_O_V1_8814B BIT(1)\n#define BIT_EESK_DATA_I_V1_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_PMC_DBG_CTRL2_8814B */\n\n#define BIT_SHIFT_EFUSE_BURN_GNT_8814B 24\n#define BIT_MASK_EFUSE_BURN_GNT_8814B 0xff\n#define BIT_EFUSE_BURN_GNT_8814B(x)                                            \\\n\t(((x) & BIT_MASK_EFUSE_BURN_GNT_8814B)                                 \\\n\t << BIT_SHIFT_EFUSE_BURN_GNT_8814B)\n#define BITS_EFUSE_BURN_GNT_8814B                                              \\\n\t(BIT_MASK_EFUSE_BURN_GNT_8814B << BIT_SHIFT_EFUSE_BURN_GNT_8814B)\n#define BIT_CLEAR_EFUSE_BURN_GNT_8814B(x) ((x) & (~BITS_EFUSE_BURN_GNT_8814B))\n#define BIT_GET_EFUSE_BURN_GNT_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8814B) &                             \\\n\t BIT_MASK_EFUSE_BURN_GNT_8814B)\n#define BIT_SET_EFUSE_BURN_GNT_8814B(x, v)                                     \\\n\t(BIT_CLEAR_EFUSE_BURN_GNT_8814B(x) | BIT_EFUSE_BURN_GNT_8814B(v))\n\n#define BIT_STOP_WL_PMC_8814B BIT(9)\n#define BIT_STOP_SYM_PMC_8814B BIT(8)\n#define BIT_BT_ACCESS_WL_PAGE0_8814B BIT(6)\n#define BIT_REG_RST_WLPMC_8814B BIT(5)\n#define BIT_REG_RST_PD12N_8814B BIT(4)\n#define BIT_SYSON_DIS_WLREG_WRMSK_8814B BIT(3)\n#define BIT_SYSON_DIS_PMCREG_WRMSK_8814B BIT(2)\n\n#define BIT_SHIFT_SYSON_REG_ARB_8814B 0\n#define BIT_MASK_SYSON_REG_ARB_8814B 0x3\n#define BIT_SYSON_REG_ARB_8814B(x)                                             \\\n\t(((x) & BIT_MASK_SYSON_REG_ARB_8814B) << BIT_SHIFT_SYSON_REG_ARB_8814B)\n#define BITS_SYSON_REG_ARB_8814B                                               \\\n\t(BIT_MASK_SYSON_REG_ARB_8814B << BIT_SHIFT_SYSON_REG_ARB_8814B)\n#define BIT_CLEAR_SYSON_REG_ARB_8814B(x) ((x) & (~BITS_SYSON_REG_ARB_8814B))\n#define BIT_GET_SYSON_REG_ARB_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SYSON_REG_ARB_8814B) & BIT_MASK_SYSON_REG_ARB_8814B)\n#define BIT_SET_SYSON_REG_ARB_8814B(x, v)                                      \\\n\t(BIT_CLEAR_SYSON_REG_ARB_8814B(x) | BIT_SYSON_REG_ARB_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_MEM_CTRL_8814B */\n#define BIT_UMEM_RME_8814B BIT(31)\n\n#define BIT_SHIFT_BT_SPRAM_8814B 28\n#define BIT_MASK_BT_SPRAM_8814B 0x3\n#define BIT_BT_SPRAM_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_BT_SPRAM_8814B) << BIT_SHIFT_BT_SPRAM_8814B)\n#define BITS_BT_SPRAM_8814B                                                    \\\n\t(BIT_MASK_BT_SPRAM_8814B << BIT_SHIFT_BT_SPRAM_8814B)\n#define BIT_CLEAR_BT_SPRAM_8814B(x) ((x) & (~BITS_BT_SPRAM_8814B))\n#define BIT_GET_BT_SPRAM_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_BT_SPRAM_8814B) & BIT_MASK_BT_SPRAM_8814B)\n#define BIT_SET_BT_SPRAM_8814B(x, v)                                           \\\n\t(BIT_CLEAR_BT_SPRAM_8814B(x) | BIT_BT_SPRAM_8814B(v))\n\n#define BIT_SHIFT_BT_ROM_8814B 24\n#define BIT_MASK_BT_ROM_8814B 0xf\n#define BIT_BT_ROM_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_BT_ROM_8814B) << BIT_SHIFT_BT_ROM_8814B)\n#define BITS_BT_ROM_8814B (BIT_MASK_BT_ROM_8814B << BIT_SHIFT_BT_ROM_8814B)\n#define BIT_CLEAR_BT_ROM_8814B(x) ((x) & (~BITS_BT_ROM_8814B))\n#define BIT_GET_BT_ROM_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_BT_ROM_8814B) & BIT_MASK_BT_ROM_8814B)\n#define BIT_SET_BT_ROM_8814B(x, v)                                             \\\n\t(BIT_CLEAR_BT_ROM_8814B(x) | BIT_BT_ROM_8814B(v))\n\n#define BIT_SHIFT_PCI_DPRAM_8814B 10\n#define BIT_MASK_PCI_DPRAM_8814B 0x3\n#define BIT_PCI_DPRAM_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_PCI_DPRAM_8814B) << BIT_SHIFT_PCI_DPRAM_8814B)\n#define BITS_PCI_DPRAM_8814B                                                   \\\n\t(BIT_MASK_PCI_DPRAM_8814B << BIT_SHIFT_PCI_DPRAM_8814B)\n#define BIT_CLEAR_PCI_DPRAM_8814B(x) ((x) & (~BITS_PCI_DPRAM_8814B))\n#define BIT_GET_PCI_DPRAM_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_PCI_DPRAM_8814B) & BIT_MASK_PCI_DPRAM_8814B)\n#define BIT_SET_PCI_DPRAM_8814B(x, v)                                          \\\n\t(BIT_CLEAR_PCI_DPRAM_8814B(x) | BIT_PCI_DPRAM_8814B(v))\n\n#define BIT_SHIFT_PCI_SPRAM_8814B 8\n#define BIT_MASK_PCI_SPRAM_8814B 0x3\n#define BIT_PCI_SPRAM_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_PCI_SPRAM_8814B) << BIT_SHIFT_PCI_SPRAM_8814B)\n#define BITS_PCI_SPRAM_8814B                                                   \\\n\t(BIT_MASK_PCI_SPRAM_8814B << BIT_SHIFT_PCI_SPRAM_8814B)\n#define BIT_CLEAR_PCI_SPRAM_8814B(x) ((x) & (~BITS_PCI_SPRAM_8814B))\n#define BIT_GET_PCI_SPRAM_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_PCI_SPRAM_8814B) & BIT_MASK_PCI_SPRAM_8814B)\n#define BIT_SET_PCI_SPRAM_8814B(x, v)                                          \\\n\t(BIT_CLEAR_PCI_SPRAM_8814B(x) | BIT_PCI_SPRAM_8814B(v))\n\n#define BIT_SHIFT_USB_SPRAM_8814B 6\n#define BIT_MASK_USB_SPRAM_8814B 0x3\n#define BIT_USB_SPRAM_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_USB_SPRAM_8814B) << BIT_SHIFT_USB_SPRAM_8814B)\n#define BITS_USB_SPRAM_8814B                                                   \\\n\t(BIT_MASK_USB_SPRAM_8814B << BIT_SHIFT_USB_SPRAM_8814B)\n#define BIT_CLEAR_USB_SPRAM_8814B(x) ((x) & (~BITS_USB_SPRAM_8814B))\n#define BIT_GET_USB_SPRAM_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_USB_SPRAM_8814B) & BIT_MASK_USB_SPRAM_8814B)\n#define BIT_SET_USB_SPRAM_8814B(x, v)                                          \\\n\t(BIT_CLEAR_USB_SPRAM_8814B(x) | BIT_USB_SPRAM_8814B(v))\n\n#define BIT_SHIFT_USB_SPRF_8814B 4\n#define BIT_MASK_USB_SPRF_8814B 0x3\n#define BIT_USB_SPRF_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_USB_SPRF_8814B) << BIT_SHIFT_USB_SPRF_8814B)\n#define BITS_USB_SPRF_8814B                                                    \\\n\t(BIT_MASK_USB_SPRF_8814B << BIT_SHIFT_USB_SPRF_8814B)\n#define BIT_CLEAR_USB_SPRF_8814B(x) ((x) & (~BITS_USB_SPRF_8814B))\n#define BIT_GET_USB_SPRF_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_USB_SPRF_8814B) & BIT_MASK_USB_SPRF_8814B)\n#define BIT_SET_USB_SPRF_8814B(x, v)                                           \\\n\t(BIT_CLEAR_USB_SPRF_8814B(x) | BIT_USB_SPRF_8814B(v))\n\n#define BIT_SHIFT_MCU_ROM_8814B 0\n#define BIT_MASK_MCU_ROM_8814B 0xf\n#define BIT_MCU_ROM_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_MCU_ROM_8814B) << BIT_SHIFT_MCU_ROM_8814B)\n#define BITS_MCU_ROM_8814B (BIT_MASK_MCU_ROM_8814B << BIT_SHIFT_MCU_ROM_8814B)\n#define BIT_CLEAR_MCU_ROM_8814B(x) ((x) & (~BITS_MCU_ROM_8814B))\n#define BIT_GET_MCU_ROM_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_MCU_ROM_8814B) & BIT_MASK_MCU_ROM_8814B)\n#define BIT_SET_MCU_ROM_8814B(x, v)                                            \\\n\t(BIT_CLEAR_MCU_ROM_8814B(x) | BIT_MCU_ROM_8814B(v))\n\n/* 2 REG_SYN_RFC_CTRL_8814B */\n\n#define BIT_SHIFT_SYN_RF1_CTRL_8814B 8\n#define BIT_MASK_SYN_RF1_CTRL_8814B 0xff\n#define BIT_SYN_RF1_CTRL_8814B(x)                                              \\\n\t(((x) & BIT_MASK_SYN_RF1_CTRL_8814B) << BIT_SHIFT_SYN_RF1_CTRL_8814B)\n#define BITS_SYN_RF1_CTRL_8814B                                                \\\n\t(BIT_MASK_SYN_RF1_CTRL_8814B << BIT_SHIFT_SYN_RF1_CTRL_8814B)\n#define BIT_CLEAR_SYN_RF1_CTRL_8814B(x) ((x) & (~BITS_SYN_RF1_CTRL_8814B))\n#define BIT_GET_SYN_RF1_CTRL_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SYN_RF1_CTRL_8814B) & BIT_MASK_SYN_RF1_CTRL_8814B)\n#define BIT_SET_SYN_RF1_CTRL_8814B(x, v)                                       \\\n\t(BIT_CLEAR_SYN_RF1_CTRL_8814B(x) | BIT_SYN_RF1_CTRL_8814B(v))\n\n#define BIT_SHIFT_SYN_RF0_CTRL_8814B 0\n#define BIT_MASK_SYN_RF0_CTRL_8814B 0xff\n#define BIT_SYN_RF0_CTRL_8814B(x)                                              \\\n\t(((x) & BIT_MASK_SYN_RF0_CTRL_8814B) << BIT_SHIFT_SYN_RF0_CTRL_8814B)\n#define BITS_SYN_RF0_CTRL_8814B                                                \\\n\t(BIT_MASK_SYN_RF0_CTRL_8814B << BIT_SHIFT_SYN_RF0_CTRL_8814B)\n#define BIT_CLEAR_SYN_RF0_CTRL_8814B(x) ((x) & (~BITS_SYN_RF0_CTRL_8814B))\n#define BIT_GET_SYN_RF0_CTRL_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SYN_RF0_CTRL_8814B) & BIT_MASK_SYN_RF0_CTRL_8814B)\n#define BIT_SET_SYN_RF0_CTRL_8814B(x, v)                                       \\\n\t(BIT_CLEAR_SYN_RF0_CTRL_8814B(x) | BIT_SYN_RF0_CTRL_8814B(v))\n\n/* 2 REG_USB_SIE_INTF_8814B */\n#define BIT_RD_SEL_8814B BIT(31)\n#define BIT_USB_SIE_INTF_WE_V1_8814B BIT(30)\n#define BIT_USB_SIE_INTF_BYIOREG_V1_8814B BIT(29)\n#define BIT_USB_SIE_SELECT_8814B BIT(28)\n\n#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B 16\n#define BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B 0x1ff\n#define BIT_USB_SIE_INTF_ADDR_V1_8814B(x)                                      \\\n\t(((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B)                           \\\n\t << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B)\n#define BITS_USB_SIE_INTF_ADDR_V1_8814B                                        \\\n\t(BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B                                   \\\n\t << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B)\n#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8814B(x)                                \\\n\t((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8814B))\n#define BIT_GET_USB_SIE_INTF_ADDR_V1_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B) &                       \\\n\t BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B)\n#define BIT_SET_USB_SIE_INTF_ADDR_V1_8814B(x, v)                               \\\n\t(BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8814B(x) |                             \\\n\t BIT_USB_SIE_INTF_ADDR_V1_8814B(v))\n\n#define BIT_SHIFT_USB_SIE_INTF_RD_8814B 8\n#define BIT_MASK_USB_SIE_INTF_RD_8814B 0xff\n#define BIT_USB_SIE_INTF_RD_8814B(x)                                           \\\n\t(((x) & BIT_MASK_USB_SIE_INTF_RD_8814B)                                \\\n\t << BIT_SHIFT_USB_SIE_INTF_RD_8814B)\n#define BITS_USB_SIE_INTF_RD_8814B                                             \\\n\t(BIT_MASK_USB_SIE_INTF_RD_8814B << BIT_SHIFT_USB_SIE_INTF_RD_8814B)\n#define BIT_CLEAR_USB_SIE_INTF_RD_8814B(x) ((x) & (~BITS_USB_SIE_INTF_RD_8814B))\n#define BIT_GET_USB_SIE_INTF_RD_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8814B) &                            \\\n\t BIT_MASK_USB_SIE_INTF_RD_8814B)\n#define BIT_SET_USB_SIE_INTF_RD_8814B(x, v)                                    \\\n\t(BIT_CLEAR_USB_SIE_INTF_RD_8814B(x) | BIT_USB_SIE_INTF_RD_8814B(v))\n\n#define BIT_SHIFT_USB_SIE_INTF_WD_8814B 0\n#define BIT_MASK_USB_SIE_INTF_WD_8814B 0xff\n#define BIT_USB_SIE_INTF_WD_8814B(x)                                           \\\n\t(((x) & BIT_MASK_USB_SIE_INTF_WD_8814B)                                \\\n\t << BIT_SHIFT_USB_SIE_INTF_WD_8814B)\n#define BITS_USB_SIE_INTF_WD_8814B                                             \\\n\t(BIT_MASK_USB_SIE_INTF_WD_8814B << BIT_SHIFT_USB_SIE_INTF_WD_8814B)\n#define BIT_CLEAR_USB_SIE_INTF_WD_8814B(x) ((x) & (~BITS_USB_SIE_INTF_WD_8814B))\n#define BIT_GET_USB_SIE_INTF_WD_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8814B) &                            \\\n\t BIT_MASK_USB_SIE_INTF_WD_8814B)\n#define BIT_SET_USB_SIE_INTF_WD_8814B(x, v)                                    \\\n\t(BIT_CLEAR_USB_SIE_INTF_WD_8814B(x) | BIT_USB_SIE_INTF_WD_8814B(v))\n\n/* 2 REG_PCIE_MIO_INTF_8814B */\n\n#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B 16\n#define BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B 0x3\n#define BIT_PCIE_MIO_ADDR_PAGE_8814B(x)                                        \\\n\t(((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B)                             \\\n\t << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B)\n#define BITS_PCIE_MIO_ADDR_PAGE_8814B                                          \\\n\t(BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B                                     \\\n\t << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B)\n#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8814B(x)                                  \\\n\t((x) & (~BITS_PCIE_MIO_ADDR_PAGE_8814B))\n#define BIT_GET_PCIE_MIO_ADDR_PAGE_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B) &                         \\\n\t BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B)\n#define BIT_SET_PCIE_MIO_ADDR_PAGE_8814B(x, v)                                 \\\n\t(BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8814B(x) |                               \\\n\t BIT_PCIE_MIO_ADDR_PAGE_8814B(v))\n\n#define BIT_PCIE_MIO_BYIOREG_8814B BIT(13)\n#define BIT_PCIE_MIO_RE_8814B BIT(12)\n\n#define BIT_SHIFT_PCIE_MIO_WE_8814B 8\n#define BIT_MASK_PCIE_MIO_WE_8814B 0xf\n#define BIT_PCIE_MIO_WE_8814B(x)                                               \\\n\t(((x) & BIT_MASK_PCIE_MIO_WE_8814B) << BIT_SHIFT_PCIE_MIO_WE_8814B)\n#define BITS_PCIE_MIO_WE_8814B                                                 \\\n\t(BIT_MASK_PCIE_MIO_WE_8814B << BIT_SHIFT_PCIE_MIO_WE_8814B)\n#define BIT_CLEAR_PCIE_MIO_WE_8814B(x) ((x) & (~BITS_PCIE_MIO_WE_8814B))\n#define BIT_GET_PCIE_MIO_WE_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_WE_8814B) & BIT_MASK_PCIE_MIO_WE_8814B)\n#define BIT_SET_PCIE_MIO_WE_8814B(x, v)                                        \\\n\t(BIT_CLEAR_PCIE_MIO_WE_8814B(x) | BIT_PCIE_MIO_WE_8814B(v))\n\n#define BIT_SHIFT_PCIE_MIO_ADDR_8814B 0\n#define BIT_MASK_PCIE_MIO_ADDR_8814B 0xff\n#define BIT_PCIE_MIO_ADDR_8814B(x)                                             \\\n\t(((x) & BIT_MASK_PCIE_MIO_ADDR_8814B) << BIT_SHIFT_PCIE_MIO_ADDR_8814B)\n#define BITS_PCIE_MIO_ADDR_8814B                                               \\\n\t(BIT_MASK_PCIE_MIO_ADDR_8814B << BIT_SHIFT_PCIE_MIO_ADDR_8814B)\n#define BIT_CLEAR_PCIE_MIO_ADDR_8814B(x) ((x) & (~BITS_PCIE_MIO_ADDR_8814B))\n#define BIT_GET_PCIE_MIO_ADDR_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8814B) & BIT_MASK_PCIE_MIO_ADDR_8814B)\n#define BIT_SET_PCIE_MIO_ADDR_8814B(x, v)                                      \\\n\t(BIT_CLEAR_PCIE_MIO_ADDR_8814B(x) | BIT_PCIE_MIO_ADDR_8814B(v))\n\n/* 2 REG_PCIE_MIO_INTD_8814B */\n\n#define BIT_SHIFT_PCIE_MIO_DATA_8814B 0\n#define BIT_MASK_PCIE_MIO_DATA_8814B 0xffffffffL\n#define BIT_PCIE_MIO_DATA_8814B(x)                                             \\\n\t(((x) & BIT_MASK_PCIE_MIO_DATA_8814B) << BIT_SHIFT_PCIE_MIO_DATA_8814B)\n#define BITS_PCIE_MIO_DATA_8814B                                               \\\n\t(BIT_MASK_PCIE_MIO_DATA_8814B << BIT_SHIFT_PCIE_MIO_DATA_8814B)\n#define BIT_CLEAR_PCIE_MIO_DATA_8814B(x) ((x) & (~BITS_PCIE_MIO_DATA_8814B))\n#define BIT_GET_PCIE_MIO_DATA_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_DATA_8814B) & BIT_MASK_PCIE_MIO_DATA_8814B)\n#define BIT_SET_PCIE_MIO_DATA_8814B(x, v)                                      \\\n\t(BIT_CLEAR_PCIE_MIO_DATA_8814B(x) | BIT_PCIE_MIO_DATA_8814B(v))\n\n/* 2 REG_WLRF1_8814B */\n\n#define BIT_SHIFT_WLRF1_CTRL_8814B 24\n#define BIT_MASK_WLRF1_CTRL_8814B 0xff\n#define BIT_WLRF1_CTRL_8814B(x)                                                \\\n\t(((x) & BIT_MASK_WLRF1_CTRL_8814B) << BIT_SHIFT_WLRF1_CTRL_8814B)\n#define BITS_WLRF1_CTRL_8814B                                                  \\\n\t(BIT_MASK_WLRF1_CTRL_8814B << BIT_SHIFT_WLRF1_CTRL_8814B)\n#define BIT_CLEAR_WLRF1_CTRL_8814B(x) ((x) & (~BITS_WLRF1_CTRL_8814B))\n#define BIT_GET_WLRF1_CTRL_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_WLRF1_CTRL_8814B) & BIT_MASK_WLRF1_CTRL_8814B)\n#define BIT_SET_WLRF1_CTRL_8814B(x, v)                                         \\\n\t(BIT_CLEAR_WLRF1_CTRL_8814B(x) | BIT_WLRF1_CTRL_8814B(v))\n\n#define BIT_SHIFT_WLRF2_CTRL_8814B 16\n#define BIT_MASK_WLRF2_CTRL_8814B 0xff\n#define BIT_WLRF2_CTRL_8814B(x)                                                \\\n\t(((x) & BIT_MASK_WLRF2_CTRL_8814B) << BIT_SHIFT_WLRF2_CTRL_8814B)\n#define BITS_WLRF2_CTRL_8814B                                                  \\\n\t(BIT_MASK_WLRF2_CTRL_8814B << BIT_SHIFT_WLRF2_CTRL_8814B)\n#define BIT_CLEAR_WLRF2_CTRL_8814B(x) ((x) & (~BITS_WLRF2_CTRL_8814B))\n#define BIT_GET_WLRF2_CTRL_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_WLRF2_CTRL_8814B) & BIT_MASK_WLRF2_CTRL_8814B)\n#define BIT_SET_WLRF2_CTRL_8814B(x, v)                                         \\\n\t(BIT_CLEAR_WLRF2_CTRL_8814B(x) | BIT_WLRF2_CTRL_8814B(v))\n\n#define BIT_SHIFT_WLRF3_CTRL_8814B 8\n#define BIT_MASK_WLRF3_CTRL_8814B 0xff\n#define BIT_WLRF3_CTRL_8814B(x)                                                \\\n\t(((x) & BIT_MASK_WLRF3_CTRL_8814B) << BIT_SHIFT_WLRF3_CTRL_8814B)\n#define BITS_WLRF3_CTRL_8814B                                                  \\\n\t(BIT_MASK_WLRF3_CTRL_8814B << BIT_SHIFT_WLRF3_CTRL_8814B)\n#define BIT_CLEAR_WLRF3_CTRL_8814B(x) ((x) & (~BITS_WLRF3_CTRL_8814B))\n#define BIT_GET_WLRF3_CTRL_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_WLRF3_CTRL_8814B) & BIT_MASK_WLRF3_CTRL_8814B)\n#define BIT_SET_WLRF3_CTRL_8814B(x, v)                                         \\\n\t(BIT_CLEAR_WLRF3_CTRL_8814B(x) | BIT_WLRF3_CTRL_8814B(v))\n\n/* 2 REG_SYS_CFG1_8814B */\n\n#define BIT_SHIFT_TRP_ICFG_8814B 28\n#define BIT_MASK_TRP_ICFG_8814B 0xf\n#define BIT_TRP_ICFG_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_TRP_ICFG_8814B) << BIT_SHIFT_TRP_ICFG_8814B)\n#define BITS_TRP_ICFG_8814B                                                    \\\n\t(BIT_MASK_TRP_ICFG_8814B << BIT_SHIFT_TRP_ICFG_8814B)\n#define BIT_CLEAR_TRP_ICFG_8814B(x) ((x) & (~BITS_TRP_ICFG_8814B))\n#define BIT_GET_TRP_ICFG_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TRP_ICFG_8814B) & BIT_MASK_TRP_ICFG_8814B)\n#define BIT_SET_TRP_ICFG_8814B(x, v)                                           \\\n\t(BIT_CLEAR_TRP_ICFG_8814B(x) | BIT_TRP_ICFG_8814B(v))\n\n#define BIT_RF_TYPE_ID_8814B BIT(27)\n#define BIT_BD_HCI_SEL_8814B BIT(26)\n#define BIT_BD_PKG_SEL_8814B BIT(25)\n#define BIT_SPSLDO_SEL_8814B BIT(24)\n#define BIT_RTL_ID_8814B BIT(23)\n#define BIT_PAD_HWPD_IDN_8814B BIT(22)\n#define BIT_TESTMODE_8814B BIT(20)\n\n#define BIT_SHIFT_VENDOR_ID_8814B 16\n#define BIT_MASK_VENDOR_ID_8814B 0xf\n#define BIT_VENDOR_ID_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_VENDOR_ID_8814B) << BIT_SHIFT_VENDOR_ID_8814B)\n#define BITS_VENDOR_ID_8814B                                                   \\\n\t(BIT_MASK_VENDOR_ID_8814B << BIT_SHIFT_VENDOR_ID_8814B)\n#define BIT_CLEAR_VENDOR_ID_8814B(x) ((x) & (~BITS_VENDOR_ID_8814B))\n#define BIT_GET_VENDOR_ID_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_VENDOR_ID_8814B) & BIT_MASK_VENDOR_ID_8814B)\n#define BIT_SET_VENDOR_ID_8814B(x, v)                                          \\\n\t(BIT_CLEAR_VENDOR_ID_8814B(x) | BIT_VENDOR_ID_8814B(v))\n\n#define BIT_SHIFT_CHIP_VER_8814B 12\n#define BIT_MASK_CHIP_VER_8814B 0xf\n#define BIT_CHIP_VER_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_CHIP_VER_8814B) << BIT_SHIFT_CHIP_VER_8814B)\n#define BITS_CHIP_VER_8814B                                                    \\\n\t(BIT_MASK_CHIP_VER_8814B << BIT_SHIFT_CHIP_VER_8814B)\n#define BIT_CLEAR_CHIP_VER_8814B(x) ((x) & (~BITS_CHIP_VER_8814B))\n#define BIT_GET_CHIP_VER_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_CHIP_VER_8814B) & BIT_MASK_CHIP_VER_8814B)\n#define BIT_SET_CHIP_VER_8814B(x, v)                                           \\\n\t(BIT_CLEAR_CHIP_VER_8814B(x) | BIT_CHIP_VER_8814B(v))\n\n#define BIT_BD_MAC3_8814B BIT(11)\n#define BIT_BD_MAC1_8814B BIT(10)\n#define BIT_BD_MAC2_8814B BIT(9)\n#define BIT_SIC_IDLE_8814B BIT(8)\n#define BIT_SW_OFFLOAD_EN_8814B BIT(7)\n#define BIT_OCP_SHUTDN_8814B BIT(6)\n#define BIT_V15_VLD_8814B BIT(5)\n#define BIT_PCIRSTB_8814B BIT(4)\n#define BIT_PCLK_VLD_8814B BIT(3)\n#define BIT_UCLK_VLD_8814B BIT(2)\n#define BIT_ACLK_VLD_8814B BIT(1)\n#define BIT_XCLK_VLD_8814B BIT(0)\n\n/* 2 REG_SYS_STATUS1_8814B */\n\n#define BIT_SHIFT_RF_RL_ID_8814B 28\n#define BIT_MASK_RF_RL_ID_8814B 0xf\n#define BIT_RF_RL_ID_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_RF_RL_ID_8814B) << BIT_SHIFT_RF_RL_ID_8814B)\n#define BITS_RF_RL_ID_8814B                                                    \\\n\t(BIT_MASK_RF_RL_ID_8814B << BIT_SHIFT_RF_RL_ID_8814B)\n#define BIT_CLEAR_RF_RL_ID_8814B(x) ((x) & (~BITS_RF_RL_ID_8814B))\n#define BIT_GET_RF_RL_ID_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RF_RL_ID_8814B) & BIT_MASK_RF_RL_ID_8814B)\n#define BIT_SET_RF_RL_ID_8814B(x, v)                                           \\\n\t(BIT_CLEAR_RF_RL_ID_8814B(x) | BIT_RF_RL_ID_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_XTAL_SEL_8814B 25\n#define BIT_MASK_XTAL_SEL_8814B 0x3\n#define BIT_XTAL_SEL_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_XTAL_SEL_8814B) << BIT_SHIFT_XTAL_SEL_8814B)\n#define BITS_XTAL_SEL_8814B                                                    \\\n\t(BIT_MASK_XTAL_SEL_8814B << BIT_SHIFT_XTAL_SEL_8814B)\n#define BIT_CLEAR_XTAL_SEL_8814B(x) ((x) & (~BITS_XTAL_SEL_8814B))\n#define BIT_GET_XTAL_SEL_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_XTAL_SEL_8814B) & BIT_MASK_XTAL_SEL_8814B)\n#define BIT_SET_XTAL_SEL_8814B(x, v)                                           \\\n\t(BIT_CLEAR_XTAL_SEL_8814B(x) | BIT_XTAL_SEL_8814B(v))\n\n#define BIT_HPHY_ICFG_8814B BIT(19)\n\n#define BIT_SHIFT_SEL_0XC0_8814B 16\n#define BIT_MASK_SEL_0XC0_8814B 0x3\n#define BIT_SEL_0XC0_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_SEL_0XC0_8814B) << BIT_SHIFT_SEL_0XC0_8814B)\n#define BITS_SEL_0XC0_8814B                                                    \\\n\t(BIT_MASK_SEL_0XC0_8814B << BIT_SHIFT_SEL_0XC0_8814B)\n#define BIT_CLEAR_SEL_0XC0_8814B(x) ((x) & (~BITS_SEL_0XC0_8814B))\n#define BIT_GET_SEL_0XC0_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_SEL_0XC0_8814B) & BIT_MASK_SEL_0XC0_8814B)\n#define BIT_SET_SEL_0XC0_8814B(x, v)                                           \\\n\t(BIT_CLEAR_SEL_0XC0_8814B(x) | BIT_SEL_0XC0_8814B(v))\n\n#define BIT_SHIFT_HCI_SEL_V4_8814B 12\n#define BIT_MASK_HCI_SEL_V4_8814B 0x3\n#define BIT_HCI_SEL_V4_8814B(x)                                                \\\n\t(((x) & BIT_MASK_HCI_SEL_V4_8814B) << BIT_SHIFT_HCI_SEL_V4_8814B)\n#define BITS_HCI_SEL_V4_8814B                                                  \\\n\t(BIT_MASK_HCI_SEL_V4_8814B << BIT_SHIFT_HCI_SEL_V4_8814B)\n#define BIT_CLEAR_HCI_SEL_V4_8814B(x) ((x) & (~BITS_HCI_SEL_V4_8814B))\n#define BIT_GET_HCI_SEL_V4_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_HCI_SEL_V4_8814B) & BIT_MASK_HCI_SEL_V4_8814B)\n#define BIT_SET_HCI_SEL_V4_8814B(x, v)                                         \\\n\t(BIT_CLEAR_HCI_SEL_V4_8814B(x) | BIT_HCI_SEL_V4_8814B(v))\n\n#define BIT_USB_OPERATION_MODE_8814B BIT(10)\n#define BIT_BT_PDN_8814B BIT(9)\n#define BIT_AUTO_WLPON_8814B BIT(8)\n#define BIT_WL_MODE_8814B BIT(7)\n#define BIT_PKG_SEL_HCI_8814B BIT(6)\n\n#define BIT_SHIFT_PAD_HCI_SEL_V2_8814B 3\n#define BIT_MASK_PAD_HCI_SEL_V2_8814B 0x3\n#define BIT_PAD_HCI_SEL_V2_8814B(x)                                            \\\n\t(((x) & BIT_MASK_PAD_HCI_SEL_V2_8814B)                                 \\\n\t << BIT_SHIFT_PAD_HCI_SEL_V2_8814B)\n#define BITS_PAD_HCI_SEL_V2_8814B                                              \\\n\t(BIT_MASK_PAD_HCI_SEL_V2_8814B << BIT_SHIFT_PAD_HCI_SEL_V2_8814B)\n#define BIT_CLEAR_PAD_HCI_SEL_V2_8814B(x) ((x) & (~BITS_PAD_HCI_SEL_V2_8814B))\n#define BIT_GET_PAD_HCI_SEL_V2_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_PAD_HCI_SEL_V2_8814B) &                             \\\n\t BIT_MASK_PAD_HCI_SEL_V2_8814B)\n#define BIT_SET_PAD_HCI_SEL_V2_8814B(x, v)                                     \\\n\t(BIT_CLEAR_PAD_HCI_SEL_V2_8814B(x) | BIT_PAD_HCI_SEL_V2_8814B(v))\n\n#define BIT_SHIFT_EFS_HCI_SEL_8814B 0\n#define BIT_MASK_EFS_HCI_SEL_8814B 0x3\n#define BIT_EFS_HCI_SEL_8814B(x)                                               \\\n\t(((x) & BIT_MASK_EFS_HCI_SEL_8814B) << BIT_SHIFT_EFS_HCI_SEL_8814B)\n#define BITS_EFS_HCI_SEL_8814B                                                 \\\n\t(BIT_MASK_EFS_HCI_SEL_8814B << BIT_SHIFT_EFS_HCI_SEL_8814B)\n#define BIT_CLEAR_EFS_HCI_SEL_8814B(x) ((x) & (~BITS_EFS_HCI_SEL_8814B))\n#define BIT_GET_EFS_HCI_SEL_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_EFS_HCI_SEL_8814B) & BIT_MASK_EFS_HCI_SEL_8814B)\n#define BIT_SET_EFS_HCI_SEL_8814B(x, v)                                        \\\n\t(BIT_CLEAR_EFS_HCI_SEL_8814B(x) | BIT_EFS_HCI_SEL_8814B(v))\n\n/* 2 REG_SYS_STATUS2_8814B */\n#define BIT_SIO_ALDN_8814B BIT(19)\n#define BIT_USB_ALDN_8814B BIT(18)\n#define BIT_PCI_ALDN_8814B BIT(17)\n#define BIT_SYS_ALDN_8814B BIT(16)\n\n#define BIT_SHIFT_EPVID1_8814B 8\n#define BIT_MASK_EPVID1_8814B 0xff\n#define BIT_EPVID1_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_EPVID1_8814B) << BIT_SHIFT_EPVID1_8814B)\n#define BITS_EPVID1_8814B (BIT_MASK_EPVID1_8814B << BIT_SHIFT_EPVID1_8814B)\n#define BIT_CLEAR_EPVID1_8814B(x) ((x) & (~BITS_EPVID1_8814B))\n#define BIT_GET_EPVID1_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_EPVID1_8814B) & BIT_MASK_EPVID1_8814B)\n#define BIT_SET_EPVID1_8814B(x, v)                                             \\\n\t(BIT_CLEAR_EPVID1_8814B(x) | BIT_EPVID1_8814B(v))\n\n#define BIT_SHIFT_EPVID0_8814B 0\n#define BIT_MASK_EPVID0_8814B 0xff\n#define BIT_EPVID0_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_EPVID0_8814B) << BIT_SHIFT_EPVID0_8814B)\n#define BITS_EPVID0_8814B (BIT_MASK_EPVID0_8814B << BIT_SHIFT_EPVID0_8814B)\n#define BIT_CLEAR_EPVID0_8814B(x) ((x) & (~BITS_EPVID0_8814B))\n#define BIT_GET_EPVID0_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_EPVID0_8814B) & BIT_MASK_EPVID0_8814B)\n#define BIT_SET_EPVID0_8814B(x, v)                                             \\\n\t(BIT_CLEAR_EPVID0_8814B(x) | BIT_EPVID0_8814B(v))\n\n/* 2 REG_SYS_CFG2_8814B */\n#define BIT_USB2_SEL_8814B BIT(31)\n#define BIT_U3PHY_RST_V1_8814B BIT(30)\n#define BIT_U3_TERM_DETECT_8814B BIT(29)\n\n#define BIT_SHIFT_HW_ID_8814B 0\n#define BIT_MASK_HW_ID_8814B 0xff\n#define BIT_HW_ID_8814B(x)                                                     \\\n\t(((x) & BIT_MASK_HW_ID_8814B) << BIT_SHIFT_HW_ID_8814B)\n#define BITS_HW_ID_8814B (BIT_MASK_HW_ID_8814B << BIT_SHIFT_HW_ID_8814B)\n#define BIT_CLEAR_HW_ID_8814B(x) ((x) & (~BITS_HW_ID_8814B))\n#define BIT_GET_HW_ID_8814B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HW_ID_8814B) & BIT_MASK_HW_ID_8814B)\n#define BIT_SET_HW_ID_8814B(x, v)                                              \\\n\t(BIT_CLEAR_HW_ID_8814B(x) | BIT_HW_ID_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_FEN_WLMAC_OFF_8814B BIT(31)\n#define BIT_PWC_MA33V_8814B BIT(15)\n#define BIT_PWC_MA12V_8814B BIT(14)\n#define BIT_PWC_MD12V_8814B BIT(13)\n#define BIT_PWC_PD12V_8814B BIT(12)\n#define BIT_PWC_UD12V_8814B BIT(11)\n#define BIT_ISO_BB2PP_8814B BIT(7)\n#define BIT_ISO_DENG2PP_8814B BIT(6)\n#define BIT_ISO_MA2MD_8814B BIT(1)\n#define BIT_ISO_MD2PP_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_ANAPARSW_MAC_0_8814B */\n#define BIT_OCP_L_0_8814B BIT(31)\n#define BIT_POWOCP_L_8814B BIT(30)\n\n#define BIT_SHIFT_CF_L_1_0_8814B 28\n#define BIT_MASK_CF_L_1_0_8814B 0x3\n#define BIT_CF_L_1_0_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_CF_L_1_0_8814B) << BIT_SHIFT_CF_L_1_0_8814B)\n#define BITS_CF_L_1_0_8814B                                                    \\\n\t(BIT_MASK_CF_L_1_0_8814B << BIT_SHIFT_CF_L_1_0_8814B)\n#define BIT_CLEAR_CF_L_1_0_8814B(x) ((x) & (~BITS_CF_L_1_0_8814B))\n#define BIT_GET_CF_L_1_0_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_CF_L_1_0_8814B) & BIT_MASK_CF_L_1_0_8814B)\n#define BIT_SET_CF_L_1_0_8814B(x, v)                                           \\\n\t(BIT_CLEAR_CF_L_1_0_8814B(x) | BIT_CF_L_1_0_8814B(v))\n\n#define BIT_SHIFT_CFC_L_1_0_8814B 26\n#define BIT_MASK_CFC_L_1_0_8814B 0x3\n#define BIT_CFC_L_1_0_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_CFC_L_1_0_8814B) << BIT_SHIFT_CFC_L_1_0_8814B)\n#define BITS_CFC_L_1_0_8814B                                                   \\\n\t(BIT_MASK_CFC_L_1_0_8814B << BIT_SHIFT_CFC_L_1_0_8814B)\n#define BIT_CLEAR_CFC_L_1_0_8814B(x) ((x) & (~BITS_CFC_L_1_0_8814B))\n#define BIT_GET_CFC_L_1_0_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_CFC_L_1_0_8814B) & BIT_MASK_CFC_L_1_0_8814B)\n#define BIT_SET_CFC_L_1_0_8814B(x, v)                                          \\\n\t(BIT_CLEAR_CFC_L_1_0_8814B(x) | BIT_CFC_L_1_0_8814B(v))\n\n#define BIT_SHIFT_R3_L_1_0_8814B 24\n#define BIT_MASK_R3_L_1_0_8814B 0x3\n#define BIT_R3_L_1_0_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_R3_L_1_0_8814B) << BIT_SHIFT_R3_L_1_0_8814B)\n#define BITS_R3_L_1_0_8814B                                                    \\\n\t(BIT_MASK_R3_L_1_0_8814B << BIT_SHIFT_R3_L_1_0_8814B)\n#define BIT_CLEAR_R3_L_1_0_8814B(x) ((x) & (~BITS_R3_L_1_0_8814B))\n#define BIT_GET_R3_L_1_0_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_R3_L_1_0_8814B) & BIT_MASK_R3_L_1_0_8814B)\n#define BIT_SET_R3_L_1_0_8814B(x, v)                                           \\\n\t(BIT_CLEAR_R3_L_1_0_8814B(x) | BIT_R3_L_1_0_8814B(v))\n\n#define BIT_SHIFT_R2_L_1_0_8814B 22\n#define BIT_MASK_R2_L_1_0_8814B 0x3\n#define BIT_R2_L_1_0_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_R2_L_1_0_8814B) << BIT_SHIFT_R2_L_1_0_8814B)\n#define BITS_R2_L_1_0_8814B                                                    \\\n\t(BIT_MASK_R2_L_1_0_8814B << BIT_SHIFT_R2_L_1_0_8814B)\n#define BIT_CLEAR_R2_L_1_0_8814B(x) ((x) & (~BITS_R2_L_1_0_8814B))\n#define BIT_GET_R2_L_1_0_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_R2_L_1_0_8814B) & BIT_MASK_R2_L_1_0_8814B)\n#define BIT_SET_R2_L_1_0_8814B(x, v)                                           \\\n\t(BIT_CLEAR_R2_L_1_0_8814B(x) | BIT_R2_L_1_0_8814B(v))\n\n#define BIT_SHIFT_R1_L_1_0_8814B 20\n#define BIT_MASK_R1_L_1_0_8814B 0x3\n#define BIT_R1_L_1_0_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_R1_L_1_0_8814B) << BIT_SHIFT_R1_L_1_0_8814B)\n#define BITS_R1_L_1_0_8814B                                                    \\\n\t(BIT_MASK_R1_L_1_0_8814B << BIT_SHIFT_R1_L_1_0_8814B)\n#define BIT_CLEAR_R1_L_1_0_8814B(x) ((x) & (~BITS_R1_L_1_0_8814B))\n#define BIT_GET_R1_L_1_0_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_R1_L_1_0_8814B) & BIT_MASK_R1_L_1_0_8814B)\n#define BIT_SET_R1_L_1_0_8814B(x, v)                                           \\\n\t(BIT_CLEAR_R1_L_1_0_8814B(x) | BIT_R1_L_1_0_8814B(v))\n\n#define BIT_SHIFT_C3_L_1_0_8814B 18\n#define BIT_MASK_C3_L_1_0_8814B 0x3\n#define BIT_C3_L_1_0_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_C3_L_1_0_8814B) << BIT_SHIFT_C3_L_1_0_8814B)\n#define BITS_C3_L_1_0_8814B                                                    \\\n\t(BIT_MASK_C3_L_1_0_8814B << BIT_SHIFT_C3_L_1_0_8814B)\n#define BIT_CLEAR_C3_L_1_0_8814B(x) ((x) & (~BITS_C3_L_1_0_8814B))\n#define BIT_GET_C3_L_1_0_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_C3_L_1_0_8814B) & BIT_MASK_C3_L_1_0_8814B)\n#define BIT_SET_C3_L_1_0_8814B(x, v)                                           \\\n\t(BIT_CLEAR_C3_L_1_0_8814B(x) | BIT_C3_L_1_0_8814B(v))\n\n#define BIT_SHIFT_C2_L_1_0_8814B 16\n#define BIT_MASK_C2_L_1_0_8814B 0x3\n#define BIT_C2_L_1_0_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_C2_L_1_0_8814B) << BIT_SHIFT_C2_L_1_0_8814B)\n#define BITS_C2_L_1_0_8814B                                                    \\\n\t(BIT_MASK_C2_L_1_0_8814B << BIT_SHIFT_C2_L_1_0_8814B)\n#define BIT_CLEAR_C2_L_1_0_8814B(x) ((x) & (~BITS_C2_L_1_0_8814B))\n#define BIT_GET_C2_L_1_0_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_C2_L_1_0_8814B) & BIT_MASK_C2_L_1_0_8814B)\n#define BIT_SET_C2_L_1_0_8814B(x, v)                                           \\\n\t(BIT_CLEAR_C2_L_1_0_8814B(x) | BIT_C2_L_1_0_8814B(v))\n\n#define BIT_SHIFT_C1_L_1_0_8814B 14\n#define BIT_MASK_C1_L_1_0_8814B 0x3\n#define BIT_C1_L_1_0_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_C1_L_1_0_8814B) << BIT_SHIFT_C1_L_1_0_8814B)\n#define BITS_C1_L_1_0_8814B                                                    \\\n\t(BIT_MASK_C1_L_1_0_8814B << BIT_SHIFT_C1_L_1_0_8814B)\n#define BIT_CLEAR_C1_L_1_0_8814B(x) ((x) & (~BITS_C1_L_1_0_8814B))\n#define BIT_GET_C1_L_1_0_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_C1_L_1_0_8814B) & BIT_MASK_C1_L_1_0_8814B)\n#define BIT_SET_C1_L_1_0_8814B(x, v)                                           \\\n\t(BIT_CLEAR_C1_L_1_0_8814B(x) | BIT_C1_L_1_0_8814B(v))\n\n#define BIT_REG_TYPE_L_V2_8814B BIT(13)\n#define BIT_REG_PWM_L_8814B BIT(12)\n\n#define BIT_SHIFT_V15ADJ_L_2_0_8814B 9\n#define BIT_MASK_V15ADJ_L_2_0_8814B 0x7\n#define BIT_V15ADJ_L_2_0_8814B(x)                                              \\\n\t(((x) & BIT_MASK_V15ADJ_L_2_0_8814B) << BIT_SHIFT_V15ADJ_L_2_0_8814B)\n#define BITS_V15ADJ_L_2_0_8814B                                                \\\n\t(BIT_MASK_V15ADJ_L_2_0_8814B << BIT_SHIFT_V15ADJ_L_2_0_8814B)\n#define BIT_CLEAR_V15ADJ_L_2_0_8814B(x) ((x) & (~BITS_V15ADJ_L_2_0_8814B))\n#define BIT_GET_V15ADJ_L_2_0_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_V15ADJ_L_2_0_8814B) & BIT_MASK_V15ADJ_L_2_0_8814B)\n#define BIT_SET_V15ADJ_L_2_0_8814B(x, v)                                       \\\n\t(BIT_CLEAR_V15ADJ_L_2_0_8814B(x) | BIT_V15ADJ_L_2_0_8814B(v))\n\n#define BIT_SHIFT_IN_L_2_0_8814B 6\n#define BIT_MASK_IN_L_2_0_8814B 0x7\n#define BIT_IN_L_2_0_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_IN_L_2_0_8814B) << BIT_SHIFT_IN_L_2_0_8814B)\n#define BITS_IN_L_2_0_8814B                                                    \\\n\t(BIT_MASK_IN_L_2_0_8814B << BIT_SHIFT_IN_L_2_0_8814B)\n#define BIT_CLEAR_IN_L_2_0_8814B(x) ((x) & (~BITS_IN_L_2_0_8814B))\n#define BIT_GET_IN_L_2_0_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_IN_L_2_0_8814B) & BIT_MASK_IN_L_2_0_8814B)\n#define BIT_SET_IN_L_2_0_8814B(x, v)                                           \\\n\t(BIT_CLEAR_IN_L_2_0_8814B(x) | BIT_IN_L_2_0_8814B(v))\n\n#define BIT_SHIFT_STD_L_1_0_8814B 4\n#define BIT_MASK_STD_L_1_0_8814B 0x3\n#define BIT_STD_L_1_0_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_STD_L_1_0_8814B) << BIT_SHIFT_STD_L_1_0_8814B)\n#define BITS_STD_L_1_0_8814B                                                   \\\n\t(BIT_MASK_STD_L_1_0_8814B << BIT_SHIFT_STD_L_1_0_8814B)\n#define BIT_CLEAR_STD_L_1_0_8814B(x) ((x) & (~BITS_STD_L_1_0_8814B))\n#define BIT_GET_STD_L_1_0_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_STD_L_1_0_8814B) & BIT_MASK_STD_L_1_0_8814B)\n#define BIT_SET_STD_L_1_0_8814B(x, v)                                          \\\n\t(BIT_CLEAR_STD_L_1_0_8814B(x) | BIT_STD_L_1_0_8814B(v))\n\n#define BIT_SHIFT_VOL_L_3_0_8814B 0\n#define BIT_MASK_VOL_L_3_0_8814B 0xf\n#define BIT_VOL_L_3_0_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_VOL_L_3_0_8814B) << BIT_SHIFT_VOL_L_3_0_8814B)\n#define BITS_VOL_L_3_0_8814B                                                   \\\n\t(BIT_MASK_VOL_L_3_0_8814B << BIT_SHIFT_VOL_L_3_0_8814B)\n#define BIT_CLEAR_VOL_L_3_0_8814B(x) ((x) & (~BITS_VOL_L_3_0_8814B))\n#define BIT_GET_VOL_L_3_0_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_VOL_L_3_0_8814B) & BIT_MASK_VOL_L_3_0_8814B)\n#define BIT_SET_VOL_L_3_0_8814B(x, v)                                          \\\n\t(BIT_CLEAR_VOL_L_3_0_8814B(x) | BIT_VOL_L_3_0_8814B(v))\n\n/* 2 REG_ANAPARSW_MAC_1_8814B */\n\n#define BIT_SHIFT_REG_FREQ_L_V1_8814B 20\n#define BIT_MASK_REG_FREQ_L_V1_8814B 0x7\n#define BIT_REG_FREQ_L_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_REG_FREQ_L_V1_8814B) << BIT_SHIFT_REG_FREQ_L_V1_8814B)\n#define BITS_REG_FREQ_L_V1_8814B                                               \\\n\t(BIT_MASK_REG_FREQ_L_V1_8814B << BIT_SHIFT_REG_FREQ_L_V1_8814B)\n#define BIT_CLEAR_REG_FREQ_L_V1_8814B(x) ((x) & (~BITS_REG_FREQ_L_V1_8814B))\n#define BIT_GET_REG_FREQ_L_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_REG_FREQ_L_V1_8814B) & BIT_MASK_REG_FREQ_L_V1_8814B)\n#define BIT_SET_REG_FREQ_L_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_REG_FREQ_L_V1_8814B(x) | BIT_REG_FREQ_L_V1_8814B(v))\n\n#define BIT_EN_DUTY_8814B BIT(19)\n\n#define BIT_SHIFT_REG_MOS_HALF_8814B 17\n#define BIT_MASK_REG_MOS_HALF_8814B 0x3\n#define BIT_REG_MOS_HALF_8814B(x)                                              \\\n\t(((x) & BIT_MASK_REG_MOS_HALF_8814B) << BIT_SHIFT_REG_MOS_HALF_8814B)\n#define BITS_REG_MOS_HALF_8814B                                                \\\n\t(BIT_MASK_REG_MOS_HALF_8814B << BIT_SHIFT_REG_MOS_HALF_8814B)\n#define BIT_CLEAR_REG_MOS_HALF_8814B(x) ((x) & (~BITS_REG_MOS_HALF_8814B))\n#define BIT_GET_REG_MOS_HALF_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_REG_MOS_HALF_8814B) & BIT_MASK_REG_MOS_HALF_8814B)\n#define BIT_SET_REG_MOS_HALF_8814B(x, v)                                       \\\n\t(BIT_CLEAR_REG_MOS_HALF_8814B(x) | BIT_REG_MOS_HALF_8814B(v))\n\n#define BIT_EN_SP_8814B BIT(16)\n#define BIT_REG_AUTO_L_V1_8814B BIT(15)\n#define BIT_REG_LDOF_L_V2_8814B BIT(14)\n#define BIT_REG_OCPS_L_V2_8814B BIT(13)\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_ARENB_L_V1_8814B BIT(11)\n\n#define BIT_SHIFT_TBOX_L1_1_0_8814B 9\n#define BIT_MASK_TBOX_L1_1_0_8814B 0x3\n#define BIT_TBOX_L1_1_0_8814B(x)                                               \\\n\t(((x) & BIT_MASK_TBOX_L1_1_0_8814B) << BIT_SHIFT_TBOX_L1_1_0_8814B)\n#define BITS_TBOX_L1_1_0_8814B                                                 \\\n\t(BIT_MASK_TBOX_L1_1_0_8814B << BIT_SHIFT_TBOX_L1_1_0_8814B)\n#define BIT_CLEAR_TBOX_L1_1_0_8814B(x) ((x) & (~BITS_TBOX_L1_1_0_8814B))\n#define BIT_GET_TBOX_L1_1_0_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_TBOX_L1_1_0_8814B) & BIT_MASK_TBOX_L1_1_0_8814B)\n#define BIT_SET_TBOX_L1_1_0_8814B(x, v)                                        \\\n\t(BIT_CLEAR_TBOX_L1_1_0_8814B(x) | BIT_TBOX_L1_1_0_8814B(v))\n\n#define BIT_SHIFT_REG_DELAY_L_1_0_8814B 7\n#define BIT_MASK_REG_DELAY_L_1_0_8814B 0x3\n#define BIT_REG_DELAY_L_1_0_8814B(x)                                           \\\n\t(((x) & BIT_MASK_REG_DELAY_L_1_0_8814B)                                \\\n\t << BIT_SHIFT_REG_DELAY_L_1_0_8814B)\n#define BITS_REG_DELAY_L_1_0_8814B                                             \\\n\t(BIT_MASK_REG_DELAY_L_1_0_8814B << BIT_SHIFT_REG_DELAY_L_1_0_8814B)\n#define BIT_CLEAR_REG_DELAY_L_1_0_8814B(x) ((x) & (~BITS_REG_DELAY_L_1_0_8814B))\n#define BIT_GET_REG_DELAY_L_1_0_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_REG_DELAY_L_1_0_8814B) &                            \\\n\t BIT_MASK_REG_DELAY_L_1_0_8814B)\n#define BIT_SET_REG_DELAY_L_1_0_8814B(x, v)                                    \\\n\t(BIT_CLEAR_REG_DELAY_L_1_0_8814B(x) | BIT_REG_DELAY_L_1_0_8814B(v))\n\n#define BIT_REG_CLAMP_D_L_8814B BIT(6)\n#define BIT_REG_BYPASS_L_V1_8814B BIT(5)\n#define BIT_REG_AUTOZCD_L_8814B BIT(4)\n#define BIT_POW_ZCD_L_V1_8814B BIT(3)\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_OCP_L_2_1_8814B 0\n#define BIT_MASK_OCP_L_2_1_8814B 0x3\n#define BIT_OCP_L_2_1_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_OCP_L_2_1_8814B) << BIT_SHIFT_OCP_L_2_1_8814B)\n#define BITS_OCP_L_2_1_8814B                                                   \\\n\t(BIT_MASK_OCP_L_2_1_8814B << BIT_SHIFT_OCP_L_2_1_8814B)\n#define BIT_CLEAR_OCP_L_2_1_8814B(x) ((x) & (~BITS_OCP_L_2_1_8814B))\n#define BIT_GET_OCP_L_2_1_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_OCP_L_2_1_8814B) & BIT_MASK_OCP_L_2_1_8814B)\n#define BIT_SET_OCP_L_2_1_8814B(x, v)                                          \\\n\t(BIT_CLEAR_OCP_L_2_1_8814B(x) | BIT_OCP_L_2_1_8814B(v))\n\n/* 2 REG_ANAPAR_MAC_0_8814B */\n\n#define BIT_SHIFT_LPF_C2_1_0_8814B 30\n#define BIT_MASK_LPF_C2_1_0_8814B 0x3\n#define BIT_LPF_C2_1_0_8814B(x)                                                \\\n\t(((x) & BIT_MASK_LPF_C2_1_0_8814B) << BIT_SHIFT_LPF_C2_1_0_8814B)\n#define BITS_LPF_C2_1_0_8814B                                                  \\\n\t(BIT_MASK_LPF_C2_1_0_8814B << BIT_SHIFT_LPF_C2_1_0_8814B)\n#define BIT_CLEAR_LPF_C2_1_0_8814B(x) ((x) & (~BITS_LPF_C2_1_0_8814B))\n#define BIT_GET_LPF_C2_1_0_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_LPF_C2_1_0_8814B) & BIT_MASK_LPF_C2_1_0_8814B)\n#define BIT_SET_LPF_C2_1_0_8814B(x, v)                                         \\\n\t(BIT_CLEAR_LPF_C2_1_0_8814B(x) | BIT_LPF_C2_1_0_8814B(v))\n\n#define BIT_SHIFT_LPF_C1_5_0_8814B 24\n#define BIT_MASK_LPF_C1_5_0_8814B 0x3f\n#define BIT_LPF_C1_5_0_8814B(x)                                                \\\n\t(((x) & BIT_MASK_LPF_C1_5_0_8814B) << BIT_SHIFT_LPF_C1_5_0_8814B)\n#define BITS_LPF_C1_5_0_8814B                                                  \\\n\t(BIT_MASK_LPF_C1_5_0_8814B << BIT_SHIFT_LPF_C1_5_0_8814B)\n#define BIT_CLEAR_LPF_C1_5_0_8814B(x) ((x) & (~BITS_LPF_C1_5_0_8814B))\n#define BIT_GET_LPF_C1_5_0_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_LPF_C1_5_0_8814B) & BIT_MASK_LPF_C1_5_0_8814B)\n#define BIT_SET_LPF_C1_5_0_8814B(x, v)                                         \\\n\t(BIT_CLEAR_LPF_C1_5_0_8814B(x) | BIT_LPF_C1_5_0_8814B(v))\n\n#define BIT_LPF_TIEL_8814B BIT(23)\n#define BIT_LPF_TIEH_8814B BIT(22)\n\n#define BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B 20\n#define BIT_MASK_LOCKDET_VREF_L_1_0_8814B 0x3\n#define BIT_LOCKDET_VREF_L_1_0_8814B(x)                                        \\\n\t(((x) & BIT_MASK_LOCKDET_VREF_L_1_0_8814B)                             \\\n\t << BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B)\n#define BITS_LOCKDET_VREF_L_1_0_8814B                                          \\\n\t(BIT_MASK_LOCKDET_VREF_L_1_0_8814B                                     \\\n\t << BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B)\n#define BIT_CLEAR_LOCKDET_VREF_L_1_0_8814B(x)                                  \\\n\t((x) & (~BITS_LOCKDET_VREF_L_1_0_8814B))\n#define BIT_GET_LOCKDET_VREF_L_1_0_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B) &                         \\\n\t BIT_MASK_LOCKDET_VREF_L_1_0_8814B)\n#define BIT_SET_LOCKDET_VREF_L_1_0_8814B(x, v)                                 \\\n\t(BIT_CLEAR_LOCKDET_VREF_L_1_0_8814B(x) |                               \\\n\t BIT_LOCKDET_VREF_L_1_0_8814B(v))\n\n#define BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B 18\n#define BIT_MASK_LOCKDET_VREF_H_1_0_8814B 0x3\n#define BIT_LOCKDET_VREF_H_1_0_8814B(x)                                        \\\n\t(((x) & BIT_MASK_LOCKDET_VREF_H_1_0_8814B)                             \\\n\t << BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B)\n#define BITS_LOCKDET_VREF_H_1_0_8814B                                          \\\n\t(BIT_MASK_LOCKDET_VREF_H_1_0_8814B                                     \\\n\t << BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B)\n#define BIT_CLEAR_LOCKDET_VREF_H_1_0_8814B(x)                                  \\\n\t((x) & (~BITS_LOCKDET_VREF_H_1_0_8814B))\n#define BIT_GET_LOCKDET_VREF_H_1_0_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B) &                         \\\n\t BIT_MASK_LOCKDET_VREF_H_1_0_8814B)\n#define BIT_SET_LOCKDET_VREF_H_1_0_8814B(x, v)                                 \\\n\t(BIT_CLEAR_LOCKDET_VREF_H_1_0_8814B(x) |                               \\\n\t BIT_LOCKDET_VREF_H_1_0_8814B(v))\n\n#define BIT_SHIFT_LDO_SEL_1_0_8814B 16\n#define BIT_MASK_LDO_SEL_1_0_8814B 0x3\n#define BIT_LDO_SEL_1_0_8814B(x)                                               \\\n\t(((x) & BIT_MASK_LDO_SEL_1_0_8814B) << BIT_SHIFT_LDO_SEL_1_0_8814B)\n#define BITS_LDO_SEL_1_0_8814B                                                 \\\n\t(BIT_MASK_LDO_SEL_1_0_8814B << BIT_SHIFT_LDO_SEL_1_0_8814B)\n#define BIT_CLEAR_LDO_SEL_1_0_8814B(x) ((x) & (~BITS_LDO_SEL_1_0_8814B))\n#define BIT_GET_LDO_SEL_1_0_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_LDO_SEL_1_0_8814B) & BIT_MASK_LDO_SEL_1_0_8814B)\n#define BIT_SET_LDO_SEL_1_0_8814B(x, v)                                        \\\n\t(BIT_CLEAR_LDO_SEL_1_0_8814B(x) | BIT_LDO_SEL_1_0_8814B(v))\n\n#define BIT_SHIFT_IOFFSET_5_0_8814B 10\n#define BIT_MASK_IOFFSET_5_0_8814B 0x3f\n#define BIT_IOFFSET_5_0_8814B(x)                                               \\\n\t(((x) & BIT_MASK_IOFFSET_5_0_8814B) << BIT_SHIFT_IOFFSET_5_0_8814B)\n#define BITS_IOFFSET_5_0_8814B                                                 \\\n\t(BIT_MASK_IOFFSET_5_0_8814B << BIT_SHIFT_IOFFSET_5_0_8814B)\n#define BIT_CLEAR_IOFFSET_5_0_8814B(x) ((x) & (~BITS_IOFFSET_5_0_8814B))\n#define BIT_GET_IOFFSET_5_0_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_IOFFSET_5_0_8814B) & BIT_MASK_IOFFSET_5_0_8814B)\n#define BIT_SET_IOFFSET_5_0_8814B(x, v)                                        \\\n\t(BIT_CLEAR_IOFFSET_5_0_8814B(x) | BIT_IOFFSET_5_0_8814B(v))\n\n#define BIT_CP_ICPX2_8814B BIT(9)\n\n#define BIT_SHIFT_CP_ICP_SEL_4_0_8814B 4\n#define BIT_MASK_CP_ICP_SEL_4_0_8814B 0x1f\n#define BIT_CP_ICP_SEL_4_0_8814B(x)                                            \\\n\t(((x) & BIT_MASK_CP_ICP_SEL_4_0_8814B)                                 \\\n\t << BIT_SHIFT_CP_ICP_SEL_4_0_8814B)\n#define BITS_CP_ICP_SEL_4_0_8814B                                              \\\n\t(BIT_MASK_CP_ICP_SEL_4_0_8814B << BIT_SHIFT_CP_ICP_SEL_4_0_8814B)\n#define BIT_CLEAR_CP_ICP_SEL_4_0_8814B(x) ((x) & (~BITS_CP_ICP_SEL_4_0_8814B))\n#define BIT_GET_CP_ICP_SEL_4_0_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_CP_ICP_SEL_4_0_8814B) &                             \\\n\t BIT_MASK_CP_ICP_SEL_4_0_8814B)\n#define BIT_SET_CP_ICP_SEL_4_0_8814B(x, v)                                     \\\n\t(BIT_CLEAR_CP_ICP_SEL_4_0_8814B(x) | BIT_CP_ICP_SEL_4_0_8814B(v))\n\n#define BIT_SHIFT_IB_PI_1_0_8814B 2\n#define BIT_MASK_IB_PI_1_0_8814B 0x3\n#define BIT_IB_PI_1_0_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_IB_PI_1_0_8814B) << BIT_SHIFT_IB_PI_1_0_8814B)\n#define BITS_IB_PI_1_0_8814B                                                   \\\n\t(BIT_MASK_IB_PI_1_0_8814B << BIT_SHIFT_IB_PI_1_0_8814B)\n#define BIT_CLEAR_IB_PI_1_0_8814B(x) ((x) & (~BITS_IB_PI_1_0_8814B))\n#define BIT_GET_IB_PI_1_0_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_IB_PI_1_0_8814B) & BIT_MASK_IB_PI_1_0_8814B)\n#define BIT_SET_IB_PI_1_0_8814B(x, v)                                          \\\n\t(BIT_CLEAR_IB_PI_1_0_8814B(x) | BIT_IB_PI_1_0_8814B(v))\n\n#define BIT_SHIFT_LDO_VSEL_8814B 0\n#define BIT_MASK_LDO_VSEL_8814B 0x3\n#define BIT_LDO_VSEL_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_LDO_VSEL_8814B) << BIT_SHIFT_LDO_VSEL_8814B)\n#define BITS_LDO_VSEL_8814B                                                    \\\n\t(BIT_MASK_LDO_VSEL_8814B << BIT_SHIFT_LDO_VSEL_8814B)\n#define BIT_CLEAR_LDO_VSEL_8814B(x) ((x) & (~BITS_LDO_VSEL_8814B))\n#define BIT_GET_LDO_VSEL_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_LDO_VSEL_8814B) & BIT_MASK_LDO_VSEL_8814B)\n#define BIT_SET_LDO_VSEL_8814B(x, v)                                           \\\n\t(BIT_CLEAR_LDO_VSEL_8814B(x) | BIT_LDO_VSEL_8814B(v))\n\n/* 2 REG_ANAPAR_MAC_1_8814B */\n\n#define BIT_SHIFT_CKX_USB_IB_SEL_8814B 29\n#define BIT_MASK_CKX_USB_IB_SEL_8814B 0x7\n#define BIT_CKX_USB_IB_SEL_8814B(x)                                            \\\n\t(((x) & BIT_MASK_CKX_USB_IB_SEL_8814B)                                 \\\n\t << BIT_SHIFT_CKX_USB_IB_SEL_8814B)\n#define BITS_CKX_USB_IB_SEL_8814B                                              \\\n\t(BIT_MASK_CKX_USB_IB_SEL_8814B << BIT_SHIFT_CKX_USB_IB_SEL_8814B)\n#define BIT_CLEAR_CKX_USB_IB_SEL_8814B(x) ((x) & (~BITS_CKX_USB_IB_SEL_8814B))\n#define BIT_GET_CKX_USB_IB_SEL_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_CKX_USB_IB_SEL_8814B) &                             \\\n\t BIT_MASK_CKX_USB_IB_SEL_8814B)\n#define BIT_SET_CKX_USB_IB_SEL_8814B(x, v)                                     \\\n\t(BIT_CLEAR_CKX_USB_IB_SEL_8814B(x) | BIT_CKX_USB_IB_SEL_8814B(v))\n\n#define BIT_PFD_DN_GATED_8814B BIT(28)\n#define BIT_PFD_UP_GATED_8814B BIT(27)\n#define BIT_PFD_RESET_GATED_8814B BIT(26)\n\n#define BIT_SHIFT_PFD_OUT_DRV_1_0_8814B 24\n#define BIT_MASK_PFD_OUT_DRV_1_0_8814B 0x3\n#define BIT_PFD_OUT_DRV_1_0_8814B(x)                                           \\\n\t(((x) & BIT_MASK_PFD_OUT_DRV_1_0_8814B)                                \\\n\t << BIT_SHIFT_PFD_OUT_DRV_1_0_8814B)\n#define BITS_PFD_OUT_DRV_1_0_8814B                                             \\\n\t(BIT_MASK_PFD_OUT_DRV_1_0_8814B << BIT_SHIFT_PFD_OUT_DRV_1_0_8814B)\n#define BIT_CLEAR_PFD_OUT_DRV_1_0_8814B(x) ((x) & (~BITS_PFD_OUT_DRV_1_0_8814B))\n#define BIT_GET_PFD_OUT_DRV_1_0_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_PFD_OUT_DRV_1_0_8814B) &                            \\\n\t BIT_MASK_PFD_OUT_DRV_1_0_8814B)\n#define BIT_SET_PFD_OUT_DRV_1_0_8814B(x, v)                                    \\\n\t(BIT_CLEAR_PFD_OUT_DRV_1_0_8814B(x) | BIT_PFD_OUT_DRV_1_0_8814B(v))\n\n#define BIT_SHIFT_LPF_TIEMID_2_0_8814B 20\n#define BIT_MASK_LPF_TIEMID_2_0_8814B 0x7\n#define BIT_LPF_TIEMID_2_0_8814B(x)                                            \\\n\t(((x) & BIT_MASK_LPF_TIEMID_2_0_8814B)                                 \\\n\t << BIT_SHIFT_LPF_TIEMID_2_0_8814B)\n#define BITS_LPF_TIEMID_2_0_8814B                                              \\\n\t(BIT_MASK_LPF_TIEMID_2_0_8814B << BIT_SHIFT_LPF_TIEMID_2_0_8814B)\n#define BIT_CLEAR_LPF_TIEMID_2_0_8814B(x) ((x) & (~BITS_LPF_TIEMID_2_0_8814B))\n#define BIT_GET_LPF_TIEMID_2_0_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_LPF_TIEMID_2_0_8814B) &                             \\\n\t BIT_MASK_LPF_TIEMID_2_0_8814B)\n#define BIT_SET_LPF_TIEMID_2_0_8814B(x, v)                                     \\\n\t(BIT_CLEAR_LPF_TIEMID_2_0_8814B(x) | BIT_LPF_TIEMID_2_0_8814B(v))\n\n#define BIT_SHIFT_LPF_R3_4_0_8814B 15\n#define BIT_MASK_LPF_R3_4_0_8814B 0x1f\n#define BIT_LPF_R3_4_0_8814B(x)                                                \\\n\t(((x) & BIT_MASK_LPF_R3_4_0_8814B) << BIT_SHIFT_LPF_R3_4_0_8814B)\n#define BITS_LPF_R3_4_0_8814B                                                  \\\n\t(BIT_MASK_LPF_R3_4_0_8814B << BIT_SHIFT_LPF_R3_4_0_8814B)\n#define BIT_CLEAR_LPF_R3_4_0_8814B(x) ((x) & (~BITS_LPF_R3_4_0_8814B))\n#define BIT_GET_LPF_R3_4_0_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_LPF_R3_4_0_8814B) & BIT_MASK_LPF_R3_4_0_8814B)\n#define BIT_SET_LPF_R3_4_0_8814B(x, v)                                         \\\n\t(BIT_CLEAR_LPF_R3_4_0_8814B(x) | BIT_LPF_R3_4_0_8814B(v))\n\n#define BIT_SHIFT_LPF_R2_4_0_8814B 10\n#define BIT_MASK_LPF_R2_4_0_8814B 0x1f\n#define BIT_LPF_R2_4_0_8814B(x)                                                \\\n\t(((x) & BIT_MASK_LPF_R2_4_0_8814B) << BIT_SHIFT_LPF_R2_4_0_8814B)\n#define BITS_LPF_R2_4_0_8814B                                                  \\\n\t(BIT_MASK_LPF_R2_4_0_8814B << BIT_SHIFT_LPF_R2_4_0_8814B)\n#define BIT_CLEAR_LPF_R2_4_0_8814B(x) ((x) & (~BITS_LPF_R2_4_0_8814B))\n#define BIT_GET_LPF_R2_4_0_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_LPF_R2_4_0_8814B) & BIT_MASK_LPF_R2_4_0_8814B)\n#define BIT_SET_LPF_R2_4_0_8814B(x, v)                                         \\\n\t(BIT_CLEAR_LPF_R2_4_0_8814B(x) | BIT_LPF_R2_4_0_8814B(v))\n\n#define BIT_SHIFT_LPF_C3_5_0_8814B 4\n#define BIT_MASK_LPF_C3_5_0_8814B 0x3f\n#define BIT_LPF_C3_5_0_8814B(x)                                                \\\n\t(((x) & BIT_MASK_LPF_C3_5_0_8814B) << BIT_SHIFT_LPF_C3_5_0_8814B)\n#define BITS_LPF_C3_5_0_8814B                                                  \\\n\t(BIT_MASK_LPF_C3_5_0_8814B << BIT_SHIFT_LPF_C3_5_0_8814B)\n#define BIT_CLEAR_LPF_C3_5_0_8814B(x) ((x) & (~BITS_LPF_C3_5_0_8814B))\n#define BIT_GET_LPF_C3_5_0_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_LPF_C3_5_0_8814B) & BIT_MASK_LPF_C3_5_0_8814B)\n#define BIT_SET_LPF_C3_5_0_8814B(x, v)                                         \\\n\t(BIT_CLEAR_LPF_C3_5_0_8814B(x) | BIT_LPF_C3_5_0_8814B(v))\n\n#define BIT_SHIFT_LPF_C2_5_2_8814B 0\n#define BIT_MASK_LPF_C2_5_2_8814B 0xf\n#define BIT_LPF_C2_5_2_8814B(x)                                                \\\n\t(((x) & BIT_MASK_LPF_C2_5_2_8814B) << BIT_SHIFT_LPF_C2_5_2_8814B)\n#define BITS_LPF_C2_5_2_8814B                                                  \\\n\t(BIT_MASK_LPF_C2_5_2_8814B << BIT_SHIFT_LPF_C2_5_2_8814B)\n#define BIT_CLEAR_LPF_C2_5_2_8814B(x) ((x) & (~BITS_LPF_C2_5_2_8814B))\n#define BIT_GET_LPF_C2_5_2_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_LPF_C2_5_2_8814B) & BIT_MASK_LPF_C2_5_2_8814B)\n#define BIT_SET_LPF_C2_5_2_8814B(x, v)                                         \\\n\t(BIT_CLEAR_LPF_C2_5_2_8814B(x) | BIT_LPF_C2_5_2_8814B(v))\n\n/* 2 REG_ANAPAR_MAC_2_8814B */\n#define BIT_CK_PHASE_SEL_8814B BIT(31)\n#define BIT_CK960M_EN_8814B BIT(30)\n#define BIT_CK640M_EN_8814B BIT(29)\n#define BIT_CK240M_EN_8814B BIT(28)\n\n#define BIT_SHIFT_CK_MON_SEL_2_0_8814B 25\n#define BIT_MASK_CK_MON_SEL_2_0_8814B 0x7\n#define BIT_CK_MON_SEL_2_0_8814B(x)                                            \\\n\t(((x) & BIT_MASK_CK_MON_SEL_2_0_8814B)                                 \\\n\t << BIT_SHIFT_CK_MON_SEL_2_0_8814B)\n#define BITS_CK_MON_SEL_2_0_8814B                                              \\\n\t(BIT_MASK_CK_MON_SEL_2_0_8814B << BIT_SHIFT_CK_MON_SEL_2_0_8814B)\n#define BIT_CLEAR_CK_MON_SEL_2_0_8814B(x) ((x) & (~BITS_CK_MON_SEL_2_0_8814B))\n#define BIT_GET_CK_MON_SEL_2_0_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_CK_MON_SEL_2_0_8814B) &                             \\\n\t BIT_MASK_CK_MON_SEL_2_0_8814B)\n#define BIT_SET_CK_MON_SEL_2_0_8814B(x, v)                                     \\\n\t(BIT_CLEAR_CK_MON_SEL_2_0_8814B(x) | BIT_CK_MON_SEL_2_0_8814B(v))\n\n#define BIT_CK_MON_EN_V1_8814B BIT(24)\n#define BIT_XTAL_SOURCE_SEL_8814B BIT(23)\n#define BIT_XTAL_FREQ_SEL_8814B BIT(22)\n#define BIT_XTAL_EDGE_SEL_8814B BIT(21)\n#define BIT_XTAL_BUF_SEL_8814B BIT(20)\n\n#define BIT_SHIFT_VCO_CV_7_0_8814B 4\n#define BIT_MASK_VCO_CV_7_0_8814B 0xff\n#define BIT_VCO_CV_7_0_8814B(x)                                                \\\n\t(((x) & BIT_MASK_VCO_CV_7_0_8814B) << BIT_SHIFT_VCO_CV_7_0_8814B)\n#define BITS_VCO_CV_7_0_8814B                                                  \\\n\t(BIT_MASK_VCO_CV_7_0_8814B << BIT_SHIFT_VCO_CV_7_0_8814B)\n#define BIT_CLEAR_VCO_CV_7_0_8814B(x) ((x) & (~BITS_VCO_CV_7_0_8814B))\n#define BIT_GET_VCO_CV_7_0_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_VCO_CV_7_0_8814B) & BIT_MASK_VCO_CV_7_0_8814B)\n#define BIT_SET_VCO_CV_7_0_8814B(x, v)                                         \\\n\t(BIT_CLEAR_VCO_CV_7_0_8814B(x) | BIT_VCO_CV_7_0_8814B(v))\n\n#define BIT_VCO_KVCO_8814B BIT(3)\n#define BIT_SDM_EDGE_SEL_8814B BIT(2)\n#define BIT_SDM_CK_SEL_8814B BIT(1)\n#define BIT_SDM_CK_GATED_8814B BIT(0)\n\n/* 2 REG_ANAPAR_MAC_3_8814B */\n\n#define BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B 28\n#define BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B 0x7\n#define BIT_LCK_WAIT_CYCLE_2_0_8814B(x)                                        \\\n\t(((x) & BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B)                             \\\n\t << BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B)\n#define BITS_LCK_WAIT_CYCLE_2_0_8814B                                          \\\n\t(BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B                                     \\\n\t << BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B)\n#define BIT_CLEAR_LCK_WAIT_CYCLE_2_0_8814B(x)                                  \\\n\t((x) & (~BITS_LCK_WAIT_CYCLE_2_0_8814B))\n#define BIT_GET_LCK_WAIT_CYCLE_2_0_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B) &                         \\\n\t BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B)\n#define BIT_SET_LCK_WAIT_CYCLE_2_0_8814B(x, v)                                 \\\n\t(BIT_CLEAR_LCK_WAIT_CYCLE_2_0_8814B(x) |                               \\\n\t BIT_LCK_WAIT_CYCLE_2_0_8814B(v))\n\n#define BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B 26\n#define BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B 0x3\n#define BIT_LCK_VCO_DIVISOR_1_0_8814B(x)                                       \\\n\t(((x) & BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B)                            \\\n\t << BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B)\n#define BITS_LCK_VCO_DIVISOR_1_0_8814B                                         \\\n\t(BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B                                    \\\n\t << BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B)\n#define BIT_CLEAR_LCK_VCO_DIVISOR_1_0_8814B(x)                                 \\\n\t((x) & (~BITS_LCK_VCO_DIVISOR_1_0_8814B))\n#define BIT_GET_LCK_VCO_DIVISOR_1_0_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B) &                        \\\n\t BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B)\n#define BIT_SET_LCK_VCO_DIVISOR_1_0_8814B(x, v)                                \\\n\t(BIT_CLEAR_LCK_VCO_DIVISOR_1_0_8814B(x) |                              \\\n\t BIT_LCK_VCO_DIVISOR_1_0_8814B(v))\n\n#define BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B 24\n#define BIT_MASK_LCK_SEARCH_MODE_1_0_8814B 0x3\n#define BIT_LCK_SEARCH_MODE_1_0_8814B(x)                                       \\\n\t(((x) & BIT_MASK_LCK_SEARCH_MODE_1_0_8814B)                            \\\n\t << BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B)\n#define BITS_LCK_SEARCH_MODE_1_0_8814B                                         \\\n\t(BIT_MASK_LCK_SEARCH_MODE_1_0_8814B                                    \\\n\t << BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B)\n#define BIT_CLEAR_LCK_SEARCH_MODE_1_0_8814B(x)                                 \\\n\t((x) & (~BITS_LCK_SEARCH_MODE_1_0_8814B))\n#define BIT_GET_LCK_SEARCH_MODE_1_0_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B) &                        \\\n\t BIT_MASK_LCK_SEARCH_MODE_1_0_8814B)\n#define BIT_SET_LCK_SEARCH_MODE_1_0_8814B(x, v)                                \\\n\t(BIT_CLEAR_LCK_SEARCH_MODE_1_0_8814B(x) |                              \\\n\t BIT_LCK_SEARCH_MODE_1_0_8814B(v))\n\n#define BIT_SHIFT_LS_CV_OFFSET_3_0_8814B 12\n#define BIT_MASK_LS_CV_OFFSET_3_0_8814B 0xf\n#define BIT_LS_CV_OFFSET_3_0_8814B(x)                                          \\\n\t(((x) & BIT_MASK_LS_CV_OFFSET_3_0_8814B)                               \\\n\t << BIT_SHIFT_LS_CV_OFFSET_3_0_8814B)\n#define BITS_LS_CV_OFFSET_3_0_8814B                                            \\\n\t(BIT_MASK_LS_CV_OFFSET_3_0_8814B << BIT_SHIFT_LS_CV_OFFSET_3_0_8814B)\n#define BIT_CLEAR_LS_CV_OFFSET_3_0_8814B(x)                                    \\\n\t((x) & (~BITS_LS_CV_OFFSET_3_0_8814B))\n#define BIT_GET_LS_CV_OFFSET_3_0_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_LS_CV_OFFSET_3_0_8814B) &                           \\\n\t BIT_MASK_LS_CV_OFFSET_3_0_8814B)\n#define BIT_SET_LS_CV_OFFSET_3_0_8814B(x, v)                                   \\\n\t(BIT_CLEAR_LS_CV_OFFSET_3_0_8814B(x) | BIT_LS_CV_OFFSET_3_0_8814B(v))\n\n#define BIT_LS_EN_LC_CK40M_8814B BIT(11)\n#define BIT_LS__CV_MANUAL_8814B BIT(10)\n#define BIT_LS_PYPASS_PI_8814B BIT(9)\n#define BIT_MBIASE_8814B BIT(4)\n\n/* 2 REG_ANAPAR_MAC_4_8814B */\n#define BIT_LS_TIE_MID_MODE_8814B BIT(28)\n\n#define BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B 26\n#define BIT_MASK_LS_SYNC_CYCLE_1_0_8814B 0x3\n#define BIT_LS_SYNC_CYCLE_1_0_8814B(x)                                         \\\n\t(((x) & BIT_MASK_LS_SYNC_CYCLE_1_0_8814B)                              \\\n\t << BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B)\n#define BITS_LS_SYNC_CYCLE_1_0_8814B                                           \\\n\t(BIT_MASK_LS_SYNC_CYCLE_1_0_8814B << BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B)\n#define BIT_CLEAR_LS_SYNC_CYCLE_1_0_8814B(x)                                   \\\n\t((x) & (~BITS_LS_SYNC_CYCLE_1_0_8814B))\n#define BIT_GET_LS_SYNC_CYCLE_1_0_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B) &                          \\\n\t BIT_MASK_LS_SYNC_CYCLE_1_0_8814B)\n#define BIT_SET_LS_SYNC_CYCLE_1_0_8814B(x, v)                                  \\\n\t(BIT_CLEAR_LS_SYNC_CYCLE_1_0_8814B(x) | BIT_LS_SYNC_CYCLE_1_0_8814B(v))\n\n#define BIT_LS_SDM_ORDER_8814B BIT(25)\n#define BIT_LS_RST_LC_CAL_8814B BIT(14)\n#define BIT_LS_RSTB_8814B BIT(13)\n#define BIT_LS_POW_LC_CAL_PREP_8814B BIT(11)\n\n#define BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B 0\n#define BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B 0x3\n#define BIT_LCK_XTAL_DIVISOR_1_0_8814B(x)                                      \\\n\t(((x) & BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B)                           \\\n\t << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B)\n#define BITS_LCK_XTAL_DIVISOR_1_0_8814B                                        \\\n\t(BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B                                   \\\n\t << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B)\n#define BIT_CLEAR_LCK_XTAL_DIVISOR_1_0_8814B(x)                                \\\n\t((x) & (~BITS_LCK_XTAL_DIVISOR_1_0_8814B))\n#define BIT_GET_LCK_XTAL_DIVISOR_1_0_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B) &                       \\\n\t BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B)\n#define BIT_SET_LCK_XTAL_DIVISOR_1_0_8814B(x, v)                               \\\n\t(BIT_CLEAR_LCK_XTAL_DIVISOR_1_0_8814B(x) |                             \\\n\t BIT_LCK_XTAL_DIVISOR_1_0_8814B(v))\n\n/* 2 REG_ANAPAR_MAC_5_8814B */\n\n#define BIT_SHIFT_LS_XTAL_SEL_3_0_8814B 0\n#define BIT_MASK_LS_XTAL_SEL_3_0_8814B 0xf\n#define BIT_LS_XTAL_SEL_3_0_8814B(x)                                           \\\n\t(((x) & BIT_MASK_LS_XTAL_SEL_3_0_8814B)                                \\\n\t << BIT_SHIFT_LS_XTAL_SEL_3_0_8814B)\n#define BITS_LS_XTAL_SEL_3_0_8814B                                             \\\n\t(BIT_MASK_LS_XTAL_SEL_3_0_8814B << BIT_SHIFT_LS_XTAL_SEL_3_0_8814B)\n#define BIT_CLEAR_LS_XTAL_SEL_3_0_8814B(x) ((x) & (~BITS_LS_XTAL_SEL_3_0_8814B))\n#define BIT_GET_LS_XTAL_SEL_3_0_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_LS_XTAL_SEL_3_0_8814B) &                            \\\n\t BIT_MASK_LS_XTAL_SEL_3_0_8814B)\n#define BIT_SET_LS_XTAL_SEL_3_0_8814B(x, v)                                    \\\n\t(BIT_CLEAR_LS_XTAL_SEL_3_0_8814B(x) | BIT_LS_XTAL_SEL_3_0_8814B(v))\n\n/* 2 REG_ANAPAR_MAC_6_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_ANAPAR_MAC_7_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_ANAPAR_MAC_8_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_ANAPAR_XTAL_0_8814B */\n#define BIT_XTAL_DRV_RF1_0_8814B BIT(31)\n#define BIT_XTAL_GATED_RF1N_8814B BIT(30)\n#define BIT_XTAL_GATED_RF1P_8814B BIT(29)\n#define BIT_XTAL_GM_SEP_V2_8814B BIT(28)\n\n#define BIT_SHIFT_XTAL_LDO_1_0_8814B 26\n#define BIT_MASK_XTAL_LDO_1_0_8814B 0x3\n#define BIT_XTAL_LDO_1_0_8814B(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_LDO_1_0_8814B) << BIT_SHIFT_XTAL_LDO_1_0_8814B)\n#define BITS_XTAL_LDO_1_0_8814B                                                \\\n\t(BIT_MASK_XTAL_LDO_1_0_8814B << BIT_SHIFT_XTAL_LDO_1_0_8814B)\n#define BIT_CLEAR_XTAL_LDO_1_0_8814B(x) ((x) & (~BITS_XTAL_LDO_1_0_8814B))\n#define BIT_GET_XTAL_LDO_1_0_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_LDO_1_0_8814B) & BIT_MASK_XTAL_LDO_1_0_8814B)\n#define BIT_SET_XTAL_LDO_1_0_8814B(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_LDO_1_0_8814B(x) | BIT_XTAL_LDO_1_0_8814B(v))\n\n#define BIT_XQSEL_V1_8814B BIT(25)\n#define BIT_GATED_XTAL_OK0_8814B BIT(24)\n\n#define BIT_SHIFT_XTAL_SC_XO_6_0_8814B 17\n#define BIT_MASK_XTAL_SC_XO_6_0_8814B 0x7f\n#define BIT_XTAL_SC_XO_6_0_8814B(x)                                            \\\n\t(((x) & BIT_MASK_XTAL_SC_XO_6_0_8814B)                                 \\\n\t << BIT_SHIFT_XTAL_SC_XO_6_0_8814B)\n#define BITS_XTAL_SC_XO_6_0_8814B                                              \\\n\t(BIT_MASK_XTAL_SC_XO_6_0_8814B << BIT_SHIFT_XTAL_SC_XO_6_0_8814B)\n#define BIT_CLEAR_XTAL_SC_XO_6_0_8814B(x) ((x) & (~BITS_XTAL_SC_XO_6_0_8814B))\n#define BIT_GET_XTAL_SC_XO_6_0_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_XTAL_SC_XO_6_0_8814B) &                             \\\n\t BIT_MASK_XTAL_SC_XO_6_0_8814B)\n#define BIT_SET_XTAL_SC_XO_6_0_8814B(x, v)                                     \\\n\t(BIT_CLEAR_XTAL_SC_XO_6_0_8814B(x) | BIT_XTAL_SC_XO_6_0_8814B(v))\n\n#define BIT_SHIFT_XTAL_SC_XI_6_0_8814B 10\n#define BIT_MASK_XTAL_SC_XI_6_0_8814B 0x7f\n#define BIT_XTAL_SC_XI_6_0_8814B(x)                                            \\\n\t(((x) & BIT_MASK_XTAL_SC_XI_6_0_8814B)                                 \\\n\t << BIT_SHIFT_XTAL_SC_XI_6_0_8814B)\n#define BITS_XTAL_SC_XI_6_0_8814B                                              \\\n\t(BIT_MASK_XTAL_SC_XI_6_0_8814B << BIT_SHIFT_XTAL_SC_XI_6_0_8814B)\n#define BIT_CLEAR_XTAL_SC_XI_6_0_8814B(x) ((x) & (~BITS_XTAL_SC_XI_6_0_8814B))\n#define BIT_GET_XTAL_SC_XI_6_0_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_XTAL_SC_XI_6_0_8814B) &                             \\\n\t BIT_MASK_XTAL_SC_XI_6_0_8814B)\n#define BIT_SET_XTAL_SC_XI_6_0_8814B(x, v)                                     \\\n\t(BIT_CLEAR_XTAL_SC_XI_6_0_8814B(x) | BIT_XTAL_SC_XI_6_0_8814B(v))\n\n#define BIT_SHIFT_XTAL_GMN_4_0_8814B 5\n#define BIT_MASK_XTAL_GMN_4_0_8814B 0x1f\n#define BIT_XTAL_GMN_4_0_8814B(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_GMN_4_0_8814B) << BIT_SHIFT_XTAL_GMN_4_0_8814B)\n#define BITS_XTAL_GMN_4_0_8814B                                                \\\n\t(BIT_MASK_XTAL_GMN_4_0_8814B << BIT_SHIFT_XTAL_GMN_4_0_8814B)\n#define BIT_CLEAR_XTAL_GMN_4_0_8814B(x) ((x) & (~BITS_XTAL_GMN_4_0_8814B))\n#define BIT_GET_XTAL_GMN_4_0_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_GMN_4_0_8814B) & BIT_MASK_XTAL_GMN_4_0_8814B)\n#define BIT_SET_XTAL_GMN_4_0_8814B(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_GMN_4_0_8814B(x) | BIT_XTAL_GMN_4_0_8814B(v))\n\n#define BIT_SHIFT_XTAL_GMP_4_0_8814B 0\n#define BIT_MASK_XTAL_GMP_4_0_8814B 0x1f\n#define BIT_XTAL_GMP_4_0_8814B(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_GMP_4_0_8814B) << BIT_SHIFT_XTAL_GMP_4_0_8814B)\n#define BITS_XTAL_GMP_4_0_8814B                                                \\\n\t(BIT_MASK_XTAL_GMP_4_0_8814B << BIT_SHIFT_XTAL_GMP_4_0_8814B)\n#define BIT_CLEAR_XTAL_GMP_4_0_8814B(x) ((x) & (~BITS_XTAL_GMP_4_0_8814B))\n#define BIT_GET_XTAL_GMP_4_0_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_GMP_4_0_8814B) & BIT_MASK_XTAL_GMP_4_0_8814B)\n#define BIT_SET_XTAL_GMP_4_0_8814B(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_GMP_4_0_8814B(x) | BIT_XTAL_GMP_4_0_8814B(v))\n\n/* 2 REG_ANAPAR_XTAL_1_8814B */\n\n#define BIT_SHIFT_XTAL_LDO_OK_1_0_8814B 30\n#define BIT_MASK_XTAL_LDO_OK_1_0_8814B 0x3\n#define BIT_XTAL_LDO_OK_1_0_8814B(x)                                           \\\n\t(((x) & BIT_MASK_XTAL_LDO_OK_1_0_8814B)                                \\\n\t << BIT_SHIFT_XTAL_LDO_OK_1_0_8814B)\n#define BITS_XTAL_LDO_OK_1_0_8814B                                             \\\n\t(BIT_MASK_XTAL_LDO_OK_1_0_8814B << BIT_SHIFT_XTAL_LDO_OK_1_0_8814B)\n#define BIT_CLEAR_XTAL_LDO_OK_1_0_8814B(x) ((x) & (~BITS_XTAL_LDO_OK_1_0_8814B))\n#define BIT_GET_XTAL_LDO_OK_1_0_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_XTAL_LDO_OK_1_0_8814B) &                            \\\n\t BIT_MASK_XTAL_LDO_OK_1_0_8814B)\n#define BIT_SET_XTAL_LDO_OK_1_0_8814B(x, v)                                    \\\n\t(BIT_CLEAR_XTAL_LDO_OK_1_0_8814B(x) | BIT_XTAL_LDO_OK_1_0_8814B(v))\n\n#define BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B 27\n#define BIT_MASK_XTAL_XORES_SEL_2_0_8814B 0x7\n#define BIT_XTAL_XORES_SEL_2_0_8814B(x)                                        \\\n\t(((x) & BIT_MASK_XTAL_XORES_SEL_2_0_8814B)                             \\\n\t << BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B)\n#define BITS_XTAL_XORES_SEL_2_0_8814B                                          \\\n\t(BIT_MASK_XTAL_XORES_SEL_2_0_8814B                                     \\\n\t << BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B)\n#define BIT_CLEAR_XTAL_XORES_SEL_2_0_8814B(x)                                  \\\n\t((x) & (~BITS_XTAL_XORES_SEL_2_0_8814B))\n#define BIT_GET_XTAL_XORES_SEL_2_0_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B) &                         \\\n\t BIT_MASK_XTAL_XORES_SEL_2_0_8814B)\n#define BIT_SET_XTAL_XORES_SEL_2_0_8814B(x, v)                                 \\\n\t(BIT_CLEAR_XTAL_XORES_SEL_2_0_8814B(x) |                               \\\n\t BIT_XTAL_XORES_SEL_2_0_8814B(v))\n\n#define BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B 25\n#define BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B 0x3\n#define BIT_XTAL_AAC_PK_SEL_1_0_8814B(x)                                       \\\n\t(((x) & BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B)                            \\\n\t << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B)\n#define BITS_XTAL_AAC_PK_SEL_1_0_8814B                                         \\\n\t(BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B                                    \\\n\t << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B)\n#define BIT_CLEAR_XTAL_AAC_PK_SEL_1_0_8814B(x)                                 \\\n\t((x) & (~BITS_XTAL_AAC_PK_SEL_1_0_8814B))\n#define BIT_GET_XTAL_AAC_PK_SEL_1_0_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B) &                        \\\n\t BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B)\n#define BIT_SET_XTAL_AAC_PK_SEL_1_0_8814B(x, v)                                \\\n\t(BIT_CLEAR_XTAL_AAC_PK_SEL_1_0_8814B(x) |                              \\\n\t BIT_XTAL_AAC_PK_SEL_1_0_8814B(v))\n\n#define BIT_EN_XTAL_AAC_PKDET_8814B BIT(24)\n#define BIT_EN_XTAL_AAC_GM_8814B BIT(23)\n#define BIT_XTAL_LPMODE_8814B BIT(22)\n\n#define BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B 19\n#define BIT_MASK_XTAL_SEL_TOK_2_0_8814B 0x7\n#define BIT_XTAL_SEL_TOK_2_0_8814B(x)                                          \\\n\t(((x) & BIT_MASK_XTAL_SEL_TOK_2_0_8814B)                               \\\n\t << BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B)\n#define BITS_XTAL_SEL_TOK_2_0_8814B                                            \\\n\t(BIT_MASK_XTAL_SEL_TOK_2_0_8814B << BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B)\n#define BIT_CLEAR_XTAL_SEL_TOK_2_0_8814B(x)                                    \\\n\t((x) & (~BITS_XTAL_SEL_TOK_2_0_8814B))\n#define BIT_GET_XTAL_SEL_TOK_2_0_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B) &                           \\\n\t BIT_MASK_XTAL_SEL_TOK_2_0_8814B)\n#define BIT_SET_XTAL_SEL_TOK_2_0_8814B(x, v)                                   \\\n\t(BIT_CLEAR_XTAL_SEL_TOK_2_0_8814B(x) | BIT_XTAL_SEL_TOK_2_0_8814B(v))\n\n#define BIT_XQSEL_RF_AWAKE_V2_8814B BIT(18)\n#define BIT_XQSEL_RF_INITIAL_V2_8814B BIT(17)\n#define BIT_XTAL_DELAY_USB_V1_8814B BIT(16)\n#define BIT_XTAL_DELAY_DIGI_V1_8814B BIT(15)\n#define BIT_XTAL_DELAY_AFE_V1_8814B BIT(14)\n#define BIT_XTAL_DRV_RF_LATCH_V3_8814B BIT(13)\n\n#define BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B 11\n#define BIT_MASK_XTAL_DRV_DIGI_1_0_8814B 0x3\n#define BIT_XTAL_DRV_DIGI_1_0_8814B(x)                                         \\\n\t(((x) & BIT_MASK_XTAL_DRV_DIGI_1_0_8814B)                              \\\n\t << BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B)\n#define BITS_XTAL_DRV_DIGI_1_0_8814B                                           \\\n\t(BIT_MASK_XTAL_DRV_DIGI_1_0_8814B << BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B)\n#define BIT_CLEAR_XTAL_DRV_DIGI_1_0_8814B(x)                                   \\\n\t((x) & (~BITS_XTAL_DRV_DIGI_1_0_8814B))\n#define BIT_GET_XTAL_DRV_DIGI_1_0_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B) &                          \\\n\t BIT_MASK_XTAL_DRV_DIGI_1_0_8814B)\n#define BIT_SET_XTAL_DRV_DIGI_1_0_8814B(x, v)                                  \\\n\t(BIT_CLEAR_XTAL_DRV_DIGI_1_0_8814B(x) | BIT_XTAL_DRV_DIGI_1_0_8814B(v))\n\n#define BIT_XTAL_GATED_DIGIN_8814B BIT(10)\n#define BIT_XTAL_GATED_DIGIP_8814B BIT(9)\n\n#define BIT_SHIFT_XTAL_DRV_USB_1_0_8814B 7\n#define BIT_MASK_XTAL_DRV_USB_1_0_8814B 0x3\n#define BIT_XTAL_DRV_USB_1_0_8814B(x)                                          \\\n\t(((x) & BIT_MASK_XTAL_DRV_USB_1_0_8814B)                               \\\n\t << BIT_SHIFT_XTAL_DRV_USB_1_0_8814B)\n#define BITS_XTAL_DRV_USB_1_0_8814B                                            \\\n\t(BIT_MASK_XTAL_DRV_USB_1_0_8814B << BIT_SHIFT_XTAL_DRV_USB_1_0_8814B)\n#define BIT_CLEAR_XTAL_DRV_USB_1_0_8814B(x)                                    \\\n\t((x) & (~BITS_XTAL_DRV_USB_1_0_8814B))\n#define BIT_GET_XTAL_DRV_USB_1_0_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_USB_1_0_8814B) &                           \\\n\t BIT_MASK_XTAL_DRV_USB_1_0_8814B)\n#define BIT_SET_XTAL_DRV_USB_1_0_8814B(x, v)                                   \\\n\t(BIT_CLEAR_XTAL_DRV_USB_1_0_8814B(x) | BIT_XTAL_DRV_USB_1_0_8814B(v))\n\n#define BIT_XTAL_GATED_USBN_8814B BIT(6)\n#define BIT_XTAL_GATED_USBP_8814B BIT(5)\n\n#define BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B 3\n#define BIT_MASK_XTAL_DRV_AFE_1_0_8814B 0x3\n#define BIT_XTAL_DRV_AFE_1_0_8814B(x)                                          \\\n\t(((x) & BIT_MASK_XTAL_DRV_AFE_1_0_8814B)                               \\\n\t << BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B)\n#define BITS_XTAL_DRV_AFE_1_0_8814B                                            \\\n\t(BIT_MASK_XTAL_DRV_AFE_1_0_8814B << BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B)\n#define BIT_CLEAR_XTAL_DRV_AFE_1_0_8814B(x)                                    \\\n\t((x) & (~BITS_XTAL_DRV_AFE_1_0_8814B))\n#define BIT_GET_XTAL_DRV_AFE_1_0_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B) &                           \\\n\t BIT_MASK_XTAL_DRV_AFE_1_0_8814B)\n#define BIT_SET_XTAL_DRV_AFE_1_0_8814B(x, v)                                   \\\n\t(BIT_CLEAR_XTAL_DRV_AFE_1_0_8814B(x) | BIT_XTAL_DRV_AFE_1_0_8814B(v))\n\n#define BIT_XTAL_GATED_AFEN_8814B BIT(2)\n#define BIT_XTAL_GATED_AFEP_8814B BIT(1)\n#define BIT_XTAL_DRV_RF1_1_8814B BIT(0)\n\n/* 2 REG_ANAPAR_XTAL_2_8814B */\n#define BIT_XTAL_DRV_RF2_LATCH_8814B BIT(6)\n\n#define BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B 4\n#define BIT_MASK_XTAL_DRV_RF2_1_0_8814B 0x3\n#define BIT_XTAL_DRV_RF2_1_0_8814B(x)                                          \\\n\t(((x) & BIT_MASK_XTAL_DRV_RF2_1_0_8814B)                               \\\n\t << BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B)\n#define BITS_XTAL_DRV_RF2_1_0_8814B                                            \\\n\t(BIT_MASK_XTAL_DRV_RF2_1_0_8814B << BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B)\n#define BIT_CLEAR_XTAL_DRV_RF2_1_0_8814B(x)                                    \\\n\t((x) & (~BITS_XTAL_DRV_RF2_1_0_8814B))\n#define BIT_GET_XTAL_DRV_RF2_1_0_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B) &                           \\\n\t BIT_MASK_XTAL_DRV_RF2_1_0_8814B)\n#define BIT_SET_XTAL_DRV_RF2_1_0_8814B(x, v)                                   \\\n\t(BIT_CLEAR_XTAL_DRV_RF2_1_0_8814B(x) | BIT_XTAL_DRV_RF2_1_0_8814B(v))\n\n#define BIT_XTAL_GATED_RF2N_8814B BIT(3)\n#define BIT_XTAL_GATED_RF2P_8814B BIT(2)\n#define BIT_XTAL_LDO_DI_8814B BIT(1)\n#define BIT_XTAL_SEL_PWR_8814B BIT(0)\n\n/* 2 REG_ANAPAR_XTAL_AAC_8814B */\n#define BIT_EN_XTAL_AAC_TRIG_8814B BIT(28)\n#define BIT_EN_XTAL_AAC_8814B BIT(27)\n#define BIT_EN_XTAL_AAC_DIGI_8814B BIT(26)\n\n#define BIT_SHIFT_GM_MANUAL_4_0_8814B 21\n#define BIT_MASK_GM_MANUAL_4_0_8814B 0x1f\n#define BIT_GM_MANUAL_4_0_8814B(x)                                             \\\n\t(((x) & BIT_MASK_GM_MANUAL_4_0_8814B) << BIT_SHIFT_GM_MANUAL_4_0_8814B)\n#define BITS_GM_MANUAL_4_0_8814B                                               \\\n\t(BIT_MASK_GM_MANUAL_4_0_8814B << BIT_SHIFT_GM_MANUAL_4_0_8814B)\n#define BIT_CLEAR_GM_MANUAL_4_0_8814B(x) ((x) & (~BITS_GM_MANUAL_4_0_8814B))\n#define BIT_GET_GM_MANUAL_4_0_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_GM_MANUAL_4_0_8814B) & BIT_MASK_GM_MANUAL_4_0_8814B)\n#define BIT_SET_GM_MANUAL_4_0_8814B(x, v)                                      \\\n\t(BIT_CLEAR_GM_MANUAL_4_0_8814B(x) | BIT_GM_MANUAL_4_0_8814B(v))\n\n#define BIT_SHIFT_GM_STUP_4_0_8814B 16\n#define BIT_MASK_GM_STUP_4_0_8814B 0x1f\n#define BIT_GM_STUP_4_0_8814B(x)                                               \\\n\t(((x) & BIT_MASK_GM_STUP_4_0_8814B) << BIT_SHIFT_GM_STUP_4_0_8814B)\n#define BITS_GM_STUP_4_0_8814B                                                 \\\n\t(BIT_MASK_GM_STUP_4_0_8814B << BIT_SHIFT_GM_STUP_4_0_8814B)\n#define BIT_CLEAR_GM_STUP_4_0_8814B(x) ((x) & (~BITS_GM_STUP_4_0_8814B))\n#define BIT_GET_GM_STUP_4_0_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_GM_STUP_4_0_8814B) & BIT_MASK_GM_STUP_4_0_8814B)\n#define BIT_SET_GM_STUP_4_0_8814B(x, v)                                        \\\n\t(BIT_CLEAR_GM_STUP_4_0_8814B(x) | BIT_GM_STUP_4_0_8814B(v))\n\n#define BIT_SHIFT_XTAL_CK_SET_2_0_8814B 13\n#define BIT_MASK_XTAL_CK_SET_2_0_8814B 0x7\n#define BIT_XTAL_CK_SET_2_0_8814B(x)                                           \\\n\t(((x) & BIT_MASK_XTAL_CK_SET_2_0_8814B)                                \\\n\t << BIT_SHIFT_XTAL_CK_SET_2_0_8814B)\n#define BITS_XTAL_CK_SET_2_0_8814B                                             \\\n\t(BIT_MASK_XTAL_CK_SET_2_0_8814B << BIT_SHIFT_XTAL_CK_SET_2_0_8814B)\n#define BIT_CLEAR_XTAL_CK_SET_2_0_8814B(x) ((x) & (~BITS_XTAL_CK_SET_2_0_8814B))\n#define BIT_GET_XTAL_CK_SET_2_0_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_XTAL_CK_SET_2_0_8814B) &                            \\\n\t BIT_MASK_XTAL_CK_SET_2_0_8814B)\n#define BIT_SET_XTAL_CK_SET_2_0_8814B(x, v)                                    \\\n\t(BIT_CLEAR_XTAL_CK_SET_2_0_8814B(x) | BIT_XTAL_CK_SET_2_0_8814B(v))\n\n#define BIT_SHIFT_GM_INIT_4_0_8814B 8\n#define BIT_MASK_GM_INIT_4_0_8814B 0x1f\n#define BIT_GM_INIT_4_0_8814B(x)                                               \\\n\t(((x) & BIT_MASK_GM_INIT_4_0_8814B) << BIT_SHIFT_GM_INIT_4_0_8814B)\n#define BITS_GM_INIT_4_0_8814B                                                 \\\n\t(BIT_MASK_GM_INIT_4_0_8814B << BIT_SHIFT_GM_INIT_4_0_8814B)\n#define BIT_CLEAR_GM_INIT_4_0_8814B(x) ((x) & (~BITS_GM_INIT_4_0_8814B))\n#define BIT_GET_GM_INIT_4_0_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_GM_INIT_4_0_8814B) & BIT_MASK_GM_INIT_4_0_8814B)\n#define BIT_SET_GM_INIT_4_0_8814B(x, v)                                        \\\n\t(BIT_CLEAR_GM_INIT_4_0_8814B(x) | BIT_GM_INIT_4_0_8814B(v))\n\n#define BIT_GM_STEP_8814B BIT(7)\n\n#define BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B 2\n#define BIT_MASK_XAAC_GM_OFFSET_4_0_8814B 0x1f\n#define BIT_XAAC_GM_OFFSET_4_0_8814B(x)                                        \\\n\t(((x) & BIT_MASK_XAAC_GM_OFFSET_4_0_8814B)                             \\\n\t << BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B)\n#define BITS_XAAC_GM_OFFSET_4_0_8814B                                          \\\n\t(BIT_MASK_XAAC_GM_OFFSET_4_0_8814B                                     \\\n\t << BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B)\n#define BIT_CLEAR_XAAC_GM_OFFSET_4_0_8814B(x)                                  \\\n\t((x) & (~BITS_XAAC_GM_OFFSET_4_0_8814B))\n#define BIT_GET_XAAC_GM_OFFSET_4_0_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B) &                         \\\n\t BIT_MASK_XAAC_GM_OFFSET_4_0_8814B)\n#define BIT_SET_XAAC_GM_OFFSET_4_0_8814B(x, v)                                 \\\n\t(BIT_CLEAR_XAAC_GM_OFFSET_4_0_8814B(x) |                               \\\n\t BIT_XAAC_GM_OFFSET_4_0_8814B(v))\n\n#define BIT_OFFSET_PLUS_8814B BIT(1)\n#define BIT_RESET_N_8814B BIT(0)\n\n/* 2 REG_ANAPAR_XTAL_R_ONLY_8814B */\n#define BIT_XTAL_PKDET_OUT_8814B BIT(6)\n\n#define BIT_SHIFT_XTAL_GM_AAC_4_0_8814B 1\n#define BIT_MASK_XTAL_GM_AAC_4_0_8814B 0x1f\n#define BIT_XTAL_GM_AAC_4_0_8814B(x)                                           \\\n\t(((x) & BIT_MASK_XTAL_GM_AAC_4_0_8814B)                                \\\n\t << BIT_SHIFT_XTAL_GM_AAC_4_0_8814B)\n#define BITS_XTAL_GM_AAC_4_0_8814B                                             \\\n\t(BIT_MASK_XTAL_GM_AAC_4_0_8814B << BIT_SHIFT_XTAL_GM_AAC_4_0_8814B)\n#define BIT_CLEAR_XTAL_GM_AAC_4_0_8814B(x) ((x) & (~BITS_XTAL_GM_AAC_4_0_8814B))\n#define BIT_GET_XTAL_GM_AAC_4_0_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_XTAL_GM_AAC_4_0_8814B) &                            \\\n\t BIT_MASK_XTAL_GM_AAC_4_0_8814B)\n#define BIT_SET_XTAL_GM_AAC_4_0_8814B(x, v)                                    \\\n\t(BIT_CLEAR_XTAL_GM_AAC_4_0_8814B(x) | BIT_XTAL_GM_AAC_4_0_8814B(v))\n\n#define BIT_XAAC_READY_8814B BIT(0)\n\n/* 2 REG_CPHY_LDO_8814B */\n\n#define BIT_SHIFT_CPHY_LDO_PD_8814B 12\n#define BIT_MASK_CPHY_LDO_PD_8814B 0x3\n#define BIT_CPHY_LDO_PD_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CPHY_LDO_PD_8814B) << BIT_SHIFT_CPHY_LDO_PD_8814B)\n#define BITS_CPHY_LDO_PD_8814B                                                 \\\n\t(BIT_MASK_CPHY_LDO_PD_8814B << BIT_SHIFT_CPHY_LDO_PD_8814B)\n#define BIT_CLEAR_CPHY_LDO_PD_8814B(x) ((x) & (~BITS_CPHY_LDO_PD_8814B))\n#define BIT_GET_CPHY_LDO_PD_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CPHY_LDO_PD_8814B) & BIT_MASK_CPHY_LDO_PD_8814B)\n#define BIT_SET_CPHY_LDO_PD_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CPHY_LDO_PD_8814B(x) | BIT_CPHY_LDO_PD_8814B(v))\n\n#define BIT_SHIFT_CPHY_LDO_SR_8814B 10\n#define BIT_MASK_CPHY_LDO_SR_8814B 0x3\n#define BIT_CPHY_LDO_SR_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CPHY_LDO_SR_8814B) << BIT_SHIFT_CPHY_LDO_SR_8814B)\n#define BITS_CPHY_LDO_SR_8814B                                                 \\\n\t(BIT_MASK_CPHY_LDO_SR_8814B << BIT_SHIFT_CPHY_LDO_SR_8814B)\n#define BIT_CLEAR_CPHY_LDO_SR_8814B(x) ((x) & (~BITS_CPHY_LDO_SR_8814B))\n#define BIT_GET_CPHY_LDO_SR_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CPHY_LDO_SR_8814B) & BIT_MASK_CPHY_LDO_SR_8814B)\n#define BIT_SET_CPHY_LDO_SR_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CPHY_LDO_SR_8814B(x) | BIT_CPHY_LDO_SR_8814B(v))\n\n#define BIT_SHIFT_CPHY_LDO_TUNEREF_8814B 8\n#define BIT_MASK_CPHY_LDO_TUNEREF_8814B 0x3\n#define BIT_CPHY_LDO_TUNEREF_8814B(x)                                          \\\n\t(((x) & BIT_MASK_CPHY_LDO_TUNEREF_8814B)                               \\\n\t << BIT_SHIFT_CPHY_LDO_TUNEREF_8814B)\n#define BITS_CPHY_LDO_TUNEREF_8814B                                            \\\n\t(BIT_MASK_CPHY_LDO_TUNEREF_8814B << BIT_SHIFT_CPHY_LDO_TUNEREF_8814B)\n#define BIT_CLEAR_CPHY_LDO_TUNEREF_8814B(x)                                    \\\n\t((x) & (~BITS_CPHY_LDO_TUNEREF_8814B))\n#define BIT_GET_CPHY_LDO_TUNEREF_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_CPHY_LDO_TUNEREF_8814B) &                           \\\n\t BIT_MASK_CPHY_LDO_TUNEREF_8814B)\n#define BIT_SET_CPHY_LDO_TUNEREF_8814B(x, v)                                   \\\n\t(BIT_CLEAR_CPHY_LDO_TUNEREF_8814B(x) | BIT_CPHY_LDO_TUNEREF_8814B(v))\n\n#define BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B 5\n#define BIT_MASK_CPHY_LDO_TUNE_VO_8814B 0x7\n#define BIT_CPHY_LDO_TUNE_VO_8814B(x)                                          \\\n\t(((x) & BIT_MASK_CPHY_LDO_TUNE_VO_8814B)                               \\\n\t << BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B)\n#define BITS_CPHY_LDO_TUNE_VO_8814B                                            \\\n\t(BIT_MASK_CPHY_LDO_TUNE_VO_8814B << BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B)\n#define BIT_CLEAR_CPHY_LDO_TUNE_VO_8814B(x)                                    \\\n\t((x) & (~BITS_CPHY_LDO_TUNE_VO_8814B))\n#define BIT_GET_CPHY_LDO_TUNE_VO_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B) &                           \\\n\t BIT_MASK_CPHY_LDO_TUNE_VO_8814B)\n#define BIT_SET_CPHY_LDO_TUNE_VO_8814B(x, v)                                   \\\n\t(BIT_CLEAR_CPHY_LDO_TUNE_VO_8814B(x) | BIT_CPHY_LDO_TUNE_VO_8814B(v))\n\n#define BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B 2\n#define BIT_MASK_CPHY_LDO_OCP_VTH_8814B 0x7\n#define BIT_CPHY_LDO_OCP_VTH_8814B(x)                                          \\\n\t(((x) & BIT_MASK_CPHY_LDO_OCP_VTH_8814B)                               \\\n\t << BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B)\n#define BITS_CPHY_LDO_OCP_VTH_8814B                                            \\\n\t(BIT_MASK_CPHY_LDO_OCP_VTH_8814B << BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B)\n#define BIT_CLEAR_CPHY_LDO_OCP_VTH_8814B(x)                                    \\\n\t((x) & (~BITS_CPHY_LDO_OCP_VTH_8814B))\n#define BIT_GET_CPHY_LDO_OCP_VTH_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B) &                           \\\n\t BIT_MASK_CPHY_LDO_OCP_VTH_8814B)\n#define BIT_SET_CPHY_LDO_OCP_VTH_8814B(x, v)                                   \\\n\t(BIT_CLEAR_CPHY_LDO_OCP_VTH_8814B(x) | BIT_CPHY_LDO_OCP_VTH_8814B(v))\n\n#define BIT_SHIFT_VREF_LDO_OK_8814B 0\n#define BIT_MASK_VREF_LDO_OK_8814B 0x3\n#define BIT_VREF_LDO_OK_8814B(x)                                               \\\n\t(((x) & BIT_MASK_VREF_LDO_OK_8814B) << BIT_SHIFT_VREF_LDO_OK_8814B)\n#define BITS_VREF_LDO_OK_8814B                                                 \\\n\t(BIT_MASK_VREF_LDO_OK_8814B << BIT_SHIFT_VREF_LDO_OK_8814B)\n#define BIT_CLEAR_VREF_LDO_OK_8814B(x) ((x) & (~BITS_VREF_LDO_OK_8814B))\n#define BIT_GET_VREF_LDO_OK_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_VREF_LDO_OK_8814B) & BIT_MASK_VREF_LDO_OK_8814B)\n#define BIT_SET_VREF_LDO_OK_8814B(x, v)                                        \\\n\t(BIT_CLEAR_VREF_LDO_OK_8814B(x) | BIT_VREF_LDO_OK_8814B(v))\n\n/* 2 REG_CPHY_BG_8814B */\n\n#define BIT_SHIFT_BG_8814B 0\n#define BIT_MASK_BG_8814B 0x7\n#define BIT_BG_8814B(x) (((x) & BIT_MASK_BG_8814B) << BIT_SHIFT_BG_8814B)\n#define BITS_BG_8814B (BIT_MASK_BG_8814B << BIT_SHIFT_BG_8814B)\n#define BIT_CLEAR_BG_8814B(x) ((x) & (~BITS_BG_8814B))\n#define BIT_GET_BG_8814B(x) (((x) >> BIT_SHIFT_BG_8814B) & BIT_MASK_BG_8814B)\n#define BIT_SET_BG_8814B(x, v) (BIT_CLEAR_BG_8814B(x) | BIT_BG_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_HIMR_4_8814B */\n#define BIT_TXBCN_OK_PORT4_8814B BIT(31)\n#define BIT_TXBCN_OK_PORT3_8814B BIT(30)\n#define BIT_TXBCN_OK_PORT2_8814B BIT(29)\n#define BIT_TXBCN_OK_PORT1_8814B BIT(28)\n#define BIT_TXBCN15OK_8814B BIT(23)\n#define BIT_TXBCN14OK_8814B BIT(22)\n#define BIT_TXBCN13OK_8814B BIT(21)\n#define BIT_TXBCN12OK_8814B BIT(20)\n#define BIT_TXBCN11OK_8814B BIT(19)\n#define BIT_TXBCN10OK_8814B BIT(18)\n#define BIT_TXBCN9OK_8814B BIT(17)\n#define BIT_TXBCN8OK_8814B BIT(16)\n#define BIT_BCNDERR_PORT4_8814B BIT(15)\n#define BIT_BCNDERR_PORT3_8814B BIT(14)\n#define BIT_BCNDERR_PORT2_8814B BIT(13)\n#define BIT_BCNDERR_PORT1_8814B BIT(12)\n#define BIT_TXBCN15ERR_8814B BIT(7)\n#define BIT_TXBCN14ERR_8814B BIT(6)\n#define BIT_TXBCN13ERR_8814B BIT(5)\n#define BIT_TXBCN12ERR_8814B BIT(4)\n#define BIT_TXBCN11ERR_8814B BIT(3)\n#define BIT_TXBCN10ERR_8814B BIT(2)\n#define BIT_TXBCN9ERR_8814B BIT(1)\n#define BIT_TXBCN8ERR_8814B BIT(0)\n\n/* 2 REG_HISR_4_8814B */\n#define BIT_TXBCN_OK_PORT4_8814B BIT(31)\n#define BIT_TXBCN_OK_PORT3_8814B BIT(30)\n#define BIT_TXBCN_OK_PORT2_8814B BIT(29)\n#define BIT_TXBCN_OK_PORT1_8814B BIT(28)\n#define BIT_TXBCN15OK_8814B BIT(23)\n#define BIT_TXBCN14OK_8814B BIT(22)\n#define BIT_TXBCN13OK_8814B BIT(21)\n#define BIT_TXBCN12OK_8814B BIT(20)\n#define BIT_TXBCN11OK_8814B BIT(19)\n#define BIT_TXBCN10OK_8814B BIT(18)\n#define BIT_TXBCN9OK_8814B BIT(17)\n#define BIT_TXBCN8OK_8814B BIT(16)\n#define BIT_BCNDERR_PORT4_8814B BIT(15)\n#define BIT_BCNDERR_PORT3_8814B BIT(14)\n#define BIT_BCNDERR_PORT2_8814B BIT(13)\n#define BIT_BCNDERR_PORT1_8814B BIT(12)\n#define BIT_TXBCN15ERR_8814B BIT(7)\n#define BIT_TXBCN14ERR_8814B BIT(6)\n#define BIT_TXBCN13ERR_8814B BIT(5)\n#define BIT_TXBCN12ERR_8814B BIT(4)\n#define BIT_TXBCN11ERR_8814B BIT(3)\n#define BIT_TXBCN10ERR_8814B BIT(2)\n#define BIT_TXBCN9ERR_8814B BIT(1)\n#define BIT_TXBCN8ERR_8814B BIT(0)\n\n/* 2 REG_HIMR_5_8814B */\n#define BIT_BCNDMAINT15_8814B BIT(23)\n#define BIT_BCNDMAINT14_8814B BIT(22)\n#define BIT_BCNDMAINT13_8814B BIT(21)\n#define BIT_BCNDMAINT12_8814B BIT(20)\n#define BIT_BCNDMAINT11_8814B BIT(19)\n#define BIT_BCNDMAINT10_8814B BIT(18)\n#define BIT_BCNDMAINT9_8814B BIT(17)\n#define BIT_BCNDMAINT8_8814B BIT(16)\n#define BIT_BCNDERR_PORT4_8814B BIT(15)\n#define BIT_BCNDERR_PORT3_8814B BIT(14)\n#define BIT_BCNDERR_PORT2_8814B BIT(13)\n#define BIT_BCNDERR_PORT1_8814B BIT(12)\n#define BIT_BCNDERR15_8814B BIT(7)\n#define BIT_BCNDERR14_8814B BIT(6)\n#define BIT_BCNDERR13_8814B BIT(5)\n#define BIT_BCNDERR12_8814B BIT(4)\n#define BIT_BCNDERR11_8814B BIT(3)\n#define BIT_BCNDERR10_8814B BIT(2)\n#define BIT_BCNDERR9_8814B BIT(1)\n#define BIT_BCNDERR8_8814B BIT(0)\n\n/* 2 REG_HISR_5_8814B */\n#define BIT_BCNDMAINT15_8814B BIT(23)\n#define BIT_BCNDMAINT14_8814B BIT(22)\n#define BIT_BCNDMAINT13_8814B BIT(21)\n#define BIT_BCNDMAINT12_8814B BIT(20)\n#define BIT_BCNDMAINT11_8814B BIT(19)\n#define BIT_BCNDMAINT10_8814B BIT(18)\n#define BIT_BCNDMAINT9_8814B BIT(17)\n#define BIT_BCNDMAINT8_8814B BIT(16)\n#define BIT_BCNDERR_PORT4_8814B BIT(15)\n#define BIT_BCNDERR_PORT3_8814B BIT(14)\n#define BIT_BCNDERR_PORT2_8814B BIT(13)\n#define BIT_BCNDERR_PORT1_8814B BIT(12)\n#define BIT_BCNDERR15_8814B BIT(7)\n#define BIT_BCNDERR14_8814B BIT(6)\n#define BIT_BCNDERR13_8814B BIT(5)\n#define BIT_BCNDERR12_8814B BIT(4)\n#define BIT_BCNDERR11_8814B BIT(3)\n#define BIT_BCNDERR10_8814B BIT(2)\n#define BIT_BCNDERR9_8814B BIT(1)\n#define BIT_BCNDERR8_8814B BIT(0)\n\n/* 2 REG_SYS_CFG5_8814B */\n#define BIT_LPS_STATUS_8814B BIT(3)\n#define BIT_HCI_TXDMA_BUSY_8814B BIT(2)\n#define BIT_HCI_TXDMA_ALLOW_8814B BIT(1)\n#define BIT_FW_CTRL_HCI_TXDMA_EN_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_HIMR_6_8814B */\n#define BIT_ATIMEND_PORT4_8814B BIT(31)\n#define BIT_ATIMEND_PORT3_8814B BIT(30)\n#define BIT_ATIMEND_PORT2_8814B BIT(29)\n#define BIT_ATIMEND_PORT1_8814B BIT(28)\n#define BIT_ATIMEND15_8814B BIT(23)\n#define BIT_ATIMEND14_8814B BIT(22)\n#define BIT_ATIMEND13_8814B BIT(21)\n#define BIT_ATIMEND12_8814B BIT(20)\n#define BIT_ATIMEND11_8814B BIT(19)\n#define BIT_ATIMEND10_8814B BIT(18)\n#define BIT_ATIMEND9_8814B BIT(17)\n#define BIT_ATIMEND8_8814B BIT(16)\n#define BIT_PS_TIMER_EARLY_INT_5_8814B BIT(5)\n#define BIT_PS_TIMER_EARLY_INT_4_8814B BIT(4)\n#define BIT_PS_TIMER_EARLY_INT_3_8814B BIT(3)\n#define BIT_PS_TIMER_EARLY_INT_2_8814B BIT(2)\n#define BIT_PS_TIMER_EARLY_INT_1_8814B BIT(1)\n#define BIT_PS_TIMER_EARLY_INT_0_8814B BIT(0)\n\n/* 2 REG_HISR_6_8814B */\n#define BIT_ATIMEND_PORT4_8814B BIT(31)\n#define BIT_ATIMEND_PORT3_8814B BIT(30)\n#define BIT_ATIMEND_PORT2_8814B BIT(29)\n#define BIT_ATIMEND_PORT1_8814B BIT(28)\n#define BIT_ATIMEND15_8814B BIT(23)\n#define BIT_ATIMEND14_8814B BIT(22)\n#define BIT_ATIMEND13_8814B BIT(21)\n#define BIT_ATIMEND12_8814B BIT(20)\n#define BIT_ATIMEND11_8814B BIT(19)\n#define BIT_ATIMEND10_8814B BIT(18)\n#define BIT_ATIMEND9_8814B BIT(17)\n#define BIT_ATIMEND8_8814B BIT(16)\n#define BIT_PS_TIMER_EARLY_INT_5_8814B BIT(5)\n#define BIT_PS_TIMER_EARLY_INT_4_8814B BIT(4)\n#define BIT_PS_TIMER_EARLY_INT_3_8814B BIT(3)\n#define BIT_PS_TIMER_EARLY_INT_2_8814B BIT(2)\n#define BIT_PS_TIMER_EARLY_INT_1_8814B BIT(1)\n#define BIT_PS_TIMER_EARLY_INT_0_8814B BIT(0)\n\n/* 2 REG_CPU_DMEM_CON_8814B */\n#define BIT_WDT_AUTO_MODE_8814B BIT(22)\n#define BIT_WDT_PLATFORM_EN_8814B BIT(21)\n#define BIT_WDT_CPU_EN_8814B BIT(20)\n#define BIT_WDT_OPT_IOWRAPPER_8814B BIT(19)\n#define BIT_ANA_PORT_IDLE_8814B BIT(18)\n#define BIT_MAC_PORT_IDLE_8814B BIT(17)\n#define BIT_WL_PLATFORM_RST_8814B BIT(16)\n#define BIT_WL_SECURITY_CLK_8814B BIT(15)\n#define BIT_DDMA_EN_8814B BIT(8)\n\n#define BIT_SHIFT_CPU_DMEM_CON_8814B 0\n#define BIT_MASK_CPU_DMEM_CON_8814B 0xff\n#define BIT_CPU_DMEM_CON_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CPU_DMEM_CON_8814B) << BIT_SHIFT_CPU_DMEM_CON_8814B)\n#define BITS_CPU_DMEM_CON_8814B                                                \\\n\t(BIT_MASK_CPU_DMEM_CON_8814B << BIT_SHIFT_CPU_DMEM_CON_8814B)\n#define BIT_CLEAR_CPU_DMEM_CON_8814B(x) ((x) & (~BITS_CPU_DMEM_CON_8814B))\n#define BIT_GET_CPU_DMEM_CON_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CPU_DMEM_CON_8814B) & BIT_MASK_CPU_DMEM_CON_8814B)\n#define BIT_SET_CPU_DMEM_CON_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CPU_DMEM_CON_8814B(x) | BIT_CPU_DMEM_CON_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_BOOT_REASON_8814B */\n\n#define BIT_SHIFT_BOOT_REASON_V1_8814B 0\n#define BIT_MASK_BOOT_REASON_V1_8814B 0x7\n#define BIT_BOOT_REASON_V1_8814B(x)                                            \\\n\t(((x) & BIT_MASK_BOOT_REASON_V1_8814B)                                 \\\n\t << BIT_SHIFT_BOOT_REASON_V1_8814B)\n#define BITS_BOOT_REASON_V1_8814B                                              \\\n\t(BIT_MASK_BOOT_REASON_V1_8814B << BIT_SHIFT_BOOT_REASON_V1_8814B)\n#define BIT_CLEAR_BOOT_REASON_V1_8814B(x) ((x) & (~BITS_BOOT_REASON_V1_8814B))\n#define BIT_GET_BOOT_REASON_V1_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_BOOT_REASON_V1_8814B) &                             \\\n\t BIT_MASK_BOOT_REASON_V1_8814B)\n#define BIT_SET_BOOT_REASON_V1_8814B(x, v)                                     \\\n\t(BIT_CLEAR_BOOT_REASON_V1_8814B(x) | BIT_BOOT_REASON_V1_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_DATA_CPU_CTL0_8814B */\n#define BIT_DATA_FW_READY_8814B BIT(31)\n#define BIT_WDT_SYS_RST_8814B BIT(13)\n#define BIT_WDT_ENABLE_8814B BIT(12)\n\n#define BIT_SHIFT_BOOT_SEL_8814B 6\n#define BIT_MASK_BOOT_SEL_8814B 0x3\n#define BIT_BOOT_SEL_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_BOOT_SEL_8814B) << BIT_SHIFT_BOOT_SEL_8814B)\n#define BITS_BOOT_SEL_8814B                                                    \\\n\t(BIT_MASK_BOOT_SEL_8814B << BIT_SHIFT_BOOT_SEL_8814B)\n#define BIT_CLEAR_BOOT_SEL_8814B(x) ((x) & (~BITS_BOOT_SEL_8814B))\n#define BIT_GET_BOOT_SEL_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_BOOT_SEL_8814B) & BIT_MASK_BOOT_SEL_8814B)\n#define BIT_SET_BOOT_SEL_8814B(x, v)                                           \\\n\t(BIT_CLEAR_BOOT_SEL_8814B(x) | BIT_BOOT_SEL_8814B(v))\n\n#define BIT_CLK_SEL_8814B BIT(4)\n#define BIT_DATA_PLATFORM_RST_8814B BIT(1)\n#define BIT_DATA_CPU_RST_8814B BIT(0)\n\n/* 2 REG_DATA_CPU_CTL1_8814B */\n#define BIT_HOST_INTERFACE_IO_PATH_8814B BIT(7)\n#define BIT_EN_TXDMA_OFLD_8814B BIT(6)\n#define BIT_EN_RXDMA_OFLD_8814B BIT(5)\n#define BIT_EN_HCI_DMA_TX_8814B BIT(4)\n#define BIT_EN_HCI_DMA_RX_8814B BIT(3)\n#define BIT_EN_AXI_DMA_TX_8814B BIT(2)\n#define BIT_EN_AXI_DMA_RX_8814B BIT(1)\n#define BIT_EN_PKT_ENG_8814B BIT(0)\n\n/* 2 REG_TXDMA_STOP_HIMR_8814B */\n\n#define BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B 0\n#define BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B 0x1ffff\n#define BIT_NTH_TXDMA_STOP_INT_MSK_8814B(x)                                    \\\n\t(((x) & BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B)                         \\\n\t << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B)\n#define BITS_NTH_TXDMA_STOP_INT_MSK_8814B                                      \\\n\t(BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B                                 \\\n\t << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B)\n#define BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK_8814B(x)                              \\\n\t((x) & (~BITS_NTH_TXDMA_STOP_INT_MSK_8814B))\n#define BIT_GET_NTH_TXDMA_STOP_INT_MSK_8814B(x)                                \\\n\t(((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B) &                     \\\n\t BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B)\n#define BIT_SET_NTH_TXDMA_STOP_INT_MSK_8814B(x, v)                             \\\n\t(BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK_8814B(x) |                           \\\n\t BIT_NTH_TXDMA_STOP_INT_MSK_8814B(v))\n\n/* 2 REG_TXDMA_STOP_HISR_8814B */\n\n#define BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B 0\n#define BIT_MASK_NTH_TXDMA_STOP_INT_8814B 0x1ffff\n#define BIT_NTH_TXDMA_STOP_INT_8814B(x)                                        \\\n\t(((x) & BIT_MASK_NTH_TXDMA_STOP_INT_8814B)                             \\\n\t << BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B)\n#define BITS_NTH_TXDMA_STOP_INT_8814B                                          \\\n\t(BIT_MASK_NTH_TXDMA_STOP_INT_8814B                                     \\\n\t << BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B)\n#define BIT_CLEAR_NTH_TXDMA_STOP_INT_8814B(x)                                  \\\n\t((x) & (~BITS_NTH_TXDMA_STOP_INT_8814B))\n#define BIT_GET_NTH_TXDMA_STOP_INT_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B) &                         \\\n\t BIT_MASK_NTH_TXDMA_STOP_INT_8814B)\n#define BIT_SET_NTH_TXDMA_STOP_INT_8814B(x, v)                                 \\\n\t(BIT_CLEAR_NTH_TXDMA_STOP_INT_8814B(x) |                               \\\n\t BIT_NTH_TXDMA_STOP_INT_8814B(v))\n\n/* 2 REG_TXDMA_START_HIMR_8814B */\n\n#define BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B 0\n#define BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B 0x1ffff\n#define BIT_NTH_TXDMA_START_INT_MSK_8814B(x)                                   \\\n\t(((x) & BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B)                        \\\n\t << BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B)\n#define BITS_NTH_TXDMA_START_INT_MSK_8814B                                     \\\n\t(BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B                                \\\n\t << BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B)\n#define BIT_CLEAR_NTH_TXDMA_START_INT_MSK_8814B(x)                             \\\n\t((x) & (~BITS_NTH_TXDMA_START_INT_MSK_8814B))\n#define BIT_GET_NTH_TXDMA_START_INT_MSK_8814B(x)                               \\\n\t(((x) >> BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B) &                    \\\n\t BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B)\n#define BIT_SET_NTH_TXDMA_START_INT_MSK_8814B(x, v)                            \\\n\t(BIT_CLEAR_NTH_TXDMA_START_INT_MSK_8814B(x) |                          \\\n\t BIT_NTH_TXDMA_START_INT_MSK_8814B(v))\n\n/* 2 REG_TXDMA_START_HISR_8814B */\n\n#define BIT_SHIFT_NTH_TXDMA_START_INT_8814B 0\n#define BIT_MASK_NTH_TXDMA_START_INT_8814B 0x1ffff\n#define BIT_NTH_TXDMA_START_INT_8814B(x)                                       \\\n\t(((x) & BIT_MASK_NTH_TXDMA_START_INT_8814B)                            \\\n\t << BIT_SHIFT_NTH_TXDMA_START_INT_8814B)\n#define BITS_NTH_TXDMA_START_INT_8814B                                         \\\n\t(BIT_MASK_NTH_TXDMA_START_INT_8814B                                    \\\n\t << BIT_SHIFT_NTH_TXDMA_START_INT_8814B)\n#define BIT_CLEAR_NTH_TXDMA_START_INT_8814B(x)                                 \\\n\t((x) & (~BITS_NTH_TXDMA_START_INT_8814B))\n#define BIT_GET_NTH_TXDMA_START_INT_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_NTH_TXDMA_START_INT_8814B) &                        \\\n\t BIT_MASK_NTH_TXDMA_START_INT_8814B)\n#define BIT_SET_NTH_TXDMA_START_INT_8814B(x, v)                                \\\n\t(BIT_CLEAR_NTH_TXDMA_START_INT_8814B(x) |                              \\\n\t BIT_NTH_TXDMA_START_INT_8814B(v))\n\n/* 2 REG_NFCPAD_CTRL_8814B */\n#define BIT_PAD_SHUTDW_8814B BIT(18)\n#define BIT_SYSON_NFC_PAD_8814B BIT(17)\n#define BIT_NFC_INT_PAD_CTRL_8814B BIT(16)\n#define BIT_NFC_RFDIS_PAD_CTRL_8814B BIT(15)\n#define BIT_NFC_CLK_PAD_CTRL_8814B BIT(14)\n#define BIT_NFC_DATA_PAD_CTRL_8814B BIT(13)\n#define BIT_NFC_PAD_PULL_CTRL_8814B BIT(12)\n\n#define BIT_SHIFT_NFCPAD_IO_SEL_8814B 8\n#define BIT_MASK_NFCPAD_IO_SEL_8814B 0xf\n#define BIT_NFCPAD_IO_SEL_8814B(x)                                             \\\n\t(((x) & BIT_MASK_NFCPAD_IO_SEL_8814B) << BIT_SHIFT_NFCPAD_IO_SEL_8814B)\n#define BITS_NFCPAD_IO_SEL_8814B                                               \\\n\t(BIT_MASK_NFCPAD_IO_SEL_8814B << BIT_SHIFT_NFCPAD_IO_SEL_8814B)\n#define BIT_CLEAR_NFCPAD_IO_SEL_8814B(x) ((x) & (~BITS_NFCPAD_IO_SEL_8814B))\n#define BIT_GET_NFCPAD_IO_SEL_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8814B) & BIT_MASK_NFCPAD_IO_SEL_8814B)\n#define BIT_SET_NFCPAD_IO_SEL_8814B(x, v)                                      \\\n\t(BIT_CLEAR_NFCPAD_IO_SEL_8814B(x) | BIT_NFCPAD_IO_SEL_8814B(v))\n\n#define BIT_SHIFT_NFCPAD_OUT_8814B 4\n#define BIT_MASK_NFCPAD_OUT_8814B 0xf\n#define BIT_NFCPAD_OUT_8814B(x)                                                \\\n\t(((x) & BIT_MASK_NFCPAD_OUT_8814B) << BIT_SHIFT_NFCPAD_OUT_8814B)\n#define BITS_NFCPAD_OUT_8814B                                                  \\\n\t(BIT_MASK_NFCPAD_OUT_8814B << BIT_SHIFT_NFCPAD_OUT_8814B)\n#define BIT_CLEAR_NFCPAD_OUT_8814B(x) ((x) & (~BITS_NFCPAD_OUT_8814B))\n#define BIT_GET_NFCPAD_OUT_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_NFCPAD_OUT_8814B) & BIT_MASK_NFCPAD_OUT_8814B)\n#define BIT_SET_NFCPAD_OUT_8814B(x, v)                                         \\\n\t(BIT_CLEAR_NFCPAD_OUT_8814B(x) | BIT_NFCPAD_OUT_8814B(v))\n\n#define BIT_SHIFT_NFCPAD_IN_8814B 0\n#define BIT_MASK_NFCPAD_IN_8814B 0xf\n#define BIT_NFCPAD_IN_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_NFCPAD_IN_8814B) << BIT_SHIFT_NFCPAD_IN_8814B)\n#define BITS_NFCPAD_IN_8814B                                                   \\\n\t(BIT_MASK_NFCPAD_IN_8814B << BIT_SHIFT_NFCPAD_IN_8814B)\n#define BIT_CLEAR_NFCPAD_IN_8814B(x) ((x) & (~BITS_NFCPAD_IN_8814B))\n#define BIT_GET_NFCPAD_IN_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_NFCPAD_IN_8814B) & BIT_MASK_NFCPAD_IN_8814B)\n#define BIT_SET_NFCPAD_IN_8814B(x, v)                                          \\\n\t(BIT_CLEAR_NFCPAD_IN_8814B(x) | BIT_NFCPAD_IN_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_HIMR2_8814B */\n#define BIT_BCNDMAINT_P4_MSK_8814B BIT(31)\n#define BIT_BCNDMAINT_P3_MSK_8814B BIT(30)\n#define BIT_BCNDMAINT_P2_MSK_8814B BIT(29)\n#define BIT_BCNDMAINT_P1_MSK_8814B BIT(28)\n#define BIT_SCH_PHY_TXOP_SIFS_INT_MSK_8814B BIT(23)\n#define BIT_ATIMEND7_MSK_8814B BIT(22)\n#define BIT_ATIMEND6_MSK_8814B BIT(21)\n#define BIT_ATIMEND5_MSK_8814B BIT(20)\n#define BIT_ATIMEND4_MSK_8814B BIT(19)\n#define BIT_ATIMEND3_MSK_8814B BIT(18)\n#define BIT_ATIMEND2_MSK_8814B BIT(17)\n#define BIT_ATIMEND1_MSK_8814B BIT(16)\n#define BIT_TXBCN7OK_MSK_8814B BIT(14)\n#define BIT_TXBCN6OK_MSK_8814B BIT(13)\n#define BIT_TXBCN5OK_MSK_8814B BIT(12)\n#define BIT_TXBCN4OK_MSK_8814B BIT(11)\n#define BIT_TXBCN3OK_MSK_8814B BIT(10)\n#define BIT_TXBCN2OK_MSK_8814B BIT(9)\n#define BIT_TXBCN1OK_MSK_V1_8814B BIT(8)\n#define BIT_TXBCN7ERR_MSK_8814B BIT(6)\n#define BIT_TXBCN6ERR_MSK_8814B BIT(5)\n#define BIT_TXBCN5ERR_MSK_8814B BIT(4)\n#define BIT_TXBCN4ERR_MSK_8814B BIT(3)\n#define BIT_TXBCN3ERR_MSK_8814B BIT(2)\n#define BIT_TXBCN2ERR_MSK_8814B BIT(1)\n#define BIT_TXBCN1ERR_MSK_V1_8814B BIT(0)\n\n/* 2 REG_HISR2_8814B */\n#define BIT_BCNDMAINT_P4_8814B BIT(31)\n#define BIT_BCNDMAINT_P3_8814B BIT(30)\n#define BIT_BCNDMAINT_P2_8814B BIT(29)\n#define BIT_BCNDMAINT_P1_8814B BIT(28)\n#define BIT_SCH_PHY_TXOP_SIFS_INT_8814B BIT(23)\n#define BIT_ATIMEND7_8814B BIT(22)\n#define BIT_ATIMEND6_8814B BIT(21)\n#define BIT_ATIMEND5_8814B BIT(20)\n#define BIT_ATIMEND4_8814B BIT(19)\n#define BIT_ATIMEND3_8814B BIT(18)\n#define BIT_ATIMEND2_8814B BIT(17)\n#define BIT_ATIMEND1_8814B BIT(16)\n#define BIT_TXBCN7OK_8814B BIT(14)\n#define BIT_TXBCN6OK_8814B BIT(13)\n#define BIT_TXBCN5OK_8814B BIT(12)\n#define BIT_TXBCN4OK_8814B BIT(11)\n#define BIT_TXBCN3OK_8814B BIT(10)\n#define BIT_TXBCN2OK_8814B BIT(9)\n#define BIT_TXBCN1OK_8814B BIT(8)\n#define BIT_TXBCN7ERR_8814B BIT(6)\n#define BIT_TXBCN6ERR_8814B BIT(5)\n#define BIT_TXBCN5ERR_8814B BIT(4)\n#define BIT_TXBCN4ERR_8814B BIT(3)\n#define BIT_TXBCN3ERR_8814B BIT(2)\n#define BIT_TXBCN2ERR_8814B BIT(1)\n#define BIT_TXBCN1ERR_8814B BIT(0)\n\n/* 2 REG_HIMR3_8814B */\n#define BIT_GTINT12_MSK_8814B BIT(24)\n#define BIT_GTINT11_MSK_8814B BIT(23)\n#define BIT_GTINT10_MSK_8814B BIT(22)\n#define BIT_GTINT9_MSK_8814B BIT(21)\n#define BIT_RX_DESC_BUF_FULL_MSK_8814B BIT(20)\n#define BIT_CPHY_LDO_OCP_DET_INT_MSK_8814B BIT(19)\n#define BIT_WDT_PLATFORM_INT_MSK_8814B BIT(18)\n#define BIT_WDT_CPU_INT_MSK_8814B BIT(17)\n#define BIT_SETH2CDOK_MASK_8814B BIT(16)\n#define BIT_H2C_CMD_FULL_MASK_8814B BIT(15)\n#define BIT_PKT_TRANS_ERR_MASK_8814B BIT(14)\n#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8814B BIT(13)\n#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8814B BIT(12)\n#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8814B BIT(11)\n#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8814B BIT(10)\n#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8814B BIT(9)\n#define BIT_SEARCH_FAIL_MSK_8814B BIT(8)\n#define BIT_PWR_INT_127TO96_MASK_8814B BIT(7)\n#define BIT_PWR_INT_95TO64_MASK_8814B BIT(6)\n#define BIT_PWR_INT_63TO32_MASK_8814B BIT(5)\n#define BIT_PWR_INT_31TO0_MASK_8814B BIT(4)\n#define BIT_RX_DMA_STUCK_MSK_8814B BIT(3)\n#define BIT_TX_DMA_STUCK_MSK_8814B BIT(2)\n#define BIT_DDMA0_LP_INT_MSK_8814B BIT(1)\n#define BIT_DDMA0_HP_INT_MSK_8814B BIT(0)\n\n/* 2 REG_HISR3_8814B */\n#define BIT_GTINT12_8814B BIT(24)\n#define BIT_GTINT11_8814B BIT(23)\n#define BIT_GTINT10_8814B BIT(22)\n#define BIT_GTINT9_8814B BIT(21)\n#define BIT_RX_DESC_BUF_FULL_8814B BIT(20)\n#define BIT_CPHY_LDO_OCP_DET_INT_8814B BIT(19)\n#define BIT_WDT_PLATFORM_INT_8814B BIT(18)\n#define BIT_WDT_CPU_INT_8814B BIT(17)\n#define BIT_SETH2CDOK_8814B BIT(16)\n#define BIT_H2C_CMD_FULL_8814B BIT(15)\n#define BIT_PKT_TRANS_ERR_8814B BIT(14)\n#define BIT_TXSHORTCUT_TXDESUPDATEOK_8814B BIT(13)\n#define BIT_TXSHORTCUT_BKUPDATEOK_8814B BIT(12)\n#define BIT_TXSHORTCUT_BEUPDATEOK_8814B BIT(11)\n#define BIT_TXSHORTCUT_VIUPDATEOK_8814B BIT(10)\n#define BIT_TXSHORTCUT_VOUPDATEOK_8814B BIT(9)\n#define BIT_SEARCH_FAIL_8814B BIT(8)\n#define BIT_PWR_INT_127TO96_8814B BIT(7)\n#define BIT_PWR_INT_95TO64_8814B BIT(6)\n#define BIT_PWR_INT_63TO32_8814B BIT(5)\n#define BIT_PWR_INT_31TO0_8814B BIT(4)\n#define BIT_RX_DMA_STUCK_8814B BIT(3)\n#define BIT_TX_DMA_STUCK_8814B BIT(2)\n#define BIT_DDMA0_LP_INT_8814B BIT(1)\n#define BIT_DDMA0_HP_INT_8814B BIT(0)\n\n/* 2 REG_SW_MDIO_8814B */\n#define BIT_DIS_TIMEOUT_IO_8814B BIT(24)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_HIMR_7_8814B */\n#define BIT_DATA_CPU_WDT_INT_MSK_8814B BIT(31)\n#define BIT_OFLD_TXDMA_ERR_MSK_8814B BIT(30)\n#define BIT_OFLD_TXDMA_FULL_MSK_8814B BIT(29)\n#define BIT_OFLD_RXDMA_OVR_MSK_8814B BIT(28)\n#define BIT_OFLD_RXDMA_ERR_MSK_8814B BIT(27)\n#define BIT_OFLD_RXDMA_DES_UA_MSK_8814B BIT(26)\n#define BIT_TXDMAOK_CHANNEL_16_MSK_8814B BIT(16)\n#define BIT_TXDMAOK_CHANNEL_13_MSK_8814B BIT(13)\n#define BIT_TXDMAOK_CHANNEL_12_MSK_8814B BIT(12)\n#define BIT_TXDMAOK_CHANNEL_11_MSK_8814B BIT(11)\n#define BIT_TXDMAOK_CHANNEL_10_MSK_8814B BIT(10)\n#define BIT_TXDMAOK_CHANNEL_9_MSK_8814B BIT(9)\n#define BIT_TXDMAOK_CHANNEL_8_MSK_8814B BIT(8)\n#define BIT_TXDMAOK_CHANNEL_7_MSK_8814B BIT(7)\n#define BIT_TXDMAOK_CHANNEL_6_MSK_8814B BIT(6)\n#define BIT_TXDMAOK_CHANNEL_5_MSK_8814B BIT(5)\n#define BIT_TXDMAOK_CHANNEL_4_MSK_8814B BIT(4)\n\n/* 2 REG_HISR_7_8814B */\n#define BIT_DATA_CPU_WDT_INT_8814B BIT(31)\n#define BIT_OFLD_TXDMA_ERR_8814B BIT(30)\n#define BIT_OFLD_TXDMA_FULL_8814B BIT(29)\n#define BIT_OFLD_RXDMA_OVR_8814B BIT(28)\n#define BIT_OFLD_RXDMA_ERR_8814B BIT(27)\n#define BIT_OFLD_RXDMA_DES_UA_8814B BIT(26)\n#define BIT_TXDMAOK_CHANNEL_16_8814B BIT(16)\n#define BIT_TXDMAOK_CHANNEL_13_8814B BIT(13)\n#define BIT_TXDMAOK_CHANNEL_12_8814B BIT(12)\n#define BIT_TXDMAOK_CHANNEL_11_8814B BIT(11)\n#define BIT_TXDMAOK_CHANNEL_10_8814B BIT(10)\n#define BIT_TXDMAOK_CHANNEL_9_8814B BIT(9)\n#define BIT_TXDMAOK_CHANNEL_8_8814B BIT(8)\n#define BIT_TXDMAOK_CHANNEL_7_8814B BIT(7)\n#define BIT_TXDMAOK_CHANNEL_6_8814B BIT(6)\n#define BIT_TXDMAOK_CHANNEL_5_8814B BIT(5)\n#define BIT_TXDMAOK_CHANNEL_4_8814B BIT(4)\n\n/* 2 REG_H2C_PKT_READADDR_8814B */\n\n#define BIT_SHIFT_H2C_PKT_READADDR_8814B 0\n#define BIT_MASK_H2C_PKT_READADDR_8814B 0x3ffff\n#define BIT_H2C_PKT_READADDR_8814B(x)                                          \\\n\t(((x) & BIT_MASK_H2C_PKT_READADDR_8814B)                               \\\n\t << BIT_SHIFT_H2C_PKT_READADDR_8814B)\n#define BITS_H2C_PKT_READADDR_8814B                                            \\\n\t(BIT_MASK_H2C_PKT_READADDR_8814B << BIT_SHIFT_H2C_PKT_READADDR_8814B)\n#define BIT_CLEAR_H2C_PKT_READADDR_8814B(x)                                    \\\n\t((x) & (~BITS_H2C_PKT_READADDR_8814B))\n#define BIT_GET_H2C_PKT_READADDR_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_H2C_PKT_READADDR_8814B) &                           \\\n\t BIT_MASK_H2C_PKT_READADDR_8814B)\n#define BIT_SET_H2C_PKT_READADDR_8814B(x, v)                                   \\\n\t(BIT_CLEAR_H2C_PKT_READADDR_8814B(x) | BIT_H2C_PKT_READADDR_8814B(v))\n\n/* 2 REG_H2C_PKT_WRITEADDR_8814B */\n\n#define BIT_SHIFT_H2C_PKT_WRITEADDR_8814B 0\n#define BIT_MASK_H2C_PKT_WRITEADDR_8814B 0x3ffff\n#define BIT_H2C_PKT_WRITEADDR_8814B(x)                                         \\\n\t(((x) & BIT_MASK_H2C_PKT_WRITEADDR_8814B)                              \\\n\t << BIT_SHIFT_H2C_PKT_WRITEADDR_8814B)\n#define BITS_H2C_PKT_WRITEADDR_8814B                                           \\\n\t(BIT_MASK_H2C_PKT_WRITEADDR_8814B << BIT_SHIFT_H2C_PKT_WRITEADDR_8814B)\n#define BIT_CLEAR_H2C_PKT_WRITEADDR_8814B(x)                                   \\\n\t((x) & (~BITS_H2C_PKT_WRITEADDR_8814B))\n#define BIT_GET_H2C_PKT_WRITEADDR_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8814B) &                          \\\n\t BIT_MASK_H2C_PKT_WRITEADDR_8814B)\n#define BIT_SET_H2C_PKT_WRITEADDR_8814B(x, v)                                  \\\n\t(BIT_CLEAR_H2C_PKT_WRITEADDR_8814B(x) | BIT_H2C_PKT_WRITEADDR_8814B(v))\n\n/* 2 REG_MEM_PWR_CRTL_8814B */\n#define BIT_MEM_BB_SD_8814B BIT(17)\n#define BIT_MEM_BB_DS_8814B BIT(16)\n#define BIT_MEM_DENG_LS_8814B BIT(13)\n#define BIT_MEM_DENG_DS_8814B BIT(12)\n#define BIT_MEM_BT_DS_8814B BIT(10)\n#define BIT_MEM_SDIO_LS_8814B BIT(9)\n#define BIT_MEM_SDIO_DS_8814B BIT(8)\n#define BIT_MEM_USB_LS_8814B BIT(7)\n#define BIT_MEM_USB_DS_8814B BIT(6)\n#define BIT_MEM_PCI_LS_8814B BIT(5)\n#define BIT_MEM_PCI_DS_8814B BIT(4)\n#define BIT_MEM_WLMAC_LS_8814B BIT(3)\n#define BIT_MEM_WLMAC_DS_8814B BIT(2)\n#define BIT_MEM_WLMCU_LS_8814B BIT(1)\n#define BIT_MEM_WLMCU_DS_8814B BIT(0)\n\n/* 2 REG_FW_DRV_HANDSHAKE_8814B */\n\n#define BIT_SHIFT_FW_DRV_HANDSHAKE_8814B 0\n#define BIT_MASK_FW_DRV_HANDSHAKE_8814B 0xffffffffL\n#define BIT_FW_DRV_HANDSHAKE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_FW_DRV_HANDSHAKE_8814B)                               \\\n\t << BIT_SHIFT_FW_DRV_HANDSHAKE_8814B)\n#define BITS_FW_DRV_HANDSHAKE_8814B                                            \\\n\t(BIT_MASK_FW_DRV_HANDSHAKE_8814B << BIT_SHIFT_FW_DRV_HANDSHAKE_8814B)\n#define BIT_CLEAR_FW_DRV_HANDSHAKE_8814B(x)                                    \\\n\t((x) & (~BITS_FW_DRV_HANDSHAKE_8814B))\n#define BIT_GET_FW_DRV_HANDSHAKE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_FW_DRV_HANDSHAKE_8814B) &                           \\\n\t BIT_MASK_FW_DRV_HANDSHAKE_8814B)\n#define BIT_SET_FW_DRV_HANDSHAKE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_FW_DRV_HANDSHAKE_8814B(x) | BIT_FW_DRV_HANDSHAKE_8814B(v))\n\n/* 2 REG_FW_DBG0_8814B */\n\n#define BIT_SHIFT_FW_DBG0_8814B 0\n#define BIT_MASK_FW_DBG0_8814B 0xffffffffL\n#define BIT_FW_DBG0_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG0_8814B) << BIT_SHIFT_FW_DBG0_8814B)\n#define BITS_FW_DBG0_8814B (BIT_MASK_FW_DBG0_8814B << BIT_SHIFT_FW_DBG0_8814B)\n#define BIT_CLEAR_FW_DBG0_8814B(x) ((x) & (~BITS_FW_DBG0_8814B))\n#define BIT_GET_FW_DBG0_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG0_8814B) & BIT_MASK_FW_DBG0_8814B)\n#define BIT_SET_FW_DBG0_8814B(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG0_8814B(x) | BIT_FW_DBG0_8814B(v))\n\n/* 2 REG_FW_DBG1_8814B */\n\n#define BIT_SHIFT_FW_DBG1_8814B 0\n#define BIT_MASK_FW_DBG1_8814B 0xffffffffL\n#define BIT_FW_DBG1_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG1_8814B) << BIT_SHIFT_FW_DBG1_8814B)\n#define BITS_FW_DBG1_8814B (BIT_MASK_FW_DBG1_8814B << BIT_SHIFT_FW_DBG1_8814B)\n#define BIT_CLEAR_FW_DBG1_8814B(x) ((x) & (~BITS_FW_DBG1_8814B))\n#define BIT_GET_FW_DBG1_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG1_8814B) & BIT_MASK_FW_DBG1_8814B)\n#define BIT_SET_FW_DBG1_8814B(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG1_8814B(x) | BIT_FW_DBG1_8814B(v))\n\n/* 2 REG_FW_DBG2_8814B */\n\n#define BIT_SHIFT_FW_DBG2_8814B 0\n#define BIT_MASK_FW_DBG2_8814B 0xffffffffL\n#define BIT_FW_DBG2_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG2_8814B) << BIT_SHIFT_FW_DBG2_8814B)\n#define BITS_FW_DBG2_8814B (BIT_MASK_FW_DBG2_8814B << BIT_SHIFT_FW_DBG2_8814B)\n#define BIT_CLEAR_FW_DBG2_8814B(x) ((x) & (~BITS_FW_DBG2_8814B))\n#define BIT_GET_FW_DBG2_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG2_8814B) & BIT_MASK_FW_DBG2_8814B)\n#define BIT_SET_FW_DBG2_8814B(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG2_8814B(x) | BIT_FW_DBG2_8814B(v))\n\n/* 2 REG_FW_DBG3_8814B */\n\n#define BIT_SHIFT_FW_DBG3_8814B 0\n#define BIT_MASK_FW_DBG3_8814B 0xffffffffL\n#define BIT_FW_DBG3_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG3_8814B) << BIT_SHIFT_FW_DBG3_8814B)\n#define BITS_FW_DBG3_8814B (BIT_MASK_FW_DBG3_8814B << BIT_SHIFT_FW_DBG3_8814B)\n#define BIT_CLEAR_FW_DBG3_8814B(x) ((x) & (~BITS_FW_DBG3_8814B))\n#define BIT_GET_FW_DBG3_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG3_8814B) & BIT_MASK_FW_DBG3_8814B)\n#define BIT_SET_FW_DBG3_8814B(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG3_8814B(x) | BIT_FW_DBG3_8814B(v))\n\n/* 2 REG_FW_DBG4_8814B */\n\n#define BIT_SHIFT_FW_DBG4_8814B 0\n#define BIT_MASK_FW_DBG4_8814B 0xffffffffL\n#define BIT_FW_DBG4_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG4_8814B) << BIT_SHIFT_FW_DBG4_8814B)\n#define BITS_FW_DBG4_8814B (BIT_MASK_FW_DBG4_8814B << BIT_SHIFT_FW_DBG4_8814B)\n#define BIT_CLEAR_FW_DBG4_8814B(x) ((x) & (~BITS_FW_DBG4_8814B))\n#define BIT_GET_FW_DBG4_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG4_8814B) & BIT_MASK_FW_DBG4_8814B)\n#define BIT_SET_FW_DBG4_8814B(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG4_8814B(x) | BIT_FW_DBG4_8814B(v))\n\n/* 2 REG_FW_DBG5_8814B */\n\n#define BIT_SHIFT_FW_DBG5_8814B 0\n#define BIT_MASK_FW_DBG5_8814B 0xffffffffL\n#define BIT_FW_DBG5_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG5_8814B) << BIT_SHIFT_FW_DBG5_8814B)\n#define BITS_FW_DBG5_8814B (BIT_MASK_FW_DBG5_8814B << BIT_SHIFT_FW_DBG5_8814B)\n#define BIT_CLEAR_FW_DBG5_8814B(x) ((x) & (~BITS_FW_DBG5_8814B))\n#define BIT_GET_FW_DBG5_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG5_8814B) & BIT_MASK_FW_DBG5_8814B)\n#define BIT_SET_FW_DBG5_8814B(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG5_8814B(x) | BIT_FW_DBG5_8814B(v))\n\n/* 2 REG_FW_DBG6_8814B */\n\n#define BIT_SHIFT_FW_DBG6_8814B 0\n#define BIT_MASK_FW_DBG6_8814B 0xffffffffL\n#define BIT_FW_DBG6_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG6_8814B) << BIT_SHIFT_FW_DBG6_8814B)\n#define BITS_FW_DBG6_8814B (BIT_MASK_FW_DBG6_8814B << BIT_SHIFT_FW_DBG6_8814B)\n#define BIT_CLEAR_FW_DBG6_8814B(x) ((x) & (~BITS_FW_DBG6_8814B))\n#define BIT_GET_FW_DBG6_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG6_8814B) & BIT_MASK_FW_DBG6_8814B)\n#define BIT_SET_FW_DBG6_8814B(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG6_8814B(x) | BIT_FW_DBG6_8814B(v))\n\n/* 2 REG_FW_DBG7_8814B */\n\n#define BIT_SHIFT_FW_DBG7_8814B 0\n#define BIT_MASK_FW_DBG7_8814B 0xffffffffL\n#define BIT_FW_DBG7_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG7_8814B) << BIT_SHIFT_FW_DBG7_8814B)\n#define BITS_FW_DBG7_8814B (BIT_MASK_FW_DBG7_8814B << BIT_SHIFT_FW_DBG7_8814B)\n#define BIT_CLEAR_FW_DBG7_8814B(x) ((x) & (~BITS_FW_DBG7_8814B))\n#define BIT_GET_FW_DBG7_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG7_8814B) & BIT_MASK_FW_DBG7_8814B)\n#define BIT_SET_FW_DBG7_8814B(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG7_8814B(x) | BIT_FW_DBG7_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_CR_8814B */\n\n#define BIT_SHIFT_LBMODE_8814B 24\n#define BIT_MASK_LBMODE_8814B 0x1f\n#define BIT_LBMODE_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_LBMODE_8814B) << BIT_SHIFT_LBMODE_8814B)\n#define BITS_LBMODE_8814B (BIT_MASK_LBMODE_8814B << BIT_SHIFT_LBMODE_8814B)\n#define BIT_CLEAR_LBMODE_8814B(x) ((x) & (~BITS_LBMODE_8814B))\n#define BIT_GET_LBMODE_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_LBMODE_8814B) & BIT_MASK_LBMODE_8814B)\n#define BIT_SET_LBMODE_8814B(x, v)                                             \\\n\t(BIT_CLEAR_LBMODE_8814B(x) | BIT_LBMODE_8814B(v))\n\n#define BIT_SHIFT_NETYPE1_8814B 18\n#define BIT_MASK_NETYPE1_8814B 0x3\n#define BIT_NETYPE1_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE1_8814B) << BIT_SHIFT_NETYPE1_8814B)\n#define BITS_NETYPE1_8814B (BIT_MASK_NETYPE1_8814B << BIT_SHIFT_NETYPE1_8814B)\n#define BIT_CLEAR_NETYPE1_8814B(x) ((x) & (~BITS_NETYPE1_8814B))\n#define BIT_GET_NETYPE1_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE1_8814B) & BIT_MASK_NETYPE1_8814B)\n#define BIT_SET_NETYPE1_8814B(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE1_8814B(x) | BIT_NETYPE1_8814B(v))\n\n#define BIT_SHIFT_NETYPE0_8814B 16\n#define BIT_MASK_NETYPE0_8814B 0x3\n#define BIT_NETYPE0_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE0_8814B) << BIT_SHIFT_NETYPE0_8814B)\n#define BITS_NETYPE0_8814B (BIT_MASK_NETYPE0_8814B << BIT_SHIFT_NETYPE0_8814B)\n#define BIT_CLEAR_NETYPE0_8814B(x) ((x) & (~BITS_NETYPE0_8814B))\n#define BIT_GET_NETYPE0_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE0_8814B) & BIT_MASK_NETYPE0_8814B)\n#define BIT_SET_NETYPE0_8814B(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE0_8814B(x) | BIT_NETYPE0_8814B(v))\n\n#define BIT_COUNTER_STS_EN_8814B BIT(13)\n#define BIT_I2C_MAILBOX_EN_8814B BIT(12)\n#define BIT_SHCUT_EN_8814B BIT(11)\n#define BIT_32K_CAL_TMR_EN_8814B BIT(10)\n#define BIT_MAC_SEC_EN_8814B BIT(9)\n#define BIT_ENSWBCN_8814B BIT(8)\n#define BIT_MACRXEN_8814B BIT(7)\n#define BIT_MACTXEN_8814B BIT(6)\n#define BIT_SCHEDULE_EN_8814B BIT(5)\n#define BIT_PROTOCOL_EN_8814B BIT(4)\n#define BIT_RXDMA_EN_8814B BIT(3)\n#define BIT_TXDMA_EN_8814B BIT(2)\n#define BIT_HCI_RXDMA_EN_8814B BIT(1)\n#define BIT_HCI_TXDMA_EN_8814B BIT(0)\n\n/* 2 REG_PG_SIZE_8814B */\n\n#define BIT_SHIFT_DBG_FIFO_SEL_8814B 16\n#define BIT_MASK_DBG_FIFO_SEL_8814B 0xff\n#define BIT_DBG_FIFO_SEL_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DBG_FIFO_SEL_8814B) << BIT_SHIFT_DBG_FIFO_SEL_8814B)\n#define BITS_DBG_FIFO_SEL_8814B                                                \\\n\t(BIT_MASK_DBG_FIFO_SEL_8814B << BIT_SHIFT_DBG_FIFO_SEL_8814B)\n#define BIT_CLEAR_DBG_FIFO_SEL_8814B(x) ((x) & (~BITS_DBG_FIFO_SEL_8814B))\n#define BIT_GET_DBG_FIFO_SEL_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DBG_FIFO_SEL_8814B) & BIT_MASK_DBG_FIFO_SEL_8814B)\n#define BIT_SET_DBG_FIFO_SEL_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DBG_FIFO_SEL_8814B(x) | BIT_DBG_FIFO_SEL_8814B(v))\n\n/* 2 REG_PKT_BUFF_ACCESS_CTRL_8814B */\n\n#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B 0\n#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B 0xff\n#define BIT_PKT_BUFF_ACCESS_CTRL_8814B(x)                                      \\\n\t(((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B)                           \\\n\t << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B)\n#define BITS_PKT_BUFF_ACCESS_CTRL_8814B                                        \\\n\t(BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B                                   \\\n\t << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B)\n#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8814B(x)                                \\\n\t((x) & (~BITS_PKT_BUFF_ACCESS_CTRL_8814B))\n#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B) &                       \\\n\t BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B)\n#define BIT_SET_PKT_BUFF_ACCESS_CTRL_8814B(x, v)                               \\\n\t(BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8814B(x) |                             \\\n\t BIT_PKT_BUFF_ACCESS_CTRL_8814B(v))\n\n/* 2 REG_TSF_CLK_STATE_8814B */\n#define BIT_TSF_CLK_STABLE_8814B BIT(15)\n\n/* 2 REG_TXDMA_PQ_MAP_8814B */\n\n#define BIT_SHIFT_TXDMA_H2C_MAP_8814B 16\n#define BIT_MASK_TXDMA_H2C_MAP_8814B 0x3\n#define BIT_TXDMA_H2C_MAP_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_H2C_MAP_8814B) << BIT_SHIFT_TXDMA_H2C_MAP_8814B)\n#define BITS_TXDMA_H2C_MAP_8814B                                               \\\n\t(BIT_MASK_TXDMA_H2C_MAP_8814B << BIT_SHIFT_TXDMA_H2C_MAP_8814B)\n#define BIT_CLEAR_TXDMA_H2C_MAP_8814B(x) ((x) & (~BITS_TXDMA_H2C_MAP_8814B))\n#define BIT_GET_TXDMA_H2C_MAP_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_H2C_MAP_8814B) & BIT_MASK_TXDMA_H2C_MAP_8814B)\n#define BIT_SET_TXDMA_H2C_MAP_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_H2C_MAP_8814B(x) | BIT_TXDMA_H2C_MAP_8814B(v))\n\n#define BIT_SHIFT_TXDMA_HIQ_MAP_8814B 14\n#define BIT_MASK_TXDMA_HIQ_MAP_8814B 0x3\n#define BIT_TXDMA_HIQ_MAP_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_HIQ_MAP_8814B) << BIT_SHIFT_TXDMA_HIQ_MAP_8814B)\n#define BITS_TXDMA_HIQ_MAP_8814B                                               \\\n\t(BIT_MASK_TXDMA_HIQ_MAP_8814B << BIT_SHIFT_TXDMA_HIQ_MAP_8814B)\n#define BIT_CLEAR_TXDMA_HIQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8814B))\n#define BIT_GET_TXDMA_HIQ_MAP_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8814B) & BIT_MASK_TXDMA_HIQ_MAP_8814B)\n#define BIT_SET_TXDMA_HIQ_MAP_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_HIQ_MAP_8814B(x) | BIT_TXDMA_HIQ_MAP_8814B(v))\n\n#define BIT_SHIFT_TXDMA_MGQ_MAP_8814B 12\n#define BIT_MASK_TXDMA_MGQ_MAP_8814B 0x3\n#define BIT_TXDMA_MGQ_MAP_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_MGQ_MAP_8814B) << BIT_SHIFT_TXDMA_MGQ_MAP_8814B)\n#define BITS_TXDMA_MGQ_MAP_8814B                                               \\\n\t(BIT_MASK_TXDMA_MGQ_MAP_8814B << BIT_SHIFT_TXDMA_MGQ_MAP_8814B)\n#define BIT_CLEAR_TXDMA_MGQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8814B))\n#define BIT_GET_TXDMA_MGQ_MAP_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8814B) & BIT_MASK_TXDMA_MGQ_MAP_8814B)\n#define BIT_SET_TXDMA_MGQ_MAP_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_MGQ_MAP_8814B(x) | BIT_TXDMA_MGQ_MAP_8814B(v))\n\n#define BIT_SHIFT_TXDMA_BKQ_MAP_8814B 10\n#define BIT_MASK_TXDMA_BKQ_MAP_8814B 0x3\n#define BIT_TXDMA_BKQ_MAP_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_BKQ_MAP_8814B) << BIT_SHIFT_TXDMA_BKQ_MAP_8814B)\n#define BITS_TXDMA_BKQ_MAP_8814B                                               \\\n\t(BIT_MASK_TXDMA_BKQ_MAP_8814B << BIT_SHIFT_TXDMA_BKQ_MAP_8814B)\n#define BIT_CLEAR_TXDMA_BKQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8814B))\n#define BIT_GET_TXDMA_BKQ_MAP_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8814B) & BIT_MASK_TXDMA_BKQ_MAP_8814B)\n#define BIT_SET_TXDMA_BKQ_MAP_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_BKQ_MAP_8814B(x) | BIT_TXDMA_BKQ_MAP_8814B(v))\n\n#define BIT_SHIFT_TXDMA_BEQ_MAP_8814B 8\n#define BIT_MASK_TXDMA_BEQ_MAP_8814B 0x3\n#define BIT_TXDMA_BEQ_MAP_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_BEQ_MAP_8814B) << BIT_SHIFT_TXDMA_BEQ_MAP_8814B)\n#define BITS_TXDMA_BEQ_MAP_8814B                                               \\\n\t(BIT_MASK_TXDMA_BEQ_MAP_8814B << BIT_SHIFT_TXDMA_BEQ_MAP_8814B)\n#define BIT_CLEAR_TXDMA_BEQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8814B))\n#define BIT_GET_TXDMA_BEQ_MAP_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8814B) & BIT_MASK_TXDMA_BEQ_MAP_8814B)\n#define BIT_SET_TXDMA_BEQ_MAP_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_BEQ_MAP_8814B(x) | BIT_TXDMA_BEQ_MAP_8814B(v))\n\n#define BIT_SHIFT_TXDMA_VIQ_MAP_8814B 6\n#define BIT_MASK_TXDMA_VIQ_MAP_8814B 0x3\n#define BIT_TXDMA_VIQ_MAP_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_VIQ_MAP_8814B) << BIT_SHIFT_TXDMA_VIQ_MAP_8814B)\n#define BITS_TXDMA_VIQ_MAP_8814B                                               \\\n\t(BIT_MASK_TXDMA_VIQ_MAP_8814B << BIT_SHIFT_TXDMA_VIQ_MAP_8814B)\n#define BIT_CLEAR_TXDMA_VIQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8814B))\n#define BIT_GET_TXDMA_VIQ_MAP_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8814B) & BIT_MASK_TXDMA_VIQ_MAP_8814B)\n#define BIT_SET_TXDMA_VIQ_MAP_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_VIQ_MAP_8814B(x) | BIT_TXDMA_VIQ_MAP_8814B(v))\n\n#define BIT_SHIFT_TXDMA_VOQ_MAP_8814B 4\n#define BIT_MASK_TXDMA_VOQ_MAP_8814B 0x3\n#define BIT_TXDMA_VOQ_MAP_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_VOQ_MAP_8814B) << BIT_SHIFT_TXDMA_VOQ_MAP_8814B)\n#define BITS_TXDMA_VOQ_MAP_8814B                                               \\\n\t(BIT_MASK_TXDMA_VOQ_MAP_8814B << BIT_SHIFT_TXDMA_VOQ_MAP_8814B)\n#define BIT_CLEAR_TXDMA_VOQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8814B))\n#define BIT_GET_TXDMA_VOQ_MAP_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8814B) & BIT_MASK_TXDMA_VOQ_MAP_8814B)\n#define BIT_SET_TXDMA_VOQ_MAP_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_VOQ_MAP_8814B(x) | BIT_TXDMA_VOQ_MAP_8814B(v))\n\n#define BIT_RXDMA_AGG_EN_8814B BIT(2)\n#define BIT_RXSHFT_EN_8814B BIT(1)\n#define BIT_RXDMA_ARBBW_EN_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_TRXFF_BNDY_8814B */\n\n#define BIT_SHIFT_FWFFOVFL_RSV_8814B 16\n#define BIT_MASK_FWFFOVFL_RSV_8814B 0xf\n#define BIT_FWFFOVFL_RSV_8814B(x)                                              \\\n\t(((x) & BIT_MASK_FWFFOVFL_RSV_8814B) << BIT_SHIFT_FWFFOVFL_RSV_8814B)\n#define BITS_FWFFOVFL_RSV_8814B                                                \\\n\t(BIT_MASK_FWFFOVFL_RSV_8814B << BIT_SHIFT_FWFFOVFL_RSV_8814B)\n#define BIT_CLEAR_FWFFOVFL_RSV_8814B(x) ((x) & (~BITS_FWFFOVFL_RSV_8814B))\n#define BIT_GET_FWFFOVFL_RSV_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_FWFFOVFL_RSV_8814B) & BIT_MASK_FWFFOVFL_RSV_8814B)\n#define BIT_SET_FWFFOVFL_RSV_8814B(x, v)                                       \\\n\t(BIT_CLEAR_FWFFOVFL_RSV_8814B(x) | BIT_FWFFOVFL_RSV_8814B(v))\n\n#define BIT_SHIFT_RXFFOVFL_RSV_V2_8814B 8\n#define BIT_MASK_RXFFOVFL_RSV_V2_8814B 0xf\n#define BIT_RXFFOVFL_RSV_V2_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RXFFOVFL_RSV_V2_8814B)                                \\\n\t << BIT_SHIFT_RXFFOVFL_RSV_V2_8814B)\n#define BITS_RXFFOVFL_RSV_V2_8814B                                             \\\n\t(BIT_MASK_RXFFOVFL_RSV_V2_8814B << BIT_SHIFT_RXFFOVFL_RSV_V2_8814B)\n#define BIT_CLEAR_RXFFOVFL_RSV_V2_8814B(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8814B))\n#define BIT_GET_RXFFOVFL_RSV_V2_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8814B) &                            \\\n\t BIT_MASK_RXFFOVFL_RSV_V2_8814B)\n#define BIT_SET_RXFFOVFL_RSV_V2_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RXFFOVFL_RSV_V2_8814B(x) | BIT_RXFFOVFL_RSV_V2_8814B(v))\n\n/* 2 REG_PTA_I2C_MBOX_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_I2C_M_STATUS_8814B 8\n#define BIT_MASK_I2C_M_STATUS_8814B 0xf\n#define BIT_I2C_M_STATUS_8814B(x)                                              \\\n\t(((x) & BIT_MASK_I2C_M_STATUS_8814B) << BIT_SHIFT_I2C_M_STATUS_8814B)\n#define BITS_I2C_M_STATUS_8814B                                                \\\n\t(BIT_MASK_I2C_M_STATUS_8814B << BIT_SHIFT_I2C_M_STATUS_8814B)\n#define BIT_CLEAR_I2C_M_STATUS_8814B(x) ((x) & (~BITS_I2C_M_STATUS_8814B))\n#define BIT_GET_I2C_M_STATUS_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_I2C_M_STATUS_8814B) & BIT_MASK_I2C_M_STATUS_8814B)\n#define BIT_SET_I2C_M_STATUS_8814B(x, v)                                       \\\n\t(BIT_CLEAR_I2C_M_STATUS_8814B(x) | BIT_I2C_M_STATUS_8814B(v))\n\n#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B 4\n#define BIT_MASK_I2C_M_BUS_GNT_FW_8814B 0x7\n#define BIT_I2C_M_BUS_GNT_FW_8814B(x)                                          \\\n\t(((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8814B)                               \\\n\t << BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B)\n#define BITS_I2C_M_BUS_GNT_FW_8814B                                            \\\n\t(BIT_MASK_I2C_M_BUS_GNT_FW_8814B << BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B)\n#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8814B(x)                                    \\\n\t((x) & (~BITS_I2C_M_BUS_GNT_FW_8814B))\n#define BIT_GET_I2C_M_BUS_GNT_FW_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B) &                           \\\n\t BIT_MASK_I2C_M_BUS_GNT_FW_8814B)\n#define BIT_SET_I2C_M_BUS_GNT_FW_8814B(x, v)                                   \\\n\t(BIT_CLEAR_I2C_M_BUS_GNT_FW_8814B(x) | BIT_I2C_M_BUS_GNT_FW_8814B(v))\n\n#define BIT_I2C_M_GNT_FW_8814B BIT(3)\n\n#define BIT_SHIFT_I2C_M_SPEED_8814B 1\n#define BIT_MASK_I2C_M_SPEED_8814B 0x3\n#define BIT_I2C_M_SPEED_8814B(x)                                               \\\n\t(((x) & BIT_MASK_I2C_M_SPEED_8814B) << BIT_SHIFT_I2C_M_SPEED_8814B)\n#define BITS_I2C_M_SPEED_8814B                                                 \\\n\t(BIT_MASK_I2C_M_SPEED_8814B << BIT_SHIFT_I2C_M_SPEED_8814B)\n#define BIT_CLEAR_I2C_M_SPEED_8814B(x) ((x) & (~BITS_I2C_M_SPEED_8814B))\n#define BIT_GET_I2C_M_SPEED_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_I2C_M_SPEED_8814B) & BIT_MASK_I2C_M_SPEED_8814B)\n#define BIT_SET_I2C_M_SPEED_8814B(x, v)                                        \\\n\t(BIT_CLEAR_I2C_M_SPEED_8814B(x) | BIT_I2C_M_SPEED_8814B(v))\n\n#define BIT_I2C_M_UNLOCK_8814B BIT(0)\n\n/* 2 REG_RXFF_BNDY_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_RXFF0_BNDY_V2_8814B 0\n#define BIT_MASK_RXFF0_BNDY_V2_8814B 0x3ffff\n#define BIT_RXFF0_BNDY_V2_8814B(x)                                             \\\n\t(((x) & BIT_MASK_RXFF0_BNDY_V2_8814B) << BIT_SHIFT_RXFF0_BNDY_V2_8814B)\n#define BITS_RXFF0_BNDY_V2_8814B                                               \\\n\t(BIT_MASK_RXFF0_BNDY_V2_8814B << BIT_SHIFT_RXFF0_BNDY_V2_8814B)\n#define BIT_CLEAR_RXFF0_BNDY_V2_8814B(x) ((x) & (~BITS_RXFF0_BNDY_V2_8814B))\n#define BIT_GET_RXFF0_BNDY_V2_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8814B) & BIT_MASK_RXFF0_BNDY_V2_8814B)\n#define BIT_SET_RXFF0_BNDY_V2_8814B(x, v)                                      \\\n\t(BIT_CLEAR_RXFF0_BNDY_V2_8814B(x) | BIT_RXFF0_BNDY_V2_8814B(v))\n\n/* 2 REG_FE1IMR_8814B */\n#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT_EN_8814B BIT(31)\n#define BIT_FWFF_FULL_INT_EN_8814B BIT(30)\n#define BIT_BB_STOP_RX_INT_EN_8814B BIT(29)\n#define BIT_FS_RXDMA2_DONE_INT_EN_8814B BIT(28)\n#define BIT_FS_RXDONE3_INT_EN_8814B BIT(27)\n#define BIT_FS_RXDONE2_INT_EN_8814B BIT(26)\n#define BIT_FS_RX_BCN_P4_INT_EN_8814B BIT(25)\n#define BIT_FS_RX_BCN_P3_INT_EN_8814B BIT(24)\n#define BIT_FS_RX_BCN_P2_INT_EN_8814B BIT(23)\n#define BIT_FS_RX_BCN_P1_INT_EN_8814B BIT(22)\n#define BIT_FS_RX_BCN_P0_INT_EN_8814B BIT(21)\n#define BIT_FS_RX_UMD0_INT_EN_8814B BIT(20)\n#define BIT_FS_RX_UMD1_INT_EN_8814B BIT(19)\n#define BIT_FS_RX_BMD0_INT_EN_8814B BIT(18)\n#define BIT_FS_RX_BMD1_INT_EN_8814B BIT(17)\n#define BIT_FS_RXDONE_INT_EN_8814B BIT(16)\n#define BIT_FS_WWLAN_INT_EN_8814B BIT(15)\n#define BIT_FS_SOUND_DONE_INT_EN_8814B BIT(14)\n#define BIT_FS_TRL_MTR_INT_EN_8814B BIT(12)\n#define BIT_FS_BF1_PRETO_INT_EN_8814B BIT(11)\n#define BIT_FS_BF0_PRETO_INT_EN_8814B BIT(10)\n#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8814B BIT(9)\n#define BIT_PRETX_ERRHLD_INT_EN_8814B BIT(8)\n#define BIT_FS_GTRD_INT_EN_8814B BIT(7)\n#define BIT_FS_LTE_COEX_EN_8814B BIT(6)\n#define BIT_FS_WLACTOFF_INT_EN_8814B BIT(5)\n#define BIT_FS_WLACTON_INT_EN_8814B BIT(4)\n#define BIT_FS_BTCMD_INT_EN_8814B BIT(3)\n#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8814B BIT(2)\n#define BIT_FS_TRPC_TO_INT_EN_V1_8814B BIT(1)\n#define BIT_FS_RPC_O_T_INT_EN_V1_8814B BIT(0)\n\n/* 2 REG_FE1ISR_8814B */\n#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT_8814B BIT(31)\n#define BIT_FWFF_FULL_INT_8814B BIT(30)\n#define BIT_BB_STOP_RX_INT_8814B BIT(29)\n#define BIT_FS_RXDMA2_DONE_INT_8814B BIT(28)\n#define BIT_FS_RXDONE3_INT_INT_8814B BIT(27)\n#define BIT_FS_RXDONE2_INT_8814B BIT(26)\n#define BIT_FS_RX_BCN_P4_INT_8814B BIT(25)\n#define BIT_FS_RX_BCN_P3_INT_8814B BIT(24)\n#define BIT_FS_RX_BCN_P2_INT_8814B BIT(23)\n#define BIT_FS_RX_BCN_P1_INT_8814B BIT(22)\n#define BIT_FS_RX_BCN_P0_INT_8814B BIT(21)\n#define BIT_FS_RX_UMD0_INT_8814B BIT(20)\n#define BIT_FS_RX_UMD1_INT_8814B BIT(19)\n#define BIT_FS_RX_BMD0_INT_8814B BIT(18)\n#define BIT_FS_RX_BMD1_INT_8814B BIT(17)\n#define BIT_FS_RXDONE_INT_8814B BIT(16)\n#define BIT_FS_WWLAN_INT_8814B BIT(15)\n#define BIT_FS_SOUND_DONE_INT_8814B BIT(14)\n#define BIT_FS_TRL_MTR_INT_8814B BIT(12)\n#define BIT_FS_BF1_PRETO_INT_8814B BIT(11)\n#define BIT_FS_BF0_PRETO_INT_8814B BIT(10)\n#define BIT_FS_PTCL_RELEASE_MACID_INT_8814B BIT(9)\n#define BIT_PRETX_ERRHLD_INT_8814B BIT(8)\n#define BIT_SND_RDY_INT_8814B BIT(7)\n#define BIT_FS_LTE_COEX_INT_8814B BIT(6)\n#define BIT_FS_WLACTOFF_INT_8814B BIT(5)\n#define BIT_FS_WLACTON_INT_8814B BIT(4)\n#define BIT_BT_CMD_INT_8814B BIT(3)\n#define BIT_FS_MAILBOX_TO_I2C_INT_8814B BIT(2)\n#define BIT_FS_TRPC_TO_INT_8814B BIT(1)\n#define BIT_FS_RPC_O_T_INT_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_CPWM_8814B */\n#define BIT_CPWM_TOGGLING_8814B BIT(31)\n\n#define BIT_SHIFT_CPWM_MOD_8814B 24\n#define BIT_MASK_CPWM_MOD_8814B 0x7f\n#define BIT_CPWM_MOD_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_CPWM_MOD_8814B) << BIT_SHIFT_CPWM_MOD_8814B)\n#define BITS_CPWM_MOD_8814B                                                    \\\n\t(BIT_MASK_CPWM_MOD_8814B << BIT_SHIFT_CPWM_MOD_8814B)\n#define BIT_CLEAR_CPWM_MOD_8814B(x) ((x) & (~BITS_CPWM_MOD_8814B))\n#define BIT_GET_CPWM_MOD_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_CPWM_MOD_8814B) & BIT_MASK_CPWM_MOD_8814B)\n#define BIT_SET_CPWM_MOD_8814B(x, v)                                           \\\n\t(BIT_CLEAR_CPWM_MOD_8814B(x) | BIT_CPWM_MOD_8814B(v))\n\n/* 2 REG_FWIMR_8814B */\n#define BIT_FS_TXBCNOK_MB7_INT_EN_8814B BIT(31)\n#define BIT_FS_TXBCNOK_MB6_INT_EN_8814B BIT(30)\n#define BIT_FS_TXBCNOK_MB5_INT_EN_8814B BIT(29)\n#define BIT_FS_TXBCNOK_MB4_INT_EN_8814B BIT(28)\n#define BIT_FS_TXBCNOK_MB3_INT_EN_8814B BIT(27)\n#define BIT_FS_TXBCNOK_MB2_INT_EN_8814B BIT(26)\n#define BIT_FS_TXBCNOK_MB1_INT_EN_8814B BIT(25)\n#define BIT_FS_TXBCNOK_MB0_INT_EN_8814B BIT(24)\n#define BIT_FS_TXBCNERR_MB7_INT_EN_8814B BIT(23)\n#define BIT_FS_TXBCNERR_MB6_INT_EN_8814B BIT(22)\n#define BIT_FS_TXBCNERR_MB5_INT_EN_8814B BIT(21)\n#define BIT_FS_TXBCNERR_MB4_INT_EN_8814B BIT(20)\n#define BIT_FS_TXBCNERR_MB3_INT_EN_8814B BIT(19)\n#define BIT_FS_TXBCNERR_MB2_INT_EN_8814B BIT(18)\n#define BIT_FS_TXBCNERR_MB1_INT_EN_8814B BIT(17)\n#define BIT_FS_TXBCNERR_MB0_INT_EN_8814B BIT(16)\n#define BIT_CPU_MGQ_TXDONE_INT_EN_8814B BIT(15)\n#define BIT_SIFS_OVERSPEC_INT_EN_8814B BIT(14)\n#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8814B BIT(13)\n#define BIT_FS_MGNTQFF_TO_INT_EN_8814B BIT(12)\n#define BIT_FS_CPUMGQ_ERR_INT_EN_8814B BIT(11)\n#define BIT_FS_DDMA0_LP_INT_EN_8814B BIT(9)\n#define BIT_FS_DDMA0_HP_INT_EN_8814B BIT(8)\n#define BIT_FS_TRXRPT_INT_EN_8814B BIT(7)\n#define BIT_FS_C2H_W_READY_INT_EN_8814B BIT(6)\n#define BIT_FS_HRCV_INT_EN_8814B BIT(5)\n#define BIT_FS_H2CCMD_INT_EN_8814B BIT(4)\n#define BIT_FS_TXPKTIN_INT_EN_8814B BIT(3)\n#define BIT_FS_ERRORHDL_INT_EN_8814B BIT(2)\n#define BIT_FS_TXCCX_INT_EN_8814B BIT(1)\n#define BIT_FS_TXCLOSE_INT_EN_8814B BIT(0)\n\n/* 2 REG_FWISR_8814B */\n#define BIT_FS_TXBCNOK_MB7_INT_8814B BIT(31)\n#define BIT_FS_TXBCNOK_MB6_INT_8814B BIT(30)\n#define BIT_FS_TXBCNOK_MB5_INT_8814B BIT(29)\n#define BIT_FS_TXBCNOK_MB4_INT_8814B BIT(28)\n#define BIT_FS_TXBCNOK_MB3_INT_8814B BIT(27)\n#define BIT_FS_TXBCNOK_MB2_INT_8814B BIT(26)\n#define BIT_FS_TXBCNOK_MB1_INT_8814B BIT(25)\n#define BIT_FS_TXBCNOK_MB0_INT_8814B BIT(24)\n#define BIT_FS_TXBCNERR_MB7_INT_8814B BIT(23)\n#define BIT_FS_TXBCNERR_MB6_INT_8814B BIT(22)\n#define BIT_FS_TXBCNERR_MB5_INT_8814B BIT(21)\n#define BIT_FS_TXBCNERR_MB4_INT_8814B BIT(20)\n#define BIT_FS_TXBCNERR_MB3_INT_8814B BIT(19)\n#define BIT_FS_TXBCNERR_MB2_INT_8814B BIT(18)\n#define BIT_FS_TXBCNERR_MB1_INT_8814B BIT(17)\n#define BIT_FS_TXBCNERR_MB0_INT_8814B BIT(16)\n#define BIT_CPU_MGQ_TXDONE_INT_8814B BIT(15)\n#define BIT_SIFS_OVERSPEC_INT_8814B BIT(14)\n#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8814B BIT(13)\n#define BIT_FS_MGNTQFF_TO_INT_8814B BIT(12)\n#define BIT_FS_CPUMGQ_ERR_INT_8814B BIT(11)\n#define BIT_FWCMD_PKTIN_INT_8814B BIT(10)\n#define BIT_FS_DDMA0_LP_INT_8814B BIT(9)\n#define BIT_FS_DDMA0_HP_INT_8814B BIT(8)\n#define BIT_FS_TRXRPT_INT_8814B BIT(7)\n#define BIT_FS_C2H_W_READY_INT_8814B BIT(6)\n#define BIT_FS_HRCV_INT_8814B BIT(5)\n#define BIT_FS_H2CCMD_INT_8814B BIT(4)\n#define BIT_FS_TXPKTIN_INT_8814B BIT(3)\n#define BIT_FS_ERRORHDL_INT_8814B BIT(2)\n#define BIT_FS_TXCCX_INT_8814B BIT(1)\n#define BIT_FS_TXCLOSE_INT_8814B BIT(0)\n\n/* 2 REG_FTIMR_8814B */\n#define BIT_PS_TIMER_C_EARLY_INT_EN_8814B BIT(23)\n#define BIT_PS_TIMER_B_EARLY_INT_EN_8814B BIT(22)\n#define BIT_PS_TIMER_A_EARLY_INT_EN_8814B BIT(21)\n#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8814B BIT(20)\n#define BIT_PS_TIMER_C_INT_EN_8814B BIT(19)\n#define BIT_PS_TIMER_B_INT_EN_8814B BIT(18)\n#define BIT_PS_TIMER_A_INT_EN_8814B BIT(17)\n#define BIT_CPUMGQ_TX_TIMER_INT_EN_8814B BIT(16)\n#define BIT_FS_PS_TIMEOUT2_EN_8814B BIT(15)\n#define BIT_FS_PS_TIMEOUT1_EN_8814B BIT(14)\n#define BIT_FS_PS_TIMEOUT0_EN_8814B BIT(13)\n#define BIT_FS_GTINT12_EN_8814B BIT(12)\n#define BIT_FS_GTINT11_EN_8814B BIT(11)\n#define BIT_FS_GTINT10_EN_8814B BIT(10)\n#define BIT_FS_GTINT9_EN_8814B BIT(9)\n#define BIT_FS_GTINT8_EN_8814B BIT(8)\n#define BIT_FS_GTINT7_EN_8814B BIT(7)\n#define BIT_FS_GTINT6_EN_8814B BIT(6)\n#define BIT_FS_GTINT5_EN_8814B BIT(5)\n#define BIT_FS_GTINT4_EN_8814B BIT(4)\n#define BIT_FS_GTINT3_EN_8814B BIT(3)\n#define BIT_FS_GTINT2_EN_8814B BIT(2)\n#define BIT_FS_GTINT1_EN_8814B BIT(1)\n#define BIT_FS_GTINT0_EN_8814B BIT(0)\n\n/* 2 REG_FTISR_8814B */\n#define BIT_PS_TIMER_5_EARLY__INT_8814B BIT(26)\n#define BIT_PS_TIMER_4_EARLY__INT_8814B BIT(25)\n#define BIT_PS_TIMER_3_EARLY__INT_8814B BIT(24)\n#define BIT_PS_TIMER_2_EARLY__INT_8814B BIT(23)\n#define BIT_PS_TIMER_1_EARLY__INT_8814B BIT(22)\n#define BIT_PS_TIMER_0_EARLY__INT_8814B BIT(21)\n#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8814B BIT(20)\n#define BIT_PS_TIMER_5_INT_8814B BIT(19)\n#define BIT_PS_TIMER_4_INT_8814B BIT(18)\n#define BIT_PS_TIMER_3_INT_8814B BIT(17)\n#define BIT_CPUMGQ_TX_TIMER_INT_8814B BIT(16)\n#define BIT_PS_TIMER_2_INT_8814B BIT(15)\n#define BIT_PS_TIMER_1_INT_8814B BIT(14)\n#define BIT_PS_TIMER_0_INT_8814B BIT(13)\n#define BIT_FS_GTINT12_INT_8814B BIT(12)\n#define BIT_FS_GTINT11_INT_8814B BIT(11)\n#define BIT_FS_GTINT10_INT_8814B BIT(10)\n#define BIT_FS_GTINT9_INT_8814B BIT(9)\n#define BIT_FS_GTINT8_INT_8814B BIT(8)\n#define BIT_FS_GTINT7_INT_8814B BIT(7)\n#define BIT_FS_GTINT6_INT_8814B BIT(6)\n#define BIT_FS_GTINT5_INT_8814B BIT(5)\n#define BIT_FS_GTINT4_INT_8814B BIT(4)\n#define BIT_FS_GTINT3_INT_8814B BIT(3)\n#define BIT_FS_GTINT2_INT_8814B BIT(2)\n#define BIT_FS_GTINT1_INT_8814B BIT(1)\n#define BIT_FS_GTINT0_INT_8814B BIT(0)\n\n/* 2 REG_PKTBUF_DBG_CTRL_8814B */\n\n#define BIT_SHIFT_PKTBUF_WRITE_EN_8814B 24\n#define BIT_MASK_PKTBUF_WRITE_EN_8814B 0xff\n#define BIT_PKTBUF_WRITE_EN_8814B(x)                                           \\\n\t(((x) & BIT_MASK_PKTBUF_WRITE_EN_8814B)                                \\\n\t << BIT_SHIFT_PKTBUF_WRITE_EN_8814B)\n#define BITS_PKTBUF_WRITE_EN_8814B                                             \\\n\t(BIT_MASK_PKTBUF_WRITE_EN_8814B << BIT_SHIFT_PKTBUF_WRITE_EN_8814B)\n#define BIT_CLEAR_PKTBUF_WRITE_EN_8814B(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8814B))\n#define BIT_GET_PKTBUF_WRITE_EN_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8814B) &                            \\\n\t BIT_MASK_PKTBUF_WRITE_EN_8814B)\n#define BIT_SET_PKTBUF_WRITE_EN_8814B(x, v)                                    \\\n\t(BIT_CLEAR_PKTBUF_WRITE_EN_8814B(x) | BIT_PKTBUF_WRITE_EN_8814B(v))\n\n#define BIT_TXRPTBUF_DBG_8814B BIT(23)\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_TXPKTBUF_DBG_V2_8814B BIT(20)\n#define BIT_RXPKTBUF_DBG_8814B BIT(16)\n\n#define BIT_SHIFT_PKTBUF_DBG_ADDR_8814B 0\n#define BIT_MASK_PKTBUF_DBG_ADDR_8814B 0x1fff\n#define BIT_PKTBUF_DBG_ADDR_8814B(x)                                           \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_ADDR_8814B)                                \\\n\t << BIT_SHIFT_PKTBUF_DBG_ADDR_8814B)\n#define BITS_PKTBUF_DBG_ADDR_8814B                                             \\\n\t(BIT_MASK_PKTBUF_DBG_ADDR_8814B << BIT_SHIFT_PKTBUF_DBG_ADDR_8814B)\n#define BIT_CLEAR_PKTBUF_DBG_ADDR_8814B(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8814B))\n#define BIT_GET_PKTBUF_DBG_ADDR_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8814B) &                            \\\n\t BIT_MASK_PKTBUF_DBG_ADDR_8814B)\n#define BIT_SET_PKTBUF_DBG_ADDR_8814B(x, v)                                    \\\n\t(BIT_CLEAR_PKTBUF_DBG_ADDR_8814B(x) | BIT_PKTBUF_DBG_ADDR_8814B(v))\n\n/* 2 REG_PKTBUF_DBG_DATA_L_8814B */\n\n#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B 0\n#define BIT_MASK_PKTBUF_DBG_DATA_L_8814B 0xffffffffL\n#define BIT_PKTBUF_DBG_DATA_L_8814B(x)                                         \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8814B)                              \\\n\t << BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B)\n#define BITS_PKTBUF_DBG_DATA_L_8814B                                           \\\n\t(BIT_MASK_PKTBUF_DBG_DATA_L_8814B << BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B)\n#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8814B(x)                                   \\\n\t((x) & (~BITS_PKTBUF_DBG_DATA_L_8814B))\n#define BIT_GET_PKTBUF_DBG_DATA_L_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B) &                          \\\n\t BIT_MASK_PKTBUF_DBG_DATA_L_8814B)\n#define BIT_SET_PKTBUF_DBG_DATA_L_8814B(x, v)                                  \\\n\t(BIT_CLEAR_PKTBUF_DBG_DATA_L_8814B(x) | BIT_PKTBUF_DBG_DATA_L_8814B(v))\n\n/* 2 REG_PKTBUF_DBG_DATA_H_8814B */\n\n#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B 0\n#define BIT_MASK_PKTBUF_DBG_DATA_H_8814B 0xffffffffL\n#define BIT_PKTBUF_DBG_DATA_H_8814B(x)                                         \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8814B)                              \\\n\t << BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B)\n#define BITS_PKTBUF_DBG_DATA_H_8814B                                           \\\n\t(BIT_MASK_PKTBUF_DBG_DATA_H_8814B << BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B)\n#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8814B(x)                                   \\\n\t((x) & (~BITS_PKTBUF_DBG_DATA_H_8814B))\n#define BIT_GET_PKTBUF_DBG_DATA_H_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B) &                          \\\n\t BIT_MASK_PKTBUF_DBG_DATA_H_8814B)\n#define BIT_SET_PKTBUF_DBG_DATA_H_8814B(x, v)                                  \\\n\t(BIT_CLEAR_PKTBUF_DBG_DATA_H_8814B(x) | BIT_PKTBUF_DBG_DATA_H_8814B(v))\n\n/* 2 REG_CPWM2_8814B */\n\n#define BIT_SHIFT_L0S_TO_RCVY_NUM_8814B 16\n#define BIT_MASK_L0S_TO_RCVY_NUM_8814B 0xff\n#define BIT_L0S_TO_RCVY_NUM_8814B(x)                                           \\\n\t(((x) & BIT_MASK_L0S_TO_RCVY_NUM_8814B)                                \\\n\t << BIT_SHIFT_L0S_TO_RCVY_NUM_8814B)\n#define BITS_L0S_TO_RCVY_NUM_8814B                                             \\\n\t(BIT_MASK_L0S_TO_RCVY_NUM_8814B << BIT_SHIFT_L0S_TO_RCVY_NUM_8814B)\n#define BIT_CLEAR_L0S_TO_RCVY_NUM_8814B(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8814B))\n#define BIT_GET_L0S_TO_RCVY_NUM_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8814B) &                            \\\n\t BIT_MASK_L0S_TO_RCVY_NUM_8814B)\n#define BIT_SET_L0S_TO_RCVY_NUM_8814B(x, v)                                    \\\n\t(BIT_CLEAR_L0S_TO_RCVY_NUM_8814B(x) | BIT_L0S_TO_RCVY_NUM_8814B(v))\n\n#define BIT_CPWM2_TOGGLING_8814B BIT(15)\n\n#define BIT_SHIFT_CPWM2_MOD_8814B 0\n#define BIT_MASK_CPWM2_MOD_8814B 0x7fff\n#define BIT_CPWM2_MOD_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_CPWM2_MOD_8814B) << BIT_SHIFT_CPWM2_MOD_8814B)\n#define BITS_CPWM2_MOD_8814B                                                   \\\n\t(BIT_MASK_CPWM2_MOD_8814B << BIT_SHIFT_CPWM2_MOD_8814B)\n#define BIT_CLEAR_CPWM2_MOD_8814B(x) ((x) & (~BITS_CPWM2_MOD_8814B))\n#define BIT_GET_CPWM2_MOD_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_CPWM2_MOD_8814B) & BIT_MASK_CPWM2_MOD_8814B)\n#define BIT_SET_CPWM2_MOD_8814B(x, v)                                          \\\n\t(BIT_CLEAR_CPWM2_MOD_8814B(x) | BIT_CPWM2_MOD_8814B(v))\n\n/* 2 REG_TC0_CTRL_8814B */\n#define BIT_TC0INT_EN_8814B BIT(26)\n#define BIT_TC0MODE_8814B BIT(25)\n#define BIT_TC0EN_8814B BIT(24)\n\n#define BIT_SHIFT_TC0DATA_8814B 0\n#define BIT_MASK_TC0DATA_8814B 0xffffff\n#define BIT_TC0DATA_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_TC0DATA_8814B) << BIT_SHIFT_TC0DATA_8814B)\n#define BITS_TC0DATA_8814B (BIT_MASK_TC0DATA_8814B << BIT_SHIFT_TC0DATA_8814B)\n#define BIT_CLEAR_TC0DATA_8814B(x) ((x) & (~BITS_TC0DATA_8814B))\n#define BIT_GET_TC0DATA_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC0DATA_8814B) & BIT_MASK_TC0DATA_8814B)\n#define BIT_SET_TC0DATA_8814B(x, v)                                            \\\n\t(BIT_CLEAR_TC0DATA_8814B(x) | BIT_TC0DATA_8814B(v))\n\n/* 2 REG_TC1_CTRL_8814B */\n#define BIT_TC1INT_EN_8814B BIT(26)\n#define BIT_TC1MODE_8814B BIT(25)\n#define BIT_TC1EN_8814B BIT(24)\n\n#define BIT_SHIFT_TC1DATA_8814B 0\n#define BIT_MASK_TC1DATA_8814B 0xffffff\n#define BIT_TC1DATA_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_TC1DATA_8814B) << BIT_SHIFT_TC1DATA_8814B)\n#define BITS_TC1DATA_8814B (BIT_MASK_TC1DATA_8814B << BIT_SHIFT_TC1DATA_8814B)\n#define BIT_CLEAR_TC1DATA_8814B(x) ((x) & (~BITS_TC1DATA_8814B))\n#define BIT_GET_TC1DATA_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC1DATA_8814B) & BIT_MASK_TC1DATA_8814B)\n#define BIT_SET_TC1DATA_8814B(x, v)                                            \\\n\t(BIT_CLEAR_TC1DATA_8814B(x) | BIT_TC1DATA_8814B(v))\n\n/* 2 REG_TC2_CTRL_8814B */\n#define BIT_TC2INT_EN_8814B BIT(26)\n#define BIT_TC2MODE_8814B BIT(25)\n#define BIT_TC2EN_8814B BIT(24)\n\n#define BIT_SHIFT_TC2DATA_8814B 0\n#define BIT_MASK_TC2DATA_8814B 0xffffff\n#define BIT_TC2DATA_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_TC2DATA_8814B) << BIT_SHIFT_TC2DATA_8814B)\n#define BITS_TC2DATA_8814B (BIT_MASK_TC2DATA_8814B << BIT_SHIFT_TC2DATA_8814B)\n#define BIT_CLEAR_TC2DATA_8814B(x) ((x) & (~BITS_TC2DATA_8814B))\n#define BIT_GET_TC2DATA_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC2DATA_8814B) & BIT_MASK_TC2DATA_8814B)\n#define BIT_SET_TC2DATA_8814B(x, v)                                            \\\n\t(BIT_CLEAR_TC2DATA_8814B(x) | BIT_TC2DATA_8814B(v))\n\n/* 2 REG_TC3_CTRL_8814B */\n#define BIT_TC3INT_EN_8814B BIT(26)\n#define BIT_TC3MODE_8814B BIT(25)\n#define BIT_TC3EN_8814B BIT(24)\n\n#define BIT_SHIFT_TC3DATA_8814B 0\n#define BIT_MASK_TC3DATA_8814B 0xffffff\n#define BIT_TC3DATA_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_TC3DATA_8814B) << BIT_SHIFT_TC3DATA_8814B)\n#define BITS_TC3DATA_8814B (BIT_MASK_TC3DATA_8814B << BIT_SHIFT_TC3DATA_8814B)\n#define BIT_CLEAR_TC3DATA_8814B(x) ((x) & (~BITS_TC3DATA_8814B))\n#define BIT_GET_TC3DATA_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC3DATA_8814B) & BIT_MASK_TC3DATA_8814B)\n#define BIT_SET_TC3DATA_8814B(x, v)                                            \\\n\t(BIT_CLEAR_TC3DATA_8814B(x) | BIT_TC3DATA_8814B(v))\n\n/* 2 REG_TC4_CTRL_8814B */\n#define BIT_TC4INT_EN_8814B BIT(26)\n#define BIT_TC4MODE_8814B BIT(25)\n#define BIT_TC4EN_8814B BIT(24)\n\n#define BIT_SHIFT_TC4DATA_8814B 0\n#define BIT_MASK_TC4DATA_8814B 0xffffff\n#define BIT_TC4DATA_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_TC4DATA_8814B) << BIT_SHIFT_TC4DATA_8814B)\n#define BITS_TC4DATA_8814B (BIT_MASK_TC4DATA_8814B << BIT_SHIFT_TC4DATA_8814B)\n#define BIT_CLEAR_TC4DATA_8814B(x) ((x) & (~BITS_TC4DATA_8814B))\n#define BIT_GET_TC4DATA_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC4DATA_8814B) & BIT_MASK_TC4DATA_8814B)\n#define BIT_SET_TC4DATA_8814B(x, v)                                            \\\n\t(BIT_CLEAR_TC4DATA_8814B(x) | BIT_TC4DATA_8814B(v))\n\n/* 2 REG_TCUNIT_BASE_8814B */\n\n#define BIT_SHIFT_TCUNIT_BASE_8814B 0\n#define BIT_MASK_TCUNIT_BASE_8814B 0x3fff\n#define BIT_TCUNIT_BASE_8814B(x)                                               \\\n\t(((x) & BIT_MASK_TCUNIT_BASE_8814B) << BIT_SHIFT_TCUNIT_BASE_8814B)\n#define BITS_TCUNIT_BASE_8814B                                                 \\\n\t(BIT_MASK_TCUNIT_BASE_8814B << BIT_SHIFT_TCUNIT_BASE_8814B)\n#define BIT_CLEAR_TCUNIT_BASE_8814B(x) ((x) & (~BITS_TCUNIT_BASE_8814B))\n#define BIT_GET_TCUNIT_BASE_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_TCUNIT_BASE_8814B) & BIT_MASK_TCUNIT_BASE_8814B)\n#define BIT_SET_TCUNIT_BASE_8814B(x, v)                                        \\\n\t(BIT_CLEAR_TCUNIT_BASE_8814B(x) | BIT_TCUNIT_BASE_8814B(v))\n\n/* 2 REG_TC5_CTRL_8814B */\n#define BIT_TC5INT_EN_8814B BIT(26)\n#define BIT_TC5MODE_8814B BIT(25)\n#define BIT_TC5EN_8814B BIT(24)\n\n#define BIT_SHIFT_TC5DATA_8814B 0\n#define BIT_MASK_TC5DATA_8814B 0xffffff\n#define BIT_TC5DATA_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_TC5DATA_8814B) << BIT_SHIFT_TC5DATA_8814B)\n#define BITS_TC5DATA_8814B (BIT_MASK_TC5DATA_8814B << BIT_SHIFT_TC5DATA_8814B)\n#define BIT_CLEAR_TC5DATA_8814B(x) ((x) & (~BITS_TC5DATA_8814B))\n#define BIT_GET_TC5DATA_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC5DATA_8814B) & BIT_MASK_TC5DATA_8814B)\n#define BIT_SET_TC5DATA_8814B(x, v)                                            \\\n\t(BIT_CLEAR_TC5DATA_8814B(x) | BIT_TC5DATA_8814B(v))\n\n/* 2 REG_TC6_CTRL_8814B */\n#define BIT_TC6INT_EN_8814B BIT(26)\n#define BIT_TC6MODE_8814B BIT(25)\n#define BIT_TC6EN_8814B BIT(24)\n\n#define BIT_SHIFT_TC6DATA_8814B 0\n#define BIT_MASK_TC6DATA_8814B 0xffffff\n#define BIT_TC6DATA_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_TC6DATA_8814B) << BIT_SHIFT_TC6DATA_8814B)\n#define BITS_TC6DATA_8814B (BIT_MASK_TC6DATA_8814B << BIT_SHIFT_TC6DATA_8814B)\n#define BIT_CLEAR_TC6DATA_8814B(x) ((x) & (~BITS_TC6DATA_8814B))\n#define BIT_GET_TC6DATA_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC6DATA_8814B) & BIT_MASK_TC6DATA_8814B)\n#define BIT_SET_TC6DATA_8814B(x, v)                                            \\\n\t(BIT_CLEAR_TC6DATA_8814B(x) | BIT_TC6DATA_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_AES_DECRPT_DATA_8814B */\n\n#define BIT_SHIFT_IPS_CFG_ADDR_8814B 0\n#define BIT_MASK_IPS_CFG_ADDR_8814B 0xff\n#define BIT_IPS_CFG_ADDR_8814B(x)                                              \\\n\t(((x) & BIT_MASK_IPS_CFG_ADDR_8814B) << BIT_SHIFT_IPS_CFG_ADDR_8814B)\n#define BITS_IPS_CFG_ADDR_8814B                                                \\\n\t(BIT_MASK_IPS_CFG_ADDR_8814B << BIT_SHIFT_IPS_CFG_ADDR_8814B)\n#define BIT_CLEAR_IPS_CFG_ADDR_8814B(x) ((x) & (~BITS_IPS_CFG_ADDR_8814B))\n#define BIT_GET_IPS_CFG_ADDR_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_IPS_CFG_ADDR_8814B) & BIT_MASK_IPS_CFG_ADDR_8814B)\n#define BIT_SET_IPS_CFG_ADDR_8814B(x, v)                                       \\\n\t(BIT_CLEAR_IPS_CFG_ADDR_8814B(x) | BIT_IPS_CFG_ADDR_8814B(v))\n\n/* 2 REG_AES_DECRPT_CFG_8814B */\n\n#define BIT_SHIFT_IPS_CFG_DATA_8814B 0\n#define BIT_MASK_IPS_CFG_DATA_8814B 0xffffffffL\n#define BIT_IPS_CFG_DATA_8814B(x)                                              \\\n\t(((x) & BIT_MASK_IPS_CFG_DATA_8814B) << BIT_SHIFT_IPS_CFG_DATA_8814B)\n#define BITS_IPS_CFG_DATA_8814B                                                \\\n\t(BIT_MASK_IPS_CFG_DATA_8814B << BIT_SHIFT_IPS_CFG_DATA_8814B)\n#define BIT_CLEAR_IPS_CFG_DATA_8814B(x) ((x) & (~BITS_IPS_CFG_DATA_8814B))\n#define BIT_GET_IPS_CFG_DATA_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_IPS_CFG_DATA_8814B) & BIT_MASK_IPS_CFG_DATA_8814B)\n#define BIT_SET_IPS_CFG_DATA_8814B(x, v)                                       \\\n\t(BIT_CLEAR_IPS_CFG_DATA_8814B(x) | BIT_IPS_CFG_DATA_8814B(v))\n\n/* 2 REG_HIOE_CTRL_8814B */\n#define BIT_HIOE_WRITE_REQ_8814B BIT(30)\n#define BIT_HIOE_READ_REQ_8814B BIT(29)\n#define BIT_INST_FORMAT_ERR_8814B BIT(25)\n#define BIT_OP_TIMEOUT_ERR_8814B BIT(24)\n\n#define BIT_SHIFT_HIOE_OP_TIMEOUT_8814B 16\n#define BIT_MASK_HIOE_OP_TIMEOUT_8814B 0xff\n#define BIT_HIOE_OP_TIMEOUT_8814B(x)                                           \\\n\t(((x) & BIT_MASK_HIOE_OP_TIMEOUT_8814B)                                \\\n\t << BIT_SHIFT_HIOE_OP_TIMEOUT_8814B)\n#define BITS_HIOE_OP_TIMEOUT_8814B                                             \\\n\t(BIT_MASK_HIOE_OP_TIMEOUT_8814B << BIT_SHIFT_HIOE_OP_TIMEOUT_8814B)\n#define BIT_CLEAR_HIOE_OP_TIMEOUT_8814B(x) ((x) & (~BITS_HIOE_OP_TIMEOUT_8814B))\n#define BIT_GET_HIOE_OP_TIMEOUT_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_HIOE_OP_TIMEOUT_8814B) &                            \\\n\t BIT_MASK_HIOE_OP_TIMEOUT_8814B)\n#define BIT_SET_HIOE_OP_TIMEOUT_8814B(x, v)                                    \\\n\t(BIT_CLEAR_HIOE_OP_TIMEOUT_8814B(x) | BIT_HIOE_OP_TIMEOUT_8814B(v))\n\n#define BIT_SHIFT_BITDATA_CHECKSUM_8814B 0\n#define BIT_MASK_BITDATA_CHECKSUM_8814B 0xffff\n#define BIT_BITDATA_CHECKSUM_8814B(x)                                          \\\n\t(((x) & BIT_MASK_BITDATA_CHECKSUM_8814B)                               \\\n\t << BIT_SHIFT_BITDATA_CHECKSUM_8814B)\n#define BITS_BITDATA_CHECKSUM_8814B                                            \\\n\t(BIT_MASK_BITDATA_CHECKSUM_8814B << BIT_SHIFT_BITDATA_CHECKSUM_8814B)\n#define BIT_CLEAR_BITDATA_CHECKSUM_8814B(x)                                    \\\n\t((x) & (~BITS_BITDATA_CHECKSUM_8814B))\n#define BIT_GET_BITDATA_CHECKSUM_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BITDATA_CHECKSUM_8814B) &                           \\\n\t BIT_MASK_BITDATA_CHECKSUM_8814B)\n#define BIT_SET_BITDATA_CHECKSUM_8814B(x, v)                                   \\\n\t(BIT_CLEAR_BITDATA_CHECKSUM_8814B(x) | BIT_BITDATA_CHECKSUM_8814B(v))\n\n/* 2 REG_HIOE_CFG_FILE_8814B */\n\n#define BIT_SHIFT_TXBF_END_ADDR_8814B 16\n#define BIT_MASK_TXBF_END_ADDR_8814B 0xffff\n#define BIT_TXBF_END_ADDR_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TXBF_END_ADDR_8814B) << BIT_SHIFT_TXBF_END_ADDR_8814B)\n#define BITS_TXBF_END_ADDR_8814B                                               \\\n\t(BIT_MASK_TXBF_END_ADDR_8814B << BIT_SHIFT_TXBF_END_ADDR_8814B)\n#define BIT_CLEAR_TXBF_END_ADDR_8814B(x) ((x) & (~BITS_TXBF_END_ADDR_8814B))\n#define BIT_GET_TXBF_END_ADDR_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXBF_END_ADDR_8814B) & BIT_MASK_TXBF_END_ADDR_8814B)\n#define BIT_SET_TXBF_END_ADDR_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TXBF_END_ADDR_8814B(x) | BIT_TXBF_END_ADDR_8814B(v))\n\n#define BIT_SHIFT_TXBF_STR_ADDR_8814B 0\n#define BIT_MASK_TXBF_STR_ADDR_8814B 0xffff\n#define BIT_TXBF_STR_ADDR_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TXBF_STR_ADDR_8814B) << BIT_SHIFT_TXBF_STR_ADDR_8814B)\n#define BITS_TXBF_STR_ADDR_8814B                                               \\\n\t(BIT_MASK_TXBF_STR_ADDR_8814B << BIT_SHIFT_TXBF_STR_ADDR_8814B)\n#define BIT_CLEAR_TXBF_STR_ADDR_8814B(x) ((x) & (~BITS_TXBF_STR_ADDR_8814B))\n#define BIT_GET_TXBF_STR_ADDR_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXBF_STR_ADDR_8814B) & BIT_MASK_TXBF_STR_ADDR_8814B)\n#define BIT_SET_TXBF_STR_ADDR_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TXBF_STR_ADDR_8814B(x) | BIT_TXBF_STR_ADDR_8814B(v))\n\n/* 2 REG_TMETER_8814B */\n#define BIT_TEMP_VALID_8814B BIT(31)\n\n#define BIT_SHIFT_TEMP_VALUE_8814B 24\n#define BIT_MASK_TEMP_VALUE_8814B 0x3f\n#define BIT_TEMP_VALUE_8814B(x)                                                \\\n\t(((x) & BIT_MASK_TEMP_VALUE_8814B) << BIT_SHIFT_TEMP_VALUE_8814B)\n#define BITS_TEMP_VALUE_8814B                                                  \\\n\t(BIT_MASK_TEMP_VALUE_8814B << BIT_SHIFT_TEMP_VALUE_8814B)\n#define BIT_CLEAR_TEMP_VALUE_8814B(x) ((x) & (~BITS_TEMP_VALUE_8814B))\n#define BIT_GET_TEMP_VALUE_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_TEMP_VALUE_8814B) & BIT_MASK_TEMP_VALUE_8814B)\n#define BIT_SET_TEMP_VALUE_8814B(x, v)                                         \\\n\t(BIT_CLEAR_TEMP_VALUE_8814B(x) | BIT_TEMP_VALUE_8814B(v))\n\n#define BIT_SHIFT_REG_TMETER_TIMER_8814B 8\n#define BIT_MASK_REG_TMETER_TIMER_8814B 0xfff\n#define BIT_REG_TMETER_TIMER_8814B(x)                                          \\\n\t(((x) & BIT_MASK_REG_TMETER_TIMER_8814B)                               \\\n\t << BIT_SHIFT_REG_TMETER_TIMER_8814B)\n#define BITS_REG_TMETER_TIMER_8814B                                            \\\n\t(BIT_MASK_REG_TMETER_TIMER_8814B << BIT_SHIFT_REG_TMETER_TIMER_8814B)\n#define BIT_CLEAR_REG_TMETER_TIMER_8814B(x)                                    \\\n\t((x) & (~BITS_REG_TMETER_TIMER_8814B))\n#define BIT_GET_REG_TMETER_TIMER_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_REG_TMETER_TIMER_8814B) &                           \\\n\t BIT_MASK_REG_TMETER_TIMER_8814B)\n#define BIT_SET_REG_TMETER_TIMER_8814B(x, v)                                   \\\n\t(BIT_CLEAR_REG_TMETER_TIMER_8814B(x) | BIT_REG_TMETER_TIMER_8814B(v))\n\n#define BIT_SHIFT_REG_TEMP_DELTA_8814B 2\n#define BIT_MASK_REG_TEMP_DELTA_8814B 0x3f\n#define BIT_REG_TEMP_DELTA_8814B(x)                                            \\\n\t(((x) & BIT_MASK_REG_TEMP_DELTA_8814B)                                 \\\n\t << BIT_SHIFT_REG_TEMP_DELTA_8814B)\n#define BITS_REG_TEMP_DELTA_8814B                                              \\\n\t(BIT_MASK_REG_TEMP_DELTA_8814B << BIT_SHIFT_REG_TEMP_DELTA_8814B)\n#define BIT_CLEAR_REG_TEMP_DELTA_8814B(x) ((x) & (~BITS_REG_TEMP_DELTA_8814B))\n#define BIT_GET_REG_TEMP_DELTA_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_REG_TEMP_DELTA_8814B) &                             \\\n\t BIT_MASK_REG_TEMP_DELTA_8814B)\n#define BIT_SET_REG_TEMP_DELTA_8814B(x, v)                                     \\\n\t(BIT_CLEAR_REG_TEMP_DELTA_8814B(x) | BIT_REG_TEMP_DELTA_8814B(v))\n\n#define BIT_REG_TMETER_EN_8814B BIT(0)\n\n/* 2 REG_OSC_32K_CTRL_8814B */\n\n#define BIT_SHIFT_OSC_32K_CLKGEN_0_8814B 16\n#define BIT_MASK_OSC_32K_CLKGEN_0_8814B 0xffff\n#define BIT_OSC_32K_CLKGEN_0_8814B(x)                                          \\\n\t(((x) & BIT_MASK_OSC_32K_CLKGEN_0_8814B)                               \\\n\t << BIT_SHIFT_OSC_32K_CLKGEN_0_8814B)\n#define BITS_OSC_32K_CLKGEN_0_8814B                                            \\\n\t(BIT_MASK_OSC_32K_CLKGEN_0_8814B << BIT_SHIFT_OSC_32K_CLKGEN_0_8814B)\n#define BIT_CLEAR_OSC_32K_CLKGEN_0_8814B(x)                                    \\\n\t((x) & (~BITS_OSC_32K_CLKGEN_0_8814B))\n#define BIT_GET_OSC_32K_CLKGEN_0_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8814B) &                           \\\n\t BIT_MASK_OSC_32K_CLKGEN_0_8814B)\n#define BIT_SET_OSC_32K_CLKGEN_0_8814B(x, v)                                   \\\n\t(BIT_CLEAR_OSC_32K_CLKGEN_0_8814B(x) | BIT_OSC_32K_CLKGEN_0_8814B(v))\n\n#define BIT_SHIFT_OSC_32K_RES_COMP_8814B 4\n#define BIT_MASK_OSC_32K_RES_COMP_8814B 0x3\n#define BIT_OSC_32K_RES_COMP_8814B(x)                                          \\\n\t(((x) & BIT_MASK_OSC_32K_RES_COMP_8814B)                               \\\n\t << BIT_SHIFT_OSC_32K_RES_COMP_8814B)\n#define BITS_OSC_32K_RES_COMP_8814B                                            \\\n\t(BIT_MASK_OSC_32K_RES_COMP_8814B << BIT_SHIFT_OSC_32K_RES_COMP_8814B)\n#define BIT_CLEAR_OSC_32K_RES_COMP_8814B(x)                                    \\\n\t((x) & (~BITS_OSC_32K_RES_COMP_8814B))\n#define BIT_GET_OSC_32K_RES_COMP_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8814B) &                           \\\n\t BIT_MASK_OSC_32K_RES_COMP_8814B)\n#define BIT_SET_OSC_32K_RES_COMP_8814B(x, v)                                   \\\n\t(BIT_CLEAR_OSC_32K_RES_COMP_8814B(x) | BIT_OSC_32K_RES_COMP_8814B(v))\n\n#define BIT_OSC_32K_OUT_SEL_8814B BIT(3)\n#define BIT_ISO_WL_2_OSC_32K_8814B BIT(1)\n#define BIT_POW_CKGEN_8814B BIT(0)\n\n/* 2 REG_32K_CAL_REG1_8814B */\n#define BIT_CAL_32K_REG_WR_8814B BIT(31)\n#define BIT_CAL_32K_DBG_SEL_8814B BIT(22)\n\n#define BIT_SHIFT_CAL_32K_REG_ADDR_8814B 16\n#define BIT_MASK_CAL_32K_REG_ADDR_8814B 0x3f\n#define BIT_CAL_32K_REG_ADDR_8814B(x)                                          \\\n\t(((x) & BIT_MASK_CAL_32K_REG_ADDR_8814B)                               \\\n\t << BIT_SHIFT_CAL_32K_REG_ADDR_8814B)\n#define BITS_CAL_32K_REG_ADDR_8814B                                            \\\n\t(BIT_MASK_CAL_32K_REG_ADDR_8814B << BIT_SHIFT_CAL_32K_REG_ADDR_8814B)\n#define BIT_CLEAR_CAL_32K_REG_ADDR_8814B(x)                                    \\\n\t((x) & (~BITS_CAL_32K_REG_ADDR_8814B))\n#define BIT_GET_CAL_32K_REG_ADDR_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8814B) &                           \\\n\t BIT_MASK_CAL_32K_REG_ADDR_8814B)\n#define BIT_SET_CAL_32K_REG_ADDR_8814B(x, v)                                   \\\n\t(BIT_CLEAR_CAL_32K_REG_ADDR_8814B(x) | BIT_CAL_32K_REG_ADDR_8814B(v))\n\n#define BIT_SHIFT_CAL_32K_REG_DATA_8814B 0\n#define BIT_MASK_CAL_32K_REG_DATA_8814B 0xffff\n#define BIT_CAL_32K_REG_DATA_8814B(x)                                          \\\n\t(((x) & BIT_MASK_CAL_32K_REG_DATA_8814B)                               \\\n\t << BIT_SHIFT_CAL_32K_REG_DATA_8814B)\n#define BITS_CAL_32K_REG_DATA_8814B                                            \\\n\t(BIT_MASK_CAL_32K_REG_DATA_8814B << BIT_SHIFT_CAL_32K_REG_DATA_8814B)\n#define BIT_CLEAR_CAL_32K_REG_DATA_8814B(x)                                    \\\n\t((x) & (~BITS_CAL_32K_REG_DATA_8814B))\n#define BIT_GET_CAL_32K_REG_DATA_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8814B) &                           \\\n\t BIT_MASK_CAL_32K_REG_DATA_8814B)\n#define BIT_SET_CAL_32K_REG_DATA_8814B(x, v)                                   \\\n\t(BIT_CLEAR_CAL_32K_REG_DATA_8814B(x) | BIT_CAL_32K_REG_DATA_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_C2HEVT_8814B */\n\n#define BIT_SHIFT_C2HEVT_MSG_V1_8814B 0\n#define BIT_MASK_C2HEVT_MSG_V1_8814B 0xffffffffL\n#define BIT_C2HEVT_MSG_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_V1_8814B) << BIT_SHIFT_C2HEVT_MSG_V1_8814B)\n#define BITS_C2HEVT_MSG_V1_8814B                                               \\\n\t(BIT_MASK_C2HEVT_MSG_V1_8814B << BIT_SHIFT_C2HEVT_MSG_V1_8814B)\n#define BIT_CLEAR_C2HEVT_MSG_V1_8814B(x) ((x) & (~BITS_C2HEVT_MSG_V1_8814B))\n#define BIT_GET_C2HEVT_MSG_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8814B) & BIT_MASK_C2HEVT_MSG_V1_8814B)\n#define BIT_SET_C2HEVT_MSG_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_C2HEVT_MSG_V1_8814B(x) | BIT_C2HEVT_MSG_V1_8814B(v))\n\n/* 2 REG_C2HEVT_1_8814B */\n\n#define BIT_SHIFT_C2HEVT_MSG_1_8814B 0\n#define BIT_MASK_C2HEVT_MSG_1_8814B 0xffffffffL\n#define BIT_C2HEVT_MSG_1_8814B(x)                                              \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_1_8814B) << BIT_SHIFT_C2HEVT_MSG_1_8814B)\n#define BITS_C2HEVT_MSG_1_8814B                                                \\\n\t(BIT_MASK_C2HEVT_MSG_1_8814B << BIT_SHIFT_C2HEVT_MSG_1_8814B)\n#define BIT_CLEAR_C2HEVT_MSG_1_8814B(x) ((x) & (~BITS_C2HEVT_MSG_1_8814B))\n#define BIT_GET_C2HEVT_MSG_1_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_1_8814B) & BIT_MASK_C2HEVT_MSG_1_8814B)\n#define BIT_SET_C2HEVT_MSG_1_8814B(x, v)                                       \\\n\t(BIT_CLEAR_C2HEVT_MSG_1_8814B(x) | BIT_C2HEVT_MSG_1_8814B(v))\n\n/* 2 REG_C2HEVT_2_8814B */\n\n#define BIT_SHIFT_C2HEVT_MSG_2_8814B 0\n#define BIT_MASK_C2HEVT_MSG_2_8814B 0xffffffffL\n#define BIT_C2HEVT_MSG_2_8814B(x)                                              \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_2_8814B) << BIT_SHIFT_C2HEVT_MSG_2_8814B)\n#define BITS_C2HEVT_MSG_2_8814B                                                \\\n\t(BIT_MASK_C2HEVT_MSG_2_8814B << BIT_SHIFT_C2HEVT_MSG_2_8814B)\n#define BIT_CLEAR_C2HEVT_MSG_2_8814B(x) ((x) & (~BITS_C2HEVT_MSG_2_8814B))\n#define BIT_GET_C2HEVT_MSG_2_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_2_8814B) & BIT_MASK_C2HEVT_MSG_2_8814B)\n#define BIT_SET_C2HEVT_MSG_2_8814B(x, v)                                       \\\n\t(BIT_CLEAR_C2HEVT_MSG_2_8814B(x) | BIT_C2HEVT_MSG_2_8814B(v))\n\n/* 2 REG_C2HEVT_3_8814B */\n\n#define BIT_SHIFT_C2HEVT_MSG_3_8814B 0\n#define BIT_MASK_C2HEVT_MSG_3_8814B 0xffffffffL\n#define BIT_C2HEVT_MSG_3_8814B(x)                                              \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_3_8814B) << BIT_SHIFT_C2HEVT_MSG_3_8814B)\n#define BITS_C2HEVT_MSG_3_8814B                                                \\\n\t(BIT_MASK_C2HEVT_MSG_3_8814B << BIT_SHIFT_C2HEVT_MSG_3_8814B)\n#define BIT_CLEAR_C2HEVT_MSG_3_8814B(x) ((x) & (~BITS_C2HEVT_MSG_3_8814B))\n#define BIT_GET_C2HEVT_MSG_3_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_3_8814B) & BIT_MASK_C2HEVT_MSG_3_8814B)\n#define BIT_SET_C2HEVT_MSG_3_8814B(x, v)                                       \\\n\t(BIT_CLEAR_C2HEVT_MSG_3_8814B(x) | BIT_C2HEVT_MSG_3_8814B(v))\n\n/* 2 REG_RXDESC_BUFF_RPTR_8814B */\n\n#define BIT_SHIFT_RXDESC_BUFF_RPTR_8814B 0\n#define BIT_MASK_RXDESC_BUFF_RPTR_8814B 0xffffffffL\n#define BIT_RXDESC_BUFF_RPTR_8814B(x)                                          \\\n\t(((x) & BIT_MASK_RXDESC_BUFF_RPTR_8814B)                               \\\n\t << BIT_SHIFT_RXDESC_BUFF_RPTR_8814B)\n#define BITS_RXDESC_BUFF_RPTR_8814B                                            \\\n\t(BIT_MASK_RXDESC_BUFF_RPTR_8814B << BIT_SHIFT_RXDESC_BUFF_RPTR_8814B)\n#define BIT_CLEAR_RXDESC_BUFF_RPTR_8814B(x)                                    \\\n\t((x) & (~BITS_RXDESC_BUFF_RPTR_8814B))\n#define BIT_GET_RXDESC_BUFF_RPTR_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_RXDESC_BUFF_RPTR_8814B) &                           \\\n\t BIT_MASK_RXDESC_BUFF_RPTR_8814B)\n#define BIT_SET_RXDESC_BUFF_RPTR_8814B(x, v)                                   \\\n\t(BIT_CLEAR_RXDESC_BUFF_RPTR_8814B(x) | BIT_RXDESC_BUFF_RPTR_8814B(v))\n\n/* 2 REG_RXDESC_BUFF_WPTR_8814B */\n\n#define BIT_SHIFT_RXDESC_BUFF_WPTR_8814B 0\n#define BIT_MASK_RXDESC_BUFF_WPTR_8814B 0xffffffffL\n#define BIT_RXDESC_BUFF_WPTR_8814B(x)                                          \\\n\t(((x) & BIT_MASK_RXDESC_BUFF_WPTR_8814B)                               \\\n\t << BIT_SHIFT_RXDESC_BUFF_WPTR_8814B)\n#define BITS_RXDESC_BUFF_WPTR_8814B                                            \\\n\t(BIT_MASK_RXDESC_BUFF_WPTR_8814B << BIT_SHIFT_RXDESC_BUFF_WPTR_8814B)\n#define BIT_CLEAR_RXDESC_BUFF_WPTR_8814B(x)                                    \\\n\t((x) & (~BITS_RXDESC_BUFF_WPTR_8814B))\n#define BIT_GET_RXDESC_BUFF_WPTR_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_RXDESC_BUFF_WPTR_8814B) &                           \\\n\t BIT_MASK_RXDESC_BUFF_WPTR_8814B)\n#define BIT_SET_RXDESC_BUFF_WPTR_8814B(x, v)                                   \\\n\t(BIT_CLEAR_RXDESC_BUFF_WPTR_8814B(x) | BIT_RXDESC_BUFF_WPTR_8814B(v))\n\n/* 2 REG_SW_DEFINED_PAGE1_8814B */\n\n#define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B 0\n#define BIT_MASK_SW_DEFINED_PAGE1_V1_8814B 0xffffffffL\n#define BIT_SW_DEFINED_PAGE1_V1_8814B(x)                                       \\\n\t(((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8814B)                            \\\n\t << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B)\n#define BITS_SW_DEFINED_PAGE1_V1_8814B                                         \\\n\t(BIT_MASK_SW_DEFINED_PAGE1_V1_8814B                                    \\\n\t << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B)\n#define BIT_CLEAR_SW_DEFINED_PAGE1_V1_8814B(x)                                 \\\n\t((x) & (~BITS_SW_DEFINED_PAGE1_V1_8814B))\n#define BIT_GET_SW_DEFINED_PAGE1_V1_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B) &                        \\\n\t BIT_MASK_SW_DEFINED_PAGE1_V1_8814B)\n#define BIT_SET_SW_DEFINED_PAGE1_V1_8814B(x, v)                                \\\n\t(BIT_CLEAR_SW_DEFINED_PAGE1_V1_8814B(x) |                              \\\n\t BIT_SW_DEFINED_PAGE1_V1_8814B(v))\n\n/* 2 REG_SW_DEFINED_PAGE2_8814B */\n\n#define BIT_SHIFT_SW_DEFINED_PAGE2_8814B 0\n#define BIT_MASK_SW_DEFINED_PAGE2_8814B 0xffffffffL\n#define BIT_SW_DEFINED_PAGE2_8814B(x)                                          \\\n\t(((x) & BIT_MASK_SW_DEFINED_PAGE2_8814B)                               \\\n\t << BIT_SHIFT_SW_DEFINED_PAGE2_8814B)\n#define BITS_SW_DEFINED_PAGE2_8814B                                            \\\n\t(BIT_MASK_SW_DEFINED_PAGE2_8814B << BIT_SHIFT_SW_DEFINED_PAGE2_8814B)\n#define BIT_CLEAR_SW_DEFINED_PAGE2_8814B(x)                                    \\\n\t((x) & (~BITS_SW_DEFINED_PAGE2_8814B))\n#define BIT_GET_SW_DEFINED_PAGE2_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8814B) &                           \\\n\t BIT_MASK_SW_DEFINED_PAGE2_8814B)\n#define BIT_SET_SW_DEFINED_PAGE2_8814B(x, v)                                   \\\n\t(BIT_CLEAR_SW_DEFINED_PAGE2_8814B(x) | BIT_SW_DEFINED_PAGE2_8814B(v))\n\n/* 2 REG_MCUTST_I_8814B */\n\n#define BIT_SHIFT_MCUDMSG_I_8814B 0\n#define BIT_MASK_MCUDMSG_I_8814B 0xffffffffL\n#define BIT_MCUDMSG_I_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_MCUDMSG_I_8814B) << BIT_SHIFT_MCUDMSG_I_8814B)\n#define BITS_MCUDMSG_I_8814B                                                   \\\n\t(BIT_MASK_MCUDMSG_I_8814B << BIT_SHIFT_MCUDMSG_I_8814B)\n#define BIT_CLEAR_MCUDMSG_I_8814B(x) ((x) & (~BITS_MCUDMSG_I_8814B))\n#define BIT_GET_MCUDMSG_I_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_MCUDMSG_I_8814B) & BIT_MASK_MCUDMSG_I_8814B)\n#define BIT_SET_MCUDMSG_I_8814B(x, v)                                          \\\n\t(BIT_CLEAR_MCUDMSG_I_8814B(x) | BIT_MCUDMSG_I_8814B(v))\n\n/* 2 REG_MCUTST_II_8814B */\n\n#define BIT_SHIFT_MCUDMSG_II_8814B 0\n#define BIT_MASK_MCUDMSG_II_8814B 0xffffffffL\n#define BIT_MCUDMSG_II_8814B(x)                                                \\\n\t(((x) & BIT_MASK_MCUDMSG_II_8814B) << BIT_SHIFT_MCUDMSG_II_8814B)\n#define BITS_MCUDMSG_II_8814B                                                  \\\n\t(BIT_MASK_MCUDMSG_II_8814B << BIT_SHIFT_MCUDMSG_II_8814B)\n#define BIT_CLEAR_MCUDMSG_II_8814B(x) ((x) & (~BITS_MCUDMSG_II_8814B))\n#define BIT_GET_MCUDMSG_II_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_MCUDMSG_II_8814B) & BIT_MASK_MCUDMSG_II_8814B)\n#define BIT_SET_MCUDMSG_II_8814B(x, v)                                         \\\n\t(BIT_CLEAR_MCUDMSG_II_8814B(x) | BIT_MCUDMSG_II_8814B(v))\n\n/* 2 REG_FMETHR_8814B */\n#define BIT_FMSG_INT_8814B BIT(31)\n\n#define BIT_SHIFT_FW_MSG_8814B 0\n#define BIT_MASK_FW_MSG_8814B 0xffffffffL\n#define BIT_FW_MSG_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_FW_MSG_8814B) << BIT_SHIFT_FW_MSG_8814B)\n#define BITS_FW_MSG_8814B (BIT_MASK_FW_MSG_8814B << BIT_SHIFT_FW_MSG_8814B)\n#define BIT_CLEAR_FW_MSG_8814B(x) ((x) & (~BITS_FW_MSG_8814B))\n#define BIT_GET_FW_MSG_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_FW_MSG_8814B) & BIT_MASK_FW_MSG_8814B)\n#define BIT_SET_FW_MSG_8814B(x, v)                                             \\\n\t(BIT_CLEAR_FW_MSG_8814B(x) | BIT_FW_MSG_8814B(v))\n\n/* 2 REG_HMETFR_8814B */\n\n#define BIT_SHIFT_HRCV_MSG_8814B 24\n#define BIT_MASK_HRCV_MSG_8814B 0xff\n#define BIT_HRCV_MSG_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_HRCV_MSG_8814B) << BIT_SHIFT_HRCV_MSG_8814B)\n#define BITS_HRCV_MSG_8814B                                                    \\\n\t(BIT_MASK_HRCV_MSG_8814B << BIT_SHIFT_HRCV_MSG_8814B)\n#define BIT_CLEAR_HRCV_MSG_8814B(x) ((x) & (~BITS_HRCV_MSG_8814B))\n#define BIT_GET_HRCV_MSG_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_HRCV_MSG_8814B) & BIT_MASK_HRCV_MSG_8814B)\n#define BIT_SET_HRCV_MSG_8814B(x, v)                                           \\\n\t(BIT_CLEAR_HRCV_MSG_8814B(x) | BIT_HRCV_MSG_8814B(v))\n\n#define BIT_INT_BOX3_8814B BIT(3)\n#define BIT_INT_BOX2_8814B BIT(2)\n#define BIT_INT_BOX1_8814B BIT(1)\n#define BIT_INT_BOX0_8814B BIT(0)\n\n/* 2 REG_HMEBOX0_8814B */\n\n#define BIT_SHIFT_HOST_MSG_0_8814B 0\n#define BIT_MASK_HOST_MSG_0_8814B 0xffffffffL\n#define BIT_HOST_MSG_0_8814B(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_0_8814B) << BIT_SHIFT_HOST_MSG_0_8814B)\n#define BITS_HOST_MSG_0_8814B                                                  \\\n\t(BIT_MASK_HOST_MSG_0_8814B << BIT_SHIFT_HOST_MSG_0_8814B)\n#define BIT_CLEAR_HOST_MSG_0_8814B(x) ((x) & (~BITS_HOST_MSG_0_8814B))\n#define BIT_GET_HOST_MSG_0_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_0_8814B) & BIT_MASK_HOST_MSG_0_8814B)\n#define BIT_SET_HOST_MSG_0_8814B(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_0_8814B(x) | BIT_HOST_MSG_0_8814B(v))\n\n/* 2 REG_HMEBOX1_8814B */\n\n#define BIT_SHIFT_HOST_MSG_1_8814B 0\n#define BIT_MASK_HOST_MSG_1_8814B 0xffffffffL\n#define BIT_HOST_MSG_1_8814B(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_1_8814B) << BIT_SHIFT_HOST_MSG_1_8814B)\n#define BITS_HOST_MSG_1_8814B                                                  \\\n\t(BIT_MASK_HOST_MSG_1_8814B << BIT_SHIFT_HOST_MSG_1_8814B)\n#define BIT_CLEAR_HOST_MSG_1_8814B(x) ((x) & (~BITS_HOST_MSG_1_8814B))\n#define BIT_GET_HOST_MSG_1_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_1_8814B) & BIT_MASK_HOST_MSG_1_8814B)\n#define BIT_SET_HOST_MSG_1_8814B(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_1_8814B(x) | BIT_HOST_MSG_1_8814B(v))\n\n/* 2 REG_HMEBOX2_8814B */\n\n#define BIT_SHIFT_HOST_MSG_2_8814B 0\n#define BIT_MASK_HOST_MSG_2_8814B 0xffffffffL\n#define BIT_HOST_MSG_2_8814B(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_2_8814B) << BIT_SHIFT_HOST_MSG_2_8814B)\n#define BITS_HOST_MSG_2_8814B                                                  \\\n\t(BIT_MASK_HOST_MSG_2_8814B << BIT_SHIFT_HOST_MSG_2_8814B)\n#define BIT_CLEAR_HOST_MSG_2_8814B(x) ((x) & (~BITS_HOST_MSG_2_8814B))\n#define BIT_GET_HOST_MSG_2_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_2_8814B) & BIT_MASK_HOST_MSG_2_8814B)\n#define BIT_SET_HOST_MSG_2_8814B(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_2_8814B(x) | BIT_HOST_MSG_2_8814B(v))\n\n/* 2 REG_HMEBOX3_8814B */\n\n#define BIT_SHIFT_HOST_MSG_3_8814B 0\n#define BIT_MASK_HOST_MSG_3_8814B 0xffffffffL\n#define BIT_HOST_MSG_3_8814B(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_3_8814B) << BIT_SHIFT_HOST_MSG_3_8814B)\n#define BITS_HOST_MSG_3_8814B                                                  \\\n\t(BIT_MASK_HOST_MSG_3_8814B << BIT_SHIFT_HOST_MSG_3_8814B)\n#define BIT_CLEAR_HOST_MSG_3_8814B(x) ((x) & (~BITS_HOST_MSG_3_8814B))\n#define BIT_GET_HOST_MSG_3_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_3_8814B) & BIT_MASK_HOST_MSG_3_8814B)\n#define BIT_SET_HOST_MSG_3_8814B(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_3_8814B(x) | BIT_HOST_MSG_3_8814B(v))\n\n/* 2 REG_RXDESC_BUFF_BNDY_8814B */\n\n#define BIT_SHIFT_RXDESC_BUFF_BNDY_8814B 0\n#define BIT_MASK_RXDESC_BUFF_BNDY_8814B 0xffffffffL\n#define BIT_RXDESC_BUFF_BNDY_8814B(x)                                          \\\n\t(((x) & BIT_MASK_RXDESC_BUFF_BNDY_8814B)                               \\\n\t << BIT_SHIFT_RXDESC_BUFF_BNDY_8814B)\n#define BITS_RXDESC_BUFF_BNDY_8814B                                            \\\n\t(BIT_MASK_RXDESC_BUFF_BNDY_8814B << BIT_SHIFT_RXDESC_BUFF_BNDY_8814B)\n#define BIT_CLEAR_RXDESC_BUFF_BNDY_8814B(x)                                    \\\n\t((x) & (~BITS_RXDESC_BUFF_BNDY_8814B))\n#define BIT_GET_RXDESC_BUFF_BNDY_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_RXDESC_BUFF_BNDY_8814B) &                           \\\n\t BIT_MASK_RXDESC_BUFF_BNDY_8814B)\n#define BIT_SET_RXDESC_BUFF_BNDY_8814B(x, v)                                   \\\n\t(BIT_CLEAR_RXDESC_BUFF_BNDY_8814B(x) | BIT_RXDESC_BUFF_BNDY_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_BB_ACCESS_CTRL_8814B */\n\n#define BIT_SHIFT_BB_WRITE_READ_8814B 30\n#define BIT_MASK_BB_WRITE_READ_8814B 0x3\n#define BIT_BB_WRITE_READ_8814B(x)                                             \\\n\t(((x) & BIT_MASK_BB_WRITE_READ_8814B) << BIT_SHIFT_BB_WRITE_READ_8814B)\n#define BITS_BB_WRITE_READ_8814B                                               \\\n\t(BIT_MASK_BB_WRITE_READ_8814B << BIT_SHIFT_BB_WRITE_READ_8814B)\n#define BIT_CLEAR_BB_WRITE_READ_8814B(x) ((x) & (~BITS_BB_WRITE_READ_8814B))\n#define BIT_GET_BB_WRITE_READ_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_BB_WRITE_READ_8814B) & BIT_MASK_BB_WRITE_READ_8814B)\n#define BIT_SET_BB_WRITE_READ_8814B(x, v)                                      \\\n\t(BIT_CLEAR_BB_WRITE_READ_8814B(x) | BIT_BB_WRITE_READ_8814B(v))\n\n#define BIT_SHIFT_BB_WRITE_EN_8814B 12\n#define BIT_MASK_BB_WRITE_EN_8814B 0xf\n#define BIT_BB_WRITE_EN_8814B(x)                                               \\\n\t(((x) & BIT_MASK_BB_WRITE_EN_8814B) << BIT_SHIFT_BB_WRITE_EN_8814B)\n#define BITS_BB_WRITE_EN_8814B                                                 \\\n\t(BIT_MASK_BB_WRITE_EN_8814B << BIT_SHIFT_BB_WRITE_EN_8814B)\n#define BIT_CLEAR_BB_WRITE_EN_8814B(x) ((x) & (~BITS_BB_WRITE_EN_8814B))\n#define BIT_GET_BB_WRITE_EN_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_BB_WRITE_EN_8814B) & BIT_MASK_BB_WRITE_EN_8814B)\n#define BIT_SET_BB_WRITE_EN_8814B(x, v)                                        \\\n\t(BIT_CLEAR_BB_WRITE_EN_8814B(x) | BIT_BB_WRITE_EN_8814B(v))\n\n#define BIT_SHIFT_BB_ADDR_8814B 2\n#define BIT_MASK_BB_ADDR_8814B 0x1ff\n#define BIT_BB_ADDR_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_BB_ADDR_8814B) << BIT_SHIFT_BB_ADDR_8814B)\n#define BITS_BB_ADDR_8814B (BIT_MASK_BB_ADDR_8814B << BIT_SHIFT_BB_ADDR_8814B)\n#define BIT_CLEAR_BB_ADDR_8814B(x) ((x) & (~BITS_BB_ADDR_8814B))\n#define BIT_GET_BB_ADDR_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_BB_ADDR_8814B) & BIT_MASK_BB_ADDR_8814B)\n#define BIT_SET_BB_ADDR_8814B(x, v)                                            \\\n\t(BIT_CLEAR_BB_ADDR_8814B(x) | BIT_BB_ADDR_8814B(v))\n\n#define BIT_BB_ERRACC_8814B BIT(0)\n\n/* 2 REG_BB_ACCESS_DATA_8814B */\n\n#define BIT_SHIFT_BB_DATA_8814B 0\n#define BIT_MASK_BB_DATA_8814B 0xffffffffL\n#define BIT_BB_DATA_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_BB_DATA_8814B) << BIT_SHIFT_BB_DATA_8814B)\n#define BITS_BB_DATA_8814B (BIT_MASK_BB_DATA_8814B << BIT_SHIFT_BB_DATA_8814B)\n#define BIT_CLEAR_BB_DATA_8814B(x) ((x) & (~BITS_BB_DATA_8814B))\n#define BIT_GET_BB_DATA_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_BB_DATA_8814B) & BIT_MASK_BB_DATA_8814B)\n#define BIT_SET_BB_DATA_8814B(x, v)                                            \\\n\t(BIT_CLEAR_BB_DATA_8814B(x) | BIT_BB_DATA_8814B(v))\n\n/* 2 REG_HMEBOX_E0_8814B */\n\n#define BIT_SHIFT_HMEBOX_E0_8814B 0\n#define BIT_MASK_HMEBOX_E0_8814B 0xffffffffL\n#define BIT_HMEBOX_E0_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E0_8814B) << BIT_SHIFT_HMEBOX_E0_8814B)\n#define BITS_HMEBOX_E0_8814B                                                   \\\n\t(BIT_MASK_HMEBOX_E0_8814B << BIT_SHIFT_HMEBOX_E0_8814B)\n#define BIT_CLEAR_HMEBOX_E0_8814B(x) ((x) & (~BITS_HMEBOX_E0_8814B))\n#define BIT_GET_HMEBOX_E0_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E0_8814B) & BIT_MASK_HMEBOX_E0_8814B)\n#define BIT_SET_HMEBOX_E0_8814B(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E0_8814B(x) | BIT_HMEBOX_E0_8814B(v))\n\n/* 2 REG_HMEBOX_E1_8814B */\n\n#define BIT_SHIFT_HMEBOX_E1_8814B 0\n#define BIT_MASK_HMEBOX_E1_8814B 0xffffffffL\n#define BIT_HMEBOX_E1_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E1_8814B) << BIT_SHIFT_HMEBOX_E1_8814B)\n#define BITS_HMEBOX_E1_8814B                                                   \\\n\t(BIT_MASK_HMEBOX_E1_8814B << BIT_SHIFT_HMEBOX_E1_8814B)\n#define BIT_CLEAR_HMEBOX_E1_8814B(x) ((x) & (~BITS_HMEBOX_E1_8814B))\n#define BIT_GET_HMEBOX_E1_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E1_8814B) & BIT_MASK_HMEBOX_E1_8814B)\n#define BIT_SET_HMEBOX_E1_8814B(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E1_8814B(x) | BIT_HMEBOX_E1_8814B(v))\n\n/* 2 REG_HMEBOX_E2_8814B */\n\n#define BIT_SHIFT_HMEBOX_E2_8814B 0\n#define BIT_MASK_HMEBOX_E2_8814B 0xffffffffL\n#define BIT_HMEBOX_E2_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E2_8814B) << BIT_SHIFT_HMEBOX_E2_8814B)\n#define BITS_HMEBOX_E2_8814B                                                   \\\n\t(BIT_MASK_HMEBOX_E2_8814B << BIT_SHIFT_HMEBOX_E2_8814B)\n#define BIT_CLEAR_HMEBOX_E2_8814B(x) ((x) & (~BITS_HMEBOX_E2_8814B))\n#define BIT_GET_HMEBOX_E2_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E2_8814B) & BIT_MASK_HMEBOX_E2_8814B)\n#define BIT_SET_HMEBOX_E2_8814B(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E2_8814B(x) | BIT_HMEBOX_E2_8814B(v))\n\n/* 2 REG_HMEBOX_E3_8814B */\n\n#define BIT_SHIFT_HMEBOX_E3_8814B 0\n#define BIT_MASK_HMEBOX_E3_8814B 0xffffffffL\n#define BIT_HMEBOX_E3_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E3_8814B) << BIT_SHIFT_HMEBOX_E3_8814B)\n#define BITS_HMEBOX_E3_8814B                                                   \\\n\t(BIT_MASK_HMEBOX_E3_8814B << BIT_SHIFT_HMEBOX_E3_8814B)\n#define BIT_CLEAR_HMEBOX_E3_8814B(x) ((x) & (~BITS_HMEBOX_E3_8814B))\n#define BIT_GET_HMEBOX_E3_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E3_8814B) & BIT_MASK_HMEBOX_E3_8814B)\n#define BIT_SET_HMEBOX_E3_8814B(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E3_8814B(x) | BIT_HMEBOX_E3_8814B(v))\n\n/* 2 REG_CR_EXT_8814B */\n\n#define BIT_SHIFT_PHY_REQ_DELAY_8814B 24\n#define BIT_MASK_PHY_REQ_DELAY_8814B 0xf\n#define BIT_PHY_REQ_DELAY_8814B(x)                                             \\\n\t(((x) & BIT_MASK_PHY_REQ_DELAY_8814B) << BIT_SHIFT_PHY_REQ_DELAY_8814B)\n#define BITS_PHY_REQ_DELAY_8814B                                               \\\n\t(BIT_MASK_PHY_REQ_DELAY_8814B << BIT_SHIFT_PHY_REQ_DELAY_8814B)\n#define BIT_CLEAR_PHY_REQ_DELAY_8814B(x) ((x) & (~BITS_PHY_REQ_DELAY_8814B))\n#define BIT_GET_PHY_REQ_DELAY_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PHY_REQ_DELAY_8814B) & BIT_MASK_PHY_REQ_DELAY_8814B)\n#define BIT_SET_PHY_REQ_DELAY_8814B(x, v)                                      \\\n\t(BIT_CLEAR_PHY_REQ_DELAY_8814B(x) | BIT_PHY_REQ_DELAY_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_FW_FIFO_PTR_RST_8814B BIT(18)\n#define BIT_PHY_FIFO_PTR_RST_8814B BIT(17)\n#define BIT_SPD_DOWN_8814B BIT(16)\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_NETYPE4_8814B 4\n#define BIT_MASK_NETYPE4_8814B 0x3\n#define BIT_NETYPE4_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE4_8814B) << BIT_SHIFT_NETYPE4_8814B)\n#define BITS_NETYPE4_8814B (BIT_MASK_NETYPE4_8814B << BIT_SHIFT_NETYPE4_8814B)\n#define BIT_CLEAR_NETYPE4_8814B(x) ((x) & (~BITS_NETYPE4_8814B))\n#define BIT_GET_NETYPE4_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE4_8814B) & BIT_MASK_NETYPE4_8814B)\n#define BIT_SET_NETYPE4_8814B(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE4_8814B(x) | BIT_NETYPE4_8814B(v))\n\n#define BIT_SHIFT_NETYPE3_8814B 2\n#define BIT_MASK_NETYPE3_8814B 0x3\n#define BIT_NETYPE3_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE3_8814B) << BIT_SHIFT_NETYPE3_8814B)\n#define BITS_NETYPE3_8814B (BIT_MASK_NETYPE3_8814B << BIT_SHIFT_NETYPE3_8814B)\n#define BIT_CLEAR_NETYPE3_8814B(x) ((x) & (~BITS_NETYPE3_8814B))\n#define BIT_GET_NETYPE3_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE3_8814B) & BIT_MASK_NETYPE3_8814B)\n#define BIT_SET_NETYPE3_8814B(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE3_8814B(x) | BIT_NETYPE3_8814B(v))\n\n#define BIT_SHIFT_NETYPE2_8814B 0\n#define BIT_MASK_NETYPE2_8814B 0x3\n#define BIT_NETYPE2_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE2_8814B) << BIT_SHIFT_NETYPE2_8814B)\n#define BITS_NETYPE2_8814B (BIT_MASK_NETYPE2_8814B << BIT_SHIFT_NETYPE2_8814B)\n#define BIT_CLEAR_NETYPE2_8814B(x) ((x) & (~BITS_NETYPE2_8814B))\n#define BIT_GET_NETYPE2_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE2_8814B) & BIT_MASK_NETYPE2_8814B)\n#define BIT_SET_NETYPE2_8814B(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE2_8814B(x) | BIT_NETYPE2_8814B(v))\n\n/* 2 REG_TC9_CTRL_8814B */\n#define BIT_TC9INT_EN_8814B BIT(26)\n#define BIT_TC9MODE_8814B BIT(25)\n#define BIT_TC9EN_8814B BIT(24)\n\n#define BIT_SHIFT_TC9DATA_8814B 0\n#define BIT_MASK_TC9DATA_8814B 0xffffff\n#define BIT_TC9DATA_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_TC9DATA_8814B) << BIT_SHIFT_TC9DATA_8814B)\n#define BITS_TC9DATA_8814B (BIT_MASK_TC9DATA_8814B << BIT_SHIFT_TC9DATA_8814B)\n#define BIT_CLEAR_TC9DATA_8814B(x) ((x) & (~BITS_TC9DATA_8814B))\n#define BIT_GET_TC9DATA_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC9DATA_8814B) & BIT_MASK_TC9DATA_8814B)\n#define BIT_SET_TC9DATA_8814B(x, v)                                            \\\n\t(BIT_CLEAR_TC9DATA_8814B(x) | BIT_TC9DATA_8814B(v))\n\n/* 2 REG_TC10_CTRL_8814B */\n#define BIT_TC10INT_EN_8814B BIT(26)\n#define BIT_TC10MODE_8814B BIT(25)\n#define BIT_TC10EN_8814B BIT(24)\n\n#define BIT_SHIFT_TC10DATA_8814B 0\n#define BIT_MASK_TC10DATA_8814B 0xffffff\n#define BIT_TC10DATA_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_TC10DATA_8814B) << BIT_SHIFT_TC10DATA_8814B)\n#define BITS_TC10DATA_8814B                                                    \\\n\t(BIT_MASK_TC10DATA_8814B << BIT_SHIFT_TC10DATA_8814B)\n#define BIT_CLEAR_TC10DATA_8814B(x) ((x) & (~BITS_TC10DATA_8814B))\n#define BIT_GET_TC10DATA_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TC10DATA_8814B) & BIT_MASK_TC10DATA_8814B)\n#define BIT_SET_TC10DATA_8814B(x, v)                                           \\\n\t(BIT_CLEAR_TC10DATA_8814B(x) | BIT_TC10DATA_8814B(v))\n\n/* 2 REG_TC11_CTRL_8814B */\n#define BIT_TC11INT_EN_8814B BIT(26)\n#define BIT_TC11MODE_8814B BIT(25)\n#define BIT_TC11EN_8814B BIT(24)\n\n#define BIT_SHIFT_TC11DATA_8814B 0\n#define BIT_MASK_TC11DATA_8814B 0xffffff\n#define BIT_TC11DATA_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_TC11DATA_8814B) << BIT_SHIFT_TC11DATA_8814B)\n#define BITS_TC11DATA_8814B                                                    \\\n\t(BIT_MASK_TC11DATA_8814B << BIT_SHIFT_TC11DATA_8814B)\n#define BIT_CLEAR_TC11DATA_8814B(x) ((x) & (~BITS_TC11DATA_8814B))\n#define BIT_GET_TC11DATA_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TC11DATA_8814B) & BIT_MASK_TC11DATA_8814B)\n#define BIT_SET_TC11DATA_8814B(x, v)                                           \\\n\t(BIT_CLEAR_TC11DATA_8814B(x) | BIT_TC11DATA_8814B(v))\n\n/* 2 REG_TC12_CTRL_8814B */\n#define BIT_TC12INT_EN_8814B BIT(26)\n#define BIT_TC12MODE_8814B BIT(25)\n#define BIT_TC12EN_8814B BIT(24)\n\n#define BIT_SHIFT_TC12DATA_8814B 0\n#define BIT_MASK_TC12DATA_8814B 0xffffff\n#define BIT_TC12DATA_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_TC12DATA_8814B) << BIT_SHIFT_TC12DATA_8814B)\n#define BITS_TC12DATA_8814B                                                    \\\n\t(BIT_MASK_TC12DATA_8814B << BIT_SHIFT_TC12DATA_8814B)\n#define BIT_CLEAR_TC12DATA_8814B(x) ((x) & (~BITS_TC12DATA_8814B))\n#define BIT_GET_TC12DATA_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TC12DATA_8814B) & BIT_MASK_TC12DATA_8814B)\n#define BIT_SET_TC12DATA_8814B(x, v)                                           \\\n\t(BIT_CLEAR_TC12DATA_8814B(x) | BIT_TC12DATA_8814B(v))\n\n/* 2 REG_FWFF_8814B */\n\n#define BIT_SHIFT_PKTNUM_TH_V1_8814B 24\n#define BIT_MASK_PKTNUM_TH_V1_8814B 0xff\n#define BIT_PKTNUM_TH_V1_8814B(x)                                              \\\n\t(((x) & BIT_MASK_PKTNUM_TH_V1_8814B) << BIT_SHIFT_PKTNUM_TH_V1_8814B)\n#define BITS_PKTNUM_TH_V1_8814B                                                \\\n\t(BIT_MASK_PKTNUM_TH_V1_8814B << BIT_SHIFT_PKTNUM_TH_V1_8814B)\n#define BIT_CLEAR_PKTNUM_TH_V1_8814B(x) ((x) & (~BITS_PKTNUM_TH_V1_8814B))\n#define BIT_GET_PKTNUM_TH_V1_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_PKTNUM_TH_V1_8814B) & BIT_MASK_PKTNUM_TH_V1_8814B)\n#define BIT_SET_PKTNUM_TH_V1_8814B(x, v)                                       \\\n\t(BIT_CLEAR_PKTNUM_TH_V1_8814B(x) | BIT_PKTNUM_TH_V1_8814B(v))\n\n#define BIT_SHIFT_TIMER_TH_8814B 16\n#define BIT_MASK_TIMER_TH_8814B 0xff\n#define BIT_TIMER_TH_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_TIMER_TH_8814B) << BIT_SHIFT_TIMER_TH_8814B)\n#define BITS_TIMER_TH_8814B                                                    \\\n\t(BIT_MASK_TIMER_TH_8814B << BIT_SHIFT_TIMER_TH_8814B)\n#define BIT_CLEAR_TIMER_TH_8814B(x) ((x) & (~BITS_TIMER_TH_8814B))\n#define BIT_GET_TIMER_TH_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TIMER_TH_8814B) & BIT_MASK_TIMER_TH_8814B)\n#define BIT_SET_TIMER_TH_8814B(x, v)                                           \\\n\t(BIT_CLEAR_TIMER_TH_8814B(x) | BIT_TIMER_TH_8814B(v))\n\n#define BIT_SHIFT_RXPKT1ENADDR_8814B 0\n#define BIT_MASK_RXPKT1ENADDR_8814B 0xffff\n#define BIT_RXPKT1ENADDR_8814B(x)                                              \\\n\t(((x) & BIT_MASK_RXPKT1ENADDR_8814B) << BIT_SHIFT_RXPKT1ENADDR_8814B)\n#define BITS_RXPKT1ENADDR_8814B                                                \\\n\t(BIT_MASK_RXPKT1ENADDR_8814B << BIT_SHIFT_RXPKT1ENADDR_8814B)\n#define BIT_CLEAR_RXPKT1ENADDR_8814B(x) ((x) & (~BITS_RXPKT1ENADDR_8814B))\n#define BIT_GET_RXPKT1ENADDR_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXPKT1ENADDR_8814B) & BIT_MASK_RXPKT1ENADDR_8814B)\n#define BIT_SET_RXPKT1ENADDR_8814B(x, v)                                       \\\n\t(BIT_CLEAR_RXPKT1ENADDR_8814B(x) | BIT_RXPKT1ENADDR_8814B(v))\n\n/* 2 REG_RXFF_PTR_V1_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_RXFF0_RDPTR_V2_8814B 0\n#define BIT_MASK_RXFF0_RDPTR_V2_8814B 0x3ffff\n#define BIT_RXFF0_RDPTR_V2_8814B(x)                                            \\\n\t(((x) & BIT_MASK_RXFF0_RDPTR_V2_8814B)                                 \\\n\t << BIT_SHIFT_RXFF0_RDPTR_V2_8814B)\n#define BITS_RXFF0_RDPTR_V2_8814B                                              \\\n\t(BIT_MASK_RXFF0_RDPTR_V2_8814B << BIT_SHIFT_RXFF0_RDPTR_V2_8814B)\n#define BIT_CLEAR_RXFF0_RDPTR_V2_8814B(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8814B))\n#define BIT_GET_RXFF0_RDPTR_V2_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8814B) &                             \\\n\t BIT_MASK_RXFF0_RDPTR_V2_8814B)\n#define BIT_SET_RXFF0_RDPTR_V2_8814B(x, v)                                     \\\n\t(BIT_CLEAR_RXFF0_RDPTR_V2_8814B(x) | BIT_RXFF0_RDPTR_V2_8814B(v))\n\n/* 2 REG_RXFF_WTR_V1_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_RXFF0_WTPTR_V2_8814B 0\n#define BIT_MASK_RXFF0_WTPTR_V2_8814B 0x3ffff\n#define BIT_RXFF0_WTPTR_V2_8814B(x)                                            \\\n\t(((x) & BIT_MASK_RXFF0_WTPTR_V2_8814B)                                 \\\n\t << BIT_SHIFT_RXFF0_WTPTR_V2_8814B)\n#define BITS_RXFF0_WTPTR_V2_8814B                                              \\\n\t(BIT_MASK_RXFF0_WTPTR_V2_8814B << BIT_SHIFT_RXFF0_WTPTR_V2_8814B)\n#define BIT_CLEAR_RXFF0_WTPTR_V2_8814B(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8814B))\n#define BIT_GET_RXFF0_WTPTR_V2_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8814B) &                             \\\n\t BIT_MASK_RXFF0_WTPTR_V2_8814B)\n#define BIT_SET_RXFF0_WTPTR_V2_8814B(x, v)                                     \\\n\t(BIT_CLEAR_RXFF0_WTPTR_V2_8814B(x) | BIT_RXFF0_WTPTR_V2_8814B(v))\n\n/* 2 REG_FE2IMR_8814B */\n#define BIT__FE4ISR__IND_MSK_8814B BIT(29)\n#define BIT_FS_TXSC_DESC_DONE_INT_EN_8814B BIT(28)\n#define BIT_FS_TXSC_BKDONE_INT_EN_8814B BIT(27)\n#define BIT_FS_TXSC_BEDONE_INT_EN_8814B BIT(26)\n#define BIT_FS_TXSC_VIDONE_INT_EN_8814B BIT(25)\n#define BIT_FS_TXSC_VODONE_INT_EN_8814B BIT(24)\n#define BIT_FS_ATIM_MB7_INT_EN_8814B BIT(23)\n#define BIT_FS_ATIM_MB6_INT_EN_8814B BIT(22)\n#define BIT_FS_ATIM_MB5_INT_EN_8814B BIT(21)\n#define BIT_FS_ATIM_MB4_INT_EN_8814B BIT(20)\n#define BIT_FS_ATIM_MB3_INT_EN_8814B BIT(19)\n#define BIT_FS_ATIM_MB2_INT_EN_8814B BIT(18)\n#define BIT_FS_ATIM_MB1_INT_EN_8814B BIT(17)\n#define BIT_FS_ATIM_MB0_INT_EN_8814B BIT(16)\n#define BIT_FS_TBTT4INT_EN_8814B BIT(11)\n#define BIT_FS_TBTT3INT_EN_8814B BIT(10)\n#define BIT_FS_TBTT2INT_EN_8814B BIT(9)\n#define BIT_FS_TBTT1INT_EN_8814B BIT(8)\n#define BIT_FS_TBTT0_MB7INT_EN_8814B BIT(7)\n#define BIT_FS_TBTT0_MB6INT_EN_8814B BIT(6)\n#define BIT_FS_TBTT0_MB5INT_EN_8814B BIT(5)\n#define BIT_FS_TBTT0_MB4INT_EN_8814B BIT(4)\n#define BIT_FS_TBTT0_MB3INT_EN_8814B BIT(3)\n#define BIT_FS_TBTT0_MB2INT_EN_8814B BIT(2)\n#define BIT_FS_TBTT0_MB1INT_EN_8814B BIT(1)\n#define BIT_FS_TBTT0_INT_EN_8814B BIT(0)\n\n/* 2 REG_FE2ISR_8814B */\n#define BIT__FE4ISR__IND_INT_8814B BIT(29)\n#define BIT_FS_TXSC_DESC_DONE_INT_8814B BIT(28)\n#define BIT_FS_TXSC_BKDONE_INT_8814B BIT(27)\n#define BIT_FS_TXSC_BEDONE_INT_8814B BIT(26)\n#define BIT_FS_TXSC_VIDONE_INT_8814B BIT(25)\n#define BIT_FS_TXSC_VODONE_INT_8814B BIT(24)\n#define BIT_FS_ATIM_MB7_INT_8814B BIT(23)\n#define BIT_FS_ATIM_MB6_INT_8814B BIT(22)\n#define BIT_FS_ATIM_MB5_INT_8814B BIT(21)\n#define BIT_FS_ATIM_MB4_INT_8814B BIT(20)\n#define BIT_FS_ATIM_MB3_INT_8814B BIT(19)\n#define BIT_FS_ATIM_MB2_INT_8814B BIT(18)\n#define BIT_FS_ATIM_MB1_INT_8814B BIT(17)\n#define BIT_FS_ATIM_MB0_INT_8814B BIT(16)\n#define BIT_FS_TBTT4INT_8814B BIT(11)\n#define BIT_FS_TBTT3INT_8814B BIT(10)\n#define BIT_FS_TBTT2INT_8814B BIT(9)\n#define BIT_FS_TBTT1INT_8814B BIT(8)\n#define BIT_FS_TBTT0_MB7INT_8814B BIT(7)\n#define BIT_FS_TBTT0_MB6INT_8814B BIT(6)\n#define BIT_FS_TBTT0_MB5INT_8814B BIT(5)\n#define BIT_FS_TBTT0_MB4INT_8814B BIT(4)\n#define BIT_FS_TBTT0_MB3INT_8814B BIT(3)\n#define BIT_FS_TBTT0_MB2INT_8814B BIT(2)\n#define BIT_FS_TBTT0_MB1INT_8814B BIT(1)\n#define BIT_FS_TBTT0_INT_8814B BIT(0)\n\n/* 2 REG_FE3IMR_8814B */\n#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN_8814B BIT(31)\n#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN_8814B BIT(30)\n#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN_8814B BIT(29)\n#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN_8814B BIT(28)\n#define BIT_FS_BCNDMA4_INT_EN_8814B BIT(27)\n#define BIT_FS_BCNDMA3_INT_EN_8814B BIT(26)\n#define BIT_FS_BCNDMA2_INT_EN_8814B BIT(25)\n#define BIT_FS_BCNDMA1_INT_EN_8814B BIT(24)\n#define BIT_FS_BCNDMA0_MB7_INT_EN_8814B BIT(23)\n#define BIT_FS_BCNDMA0_MB6_INT_EN_8814B BIT(22)\n#define BIT_FS_BCNDMA0_MB5_INT_EN_8814B BIT(21)\n#define BIT_FS_BCNDMA0_MB4_INT_EN_8814B BIT(20)\n#define BIT_FS_BCNDMA0_MB3_INT_EN_8814B BIT(19)\n#define BIT_FS_BCNDMA0_MB2_INT_EN_8814B BIT(18)\n#define BIT_FS_BCNDMA0_MB1_INT_EN_8814B BIT(17)\n#define BIT_FS_BCNDMA0_INT_EN_8814B BIT(16)\n#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8814B BIT(15)\n#define BIT_FS_BCNERLY4_INT_EN_8814B BIT(11)\n#define BIT_FS_BCNERLY3_INT_EN_8814B BIT(10)\n#define BIT_FS_BCNERLY2_INT_EN_8814B BIT(9)\n#define BIT_FS_BCNERLY1_INT_EN_8814B BIT(8)\n#define BIT_FS_BCNERLY0_MB7INT_EN_8814B BIT(7)\n#define BIT_FS_BCNERLY0_MB6INT_EN_8814B BIT(6)\n#define BIT_FS_BCNERLY0_MB5INT_EN_8814B BIT(5)\n#define BIT_FS_BCNERLY0_MB4INT_EN_8814B BIT(4)\n#define BIT_FS_BCNERLY0_MB3INT_EN_8814B BIT(3)\n#define BIT_FS_BCNERLY0_MB2INT_EN_8814B BIT(2)\n#define BIT_FS_BCNERLY0_MB1INT_EN_8814B BIT(1)\n#define BIT_FS_BCNERLY0_INT_EN_8814B BIT(0)\n\n/* 2 REG_FE3ISR_8814B */\n#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT_8814B BIT(31)\n#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT_8814B BIT(30)\n#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT_8814B BIT(29)\n#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT_8814B BIT(28)\n#define BIT_FS_BCNDMA4_INT_8814B BIT(27)\n#define BIT_FS_BCNDMA3_INT_8814B BIT(26)\n#define BIT_FS_BCNDMA2_INT_8814B BIT(25)\n#define BIT_FS_BCNDMA1_INT_8814B BIT(24)\n#define BIT_FS_BCNDMA0_MB7_INT_8814B BIT(23)\n#define BIT_FS_BCNDMA0_MB6_INT_8814B BIT(22)\n#define BIT_FS_BCNDMA0_MB5_INT_8814B BIT(21)\n#define BIT_FS_BCNDMA0_MB4_INT_8814B BIT(20)\n#define BIT_FS_BCNDMA0_MB3_INT_8814B BIT(19)\n#define BIT_FS_BCNDMA0_MB2_INT_8814B BIT(18)\n#define BIT_FS_BCNDMA0_MB1_INT_8814B BIT(17)\n#define BIT_FS_BCNDMA0_INT_8814B BIT(16)\n#define BIT_FS_MTI_BCNIVLEAR_INT_8814B BIT(15)\n#define BIT_FS_BCNERLY4_INT_8814B BIT(11)\n#define BIT_FS_BCNERLY3_INT_8814B BIT(10)\n#define BIT_FS_BCNERLY2_INT_8814B BIT(9)\n#define BIT_FS_BCNERLY1_INT_8814B BIT(8)\n#define BIT_FS_BCNERLY0_MB7INT_8814B BIT(7)\n#define BIT_FS_BCNERLY0_MB6INT_8814B BIT(6)\n#define BIT_FS_BCNERLY0_MB5INT_8814B BIT(5)\n#define BIT_FS_BCNERLY0_MB4INT_8814B BIT(4)\n#define BIT_FS_BCNERLY0_MB3INT_8814B BIT(3)\n#define BIT_FS_BCNERLY0_MB2INT_8814B BIT(2)\n#define BIT_FS_BCNERLY0_MB1INT_8814B BIT(1)\n#define BIT_FS_BCNERLY0_INT_8814B BIT(0)\n\n/* 2 REG_FE4IMR_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_FS_CLI3_TXPKTIN_INT_EN_8814B BIT(19)\n#define BIT_FS_CLI2_TXPKTIN_INT_EN_8814B BIT(18)\n#define BIT_FS_CLI1_TXPKTIN_INT_EN_8814B BIT(17)\n#define BIT_FS_CLI0_TXPKTIN_INT_EN_8814B BIT(16)\n#define BIT_FS_CLI3_RX_UMD0_INT_EN_8814B BIT(15)\n#define BIT_FS_CLI3_RX_UMD1_INT_EN_8814B BIT(14)\n#define BIT_FS_CLI3_RX_BMD0_INT_EN_8814B BIT(13)\n#define BIT_FS_CLI3_RX_BMD1_INT_EN_8814B BIT(12)\n#define BIT_FS_CLI2_RX_UMD0_INT_EN_8814B BIT(11)\n#define BIT_FS_CLI2_RX_UMD1_INT_EN_8814B BIT(10)\n#define BIT_FS_CLI2_RX_BMD0_INT_EN_8814B BIT(9)\n#define BIT_FS_CLI2_RX_BMD1_INT_EN_8814B BIT(8)\n#define BIT_FS_CLI1_RX_UMD0_INT_EN_8814B BIT(7)\n#define BIT_FS_CLI1_RX_UMD1_INT_EN_8814B BIT(6)\n#define BIT_FS_CLI1_RX_BMD0_INT_EN_8814B BIT(5)\n#define BIT_FS_CLI1_RX_BMD1_INT_EN_8814B BIT(4)\n#define BIT_FS_CLI0_RX_UMD0_INT_EN_8814B BIT(3)\n#define BIT_FS_CLI0_RX_UMD1_INT_EN_8814B BIT(2)\n#define BIT_FS_CLI0_RX_BMD0_INT_EN_8814B BIT(1)\n#define BIT_FS_CLI0_RX_BMD1_INT_EN_8814B BIT(0)\n\n/* 2 REG_FE4ISR_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_P2P_PWROFF_NOA2_ERLY_INT_8814B BIT(22)\n#define BIT_P2P_PWROFF_NOA1_ERLY_INT_8814B BIT(21)\n#define BIT_P2P_PWROFF_NOA0_ERLY_INT_8814B BIT(20)\n#define BIT_FS_CLI3_TXPKTIN_INT_8814B BIT(19)\n#define BIT_FS_CLI2_TXPKTIN_INT_8814B BIT(18)\n#define BIT_FS_CLI1_TXPKTIN_INT_8814B BIT(17)\n#define BIT_FS_CLI0_TXPKTIN_INT_8814B BIT(16)\n#define BIT_FS_CLI3_RX_UMD0_INT_8814B BIT(15)\n#define BIT_FS_CLI3_RX_UMD1_INT_8814B BIT(14)\n#define BIT_FS_CLI3_RX_BMD0_INT_8814B BIT(13)\n#define BIT_FS_CLI3_RX_BMD1_INT_8814B BIT(12)\n#define BIT_FS_CLI2_RX_UMD0_INT_8814B BIT(11)\n#define BIT_FS_CLI2_RX_UMD1_INT_8814B BIT(10)\n#define BIT_FS_CLI2_RX_BMD0_INT_8814B BIT(9)\n#define BIT_FS_CLI2_RX_BMD1_INT_8814B BIT(8)\n#define BIT_FS_CLI1_RX_UMD0_INT_8814B BIT(7)\n#define BIT_FS_CLI1_RX_UMD1_INT_8814B BIT(6)\n#define BIT_FS_CLI1_RX_BMD0_INT_8814B BIT(5)\n#define BIT_FS_CLI1_RX_BMD1_INT_8814B BIT(4)\n#define BIT_FS_CLI0_RX_UMD0_INT_8814B BIT(3)\n#define BIT_FS_CLI0_RX_UMD1_INT_8814B BIT(2)\n#define BIT_FS_CLI0_RX_BMD0_INT_8814B BIT(1)\n#define BIT_FS_CLI0_RX_BMD1_INT_8814B BIT(0)\n\n/* 2 REG_FT1IMR_8814B */\n#define BIT__FT2ISR__IND_MSK_8814B BIT(30)\n#define BIT_FTM_PTT_INT_EN_8814B BIT(29)\n#define BIT_RXFTMREQ_INT_EN_8814B BIT(28)\n#define BIT_RXFTM_INT_EN_8814B BIT(27)\n#define BIT_TXFTM_INT_EN_8814B BIT(26)\n#define BIT_FS_H2C_CMD_OK_INT_EN_8814B BIT(25)\n#define BIT_FS_H2C_CMD_FULL_INT_EN_8814B BIT(24)\n#define BIT_FS_MACID_SEARCH_FAIL_INT_EN_8814B BIT(22)\n#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8814B BIT(21)\n#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8814B BIT(20)\n#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8814B BIT(19)\n#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8814B BIT(18)\n#define BIT_FS_CTWEND2_INT_EN_8814B BIT(17)\n#define BIT_FS_CTWEND1_INT_EN_8814B BIT(16)\n#define BIT_FS_CTWEND0_INT_EN_8814B BIT(15)\n#define BIT_FS_TX_NULL1_INT_EN_8814B BIT(14)\n#define BIT_FS_TX_NULL0_INT_EN_8814B BIT(13)\n#define BIT_FS_TSF_BIT32_TOGGLE_EN_8814B BIT(12)\n#define BIT_FS_P2P_RFON2_INT_EN_8814B BIT(11)\n#define BIT_FS_P2P_RFOFF2_INT_EN_8814B BIT(10)\n#define BIT_FS_P2P_RFON1_INT_EN_8814B BIT(9)\n#define BIT_FS_P2P_RFOFF1_INT_EN_8814B BIT(8)\n#define BIT_FS_P2P_RFON0_INT_EN_8814B BIT(7)\n#define BIT_FS_P2P_RFOFF0_INT_EN_8814B BIT(6)\n#define BIT_FS_RX_UAPSDMD1_EN_8814B BIT(5)\n#define BIT_FS_RX_UAPSDMD0_EN_8814B BIT(4)\n#define BIT_FS_TRIGGER_PKT_EN_8814B BIT(3)\n#define BIT_FS_EOSP_INT_EN_8814B BIT(2)\n#define BIT_FS_RPWM2_INT_EN_8814B BIT(1)\n#define BIT_FS_RPWM_INT_EN_8814B BIT(0)\n\n/* 2 REG_FT1ISR_8814B */\n#define BIT__FT2ISR__IND_INT_8814B BIT(30)\n#define BIT_FTM_PTT_INT_8814B BIT(29)\n#define BIT_RXFTMREQ_INT_8814B BIT(28)\n#define BIT_RXFTM_INT_8814B BIT(27)\n#define BIT_TXFTM_INT_8814B BIT(26)\n#define BIT_FS_H2C_CMD_OK_INT_8814B BIT(25)\n#define BIT_FS_H2C_CMD_FULL_INT_8814B BIT(24)\n#define BIT_FS_MACID_SEARCH_FAIL_INT_8814B BIT(22)\n#define BIT_FS_MACID_PWRCHANGE3_INT_8814B BIT(21)\n#define BIT_FS_MACID_PWRCHANGE2_INT_8814B BIT(20)\n#define BIT_FS_MACID_PWRCHANGE1_INT_8814B BIT(19)\n#define BIT_FS_MACID_PWRCHANGE0_INT_8814B BIT(18)\n#define BIT_FS_CTWEND2_INT_8814B BIT(17)\n#define BIT_FS_CTWEND1_INT_8814B BIT(16)\n#define BIT_FS_CTWEND0_INT_8814B BIT(15)\n#define BIT_FS_TX_NULL1_INT_8814B BIT(14)\n#define BIT_FS_TX_NULL0_INT_8814B BIT(13)\n#define BIT_FS_TSF_BIT32_TOGGLE_INT_8814B BIT(12)\n#define BIT_FS_P2P_RFON2_INT_8814B BIT(11)\n#define BIT_FS_P2P_RFOFF2_INT_8814B BIT(10)\n#define BIT_FS_P2P_RFON1_INT_8814B BIT(9)\n#define BIT_FS_P2P_RFOFF1_INT_8814B BIT(8)\n#define BIT_FS_P2P_RFON0_INT_8814B BIT(7)\n#define BIT_FS_P2P_RFOFF0_INT_8814B BIT(6)\n#define BIT_FS_RX_UAPSDMD1_INT_8814B BIT(5)\n#define BIT_FS_RX_UAPSDMD0_INT_8814B BIT(4)\n#define BIT_FS_TRIGGER_PKT_INT_8814B BIT(3)\n#define BIT_FS_EOSP_INT_8814B BIT(2)\n#define BIT_FS_RPWM2_INT_8814B BIT(1)\n#define BIT_FS_RPWM_INT_8814B BIT(0)\n\n/* 2 REG_SPWR0_8814B */\n\n#define BIT_SHIFT_MID_31TO0_8814B 0\n#define BIT_MASK_MID_31TO0_8814B 0xffffffffL\n#define BIT_MID_31TO0_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_MID_31TO0_8814B) << BIT_SHIFT_MID_31TO0_8814B)\n#define BITS_MID_31TO0_8814B                                                   \\\n\t(BIT_MASK_MID_31TO0_8814B << BIT_SHIFT_MID_31TO0_8814B)\n#define BIT_CLEAR_MID_31TO0_8814B(x) ((x) & (~BITS_MID_31TO0_8814B))\n#define BIT_GET_MID_31TO0_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_MID_31TO0_8814B) & BIT_MASK_MID_31TO0_8814B)\n#define BIT_SET_MID_31TO0_8814B(x, v)                                          \\\n\t(BIT_CLEAR_MID_31TO0_8814B(x) | BIT_MID_31TO0_8814B(v))\n\n/* 2 REG_SPWR1_8814B */\n\n#define BIT_SHIFT_MID_63TO32_8814B 0\n#define BIT_MASK_MID_63TO32_8814B 0xffffffffL\n#define BIT_MID_63TO32_8814B(x)                                                \\\n\t(((x) & BIT_MASK_MID_63TO32_8814B) << BIT_SHIFT_MID_63TO32_8814B)\n#define BITS_MID_63TO32_8814B                                                  \\\n\t(BIT_MASK_MID_63TO32_8814B << BIT_SHIFT_MID_63TO32_8814B)\n#define BIT_CLEAR_MID_63TO32_8814B(x) ((x) & (~BITS_MID_63TO32_8814B))\n#define BIT_GET_MID_63TO32_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_MID_63TO32_8814B) & BIT_MASK_MID_63TO32_8814B)\n#define BIT_SET_MID_63TO32_8814B(x, v)                                         \\\n\t(BIT_CLEAR_MID_63TO32_8814B(x) | BIT_MID_63TO32_8814B(v))\n\n/* 2 REG_SPWR2_8814B */\n\n#define BIT_SHIFT_MID_95O64_8814B 0\n#define BIT_MASK_MID_95O64_8814B 0xffffffffL\n#define BIT_MID_95O64_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_MID_95O64_8814B) << BIT_SHIFT_MID_95O64_8814B)\n#define BITS_MID_95O64_8814B                                                   \\\n\t(BIT_MASK_MID_95O64_8814B << BIT_SHIFT_MID_95O64_8814B)\n#define BIT_CLEAR_MID_95O64_8814B(x) ((x) & (~BITS_MID_95O64_8814B))\n#define BIT_GET_MID_95O64_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_MID_95O64_8814B) & BIT_MASK_MID_95O64_8814B)\n#define BIT_SET_MID_95O64_8814B(x, v)                                          \\\n\t(BIT_CLEAR_MID_95O64_8814B(x) | BIT_MID_95O64_8814B(v))\n\n/* 2 REG_SPWR3_8814B */\n\n#define BIT_SHIFT_MID_127TO96_8814B 0\n#define BIT_MASK_MID_127TO96_8814B 0xffffffffL\n#define BIT_MID_127TO96_8814B(x)                                               \\\n\t(((x) & BIT_MASK_MID_127TO96_8814B) << BIT_SHIFT_MID_127TO96_8814B)\n#define BITS_MID_127TO96_8814B                                                 \\\n\t(BIT_MASK_MID_127TO96_8814B << BIT_SHIFT_MID_127TO96_8814B)\n#define BIT_CLEAR_MID_127TO96_8814B(x) ((x) & (~BITS_MID_127TO96_8814B))\n#define BIT_GET_MID_127TO96_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_MID_127TO96_8814B) & BIT_MASK_MID_127TO96_8814B)\n#define BIT_SET_MID_127TO96_8814B(x, v)                                        \\\n\t(BIT_CLEAR_MID_127TO96_8814B(x) | BIT_MID_127TO96_8814B(v))\n\n/* 2 REG_POWSEQ_8814B */\n\n#define BIT_SHIFT_SEQNUM_MID_8814B 16\n#define BIT_MASK_SEQNUM_MID_8814B 0xffff\n#define BIT_SEQNUM_MID_8814B(x)                                                \\\n\t(((x) & BIT_MASK_SEQNUM_MID_8814B) << BIT_SHIFT_SEQNUM_MID_8814B)\n#define BITS_SEQNUM_MID_8814B                                                  \\\n\t(BIT_MASK_SEQNUM_MID_8814B << BIT_SHIFT_SEQNUM_MID_8814B)\n#define BIT_CLEAR_SEQNUM_MID_8814B(x) ((x) & (~BITS_SEQNUM_MID_8814B))\n#define BIT_GET_SEQNUM_MID_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_SEQNUM_MID_8814B) & BIT_MASK_SEQNUM_MID_8814B)\n#define BIT_SET_SEQNUM_MID_8814B(x, v)                                         \\\n\t(BIT_CLEAR_SEQNUM_MID_8814B(x) | BIT_SEQNUM_MID_8814B(v))\n\n#define BIT_SHIFT_REF_MID_8814B 0\n#define BIT_MASK_REF_MID_8814B 0x7f\n#define BIT_REF_MID_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_REF_MID_8814B) << BIT_SHIFT_REF_MID_8814B)\n#define BITS_REF_MID_8814B (BIT_MASK_REF_MID_8814B << BIT_SHIFT_REF_MID_8814B)\n#define BIT_CLEAR_REF_MID_8814B(x) ((x) & (~BITS_REF_MID_8814B))\n#define BIT_GET_REF_MID_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_REF_MID_8814B) & BIT_MASK_REF_MID_8814B)\n#define BIT_SET_REF_MID_8814B(x, v)                                            \\\n\t(BIT_CLEAR_REF_MID_8814B(x) | BIT_REF_MID_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_TC7_CTRL_V1_8814B */\n#define BIT_TC7INT_EN_8814B BIT(26)\n#define BIT_TC7MODE_8814B BIT(25)\n#define BIT_TC7EN_8814B BIT(24)\n\n#define BIT_SHIFT_TC7DATA_8814B 0\n#define BIT_MASK_TC7DATA_8814B 0xffffff\n#define BIT_TC7DATA_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_TC7DATA_8814B) << BIT_SHIFT_TC7DATA_8814B)\n#define BITS_TC7DATA_8814B (BIT_MASK_TC7DATA_8814B << BIT_SHIFT_TC7DATA_8814B)\n#define BIT_CLEAR_TC7DATA_8814B(x) ((x) & (~BITS_TC7DATA_8814B))\n#define BIT_GET_TC7DATA_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC7DATA_8814B) & BIT_MASK_TC7DATA_8814B)\n#define BIT_SET_TC7DATA_8814B(x, v)                                            \\\n\t(BIT_CLEAR_TC7DATA_8814B(x) | BIT_TC7DATA_8814B(v))\n\n/* 2 REG_TC8_CTRL_V1_8814B */\n#define BIT_TC8INT_EN_8814B BIT(26)\n#define BIT_TC8MODE_8814B BIT(25)\n#define BIT_TC8EN_8814B BIT(24)\n\n#define BIT_SHIFT_TC8DATA_8814B 0\n#define BIT_MASK_TC8DATA_8814B 0xffffff\n#define BIT_TC8DATA_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_TC8DATA_8814B) << BIT_SHIFT_TC8DATA_8814B)\n#define BITS_TC8DATA_8814B (BIT_MASK_TC8DATA_8814B << BIT_SHIFT_TC8DATA_8814B)\n#define BIT_CLEAR_TC8DATA_8814B(x) ((x) & (~BITS_TC8DATA_8814B))\n#define BIT_GET_TC8DATA_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC8DATA_8814B) & BIT_MASK_TC8DATA_8814B)\n#define BIT_SET_TC8DATA_8814B(x, v)                                            \\\n\t(BIT_CLEAR_TC8DATA_8814B(x) | BIT_TC8DATA_8814B(v))\n\n/* 2 REG_RX_BCN_TBTT_ITVL0_8814B */\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B 24\n#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B 0xff\n#define BIT_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x)                                  \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B)                       \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B)\n#define BITS_RX_BCN_TBTT_ITVL_CLIENT2_8814B                                    \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B                               \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x)                            \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2_8814B))\n#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x)                              \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B) &                   \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B)\n#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x, v)                           \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x) |                         \\\n\t BIT_RX_BCN_TBTT_ITVL_CLIENT2_8814B(v))\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B 16\n#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B 0xff\n#define BIT_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x)                                  \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B)                       \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B)\n#define BITS_RX_BCN_TBTT_ITVL_CLIENT1_8814B                                    \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B                               \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x)                            \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1_8814B))\n#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x)                              \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B) &                   \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B)\n#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x, v)                           \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x) |                         \\\n\t BIT_RX_BCN_TBTT_ITVL_CLIENT1_8814B(v))\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B 8\n#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B 0xff\n#define BIT_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x)                                  \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B)                       \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B)\n#define BITS_RX_BCN_TBTT_ITVL_CLIENT0_8814B                                    \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B                               \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x)                            \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0_8814B))\n#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x)                              \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B) &                   \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B)\n#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x, v)                           \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x) |                         \\\n\t BIT_RX_BCN_TBTT_ITVL_CLIENT0_8814B(v))\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B 0\n#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B 0xff\n#define BIT_RX_BCN_TBTT_ITVL_PORT0_8814B(x)                                    \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B)                         \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B)\n#define BITS_RX_BCN_TBTT_ITVL_PORT0_8814B                                      \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B                                 \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8814B(x)                              \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0_8814B))\n#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0_8814B(x)                                \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B) &                     \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B)\n#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0_8814B(x, v)                             \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8814B(x) |                           \\\n\t BIT_RX_BCN_TBTT_ITVL_PORT0_8814B(v))\n\n/* 2 REG_RX_BCN_TBTT_ITVL1_8814B */\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B 0\n#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B 0xff\n#define BIT_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x)                                  \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B)                       \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B)\n#define BITS_RX_BCN_TBTT_ITVL_CLIENT3_8814B                                    \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B                               \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x)                            \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3_8814B))\n#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x)                              \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B) &                   \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B)\n#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x, v)                           \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x) |                         \\\n\t BIT_RX_BCN_TBTT_ITVL_CLIENT3_8814B(v))\n\n/* 2 REG_FWIMR1_8814B */\n#define BIT_FS_ATIM_MB15_INT_EN_8814B BIT(31)\n#define BIT_FS_ATIM_MB14_INT_EN_8814B BIT(30)\n#define BIT_FS_ATIM_MB13_INT_EN_8814B BIT(29)\n#define BIT_FS_ATIM_MB12_INT_EN_8814B BIT(28)\n#define BIT_FS_ATIM_MB11_INT_EN_8814B BIT(27)\n#define BIT_FS_ATIM_MB10_INT_EN_8814B BIT(26)\n#define BIT_FS_ATIM_MB9_INT_EN_8814B BIT(25)\n#define BIT_FS_ATIM_MB8_INT_EN_8814B BIT(24)\n#define BIT_FS_TXBCNERR_MB15_INT_EN_8814B BIT(23)\n#define BIT_FS_TXBCNERR_MB14_INT_EN_8814B BIT(22)\n#define BIT_FS_TXBCNERR_MB13_INT_EN_8814B BIT(21)\n#define BIT_FS_TXBCNERR_MB12_INT_EN_8814B BIT(20)\n#define BIT_FS_TXBCNERR_MB11_INT_EN_8814B BIT(19)\n#define BIT_FS_TXBCNERR_MB10_INT_EN_8814B BIT(18)\n#define BIT_FS_TXBCNERR_MB9_INT_EN_8814B BIT(17)\n#define BIT_FS_TXBCNERR_MB8_INT_EN_8814B BIT(16)\n#define BIT_FS_TXBCNOK_MB15_INT_EN_8814B BIT(15)\n#define BIT_FS_TXBCNOK_MB14_INT_EN_8814B BIT(14)\n#define BIT_FS_TXBCNOK_MB13_INT_EN_8814B BIT(13)\n#define BIT_FS_TXBCNOK_MB12_INT_EN_8814B BIT(12)\n#define BIT_FS_TXBCNOK_MB11_INT_EN_8814B BIT(11)\n#define BIT_FS_TXBCNOK_MB10_INT_EN_8814B BIT(10)\n#define BIT_FS_TXBCNOK_MB9_INT_EN_8814B BIT(9)\n#define BIT_FS_TXBCNOK_MB8_INT_EN_8814B BIT(8)\n#define BIT_FS_BCNERLY0_MB15INT_EN_8814B BIT(7)\n#define BIT_FS_BCNERLY0_MB14INT_EN_8814B BIT(6)\n#define BIT_FS_BCNERLY0_MB13INT_EN_8814B BIT(5)\n#define BIT_FS_BCNERLY0_MB12INT_EN_8814B BIT(4)\n#define BIT_FS_BCNERLY0_MB11INT_EN_8814B BIT(3)\n#define BIT_FS_BCNERLY0_MB10INT_EN_8814B BIT(2)\n#define BIT_FS_BCNERLY0_MB9INT_EN_8814B BIT(1)\n#define BIT_FS_BCNERLY0_MB8INT_EN_8814B BIT(0)\n\n/* 2 REG_FWISR1_8814B */\n#define BIT_FS_ATIM_MB15_INT_8814B BIT(31)\n#define BIT_FS_ATIM_MB14_INT_8814B BIT(30)\n#define BIT_FS_ATIM_MB13_INT_8814B BIT(29)\n#define BIT_FS_ATIM_MB12_INT_8814B BIT(28)\n#define BIT_FS_ATIM_MB11_INT_8814B BIT(27)\n#define BIT_FS_ATIM_MB10_INT_8814B BIT(26)\n#define BIT_FS_ATIM_MB9_INT_8814B BIT(25)\n#define BIT_FS_ATIM_MB8_INT_8814B BIT(24)\n#define BIT_FS_TXBCNERR_MB15_INT_8814B BIT(23)\n#define BIT_FS_TXBCNERR_MB14_INT_8814B BIT(22)\n#define BIT_FS_TXBCNERR_MB13_INT_8814B BIT(21)\n#define BIT_FS_TXBCNERR_MB12_INT_8814B BIT(20)\n#define BIT_FS_TXBCNERR_MB11_INT_8814B BIT(19)\n#define BIT_FS_TXBCNERR_MB10_INT_8814B BIT(18)\n#define BIT_FS_TXBCNERR_MB9_INT_8814B BIT(17)\n#define BIT_FS_TXBCNERR_MB8_INT_8814B BIT(16)\n#define BIT_FS_TXBCNOK_MB15_INT_8814B BIT(15)\n#define BIT_FS_TXBCNOK_MB14_INT_8814B BIT(14)\n#define BIT_FS_TXBCNOK_MB13_INT_8814B BIT(13)\n#define BIT_FS_TXBCNOK_MB12_INT_8814B BIT(12)\n#define BIT_FS_TXBCNOK_MB11_INT_8814B BIT(11)\n#define BIT_FS_TXBCNOK_MB10_INT_8814B BIT(10)\n#define BIT_FS_TXBCNOK_MB9_INT_8814B BIT(9)\n#define BIT_FS_TXBCNOK_MB8_INT_8814B BIT(8)\n#define BIT_FS_BCNERLY0_MB15INT_8814B BIT(7)\n#define BIT_FS_BCNERLY0_MB14INT_8814B BIT(6)\n#define BIT_FS_BCNERLY0_MB13INT_8814B BIT(5)\n#define BIT_FS_BCNERLY0_MB12INT_8814B BIT(4)\n#define BIT_FS_BCNERLY0_MB11INT_8814B BIT(3)\n#define BIT_FS_BCNERLY0_MB10INT_8814B BIT(2)\n#define BIT_FS_BCNERLY0_MB9INT_8814B BIT(1)\n#define BIT_FS_BCNERLY0_MB8INT_8814B BIT(0)\n\n/* 2 REG_FWIMR2_8814B */\n#define BIT_FS_BCNDMA0_MB15_INT_EN_8814B BIT(15)\n#define BIT_FS_BCNDMA0_MB14_INT_EN_8814B BIT(14)\n#define BIT_FS_BCNDMA0_MB13_INT_EN_8814B BIT(13)\n#define BIT_FS_BCNDMA0_MB12_INT_EN_8814B BIT(12)\n#define BIT_FS_BCNDMA0_MB11_INT_EN_8814B BIT(11)\n#define BIT_FS_BCNDMA0_MB10_INT_EN_8814B BIT(10)\n#define BIT_FS_BCNDMA0_MB9_INT_EN_8814B BIT(9)\n#define BIT_FS_BCNDMA0_MB8_INT_EN_8814B BIT(8)\n#define BIT_FS_TBTT0_MB15INT_EN_8814B BIT(7)\n#define BIT_FS_TBTT0_MB14INT_EN_8814B BIT(6)\n#define BIT_FS_TBTT0_MB13INT_EN_8814B BIT(5)\n#define BIT_FS_TBTT0_MB12INT_EN_8814B BIT(4)\n#define BIT_FS_TBTT0_MB11INT_EN_8814B BIT(3)\n#define BIT_FS_TBTT0_MB10INT_EN_8814B BIT(2)\n#define BIT_FS_TBTT0_MB9INT_EN_8814B BIT(1)\n#define BIT_FS_TBTT0_MB8INT_EN_8814B BIT(0)\n\n/* 2 REG_FWISR2_8814B */\n#define BIT_FS_BCNDMA0_MB15_INT_8814B BIT(15)\n#define BIT_FS_BCNDMA0_MB14_INT_8814B BIT(14)\n#define BIT_FS_BCNDMA0_MB13_INT_8814B BIT(13)\n#define BIT_FS_BCNDMA0_MB12_INT_8814B BIT(12)\n#define BIT_FS_BCNDMA0_MB11_INT_8814B BIT(11)\n#define BIT_FS_BCNDMA0_MB10_INT_8814B BIT(10)\n#define BIT_FS_BCNDMA0_MB9_INT_8814B BIT(9)\n#define BIT_FS_BCNDMA0_MB8_INT_8814B BIT(8)\n#define BIT_FS_TBTT0_MB15INT_8814B BIT(7)\n#define BIT_FS_TBTT0_MB14INT_8814B BIT(6)\n#define BIT_FS_TBTT0_MB13INT_8814B BIT(5)\n#define BIT_FS_TBTT0_MB12INT_8814B BIT(4)\n#define BIT_FS_TBTT0_MB11INT_8814B BIT(3)\n#define BIT_FS_TBTT0_MB10INT_8814B BIT(2)\n#define BIT_FS_TBTT0_MB9INT_8814B BIT(1)\n#define BIT_FS_TBTT0_MB8INT_8814B BIT(0)\n\n/* 2 REG_FWIMR3_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_FS_TXBCNOK_PORT4_INT_EN_8814B BIT(11)\n#define BIT_FS_TXBCNOK_PORT3_INT_EN_8814B BIT(10)\n#define BIT_FS_TXBCNOK_PORT2_INT_EN_8814B BIT(9)\n#define BIT_FS_TXBCNOK_PORT1_INT_EN_8814B BIT(8)\n#define BIT_FS_TXBCNERR_PORT4_INT_EN_8814B BIT(7)\n#define BIT_FS_TXBCNERR_PORT3_INT_EN_8814B BIT(6)\n#define BIT_FS_TXBCNERR_PORT2_INT_EN_8814B BIT(5)\n#define BIT_FS_TXBCNERR_PORT1_INT_EN_8814B BIT(4)\n#define BIT_FS_ATIM_PORT4_INT_EN_8814B BIT(3)\n#define BIT_FS_ATIM_PORT3_INT_EN_8814B BIT(2)\n#define BIT_FS_ATIM_PORT2_INT_EN_8814B BIT(1)\n#define BIT_FS_ATIM_PORT1_INT_EN_8814B BIT(0)\n\n/* 2 REG_FWISR3_8814B */\n#define BIT_FS_TXBCNOK_PORT4_INT_8814B BIT(11)\n#define BIT_FS_TXBCNOK_PORT3_INT_8814B BIT(10)\n#define BIT_FS_TXBCNOK_PORT2_INT_8814B BIT(9)\n#define BIT_FS_TXBCNOK_PORT1_INT_8814B BIT(8)\n#define BIT_FS_TXBCNERR_PORT4_INT_8814B BIT(7)\n#define BIT_FS_TXBCNERR_PORT3_INT_8814B BIT(6)\n#define BIT_FS_TXBCNERR_PORT2_INT_8814B BIT(5)\n#define BIT_FS_TXBCNERR_PORT1_INT_8814B BIT(4)\n#define BIT_FS_ATIM_PORT4_INT_8814B BIT(3)\n#define BIT_FS_ATIM_PORT3_INT_8814B BIT(2)\n#define BIT_FS_ATIM_PORT2_INT_8814B BIT(1)\n#define BIT_FS_ATIM_PORT1_INT_8814B BIT(0)\n\n/* 2 REG_SPEED_SENSOR_8814B */\n#define BIT_DSS_1_RST_N_8814B BIT(31)\n#define BIT_DSS_1_SPEED_EN_8814B BIT(30)\n#define BIT_DSS_1_WIRE_SEL_8814B BIT(29)\n#define BIT_DSS_ENCLK_8814B BIT(28)\n\n#define BIT_SHIFT_DSS_1_RO_SEL_8814B 24\n#define BIT_MASK_DSS_1_RO_SEL_8814B 0x7\n#define BIT_DSS_1_RO_SEL_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DSS_1_RO_SEL_8814B) << BIT_SHIFT_DSS_1_RO_SEL_8814B)\n#define BITS_DSS_1_RO_SEL_8814B                                                \\\n\t(BIT_MASK_DSS_1_RO_SEL_8814B << BIT_SHIFT_DSS_1_RO_SEL_8814B)\n#define BIT_CLEAR_DSS_1_RO_SEL_8814B(x) ((x) & (~BITS_DSS_1_RO_SEL_8814B))\n#define BIT_GET_DSS_1_RO_SEL_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DSS_1_RO_SEL_8814B) & BIT_MASK_DSS_1_RO_SEL_8814B)\n#define BIT_SET_DSS_1_RO_SEL_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DSS_1_RO_SEL_8814B(x) | BIT_DSS_1_RO_SEL_8814B(v))\n\n#define BIT_SHIFT_DSS_1_DATA_IN_8814B 0\n#define BIT_MASK_DSS_1_DATA_IN_8814B 0xfffff\n#define BIT_DSS_1_DATA_IN_8814B(x)                                             \\\n\t(((x) & BIT_MASK_DSS_1_DATA_IN_8814B) << BIT_SHIFT_DSS_1_DATA_IN_8814B)\n#define BITS_DSS_1_DATA_IN_8814B                                               \\\n\t(BIT_MASK_DSS_1_DATA_IN_8814B << BIT_SHIFT_DSS_1_DATA_IN_8814B)\n#define BIT_CLEAR_DSS_1_DATA_IN_8814B(x) ((x) & (~BITS_DSS_1_DATA_IN_8814B))\n#define BIT_GET_DSS_1_DATA_IN_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_DSS_1_DATA_IN_8814B) & BIT_MASK_DSS_1_DATA_IN_8814B)\n#define BIT_SET_DSS_1_DATA_IN_8814B(x, v)                                      \\\n\t(BIT_CLEAR_DSS_1_DATA_IN_8814B(x) | BIT_DSS_1_DATA_IN_8814B(v))\n\n/* 2 REG_SPEED_SENSOR1_8814B */\n#define BIT_DSS_1_READY_8814B BIT(31)\n#define BIT_DSS_1_WSORT_GO_8814B BIT(30)\n\n#define BIT_SHIFT_DSS_1_COUNT_OUT_8814B 0\n#define BIT_MASK_DSS_1_COUNT_OUT_8814B 0xfffff\n#define BIT_DSS_1_COUNT_OUT_8814B(x)                                           \\\n\t(((x) & BIT_MASK_DSS_1_COUNT_OUT_8814B)                                \\\n\t << BIT_SHIFT_DSS_1_COUNT_OUT_8814B)\n#define BITS_DSS_1_COUNT_OUT_8814B                                             \\\n\t(BIT_MASK_DSS_1_COUNT_OUT_8814B << BIT_SHIFT_DSS_1_COUNT_OUT_8814B)\n#define BIT_CLEAR_DSS_1_COUNT_OUT_8814B(x) ((x) & (~BITS_DSS_1_COUNT_OUT_8814B))\n#define BIT_GET_DSS_1_COUNT_OUT_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_DSS_1_COUNT_OUT_8814B) &                            \\\n\t BIT_MASK_DSS_1_COUNT_OUT_8814B)\n#define BIT_SET_DSS_1_COUNT_OUT_8814B(x, v)                                    \\\n\t(BIT_CLEAR_DSS_1_COUNT_OUT_8814B(x) | BIT_DSS_1_COUNT_OUT_8814B(v))\n\n/* 2 REG_SPEED_SENSOR2_8814B */\n#define BIT_DSS_2_RST_N_8814B BIT(31)\n#define BIT_DSS_2_SPEED_EN_8814B BIT(30)\n#define BIT_DSS_2_WIRE_SEL_8814B BIT(29)\n#define BIT_DSS_ENCLK_8814B BIT(28)\n\n#define BIT_SHIFT_DSS_2_RO_SEL_8814B 24\n#define BIT_MASK_DSS_2_RO_SEL_8814B 0x7\n#define BIT_DSS_2_RO_SEL_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DSS_2_RO_SEL_8814B) << BIT_SHIFT_DSS_2_RO_SEL_8814B)\n#define BITS_DSS_2_RO_SEL_8814B                                                \\\n\t(BIT_MASK_DSS_2_RO_SEL_8814B << BIT_SHIFT_DSS_2_RO_SEL_8814B)\n#define BIT_CLEAR_DSS_2_RO_SEL_8814B(x) ((x) & (~BITS_DSS_2_RO_SEL_8814B))\n#define BIT_GET_DSS_2_RO_SEL_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DSS_2_RO_SEL_8814B) & BIT_MASK_DSS_2_RO_SEL_8814B)\n#define BIT_SET_DSS_2_RO_SEL_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DSS_2_RO_SEL_8814B(x) | BIT_DSS_2_RO_SEL_8814B(v))\n\n#define BIT_SHIFT_DSS_2_DATA_IN_8814B 0\n#define BIT_MASK_DSS_2_DATA_IN_8814B 0xfffff\n#define BIT_DSS_2_DATA_IN_8814B(x)                                             \\\n\t(((x) & BIT_MASK_DSS_2_DATA_IN_8814B) << BIT_SHIFT_DSS_2_DATA_IN_8814B)\n#define BITS_DSS_2_DATA_IN_8814B                                               \\\n\t(BIT_MASK_DSS_2_DATA_IN_8814B << BIT_SHIFT_DSS_2_DATA_IN_8814B)\n#define BIT_CLEAR_DSS_2_DATA_IN_8814B(x) ((x) & (~BITS_DSS_2_DATA_IN_8814B))\n#define BIT_GET_DSS_2_DATA_IN_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_DSS_2_DATA_IN_8814B) & BIT_MASK_DSS_2_DATA_IN_8814B)\n#define BIT_SET_DSS_2_DATA_IN_8814B(x, v)                                      \\\n\t(BIT_CLEAR_DSS_2_DATA_IN_8814B(x) | BIT_DSS_2_DATA_IN_8814B(v))\n\n/* 2 REG_SPEED_SENSOR3_8814B */\n#define BIT_DSS_2_READY_8814B BIT(31)\n#define BIT_DSS_2_WSORT_GO_8814B BIT(30)\n\n#define BIT_SHIFT_DSS_2_COUNT_OUT_8814B 0\n#define BIT_MASK_DSS_2_COUNT_OUT_8814B 0xfffff\n#define BIT_DSS_2_COUNT_OUT_8814B(x)                                           \\\n\t(((x) & BIT_MASK_DSS_2_COUNT_OUT_8814B)                                \\\n\t << BIT_SHIFT_DSS_2_COUNT_OUT_8814B)\n#define BITS_DSS_2_COUNT_OUT_8814B                                             \\\n\t(BIT_MASK_DSS_2_COUNT_OUT_8814B << BIT_SHIFT_DSS_2_COUNT_OUT_8814B)\n#define BIT_CLEAR_DSS_2_COUNT_OUT_8814B(x) ((x) & (~BITS_DSS_2_COUNT_OUT_8814B))\n#define BIT_GET_DSS_2_COUNT_OUT_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_DSS_2_COUNT_OUT_8814B) &                            \\\n\t BIT_MASK_DSS_2_COUNT_OUT_8814B)\n#define BIT_SET_DSS_2_COUNT_OUT_8814B(x, v)                                    \\\n\t(BIT_CLEAR_DSS_2_COUNT_OUT_8814B(x) | BIT_DSS_2_COUNT_OUT_8814B(v))\n\n/* 2 REG_SPEED_SENSOR4_8814B */\n#define BIT_DSS_3_RST_N_8814B BIT(31)\n#define BIT_DSS_3_SPEED_EN_8814B BIT(30)\n#define BIT_DSS_3_WIRE_SEL_8814B BIT(29)\n#define BIT_DSS_ENCLK_8814B BIT(28)\n\n#define BIT_SHIFT_DSS_3_RO_SEL_8814B 24\n#define BIT_MASK_DSS_3_RO_SEL_8814B 0x7\n#define BIT_DSS_3_RO_SEL_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DSS_3_RO_SEL_8814B) << BIT_SHIFT_DSS_3_RO_SEL_8814B)\n#define BITS_DSS_3_RO_SEL_8814B                                                \\\n\t(BIT_MASK_DSS_3_RO_SEL_8814B << BIT_SHIFT_DSS_3_RO_SEL_8814B)\n#define BIT_CLEAR_DSS_3_RO_SEL_8814B(x) ((x) & (~BITS_DSS_3_RO_SEL_8814B))\n#define BIT_GET_DSS_3_RO_SEL_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DSS_3_RO_SEL_8814B) & BIT_MASK_DSS_3_RO_SEL_8814B)\n#define BIT_SET_DSS_3_RO_SEL_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DSS_3_RO_SEL_8814B(x) | BIT_DSS_3_RO_SEL_8814B(v))\n\n#define BIT_SHIFT_DSS_3_DATA_IN_8814B 0\n#define BIT_MASK_DSS_3_DATA_IN_8814B 0xfffff\n#define BIT_DSS_3_DATA_IN_8814B(x)                                             \\\n\t(((x) & BIT_MASK_DSS_3_DATA_IN_8814B) << BIT_SHIFT_DSS_3_DATA_IN_8814B)\n#define BITS_DSS_3_DATA_IN_8814B                                               \\\n\t(BIT_MASK_DSS_3_DATA_IN_8814B << BIT_SHIFT_DSS_3_DATA_IN_8814B)\n#define BIT_CLEAR_DSS_3_DATA_IN_8814B(x) ((x) & (~BITS_DSS_3_DATA_IN_8814B))\n#define BIT_GET_DSS_3_DATA_IN_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_DSS_3_DATA_IN_8814B) & BIT_MASK_DSS_3_DATA_IN_8814B)\n#define BIT_SET_DSS_3_DATA_IN_8814B(x, v)                                      \\\n\t(BIT_CLEAR_DSS_3_DATA_IN_8814B(x) | BIT_DSS_3_DATA_IN_8814B(v))\n\n/* 2 REG_SPEED_SENSOR5_8814B */\n#define BIT_DSS_3_READY_8814B BIT(31)\n#define BIT_DSS_3_WSORT_GO_8814B BIT(30)\n\n#define BIT_SHIFT_DSS_3_COUNT_OUT_8814B 0\n#define BIT_MASK_DSS_3_COUNT_OUT_8814B 0xfffff\n#define BIT_DSS_3_COUNT_OUT_8814B(x)                                           \\\n\t(((x) & BIT_MASK_DSS_3_COUNT_OUT_8814B)                                \\\n\t << BIT_SHIFT_DSS_3_COUNT_OUT_8814B)\n#define BITS_DSS_3_COUNT_OUT_8814B                                             \\\n\t(BIT_MASK_DSS_3_COUNT_OUT_8814B << BIT_SHIFT_DSS_3_COUNT_OUT_8814B)\n#define BIT_CLEAR_DSS_3_COUNT_OUT_8814B(x) ((x) & (~BITS_DSS_3_COUNT_OUT_8814B))\n#define BIT_GET_DSS_3_COUNT_OUT_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_DSS_3_COUNT_OUT_8814B) &                            \\\n\t BIT_MASK_DSS_3_COUNT_OUT_8814B)\n#define BIT_SET_DSS_3_COUNT_OUT_8814B(x, v)                                    \\\n\t(BIT_CLEAR_DSS_3_COUNT_OUT_8814B(x) | BIT_DSS_3_COUNT_OUT_8814B(v))\n\n/* 2 REG_RXPKTBUF_1_MAX_ADDR_8814B */\n\n#define BIT_SHIFT_RXPKTBUF_SIZE_8814B 30\n#define BIT_MASK_RXPKTBUF_SIZE_8814B 0x3\n#define BIT_RXPKTBUF_SIZE_8814B(x)                                             \\\n\t(((x) & BIT_MASK_RXPKTBUF_SIZE_8814B) << BIT_SHIFT_RXPKTBUF_SIZE_8814B)\n#define BITS_RXPKTBUF_SIZE_8814B                                               \\\n\t(BIT_MASK_RXPKTBUF_SIZE_8814B << BIT_SHIFT_RXPKTBUF_SIZE_8814B)\n#define BIT_CLEAR_RXPKTBUF_SIZE_8814B(x) ((x) & (~BITS_RXPKTBUF_SIZE_8814B))\n#define BIT_GET_RXPKTBUF_SIZE_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXPKTBUF_SIZE_8814B) & BIT_MASK_RXPKTBUF_SIZE_8814B)\n#define BIT_SET_RXPKTBUF_SIZE_8814B(x, v)                                      \\\n\t(BIT_CLEAR_RXPKTBUF_SIZE_8814B(x) | BIT_RXPKTBUF_SIZE_8814B(v))\n\n#define BIT_RXPKTBUF_DBG_SEL_8814B BIT(29)\n\n#define BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B 0\n#define BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B 0x3ffff\n#define BIT_RXPKTBUF_1_MAX_ADDR_8814B(x)                                       \\\n\t(((x) & BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B)                            \\\n\t << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B)\n#define BITS_RXPKTBUF_1_MAX_ADDR_8814B                                         \\\n\t(BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B                                    \\\n\t << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B)\n#define BIT_CLEAR_RXPKTBUF_1_MAX_ADDR_8814B(x)                                 \\\n\t((x) & (~BITS_RXPKTBUF_1_MAX_ADDR_8814B))\n#define BIT_GET_RXPKTBUF_1_MAX_ADDR_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B) &                        \\\n\t BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B)\n#define BIT_SET_RXPKTBUF_1_MAX_ADDR_8814B(x, v)                                \\\n\t(BIT_CLEAR_RXPKTBUF_1_MAX_ADDR_8814B(x) |                              \\\n\t BIT_RXPKTBUF_1_MAX_ADDR_8814B(v))\n\n/* 2 REG_RXFWBUF_1_MAX_ADDR_8814B */\n\n#define BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B 0\n#define BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B 0xffff\n#define BIT_RXFWBUF_1_MAX_ADDR_8814B(x)                                        \\\n\t(((x) & BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B)                             \\\n\t << BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B)\n#define BITS_RXFWBUF_1_MAX_ADDR_8814B                                          \\\n\t(BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B                                     \\\n\t << BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B)\n#define BIT_CLEAR_RXFWBUF_1_MAX_ADDR_8814B(x)                                  \\\n\t((x) & (~BITS_RXFWBUF_1_MAX_ADDR_8814B))\n#define BIT_GET_RXFWBUF_1_MAX_ADDR_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B) &                         \\\n\t BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B)\n#define BIT_SET_RXFWBUF_1_MAX_ADDR_8814B(x, v)                                 \\\n\t(BIT_CLEAR_RXFWBUF_1_MAX_ADDR_8814B(x) |                               \\\n\t BIT_RXFWBUF_1_MAX_ADDR_8814B(v))\n\n/* 2 REG_IO_WRAP_ERR_FLAG_V1_8814B */\n#define BIT_IO_WRAP_ERR_8814B BIT(0)\n\n/* 2 REG_RXPKTBUF_1_READ_8814B */\n\n#define BIT_SHIFT_RXPKTBUF_1_READ_8814B 0\n#define BIT_MASK_RXPKTBUF_1_READ_8814B 0x3ffff\n#define BIT_RXPKTBUF_1_READ_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RXPKTBUF_1_READ_8814B)                                \\\n\t << BIT_SHIFT_RXPKTBUF_1_READ_8814B)\n#define BITS_RXPKTBUF_1_READ_8814B                                             \\\n\t(BIT_MASK_RXPKTBUF_1_READ_8814B << BIT_SHIFT_RXPKTBUF_1_READ_8814B)\n#define BIT_CLEAR_RXPKTBUF_1_READ_8814B(x) ((x) & (~BITS_RXPKTBUF_1_READ_8814B))\n#define BIT_GET_RXPKTBUF_1_READ_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RXPKTBUF_1_READ_8814B) &                            \\\n\t BIT_MASK_RXPKTBUF_1_READ_8814B)\n#define BIT_SET_RXPKTBUF_1_READ_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RXPKTBUF_1_READ_8814B(x) | BIT_RXPKTBUF_1_READ_8814B(v))\n\n/* 2 REG_RXPKTBUF_1_WRITE_8814B */\n\n#define BIT_SHIFT_RXPKTBUF_1_WRITE_8814B 0\n#define BIT_MASK_RXPKTBUF_1_WRITE_8814B 0x3ffff\n#define BIT_RXPKTBUF_1_WRITE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_RXPKTBUF_1_WRITE_8814B)                               \\\n\t << BIT_SHIFT_RXPKTBUF_1_WRITE_8814B)\n#define BITS_RXPKTBUF_1_WRITE_8814B                                            \\\n\t(BIT_MASK_RXPKTBUF_1_WRITE_8814B << BIT_SHIFT_RXPKTBUF_1_WRITE_8814B)\n#define BIT_CLEAR_RXPKTBUF_1_WRITE_8814B(x)                                    \\\n\t((x) & (~BITS_RXPKTBUF_1_WRITE_8814B))\n#define BIT_GET_RXPKTBUF_1_WRITE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_RXPKTBUF_1_WRITE_8814B) &                           \\\n\t BIT_MASK_RXPKTBUF_1_WRITE_8814B)\n#define BIT_SET_RXPKTBUF_1_WRITE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_RXPKTBUF_1_WRITE_8814B(x) | BIT_RXPKTBUF_1_WRITE_8814B(v))\n\n/* 2 REG_BUFF_DBGUG_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_R_OQT_DBG_SEL_8814B 16\n#define BIT_MASK_R_OQT_DBG_SEL_8814B 0xff\n#define BIT_R_OQT_DBG_SEL_8814B(x)                                             \\\n\t(((x) & BIT_MASK_R_OQT_DBG_SEL_8814B) << BIT_SHIFT_R_OQT_DBG_SEL_8814B)\n#define BITS_R_OQT_DBG_SEL_8814B                                               \\\n\t(BIT_MASK_R_OQT_DBG_SEL_8814B << BIT_SHIFT_R_OQT_DBG_SEL_8814B)\n#define BIT_CLEAR_R_OQT_DBG_SEL_8814B(x) ((x) & (~BITS_R_OQT_DBG_SEL_8814B))\n#define BIT_GET_R_OQT_DBG_SEL_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_OQT_DBG_SEL_8814B) & BIT_MASK_R_OQT_DBG_SEL_8814B)\n#define BIT_SET_R_OQT_DBG_SEL_8814B(x, v)                                      \\\n\t(BIT_CLEAR_R_OQT_DBG_SEL_8814B(x) | BIT_R_OQT_DBG_SEL_8814B(v))\n\n#define BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B 8\n#define BIT_MASK_R_TXPKTBF_DBG_SEL_8814B 0x7\n#define BIT_R_TXPKTBF_DBG_SEL_8814B(x)                                         \\\n\t(((x) & BIT_MASK_R_TXPKTBF_DBG_SEL_8814B)                              \\\n\t << BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B)\n#define BITS_R_TXPKTBF_DBG_SEL_8814B                                           \\\n\t(BIT_MASK_R_TXPKTBF_DBG_SEL_8814B << BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B)\n#define BIT_CLEAR_R_TXPKTBF_DBG_SEL_8814B(x)                                   \\\n\t((x) & (~BITS_R_TXPKTBF_DBG_SEL_8814B))\n#define BIT_GET_R_TXPKTBF_DBG_SEL_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B) &                          \\\n\t BIT_MASK_R_TXPKTBF_DBG_SEL_8814B)\n#define BIT_SET_R_TXPKTBF_DBG_SEL_8814B(x, v)                                  \\\n\t(BIT_CLEAR_R_TXPKTBF_DBG_SEL_8814B(x) | BIT_R_TXPKTBF_DBG_SEL_8814B(v))\n\n#define BIT_SHIFT_R_RXPKT_DBG_SEL_8814B 6\n#define BIT_MASK_R_RXPKT_DBG_SEL_8814B 0x3\n#define BIT_R_RXPKT_DBG_SEL_8814B(x)                                           \\\n\t(((x) & BIT_MASK_R_RXPKT_DBG_SEL_8814B)                                \\\n\t << BIT_SHIFT_R_RXPKT_DBG_SEL_8814B)\n#define BITS_R_RXPKT_DBG_SEL_8814B                                             \\\n\t(BIT_MASK_R_RXPKT_DBG_SEL_8814B << BIT_SHIFT_R_RXPKT_DBG_SEL_8814B)\n#define BIT_CLEAR_R_RXPKT_DBG_SEL_8814B(x) ((x) & (~BITS_R_RXPKT_DBG_SEL_8814B))\n#define BIT_GET_R_RXPKT_DBG_SEL_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_RXPKT_DBG_SEL_8814B) &                            \\\n\t BIT_MASK_R_RXPKT_DBG_SEL_8814B)\n#define BIT_SET_R_RXPKT_DBG_SEL_8814B(x, v)                                    \\\n\t(BIT_CLEAR_R_RXPKT_DBG_SEL_8814B(x) | BIT_R_RXPKT_DBG_SEL_8814B(v))\n\n#define BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B 0\n#define BIT_MASK_R_RXPKTBF_DBG_SEL_8814B 0x3\n#define BIT_R_RXPKTBF_DBG_SEL_8814B(x)                                         \\\n\t(((x) & BIT_MASK_R_RXPKTBF_DBG_SEL_8814B)                              \\\n\t << BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B)\n#define BITS_R_RXPKTBF_DBG_SEL_8814B                                           \\\n\t(BIT_MASK_R_RXPKTBF_DBG_SEL_8814B << BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B)\n#define BIT_CLEAR_R_RXPKTBF_DBG_SEL_8814B(x)                                   \\\n\t((x) & (~BITS_R_RXPKTBF_DBG_SEL_8814B))\n#define BIT_GET_R_RXPKTBF_DBG_SEL_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B) &                          \\\n\t BIT_MASK_R_RXPKTBF_DBG_SEL_8814B)\n#define BIT_SET_R_RXPKTBF_DBG_SEL_8814B(x, v)                                  \\\n\t(BIT_CLEAR_R_RXPKTBF_DBG_SEL_8814B(x) | BIT_R_RXPKTBF_DBG_SEL_8814B(v))\n\n/* 2 REG_RFE_CTRL_PAD_E2_8814B */\n#define BIT_RFE_CTRL_ANTSW_E2_8814B BIT(16)\n#define BIT_RFE_CTRL_PIN15_E2_8814B BIT(15)\n#define BIT_RFE_CTRL_PIN14_E2_8814B BIT(14)\n#define BIT_RFE_CTRL_PIN13_E2_8814B BIT(13)\n#define BIT_RFE_CTRL_PIN12_E2_8814B BIT(12)\n#define BIT_RFE_CTRL_PIN11_E2_8814B BIT(11)\n#define BIT_RFE_CTRL_PIN10_E2_8814B BIT(10)\n#define BIT_RFE_CTRL_PIN9_E2_8814B BIT(9)\n#define BIT_RFE_CTRL_PIN8_E2_8814B BIT(8)\n#define BIT_RFE_CTRL_PIN7_E2_8814B BIT(7)\n#define BIT_RFE_CTRL_PIN6_E2_8814B BIT(6)\n#define BIT_RFE_CTRL_PIN5_E2_8814B BIT(5)\n#define BIT_RFE_CTRL_PIN4_E2_8814B BIT(4)\n#define BIT_RFE_CTRL_PIN3_E2_8814B BIT(3)\n#define BIT_RFE_CTRL_PIN2_E2_8814B BIT(2)\n#define BIT_RFE_CTRL_PIN1_E2_8814B BIT(1)\n#define BIT_RFE_CTRL_PIN0_E2_8814B BIT(0)\n\n/* 2 REG_RFE_CTRL_PAD_SR_8814B */\n#define BIT_RFE_CTRL_ANTSW_SR_8814B BIT(16)\n#define BIT_RFE_CTRL_PIN15_SR_8814B BIT(15)\n#define BIT_RFE_CTRL_PIN14_SR_8814B BIT(14)\n#define BIT_RFE_CTRL_PIN13_SR_8814B BIT(13)\n#define BIT_RFE_CTRL_PIN12_SR_8814B BIT(12)\n#define BIT_RFE_CTRL_PIN11_SR_8814B BIT(11)\n#define BIT_RFE_CTRL_PIN10_SR_8814B BIT(10)\n#define BIT_RFE_CTRL_PIN9_SR_8814B BIT(9)\n#define BIT_RFE_CTRL_PIN8_SR_8814B BIT(8)\n#define BIT_RFE_CTRL_PIN7_SR_8814B BIT(7)\n#define BIT_RFE_CTRL_PIN6_SR_8814B BIT(6)\n#define BIT_RFE_CTRL_PIN5_SR_8814B BIT(5)\n#define BIT_RFE_CTRL_PIN4_SR_8814B BIT(4)\n#define BIT_RFE_CTRL_PIN3_SR_8814B BIT(3)\n#define BIT_RFE_CTRL_PIN2_SR_8814B BIT(2)\n#define BIT_RFE_CTRL_PIN1_SR_8814B BIT(1)\n#define BIT_RFE_CTRL_PIN0_SR_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_H2C_PRIORITY_SEL_8814B */\n\n#define BIT_SHIFT_H2C_PRIORITY_SEL_8814B 0\n#define BIT_MASK_H2C_PRIORITY_SEL_8814B 0x3\n#define BIT_H2C_PRIORITY_SEL_8814B(x)                                          \\\n\t(((x) & BIT_MASK_H2C_PRIORITY_SEL_8814B)                               \\\n\t << BIT_SHIFT_H2C_PRIORITY_SEL_8814B)\n#define BITS_H2C_PRIORITY_SEL_8814B                                            \\\n\t(BIT_MASK_H2C_PRIORITY_SEL_8814B << BIT_SHIFT_H2C_PRIORITY_SEL_8814B)\n#define BIT_CLEAR_H2C_PRIORITY_SEL_8814B(x)                                    \\\n\t((x) & (~BITS_H2C_PRIORITY_SEL_8814B))\n#define BIT_GET_H2C_PRIORITY_SEL_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_H2C_PRIORITY_SEL_8814B) &                           \\\n\t BIT_MASK_H2C_PRIORITY_SEL_8814B)\n#define BIT_SET_H2C_PRIORITY_SEL_8814B(x, v)                                   \\\n\t(BIT_CLEAR_H2C_PRIORITY_SEL_8814B(x) | BIT_H2C_PRIORITY_SEL_8814B(v))\n\n/* 2 REG_COUNTER_CTRL_8814B */\n\n#define BIT_SHIFT_COUNTER_BASE_8814B 16\n#define BIT_MASK_COUNTER_BASE_8814B 0x1fff\n#define BIT_COUNTER_BASE_8814B(x)                                              \\\n\t(((x) & BIT_MASK_COUNTER_BASE_8814B) << BIT_SHIFT_COUNTER_BASE_8814B)\n#define BITS_COUNTER_BASE_8814B                                                \\\n\t(BIT_MASK_COUNTER_BASE_8814B << BIT_SHIFT_COUNTER_BASE_8814B)\n#define BIT_CLEAR_COUNTER_BASE_8814B(x) ((x) & (~BITS_COUNTER_BASE_8814B))\n#define BIT_GET_COUNTER_BASE_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_COUNTER_BASE_8814B) & BIT_MASK_COUNTER_BASE_8814B)\n#define BIT_SET_COUNTER_BASE_8814B(x, v)                                       \\\n\t(BIT_CLEAR_COUNTER_BASE_8814B(x) | BIT_COUNTER_BASE_8814B(v))\n\n#define BIT_EN_RTS_REQ_8814B BIT(9)\n#define BIT_EN_EDCA_REQ_8814B BIT(8)\n#define BIT_EN_PTCL_REQ_8814B BIT(7)\n#define BIT_EN_SCH_REQ_8814B BIT(6)\n#define BIT_USB_COUNT_EN_8814B BIT(5)\n#define BIT_PCIE_COUNT_EN_8814B BIT(4)\n#define BIT_RQPN_COUNT_EN_8814B BIT(3)\n#define BIT_RDE_COUNT_EN_8814B BIT(2)\n#define BIT_TDE_COUNT_EN_8814B BIT(1)\n#define BIT_DISABLE_COUNTER_8814B BIT(0)\n\n/* 2 REG_COUNTER_THRESHOLD_8814B */\n#define BIT_SEL_ALL_MACID_8814B BIT(31)\n\n#define BIT_SHIFT_COUNTER_MACID_8814B 24\n#define BIT_MASK_COUNTER_MACID_8814B 0x7f\n#define BIT_COUNTER_MACID_8814B(x)                                             \\\n\t(((x) & BIT_MASK_COUNTER_MACID_8814B) << BIT_SHIFT_COUNTER_MACID_8814B)\n#define BITS_COUNTER_MACID_8814B                                               \\\n\t(BIT_MASK_COUNTER_MACID_8814B << BIT_SHIFT_COUNTER_MACID_8814B)\n#define BIT_CLEAR_COUNTER_MACID_8814B(x) ((x) & (~BITS_COUNTER_MACID_8814B))\n#define BIT_GET_COUNTER_MACID_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_COUNTER_MACID_8814B) & BIT_MASK_COUNTER_MACID_8814B)\n#define BIT_SET_COUNTER_MACID_8814B(x, v)                                      \\\n\t(BIT_CLEAR_COUNTER_MACID_8814B(x) | BIT_COUNTER_MACID_8814B(v))\n\n#define BIT_SHIFT_AGG_VALUE2_8814B 16\n#define BIT_MASK_AGG_VALUE2_8814B 0x7f\n#define BIT_AGG_VALUE2_8814B(x)                                                \\\n\t(((x) & BIT_MASK_AGG_VALUE2_8814B) << BIT_SHIFT_AGG_VALUE2_8814B)\n#define BITS_AGG_VALUE2_8814B                                                  \\\n\t(BIT_MASK_AGG_VALUE2_8814B << BIT_SHIFT_AGG_VALUE2_8814B)\n#define BIT_CLEAR_AGG_VALUE2_8814B(x) ((x) & (~BITS_AGG_VALUE2_8814B))\n#define BIT_GET_AGG_VALUE2_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_AGG_VALUE2_8814B) & BIT_MASK_AGG_VALUE2_8814B)\n#define BIT_SET_AGG_VALUE2_8814B(x, v)                                         \\\n\t(BIT_CLEAR_AGG_VALUE2_8814B(x) | BIT_AGG_VALUE2_8814B(v))\n\n#define BIT_SHIFT_AGG_VALUE1_8814B 8\n#define BIT_MASK_AGG_VALUE1_8814B 0x7f\n#define BIT_AGG_VALUE1_8814B(x)                                                \\\n\t(((x) & BIT_MASK_AGG_VALUE1_8814B) << BIT_SHIFT_AGG_VALUE1_8814B)\n#define BITS_AGG_VALUE1_8814B                                                  \\\n\t(BIT_MASK_AGG_VALUE1_8814B << BIT_SHIFT_AGG_VALUE1_8814B)\n#define BIT_CLEAR_AGG_VALUE1_8814B(x) ((x) & (~BITS_AGG_VALUE1_8814B))\n#define BIT_GET_AGG_VALUE1_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_AGG_VALUE1_8814B) & BIT_MASK_AGG_VALUE1_8814B)\n#define BIT_SET_AGG_VALUE1_8814B(x, v)                                         \\\n\t(BIT_CLEAR_AGG_VALUE1_8814B(x) | BIT_AGG_VALUE1_8814B(v))\n\n#define BIT_SHIFT_AGG_VALUE0_8814B 0\n#define BIT_MASK_AGG_VALUE0_8814B 0x7f\n#define BIT_AGG_VALUE0_8814B(x)                                                \\\n\t(((x) & BIT_MASK_AGG_VALUE0_8814B) << BIT_SHIFT_AGG_VALUE0_8814B)\n#define BITS_AGG_VALUE0_8814B                                                  \\\n\t(BIT_MASK_AGG_VALUE0_8814B << BIT_SHIFT_AGG_VALUE0_8814B)\n#define BIT_CLEAR_AGG_VALUE0_8814B(x) ((x) & (~BITS_AGG_VALUE0_8814B))\n#define BIT_GET_AGG_VALUE0_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_AGG_VALUE0_8814B) & BIT_MASK_AGG_VALUE0_8814B)\n#define BIT_SET_AGG_VALUE0_8814B(x, v)                                         \\\n\t(BIT_CLEAR_AGG_VALUE0_8814B(x) | BIT_AGG_VALUE0_8814B(v))\n\n/* 2 REG_COUNTER_SET_8814B */\n\n#define BIT_SHIFT_REQUEST_RESET_8814B 16\n#define BIT_MASK_REQUEST_RESET_8814B 0xffff\n#define BIT_REQUEST_RESET_8814B(x)                                             \\\n\t(((x) & BIT_MASK_REQUEST_RESET_8814B) << BIT_SHIFT_REQUEST_RESET_8814B)\n#define BITS_REQUEST_RESET_8814B                                               \\\n\t(BIT_MASK_REQUEST_RESET_8814B << BIT_SHIFT_REQUEST_RESET_8814B)\n#define BIT_CLEAR_REQUEST_RESET_8814B(x) ((x) & (~BITS_REQUEST_RESET_8814B))\n#define BIT_GET_REQUEST_RESET_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_REQUEST_RESET_8814B) & BIT_MASK_REQUEST_RESET_8814B)\n#define BIT_SET_REQUEST_RESET_8814B(x, v)                                      \\\n\t(BIT_CLEAR_REQUEST_RESET_8814B(x) | BIT_REQUEST_RESET_8814B(v))\n\n#define BIT_SHIFT_REQUEST_START_8814B 0\n#define BIT_MASK_REQUEST_START_8814B 0xffff\n#define BIT_REQUEST_START_8814B(x)                                             \\\n\t(((x) & BIT_MASK_REQUEST_START_8814B) << BIT_SHIFT_REQUEST_START_8814B)\n#define BITS_REQUEST_START_8814B                                               \\\n\t(BIT_MASK_REQUEST_START_8814B << BIT_SHIFT_REQUEST_START_8814B)\n#define BIT_CLEAR_REQUEST_START_8814B(x) ((x) & (~BITS_REQUEST_START_8814B))\n#define BIT_GET_REQUEST_START_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_REQUEST_START_8814B) & BIT_MASK_REQUEST_START_8814B)\n#define BIT_SET_REQUEST_START_8814B(x, v)                                      \\\n\t(BIT_CLEAR_REQUEST_START_8814B(x) | BIT_REQUEST_START_8814B(v))\n\n/* 2 REG_COUNTER_OVERFLOW_8814B */\n\n#define BIT_SHIFT_CNT_OVF_REG_8814B 0\n#define BIT_MASK_CNT_OVF_REG_8814B 0xffff\n#define BIT_CNT_OVF_REG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CNT_OVF_REG_8814B) << BIT_SHIFT_CNT_OVF_REG_8814B)\n#define BITS_CNT_OVF_REG_8814B                                                 \\\n\t(BIT_MASK_CNT_OVF_REG_8814B << BIT_SHIFT_CNT_OVF_REG_8814B)\n#define BIT_CLEAR_CNT_OVF_REG_8814B(x) ((x) & (~BITS_CNT_OVF_REG_8814B))\n#define BIT_GET_CNT_OVF_REG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CNT_OVF_REG_8814B) & BIT_MASK_CNT_OVF_REG_8814B)\n#define BIT_SET_CNT_OVF_REG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CNT_OVF_REG_8814B(x) | BIT_CNT_OVF_REG_8814B(v))\n\n/* 2 REG_TXDMA_LEN_THRESHOLD_8814B */\n\n#define BIT_SHIFT_TDE_LEN_TH1_8814B 16\n#define BIT_MASK_TDE_LEN_TH1_8814B 0xffff\n#define BIT_TDE_LEN_TH1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_TDE_LEN_TH1_8814B) << BIT_SHIFT_TDE_LEN_TH1_8814B)\n#define BITS_TDE_LEN_TH1_8814B                                                 \\\n\t(BIT_MASK_TDE_LEN_TH1_8814B << BIT_SHIFT_TDE_LEN_TH1_8814B)\n#define BIT_CLEAR_TDE_LEN_TH1_8814B(x) ((x) & (~BITS_TDE_LEN_TH1_8814B))\n#define BIT_GET_TDE_LEN_TH1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_TDE_LEN_TH1_8814B) & BIT_MASK_TDE_LEN_TH1_8814B)\n#define BIT_SET_TDE_LEN_TH1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_TDE_LEN_TH1_8814B(x) | BIT_TDE_LEN_TH1_8814B(v))\n\n#define BIT_SHIFT_TDE_LEN_TH0_8814B 0\n#define BIT_MASK_TDE_LEN_TH0_8814B 0xffff\n#define BIT_TDE_LEN_TH0_8814B(x)                                               \\\n\t(((x) & BIT_MASK_TDE_LEN_TH0_8814B) << BIT_SHIFT_TDE_LEN_TH0_8814B)\n#define BITS_TDE_LEN_TH0_8814B                                                 \\\n\t(BIT_MASK_TDE_LEN_TH0_8814B << BIT_SHIFT_TDE_LEN_TH0_8814B)\n#define BIT_CLEAR_TDE_LEN_TH0_8814B(x) ((x) & (~BITS_TDE_LEN_TH0_8814B))\n#define BIT_GET_TDE_LEN_TH0_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_TDE_LEN_TH0_8814B) & BIT_MASK_TDE_LEN_TH0_8814B)\n#define BIT_SET_TDE_LEN_TH0_8814B(x, v)                                        \\\n\t(BIT_CLEAR_TDE_LEN_TH0_8814B(x) | BIT_TDE_LEN_TH0_8814B(v))\n\n/* 2 REG_RXDMA_LEN_THRESHOLD_8814B */\n\n#define BIT_SHIFT_RDE_LEN_TH1_8814B 16\n#define BIT_MASK_RDE_LEN_TH1_8814B 0xffff\n#define BIT_RDE_LEN_TH1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_RDE_LEN_TH1_8814B) << BIT_SHIFT_RDE_LEN_TH1_8814B)\n#define BITS_RDE_LEN_TH1_8814B                                                 \\\n\t(BIT_MASK_RDE_LEN_TH1_8814B << BIT_SHIFT_RDE_LEN_TH1_8814B)\n#define BIT_CLEAR_RDE_LEN_TH1_8814B(x) ((x) & (~BITS_RDE_LEN_TH1_8814B))\n#define BIT_GET_RDE_LEN_TH1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_RDE_LEN_TH1_8814B) & BIT_MASK_RDE_LEN_TH1_8814B)\n#define BIT_SET_RDE_LEN_TH1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_RDE_LEN_TH1_8814B(x) | BIT_RDE_LEN_TH1_8814B(v))\n\n#define BIT_SHIFT_RDE_LEN_TH0_8814B 0\n#define BIT_MASK_RDE_LEN_TH0_8814B 0xffff\n#define BIT_RDE_LEN_TH0_8814B(x)                                               \\\n\t(((x) & BIT_MASK_RDE_LEN_TH0_8814B) << BIT_SHIFT_RDE_LEN_TH0_8814B)\n#define BITS_RDE_LEN_TH0_8814B                                                 \\\n\t(BIT_MASK_RDE_LEN_TH0_8814B << BIT_SHIFT_RDE_LEN_TH0_8814B)\n#define BIT_CLEAR_RDE_LEN_TH0_8814B(x) ((x) & (~BITS_RDE_LEN_TH0_8814B))\n#define BIT_GET_RDE_LEN_TH0_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_RDE_LEN_TH0_8814B) & BIT_MASK_RDE_LEN_TH0_8814B)\n#define BIT_SET_RDE_LEN_TH0_8814B(x, v)                                        \\\n\t(BIT_CLEAR_RDE_LEN_TH0_8814B(x) | BIT_RDE_LEN_TH0_8814B(v))\n\n/* 2 REG_PCIE_EXEC_TIME_THRESHOLD_8814B */\n\n#define BIT_SHIFT_COUNT_INT_SEL_8814B 16\n#define BIT_MASK_COUNT_INT_SEL_8814B 0x3\n#define BIT_COUNT_INT_SEL_8814B(x)                                             \\\n\t(((x) & BIT_MASK_COUNT_INT_SEL_8814B) << BIT_SHIFT_COUNT_INT_SEL_8814B)\n#define BITS_COUNT_INT_SEL_8814B                                               \\\n\t(BIT_MASK_COUNT_INT_SEL_8814B << BIT_SHIFT_COUNT_INT_SEL_8814B)\n#define BIT_CLEAR_COUNT_INT_SEL_8814B(x) ((x) & (~BITS_COUNT_INT_SEL_8814B))\n#define BIT_GET_COUNT_INT_SEL_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_COUNT_INT_SEL_8814B) & BIT_MASK_COUNT_INT_SEL_8814B)\n#define BIT_SET_COUNT_INT_SEL_8814B(x, v)                                      \\\n\t(BIT_CLEAR_COUNT_INT_SEL_8814B(x) | BIT_COUNT_INT_SEL_8814B(v))\n\n#define BIT_SHIFT_EXEC_TIME_TH_8814B 0\n#define BIT_MASK_EXEC_TIME_TH_8814B 0xffff\n#define BIT_EXEC_TIME_TH_8814B(x)                                              \\\n\t(((x) & BIT_MASK_EXEC_TIME_TH_8814B) << BIT_SHIFT_EXEC_TIME_TH_8814B)\n#define BITS_EXEC_TIME_TH_8814B                                                \\\n\t(BIT_MASK_EXEC_TIME_TH_8814B << BIT_SHIFT_EXEC_TIME_TH_8814B)\n#define BIT_CLEAR_EXEC_TIME_TH_8814B(x) ((x) & (~BITS_EXEC_TIME_TH_8814B))\n#define BIT_GET_EXEC_TIME_TH_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_EXEC_TIME_TH_8814B) & BIT_MASK_EXEC_TIME_TH_8814B)\n#define BIT_SET_EXEC_TIME_TH_8814B(x, v)                                       \\\n\t(BIT_CLEAR_EXEC_TIME_TH_8814B(x) | BIT_EXEC_TIME_TH_8814B(v))\n\n/* 2 REG_FT2IMR_8814B */\n#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8814B BIT(31)\n#define BIT_FS_CLI3_RX_UAPSDMD0_EN_8814B BIT(30)\n#define BIT_FS_CLI3_TRIGGER_PKT_EN_8814B BIT(29)\n#define BIT_FS_CLI3_EOSP_INT_EN_8814B BIT(28)\n#define BIT_FS_CLI2_RX_UAPSDMD1_EN_8814B BIT(27)\n#define BIT_FS_CLI2_RX_UAPSDMD0_EN_8814B BIT(26)\n#define BIT_FS_CLI2_TRIGGER_PKT_EN_8814B BIT(25)\n#define BIT_FS_CLI2_EOSP_INT_EN_8814B BIT(24)\n#define BIT_FS_CLI1_RX_UAPSDMD1_EN_8814B BIT(23)\n#define BIT_FS_CLI1_RX_UAPSDMD0_EN_8814B BIT(22)\n#define BIT_FS_CLI1_TRIGGER_PKT_EN_8814B BIT(21)\n#define BIT_FS_CLI1_EOSP_INT_EN_8814B BIT(20)\n#define BIT_FS_CLI0_RX_UAPSDMD1_EN_8814B BIT(19)\n#define BIT_FS_CLI0_RX_UAPSDMD0_EN_8814B BIT(18)\n#define BIT_FS_CLI0_TRIGGER_PKT_EN_8814B BIT(17)\n#define BIT_FS_CLI0_EOSP_INT_EN_8814B BIT(16)\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN_8814B BIT(9)\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN_8814B BIT(8)\n#define BIT_FS_CLI3_TX_NULL1_INT_EN_8814B BIT(7)\n#define BIT_FS_CLI3_TX_NULL0_INT_EN_8814B BIT(6)\n#define BIT_FS_CLI2_TX_NULL1_INT_EN_8814B BIT(5)\n#define BIT_FS_CLI2_TX_NULL0_INT_EN_8814B BIT(4)\n#define BIT_FS_CLI1_TX_NULL1_INT_EN_8814B BIT(3)\n#define BIT_FS_CLI1_TX_NULL0_INT_EN_8814B BIT(2)\n#define BIT_FS_CLI0_TX_NULL1_INT_EN_8814B BIT(1)\n#define BIT_FS_CLI0_TX_NULL0_INT_EN_8814B BIT(0)\n\n/* 2 REG_FT2ISR_8814B */\n#define BIT_FS_CLI3_RX_UAPSDMD1_INT_8814B BIT(31)\n#define BIT_FS_CLI3_RX_UAPSDMD0_INT_8814B BIT(30)\n#define BIT_FS_CLI3_TRIGGER_PKT_INT_8814B BIT(29)\n#define BIT_FS_CLI3_EOSP_INT_8814B BIT(28)\n#define BIT_FS_CLI2_RX_UAPSDMD1_INT_8814B BIT(27)\n#define BIT_FS_CLI2_RX_UAPSDMD0_INT_8814B BIT(26)\n#define BIT_FS_CLI2_TRIGGER_PKT_INT_8814B BIT(25)\n#define BIT_FS_CLI2_EOSP_INT_8814B BIT(24)\n#define BIT_FS_CLI1_RX_UAPSDMD1_INT_8814B BIT(23)\n#define BIT_FS_CLI1_RX_UAPSDMD0_INT_8814B BIT(22)\n#define BIT_FS_CLI1_TRIGGER_PKT_INT_8814B BIT(21)\n#define BIT_FS_CLI1_EOSP_INT_8814B BIT(20)\n#define BIT_FS_CLI0_RX_UAPSDMD1_INT_8814B BIT(19)\n#define BIT_FS_CLI0_RX_UAPSDMD0_INT_8814B BIT(18)\n#define BIT_FS_CLI0_TRIGGER_PKT_INT_8814B BIT(17)\n#define BIT_FS_CLI0_EOSP_INT_8814B BIT(16)\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT_8814B BIT(9)\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT_8814B BIT(8)\n#define BIT_FS_CLI3_TX_NULL1_INT_8814B BIT(7)\n#define BIT_FS_CLI3_TX_NULL0_INT_8814B BIT(6)\n#define BIT_FS_CLI2_TX_NULL1_INT_8814B BIT(5)\n#define BIT_FS_CLI2_TX_NULL0_INT_8814B BIT(4)\n#define BIT_FS_CLI1_TX_NULL1_INT_8814B BIT(3)\n#define BIT_FS_CLI1_TX_NULL0_INT_8814B BIT(2)\n#define BIT_FS_CLI0_TX_NULL1_INT_8814B BIT(1)\n#define BIT_FS_CLI0_TX_NULL0_INT_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_MSG2_8814B */\n\n#define BIT_SHIFT_FW_MSG2_8814B 0\n#define BIT_MASK_FW_MSG2_8814B 0xffffffffL\n#define BIT_FW_MSG2_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG2_8814B) << BIT_SHIFT_FW_MSG2_8814B)\n#define BITS_FW_MSG2_8814B (BIT_MASK_FW_MSG2_8814B << BIT_SHIFT_FW_MSG2_8814B)\n#define BIT_CLEAR_FW_MSG2_8814B(x) ((x) & (~BITS_FW_MSG2_8814B))\n#define BIT_GET_FW_MSG2_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG2_8814B) & BIT_MASK_FW_MSG2_8814B)\n#define BIT_SET_FW_MSG2_8814B(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG2_8814B(x) | BIT_FW_MSG2_8814B(v))\n\n/* 2 REG_MSG3_8814B */\n\n#define BIT_SHIFT_FW_MSG3_8814B 0\n#define BIT_MASK_FW_MSG3_8814B 0xffffffffL\n#define BIT_FW_MSG3_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG3_8814B) << BIT_SHIFT_FW_MSG3_8814B)\n#define BITS_FW_MSG3_8814B (BIT_MASK_FW_MSG3_8814B << BIT_SHIFT_FW_MSG3_8814B)\n#define BIT_CLEAR_FW_MSG3_8814B(x) ((x) & (~BITS_FW_MSG3_8814B))\n#define BIT_GET_FW_MSG3_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG3_8814B) & BIT_MASK_FW_MSG3_8814B)\n#define BIT_SET_FW_MSG3_8814B(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG3_8814B(x) | BIT_FW_MSG3_8814B(v))\n\n/* 2 REG_MSG4_8814B */\n\n#define BIT_SHIFT_FW_MSG4_8814B 0\n#define BIT_MASK_FW_MSG4_8814B 0xffffffffL\n#define BIT_FW_MSG4_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG4_8814B) << BIT_SHIFT_FW_MSG4_8814B)\n#define BITS_FW_MSG4_8814B (BIT_MASK_FW_MSG4_8814B << BIT_SHIFT_FW_MSG4_8814B)\n#define BIT_CLEAR_FW_MSG4_8814B(x) ((x) & (~BITS_FW_MSG4_8814B))\n#define BIT_GET_FW_MSG4_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG4_8814B) & BIT_MASK_FW_MSG4_8814B)\n#define BIT_SET_FW_MSG4_8814B(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG4_8814B(x) | BIT_FW_MSG4_8814B(v))\n\n/* 2 REG_MSG5_8814B */\n\n#define BIT_SHIFT_FW_MSG5_8814B 0\n#define BIT_MASK_FW_MSG5_8814B 0xffffffffL\n#define BIT_FW_MSG5_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG5_8814B) << BIT_SHIFT_FW_MSG5_8814B)\n#define BITS_FW_MSG5_8814B (BIT_MASK_FW_MSG5_8814B << BIT_SHIFT_FW_MSG5_8814B)\n#define BIT_CLEAR_FW_MSG5_8814B(x) ((x) & (~BITS_FW_MSG5_8814B))\n#define BIT_GET_FW_MSG5_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG5_8814B) & BIT_MASK_FW_MSG5_8814B)\n#define BIT_SET_FW_MSG5_8814B(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG5_8814B(x) | BIT_FW_MSG5_8814B(v))\n\n/* 2 REG_BIST_RSTN0_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_BIST_RSTN2_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_BIST_MODE_NRML0_8814B */\n\n/* 2 REG_BIST_MODE_NRML1_8814B */\n\n/* 2 REG_BIST_MODE_NRML2_8814B */\n\n/* 2 REG_BIST_MODE_NRML3_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_BIST_DONE_NRML_MAC_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_BIST_DONE_NRML1_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_BIST_DONE_DRF_MAC_8814B */\n\n/* 2 REG_BIST_DONE_DRF_8814B */\n\n/* 2 REG_BIST_DONE_DRF1_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_BIST_FAIL_NRML_MAC_8814B */\n\n/* 2 REG_BIST_FAIL_NRML_8814B */\n\n/* 2 REG_BIST_FAIL_NRML1_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_BIST_FAIL_NRML_MAC_V1_8814B */\n\n/* 2 REG_BIST_FAIL_NRML_V1_8814B */\n\n/* 2 REG_BIST_FAIL_NRML1_V1_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_BIST_MISR_DATAOUT_8814B */\n\n/* 2 REG_BIST_MISR_DATAOUT1_8814B */\n\n/* 2 REG_BIST_MISR_DATAOUT_CPU_8814B */\n\n/* 2 REG_BIST_MISR_DATAOUT_CPU1_8814B */\n\n/* 2 REG_BIST_MISR_DATAOUT_CPU2_8814B */\n\n/* 2 REG_BIST_MISR_DATOUT_CPU3_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_BCN_CTRL_0_8814B */\n#define BIT_BCN1_VALID_8814B BIT(31)\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_BCN1_HEAD_8814B 16\n#define BIT_MASK_BCN1_HEAD_8814B 0xfff\n#define BIT_BCN1_HEAD_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_BCN1_HEAD_8814B) << BIT_SHIFT_BCN1_HEAD_8814B)\n#define BITS_BCN1_HEAD_8814B                                                   \\\n\t(BIT_MASK_BCN1_HEAD_8814B << BIT_SHIFT_BCN1_HEAD_8814B)\n#define BIT_CLEAR_BCN1_HEAD_8814B(x) ((x) & (~BITS_BCN1_HEAD_8814B))\n#define BIT_GET_BCN1_HEAD_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCN1_HEAD_8814B) & BIT_MASK_BCN1_HEAD_8814B)\n#define BIT_SET_BCN1_HEAD_8814B(x, v)                                          \\\n\t(BIT_CLEAR_BCN1_HEAD_8814B(x) | BIT_BCN1_HEAD_8814B(v))\n\n#define BIT_BCN0_VALID_8814B BIT(15)\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_BCN0_HEAD_8814B 0\n#define BIT_MASK_BCN0_HEAD_8814B 0xfff\n#define BIT_BCN0_HEAD_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_BCN0_HEAD_8814B) << BIT_SHIFT_BCN0_HEAD_8814B)\n#define BITS_BCN0_HEAD_8814B                                                   \\\n\t(BIT_MASK_BCN0_HEAD_8814B << BIT_SHIFT_BCN0_HEAD_8814B)\n#define BIT_CLEAR_BCN0_HEAD_8814B(x) ((x) & (~BITS_BCN0_HEAD_8814B))\n#define BIT_GET_BCN0_HEAD_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCN0_HEAD_8814B) & BIT_MASK_BCN0_HEAD_8814B)\n#define BIT_SET_BCN0_HEAD_8814B(x, v)                                          \\\n\t(BIT_CLEAR_BCN0_HEAD_8814B(x) | BIT_BCN0_HEAD_8814B(v))\n\n/* 2 REG_BCN_CTRL_1_8814B */\n#define BIT_BCN3_VALID_8814B BIT(31)\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_BCN3_HEAD_8814B 16\n#define BIT_MASK_BCN3_HEAD_8814B 0xfff\n#define BIT_BCN3_HEAD_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_BCN3_HEAD_8814B) << BIT_SHIFT_BCN3_HEAD_8814B)\n#define BITS_BCN3_HEAD_8814B                                                   \\\n\t(BIT_MASK_BCN3_HEAD_8814B << BIT_SHIFT_BCN3_HEAD_8814B)\n#define BIT_CLEAR_BCN3_HEAD_8814B(x) ((x) & (~BITS_BCN3_HEAD_8814B))\n#define BIT_GET_BCN3_HEAD_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCN3_HEAD_8814B) & BIT_MASK_BCN3_HEAD_8814B)\n#define BIT_SET_BCN3_HEAD_8814B(x, v)                                          \\\n\t(BIT_CLEAR_BCN3_HEAD_8814B(x) | BIT_BCN3_HEAD_8814B(v))\n\n#define BIT_BCN2_VALID_8814B BIT(15)\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_BCN2_HEAD_8814B 0\n#define BIT_MASK_BCN2_HEAD_8814B 0xfff\n#define BIT_BCN2_HEAD_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_BCN2_HEAD_8814B) << BIT_SHIFT_BCN2_HEAD_8814B)\n#define BITS_BCN2_HEAD_8814B                                                   \\\n\t(BIT_MASK_BCN2_HEAD_8814B << BIT_SHIFT_BCN2_HEAD_8814B)\n#define BIT_CLEAR_BCN2_HEAD_8814B(x) ((x) & (~BITS_BCN2_HEAD_8814B))\n#define BIT_GET_BCN2_HEAD_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCN2_HEAD_8814B) & BIT_MASK_BCN2_HEAD_8814B)\n#define BIT_SET_BCN2_HEAD_8814B(x, v)                                          \\\n\t(BIT_CLEAR_BCN2_HEAD_8814B(x) | BIT_BCN2_HEAD_8814B(v))\n\n/* 2 REG_AUTO_LLT_V1_8814B */\n\n#define BIT_SHIFT_MAX_TX_PKT_V1_8814B 24\n#define BIT_MASK_MAX_TX_PKT_V1_8814B 0xff\n#define BIT_MAX_TX_PKT_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_MAX_TX_PKT_V1_8814B) << BIT_SHIFT_MAX_TX_PKT_V1_8814B)\n#define BITS_MAX_TX_PKT_V1_8814B                                               \\\n\t(BIT_MASK_MAX_TX_PKT_V1_8814B << BIT_SHIFT_MAX_TX_PKT_V1_8814B)\n#define BIT_CLEAR_MAX_TX_PKT_V1_8814B(x) ((x) & (~BITS_MAX_TX_PKT_V1_8814B))\n#define BIT_GET_MAX_TX_PKT_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MAX_TX_PKT_V1_8814B) & BIT_MASK_MAX_TX_PKT_V1_8814B)\n#define BIT_SET_MAX_TX_PKT_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_MAX_TX_PKT_V1_8814B(x) | BIT_MAX_TX_PKT_V1_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B 20\n#define BIT_MASK_R_BCN_HEAD_SEL_V1_8814B 0x7\n#define BIT_R_BCN_HEAD_SEL_V1_8814B(x)                                         \\\n\t(((x) & BIT_MASK_R_BCN_HEAD_SEL_V1_8814B)                              \\\n\t << BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B)\n#define BITS_R_BCN_HEAD_SEL_V1_8814B                                           \\\n\t(BIT_MASK_R_BCN_HEAD_SEL_V1_8814B << BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B)\n#define BIT_CLEAR_R_BCN_HEAD_SEL_V1_8814B(x)                                   \\\n\t((x) & (~BITS_R_BCN_HEAD_SEL_V1_8814B))\n#define BIT_GET_R_BCN_HEAD_SEL_V1_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B) &                          \\\n\t BIT_MASK_R_BCN_HEAD_SEL_V1_8814B)\n#define BIT_SET_R_BCN_HEAD_SEL_V1_8814B(x, v)                                  \\\n\t(BIT_CLEAR_R_BCN_HEAD_SEL_V1_8814B(x) | BIT_R_BCN_HEAD_SEL_V1_8814B(v))\n\n#define BIT_SHIFT_LLT_FREE_PAGE_V2_8814B 8\n#define BIT_MASK_LLT_FREE_PAGE_V2_8814B 0xfff\n#define BIT_LLT_FREE_PAGE_V2_8814B(x)                                          \\\n\t(((x) & BIT_MASK_LLT_FREE_PAGE_V2_8814B)                               \\\n\t << BIT_SHIFT_LLT_FREE_PAGE_V2_8814B)\n#define BITS_LLT_FREE_PAGE_V2_8814B                                            \\\n\t(BIT_MASK_LLT_FREE_PAGE_V2_8814B << BIT_SHIFT_LLT_FREE_PAGE_V2_8814B)\n#define BIT_CLEAR_LLT_FREE_PAGE_V2_8814B(x)                                    \\\n\t((x) & (~BITS_LLT_FREE_PAGE_V2_8814B))\n#define BIT_GET_LLT_FREE_PAGE_V2_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2_8814B) &                           \\\n\t BIT_MASK_LLT_FREE_PAGE_V2_8814B)\n#define BIT_SET_LLT_FREE_PAGE_V2_8814B(x, v)                                   \\\n\t(BIT_CLEAR_LLT_FREE_PAGE_V2_8814B(x) | BIT_LLT_FREE_PAGE_V2_8814B(v))\n\n#define BIT_SHIFT_BLK_DESC_NUM_8814B 4\n#define BIT_MASK_BLK_DESC_NUM_8814B 0xf\n#define BIT_BLK_DESC_NUM_8814B(x)                                              \\\n\t(((x) & BIT_MASK_BLK_DESC_NUM_8814B) << BIT_SHIFT_BLK_DESC_NUM_8814B)\n#define BITS_BLK_DESC_NUM_8814B                                                \\\n\t(BIT_MASK_BLK_DESC_NUM_8814B << BIT_SHIFT_BLK_DESC_NUM_8814B)\n#define BIT_CLEAR_BLK_DESC_NUM_8814B(x) ((x) & (~BITS_BLK_DESC_NUM_8814B))\n#define BIT_GET_BLK_DESC_NUM_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BLK_DESC_NUM_8814B) & BIT_MASK_BLK_DESC_NUM_8814B)\n#define BIT_SET_BLK_DESC_NUM_8814B(x, v)                                       \\\n\t(BIT_CLEAR_BLK_DESC_NUM_8814B(x) | BIT_BLK_DESC_NUM_8814B(v))\n\n#define BIT_TDE_ERROR_STOP_8814B BIT(3)\n#define BIT_R_EN_BCN_SW_HEAD_SEL_8814B BIT(2)\n#define BIT_LLT_DBG_SEL_8814B BIT(1)\n#define BIT_AUTO_INIT_LLT_V1_8814B BIT(0)\n\n/* 2 REG_TXDMA_OFFSET_CHK_8814B */\n#define BIT_EM_CHKSUM_FIN_8814B BIT(31)\n#define BIT_EMN_PCIE_DMA_MOD_8814B BIT(30)\n#define BIT_EN_TXQUE_CLR_8814B BIT(29)\n#define BIT_EN_PCIE_FIFO_MODE_8814B BIT(28)\n\n#define BIT_SHIFT_PG_UNDER_TH_V1_8814B 16\n#define BIT_MASK_PG_UNDER_TH_V1_8814B 0xfff\n#define BIT_PG_UNDER_TH_V1_8814B(x)                                            \\\n\t(((x) & BIT_MASK_PG_UNDER_TH_V1_8814B)                                 \\\n\t << BIT_SHIFT_PG_UNDER_TH_V1_8814B)\n#define BITS_PG_UNDER_TH_V1_8814B                                              \\\n\t(BIT_MASK_PG_UNDER_TH_V1_8814B << BIT_SHIFT_PG_UNDER_TH_V1_8814B)\n#define BIT_CLEAR_PG_UNDER_TH_V1_8814B(x) ((x) & (~BITS_PG_UNDER_TH_V1_8814B))\n#define BIT_GET_PG_UNDER_TH_V1_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8814B) &                             \\\n\t BIT_MASK_PG_UNDER_TH_V1_8814B)\n#define BIT_SET_PG_UNDER_TH_V1_8814B(x, v)                                     \\\n\t(BIT_CLEAR_PG_UNDER_TH_V1_8814B(x) | BIT_PG_UNDER_TH_V1_8814B(v))\n\n#define BIT_R_EN_RESET_RESTORE_H2C_8814B BIT(15)\n#define BIT_SDIO_TDE_FINISH_8814B BIT(14)\n#define BIT_SDIO_TXDESC_CHKSUM_EN_8814B BIT(13)\n#define BIT_RST_RDPTR_8814B BIT(12)\n#define BIT_RST_WRPTR_8814B BIT(11)\n#define BIT_CHK_PG_TH_EN_8814B BIT(10)\n#define BIT_DROP_DATA_EN_8814B BIT(9)\n#define BIT_CHECK_OFFSET_EN_8814B BIT(8)\n\n#define BIT_SHIFT_CHECK_OFFSET_8814B 0\n#define BIT_MASK_CHECK_OFFSET_8814B 0xff\n#define BIT_CHECK_OFFSET_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CHECK_OFFSET_8814B) << BIT_SHIFT_CHECK_OFFSET_8814B)\n#define BITS_CHECK_OFFSET_8814B                                                \\\n\t(BIT_MASK_CHECK_OFFSET_8814B << BIT_SHIFT_CHECK_OFFSET_8814B)\n#define BIT_CLEAR_CHECK_OFFSET_8814B(x) ((x) & (~BITS_CHECK_OFFSET_8814B))\n#define BIT_GET_CHECK_OFFSET_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CHECK_OFFSET_8814B) & BIT_MASK_CHECK_OFFSET_8814B)\n#define BIT_SET_CHECK_OFFSET_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CHECK_OFFSET_8814B(x) | BIT_CHECK_OFFSET_8814B(v))\n\n/* 2 REG_TXDMA_STATUS_8814B */\n#define BIT_AMSDU_PKT_SIZE_ERR_8814B BIT(31)\n#define BIT_AMSDU_EN_ERR_8814B BIT(30)\n#define BIT_CHKSUM_AMSDU_EN_ERR_8814B BIT(29)\n#define BIT_TXPKTBF_REQ_ERR_8814B BIT(28)\n#define BIT_OQT_UDN_16_8814B BIT(27)\n#define BIT_OQT_OVF_16_8814B BIT(26)\n#define BIT_OQT_UDN_14_15_8814B BIT(25)\n#define BIT_OQT_OVF_14_15_8814B BIT(24)\n#define BIT_OQT_UDN_13_8814B BIT(23)\n#define BIT_OQT_OVF_13_8814B BIT(22)\n#define BIT_OQT_UDN_12_8814B BIT(21)\n#define BIT_OQT_OVF_12_8814B BIT(20)\n#define BIT_OQT_UDN_8_11_8814B BIT(19)\n#define BIT_OQT_OVF_8_11_8814B BIT(18)\n#define BIT_OQT_UDN_4_7_8814B BIT(17)\n#define BIT_OQT_OVF_4_7_8814B BIT(16)\n#define BIT_PAYLOAD_CHKSUM_ERR_8814B BIT(15)\n#define BIT_PAYLOAD_UDN_8814B BIT(14)\n#define BIT_PAYLOAD_OVF_8814B BIT(13)\n#define BIT_DSC_CHKSUM_FAIL_8814B BIT(12)\n#define BIT_EP_QSEL_DIFF_8814B BIT(10)\n#define BIT_TX_OFFS_UNMATCH_8814B BIT(9)\n#define BIT_TXOQT_UDN_0_3_8814B BIT(8)\n#define BIT_TXOQT_OVF_0_3_8814B BIT(7)\n#define BIT_TXDMA_SFF_UDN_8814B BIT(6)\n#define BIT_TXDMA_SFF_OVF_8814B BIT(5)\n#define BIT_LLT_NULL_PG_8814B BIT(4)\n#define BIT_PAGE_UDN_8814B BIT(3)\n#define BIT_PAGE_OVF_8814B BIT(2)\n#define BIT_TXFF_PG_UDN_8814B BIT(1)\n#define BIT_TXFF_PG_OVF_8814B BIT(0)\n\n/* 2 REG_TX_DMA_DBG_8814B */\n\n/* 2 REG_DMA_RQPN_INFO_PUB_8814B */\n\n#define BIT_SHIFT_PUB_AVAL_PG_8814B 16\n#define BIT_MASK_PUB_AVAL_PG_8814B 0xfff\n#define BIT_PUB_AVAL_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_PUB_AVAL_PG_8814B) << BIT_SHIFT_PUB_AVAL_PG_8814B)\n#define BITS_PUB_AVAL_PG_8814B                                                 \\\n\t(BIT_MASK_PUB_AVAL_PG_8814B << BIT_SHIFT_PUB_AVAL_PG_8814B)\n#define BIT_CLEAR_PUB_AVAL_PG_8814B(x) ((x) & (~BITS_PUB_AVAL_PG_8814B))\n#define BIT_GET_PUB_AVAL_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_PUB_AVAL_PG_8814B) & BIT_MASK_PUB_AVAL_PG_8814B)\n#define BIT_SET_PUB_AVAL_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_PUB_AVAL_PG_8814B(x) | BIT_PUB_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_PUB_RSVD_PG_8814B 0\n#define BIT_MASK_PUB_RSVD_PG_8814B 0xfff\n#define BIT_PUB_RSVD_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_PUB_RSVD_PG_8814B) << BIT_SHIFT_PUB_RSVD_PG_8814B)\n#define BITS_PUB_RSVD_PG_8814B                                                 \\\n\t(BIT_MASK_PUB_RSVD_PG_8814B << BIT_SHIFT_PUB_RSVD_PG_8814B)\n#define BIT_CLEAR_PUB_RSVD_PG_8814B(x) ((x) & (~BITS_PUB_RSVD_PG_8814B))\n#define BIT_GET_PUB_RSVD_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_PUB_RSVD_PG_8814B) & BIT_MASK_PUB_RSVD_PG_8814B)\n#define BIT_SET_PUB_RSVD_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_PUB_RSVD_PG_8814B(x) | BIT_PUB_RSVD_PG_8814B(v))\n\n/* 2 REG_RQPN_CTRL_2_V1_8814B */\n#define BIT_LD_RQPN_V1_8814B BIT(31)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_CH16_PUBLIC_DIS_8814B BIT(16)\n#define BIT_CH15_PUBLIC_DIS_8814B BIT(15)\n#define BIT_CH14_PUBLIC_DIS_8814B BIT(14)\n#define BIT_CH13_PUBLIC_DIS_8814B BIT(13)\n#define BIT_CH12_PUBLIC_DIS_8814B BIT(12)\n#define BIT_CH11_PUBLIC_DIS_8814B BIT(11)\n#define BIT_CH10_PUBLIC_DIS_8814B BIT(10)\n#define BIT_CH9_PUBLIC_DIS_8814B BIT(9)\n#define BIT_CH8_PUBLIC_DIS_8814B BIT(8)\n#define BIT_CH7_PUBLIC_DIS_8814B BIT(7)\n#define BIT_CH6_PUBLIC_DIS_8814B BIT(6)\n#define BIT_CH5_PUBLIC_DIS_8814B BIT(5)\n#define BIT_CH4_PUBLIC_DIS_8814B BIT(4)\n#define BIT_CH3_PUBLIC_DIS_8814B BIT(3)\n#define BIT_CH2_PUBLIC_DIS_8814B BIT(2)\n#define BIT_CH1_PUBLIC_DIS_8814B BIT(1)\n#define BIT_CH0_PUBLIC_DIS_8814B BIT(0)\n\n/* 2 REG_BCN_CTRL_2_8814B */\n#define BIT_BCN0_EXT_VALID_8814B BIT(31)\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_BCN0_EXT_HEAD_8814B 16\n#define BIT_MASK_BCN0_EXT_HEAD_8814B 0xfff\n#define BIT_BCN0_EXT_HEAD_8814B(x)                                             \\\n\t(((x) & BIT_MASK_BCN0_EXT_HEAD_8814B) << BIT_SHIFT_BCN0_EXT_HEAD_8814B)\n#define BITS_BCN0_EXT_HEAD_8814B                                               \\\n\t(BIT_MASK_BCN0_EXT_HEAD_8814B << BIT_SHIFT_BCN0_EXT_HEAD_8814B)\n#define BIT_CLEAR_BCN0_EXT_HEAD_8814B(x) ((x) & (~BITS_BCN0_EXT_HEAD_8814B))\n#define BIT_GET_BCN0_EXT_HEAD_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_BCN0_EXT_HEAD_8814B) & BIT_MASK_BCN0_EXT_HEAD_8814B)\n#define BIT_SET_BCN0_EXT_HEAD_8814B(x, v)                                      \\\n\t(BIT_CLEAR_BCN0_EXT_HEAD_8814B(x) | BIT_BCN0_EXT_HEAD_8814B(v))\n\n#define BIT_BCN4_VALID_8814B BIT(15)\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_BCN4_HEAD_8814B 0\n#define BIT_MASK_BCN4_HEAD_8814B 0xfff\n#define BIT_BCN4_HEAD_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_BCN4_HEAD_8814B) << BIT_SHIFT_BCN4_HEAD_8814B)\n#define BITS_BCN4_HEAD_8814B                                                   \\\n\t(BIT_MASK_BCN4_HEAD_8814B << BIT_SHIFT_BCN4_HEAD_8814B)\n#define BIT_CLEAR_BCN4_HEAD_8814B(x) ((x) & (~BITS_BCN4_HEAD_8814B))\n#define BIT_GET_BCN4_HEAD_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCN4_HEAD_8814B) & BIT_MASK_BCN4_HEAD_8814B)\n#define BIT_SET_BCN4_HEAD_8814B(x, v)                                          \\\n\t(BIT_CLEAR_BCN4_HEAD_8814B(x) | BIT_BCN4_HEAD_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_TXPKTNUM_0_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_TXPKTNUM_CH4_7_8814B 16\n#define BIT_MASK_TXPKTNUM_CH4_7_8814B 0xfff\n#define BIT_TXPKTNUM_CH4_7_8814B(x)                                            \\\n\t(((x) & BIT_MASK_TXPKTNUM_CH4_7_8814B)                                 \\\n\t << BIT_SHIFT_TXPKTNUM_CH4_7_8814B)\n#define BITS_TXPKTNUM_CH4_7_8814B                                              \\\n\t(BIT_MASK_TXPKTNUM_CH4_7_8814B << BIT_SHIFT_TXPKTNUM_CH4_7_8814B)\n#define BIT_CLEAR_TXPKTNUM_CH4_7_8814B(x) ((x) & (~BITS_TXPKTNUM_CH4_7_8814B))\n#define BIT_GET_TXPKTNUM_CH4_7_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_CH4_7_8814B) &                             \\\n\t BIT_MASK_TXPKTNUM_CH4_7_8814B)\n#define BIT_SET_TXPKTNUM_CH4_7_8814B(x, v)                                     \\\n\t(BIT_CLEAR_TXPKTNUM_CH4_7_8814B(x) | BIT_TXPKTNUM_CH4_7_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_TXPKTNUM_CH0_3_8814B 0\n#define BIT_MASK_TXPKTNUM_CH0_3_8814B 0xfff\n#define BIT_TXPKTNUM_CH0_3_8814B(x)                                            \\\n\t(((x) & BIT_MASK_TXPKTNUM_CH0_3_8814B)                                 \\\n\t << BIT_SHIFT_TXPKTNUM_CH0_3_8814B)\n#define BITS_TXPKTNUM_CH0_3_8814B                                              \\\n\t(BIT_MASK_TXPKTNUM_CH0_3_8814B << BIT_SHIFT_TXPKTNUM_CH0_3_8814B)\n#define BIT_CLEAR_TXPKTNUM_CH0_3_8814B(x) ((x) & (~BITS_TXPKTNUM_CH0_3_8814B))\n#define BIT_GET_TXPKTNUM_CH0_3_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_CH0_3_8814B) &                             \\\n\t BIT_MASK_TXPKTNUM_CH0_3_8814B)\n#define BIT_SET_TXPKTNUM_CH0_3_8814B(x, v)                                     \\\n\t(BIT_CLEAR_TXPKTNUM_CH0_3_8814B(x) | BIT_TXPKTNUM_CH0_3_8814B(v))\n\n/* 2 REG_TXPKTNUM_1_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_TXPKTNUM_CH12_8814B 16\n#define BIT_MASK_TXPKTNUM_CH12_8814B 0xfff\n#define BIT_TXPKTNUM_CH12_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TXPKTNUM_CH12_8814B) << BIT_SHIFT_TXPKTNUM_CH12_8814B)\n#define BITS_TXPKTNUM_CH12_8814B                                               \\\n\t(BIT_MASK_TXPKTNUM_CH12_8814B << BIT_SHIFT_TXPKTNUM_CH12_8814B)\n#define BIT_CLEAR_TXPKTNUM_CH12_8814B(x) ((x) & (~BITS_TXPKTNUM_CH12_8814B))\n#define BIT_GET_TXPKTNUM_CH12_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_CH12_8814B) & BIT_MASK_TXPKTNUM_CH12_8814B)\n#define BIT_SET_TXPKTNUM_CH12_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TXPKTNUM_CH12_8814B(x) | BIT_TXPKTNUM_CH12_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_TXPKTNUM_CH8_11_8814B 0\n#define BIT_MASK_TXPKTNUM_CH8_11_8814B 0xfff\n#define BIT_TXPKTNUM_CH8_11_8814B(x)                                           \\\n\t(((x) & BIT_MASK_TXPKTNUM_CH8_11_8814B)                                \\\n\t << BIT_SHIFT_TXPKTNUM_CH8_11_8814B)\n#define BITS_TXPKTNUM_CH8_11_8814B                                             \\\n\t(BIT_MASK_TXPKTNUM_CH8_11_8814B << BIT_SHIFT_TXPKTNUM_CH8_11_8814B)\n#define BIT_CLEAR_TXPKTNUM_CH8_11_8814B(x) ((x) & (~BITS_TXPKTNUM_CH8_11_8814B))\n#define BIT_GET_TXPKTNUM_CH8_11_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_CH8_11_8814B) &                            \\\n\t BIT_MASK_TXPKTNUM_CH8_11_8814B)\n#define BIT_SET_TXPKTNUM_CH8_11_8814B(x, v)                                    \\\n\t(BIT_CLEAR_TXPKTNUM_CH8_11_8814B(x) | BIT_TXPKTNUM_CH8_11_8814B(v))\n\n/* 2 REG_TXPKTNUM_2_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_TXPKTNUM_CH14_15_8814B 16\n#define BIT_MASK_TXPKTNUM_CH14_15_8814B 0xfff\n#define BIT_TXPKTNUM_CH14_15_8814B(x)                                          \\\n\t(((x) & BIT_MASK_TXPKTNUM_CH14_15_8814B)                               \\\n\t << BIT_SHIFT_TXPKTNUM_CH14_15_8814B)\n#define BITS_TXPKTNUM_CH14_15_8814B                                            \\\n\t(BIT_MASK_TXPKTNUM_CH14_15_8814B << BIT_SHIFT_TXPKTNUM_CH14_15_8814B)\n#define BIT_CLEAR_TXPKTNUM_CH14_15_8814B(x)                                    \\\n\t((x) & (~BITS_TXPKTNUM_CH14_15_8814B))\n#define BIT_GET_TXPKTNUM_CH14_15_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_CH14_15_8814B) &                           \\\n\t BIT_MASK_TXPKTNUM_CH14_15_8814B)\n#define BIT_SET_TXPKTNUM_CH14_15_8814B(x, v)                                   \\\n\t(BIT_CLEAR_TXPKTNUM_CH14_15_8814B(x) | BIT_TXPKTNUM_CH14_15_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_TXPKTNUM_CH13_8814B 0\n#define BIT_MASK_TXPKTNUM_CH13_8814B 0xfff\n#define BIT_TXPKTNUM_CH13_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TXPKTNUM_CH13_8814B) << BIT_SHIFT_TXPKTNUM_CH13_8814B)\n#define BITS_TXPKTNUM_CH13_8814B                                               \\\n\t(BIT_MASK_TXPKTNUM_CH13_8814B << BIT_SHIFT_TXPKTNUM_CH13_8814B)\n#define BIT_CLEAR_TXPKTNUM_CH13_8814B(x) ((x) & (~BITS_TXPKTNUM_CH13_8814B))\n#define BIT_GET_TXPKTNUM_CH13_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_CH13_8814B) & BIT_MASK_TXPKTNUM_CH13_8814B)\n#define BIT_SET_TXPKTNUM_CH13_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TXPKTNUM_CH13_8814B(x) | BIT_TXPKTNUM_CH13_8814B(v))\n\n/* 2 REG_TXPKTNUM_3_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_TXPKTNUM_CH16_8814B 0\n#define BIT_MASK_TXPKTNUM_CH16_8814B 0xfff\n#define BIT_TXPKTNUM_CH16_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TXPKTNUM_CH16_8814B) << BIT_SHIFT_TXPKTNUM_CH16_8814B)\n#define BITS_TXPKTNUM_CH16_8814B                                               \\\n\t(BIT_MASK_TXPKTNUM_CH16_8814B << BIT_SHIFT_TXPKTNUM_CH16_8814B)\n#define BIT_CLEAR_TXPKTNUM_CH16_8814B(x) ((x) & (~BITS_TXPKTNUM_CH16_8814B))\n#define BIT_GET_TXPKTNUM_CH16_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_CH16_8814B) & BIT_MASK_TXPKTNUM_CH16_8814B)\n#define BIT_SET_TXPKTNUM_CH16_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TXPKTNUM_CH16_8814B(x) | BIT_TXPKTNUM_CH16_8814B(v))\n\n/* 2 REG_TX_AGG_ALIGN_8814B */\n\n#define BIT_SHIFT_HW_FLOW_CTL_EN_8814B 16\n#define BIT_MASK_HW_FLOW_CTL_EN_8814B 0xffff\n#define BIT_HW_FLOW_CTL_EN_8814B(x)                                            \\\n\t(((x) & BIT_MASK_HW_FLOW_CTL_EN_8814B)                                 \\\n\t << BIT_SHIFT_HW_FLOW_CTL_EN_8814B)\n#define BITS_HW_FLOW_CTL_EN_8814B                                              \\\n\t(BIT_MASK_HW_FLOW_CTL_EN_8814B << BIT_SHIFT_HW_FLOW_CTL_EN_8814B)\n#define BIT_CLEAR_HW_FLOW_CTL_EN_8814B(x) ((x) & (~BITS_HW_FLOW_CTL_EN_8814B))\n#define BIT_GET_HW_FLOW_CTL_EN_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HW_FLOW_CTL_EN_8814B) &                             \\\n\t BIT_MASK_HW_FLOW_CTL_EN_8814B)\n#define BIT_SET_HW_FLOW_CTL_EN_8814B(x, v)                                     \\\n\t(BIT_CLEAR_HW_FLOW_CTL_EN_8814B(x) | BIT_HW_FLOW_CTL_EN_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_V1_8814B BIT(15)\n\n#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B 0\n#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B 0xfff\n#define BIT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x)                                  \\\n\t(((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B)                       \\\n\t << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B)\n#define BITS_SDIO_TXAGG_ALIGN_SIZE_V1_8814B                                    \\\n\t(BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B                               \\\n\t << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B)\n#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x)                            \\\n\t((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_V1_8814B))\n#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x)                              \\\n\t(((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B) &                   \\\n\t BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B)\n#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x, v)                           \\\n\t(BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x) |                         \\\n\t BIT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(v))\n\n/* 2 REG_H2C_HEAD_8814B */\n\n#define BIT_SHIFT_H2C_HEAD_V1_8814B 0\n#define BIT_MASK_H2C_HEAD_V1_8814B 0x7ffff\n#define BIT_H2C_HEAD_V1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_H2C_HEAD_V1_8814B) << BIT_SHIFT_H2C_HEAD_V1_8814B)\n#define BITS_H2C_HEAD_V1_8814B                                                 \\\n\t(BIT_MASK_H2C_HEAD_V1_8814B << BIT_SHIFT_H2C_HEAD_V1_8814B)\n#define BIT_CLEAR_H2C_HEAD_V1_8814B(x) ((x) & (~BITS_H2C_HEAD_V1_8814B))\n#define BIT_GET_H2C_HEAD_V1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_H2C_HEAD_V1_8814B) & BIT_MASK_H2C_HEAD_V1_8814B)\n#define BIT_SET_H2C_HEAD_V1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_H2C_HEAD_V1_8814B(x) | BIT_H2C_HEAD_V1_8814B(v))\n\n/* 2 REG_H2C_TAIL_8814B */\n\n#define BIT_SHIFT_H2C_TAIL_V1_8814B 0\n#define BIT_MASK_H2C_TAIL_V1_8814B 0x7ffff\n#define BIT_H2C_TAIL_V1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_H2C_TAIL_V1_8814B) << BIT_SHIFT_H2C_TAIL_V1_8814B)\n#define BITS_H2C_TAIL_V1_8814B                                                 \\\n\t(BIT_MASK_H2C_TAIL_V1_8814B << BIT_SHIFT_H2C_TAIL_V1_8814B)\n#define BIT_CLEAR_H2C_TAIL_V1_8814B(x) ((x) & (~BITS_H2C_TAIL_V1_8814B))\n#define BIT_GET_H2C_TAIL_V1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_H2C_TAIL_V1_8814B) & BIT_MASK_H2C_TAIL_V1_8814B)\n#define BIT_SET_H2C_TAIL_V1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_H2C_TAIL_V1_8814B(x) | BIT_H2C_TAIL_V1_8814B(v))\n\n/* 2 REG_H2C_READ_ADDR_8814B */\n\n#define BIT_SHIFT_H2C_READ_ADDR_V1_8814B 0\n#define BIT_MASK_H2C_READ_ADDR_V1_8814B 0x7ffff\n#define BIT_H2C_READ_ADDR_V1_8814B(x)                                          \\\n\t(((x) & BIT_MASK_H2C_READ_ADDR_V1_8814B)                               \\\n\t << BIT_SHIFT_H2C_READ_ADDR_V1_8814B)\n#define BITS_H2C_READ_ADDR_V1_8814B                                            \\\n\t(BIT_MASK_H2C_READ_ADDR_V1_8814B << BIT_SHIFT_H2C_READ_ADDR_V1_8814B)\n#define BIT_CLEAR_H2C_READ_ADDR_V1_8814B(x)                                    \\\n\t((x) & (~BITS_H2C_READ_ADDR_V1_8814B))\n#define BIT_GET_H2C_READ_ADDR_V1_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_H2C_READ_ADDR_V1_8814B) &                           \\\n\t BIT_MASK_H2C_READ_ADDR_V1_8814B)\n#define BIT_SET_H2C_READ_ADDR_V1_8814B(x, v)                                   \\\n\t(BIT_CLEAR_H2C_READ_ADDR_V1_8814B(x) | BIT_H2C_READ_ADDR_V1_8814B(v))\n\n/* 2 REG_H2C_WR_ADDR_8814B */\n\n#define BIT_SHIFT_H2C_WR_ADDR_V1_8814B 0\n#define BIT_MASK_H2C_WR_ADDR_V1_8814B 0x7ffff\n#define BIT_H2C_WR_ADDR_V1_8814B(x)                                            \\\n\t(((x) & BIT_MASK_H2C_WR_ADDR_V1_8814B)                                 \\\n\t << BIT_SHIFT_H2C_WR_ADDR_V1_8814B)\n#define BITS_H2C_WR_ADDR_V1_8814B                                              \\\n\t(BIT_MASK_H2C_WR_ADDR_V1_8814B << BIT_SHIFT_H2C_WR_ADDR_V1_8814B)\n#define BIT_CLEAR_H2C_WR_ADDR_V1_8814B(x) ((x) & (~BITS_H2C_WR_ADDR_V1_8814B))\n#define BIT_GET_H2C_WR_ADDR_V1_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_H2C_WR_ADDR_V1_8814B) &                             \\\n\t BIT_MASK_H2C_WR_ADDR_V1_8814B)\n#define BIT_SET_H2C_WR_ADDR_V1_8814B(x, v)                                     \\\n\t(BIT_CLEAR_H2C_WR_ADDR_V1_8814B(x) | BIT_H2C_WR_ADDR_V1_8814B(v))\n\n/* 2 REG_H2C_INFO_8814B */\n#define BIT_H2C_SPACE_VLD_8814B BIT(3)\n#define BIT_H2C_WR_ADDR_RST_8814B BIT(2)\n\n#define BIT_SHIFT_H2C_LEN_SEL_8814B 0\n#define BIT_MASK_H2C_LEN_SEL_8814B 0x3\n#define BIT_H2C_LEN_SEL_8814B(x)                                               \\\n\t(((x) & BIT_MASK_H2C_LEN_SEL_8814B) << BIT_SHIFT_H2C_LEN_SEL_8814B)\n#define BITS_H2C_LEN_SEL_8814B                                                 \\\n\t(BIT_MASK_H2C_LEN_SEL_8814B << BIT_SHIFT_H2C_LEN_SEL_8814B)\n#define BIT_CLEAR_H2C_LEN_SEL_8814B(x) ((x) & (~BITS_H2C_LEN_SEL_8814B))\n#define BIT_GET_H2C_LEN_SEL_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_H2C_LEN_SEL_8814B) & BIT_MASK_H2C_LEN_SEL_8814B)\n#define BIT_SET_H2C_LEN_SEL_8814B(x, v)                                        \\\n\t(BIT_CLEAR_H2C_LEN_SEL_8814B(x) | BIT_H2C_LEN_SEL_8814B(v))\n\n/* 2 REG_DMA_OQT_0_8814B */\n\n#define BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B 24\n#define BIT_MASK_TX_OQT_12_FREE_SPACE_8814B 0xff\n#define BIT_TX_OQT_12_FREE_SPACE_8814B(x)                                      \\\n\t(((x) & BIT_MASK_TX_OQT_12_FREE_SPACE_8814B)                           \\\n\t << BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B)\n#define BITS_TX_OQT_12_FREE_SPACE_8814B                                        \\\n\t(BIT_MASK_TX_OQT_12_FREE_SPACE_8814B                                   \\\n\t << BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B)\n#define BIT_CLEAR_TX_OQT_12_FREE_SPACE_8814B(x)                                \\\n\t((x) & (~BITS_TX_OQT_12_FREE_SPACE_8814B))\n#define BIT_GET_TX_OQT_12_FREE_SPACE_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B) &                       \\\n\t BIT_MASK_TX_OQT_12_FREE_SPACE_8814B)\n#define BIT_SET_TX_OQT_12_FREE_SPACE_8814B(x, v)                               \\\n\t(BIT_CLEAR_TX_OQT_12_FREE_SPACE_8814B(x) |                             \\\n\t BIT_TX_OQT_12_FREE_SPACE_8814B(v))\n\n#define BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B 16\n#define BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B 0xff\n#define BIT_TX_OQT_8_11_FREE_SPACE_8814B(x)                                    \\\n\t(((x) & BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B)                         \\\n\t << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B)\n#define BITS_TX_OQT_8_11_FREE_SPACE_8814B                                      \\\n\t(BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B                                 \\\n\t << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B)\n#define BIT_CLEAR_TX_OQT_8_11_FREE_SPACE_8814B(x)                              \\\n\t((x) & (~BITS_TX_OQT_8_11_FREE_SPACE_8814B))\n#define BIT_GET_TX_OQT_8_11_FREE_SPACE_8814B(x)                                \\\n\t(((x) >> BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B) &                     \\\n\t BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B)\n#define BIT_SET_TX_OQT_8_11_FREE_SPACE_8814B(x, v)                             \\\n\t(BIT_CLEAR_TX_OQT_8_11_FREE_SPACE_8814B(x) |                           \\\n\t BIT_TX_OQT_8_11_FREE_SPACE_8814B(v))\n\n#define BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B 8\n#define BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B 0xff\n#define BIT_TX_OQT_4_7_FREE_SPACE_8814B(x)                                     \\\n\t(((x) & BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B)                          \\\n\t << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B)\n#define BITS_TX_OQT_4_7_FREE_SPACE_8814B                                       \\\n\t(BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B                                  \\\n\t << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B)\n#define BIT_CLEAR_TX_OQT_4_7_FREE_SPACE_8814B(x)                               \\\n\t((x) & (~BITS_TX_OQT_4_7_FREE_SPACE_8814B))\n#define BIT_GET_TX_OQT_4_7_FREE_SPACE_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B) &                      \\\n\t BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B)\n#define BIT_SET_TX_OQT_4_7_FREE_SPACE_8814B(x, v)                              \\\n\t(BIT_CLEAR_TX_OQT_4_7_FREE_SPACE_8814B(x) |                            \\\n\t BIT_TX_OQT_4_7_FREE_SPACE_8814B(v))\n\n#define BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B 0\n#define BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B 0xff\n#define BIT_TX_OQT_0_3_FREE_SPACE_8814B(x)                                     \\\n\t(((x) & BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B)                          \\\n\t << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B)\n#define BITS_TX_OQT_0_3_FREE_SPACE_8814B                                       \\\n\t(BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B                                  \\\n\t << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B)\n#define BIT_CLEAR_TX_OQT_0_3_FREE_SPACE_8814B(x)                               \\\n\t((x) & (~BITS_TX_OQT_0_3_FREE_SPACE_8814B))\n#define BIT_GET_TX_OQT_0_3_FREE_SPACE_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B) &                      \\\n\t BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B)\n#define BIT_SET_TX_OQT_0_3_FREE_SPACE_8814B(x, v)                              \\\n\t(BIT_CLEAR_TX_OQT_0_3_FREE_SPACE_8814B(x) |                            \\\n\t BIT_TX_OQT_0_3_FREE_SPACE_8814B(v))\n\n/* 2 REG_DMA_OQT_1_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B 16\n#define BIT_MASK_TX_OQT_16_FREE_SPACE_8814B 0xff\n#define BIT_TX_OQT_16_FREE_SPACE_8814B(x)                                      \\\n\t(((x) & BIT_MASK_TX_OQT_16_FREE_SPACE_8814B)                           \\\n\t << BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B)\n#define BITS_TX_OQT_16_FREE_SPACE_8814B                                        \\\n\t(BIT_MASK_TX_OQT_16_FREE_SPACE_8814B                                   \\\n\t << BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B)\n#define BIT_CLEAR_TX_OQT_16_FREE_SPACE_8814B(x)                                \\\n\t((x) & (~BITS_TX_OQT_16_FREE_SPACE_8814B))\n#define BIT_GET_TX_OQT_16_FREE_SPACE_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B) &                       \\\n\t BIT_MASK_TX_OQT_16_FREE_SPACE_8814B)\n#define BIT_SET_TX_OQT_16_FREE_SPACE_8814B(x, v)                               \\\n\t(BIT_CLEAR_TX_OQT_16_FREE_SPACE_8814B(x) |                             \\\n\t BIT_TX_OQT_16_FREE_SPACE_8814B(v))\n\n#define BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B 8\n#define BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B 0xff\n#define BIT_TX_OQT_14_15_FREE_SPACE_8814B(x)                                   \\\n\t(((x) & BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B)                        \\\n\t << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B)\n#define BITS_TX_OQT_14_15_FREE_SPACE_8814B                                     \\\n\t(BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B                                \\\n\t << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B)\n#define BIT_CLEAR_TX_OQT_14_15_FREE_SPACE_8814B(x)                             \\\n\t((x) & (~BITS_TX_OQT_14_15_FREE_SPACE_8814B))\n#define BIT_GET_TX_OQT_14_15_FREE_SPACE_8814B(x)                               \\\n\t(((x) >> BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B) &                    \\\n\t BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B)\n#define BIT_SET_TX_OQT_14_15_FREE_SPACE_8814B(x, v)                            \\\n\t(BIT_CLEAR_TX_OQT_14_15_FREE_SPACE_8814B(x) |                          \\\n\t BIT_TX_OQT_14_15_FREE_SPACE_8814B(v))\n\n#define BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B 0\n#define BIT_MASK_TX_OQT_13_FREE_SPACE_8814B 0xff\n#define BIT_TX_OQT_13_FREE_SPACE_8814B(x)                                      \\\n\t(((x) & BIT_MASK_TX_OQT_13_FREE_SPACE_8814B)                           \\\n\t << BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B)\n#define BITS_TX_OQT_13_FREE_SPACE_8814B                                        \\\n\t(BIT_MASK_TX_OQT_13_FREE_SPACE_8814B                                   \\\n\t << BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B)\n#define BIT_CLEAR_TX_OQT_13_FREE_SPACE_8814B(x)                                \\\n\t((x) & (~BITS_TX_OQT_13_FREE_SPACE_8814B))\n#define BIT_GET_TX_OQT_13_FREE_SPACE_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B) &                       \\\n\t BIT_MASK_TX_OQT_13_FREE_SPACE_8814B)\n#define BIT_SET_TX_OQT_13_FREE_SPACE_8814B(x, v)                               \\\n\t(BIT_CLEAR_TX_OQT_13_FREE_SPACE_8814B(x) |                             \\\n\t BIT_TX_OQT_13_FREE_SPACE_8814B(v))\n\n/* 2 REG_RXDMA_AGG_PG_TH_8814B */\n#define BIT_DMA_STORE_8814B BIT(31)\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_EN_PRE_CALC_8814B BIT(29)\n#define BIT_RXAGG_SW_EN_8814B BIT(28)\n#define BIT_RXAGG_SW_TRIG_8814B BIT(27)\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_DMA_AGG_TO_V1_8814B 8\n#define BIT_MASK_DMA_AGG_TO_V1_8814B 0xff\n#define BIT_DMA_AGG_TO_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_DMA_AGG_TO_V1_8814B) << BIT_SHIFT_DMA_AGG_TO_V1_8814B)\n#define BITS_DMA_AGG_TO_V1_8814B                                               \\\n\t(BIT_MASK_DMA_AGG_TO_V1_8814B << BIT_SHIFT_DMA_AGG_TO_V1_8814B)\n#define BIT_CLEAR_DMA_AGG_TO_V1_8814B(x) ((x) & (~BITS_DMA_AGG_TO_V1_8814B))\n#define BIT_GET_DMA_AGG_TO_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8814B) & BIT_MASK_DMA_AGG_TO_V1_8814B)\n#define BIT_SET_DMA_AGG_TO_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_DMA_AGG_TO_V1_8814B(x) | BIT_DMA_AGG_TO_V1_8814B(v))\n\n#define BIT_SHIFT_RXDMA_AGG_PG_TH_8814B 0\n#define BIT_MASK_RXDMA_AGG_PG_TH_8814B 0xff\n#define BIT_RXDMA_AGG_PG_TH_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RXDMA_AGG_PG_TH_8814B)                                \\\n\t << BIT_SHIFT_RXDMA_AGG_PG_TH_8814B)\n#define BITS_RXDMA_AGG_PG_TH_8814B                                             \\\n\t(BIT_MASK_RXDMA_AGG_PG_TH_8814B << BIT_SHIFT_RXDMA_AGG_PG_TH_8814B)\n#define BIT_CLEAR_RXDMA_AGG_PG_TH_8814B(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8814B))\n#define BIT_GET_RXDMA_AGG_PG_TH_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8814B) &                            \\\n\t BIT_MASK_RXDMA_AGG_PG_TH_8814B)\n#define BIT_SET_RXDMA_AGG_PG_TH_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RXDMA_AGG_PG_TH_8814B(x) | BIT_RXDMA_AGG_PG_TH_8814B(v))\n\n/* 2 REG_RXDMA_CTRL_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B 20\n#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B 0xf\n#define BIT_FW_UPD_RDPTR19_TO_16_8814B(x)                                      \\\n\t(((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B)                           \\\n\t << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B)\n#define BITS_FW_UPD_RDPTR19_TO_16_8814B                                        \\\n\t(BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B                                   \\\n\t << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B)\n#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8814B(x)                                \\\n\t((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8814B))\n#define BIT_GET_FW_UPD_RDPTR19_TO_16_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B) &                       \\\n\t BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B)\n#define BIT_SET_FW_UPD_RDPTR19_TO_16_8814B(x, v)                               \\\n\t(BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8814B(x) |                             \\\n\t BIT_FW_UPD_RDPTR19_TO_16_8814B(v))\n\n#define BIT_RXDMA_REQ_8814B BIT(19)\n#define BIT_RW_RELEASE_EN_8814B BIT(18)\n#define BIT_RXDMA_IDLE_8814B BIT(17)\n#define BIT_RXPKT_RELEASE_POLL_8814B BIT(16)\n\n#define BIT_SHIFT_FW_UPD_RDPTR_8814B 0\n#define BIT_MASK_FW_UPD_RDPTR_8814B 0xffff\n#define BIT_FW_UPD_RDPTR_8814B(x)                                              \\\n\t(((x) & BIT_MASK_FW_UPD_RDPTR_8814B) << BIT_SHIFT_FW_UPD_RDPTR_8814B)\n#define BITS_FW_UPD_RDPTR_8814B                                                \\\n\t(BIT_MASK_FW_UPD_RDPTR_8814B << BIT_SHIFT_FW_UPD_RDPTR_8814B)\n#define BIT_CLEAR_FW_UPD_RDPTR_8814B(x) ((x) & (~BITS_FW_UPD_RDPTR_8814B))\n#define BIT_GET_FW_UPD_RDPTR_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_FW_UPD_RDPTR_8814B) & BIT_MASK_FW_UPD_RDPTR_8814B)\n#define BIT_SET_FW_UPD_RDPTR_8814B(x, v)                                       \\\n\t(BIT_CLEAR_FW_UPD_RDPTR_8814B(x) | BIT_FW_UPD_RDPTR_8814B(v))\n\n/* 2 REG_RXDMA_STATUS_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_C2H_PKT_OVF_8814B BIT(7)\n#define BIT_AGG_CONFGI_ISSUE_8814B BIT(6)\n#define BIT_FW_POLL_ISSUE_8814B BIT(5)\n#define BIT_RX_DATA_UDN_8814B BIT(4)\n#define BIT_RX_SFF_UDN_8814B BIT(3)\n#define BIT_RX_SFF_OVF_8814B BIT(2)\n#define BIT_RXPKT_OVF_8814B BIT(0)\n\n/* 2 REG_RXDMA_DPR_8814B */\n\n#define BIT_SHIFT_RDE_DEBUG_8814B 0\n#define BIT_MASK_RDE_DEBUG_8814B 0xffffffffL\n#define BIT_RDE_DEBUG_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_RDE_DEBUG_8814B) << BIT_SHIFT_RDE_DEBUG_8814B)\n#define BITS_RDE_DEBUG_8814B                                                   \\\n\t(BIT_MASK_RDE_DEBUG_8814B << BIT_SHIFT_RDE_DEBUG_8814B)\n#define BIT_CLEAR_RDE_DEBUG_8814B(x) ((x) & (~BITS_RDE_DEBUG_8814B))\n#define BIT_GET_RDE_DEBUG_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_RDE_DEBUG_8814B) & BIT_MASK_RDE_DEBUG_8814B)\n#define BIT_SET_RDE_DEBUG_8814B(x, v)                                          \\\n\t(BIT_CLEAR_RDE_DEBUG_8814B(x) | BIT_RDE_DEBUG_8814B(v))\n\n/* 2 REG_RXDMA_MODE_8814B */\n\n#define BIT_SHIFT_PKTNUM_TH_V2_8814B 24\n#define BIT_MASK_PKTNUM_TH_V2_8814B 0x1f\n#define BIT_PKTNUM_TH_V2_8814B(x)                                              \\\n\t(((x) & BIT_MASK_PKTNUM_TH_V2_8814B) << BIT_SHIFT_PKTNUM_TH_V2_8814B)\n#define BITS_PKTNUM_TH_V2_8814B                                                \\\n\t(BIT_MASK_PKTNUM_TH_V2_8814B << BIT_SHIFT_PKTNUM_TH_V2_8814B)\n#define BIT_CLEAR_PKTNUM_TH_V2_8814B(x) ((x) & (~BITS_PKTNUM_TH_V2_8814B))\n#define BIT_GET_PKTNUM_TH_V2_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_PKTNUM_TH_V2_8814B) & BIT_MASK_PKTNUM_TH_V2_8814B)\n#define BIT_SET_PKTNUM_TH_V2_8814B(x, v)                                       \\\n\t(BIT_CLEAR_PKTNUM_TH_V2_8814B(x) | BIT_PKTNUM_TH_V2_8814B(v))\n\n#define BIT_TXBA_BREAK_USBAGG_8814B BIT(23)\n\n#define BIT_SHIFT_PKTLEN_PARA_8814B 16\n#define BIT_MASK_PKTLEN_PARA_8814B 0x7\n#define BIT_PKTLEN_PARA_8814B(x)                                               \\\n\t(((x) & BIT_MASK_PKTLEN_PARA_8814B) << BIT_SHIFT_PKTLEN_PARA_8814B)\n#define BITS_PKTLEN_PARA_8814B                                                 \\\n\t(BIT_MASK_PKTLEN_PARA_8814B << BIT_SHIFT_PKTLEN_PARA_8814B)\n#define BIT_CLEAR_PKTLEN_PARA_8814B(x) ((x) & (~BITS_PKTLEN_PARA_8814B))\n#define BIT_GET_PKTLEN_PARA_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_PKTLEN_PARA_8814B) & BIT_MASK_PKTLEN_PARA_8814B)\n#define BIT_SET_PKTLEN_PARA_8814B(x, v)                                        \\\n\t(BIT_CLEAR_PKTLEN_PARA_8814B(x) | BIT_PKTLEN_PARA_8814B(v))\n\n#define BIT_RX_DBG_SEL_8814B BIT(7)\n#define BIT_EN_SPD_8814B BIT(6)\n\n#define BIT_SHIFT_BURST_SIZE_8814B 4\n#define BIT_MASK_BURST_SIZE_8814B 0x3\n#define BIT_BURST_SIZE_8814B(x)                                                \\\n\t(((x) & BIT_MASK_BURST_SIZE_8814B) << BIT_SHIFT_BURST_SIZE_8814B)\n#define BITS_BURST_SIZE_8814B                                                  \\\n\t(BIT_MASK_BURST_SIZE_8814B << BIT_SHIFT_BURST_SIZE_8814B)\n#define BIT_CLEAR_BURST_SIZE_8814B(x) ((x) & (~BITS_BURST_SIZE_8814B))\n#define BIT_GET_BURST_SIZE_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_BURST_SIZE_8814B) & BIT_MASK_BURST_SIZE_8814B)\n#define BIT_SET_BURST_SIZE_8814B(x, v)                                         \\\n\t(BIT_CLEAR_BURST_SIZE_8814B(x) | BIT_BURST_SIZE_8814B(v))\n\n#define BIT_SHIFT_BURST_CNT_8814B 2\n#define BIT_MASK_BURST_CNT_8814B 0x3\n#define BIT_BURST_CNT_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_BURST_CNT_8814B) << BIT_SHIFT_BURST_CNT_8814B)\n#define BITS_BURST_CNT_8814B                                                   \\\n\t(BIT_MASK_BURST_CNT_8814B << BIT_SHIFT_BURST_CNT_8814B)\n#define BIT_CLEAR_BURST_CNT_8814B(x) ((x) & (~BITS_BURST_CNT_8814B))\n#define BIT_GET_BURST_CNT_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_BURST_CNT_8814B) & BIT_MASK_BURST_CNT_8814B)\n#define BIT_SET_BURST_CNT_8814B(x, v)                                          \\\n\t(BIT_CLEAR_BURST_CNT_8814B(x) | BIT_BURST_CNT_8814B(v))\n\n#define BIT_DMA_MODE_8814B BIT(1)\n\n/* 2 REG_C2H_PKT_8814B */\n\n#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B 24\n#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B 0xf\n#define BIT_R_C2H_STR_ADDR_16_TO_19_8814B(x)                                   \\\n\t(((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B)                        \\\n\t << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B)\n#define BITS_R_C2H_STR_ADDR_16_TO_19_8814B                                     \\\n\t(BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B                                \\\n\t << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B)\n#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8814B(x)                             \\\n\t((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8814B))\n#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8814B(x)                               \\\n\t(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B) &                    \\\n\t BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B)\n#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8814B(x, v)                            \\\n\t(BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8814B(x) |                          \\\n\t BIT_R_C2H_STR_ADDR_16_TO_19_8814B(v))\n\n#define BIT_R_C2H_PKT_REQ_8814B BIT(16)\n\n#define BIT_SHIFT_R_C2H_STR_ADDR_8814B 0\n#define BIT_MASK_R_C2H_STR_ADDR_8814B 0xffff\n#define BIT_R_C2H_STR_ADDR_8814B(x)                                            \\\n\t(((x) & BIT_MASK_R_C2H_STR_ADDR_8814B)                                 \\\n\t << BIT_SHIFT_R_C2H_STR_ADDR_8814B)\n#define BITS_R_C2H_STR_ADDR_8814B                                              \\\n\t(BIT_MASK_R_C2H_STR_ADDR_8814B << BIT_SHIFT_R_C2H_STR_ADDR_8814B)\n#define BIT_CLEAR_R_C2H_STR_ADDR_8814B(x) ((x) & (~BITS_R_C2H_STR_ADDR_8814B))\n#define BIT_GET_R_C2H_STR_ADDR_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8814B) &                             \\\n\t BIT_MASK_R_C2H_STR_ADDR_8814B)\n#define BIT_SET_R_C2H_STR_ADDR_8814B(x, v)                                     \\\n\t(BIT_CLEAR_R_C2H_STR_ADDR_8814B(x) | BIT_R_C2H_STR_ADDR_8814B(v))\n\n/* 2 REG_FWFF_C2H_8814B */\n\n#define BIT_SHIFT_C2H_DMA_ADDR_8814B 0\n#define BIT_MASK_C2H_DMA_ADDR_8814B 0x3ffff\n#define BIT_C2H_DMA_ADDR_8814B(x)                                              \\\n\t(((x) & BIT_MASK_C2H_DMA_ADDR_8814B) << BIT_SHIFT_C2H_DMA_ADDR_8814B)\n#define BITS_C2H_DMA_ADDR_8814B                                                \\\n\t(BIT_MASK_C2H_DMA_ADDR_8814B << BIT_SHIFT_C2H_DMA_ADDR_8814B)\n#define BIT_CLEAR_C2H_DMA_ADDR_8814B(x) ((x) & (~BITS_C2H_DMA_ADDR_8814B))\n#define BIT_GET_C2H_DMA_ADDR_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_C2H_DMA_ADDR_8814B) & BIT_MASK_C2H_DMA_ADDR_8814B)\n#define BIT_SET_C2H_DMA_ADDR_8814B(x, v)                                       \\\n\t(BIT_CLEAR_C2H_DMA_ADDR_8814B(x) | BIT_C2H_DMA_ADDR_8814B(v))\n\n/* 2 REG_FWFF_CTRL_8814B */\n#define BIT_FWFF_DMAPKT_REQ_8814B BIT(31)\n\n#define BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B 16\n#define BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B 0x7fff\n#define BIT_FWFF_DMA_PKT_NUM_V1_8814B(x)                                       \\\n\t(((x) & BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B)                            \\\n\t << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B)\n#define BITS_FWFF_DMA_PKT_NUM_V1_8814B                                         \\\n\t(BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B                                    \\\n\t << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B)\n#define BIT_CLEAR_FWFF_DMA_PKT_NUM_V1_8814B(x)                                 \\\n\t((x) & (~BITS_FWFF_DMA_PKT_NUM_V1_8814B))\n#define BIT_GET_FWFF_DMA_PKT_NUM_V1_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B) &                        \\\n\t BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B)\n#define BIT_SET_FWFF_DMA_PKT_NUM_V1_8814B(x, v)                                \\\n\t(BIT_CLEAR_FWFF_DMA_PKT_NUM_V1_8814B(x) |                              \\\n\t BIT_FWFF_DMA_PKT_NUM_V1_8814B(v))\n\n#define BIT_SHIFT_FWFF_STR_ADDR_8814B 0\n#define BIT_MASK_FWFF_STR_ADDR_8814B 0xffff\n#define BIT_FWFF_STR_ADDR_8814B(x)                                             \\\n\t(((x) & BIT_MASK_FWFF_STR_ADDR_8814B) << BIT_SHIFT_FWFF_STR_ADDR_8814B)\n#define BITS_FWFF_STR_ADDR_8814B                                               \\\n\t(BIT_MASK_FWFF_STR_ADDR_8814B << BIT_SHIFT_FWFF_STR_ADDR_8814B)\n#define BIT_CLEAR_FWFF_STR_ADDR_8814B(x) ((x) & (~BITS_FWFF_STR_ADDR_8814B))\n#define BIT_GET_FWFF_STR_ADDR_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_FWFF_STR_ADDR_8814B) & BIT_MASK_FWFF_STR_ADDR_8814B)\n#define BIT_SET_FWFF_STR_ADDR_8814B(x, v)                                      \\\n\t(BIT_CLEAR_FWFF_STR_ADDR_8814B(x) | BIT_FWFF_STR_ADDR_8814B(v))\n\n/* 2 REG_FWFF_PKT_INFO_8814B */\n\n#define BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B 16\n#define BIT_MASK_FWFF_PKT_READ_ADDR_8814B 0xffff\n#define BIT_FWFF_PKT_READ_ADDR_8814B(x)                                        \\\n\t(((x) & BIT_MASK_FWFF_PKT_READ_ADDR_8814B)                             \\\n\t << BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B)\n#define BITS_FWFF_PKT_READ_ADDR_8814B                                          \\\n\t(BIT_MASK_FWFF_PKT_READ_ADDR_8814B                                     \\\n\t << BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B)\n#define BIT_CLEAR_FWFF_PKT_READ_ADDR_8814B(x)                                  \\\n\t((x) & (~BITS_FWFF_PKT_READ_ADDR_8814B))\n#define BIT_GET_FWFF_PKT_READ_ADDR_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B) &                         \\\n\t BIT_MASK_FWFF_PKT_READ_ADDR_8814B)\n#define BIT_SET_FWFF_PKT_READ_ADDR_8814B(x, v)                                 \\\n\t(BIT_CLEAR_FWFF_PKT_READ_ADDR_8814B(x) |                               \\\n\t BIT_FWFF_PKT_READ_ADDR_8814B(v))\n\n#define BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B 0\n#define BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B 0xffff\n#define BIT_FWFF_PKT_WRITE_ADDR_8814B(x)                                       \\\n\t(((x) & BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B)                            \\\n\t << BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B)\n#define BITS_FWFF_PKT_WRITE_ADDR_8814B                                         \\\n\t(BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B                                    \\\n\t << BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B)\n#define BIT_CLEAR_FWFF_PKT_WRITE_ADDR_8814B(x)                                 \\\n\t((x) & (~BITS_FWFF_PKT_WRITE_ADDR_8814B))\n#define BIT_GET_FWFF_PKT_WRITE_ADDR_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B) &                        \\\n\t BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B)\n#define BIT_SET_FWFF_PKT_WRITE_ADDR_8814B(x, v)                                \\\n\t(BIT_CLEAR_FWFF_PKT_WRITE_ADDR_8814B(x) |                              \\\n\t BIT_FWFF_PKT_WRITE_ADDR_8814B(v))\n\n/* 2 REG_FWFF_PKT_INFO2_8814B */\n\n#define BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B 0\n#define BIT_MASK_FWFF_PKT_QUEUED_V1_8814B 0xffff\n#define BIT_FWFF_PKT_QUEUED_V1_8814B(x)                                        \\\n\t(((x) & BIT_MASK_FWFF_PKT_QUEUED_V1_8814B)                             \\\n\t << BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B)\n#define BITS_FWFF_PKT_QUEUED_V1_8814B                                          \\\n\t(BIT_MASK_FWFF_PKT_QUEUED_V1_8814B                                     \\\n\t << BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B)\n#define BIT_CLEAR_FWFF_PKT_QUEUED_V1_8814B(x)                                  \\\n\t((x) & (~BITS_FWFF_PKT_QUEUED_V1_8814B))\n#define BIT_GET_FWFF_PKT_QUEUED_V1_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B) &                         \\\n\t BIT_MASK_FWFF_PKT_QUEUED_V1_8814B)\n#define BIT_SET_FWFF_PKT_QUEUED_V1_8814B(x, v)                                 \\\n\t(BIT_CLEAR_FWFF_PKT_QUEUED_V1_8814B(x) |                               \\\n\t BIT_FWFF_PKT_QUEUED_V1_8814B(v))\n\n/* 2 REG_RXPKTNUM_8814B */\n\n#define BIT_SHIFT_PKT_NUM_WOL_V1_8814B 16\n#define BIT_MASK_PKT_NUM_WOL_V1_8814B 0xffff\n#define BIT_PKT_NUM_WOL_V1_8814B(x)                                            \\\n\t(((x) & BIT_MASK_PKT_NUM_WOL_V1_8814B)                                 \\\n\t << BIT_SHIFT_PKT_NUM_WOL_V1_8814B)\n#define BITS_PKT_NUM_WOL_V1_8814B                                              \\\n\t(BIT_MASK_PKT_NUM_WOL_V1_8814B << BIT_SHIFT_PKT_NUM_WOL_V1_8814B)\n#define BIT_CLEAR_PKT_NUM_WOL_V1_8814B(x) ((x) & (~BITS_PKT_NUM_WOL_V1_8814B))\n#define BIT_GET_PKT_NUM_WOL_V1_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_WOL_V1_8814B) &                             \\\n\t BIT_MASK_PKT_NUM_WOL_V1_8814B)\n#define BIT_SET_PKT_NUM_WOL_V1_8814B(x, v)                                     \\\n\t(BIT_CLEAR_PKT_NUM_WOL_V1_8814B(x) | BIT_PKT_NUM_WOL_V1_8814B(v))\n\n#define BIT_SHIFT_RXPKT_NUM_V1_8814B 0\n#define BIT_MASK_RXPKT_NUM_V1_8814B 0xffff\n#define BIT_RXPKT_NUM_V1_8814B(x)                                              \\\n\t(((x) & BIT_MASK_RXPKT_NUM_V1_8814B) << BIT_SHIFT_RXPKT_NUM_V1_8814B)\n#define BITS_RXPKT_NUM_V1_8814B                                                \\\n\t(BIT_MASK_RXPKT_NUM_V1_8814B << BIT_SHIFT_RXPKT_NUM_V1_8814B)\n#define BIT_CLEAR_RXPKT_NUM_V1_8814B(x) ((x) & (~BITS_RXPKT_NUM_V1_8814B))\n#define BIT_GET_RXPKT_NUM_V1_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXPKT_NUM_V1_8814B) & BIT_MASK_RXPKT_NUM_V1_8814B)\n#define BIT_SET_RXPKT_NUM_V1_8814B(x, v)                                       \\\n\t(BIT_CLEAR_RXPKT_NUM_V1_8814B(x) | BIT_RXPKT_NUM_V1_8814B(v))\n\n/* 2 REG_RXPKTNUM_TH_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_RXPKT_NUM_TH_8814B 0\n#define BIT_MASK_RXPKT_NUM_TH_8814B 0xff\n#define BIT_RXPKT_NUM_TH_8814B(x)                                              \\\n\t(((x) & BIT_MASK_RXPKT_NUM_TH_8814B) << BIT_SHIFT_RXPKT_NUM_TH_8814B)\n#define BITS_RXPKT_NUM_TH_8814B                                                \\\n\t(BIT_MASK_RXPKT_NUM_TH_8814B << BIT_SHIFT_RXPKT_NUM_TH_8814B)\n#define BIT_CLEAR_RXPKT_NUM_TH_8814B(x) ((x) & (~BITS_RXPKT_NUM_TH_8814B))\n#define BIT_GET_RXPKT_NUM_TH_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXPKT_NUM_TH_8814B) & BIT_MASK_RXPKT_NUM_TH_8814B)\n#define BIT_SET_RXPKT_NUM_TH_8814B(x, v)                                       \\\n\t(BIT_CLEAR_RXPKT_NUM_TH_8814B(x) | BIT_RXPKT_NUM_TH_8814B(v))\n\n/* 2 REG_FW_UPD_RXDES_RDPTR_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B 0\n#define BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B 0x3ffff\n#define BIT_FW_UPD_RXDES_RD_PTR_8814B(x)                                       \\\n\t(((x) & BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B)                            \\\n\t << BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B)\n#define BITS_FW_UPD_RXDES_RD_PTR_8814B                                         \\\n\t(BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B                                    \\\n\t << BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B)\n#define BIT_CLEAR_FW_UPD_RXDES_RD_PTR_8814B(x)                                 \\\n\t((x) & (~BITS_FW_UPD_RXDES_RD_PTR_8814B))\n#define BIT_GET_FW_UPD_RXDES_RD_PTR_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B) &                        \\\n\t BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B)\n#define BIT_SET_FW_UPD_RXDES_RD_PTR_8814B(x, v)                                \\\n\t(BIT_CLEAR_FW_UPD_RXDES_RD_PTR_8814B(x) |                              \\\n\t BIT_FW_UPD_RXDES_RD_PTR_8814B(v))\n\n/* 2 REG_DDMA_CH0SA_8814B */\n\n#define BIT_SHIFT_DDMACH0_SA_8814B 0\n#define BIT_MASK_DDMACH0_SA_8814B 0xffffffffL\n#define BIT_DDMACH0_SA_8814B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH0_SA_8814B) << BIT_SHIFT_DDMACH0_SA_8814B)\n#define BITS_DDMACH0_SA_8814B                                                  \\\n\t(BIT_MASK_DDMACH0_SA_8814B << BIT_SHIFT_DDMACH0_SA_8814B)\n#define BIT_CLEAR_DDMACH0_SA_8814B(x) ((x) & (~BITS_DDMACH0_SA_8814B))\n#define BIT_GET_DDMACH0_SA_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH0_SA_8814B) & BIT_MASK_DDMACH0_SA_8814B)\n#define BIT_SET_DDMACH0_SA_8814B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH0_SA_8814B(x) | BIT_DDMACH0_SA_8814B(v))\n\n/* 2 REG_DDMA_CH0DA_8814B */\n\n#define BIT_SHIFT_DDMACH0_DA_8814B 0\n#define BIT_MASK_DDMACH0_DA_8814B 0xffffffffL\n#define BIT_DDMACH0_DA_8814B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH0_DA_8814B) << BIT_SHIFT_DDMACH0_DA_8814B)\n#define BITS_DDMACH0_DA_8814B                                                  \\\n\t(BIT_MASK_DDMACH0_DA_8814B << BIT_SHIFT_DDMACH0_DA_8814B)\n#define BIT_CLEAR_DDMACH0_DA_8814B(x) ((x) & (~BITS_DDMACH0_DA_8814B))\n#define BIT_GET_DDMACH0_DA_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH0_DA_8814B) & BIT_MASK_DDMACH0_DA_8814B)\n#define BIT_SET_DDMACH0_DA_8814B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH0_DA_8814B(x) | BIT_DDMACH0_DA_8814B(v))\n\n/* 2 REG_DDMA_CH0CTRL_8814B */\n#define BIT_DDMACH0_OWN_8814B BIT(31)\n#define BIT_DDMACH0_IDMEM_ERR_8814B BIT(30)\n#define BIT_DDMACH0_CHKSUM_EN_8814B BIT(29)\n#define BIT_DDMACH0_DA_W_DISABLE_8814B BIT(28)\n#define BIT_DDMACH0_CHKSUM_STS_8814B BIT(27)\n#define BIT_DDMACH0_DDMA_MODE_8814B BIT(26)\n#define BIT_DDMACH0_RESET_CHKSUM_STS_8814B BIT(25)\n#define BIT_DDMACH0_CHKSUM_CONT_8814B BIT(24)\n\n#define BIT_SHIFT_DDMACH0_DLEN_8814B 0\n#define BIT_MASK_DDMACH0_DLEN_8814B 0x3ffff\n#define BIT_DDMACH0_DLEN_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH0_DLEN_8814B) << BIT_SHIFT_DDMACH0_DLEN_8814B)\n#define BITS_DDMACH0_DLEN_8814B                                                \\\n\t(BIT_MASK_DDMACH0_DLEN_8814B << BIT_SHIFT_DDMACH0_DLEN_8814B)\n#define BIT_CLEAR_DDMACH0_DLEN_8814B(x) ((x) & (~BITS_DDMACH0_DLEN_8814B))\n#define BIT_GET_DDMACH0_DLEN_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH0_DLEN_8814B) & BIT_MASK_DDMACH0_DLEN_8814B)\n#define BIT_SET_DDMACH0_DLEN_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH0_DLEN_8814B(x) | BIT_DDMACH0_DLEN_8814B(v))\n\n/* 2 REG_DDMA_CH1SA_8814B */\n\n#define BIT_SHIFT_DDMACH1_SA_8814B 0\n#define BIT_MASK_DDMACH1_SA_8814B 0xffffffffL\n#define BIT_DDMACH1_SA_8814B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH1_SA_8814B) << BIT_SHIFT_DDMACH1_SA_8814B)\n#define BITS_DDMACH1_SA_8814B                                                  \\\n\t(BIT_MASK_DDMACH1_SA_8814B << BIT_SHIFT_DDMACH1_SA_8814B)\n#define BIT_CLEAR_DDMACH1_SA_8814B(x) ((x) & (~BITS_DDMACH1_SA_8814B))\n#define BIT_GET_DDMACH1_SA_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH1_SA_8814B) & BIT_MASK_DDMACH1_SA_8814B)\n#define BIT_SET_DDMACH1_SA_8814B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH1_SA_8814B(x) | BIT_DDMACH1_SA_8814B(v))\n\n/* 2 REG_DDMA_CH1DA_8814B */\n\n#define BIT_SHIFT_DDMACH1_DA_8814B 0\n#define BIT_MASK_DDMACH1_DA_8814B 0xffffffffL\n#define BIT_DDMACH1_DA_8814B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH1_DA_8814B) << BIT_SHIFT_DDMACH1_DA_8814B)\n#define BITS_DDMACH1_DA_8814B                                                  \\\n\t(BIT_MASK_DDMACH1_DA_8814B << BIT_SHIFT_DDMACH1_DA_8814B)\n#define BIT_CLEAR_DDMACH1_DA_8814B(x) ((x) & (~BITS_DDMACH1_DA_8814B))\n#define BIT_GET_DDMACH1_DA_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH1_DA_8814B) & BIT_MASK_DDMACH1_DA_8814B)\n#define BIT_SET_DDMACH1_DA_8814B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH1_DA_8814B(x) | BIT_DDMACH1_DA_8814B(v))\n\n/* 2 REG_DDMA_CH1CTRL_8814B */\n#define BIT_DDMACH1_OWN_8814B BIT(31)\n#define BIT_DDMACH1_IDMEM_ERR_8814B BIT(30)\n#define BIT_DDMACH1_CHKSUM_EN_8814B BIT(29)\n#define BIT_DDMACH1_DA_W_DISABLE_8814B BIT(28)\n#define BIT_DDMACH1_CHKSUM_STS_8814B BIT(27)\n#define BIT_DDMACH1_DDMA_MODE_8814B BIT(26)\n#define BIT_DDMACH1_RESET_CHKSUM_STS_8814B BIT(25)\n#define BIT_DDMACH1_CHKSUM_CONT_8814B BIT(24)\n\n#define BIT_SHIFT_DDMACH1_DLEN_8814B 0\n#define BIT_MASK_DDMACH1_DLEN_8814B 0x3ffff\n#define BIT_DDMACH1_DLEN_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH1_DLEN_8814B) << BIT_SHIFT_DDMACH1_DLEN_8814B)\n#define BITS_DDMACH1_DLEN_8814B                                                \\\n\t(BIT_MASK_DDMACH1_DLEN_8814B << BIT_SHIFT_DDMACH1_DLEN_8814B)\n#define BIT_CLEAR_DDMACH1_DLEN_8814B(x) ((x) & (~BITS_DDMACH1_DLEN_8814B))\n#define BIT_GET_DDMACH1_DLEN_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH1_DLEN_8814B) & BIT_MASK_DDMACH1_DLEN_8814B)\n#define BIT_SET_DDMACH1_DLEN_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH1_DLEN_8814B(x) | BIT_DDMACH1_DLEN_8814B(v))\n\n/* 2 REG_DDMA_CH2SA_8814B */\n\n#define BIT_SHIFT_DDMACH2_SA_8814B 0\n#define BIT_MASK_DDMACH2_SA_8814B 0xffffffffL\n#define BIT_DDMACH2_SA_8814B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH2_SA_8814B) << BIT_SHIFT_DDMACH2_SA_8814B)\n#define BITS_DDMACH2_SA_8814B                                                  \\\n\t(BIT_MASK_DDMACH2_SA_8814B << BIT_SHIFT_DDMACH2_SA_8814B)\n#define BIT_CLEAR_DDMACH2_SA_8814B(x) ((x) & (~BITS_DDMACH2_SA_8814B))\n#define BIT_GET_DDMACH2_SA_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH2_SA_8814B) & BIT_MASK_DDMACH2_SA_8814B)\n#define BIT_SET_DDMACH2_SA_8814B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH2_SA_8814B(x) | BIT_DDMACH2_SA_8814B(v))\n\n/* 2 REG_DDMA_CH2DA_8814B */\n\n#define BIT_SHIFT_DDMACH2_DA_8814B 0\n#define BIT_MASK_DDMACH2_DA_8814B 0xffffffffL\n#define BIT_DDMACH2_DA_8814B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH2_DA_8814B) << BIT_SHIFT_DDMACH2_DA_8814B)\n#define BITS_DDMACH2_DA_8814B                                                  \\\n\t(BIT_MASK_DDMACH2_DA_8814B << BIT_SHIFT_DDMACH2_DA_8814B)\n#define BIT_CLEAR_DDMACH2_DA_8814B(x) ((x) & (~BITS_DDMACH2_DA_8814B))\n#define BIT_GET_DDMACH2_DA_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH2_DA_8814B) & BIT_MASK_DDMACH2_DA_8814B)\n#define BIT_SET_DDMACH2_DA_8814B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH2_DA_8814B(x) | BIT_DDMACH2_DA_8814B(v))\n\n/* 2 REG_DDMA_CH2CTRL_8814B */\n#define BIT_DDMACH2_OWN_8814B BIT(31)\n#define BIT_DDMACH2_IDMEM_ERR_8814B BIT(30)\n#define BIT_DDMACH2_CHKSUM_EN_8814B BIT(29)\n#define BIT_DDMACH2_DA_W_DISABLE_8814B BIT(28)\n#define BIT_DDMACH2_CHKSUM_STS_8814B BIT(27)\n#define BIT_DDMACH2_DDMA_MODE_8814B BIT(26)\n#define BIT_DDMACH2_RESET_CHKSUM_STS_8814B BIT(25)\n#define BIT_DDMACH2_CHKSUM_CONT_8814B BIT(24)\n\n#define BIT_SHIFT_DDMACH2_DLEN_8814B 0\n#define BIT_MASK_DDMACH2_DLEN_8814B 0x3ffff\n#define BIT_DDMACH2_DLEN_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH2_DLEN_8814B) << BIT_SHIFT_DDMACH2_DLEN_8814B)\n#define BITS_DDMACH2_DLEN_8814B                                                \\\n\t(BIT_MASK_DDMACH2_DLEN_8814B << BIT_SHIFT_DDMACH2_DLEN_8814B)\n#define BIT_CLEAR_DDMACH2_DLEN_8814B(x) ((x) & (~BITS_DDMACH2_DLEN_8814B))\n#define BIT_GET_DDMACH2_DLEN_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH2_DLEN_8814B) & BIT_MASK_DDMACH2_DLEN_8814B)\n#define BIT_SET_DDMACH2_DLEN_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH2_DLEN_8814B(x) | BIT_DDMACH2_DLEN_8814B(v))\n\n/* 2 REG_DDMA_CH3SA_8814B */\n\n#define BIT_SHIFT_DDMACH3_SA_8814B 0\n#define BIT_MASK_DDMACH3_SA_8814B 0xffffffffL\n#define BIT_DDMACH3_SA_8814B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH3_SA_8814B) << BIT_SHIFT_DDMACH3_SA_8814B)\n#define BITS_DDMACH3_SA_8814B                                                  \\\n\t(BIT_MASK_DDMACH3_SA_8814B << BIT_SHIFT_DDMACH3_SA_8814B)\n#define BIT_CLEAR_DDMACH3_SA_8814B(x) ((x) & (~BITS_DDMACH3_SA_8814B))\n#define BIT_GET_DDMACH3_SA_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH3_SA_8814B) & BIT_MASK_DDMACH3_SA_8814B)\n#define BIT_SET_DDMACH3_SA_8814B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH3_SA_8814B(x) | BIT_DDMACH3_SA_8814B(v))\n\n/* 2 REG_DDMA_CH3DA_8814B */\n\n#define BIT_SHIFT_DDMACH3_DA_8814B 0\n#define BIT_MASK_DDMACH3_DA_8814B 0xffffffffL\n#define BIT_DDMACH3_DA_8814B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH3_DA_8814B) << BIT_SHIFT_DDMACH3_DA_8814B)\n#define BITS_DDMACH3_DA_8814B                                                  \\\n\t(BIT_MASK_DDMACH3_DA_8814B << BIT_SHIFT_DDMACH3_DA_8814B)\n#define BIT_CLEAR_DDMACH3_DA_8814B(x) ((x) & (~BITS_DDMACH3_DA_8814B))\n#define BIT_GET_DDMACH3_DA_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH3_DA_8814B) & BIT_MASK_DDMACH3_DA_8814B)\n#define BIT_SET_DDMACH3_DA_8814B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH3_DA_8814B(x) | BIT_DDMACH3_DA_8814B(v))\n\n/* 2 REG_DDMA_CH3CTRL_8814B */\n#define BIT_DDMACH3_OWN_8814B BIT(31)\n#define BIT_DDMACH3_IDMEM_ERR_8814B BIT(30)\n#define BIT_DDMACH3_CHKSUM_EN_8814B BIT(29)\n#define BIT_DDMACH3_DA_W_DISABLE_8814B BIT(28)\n#define BIT_DDMACH3_CHKSUM_STS_8814B BIT(27)\n#define BIT_DDMACH3_DDMA_MODE_8814B BIT(26)\n#define BIT_DDMACH3_RESET_CHKSUM_STS_8814B BIT(25)\n#define BIT_DDMACH3_CHKSUM_CONT_8814B BIT(24)\n\n#define BIT_SHIFT_DDMACH3_DLEN_8814B 0\n#define BIT_MASK_DDMACH3_DLEN_8814B 0x3ffff\n#define BIT_DDMACH3_DLEN_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH3_DLEN_8814B) << BIT_SHIFT_DDMACH3_DLEN_8814B)\n#define BITS_DDMACH3_DLEN_8814B                                                \\\n\t(BIT_MASK_DDMACH3_DLEN_8814B << BIT_SHIFT_DDMACH3_DLEN_8814B)\n#define BIT_CLEAR_DDMACH3_DLEN_8814B(x) ((x) & (~BITS_DDMACH3_DLEN_8814B))\n#define BIT_GET_DDMACH3_DLEN_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH3_DLEN_8814B) & BIT_MASK_DDMACH3_DLEN_8814B)\n#define BIT_SET_DDMACH3_DLEN_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH3_DLEN_8814B(x) | BIT_DDMACH3_DLEN_8814B(v))\n\n/* 2 REG_DDMA_CH4SA_8814B */\n\n#define BIT_SHIFT_DDMACH4_SA_8814B 0\n#define BIT_MASK_DDMACH4_SA_8814B 0xffffffffL\n#define BIT_DDMACH4_SA_8814B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH4_SA_8814B) << BIT_SHIFT_DDMACH4_SA_8814B)\n#define BITS_DDMACH4_SA_8814B                                                  \\\n\t(BIT_MASK_DDMACH4_SA_8814B << BIT_SHIFT_DDMACH4_SA_8814B)\n#define BIT_CLEAR_DDMACH4_SA_8814B(x) ((x) & (~BITS_DDMACH4_SA_8814B))\n#define BIT_GET_DDMACH4_SA_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH4_SA_8814B) & BIT_MASK_DDMACH4_SA_8814B)\n#define BIT_SET_DDMACH4_SA_8814B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH4_SA_8814B(x) | BIT_DDMACH4_SA_8814B(v))\n\n/* 2 REG_DDMA_CH4DA_8814B */\n\n#define BIT_SHIFT_DDMACH4_DA_8814B 0\n#define BIT_MASK_DDMACH4_DA_8814B 0xffffffffL\n#define BIT_DDMACH4_DA_8814B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH4_DA_8814B) << BIT_SHIFT_DDMACH4_DA_8814B)\n#define BITS_DDMACH4_DA_8814B                                                  \\\n\t(BIT_MASK_DDMACH4_DA_8814B << BIT_SHIFT_DDMACH4_DA_8814B)\n#define BIT_CLEAR_DDMACH4_DA_8814B(x) ((x) & (~BITS_DDMACH4_DA_8814B))\n#define BIT_GET_DDMACH4_DA_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH4_DA_8814B) & BIT_MASK_DDMACH4_DA_8814B)\n#define BIT_SET_DDMACH4_DA_8814B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH4_DA_8814B(x) | BIT_DDMACH4_DA_8814B(v))\n\n/* 2 REG_DDMA_CH4CTRL_8814B */\n#define BIT_DDMACH4_OWN_8814B BIT(31)\n#define BIT_DDMACH4_IDMEM_ERR_8814B BIT(30)\n#define BIT_DDMACH4_CHKSUM_EN_8814B BIT(29)\n#define BIT_DDMACH4_DA_W_DISABLE_8814B BIT(28)\n#define BIT_DDMACH4_CHKSUM_STS_8814B BIT(27)\n#define BIT_DDMACH4_DDMA_MODE_8814B BIT(26)\n#define BIT_DDMACH4_RESET_CHKSUM_STS_8814B BIT(25)\n#define BIT_DDMACH4_CHKSUM_CONT_8814B BIT(24)\n\n#define BIT_SHIFT_DDMACH4_DLEN_8814B 0\n#define BIT_MASK_DDMACH4_DLEN_8814B 0x3ffff\n#define BIT_DDMACH4_DLEN_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH4_DLEN_8814B) << BIT_SHIFT_DDMACH4_DLEN_8814B)\n#define BITS_DDMACH4_DLEN_8814B                                                \\\n\t(BIT_MASK_DDMACH4_DLEN_8814B << BIT_SHIFT_DDMACH4_DLEN_8814B)\n#define BIT_CLEAR_DDMACH4_DLEN_8814B(x) ((x) & (~BITS_DDMACH4_DLEN_8814B))\n#define BIT_GET_DDMACH4_DLEN_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH4_DLEN_8814B) & BIT_MASK_DDMACH4_DLEN_8814B)\n#define BIT_SET_DDMACH4_DLEN_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH4_DLEN_8814B(x) | BIT_DDMACH4_DLEN_8814B(v))\n\n/* 2 REG_DDMA_CH5SA_8814B */\n\n#define BIT_SHIFT_DDMACH5_SA_8814B 0\n#define BIT_MASK_DDMACH5_SA_8814B 0xffffffffL\n#define BIT_DDMACH5_SA_8814B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH5_SA_8814B) << BIT_SHIFT_DDMACH5_SA_8814B)\n#define BITS_DDMACH5_SA_8814B                                                  \\\n\t(BIT_MASK_DDMACH5_SA_8814B << BIT_SHIFT_DDMACH5_SA_8814B)\n#define BIT_CLEAR_DDMACH5_SA_8814B(x) ((x) & (~BITS_DDMACH5_SA_8814B))\n#define BIT_GET_DDMACH5_SA_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH5_SA_8814B) & BIT_MASK_DDMACH5_SA_8814B)\n#define BIT_SET_DDMACH5_SA_8814B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH5_SA_8814B(x) | BIT_DDMACH5_SA_8814B(v))\n\n/* 2 REG_DDMA_CH5DA_8814B */\n\n#define BIT_SHIFT_DDMACH5_DA_8814B 0\n#define BIT_MASK_DDMACH5_DA_8814B 0xffffffffL\n#define BIT_DDMACH5_DA_8814B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH5_DA_8814B) << BIT_SHIFT_DDMACH5_DA_8814B)\n#define BITS_DDMACH5_DA_8814B                                                  \\\n\t(BIT_MASK_DDMACH5_DA_8814B << BIT_SHIFT_DDMACH5_DA_8814B)\n#define BIT_CLEAR_DDMACH5_DA_8814B(x) ((x) & (~BITS_DDMACH5_DA_8814B))\n#define BIT_GET_DDMACH5_DA_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH5_DA_8814B) & BIT_MASK_DDMACH5_DA_8814B)\n#define BIT_SET_DDMACH5_DA_8814B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH5_DA_8814B(x) | BIT_DDMACH5_DA_8814B(v))\n\n/* 2 REG_DDMA_CH5CTRL_8814B */\n#define BIT_DDMACH5_OWN_8814B BIT(31)\n#define BIT_DDMACH5_IDMEM_ERR_8814B BIT(30)\n#define BIT_DDMACH5_CHKSUM_EN_8814B BIT(29)\n#define BIT_DDMACH5_DA_W_DISABLE_8814B BIT(28)\n#define BIT_DDMACH5_CHKSUM_STS_8814B BIT(27)\n#define BIT_DDMACH5_DDMA_MODE_8814B BIT(26)\n#define BIT_DDMACH5_RESET_CHKSUM_STS_8814B BIT(25)\n#define BIT_DDMACH5_CHKSUM_CONT_8814B BIT(24)\n\n#define BIT_SHIFT_DDMACH5_DLEN_8814B 0\n#define BIT_MASK_DDMACH5_DLEN_8814B 0x3ffff\n#define BIT_DDMACH5_DLEN_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH5_DLEN_8814B) << BIT_SHIFT_DDMACH5_DLEN_8814B)\n#define BITS_DDMACH5_DLEN_8814B                                                \\\n\t(BIT_MASK_DDMACH5_DLEN_8814B << BIT_SHIFT_DDMACH5_DLEN_8814B)\n#define BIT_CLEAR_DDMACH5_DLEN_8814B(x) ((x) & (~BITS_DDMACH5_DLEN_8814B))\n#define BIT_GET_DDMACH5_DLEN_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH5_DLEN_8814B) & BIT_MASK_DDMACH5_DLEN_8814B)\n#define BIT_SET_DDMACH5_DLEN_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH5_DLEN_8814B(x) | BIT_DDMACH5_DLEN_8814B(v))\n\n/* 2 REG_DDMA_INT_MSK_8814B */\n#define BIT_DDMACH5_MSK_8814B BIT(5)\n#define BIT_DDMACH4_MSK_8814B BIT(4)\n#define BIT_DDMACH3_MSK_8814B BIT(3)\n#define BIT_DDMACH2_MSK_8814B BIT(2)\n#define BIT_DDMACH1_MSK_8814B BIT(1)\n#define BIT_DDMACH0_MSK_8814B BIT(0)\n\n/* 2 REG_DDMA_CHSTATUS_8814B */\n#define BIT_DDMACH5_BUSY_8814B BIT(5)\n#define BIT_DDMACH4_BUSY_8814B BIT(4)\n#define BIT_DDMACH3_BUSY_8814B BIT(3)\n#define BIT_DDMACH2_BUSY_8814B BIT(2)\n#define BIT_DDMACH1_BUSY_8814B BIT(1)\n#define BIT_DDMACH0_BUSY_8814B BIT(0)\n\n/* 2 REG_DDMA_CHKSUM_8814B */\n\n#define BIT_SHIFT_IDDMA0_CHKSUM_8814B 0\n#define BIT_MASK_IDDMA0_CHKSUM_8814B 0xffff\n#define BIT_IDDMA0_CHKSUM_8814B(x)                                             \\\n\t(((x) & BIT_MASK_IDDMA0_CHKSUM_8814B) << BIT_SHIFT_IDDMA0_CHKSUM_8814B)\n#define BITS_IDDMA0_CHKSUM_8814B                                               \\\n\t(BIT_MASK_IDDMA0_CHKSUM_8814B << BIT_SHIFT_IDDMA0_CHKSUM_8814B)\n#define BIT_CLEAR_IDDMA0_CHKSUM_8814B(x) ((x) & (~BITS_IDDMA0_CHKSUM_8814B))\n#define BIT_GET_IDDMA0_CHKSUM_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8814B) & BIT_MASK_IDDMA0_CHKSUM_8814B)\n#define BIT_SET_IDDMA0_CHKSUM_8814B(x, v)                                      \\\n\t(BIT_CLEAR_IDDMA0_CHKSUM_8814B(x) | BIT_IDDMA0_CHKSUM_8814B(v))\n\n/* 2 REG_DDMA_MONITOR_8814B */\n#define BIT_IDDMA0_PERMU_UNDERFLOW_8814B BIT(14)\n#define BIT_IDDMA0_FIFO_UNDERFLOW_8814B BIT(13)\n#define BIT_IDDMA0_FIFO_OVERFLOW_8814B BIT(12)\n#define BIT_CH5_ERR_8814B BIT(5)\n#define BIT_CH4_ERR_8814B BIT(4)\n#define BIT_CH3_ERR_8814B BIT(3)\n#define BIT_CH2_ERR_8814B BIT(2)\n#define BIT_CH1_ERR_8814B BIT(1)\n#define BIT_CH0_ERR_8814B BIT(0)\n\n/* 2 REG_DMA_RQPN_INFO_0_8814B */\n\n#define BIT_SHIFT_CH0_AVAL_PG_8814B 16\n#define BIT_MASK_CH0_AVAL_PG_8814B 0xfff\n#define BIT_CH0_AVAL_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH0_AVAL_PG_8814B) << BIT_SHIFT_CH0_AVAL_PG_8814B)\n#define BITS_CH0_AVAL_PG_8814B                                                 \\\n\t(BIT_MASK_CH0_AVAL_PG_8814B << BIT_SHIFT_CH0_AVAL_PG_8814B)\n#define BIT_CLEAR_CH0_AVAL_PG_8814B(x) ((x) & (~BITS_CH0_AVAL_PG_8814B))\n#define BIT_GET_CH0_AVAL_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH0_AVAL_PG_8814B) & BIT_MASK_CH0_AVAL_PG_8814B)\n#define BIT_SET_CH0_AVAL_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH0_AVAL_PG_8814B(x) | BIT_CH0_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_CH0_RSVD_PG_8814B 0\n#define BIT_MASK_CH0_RSVD_PG_8814B 0xfff\n#define BIT_CH0_RSVD_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH0_RSVD_PG_8814B) << BIT_SHIFT_CH0_RSVD_PG_8814B)\n#define BITS_CH0_RSVD_PG_8814B                                                 \\\n\t(BIT_MASK_CH0_RSVD_PG_8814B << BIT_SHIFT_CH0_RSVD_PG_8814B)\n#define BIT_CLEAR_CH0_RSVD_PG_8814B(x) ((x) & (~BITS_CH0_RSVD_PG_8814B))\n#define BIT_GET_CH0_RSVD_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH0_RSVD_PG_8814B) & BIT_MASK_CH0_RSVD_PG_8814B)\n#define BIT_SET_CH0_RSVD_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH0_RSVD_PG_8814B(x) | BIT_CH0_RSVD_PG_8814B(v))\n\n/* 2 REG_DMA_RQPN_INFO_1_8814B */\n\n#define BIT_SHIFT_CH1_AVAL_PG_8814B 16\n#define BIT_MASK_CH1_AVAL_PG_8814B 0xfff\n#define BIT_CH1_AVAL_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH1_AVAL_PG_8814B) << BIT_SHIFT_CH1_AVAL_PG_8814B)\n#define BITS_CH1_AVAL_PG_8814B                                                 \\\n\t(BIT_MASK_CH1_AVAL_PG_8814B << BIT_SHIFT_CH1_AVAL_PG_8814B)\n#define BIT_CLEAR_CH1_AVAL_PG_8814B(x) ((x) & (~BITS_CH1_AVAL_PG_8814B))\n#define BIT_GET_CH1_AVAL_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH1_AVAL_PG_8814B) & BIT_MASK_CH1_AVAL_PG_8814B)\n#define BIT_SET_CH1_AVAL_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH1_AVAL_PG_8814B(x) | BIT_CH1_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_CH1_RSVD_PG_8814B 0\n#define BIT_MASK_CH1_RSVD_PG_8814B 0xfff\n#define BIT_CH1_RSVD_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH1_RSVD_PG_8814B) << BIT_SHIFT_CH1_RSVD_PG_8814B)\n#define BITS_CH1_RSVD_PG_8814B                                                 \\\n\t(BIT_MASK_CH1_RSVD_PG_8814B << BIT_SHIFT_CH1_RSVD_PG_8814B)\n#define BIT_CLEAR_CH1_RSVD_PG_8814B(x) ((x) & (~BITS_CH1_RSVD_PG_8814B))\n#define BIT_GET_CH1_RSVD_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH1_RSVD_PG_8814B) & BIT_MASK_CH1_RSVD_PG_8814B)\n#define BIT_SET_CH1_RSVD_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH1_RSVD_PG_8814B(x) | BIT_CH1_RSVD_PG_8814B(v))\n\n/* 2 REG_DMA_RQPN_INFO_2_8814B */\n\n#define BIT_SHIFT_CH2_AVAL_PG_8814B 16\n#define BIT_MASK_CH2_AVAL_PG_8814B 0xfff\n#define BIT_CH2_AVAL_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH2_AVAL_PG_8814B) << BIT_SHIFT_CH2_AVAL_PG_8814B)\n#define BITS_CH2_AVAL_PG_8814B                                                 \\\n\t(BIT_MASK_CH2_AVAL_PG_8814B << BIT_SHIFT_CH2_AVAL_PG_8814B)\n#define BIT_CLEAR_CH2_AVAL_PG_8814B(x) ((x) & (~BITS_CH2_AVAL_PG_8814B))\n#define BIT_GET_CH2_AVAL_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH2_AVAL_PG_8814B) & BIT_MASK_CH2_AVAL_PG_8814B)\n#define BIT_SET_CH2_AVAL_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH2_AVAL_PG_8814B(x) | BIT_CH2_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_CH2_RSVD_PG_8814B 0\n#define BIT_MASK_CH2_RSVD_PG_8814B 0xfff\n#define BIT_CH2_RSVD_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH2_RSVD_PG_8814B) << BIT_SHIFT_CH2_RSVD_PG_8814B)\n#define BITS_CH2_RSVD_PG_8814B                                                 \\\n\t(BIT_MASK_CH2_RSVD_PG_8814B << BIT_SHIFT_CH2_RSVD_PG_8814B)\n#define BIT_CLEAR_CH2_RSVD_PG_8814B(x) ((x) & (~BITS_CH2_RSVD_PG_8814B))\n#define BIT_GET_CH2_RSVD_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH2_RSVD_PG_8814B) & BIT_MASK_CH2_RSVD_PG_8814B)\n#define BIT_SET_CH2_RSVD_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH2_RSVD_PG_8814B(x) | BIT_CH2_RSVD_PG_8814B(v))\n\n/* 2 REG_DMA_RQPN_INFO_3_8814B */\n\n#define BIT_SHIFT_CH3_AVAL_PG_8814B 16\n#define BIT_MASK_CH3_AVAL_PG_8814B 0xfff\n#define BIT_CH3_AVAL_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH3_AVAL_PG_8814B) << BIT_SHIFT_CH3_AVAL_PG_8814B)\n#define BITS_CH3_AVAL_PG_8814B                                                 \\\n\t(BIT_MASK_CH3_AVAL_PG_8814B << BIT_SHIFT_CH3_AVAL_PG_8814B)\n#define BIT_CLEAR_CH3_AVAL_PG_8814B(x) ((x) & (~BITS_CH3_AVAL_PG_8814B))\n#define BIT_GET_CH3_AVAL_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH3_AVAL_PG_8814B) & BIT_MASK_CH3_AVAL_PG_8814B)\n#define BIT_SET_CH3_AVAL_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH3_AVAL_PG_8814B(x) | BIT_CH3_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_CH3_RSVD_PG_8814B 0\n#define BIT_MASK_CH3_RSVD_PG_8814B 0xfff\n#define BIT_CH3_RSVD_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH3_RSVD_PG_8814B) << BIT_SHIFT_CH3_RSVD_PG_8814B)\n#define BITS_CH3_RSVD_PG_8814B                                                 \\\n\t(BIT_MASK_CH3_RSVD_PG_8814B << BIT_SHIFT_CH3_RSVD_PG_8814B)\n#define BIT_CLEAR_CH3_RSVD_PG_8814B(x) ((x) & (~BITS_CH3_RSVD_PG_8814B))\n#define BIT_GET_CH3_RSVD_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH3_RSVD_PG_8814B) & BIT_MASK_CH3_RSVD_PG_8814B)\n#define BIT_SET_CH3_RSVD_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH3_RSVD_PG_8814B(x) | BIT_CH3_RSVD_PG_8814B(v))\n\n/* 2 REG_DMA_RQPN_INFO_4_8814B */\n\n#define BIT_SHIFT_CH4_AVAL_PG_8814B 16\n#define BIT_MASK_CH4_AVAL_PG_8814B 0xfff\n#define BIT_CH4_AVAL_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH4_AVAL_PG_8814B) << BIT_SHIFT_CH4_AVAL_PG_8814B)\n#define BITS_CH4_AVAL_PG_8814B                                                 \\\n\t(BIT_MASK_CH4_AVAL_PG_8814B << BIT_SHIFT_CH4_AVAL_PG_8814B)\n#define BIT_CLEAR_CH4_AVAL_PG_8814B(x) ((x) & (~BITS_CH4_AVAL_PG_8814B))\n#define BIT_GET_CH4_AVAL_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH4_AVAL_PG_8814B) & BIT_MASK_CH4_AVAL_PG_8814B)\n#define BIT_SET_CH4_AVAL_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH4_AVAL_PG_8814B(x) | BIT_CH4_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_CH4_RSVD_PG_8814B 0\n#define BIT_MASK_CH4_RSVD_PG_8814B 0xfff\n#define BIT_CH4_RSVD_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH4_RSVD_PG_8814B) << BIT_SHIFT_CH4_RSVD_PG_8814B)\n#define BITS_CH4_RSVD_PG_8814B                                                 \\\n\t(BIT_MASK_CH4_RSVD_PG_8814B << BIT_SHIFT_CH4_RSVD_PG_8814B)\n#define BIT_CLEAR_CH4_RSVD_PG_8814B(x) ((x) & (~BITS_CH4_RSVD_PG_8814B))\n#define BIT_GET_CH4_RSVD_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH4_RSVD_PG_8814B) & BIT_MASK_CH4_RSVD_PG_8814B)\n#define BIT_SET_CH4_RSVD_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH4_RSVD_PG_8814B(x) | BIT_CH4_RSVD_PG_8814B(v))\n\n/* 2 REG_DMA_RQPN_INFO_5_8814B */\n\n#define BIT_SHIFT_CH5_AVAL_PG_8814B 16\n#define BIT_MASK_CH5_AVAL_PG_8814B 0xfff\n#define BIT_CH5_AVAL_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH5_AVAL_PG_8814B) << BIT_SHIFT_CH5_AVAL_PG_8814B)\n#define BITS_CH5_AVAL_PG_8814B                                                 \\\n\t(BIT_MASK_CH5_AVAL_PG_8814B << BIT_SHIFT_CH5_AVAL_PG_8814B)\n#define BIT_CLEAR_CH5_AVAL_PG_8814B(x) ((x) & (~BITS_CH5_AVAL_PG_8814B))\n#define BIT_GET_CH5_AVAL_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH5_AVAL_PG_8814B) & BIT_MASK_CH5_AVAL_PG_8814B)\n#define BIT_SET_CH5_AVAL_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH5_AVAL_PG_8814B(x) | BIT_CH5_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_CH5_RSVD_PG_8814B 0\n#define BIT_MASK_CH5_RSVD_PG_8814B 0xfff\n#define BIT_CH5_RSVD_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH5_RSVD_PG_8814B) << BIT_SHIFT_CH5_RSVD_PG_8814B)\n#define BITS_CH5_RSVD_PG_8814B                                                 \\\n\t(BIT_MASK_CH5_RSVD_PG_8814B << BIT_SHIFT_CH5_RSVD_PG_8814B)\n#define BIT_CLEAR_CH5_RSVD_PG_8814B(x) ((x) & (~BITS_CH5_RSVD_PG_8814B))\n#define BIT_GET_CH5_RSVD_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH5_RSVD_PG_8814B) & BIT_MASK_CH5_RSVD_PG_8814B)\n#define BIT_SET_CH5_RSVD_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH5_RSVD_PG_8814B(x) | BIT_CH5_RSVD_PG_8814B(v))\n\n/* 2 REG_DMA_RQPN_INFO_6_8814B */\n\n#define BIT_SHIFT_CH6_AVAL_PG_8814B 16\n#define BIT_MASK_CH6_AVAL_PG_8814B 0xfff\n#define BIT_CH6_AVAL_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH6_AVAL_PG_8814B) << BIT_SHIFT_CH6_AVAL_PG_8814B)\n#define BITS_CH6_AVAL_PG_8814B                                                 \\\n\t(BIT_MASK_CH6_AVAL_PG_8814B << BIT_SHIFT_CH6_AVAL_PG_8814B)\n#define BIT_CLEAR_CH6_AVAL_PG_8814B(x) ((x) & (~BITS_CH6_AVAL_PG_8814B))\n#define BIT_GET_CH6_AVAL_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH6_AVAL_PG_8814B) & BIT_MASK_CH6_AVAL_PG_8814B)\n#define BIT_SET_CH6_AVAL_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH6_AVAL_PG_8814B(x) | BIT_CH6_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_CH6_RSVD_PG_8814B 0\n#define BIT_MASK_CH6_RSVD_PG_8814B 0xfff\n#define BIT_CH6_RSVD_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH6_RSVD_PG_8814B) << BIT_SHIFT_CH6_RSVD_PG_8814B)\n#define BITS_CH6_RSVD_PG_8814B                                                 \\\n\t(BIT_MASK_CH6_RSVD_PG_8814B << BIT_SHIFT_CH6_RSVD_PG_8814B)\n#define BIT_CLEAR_CH6_RSVD_PG_8814B(x) ((x) & (~BITS_CH6_RSVD_PG_8814B))\n#define BIT_GET_CH6_RSVD_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH6_RSVD_PG_8814B) & BIT_MASK_CH6_RSVD_PG_8814B)\n#define BIT_SET_CH6_RSVD_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH6_RSVD_PG_8814B(x) | BIT_CH6_RSVD_PG_8814B(v))\n\n/* 2 REG_DMA_RQPN_INFO_7_8814B */\n\n#define BIT_SHIFT_CH7_AVAL_PG_8814B 16\n#define BIT_MASK_CH7_AVAL_PG_8814B 0xfff\n#define BIT_CH7_AVAL_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH7_AVAL_PG_8814B) << BIT_SHIFT_CH7_AVAL_PG_8814B)\n#define BITS_CH7_AVAL_PG_8814B                                                 \\\n\t(BIT_MASK_CH7_AVAL_PG_8814B << BIT_SHIFT_CH7_AVAL_PG_8814B)\n#define BIT_CLEAR_CH7_AVAL_PG_8814B(x) ((x) & (~BITS_CH7_AVAL_PG_8814B))\n#define BIT_GET_CH7_AVAL_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH7_AVAL_PG_8814B) & BIT_MASK_CH7_AVAL_PG_8814B)\n#define BIT_SET_CH7_AVAL_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH7_AVAL_PG_8814B(x) | BIT_CH7_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_CH7_RSVD_PG_8814B 0\n#define BIT_MASK_CH7_RSVD_PG_8814B 0xfff\n#define BIT_CH7_RSVD_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH7_RSVD_PG_8814B) << BIT_SHIFT_CH7_RSVD_PG_8814B)\n#define BITS_CH7_RSVD_PG_8814B                                                 \\\n\t(BIT_MASK_CH7_RSVD_PG_8814B << BIT_SHIFT_CH7_RSVD_PG_8814B)\n#define BIT_CLEAR_CH7_RSVD_PG_8814B(x) ((x) & (~BITS_CH7_RSVD_PG_8814B))\n#define BIT_GET_CH7_RSVD_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH7_RSVD_PG_8814B) & BIT_MASK_CH7_RSVD_PG_8814B)\n#define BIT_SET_CH7_RSVD_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH7_RSVD_PG_8814B(x) | BIT_CH7_RSVD_PG_8814B(v))\n\n/* 2 REG_DMA_RQPN_INFO_8_8814B */\n\n#define BIT_SHIFT_CH8_AVAL_PG_8814B 16\n#define BIT_MASK_CH8_AVAL_PG_8814B 0xfff\n#define BIT_CH8_AVAL_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH8_AVAL_PG_8814B) << BIT_SHIFT_CH8_AVAL_PG_8814B)\n#define BITS_CH8_AVAL_PG_8814B                                                 \\\n\t(BIT_MASK_CH8_AVAL_PG_8814B << BIT_SHIFT_CH8_AVAL_PG_8814B)\n#define BIT_CLEAR_CH8_AVAL_PG_8814B(x) ((x) & (~BITS_CH8_AVAL_PG_8814B))\n#define BIT_GET_CH8_AVAL_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH8_AVAL_PG_8814B) & BIT_MASK_CH8_AVAL_PG_8814B)\n#define BIT_SET_CH8_AVAL_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH8_AVAL_PG_8814B(x) | BIT_CH8_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_CH8_RSVD_PG_8814B 0\n#define BIT_MASK_CH8_RSVD_PG_8814B 0xfff\n#define BIT_CH8_RSVD_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH8_RSVD_PG_8814B) << BIT_SHIFT_CH8_RSVD_PG_8814B)\n#define BITS_CH8_RSVD_PG_8814B                                                 \\\n\t(BIT_MASK_CH8_RSVD_PG_8814B << BIT_SHIFT_CH8_RSVD_PG_8814B)\n#define BIT_CLEAR_CH8_RSVD_PG_8814B(x) ((x) & (~BITS_CH8_RSVD_PG_8814B))\n#define BIT_GET_CH8_RSVD_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH8_RSVD_PG_8814B) & BIT_MASK_CH8_RSVD_PG_8814B)\n#define BIT_SET_CH8_RSVD_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH8_RSVD_PG_8814B(x) | BIT_CH8_RSVD_PG_8814B(v))\n\n/* 2 REG_DMA_RQPN_INFO_9_8814B */\n\n#define BIT_SHIFT_CH9_AVAL_PG_8814B 16\n#define BIT_MASK_CH9_AVAL_PG_8814B 0xfff\n#define BIT_CH9_AVAL_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH9_AVAL_PG_8814B) << BIT_SHIFT_CH9_AVAL_PG_8814B)\n#define BITS_CH9_AVAL_PG_8814B                                                 \\\n\t(BIT_MASK_CH9_AVAL_PG_8814B << BIT_SHIFT_CH9_AVAL_PG_8814B)\n#define BIT_CLEAR_CH9_AVAL_PG_8814B(x) ((x) & (~BITS_CH9_AVAL_PG_8814B))\n#define BIT_GET_CH9_AVAL_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH9_AVAL_PG_8814B) & BIT_MASK_CH9_AVAL_PG_8814B)\n#define BIT_SET_CH9_AVAL_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH9_AVAL_PG_8814B(x) | BIT_CH9_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_CH9_RSVD_PG_8814B 0\n#define BIT_MASK_CH9_RSVD_PG_8814B 0xfff\n#define BIT_CH9_RSVD_PG_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH9_RSVD_PG_8814B) << BIT_SHIFT_CH9_RSVD_PG_8814B)\n#define BITS_CH9_RSVD_PG_8814B                                                 \\\n\t(BIT_MASK_CH9_RSVD_PG_8814B << BIT_SHIFT_CH9_RSVD_PG_8814B)\n#define BIT_CLEAR_CH9_RSVD_PG_8814B(x) ((x) & (~BITS_CH9_RSVD_PG_8814B))\n#define BIT_GET_CH9_RSVD_PG_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH9_RSVD_PG_8814B) & BIT_MASK_CH9_RSVD_PG_8814B)\n#define BIT_SET_CH9_RSVD_PG_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH9_RSVD_PG_8814B(x) | BIT_CH9_RSVD_PG_8814B(v))\n\n/* 2 REG_DMA_RQPN_INFO_10_8814B */\n\n#define BIT_SHIFT_CH10_AVAL_PG_8814B 16\n#define BIT_MASK_CH10_AVAL_PG_8814B 0xfff\n#define BIT_CH10_AVAL_PG_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH10_AVAL_PG_8814B) << BIT_SHIFT_CH10_AVAL_PG_8814B)\n#define BITS_CH10_AVAL_PG_8814B                                                \\\n\t(BIT_MASK_CH10_AVAL_PG_8814B << BIT_SHIFT_CH10_AVAL_PG_8814B)\n#define BIT_CLEAR_CH10_AVAL_PG_8814B(x) ((x) & (~BITS_CH10_AVAL_PG_8814B))\n#define BIT_GET_CH10_AVAL_PG_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH10_AVAL_PG_8814B) & BIT_MASK_CH10_AVAL_PG_8814B)\n#define BIT_SET_CH10_AVAL_PG_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH10_AVAL_PG_8814B(x) | BIT_CH10_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_CH10_RSVD_PG_8814B 0\n#define BIT_MASK_CH10_RSVD_PG_8814B 0xfff\n#define BIT_CH10_RSVD_PG_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH10_RSVD_PG_8814B) << BIT_SHIFT_CH10_RSVD_PG_8814B)\n#define BITS_CH10_RSVD_PG_8814B                                                \\\n\t(BIT_MASK_CH10_RSVD_PG_8814B << BIT_SHIFT_CH10_RSVD_PG_8814B)\n#define BIT_CLEAR_CH10_RSVD_PG_8814B(x) ((x) & (~BITS_CH10_RSVD_PG_8814B))\n#define BIT_GET_CH10_RSVD_PG_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH10_RSVD_PG_8814B) & BIT_MASK_CH10_RSVD_PG_8814B)\n#define BIT_SET_CH10_RSVD_PG_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH10_RSVD_PG_8814B(x) | BIT_CH10_RSVD_PG_8814B(v))\n\n/* 2 REG_DMA_RQPN_INFO_11_8814B */\n\n#define BIT_SHIFT_CH11_AVAL_PG_8814B 16\n#define BIT_MASK_CH11_AVAL_PG_8814B 0xfff\n#define BIT_CH11_AVAL_PG_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH11_AVAL_PG_8814B) << BIT_SHIFT_CH11_AVAL_PG_8814B)\n#define BITS_CH11_AVAL_PG_8814B                                                \\\n\t(BIT_MASK_CH11_AVAL_PG_8814B << BIT_SHIFT_CH11_AVAL_PG_8814B)\n#define BIT_CLEAR_CH11_AVAL_PG_8814B(x) ((x) & (~BITS_CH11_AVAL_PG_8814B))\n#define BIT_GET_CH11_AVAL_PG_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH11_AVAL_PG_8814B) & BIT_MASK_CH11_AVAL_PG_8814B)\n#define BIT_SET_CH11_AVAL_PG_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH11_AVAL_PG_8814B(x) | BIT_CH11_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_CH11_RSVD_PG_8814B 0\n#define BIT_MASK_CH11_RSVD_PG_8814B 0xfff\n#define BIT_CH11_RSVD_PG_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH11_RSVD_PG_8814B) << BIT_SHIFT_CH11_RSVD_PG_8814B)\n#define BITS_CH11_RSVD_PG_8814B                                                \\\n\t(BIT_MASK_CH11_RSVD_PG_8814B << BIT_SHIFT_CH11_RSVD_PG_8814B)\n#define BIT_CLEAR_CH11_RSVD_PG_8814B(x) ((x) & (~BITS_CH11_RSVD_PG_8814B))\n#define BIT_GET_CH11_RSVD_PG_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH11_RSVD_PG_8814B) & BIT_MASK_CH11_RSVD_PG_8814B)\n#define BIT_SET_CH11_RSVD_PG_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH11_RSVD_PG_8814B(x) | BIT_CH11_RSVD_PG_8814B(v))\n\n/* 2 REG_DMA_RQPN_INFO_12_8814B */\n\n#define BIT_SHIFT_CH12_AVAL_PG_8814B 16\n#define BIT_MASK_CH12_AVAL_PG_8814B 0xfff\n#define BIT_CH12_AVAL_PG_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH12_AVAL_PG_8814B) << BIT_SHIFT_CH12_AVAL_PG_8814B)\n#define BITS_CH12_AVAL_PG_8814B                                                \\\n\t(BIT_MASK_CH12_AVAL_PG_8814B << BIT_SHIFT_CH12_AVAL_PG_8814B)\n#define BIT_CLEAR_CH12_AVAL_PG_8814B(x) ((x) & (~BITS_CH12_AVAL_PG_8814B))\n#define BIT_GET_CH12_AVAL_PG_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH12_AVAL_PG_8814B) & BIT_MASK_CH12_AVAL_PG_8814B)\n#define BIT_SET_CH12_AVAL_PG_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH12_AVAL_PG_8814B(x) | BIT_CH12_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_CH12_RSVD_PG_8814B 0\n#define BIT_MASK_CH12_RSVD_PG_8814B 0xfff\n#define BIT_CH12_RSVD_PG_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH12_RSVD_PG_8814B) << BIT_SHIFT_CH12_RSVD_PG_8814B)\n#define BITS_CH12_RSVD_PG_8814B                                                \\\n\t(BIT_MASK_CH12_RSVD_PG_8814B << BIT_SHIFT_CH12_RSVD_PG_8814B)\n#define BIT_CLEAR_CH12_RSVD_PG_8814B(x) ((x) & (~BITS_CH12_RSVD_PG_8814B))\n#define BIT_GET_CH12_RSVD_PG_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH12_RSVD_PG_8814B) & BIT_MASK_CH12_RSVD_PG_8814B)\n#define BIT_SET_CH12_RSVD_PG_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH12_RSVD_PG_8814B(x) | BIT_CH12_RSVD_PG_8814B(v))\n\n/* 2 REG_DMA_RQPN_INFO_13_8814B */\n\n#define BIT_SHIFT_CH13_AVAL_PG_8814B 16\n#define BIT_MASK_CH13_AVAL_PG_8814B 0xfff\n#define BIT_CH13_AVAL_PG_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH13_AVAL_PG_8814B) << BIT_SHIFT_CH13_AVAL_PG_8814B)\n#define BITS_CH13_AVAL_PG_8814B                                                \\\n\t(BIT_MASK_CH13_AVAL_PG_8814B << BIT_SHIFT_CH13_AVAL_PG_8814B)\n#define BIT_CLEAR_CH13_AVAL_PG_8814B(x) ((x) & (~BITS_CH13_AVAL_PG_8814B))\n#define BIT_GET_CH13_AVAL_PG_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH13_AVAL_PG_8814B) & BIT_MASK_CH13_AVAL_PG_8814B)\n#define BIT_SET_CH13_AVAL_PG_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH13_AVAL_PG_8814B(x) | BIT_CH13_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_CH13_RSVD_PG_8814B 0\n#define BIT_MASK_CH13_RSVD_PG_8814B 0xfff\n#define BIT_CH13_RSVD_PG_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH13_RSVD_PG_8814B) << BIT_SHIFT_CH13_RSVD_PG_8814B)\n#define BITS_CH13_RSVD_PG_8814B                                                \\\n\t(BIT_MASK_CH13_RSVD_PG_8814B << BIT_SHIFT_CH13_RSVD_PG_8814B)\n#define BIT_CLEAR_CH13_RSVD_PG_8814B(x) ((x) & (~BITS_CH13_RSVD_PG_8814B))\n#define BIT_GET_CH13_RSVD_PG_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH13_RSVD_PG_8814B) & BIT_MASK_CH13_RSVD_PG_8814B)\n#define BIT_SET_CH13_RSVD_PG_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH13_RSVD_PG_8814B(x) | BIT_CH13_RSVD_PG_8814B(v))\n\n/* 2 REG_DMA_RQPN_INFO_14_8814B */\n\n#define BIT_SHIFT_CH14_AVAL_PG_8814B 16\n#define BIT_MASK_CH14_AVAL_PG_8814B 0xfff\n#define BIT_CH14_AVAL_PG_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH14_AVAL_PG_8814B) << BIT_SHIFT_CH14_AVAL_PG_8814B)\n#define BITS_CH14_AVAL_PG_8814B                                                \\\n\t(BIT_MASK_CH14_AVAL_PG_8814B << BIT_SHIFT_CH14_AVAL_PG_8814B)\n#define BIT_CLEAR_CH14_AVAL_PG_8814B(x) ((x) & (~BITS_CH14_AVAL_PG_8814B))\n#define BIT_GET_CH14_AVAL_PG_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH14_AVAL_PG_8814B) & BIT_MASK_CH14_AVAL_PG_8814B)\n#define BIT_SET_CH14_AVAL_PG_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH14_AVAL_PG_8814B(x) | BIT_CH14_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_CH14_RSVD_PG_8814B 0\n#define BIT_MASK_CH14_RSVD_PG_8814B 0xfff\n#define BIT_CH14_RSVD_PG_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH14_RSVD_PG_8814B) << BIT_SHIFT_CH14_RSVD_PG_8814B)\n#define BITS_CH14_RSVD_PG_8814B                                                \\\n\t(BIT_MASK_CH14_RSVD_PG_8814B << BIT_SHIFT_CH14_RSVD_PG_8814B)\n#define BIT_CLEAR_CH14_RSVD_PG_8814B(x) ((x) & (~BITS_CH14_RSVD_PG_8814B))\n#define BIT_GET_CH14_RSVD_PG_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH14_RSVD_PG_8814B) & BIT_MASK_CH14_RSVD_PG_8814B)\n#define BIT_SET_CH14_RSVD_PG_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH14_RSVD_PG_8814B(x) | BIT_CH14_RSVD_PG_8814B(v))\n\n/* 2 REG_DMA_RQPN_INFO_15_8814B */\n\n#define BIT_SHIFT_CH15_AVAL_PG_8814B 16\n#define BIT_MASK_CH15_AVAL_PG_8814B 0xfff\n#define BIT_CH15_AVAL_PG_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH15_AVAL_PG_8814B) << BIT_SHIFT_CH15_AVAL_PG_8814B)\n#define BITS_CH15_AVAL_PG_8814B                                                \\\n\t(BIT_MASK_CH15_AVAL_PG_8814B << BIT_SHIFT_CH15_AVAL_PG_8814B)\n#define BIT_CLEAR_CH15_AVAL_PG_8814B(x) ((x) & (~BITS_CH15_AVAL_PG_8814B))\n#define BIT_GET_CH15_AVAL_PG_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH15_AVAL_PG_8814B) & BIT_MASK_CH15_AVAL_PG_8814B)\n#define BIT_SET_CH15_AVAL_PG_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH15_AVAL_PG_8814B(x) | BIT_CH15_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_CH15_RSVD_PG_8814B 0\n#define BIT_MASK_CH15_RSVD_PG_8814B 0xfff\n#define BIT_CH15_RSVD_PG_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH15_RSVD_PG_8814B) << BIT_SHIFT_CH15_RSVD_PG_8814B)\n#define BITS_CH15_RSVD_PG_8814B                                                \\\n\t(BIT_MASK_CH15_RSVD_PG_8814B << BIT_SHIFT_CH15_RSVD_PG_8814B)\n#define BIT_CLEAR_CH15_RSVD_PG_8814B(x) ((x) & (~BITS_CH15_RSVD_PG_8814B))\n#define BIT_GET_CH15_RSVD_PG_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH15_RSVD_PG_8814B) & BIT_MASK_CH15_RSVD_PG_8814B)\n#define BIT_SET_CH15_RSVD_PG_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH15_RSVD_PG_8814B(x) | BIT_CH15_RSVD_PG_8814B(v))\n\n/* 2 REG_DMA_RQPN_INFO_16_8814B */\n\n#define BIT_SHIFT_CH16_AVAL_PG_8814B 16\n#define BIT_MASK_CH16_AVAL_PG_8814B 0xfff\n#define BIT_CH16_AVAL_PG_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH16_AVAL_PG_8814B) << BIT_SHIFT_CH16_AVAL_PG_8814B)\n#define BITS_CH16_AVAL_PG_8814B                                                \\\n\t(BIT_MASK_CH16_AVAL_PG_8814B << BIT_SHIFT_CH16_AVAL_PG_8814B)\n#define BIT_CLEAR_CH16_AVAL_PG_8814B(x) ((x) & (~BITS_CH16_AVAL_PG_8814B))\n#define BIT_GET_CH16_AVAL_PG_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH16_AVAL_PG_8814B) & BIT_MASK_CH16_AVAL_PG_8814B)\n#define BIT_SET_CH16_AVAL_PG_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH16_AVAL_PG_8814B(x) | BIT_CH16_AVAL_PG_8814B(v))\n\n#define BIT_SHIFT_CH16_RSVD_PG_8814B 0\n#define BIT_MASK_CH16_RSVD_PG_8814B 0xfff\n#define BIT_CH16_RSVD_PG_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH16_RSVD_PG_8814B) << BIT_SHIFT_CH16_RSVD_PG_8814B)\n#define BITS_CH16_RSVD_PG_8814B                                                \\\n\t(BIT_MASK_CH16_RSVD_PG_8814B << BIT_SHIFT_CH16_RSVD_PG_8814B)\n#define BIT_CLEAR_CH16_RSVD_PG_8814B(x) ((x) & (~BITS_CH16_RSVD_PG_8814B))\n#define BIT_GET_CH16_RSVD_PG_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH16_RSVD_PG_8814B) & BIT_MASK_CH16_RSVD_PG_8814B)\n#define BIT_SET_CH16_RSVD_PG_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH16_RSVD_PG_8814B(x) | BIT_CH16_RSVD_PG_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_HWAMSDU_CTL1_8814B */\n\n#define BIT_SHIFT_HWAMSDU_PKTNUM_8814B 8\n#define BIT_MASK_HWAMSDU_PKTNUM_8814B 0x3f\n#define BIT_HWAMSDU_PKTNUM_8814B(x)                                            \\\n\t(((x) & BIT_MASK_HWAMSDU_PKTNUM_8814B)                                 \\\n\t << BIT_SHIFT_HWAMSDU_PKTNUM_8814B)\n#define BITS_HWAMSDU_PKTNUM_8814B                                              \\\n\t(BIT_MASK_HWAMSDU_PKTNUM_8814B << BIT_SHIFT_HWAMSDU_PKTNUM_8814B)\n#define BIT_CLEAR_HWAMSDU_PKTNUM_8814B(x) ((x) & (~BITS_HWAMSDU_PKTNUM_8814B))\n#define BIT_GET_HWAMSDU_PKTNUM_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HWAMSDU_PKTNUM_8814B) &                             \\\n\t BIT_MASK_HWAMSDU_PKTNUM_8814B)\n#define BIT_SET_HWAMSDU_PKTNUM_8814B(x, v)                                     \\\n\t(BIT_CLEAR_HWAMSDU_PKTNUM_8814B(x) | BIT_HWAMSDU_PKTNUM_8814B(v))\n\n#define BIT_HWAMSDU_BUSY_8814B BIT(7)\n#define BIT_SINGLE_AMSDU_8814B BIT(2)\n#define BIT_HWAMSDU_PADDING_MODE_8814B BIT(1)\n#define BIT_HWAMSDU_EN_8814B BIT(0)\n\n/* 2 REG_HWAMSDU_CTL2_8814B */\n\n#define BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B 16\n#define BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B 0xffff\n#define BIT_HWAMSDU_AMSDU_TIMEOUT_8814B(x)                                     \\\n\t(((x) & BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B)                          \\\n\t << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B)\n#define BITS_HWAMSDU_AMSDU_TIMEOUT_8814B                                       \\\n\t(BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B                                  \\\n\t << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B)\n#define BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT_8814B(x)                               \\\n\t((x) & (~BITS_HWAMSDU_AMSDU_TIMEOUT_8814B))\n#define BIT_GET_HWAMSDU_AMSDU_TIMEOUT_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B) &                      \\\n\t BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B)\n#define BIT_SET_HWAMSDU_AMSDU_TIMEOUT_8814B(x, v)                              \\\n\t(BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT_8814B(x) |                            \\\n\t BIT_HWAMSDU_AMSDU_TIMEOUT_8814B(v))\n\n#define BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B 0\n#define BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B 0xffff\n#define BIT_HWAMSDU_MSDU_TIMEOUT_8814B(x)                                      \\\n\t(((x) & BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B)                           \\\n\t << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B)\n#define BITS_HWAMSDU_MSDU_TIMEOUT_8814B                                        \\\n\t(BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B                                   \\\n\t << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B)\n#define BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT_8814B(x)                                \\\n\t((x) & (~BITS_HWAMSDU_MSDU_TIMEOUT_8814B))\n#define BIT_GET_HWAMSDU_MSDU_TIMEOUT_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B) &                       \\\n\t BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B)\n#define BIT_SET_HWAMSDU_MSDU_TIMEOUT_8814B(x, v)                               \\\n\t(BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT_8814B(x) |                             \\\n\t BIT_HWAMSDU_MSDU_TIMEOUT_8814B(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_0_8814B */\n#define BIT_CH0_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_CH0_HIGH_TH_8814B 16\n#define BIT_MASK_CH0_HIGH_TH_8814B 0xfff\n#define BIT_CH0_HIGH_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH0_HIGH_TH_8814B) << BIT_SHIFT_CH0_HIGH_TH_8814B)\n#define BITS_CH0_HIGH_TH_8814B                                                 \\\n\t(BIT_MASK_CH0_HIGH_TH_8814B << BIT_SHIFT_CH0_HIGH_TH_8814B)\n#define BIT_CLEAR_CH0_HIGH_TH_8814B(x) ((x) & (~BITS_CH0_HIGH_TH_8814B))\n#define BIT_GET_CH0_HIGH_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH0_HIGH_TH_8814B) & BIT_MASK_CH0_HIGH_TH_8814B)\n#define BIT_SET_CH0_HIGH_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH0_HIGH_TH_8814B(x) | BIT_CH0_HIGH_TH_8814B(v))\n\n#define BIT_SHIFT_CH0_LOW_TH_8814B 0\n#define BIT_MASK_CH0_LOW_TH_8814B 0xfff\n#define BIT_CH0_LOW_TH_8814B(x)                                                \\\n\t(((x) & BIT_MASK_CH0_LOW_TH_8814B) << BIT_SHIFT_CH0_LOW_TH_8814B)\n#define BITS_CH0_LOW_TH_8814B                                                  \\\n\t(BIT_MASK_CH0_LOW_TH_8814B << BIT_SHIFT_CH0_LOW_TH_8814B)\n#define BIT_CLEAR_CH0_LOW_TH_8814B(x) ((x) & (~BITS_CH0_LOW_TH_8814B))\n#define BIT_GET_CH0_LOW_TH_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_CH0_LOW_TH_8814B) & BIT_MASK_CH0_LOW_TH_8814B)\n#define BIT_SET_CH0_LOW_TH_8814B(x, v)                                         \\\n\t(BIT_CLEAR_CH0_LOW_TH_8814B(x) | BIT_CH0_LOW_TH_8814B(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_1_8814B */\n#define BIT_CH1_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_CH1_HIGH_TH_8814B 16\n#define BIT_MASK_CH1_HIGH_TH_8814B 0xfff\n#define BIT_CH1_HIGH_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH1_HIGH_TH_8814B) << BIT_SHIFT_CH1_HIGH_TH_8814B)\n#define BITS_CH1_HIGH_TH_8814B                                                 \\\n\t(BIT_MASK_CH1_HIGH_TH_8814B << BIT_SHIFT_CH1_HIGH_TH_8814B)\n#define BIT_CLEAR_CH1_HIGH_TH_8814B(x) ((x) & (~BITS_CH1_HIGH_TH_8814B))\n#define BIT_GET_CH1_HIGH_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH1_HIGH_TH_8814B) & BIT_MASK_CH1_HIGH_TH_8814B)\n#define BIT_SET_CH1_HIGH_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH1_HIGH_TH_8814B(x) | BIT_CH1_HIGH_TH_8814B(v))\n\n#define BIT_SHIFT_CH1_LOW_TH_8814B 0\n#define BIT_MASK_CH1_LOW_TH_8814B 0xfff\n#define BIT_CH1_LOW_TH_8814B(x)                                                \\\n\t(((x) & BIT_MASK_CH1_LOW_TH_8814B) << BIT_SHIFT_CH1_LOW_TH_8814B)\n#define BITS_CH1_LOW_TH_8814B                                                  \\\n\t(BIT_MASK_CH1_LOW_TH_8814B << BIT_SHIFT_CH1_LOW_TH_8814B)\n#define BIT_CLEAR_CH1_LOW_TH_8814B(x) ((x) & (~BITS_CH1_LOW_TH_8814B))\n#define BIT_GET_CH1_LOW_TH_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_CH1_LOW_TH_8814B) & BIT_MASK_CH1_LOW_TH_8814B)\n#define BIT_SET_CH1_LOW_TH_8814B(x, v)                                         \\\n\t(BIT_CLEAR_CH1_LOW_TH_8814B(x) | BIT_CH1_LOW_TH_8814B(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_2_8814B */\n#define BIT_CH2_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_CH2_HIGH_TH_8814B 16\n#define BIT_MASK_CH2_HIGH_TH_8814B 0xfff\n#define BIT_CH2_HIGH_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH2_HIGH_TH_8814B) << BIT_SHIFT_CH2_HIGH_TH_8814B)\n#define BITS_CH2_HIGH_TH_8814B                                                 \\\n\t(BIT_MASK_CH2_HIGH_TH_8814B << BIT_SHIFT_CH2_HIGH_TH_8814B)\n#define BIT_CLEAR_CH2_HIGH_TH_8814B(x) ((x) & (~BITS_CH2_HIGH_TH_8814B))\n#define BIT_GET_CH2_HIGH_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH2_HIGH_TH_8814B) & BIT_MASK_CH2_HIGH_TH_8814B)\n#define BIT_SET_CH2_HIGH_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH2_HIGH_TH_8814B(x) | BIT_CH2_HIGH_TH_8814B(v))\n\n#define BIT_SHIFT_CH2_LOW_TH_8814B 0\n#define BIT_MASK_CH2_LOW_TH_8814B 0xfff\n#define BIT_CH2_LOW_TH_8814B(x)                                                \\\n\t(((x) & BIT_MASK_CH2_LOW_TH_8814B) << BIT_SHIFT_CH2_LOW_TH_8814B)\n#define BITS_CH2_LOW_TH_8814B                                                  \\\n\t(BIT_MASK_CH2_LOW_TH_8814B << BIT_SHIFT_CH2_LOW_TH_8814B)\n#define BIT_CLEAR_CH2_LOW_TH_8814B(x) ((x) & (~BITS_CH2_LOW_TH_8814B))\n#define BIT_GET_CH2_LOW_TH_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_CH2_LOW_TH_8814B) & BIT_MASK_CH2_LOW_TH_8814B)\n#define BIT_SET_CH2_LOW_TH_8814B(x, v)                                         \\\n\t(BIT_CLEAR_CH2_LOW_TH_8814B(x) | BIT_CH2_LOW_TH_8814B(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_3_8814B */\n#define BIT_CH3_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_CH3_HIGH_TH_8814B 16\n#define BIT_MASK_CH3_HIGH_TH_8814B 0xfff\n#define BIT_CH3_HIGH_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH3_HIGH_TH_8814B) << BIT_SHIFT_CH3_HIGH_TH_8814B)\n#define BITS_CH3_HIGH_TH_8814B                                                 \\\n\t(BIT_MASK_CH3_HIGH_TH_8814B << BIT_SHIFT_CH3_HIGH_TH_8814B)\n#define BIT_CLEAR_CH3_HIGH_TH_8814B(x) ((x) & (~BITS_CH3_HIGH_TH_8814B))\n#define BIT_GET_CH3_HIGH_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH3_HIGH_TH_8814B) & BIT_MASK_CH3_HIGH_TH_8814B)\n#define BIT_SET_CH3_HIGH_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH3_HIGH_TH_8814B(x) | BIT_CH3_HIGH_TH_8814B(v))\n\n#define BIT_SHIFT_CH3_LOW_TH_8814B 0\n#define BIT_MASK_CH3_LOW_TH_8814B 0xfff\n#define BIT_CH3_LOW_TH_8814B(x)                                                \\\n\t(((x) & BIT_MASK_CH3_LOW_TH_8814B) << BIT_SHIFT_CH3_LOW_TH_8814B)\n#define BITS_CH3_LOW_TH_8814B                                                  \\\n\t(BIT_MASK_CH3_LOW_TH_8814B << BIT_SHIFT_CH3_LOW_TH_8814B)\n#define BIT_CLEAR_CH3_LOW_TH_8814B(x) ((x) & (~BITS_CH3_LOW_TH_8814B))\n#define BIT_GET_CH3_LOW_TH_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_CH3_LOW_TH_8814B) & BIT_MASK_CH3_LOW_TH_8814B)\n#define BIT_SET_CH3_LOW_TH_8814B(x, v)                                         \\\n\t(BIT_CLEAR_CH3_LOW_TH_8814B(x) | BIT_CH3_LOW_TH_8814B(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_4_8814B */\n#define BIT_CH4_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_CH4_HIGH_TH_8814B 16\n#define BIT_MASK_CH4_HIGH_TH_8814B 0xfff\n#define BIT_CH4_HIGH_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH4_HIGH_TH_8814B) << BIT_SHIFT_CH4_HIGH_TH_8814B)\n#define BITS_CH4_HIGH_TH_8814B                                                 \\\n\t(BIT_MASK_CH4_HIGH_TH_8814B << BIT_SHIFT_CH4_HIGH_TH_8814B)\n#define BIT_CLEAR_CH4_HIGH_TH_8814B(x) ((x) & (~BITS_CH4_HIGH_TH_8814B))\n#define BIT_GET_CH4_HIGH_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH4_HIGH_TH_8814B) & BIT_MASK_CH4_HIGH_TH_8814B)\n#define BIT_SET_CH4_HIGH_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH4_HIGH_TH_8814B(x) | BIT_CH4_HIGH_TH_8814B(v))\n\n#define BIT_SHIFT_CH4_LOW_TH_8814B 0\n#define BIT_MASK_CH4_LOW_TH_8814B 0xfff\n#define BIT_CH4_LOW_TH_8814B(x)                                                \\\n\t(((x) & BIT_MASK_CH4_LOW_TH_8814B) << BIT_SHIFT_CH4_LOW_TH_8814B)\n#define BITS_CH4_LOW_TH_8814B                                                  \\\n\t(BIT_MASK_CH4_LOW_TH_8814B << BIT_SHIFT_CH4_LOW_TH_8814B)\n#define BIT_CLEAR_CH4_LOW_TH_8814B(x) ((x) & (~BITS_CH4_LOW_TH_8814B))\n#define BIT_GET_CH4_LOW_TH_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_CH4_LOW_TH_8814B) & BIT_MASK_CH4_LOW_TH_8814B)\n#define BIT_SET_CH4_LOW_TH_8814B(x, v)                                         \\\n\t(BIT_CLEAR_CH4_LOW_TH_8814B(x) | BIT_CH4_LOW_TH_8814B(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_5_8814B */\n#define BIT_CH5_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_CH5_HIGH_TH_8814B 16\n#define BIT_MASK_CH5_HIGH_TH_8814B 0xfff\n#define BIT_CH5_HIGH_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH5_HIGH_TH_8814B) << BIT_SHIFT_CH5_HIGH_TH_8814B)\n#define BITS_CH5_HIGH_TH_8814B                                                 \\\n\t(BIT_MASK_CH5_HIGH_TH_8814B << BIT_SHIFT_CH5_HIGH_TH_8814B)\n#define BIT_CLEAR_CH5_HIGH_TH_8814B(x) ((x) & (~BITS_CH5_HIGH_TH_8814B))\n#define BIT_GET_CH5_HIGH_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH5_HIGH_TH_8814B) & BIT_MASK_CH5_HIGH_TH_8814B)\n#define BIT_SET_CH5_HIGH_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH5_HIGH_TH_8814B(x) | BIT_CH5_HIGH_TH_8814B(v))\n\n#define BIT_SHIFT_CH5_LOW_TH_8814B 0\n#define BIT_MASK_CH5_LOW_TH_8814B 0xfff\n#define BIT_CH5_LOW_TH_8814B(x)                                                \\\n\t(((x) & BIT_MASK_CH5_LOW_TH_8814B) << BIT_SHIFT_CH5_LOW_TH_8814B)\n#define BITS_CH5_LOW_TH_8814B                                                  \\\n\t(BIT_MASK_CH5_LOW_TH_8814B << BIT_SHIFT_CH5_LOW_TH_8814B)\n#define BIT_CLEAR_CH5_LOW_TH_8814B(x) ((x) & (~BITS_CH5_LOW_TH_8814B))\n#define BIT_GET_CH5_LOW_TH_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_CH5_LOW_TH_8814B) & BIT_MASK_CH5_LOW_TH_8814B)\n#define BIT_SET_CH5_LOW_TH_8814B(x, v)                                         \\\n\t(BIT_CLEAR_CH5_LOW_TH_8814B(x) | BIT_CH5_LOW_TH_8814B(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_6_8814B */\n#define BIT_CH6_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_CH6_HIGH_TH_8814B 16\n#define BIT_MASK_CH6_HIGH_TH_8814B 0xfff\n#define BIT_CH6_HIGH_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH6_HIGH_TH_8814B) << BIT_SHIFT_CH6_HIGH_TH_8814B)\n#define BITS_CH6_HIGH_TH_8814B                                                 \\\n\t(BIT_MASK_CH6_HIGH_TH_8814B << BIT_SHIFT_CH6_HIGH_TH_8814B)\n#define BIT_CLEAR_CH6_HIGH_TH_8814B(x) ((x) & (~BITS_CH6_HIGH_TH_8814B))\n#define BIT_GET_CH6_HIGH_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH6_HIGH_TH_8814B) & BIT_MASK_CH6_HIGH_TH_8814B)\n#define BIT_SET_CH6_HIGH_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH6_HIGH_TH_8814B(x) | BIT_CH6_HIGH_TH_8814B(v))\n\n#define BIT_SHIFT_CH6_LOW_TH_8814B 0\n#define BIT_MASK_CH6_LOW_TH_8814B 0xfff\n#define BIT_CH6_LOW_TH_8814B(x)                                                \\\n\t(((x) & BIT_MASK_CH6_LOW_TH_8814B) << BIT_SHIFT_CH6_LOW_TH_8814B)\n#define BITS_CH6_LOW_TH_8814B                                                  \\\n\t(BIT_MASK_CH6_LOW_TH_8814B << BIT_SHIFT_CH6_LOW_TH_8814B)\n#define BIT_CLEAR_CH6_LOW_TH_8814B(x) ((x) & (~BITS_CH6_LOW_TH_8814B))\n#define BIT_GET_CH6_LOW_TH_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_CH6_LOW_TH_8814B) & BIT_MASK_CH6_LOW_TH_8814B)\n#define BIT_SET_CH6_LOW_TH_8814B(x, v)                                         \\\n\t(BIT_CLEAR_CH6_LOW_TH_8814B(x) | BIT_CH6_LOW_TH_8814B(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_7_8814B */\n#define BIT_CH7_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_CH7_HIGH_TH_8814B 16\n#define BIT_MASK_CH7_HIGH_TH_8814B 0xfff\n#define BIT_CH7_HIGH_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH7_HIGH_TH_8814B) << BIT_SHIFT_CH7_HIGH_TH_8814B)\n#define BITS_CH7_HIGH_TH_8814B                                                 \\\n\t(BIT_MASK_CH7_HIGH_TH_8814B << BIT_SHIFT_CH7_HIGH_TH_8814B)\n#define BIT_CLEAR_CH7_HIGH_TH_8814B(x) ((x) & (~BITS_CH7_HIGH_TH_8814B))\n#define BIT_GET_CH7_HIGH_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH7_HIGH_TH_8814B) & BIT_MASK_CH7_HIGH_TH_8814B)\n#define BIT_SET_CH7_HIGH_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH7_HIGH_TH_8814B(x) | BIT_CH7_HIGH_TH_8814B(v))\n\n#define BIT_SHIFT_CH7_LOW_TH_8814B 0\n#define BIT_MASK_CH7_LOW_TH_8814B 0xfff\n#define BIT_CH7_LOW_TH_8814B(x)                                                \\\n\t(((x) & BIT_MASK_CH7_LOW_TH_8814B) << BIT_SHIFT_CH7_LOW_TH_8814B)\n#define BITS_CH7_LOW_TH_8814B                                                  \\\n\t(BIT_MASK_CH7_LOW_TH_8814B << BIT_SHIFT_CH7_LOW_TH_8814B)\n#define BIT_CLEAR_CH7_LOW_TH_8814B(x) ((x) & (~BITS_CH7_LOW_TH_8814B))\n#define BIT_GET_CH7_LOW_TH_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_CH7_LOW_TH_8814B) & BIT_MASK_CH7_LOW_TH_8814B)\n#define BIT_SET_CH7_LOW_TH_8814B(x, v)                                         \\\n\t(BIT_CLEAR_CH7_LOW_TH_8814B(x) | BIT_CH7_LOW_TH_8814B(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_8_8814B */\n#define BIT_CH8_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_CH8_HIGH_TH_8814B 16\n#define BIT_MASK_CH8_HIGH_TH_8814B 0xfff\n#define BIT_CH8_HIGH_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH8_HIGH_TH_8814B) << BIT_SHIFT_CH8_HIGH_TH_8814B)\n#define BITS_CH8_HIGH_TH_8814B                                                 \\\n\t(BIT_MASK_CH8_HIGH_TH_8814B << BIT_SHIFT_CH8_HIGH_TH_8814B)\n#define BIT_CLEAR_CH8_HIGH_TH_8814B(x) ((x) & (~BITS_CH8_HIGH_TH_8814B))\n#define BIT_GET_CH8_HIGH_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH8_HIGH_TH_8814B) & BIT_MASK_CH8_HIGH_TH_8814B)\n#define BIT_SET_CH8_HIGH_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH8_HIGH_TH_8814B(x) | BIT_CH8_HIGH_TH_8814B(v))\n\n#define BIT_SHIFT_CH8_LOW_TH_8814B 0\n#define BIT_MASK_CH8_LOW_TH_8814B 0xfff\n#define BIT_CH8_LOW_TH_8814B(x)                                                \\\n\t(((x) & BIT_MASK_CH8_LOW_TH_8814B) << BIT_SHIFT_CH8_LOW_TH_8814B)\n#define BITS_CH8_LOW_TH_8814B                                                  \\\n\t(BIT_MASK_CH8_LOW_TH_8814B << BIT_SHIFT_CH8_LOW_TH_8814B)\n#define BIT_CLEAR_CH8_LOW_TH_8814B(x) ((x) & (~BITS_CH8_LOW_TH_8814B))\n#define BIT_GET_CH8_LOW_TH_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_CH8_LOW_TH_8814B) & BIT_MASK_CH8_LOW_TH_8814B)\n#define BIT_SET_CH8_LOW_TH_8814B(x, v)                                         \\\n\t(BIT_CLEAR_CH8_LOW_TH_8814B(x) | BIT_CH8_LOW_TH_8814B(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_9_8814B */\n#define BIT_CH9_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_CH9_HIGH_TH_8814B 16\n#define BIT_MASK_CH9_HIGH_TH_8814B 0xfff\n#define BIT_CH9_HIGH_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH9_HIGH_TH_8814B) << BIT_SHIFT_CH9_HIGH_TH_8814B)\n#define BITS_CH9_HIGH_TH_8814B                                                 \\\n\t(BIT_MASK_CH9_HIGH_TH_8814B << BIT_SHIFT_CH9_HIGH_TH_8814B)\n#define BIT_CLEAR_CH9_HIGH_TH_8814B(x) ((x) & (~BITS_CH9_HIGH_TH_8814B))\n#define BIT_GET_CH9_HIGH_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH9_HIGH_TH_8814B) & BIT_MASK_CH9_HIGH_TH_8814B)\n#define BIT_SET_CH9_HIGH_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH9_HIGH_TH_8814B(x) | BIT_CH9_HIGH_TH_8814B(v))\n\n#define BIT_SHIFT_CH9_LOW_TH_8814B 0\n#define BIT_MASK_CH9_LOW_TH_8814B 0xfff\n#define BIT_CH9_LOW_TH_8814B(x)                                                \\\n\t(((x) & BIT_MASK_CH9_LOW_TH_8814B) << BIT_SHIFT_CH9_LOW_TH_8814B)\n#define BITS_CH9_LOW_TH_8814B                                                  \\\n\t(BIT_MASK_CH9_LOW_TH_8814B << BIT_SHIFT_CH9_LOW_TH_8814B)\n#define BIT_CLEAR_CH9_LOW_TH_8814B(x) ((x) & (~BITS_CH9_LOW_TH_8814B))\n#define BIT_GET_CH9_LOW_TH_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_CH9_LOW_TH_8814B) & BIT_MASK_CH9_LOW_TH_8814B)\n#define BIT_SET_CH9_LOW_TH_8814B(x, v)                                         \\\n\t(BIT_CLEAR_CH9_LOW_TH_8814B(x) | BIT_CH9_LOW_TH_8814B(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_10_8814B */\n#define BIT_CH10_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_CH10_HIGH_TH_8814B 16\n#define BIT_MASK_CH10_HIGH_TH_8814B 0xfff\n#define BIT_CH10_HIGH_TH_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH10_HIGH_TH_8814B) << BIT_SHIFT_CH10_HIGH_TH_8814B)\n#define BITS_CH10_HIGH_TH_8814B                                                \\\n\t(BIT_MASK_CH10_HIGH_TH_8814B << BIT_SHIFT_CH10_HIGH_TH_8814B)\n#define BIT_CLEAR_CH10_HIGH_TH_8814B(x) ((x) & (~BITS_CH10_HIGH_TH_8814B))\n#define BIT_GET_CH10_HIGH_TH_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH10_HIGH_TH_8814B) & BIT_MASK_CH10_HIGH_TH_8814B)\n#define BIT_SET_CH10_HIGH_TH_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH10_HIGH_TH_8814B(x) | BIT_CH10_HIGH_TH_8814B(v))\n\n#define BIT_SHIFT_CH10_LOW_TH_8814B 0\n#define BIT_MASK_CH10_LOW_TH_8814B 0xfff\n#define BIT_CH10_LOW_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH10_LOW_TH_8814B) << BIT_SHIFT_CH10_LOW_TH_8814B)\n#define BITS_CH10_LOW_TH_8814B                                                 \\\n\t(BIT_MASK_CH10_LOW_TH_8814B << BIT_SHIFT_CH10_LOW_TH_8814B)\n#define BIT_CLEAR_CH10_LOW_TH_8814B(x) ((x) & (~BITS_CH10_LOW_TH_8814B))\n#define BIT_GET_CH10_LOW_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH10_LOW_TH_8814B) & BIT_MASK_CH10_LOW_TH_8814B)\n#define BIT_SET_CH10_LOW_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH10_LOW_TH_8814B(x) | BIT_CH10_LOW_TH_8814B(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_11_8814B */\n#define BIT_CH11_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_CH11_HIGH_TH_8814B 16\n#define BIT_MASK_CH11_HIGH_TH_8814B 0xfff\n#define BIT_CH11_HIGH_TH_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH11_HIGH_TH_8814B) << BIT_SHIFT_CH11_HIGH_TH_8814B)\n#define BITS_CH11_HIGH_TH_8814B                                                \\\n\t(BIT_MASK_CH11_HIGH_TH_8814B << BIT_SHIFT_CH11_HIGH_TH_8814B)\n#define BIT_CLEAR_CH11_HIGH_TH_8814B(x) ((x) & (~BITS_CH11_HIGH_TH_8814B))\n#define BIT_GET_CH11_HIGH_TH_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH11_HIGH_TH_8814B) & BIT_MASK_CH11_HIGH_TH_8814B)\n#define BIT_SET_CH11_HIGH_TH_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH11_HIGH_TH_8814B(x) | BIT_CH11_HIGH_TH_8814B(v))\n\n#define BIT_SHIFT_CH11_LOW_TH_8814B 0\n#define BIT_MASK_CH11_LOW_TH_8814B 0xfff\n#define BIT_CH11_LOW_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH11_LOW_TH_8814B) << BIT_SHIFT_CH11_LOW_TH_8814B)\n#define BITS_CH11_LOW_TH_8814B                                                 \\\n\t(BIT_MASK_CH11_LOW_TH_8814B << BIT_SHIFT_CH11_LOW_TH_8814B)\n#define BIT_CLEAR_CH11_LOW_TH_8814B(x) ((x) & (~BITS_CH11_LOW_TH_8814B))\n#define BIT_GET_CH11_LOW_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH11_LOW_TH_8814B) & BIT_MASK_CH11_LOW_TH_8814B)\n#define BIT_SET_CH11_LOW_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH11_LOW_TH_8814B(x) | BIT_CH11_LOW_TH_8814B(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_12_8814B */\n#define BIT_CH12_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_CH12_HIGH_TH_8814B 16\n#define BIT_MASK_CH12_HIGH_TH_8814B 0xfff\n#define BIT_CH12_HIGH_TH_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH12_HIGH_TH_8814B) << BIT_SHIFT_CH12_HIGH_TH_8814B)\n#define BITS_CH12_HIGH_TH_8814B                                                \\\n\t(BIT_MASK_CH12_HIGH_TH_8814B << BIT_SHIFT_CH12_HIGH_TH_8814B)\n#define BIT_CLEAR_CH12_HIGH_TH_8814B(x) ((x) & (~BITS_CH12_HIGH_TH_8814B))\n#define BIT_GET_CH12_HIGH_TH_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH12_HIGH_TH_8814B) & BIT_MASK_CH12_HIGH_TH_8814B)\n#define BIT_SET_CH12_HIGH_TH_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH12_HIGH_TH_8814B(x) | BIT_CH12_HIGH_TH_8814B(v))\n\n#define BIT_SHIFT_CH12_LOW_TH_8814B 0\n#define BIT_MASK_CH12_LOW_TH_8814B 0xfff\n#define BIT_CH12_LOW_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH12_LOW_TH_8814B) << BIT_SHIFT_CH12_LOW_TH_8814B)\n#define BITS_CH12_LOW_TH_8814B                                                 \\\n\t(BIT_MASK_CH12_LOW_TH_8814B << BIT_SHIFT_CH12_LOW_TH_8814B)\n#define BIT_CLEAR_CH12_LOW_TH_8814B(x) ((x) & (~BITS_CH12_LOW_TH_8814B))\n#define BIT_GET_CH12_LOW_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH12_LOW_TH_8814B) & BIT_MASK_CH12_LOW_TH_8814B)\n#define BIT_SET_CH12_LOW_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH12_LOW_TH_8814B(x) | BIT_CH12_LOW_TH_8814B(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_13_8814B */\n#define BIT_CH13_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_CH13_HIGH_TH_8814B 16\n#define BIT_MASK_CH13_HIGH_TH_8814B 0xfff\n#define BIT_CH13_HIGH_TH_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH13_HIGH_TH_8814B) << BIT_SHIFT_CH13_HIGH_TH_8814B)\n#define BITS_CH13_HIGH_TH_8814B                                                \\\n\t(BIT_MASK_CH13_HIGH_TH_8814B << BIT_SHIFT_CH13_HIGH_TH_8814B)\n#define BIT_CLEAR_CH13_HIGH_TH_8814B(x) ((x) & (~BITS_CH13_HIGH_TH_8814B))\n#define BIT_GET_CH13_HIGH_TH_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH13_HIGH_TH_8814B) & BIT_MASK_CH13_HIGH_TH_8814B)\n#define BIT_SET_CH13_HIGH_TH_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH13_HIGH_TH_8814B(x) | BIT_CH13_HIGH_TH_8814B(v))\n\n#define BIT_SHIFT_CH13_LOW_TH_8814B 0\n#define BIT_MASK_CH13_LOW_TH_8814B 0xfff\n#define BIT_CH13_LOW_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH13_LOW_TH_8814B) << BIT_SHIFT_CH13_LOW_TH_8814B)\n#define BITS_CH13_LOW_TH_8814B                                                 \\\n\t(BIT_MASK_CH13_LOW_TH_8814B << BIT_SHIFT_CH13_LOW_TH_8814B)\n#define BIT_CLEAR_CH13_LOW_TH_8814B(x) ((x) & (~BITS_CH13_LOW_TH_8814B))\n#define BIT_GET_CH13_LOW_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH13_LOW_TH_8814B) & BIT_MASK_CH13_LOW_TH_8814B)\n#define BIT_SET_CH13_LOW_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH13_LOW_TH_8814B(x) | BIT_CH13_LOW_TH_8814B(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_14_8814B */\n#define BIT_CH14_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_CH14_HIGH_TH_8814B 16\n#define BIT_MASK_CH14_HIGH_TH_8814B 0xfff\n#define BIT_CH14_HIGH_TH_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH14_HIGH_TH_8814B) << BIT_SHIFT_CH14_HIGH_TH_8814B)\n#define BITS_CH14_HIGH_TH_8814B                                                \\\n\t(BIT_MASK_CH14_HIGH_TH_8814B << BIT_SHIFT_CH14_HIGH_TH_8814B)\n#define BIT_CLEAR_CH14_HIGH_TH_8814B(x) ((x) & (~BITS_CH14_HIGH_TH_8814B))\n#define BIT_GET_CH14_HIGH_TH_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH14_HIGH_TH_8814B) & BIT_MASK_CH14_HIGH_TH_8814B)\n#define BIT_SET_CH14_HIGH_TH_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH14_HIGH_TH_8814B(x) | BIT_CH14_HIGH_TH_8814B(v))\n\n#define BIT_SHIFT_CH14_LOW_TH_8814B 0\n#define BIT_MASK_CH14_LOW_TH_8814B 0xfff\n#define BIT_CH14_LOW_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH14_LOW_TH_8814B) << BIT_SHIFT_CH14_LOW_TH_8814B)\n#define BITS_CH14_LOW_TH_8814B                                                 \\\n\t(BIT_MASK_CH14_LOW_TH_8814B << BIT_SHIFT_CH14_LOW_TH_8814B)\n#define BIT_CLEAR_CH14_LOW_TH_8814B(x) ((x) & (~BITS_CH14_LOW_TH_8814B))\n#define BIT_GET_CH14_LOW_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH14_LOW_TH_8814B) & BIT_MASK_CH14_LOW_TH_8814B)\n#define BIT_SET_CH14_LOW_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH14_LOW_TH_8814B(x) | BIT_CH14_LOW_TH_8814B(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_15_8814B */\n#define BIT_CH15_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_CH15_HIGH_TH_8814B 16\n#define BIT_MASK_CH15_HIGH_TH_8814B 0xfff\n#define BIT_CH15_HIGH_TH_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH15_HIGH_TH_8814B) << BIT_SHIFT_CH15_HIGH_TH_8814B)\n#define BITS_CH15_HIGH_TH_8814B                                                \\\n\t(BIT_MASK_CH15_HIGH_TH_8814B << BIT_SHIFT_CH15_HIGH_TH_8814B)\n#define BIT_CLEAR_CH15_HIGH_TH_8814B(x) ((x) & (~BITS_CH15_HIGH_TH_8814B))\n#define BIT_GET_CH15_HIGH_TH_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH15_HIGH_TH_8814B) & BIT_MASK_CH15_HIGH_TH_8814B)\n#define BIT_SET_CH15_HIGH_TH_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH15_HIGH_TH_8814B(x) | BIT_CH15_HIGH_TH_8814B(v))\n\n#define BIT_SHIFT_CH15_LOW_TH_8814B 0\n#define BIT_MASK_CH15_LOW_TH_8814B 0xfff\n#define BIT_CH15_LOW_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH15_LOW_TH_8814B) << BIT_SHIFT_CH15_LOW_TH_8814B)\n#define BITS_CH15_LOW_TH_8814B                                                 \\\n\t(BIT_MASK_CH15_LOW_TH_8814B << BIT_SHIFT_CH15_LOW_TH_8814B)\n#define BIT_CLEAR_CH15_LOW_TH_8814B(x) ((x) & (~BITS_CH15_LOW_TH_8814B))\n#define BIT_GET_CH15_LOW_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH15_LOW_TH_8814B) & BIT_MASK_CH15_LOW_TH_8814B)\n#define BIT_SET_CH15_LOW_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH15_LOW_TH_8814B(x) | BIT_CH15_LOW_TH_8814B(v))\n\n/* 2 REG_TXPAGE_INT_CTRL_16_8814B */\n#define BIT_CH16_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_CH16_HIGH_TH_8814B 16\n#define BIT_MASK_CH16_HIGH_TH_8814B 0xfff\n#define BIT_CH16_HIGH_TH_8814B(x)                                              \\\n\t(((x) & BIT_MASK_CH16_HIGH_TH_8814B) << BIT_SHIFT_CH16_HIGH_TH_8814B)\n#define BITS_CH16_HIGH_TH_8814B                                                \\\n\t(BIT_MASK_CH16_HIGH_TH_8814B << BIT_SHIFT_CH16_HIGH_TH_8814B)\n#define BIT_CLEAR_CH16_HIGH_TH_8814B(x) ((x) & (~BITS_CH16_HIGH_TH_8814B))\n#define BIT_GET_CH16_HIGH_TH_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CH16_HIGH_TH_8814B) & BIT_MASK_CH16_HIGH_TH_8814B)\n#define BIT_SET_CH16_HIGH_TH_8814B(x, v)                                       \\\n\t(BIT_CLEAR_CH16_HIGH_TH_8814B(x) | BIT_CH16_HIGH_TH_8814B(v))\n\n#define BIT_SHIFT_CH16_LOW_TH_8814B 0\n#define BIT_MASK_CH16_LOW_TH_8814B 0xfff\n#define BIT_CH16_LOW_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_CH16_LOW_TH_8814B) << BIT_SHIFT_CH16_LOW_TH_8814B)\n#define BITS_CH16_LOW_TH_8814B                                                 \\\n\t(BIT_MASK_CH16_LOW_TH_8814B << BIT_SHIFT_CH16_LOW_TH_8814B)\n#define BIT_CLEAR_CH16_LOW_TH_8814B(x) ((x) & (~BITS_CH16_LOW_TH_8814B))\n#define BIT_GET_CH16_LOW_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CH16_LOW_TH_8814B) & BIT_MASK_CH16_LOW_TH_8814B)\n#define BIT_SET_CH16_LOW_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_CH16_LOW_TH_8814B(x) | BIT_CH16_LOW_TH_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_PCIE_CTRL_8814B */\n#define BIT_PCIEIO_PERSTB_SEL_8814B BIT(31)\n\n#define BIT_SHIFT_PCIE_MAX_RXDMA_8814B 28\n#define BIT_MASK_PCIE_MAX_RXDMA_8814B 0x7\n#define BIT_PCIE_MAX_RXDMA_8814B(x)                                            \\\n\t(((x) & BIT_MASK_PCIE_MAX_RXDMA_8814B)                                 \\\n\t << BIT_SHIFT_PCIE_MAX_RXDMA_8814B)\n#define BITS_PCIE_MAX_RXDMA_8814B                                              \\\n\t(BIT_MASK_PCIE_MAX_RXDMA_8814B << BIT_SHIFT_PCIE_MAX_RXDMA_8814B)\n#define BIT_CLEAR_PCIE_MAX_RXDMA_8814B(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8814B))\n#define BIT_GET_PCIE_MAX_RXDMA_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8814B) &                             \\\n\t BIT_MASK_PCIE_MAX_RXDMA_8814B)\n#define BIT_SET_PCIE_MAX_RXDMA_8814B(x, v)                                     \\\n\t(BIT_CLEAR_PCIE_MAX_RXDMA_8814B(x) | BIT_PCIE_MAX_RXDMA_8814B(v))\n\n#define BIT_MULRW_8814B BIT(27)\n\n#define BIT_SHIFT_PCIE_MAX_TXDMA_8814B 24\n#define BIT_MASK_PCIE_MAX_TXDMA_8814B 0x7\n#define BIT_PCIE_MAX_TXDMA_8814B(x)                                            \\\n\t(((x) & BIT_MASK_PCIE_MAX_TXDMA_8814B)                                 \\\n\t << BIT_SHIFT_PCIE_MAX_TXDMA_8814B)\n#define BITS_PCIE_MAX_TXDMA_8814B                                              \\\n\t(BIT_MASK_PCIE_MAX_TXDMA_8814B << BIT_SHIFT_PCIE_MAX_TXDMA_8814B)\n#define BIT_CLEAR_PCIE_MAX_TXDMA_8814B(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8814B))\n#define BIT_GET_PCIE_MAX_TXDMA_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8814B) &                             \\\n\t BIT_MASK_PCIE_MAX_TXDMA_8814B)\n#define BIT_SET_PCIE_MAX_TXDMA_8814B(x, v)                                     \\\n\t(BIT_CLEAR_PCIE_MAX_TXDMA_8814B(x) | BIT_PCIE_MAX_TXDMA_8814B(v))\n\n#define BIT_PWR_SCALE_START_PS_8814B BIT(23)\n#define BIT_EN_CPL_TIMEOUT_PS_8814B BIT(22)\n#define BIT_REG_TXDMA_FAIL_PS_8814B BIT(21)\n#define BIT_PCIE_RST_TRXDMA_INTF_8814B BIT(20)\n#define BIT_EN_HWENTR_L1_8814B BIT(19)\n#define BIT_EN_ADV_CLKGATE_8814B BIT(18)\n#define BIT_PCIE_EN_SWENT_L23_8814B BIT(17)\n#define BIT_PCIE_EN_HWEXT_L1_8814B BIT(16)\n#define BIT_STOP_P0_MPRT_BCNQ4_8814B BIT(6)\n#define BIT_STOP_P0_MPRT_BCNQ3_8814B BIT(4)\n#define BIT_STOP_P0_MPRT_BCNQ2_8814B BIT(2)\n#define BIT_STOP_P0_MPRT_BCNQ1_8814B BIT(0)\n\n/* 2 REG_ACH_CTRL_8814B */\n#define BIT_STOP_P0HIQ19_8814B BIT(27)\n#define BIT_STOP_P0HIQ18_8814B BIT(26)\n#define BIT_STOP_P0HIQ17_8814B BIT(25)\n#define BIT_STOP_P0HIQ16_8814B BIT(24)\n#define BIT_RX_CLOSE_EN_V1_8814B BIT(21)\n#define BIT_STOP_FWCMDQ_8814B BIT(20)\n#define BIT_STOP_P0BCNQ_8814B BIT(18)\n#define BIT_STOP_P0MGQ_8814B BIT(16)\n#define BIT_STOP_ACH13_8814B BIT(15)\n#define BIT_STOP_ACH12_8814B BIT(14)\n#define BIT_STOP_ACH11_8814B BIT(13)\n#define BIT_STOP_ACH10_8814B BIT(12)\n#define BIT_STOP_ACH9_8814B BIT(11)\n#define BIT_STOP_ACH8_8814B BIT(10)\n#define BIT_STOP_ACH7_8814B BIT(9)\n#define BIT_STOP_ACH6_8814B BIT(8)\n#define BIT_STOP_ACH5_8814B BIT(7)\n#define BIT_STOP_ACH4_8814B BIT(6)\n#define BIT_STOP_ACH3_8814B BIT(5)\n#define BIT_STOP_ACH2_8814B BIT(4)\n#define BIT_STOP_ACH1_8814B BIT(3)\n#define BIT_STOP_ACH0_8814B BIT(2)\n#define BIT_STOP_P0RX_8814B BIT(0)\n\n/* 2 REG_HIQ_CTRL_8814B */\n#define BIT_STOP_P0HIQ15_8814B BIT(15)\n#define BIT_STOP_P0HIQ14_8814B BIT(14)\n#define BIT_STOP_P0HIQ13_8814B BIT(13)\n#define BIT_STOP_P0HIQ12_8814B BIT(12)\n#define BIT_STOP_P0HIQ11_8814B BIT(11)\n#define BIT_STOP_P0HIQ10_8814B BIT(10)\n#define BIT_STOP_P0HIQ9_8814B BIT(9)\n#define BIT_STOP_P0HIQ8_8814B BIT(8)\n#define BIT_STOP_P0HIQ7_8814B BIT(7)\n#define BIT_STOP_P0HIQ6_8814B BIT(6)\n#define BIT_STOP_P0HIQ5_8814B BIT(5)\n#define BIT_STOP_P0HIQ4_8814B BIT(4)\n#define BIT_STOP_P0HIQ3_8814B BIT(3)\n#define BIT_STOP_P0HIQ2_8814B BIT(2)\n#define BIT_STOP_P0HIQ1_8814B BIT(1)\n#define BIT_STOP_P0HIQ0_8814B BIT(0)\n\n/* 2 REG_INT_MIG_V1_8814B */\n\n#define BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B 28\n#define BIT_MASK_TXTTIMER_MATCH_NUM_8814B 0xf\n#define BIT_TXTTIMER_MATCH_NUM_8814B(x)                                        \\\n\t(((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8814B)                             \\\n\t << BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B)\n#define BITS_TXTTIMER_MATCH_NUM_8814B                                          \\\n\t(BIT_MASK_TXTTIMER_MATCH_NUM_8814B                                     \\\n\t << BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B)\n#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8814B(x)                                  \\\n\t((x) & (~BITS_TXTTIMER_MATCH_NUM_8814B))\n#define BIT_GET_TXTTIMER_MATCH_NUM_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B) &                         \\\n\t BIT_MASK_TXTTIMER_MATCH_NUM_8814B)\n#define BIT_SET_TXTTIMER_MATCH_NUM_8814B(x, v)                                 \\\n\t(BIT_CLEAR_TXTTIMER_MATCH_NUM_8814B(x) |                               \\\n\t BIT_TXTTIMER_MATCH_NUM_8814B(v))\n\n#define BIT_SHIFT_TXPKT_NUM_MATCH_8814B 24\n#define BIT_MASK_TXPKT_NUM_MATCH_8814B 0xf\n#define BIT_TXPKT_NUM_MATCH_8814B(x)                                           \\\n\t(((x) & BIT_MASK_TXPKT_NUM_MATCH_8814B)                                \\\n\t << BIT_SHIFT_TXPKT_NUM_MATCH_8814B)\n#define BITS_TXPKT_NUM_MATCH_8814B                                             \\\n\t(BIT_MASK_TXPKT_NUM_MATCH_8814B << BIT_SHIFT_TXPKT_NUM_MATCH_8814B)\n#define BIT_CLEAR_TXPKT_NUM_MATCH_8814B(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8814B))\n#define BIT_GET_TXPKT_NUM_MATCH_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8814B) &                            \\\n\t BIT_MASK_TXPKT_NUM_MATCH_8814B)\n#define BIT_SET_TXPKT_NUM_MATCH_8814B(x, v)                                    \\\n\t(BIT_CLEAR_TXPKT_NUM_MATCH_8814B(x) | BIT_TXPKT_NUM_MATCH_8814B(v))\n\n#define BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B 20\n#define BIT_MASK_RXTTIMER_MATCH_NUM_8814B 0xf\n#define BIT_RXTTIMER_MATCH_NUM_8814B(x)                                        \\\n\t(((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8814B)                             \\\n\t << BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B)\n#define BITS_RXTTIMER_MATCH_NUM_8814B                                          \\\n\t(BIT_MASK_RXTTIMER_MATCH_NUM_8814B                                     \\\n\t << BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B)\n#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8814B(x)                                  \\\n\t((x) & (~BITS_RXTTIMER_MATCH_NUM_8814B))\n#define BIT_GET_RXTTIMER_MATCH_NUM_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B) &                         \\\n\t BIT_MASK_RXTTIMER_MATCH_NUM_8814B)\n#define BIT_SET_RXTTIMER_MATCH_NUM_8814B(x, v)                                 \\\n\t(BIT_CLEAR_RXTTIMER_MATCH_NUM_8814B(x) |                               \\\n\t BIT_RXTTIMER_MATCH_NUM_8814B(v))\n\n#define BIT_SHIFT_RXPKT_NUM_MATCH_8814B 16\n#define BIT_MASK_RXPKT_NUM_MATCH_8814B 0xf\n#define BIT_RXPKT_NUM_MATCH_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RXPKT_NUM_MATCH_8814B)                                \\\n\t << BIT_SHIFT_RXPKT_NUM_MATCH_8814B)\n#define BITS_RXPKT_NUM_MATCH_8814B                                             \\\n\t(BIT_MASK_RXPKT_NUM_MATCH_8814B << BIT_SHIFT_RXPKT_NUM_MATCH_8814B)\n#define BIT_CLEAR_RXPKT_NUM_MATCH_8814B(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8814B))\n#define BIT_GET_RXPKT_NUM_MATCH_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8814B) &                            \\\n\t BIT_MASK_RXPKT_NUM_MATCH_8814B)\n#define BIT_SET_RXPKT_NUM_MATCH_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RXPKT_NUM_MATCH_8814B(x) | BIT_RXPKT_NUM_MATCH_8814B(v))\n\n#define BIT_SHIFT_MIGRATE_TIMER_8814B 0\n#define BIT_MASK_MIGRATE_TIMER_8814B 0xffff\n#define BIT_MIGRATE_TIMER_8814B(x)                                             \\\n\t(((x) & BIT_MASK_MIGRATE_TIMER_8814B) << BIT_SHIFT_MIGRATE_TIMER_8814B)\n#define BITS_MIGRATE_TIMER_8814B                                               \\\n\t(BIT_MASK_MIGRATE_TIMER_8814B << BIT_SHIFT_MIGRATE_TIMER_8814B)\n#define BIT_CLEAR_MIGRATE_TIMER_8814B(x) ((x) & (~BITS_MIGRATE_TIMER_8814B))\n#define BIT_GET_MIGRATE_TIMER_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MIGRATE_TIMER_8814B) & BIT_MASK_MIGRATE_TIMER_8814B)\n#define BIT_SET_MIGRATE_TIMER_8814B(x, v)                                      \\\n\t(BIT_CLEAR_MIGRATE_TIMER_8814B(x) | BIT_MIGRATE_TIMER_8814B(v))\n\n/* 2 REG_P0MGQ_TXBD_DESA_L_8814B */\n\n/* 2 REG_P0MGQ_TXBD_DESA_H_8814B */\n\n/* 2 REG_ACH0_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_ACH0_TXBD_DESA_L_8814B 0\n#define BIT_MASK_ACH0_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_ACH0_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH0_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_ACH0_TXBD_DESA_L_8814B)\n#define BITS_ACH0_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_ACH0_TXBD_DESA_L_8814B << BIT_SHIFT_ACH0_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_ACH0_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_ACH0_TXBD_DESA_L_8814B))\n#define BIT_GET_ACH0_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH0_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_ACH0_TXBD_DESA_L_8814B)\n#define BIT_SET_ACH0_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH0_TXBD_DESA_L_8814B(x) | BIT_ACH0_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_ACH0_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_ACH0_TXBD_DESA_H_8814B 0\n#define BIT_MASK_ACH0_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_ACH0_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH0_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_ACH0_TXBD_DESA_H_8814B)\n#define BITS_ACH0_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_ACH0_TXBD_DESA_H_8814B << BIT_SHIFT_ACH0_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_ACH0_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_ACH0_TXBD_DESA_H_8814B))\n#define BIT_GET_ACH0_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH0_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_ACH0_TXBD_DESA_H_8814B)\n#define BIT_SET_ACH0_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH0_TXBD_DESA_H_8814B(x) | BIT_ACH0_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_ACH1_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_ACH1_TXBD_DESA_L_8814B 0\n#define BIT_MASK_ACH1_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_ACH1_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH1_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_ACH1_TXBD_DESA_L_8814B)\n#define BITS_ACH1_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_ACH1_TXBD_DESA_L_8814B << BIT_SHIFT_ACH1_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_ACH1_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_ACH1_TXBD_DESA_L_8814B))\n#define BIT_GET_ACH1_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH1_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_ACH1_TXBD_DESA_L_8814B)\n#define BIT_SET_ACH1_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH1_TXBD_DESA_L_8814B(x) | BIT_ACH1_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_ACH1_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_ACH1_TXBD_DESA_H_8814B 0\n#define BIT_MASK_ACH1_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_ACH1_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH1_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_ACH1_TXBD_DESA_H_8814B)\n#define BITS_ACH1_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_ACH1_TXBD_DESA_H_8814B << BIT_SHIFT_ACH1_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_ACH1_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_ACH1_TXBD_DESA_H_8814B))\n#define BIT_GET_ACH1_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH1_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_ACH1_TXBD_DESA_H_8814B)\n#define BIT_SET_ACH1_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH1_TXBD_DESA_H_8814B(x) | BIT_ACH1_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_ACH2_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_ACH2_TXBD_DESA_L_8814B 0\n#define BIT_MASK_ACH2_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_ACH2_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH2_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_ACH2_TXBD_DESA_L_8814B)\n#define BITS_ACH2_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_ACH2_TXBD_DESA_L_8814B << BIT_SHIFT_ACH2_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_ACH2_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_ACH2_TXBD_DESA_L_8814B))\n#define BIT_GET_ACH2_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH2_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_ACH2_TXBD_DESA_L_8814B)\n#define BIT_SET_ACH2_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH2_TXBD_DESA_L_8814B(x) | BIT_ACH2_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_ACH2_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_ACH2_TXBD_DESA_H_8814B 0\n#define BIT_MASK_ACH2_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_ACH2_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH2_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_ACH2_TXBD_DESA_H_8814B)\n#define BITS_ACH2_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_ACH2_TXBD_DESA_H_8814B << BIT_SHIFT_ACH2_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_ACH2_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_ACH2_TXBD_DESA_H_8814B))\n#define BIT_GET_ACH2_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH2_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_ACH2_TXBD_DESA_H_8814B)\n#define BIT_SET_ACH2_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH2_TXBD_DESA_H_8814B(x) | BIT_ACH2_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_ACH3_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_ACH3_TXBD_DESA_L_8814B 0\n#define BIT_MASK_ACH3_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_ACH3_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH3_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_ACH3_TXBD_DESA_L_8814B)\n#define BITS_ACH3_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_ACH3_TXBD_DESA_L_8814B << BIT_SHIFT_ACH3_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_ACH3_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_ACH3_TXBD_DESA_L_8814B))\n#define BIT_GET_ACH3_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH3_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_ACH3_TXBD_DESA_L_8814B)\n#define BIT_SET_ACH3_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH3_TXBD_DESA_L_8814B(x) | BIT_ACH3_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_ACH3_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_ACH3_TXBD_DESA_H_8814B 0\n#define BIT_MASK_ACH3_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_ACH3_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH3_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_ACH3_TXBD_DESA_H_8814B)\n#define BITS_ACH3_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_ACH3_TXBD_DESA_H_8814B << BIT_SHIFT_ACH3_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_ACH3_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_ACH3_TXBD_DESA_H_8814B))\n#define BIT_GET_ACH3_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH3_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_ACH3_TXBD_DESA_H_8814B)\n#define BIT_SET_ACH3_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH3_TXBD_DESA_H_8814B(x) | BIT_ACH3_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_P0RXQ_RXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B 0\n#define BIT_MASK_P0RXQ_RXBD_DESA_L_8814B 0xffffffffL\n#define BIT_P0RXQ_RXBD_DESA_L_8814B(x)                                         \\\n\t(((x) & BIT_MASK_P0RXQ_RXBD_DESA_L_8814B)                              \\\n\t << BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B)\n#define BITS_P0RXQ_RXBD_DESA_L_8814B                                           \\\n\t(BIT_MASK_P0RXQ_RXBD_DESA_L_8814B << BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B)\n#define BIT_CLEAR_P0RXQ_RXBD_DESA_L_8814B(x)                                   \\\n\t((x) & (~BITS_P0RXQ_RXBD_DESA_L_8814B))\n#define BIT_GET_P0RXQ_RXBD_DESA_L_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B) &                          \\\n\t BIT_MASK_P0RXQ_RXBD_DESA_L_8814B)\n#define BIT_SET_P0RXQ_RXBD_DESA_L_8814B(x, v)                                  \\\n\t(BIT_CLEAR_P0RXQ_RXBD_DESA_L_8814B(x) | BIT_P0RXQ_RXBD_DESA_L_8814B(v))\n\n/* 2 REG_P0RXQ_RXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B 0\n#define BIT_MASK_P0RXQ_RXBD_DESA_H_8814B 0xffffffffL\n#define BIT_P0RXQ_RXBD_DESA_H_8814B(x)                                         \\\n\t(((x) & BIT_MASK_P0RXQ_RXBD_DESA_H_8814B)                              \\\n\t << BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B)\n#define BITS_P0RXQ_RXBD_DESA_H_8814B                                           \\\n\t(BIT_MASK_P0RXQ_RXBD_DESA_H_8814B << BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B)\n#define BIT_CLEAR_P0RXQ_RXBD_DESA_H_8814B(x)                                   \\\n\t((x) & (~BITS_P0RXQ_RXBD_DESA_H_8814B))\n#define BIT_GET_P0RXQ_RXBD_DESA_H_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B) &                          \\\n\t BIT_MASK_P0RXQ_RXBD_DESA_H_8814B)\n#define BIT_SET_P0RXQ_RXBD_DESA_H_8814B(x, v)                                  \\\n\t(BIT_CLEAR_P0RXQ_RXBD_DESA_H_8814B(x) | BIT_P0RXQ_RXBD_DESA_H_8814B(v))\n\n/* 2 REG_P0BCNQ_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B 0\n#define BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_P0BCNQ_TXBD_DESA_L_8814B(x)                                        \\\n\t(((x) & BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B)                             \\\n\t << BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B)\n#define BITS_P0BCNQ_TXBD_DESA_L_8814B                                          \\\n\t(BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B                                     \\\n\t << BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_P0BCNQ_TXBD_DESA_L_8814B(x)                                  \\\n\t((x) & (~BITS_P0BCNQ_TXBD_DESA_L_8814B))\n#define BIT_GET_P0BCNQ_TXBD_DESA_L_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B) &                         \\\n\t BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B)\n#define BIT_SET_P0BCNQ_TXBD_DESA_L_8814B(x, v)                                 \\\n\t(BIT_CLEAR_P0BCNQ_TXBD_DESA_L_8814B(x) |                               \\\n\t BIT_P0BCNQ_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_P0BCNQ_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B 0\n#define BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_P0BCNQ_TXBD_DESA_H_8814B(x)                                        \\\n\t(((x) & BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B)                             \\\n\t << BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B)\n#define BITS_P0BCNQ_TXBD_DESA_H_8814B                                          \\\n\t(BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B                                     \\\n\t << BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_P0BCNQ_TXBD_DESA_H_8814B(x)                                  \\\n\t((x) & (~BITS_P0BCNQ_TXBD_DESA_H_8814B))\n#define BIT_GET_P0BCNQ_TXBD_DESA_H_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B) &                         \\\n\t BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B)\n#define BIT_SET_P0BCNQ_TXBD_DESA_H_8814B(x, v)                                 \\\n\t(BIT_CLEAR_P0BCNQ_TXBD_DESA_H_8814B(x) |                               \\\n\t BIT_P0BCNQ_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_FWCMDQ_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B 0\n#define BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_FWCMDQ_TXBD_DESA_L_8814B(x)                                        \\\n\t(((x) & BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B)                             \\\n\t << BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B)\n#define BITS_FWCMDQ_TXBD_DESA_L_8814B                                          \\\n\t(BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B                                     \\\n\t << BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_FWCMDQ_TXBD_DESA_L_8814B(x)                                  \\\n\t((x) & (~BITS_FWCMDQ_TXBD_DESA_L_8814B))\n#define BIT_GET_FWCMDQ_TXBD_DESA_L_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B) &                         \\\n\t BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B)\n#define BIT_SET_FWCMDQ_TXBD_DESA_L_8814B(x, v)                                 \\\n\t(BIT_CLEAR_FWCMDQ_TXBD_DESA_L_8814B(x) |                               \\\n\t BIT_FWCMDQ_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_FWCMDQ_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B 0\n#define BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_FWCMDQ_TXBD_DESA_H_8814B(x)                                        \\\n\t(((x) & BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B)                             \\\n\t << BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B)\n#define BITS_FWCMDQ_TXBD_DESA_H_8814B                                          \\\n\t(BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B                                     \\\n\t << BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_FWCMDQ_TXBD_DESA_H_8814B(x)                                  \\\n\t((x) & (~BITS_FWCMDQ_TXBD_DESA_H_8814B))\n#define BIT_GET_FWCMDQ_TXBD_DESA_H_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B) &                         \\\n\t BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B)\n#define BIT_SET_FWCMDQ_TXBD_DESA_H_8814B(x, v)                                 \\\n\t(BIT_CLEAR_FWCMDQ_TXBD_DESA_H_8814B(x) |                               \\\n\t BIT_FWCMDQ_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_PCIE_HRPWM1_HCPWM1_DCPU_8814B */\n\n#define BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B 16\n#define BIT_MASK_PCIE_HCPWM1_DCPU_8814B 0xff\n#define BIT_PCIE_HCPWM1_DCPU_8814B(x)                                          \\\n\t(((x) & BIT_MASK_PCIE_HCPWM1_DCPU_8814B)                               \\\n\t << BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B)\n#define BITS_PCIE_HCPWM1_DCPU_8814B                                            \\\n\t(BIT_MASK_PCIE_HCPWM1_DCPU_8814B << BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B)\n#define BIT_CLEAR_PCIE_HCPWM1_DCPU_8814B(x)                                    \\\n\t((x) & (~BITS_PCIE_HCPWM1_DCPU_8814B))\n#define BIT_GET_PCIE_HCPWM1_DCPU_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B) &                           \\\n\t BIT_MASK_PCIE_HCPWM1_DCPU_8814B)\n#define BIT_SET_PCIE_HCPWM1_DCPU_8814B(x, v)                                   \\\n\t(BIT_CLEAR_PCIE_HCPWM1_DCPU_8814B(x) | BIT_PCIE_HCPWM1_DCPU_8814B(v))\n\n#define BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B 8\n#define BIT_MASK_PCIE_HRPWM1_DCPU_8814B 0xff\n#define BIT_PCIE_HRPWM1_DCPU_8814B(x)                                          \\\n\t(((x) & BIT_MASK_PCIE_HRPWM1_DCPU_8814B)                               \\\n\t << BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B)\n#define BITS_PCIE_HRPWM1_DCPU_8814B                                            \\\n\t(BIT_MASK_PCIE_HRPWM1_DCPU_8814B << BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B)\n#define BIT_CLEAR_PCIE_HRPWM1_DCPU_8814B(x)                                    \\\n\t((x) & (~BITS_PCIE_HRPWM1_DCPU_8814B))\n#define BIT_GET_PCIE_HRPWM1_DCPU_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B) &                           \\\n\t BIT_MASK_PCIE_HRPWM1_DCPU_8814B)\n#define BIT_SET_PCIE_HRPWM1_DCPU_8814B(x, v)                                   \\\n\t(BIT_CLEAR_PCIE_HRPWM1_DCPU_8814B(x) | BIT_PCIE_HRPWM1_DCPU_8814B(v))\n\n/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B 0\n#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x)                                  \\\n\t(((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B)                       \\\n\t << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B)\n#define BITS_P0_MPRT_BCNQ_TXBD_DESA_L_8814B                                    \\\n\t(BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B                               \\\n\t << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x)                            \\\n\t((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_L_8814B))\n#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x)                              \\\n\t(((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B) &                   \\\n\t BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B)\n#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x, v)                           \\\n\t(BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x) |                         \\\n\t BIT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B 0\n#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x)                                  \\\n\t(((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B)                       \\\n\t << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B)\n#define BITS_P0_MPRT_BCNQ_TXBD_DESA_H_8814B                                    \\\n\t(BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B                               \\\n\t << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x)                            \\\n\t((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_H_8814B))\n#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x)                              \\\n\t(((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B) &                   \\\n\t BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B)\n#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x, v)                           \\\n\t(BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x) |                         \\\n\t BIT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_P0_MPRT_BCNQ_TXRXBD_NUM_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B 13\n#define BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B 0x3\n#define BIT_P0_MPRT_BCNQ_DESC_MODE_8814B(x)                                    \\\n\t(((x) & BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B)                         \\\n\t << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B)\n#define BITS_P0_MPRT_BCNQ_DESC_MODE_8814B                                      \\\n\t(BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B                                 \\\n\t << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B)\n#define BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE_8814B(x)                              \\\n\t((x) & (~BITS_P0_MPRT_BCNQ_DESC_MODE_8814B))\n#define BIT_GET_P0_MPRT_BCNQ_DESC_MODE_8814B(x)                                \\\n\t(((x) >> BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B) &                     \\\n\t BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B)\n#define BIT_SET_P0_MPRT_BCNQ_DESC_MODE_8814B(x, v)                             \\\n\t(BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE_8814B(x) |                           \\\n\t BIT_P0_MPRT_BCNQ_DESC_MODE_8814B(v))\n\n#define BIT_PCIE_P0MPRT_BCNQ4_FLAG_8814B BIT(11)\n#define BIT_PCIE_P0MPRT_BCNQ3_FLAG_8814B BIT(10)\n#define BIT_PCIE_P0MPRT_BCNQ2_FLAG_8814B BIT(9)\n#define BIT_PCIE_P0MPRT_BCNQ1_FLAG_8814B BIT(8)\n#define BIT_EPHY_CAL_DONE_8814B BIT(1)\n#define BIT_RESET_APHY_8814B BIT(0)\n\n/* 2 REG_BD_RWPTR_CLR2_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_CLR_ACH7_HW_IDX_8814B BIT(21)\n#define BIT_CLR_ACH6_HW_IDX_8814B BIT(20)\n#define BIT_CLR_ACH5_HW_IDX_8814B BIT(19)\n#define BIT_CLR_ACH4_HW_IDX_8814B BIT(18)\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_CLR_ACH7_HOST_IDX_8814B BIT(5)\n#define BIT_CLR_ACH6_HOST_IDX_8814B BIT(4)\n#define BIT_CLR_ACH5_HOST_IDX_8814B BIT(3)\n#define BIT_CLR_ACH4_HOST_IDX_8814B BIT(2)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_BD_RWPTR_CLR3_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_CLR_P0HI15Q_HW_IDX_8814B BIT(29)\n#define BIT_CLR_P0HI14Q_HW_IDX_8814B BIT(28)\n#define BIT_CLR_P0HI13Q_HW_IDX_8814B BIT(27)\n#define BIT_CLR_P0HI12Q_HW_IDX_8814B BIT(26)\n#define BIT_CLR_P0HI11Q_HW_IDX_8814B BIT(25)\n#define BIT_CLR_P0HI10Q_HW_IDX_8814B BIT(24)\n#define BIT_CLR_P0HI9Q_HW_IDX_8814B BIT(23)\n#define BIT_CLR_P0HI8Q_HW_IDX_8814B BIT(22)\n#define BIT_CLR_ACH13_HW_IDX_8814B BIT(21)\n#define BIT_CLR_ACH12_HW_IDX_8814B BIT(20)\n#define BIT_CLR_ACH11_HW_IDX_8814B BIT(19)\n#define BIT_CLR_ACH10_HW_IDX_8814B BIT(18)\n#define BIT_CLR_ACH9_HW_IDX_8814B BIT(17)\n#define BIT_CLR_ACH8_HW_IDX_8814B BIT(16)\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_CLR_P0HI15Q_HOST_IDX_8814B BIT(13)\n#define BIT_CLR_P0HI14Q_HOST_IDX_8814B BIT(12)\n#define BIT_CLR_P0HI13Q_HOST_IDX_8814B BIT(11)\n#define BIT_CLR_P0HI12Q_HOST_IDX_8814B BIT(10)\n#define BIT_CLR_P0HI11Q_HOST_IDX_8814B BIT(9)\n#define BIT_CLR_P0HI10Q_HOST_IDX_8814B BIT(8)\n#define BIT_CLR_P0HI9Q_HOST_IDX_8814B BIT(7)\n#define BIT_CLR_P0HI8Q_HOST_IDX_8814B BIT(6)\n#define BIT_CLR_ACH13_HOST_IDX_8814B BIT(5)\n#define BIT_CLR_ACH12_HOST_IDX_8814B BIT(4)\n#define BIT_CLR_ACH11_HOST_IDX_8814B BIT(3)\n#define BIT_CLR_ACH10_HOST_IDX_8814B BIT(2)\n#define BIT_CLR_ACH9_HOST_IDX_8814B BIT(1)\n#define BIT_CLR_ACH8_HOST_IDX_8814B BIT(0)\n\n/* 2 REG_P0MGQ_RXQ_TXRXBD_NUM_8814B */\n#define BIT_SYS_32_64_V1_8814B BIT(31)\n\n#define BIT_SHIFT_P0BCNQ_DESC_MODE_8814B 29\n#define BIT_MASK_P0BCNQ_DESC_MODE_8814B 0x3\n#define BIT_P0BCNQ_DESC_MODE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0BCNQ_DESC_MODE_8814B)                               \\\n\t << BIT_SHIFT_P0BCNQ_DESC_MODE_8814B)\n#define BITS_P0BCNQ_DESC_MODE_8814B                                            \\\n\t(BIT_MASK_P0BCNQ_DESC_MODE_8814B << BIT_SHIFT_P0BCNQ_DESC_MODE_8814B)\n#define BIT_CLEAR_P0BCNQ_DESC_MODE_8814B(x)                                    \\\n\t((x) & (~BITS_P0BCNQ_DESC_MODE_8814B))\n#define BIT_GET_P0BCNQ_DESC_MODE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0BCNQ_DESC_MODE_8814B) &                           \\\n\t BIT_MASK_P0BCNQ_DESC_MODE_8814B)\n#define BIT_SET_P0BCNQ_DESC_MODE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0BCNQ_DESC_MODE_8814B(x) | BIT_P0BCNQ_DESC_MODE_8814B(v))\n\n#define BIT_PCIE_P0BCNQ_FLAG_8814B BIT(28)\n\n#define BIT_SHIFT_P0RXQ_DESC_NUM_8814B 16\n#define BIT_MASK_P0RXQ_DESC_NUM_8814B 0xfff\n#define BIT_P0RXQ_DESC_NUM_8814B(x)                                            \\\n\t(((x) & BIT_MASK_P0RXQ_DESC_NUM_8814B)                                 \\\n\t << BIT_SHIFT_P0RXQ_DESC_NUM_8814B)\n#define BITS_P0RXQ_DESC_NUM_8814B                                              \\\n\t(BIT_MASK_P0RXQ_DESC_NUM_8814B << BIT_SHIFT_P0RXQ_DESC_NUM_8814B)\n#define BIT_CLEAR_P0RXQ_DESC_NUM_8814B(x) ((x) & (~BITS_P0RXQ_DESC_NUM_8814B))\n#define BIT_GET_P0RXQ_DESC_NUM_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_P0RXQ_DESC_NUM_8814B) &                             \\\n\t BIT_MASK_P0RXQ_DESC_NUM_8814B)\n#define BIT_SET_P0RXQ_DESC_NUM_8814B(x, v)                                     \\\n\t(BIT_CLEAR_P0RXQ_DESC_NUM_8814B(x) | BIT_P0RXQ_DESC_NUM_8814B(v))\n\n#define BIT_PCIE_P0MGQ_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_P0MGQ_DESC_MODE_8814B 12\n#define BIT_MASK_P0MGQ_DESC_MODE_8814B 0x3\n#define BIT_P0MGQ_DESC_MODE_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0MGQ_DESC_MODE_8814B)                                \\\n\t << BIT_SHIFT_P0MGQ_DESC_MODE_8814B)\n#define BITS_P0MGQ_DESC_MODE_8814B                                             \\\n\t(BIT_MASK_P0MGQ_DESC_MODE_8814B << BIT_SHIFT_P0MGQ_DESC_MODE_8814B)\n#define BIT_CLEAR_P0MGQ_DESC_MODE_8814B(x) ((x) & (~BITS_P0MGQ_DESC_MODE_8814B))\n#define BIT_GET_P0MGQ_DESC_MODE_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0MGQ_DESC_MODE_8814B) &                            \\\n\t BIT_MASK_P0MGQ_DESC_MODE_8814B)\n#define BIT_SET_P0MGQ_DESC_MODE_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0MGQ_DESC_MODE_8814B(x) | BIT_P0MGQ_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0MGQ_DESC_NUM_8814B 0\n#define BIT_MASK_P0MGQ_DESC_NUM_8814B 0xfff\n#define BIT_P0MGQ_DESC_NUM_8814B(x)                                            \\\n\t(((x) & BIT_MASK_P0MGQ_DESC_NUM_8814B)                                 \\\n\t << BIT_SHIFT_P0MGQ_DESC_NUM_8814B)\n#define BITS_P0MGQ_DESC_NUM_8814B                                              \\\n\t(BIT_MASK_P0MGQ_DESC_NUM_8814B << BIT_SHIFT_P0MGQ_DESC_NUM_8814B)\n#define BIT_CLEAR_P0MGQ_DESC_NUM_8814B(x) ((x) & (~BITS_P0MGQ_DESC_NUM_8814B))\n#define BIT_GET_P0MGQ_DESC_NUM_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_P0MGQ_DESC_NUM_8814B) &                             \\\n\t BIT_MASK_P0MGQ_DESC_NUM_8814B)\n#define BIT_SET_P0MGQ_DESC_NUM_8814B(x, v)                                     \\\n\t(BIT_CLEAR_P0MGQ_DESC_NUM_8814B(x) | BIT_P0MGQ_DESC_NUM_8814B(v))\n\n/* 2 REG_CHNL_DMA_CFG_8814B */\n#define BIT_TXHCI_EN_8814B BIT(26)\n#define BIT_TXHCI_IDLE_8814B BIT(25)\n#define BIT_DMA_PRI_EN_8814B BIT(24)\n\n/* 2 REG_FWCMDQ_TXBD_NUM_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_PCIE_FWCMDQ_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_FWCMDQ_DESC_MODE_8814B 12\n#define BIT_MASK_FWCMDQ_DESC_MODE_8814B 0x3\n#define BIT_FWCMDQ_DESC_MODE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_FWCMDQ_DESC_MODE_8814B)                               \\\n\t << BIT_SHIFT_FWCMDQ_DESC_MODE_8814B)\n#define BITS_FWCMDQ_DESC_MODE_8814B                                            \\\n\t(BIT_MASK_FWCMDQ_DESC_MODE_8814B << BIT_SHIFT_FWCMDQ_DESC_MODE_8814B)\n#define BIT_CLEAR_FWCMDQ_DESC_MODE_8814B(x)                                    \\\n\t((x) & (~BITS_FWCMDQ_DESC_MODE_8814B))\n#define BIT_GET_FWCMDQ_DESC_MODE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_DESC_MODE_8814B) &                           \\\n\t BIT_MASK_FWCMDQ_DESC_MODE_8814B)\n#define BIT_SET_FWCMDQ_DESC_MODE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_FWCMDQ_DESC_MODE_8814B(x) | BIT_FWCMDQ_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_FWCMDQ_DESC_NUM_8814B 0\n#define BIT_MASK_FWCMDQ_DESC_NUM_8814B 0xfff\n#define BIT_FWCMDQ_DESC_NUM_8814B(x)                                           \\\n\t(((x) & BIT_MASK_FWCMDQ_DESC_NUM_8814B)                                \\\n\t << BIT_SHIFT_FWCMDQ_DESC_NUM_8814B)\n#define BITS_FWCMDQ_DESC_NUM_8814B                                             \\\n\t(BIT_MASK_FWCMDQ_DESC_NUM_8814B << BIT_SHIFT_FWCMDQ_DESC_NUM_8814B)\n#define BIT_CLEAR_FWCMDQ_DESC_NUM_8814B(x) ((x) & (~BITS_FWCMDQ_DESC_NUM_8814B))\n#define BIT_GET_FWCMDQ_DESC_NUM_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_DESC_NUM_8814B) &                            \\\n\t BIT_MASK_FWCMDQ_DESC_NUM_8814B)\n#define BIT_SET_FWCMDQ_DESC_NUM_8814B(x, v)                                    \\\n\t(BIT_CLEAR_FWCMDQ_DESC_NUM_8814B(x) | BIT_FWCMDQ_DESC_NUM_8814B(v))\n\n/* 2 REG_ACH0_ACH1_TXBD_NUM_8814B */\n#define BIT_PCIE_ACH1_FLAG_V1_8814B BIT(30)\n\n#define BIT_SHIFT_ACH1_DESC_MODE_V1_8814B 28\n#define BIT_MASK_ACH1_DESC_MODE_V1_8814B 0x3\n#define BIT_ACH1_DESC_MODE_V1_8814B(x)                                         \\\n\t(((x) & BIT_MASK_ACH1_DESC_MODE_V1_8814B)                              \\\n\t << BIT_SHIFT_ACH1_DESC_MODE_V1_8814B)\n#define BITS_ACH1_DESC_MODE_V1_8814B                                           \\\n\t(BIT_MASK_ACH1_DESC_MODE_V1_8814B << BIT_SHIFT_ACH1_DESC_MODE_V1_8814B)\n#define BIT_CLEAR_ACH1_DESC_MODE_V1_8814B(x)                                   \\\n\t((x) & (~BITS_ACH1_DESC_MODE_V1_8814B))\n#define BIT_GET_ACH1_DESC_MODE_V1_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_ACH1_DESC_MODE_V1_8814B) &                          \\\n\t BIT_MASK_ACH1_DESC_MODE_V1_8814B)\n#define BIT_SET_ACH1_DESC_MODE_V1_8814B(x, v)                                  \\\n\t(BIT_CLEAR_ACH1_DESC_MODE_V1_8814B(x) | BIT_ACH1_DESC_MODE_V1_8814B(v))\n\n#define BIT_SHIFT_ACH1_DESC_NUM_V1_8814B 16\n#define BIT_MASK_ACH1_DESC_NUM_V1_8814B 0xfff\n#define BIT_ACH1_DESC_NUM_V1_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH1_DESC_NUM_V1_8814B)                               \\\n\t << BIT_SHIFT_ACH1_DESC_NUM_V1_8814B)\n#define BITS_ACH1_DESC_NUM_V1_8814B                                            \\\n\t(BIT_MASK_ACH1_DESC_NUM_V1_8814B << BIT_SHIFT_ACH1_DESC_NUM_V1_8814B)\n#define BIT_CLEAR_ACH1_DESC_NUM_V1_8814B(x)                                    \\\n\t((x) & (~BITS_ACH1_DESC_NUM_V1_8814B))\n#define BIT_GET_ACH1_DESC_NUM_V1_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH1_DESC_NUM_V1_8814B) &                           \\\n\t BIT_MASK_ACH1_DESC_NUM_V1_8814B)\n#define BIT_SET_ACH1_DESC_NUM_V1_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH1_DESC_NUM_V1_8814B(x) | BIT_ACH1_DESC_NUM_V1_8814B(v))\n\n#define BIT_PCIE_ACH0_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_ACH0_DESC_MODE_8814B 12\n#define BIT_MASK_ACH0_DESC_MODE_8814B 0x3\n#define BIT_ACH0_DESC_MODE_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACH0_DESC_MODE_8814B)                                 \\\n\t << BIT_SHIFT_ACH0_DESC_MODE_8814B)\n#define BITS_ACH0_DESC_MODE_8814B                                              \\\n\t(BIT_MASK_ACH0_DESC_MODE_8814B << BIT_SHIFT_ACH0_DESC_MODE_8814B)\n#define BIT_CLEAR_ACH0_DESC_MODE_8814B(x) ((x) & (~BITS_ACH0_DESC_MODE_8814B))\n#define BIT_GET_ACH0_DESC_MODE_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACH0_DESC_MODE_8814B) &                             \\\n\t BIT_MASK_ACH0_DESC_MODE_8814B)\n#define BIT_SET_ACH0_DESC_MODE_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACH0_DESC_MODE_8814B(x) | BIT_ACH0_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_ACH0_DESC_NUM_8814B 0\n#define BIT_MASK_ACH0_DESC_NUM_8814B 0xfff\n#define BIT_ACH0_DESC_NUM_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH0_DESC_NUM_8814B) << BIT_SHIFT_ACH0_DESC_NUM_8814B)\n#define BITS_ACH0_DESC_NUM_8814B                                               \\\n\t(BIT_MASK_ACH0_DESC_NUM_8814B << BIT_SHIFT_ACH0_DESC_NUM_8814B)\n#define BIT_CLEAR_ACH0_DESC_NUM_8814B(x) ((x) & (~BITS_ACH0_DESC_NUM_8814B))\n#define BIT_GET_ACH0_DESC_NUM_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH0_DESC_NUM_8814B) & BIT_MASK_ACH0_DESC_NUM_8814B)\n#define BIT_SET_ACH0_DESC_NUM_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH0_DESC_NUM_8814B(x) | BIT_ACH0_DESC_NUM_8814B(v))\n\n/* 2 REG_ACH2_ACH3_TXBD_NUM_8814B */\n#define BIT_PCIE_ACH3_FLAG_V1_8814B BIT(30)\n\n#define BIT_SHIFT_ACH3_DESC_MODE_V1_8814B 28\n#define BIT_MASK_ACH3_DESC_MODE_V1_8814B 0x3\n#define BIT_ACH3_DESC_MODE_V1_8814B(x)                                         \\\n\t(((x) & BIT_MASK_ACH3_DESC_MODE_V1_8814B)                              \\\n\t << BIT_SHIFT_ACH3_DESC_MODE_V1_8814B)\n#define BITS_ACH3_DESC_MODE_V1_8814B                                           \\\n\t(BIT_MASK_ACH3_DESC_MODE_V1_8814B << BIT_SHIFT_ACH3_DESC_MODE_V1_8814B)\n#define BIT_CLEAR_ACH3_DESC_MODE_V1_8814B(x)                                   \\\n\t((x) & (~BITS_ACH3_DESC_MODE_V1_8814B))\n#define BIT_GET_ACH3_DESC_MODE_V1_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_ACH3_DESC_MODE_V1_8814B) &                          \\\n\t BIT_MASK_ACH3_DESC_MODE_V1_8814B)\n#define BIT_SET_ACH3_DESC_MODE_V1_8814B(x, v)                                  \\\n\t(BIT_CLEAR_ACH3_DESC_MODE_V1_8814B(x) | BIT_ACH3_DESC_MODE_V1_8814B(v))\n\n#define BIT_SHIFT_ACH3_DESC_NUM_V1_8814B 16\n#define BIT_MASK_ACH3_DESC_NUM_V1_8814B 0xfff\n#define BIT_ACH3_DESC_NUM_V1_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH3_DESC_NUM_V1_8814B)                               \\\n\t << BIT_SHIFT_ACH3_DESC_NUM_V1_8814B)\n#define BITS_ACH3_DESC_NUM_V1_8814B                                            \\\n\t(BIT_MASK_ACH3_DESC_NUM_V1_8814B << BIT_SHIFT_ACH3_DESC_NUM_V1_8814B)\n#define BIT_CLEAR_ACH3_DESC_NUM_V1_8814B(x)                                    \\\n\t((x) & (~BITS_ACH3_DESC_NUM_V1_8814B))\n#define BIT_GET_ACH3_DESC_NUM_V1_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH3_DESC_NUM_V1_8814B) &                           \\\n\t BIT_MASK_ACH3_DESC_NUM_V1_8814B)\n#define BIT_SET_ACH3_DESC_NUM_V1_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH3_DESC_NUM_V1_8814B(x) | BIT_ACH3_DESC_NUM_V1_8814B(v))\n\n#define BIT_PCIE_ACH2_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_ACH2_DESC_MODE_8814B 12\n#define BIT_MASK_ACH2_DESC_MODE_8814B 0x3\n#define BIT_ACH2_DESC_MODE_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACH2_DESC_MODE_8814B)                                 \\\n\t << BIT_SHIFT_ACH2_DESC_MODE_8814B)\n#define BITS_ACH2_DESC_MODE_8814B                                              \\\n\t(BIT_MASK_ACH2_DESC_MODE_8814B << BIT_SHIFT_ACH2_DESC_MODE_8814B)\n#define BIT_CLEAR_ACH2_DESC_MODE_8814B(x) ((x) & (~BITS_ACH2_DESC_MODE_8814B))\n#define BIT_GET_ACH2_DESC_MODE_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACH2_DESC_MODE_8814B) &                             \\\n\t BIT_MASK_ACH2_DESC_MODE_8814B)\n#define BIT_SET_ACH2_DESC_MODE_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACH2_DESC_MODE_8814B(x) | BIT_ACH2_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_ACH2_DESC_NUM_8814B 0\n#define BIT_MASK_ACH2_DESC_NUM_8814B 0xfff\n#define BIT_ACH2_DESC_NUM_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH2_DESC_NUM_8814B) << BIT_SHIFT_ACH2_DESC_NUM_8814B)\n#define BITS_ACH2_DESC_NUM_8814B                                               \\\n\t(BIT_MASK_ACH2_DESC_NUM_8814B << BIT_SHIFT_ACH2_DESC_NUM_8814B)\n#define BIT_CLEAR_ACH2_DESC_NUM_8814B(x) ((x) & (~BITS_ACH2_DESC_NUM_8814B))\n#define BIT_GET_ACH2_DESC_NUM_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH2_DESC_NUM_8814B) & BIT_MASK_ACH2_DESC_NUM_8814B)\n#define BIT_SET_ACH2_DESC_NUM_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH2_DESC_NUM_8814B(x) | BIT_ACH2_DESC_NUM_8814B(v))\n\n/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM_8814B */\n#define BIT_P0HI1Q_FLAG_8814B BIT(30)\n\n#define BIT_SHIFT_P0HI1Q_DESC_MODE_8814B 28\n#define BIT_MASK_P0HI1Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI1Q_DESC_MODE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI1Q_DESC_MODE_8814B)                               \\\n\t << BIT_SHIFT_P0HI1Q_DESC_MODE_8814B)\n#define BITS_P0HI1Q_DESC_MODE_8814B                                            \\\n\t(BIT_MASK_P0HI1Q_DESC_MODE_8814B << BIT_SHIFT_P0HI1Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI1Q_DESC_MODE_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI1Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI1Q_DESC_MODE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI1Q_DESC_MODE_8814B) &                           \\\n\t BIT_MASK_P0HI1Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI1Q_DESC_MODE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI1Q_DESC_MODE_8814B(x) | BIT_P0HI1Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI1Q_DESC_NUM_8814B 16\n#define BIT_MASK_P0HI1Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI1Q_DESC_NUM_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI1Q_DESC_NUM_8814B)                                \\\n\t << BIT_SHIFT_P0HI1Q_DESC_NUM_8814B)\n#define BITS_P0HI1Q_DESC_NUM_8814B                                             \\\n\t(BIT_MASK_P0HI1Q_DESC_NUM_8814B << BIT_SHIFT_P0HI1Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI1Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI1Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI1Q_DESC_NUM_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI1Q_DESC_NUM_8814B) &                            \\\n\t BIT_MASK_P0HI1Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI1Q_DESC_NUM_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI1Q_DESC_NUM_8814B(x) | BIT_P0HI1Q_DESC_NUM_8814B(v))\n\n#define BIT_P0HI0Q_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_P0HI0Q_DESC_MODE_8814B 12\n#define BIT_MASK_P0HI0Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI0Q_DESC_MODE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI0Q_DESC_MODE_8814B)                               \\\n\t << BIT_SHIFT_P0HI0Q_DESC_MODE_8814B)\n#define BITS_P0HI0Q_DESC_MODE_8814B                                            \\\n\t(BIT_MASK_P0HI0Q_DESC_MODE_8814B << BIT_SHIFT_P0HI0Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI0Q_DESC_MODE_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI0Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI0Q_DESC_MODE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI0Q_DESC_MODE_8814B) &                           \\\n\t BIT_MASK_P0HI0Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI0Q_DESC_MODE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI0Q_DESC_MODE_8814B(x) | BIT_P0HI0Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI0Q_DESC_NUM_8814B 0\n#define BIT_MASK_P0HI0Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI0Q_DESC_NUM_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI0Q_DESC_NUM_8814B)                                \\\n\t << BIT_SHIFT_P0HI0Q_DESC_NUM_8814B)\n#define BITS_P0HI0Q_DESC_NUM_8814B                                             \\\n\t(BIT_MASK_P0HI0Q_DESC_NUM_8814B << BIT_SHIFT_P0HI0Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI0Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI0Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI0Q_DESC_NUM_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI0Q_DESC_NUM_8814B) &                            \\\n\t BIT_MASK_P0HI0Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI0Q_DESC_NUM_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI0Q_DESC_NUM_8814B(x) | BIT_P0HI0Q_DESC_NUM_8814B(v))\n\n/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM_8814B */\n#define BIT_P0HI3Q_FLAG_8814B BIT(30)\n\n#define BIT_SHIFT_P0HI3Q_DESC_MODE_8814B 28\n#define BIT_MASK_P0HI3Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI3Q_DESC_MODE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI3Q_DESC_MODE_8814B)                               \\\n\t << BIT_SHIFT_P0HI3Q_DESC_MODE_8814B)\n#define BITS_P0HI3Q_DESC_MODE_8814B                                            \\\n\t(BIT_MASK_P0HI3Q_DESC_MODE_8814B << BIT_SHIFT_P0HI3Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI3Q_DESC_MODE_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI3Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI3Q_DESC_MODE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI3Q_DESC_MODE_8814B) &                           \\\n\t BIT_MASK_P0HI3Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI3Q_DESC_MODE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI3Q_DESC_MODE_8814B(x) | BIT_P0HI3Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI3Q_DESC_NUM_8814B 16\n#define BIT_MASK_P0HI3Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI3Q_DESC_NUM_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI3Q_DESC_NUM_8814B)                                \\\n\t << BIT_SHIFT_P0HI3Q_DESC_NUM_8814B)\n#define BITS_P0HI3Q_DESC_NUM_8814B                                             \\\n\t(BIT_MASK_P0HI3Q_DESC_NUM_8814B << BIT_SHIFT_P0HI3Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI3Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI3Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI3Q_DESC_NUM_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI3Q_DESC_NUM_8814B) &                            \\\n\t BIT_MASK_P0HI3Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI3Q_DESC_NUM_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI3Q_DESC_NUM_8814B(x) | BIT_P0HI3Q_DESC_NUM_8814B(v))\n\n#define BIT_P0HI2Q_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_P0HI2Q_DESC_MODE_8814B 12\n#define BIT_MASK_P0HI2Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI2Q_DESC_MODE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI2Q_DESC_MODE_8814B)                               \\\n\t << BIT_SHIFT_P0HI2Q_DESC_MODE_8814B)\n#define BITS_P0HI2Q_DESC_MODE_8814B                                            \\\n\t(BIT_MASK_P0HI2Q_DESC_MODE_8814B << BIT_SHIFT_P0HI2Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI2Q_DESC_MODE_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI2Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI2Q_DESC_MODE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI2Q_DESC_MODE_8814B) &                           \\\n\t BIT_MASK_P0HI2Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI2Q_DESC_MODE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI2Q_DESC_MODE_8814B(x) | BIT_P0HI2Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI2Q_DESC_NUM_8814B 0\n#define BIT_MASK_P0HI2Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI2Q_DESC_NUM_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI2Q_DESC_NUM_8814B)                                \\\n\t << BIT_SHIFT_P0HI2Q_DESC_NUM_8814B)\n#define BITS_P0HI2Q_DESC_NUM_8814B                                             \\\n\t(BIT_MASK_P0HI2Q_DESC_NUM_8814B << BIT_SHIFT_P0HI2Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI2Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI2Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI2Q_DESC_NUM_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI2Q_DESC_NUM_8814B) &                            \\\n\t BIT_MASK_P0HI2Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI2Q_DESC_NUM_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI2Q_DESC_NUM_8814B(x) | BIT_P0HI2Q_DESC_NUM_8814B(v))\n\n/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM_8814B */\n#define BIT_P0HI5Q_FLAG_8814B BIT(30)\n\n#define BIT_SHIFT_P0HI5Q_DESC_MODE_8814B 28\n#define BIT_MASK_P0HI5Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI5Q_DESC_MODE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI5Q_DESC_MODE_8814B)                               \\\n\t << BIT_SHIFT_P0HI5Q_DESC_MODE_8814B)\n#define BITS_P0HI5Q_DESC_MODE_8814B                                            \\\n\t(BIT_MASK_P0HI5Q_DESC_MODE_8814B << BIT_SHIFT_P0HI5Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI5Q_DESC_MODE_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI5Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI5Q_DESC_MODE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI5Q_DESC_MODE_8814B) &                           \\\n\t BIT_MASK_P0HI5Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI5Q_DESC_MODE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI5Q_DESC_MODE_8814B(x) | BIT_P0HI5Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI5Q_DESC_NUM_8814B 16\n#define BIT_MASK_P0HI5Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI5Q_DESC_NUM_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI5Q_DESC_NUM_8814B)                                \\\n\t << BIT_SHIFT_P0HI5Q_DESC_NUM_8814B)\n#define BITS_P0HI5Q_DESC_NUM_8814B                                             \\\n\t(BIT_MASK_P0HI5Q_DESC_NUM_8814B << BIT_SHIFT_P0HI5Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI5Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI5Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI5Q_DESC_NUM_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI5Q_DESC_NUM_8814B) &                            \\\n\t BIT_MASK_P0HI5Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI5Q_DESC_NUM_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI5Q_DESC_NUM_8814B(x) | BIT_P0HI5Q_DESC_NUM_8814B(v))\n\n#define BIT_P0HI4Q_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_P0HI4Q_DESC_MODE_8814B 12\n#define BIT_MASK_P0HI4Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI4Q_DESC_MODE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI4Q_DESC_MODE_8814B)                               \\\n\t << BIT_SHIFT_P0HI4Q_DESC_MODE_8814B)\n#define BITS_P0HI4Q_DESC_MODE_8814B                                            \\\n\t(BIT_MASK_P0HI4Q_DESC_MODE_8814B << BIT_SHIFT_P0HI4Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI4Q_DESC_MODE_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI4Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI4Q_DESC_MODE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI4Q_DESC_MODE_8814B) &                           \\\n\t BIT_MASK_P0HI4Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI4Q_DESC_MODE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI4Q_DESC_MODE_8814B(x) | BIT_P0HI4Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI4Q_DESC_NUM_8814B 0\n#define BIT_MASK_P0HI4Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI4Q_DESC_NUM_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI4Q_DESC_NUM_8814B)                                \\\n\t << BIT_SHIFT_P0HI4Q_DESC_NUM_8814B)\n#define BITS_P0HI4Q_DESC_NUM_8814B                                             \\\n\t(BIT_MASK_P0HI4Q_DESC_NUM_8814B << BIT_SHIFT_P0HI4Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI4Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI4Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI4Q_DESC_NUM_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI4Q_DESC_NUM_8814B) &                            \\\n\t BIT_MASK_P0HI4Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI4Q_DESC_NUM_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI4Q_DESC_NUM_8814B(x) | BIT_P0HI4Q_DESC_NUM_8814B(v))\n\n/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM_8814B */\n#define BIT_P0HI7Q_FLAG_8814B BIT(30)\n\n#define BIT_SHIFT_P0HI7Q_DESC_MODE_8814B 28\n#define BIT_MASK_P0HI7Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI7Q_DESC_MODE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI7Q_DESC_MODE_8814B)                               \\\n\t << BIT_SHIFT_P0HI7Q_DESC_MODE_8814B)\n#define BITS_P0HI7Q_DESC_MODE_8814B                                            \\\n\t(BIT_MASK_P0HI7Q_DESC_MODE_8814B << BIT_SHIFT_P0HI7Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI7Q_DESC_MODE_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI7Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI7Q_DESC_MODE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI7Q_DESC_MODE_8814B) &                           \\\n\t BIT_MASK_P0HI7Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI7Q_DESC_MODE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI7Q_DESC_MODE_8814B(x) | BIT_P0HI7Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI7Q_DESC_NUM_8814B 16\n#define BIT_MASK_P0HI7Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI7Q_DESC_NUM_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI7Q_DESC_NUM_8814B)                                \\\n\t << BIT_SHIFT_P0HI7Q_DESC_NUM_8814B)\n#define BITS_P0HI7Q_DESC_NUM_8814B                                             \\\n\t(BIT_MASK_P0HI7Q_DESC_NUM_8814B << BIT_SHIFT_P0HI7Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI7Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI7Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI7Q_DESC_NUM_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI7Q_DESC_NUM_8814B) &                            \\\n\t BIT_MASK_P0HI7Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI7Q_DESC_NUM_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI7Q_DESC_NUM_8814B(x) | BIT_P0HI7Q_DESC_NUM_8814B(v))\n\n#define BIT_P0HI6Q_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_P0HI6Q_DESC_MODE_8814B 12\n#define BIT_MASK_P0HI6Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI6Q_DESC_MODE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI6Q_DESC_MODE_8814B)                               \\\n\t << BIT_SHIFT_P0HI6Q_DESC_MODE_8814B)\n#define BITS_P0HI6Q_DESC_MODE_8814B                                            \\\n\t(BIT_MASK_P0HI6Q_DESC_MODE_8814B << BIT_SHIFT_P0HI6Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI6Q_DESC_MODE_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI6Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI6Q_DESC_MODE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI6Q_DESC_MODE_8814B) &                           \\\n\t BIT_MASK_P0HI6Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI6Q_DESC_MODE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI6Q_DESC_MODE_8814B(x) | BIT_P0HI6Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI6Q_DESC_NUM_8814B 0\n#define BIT_MASK_P0HI6Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI6Q_DESC_NUM_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI6Q_DESC_NUM_8814B)                                \\\n\t << BIT_SHIFT_P0HI6Q_DESC_NUM_8814B)\n#define BITS_P0HI6Q_DESC_NUM_8814B                                             \\\n\t(BIT_MASK_P0HI6Q_DESC_NUM_8814B << BIT_SHIFT_P0HI6Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI6Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI6Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI6Q_DESC_NUM_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI6Q_DESC_NUM_8814B) &                            \\\n\t BIT_MASK_P0HI6Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI6Q_DESC_NUM_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI6Q_DESC_NUM_8814B(x) | BIT_P0HI6Q_DESC_NUM_8814B(v))\n\n/* 2 REG_BD_RWPTR_CLR1_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_CLR_FWCMDQ_HW_IDX_8814B BIT(30)\n#define BIT_CLR_P0HI7Q_HW_IDX_8814B BIT(29)\n#define BIT_CLR_P0HI6Q_HW_IDX_8814B BIT(28)\n#define BIT_CLR_P0HI5Q_HW_IDX_8814B BIT(27)\n#define BIT_CLR_P0HI4Q_HW_IDX_8814B BIT(26)\n#define BIT_CLR_P0HI3Q_HW_IDX_8814B BIT(25)\n#define BIT_CLR_P0HI2Q_HW_IDX_8814B BIT(24)\n#define BIT_CLR_P0HI1Q_HW_IDX_8814B BIT(23)\n#define BIT_CLR_P0HI0Q_HW_IDX_8814B BIT(22)\n#define BIT_CLR_ACH3_HW_IDX_8814B BIT(21)\n#define BIT_CLR_ACH2_HW_IDX_8814B BIT(20)\n#define BIT_CLR_ACH1_HW_IDX_8814B BIT(19)\n#define BIT_CLR_ACH0_HW_IDX_8814B BIT(18)\n#define BIT_CLR_P0MGQ_HW_IDX_8814B BIT(17)\n#define BIT_CLR_P0RXQ_HW_IDX_8814B BIT(16)\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_CLR_PFWCMDQ_HOST_IDX_8814B BIT(14)\n#define BIT_CLR_P0HI7Q_HOST_IDX_8814B BIT(13)\n#define BIT_CLR_P0HI6Q_HOST_IDX_8814B BIT(12)\n#define BIT_CLR_P0HI5Q_HOST_IDX_8814B BIT(11)\n#define BIT_CLR_P0HI4Q_HOST_IDX_8814B BIT(10)\n#define BIT_CLR_P0HI3Q_HOST_IDX_8814B BIT(9)\n#define BIT_CLR_P0HI2Q_HOST_IDX_8814B BIT(8)\n#define BIT_CLR_P0HI1Q_HOST_IDX_8814B BIT(7)\n#define BIT_CLR_P0HI0Q_HOST_IDX_8814B BIT(6)\n#define BIT_CLR_ACH3_HOST_IDX_8814B BIT(5)\n#define BIT_CLR_ACH2_HOST_IDX_8814B BIT(4)\n#define BIT_CLR_ACH1_HOST_IDX_8814B BIT(3)\n#define BIT_CLR_ACH0_HOST_IDX_8814B BIT(2)\n#define BIT_CLR_P0MGQ_HOST_IDX_8814B BIT(1)\n#define BIT_CLR_P0RXQ_HOST_IDX_8814B BIT(0)\n\n/* 2 REG_TSFTIMER_HCI_8814B */\n\n#define BIT_SHIFT_TSFT2_HCI_8814B 16\n#define BIT_MASK_TSFT2_HCI_8814B 0xffff\n#define BIT_TSFT2_HCI_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_TSFT2_HCI_8814B) << BIT_SHIFT_TSFT2_HCI_8814B)\n#define BITS_TSFT2_HCI_8814B                                                   \\\n\t(BIT_MASK_TSFT2_HCI_8814B << BIT_SHIFT_TSFT2_HCI_8814B)\n#define BIT_CLEAR_TSFT2_HCI_8814B(x) ((x) & (~BITS_TSFT2_HCI_8814B))\n#define BIT_GET_TSFT2_HCI_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_TSFT2_HCI_8814B) & BIT_MASK_TSFT2_HCI_8814B)\n#define BIT_SET_TSFT2_HCI_8814B(x, v)                                          \\\n\t(BIT_CLEAR_TSFT2_HCI_8814B(x) | BIT_TSFT2_HCI_8814B(v))\n\n#define BIT_SHIFT_TSFT1_HCI_8814B 0\n#define BIT_MASK_TSFT1_HCI_8814B 0xffff\n#define BIT_TSFT1_HCI_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_TSFT1_HCI_8814B) << BIT_SHIFT_TSFT1_HCI_8814B)\n#define BITS_TSFT1_HCI_8814B                                                   \\\n\t(BIT_MASK_TSFT1_HCI_8814B << BIT_SHIFT_TSFT1_HCI_8814B)\n#define BIT_CLEAR_TSFT1_HCI_8814B(x) ((x) & (~BITS_TSFT1_HCI_8814B))\n#define BIT_GET_TSFT1_HCI_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_TSFT1_HCI_8814B) & BIT_MASK_TSFT1_HCI_8814B)\n#define BIT_SET_TSFT1_HCI_8814B(x, v)                                          \\\n\t(BIT_CLEAR_TSFT1_HCI_8814B(x) | BIT_TSFT1_HCI_8814B(v))\n\n/* 2 REG_ACH0_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_ACH0_HW_IDX_8814B 16\n#define BIT_MASK_ACH0_HW_IDX_8814B 0xfff\n#define BIT_ACH0_HW_IDX_8814B(x)                                               \\\n\t(((x) & BIT_MASK_ACH0_HW_IDX_8814B) << BIT_SHIFT_ACH0_HW_IDX_8814B)\n#define BITS_ACH0_HW_IDX_8814B                                                 \\\n\t(BIT_MASK_ACH0_HW_IDX_8814B << BIT_SHIFT_ACH0_HW_IDX_8814B)\n#define BIT_CLEAR_ACH0_HW_IDX_8814B(x) ((x) & (~BITS_ACH0_HW_IDX_8814B))\n#define BIT_GET_ACH0_HW_IDX_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH0_HW_IDX_8814B) & BIT_MASK_ACH0_HW_IDX_8814B)\n#define BIT_SET_ACH0_HW_IDX_8814B(x, v)                                        \\\n\t(BIT_CLEAR_ACH0_HW_IDX_8814B(x) | BIT_ACH0_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_ACH0_HOST_IDX_8814B 0\n#define BIT_MASK_ACH0_HOST_IDX_8814B 0xfff\n#define BIT_ACH0_HOST_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH0_HOST_IDX_8814B) << BIT_SHIFT_ACH0_HOST_IDX_8814B)\n#define BITS_ACH0_HOST_IDX_8814B                                               \\\n\t(BIT_MASK_ACH0_HOST_IDX_8814B << BIT_SHIFT_ACH0_HOST_IDX_8814B)\n#define BIT_CLEAR_ACH0_HOST_IDX_8814B(x) ((x) & (~BITS_ACH0_HOST_IDX_8814B))\n#define BIT_GET_ACH0_HOST_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH0_HOST_IDX_8814B) & BIT_MASK_ACH0_HOST_IDX_8814B)\n#define BIT_SET_ACH0_HOST_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH0_HOST_IDX_8814B(x) | BIT_ACH0_HOST_IDX_8814B(v))\n\n/* 2 REG_ACH1_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_ACH1_HW_IDX_8814B 16\n#define BIT_MASK_ACH1_HW_IDX_8814B 0xfff\n#define BIT_ACH1_HW_IDX_8814B(x)                                               \\\n\t(((x) & BIT_MASK_ACH1_HW_IDX_8814B) << BIT_SHIFT_ACH1_HW_IDX_8814B)\n#define BITS_ACH1_HW_IDX_8814B                                                 \\\n\t(BIT_MASK_ACH1_HW_IDX_8814B << BIT_SHIFT_ACH1_HW_IDX_8814B)\n#define BIT_CLEAR_ACH1_HW_IDX_8814B(x) ((x) & (~BITS_ACH1_HW_IDX_8814B))\n#define BIT_GET_ACH1_HW_IDX_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH1_HW_IDX_8814B) & BIT_MASK_ACH1_HW_IDX_8814B)\n#define BIT_SET_ACH1_HW_IDX_8814B(x, v)                                        \\\n\t(BIT_CLEAR_ACH1_HW_IDX_8814B(x) | BIT_ACH1_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_ACH1_HOST_IDX_8814B 0\n#define BIT_MASK_ACH1_HOST_IDX_8814B 0xfff\n#define BIT_ACH1_HOST_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH1_HOST_IDX_8814B) << BIT_SHIFT_ACH1_HOST_IDX_8814B)\n#define BITS_ACH1_HOST_IDX_8814B                                               \\\n\t(BIT_MASK_ACH1_HOST_IDX_8814B << BIT_SHIFT_ACH1_HOST_IDX_8814B)\n#define BIT_CLEAR_ACH1_HOST_IDX_8814B(x) ((x) & (~BITS_ACH1_HOST_IDX_8814B))\n#define BIT_GET_ACH1_HOST_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH1_HOST_IDX_8814B) & BIT_MASK_ACH1_HOST_IDX_8814B)\n#define BIT_SET_ACH1_HOST_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH1_HOST_IDX_8814B(x) | BIT_ACH1_HOST_IDX_8814B(v))\n\n/* 2 REG_ACH2_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_ACH2_HW_IDX_8814B 16\n#define BIT_MASK_ACH2_HW_IDX_8814B 0xfff\n#define BIT_ACH2_HW_IDX_8814B(x)                                               \\\n\t(((x) & BIT_MASK_ACH2_HW_IDX_8814B) << BIT_SHIFT_ACH2_HW_IDX_8814B)\n#define BITS_ACH2_HW_IDX_8814B                                                 \\\n\t(BIT_MASK_ACH2_HW_IDX_8814B << BIT_SHIFT_ACH2_HW_IDX_8814B)\n#define BIT_CLEAR_ACH2_HW_IDX_8814B(x) ((x) & (~BITS_ACH2_HW_IDX_8814B))\n#define BIT_GET_ACH2_HW_IDX_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH2_HW_IDX_8814B) & BIT_MASK_ACH2_HW_IDX_8814B)\n#define BIT_SET_ACH2_HW_IDX_8814B(x, v)                                        \\\n\t(BIT_CLEAR_ACH2_HW_IDX_8814B(x) | BIT_ACH2_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_ACH2_HOST_IDX_8814B 0\n#define BIT_MASK_ACH2_HOST_IDX_8814B 0xfff\n#define BIT_ACH2_HOST_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH2_HOST_IDX_8814B) << BIT_SHIFT_ACH2_HOST_IDX_8814B)\n#define BITS_ACH2_HOST_IDX_8814B                                               \\\n\t(BIT_MASK_ACH2_HOST_IDX_8814B << BIT_SHIFT_ACH2_HOST_IDX_8814B)\n#define BIT_CLEAR_ACH2_HOST_IDX_8814B(x) ((x) & (~BITS_ACH2_HOST_IDX_8814B))\n#define BIT_GET_ACH2_HOST_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH2_HOST_IDX_8814B) & BIT_MASK_ACH2_HOST_IDX_8814B)\n#define BIT_SET_ACH2_HOST_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH2_HOST_IDX_8814B(x) | BIT_ACH2_HOST_IDX_8814B(v))\n\n/* 2 REG_ACH3_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_ACH3_HW_IDX_8814B 16\n#define BIT_MASK_ACH3_HW_IDX_8814B 0xfff\n#define BIT_ACH3_HW_IDX_8814B(x)                                               \\\n\t(((x) & BIT_MASK_ACH3_HW_IDX_8814B) << BIT_SHIFT_ACH3_HW_IDX_8814B)\n#define BITS_ACH3_HW_IDX_8814B                                                 \\\n\t(BIT_MASK_ACH3_HW_IDX_8814B << BIT_SHIFT_ACH3_HW_IDX_8814B)\n#define BIT_CLEAR_ACH3_HW_IDX_8814B(x) ((x) & (~BITS_ACH3_HW_IDX_8814B))\n#define BIT_GET_ACH3_HW_IDX_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH3_HW_IDX_8814B) & BIT_MASK_ACH3_HW_IDX_8814B)\n#define BIT_SET_ACH3_HW_IDX_8814B(x, v)                                        \\\n\t(BIT_CLEAR_ACH3_HW_IDX_8814B(x) | BIT_ACH3_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_ACH3_HOST_IDX_8814B 0\n#define BIT_MASK_ACH3_HOST_IDX_8814B 0xfff\n#define BIT_ACH3_HOST_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH3_HOST_IDX_8814B) << BIT_SHIFT_ACH3_HOST_IDX_8814B)\n#define BITS_ACH3_HOST_IDX_8814B                                               \\\n\t(BIT_MASK_ACH3_HOST_IDX_8814B << BIT_SHIFT_ACH3_HOST_IDX_8814B)\n#define BIT_CLEAR_ACH3_HOST_IDX_8814B(x) ((x) & (~BITS_ACH3_HOST_IDX_8814B))\n#define BIT_GET_ACH3_HOST_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH3_HOST_IDX_8814B) & BIT_MASK_ACH3_HOST_IDX_8814B)\n#define BIT_SET_ACH3_HOST_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH3_HOST_IDX_8814B(x) | BIT_ACH3_HOST_IDX_8814B(v))\n\n/* 2 REG_P0MGQ_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0MGQ_HW_IDX_8814B 16\n#define BIT_MASK_P0MGQ_HW_IDX_8814B 0xfff\n#define BIT_P0MGQ_HW_IDX_8814B(x)                                              \\\n\t(((x) & BIT_MASK_P0MGQ_HW_IDX_8814B) << BIT_SHIFT_P0MGQ_HW_IDX_8814B)\n#define BITS_P0MGQ_HW_IDX_8814B                                                \\\n\t(BIT_MASK_P0MGQ_HW_IDX_8814B << BIT_SHIFT_P0MGQ_HW_IDX_8814B)\n#define BIT_CLEAR_P0MGQ_HW_IDX_8814B(x) ((x) & (~BITS_P0MGQ_HW_IDX_8814B))\n#define BIT_GET_P0MGQ_HW_IDX_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_P0MGQ_HW_IDX_8814B) & BIT_MASK_P0MGQ_HW_IDX_8814B)\n#define BIT_SET_P0MGQ_HW_IDX_8814B(x, v)                                       \\\n\t(BIT_CLEAR_P0MGQ_HW_IDX_8814B(x) | BIT_P0MGQ_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0MGQ_HOST_IDX_8814B 0\n#define BIT_MASK_P0MGQ_HOST_IDX_8814B 0xfff\n#define BIT_P0MGQ_HOST_IDX_8814B(x)                                            \\\n\t(((x) & BIT_MASK_P0MGQ_HOST_IDX_8814B)                                 \\\n\t << BIT_SHIFT_P0MGQ_HOST_IDX_8814B)\n#define BITS_P0MGQ_HOST_IDX_8814B                                              \\\n\t(BIT_MASK_P0MGQ_HOST_IDX_8814B << BIT_SHIFT_P0MGQ_HOST_IDX_8814B)\n#define BIT_CLEAR_P0MGQ_HOST_IDX_8814B(x) ((x) & (~BITS_P0MGQ_HOST_IDX_8814B))\n#define BIT_GET_P0MGQ_HOST_IDX_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_P0MGQ_HOST_IDX_8814B) &                             \\\n\t BIT_MASK_P0MGQ_HOST_IDX_8814B)\n#define BIT_SET_P0MGQ_HOST_IDX_8814B(x, v)                                     \\\n\t(BIT_CLEAR_P0MGQ_HOST_IDX_8814B(x) | BIT_P0MGQ_HOST_IDX_8814B(v))\n\n/* 2 REG_P0RXQ_RXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0RXQ_HW_IDX_8814B 16\n#define BIT_MASK_P0RXQ_HW_IDX_8814B 0xfff\n#define BIT_P0RXQ_HW_IDX_8814B(x)                                              \\\n\t(((x) & BIT_MASK_P0RXQ_HW_IDX_8814B) << BIT_SHIFT_P0RXQ_HW_IDX_8814B)\n#define BITS_P0RXQ_HW_IDX_8814B                                                \\\n\t(BIT_MASK_P0RXQ_HW_IDX_8814B << BIT_SHIFT_P0RXQ_HW_IDX_8814B)\n#define BIT_CLEAR_P0RXQ_HW_IDX_8814B(x) ((x) & (~BITS_P0RXQ_HW_IDX_8814B))\n#define BIT_GET_P0RXQ_HW_IDX_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_P0RXQ_HW_IDX_8814B) & BIT_MASK_P0RXQ_HW_IDX_8814B)\n#define BIT_SET_P0RXQ_HW_IDX_8814B(x, v)                                       \\\n\t(BIT_CLEAR_P0RXQ_HW_IDX_8814B(x) | BIT_P0RXQ_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0RXQ_HOST_IDX_8814B 0\n#define BIT_MASK_P0RXQ_HOST_IDX_8814B 0xfff\n#define BIT_P0RXQ_HOST_IDX_8814B(x)                                            \\\n\t(((x) & BIT_MASK_P0RXQ_HOST_IDX_8814B)                                 \\\n\t << BIT_SHIFT_P0RXQ_HOST_IDX_8814B)\n#define BITS_P0RXQ_HOST_IDX_8814B                                              \\\n\t(BIT_MASK_P0RXQ_HOST_IDX_8814B << BIT_SHIFT_P0RXQ_HOST_IDX_8814B)\n#define BIT_CLEAR_P0RXQ_HOST_IDX_8814B(x) ((x) & (~BITS_P0RXQ_HOST_IDX_8814B))\n#define BIT_GET_P0RXQ_HOST_IDX_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_P0RXQ_HOST_IDX_8814B) &                             \\\n\t BIT_MASK_P0RXQ_HOST_IDX_8814B)\n#define BIT_SET_P0RXQ_HOST_IDX_8814B(x, v)                                     \\\n\t(BIT_CLEAR_P0RXQ_HOST_IDX_8814B(x) | BIT_P0RXQ_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI0Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI0Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI0Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI0Q_HW_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_P0HI0Q_HW_IDX_8814B) << BIT_SHIFT_P0HI0Q_HW_IDX_8814B)\n#define BITS_P0HI0Q_HW_IDX_8814B                                               \\\n\t(BIT_MASK_P0HI0Q_HW_IDX_8814B << BIT_SHIFT_P0HI0Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI0Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI0Q_HW_IDX_8814B))\n#define BIT_GET_P0HI0Q_HW_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_P0HI0Q_HW_IDX_8814B) & BIT_MASK_P0HI0Q_HW_IDX_8814B)\n#define BIT_SET_P0HI0Q_HW_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_P0HI0Q_HW_IDX_8814B(x) | BIT_P0HI0Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI0Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI0Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI0Q_HOST_IDX_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI0Q_HOST_IDX_8814B)                                \\\n\t << BIT_SHIFT_P0HI0Q_HOST_IDX_8814B)\n#define BITS_P0HI0Q_HOST_IDX_8814B                                             \\\n\t(BIT_MASK_P0HI0Q_HOST_IDX_8814B << BIT_SHIFT_P0HI0Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI0Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI0Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI0Q_HOST_IDX_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI0Q_HOST_IDX_8814B) &                            \\\n\t BIT_MASK_P0HI0Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI0Q_HOST_IDX_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI0Q_HOST_IDX_8814B(x) | BIT_P0HI0Q_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI1Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI1Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI1Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI1Q_HW_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_P0HI1Q_HW_IDX_8814B) << BIT_SHIFT_P0HI1Q_HW_IDX_8814B)\n#define BITS_P0HI1Q_HW_IDX_8814B                                               \\\n\t(BIT_MASK_P0HI1Q_HW_IDX_8814B << BIT_SHIFT_P0HI1Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI1Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI1Q_HW_IDX_8814B))\n#define BIT_GET_P0HI1Q_HW_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_P0HI1Q_HW_IDX_8814B) & BIT_MASK_P0HI1Q_HW_IDX_8814B)\n#define BIT_SET_P0HI1Q_HW_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_P0HI1Q_HW_IDX_8814B(x) | BIT_P0HI1Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI1Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI1Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI1Q_HOST_IDX_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI1Q_HOST_IDX_8814B)                                \\\n\t << BIT_SHIFT_P0HI1Q_HOST_IDX_8814B)\n#define BITS_P0HI1Q_HOST_IDX_8814B                                             \\\n\t(BIT_MASK_P0HI1Q_HOST_IDX_8814B << BIT_SHIFT_P0HI1Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI1Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI1Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI1Q_HOST_IDX_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI1Q_HOST_IDX_8814B) &                            \\\n\t BIT_MASK_P0HI1Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI1Q_HOST_IDX_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI1Q_HOST_IDX_8814B(x) | BIT_P0HI1Q_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI2Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI2Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI2Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI2Q_HW_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_P0HI2Q_HW_IDX_8814B) << BIT_SHIFT_P0HI2Q_HW_IDX_8814B)\n#define BITS_P0HI2Q_HW_IDX_8814B                                               \\\n\t(BIT_MASK_P0HI2Q_HW_IDX_8814B << BIT_SHIFT_P0HI2Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI2Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI2Q_HW_IDX_8814B))\n#define BIT_GET_P0HI2Q_HW_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_P0HI2Q_HW_IDX_8814B) & BIT_MASK_P0HI2Q_HW_IDX_8814B)\n#define BIT_SET_P0HI2Q_HW_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_P0HI2Q_HW_IDX_8814B(x) | BIT_P0HI2Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI2Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI2Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI2Q_HOST_IDX_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI2Q_HOST_IDX_8814B)                                \\\n\t << BIT_SHIFT_P0HI2Q_HOST_IDX_8814B)\n#define BITS_P0HI2Q_HOST_IDX_8814B                                             \\\n\t(BIT_MASK_P0HI2Q_HOST_IDX_8814B << BIT_SHIFT_P0HI2Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI2Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI2Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI2Q_HOST_IDX_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI2Q_HOST_IDX_8814B) &                            \\\n\t BIT_MASK_P0HI2Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI2Q_HOST_IDX_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI2Q_HOST_IDX_8814B(x) | BIT_P0HI2Q_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI3Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI3Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI3Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI3Q_HW_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_P0HI3Q_HW_IDX_8814B) << BIT_SHIFT_P0HI3Q_HW_IDX_8814B)\n#define BITS_P0HI3Q_HW_IDX_8814B                                               \\\n\t(BIT_MASK_P0HI3Q_HW_IDX_8814B << BIT_SHIFT_P0HI3Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI3Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI3Q_HW_IDX_8814B))\n#define BIT_GET_P0HI3Q_HW_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_P0HI3Q_HW_IDX_8814B) & BIT_MASK_P0HI3Q_HW_IDX_8814B)\n#define BIT_SET_P0HI3Q_HW_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_P0HI3Q_HW_IDX_8814B(x) | BIT_P0HI3Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI3Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI3Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI3Q_HOST_IDX_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI3Q_HOST_IDX_8814B)                                \\\n\t << BIT_SHIFT_P0HI3Q_HOST_IDX_8814B)\n#define BITS_P0HI3Q_HOST_IDX_8814B                                             \\\n\t(BIT_MASK_P0HI3Q_HOST_IDX_8814B << BIT_SHIFT_P0HI3Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI3Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI3Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI3Q_HOST_IDX_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI3Q_HOST_IDX_8814B) &                            \\\n\t BIT_MASK_P0HI3Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI3Q_HOST_IDX_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI3Q_HOST_IDX_8814B(x) | BIT_P0HI3Q_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI4Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI4Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI4Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI4Q_HW_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_P0HI4Q_HW_IDX_8814B) << BIT_SHIFT_P0HI4Q_HW_IDX_8814B)\n#define BITS_P0HI4Q_HW_IDX_8814B                                               \\\n\t(BIT_MASK_P0HI4Q_HW_IDX_8814B << BIT_SHIFT_P0HI4Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI4Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI4Q_HW_IDX_8814B))\n#define BIT_GET_P0HI4Q_HW_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_P0HI4Q_HW_IDX_8814B) & BIT_MASK_P0HI4Q_HW_IDX_8814B)\n#define BIT_SET_P0HI4Q_HW_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_P0HI4Q_HW_IDX_8814B(x) | BIT_P0HI4Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI4Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI4Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI4Q_HOST_IDX_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI4Q_HOST_IDX_8814B)                                \\\n\t << BIT_SHIFT_P0HI4Q_HOST_IDX_8814B)\n#define BITS_P0HI4Q_HOST_IDX_8814B                                             \\\n\t(BIT_MASK_P0HI4Q_HOST_IDX_8814B << BIT_SHIFT_P0HI4Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI4Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI4Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI4Q_HOST_IDX_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI4Q_HOST_IDX_8814B) &                            \\\n\t BIT_MASK_P0HI4Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI4Q_HOST_IDX_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI4Q_HOST_IDX_8814B(x) | BIT_P0HI4Q_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI5Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI5Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI5Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI5Q_HW_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_P0HI5Q_HW_IDX_8814B) << BIT_SHIFT_P0HI5Q_HW_IDX_8814B)\n#define BITS_P0HI5Q_HW_IDX_8814B                                               \\\n\t(BIT_MASK_P0HI5Q_HW_IDX_8814B << BIT_SHIFT_P0HI5Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI5Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI5Q_HW_IDX_8814B))\n#define BIT_GET_P0HI5Q_HW_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_P0HI5Q_HW_IDX_8814B) & BIT_MASK_P0HI5Q_HW_IDX_8814B)\n#define BIT_SET_P0HI5Q_HW_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_P0HI5Q_HW_IDX_8814B(x) | BIT_P0HI5Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI5Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI5Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI5Q_HOST_IDX_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI5Q_HOST_IDX_8814B)                                \\\n\t << BIT_SHIFT_P0HI5Q_HOST_IDX_8814B)\n#define BITS_P0HI5Q_HOST_IDX_8814B                                             \\\n\t(BIT_MASK_P0HI5Q_HOST_IDX_8814B << BIT_SHIFT_P0HI5Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI5Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI5Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI5Q_HOST_IDX_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI5Q_HOST_IDX_8814B) &                            \\\n\t BIT_MASK_P0HI5Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI5Q_HOST_IDX_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI5Q_HOST_IDX_8814B(x) | BIT_P0HI5Q_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI6Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI6Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI6Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI6Q_HW_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_P0HI6Q_HW_IDX_8814B) << BIT_SHIFT_P0HI6Q_HW_IDX_8814B)\n#define BITS_P0HI6Q_HW_IDX_8814B                                               \\\n\t(BIT_MASK_P0HI6Q_HW_IDX_8814B << BIT_SHIFT_P0HI6Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI6Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI6Q_HW_IDX_8814B))\n#define BIT_GET_P0HI6Q_HW_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_P0HI6Q_HW_IDX_8814B) & BIT_MASK_P0HI6Q_HW_IDX_8814B)\n#define BIT_SET_P0HI6Q_HW_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_P0HI6Q_HW_IDX_8814B(x) | BIT_P0HI6Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI6Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI6Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI6Q_HOST_IDX_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI6Q_HOST_IDX_8814B)                                \\\n\t << BIT_SHIFT_P0HI6Q_HOST_IDX_8814B)\n#define BITS_P0HI6Q_HOST_IDX_8814B                                             \\\n\t(BIT_MASK_P0HI6Q_HOST_IDX_8814B << BIT_SHIFT_P0HI6Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI6Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI6Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI6Q_HOST_IDX_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI6Q_HOST_IDX_8814B) &                            \\\n\t BIT_MASK_P0HI6Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI6Q_HOST_IDX_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI6Q_HOST_IDX_8814B(x) | BIT_P0HI6Q_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI7Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI7Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI7Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI7Q_HW_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_P0HI7Q_HW_IDX_8814B) << BIT_SHIFT_P0HI7Q_HW_IDX_8814B)\n#define BITS_P0HI7Q_HW_IDX_8814B                                               \\\n\t(BIT_MASK_P0HI7Q_HW_IDX_8814B << BIT_SHIFT_P0HI7Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI7Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI7Q_HW_IDX_8814B))\n#define BIT_GET_P0HI7Q_HW_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_P0HI7Q_HW_IDX_8814B) & BIT_MASK_P0HI7Q_HW_IDX_8814B)\n#define BIT_SET_P0HI7Q_HW_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_P0HI7Q_HW_IDX_8814B(x) | BIT_P0HI7Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI7Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI7Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI7Q_HOST_IDX_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI7Q_HOST_IDX_8814B)                                \\\n\t << BIT_SHIFT_P0HI7Q_HOST_IDX_8814B)\n#define BITS_P0HI7Q_HOST_IDX_8814B                                             \\\n\t(BIT_MASK_P0HI7Q_HOST_IDX_8814B << BIT_SHIFT_P0HI7Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI7Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI7Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI7Q_HOST_IDX_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI7Q_HOST_IDX_8814B) &                            \\\n\t BIT_MASK_P0HI7Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI7Q_HOST_IDX_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI7Q_HOST_IDX_8814B(x) | BIT_P0HI7Q_HOST_IDX_8814B(v))\n\n/* 2 REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1_8814B */\n#define BIT_DIS_TXDMA_PRE_V1_8814B BIT(31)\n#define BIT_DIS_RXDMA_PRE_V1_8814B BIT(30)\n\n#define BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B 28\n#define BIT_MASK_HPS_CLKR_PCIE_V1_8814B 0x3\n#define BIT_HPS_CLKR_PCIE_V1_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HPS_CLKR_PCIE_V1_8814B)                               \\\n\t << BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B)\n#define BITS_HPS_CLKR_PCIE_V1_8814B                                            \\\n\t(BIT_MASK_HPS_CLKR_PCIE_V1_8814B << BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B)\n#define BIT_CLEAR_HPS_CLKR_PCIE_V1_8814B(x)                                    \\\n\t((x) & (~BITS_HPS_CLKR_PCIE_V1_8814B))\n#define BIT_GET_HPS_CLKR_PCIE_V1_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B) &                           \\\n\t BIT_MASK_HPS_CLKR_PCIE_V1_8814B)\n#define BIT_SET_HPS_CLKR_PCIE_V1_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HPS_CLKR_PCIE_V1_8814B(x) | BIT_HPS_CLKR_PCIE_V1_8814B(v))\n\n#define BIT_PCIE_INT_V1_8814B BIT(27)\n#define BIT_TXFLAG_EXIT_L1_EN_V1_8814B BIT(26)\n#define BIT_EN_RXDMA_ALIGN_V2_8814B BIT(25)\n#define BIT_EN_TXDMA_ALIGN_V2_8814B BIT(24)\n\n#define BIT_SHIFT_PCIE_HCPWM_V1_8814B 16\n#define BIT_MASK_PCIE_HCPWM_V1_8814B 0xff\n#define BIT_PCIE_HCPWM_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_PCIE_HCPWM_V1_8814B) << BIT_SHIFT_PCIE_HCPWM_V1_8814B)\n#define BITS_PCIE_HCPWM_V1_8814B                                               \\\n\t(BIT_MASK_PCIE_HCPWM_V1_8814B << BIT_SHIFT_PCIE_HCPWM_V1_8814B)\n#define BIT_CLEAR_PCIE_HCPWM_V1_8814B(x) ((x) & (~BITS_PCIE_HCPWM_V1_8814B))\n#define BIT_GET_PCIE_HCPWM_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PCIE_HCPWM_V1_8814B) & BIT_MASK_PCIE_HCPWM_V1_8814B)\n#define BIT_SET_PCIE_HCPWM_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_PCIE_HCPWM_V1_8814B(x) | BIT_PCIE_HCPWM_V1_8814B(v))\n\n#define BIT_SHIFT_PCIE_HRPWM_V1_8814B 8\n#define BIT_MASK_PCIE_HRPWM_V1_8814B 0xff\n#define BIT_PCIE_HRPWM_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_PCIE_HRPWM_V1_8814B) << BIT_SHIFT_PCIE_HRPWM_V1_8814B)\n#define BITS_PCIE_HRPWM_V1_8814B                                               \\\n\t(BIT_MASK_PCIE_HRPWM_V1_8814B << BIT_SHIFT_PCIE_HRPWM_V1_8814B)\n#define BIT_CLEAR_PCIE_HRPWM_V1_8814B(x) ((x) & (~BITS_PCIE_HRPWM_V1_8814B))\n#define BIT_GET_PCIE_HRPWM_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PCIE_HRPWM_V1_8814B) & BIT_MASK_PCIE_HRPWM_V1_8814B)\n#define BIT_SET_PCIE_HRPWM_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_PCIE_HRPWM_V1_8814B(x) | BIT_PCIE_HRPWM_V1_8814B(v))\n\n#define BIT_SHIFT_DBG_SEL_8814B 0\n#define BIT_MASK_DBG_SEL_8814B 0xff\n#define BIT_DBG_SEL_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_DBG_SEL_8814B) << BIT_SHIFT_DBG_SEL_8814B)\n#define BITS_DBG_SEL_8814B (BIT_MASK_DBG_SEL_8814B << BIT_SHIFT_DBG_SEL_8814B)\n#define BIT_CLEAR_DBG_SEL_8814B(x) ((x) & (~BITS_DBG_SEL_8814B))\n#define BIT_GET_DBG_SEL_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_DBG_SEL_8814B) & BIT_MASK_DBG_SEL_8814B)\n#define BIT_SET_DBG_SEL_8814B(x, v)                                            \\\n\t(BIT_CLEAR_DBG_SEL_8814B(x) | BIT_DBG_SEL_8814B(v))\n\n/* 2 REG_PCIE_HRPWM2_HCPWM2_V1_8814B */\n\n#define BIT_SHIFT_PCIE_HCPWM2_V1_8814B 16\n#define BIT_MASK_PCIE_HCPWM2_V1_8814B 0xffff\n#define BIT_PCIE_HCPWM2_V1_8814B(x)                                            \\\n\t(((x) & BIT_MASK_PCIE_HCPWM2_V1_8814B)                                 \\\n\t << BIT_SHIFT_PCIE_HCPWM2_V1_8814B)\n#define BITS_PCIE_HCPWM2_V1_8814B                                              \\\n\t(BIT_MASK_PCIE_HCPWM2_V1_8814B << BIT_SHIFT_PCIE_HCPWM2_V1_8814B)\n#define BIT_CLEAR_PCIE_HCPWM2_V1_8814B(x) ((x) & (~BITS_PCIE_HCPWM2_V1_8814B))\n#define BIT_GET_PCIE_HCPWM2_V1_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_PCIE_HCPWM2_V1_8814B) &                             \\\n\t BIT_MASK_PCIE_HCPWM2_V1_8814B)\n#define BIT_SET_PCIE_HCPWM2_V1_8814B(x, v)                                     \\\n\t(BIT_CLEAR_PCIE_HCPWM2_V1_8814B(x) | BIT_PCIE_HCPWM2_V1_8814B(v))\n\n#define BIT_SHIFT_PCIE_HRPWM2_8814B 0\n#define BIT_MASK_PCIE_HRPWM2_8814B 0xffff\n#define BIT_PCIE_HRPWM2_8814B(x)                                               \\\n\t(((x) & BIT_MASK_PCIE_HRPWM2_8814B) << BIT_SHIFT_PCIE_HRPWM2_8814B)\n#define BITS_PCIE_HRPWM2_8814B                                                 \\\n\t(BIT_MASK_PCIE_HRPWM2_8814B << BIT_SHIFT_PCIE_HRPWM2_8814B)\n#define BIT_CLEAR_PCIE_HRPWM2_8814B(x) ((x) & (~BITS_PCIE_HRPWM2_8814B))\n#define BIT_GET_PCIE_HRPWM2_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_PCIE_HRPWM2_8814B) & BIT_MASK_PCIE_HRPWM2_8814B)\n#define BIT_SET_PCIE_HRPWM2_8814B(x, v)                                        \\\n\t(BIT_CLEAR_PCIE_HRPWM2_8814B(x) | BIT_PCIE_HRPWM2_8814B(v))\n\n/* 2 REG_PCIE_H2C_MSG_V1_8814B */\n\n#define BIT_SHIFT_DRV2FW_INFO_8814B 0\n#define BIT_MASK_DRV2FW_INFO_8814B 0xffffffffL\n#define BIT_DRV2FW_INFO_8814B(x)                                               \\\n\t(((x) & BIT_MASK_DRV2FW_INFO_8814B) << BIT_SHIFT_DRV2FW_INFO_8814B)\n#define BITS_DRV2FW_INFO_8814B                                                 \\\n\t(BIT_MASK_DRV2FW_INFO_8814B << BIT_SHIFT_DRV2FW_INFO_8814B)\n#define BIT_CLEAR_DRV2FW_INFO_8814B(x) ((x) & (~BITS_DRV2FW_INFO_8814B))\n#define BIT_GET_DRV2FW_INFO_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_DRV2FW_INFO_8814B) & BIT_MASK_DRV2FW_INFO_8814B)\n#define BIT_SET_DRV2FW_INFO_8814B(x, v)                                        \\\n\t(BIT_CLEAR_DRV2FW_INFO_8814B(x) | BIT_DRV2FW_INFO_8814B(v))\n\n/* 2 REG_PCIE_C2H_MSG_V1_8814B */\n\n#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B 0\n#define BIT_MASK_HCI_PCIE_C2H_MSG_8814B 0xffffffffL\n#define BIT_HCI_PCIE_C2H_MSG_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8814B)                               \\\n\t << BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B)\n#define BITS_HCI_PCIE_C2H_MSG_8814B                                            \\\n\t(BIT_MASK_HCI_PCIE_C2H_MSG_8814B << BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B)\n#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8814B(x)                                    \\\n\t((x) & (~BITS_HCI_PCIE_C2H_MSG_8814B))\n#define BIT_GET_HCI_PCIE_C2H_MSG_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B) &                           \\\n\t BIT_MASK_HCI_PCIE_C2H_MSG_8814B)\n#define BIT_SET_HCI_PCIE_C2H_MSG_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HCI_PCIE_C2H_MSG_8814B(x) | BIT_HCI_PCIE_C2H_MSG_8814B(v))\n\n/* 2 REG_DBI_WDATA_V1_8814B */\n\n#define BIT_SHIFT_DBI_WDATA_8814B 0\n#define BIT_MASK_DBI_WDATA_8814B 0xffffffffL\n#define BIT_DBI_WDATA_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_DBI_WDATA_8814B) << BIT_SHIFT_DBI_WDATA_8814B)\n#define BITS_DBI_WDATA_8814B                                                   \\\n\t(BIT_MASK_DBI_WDATA_8814B << BIT_SHIFT_DBI_WDATA_8814B)\n#define BIT_CLEAR_DBI_WDATA_8814B(x) ((x) & (~BITS_DBI_WDATA_8814B))\n#define BIT_GET_DBI_WDATA_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBI_WDATA_8814B) & BIT_MASK_DBI_WDATA_8814B)\n#define BIT_SET_DBI_WDATA_8814B(x, v)                                          \\\n\t(BIT_CLEAR_DBI_WDATA_8814B(x) | BIT_DBI_WDATA_8814B(v))\n\n/* 2 REG_DBI_RDATA_V1_8814B */\n\n#define BIT_SHIFT_DBI_RDATA_8814B 0\n#define BIT_MASK_DBI_RDATA_8814B 0xffffffffL\n#define BIT_DBI_RDATA_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_DBI_RDATA_8814B) << BIT_SHIFT_DBI_RDATA_8814B)\n#define BITS_DBI_RDATA_8814B                                                   \\\n\t(BIT_MASK_DBI_RDATA_8814B << BIT_SHIFT_DBI_RDATA_8814B)\n#define BIT_CLEAR_DBI_RDATA_8814B(x) ((x) & (~BITS_DBI_RDATA_8814B))\n#define BIT_GET_DBI_RDATA_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBI_RDATA_8814B) & BIT_MASK_DBI_RDATA_8814B)\n#define BIT_SET_DBI_RDATA_8814B(x, v)                                          \\\n\t(BIT_CLEAR_DBI_RDATA_8814B(x) | BIT_DBI_RDATA_8814B(v))\n\n/* 2 REG_DBI_FLAG_V1_8814B */\n\n#define BIT_SHIFT_LOOPBACK_DBG_SEL_8814B 28\n#define BIT_MASK_LOOPBACK_DBG_SEL_8814B 0xf\n#define BIT_LOOPBACK_DBG_SEL_8814B(x)                                          \\\n\t(((x) & BIT_MASK_LOOPBACK_DBG_SEL_8814B)                               \\\n\t << BIT_SHIFT_LOOPBACK_DBG_SEL_8814B)\n#define BITS_LOOPBACK_DBG_SEL_8814B                                            \\\n\t(BIT_MASK_LOOPBACK_DBG_SEL_8814B << BIT_SHIFT_LOOPBACK_DBG_SEL_8814B)\n#define BIT_CLEAR_LOOPBACK_DBG_SEL_8814B(x)                                    \\\n\t((x) & (~BITS_LOOPBACK_DBG_SEL_8814B))\n#define BIT_GET_LOOPBACK_DBG_SEL_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_LOOPBACK_DBG_SEL_8814B) &                           \\\n\t BIT_MASK_LOOPBACK_DBG_SEL_8814B)\n#define BIT_SET_LOOPBACK_DBG_SEL_8814B(x, v)                                   \\\n\t(BIT_CLEAR_LOOPBACK_DBG_SEL_8814B(x) | BIT_LOOPBACK_DBG_SEL_8814B(v))\n\n#define BIT_EN_STUCK_DBG_8814B BIT(26)\n#define BIT_RX_STUCK_8814B BIT(25)\n#define BIT_TX_STUCK_8814B BIT(24)\n#define BIT_DBI_RFLAG_8814B BIT(17)\n#define BIT_DBI_WFLAG_8814B BIT(16)\n\n#define BIT_SHIFT_DBI_WREN_8814B 12\n#define BIT_MASK_DBI_WREN_8814B 0xf\n#define BIT_DBI_WREN_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_DBI_WREN_8814B) << BIT_SHIFT_DBI_WREN_8814B)\n#define BITS_DBI_WREN_8814B                                                    \\\n\t(BIT_MASK_DBI_WREN_8814B << BIT_SHIFT_DBI_WREN_8814B)\n#define BIT_CLEAR_DBI_WREN_8814B(x) ((x) & (~BITS_DBI_WREN_8814B))\n#define BIT_GET_DBI_WREN_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_DBI_WREN_8814B) & BIT_MASK_DBI_WREN_8814B)\n#define BIT_SET_DBI_WREN_8814B(x, v)                                           \\\n\t(BIT_CLEAR_DBI_WREN_8814B(x) | BIT_DBI_WREN_8814B(v))\n\n#define BIT_SHIFT_DBI_ADDR_8814B 0\n#define BIT_MASK_DBI_ADDR_8814B 0xfff\n#define BIT_DBI_ADDR_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_DBI_ADDR_8814B) << BIT_SHIFT_DBI_ADDR_8814B)\n#define BITS_DBI_ADDR_8814B                                                    \\\n\t(BIT_MASK_DBI_ADDR_8814B << BIT_SHIFT_DBI_ADDR_8814B)\n#define BIT_CLEAR_DBI_ADDR_8814B(x) ((x) & (~BITS_DBI_ADDR_8814B))\n#define BIT_GET_DBI_ADDR_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_DBI_ADDR_8814B) & BIT_MASK_DBI_ADDR_8814B)\n#define BIT_SET_DBI_ADDR_8814B(x, v)                                           \\\n\t(BIT_CLEAR_DBI_ADDR_8814B(x) | BIT_DBI_ADDR_8814B(v))\n\n/* 2 REG_MDIO_V1_8814B */\n\n#define BIT_SHIFT_MDIO_RDATA_8814B 16\n#define BIT_MASK_MDIO_RDATA_8814B 0xffff\n#define BIT_MDIO_RDATA_8814B(x)                                                \\\n\t(((x) & BIT_MASK_MDIO_RDATA_8814B) << BIT_SHIFT_MDIO_RDATA_8814B)\n#define BITS_MDIO_RDATA_8814B                                                  \\\n\t(BIT_MASK_MDIO_RDATA_8814B << BIT_SHIFT_MDIO_RDATA_8814B)\n#define BIT_CLEAR_MDIO_RDATA_8814B(x) ((x) & (~BITS_MDIO_RDATA_8814B))\n#define BIT_GET_MDIO_RDATA_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_MDIO_RDATA_8814B) & BIT_MASK_MDIO_RDATA_8814B)\n#define BIT_SET_MDIO_RDATA_8814B(x, v)                                         \\\n\t(BIT_CLEAR_MDIO_RDATA_8814B(x) | BIT_MDIO_RDATA_8814B(v))\n\n#define BIT_SHIFT_MDIO_WDATA_8814B 0\n#define BIT_MASK_MDIO_WDATA_8814B 0xffff\n#define BIT_MDIO_WDATA_8814B(x)                                                \\\n\t(((x) & BIT_MASK_MDIO_WDATA_8814B) << BIT_SHIFT_MDIO_WDATA_8814B)\n#define BITS_MDIO_WDATA_8814B                                                  \\\n\t(BIT_MASK_MDIO_WDATA_8814B << BIT_SHIFT_MDIO_WDATA_8814B)\n#define BIT_CLEAR_MDIO_WDATA_8814B(x) ((x) & (~BITS_MDIO_WDATA_8814B))\n#define BIT_GET_MDIO_WDATA_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_MDIO_WDATA_8814B) & BIT_MASK_MDIO_WDATA_8814B)\n#define BIT_SET_MDIO_WDATA_8814B(x, v)                                         \\\n\t(BIT_CLEAR_MDIO_WDATA_8814B(x) | BIT_MDIO_WDATA_8814B(v))\n\n/* 2 REG_PCIE_MIX_CFG_8814B */\n\n#define BIT_SHIFT_MDIO_PHY_ADDR_8814B 24\n#define BIT_MASK_MDIO_PHY_ADDR_8814B 0x1f\n#define BIT_MDIO_PHY_ADDR_8814B(x)                                             \\\n\t(((x) & BIT_MASK_MDIO_PHY_ADDR_8814B) << BIT_SHIFT_MDIO_PHY_ADDR_8814B)\n#define BITS_MDIO_PHY_ADDR_8814B                                               \\\n\t(BIT_MASK_MDIO_PHY_ADDR_8814B << BIT_SHIFT_MDIO_PHY_ADDR_8814B)\n#define BIT_CLEAR_MDIO_PHY_ADDR_8814B(x) ((x) & (~BITS_MDIO_PHY_ADDR_8814B))\n#define BIT_GET_MDIO_PHY_ADDR_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8814B) & BIT_MASK_MDIO_PHY_ADDR_8814B)\n#define BIT_SET_MDIO_PHY_ADDR_8814B(x, v)                                      \\\n\t(BIT_CLEAR_MDIO_PHY_ADDR_8814B(x) | BIT_MDIO_PHY_ADDR_8814B(v))\n\n#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B 10\n#define BIT_MASK_WATCH_DOG_RECORD_V1_8814B 0x3fff\n#define BIT_WATCH_DOG_RECORD_V1_8814B(x)                                       \\\n\t(((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8814B)                            \\\n\t << BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B)\n#define BITS_WATCH_DOG_RECORD_V1_8814B                                         \\\n\t(BIT_MASK_WATCH_DOG_RECORD_V1_8814B                                    \\\n\t << BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B)\n#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8814B(x)                                 \\\n\t((x) & (~BITS_WATCH_DOG_RECORD_V1_8814B))\n#define BIT_GET_WATCH_DOG_RECORD_V1_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B) &                        \\\n\t BIT_MASK_WATCH_DOG_RECORD_V1_8814B)\n#define BIT_SET_WATCH_DOG_RECORD_V1_8814B(x, v)                                \\\n\t(BIT_CLEAR_WATCH_DOG_RECORD_V1_8814B(x) |                              \\\n\t BIT_WATCH_DOG_RECORD_V1_8814B(v))\n\n#define BIT_R_IO_TIMEOUT_FLAG_V1_8814B BIT(9)\n#define BIT_EN_WATCH_DOG_8814B BIT(8)\n#define BIT_ECRC_EN_8814B BIT(7)\n#define BIT_MDIO_RFLAG_8814B BIT(6)\n#define BIT_MDIO_WFLAG_8814B BIT(5)\n\n#define BIT_SHIFT_MDIO_REG_ADDR_8814B 0\n#define BIT_MASK_MDIO_REG_ADDR_8814B 0x1f\n#define BIT_MDIO_REG_ADDR_8814B(x)                                             \\\n\t(((x) & BIT_MASK_MDIO_REG_ADDR_8814B) << BIT_SHIFT_MDIO_REG_ADDR_8814B)\n#define BITS_MDIO_REG_ADDR_8814B                                               \\\n\t(BIT_MASK_MDIO_REG_ADDR_8814B << BIT_SHIFT_MDIO_REG_ADDR_8814B)\n#define BIT_CLEAR_MDIO_REG_ADDR_8814B(x) ((x) & (~BITS_MDIO_REG_ADDR_8814B))\n#define BIT_GET_MDIO_REG_ADDR_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MDIO_REG_ADDR_8814B) & BIT_MASK_MDIO_REG_ADDR_8814B)\n#define BIT_SET_MDIO_REG_ADDR_8814B(x, v)                                      \\\n\t(BIT_CLEAR_MDIO_REG_ADDR_8814B(x) | BIT_MDIO_REG_ADDR_8814B(v))\n\n/* 2 REG_HCI_MIX_CFG_8814B */\n#define BIT_EN_ALIGN_MTU_8814B BIT(23)\n\n#define BIT_SHIFT_LATENCY_CONTROL_8814B 21\n#define BIT_MASK_LATENCY_CONTROL_8814B 0x3\n#define BIT_LATENCY_CONTROL_8814B(x)                                           \\\n\t(((x) & BIT_MASK_LATENCY_CONTROL_8814B)                                \\\n\t << BIT_SHIFT_LATENCY_CONTROL_8814B)\n#define BITS_LATENCY_CONTROL_8814B                                             \\\n\t(BIT_MASK_LATENCY_CONTROL_8814B << BIT_SHIFT_LATENCY_CONTROL_8814B)\n#define BIT_CLEAR_LATENCY_CONTROL_8814B(x) ((x) & (~BITS_LATENCY_CONTROL_8814B))\n#define BIT_GET_LATENCY_CONTROL_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_LATENCY_CONTROL_8814B) &                            \\\n\t BIT_MASK_LATENCY_CONTROL_8814B)\n#define BIT_SET_LATENCY_CONTROL_8814B(x, v)                                    \\\n\t(BIT_CLEAR_LATENCY_CONTROL_8814B(x) | BIT_LATENCY_CONTROL_8814B(v))\n\n#define BIT_HOST_GEN2_SUPPORT_8814B BIT(20)\n\n#define BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B 15\n#define BIT_MASK_TXDMA_ERR_FLAG_V1_8814B 0x1f\n#define BIT_TXDMA_ERR_FLAG_V1_8814B(x)                                         \\\n\t(((x) & BIT_MASK_TXDMA_ERR_FLAG_V1_8814B)                              \\\n\t << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B)\n#define BITS_TXDMA_ERR_FLAG_V1_8814B                                           \\\n\t(BIT_MASK_TXDMA_ERR_FLAG_V1_8814B << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B)\n#define BIT_CLEAR_TXDMA_ERR_FLAG_V1_8814B(x)                                   \\\n\t((x) & (~BITS_TXDMA_ERR_FLAG_V1_8814B))\n#define BIT_GET_TXDMA_ERR_FLAG_V1_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B) &                          \\\n\t BIT_MASK_TXDMA_ERR_FLAG_V1_8814B)\n#define BIT_SET_TXDMA_ERR_FLAG_V1_8814B(x, v)                                  \\\n\t(BIT_CLEAR_TXDMA_ERR_FLAG_V1_8814B(x) | BIT_TXDMA_ERR_FLAG_V1_8814B(v))\n\n#define BIT_EPHY_RX50_EN_8814B BIT(11)\n\n#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B 8\n#define BIT_MASK_MSI_TIMEOUT_ID_V1_8814B 0x7\n#define BIT_MSI_TIMEOUT_ID_V1_8814B(x)                                         \\\n\t(((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8814B)                              \\\n\t << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B)\n#define BITS_MSI_TIMEOUT_ID_V1_8814B                                           \\\n\t(BIT_MASK_MSI_TIMEOUT_ID_V1_8814B << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B)\n#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8814B(x)                                   \\\n\t((x) & (~BITS_MSI_TIMEOUT_ID_V1_8814B))\n#define BIT_GET_MSI_TIMEOUT_ID_V1_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B) &                          \\\n\t BIT_MASK_MSI_TIMEOUT_ID_V1_8814B)\n#define BIT_SET_MSI_TIMEOUT_ID_V1_8814B(x, v)                                  \\\n\t(BIT_CLEAR_MSI_TIMEOUT_ID_V1_8814B(x) | BIT_MSI_TIMEOUT_ID_V1_8814B(v))\n\n#define BIT_RADDR_RD_8814B BIT(7)\n#define BIT_L0S_LINK_OFF_8814B BIT(4)\n#define BIT_ACT_LINK_OFF_8814B BIT(3)\n#define BIT_EN_SLOW_MAC_TX_8814B BIT(2)\n#define BIT_EN_SLOW_MAC_RX_8814B BIT(1)\n#define BIT_EN_SLOW_MAC_HW_8814B BIT(0)\n\n/* 2 REG_STC_INT_CS_8814B(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */\n#define BIT_STC_INT_EN_8814B BIT(31)\n\n#define BIT_SHIFT_STC_INT_FLAG_8814B 16\n#define BIT_MASK_STC_INT_FLAG_8814B 0xff\n#define BIT_STC_INT_FLAG_8814B(x)                                              \\\n\t(((x) & BIT_MASK_STC_INT_FLAG_8814B) << BIT_SHIFT_STC_INT_FLAG_8814B)\n#define BITS_STC_INT_FLAG_8814B                                                \\\n\t(BIT_MASK_STC_INT_FLAG_8814B << BIT_SHIFT_STC_INT_FLAG_8814B)\n#define BIT_CLEAR_STC_INT_FLAG_8814B(x) ((x) & (~BITS_STC_INT_FLAG_8814B))\n#define BIT_GET_STC_INT_FLAG_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_STC_INT_FLAG_8814B) & BIT_MASK_STC_INT_FLAG_8814B)\n#define BIT_SET_STC_INT_FLAG_8814B(x, v)                                       \\\n\t(BIT_CLEAR_STC_INT_FLAG_8814B(x) | BIT_STC_INT_FLAG_8814B(v))\n\n#define BIT_SHIFT_STC_INT_IDX_8814B 8\n#define BIT_MASK_STC_INT_IDX_8814B 0x7\n#define BIT_STC_INT_IDX_8814B(x)                                               \\\n\t(((x) & BIT_MASK_STC_INT_IDX_8814B) << BIT_SHIFT_STC_INT_IDX_8814B)\n#define BITS_STC_INT_IDX_8814B                                                 \\\n\t(BIT_MASK_STC_INT_IDX_8814B << BIT_SHIFT_STC_INT_IDX_8814B)\n#define BIT_CLEAR_STC_INT_IDX_8814B(x) ((x) & (~BITS_STC_INT_IDX_8814B))\n#define BIT_GET_STC_INT_IDX_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_STC_INT_IDX_8814B) & BIT_MASK_STC_INT_IDX_8814B)\n#define BIT_SET_STC_INT_IDX_8814B(x, v)                                        \\\n\t(BIT_CLEAR_STC_INT_IDX_8814B(x) | BIT_STC_INT_IDX_8814B(v))\n\n#define BIT_SHIFT_STC_INT_REALTIME_CS_8814B 0\n#define BIT_MASK_STC_INT_REALTIME_CS_8814B 0x3f\n#define BIT_STC_INT_REALTIME_CS_8814B(x)                                       \\\n\t(((x) & BIT_MASK_STC_INT_REALTIME_CS_8814B)                            \\\n\t << BIT_SHIFT_STC_INT_REALTIME_CS_8814B)\n#define BITS_STC_INT_REALTIME_CS_8814B                                         \\\n\t(BIT_MASK_STC_INT_REALTIME_CS_8814B                                    \\\n\t << BIT_SHIFT_STC_INT_REALTIME_CS_8814B)\n#define BIT_CLEAR_STC_INT_REALTIME_CS_8814B(x)                                 \\\n\t((x) & (~BITS_STC_INT_REALTIME_CS_8814B))\n#define BIT_GET_STC_INT_REALTIME_CS_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8814B) &                        \\\n\t BIT_MASK_STC_INT_REALTIME_CS_8814B)\n#define BIT_SET_STC_INT_REALTIME_CS_8814B(x, v)                                \\\n\t(BIT_CLEAR_STC_INT_REALTIME_CS_8814B(x) |                              \\\n\t BIT_STC_INT_REALTIME_CS_8814B(v))\n\n/* 2 REG_ST_INT_CFG_8814B(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */\n#define BIT_STC_INT_GRP_EN_8814B BIT(31)\n\n#define BIT_SHIFT_STC_INT_EXPECT_LS_8814B 8\n#define BIT_MASK_STC_INT_EXPECT_LS_8814B 0x3f\n#define BIT_STC_INT_EXPECT_LS_8814B(x)                                         \\\n\t(((x) & BIT_MASK_STC_INT_EXPECT_LS_8814B)                              \\\n\t << BIT_SHIFT_STC_INT_EXPECT_LS_8814B)\n#define BITS_STC_INT_EXPECT_LS_8814B                                           \\\n\t(BIT_MASK_STC_INT_EXPECT_LS_8814B << BIT_SHIFT_STC_INT_EXPECT_LS_8814B)\n#define BIT_CLEAR_STC_INT_EXPECT_LS_8814B(x)                                   \\\n\t((x) & (~BITS_STC_INT_EXPECT_LS_8814B))\n#define BIT_GET_STC_INT_EXPECT_LS_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8814B) &                          \\\n\t BIT_MASK_STC_INT_EXPECT_LS_8814B)\n#define BIT_SET_STC_INT_EXPECT_LS_8814B(x, v)                                  \\\n\t(BIT_CLEAR_STC_INT_EXPECT_LS_8814B(x) | BIT_STC_INT_EXPECT_LS_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_STC_INT_EXPECT_CS_8814B 0\n#define BIT_MASK_STC_INT_EXPECT_CS_8814B 0x3f\n#define BIT_STC_INT_EXPECT_CS_8814B(x)                                         \\\n\t(((x) & BIT_MASK_STC_INT_EXPECT_CS_8814B)                              \\\n\t << BIT_SHIFT_STC_INT_EXPECT_CS_8814B)\n#define BITS_STC_INT_EXPECT_CS_8814B                                           \\\n\t(BIT_MASK_STC_INT_EXPECT_CS_8814B << BIT_SHIFT_STC_INT_EXPECT_CS_8814B)\n#define BIT_CLEAR_STC_INT_EXPECT_CS_8814B(x)                                   \\\n\t((x) & (~BITS_STC_INT_EXPECT_CS_8814B))\n#define BIT_GET_STC_INT_EXPECT_CS_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8814B) &                          \\\n\t BIT_MASK_STC_INT_EXPECT_CS_8814B)\n#define BIT_SET_STC_INT_EXPECT_CS_8814B(x, v)                                  \\\n\t(BIT_CLEAR_STC_INT_EXPECT_CS_8814B(x) | BIT_STC_INT_EXPECT_CS_8814B(v))\n\n/* 2 REG_ACH4_ACH5_TXBD_NUM_8814B */\n#define BIT_PCIE_ACH5_FLAG_8814B BIT(30)\n\n#define BIT_SHIFT_ACH5_DESC_MODE_8814B 28\n#define BIT_MASK_ACH5_DESC_MODE_8814B 0x3\n#define BIT_ACH5_DESC_MODE_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACH5_DESC_MODE_8814B)                                 \\\n\t << BIT_SHIFT_ACH5_DESC_MODE_8814B)\n#define BITS_ACH5_DESC_MODE_8814B                                              \\\n\t(BIT_MASK_ACH5_DESC_MODE_8814B << BIT_SHIFT_ACH5_DESC_MODE_8814B)\n#define BIT_CLEAR_ACH5_DESC_MODE_8814B(x) ((x) & (~BITS_ACH5_DESC_MODE_8814B))\n#define BIT_GET_ACH5_DESC_MODE_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACH5_DESC_MODE_8814B) &                             \\\n\t BIT_MASK_ACH5_DESC_MODE_8814B)\n#define BIT_SET_ACH5_DESC_MODE_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACH5_DESC_MODE_8814B(x) | BIT_ACH5_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_ACH5_DESC_NUM_8814B 16\n#define BIT_MASK_ACH5_DESC_NUM_8814B 0xfff\n#define BIT_ACH5_DESC_NUM_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH5_DESC_NUM_8814B) << BIT_SHIFT_ACH5_DESC_NUM_8814B)\n#define BITS_ACH5_DESC_NUM_8814B                                               \\\n\t(BIT_MASK_ACH5_DESC_NUM_8814B << BIT_SHIFT_ACH5_DESC_NUM_8814B)\n#define BIT_CLEAR_ACH5_DESC_NUM_8814B(x) ((x) & (~BITS_ACH5_DESC_NUM_8814B))\n#define BIT_GET_ACH5_DESC_NUM_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH5_DESC_NUM_8814B) & BIT_MASK_ACH5_DESC_NUM_8814B)\n#define BIT_SET_ACH5_DESC_NUM_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH5_DESC_NUM_8814B(x) | BIT_ACH5_DESC_NUM_8814B(v))\n\n#define BIT_PCIE_ACH4_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_ACH4_DESC_MODE_8814B 12\n#define BIT_MASK_ACH4_DESC_MODE_8814B 0x3\n#define BIT_ACH4_DESC_MODE_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACH4_DESC_MODE_8814B)                                 \\\n\t << BIT_SHIFT_ACH4_DESC_MODE_8814B)\n#define BITS_ACH4_DESC_MODE_8814B                                              \\\n\t(BIT_MASK_ACH4_DESC_MODE_8814B << BIT_SHIFT_ACH4_DESC_MODE_8814B)\n#define BIT_CLEAR_ACH4_DESC_MODE_8814B(x) ((x) & (~BITS_ACH4_DESC_MODE_8814B))\n#define BIT_GET_ACH4_DESC_MODE_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACH4_DESC_MODE_8814B) &                             \\\n\t BIT_MASK_ACH4_DESC_MODE_8814B)\n#define BIT_SET_ACH4_DESC_MODE_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACH4_DESC_MODE_8814B(x) | BIT_ACH4_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_ACH4_DESC_NUM_8814B 0\n#define BIT_MASK_ACH4_DESC_NUM_8814B 0xfff\n#define BIT_ACH4_DESC_NUM_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH4_DESC_NUM_8814B) << BIT_SHIFT_ACH4_DESC_NUM_8814B)\n#define BITS_ACH4_DESC_NUM_8814B                                               \\\n\t(BIT_MASK_ACH4_DESC_NUM_8814B << BIT_SHIFT_ACH4_DESC_NUM_8814B)\n#define BIT_CLEAR_ACH4_DESC_NUM_8814B(x) ((x) & (~BITS_ACH4_DESC_NUM_8814B))\n#define BIT_GET_ACH4_DESC_NUM_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH4_DESC_NUM_8814B) & BIT_MASK_ACH4_DESC_NUM_8814B)\n#define BIT_SET_ACH4_DESC_NUM_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH4_DESC_NUM_8814B(x) | BIT_ACH4_DESC_NUM_8814B(v))\n\n/* 2 REG_FWCMDQ_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_FWCMDQ_HW_IDX_8814B 16\n#define BIT_MASK_FWCMDQ_HW_IDX_8814B 0xfff\n#define BIT_FWCMDQ_HW_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_FWCMDQ_HW_IDX_8814B) << BIT_SHIFT_FWCMDQ_HW_IDX_8814B)\n#define BITS_FWCMDQ_HW_IDX_8814B                                               \\\n\t(BIT_MASK_FWCMDQ_HW_IDX_8814B << BIT_SHIFT_FWCMDQ_HW_IDX_8814B)\n#define BIT_CLEAR_FWCMDQ_HW_IDX_8814B(x) ((x) & (~BITS_FWCMDQ_HW_IDX_8814B))\n#define BIT_GET_FWCMDQ_HW_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_HW_IDX_8814B) & BIT_MASK_FWCMDQ_HW_IDX_8814B)\n#define BIT_SET_FWCMDQ_HW_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_FWCMDQ_HW_IDX_8814B(x) | BIT_FWCMDQ_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_FWCMDQ_HOST_IDX_8814B 0\n#define BIT_MASK_FWCMDQ_HOST_IDX_8814B 0xfff\n#define BIT_FWCMDQ_HOST_IDX_8814B(x)                                           \\\n\t(((x) & BIT_MASK_FWCMDQ_HOST_IDX_8814B)                                \\\n\t << BIT_SHIFT_FWCMDQ_HOST_IDX_8814B)\n#define BITS_FWCMDQ_HOST_IDX_8814B                                             \\\n\t(BIT_MASK_FWCMDQ_HOST_IDX_8814B << BIT_SHIFT_FWCMDQ_HOST_IDX_8814B)\n#define BIT_CLEAR_FWCMDQ_HOST_IDX_8814B(x) ((x) & (~BITS_FWCMDQ_HOST_IDX_8814B))\n#define BIT_GET_FWCMDQ_HOST_IDX_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_HOST_IDX_8814B) &                            \\\n\t BIT_MASK_FWCMDQ_HOST_IDX_8814B)\n#define BIT_SET_FWCMDQ_HOST_IDX_8814B(x, v)                                    \\\n\t(BIT_CLEAR_FWCMDQ_HOST_IDX_8814B(x) | BIT_FWCMDQ_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI8Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI8Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI8Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI8Q_HW_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_P0HI8Q_HW_IDX_8814B) << BIT_SHIFT_P0HI8Q_HW_IDX_8814B)\n#define BITS_P0HI8Q_HW_IDX_8814B                                               \\\n\t(BIT_MASK_P0HI8Q_HW_IDX_8814B << BIT_SHIFT_P0HI8Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI8Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI8Q_HW_IDX_8814B))\n#define BIT_GET_P0HI8Q_HW_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_P0HI8Q_HW_IDX_8814B) & BIT_MASK_P0HI8Q_HW_IDX_8814B)\n#define BIT_SET_P0HI8Q_HW_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_P0HI8Q_HW_IDX_8814B(x) | BIT_P0HI8Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI8Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI8Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI8Q_HOST_IDX_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI8Q_HOST_IDX_8814B)                                \\\n\t << BIT_SHIFT_P0HI8Q_HOST_IDX_8814B)\n#define BITS_P0HI8Q_HOST_IDX_8814B                                             \\\n\t(BIT_MASK_P0HI8Q_HOST_IDX_8814B << BIT_SHIFT_P0HI8Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI8Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI8Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI8Q_HOST_IDX_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI8Q_HOST_IDX_8814B) &                            \\\n\t BIT_MASK_P0HI8Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI8Q_HOST_IDX_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI8Q_HOST_IDX_8814B(x) | BIT_P0HI8Q_HOST_IDX_8814B(v))\n\n/* 2 REG_H2CQ_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B 0\n#define BIT_MASK_H2CQ_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_H2CQ_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_H2CQ_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B)\n#define BITS_H2CQ_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_H2CQ_TXBD_DESA_L_8814B << BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_H2CQ_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_H2CQ_TXBD_DESA_L_8814B))\n#define BIT_GET_H2CQ_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_H2CQ_TXBD_DESA_L_8814B)\n#define BIT_SET_H2CQ_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_H2CQ_TXBD_DESA_L_8814B(x) | BIT_H2CQ_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_H2CQ_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B 0\n#define BIT_MASK_H2CQ_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_H2CQ_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_H2CQ_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B)\n#define BITS_H2CQ_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_H2CQ_TXBD_DESA_H_8814B << BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_H2CQ_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_H2CQ_TXBD_DESA_H_8814B))\n#define BIT_GET_H2CQ_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_H2CQ_TXBD_DESA_H_8814B)\n#define BIT_SET_H2CQ_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_H2CQ_TXBD_DESA_H_8814B(x) | BIT_H2CQ_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_H2CQ_TXBD_NUM_8814B */\n#define BIT_PCIE_H2CQ_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_H2CQ_DESC_MODE_8814B 12\n#define BIT_MASK_H2CQ_DESC_MODE_8814B 0x3\n#define BIT_H2CQ_DESC_MODE_8814B(x)                                            \\\n\t(((x) & BIT_MASK_H2CQ_DESC_MODE_8814B)                                 \\\n\t << BIT_SHIFT_H2CQ_DESC_MODE_8814B)\n#define BITS_H2CQ_DESC_MODE_8814B                                              \\\n\t(BIT_MASK_H2CQ_DESC_MODE_8814B << BIT_SHIFT_H2CQ_DESC_MODE_8814B)\n#define BIT_CLEAR_H2CQ_DESC_MODE_8814B(x) ((x) & (~BITS_H2CQ_DESC_MODE_8814B))\n#define BIT_GET_H2CQ_DESC_MODE_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8814B) &                             \\\n\t BIT_MASK_H2CQ_DESC_MODE_8814B)\n#define BIT_SET_H2CQ_DESC_MODE_8814B(x, v)                                     \\\n\t(BIT_CLEAR_H2CQ_DESC_MODE_8814B(x) | BIT_H2CQ_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_H2CQ_DESC_NUM_8814B 0\n#define BIT_MASK_H2CQ_DESC_NUM_8814B 0xfff\n#define BIT_H2CQ_DESC_NUM_8814B(x)                                             \\\n\t(((x) & BIT_MASK_H2CQ_DESC_NUM_8814B) << BIT_SHIFT_H2CQ_DESC_NUM_8814B)\n#define BITS_H2CQ_DESC_NUM_8814B                                               \\\n\t(BIT_MASK_H2CQ_DESC_NUM_8814B << BIT_SHIFT_H2CQ_DESC_NUM_8814B)\n#define BIT_CLEAR_H2CQ_DESC_NUM_8814B(x) ((x) & (~BITS_H2CQ_DESC_NUM_8814B))\n#define BIT_GET_H2CQ_DESC_NUM_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8814B) & BIT_MASK_H2CQ_DESC_NUM_8814B)\n#define BIT_SET_H2CQ_DESC_NUM_8814B(x, v)                                      \\\n\t(BIT_CLEAR_H2CQ_DESC_NUM_8814B(x) | BIT_H2CQ_DESC_NUM_8814B(v))\n\n/* 2 REG_H2CQ_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_H2CQ_HW_IDX_8814B 16\n#define BIT_MASK_H2CQ_HW_IDX_8814B 0xfff\n#define BIT_H2CQ_HW_IDX_8814B(x)                                               \\\n\t(((x) & BIT_MASK_H2CQ_HW_IDX_8814B) << BIT_SHIFT_H2CQ_HW_IDX_8814B)\n#define BITS_H2CQ_HW_IDX_8814B                                                 \\\n\t(BIT_MASK_H2CQ_HW_IDX_8814B << BIT_SHIFT_H2CQ_HW_IDX_8814B)\n#define BIT_CLEAR_H2CQ_HW_IDX_8814B(x) ((x) & (~BITS_H2CQ_HW_IDX_8814B))\n#define BIT_GET_H2CQ_HW_IDX_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_H2CQ_HW_IDX_8814B) & BIT_MASK_H2CQ_HW_IDX_8814B)\n#define BIT_SET_H2CQ_HW_IDX_8814B(x, v)                                        \\\n\t(BIT_CLEAR_H2CQ_HW_IDX_8814B(x) | BIT_H2CQ_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_H2CQ_HOST_IDX_8814B 0\n#define BIT_MASK_H2CQ_HOST_IDX_8814B 0xfff\n#define BIT_H2CQ_HOST_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_H2CQ_HOST_IDX_8814B) << BIT_SHIFT_H2CQ_HOST_IDX_8814B)\n#define BITS_H2CQ_HOST_IDX_8814B                                               \\\n\t(BIT_MASK_H2CQ_HOST_IDX_8814B << BIT_SHIFT_H2CQ_HOST_IDX_8814B)\n#define BIT_CLEAR_H2CQ_HOST_IDX_8814B(x) ((x) & (~BITS_H2CQ_HOST_IDX_8814B))\n#define BIT_GET_H2CQ_HOST_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8814B) & BIT_MASK_H2CQ_HOST_IDX_8814B)\n#define BIT_SET_H2CQ_HOST_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_H2CQ_HOST_IDX_8814B(x) | BIT_H2CQ_HOST_IDX_8814B(v))\n\n/* 2 REG_H2CQ_CSR_8814B[31:0] (H2CQ CONTROL AND STATUS) */\n#define BIT_H2CQ_FULL_8814B BIT(31)\n#define BIT_CLR_H2CQ_HOST_IDX_8814B BIT(16)\n#define BIT_CLR_H2CQ_HW_IDX_8814B BIT(8)\n#define BIT_STOP_H2CQ_8814B BIT(0)\n\n/* 2 REG_P0HI9Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI9Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI9Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI9Q_HW_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_P0HI9Q_HW_IDX_8814B) << BIT_SHIFT_P0HI9Q_HW_IDX_8814B)\n#define BITS_P0HI9Q_HW_IDX_8814B                                               \\\n\t(BIT_MASK_P0HI9Q_HW_IDX_8814B << BIT_SHIFT_P0HI9Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI9Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI9Q_HW_IDX_8814B))\n#define BIT_GET_P0HI9Q_HW_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_P0HI9Q_HW_IDX_8814B) & BIT_MASK_P0HI9Q_HW_IDX_8814B)\n#define BIT_SET_P0HI9Q_HW_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_P0HI9Q_HW_IDX_8814B(x) | BIT_P0HI9Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI9Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI9Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI9Q_HOST_IDX_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI9Q_HOST_IDX_8814B)                                \\\n\t << BIT_SHIFT_P0HI9Q_HOST_IDX_8814B)\n#define BITS_P0HI9Q_HOST_IDX_8814B                                             \\\n\t(BIT_MASK_P0HI9Q_HOST_IDX_8814B << BIT_SHIFT_P0HI9Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI9Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI9Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI9Q_HOST_IDX_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI9Q_HOST_IDX_8814B) &                            \\\n\t BIT_MASK_P0HI9Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI9Q_HOST_IDX_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI9Q_HOST_IDX_8814B(x) | BIT_P0HI9Q_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI10Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI10Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI10Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI10Q_HW_IDX_8814B(x)                                            \\\n\t(((x) & BIT_MASK_P0HI10Q_HW_IDX_8814B)                                 \\\n\t << BIT_SHIFT_P0HI10Q_HW_IDX_8814B)\n#define BITS_P0HI10Q_HW_IDX_8814B                                              \\\n\t(BIT_MASK_P0HI10Q_HW_IDX_8814B << BIT_SHIFT_P0HI10Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI10Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI10Q_HW_IDX_8814B))\n#define BIT_GET_P0HI10Q_HW_IDX_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_P0HI10Q_HW_IDX_8814B) &                             \\\n\t BIT_MASK_P0HI10Q_HW_IDX_8814B)\n#define BIT_SET_P0HI10Q_HW_IDX_8814B(x, v)                                     \\\n\t(BIT_CLEAR_P0HI10Q_HW_IDX_8814B(x) | BIT_P0HI10Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI10Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI10Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI10Q_HOST_IDX_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI10Q_HOST_IDX_8814B)                               \\\n\t << BIT_SHIFT_P0HI10Q_HOST_IDX_8814B)\n#define BITS_P0HI10Q_HOST_IDX_8814B                                            \\\n\t(BIT_MASK_P0HI10Q_HOST_IDX_8814B << BIT_SHIFT_P0HI10Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI10Q_HOST_IDX_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI10Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI10Q_HOST_IDX_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI10Q_HOST_IDX_8814B) &                           \\\n\t BIT_MASK_P0HI10Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI10Q_HOST_IDX_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI10Q_HOST_IDX_8814B(x) | BIT_P0HI10Q_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI11Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI11Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI11Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI11Q_HW_IDX_8814B(x)                                            \\\n\t(((x) & BIT_MASK_P0HI11Q_HW_IDX_8814B)                                 \\\n\t << BIT_SHIFT_P0HI11Q_HW_IDX_8814B)\n#define BITS_P0HI11Q_HW_IDX_8814B                                              \\\n\t(BIT_MASK_P0HI11Q_HW_IDX_8814B << BIT_SHIFT_P0HI11Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI11Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI11Q_HW_IDX_8814B))\n#define BIT_GET_P0HI11Q_HW_IDX_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_P0HI11Q_HW_IDX_8814B) &                             \\\n\t BIT_MASK_P0HI11Q_HW_IDX_8814B)\n#define BIT_SET_P0HI11Q_HW_IDX_8814B(x, v)                                     \\\n\t(BIT_CLEAR_P0HI11Q_HW_IDX_8814B(x) | BIT_P0HI11Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI11Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI11Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI11Q_HOST_IDX_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI11Q_HOST_IDX_8814B)                               \\\n\t << BIT_SHIFT_P0HI11Q_HOST_IDX_8814B)\n#define BITS_P0HI11Q_HOST_IDX_8814B                                            \\\n\t(BIT_MASK_P0HI11Q_HOST_IDX_8814B << BIT_SHIFT_P0HI11Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI11Q_HOST_IDX_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI11Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI11Q_HOST_IDX_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI11Q_HOST_IDX_8814B) &                           \\\n\t BIT_MASK_P0HI11Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI11Q_HOST_IDX_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI11Q_HOST_IDX_8814B(x) | BIT_P0HI11Q_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI12Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI12Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI12Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI12Q_HW_IDX_8814B(x)                                            \\\n\t(((x) & BIT_MASK_P0HI12Q_HW_IDX_8814B)                                 \\\n\t << BIT_SHIFT_P0HI12Q_HW_IDX_8814B)\n#define BITS_P0HI12Q_HW_IDX_8814B                                              \\\n\t(BIT_MASK_P0HI12Q_HW_IDX_8814B << BIT_SHIFT_P0HI12Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI12Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI12Q_HW_IDX_8814B))\n#define BIT_GET_P0HI12Q_HW_IDX_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_P0HI12Q_HW_IDX_8814B) &                             \\\n\t BIT_MASK_P0HI12Q_HW_IDX_8814B)\n#define BIT_SET_P0HI12Q_HW_IDX_8814B(x, v)                                     \\\n\t(BIT_CLEAR_P0HI12Q_HW_IDX_8814B(x) | BIT_P0HI12Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI12Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI12Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI12Q_HOST_IDX_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI12Q_HOST_IDX_8814B)                               \\\n\t << BIT_SHIFT_P0HI12Q_HOST_IDX_8814B)\n#define BITS_P0HI12Q_HOST_IDX_8814B                                            \\\n\t(BIT_MASK_P0HI12Q_HOST_IDX_8814B << BIT_SHIFT_P0HI12Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI12Q_HOST_IDX_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI12Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI12Q_HOST_IDX_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI12Q_HOST_IDX_8814B) &                           \\\n\t BIT_MASK_P0HI12Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI12Q_HOST_IDX_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI12Q_HOST_IDX_8814B(x) | BIT_P0HI12Q_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI13Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI13Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI13Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI13Q_HW_IDX_8814B(x)                                            \\\n\t(((x) & BIT_MASK_P0HI13Q_HW_IDX_8814B)                                 \\\n\t << BIT_SHIFT_P0HI13Q_HW_IDX_8814B)\n#define BITS_P0HI13Q_HW_IDX_8814B                                              \\\n\t(BIT_MASK_P0HI13Q_HW_IDX_8814B << BIT_SHIFT_P0HI13Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI13Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI13Q_HW_IDX_8814B))\n#define BIT_GET_P0HI13Q_HW_IDX_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_P0HI13Q_HW_IDX_8814B) &                             \\\n\t BIT_MASK_P0HI13Q_HW_IDX_8814B)\n#define BIT_SET_P0HI13Q_HW_IDX_8814B(x, v)                                     \\\n\t(BIT_CLEAR_P0HI13Q_HW_IDX_8814B(x) | BIT_P0HI13Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI13Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI13Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI13Q_HOST_IDX_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI13Q_HOST_IDX_8814B)                               \\\n\t << BIT_SHIFT_P0HI13Q_HOST_IDX_8814B)\n#define BITS_P0HI13Q_HOST_IDX_8814B                                            \\\n\t(BIT_MASK_P0HI13Q_HOST_IDX_8814B << BIT_SHIFT_P0HI13Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI13Q_HOST_IDX_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI13Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI13Q_HOST_IDX_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI13Q_HOST_IDX_8814B) &                           \\\n\t BIT_MASK_P0HI13Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI13Q_HOST_IDX_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI13Q_HOST_IDX_8814B(x) | BIT_P0HI13Q_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI14Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI14Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI14Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI14Q_HW_IDX_8814B(x)                                            \\\n\t(((x) & BIT_MASK_P0HI14Q_HW_IDX_8814B)                                 \\\n\t << BIT_SHIFT_P0HI14Q_HW_IDX_8814B)\n#define BITS_P0HI14Q_HW_IDX_8814B                                              \\\n\t(BIT_MASK_P0HI14Q_HW_IDX_8814B << BIT_SHIFT_P0HI14Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI14Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI14Q_HW_IDX_8814B))\n#define BIT_GET_P0HI14Q_HW_IDX_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_P0HI14Q_HW_IDX_8814B) &                             \\\n\t BIT_MASK_P0HI14Q_HW_IDX_8814B)\n#define BIT_SET_P0HI14Q_HW_IDX_8814B(x, v)                                     \\\n\t(BIT_CLEAR_P0HI14Q_HW_IDX_8814B(x) | BIT_P0HI14Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI14Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI14Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI14Q_HOST_IDX_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI14Q_HOST_IDX_8814B)                               \\\n\t << BIT_SHIFT_P0HI14Q_HOST_IDX_8814B)\n#define BITS_P0HI14Q_HOST_IDX_8814B                                            \\\n\t(BIT_MASK_P0HI14Q_HOST_IDX_8814B << BIT_SHIFT_P0HI14Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI14Q_HOST_IDX_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI14Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI14Q_HOST_IDX_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI14Q_HOST_IDX_8814B) &                           \\\n\t BIT_MASK_P0HI14Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI14Q_HOST_IDX_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI14Q_HOST_IDX_8814B(x) | BIT_P0HI14Q_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI15Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI15Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI15Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI15Q_HW_IDX_8814B(x)                                            \\\n\t(((x) & BIT_MASK_P0HI15Q_HW_IDX_8814B)                                 \\\n\t << BIT_SHIFT_P0HI15Q_HW_IDX_8814B)\n#define BITS_P0HI15Q_HW_IDX_8814B                                              \\\n\t(BIT_MASK_P0HI15Q_HW_IDX_8814B << BIT_SHIFT_P0HI15Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI15Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI15Q_HW_IDX_8814B))\n#define BIT_GET_P0HI15Q_HW_IDX_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_P0HI15Q_HW_IDX_8814B) &                             \\\n\t BIT_MASK_P0HI15Q_HW_IDX_8814B)\n#define BIT_SET_P0HI15Q_HW_IDX_8814B(x, v)                                     \\\n\t(BIT_CLEAR_P0HI15Q_HW_IDX_8814B(x) | BIT_P0HI15Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI15Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI15Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI15Q_HOST_IDX_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI15Q_HOST_IDX_8814B)                               \\\n\t << BIT_SHIFT_P0HI15Q_HOST_IDX_8814B)\n#define BITS_P0HI15Q_HOST_IDX_8814B                                            \\\n\t(BIT_MASK_P0HI15Q_HOST_IDX_8814B << BIT_SHIFT_P0HI15Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI15Q_HOST_IDX_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI15Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI15Q_HOST_IDX_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI15Q_HOST_IDX_8814B) &                           \\\n\t BIT_MASK_P0HI15Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI15Q_HOST_IDX_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI15Q_HOST_IDX_8814B(x) | BIT_P0HI15Q_HOST_IDX_8814B(v))\n\n/* 2 REG_CHANGE_PCIE_SPEED_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_RXDMA_ERR_CNT_8814B 8\n#define BIT_MASK_RXDMA_ERR_CNT_8814B 0xff\n#define BIT_RXDMA_ERR_CNT_8814B(x)                                             \\\n\t(((x) & BIT_MASK_RXDMA_ERR_CNT_8814B) << BIT_SHIFT_RXDMA_ERR_CNT_8814B)\n#define BITS_RXDMA_ERR_CNT_8814B                                               \\\n\t(BIT_MASK_RXDMA_ERR_CNT_8814B << BIT_SHIFT_RXDMA_ERR_CNT_8814B)\n#define BIT_CLEAR_RXDMA_ERR_CNT_8814B(x) ((x) & (~BITS_RXDMA_ERR_CNT_8814B))\n#define BIT_GET_RXDMA_ERR_CNT_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXDMA_ERR_CNT_8814B) & BIT_MASK_RXDMA_ERR_CNT_8814B)\n#define BIT_SET_RXDMA_ERR_CNT_8814B(x, v)                                      \\\n\t(BIT_CLEAR_RXDMA_ERR_CNT_8814B(x) | BIT_RXDMA_ERR_CNT_8814B(v))\n\n#define BIT_TXDMA_ERR_HANDLE_REQ_8814B BIT(7)\n#define BIT_TXDMA_ERROR_PS_8814B BIT(6)\n#define BIT_EN_TXDMA_STUCK_ERR_HANDLE_8814B BIT(5)\n#define BIT_EN_TXDMA_RTN_ERR_HANDLE_8814B BIT(4)\n#define BIT_RXDMA_ERR_HANDLE_REQ_8814B BIT(3)\n#define BIT_RXDMA_ERROR_PS_8814B BIT(2)\n#define BIT_EN_RXDMA_STUCK_ERR_HANDLE_8814B BIT(1)\n#define BIT_EN_RXDMA_RTN_ERR_HANDLE_8814B BIT(0)\n\n/* 2 REG_DEBUG_STATE1_8814B */\n\n#define BIT_SHIFT_DEBUG_STATE1_8814B 0\n#define BIT_MASK_DEBUG_STATE1_8814B 0xffffffffL\n#define BIT_DEBUG_STATE1_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DEBUG_STATE1_8814B) << BIT_SHIFT_DEBUG_STATE1_8814B)\n#define BITS_DEBUG_STATE1_8814B                                                \\\n\t(BIT_MASK_DEBUG_STATE1_8814B << BIT_SHIFT_DEBUG_STATE1_8814B)\n#define BIT_CLEAR_DEBUG_STATE1_8814B(x) ((x) & (~BITS_DEBUG_STATE1_8814B))\n#define BIT_GET_DEBUG_STATE1_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DEBUG_STATE1_8814B) & BIT_MASK_DEBUG_STATE1_8814B)\n#define BIT_SET_DEBUG_STATE1_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DEBUG_STATE1_8814B(x) | BIT_DEBUG_STATE1_8814B(v))\n\n/* 2 REG_DEBUG_STATE2_8814B */\n\n#define BIT_SHIFT_DEBUG_STATE2_8814B 0\n#define BIT_MASK_DEBUG_STATE2_8814B 0xffffffffL\n#define BIT_DEBUG_STATE2_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DEBUG_STATE2_8814B) << BIT_SHIFT_DEBUG_STATE2_8814B)\n#define BITS_DEBUG_STATE2_8814B                                                \\\n\t(BIT_MASK_DEBUG_STATE2_8814B << BIT_SHIFT_DEBUG_STATE2_8814B)\n#define BIT_CLEAR_DEBUG_STATE2_8814B(x) ((x) & (~BITS_DEBUG_STATE2_8814B))\n#define BIT_GET_DEBUG_STATE2_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DEBUG_STATE2_8814B) & BIT_MASK_DEBUG_STATE2_8814B)\n#define BIT_SET_DEBUG_STATE2_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DEBUG_STATE2_8814B(x) | BIT_DEBUG_STATE2_8814B(v))\n\n/* 2 REG_DEBUG_STATE3_8814B */\n\n#define BIT_SHIFT_DEBUG_STATE3_8814B 0\n#define BIT_MASK_DEBUG_STATE3_8814B 0xffffffffL\n#define BIT_DEBUG_STATE3_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DEBUG_STATE3_8814B) << BIT_SHIFT_DEBUG_STATE3_8814B)\n#define BITS_DEBUG_STATE3_8814B                                                \\\n\t(BIT_MASK_DEBUG_STATE3_8814B << BIT_SHIFT_DEBUG_STATE3_8814B)\n#define BIT_CLEAR_DEBUG_STATE3_8814B(x) ((x) & (~BITS_DEBUG_STATE3_8814B))\n#define BIT_GET_DEBUG_STATE3_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DEBUG_STATE3_8814B) & BIT_MASK_DEBUG_STATE3_8814B)\n#define BIT_SET_DEBUG_STATE3_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DEBUG_STATE3_8814B(x) | BIT_DEBUG_STATE3_8814B(v))\n\n/* 2 REG_ACH5_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_ACH5_TXBD_DESA_L_8814B 0\n#define BIT_MASK_ACH5_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_ACH5_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH5_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_ACH5_TXBD_DESA_L_8814B)\n#define BITS_ACH5_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_ACH5_TXBD_DESA_L_8814B << BIT_SHIFT_ACH5_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_ACH5_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_ACH5_TXBD_DESA_L_8814B))\n#define BIT_GET_ACH5_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH5_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_ACH5_TXBD_DESA_L_8814B)\n#define BIT_SET_ACH5_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH5_TXBD_DESA_L_8814B(x) | BIT_ACH5_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_ACH5_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_ACH5_TXBD_DESA_H_8814B 0\n#define BIT_MASK_ACH5_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_ACH5_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH5_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_ACH5_TXBD_DESA_H_8814B)\n#define BITS_ACH5_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_ACH5_TXBD_DESA_H_8814B << BIT_SHIFT_ACH5_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_ACH5_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_ACH5_TXBD_DESA_H_8814B))\n#define BIT_GET_ACH5_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH5_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_ACH5_TXBD_DESA_H_8814B)\n#define BIT_SET_ACH5_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH5_TXBD_DESA_H_8814B(x) | BIT_ACH5_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_ACH6_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_ACH6_TXBD_DESA_L_8814B 0\n#define BIT_MASK_ACH6_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_ACH6_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH6_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_ACH6_TXBD_DESA_L_8814B)\n#define BITS_ACH6_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_ACH6_TXBD_DESA_L_8814B << BIT_SHIFT_ACH6_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_ACH6_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_ACH6_TXBD_DESA_L_8814B))\n#define BIT_GET_ACH6_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH6_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_ACH6_TXBD_DESA_L_8814B)\n#define BIT_SET_ACH6_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH6_TXBD_DESA_L_8814B(x) | BIT_ACH6_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_ACH6_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_ACH6_TXBD_DESA_H_8814B 0\n#define BIT_MASK_ACH6_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_ACH6_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH6_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_ACH6_TXBD_DESA_H_8814B)\n#define BITS_ACH6_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_ACH6_TXBD_DESA_H_8814B << BIT_SHIFT_ACH6_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_ACH6_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_ACH6_TXBD_DESA_H_8814B))\n#define BIT_GET_ACH6_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH6_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_ACH6_TXBD_DESA_H_8814B)\n#define BIT_SET_ACH6_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH6_TXBD_DESA_H_8814B(x) | BIT_ACH6_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_ACH7_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_ACH7_TXBD_DESA_L_8814B 0\n#define BIT_MASK_ACH7_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_ACH7_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH7_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_ACH7_TXBD_DESA_L_8814B)\n#define BITS_ACH7_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_ACH7_TXBD_DESA_L_8814B << BIT_SHIFT_ACH7_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_ACH7_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_ACH7_TXBD_DESA_L_8814B))\n#define BIT_GET_ACH7_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH7_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_ACH7_TXBD_DESA_L_8814B)\n#define BIT_SET_ACH7_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH7_TXBD_DESA_L_8814B(x) | BIT_ACH7_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_ACH7_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_ACH7_TXBD_DESA_H_8814B 0\n#define BIT_MASK_ACH7_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_ACH7_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH7_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_ACH7_TXBD_DESA_H_8814B)\n#define BITS_ACH7_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_ACH7_TXBD_DESA_H_8814B << BIT_SHIFT_ACH7_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_ACH7_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_ACH7_TXBD_DESA_H_8814B))\n#define BIT_GET_ACH7_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH7_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_ACH7_TXBD_DESA_H_8814B)\n#define BIT_SET_ACH7_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH7_TXBD_DESA_H_8814B(x) | BIT_ACH7_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_ACH8_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_ACH8_TXBD_DESA_L_8814B 0\n#define BIT_MASK_ACH8_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_ACH8_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH8_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_ACH8_TXBD_DESA_L_8814B)\n#define BITS_ACH8_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_ACH8_TXBD_DESA_L_8814B << BIT_SHIFT_ACH8_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_ACH8_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_ACH8_TXBD_DESA_L_8814B))\n#define BIT_GET_ACH8_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH8_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_ACH8_TXBD_DESA_L_8814B)\n#define BIT_SET_ACH8_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH8_TXBD_DESA_L_8814B(x) | BIT_ACH8_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_ACH8_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_ACH8_TXBD_DESA_H_8814B 0\n#define BIT_MASK_ACH8_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_ACH8_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH8_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_ACH8_TXBD_DESA_H_8814B)\n#define BITS_ACH8_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_ACH8_TXBD_DESA_H_8814B << BIT_SHIFT_ACH8_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_ACH8_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_ACH8_TXBD_DESA_H_8814B))\n#define BIT_GET_ACH8_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH8_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_ACH8_TXBD_DESA_H_8814B)\n#define BIT_SET_ACH8_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH8_TXBD_DESA_H_8814B(x) | BIT_ACH8_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_ACH9_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_ACH9_TXBD_DESA_L_8814B 0\n#define BIT_MASK_ACH9_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_ACH9_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH9_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_ACH9_TXBD_DESA_L_8814B)\n#define BITS_ACH9_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_ACH9_TXBD_DESA_L_8814B << BIT_SHIFT_ACH9_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_ACH9_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_ACH9_TXBD_DESA_L_8814B))\n#define BIT_GET_ACH9_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH9_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_ACH9_TXBD_DESA_L_8814B)\n#define BIT_SET_ACH9_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH9_TXBD_DESA_L_8814B(x) | BIT_ACH9_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_ACH9_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_ACH9_TXBD_DESA_H_8814B 0\n#define BIT_MASK_ACH9_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_ACH9_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH9_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_ACH9_TXBD_DESA_H_8814B)\n#define BITS_ACH9_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_ACH9_TXBD_DESA_H_8814B << BIT_SHIFT_ACH9_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_ACH9_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_ACH9_TXBD_DESA_H_8814B))\n#define BIT_GET_ACH9_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH9_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_ACH9_TXBD_DESA_H_8814B)\n#define BIT_SET_ACH9_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH9_TXBD_DESA_H_8814B(x) | BIT_ACH9_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_ACH10_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_ACH10_TXBD_DESA_L_8814B 0\n#define BIT_MASK_ACH10_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_ACH10_TXBD_DESA_L_8814B(x)                                         \\\n\t(((x) & BIT_MASK_ACH10_TXBD_DESA_L_8814B)                              \\\n\t << BIT_SHIFT_ACH10_TXBD_DESA_L_8814B)\n#define BITS_ACH10_TXBD_DESA_L_8814B                                           \\\n\t(BIT_MASK_ACH10_TXBD_DESA_L_8814B << BIT_SHIFT_ACH10_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_ACH10_TXBD_DESA_L_8814B(x)                                   \\\n\t((x) & (~BITS_ACH10_TXBD_DESA_L_8814B))\n#define BIT_GET_ACH10_TXBD_DESA_L_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_ACH10_TXBD_DESA_L_8814B) &                          \\\n\t BIT_MASK_ACH10_TXBD_DESA_L_8814B)\n#define BIT_SET_ACH10_TXBD_DESA_L_8814B(x, v)                                  \\\n\t(BIT_CLEAR_ACH10_TXBD_DESA_L_8814B(x) | BIT_ACH10_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_ACH10_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_ACH10_TXBD_DESA_H_8814B 0\n#define BIT_MASK_ACH10_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_ACH10_TXBD_DESA_H_8814B(x)                                         \\\n\t(((x) & BIT_MASK_ACH10_TXBD_DESA_H_8814B)                              \\\n\t << BIT_SHIFT_ACH10_TXBD_DESA_H_8814B)\n#define BITS_ACH10_TXBD_DESA_H_8814B                                           \\\n\t(BIT_MASK_ACH10_TXBD_DESA_H_8814B << BIT_SHIFT_ACH10_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_ACH10_TXBD_DESA_H_8814B(x)                                   \\\n\t((x) & (~BITS_ACH10_TXBD_DESA_H_8814B))\n#define BIT_GET_ACH10_TXBD_DESA_H_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_ACH10_TXBD_DESA_H_8814B) &                          \\\n\t BIT_MASK_ACH10_TXBD_DESA_H_8814B)\n#define BIT_SET_ACH10_TXBD_DESA_H_8814B(x, v)                                  \\\n\t(BIT_CLEAR_ACH10_TXBD_DESA_H_8814B(x) | BIT_ACH10_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_ACH11_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_ACH11_TXBD_DESA_L_8814B 0\n#define BIT_MASK_ACH11_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_ACH11_TXBD_DESA_L_8814B(x)                                         \\\n\t(((x) & BIT_MASK_ACH11_TXBD_DESA_L_8814B)                              \\\n\t << BIT_SHIFT_ACH11_TXBD_DESA_L_8814B)\n#define BITS_ACH11_TXBD_DESA_L_8814B                                           \\\n\t(BIT_MASK_ACH11_TXBD_DESA_L_8814B << BIT_SHIFT_ACH11_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_ACH11_TXBD_DESA_L_8814B(x)                                   \\\n\t((x) & (~BITS_ACH11_TXBD_DESA_L_8814B))\n#define BIT_GET_ACH11_TXBD_DESA_L_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_ACH11_TXBD_DESA_L_8814B) &                          \\\n\t BIT_MASK_ACH11_TXBD_DESA_L_8814B)\n#define BIT_SET_ACH11_TXBD_DESA_L_8814B(x, v)                                  \\\n\t(BIT_CLEAR_ACH11_TXBD_DESA_L_8814B(x) | BIT_ACH11_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_ACH11_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_ACH11_TXBD_DESA_H_8814B 0\n#define BIT_MASK_ACH11_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_ACH11_TXBD_DESA_H_8814B(x)                                         \\\n\t(((x) & BIT_MASK_ACH11_TXBD_DESA_H_8814B)                              \\\n\t << BIT_SHIFT_ACH11_TXBD_DESA_H_8814B)\n#define BITS_ACH11_TXBD_DESA_H_8814B                                           \\\n\t(BIT_MASK_ACH11_TXBD_DESA_H_8814B << BIT_SHIFT_ACH11_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_ACH11_TXBD_DESA_H_8814B(x)                                   \\\n\t((x) & (~BITS_ACH11_TXBD_DESA_H_8814B))\n#define BIT_GET_ACH11_TXBD_DESA_H_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_ACH11_TXBD_DESA_H_8814B) &                          \\\n\t BIT_MASK_ACH11_TXBD_DESA_H_8814B)\n#define BIT_SET_ACH11_TXBD_DESA_H_8814B(x, v)                                  \\\n\t(BIT_CLEAR_ACH11_TXBD_DESA_H_8814B(x) | BIT_ACH11_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_ACH12_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_ACH12_TXBD_DESA_L_8814B 0\n#define BIT_MASK_ACH12_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_ACH12_TXBD_DESA_L_8814B(x)                                         \\\n\t(((x) & BIT_MASK_ACH12_TXBD_DESA_L_8814B)                              \\\n\t << BIT_SHIFT_ACH12_TXBD_DESA_L_8814B)\n#define BITS_ACH12_TXBD_DESA_L_8814B                                           \\\n\t(BIT_MASK_ACH12_TXBD_DESA_L_8814B << BIT_SHIFT_ACH12_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_ACH12_TXBD_DESA_L_8814B(x)                                   \\\n\t((x) & (~BITS_ACH12_TXBD_DESA_L_8814B))\n#define BIT_GET_ACH12_TXBD_DESA_L_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_ACH12_TXBD_DESA_L_8814B) &                          \\\n\t BIT_MASK_ACH12_TXBD_DESA_L_8814B)\n#define BIT_SET_ACH12_TXBD_DESA_L_8814B(x, v)                                  \\\n\t(BIT_CLEAR_ACH12_TXBD_DESA_L_8814B(x) | BIT_ACH12_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_ACH12_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_ACH12_TXBD_DESA_H_8814B 0\n#define BIT_MASK_ACH12_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_ACH12_TXBD_DESA_H_8814B(x)                                         \\\n\t(((x) & BIT_MASK_ACH12_TXBD_DESA_H_8814B)                              \\\n\t << BIT_SHIFT_ACH12_TXBD_DESA_H_8814B)\n#define BITS_ACH12_TXBD_DESA_H_8814B                                           \\\n\t(BIT_MASK_ACH12_TXBD_DESA_H_8814B << BIT_SHIFT_ACH12_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_ACH12_TXBD_DESA_H_8814B(x)                                   \\\n\t((x) & (~BITS_ACH12_TXBD_DESA_H_8814B))\n#define BIT_GET_ACH12_TXBD_DESA_H_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_ACH12_TXBD_DESA_H_8814B) &                          \\\n\t BIT_MASK_ACH12_TXBD_DESA_H_8814B)\n#define BIT_SET_ACH12_TXBD_DESA_H_8814B(x, v)                                  \\\n\t(BIT_CLEAR_ACH12_TXBD_DESA_H_8814B(x) | BIT_ACH12_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_ACH13_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_ACH13_TXBD_DESA_L_8814B 0\n#define BIT_MASK_ACH13_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_ACH13_TXBD_DESA_L_8814B(x)                                         \\\n\t(((x) & BIT_MASK_ACH13_TXBD_DESA_L_8814B)                              \\\n\t << BIT_SHIFT_ACH13_TXBD_DESA_L_8814B)\n#define BITS_ACH13_TXBD_DESA_L_8814B                                           \\\n\t(BIT_MASK_ACH13_TXBD_DESA_L_8814B << BIT_SHIFT_ACH13_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_ACH13_TXBD_DESA_L_8814B(x)                                   \\\n\t((x) & (~BITS_ACH13_TXBD_DESA_L_8814B))\n#define BIT_GET_ACH13_TXBD_DESA_L_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_ACH13_TXBD_DESA_L_8814B) &                          \\\n\t BIT_MASK_ACH13_TXBD_DESA_L_8814B)\n#define BIT_SET_ACH13_TXBD_DESA_L_8814B(x, v)                                  \\\n\t(BIT_CLEAR_ACH13_TXBD_DESA_L_8814B(x) | BIT_ACH13_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_ACH13_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_ACH13_TXBD_DESA_H_8814B 0\n#define BIT_MASK_ACH13_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_ACH13_TXBD_DESA_H_8814B(x)                                         \\\n\t(((x) & BIT_MASK_ACH13_TXBD_DESA_H_8814B)                              \\\n\t << BIT_SHIFT_ACH13_TXBD_DESA_H_8814B)\n#define BITS_ACH13_TXBD_DESA_H_8814B                                           \\\n\t(BIT_MASK_ACH13_TXBD_DESA_H_8814B << BIT_SHIFT_ACH13_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_ACH13_TXBD_DESA_H_8814B(x)                                   \\\n\t((x) & (~BITS_ACH13_TXBD_DESA_H_8814B))\n#define BIT_GET_ACH13_TXBD_DESA_H_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_ACH13_TXBD_DESA_H_8814B) &                          \\\n\t BIT_MASK_ACH13_TXBD_DESA_H_8814B)\n#define BIT_SET_ACH13_TXBD_DESA_H_8814B(x, v)                                  \\\n\t(BIT_CLEAR_ACH13_TXBD_DESA_H_8814B(x) | BIT_ACH13_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI0Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI0Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI0Q_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI0Q_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B)\n#define BITS_HI0Q_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_HI0Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI0Q_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_HI0Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI0Q_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_HI0Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI0Q_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI0Q_TXBD_DESA_L_8814B(x) | BIT_HI0Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI0Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI0Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI0Q_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI0Q_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B)\n#define BITS_HI0Q_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_HI0Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI0Q_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_HI0Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI0Q_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_HI0Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI0Q_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI0Q_TXBD_DESA_H_8814B(x) | BIT_HI0Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI1Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI1Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI1Q_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI1Q_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B)\n#define BITS_HI1Q_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_HI1Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI1Q_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_HI1Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI1Q_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_HI1Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI1Q_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI1Q_TXBD_DESA_L_8814B(x) | BIT_HI1Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI1Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI1Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI1Q_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI1Q_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B)\n#define BITS_HI1Q_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_HI1Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI1Q_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_HI1Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI1Q_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_HI1Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI1Q_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI1Q_TXBD_DESA_H_8814B(x) | BIT_HI1Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI2Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI2Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI2Q_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI2Q_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B)\n#define BITS_HI2Q_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_HI2Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI2Q_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_HI2Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI2Q_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_HI2Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI2Q_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI2Q_TXBD_DESA_L_8814B(x) | BIT_HI2Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI2Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI2Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI2Q_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI2Q_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B)\n#define BITS_HI2Q_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_HI2Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI2Q_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_HI2Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI2Q_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_HI2Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI2Q_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI2Q_TXBD_DESA_H_8814B(x) | BIT_HI2Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI3Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI3Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI3Q_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI3Q_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B)\n#define BITS_HI3Q_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_HI3Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI3Q_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_HI3Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI3Q_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_HI3Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI3Q_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI3Q_TXBD_DESA_L_8814B(x) | BIT_HI3Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI3Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI3Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI3Q_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI3Q_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B)\n#define BITS_HI3Q_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_HI3Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI3Q_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_HI3Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI3Q_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_HI3Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI3Q_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI3Q_TXBD_DESA_H_8814B(x) | BIT_HI3Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI4Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI4Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI4Q_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI4Q_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B)\n#define BITS_HI4Q_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_HI4Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI4Q_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_HI4Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI4Q_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_HI4Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI4Q_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI4Q_TXBD_DESA_L_8814B(x) | BIT_HI4Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI4Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI4Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI4Q_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI4Q_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B)\n#define BITS_HI4Q_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_HI4Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI4Q_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_HI4Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI4Q_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_HI4Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI4Q_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI4Q_TXBD_DESA_H_8814B(x) | BIT_HI4Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI5Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI5Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI5Q_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI5Q_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B)\n#define BITS_HI5Q_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_HI5Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI5Q_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_HI5Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI5Q_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_HI5Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI5Q_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI5Q_TXBD_DESA_L_8814B(x) | BIT_HI5Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI5Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI5Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI5Q_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI5Q_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B)\n#define BITS_HI5Q_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_HI5Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI5Q_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_HI5Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI5Q_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_HI5Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI5Q_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI5Q_TXBD_DESA_H_8814B(x) | BIT_HI5Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI6Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI6Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI6Q_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI6Q_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B)\n#define BITS_HI6Q_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_HI6Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI6Q_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_HI6Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI6Q_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_HI6Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI6Q_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI6Q_TXBD_DESA_L_8814B(x) | BIT_HI6Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI6Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI6Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI6Q_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI6Q_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B)\n#define BITS_HI6Q_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_HI6Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI6Q_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_HI6Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI6Q_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_HI6Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI6Q_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI6Q_TXBD_DESA_H_8814B(x) | BIT_HI6Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI7Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI7Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI7Q_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI7Q_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B)\n#define BITS_HI7Q_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_HI7Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI7Q_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_HI7Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI7Q_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_HI7Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI7Q_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI7Q_TXBD_DESA_L_8814B(x) | BIT_HI7Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI7Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI7Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI7Q_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI7Q_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B)\n#define BITS_HI7Q_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_HI7Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI7Q_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_HI7Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI7Q_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_HI7Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI7Q_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI7Q_TXBD_DESA_H_8814B(x) | BIT_HI7Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_ACH8_ACH9_TXBD_NUM_8814B */\n#define BIT_PCIE_ACH9_FLAG_8814B BIT(30)\n\n#define BIT_SHIFT_ACH9_DESC_MODE_8814B 28\n#define BIT_MASK_ACH9_DESC_MODE_8814B 0x3\n#define BIT_ACH9_DESC_MODE_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACH9_DESC_MODE_8814B)                                 \\\n\t << BIT_SHIFT_ACH9_DESC_MODE_8814B)\n#define BITS_ACH9_DESC_MODE_8814B                                              \\\n\t(BIT_MASK_ACH9_DESC_MODE_8814B << BIT_SHIFT_ACH9_DESC_MODE_8814B)\n#define BIT_CLEAR_ACH9_DESC_MODE_8814B(x) ((x) & (~BITS_ACH9_DESC_MODE_8814B))\n#define BIT_GET_ACH9_DESC_MODE_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACH9_DESC_MODE_8814B) &                             \\\n\t BIT_MASK_ACH9_DESC_MODE_8814B)\n#define BIT_SET_ACH9_DESC_MODE_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACH9_DESC_MODE_8814B(x) | BIT_ACH9_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_ACH9_DESC_NUM_8814B 16\n#define BIT_MASK_ACH9_DESC_NUM_8814B 0xfff\n#define BIT_ACH9_DESC_NUM_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH9_DESC_NUM_8814B) << BIT_SHIFT_ACH9_DESC_NUM_8814B)\n#define BITS_ACH9_DESC_NUM_8814B                                               \\\n\t(BIT_MASK_ACH9_DESC_NUM_8814B << BIT_SHIFT_ACH9_DESC_NUM_8814B)\n#define BIT_CLEAR_ACH9_DESC_NUM_8814B(x) ((x) & (~BITS_ACH9_DESC_NUM_8814B))\n#define BIT_GET_ACH9_DESC_NUM_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH9_DESC_NUM_8814B) & BIT_MASK_ACH9_DESC_NUM_8814B)\n#define BIT_SET_ACH9_DESC_NUM_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH9_DESC_NUM_8814B(x) | BIT_ACH9_DESC_NUM_8814B(v))\n\n#define BIT_PCIE_ACH8_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_ACH8_DESC_MODE_8814B 12\n#define BIT_MASK_ACH8_DESC_MODE_8814B 0x3\n#define BIT_ACH8_DESC_MODE_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACH8_DESC_MODE_8814B)                                 \\\n\t << BIT_SHIFT_ACH8_DESC_MODE_8814B)\n#define BITS_ACH8_DESC_MODE_8814B                                              \\\n\t(BIT_MASK_ACH8_DESC_MODE_8814B << BIT_SHIFT_ACH8_DESC_MODE_8814B)\n#define BIT_CLEAR_ACH8_DESC_MODE_8814B(x) ((x) & (~BITS_ACH8_DESC_MODE_8814B))\n#define BIT_GET_ACH8_DESC_MODE_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACH8_DESC_MODE_8814B) &                             \\\n\t BIT_MASK_ACH8_DESC_MODE_8814B)\n#define BIT_SET_ACH8_DESC_MODE_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACH8_DESC_MODE_8814B(x) | BIT_ACH8_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_ACH8_DESC_NUM_8814B 0\n#define BIT_MASK_ACH8_DESC_NUM_8814B 0xfff\n#define BIT_ACH8_DESC_NUM_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH8_DESC_NUM_8814B) << BIT_SHIFT_ACH8_DESC_NUM_8814B)\n#define BITS_ACH8_DESC_NUM_8814B                                               \\\n\t(BIT_MASK_ACH8_DESC_NUM_8814B << BIT_SHIFT_ACH8_DESC_NUM_8814B)\n#define BIT_CLEAR_ACH8_DESC_NUM_8814B(x) ((x) & (~BITS_ACH8_DESC_NUM_8814B))\n#define BIT_GET_ACH8_DESC_NUM_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH8_DESC_NUM_8814B) & BIT_MASK_ACH8_DESC_NUM_8814B)\n#define BIT_SET_ACH8_DESC_NUM_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH8_DESC_NUM_8814B(x) | BIT_ACH8_DESC_NUM_8814B(v))\n\n/* 2 REG_ACH10_ACH11_TXBD_NUM_8814B */\n#define BIT_PCIE_ACH11_FLAG_8814B BIT(30)\n\n#define BIT_SHIFT_ACH11_DESC_MODE_8814B 28\n#define BIT_MASK_ACH11_DESC_MODE_8814B 0x3\n#define BIT_ACH11_DESC_MODE_8814B(x)                                           \\\n\t(((x) & BIT_MASK_ACH11_DESC_MODE_8814B)                                \\\n\t << BIT_SHIFT_ACH11_DESC_MODE_8814B)\n#define BITS_ACH11_DESC_MODE_8814B                                             \\\n\t(BIT_MASK_ACH11_DESC_MODE_8814B << BIT_SHIFT_ACH11_DESC_MODE_8814B)\n#define BIT_CLEAR_ACH11_DESC_MODE_8814B(x) ((x) & (~BITS_ACH11_DESC_MODE_8814B))\n#define BIT_GET_ACH11_DESC_MODE_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_ACH11_DESC_MODE_8814B) &                            \\\n\t BIT_MASK_ACH11_DESC_MODE_8814B)\n#define BIT_SET_ACH11_DESC_MODE_8814B(x, v)                                    \\\n\t(BIT_CLEAR_ACH11_DESC_MODE_8814B(x) | BIT_ACH11_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_ACH11_DESC_NUM_8814B 16\n#define BIT_MASK_ACH11_DESC_NUM_8814B 0xfff\n#define BIT_ACH11_DESC_NUM_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACH11_DESC_NUM_8814B)                                 \\\n\t << BIT_SHIFT_ACH11_DESC_NUM_8814B)\n#define BITS_ACH11_DESC_NUM_8814B                                              \\\n\t(BIT_MASK_ACH11_DESC_NUM_8814B << BIT_SHIFT_ACH11_DESC_NUM_8814B)\n#define BIT_CLEAR_ACH11_DESC_NUM_8814B(x) ((x) & (~BITS_ACH11_DESC_NUM_8814B))\n#define BIT_GET_ACH11_DESC_NUM_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACH11_DESC_NUM_8814B) &                             \\\n\t BIT_MASK_ACH11_DESC_NUM_8814B)\n#define BIT_SET_ACH11_DESC_NUM_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACH11_DESC_NUM_8814B(x) | BIT_ACH11_DESC_NUM_8814B(v))\n\n#define BIT_PCIE_ACH10_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_ACH10_DESC_MODE_8814B 12\n#define BIT_MASK_ACH10_DESC_MODE_8814B 0x3\n#define BIT_ACH10_DESC_MODE_8814B(x)                                           \\\n\t(((x) & BIT_MASK_ACH10_DESC_MODE_8814B)                                \\\n\t << BIT_SHIFT_ACH10_DESC_MODE_8814B)\n#define BITS_ACH10_DESC_MODE_8814B                                             \\\n\t(BIT_MASK_ACH10_DESC_MODE_8814B << BIT_SHIFT_ACH10_DESC_MODE_8814B)\n#define BIT_CLEAR_ACH10_DESC_MODE_8814B(x) ((x) & (~BITS_ACH10_DESC_MODE_8814B))\n#define BIT_GET_ACH10_DESC_MODE_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_ACH10_DESC_MODE_8814B) &                            \\\n\t BIT_MASK_ACH10_DESC_MODE_8814B)\n#define BIT_SET_ACH10_DESC_MODE_8814B(x, v)                                    \\\n\t(BIT_CLEAR_ACH10_DESC_MODE_8814B(x) | BIT_ACH10_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_ACH10_DESC_NUM_8814B 0\n#define BIT_MASK_ACH10_DESC_NUM_8814B 0xfff\n#define BIT_ACH10_DESC_NUM_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACH10_DESC_NUM_8814B)                                 \\\n\t << BIT_SHIFT_ACH10_DESC_NUM_8814B)\n#define BITS_ACH10_DESC_NUM_8814B                                              \\\n\t(BIT_MASK_ACH10_DESC_NUM_8814B << BIT_SHIFT_ACH10_DESC_NUM_8814B)\n#define BIT_CLEAR_ACH10_DESC_NUM_8814B(x) ((x) & (~BITS_ACH10_DESC_NUM_8814B))\n#define BIT_GET_ACH10_DESC_NUM_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACH10_DESC_NUM_8814B) &                             \\\n\t BIT_MASK_ACH10_DESC_NUM_8814B)\n#define BIT_SET_ACH10_DESC_NUM_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACH10_DESC_NUM_8814B(x) | BIT_ACH10_DESC_NUM_8814B(v))\n\n/* 2 REG_ACH12_ACH13_TXBD_NUM_8814B */\n#define BIT_PCIE_ACH13_FLAG_8814B BIT(30)\n\n#define BIT_SHIFT_ACH13_DESC_MODE_8814B 28\n#define BIT_MASK_ACH13_DESC_MODE_8814B 0x3\n#define BIT_ACH13_DESC_MODE_8814B(x)                                           \\\n\t(((x) & BIT_MASK_ACH13_DESC_MODE_8814B)                                \\\n\t << BIT_SHIFT_ACH13_DESC_MODE_8814B)\n#define BITS_ACH13_DESC_MODE_8814B                                             \\\n\t(BIT_MASK_ACH13_DESC_MODE_8814B << BIT_SHIFT_ACH13_DESC_MODE_8814B)\n#define BIT_CLEAR_ACH13_DESC_MODE_8814B(x) ((x) & (~BITS_ACH13_DESC_MODE_8814B))\n#define BIT_GET_ACH13_DESC_MODE_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_ACH13_DESC_MODE_8814B) &                            \\\n\t BIT_MASK_ACH13_DESC_MODE_8814B)\n#define BIT_SET_ACH13_DESC_MODE_8814B(x, v)                                    \\\n\t(BIT_CLEAR_ACH13_DESC_MODE_8814B(x) | BIT_ACH13_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_ACH13_DESC_NUM_8814B 16\n#define BIT_MASK_ACH13_DESC_NUM_8814B 0xfff\n#define BIT_ACH13_DESC_NUM_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACH13_DESC_NUM_8814B)                                 \\\n\t << BIT_SHIFT_ACH13_DESC_NUM_8814B)\n#define BITS_ACH13_DESC_NUM_8814B                                              \\\n\t(BIT_MASK_ACH13_DESC_NUM_8814B << BIT_SHIFT_ACH13_DESC_NUM_8814B)\n#define BIT_CLEAR_ACH13_DESC_NUM_8814B(x) ((x) & (~BITS_ACH13_DESC_NUM_8814B))\n#define BIT_GET_ACH13_DESC_NUM_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACH13_DESC_NUM_8814B) &                             \\\n\t BIT_MASK_ACH13_DESC_NUM_8814B)\n#define BIT_SET_ACH13_DESC_NUM_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACH13_DESC_NUM_8814B(x) | BIT_ACH13_DESC_NUM_8814B(v))\n\n#define BIT_PCIE_ACH12_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_ACH12_DESC_MODE_8814B 12\n#define BIT_MASK_ACH12_DESC_MODE_8814B 0x3\n#define BIT_ACH12_DESC_MODE_8814B(x)                                           \\\n\t(((x) & BIT_MASK_ACH12_DESC_MODE_8814B)                                \\\n\t << BIT_SHIFT_ACH12_DESC_MODE_8814B)\n#define BITS_ACH12_DESC_MODE_8814B                                             \\\n\t(BIT_MASK_ACH12_DESC_MODE_8814B << BIT_SHIFT_ACH12_DESC_MODE_8814B)\n#define BIT_CLEAR_ACH12_DESC_MODE_8814B(x) ((x) & (~BITS_ACH12_DESC_MODE_8814B))\n#define BIT_GET_ACH12_DESC_MODE_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_ACH12_DESC_MODE_8814B) &                            \\\n\t BIT_MASK_ACH12_DESC_MODE_8814B)\n#define BIT_SET_ACH12_DESC_MODE_8814B(x, v)                                    \\\n\t(BIT_CLEAR_ACH12_DESC_MODE_8814B(x) | BIT_ACH12_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_ACH12_DESC_NUM_8814B 0\n#define BIT_MASK_ACH12_DESC_NUM_8814B 0xfff\n#define BIT_ACH12_DESC_NUM_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACH12_DESC_NUM_8814B)                                 \\\n\t << BIT_SHIFT_ACH12_DESC_NUM_8814B)\n#define BITS_ACH12_DESC_NUM_8814B                                              \\\n\t(BIT_MASK_ACH12_DESC_NUM_8814B << BIT_SHIFT_ACH12_DESC_NUM_8814B)\n#define BIT_CLEAR_ACH12_DESC_NUM_8814B(x) ((x) & (~BITS_ACH12_DESC_NUM_8814B))\n#define BIT_GET_ACH12_DESC_NUM_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACH12_DESC_NUM_8814B) &                             \\\n\t BIT_MASK_ACH12_DESC_NUM_8814B)\n#define BIT_SET_ACH12_DESC_NUM_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACH12_DESC_NUM_8814B(x) | BIT_ACH12_DESC_NUM_8814B(v))\n\n/* 2 REG_OLD_DEHANG_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_OLD_DEHANG_8814B BIT(1)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_ACH4_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_ACH4_TXBD_DESA_L_8814B 0\n#define BIT_MASK_ACH4_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_ACH4_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH4_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_ACH4_TXBD_DESA_L_8814B)\n#define BITS_ACH4_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_ACH4_TXBD_DESA_L_8814B << BIT_SHIFT_ACH4_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_ACH4_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_ACH4_TXBD_DESA_L_8814B))\n#define BIT_GET_ACH4_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH4_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_ACH4_TXBD_DESA_L_8814B)\n#define BIT_SET_ACH4_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH4_TXBD_DESA_L_8814B(x) | BIT_ACH4_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_ACH4_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_ACH4_TXBD_DESA_H_8814B 0\n#define BIT_MASK_ACH4_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_ACH4_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_ACH4_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_ACH4_TXBD_DESA_H_8814B)\n#define BITS_ACH4_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_ACH4_TXBD_DESA_H_8814B << BIT_SHIFT_ACH4_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_ACH4_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_ACH4_TXBD_DESA_H_8814B))\n#define BIT_GET_ACH4_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_ACH4_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_ACH4_TXBD_DESA_H_8814B)\n#define BIT_SET_ACH4_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_ACH4_TXBD_DESA_H_8814B(x) | BIT_ACH4_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI8Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI8Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI8Q_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI8Q_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B)\n#define BITS_HI8Q_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_HI8Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI8Q_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_HI8Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI8Q_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_HI8Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI8Q_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI8Q_TXBD_DESA_L_8814B(x) | BIT_HI8Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI8Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI8Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI8Q_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI8Q_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B)\n#define BITS_HI8Q_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_HI8Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI8Q_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_HI8Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI8Q_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_HI8Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI8Q_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI8Q_TXBD_DESA_H_8814B(x) | BIT_HI8Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI9Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI9Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI9Q_TXBD_DESA_L_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI9Q_TXBD_DESA_L_8814B)                               \\\n\t << BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B)\n#define BITS_HI9Q_TXBD_DESA_L_8814B                                            \\\n\t(BIT_MASK_HI9Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI9Q_TXBD_DESA_L_8814B(x)                                    \\\n\t((x) & (~BITS_HI9Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI9Q_TXBD_DESA_L_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B) &                           \\\n\t BIT_MASK_HI9Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI9Q_TXBD_DESA_L_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI9Q_TXBD_DESA_L_8814B(x) | BIT_HI9Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI9Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI9Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI9Q_TXBD_DESA_H_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HI9Q_TXBD_DESA_H_8814B)                               \\\n\t << BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B)\n#define BITS_HI9Q_TXBD_DESA_H_8814B                                            \\\n\t(BIT_MASK_HI9Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI9Q_TXBD_DESA_H_8814B(x)                                    \\\n\t((x) & (~BITS_HI9Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI9Q_TXBD_DESA_H_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B) &                           \\\n\t BIT_MASK_HI9Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI9Q_TXBD_DESA_H_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HI9Q_TXBD_DESA_H_8814B(x) | BIT_HI9Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI10Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI10Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI10Q_TXBD_DESA_L_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI10Q_TXBD_DESA_L_8814B)                              \\\n\t << BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B)\n#define BITS_HI10Q_TXBD_DESA_L_8814B                                           \\\n\t(BIT_MASK_HI10Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI10Q_TXBD_DESA_L_8814B(x)                                   \\\n\t((x) & (~BITS_HI10Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI10Q_TXBD_DESA_L_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B) &                          \\\n\t BIT_MASK_HI10Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI10Q_TXBD_DESA_L_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI10Q_TXBD_DESA_L_8814B(x) | BIT_HI10Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI10Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI10Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI10Q_TXBD_DESA_H_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI10Q_TXBD_DESA_H_8814B)                              \\\n\t << BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B)\n#define BITS_HI10Q_TXBD_DESA_H_8814B                                           \\\n\t(BIT_MASK_HI10Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI10Q_TXBD_DESA_H_8814B(x)                                   \\\n\t((x) & (~BITS_HI10Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI10Q_TXBD_DESA_H_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B) &                          \\\n\t BIT_MASK_HI10Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI10Q_TXBD_DESA_H_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI10Q_TXBD_DESA_H_8814B(x) | BIT_HI10Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI11Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI11Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI11Q_TXBD_DESA_L_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI11Q_TXBD_DESA_L_8814B)                              \\\n\t << BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B)\n#define BITS_HI11Q_TXBD_DESA_L_8814B                                           \\\n\t(BIT_MASK_HI11Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI11Q_TXBD_DESA_L_8814B(x)                                   \\\n\t((x) & (~BITS_HI11Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI11Q_TXBD_DESA_L_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B) &                          \\\n\t BIT_MASK_HI11Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI11Q_TXBD_DESA_L_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI11Q_TXBD_DESA_L_8814B(x) | BIT_HI11Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI11Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI11Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI11Q_TXBD_DESA_H_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI11Q_TXBD_DESA_H_8814B)                              \\\n\t << BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B)\n#define BITS_HI11Q_TXBD_DESA_H_8814B                                           \\\n\t(BIT_MASK_HI11Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI11Q_TXBD_DESA_H_8814B(x)                                   \\\n\t((x) & (~BITS_HI11Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI11Q_TXBD_DESA_H_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B) &                          \\\n\t BIT_MASK_HI11Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI11Q_TXBD_DESA_H_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI11Q_TXBD_DESA_H_8814B(x) | BIT_HI11Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI12Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI12Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI12Q_TXBD_DESA_L_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI12Q_TXBD_DESA_L_8814B)                              \\\n\t << BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B)\n#define BITS_HI12Q_TXBD_DESA_L_8814B                                           \\\n\t(BIT_MASK_HI12Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI12Q_TXBD_DESA_L_8814B(x)                                   \\\n\t((x) & (~BITS_HI12Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI12Q_TXBD_DESA_L_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B) &                          \\\n\t BIT_MASK_HI12Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI12Q_TXBD_DESA_L_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI12Q_TXBD_DESA_L_8814B(x) | BIT_HI12Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI12Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI12Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI12Q_TXBD_DESA_H_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI12Q_TXBD_DESA_H_8814B)                              \\\n\t << BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B)\n#define BITS_HI12Q_TXBD_DESA_H_8814B                                           \\\n\t(BIT_MASK_HI12Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI12Q_TXBD_DESA_H_8814B(x)                                   \\\n\t((x) & (~BITS_HI12Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI12Q_TXBD_DESA_H_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B) &                          \\\n\t BIT_MASK_HI12Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI12Q_TXBD_DESA_H_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI12Q_TXBD_DESA_H_8814B(x) | BIT_HI12Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI13Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI13Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI13Q_TXBD_DESA_L_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI13Q_TXBD_DESA_L_8814B)                              \\\n\t << BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B)\n#define BITS_HI13Q_TXBD_DESA_L_8814B                                           \\\n\t(BIT_MASK_HI13Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI13Q_TXBD_DESA_L_8814B(x)                                   \\\n\t((x) & (~BITS_HI13Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI13Q_TXBD_DESA_L_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B) &                          \\\n\t BIT_MASK_HI13Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI13Q_TXBD_DESA_L_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI13Q_TXBD_DESA_L_8814B(x) | BIT_HI13Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI13Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI13Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI13Q_TXBD_DESA_H_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI13Q_TXBD_DESA_H_8814B)                              \\\n\t << BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B)\n#define BITS_HI13Q_TXBD_DESA_H_8814B                                           \\\n\t(BIT_MASK_HI13Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI13Q_TXBD_DESA_H_8814B(x)                                   \\\n\t((x) & (~BITS_HI13Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI13Q_TXBD_DESA_H_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B) &                          \\\n\t BIT_MASK_HI13Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI13Q_TXBD_DESA_H_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI13Q_TXBD_DESA_H_8814B(x) | BIT_HI13Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI14Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI14Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI14Q_TXBD_DESA_L_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI14Q_TXBD_DESA_L_8814B)                              \\\n\t << BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B)\n#define BITS_HI14Q_TXBD_DESA_L_8814B                                           \\\n\t(BIT_MASK_HI14Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI14Q_TXBD_DESA_L_8814B(x)                                   \\\n\t((x) & (~BITS_HI14Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI14Q_TXBD_DESA_L_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B) &                          \\\n\t BIT_MASK_HI14Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI14Q_TXBD_DESA_L_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI14Q_TXBD_DESA_L_8814B(x) | BIT_HI14Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI14Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI14Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI14Q_TXBD_DESA_H_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI14Q_TXBD_DESA_H_8814B)                              \\\n\t << BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B)\n#define BITS_HI14Q_TXBD_DESA_H_8814B                                           \\\n\t(BIT_MASK_HI14Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI14Q_TXBD_DESA_H_8814B(x)                                   \\\n\t((x) & (~BITS_HI14Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI14Q_TXBD_DESA_H_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B) &                          \\\n\t BIT_MASK_HI14Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI14Q_TXBD_DESA_H_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI14Q_TXBD_DESA_H_8814B(x) | BIT_HI14Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI15Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI15Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI15Q_TXBD_DESA_L_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI15Q_TXBD_DESA_L_8814B)                              \\\n\t << BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B)\n#define BITS_HI15Q_TXBD_DESA_L_8814B                                           \\\n\t(BIT_MASK_HI15Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI15Q_TXBD_DESA_L_8814B(x)                                   \\\n\t((x) & (~BITS_HI15Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI15Q_TXBD_DESA_L_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B) &                          \\\n\t BIT_MASK_HI15Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI15Q_TXBD_DESA_L_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI15Q_TXBD_DESA_L_8814B(x) | BIT_HI15Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI15Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI15Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI15Q_TXBD_DESA_H_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI15Q_TXBD_DESA_H_8814B)                              \\\n\t << BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B)\n#define BITS_HI15Q_TXBD_DESA_H_8814B                                           \\\n\t(BIT_MASK_HI15Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI15Q_TXBD_DESA_H_8814B(x)                                   \\\n\t((x) & (~BITS_HI15Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI15Q_TXBD_DESA_H_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B) &                          \\\n\t BIT_MASK_HI15Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI15Q_TXBD_DESA_H_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI15Q_TXBD_DESA_H_8814B(x) | BIT_HI15Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI16Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI16Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI16Q_TXBD_DESA_L_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI16Q_TXBD_DESA_L_8814B)                              \\\n\t << BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B)\n#define BITS_HI16Q_TXBD_DESA_L_8814B                                           \\\n\t(BIT_MASK_HI16Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI16Q_TXBD_DESA_L_8814B(x)                                   \\\n\t((x) & (~BITS_HI16Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI16Q_TXBD_DESA_L_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B) &                          \\\n\t BIT_MASK_HI16Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI16Q_TXBD_DESA_L_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI16Q_TXBD_DESA_L_8814B(x) | BIT_HI16Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI16Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI16Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI16Q_TXBD_DESA_H_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI16Q_TXBD_DESA_H_8814B)                              \\\n\t << BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B)\n#define BITS_HI16Q_TXBD_DESA_H_8814B                                           \\\n\t(BIT_MASK_HI16Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI16Q_TXBD_DESA_H_8814B(x)                                   \\\n\t((x) & (~BITS_HI16Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI16Q_TXBD_DESA_H_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B) &                          \\\n\t BIT_MASK_HI16Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI16Q_TXBD_DESA_H_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI16Q_TXBD_DESA_H_8814B(x) | BIT_HI16Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI17Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI17Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI17Q_TXBD_DESA_L_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI17Q_TXBD_DESA_L_8814B)                              \\\n\t << BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B)\n#define BITS_HI17Q_TXBD_DESA_L_8814B                                           \\\n\t(BIT_MASK_HI17Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI17Q_TXBD_DESA_L_8814B(x)                                   \\\n\t((x) & (~BITS_HI17Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI17Q_TXBD_DESA_L_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B) &                          \\\n\t BIT_MASK_HI17Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI17Q_TXBD_DESA_L_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI17Q_TXBD_DESA_L_8814B(x) | BIT_HI17Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI17Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI17Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI17Q_TXBD_DESA_H_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI17Q_TXBD_DESA_H_8814B)                              \\\n\t << BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B)\n#define BITS_HI17Q_TXBD_DESA_H_8814B                                           \\\n\t(BIT_MASK_HI17Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI17Q_TXBD_DESA_H_8814B(x)                                   \\\n\t((x) & (~BITS_HI17Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI17Q_TXBD_DESA_H_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B) &                          \\\n\t BIT_MASK_HI17Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI17Q_TXBD_DESA_H_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI17Q_TXBD_DESA_H_8814B(x) | BIT_HI17Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI18Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI18Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI18Q_TXBD_DESA_L_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI18Q_TXBD_DESA_L_8814B)                              \\\n\t << BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B)\n#define BITS_HI18Q_TXBD_DESA_L_8814B                                           \\\n\t(BIT_MASK_HI18Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI18Q_TXBD_DESA_L_8814B(x)                                   \\\n\t((x) & (~BITS_HI18Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI18Q_TXBD_DESA_L_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B) &                          \\\n\t BIT_MASK_HI18Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI18Q_TXBD_DESA_L_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI18Q_TXBD_DESA_L_8814B(x) | BIT_HI18Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI18Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI18Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI18Q_TXBD_DESA_H_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI18Q_TXBD_DESA_H_8814B)                              \\\n\t << BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B)\n#define BITS_HI18Q_TXBD_DESA_H_8814B                                           \\\n\t(BIT_MASK_HI18Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI18Q_TXBD_DESA_H_8814B(x)                                   \\\n\t((x) & (~BITS_HI18Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI18Q_TXBD_DESA_H_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B) &                          \\\n\t BIT_MASK_HI18Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI18Q_TXBD_DESA_H_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI18Q_TXBD_DESA_H_8814B(x) | BIT_HI18Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_HI19Q_TXBD_DESA_L_8814B */\n\n#define BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B 0\n#define BIT_MASK_HI19Q_TXBD_DESA_L_8814B 0xffffffffL\n#define BIT_HI19Q_TXBD_DESA_L_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI19Q_TXBD_DESA_L_8814B)                              \\\n\t << BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B)\n#define BITS_HI19Q_TXBD_DESA_L_8814B                                           \\\n\t(BIT_MASK_HI19Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B)\n#define BIT_CLEAR_HI19Q_TXBD_DESA_L_8814B(x)                                   \\\n\t((x) & (~BITS_HI19Q_TXBD_DESA_L_8814B))\n#define BIT_GET_HI19Q_TXBD_DESA_L_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B) &                          \\\n\t BIT_MASK_HI19Q_TXBD_DESA_L_8814B)\n#define BIT_SET_HI19Q_TXBD_DESA_L_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI19Q_TXBD_DESA_L_8814B(x) | BIT_HI19Q_TXBD_DESA_L_8814B(v))\n\n/* 2 REG_HI19Q_TXBD_DESA_H_8814B */\n\n#define BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B 0\n#define BIT_MASK_HI19Q_TXBD_DESA_H_8814B 0xffffffffL\n#define BIT_HI19Q_TXBD_DESA_H_8814B(x)                                         \\\n\t(((x) & BIT_MASK_HI19Q_TXBD_DESA_H_8814B)                              \\\n\t << BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B)\n#define BITS_HI19Q_TXBD_DESA_H_8814B                                           \\\n\t(BIT_MASK_HI19Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B)\n#define BIT_CLEAR_HI19Q_TXBD_DESA_H_8814B(x)                                   \\\n\t((x) & (~BITS_HI19Q_TXBD_DESA_H_8814B))\n#define BIT_GET_HI19Q_TXBD_DESA_H_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B) &                          \\\n\t BIT_MASK_HI19Q_TXBD_DESA_H_8814B)\n#define BIT_SET_HI19Q_TXBD_DESA_H_8814B(x, v)                                  \\\n\t(BIT_CLEAR_HI19Q_TXBD_DESA_H_8814B(x) | BIT_HI19Q_TXBD_DESA_H_8814B(v))\n\n/* 2 REG_BD_RWPTR_CLR6_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_CLR_P0HI19Q_HW_IDX_8814B BIT(25)\n#define BIT_CLR_P0HI18Q_HW_IDX_8814B BIT(24)\n#define BIT_CLR_P0HI17Q_HW_IDX_8814B BIT(23)\n#define BIT_CLR_P0HI16Q_HW_IDX_8814B BIT(22)\n\n/* 2 REG_NOT_VALID_8814B */\n#define BIT_CLR_P0HI19Q_HOST_IDX_8814B BIT(9)\n#define BIT_CLR_P0HI18Q_HOST_IDX_8814B BIT(8)\n#define BIT_CLR_P0HI17Q_HOST_IDX_8814B BIT(7)\n#define BIT_CLR_P0HI16Q_HOST_IDX_8814B BIT(6)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_P0HI16Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI16Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI16Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI16Q_HW_IDX_8814B(x)                                            \\\n\t(((x) & BIT_MASK_P0HI16Q_HW_IDX_8814B)                                 \\\n\t << BIT_SHIFT_P0HI16Q_HW_IDX_8814B)\n#define BITS_P0HI16Q_HW_IDX_8814B                                              \\\n\t(BIT_MASK_P0HI16Q_HW_IDX_8814B << BIT_SHIFT_P0HI16Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI16Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI16Q_HW_IDX_8814B))\n#define BIT_GET_P0HI16Q_HW_IDX_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_P0HI16Q_HW_IDX_8814B) &                             \\\n\t BIT_MASK_P0HI16Q_HW_IDX_8814B)\n#define BIT_SET_P0HI16Q_HW_IDX_8814B(x, v)                                     \\\n\t(BIT_CLEAR_P0HI16Q_HW_IDX_8814B(x) | BIT_P0HI16Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI16Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI16Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI16Q_HOST_IDX_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI16Q_HOST_IDX_8814B)                               \\\n\t << BIT_SHIFT_P0HI16Q_HOST_IDX_8814B)\n#define BITS_P0HI16Q_HOST_IDX_8814B                                            \\\n\t(BIT_MASK_P0HI16Q_HOST_IDX_8814B << BIT_SHIFT_P0HI16Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI16Q_HOST_IDX_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI16Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI16Q_HOST_IDX_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI16Q_HOST_IDX_8814B) &                           \\\n\t BIT_MASK_P0HI16Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI16Q_HOST_IDX_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI16Q_HOST_IDX_8814B(x) | BIT_P0HI16Q_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI17Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI17Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI17Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI17Q_HW_IDX_8814B(x)                                            \\\n\t(((x) & BIT_MASK_P0HI17Q_HW_IDX_8814B)                                 \\\n\t << BIT_SHIFT_P0HI17Q_HW_IDX_8814B)\n#define BITS_P0HI17Q_HW_IDX_8814B                                              \\\n\t(BIT_MASK_P0HI17Q_HW_IDX_8814B << BIT_SHIFT_P0HI17Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI17Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI17Q_HW_IDX_8814B))\n#define BIT_GET_P0HI17Q_HW_IDX_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_P0HI17Q_HW_IDX_8814B) &                             \\\n\t BIT_MASK_P0HI17Q_HW_IDX_8814B)\n#define BIT_SET_P0HI17Q_HW_IDX_8814B(x, v)                                     \\\n\t(BIT_CLEAR_P0HI17Q_HW_IDX_8814B(x) | BIT_P0HI17Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI17Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI17Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI17Q_HOST_IDX_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI17Q_HOST_IDX_8814B)                               \\\n\t << BIT_SHIFT_P0HI17Q_HOST_IDX_8814B)\n#define BITS_P0HI17Q_HOST_IDX_8814B                                            \\\n\t(BIT_MASK_P0HI17Q_HOST_IDX_8814B << BIT_SHIFT_P0HI17Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI17Q_HOST_IDX_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI17Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI17Q_HOST_IDX_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI17Q_HOST_IDX_8814B) &                           \\\n\t BIT_MASK_P0HI17Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI17Q_HOST_IDX_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI17Q_HOST_IDX_8814B(x) | BIT_P0HI17Q_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI18Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI18Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI18Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI18Q_HW_IDX_8814B(x)                                            \\\n\t(((x) & BIT_MASK_P0HI18Q_HW_IDX_8814B)                                 \\\n\t << BIT_SHIFT_P0HI18Q_HW_IDX_8814B)\n#define BITS_P0HI18Q_HW_IDX_8814B                                              \\\n\t(BIT_MASK_P0HI18Q_HW_IDX_8814B << BIT_SHIFT_P0HI18Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI18Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI18Q_HW_IDX_8814B))\n#define BIT_GET_P0HI18Q_HW_IDX_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_P0HI18Q_HW_IDX_8814B) &                             \\\n\t BIT_MASK_P0HI18Q_HW_IDX_8814B)\n#define BIT_SET_P0HI18Q_HW_IDX_8814B(x, v)                                     \\\n\t(BIT_CLEAR_P0HI18Q_HW_IDX_8814B(x) | BIT_P0HI18Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI18Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI18Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI18Q_HOST_IDX_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI18Q_HOST_IDX_8814B)                               \\\n\t << BIT_SHIFT_P0HI18Q_HOST_IDX_8814B)\n#define BITS_P0HI18Q_HOST_IDX_8814B                                            \\\n\t(BIT_MASK_P0HI18Q_HOST_IDX_8814B << BIT_SHIFT_P0HI18Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI18Q_HOST_IDX_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI18Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI18Q_HOST_IDX_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI18Q_HOST_IDX_8814B) &                           \\\n\t BIT_MASK_P0HI18Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI18Q_HOST_IDX_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI18Q_HOST_IDX_8814B(x) | BIT_P0HI18Q_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI19Q_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_P0HI19Q_HW_IDX_8814B 16\n#define BIT_MASK_P0HI19Q_HW_IDX_8814B 0xfff\n#define BIT_P0HI19Q_HW_IDX_8814B(x)                                            \\\n\t(((x) & BIT_MASK_P0HI19Q_HW_IDX_8814B)                                 \\\n\t << BIT_SHIFT_P0HI19Q_HW_IDX_8814B)\n#define BITS_P0HI19Q_HW_IDX_8814B                                              \\\n\t(BIT_MASK_P0HI19Q_HW_IDX_8814B << BIT_SHIFT_P0HI19Q_HW_IDX_8814B)\n#define BIT_CLEAR_P0HI19Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI19Q_HW_IDX_8814B))\n#define BIT_GET_P0HI19Q_HW_IDX_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_P0HI19Q_HW_IDX_8814B) &                             \\\n\t BIT_MASK_P0HI19Q_HW_IDX_8814B)\n#define BIT_SET_P0HI19Q_HW_IDX_8814B(x, v)                                     \\\n\t(BIT_CLEAR_P0HI19Q_HW_IDX_8814B(x) | BIT_P0HI19Q_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_P0HI19Q_HOST_IDX_8814B 0\n#define BIT_MASK_P0HI19Q_HOST_IDX_8814B 0xfff\n#define BIT_P0HI19Q_HOST_IDX_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI19Q_HOST_IDX_8814B)                               \\\n\t << BIT_SHIFT_P0HI19Q_HOST_IDX_8814B)\n#define BITS_P0HI19Q_HOST_IDX_8814B                                            \\\n\t(BIT_MASK_P0HI19Q_HOST_IDX_8814B << BIT_SHIFT_P0HI19Q_HOST_IDX_8814B)\n#define BIT_CLEAR_P0HI19Q_HOST_IDX_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI19Q_HOST_IDX_8814B))\n#define BIT_GET_P0HI19Q_HOST_IDX_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI19Q_HOST_IDX_8814B) &                           \\\n\t BIT_MASK_P0HI19Q_HOST_IDX_8814B)\n#define BIT_SET_P0HI19Q_HOST_IDX_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI19Q_HOST_IDX_8814B(x) | BIT_P0HI19Q_HOST_IDX_8814B(v))\n\n/* 2 REG_P0HI16Q_HI17Q_TXBD_NUM_8814B */\n#define BIT_P0HI17Q_FLAG_8814B BIT(30)\n\n#define BIT_SHIFT_P0HI17Q_DESC_MODE_8814B 28\n#define BIT_MASK_P0HI17Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI17Q_DESC_MODE_8814B(x)                                         \\\n\t(((x) & BIT_MASK_P0HI17Q_DESC_MODE_8814B)                              \\\n\t << BIT_SHIFT_P0HI17Q_DESC_MODE_8814B)\n#define BITS_P0HI17Q_DESC_MODE_8814B                                           \\\n\t(BIT_MASK_P0HI17Q_DESC_MODE_8814B << BIT_SHIFT_P0HI17Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI17Q_DESC_MODE_8814B(x)                                   \\\n\t((x) & (~BITS_P0HI17Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI17Q_DESC_MODE_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_P0HI17Q_DESC_MODE_8814B) &                          \\\n\t BIT_MASK_P0HI17Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI17Q_DESC_MODE_8814B(x, v)                                  \\\n\t(BIT_CLEAR_P0HI17Q_DESC_MODE_8814B(x) | BIT_P0HI17Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI17Q_DESC_NUM_8814B 16\n#define BIT_MASK_P0HI17Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI17Q_DESC_NUM_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI17Q_DESC_NUM_8814B)                               \\\n\t << BIT_SHIFT_P0HI17Q_DESC_NUM_8814B)\n#define BITS_P0HI17Q_DESC_NUM_8814B                                            \\\n\t(BIT_MASK_P0HI17Q_DESC_NUM_8814B << BIT_SHIFT_P0HI17Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI17Q_DESC_NUM_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI17Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI17Q_DESC_NUM_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI17Q_DESC_NUM_8814B) &                           \\\n\t BIT_MASK_P0HI17Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI17Q_DESC_NUM_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI17Q_DESC_NUM_8814B(x) | BIT_P0HI17Q_DESC_NUM_8814B(v))\n\n#define BIT_P0HI16Q_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_P0HI16Q_DESC_MODE_8814B 12\n#define BIT_MASK_P0HI16Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI16Q_DESC_MODE_8814B(x)                                         \\\n\t(((x) & BIT_MASK_P0HI16Q_DESC_MODE_8814B)                              \\\n\t << BIT_SHIFT_P0HI16Q_DESC_MODE_8814B)\n#define BITS_P0HI16Q_DESC_MODE_8814B                                           \\\n\t(BIT_MASK_P0HI16Q_DESC_MODE_8814B << BIT_SHIFT_P0HI16Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI16Q_DESC_MODE_8814B(x)                                   \\\n\t((x) & (~BITS_P0HI16Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI16Q_DESC_MODE_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_P0HI16Q_DESC_MODE_8814B) &                          \\\n\t BIT_MASK_P0HI16Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI16Q_DESC_MODE_8814B(x, v)                                  \\\n\t(BIT_CLEAR_P0HI16Q_DESC_MODE_8814B(x) | BIT_P0HI16Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI16Q_DESC_NUM_8814B 0\n#define BIT_MASK_P0HI16Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI16Q_DESC_NUM_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI16Q_DESC_NUM_8814B)                               \\\n\t << BIT_SHIFT_P0HI16Q_DESC_NUM_8814B)\n#define BITS_P0HI16Q_DESC_NUM_8814B                                            \\\n\t(BIT_MASK_P0HI16Q_DESC_NUM_8814B << BIT_SHIFT_P0HI16Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI16Q_DESC_NUM_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI16Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI16Q_DESC_NUM_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI16Q_DESC_NUM_8814B) &                           \\\n\t BIT_MASK_P0HI16Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI16Q_DESC_NUM_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI16Q_DESC_NUM_8814B(x) | BIT_P0HI16Q_DESC_NUM_8814B(v))\n\n/* 2 REG_P0HI18Q_HI19Q_TXBD_NUM_8814B */\n#define BIT_P0HI19Q_FLAG_8814B BIT(30)\n\n#define BIT_SHIFT_P0HI19Q_DESC_MODE_8814B 28\n#define BIT_MASK_P0HI19Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI19Q_DESC_MODE_8814B(x)                                         \\\n\t(((x) & BIT_MASK_P0HI19Q_DESC_MODE_8814B)                              \\\n\t << BIT_SHIFT_P0HI19Q_DESC_MODE_8814B)\n#define BITS_P0HI19Q_DESC_MODE_8814B                                           \\\n\t(BIT_MASK_P0HI19Q_DESC_MODE_8814B << BIT_SHIFT_P0HI19Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI19Q_DESC_MODE_8814B(x)                                   \\\n\t((x) & (~BITS_P0HI19Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI19Q_DESC_MODE_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_P0HI19Q_DESC_MODE_8814B) &                          \\\n\t BIT_MASK_P0HI19Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI19Q_DESC_MODE_8814B(x, v)                                  \\\n\t(BIT_CLEAR_P0HI19Q_DESC_MODE_8814B(x) | BIT_P0HI19Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI19Q_DESC_NUM_8814B 16\n#define BIT_MASK_P0HI19Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI19Q_DESC_NUM_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI19Q_DESC_NUM_8814B)                               \\\n\t << BIT_SHIFT_P0HI19Q_DESC_NUM_8814B)\n#define BITS_P0HI19Q_DESC_NUM_8814B                                            \\\n\t(BIT_MASK_P0HI19Q_DESC_NUM_8814B << BIT_SHIFT_P0HI19Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI19Q_DESC_NUM_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI19Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI19Q_DESC_NUM_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI19Q_DESC_NUM_8814B) &                           \\\n\t BIT_MASK_P0HI19Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI19Q_DESC_NUM_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI19Q_DESC_NUM_8814B(x) | BIT_P0HI19Q_DESC_NUM_8814B(v))\n\n#define BIT_P0HI18Q_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_P0HI18Q_DESC_MODE_8814B 12\n#define BIT_MASK_P0HI18Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI18Q_DESC_MODE_8814B(x)                                         \\\n\t(((x) & BIT_MASK_P0HI18Q_DESC_MODE_8814B)                              \\\n\t << BIT_SHIFT_P0HI18Q_DESC_MODE_8814B)\n#define BITS_P0HI18Q_DESC_MODE_8814B                                           \\\n\t(BIT_MASK_P0HI18Q_DESC_MODE_8814B << BIT_SHIFT_P0HI18Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI18Q_DESC_MODE_8814B(x)                                   \\\n\t((x) & (~BITS_P0HI18Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI18Q_DESC_MODE_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_P0HI18Q_DESC_MODE_8814B) &                          \\\n\t BIT_MASK_P0HI18Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI18Q_DESC_MODE_8814B(x, v)                                  \\\n\t(BIT_CLEAR_P0HI18Q_DESC_MODE_8814B(x) | BIT_P0HI18Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI18Q_DESC_NUM_8814B 0\n#define BIT_MASK_P0HI18Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI18Q_DESC_NUM_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI18Q_DESC_NUM_8814B)                               \\\n\t << BIT_SHIFT_P0HI18Q_DESC_NUM_8814B)\n#define BITS_P0HI18Q_DESC_NUM_8814B                                            \\\n\t(BIT_MASK_P0HI18Q_DESC_NUM_8814B << BIT_SHIFT_P0HI18Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI18Q_DESC_NUM_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI18Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI18Q_DESC_NUM_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI18Q_DESC_NUM_8814B) &                           \\\n\t BIT_MASK_P0HI18Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI18Q_DESC_NUM_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI18Q_DESC_NUM_8814B(x) | BIT_P0HI18Q_DESC_NUM_8814B(v))\n\n/* 2 REG_PCIE_HISR0_8814B */\n#define BIT_PSTIMER_2_8814B BIT(31)\n#define BIT_PSTIMER_1_8814B BIT(30)\n#define BIT_PSTIMER_0_8814B BIT(29)\n#define BIT_GTINT4_8814B BIT(28)\n#define BIT_GTINT3_8814B BIT(27)\n#define BIT_TXBCN0ERR_8814B BIT(26)\n#define BIT_TXBCN0OK_8814B BIT(25)\n#define BIT_TSF_BIT32_TOGGLE_8814B BIT(24)\n#define BIT_TXDMA_START_INT_8814B BIT(23)\n#define BIT_TXDMA_STOP_INT_8814B BIT(22)\n#define BIT_HISR7_IND_8814B BIT(21)\n#define BIT_BCNDMAINT0_8814B BIT(20)\n#define BIT_HISR6_IND_8814B BIT(19)\n#define BIT_HISR5_IND_8814B BIT(18)\n#define BIT_HISR4_IND_8814B BIT(17)\n#define BIT_BCNDERR0_8814B BIT(16)\n#define BIT_HSISR_IND_ON_INT_8814B BIT(15)\n#define BIT_HISR3_IND_8814B BIT(14)\n#define BIT_HISR2_IND_8814B BIT(13)\n#define BIT_HISR1_IND_8814B BIT(11)\n#define BIT_C2HCMD_8814B BIT(10)\n#define BIT_CPWM2_8814B BIT(9)\n#define BIT_CPWM_8814B BIT(8)\n#define BIT_TXDMAOK_CHANNEL15_8814B BIT(7)\n#define BIT_TXDMAOK_CHANNEL14_8814B BIT(6)\n#define BIT_TXDMAOK_CHANNEL3_8814B BIT(5)\n#define BIT_TXDMAOK_CHANNEL2_8814B BIT(4)\n#define BIT_TXDMAOK_CHANNEL1_8814B BIT(3)\n#define BIT_TXDMAOK_CHANNEL0_8814B BIT(2)\n#define BIT_RDU_8814B BIT(1)\n#define BIT_RXOK_8814B BIT(0)\n\n/* 2 REG_PCIE_HISR1_8814B */\n#define BIT_PRE_TX_ERR_INT_8814B BIT(31)\n#define BIT_TXFIFO_TH_INT_8814B BIT(30)\n#define BIT_BTON_STS_UPDATE_INT_8814B BIT(29)\n#define BIT_BCNDMAINT7_8814B BIT(27)\n#define BIT_BCNDMAINT6_8814B BIT(26)\n#define BIT_BCNDMAINT5_8814B BIT(25)\n#define BIT_BCNDMAINT4_8814B BIT(24)\n#define BIT_BCNDMAINT3_8814B BIT(23)\n#define BIT_BCNDMAINT2_8814B BIT(22)\n#define BIT_BCNDMAINT1_8814B BIT(21)\n#define BIT_BCNDERR7_8814B BIT(20)\n#define BIT_BCNDERR6_8814B BIT(19)\n#define BIT_BCNDERR5_8814B BIT(18)\n#define BIT_BCNDERR4_8814B BIT(17)\n#define BIT_BCNDERR3_8814B BIT(16)\n#define BIT_BCNDERR2_8814B BIT(15)\n#define BIT_BCNDERR1_8814B BIT(14)\n#define BIT_ATIMEND_8814B BIT(12)\n#define BIT_TXERR_INT_8814B BIT(11)\n#define BIT_RXERR_INT_8814B BIT(10)\n#define BIT_TXFOVW_8814B BIT(9)\n#define BIT_FOVW_8814B BIT(8)\n#define BIT_CPU_MGQ_EARLY_INT_8814B BIT(6)\n#define BIT_CPU_MGQ_TXDONE_8814B BIT(5)\n#define BIT_PSTIMER_5_8814B BIT(4)\n#define BIT_PSTIMER_4_8814B BIT(3)\n#define BIT_PSTIMER_3_8814B BIT(2)\n#define BIT_CPUMGQ_TX_TIMER_8814B BIT(1)\n#define BIT_BB_STOPRX_INT_8814B BIT(0)\n\n/* 2 REG_P0HI8Q_HI9Q_TXBD_NUM_8814B */\n#define BIT_P0HI9Q_FLAG_8814B BIT(30)\n\n#define BIT_SHIFT_P0HI9Q_DESC_MODE_8814B 28\n#define BIT_MASK_P0HI9Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI9Q_DESC_MODE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI9Q_DESC_MODE_8814B)                               \\\n\t << BIT_SHIFT_P0HI9Q_DESC_MODE_8814B)\n#define BITS_P0HI9Q_DESC_MODE_8814B                                            \\\n\t(BIT_MASK_P0HI9Q_DESC_MODE_8814B << BIT_SHIFT_P0HI9Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI9Q_DESC_MODE_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI9Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI9Q_DESC_MODE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI9Q_DESC_MODE_8814B) &                           \\\n\t BIT_MASK_P0HI9Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI9Q_DESC_MODE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI9Q_DESC_MODE_8814B(x) | BIT_P0HI9Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI9Q_DESC_NUM_8814B 16\n#define BIT_MASK_P0HI9Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI9Q_DESC_NUM_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI9Q_DESC_NUM_8814B)                                \\\n\t << BIT_SHIFT_P0HI9Q_DESC_NUM_8814B)\n#define BITS_P0HI9Q_DESC_NUM_8814B                                             \\\n\t(BIT_MASK_P0HI9Q_DESC_NUM_8814B << BIT_SHIFT_P0HI9Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI9Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI9Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI9Q_DESC_NUM_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI9Q_DESC_NUM_8814B) &                            \\\n\t BIT_MASK_P0HI9Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI9Q_DESC_NUM_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI9Q_DESC_NUM_8814B(x) | BIT_P0HI9Q_DESC_NUM_8814B(v))\n\n#define BIT_P0HI8Q_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_P0HI8Q_DESC_MODE_8814B 12\n#define BIT_MASK_P0HI8Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI8Q_DESC_MODE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI8Q_DESC_MODE_8814B)                               \\\n\t << BIT_SHIFT_P0HI8Q_DESC_MODE_8814B)\n#define BITS_P0HI8Q_DESC_MODE_8814B                                            \\\n\t(BIT_MASK_P0HI8Q_DESC_MODE_8814B << BIT_SHIFT_P0HI8Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI8Q_DESC_MODE_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI8Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI8Q_DESC_MODE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI8Q_DESC_MODE_8814B) &                           \\\n\t BIT_MASK_P0HI8Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI8Q_DESC_MODE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI8Q_DESC_MODE_8814B(x) | BIT_P0HI8Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI8Q_DESC_NUM_8814B 0\n#define BIT_MASK_P0HI8Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI8Q_DESC_NUM_8814B(x)                                           \\\n\t(((x) & BIT_MASK_P0HI8Q_DESC_NUM_8814B)                                \\\n\t << BIT_SHIFT_P0HI8Q_DESC_NUM_8814B)\n#define BITS_P0HI8Q_DESC_NUM_8814B                                             \\\n\t(BIT_MASK_P0HI8Q_DESC_NUM_8814B << BIT_SHIFT_P0HI8Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI8Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI8Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI8Q_DESC_NUM_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_P0HI8Q_DESC_NUM_8814B) &                            \\\n\t BIT_MASK_P0HI8Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI8Q_DESC_NUM_8814B(x, v)                                    \\\n\t(BIT_CLEAR_P0HI8Q_DESC_NUM_8814B(x) | BIT_P0HI8Q_DESC_NUM_8814B(v))\n\n/* 2 REG_P0HI10Q_HI11Q_TXBD_NUM_8814B */\n#define BIT_P0HI11Q_FLAG_8814B BIT(30)\n\n#define BIT_SHIFT_P0HI11Q_DESC_MODE_8814B 28\n#define BIT_MASK_P0HI11Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI11Q_DESC_MODE_8814B(x)                                         \\\n\t(((x) & BIT_MASK_P0HI11Q_DESC_MODE_8814B)                              \\\n\t << BIT_SHIFT_P0HI11Q_DESC_MODE_8814B)\n#define BITS_P0HI11Q_DESC_MODE_8814B                                           \\\n\t(BIT_MASK_P0HI11Q_DESC_MODE_8814B << BIT_SHIFT_P0HI11Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI11Q_DESC_MODE_8814B(x)                                   \\\n\t((x) & (~BITS_P0HI11Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI11Q_DESC_MODE_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_P0HI11Q_DESC_MODE_8814B) &                          \\\n\t BIT_MASK_P0HI11Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI11Q_DESC_MODE_8814B(x, v)                                  \\\n\t(BIT_CLEAR_P0HI11Q_DESC_MODE_8814B(x) | BIT_P0HI11Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI11Q_DESC_NUM_8814B 16\n#define BIT_MASK_P0HI11Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI11Q_DESC_NUM_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI11Q_DESC_NUM_8814B)                               \\\n\t << BIT_SHIFT_P0HI11Q_DESC_NUM_8814B)\n#define BITS_P0HI11Q_DESC_NUM_8814B                                            \\\n\t(BIT_MASK_P0HI11Q_DESC_NUM_8814B << BIT_SHIFT_P0HI11Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI11Q_DESC_NUM_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI11Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI11Q_DESC_NUM_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI11Q_DESC_NUM_8814B) &                           \\\n\t BIT_MASK_P0HI11Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI11Q_DESC_NUM_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI11Q_DESC_NUM_8814B(x) | BIT_P0HI11Q_DESC_NUM_8814B(v))\n\n#define BIT_P0HI10Q_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_P0HI10Q_DESC_MODE_8814B 12\n#define BIT_MASK_P0HI10Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI10Q_DESC_MODE_8814B(x)                                         \\\n\t(((x) & BIT_MASK_P0HI10Q_DESC_MODE_8814B)                              \\\n\t << BIT_SHIFT_P0HI10Q_DESC_MODE_8814B)\n#define BITS_P0HI10Q_DESC_MODE_8814B                                           \\\n\t(BIT_MASK_P0HI10Q_DESC_MODE_8814B << BIT_SHIFT_P0HI10Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI10Q_DESC_MODE_8814B(x)                                   \\\n\t((x) & (~BITS_P0HI10Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI10Q_DESC_MODE_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_P0HI10Q_DESC_MODE_8814B) &                          \\\n\t BIT_MASK_P0HI10Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI10Q_DESC_MODE_8814B(x, v)                                  \\\n\t(BIT_CLEAR_P0HI10Q_DESC_MODE_8814B(x) | BIT_P0HI10Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI10Q_DESC_NUM_8814B 0\n#define BIT_MASK_P0HI10Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI10Q_DESC_NUM_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI10Q_DESC_NUM_8814B)                               \\\n\t << BIT_SHIFT_P0HI10Q_DESC_NUM_8814B)\n#define BITS_P0HI10Q_DESC_NUM_8814B                                            \\\n\t(BIT_MASK_P0HI10Q_DESC_NUM_8814B << BIT_SHIFT_P0HI10Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI10Q_DESC_NUM_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI10Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI10Q_DESC_NUM_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI10Q_DESC_NUM_8814B) &                           \\\n\t BIT_MASK_P0HI10Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI10Q_DESC_NUM_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI10Q_DESC_NUM_8814B(x) | BIT_P0HI10Q_DESC_NUM_8814B(v))\n\n/* 2 REG_P0HI12Q_HI13Q_TXBD_NUM_8814B */\n#define BIT_P0HI13Q_FLAG_8814B BIT(30)\n\n#define BIT_SHIFT_P0HI13Q_DESC_MODE_8814B 28\n#define BIT_MASK_P0HI13Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI13Q_DESC_MODE_8814B(x)                                         \\\n\t(((x) & BIT_MASK_P0HI13Q_DESC_MODE_8814B)                              \\\n\t << BIT_SHIFT_P0HI13Q_DESC_MODE_8814B)\n#define BITS_P0HI13Q_DESC_MODE_8814B                                           \\\n\t(BIT_MASK_P0HI13Q_DESC_MODE_8814B << BIT_SHIFT_P0HI13Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI13Q_DESC_MODE_8814B(x)                                   \\\n\t((x) & (~BITS_P0HI13Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI13Q_DESC_MODE_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_P0HI13Q_DESC_MODE_8814B) &                          \\\n\t BIT_MASK_P0HI13Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI13Q_DESC_MODE_8814B(x, v)                                  \\\n\t(BIT_CLEAR_P0HI13Q_DESC_MODE_8814B(x) | BIT_P0HI13Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI13Q_DESC_NUM_8814B 16\n#define BIT_MASK_P0HI13Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI13Q_DESC_NUM_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI13Q_DESC_NUM_8814B)                               \\\n\t << BIT_SHIFT_P0HI13Q_DESC_NUM_8814B)\n#define BITS_P0HI13Q_DESC_NUM_8814B                                            \\\n\t(BIT_MASK_P0HI13Q_DESC_NUM_8814B << BIT_SHIFT_P0HI13Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI13Q_DESC_NUM_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI13Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI13Q_DESC_NUM_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI13Q_DESC_NUM_8814B) &                           \\\n\t BIT_MASK_P0HI13Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI13Q_DESC_NUM_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI13Q_DESC_NUM_8814B(x) | BIT_P0HI13Q_DESC_NUM_8814B(v))\n\n#define BIT_P0HI12Q_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_P0HI12Q_DESC_MODE_8814B 12\n#define BIT_MASK_P0HI12Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI12Q_DESC_MODE_8814B(x)                                         \\\n\t(((x) & BIT_MASK_P0HI12Q_DESC_MODE_8814B)                              \\\n\t << BIT_SHIFT_P0HI12Q_DESC_MODE_8814B)\n#define BITS_P0HI12Q_DESC_MODE_8814B                                           \\\n\t(BIT_MASK_P0HI12Q_DESC_MODE_8814B << BIT_SHIFT_P0HI12Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI12Q_DESC_MODE_8814B(x)                                   \\\n\t((x) & (~BITS_P0HI12Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI12Q_DESC_MODE_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_P0HI12Q_DESC_MODE_8814B) &                          \\\n\t BIT_MASK_P0HI12Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI12Q_DESC_MODE_8814B(x, v)                                  \\\n\t(BIT_CLEAR_P0HI12Q_DESC_MODE_8814B(x) | BIT_P0HI12Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI12Q_DESC_NUM_8814B 0\n#define BIT_MASK_P0HI12Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI12Q_DESC_NUM_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI12Q_DESC_NUM_8814B)                               \\\n\t << BIT_SHIFT_P0HI12Q_DESC_NUM_8814B)\n#define BITS_P0HI12Q_DESC_NUM_8814B                                            \\\n\t(BIT_MASK_P0HI12Q_DESC_NUM_8814B << BIT_SHIFT_P0HI12Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI12Q_DESC_NUM_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI12Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI12Q_DESC_NUM_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI12Q_DESC_NUM_8814B) &                           \\\n\t BIT_MASK_P0HI12Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI12Q_DESC_NUM_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI12Q_DESC_NUM_8814B(x) | BIT_P0HI12Q_DESC_NUM_8814B(v))\n\n/* 2 REG_P0HI14Q_HI15Q_TXBD_NUM_8814B */\n#define BIT_P0HI15Q_FLAG_8814B BIT(30)\n\n#define BIT_SHIFT_P0HI15Q_DESC_MODE_8814B 28\n#define BIT_MASK_P0HI15Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI15Q_DESC_MODE_8814B(x)                                         \\\n\t(((x) & BIT_MASK_P0HI15Q_DESC_MODE_8814B)                              \\\n\t << BIT_SHIFT_P0HI15Q_DESC_MODE_8814B)\n#define BITS_P0HI15Q_DESC_MODE_8814B                                           \\\n\t(BIT_MASK_P0HI15Q_DESC_MODE_8814B << BIT_SHIFT_P0HI15Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI15Q_DESC_MODE_8814B(x)                                   \\\n\t((x) & (~BITS_P0HI15Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI15Q_DESC_MODE_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_P0HI15Q_DESC_MODE_8814B) &                          \\\n\t BIT_MASK_P0HI15Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI15Q_DESC_MODE_8814B(x, v)                                  \\\n\t(BIT_CLEAR_P0HI15Q_DESC_MODE_8814B(x) | BIT_P0HI15Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI15Q_DESC_NUM_8814B 16\n#define BIT_MASK_P0HI15Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI15Q_DESC_NUM_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI15Q_DESC_NUM_8814B)                               \\\n\t << BIT_SHIFT_P0HI15Q_DESC_NUM_8814B)\n#define BITS_P0HI15Q_DESC_NUM_8814B                                            \\\n\t(BIT_MASK_P0HI15Q_DESC_NUM_8814B << BIT_SHIFT_P0HI15Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI15Q_DESC_NUM_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI15Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI15Q_DESC_NUM_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI15Q_DESC_NUM_8814B) &                           \\\n\t BIT_MASK_P0HI15Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI15Q_DESC_NUM_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI15Q_DESC_NUM_8814B(x) | BIT_P0HI15Q_DESC_NUM_8814B(v))\n\n#define BIT_P0HI14Q_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_P0HI14Q_DESC_MODE_8814B 12\n#define BIT_MASK_P0HI14Q_DESC_MODE_8814B 0x3\n#define BIT_P0HI14Q_DESC_MODE_8814B(x)                                         \\\n\t(((x) & BIT_MASK_P0HI14Q_DESC_MODE_8814B)                              \\\n\t << BIT_SHIFT_P0HI14Q_DESC_MODE_8814B)\n#define BITS_P0HI14Q_DESC_MODE_8814B                                           \\\n\t(BIT_MASK_P0HI14Q_DESC_MODE_8814B << BIT_SHIFT_P0HI14Q_DESC_MODE_8814B)\n#define BIT_CLEAR_P0HI14Q_DESC_MODE_8814B(x)                                   \\\n\t((x) & (~BITS_P0HI14Q_DESC_MODE_8814B))\n#define BIT_GET_P0HI14Q_DESC_MODE_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_P0HI14Q_DESC_MODE_8814B) &                          \\\n\t BIT_MASK_P0HI14Q_DESC_MODE_8814B)\n#define BIT_SET_P0HI14Q_DESC_MODE_8814B(x, v)                                  \\\n\t(BIT_CLEAR_P0HI14Q_DESC_MODE_8814B(x) | BIT_P0HI14Q_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_P0HI14Q_DESC_NUM_8814B 0\n#define BIT_MASK_P0HI14Q_DESC_NUM_8814B 0xfff\n#define BIT_P0HI14Q_DESC_NUM_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P0HI14Q_DESC_NUM_8814B)                               \\\n\t << BIT_SHIFT_P0HI14Q_DESC_NUM_8814B)\n#define BITS_P0HI14Q_DESC_NUM_8814B                                            \\\n\t(BIT_MASK_P0HI14Q_DESC_NUM_8814B << BIT_SHIFT_P0HI14Q_DESC_NUM_8814B)\n#define BIT_CLEAR_P0HI14Q_DESC_NUM_8814B(x)                                    \\\n\t((x) & (~BITS_P0HI14Q_DESC_NUM_8814B))\n#define BIT_GET_P0HI14Q_DESC_NUM_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P0HI14Q_DESC_NUM_8814B) &                           \\\n\t BIT_MASK_P0HI14Q_DESC_NUM_8814B)\n#define BIT_SET_P0HI14Q_DESC_NUM_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P0HI14Q_DESC_NUM_8814B(x) | BIT_P0HI14Q_DESC_NUM_8814B(v))\n\n/* 2 REG_ACH6_ACH7_TXBD_NUM_8814B */\n#define BIT_PCIE_ACH7_FLAG_8814B BIT(30)\n\n#define BIT_SHIFT_ACH7_DESC_MODE_8814B 28\n#define BIT_MASK_ACH7_DESC_MODE_8814B 0x3\n#define BIT_ACH7_DESC_MODE_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACH7_DESC_MODE_8814B)                                 \\\n\t << BIT_SHIFT_ACH7_DESC_MODE_8814B)\n#define BITS_ACH7_DESC_MODE_8814B                                              \\\n\t(BIT_MASK_ACH7_DESC_MODE_8814B << BIT_SHIFT_ACH7_DESC_MODE_8814B)\n#define BIT_CLEAR_ACH7_DESC_MODE_8814B(x) ((x) & (~BITS_ACH7_DESC_MODE_8814B))\n#define BIT_GET_ACH7_DESC_MODE_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACH7_DESC_MODE_8814B) &                             \\\n\t BIT_MASK_ACH7_DESC_MODE_8814B)\n#define BIT_SET_ACH7_DESC_MODE_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACH7_DESC_MODE_8814B(x) | BIT_ACH7_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_ACH7_DESC_NUM_8814B 16\n#define BIT_MASK_ACH7_DESC_NUM_8814B 0xfff\n#define BIT_ACH7_DESC_NUM_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH7_DESC_NUM_8814B) << BIT_SHIFT_ACH7_DESC_NUM_8814B)\n#define BITS_ACH7_DESC_NUM_8814B                                               \\\n\t(BIT_MASK_ACH7_DESC_NUM_8814B << BIT_SHIFT_ACH7_DESC_NUM_8814B)\n#define BIT_CLEAR_ACH7_DESC_NUM_8814B(x) ((x) & (~BITS_ACH7_DESC_NUM_8814B))\n#define BIT_GET_ACH7_DESC_NUM_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH7_DESC_NUM_8814B) & BIT_MASK_ACH7_DESC_NUM_8814B)\n#define BIT_SET_ACH7_DESC_NUM_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH7_DESC_NUM_8814B(x) | BIT_ACH7_DESC_NUM_8814B(v))\n\n#define BIT_PCIE_ACH6_FLAG_8814B BIT(14)\n\n#define BIT_SHIFT_ACH6_DESC_MODE_8814B 12\n#define BIT_MASK_ACH6_DESC_MODE_8814B 0x3\n#define BIT_ACH6_DESC_MODE_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACH6_DESC_MODE_8814B)                                 \\\n\t << BIT_SHIFT_ACH6_DESC_MODE_8814B)\n#define BITS_ACH6_DESC_MODE_8814B                                              \\\n\t(BIT_MASK_ACH6_DESC_MODE_8814B << BIT_SHIFT_ACH6_DESC_MODE_8814B)\n#define BIT_CLEAR_ACH6_DESC_MODE_8814B(x) ((x) & (~BITS_ACH6_DESC_MODE_8814B))\n#define BIT_GET_ACH6_DESC_MODE_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACH6_DESC_MODE_8814B) &                             \\\n\t BIT_MASK_ACH6_DESC_MODE_8814B)\n#define BIT_SET_ACH6_DESC_MODE_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACH6_DESC_MODE_8814B(x) | BIT_ACH6_DESC_MODE_8814B(v))\n\n#define BIT_SHIFT_ACH6_DESC_NUM_8814B 0\n#define BIT_MASK_ACH6_DESC_NUM_8814B 0xfff\n#define BIT_ACH6_DESC_NUM_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH6_DESC_NUM_8814B) << BIT_SHIFT_ACH6_DESC_NUM_8814B)\n#define BITS_ACH6_DESC_NUM_8814B                                               \\\n\t(BIT_MASK_ACH6_DESC_NUM_8814B << BIT_SHIFT_ACH6_DESC_NUM_8814B)\n#define BIT_CLEAR_ACH6_DESC_NUM_8814B(x) ((x) & (~BITS_ACH6_DESC_NUM_8814B))\n#define BIT_GET_ACH6_DESC_NUM_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH6_DESC_NUM_8814B) & BIT_MASK_ACH6_DESC_NUM_8814B)\n#define BIT_SET_ACH6_DESC_NUM_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH6_DESC_NUM_8814B(x) | BIT_ACH6_DESC_NUM_8814B(v))\n\n/* 2 REG_ACH4_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_ACH4_HW_IDX_8814B 16\n#define BIT_MASK_ACH4_HW_IDX_8814B 0xfff\n#define BIT_ACH4_HW_IDX_8814B(x)                                               \\\n\t(((x) & BIT_MASK_ACH4_HW_IDX_8814B) << BIT_SHIFT_ACH4_HW_IDX_8814B)\n#define BITS_ACH4_HW_IDX_8814B                                                 \\\n\t(BIT_MASK_ACH4_HW_IDX_8814B << BIT_SHIFT_ACH4_HW_IDX_8814B)\n#define BIT_CLEAR_ACH4_HW_IDX_8814B(x) ((x) & (~BITS_ACH4_HW_IDX_8814B))\n#define BIT_GET_ACH4_HW_IDX_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH4_HW_IDX_8814B) & BIT_MASK_ACH4_HW_IDX_8814B)\n#define BIT_SET_ACH4_HW_IDX_8814B(x, v)                                        \\\n\t(BIT_CLEAR_ACH4_HW_IDX_8814B(x) | BIT_ACH4_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_ACH4_HOST_IDX_8814B 0\n#define BIT_MASK_ACH4_HOST_IDX_8814B 0xfff\n#define BIT_ACH4_HOST_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH4_HOST_IDX_8814B) << BIT_SHIFT_ACH4_HOST_IDX_8814B)\n#define BITS_ACH4_HOST_IDX_8814B                                               \\\n\t(BIT_MASK_ACH4_HOST_IDX_8814B << BIT_SHIFT_ACH4_HOST_IDX_8814B)\n#define BIT_CLEAR_ACH4_HOST_IDX_8814B(x) ((x) & (~BITS_ACH4_HOST_IDX_8814B))\n#define BIT_GET_ACH4_HOST_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH4_HOST_IDX_8814B) & BIT_MASK_ACH4_HOST_IDX_8814B)\n#define BIT_SET_ACH4_HOST_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH4_HOST_IDX_8814B(x) | BIT_ACH4_HOST_IDX_8814B(v))\n\n/* 2 REG_ACH5_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_ACH5_HW_IDX_8814B 16\n#define BIT_MASK_ACH5_HW_IDX_8814B 0xfff\n#define BIT_ACH5_HW_IDX_8814B(x)                                               \\\n\t(((x) & BIT_MASK_ACH5_HW_IDX_8814B) << BIT_SHIFT_ACH5_HW_IDX_8814B)\n#define BITS_ACH5_HW_IDX_8814B                                                 \\\n\t(BIT_MASK_ACH5_HW_IDX_8814B << BIT_SHIFT_ACH5_HW_IDX_8814B)\n#define BIT_CLEAR_ACH5_HW_IDX_8814B(x) ((x) & (~BITS_ACH5_HW_IDX_8814B))\n#define BIT_GET_ACH5_HW_IDX_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH5_HW_IDX_8814B) & BIT_MASK_ACH5_HW_IDX_8814B)\n#define BIT_SET_ACH5_HW_IDX_8814B(x, v)                                        \\\n\t(BIT_CLEAR_ACH5_HW_IDX_8814B(x) | BIT_ACH5_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_ACH5_HOST_IDX_8814B 0\n#define BIT_MASK_ACH5_HOST_IDX_8814B 0xfff\n#define BIT_ACH5_HOST_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH5_HOST_IDX_8814B) << BIT_SHIFT_ACH5_HOST_IDX_8814B)\n#define BITS_ACH5_HOST_IDX_8814B                                               \\\n\t(BIT_MASK_ACH5_HOST_IDX_8814B << BIT_SHIFT_ACH5_HOST_IDX_8814B)\n#define BIT_CLEAR_ACH5_HOST_IDX_8814B(x) ((x) & (~BITS_ACH5_HOST_IDX_8814B))\n#define BIT_GET_ACH5_HOST_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH5_HOST_IDX_8814B) & BIT_MASK_ACH5_HOST_IDX_8814B)\n#define BIT_SET_ACH5_HOST_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH5_HOST_IDX_8814B(x) | BIT_ACH5_HOST_IDX_8814B(v))\n\n/* 2 REG_ACH6_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_ACH6_HW_IDX_8814B 16\n#define BIT_MASK_ACH6_HW_IDX_8814B 0xfff\n#define BIT_ACH6_HW_IDX_8814B(x)                                               \\\n\t(((x) & BIT_MASK_ACH6_HW_IDX_8814B) << BIT_SHIFT_ACH6_HW_IDX_8814B)\n#define BITS_ACH6_HW_IDX_8814B                                                 \\\n\t(BIT_MASK_ACH6_HW_IDX_8814B << BIT_SHIFT_ACH6_HW_IDX_8814B)\n#define BIT_CLEAR_ACH6_HW_IDX_8814B(x) ((x) & (~BITS_ACH6_HW_IDX_8814B))\n#define BIT_GET_ACH6_HW_IDX_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH6_HW_IDX_8814B) & BIT_MASK_ACH6_HW_IDX_8814B)\n#define BIT_SET_ACH6_HW_IDX_8814B(x, v)                                        \\\n\t(BIT_CLEAR_ACH6_HW_IDX_8814B(x) | BIT_ACH6_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_ACH6_HOST_IDX_8814B 0\n#define BIT_MASK_ACH6_HOST_IDX_8814B 0xfff\n#define BIT_ACH6_HOST_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH6_HOST_IDX_8814B) << BIT_SHIFT_ACH6_HOST_IDX_8814B)\n#define BITS_ACH6_HOST_IDX_8814B                                               \\\n\t(BIT_MASK_ACH6_HOST_IDX_8814B << BIT_SHIFT_ACH6_HOST_IDX_8814B)\n#define BIT_CLEAR_ACH6_HOST_IDX_8814B(x) ((x) & (~BITS_ACH6_HOST_IDX_8814B))\n#define BIT_GET_ACH6_HOST_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH6_HOST_IDX_8814B) & BIT_MASK_ACH6_HOST_IDX_8814B)\n#define BIT_SET_ACH6_HOST_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH6_HOST_IDX_8814B(x) | BIT_ACH6_HOST_IDX_8814B(v))\n\n/* 2 REG_ACH7_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_ACH7_HW_IDX_8814B 16\n#define BIT_MASK_ACH7_HW_IDX_8814B 0xfff\n#define BIT_ACH7_HW_IDX_8814B(x)                                               \\\n\t(((x) & BIT_MASK_ACH7_HW_IDX_8814B) << BIT_SHIFT_ACH7_HW_IDX_8814B)\n#define BITS_ACH7_HW_IDX_8814B                                                 \\\n\t(BIT_MASK_ACH7_HW_IDX_8814B << BIT_SHIFT_ACH7_HW_IDX_8814B)\n#define BIT_CLEAR_ACH7_HW_IDX_8814B(x) ((x) & (~BITS_ACH7_HW_IDX_8814B))\n#define BIT_GET_ACH7_HW_IDX_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH7_HW_IDX_8814B) & BIT_MASK_ACH7_HW_IDX_8814B)\n#define BIT_SET_ACH7_HW_IDX_8814B(x, v)                                        \\\n\t(BIT_CLEAR_ACH7_HW_IDX_8814B(x) | BIT_ACH7_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_ACH7_HOST_IDX_8814B 0\n#define BIT_MASK_ACH7_HOST_IDX_8814B 0xfff\n#define BIT_ACH7_HOST_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH7_HOST_IDX_8814B) << BIT_SHIFT_ACH7_HOST_IDX_8814B)\n#define BITS_ACH7_HOST_IDX_8814B                                               \\\n\t(BIT_MASK_ACH7_HOST_IDX_8814B << BIT_SHIFT_ACH7_HOST_IDX_8814B)\n#define BIT_CLEAR_ACH7_HOST_IDX_8814B(x) ((x) & (~BITS_ACH7_HOST_IDX_8814B))\n#define BIT_GET_ACH7_HOST_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH7_HOST_IDX_8814B) & BIT_MASK_ACH7_HOST_IDX_8814B)\n#define BIT_SET_ACH7_HOST_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH7_HOST_IDX_8814B(x) | BIT_ACH7_HOST_IDX_8814B(v))\n\n/* 2 REG_ACH8_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_ACH8_HW_IDX_8814B 16\n#define BIT_MASK_ACH8_HW_IDX_8814B 0xfff\n#define BIT_ACH8_HW_IDX_8814B(x)                                               \\\n\t(((x) & BIT_MASK_ACH8_HW_IDX_8814B) << BIT_SHIFT_ACH8_HW_IDX_8814B)\n#define BITS_ACH8_HW_IDX_8814B                                                 \\\n\t(BIT_MASK_ACH8_HW_IDX_8814B << BIT_SHIFT_ACH8_HW_IDX_8814B)\n#define BIT_CLEAR_ACH8_HW_IDX_8814B(x) ((x) & (~BITS_ACH8_HW_IDX_8814B))\n#define BIT_GET_ACH8_HW_IDX_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH8_HW_IDX_8814B) & BIT_MASK_ACH8_HW_IDX_8814B)\n#define BIT_SET_ACH8_HW_IDX_8814B(x, v)                                        \\\n\t(BIT_CLEAR_ACH8_HW_IDX_8814B(x) | BIT_ACH8_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_ACH8_HOST_IDX_8814B 0\n#define BIT_MASK_ACH8_HOST_IDX_8814B 0xfff\n#define BIT_ACH8_HOST_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH8_HOST_IDX_8814B) << BIT_SHIFT_ACH8_HOST_IDX_8814B)\n#define BITS_ACH8_HOST_IDX_8814B                                               \\\n\t(BIT_MASK_ACH8_HOST_IDX_8814B << BIT_SHIFT_ACH8_HOST_IDX_8814B)\n#define BIT_CLEAR_ACH8_HOST_IDX_8814B(x) ((x) & (~BITS_ACH8_HOST_IDX_8814B))\n#define BIT_GET_ACH8_HOST_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH8_HOST_IDX_8814B) & BIT_MASK_ACH8_HOST_IDX_8814B)\n#define BIT_SET_ACH8_HOST_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH8_HOST_IDX_8814B(x) | BIT_ACH8_HOST_IDX_8814B(v))\n\n/* 2 REG_ACH9_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_ACH9_HW_IDX_8814B 16\n#define BIT_MASK_ACH9_HW_IDX_8814B 0xfff\n#define BIT_ACH9_HW_IDX_8814B(x)                                               \\\n\t(((x) & BIT_MASK_ACH9_HW_IDX_8814B) << BIT_SHIFT_ACH9_HW_IDX_8814B)\n#define BITS_ACH9_HW_IDX_8814B                                                 \\\n\t(BIT_MASK_ACH9_HW_IDX_8814B << BIT_SHIFT_ACH9_HW_IDX_8814B)\n#define BIT_CLEAR_ACH9_HW_IDX_8814B(x) ((x) & (~BITS_ACH9_HW_IDX_8814B))\n#define BIT_GET_ACH9_HW_IDX_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_ACH9_HW_IDX_8814B) & BIT_MASK_ACH9_HW_IDX_8814B)\n#define BIT_SET_ACH9_HW_IDX_8814B(x, v)                                        \\\n\t(BIT_CLEAR_ACH9_HW_IDX_8814B(x) | BIT_ACH9_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_ACH9_HOST_IDX_8814B 0\n#define BIT_MASK_ACH9_HOST_IDX_8814B 0xfff\n#define BIT_ACH9_HOST_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACH9_HOST_IDX_8814B) << BIT_SHIFT_ACH9_HOST_IDX_8814B)\n#define BITS_ACH9_HOST_IDX_8814B                                               \\\n\t(BIT_MASK_ACH9_HOST_IDX_8814B << BIT_SHIFT_ACH9_HOST_IDX_8814B)\n#define BIT_CLEAR_ACH9_HOST_IDX_8814B(x) ((x) & (~BITS_ACH9_HOST_IDX_8814B))\n#define BIT_GET_ACH9_HOST_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACH9_HOST_IDX_8814B) & BIT_MASK_ACH9_HOST_IDX_8814B)\n#define BIT_SET_ACH9_HOST_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACH9_HOST_IDX_8814B(x) | BIT_ACH9_HOST_IDX_8814B(v))\n\n/* 2 REG_ACH10_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_ACH10_HW_IDX_8814B 16\n#define BIT_MASK_ACH10_HW_IDX_8814B 0xfff\n#define BIT_ACH10_HW_IDX_8814B(x)                                              \\\n\t(((x) & BIT_MASK_ACH10_HW_IDX_8814B) << BIT_SHIFT_ACH10_HW_IDX_8814B)\n#define BITS_ACH10_HW_IDX_8814B                                                \\\n\t(BIT_MASK_ACH10_HW_IDX_8814B << BIT_SHIFT_ACH10_HW_IDX_8814B)\n#define BIT_CLEAR_ACH10_HW_IDX_8814B(x) ((x) & (~BITS_ACH10_HW_IDX_8814B))\n#define BIT_GET_ACH10_HW_IDX_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_ACH10_HW_IDX_8814B) & BIT_MASK_ACH10_HW_IDX_8814B)\n#define BIT_SET_ACH10_HW_IDX_8814B(x, v)                                       \\\n\t(BIT_CLEAR_ACH10_HW_IDX_8814B(x) | BIT_ACH10_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_ACH10_HOST_IDX_8814B 0\n#define BIT_MASK_ACH10_HOST_IDX_8814B 0xfff\n#define BIT_ACH10_HOST_IDX_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACH10_HOST_IDX_8814B)                                 \\\n\t << BIT_SHIFT_ACH10_HOST_IDX_8814B)\n#define BITS_ACH10_HOST_IDX_8814B                                              \\\n\t(BIT_MASK_ACH10_HOST_IDX_8814B << BIT_SHIFT_ACH10_HOST_IDX_8814B)\n#define BIT_CLEAR_ACH10_HOST_IDX_8814B(x) ((x) & (~BITS_ACH10_HOST_IDX_8814B))\n#define BIT_GET_ACH10_HOST_IDX_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACH10_HOST_IDX_8814B) &                             \\\n\t BIT_MASK_ACH10_HOST_IDX_8814B)\n#define BIT_SET_ACH10_HOST_IDX_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACH10_HOST_IDX_8814B(x) | BIT_ACH10_HOST_IDX_8814B(v))\n\n/* 2 REG_ACH11_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_ACH11_HW_IDX_8814B 16\n#define BIT_MASK_ACH11_HW_IDX_8814B 0xfff\n#define BIT_ACH11_HW_IDX_8814B(x)                                              \\\n\t(((x) & BIT_MASK_ACH11_HW_IDX_8814B) << BIT_SHIFT_ACH11_HW_IDX_8814B)\n#define BITS_ACH11_HW_IDX_8814B                                                \\\n\t(BIT_MASK_ACH11_HW_IDX_8814B << BIT_SHIFT_ACH11_HW_IDX_8814B)\n#define BIT_CLEAR_ACH11_HW_IDX_8814B(x) ((x) & (~BITS_ACH11_HW_IDX_8814B))\n#define BIT_GET_ACH11_HW_IDX_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_ACH11_HW_IDX_8814B) & BIT_MASK_ACH11_HW_IDX_8814B)\n#define BIT_SET_ACH11_HW_IDX_8814B(x, v)                                       \\\n\t(BIT_CLEAR_ACH11_HW_IDX_8814B(x) | BIT_ACH11_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_ACH11_HOST_IDX_8814B 0\n#define BIT_MASK_ACH11_HOST_IDX_8814B 0xfff\n#define BIT_ACH11_HOST_IDX_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACH11_HOST_IDX_8814B)                                 \\\n\t << BIT_SHIFT_ACH11_HOST_IDX_8814B)\n#define BITS_ACH11_HOST_IDX_8814B                                              \\\n\t(BIT_MASK_ACH11_HOST_IDX_8814B << BIT_SHIFT_ACH11_HOST_IDX_8814B)\n#define BIT_CLEAR_ACH11_HOST_IDX_8814B(x) ((x) & (~BITS_ACH11_HOST_IDX_8814B))\n#define BIT_GET_ACH11_HOST_IDX_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACH11_HOST_IDX_8814B) &                             \\\n\t BIT_MASK_ACH11_HOST_IDX_8814B)\n#define BIT_SET_ACH11_HOST_IDX_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACH11_HOST_IDX_8814B(x) | BIT_ACH11_HOST_IDX_8814B(v))\n\n/* 2 REG_ACH12_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_ACH12_HW_IDX_8814B 16\n#define BIT_MASK_ACH12_HW_IDX_8814B 0xfff\n#define BIT_ACH12_HW_IDX_8814B(x)                                              \\\n\t(((x) & BIT_MASK_ACH12_HW_IDX_8814B) << BIT_SHIFT_ACH12_HW_IDX_8814B)\n#define BITS_ACH12_HW_IDX_8814B                                                \\\n\t(BIT_MASK_ACH12_HW_IDX_8814B << BIT_SHIFT_ACH12_HW_IDX_8814B)\n#define BIT_CLEAR_ACH12_HW_IDX_8814B(x) ((x) & (~BITS_ACH12_HW_IDX_8814B))\n#define BIT_GET_ACH12_HW_IDX_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_ACH12_HW_IDX_8814B) & BIT_MASK_ACH12_HW_IDX_8814B)\n#define BIT_SET_ACH12_HW_IDX_8814B(x, v)                                       \\\n\t(BIT_CLEAR_ACH12_HW_IDX_8814B(x) | BIT_ACH12_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_ACH12_HOST_IDX_8814B 0\n#define BIT_MASK_ACH12_HOST_IDX_8814B 0xfff\n#define BIT_ACH12_HOST_IDX_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACH12_HOST_IDX_8814B)                                 \\\n\t << BIT_SHIFT_ACH12_HOST_IDX_8814B)\n#define BITS_ACH12_HOST_IDX_8814B                                              \\\n\t(BIT_MASK_ACH12_HOST_IDX_8814B << BIT_SHIFT_ACH12_HOST_IDX_8814B)\n#define BIT_CLEAR_ACH12_HOST_IDX_8814B(x) ((x) & (~BITS_ACH12_HOST_IDX_8814B))\n#define BIT_GET_ACH12_HOST_IDX_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACH12_HOST_IDX_8814B) &                             \\\n\t BIT_MASK_ACH12_HOST_IDX_8814B)\n#define BIT_SET_ACH12_HOST_IDX_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACH12_HOST_IDX_8814B(x) | BIT_ACH12_HOST_IDX_8814B(v))\n\n/* 2 REG_ACH13_TXBD_IDX_8814B */\n\n#define BIT_SHIFT_ACH13_HW_IDX_8814B 16\n#define BIT_MASK_ACH13_HW_IDX_8814B 0xfff\n#define BIT_ACH13_HW_IDX_8814B(x)                                              \\\n\t(((x) & BIT_MASK_ACH13_HW_IDX_8814B) << BIT_SHIFT_ACH13_HW_IDX_8814B)\n#define BITS_ACH13_HW_IDX_8814B                                                \\\n\t(BIT_MASK_ACH13_HW_IDX_8814B << BIT_SHIFT_ACH13_HW_IDX_8814B)\n#define BIT_CLEAR_ACH13_HW_IDX_8814B(x) ((x) & (~BITS_ACH13_HW_IDX_8814B))\n#define BIT_GET_ACH13_HW_IDX_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_ACH13_HW_IDX_8814B) & BIT_MASK_ACH13_HW_IDX_8814B)\n#define BIT_SET_ACH13_HW_IDX_8814B(x, v)                                       \\\n\t(BIT_CLEAR_ACH13_HW_IDX_8814B(x) | BIT_ACH13_HW_IDX_8814B(v))\n\n#define BIT_SHIFT_ACH13_HOST_IDX_8814B 0\n#define BIT_MASK_ACH13_HOST_IDX_8814B 0xfff\n#define BIT_ACH13_HOST_IDX_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACH13_HOST_IDX_8814B)                                 \\\n\t << BIT_SHIFT_ACH13_HOST_IDX_8814B)\n#define BITS_ACH13_HOST_IDX_8814B                                              \\\n\t(BIT_MASK_ACH13_HOST_IDX_8814B << BIT_SHIFT_ACH13_HOST_IDX_8814B)\n#define BIT_CLEAR_ACH13_HOST_IDX_8814B(x) ((x) & (~BITS_ACH13_HOST_IDX_8814B))\n#define BIT_GET_ACH13_HOST_IDX_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACH13_HOST_IDX_8814B) &                             \\\n\t BIT_MASK_ACH13_HOST_IDX_8814B)\n#define BIT_SET_ACH13_HOST_IDX_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACH13_HOST_IDX_8814B(x) | BIT_ACH13_HOST_IDX_8814B(v))\n\n/* 2 REG_AC_CHANNEL0_WEIGHT_8814B */\n\n#define BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B 0\n#define BIT_MASK_AC_CHANNEL0_WEIGHT_8814B 0xff\n#define BIT_AC_CHANNEL0_WEIGHT_8814B(x)                                        \\\n\t(((x) & BIT_MASK_AC_CHANNEL0_WEIGHT_8814B)                             \\\n\t << BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B)\n#define BITS_AC_CHANNEL0_WEIGHT_8814B                                          \\\n\t(BIT_MASK_AC_CHANNEL0_WEIGHT_8814B                                     \\\n\t << BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B)\n#define BIT_CLEAR_AC_CHANNEL0_WEIGHT_8814B(x)                                  \\\n\t((x) & (~BITS_AC_CHANNEL0_WEIGHT_8814B))\n#define BIT_GET_AC_CHANNEL0_WEIGHT_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B) &                         \\\n\t BIT_MASK_AC_CHANNEL0_WEIGHT_8814B)\n#define BIT_SET_AC_CHANNEL0_WEIGHT_8814B(x, v)                                 \\\n\t(BIT_CLEAR_AC_CHANNEL0_WEIGHT_8814B(x) |                               \\\n\t BIT_AC_CHANNEL0_WEIGHT_8814B(v))\n\n/* 2 REG_AC_CHANNEL1_WEIGHT_8814B */\n\n#define BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B 0\n#define BIT_MASK_AC_CHANNEL1_WEIGHT_8814B 0xff\n#define BIT_AC_CHANNEL1_WEIGHT_8814B(x)                                        \\\n\t(((x) & BIT_MASK_AC_CHANNEL1_WEIGHT_8814B)                             \\\n\t << BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B)\n#define BITS_AC_CHANNEL1_WEIGHT_8814B                                          \\\n\t(BIT_MASK_AC_CHANNEL1_WEIGHT_8814B                                     \\\n\t << BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B)\n#define BIT_CLEAR_AC_CHANNEL1_WEIGHT_8814B(x)                                  \\\n\t((x) & (~BITS_AC_CHANNEL1_WEIGHT_8814B))\n#define BIT_GET_AC_CHANNEL1_WEIGHT_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B) &                         \\\n\t BIT_MASK_AC_CHANNEL1_WEIGHT_8814B)\n#define BIT_SET_AC_CHANNEL1_WEIGHT_8814B(x, v)                                 \\\n\t(BIT_CLEAR_AC_CHANNEL1_WEIGHT_8814B(x) |                               \\\n\t BIT_AC_CHANNEL1_WEIGHT_8814B(v))\n\n/* 2 REG_AC_CHANNEL2_WEIGHT_8814B */\n\n#define BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B 0\n#define BIT_MASK_AC_CHANNEL2_WEIGHT_8814B 0xff\n#define BIT_AC_CHANNEL2_WEIGHT_8814B(x)                                        \\\n\t(((x) & BIT_MASK_AC_CHANNEL2_WEIGHT_8814B)                             \\\n\t << BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B)\n#define BITS_AC_CHANNEL2_WEIGHT_8814B                                          \\\n\t(BIT_MASK_AC_CHANNEL2_WEIGHT_8814B                                     \\\n\t << BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B)\n#define BIT_CLEAR_AC_CHANNEL2_WEIGHT_8814B(x)                                  \\\n\t((x) & (~BITS_AC_CHANNEL2_WEIGHT_8814B))\n#define BIT_GET_AC_CHANNEL2_WEIGHT_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B) &                         \\\n\t BIT_MASK_AC_CHANNEL2_WEIGHT_8814B)\n#define BIT_SET_AC_CHANNEL2_WEIGHT_8814B(x, v)                                 \\\n\t(BIT_CLEAR_AC_CHANNEL2_WEIGHT_8814B(x) |                               \\\n\t BIT_AC_CHANNEL2_WEIGHT_8814B(v))\n\n/* 2 REG_AC_CHANNEL3_WEIGHT_8814B */\n\n#define BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B 0\n#define BIT_MASK_AC_CHANNEL3_WEIGHT_8814B 0xff\n#define BIT_AC_CHANNEL3_WEIGHT_8814B(x)                                        \\\n\t(((x) & BIT_MASK_AC_CHANNEL3_WEIGHT_8814B)                             \\\n\t << BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B)\n#define BITS_AC_CHANNEL3_WEIGHT_8814B                                          \\\n\t(BIT_MASK_AC_CHANNEL3_WEIGHT_8814B                                     \\\n\t << BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B)\n#define BIT_CLEAR_AC_CHANNEL3_WEIGHT_8814B(x)                                  \\\n\t((x) & (~BITS_AC_CHANNEL3_WEIGHT_8814B))\n#define BIT_GET_AC_CHANNEL3_WEIGHT_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B) &                         \\\n\t BIT_MASK_AC_CHANNEL3_WEIGHT_8814B)\n#define BIT_SET_AC_CHANNEL3_WEIGHT_8814B(x, v)                                 \\\n\t(BIT_CLEAR_AC_CHANNEL3_WEIGHT_8814B(x) |                               \\\n\t BIT_AC_CHANNEL3_WEIGHT_8814B(v))\n\n/* 2 REG_AC_CHANNEL4_WEIGHT_8814B */\n\n#define BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B 0\n#define BIT_MASK_AC_CHANNEL4_WEIGHT_8814B 0xff\n#define BIT_AC_CHANNEL4_WEIGHT_8814B(x)                                        \\\n\t(((x) & BIT_MASK_AC_CHANNEL4_WEIGHT_8814B)                             \\\n\t << BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B)\n#define BITS_AC_CHANNEL4_WEIGHT_8814B                                          \\\n\t(BIT_MASK_AC_CHANNEL4_WEIGHT_8814B                                     \\\n\t << BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B)\n#define BIT_CLEAR_AC_CHANNEL4_WEIGHT_8814B(x)                                  \\\n\t((x) & (~BITS_AC_CHANNEL4_WEIGHT_8814B))\n#define BIT_GET_AC_CHANNEL4_WEIGHT_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B) &                         \\\n\t BIT_MASK_AC_CHANNEL4_WEIGHT_8814B)\n#define BIT_SET_AC_CHANNEL4_WEIGHT_8814B(x, v)                                 \\\n\t(BIT_CLEAR_AC_CHANNEL4_WEIGHT_8814B(x) |                               \\\n\t BIT_AC_CHANNEL4_WEIGHT_8814B(v))\n\n/* 2 REG_AC_CHANNEL5_WEIGHT_8814B */\n\n#define BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B 0\n#define BIT_MASK_AC_CHANNEL5_WEIGHT_8814B 0xff\n#define BIT_AC_CHANNEL5_WEIGHT_8814B(x)                                        \\\n\t(((x) & BIT_MASK_AC_CHANNEL5_WEIGHT_8814B)                             \\\n\t << BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B)\n#define BITS_AC_CHANNEL5_WEIGHT_8814B                                          \\\n\t(BIT_MASK_AC_CHANNEL5_WEIGHT_8814B                                     \\\n\t << BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B)\n#define BIT_CLEAR_AC_CHANNEL5_WEIGHT_8814B(x)                                  \\\n\t((x) & (~BITS_AC_CHANNEL5_WEIGHT_8814B))\n#define BIT_GET_AC_CHANNEL5_WEIGHT_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B) &                         \\\n\t BIT_MASK_AC_CHANNEL5_WEIGHT_8814B)\n#define BIT_SET_AC_CHANNEL5_WEIGHT_8814B(x, v)                                 \\\n\t(BIT_CLEAR_AC_CHANNEL5_WEIGHT_8814B(x) |                               \\\n\t BIT_AC_CHANNEL5_WEIGHT_8814B(v))\n\n/* 2 REG_AC_CHANNEL6_WEIGHT_8814B */\n\n#define BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B 0\n#define BIT_MASK_AC_CHANNEL6_WEIGHT_8814B 0xff\n#define BIT_AC_CHANNEL6_WEIGHT_8814B(x)                                        \\\n\t(((x) & BIT_MASK_AC_CHANNEL6_WEIGHT_8814B)                             \\\n\t << BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B)\n#define BITS_AC_CHANNEL6_WEIGHT_8814B                                          \\\n\t(BIT_MASK_AC_CHANNEL6_WEIGHT_8814B                                     \\\n\t << BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B)\n#define BIT_CLEAR_AC_CHANNEL6_WEIGHT_8814B(x)                                  \\\n\t((x) & (~BITS_AC_CHANNEL6_WEIGHT_8814B))\n#define BIT_GET_AC_CHANNEL6_WEIGHT_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B) &                         \\\n\t BIT_MASK_AC_CHANNEL6_WEIGHT_8814B)\n#define BIT_SET_AC_CHANNEL6_WEIGHT_8814B(x, v)                                 \\\n\t(BIT_CLEAR_AC_CHANNEL6_WEIGHT_8814B(x) |                               \\\n\t BIT_AC_CHANNEL6_WEIGHT_8814B(v))\n\n/* 2 REG_AC_CHANNEL7_WEIGHT_8814B */\n\n#define BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B 0\n#define BIT_MASK_AC_CHANNEL7_WEIGHT_8814B 0xff\n#define BIT_AC_CHANNEL7_WEIGHT_8814B(x)                                        \\\n\t(((x) & BIT_MASK_AC_CHANNEL7_WEIGHT_8814B)                             \\\n\t << BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B)\n#define BITS_AC_CHANNEL7_WEIGHT_8814B                                          \\\n\t(BIT_MASK_AC_CHANNEL7_WEIGHT_8814B                                     \\\n\t << BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B)\n#define BIT_CLEAR_AC_CHANNEL7_WEIGHT_8814B(x)                                  \\\n\t((x) & (~BITS_AC_CHANNEL7_WEIGHT_8814B))\n#define BIT_GET_AC_CHANNEL7_WEIGHT_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B) &                         \\\n\t BIT_MASK_AC_CHANNEL7_WEIGHT_8814B)\n#define BIT_SET_AC_CHANNEL7_WEIGHT_8814B(x, v)                                 \\\n\t(BIT_CLEAR_AC_CHANNEL7_WEIGHT_8814B(x) |                               \\\n\t BIT_AC_CHANNEL7_WEIGHT_8814B(v))\n\n/* 2 REG_AC_CHANNEL8_WEIGHT_8814B */\n\n#define BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B 0\n#define BIT_MASK_AC_CHANNEL8_WEIGHT_8814B 0xff\n#define BIT_AC_CHANNEL8_WEIGHT_8814B(x)                                        \\\n\t(((x) & BIT_MASK_AC_CHANNEL8_WEIGHT_8814B)                             \\\n\t << BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B)\n#define BITS_AC_CHANNEL8_WEIGHT_8814B                                          \\\n\t(BIT_MASK_AC_CHANNEL8_WEIGHT_8814B                                     \\\n\t << BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B)\n#define BIT_CLEAR_AC_CHANNEL8_WEIGHT_8814B(x)                                  \\\n\t((x) & (~BITS_AC_CHANNEL8_WEIGHT_8814B))\n#define BIT_GET_AC_CHANNEL8_WEIGHT_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B) &                         \\\n\t BIT_MASK_AC_CHANNEL8_WEIGHT_8814B)\n#define BIT_SET_AC_CHANNEL8_WEIGHT_8814B(x, v)                                 \\\n\t(BIT_CLEAR_AC_CHANNEL8_WEIGHT_8814B(x) |                               \\\n\t BIT_AC_CHANNEL8_WEIGHT_8814B(v))\n\n/* 2 REG_AC_CHANNEL9_WEIGHT_8814B */\n\n#define BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B 0\n#define BIT_MASK_AC_CHANNEL9_WEIGHT_8814B 0xff\n#define BIT_AC_CHANNEL9_WEIGHT_8814B(x)                                        \\\n\t(((x) & BIT_MASK_AC_CHANNEL9_WEIGHT_8814B)                             \\\n\t << BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B)\n#define BITS_AC_CHANNEL9_WEIGHT_8814B                                          \\\n\t(BIT_MASK_AC_CHANNEL9_WEIGHT_8814B                                     \\\n\t << BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B)\n#define BIT_CLEAR_AC_CHANNEL9_WEIGHT_8814B(x)                                  \\\n\t((x) & (~BITS_AC_CHANNEL9_WEIGHT_8814B))\n#define BIT_GET_AC_CHANNEL9_WEIGHT_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B) &                         \\\n\t BIT_MASK_AC_CHANNEL9_WEIGHT_8814B)\n#define BIT_SET_AC_CHANNEL9_WEIGHT_8814B(x, v)                                 \\\n\t(BIT_CLEAR_AC_CHANNEL9_WEIGHT_8814B(x) |                               \\\n\t BIT_AC_CHANNEL9_WEIGHT_8814B(v))\n\n/* 2 REG_AC_CHANNEL10_WEIGHT_8814B */\n\n#define BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B 0\n#define BIT_MASK_AC_CHANNEL10_WEIGHT_8814B 0xff\n#define BIT_AC_CHANNEL10_WEIGHT_8814B(x)                                       \\\n\t(((x) & BIT_MASK_AC_CHANNEL10_WEIGHT_8814B)                            \\\n\t << BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B)\n#define BITS_AC_CHANNEL10_WEIGHT_8814B                                         \\\n\t(BIT_MASK_AC_CHANNEL10_WEIGHT_8814B                                    \\\n\t << BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B)\n#define BIT_CLEAR_AC_CHANNEL10_WEIGHT_8814B(x)                                 \\\n\t((x) & (~BITS_AC_CHANNEL10_WEIGHT_8814B))\n#define BIT_GET_AC_CHANNEL10_WEIGHT_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B) &                        \\\n\t BIT_MASK_AC_CHANNEL10_WEIGHT_8814B)\n#define BIT_SET_AC_CHANNEL10_WEIGHT_8814B(x, v)                                \\\n\t(BIT_CLEAR_AC_CHANNEL10_WEIGHT_8814B(x) |                              \\\n\t BIT_AC_CHANNEL10_WEIGHT_8814B(v))\n\n/* 2 REG_AC_CHANNEL11_WEIGHT_8814B */\n\n#define BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B 0\n#define BIT_MASK_AC_CHANNEL11_WEIGHT_8814B 0xff\n#define BIT_AC_CHANNEL11_WEIGHT_8814B(x)                                       \\\n\t(((x) & BIT_MASK_AC_CHANNEL11_WEIGHT_8814B)                            \\\n\t << BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B)\n#define BITS_AC_CHANNEL11_WEIGHT_8814B                                         \\\n\t(BIT_MASK_AC_CHANNEL11_WEIGHT_8814B                                    \\\n\t << BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B)\n#define BIT_CLEAR_AC_CHANNEL11_WEIGHT_8814B(x)                                 \\\n\t((x) & (~BITS_AC_CHANNEL11_WEIGHT_8814B))\n#define BIT_GET_AC_CHANNEL11_WEIGHT_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B) &                        \\\n\t BIT_MASK_AC_CHANNEL11_WEIGHT_8814B)\n#define BIT_SET_AC_CHANNEL11_WEIGHT_8814B(x, v)                                \\\n\t(BIT_CLEAR_AC_CHANNEL11_WEIGHT_8814B(x) |                              \\\n\t BIT_AC_CHANNEL11_WEIGHT_8814B(v))\n\n/* 2 REG_AC_CHANNEL12_WEIGHT_8814B */\n\n#define BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B 0\n#define BIT_MASK_AC_CHANNEL12_WEIGHT_8814B 0xff\n#define BIT_AC_CHANNEL12_WEIGHT_8814B(x)                                       \\\n\t(((x) & BIT_MASK_AC_CHANNEL12_WEIGHT_8814B)                            \\\n\t << BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B)\n#define BITS_AC_CHANNEL12_WEIGHT_8814B                                         \\\n\t(BIT_MASK_AC_CHANNEL12_WEIGHT_8814B                                    \\\n\t << BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B)\n#define BIT_CLEAR_AC_CHANNEL12_WEIGHT_8814B(x)                                 \\\n\t((x) & (~BITS_AC_CHANNEL12_WEIGHT_8814B))\n#define BIT_GET_AC_CHANNEL12_WEIGHT_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B) &                        \\\n\t BIT_MASK_AC_CHANNEL12_WEIGHT_8814B)\n#define BIT_SET_AC_CHANNEL12_WEIGHT_8814B(x, v)                                \\\n\t(BIT_CLEAR_AC_CHANNEL12_WEIGHT_8814B(x) |                              \\\n\t BIT_AC_CHANNEL12_WEIGHT_8814B(v))\n\n/* 2 REG_AC_CHANNEL13_WEIGHT_8814B */\n\n#define BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B 0\n#define BIT_MASK_AC_CHANNEL13_WEIGHT_8814B 0xff\n#define BIT_AC_CHANNEL13_WEIGHT_8814B(x)                                       \\\n\t(((x) & BIT_MASK_AC_CHANNEL13_WEIGHT_8814B)                            \\\n\t << BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B)\n#define BITS_AC_CHANNEL13_WEIGHT_8814B                                         \\\n\t(BIT_MASK_AC_CHANNEL13_WEIGHT_8814B                                    \\\n\t << BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B)\n#define BIT_CLEAR_AC_CHANNEL13_WEIGHT_8814B(x)                                 \\\n\t((x) & (~BITS_AC_CHANNEL13_WEIGHT_8814B))\n#define BIT_GET_AC_CHANNEL13_WEIGHT_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B) &                        \\\n\t BIT_MASK_AC_CHANNEL13_WEIGHT_8814B)\n#define BIT_SET_AC_CHANNEL13_WEIGHT_8814B(x, v)                                \\\n\t(BIT_CLEAR_AC_CHANNEL13_WEIGHT_8814B(x) |                              \\\n\t BIT_AC_CHANNEL13_WEIGHT_8814B(v))\n\n/* 2 REG_PCIE_HISR2_8814B */\n#define BIT_BCNDMAINT_P4_8814B BIT(31)\n#define BIT_BCNDMAINT_P3_8814B BIT(30)\n#define BIT_BCNDMAINT_P2_8814B BIT(29)\n#define BIT_BCNDMAINT_P1_8814B BIT(28)\n#define BIT_SCH_PHY_TXOP_SIFS_INT_8814B BIT(23)\n#define BIT_ATIMEND7_8814B BIT(22)\n#define BIT_ATIMEND6_8814B BIT(21)\n#define BIT_ATIMEND5_8814B BIT(20)\n#define BIT_ATIMEND4_8814B BIT(19)\n#define BIT_ATIMEND3_8814B BIT(18)\n#define BIT_ATIMEND2_8814B BIT(17)\n#define BIT_ATIMEND1_8814B BIT(16)\n#define BIT_TXBCN7OK_8814B BIT(14)\n#define BIT_TXBCN6OK_8814B BIT(13)\n#define BIT_TXBCN5OK_8814B BIT(12)\n#define BIT_TXBCN4OK_8814B BIT(11)\n#define BIT_TXBCN3OK_8814B BIT(10)\n#define BIT_TXBCN2OK_8814B BIT(9)\n#define BIT_TXBCN1OK_8814B BIT(8)\n#define BIT_TXBCN7ERR_8814B BIT(6)\n#define BIT_TXBCN6ERR_8814B BIT(5)\n#define BIT_TXBCN5ERR_8814B BIT(4)\n#define BIT_TXBCN4ERR_8814B BIT(3)\n#define BIT_TXBCN3ERR_8814B BIT(2)\n#define BIT_TXBCN2ERR_8814B BIT(1)\n#define BIT_TXBCN1ERR_8814B BIT(0)\n\n/* 2 REG_PCIE_HISR3_8814B */\n#define BIT_GTINT12_8814B BIT(24)\n#define BIT_GTINT11_8814B BIT(23)\n#define BIT_GTINT10_8814B BIT(22)\n#define BIT_GTINT9_8814B BIT(21)\n#define BIT_RX_DESC_BUF_FULL_8814B BIT(20)\n#define BIT_CPHY_LDO_OCP_DET_INT_8814B BIT(19)\n#define BIT_WDT_PLATFORM_INT_8814B BIT(18)\n#define BIT_WDT_CPU_INT_8814B BIT(17)\n#define BIT_SETH2CDOK_8814B BIT(16)\n#define BIT_H2C_CMD_FULL_8814B BIT(15)\n#define BIT_PKT_TRANS_ERR_8814B BIT(14)\n#define BIT_TXSHORTCUT_TXDESUPDATEOK_8814B BIT(13)\n#define BIT_TXSHORTCUT_BKUPDATEOK_8814B BIT(12)\n#define BIT_TXSHORTCUT_BEUPDATEOK_8814B BIT(11)\n#define BIT_TXSHORTCUT_VIUPDATEOK_8814B BIT(10)\n#define BIT_TXSHORTCUT_VOUPDATEOK_8814B BIT(9)\n#define BIT_SEARCH_FAIL_8814B BIT(8)\n#define BIT_PWR_INT_127TO96_8814B BIT(7)\n#define BIT_PWR_INT_95TO64_8814B BIT(6)\n#define BIT_PWR_INT_63TO32_8814B BIT(5)\n#define BIT_PWR_INT_31TO0_8814B BIT(4)\n#define BIT_RX_DMA_STUCK_8814B BIT(3)\n#define BIT_TX_DMA_STUCK_8814B BIT(2)\n#define BIT_DDMA0_LP_INT_8814B BIT(1)\n#define BIT_DDMA0_HP_INT_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_QUEUELIST_INFO0_8814B */\n\n#define BIT_SHIFT_QINFO0_8814B 0\n#define BIT_MASK_QINFO0_8814B 0xffffffffL\n#define BIT_QINFO0_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_QINFO0_8814B) << BIT_SHIFT_QINFO0_8814B)\n#define BITS_QINFO0_8814B (BIT_MASK_QINFO0_8814B << BIT_SHIFT_QINFO0_8814B)\n#define BIT_CLEAR_QINFO0_8814B(x) ((x) & (~BITS_QINFO0_8814B))\n#define BIT_GET_QINFO0_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_QINFO0_8814B) & BIT_MASK_QINFO0_8814B)\n#define BIT_SET_QINFO0_8814B(x, v)                                             \\\n\t(BIT_CLEAR_QINFO0_8814B(x) | BIT_QINFO0_8814B(v))\n\n/* 2 REG_QUEUELIST_INFO1_8814B */\n\n#define BIT_SHIFT_QINFO1_8814B 0\n#define BIT_MASK_QINFO1_8814B 0xffffffffL\n#define BIT_QINFO1_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_QINFO1_8814B) << BIT_SHIFT_QINFO1_8814B)\n#define BITS_QINFO1_8814B (BIT_MASK_QINFO1_8814B << BIT_SHIFT_QINFO1_8814B)\n#define BIT_CLEAR_QINFO1_8814B(x) ((x) & (~BITS_QINFO1_8814B))\n#define BIT_GET_QINFO1_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_QINFO1_8814B) & BIT_MASK_QINFO1_8814B)\n#define BIT_SET_QINFO1_8814B(x, v)                                             \\\n\t(BIT_CLEAR_QINFO1_8814B(x) | BIT_QINFO1_8814B(v))\n\n/* 2 REG_QUEUELIST_INFO2_8814B */\n\n#define BIT_SHIFT_QINFO2_8814B 0\n#define BIT_MASK_QINFO2_8814B 0xffffffffL\n#define BIT_QINFO2_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_QINFO2_8814B) << BIT_SHIFT_QINFO2_8814B)\n#define BITS_QINFO2_8814B (BIT_MASK_QINFO2_8814B << BIT_SHIFT_QINFO2_8814B)\n#define BIT_CLEAR_QINFO2_8814B(x) ((x) & (~BITS_QINFO2_8814B))\n#define BIT_GET_QINFO2_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_QINFO2_8814B) & BIT_MASK_QINFO2_8814B)\n#define BIT_SET_QINFO2_8814B(x, v)                                             \\\n\t(BIT_CLEAR_QINFO2_8814B(x) | BIT_QINFO2_8814B(v))\n\n/* 2 REG_QUEUELIST_INFO3_8814B */\n\n#define BIT_SHIFT_QINFO3_8814B 0\n#define BIT_MASK_QINFO3_8814B 0xffffffffL\n#define BIT_QINFO3_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_QINFO3_8814B) << BIT_SHIFT_QINFO3_8814B)\n#define BITS_QINFO3_8814B (BIT_MASK_QINFO3_8814B << BIT_SHIFT_QINFO3_8814B)\n#define BIT_CLEAR_QINFO3_8814B(x) ((x) & (~BITS_QINFO3_8814B))\n#define BIT_GET_QINFO3_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_QINFO3_8814B) & BIT_MASK_QINFO3_8814B)\n#define BIT_SET_QINFO3_8814B(x, v)                                             \\\n\t(BIT_CLEAR_QINFO3_8814B(x) | BIT_QINFO3_8814B(v))\n\n/* 2 REG_QUEUELIST_INFO_EMPTY_8814B */\n#define BIT_FWCMDQ_EMPTY_8814B BIT(31)\n#define BIT_MGQ_CPU_EMPTY_V1_8814B BIT(30)\n#define BIT_BCNQ_EMPTY_EXTP0_8814B BIT(29)\n#define BIT_BCNQ_EMPTY_PORT4_8814B BIT(28)\n#define BIT_BCNQ_EMPTY_PORT3_8814B BIT(27)\n#define BIT_BCNQ_EMPTY_PORT2_8814B BIT(26)\n#define BIT_BCNQ_EMPTY_PORT1_8814B BIT(25)\n#define BIT_BCNQ_EMPTY_PORT0_8814B BIT(24)\n#define BIT_HQQ_EMPTY_V1_8814B BIT(23)\n#define BIT_MQQ_EMPTY_V2_8814B BIT(22)\n#define BIT_S1_EMPTY_8814B BIT(21)\n#define BIT_S0_EMPTY_8814B BIT(20)\n#define BIT_AC19Q_EMPTY_8814B BIT(19)\n#define BIT_AC18Q_EMPTY_8814B BIT(18)\n#define BIT_AC17Q_EMPTY_8814B BIT(17)\n#define BIT_AC16Q_EMPTY_8814B BIT(16)\n#define BIT_AC15Q_EMPTY_8814B BIT(15)\n#define BIT_AC14Q_EMPTY_8814B BIT(14)\n#define BIT_AC13Q_EMPTY_8814B BIT(13)\n#define BIT_AC12Q_EMPTY_8814B BIT(12)\n#define BIT_AC11Q_EMPTY_8814B BIT(11)\n#define BIT_AC10Q_EMPTY_8814B BIT(10)\n#define BIT_AC9Q_EMPTY_8814B BIT(9)\n#define BIT_AC8Q_EMPTY_8814B BIT(8)\n#define BIT_AC7Q_EMPTY_8814B BIT(7)\n#define BIT_AC6Q_EMPTY_8814B BIT(6)\n#define BIT_AC5Q_EMPTY_8814B BIT(5)\n#define BIT_AC4Q_EMPTY_8814B BIT(4)\n#define BIT_AC3Q_EMPTY_8814B BIT(3)\n#define BIT_AC2Q_EMPTY_8814B BIT(2)\n#define BIT_AC1Q_EMPTY_8814B BIT(1)\n#define BIT_AC0Q_EMPTY_8814B BIT(0)\n\n/* 2 REG_QUEUELIST_ACQ_EN_8814B */\n\n#define BIT_SHIFT_QINFO_CTRL_8814B 24\n#define BIT_MASK_QINFO_CTRL_8814B 0x3f\n#define BIT_QINFO_CTRL_8814B(x)                                                \\\n\t(((x) & BIT_MASK_QINFO_CTRL_8814B) << BIT_SHIFT_QINFO_CTRL_8814B)\n#define BITS_QINFO_CTRL_8814B                                                  \\\n\t(BIT_MASK_QINFO_CTRL_8814B << BIT_SHIFT_QINFO_CTRL_8814B)\n#define BIT_CLEAR_QINFO_CTRL_8814B(x) ((x) & (~BITS_QINFO_CTRL_8814B))\n#define BIT_GET_QINFO_CTRL_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_QINFO_CTRL_8814B) & BIT_MASK_QINFO_CTRL_8814B)\n#define BIT_SET_QINFO_CTRL_8814B(x, v)                                         \\\n\t(BIT_CLEAR_QINFO_CTRL_8814B(x) | BIT_QINFO_CTRL_8814B(v))\n\n#define BIT_SHIFT_QINFO_MODE_BAND_8814B 20\n#define BIT_MASK_QINFO_MODE_BAND_8814B 0x7\n#define BIT_QINFO_MODE_BAND_8814B(x)                                           \\\n\t(((x) & BIT_MASK_QINFO_MODE_BAND_8814B)                                \\\n\t << BIT_SHIFT_QINFO_MODE_BAND_8814B)\n#define BITS_QINFO_MODE_BAND_8814B                                             \\\n\t(BIT_MASK_QINFO_MODE_BAND_8814B << BIT_SHIFT_QINFO_MODE_BAND_8814B)\n#define BIT_CLEAR_QINFO_MODE_BAND_8814B(x) ((x) & (~BITS_QINFO_MODE_BAND_8814B))\n#define BIT_GET_QINFO_MODE_BAND_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_QINFO_MODE_BAND_8814B) &                            \\\n\t BIT_MASK_QINFO_MODE_BAND_8814B)\n#define BIT_SET_QINFO_MODE_BAND_8814B(x, v)                                    \\\n\t(BIT_CLEAR_QINFO_MODE_BAND_8814B(x) | BIT_QINFO_MODE_BAND_8814B(v))\n\n#define BIT_ACQ19_ENABLE_8814B BIT(19)\n#define BIT_ACQ18_ENABLE_8814B BIT(18)\n#define BIT_ACQ17_ENABLE_8814B BIT(17)\n#define BIT_ACQ16_ENABLE_8814B BIT(16)\n#define BIT_ACQ15_ENABLE_8814B BIT(15)\n#define BIT_ACQ14_ENABLE_8814B BIT(14)\n#define BIT_ACQ13_ENABLE_8814B BIT(13)\n#define BIT_ACQ12_ENABLE_8814B BIT(12)\n#define BIT_ACQ11_ENABLE_8814B BIT(11)\n#define BIT_ACQ10_ENABLE_8814B BIT(10)\n#define BIT_ACQ9_ENABLE_8814B BIT(9)\n#define BIT_ACQ8_ENABLE_8814B BIT(8)\n#define BIT_ACQ7_ENABLE_8814B BIT(7)\n#define BIT_ACQ6_ENABLE_8814B BIT(6)\n#define BIT_ACQ5_ENABLE_8814B BIT(5)\n#define BIT_ACQ4_ENABLE_8814B BIT(4)\n#define BIT_ACQ3_ENABLE_8814B BIT(3)\n#define BIT_ACQ2_ENABLE_8814B BIT(2)\n#define BIT_ACQ1_ENABLE_8814B BIT(1)\n#define BIT_ACQ0_ENABLE_8814B BIT(0)\n\n/* 2 REG_BCNQ_BDNY_V2_8814B */\n\n#define BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B 28\n#define BIT_MASK_BCNQ_PGBNDY_WSEL_8814B 0x7\n#define BIT_BCNQ_PGBNDY_WSEL_8814B(x)                                          \\\n\t(((x) & BIT_MASK_BCNQ_PGBNDY_WSEL_8814B)                               \\\n\t << BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B)\n#define BITS_BCNQ_PGBNDY_WSEL_8814B                                            \\\n\t(BIT_MASK_BCNQ_PGBNDY_WSEL_8814B << BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B)\n#define BIT_CLEAR_BCNQ_PGBNDY_WSEL_8814B(x)                                    \\\n\t((x) & (~BITS_BCNQ_PGBNDY_WSEL_8814B))\n#define BIT_GET_BCNQ_PGBNDY_WSEL_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B) &                           \\\n\t BIT_MASK_BCNQ_PGBNDY_WSEL_8814B)\n#define BIT_SET_BCNQ_PGBNDY_WSEL_8814B(x, v)                                   \\\n\t(BIT_CLEAR_BCNQ_PGBNDY_WSEL_8814B(x) | BIT_BCNQ_PGBNDY_WSEL_8814B(v))\n\n#define BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B 12\n#define BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B 0xfff\n#define BIT_BCNQ_PGBNDY_RCONTENT_8814B(x)                                      \\\n\t(((x) & BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B)                           \\\n\t << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B)\n#define BITS_BCNQ_PGBNDY_RCONTENT_8814B                                        \\\n\t(BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B                                   \\\n\t << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B)\n#define BIT_CLEAR_BCNQ_PGBNDY_RCONTENT_8814B(x)                                \\\n\t((x) & (~BITS_BCNQ_PGBNDY_RCONTENT_8814B))\n#define BIT_GET_BCNQ_PGBNDY_RCONTENT_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B) &                       \\\n\t BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B)\n#define BIT_SET_BCNQ_PGBNDY_RCONTENT_8814B(x, v)                               \\\n\t(BIT_CLEAR_BCNQ_PGBNDY_RCONTENT_8814B(x) |                             \\\n\t BIT_BCNQ_PGBNDY_RCONTENT_8814B(v))\n\n#define BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B 0\n#define BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B 0xfff\n#define BIT_BCNQ_PGBNDY_WCONTENT_8814B(x)                                      \\\n\t(((x) & BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B)                           \\\n\t << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B)\n#define BITS_BCNQ_PGBNDY_WCONTENT_8814B                                        \\\n\t(BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B                                   \\\n\t << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B)\n#define BIT_CLEAR_BCNQ_PGBNDY_WCONTENT_8814B(x)                                \\\n\t((x) & (~BITS_BCNQ_PGBNDY_WCONTENT_8814B))\n#define BIT_GET_BCNQ_PGBNDY_WCONTENT_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B) &                       \\\n\t BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B)\n#define BIT_SET_BCNQ_PGBNDY_WCONTENT_8814B(x, v)                               \\\n\t(BIT_CLEAR_BCNQ_PGBNDY_WCONTENT_8814B(x) |                             \\\n\t BIT_BCNQ_PGBNDY_WCONTENT_8814B(v))\n\n/* 2 REG_CPU_MGQ_INFO_8814B */\n#define BIT_CPUMGT_CLR_V1_8814B BIT(30)\n#define BIT_CPUMGT_POLL_8814B BIT(29)\n#define BIT_BCN_EXT_POLL_8814B BIT(21)\n#define BIT_BCN4_POLL_8814B BIT(20)\n#define BIT_BCN3_POLL_8814B BIT(19)\n#define BIT_BCN2_POLL_8814B BIT(18)\n#define BIT_BCN1_POLL_V1_8814B BIT(17)\n#define BIT_BCN_POLL_V1_8814B BIT(16)\n\n#define BIT_SHIFT_FREE_TAIL_PAGE_8814B 0\n#define BIT_MASK_FREE_TAIL_PAGE_8814B 0xfff\n#define BIT_FREE_TAIL_PAGE_8814B(x)                                            \\\n\t(((x) & BIT_MASK_FREE_TAIL_PAGE_8814B)                                 \\\n\t << BIT_SHIFT_FREE_TAIL_PAGE_8814B)\n#define BITS_FREE_TAIL_PAGE_8814B                                              \\\n\t(BIT_MASK_FREE_TAIL_PAGE_8814B << BIT_SHIFT_FREE_TAIL_PAGE_8814B)\n#define BIT_CLEAR_FREE_TAIL_PAGE_8814B(x) ((x) & (~BITS_FREE_TAIL_PAGE_8814B))\n#define BIT_GET_FREE_TAIL_PAGE_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_FREE_TAIL_PAGE_8814B) &                             \\\n\t BIT_MASK_FREE_TAIL_PAGE_8814B)\n#define BIT_SET_FREE_TAIL_PAGE_8814B(x, v)                                     \\\n\t(BIT_CLEAR_FREE_TAIL_PAGE_8814B(x) | BIT_FREE_TAIL_PAGE_8814B(v))\n\n/* 2 REG_FWHW_TXQ_CTRL_8814B */\n#define BIT_RTS_LIMIT_IN_OFDM_8814B BIT(23)\n#define BIT_EN_RD_RESP_NAV_BK_8814B BIT(21)\n#define BIT_EN_WR_FREE_TAIL_8814B BIT(20)\n#define BIT_NOTXRPT_USERATE_EN_8814B BIT(19)\n#define BIT_DIS_TXFAIL_RPT_8814B BIT(18)\n#define BIT_FTM_TIMEOUT_BYPASS_8814B BIT(16)\n#define BIT_EN_BCNQ_DL5_8814B BIT(13)\n#define BIT_EN_BCNQ_DL4_8814B BIT(12)\n#define BIT_EN_BCNQ_DL3_8814B BIT(11)\n#define BIT_EN_BCNQ_DL2_8814B BIT(10)\n#define BIT_EN_BCNQ_DL1_8814B BIT(9)\n#define BIT_EN_BCNQ_DL0_8814B BIT(8)\n#define BIT_EN_RTY_BK_8814B BIT(7)\n#define BIT_EN_USE_INI_RAT_8814B BIT(6)\n#define BIT_EN_RTS_NAV_BK_8814B BIT(5)\n#define BIT_DIS_SSN_CHECK_8814B BIT(4)\n#define BIT_MACID_MATCH_RTS_8814B BIT(3)\n#define BIT_EN_BCN_TRXRPT_V1_8814B BIT(2)\n#define BIT_EN_FTMRPT_V1_8814B BIT(1)\n#define BIT_BMC_NAV_PROTECT_8814B BIT(0)\n\n/* 2 REG_DATAFB_SEL_8814B */\n#define BIT_BROADCAST_RTY_EN_8814B BIT(3)\n#define BIT_EN_RTY_BK_COD_8814B BIT(2)\n\n#define BIT_SHIFT__DATA_FALLBACK_SEL_8814B 0\n#define BIT_MASK__DATA_FALLBACK_SEL_8814B 0x3\n#define BIT__DATA_FALLBACK_SEL_8814B(x)                                        \\\n\t(((x) & BIT_MASK__DATA_FALLBACK_SEL_8814B)                             \\\n\t << BIT_SHIFT__DATA_FALLBACK_SEL_8814B)\n#define BITS__DATA_FALLBACK_SEL_8814B                                          \\\n\t(BIT_MASK__DATA_FALLBACK_SEL_8814B                                     \\\n\t << BIT_SHIFT__DATA_FALLBACK_SEL_8814B)\n#define BIT_CLEAR__DATA_FALLBACK_SEL_8814B(x)                                  \\\n\t((x) & (~BITS__DATA_FALLBACK_SEL_8814B))\n#define BIT_GET__DATA_FALLBACK_SEL_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT__DATA_FALLBACK_SEL_8814B) &                         \\\n\t BIT_MASK__DATA_FALLBACK_SEL_8814B)\n#define BIT_SET__DATA_FALLBACK_SEL_8814B(x, v)                                 \\\n\t(BIT_CLEAR__DATA_FALLBACK_SEL_8814B(x) |                               \\\n\t BIT__DATA_FALLBACK_SEL_8814B(v))\n\n/* 2 REG_TXBDNY_8814B */\n\n#define BIT_SHIFT_TXBNDY_8814B 0\n#define BIT_MASK_TXBNDY_8814B 0xfff\n#define BIT_TXBNDY_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_TXBNDY_8814B) << BIT_SHIFT_TXBNDY_8814B)\n#define BITS_TXBNDY_8814B (BIT_MASK_TXBNDY_8814B << BIT_SHIFT_TXBNDY_8814B)\n#define BIT_CLEAR_TXBNDY_8814B(x) ((x) & (~BITS_TXBNDY_8814B))\n#define BIT_GET_TXBNDY_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_TXBNDY_8814B) & BIT_MASK_TXBNDY_8814B)\n#define BIT_SET_TXBNDY_8814B(x, v)                                             \\\n\t(BIT_CLEAR_TXBNDY_8814B(x) | BIT_TXBNDY_8814B(v))\n\n/* 2 REG_LIFETIME_EN_8814B */\n#define BIT_BT_INT_CPU_8814B BIT(7)\n#define BIT_BT_INT_PTA_8814B BIT(6)\n#define BIT_EN_CTRL_RTYBIT_8814B BIT(4)\n#define BIT_LIFETIME_BK_EN_8814B BIT(3)\n#define BIT_LIFETIME_BE_EN_8814B BIT(2)\n#define BIT_LIFETIME_VI_EN_8814B BIT(1)\n#define BIT_LIFETIME_VO_EN_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_SPEC_SIFS_8814B */\n\n#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B 8\n#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B 0xff\n#define BIT_SPEC_SIFS_OFDM_PTCL_8814B(x)                                       \\\n\t(((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B)                            \\\n\t << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B)\n#define BITS_SPEC_SIFS_OFDM_PTCL_8814B                                         \\\n\t(BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B                                    \\\n\t << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B)\n#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8814B(x)                                 \\\n\t((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8814B))\n#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B) &                        \\\n\t BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B)\n#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8814B(x, v)                                \\\n\t(BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8814B(x) |                              \\\n\t BIT_SPEC_SIFS_OFDM_PTCL_8814B(v))\n\n#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B 0\n#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B 0xff\n#define BIT_SPEC_SIFS_CCK_PTCL_8814B(x)                                        \\\n\t(((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B)                             \\\n\t << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B)\n#define BITS_SPEC_SIFS_CCK_PTCL_8814B                                          \\\n\t(BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B                                     \\\n\t << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B)\n#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8814B(x)                                  \\\n\t((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8814B))\n#define BIT_GET_SPEC_SIFS_CCK_PTCL_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B) &                         \\\n\t BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B)\n#define BIT_SET_SPEC_SIFS_CCK_PTCL_8814B(x, v)                                 \\\n\t(BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8814B(x) |                               \\\n\t BIT_SPEC_SIFS_CCK_PTCL_8814B(v))\n\n/* 2 REG_RETRY_LIMIT_8814B */\n\n#define BIT_SHIFT_SRL_8814B 8\n#define BIT_MASK_SRL_8814B 0x3f\n#define BIT_SRL_8814B(x) (((x) & BIT_MASK_SRL_8814B) << BIT_SHIFT_SRL_8814B)\n#define BITS_SRL_8814B (BIT_MASK_SRL_8814B << BIT_SHIFT_SRL_8814B)\n#define BIT_CLEAR_SRL_8814B(x) ((x) & (~BITS_SRL_8814B))\n#define BIT_GET_SRL_8814B(x) (((x) >> BIT_SHIFT_SRL_8814B) & BIT_MASK_SRL_8814B)\n#define BIT_SET_SRL_8814B(x, v) (BIT_CLEAR_SRL_8814B(x) | BIT_SRL_8814B(v))\n\n#define BIT_SHIFT_LRL_8814B 0\n#define BIT_MASK_LRL_8814B 0x3f\n#define BIT_LRL_8814B(x) (((x) & BIT_MASK_LRL_8814B) << BIT_SHIFT_LRL_8814B)\n#define BITS_LRL_8814B (BIT_MASK_LRL_8814B << BIT_SHIFT_LRL_8814B)\n#define BIT_CLEAR_LRL_8814B(x) ((x) & (~BITS_LRL_8814B))\n#define BIT_GET_LRL_8814B(x) (((x) >> BIT_SHIFT_LRL_8814B) & BIT_MASK_LRL_8814B)\n#define BIT_SET_LRL_8814B(x, v) (BIT_CLEAR_LRL_8814B(x) | BIT_LRL_8814B(v))\n\n/* 2 REG_TXBF_CTRL_8814B */\n#define BIT_ENABLE_NDPA_8814B BIT(31)\n#define BIT_NDPA_PARA_8814B BIT(30)\n#define BIT_PROP_TXBF_8814B BIT(29)\n#define BIT_EN_NDPA_INT_8814B BIT(28)\n#define BIT_TXBF1_80M_160M_8814B BIT(27)\n#define BIT_TXBF1_40M_8814B BIT(26)\n#define BIT_TXBF1_20M_8814B BIT(25)\n\n#define BIT_SHIFT_TXBF1_AID_8814B 16\n#define BIT_MASK_TXBF1_AID_8814B 0x1ff\n#define BIT_TXBF1_AID_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_TXBF1_AID_8814B) << BIT_SHIFT_TXBF1_AID_8814B)\n#define BITS_TXBF1_AID_8814B                                                   \\\n\t(BIT_MASK_TXBF1_AID_8814B << BIT_SHIFT_TXBF1_AID_8814B)\n#define BIT_CLEAR_TXBF1_AID_8814B(x) ((x) & (~BITS_TXBF1_AID_8814B))\n#define BIT_GET_TXBF1_AID_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXBF1_AID_8814B) & BIT_MASK_TXBF1_AID_8814B)\n#define BIT_SET_TXBF1_AID_8814B(x, v)                                          \\\n\t(BIT_CLEAR_TXBF1_AID_8814B(x) | BIT_TXBF1_AID_8814B(v))\n\n#define BIT_DIS_NDP_BFEN_8814B BIT(15)\n#define BIT_TXBCN_NOBLOCK_NDP_8814B BIT(14)\n#define BIT_TXBF0_80M_160M_8814B BIT(11)\n#define BIT_TXBF0_40M_8814B BIT(10)\n#define BIT_TXBF0_20M_8814B BIT(9)\n\n#define BIT_SHIFT_TXBF0_AID_8814B 0\n#define BIT_MASK_TXBF0_AID_8814B 0x1ff\n#define BIT_TXBF0_AID_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_TXBF0_AID_8814B) << BIT_SHIFT_TXBF0_AID_8814B)\n#define BITS_TXBF0_AID_8814B                                                   \\\n\t(BIT_MASK_TXBF0_AID_8814B << BIT_SHIFT_TXBF0_AID_8814B)\n#define BIT_CLEAR_TXBF0_AID_8814B(x) ((x) & (~BITS_TXBF0_AID_8814B))\n#define BIT_GET_TXBF0_AID_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXBF0_AID_8814B) & BIT_MASK_TXBF0_AID_8814B)\n#define BIT_SET_TXBF0_AID_8814B(x, v)                                          \\\n\t(BIT_CLEAR_TXBF0_AID_8814B(x) | BIT_TXBF0_AID_8814B(v))\n\n/* 2 REG_DARFRC_8814B */\n\n#define BIT_SHIFT_DARF_RC4_V1_8814B 24\n#define BIT_MASK_DARF_RC4_V1_8814B 0x3f\n#define BIT_DARF_RC4_V1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC4_V1_8814B) << BIT_SHIFT_DARF_RC4_V1_8814B)\n#define BITS_DARF_RC4_V1_8814B                                                 \\\n\t(BIT_MASK_DARF_RC4_V1_8814B << BIT_SHIFT_DARF_RC4_V1_8814B)\n#define BIT_CLEAR_DARF_RC4_V1_8814B(x) ((x) & (~BITS_DARF_RC4_V1_8814B))\n#define BIT_GET_DARF_RC4_V1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC4_V1_8814B) & BIT_MASK_DARF_RC4_V1_8814B)\n#define BIT_SET_DARF_RC4_V1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC4_V1_8814B(x) | BIT_DARF_RC4_V1_8814B(v))\n\n#define BIT_SHIFT_DARF_RC3_V1_8814B 16\n#define BIT_MASK_DARF_RC3_V1_8814B 0x3f\n#define BIT_DARF_RC3_V1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC3_V1_8814B) << BIT_SHIFT_DARF_RC3_V1_8814B)\n#define BITS_DARF_RC3_V1_8814B                                                 \\\n\t(BIT_MASK_DARF_RC3_V1_8814B << BIT_SHIFT_DARF_RC3_V1_8814B)\n#define BIT_CLEAR_DARF_RC3_V1_8814B(x) ((x) & (~BITS_DARF_RC3_V1_8814B))\n#define BIT_GET_DARF_RC3_V1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC3_V1_8814B) & BIT_MASK_DARF_RC3_V1_8814B)\n#define BIT_SET_DARF_RC3_V1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC3_V1_8814B(x) | BIT_DARF_RC3_V1_8814B(v))\n\n#define BIT_SHIFT_DARF_RC2_V1_8814B 8\n#define BIT_MASK_DARF_RC2_V1_8814B 0x3f\n#define BIT_DARF_RC2_V1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC2_V1_8814B) << BIT_SHIFT_DARF_RC2_V1_8814B)\n#define BITS_DARF_RC2_V1_8814B                                                 \\\n\t(BIT_MASK_DARF_RC2_V1_8814B << BIT_SHIFT_DARF_RC2_V1_8814B)\n#define BIT_CLEAR_DARF_RC2_V1_8814B(x) ((x) & (~BITS_DARF_RC2_V1_8814B))\n#define BIT_GET_DARF_RC2_V1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC2_V1_8814B) & BIT_MASK_DARF_RC2_V1_8814B)\n#define BIT_SET_DARF_RC2_V1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC2_V1_8814B(x) | BIT_DARF_RC2_V1_8814B(v))\n\n#define BIT_SHIFT_DARF_RC1_V1_8814B 0\n#define BIT_MASK_DARF_RC1_V1_8814B 0x3f\n#define BIT_DARF_RC1_V1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC1_V1_8814B) << BIT_SHIFT_DARF_RC1_V1_8814B)\n#define BITS_DARF_RC1_V1_8814B                                                 \\\n\t(BIT_MASK_DARF_RC1_V1_8814B << BIT_SHIFT_DARF_RC1_V1_8814B)\n#define BIT_CLEAR_DARF_RC1_V1_8814B(x) ((x) & (~BITS_DARF_RC1_V1_8814B))\n#define BIT_GET_DARF_RC1_V1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC1_V1_8814B) & BIT_MASK_DARF_RC1_V1_8814B)\n#define BIT_SET_DARF_RC1_V1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC1_V1_8814B(x) | BIT_DARF_RC1_V1_8814B(v))\n\n/* 2 REG_DARFRCH_8814B */\n\n#define BIT_SHIFT_DARF_RC8_V2_8814B 24\n#define BIT_MASK_DARF_RC8_V2_8814B 0x3f\n#define BIT_DARF_RC8_V2_8814B(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC8_V2_8814B) << BIT_SHIFT_DARF_RC8_V2_8814B)\n#define BITS_DARF_RC8_V2_8814B                                                 \\\n\t(BIT_MASK_DARF_RC8_V2_8814B << BIT_SHIFT_DARF_RC8_V2_8814B)\n#define BIT_CLEAR_DARF_RC8_V2_8814B(x) ((x) & (~BITS_DARF_RC8_V2_8814B))\n#define BIT_GET_DARF_RC8_V2_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC8_V2_8814B) & BIT_MASK_DARF_RC8_V2_8814B)\n#define BIT_SET_DARF_RC8_V2_8814B(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC8_V2_8814B(x) | BIT_DARF_RC8_V2_8814B(v))\n\n#define BIT_SHIFT_DARF_RC7_V2_8814B 16\n#define BIT_MASK_DARF_RC7_V2_8814B 0x3f\n#define BIT_DARF_RC7_V2_8814B(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC7_V2_8814B) << BIT_SHIFT_DARF_RC7_V2_8814B)\n#define BITS_DARF_RC7_V2_8814B                                                 \\\n\t(BIT_MASK_DARF_RC7_V2_8814B << BIT_SHIFT_DARF_RC7_V2_8814B)\n#define BIT_CLEAR_DARF_RC7_V2_8814B(x) ((x) & (~BITS_DARF_RC7_V2_8814B))\n#define BIT_GET_DARF_RC7_V2_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC7_V2_8814B) & BIT_MASK_DARF_RC7_V2_8814B)\n#define BIT_SET_DARF_RC7_V2_8814B(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC7_V2_8814B(x) | BIT_DARF_RC7_V2_8814B(v))\n\n#define BIT_SHIFT_DARF_RC6_V2_8814B 8\n#define BIT_MASK_DARF_RC6_V2_8814B 0x3f\n#define BIT_DARF_RC6_V2_8814B(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC6_V2_8814B) << BIT_SHIFT_DARF_RC6_V2_8814B)\n#define BITS_DARF_RC6_V2_8814B                                                 \\\n\t(BIT_MASK_DARF_RC6_V2_8814B << BIT_SHIFT_DARF_RC6_V2_8814B)\n#define BIT_CLEAR_DARF_RC6_V2_8814B(x) ((x) & (~BITS_DARF_RC6_V2_8814B))\n#define BIT_GET_DARF_RC6_V2_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC6_V2_8814B) & BIT_MASK_DARF_RC6_V2_8814B)\n#define BIT_SET_DARF_RC6_V2_8814B(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC6_V2_8814B(x) | BIT_DARF_RC6_V2_8814B(v))\n\n#define BIT_SHIFT_DARF_RC5_V2_8814B 0\n#define BIT_MASK_DARF_RC5_V2_8814B 0x3f\n#define BIT_DARF_RC5_V2_8814B(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC5_V2_8814B) << BIT_SHIFT_DARF_RC5_V2_8814B)\n#define BITS_DARF_RC5_V2_8814B                                                 \\\n\t(BIT_MASK_DARF_RC5_V2_8814B << BIT_SHIFT_DARF_RC5_V2_8814B)\n#define BIT_CLEAR_DARF_RC5_V2_8814B(x) ((x) & (~BITS_DARF_RC5_V2_8814B))\n#define BIT_GET_DARF_RC5_V2_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC5_V2_8814B) & BIT_MASK_DARF_RC5_V2_8814B)\n#define BIT_SET_DARF_RC5_V2_8814B(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC5_V2_8814B(x) | BIT_DARF_RC5_V2_8814B(v))\n\n/* 2 REG_RARFRC_8814B */\n\n#define BIT_SHIFT_RARF_RC4_8814B 24\n#define BIT_MASK_RARF_RC4_8814B 0x1f\n#define BIT_RARF_RC4_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC4_8814B) << BIT_SHIFT_RARF_RC4_8814B)\n#define BITS_RARF_RC4_8814B                                                    \\\n\t(BIT_MASK_RARF_RC4_8814B << BIT_SHIFT_RARF_RC4_8814B)\n#define BIT_CLEAR_RARF_RC4_8814B(x) ((x) & (~BITS_RARF_RC4_8814B))\n#define BIT_GET_RARF_RC4_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC4_8814B) & BIT_MASK_RARF_RC4_8814B)\n#define BIT_SET_RARF_RC4_8814B(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC4_8814B(x) | BIT_RARF_RC4_8814B(v))\n\n#define BIT_SHIFT_RARF_RC3_8814B 16\n#define BIT_MASK_RARF_RC3_8814B 0x1f\n#define BIT_RARF_RC3_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC3_8814B) << BIT_SHIFT_RARF_RC3_8814B)\n#define BITS_RARF_RC3_8814B                                                    \\\n\t(BIT_MASK_RARF_RC3_8814B << BIT_SHIFT_RARF_RC3_8814B)\n#define BIT_CLEAR_RARF_RC3_8814B(x) ((x) & (~BITS_RARF_RC3_8814B))\n#define BIT_GET_RARF_RC3_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC3_8814B) & BIT_MASK_RARF_RC3_8814B)\n#define BIT_SET_RARF_RC3_8814B(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC3_8814B(x) | BIT_RARF_RC3_8814B(v))\n\n#define BIT_SHIFT_RARF_RC2_8814B 8\n#define BIT_MASK_RARF_RC2_8814B 0x1f\n#define BIT_RARF_RC2_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC2_8814B) << BIT_SHIFT_RARF_RC2_8814B)\n#define BITS_RARF_RC2_8814B                                                    \\\n\t(BIT_MASK_RARF_RC2_8814B << BIT_SHIFT_RARF_RC2_8814B)\n#define BIT_CLEAR_RARF_RC2_8814B(x) ((x) & (~BITS_RARF_RC2_8814B))\n#define BIT_GET_RARF_RC2_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC2_8814B) & BIT_MASK_RARF_RC2_8814B)\n#define BIT_SET_RARF_RC2_8814B(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC2_8814B(x) | BIT_RARF_RC2_8814B(v))\n\n#define BIT_SHIFT_RARF_RC1_8814B 0\n#define BIT_MASK_RARF_RC1_8814B 0x1f\n#define BIT_RARF_RC1_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC1_8814B) << BIT_SHIFT_RARF_RC1_8814B)\n#define BITS_RARF_RC1_8814B                                                    \\\n\t(BIT_MASK_RARF_RC1_8814B << BIT_SHIFT_RARF_RC1_8814B)\n#define BIT_CLEAR_RARF_RC1_8814B(x) ((x) & (~BITS_RARF_RC1_8814B))\n#define BIT_GET_RARF_RC1_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC1_8814B) & BIT_MASK_RARF_RC1_8814B)\n#define BIT_SET_RARF_RC1_8814B(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC1_8814B(x) | BIT_RARF_RC1_8814B(v))\n\n/* 2 REG_RARFRCH_8814B */\n\n#define BIT_SHIFT_RARF_RC8_V1_8814B 24\n#define BIT_MASK_RARF_RC8_V1_8814B 0x1f\n#define BIT_RARF_RC8_V1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_RARF_RC8_V1_8814B) << BIT_SHIFT_RARF_RC8_V1_8814B)\n#define BITS_RARF_RC8_V1_8814B                                                 \\\n\t(BIT_MASK_RARF_RC8_V1_8814B << BIT_SHIFT_RARF_RC8_V1_8814B)\n#define BIT_CLEAR_RARF_RC8_V1_8814B(x) ((x) & (~BITS_RARF_RC8_V1_8814B))\n#define BIT_GET_RARF_RC8_V1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_RARF_RC8_V1_8814B) & BIT_MASK_RARF_RC8_V1_8814B)\n#define BIT_SET_RARF_RC8_V1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_RARF_RC8_V1_8814B(x) | BIT_RARF_RC8_V1_8814B(v))\n\n#define BIT_SHIFT_RARF_RC7_V1_8814B 16\n#define BIT_MASK_RARF_RC7_V1_8814B 0x1f\n#define BIT_RARF_RC7_V1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_RARF_RC7_V1_8814B) << BIT_SHIFT_RARF_RC7_V1_8814B)\n#define BITS_RARF_RC7_V1_8814B                                                 \\\n\t(BIT_MASK_RARF_RC7_V1_8814B << BIT_SHIFT_RARF_RC7_V1_8814B)\n#define BIT_CLEAR_RARF_RC7_V1_8814B(x) ((x) & (~BITS_RARF_RC7_V1_8814B))\n#define BIT_GET_RARF_RC7_V1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_RARF_RC7_V1_8814B) & BIT_MASK_RARF_RC7_V1_8814B)\n#define BIT_SET_RARF_RC7_V1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_RARF_RC7_V1_8814B(x) | BIT_RARF_RC7_V1_8814B(v))\n\n#define BIT_SHIFT_RARF_RC6_V1_8814B 8\n#define BIT_MASK_RARF_RC6_V1_8814B 0x1f\n#define BIT_RARF_RC6_V1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_RARF_RC6_V1_8814B) << BIT_SHIFT_RARF_RC6_V1_8814B)\n#define BITS_RARF_RC6_V1_8814B                                                 \\\n\t(BIT_MASK_RARF_RC6_V1_8814B << BIT_SHIFT_RARF_RC6_V1_8814B)\n#define BIT_CLEAR_RARF_RC6_V1_8814B(x) ((x) & (~BITS_RARF_RC6_V1_8814B))\n#define BIT_GET_RARF_RC6_V1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_RARF_RC6_V1_8814B) & BIT_MASK_RARF_RC6_V1_8814B)\n#define BIT_SET_RARF_RC6_V1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_RARF_RC6_V1_8814B(x) | BIT_RARF_RC6_V1_8814B(v))\n\n#define BIT_SHIFT_RARF_RC5_V1_8814B 0\n#define BIT_MASK_RARF_RC5_V1_8814B 0x1f\n#define BIT_RARF_RC5_V1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_RARF_RC5_V1_8814B) << BIT_SHIFT_RARF_RC5_V1_8814B)\n#define BITS_RARF_RC5_V1_8814B                                                 \\\n\t(BIT_MASK_RARF_RC5_V1_8814B << BIT_SHIFT_RARF_RC5_V1_8814B)\n#define BIT_CLEAR_RARF_RC5_V1_8814B(x) ((x) & (~BITS_RARF_RC5_V1_8814B))\n#define BIT_GET_RARF_RC5_V1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_RARF_RC5_V1_8814B) & BIT_MASK_RARF_RC5_V1_8814B)\n#define BIT_SET_RARF_RC5_V1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_RARF_RC5_V1_8814B(x) | BIT_RARF_RC5_V1_8814B(v))\n\n/* 2 REG_RRSR_8814B */\n\n#define BIT_SHIFT_RRSR_RSC_8814B 21\n#define BIT_MASK_RRSR_RSC_8814B 0x3\n#define BIT_RRSR_RSC_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_RRSR_RSC_8814B) << BIT_SHIFT_RRSR_RSC_8814B)\n#define BITS_RRSR_RSC_8814B                                                    \\\n\t(BIT_MASK_RRSR_RSC_8814B << BIT_SHIFT_RRSR_RSC_8814B)\n#define BIT_CLEAR_RRSR_RSC_8814B(x) ((x) & (~BITS_RRSR_RSC_8814B))\n#define BIT_GET_RRSR_RSC_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RRSR_RSC_8814B) & BIT_MASK_RRSR_RSC_8814B)\n#define BIT_SET_RRSR_RSC_8814B(x, v)                                           \\\n\t(BIT_CLEAR_RRSR_RSC_8814B(x) | BIT_RRSR_RSC_8814B(v))\n\n#define BIT_SHIFT_RRSC_BITMAP_8814B 0\n#define BIT_MASK_RRSC_BITMAP_8814B 0xfffff\n#define BIT_RRSC_BITMAP_8814B(x)                                               \\\n\t(((x) & BIT_MASK_RRSC_BITMAP_8814B) << BIT_SHIFT_RRSC_BITMAP_8814B)\n#define BITS_RRSC_BITMAP_8814B                                                 \\\n\t(BIT_MASK_RRSC_BITMAP_8814B << BIT_SHIFT_RRSC_BITMAP_8814B)\n#define BIT_CLEAR_RRSC_BITMAP_8814B(x) ((x) & (~BITS_RRSC_BITMAP_8814B))\n#define BIT_GET_RRSC_BITMAP_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_RRSC_BITMAP_8814B) & BIT_MASK_RRSC_BITMAP_8814B)\n#define BIT_SET_RRSC_BITMAP_8814B(x, v)                                        \\\n\t(BIT_CLEAR_RRSC_BITMAP_8814B(x) | BIT_RRSC_BITMAP_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_ARFR0_8814B */\n\n#define BIT_SHIFT_ARFRL0_8814B 0\n#define BIT_MASK_ARFRL0_8814B 0xffffffffL\n#define BIT_ARFRL0_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRL0_8814B) << BIT_SHIFT_ARFRL0_8814B)\n#define BITS_ARFRL0_8814B (BIT_MASK_ARFRL0_8814B << BIT_SHIFT_ARFRL0_8814B)\n#define BIT_CLEAR_ARFRL0_8814B(x) ((x) & (~BITS_ARFRL0_8814B))\n#define BIT_GET_ARFRL0_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRL0_8814B) & BIT_MASK_ARFRL0_8814B)\n#define BIT_SET_ARFRL0_8814B(x, v)                                             \\\n\t(BIT_CLEAR_ARFRL0_8814B(x) | BIT_ARFRL0_8814B(v))\n\n/* 2 REG_ARFRH0_8814B */\n\n#define BIT_SHIFT_ARFRH0_8814B 0\n#define BIT_MASK_ARFRH0_8814B 0xffffffffL\n#define BIT_ARFRH0_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRH0_8814B) << BIT_SHIFT_ARFRH0_8814B)\n#define BITS_ARFRH0_8814B (BIT_MASK_ARFRH0_8814B << BIT_SHIFT_ARFRH0_8814B)\n#define BIT_CLEAR_ARFRH0_8814B(x) ((x) & (~BITS_ARFRH0_8814B))\n#define BIT_GET_ARFRH0_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRH0_8814B) & BIT_MASK_ARFRH0_8814B)\n#define BIT_SET_ARFRH0_8814B(x, v)                                             \\\n\t(BIT_CLEAR_ARFRH0_8814B(x) | BIT_ARFRH0_8814B(v))\n\n/* 2 REG_REG_ARFR_WT0_8814B */\n\n#define BIT_SHIFT_RATE7_WEIGHTING_8814B 28\n#define BIT_MASK_RATE7_WEIGHTING_8814B 0xf\n#define BIT_RATE7_WEIGHTING_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RATE7_WEIGHTING_8814B)                                \\\n\t << BIT_SHIFT_RATE7_WEIGHTING_8814B)\n#define BITS_RATE7_WEIGHTING_8814B                                             \\\n\t(BIT_MASK_RATE7_WEIGHTING_8814B << BIT_SHIFT_RATE7_WEIGHTING_8814B)\n#define BIT_CLEAR_RATE7_WEIGHTING_8814B(x) ((x) & (~BITS_RATE7_WEIGHTING_8814B))\n#define BIT_GET_RATE7_WEIGHTING_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RATE7_WEIGHTING_8814B) &                            \\\n\t BIT_MASK_RATE7_WEIGHTING_8814B)\n#define BIT_SET_RATE7_WEIGHTING_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RATE7_WEIGHTING_8814B(x) | BIT_RATE7_WEIGHTING_8814B(v))\n\n#define BIT_SHIFT_RATE6_WEIGHTING_8814B 24\n#define BIT_MASK_RATE6_WEIGHTING_8814B 0xf\n#define BIT_RATE6_WEIGHTING_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RATE6_WEIGHTING_8814B)                                \\\n\t << BIT_SHIFT_RATE6_WEIGHTING_8814B)\n#define BITS_RATE6_WEIGHTING_8814B                                             \\\n\t(BIT_MASK_RATE6_WEIGHTING_8814B << BIT_SHIFT_RATE6_WEIGHTING_8814B)\n#define BIT_CLEAR_RATE6_WEIGHTING_8814B(x) ((x) & (~BITS_RATE6_WEIGHTING_8814B))\n#define BIT_GET_RATE6_WEIGHTING_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RATE6_WEIGHTING_8814B) &                            \\\n\t BIT_MASK_RATE6_WEIGHTING_8814B)\n#define BIT_SET_RATE6_WEIGHTING_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RATE6_WEIGHTING_8814B(x) | BIT_RATE6_WEIGHTING_8814B(v))\n\n#define BIT_SHIFT_RATE5_WEIGHTING_8814B 20\n#define BIT_MASK_RATE5_WEIGHTING_8814B 0xf\n#define BIT_RATE5_WEIGHTING_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RATE5_WEIGHTING_8814B)                                \\\n\t << BIT_SHIFT_RATE5_WEIGHTING_8814B)\n#define BITS_RATE5_WEIGHTING_8814B                                             \\\n\t(BIT_MASK_RATE5_WEIGHTING_8814B << BIT_SHIFT_RATE5_WEIGHTING_8814B)\n#define BIT_CLEAR_RATE5_WEIGHTING_8814B(x) ((x) & (~BITS_RATE5_WEIGHTING_8814B))\n#define BIT_GET_RATE5_WEIGHTING_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RATE5_WEIGHTING_8814B) &                            \\\n\t BIT_MASK_RATE5_WEIGHTING_8814B)\n#define BIT_SET_RATE5_WEIGHTING_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RATE5_WEIGHTING_8814B(x) | BIT_RATE5_WEIGHTING_8814B(v))\n\n#define BIT_SHIFT_RATE4_WEIGHTING_8814B 16\n#define BIT_MASK_RATE4_WEIGHTING_8814B 0xf\n#define BIT_RATE4_WEIGHTING_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RATE4_WEIGHTING_8814B)                                \\\n\t << BIT_SHIFT_RATE4_WEIGHTING_8814B)\n#define BITS_RATE4_WEIGHTING_8814B                                             \\\n\t(BIT_MASK_RATE4_WEIGHTING_8814B << BIT_SHIFT_RATE4_WEIGHTING_8814B)\n#define BIT_CLEAR_RATE4_WEIGHTING_8814B(x) ((x) & (~BITS_RATE4_WEIGHTING_8814B))\n#define BIT_GET_RATE4_WEIGHTING_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RATE4_WEIGHTING_8814B) &                            \\\n\t BIT_MASK_RATE4_WEIGHTING_8814B)\n#define BIT_SET_RATE4_WEIGHTING_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RATE4_WEIGHTING_8814B(x) | BIT_RATE4_WEIGHTING_8814B(v))\n\n#define BIT_SHIFT_RATE3_WEIGHTING_8814B 12\n#define BIT_MASK_RATE3_WEIGHTING_8814B 0xf\n#define BIT_RATE3_WEIGHTING_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RATE3_WEIGHTING_8814B)                                \\\n\t << BIT_SHIFT_RATE3_WEIGHTING_8814B)\n#define BITS_RATE3_WEIGHTING_8814B                                             \\\n\t(BIT_MASK_RATE3_WEIGHTING_8814B << BIT_SHIFT_RATE3_WEIGHTING_8814B)\n#define BIT_CLEAR_RATE3_WEIGHTING_8814B(x) ((x) & (~BITS_RATE3_WEIGHTING_8814B))\n#define BIT_GET_RATE3_WEIGHTING_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RATE3_WEIGHTING_8814B) &                            \\\n\t BIT_MASK_RATE3_WEIGHTING_8814B)\n#define BIT_SET_RATE3_WEIGHTING_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RATE3_WEIGHTING_8814B(x) | BIT_RATE3_WEIGHTING_8814B(v))\n\n#define BIT_SHIFT_RATE2_WEIGHTING_8814B 8\n#define BIT_MASK_RATE2_WEIGHTING_8814B 0xf\n#define BIT_RATE2_WEIGHTING_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RATE2_WEIGHTING_8814B)                                \\\n\t << BIT_SHIFT_RATE2_WEIGHTING_8814B)\n#define BITS_RATE2_WEIGHTING_8814B                                             \\\n\t(BIT_MASK_RATE2_WEIGHTING_8814B << BIT_SHIFT_RATE2_WEIGHTING_8814B)\n#define BIT_CLEAR_RATE2_WEIGHTING_8814B(x) ((x) & (~BITS_RATE2_WEIGHTING_8814B))\n#define BIT_GET_RATE2_WEIGHTING_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RATE2_WEIGHTING_8814B) &                            \\\n\t BIT_MASK_RATE2_WEIGHTING_8814B)\n#define BIT_SET_RATE2_WEIGHTING_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RATE2_WEIGHTING_8814B(x) | BIT_RATE2_WEIGHTING_8814B(v))\n\n#define BIT_SHIFT_RATE1_WEIGHTING_8814B 4\n#define BIT_MASK_RATE1_WEIGHTING_8814B 0xf\n#define BIT_RATE1_WEIGHTING_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RATE1_WEIGHTING_8814B)                                \\\n\t << BIT_SHIFT_RATE1_WEIGHTING_8814B)\n#define BITS_RATE1_WEIGHTING_8814B                                             \\\n\t(BIT_MASK_RATE1_WEIGHTING_8814B << BIT_SHIFT_RATE1_WEIGHTING_8814B)\n#define BIT_CLEAR_RATE1_WEIGHTING_8814B(x) ((x) & (~BITS_RATE1_WEIGHTING_8814B))\n#define BIT_GET_RATE1_WEIGHTING_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RATE1_WEIGHTING_8814B) &                            \\\n\t BIT_MASK_RATE1_WEIGHTING_8814B)\n#define BIT_SET_RATE1_WEIGHTING_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RATE1_WEIGHTING_8814B(x) | BIT_RATE1_WEIGHTING_8814B(v))\n\n#define BIT_SHIFT_RATE0_WEIGHTING_8814B 0\n#define BIT_MASK_RATE0_WEIGHTING_8814B 0xf\n#define BIT_RATE0_WEIGHTING_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RATE0_WEIGHTING_8814B)                                \\\n\t << BIT_SHIFT_RATE0_WEIGHTING_8814B)\n#define BITS_RATE0_WEIGHTING_8814B                                             \\\n\t(BIT_MASK_RATE0_WEIGHTING_8814B << BIT_SHIFT_RATE0_WEIGHTING_8814B)\n#define BIT_CLEAR_RATE0_WEIGHTING_8814B(x) ((x) & (~BITS_RATE0_WEIGHTING_8814B))\n#define BIT_GET_RATE0_WEIGHTING_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RATE0_WEIGHTING_8814B) &                            \\\n\t BIT_MASK_RATE0_WEIGHTING_8814B)\n#define BIT_SET_RATE0_WEIGHTING_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RATE0_WEIGHTING_8814B(x) | BIT_RATE0_WEIGHTING_8814B(v))\n\n/* 2 REG_REG_ARFR_WT1_8814B */\n\n#define BIT_SHIFT_RATE15_WEIGHTING_8814B 28\n#define BIT_MASK_RATE15_WEIGHTING_8814B 0xf\n#define BIT_RATE15_WEIGHTING_8814B(x)                                          \\\n\t(((x) & BIT_MASK_RATE15_WEIGHTING_8814B)                               \\\n\t << BIT_SHIFT_RATE15_WEIGHTING_8814B)\n#define BITS_RATE15_WEIGHTING_8814B                                            \\\n\t(BIT_MASK_RATE15_WEIGHTING_8814B << BIT_SHIFT_RATE15_WEIGHTING_8814B)\n#define BIT_CLEAR_RATE15_WEIGHTING_8814B(x)                                    \\\n\t((x) & (~BITS_RATE15_WEIGHTING_8814B))\n#define BIT_GET_RATE15_WEIGHTING_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_RATE15_WEIGHTING_8814B) &                           \\\n\t BIT_MASK_RATE15_WEIGHTING_8814B)\n#define BIT_SET_RATE15_WEIGHTING_8814B(x, v)                                   \\\n\t(BIT_CLEAR_RATE15_WEIGHTING_8814B(x) | BIT_RATE15_WEIGHTING_8814B(v))\n\n#define BIT_SHIFT_RATE14_WEIGHTING_8814B 24\n#define BIT_MASK_RATE14_WEIGHTING_8814B 0xf\n#define BIT_RATE14_WEIGHTING_8814B(x)                                          \\\n\t(((x) & BIT_MASK_RATE14_WEIGHTING_8814B)                               \\\n\t << BIT_SHIFT_RATE14_WEIGHTING_8814B)\n#define BITS_RATE14_WEIGHTING_8814B                                            \\\n\t(BIT_MASK_RATE14_WEIGHTING_8814B << BIT_SHIFT_RATE14_WEIGHTING_8814B)\n#define BIT_CLEAR_RATE14_WEIGHTING_8814B(x)                                    \\\n\t((x) & (~BITS_RATE14_WEIGHTING_8814B))\n#define BIT_GET_RATE14_WEIGHTING_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_RATE14_WEIGHTING_8814B) &                           \\\n\t BIT_MASK_RATE14_WEIGHTING_8814B)\n#define BIT_SET_RATE14_WEIGHTING_8814B(x, v)                                   \\\n\t(BIT_CLEAR_RATE14_WEIGHTING_8814B(x) | BIT_RATE14_WEIGHTING_8814B(v))\n\n#define BIT_SHIFT_RATE13_WEIGHTING_8814B 20\n#define BIT_MASK_RATE13_WEIGHTING_8814B 0xf\n#define BIT_RATE13_WEIGHTING_8814B(x)                                          \\\n\t(((x) & BIT_MASK_RATE13_WEIGHTING_8814B)                               \\\n\t << BIT_SHIFT_RATE13_WEIGHTING_8814B)\n#define BITS_RATE13_WEIGHTING_8814B                                            \\\n\t(BIT_MASK_RATE13_WEIGHTING_8814B << BIT_SHIFT_RATE13_WEIGHTING_8814B)\n#define BIT_CLEAR_RATE13_WEIGHTING_8814B(x)                                    \\\n\t((x) & (~BITS_RATE13_WEIGHTING_8814B))\n#define BIT_GET_RATE13_WEIGHTING_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_RATE13_WEIGHTING_8814B) &                           \\\n\t BIT_MASK_RATE13_WEIGHTING_8814B)\n#define BIT_SET_RATE13_WEIGHTING_8814B(x, v)                                   \\\n\t(BIT_CLEAR_RATE13_WEIGHTING_8814B(x) | BIT_RATE13_WEIGHTING_8814B(v))\n\n#define BIT_SHIFT_RATE12_WEIGHTING_8814B 16\n#define BIT_MASK_RATE12_WEIGHTING_8814B 0xf\n#define BIT_RATE12_WEIGHTING_8814B(x)                                          \\\n\t(((x) & BIT_MASK_RATE12_WEIGHTING_8814B)                               \\\n\t << BIT_SHIFT_RATE12_WEIGHTING_8814B)\n#define BITS_RATE12_WEIGHTING_8814B                                            \\\n\t(BIT_MASK_RATE12_WEIGHTING_8814B << BIT_SHIFT_RATE12_WEIGHTING_8814B)\n#define BIT_CLEAR_RATE12_WEIGHTING_8814B(x)                                    \\\n\t((x) & (~BITS_RATE12_WEIGHTING_8814B))\n#define BIT_GET_RATE12_WEIGHTING_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_RATE12_WEIGHTING_8814B) &                           \\\n\t BIT_MASK_RATE12_WEIGHTING_8814B)\n#define BIT_SET_RATE12_WEIGHTING_8814B(x, v)                                   \\\n\t(BIT_CLEAR_RATE12_WEIGHTING_8814B(x) | BIT_RATE12_WEIGHTING_8814B(v))\n\n#define BIT_SHIFT_RATE11_WEIGHTING_8814B 12\n#define BIT_MASK_RATE11_WEIGHTING_8814B 0xf\n#define BIT_RATE11_WEIGHTING_8814B(x)                                          \\\n\t(((x) & BIT_MASK_RATE11_WEIGHTING_8814B)                               \\\n\t << BIT_SHIFT_RATE11_WEIGHTING_8814B)\n#define BITS_RATE11_WEIGHTING_8814B                                            \\\n\t(BIT_MASK_RATE11_WEIGHTING_8814B << BIT_SHIFT_RATE11_WEIGHTING_8814B)\n#define BIT_CLEAR_RATE11_WEIGHTING_8814B(x)                                    \\\n\t((x) & (~BITS_RATE11_WEIGHTING_8814B))\n#define BIT_GET_RATE11_WEIGHTING_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_RATE11_WEIGHTING_8814B) &                           \\\n\t BIT_MASK_RATE11_WEIGHTING_8814B)\n#define BIT_SET_RATE11_WEIGHTING_8814B(x, v)                                   \\\n\t(BIT_CLEAR_RATE11_WEIGHTING_8814B(x) | BIT_RATE11_WEIGHTING_8814B(v))\n\n#define BIT_SHIFT_RATE10_WEIGHTING_8814B 8\n#define BIT_MASK_RATE10_WEIGHTING_8814B 0xf\n#define BIT_RATE10_WEIGHTING_8814B(x)                                          \\\n\t(((x) & BIT_MASK_RATE10_WEIGHTING_8814B)                               \\\n\t << BIT_SHIFT_RATE10_WEIGHTING_8814B)\n#define BITS_RATE10_WEIGHTING_8814B                                            \\\n\t(BIT_MASK_RATE10_WEIGHTING_8814B << BIT_SHIFT_RATE10_WEIGHTING_8814B)\n#define BIT_CLEAR_RATE10_WEIGHTING_8814B(x)                                    \\\n\t((x) & (~BITS_RATE10_WEIGHTING_8814B))\n#define BIT_GET_RATE10_WEIGHTING_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_RATE10_WEIGHTING_8814B) &                           \\\n\t BIT_MASK_RATE10_WEIGHTING_8814B)\n#define BIT_SET_RATE10_WEIGHTING_8814B(x, v)                                   \\\n\t(BIT_CLEAR_RATE10_WEIGHTING_8814B(x) | BIT_RATE10_WEIGHTING_8814B(v))\n\n#define BIT_SHIFT_RATE9_WEIGHTING_8814B 4\n#define BIT_MASK_RATE9_WEIGHTING_8814B 0xf\n#define BIT_RATE9_WEIGHTING_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RATE9_WEIGHTING_8814B)                                \\\n\t << BIT_SHIFT_RATE9_WEIGHTING_8814B)\n#define BITS_RATE9_WEIGHTING_8814B                                             \\\n\t(BIT_MASK_RATE9_WEIGHTING_8814B << BIT_SHIFT_RATE9_WEIGHTING_8814B)\n#define BIT_CLEAR_RATE9_WEIGHTING_8814B(x) ((x) & (~BITS_RATE9_WEIGHTING_8814B))\n#define BIT_GET_RATE9_WEIGHTING_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RATE9_WEIGHTING_8814B) &                            \\\n\t BIT_MASK_RATE9_WEIGHTING_8814B)\n#define BIT_SET_RATE9_WEIGHTING_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RATE9_WEIGHTING_8814B(x) | BIT_RATE9_WEIGHTING_8814B(v))\n\n#define BIT_SHIFT_RATE8_WEIGHTING_8814B 0\n#define BIT_MASK_RATE8_WEIGHTING_8814B 0xf\n#define BIT_RATE8_WEIGHTING_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RATE8_WEIGHTING_8814B)                                \\\n\t << BIT_SHIFT_RATE8_WEIGHTING_8814B)\n#define BITS_RATE8_WEIGHTING_8814B                                             \\\n\t(BIT_MASK_RATE8_WEIGHTING_8814B << BIT_SHIFT_RATE8_WEIGHTING_8814B)\n#define BIT_CLEAR_RATE8_WEIGHTING_8814B(x) ((x) & (~BITS_RATE8_WEIGHTING_8814B))\n#define BIT_GET_RATE8_WEIGHTING_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RATE8_WEIGHTING_8814B) &                            \\\n\t BIT_MASK_RATE8_WEIGHTING_8814B)\n#define BIT_SET_RATE8_WEIGHTING_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RATE8_WEIGHTING_8814B(x) | BIT_RATE8_WEIGHTING_8814B(v))\n\n/* 2 REG_CCK_CHECK_8814B */\n#define BIT_CHECK_CCK_EN_8814B BIT(7)\n#define BIT_EN_BCN_PKT_REL_P0_8814B BIT(6)\n#define BIT_BCN_PORT_SEL_8814B BIT(5)\n#define BIT_MOREDATA_BYPASS_8814B BIT(4)\n#define BIT_EN_CLR_CMD_REL_BCN_PKT_P0_8814B BIT(3)\n#define BIT_EN_SET_MOREDATA_8814B BIT(2)\n#define BIT__R_DIS_CLEAR_MACID_RELEASE_8814B BIT(1)\n#define BIT__R_MACID_RELEASE_EN_8814B BIT(0)\n\n/* 2 REG_AMPDU_MAX_TIME_V1_8814B */\n\n#define BIT_SHIFT_AMPDU_MAX_TIME_8814B 0\n#define BIT_MASK_AMPDU_MAX_TIME_8814B 0xff\n#define BIT_AMPDU_MAX_TIME_8814B(x)                                            \\\n\t(((x) & BIT_MASK_AMPDU_MAX_TIME_8814B)                                 \\\n\t << BIT_SHIFT_AMPDU_MAX_TIME_8814B)\n#define BITS_AMPDU_MAX_TIME_8814B                                              \\\n\t(BIT_MASK_AMPDU_MAX_TIME_8814B << BIT_SHIFT_AMPDU_MAX_TIME_8814B)\n#define BIT_CLEAR_AMPDU_MAX_TIME_8814B(x) ((x) & (~BITS_AMPDU_MAX_TIME_8814B))\n#define BIT_GET_AMPDU_MAX_TIME_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8814B) &                             \\\n\t BIT_MASK_AMPDU_MAX_TIME_8814B)\n#define BIT_SET_AMPDU_MAX_TIME_8814B(x, v)                                     \\\n\t(BIT_CLEAR_AMPDU_MAX_TIME_8814B(x) | BIT_AMPDU_MAX_TIME_8814B(v))\n\n/* 2 REG_TAB_SEL_8814B */\n\n#define BIT_SHIFT_RATE_SEL_8814B 0\n#define BIT_MASK_RATE_SEL_8814B 0xf\n#define BIT_RATE_SEL_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_RATE_SEL_8814B) << BIT_SHIFT_RATE_SEL_8814B)\n#define BITS_RATE_SEL_8814B                                                    \\\n\t(BIT_MASK_RATE_SEL_8814B << BIT_SHIFT_RATE_SEL_8814B)\n#define BIT_CLEAR_RATE_SEL_8814B(x) ((x) & (~BITS_RATE_SEL_8814B))\n#define BIT_GET_RATE_SEL_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RATE_SEL_8814B) & BIT_MASK_RATE_SEL_8814B)\n#define BIT_SET_RATE_SEL_8814B(x, v)                                           \\\n\t(BIT_CLEAR_RATE_SEL_8814B(x) | BIT_RATE_SEL_8814B(v))\n\n/* 2 REG_BCN_INVALID_CTRL_8814B */\n#define BIT_EN_CLR_CMD_REL_BCN_PKT_P4_8814B BIT(7)\n#define BIT_EN_BCN_PKT_REL_P4_8814B BIT(6)\n#define BIT_EN_CLR_CMD_REL_BCN_PKT_P3_8814B BIT(5)\n#define BIT_EN_BCN_PKT_REL_P3_8814B BIT(4)\n#define BIT_EN_CLR_CMD_REL_BCN_PKT_P2_8814B BIT(3)\n#define BIT_EN_BCN_PKT_REL_P2_8814B BIT(2)\n#define BIT_EN_CLR_CMD_REL_BCN_PKT_P1_8814B BIT(1)\n#define BIT_EN_BCN_PKT_REL_P1_8814B BIT(0)\n\n/* 2 REG_AMPDU_MAX_LENGTH_HT_8814B */\n\n#define BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B 0\n#define BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B 0xffff\n#define BIT_AMPDU_MAX_LENGTH_HT_8814B(x)                                       \\\n\t(((x) & BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B)                            \\\n\t << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B)\n#define BITS_AMPDU_MAX_LENGTH_HT_8814B                                         \\\n\t(BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B                                    \\\n\t << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B)\n#define BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8814B(x)                                 \\\n\t((x) & (~BITS_AMPDU_MAX_LENGTH_HT_8814B))\n#define BIT_GET_AMPDU_MAX_LENGTH_HT_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B) &                        \\\n\t BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B)\n#define BIT_SET_AMPDU_MAX_LENGTH_HT_8814B(x, v)                                \\\n\t(BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8814B(x) |                              \\\n\t BIT_AMPDU_MAX_LENGTH_HT_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NDPA_RATE_8814B */\n\n#define BIT_SHIFT_R_NDPA_RATE_V1_8814B 0\n#define BIT_MASK_R_NDPA_RATE_V1_8814B 0xff\n#define BIT_R_NDPA_RATE_V1_8814B(x)                                            \\\n\t(((x) & BIT_MASK_R_NDPA_RATE_V1_8814B)                                 \\\n\t << BIT_SHIFT_R_NDPA_RATE_V1_8814B)\n#define BITS_R_NDPA_RATE_V1_8814B                                              \\\n\t(BIT_MASK_R_NDPA_RATE_V1_8814B << BIT_SHIFT_R_NDPA_RATE_V1_8814B)\n#define BIT_CLEAR_R_NDPA_RATE_V1_8814B(x) ((x) & (~BITS_R_NDPA_RATE_V1_8814B))\n#define BIT_GET_R_NDPA_RATE_V1_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8814B) &                             \\\n\t BIT_MASK_R_NDPA_RATE_V1_8814B)\n#define BIT_SET_R_NDPA_RATE_V1_8814B(x, v)                                     \\\n\t(BIT_CLEAR_R_NDPA_RATE_V1_8814B(x) | BIT_R_NDPA_RATE_V1_8814B(v))\n\n/* 2 REG_TX_HANG_CTRL_8814B */\n#define BIT_EN_GNT_BT_AWAKE_8814B BIT(3)\n#define BIT_EN_EOF_V1_8814B BIT(2)\n#define BIT_DIS_OQT_BLOCK_8814B BIT(1)\n#define BIT_SEARCH_QUEUE_EN_8814B BIT(0)\n\n/* 2 REG_NDPA_OPT_CTRL_8814B */\n#define BIT_DIS_MACID_RELEASE_RTY_8814B BIT(5)\n\n#define BIT_SHIFT_BW_SIGTA_8814B 3\n#define BIT_MASK_BW_SIGTA_8814B 0x3\n#define BIT_BW_SIGTA_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_BW_SIGTA_8814B) << BIT_SHIFT_BW_SIGTA_8814B)\n#define BITS_BW_SIGTA_8814B                                                    \\\n\t(BIT_MASK_BW_SIGTA_8814B << BIT_SHIFT_BW_SIGTA_8814B)\n#define BIT_CLEAR_BW_SIGTA_8814B(x) ((x) & (~BITS_BW_SIGTA_8814B))\n#define BIT_GET_BW_SIGTA_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_BW_SIGTA_8814B) & BIT_MASK_BW_SIGTA_8814B)\n#define BIT_SET_BW_SIGTA_8814B(x, v)                                           \\\n\t(BIT_CLEAR_BW_SIGTA_8814B(x) | BIT_BW_SIGTA_8814B(v))\n\n#define BIT_EN_BAR_SIGTA_8814B BIT(2)\n\n#define BIT_SHIFT_NDPA_BW_8814B 0\n#define BIT_MASK_NDPA_BW_8814B 0x3\n#define BIT_NDPA_BW_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_NDPA_BW_8814B) << BIT_SHIFT_NDPA_BW_8814B)\n#define BITS_NDPA_BW_8814B (BIT_MASK_NDPA_BW_8814B << BIT_SHIFT_NDPA_BW_8814B)\n#define BIT_CLEAR_NDPA_BW_8814B(x) ((x) & (~BITS_NDPA_BW_8814B))\n#define BIT_GET_NDPA_BW_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_NDPA_BW_8814B) & BIT_MASK_NDPA_BW_8814B)\n#define BIT_SET_NDPA_BW_8814B(x, v)                                            \\\n\t(BIT_CLEAR_NDPA_BW_8814B(x) | BIT_NDPA_BW_8814B(v))\n\n/* 2 REG_AMPDU_MAX_LENGTH_VHT_8814B */\n\n#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B 0\n#define BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B 0x3ffff\n#define BIT_AMPDU_MAX_LENGTH_VHT_8814B(x)                                      \\\n\t(((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B)                           \\\n\t << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B)\n#define BITS_AMPDU_MAX_LENGTH_VHT_8814B                                        \\\n\t(BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B                                   \\\n\t << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B)\n#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_8814B(x)                                \\\n\t((x) & (~BITS_AMPDU_MAX_LENGTH_VHT_8814B))\n#define BIT_GET_AMPDU_MAX_LENGTH_VHT_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B) &                       \\\n\t BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B)\n#define BIT_SET_AMPDU_MAX_LENGTH_VHT_8814B(x, v)                               \\\n\t(BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_8814B(x) |                             \\\n\t BIT_AMPDU_MAX_LENGTH_VHT_8814B(v))\n\n/* 2 REG_RD_RESP_PKT_TH_8814B */\n\n#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B 0\n#define BIT_MASK_RD_RESP_PKT_TH_V1_8814B 0x3f\n#define BIT_RD_RESP_PKT_TH_V1_8814B(x)                                         \\\n\t(((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8814B)                              \\\n\t << BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B)\n#define BITS_RD_RESP_PKT_TH_V1_8814B                                           \\\n\t(BIT_MASK_RD_RESP_PKT_TH_V1_8814B << BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B)\n#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8814B(x)                                   \\\n\t((x) & (~BITS_RD_RESP_PKT_TH_V1_8814B))\n#define BIT_GET_RD_RESP_PKT_TH_V1_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B) &                          \\\n\t BIT_MASK_RD_RESP_PKT_TH_V1_8814B)\n#define BIT_SET_RD_RESP_PKT_TH_V1_8814B(x, v)                                  \\\n\t(BIT_CLEAR_RD_RESP_PKT_TH_V1_8814B(x) | BIT_RD_RESP_PKT_TH_V1_8814B(v))\n\n/* 2 REG_NEW_EDCA_CTRL_V1_8814B */\n\n#define BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B 9\n#define BIT_MASK_RANDOM_VALUE_SHIFT_8814B 0x7\n#define BIT_RANDOM_VALUE_SHIFT_8814B(x)                                        \\\n\t(((x) & BIT_MASK_RANDOM_VALUE_SHIFT_8814B)                             \\\n\t << BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B)\n#define BITS_RANDOM_VALUE_SHIFT_8814B                                          \\\n\t(BIT_MASK_RANDOM_VALUE_SHIFT_8814B                                     \\\n\t << BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B)\n#define BIT_CLEAR_RANDOM_VALUE_SHIFT_8814B(x)                                  \\\n\t((x) & (~BITS_RANDOM_VALUE_SHIFT_8814B))\n#define BIT_GET_RANDOM_VALUE_SHIFT_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B) &                         \\\n\t BIT_MASK_RANDOM_VALUE_SHIFT_8814B)\n#define BIT_SET_RANDOM_VALUE_SHIFT_8814B(x, v)                                 \\\n\t(BIT_CLEAR_RANDOM_VALUE_SHIFT_8814B(x) |                               \\\n\t BIT_RANDOM_VALUE_SHIFT_8814B(v))\n\n#define BIT_ENABLE_NEW_EDCA_8814B BIT(8)\n\n#define BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B 0\n#define BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B 0xff\n#define BIT_MEDIUM_HAS_IDKE_TRIGGER_8814B(x)                                   \\\n\t(((x) & BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B)                        \\\n\t << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B)\n#define BITS_MEDIUM_HAS_IDKE_TRIGGER_8814B                                     \\\n\t(BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B                                \\\n\t << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B)\n#define BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER_8814B(x)                             \\\n\t((x) & (~BITS_MEDIUM_HAS_IDKE_TRIGGER_8814B))\n#define BIT_GET_MEDIUM_HAS_IDKE_TRIGGER_8814B(x)                               \\\n\t(((x) >> BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B) &                    \\\n\t BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B)\n#define BIT_SET_MEDIUM_HAS_IDKE_TRIGGER_8814B(x, v)                            \\\n\t(BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER_8814B(x) |                          \\\n\t BIT_MEDIUM_HAS_IDKE_TRIGGER_8814B(v))\n\n/* 2 REG_ACQ_STOP_V2_8814B */\n#define BIT_AC19Q_STOP_8814B BIT(19)\n#define BIT_AC18Q_STOP_8814B BIT(18)\n#define BIT_AC17Q_STOP_8814B BIT(17)\n#define BIT_AC16Q_STOP_8814B BIT(16)\n#define BIT_AC15Q_STOP_8814B BIT(15)\n#define BIT_AC14Q_STOP_8814B BIT(14)\n#define BIT_AC13Q_STOP_8814B BIT(13)\n#define BIT_AC12Q_STOP_8814B BIT(12)\n#define BIT_AC11Q_STOP_8814B BIT(11)\n#define BIT_AC10Q_STOP_8814B BIT(10)\n#define BIT_AC9Q_STOP_8814B BIT(9)\n#define BIT_AC8Q_STOP_8814B BIT(8)\n#define BIT_AC7Q_STOP_8814B BIT(7)\n#define BIT_AC6Q_STOP_8814B BIT(6)\n#define BIT_AC5Q_STOP_8814B BIT(5)\n#define BIT_AC4Q_STOP_8814B BIT(4)\n#define BIT_AC3Q_STOP_8814B BIT(3)\n#define BIT_AC2Q_STOP_8814B BIT(2)\n#define BIT_AC1Q_STOP_8814B BIT(1)\n#define BIT_AC0Q_STOP_8814B BIT(0)\n\n/* 2 REG_WMAC_LBK_BUF_HD_V1_8814B */\n\n#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B 0\n#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B 0xfff\n#define BIT_WMAC_LBK_BUF_HEAD_V1_8814B(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B)                           \\\n\t << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B)\n#define BITS_WMAC_LBK_BUF_HEAD_V1_8814B                                        \\\n\t(BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B                                   \\\n\t << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B)\n#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8814B(x)                                \\\n\t((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8814B))\n#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B) &                       \\\n\t BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B)\n#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8814B(x, v)                               \\\n\t(BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8814B(x) |                             \\\n\t BIT_WMAC_LBK_BUF_HEAD_V1_8814B(v))\n\n/* 2 REG_MGQ_BDNY_V1_8814B */\n\n#define BIT_SHIFT_MGQ_PGBNDY_V1_8814B 0\n#define BIT_MASK_MGQ_PGBNDY_V1_8814B 0xfff\n#define BIT_MGQ_PGBNDY_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_PGBNDY_V1_8814B) << BIT_SHIFT_MGQ_PGBNDY_V1_8814B)\n#define BITS_MGQ_PGBNDY_V1_8814B                                               \\\n\t(BIT_MASK_MGQ_PGBNDY_V1_8814B << BIT_SHIFT_MGQ_PGBNDY_V1_8814B)\n#define BIT_CLEAR_MGQ_PGBNDY_V1_8814B(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8814B))\n#define BIT_GET_MGQ_PGBNDY_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8814B) & BIT_MASK_MGQ_PGBNDY_V1_8814B)\n#define BIT_SET_MGQ_PGBNDY_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_PGBNDY_V1_8814B(x) | BIT_MGQ_PGBNDY_V1_8814B(v))\n\n/* 2 REG_TXRPT_CTRL_8814B */\n\n#define BIT_SHIFT_TRXRPT_TIMER_TH_8814B 24\n#define BIT_MASK_TRXRPT_TIMER_TH_8814B 0xff\n#define BIT_TRXRPT_TIMER_TH_8814B(x)                                           \\\n\t(((x) & BIT_MASK_TRXRPT_TIMER_TH_8814B)                                \\\n\t << BIT_SHIFT_TRXRPT_TIMER_TH_8814B)\n#define BITS_TRXRPT_TIMER_TH_8814B                                             \\\n\t(BIT_MASK_TRXRPT_TIMER_TH_8814B << BIT_SHIFT_TRXRPT_TIMER_TH_8814B)\n#define BIT_CLEAR_TRXRPT_TIMER_TH_8814B(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8814B))\n#define BIT_GET_TRXRPT_TIMER_TH_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8814B) &                            \\\n\t BIT_MASK_TRXRPT_TIMER_TH_8814B)\n#define BIT_SET_TRXRPT_TIMER_TH_8814B(x, v)                                    \\\n\t(BIT_CLEAR_TRXRPT_TIMER_TH_8814B(x) | BIT_TRXRPT_TIMER_TH_8814B(v))\n\n#define BIT_SHIFT_TRXRPT_LEN_TH_8814B 16\n#define BIT_MASK_TRXRPT_LEN_TH_8814B 0xff\n#define BIT_TRXRPT_LEN_TH_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TRXRPT_LEN_TH_8814B) << BIT_SHIFT_TRXRPT_LEN_TH_8814B)\n#define BITS_TRXRPT_LEN_TH_8814B                                               \\\n\t(BIT_MASK_TRXRPT_LEN_TH_8814B << BIT_SHIFT_TRXRPT_LEN_TH_8814B)\n#define BIT_CLEAR_TRXRPT_LEN_TH_8814B(x) ((x) & (~BITS_TRXRPT_LEN_TH_8814B))\n#define BIT_GET_TRXRPT_LEN_TH_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8814B) & BIT_MASK_TRXRPT_LEN_TH_8814B)\n#define BIT_SET_TRXRPT_LEN_TH_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TRXRPT_LEN_TH_8814B(x) | BIT_TRXRPT_LEN_TH_8814B(v))\n\n#define BIT_SHIFT_TRXRPT_READ_PTR_8814B 8\n#define BIT_MASK_TRXRPT_READ_PTR_8814B 0xff\n#define BIT_TRXRPT_READ_PTR_8814B(x)                                           \\\n\t(((x) & BIT_MASK_TRXRPT_READ_PTR_8814B)                                \\\n\t << BIT_SHIFT_TRXRPT_READ_PTR_8814B)\n#define BITS_TRXRPT_READ_PTR_8814B                                             \\\n\t(BIT_MASK_TRXRPT_READ_PTR_8814B << BIT_SHIFT_TRXRPT_READ_PTR_8814B)\n#define BIT_CLEAR_TRXRPT_READ_PTR_8814B(x) ((x) & (~BITS_TRXRPT_READ_PTR_8814B))\n#define BIT_GET_TRXRPT_READ_PTR_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8814B) &                            \\\n\t BIT_MASK_TRXRPT_READ_PTR_8814B)\n#define BIT_SET_TRXRPT_READ_PTR_8814B(x, v)                                    \\\n\t(BIT_CLEAR_TRXRPT_READ_PTR_8814B(x) | BIT_TRXRPT_READ_PTR_8814B(v))\n\n#define BIT_SHIFT_TRXRPT_WRITE_PTR_8814B 0\n#define BIT_MASK_TRXRPT_WRITE_PTR_8814B 0xff\n#define BIT_TRXRPT_WRITE_PTR_8814B(x)                                          \\\n\t(((x) & BIT_MASK_TRXRPT_WRITE_PTR_8814B)                               \\\n\t << BIT_SHIFT_TRXRPT_WRITE_PTR_8814B)\n#define BITS_TRXRPT_WRITE_PTR_8814B                                            \\\n\t(BIT_MASK_TRXRPT_WRITE_PTR_8814B << BIT_SHIFT_TRXRPT_WRITE_PTR_8814B)\n#define BIT_CLEAR_TRXRPT_WRITE_PTR_8814B(x)                                    \\\n\t((x) & (~BITS_TRXRPT_WRITE_PTR_8814B))\n#define BIT_GET_TRXRPT_WRITE_PTR_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8814B) &                           \\\n\t BIT_MASK_TRXRPT_WRITE_PTR_8814B)\n#define BIT_SET_TRXRPT_WRITE_PTR_8814B(x, v)                                   \\\n\t(BIT_CLEAR_TRXRPT_WRITE_PTR_8814B(x) | BIT_TRXRPT_WRITE_PTR_8814B(v))\n\n/* 2 REG_INIRTS_RATE_SEL_8814B */\n#define BIT_LEAG_RTS_BW_DUP_8814B BIT(5)\n\n/* 2 REG_BASIC_CFEND_RATE_8814B */\n\n#define BIT_SHIFT_BASIC_CFEND_RATE_8814B 0\n#define BIT_MASK_BASIC_CFEND_RATE_8814B 0x1f\n#define BIT_BASIC_CFEND_RATE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_BASIC_CFEND_RATE_8814B)                               \\\n\t << BIT_SHIFT_BASIC_CFEND_RATE_8814B)\n#define BITS_BASIC_CFEND_RATE_8814B                                            \\\n\t(BIT_MASK_BASIC_CFEND_RATE_8814B << BIT_SHIFT_BASIC_CFEND_RATE_8814B)\n#define BIT_CLEAR_BASIC_CFEND_RATE_8814B(x)                                    \\\n\t((x) & (~BITS_BASIC_CFEND_RATE_8814B))\n#define BIT_GET_BASIC_CFEND_RATE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8814B) &                           \\\n\t BIT_MASK_BASIC_CFEND_RATE_8814B)\n#define BIT_SET_BASIC_CFEND_RATE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_BASIC_CFEND_RATE_8814B(x) | BIT_BASIC_CFEND_RATE_8814B(v))\n\n/* 2 REG_STBC_CFEND_RATE_8814B */\n\n#define BIT_SHIFT_STBC_CFEND_RATE_8814B 0\n#define BIT_MASK_STBC_CFEND_RATE_8814B 0x1f\n#define BIT_STBC_CFEND_RATE_8814B(x)                                           \\\n\t(((x) & BIT_MASK_STBC_CFEND_RATE_8814B)                                \\\n\t << BIT_SHIFT_STBC_CFEND_RATE_8814B)\n#define BITS_STBC_CFEND_RATE_8814B                                             \\\n\t(BIT_MASK_STBC_CFEND_RATE_8814B << BIT_SHIFT_STBC_CFEND_RATE_8814B)\n#define BIT_CLEAR_STBC_CFEND_RATE_8814B(x) ((x) & (~BITS_STBC_CFEND_RATE_8814B))\n#define BIT_GET_STBC_CFEND_RATE_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_STBC_CFEND_RATE_8814B) &                            \\\n\t BIT_MASK_STBC_CFEND_RATE_8814B)\n#define BIT_SET_STBC_CFEND_RATE_8814B(x, v)                                    \\\n\t(BIT_CLEAR_STBC_CFEND_RATE_8814B(x) | BIT_STBC_CFEND_RATE_8814B(v))\n\n/* 2 REG_DATA_SC_8814B */\n\n#define BIT_SHIFT_TXSC_40M_8814B 4\n#define BIT_MASK_TXSC_40M_8814B 0xf\n#define BIT_TXSC_40M_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_TXSC_40M_8814B) << BIT_SHIFT_TXSC_40M_8814B)\n#define BITS_TXSC_40M_8814B                                                    \\\n\t(BIT_MASK_TXSC_40M_8814B << BIT_SHIFT_TXSC_40M_8814B)\n#define BIT_CLEAR_TXSC_40M_8814B(x) ((x) & (~BITS_TXSC_40M_8814B))\n#define BIT_GET_TXSC_40M_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXSC_40M_8814B) & BIT_MASK_TXSC_40M_8814B)\n#define BIT_SET_TXSC_40M_8814B(x, v)                                           \\\n\t(BIT_CLEAR_TXSC_40M_8814B(x) | BIT_TXSC_40M_8814B(v))\n\n#define BIT_SHIFT_TXSC_20M_8814B 0\n#define BIT_MASK_TXSC_20M_8814B 0xf\n#define BIT_TXSC_20M_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_TXSC_20M_8814B) << BIT_SHIFT_TXSC_20M_8814B)\n#define BITS_TXSC_20M_8814B                                                    \\\n\t(BIT_MASK_TXSC_20M_8814B << BIT_SHIFT_TXSC_20M_8814B)\n#define BIT_CLEAR_TXSC_20M_8814B(x) ((x) & (~BITS_TXSC_20M_8814B))\n#define BIT_GET_TXSC_20M_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXSC_20M_8814B) & BIT_MASK_TXSC_20M_8814B)\n#define BIT_SET_TXSC_20M_8814B(x, v)                                           \\\n\t(BIT_CLEAR_TXSC_20M_8814B(x) | BIT_TXSC_20M_8814B(v))\n\n/* 2 REG_MOREDATA_V1_8814B */\n#define BIT_MOREDATA_CTRL2_EN_V1_8814B BIT(3)\n#define BIT_MOREDATA_CTRL1_EN_V1_8814B BIT(2)\n#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_DATA_SC1_8814B */\n\n#define BIT_SHIFT_TXSC_160M_8814B 4\n#define BIT_MASK_TXSC_160M_8814B 0xf\n#define BIT_TXSC_160M_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_TXSC_160M_8814B) << BIT_SHIFT_TXSC_160M_8814B)\n#define BITS_TXSC_160M_8814B                                                   \\\n\t(BIT_MASK_TXSC_160M_8814B << BIT_SHIFT_TXSC_160M_8814B)\n#define BIT_CLEAR_TXSC_160M_8814B(x) ((x) & (~BITS_TXSC_160M_8814B))\n#define BIT_GET_TXSC_160M_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXSC_160M_8814B) & BIT_MASK_TXSC_160M_8814B)\n#define BIT_SET_TXSC_160M_8814B(x, v)                                          \\\n\t(BIT_CLEAR_TXSC_160M_8814B(x) | BIT_TXSC_160M_8814B(v))\n\n#define BIT_SHIFT_TXSC_80M_8814B 0\n#define BIT_MASK_TXSC_80M_8814B 0xf\n#define BIT_TXSC_80M_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_TXSC_80M_8814B) << BIT_SHIFT_TXSC_80M_8814B)\n#define BITS_TXSC_80M_8814B                                                    \\\n\t(BIT_MASK_TXSC_80M_8814B << BIT_SHIFT_TXSC_80M_8814B)\n#define BIT_CLEAR_TXSC_80M_8814B(x) ((x) & (~BITS_TXSC_80M_8814B))\n#define BIT_GET_TXSC_80M_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXSC_80M_8814B) & BIT_MASK_TXSC_80M_8814B)\n#define BIT_SET_TXSC_80M_8814B(x, v)                                           \\\n\t(BIT_CLEAR_TXSC_80M_8814B(x) | BIT_TXSC_80M_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_TXRPT_START_OFFSET_8814B */\n#define BIT_RPTFIFO_RPTNUM_OPT_8814B BIT(31)\n\n#define BIT_SHIFT_MISSED_RPT_NUM_8814B 28\n#define BIT_MASK_MISSED_RPT_NUM_8814B 0x7\n#define BIT_MISSED_RPT_NUM_8814B(x)                                            \\\n\t(((x) & BIT_MASK_MISSED_RPT_NUM_8814B)                                 \\\n\t << BIT_SHIFT_MISSED_RPT_NUM_8814B)\n#define BITS_MISSED_RPT_NUM_8814B                                              \\\n\t(BIT_MASK_MISSED_RPT_NUM_8814B << BIT_SHIFT_MISSED_RPT_NUM_8814B)\n#define BIT_CLEAR_MISSED_RPT_NUM_8814B(x) ((x) & (~BITS_MISSED_RPT_NUM_8814B))\n#define BIT_GET_MISSED_RPT_NUM_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_MISSED_RPT_NUM_8814B) &                             \\\n\t BIT_MASK_MISSED_RPT_NUM_8814B)\n#define BIT_SET_MISSED_RPT_NUM_8814B(x, v)                                     \\\n\t(BIT_CLEAR_MISSED_RPT_NUM_8814B(x) | BIT_MISSED_RPT_NUM_8814B(v))\n\n#define BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B 16\n#define BIT_MASK_MACID_CTRL_OFFSET_V1_8814B 0x1ff\n#define BIT_MACID_CTRL_OFFSET_V1_8814B(x)                                      \\\n\t(((x) & BIT_MASK_MACID_CTRL_OFFSET_V1_8814B)                           \\\n\t << BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B)\n#define BITS_MACID_CTRL_OFFSET_V1_8814B                                        \\\n\t(BIT_MASK_MACID_CTRL_OFFSET_V1_8814B                                   \\\n\t << BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B)\n#define BIT_CLEAR_MACID_CTRL_OFFSET_V1_8814B(x)                                \\\n\t((x) & (~BITS_MACID_CTRL_OFFSET_V1_8814B))\n#define BIT_GET_MACID_CTRL_OFFSET_V1_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B) &                       \\\n\t BIT_MASK_MACID_CTRL_OFFSET_V1_8814B)\n#define BIT_SET_MACID_CTRL_OFFSET_V1_8814B(x, v)                               \\\n\t(BIT_CLEAR_MACID_CTRL_OFFSET_V1_8814B(x) |                             \\\n\t BIT_MACID_CTRL_OFFSET_V1_8814B(v))\n\n#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B 0\n#define BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B 0x1ff\n#define BIT_AMPDU_TXRPT_OFFSET_V1_8814B(x)                                     \\\n\t(((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B)                          \\\n\t << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B)\n#define BITS_AMPDU_TXRPT_OFFSET_V1_8814B                                       \\\n\t(BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B                                  \\\n\t << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B)\n#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1_8814B(x)                               \\\n\t((x) & (~BITS_AMPDU_TXRPT_OFFSET_V1_8814B))\n#define BIT_GET_AMPDU_TXRPT_OFFSET_V1_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B) &                      \\\n\t BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B)\n#define BIT_SET_AMPDU_TXRPT_OFFSET_V1_8814B(x, v)                              \\\n\t(BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1_8814B(x) |                            \\\n\t BIT_AMPDU_TXRPT_OFFSET_V1_8814B(v))\n\n/* 2 REG_POWER_STAGE1_8814B */\n#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8814B BIT(31)\n#define BIT_PTA_WL_PRI_MASK_BCNQ_8814B BIT(30)\n#define BIT_PTA_WL_PRI_MASK_HIQ_8814B BIT(29)\n#define BIT_PTA_WL_PRI_MASK_MGQ_8814B BIT(28)\n#define BIT_PTA_WL_PRI_MASK_BK_8814B BIT(27)\n#define BIT_PTA_WL_PRI_MASK_BE_8814B BIT(26)\n#define BIT_PTA_WL_PRI_MASK_VI_8814B BIT(25)\n#define BIT_PTA_WL_PRI_MASK_VO_8814B BIT(24)\n\n#define BIT_SHIFT_POWER_STAGE1_8814B 0\n#define BIT_MASK_POWER_STAGE1_8814B 0xffffff\n#define BIT_POWER_STAGE1_8814B(x)                                              \\\n\t(((x) & BIT_MASK_POWER_STAGE1_8814B) << BIT_SHIFT_POWER_STAGE1_8814B)\n#define BITS_POWER_STAGE1_8814B                                                \\\n\t(BIT_MASK_POWER_STAGE1_8814B << BIT_SHIFT_POWER_STAGE1_8814B)\n#define BIT_CLEAR_POWER_STAGE1_8814B(x) ((x) & (~BITS_POWER_STAGE1_8814B))\n#define BIT_GET_POWER_STAGE1_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_POWER_STAGE1_8814B) & BIT_MASK_POWER_STAGE1_8814B)\n#define BIT_SET_POWER_STAGE1_8814B(x, v)                                       \\\n\t(BIT_CLEAR_POWER_STAGE1_8814B(x) | BIT_POWER_STAGE1_8814B(v))\n\n/* 2 REG_POWER_STAGE2_8814B */\n#define BIT__CTRL_PKT_POW_ADJ_8814B BIT(24)\n\n#define BIT_SHIFT_POWER_STAGE2_8814B 0\n#define BIT_MASK_POWER_STAGE2_8814B 0xffffff\n#define BIT_POWER_STAGE2_8814B(x)                                              \\\n\t(((x) & BIT_MASK_POWER_STAGE2_8814B) << BIT_SHIFT_POWER_STAGE2_8814B)\n#define BITS_POWER_STAGE2_8814B                                                \\\n\t(BIT_MASK_POWER_STAGE2_8814B << BIT_SHIFT_POWER_STAGE2_8814B)\n#define BIT_CLEAR_POWER_STAGE2_8814B(x) ((x) & (~BITS_POWER_STAGE2_8814B))\n#define BIT_GET_POWER_STAGE2_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_POWER_STAGE2_8814B) & BIT_MASK_POWER_STAGE2_8814B)\n#define BIT_SET_POWER_STAGE2_8814B(x, v)                                       \\\n\t(BIT_CLEAR_POWER_STAGE2_8814B(x) | BIT_POWER_STAGE2_8814B(v))\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8814B */\n#define BIT_DMA_THIS_QUEUE_BK_8814B BIT(23)\n#define BIT_DMA_THIS_QUEUE_BE_8814B BIT(22)\n#define BIT_DMA_THIS_QUEUE_VI_8814B BIT(21)\n#define BIT_DMA_THIS_QUEUE_VO_8814B BIT(20)\n\n#define BIT_SHIFT_TOTAL_LEN_TH_8814B 8\n#define BIT_MASK_TOTAL_LEN_TH_8814B 0xfff\n#define BIT_TOTAL_LEN_TH_8814B(x)                                              \\\n\t(((x) & BIT_MASK_TOTAL_LEN_TH_8814B) << BIT_SHIFT_TOTAL_LEN_TH_8814B)\n#define BITS_TOTAL_LEN_TH_8814B                                                \\\n\t(BIT_MASK_TOTAL_LEN_TH_8814B << BIT_SHIFT_TOTAL_LEN_TH_8814B)\n#define BIT_CLEAR_TOTAL_LEN_TH_8814B(x) ((x) & (~BITS_TOTAL_LEN_TH_8814B))\n#define BIT_GET_TOTAL_LEN_TH_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_TOTAL_LEN_TH_8814B) & BIT_MASK_TOTAL_LEN_TH_8814B)\n#define BIT_SET_TOTAL_LEN_TH_8814B(x, v)                                       \\\n\t(BIT_CLEAR_TOTAL_LEN_TH_8814B(x) | BIT_TOTAL_LEN_TH_8814B(v))\n\n#define BIT_PRE_TX_CMD_8814B BIT(6)\n\n#define BIT_SHIFT_NUM_SCL_EN_8814B 4\n#define BIT_MASK_NUM_SCL_EN_8814B 0x3\n#define BIT_NUM_SCL_EN_8814B(x)                                                \\\n\t(((x) & BIT_MASK_NUM_SCL_EN_8814B) << BIT_SHIFT_NUM_SCL_EN_8814B)\n#define BITS_NUM_SCL_EN_8814B                                                  \\\n\t(BIT_MASK_NUM_SCL_EN_8814B << BIT_SHIFT_NUM_SCL_EN_8814B)\n#define BIT_CLEAR_NUM_SCL_EN_8814B(x) ((x) & (~BITS_NUM_SCL_EN_8814B))\n#define BIT_GET_NUM_SCL_EN_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_NUM_SCL_EN_8814B) & BIT_MASK_NUM_SCL_EN_8814B)\n#define BIT_SET_NUM_SCL_EN_8814B(x, v)                                         \\\n\t(BIT_CLEAR_NUM_SCL_EN_8814B(x) | BIT_NUM_SCL_EN_8814B(v))\n\n#define BIT_BK_EN_8814B BIT(3)\n#define BIT_BE_EN_8814B BIT(2)\n#define BIT_VI_EN_8814B BIT(1)\n#define BIT_VO_EN_8814B BIT(0)\n\n/* 2 REG_PKT_LIFE_TIME_8814B */\n\n#define BIT_SHIFT_PKT_LIFTIME_BEBK_8814B 16\n#define BIT_MASK_PKT_LIFTIME_BEBK_8814B 0xffff\n#define BIT_PKT_LIFTIME_BEBK_8814B(x)                                          \\\n\t(((x) & BIT_MASK_PKT_LIFTIME_BEBK_8814B)                               \\\n\t << BIT_SHIFT_PKT_LIFTIME_BEBK_8814B)\n#define BITS_PKT_LIFTIME_BEBK_8814B                                            \\\n\t(BIT_MASK_PKT_LIFTIME_BEBK_8814B << BIT_SHIFT_PKT_LIFTIME_BEBK_8814B)\n#define BIT_CLEAR_PKT_LIFTIME_BEBK_8814B(x)                                    \\\n\t((x) & (~BITS_PKT_LIFTIME_BEBK_8814B))\n#define BIT_GET_PKT_LIFTIME_BEBK_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8814B) &                           \\\n\t BIT_MASK_PKT_LIFTIME_BEBK_8814B)\n#define BIT_SET_PKT_LIFTIME_BEBK_8814B(x, v)                                   \\\n\t(BIT_CLEAR_PKT_LIFTIME_BEBK_8814B(x) | BIT_PKT_LIFTIME_BEBK_8814B(v))\n\n#define BIT_SHIFT_PKT_LIFTIME_VOVI_8814B 0\n#define BIT_MASK_PKT_LIFTIME_VOVI_8814B 0xffff\n#define BIT_PKT_LIFTIME_VOVI_8814B(x)                                          \\\n\t(((x) & BIT_MASK_PKT_LIFTIME_VOVI_8814B)                               \\\n\t << BIT_SHIFT_PKT_LIFTIME_VOVI_8814B)\n#define BITS_PKT_LIFTIME_VOVI_8814B                                            \\\n\t(BIT_MASK_PKT_LIFTIME_VOVI_8814B << BIT_SHIFT_PKT_LIFTIME_VOVI_8814B)\n#define BIT_CLEAR_PKT_LIFTIME_VOVI_8814B(x)                                    \\\n\t((x) & (~BITS_PKT_LIFTIME_VOVI_8814B))\n#define BIT_GET_PKT_LIFTIME_VOVI_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8814B) &                           \\\n\t BIT_MASK_PKT_LIFTIME_VOVI_8814B)\n#define BIT_SET_PKT_LIFTIME_VOVI_8814B(x, v)                                   \\\n\t(BIT_CLEAR_PKT_LIFTIME_VOVI_8814B(x) | BIT_PKT_LIFTIME_VOVI_8814B(v))\n\n/* 2 REG_STBC_SETTING_8814B */\n\n#define BIT_SHIFT_CDEND_TXTIME_L_8814B 4\n#define BIT_MASK_CDEND_TXTIME_L_8814B 0xf\n#define BIT_CDEND_TXTIME_L_8814B(x)                                            \\\n\t(((x) & BIT_MASK_CDEND_TXTIME_L_8814B)                                 \\\n\t << BIT_SHIFT_CDEND_TXTIME_L_8814B)\n#define BITS_CDEND_TXTIME_L_8814B                                              \\\n\t(BIT_MASK_CDEND_TXTIME_L_8814B << BIT_SHIFT_CDEND_TXTIME_L_8814B)\n#define BIT_CLEAR_CDEND_TXTIME_L_8814B(x) ((x) & (~BITS_CDEND_TXTIME_L_8814B))\n#define BIT_GET_CDEND_TXTIME_L_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_CDEND_TXTIME_L_8814B) &                             \\\n\t BIT_MASK_CDEND_TXTIME_L_8814B)\n#define BIT_SET_CDEND_TXTIME_L_8814B(x, v)                                     \\\n\t(BIT_CLEAR_CDEND_TXTIME_L_8814B(x) | BIT_CDEND_TXTIME_L_8814B(v))\n\n#define BIT_SHIFT_NESS_8814B 2\n#define BIT_MASK_NESS_8814B 0x3\n#define BIT_NESS_8814B(x) (((x) & BIT_MASK_NESS_8814B) << BIT_SHIFT_NESS_8814B)\n#define BITS_NESS_8814B (BIT_MASK_NESS_8814B << BIT_SHIFT_NESS_8814B)\n#define BIT_CLEAR_NESS_8814B(x) ((x) & (~BITS_NESS_8814B))\n#define BIT_GET_NESS_8814B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_NESS_8814B) & BIT_MASK_NESS_8814B)\n#define BIT_SET_NESS_8814B(x, v) (BIT_CLEAR_NESS_8814B(x) | BIT_NESS_8814B(v))\n\n#define BIT_SHIFT_STBC_CFEND_8814B 0\n#define BIT_MASK_STBC_CFEND_8814B 0x3\n#define BIT_STBC_CFEND_8814B(x)                                                \\\n\t(((x) & BIT_MASK_STBC_CFEND_8814B) << BIT_SHIFT_STBC_CFEND_8814B)\n#define BITS_STBC_CFEND_8814B                                                  \\\n\t(BIT_MASK_STBC_CFEND_8814B << BIT_SHIFT_STBC_CFEND_8814B)\n#define BIT_CLEAR_STBC_CFEND_8814B(x) ((x) & (~BITS_STBC_CFEND_8814B))\n#define BIT_GET_STBC_CFEND_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_STBC_CFEND_8814B) & BIT_MASK_STBC_CFEND_8814B)\n#define BIT_SET_STBC_CFEND_8814B(x, v)                                         \\\n\t(BIT_CLEAR_STBC_CFEND_8814B(x) | BIT_STBC_CFEND_8814B(v))\n\n/* 2 REG_STBC_SETTING2_8814B */\n\n#define BIT_SHIFT_CDEND_TXTIME_H_8814B 0\n#define BIT_MASK_CDEND_TXTIME_H_8814B 0x1f\n#define BIT_CDEND_TXTIME_H_8814B(x)                                            \\\n\t(((x) & BIT_MASK_CDEND_TXTIME_H_8814B)                                 \\\n\t << BIT_SHIFT_CDEND_TXTIME_H_8814B)\n#define BITS_CDEND_TXTIME_H_8814B                                              \\\n\t(BIT_MASK_CDEND_TXTIME_H_8814B << BIT_SHIFT_CDEND_TXTIME_H_8814B)\n#define BIT_CLEAR_CDEND_TXTIME_H_8814B(x) ((x) & (~BITS_CDEND_TXTIME_H_8814B))\n#define BIT_GET_CDEND_TXTIME_H_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_CDEND_TXTIME_H_8814B) &                             \\\n\t BIT_MASK_CDEND_TXTIME_H_8814B)\n#define BIT_SET_CDEND_TXTIME_H_8814B(x, v)                                     \\\n\t(BIT_CLEAR_CDEND_TXTIME_H_8814B(x) | BIT_CDEND_TXTIME_H_8814B(v))\n\n/* 2 REG_QUEUE_CTRL_8814B */\n#define BIT_FORCE_RND_PRI_8814B BIT(6)\n#define BIT_PTA_EDCCA_EN_8814B BIT(5)\n#define BIT_PTA_WL_TX_EN_8814B BIT(4)\n#define BIT_USE_DATA_BW_8814B BIT(3)\n#define BIT_TRI_PKT_INT_MODE1_8814B BIT(2)\n#define BIT_TRI_PKT_INT_MODE0_8814B BIT(1)\n#define BIT_ACQ_MODE_SEL_8814B BIT(0)\n\n/* 2 REG_SINGLE_AMPDU_CTRL_8814B */\n#define BIT_EN_SINGLE_APMDU_8814B BIT(7)\n\n/* 2 REG_PROT_MODE_CTRL_8814B */\n\n#define BIT_SHIFT_RTS_MAX_AGG_NUM_8814B 24\n#define BIT_MASK_RTS_MAX_AGG_NUM_8814B 0x3f\n#define BIT_RTS_MAX_AGG_NUM_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RTS_MAX_AGG_NUM_8814B)                                \\\n\t << BIT_SHIFT_RTS_MAX_AGG_NUM_8814B)\n#define BITS_RTS_MAX_AGG_NUM_8814B                                             \\\n\t(BIT_MASK_RTS_MAX_AGG_NUM_8814B << BIT_SHIFT_RTS_MAX_AGG_NUM_8814B)\n#define BIT_CLEAR_RTS_MAX_AGG_NUM_8814B(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8814B))\n#define BIT_GET_RTS_MAX_AGG_NUM_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8814B) &                            \\\n\t BIT_MASK_RTS_MAX_AGG_NUM_8814B)\n#define BIT_SET_RTS_MAX_AGG_NUM_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RTS_MAX_AGG_NUM_8814B(x) | BIT_RTS_MAX_AGG_NUM_8814B(v))\n\n#define BIT_SHIFT_MAX_AGG_NUM_8814B 16\n#define BIT_MASK_MAX_AGG_NUM_8814B 0x3f\n#define BIT_MAX_AGG_NUM_8814B(x)                                               \\\n\t(((x) & BIT_MASK_MAX_AGG_NUM_8814B) << BIT_SHIFT_MAX_AGG_NUM_8814B)\n#define BITS_MAX_AGG_NUM_8814B                                                 \\\n\t(BIT_MASK_MAX_AGG_NUM_8814B << BIT_SHIFT_MAX_AGG_NUM_8814B)\n#define BIT_CLEAR_MAX_AGG_NUM_8814B(x) ((x) & (~BITS_MAX_AGG_NUM_8814B))\n#define BIT_GET_MAX_AGG_NUM_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_MAX_AGG_NUM_8814B) & BIT_MASK_MAX_AGG_NUM_8814B)\n#define BIT_SET_MAX_AGG_NUM_8814B(x, v)                                        \\\n\t(BIT_CLEAR_MAX_AGG_NUM_8814B(x) | BIT_MAX_AGG_NUM_8814B(v))\n\n#define BIT_SHIFT_RTS_TXTIME_TH_8814B 8\n#define BIT_MASK_RTS_TXTIME_TH_8814B 0xff\n#define BIT_RTS_TXTIME_TH_8814B(x)                                             \\\n\t(((x) & BIT_MASK_RTS_TXTIME_TH_8814B) << BIT_SHIFT_RTS_TXTIME_TH_8814B)\n#define BITS_RTS_TXTIME_TH_8814B                                               \\\n\t(BIT_MASK_RTS_TXTIME_TH_8814B << BIT_SHIFT_RTS_TXTIME_TH_8814B)\n#define BIT_CLEAR_RTS_TXTIME_TH_8814B(x) ((x) & (~BITS_RTS_TXTIME_TH_8814B))\n#define BIT_GET_RTS_TXTIME_TH_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_RTS_TXTIME_TH_8814B) & BIT_MASK_RTS_TXTIME_TH_8814B)\n#define BIT_SET_RTS_TXTIME_TH_8814B(x, v)                                      \\\n\t(BIT_CLEAR_RTS_TXTIME_TH_8814B(x) | BIT_RTS_TXTIME_TH_8814B(v))\n\n#define BIT_SHIFT_RTS_LEN_TH_8814B 0\n#define BIT_MASK_RTS_LEN_TH_8814B 0xff\n#define BIT_RTS_LEN_TH_8814B(x)                                                \\\n\t(((x) & BIT_MASK_RTS_LEN_TH_8814B) << BIT_SHIFT_RTS_LEN_TH_8814B)\n#define BITS_RTS_LEN_TH_8814B                                                  \\\n\t(BIT_MASK_RTS_LEN_TH_8814B << BIT_SHIFT_RTS_LEN_TH_8814B)\n#define BIT_CLEAR_RTS_LEN_TH_8814B(x) ((x) & (~BITS_RTS_LEN_TH_8814B))\n#define BIT_GET_RTS_LEN_TH_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_RTS_LEN_TH_8814B) & BIT_MASK_RTS_LEN_TH_8814B)\n#define BIT_SET_RTS_LEN_TH_8814B(x, v)                                         \\\n\t(BIT_CLEAR_RTS_LEN_TH_8814B(x) | BIT_RTS_LEN_TH_8814B(v))\n\n/* 2 REG_BAR_MODE_CTRL_8814B */\n\n#define BIT_SHIFT_BAR_RTY_LMT_8814B 16\n#define BIT_MASK_BAR_RTY_LMT_8814B 0x3\n#define BIT_BAR_RTY_LMT_8814B(x)                                               \\\n\t(((x) & BIT_MASK_BAR_RTY_LMT_8814B) << BIT_SHIFT_BAR_RTY_LMT_8814B)\n#define BITS_BAR_RTY_LMT_8814B                                                 \\\n\t(BIT_MASK_BAR_RTY_LMT_8814B << BIT_SHIFT_BAR_RTY_LMT_8814B)\n#define BIT_CLEAR_BAR_RTY_LMT_8814B(x) ((x) & (~BITS_BAR_RTY_LMT_8814B))\n#define BIT_GET_BAR_RTY_LMT_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_BAR_RTY_LMT_8814B) & BIT_MASK_BAR_RTY_LMT_8814B)\n#define BIT_SET_BAR_RTY_LMT_8814B(x, v)                                        \\\n\t(BIT_CLEAR_BAR_RTY_LMT_8814B(x) | BIT_BAR_RTY_LMT_8814B(v))\n\n#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B 8\n#define BIT_MASK_BAR_PKT_TXTIME_TH_8814B 0xff\n#define BIT_BAR_PKT_TXTIME_TH_8814B(x)                                         \\\n\t(((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8814B)                              \\\n\t << BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B)\n#define BITS_BAR_PKT_TXTIME_TH_8814B                                           \\\n\t(BIT_MASK_BAR_PKT_TXTIME_TH_8814B << BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B)\n#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8814B(x)                                   \\\n\t((x) & (~BITS_BAR_PKT_TXTIME_TH_8814B))\n#define BIT_GET_BAR_PKT_TXTIME_TH_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B) &                          \\\n\t BIT_MASK_BAR_PKT_TXTIME_TH_8814B)\n#define BIT_SET_BAR_PKT_TXTIME_TH_8814B(x, v)                                  \\\n\t(BIT_CLEAR_BAR_PKT_TXTIME_TH_8814B(x) | BIT_BAR_PKT_TXTIME_TH_8814B(v))\n\n#define BIT_BAR_EN_V1_8814B BIT(6)\n\n#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B 0\n#define BIT_MASK_BAR_PKTNUM_TH_V1_8814B 0x3f\n#define BIT_BAR_PKTNUM_TH_V1_8814B(x)                                          \\\n\t(((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8814B)                               \\\n\t << BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B)\n#define BITS_BAR_PKTNUM_TH_V1_8814B                                            \\\n\t(BIT_MASK_BAR_PKTNUM_TH_V1_8814B << BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B)\n#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8814B(x)                                    \\\n\t((x) & (~BITS_BAR_PKTNUM_TH_V1_8814B))\n#define BIT_GET_BAR_PKTNUM_TH_V1_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B) &                           \\\n\t BIT_MASK_BAR_PKTNUM_TH_V1_8814B)\n#define BIT_SET_BAR_PKTNUM_TH_V1_8814B(x, v)                                   \\\n\t(BIT_CLEAR_BAR_PKTNUM_TH_V1_8814B(x) | BIT_BAR_PKTNUM_TH_V1_8814B(v))\n\n/* 2 REG_RA_TRY_RATE_AGG_LMT_8814B */\n\n#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B 0\n#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B 0x3f\n#define BIT_RA_TRY_RATE_AGG_LMT_V1_8814B(x)                                    \\\n\t(((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B)                         \\\n\t << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B)\n#define BITS_RA_TRY_RATE_AGG_LMT_V1_8814B                                      \\\n\t(BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B                                 \\\n\t << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B)\n#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8814B(x)                              \\\n\t((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8814B))\n#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8814B(x)                                \\\n\t(((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B) &                     \\\n\t BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B)\n#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8814B(x, v)                             \\\n\t(BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8814B(x) |                           \\\n\t BIT_RA_TRY_RATE_AGG_LMT_V1_8814B(v))\n\n/* 2 REG_MACID_SLEEP_CTRL_8814B */\n\n#define BIT_SHIFT_DEBUG_PROTOCOL_8814B 24\n#define BIT_MASK_DEBUG_PROTOCOL_8814B 0xff\n#define BIT_DEBUG_PROTOCOL_8814B(x)                                            \\\n\t(((x) & BIT_MASK_DEBUG_PROTOCOL_8814B)                                 \\\n\t << BIT_SHIFT_DEBUG_PROTOCOL_8814B)\n#define BITS_DEBUG_PROTOCOL_8814B                                              \\\n\t(BIT_MASK_DEBUG_PROTOCOL_8814B << BIT_SHIFT_DEBUG_PROTOCOL_8814B)\n#define BIT_CLEAR_DEBUG_PROTOCOL_8814B(x) ((x) & (~BITS_DEBUG_PROTOCOL_8814B))\n#define BIT_GET_DEBUG_PROTOCOL_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_DEBUG_PROTOCOL_8814B) &                             \\\n\t BIT_MASK_DEBUG_PROTOCOL_8814B)\n#define BIT_SET_DEBUG_PROTOCOL_8814B(x, v)                                     \\\n\t(BIT_CLEAR_DEBUG_PROTOCOL_8814B(x) | BIT_DEBUG_PROTOCOL_8814B(v))\n\n#define BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B 16\n#define BIT_MASK_BCNQ_PGBNDY_RSEL_8814B 0x7\n#define BIT_BCNQ_PGBNDY_RSEL_8814B(x)                                          \\\n\t(((x) & BIT_MASK_BCNQ_PGBNDY_RSEL_8814B)                               \\\n\t << BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B)\n#define BITS_BCNQ_PGBNDY_RSEL_8814B                                            \\\n\t(BIT_MASK_BCNQ_PGBNDY_RSEL_8814B << BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B)\n#define BIT_CLEAR_BCNQ_PGBNDY_RSEL_8814B(x)                                    \\\n\t((x) & (~BITS_BCNQ_PGBNDY_RSEL_8814B))\n#define BIT_GET_BCNQ_PGBNDY_RSEL_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B) &                           \\\n\t BIT_MASK_BCNQ_PGBNDY_RSEL_8814B)\n#define BIT_SET_BCNQ_PGBNDY_RSEL_8814B(x, v)                                   \\\n\t(BIT_CLEAR_BCNQ_PGBNDY_RSEL_8814B(x) | BIT_BCNQ_PGBNDY_RSEL_8814B(v))\n\n#define BIT_SHIFT_MACID_SLEEP_SEL_8814B 0\n#define BIT_MASK_MACID_SLEEP_SEL_8814B 0x7\n#define BIT_MACID_SLEEP_SEL_8814B(x)                                           \\\n\t(((x) & BIT_MASK_MACID_SLEEP_SEL_8814B)                                \\\n\t << BIT_SHIFT_MACID_SLEEP_SEL_8814B)\n#define BITS_MACID_SLEEP_SEL_8814B                                             \\\n\t(BIT_MASK_MACID_SLEEP_SEL_8814B << BIT_SHIFT_MACID_SLEEP_SEL_8814B)\n#define BIT_CLEAR_MACID_SLEEP_SEL_8814B(x) ((x) & (~BITS_MACID_SLEEP_SEL_8814B))\n#define BIT_GET_MACID_SLEEP_SEL_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_MACID_SLEEP_SEL_8814B) &                            \\\n\t BIT_MASK_MACID_SLEEP_SEL_8814B)\n#define BIT_SET_MACID_SLEEP_SEL_8814B(x, v)                                    \\\n\t(BIT_CLEAR_MACID_SLEEP_SEL_8814B(x) | BIT_MACID_SLEEP_SEL_8814B(v))\n\n/* 2 REG_MACID_SLEEP_INFO_8814B */\n\n#define BIT_SHIFT_MACID_SLEEP_INFO_8814B 0\n#define BIT_MASK_MACID_SLEEP_INFO_8814B 0xffffffffL\n#define BIT_MACID_SLEEP_INFO_8814B(x)                                          \\\n\t(((x) & BIT_MASK_MACID_SLEEP_INFO_8814B)                               \\\n\t << BIT_SHIFT_MACID_SLEEP_INFO_8814B)\n#define BITS_MACID_SLEEP_INFO_8814B                                            \\\n\t(BIT_MASK_MACID_SLEEP_INFO_8814B << BIT_SHIFT_MACID_SLEEP_INFO_8814B)\n#define BIT_CLEAR_MACID_SLEEP_INFO_8814B(x)                                    \\\n\t((x) & (~BITS_MACID_SLEEP_INFO_8814B))\n#define BIT_GET_MACID_SLEEP_INFO_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_MACID_SLEEP_INFO_8814B) &                           \\\n\t BIT_MASK_MACID_SLEEP_INFO_8814B)\n#define BIT_SET_MACID_SLEEP_INFO_8814B(x, v)                                   \\\n\t(BIT_CLEAR_MACID_SLEEP_INFO_8814B(x) | BIT_MACID_SLEEP_INFO_8814B(v))\n\n/* 2 REG_HW_SEQ0_8814B */\n\n#define BIT_SHIFT_HW_SSN_SEQ0_8814B 0\n#define BIT_MASK_HW_SSN_SEQ0_8814B 0xfff\n#define BIT_HW_SSN_SEQ0_8814B(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ0_8814B) << BIT_SHIFT_HW_SSN_SEQ0_8814B)\n#define BITS_HW_SSN_SEQ0_8814B                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ0_8814B << BIT_SHIFT_HW_SSN_SEQ0_8814B)\n#define BIT_CLEAR_HW_SSN_SEQ0_8814B(x) ((x) & (~BITS_HW_SSN_SEQ0_8814B))\n#define BIT_GET_HW_SSN_SEQ0_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ0_8814B) & BIT_MASK_HW_SSN_SEQ0_8814B)\n#define BIT_SET_HW_SSN_SEQ0_8814B(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ0_8814B(x) | BIT_HW_SSN_SEQ0_8814B(v))\n\n/* 2 REG_HW_SEQ1_8814B */\n\n#define BIT_SHIFT_HW_SSN_SEQ1_8814B 0\n#define BIT_MASK_HW_SSN_SEQ1_8814B 0xfff\n#define BIT_HW_SSN_SEQ1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ1_8814B) << BIT_SHIFT_HW_SSN_SEQ1_8814B)\n#define BITS_HW_SSN_SEQ1_8814B                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ1_8814B << BIT_SHIFT_HW_SSN_SEQ1_8814B)\n#define BIT_CLEAR_HW_SSN_SEQ1_8814B(x) ((x) & (~BITS_HW_SSN_SEQ1_8814B))\n#define BIT_GET_HW_SSN_SEQ1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ1_8814B) & BIT_MASK_HW_SSN_SEQ1_8814B)\n#define BIT_SET_HW_SSN_SEQ1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ1_8814B(x) | BIT_HW_SSN_SEQ1_8814B(v))\n\n/* 2 REG_HW_SEQ2_8814B */\n\n#define BIT_SHIFT_HW_SSN_SEQ2_8814B 0\n#define BIT_MASK_HW_SSN_SEQ2_8814B 0xfff\n#define BIT_HW_SSN_SEQ2_8814B(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ2_8814B) << BIT_SHIFT_HW_SSN_SEQ2_8814B)\n#define BITS_HW_SSN_SEQ2_8814B                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ2_8814B << BIT_SHIFT_HW_SSN_SEQ2_8814B)\n#define BIT_CLEAR_HW_SSN_SEQ2_8814B(x) ((x) & (~BITS_HW_SSN_SEQ2_8814B))\n#define BIT_GET_HW_SSN_SEQ2_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ2_8814B) & BIT_MASK_HW_SSN_SEQ2_8814B)\n#define BIT_SET_HW_SSN_SEQ2_8814B(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ2_8814B(x) | BIT_HW_SSN_SEQ2_8814B(v))\n\n/* 2 REG_HW_SEQ3_8814B */\n\n#define BIT_SHIFT_CSI_HWSEQ_SEL_8814B 12\n#define BIT_MASK_CSI_HWSEQ_SEL_8814B 0x3\n#define BIT_CSI_HWSEQ_SEL_8814B(x)                                             \\\n\t(((x) & BIT_MASK_CSI_HWSEQ_SEL_8814B) << BIT_SHIFT_CSI_HWSEQ_SEL_8814B)\n#define BITS_CSI_HWSEQ_SEL_8814B                                               \\\n\t(BIT_MASK_CSI_HWSEQ_SEL_8814B << BIT_SHIFT_CSI_HWSEQ_SEL_8814B)\n#define BIT_CLEAR_CSI_HWSEQ_SEL_8814B(x) ((x) & (~BITS_CSI_HWSEQ_SEL_8814B))\n#define BIT_GET_CSI_HWSEQ_SEL_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_CSI_HWSEQ_SEL_8814B) & BIT_MASK_CSI_HWSEQ_SEL_8814B)\n#define BIT_SET_CSI_HWSEQ_SEL_8814B(x, v)                                      \\\n\t(BIT_CLEAR_CSI_HWSEQ_SEL_8814B(x) | BIT_CSI_HWSEQ_SEL_8814B(v))\n\n#define BIT_SHIFT_HW_SSN_SEQ3_8814B 0\n#define BIT_MASK_HW_SSN_SEQ3_8814B 0xfff\n#define BIT_HW_SSN_SEQ3_8814B(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ3_8814B) << BIT_SHIFT_HW_SSN_SEQ3_8814B)\n#define BITS_HW_SSN_SEQ3_8814B                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ3_8814B << BIT_SHIFT_HW_SSN_SEQ3_8814B)\n#define BIT_CLEAR_HW_SSN_SEQ3_8814B(x) ((x) & (~BITS_HW_SSN_SEQ3_8814B))\n#define BIT_GET_HW_SSN_SEQ3_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ3_8814B) & BIT_MASK_HW_SSN_SEQ3_8814B)\n#define BIT_SET_HW_SSN_SEQ3_8814B(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ3_8814B(x) | BIT_HW_SSN_SEQ3_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B 0\n#define BIT_MASK_PTCL_TOTAL_PG_V3_8814B 0x1fff\n#define BIT_PTCL_TOTAL_PG_V3_8814B(x)                                          \\\n\t(((x) & BIT_MASK_PTCL_TOTAL_PG_V3_8814B)                               \\\n\t << BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B)\n#define BITS_PTCL_TOTAL_PG_V3_8814B                                            \\\n\t(BIT_MASK_PTCL_TOTAL_PG_V3_8814B << BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B)\n#define BIT_CLEAR_PTCL_TOTAL_PG_V3_8814B(x)                                    \\\n\t((x) & (~BITS_PTCL_TOTAL_PG_V3_8814B))\n#define BIT_GET_PTCL_TOTAL_PG_V3_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B) &                           \\\n\t BIT_MASK_PTCL_TOTAL_PG_V3_8814B)\n#define BIT_SET_PTCL_TOTAL_PG_V3_8814B(x, v)                                   \\\n\t(BIT_CLEAR_PTCL_TOTAL_PG_V3_8814B(x) | BIT_PTCL_TOTAL_PG_V3_8814B(v))\n\n/* 2 REG_PTCL_ERR_STATUS_V1_8814B */\n#define BIT_MUARB_SEARCH_ERR_8814B BIT(14)\n#define BIT_MU_BFEN_ERR_8814B BIT(12)\n#define BIT_NDPA_DROPNULL_ERR_8814B BIT(11)\n#define BIT_NDPA_DROPPKT_ERR_8814B BIT(10)\n#define BIT_PTCL_PKYIN_ERR_8814B BIT(9)\n#define BIT_PTCL_QSELCNL_ERR_8814B BIT(8)\n#define BIT_PTCL_RATE_TABLE_INVALID_8814B BIT(7)\n#define BIT_FTM_T2R_ERROR_8814B BIT(6)\n#define BIT_TXTIMEOUT_ERR_8814B BIT(5)\n#define BIT_NULLPAGE_ERR_8814B BIT(4)\n#define BIT_CONTENTION_ERR_8814B BIT(3)\n#define BIT_HEADNULL_ERR_8814B BIT(2)\n#define BIT_OVERFLOW_ERR_8814B BIT(1)\n#define BIT_QUEUE_INDEX_ERR_8814B BIT(0)\n\n/* 2 REG_NULL_PKT_STATUS_V2_8814B */\n#define BIT_HIQ_DROP_8814B BIT(7)\n#define BIT_MGQ_DROP_8814B BIT(6)\n#define BIT_TX_NULL_1_V1_8814B BIT(1)\n#define BIT_TX_NULL_0_V1_8814B BIT(0)\n\n/* 2 REG_PRECNT_CTRL_8814B */\n#define BIT_EN_PRECNT_8814B BIT(11)\n\n#define BIT_SHIFT_PRECNT_TH_8814B 0\n#define BIT_MASK_PRECNT_TH_8814B 0x7ff\n#define BIT_PRECNT_TH_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_PRECNT_TH_8814B) << BIT_SHIFT_PRECNT_TH_8814B)\n#define BITS_PRECNT_TH_8814B                                                   \\\n\t(BIT_MASK_PRECNT_TH_8814B << BIT_SHIFT_PRECNT_TH_8814B)\n#define BIT_CLEAR_PRECNT_TH_8814B(x) ((x) & (~BITS_PRECNT_TH_8814B))\n#define BIT_GET_PRECNT_TH_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_PRECNT_TH_8814B) & BIT_MASK_PRECNT_TH_8814B)\n#define BIT_SET_PRECNT_TH_8814B(x, v)                                          \\\n\t(BIT_CLEAR_PRECNT_TH_8814B(x) | BIT_PRECNT_TH_8814B(v))\n\n/* 2 REG_NULL_PKT_STATUS_EXTEND_V1_8814B */\n#define BIT_CLI3_TX_NULL_1_V1_8814B BIT(7)\n#define BIT_CLI3_TX_NULL_0_V1_8814B BIT(6)\n#define BIT_CLI2_TX_NULL_1_V1_8814B BIT(5)\n#define BIT_CLI2_TX_NULL_0_V1_8814B BIT(4)\n#define BIT_CLI1_TX_NULL_1_V1_8814B BIT(3)\n#define BIT_CLI1_TX_NULL_0_V1_8814B BIT(2)\n#define BIT_CLI0_TX_NULL_1_V1_8814B BIT(1)\n#define BIT_CLI0_TX_NULL_0_V1_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_PTCL_DBG_V1_8814B */\n\n#define BIT_SHIFT_PTCL_DBG_8814B 0\n#define BIT_MASK_PTCL_DBG_8814B 0xffffffffL\n#define BIT_PTCL_DBG_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_PTCL_DBG_8814B) << BIT_SHIFT_PTCL_DBG_8814B)\n#define BITS_PTCL_DBG_8814B                                                    \\\n\t(BIT_MASK_PTCL_DBG_8814B << BIT_SHIFT_PTCL_DBG_8814B)\n#define BIT_CLEAR_PTCL_DBG_8814B(x) ((x) & (~BITS_PTCL_DBG_8814B))\n#define BIT_GET_PTCL_DBG_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_PTCL_DBG_8814B) & BIT_MASK_PTCL_DBG_8814B)\n#define BIT_SET_PTCL_DBG_8814B(x, v)                                           \\\n\t(BIT_CLEAR_PTCL_DBG_8814B(x) | BIT_PTCL_DBG_8814B(v))\n\n/* 2 REG_BT_POLLUTE_PKTCNT_8814B */\n\n#define BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B 0\n#define BIT_MASK_BT_POLLUTE_PKTCNT_8814B 0xffff\n#define BIT_BT_POLLUTE_PKTCNT_8814B(x)                                         \\\n\t(((x) & BIT_MASK_BT_POLLUTE_PKTCNT_8814B)                              \\\n\t << BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B)\n#define BITS_BT_POLLUTE_PKTCNT_8814B                                           \\\n\t(BIT_MASK_BT_POLLUTE_PKTCNT_8814B << BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B)\n#define BIT_CLEAR_BT_POLLUTE_PKTCNT_8814B(x)                                   \\\n\t((x) & (~BITS_BT_POLLUTE_PKTCNT_8814B))\n#define BIT_GET_BT_POLLUTE_PKTCNT_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B) &                          \\\n\t BIT_MASK_BT_POLLUTE_PKTCNT_8814B)\n#define BIT_SET_BT_POLLUTE_PKTCNT_8814B(x, v)                                  \\\n\t(BIT_CLEAR_BT_POLLUTE_PKTCNT_8814B(x) | BIT_BT_POLLUTE_PKTCNT_8814B(v))\n\n/* 2 REG_CPUMGQ_TIMER_CTRL2_8814B */\n\n#define BIT_SHIFT_TRI_HEAD_ADDR_8814B 16\n#define BIT_MASK_TRI_HEAD_ADDR_8814B 0xfff\n#define BIT_TRI_HEAD_ADDR_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TRI_HEAD_ADDR_8814B) << BIT_SHIFT_TRI_HEAD_ADDR_8814B)\n#define BITS_TRI_HEAD_ADDR_8814B                                               \\\n\t(BIT_MASK_TRI_HEAD_ADDR_8814B << BIT_SHIFT_TRI_HEAD_ADDR_8814B)\n#define BIT_CLEAR_TRI_HEAD_ADDR_8814B(x) ((x) & (~BITS_TRI_HEAD_ADDR_8814B))\n#define BIT_GET_TRI_HEAD_ADDR_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8814B) & BIT_MASK_TRI_HEAD_ADDR_8814B)\n#define BIT_SET_TRI_HEAD_ADDR_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TRI_HEAD_ADDR_8814B(x) | BIT_TRI_HEAD_ADDR_8814B(v))\n\n#define BIT_DROP_TH_EN_8814B BIT(8)\n\n#define BIT_SHIFT_DROP_TH_8814B 0\n#define BIT_MASK_DROP_TH_8814B 0xff\n#define BIT_DROP_TH_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_DROP_TH_8814B) << BIT_SHIFT_DROP_TH_8814B)\n#define BITS_DROP_TH_8814B (BIT_MASK_DROP_TH_8814B << BIT_SHIFT_DROP_TH_8814B)\n#define BIT_CLEAR_DROP_TH_8814B(x) ((x) & (~BITS_DROP_TH_8814B))\n#define BIT_GET_DROP_TH_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_DROP_TH_8814B) & BIT_MASK_DROP_TH_8814B)\n#define BIT_SET_DROP_TH_8814B(x, v)                                            \\\n\t(BIT_CLEAR_DROP_TH_8814B(x) | BIT_DROP_TH_8814B(v))\n\n/* 2 REG_PTCL_DBG_OUT_8814B */\n\n#define BIT_SHIFT_PTCL_DBG_OUT_8814B 0\n#define BIT_MASK_PTCL_DBG_OUT_8814B 0xffffffffL\n#define BIT_PTCL_DBG_OUT_8814B(x)                                              \\\n\t(((x) & BIT_MASK_PTCL_DBG_OUT_8814B) << BIT_SHIFT_PTCL_DBG_OUT_8814B)\n#define BITS_PTCL_DBG_OUT_8814B                                                \\\n\t(BIT_MASK_PTCL_DBG_OUT_8814B << BIT_SHIFT_PTCL_DBG_OUT_8814B)\n#define BIT_CLEAR_PTCL_DBG_OUT_8814B(x) ((x) & (~BITS_PTCL_DBG_OUT_8814B))\n#define BIT_GET_PTCL_DBG_OUT_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_PTCL_DBG_OUT_8814B) & BIT_MASK_PTCL_DBG_OUT_8814B)\n#define BIT_SET_PTCL_DBG_OUT_8814B(x, v)                                       \\\n\t(BIT_CLEAR_PTCL_DBG_OUT_8814B(x) | BIT_PTCL_DBG_OUT_8814B(v))\n\n/* 2 REG_DUMMY_PAGE4_V1_8814B */\n\n/* 2 REG_DUMMY_PAGE4_1_8814B */\n\n/* 2 REG_MU_OFFSET_8814B */\n\n#define BIT_SHIFT_MU_RATETABLE_OFFSET_8814B 16\n#define BIT_MASK_MU_RATETABLE_OFFSET_8814B 0x1ff\n#define BIT_MU_RATETABLE_OFFSET_8814B(x)                                       \\\n\t(((x) & BIT_MASK_MU_RATETABLE_OFFSET_8814B)                            \\\n\t << BIT_SHIFT_MU_RATETABLE_OFFSET_8814B)\n#define BITS_MU_RATETABLE_OFFSET_8814B                                         \\\n\t(BIT_MASK_MU_RATETABLE_OFFSET_8814B                                    \\\n\t << BIT_SHIFT_MU_RATETABLE_OFFSET_8814B)\n#define BIT_CLEAR_MU_RATETABLE_OFFSET_8814B(x)                                 \\\n\t((x) & (~BITS_MU_RATETABLE_OFFSET_8814B))\n#define BIT_GET_MU_RATETABLE_OFFSET_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_MU_RATETABLE_OFFSET_8814B) &                        \\\n\t BIT_MASK_MU_RATETABLE_OFFSET_8814B)\n#define BIT_SET_MU_RATETABLE_OFFSET_8814B(x, v)                                \\\n\t(BIT_CLEAR_MU_RATETABLE_OFFSET_8814B(x) |                              \\\n\t BIT_MU_RATETABLE_OFFSET_8814B(v))\n\n#define BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B 0\n#define BIT_MASK_MU_SCORETABLE_OFFSET_8814B 0x1ff\n#define BIT_MU_SCORETABLE_OFFSET_8814B(x)                                      \\\n\t(((x) & BIT_MASK_MU_SCORETABLE_OFFSET_8814B)                           \\\n\t << BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B)\n#define BITS_MU_SCORETABLE_OFFSET_8814B                                        \\\n\t(BIT_MASK_MU_SCORETABLE_OFFSET_8814B                                   \\\n\t << BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B)\n#define BIT_CLEAR_MU_SCORETABLE_OFFSET_8814B(x)                                \\\n\t((x) & (~BITS_MU_SCORETABLE_OFFSET_8814B))\n#define BIT_GET_MU_SCORETABLE_OFFSET_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B) &                       \\\n\t BIT_MASK_MU_SCORETABLE_OFFSET_8814B)\n#define BIT_SET_MU_SCORETABLE_OFFSET_8814B(x, v)                               \\\n\t(BIT_CLEAR_MU_SCORETABLE_OFFSET_8814B(x) |                             \\\n\t BIT_MU_SCORETABLE_OFFSET_8814B(v))\n\n/* 2 REG_BF0_TIME_SETTING_8814B */\n#define BIT_BF0_TIMER_SET_8814B BIT(31)\n#define BIT_BF0_TIMER_CLR_8814B BIT(30)\n#define BIT_BF0_UPDATE_EN_8814B BIT(29)\n#define BIT_BF0_TIMER_EN_8814B BIT(28)\n\n#define BIT_SHIFT_BF0_PRETIME_OVER_8814B 16\n#define BIT_MASK_BF0_PRETIME_OVER_8814B 0xfff\n#define BIT_BF0_PRETIME_OVER_8814B(x)                                          \\\n\t(((x) & BIT_MASK_BF0_PRETIME_OVER_8814B)                               \\\n\t << BIT_SHIFT_BF0_PRETIME_OVER_8814B)\n#define BITS_BF0_PRETIME_OVER_8814B                                            \\\n\t(BIT_MASK_BF0_PRETIME_OVER_8814B << BIT_SHIFT_BF0_PRETIME_OVER_8814B)\n#define BIT_CLEAR_BF0_PRETIME_OVER_8814B(x)                                    \\\n\t((x) & (~BITS_BF0_PRETIME_OVER_8814B))\n#define BIT_GET_BF0_PRETIME_OVER_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8814B) &                           \\\n\t BIT_MASK_BF0_PRETIME_OVER_8814B)\n#define BIT_SET_BF0_PRETIME_OVER_8814B(x, v)                                   \\\n\t(BIT_CLEAR_BF0_PRETIME_OVER_8814B(x) | BIT_BF0_PRETIME_OVER_8814B(v))\n\n#define BIT_SHIFT_BF0_LIFETIME_8814B 0\n#define BIT_MASK_BF0_LIFETIME_8814B 0xffff\n#define BIT_BF0_LIFETIME_8814B(x)                                              \\\n\t(((x) & BIT_MASK_BF0_LIFETIME_8814B) << BIT_SHIFT_BF0_LIFETIME_8814B)\n#define BITS_BF0_LIFETIME_8814B                                                \\\n\t(BIT_MASK_BF0_LIFETIME_8814B << BIT_SHIFT_BF0_LIFETIME_8814B)\n#define BIT_CLEAR_BF0_LIFETIME_8814B(x) ((x) & (~BITS_BF0_LIFETIME_8814B))\n#define BIT_GET_BF0_LIFETIME_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BF0_LIFETIME_8814B) & BIT_MASK_BF0_LIFETIME_8814B)\n#define BIT_SET_BF0_LIFETIME_8814B(x, v)                                       \\\n\t(BIT_CLEAR_BF0_LIFETIME_8814B(x) | BIT_BF0_LIFETIME_8814B(v))\n\n/* 2 REG_BF1_TIME_SETTING_8814B */\n#define BIT_BF1_TIMER_SET_8814B BIT(31)\n#define BIT_BF1_TIMER_CLR_8814B BIT(30)\n#define BIT_BF1_UPDATE_EN_8814B BIT(29)\n#define BIT_BF1_TIMER_EN_8814B BIT(28)\n\n#define BIT_SHIFT_BF1_PRETIME_OVER_8814B 16\n#define BIT_MASK_BF1_PRETIME_OVER_8814B 0xfff\n#define BIT_BF1_PRETIME_OVER_8814B(x)                                          \\\n\t(((x) & BIT_MASK_BF1_PRETIME_OVER_8814B)                               \\\n\t << BIT_SHIFT_BF1_PRETIME_OVER_8814B)\n#define BITS_BF1_PRETIME_OVER_8814B                                            \\\n\t(BIT_MASK_BF1_PRETIME_OVER_8814B << BIT_SHIFT_BF1_PRETIME_OVER_8814B)\n#define BIT_CLEAR_BF1_PRETIME_OVER_8814B(x)                                    \\\n\t((x) & (~BITS_BF1_PRETIME_OVER_8814B))\n#define BIT_GET_BF1_PRETIME_OVER_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8814B) &                           \\\n\t BIT_MASK_BF1_PRETIME_OVER_8814B)\n#define BIT_SET_BF1_PRETIME_OVER_8814B(x, v)                                   \\\n\t(BIT_CLEAR_BF1_PRETIME_OVER_8814B(x) | BIT_BF1_PRETIME_OVER_8814B(v))\n\n#define BIT_SHIFT_BF1_LIFETIME_8814B 0\n#define BIT_MASK_BF1_LIFETIME_8814B 0xffff\n#define BIT_BF1_LIFETIME_8814B(x)                                              \\\n\t(((x) & BIT_MASK_BF1_LIFETIME_8814B) << BIT_SHIFT_BF1_LIFETIME_8814B)\n#define BITS_BF1_LIFETIME_8814B                                                \\\n\t(BIT_MASK_BF1_LIFETIME_8814B << BIT_SHIFT_BF1_LIFETIME_8814B)\n#define BIT_CLEAR_BF1_LIFETIME_8814B(x) ((x) & (~BITS_BF1_LIFETIME_8814B))\n#define BIT_GET_BF1_LIFETIME_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BF1_LIFETIME_8814B) & BIT_MASK_BF1_LIFETIME_8814B)\n#define BIT_SET_BF1_LIFETIME_8814B(x, v)                                       \\\n\t(BIT_CLEAR_BF1_LIFETIME_8814B(x) | BIT_BF1_LIFETIME_8814B(v))\n\n/* 2 REG_BF_TIMEOUT_EN_8814B */\n#define BIT_EN_VHT_LDPC_8814B BIT(9)\n#define BIT_EN_HT_LDPC_8814B BIT(8)\n#define BIT_BF1_TIMEOUT_EN_8814B BIT(1)\n#define BIT_BF0_TIMEOUT_EN_8814B BIT(0)\n\n/* 2 REG_MACID_RELEASE_INFO_8814B */\n\n#define BIT_SHIFT_MACID_RELEASE_INFO_8814B 0\n#define BIT_MASK_MACID_RELEASE_INFO_8814B 0xffffffffL\n#define BIT_MACID_RELEASE_INFO_8814B(x)                                        \\\n\t(((x) & BIT_MASK_MACID_RELEASE_INFO_8814B)                             \\\n\t << BIT_SHIFT_MACID_RELEASE_INFO_8814B)\n#define BITS_MACID_RELEASE_INFO_8814B                                          \\\n\t(BIT_MASK_MACID_RELEASE_INFO_8814B                                     \\\n\t << BIT_SHIFT_MACID_RELEASE_INFO_8814B)\n#define BIT_CLEAR_MACID_RELEASE_INFO_8814B(x)                                  \\\n\t((x) & (~BITS_MACID_RELEASE_INFO_8814B))\n#define BIT_GET_MACID_RELEASE_INFO_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACID_RELEASE_INFO_8814B) &                         \\\n\t BIT_MASK_MACID_RELEASE_INFO_8814B)\n#define BIT_SET_MACID_RELEASE_INFO_8814B(x, v)                                 \\\n\t(BIT_CLEAR_MACID_RELEASE_INFO_8814B(x) |                               \\\n\t BIT_MACID_RELEASE_INFO_8814B(v))\n\n/* 2 REG_MACID_RELEASE_SUCCESS_INFO_8814B */\n\n#define BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B 0\n#define BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B 0xffffffffL\n#define BIT_MACID_RELEASE_SUCCESS_INFO_8814B(x)                                \\\n\t(((x) & BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B)                     \\\n\t << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B)\n#define BITS_MACID_RELEASE_SUCCESS_INFO_8814B                                  \\\n\t(BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B                             \\\n\t << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B)\n#define BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO_8814B(x)                          \\\n\t((x) & (~BITS_MACID_RELEASE_SUCCESS_INFO_8814B))\n#define BIT_GET_MACID_RELEASE_SUCCESS_INFO_8814B(x)                            \\\n\t(((x) >> BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B) &                 \\\n\t BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B)\n#define BIT_SET_MACID_RELEASE_SUCCESS_INFO_8814B(x, v)                         \\\n\t(BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO_8814B(x) |                       \\\n\t BIT_MACID_RELEASE_SUCCESS_INFO_8814B(v))\n\n/* 2 REG_MACID_RELEASE_CTRL_8814B */\n\n#define BIT_SHIFT_MACID_RELEASE_SEL_8814B 24\n#define BIT_MASK_MACID_RELEASE_SEL_8814B 0x7\n#define BIT_MACID_RELEASE_SEL_8814B(x)                                         \\\n\t(((x) & BIT_MASK_MACID_RELEASE_SEL_8814B)                              \\\n\t << BIT_SHIFT_MACID_RELEASE_SEL_8814B)\n#define BITS_MACID_RELEASE_SEL_8814B                                           \\\n\t(BIT_MASK_MACID_RELEASE_SEL_8814B << BIT_SHIFT_MACID_RELEASE_SEL_8814B)\n#define BIT_CLEAR_MACID_RELEASE_SEL_8814B(x)                                   \\\n\t((x) & (~BITS_MACID_RELEASE_SEL_8814B))\n#define BIT_GET_MACID_RELEASE_SEL_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_MACID_RELEASE_SEL_8814B) &                          \\\n\t BIT_MASK_MACID_RELEASE_SEL_8814B)\n#define BIT_SET_MACID_RELEASE_SEL_8814B(x, v)                                  \\\n\t(BIT_CLEAR_MACID_RELEASE_SEL_8814B(x) | BIT_MACID_RELEASE_SEL_8814B(v))\n\n#define BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B 16\n#define BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B 0xff\n#define BIT_MACID_RELEASE_CLEAR_OFFSET_8814B(x)                                \\\n\t(((x) & BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B)                     \\\n\t << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B)\n#define BITS_MACID_RELEASE_CLEAR_OFFSET_8814B                                  \\\n\t(BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B                             \\\n\t << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B)\n#define BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET_8814B(x)                          \\\n\t((x) & (~BITS_MACID_RELEASE_CLEAR_OFFSET_8814B))\n#define BIT_GET_MACID_RELEASE_CLEAR_OFFSET_8814B(x)                            \\\n\t(((x) >> BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B) &                 \\\n\t BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B)\n#define BIT_SET_MACID_RELEASE_CLEAR_OFFSET_8814B(x, v)                         \\\n\t(BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET_8814B(x) |                       \\\n\t BIT_MACID_RELEASE_CLEAR_OFFSET_8814B(v))\n\n#define BIT_MACID_RELEASE_VALUE_8814B BIT(8)\n\n#define BIT_SHIFT_MACID_RELEASE_OFFSET_8814B 0\n#define BIT_MASK_MACID_RELEASE_OFFSET_8814B 0xff\n#define BIT_MACID_RELEASE_OFFSET_8814B(x)                                      \\\n\t(((x) & BIT_MASK_MACID_RELEASE_OFFSET_8814B)                           \\\n\t << BIT_SHIFT_MACID_RELEASE_OFFSET_8814B)\n#define BITS_MACID_RELEASE_OFFSET_8814B                                        \\\n\t(BIT_MASK_MACID_RELEASE_OFFSET_8814B                                   \\\n\t << BIT_SHIFT_MACID_RELEASE_OFFSET_8814B)\n#define BIT_CLEAR_MACID_RELEASE_OFFSET_8814B(x)                                \\\n\t((x) & (~BITS_MACID_RELEASE_OFFSET_8814B))\n#define BIT_GET_MACID_RELEASE_OFFSET_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_MACID_RELEASE_OFFSET_8814B) &                       \\\n\t BIT_MASK_MACID_RELEASE_OFFSET_8814B)\n#define BIT_SET_MACID_RELEASE_OFFSET_8814B(x, v)                               \\\n\t(BIT_CLEAR_MACID_RELEASE_OFFSET_8814B(x) |                             \\\n\t BIT_MACID_RELEASE_OFFSET_8814B(v))\n\n/* 2 REG_FAST_EDCA_VOVI_SETTING_8814B */\n\n#define BIT_SHIFT_VI_FAST_EDCA_TO_8814B 24\n#define BIT_MASK_VI_FAST_EDCA_TO_8814B 0xff\n#define BIT_VI_FAST_EDCA_TO_8814B(x)                                           \\\n\t(((x) & BIT_MASK_VI_FAST_EDCA_TO_8814B)                                \\\n\t << BIT_SHIFT_VI_FAST_EDCA_TO_8814B)\n#define BITS_VI_FAST_EDCA_TO_8814B                                             \\\n\t(BIT_MASK_VI_FAST_EDCA_TO_8814B << BIT_SHIFT_VI_FAST_EDCA_TO_8814B)\n#define BIT_CLEAR_VI_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8814B))\n#define BIT_GET_VI_FAST_EDCA_TO_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8814B) &                            \\\n\t BIT_MASK_VI_FAST_EDCA_TO_8814B)\n#define BIT_SET_VI_FAST_EDCA_TO_8814B(x, v)                                    \\\n\t(BIT_CLEAR_VI_FAST_EDCA_TO_8814B(x) | BIT_VI_FAST_EDCA_TO_8814B(v))\n\n#define BIT_VI_THRESHOLD_SEL_8814B BIT(23)\n\n#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B 16\n#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B 0x7f\n#define BIT_VI_FAST_EDCA_PKT_TH_8814B(x)                                       \\\n\t(((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B)                            \\\n\t << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B)\n#define BITS_VI_FAST_EDCA_PKT_TH_8814B                                         \\\n\t(BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B                                    \\\n\t << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B)\n#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8814B(x)                                 \\\n\t((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8814B))\n#define BIT_GET_VI_FAST_EDCA_PKT_TH_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B) &                        \\\n\t BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B)\n#define BIT_SET_VI_FAST_EDCA_PKT_TH_8814B(x, v)                                \\\n\t(BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8814B(x) |                              \\\n\t BIT_VI_FAST_EDCA_PKT_TH_8814B(v))\n\n#define BIT_SHIFT_VO_FAST_EDCA_TO_8814B 8\n#define BIT_MASK_VO_FAST_EDCA_TO_8814B 0xff\n#define BIT_VO_FAST_EDCA_TO_8814B(x)                                           \\\n\t(((x) & BIT_MASK_VO_FAST_EDCA_TO_8814B)                                \\\n\t << BIT_SHIFT_VO_FAST_EDCA_TO_8814B)\n#define BITS_VO_FAST_EDCA_TO_8814B                                             \\\n\t(BIT_MASK_VO_FAST_EDCA_TO_8814B << BIT_SHIFT_VO_FAST_EDCA_TO_8814B)\n#define BIT_CLEAR_VO_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8814B))\n#define BIT_GET_VO_FAST_EDCA_TO_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8814B) &                            \\\n\t BIT_MASK_VO_FAST_EDCA_TO_8814B)\n#define BIT_SET_VO_FAST_EDCA_TO_8814B(x, v)                                    \\\n\t(BIT_CLEAR_VO_FAST_EDCA_TO_8814B(x) | BIT_VO_FAST_EDCA_TO_8814B(v))\n\n#define BIT_VO_THRESHOLD_SEL_8814B BIT(7)\n\n#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B 0\n#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B 0x7f\n#define BIT_VO_FAST_EDCA_PKT_TH_8814B(x)                                       \\\n\t(((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B)                            \\\n\t << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B)\n#define BITS_VO_FAST_EDCA_PKT_TH_8814B                                         \\\n\t(BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B                                    \\\n\t << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B)\n#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8814B(x)                                 \\\n\t((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8814B))\n#define BIT_GET_VO_FAST_EDCA_PKT_TH_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B) &                        \\\n\t BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B)\n#define BIT_SET_VO_FAST_EDCA_PKT_TH_8814B(x, v)                                \\\n\t(BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8814B(x) |                              \\\n\t BIT_VO_FAST_EDCA_PKT_TH_8814B(v))\n\n/* 2 REG_FAST_EDCA_BEBK_SETTING_8814B */\n\n#define BIT_SHIFT_BK_FAST_EDCA_TO_8814B 24\n#define BIT_MASK_BK_FAST_EDCA_TO_8814B 0xff\n#define BIT_BK_FAST_EDCA_TO_8814B(x)                                           \\\n\t(((x) & BIT_MASK_BK_FAST_EDCA_TO_8814B)                                \\\n\t << BIT_SHIFT_BK_FAST_EDCA_TO_8814B)\n#define BITS_BK_FAST_EDCA_TO_8814B                                             \\\n\t(BIT_MASK_BK_FAST_EDCA_TO_8814B << BIT_SHIFT_BK_FAST_EDCA_TO_8814B)\n#define BIT_CLEAR_BK_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8814B))\n#define BIT_GET_BK_FAST_EDCA_TO_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8814B) &                            \\\n\t BIT_MASK_BK_FAST_EDCA_TO_8814B)\n#define BIT_SET_BK_FAST_EDCA_TO_8814B(x, v)                                    \\\n\t(BIT_CLEAR_BK_FAST_EDCA_TO_8814B(x) | BIT_BK_FAST_EDCA_TO_8814B(v))\n\n#define BIT_BK_THRESHOLD_SEL_8814B BIT(23)\n\n#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B 16\n#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B 0x7f\n#define BIT_BK_FAST_EDCA_PKT_TH_8814B(x)                                       \\\n\t(((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B)                            \\\n\t << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B)\n#define BITS_BK_FAST_EDCA_PKT_TH_8814B                                         \\\n\t(BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B                                    \\\n\t << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B)\n#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8814B(x)                                 \\\n\t((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8814B))\n#define BIT_GET_BK_FAST_EDCA_PKT_TH_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B) &                        \\\n\t BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B)\n#define BIT_SET_BK_FAST_EDCA_PKT_TH_8814B(x, v)                                \\\n\t(BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8814B(x) |                              \\\n\t BIT_BK_FAST_EDCA_PKT_TH_8814B(v))\n\n#define BIT_SHIFT_BE_FAST_EDCA_TO_8814B 8\n#define BIT_MASK_BE_FAST_EDCA_TO_8814B 0xff\n#define BIT_BE_FAST_EDCA_TO_8814B(x)                                           \\\n\t(((x) & BIT_MASK_BE_FAST_EDCA_TO_8814B)                                \\\n\t << BIT_SHIFT_BE_FAST_EDCA_TO_8814B)\n#define BITS_BE_FAST_EDCA_TO_8814B                                             \\\n\t(BIT_MASK_BE_FAST_EDCA_TO_8814B << BIT_SHIFT_BE_FAST_EDCA_TO_8814B)\n#define BIT_CLEAR_BE_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8814B))\n#define BIT_GET_BE_FAST_EDCA_TO_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8814B) &                            \\\n\t BIT_MASK_BE_FAST_EDCA_TO_8814B)\n#define BIT_SET_BE_FAST_EDCA_TO_8814B(x, v)                                    \\\n\t(BIT_CLEAR_BE_FAST_EDCA_TO_8814B(x) | BIT_BE_FAST_EDCA_TO_8814B(v))\n\n#define BIT_BE_THRESHOLD_SEL_8814B BIT(7)\n\n#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B 0\n#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B 0x7f\n#define BIT_BE_FAST_EDCA_PKT_TH_8814B(x)                                       \\\n\t(((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B)                            \\\n\t << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B)\n#define BITS_BE_FAST_EDCA_PKT_TH_8814B                                         \\\n\t(BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B                                    \\\n\t << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B)\n#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8814B(x)                                 \\\n\t((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8814B))\n#define BIT_GET_BE_FAST_EDCA_PKT_TH_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B) &                        \\\n\t BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B)\n#define BIT_SET_BE_FAST_EDCA_PKT_TH_8814B(x, v)                                \\\n\t(BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8814B(x) |                              \\\n\t BIT_BE_FAST_EDCA_PKT_TH_8814B(v))\n\n/* 2 REG_MACID_DROP_INFO_8814B */\n\n#define BIT_SHIFT_MACID_DROP_INFO_8814B 0\n#define BIT_MASK_MACID_DROP_INFO_8814B 0xffffffffL\n#define BIT_MACID_DROP_INFO_8814B(x)                                           \\\n\t(((x) & BIT_MASK_MACID_DROP_INFO_8814B)                                \\\n\t << BIT_SHIFT_MACID_DROP_INFO_8814B)\n#define BITS_MACID_DROP_INFO_8814B                                             \\\n\t(BIT_MASK_MACID_DROP_INFO_8814B << BIT_SHIFT_MACID_DROP_INFO_8814B)\n#define BIT_CLEAR_MACID_DROP_INFO_8814B(x) ((x) & (~BITS_MACID_DROP_INFO_8814B))\n#define BIT_GET_MACID_DROP_INFO_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_MACID_DROP_INFO_8814B) &                            \\\n\t BIT_MASK_MACID_DROP_INFO_8814B)\n#define BIT_SET_MACID_DROP_INFO_8814B(x, v)                                    \\\n\t(BIT_CLEAR_MACID_DROP_INFO_8814B(x) | BIT_MACID_DROP_INFO_8814B(v))\n\n/* 2 REG_MACID_DROP_CTRL_8814B */\n\n#define BIT_SHIFT_MACID_DROP_SEL_8814B 0\n#define BIT_MASK_MACID_DROP_SEL_8814B 0x7\n#define BIT_MACID_DROP_SEL_8814B(x)                                            \\\n\t(((x) & BIT_MASK_MACID_DROP_SEL_8814B)                                 \\\n\t << BIT_SHIFT_MACID_DROP_SEL_8814B)\n#define BITS_MACID_DROP_SEL_8814B                                              \\\n\t(BIT_MASK_MACID_DROP_SEL_8814B << BIT_SHIFT_MACID_DROP_SEL_8814B)\n#define BIT_CLEAR_MACID_DROP_SEL_8814B(x) ((x) & (~BITS_MACID_DROP_SEL_8814B))\n#define BIT_GET_MACID_DROP_SEL_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_MACID_DROP_SEL_8814B) &                             \\\n\t BIT_MASK_MACID_DROP_SEL_8814B)\n#define BIT_SET_MACID_DROP_SEL_8814B(x, v)                                     \\\n\t(BIT_CLEAR_MACID_DROP_SEL_8814B(x) | BIT_MACID_DROP_SEL_8814B(v))\n\n/* 2 REG_MGQ_FIFO_WRITE_POINTER_8814B */\n#define BIT_MGQ_FIFO_OV_8814B BIT(7)\n#define BIT_MGQ_FIFO_WPTR_ERROR_8814B BIT(6)\n#define BIT_EN_MGQ_FIFO_LIFETIME_8814B BIT(5)\n\n#define BIT_SHIFT_MGQ_FIFO_WPTR_8814B 0\n#define BIT_MASK_MGQ_FIFO_WPTR_8814B 0x1f\n#define BIT_MGQ_FIFO_WPTR_8814B(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_FIFO_WPTR_8814B) << BIT_SHIFT_MGQ_FIFO_WPTR_8814B)\n#define BITS_MGQ_FIFO_WPTR_8814B                                               \\\n\t(BIT_MASK_MGQ_FIFO_WPTR_8814B << BIT_SHIFT_MGQ_FIFO_WPTR_8814B)\n#define BIT_CLEAR_MGQ_FIFO_WPTR_8814B(x) ((x) & (~BITS_MGQ_FIFO_WPTR_8814B))\n#define BIT_GET_MGQ_FIFO_WPTR_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_WPTR_8814B) & BIT_MASK_MGQ_FIFO_WPTR_8814B)\n#define BIT_SET_MGQ_FIFO_WPTR_8814B(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_FIFO_WPTR_8814B(x) | BIT_MGQ_FIFO_WPTR_8814B(v))\n\n/* 2 REG_MGQ_FIFO_READ_POINTER_8814B */\n\n#define BIT_SHIFT_MGQ_FIFO_SIZE_8814B 14\n#define BIT_MASK_MGQ_FIFO_SIZE_8814B 0x3\n#define BIT_MGQ_FIFO_SIZE_8814B(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_FIFO_SIZE_8814B) << BIT_SHIFT_MGQ_FIFO_SIZE_8814B)\n#define BITS_MGQ_FIFO_SIZE_8814B                                               \\\n\t(BIT_MASK_MGQ_FIFO_SIZE_8814B << BIT_SHIFT_MGQ_FIFO_SIZE_8814B)\n#define BIT_CLEAR_MGQ_FIFO_SIZE_8814B(x) ((x) & (~BITS_MGQ_FIFO_SIZE_8814B))\n#define BIT_GET_MGQ_FIFO_SIZE_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_SIZE_8814B) & BIT_MASK_MGQ_FIFO_SIZE_8814B)\n#define BIT_SET_MGQ_FIFO_SIZE_8814B(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_FIFO_SIZE_8814B(x) | BIT_MGQ_FIFO_SIZE_8814B(v))\n\n#define BIT_MGQ_FIFO_PAUSE_8814B BIT(13)\n\n#define BIT_SHIFT_MGQ_FIFO_RPTR_8814B 8\n#define BIT_MASK_MGQ_FIFO_RPTR_8814B 0x1f\n#define BIT_MGQ_FIFO_RPTR_8814B(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_FIFO_RPTR_8814B) << BIT_SHIFT_MGQ_FIFO_RPTR_8814B)\n#define BITS_MGQ_FIFO_RPTR_8814B                                               \\\n\t(BIT_MASK_MGQ_FIFO_RPTR_8814B << BIT_SHIFT_MGQ_FIFO_RPTR_8814B)\n#define BIT_CLEAR_MGQ_FIFO_RPTR_8814B(x) ((x) & (~BITS_MGQ_FIFO_RPTR_8814B))\n#define BIT_GET_MGQ_FIFO_RPTR_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_RPTR_8814B) & BIT_MASK_MGQ_FIFO_RPTR_8814B)\n#define BIT_SET_MGQ_FIFO_RPTR_8814B(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_FIFO_RPTR_8814B(x) | BIT_MGQ_FIFO_RPTR_8814B(v))\n\n/* 2 REG_MGQ_FIFO_ENABLE_8814B */\n#define BIT_MGQ_FIFO_EN_V1_8814B BIT(15)\n\n#define BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B 12\n#define BIT_MASK_MGQ_FIFO_PG_SIZE_8814B 0x7\n#define BIT_MGQ_FIFO_PG_SIZE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_MGQ_FIFO_PG_SIZE_8814B)                               \\\n\t << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B)\n#define BITS_MGQ_FIFO_PG_SIZE_8814B                                            \\\n\t(BIT_MASK_MGQ_FIFO_PG_SIZE_8814B << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B)\n#define BIT_CLEAR_MGQ_FIFO_PG_SIZE_8814B(x)                                    \\\n\t((x) & (~BITS_MGQ_FIFO_PG_SIZE_8814B))\n#define BIT_GET_MGQ_FIFO_PG_SIZE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B) &                           \\\n\t BIT_MASK_MGQ_FIFO_PG_SIZE_8814B)\n#define BIT_SET_MGQ_FIFO_PG_SIZE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_MGQ_FIFO_PG_SIZE_8814B(x) | BIT_MGQ_FIFO_PG_SIZE_8814B(v))\n\n#define BIT_SHIFT_MGQ_FIFO_START_PG_8814B 0\n#define BIT_MASK_MGQ_FIFO_START_PG_8814B 0xfff\n#define BIT_MGQ_FIFO_START_PG_8814B(x)                                         \\\n\t(((x) & BIT_MASK_MGQ_FIFO_START_PG_8814B)                              \\\n\t << BIT_SHIFT_MGQ_FIFO_START_PG_8814B)\n#define BITS_MGQ_FIFO_START_PG_8814B                                           \\\n\t(BIT_MASK_MGQ_FIFO_START_PG_8814B << BIT_SHIFT_MGQ_FIFO_START_PG_8814B)\n#define BIT_CLEAR_MGQ_FIFO_START_PG_8814B(x)                                   \\\n\t((x) & (~BITS_MGQ_FIFO_START_PG_8814B))\n#define BIT_GET_MGQ_FIFO_START_PG_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_START_PG_8814B) &                          \\\n\t BIT_MASK_MGQ_FIFO_START_PG_8814B)\n#define BIT_SET_MGQ_FIFO_START_PG_8814B(x, v)                                  \\\n\t(BIT_CLEAR_MGQ_FIFO_START_PG_8814B(x) | BIT_MGQ_FIFO_START_PG_8814B(v))\n\n/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK_8814B */\n\n#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B 0\n#define BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B 0xffff\n#define BIT_MGQ_FIFO_REL_INT_MASK_8814B(x)                                     \\\n\t(((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B)                          \\\n\t << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B)\n#define BITS_MGQ_FIFO_REL_INT_MASK_8814B                                       \\\n\t(BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B                                  \\\n\t << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B)\n#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8814B(x)                               \\\n\t((x) & (~BITS_MGQ_FIFO_REL_INT_MASK_8814B))\n#define BIT_GET_MGQ_FIFO_REL_INT_MASK_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B) &                      \\\n\t BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B)\n#define BIT_SET_MGQ_FIFO_REL_INT_MASK_8814B(x, v)                              \\\n\t(BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8814B(x) |                            \\\n\t BIT_MGQ_FIFO_REL_INT_MASK_8814B(v))\n\n/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG_8814B */\n\n#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B 0\n#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B 0xffff\n#define BIT_MGQ_FIFO_REL_INT_FLAG_8814B(x)                                     \\\n\t(((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B)                          \\\n\t << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B)\n#define BITS_MGQ_FIFO_REL_INT_FLAG_8814B                                       \\\n\t(BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B                                  \\\n\t << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B)\n#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8814B(x)                               \\\n\t((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG_8814B))\n#define BIT_GET_MGQ_FIFO_REL_INT_FLAG_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B) &                      \\\n\t BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B)\n#define BIT_SET_MGQ_FIFO_REL_INT_FLAG_8814B(x, v)                              \\\n\t(BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8814B(x) |                            \\\n\t BIT_MGQ_FIFO_REL_INT_FLAG_8814B(v))\n\n/* 2 REG_MGQ_FIFO_VALID_MAP_8814B */\n\n#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B 0\n#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B 0xffff\n#define BIT_MGQ_FIFO_PKT_VALID_MAP_8814B(x)                                    \\\n\t(((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B)                         \\\n\t << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B)\n#define BITS_MGQ_FIFO_PKT_VALID_MAP_8814B                                      \\\n\t(BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B                                 \\\n\t << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B)\n#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8814B(x)                              \\\n\t((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP_8814B))\n#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP_8814B(x)                                \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B) &                     \\\n\t BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B)\n#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP_8814B(x, v)                             \\\n\t(BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8814B(x) |                           \\\n\t BIT_MGQ_FIFO_PKT_VALID_MAP_8814B(v))\n\n/* 2 REG_MGQ_FIFO_LIFETIME_8814B */\n\n#define BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B 0\n#define BIT_MASK_MGQ_FIFO_LIFETIME_8814B 0xffff\n#define BIT_MGQ_FIFO_LIFETIME_8814B(x)                                         \\\n\t(((x) & BIT_MASK_MGQ_FIFO_LIFETIME_8814B)                              \\\n\t << BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B)\n#define BITS_MGQ_FIFO_LIFETIME_8814B                                           \\\n\t(BIT_MASK_MGQ_FIFO_LIFETIME_8814B << BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B)\n#define BIT_CLEAR_MGQ_FIFO_LIFETIME_8814B(x)                                   \\\n\t((x) & (~BITS_MGQ_FIFO_LIFETIME_8814B))\n#define BIT_GET_MGQ_FIFO_LIFETIME_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B) &                          \\\n\t BIT_MASK_MGQ_FIFO_LIFETIME_8814B)\n#define BIT_SET_MGQ_FIFO_LIFETIME_8814B(x, v)                                  \\\n\t(BIT_CLEAR_MGQ_FIFO_LIFETIME_8814B(x) | BIT_MGQ_FIFO_LIFETIME_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_PKT_TRANS_8814B */\n\n#define BIT_SHIFT_IE_DESC_OFFSET_8814B 16\n#define BIT_MASK_IE_DESC_OFFSET_8814B 0x1ff\n#define BIT_IE_DESC_OFFSET_8814B(x)                                            \\\n\t(((x) & BIT_MASK_IE_DESC_OFFSET_8814B)                                 \\\n\t << BIT_SHIFT_IE_DESC_OFFSET_8814B)\n#define BITS_IE_DESC_OFFSET_8814B                                              \\\n\t(BIT_MASK_IE_DESC_OFFSET_8814B << BIT_SHIFT_IE_DESC_OFFSET_8814B)\n#define BIT_CLEAR_IE_DESC_OFFSET_8814B(x) ((x) & (~BITS_IE_DESC_OFFSET_8814B))\n#define BIT_GET_IE_DESC_OFFSET_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_IE_DESC_OFFSET_8814B) &                             \\\n\t BIT_MASK_IE_DESC_OFFSET_8814B)\n#define BIT_SET_IE_DESC_OFFSET_8814B(x, v)                                     \\\n\t(BIT_CLEAR_IE_DESC_OFFSET_8814B(x) | BIT_IE_DESC_OFFSET_8814B(v))\n\n#define BIT_DIS_FWCMD_PATH_ERRCHK_8814B BIT(13)\n#define BIT_MAC_HDR_CONVERT_EN_8814B BIT(12)\n#define BIT_TXDESC_TRANS_EN_8814B BIT(8)\n#define BIT_PKT_TRANS_ERRINT_EN_8814B BIT(7)\n\n#define BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B 4\n#define BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B 0x3\n#define BIT_PKT_TRANS_ERR_MACID_SEL_8814B(x)                                   \\\n\t(((x) & BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B)                        \\\n\t << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B)\n#define BITS_PKT_TRANS_ERR_MACID_SEL_8814B                                     \\\n\t(BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B                                \\\n\t << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B)\n#define BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL_8814B(x)                             \\\n\t((x) & (~BITS_PKT_TRANS_ERR_MACID_SEL_8814B))\n#define BIT_GET_PKT_TRANS_ERR_MACID_SEL_8814B(x)                               \\\n\t(((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B) &                    \\\n\t BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B)\n#define BIT_SET_PKT_TRANS_ERR_MACID_SEL_8814B(x, v)                            \\\n\t(BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL_8814B(x) |                          \\\n\t BIT_PKT_TRANS_ERR_MACID_SEL_8814B(v))\n\n#define BIT_PKT_TRANS_IEINIT_ERR_8814B BIT(3)\n#define BIT_PKT_TRANS_IENUM_ERR_8814B BIT(2)\n#define BIT_PKT_TRANS_IECNT_ERR1_8814B BIT(1)\n#define BIT_PKT_TRANS_IECNT_ERR0_8814B BIT(0)\n\n/* 2 REG_SHCUT_LLC_ETH_TYPE0_8814B */\n\n/* 2 REG_SHCUT_LLC_ETH_TYPE1_8814B */\n\n#define BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B 16\n#define BIT_MASK_SHCUT_MHDR_OFFSET_8814B 0x1ff\n#define BIT_SHCUT_MHDR_OFFSET_8814B(x)                                         \\\n\t(((x) & BIT_MASK_SHCUT_MHDR_OFFSET_8814B)                              \\\n\t << BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B)\n#define BITS_SHCUT_MHDR_OFFSET_8814B                                           \\\n\t(BIT_MASK_SHCUT_MHDR_OFFSET_8814B << BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B)\n#define BIT_CLEAR_SHCUT_MHDR_OFFSET_8814B(x)                                   \\\n\t((x) & (~BITS_SHCUT_MHDR_OFFSET_8814B))\n#define BIT_GET_SHCUT_MHDR_OFFSET_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B) &                          \\\n\t BIT_MASK_SHCUT_MHDR_OFFSET_8814B)\n#define BIT_SET_SHCUT_MHDR_OFFSET_8814B(x, v)                                  \\\n\t(BIT_CLEAR_SHCUT_MHDR_OFFSET_8814B(x) | BIT_SHCUT_MHDR_OFFSET_8814B(v))\n\n/* 2 REG_SHCUT_LLC_OUI0_8814B */\n\n/* 2 REG_SHCUT_LLC_OUI1_8814B */\n\n/* 2 REG_SHCUT_LLC_OUI2_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B 0\n#define BIT_MASK_PKT_TRANS_ERR_MACID_8814B 0xffffffffL\n#define BIT_PKT_TRANS_ERR_MACID_8814B(x)                                       \\\n\t(((x) & BIT_MASK_PKT_TRANS_ERR_MACID_8814B)                            \\\n\t << BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B)\n#define BITS_PKT_TRANS_ERR_MACID_8814B                                         \\\n\t(BIT_MASK_PKT_TRANS_ERR_MACID_8814B                                    \\\n\t << BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B)\n#define BIT_CLEAR_PKT_TRANS_ERR_MACID_8814B(x)                                 \\\n\t((x) & (~BITS_PKT_TRANS_ERR_MACID_8814B))\n#define BIT_GET_PKT_TRANS_ERR_MACID_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B) &                        \\\n\t BIT_MASK_PKT_TRANS_ERR_MACID_8814B)\n#define BIT_SET_PKT_TRANS_ERR_MACID_8814B(x, v)                                \\\n\t(BIT_CLEAR_PKT_TRANS_ERR_MACID_8814B(x) |                              \\\n\t BIT_PKT_TRANS_ERR_MACID_8814B(v))\n\n/* 2 REG_FWCMDQ_CTRL_8814B */\n#define BIT_FW_RELEASEPKT_POLLING_8814B BIT(31)\n\n#define BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B 16\n#define BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B 0xfff\n#define BIT_FWCMDQ_RELEASE_HEAD_8814B(x)                                       \\\n\t(((x) & BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B)                            \\\n\t << BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B)\n#define BITS_FWCMDQ_RELEASE_HEAD_8814B                                         \\\n\t(BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B                                    \\\n\t << BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B)\n#define BIT_CLEAR_FWCMDQ_RELEASE_HEAD_8814B(x)                                 \\\n\t((x) & (~BITS_FWCMDQ_RELEASE_HEAD_8814B))\n#define BIT_GET_FWCMDQ_RELEASE_HEAD_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B) &                        \\\n\t BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B)\n#define BIT_SET_FWCMDQ_RELEASE_HEAD_8814B(x, v)                                \\\n\t(BIT_CLEAR_FWCMDQ_RELEASE_HEAD_8814B(x) |                              \\\n\t BIT_FWCMDQ_RELEASE_HEAD_8814B(v))\n\n#define BIT_FW_GETPKTT_POLLING_8814B BIT(15)\n\n#define BIT_SHIFT_FWCMDQ_H_8814B 0\n#define BIT_MASK_FWCMDQ_H_8814B 0xfff\n#define BIT_FWCMDQ_H_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_FWCMDQ_H_8814B) << BIT_SHIFT_FWCMDQ_H_8814B)\n#define BITS_FWCMDQ_H_8814B                                                    \\\n\t(BIT_MASK_FWCMDQ_H_8814B << BIT_SHIFT_FWCMDQ_H_8814B)\n#define BIT_CLEAR_FWCMDQ_H_8814B(x) ((x) & (~BITS_FWCMDQ_H_8814B))\n#define BIT_GET_FWCMDQ_H_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_H_8814B) & BIT_MASK_FWCMDQ_H_8814B)\n#define BIT_SET_FWCMDQ_H_8814B(x, v)                                           \\\n\t(BIT_CLEAR_FWCMDQ_H_8814B(x) | BIT_FWCMDQ_H_8814B(v))\n\n/* 2 REG_FWCMDQ_PAGE_8814B */\n\n#define BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B 16\n#define BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B 0xfff\n#define BIT_FWCMDQ_TOTAL_PAGE_8814B(x)                                         \\\n\t(((x) & BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B)                              \\\n\t << BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B)\n#define BITS_FWCMDQ_TOTAL_PAGE_8814B                                           \\\n\t(BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B << BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B)\n#define BIT_CLEAR_FWCMDQ_TOTAL_PAGE_8814B(x)                                   \\\n\t((x) & (~BITS_FWCMDQ_TOTAL_PAGE_8814B))\n#define BIT_GET_FWCMDQ_TOTAL_PAGE_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B) &                          \\\n\t BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B)\n#define BIT_SET_FWCMDQ_TOTAL_PAGE_8814B(x, v)                                  \\\n\t(BIT_CLEAR_FWCMDQ_TOTAL_PAGE_8814B(x) | BIT_FWCMDQ_TOTAL_PAGE_8814B(v))\n\n#define BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B 0\n#define BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B 0xfff\n#define BIT_FWCMDQ_QUEUE_PAGE_8814B(x)                                         \\\n\t(((x) & BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B)                              \\\n\t << BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B)\n#define BITS_FWCMDQ_QUEUE_PAGE_8814B                                           \\\n\t(BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B << BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B)\n#define BIT_CLEAR_FWCMDQ_QUEUE_PAGE_8814B(x)                                   \\\n\t((x) & (~BITS_FWCMDQ_QUEUE_PAGE_8814B))\n#define BIT_GET_FWCMDQ_QUEUE_PAGE_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B) &                          \\\n\t BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B)\n#define BIT_SET_FWCMDQ_QUEUE_PAGE_8814B(x, v)                                  \\\n\t(BIT_CLEAR_FWCMDQ_QUEUE_PAGE_8814B(x) | BIT_FWCMDQ_QUEUE_PAGE_8814B(v))\n\n/* 2 REG_FWCMDQ_INFO_8814B */\n#define BIT_FWCMD_READY_8814B BIT(31)\n#define BIT_FWCMDQ_OVERFLOW_8814B BIT(30)\n#define BIT_FWCMDQ_UNDERFLOW_8814B BIT(29)\n#define BIT_FWCMDQ_RELEASE_MISS_8814B BIT(28)\n\n#define BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B 16\n#define BIT_MASK_FWCMDQ_TOTAL_PKT_8814B 0xfff\n#define BIT_FWCMDQ_TOTAL_PKT_8814B(x)                                          \\\n\t(((x) & BIT_MASK_FWCMDQ_TOTAL_PKT_8814B)                               \\\n\t << BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B)\n#define BITS_FWCMDQ_TOTAL_PKT_8814B                                            \\\n\t(BIT_MASK_FWCMDQ_TOTAL_PKT_8814B << BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B)\n#define BIT_CLEAR_FWCMDQ_TOTAL_PKT_8814B(x)                                    \\\n\t((x) & (~BITS_FWCMDQ_TOTAL_PKT_8814B))\n#define BIT_GET_FWCMDQ_TOTAL_PKT_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B) &                           \\\n\t BIT_MASK_FWCMDQ_TOTAL_PKT_8814B)\n#define BIT_SET_FWCMDQ_TOTAL_PKT_8814B(x, v)                                   \\\n\t(BIT_CLEAR_FWCMDQ_TOTAL_PKT_8814B(x) | BIT_FWCMDQ_TOTAL_PKT_8814B(v))\n\n#define BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B 0\n#define BIT_MASK_FWCMDQ_QUEUE_PKT_8814B 0xfff\n#define BIT_FWCMDQ_QUEUE_PKT_8814B(x)                                          \\\n\t(((x) & BIT_MASK_FWCMDQ_QUEUE_PKT_8814B)                               \\\n\t << BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B)\n#define BITS_FWCMDQ_QUEUE_PKT_8814B                                            \\\n\t(BIT_MASK_FWCMDQ_QUEUE_PKT_8814B << BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B)\n#define BIT_CLEAR_FWCMDQ_QUEUE_PKT_8814B(x)                                    \\\n\t((x) & (~BITS_FWCMDQ_QUEUE_PKT_8814B))\n#define BIT_GET_FWCMDQ_QUEUE_PKT_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B) &                           \\\n\t BIT_MASK_FWCMDQ_QUEUE_PKT_8814B)\n#define BIT_SET_FWCMDQ_QUEUE_PKT_8814B(x, v)                                   \\\n\t(BIT_CLEAR_FWCMDQ_QUEUE_PKT_8814B(x) | BIT_FWCMDQ_QUEUE_PKT_8814B(v))\n\n/* 2 REG_FWCMDQ_HOLD_PKTNUM_8814B */\n\n#define BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B 0\n#define BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B 0xfff\n#define BIT_FWCMDQ_HOLD__PKTNUM_8814B(x)                                       \\\n\t(((x) & BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B)                            \\\n\t << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B)\n#define BITS_FWCMDQ_HOLD__PKTNUM_8814B                                         \\\n\t(BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B                                    \\\n\t << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B)\n#define BIT_CLEAR_FWCMDQ_HOLD__PKTNUM_8814B(x)                                 \\\n\t((x) & (~BITS_FWCMDQ_HOLD__PKTNUM_8814B))\n#define BIT_GET_FWCMDQ_HOLD__PKTNUM_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B) &                        \\\n\t BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B)\n#define BIT_SET_FWCMDQ_HOLD__PKTNUM_8814B(x, v)                                \\\n\t(BIT_CLEAR_FWCMDQ_HOLD__PKTNUM_8814B(x) |                              \\\n\t BIT_FWCMDQ_HOLD__PKTNUM_8814B(v))\n\n/* 2 REG_MU_TX_CTRL_8814B */\n#define BIT_SEARCH_DONE_RDY_8814B BIT(31)\n#define BIT_MU_EN_8814B BIT(30)\n#define BIT_MU_SECONDARY_WAITMODE_EN_8814B BIT(29)\n#define BIT_MU_BB_SCORE_EN_8814B BIT(28)\n#define BIT_MU_SECONDARY_ANT_COUNT_EN_8814B BIT(27)\n#define BIT_MUARB_SEARCH_ERR_EN_8814B BIT(26)\n\n#define BIT_SHIFT_DIS_SU_TXBF_8814B 16\n#define BIT_MASK_DIS_SU_TXBF_8814B 0x3f\n#define BIT_DIS_SU_TXBF_8814B(x)                                               \\\n\t(((x) & BIT_MASK_DIS_SU_TXBF_8814B) << BIT_SHIFT_DIS_SU_TXBF_8814B)\n#define BITS_DIS_SU_TXBF_8814B                                                 \\\n\t(BIT_MASK_DIS_SU_TXBF_8814B << BIT_SHIFT_DIS_SU_TXBF_8814B)\n#define BIT_CLEAR_DIS_SU_TXBF_8814B(x) ((x) & (~BITS_DIS_SU_TXBF_8814B))\n#define BIT_GET_DIS_SU_TXBF_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_DIS_SU_TXBF_8814B) & BIT_MASK_DIS_SU_TXBF_8814B)\n#define BIT_SET_DIS_SU_TXBF_8814B(x, v)                                        \\\n\t(BIT_CLEAR_DIS_SU_TXBF_8814B(x) | BIT_DIS_SU_TXBF_8814B(v))\n\n#define BIT_SHIFT_MU_RL_8814B 12\n#define BIT_MASK_MU_RL_8814B 0xf\n#define BIT_MU_RL_8814B(x)                                                     \\\n\t(((x) & BIT_MASK_MU_RL_8814B) << BIT_SHIFT_MU_RL_8814B)\n#define BITS_MU_RL_8814B (BIT_MASK_MU_RL_8814B << BIT_SHIFT_MU_RL_8814B)\n#define BIT_CLEAR_MU_RL_8814B(x) ((x) & (~BITS_MU_RL_8814B))\n#define BIT_GET_MU_RL_8814B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_MU_RL_8814B) & BIT_MASK_MU_RL_8814B)\n#define BIT_SET_MU_RL_8814B(x, v)                                              \\\n\t(BIT_CLEAR_MU_RL_8814B(x) | BIT_MU_RL_8814B(v))\n\n#define BIT_SHIFT_MU_TAB_SEL_8814B 8\n#define BIT_MASK_MU_TAB_SEL_8814B 0xf\n#define BIT_MU_TAB_SEL_8814B(x)                                                \\\n\t(((x) & BIT_MASK_MU_TAB_SEL_8814B) << BIT_SHIFT_MU_TAB_SEL_8814B)\n#define BITS_MU_TAB_SEL_8814B                                                  \\\n\t(BIT_MASK_MU_TAB_SEL_8814B << BIT_SHIFT_MU_TAB_SEL_8814B)\n#define BIT_CLEAR_MU_TAB_SEL_8814B(x) ((x) & (~BITS_MU_TAB_SEL_8814B))\n#define BIT_GET_MU_TAB_SEL_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_MU_TAB_SEL_8814B) & BIT_MASK_MU_TAB_SEL_8814B)\n#define BIT_SET_MU_TAB_SEL_8814B(x, v)                                         \\\n\t(BIT_CLEAR_MU_TAB_SEL_8814B(x) | BIT_MU_TAB_SEL_8814B(v))\n\n#define BIT_SHIFT_MU_TAB_VALID_8814B 0\n#define BIT_MASK_MU_TAB_VALID_8814B 0x3f\n#define BIT_MU_TAB_VALID_8814B(x)                                              \\\n\t(((x) & BIT_MASK_MU_TAB_VALID_8814B) << BIT_SHIFT_MU_TAB_VALID_8814B)\n#define BITS_MU_TAB_VALID_8814B                                                \\\n\t(BIT_MASK_MU_TAB_VALID_8814B << BIT_SHIFT_MU_TAB_VALID_8814B)\n#define BIT_CLEAR_MU_TAB_VALID_8814B(x) ((x) & (~BITS_MU_TAB_VALID_8814B))\n#define BIT_GET_MU_TAB_VALID_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_MU_TAB_VALID_8814B) & BIT_MASK_MU_TAB_VALID_8814B)\n#define BIT_SET_MU_TAB_VALID_8814B(x, v)                                       \\\n\t(BIT_CLEAR_MU_TAB_VALID_8814B(x) | BIT_MU_TAB_VALID_8814B(v))\n\n/* 2 REG_MU_STA_GID_VLD_8814B */\n\n#define BIT_SHIFT_MU_STA_GTAB_VALID_8814B 0\n#define BIT_MASK_MU_STA_GTAB_VALID_8814B 0xffffffffL\n#define BIT_MU_STA_GTAB_VALID_8814B(x)                                         \\\n\t(((x) & BIT_MASK_MU_STA_GTAB_VALID_8814B)                              \\\n\t << BIT_SHIFT_MU_STA_GTAB_VALID_8814B)\n#define BITS_MU_STA_GTAB_VALID_8814B                                           \\\n\t(BIT_MASK_MU_STA_GTAB_VALID_8814B << BIT_SHIFT_MU_STA_GTAB_VALID_8814B)\n#define BIT_CLEAR_MU_STA_GTAB_VALID_8814B(x)                                   \\\n\t((x) & (~BITS_MU_STA_GTAB_VALID_8814B))\n#define BIT_GET_MU_STA_GTAB_VALID_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_MU_STA_GTAB_VALID_8814B) &                          \\\n\t BIT_MASK_MU_STA_GTAB_VALID_8814B)\n#define BIT_SET_MU_STA_GTAB_VALID_8814B(x, v)                                  \\\n\t(BIT_CLEAR_MU_STA_GTAB_VALID_8814B(x) | BIT_MU_STA_GTAB_VALID_8814B(v))\n\n/* 2 REG_MU_STA_USER_POS_INFO_8814B */\n\n#define BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B 0\n#define BIT_MASK_MU_STA_GTAB_POSITION_L_8814B 0xffffffffL\n#define BIT_MU_STA_GTAB_POSITION_L_8814B(x)                                    \\\n\t(((x) & BIT_MASK_MU_STA_GTAB_POSITION_L_8814B)                         \\\n\t << BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B)\n#define BITS_MU_STA_GTAB_POSITION_L_8814B                                      \\\n\t(BIT_MASK_MU_STA_GTAB_POSITION_L_8814B                                 \\\n\t << BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B)\n#define BIT_CLEAR_MU_STA_GTAB_POSITION_L_8814B(x)                              \\\n\t((x) & (~BITS_MU_STA_GTAB_POSITION_L_8814B))\n#define BIT_GET_MU_STA_GTAB_POSITION_L_8814B(x)                                \\\n\t(((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B) &                     \\\n\t BIT_MASK_MU_STA_GTAB_POSITION_L_8814B)\n#define BIT_SET_MU_STA_GTAB_POSITION_L_8814B(x, v)                             \\\n\t(BIT_CLEAR_MU_STA_GTAB_POSITION_L_8814B(x) |                           \\\n\t BIT_MU_STA_GTAB_POSITION_L_8814B(v))\n\n/* 2 REG_MU_STA_USER_POS_INFO_H_8814B */\n\n#define BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B 0\n#define BIT_MASK_MU_STA_GTAB_POSITION_H_8814B 0xffffffffL\n#define BIT_MU_STA_GTAB_POSITION_H_8814B(x)                                    \\\n\t(((x) & BIT_MASK_MU_STA_GTAB_POSITION_H_8814B)                         \\\n\t << BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B)\n#define BITS_MU_STA_GTAB_POSITION_H_8814B                                      \\\n\t(BIT_MASK_MU_STA_GTAB_POSITION_H_8814B                                 \\\n\t << BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B)\n#define BIT_CLEAR_MU_STA_GTAB_POSITION_H_8814B(x)                              \\\n\t((x) & (~BITS_MU_STA_GTAB_POSITION_H_8814B))\n#define BIT_GET_MU_STA_GTAB_POSITION_H_8814B(x)                                \\\n\t(((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B) &                     \\\n\t BIT_MASK_MU_STA_GTAB_POSITION_H_8814B)\n#define BIT_SET_MU_STA_GTAB_POSITION_H_8814B(x, v)                             \\\n\t(BIT_CLEAR_MU_STA_GTAB_POSITION_H_8814B(x) |                           \\\n\t BIT_MU_STA_GTAB_POSITION_H_8814B(v))\n\n/* 2 REG_CHNL_INFO_CTRL_8814B */\n#define BIT_CHNL_REF_RXNAV_8814B BIT(7)\n#define BIT_CHNL_REF_VBON_8814B BIT(6)\n#define BIT_CHNL_REF_EDCA_8814B BIT(5)\n#define BIT_CHNL_REF_CCA_8814B BIT(4)\n#define BIT_RST_CHNL_BUSY_8814B BIT(3)\n#define BIT_RST_CHNL_IDLE_8814B BIT(2)\n#define BIT_CHNL_INFO_RST_8814B BIT(1)\n#define BIT_ATM_AIRTIME_EN_8814B BIT(0)\n\n/* 2 REG_CHNL_IDLE_TIME_8814B */\n\n#define BIT_SHIFT_CHNL_IDLE_TIME_8814B 0\n#define BIT_MASK_CHNL_IDLE_TIME_8814B 0xffffffffL\n#define BIT_CHNL_IDLE_TIME_8814B(x)                                            \\\n\t(((x) & BIT_MASK_CHNL_IDLE_TIME_8814B)                                 \\\n\t << BIT_SHIFT_CHNL_IDLE_TIME_8814B)\n#define BITS_CHNL_IDLE_TIME_8814B                                              \\\n\t(BIT_MASK_CHNL_IDLE_TIME_8814B << BIT_SHIFT_CHNL_IDLE_TIME_8814B)\n#define BIT_CLEAR_CHNL_IDLE_TIME_8814B(x) ((x) & (~BITS_CHNL_IDLE_TIME_8814B))\n#define BIT_GET_CHNL_IDLE_TIME_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8814B) &                             \\\n\t BIT_MASK_CHNL_IDLE_TIME_8814B)\n#define BIT_SET_CHNL_IDLE_TIME_8814B(x, v)                                     \\\n\t(BIT_CLEAR_CHNL_IDLE_TIME_8814B(x) | BIT_CHNL_IDLE_TIME_8814B(v))\n\n/* 2 REG_CHNL_BUSY_TIME_8814B */\n\n#define BIT_SHIFT_CHNL_BUSY_TIME_8814B 0\n#define BIT_MASK_CHNL_BUSY_TIME_8814B 0xffffffffL\n#define BIT_CHNL_BUSY_TIME_8814B(x)                                            \\\n\t(((x) & BIT_MASK_CHNL_BUSY_TIME_8814B)                                 \\\n\t << BIT_SHIFT_CHNL_BUSY_TIME_8814B)\n#define BITS_CHNL_BUSY_TIME_8814B                                              \\\n\t(BIT_MASK_CHNL_BUSY_TIME_8814B << BIT_SHIFT_CHNL_BUSY_TIME_8814B)\n#define BIT_CLEAR_CHNL_BUSY_TIME_8814B(x) ((x) & (~BITS_CHNL_BUSY_TIME_8814B))\n#define BIT_GET_CHNL_BUSY_TIME_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8814B) &                             \\\n\t BIT_MASK_CHNL_BUSY_TIME_8814B)\n#define BIT_SET_CHNL_BUSY_TIME_8814B(x, v)                                     \\\n\t(BIT_CLEAR_CHNL_BUSY_TIME_8814B(x) | BIT_CHNL_BUSY_TIME_8814B(v))\n\n/* 2 REG_MU_TRX_DBG_CNT_V1_8814B */\n#define BIT_FORCE_SND_STS_EN_8814B BIT(31)\n\n#define BIT_SHIFT_SND_STS_VALUE_8814B 24\n#define BIT_MASK_SND_STS_VALUE_8814B 0x3f\n#define BIT_SND_STS_VALUE_8814B(x)                                             \\\n\t(((x) & BIT_MASK_SND_STS_VALUE_8814B) << BIT_SHIFT_SND_STS_VALUE_8814B)\n#define BITS_SND_STS_VALUE_8814B                                               \\\n\t(BIT_MASK_SND_STS_VALUE_8814B << BIT_SHIFT_SND_STS_VALUE_8814B)\n#define BIT_CLEAR_SND_STS_VALUE_8814B(x) ((x) & (~BITS_SND_STS_VALUE_8814B))\n#define BIT_GET_SND_STS_VALUE_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SND_STS_VALUE_8814B) & BIT_MASK_SND_STS_VALUE_8814B)\n#define BIT_SET_SND_STS_VALUE_8814B(x, v)                                      \\\n\t(BIT_CLEAR_SND_STS_VALUE_8814B(x) | BIT_SND_STS_VALUE_8814B(v))\n\n#define BIT_MU_DNGCNT_RST_8814B BIT(20)\n\n#define BIT_SHIFT_MU_DNGCNT_SEL_8814B 16\n#define BIT_MASK_MU_DNGCNT_SEL_8814B 0xf\n#define BIT_MU_DNGCNT_SEL_8814B(x)                                             \\\n\t(((x) & BIT_MASK_MU_DNGCNT_SEL_8814B) << BIT_SHIFT_MU_DNGCNT_SEL_8814B)\n#define BITS_MU_DNGCNT_SEL_8814B                                               \\\n\t(BIT_MASK_MU_DNGCNT_SEL_8814B << BIT_SHIFT_MU_DNGCNT_SEL_8814B)\n#define BIT_CLEAR_MU_DNGCNT_SEL_8814B(x) ((x) & (~BITS_MU_DNGCNT_SEL_8814B))\n#define BIT_GET_MU_DNGCNT_SEL_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MU_DNGCNT_SEL_8814B) & BIT_MASK_MU_DNGCNT_SEL_8814B)\n#define BIT_SET_MU_DNGCNT_SEL_8814B(x, v)                                      \\\n\t(BIT_CLEAR_MU_DNGCNT_SEL_8814B(x) | BIT_MU_DNGCNT_SEL_8814B(v))\n\n#define BIT_SHIFT_MU_DNGCNT_8814B 0\n#define BIT_MASK_MU_DNGCNT_8814B 0xffff\n#define BIT_MU_DNGCNT_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_MU_DNGCNT_8814B) << BIT_SHIFT_MU_DNGCNT_8814B)\n#define BITS_MU_DNGCNT_8814B                                                   \\\n\t(BIT_MASK_MU_DNGCNT_8814B << BIT_SHIFT_MU_DNGCNT_8814B)\n#define BIT_CLEAR_MU_DNGCNT_8814B(x) ((x) & (~BITS_MU_DNGCNT_8814B))\n#define BIT_GET_MU_DNGCNT_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_MU_DNGCNT_8814B) & BIT_MASK_MU_DNGCNT_8814B)\n#define BIT_SET_MU_DNGCNT_8814B(x, v)                                          \\\n\t(BIT_CLEAR_MU_DNGCNT_8814B(x) | BIT_MU_DNGCNT_8814B(v))\n\n/* 2 REG_SWPS_CTRL_8814B */\n\n#define BIT_SHIFT_SWPS_RPT_LENGTH_8814B 8\n#define BIT_MASK_SWPS_RPT_LENGTH_8814B 0x7f\n#define BIT_SWPS_RPT_LENGTH_8814B(x)                                           \\\n\t(((x) & BIT_MASK_SWPS_RPT_LENGTH_8814B)                                \\\n\t << BIT_SHIFT_SWPS_RPT_LENGTH_8814B)\n#define BITS_SWPS_RPT_LENGTH_8814B                                             \\\n\t(BIT_MASK_SWPS_RPT_LENGTH_8814B << BIT_SHIFT_SWPS_RPT_LENGTH_8814B)\n#define BIT_CLEAR_SWPS_RPT_LENGTH_8814B(x) ((x) & (~BITS_SWPS_RPT_LENGTH_8814B))\n#define BIT_GET_SWPS_RPT_LENGTH_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_SWPS_RPT_LENGTH_8814B) &                            \\\n\t BIT_MASK_SWPS_RPT_LENGTH_8814B)\n#define BIT_SET_SWPS_RPT_LENGTH_8814B(x, v)                                    \\\n\t(BIT_CLEAR_SWPS_RPT_LENGTH_8814B(x) | BIT_SWPS_RPT_LENGTH_8814B(v))\n\n#define BIT_SHIFT_MACID_SWPS_EN_SEL_8814B 2\n#define BIT_MASK_MACID_SWPS_EN_SEL_8814B 0x3\n#define BIT_MACID_SWPS_EN_SEL_8814B(x)                                         \\\n\t(((x) & BIT_MASK_MACID_SWPS_EN_SEL_8814B)                              \\\n\t << BIT_SHIFT_MACID_SWPS_EN_SEL_8814B)\n#define BITS_MACID_SWPS_EN_SEL_8814B                                           \\\n\t(BIT_MASK_MACID_SWPS_EN_SEL_8814B << BIT_SHIFT_MACID_SWPS_EN_SEL_8814B)\n#define BIT_CLEAR_MACID_SWPS_EN_SEL_8814B(x)                                   \\\n\t((x) & (~BITS_MACID_SWPS_EN_SEL_8814B))\n#define BIT_GET_MACID_SWPS_EN_SEL_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_MACID_SWPS_EN_SEL_8814B) &                          \\\n\t BIT_MASK_MACID_SWPS_EN_SEL_8814B)\n#define BIT_SET_MACID_SWPS_EN_SEL_8814B(x, v)                                  \\\n\t(BIT_CLEAR_MACID_SWPS_EN_SEL_8814B(x) | BIT_MACID_SWPS_EN_SEL_8814B(v))\n\n#define BIT_SWPS_MANUALL_POLLING_8814B BIT(1)\n#define BIT_SWPS_EN_8814B BIT(0)\n\n/* 2 REG_SWPS_PKT_TH_8814B */\n\n#define BIT_SHIFT_SWPS_PKT_TH_8814B 0\n#define BIT_MASK_SWPS_PKT_TH_8814B 0xffff\n#define BIT_SWPS_PKT_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_SWPS_PKT_TH_8814B) << BIT_SHIFT_SWPS_PKT_TH_8814B)\n#define BITS_SWPS_PKT_TH_8814B                                                 \\\n\t(BIT_MASK_SWPS_PKT_TH_8814B << BIT_SHIFT_SWPS_PKT_TH_8814B)\n#define BIT_CLEAR_SWPS_PKT_TH_8814B(x) ((x) & (~BITS_SWPS_PKT_TH_8814B))\n#define BIT_GET_SWPS_PKT_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_SWPS_PKT_TH_8814B) & BIT_MASK_SWPS_PKT_TH_8814B)\n#define BIT_SET_SWPS_PKT_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_SWPS_PKT_TH_8814B(x) | BIT_SWPS_PKT_TH_8814B(v))\n\n/* 2 REG_SWPS_TIME_TH_8814B */\n\n#define BIT_SHIFT_SWPS_PSTIME_TH_8814B 16\n#define BIT_MASK_SWPS_PSTIME_TH_8814B 0xffff\n#define BIT_SWPS_PSTIME_TH_8814B(x)                                            \\\n\t(((x) & BIT_MASK_SWPS_PSTIME_TH_8814B)                                 \\\n\t << BIT_SHIFT_SWPS_PSTIME_TH_8814B)\n#define BITS_SWPS_PSTIME_TH_8814B                                              \\\n\t(BIT_MASK_SWPS_PSTIME_TH_8814B << BIT_SHIFT_SWPS_PSTIME_TH_8814B)\n#define BIT_CLEAR_SWPS_PSTIME_TH_8814B(x) ((x) & (~BITS_SWPS_PSTIME_TH_8814B))\n#define BIT_GET_SWPS_PSTIME_TH_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_SWPS_PSTIME_TH_8814B) &                             \\\n\t BIT_MASK_SWPS_PSTIME_TH_8814B)\n#define BIT_SET_SWPS_PSTIME_TH_8814B(x, v)                                     \\\n\t(BIT_CLEAR_SWPS_PSTIME_TH_8814B(x) | BIT_SWPS_PSTIME_TH_8814B(v))\n\n#define BIT_SHIFT_SWPS_TIME_TH_8814B 0\n#define BIT_MASK_SWPS_TIME_TH_8814B 0xffff\n#define BIT_SWPS_TIME_TH_8814B(x)                                              \\\n\t(((x) & BIT_MASK_SWPS_TIME_TH_8814B) << BIT_SHIFT_SWPS_TIME_TH_8814B)\n#define BITS_SWPS_TIME_TH_8814B                                                \\\n\t(BIT_MASK_SWPS_TIME_TH_8814B << BIT_SHIFT_SWPS_TIME_TH_8814B)\n#define BIT_CLEAR_SWPS_TIME_TH_8814B(x) ((x) & (~BITS_SWPS_TIME_TH_8814B))\n#define BIT_GET_SWPS_TIME_TH_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SWPS_TIME_TH_8814B) & BIT_MASK_SWPS_TIME_TH_8814B)\n#define BIT_SET_SWPS_TIME_TH_8814B(x, v)                                       \\\n\t(BIT_CLEAR_SWPS_TIME_TH_8814B(x) | BIT_SWPS_TIME_TH_8814B(v))\n\n/* 2 REG_MACID_SWPS_EN_8814B */\n\n#define BIT_SHIFT_MACID_SWPS_EN_8814B 0\n#define BIT_MASK_MACID_SWPS_EN_8814B 0xffffffffL\n#define BIT_MACID_SWPS_EN_8814B(x)                                             \\\n\t(((x) & BIT_MASK_MACID_SWPS_EN_8814B) << BIT_SHIFT_MACID_SWPS_EN_8814B)\n#define BITS_MACID_SWPS_EN_8814B                                               \\\n\t(BIT_MASK_MACID_SWPS_EN_8814B << BIT_SHIFT_MACID_SWPS_EN_8814B)\n#define BIT_CLEAR_MACID_SWPS_EN_8814B(x) ((x) & (~BITS_MACID_SWPS_EN_8814B))\n#define BIT_GET_MACID_SWPS_EN_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MACID_SWPS_EN_8814B) & BIT_MASK_MACID_SWPS_EN_8814B)\n#define BIT_SET_MACID_SWPS_EN_8814B(x, v)                                      \\\n\t(BIT_CLEAR_MACID_SWPS_EN_8814B(x) | BIT_MACID_SWPS_EN_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_EDCA_VO_PARAM_8814B */\n\n#define BIT_SHIFT_TXOPLIMIT_8814B 16\n#define BIT_MASK_TXOPLIMIT_8814B 0x7ff\n#define BIT_TXOPLIMIT_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B)\n#define BITS_TXOPLIMIT_8814B                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B)\n#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B))\n#define BIT_GET_TXOPLIMIT_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B)\n#define BIT_SET_TXOPLIMIT_8814B(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v))\n\n#define BIT_SHIFT_CW_8814B 8\n#define BIT_MASK_CW_8814B 0xff\n#define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B)\n#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B)\n#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B))\n#define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B)\n#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v))\n\n#define BIT_SHIFT_AIFS_8814B 0\n#define BIT_MASK_AIFS_8814B 0xff\n#define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B)\n#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B)\n#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B))\n#define BIT_GET_AIFS_8814B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B)\n#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v))\n\n/* 2 REG_EDCA_VI_PARAM_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_TXOPLIMIT_8814B 16\n#define BIT_MASK_TXOPLIMIT_8814B 0x7ff\n#define BIT_TXOPLIMIT_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B)\n#define BITS_TXOPLIMIT_8814B                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B)\n#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B))\n#define BIT_GET_TXOPLIMIT_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B)\n#define BIT_SET_TXOPLIMIT_8814B(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v))\n\n#define BIT_SHIFT_CW_8814B 8\n#define BIT_MASK_CW_8814B 0xff\n#define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B)\n#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B)\n#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B))\n#define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B)\n#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v))\n\n#define BIT_SHIFT_AIFS_8814B 0\n#define BIT_MASK_AIFS_8814B 0xff\n#define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B)\n#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B)\n#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B))\n#define BIT_GET_AIFS_8814B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B)\n#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v))\n\n/* 2 REG_EDCA_BE_PARAM_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_TXOPLIMIT_8814B 16\n#define BIT_MASK_TXOPLIMIT_8814B 0x7ff\n#define BIT_TXOPLIMIT_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B)\n#define BITS_TXOPLIMIT_8814B                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B)\n#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B))\n#define BIT_GET_TXOPLIMIT_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B)\n#define BIT_SET_TXOPLIMIT_8814B(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v))\n\n#define BIT_SHIFT_CW_8814B 8\n#define BIT_MASK_CW_8814B 0xff\n#define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B)\n#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B)\n#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B))\n#define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B)\n#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v))\n\n#define BIT_SHIFT_AIFS_8814B 0\n#define BIT_MASK_AIFS_8814B 0xff\n#define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B)\n#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B)\n#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B))\n#define BIT_GET_AIFS_8814B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B)\n#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v))\n\n/* 2 REG_EDCA_BK_PARAM_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_TXOPLIMIT_8814B 16\n#define BIT_MASK_TXOPLIMIT_8814B 0x7ff\n#define BIT_TXOPLIMIT_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B)\n#define BITS_TXOPLIMIT_8814B                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B)\n#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B))\n#define BIT_GET_TXOPLIMIT_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B)\n#define BIT_SET_TXOPLIMIT_8814B(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v))\n\n#define BIT_SHIFT_CW_8814B 8\n#define BIT_MASK_CW_8814B 0xff\n#define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B)\n#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B)\n#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B))\n#define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B)\n#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v))\n\n#define BIT_SHIFT_AIFS_8814B 0\n#define BIT_MASK_AIFS_8814B 0xff\n#define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B)\n#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B)\n#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B))\n#define BIT_GET_AIFS_8814B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B)\n#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v))\n\n/* 2 REG_BCNTCFG_8814B */\n\n#define BIT_SHIFT_BCNCW_MAX_8814B 12\n#define BIT_MASK_BCNCW_MAX_8814B 0xf\n#define BIT_BCNCW_MAX_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_BCNCW_MAX_8814B) << BIT_SHIFT_BCNCW_MAX_8814B)\n#define BITS_BCNCW_MAX_8814B                                                   \\\n\t(BIT_MASK_BCNCW_MAX_8814B << BIT_SHIFT_BCNCW_MAX_8814B)\n#define BIT_CLEAR_BCNCW_MAX_8814B(x) ((x) & (~BITS_BCNCW_MAX_8814B))\n#define BIT_GET_BCNCW_MAX_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNCW_MAX_8814B) & BIT_MASK_BCNCW_MAX_8814B)\n#define BIT_SET_BCNCW_MAX_8814B(x, v)                                          \\\n\t(BIT_CLEAR_BCNCW_MAX_8814B(x) | BIT_BCNCW_MAX_8814B(v))\n\n#define BIT_SHIFT_BCNCW_MIN_8814B 8\n#define BIT_MASK_BCNCW_MIN_8814B 0xf\n#define BIT_BCNCW_MIN_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_BCNCW_MIN_8814B) << BIT_SHIFT_BCNCW_MIN_8814B)\n#define BITS_BCNCW_MIN_8814B                                                   \\\n\t(BIT_MASK_BCNCW_MIN_8814B << BIT_SHIFT_BCNCW_MIN_8814B)\n#define BIT_CLEAR_BCNCW_MIN_8814B(x) ((x) & (~BITS_BCNCW_MIN_8814B))\n#define BIT_GET_BCNCW_MIN_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNCW_MIN_8814B) & BIT_MASK_BCNCW_MIN_8814B)\n#define BIT_SET_BCNCW_MIN_8814B(x, v)                                          \\\n\t(BIT_CLEAR_BCNCW_MIN_8814B(x) | BIT_BCNCW_MIN_8814B(v))\n\n#define BIT_SHIFT_BCNIFS_8814B 0\n#define BIT_MASK_BCNIFS_8814B 0xff\n#define BIT_BCNIFS_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_BCNIFS_8814B) << BIT_SHIFT_BCNIFS_8814B)\n#define BITS_BCNIFS_8814B (BIT_MASK_BCNIFS_8814B << BIT_SHIFT_BCNIFS_8814B)\n#define BIT_CLEAR_BCNIFS_8814B(x) ((x) & (~BITS_BCNIFS_8814B))\n#define BIT_GET_BCNIFS_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_BCNIFS_8814B) & BIT_MASK_BCNIFS_8814B)\n#define BIT_SET_BCNIFS_8814B(x, v)                                             \\\n\t(BIT_CLEAR_BCNIFS_8814B(x) | BIT_BCNIFS_8814B(v))\n\n/* 2 REG_PIFS_8814B */\n\n#define BIT_SHIFT_PIFS_8814B 0\n#define BIT_MASK_PIFS_8814B 0xff\n#define BIT_PIFS_8814B(x) (((x) & BIT_MASK_PIFS_8814B) << BIT_SHIFT_PIFS_8814B)\n#define BITS_PIFS_8814B (BIT_MASK_PIFS_8814B << BIT_SHIFT_PIFS_8814B)\n#define BIT_CLEAR_PIFS_8814B(x) ((x) & (~BITS_PIFS_8814B))\n#define BIT_GET_PIFS_8814B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_PIFS_8814B) & BIT_MASK_PIFS_8814B)\n#define BIT_SET_PIFS_8814B(x, v) (BIT_CLEAR_PIFS_8814B(x) | BIT_PIFS_8814B(v))\n\n/* 2 REG_RDG_PIFS_8814B */\n\n#define BIT_SHIFT_RDG_PIFS_8814B 0\n#define BIT_MASK_RDG_PIFS_8814B 0xff\n#define BIT_RDG_PIFS_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_RDG_PIFS_8814B) << BIT_SHIFT_RDG_PIFS_8814B)\n#define BITS_RDG_PIFS_8814B                                                    \\\n\t(BIT_MASK_RDG_PIFS_8814B << BIT_SHIFT_RDG_PIFS_8814B)\n#define BIT_CLEAR_RDG_PIFS_8814B(x) ((x) & (~BITS_RDG_PIFS_8814B))\n#define BIT_GET_RDG_PIFS_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RDG_PIFS_8814B) & BIT_MASK_RDG_PIFS_8814B)\n#define BIT_SET_RDG_PIFS_8814B(x, v)                                           \\\n\t(BIT_CLEAR_RDG_PIFS_8814B(x) | BIT_RDG_PIFS_8814B(v))\n\n/* 2 REG_SIFS_8814B */\n\n#define BIT_SHIFT_SIFS_OFDM_TRX_8814B 24\n#define BIT_MASK_SIFS_OFDM_TRX_8814B 0xff\n#define BIT_SIFS_OFDM_TRX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_OFDM_TRX_8814B) << BIT_SHIFT_SIFS_OFDM_TRX_8814B)\n#define BITS_SIFS_OFDM_TRX_8814B                                               \\\n\t(BIT_MASK_SIFS_OFDM_TRX_8814B << BIT_SHIFT_SIFS_OFDM_TRX_8814B)\n#define BIT_CLEAR_SIFS_OFDM_TRX_8814B(x) ((x) & (~BITS_SIFS_OFDM_TRX_8814B))\n#define BIT_GET_SIFS_OFDM_TRX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8814B) & BIT_MASK_SIFS_OFDM_TRX_8814B)\n#define BIT_SET_SIFS_OFDM_TRX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_OFDM_TRX_8814B(x) | BIT_SIFS_OFDM_TRX_8814B(v))\n\n#define BIT_SHIFT_SIFS_CCK_TRX_8814B 16\n#define BIT_MASK_SIFS_CCK_TRX_8814B 0xff\n#define BIT_SIFS_CCK_TRX_8814B(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_CCK_TRX_8814B) << BIT_SHIFT_SIFS_CCK_TRX_8814B)\n#define BITS_SIFS_CCK_TRX_8814B                                                \\\n\t(BIT_MASK_SIFS_CCK_TRX_8814B << BIT_SHIFT_SIFS_CCK_TRX_8814B)\n#define BIT_CLEAR_SIFS_CCK_TRX_8814B(x) ((x) & (~BITS_SIFS_CCK_TRX_8814B))\n#define BIT_GET_SIFS_CCK_TRX_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_CCK_TRX_8814B) & BIT_MASK_SIFS_CCK_TRX_8814B)\n#define BIT_SET_SIFS_CCK_TRX_8814B(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_CCK_TRX_8814B(x) | BIT_SIFS_CCK_TRX_8814B(v))\n\n#define BIT_SHIFT_SIFS_OFDM_CTX_8814B 8\n#define BIT_MASK_SIFS_OFDM_CTX_8814B 0xff\n#define BIT_SIFS_OFDM_CTX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_OFDM_CTX_8814B) << BIT_SHIFT_SIFS_OFDM_CTX_8814B)\n#define BITS_SIFS_OFDM_CTX_8814B                                               \\\n\t(BIT_MASK_SIFS_OFDM_CTX_8814B << BIT_SHIFT_SIFS_OFDM_CTX_8814B)\n#define BIT_CLEAR_SIFS_OFDM_CTX_8814B(x) ((x) & (~BITS_SIFS_OFDM_CTX_8814B))\n#define BIT_GET_SIFS_OFDM_CTX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8814B) & BIT_MASK_SIFS_OFDM_CTX_8814B)\n#define BIT_SET_SIFS_OFDM_CTX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_OFDM_CTX_8814B(x) | BIT_SIFS_OFDM_CTX_8814B(v))\n\n#define BIT_SHIFT_SIFS_CCK_CTX_8814B 0\n#define BIT_MASK_SIFS_CCK_CTX_8814B 0xff\n#define BIT_SIFS_CCK_CTX_8814B(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_CCK_CTX_8814B) << BIT_SHIFT_SIFS_CCK_CTX_8814B)\n#define BITS_SIFS_CCK_CTX_8814B                                                \\\n\t(BIT_MASK_SIFS_CCK_CTX_8814B << BIT_SHIFT_SIFS_CCK_CTX_8814B)\n#define BIT_CLEAR_SIFS_CCK_CTX_8814B(x) ((x) & (~BITS_SIFS_CCK_CTX_8814B))\n#define BIT_GET_SIFS_CCK_CTX_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_CCK_CTX_8814B) & BIT_MASK_SIFS_CCK_CTX_8814B)\n#define BIT_SET_SIFS_CCK_CTX_8814B(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_CCK_CTX_8814B(x) | BIT_SIFS_CCK_CTX_8814B(v))\n\n/* 2 REG_FORCE_BCN_IFS_V1_8814B */\n\n#define BIT_SHIFT_FORCE_BCN_IFS_8814B 0\n#define BIT_MASK_FORCE_BCN_IFS_8814B 0xff\n#define BIT_FORCE_BCN_IFS_8814B(x)                                             \\\n\t(((x) & BIT_MASK_FORCE_BCN_IFS_8814B) << BIT_SHIFT_FORCE_BCN_IFS_8814B)\n#define BITS_FORCE_BCN_IFS_8814B                                               \\\n\t(BIT_MASK_FORCE_BCN_IFS_8814B << BIT_SHIFT_FORCE_BCN_IFS_8814B)\n#define BIT_CLEAR_FORCE_BCN_IFS_8814B(x) ((x) & (~BITS_FORCE_BCN_IFS_8814B))\n#define BIT_GET_FORCE_BCN_IFS_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_FORCE_BCN_IFS_8814B) & BIT_MASK_FORCE_BCN_IFS_8814B)\n#define BIT_SET_FORCE_BCN_IFS_8814B(x, v)                                      \\\n\t(BIT_CLEAR_FORCE_BCN_IFS_8814B(x) | BIT_FORCE_BCN_IFS_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_AGGR_BREAK_TIME_8814B */\n\n#define BIT_SHIFT_AGGR_BK_TIME_8814B 0\n#define BIT_MASK_AGGR_BK_TIME_8814B 0xff\n#define BIT_AGGR_BK_TIME_8814B(x)                                              \\\n\t(((x) & BIT_MASK_AGGR_BK_TIME_8814B) << BIT_SHIFT_AGGR_BK_TIME_8814B)\n#define BITS_AGGR_BK_TIME_8814B                                                \\\n\t(BIT_MASK_AGGR_BK_TIME_8814B << BIT_SHIFT_AGGR_BK_TIME_8814B)\n#define BIT_CLEAR_AGGR_BK_TIME_8814B(x) ((x) & (~BITS_AGGR_BK_TIME_8814B))\n#define BIT_GET_AGGR_BK_TIME_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_AGGR_BK_TIME_8814B) & BIT_MASK_AGGR_BK_TIME_8814B)\n#define BIT_SET_AGGR_BK_TIME_8814B(x, v)                                       \\\n\t(BIT_CLEAR_AGGR_BK_TIME_8814B(x) | BIT_AGGR_BK_TIME_8814B(v))\n\n/* 2 REG_SLOT_8814B */\n\n#define BIT_SHIFT_SLOT_8814B 0\n#define BIT_MASK_SLOT_8814B 0xff\n#define BIT_SLOT_8814B(x) (((x) & BIT_MASK_SLOT_8814B) << BIT_SHIFT_SLOT_8814B)\n#define BITS_SLOT_8814B (BIT_MASK_SLOT_8814B << BIT_SHIFT_SLOT_8814B)\n#define BIT_CLEAR_SLOT_8814B(x) ((x) & (~BITS_SLOT_8814B))\n#define BIT_GET_SLOT_8814B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_SLOT_8814B) & BIT_MASK_SLOT_8814B)\n#define BIT_SET_SLOT_8814B(x, v) (BIT_CLEAR_SLOT_8814B(x) | BIT_SLOT_8814B(v))\n\n/* 2 REG_EDCA_CPUMGQ_PARAM_8814B */\n\n#define BIT_SHIFT_CW_V1_8814B 8\n#define BIT_MASK_CW_V1_8814B 0xff\n#define BIT_CW_V1_8814B(x)                                                     \\\n\t(((x) & BIT_MASK_CW_V1_8814B) << BIT_SHIFT_CW_V1_8814B)\n#define BITS_CW_V1_8814B (BIT_MASK_CW_V1_8814B << BIT_SHIFT_CW_V1_8814B)\n#define BIT_CLEAR_CW_V1_8814B(x) ((x) & (~BITS_CW_V1_8814B))\n#define BIT_GET_CW_V1_8814B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CW_V1_8814B) & BIT_MASK_CW_V1_8814B)\n#define BIT_SET_CW_V1_8814B(x, v)                                              \\\n\t(BIT_CLEAR_CW_V1_8814B(x) | BIT_CW_V1_8814B(v))\n\n#define BIT_SHIFT_AIFS_V1_8814B 0\n#define BIT_MASK_AIFS_V1_8814B 0xff\n#define BIT_AIFS_V1_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_AIFS_V1_8814B) << BIT_SHIFT_AIFS_V1_8814B)\n#define BITS_AIFS_V1_8814B (BIT_MASK_AIFS_V1_8814B << BIT_SHIFT_AIFS_V1_8814B)\n#define BIT_CLEAR_AIFS_V1_8814B(x) ((x) & (~BITS_AIFS_V1_8814B))\n#define BIT_GET_AIFS_V1_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_AIFS_V1_8814B) & BIT_MASK_AIFS_V1_8814B)\n#define BIT_SET_AIFS_V1_8814B(x, v)                                            \\\n\t(BIT_CLEAR_AIFS_V1_8814B(x) | BIT_AIFS_V1_8814B(v))\n\n/* 2 REG_CPUMGQ_PAUSE_8814B */\n#define BIT_MAC_STOP_CPUMGQ_V1_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_TX_PTCL_CTRL_8814B */\n#define BIT_DIS_EDCCA_8814B BIT(15)\n#define BIT_DIS_CCA_8814B BIT(14)\n#define BIT_LSIG_TXOP_TXCMD_NAV_8814B BIT(13)\n#define BIT_SIFS_BK_EN_8814B BIT(12)\n\n#define BIT_SHIFT_TXQ_NAV_MSK_8814B 8\n#define BIT_MASK_TXQ_NAV_MSK_8814B 0xf\n#define BIT_TXQ_NAV_MSK_8814B(x)                                               \\\n\t(((x) & BIT_MASK_TXQ_NAV_MSK_8814B) << BIT_SHIFT_TXQ_NAV_MSK_8814B)\n#define BITS_TXQ_NAV_MSK_8814B                                                 \\\n\t(BIT_MASK_TXQ_NAV_MSK_8814B << BIT_SHIFT_TXQ_NAV_MSK_8814B)\n#define BIT_CLEAR_TXQ_NAV_MSK_8814B(x) ((x) & (~BITS_TXQ_NAV_MSK_8814B))\n#define BIT_GET_TXQ_NAV_MSK_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_TXQ_NAV_MSK_8814B) & BIT_MASK_TXQ_NAV_MSK_8814B)\n#define BIT_SET_TXQ_NAV_MSK_8814B(x, v)                                        \\\n\t(BIT_CLEAR_TXQ_NAV_MSK_8814B(x) | BIT_TXQ_NAV_MSK_8814B(v))\n\n#define BIT_DIS_CW_8814B BIT(7)\n#define BIT_NAV_END_TXOP_8814B BIT(6)\n#define BIT_RDG_END_TXOP_8814B BIT(5)\n#define BIT_AC_INBCN_HOLD_8814B BIT(4)\n#define BIT_MGTQ_TXOP_EN_8814B BIT(3)\n#define BIT_MGTQ_RTSMF_EN_8814B BIT(2)\n#define BIT_HIQ_RTSMF_EN_8814B BIT(1)\n#define BIT_BCN_RTSMF_EN_8814B BIT(0)\n\n/* 2 REG_TXPAUSE_8814B */\n#define BIT_STOP_BCN_HI_MGT_8814B BIT(7)\n#define BIT_MAC_STOPBCNQ_8814B BIT(6)\n#define BIT_MAC_STOPHIQ_8814B BIT(5)\n#define BIT_MAC_STOPMGQ_8814B BIT(4)\n#define BIT_MAC_STOPBK_8814B BIT(3)\n#define BIT_MAC_STOPBE_8814B BIT(2)\n#define BIT_MAC_STOPVI_8814B BIT(1)\n#define BIT_MAC_STOPVO_8814B BIT(0)\n\n/* 2 REG_DIS_TXREQ_CLR_8814B */\n#define BIT_DIS_BT_CCA_8814B BIT(7)\n#define BIT_DIS_TXREQ_CLR_HI_8814B BIT(5)\n#define BIT_DIS_TXREQ_CLR_MGQ_8814B BIT(4)\n#define BIT_DIS_TXREQ_CLR_VO_8814B BIT(3)\n#define BIT_DIS_TXREQ_CLR_VI_8814B BIT(2)\n#define BIT_DIS_TXREQ_CLR_BE_8814B BIT(1)\n#define BIT_DIS_TXREQ_CLR_BK_8814B BIT(0)\n\n/* 2 REG_RD_CTRL_8814B */\n#define BIT_EN_CLR_TXREQ_INCCA_8814B BIT(15)\n#define BIT_DIS_TX_OVER_BCNQ_8814B BIT(14)\n#define BIT_EN_BCNERR_INCCCA_8814B BIT(13)\n#define BIT_EDCCA_MSK_CNTDOWN_EN_8814B BIT(11)\n#define BIT_DIS_TXOP_CFE_8814B BIT(10)\n#define BIT_DIS_LSIG_CFE_8814B BIT(9)\n#define BIT_BKQ_RD_INIT_EN_8814B BIT(7)\n#define BIT_BEQ_RD_INIT_EN_8814B BIT(6)\n#define BIT_VIQ_RD_INIT_EN_8814B BIT(5)\n#define BIT_VOQ_RD_INIT_EN_8814B BIT(4)\n#define BIT_BKQ_RD_RESP_EN_8814B BIT(3)\n#define BIT_BEQ_RD_RESP_EN_8814B BIT(2)\n#define BIT_VIQ_RD_RESP_EN_8814B BIT(1)\n#define BIT_VOQ_RD_RESP_EN_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_PKT_LIFETIME_CTRL_8814B */\n#define BIT_EN_P2P_CTWND1_8814B BIT(23)\n#define BIT_EN_BKF_CLR_TXREQ_8814B BIT(22)\n#define BIT_EN_BCN_TX_BTCCA_8814B BIT(20)\n#define BIT_DIS_PKT_TX_ATIM_8814B BIT(19)\n#define BIT_DIS_BCN_DIS_CTN_8814B BIT(18)\n#define BIT_EN_NAVEND_RST_TXOP_8814B BIT(17)\n#define BIT_EN_FILTER_CCA_8814B BIT(16)\n\n#define BIT_SHIFT_CCA_FILTER_THRS_8814B 8\n#define BIT_MASK_CCA_FILTER_THRS_8814B 0xff\n#define BIT_CCA_FILTER_THRS_8814B(x)                                           \\\n\t(((x) & BIT_MASK_CCA_FILTER_THRS_8814B)                                \\\n\t << BIT_SHIFT_CCA_FILTER_THRS_8814B)\n#define BITS_CCA_FILTER_THRS_8814B                                             \\\n\t(BIT_MASK_CCA_FILTER_THRS_8814B << BIT_SHIFT_CCA_FILTER_THRS_8814B)\n#define BIT_CLEAR_CCA_FILTER_THRS_8814B(x) ((x) & (~BITS_CCA_FILTER_THRS_8814B))\n#define BIT_GET_CCA_FILTER_THRS_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_CCA_FILTER_THRS_8814B) &                            \\\n\t BIT_MASK_CCA_FILTER_THRS_8814B)\n#define BIT_SET_CCA_FILTER_THRS_8814B(x, v)                                    \\\n\t(BIT_CLEAR_CCA_FILTER_THRS_8814B(x) | BIT_CCA_FILTER_THRS_8814B(v))\n\n#define BIT_SHIFT_EDCCA_THRS_8814B 0\n#define BIT_MASK_EDCCA_THRS_8814B 0xff\n#define BIT_EDCCA_THRS_8814B(x)                                                \\\n\t(((x) & BIT_MASK_EDCCA_THRS_8814B) << BIT_SHIFT_EDCCA_THRS_8814B)\n#define BITS_EDCCA_THRS_8814B                                                  \\\n\t(BIT_MASK_EDCCA_THRS_8814B << BIT_SHIFT_EDCCA_THRS_8814B)\n#define BIT_CLEAR_EDCCA_THRS_8814B(x) ((x) & (~BITS_EDCCA_THRS_8814B))\n#define BIT_GET_EDCCA_THRS_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_EDCCA_THRS_8814B) & BIT_MASK_EDCCA_THRS_8814B)\n#define BIT_SET_EDCCA_THRS_8814B(x, v)                                         \\\n\t(BIT_CLEAR_EDCCA_THRS_8814B(x) | BIT_EDCCA_THRS_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_TXOP_LIMIT_CTRL_8814B */\n\n#define BIT_SHIFT_TXOP_TBTT_CNT_8814B 24\n#define BIT_MASK_TXOP_TBTT_CNT_8814B 0xff\n#define BIT_TXOP_TBTT_CNT_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TXOP_TBTT_CNT_8814B) << BIT_SHIFT_TXOP_TBTT_CNT_8814B)\n#define BITS_TXOP_TBTT_CNT_8814B                                               \\\n\t(BIT_MASK_TXOP_TBTT_CNT_8814B << BIT_SHIFT_TXOP_TBTT_CNT_8814B)\n#define BIT_CLEAR_TXOP_TBTT_CNT_8814B(x) ((x) & (~BITS_TXOP_TBTT_CNT_8814B))\n#define BIT_GET_TXOP_TBTT_CNT_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXOP_TBTT_CNT_8814B) & BIT_MASK_TXOP_TBTT_CNT_8814B)\n#define BIT_SET_TXOP_TBTT_CNT_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TXOP_TBTT_CNT_8814B(x) | BIT_TXOP_TBTT_CNT_8814B(v))\n\n#define BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B 20\n#define BIT_MASK_TXOP_TBTT_CNT_SEL_8814B 0xf\n#define BIT_TXOP_TBTT_CNT_SEL_8814B(x)                                         \\\n\t(((x) & BIT_MASK_TXOP_TBTT_CNT_SEL_8814B)                              \\\n\t << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B)\n#define BITS_TXOP_TBTT_CNT_SEL_8814B                                           \\\n\t(BIT_MASK_TXOP_TBTT_CNT_SEL_8814B << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B)\n#define BIT_CLEAR_TXOP_TBTT_CNT_SEL_8814B(x)                                   \\\n\t((x) & (~BITS_TXOP_TBTT_CNT_SEL_8814B))\n#define BIT_GET_TXOP_TBTT_CNT_SEL_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B) &                          \\\n\t BIT_MASK_TXOP_TBTT_CNT_SEL_8814B)\n#define BIT_SET_TXOP_TBTT_CNT_SEL_8814B(x, v)                                  \\\n\t(BIT_CLEAR_TXOP_TBTT_CNT_SEL_8814B(x) | BIT_TXOP_TBTT_CNT_SEL_8814B(v))\n\n#define BIT_SHIFT_TXOP_LMT_EN_8814B 16\n#define BIT_MASK_TXOP_LMT_EN_8814B 0xf\n#define BIT_TXOP_LMT_EN_8814B(x)                                               \\\n\t(((x) & BIT_MASK_TXOP_LMT_EN_8814B) << BIT_SHIFT_TXOP_LMT_EN_8814B)\n#define BITS_TXOP_LMT_EN_8814B                                                 \\\n\t(BIT_MASK_TXOP_LMT_EN_8814B << BIT_SHIFT_TXOP_LMT_EN_8814B)\n#define BIT_CLEAR_TXOP_LMT_EN_8814B(x) ((x) & (~BITS_TXOP_LMT_EN_8814B))\n#define BIT_GET_TXOP_LMT_EN_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_TXOP_LMT_EN_8814B) & BIT_MASK_TXOP_LMT_EN_8814B)\n#define BIT_SET_TXOP_LMT_EN_8814B(x, v)                                        \\\n\t(BIT_CLEAR_TXOP_LMT_EN_8814B(x) | BIT_TXOP_LMT_EN_8814B(v))\n\n#define BIT_SHIFT_TXOP_LMT_TX_TIME_8814B 8\n#define BIT_MASK_TXOP_LMT_TX_TIME_8814B 0xff\n#define BIT_TXOP_LMT_TX_TIME_8814B(x)                                          \\\n\t(((x) & BIT_MASK_TXOP_LMT_TX_TIME_8814B)                               \\\n\t << BIT_SHIFT_TXOP_LMT_TX_TIME_8814B)\n#define BITS_TXOP_LMT_TX_TIME_8814B                                            \\\n\t(BIT_MASK_TXOP_LMT_TX_TIME_8814B << BIT_SHIFT_TXOP_LMT_TX_TIME_8814B)\n#define BIT_CLEAR_TXOP_LMT_TX_TIME_8814B(x)                                    \\\n\t((x) & (~BITS_TXOP_LMT_TX_TIME_8814B))\n#define BIT_GET_TXOP_LMT_TX_TIME_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME_8814B) &                           \\\n\t BIT_MASK_TXOP_LMT_TX_TIME_8814B)\n#define BIT_SET_TXOP_LMT_TX_TIME_8814B(x, v)                                   \\\n\t(BIT_CLEAR_TXOP_LMT_TX_TIME_8814B(x) | BIT_TXOP_LMT_TX_TIME_8814B(v))\n\n#define BIT_TXOP_CNT_TRIGGER_RESET_8814B BIT(7)\n\n#define BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B 0\n#define BIT_MASK_TXOP_LMT_PKT_NUM_8814B 0x3f\n#define BIT_TXOP_LMT_PKT_NUM_8814B(x)                                          \\\n\t(((x) & BIT_MASK_TXOP_LMT_PKT_NUM_8814B)                               \\\n\t << BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B)\n#define BITS_TXOP_LMT_PKT_NUM_8814B                                            \\\n\t(BIT_MASK_TXOP_LMT_PKT_NUM_8814B << BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B)\n#define BIT_CLEAR_TXOP_LMT_PKT_NUM_8814B(x)                                    \\\n\t((x) & (~BITS_TXOP_LMT_PKT_NUM_8814B))\n#define BIT_GET_TXOP_LMT_PKT_NUM_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B) &                           \\\n\t BIT_MASK_TXOP_LMT_PKT_NUM_8814B)\n#define BIT_SET_TXOP_LMT_PKT_NUM_8814B(x, v)                                   \\\n\t(BIT_CLEAR_TXOP_LMT_PKT_NUM_8814B(x) | BIT_TXOP_LMT_PKT_NUM_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_CCA_TXEN_CNT_8814B */\n#define BIT_CCA_TXEN_CNT_SWITCH_8814B BIT(17)\n#define BIT_CCA_TXEN_CNT_EN_8814B BIT(16)\n\n#define BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B 8\n#define BIT_MASK_CCA_TXEN_BIG_CNT_8814B 0xff\n#define BIT_CCA_TXEN_BIG_CNT_8814B(x)                                          \\\n\t(((x) & BIT_MASK_CCA_TXEN_BIG_CNT_8814B)                               \\\n\t << BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B)\n#define BITS_CCA_TXEN_BIG_CNT_8814B                                            \\\n\t(BIT_MASK_CCA_TXEN_BIG_CNT_8814B << BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B)\n#define BIT_CLEAR_CCA_TXEN_BIG_CNT_8814B(x)                                    \\\n\t((x) & (~BITS_CCA_TXEN_BIG_CNT_8814B))\n#define BIT_GET_CCA_TXEN_BIG_CNT_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B) &                           \\\n\t BIT_MASK_CCA_TXEN_BIG_CNT_8814B)\n#define BIT_SET_CCA_TXEN_BIG_CNT_8814B(x, v)                                   \\\n\t(BIT_CLEAR_CCA_TXEN_BIG_CNT_8814B(x) | BIT_CCA_TXEN_BIG_CNT_8814B(v))\n\n#define BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B 0\n#define BIT_MASK_CCA_TXEN_SMALL_CNT_8814B 0xff\n#define BIT_CCA_TXEN_SMALL_CNT_8814B(x)                                        \\\n\t(((x) & BIT_MASK_CCA_TXEN_SMALL_CNT_8814B)                             \\\n\t << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B)\n#define BITS_CCA_TXEN_SMALL_CNT_8814B                                          \\\n\t(BIT_MASK_CCA_TXEN_SMALL_CNT_8814B                                     \\\n\t << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B)\n#define BIT_CLEAR_CCA_TXEN_SMALL_CNT_8814B(x)                                  \\\n\t((x) & (~BITS_CCA_TXEN_SMALL_CNT_8814B))\n#define BIT_GET_CCA_TXEN_SMALL_CNT_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B) &                         \\\n\t BIT_MASK_CCA_TXEN_SMALL_CNT_8814B)\n#define BIT_SET_CCA_TXEN_SMALL_CNT_8814B(x, v)                                 \\\n\t(BIT_CLEAR_CCA_TXEN_SMALL_CNT_8814B(x) |                               \\\n\t BIT_CCA_TXEN_SMALL_CNT_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_MAX_INTER_COLLISION_8814B */\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B 24\n#define BIT_MASK_MAX_INTER_COLLISION_BK_8814B 0xff\n#define BIT_MAX_INTER_COLLISION_BK_8814B(x)                                    \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_BK_8814B)                         \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B)\n#define BITS_MAX_INTER_COLLISION_BK_8814B                                      \\\n\t(BIT_MASK_MAX_INTER_COLLISION_BK_8814B                                 \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B)\n#define BIT_CLEAR_MAX_INTER_COLLISION_BK_8814B(x)                              \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_BK_8814B))\n#define BIT_GET_MAX_INTER_COLLISION_BK_8814B(x)                                \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B) &                     \\\n\t BIT_MASK_MAX_INTER_COLLISION_BK_8814B)\n#define BIT_SET_MAX_INTER_COLLISION_BK_8814B(x, v)                             \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_BK_8814B(x) |                           \\\n\t BIT_MAX_INTER_COLLISION_BK_8814B(v))\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B 16\n#define BIT_MASK_MAX_INTER_COLLISION_BE_8814B 0xff\n#define BIT_MAX_INTER_COLLISION_BE_8814B(x)                                    \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_BE_8814B)                         \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B)\n#define BITS_MAX_INTER_COLLISION_BE_8814B                                      \\\n\t(BIT_MASK_MAX_INTER_COLLISION_BE_8814B                                 \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B)\n#define BIT_CLEAR_MAX_INTER_COLLISION_BE_8814B(x)                              \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_BE_8814B))\n#define BIT_GET_MAX_INTER_COLLISION_BE_8814B(x)                                \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B) &                     \\\n\t BIT_MASK_MAX_INTER_COLLISION_BE_8814B)\n#define BIT_SET_MAX_INTER_COLLISION_BE_8814B(x, v)                             \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_BE_8814B(x) |                           \\\n\t BIT_MAX_INTER_COLLISION_BE_8814B(v))\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B 8\n#define BIT_MASK_MAX_INTER_COLLISION_VI_8814B 0xff\n#define BIT_MAX_INTER_COLLISION_VI_8814B(x)                                    \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_VI_8814B)                         \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B)\n#define BITS_MAX_INTER_COLLISION_VI_8814B                                      \\\n\t(BIT_MASK_MAX_INTER_COLLISION_VI_8814B                                 \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B)\n#define BIT_CLEAR_MAX_INTER_COLLISION_VI_8814B(x)                              \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_VI_8814B))\n#define BIT_GET_MAX_INTER_COLLISION_VI_8814B(x)                                \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B) &                     \\\n\t BIT_MASK_MAX_INTER_COLLISION_VI_8814B)\n#define BIT_SET_MAX_INTER_COLLISION_VI_8814B(x, v)                             \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_VI_8814B(x) |                           \\\n\t BIT_MAX_INTER_COLLISION_VI_8814B(v))\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B 0\n#define BIT_MASK_MAX_INTER_COLLISION_VO_8814B 0xff\n#define BIT_MAX_INTER_COLLISION_VO_8814B(x)                                    \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_VO_8814B)                         \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B)\n#define BITS_MAX_INTER_COLLISION_VO_8814B                                      \\\n\t(BIT_MASK_MAX_INTER_COLLISION_VO_8814B                                 \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B)\n#define BIT_CLEAR_MAX_INTER_COLLISION_VO_8814B(x)                              \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_VO_8814B))\n#define BIT_GET_MAX_INTER_COLLISION_VO_8814B(x)                                \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B) &                     \\\n\t BIT_MASK_MAX_INTER_COLLISION_VO_8814B)\n#define BIT_SET_MAX_INTER_COLLISION_VO_8814B(x, v)                             \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_VO_8814B(x) |                           \\\n\t BIT_MAX_INTER_COLLISION_VO_8814B(v))\n\n/* 2 REG_MAX_INTER_COLLISION_CNT_8814B */\n#define BIT_MAX_INTER_COLLISION_EN_8814B BIT(16)\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B 12\n#define BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B 0xf\n#define BIT_MAX_INTER_COLLISION_CNT_BK_8814B(x)                                \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B)                     \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B)\n#define BITS_MAX_INTER_COLLISION_CNT_BK_8814B                                  \\\n\t(BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B                             \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B)\n#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8814B(x)                          \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_CNT_BK_8814B))\n#define BIT_GET_MAX_INTER_COLLISION_CNT_BK_8814B(x)                            \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B) &                 \\\n\t BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B)\n#define BIT_SET_MAX_INTER_COLLISION_CNT_BK_8814B(x, v)                         \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8814B(x) |                       \\\n\t BIT_MAX_INTER_COLLISION_CNT_BK_8814B(v))\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B 8\n#define BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B 0xf\n#define BIT_MAX_INTER_COLLISION_CNT_BE_8814B(x)                                \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B)                     \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B)\n#define BITS_MAX_INTER_COLLISION_CNT_BE_8814B                                  \\\n\t(BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B                             \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B)\n#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8814B(x)                          \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_CNT_BE_8814B))\n#define BIT_GET_MAX_INTER_COLLISION_CNT_BE_8814B(x)                            \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B) &                 \\\n\t BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B)\n#define BIT_SET_MAX_INTER_COLLISION_CNT_BE_8814B(x, v)                         \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8814B(x) |                       \\\n\t BIT_MAX_INTER_COLLISION_CNT_BE_8814B(v))\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B 4\n#define BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B 0xf\n#define BIT_MAX_INTER_COLLISION_CNT_VI_8814B(x)                                \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B)                     \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B)\n#define BITS_MAX_INTER_COLLISION_CNT_VI_8814B                                  \\\n\t(BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B                             \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B)\n#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8814B(x)                          \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_CNT_VI_8814B))\n#define BIT_GET_MAX_INTER_COLLISION_CNT_VI_8814B(x)                            \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B) &                 \\\n\t BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B)\n#define BIT_SET_MAX_INTER_COLLISION_CNT_VI_8814B(x, v)                         \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8814B(x) |                       \\\n\t BIT_MAX_INTER_COLLISION_CNT_VI_8814B(v))\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B 0\n#define BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B 0xf\n#define BIT_MAX_INTER_COLLISION_CNT_VO_8814B(x)                                \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B)                     \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B)\n#define BITS_MAX_INTER_COLLISION_CNT_VO_8814B                                  \\\n\t(BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B                             \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B)\n#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8814B(x)                          \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_CNT_VO_8814B))\n#define BIT_GET_MAX_INTER_COLLISION_CNT_VO_8814B(x)                            \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B) &                 \\\n\t BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B)\n#define BIT_SET_MAX_INTER_COLLISION_CNT_VO_8814B(x, v)                         \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8814B(x) |                       \\\n\t BIT_MAX_INTER_COLLISION_CNT_VO_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_RD_NAV_NXT_8814B */\n\n#define BIT_SHIFT_RD_NAV_PROT_NXT_8814B 0\n#define BIT_MASK_RD_NAV_PROT_NXT_8814B 0xffff\n#define BIT_RD_NAV_PROT_NXT_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RD_NAV_PROT_NXT_8814B)                                \\\n\t << BIT_SHIFT_RD_NAV_PROT_NXT_8814B)\n#define BITS_RD_NAV_PROT_NXT_8814B                                             \\\n\t(BIT_MASK_RD_NAV_PROT_NXT_8814B << BIT_SHIFT_RD_NAV_PROT_NXT_8814B)\n#define BIT_CLEAR_RD_NAV_PROT_NXT_8814B(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8814B))\n#define BIT_GET_RD_NAV_PROT_NXT_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8814B) &                            \\\n\t BIT_MASK_RD_NAV_PROT_NXT_8814B)\n#define BIT_SET_RD_NAV_PROT_NXT_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RD_NAV_PROT_NXT_8814B(x) | BIT_RD_NAV_PROT_NXT_8814B(v))\n\n/* 2 REG_NAV_PROT_LEN_8814B */\n\n#define BIT_SHIFT_NAV_PROT_LEN_8814B 0\n#define BIT_MASK_NAV_PROT_LEN_8814B 0xffff\n#define BIT_NAV_PROT_LEN_8814B(x)                                              \\\n\t(((x) & BIT_MASK_NAV_PROT_LEN_8814B) << BIT_SHIFT_NAV_PROT_LEN_8814B)\n#define BITS_NAV_PROT_LEN_8814B                                                \\\n\t(BIT_MASK_NAV_PROT_LEN_8814B << BIT_SHIFT_NAV_PROT_LEN_8814B)\n#define BIT_CLEAR_NAV_PROT_LEN_8814B(x) ((x) & (~BITS_NAV_PROT_LEN_8814B))\n#define BIT_GET_NAV_PROT_LEN_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_NAV_PROT_LEN_8814B) & BIT_MASK_NAV_PROT_LEN_8814B)\n#define BIT_SET_NAV_PROT_LEN_8814B(x, v)                                       \\\n\t(BIT_CLEAR_NAV_PROT_LEN_8814B(x) | BIT_NAV_PROT_LEN_8814B(v))\n\n/* 2 REG_FTM_PTT_8814B */\n\n#define BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B 22\n#define BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B 0x7\n#define BIT_FTM_PTT_TSF_R2T_SEL_8814B(x)                                       \\\n\t(((x) & BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B)                            \\\n\t << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B)\n#define BITS_FTM_PTT_TSF_R2T_SEL_8814B                                         \\\n\t(BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B                                    \\\n\t << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B)\n#define BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8814B(x)                                 \\\n\t((x) & (~BITS_FTM_PTT_TSF_R2T_SEL_8814B))\n#define BIT_GET_FTM_PTT_TSF_R2T_SEL_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B) &                        \\\n\t BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B)\n#define BIT_SET_FTM_PTT_TSF_R2T_SEL_8814B(x, v)                                \\\n\t(BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8814B(x) |                              \\\n\t BIT_FTM_PTT_TSF_R2T_SEL_8814B(v))\n\n#define BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B 19\n#define BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B 0x7\n#define BIT_FTM_PTT_TSF_T2R_SEL_8814B(x)                                       \\\n\t(((x) & BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B)                            \\\n\t << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B)\n#define BITS_FTM_PTT_TSF_T2R_SEL_8814B                                         \\\n\t(BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B                                    \\\n\t << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B)\n#define BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8814B(x)                                 \\\n\t((x) & (~BITS_FTM_PTT_TSF_T2R_SEL_8814B))\n#define BIT_GET_FTM_PTT_TSF_T2R_SEL_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B) &                        \\\n\t BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B)\n#define BIT_SET_FTM_PTT_TSF_T2R_SEL_8814B(x, v)                                \\\n\t(BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8814B(x) |                              \\\n\t BIT_FTM_PTT_TSF_T2R_SEL_8814B(v))\n\n#define BIT_SHIFT_FTM_PTT_TSF_SEL_8814B 16\n#define BIT_MASK_FTM_PTT_TSF_SEL_8814B 0x7\n#define BIT_FTM_PTT_TSF_SEL_8814B(x)                                           \\\n\t(((x) & BIT_MASK_FTM_PTT_TSF_SEL_8814B)                                \\\n\t << BIT_SHIFT_FTM_PTT_TSF_SEL_8814B)\n#define BITS_FTM_PTT_TSF_SEL_8814B                                             \\\n\t(BIT_MASK_FTM_PTT_TSF_SEL_8814B << BIT_SHIFT_FTM_PTT_TSF_SEL_8814B)\n#define BIT_CLEAR_FTM_PTT_TSF_SEL_8814B(x) ((x) & (~BITS_FTM_PTT_TSF_SEL_8814B))\n#define BIT_GET_FTM_PTT_TSF_SEL_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_FTM_PTT_TSF_SEL_8814B) &                            \\\n\t BIT_MASK_FTM_PTT_TSF_SEL_8814B)\n#define BIT_SET_FTM_PTT_TSF_SEL_8814B(x, v)                                    \\\n\t(BIT_CLEAR_FTM_PTT_TSF_SEL_8814B(x) | BIT_FTM_PTT_TSF_SEL_8814B(v))\n\n#define BIT_SHIFT_FTM_PTT_VALUE_8814B 0\n#define BIT_MASK_FTM_PTT_VALUE_8814B 0xffff\n#define BIT_FTM_PTT_VALUE_8814B(x)                                             \\\n\t(((x) & BIT_MASK_FTM_PTT_VALUE_8814B) << BIT_SHIFT_FTM_PTT_VALUE_8814B)\n#define BITS_FTM_PTT_VALUE_8814B                                               \\\n\t(BIT_MASK_FTM_PTT_VALUE_8814B << BIT_SHIFT_FTM_PTT_VALUE_8814B)\n#define BIT_CLEAR_FTM_PTT_VALUE_8814B(x) ((x) & (~BITS_FTM_PTT_VALUE_8814B))\n#define BIT_GET_FTM_PTT_VALUE_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_FTM_PTT_VALUE_8814B) & BIT_MASK_FTM_PTT_VALUE_8814B)\n#define BIT_SET_FTM_PTT_VALUE_8814B(x, v)                                      \\\n\t(BIT_CLEAR_FTM_PTT_VALUE_8814B(x) | BIT_FTM_PTT_VALUE_8814B(v))\n\n/* 2 REG_FTM_TSF_8814B */\n\n#define BIT_SHIFT_FTM_T2_TSF_8814B 16\n#define BIT_MASK_FTM_T2_TSF_8814B 0xffff\n#define BIT_FTM_T2_TSF_8814B(x)                                                \\\n\t(((x) & BIT_MASK_FTM_T2_TSF_8814B) << BIT_SHIFT_FTM_T2_TSF_8814B)\n#define BITS_FTM_T2_TSF_8814B                                                  \\\n\t(BIT_MASK_FTM_T2_TSF_8814B << BIT_SHIFT_FTM_T2_TSF_8814B)\n#define BIT_CLEAR_FTM_T2_TSF_8814B(x) ((x) & (~BITS_FTM_T2_TSF_8814B))\n#define BIT_GET_FTM_T2_TSF_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_FTM_T2_TSF_8814B) & BIT_MASK_FTM_T2_TSF_8814B)\n#define BIT_SET_FTM_T2_TSF_8814B(x, v)                                         \\\n\t(BIT_CLEAR_FTM_T2_TSF_8814B(x) | BIT_FTM_T2_TSF_8814B(v))\n\n#define BIT_SHIFT_FTM_T1_TSF_8814B 0\n#define BIT_MASK_FTM_T1_TSF_8814B 0xffff\n#define BIT_FTM_T1_TSF_8814B(x)                                                \\\n\t(((x) & BIT_MASK_FTM_T1_TSF_8814B) << BIT_SHIFT_FTM_T1_TSF_8814B)\n#define BITS_FTM_T1_TSF_8814B                                                  \\\n\t(BIT_MASK_FTM_T1_TSF_8814B << BIT_SHIFT_FTM_T1_TSF_8814B)\n#define BIT_CLEAR_FTM_T1_TSF_8814B(x) ((x) & (~BITS_FTM_T1_TSF_8814B))\n#define BIT_GET_FTM_T1_TSF_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_FTM_T1_TSF_8814B) & BIT_MASK_FTM_T1_TSF_8814B)\n#define BIT_SET_FTM_T1_TSF_8814B(x, v)                                         \\\n\t(BIT_CLEAR_FTM_T1_TSF_8814B(x) | BIT_FTM_T1_TSF_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_HGQ_TIMEOUT_PERIOD_8814B */\n\n#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B 0\n#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B 0xff\n#define BIT_HGQ_TIMEOUT_PERIOD_8814B(x)                                        \\\n\t(((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B)                             \\\n\t << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B)\n#define BITS_HGQ_TIMEOUT_PERIOD_8814B                                          \\\n\t(BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B                                     \\\n\t << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B)\n#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8814B(x)                                  \\\n\t((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8814B))\n#define BIT_GET_HGQ_TIMEOUT_PERIOD_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B) &                         \\\n\t BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B)\n#define BIT_SET_HGQ_TIMEOUT_PERIOD_8814B(x, v)                                 \\\n\t(BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8814B(x) |                               \\\n\t BIT_HGQ_TIMEOUT_PERIOD_8814B(v))\n\n/* 2 REG_TXCMD_TIMEOUT_PERIOD_8814B */\n\n#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B 0\n#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B 0xff\n#define BIT_TXCMD_TIMEOUT_PERIOD_8814B(x)                                      \\\n\t(((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B)                           \\\n\t << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B)\n#define BITS_TXCMD_TIMEOUT_PERIOD_8814B                                        \\\n\t(BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B                                   \\\n\t << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B)\n#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8814B(x)                                \\\n\t((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8814B))\n#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B) &                       \\\n\t BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B)\n#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8814B(x, v)                               \\\n\t(BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8814B(x) |                             \\\n\t BIT_TXCMD_TIMEOUT_PERIOD_8814B(v))\n\n/* 2 REG_MISC_CTRL_8814B */\n#define BIT_DIS_SECONDARY_CCA_80M_8814B BIT(2)\n#define BIT_DIS_SECONDARY_CCA_40M_8814B BIT(1)\n#define BIT_DIS_SECONDARY_CCA_20M_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_TXOP_MIN_8814B */\n#define BIT_HIQ_NAV_BREAK_EN_8814B BIT(15)\n#define BIT_MGQ_NAV_BREAK_EN_8814B BIT(14)\n\n#define BIT_SHIFT_TXOP_MIN_8814B 0\n#define BIT_MASK_TXOP_MIN_8814B 0x3fff\n#define BIT_TXOP_MIN_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_TXOP_MIN_8814B) << BIT_SHIFT_TXOP_MIN_8814B)\n#define BITS_TXOP_MIN_8814B                                                    \\\n\t(BIT_MASK_TXOP_MIN_8814B << BIT_SHIFT_TXOP_MIN_8814B)\n#define BIT_CLEAR_TXOP_MIN_8814B(x) ((x) & (~BITS_TXOP_MIN_8814B))\n#define BIT_GET_TXOP_MIN_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXOP_MIN_8814B) & BIT_MASK_TXOP_MIN_8814B)\n#define BIT_SET_TXOP_MIN_8814B(x, v)                                           \\\n\t(BIT_CLEAR_TXOP_MIN_8814B(x) | BIT_TXOP_MIN_8814B(v))\n\n/* 2 REG_PRE_BKF_TIME_8814B */\n\n#define BIT_SHIFT_PRE_BKF_TIME_8814B 0\n#define BIT_MASK_PRE_BKF_TIME_8814B 0xff\n#define BIT_PRE_BKF_TIME_8814B(x)                                              \\\n\t(((x) & BIT_MASK_PRE_BKF_TIME_8814B) << BIT_SHIFT_PRE_BKF_TIME_8814B)\n#define BITS_PRE_BKF_TIME_8814B                                                \\\n\t(BIT_MASK_PRE_BKF_TIME_8814B << BIT_SHIFT_PRE_BKF_TIME_8814B)\n#define BIT_CLEAR_PRE_BKF_TIME_8814B(x) ((x) & (~BITS_PRE_BKF_TIME_8814B))\n#define BIT_GET_PRE_BKF_TIME_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_PRE_BKF_TIME_8814B) & BIT_MASK_PRE_BKF_TIME_8814B)\n#define BIT_SET_PRE_BKF_TIME_8814B(x, v)                                       \\\n\t(BIT_CLEAR_PRE_BKF_TIME_8814B(x) | BIT_PRE_BKF_TIME_8814B(v))\n\n/* 2 REG_CROSS_TXOP_CTRL_8814B */\n#define BIT_TBTT_RETRY_8814B BIT(4)\n#define BIT_TXFAIL_BREACK_TXOP_EN_8814B BIT(3)\n#define BIT_RTS_NAV_TXOP_8814B BIT(1)\n#define BIT_NOT_CROSS_TXOP_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_ACMHWCTRL_8814B */\n#define BIT_BEQ_ACM_STATUS_8814B BIT(7)\n#define BIT_VIQ_ACM_STATUS_8814B BIT(6)\n#define BIT_VOQ_ACM_STATUS_8814B BIT(5)\n#define BIT_BEQ_ACM_EN_8814B BIT(3)\n#define BIT_VIQ_ACM_EN_8814B BIT(2)\n#define BIT_VOQ_ACM_EN_8814B BIT(1)\n#define BIT_ACMHWEN_8814B BIT(0)\n\n/* 2 REG_ACMRSTCTRL_8814B */\n#define BIT_BE_ACM_RESET_USED_TIME_8814B BIT(2)\n#define BIT_VI_ACM_RESET_USED_TIME_8814B BIT(1)\n#define BIT_VO_ACM_RESET_USED_TIME_8814B BIT(0)\n\n/* 2 REG_ACMAVG_8814B */\n\n#define BIT_SHIFT_AVGPERIOD_8814B 0\n#define BIT_MASK_AVGPERIOD_8814B 0xffff\n#define BIT_AVGPERIOD_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_AVGPERIOD_8814B) << BIT_SHIFT_AVGPERIOD_8814B)\n#define BITS_AVGPERIOD_8814B                                                   \\\n\t(BIT_MASK_AVGPERIOD_8814B << BIT_SHIFT_AVGPERIOD_8814B)\n#define BIT_CLEAR_AVGPERIOD_8814B(x) ((x) & (~BITS_AVGPERIOD_8814B))\n#define BIT_GET_AVGPERIOD_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_AVGPERIOD_8814B) & BIT_MASK_AVGPERIOD_8814B)\n#define BIT_SET_AVGPERIOD_8814B(x, v)                                          \\\n\t(BIT_CLEAR_AVGPERIOD_8814B(x) | BIT_AVGPERIOD_8814B(v))\n\n/* 2 REG_VO_ADMTIME_8814B */\n\n#define BIT_SHIFT_VO_ADMITTED_TIME_8814B 0\n#define BIT_MASK_VO_ADMITTED_TIME_8814B 0xffff\n#define BIT_VO_ADMITTED_TIME_8814B(x)                                          \\\n\t(((x) & BIT_MASK_VO_ADMITTED_TIME_8814B)                               \\\n\t << BIT_SHIFT_VO_ADMITTED_TIME_8814B)\n#define BITS_VO_ADMITTED_TIME_8814B                                            \\\n\t(BIT_MASK_VO_ADMITTED_TIME_8814B << BIT_SHIFT_VO_ADMITTED_TIME_8814B)\n#define BIT_CLEAR_VO_ADMITTED_TIME_8814B(x)                                    \\\n\t((x) & (~BITS_VO_ADMITTED_TIME_8814B))\n#define BIT_GET_VO_ADMITTED_TIME_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8814B) &                           \\\n\t BIT_MASK_VO_ADMITTED_TIME_8814B)\n#define BIT_SET_VO_ADMITTED_TIME_8814B(x, v)                                   \\\n\t(BIT_CLEAR_VO_ADMITTED_TIME_8814B(x) | BIT_VO_ADMITTED_TIME_8814B(v))\n\n/* 2 REG_VI_ADMTIME_8814B */\n\n#define BIT_SHIFT_VI_ADMITTED_TIME_8814B 0\n#define BIT_MASK_VI_ADMITTED_TIME_8814B 0xffff\n#define BIT_VI_ADMITTED_TIME_8814B(x)                                          \\\n\t(((x) & BIT_MASK_VI_ADMITTED_TIME_8814B)                               \\\n\t << BIT_SHIFT_VI_ADMITTED_TIME_8814B)\n#define BITS_VI_ADMITTED_TIME_8814B                                            \\\n\t(BIT_MASK_VI_ADMITTED_TIME_8814B << BIT_SHIFT_VI_ADMITTED_TIME_8814B)\n#define BIT_CLEAR_VI_ADMITTED_TIME_8814B(x)                                    \\\n\t((x) & (~BITS_VI_ADMITTED_TIME_8814B))\n#define BIT_GET_VI_ADMITTED_TIME_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8814B) &                           \\\n\t BIT_MASK_VI_ADMITTED_TIME_8814B)\n#define BIT_SET_VI_ADMITTED_TIME_8814B(x, v)                                   \\\n\t(BIT_CLEAR_VI_ADMITTED_TIME_8814B(x) | BIT_VI_ADMITTED_TIME_8814B(v))\n\n/* 2 REG_BE_ADMTIME_8814B */\n\n#define BIT_SHIFT_BE_ADMITTED_TIME_8814B 0\n#define BIT_MASK_BE_ADMITTED_TIME_8814B 0xffff\n#define BIT_BE_ADMITTED_TIME_8814B(x)                                          \\\n\t(((x) & BIT_MASK_BE_ADMITTED_TIME_8814B)                               \\\n\t << BIT_SHIFT_BE_ADMITTED_TIME_8814B)\n#define BITS_BE_ADMITTED_TIME_8814B                                            \\\n\t(BIT_MASK_BE_ADMITTED_TIME_8814B << BIT_SHIFT_BE_ADMITTED_TIME_8814B)\n#define BIT_CLEAR_BE_ADMITTED_TIME_8814B(x)                                    \\\n\t((x) & (~BITS_BE_ADMITTED_TIME_8814B))\n#define BIT_GET_BE_ADMITTED_TIME_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8814B) &                           \\\n\t BIT_MASK_BE_ADMITTED_TIME_8814B)\n#define BIT_SET_BE_ADMITTED_TIME_8814B(x, v)                                   \\\n\t(BIT_CLEAR_BE_ADMITTED_TIME_8814B(x) | BIT_BE_ADMITTED_TIME_8814B(v))\n\n/* 2 REG_MAC_HEADER_NAV_OFFSET_8814B */\n\n#define BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B 0\n#define BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B 0xff\n#define BIT_MAC_HEADER_NAV_OFFSET_8814B(x)                                     \\\n\t(((x) & BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B)                          \\\n\t << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B)\n#define BITS_MAC_HEADER_NAV_OFFSET_8814B                                       \\\n\t(BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B                                  \\\n\t << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B)\n#define BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8814B(x)                               \\\n\t((x) & (~BITS_MAC_HEADER_NAV_OFFSET_8814B))\n#define BIT_GET_MAC_HEADER_NAV_OFFSET_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B) &                      \\\n\t BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B)\n#define BIT_SET_MAC_HEADER_NAV_OFFSET_8814B(x, v)                              \\\n\t(BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8814B(x) |                            \\\n\t BIT_MAC_HEADER_NAV_OFFSET_8814B(v))\n\n/* 2 REG_DIS_NDPA_NAV_CHECK_8814B */\n#define BIT_DIS_NDPA_NAV_CHECK_8814B BIT(0)\n\n/* 2 REG_EDCA_RANDOM_GEN_8814B */\n\n#define BIT_SHIFT_RANDOM_GEN_8814B 0\n#define BIT_MASK_RANDOM_GEN_8814B 0xffffff\n#define BIT_RANDOM_GEN_8814B(x)                                                \\\n\t(((x) & BIT_MASK_RANDOM_GEN_8814B) << BIT_SHIFT_RANDOM_GEN_8814B)\n#define BITS_RANDOM_GEN_8814B                                                  \\\n\t(BIT_MASK_RANDOM_GEN_8814B << BIT_SHIFT_RANDOM_GEN_8814B)\n#define BIT_CLEAR_RANDOM_GEN_8814B(x) ((x) & (~BITS_RANDOM_GEN_8814B))\n#define BIT_GET_RANDOM_GEN_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_RANDOM_GEN_8814B) & BIT_MASK_RANDOM_GEN_8814B)\n#define BIT_SET_RANDOM_GEN_8814B(x, v)                                         \\\n\t(BIT_CLEAR_RANDOM_GEN_8814B(x) | BIT_RANDOM_GEN_8814B(v))\n\n/* 2 REG_TXCMD_SEL_8814B */\n\n#define BIT_SHIFT_TXCMD_SEG_SEL_8814B 0\n#define BIT_MASK_TXCMD_SEG_SEL_8814B 0xf\n#define BIT_TXCMD_SEG_SEL_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TXCMD_SEG_SEL_8814B) << BIT_SHIFT_TXCMD_SEG_SEL_8814B)\n#define BITS_TXCMD_SEG_SEL_8814B                                               \\\n\t(BIT_MASK_TXCMD_SEG_SEL_8814B << BIT_SHIFT_TXCMD_SEG_SEL_8814B)\n#define BIT_CLEAR_TXCMD_SEG_SEL_8814B(x) ((x) & (~BITS_TXCMD_SEG_SEL_8814B))\n#define BIT_GET_TXCMD_SEG_SEL_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8814B) & BIT_MASK_TXCMD_SEG_SEL_8814B)\n#define BIT_SET_TXCMD_SEG_SEL_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TXCMD_SEG_SEL_8814B(x) | BIT_TXCMD_SEG_SEL_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_MU_DBG_INFO_8814B */\n\n#define BIT_SHIFT_MU_DBG_INFO_8814B 0\n#define BIT_MASK_MU_DBG_INFO_8814B 0xffffffffL\n#define BIT_MU_DBG_INFO_8814B(x)                                               \\\n\t(((x) & BIT_MASK_MU_DBG_INFO_8814B) << BIT_SHIFT_MU_DBG_INFO_8814B)\n#define BITS_MU_DBG_INFO_8814B                                                 \\\n\t(BIT_MASK_MU_DBG_INFO_8814B << BIT_SHIFT_MU_DBG_INFO_8814B)\n#define BIT_CLEAR_MU_DBG_INFO_8814B(x) ((x) & (~BITS_MU_DBG_INFO_8814B))\n#define BIT_GET_MU_DBG_INFO_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_MU_DBG_INFO_8814B) & BIT_MASK_MU_DBG_INFO_8814B)\n#define BIT_SET_MU_DBG_INFO_8814B(x, v)                                        \\\n\t(BIT_CLEAR_MU_DBG_INFO_8814B(x) | BIT_MU_DBG_INFO_8814B(v))\n\n/* 2 REG_MU_DBG_INFO_1_8814B */\n\n#define BIT_SHIFT_MU_DBG_INFO_1_8814B 0\n#define BIT_MASK_MU_DBG_INFO_1_8814B 0xffffffffL\n#define BIT_MU_DBG_INFO_1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_MU_DBG_INFO_1_8814B) << BIT_SHIFT_MU_DBG_INFO_1_8814B)\n#define BITS_MU_DBG_INFO_1_8814B                                               \\\n\t(BIT_MASK_MU_DBG_INFO_1_8814B << BIT_SHIFT_MU_DBG_INFO_1_8814B)\n#define BIT_CLEAR_MU_DBG_INFO_1_8814B(x) ((x) & (~BITS_MU_DBG_INFO_1_8814B))\n#define BIT_GET_MU_DBG_INFO_1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MU_DBG_INFO_1_8814B) & BIT_MASK_MU_DBG_INFO_1_8814B)\n#define BIT_SET_MU_DBG_INFO_1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_MU_DBG_INFO_1_8814B(x) | BIT_MU_DBG_INFO_1_8814B(v))\n\n/* 2 REG_SCH_DBG_SEL_8814B */\n\n#define BIT_SHIFT_SCH_DBG_SEL_8814B 0\n#define BIT_MASK_SCH_DBG_SEL_8814B 0xff\n#define BIT_SCH_DBG_SEL_8814B(x)                                               \\\n\t(((x) & BIT_MASK_SCH_DBG_SEL_8814B) << BIT_SHIFT_SCH_DBG_SEL_8814B)\n#define BITS_SCH_DBG_SEL_8814B                                                 \\\n\t(BIT_MASK_SCH_DBG_SEL_8814B << BIT_SHIFT_SCH_DBG_SEL_8814B)\n#define BIT_CLEAR_SCH_DBG_SEL_8814B(x) ((x) & (~BITS_SCH_DBG_SEL_8814B))\n#define BIT_GET_SCH_DBG_SEL_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_SCH_DBG_SEL_8814B) & BIT_MASK_SCH_DBG_SEL_8814B)\n#define BIT_SET_SCH_DBG_SEL_8814B(x, v)                                        \\\n\t(BIT_CLEAR_SCH_DBG_SEL_8814B(x) | BIT_SCH_DBG_SEL_8814B(v))\n\n/* 2 REG_SCHEDULER_RST_8814B */\n#define BIT_SCHEDULER_RST_V1_8814B BIT(0)\n\n/* 2 REG_MU_DBG_ERR_FLAG_8814B */\n#define BIT_BCN_PORTID_ERR_8814B BIT(2)\n\n#define BIT_SHIFT_MU_DBG_ERR_FLAG_8814B 0\n#define BIT_MASK_MU_DBG_ERR_FLAG_8814B 0x3\n#define BIT_MU_DBG_ERR_FLAG_8814B(x)                                           \\\n\t(((x) & BIT_MASK_MU_DBG_ERR_FLAG_8814B)                                \\\n\t << BIT_SHIFT_MU_DBG_ERR_FLAG_8814B)\n#define BITS_MU_DBG_ERR_FLAG_8814B                                             \\\n\t(BIT_MASK_MU_DBG_ERR_FLAG_8814B << BIT_SHIFT_MU_DBG_ERR_FLAG_8814B)\n#define BIT_CLEAR_MU_DBG_ERR_FLAG_8814B(x) ((x) & (~BITS_MU_DBG_ERR_FLAG_8814B))\n#define BIT_GET_MU_DBG_ERR_FLAG_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_MU_DBG_ERR_FLAG_8814B) &                            \\\n\t BIT_MASK_MU_DBG_ERR_FLAG_8814B)\n#define BIT_SET_MU_DBG_ERR_FLAG_8814B(x, v)                                    \\\n\t(BIT_CLEAR_MU_DBG_ERR_FLAG_8814B(x) | BIT_MU_DBG_ERR_FLAG_8814B(v))\n\n/* 2 REG_TX_ERR_RECOVERY_RST_8814B */\n\n#define BIT_SHIFT_ERR_RECOVER_CNT_8814B 4\n#define BIT_MASK_ERR_RECOVER_CNT_8814B 0xf\n#define BIT_ERR_RECOVER_CNT_8814B(x)                                           \\\n\t(((x) & BIT_MASK_ERR_RECOVER_CNT_8814B)                                \\\n\t << BIT_SHIFT_ERR_RECOVER_CNT_8814B)\n#define BITS_ERR_RECOVER_CNT_8814B                                             \\\n\t(BIT_MASK_ERR_RECOVER_CNT_8814B << BIT_SHIFT_ERR_RECOVER_CNT_8814B)\n#define BIT_CLEAR_ERR_RECOVER_CNT_8814B(x) ((x) & (~BITS_ERR_RECOVER_CNT_8814B))\n#define BIT_GET_ERR_RECOVER_CNT_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_ERR_RECOVER_CNT_8814B) &                            \\\n\t BIT_MASK_ERR_RECOVER_CNT_8814B)\n#define BIT_SET_ERR_RECOVER_CNT_8814B(x, v)                                    \\\n\t(BIT_CLEAR_ERR_RECOVER_CNT_8814B(x) | BIT_ERR_RECOVER_CNT_8814B(v))\n\n#define BIT_RX_HANG_ERR_8814B BIT(2)\n#define BIT_TX_HANG_ERR_8814B BIT(1)\n#define BIT_TX_ERR_RECOVERY_RST_8814B BIT(0)\n\n/* 2 REG_SCH_DBG_VALUE_8814B */\n\n#define BIT_SHIFT_SCH_DBG_VALUE_8814B 0\n#define BIT_MASK_SCH_DBG_VALUE_8814B 0xffffffffL\n#define BIT_SCH_DBG_VALUE_8814B(x)                                             \\\n\t(((x) & BIT_MASK_SCH_DBG_VALUE_8814B) << BIT_SHIFT_SCH_DBG_VALUE_8814B)\n#define BITS_SCH_DBG_VALUE_8814B                                               \\\n\t(BIT_MASK_SCH_DBG_VALUE_8814B << BIT_SHIFT_SCH_DBG_VALUE_8814B)\n#define BIT_CLEAR_SCH_DBG_VALUE_8814B(x) ((x) & (~BITS_SCH_DBG_VALUE_8814B))\n#define BIT_GET_SCH_DBG_VALUE_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SCH_DBG_VALUE_8814B) & BIT_MASK_SCH_DBG_VALUE_8814B)\n#define BIT_SET_SCH_DBG_VALUE_8814B(x, v)                                      \\\n\t(BIT_CLEAR_SCH_DBG_VALUE_8814B(x) | BIT_SCH_DBG_VALUE_8814B(v))\n\n/* 2 REG_SCH_TXCMD_8814B */\n\n#define BIT_SHIFT_SCH_TXCMD_8814B 0\n#define BIT_MASK_SCH_TXCMD_8814B 0xffffffffL\n#define BIT_SCH_TXCMD_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_SCH_TXCMD_8814B) << BIT_SHIFT_SCH_TXCMD_8814B)\n#define BITS_SCH_TXCMD_8814B                                                   \\\n\t(BIT_MASK_SCH_TXCMD_8814B << BIT_SHIFT_SCH_TXCMD_8814B)\n#define BIT_CLEAR_SCH_TXCMD_8814B(x) ((x) & (~BITS_SCH_TXCMD_8814B))\n#define BIT_GET_SCH_TXCMD_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_SCH_TXCMD_8814B) & BIT_MASK_SCH_TXCMD_8814B)\n#define BIT_SET_SCH_TXCMD_8814B(x, v)                                          \\\n\t(BIT_CLEAR_SCH_TXCMD_8814B(x) | BIT_SCH_TXCMD_8814B(v))\n\n/* 2 REG_PAGE5_DUMMY_8814B */\n\n/* 2 REG_PORT_CTRL_SEL_8814B */\n\n#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B 4\n#define BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B 0x7\n#define BIT_BCN_TIMER_SEL_FWRD_V1_8814B(x)                                     \\\n\t(((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B)                          \\\n\t << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B)\n#define BITS_BCN_TIMER_SEL_FWRD_V1_8814B                                       \\\n\t(BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B                                  \\\n\t << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B)\n#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1_8814B(x)                               \\\n\t((x) & (~BITS_BCN_TIMER_SEL_FWRD_V1_8814B))\n#define BIT_GET_BCN_TIMER_SEL_FWRD_V1_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B) &                      \\\n\t BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B)\n#define BIT_SET_BCN_TIMER_SEL_FWRD_V1_8814B(x, v)                              \\\n\t(BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1_8814B(x) |                            \\\n\t BIT_BCN_TIMER_SEL_FWRD_V1_8814B(v))\n\n#define BIT_SHIFT_PORT_CTRL_SEL_8814B 0\n#define BIT_MASK_PORT_CTRL_SEL_8814B 0x7\n#define BIT_PORT_CTRL_SEL_8814B(x)                                             \\\n\t(((x) & BIT_MASK_PORT_CTRL_SEL_8814B) << BIT_SHIFT_PORT_CTRL_SEL_8814B)\n#define BITS_PORT_CTRL_SEL_8814B                                               \\\n\t(BIT_MASK_PORT_CTRL_SEL_8814B << BIT_SHIFT_PORT_CTRL_SEL_8814B)\n#define BIT_CLEAR_PORT_CTRL_SEL_8814B(x) ((x) & (~BITS_PORT_CTRL_SEL_8814B))\n#define BIT_GET_PORT_CTRL_SEL_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PORT_CTRL_SEL_8814B) & BIT_MASK_PORT_CTRL_SEL_8814B)\n#define BIT_SET_PORT_CTRL_SEL_8814B(x, v)                                      \\\n\t(BIT_CLEAR_PORT_CTRL_SEL_8814B(x) | BIT_PORT_CTRL_SEL_8814B(v))\n\n/* 2 REG_PORT_CTRL_CFG_8814B */\n#define BIT_BCNERR_CNT_EN_V1_8814B BIT(11)\n#define BIT_DIS_TRX_CAL_BCN_V1_8814B BIT(10)\n#define BIT_DIS_TX_CAL_TBTT_V1_8814B BIT(9)\n#define BIT_BCN_AGGRESSION_V1_8814B BIT(8)\n#define BIT_TSFTR_RST_V1_8814B BIT(7)\n#define BIT_DIS_RX_BSSID_FIT_8814B BIT(6)\n#define BIT_EN_TXBCN_RPT_V1_8814B BIT(5)\n#define BIT_DIS_TSF_UDT_8814B BIT(4)\n#define BIT_EN_PORT_FUNCTION_8814B BIT(3)\n#define BIT_EN_RXBCN_RPT_8814B BIT(2)\n#define BIT_EN_P2P_CTWINDOW_8814B BIT(1)\n#define BIT_EN_P2P_BCNQ_AREA_8814B BIT(0)\n\n/* 2 REG_TBTT_PROHIBIT_CFG_8814B */\n#define BIT_MASK_PROHIBIT_8814B BIT(23)\n\n#define BIT_SHIFT_TBTT_HOLD_TIME_8814B 8\n#define BIT_MASK_TBTT_HOLD_TIME_8814B 0xfff\n#define BIT_TBTT_HOLD_TIME_8814B(x)                                            \\\n\t(((x) & BIT_MASK_TBTT_HOLD_TIME_8814B)                                 \\\n\t << BIT_SHIFT_TBTT_HOLD_TIME_8814B)\n#define BITS_TBTT_HOLD_TIME_8814B                                              \\\n\t(BIT_MASK_TBTT_HOLD_TIME_8814B << BIT_SHIFT_TBTT_HOLD_TIME_8814B)\n#define BIT_CLEAR_TBTT_HOLD_TIME_8814B(x) ((x) & (~BITS_TBTT_HOLD_TIME_8814B))\n#define BIT_GET_TBTT_HOLD_TIME_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_TBTT_HOLD_TIME_8814B) &                             \\\n\t BIT_MASK_TBTT_HOLD_TIME_8814B)\n#define BIT_SET_TBTT_HOLD_TIME_8814B(x, v)                                     \\\n\t(BIT_CLEAR_TBTT_HOLD_TIME_8814B(x) | BIT_TBTT_HOLD_TIME_8814B(v))\n\n#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B 0\n#define BIT_MASK_TBTT_PROHIBIT_SETUP_8814B 0xf\n#define BIT_TBTT_PROHIBIT_SETUP_8814B(x)                                       \\\n\t(((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8814B)                            \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B)\n#define BITS_TBTT_PROHIBIT_SETUP_8814B                                         \\\n\t(BIT_MASK_TBTT_PROHIBIT_SETUP_8814B                                    \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B)\n#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8814B(x)                                 \\\n\t((x) & (~BITS_TBTT_PROHIBIT_SETUP_8814B))\n#define BIT_GET_TBTT_PROHIBIT_SETUP_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B) &                        \\\n\t BIT_MASK_TBTT_PROHIBIT_SETUP_8814B)\n#define BIT_SET_TBTT_PROHIBIT_SETUP_8814B(x, v)                                \\\n\t(BIT_CLEAR_TBTT_PROHIBIT_SETUP_8814B(x) |                              \\\n\t BIT_TBTT_PROHIBIT_SETUP_8814B(v))\n\n/* 2 REG_DRVERLYINT_CFG_8814B */\n\n#define BIT_SHIFT_DRVERLYITV_8814B 0\n#define BIT_MASK_DRVERLYITV_8814B 0xff\n#define BIT_DRVERLYITV_8814B(x)                                                \\\n\t(((x) & BIT_MASK_DRVERLYITV_8814B) << BIT_SHIFT_DRVERLYITV_8814B)\n#define BITS_DRVERLYITV_8814B                                                  \\\n\t(BIT_MASK_DRVERLYITV_8814B << BIT_SHIFT_DRVERLYITV_8814B)\n#define BIT_CLEAR_DRVERLYITV_8814B(x) ((x) & (~BITS_DRVERLYITV_8814B))\n#define BIT_GET_DRVERLYITV_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DRVERLYITV_8814B) & BIT_MASK_DRVERLYITV_8814B)\n#define BIT_SET_DRVERLYITV_8814B(x, v)                                         \\\n\t(BIT_CLEAR_DRVERLYITV_8814B(x) | BIT_DRVERLYITV_8814B(v))\n\n/* 2 REG_BCNDMATIM_CFG_8814B */\n\n#define BIT_SHIFT_BCNDMATIM_8814B 0\n#define BIT_MASK_BCNDMATIM_8814B 0xff\n#define BIT_BCNDMATIM_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_BCNDMATIM_8814B) << BIT_SHIFT_BCNDMATIM_8814B)\n#define BITS_BCNDMATIM_8814B                                                   \\\n\t(BIT_MASK_BCNDMATIM_8814B << BIT_SHIFT_BCNDMATIM_8814B)\n#define BIT_CLEAR_BCNDMATIM_8814B(x) ((x) & (~BITS_BCNDMATIM_8814B))\n#define BIT_GET_BCNDMATIM_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNDMATIM_8814B) & BIT_MASK_BCNDMATIM_8814B)\n#define BIT_SET_BCNDMATIM_8814B(x, v)                                          \\\n\t(BIT_CLEAR_BCNDMATIM_8814B(x) | BIT_BCNDMATIM_8814B(v))\n\n/* 2 REG_CTWND_CFG_8814B */\n\n#define BIT_SHIFT_CTWND_8814B 0\n#define BIT_MASK_CTWND_8814B 0xff\n#define BIT_CTWND_8814B(x)                                                     \\\n\t(((x) & BIT_MASK_CTWND_8814B) << BIT_SHIFT_CTWND_8814B)\n#define BITS_CTWND_8814B (BIT_MASK_CTWND_8814B << BIT_SHIFT_CTWND_8814B)\n#define BIT_CLEAR_CTWND_8814B(x) ((x) & (~BITS_CTWND_8814B))\n#define BIT_GET_CTWND_8814B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CTWND_8814B) & BIT_MASK_CTWND_8814B)\n#define BIT_SET_CTWND_8814B(x, v)                                              \\\n\t(BIT_CLEAR_CTWND_8814B(x) | BIT_CTWND_8814B(v))\n\n/* 2 REG_BCNIVLCUNT_CFG_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_BCNIVLCUNT_8814B 0\n#define BIT_MASK_BCNIVLCUNT_8814B 0x7f\n#define BIT_BCNIVLCUNT_8814B(x)                                                \\\n\t(((x) & BIT_MASK_BCNIVLCUNT_8814B) << BIT_SHIFT_BCNIVLCUNT_8814B)\n#define BITS_BCNIVLCUNT_8814B                                                  \\\n\t(BIT_MASK_BCNIVLCUNT_8814B << BIT_SHIFT_BCNIVLCUNT_8814B)\n#define BIT_CLEAR_BCNIVLCUNT_8814B(x) ((x) & (~BITS_BCNIVLCUNT_8814B))\n#define BIT_GET_BCNIVLCUNT_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_BCNIVLCUNT_8814B) & BIT_MASK_BCNIVLCUNT_8814B)\n#define BIT_SET_BCNIVLCUNT_8814B(x, v)                                         \\\n\t(BIT_CLEAR_BCNIVLCUNT_8814B(x) | BIT_BCNIVLCUNT_8814B(v))\n\n/* 2 REG_EARLY_128US_CFG_8814B */\n\n#define BIT_SHIFT_EARLY_128US_8814B 0\n#define BIT_MASK_EARLY_128US_8814B 0x7\n#define BIT_EARLY_128US_8814B(x)                                               \\\n\t(((x) & BIT_MASK_EARLY_128US_8814B) << BIT_SHIFT_EARLY_128US_8814B)\n#define BITS_EARLY_128US_8814B                                                 \\\n\t(BIT_MASK_EARLY_128US_8814B << BIT_SHIFT_EARLY_128US_8814B)\n#define BIT_CLEAR_EARLY_128US_8814B(x) ((x) & (~BITS_EARLY_128US_8814B))\n#define BIT_GET_EARLY_128US_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_EARLY_128US_8814B) & BIT_MASK_EARLY_128US_8814B)\n#define BIT_SET_EARLY_128US_8814B(x, v)                                        \\\n\t(BIT_CLEAR_EARLY_128US_8814B(x) | BIT_EARLY_128US_8814B(v))\n\n/* 2 REG_TSFTR_SYNC_OFFSET_CFG_8814B */\n\n#define BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B 0\n#define BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B 0xffffff\n#define BIT_TSFTR_SNC_OFFSET_V1_8814B(x)                                       \\\n\t(((x) & BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B)                            \\\n\t << BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B)\n#define BITS_TSFTR_SNC_OFFSET_V1_8814B                                         \\\n\t(BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B                                    \\\n\t << BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B)\n#define BIT_CLEAR_TSFTR_SNC_OFFSET_V1_8814B(x)                                 \\\n\t((x) & (~BITS_TSFTR_SNC_OFFSET_V1_8814B))\n#define BIT_GET_TSFTR_SNC_OFFSET_V1_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B) &                        \\\n\t BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B)\n#define BIT_SET_TSFTR_SNC_OFFSET_V1_8814B(x, v)                                \\\n\t(BIT_CLEAR_TSFTR_SNC_OFFSET_V1_8814B(x) |                              \\\n\t BIT_TSFTR_SNC_OFFSET_V1_8814B(v))\n\n/* 2 REG_TSFTR_SYNC_CTRL_CFG_8814B */\n#define BIT_SYNC_TSF_NOW_V1_8814B BIT(5)\n#define BIT_SYNC_TSF_ONCE_8814B BIT(4)\n#define BIT_SYNC_TSF_AUTO_8814B BIT(3)\n\n#define BIT_SHIFT_SYNC_PORT_SEL_8814B 0\n#define BIT_MASK_SYNC_PORT_SEL_8814B 0x7\n#define BIT_SYNC_PORT_SEL_8814B(x)                                             \\\n\t(((x) & BIT_MASK_SYNC_PORT_SEL_8814B) << BIT_SHIFT_SYNC_PORT_SEL_8814B)\n#define BITS_SYNC_PORT_SEL_8814B                                               \\\n\t(BIT_MASK_SYNC_PORT_SEL_8814B << BIT_SHIFT_SYNC_PORT_SEL_8814B)\n#define BIT_CLEAR_SYNC_PORT_SEL_8814B(x) ((x) & (~BITS_SYNC_PORT_SEL_8814B))\n#define BIT_GET_SYNC_PORT_SEL_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SYNC_PORT_SEL_8814B) & BIT_MASK_SYNC_PORT_SEL_8814B)\n#define BIT_SET_SYNC_PORT_SEL_8814B(x, v)                                      \\\n\t(BIT_CLEAR_SYNC_PORT_SEL_8814B(x) | BIT_SYNC_PORT_SEL_8814B(v))\n\n/* 2 REG_BCN_SPACE_CFG_8814B */\n\n#define BIT_SHIFT_BCN_SPACE_8814B 0\n#define BIT_MASK_BCN_SPACE_8814B 0xffff\n#define BIT_BCN_SPACE_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_BCN_SPACE_8814B) << BIT_SHIFT_BCN_SPACE_8814B)\n#define BITS_BCN_SPACE_8814B                                                   \\\n\t(BIT_MASK_BCN_SPACE_8814B << BIT_SHIFT_BCN_SPACE_8814B)\n#define BIT_CLEAR_BCN_SPACE_8814B(x) ((x) & (~BITS_BCN_SPACE_8814B))\n#define BIT_GET_BCN_SPACE_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_8814B) & BIT_MASK_BCN_SPACE_8814B)\n#define BIT_SET_BCN_SPACE_8814B(x, v)                                          \\\n\t(BIT_CLEAR_BCN_SPACE_8814B(x) | BIT_BCN_SPACE_8814B(v))\n\n/* 2 REG_EARLY_INT_ADJUST_CFG_8814B */\n\n#define BIT_SHIFT_EARLY_INT_ADJUST_8814B 0\n#define BIT_MASK_EARLY_INT_ADJUST_8814B 0xffff\n#define BIT_EARLY_INT_ADJUST_8814B(x)                                          \\\n\t(((x) & BIT_MASK_EARLY_INT_ADJUST_8814B)                               \\\n\t << BIT_SHIFT_EARLY_INT_ADJUST_8814B)\n#define BITS_EARLY_INT_ADJUST_8814B                                            \\\n\t(BIT_MASK_EARLY_INT_ADJUST_8814B << BIT_SHIFT_EARLY_INT_ADJUST_8814B)\n#define BIT_CLEAR_EARLY_INT_ADJUST_8814B(x)                                    \\\n\t((x) & (~BITS_EARLY_INT_ADJUST_8814B))\n#define BIT_GET_EARLY_INT_ADJUST_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_EARLY_INT_ADJUST_8814B) &                           \\\n\t BIT_MASK_EARLY_INT_ADJUST_8814B)\n#define BIT_SET_EARLY_INT_ADJUST_8814B(x, v)                                   \\\n\t(BIT_CLEAR_EARLY_INT_ADJUST_8814B(x) | BIT_EARLY_INT_ADJUST_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_SW_TBTT_TSF_INFO_8814B */\n\n#define BIT_SHIFT_SW_TBTT_TSF_INFO_8814B 0\n#define BIT_MASK_SW_TBTT_TSF_INFO_8814B 0xffffffffL\n#define BIT_SW_TBTT_TSF_INFO_8814B(x)                                          \\\n\t(((x) & BIT_MASK_SW_TBTT_TSF_INFO_8814B)                               \\\n\t << BIT_SHIFT_SW_TBTT_TSF_INFO_8814B)\n#define BITS_SW_TBTT_TSF_INFO_8814B                                            \\\n\t(BIT_MASK_SW_TBTT_TSF_INFO_8814B << BIT_SHIFT_SW_TBTT_TSF_INFO_8814B)\n#define BIT_CLEAR_SW_TBTT_TSF_INFO_8814B(x)                                    \\\n\t((x) & (~BITS_SW_TBTT_TSF_INFO_8814B))\n#define BIT_GET_SW_TBTT_TSF_INFO_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_SW_TBTT_TSF_INFO_8814B) &                           \\\n\t BIT_MASK_SW_TBTT_TSF_INFO_8814B)\n#define BIT_SET_SW_TBTT_TSF_INFO_8814B(x, v)                                   \\\n\t(BIT_CLEAR_SW_TBTT_TSF_INFO_8814B(x) | BIT_SW_TBTT_TSF_INFO_8814B(v))\n\n/* 2 REG_TSFTR_LOW_8814B */\n\n#define BIT_SHIFT_TSF_TIMER_LOW_8814B 0\n#define BIT_MASK_TSF_TIMER_LOW_8814B 0xffffffffL\n#define BIT_TSF_TIMER_LOW_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TSF_TIMER_LOW_8814B) << BIT_SHIFT_TSF_TIMER_LOW_8814B)\n#define BITS_TSF_TIMER_LOW_8814B                                               \\\n\t(BIT_MASK_TSF_TIMER_LOW_8814B << BIT_SHIFT_TSF_TIMER_LOW_8814B)\n#define BIT_CLEAR_TSF_TIMER_LOW_8814B(x) ((x) & (~BITS_TSF_TIMER_LOW_8814B))\n#define BIT_GET_TSF_TIMER_LOW_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TSF_TIMER_LOW_8814B) & BIT_MASK_TSF_TIMER_LOW_8814B)\n#define BIT_SET_TSF_TIMER_LOW_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TSF_TIMER_LOW_8814B(x) | BIT_TSF_TIMER_LOW_8814B(v))\n\n/* 2 REG_TSFTR_HIGH_8814B */\n\n#define BIT_SHIFT_TSF_TIMER_HIGH_8814B 0\n#define BIT_MASK_TSF_TIMER_HIGH_8814B 0xffffffffL\n#define BIT_TSF_TIMER_HIGH_8814B(x)                                            \\\n\t(((x) & BIT_MASK_TSF_TIMER_HIGH_8814B)                                 \\\n\t << BIT_SHIFT_TSF_TIMER_HIGH_8814B)\n#define BITS_TSF_TIMER_HIGH_8814B                                              \\\n\t(BIT_MASK_TSF_TIMER_HIGH_8814B << BIT_SHIFT_TSF_TIMER_HIGH_8814B)\n#define BIT_CLEAR_TSF_TIMER_HIGH_8814B(x) ((x) & (~BITS_TSF_TIMER_HIGH_8814B))\n#define BIT_GET_TSF_TIMER_HIGH_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_TSF_TIMER_HIGH_8814B) &                             \\\n\t BIT_MASK_TSF_TIMER_HIGH_8814B)\n#define BIT_SET_TSF_TIMER_HIGH_8814B(x, v)                                     \\\n\t(BIT_CLEAR_TSF_TIMER_HIGH_8814B(x) | BIT_TSF_TIMER_HIGH_8814B(v))\n\n/* 2 REG_BCN_ERR_CNT_MAC_8814B */\n\n#define BIT_SHIFT_BCN_ERR_CNT_MAC_8814B 0\n#define BIT_MASK_BCN_ERR_CNT_MAC_8814B 0xff\n#define BIT_BCN_ERR_CNT_MAC_8814B(x)                                           \\\n\t(((x) & BIT_MASK_BCN_ERR_CNT_MAC_8814B)                                \\\n\t << BIT_SHIFT_BCN_ERR_CNT_MAC_8814B)\n#define BITS_BCN_ERR_CNT_MAC_8814B                                             \\\n\t(BIT_MASK_BCN_ERR_CNT_MAC_8814B << BIT_SHIFT_BCN_ERR_CNT_MAC_8814B)\n#define BIT_CLEAR_BCN_ERR_CNT_MAC_8814B(x) ((x) & (~BITS_BCN_ERR_CNT_MAC_8814B))\n#define BIT_GET_BCN_ERR_CNT_MAC_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_BCN_ERR_CNT_MAC_8814B) &                            \\\n\t BIT_MASK_BCN_ERR_CNT_MAC_8814B)\n#define BIT_SET_BCN_ERR_CNT_MAC_8814B(x, v)                                    \\\n\t(BIT_CLEAR_BCN_ERR_CNT_MAC_8814B(x) | BIT_BCN_ERR_CNT_MAC_8814B(v))\n\n/* 2 REG_BCN_ERR_CNT_EDCCA_8814B */\n\n#define BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B 0\n#define BIT_MASK_BCN_ERR_CNT_EDCCA_8814B 0xff\n#define BIT_BCN_ERR_CNT_EDCCA_8814B(x)                                         \\\n\t(((x) & BIT_MASK_BCN_ERR_CNT_EDCCA_8814B)                              \\\n\t << BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B)\n#define BITS_BCN_ERR_CNT_EDCCA_8814B                                           \\\n\t(BIT_MASK_BCN_ERR_CNT_EDCCA_8814B << BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B)\n#define BIT_CLEAR_BCN_ERR_CNT_EDCCA_8814B(x)                                   \\\n\t((x) & (~BITS_BCN_ERR_CNT_EDCCA_8814B))\n#define BIT_GET_BCN_ERR_CNT_EDCCA_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B) &                          \\\n\t BIT_MASK_BCN_ERR_CNT_EDCCA_8814B)\n#define BIT_SET_BCN_ERR_CNT_EDCCA_8814B(x, v)                                  \\\n\t(BIT_CLEAR_BCN_ERR_CNT_EDCCA_8814B(x) | BIT_BCN_ERR_CNT_EDCCA_8814B(v))\n\n/* 2 REG_BCN_ERR_CNT_CCA_8814B */\n\n#define BIT_SHIFT_BCN_ERR_CNT_CCA_8814B 0\n#define BIT_MASK_BCN_ERR_CNT_CCA_8814B 0xff\n#define BIT_BCN_ERR_CNT_CCA_8814B(x)                                           \\\n\t(((x) & BIT_MASK_BCN_ERR_CNT_CCA_8814B)                                \\\n\t << BIT_SHIFT_BCN_ERR_CNT_CCA_8814B)\n#define BITS_BCN_ERR_CNT_CCA_8814B                                             \\\n\t(BIT_MASK_BCN_ERR_CNT_CCA_8814B << BIT_SHIFT_BCN_ERR_CNT_CCA_8814B)\n#define BIT_CLEAR_BCN_ERR_CNT_CCA_8814B(x) ((x) & (~BITS_BCN_ERR_CNT_CCA_8814B))\n#define BIT_GET_BCN_ERR_CNT_CCA_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_BCN_ERR_CNT_CCA_8814B) &                            \\\n\t BIT_MASK_BCN_ERR_CNT_CCA_8814B)\n#define BIT_SET_BCN_ERR_CNT_CCA_8814B(x, v)                                    \\\n\t(BIT_CLEAR_BCN_ERR_CNT_CCA_8814B(x) | BIT_BCN_ERR_CNT_CCA_8814B(v))\n\n/* 2 REG_BCN_ERR_CNT_INVALID_8814B */\n\n#define BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B 0\n#define BIT_MASK_BCN_ERR_CNT_INVALID_8814B 0xff\n#define BIT_BCN_ERR_CNT_INVALID_8814B(x)                                       \\\n\t(((x) & BIT_MASK_BCN_ERR_CNT_INVALID_8814B)                            \\\n\t << BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B)\n#define BITS_BCN_ERR_CNT_INVALID_8814B                                         \\\n\t(BIT_MASK_BCN_ERR_CNT_INVALID_8814B                                    \\\n\t << BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B)\n#define BIT_CLEAR_BCN_ERR_CNT_INVALID_8814B(x)                                 \\\n\t((x) & (~BITS_BCN_ERR_CNT_INVALID_8814B))\n#define BIT_GET_BCN_ERR_CNT_INVALID_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B) &                        \\\n\t BIT_MASK_BCN_ERR_CNT_INVALID_8814B)\n#define BIT_SET_BCN_ERR_CNT_INVALID_8814B(x, v)                                \\\n\t(BIT_CLEAR_BCN_ERR_CNT_INVALID_8814B(x) |                              \\\n\t BIT_BCN_ERR_CNT_INVALID_8814B(v))\n\n/* 2 REG_BCN_ERR_CNT_OTHERS_8814B */\n\n#define BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B 0\n#define BIT_MASK_BCN_ERR_CNT_OTHERS_8814B 0xff\n#define BIT_BCN_ERR_CNT_OTHERS_8814B(x)                                        \\\n\t(((x) & BIT_MASK_BCN_ERR_CNT_OTHERS_8814B)                             \\\n\t << BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B)\n#define BITS_BCN_ERR_CNT_OTHERS_8814B                                          \\\n\t(BIT_MASK_BCN_ERR_CNT_OTHERS_8814B                                     \\\n\t << BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B)\n#define BIT_CLEAR_BCN_ERR_CNT_OTHERS_8814B(x)                                  \\\n\t((x) & (~BITS_BCN_ERR_CNT_OTHERS_8814B))\n#define BIT_GET_BCN_ERR_CNT_OTHERS_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B) &                         \\\n\t BIT_MASK_BCN_ERR_CNT_OTHERS_8814B)\n#define BIT_SET_BCN_ERR_CNT_OTHERS_8814B(x, v)                                 \\\n\t(BIT_CLEAR_BCN_ERR_CNT_OTHERS_8814B(x) |                               \\\n\t BIT_BCN_ERR_CNT_OTHERS_8814B(v))\n\n/* 2 REG_RX_BCN_TIMER_8814B */\n\n#define BIT_SHIFT_RX_BCN_TIMER_8814B 0\n#define BIT_MASK_RX_BCN_TIMER_8814B 0xffff\n#define BIT_RX_BCN_TIMER_8814B(x)                                              \\\n\t(((x) & BIT_MASK_RX_BCN_TIMER_8814B) << BIT_SHIFT_RX_BCN_TIMER_8814B)\n#define BITS_RX_BCN_TIMER_8814B                                                \\\n\t(BIT_MASK_RX_BCN_TIMER_8814B << BIT_SHIFT_RX_BCN_TIMER_8814B)\n#define BIT_CLEAR_RX_BCN_TIMER_8814B(x) ((x) & (~BITS_RX_BCN_TIMER_8814B))\n#define BIT_GET_RX_BCN_TIMER_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TIMER_8814B) & BIT_MASK_RX_BCN_TIMER_8814B)\n#define BIT_SET_RX_BCN_TIMER_8814B(x, v)                                       \\\n\t(BIT_CLEAR_RX_BCN_TIMER_8814B(x) | BIT_RX_BCN_TIMER_8814B(v))\n\n/* 2 REG_TBTT_CTN_AREA_V1_8814B */\n\n#define BIT_SHIFT_TBTT_CTN_AREA_8814B 0\n#define BIT_MASK_TBTT_CTN_AREA_8814B 0xff\n#define BIT_TBTT_CTN_AREA_8814B(x)                                             \\\n\t(((x) & BIT_MASK_TBTT_CTN_AREA_8814B) << BIT_SHIFT_TBTT_CTN_AREA_8814B)\n#define BITS_TBTT_CTN_AREA_8814B                                               \\\n\t(BIT_MASK_TBTT_CTN_AREA_8814B << BIT_SHIFT_TBTT_CTN_AREA_8814B)\n#define BIT_CLEAR_TBTT_CTN_AREA_8814B(x) ((x) & (~BITS_TBTT_CTN_AREA_8814B))\n#define BIT_GET_TBTT_CTN_AREA_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TBTT_CTN_AREA_8814B) & BIT_MASK_TBTT_CTN_AREA_8814B)\n#define BIT_SET_TBTT_CTN_AREA_8814B(x, v)                                      \\\n\t(BIT_CLEAR_TBTT_CTN_AREA_8814B(x) | BIT_TBTT_CTN_AREA_8814B(v))\n\n/* 2 REG_BCN_MAX_ERR_V1_8814B */\n\n#define BIT_SHIFT_BCN_MAX_ERR_8814B 0\n#define BIT_MASK_BCN_MAX_ERR_8814B 0xff\n#define BIT_BCN_MAX_ERR_8814B(x)                                               \\\n\t(((x) & BIT_MASK_BCN_MAX_ERR_8814B) << BIT_SHIFT_BCN_MAX_ERR_8814B)\n#define BITS_BCN_MAX_ERR_8814B                                                 \\\n\t(BIT_MASK_BCN_MAX_ERR_8814B << BIT_SHIFT_BCN_MAX_ERR_8814B)\n#define BIT_CLEAR_BCN_MAX_ERR_8814B(x) ((x) & (~BITS_BCN_MAX_ERR_8814B))\n#define BIT_GET_BCN_MAX_ERR_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_BCN_MAX_ERR_8814B) & BIT_MASK_BCN_MAX_ERR_8814B)\n#define BIT_SET_BCN_MAX_ERR_8814B(x, v)                                        \\\n\t(BIT_CLEAR_BCN_MAX_ERR_8814B(x) | BIT_BCN_MAX_ERR_8814B(v))\n\n/* 2 REG_RXTSF_OFFSET_CCK_V1_8814B */\n\n#define BIT_SHIFT_CCK_RXTSF_OFFSET_8814B 0\n#define BIT_MASK_CCK_RXTSF_OFFSET_8814B 0xff\n#define BIT_CCK_RXTSF_OFFSET_8814B(x)                                          \\\n\t(((x) & BIT_MASK_CCK_RXTSF_OFFSET_8814B)                               \\\n\t << BIT_SHIFT_CCK_RXTSF_OFFSET_8814B)\n#define BITS_CCK_RXTSF_OFFSET_8814B                                            \\\n\t(BIT_MASK_CCK_RXTSF_OFFSET_8814B << BIT_SHIFT_CCK_RXTSF_OFFSET_8814B)\n#define BIT_CLEAR_CCK_RXTSF_OFFSET_8814B(x)                                    \\\n\t((x) & (~BITS_CCK_RXTSF_OFFSET_8814B))\n#define BIT_GET_CCK_RXTSF_OFFSET_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8814B) &                           \\\n\t BIT_MASK_CCK_RXTSF_OFFSET_8814B)\n#define BIT_SET_CCK_RXTSF_OFFSET_8814B(x, v)                                   \\\n\t(BIT_CLEAR_CCK_RXTSF_OFFSET_8814B(x) | BIT_CCK_RXTSF_OFFSET_8814B(v))\n\n/* 2 REG_RXTSF_OFFSET_OFDM_V1_8814B */\n\n#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B 0\n#define BIT_MASK_OFDM_RXTSF_OFFSET_8814B 0xff\n#define BIT_OFDM_RXTSF_OFFSET_8814B(x)                                         \\\n\t(((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8814B)                              \\\n\t << BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B)\n#define BITS_OFDM_RXTSF_OFFSET_8814B                                           \\\n\t(BIT_MASK_OFDM_RXTSF_OFFSET_8814B << BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B)\n#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8814B(x)                                   \\\n\t((x) & (~BITS_OFDM_RXTSF_OFFSET_8814B))\n#define BIT_GET_OFDM_RXTSF_OFFSET_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B) &                          \\\n\t BIT_MASK_OFDM_RXTSF_OFFSET_8814B)\n#define BIT_SET_OFDM_RXTSF_OFFSET_8814B(x, v)                                  \\\n\t(BIT_CLEAR_OFDM_RXTSF_OFFSET_8814B(x) | BIT_OFDM_RXTSF_OFFSET_8814B(v))\n\n/* 2 REG_SUB_BCN_SPACE_8814B */\n\n#define BIT_SHIFT_SUB_BCN_SPACE_V2_8814B 0\n#define BIT_MASK_SUB_BCN_SPACE_V2_8814B 0xff\n#define BIT_SUB_BCN_SPACE_V2_8814B(x)                                          \\\n\t(((x) & BIT_MASK_SUB_BCN_SPACE_V2_8814B)                               \\\n\t << BIT_SHIFT_SUB_BCN_SPACE_V2_8814B)\n#define BITS_SUB_BCN_SPACE_V2_8814B                                            \\\n\t(BIT_MASK_SUB_BCN_SPACE_V2_8814B << BIT_SHIFT_SUB_BCN_SPACE_V2_8814B)\n#define BIT_CLEAR_SUB_BCN_SPACE_V2_8814B(x)                                    \\\n\t((x) & (~BITS_SUB_BCN_SPACE_V2_8814B))\n#define BIT_GET_SUB_BCN_SPACE_V2_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_SUB_BCN_SPACE_V2_8814B) &                           \\\n\t BIT_MASK_SUB_BCN_SPACE_V2_8814B)\n#define BIT_SET_SUB_BCN_SPACE_V2_8814B(x, v)                                   \\\n\t(BIT_CLEAR_SUB_BCN_SPACE_V2_8814B(x) | BIT_SUB_BCN_SPACE_V2_8814B(v))\n\n/* 2 REG_MBID_NUM_V1_8814B */\n\n#define BIT_SHIFT_BCN_ERR_PORT_SEL_8814B 4\n#define BIT_MASK_BCN_ERR_PORT_SEL_8814B 0xf\n#define BIT_BCN_ERR_PORT_SEL_8814B(x)                                          \\\n\t(((x) & BIT_MASK_BCN_ERR_PORT_SEL_8814B)                               \\\n\t << BIT_SHIFT_BCN_ERR_PORT_SEL_8814B)\n#define BITS_BCN_ERR_PORT_SEL_8814B                                            \\\n\t(BIT_MASK_BCN_ERR_PORT_SEL_8814B << BIT_SHIFT_BCN_ERR_PORT_SEL_8814B)\n#define BIT_CLEAR_BCN_ERR_PORT_SEL_8814B(x)                                    \\\n\t((x) & (~BITS_BCN_ERR_PORT_SEL_8814B))\n#define BIT_GET_BCN_ERR_PORT_SEL_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCN_ERR_PORT_SEL_8814B) &                           \\\n\t BIT_MASK_BCN_ERR_PORT_SEL_8814B)\n#define BIT_SET_BCN_ERR_PORT_SEL_8814B(x, v)                                   \\\n\t(BIT_CLEAR_BCN_ERR_PORT_SEL_8814B(x) | BIT_BCN_ERR_PORT_SEL_8814B(v))\n\n#define BIT_SHIFT_MBID_BCN_NUM_V1_8814B 0\n#define BIT_MASK_MBID_BCN_NUM_V1_8814B 0xf\n#define BIT_MBID_BCN_NUM_V1_8814B(x)                                           \\\n\t(((x) & BIT_MASK_MBID_BCN_NUM_V1_8814B)                                \\\n\t << BIT_SHIFT_MBID_BCN_NUM_V1_8814B)\n#define BITS_MBID_BCN_NUM_V1_8814B                                             \\\n\t(BIT_MASK_MBID_BCN_NUM_V1_8814B << BIT_SHIFT_MBID_BCN_NUM_V1_8814B)\n#define BIT_CLEAR_MBID_BCN_NUM_V1_8814B(x) ((x) & (~BITS_MBID_BCN_NUM_V1_8814B))\n#define BIT_GET_MBID_BCN_NUM_V1_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_MBID_BCN_NUM_V1_8814B) &                            \\\n\t BIT_MASK_MBID_BCN_NUM_V1_8814B)\n#define BIT_SET_MBID_BCN_NUM_V1_8814B(x, v)                                    \\\n\t(BIT_CLEAR_MBID_BCN_NUM_V1_8814B(x) | BIT_MBID_BCN_NUM_V1_8814B(v))\n\n/* 2 REG_MBSSID_CTRL_V1_8814B */\n#define BIT_MBID_BCNQ15_EN_8814B BIT(15)\n#define BIT_MBID_BCNQ14_EN_8814B BIT(14)\n#define BIT_MBID_BCNQ13_EN_8814B BIT(13)\n#define BIT_MBID_BCNQ12_EN_8814B BIT(12)\n#define BIT_MBID_BCNQ11_EN_8814B BIT(11)\n#define BIT_MBID_BCNQ10_EN_8814B BIT(10)\n#define BIT_MBID_BCNQ9_EN_8814B BIT(9)\n#define BIT_MBID_BCNQ8_EN_8814B BIT(8)\n#define BIT_MBID_BCNQ7_EN_8814B BIT(7)\n#define BIT_MBID_BCNQ6_EN_8814B BIT(6)\n#define BIT_MBID_BCNQ5_EN_8814B BIT(5)\n#define BIT_MBID_BCNQ4_EN_8814B BIT(4)\n#define BIT_MBID_BCNQ3_EN_8814B BIT(3)\n#define BIT_MBID_BCNQ2_EN_8814B BIT(2)\n#define BIT_MBID_BCNQ1_EN_8814B BIT(1)\n#define BIT_MBID_BCNQ0_EN_8814B BIT(0)\n\n/* 2 REG_USTIME_TSF_V1_8814B */\n\n#define BIT_SHIFT_USTIME_TSF_V1_8814B 0\n#define BIT_MASK_USTIME_TSF_V1_8814B 0xff\n#define BIT_USTIME_TSF_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_USTIME_TSF_V1_8814B) << BIT_SHIFT_USTIME_TSF_V1_8814B)\n#define BITS_USTIME_TSF_V1_8814B                                               \\\n\t(BIT_MASK_USTIME_TSF_V1_8814B << BIT_SHIFT_USTIME_TSF_V1_8814B)\n#define BIT_CLEAR_USTIME_TSF_V1_8814B(x) ((x) & (~BITS_USTIME_TSF_V1_8814B))\n#define BIT_GET_USTIME_TSF_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_USTIME_TSF_V1_8814B) & BIT_MASK_USTIME_TSF_V1_8814B)\n#define BIT_SET_USTIME_TSF_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_USTIME_TSF_V1_8814B(x) | BIT_USTIME_TSF_V1_8814B(v))\n\n/* 2 REG_BW_CFG_8814B */\n#define BIT_SLEEP_32K_EN_8814B BIT(3)\n#define BIT_DIS_MARK_TSF_US_V1_8814B BIT(2)\n\n#define BIT_SHIFT_BW_CFG_8814B 0\n#define BIT_MASK_BW_CFG_8814B 0x3\n#define BIT_BW_CFG_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_BW_CFG_8814B) << BIT_SHIFT_BW_CFG_8814B)\n#define BITS_BW_CFG_8814B (BIT_MASK_BW_CFG_8814B << BIT_SHIFT_BW_CFG_8814B)\n#define BIT_CLEAR_BW_CFG_8814B(x) ((x) & (~BITS_BW_CFG_8814B))\n#define BIT_GET_BW_CFG_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_BW_CFG_8814B) & BIT_MASK_BW_CFG_8814B)\n#define BIT_SET_BW_CFG_8814B(x, v)                                             \\\n\t(BIT_CLEAR_BW_CFG_8814B(x) | BIT_BW_CFG_8814B(v))\n\n/* 2 REG_ATIMWND_CFG_8814B */\n\n#define BIT_SHIFT_ATIMWND_V1_8814B 0\n#define BIT_MASK_ATIMWND_V1_8814B 0xff\n#define BIT_ATIMWND_V1_8814B(x)                                                \\\n\t(((x) & BIT_MASK_ATIMWND_V1_8814B) << BIT_SHIFT_ATIMWND_V1_8814B)\n#define BITS_ATIMWND_V1_8814B                                                  \\\n\t(BIT_MASK_ATIMWND_V1_8814B << BIT_SHIFT_ATIMWND_V1_8814B)\n#define BIT_CLEAR_ATIMWND_V1_8814B(x) ((x) & (~BITS_ATIMWND_V1_8814B))\n#define BIT_GET_ATIMWND_V1_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_ATIMWND_V1_8814B) & BIT_MASK_ATIMWND_V1_8814B)\n#define BIT_SET_ATIMWND_V1_8814B(x, v)                                         \\\n\t(BIT_CLEAR_ATIMWND_V1_8814B(x) | BIT_ATIMWND_V1_8814B(v))\n\n/* 2 REG_DTIM_COUNTER_CFG_8814B */\n\n#define BIT_SHIFT_DTIM_COUNT_8814B 0\n#define BIT_MASK_DTIM_COUNT_8814B 0xff\n#define BIT_DTIM_COUNT_8814B(x)                                                \\\n\t(((x) & BIT_MASK_DTIM_COUNT_8814B) << BIT_SHIFT_DTIM_COUNT_8814B)\n#define BITS_DTIM_COUNT_8814B                                                  \\\n\t(BIT_MASK_DTIM_COUNT_8814B << BIT_SHIFT_DTIM_COUNT_8814B)\n#define BIT_CLEAR_DTIM_COUNT_8814B(x) ((x) & (~BITS_DTIM_COUNT_8814B))\n#define BIT_GET_DTIM_COUNT_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_8814B) & BIT_MASK_DTIM_COUNT_8814B)\n#define BIT_SET_DTIM_COUNT_8814B(x, v)                                         \\\n\t(BIT_CLEAR_DTIM_COUNT_8814B(x) | BIT_DTIM_COUNT_8814B(v))\n\n/* 2 REG_ATIM_DTIM_CTRL_SEL_8814B */\n#define BIT_DTIM_BYPASS_V1_8814B BIT(7)\n\n#define BIT_SHIFT_ATIM_DTIM_SEL_8814B 0\n#define BIT_MASK_ATIM_DTIM_SEL_8814B 0x1f\n#define BIT_ATIM_DTIM_SEL_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ATIM_DTIM_SEL_8814B) << BIT_SHIFT_ATIM_DTIM_SEL_8814B)\n#define BITS_ATIM_DTIM_SEL_8814B                                               \\\n\t(BIT_MASK_ATIM_DTIM_SEL_8814B << BIT_SHIFT_ATIM_DTIM_SEL_8814B)\n#define BIT_CLEAR_ATIM_DTIM_SEL_8814B(x) ((x) & (~BITS_ATIM_DTIM_SEL_8814B))\n#define BIT_GET_ATIM_DTIM_SEL_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ATIM_DTIM_SEL_8814B) & BIT_MASK_ATIM_DTIM_SEL_8814B)\n#define BIT_SET_ATIM_DTIM_SEL_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ATIM_DTIM_SEL_8814B(x) | BIT_ATIM_DTIM_SEL_8814B(v))\n\n/* 2 REG_ATIMUGT_V1_8814B */\n\n#define BIT_SHIFT_ATIM_URGENT_8814B 0\n#define BIT_MASK_ATIM_URGENT_8814B 0xff\n#define BIT_ATIM_URGENT_8814B(x)                                               \\\n\t(((x) & BIT_MASK_ATIM_URGENT_8814B) << BIT_SHIFT_ATIM_URGENT_8814B)\n#define BITS_ATIM_URGENT_8814B                                                 \\\n\t(BIT_MASK_ATIM_URGENT_8814B << BIT_SHIFT_ATIM_URGENT_8814B)\n#define BIT_CLEAR_ATIM_URGENT_8814B(x) ((x) & (~BITS_ATIM_URGENT_8814B))\n#define BIT_GET_ATIM_URGENT_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_ATIM_URGENT_8814B) & BIT_MASK_ATIM_URGENT_8814B)\n#define BIT_SET_ATIM_URGENT_8814B(x, v)                                        \\\n\t(BIT_CLEAR_ATIM_URGENT_8814B(x) | BIT_ATIM_URGENT_8814B(v))\n\n/* 2 REG_BCNDROPCTRL_V1_8814B */\n#define BIT_BEACON_DROP_EN_8814B BIT(7)\n\n#define BIT_SHIFT_BEACON_DROP_IVL_8814B 0\n#define BIT_MASK_BEACON_DROP_IVL_8814B 0x7f\n#define BIT_BEACON_DROP_IVL_8814B(x)                                           \\\n\t(((x) & BIT_MASK_BEACON_DROP_IVL_8814B)                                \\\n\t << BIT_SHIFT_BEACON_DROP_IVL_8814B)\n#define BITS_BEACON_DROP_IVL_8814B                                             \\\n\t(BIT_MASK_BEACON_DROP_IVL_8814B << BIT_SHIFT_BEACON_DROP_IVL_8814B)\n#define BIT_CLEAR_BEACON_DROP_IVL_8814B(x) ((x) & (~BITS_BEACON_DROP_IVL_8814B))\n#define BIT_GET_BEACON_DROP_IVL_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_BEACON_DROP_IVL_8814B) &                            \\\n\t BIT_MASK_BEACON_DROP_IVL_8814B)\n#define BIT_SET_BEACON_DROP_IVL_8814B(x, v)                                    \\\n\t(BIT_CLEAR_BEACON_DROP_IVL_8814B(x) | BIT_BEACON_DROP_IVL_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_DIS_ATIM_V1_8814B */\n#define BIT_DIS_ATIM_P4_8814B BIT(19)\n#define BIT_DIS_ATIM_P3_8814B BIT(18)\n#define BIT_DIS_ATIM_P2_8814B BIT(17)\n#define BIT_DIS_ATIM_P1_8814B BIT(16)\n#define BIT_DIS_ATIM_VAP15_8814B BIT(15)\n#define BIT_DIS_ATIM_VAP14_8814B BIT(14)\n#define BIT_DIS_ATIM_VAP13_8814B BIT(13)\n#define BIT_DIS_ATIM_VAP12_8814B BIT(12)\n#define BIT_DIS_ATIM_VAP11_8814B BIT(11)\n#define BIT_DIS_ATIM_VAP10_8814B BIT(10)\n#define BIT_DIS_ATIM_VAP9_8814B BIT(9)\n#define BIT_DIS_ATIM_VAP8_8814B BIT(8)\n#define BIT_DIS_ATIM_VAP7_8814B BIT(7)\n#define BIT_DIS_ATIM_VAP6_8814B BIT(6)\n#define BIT_DIS_ATIM_VAP5_8814B BIT(5)\n#define BIT_DIS_ATIM_VAP4_8814B BIT(4)\n#define BIT_DIS_ATIM_VAP3_8814B BIT(3)\n#define BIT_DIS_ATIM_VAP2_8814B BIT(2)\n#define BIT_DIS_ATIM_VAP1_8814B BIT(1)\n#define BIT_DIS_ATIM_ROOT_P0_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_HIQ_NO_LMT_EN_V1_8814B */\n#define BIT_HIQ_NO_LMT_EN_P4_8814B BIT(19)\n#define BIT_HIQ_NO_LMT_EN_P3_8814B BIT(18)\n#define BIT_HIQ_NO_LMT_EN_P2_8814B BIT(17)\n#define BIT_HIQ_NO_LMT_EN_P1_8814B BIT(16)\n#define BIT_HIQ_NO_LMT_EN_VAP15_8814B BIT(15)\n#define BIT_HIQ_NO_LMT_EN_VAP14_8814B BIT(14)\n#define BIT_HIQ_NO_LMT_EN_VAP13_8814B BIT(13)\n#define BIT_HIQ_NO_LMT_EN_VAP12_8814B BIT(12)\n#define BIT_HIQ_NO_LMT_EN_VAP11_8814B BIT(11)\n#define BIT_HIQ_NO_LMT_EN_VAP10_8814B BIT(10)\n#define BIT_HIQ_NO_LMT_EN_VAP9_8814B BIT(9)\n#define BIT_HIQ_NO_LMT_EN_VAP8_8814B BIT(8)\n#define BIT_HIQ_NO_LMT_EN_VAP7_8814B BIT(7)\n#define BIT_HIQ_NO_LMT_EN_VAP6_8814B BIT(6)\n#define BIT_HIQ_NO_LMT_EN_VAP5_8814B BIT(5)\n#define BIT_HIQ_NO_LMT_EN_VAP4_8814B BIT(4)\n#define BIT_HIQ_NO_LMT_EN_VAP3_8814B BIT(3)\n#define BIT_HIQ_NO_LMT_EN_VAP2_8814B BIT(2)\n#define BIT_HIQ_NO_LMT_EN_VAP1_8814B BIT(1)\n#define BIT_HIQ_NO_LMT_EN_ROOT_P0_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_P2PPS_CTRL_V1_8814B */\n#define BIT_P2P_PWR_RST1_V2_8814B BIT(15)\n#define BIT_P2P_PWR_RST0_V2_8814B BIT(14)\n#define BIT_EN_TSFBIT32_RST_P2P_V1_8814B BIT(13)\n\n#define BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B 8\n#define BIT_MASK_NOA_UNIT0_SEL_V1_8814B 0x7\n#define BIT_NOA_UNIT0_SEL_V1_8814B(x)                                          \\\n\t(((x) & BIT_MASK_NOA_UNIT0_SEL_V1_8814B)                               \\\n\t << BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B)\n#define BITS_NOA_UNIT0_SEL_V1_8814B                                            \\\n\t(BIT_MASK_NOA_UNIT0_SEL_V1_8814B << BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B)\n#define BIT_CLEAR_NOA_UNIT0_SEL_V1_8814B(x)                                    \\\n\t((x) & (~BITS_NOA_UNIT0_SEL_V1_8814B))\n#define BIT_GET_NOA_UNIT0_SEL_V1_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B) &                           \\\n\t BIT_MASK_NOA_UNIT0_SEL_V1_8814B)\n#define BIT_SET_NOA_UNIT0_SEL_V1_8814B(x, v)                                   \\\n\t(BIT_CLEAR_NOA_UNIT0_SEL_V1_8814B(x) | BIT_NOA_UNIT0_SEL_V1_8814B(v))\n\n#define BIT_P2P_CTW_ALLSTASLEEP_V1_8814B BIT(7)\n#define BIT_P2P_OFF_DISTX_EN_V1_8814B BIT(6)\n#define BIT_PWR_MGT_EN_V1_8814B BIT(5)\n#define BIT_P2P_NOA1_EN_V1_8814B BIT(2)\n#define BIT_P2P_NOA0_EN_V1_8814B BIT(1)\n\n/* 2 REG_P2PPS_SPEC_STATE_V1_8814B */\n#define BIT_SPEC_POWER_STATE_8814B BIT(7)\n#define BIT_SPEC_CTWINDOW_ON_8814B BIT(6)\n#define BIT_SPEC_BEACON_AREA_ON_8814B BIT(5)\n#define BIT_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4)\n#define BIT_SPEC_NOA1_OFF_PERIOD_8814B BIT(3)\n#define BIT_SPEC_FORCE_DOZE1_8814B BIT(2)\n#define BIT_SPEC_NOA0_OFF_PERIOD_8814B BIT(1)\n#define BIT_SPEC_FORCE_DOZE0_8814B BIT(0)\n\n/* 2 REG_P2PPS_STATE_V1_8814B */\n#define BIT_POWER_STATE_8814B BIT(7)\n#define BIT_CTWINDOW_ON_8814B BIT(6)\n#define BIT_BEACON_AREA_ON_8814B BIT(5)\n#define BIT_CTWIN_EARLY_DISTX_8814B BIT(4)\n#define BIT_NOA1_OFF_PERIOD_8814B BIT(3)\n#define BIT_FORCE_DOZE1_8814B BIT(2)\n#define BIT_NOA0_OFF_PERIOD_8814B BIT(1)\n#define BIT_FORCE_DOZE0_8814B BIT(0)\n\n/* 2 REG_P2PPS1_CTRL_V1_8814B */\n#define BIT_P2P1_PWR_RST1_V2_8814B BIT(15)\n#define BIT_P2P1_PWR_RST0_V2_8814B BIT(14)\n#define BIT_EN_TSFBIT32_RST_P2P1_V1_8814B BIT(13)\n\n#define BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B 8\n#define BIT_MASK_NOA_UNIT1_SEL_V1_8814B 0x7\n#define BIT_NOA_UNIT1_SEL_V1_8814B(x)                                          \\\n\t(((x) & BIT_MASK_NOA_UNIT1_SEL_V1_8814B)                               \\\n\t << BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B)\n#define BITS_NOA_UNIT1_SEL_V1_8814B                                            \\\n\t(BIT_MASK_NOA_UNIT1_SEL_V1_8814B << BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B)\n#define BIT_CLEAR_NOA_UNIT1_SEL_V1_8814B(x)                                    \\\n\t((x) & (~BITS_NOA_UNIT1_SEL_V1_8814B))\n#define BIT_GET_NOA_UNIT1_SEL_V1_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B) &                           \\\n\t BIT_MASK_NOA_UNIT1_SEL_V1_8814B)\n#define BIT_SET_NOA_UNIT1_SEL_V1_8814B(x, v)                                   \\\n\t(BIT_CLEAR_NOA_UNIT1_SEL_V1_8814B(x) | BIT_NOA_UNIT1_SEL_V1_8814B(v))\n\n#define BIT_P2P1_CTW_ALLSTASLEEP_V1_8814B BIT(7)\n#define BIT_P2P1_OFF_DISTX_EN_8814B BIT(6)\n#define BIT_P2P1_PWR_MGT_EN_V1_8814B BIT(5)\n#define BIT_P2P1_NOA1_EN_V1_8814B BIT(2)\n#define BIT_P2P1_NOA0_EN_V1_8814B BIT(1)\n\n/* 2 REG_P2PPS1_SPEC_STATE_V1_8814B */\n#define BIT_P2P1_SPEC_POWER_STATEP_8814B BIT(7)\n#define BIT_P2P1_SPEC_CTWINDOW_ON_8814B BIT(6)\n#define BIT_P2P1_SPEC_BEACON_AREA_ON_8814B BIT(5)\n#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4)\n#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8814B BIT(3)\n#define BIT_P2P1_SPEC_FORCE_DOZE1_8814B BIT(2)\n#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8814B BIT(1)\n#define BIT_P2P1_SPEC_FORCE_DOZE0_8814B BIT(0)\n\n/* 2 REG_P2PPS1_STATE_V1_8814B */\n#define BIT_P2P1_POWER_STATE_8814B BIT(7)\n#define BIT_P2P1_CTWINDOW_ON_8814B BIT(6)\n#define BIT_P2P1_BEACON_AREA_ON_8814B BIT(5)\n#define BIT_P2P1_CTWIN_EARLY_DISTX_8814B BIT(4)\n#define BIT_P2P1_NOA1_OFF_PERIOD_8814B BIT(3)\n#define BIT_P2P1_FORCE_DOZE1_8814B BIT(2)\n#define BIT_P2P1_NOA0_OFF_PERIOD_8814B BIT(1)\n#define BIT_P2P1_FORCE_DOZE0_8814B BIT(0)\n\n/* 2 REG_P2PPS2_CTRL_V1_8814B */\n#define BIT_P2P2_PWR_RST1_V2_8814B BIT(15)\n#define BIT_P2P2_PWR_RST0_V2_8814B BIT(14)\n#define BIT_EN_TSFBIT32_RST_P2P2_V1_8814B BIT(13)\n\n#define BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B 8\n#define BIT_MASK_NOA_UNIT2_SEL_V1_8814B 0x7\n#define BIT_NOA_UNIT2_SEL_V1_8814B(x)                                          \\\n\t(((x) & BIT_MASK_NOA_UNIT2_SEL_V1_8814B)                               \\\n\t << BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B)\n#define BITS_NOA_UNIT2_SEL_V1_8814B                                            \\\n\t(BIT_MASK_NOA_UNIT2_SEL_V1_8814B << BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B)\n#define BIT_CLEAR_NOA_UNIT2_SEL_V1_8814B(x)                                    \\\n\t((x) & (~BITS_NOA_UNIT2_SEL_V1_8814B))\n#define BIT_GET_NOA_UNIT2_SEL_V1_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B) &                           \\\n\t BIT_MASK_NOA_UNIT2_SEL_V1_8814B)\n#define BIT_SET_NOA_UNIT2_SEL_V1_8814B(x, v)                                   \\\n\t(BIT_CLEAR_NOA_UNIT2_SEL_V1_8814B(x) | BIT_NOA_UNIT2_SEL_V1_8814B(v))\n\n#define BIT_P2P2_CTW_ALLSTASLEEP_V1_8814B BIT(7)\n#define BIT_P2P2_OFF_DISTX_EN_V1_8814B BIT(6)\n#define BIT_P2P2_PWR_MGT_EN_V1_8814B BIT(5)\n#define BIT_P2P2_NOA1_EN_V1_8814B BIT(2)\n#define BIT_P2P2_NOA0_EN_V1_8814B BIT(1)\n\n/* 2 REG_P2PPS2_SPEC_STATE_V1_8814B */\n#define BIT_P2P2_SPEC_POWER_STATEP_8814B BIT(7)\n#define BIT_P2P2_SPEC_CTWINDOW_ON_8814B BIT(6)\n#define BIT_P2P2_SPEC_BEACON_AREA_ON_8814B BIT(5)\n#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4)\n#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8814B BIT(3)\n#define BIT_P2P2_SPEC_FORCE_DOZE1_8814B BIT(2)\n#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8814B BIT(1)\n#define BIT_P2P2_SPEC_FORCE_DOZE0_8814B BIT(0)\n\n/* 2 REG_P2PPS2_STATE_V1_8814B */\n#define BIT_P2P2_POWER_STATE_8814B BIT(7)\n#define BIT_P2P2_CTWINDOW_ON_8814B BIT(6)\n#define BIT_P2P2_BEACON_AREA_ON_8814B BIT(5)\n#define BIT_P2P2_CTWIN_EARLY_DISTX_8814B BIT(4)\n#define BIT_P2P2_NOA1_OFF_PERIOD_8814B BIT(3)\n#define BIT_P2P2_FORCE_DOZE1_8814B BIT(2)\n#define BIT_P2P2_NOA0_OFF_PERIOD_8814B BIT(1)\n#define BIT_P2P2_FORCE_DOZE0_8814B BIT(0)\n\n/* 2 REG_P2PON_DIS_TXTIME_V1_8814B */\n\n#define BIT_SHIFT_P2PON_DIS_TXTIME_8814B 0\n#define BIT_MASK_P2PON_DIS_TXTIME_8814B 0xff\n#define BIT_P2PON_DIS_TXTIME_8814B(x)                                          \\\n\t(((x) & BIT_MASK_P2PON_DIS_TXTIME_8814B)                               \\\n\t << BIT_SHIFT_P2PON_DIS_TXTIME_8814B)\n#define BITS_P2PON_DIS_TXTIME_8814B                                            \\\n\t(BIT_MASK_P2PON_DIS_TXTIME_8814B << BIT_SHIFT_P2PON_DIS_TXTIME_8814B)\n#define BIT_CLEAR_P2PON_DIS_TXTIME_8814B(x)                                    \\\n\t((x) & (~BITS_P2PON_DIS_TXTIME_8814B))\n#define BIT_GET_P2PON_DIS_TXTIME_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8814B) &                           \\\n\t BIT_MASK_P2PON_DIS_TXTIME_8814B)\n#define BIT_SET_P2PON_DIS_TXTIME_8814B(x, v)                                   \\\n\t(BIT_CLEAR_P2PON_DIS_TXTIME_8814B(x) | BIT_P2PON_DIS_TXTIME_8814B(v))\n\n/* 2 REG_P2POFF_DIS_TXTIME_V1_8814B */\n\n#define BIT_SHIFT_P2POFF_DIS_TXTIME_8814B 0\n#define BIT_MASK_P2POFF_DIS_TXTIME_8814B 0xff\n#define BIT_P2POFF_DIS_TXTIME_8814B(x)                                         \\\n\t(((x) & BIT_MASK_P2POFF_DIS_TXTIME_8814B)                              \\\n\t << BIT_SHIFT_P2POFF_DIS_TXTIME_8814B)\n#define BITS_P2POFF_DIS_TXTIME_8814B                                           \\\n\t(BIT_MASK_P2POFF_DIS_TXTIME_8814B << BIT_SHIFT_P2POFF_DIS_TXTIME_8814B)\n#define BIT_CLEAR_P2POFF_DIS_TXTIME_8814B(x)                                   \\\n\t((x) & (~BITS_P2POFF_DIS_TXTIME_8814B))\n#define BIT_GET_P2POFF_DIS_TXTIME_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8814B) &                          \\\n\t BIT_MASK_P2POFF_DIS_TXTIME_8814B)\n#define BIT_SET_P2POFF_DIS_TXTIME_8814B(x, v)                                  \\\n\t(BIT_CLEAR_P2POFF_DIS_TXTIME_8814B(x) | BIT_P2POFF_DIS_TXTIME_8814B(v))\n\n/* 2 REG_CHG_POWER_BCN_AREA_8814B */\n#define BIT_CHG_POWER_BCN_AREA_8814B BIT(0)\n\n/* 2 REG_NOA_SEL_8814B */\n\n#define BIT_SHIFT_NOA_SEL_V1_8814B 0\n#define BIT_MASK_NOA_SEL_V1_8814B 0x7\n#define BIT_NOA_SEL_V1_8814B(x)                                                \\\n\t(((x) & BIT_MASK_NOA_SEL_V1_8814B) << BIT_SHIFT_NOA_SEL_V1_8814B)\n#define BITS_NOA_SEL_V1_8814B                                                  \\\n\t(BIT_MASK_NOA_SEL_V1_8814B << BIT_SHIFT_NOA_SEL_V1_8814B)\n#define BIT_CLEAR_NOA_SEL_V1_8814B(x) ((x) & (~BITS_NOA_SEL_V1_8814B))\n#define BIT_GET_NOA_SEL_V1_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_NOA_SEL_V1_8814B) & BIT_MASK_NOA_SEL_V1_8814B)\n#define BIT_SET_NOA_SEL_V1_8814B(x, v)                                         \\\n\t(BIT_CLEAR_NOA_SEL_V1_8814B(x) | BIT_NOA_SEL_V1_8814B(v))\n\n/* 2 REG_NOA_PARAM_V1_8814B */\n\n#define BIT_SHIFT_NOA_DURATION_8814B 0\n#define BIT_MASK_NOA_DURATION_8814B 0xffffffffL\n#define BIT_NOA_DURATION_8814B(x)                                              \\\n\t(((x) & BIT_MASK_NOA_DURATION_8814B) << BIT_SHIFT_NOA_DURATION_8814B)\n#define BITS_NOA_DURATION_8814B                                                \\\n\t(BIT_MASK_NOA_DURATION_8814B << BIT_SHIFT_NOA_DURATION_8814B)\n#define BIT_CLEAR_NOA_DURATION_8814B(x) ((x) & (~BITS_NOA_DURATION_8814B))\n#define BIT_GET_NOA_DURATION_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_NOA_DURATION_8814B) & BIT_MASK_NOA_DURATION_8814B)\n#define BIT_SET_NOA_DURATION_8814B(x, v)                                       \\\n\t(BIT_CLEAR_NOA_DURATION_8814B(x) | BIT_NOA_DURATION_8814B(v))\n\n/* 2 REG_NOA_PARAM_1_V1_8814B */\n\n#define BIT_SHIFT_NOA_INTERVAL_8814B 0\n#define BIT_MASK_NOA_INTERVAL_8814B 0xffffffffL\n#define BIT_NOA_INTERVAL_8814B(x)                                              \\\n\t(((x) & BIT_MASK_NOA_INTERVAL_8814B) << BIT_SHIFT_NOA_INTERVAL_8814B)\n#define BITS_NOA_INTERVAL_8814B                                                \\\n\t(BIT_MASK_NOA_INTERVAL_8814B << BIT_SHIFT_NOA_INTERVAL_8814B)\n#define BIT_CLEAR_NOA_INTERVAL_8814B(x) ((x) & (~BITS_NOA_INTERVAL_8814B))\n#define BIT_GET_NOA_INTERVAL_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_NOA_INTERVAL_8814B) & BIT_MASK_NOA_INTERVAL_8814B)\n#define BIT_SET_NOA_INTERVAL_8814B(x, v)                                       \\\n\t(BIT_CLEAR_NOA_INTERVAL_8814B(x) | BIT_NOA_INTERVAL_8814B(v))\n\n/* 2 REG_NOA_PARAM_2_V1_8814B */\n\n#define BIT_SHIFT_NOA_START_TIME_8814B 0\n#define BIT_MASK_NOA_START_TIME_8814B 0xffffffffL\n#define BIT_NOA_START_TIME_8814B(x)                                            \\\n\t(((x) & BIT_MASK_NOA_START_TIME_8814B)                                 \\\n\t << BIT_SHIFT_NOA_START_TIME_8814B)\n#define BITS_NOA_START_TIME_8814B                                              \\\n\t(BIT_MASK_NOA_START_TIME_8814B << BIT_SHIFT_NOA_START_TIME_8814B)\n#define BIT_CLEAR_NOA_START_TIME_8814B(x) ((x) & (~BITS_NOA_START_TIME_8814B))\n#define BIT_GET_NOA_START_TIME_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_NOA_START_TIME_8814B) &                             \\\n\t BIT_MASK_NOA_START_TIME_8814B)\n#define BIT_SET_NOA_START_TIME_8814B(x, v)                                     \\\n\t(BIT_CLEAR_NOA_START_TIME_8814B(x) | BIT_NOA_START_TIME_8814B(v))\n\n/* 2 REG_NOA_PARAM_3_V1_8814B */\n\n#define BIT_SHIFT_NOA_COUNT_V2_8814B 0\n#define BIT_MASK_NOA_COUNT_V2_8814B 0xffffffffL\n#define BIT_NOA_COUNT_V2_8814B(x)                                              \\\n\t(((x) & BIT_MASK_NOA_COUNT_V2_8814B) << BIT_SHIFT_NOA_COUNT_V2_8814B)\n#define BITS_NOA_COUNT_V2_8814B                                                \\\n\t(BIT_MASK_NOA_COUNT_V2_8814B << BIT_SHIFT_NOA_COUNT_V2_8814B)\n#define BIT_CLEAR_NOA_COUNT_V2_8814B(x) ((x) & (~BITS_NOA_COUNT_V2_8814B))\n#define BIT_GET_NOA_COUNT_V2_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_NOA_COUNT_V2_8814B) & BIT_MASK_NOA_COUNT_V2_8814B)\n#define BIT_SET_NOA_COUNT_V2_8814B(x, v)                                       \\\n\t(BIT_CLEAR_NOA_COUNT_V2_8814B(x) | BIT_NOA_COUNT_V2_8814B(v))\n\n/* 2 REG_NOA_ON_ERLY_TIME_V1_8814B */\n\n#define BIT_SHIFT__NOA_ON_ERLY_TIME_8814B 0\n#define BIT_MASK__NOA_ON_ERLY_TIME_8814B 0xff\n#define BIT__NOA_ON_ERLY_TIME_8814B(x)                                         \\\n\t(((x) & BIT_MASK__NOA_ON_ERLY_TIME_8814B)                              \\\n\t << BIT_SHIFT__NOA_ON_ERLY_TIME_8814B)\n#define BITS__NOA_ON_ERLY_TIME_8814B                                           \\\n\t(BIT_MASK__NOA_ON_ERLY_TIME_8814B << BIT_SHIFT__NOA_ON_ERLY_TIME_8814B)\n#define BIT_CLEAR__NOA_ON_ERLY_TIME_8814B(x)                                   \\\n\t((x) & (~BITS__NOA_ON_ERLY_TIME_8814B))\n#define BIT_GET__NOA_ON_ERLY_TIME_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME_8814B) &                          \\\n\t BIT_MASK__NOA_ON_ERLY_TIME_8814B)\n#define BIT_SET__NOA_ON_ERLY_TIME_8814B(x, v)                                  \\\n\t(BIT_CLEAR__NOA_ON_ERLY_TIME_8814B(x) | BIT__NOA_ON_ERLY_TIME_8814B(v))\n\n/* 2 REG_NOA_OFF_ERLY_TIME_V1_8814B */\n\n#define BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B 0\n#define BIT_MASK__NOA_OFF_ERLY_TIME_8814B 0xff\n#define BIT__NOA_OFF_ERLY_TIME_8814B(x)                                        \\\n\t(((x) & BIT_MASK__NOA_OFF_ERLY_TIME_8814B)                             \\\n\t << BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B)\n#define BITS__NOA_OFF_ERLY_TIME_8814B                                          \\\n\t(BIT_MASK__NOA_OFF_ERLY_TIME_8814B                                     \\\n\t << BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B)\n#define BIT_CLEAR__NOA_OFF_ERLY_TIME_8814B(x)                                  \\\n\t((x) & (~BITS__NOA_OFF_ERLY_TIME_8814B))\n#define BIT_GET__NOA_OFF_ERLY_TIME_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B) &                         \\\n\t BIT_MASK__NOA_OFF_ERLY_TIME_8814B)\n#define BIT_SET__NOA_OFF_ERLY_TIME_8814B(x, v)                                 \\\n\t(BIT_CLEAR__NOA_OFF_ERLY_TIME_8814B(x) |                               \\\n\t BIT__NOA_OFF_ERLY_TIME_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_P2PPS_HW_AUTO_PAUSE_CTRL_8814B */\n#define BIT_P2PPS_NOA_STOP_TX_HANG_8814B BIT(31)\n#define BIT_P2PPS_MACID_PAUSE_EN_8814B BIT(11)\n#define BIT_P2PPS__MGQ_PAUSE_8814B BIT(10)\n#define BIT_P2PPS__HIQ_PAUSE_8814B BIT(9)\n#define BIT_P2PPS__BCNQ_PAUSE_8814B BIT(8)\n\n#define BIT_SHIFT_P2PPS_MACID_PAUSE_8814B 0\n#define BIT_MASK_P2PPS_MACID_PAUSE_8814B 0xff\n#define BIT_P2PPS_MACID_PAUSE_8814B(x)                                         \\\n\t(((x) & BIT_MASK_P2PPS_MACID_PAUSE_8814B)                              \\\n\t << BIT_SHIFT_P2PPS_MACID_PAUSE_8814B)\n#define BITS_P2PPS_MACID_PAUSE_8814B                                           \\\n\t(BIT_MASK_P2PPS_MACID_PAUSE_8814B << BIT_SHIFT_P2PPS_MACID_PAUSE_8814B)\n#define BIT_CLEAR_P2PPS_MACID_PAUSE_8814B(x)                                   \\\n\t((x) & (~BITS_P2PPS_MACID_PAUSE_8814B))\n#define BIT_GET_P2PPS_MACID_PAUSE_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_P2PPS_MACID_PAUSE_8814B) &                          \\\n\t BIT_MASK_P2PPS_MACID_PAUSE_8814B)\n#define BIT_SET_P2PPS_MACID_PAUSE_8814B(x, v)                                  \\\n\t(BIT_CLEAR_P2PPS_MACID_PAUSE_8814B(x) | BIT_P2PPS_MACID_PAUSE_8814B(v))\n\n/* 2 REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8814B */\n#define BIT_P2PPS1_NOA_STOP_TX_HANG_8814B BIT(31)\n#define BIT_P2PPS1_MACID_PAUSE_EN_8814B BIT(11)\n#define BIT_P2PPS1__MGQ_PAUSE_8814B BIT(10)\n#define BIT_P2PPS1__HIQ_PAUSE_8814B BIT(9)\n#define BIT_P2PPS1__BCNQ_PAUSE_8814B BIT(8)\n\n#define BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B 0\n#define BIT_MASK_P2PPS1_MACID_PAUSE_8814B 0xff\n#define BIT_P2PPS1_MACID_PAUSE_8814B(x)                                        \\\n\t(((x) & BIT_MASK_P2PPS1_MACID_PAUSE_8814B)                             \\\n\t << BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B)\n#define BITS_P2PPS1_MACID_PAUSE_8814B                                          \\\n\t(BIT_MASK_P2PPS1_MACID_PAUSE_8814B                                     \\\n\t << BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B)\n#define BIT_CLEAR_P2PPS1_MACID_PAUSE_8814B(x)                                  \\\n\t((x) & (~BITS_P2PPS1_MACID_PAUSE_8814B))\n#define BIT_GET_P2PPS1_MACID_PAUSE_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B) &                         \\\n\t BIT_MASK_P2PPS1_MACID_PAUSE_8814B)\n#define BIT_SET_P2PPS1_MACID_PAUSE_8814B(x, v)                                 \\\n\t(BIT_CLEAR_P2PPS1_MACID_PAUSE_8814B(x) |                               \\\n\t BIT_P2PPS1_MACID_PAUSE_8814B(v))\n\n/* 2 REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8814B */\n#define BIT_P2PPS2_NOA_STOP_TX_HANG_8814B BIT(31)\n#define BIT_P2PPS2_MACID_PAUSE_EN_8814B BIT(11)\n#define BIT_P2PPS2__MGQ_PAUSE_8814B BIT(10)\n#define BIT_P2PPS2__HIQ_PAUSE_8814B BIT(9)\n#define BIT_P2PPS2__BCNQ_PAUSE_8814B BIT(8)\n\n#define BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B 0\n#define BIT_MASK_P2PPS2_MACID_PAUSE_8814B 0xff\n#define BIT_P2PPS2_MACID_PAUSE_8814B(x)                                        \\\n\t(((x) & BIT_MASK_P2PPS2_MACID_PAUSE_8814B)                             \\\n\t << BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B)\n#define BITS_P2PPS2_MACID_PAUSE_8814B                                          \\\n\t(BIT_MASK_P2PPS2_MACID_PAUSE_8814B                                     \\\n\t << BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B)\n#define BIT_CLEAR_P2PPS2_MACID_PAUSE_8814B(x)                                  \\\n\t((x) & (~BITS_P2PPS2_MACID_PAUSE_8814B))\n#define BIT_GET_P2PPS2_MACID_PAUSE_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B) &                         \\\n\t BIT_MASK_P2PPS2_MACID_PAUSE_8814B)\n#define BIT_SET_P2PPS2_MACID_PAUSE_8814B(x, v)                                 \\\n\t(BIT_CLEAR_P2PPS2_MACID_PAUSE_8814B(x) |                               \\\n\t BIT_P2PPS2_MACID_PAUSE_8814B(v))\n\n/* 2 REG_RX_TBTT_SHIFT_8814B */\n\n#define BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B 24\n#define BIT_MASK_RX_TBTT_SHIFT_SEL_8814B 0x7\n#define BIT_RX_TBTT_SHIFT_SEL_8814B(x)                                         \\\n\t(((x) & BIT_MASK_RX_TBTT_SHIFT_SEL_8814B)                              \\\n\t << BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B)\n#define BITS_RX_TBTT_SHIFT_SEL_8814B                                           \\\n\t(BIT_MASK_RX_TBTT_SHIFT_SEL_8814B << BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B)\n#define BIT_CLEAR_RX_TBTT_SHIFT_SEL_8814B(x)                                   \\\n\t((x) & (~BITS_RX_TBTT_SHIFT_SEL_8814B))\n#define BIT_GET_RX_TBTT_SHIFT_SEL_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B) &                          \\\n\t BIT_MASK_RX_TBTT_SHIFT_SEL_8814B)\n#define BIT_SET_RX_TBTT_SHIFT_SEL_8814B(x, v)                                  \\\n\t(BIT_CLEAR_RX_TBTT_SHIFT_SEL_8814B(x) | BIT_RX_TBTT_SHIFT_SEL_8814B(v))\n\n#define BIT_RX_TBTT_SHIFT_RW_FLAG_8814B BIT(15)\n\n#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B 0\n#define BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B 0xfff\n#define BIT_RX_TBTT_SHIFT_OFFSET_8814B(x)                                      \\\n\t(((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B)                           \\\n\t << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B)\n#define BITS_RX_TBTT_SHIFT_OFFSET_8814B                                        \\\n\t(BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B                                   \\\n\t << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B)\n#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_8814B(x)                                \\\n\t((x) & (~BITS_RX_TBTT_SHIFT_OFFSET_8814B))\n#define BIT_GET_RX_TBTT_SHIFT_OFFSET_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B) &                       \\\n\t BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B)\n#define BIT_SET_RX_TBTT_SHIFT_OFFSET_8814B(x, v)                               \\\n\t(BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_8814B(x) |                             \\\n\t BIT_RX_TBTT_SHIFT_OFFSET_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_FREERUN_CNT_LOW_8814B */\n\n#define BIT_SHIFT_FREERUN_CNT_LOW_8814B 0\n#define BIT_MASK_FREERUN_CNT_LOW_8814B 0xffffffffL\n#define BIT_FREERUN_CNT_LOW_8814B(x)                                           \\\n\t(((x) & BIT_MASK_FREERUN_CNT_LOW_8814B)                                \\\n\t << BIT_SHIFT_FREERUN_CNT_LOW_8814B)\n#define BITS_FREERUN_CNT_LOW_8814B                                             \\\n\t(BIT_MASK_FREERUN_CNT_LOW_8814B << BIT_SHIFT_FREERUN_CNT_LOW_8814B)\n#define BIT_CLEAR_FREERUN_CNT_LOW_8814B(x) ((x) & (~BITS_FREERUN_CNT_LOW_8814B))\n#define BIT_GET_FREERUN_CNT_LOW_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_FREERUN_CNT_LOW_8814B) &                            \\\n\t BIT_MASK_FREERUN_CNT_LOW_8814B)\n#define BIT_SET_FREERUN_CNT_LOW_8814B(x, v)                                    \\\n\t(BIT_CLEAR_FREERUN_CNT_LOW_8814B(x) | BIT_FREERUN_CNT_LOW_8814B(v))\n\n/* 2 REG_FREERUN_CNT_HIGH_8814B */\n\n#define BIT_SHIFT_FREERUN_CNT_HIGH_8814B 0\n#define BIT_MASK_FREERUN_CNT_HIGH_8814B 0xffffffffL\n#define BIT_FREERUN_CNT_HIGH_8814B(x)                                          \\\n\t(((x) & BIT_MASK_FREERUN_CNT_HIGH_8814B)                               \\\n\t << BIT_SHIFT_FREERUN_CNT_HIGH_8814B)\n#define BITS_FREERUN_CNT_HIGH_8814B                                            \\\n\t(BIT_MASK_FREERUN_CNT_HIGH_8814B << BIT_SHIFT_FREERUN_CNT_HIGH_8814B)\n#define BIT_CLEAR_FREERUN_CNT_HIGH_8814B(x)                                    \\\n\t((x) & (~BITS_FREERUN_CNT_HIGH_8814B))\n#define BIT_GET_FREERUN_CNT_HIGH_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_FREERUN_CNT_HIGH_8814B) &                           \\\n\t BIT_MASK_FREERUN_CNT_HIGH_8814B)\n#define BIT_SET_FREERUN_CNT_HIGH_8814B(x, v)                                   \\\n\t(BIT_CLEAR_FREERUN_CNT_HIGH_8814B(x) | BIT_FREERUN_CNT_HIGH_8814B(v))\n\n/* 2 REG_CPUMGQ_TX_TIMER_V1_8814B */\n\n#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B 0\n#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B 0xffffffffL\n#define BIT_CPUMGQ_TX_TIMER_V1_8814B(x)                                        \\\n\t(((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B)                             \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B)\n#define BITS_CPUMGQ_TX_TIMER_V1_8814B                                          \\\n\t(BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B                                     \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B)\n#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8814B(x)                                  \\\n\t((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8814B))\n#define BIT_GET_CPUMGQ_TX_TIMER_V1_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B) &                         \\\n\t BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B)\n#define BIT_SET_CPUMGQ_TX_TIMER_V1_8814B(x, v)                                 \\\n\t(BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8814B(x) |                               \\\n\t BIT_CPUMGQ_TX_TIMER_V1_8814B(v))\n\n/* 2 REG_PS_TIMER_0_8814B */\n\n#define BIT_SHIFT_PS_TIMER_0_8814B 0\n#define BIT_MASK_PS_TIMER_0_8814B 0xffffffffL\n#define BIT_PS_TIMER_0_8814B(x)                                                \\\n\t(((x) & BIT_MASK_PS_TIMER_0_8814B) << BIT_SHIFT_PS_TIMER_0_8814B)\n#define BITS_PS_TIMER_0_8814B                                                  \\\n\t(BIT_MASK_PS_TIMER_0_8814B << BIT_SHIFT_PS_TIMER_0_8814B)\n#define BIT_CLEAR_PS_TIMER_0_8814B(x) ((x) & (~BITS_PS_TIMER_0_8814B))\n#define BIT_GET_PS_TIMER_0_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_0_8814B) & BIT_MASK_PS_TIMER_0_8814B)\n#define BIT_SET_PS_TIMER_0_8814B(x, v)                                         \\\n\t(BIT_CLEAR_PS_TIMER_0_8814B(x) | BIT_PS_TIMER_0_8814B(v))\n\n/* 2 REG_PS_TIMER_1_8814B */\n\n#define BIT_SHIFT_PS_TIMER_1_8814B 0\n#define BIT_MASK_PS_TIMER_1_8814B 0xffffffffL\n#define BIT_PS_TIMER_1_8814B(x)                                                \\\n\t(((x) & BIT_MASK_PS_TIMER_1_8814B) << BIT_SHIFT_PS_TIMER_1_8814B)\n#define BITS_PS_TIMER_1_8814B                                                  \\\n\t(BIT_MASK_PS_TIMER_1_8814B << BIT_SHIFT_PS_TIMER_1_8814B)\n#define BIT_CLEAR_PS_TIMER_1_8814B(x) ((x) & (~BITS_PS_TIMER_1_8814B))\n#define BIT_GET_PS_TIMER_1_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_1_8814B) & BIT_MASK_PS_TIMER_1_8814B)\n#define BIT_SET_PS_TIMER_1_8814B(x, v)                                         \\\n\t(BIT_CLEAR_PS_TIMER_1_8814B(x) | BIT_PS_TIMER_1_8814B(v))\n\n/* 2 REG_PS_TIMER_2_8814B */\n\n#define BIT_SHIFT_PS_TIMER_2_8814B 0\n#define BIT_MASK_PS_TIMER_2_8814B 0xffffffffL\n#define BIT_PS_TIMER_2_8814B(x)                                                \\\n\t(((x) & BIT_MASK_PS_TIMER_2_8814B) << BIT_SHIFT_PS_TIMER_2_8814B)\n#define BITS_PS_TIMER_2_8814B                                                  \\\n\t(BIT_MASK_PS_TIMER_2_8814B << BIT_SHIFT_PS_TIMER_2_8814B)\n#define BIT_CLEAR_PS_TIMER_2_8814B(x) ((x) & (~BITS_PS_TIMER_2_8814B))\n#define BIT_GET_PS_TIMER_2_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_2_8814B) & BIT_MASK_PS_TIMER_2_8814B)\n#define BIT_SET_PS_TIMER_2_8814B(x, v)                                         \\\n\t(BIT_CLEAR_PS_TIMER_2_8814B(x) | BIT_PS_TIMER_2_8814B(v))\n\n/* 2 REG_PS_TIMER_3_8814B */\n\n#define BIT_SHIFT_PS_TIMER_3_8814B 0\n#define BIT_MASK_PS_TIMER_3_8814B 0xffffffffL\n#define BIT_PS_TIMER_3_8814B(x)                                                \\\n\t(((x) & BIT_MASK_PS_TIMER_3_8814B) << BIT_SHIFT_PS_TIMER_3_8814B)\n#define BITS_PS_TIMER_3_8814B                                                  \\\n\t(BIT_MASK_PS_TIMER_3_8814B << BIT_SHIFT_PS_TIMER_3_8814B)\n#define BIT_CLEAR_PS_TIMER_3_8814B(x) ((x) & (~BITS_PS_TIMER_3_8814B))\n#define BIT_GET_PS_TIMER_3_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_3_8814B) & BIT_MASK_PS_TIMER_3_8814B)\n#define BIT_SET_PS_TIMER_3_8814B(x, v)                                         \\\n\t(BIT_CLEAR_PS_TIMER_3_8814B(x) | BIT_PS_TIMER_3_8814B(v))\n\n/* 2 REG_PS_TIMER_4_8814B */\n\n#define BIT_SHIFT_PS_TIMER_4_8814B 0\n#define BIT_MASK_PS_TIMER_4_8814B 0xffffffffL\n#define BIT_PS_TIMER_4_8814B(x)                                                \\\n\t(((x) & BIT_MASK_PS_TIMER_4_8814B) << BIT_SHIFT_PS_TIMER_4_8814B)\n#define BITS_PS_TIMER_4_8814B                                                  \\\n\t(BIT_MASK_PS_TIMER_4_8814B << BIT_SHIFT_PS_TIMER_4_8814B)\n#define BIT_CLEAR_PS_TIMER_4_8814B(x) ((x) & (~BITS_PS_TIMER_4_8814B))\n#define BIT_GET_PS_TIMER_4_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_4_8814B) & BIT_MASK_PS_TIMER_4_8814B)\n#define BIT_SET_PS_TIMER_4_8814B(x, v)                                         \\\n\t(BIT_CLEAR_PS_TIMER_4_8814B(x) | BIT_PS_TIMER_4_8814B(v))\n\n/* 2 REG_PS_TIMER_5_8814B */\n\n#define BIT_SHIFT_PS_TIMER_5_8814B 0\n#define BIT_MASK_PS_TIMER_5_8814B 0xffffffffL\n#define BIT_PS_TIMER_5_8814B(x)                                                \\\n\t(((x) & BIT_MASK_PS_TIMER_5_8814B) << BIT_SHIFT_PS_TIMER_5_8814B)\n#define BITS_PS_TIMER_5_8814B                                                  \\\n\t(BIT_MASK_PS_TIMER_5_8814B << BIT_SHIFT_PS_TIMER_5_8814B)\n#define BIT_CLEAR_PS_TIMER_5_8814B(x) ((x) & (~BITS_PS_TIMER_5_8814B))\n#define BIT_GET_PS_TIMER_5_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_5_8814B) & BIT_MASK_PS_TIMER_5_8814B)\n#define BIT_SET_PS_TIMER_5_8814B(x, v)                                         \\\n\t(BIT_CLEAR_PS_TIMER_5_8814B(x) | BIT_PS_TIMER_5_8814B(v))\n\n/* 2 REG_PS_TIMER_01_CTRL_8814B */\n\n#define BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B 24\n#define BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B 0xff\n#define BIT_PS_TIMER_1_EARLY_TIME_8814B(x)                                     \\\n\t(((x) & BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B)                          \\\n\t << BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B)\n#define BITS_PS_TIMER_1_EARLY_TIME_8814B                                       \\\n\t(BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B                                  \\\n\t << BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B)\n#define BIT_CLEAR_PS_TIMER_1_EARLY_TIME_8814B(x)                               \\\n\t((x) & (~BITS_PS_TIMER_1_EARLY_TIME_8814B))\n#define BIT_GET_PS_TIMER_1_EARLY_TIME_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B) &                      \\\n\t BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B)\n#define BIT_SET_PS_TIMER_1_EARLY_TIME_8814B(x, v)                              \\\n\t(BIT_CLEAR_PS_TIMER_1_EARLY_TIME_8814B(x) |                            \\\n\t BIT_PS_TIMER_1_EARLY_TIME_8814B(v))\n\n#define BIT_PS_TIMER_1_EN_8814B BIT(23)\n\n#define BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B 16\n#define BIT_MASK_PS_TIMER_1_TSF_SEL_8814B 0x7\n#define BIT_PS_TIMER_1_TSF_SEL_8814B(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_1_TSF_SEL_8814B)                             \\\n\t << BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B)\n#define BITS_PS_TIMER_1_TSF_SEL_8814B                                          \\\n\t(BIT_MASK_PS_TIMER_1_TSF_SEL_8814B                                     \\\n\t << BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B)\n#define BIT_CLEAR_PS_TIMER_1_TSF_SEL_8814B(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_1_TSF_SEL_8814B))\n#define BIT_GET_PS_TIMER_1_TSF_SEL_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B) &                         \\\n\t BIT_MASK_PS_TIMER_1_TSF_SEL_8814B)\n#define BIT_SET_PS_TIMER_1_TSF_SEL_8814B(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_1_TSF_SEL_8814B(x) |                               \\\n\t BIT_PS_TIMER_1_TSF_SEL_8814B(v))\n\n#define BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B 8\n#define BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B 0xff\n#define BIT_PS_TIMER_0_EARLY_TIME_8814B(x)                                     \\\n\t(((x) & BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B)                          \\\n\t << BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B)\n#define BITS_PS_TIMER_0_EARLY_TIME_8814B                                       \\\n\t(BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B                                  \\\n\t << BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B)\n#define BIT_CLEAR_PS_TIMER_0_EARLY_TIME_8814B(x)                               \\\n\t((x) & (~BITS_PS_TIMER_0_EARLY_TIME_8814B))\n#define BIT_GET_PS_TIMER_0_EARLY_TIME_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B) &                      \\\n\t BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B)\n#define BIT_SET_PS_TIMER_0_EARLY_TIME_8814B(x, v)                              \\\n\t(BIT_CLEAR_PS_TIMER_0_EARLY_TIME_8814B(x) |                            \\\n\t BIT_PS_TIMER_0_EARLY_TIME_8814B(v))\n\n#define BIT_PS_TIMER_0_EN_8814B BIT(7)\n\n#define BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B 0\n#define BIT_MASK_PS_TIMER_0_TSF_SEL_8814B 0x7\n#define BIT_PS_TIMER_0_TSF_SEL_8814B(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_0_TSF_SEL_8814B)                             \\\n\t << BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B)\n#define BITS_PS_TIMER_0_TSF_SEL_8814B                                          \\\n\t(BIT_MASK_PS_TIMER_0_TSF_SEL_8814B                                     \\\n\t << BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B)\n#define BIT_CLEAR_PS_TIMER_0_TSF_SEL_8814B(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_0_TSF_SEL_8814B))\n#define BIT_GET_PS_TIMER_0_TSF_SEL_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B) &                         \\\n\t BIT_MASK_PS_TIMER_0_TSF_SEL_8814B)\n#define BIT_SET_PS_TIMER_0_TSF_SEL_8814B(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_0_TSF_SEL_8814B(x) |                               \\\n\t BIT_PS_TIMER_0_TSF_SEL_8814B(v))\n\n/* 2 REG_PS_TIMER_23_CTRL_8814B */\n\n#define BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B 24\n#define BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B 0xff\n#define BIT_PS_TIMER_3_EARLY_TIME_8814B(x)                                     \\\n\t(((x) & BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B)                          \\\n\t << BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B)\n#define BITS_PS_TIMER_3_EARLY_TIME_8814B                                       \\\n\t(BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B                                  \\\n\t << BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B)\n#define BIT_CLEAR_PS_TIMER_3_EARLY_TIME_8814B(x)                               \\\n\t((x) & (~BITS_PS_TIMER_3_EARLY_TIME_8814B))\n#define BIT_GET_PS_TIMER_3_EARLY_TIME_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B) &                      \\\n\t BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B)\n#define BIT_SET_PS_TIMER_3_EARLY_TIME_8814B(x, v)                              \\\n\t(BIT_CLEAR_PS_TIMER_3_EARLY_TIME_8814B(x) |                            \\\n\t BIT_PS_TIMER_3_EARLY_TIME_8814B(v))\n\n#define BIT_PS_TIMER_3_EN_8814B BIT(23)\n\n#define BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B 16\n#define BIT_MASK_PS_TIMER_3_TSF_SEL_8814B 0x7\n#define BIT_PS_TIMER_3_TSF_SEL_8814B(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_3_TSF_SEL_8814B)                             \\\n\t << BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B)\n#define BITS_PS_TIMER_3_TSF_SEL_8814B                                          \\\n\t(BIT_MASK_PS_TIMER_3_TSF_SEL_8814B                                     \\\n\t << BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B)\n#define BIT_CLEAR_PS_TIMER_3_TSF_SEL_8814B(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_3_TSF_SEL_8814B))\n#define BIT_GET_PS_TIMER_3_TSF_SEL_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B) &                         \\\n\t BIT_MASK_PS_TIMER_3_TSF_SEL_8814B)\n#define BIT_SET_PS_TIMER_3_TSF_SEL_8814B(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_3_TSF_SEL_8814B(x) |                               \\\n\t BIT_PS_TIMER_3_TSF_SEL_8814B(v))\n\n#define BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B 8\n#define BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B 0xff\n#define BIT_PS_TIMER_2_EARLY_TIME_8814B(x)                                     \\\n\t(((x) & BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B)                          \\\n\t << BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B)\n#define BITS_PS_TIMER_2_EARLY_TIME_8814B                                       \\\n\t(BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B                                  \\\n\t << BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B)\n#define BIT_CLEAR_PS_TIMER_2_EARLY_TIME_8814B(x)                               \\\n\t((x) & (~BITS_PS_TIMER_2_EARLY_TIME_8814B))\n#define BIT_GET_PS_TIMER_2_EARLY_TIME_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B) &                      \\\n\t BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B)\n#define BIT_SET_PS_TIMER_2_EARLY_TIME_8814B(x, v)                              \\\n\t(BIT_CLEAR_PS_TIMER_2_EARLY_TIME_8814B(x) |                            \\\n\t BIT_PS_TIMER_2_EARLY_TIME_8814B(v))\n\n#define BIT_PS_TIMER_2_EN_8814B BIT(7)\n\n#define BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B 0\n#define BIT_MASK_PS_TIMER_2_TSF_SEL_8814B 0x7\n#define BIT_PS_TIMER_2_TSF_SEL_8814B(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_2_TSF_SEL_8814B)                             \\\n\t << BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B)\n#define BITS_PS_TIMER_2_TSF_SEL_8814B                                          \\\n\t(BIT_MASK_PS_TIMER_2_TSF_SEL_8814B                                     \\\n\t << BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B)\n#define BIT_CLEAR_PS_TIMER_2_TSF_SEL_8814B(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_2_TSF_SEL_8814B))\n#define BIT_GET_PS_TIMER_2_TSF_SEL_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B) &                         \\\n\t BIT_MASK_PS_TIMER_2_TSF_SEL_8814B)\n#define BIT_SET_PS_TIMER_2_TSF_SEL_8814B(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_2_TSF_SEL_8814B(x) |                               \\\n\t BIT_PS_TIMER_2_TSF_SEL_8814B(v))\n\n/* 2 REG_PS_TIMER_45_CTRL_8814B */\n\n#define BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B 24\n#define BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B 0xff\n#define BIT_PS_TIMER_5_EARLY_TIME_8814B(x)                                     \\\n\t(((x) & BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B)                          \\\n\t << BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B)\n#define BITS_PS_TIMER_5_EARLY_TIME_8814B                                       \\\n\t(BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B                                  \\\n\t << BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B)\n#define BIT_CLEAR_PS_TIMER_5_EARLY_TIME_8814B(x)                               \\\n\t((x) & (~BITS_PS_TIMER_5_EARLY_TIME_8814B))\n#define BIT_GET_PS_TIMER_5_EARLY_TIME_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B) &                      \\\n\t BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B)\n#define BIT_SET_PS_TIMER_5_EARLY_TIME_8814B(x, v)                              \\\n\t(BIT_CLEAR_PS_TIMER_5_EARLY_TIME_8814B(x) |                            \\\n\t BIT_PS_TIMER_5_EARLY_TIME_8814B(v))\n\n#define BIT_PS_TIMER_5_EN_8814B BIT(23)\n\n#define BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B 16\n#define BIT_MASK_PS_TIMER_5_TSF_SEL_8814B 0x7\n#define BIT_PS_TIMER_5_TSF_SEL_8814B(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_5_TSF_SEL_8814B)                             \\\n\t << BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B)\n#define BITS_PS_TIMER_5_TSF_SEL_8814B                                          \\\n\t(BIT_MASK_PS_TIMER_5_TSF_SEL_8814B                                     \\\n\t << BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B)\n#define BIT_CLEAR_PS_TIMER_5_TSF_SEL_8814B(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_5_TSF_SEL_8814B))\n#define BIT_GET_PS_TIMER_5_TSF_SEL_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B) &                         \\\n\t BIT_MASK_PS_TIMER_5_TSF_SEL_8814B)\n#define BIT_SET_PS_TIMER_5_TSF_SEL_8814B(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_5_TSF_SEL_8814B(x) |                               \\\n\t BIT_PS_TIMER_5_TSF_SEL_8814B(v))\n\n#define BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B 8\n#define BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B 0xff\n#define BIT_PS_TIMER_4_EARLY_TIME_8814B(x)                                     \\\n\t(((x) & BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B)                          \\\n\t << BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B)\n#define BITS_PS_TIMER_4_EARLY_TIME_8814B                                       \\\n\t(BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B                                  \\\n\t << BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B)\n#define BIT_CLEAR_PS_TIMER_4_EARLY_TIME_8814B(x)                               \\\n\t((x) & (~BITS_PS_TIMER_4_EARLY_TIME_8814B))\n#define BIT_GET_PS_TIMER_4_EARLY_TIME_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B) &                      \\\n\t BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B)\n#define BIT_SET_PS_TIMER_4_EARLY_TIME_8814B(x, v)                              \\\n\t(BIT_CLEAR_PS_TIMER_4_EARLY_TIME_8814B(x) |                            \\\n\t BIT_PS_TIMER_4_EARLY_TIME_8814B(v))\n\n#define BIT_PS_TIMER_4_EN_8814B BIT(7)\n\n#define BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B 0\n#define BIT_MASK_PS_TIMER_4_TSF_SEL_8814B 0x7\n#define BIT_PS_TIMER_4_TSF_SEL_8814B(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_4_TSF_SEL_8814B)                             \\\n\t << BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B)\n#define BITS_PS_TIMER_4_TSF_SEL_8814B                                          \\\n\t(BIT_MASK_PS_TIMER_4_TSF_SEL_8814B                                     \\\n\t << BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B)\n#define BIT_CLEAR_PS_TIMER_4_TSF_SEL_8814B(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_4_TSF_SEL_8814B))\n#define BIT_GET_PS_TIMER_4_TSF_SEL_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B) &                         \\\n\t BIT_MASK_PS_TIMER_4_TSF_SEL_8814B)\n#define BIT_SET_PS_TIMER_4_TSF_SEL_8814B(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_4_TSF_SEL_8814B(x) |                               \\\n\t BIT_PS_TIMER_4_TSF_SEL_8814B(v))\n\n/* 2 REG_CPUMGQ_FREERUN_TIMER_CTRL_8814B */\n#define BIT_FREECNT_RST_V1_8814B BIT(23)\n#define BIT_EN_FREECNT_V1_8814B BIT(16)\n\n#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B 8\n#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B 0xff\n#define BIT_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x)                                  \\\n\t(((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B)                       \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B)\n#define BITS_CPUMGQ_TX_TIMER_EARLY_V1_8814B                                    \\\n\t(BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B                               \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B)\n#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x)                            \\\n\t((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_V1_8814B))\n#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x)                              \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B) &                   \\\n\t BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B)\n#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x, v)                           \\\n\t(BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x) |                         \\\n\t BIT_CPUMGQ_TX_TIMER_EARLY_V1_8814B(v))\n\n#define BIT_CPUMGQ_TIMER_EN_V1_8814B BIT(7)\n#define BIT_CPUMGQ_DROP_BY_HOLDTIME_8814B BIT(5)\n#define BIT_CPUMGQ_TX_EN_V1_8814B BIT(4)\n\n#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B 0\n#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B 0x7\n#define BIT_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x)                                   \\\n\t(((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B)                        \\\n\t << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B)\n#define BITS_CPUMGQ_TIMER_TSF_SEL_V1_8814B                                     \\\n\t(BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B                                \\\n\t << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B)\n#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x)                             \\\n\t((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_V1_8814B))\n#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x)                               \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B) &                    \\\n\t BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B)\n#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x, v)                            \\\n\t(BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x) |                          \\\n\t BIT_CPUMGQ_TIMER_TSF_SEL_V1_8814B(v))\n\n/* 2 REG_CPUMGQ_PROHIBIT_8814B */\n\n#define BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B 8\n#define BIT_MASK_CPUMGQ_HOLD_TIME_8814B 0xfff\n#define BIT_CPUMGQ_HOLD_TIME_8814B(x)                                          \\\n\t(((x) & BIT_MASK_CPUMGQ_HOLD_TIME_8814B)                               \\\n\t << BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B)\n#define BITS_CPUMGQ_HOLD_TIME_8814B                                            \\\n\t(BIT_MASK_CPUMGQ_HOLD_TIME_8814B << BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B)\n#define BIT_CLEAR_CPUMGQ_HOLD_TIME_8814B(x)                                    \\\n\t((x) & (~BITS_CPUMGQ_HOLD_TIME_8814B))\n#define BIT_GET_CPUMGQ_HOLD_TIME_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B) &                           \\\n\t BIT_MASK_CPUMGQ_HOLD_TIME_8814B)\n#define BIT_SET_CPUMGQ_HOLD_TIME_8814B(x, v)                                   \\\n\t(BIT_CLEAR_CPUMGQ_HOLD_TIME_8814B(x) | BIT_CPUMGQ_HOLD_TIME_8814B(v))\n\n#define BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B 0\n#define BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B 0xf\n#define BIT_CPUMGQ_PROHIBIT_SETUP_8814B(x)                                     \\\n\t(((x) & BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B)                          \\\n\t << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B)\n#define BITS_CPUMGQ_PROHIBIT_SETUP_8814B                                       \\\n\t(BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B                                  \\\n\t << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B)\n#define BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP_8814B(x)                               \\\n\t((x) & (~BITS_CPUMGQ_PROHIBIT_SETUP_8814B))\n#define BIT_GET_CPUMGQ_PROHIBIT_SETUP_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B) &                      \\\n\t BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B)\n#define BIT_SET_CPUMGQ_PROHIBIT_SETUP_8814B(x, v)                              \\\n\t(BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP_8814B(x) |                            \\\n\t BIT_CPUMGQ_PROHIBIT_SETUP_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_TIMER_COMPARE_8814B */\n#define BIT_COMP_TRIGGER_8814B BIT(7)\n\n#define BIT_SHIFT_Y_COMP_8814B 4\n#define BIT_MASK_Y_COMP_8814B 0x7\n#define BIT_Y_COMP_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_Y_COMP_8814B) << BIT_SHIFT_Y_COMP_8814B)\n#define BITS_Y_COMP_8814B (BIT_MASK_Y_COMP_8814B << BIT_SHIFT_Y_COMP_8814B)\n#define BIT_CLEAR_Y_COMP_8814B(x) ((x) & (~BITS_Y_COMP_8814B))\n#define BIT_GET_Y_COMP_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_Y_COMP_8814B) & BIT_MASK_Y_COMP_8814B)\n#define BIT_SET_Y_COMP_8814B(x, v)                                             \\\n\t(BIT_CLEAR_Y_COMP_8814B(x) | BIT_Y_COMP_8814B(v))\n\n#define BIT_X_COMP_Y_OVERFLOW_8814B BIT(3)\n\n#define BIT_SHIFT_X_COMP_8814B 0\n#define BIT_MASK_X_COMP_8814B 0x7\n#define BIT_X_COMP_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_X_COMP_8814B) << BIT_SHIFT_X_COMP_8814B)\n#define BITS_X_COMP_8814B (BIT_MASK_X_COMP_8814B << BIT_SHIFT_X_COMP_8814B)\n#define BIT_CLEAR_X_COMP_8814B(x) ((x) & (~BITS_X_COMP_8814B))\n#define BIT_GET_X_COMP_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_X_COMP_8814B) & BIT_MASK_X_COMP_8814B)\n#define BIT_SET_X_COMP_8814B(x, v)                                             \\\n\t(BIT_CLEAR_X_COMP_8814B(x) | BIT_X_COMP_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_TIMER_COMPARE_VALUE_LOW_8814B */\n\n#define BIT_SHIFT_COMP_VALUE_LOW_8814B 0\n#define BIT_MASK_COMP_VALUE_LOW_8814B 0xffffffffL\n#define BIT_COMP_VALUE_LOW_8814B(x)                                            \\\n\t(((x) & BIT_MASK_COMP_VALUE_LOW_8814B)                                 \\\n\t << BIT_SHIFT_COMP_VALUE_LOW_8814B)\n#define BITS_COMP_VALUE_LOW_8814B                                              \\\n\t(BIT_MASK_COMP_VALUE_LOW_8814B << BIT_SHIFT_COMP_VALUE_LOW_8814B)\n#define BIT_CLEAR_COMP_VALUE_LOW_8814B(x) ((x) & (~BITS_COMP_VALUE_LOW_8814B))\n#define BIT_GET_COMP_VALUE_LOW_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_COMP_VALUE_LOW_8814B) &                             \\\n\t BIT_MASK_COMP_VALUE_LOW_8814B)\n#define BIT_SET_COMP_VALUE_LOW_8814B(x, v)                                     \\\n\t(BIT_CLEAR_COMP_VALUE_LOW_8814B(x) | BIT_COMP_VALUE_LOW_8814B(v))\n\n/* 2 REG_TIMER_COMPARE_VALUE_HIGH_8814B */\n\n#define BIT_SHIFT_COMP_VALUE_HIGH_8814B 0\n#define BIT_MASK_COMP_VALUE_HIGH_8814B 0xffffffffL\n#define BIT_COMP_VALUE_HIGH_8814B(x)                                           \\\n\t(((x) & BIT_MASK_COMP_VALUE_HIGH_8814B)                                \\\n\t << BIT_SHIFT_COMP_VALUE_HIGH_8814B)\n#define BITS_COMP_VALUE_HIGH_8814B                                             \\\n\t(BIT_MASK_COMP_VALUE_HIGH_8814B << BIT_SHIFT_COMP_VALUE_HIGH_8814B)\n#define BIT_CLEAR_COMP_VALUE_HIGH_8814B(x) ((x) & (~BITS_COMP_VALUE_HIGH_8814B))\n#define BIT_GET_COMP_VALUE_HIGH_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_COMP_VALUE_HIGH_8814B) &                            \\\n\t BIT_MASK_COMP_VALUE_HIGH_8814B)\n#define BIT_SET_COMP_VALUE_HIGH_8814B(x, v)                                    \\\n\t(BIT_CLEAR_COMP_VALUE_HIGH_8814B(x) | BIT_COMP_VALUE_HIGH_8814B(v))\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_SCHEDULER_COUNTER_8814B */\n\n#define BIT_SHIFT__SCHEDULER_COUNTER_8814B 16\n#define BIT_MASK__SCHEDULER_COUNTER_8814B 0xffff\n#define BIT__SCHEDULER_COUNTER_8814B(x)                                        \\\n\t(((x) & BIT_MASK__SCHEDULER_COUNTER_8814B)                             \\\n\t << BIT_SHIFT__SCHEDULER_COUNTER_8814B)\n#define BITS__SCHEDULER_COUNTER_8814B                                          \\\n\t(BIT_MASK__SCHEDULER_COUNTER_8814B                                     \\\n\t << BIT_SHIFT__SCHEDULER_COUNTER_8814B)\n#define BIT_CLEAR__SCHEDULER_COUNTER_8814B(x)                                  \\\n\t((x) & (~BITS__SCHEDULER_COUNTER_8814B))\n#define BIT_GET__SCHEDULER_COUNTER_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT__SCHEDULER_COUNTER_8814B) &                         \\\n\t BIT_MASK__SCHEDULER_COUNTER_8814B)\n#define BIT_SET__SCHEDULER_COUNTER_8814B(x, v)                                 \\\n\t(BIT_CLEAR__SCHEDULER_COUNTER_8814B(x) |                               \\\n\t BIT__SCHEDULER_COUNTER_8814B(v))\n\n#define BIT__SCHEDULER_COUNTER_RST_8814B BIT(8)\n\n#define BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B 0\n#define BIT_MASK_SCHEDULER_COUNTER_SEL_8814B 0xff\n#define BIT_SCHEDULER_COUNTER_SEL_8814B(x)                                     \\\n\t(((x) & BIT_MASK_SCHEDULER_COUNTER_SEL_8814B)                          \\\n\t << BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B)\n#define BITS_SCHEDULER_COUNTER_SEL_8814B                                       \\\n\t(BIT_MASK_SCHEDULER_COUNTER_SEL_8814B                                  \\\n\t << BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B)\n#define BIT_CLEAR_SCHEDULER_COUNTER_SEL_8814B(x)                               \\\n\t((x) & (~BITS_SCHEDULER_COUNTER_SEL_8814B))\n#define BIT_GET_SCHEDULER_COUNTER_SEL_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B) &                      \\\n\t BIT_MASK_SCHEDULER_COUNTER_SEL_8814B)\n#define BIT_SET_SCHEDULER_COUNTER_SEL_8814B(x, v)                              \\\n\t(BIT_CLEAR_SCHEDULER_COUNTER_SEL_8814B(x) |                            \\\n\t BIT_SCHEDULER_COUNTER_SEL_8814B(v))\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_WMAC_CR_8814B (WMAC CR AND APSD CONTROL REGISTER) */\n#define BIT_IC_MACPHY_M_8814B BIT(0)\n\n/* 2 REG_WMAC_FWPKT_CR_8814B */\n#define BIT_FWEN_8814B BIT(7)\n#define BIT_PHYSTS_PKT_CTRL_8814B BIT(6)\n#define BIT_FWFULL_TO_RXFF_EN_8814B BIT(5)\n#define BIT_APPHDR_MIDSRCH_FAIL_8814B BIT(4)\n#define BIT_FWPARSING_EN_8814B BIT(3)\n\n#define BIT_SHIFT_APPEND_MHDR_LEN_8814B 0\n#define BIT_MASK_APPEND_MHDR_LEN_8814B 0x7\n#define BIT_APPEND_MHDR_LEN_8814B(x)                                           \\\n\t(((x) & BIT_MASK_APPEND_MHDR_LEN_8814B)                                \\\n\t << BIT_SHIFT_APPEND_MHDR_LEN_8814B)\n#define BITS_APPEND_MHDR_LEN_8814B                                             \\\n\t(BIT_MASK_APPEND_MHDR_LEN_8814B << BIT_SHIFT_APPEND_MHDR_LEN_8814B)\n#define BIT_CLEAR_APPEND_MHDR_LEN_8814B(x) ((x) & (~BITS_APPEND_MHDR_LEN_8814B))\n#define BIT_GET_APPEND_MHDR_LEN_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8814B) &                            \\\n\t BIT_MASK_APPEND_MHDR_LEN_8814B)\n#define BIT_SET_APPEND_MHDR_LEN_8814B(x, v)                                    \\\n\t(BIT_CLEAR_APPEND_MHDR_LEN_8814B(x) | BIT_APPEND_MHDR_LEN_8814B(v))\n\n/* 2 REG_FW_STS_FILTER_8814B */\n#define BIT_DATA_FW_STS_FILTER_8814B BIT(2)\n#define BIT_CTRL_FW_STS_FILTER_8814B BIT(1)\n#define BIT_MGNT_FW_STS_FILTER_8814B BIT(0)\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_TCR_8814B (TRANSMISSION CONFIGURATION REGISTER) */\n#define BIT_WMAC_EN_RTS_ADDR_8814B BIT(31)\n#define BIT_WMAC_DISABLE_CCK_8814B BIT(30)\n#define BIT_WMAC_RAW_LEN_8814B BIT(29)\n#define BIT_WMAC_NOTX_IN_RXNDP_8814B BIT(28)\n#define BIT_WMAC_EN_EOF_8814B BIT(27)\n#define BIT_WMAC_BF_SEL_8814B BIT(26)\n#define BIT_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(24)\n#define BIT_WMAC_SMOOTH_VAL_8814B BIT(23)\n#define BIT_WMAC_EN_SCRAM_INC_8814B BIT(22)\n#define BIT_UNDERFLOWEN_CMPLEN_SEL_8814B BIT(21)\n#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8814B BIT(20)\n#define BIT_WMAC_TCR_EN_20MST_8814B BIT(19)\n#define BIT_WMAC_DIS_SIGTA_8814B BIT(18)\n#define BIT_WMAC_DIS_A2B0_8814B BIT(17)\n#define BIT_WMAC_MSK_SIGBCRC_8814B BIT(16)\n#define BIT_WMAC_TCR_ERRSTEN_3_8814B BIT(15)\n#define BIT_WMAC_TCR_ERRSTEN_2_8814B BIT(14)\n#define BIT_WMAC_TCR_ERRSTEN_1_8814B BIT(13)\n#define BIT_WMAC_TCR_ERRSTEN_0_8814B BIT(12)\n#define BIT_WMAC_TCR_TXSK_PERPKT_8814B BIT(11)\n#define BIT_ICV_8814B BIT(10)\n#define BIT_CRC_8814B BIT(8)\n#define BIT_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(7)\n#define BIT_PWR_ST_8814B BIT(6)\n#define BIT_WMAC_TCR_UPD_TIMIE_8814B BIT(5)\n#define BIT_WMAC_TCR_UPD_HGQMD_8814B BIT(4)\n#define BIT_VHTSIGA1_TXPS_8814B BIT(3)\n#define BIT_PAD_SEL_8814B BIT(2)\n#define BIT_DIS_GCLK_8814B BIT(1)\n#define BIT_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(0)\n\n/* 2 REG_RCR_8814B (RECEIVE CONFIGURATION REGISTER) */\n#define BIT_APP_FCS_8814B BIT(31)\n#define BIT_APP_MIC_8814B BIT(30)\n#define BIT_APP_ICV_8814B BIT(29)\n#define BIT_APP_PHYSTS_8814B BIT(28)\n#define BIT_APP_BASSN_8814B BIT(27)\n#define BIT_VHT_DACK_8814B BIT(26)\n#define BIT_TCPOFLD_EN_8814B BIT(25)\n#define BIT_ENADDRCAM_8814B BIT(24)\n#define BIT_LSIGEN_8814B BIT(23)\n#define BIT_MFBEN_8814B BIT(22)\n#define BIT_DISCHKPPDLLEN_8814B BIT(21)\n#define BIT_PKTCTL_DLEN_8814B BIT(20)\n#define BIT_DISGCLK_8814B BIT(19)\n#define BIT_TIM_PARSER_EN_8814B BIT(18)\n#define BIT_BC_MD_EN_8814B BIT(17)\n#define BIT_UC_MD_EN_8814B BIT(16)\n#define BIT_RXSK_PERPKT_8814B BIT(15)\n#define BIT_HTC_LOC_CTRL_8814B BIT(14)\n#define BIT_ACK_WITH_CBSSID_DATA_OPTION_8814B BIT(13)\n#define BIT_RPFM_CAM_ENABLE_8814B BIT(12)\n#define BIT_TA_BCN_8814B BIT(11)\n#define BIT_DISDECMYPKT_8814B BIT(10)\n#define BIT_AICV_8814B BIT(9)\n#define BIT_ACRC32_8814B BIT(8)\n#define BIT_CBSSID_BCN_8814B BIT(7)\n#define BIT_CBSSID_DATA_8814B BIT(6)\n#define BIT_APWRMGT_8814B BIT(5)\n#define BIT_ADD3_8814B BIT(4)\n#define BIT_AB_8814B BIT(3)\n#define BIT_AM_8814B BIT(2)\n#define BIT_APM_8814B BIT(1)\n#define BIT_AAP_8814B BIT(0)\n\n/* 2 REG_RX_PKT_LIMIT_8814B (RX PACKET LENGTH LIMIT REGISTER) */\n\n#define BIT_SHIFT_RXPKTLMT_8814B 0\n#define BIT_MASK_RXPKTLMT_8814B 0x3f\n#define BIT_RXPKTLMT_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_RXPKTLMT_8814B) << BIT_SHIFT_RXPKTLMT_8814B)\n#define BITS_RXPKTLMT_8814B                                                    \\\n\t(BIT_MASK_RXPKTLMT_8814B << BIT_SHIFT_RXPKTLMT_8814B)\n#define BIT_CLEAR_RXPKTLMT_8814B(x) ((x) & (~BITS_RXPKTLMT_8814B))\n#define BIT_GET_RXPKTLMT_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RXPKTLMT_8814B) & BIT_MASK_RXPKTLMT_8814B)\n#define BIT_SET_RXPKTLMT_8814B(x, v)                                           \\\n\t(BIT_CLEAR_RXPKTLMT_8814B(x) | BIT_RXPKTLMT_8814B(v))\n\n/* 2 REG_RX_DLK_TIME_8814B (RX DEADLOCK TIME REGISTER) */\n\n#define BIT_SHIFT_RX_DLK_TIME_8814B 0\n#define BIT_MASK_RX_DLK_TIME_8814B 0xff\n#define BIT_RX_DLK_TIME_8814B(x)                                               \\\n\t(((x) & BIT_MASK_RX_DLK_TIME_8814B) << BIT_SHIFT_RX_DLK_TIME_8814B)\n#define BITS_RX_DLK_TIME_8814B                                                 \\\n\t(BIT_MASK_RX_DLK_TIME_8814B << BIT_SHIFT_RX_DLK_TIME_8814B)\n#define BIT_CLEAR_RX_DLK_TIME_8814B(x) ((x) & (~BITS_RX_DLK_TIME_8814B))\n#define BIT_GET_RX_DLK_TIME_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_RX_DLK_TIME_8814B) & BIT_MASK_RX_DLK_TIME_8814B)\n#define BIT_SET_RX_DLK_TIME_8814B(x, v)                                        \\\n\t(BIT_CLEAR_RX_DLK_TIME_8814B(x) | BIT_RX_DLK_TIME_8814B(v))\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RX_DRVINFO_SZ_8814B (RX DRIVER INFO SIZE REGISTER) */\n#define BIT_PHYSTS_PER_PKT_MODE_8814B BIT(7)\n\n#define BIT_SHIFT_DRVINFO_SZ_V1_8814B 0\n#define BIT_MASK_DRVINFO_SZ_V1_8814B 0xf\n#define BIT_DRVINFO_SZ_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_DRVINFO_SZ_V1_8814B) << BIT_SHIFT_DRVINFO_SZ_V1_8814B)\n#define BITS_DRVINFO_SZ_V1_8814B                                               \\\n\t(BIT_MASK_DRVINFO_SZ_V1_8814B << BIT_SHIFT_DRVINFO_SZ_V1_8814B)\n#define BIT_CLEAR_DRVINFO_SZ_V1_8814B(x) ((x) & (~BITS_DRVINFO_SZ_V1_8814B))\n#define BIT_GET_DRVINFO_SZ_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8814B) & BIT_MASK_DRVINFO_SZ_V1_8814B)\n#define BIT_SET_DRVINFO_SZ_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_DRVINFO_SZ_V1_8814B(x) | BIT_DRVINFO_SZ_V1_8814B(v))\n\n/* 2 REG_MACID_8814B\t(MAC ID REGISTER) */\n\n#define BIT_SHIFT_MACID_V1_8814B 0\n#define BIT_MASK_MACID_V1_8814B 0xffffffffL\n#define BIT_MACID_V1_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_MACID_V1_8814B) << BIT_SHIFT_MACID_V1_8814B)\n#define BITS_MACID_V1_8814B                                                    \\\n\t(BIT_MASK_MACID_V1_8814B << BIT_SHIFT_MACID_V1_8814B)\n#define BIT_CLEAR_MACID_V1_8814B(x) ((x) & (~BITS_MACID_V1_8814B))\n#define BIT_GET_MACID_V1_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_MACID_V1_8814B) & BIT_MASK_MACID_V1_8814B)\n#define BIT_SET_MACID_V1_8814B(x, v)                                           \\\n\t(BIT_CLEAR_MACID_V1_8814B(x) | BIT_MACID_V1_8814B(v))\n\n/* 2 REG_MACID_H_8814B\t(MAC ID REGISTER) */\n\n#define BIT_SHIFT_MACID_H_V1_8814B 0\n#define BIT_MASK_MACID_H_V1_8814B 0xffff\n#define BIT_MACID_H_V1_8814B(x)                                                \\\n\t(((x) & BIT_MASK_MACID_H_V1_8814B) << BIT_SHIFT_MACID_H_V1_8814B)\n#define BITS_MACID_H_V1_8814B                                                  \\\n\t(BIT_MASK_MACID_H_V1_8814B << BIT_SHIFT_MACID_H_V1_8814B)\n#define BIT_CLEAR_MACID_H_V1_8814B(x) ((x) & (~BITS_MACID_H_V1_8814B))\n#define BIT_GET_MACID_H_V1_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_MACID_H_V1_8814B) & BIT_MASK_MACID_H_V1_8814B)\n#define BIT_SET_MACID_H_V1_8814B(x, v)                                         \\\n\t(BIT_CLEAR_MACID_H_V1_8814B(x) | BIT_MACID_H_V1_8814B(v))\n\n/* 2 REG_BSSID_8814B (BSSID REGISTER) */\n\n#define BIT_SHIFT_BSSID_V1_8814B 0\n#define BIT_MASK_BSSID_V1_8814B 0xffffffffL\n#define BIT_BSSID_V1_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_BSSID_V1_8814B) << BIT_SHIFT_BSSID_V1_8814B)\n#define BITS_BSSID_V1_8814B                                                    \\\n\t(BIT_MASK_BSSID_V1_8814B << BIT_SHIFT_BSSID_V1_8814B)\n#define BIT_CLEAR_BSSID_V1_8814B(x) ((x) & (~BITS_BSSID_V1_8814B))\n#define BIT_GET_BSSID_V1_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_BSSID_V1_8814B) & BIT_MASK_BSSID_V1_8814B)\n#define BIT_SET_BSSID_V1_8814B(x, v)                                           \\\n\t(BIT_CLEAR_BSSID_V1_8814B(x) | BIT_BSSID_V1_8814B(v))\n\n/* 2 REG_BSSID_H_8814B\t(BSSID REGISTER) */\n\n/* 2 REG_NOT_VALID_8814B */\n\n#define BIT_SHIFT_BSSID_H_V1_8814B 0\n#define BIT_MASK_BSSID_H_V1_8814B 0xffff\n#define BIT_BSSID_H_V1_8814B(x)                                                \\\n\t(((x) & BIT_MASK_BSSID_H_V1_8814B) << BIT_SHIFT_BSSID_H_V1_8814B)\n#define BITS_BSSID_H_V1_8814B                                                  \\\n\t(BIT_MASK_BSSID_H_V1_8814B << BIT_SHIFT_BSSID_H_V1_8814B)\n#define BIT_CLEAR_BSSID_H_V1_8814B(x) ((x) & (~BITS_BSSID_H_V1_8814B))\n#define BIT_GET_BSSID_H_V1_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_BSSID_H_V1_8814B) & BIT_MASK_BSSID_H_V1_8814B)\n#define BIT_SET_BSSID_H_V1_8814B(x, v)                                         \\\n\t(BIT_CLEAR_BSSID_H_V1_8814B(x) | BIT_BSSID_H_V1_8814B(v))\n\n/* 2 REG_MAR_8814B (MULTICAST ADDRESS REGISTER) */\n\n#define BIT_SHIFT_MAR_V1_8814B 0\n#define BIT_MASK_MAR_V1_8814B 0xffffffffL\n#define BIT_MAR_V1_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_MAR_V1_8814B) << BIT_SHIFT_MAR_V1_8814B)\n#define BITS_MAR_V1_8814B (BIT_MASK_MAR_V1_8814B << BIT_SHIFT_MAR_V1_8814B)\n#define BIT_CLEAR_MAR_V1_8814B(x) ((x) & (~BITS_MAR_V1_8814B))\n#define BIT_GET_MAR_V1_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_MAR_V1_8814B) & BIT_MASK_MAR_V1_8814B)\n#define BIT_SET_MAR_V1_8814B(x, v)                                             \\\n\t(BIT_CLEAR_MAR_V1_8814B(x) | BIT_MAR_V1_8814B(v))\n\n/* 2 REG_MAR_H_8814B (MULTICAST ADDRESS REGISTER) */\n\n#define BIT_SHIFT_MAR_H_V1_8814B 0\n#define BIT_MASK_MAR_H_V1_8814B 0xffffffffL\n#define BIT_MAR_H_V1_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_MAR_H_V1_8814B) << BIT_SHIFT_MAR_H_V1_8814B)\n#define BITS_MAR_H_V1_8814B                                                    \\\n\t(BIT_MASK_MAR_H_V1_8814B << BIT_SHIFT_MAR_H_V1_8814B)\n#define BIT_CLEAR_MAR_H_V1_8814B(x) ((x) & (~BITS_MAR_H_V1_8814B))\n#define BIT_GET_MAR_H_V1_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_MAR_H_V1_8814B) & BIT_MASK_MAR_H_V1_8814B)\n#define BIT_SET_MAR_H_V1_8814B(x, v)                                           \\\n\t(BIT_CLEAR_MAR_H_V1_8814B(x) | BIT_MAR_H_V1_8814B(v))\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_WMAC_DEBUG_SEL_8814B */\n\n#define BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B 3\n#define BIT_MASK_WMAC_ARB_DBG_SEL_8814B 0x3\n#define BIT_WMAC_ARB_DBG_SEL_8814B(x)                                          \\\n\t(((x) & BIT_MASK_WMAC_ARB_DBG_SEL_8814B)                               \\\n\t << BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B)\n#define BITS_WMAC_ARB_DBG_SEL_8814B                                            \\\n\t(BIT_MASK_WMAC_ARB_DBG_SEL_8814B << BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B)\n#define BIT_CLEAR_WMAC_ARB_DBG_SEL_8814B(x)                                    \\\n\t((x) & (~BITS_WMAC_ARB_DBG_SEL_8814B))\n#define BIT_GET_WMAC_ARB_DBG_SEL_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B) &                           \\\n\t BIT_MASK_WMAC_ARB_DBG_SEL_8814B)\n#define BIT_SET_WMAC_ARB_DBG_SEL_8814B(x, v)                                   \\\n\t(BIT_CLEAR_WMAC_ARB_DBG_SEL_8814B(x) | BIT_WMAC_ARB_DBG_SEL_8814B(v))\n\n#define BIT_WMAC_EXT_DBG_SEL_8814B BIT(2)\n\n#define BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B 0\n#define BIT_MASK_WMAC_MU_DBGSEL_V1_8814B 0x3\n#define BIT_WMAC_MU_DBGSEL_V1_8814B(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_DBGSEL_V1_8814B)                              \\\n\t << BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B)\n#define BITS_WMAC_MU_DBGSEL_V1_8814B                                           \\\n\t(BIT_MASK_WMAC_MU_DBGSEL_V1_8814B << BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B)\n#define BIT_CLEAR_WMAC_MU_DBGSEL_V1_8814B(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_DBGSEL_V1_8814B))\n#define BIT_GET_WMAC_MU_DBGSEL_V1_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B) &                          \\\n\t BIT_MASK_WMAC_MU_DBGSEL_V1_8814B)\n#define BIT_SET_WMAC_MU_DBGSEL_V1_8814B(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_DBGSEL_V1_8814B(x) | BIT_WMAC_MU_DBGSEL_V1_8814B(v))\n\n/* 2 REG_WMAC_TCR_TSFT_OFS_8814B */\n\n#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B 0\n#define BIT_MASK_WMAC_TCR_TSFT_OFS_8814B 0xffff\n#define BIT_WMAC_TCR_TSFT_OFS_8814B(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8814B)                              \\\n\t << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B)\n#define BITS_WMAC_TCR_TSFT_OFS_8814B                                           \\\n\t(BIT_MASK_WMAC_TCR_TSFT_OFS_8814B << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B)\n#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8814B(x)                                   \\\n\t((x) & (~BITS_WMAC_TCR_TSFT_OFS_8814B))\n#define BIT_GET_WMAC_TCR_TSFT_OFS_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B) &                          \\\n\t BIT_MASK_WMAC_TCR_TSFT_OFS_8814B)\n#define BIT_SET_WMAC_TCR_TSFT_OFS_8814B(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_TCR_TSFT_OFS_8814B(x) | BIT_WMAC_TCR_TSFT_OFS_8814B(v))\n\n/* 2 REG_UDF_THSD_8814B */\n#define BIT_UDF_THSD_V1_8814B BIT(7)\n\n#define BIT_SHIFT_UDF_THSD_VALUE_8814B 0\n#define BIT_MASK_UDF_THSD_VALUE_8814B 0x7f\n#define BIT_UDF_THSD_VALUE_8814B(x)                                            \\\n\t(((x) & BIT_MASK_UDF_THSD_VALUE_8814B)                                 \\\n\t << BIT_SHIFT_UDF_THSD_VALUE_8814B)\n#define BITS_UDF_THSD_VALUE_8814B                                              \\\n\t(BIT_MASK_UDF_THSD_VALUE_8814B << BIT_SHIFT_UDF_THSD_VALUE_8814B)\n#define BIT_CLEAR_UDF_THSD_VALUE_8814B(x) ((x) & (~BITS_UDF_THSD_VALUE_8814B))\n#define BIT_GET_UDF_THSD_VALUE_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_UDF_THSD_VALUE_8814B) &                             \\\n\t BIT_MASK_UDF_THSD_VALUE_8814B)\n#define BIT_SET_UDF_THSD_VALUE_8814B(x, v)                                     \\\n\t(BIT_CLEAR_UDF_THSD_VALUE_8814B(x) | BIT_UDF_THSD_VALUE_8814B(v))\n\n/* 2 REG_ZLD_NUM_8814B */\n\n#define BIT_SHIFT_ZLD_NUM_8814B 0\n#define BIT_MASK_ZLD_NUM_8814B 0xff\n#define BIT_ZLD_NUM_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_ZLD_NUM_8814B) << BIT_SHIFT_ZLD_NUM_8814B)\n#define BITS_ZLD_NUM_8814B (BIT_MASK_ZLD_NUM_8814B << BIT_SHIFT_ZLD_NUM_8814B)\n#define BIT_CLEAR_ZLD_NUM_8814B(x) ((x) & (~BITS_ZLD_NUM_8814B))\n#define BIT_GET_ZLD_NUM_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_ZLD_NUM_8814B) & BIT_MASK_ZLD_NUM_8814B)\n#define BIT_SET_ZLD_NUM_8814B(x, v)                                            \\\n\t(BIT_CLEAR_ZLD_NUM_8814B(x) | BIT_ZLD_NUM_8814B(v))\n\n/* 2 REG_STMP_THSD_8814B */\n\n#define BIT_SHIFT_STMP_THSD_8814B 0\n#define BIT_MASK_STMP_THSD_8814B 0xff\n#define BIT_STMP_THSD_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_STMP_THSD_8814B) << BIT_SHIFT_STMP_THSD_8814B)\n#define BITS_STMP_THSD_8814B                                                   \\\n\t(BIT_MASK_STMP_THSD_8814B << BIT_SHIFT_STMP_THSD_8814B)\n#define BIT_CLEAR_STMP_THSD_8814B(x) ((x) & (~BITS_STMP_THSD_8814B))\n#define BIT_GET_STMP_THSD_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_STMP_THSD_8814B) & BIT_MASK_STMP_THSD_8814B)\n#define BIT_SET_STMP_THSD_8814B(x, v)                                          \\\n\t(BIT_CLEAR_STMP_THSD_8814B(x) | BIT_STMP_THSD_8814B(v))\n\n/* 2 REG_WMAC_TXTIMEOUT_8814B */\n\n#define BIT_SHIFT_WMAC_TXTIMEOUT_8814B 0\n#define BIT_MASK_WMAC_TXTIMEOUT_8814B 0xff\n#define BIT_WMAC_TXTIMEOUT_8814B(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_TXTIMEOUT_8814B)                                 \\\n\t << BIT_SHIFT_WMAC_TXTIMEOUT_8814B)\n#define BITS_WMAC_TXTIMEOUT_8814B                                              \\\n\t(BIT_MASK_WMAC_TXTIMEOUT_8814B << BIT_SHIFT_WMAC_TXTIMEOUT_8814B)\n#define BIT_CLEAR_WMAC_TXTIMEOUT_8814B(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8814B))\n#define BIT_GET_WMAC_TXTIMEOUT_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8814B) &                             \\\n\t BIT_MASK_WMAC_TXTIMEOUT_8814B)\n#define BIT_SET_WMAC_TXTIMEOUT_8814B(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_TXTIMEOUT_8814B(x) | BIT_WMAC_TXTIMEOUT_8814B(v))\n\n/* 2 REG_MCU_TEST_2_V1_8814B */\n\n#define BIT_SHIFT_MCU_RSVD_2_V1_8814B 0\n#define BIT_MASK_MCU_RSVD_2_V1_8814B 0xffff\n#define BIT_MCU_RSVD_2_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_MCU_RSVD_2_V1_8814B) << BIT_SHIFT_MCU_RSVD_2_V1_8814B)\n#define BITS_MCU_RSVD_2_V1_8814B                                               \\\n\t(BIT_MASK_MCU_RSVD_2_V1_8814B << BIT_SHIFT_MCU_RSVD_2_V1_8814B)\n#define BIT_CLEAR_MCU_RSVD_2_V1_8814B(x) ((x) & (~BITS_MCU_RSVD_2_V1_8814B))\n#define BIT_GET_MCU_RSVD_2_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8814B) & BIT_MASK_MCU_RSVD_2_V1_8814B)\n#define BIT_SET_MCU_RSVD_2_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_MCU_RSVD_2_V1_8814B(x) | BIT_MCU_RSVD_2_V1_8814B(v))\n\n/* 2 REG_USTIME_EDCA_8814B (US TIME TUNING FOR EDCA REGISTER) */\n\n#define BIT_SHIFT_USTIME_EDCA_8814B 0\n#define BIT_MASK_USTIME_EDCA_8814B 0xff\n#define BIT_USTIME_EDCA_8814B(x)                                               \\\n\t(((x) & BIT_MASK_USTIME_EDCA_8814B) << BIT_SHIFT_USTIME_EDCA_8814B)\n#define BITS_USTIME_EDCA_8814B                                                 \\\n\t(BIT_MASK_USTIME_EDCA_8814B << BIT_SHIFT_USTIME_EDCA_8814B)\n#define BIT_CLEAR_USTIME_EDCA_8814B(x) ((x) & (~BITS_USTIME_EDCA_8814B))\n#define BIT_GET_USTIME_EDCA_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_USTIME_EDCA_8814B) & BIT_MASK_USTIME_EDCA_8814B)\n#define BIT_SET_USTIME_EDCA_8814B(x, v)                                        \\\n\t(BIT_CLEAR_USTIME_EDCA_8814B(x) | BIT_USTIME_EDCA_8814B(v))\n\n/* 2 REG_ACKTO_CCK_8814B (ACK TIMEOUT REGISTER FOR CCK RATE) */\n\n#define BIT_SHIFT_ACKTO_CCK_8814B 0\n#define BIT_MASK_ACKTO_CCK_8814B 0xff\n#define BIT_ACKTO_CCK_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_ACKTO_CCK_8814B) << BIT_SHIFT_ACKTO_CCK_8814B)\n#define BITS_ACKTO_CCK_8814B                                                   \\\n\t(BIT_MASK_ACKTO_CCK_8814B << BIT_SHIFT_ACKTO_CCK_8814B)\n#define BIT_CLEAR_ACKTO_CCK_8814B(x) ((x) & (~BITS_ACKTO_CCK_8814B))\n#define BIT_GET_ACKTO_CCK_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_ACKTO_CCK_8814B) & BIT_MASK_ACKTO_CCK_8814B)\n#define BIT_SET_ACKTO_CCK_8814B(x, v)                                          \\\n\t(BIT_CLEAR_ACKTO_CCK_8814B(x) | BIT_ACKTO_CCK_8814B(v))\n\n/* 2 REG_MAC_SPEC_SIFS_8814B (SPECIFICATION SIFS REGISTER) */\n\n#define BIT_SHIFT_SPEC_SIFS_OFDM_8814B 8\n#define BIT_MASK_SPEC_SIFS_OFDM_8814B 0xff\n#define BIT_SPEC_SIFS_OFDM_8814B(x)                                            \\\n\t(((x) & BIT_MASK_SPEC_SIFS_OFDM_8814B)                                 \\\n\t << BIT_SHIFT_SPEC_SIFS_OFDM_8814B)\n#define BITS_SPEC_SIFS_OFDM_8814B                                              \\\n\t(BIT_MASK_SPEC_SIFS_OFDM_8814B << BIT_SHIFT_SPEC_SIFS_OFDM_8814B)\n#define BIT_CLEAR_SPEC_SIFS_OFDM_8814B(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8814B))\n#define BIT_GET_SPEC_SIFS_OFDM_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8814B) &                             \\\n\t BIT_MASK_SPEC_SIFS_OFDM_8814B)\n#define BIT_SET_SPEC_SIFS_OFDM_8814B(x, v)                                     \\\n\t(BIT_CLEAR_SPEC_SIFS_OFDM_8814B(x) | BIT_SPEC_SIFS_OFDM_8814B(v))\n\n#define BIT_SHIFT_SPEC_SIFS_CCK_8814B 0\n#define BIT_MASK_SPEC_SIFS_CCK_8814B 0xff\n#define BIT_SPEC_SIFS_CCK_8814B(x)                                             \\\n\t(((x) & BIT_MASK_SPEC_SIFS_CCK_8814B) << BIT_SHIFT_SPEC_SIFS_CCK_8814B)\n#define BITS_SPEC_SIFS_CCK_8814B                                               \\\n\t(BIT_MASK_SPEC_SIFS_CCK_8814B << BIT_SHIFT_SPEC_SIFS_CCK_8814B)\n#define BIT_CLEAR_SPEC_SIFS_CCK_8814B(x) ((x) & (~BITS_SPEC_SIFS_CCK_8814B))\n#define BIT_GET_SPEC_SIFS_CCK_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8814B) & BIT_MASK_SPEC_SIFS_CCK_8814B)\n#define BIT_SET_SPEC_SIFS_CCK_8814B(x, v)                                      \\\n\t(BIT_CLEAR_SPEC_SIFS_CCK_8814B(x) | BIT_SPEC_SIFS_CCK_8814B(v))\n\n/* 2 REG_RESP_SIFS_CCK_8814B (RESPONSE SIFS FOR CCK REGISTER) */\n\n#define BIT_SHIFT_SIFS_R2T_CCK_8814B 8\n#define BIT_MASK_SIFS_R2T_CCK_8814B 0xff\n#define BIT_SIFS_R2T_CCK_8814B(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_R2T_CCK_8814B) << BIT_SHIFT_SIFS_R2T_CCK_8814B)\n#define BITS_SIFS_R2T_CCK_8814B                                                \\\n\t(BIT_MASK_SIFS_R2T_CCK_8814B << BIT_SHIFT_SIFS_R2T_CCK_8814B)\n#define BIT_CLEAR_SIFS_R2T_CCK_8814B(x) ((x) & (~BITS_SIFS_R2T_CCK_8814B))\n#define BIT_GET_SIFS_R2T_CCK_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_R2T_CCK_8814B) & BIT_MASK_SIFS_R2T_CCK_8814B)\n#define BIT_SET_SIFS_R2T_CCK_8814B(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_R2T_CCK_8814B(x) | BIT_SIFS_R2T_CCK_8814B(v))\n\n#define BIT_SHIFT_SIFS_T2T_CCK_8814B 0\n#define BIT_MASK_SIFS_T2T_CCK_8814B 0xff\n#define BIT_SIFS_T2T_CCK_8814B(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_T2T_CCK_8814B) << BIT_SHIFT_SIFS_T2T_CCK_8814B)\n#define BITS_SIFS_T2T_CCK_8814B                                                \\\n\t(BIT_MASK_SIFS_T2T_CCK_8814B << BIT_SHIFT_SIFS_T2T_CCK_8814B)\n#define BIT_CLEAR_SIFS_T2T_CCK_8814B(x) ((x) & (~BITS_SIFS_T2T_CCK_8814B))\n#define BIT_GET_SIFS_T2T_CCK_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_T2T_CCK_8814B) & BIT_MASK_SIFS_T2T_CCK_8814B)\n#define BIT_SET_SIFS_T2T_CCK_8814B(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_T2T_CCK_8814B(x) | BIT_SIFS_T2T_CCK_8814B(v))\n\n/* 2 REG_RESP_SIFS_OFDM_8814B (RESPONSE SIFS FOR OFDM REGISTER) */\n\n#define BIT_SHIFT_SIFS_R2T_OFDM_8814B 8\n#define BIT_MASK_SIFS_R2T_OFDM_8814B 0xff\n#define BIT_SIFS_R2T_OFDM_8814B(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_R2T_OFDM_8814B) << BIT_SHIFT_SIFS_R2T_OFDM_8814B)\n#define BITS_SIFS_R2T_OFDM_8814B                                               \\\n\t(BIT_MASK_SIFS_R2T_OFDM_8814B << BIT_SHIFT_SIFS_R2T_OFDM_8814B)\n#define BIT_CLEAR_SIFS_R2T_OFDM_8814B(x) ((x) & (~BITS_SIFS_R2T_OFDM_8814B))\n#define BIT_GET_SIFS_R2T_OFDM_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8814B) & BIT_MASK_SIFS_R2T_OFDM_8814B)\n#define BIT_SET_SIFS_R2T_OFDM_8814B(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_R2T_OFDM_8814B(x) | BIT_SIFS_R2T_OFDM_8814B(v))\n\n#define BIT_SHIFT_SIFS_T2T_OFDM_8814B 0\n#define BIT_MASK_SIFS_T2T_OFDM_8814B 0xff\n#define BIT_SIFS_T2T_OFDM_8814B(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_T2T_OFDM_8814B) << BIT_SHIFT_SIFS_T2T_OFDM_8814B)\n#define BITS_SIFS_T2T_OFDM_8814B                                               \\\n\t(BIT_MASK_SIFS_T2T_OFDM_8814B << BIT_SHIFT_SIFS_T2T_OFDM_8814B)\n#define BIT_CLEAR_SIFS_T2T_OFDM_8814B(x) ((x) & (~BITS_SIFS_T2T_OFDM_8814B))\n#define BIT_GET_SIFS_T2T_OFDM_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8814B) & BIT_MASK_SIFS_T2T_OFDM_8814B)\n#define BIT_SET_SIFS_T2T_OFDM_8814B(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_T2T_OFDM_8814B(x) | BIT_SIFS_T2T_OFDM_8814B(v))\n\n/* 2 REG_ACKTO_8814B (ACK TIMEOUT REGISTER) */\n\n#define BIT_SHIFT_ACKTO_8814B 0\n#define BIT_MASK_ACKTO_8814B 0xff\n#define BIT_ACKTO_8814B(x)                                                     \\\n\t(((x) & BIT_MASK_ACKTO_8814B) << BIT_SHIFT_ACKTO_8814B)\n#define BITS_ACKTO_8814B (BIT_MASK_ACKTO_8814B << BIT_SHIFT_ACKTO_8814B)\n#define BIT_CLEAR_ACKTO_8814B(x) ((x) & (~BITS_ACKTO_8814B))\n#define BIT_GET_ACKTO_8814B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ACKTO_8814B) & BIT_MASK_ACKTO_8814B)\n#define BIT_SET_ACKTO_8814B(x, v)                                              \\\n\t(BIT_CLEAR_ACKTO_8814B(x) | BIT_ACKTO_8814B(v))\n\n/* 2 REG_CTS2TO_8814B (CTS2 TIMEOUT REGISTER) */\n\n#define BIT_SHIFT_CTS2TO_8814B 0\n#define BIT_MASK_CTS2TO_8814B 0xff\n#define BIT_CTS2TO_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_CTS2TO_8814B) << BIT_SHIFT_CTS2TO_8814B)\n#define BITS_CTS2TO_8814B (BIT_MASK_CTS2TO_8814B << BIT_SHIFT_CTS2TO_8814B)\n#define BIT_CLEAR_CTS2TO_8814B(x) ((x) & (~BITS_CTS2TO_8814B))\n#define BIT_GET_CTS2TO_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_CTS2TO_8814B) & BIT_MASK_CTS2TO_8814B)\n#define BIT_SET_CTS2TO_8814B(x, v)                                             \\\n\t(BIT_CLEAR_CTS2TO_8814B(x) | BIT_CTS2TO_8814B(v))\n\n/* 2 REG_EIFS_8814B (EIFS REGISTER) */\n\n#define BIT_SHIFT_EIFS_8814B 0\n#define BIT_MASK_EIFS_8814B 0xffff\n#define BIT_EIFS_8814B(x) (((x) & BIT_MASK_EIFS_8814B) << BIT_SHIFT_EIFS_8814B)\n#define BITS_EIFS_8814B (BIT_MASK_EIFS_8814B << BIT_SHIFT_EIFS_8814B)\n#define BIT_CLEAR_EIFS_8814B(x) ((x) & (~BITS_EIFS_8814B))\n#define BIT_GET_EIFS_8814B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_EIFS_8814B) & BIT_MASK_EIFS_8814B)\n#define BIT_SET_EIFS_8814B(x, v) (BIT_CLEAR_EIFS_8814B(x) | BIT_EIFS_8814B(v))\n\n/* 2 REG_RPFM_MAP0_8814B */\n#define BIT_MGT_RPFM15EN_8814B BIT(15)\n#define BIT_MGT_RPFM14EN_8814B BIT(14)\n#define BIT_MGT_RPFM13EN_8814B BIT(13)\n#define BIT_MGT_RPFM12EN_8814B BIT(12)\n#define BIT_MGT_RPFM11EN_8814B BIT(11)\n#define BIT_MGT_RPFM10EN_8814B BIT(10)\n#define BIT_MGT_RPFM9EN_8814B BIT(9)\n#define BIT_MGT_RPFM8EN_8814B BIT(8)\n#define BIT_MGT_RPFM7EN_8814B BIT(7)\n#define BIT_MGT_RPFM6EN_8814B BIT(6)\n#define BIT_MGT_RPFM5EN_8814B BIT(5)\n#define BIT_MGT_RPFM4EN_8814B BIT(4)\n#define BIT_MGT_RPFM3EN_8814B BIT(3)\n#define BIT_MGT_RPFM2EN_8814B BIT(2)\n#define BIT_MGT_RPFM1EN_8814B BIT(1)\n#define BIT_MGT_RPFM0EN_8814B BIT(0)\n\n/* 2 REG_RPFM_MAP1_V1_8814B */\n#define BIT_DATA_RPFM15EN_8814B BIT(15)\n#define BIT_DATA_RPFM14EN_8814B BIT(14)\n#define BIT_DATA_RPFM13EN_8814B BIT(13)\n#define BIT_DATA_RPFM12EN_8814B BIT(12)\n#define BIT_DATA_RPFM11EN_8814B BIT(11)\n#define BIT_DATA_RPFM10EN_8814B BIT(10)\n#define BIT_DATA_RPFM9EN_8814B BIT(9)\n#define BIT_DATA_RPFM8EN_8814B BIT(8)\n#define BIT_DATA_RPFM7EN_8814B BIT(7)\n#define BIT_DATA_RPFM6EN_8814B BIT(6)\n#define BIT_DATA_RPFM5EN_8814B BIT(5)\n#define BIT_DATA_RPFM4EN_8814B BIT(4)\n#define BIT_DATA_RPFM3EN_8814B BIT(3)\n#define BIT_DATA_RPFM2EN_8814B BIT(2)\n#define BIT_DATA_RPFM1EN_8814B BIT(1)\n#define BIT_DATA_RPFM0EN_8814B BIT(0)\n\n/* 2 REG_RPFM_CAM_CMD_8814B (RX PAYLOAD FRAME MASK CAM COMMAND REGISTER) */\n#define BIT_RPFM_CAM_POLLING_8814B BIT(31)\n#define BIT_RPFM_CAM_CLR_8814B BIT(30)\n#define BIT_RPFM_CAM_WE_8814B BIT(16)\n\n#define BIT_SHIFT_RPFM_CAM_ADDR_8814B 0\n#define BIT_MASK_RPFM_CAM_ADDR_8814B 0x7f\n#define BIT_RPFM_CAM_ADDR_8814B(x)                                             \\\n\t(((x) & BIT_MASK_RPFM_CAM_ADDR_8814B) << BIT_SHIFT_RPFM_CAM_ADDR_8814B)\n#define BITS_RPFM_CAM_ADDR_8814B                                               \\\n\t(BIT_MASK_RPFM_CAM_ADDR_8814B << BIT_SHIFT_RPFM_CAM_ADDR_8814B)\n#define BIT_CLEAR_RPFM_CAM_ADDR_8814B(x) ((x) & (~BITS_RPFM_CAM_ADDR_8814B))\n#define BIT_GET_RPFM_CAM_ADDR_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8814B) & BIT_MASK_RPFM_CAM_ADDR_8814B)\n#define BIT_SET_RPFM_CAM_ADDR_8814B(x, v)                                      \\\n\t(BIT_CLEAR_RPFM_CAM_ADDR_8814B(x) | BIT_RPFM_CAM_ADDR_8814B(v))\n\n/* 2 REG_RPFM_CAM_RWD_8814B (ACK TIMEOUT REGISTER) */\n\n#define BIT_SHIFT_RPFM_CAM_RWD_8814B 0\n#define BIT_MASK_RPFM_CAM_RWD_8814B 0xffffffffL\n#define BIT_RPFM_CAM_RWD_8814B(x)                                              \\\n\t(((x) & BIT_MASK_RPFM_CAM_RWD_8814B) << BIT_SHIFT_RPFM_CAM_RWD_8814B)\n#define BITS_RPFM_CAM_RWD_8814B                                                \\\n\t(BIT_MASK_RPFM_CAM_RWD_8814B << BIT_SHIFT_RPFM_CAM_RWD_8814B)\n#define BIT_CLEAR_RPFM_CAM_RWD_8814B(x) ((x) & (~BITS_RPFM_CAM_RWD_8814B))\n#define BIT_GET_RPFM_CAM_RWD_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RPFM_CAM_RWD_8814B) & BIT_MASK_RPFM_CAM_RWD_8814B)\n#define BIT_SET_RPFM_CAM_RWD_8814B(x, v)                                       \\\n\t(BIT_CLEAR_RPFM_CAM_RWD_8814B(x) | BIT_RPFM_CAM_RWD_8814B(v))\n\n/* 2 REG_NAV_CTRL_8814B (NAV CONTROL REGISTER) */\n\n#define BIT_SHIFT_NAV_UPPER_8814B 16\n#define BIT_MASK_NAV_UPPER_8814B 0xff\n#define BIT_NAV_UPPER_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_NAV_UPPER_8814B) << BIT_SHIFT_NAV_UPPER_8814B)\n#define BITS_NAV_UPPER_8814B                                                   \\\n\t(BIT_MASK_NAV_UPPER_8814B << BIT_SHIFT_NAV_UPPER_8814B)\n#define BIT_CLEAR_NAV_UPPER_8814B(x) ((x) & (~BITS_NAV_UPPER_8814B))\n#define BIT_GET_NAV_UPPER_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_NAV_UPPER_8814B) & BIT_MASK_NAV_UPPER_8814B)\n#define BIT_SET_NAV_UPPER_8814B(x, v)                                          \\\n\t(BIT_CLEAR_NAV_UPPER_8814B(x) | BIT_NAV_UPPER_8814B(v))\n\n#define BIT_SHIFT_RXMYRTS_NAV_8814B 8\n#define BIT_MASK_RXMYRTS_NAV_8814B 0xf\n#define BIT_RXMYRTS_NAV_8814B(x)                                               \\\n\t(((x) & BIT_MASK_RXMYRTS_NAV_8814B) << BIT_SHIFT_RXMYRTS_NAV_8814B)\n#define BITS_RXMYRTS_NAV_8814B                                                 \\\n\t(BIT_MASK_RXMYRTS_NAV_8814B << BIT_SHIFT_RXMYRTS_NAV_8814B)\n#define BIT_CLEAR_RXMYRTS_NAV_8814B(x) ((x) & (~BITS_RXMYRTS_NAV_8814B))\n#define BIT_GET_RXMYRTS_NAV_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_RXMYRTS_NAV_8814B) & BIT_MASK_RXMYRTS_NAV_8814B)\n#define BIT_SET_RXMYRTS_NAV_8814B(x, v)                                        \\\n\t(BIT_CLEAR_RXMYRTS_NAV_8814B(x) | BIT_RXMYRTS_NAV_8814B(v))\n\n#define BIT_SHIFT_RTSRST_8814B 0\n#define BIT_MASK_RTSRST_8814B 0xff\n#define BIT_RTSRST_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_RTSRST_8814B) << BIT_SHIFT_RTSRST_8814B)\n#define BITS_RTSRST_8814B (BIT_MASK_RTSRST_8814B << BIT_SHIFT_RTSRST_8814B)\n#define BIT_CLEAR_RTSRST_8814B(x) ((x) & (~BITS_RTSRST_8814B))\n#define BIT_GET_RTSRST_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_RTSRST_8814B) & BIT_MASK_RTSRST_8814B)\n#define BIT_SET_RTSRST_8814B(x, v)                                             \\\n\t(BIT_CLEAR_RTSRST_8814B(x) | BIT_RTSRST_8814B(v))\n\n/* 2 REG_BACAMCMD_8814B (BLOCK ACK CAM COMMAND REGISTER) */\n#define BIT_BACAM_POLL_8814B BIT(31)\n#define BIT_BACAM_RST_8814B BIT(17)\n#define BIT_BACAM_RW_8814B BIT(16)\n\n#define BIT_SHIFT_TXSBM_8814B 14\n#define BIT_MASK_TXSBM_8814B 0x3\n#define BIT_TXSBM_8814B(x)                                                     \\\n\t(((x) & BIT_MASK_TXSBM_8814B) << BIT_SHIFT_TXSBM_8814B)\n#define BITS_TXSBM_8814B (BIT_MASK_TXSBM_8814B << BIT_SHIFT_TXSBM_8814B)\n#define BIT_CLEAR_TXSBM_8814B(x) ((x) & (~BITS_TXSBM_8814B))\n#define BIT_GET_TXSBM_8814B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TXSBM_8814B) & BIT_MASK_TXSBM_8814B)\n#define BIT_SET_TXSBM_8814B(x, v)                                              \\\n\t(BIT_CLEAR_TXSBM_8814B(x) | BIT_TXSBM_8814B(v))\n\n#define BIT_SHIFT_BACAM_ADDR_8814B 0\n#define BIT_MASK_BACAM_ADDR_8814B 0x3f\n#define BIT_BACAM_ADDR_8814B(x)                                                \\\n\t(((x) & BIT_MASK_BACAM_ADDR_8814B) << BIT_SHIFT_BACAM_ADDR_8814B)\n#define BITS_BACAM_ADDR_8814B                                                  \\\n\t(BIT_MASK_BACAM_ADDR_8814B << BIT_SHIFT_BACAM_ADDR_8814B)\n#define BIT_CLEAR_BACAM_ADDR_8814B(x) ((x) & (~BITS_BACAM_ADDR_8814B))\n#define BIT_GET_BACAM_ADDR_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_BACAM_ADDR_8814B) & BIT_MASK_BACAM_ADDR_8814B)\n#define BIT_SET_BACAM_ADDR_8814B(x, v)                                         \\\n\t(BIT_CLEAR_BACAM_ADDR_8814B(x) | BIT_BACAM_ADDR_8814B(v))\n\n/* 2 REG_BACAMCONTENT_8814B (BLOCK ACK CAM CONTENT REGISTER) */\n\n#define BIT_SHIFT_BA_CONTENT_L_8814B 0\n#define BIT_MASK_BA_CONTENT_L_8814B 0xffffffffL\n#define BIT_BA_CONTENT_L_8814B(x)                                              \\\n\t(((x) & BIT_MASK_BA_CONTENT_L_8814B) << BIT_SHIFT_BA_CONTENT_L_8814B)\n#define BITS_BA_CONTENT_L_8814B                                                \\\n\t(BIT_MASK_BA_CONTENT_L_8814B << BIT_SHIFT_BA_CONTENT_L_8814B)\n#define BIT_CLEAR_BA_CONTENT_L_8814B(x) ((x) & (~BITS_BA_CONTENT_L_8814B))\n#define BIT_GET_BA_CONTENT_L_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BA_CONTENT_L_8814B) & BIT_MASK_BA_CONTENT_L_8814B)\n#define BIT_SET_BA_CONTENT_L_8814B(x, v)                                       \\\n\t(BIT_CLEAR_BA_CONTENT_L_8814B(x) | BIT_BA_CONTENT_L_8814B(v))\n\n/* 2 REG_BACAMCONTENT_H_8814B (BLOCK ACK CAM CONTENT REGISTER) */\n\n#define BIT_SHIFT_BA_CONTENT_H_8814B 0\n#define BIT_MASK_BA_CONTENT_H_8814B 0xffffffffL\n#define BIT_BA_CONTENT_H_8814B(x)                                              \\\n\t(((x) & BIT_MASK_BA_CONTENT_H_8814B) << BIT_SHIFT_BA_CONTENT_H_8814B)\n#define BITS_BA_CONTENT_H_8814B                                                \\\n\t(BIT_MASK_BA_CONTENT_H_8814B << BIT_SHIFT_BA_CONTENT_H_8814B)\n#define BIT_CLEAR_BA_CONTENT_H_8814B(x) ((x) & (~BITS_BA_CONTENT_H_8814B))\n#define BIT_GET_BA_CONTENT_H_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BA_CONTENT_H_8814B) & BIT_MASK_BA_CONTENT_H_8814B)\n#define BIT_SET_BA_CONTENT_H_8814B(x, v)                                       \\\n\t(BIT_CLEAR_BA_CONTENT_H_8814B(x) | BIT_BA_CONTENT_H_8814B(v))\n\n/* 2 REG_LBDLY_8814B (LOOPBACK DELAY REGISTER) */\n\n#define BIT_SHIFT_LBDLY_8814B 0\n#define BIT_MASK_LBDLY_8814B 0x1f\n#define BIT_LBDLY_8814B(x)                                                     \\\n\t(((x) & BIT_MASK_LBDLY_8814B) << BIT_SHIFT_LBDLY_8814B)\n#define BITS_LBDLY_8814B (BIT_MASK_LBDLY_8814B << BIT_SHIFT_LBDLY_8814B)\n#define BIT_CLEAR_LBDLY_8814B(x) ((x) & (~BITS_LBDLY_8814B))\n#define BIT_GET_LBDLY_8814B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_LBDLY_8814B) & BIT_MASK_LBDLY_8814B)\n#define BIT_SET_LBDLY_8814B(x, v)                                              \\\n\t(BIT_CLEAR_LBDLY_8814B(x) | BIT_LBDLY_8814B(v))\n\n/* 2 REG_WMAC_BACAM_RPMEN_8814B */\n\n#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B 2\n#define BIT_MASK_BITMAP_SSNBK_COUNTER_8814B 0x3f\n#define BIT_BITMAP_SSNBK_COUNTER_8814B(x)                                      \\\n\t(((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8814B)                           \\\n\t << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B)\n#define BITS_BITMAP_SSNBK_COUNTER_8814B                                        \\\n\t(BIT_MASK_BITMAP_SSNBK_COUNTER_8814B                                   \\\n\t << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B)\n#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8814B(x)                                \\\n\t((x) & (~BITS_BITMAP_SSNBK_COUNTER_8814B))\n#define BIT_GET_BITMAP_SSNBK_COUNTER_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B) &                       \\\n\t BIT_MASK_BITMAP_SSNBK_COUNTER_8814B)\n#define BIT_SET_BITMAP_SSNBK_COUNTER_8814B(x, v)                               \\\n\t(BIT_CLEAR_BITMAP_SSNBK_COUNTER_8814B(x) |                             \\\n\t BIT_BITMAP_SSNBK_COUNTER_8814B(v))\n\n#define BIT_BITMAP_EN_8814B BIT(1)\n#define BIT_WMAC_BACAM_RPMEN_8814B BIT(0)\n\n/* 2 REG_TX_RX_8814B STATUS */\n\n#define BIT_SHIFT_RXPKT_TYPE_8814B 2\n#define BIT_MASK_RXPKT_TYPE_8814B 0x3f\n#define BIT_RXPKT_TYPE_8814B(x)                                                \\\n\t(((x) & BIT_MASK_RXPKT_TYPE_8814B) << BIT_SHIFT_RXPKT_TYPE_8814B)\n#define BITS_RXPKT_TYPE_8814B                                                  \\\n\t(BIT_MASK_RXPKT_TYPE_8814B << BIT_SHIFT_RXPKT_TYPE_8814B)\n#define BIT_CLEAR_RXPKT_TYPE_8814B(x) ((x) & (~BITS_RXPKT_TYPE_8814B))\n#define BIT_GET_RXPKT_TYPE_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXPKT_TYPE_8814B) & BIT_MASK_RXPKT_TYPE_8814B)\n#define BIT_SET_RXPKT_TYPE_8814B(x, v)                                         \\\n\t(BIT_CLEAR_RXPKT_TYPE_8814B(x) | BIT_RXPKT_TYPE_8814B(v))\n\n#define BIT_TXACT_IND_8814B BIT(1)\n#define BIT_RXACT_IND_8814B BIT(0)\n\n/* 2 REG_WMAC_BITMAP_CTL_8814B */\n#define BIT_BITMAP_VO_8814B BIT(7)\n#define BIT_BITMAP_VI_8814B BIT(6)\n#define BIT_BITMAP_BE_8814B BIT(5)\n#define BIT_BITMAP_BK_8814B BIT(4)\n\n#define BIT_SHIFT_BITMAP_CONDITION_8814B 2\n#define BIT_MASK_BITMAP_CONDITION_8814B 0x3\n#define BIT_BITMAP_CONDITION_8814B(x)                                          \\\n\t(((x) & BIT_MASK_BITMAP_CONDITION_8814B)                               \\\n\t << BIT_SHIFT_BITMAP_CONDITION_8814B)\n#define BITS_BITMAP_CONDITION_8814B                                            \\\n\t(BIT_MASK_BITMAP_CONDITION_8814B << BIT_SHIFT_BITMAP_CONDITION_8814B)\n#define BIT_CLEAR_BITMAP_CONDITION_8814B(x)                                    \\\n\t((x) & (~BITS_BITMAP_CONDITION_8814B))\n#define BIT_GET_BITMAP_CONDITION_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BITMAP_CONDITION_8814B) &                           \\\n\t BIT_MASK_BITMAP_CONDITION_8814B)\n#define BIT_SET_BITMAP_CONDITION_8814B(x, v)                                   \\\n\t(BIT_CLEAR_BITMAP_CONDITION_8814B(x) | BIT_BITMAP_CONDITION_8814B(v))\n\n#define BIT_BITMAP_SSNBK_COUNTER_CLR_8814B BIT(1)\n#define BIT_BITMAP_FORCE_8814B BIT(0)\n\n/* 2 REG_RXERR_RPT_8814B (RX ERROR REPORT REGISTER) */\n\n#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B 28\n#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B 0xf\n#define BIT_RXERR_RPT_SEL_V1_3_0_8814B(x)                                      \\\n\t(((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B)                           \\\n\t << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B)\n#define BITS_RXERR_RPT_SEL_V1_3_0_8814B                                        \\\n\t(BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B                                   \\\n\t << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B)\n#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8814B(x)                                \\\n\t((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8814B))\n#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B) &                       \\\n\t BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B)\n#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8814B(x, v)                               \\\n\t(BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8814B(x) |                             \\\n\t BIT_RXERR_RPT_SEL_V1_3_0_8814B(v))\n\n#define BIT_RXERR_RPT_RST_8814B BIT(27)\n#define BIT_RXERR_RPT_SEL_V1_4_8814B BIT(26)\n#define BIT_W1S_8814B BIT(23)\n#define BIT_UD_SELECT_BSSID_8814B BIT(22)\n\n#define BIT_SHIFT_UD_SUB_TYPE_8814B 18\n#define BIT_MASK_UD_SUB_TYPE_8814B 0xf\n#define BIT_UD_SUB_TYPE_8814B(x)                                               \\\n\t(((x) & BIT_MASK_UD_SUB_TYPE_8814B) << BIT_SHIFT_UD_SUB_TYPE_8814B)\n#define BITS_UD_SUB_TYPE_8814B                                                 \\\n\t(BIT_MASK_UD_SUB_TYPE_8814B << BIT_SHIFT_UD_SUB_TYPE_8814B)\n#define BIT_CLEAR_UD_SUB_TYPE_8814B(x) ((x) & (~BITS_UD_SUB_TYPE_8814B))\n#define BIT_GET_UD_SUB_TYPE_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_UD_SUB_TYPE_8814B) & BIT_MASK_UD_SUB_TYPE_8814B)\n#define BIT_SET_UD_SUB_TYPE_8814B(x, v)                                        \\\n\t(BIT_CLEAR_UD_SUB_TYPE_8814B(x) | BIT_UD_SUB_TYPE_8814B(v))\n\n#define BIT_SHIFT_UD_TYPE_8814B 16\n#define BIT_MASK_UD_TYPE_8814B 0x3\n#define BIT_UD_TYPE_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_UD_TYPE_8814B) << BIT_SHIFT_UD_TYPE_8814B)\n#define BITS_UD_TYPE_8814B (BIT_MASK_UD_TYPE_8814B << BIT_SHIFT_UD_TYPE_8814B)\n#define BIT_CLEAR_UD_TYPE_8814B(x) ((x) & (~BITS_UD_TYPE_8814B))\n#define BIT_GET_UD_TYPE_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_UD_TYPE_8814B) & BIT_MASK_UD_TYPE_8814B)\n#define BIT_SET_UD_TYPE_8814B(x, v)                                            \\\n\t(BIT_CLEAR_UD_TYPE_8814B(x) | BIT_UD_TYPE_8814B(v))\n\n#define BIT_SHIFT_RPT_COUNTER_8814B 0\n#define BIT_MASK_RPT_COUNTER_8814B 0xffff\n#define BIT_RPT_COUNTER_8814B(x)                                               \\\n\t(((x) & BIT_MASK_RPT_COUNTER_8814B) << BIT_SHIFT_RPT_COUNTER_8814B)\n#define BITS_RPT_COUNTER_8814B                                                 \\\n\t(BIT_MASK_RPT_COUNTER_8814B << BIT_SHIFT_RPT_COUNTER_8814B)\n#define BIT_CLEAR_RPT_COUNTER_8814B(x) ((x) & (~BITS_RPT_COUNTER_8814B))\n#define BIT_GET_RPT_COUNTER_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_RPT_COUNTER_8814B) & BIT_MASK_RPT_COUNTER_8814B)\n#define BIT_SET_RPT_COUNTER_8814B(x, v)                                        \\\n\t(BIT_CLEAR_RPT_COUNTER_8814B(x) | BIT_RPT_COUNTER_8814B(v))\n\n/* 2 REG_WMAC_TRXPTCL_CTL_8814B\t(WMAC TX/RX PROTOCOL CONTROL REGISTER) */\n#define BIT_EN_TXCTS_INTXOP_8814B BIT(32)\n#define BIT_BLK_EDCA_BBSLP_8814B BIT(31)\n#define BIT_BLK_EDCA_BBSBY_8814B BIT(30)\n#define BIT_ACKTO_BLOCK_SCH_EN_8814B BIT(27)\n#define BIT_EIFS_BLOCK_SCH_EN_8814B BIT(26)\n#define BIT_PLCPCHK_RST_EIFS_8814B BIT(25)\n#define BIT_CCA_RST_EIFS_8814B BIT(24)\n#define BIT_DIS_UPD_MYRXPKTNAV_8814B BIT(23)\n#define BIT_EARLY_TXBA_8814B BIT(22)\n\n#define BIT_SHIFT_RESP_CHNBUSY_8814B 20\n#define BIT_MASK_RESP_CHNBUSY_8814B 0x3\n#define BIT_RESP_CHNBUSY_8814B(x)                                              \\\n\t(((x) & BIT_MASK_RESP_CHNBUSY_8814B) << BIT_SHIFT_RESP_CHNBUSY_8814B)\n#define BITS_RESP_CHNBUSY_8814B                                                \\\n\t(BIT_MASK_RESP_CHNBUSY_8814B << BIT_SHIFT_RESP_CHNBUSY_8814B)\n#define BIT_CLEAR_RESP_CHNBUSY_8814B(x) ((x) & (~BITS_RESP_CHNBUSY_8814B))\n#define BIT_GET_RESP_CHNBUSY_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RESP_CHNBUSY_8814B) & BIT_MASK_RESP_CHNBUSY_8814B)\n#define BIT_SET_RESP_CHNBUSY_8814B(x, v)                                       \\\n\t(BIT_CLEAR_RESP_CHNBUSY_8814B(x) | BIT_RESP_CHNBUSY_8814B(v))\n\n#define BIT_RESP_DCTS_EN_8814B BIT(19)\n#define BIT_RESP_DCFE_EN_8814B BIT(18)\n#define BIT_RESP_SPLCPEN_8814B BIT(17)\n#define BIT_RESP_SGIEN_8814B BIT(16)\n#define BIT_RESP_LDPC_EN_8814B BIT(15)\n#define BIT_DIS_RESP_ACKINCCA_8814B BIT(14)\n#define BIT_DIS_RESP_CTSINCCA_8814B BIT(13)\n\n#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B 10\n#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B 0x7\n#define BIT_R_WMAC_SECOND_CCA_TIMER_8814B(x)                                   \\\n\t(((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B)                        \\\n\t << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B)\n#define BITS_R_WMAC_SECOND_CCA_TIMER_8814B                                     \\\n\t(BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B                                \\\n\t << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B)\n#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8814B(x)                             \\\n\t((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8814B))\n#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8814B(x)                               \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B) &                    \\\n\t BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B)\n#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8814B(x, v)                            \\\n\t(BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8814B(x) |                          \\\n\t BIT_R_WMAC_SECOND_CCA_TIMER_8814B(v))\n\n#define BIT_SHIFT_RFMOD_8814B 7\n#define BIT_MASK_RFMOD_8814B 0x3\n#define BIT_RFMOD_8814B(x)                                                     \\\n\t(((x) & BIT_MASK_RFMOD_8814B) << BIT_SHIFT_RFMOD_8814B)\n#define BITS_RFMOD_8814B (BIT_MASK_RFMOD_8814B << BIT_SHIFT_RFMOD_8814B)\n#define BIT_CLEAR_RFMOD_8814B(x) ((x) & (~BITS_RFMOD_8814B))\n#define BIT_GET_RFMOD_8814B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RFMOD_8814B) & BIT_MASK_RFMOD_8814B)\n#define BIT_SET_RFMOD_8814B(x, v)                                              \\\n\t(BIT_CLEAR_RFMOD_8814B(x) | BIT_RFMOD_8814B(v))\n\n#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B 5\n#define BIT_MASK_RESP_CTS_DYNBW_SEL_8814B 0x3\n#define BIT_RESP_CTS_DYNBW_SEL_8814B(x)                                        \\\n\t(((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8814B)                             \\\n\t << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B)\n#define BITS_RESP_CTS_DYNBW_SEL_8814B                                          \\\n\t(BIT_MASK_RESP_CTS_DYNBW_SEL_8814B                                     \\\n\t << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B)\n#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8814B(x)                                  \\\n\t((x) & (~BITS_RESP_CTS_DYNBW_SEL_8814B))\n#define BIT_GET_RESP_CTS_DYNBW_SEL_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B) &                         \\\n\t BIT_MASK_RESP_CTS_DYNBW_SEL_8814B)\n#define BIT_SET_RESP_CTS_DYNBW_SEL_8814B(x, v)                                 \\\n\t(BIT_CLEAR_RESP_CTS_DYNBW_SEL_8814B(x) |                               \\\n\t BIT_RESP_CTS_DYNBW_SEL_8814B(v))\n\n#define BIT_DLY_TX_WAIT_RXANTSEL_8814B BIT(4)\n#define BIT_TXRESP_BY_RXANTSEL_8814B BIT(3)\n\n#define BIT_SHIFT_ORIG_DCTS_CHK_8814B 0\n#define BIT_MASK_ORIG_DCTS_CHK_8814B 0x3\n#define BIT_ORIG_DCTS_CHK_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ORIG_DCTS_CHK_8814B) << BIT_SHIFT_ORIG_DCTS_CHK_8814B)\n#define BITS_ORIG_DCTS_CHK_8814B                                               \\\n\t(BIT_MASK_ORIG_DCTS_CHK_8814B << BIT_SHIFT_ORIG_DCTS_CHK_8814B)\n#define BIT_CLEAR_ORIG_DCTS_CHK_8814B(x) ((x) & (~BITS_ORIG_DCTS_CHK_8814B))\n#define BIT_GET_ORIG_DCTS_CHK_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8814B) & BIT_MASK_ORIG_DCTS_CHK_8814B)\n#define BIT_SET_ORIG_DCTS_CHK_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ORIG_DCTS_CHK_8814B(x) | BIT_ORIG_DCTS_CHK_8814B(v))\n\n/* 2 REG_WMAC_TRXPTCL_CTL_H_8814B */\n\n#define BIT_SHIFT_ACKBA_TYPSEL_8814B 28\n#define BIT_MASK_ACKBA_TYPSEL_8814B 0xf\n#define BIT_ACKBA_TYPSEL_8814B(x)                                              \\\n\t(((x) & BIT_MASK_ACKBA_TYPSEL_8814B) << BIT_SHIFT_ACKBA_TYPSEL_8814B)\n#define BITS_ACKBA_TYPSEL_8814B                                                \\\n\t(BIT_MASK_ACKBA_TYPSEL_8814B << BIT_SHIFT_ACKBA_TYPSEL_8814B)\n#define BIT_CLEAR_ACKBA_TYPSEL_8814B(x) ((x) & (~BITS_ACKBA_TYPSEL_8814B))\n#define BIT_GET_ACKBA_TYPSEL_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_ACKBA_TYPSEL_8814B) & BIT_MASK_ACKBA_TYPSEL_8814B)\n#define BIT_SET_ACKBA_TYPSEL_8814B(x, v)                                       \\\n\t(BIT_CLEAR_ACKBA_TYPSEL_8814B(x) | BIT_ACKBA_TYPSEL_8814B(v))\n\n#define BIT_SHIFT_ACKBA_ACKPCHK_8814B 24\n#define BIT_MASK_ACKBA_ACKPCHK_8814B 0xf\n#define BIT_ACKBA_ACKPCHK_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ACKBA_ACKPCHK_8814B) << BIT_SHIFT_ACKBA_ACKPCHK_8814B)\n#define BITS_ACKBA_ACKPCHK_8814B                                               \\\n\t(BIT_MASK_ACKBA_ACKPCHK_8814B << BIT_SHIFT_ACKBA_ACKPCHK_8814B)\n#define BIT_CLEAR_ACKBA_ACKPCHK_8814B(x) ((x) & (~BITS_ACKBA_ACKPCHK_8814B))\n#define BIT_GET_ACKBA_ACKPCHK_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8814B) & BIT_MASK_ACKBA_ACKPCHK_8814B)\n#define BIT_SET_ACKBA_ACKPCHK_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ACKBA_ACKPCHK_8814B(x) | BIT_ACKBA_ACKPCHK_8814B(v))\n\n#define BIT_SHIFT_ACKBAR_TYPESEL_8814B 16\n#define BIT_MASK_ACKBAR_TYPESEL_8814B 0xff\n#define BIT_ACKBAR_TYPESEL_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACKBAR_TYPESEL_8814B)                                 \\\n\t << BIT_SHIFT_ACKBAR_TYPESEL_8814B)\n#define BITS_ACKBAR_TYPESEL_8814B                                              \\\n\t(BIT_MASK_ACKBAR_TYPESEL_8814B << BIT_SHIFT_ACKBAR_TYPESEL_8814B)\n#define BIT_CLEAR_ACKBAR_TYPESEL_8814B(x) ((x) & (~BITS_ACKBAR_TYPESEL_8814B))\n#define BIT_GET_ACKBAR_TYPESEL_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8814B) &                             \\\n\t BIT_MASK_ACKBAR_TYPESEL_8814B)\n#define BIT_SET_ACKBAR_TYPESEL_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACKBAR_TYPESEL_8814B(x) | BIT_ACKBAR_TYPESEL_8814B(v))\n\n#define BIT_SHIFT_ACKBAR_ACKPCHK_8814B 12\n#define BIT_MASK_ACKBAR_ACKPCHK_8814B 0xf\n#define BIT_ACKBAR_ACKPCHK_8814B(x)                                            \\\n\t(((x) & BIT_MASK_ACKBAR_ACKPCHK_8814B)                                 \\\n\t << BIT_SHIFT_ACKBAR_ACKPCHK_8814B)\n#define BITS_ACKBAR_ACKPCHK_8814B                                              \\\n\t(BIT_MASK_ACKBAR_ACKPCHK_8814B << BIT_SHIFT_ACKBAR_ACKPCHK_8814B)\n#define BIT_CLEAR_ACKBAR_ACKPCHK_8814B(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8814B))\n#define BIT_GET_ACKBAR_ACKPCHK_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8814B) &                             \\\n\t BIT_MASK_ACKBAR_ACKPCHK_8814B)\n#define BIT_SET_ACKBAR_ACKPCHK_8814B(x, v)                                     \\\n\t(BIT_CLEAR_ACKBAR_ACKPCHK_8814B(x) | BIT_ACKBAR_ACKPCHK_8814B(v))\n\n#define BIT_RXBA_IGNOREA2_V1_8814B BIT(10)\n#define BIT_EN_SAVE_ALL_TXOPADDR_V1_8814B BIT(9)\n#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1_8814B BIT(8)\n#define BIT_DIS_TXBA_AMPDUFCSERR_V1_8814B BIT(7)\n#define BIT_DIS_TXBA_RXBARINFULL_V1_8814B BIT(6)\n#define BIT_DIS_TXCFE_INFULL_V1_8814B BIT(5)\n#define BIT_DIS_TXCTS_INFULL_V1_8814B BIT(4)\n#define BIT_EN_TXACKBA_IN_TX_RDG_V1_8814B BIT(3)\n#define BIT_EN_TXACKBA_IN_TXOP_V1_8814B BIT(2)\n#define BIT_EN_TXCTS_IN_RXNAV_V1_8814B BIT(1)\n#define BIT_EN_TXCTS_INTXOP_V1_8814B BIT(0)\n\n/* 2 REG_CAMCMD_8814B (CAM COMMAND REGISTER) */\n#define BIT_SECCAM_POLLING_8814B BIT(31)\n#define BIT_SECCAM_CLR_8814B BIT(30)\n#define BIT_SECCAM_WE_8814B BIT(16)\n\n#define BIT_SHIFT_SECCAM_ADDR_V2_8814B 0\n#define BIT_MASK_SECCAM_ADDR_V2_8814B 0x3ff\n#define BIT_SECCAM_ADDR_V2_8814B(x)                                            \\\n\t(((x) & BIT_MASK_SECCAM_ADDR_V2_8814B)                                 \\\n\t << BIT_SHIFT_SECCAM_ADDR_V2_8814B)\n#define BITS_SECCAM_ADDR_V2_8814B                                              \\\n\t(BIT_MASK_SECCAM_ADDR_V2_8814B << BIT_SHIFT_SECCAM_ADDR_V2_8814B)\n#define BIT_CLEAR_SECCAM_ADDR_V2_8814B(x) ((x) & (~BITS_SECCAM_ADDR_V2_8814B))\n#define BIT_GET_SECCAM_ADDR_V2_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8814B) &                             \\\n\t BIT_MASK_SECCAM_ADDR_V2_8814B)\n#define BIT_SET_SECCAM_ADDR_V2_8814B(x, v)                                     \\\n\t(BIT_CLEAR_SECCAM_ADDR_V2_8814B(x) | BIT_SECCAM_ADDR_V2_8814B(v))\n\n/* 2 REG_CAMWRITE_8814B (CAM WRITE REGISTER) */\n\n#define BIT_SHIFT_CAMW_DATA_8814B 0\n#define BIT_MASK_CAMW_DATA_8814B 0xffffffffL\n#define BIT_CAMW_DATA_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_CAMW_DATA_8814B) << BIT_SHIFT_CAMW_DATA_8814B)\n#define BITS_CAMW_DATA_8814B                                                   \\\n\t(BIT_MASK_CAMW_DATA_8814B << BIT_SHIFT_CAMW_DATA_8814B)\n#define BIT_CLEAR_CAMW_DATA_8814B(x) ((x) & (~BITS_CAMW_DATA_8814B))\n#define BIT_GET_CAMW_DATA_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_CAMW_DATA_8814B) & BIT_MASK_CAMW_DATA_8814B)\n#define BIT_SET_CAMW_DATA_8814B(x, v)                                          \\\n\t(BIT_CLEAR_CAMW_DATA_8814B(x) | BIT_CAMW_DATA_8814B(v))\n\n/* 2 REG_CAMREAD_8814B (CAM READ REGISTER) */\n\n#define BIT_SHIFT_CAMR_DATA_8814B 0\n#define BIT_MASK_CAMR_DATA_8814B 0xffffffffL\n#define BIT_CAMR_DATA_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_CAMR_DATA_8814B) << BIT_SHIFT_CAMR_DATA_8814B)\n#define BITS_CAMR_DATA_8814B                                                   \\\n\t(BIT_MASK_CAMR_DATA_8814B << BIT_SHIFT_CAMR_DATA_8814B)\n#define BIT_CLEAR_CAMR_DATA_8814B(x) ((x) & (~BITS_CAMR_DATA_8814B))\n#define BIT_GET_CAMR_DATA_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_CAMR_DATA_8814B) & BIT_MASK_CAMR_DATA_8814B)\n#define BIT_SET_CAMR_DATA_8814B(x, v)                                          \\\n\t(BIT_CLEAR_CAMR_DATA_8814B(x) | BIT_CAMR_DATA_8814B(v))\n\n/* 2 REG_CAMDBG_8814B (CAM DEBUG REGISTER) */\n#define BIT_SECCAM_INFO_8814B BIT(31)\n#define BIT_SEC_KEYFOUND_8814B BIT(15)\n\n#define BIT_SHIFT_CAMDBG_SEC_TYPE_8814B 12\n#define BIT_MASK_CAMDBG_SEC_TYPE_8814B 0x7\n#define BIT_CAMDBG_SEC_TYPE_8814B(x)                                           \\\n\t(((x) & BIT_MASK_CAMDBG_SEC_TYPE_8814B)                                \\\n\t << BIT_SHIFT_CAMDBG_SEC_TYPE_8814B)\n#define BITS_CAMDBG_SEC_TYPE_8814B                                             \\\n\t(BIT_MASK_CAMDBG_SEC_TYPE_8814B << BIT_SHIFT_CAMDBG_SEC_TYPE_8814B)\n#define BIT_CLEAR_CAMDBG_SEC_TYPE_8814B(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8814B))\n#define BIT_GET_CAMDBG_SEC_TYPE_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8814B) &                            \\\n\t BIT_MASK_CAMDBG_SEC_TYPE_8814B)\n#define BIT_SET_CAMDBG_SEC_TYPE_8814B(x, v)                                    \\\n\t(BIT_CLEAR_CAMDBG_SEC_TYPE_8814B(x) | BIT_CAMDBG_SEC_TYPE_8814B(v))\n\n#define BIT_CAMDBG_EXT_SECTYPE_8814B BIT(11)\n\n#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B 5\n#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B 0x1f\n#define BIT_CAMDBG_MIC_KEY_IDX_8814B(x)                                        \\\n\t(((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B)                             \\\n\t << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B)\n#define BITS_CAMDBG_MIC_KEY_IDX_8814B                                          \\\n\t(BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B                                     \\\n\t << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B)\n#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8814B(x)                                  \\\n\t((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8814B))\n#define BIT_GET_CAMDBG_MIC_KEY_IDX_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B) &                         \\\n\t BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B)\n#define BIT_SET_CAMDBG_MIC_KEY_IDX_8814B(x, v)                                 \\\n\t(BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8814B(x) |                               \\\n\t BIT_CAMDBG_MIC_KEY_IDX_8814B(v))\n\n#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B 0\n#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B 0x1f\n#define BIT_CAMDBG_SEC_KEY_IDX_8814B(x)                                        \\\n\t(((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B)                             \\\n\t << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B)\n#define BITS_CAMDBG_SEC_KEY_IDX_8814B                                          \\\n\t(BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B                                     \\\n\t << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B)\n#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8814B(x)                                  \\\n\t((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8814B))\n#define BIT_GET_CAMDBG_SEC_KEY_IDX_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B) &                         \\\n\t BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B)\n#define BIT_SET_CAMDBG_SEC_KEY_IDX_8814B(x, v)                                 \\\n\t(BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8814B(x) |                               \\\n\t BIT_CAMDBG_SEC_KEY_IDX_8814B(v))\n\n/* 2 REG_SECCFG_8814B (SECURITY CONFIGURATION REGISTER) */\n#define BIT_DIS_GCLK_WAPI_8814B BIT(15)\n#define BIT_DIS_GCLK_AES_8814B BIT(14)\n#define BIT_DIS_GCLK_TKIP_8814B BIT(13)\n#define BIT_AES_SEL_QC_1_8814B BIT(12)\n#define BIT_AES_SEL_QC_0_8814B BIT(11)\n#define BIT_CHK_BMC_8814B BIT(9)\n#define BIT_CHK_KEYID_8814B BIT(8)\n#define BIT_RXBCUSEDK_8814B BIT(7)\n#define BIT_TXBCUSEDK_8814B BIT(6)\n#define BIT_NOSKMC_8814B BIT(5)\n#define BIT_SKBYA2_8814B BIT(4)\n#define BIT_RXDEC_8814B BIT(3)\n#define BIT_TXENC_8814B BIT(2)\n#define BIT_RXUHUSEDK_8814B BIT(1)\n#define BIT_TXUHUSEDK_8814B BIT(0)\n\n/* 2 REG_RXFILTER_CATEGORY_1_8814B */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_1_8814B 0\n#define BIT_MASK_RXFILTER_CATEGORY_1_8814B 0xff\n#define BIT_RXFILTER_CATEGORY_1_8814B(x)                                       \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_1_8814B)                            \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_1_8814B)\n#define BITS_RXFILTER_CATEGORY_1_8814B                                         \\\n\t(BIT_MASK_RXFILTER_CATEGORY_1_8814B                                    \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_1_8814B)\n#define BIT_CLEAR_RXFILTER_CATEGORY_1_8814B(x)                                 \\\n\t((x) & (~BITS_RXFILTER_CATEGORY_1_8814B))\n#define BIT_GET_RXFILTER_CATEGORY_1_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8814B) &                        \\\n\t BIT_MASK_RXFILTER_CATEGORY_1_8814B)\n#define BIT_SET_RXFILTER_CATEGORY_1_8814B(x, v)                                \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_1_8814B(x) |                              \\\n\t BIT_RXFILTER_CATEGORY_1_8814B(v))\n\n/* 2 REG_RXFILTER_ACTION_1_8814B */\n\n#define BIT_SHIFT_RXFILTER_ACTION_1_8814B 0\n#define BIT_MASK_RXFILTER_ACTION_1_8814B 0xff\n#define BIT_RXFILTER_ACTION_1_8814B(x)                                         \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_1_8814B)                              \\\n\t << BIT_SHIFT_RXFILTER_ACTION_1_8814B)\n#define BITS_RXFILTER_ACTION_1_8814B                                           \\\n\t(BIT_MASK_RXFILTER_ACTION_1_8814B << BIT_SHIFT_RXFILTER_ACTION_1_8814B)\n#define BIT_CLEAR_RXFILTER_ACTION_1_8814B(x)                                   \\\n\t((x) & (~BITS_RXFILTER_ACTION_1_8814B))\n#define BIT_GET_RXFILTER_ACTION_1_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8814B) &                          \\\n\t BIT_MASK_RXFILTER_ACTION_1_8814B)\n#define BIT_SET_RXFILTER_ACTION_1_8814B(x, v)                                  \\\n\t(BIT_CLEAR_RXFILTER_ACTION_1_8814B(x) | BIT_RXFILTER_ACTION_1_8814B(v))\n\n/* 2 REG_RXFILTER_CATEGORY_2_8814B */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_2_8814B 0\n#define BIT_MASK_RXFILTER_CATEGORY_2_8814B 0xff\n#define BIT_RXFILTER_CATEGORY_2_8814B(x)                                       \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_2_8814B)                            \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_2_8814B)\n#define BITS_RXFILTER_CATEGORY_2_8814B                                         \\\n\t(BIT_MASK_RXFILTER_CATEGORY_2_8814B                                    \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_2_8814B)\n#define BIT_CLEAR_RXFILTER_CATEGORY_2_8814B(x)                                 \\\n\t((x) & (~BITS_RXFILTER_CATEGORY_2_8814B))\n#define BIT_GET_RXFILTER_CATEGORY_2_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8814B) &                        \\\n\t BIT_MASK_RXFILTER_CATEGORY_2_8814B)\n#define BIT_SET_RXFILTER_CATEGORY_2_8814B(x, v)                                \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_2_8814B(x) |                              \\\n\t BIT_RXFILTER_CATEGORY_2_8814B(v))\n\n/* 2 REG_RXFILTER_ACTION_2_8814B */\n\n#define BIT_SHIFT_RXFILTER_ACTION_2_8814B 0\n#define BIT_MASK_RXFILTER_ACTION_2_8814B 0xff\n#define BIT_RXFILTER_ACTION_2_8814B(x)                                         \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_2_8814B)                              \\\n\t << BIT_SHIFT_RXFILTER_ACTION_2_8814B)\n#define BITS_RXFILTER_ACTION_2_8814B                                           \\\n\t(BIT_MASK_RXFILTER_ACTION_2_8814B << BIT_SHIFT_RXFILTER_ACTION_2_8814B)\n#define BIT_CLEAR_RXFILTER_ACTION_2_8814B(x)                                   \\\n\t((x) & (~BITS_RXFILTER_ACTION_2_8814B))\n#define BIT_GET_RXFILTER_ACTION_2_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8814B) &                          \\\n\t BIT_MASK_RXFILTER_ACTION_2_8814B)\n#define BIT_SET_RXFILTER_ACTION_2_8814B(x, v)                                  \\\n\t(BIT_CLEAR_RXFILTER_ACTION_2_8814B(x) | BIT_RXFILTER_ACTION_2_8814B(v))\n\n/* 2 REG_RXFILTER_CATEGORY_3_8814B */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_3_8814B 0\n#define BIT_MASK_RXFILTER_CATEGORY_3_8814B 0xff\n#define BIT_RXFILTER_CATEGORY_3_8814B(x)                                       \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_3_8814B)                            \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_3_8814B)\n#define BITS_RXFILTER_CATEGORY_3_8814B                                         \\\n\t(BIT_MASK_RXFILTER_CATEGORY_3_8814B                                    \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_3_8814B)\n#define BIT_CLEAR_RXFILTER_CATEGORY_3_8814B(x)                                 \\\n\t((x) & (~BITS_RXFILTER_CATEGORY_3_8814B))\n#define BIT_GET_RXFILTER_CATEGORY_3_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8814B) &                        \\\n\t BIT_MASK_RXFILTER_CATEGORY_3_8814B)\n#define BIT_SET_RXFILTER_CATEGORY_3_8814B(x, v)                                \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_3_8814B(x) |                              \\\n\t BIT_RXFILTER_CATEGORY_3_8814B(v))\n\n/* 2 REG_RXFILTER_ACTION_3_8814B */\n\n#define BIT_SHIFT_RXFILTER_ACTION_3_8814B 0\n#define BIT_MASK_RXFILTER_ACTION_3_8814B 0xff\n#define BIT_RXFILTER_ACTION_3_8814B(x)                                         \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_3_8814B)                              \\\n\t << BIT_SHIFT_RXFILTER_ACTION_3_8814B)\n#define BITS_RXFILTER_ACTION_3_8814B                                           \\\n\t(BIT_MASK_RXFILTER_ACTION_3_8814B << BIT_SHIFT_RXFILTER_ACTION_3_8814B)\n#define BIT_CLEAR_RXFILTER_ACTION_3_8814B(x)                                   \\\n\t((x) & (~BITS_RXFILTER_ACTION_3_8814B))\n#define BIT_GET_RXFILTER_ACTION_3_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8814B) &                          \\\n\t BIT_MASK_RXFILTER_ACTION_3_8814B)\n#define BIT_SET_RXFILTER_ACTION_3_8814B(x, v)                                  \\\n\t(BIT_CLEAR_RXFILTER_ACTION_3_8814B(x) | BIT_RXFILTER_ACTION_3_8814B(v))\n\n/* 2 REG_RXFLTMAP3_8814B (RX FILTER MAP GROUP 3) */\n#define BIT_MGTFLT15EN_FW_8814B BIT(15)\n#define BIT_MGTFLT14EN_FW_8814B BIT(14)\n#define BIT_MGTFLT13EN_FW_8814B BIT(13)\n#define BIT_MGTFLT12EN_FW_8814B BIT(12)\n#define BIT_MGTFLT11EN_FW_8814B BIT(11)\n#define BIT_MGTFLT10EN_FW_8814B BIT(10)\n#define BIT_MGTFLT9EN_FW_8814B BIT(9)\n#define BIT_MGTFLT8EN_FW_8814B BIT(8)\n#define BIT_MGTFLT7EN_FW_8814B BIT(7)\n#define BIT_MGTFLT6EN_FW_8814B BIT(6)\n#define BIT_MGTFLT5EN_FW_8814B BIT(5)\n#define BIT_MGTFLT4EN_FW_8814B BIT(4)\n#define BIT_MGTFLT3EN_FW_8814B BIT(3)\n#define BIT_MGTFLT2EN_FW_8814B BIT(2)\n#define BIT_MGTFLT1EN_FW_8814B BIT(1)\n#define BIT_MGTFLT0EN_FW_8814B BIT(0)\n\n/* 2 REG_RXFLTMAP4_8814B (RX FILTER MAP GROUP 4) */\n#define BIT_CTRLFLT15EN_FW_8814B BIT(15)\n#define BIT_CTRLFLT14EN_FW_8814B BIT(14)\n#define BIT_CTRLFLT13EN_FW_8814B BIT(13)\n#define BIT_CTRLFLT12EN_FW_8814B BIT(12)\n#define BIT_CTRLFLT11EN_FW_8814B BIT(11)\n#define BIT_CTRLFLT10EN_FW_8814B BIT(10)\n#define BIT_CTRLFLT9EN_FW_8814B BIT(9)\n#define BIT_CTRLFLT8EN_FW_8814B BIT(8)\n#define BIT_CTRLFLT7EN_FW_8814B BIT(7)\n#define BIT_CTRLFLT6EN_FW_8814B BIT(6)\n#define BIT_CTRLFLT5EN_FW_8814B BIT(5)\n#define BIT_CTRLFLT4EN_FW_8814B BIT(4)\n#define BIT_CTRLFLT3EN_FW_8814B BIT(3)\n#define BIT_CTRLFLT2EN_FW_8814B BIT(2)\n#define BIT_CTRLFLT1EN_FW_8814B BIT(1)\n#define BIT_CTRLFLT0EN_FW_8814B BIT(0)\n\n/* 2 REG_RXFLTMAP5_8814B (RX FILTER MAP GROUP 5) */\n#define BIT_DATAFLT15EN_FW_8814B BIT(15)\n#define BIT_DATAFLT14EN_FW_8814B BIT(14)\n#define BIT_DATAFLT13EN_FW_8814B BIT(13)\n#define BIT_DATAFLT12EN_FW_8814B BIT(12)\n#define BIT_DATAFLT11EN_FW_8814B BIT(11)\n#define BIT_DATAFLT10EN_FW_8814B BIT(10)\n#define BIT_DATAFLT9EN_FW_8814B BIT(9)\n#define BIT_DATAFLT8EN_FW_8814B BIT(8)\n#define BIT_DATAFLT7EN_FW_8814B BIT(7)\n#define BIT_DATAFLT6EN_FW_8814B BIT(6)\n#define BIT_DATAFLT5EN_FW_8814B BIT(5)\n#define BIT_DATAFLT4EN_FW_8814B BIT(4)\n#define BIT_DATAFLT3EN_FW_8814B BIT(3)\n#define BIT_DATAFLT2EN_FW_8814B BIT(2)\n#define BIT_DATAFLT1EN_FW_8814B BIT(1)\n#define BIT_DATAFLT0EN_FW_8814B BIT(0)\n\n/* 2 REG_RXFLTMAP6_8814B (RX FILTER MAP GROUP 6) */\n#define BIT_ACTIONFLT15EN_FW_8814B BIT(15)\n#define BIT_ACTIONFLT14EN_FW_8814B BIT(14)\n#define BIT_ACTIONFLT13EN_FW_8814B BIT(13)\n#define BIT_ACTIONFLT12EN_FW_8814B BIT(12)\n#define BIT_ACTIONFLT11EN_FW_8814B BIT(11)\n#define BIT_ACTIONFLT10EN_FW_8814B BIT(10)\n#define BIT_ACTIONFLT9EN_FW_8814B BIT(9)\n#define BIT_ACTIONFLT8EN_FW_8814B BIT(8)\n#define BIT_ACTIONFLT7EN_FW_8814B BIT(7)\n#define BIT_ACTIONFLT6EN_FW_8814B BIT(6)\n#define BIT_ACTIONFLT5EN_FW_8814B BIT(5)\n#define BIT_ACTIONFLT4EN_FW_8814B BIT(4)\n#define BIT_ACTIONFLT3EN_FW_8814B BIT(3)\n#define BIT_ACTIONFLT2EN_FW_8814B BIT(2)\n#define BIT_ACTIONFLT1EN_FW_8814B BIT(1)\n#define BIT_ACTIONFLT0EN_FW_8814B BIT(0)\n\n/* 2 REG_WOW_CTRL_8814B (WAKE ON WLAN CONTROL REGISTER) */\n\n#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B 6\n#define BIT_MASK_PSF_BSSIDSEL_B2B1_8814B 0x3\n#define BIT_PSF_BSSIDSEL_B2B1_8814B(x)                                         \\\n\t(((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8814B)                              \\\n\t << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B)\n#define BITS_PSF_BSSIDSEL_B2B1_8814B                                           \\\n\t(BIT_MASK_PSF_BSSIDSEL_B2B1_8814B << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B)\n#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8814B(x)                                   \\\n\t((x) & (~BITS_PSF_BSSIDSEL_B2B1_8814B))\n#define BIT_GET_PSF_BSSIDSEL_B2B1_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B) &                          \\\n\t BIT_MASK_PSF_BSSIDSEL_B2B1_8814B)\n#define BIT_SET_PSF_BSSIDSEL_B2B1_8814B(x, v)                                  \\\n\t(BIT_CLEAR_PSF_BSSIDSEL_B2B1_8814B(x) | BIT_PSF_BSSIDSEL_B2B1_8814B(v))\n\n#define BIT_WOWHCI_8814B BIT(5)\n#define BIT_PSF_BSSIDSEL_B0_8814B BIT(4)\n#define BIT_UWF_8814B BIT(3)\n#define BIT_MAGIC_8814B BIT(2)\n#define BIT_WOWEN_8814B BIT(1)\n#define BIT_FORCE_WAKEUP_8814B BIT(0)\n\n/* 2 REG_NAN_RX_TSF_FILTER_8814B(NAN_RX_TSF_ADDRESS_FILTER) */\n#define BIT_CHK_TSF_TA_8814B BIT(2)\n#define BIT_CHK_TSF_CBSSID_8814B BIT(1)\n#define BIT_CHK_TSF_EN_8814B BIT(0)\n\n/* 2 REG_PS_RX_INFO_8814B (POWER SAVE RX INFORMATION REGISTER) */\n\n#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B 5\n#define BIT_MASK_PORTSEL__PS_RX_INFO_8814B 0x7\n#define BIT_PORTSEL__PS_RX_INFO_8814B(x)                                       \\\n\t(((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8814B)                            \\\n\t << BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B)\n#define BITS_PORTSEL__PS_RX_INFO_8814B                                         \\\n\t(BIT_MASK_PORTSEL__PS_RX_INFO_8814B                                    \\\n\t << BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B)\n#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8814B(x)                                 \\\n\t((x) & (~BITS_PORTSEL__PS_RX_INFO_8814B))\n#define BIT_GET_PORTSEL__PS_RX_INFO_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B) &                        \\\n\t BIT_MASK_PORTSEL__PS_RX_INFO_8814B)\n#define BIT_SET_PORTSEL__PS_RX_INFO_8814B(x, v)                                \\\n\t(BIT_CLEAR_PORTSEL__PS_RX_INFO_8814B(x) |                              \\\n\t BIT_PORTSEL__PS_RX_INFO_8814B(v))\n\n#define BIT_RXCTRLIN0_8814B BIT(4)\n#define BIT_RXMGTIN0_8814B BIT(3)\n#define BIT_RXDATAIN2_8814B BIT(2)\n#define BIT_RXDATAIN1_8814B BIT(1)\n#define BIT_RXDATAIN0_8814B BIT(0)\n\n/* 2 REG_WMMPS_UAPSD_TID_8814B (WMM POWER SAVE UAPSD TID REGISTER) */\n#define BIT_WMMPS_UAPSD_TID7_8814B BIT(7)\n#define BIT_WMMPS_UAPSD_TID6_8814B BIT(6)\n#define BIT_WMMPS_UAPSD_TID5_8814B BIT(5)\n#define BIT_WMMPS_UAPSD_TID4_8814B BIT(4)\n#define BIT_WMMPS_UAPSD_TID3_8814B BIT(3)\n#define BIT_WMMPS_UAPSD_TID2_8814B BIT(2)\n#define BIT_WMMPS_UAPSD_TID1_8814B BIT(1)\n#define BIT_WMMPS_UAPSD_TID0_8814B BIT(0)\n\n/* 2 REG_LPNAV_CTRL_8814B (LOW POWER NAV CONTROL REGISTER) */\n\n/* 2 REG_WKFMCAM_CMD_8814B (WAKEUP FRAME CAM COMMAND REGISTER) */\n#define BIT_WKFCAM_POLLING_V1_8814B BIT(31)\n#define BIT_WKFCAM_CLR_V1_8814B BIT(30)\n#define BIT_WKFCAM_WE_8814B BIT(16)\n\n#define BIT_SHIFT_WKFCAM_ADDR_V2_8814B 8\n#define BIT_MASK_WKFCAM_ADDR_V2_8814B 0xff\n#define BIT_WKFCAM_ADDR_V2_8814B(x)                                            \\\n\t(((x) & BIT_MASK_WKFCAM_ADDR_V2_8814B)                                 \\\n\t << BIT_SHIFT_WKFCAM_ADDR_V2_8814B)\n#define BITS_WKFCAM_ADDR_V2_8814B                                              \\\n\t(BIT_MASK_WKFCAM_ADDR_V2_8814B << BIT_SHIFT_WKFCAM_ADDR_V2_8814B)\n#define BIT_CLEAR_WKFCAM_ADDR_V2_8814B(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8814B))\n#define BIT_GET_WKFCAM_ADDR_V2_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8814B) &                             \\\n\t BIT_MASK_WKFCAM_ADDR_V2_8814B)\n#define BIT_SET_WKFCAM_ADDR_V2_8814B(x, v)                                     \\\n\t(BIT_CLEAR_WKFCAM_ADDR_V2_8814B(x) | BIT_WKFCAM_ADDR_V2_8814B(v))\n\n#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B 0\n#define BIT_MASK_WKFCAM_CAM_NUM_V1_8814B 0xff\n#define BIT_WKFCAM_CAM_NUM_V1_8814B(x)                                         \\\n\t(((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8814B)                              \\\n\t << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B)\n#define BITS_WKFCAM_CAM_NUM_V1_8814B                                           \\\n\t(BIT_MASK_WKFCAM_CAM_NUM_V1_8814B << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B)\n#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8814B(x)                                   \\\n\t((x) & (~BITS_WKFCAM_CAM_NUM_V1_8814B))\n#define BIT_GET_WKFCAM_CAM_NUM_V1_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B) &                          \\\n\t BIT_MASK_WKFCAM_CAM_NUM_V1_8814B)\n#define BIT_SET_WKFCAM_CAM_NUM_V1_8814B(x, v)                                  \\\n\t(BIT_CLEAR_WKFCAM_CAM_NUM_V1_8814B(x) | BIT_WKFCAM_CAM_NUM_V1_8814B(v))\n\n/* 2 REG_WKFMCAM_RWD_8814B (WAKEUP FRAME READ/WRITE DATA) */\n\n#define BIT_SHIFT_WKFMCAM_RWD_8814B 0\n#define BIT_MASK_WKFMCAM_RWD_8814B 0xffffffffL\n#define BIT_WKFMCAM_RWD_8814B(x)                                               \\\n\t(((x) & BIT_MASK_WKFMCAM_RWD_8814B) << BIT_SHIFT_WKFMCAM_RWD_8814B)\n#define BITS_WKFMCAM_RWD_8814B                                                 \\\n\t(BIT_MASK_WKFMCAM_RWD_8814B << BIT_SHIFT_WKFMCAM_RWD_8814B)\n#define BIT_CLEAR_WKFMCAM_RWD_8814B(x) ((x) & (~BITS_WKFMCAM_RWD_8814B))\n#define BIT_GET_WKFMCAM_RWD_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_WKFMCAM_RWD_8814B) & BIT_MASK_WKFMCAM_RWD_8814B)\n#define BIT_SET_WKFMCAM_RWD_8814B(x, v)                                        \\\n\t(BIT_CLEAR_WKFMCAM_RWD_8814B(x) | BIT_WKFMCAM_RWD_8814B(v))\n\n/* 2 REG_RXFLTMAP0_8814B (RX FILTER MAP GROUP 0) */\n#define BIT_MGTFLT15EN_8814B BIT(15)\n#define BIT_MGTFLT14EN_8814B BIT(14)\n#define BIT_MGTFLT13EN_8814B BIT(13)\n#define BIT_MGTFLT12EN_8814B BIT(12)\n#define BIT_MGTFLT11EN_8814B BIT(11)\n#define BIT_MGTFLT10EN_8814B BIT(10)\n#define BIT_MGTFLT9EN_8814B BIT(9)\n#define BIT_MGTFLT8EN_8814B BIT(8)\n#define BIT_MGTFLT7EN_8814B BIT(7)\n#define BIT_MGTFLT6EN_8814B BIT(6)\n#define BIT_MGTFLT5EN_8814B BIT(5)\n#define BIT_MGTFLT4EN_8814B BIT(4)\n#define BIT_MGTFLT3EN_8814B BIT(3)\n#define BIT_MGTFLT2EN_8814B BIT(2)\n#define BIT_MGTFLT1EN_8814B BIT(1)\n#define BIT_MGTFLT0EN_8814B BIT(0)\n\n/* 2 REG_RXFLTMAP1_8814B (RX FILTER MAP GROUP 1) */\n#define BIT_CTRLFLT15EN_8814B BIT(15)\n#define BIT_CTRLFLT14EN_8814B BIT(14)\n#define BIT_CTRLFLT13EN_8814B BIT(13)\n#define BIT_CTRLFLT12EN_8814B BIT(12)\n#define BIT_CTRLFLT11EN_8814B BIT(11)\n#define BIT_CTRLFLT10EN_8814B BIT(10)\n#define BIT_CTRLFLT9EN_8814B BIT(9)\n#define BIT_CTRLFLT8EN_8814B BIT(8)\n#define BIT_CTRLFLT7EN_8814B BIT(7)\n#define BIT_CTRLFLT6EN_8814B BIT(6)\n#define BIT_CTRLFLT5EN_8814B BIT(5)\n#define BIT_CTRLFLT4EN_8814B BIT(4)\n#define BIT_CTRLFLT3EN_8814B BIT(3)\n#define BIT_CTRLFLT2EN_8814B BIT(2)\n#define BIT_CTRLFLT1EN_8814B BIT(1)\n#define BIT_CTRLFLT0EN_8814B BIT(0)\n\n/* 2 REG_RXFLTMAP2_8814B (RX FILTER MAP GROUP 2) */\n#define BIT_DATAFLT15EN_8814B BIT(15)\n#define BIT_DATAFLT14EN_8814B BIT(14)\n#define BIT_DATAFLT13EN_8814B BIT(13)\n#define BIT_DATAFLT12EN_8814B BIT(12)\n#define BIT_DATAFLT11EN_8814B BIT(11)\n#define BIT_DATAFLT10EN_8814B BIT(10)\n#define BIT_DATAFLT9EN_8814B BIT(9)\n#define BIT_DATAFLT8EN_8814B BIT(8)\n#define BIT_DATAFLT7EN_8814B BIT(7)\n#define BIT_DATAFLT6EN_8814B BIT(6)\n#define BIT_DATAFLT5EN_8814B BIT(5)\n#define BIT_DATAFLT4EN_8814B BIT(4)\n#define BIT_DATAFLT3EN_8814B BIT(3)\n#define BIT_DATAFLT2EN_8814B BIT(2)\n#define BIT_DATAFLT1EN_8814B BIT(1)\n#define BIT_DATAFLT0EN_8814B BIT(0)\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_BCN_PSR_RPT_8814B (BEACON PARSER REPORT REGISTER) */\n\n#define BIT_SHIFT_DTIM_CNT_8814B 24\n#define BIT_MASK_DTIM_CNT_8814B 0xff\n#define BIT_DTIM_CNT_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_DTIM_CNT_8814B) << BIT_SHIFT_DTIM_CNT_8814B)\n#define BITS_DTIM_CNT_8814B                                                    \\\n\t(BIT_MASK_DTIM_CNT_8814B << BIT_SHIFT_DTIM_CNT_8814B)\n#define BIT_CLEAR_DTIM_CNT_8814B(x) ((x) & (~BITS_DTIM_CNT_8814B))\n#define BIT_GET_DTIM_CNT_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT_8814B) & BIT_MASK_DTIM_CNT_8814B)\n#define BIT_SET_DTIM_CNT_8814B(x, v)                                           \\\n\t(BIT_CLEAR_DTIM_CNT_8814B(x) | BIT_DTIM_CNT_8814B(v))\n\n#define BIT_SHIFT_DTIM_PERIOD_8814B 16\n#define BIT_MASK_DTIM_PERIOD_8814B 0xff\n#define BIT_DTIM_PERIOD_8814B(x)                                               \\\n\t(((x) & BIT_MASK_DTIM_PERIOD_8814B) << BIT_SHIFT_DTIM_PERIOD_8814B)\n#define BITS_DTIM_PERIOD_8814B                                                 \\\n\t(BIT_MASK_DTIM_PERIOD_8814B << BIT_SHIFT_DTIM_PERIOD_8814B)\n#define BIT_CLEAR_DTIM_PERIOD_8814B(x) ((x) & (~BITS_DTIM_PERIOD_8814B))\n#define BIT_GET_DTIM_PERIOD_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD_8814B) & BIT_MASK_DTIM_PERIOD_8814B)\n#define BIT_SET_DTIM_PERIOD_8814B(x, v)                                        \\\n\t(BIT_CLEAR_DTIM_PERIOD_8814B(x) | BIT_DTIM_PERIOD_8814B(v))\n\n#define BIT_DTIM_8814B BIT(15)\n#define BIT_TIM_8814B BIT(14)\n#define BIT_RPT_VALID_8814B BIT(13)\n\n#define BIT_SHIFT_PS_AID_0_8814B 0\n#define BIT_MASK_PS_AID_0_8814B 0x7ff\n#define BIT_PS_AID_0_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_0_8814B) << BIT_SHIFT_PS_AID_0_8814B)\n#define BITS_PS_AID_0_8814B                                                    \\\n\t(BIT_MASK_PS_AID_0_8814B << BIT_SHIFT_PS_AID_0_8814B)\n#define BIT_CLEAR_PS_AID_0_8814B(x) ((x) & (~BITS_PS_AID_0_8814B))\n#define BIT_GET_PS_AID_0_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_0_8814B) & BIT_MASK_PS_AID_0_8814B)\n#define BIT_SET_PS_AID_0_8814B(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_0_8814B(x) | BIT_PS_AID_0_8814B(v))\n\n/* 2 REG_FLC_RPC_8814B (FW LPS CONDITION -- RX PKT COUNTER) */\n\n#define BIT_SHIFT_FLC_RPC_8814B 0\n#define BIT_MASK_FLC_RPC_8814B 0xff\n#define BIT_FLC_RPC_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_FLC_RPC_8814B) << BIT_SHIFT_FLC_RPC_8814B)\n#define BITS_FLC_RPC_8814B (BIT_MASK_FLC_RPC_8814B << BIT_SHIFT_FLC_RPC_8814B)\n#define BIT_CLEAR_FLC_RPC_8814B(x) ((x) & (~BITS_FLC_RPC_8814B))\n#define BIT_GET_FLC_RPC_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FLC_RPC_8814B) & BIT_MASK_FLC_RPC_8814B)\n#define BIT_SET_FLC_RPC_8814B(x, v)                                            \\\n\t(BIT_CLEAR_FLC_RPC_8814B(x) | BIT_FLC_RPC_8814B(v))\n\n/* 2 REG_FLC_RPCT_8814B (FLC_RPC THRESHOLD) */\n\n#define BIT_SHIFT_FLC_RPCT_8814B 0\n#define BIT_MASK_FLC_RPCT_8814B 0xff\n#define BIT_FLC_RPCT_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_FLC_RPCT_8814B) << BIT_SHIFT_FLC_RPCT_8814B)\n#define BITS_FLC_RPCT_8814B                                                    \\\n\t(BIT_MASK_FLC_RPCT_8814B << BIT_SHIFT_FLC_RPCT_8814B)\n#define BIT_CLEAR_FLC_RPCT_8814B(x) ((x) & (~BITS_FLC_RPCT_8814B))\n#define BIT_GET_FLC_RPCT_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_FLC_RPCT_8814B) & BIT_MASK_FLC_RPCT_8814B)\n#define BIT_SET_FLC_RPCT_8814B(x, v)                                           \\\n\t(BIT_CLEAR_FLC_RPCT_8814B(x) | BIT_FLC_RPCT_8814B(v))\n\n/* 2 REG_FLC_PTS_8814B (PKT TYPE SELECTION OF FLC_RPC T) */\n#define BIT_CMF_8814B BIT(2)\n#define BIT_CCF_8814B BIT(1)\n#define BIT_CDF_8814B BIT(0)\n\n/* 2 REG_FLC_TRPC_8814B (TIMER OF FLC_RPC) */\n#define BIT_FLC_RPCT_V1_8814B BIT(7)\n#define BIT_MODE_8814B BIT(6)\n\n#define BIT_SHIFT_TRPCD_8814B 0\n#define BIT_MASK_TRPCD_8814B 0x3f\n#define BIT_TRPCD_8814B(x)                                                     \\\n\t(((x) & BIT_MASK_TRPCD_8814B) << BIT_SHIFT_TRPCD_8814B)\n#define BITS_TRPCD_8814B (BIT_MASK_TRPCD_8814B << BIT_SHIFT_TRPCD_8814B)\n#define BIT_CLEAR_TRPCD_8814B(x) ((x) & (~BITS_TRPCD_8814B))\n#define BIT_GET_TRPCD_8814B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TRPCD_8814B) & BIT_MASK_TRPCD_8814B)\n#define BIT_SET_TRPCD_8814B(x, v)                                              \\\n\t(BIT_CLEAR_TRPCD_8814B(x) | BIT_TRPCD_8814B(v))\n\n/* 2 REG_RXPKTMON_CTRL_8814B */\n\n#define BIT_SHIFT_RXBKQPKT_SEQ_8814B 20\n#define BIT_MASK_RXBKQPKT_SEQ_8814B 0xf\n#define BIT_RXBKQPKT_SEQ_8814B(x)                                              \\\n\t(((x) & BIT_MASK_RXBKQPKT_SEQ_8814B) << BIT_SHIFT_RXBKQPKT_SEQ_8814B)\n#define BITS_RXBKQPKT_SEQ_8814B                                                \\\n\t(BIT_MASK_RXBKQPKT_SEQ_8814B << BIT_SHIFT_RXBKQPKT_SEQ_8814B)\n#define BIT_CLEAR_RXBKQPKT_SEQ_8814B(x) ((x) & (~BITS_RXBKQPKT_SEQ_8814B))\n#define BIT_GET_RXBKQPKT_SEQ_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8814B) & BIT_MASK_RXBKQPKT_SEQ_8814B)\n#define BIT_SET_RXBKQPKT_SEQ_8814B(x, v)                                       \\\n\t(BIT_CLEAR_RXBKQPKT_SEQ_8814B(x) | BIT_RXBKQPKT_SEQ_8814B(v))\n\n#define BIT_SHIFT_RXBEQPKT_SEQ_8814B 16\n#define BIT_MASK_RXBEQPKT_SEQ_8814B 0xf\n#define BIT_RXBEQPKT_SEQ_8814B(x)                                              \\\n\t(((x) & BIT_MASK_RXBEQPKT_SEQ_8814B) << BIT_SHIFT_RXBEQPKT_SEQ_8814B)\n#define BITS_RXBEQPKT_SEQ_8814B                                                \\\n\t(BIT_MASK_RXBEQPKT_SEQ_8814B << BIT_SHIFT_RXBEQPKT_SEQ_8814B)\n#define BIT_CLEAR_RXBEQPKT_SEQ_8814B(x) ((x) & (~BITS_RXBEQPKT_SEQ_8814B))\n#define BIT_GET_RXBEQPKT_SEQ_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8814B) & BIT_MASK_RXBEQPKT_SEQ_8814B)\n#define BIT_SET_RXBEQPKT_SEQ_8814B(x, v)                                       \\\n\t(BIT_CLEAR_RXBEQPKT_SEQ_8814B(x) | BIT_RXBEQPKT_SEQ_8814B(v))\n\n#define BIT_SHIFT_RXVIQPKT_SEQ_8814B 12\n#define BIT_MASK_RXVIQPKT_SEQ_8814B 0xf\n#define BIT_RXVIQPKT_SEQ_8814B(x)                                              \\\n\t(((x) & BIT_MASK_RXVIQPKT_SEQ_8814B) << BIT_SHIFT_RXVIQPKT_SEQ_8814B)\n#define BITS_RXVIQPKT_SEQ_8814B                                                \\\n\t(BIT_MASK_RXVIQPKT_SEQ_8814B << BIT_SHIFT_RXVIQPKT_SEQ_8814B)\n#define BIT_CLEAR_RXVIQPKT_SEQ_8814B(x) ((x) & (~BITS_RXVIQPKT_SEQ_8814B))\n#define BIT_GET_RXVIQPKT_SEQ_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8814B) & BIT_MASK_RXVIQPKT_SEQ_8814B)\n#define BIT_SET_RXVIQPKT_SEQ_8814B(x, v)                                       \\\n\t(BIT_CLEAR_RXVIQPKT_SEQ_8814B(x) | BIT_RXVIQPKT_SEQ_8814B(v))\n\n#define BIT_SHIFT_RXVOQPKT_SEQ_8814B 8\n#define BIT_MASK_RXVOQPKT_SEQ_8814B 0xf\n#define BIT_RXVOQPKT_SEQ_8814B(x)                                              \\\n\t(((x) & BIT_MASK_RXVOQPKT_SEQ_8814B) << BIT_SHIFT_RXVOQPKT_SEQ_8814B)\n#define BITS_RXVOQPKT_SEQ_8814B                                                \\\n\t(BIT_MASK_RXVOQPKT_SEQ_8814B << BIT_SHIFT_RXVOQPKT_SEQ_8814B)\n#define BIT_CLEAR_RXVOQPKT_SEQ_8814B(x) ((x) & (~BITS_RXVOQPKT_SEQ_8814B))\n#define BIT_GET_RXVOQPKT_SEQ_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8814B) & BIT_MASK_RXVOQPKT_SEQ_8814B)\n#define BIT_SET_RXVOQPKT_SEQ_8814B(x, v)                                       \\\n\t(BIT_CLEAR_RXVOQPKT_SEQ_8814B(x) | BIT_RXVOQPKT_SEQ_8814B(v))\n\n#define BIT_RXBKQPKT_ERR_8814B BIT(7)\n#define BIT_RXBEQPKT_ERR_8814B BIT(6)\n#define BIT_RXVIQPKT_ERR_8814B BIT(5)\n#define BIT_RXVOQPKT_ERR_8814B BIT(4)\n#define BIT_RXDMA_MON_EN_8814B BIT(2)\n#define BIT_RXPKT_MON_RST_8814B BIT(1)\n#define BIT_RXPKT_MON_EN_8814B BIT(0)\n\n/* 2 REG_STATE_MON_8814B */\n\n#define BIT_SHIFT_STATE_SEL_8814B 24\n#define BIT_MASK_STATE_SEL_8814B 0x1f\n#define BIT_STATE_SEL_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_STATE_SEL_8814B) << BIT_SHIFT_STATE_SEL_8814B)\n#define BITS_STATE_SEL_8814B                                                   \\\n\t(BIT_MASK_STATE_SEL_8814B << BIT_SHIFT_STATE_SEL_8814B)\n#define BIT_CLEAR_STATE_SEL_8814B(x) ((x) & (~BITS_STATE_SEL_8814B))\n#define BIT_GET_STATE_SEL_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_STATE_SEL_8814B) & BIT_MASK_STATE_SEL_8814B)\n#define BIT_SET_STATE_SEL_8814B(x, v)                                          \\\n\t(BIT_CLEAR_STATE_SEL_8814B(x) | BIT_STATE_SEL_8814B(v))\n\n#define BIT_SHIFT_STATE_INFO_8814B 8\n#define BIT_MASK_STATE_INFO_8814B 0xff\n#define BIT_STATE_INFO_8814B(x)                                                \\\n\t(((x) & BIT_MASK_STATE_INFO_8814B) << BIT_SHIFT_STATE_INFO_8814B)\n#define BITS_STATE_INFO_8814B                                                  \\\n\t(BIT_MASK_STATE_INFO_8814B << BIT_SHIFT_STATE_INFO_8814B)\n#define BIT_CLEAR_STATE_INFO_8814B(x) ((x) & (~BITS_STATE_INFO_8814B))\n#define BIT_GET_STATE_INFO_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_STATE_INFO_8814B) & BIT_MASK_STATE_INFO_8814B)\n#define BIT_SET_STATE_INFO_8814B(x, v)                                         \\\n\t(BIT_CLEAR_STATE_INFO_8814B(x) | BIT_STATE_INFO_8814B(v))\n\n#define BIT_UPD_NXT_STATE_8814B BIT(7)\n\n#define BIT_SHIFT_CUR_STATE_8814B 0\n#define BIT_MASK_CUR_STATE_8814B 0x7f\n#define BIT_CUR_STATE_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_CUR_STATE_8814B) << BIT_SHIFT_CUR_STATE_8814B)\n#define BITS_CUR_STATE_8814B                                                   \\\n\t(BIT_MASK_CUR_STATE_8814B << BIT_SHIFT_CUR_STATE_8814B)\n#define BIT_CLEAR_CUR_STATE_8814B(x) ((x) & (~BITS_CUR_STATE_8814B))\n#define BIT_GET_CUR_STATE_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_CUR_STATE_8814B) & BIT_MASK_CUR_STATE_8814B)\n#define BIT_SET_CUR_STATE_8814B(x, v)                                          \\\n\t(BIT_CLEAR_CUR_STATE_8814B(x) | BIT_CUR_STATE_8814B(v))\n\n/* 2 REG_ERROR_MON_8814B */\n#define BIT_CSIRPT_LEN_BB_MORE_THAN_MAC_8814B BIT(23)\n#define BIT_CSI_CHKSUM_ERROR_8814B BIT(22)\n#define BIT_MACRX_ERR_5_8814B BIT(21)\n#define BIT_MACRX_ERR_4_8814B BIT(20)\n#define BIT_MACRX_ERR_3_8814B BIT(19)\n#define BIT_MACRX_ERR_2_8814B BIT(18)\n#define BIT_MACRX_ERR_1_8814B BIT(17)\n#define BIT_MACRX_ERR_0_8814B BIT(16)\n#define BIT_WMAC_PRETX_ERRHDL_EN_8814B BIT(15)\n#define BIT_MACTX_ERR_5_8814B BIT(5)\n#define BIT_MACTX_ERR_4_8814B BIT(4)\n#define BIT_MACTX_ERR_3_8814B BIT(3)\n#define BIT_MACTX_ERR_2_8814B BIT(2)\n#define BIT_MACTX_ERR_1_8814B BIT(1)\n#define BIT_MACTX_ERR_0_8814B BIT(0)\n\n/* 2 REG_SEARCH_MACID_8814B */\n#define BIT_EN_TXRPTBUF_CLK_8814B BIT(31)\n#define BIT_WMAC_SRCH_FIFOFULL_8814B BIT(15)\n#define BIT_DIS_INFOSRCH_8814B BIT(14)\n#define BIT_DISABLE_B0_8814B BIT(13)\n\n#define BIT_SHIFT_INFO_ADDR_OFFSET_8814B 0\n#define BIT_MASK_INFO_ADDR_OFFSET_8814B 0x1fff\n#define BIT_INFO_ADDR_OFFSET_8814B(x)                                          \\\n\t(((x) & BIT_MASK_INFO_ADDR_OFFSET_8814B)                               \\\n\t << BIT_SHIFT_INFO_ADDR_OFFSET_8814B)\n#define BITS_INFO_ADDR_OFFSET_8814B                                            \\\n\t(BIT_MASK_INFO_ADDR_OFFSET_8814B << BIT_SHIFT_INFO_ADDR_OFFSET_8814B)\n#define BIT_CLEAR_INFO_ADDR_OFFSET_8814B(x)                                    \\\n\t((x) & (~BITS_INFO_ADDR_OFFSET_8814B))\n#define BIT_GET_INFO_ADDR_OFFSET_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8814B) &                           \\\n\t BIT_MASK_INFO_ADDR_OFFSET_8814B)\n#define BIT_SET_INFO_ADDR_OFFSET_8814B(x, v)                                   \\\n\t(BIT_CLEAR_INFO_ADDR_OFFSET_8814B(x) | BIT_INFO_ADDR_OFFSET_8814B(v))\n\n/* 2 REG_BT_COEX_TABLE_8814B (BT-COEXISTENCE CONTROL REGISTER) */\n\n#define BIT_SHIFT_COEX_TABLE_1_8814B 0\n#define BIT_MASK_COEX_TABLE_1_8814B 0xffffffffL\n#define BIT_COEX_TABLE_1_8814B(x)                                              \\\n\t(((x) & BIT_MASK_COEX_TABLE_1_8814B) << BIT_SHIFT_COEX_TABLE_1_8814B)\n#define BITS_COEX_TABLE_1_8814B                                                \\\n\t(BIT_MASK_COEX_TABLE_1_8814B << BIT_SHIFT_COEX_TABLE_1_8814B)\n#define BIT_CLEAR_COEX_TABLE_1_8814B(x) ((x) & (~BITS_COEX_TABLE_1_8814B))\n#define BIT_GET_COEX_TABLE_1_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_COEX_TABLE_1_8814B) & BIT_MASK_COEX_TABLE_1_8814B)\n#define BIT_SET_COEX_TABLE_1_8814B(x, v)                                       \\\n\t(BIT_CLEAR_COEX_TABLE_1_8814B(x) | BIT_COEX_TABLE_1_8814B(v))\n\n/* 2 REG_BT_COEX_TABLE2_8814B (BT-COEXISTENCE CONTROL REGISTER) */\n\n#define BIT_SHIFT_COEX_TABLE_2_8814B 0\n#define BIT_MASK_COEX_TABLE_2_8814B 0xffffffffL\n#define BIT_COEX_TABLE_2_8814B(x)                                              \\\n\t(((x) & BIT_MASK_COEX_TABLE_2_8814B) << BIT_SHIFT_COEX_TABLE_2_8814B)\n#define BITS_COEX_TABLE_2_8814B                                                \\\n\t(BIT_MASK_COEX_TABLE_2_8814B << BIT_SHIFT_COEX_TABLE_2_8814B)\n#define BIT_CLEAR_COEX_TABLE_2_8814B(x) ((x) & (~BITS_COEX_TABLE_2_8814B))\n#define BIT_GET_COEX_TABLE_2_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_COEX_TABLE_2_8814B) & BIT_MASK_COEX_TABLE_2_8814B)\n#define BIT_SET_COEX_TABLE_2_8814B(x, v)                                       \\\n\t(BIT_CLEAR_COEX_TABLE_2_8814B(x) | BIT_COEX_TABLE_2_8814B(v))\n\n/* 2 REG_BT_COEX_BREAK_TABLE_8814B (BT-COEXISTENCE CONTROL REGISTER) */\n\n#define BIT_SHIFT_BREAK_TABLE_2_8814B 16\n#define BIT_MASK_BREAK_TABLE_2_8814B 0xffff\n#define BIT_BREAK_TABLE_2_8814B(x)                                             \\\n\t(((x) & BIT_MASK_BREAK_TABLE_2_8814B) << BIT_SHIFT_BREAK_TABLE_2_8814B)\n#define BITS_BREAK_TABLE_2_8814B                                               \\\n\t(BIT_MASK_BREAK_TABLE_2_8814B << BIT_SHIFT_BREAK_TABLE_2_8814B)\n#define BIT_CLEAR_BREAK_TABLE_2_8814B(x) ((x) & (~BITS_BREAK_TABLE_2_8814B))\n#define BIT_GET_BREAK_TABLE_2_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_BREAK_TABLE_2_8814B) & BIT_MASK_BREAK_TABLE_2_8814B)\n#define BIT_SET_BREAK_TABLE_2_8814B(x, v)                                      \\\n\t(BIT_CLEAR_BREAK_TABLE_2_8814B(x) | BIT_BREAK_TABLE_2_8814B(v))\n\n#define BIT_SHIFT_BREAK_TABLE_1_8814B 0\n#define BIT_MASK_BREAK_TABLE_1_8814B 0xffff\n#define BIT_BREAK_TABLE_1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_BREAK_TABLE_1_8814B) << BIT_SHIFT_BREAK_TABLE_1_8814B)\n#define BITS_BREAK_TABLE_1_8814B                                               \\\n\t(BIT_MASK_BREAK_TABLE_1_8814B << BIT_SHIFT_BREAK_TABLE_1_8814B)\n#define BIT_CLEAR_BREAK_TABLE_1_8814B(x) ((x) & (~BITS_BREAK_TABLE_1_8814B))\n#define BIT_GET_BREAK_TABLE_1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_BREAK_TABLE_1_8814B) & BIT_MASK_BREAK_TABLE_1_8814B)\n#define BIT_SET_BREAK_TABLE_1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_BREAK_TABLE_1_8814B(x) | BIT_BREAK_TABLE_1_8814B(v))\n\n/* 2 REG_BT_COEX_TABLE_H_8814B (BT-COEXISTENCE CONTROL REGISTER) */\n#define BIT_PRI_MASK_RX_RESP_V1_8814B BIT(30)\n#define BIT_PRI_MASK_RXOFDM_V1_8814B BIT(29)\n#define BIT_PRI_MASK_RXCCK_V1_8814B BIT(28)\n\n#define BIT_SHIFT_PRI_MASK_TXAC_8814B 21\n#define BIT_MASK_PRI_MASK_TXAC_8814B 0x7f\n#define BIT_PRI_MASK_TXAC_8814B(x)                                             \\\n\t(((x) & BIT_MASK_PRI_MASK_TXAC_8814B) << BIT_SHIFT_PRI_MASK_TXAC_8814B)\n#define BITS_PRI_MASK_TXAC_8814B                                               \\\n\t(BIT_MASK_PRI_MASK_TXAC_8814B << BIT_SHIFT_PRI_MASK_TXAC_8814B)\n#define BIT_CLEAR_PRI_MASK_TXAC_8814B(x) ((x) & (~BITS_PRI_MASK_TXAC_8814B))\n#define BIT_GET_PRI_MASK_TXAC_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_TXAC_8814B) & BIT_MASK_PRI_MASK_TXAC_8814B)\n#define BIT_SET_PRI_MASK_TXAC_8814B(x, v)                                      \\\n\t(BIT_CLEAR_PRI_MASK_TXAC_8814B(x) | BIT_PRI_MASK_TXAC_8814B(v))\n\n#define BIT_SHIFT_PRI_MASK_NAV_8814B 13\n#define BIT_MASK_PRI_MASK_NAV_8814B 0xff\n#define BIT_PRI_MASK_NAV_8814B(x)                                              \\\n\t(((x) & BIT_MASK_PRI_MASK_NAV_8814B) << BIT_SHIFT_PRI_MASK_NAV_8814B)\n#define BITS_PRI_MASK_NAV_8814B                                                \\\n\t(BIT_MASK_PRI_MASK_NAV_8814B << BIT_SHIFT_PRI_MASK_NAV_8814B)\n#define BIT_CLEAR_PRI_MASK_NAV_8814B(x) ((x) & (~BITS_PRI_MASK_NAV_8814B))\n#define BIT_GET_PRI_MASK_NAV_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_NAV_8814B) & BIT_MASK_PRI_MASK_NAV_8814B)\n#define BIT_SET_PRI_MASK_NAV_8814B(x, v)                                       \\\n\t(BIT_CLEAR_PRI_MASK_NAV_8814B(x) | BIT_PRI_MASK_NAV_8814B(v))\n\n#define BIT_PRI_MASK_CCK_V1_8814B BIT(12)\n#define BIT_PRI_MASK_OFDM_V1_8814B BIT(11)\n#define BIT_PRI_MASK_RTY_V1_8814B BIT(10)\n\n#define BIT_SHIFT_PRI_MASK_NUM_8814B 6\n#define BIT_MASK_PRI_MASK_NUM_8814B 0xf\n#define BIT_PRI_MASK_NUM_8814B(x)                                              \\\n\t(((x) & BIT_MASK_PRI_MASK_NUM_8814B) << BIT_SHIFT_PRI_MASK_NUM_8814B)\n#define BITS_PRI_MASK_NUM_8814B                                                \\\n\t(BIT_MASK_PRI_MASK_NUM_8814B << BIT_SHIFT_PRI_MASK_NUM_8814B)\n#define BIT_CLEAR_PRI_MASK_NUM_8814B(x) ((x) & (~BITS_PRI_MASK_NUM_8814B))\n#define BIT_GET_PRI_MASK_NUM_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_NUM_8814B) & BIT_MASK_PRI_MASK_NUM_8814B)\n#define BIT_SET_PRI_MASK_NUM_8814B(x, v)                                       \\\n\t(BIT_CLEAR_PRI_MASK_NUM_8814B(x) | BIT_PRI_MASK_NUM_8814B(v))\n\n#define BIT_SHIFT_PRI_MASK_TYPE_8814B 2\n#define BIT_MASK_PRI_MASK_TYPE_8814B 0xf\n#define BIT_PRI_MASK_TYPE_8814B(x)                                             \\\n\t(((x) & BIT_MASK_PRI_MASK_TYPE_8814B) << BIT_SHIFT_PRI_MASK_TYPE_8814B)\n#define BITS_PRI_MASK_TYPE_8814B                                               \\\n\t(BIT_MASK_PRI_MASK_TYPE_8814B << BIT_SHIFT_PRI_MASK_TYPE_8814B)\n#define BIT_CLEAR_PRI_MASK_TYPE_8814B(x) ((x) & (~BITS_PRI_MASK_TYPE_8814B))\n#define BIT_GET_PRI_MASK_TYPE_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_TYPE_8814B) & BIT_MASK_PRI_MASK_TYPE_8814B)\n#define BIT_SET_PRI_MASK_TYPE_8814B(x, v)                                      \\\n\t(BIT_CLEAR_PRI_MASK_TYPE_8814B(x) | BIT_PRI_MASK_TYPE_8814B(v))\n\n#define BIT_OOB_V1_8814B BIT(1)\n#define BIT_ANT_SEL_V1_8814B BIT(0)\n\n/* 2 REG_RXCMD_0_8814B */\n#define BIT_RXCMD_EN_8814B BIT(31)\n\n#define BIT_SHIFT_RXCMD_INFO_8814B 0\n#define BIT_MASK_RXCMD_INFO_8814B 0x7fffffffL\n#define BIT_RXCMD_INFO_8814B(x)                                                \\\n\t(((x) & BIT_MASK_RXCMD_INFO_8814B) << BIT_SHIFT_RXCMD_INFO_8814B)\n#define BITS_RXCMD_INFO_8814B                                                  \\\n\t(BIT_MASK_RXCMD_INFO_8814B << BIT_SHIFT_RXCMD_INFO_8814B)\n#define BIT_CLEAR_RXCMD_INFO_8814B(x) ((x) & (~BITS_RXCMD_INFO_8814B))\n#define BIT_GET_RXCMD_INFO_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXCMD_INFO_8814B) & BIT_MASK_RXCMD_INFO_8814B)\n#define BIT_SET_RXCMD_INFO_8814B(x, v)                                         \\\n\t(BIT_CLEAR_RXCMD_INFO_8814B(x) | BIT_RXCMD_INFO_8814B(v))\n\n/* 2 REG_RXCMD_1_8814B */\n\n#define BIT_SHIFT_CSI_RADDR_LATCH_8814B 24\n#define BIT_MASK_CSI_RADDR_LATCH_8814B 0xff\n#define BIT_CSI_RADDR_LATCH_8814B(x)                                           \\\n\t(((x) & BIT_MASK_CSI_RADDR_LATCH_8814B)                                \\\n\t << BIT_SHIFT_CSI_RADDR_LATCH_8814B)\n#define BITS_CSI_RADDR_LATCH_8814B                                             \\\n\t(BIT_MASK_CSI_RADDR_LATCH_8814B << BIT_SHIFT_CSI_RADDR_LATCH_8814B)\n#define BIT_CLEAR_CSI_RADDR_LATCH_8814B(x) ((x) & (~BITS_CSI_RADDR_LATCH_8814B))\n#define BIT_GET_CSI_RADDR_LATCH_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_CSI_RADDR_LATCH_8814B) &                            \\\n\t BIT_MASK_CSI_RADDR_LATCH_8814B)\n#define BIT_SET_CSI_RADDR_LATCH_8814B(x, v)                                    \\\n\t(BIT_CLEAR_CSI_RADDR_LATCH_8814B(x) | BIT_CSI_RADDR_LATCH_8814B(v))\n\n#define BIT_SHIFT_CSI_WADDR_LATCH_8814B 16\n#define BIT_MASK_CSI_WADDR_LATCH_8814B 0xff\n#define BIT_CSI_WADDR_LATCH_8814B(x)                                           \\\n\t(((x) & BIT_MASK_CSI_WADDR_LATCH_8814B)                                \\\n\t << BIT_SHIFT_CSI_WADDR_LATCH_8814B)\n#define BITS_CSI_WADDR_LATCH_8814B                                             \\\n\t(BIT_MASK_CSI_WADDR_LATCH_8814B << BIT_SHIFT_CSI_WADDR_LATCH_8814B)\n#define BIT_CLEAR_CSI_WADDR_LATCH_8814B(x) ((x) & (~BITS_CSI_WADDR_LATCH_8814B))\n#define BIT_GET_CSI_WADDR_LATCH_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_CSI_WADDR_LATCH_8814B) &                            \\\n\t BIT_MASK_CSI_WADDR_LATCH_8814B)\n#define BIT_SET_CSI_WADDR_LATCH_8814B(x, v)                                    \\\n\t(BIT_CLEAR_CSI_WADDR_LATCH_8814B(x) | BIT_CSI_WADDR_LATCH_8814B(v))\n\n#define BIT_SHIFT_RXCMD_PRD_8814B 0\n#define BIT_MASK_RXCMD_PRD_8814B 0xffff\n#define BIT_RXCMD_PRD_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_RXCMD_PRD_8814B) << BIT_SHIFT_RXCMD_PRD_8814B)\n#define BITS_RXCMD_PRD_8814B                                                   \\\n\t(BIT_MASK_RXCMD_PRD_8814B << BIT_SHIFT_RXCMD_PRD_8814B)\n#define BIT_CLEAR_RXCMD_PRD_8814B(x) ((x) & (~BITS_RXCMD_PRD_8814B))\n#define BIT_GET_RXCMD_PRD_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_RXCMD_PRD_8814B) & BIT_MASK_RXCMD_PRD_8814B)\n#define BIT_SET_RXCMD_PRD_8814B(x, v)                                          \\\n\t(BIT_CLEAR_RXCMD_PRD_8814B(x) | BIT_RXCMD_PRD_8814B(v))\n\n/* 2 REG_WMAC_RESP_TXINFO_8814B (RESPONSE TXINFO REGISTER) */\n\n#define BIT_SHIFT_WMAC_RESP_MFB_8814B 25\n#define BIT_MASK_WMAC_RESP_MFB_8814B 0x7f\n#define BIT_WMAC_RESP_MFB_8814B(x)                                             \\\n\t(((x) & BIT_MASK_WMAC_RESP_MFB_8814B) << BIT_SHIFT_WMAC_RESP_MFB_8814B)\n#define BITS_WMAC_RESP_MFB_8814B                                               \\\n\t(BIT_MASK_WMAC_RESP_MFB_8814B << BIT_SHIFT_WMAC_RESP_MFB_8814B)\n#define BIT_CLEAR_WMAC_RESP_MFB_8814B(x) ((x) & (~BITS_WMAC_RESP_MFB_8814B))\n#define BIT_GET_WMAC_RESP_MFB_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_MFB_8814B) & BIT_MASK_WMAC_RESP_MFB_8814B)\n#define BIT_SET_WMAC_RESP_MFB_8814B(x, v)                                      \\\n\t(BIT_CLEAR_WMAC_RESP_MFB_8814B(x) | BIT_WMAC_RESP_MFB_8814B(v))\n\n#define BIT_SHIFT_WMAC_ANTINF_SEL_8814B 23\n#define BIT_MASK_WMAC_ANTINF_SEL_8814B 0x3\n#define BIT_WMAC_ANTINF_SEL_8814B(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_ANTINF_SEL_8814B)                                \\\n\t << BIT_SHIFT_WMAC_ANTINF_SEL_8814B)\n#define BITS_WMAC_ANTINF_SEL_8814B                                             \\\n\t(BIT_MASK_WMAC_ANTINF_SEL_8814B << BIT_SHIFT_WMAC_ANTINF_SEL_8814B)\n#define BIT_CLEAR_WMAC_ANTINF_SEL_8814B(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8814B))\n#define BIT_GET_WMAC_ANTINF_SEL_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8814B) &                            \\\n\t BIT_MASK_WMAC_ANTINF_SEL_8814B)\n#define BIT_SET_WMAC_ANTINF_SEL_8814B(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_ANTINF_SEL_8814B(x) | BIT_WMAC_ANTINF_SEL_8814B(v))\n\n#define BIT_SHIFT_WMAC_ANTSEL_SEL_8814B 21\n#define BIT_MASK_WMAC_ANTSEL_SEL_8814B 0x3\n#define BIT_WMAC_ANTSEL_SEL_8814B(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_ANTSEL_SEL_8814B)                                \\\n\t << BIT_SHIFT_WMAC_ANTSEL_SEL_8814B)\n#define BITS_WMAC_ANTSEL_SEL_8814B                                             \\\n\t(BIT_MASK_WMAC_ANTSEL_SEL_8814B << BIT_SHIFT_WMAC_ANTSEL_SEL_8814B)\n#define BIT_CLEAR_WMAC_ANTSEL_SEL_8814B(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8814B))\n#define BIT_GET_WMAC_ANTSEL_SEL_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8814B) &                            \\\n\t BIT_MASK_WMAC_ANTSEL_SEL_8814B)\n#define BIT_SET_WMAC_ANTSEL_SEL_8814B(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_ANTSEL_SEL_8814B(x) | BIT_WMAC_ANTSEL_SEL_8814B(v))\n\n#define BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B 18\n#define BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B 0x3\n#define BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x)                             \\\n\t(((x) & BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B)                  \\\n\t << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B)\n#define BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B                               \\\n\t(BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B                          \\\n\t << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B)\n#define BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x)                       \\\n\t((x) & (~BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B))\n#define BIT_GET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x)                         \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B) &              \\\n\t BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B)\n#define BIT_SET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x, v)                      \\\n\t(BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x) |                    \\\n\t BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(v))\n\n#define BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B 6\n#define BIT_MASK_WMAC_RESP_TXANT_V1_8814B 0xfff\n#define BIT_WMAC_RESP_TXANT_V1_8814B(x)                                        \\\n\t(((x) & BIT_MASK_WMAC_RESP_TXANT_V1_8814B)                             \\\n\t << BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B)\n#define BITS_WMAC_RESP_TXANT_V1_8814B                                          \\\n\t(BIT_MASK_WMAC_RESP_TXANT_V1_8814B                                     \\\n\t << BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B)\n#define BIT_CLEAR_WMAC_RESP_TXANT_V1_8814B(x)                                  \\\n\t((x) & (~BITS_WMAC_RESP_TXANT_V1_8814B))\n#define BIT_GET_WMAC_RESP_TXANT_V1_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B) &                         \\\n\t BIT_MASK_WMAC_RESP_TXANT_V1_8814B)\n#define BIT_SET_WMAC_RESP_TXANT_V1_8814B(x, v)                                 \\\n\t(BIT_CLEAR_WMAC_RESP_TXANT_V1_8814B(x) |                               \\\n\t BIT_WMAC_RESP_TXANT_V1_8814B(v))\n\n/* 2 REG_BBPSF_CTRL_8814B */\n#define BIT_CTL_IDLE_CLR_CSI_RPT_8814B BIT(31)\n#define BIT_WMAC_USE_NDPARATE_8814B BIT(30)\n\n#define BIT_SHIFT_WMAC_CSI_RATE_8814B 24\n#define BIT_MASK_WMAC_CSI_RATE_8814B 0x3f\n#define BIT_WMAC_CSI_RATE_8814B(x)                                             \\\n\t(((x) & BIT_MASK_WMAC_CSI_RATE_8814B) << BIT_SHIFT_WMAC_CSI_RATE_8814B)\n#define BITS_WMAC_CSI_RATE_8814B                                               \\\n\t(BIT_MASK_WMAC_CSI_RATE_8814B << BIT_SHIFT_WMAC_CSI_RATE_8814B)\n#define BIT_CLEAR_WMAC_CSI_RATE_8814B(x) ((x) & (~BITS_WMAC_CSI_RATE_8814B))\n#define BIT_GET_WMAC_CSI_RATE_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_WMAC_CSI_RATE_8814B) & BIT_MASK_WMAC_CSI_RATE_8814B)\n#define BIT_SET_WMAC_CSI_RATE_8814B(x, v)                                      \\\n\t(BIT_CLEAR_WMAC_CSI_RATE_8814B(x) | BIT_WMAC_CSI_RATE_8814B(v))\n\n#define BIT_SHIFT_WMAC_RESP_TXRATE_8814B 16\n#define BIT_MASK_WMAC_RESP_TXRATE_8814B 0xff\n#define BIT_WMAC_RESP_TXRATE_8814B(x)                                          \\\n\t(((x) & BIT_MASK_WMAC_RESP_TXRATE_8814B)                               \\\n\t << BIT_SHIFT_WMAC_RESP_TXRATE_8814B)\n#define BITS_WMAC_RESP_TXRATE_8814B                                            \\\n\t(BIT_MASK_WMAC_RESP_TXRATE_8814B << BIT_SHIFT_WMAC_RESP_TXRATE_8814B)\n#define BIT_CLEAR_WMAC_RESP_TXRATE_8814B(x)                                    \\\n\t((x) & (~BITS_WMAC_RESP_TXRATE_8814B))\n#define BIT_GET_WMAC_RESP_TXRATE_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8814B) &                           \\\n\t BIT_MASK_WMAC_RESP_TXRATE_8814B)\n#define BIT_SET_WMAC_RESP_TXRATE_8814B(x, v)                                   \\\n\t(BIT_CLEAR_WMAC_RESP_TXRATE_8814B(x) | BIT_WMAC_RESP_TXRATE_8814B(v))\n\n#define BIT_CSI_FORCE_RATE_EN_8814B BIT(15)\n\n#define BIT_SHIFT_CSI_RSC_8814B 13\n#define BIT_MASK_CSI_RSC_8814B 0x3\n#define BIT_CSI_RSC_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_CSI_RSC_8814B) << BIT_SHIFT_CSI_RSC_8814B)\n#define BITS_CSI_RSC_8814B (BIT_MASK_CSI_RSC_8814B << BIT_SHIFT_CSI_RSC_8814B)\n#define BIT_CLEAR_CSI_RSC_8814B(x) ((x) & (~BITS_CSI_RSC_8814B))\n#define BIT_GET_CSI_RSC_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_CSI_RSC_8814B) & BIT_MASK_CSI_RSC_8814B)\n#define BIT_SET_CSI_RSC_8814B(x, v)                                            \\\n\t(BIT_CLEAR_CSI_RSC_8814B(x) | BIT_CSI_RSC_8814B(v))\n\n#define BIT_CSI_GID_SEL_8814B BIT(12)\n#define BIT_RDCSIMD_FLAG_TRIG_SEL_8814B BIT(11)\n#define BIT_NDPVLD_POS_RST_FFPTR_DIS_V1_8814B BIT(10)\n#define BIT_NDPVLD_PROTECT_RDRDY_DIS_8814B BIT(9)\n#define BIT_RDCSI_EMPTY_APPZERO_8814B BIT(8)\n#define BIT_CSI_RATE_FB_EN_8814B BIT(7)\n#define BIT_RXFIFO_WRPTR_WO_CHKSUM_8814B BIT(6)\n\n/* 2 REG_P2P_RX_BCN_NOA_8814B (P2P RX BEACON NOA REGISTER) */\n#define BIT_NOA_PARSER_EN_8814B BIT(15)\n\n#define BIT_SHIFT_BSSID_SEL_V1_8814B 12\n#define BIT_MASK_BSSID_SEL_V1_8814B 0x7\n#define BIT_BSSID_SEL_V1_8814B(x)                                              \\\n\t(((x) & BIT_MASK_BSSID_SEL_V1_8814B) << BIT_SHIFT_BSSID_SEL_V1_8814B)\n#define BITS_BSSID_SEL_V1_8814B                                                \\\n\t(BIT_MASK_BSSID_SEL_V1_8814B << BIT_SHIFT_BSSID_SEL_V1_8814B)\n#define BIT_CLEAR_BSSID_SEL_V1_8814B(x) ((x) & (~BITS_BSSID_SEL_V1_8814B))\n#define BIT_GET_BSSID_SEL_V1_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BSSID_SEL_V1_8814B) & BIT_MASK_BSSID_SEL_V1_8814B)\n#define BIT_SET_BSSID_SEL_V1_8814B(x, v)                                       \\\n\t(BIT_CLEAR_BSSID_SEL_V1_8814B(x) | BIT_BSSID_SEL_V1_8814B(v))\n\n#define BIT_SHIFT_P2P_OUI_TYPE_8814B 0\n#define BIT_MASK_P2P_OUI_TYPE_8814B 0xff\n#define BIT_P2P_OUI_TYPE_8814B(x)                                              \\\n\t(((x) & BIT_MASK_P2P_OUI_TYPE_8814B) << BIT_SHIFT_P2P_OUI_TYPE_8814B)\n#define BITS_P2P_OUI_TYPE_8814B                                                \\\n\t(BIT_MASK_P2P_OUI_TYPE_8814B << BIT_SHIFT_P2P_OUI_TYPE_8814B)\n#define BIT_CLEAR_P2P_OUI_TYPE_8814B(x) ((x) & (~BITS_P2P_OUI_TYPE_8814B))\n#define BIT_GET_P2P_OUI_TYPE_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_P2P_OUI_TYPE_8814B) & BIT_MASK_P2P_OUI_TYPE_8814B)\n#define BIT_SET_P2P_OUI_TYPE_8814B(x, v)                                       \\\n\t(BIT_CLEAR_P2P_OUI_TYPE_8814B(x) | BIT_P2P_OUI_TYPE_8814B(v))\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_ASSOCIATED_BFMER0_INFO_8814B (ASSOCIATED BEAMFORMER0 INFO REGISTER) */\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B 0xffffffffL\n#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x)                               \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B)                    \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B)\n#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8814B                                 \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B                            \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x)                         \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8814B))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x)                           \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B) &                \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x, v)                        \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x) |                      \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(v))\n\n/* 2 REG_ASSOCIATED_BFMER0_INFO_H_8814B */\n\n#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B 16\n#define BIT_MASK_R_WMAC_TXCSI_AID0_8814B 0x1ff\n#define BIT_R_WMAC_TXCSI_AID0_8814B(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8814B)                              \\\n\t << BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B)\n#define BITS_R_WMAC_TXCSI_AID0_8814B                                           \\\n\t(BIT_MASK_R_WMAC_TXCSI_AID0_8814B << BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B)\n#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8814B(x)                                   \\\n\t((x) & (~BITS_R_WMAC_TXCSI_AID0_8814B))\n#define BIT_GET_R_WMAC_TXCSI_AID0_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B) &                          \\\n\t BIT_MASK_R_WMAC_TXCSI_AID0_8814B)\n#define BIT_SET_R_WMAC_TXCSI_AID0_8814B(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_TXCSI_AID0_8814B(x) | BIT_R_WMAC_TXCSI_AID0_8814B(v))\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B 0xffff\n#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x)                             \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B)                  \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B)\n#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B                               \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B                          \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x)                       \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x)                         \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B) &              \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x, v)                      \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x) |                    \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(v))\n\n/* 2 REG_ASSOCIATED_BFMER1_INFO_8814B (ASSOCIATED BEAMFORMER1 INFO REGISTER) */\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B 0xffffffffL\n#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x)                               \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B)                    \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B)\n#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8814B                                 \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B                            \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x)                         \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8814B))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x)                           \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B) &                \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x, v)                        \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x) |                      \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(v))\n\n/* 2 REG_ASSOCIATED_BFMER1_INFO_H_8814B */\n\n#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B 16\n#define BIT_MASK_R_WMAC_TXCSI_AID1_8814B 0x1ff\n#define BIT_R_WMAC_TXCSI_AID1_8814B(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8814B)                              \\\n\t << BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B)\n#define BITS_R_WMAC_TXCSI_AID1_8814B                                           \\\n\t(BIT_MASK_R_WMAC_TXCSI_AID1_8814B << BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B)\n#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8814B(x)                                   \\\n\t((x) & (~BITS_R_WMAC_TXCSI_AID1_8814B))\n#define BIT_GET_R_WMAC_TXCSI_AID1_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B) &                          \\\n\t BIT_MASK_R_WMAC_TXCSI_AID1_8814B)\n#define BIT_SET_R_WMAC_TXCSI_AID1_8814B(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_TXCSI_AID1_8814B(x) | BIT_R_WMAC_TXCSI_AID1_8814B(v))\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B 0xffff\n#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x)                             \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B)                  \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B)\n#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B                               \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B                          \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x)                       \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x)                         \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B) &              \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x, v)                      \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x) |                    \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(v))\n\n/* 2 REG_TX_CSI_RPT_PARAM_BW20_8814B (TX CSI REPORT PARAMETER REGISTER) */\n\n#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B 16\n#define BIT_MASK_R_WMAC_BFINFO_20M_1_8814B 0xfff\n#define BIT_R_WMAC_BFINFO_20M_1_8814B(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8814B)                            \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B)\n#define BITS_R_WMAC_BFINFO_20M_1_8814B                                         \\\n\t(BIT_MASK_R_WMAC_BFINFO_20M_1_8814B                                    \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B)\n#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8814B(x)                                 \\\n\t((x) & (~BITS_R_WMAC_BFINFO_20M_1_8814B))\n#define BIT_GET_R_WMAC_BFINFO_20M_1_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B) &                        \\\n\t BIT_MASK_R_WMAC_BFINFO_20M_1_8814B)\n#define BIT_SET_R_WMAC_BFINFO_20M_1_8814B(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_BFINFO_20M_1_8814B(x) |                              \\\n\t BIT_R_WMAC_BFINFO_20M_1_8814B(v))\n\n#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B 0\n#define BIT_MASK_R_WMAC_BFINFO_20M_0_8814B 0xfff\n#define BIT_R_WMAC_BFINFO_20M_0_8814B(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8814B)                            \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B)\n#define BITS_R_WMAC_BFINFO_20M_0_8814B                                         \\\n\t(BIT_MASK_R_WMAC_BFINFO_20M_0_8814B                                    \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B)\n#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8814B(x)                                 \\\n\t((x) & (~BITS_R_WMAC_BFINFO_20M_0_8814B))\n#define BIT_GET_R_WMAC_BFINFO_20M_0_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B) &                        \\\n\t BIT_MASK_R_WMAC_BFINFO_20M_0_8814B)\n#define BIT_SET_R_WMAC_BFINFO_20M_0_8814B(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_BFINFO_20M_0_8814B(x) |                              \\\n\t BIT_R_WMAC_BFINFO_20M_0_8814B(v))\n\n/* 2 REG_TX_CSI_RPT_PARAM_BW40_8814B (TX CSI REPORT PARAMETER_BW40 REGISTER) */\n\n#define BIT_SHIFT_WMAC_RESP_ANTD_8814B 12\n#define BIT_MASK_WMAC_RESP_ANTD_8814B 0xf\n#define BIT_WMAC_RESP_ANTD_8814B(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_RESP_ANTD_8814B)                                 \\\n\t << BIT_SHIFT_WMAC_RESP_ANTD_8814B)\n#define BITS_WMAC_RESP_ANTD_8814B                                              \\\n\t(BIT_MASK_WMAC_RESP_ANTD_8814B << BIT_SHIFT_WMAC_RESP_ANTD_8814B)\n#define BIT_CLEAR_WMAC_RESP_ANTD_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTD_8814B))\n#define BIT_GET_WMAC_RESP_ANTD_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_ANTD_8814B) &                             \\\n\t BIT_MASK_WMAC_RESP_ANTD_8814B)\n#define BIT_SET_WMAC_RESP_ANTD_8814B(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_RESP_ANTD_8814B(x) | BIT_WMAC_RESP_ANTD_8814B(v))\n\n#define BIT_SHIFT_WMAC_RESP_ANTC_8814B 8\n#define BIT_MASK_WMAC_RESP_ANTC_8814B 0xf\n#define BIT_WMAC_RESP_ANTC_8814B(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_RESP_ANTC_8814B)                                 \\\n\t << BIT_SHIFT_WMAC_RESP_ANTC_8814B)\n#define BITS_WMAC_RESP_ANTC_8814B                                              \\\n\t(BIT_MASK_WMAC_RESP_ANTC_8814B << BIT_SHIFT_WMAC_RESP_ANTC_8814B)\n#define BIT_CLEAR_WMAC_RESP_ANTC_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTC_8814B))\n#define BIT_GET_WMAC_RESP_ANTC_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_ANTC_8814B) &                             \\\n\t BIT_MASK_WMAC_RESP_ANTC_8814B)\n#define BIT_SET_WMAC_RESP_ANTC_8814B(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_RESP_ANTC_8814B(x) | BIT_WMAC_RESP_ANTC_8814B(v))\n\n#define BIT_SHIFT_WMAC_RESP_ANTB_8814B 4\n#define BIT_MASK_WMAC_RESP_ANTB_8814B 0xf\n#define BIT_WMAC_RESP_ANTB_8814B(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_RESP_ANTB_8814B)                                 \\\n\t << BIT_SHIFT_WMAC_RESP_ANTB_8814B)\n#define BITS_WMAC_RESP_ANTB_8814B                                              \\\n\t(BIT_MASK_WMAC_RESP_ANTB_8814B << BIT_SHIFT_WMAC_RESP_ANTB_8814B)\n#define BIT_CLEAR_WMAC_RESP_ANTB_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTB_8814B))\n#define BIT_GET_WMAC_RESP_ANTB_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_ANTB_8814B) &                             \\\n\t BIT_MASK_WMAC_RESP_ANTB_8814B)\n#define BIT_SET_WMAC_RESP_ANTB_8814B(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_RESP_ANTB_8814B(x) | BIT_WMAC_RESP_ANTB_8814B(v))\n\n#define BIT_SHIFT_WMAC_RESP_ANTA_8814B 0\n#define BIT_MASK_WMAC_RESP_ANTA_8814B 0xf\n#define BIT_WMAC_RESP_ANTA_8814B(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_RESP_ANTA_8814B)                                 \\\n\t << BIT_SHIFT_WMAC_RESP_ANTA_8814B)\n#define BITS_WMAC_RESP_ANTA_8814B                                              \\\n\t(BIT_MASK_WMAC_RESP_ANTA_8814B << BIT_SHIFT_WMAC_RESP_ANTA_8814B)\n#define BIT_CLEAR_WMAC_RESP_ANTA_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTA_8814B))\n#define BIT_GET_WMAC_RESP_ANTA_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_ANTA_8814B) &                             \\\n\t BIT_MASK_WMAC_RESP_ANTA_8814B)\n#define BIT_SET_WMAC_RESP_ANTA_8814B(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_RESP_ANTA_8814B(x) | BIT_WMAC_RESP_ANTA_8814B(v))\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_BCN_PSR_RPT2_8814B (BEACON PARSER REPORT REGISTER2) */\n\n#define BIT_SHIFT_DTIM_CNT2_8814B 24\n#define BIT_MASK_DTIM_CNT2_8814B 0xff\n#define BIT_DTIM_CNT2_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT2_8814B) << BIT_SHIFT_DTIM_CNT2_8814B)\n#define BITS_DTIM_CNT2_8814B                                                   \\\n\t(BIT_MASK_DTIM_CNT2_8814B << BIT_SHIFT_DTIM_CNT2_8814B)\n#define BIT_CLEAR_DTIM_CNT2_8814B(x) ((x) & (~BITS_DTIM_CNT2_8814B))\n#define BIT_GET_DTIM_CNT2_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT2_8814B) & BIT_MASK_DTIM_CNT2_8814B)\n#define BIT_SET_DTIM_CNT2_8814B(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT2_8814B(x) | BIT_DTIM_CNT2_8814B(v))\n\n#define BIT_SHIFT_DTIM_PERIOD2_8814B 16\n#define BIT_MASK_DTIM_PERIOD2_8814B 0xff\n#define BIT_DTIM_PERIOD2_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD2_8814B) << BIT_SHIFT_DTIM_PERIOD2_8814B)\n#define BITS_DTIM_PERIOD2_8814B                                                \\\n\t(BIT_MASK_DTIM_PERIOD2_8814B << BIT_SHIFT_DTIM_PERIOD2_8814B)\n#define BIT_CLEAR_DTIM_PERIOD2_8814B(x) ((x) & (~BITS_DTIM_PERIOD2_8814B))\n#define BIT_GET_DTIM_PERIOD2_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD2_8814B) & BIT_MASK_DTIM_PERIOD2_8814B)\n#define BIT_SET_DTIM_PERIOD2_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD2_8814B(x) | BIT_DTIM_PERIOD2_8814B(v))\n\n#define BIT_DTIM2_8814B BIT(15)\n#define BIT_TIM2_8814B BIT(14)\n#define BIT_RPT_VALID_8814B BIT(13)\n\n#define BIT_SHIFT_PS_AID_2_8814B 0\n#define BIT_MASK_PS_AID_2_8814B 0x7ff\n#define BIT_PS_AID_2_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_2_8814B) << BIT_SHIFT_PS_AID_2_8814B)\n#define BITS_PS_AID_2_8814B                                                    \\\n\t(BIT_MASK_PS_AID_2_8814B << BIT_SHIFT_PS_AID_2_8814B)\n#define BIT_CLEAR_PS_AID_2_8814B(x) ((x) & (~BITS_PS_AID_2_8814B))\n#define BIT_GET_PS_AID_2_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_2_8814B) & BIT_MASK_PS_AID_2_8814B)\n#define BIT_SET_PS_AID_2_8814B(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_2_8814B(x) | BIT_PS_AID_2_8814B(v))\n\n/* 2 REG_BCN_PSR_RPT3_8814B (BEACON PARSER REPORT REGISTER3) */\n\n#define BIT_SHIFT_DTIM_CNT3_8814B 24\n#define BIT_MASK_DTIM_CNT3_8814B 0xff\n#define BIT_DTIM_CNT3_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT3_8814B) << BIT_SHIFT_DTIM_CNT3_8814B)\n#define BITS_DTIM_CNT3_8814B                                                   \\\n\t(BIT_MASK_DTIM_CNT3_8814B << BIT_SHIFT_DTIM_CNT3_8814B)\n#define BIT_CLEAR_DTIM_CNT3_8814B(x) ((x) & (~BITS_DTIM_CNT3_8814B))\n#define BIT_GET_DTIM_CNT3_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT3_8814B) & BIT_MASK_DTIM_CNT3_8814B)\n#define BIT_SET_DTIM_CNT3_8814B(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT3_8814B(x) | BIT_DTIM_CNT3_8814B(v))\n\n#define BIT_SHIFT_DTIM_PERIOD3_8814B 16\n#define BIT_MASK_DTIM_PERIOD3_8814B 0xff\n#define BIT_DTIM_PERIOD3_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD3_8814B) << BIT_SHIFT_DTIM_PERIOD3_8814B)\n#define BITS_DTIM_PERIOD3_8814B                                                \\\n\t(BIT_MASK_DTIM_PERIOD3_8814B << BIT_SHIFT_DTIM_PERIOD3_8814B)\n#define BIT_CLEAR_DTIM_PERIOD3_8814B(x) ((x) & (~BITS_DTIM_PERIOD3_8814B))\n#define BIT_GET_DTIM_PERIOD3_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD3_8814B) & BIT_MASK_DTIM_PERIOD3_8814B)\n#define BIT_SET_DTIM_PERIOD3_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD3_8814B(x) | BIT_DTIM_PERIOD3_8814B(v))\n\n#define BIT_DTIM3_8814B BIT(15)\n#define BIT_TIM3_8814B BIT(14)\n#define BIT_RPT_VALID_8814B BIT(13)\n\n#define BIT_SHIFT_PS_AID_3_8814B 0\n#define BIT_MASK_PS_AID_3_8814B 0x7ff\n#define BIT_PS_AID_3_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_3_8814B) << BIT_SHIFT_PS_AID_3_8814B)\n#define BITS_PS_AID_3_8814B                                                    \\\n\t(BIT_MASK_PS_AID_3_8814B << BIT_SHIFT_PS_AID_3_8814B)\n#define BIT_CLEAR_PS_AID_3_8814B(x) ((x) & (~BITS_PS_AID_3_8814B))\n#define BIT_GET_PS_AID_3_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_3_8814B) & BIT_MASK_PS_AID_3_8814B)\n#define BIT_SET_PS_AID_3_8814B(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_3_8814B(x) | BIT_PS_AID_3_8814B(v))\n\n/* 2 REG_BCN_PSR_RPT4_8814B (BEACON PARSER REPORT REGISTER4) */\n\n#define BIT_SHIFT_DTIM_CNT4_8814B 24\n#define BIT_MASK_DTIM_CNT4_8814B 0xff\n#define BIT_DTIM_CNT4_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT4_8814B) << BIT_SHIFT_DTIM_CNT4_8814B)\n#define BITS_DTIM_CNT4_8814B                                                   \\\n\t(BIT_MASK_DTIM_CNT4_8814B << BIT_SHIFT_DTIM_CNT4_8814B)\n#define BIT_CLEAR_DTIM_CNT4_8814B(x) ((x) & (~BITS_DTIM_CNT4_8814B))\n#define BIT_GET_DTIM_CNT4_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT4_8814B) & BIT_MASK_DTIM_CNT4_8814B)\n#define BIT_SET_DTIM_CNT4_8814B(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT4_8814B(x) | BIT_DTIM_CNT4_8814B(v))\n\n#define BIT_SHIFT_DTIM_PERIOD4_8814B 16\n#define BIT_MASK_DTIM_PERIOD4_8814B 0xff\n#define BIT_DTIM_PERIOD4_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD4_8814B) << BIT_SHIFT_DTIM_PERIOD4_8814B)\n#define BITS_DTIM_PERIOD4_8814B                                                \\\n\t(BIT_MASK_DTIM_PERIOD4_8814B << BIT_SHIFT_DTIM_PERIOD4_8814B)\n#define BIT_CLEAR_DTIM_PERIOD4_8814B(x) ((x) & (~BITS_DTIM_PERIOD4_8814B))\n#define BIT_GET_DTIM_PERIOD4_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD4_8814B) & BIT_MASK_DTIM_PERIOD4_8814B)\n#define BIT_SET_DTIM_PERIOD4_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD4_8814B(x) | BIT_DTIM_PERIOD4_8814B(v))\n\n#define BIT_DTIM4_8814B BIT(15)\n#define BIT_TIM4_8814B BIT(14)\n#define BIT_RPT_VALID_8814B BIT(13)\n\n#define BIT_SHIFT_PS_AID_4_8814B 0\n#define BIT_MASK_PS_AID_4_8814B 0x7ff\n#define BIT_PS_AID_4_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_4_8814B) << BIT_SHIFT_PS_AID_4_8814B)\n#define BITS_PS_AID_4_8814B                                                    \\\n\t(BIT_MASK_PS_AID_4_8814B << BIT_SHIFT_PS_AID_4_8814B)\n#define BIT_CLEAR_PS_AID_4_8814B(x) ((x) & (~BITS_PS_AID_4_8814B))\n#define BIT_GET_PS_AID_4_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_4_8814B) & BIT_MASK_PS_AID_4_8814B)\n#define BIT_SET_PS_AID_4_8814B(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_4_8814B(x) | BIT_PS_AID_4_8814B(v))\n\n/* 2 REG_A1_ADDR_MASK_8814B (A1 ADDR MASK REGISTER) */\n\n#define BIT_SHIFT_A1_ADDR_MASK_8814B 0\n#define BIT_MASK_A1_ADDR_MASK_8814B 0xffffffffL\n#define BIT_A1_ADDR_MASK_8814B(x)                                              \\\n\t(((x) & BIT_MASK_A1_ADDR_MASK_8814B) << BIT_SHIFT_A1_ADDR_MASK_8814B)\n#define BITS_A1_ADDR_MASK_8814B                                                \\\n\t(BIT_MASK_A1_ADDR_MASK_8814B << BIT_SHIFT_A1_ADDR_MASK_8814B)\n#define BIT_CLEAR_A1_ADDR_MASK_8814B(x) ((x) & (~BITS_A1_ADDR_MASK_8814B))\n#define BIT_GET_A1_ADDR_MASK_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_A1_ADDR_MASK_8814B) & BIT_MASK_A1_ADDR_MASK_8814B)\n#define BIT_SET_A1_ADDR_MASK_8814B(x, v)                                       \\\n\t(BIT_CLEAR_A1_ADDR_MASK_8814B(x) | BIT_A1_ADDR_MASK_8814B(v))\n\n/* 2 REG_RXPSF_CTRL_8814B */\n#define BIT_RXGCK_FIFOTHR_EN_8814B BIT(28)\n\n#define BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B 26\n#define BIT_MASK_RXGCK_VHT_FIFOTHR_8814B 0x3\n#define BIT_RXGCK_VHT_FIFOTHR_8814B(x)                                         \\\n\t(((x) & BIT_MASK_RXGCK_VHT_FIFOTHR_8814B)                              \\\n\t << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B)\n#define BITS_RXGCK_VHT_FIFOTHR_8814B                                           \\\n\t(BIT_MASK_RXGCK_VHT_FIFOTHR_8814B << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B)\n#define BIT_CLEAR_RXGCK_VHT_FIFOTHR_8814B(x)                                   \\\n\t((x) & (~BITS_RXGCK_VHT_FIFOTHR_8814B))\n#define BIT_GET_RXGCK_VHT_FIFOTHR_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B) &                          \\\n\t BIT_MASK_RXGCK_VHT_FIFOTHR_8814B)\n#define BIT_SET_RXGCK_VHT_FIFOTHR_8814B(x, v)                                  \\\n\t(BIT_CLEAR_RXGCK_VHT_FIFOTHR_8814B(x) | BIT_RXGCK_VHT_FIFOTHR_8814B(v))\n\n#define BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B 24\n#define BIT_MASK_RXGCK_HT_FIFOTHR_8814B 0x3\n#define BIT_RXGCK_HT_FIFOTHR_8814B(x)                                          \\\n\t(((x) & BIT_MASK_RXGCK_HT_FIFOTHR_8814B)                               \\\n\t << BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B)\n#define BITS_RXGCK_HT_FIFOTHR_8814B                                            \\\n\t(BIT_MASK_RXGCK_HT_FIFOTHR_8814B << BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B)\n#define BIT_CLEAR_RXGCK_HT_FIFOTHR_8814B(x)                                    \\\n\t((x) & (~BITS_RXGCK_HT_FIFOTHR_8814B))\n#define BIT_GET_RXGCK_HT_FIFOTHR_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B) &                           \\\n\t BIT_MASK_RXGCK_HT_FIFOTHR_8814B)\n#define BIT_SET_RXGCK_HT_FIFOTHR_8814B(x, v)                                   \\\n\t(BIT_CLEAR_RXGCK_HT_FIFOTHR_8814B(x) | BIT_RXGCK_HT_FIFOTHR_8814B(v))\n\n#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B 22\n#define BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B 0x3\n#define BIT_RXGCK_OFDM_FIFOTHR_8814B(x)                                        \\\n\t(((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B)                             \\\n\t << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B)\n#define BITS_RXGCK_OFDM_FIFOTHR_8814B                                          \\\n\t(BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B                                     \\\n\t << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B)\n#define BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8814B(x)                                  \\\n\t((x) & (~BITS_RXGCK_OFDM_FIFOTHR_8814B))\n#define BIT_GET_RXGCK_OFDM_FIFOTHR_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B) &                         \\\n\t BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B)\n#define BIT_SET_RXGCK_OFDM_FIFOTHR_8814B(x, v)                                 \\\n\t(BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8814B(x) |                               \\\n\t BIT_RXGCK_OFDM_FIFOTHR_8814B(v))\n\n#define BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B 20\n#define BIT_MASK_RXGCK_CCK_FIFOTHR_8814B 0x3\n#define BIT_RXGCK_CCK_FIFOTHR_8814B(x)                                         \\\n\t(((x) & BIT_MASK_RXGCK_CCK_FIFOTHR_8814B)                              \\\n\t << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B)\n#define BITS_RXGCK_CCK_FIFOTHR_8814B                                           \\\n\t(BIT_MASK_RXGCK_CCK_FIFOTHR_8814B << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B)\n#define BIT_CLEAR_RXGCK_CCK_FIFOTHR_8814B(x)                                   \\\n\t((x) & (~BITS_RXGCK_CCK_FIFOTHR_8814B))\n#define BIT_GET_RXGCK_CCK_FIFOTHR_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B) &                          \\\n\t BIT_MASK_RXGCK_CCK_FIFOTHR_8814B)\n#define BIT_SET_RXGCK_CCK_FIFOTHR_8814B(x, v)                                  \\\n\t(BIT_CLEAR_RXGCK_CCK_FIFOTHR_8814B(x) | BIT_RXGCK_CCK_FIFOTHR_8814B(v))\n\n#define BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B 17\n#define BIT_MASK_RXGCK_ENTRY_DELAY_8814B 0x7\n#define BIT_RXGCK_ENTRY_DELAY_8814B(x)                                         \\\n\t(((x) & BIT_MASK_RXGCK_ENTRY_DELAY_8814B)                              \\\n\t << BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B)\n#define BITS_RXGCK_ENTRY_DELAY_8814B                                           \\\n\t(BIT_MASK_RXGCK_ENTRY_DELAY_8814B << BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B)\n#define BIT_CLEAR_RXGCK_ENTRY_DELAY_8814B(x)                                   \\\n\t((x) & (~BITS_RXGCK_ENTRY_DELAY_8814B))\n#define BIT_GET_RXGCK_ENTRY_DELAY_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B) &                          \\\n\t BIT_MASK_RXGCK_ENTRY_DELAY_8814B)\n#define BIT_SET_RXGCK_ENTRY_DELAY_8814B(x, v)                                  \\\n\t(BIT_CLEAR_RXGCK_ENTRY_DELAY_8814B(x) | BIT_RXGCK_ENTRY_DELAY_8814B(v))\n\n#define BIT_RXGCK_OFDMCCA_EN_8814B BIT(16)\n\n#define BIT_SHIFT_RXPSF_PKTLENTHR_8814B 13\n#define BIT_MASK_RXPSF_PKTLENTHR_8814B 0x7\n#define BIT_RXPSF_PKTLENTHR_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RXPSF_PKTLENTHR_8814B)                                \\\n\t << BIT_SHIFT_RXPSF_PKTLENTHR_8814B)\n#define BITS_RXPSF_PKTLENTHR_8814B                                             \\\n\t(BIT_MASK_RXPSF_PKTLENTHR_8814B << BIT_SHIFT_RXPSF_PKTLENTHR_8814B)\n#define BIT_CLEAR_RXPSF_PKTLENTHR_8814B(x) ((x) & (~BITS_RXPSF_PKTLENTHR_8814B))\n#define BIT_GET_RXPSF_PKTLENTHR_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RXPSF_PKTLENTHR_8814B) &                            \\\n\t BIT_MASK_RXPSF_PKTLENTHR_8814B)\n#define BIT_SET_RXPSF_PKTLENTHR_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RXPSF_PKTLENTHR_8814B(x) | BIT_RXPSF_PKTLENTHR_8814B(v))\n\n#define BIT_RXPSF_CTRLEN_8814B BIT(12)\n#define BIT_RXPSF_VHTCHKEN_8814B BIT(11)\n#define BIT_RXPSF_HTCHKEN_8814B BIT(10)\n#define BIT_RXPSF_OFDMCHKEN_8814B BIT(9)\n#define BIT_RXPSF_CCKCHKEN_8814B BIT(8)\n#define BIT_RXPSF_OFDMRST_8814B BIT(7)\n#define BIT_RXPSF_CCKRST_8814B BIT(6)\n#define BIT_RXPSF_MHCHKEN_8814B BIT(5)\n#define BIT_RXPSF_CONT_ERRCHKEN_8814B BIT(4)\n#define BIT_RXPSF_ALL_ERRCHKEN_8814B BIT(3)\n\n#define BIT_SHIFT_RXPSF_ERRTHR_8814B 0\n#define BIT_MASK_RXPSF_ERRTHR_8814B 0x7\n#define BIT_RXPSF_ERRTHR_8814B(x)                                              \\\n\t(((x) & BIT_MASK_RXPSF_ERRTHR_8814B) << BIT_SHIFT_RXPSF_ERRTHR_8814B)\n#define BITS_RXPSF_ERRTHR_8814B                                                \\\n\t(BIT_MASK_RXPSF_ERRTHR_8814B << BIT_SHIFT_RXPSF_ERRTHR_8814B)\n#define BIT_CLEAR_RXPSF_ERRTHR_8814B(x) ((x) & (~BITS_RXPSF_ERRTHR_8814B))\n#define BIT_GET_RXPSF_ERRTHR_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXPSF_ERRTHR_8814B) & BIT_MASK_RXPSF_ERRTHR_8814B)\n#define BIT_SET_RXPSF_ERRTHR_8814B(x, v)                                       \\\n\t(BIT_CLEAR_RXPSF_ERRTHR_8814B(x) | BIT_RXPSF_ERRTHR_8814B(v))\n\n/* 2 REG_RXPSF_TYPE_CTRL_8814B */\n#define BIT_RXPSF_DATA15EN_8814B BIT(31)\n#define BIT_RXPSF_DATA14EN_8814B BIT(30)\n#define BIT_RXPSF_DATA13EN_8814B BIT(29)\n#define BIT_RXPSF_DATA12EN_8814B BIT(28)\n#define BIT_RXPSF_DATA11EN_8814B BIT(27)\n#define BIT_RXPSF_DATA10EN_8814B BIT(26)\n#define BIT_RXPSF_DATA9EN_8814B BIT(25)\n#define BIT_RXPSF_DATA8EN_8814B BIT(24)\n#define BIT_RXPSF_DATA7EN_8814B BIT(23)\n#define BIT_RXPSF_DATA6EN_8814B BIT(22)\n#define BIT_RXPSF_DATA5EN_8814B BIT(21)\n#define BIT_RXPSF_DATA4EN_8814B BIT(20)\n#define BIT_RXPSF_DATA3EN_8814B BIT(19)\n#define BIT_RXPSF_DATA2EN_8814B BIT(18)\n#define BIT_RXPSF_DATA1EN_8814B BIT(17)\n#define BIT_RXPSF_DATA0EN_8814B BIT(16)\n#define BIT_RXPSF_MGT15EN_8814B BIT(15)\n#define BIT_RXPSF_MGT14EN_8814B BIT(14)\n#define BIT_RXPSF_MGT13EN_8814B BIT(13)\n#define BIT_RXPSF_MGT12EN_8814B BIT(12)\n#define BIT_RXPSF_MGT11EN_8814B BIT(11)\n#define BIT_RXPSF_MGT10EN_8814B BIT(10)\n#define BIT_RXPSF_MGT9EN_8814B BIT(9)\n#define BIT_RXPSF_MGT8EN_8814B BIT(8)\n#define BIT_RXPSF_MGT7EN_8814B BIT(7)\n#define BIT_RXPSF_MGT6EN_8814B BIT(6)\n#define BIT_RXPSF_MGT5EN_8814B BIT(5)\n#define BIT_RXPSF_MGT4EN_8814B BIT(4)\n#define BIT_RXPSF_MGT3EN_8814B BIT(3)\n#define BIT_RXPSF_MGT2EN_8814B BIT(2)\n#define BIT_RXPSF_MGT1EN_8814B BIT(1)\n#define BIT_RXPSF_MGT0EN_8814B BIT(0)\n\n/* 2 REG_CAM_ACCESS_CTRL_8814B */\n#define BIT_INDIRECT_ERR_8814B BIT(6)\n#define BIT_DIRECT_ERR_8814B BIT(5)\n#define BIT_DIR_ACCESS_EN_RX_BA_8814B BIT(4)\n#define BIT_DIR_ACCESS_EN_ADDRCAM_8814B BIT(3)\n#define BIT_DIR_ACCESS_EN_KEY_8814B BIT(2)\n#define BIT_DIR_ACCESS_EN_WOWLAN_8814B BIT(1)\n#define BIT_DIR_ACCESS_EN_FW_FILTER_8814B BIT(0)\n\n/* 2 REG_CUT_AMSDU_CTRL_8814B */\n#define BIT__CUT_AMSDU_CHKLEN_EN_8814B BIT(31)\n#define BIT_EN_CUT_AMSDU_8814B BIT(30)\n\n#define BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B 16\n#define BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B 0xff\n#define BIT_CUT_AMSDU_CHKLEN_L_TH_8814B(x)                                     \\\n\t(((x) & BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B)                          \\\n\t << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B)\n#define BITS_CUT_AMSDU_CHKLEN_L_TH_8814B                                       \\\n\t(BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B                                  \\\n\t << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B)\n#define BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH_8814B(x)                               \\\n\t((x) & (~BITS_CUT_AMSDU_CHKLEN_L_TH_8814B))\n#define BIT_GET_CUT_AMSDU_CHKLEN_L_TH_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B) &                      \\\n\t BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B)\n#define BIT_SET_CUT_AMSDU_CHKLEN_L_TH_8814B(x, v)                              \\\n\t(BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH_8814B(x) |                            \\\n\t BIT_CUT_AMSDU_CHKLEN_L_TH_8814B(v))\n\n#define BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B 0\n#define BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B 0xffff\n#define BIT_CUT_AMSDU_CHKLEN_H_TH_8814B(x)                                     \\\n\t(((x) & BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B)                          \\\n\t << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B)\n#define BITS_CUT_AMSDU_CHKLEN_H_TH_8814B                                       \\\n\t(BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B                                  \\\n\t << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B)\n#define BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH_8814B(x)                               \\\n\t((x) & (~BITS_CUT_AMSDU_CHKLEN_H_TH_8814B))\n#define BIT_GET_CUT_AMSDU_CHKLEN_H_TH_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B) &                      \\\n\t BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B)\n#define BIT_SET_CUT_AMSDU_CHKLEN_H_TH_8814B(x, v)                              \\\n\t(BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH_8814B(x) |                            \\\n\t BIT_CUT_AMSDU_CHKLEN_H_TH_8814B(v))\n\n/* 2 REG_MACID2_8814B (MAC ID2 REGISTER) */\n\n#define BIT_SHIFT_MACID2_V1_8814B 0\n#define BIT_MASK_MACID2_V1_8814B 0xffffffffL\n#define BIT_MACID2_V1_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_MACID2_V1_8814B) << BIT_SHIFT_MACID2_V1_8814B)\n#define BITS_MACID2_V1_8814B                                                   \\\n\t(BIT_MASK_MACID2_V1_8814B << BIT_SHIFT_MACID2_V1_8814B)\n#define BIT_CLEAR_MACID2_V1_8814B(x) ((x) & (~BITS_MACID2_V1_8814B))\n#define BIT_GET_MACID2_V1_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_MACID2_V1_8814B) & BIT_MASK_MACID2_V1_8814B)\n#define BIT_SET_MACID2_V1_8814B(x, v)                                          \\\n\t(BIT_CLEAR_MACID2_V1_8814B(x) | BIT_MACID2_V1_8814B(v))\n\n/* 2 REG_MACID2_H_8814B (MAC ID2 REGISTER) */\n\n#define BIT_SHIFT_MACID2_H_V1_8814B 0\n#define BIT_MASK_MACID2_H_V1_8814B 0xffff\n#define BIT_MACID2_H_V1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_MACID2_H_V1_8814B) << BIT_SHIFT_MACID2_H_V1_8814B)\n#define BITS_MACID2_H_V1_8814B                                                 \\\n\t(BIT_MASK_MACID2_H_V1_8814B << BIT_SHIFT_MACID2_H_V1_8814B)\n#define BIT_CLEAR_MACID2_H_V1_8814B(x) ((x) & (~BITS_MACID2_H_V1_8814B))\n#define BIT_GET_MACID2_H_V1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_MACID2_H_V1_8814B) & BIT_MASK_MACID2_H_V1_8814B)\n#define BIT_SET_MACID2_H_V1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_MACID2_H_V1_8814B(x) | BIT_MACID2_H_V1_8814B(v))\n\n/* 2 REG_BSSID2_8814B (BSSID2 REGISTER) */\n\n#define BIT_SHIFT_BSSID2_V1_8814B 0\n#define BIT_MASK_BSSID2_V1_8814B 0xffffffffL\n#define BIT_BSSID2_V1_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_BSSID2_V1_8814B) << BIT_SHIFT_BSSID2_V1_8814B)\n#define BITS_BSSID2_V1_8814B                                                   \\\n\t(BIT_MASK_BSSID2_V1_8814B << BIT_SHIFT_BSSID2_V1_8814B)\n#define BIT_CLEAR_BSSID2_V1_8814B(x) ((x) & (~BITS_BSSID2_V1_8814B))\n#define BIT_GET_BSSID2_V1_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_BSSID2_V1_8814B) & BIT_MASK_BSSID2_V1_8814B)\n#define BIT_SET_BSSID2_V1_8814B(x, v)                                          \\\n\t(BIT_CLEAR_BSSID2_V1_8814B(x) | BIT_BSSID2_V1_8814B(v))\n\n/* 2 REG_BSSID2_H_8814B (BSSID2 REGISTER) */\n\n#define BIT_SHIFT_BSSID2_H_V1_8814B 0\n#define BIT_MASK_BSSID2_H_V1_8814B 0xffff\n#define BIT_BSSID2_H_V1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_BSSID2_H_V1_8814B) << BIT_SHIFT_BSSID2_H_V1_8814B)\n#define BITS_BSSID2_H_V1_8814B                                                 \\\n\t(BIT_MASK_BSSID2_H_V1_8814B << BIT_SHIFT_BSSID2_H_V1_8814B)\n#define BIT_CLEAR_BSSID2_H_V1_8814B(x) ((x) & (~BITS_BSSID2_H_V1_8814B))\n#define BIT_GET_BSSID2_H_V1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_BSSID2_H_V1_8814B) & BIT_MASK_BSSID2_H_V1_8814B)\n#define BIT_SET_BSSID2_H_V1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_BSSID2_H_V1_8814B(x) | BIT_BSSID2_H_V1_8814B(v))\n\n/* 2 REG_MACID3_8814B (MAC ID3 REGISTER) */\n\n#define BIT_SHIFT_MACID3_V1_8814B 0\n#define BIT_MASK_MACID3_V1_8814B 0xffffffffL\n#define BIT_MACID3_V1_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_MACID3_V1_8814B) << BIT_SHIFT_MACID3_V1_8814B)\n#define BITS_MACID3_V1_8814B                                                   \\\n\t(BIT_MASK_MACID3_V1_8814B << BIT_SHIFT_MACID3_V1_8814B)\n#define BIT_CLEAR_MACID3_V1_8814B(x) ((x) & (~BITS_MACID3_V1_8814B))\n#define BIT_GET_MACID3_V1_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_MACID3_V1_8814B) & BIT_MASK_MACID3_V1_8814B)\n#define BIT_SET_MACID3_V1_8814B(x, v)                                          \\\n\t(BIT_CLEAR_MACID3_V1_8814B(x) | BIT_MACID3_V1_8814B(v))\n\n/* 2 REG_MACID3_H_8814B (MAC ID3 REGISTER) */\n\n#define BIT_SHIFT_MACID3_H_V1_8814B 0\n#define BIT_MASK_MACID3_H_V1_8814B 0xffff\n#define BIT_MACID3_H_V1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_MACID3_H_V1_8814B) << BIT_SHIFT_MACID3_H_V1_8814B)\n#define BITS_MACID3_H_V1_8814B                                                 \\\n\t(BIT_MASK_MACID3_H_V1_8814B << BIT_SHIFT_MACID3_H_V1_8814B)\n#define BIT_CLEAR_MACID3_H_V1_8814B(x) ((x) & (~BITS_MACID3_H_V1_8814B))\n#define BIT_GET_MACID3_H_V1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_MACID3_H_V1_8814B) & BIT_MASK_MACID3_H_V1_8814B)\n#define BIT_SET_MACID3_H_V1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_MACID3_H_V1_8814B(x) | BIT_MACID3_H_V1_8814B(v))\n\n/* 2 REG_BSSID3_8814B (BSSID3 REGISTER) */\n\n#define BIT_SHIFT_BSSID3_V1_8814B 0\n#define BIT_MASK_BSSID3_V1_8814B 0xffffffffL\n#define BIT_BSSID3_V1_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_BSSID3_V1_8814B) << BIT_SHIFT_BSSID3_V1_8814B)\n#define BITS_BSSID3_V1_8814B                                                   \\\n\t(BIT_MASK_BSSID3_V1_8814B << BIT_SHIFT_BSSID3_V1_8814B)\n#define BIT_CLEAR_BSSID3_V1_8814B(x) ((x) & (~BITS_BSSID3_V1_8814B))\n#define BIT_GET_BSSID3_V1_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_BSSID3_V1_8814B) & BIT_MASK_BSSID3_V1_8814B)\n#define BIT_SET_BSSID3_V1_8814B(x, v)                                          \\\n\t(BIT_CLEAR_BSSID3_V1_8814B(x) | BIT_BSSID3_V1_8814B(v))\n\n/* 2 REG_BSSID3_H_8814B (BSSID3 REGISTER) */\n\n#define BIT_SHIFT_BSSID3_H_V1_8814B 0\n#define BIT_MASK_BSSID3_H_V1_8814B 0xffff\n#define BIT_BSSID3_H_V1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_BSSID3_H_V1_8814B) << BIT_SHIFT_BSSID3_H_V1_8814B)\n#define BITS_BSSID3_H_V1_8814B                                                 \\\n\t(BIT_MASK_BSSID3_H_V1_8814B << BIT_SHIFT_BSSID3_H_V1_8814B)\n#define BIT_CLEAR_BSSID3_H_V1_8814B(x) ((x) & (~BITS_BSSID3_H_V1_8814B))\n#define BIT_GET_BSSID3_H_V1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_BSSID3_H_V1_8814B) & BIT_MASK_BSSID3_H_V1_8814B)\n#define BIT_SET_BSSID3_H_V1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_BSSID3_H_V1_8814B(x) | BIT_BSSID3_H_V1_8814B(v))\n\n/* 2 REG_MACID4_8814B (MAC ID4 REGISTER) */\n\n#define BIT_SHIFT_MACID4_V1_8814B 0\n#define BIT_MASK_MACID4_V1_8814B 0xffffffffL\n#define BIT_MACID4_V1_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_MACID4_V1_8814B) << BIT_SHIFT_MACID4_V1_8814B)\n#define BITS_MACID4_V1_8814B                                                   \\\n\t(BIT_MASK_MACID4_V1_8814B << BIT_SHIFT_MACID4_V1_8814B)\n#define BIT_CLEAR_MACID4_V1_8814B(x) ((x) & (~BITS_MACID4_V1_8814B))\n#define BIT_GET_MACID4_V1_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_MACID4_V1_8814B) & BIT_MASK_MACID4_V1_8814B)\n#define BIT_SET_MACID4_V1_8814B(x, v)                                          \\\n\t(BIT_CLEAR_MACID4_V1_8814B(x) | BIT_MACID4_V1_8814B(v))\n\n/* 2 REG_MACID4_H_8814B (MAC ID4 REGISTER) */\n\n#define BIT_SHIFT_MACID4_H_V1_8814B 0\n#define BIT_MASK_MACID4_H_V1_8814B 0xffff\n#define BIT_MACID4_H_V1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_MACID4_H_V1_8814B) << BIT_SHIFT_MACID4_H_V1_8814B)\n#define BITS_MACID4_H_V1_8814B                                                 \\\n\t(BIT_MASK_MACID4_H_V1_8814B << BIT_SHIFT_MACID4_H_V1_8814B)\n#define BIT_CLEAR_MACID4_H_V1_8814B(x) ((x) & (~BITS_MACID4_H_V1_8814B))\n#define BIT_GET_MACID4_H_V1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_MACID4_H_V1_8814B) & BIT_MASK_MACID4_H_V1_8814B)\n#define BIT_SET_MACID4_H_V1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_MACID4_H_V1_8814B(x) | BIT_MACID4_H_V1_8814B(v))\n\n/* 2 REG_BSSID4_8814B (BSSID4 REGISTER) */\n\n#define BIT_SHIFT_BSSID4_V1_8814B 0\n#define BIT_MASK_BSSID4_V1_8814B 0xffffffffL\n#define BIT_BSSID4_V1_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_BSSID4_V1_8814B) << BIT_SHIFT_BSSID4_V1_8814B)\n#define BITS_BSSID4_V1_8814B                                                   \\\n\t(BIT_MASK_BSSID4_V1_8814B << BIT_SHIFT_BSSID4_V1_8814B)\n#define BIT_CLEAR_BSSID4_V1_8814B(x) ((x) & (~BITS_BSSID4_V1_8814B))\n#define BIT_GET_BSSID4_V1_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_BSSID4_V1_8814B) & BIT_MASK_BSSID4_V1_8814B)\n#define BIT_SET_BSSID4_V1_8814B(x, v)                                          \\\n\t(BIT_CLEAR_BSSID4_V1_8814B(x) | BIT_BSSID4_V1_8814B(v))\n\n/* 2 REG_BSSID4_H_8814B (BSSID4 REGISTER) */\n\n#define BIT_SHIFT_BSSID4_H_V1_8814B 0\n#define BIT_MASK_BSSID4_H_V1_8814B 0xffff\n#define BIT_BSSID4_H_V1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_BSSID4_H_V1_8814B) << BIT_SHIFT_BSSID4_H_V1_8814B)\n#define BITS_BSSID4_H_V1_8814B                                                 \\\n\t(BIT_MASK_BSSID4_H_V1_8814B << BIT_SHIFT_BSSID4_H_V1_8814B)\n#define BIT_CLEAR_BSSID4_H_V1_8814B(x) ((x) & (~BITS_BSSID4_H_V1_8814B))\n#define BIT_GET_BSSID4_H_V1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_BSSID4_H_V1_8814B) & BIT_MASK_BSSID4_H_V1_8814B)\n#define BIT_SET_BSSID4_H_V1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_BSSID4_H_V1_8814B(x) | BIT_BSSID4_H_V1_8814B(v))\n\n/* 2 REG_NOA_REPORT_8814B */\n\n#define BIT_SHIFT_NOA_RPT_8814B 0\n#define BIT_MASK_NOA_RPT_8814B 0xffffffffL\n#define BIT_NOA_RPT_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_NOA_RPT_8814B) << BIT_SHIFT_NOA_RPT_8814B)\n#define BITS_NOA_RPT_8814B (BIT_MASK_NOA_RPT_8814B << BIT_SHIFT_NOA_RPT_8814B)\n#define BIT_CLEAR_NOA_RPT_8814B(x) ((x) & (~BITS_NOA_RPT_8814B))\n#define BIT_GET_NOA_RPT_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_NOA_RPT_8814B) & BIT_MASK_NOA_RPT_8814B)\n#define BIT_SET_NOA_RPT_8814B(x, v)                                            \\\n\t(BIT_CLEAR_NOA_RPT_8814B(x) | BIT_NOA_RPT_8814B(v))\n\n/* 2 REG_NOA_REPORT_1_8814B */\n\n#define BIT_SHIFT_NOA_RPT_1_8814B 0\n#define BIT_MASK_NOA_RPT_1_8814B 0xffffffffL\n#define BIT_NOA_RPT_1_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_NOA_RPT_1_8814B) << BIT_SHIFT_NOA_RPT_1_8814B)\n#define BITS_NOA_RPT_1_8814B                                                   \\\n\t(BIT_MASK_NOA_RPT_1_8814B << BIT_SHIFT_NOA_RPT_1_8814B)\n#define BIT_CLEAR_NOA_RPT_1_8814B(x) ((x) & (~BITS_NOA_RPT_1_8814B))\n#define BIT_GET_NOA_RPT_1_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_NOA_RPT_1_8814B) & BIT_MASK_NOA_RPT_1_8814B)\n#define BIT_SET_NOA_RPT_1_8814B(x, v)                                          \\\n\t(BIT_CLEAR_NOA_RPT_1_8814B(x) | BIT_NOA_RPT_1_8814B(v))\n\n/* 2 REG_NOA_REPORT_2_8814B */\n\n#define BIT_SHIFT_NOA_RPT_2_8814B 0\n#define BIT_MASK_NOA_RPT_2_8814B 0xffffffffL\n#define BIT_NOA_RPT_2_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_NOA_RPT_2_8814B) << BIT_SHIFT_NOA_RPT_2_8814B)\n#define BITS_NOA_RPT_2_8814B                                                   \\\n\t(BIT_MASK_NOA_RPT_2_8814B << BIT_SHIFT_NOA_RPT_2_8814B)\n#define BIT_CLEAR_NOA_RPT_2_8814B(x) ((x) & (~BITS_NOA_RPT_2_8814B))\n#define BIT_GET_NOA_RPT_2_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_NOA_RPT_2_8814B) & BIT_MASK_NOA_RPT_2_8814B)\n#define BIT_SET_NOA_RPT_2_8814B(x, v)                                          \\\n\t(BIT_CLEAR_NOA_RPT_2_8814B(x) | BIT_NOA_RPT_2_8814B(v))\n\n/* 2 REG_NOA_REPORT_3_8814B */\n\n#define BIT_SHIFT_NOA_RPT_3_8814B 0\n#define BIT_MASK_NOA_RPT_3_8814B 0xff\n#define BIT_NOA_RPT_3_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_NOA_RPT_3_8814B) << BIT_SHIFT_NOA_RPT_3_8814B)\n#define BITS_NOA_RPT_3_8814B                                                   \\\n\t(BIT_MASK_NOA_RPT_3_8814B << BIT_SHIFT_NOA_RPT_3_8814B)\n#define BIT_CLEAR_NOA_RPT_3_8814B(x) ((x) & (~BITS_NOA_RPT_3_8814B))\n#define BIT_GET_NOA_RPT_3_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_NOA_RPT_3_8814B) & BIT_MASK_NOA_RPT_3_8814B)\n#define BIT_SET_NOA_RPT_3_8814B(x, v)                                          \\\n\t(BIT_CLEAR_NOA_RPT_3_8814B(x) | BIT_NOA_RPT_3_8814B(v))\n\n/* 2 REG_PWRBIT_SETTING_8814B */\n#define BIT_CLI3_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(15)\n#define BIT_CLI3_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(14)\n#define BIT_CLI3_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(13)\n#define BIT_CLI3_PWR_ST_V1_8814B BIT(12)\n#define BIT_CLI2_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(11)\n#define BIT_CLI2_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(10)\n#define BIT_CLI2_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(9)\n#define BIT_CLI2_PWR_ST_V1_8814B BIT(8)\n#define BIT_CLI1_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(7)\n#define BIT_CLI1_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(6)\n#define BIT_CLI1_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(5)\n#define BIT_CLI1_PWR_ST_V1_8814B BIT(4)\n#define BIT_CLI0_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(3)\n#define BIT_CLI0_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(2)\n#define BIT_CLI0_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(1)\n#define BIT_CLI0_PWR_ST_V1_8814B BIT(0)\n\n/* 2 REG_GENERAL_OPTION_8814B */\n#define BIT_FIX_MSDU_TAIL_WR_8814B BIT(12)\n#define BIT_FIX_MSDU_SHIFT_8814B BIT(11)\n#define BIT_RXFIFO_GNT_CUT_8814B BIT(8)\n#define BIT_WMAC_FIX_FIRST_MPDU_WITH_PHYSTS_8814B BIT(5)\n#define BIT_DUMMY_RXD_FCS_ERROR_MASK_EN_8814B BIT(4)\n#define BIT_PATTERN_MATCH_FIX_EN_8814B BIT(3)\n#define BIT_TXSERV_FIELD_SEL_8814B BIT(2)\n#define BIT_RXVHT_LEN_SEL_8814B BIT(1)\n#define BIT_RXMIC_PROTECT_EN_8814B BIT(0)\n\n/* 2 REG_FWPHYFF_RCR_8814B */\n#define BIT_RCR2_AAMSDU_8814B BIT(25)\n#define BIT_RCR2_CBSSID_BCN_8814B BIT(24)\n#define BIT_RCR2_ACRC32_8814B BIT(23)\n#define BIT_RCR2_TA_BCN_8814B BIT(22)\n#define BIT_RCR2_CBSSID_DATA_8814B BIT(21)\n#define BIT_RCR2_ADD3_8814B BIT(20)\n#define BIT_RCR2_AB_8814B BIT(19)\n#define BIT_RCR2_AM_8814B BIT(18)\n#define BIT_RCR2_APM_8814B BIT(17)\n#define BIT_RCR2_AAP_8814B BIT(16)\n#define BIT_RCR1_AAMSDU_8814B BIT(9)\n#define BIT_RCR1_CBSSID_BCN_8814B BIT(8)\n#define BIT_RCR1_ACRC32_8814B BIT(7)\n#define BIT_RCR1_TA_BCN_8814B BIT(6)\n#define BIT_RCR1_CBSSID_DATA_8814B BIT(5)\n#define BIT_RCR1_ADD3_8814B BIT(4)\n#define BIT_RCR1_AB_8814B BIT(3)\n#define BIT_RCR1_AM_8814B BIT(2)\n#define BIT_RCR1_APM_8814B BIT(1)\n#define BIT_RCR1_AAP_8814B BIT(0)\n\n/* 2 REG_ADDRCAM_WRITE_CONTENT_8814B */\n\n#define BIT_SHIFT_ADDRCAM_WDATA_8814B 0\n#define BIT_MASK_ADDRCAM_WDATA_8814B 0xffffffffL\n#define BIT_ADDRCAM_WDATA_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ADDRCAM_WDATA_8814B) << BIT_SHIFT_ADDRCAM_WDATA_8814B)\n#define BITS_ADDRCAM_WDATA_8814B                                               \\\n\t(BIT_MASK_ADDRCAM_WDATA_8814B << BIT_SHIFT_ADDRCAM_WDATA_8814B)\n#define BIT_CLEAR_ADDRCAM_WDATA_8814B(x) ((x) & (~BITS_ADDRCAM_WDATA_8814B))\n#define BIT_GET_ADDRCAM_WDATA_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ADDRCAM_WDATA_8814B) & BIT_MASK_ADDRCAM_WDATA_8814B)\n#define BIT_SET_ADDRCAM_WDATA_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ADDRCAM_WDATA_8814B(x) | BIT_ADDRCAM_WDATA_8814B(v))\n\n/* 2 REG_ADDRCAM_READ_CONTENT_8814B */\n\n#define BIT_SHIFT_ADDRCAM_RDATA_8814B 0\n#define BIT_MASK_ADDRCAM_RDATA_8814B 0xffffffffL\n#define BIT_ADDRCAM_RDATA_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ADDRCAM_RDATA_8814B) << BIT_SHIFT_ADDRCAM_RDATA_8814B)\n#define BITS_ADDRCAM_RDATA_8814B                                               \\\n\t(BIT_MASK_ADDRCAM_RDATA_8814B << BIT_SHIFT_ADDRCAM_RDATA_8814B)\n#define BIT_CLEAR_ADDRCAM_RDATA_8814B(x) ((x) & (~BITS_ADDRCAM_RDATA_8814B))\n#define BIT_GET_ADDRCAM_RDATA_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ADDRCAM_RDATA_8814B) & BIT_MASK_ADDRCAM_RDATA_8814B)\n#define BIT_SET_ADDRCAM_RDATA_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ADDRCAM_RDATA_8814B(x) | BIT_ADDRCAM_RDATA_8814B(v))\n\n/* 2 REG_ADDRCAM_CFG_8814B */\n#define BIT_ADDRCAM_POLL_8814B BIT(31)\n#define BIT__ADDRCAM_WT_EN_8814B BIT(30)\n#define BIT_CLRADDRCAM_8814B BIT(29)\n\n#define BIT_SHIFT__ADDRCAM_ADDR_8814B 8\n#define BIT_MASK__ADDRCAM_ADDR_8814B 0x3ff\n#define BIT__ADDRCAM_ADDR_8814B(x)                                             \\\n\t(((x) & BIT_MASK__ADDRCAM_ADDR_8814B) << BIT_SHIFT__ADDRCAM_ADDR_8814B)\n#define BITS__ADDRCAM_ADDR_8814B                                               \\\n\t(BIT_MASK__ADDRCAM_ADDR_8814B << BIT_SHIFT__ADDRCAM_ADDR_8814B)\n#define BIT_CLEAR__ADDRCAM_ADDR_8814B(x) ((x) & (~BITS__ADDRCAM_ADDR_8814B))\n#define BIT_GET__ADDRCAM_ADDR_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT__ADDRCAM_ADDR_8814B) & BIT_MASK__ADDRCAM_ADDR_8814B)\n#define BIT_SET__ADDRCAM_ADDR_8814B(x, v)                                      \\\n\t(BIT_CLEAR__ADDRCAM_ADDR_8814B(x) | BIT__ADDRCAM_ADDR_8814B(v))\n\n#define BIT_SHIFT_ADDRCAM_RANGE_8814B 0\n#define BIT_MASK_ADDRCAM_RANGE_8814B 0x7f\n#define BIT_ADDRCAM_RANGE_8814B(x)                                             \\\n\t(((x) & BIT_MASK_ADDRCAM_RANGE_8814B) << BIT_SHIFT_ADDRCAM_RANGE_8814B)\n#define BITS_ADDRCAM_RANGE_8814B                                               \\\n\t(BIT_MASK_ADDRCAM_RANGE_8814B << BIT_SHIFT_ADDRCAM_RANGE_8814B)\n#define BIT_CLEAR_ADDRCAM_RANGE_8814B(x) ((x) & (~BITS_ADDRCAM_RANGE_8814B))\n#define BIT_GET_ADDRCAM_RANGE_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ADDRCAM_RANGE_8814B) & BIT_MASK_ADDRCAM_RANGE_8814B)\n#define BIT_SET_ADDRCAM_RANGE_8814B(x, v)                                      \\\n\t(BIT_CLEAR_ADDRCAM_RANGE_8814B(x) | BIT_ADDRCAM_RANGE_8814B(v))\n\n/* 2 REG_CSI_RRSR_8814B */\n#define BIT_CSI_LDPC_EN_8814B BIT(29)\n#define BIT_CSI_STBC_EN_8814B BIT(28)\n\n#define BIT_SHIFT_CSI_RRSC_BITMAP_8814B 4\n#define BIT_MASK_CSI_RRSC_BITMAP_8814B 0xffffff\n#define BIT_CSI_RRSC_BITMAP_8814B(x)                                           \\\n\t(((x) & BIT_MASK_CSI_RRSC_BITMAP_8814B)                                \\\n\t << BIT_SHIFT_CSI_RRSC_BITMAP_8814B)\n#define BITS_CSI_RRSC_BITMAP_8814B                                             \\\n\t(BIT_MASK_CSI_RRSC_BITMAP_8814B << BIT_SHIFT_CSI_RRSC_BITMAP_8814B)\n#define BIT_CLEAR_CSI_RRSC_BITMAP_8814B(x) ((x) & (~BITS_CSI_RRSC_BITMAP_8814B))\n#define BIT_GET_CSI_RRSC_BITMAP_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_CSI_RRSC_BITMAP_8814B) &                            \\\n\t BIT_MASK_CSI_RRSC_BITMAP_8814B)\n#define BIT_SET_CSI_RRSC_BITMAP_8814B(x, v)                                    \\\n\t(BIT_CLEAR_CSI_RRSC_BITMAP_8814B(x) | BIT_CSI_RRSC_BITMAP_8814B(v))\n\n#define BIT_SHIFT_OFDM_LEN_TH_8814B 0\n#define BIT_MASK_OFDM_LEN_TH_8814B 0xf\n#define BIT_OFDM_LEN_TH_8814B(x)                                               \\\n\t(((x) & BIT_MASK_OFDM_LEN_TH_8814B) << BIT_SHIFT_OFDM_LEN_TH_8814B)\n#define BITS_OFDM_LEN_TH_8814B                                                 \\\n\t(BIT_MASK_OFDM_LEN_TH_8814B << BIT_SHIFT_OFDM_LEN_TH_8814B)\n#define BIT_CLEAR_OFDM_LEN_TH_8814B(x) ((x) & (~BITS_OFDM_LEN_TH_8814B))\n#define BIT_GET_OFDM_LEN_TH_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_OFDM_LEN_TH_8814B) & BIT_MASK_OFDM_LEN_TH_8814B)\n#define BIT_SET_OFDM_LEN_TH_8814B(x, v)                                        \\\n\t(BIT_CLEAR_OFDM_LEN_TH_8814B(x) | BIT_OFDM_LEN_TH_8814B(v))\n\n/* 2 REG_MU_BF_OPTION_8814B */\n#define BIT_WMAC_RESP_NONSTA1_DIS_8814B BIT(7)\n#define BIT_WMAC_TXMU_ACKPOLICY_EN_8814B BIT(6)\n\n#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B 4\n#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B 0x3\n#define BIT_WMAC_TXMU_ACKPOLICY_8814B(x)                                       \\\n\t(((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B)                            \\\n\t << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B)\n#define BITS_WMAC_TXMU_ACKPOLICY_8814B                                         \\\n\t(BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B                                    \\\n\t << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B)\n#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8814B(x)                                 \\\n\t((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8814B))\n#define BIT_GET_WMAC_TXMU_ACKPOLICY_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B) &                        \\\n\t BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B)\n#define BIT_SET_WMAC_TXMU_ACKPOLICY_8814B(x, v)                                \\\n\t(BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8814B(x) |                              \\\n\t BIT_WMAC_TXMU_ACKPOLICY_8814B(v))\n\n#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B 1\n#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B 0x7\n#define BIT_WMAC_MU_BFEE_PORT_SEL_8814B(x)                                     \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B)                          \\\n\t << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B)\n#define BITS_WMAC_MU_BFEE_PORT_SEL_8814B                                       \\\n\t(BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B                                  \\\n\t << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B)\n#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8814B(x)                               \\\n\t((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8814B))\n#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B) &                      \\\n\t BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B)\n#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8814B(x, v)                              \\\n\t(BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8814B(x) |                            \\\n\t BIT_WMAC_MU_BFEE_PORT_SEL_8814B(v))\n\n#define BIT_WMAC_MU_BFEE_DIS_8814B BIT(0)\n\n/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8814B */\n\n#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B 0\n#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B 0xff\n#define BIT_WMAC_PAUSE_BB_CLR_TH_8814B(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B)                           \\\n\t << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B)\n#define BITS_WMAC_PAUSE_BB_CLR_TH_8814B                                        \\\n\t(BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B                                   \\\n\t << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B)\n#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8814B(x)                                \\\n\t((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8814B))\n#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B) &                       \\\n\t BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B)\n#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8814B(x, v)                               \\\n\t(BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8814B(x) |                             \\\n\t BIT_WMAC_PAUSE_BB_CLR_TH_8814B(v))\n\n/* 2 REG_WMAC_MULBK_BUF_8814B */\n\n#define BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B 0\n#define BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B 0xff\n#define BIT_WMAC_MULBK_PAGE_SIZE_8814B(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B)                           \\\n\t << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B)\n#define BITS_WMAC_MULBK_PAGE_SIZE_8814B                                        \\\n\t(BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B                                   \\\n\t << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B)\n#define BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8814B(x)                                \\\n\t((x) & (~BITS_WMAC_MULBK_PAGE_SIZE_8814B))\n#define BIT_GET_WMAC_MULBK_PAGE_SIZE_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B) &                       \\\n\t BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B)\n#define BIT_SET_WMAC_MULBK_PAGE_SIZE_8814B(x, v)                               \\\n\t(BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8814B(x) |                             \\\n\t BIT_WMAC_MULBK_PAGE_SIZE_8814B(v))\n\n/* 2 REG_WMAC_MU_OPTION_8814B */\n#define BIT_NOCHK_BFPOLL_BMP_8814B BIT(7)\n\n/* 2 REG_WMAC_MU_BF_CTL_8814B */\n#define BIT_WMAC_INVLD_BFPRT_CHK_8814B BIT(15)\n#define BIT_WMAC_RETXBFRPTSEQ_UPD_8814B BIT(14)\n\n#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B 12\n#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B 0x3\n#define BIT_WMAC_MU_BFRPTSEG_SEL_8814B(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B)                           \\\n\t << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B)\n#define BITS_WMAC_MU_BFRPTSEG_SEL_8814B                                        \\\n\t(BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B                                   \\\n\t << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B)\n#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8814B(x)                                \\\n\t((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8814B))\n#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B) &                       \\\n\t BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B)\n#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8814B(x, v)                               \\\n\t(BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8814B(x) |                             \\\n\t BIT_WMAC_MU_BFRPTSEG_SEL_8814B(v))\n\n#define BIT_SHIFT_WMAC_MU_BF_MYAID_8814B 0\n#define BIT_MASK_WMAC_MU_BF_MYAID_8814B 0xfff\n#define BIT_WMAC_MU_BF_MYAID_8814B(x)                                          \\\n\t(((x) & BIT_MASK_WMAC_MU_BF_MYAID_8814B)                               \\\n\t << BIT_SHIFT_WMAC_MU_BF_MYAID_8814B)\n#define BITS_WMAC_MU_BF_MYAID_8814B                                            \\\n\t(BIT_MASK_WMAC_MU_BF_MYAID_8814B << BIT_SHIFT_WMAC_MU_BF_MYAID_8814B)\n#define BIT_CLEAR_WMAC_MU_BF_MYAID_8814B(x)                                    \\\n\t((x) & (~BITS_WMAC_MU_BF_MYAID_8814B))\n#define BIT_GET_WMAC_MU_BF_MYAID_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8814B) &                           \\\n\t BIT_MASK_WMAC_MU_BF_MYAID_8814B)\n#define BIT_SET_WMAC_MU_BF_MYAID_8814B(x, v)                                   \\\n\t(BIT_CLEAR_WMAC_MU_BF_MYAID_8814B(x) | BIT_WMAC_MU_BF_MYAID_8814B(v))\n\n/* 2 REG_WMAC_MU_BFRPT_PARA_8814B */\n\n#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B 13\n#define BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B 0x7\n#define BIT_BFRPT_PARA_USERID_SEL_V1_8814B(x)                                  \\\n\t(((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B)                       \\\n\t << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B)\n#define BITS_BFRPT_PARA_USERID_SEL_V1_8814B                                    \\\n\t(BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B                               \\\n\t << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B)\n#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8814B(x)                            \\\n\t((x) & (~BITS_BFRPT_PARA_USERID_SEL_V1_8814B))\n#define BIT_GET_BFRPT_PARA_USERID_SEL_V1_8814B(x)                              \\\n\t(((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B) &                   \\\n\t BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B)\n#define BIT_SET_BFRPT_PARA_USERID_SEL_V1_8814B(x, v)                           \\\n\t(BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8814B(x) |                         \\\n\t BIT_BFRPT_PARA_USERID_SEL_V1_8814B(v))\n\n#define BIT_SHIFT_BFRPT_PARA_V1_8814B 0\n#define BIT_MASK_BFRPT_PARA_V1_8814B 0x1fff\n#define BIT_BFRPT_PARA_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_BFRPT_PARA_V1_8814B) << BIT_SHIFT_BFRPT_PARA_V1_8814B)\n#define BITS_BFRPT_PARA_V1_8814B                                               \\\n\t(BIT_MASK_BFRPT_PARA_V1_8814B << BIT_SHIFT_BFRPT_PARA_V1_8814B)\n#define BIT_CLEAR_BFRPT_PARA_V1_8814B(x) ((x) & (~BITS_BFRPT_PARA_V1_8814B))\n#define BIT_GET_BFRPT_PARA_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_BFRPT_PARA_V1_8814B) & BIT_MASK_BFRPT_PARA_V1_8814B)\n#define BIT_SET_BFRPT_PARA_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_BFRPT_PARA_V1_8814B(x) | BIT_BFRPT_PARA_V1_8814B(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8814B */\n#define BIT_STATUS_BFEE2_8814B BIT(10)\n#define BIT_WMAC_MU_BFEE2_EN_8814B BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B 0\n#define BIT_MASK_WMAC_MU_BFEE2_AID_8814B 0x1ff\n#define BIT_WMAC_MU_BFEE2_AID_8814B(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8814B)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B)\n#define BITS_WMAC_MU_BFEE2_AID_8814B                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE2_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B)\n#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8814B(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE2_AID_8814B))\n#define BIT_GET_WMAC_MU_BFEE2_AID_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE2_AID_8814B)\n#define BIT_SET_WMAC_MU_BFEE2_AID_8814B(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE2_AID_8814B(x) | BIT_WMAC_MU_BFEE2_AID_8814B(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8814B */\n#define BIT_STATUS_BFEE3_8814B BIT(10)\n#define BIT_WMAC_MU_BFEE3_EN_8814B BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B 0\n#define BIT_MASK_WMAC_MU_BFEE3_AID_8814B 0x1ff\n#define BIT_WMAC_MU_BFEE3_AID_8814B(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8814B)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B)\n#define BITS_WMAC_MU_BFEE3_AID_8814B                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE3_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B)\n#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8814B(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE3_AID_8814B))\n#define BIT_GET_WMAC_MU_BFEE3_AID_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE3_AID_8814B)\n#define BIT_SET_WMAC_MU_BFEE3_AID_8814B(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE3_AID_8814B(x) | BIT_WMAC_MU_BFEE3_AID_8814B(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8814B */\n#define BIT_STATUS_BFEE4_8814B BIT(10)\n#define BIT_WMAC_MU_BFEE4_EN_8814B BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B 0\n#define BIT_MASK_WMAC_MU_BFEE4_AID_8814B 0x1ff\n#define BIT_WMAC_MU_BFEE4_AID_8814B(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8814B)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B)\n#define BITS_WMAC_MU_BFEE4_AID_8814B                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE4_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B)\n#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8814B(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE4_AID_8814B))\n#define BIT_GET_WMAC_MU_BFEE4_AID_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE4_AID_8814B)\n#define BIT_SET_WMAC_MU_BFEE4_AID_8814B(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE4_AID_8814B(x) | BIT_WMAC_MU_BFEE4_AID_8814B(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8814B */\n#define BIT_BIT_STATUS_BFEE5_8814B BIT(10)\n#define BIT_WMAC_MU_BFEE5_EN_8814B BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B 0\n#define BIT_MASK_WMAC_MU_BFEE5_AID_8814B 0x1ff\n#define BIT_WMAC_MU_BFEE5_AID_8814B(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8814B)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B)\n#define BITS_WMAC_MU_BFEE5_AID_8814B                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE5_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B)\n#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8814B(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE5_AID_8814B))\n#define BIT_GET_WMAC_MU_BFEE5_AID_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE5_AID_8814B)\n#define BIT_SET_WMAC_MU_BFEE5_AID_8814B(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE5_AID_8814B(x) | BIT_WMAC_MU_BFEE5_AID_8814B(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8814B */\n#define BIT_STATUS_BFEE6_8814B BIT(10)\n#define BIT_WMAC_MU_BFEE6_EN_8814B BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B 0\n#define BIT_MASK_WMAC_MU_BFEE6_AID_8814B 0x1ff\n#define BIT_WMAC_MU_BFEE6_AID_8814B(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8814B)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B)\n#define BITS_WMAC_MU_BFEE6_AID_8814B                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE6_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B)\n#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8814B(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE6_AID_8814B))\n#define BIT_GET_WMAC_MU_BFEE6_AID_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE6_AID_8814B)\n#define BIT_SET_WMAC_MU_BFEE6_AID_8814B(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE6_AID_8814B(x) | BIT_WMAC_MU_BFEE6_AID_8814B(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8814B */\n#define BIT_STATUS_BFEE7_8814B BIT(10)\n#define BIT_WMAC_MU_BFEE7_EN_8814B BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B 0\n#define BIT_MASK_WMAC_MU_BFEE7_AID_8814B 0x1ff\n#define BIT_WMAC_MU_BFEE7_AID_8814B(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8814B)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B)\n#define BITS_WMAC_MU_BFEE7_AID_8814B                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE7_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B)\n#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8814B(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE7_AID_8814B))\n#define BIT_GET_WMAC_MU_BFEE7_AID_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE7_AID_8814B)\n#define BIT_SET_WMAC_MU_BFEE7_AID_8814B(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE7_AID_8814B(x) | BIT_WMAC_MU_BFEE7_AID_8814B(v))\n\n/* 2 REG_WMAC_BB_STOP_RX_COUNTER_8814B */\n#define BIT_RST_ALL_COUNTER_8814B BIT(31)\n\n#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B 16\n#define BIT_MASK_ABORT_RX_VBON_COUNTER_8814B 0xff\n#define BIT_ABORT_RX_VBON_COUNTER_8814B(x)                                     \\\n\t(((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8814B)                          \\\n\t << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B)\n#define BITS_ABORT_RX_VBON_COUNTER_8814B                                       \\\n\t(BIT_MASK_ABORT_RX_VBON_COUNTER_8814B                                  \\\n\t << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B)\n#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8814B(x)                               \\\n\t((x) & (~BITS_ABORT_RX_VBON_COUNTER_8814B))\n#define BIT_GET_ABORT_RX_VBON_COUNTER_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B) &                      \\\n\t BIT_MASK_ABORT_RX_VBON_COUNTER_8814B)\n#define BIT_SET_ABORT_RX_VBON_COUNTER_8814B(x, v)                              \\\n\t(BIT_CLEAR_ABORT_RX_VBON_COUNTER_8814B(x) |                            \\\n\t BIT_ABORT_RX_VBON_COUNTER_8814B(v))\n\n#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B 8\n#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B 0xff\n#define BIT_ABORT_RX_RDRDY_COUNTER_8814B(x)                                    \\\n\t(((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B)                         \\\n\t << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B)\n#define BITS_ABORT_RX_RDRDY_COUNTER_8814B                                      \\\n\t(BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B                                 \\\n\t << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B)\n#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8814B(x)                              \\\n\t((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8814B))\n#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8814B(x)                                \\\n\t(((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B) &                     \\\n\t BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B)\n#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8814B(x, v)                             \\\n\t(BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8814B(x) |                           \\\n\t BIT_ABORT_RX_RDRDY_COUNTER_8814B(v))\n\n#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B 0\n#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B 0xff\n#define BIT_VBON_EARLY_FALLING_COUNTER_8814B(x)                                \\\n\t(((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B)                     \\\n\t << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B)\n#define BITS_VBON_EARLY_FALLING_COUNTER_8814B                                  \\\n\t(BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B                             \\\n\t << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B)\n#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8814B(x)                          \\\n\t((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8814B))\n#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8814B(x)                            \\\n\t(((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B) &                 \\\n\t BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B)\n#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8814B(x, v)                         \\\n\t(BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8814B(x) |                       \\\n\t BIT_VBON_EARLY_FALLING_COUNTER_8814B(v))\n\n/* 2 REG_WMAC_PLCP_MONITOR_8814B */\n#define BIT_WMAC_PLCP_TRX_SEL_8814B BIT(31)\n\n#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B 28\n#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B 0x7\n#define BIT_WMAC_PLCP_RDSIG_SEL_8814B(x)                                       \\\n\t(((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B)                            \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B)\n#define BITS_WMAC_PLCP_RDSIG_SEL_8814B                                         \\\n\t(BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B                                    \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B)\n#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8814B(x)                                 \\\n\t((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8814B))\n#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B) &                        \\\n\t BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B)\n#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8814B(x, v)                                \\\n\t(BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8814B(x) |                              \\\n\t BIT_WMAC_PLCP_RDSIG_SEL_8814B(v))\n\n#define BIT_SHIFT_WMAC_RATE_IDX_8814B 24\n#define BIT_MASK_WMAC_RATE_IDX_8814B 0xf\n#define BIT_WMAC_RATE_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_WMAC_RATE_IDX_8814B) << BIT_SHIFT_WMAC_RATE_IDX_8814B)\n#define BITS_WMAC_RATE_IDX_8814B                                               \\\n\t(BIT_MASK_WMAC_RATE_IDX_8814B << BIT_SHIFT_WMAC_RATE_IDX_8814B)\n#define BIT_CLEAR_WMAC_RATE_IDX_8814B(x) ((x) & (~BITS_WMAC_RATE_IDX_8814B))\n#define BIT_GET_WMAC_RATE_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_WMAC_RATE_IDX_8814B) & BIT_MASK_WMAC_RATE_IDX_8814B)\n#define BIT_SET_WMAC_RATE_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_WMAC_RATE_IDX_8814B(x) | BIT_WMAC_RATE_IDX_8814B(v))\n\n#define BIT_SHIFT_WMAC_PLCP_RDSIG_8814B 0\n#define BIT_MASK_WMAC_PLCP_RDSIG_8814B 0xffffff\n#define BIT_WMAC_PLCP_RDSIG_8814B(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_PLCP_RDSIG_8814B)                                \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_8814B)\n#define BITS_WMAC_PLCP_RDSIG_8814B                                             \\\n\t(BIT_MASK_WMAC_PLCP_RDSIG_8814B << BIT_SHIFT_WMAC_PLCP_RDSIG_8814B)\n#define BIT_CLEAR_WMAC_PLCP_RDSIG_8814B(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8814B))\n#define BIT_GET_WMAC_PLCP_RDSIG_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) &                            \\\n\t BIT_MASK_WMAC_PLCP_RDSIG_8814B)\n#define BIT_SET_WMAC_PLCP_RDSIG_8814B(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_PLCP_RDSIG_8814B(x) | BIT_WMAC_PLCP_RDSIG_8814B(v))\n\n/* 2 REG_WMAC_DEBUG_PORT_8814B */\n\n#define BIT_SHIFT_WMAC_DEBUG_PORT_8814B 0\n#define BIT_MASK_WMAC_DEBUG_PORT_8814B 0xffffffffL\n#define BIT_WMAC_DEBUG_PORT_8814B(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_DEBUG_PORT_8814B)                                \\\n\t << BIT_SHIFT_WMAC_DEBUG_PORT_8814B)\n#define BITS_WMAC_DEBUG_PORT_8814B                                             \\\n\t(BIT_MASK_WMAC_DEBUG_PORT_8814B << BIT_SHIFT_WMAC_DEBUG_PORT_8814B)\n#define BIT_CLEAR_WMAC_DEBUG_PORT_8814B(x) ((x) & (~BITS_WMAC_DEBUG_PORT_8814B))\n#define BIT_GET_WMAC_DEBUG_PORT_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_DEBUG_PORT_8814B) &                            \\\n\t BIT_MASK_WMAC_DEBUG_PORT_8814B)\n#define BIT_SET_WMAC_DEBUG_PORT_8814B(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_DEBUG_PORT_8814B(x) | BIT_WMAC_DEBUG_PORT_8814B(v))\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_TRANSMIT_ADDRSS_0_8814B (TA0 REGISTER) */\n\n#define BIT_SHIFT_TA0_V1_8814B 0\n#define BIT_MASK_TA0_V1_8814B 0xffffffffL\n#define BIT_TA0_V1_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_TA0_V1_8814B) << BIT_SHIFT_TA0_V1_8814B)\n#define BITS_TA0_V1_8814B (BIT_MASK_TA0_V1_8814B << BIT_SHIFT_TA0_V1_8814B)\n#define BIT_CLEAR_TA0_V1_8814B(x) ((x) & (~BITS_TA0_V1_8814B))\n#define BIT_GET_TA0_V1_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_TA0_V1_8814B) & BIT_MASK_TA0_V1_8814B)\n#define BIT_SET_TA0_V1_8814B(x, v)                                             \\\n\t(BIT_CLEAR_TA0_V1_8814B(x) | BIT_TA0_V1_8814B(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_0_H_8814B (TA0 REGISTER) */\n\n#define BIT_SHIFT_TA0_H_V1_8814B 0\n#define BIT_MASK_TA0_H_V1_8814B 0xffff\n#define BIT_TA0_H_V1_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_TA0_H_V1_8814B) << BIT_SHIFT_TA0_H_V1_8814B)\n#define BITS_TA0_H_V1_8814B                                                    \\\n\t(BIT_MASK_TA0_H_V1_8814B << BIT_SHIFT_TA0_H_V1_8814B)\n#define BIT_CLEAR_TA0_H_V1_8814B(x) ((x) & (~BITS_TA0_H_V1_8814B))\n#define BIT_GET_TA0_H_V1_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TA0_H_V1_8814B) & BIT_MASK_TA0_H_V1_8814B)\n#define BIT_SET_TA0_H_V1_8814B(x, v)                                           \\\n\t(BIT_CLEAR_TA0_H_V1_8814B(x) | BIT_TA0_H_V1_8814B(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_1_8814B (TA1 REGISTER) */\n\n#define BIT_SHIFT_TA1_V1_8814B 0\n#define BIT_MASK_TA1_V1_8814B 0xffffffffL\n#define BIT_TA1_V1_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_TA1_V1_8814B) << BIT_SHIFT_TA1_V1_8814B)\n#define BITS_TA1_V1_8814B (BIT_MASK_TA1_V1_8814B << BIT_SHIFT_TA1_V1_8814B)\n#define BIT_CLEAR_TA1_V1_8814B(x) ((x) & (~BITS_TA1_V1_8814B))\n#define BIT_GET_TA1_V1_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_TA1_V1_8814B) & BIT_MASK_TA1_V1_8814B)\n#define BIT_SET_TA1_V1_8814B(x, v)                                             \\\n\t(BIT_CLEAR_TA1_V1_8814B(x) | BIT_TA1_V1_8814B(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_1_H_8814B (TA1 REGISTER) */\n\n#define BIT_SHIFT_TA1_H_V1_8814B 0\n#define BIT_MASK_TA1_H_V1_8814B 0xffff\n#define BIT_TA1_H_V1_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_TA1_H_V1_8814B) << BIT_SHIFT_TA1_H_V1_8814B)\n#define BITS_TA1_H_V1_8814B                                                    \\\n\t(BIT_MASK_TA1_H_V1_8814B << BIT_SHIFT_TA1_H_V1_8814B)\n#define BIT_CLEAR_TA1_H_V1_8814B(x) ((x) & (~BITS_TA1_H_V1_8814B))\n#define BIT_GET_TA1_H_V1_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TA1_H_V1_8814B) & BIT_MASK_TA1_H_V1_8814B)\n#define BIT_SET_TA1_H_V1_8814B(x, v)                                           \\\n\t(BIT_CLEAR_TA1_H_V1_8814B(x) | BIT_TA1_H_V1_8814B(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_2_8814B (TA2 REGISTER) */\n\n#define BIT_SHIFT_TA2_V1_8814B 0\n#define BIT_MASK_TA2_V1_8814B 0xffffffffL\n#define BIT_TA2_V1_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_TA2_V1_8814B) << BIT_SHIFT_TA2_V1_8814B)\n#define BITS_TA2_V1_8814B (BIT_MASK_TA2_V1_8814B << BIT_SHIFT_TA2_V1_8814B)\n#define BIT_CLEAR_TA2_V1_8814B(x) ((x) & (~BITS_TA2_V1_8814B))\n#define BIT_GET_TA2_V1_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_TA2_V1_8814B) & BIT_MASK_TA2_V1_8814B)\n#define BIT_SET_TA2_V1_8814B(x, v)                                             \\\n\t(BIT_CLEAR_TA2_V1_8814B(x) | BIT_TA2_V1_8814B(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_2_H_8814B (TA2 REGISTER) */\n\n#define BIT_SHIFT_TA2_H_V1_8814B 0\n#define BIT_MASK_TA2_H_V1_8814B 0xffff\n#define BIT_TA2_H_V1_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_TA2_H_V1_8814B) << BIT_SHIFT_TA2_H_V1_8814B)\n#define BITS_TA2_H_V1_8814B                                                    \\\n\t(BIT_MASK_TA2_H_V1_8814B << BIT_SHIFT_TA2_H_V1_8814B)\n#define BIT_CLEAR_TA2_H_V1_8814B(x) ((x) & (~BITS_TA2_H_V1_8814B))\n#define BIT_GET_TA2_H_V1_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TA2_H_V1_8814B) & BIT_MASK_TA2_H_V1_8814B)\n#define BIT_SET_TA2_H_V1_8814B(x, v)                                           \\\n\t(BIT_CLEAR_TA2_H_V1_8814B(x) | BIT_TA2_H_V1_8814B(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_3_8814B (TA3 REGISTER) */\n\n#define BIT_SHIFT_TA2_V1_8814B 0\n#define BIT_MASK_TA2_V1_8814B 0xffffffffL\n#define BIT_TA2_V1_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_TA2_V1_8814B) << BIT_SHIFT_TA2_V1_8814B)\n#define BITS_TA2_V1_8814B (BIT_MASK_TA2_V1_8814B << BIT_SHIFT_TA2_V1_8814B)\n#define BIT_CLEAR_TA2_V1_8814B(x) ((x) & (~BITS_TA2_V1_8814B))\n#define BIT_GET_TA2_V1_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_TA2_V1_8814B) & BIT_MASK_TA2_V1_8814B)\n#define BIT_SET_TA2_V1_8814B(x, v)                                             \\\n\t(BIT_CLEAR_TA2_V1_8814B(x) | BIT_TA2_V1_8814B(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_3_H_8814B (TA3 REGISTER) */\n\n#define BIT_SHIFT_TA3_H_V1_8814B 0\n#define BIT_MASK_TA3_H_V1_8814B 0xffff\n#define BIT_TA3_H_V1_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_TA3_H_V1_8814B) << BIT_SHIFT_TA3_H_V1_8814B)\n#define BITS_TA3_H_V1_8814B                                                    \\\n\t(BIT_MASK_TA3_H_V1_8814B << BIT_SHIFT_TA3_H_V1_8814B)\n#define BIT_CLEAR_TA3_H_V1_8814B(x) ((x) & (~BITS_TA3_H_V1_8814B))\n#define BIT_GET_TA3_H_V1_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TA3_H_V1_8814B) & BIT_MASK_TA3_H_V1_8814B)\n#define BIT_SET_TA3_H_V1_8814B(x, v)                                           \\\n\t(BIT_CLEAR_TA3_H_V1_8814B(x) | BIT_TA3_H_V1_8814B(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_4_8814B (TA4 REGISTER) */\n\n#define BIT_SHIFT_TA4_V1_8814B 0\n#define BIT_MASK_TA4_V1_8814B 0xffffffffL\n#define BIT_TA4_V1_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_TA4_V1_8814B) << BIT_SHIFT_TA4_V1_8814B)\n#define BITS_TA4_V1_8814B (BIT_MASK_TA4_V1_8814B << BIT_SHIFT_TA4_V1_8814B)\n#define BIT_CLEAR_TA4_V1_8814B(x) ((x) & (~BITS_TA4_V1_8814B))\n#define BIT_GET_TA4_V1_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_TA4_V1_8814B) & BIT_MASK_TA4_V1_8814B)\n#define BIT_SET_TA4_V1_8814B(x, v)                                             \\\n\t(BIT_CLEAR_TA4_V1_8814B(x) | BIT_TA4_V1_8814B(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_4_H_8814B (TA4 REGISTER) */\n\n#define BIT_SHIFT_TA4_H_V1_8814B 0\n#define BIT_MASK_TA4_H_V1_8814B 0xffff\n#define BIT_TA4_H_V1_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_TA4_H_V1_8814B) << BIT_SHIFT_TA4_H_V1_8814B)\n#define BITS_TA4_H_V1_8814B                                                    \\\n\t(BIT_MASK_TA4_H_V1_8814B << BIT_SHIFT_TA4_H_V1_8814B)\n#define BIT_CLEAR_TA4_H_V1_8814B(x) ((x) & (~BITS_TA4_H_V1_8814B))\n#define BIT_GET_TA4_H_V1_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TA4_H_V1_8814B) & BIT_MASK_TA4_H_V1_8814B)\n#define BIT_SET_TA4_H_V1_8814B(x, v)                                           \\\n\t(BIT_CLEAR_TA4_H_V1_8814B(x) | BIT_TA4_H_V1_8814B(v))\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_RSVD_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_MACID1_8814B */\n\n#define BIT_SHIFT_MACID1_0_8814B 0\n#define BIT_MASK_MACID1_0_8814B 0xffffffffL\n#define BIT_MACID1_0_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_MACID1_0_8814B) << BIT_SHIFT_MACID1_0_8814B)\n#define BITS_MACID1_0_8814B                                                    \\\n\t(BIT_MASK_MACID1_0_8814B << BIT_SHIFT_MACID1_0_8814B)\n#define BIT_CLEAR_MACID1_0_8814B(x) ((x) & (~BITS_MACID1_0_8814B))\n#define BIT_GET_MACID1_0_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_MACID1_0_8814B) & BIT_MASK_MACID1_0_8814B)\n#define BIT_SET_MACID1_0_8814B(x, v)                                           \\\n\t(BIT_CLEAR_MACID1_0_8814B(x) | BIT_MACID1_0_8814B(v))\n\n/* 2 REG_MACID1_1_8814B */\n\n#define BIT_SHIFT_MACID1_1_8814B 0\n#define BIT_MASK_MACID1_1_8814B 0xffff\n#define BIT_MACID1_1_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_MACID1_1_8814B) << BIT_SHIFT_MACID1_1_8814B)\n#define BITS_MACID1_1_8814B                                                    \\\n\t(BIT_MASK_MACID1_1_8814B << BIT_SHIFT_MACID1_1_8814B)\n#define BIT_CLEAR_MACID1_1_8814B(x) ((x) & (~BITS_MACID1_1_8814B))\n#define BIT_GET_MACID1_1_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_MACID1_1_8814B) & BIT_MASK_MACID1_1_8814B)\n#define BIT_SET_MACID1_1_8814B(x, v)                                           \\\n\t(BIT_CLEAR_MACID1_1_8814B(x) | BIT_MACID1_1_8814B(v))\n\n/* 2 REG_BSSID1_8814B */\n\n#define BIT_SHIFT_BSSID1_0_8814B 0\n#define BIT_MASK_BSSID1_0_8814B 0xffffffffL\n#define BIT_BSSID1_0_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_BSSID1_0_8814B) << BIT_SHIFT_BSSID1_0_8814B)\n#define BITS_BSSID1_0_8814B                                                    \\\n\t(BIT_MASK_BSSID1_0_8814B << BIT_SHIFT_BSSID1_0_8814B)\n#define BIT_CLEAR_BSSID1_0_8814B(x) ((x) & (~BITS_BSSID1_0_8814B))\n#define BIT_GET_BSSID1_0_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_BSSID1_0_8814B) & BIT_MASK_BSSID1_0_8814B)\n#define BIT_SET_BSSID1_0_8814B(x, v)                                           \\\n\t(BIT_CLEAR_BSSID1_0_8814B(x) | BIT_BSSID1_0_8814B(v))\n\n/* 2 REG_BSSID1_1_8814B */\n\n#define BIT_SHIFT_BSSID1_1_8814B 0\n#define BIT_MASK_BSSID1_1_8814B 0xffff\n#define BIT_BSSID1_1_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_BSSID1_1_8814B) << BIT_SHIFT_BSSID1_1_8814B)\n#define BITS_BSSID1_1_8814B                                                    \\\n\t(BIT_MASK_BSSID1_1_8814B << BIT_SHIFT_BSSID1_1_8814B)\n#define BIT_CLEAR_BSSID1_1_8814B(x) ((x) & (~BITS_BSSID1_1_8814B))\n#define BIT_GET_BSSID1_1_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_BSSID1_1_8814B) & BIT_MASK_BSSID1_1_8814B)\n#define BIT_SET_BSSID1_1_8814B(x, v)                                           \\\n\t(BIT_CLEAR_BSSID1_1_8814B(x) | BIT_BSSID1_1_8814B(v))\n\n/* 2 REG_BCN_PSR_RPT1_8814B */\n\n#define BIT_SHIFT_DTIM_CNT1_8814B 24\n#define BIT_MASK_DTIM_CNT1_8814B 0xff\n#define BIT_DTIM_CNT1_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT1_8814B) << BIT_SHIFT_DTIM_CNT1_8814B)\n#define BITS_DTIM_CNT1_8814B                                                   \\\n\t(BIT_MASK_DTIM_CNT1_8814B << BIT_SHIFT_DTIM_CNT1_8814B)\n#define BIT_CLEAR_DTIM_CNT1_8814B(x) ((x) & (~BITS_DTIM_CNT1_8814B))\n#define BIT_GET_DTIM_CNT1_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT1_8814B) & BIT_MASK_DTIM_CNT1_8814B)\n#define BIT_SET_DTIM_CNT1_8814B(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT1_8814B(x) | BIT_DTIM_CNT1_8814B(v))\n\n#define BIT_SHIFT_DTIM_PERIOD1_8814B 16\n#define BIT_MASK_DTIM_PERIOD1_8814B 0xff\n#define BIT_DTIM_PERIOD1_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD1_8814B) << BIT_SHIFT_DTIM_PERIOD1_8814B)\n#define BITS_DTIM_PERIOD1_8814B                                                \\\n\t(BIT_MASK_DTIM_PERIOD1_8814B << BIT_SHIFT_DTIM_PERIOD1_8814B)\n#define BIT_CLEAR_DTIM_PERIOD1_8814B(x) ((x) & (~BITS_DTIM_PERIOD1_8814B))\n#define BIT_GET_DTIM_PERIOD1_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD1_8814B) & BIT_MASK_DTIM_PERIOD1_8814B)\n#define BIT_SET_DTIM_PERIOD1_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD1_8814B(x) | BIT_DTIM_PERIOD1_8814B(v))\n\n#define BIT_DTIM1_8814B BIT(15)\n#define BIT_TIM1_8814B BIT(14)\n\n#define BIT_SHIFT_PS_AID_1_8814B 0\n#define BIT_MASK_PS_AID_1_8814B 0x7ff\n#define BIT_PS_AID_1_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_1_8814B) << BIT_SHIFT_PS_AID_1_8814B)\n#define BITS_PS_AID_1_8814B                                                    \\\n\t(BIT_MASK_PS_AID_1_8814B << BIT_SHIFT_PS_AID_1_8814B)\n#define BIT_CLEAR_PS_AID_1_8814B(x) ((x) & (~BITS_PS_AID_1_8814B))\n#define BIT_GET_PS_AID_1_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_1_8814B) & BIT_MASK_PS_AID_1_8814B)\n#define BIT_SET_PS_AID_1_8814B(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_1_8814B(x) | BIT_PS_AID_1_8814B(v))\n\n/* 2 REG_ASSOCIATED_BFMEE_SEL_8814B */\n#define BIT_TXUSER_ID1_8814B BIT(25)\n\n#define BIT_SHIFT_AID1_8814B 16\n#define BIT_MASK_AID1_8814B 0x1ff\n#define BIT_AID1_8814B(x) (((x) & BIT_MASK_AID1_8814B) << BIT_SHIFT_AID1_8814B)\n#define BITS_AID1_8814B (BIT_MASK_AID1_8814B << BIT_SHIFT_AID1_8814B)\n#define BIT_CLEAR_AID1_8814B(x) ((x) & (~BITS_AID1_8814B))\n#define BIT_GET_AID1_8814B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AID1_8814B) & BIT_MASK_AID1_8814B)\n#define BIT_SET_AID1_8814B(x, v) (BIT_CLEAR_AID1_8814B(x) | BIT_AID1_8814B(v))\n\n#define BIT_TXUSER_ID0_8814B BIT(9)\n\n#define BIT_SHIFT_AID0_8814B 0\n#define BIT_MASK_AID0_8814B 0x1ff\n#define BIT_AID0_8814B(x) (((x) & BIT_MASK_AID0_8814B) << BIT_SHIFT_AID0_8814B)\n#define BITS_AID0_8814B (BIT_MASK_AID0_8814B << BIT_SHIFT_AID0_8814B)\n#define BIT_CLEAR_AID0_8814B(x) ((x) & (~BITS_AID0_8814B))\n#define BIT_GET_AID0_8814B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AID0_8814B) & BIT_MASK_AID0_8814B)\n#define BIT_SET_AID0_8814B(x, v) (BIT_CLEAR_AID0_8814B(x) | BIT_AID0_8814B(v))\n\n/* 2 REG_SND_PTCL_CTRL_8814B */\n\n#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B 24\n#define BIT_MASK_NDP_RX_STANDBY_TIMER_8814B 0xff\n#define BIT_NDP_RX_STANDBY_TIMER_8814B(x)                                      \\\n\t(((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8814B)                           \\\n\t << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B)\n#define BITS_NDP_RX_STANDBY_TIMER_8814B                                        \\\n\t(BIT_MASK_NDP_RX_STANDBY_TIMER_8814B                                   \\\n\t << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B)\n#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8814B(x)                                \\\n\t((x) & (~BITS_NDP_RX_STANDBY_TIMER_8814B))\n#define BIT_GET_NDP_RX_STANDBY_TIMER_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B) &                       \\\n\t BIT_MASK_NDP_RX_STANDBY_TIMER_8814B)\n#define BIT_SET_NDP_RX_STANDBY_TIMER_8814B(x, v)                               \\\n\t(BIT_CLEAR_NDP_RX_STANDBY_TIMER_8814B(x) |                             \\\n\t BIT_NDP_RX_STANDBY_TIMER_8814B(v))\n\n#define BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B 16\n#define BIT_MASK_CSI_RPT_OFFSET_HT_8814B 0xff\n#define BIT_CSI_RPT_OFFSET_HT_8814B(x)                                         \\\n\t(((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8814B)                              \\\n\t << BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B)\n#define BITS_CSI_RPT_OFFSET_HT_8814B                                           \\\n\t(BIT_MASK_CSI_RPT_OFFSET_HT_8814B << BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B)\n#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8814B(x)                                   \\\n\t((x) & (~BITS_CSI_RPT_OFFSET_HT_8814B))\n#define BIT_GET_CSI_RPT_OFFSET_HT_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B) &                          \\\n\t BIT_MASK_CSI_RPT_OFFSET_HT_8814B)\n#define BIT_SET_CSI_RPT_OFFSET_HT_8814B(x, v)                                  \\\n\t(BIT_CLEAR_CSI_RPT_OFFSET_HT_8814B(x) | BIT_CSI_RPT_OFFSET_HT_8814B(v))\n\n#define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL_8814B BIT(15)\n#define BIT_R_WMAC_CSI_CHKSUM_DIS_8814B BIT(14)\n\n#define BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B 8\n#define BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B 0x3f\n#define BIT_R_CSI_RPT_OFFSET_VHT_V1_8814B(x)                                   \\\n\t(((x) & BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B)                        \\\n\t << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B)\n#define BITS_R_CSI_RPT_OFFSET_VHT_V1_8814B                                     \\\n\t(BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B                                \\\n\t << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B)\n#define BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8814B(x)                             \\\n\t((x) & (~BITS_R_CSI_RPT_OFFSET_VHT_V1_8814B))\n#define BIT_GET_R_CSI_RPT_OFFSET_VHT_V1_8814B(x)                               \\\n\t(((x) >> BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B) &                    \\\n\t BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B)\n#define BIT_SET_R_CSI_RPT_OFFSET_VHT_V1_8814B(x, v)                            \\\n\t(BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8814B(x) |                          \\\n\t BIT_R_CSI_RPT_OFFSET_VHT_V1_8814B(v))\n\n#define BIT_R_WMAC_USE_NSTS_8814B BIT(7)\n#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8814B BIT(6)\n#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8814B BIT(5)\n#define BIT_R_WMAC_BFPARAM_SEL_8814B BIT(4)\n#define BIT_R_WMAC_CSISEQ_SEL_8814B BIT(3)\n#define BIT_R_WMAC_CSI_WITHHTC_EN_8814B BIT(2)\n#define BIT_R_WMAC_HT_NDPA_EN_8814B BIT(1)\n#define BIT_R_WMAC_VHT_NDPA_EN_8814B BIT(0)\n\n/* 2 REG_RX_CSI_RPT_INFO_8814B */\n#define BIT_WRITE_ENABLE_8814B BIT(31)\n#define BIT_WMAC_CHECK_SOUNDING_SEQ_8814B BIT(30)\n\n#define BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B 1\n#define BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B 0xffffff\n#define BIT_VHTHT_MIMO_CTRL_FIELD_8814B(x)                                     \\\n\t(((x) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B)                          \\\n\t << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B)\n#define BITS_VHTHT_MIMO_CTRL_FIELD_8814B                                       \\\n\t(BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B                                  \\\n\t << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B)\n#define BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8814B(x)                               \\\n\t((x) & (~BITS_VHTHT_MIMO_CTRL_FIELD_8814B))\n#define BIT_GET_VHTHT_MIMO_CTRL_FIELD_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B) &                      \\\n\t BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B)\n#define BIT_SET_VHTHT_MIMO_CTRL_FIELD_8814B(x, v)                              \\\n\t(BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8814B(x) |                            \\\n\t BIT_VHTHT_MIMO_CTRL_FIELD_8814B(v))\n\n#define BIT_CSI_INTERRUPT_STATUS_8814B BIT(0)\n\n/* 2 REG_NS_ARP_CTRL_8814B */\n#define BIT_R_WMAC_NSARP_RSPEN_8814B BIT(15)\n#define BIT_R_WMAC_NSARP_RARP_8814B BIT(9)\n#define BIT_R_WMAC_NSARP_RIPV6_8814B BIT(8)\n\n#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B 6\n#define BIT_MASK_R_WMAC_NSARP_MODEN_8814B 0x3\n#define BIT_R_WMAC_NSARP_MODEN_8814B(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8814B)                             \\\n\t << BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B)\n#define BITS_R_WMAC_NSARP_MODEN_8814B                                          \\\n\t(BIT_MASK_R_WMAC_NSARP_MODEN_8814B                                     \\\n\t << BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B)\n#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8814B(x)                                  \\\n\t((x) & (~BITS_R_WMAC_NSARP_MODEN_8814B))\n#define BIT_GET_R_WMAC_NSARP_MODEN_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B) &                         \\\n\t BIT_MASK_R_WMAC_NSARP_MODEN_8814B)\n#define BIT_SET_R_WMAC_NSARP_MODEN_8814B(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_NSARP_MODEN_8814B(x) |                               \\\n\t BIT_R_WMAC_NSARP_MODEN_8814B(v))\n\n#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B 4\n#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B 0x3\n#define BIT_R_WMAC_NSARP_RSPFTP_8814B(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B)                            \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B)\n#define BITS_R_WMAC_NSARP_RSPFTP_8814B                                         \\\n\t(BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B                                    \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B)\n#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8814B(x)                                 \\\n\t((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8814B))\n#define BIT_GET_R_WMAC_NSARP_RSPFTP_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B) &                        \\\n\t BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B)\n#define BIT_SET_R_WMAC_NSARP_RSPFTP_8814B(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8814B(x) |                              \\\n\t BIT_R_WMAC_NSARP_RSPFTP_8814B(v))\n\n#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B 0\n#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B 0xf\n#define BIT_R_WMAC_NSARP_RSPSEC_8814B(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B)                            \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B)\n#define BITS_R_WMAC_NSARP_RSPSEC_8814B                                         \\\n\t(BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B                                    \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B)\n#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8814B(x)                                 \\\n\t((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8814B))\n#define BIT_GET_R_WMAC_NSARP_RSPSEC_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B) &                        \\\n\t BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B)\n#define BIT_SET_R_WMAC_NSARP_RSPSEC_8814B(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8814B(x) |                              \\\n\t BIT_R_WMAC_NSARP_RSPSEC_8814B(v))\n\n/* 2 REG_NS_ARP_INFO_8814B */\n#define BIT_REQ_IS_MCNS_8814B BIT(23)\n#define BIT_REQ_IS_UCNS_8814B BIT(22)\n#define BIT_REQ_IS_USNS_8814B BIT(21)\n#define BIT_REQ_IS_ARP_8814B BIT(20)\n#define BIT_EXPRSP_MH_WITHQC_8814B BIT(19)\n\n#define BIT_SHIFT_EXPRSP_SECTYPE_8814B 16\n#define BIT_MASK_EXPRSP_SECTYPE_8814B 0x7\n#define BIT_EXPRSP_SECTYPE_8814B(x)                                            \\\n\t(((x) & BIT_MASK_EXPRSP_SECTYPE_8814B)                                 \\\n\t << BIT_SHIFT_EXPRSP_SECTYPE_8814B)\n#define BITS_EXPRSP_SECTYPE_8814B                                              \\\n\t(BIT_MASK_EXPRSP_SECTYPE_8814B << BIT_SHIFT_EXPRSP_SECTYPE_8814B)\n#define BIT_CLEAR_EXPRSP_SECTYPE_8814B(x) ((x) & (~BITS_EXPRSP_SECTYPE_8814B))\n#define BIT_GET_EXPRSP_SECTYPE_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8814B) &                             \\\n\t BIT_MASK_EXPRSP_SECTYPE_8814B)\n#define BIT_SET_EXPRSP_SECTYPE_8814B(x, v)                                     \\\n\t(BIT_CLEAR_EXPRSP_SECTYPE_8814B(x) | BIT_EXPRSP_SECTYPE_8814B(v))\n\n#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B 8\n#define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B 0xff\n#define BIT_EXPRSP_CHKSM_7_TO_0_8814B(x)                                       \\\n\t(((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B)                            \\\n\t << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B)\n#define BITS_EXPRSP_CHKSM_7_TO_0_8814B                                         \\\n\t(BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B                                    \\\n\t << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B)\n#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8814B(x)                                 \\\n\t((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8814B))\n#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B) &                        \\\n\t BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B)\n#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8814B(x, v)                                \\\n\t(BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8814B(x) |                              \\\n\t BIT_EXPRSP_CHKSM_7_TO_0_8814B(v))\n\n#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B 0\n#define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B 0xff\n#define BIT_EXPRSP_CHKSM_15_TO_8_8814B(x)                                      \\\n\t(((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B)                           \\\n\t << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B)\n#define BITS_EXPRSP_CHKSM_15_TO_8_8814B                                        \\\n\t(BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B                                   \\\n\t << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B)\n#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8814B(x)                                \\\n\t((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8814B))\n#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B) &                       \\\n\t BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B)\n#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8814B(x, v)                               \\\n\t(BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8814B(x) |                             \\\n\t BIT_EXPRSP_CHKSM_15_TO_8_8814B(v))\n\n/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8814B */\n\n#define BIT_SHIFT_WMAC_ARPIP_8814B 0\n#define BIT_MASK_WMAC_ARPIP_8814B 0xffffffffL\n#define BIT_WMAC_ARPIP_8814B(x)                                                \\\n\t(((x) & BIT_MASK_WMAC_ARPIP_8814B) << BIT_SHIFT_WMAC_ARPIP_8814B)\n#define BITS_WMAC_ARPIP_8814B                                                  \\\n\t(BIT_MASK_WMAC_ARPIP_8814B << BIT_SHIFT_WMAC_ARPIP_8814B)\n#define BIT_CLEAR_WMAC_ARPIP_8814B(x) ((x) & (~BITS_WMAC_ARPIP_8814B))\n#define BIT_GET_WMAC_ARPIP_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_WMAC_ARPIP_8814B) & BIT_MASK_WMAC_ARPIP_8814B)\n#define BIT_SET_WMAC_ARPIP_8814B(x, v)                                         \\\n\t(BIT_CLEAR_WMAC_ARPIP_8814B(x) | BIT_WMAC_ARPIP_8814B(v))\n\n/* 2 REG_BEAMFORMING_INFO_NSARP_8814B */\n\n#define BIT_SHIFT_BEAMFORMING_INFO_8814B 0\n#define BIT_MASK_BEAMFORMING_INFO_8814B 0xffffffffL\n#define BIT_BEAMFORMING_INFO_8814B(x)                                          \\\n\t(((x) & BIT_MASK_BEAMFORMING_INFO_8814B)                               \\\n\t << BIT_SHIFT_BEAMFORMING_INFO_8814B)\n#define BITS_BEAMFORMING_INFO_8814B                                            \\\n\t(BIT_MASK_BEAMFORMING_INFO_8814B << BIT_SHIFT_BEAMFORMING_INFO_8814B)\n#define BIT_CLEAR_BEAMFORMING_INFO_8814B(x)                                    \\\n\t((x) & (~BITS_BEAMFORMING_INFO_8814B))\n#define BIT_GET_BEAMFORMING_INFO_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BEAMFORMING_INFO_8814B) &                           \\\n\t BIT_MASK_BEAMFORMING_INFO_8814B)\n#define BIT_SET_BEAMFORMING_INFO_8814B(x, v)                                   \\\n\t(BIT_CLEAR_BEAMFORMING_INFO_8814B(x) | BIT_BEAMFORMING_INFO_8814B(v))\n\n/* 2 REG_IPV6_8814B */\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B 0xffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD_0_8814B(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B)                           \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B)\n#define BITS_R_WMAC_IPV6_MYIPAD_0_8814B                                        \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B                                   \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8814B(x)                                \\\n\t((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0_8814B))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B) &                       \\\n\t BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD_0_8814B(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8814B(x) |                             \\\n\t BIT_R_WMAC_IPV6_MYIPAD_0_8814B(v))\n\n/* 2 REG_IPV6_1_8814B */\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B 0xffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD_1_8814B(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B)                           \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B)\n#define BITS_R_WMAC_IPV6_MYIPAD_1_8814B                                        \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B                                   \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8814B(x)                                \\\n\t((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1_8814B))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B) &                       \\\n\t BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD_1_8814B(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8814B(x) |                             \\\n\t BIT_R_WMAC_IPV6_MYIPAD_1_8814B(v))\n\n/* 2 REG_IPV6_2_8814B */\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B 0xffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD_2_8814B(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B)                           \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B)\n#define BITS_R_WMAC_IPV6_MYIPAD_2_8814B                                        \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B                                   \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8814B(x)                                \\\n\t((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2_8814B))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B) &                       \\\n\t BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD_2_8814B(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8814B(x) |                             \\\n\t BIT_R_WMAC_IPV6_MYIPAD_2_8814B(v))\n\n/* 2 REG_IPV6_3_8814B */\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B 0xffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD_3_8814B(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B)                           \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B)\n#define BITS_R_WMAC_IPV6_MYIPAD_3_8814B                                        \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B                                   \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8814B(x)                                \\\n\t((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3_8814B))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B) &                       \\\n\t BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD_3_8814B(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8814B(x) |                             \\\n\t BIT_R_WMAC_IPV6_MYIPAD_3_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8814B */\n\n#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B 4\n#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B 0xf\n#define BIT_R_WMAC_CTX_SUBTYPE_8814B(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B)                             \\\n\t << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B)\n#define BITS_R_WMAC_CTX_SUBTYPE_8814B                                          \\\n\t(BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B                                     \\\n\t << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B)\n#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8814B(x)                                  \\\n\t((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8814B))\n#define BIT_GET_R_WMAC_CTX_SUBTYPE_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B) &                         \\\n\t BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B)\n#define BIT_SET_R_WMAC_CTX_SUBTYPE_8814B(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8814B(x) |                               \\\n\t BIT_R_WMAC_CTX_SUBTYPE_8814B(v))\n\n#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B 0\n#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B 0xf\n#define BIT_R_WMAC_RTX_SUBTYPE_8814B(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B)                             \\\n\t << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B)\n#define BITS_R_WMAC_RTX_SUBTYPE_8814B                                          \\\n\t(BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B                                     \\\n\t << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B)\n#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8814B(x)                                  \\\n\t((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8814B))\n#define BIT_GET_R_WMAC_RTX_SUBTYPE_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B) &                         \\\n\t BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B)\n#define BIT_SET_R_WMAC_RTX_SUBTYPE_8814B(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8814B(x) |                               \\\n\t BIT_R_WMAC_RTX_SUBTYPE_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_WMAC_SWAES_CFG_8814B */\n\n/* 2 REG_BT_COEX_V2_8814B */\n#define BIT_GNT_BT_POLARITY_8814B BIT(12)\n#define BIT_GNT_BT_BYPASS_PRIORITY_8814B BIT(8)\n\n#define BIT_SHIFT_TIMER_8814B 0\n#define BIT_MASK_TIMER_8814B 0xff\n#define BIT_TIMER_8814B(x)                                                     \\\n\t(((x) & BIT_MASK_TIMER_8814B) << BIT_SHIFT_TIMER_8814B)\n#define BITS_TIMER_8814B (BIT_MASK_TIMER_8814B << BIT_SHIFT_TIMER_8814B)\n#define BIT_CLEAR_TIMER_8814B(x) ((x) & (~BITS_TIMER_8814B))\n#define BIT_GET_TIMER_8814B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TIMER_8814B) & BIT_MASK_TIMER_8814B)\n#define BIT_SET_TIMER_8814B(x, v)                                              \\\n\t(BIT_CLEAR_TIMER_8814B(x) | BIT_TIMER_8814B(v))\n\n/* 2 REG_BT_COEX_8814B */\n#define BIT_R_GNT_BT_RFC_SW_8814B BIT(12)\n#define BIT_R_GNT_BT_RFC_SW_EN_8814B BIT(11)\n#define BIT_R_GNT_BT_BB_SW_8814B BIT(10)\n#define BIT_R_GNT_BT_BB_SW_EN_8814B BIT(9)\n#define BIT_R_BT_CNT_THREN_8814B BIT(8)\n\n#define BIT_SHIFT_R_BT_CNT_THR_8814B 0\n#define BIT_MASK_R_BT_CNT_THR_8814B 0xff\n#define BIT_R_BT_CNT_THR_8814B(x)                                              \\\n\t(((x) & BIT_MASK_R_BT_CNT_THR_8814B) << BIT_SHIFT_R_BT_CNT_THR_8814B)\n#define BITS_R_BT_CNT_THR_8814B                                                \\\n\t(BIT_MASK_R_BT_CNT_THR_8814B << BIT_SHIFT_R_BT_CNT_THR_8814B)\n#define BIT_CLEAR_R_BT_CNT_THR_8814B(x) ((x) & (~BITS_R_BT_CNT_THR_8814B))\n#define BIT_GET_R_BT_CNT_THR_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_BT_CNT_THR_8814B) & BIT_MASK_R_BT_CNT_THR_8814B)\n#define BIT_SET_R_BT_CNT_THR_8814B(x, v)                                       \\\n\t(BIT_CLEAR_R_BT_CNT_THR_8814B(x) | BIT_R_BT_CNT_THR_8814B(v))\n\n/* 2 REG_WLAN_ACT_MASK_CTRL_8814B */\n\n#define BIT_SHIFT_RXMYRTS_NAV_V1_8814B 8\n#define BIT_MASK_RXMYRTS_NAV_V1_8814B 0xff\n#define BIT_RXMYRTS_NAV_V1_8814B(x)                                            \\\n\t(((x) & BIT_MASK_RXMYRTS_NAV_V1_8814B)                                 \\\n\t << BIT_SHIFT_RXMYRTS_NAV_V1_8814B)\n#define BITS_RXMYRTS_NAV_V1_8814B                                              \\\n\t(BIT_MASK_RXMYRTS_NAV_V1_8814B << BIT_SHIFT_RXMYRTS_NAV_V1_8814B)\n#define BIT_CLEAR_RXMYRTS_NAV_V1_8814B(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8814B))\n#define BIT_GET_RXMYRTS_NAV_V1_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8814B) &                             \\\n\t BIT_MASK_RXMYRTS_NAV_V1_8814B)\n#define BIT_SET_RXMYRTS_NAV_V1_8814B(x, v)                                     \\\n\t(BIT_CLEAR_RXMYRTS_NAV_V1_8814B(x) | BIT_RXMYRTS_NAV_V1_8814B(v))\n\n#define BIT_SHIFT_RTSRST_V1_8814B 0\n#define BIT_MASK_RTSRST_V1_8814B 0xff\n#define BIT_RTSRST_V1_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_RTSRST_V1_8814B) << BIT_SHIFT_RTSRST_V1_8814B)\n#define BITS_RTSRST_V1_8814B                                                   \\\n\t(BIT_MASK_RTSRST_V1_8814B << BIT_SHIFT_RTSRST_V1_8814B)\n#define BIT_CLEAR_RTSRST_V1_8814B(x) ((x) & (~BITS_RTSRST_V1_8814B))\n#define BIT_GET_RTSRST_V1_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_RTSRST_V1_8814B) & BIT_MASK_RTSRST_V1_8814B)\n#define BIT_SET_RTSRST_V1_8814B(x, v)                                          \\\n\t(BIT_CLEAR_RTSRST_V1_8814B(x) | BIT_RTSRST_V1_8814B(v))\n\n/* 2 REG_WLAN_ACT_MASK_CTRL_1_8814B */\n#define BIT_WLRX_TER_BY_CTL_1_8814B BIT(11)\n#define BIT_WLRX_TER_BY_AD_1_8814B BIT(10)\n#define BIT_ANT_DIVERSITY_SEL_1_8814B BIT(9)\n#define BIT_ANTSEL_FOR_BT_CTRL_EN_1_8814B BIT(8)\n#define BIT_WLACT_LOW_GNTWL_EN_1_8814B BIT(2)\n#define BIT_WLACT_HIGH_GNTBT_EN_1_8814B BIT(1)\n#define BIT_NAV_UPPER_1_V1_8814B BIT(0)\n\n/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8814B */\n\n#define BIT_SHIFT_BT_STAT_DELAY_8814B 12\n#define BIT_MASK_BT_STAT_DELAY_8814B 0xf\n#define BIT_BT_STAT_DELAY_8814B(x)                                             \\\n\t(((x) & BIT_MASK_BT_STAT_DELAY_8814B) << BIT_SHIFT_BT_STAT_DELAY_8814B)\n#define BITS_BT_STAT_DELAY_8814B                                               \\\n\t(BIT_MASK_BT_STAT_DELAY_8814B << BIT_SHIFT_BT_STAT_DELAY_8814B)\n#define BIT_CLEAR_BT_STAT_DELAY_8814B(x) ((x) & (~BITS_BT_STAT_DELAY_8814B))\n#define BIT_GET_BT_STAT_DELAY_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_BT_STAT_DELAY_8814B) & BIT_MASK_BT_STAT_DELAY_8814B)\n#define BIT_SET_BT_STAT_DELAY_8814B(x, v)                                      \\\n\t(BIT_CLEAR_BT_STAT_DELAY_8814B(x) | BIT_BT_STAT_DELAY_8814B(v))\n\n#define BIT_SHIFT_BT_TRX_INIT_DETECT_8814B 8\n#define BIT_MASK_BT_TRX_INIT_DETECT_8814B 0xf\n#define BIT_BT_TRX_INIT_DETECT_8814B(x)                                        \\\n\t(((x) & BIT_MASK_BT_TRX_INIT_DETECT_8814B)                             \\\n\t << BIT_SHIFT_BT_TRX_INIT_DETECT_8814B)\n#define BITS_BT_TRX_INIT_DETECT_8814B                                          \\\n\t(BIT_MASK_BT_TRX_INIT_DETECT_8814B                                     \\\n\t << BIT_SHIFT_BT_TRX_INIT_DETECT_8814B)\n#define BIT_CLEAR_BT_TRX_INIT_DETECT_8814B(x)                                  \\\n\t((x) & (~BITS_BT_TRX_INIT_DETECT_8814B))\n#define BIT_GET_BT_TRX_INIT_DETECT_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8814B) &                         \\\n\t BIT_MASK_BT_TRX_INIT_DETECT_8814B)\n#define BIT_SET_BT_TRX_INIT_DETECT_8814B(x, v)                                 \\\n\t(BIT_CLEAR_BT_TRX_INIT_DETECT_8814B(x) |                               \\\n\t BIT_BT_TRX_INIT_DETECT_8814B(v))\n\n#define BIT_SHIFT_BT_PRI_DETECT_TO_8814B 4\n#define BIT_MASK_BT_PRI_DETECT_TO_8814B 0xf\n#define BIT_BT_PRI_DETECT_TO_8814B(x)                                          \\\n\t(((x) & BIT_MASK_BT_PRI_DETECT_TO_8814B)                               \\\n\t << BIT_SHIFT_BT_PRI_DETECT_TO_8814B)\n#define BITS_BT_PRI_DETECT_TO_8814B                                            \\\n\t(BIT_MASK_BT_PRI_DETECT_TO_8814B << BIT_SHIFT_BT_PRI_DETECT_TO_8814B)\n#define BIT_CLEAR_BT_PRI_DETECT_TO_8814B(x)                                    \\\n\t((x) & (~BITS_BT_PRI_DETECT_TO_8814B))\n#define BIT_GET_BT_PRI_DETECT_TO_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8814B) &                           \\\n\t BIT_MASK_BT_PRI_DETECT_TO_8814B)\n#define BIT_SET_BT_PRI_DETECT_TO_8814B(x, v)                                   \\\n\t(BIT_CLEAR_BT_PRI_DETECT_TO_8814B(x) | BIT_BT_PRI_DETECT_TO_8814B(v))\n\n#define BIT_R_GRANTALL_WLMASK_8814B BIT(3)\n#define BIT_STATIS_BT_EN_8814B BIT(2)\n#define BIT_WL_ACT_MASK_ENABLE_8814B BIT(1)\n#define BIT_ENHANCED_BT_8814B BIT(0)\n\n/* 2 REG_BT_ACT_STATISTICS_8814B */\n\n#define BIT_SHIFT_STATIS_BT_HI_RX_8814B 16\n#define BIT_MASK_STATIS_BT_HI_RX_8814B 0xffff\n#define BIT_STATIS_BT_HI_RX_8814B(x)                                           \\\n\t(((x) & BIT_MASK_STATIS_BT_HI_RX_8814B)                                \\\n\t << BIT_SHIFT_STATIS_BT_HI_RX_8814B)\n#define BITS_STATIS_BT_HI_RX_8814B                                             \\\n\t(BIT_MASK_STATIS_BT_HI_RX_8814B << BIT_SHIFT_STATIS_BT_HI_RX_8814B)\n#define BIT_CLEAR_STATIS_BT_HI_RX_8814B(x) ((x) & (~BITS_STATIS_BT_HI_RX_8814B))\n#define BIT_GET_STATIS_BT_HI_RX_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8814B) &                            \\\n\t BIT_MASK_STATIS_BT_HI_RX_8814B)\n#define BIT_SET_STATIS_BT_HI_RX_8814B(x, v)                                    \\\n\t(BIT_CLEAR_STATIS_BT_HI_RX_8814B(x) | BIT_STATIS_BT_HI_RX_8814B(v))\n\n#define BIT_SHIFT_STATIS_BT_HI_TX_8814B 0\n#define BIT_MASK_STATIS_BT_HI_TX_8814B 0xffff\n#define BIT_STATIS_BT_HI_TX_8814B(x)                                           \\\n\t(((x) & BIT_MASK_STATIS_BT_HI_TX_8814B)                                \\\n\t << BIT_SHIFT_STATIS_BT_HI_TX_8814B)\n#define BITS_STATIS_BT_HI_TX_8814B                                             \\\n\t(BIT_MASK_STATIS_BT_HI_TX_8814B << BIT_SHIFT_STATIS_BT_HI_TX_8814B)\n#define BIT_CLEAR_STATIS_BT_HI_TX_8814B(x) ((x) & (~BITS_STATIS_BT_HI_TX_8814B))\n#define BIT_GET_STATIS_BT_HI_TX_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8814B) &                            \\\n\t BIT_MASK_STATIS_BT_HI_TX_8814B)\n#define BIT_SET_STATIS_BT_HI_TX_8814B(x, v)                                    \\\n\t(BIT_CLEAR_STATIS_BT_HI_TX_8814B(x) | BIT_STATIS_BT_HI_TX_8814B(v))\n\n/* 2 REG_BT_ACT_STATISTICS_1_8814B */\n\n#define BIT_SHIFT_STATIS_BT_LO_RX_1_8814B 16\n#define BIT_MASK_STATIS_BT_LO_RX_1_8814B 0xffff\n#define BIT_STATIS_BT_LO_RX_1_8814B(x)                                         \\\n\t(((x) & BIT_MASK_STATIS_BT_LO_RX_1_8814B)                              \\\n\t << BIT_SHIFT_STATIS_BT_LO_RX_1_8814B)\n#define BITS_STATIS_BT_LO_RX_1_8814B                                           \\\n\t(BIT_MASK_STATIS_BT_LO_RX_1_8814B << BIT_SHIFT_STATIS_BT_LO_RX_1_8814B)\n#define BIT_CLEAR_STATIS_BT_LO_RX_1_8814B(x)                                   \\\n\t((x) & (~BITS_STATIS_BT_LO_RX_1_8814B))\n#define BIT_GET_STATIS_BT_LO_RX_1_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8814B) &                          \\\n\t BIT_MASK_STATIS_BT_LO_RX_1_8814B)\n#define BIT_SET_STATIS_BT_LO_RX_1_8814B(x, v)                                  \\\n\t(BIT_CLEAR_STATIS_BT_LO_RX_1_8814B(x) | BIT_STATIS_BT_LO_RX_1_8814B(v))\n\n#define BIT_SHIFT_STATIS_BT_LO_TX_1_8814B 0\n#define BIT_MASK_STATIS_BT_LO_TX_1_8814B 0xffff\n#define BIT_STATIS_BT_LO_TX_1_8814B(x)                                         \\\n\t(((x) & BIT_MASK_STATIS_BT_LO_TX_1_8814B)                              \\\n\t << BIT_SHIFT_STATIS_BT_LO_TX_1_8814B)\n#define BITS_STATIS_BT_LO_TX_1_8814B                                           \\\n\t(BIT_MASK_STATIS_BT_LO_TX_1_8814B << BIT_SHIFT_STATIS_BT_LO_TX_1_8814B)\n#define BIT_CLEAR_STATIS_BT_LO_TX_1_8814B(x)                                   \\\n\t((x) & (~BITS_STATIS_BT_LO_TX_1_8814B))\n#define BIT_GET_STATIS_BT_LO_TX_1_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8814B) &                          \\\n\t BIT_MASK_STATIS_BT_LO_TX_1_8814B)\n#define BIT_SET_STATIS_BT_LO_TX_1_8814B(x, v)                                  \\\n\t(BIT_CLEAR_STATIS_BT_LO_TX_1_8814B(x) | BIT_STATIS_BT_LO_TX_1_8814B(v))\n\n/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8814B */\n\n#define BIT_SHIFT_R_BT_CMD_RPT_8814B 16\n#define BIT_MASK_R_BT_CMD_RPT_8814B 0xffff\n#define BIT_R_BT_CMD_RPT_8814B(x)                                              \\\n\t(((x) & BIT_MASK_R_BT_CMD_RPT_8814B) << BIT_SHIFT_R_BT_CMD_RPT_8814B)\n#define BITS_R_BT_CMD_RPT_8814B                                                \\\n\t(BIT_MASK_R_BT_CMD_RPT_8814B << BIT_SHIFT_R_BT_CMD_RPT_8814B)\n#define BIT_CLEAR_R_BT_CMD_RPT_8814B(x) ((x) & (~BITS_R_BT_CMD_RPT_8814B))\n#define BIT_GET_R_BT_CMD_RPT_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_BT_CMD_RPT_8814B) & BIT_MASK_R_BT_CMD_RPT_8814B)\n#define BIT_SET_R_BT_CMD_RPT_8814B(x, v)                                       \\\n\t(BIT_CLEAR_R_BT_CMD_RPT_8814B(x) | BIT_R_BT_CMD_RPT_8814B(v))\n\n#define BIT_SHIFT_R_RPT_FROM_BT_8814B 8\n#define BIT_MASK_R_RPT_FROM_BT_8814B 0xff\n#define BIT_R_RPT_FROM_BT_8814B(x)                                             \\\n\t(((x) & BIT_MASK_R_RPT_FROM_BT_8814B) << BIT_SHIFT_R_RPT_FROM_BT_8814B)\n#define BITS_R_RPT_FROM_BT_8814B                                               \\\n\t(BIT_MASK_R_RPT_FROM_BT_8814B << BIT_SHIFT_R_RPT_FROM_BT_8814B)\n#define BIT_CLEAR_R_RPT_FROM_BT_8814B(x) ((x) & (~BITS_R_RPT_FROM_BT_8814B))\n#define BIT_GET_R_RPT_FROM_BT_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_RPT_FROM_BT_8814B) & BIT_MASK_R_RPT_FROM_BT_8814B)\n#define BIT_SET_R_RPT_FROM_BT_8814B(x, v)                                      \\\n\t(BIT_CLEAR_R_RPT_FROM_BT_8814B(x) | BIT_R_RPT_FROM_BT_8814B(v))\n\n#define BIT_SHIFT_BT_HID_ISR_SET_8814B 6\n#define BIT_MASK_BT_HID_ISR_SET_8814B 0x3\n#define BIT_BT_HID_ISR_SET_8814B(x)                                            \\\n\t(((x) & BIT_MASK_BT_HID_ISR_SET_8814B)                                 \\\n\t << BIT_SHIFT_BT_HID_ISR_SET_8814B)\n#define BITS_BT_HID_ISR_SET_8814B                                              \\\n\t(BIT_MASK_BT_HID_ISR_SET_8814B << BIT_SHIFT_BT_HID_ISR_SET_8814B)\n#define BIT_CLEAR_BT_HID_ISR_SET_8814B(x) ((x) & (~BITS_BT_HID_ISR_SET_8814B))\n#define BIT_GET_BT_HID_ISR_SET_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_BT_HID_ISR_SET_8814B) &                             \\\n\t BIT_MASK_BT_HID_ISR_SET_8814B)\n#define BIT_SET_BT_HID_ISR_SET_8814B(x, v)                                     \\\n\t(BIT_CLEAR_BT_HID_ISR_SET_8814B(x) | BIT_BT_HID_ISR_SET_8814B(v))\n\n#define BIT_TDMA_BT_START_NOTIFY_8814B BIT(5)\n#define BIT_ENABLE_TDMA_FW_MODE_8814B BIT(4)\n#define BIT_ENABLE_PTA_TDMA_MODE_8814B BIT(3)\n#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8814B BIT(2)\n#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8814B BIT(1)\n#define BIT_RTK_BT_ENABLE_8814B BIT(0)\n\n/* 2 REG_BT_STATUS_REPORT_REGISTER_8814B */\n\n#define BIT_SHIFT_BT_PROFILE_8814B 24\n#define BIT_MASK_BT_PROFILE_8814B 0xff\n#define BIT_BT_PROFILE_8814B(x)                                                \\\n\t(((x) & BIT_MASK_BT_PROFILE_8814B) << BIT_SHIFT_BT_PROFILE_8814B)\n#define BITS_BT_PROFILE_8814B                                                  \\\n\t(BIT_MASK_BT_PROFILE_8814B << BIT_SHIFT_BT_PROFILE_8814B)\n#define BIT_CLEAR_BT_PROFILE_8814B(x) ((x) & (~BITS_BT_PROFILE_8814B))\n#define BIT_GET_BT_PROFILE_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_BT_PROFILE_8814B) & BIT_MASK_BT_PROFILE_8814B)\n#define BIT_SET_BT_PROFILE_8814B(x, v)                                         \\\n\t(BIT_CLEAR_BT_PROFILE_8814B(x) | BIT_BT_PROFILE_8814B(v))\n\n#define BIT_SHIFT_BT_POWER_8814B 16\n#define BIT_MASK_BT_POWER_8814B 0xff\n#define BIT_BT_POWER_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_BT_POWER_8814B) << BIT_SHIFT_BT_POWER_8814B)\n#define BITS_BT_POWER_8814B                                                    \\\n\t(BIT_MASK_BT_POWER_8814B << BIT_SHIFT_BT_POWER_8814B)\n#define BIT_CLEAR_BT_POWER_8814B(x) ((x) & (~BITS_BT_POWER_8814B))\n#define BIT_GET_BT_POWER_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_BT_POWER_8814B) & BIT_MASK_BT_POWER_8814B)\n#define BIT_SET_BT_POWER_8814B(x, v)                                           \\\n\t(BIT_CLEAR_BT_POWER_8814B(x) | BIT_BT_POWER_8814B(v))\n\n#define BIT_SHIFT_BT_PREDECT_STATUS_8814B 8\n#define BIT_MASK_BT_PREDECT_STATUS_8814B 0xff\n#define BIT_BT_PREDECT_STATUS_8814B(x)                                         \\\n\t(((x) & BIT_MASK_BT_PREDECT_STATUS_8814B)                              \\\n\t << BIT_SHIFT_BT_PREDECT_STATUS_8814B)\n#define BITS_BT_PREDECT_STATUS_8814B                                           \\\n\t(BIT_MASK_BT_PREDECT_STATUS_8814B << BIT_SHIFT_BT_PREDECT_STATUS_8814B)\n#define BIT_CLEAR_BT_PREDECT_STATUS_8814B(x)                                   \\\n\t((x) & (~BITS_BT_PREDECT_STATUS_8814B))\n#define BIT_GET_BT_PREDECT_STATUS_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8814B) &                          \\\n\t BIT_MASK_BT_PREDECT_STATUS_8814B)\n#define BIT_SET_BT_PREDECT_STATUS_8814B(x, v)                                  \\\n\t(BIT_CLEAR_BT_PREDECT_STATUS_8814B(x) | BIT_BT_PREDECT_STATUS_8814B(v))\n\n#define BIT_SHIFT_BT_CMD_INFO_8814B 0\n#define BIT_MASK_BT_CMD_INFO_8814B 0xff\n#define BIT_BT_CMD_INFO_8814B(x)                                               \\\n\t(((x) & BIT_MASK_BT_CMD_INFO_8814B) << BIT_SHIFT_BT_CMD_INFO_8814B)\n#define BITS_BT_CMD_INFO_8814B                                                 \\\n\t(BIT_MASK_BT_CMD_INFO_8814B << BIT_SHIFT_BT_CMD_INFO_8814B)\n#define BIT_CLEAR_BT_CMD_INFO_8814B(x) ((x) & (~BITS_BT_CMD_INFO_8814B))\n#define BIT_GET_BT_CMD_INFO_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_BT_CMD_INFO_8814B) & BIT_MASK_BT_CMD_INFO_8814B)\n#define BIT_SET_BT_CMD_INFO_8814B(x, v)                                        \\\n\t(BIT_CLEAR_BT_CMD_INFO_8814B(x) | BIT_BT_CMD_INFO_8814B(v))\n\n/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8814B */\n#define BIT_EN_MAC_NULL_PKT_NOTIFY_8814B BIT(31)\n#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8814B BIT(30)\n#define BIT_EN_BT_STSTUS_RPT_8814B BIT(29)\n#define BIT_EN_BT_POWER_8814B BIT(28)\n#define BIT_EN_BT_CHANNEL_8814B BIT(27)\n#define BIT_EN_BT_SLOT_CHANGE_8814B BIT(26)\n#define BIT_EN_BT_PROFILE_OR_HID_8814B BIT(25)\n#define BIT_WLAN_RPT_NOTIFY_8814B BIT(24)\n\n#define BIT_SHIFT_WLAN_RPT_DATA_8814B 16\n#define BIT_MASK_WLAN_RPT_DATA_8814B 0xff\n#define BIT_WLAN_RPT_DATA_8814B(x)                                             \\\n\t(((x) & BIT_MASK_WLAN_RPT_DATA_8814B) << BIT_SHIFT_WLAN_RPT_DATA_8814B)\n#define BITS_WLAN_RPT_DATA_8814B                                               \\\n\t(BIT_MASK_WLAN_RPT_DATA_8814B << BIT_SHIFT_WLAN_RPT_DATA_8814B)\n#define BIT_CLEAR_WLAN_RPT_DATA_8814B(x) ((x) & (~BITS_WLAN_RPT_DATA_8814B))\n#define BIT_GET_WLAN_RPT_DATA_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_WLAN_RPT_DATA_8814B) & BIT_MASK_WLAN_RPT_DATA_8814B)\n#define BIT_SET_WLAN_RPT_DATA_8814B(x, v)                                      \\\n\t(BIT_CLEAR_WLAN_RPT_DATA_8814B(x) | BIT_WLAN_RPT_DATA_8814B(v))\n\n#define BIT_SHIFT_CMD_ID_8814B 8\n#define BIT_MASK_CMD_ID_8814B 0xff\n#define BIT_CMD_ID_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_CMD_ID_8814B) << BIT_SHIFT_CMD_ID_8814B)\n#define BITS_CMD_ID_8814B (BIT_MASK_CMD_ID_8814B << BIT_SHIFT_CMD_ID_8814B)\n#define BIT_CLEAR_CMD_ID_8814B(x) ((x) & (~BITS_CMD_ID_8814B))\n#define BIT_GET_CMD_ID_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_CMD_ID_8814B) & BIT_MASK_CMD_ID_8814B)\n#define BIT_SET_CMD_ID_8814B(x, v)                                             \\\n\t(BIT_CLEAR_CMD_ID_8814B(x) | BIT_CMD_ID_8814B(v))\n\n#define BIT_SHIFT_BT_DATA_8814B 0\n#define BIT_MASK_BT_DATA_8814B 0xff\n#define BIT_BT_DATA_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_BT_DATA_8814B) << BIT_SHIFT_BT_DATA_8814B)\n#define BITS_BT_DATA_8814B (BIT_MASK_BT_DATA_8814B << BIT_SHIFT_BT_DATA_8814B)\n#define BIT_CLEAR_BT_DATA_8814B(x) ((x) & (~BITS_BT_DATA_8814B))\n#define BIT_GET_BT_DATA_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_BT_DATA_8814B) & BIT_MASK_BT_DATA_8814B)\n#define BIT_SET_BT_DATA_8814B(x, v)                                            \\\n\t(BIT_CLEAR_BT_DATA_8814B(x) | BIT_BT_DATA_8814B(v))\n\n/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8814B */\n\n#define BIT_SHIFT_WLAN_RPT_TO_8814B 0\n#define BIT_MASK_WLAN_RPT_TO_8814B 0xff\n#define BIT_WLAN_RPT_TO_8814B(x)                                               \\\n\t(((x) & BIT_MASK_WLAN_RPT_TO_8814B) << BIT_SHIFT_WLAN_RPT_TO_8814B)\n#define BITS_WLAN_RPT_TO_8814B                                                 \\\n\t(BIT_MASK_WLAN_RPT_TO_8814B << BIT_SHIFT_WLAN_RPT_TO_8814B)\n#define BIT_CLEAR_WLAN_RPT_TO_8814B(x) ((x) & (~BITS_WLAN_RPT_TO_8814B))\n#define BIT_GET_WLAN_RPT_TO_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_WLAN_RPT_TO_8814B) & BIT_MASK_WLAN_RPT_TO_8814B)\n#define BIT_SET_WLAN_RPT_TO_8814B(x, v)                                        \\\n\t(BIT_CLEAR_WLAN_RPT_TO_8814B(x) | BIT_WLAN_RPT_TO_8814B(v))\n\n/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8814B */\n\n#define BIT_SHIFT_ISOLATION_CHK_0_8814B 1\n#define BIT_MASK_ISOLATION_CHK_0_8814B 0x7fffff\n#define BIT_ISOLATION_CHK_0_8814B(x)                                           \\\n\t(((x) & BIT_MASK_ISOLATION_CHK_0_8814B)                                \\\n\t << BIT_SHIFT_ISOLATION_CHK_0_8814B)\n#define BITS_ISOLATION_CHK_0_8814B                                             \\\n\t(BIT_MASK_ISOLATION_CHK_0_8814B << BIT_SHIFT_ISOLATION_CHK_0_8814B)\n#define BIT_CLEAR_ISOLATION_CHK_0_8814B(x) ((x) & (~BITS_ISOLATION_CHK_0_8814B))\n#define BIT_GET_ISOLATION_CHK_0_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_ISOLATION_CHK_0_8814B) &                            \\\n\t BIT_MASK_ISOLATION_CHK_0_8814B)\n#define BIT_SET_ISOLATION_CHK_0_8814B(x, v)                                    \\\n\t(BIT_CLEAR_ISOLATION_CHK_0_8814B(x) | BIT_ISOLATION_CHK_0_8814B(v))\n\n#define BIT_ISOLATION_EN_8814B BIT(0)\n\n/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8814B */\n\n#define BIT_SHIFT_ISOLATION_CHK_1_8814B 0\n#define BIT_MASK_ISOLATION_CHK_1_8814B 0xffffffffL\n#define BIT_ISOLATION_CHK_1_8814B(x)                                           \\\n\t(((x) & BIT_MASK_ISOLATION_CHK_1_8814B)                                \\\n\t << BIT_SHIFT_ISOLATION_CHK_1_8814B)\n#define BITS_ISOLATION_CHK_1_8814B                                             \\\n\t(BIT_MASK_ISOLATION_CHK_1_8814B << BIT_SHIFT_ISOLATION_CHK_1_8814B)\n#define BIT_CLEAR_ISOLATION_CHK_1_8814B(x) ((x) & (~BITS_ISOLATION_CHK_1_8814B))\n#define BIT_GET_ISOLATION_CHK_1_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_ISOLATION_CHK_1_8814B) &                            \\\n\t BIT_MASK_ISOLATION_CHK_1_8814B)\n#define BIT_SET_ISOLATION_CHK_1_8814B(x, v)                                    \\\n\t(BIT_CLEAR_ISOLATION_CHK_1_8814B(x) | BIT_ISOLATION_CHK_1_8814B(v))\n\n/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8814B */\n\n#define BIT_SHIFT_ISOLATION_CHK_2_8814B 0\n#define BIT_MASK_ISOLATION_CHK_2_8814B 0xffffff\n#define BIT_ISOLATION_CHK_2_8814B(x)                                           \\\n\t(((x) & BIT_MASK_ISOLATION_CHK_2_8814B)                                \\\n\t << BIT_SHIFT_ISOLATION_CHK_2_8814B)\n#define BITS_ISOLATION_CHK_2_8814B                                             \\\n\t(BIT_MASK_ISOLATION_CHK_2_8814B << BIT_SHIFT_ISOLATION_CHK_2_8814B)\n#define BIT_CLEAR_ISOLATION_CHK_2_8814B(x) ((x) & (~BITS_ISOLATION_CHK_2_8814B))\n#define BIT_GET_ISOLATION_CHK_2_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_ISOLATION_CHK_2_8814B) &                            \\\n\t BIT_MASK_ISOLATION_CHK_2_8814B)\n#define BIT_SET_ISOLATION_CHK_2_8814B(x, v)                                    \\\n\t(BIT_CLEAR_ISOLATION_CHK_2_8814B(x) | BIT_ISOLATION_CHK_2_8814B(v))\n\n/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8814B */\n#define BIT_BT_HID_ISR_8814B BIT(7)\n#define BIT_BT_QUERY_ISR_8814B BIT(6)\n#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8814B BIT(5)\n#define BIT_WLAN_RPT_ISR_8814B BIT(4)\n#define BIT_BT_POWER_ISR_8814B BIT(3)\n#define BIT_BT_CHANNEL_ISR_8814B BIT(2)\n#define BIT_BT_SLOT_CHANGE_ISR_8814B BIT(1)\n#define BIT_BT_PROFILE_ISR_8814B BIT(0)\n\n/* 2 REG_BT_TDMA_TIME_REGISTER_8814B */\n\n#define BIT_SHIFT_BT_TIME_8814B 6\n#define BIT_MASK_BT_TIME_8814B 0x3ffffff\n#define BIT_BT_TIME_8814B(x)                                                   \\\n\t(((x) & BIT_MASK_BT_TIME_8814B) << BIT_SHIFT_BT_TIME_8814B)\n#define BITS_BT_TIME_8814B (BIT_MASK_BT_TIME_8814B << BIT_SHIFT_BT_TIME_8814B)\n#define BIT_CLEAR_BT_TIME_8814B(x) ((x) & (~BITS_BT_TIME_8814B))\n#define BIT_GET_BT_TIME_8814B(x)                                               \\\n\t(((x) >> BIT_SHIFT_BT_TIME_8814B) & BIT_MASK_BT_TIME_8814B)\n#define BIT_SET_BT_TIME_8814B(x, v)                                            \\\n\t(BIT_CLEAR_BT_TIME_8814B(x) | BIT_BT_TIME_8814B(v))\n\n#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B 0\n#define BIT_MASK_BT_RPT_SAMPLE_RATE_8814B 0x3f\n#define BIT_BT_RPT_SAMPLE_RATE_8814B(x)                                        \\\n\t(((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8814B)                             \\\n\t << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B)\n#define BITS_BT_RPT_SAMPLE_RATE_8814B                                          \\\n\t(BIT_MASK_BT_RPT_SAMPLE_RATE_8814B                                     \\\n\t << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B)\n#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8814B(x)                                  \\\n\t((x) & (~BITS_BT_RPT_SAMPLE_RATE_8814B))\n#define BIT_GET_BT_RPT_SAMPLE_RATE_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B) &                         \\\n\t BIT_MASK_BT_RPT_SAMPLE_RATE_8814B)\n#define BIT_SET_BT_RPT_SAMPLE_RATE_8814B(x, v)                                 \\\n\t(BIT_CLEAR_BT_RPT_SAMPLE_RATE_8814B(x) |                               \\\n\t BIT_BT_RPT_SAMPLE_RATE_8814B(v))\n\n/* 2 REG_BT_ACT_REGISTER_8814B */\n\n#define BIT_SHIFT_BT_EISR_EN_8814B 16\n#define BIT_MASK_BT_EISR_EN_8814B 0xff\n#define BIT_BT_EISR_EN_8814B(x)                                                \\\n\t(((x) & BIT_MASK_BT_EISR_EN_8814B) << BIT_SHIFT_BT_EISR_EN_8814B)\n#define BITS_BT_EISR_EN_8814B                                                  \\\n\t(BIT_MASK_BT_EISR_EN_8814B << BIT_SHIFT_BT_EISR_EN_8814B)\n#define BIT_CLEAR_BT_EISR_EN_8814B(x) ((x) & (~BITS_BT_EISR_EN_8814B))\n#define BIT_GET_BT_EISR_EN_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_BT_EISR_EN_8814B) & BIT_MASK_BT_EISR_EN_8814B)\n#define BIT_SET_BT_EISR_EN_8814B(x, v)                                         \\\n\t(BIT_CLEAR_BT_EISR_EN_8814B(x) | BIT_BT_EISR_EN_8814B(v))\n\n#define BIT_BT_ACT_FALLING_ISR_8814B BIT(10)\n#define BIT_BT_ACT_RISING_ISR_8814B BIT(9)\n#define BIT_TDMA_TO_ISR_8814B BIT(8)\n\n#define BIT_SHIFT_BT_CH_8814B 0\n#define BIT_MASK_BT_CH_8814B 0xff\n#define BIT_BT_CH_8814B(x)                                                     \\\n\t(((x) & BIT_MASK_BT_CH_8814B) << BIT_SHIFT_BT_CH_8814B)\n#define BITS_BT_CH_8814B (BIT_MASK_BT_CH_8814B << BIT_SHIFT_BT_CH_8814B)\n#define BIT_CLEAR_BT_CH_8814B(x) ((x) & (~BITS_BT_CH_8814B))\n#define BIT_GET_BT_CH_8814B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_BT_CH_8814B) & BIT_MASK_BT_CH_8814B)\n#define BIT_SET_BT_CH_8814B(x, v)                                              \\\n\t(BIT_CLEAR_BT_CH_8814B(x) | BIT_BT_CH_8814B(v))\n\n/* 2 REG_OBFF_CTRL_BASIC_8814B */\n#define BIT_OBFF_EN_V1_8814B BIT(31)\n\n#define BIT_SHIFT_OBFF_STATE_V1_8814B 28\n#define BIT_MASK_OBFF_STATE_V1_8814B 0x3\n#define BIT_OBFF_STATE_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_OBFF_STATE_V1_8814B) << BIT_SHIFT_OBFF_STATE_V1_8814B)\n#define BITS_OBFF_STATE_V1_8814B                                               \\\n\t(BIT_MASK_OBFF_STATE_V1_8814B << BIT_SHIFT_OBFF_STATE_V1_8814B)\n#define BIT_CLEAR_OBFF_STATE_V1_8814B(x) ((x) & (~BITS_OBFF_STATE_V1_8814B))\n#define BIT_GET_OBFF_STATE_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_OBFF_STATE_V1_8814B) & BIT_MASK_OBFF_STATE_V1_8814B)\n#define BIT_SET_OBFF_STATE_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_OBFF_STATE_V1_8814B(x) | BIT_OBFF_STATE_V1_8814B(v))\n\n#define BIT_OBFF_ACT_RXDMA_EN_8814B BIT(27)\n#define BIT_OBFF_BLOCK_INT_EN_8814B BIT(26)\n#define BIT_OBFF_AUTOACT_EN_8814B BIT(25)\n#define BIT_OBFF_AUTOIDLE_EN_8814B BIT(24)\n\n#define BIT_SHIFT_WAKE_MAX_PLS_8814B 20\n#define BIT_MASK_WAKE_MAX_PLS_8814B 0x7\n#define BIT_WAKE_MAX_PLS_8814B(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MAX_PLS_8814B) << BIT_SHIFT_WAKE_MAX_PLS_8814B)\n#define BITS_WAKE_MAX_PLS_8814B                                                \\\n\t(BIT_MASK_WAKE_MAX_PLS_8814B << BIT_SHIFT_WAKE_MAX_PLS_8814B)\n#define BIT_CLEAR_WAKE_MAX_PLS_8814B(x) ((x) & (~BITS_WAKE_MAX_PLS_8814B))\n#define BIT_GET_WAKE_MAX_PLS_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MAX_PLS_8814B) & BIT_MASK_WAKE_MAX_PLS_8814B)\n#define BIT_SET_WAKE_MAX_PLS_8814B(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MAX_PLS_8814B(x) | BIT_WAKE_MAX_PLS_8814B(v))\n\n#define BIT_SHIFT_WAKE_MIN_PLS_8814B 16\n#define BIT_MASK_WAKE_MIN_PLS_8814B 0x7\n#define BIT_WAKE_MIN_PLS_8814B(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MIN_PLS_8814B) << BIT_SHIFT_WAKE_MIN_PLS_8814B)\n#define BITS_WAKE_MIN_PLS_8814B                                                \\\n\t(BIT_MASK_WAKE_MIN_PLS_8814B << BIT_SHIFT_WAKE_MIN_PLS_8814B)\n#define BIT_CLEAR_WAKE_MIN_PLS_8814B(x) ((x) & (~BITS_WAKE_MIN_PLS_8814B))\n#define BIT_GET_WAKE_MIN_PLS_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MIN_PLS_8814B) & BIT_MASK_WAKE_MIN_PLS_8814B)\n#define BIT_SET_WAKE_MIN_PLS_8814B(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MIN_PLS_8814B(x) | BIT_WAKE_MIN_PLS_8814B(v))\n\n#define BIT_SHIFT_WAKE_MAX_F2F_8814B 12\n#define BIT_MASK_WAKE_MAX_F2F_8814B 0x7\n#define BIT_WAKE_MAX_F2F_8814B(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MAX_F2F_8814B) << BIT_SHIFT_WAKE_MAX_F2F_8814B)\n#define BITS_WAKE_MAX_F2F_8814B                                                \\\n\t(BIT_MASK_WAKE_MAX_F2F_8814B << BIT_SHIFT_WAKE_MAX_F2F_8814B)\n#define BIT_CLEAR_WAKE_MAX_F2F_8814B(x) ((x) & (~BITS_WAKE_MAX_F2F_8814B))\n#define BIT_GET_WAKE_MAX_F2F_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MAX_F2F_8814B) & BIT_MASK_WAKE_MAX_F2F_8814B)\n#define BIT_SET_WAKE_MAX_F2F_8814B(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MAX_F2F_8814B(x) | BIT_WAKE_MAX_F2F_8814B(v))\n\n#define BIT_SHIFT_WAKE_MIN_F2F_8814B 8\n#define BIT_MASK_WAKE_MIN_F2F_8814B 0x7\n#define BIT_WAKE_MIN_F2F_8814B(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MIN_F2F_8814B) << BIT_SHIFT_WAKE_MIN_F2F_8814B)\n#define BITS_WAKE_MIN_F2F_8814B                                                \\\n\t(BIT_MASK_WAKE_MIN_F2F_8814B << BIT_SHIFT_WAKE_MIN_F2F_8814B)\n#define BIT_CLEAR_WAKE_MIN_F2F_8814B(x) ((x) & (~BITS_WAKE_MIN_F2F_8814B))\n#define BIT_GET_WAKE_MIN_F2F_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MIN_F2F_8814B) & BIT_MASK_WAKE_MIN_F2F_8814B)\n#define BIT_SET_WAKE_MIN_F2F_8814B(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MIN_F2F_8814B(x) | BIT_WAKE_MIN_F2F_8814B(v))\n\n#define BIT_APP_CPU_ACT_V1_8814B BIT(3)\n#define BIT_APP_OBFF_V1_8814B BIT(2)\n#define BIT_APP_IDLE_V1_8814B BIT(1)\n#define BIT_APP_INIT_V1_8814B BIT(0)\n\n/* 2 REG_OBFF_CTRL2_TIMER_8814B */\n\n#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B 24\n#define BIT_MASK_RX_HIGH_TIMER_IDX_8814B 0x7\n#define BIT_RX_HIGH_TIMER_IDX_8814B(x)                                         \\\n\t(((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8814B)                              \\\n\t << BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B)\n#define BITS_RX_HIGH_TIMER_IDX_8814B                                           \\\n\t(BIT_MASK_RX_HIGH_TIMER_IDX_8814B << BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B)\n#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8814B(x)                                   \\\n\t((x) & (~BITS_RX_HIGH_TIMER_IDX_8814B))\n#define BIT_GET_RX_HIGH_TIMER_IDX_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B) &                          \\\n\t BIT_MASK_RX_HIGH_TIMER_IDX_8814B)\n#define BIT_SET_RX_HIGH_TIMER_IDX_8814B(x, v)                                  \\\n\t(BIT_CLEAR_RX_HIGH_TIMER_IDX_8814B(x) | BIT_RX_HIGH_TIMER_IDX_8814B(v))\n\n#define BIT_SHIFT_RX_MED_TIMER_IDX_8814B 16\n#define BIT_MASK_RX_MED_TIMER_IDX_8814B 0x7\n#define BIT_RX_MED_TIMER_IDX_8814B(x)                                          \\\n\t(((x) & BIT_MASK_RX_MED_TIMER_IDX_8814B)                               \\\n\t << BIT_SHIFT_RX_MED_TIMER_IDX_8814B)\n#define BITS_RX_MED_TIMER_IDX_8814B                                            \\\n\t(BIT_MASK_RX_MED_TIMER_IDX_8814B << BIT_SHIFT_RX_MED_TIMER_IDX_8814B)\n#define BIT_CLEAR_RX_MED_TIMER_IDX_8814B(x)                                    \\\n\t((x) & (~BITS_RX_MED_TIMER_IDX_8814B))\n#define BIT_GET_RX_MED_TIMER_IDX_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8814B) &                           \\\n\t BIT_MASK_RX_MED_TIMER_IDX_8814B)\n#define BIT_SET_RX_MED_TIMER_IDX_8814B(x, v)                                   \\\n\t(BIT_CLEAR_RX_MED_TIMER_IDX_8814B(x) | BIT_RX_MED_TIMER_IDX_8814B(v))\n\n#define BIT_SHIFT_RX_LOW_TIMER_IDX_8814B 8\n#define BIT_MASK_RX_LOW_TIMER_IDX_8814B 0x7\n#define BIT_RX_LOW_TIMER_IDX_8814B(x)                                          \\\n\t(((x) & BIT_MASK_RX_LOW_TIMER_IDX_8814B)                               \\\n\t << BIT_SHIFT_RX_LOW_TIMER_IDX_8814B)\n#define BITS_RX_LOW_TIMER_IDX_8814B                                            \\\n\t(BIT_MASK_RX_LOW_TIMER_IDX_8814B << BIT_SHIFT_RX_LOW_TIMER_IDX_8814B)\n#define BIT_CLEAR_RX_LOW_TIMER_IDX_8814B(x)                                    \\\n\t((x) & (~BITS_RX_LOW_TIMER_IDX_8814B))\n#define BIT_GET_RX_LOW_TIMER_IDX_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8814B) &                           \\\n\t BIT_MASK_RX_LOW_TIMER_IDX_8814B)\n#define BIT_SET_RX_LOW_TIMER_IDX_8814B(x, v)                                   \\\n\t(BIT_CLEAR_RX_LOW_TIMER_IDX_8814B(x) | BIT_RX_LOW_TIMER_IDX_8814B(v))\n\n#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B 0\n#define BIT_MASK_OBFF_INT_TIMER_IDX_8814B 0x7\n#define BIT_OBFF_INT_TIMER_IDX_8814B(x)                                        \\\n\t(((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8814B)                             \\\n\t << BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B)\n#define BITS_OBFF_INT_TIMER_IDX_8814B                                          \\\n\t(BIT_MASK_OBFF_INT_TIMER_IDX_8814B                                     \\\n\t << BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B)\n#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8814B(x)                                  \\\n\t((x) & (~BITS_OBFF_INT_TIMER_IDX_8814B))\n#define BIT_GET_OBFF_INT_TIMER_IDX_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B) &                         \\\n\t BIT_MASK_OBFF_INT_TIMER_IDX_8814B)\n#define BIT_SET_OBFF_INT_TIMER_IDX_8814B(x, v)                                 \\\n\t(BIT_CLEAR_OBFF_INT_TIMER_IDX_8814B(x) |                               \\\n\t BIT_OBFF_INT_TIMER_IDX_8814B(v))\n\n/* 2 REG_LTR_CTRL_BASIC_8814B */\n#define BIT_LTR_EN_V1_8814B BIT(31)\n#define BIT_LTR_HW_EN_V1_8814B BIT(30)\n#define BIT_LRT_ACT_CTS_EN_8814B BIT(29)\n#define BIT_LTR_ACT_RXPKT_EN_8814B BIT(28)\n#define BIT_LTR_ACT_RXDMA_EN_8814B BIT(27)\n#define BIT_LTR_IDLE_NO_SNOOP_8814B BIT(26)\n#define BIT_SPDUP_MGTPKT_8814B BIT(25)\n#define BIT_RX_AGG_EN_8814B BIT(24)\n#define BIT_APP_LTR_ACT_8814B BIT(23)\n#define BIT_APP_LTR_IDLE_8814B BIT(22)\n\n#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B 20\n#define BIT_MASK_HIGH_RATE_TRIG_SEL_8814B 0x3\n#define BIT_HIGH_RATE_TRIG_SEL_8814B(x)                                        \\\n\t(((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8814B)                             \\\n\t << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B)\n#define BITS_HIGH_RATE_TRIG_SEL_8814B                                          \\\n\t(BIT_MASK_HIGH_RATE_TRIG_SEL_8814B                                     \\\n\t << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B)\n#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8814B(x)                                  \\\n\t((x) & (~BITS_HIGH_RATE_TRIG_SEL_8814B))\n#define BIT_GET_HIGH_RATE_TRIG_SEL_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B) &                         \\\n\t BIT_MASK_HIGH_RATE_TRIG_SEL_8814B)\n#define BIT_SET_HIGH_RATE_TRIG_SEL_8814B(x, v)                                 \\\n\t(BIT_CLEAR_HIGH_RATE_TRIG_SEL_8814B(x) |                               \\\n\t BIT_HIGH_RATE_TRIG_SEL_8814B(v))\n\n#define BIT_SHIFT_MED_RATE_TRIG_SEL_8814B 18\n#define BIT_MASK_MED_RATE_TRIG_SEL_8814B 0x3\n#define BIT_MED_RATE_TRIG_SEL_8814B(x)                                         \\\n\t(((x) & BIT_MASK_MED_RATE_TRIG_SEL_8814B)                              \\\n\t << BIT_SHIFT_MED_RATE_TRIG_SEL_8814B)\n#define BITS_MED_RATE_TRIG_SEL_8814B                                           \\\n\t(BIT_MASK_MED_RATE_TRIG_SEL_8814B << BIT_SHIFT_MED_RATE_TRIG_SEL_8814B)\n#define BIT_CLEAR_MED_RATE_TRIG_SEL_8814B(x)                                   \\\n\t((x) & (~BITS_MED_RATE_TRIG_SEL_8814B))\n#define BIT_GET_MED_RATE_TRIG_SEL_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8814B) &                          \\\n\t BIT_MASK_MED_RATE_TRIG_SEL_8814B)\n#define BIT_SET_MED_RATE_TRIG_SEL_8814B(x, v)                                  \\\n\t(BIT_CLEAR_MED_RATE_TRIG_SEL_8814B(x) | BIT_MED_RATE_TRIG_SEL_8814B(v))\n\n#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B 16\n#define BIT_MASK_LOW_RATE_TRIG_SEL_8814B 0x3\n#define BIT_LOW_RATE_TRIG_SEL_8814B(x)                                         \\\n\t(((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8814B)                              \\\n\t << BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B)\n#define BITS_LOW_RATE_TRIG_SEL_8814B                                           \\\n\t(BIT_MASK_LOW_RATE_TRIG_SEL_8814B << BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B)\n#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8814B(x)                                   \\\n\t((x) & (~BITS_LOW_RATE_TRIG_SEL_8814B))\n#define BIT_GET_LOW_RATE_TRIG_SEL_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B) &                          \\\n\t BIT_MASK_LOW_RATE_TRIG_SEL_8814B)\n#define BIT_SET_LOW_RATE_TRIG_SEL_8814B(x, v)                                  \\\n\t(BIT_CLEAR_LOW_RATE_TRIG_SEL_8814B(x) | BIT_LOW_RATE_TRIG_SEL_8814B(v))\n\n#define BIT_SHIFT_HIGH_RATE_BD_IDX_8814B 8\n#define BIT_MASK_HIGH_RATE_BD_IDX_8814B 0x7f\n#define BIT_HIGH_RATE_BD_IDX_8814B(x)                                          \\\n\t(((x) & BIT_MASK_HIGH_RATE_BD_IDX_8814B)                               \\\n\t << BIT_SHIFT_HIGH_RATE_BD_IDX_8814B)\n#define BITS_HIGH_RATE_BD_IDX_8814B                                            \\\n\t(BIT_MASK_HIGH_RATE_BD_IDX_8814B << BIT_SHIFT_HIGH_RATE_BD_IDX_8814B)\n#define BIT_CLEAR_HIGH_RATE_BD_IDX_8814B(x)                                    \\\n\t((x) & (~BITS_HIGH_RATE_BD_IDX_8814B))\n#define BIT_GET_HIGH_RATE_BD_IDX_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8814B) &                           \\\n\t BIT_MASK_HIGH_RATE_BD_IDX_8814B)\n#define BIT_SET_HIGH_RATE_BD_IDX_8814B(x, v)                                   \\\n\t(BIT_CLEAR_HIGH_RATE_BD_IDX_8814B(x) | BIT_HIGH_RATE_BD_IDX_8814B(v))\n\n#define BIT_SHIFT_LOW_RATE_BD_IDX_8814B 0\n#define BIT_MASK_LOW_RATE_BD_IDX_8814B 0x7f\n#define BIT_LOW_RATE_BD_IDX_8814B(x)                                           \\\n\t(((x) & BIT_MASK_LOW_RATE_BD_IDX_8814B)                                \\\n\t << BIT_SHIFT_LOW_RATE_BD_IDX_8814B)\n#define BITS_LOW_RATE_BD_IDX_8814B                                             \\\n\t(BIT_MASK_LOW_RATE_BD_IDX_8814B << BIT_SHIFT_LOW_RATE_BD_IDX_8814B)\n#define BIT_CLEAR_LOW_RATE_BD_IDX_8814B(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8814B))\n#define BIT_GET_LOW_RATE_BD_IDX_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8814B) &                            \\\n\t BIT_MASK_LOW_RATE_BD_IDX_8814B)\n#define BIT_SET_LOW_RATE_BD_IDX_8814B(x, v)                                    \\\n\t(BIT_CLEAR_LOW_RATE_BD_IDX_8814B(x) | BIT_LOW_RATE_BD_IDX_8814B(v))\n\n/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8814B */\n\n#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B 24\n#define BIT_MASK_RX_EMPTY_TIMER_IDX_8814B 0x7\n#define BIT_RX_EMPTY_TIMER_IDX_8814B(x)                                        \\\n\t(((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8814B)                             \\\n\t << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B)\n#define BITS_RX_EMPTY_TIMER_IDX_8814B                                          \\\n\t(BIT_MASK_RX_EMPTY_TIMER_IDX_8814B                                     \\\n\t << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B)\n#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8814B(x)                                  \\\n\t((x) & (~BITS_RX_EMPTY_TIMER_IDX_8814B))\n#define BIT_GET_RX_EMPTY_TIMER_IDX_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B) &                         \\\n\t BIT_MASK_RX_EMPTY_TIMER_IDX_8814B)\n#define BIT_SET_RX_EMPTY_TIMER_IDX_8814B(x, v)                                 \\\n\t(BIT_CLEAR_RX_EMPTY_TIMER_IDX_8814B(x) |                               \\\n\t BIT_RX_EMPTY_TIMER_IDX_8814B(v))\n\n#define BIT_SHIFT_RX_AFULL_TH_IDX_8814B 20\n#define BIT_MASK_RX_AFULL_TH_IDX_8814B 0x7\n#define BIT_RX_AFULL_TH_IDX_8814B(x)                                           \\\n\t(((x) & BIT_MASK_RX_AFULL_TH_IDX_8814B)                                \\\n\t << BIT_SHIFT_RX_AFULL_TH_IDX_8814B)\n#define BITS_RX_AFULL_TH_IDX_8814B                                             \\\n\t(BIT_MASK_RX_AFULL_TH_IDX_8814B << BIT_SHIFT_RX_AFULL_TH_IDX_8814B)\n#define BIT_CLEAR_RX_AFULL_TH_IDX_8814B(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8814B))\n#define BIT_GET_RX_AFULL_TH_IDX_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8814B) &                            \\\n\t BIT_MASK_RX_AFULL_TH_IDX_8814B)\n#define BIT_SET_RX_AFULL_TH_IDX_8814B(x, v)                                    \\\n\t(BIT_CLEAR_RX_AFULL_TH_IDX_8814B(x) | BIT_RX_AFULL_TH_IDX_8814B(v))\n\n#define BIT_SHIFT_RX_HIGH_TH_IDX_8814B 16\n#define BIT_MASK_RX_HIGH_TH_IDX_8814B 0x7\n#define BIT_RX_HIGH_TH_IDX_8814B(x)                                            \\\n\t(((x) & BIT_MASK_RX_HIGH_TH_IDX_8814B)                                 \\\n\t << BIT_SHIFT_RX_HIGH_TH_IDX_8814B)\n#define BITS_RX_HIGH_TH_IDX_8814B                                              \\\n\t(BIT_MASK_RX_HIGH_TH_IDX_8814B << BIT_SHIFT_RX_HIGH_TH_IDX_8814B)\n#define BIT_CLEAR_RX_HIGH_TH_IDX_8814B(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8814B))\n#define BIT_GET_RX_HIGH_TH_IDX_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8814B) &                             \\\n\t BIT_MASK_RX_HIGH_TH_IDX_8814B)\n#define BIT_SET_RX_HIGH_TH_IDX_8814B(x, v)                                     \\\n\t(BIT_CLEAR_RX_HIGH_TH_IDX_8814B(x) | BIT_RX_HIGH_TH_IDX_8814B(v))\n\n#define BIT_SHIFT_RX_MED_TH_IDX_8814B 12\n#define BIT_MASK_RX_MED_TH_IDX_8814B 0x7\n#define BIT_RX_MED_TH_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_RX_MED_TH_IDX_8814B) << BIT_SHIFT_RX_MED_TH_IDX_8814B)\n#define BITS_RX_MED_TH_IDX_8814B                                               \\\n\t(BIT_MASK_RX_MED_TH_IDX_8814B << BIT_SHIFT_RX_MED_TH_IDX_8814B)\n#define BIT_CLEAR_RX_MED_TH_IDX_8814B(x) ((x) & (~BITS_RX_MED_TH_IDX_8814B))\n#define BIT_GET_RX_MED_TH_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_RX_MED_TH_IDX_8814B) & BIT_MASK_RX_MED_TH_IDX_8814B)\n#define BIT_SET_RX_MED_TH_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_RX_MED_TH_IDX_8814B(x) | BIT_RX_MED_TH_IDX_8814B(v))\n\n#define BIT_SHIFT_RX_LOW_TH_IDX_8814B 8\n#define BIT_MASK_RX_LOW_TH_IDX_8814B 0x7\n#define BIT_RX_LOW_TH_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_RX_LOW_TH_IDX_8814B) << BIT_SHIFT_RX_LOW_TH_IDX_8814B)\n#define BITS_RX_LOW_TH_IDX_8814B                                               \\\n\t(BIT_MASK_RX_LOW_TH_IDX_8814B << BIT_SHIFT_RX_LOW_TH_IDX_8814B)\n#define BIT_CLEAR_RX_LOW_TH_IDX_8814B(x) ((x) & (~BITS_RX_LOW_TH_IDX_8814B))\n#define BIT_GET_RX_LOW_TH_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8814B) & BIT_MASK_RX_LOW_TH_IDX_8814B)\n#define BIT_SET_RX_LOW_TH_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_RX_LOW_TH_IDX_8814B(x) | BIT_RX_LOW_TH_IDX_8814B(v))\n\n#define BIT_SHIFT_LTR_SPACE_IDX_8814B 4\n#define BIT_MASK_LTR_SPACE_IDX_8814B 0x3\n#define BIT_LTR_SPACE_IDX_8814B(x)                                             \\\n\t(((x) & BIT_MASK_LTR_SPACE_IDX_8814B) << BIT_SHIFT_LTR_SPACE_IDX_8814B)\n#define BITS_LTR_SPACE_IDX_8814B                                               \\\n\t(BIT_MASK_LTR_SPACE_IDX_8814B << BIT_SHIFT_LTR_SPACE_IDX_8814B)\n#define BIT_CLEAR_LTR_SPACE_IDX_8814B(x) ((x) & (~BITS_LTR_SPACE_IDX_8814B))\n#define BIT_GET_LTR_SPACE_IDX_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_LTR_SPACE_IDX_8814B) & BIT_MASK_LTR_SPACE_IDX_8814B)\n#define BIT_SET_LTR_SPACE_IDX_8814B(x, v)                                      \\\n\t(BIT_CLEAR_LTR_SPACE_IDX_8814B(x) | BIT_LTR_SPACE_IDX_8814B(v))\n\n#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B 0\n#define BIT_MASK_LTR_IDLE_TIMER_IDX_8814B 0x7\n#define BIT_LTR_IDLE_TIMER_IDX_8814B(x)                                        \\\n\t(((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8814B)                             \\\n\t << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B)\n#define BITS_LTR_IDLE_TIMER_IDX_8814B                                          \\\n\t(BIT_MASK_LTR_IDLE_TIMER_IDX_8814B                                     \\\n\t << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B)\n#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8814B(x)                                  \\\n\t((x) & (~BITS_LTR_IDLE_TIMER_IDX_8814B))\n#define BIT_GET_LTR_IDLE_TIMER_IDX_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B) &                         \\\n\t BIT_MASK_LTR_IDLE_TIMER_IDX_8814B)\n#define BIT_SET_LTR_IDLE_TIMER_IDX_8814B(x, v)                                 \\\n\t(BIT_CLEAR_LTR_IDLE_TIMER_IDX_8814B(x) |                               \\\n\t BIT_LTR_IDLE_TIMER_IDX_8814B(v))\n\n/* 2 REG_LTR_IDLE_LATENCY_V1_8814B */\n\n#define BIT_SHIFT_LTR_IDLE_L_8814B 0\n#define BIT_MASK_LTR_IDLE_L_8814B 0xffffffffL\n#define BIT_LTR_IDLE_L_8814B(x)                                                \\\n\t(((x) & BIT_MASK_LTR_IDLE_L_8814B) << BIT_SHIFT_LTR_IDLE_L_8814B)\n#define BITS_LTR_IDLE_L_8814B                                                  \\\n\t(BIT_MASK_LTR_IDLE_L_8814B << BIT_SHIFT_LTR_IDLE_L_8814B)\n#define BIT_CLEAR_LTR_IDLE_L_8814B(x) ((x) & (~BITS_LTR_IDLE_L_8814B))\n#define BIT_GET_LTR_IDLE_L_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_LTR_IDLE_L_8814B) & BIT_MASK_LTR_IDLE_L_8814B)\n#define BIT_SET_LTR_IDLE_L_8814B(x, v)                                         \\\n\t(BIT_CLEAR_LTR_IDLE_L_8814B(x) | BIT_LTR_IDLE_L_8814B(v))\n\n/* 2 REG_LTR_ACTIVE_LATENCY_V1_8814B */\n\n#define BIT_SHIFT_LTR_ACT_L_8814B 0\n#define BIT_MASK_LTR_ACT_L_8814B 0xffffffffL\n#define BIT_LTR_ACT_L_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_LTR_ACT_L_8814B) << BIT_SHIFT_LTR_ACT_L_8814B)\n#define BITS_LTR_ACT_L_8814B                                                   \\\n\t(BIT_MASK_LTR_ACT_L_8814B << BIT_SHIFT_LTR_ACT_L_8814B)\n#define BIT_CLEAR_LTR_ACT_L_8814B(x) ((x) & (~BITS_LTR_ACT_L_8814B))\n#define BIT_GET_LTR_ACT_L_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_LTR_ACT_L_8814B) & BIT_MASK_LTR_ACT_L_8814B)\n#define BIT_SET_LTR_ACT_L_8814B(x, v)                                          \\\n\t(BIT_CLEAR_LTR_ACT_L_8814B(x) | BIT_LTR_ACT_L_8814B(v))\n\n#define BIT_SHIFT_ANT_ADDR2_1_8814B 0\n#define BIT_MASK_ANT_ADDR2_1_8814B 0xffffffffL\n#define BIT_ANT_ADDR2_1_8814B(x)                                               \\\n\t(((x) & BIT_MASK_ANT_ADDR2_1_8814B) << BIT_SHIFT_ANT_ADDR2_1_8814B)\n#define BITS_ANT_ADDR2_1_8814B                                                 \\\n\t(BIT_MASK_ANT_ADDR2_1_8814B << BIT_SHIFT_ANT_ADDR2_1_8814B)\n#define BIT_CLEAR_ANT_ADDR2_1_8814B(x) ((x) & (~BITS_ANT_ADDR2_1_8814B))\n#define BIT_GET_ANT_ADDR2_1_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_ANT_ADDR2_1_8814B) & BIT_MASK_ANT_ADDR2_1_8814B)\n#define BIT_SET_ANT_ADDR2_1_8814B(x, v)                                        \\\n\t(BIT_CLEAR_ANT_ADDR2_1_8814B(x) | BIT_ANT_ADDR2_1_8814B(v))\n\n/* 2 REG_SMART_ANT_CTRL_8814B */\n#define BIT_ANTTRN_SWITCH_8814B BIT(19)\n#define BIT_APPEND_MACID_IN_RESP_EN_1_8814B BIT(18)\n#define BIT_ADDR2_MATCH_EN_1_8814B BIT(17)\n#define BIT_ANTTRN_EN_1_8814B BIT(16)\n\n#define BIT_SHIFT_ANT_ADDR2_2_8814B 0\n#define BIT_MASK_ANT_ADDR2_2_8814B 0xffff\n#define BIT_ANT_ADDR2_2_8814B(x)                                               \\\n\t(((x) & BIT_MASK_ANT_ADDR2_2_8814B) << BIT_SHIFT_ANT_ADDR2_2_8814B)\n#define BITS_ANT_ADDR2_2_8814B                                                 \\\n\t(BIT_MASK_ANT_ADDR2_2_8814B << BIT_SHIFT_ANT_ADDR2_2_8814B)\n#define BIT_CLEAR_ANT_ADDR2_2_8814B(x) ((x) & (~BITS_ANT_ADDR2_2_8814B))\n#define BIT_GET_ANT_ADDR2_2_8814B(x)                                           \\\n\t(((x) >> BIT_SHIFT_ANT_ADDR2_2_8814B) & BIT_MASK_ANT_ADDR2_2_8814B)\n#define BIT_SET_ANT_ADDR2_2_8814B(x, v)                                        \\\n\t(BIT_CLEAR_ANT_ADDR2_2_8814B(x) | BIT_ANT_ADDR2_2_8814B(v))\n\n/* 2 REG_CONTROL_FRAME_REPORT_8814B */\n\n#define BIT_SHIFT_CONTROL_FRAME_REPORT_8814B 0\n#define BIT_MASK_CONTROL_FRAME_REPORT_8814B 0xffffffffL\n#define BIT_CONTROL_FRAME_REPORT_8814B(x)                                      \\\n\t(((x) & BIT_MASK_CONTROL_FRAME_REPORT_8814B)                           \\\n\t << BIT_SHIFT_CONTROL_FRAME_REPORT_8814B)\n#define BITS_CONTROL_FRAME_REPORT_8814B                                        \\\n\t(BIT_MASK_CONTROL_FRAME_REPORT_8814B                                   \\\n\t << BIT_SHIFT_CONTROL_FRAME_REPORT_8814B)\n#define BIT_CLEAR_CONTROL_FRAME_REPORT_8814B(x)                                \\\n\t((x) & (~BITS_CONTROL_FRAME_REPORT_8814B))\n#define BIT_GET_CONTROL_FRAME_REPORT_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_CONTROL_FRAME_REPORT_8814B) &                       \\\n\t BIT_MASK_CONTROL_FRAME_REPORT_8814B)\n#define BIT_SET_CONTROL_FRAME_REPORT_8814B(x, v)                               \\\n\t(BIT_CLEAR_CONTROL_FRAME_REPORT_8814B(x) |                             \\\n\t BIT_CONTROL_FRAME_REPORT_8814B(v))\n\n/* 2 REG_CONTROL_FRAME_CNT_CTRL_8814B */\n#define BIT_ALLCNTRST_8814B BIT(9)\n#define BIT__ALLCNTEN_8814B BIT(8)\n\n#define BIT_SHIFT_ADDR_8814B 4\n#define BIT_MASK_ADDR_8814B 0xf\n#define BIT_ADDR_8814B(x) (((x) & BIT_MASK_ADDR_8814B) << BIT_SHIFT_ADDR_8814B)\n#define BITS_ADDR_8814B (BIT_MASK_ADDR_8814B << BIT_SHIFT_ADDR_8814B)\n#define BIT_CLEAR_ADDR_8814B(x) ((x) & (~BITS_ADDR_8814B))\n#define BIT_GET_ADDR_8814B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_ADDR_8814B) & BIT_MASK_ADDR_8814B)\n#define BIT_SET_ADDR_8814B(x, v) (BIT_CLEAR_ADDR_8814B(x) | BIT_ADDR_8814B(v))\n\n#define BIT_SHIFT_CTRL_SEL_8814B 0\n#define BIT_MASK_CTRL_SEL_8814B 0xf\n#define BIT_CTRL_SEL_8814B(x)                                                  \\\n\t(((x) & BIT_MASK_CTRL_SEL_8814B) << BIT_SHIFT_CTRL_SEL_8814B)\n#define BITS_CTRL_SEL_8814B                                                    \\\n\t(BIT_MASK_CTRL_SEL_8814B << BIT_SHIFT_CTRL_SEL_8814B)\n#define BIT_CLEAR_CTRL_SEL_8814B(x) ((x) & (~BITS_CTRL_SEL_8814B))\n#define BIT_GET_CTRL_SEL_8814B(x)                                              \\\n\t(((x) >> BIT_SHIFT_CTRL_SEL_8814B) & BIT_MASK_CTRL_SEL_8814B)\n#define BIT_SET_CTRL_SEL_8814B(x, v)                                           \\\n\t(BIT_CLEAR_CTRL_SEL_8814B(x) | BIT_CTRL_SEL_8814B(v))\n\n/* 2 REG_IQ_DUMP_8814B */\n\n#define BIT_SHIFT_DUMP_OK_ADDR_8814B 16\n#define BIT_MASK_DUMP_OK_ADDR_8814B 0xffff\n#define BIT_DUMP_OK_ADDR_8814B(x)                                              \\\n\t(((x) & BIT_MASK_DUMP_OK_ADDR_8814B) << BIT_SHIFT_DUMP_OK_ADDR_8814B)\n#define BITS_DUMP_OK_ADDR_8814B                                                \\\n\t(BIT_MASK_DUMP_OK_ADDR_8814B << BIT_SHIFT_DUMP_OK_ADDR_8814B)\n#define BIT_CLEAR_DUMP_OK_ADDR_8814B(x) ((x) & (~BITS_DUMP_OK_ADDR_8814B))\n#define BIT_GET_DUMP_OK_ADDR_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DUMP_OK_ADDR_8814B) & BIT_MASK_DUMP_OK_ADDR_8814B)\n#define BIT_SET_DUMP_OK_ADDR_8814B(x, v)                                       \\\n\t(BIT_CLEAR_DUMP_OK_ADDR_8814B(x) | BIT_DUMP_OK_ADDR_8814B(v))\n\n#define BIT_SHIFT_R_TRIG_TIME_SEL_8814B 8\n#define BIT_MASK_R_TRIG_TIME_SEL_8814B 0x7f\n#define BIT_R_TRIG_TIME_SEL_8814B(x)                                           \\\n\t(((x) & BIT_MASK_R_TRIG_TIME_SEL_8814B)                                \\\n\t << BIT_SHIFT_R_TRIG_TIME_SEL_8814B)\n#define BITS_R_TRIG_TIME_SEL_8814B                                             \\\n\t(BIT_MASK_R_TRIG_TIME_SEL_8814B << BIT_SHIFT_R_TRIG_TIME_SEL_8814B)\n#define BIT_CLEAR_R_TRIG_TIME_SEL_8814B(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8814B))\n#define BIT_GET_R_TRIG_TIME_SEL_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8814B) &                            \\\n\t BIT_MASK_R_TRIG_TIME_SEL_8814B)\n#define BIT_SET_R_TRIG_TIME_SEL_8814B(x, v)                                    \\\n\t(BIT_CLEAR_R_TRIG_TIME_SEL_8814B(x) | BIT_R_TRIG_TIME_SEL_8814B(v))\n\n#define BIT_SHIFT_R_MAC_TRIG_SEL_8814B 6\n#define BIT_MASK_R_MAC_TRIG_SEL_8814B 0x3\n#define BIT_R_MAC_TRIG_SEL_8814B(x)                                            \\\n\t(((x) & BIT_MASK_R_MAC_TRIG_SEL_8814B)                                 \\\n\t << BIT_SHIFT_R_MAC_TRIG_SEL_8814B)\n#define BITS_R_MAC_TRIG_SEL_8814B                                              \\\n\t(BIT_MASK_R_MAC_TRIG_SEL_8814B << BIT_SHIFT_R_MAC_TRIG_SEL_8814B)\n#define BIT_CLEAR_R_MAC_TRIG_SEL_8814B(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8814B))\n#define BIT_GET_R_MAC_TRIG_SEL_8814B(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8814B) &                             \\\n\t BIT_MASK_R_MAC_TRIG_SEL_8814B)\n#define BIT_SET_R_MAC_TRIG_SEL_8814B(x, v)                                     \\\n\t(BIT_CLEAR_R_MAC_TRIG_SEL_8814B(x) | BIT_R_MAC_TRIG_SEL_8814B(v))\n\n#define BIT_MAC_TRIG_REG_8814B BIT(5)\n\n#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B 3\n#define BIT_MASK_R_LEVEL_PULSE_SEL_8814B 0x3\n#define BIT_R_LEVEL_PULSE_SEL_8814B(x)                                         \\\n\t(((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8814B)                              \\\n\t << BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B)\n#define BITS_R_LEVEL_PULSE_SEL_8814B                                           \\\n\t(BIT_MASK_R_LEVEL_PULSE_SEL_8814B << BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B)\n#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8814B(x)                                   \\\n\t((x) & (~BITS_R_LEVEL_PULSE_SEL_8814B))\n#define BIT_GET_R_LEVEL_PULSE_SEL_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B) &                          \\\n\t BIT_MASK_R_LEVEL_PULSE_SEL_8814B)\n#define BIT_SET_R_LEVEL_PULSE_SEL_8814B(x, v)                                  \\\n\t(BIT_CLEAR_R_LEVEL_PULSE_SEL_8814B(x) | BIT_R_LEVEL_PULSE_SEL_8814B(v))\n\n#define BIT_EN_LA_MAC_8814B BIT(2)\n#define BIT_R_EN_IQDUMP_8814B BIT(1)\n#define BIT_R_IQDATA_DUMP_8814B BIT(0)\n\n/* 2 REG_IQ_DUMP_1_8814B */\n\n#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B 0\n#define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B 0xffffffffL\n#define BIT_R_WMAC_MASK_LA_MAC_1_8814B(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B)                           \\\n\t << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B)\n#define BITS_R_WMAC_MASK_LA_MAC_1_8814B                                        \\\n\t(BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B                                   \\\n\t << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B)\n#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8814B(x)                                \\\n\t((x) & (~BITS_R_WMAC_MASK_LA_MAC_1_8814B))\n#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B) &                       \\\n\t BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B)\n#define BIT_SET_R_WMAC_MASK_LA_MAC_1_8814B(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8814B(x) |                             \\\n\t BIT_R_WMAC_MASK_LA_MAC_1_8814B(v))\n\n/* 2 REG_IQ_DUMP_2_8814B */\n\n#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B 0\n#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B 0xffffffffL\n#define BIT_R_WMAC_MATCH_REF_MAC_2_8814B(x)                                    \\\n\t(((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B)                         \\\n\t << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B)\n#define BITS_R_WMAC_MATCH_REF_MAC_2_8814B                                      \\\n\t(BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B                                 \\\n\t << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B)\n#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8814B(x)                              \\\n\t((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2_8814B))\n#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8814B(x)                                \\\n\t(((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B) &                     \\\n\t BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B)\n#define BIT_SET_R_WMAC_MATCH_REF_MAC_2_8814B(x, v)                             \\\n\t(BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8814B(x) |                           \\\n\t BIT_R_WMAC_MATCH_REF_MAC_2_8814B(v))\n\n/* 2 REG_WMAC_FTM_CTL_8814B */\n#define BIT_RXFTM_TXACK_SC_8814B BIT(6)\n#define BIT_RXFTM_TXACK_BW_8814B BIT(5)\n#define BIT_RXFTM_EN_8814B BIT(3)\n#define BIT_RXFTMREQ_BYDRV_8814B BIT(2)\n#define BIT_RXFTMREQ_EN_8814B BIT(1)\n#define BIT_FTM_EN_8814B BIT(0)\n\n/* 2 REG_WMAC_IQ_MDPK_FUNC_8814B */\n\n/* 2 REG_WMAC_OPTION_FUNCTION_8814B */\n\n#define BIT_SHIFT_R_OFDM_LEN_8814B 26\n#define BIT_MASK_R_OFDM_LEN_8814B 0x3f\n#define BIT_R_OFDM_LEN_8814B(x)                                                \\\n\t(((x) & BIT_MASK_R_OFDM_LEN_8814B) << BIT_SHIFT_R_OFDM_LEN_8814B)\n#define BITS_R_OFDM_LEN_8814B                                                  \\\n\t(BIT_MASK_R_OFDM_LEN_8814B << BIT_SHIFT_R_OFDM_LEN_8814B)\n#define BIT_CLEAR_R_OFDM_LEN_8814B(x) ((x) & (~BITS_R_OFDM_LEN_8814B))\n#define BIT_GET_R_OFDM_LEN_8814B(x)                                            \\\n\t(((x) >> BIT_SHIFT_R_OFDM_LEN_8814B) & BIT_MASK_R_OFDM_LEN_8814B)\n#define BIT_SET_R_OFDM_LEN_8814B(x, v)                                         \\\n\t(BIT_CLEAR_R_OFDM_LEN_8814B(x) | BIT_R_OFDM_LEN_8814B(v))\n\n#define BIT_SHIFT_R_CCK_LEN_8814B 0\n#define BIT_MASK_R_CCK_LEN_8814B 0xffff\n#define BIT_R_CCK_LEN_8814B(x)                                                 \\\n\t(((x) & BIT_MASK_R_CCK_LEN_8814B) << BIT_SHIFT_R_CCK_LEN_8814B)\n#define BITS_R_CCK_LEN_8814B                                                   \\\n\t(BIT_MASK_R_CCK_LEN_8814B << BIT_SHIFT_R_CCK_LEN_8814B)\n#define BIT_CLEAR_R_CCK_LEN_8814B(x) ((x) & (~BITS_R_CCK_LEN_8814B))\n#define BIT_GET_R_CCK_LEN_8814B(x)                                             \\\n\t(((x) >> BIT_SHIFT_R_CCK_LEN_8814B) & BIT_MASK_R_CCK_LEN_8814B)\n#define BIT_SET_R_CCK_LEN_8814B(x, v)                                          \\\n\t(BIT_CLEAR_R_CCK_LEN_8814B(x) | BIT_R_CCK_LEN_8814B(v))\n\n/* 2 REG_WMAC_OPTION_FUNCTION_1_8814B */\n\n#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B 24\n#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B 0xff\n#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8814B(x)                                   \\\n\t(((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B)                        \\\n\t << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B)\n#define BITS_R_WMAC_RXFIFO_FULL_TH_1_8814B                                     \\\n\t(BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B                                \\\n\t << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B)\n#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8814B(x)                             \\\n\t((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1_8814B))\n#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8814B(x)                               \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B) &                    \\\n\t BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B)\n#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1_8814B(x, v)                            \\\n\t(BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) |                          \\\n\t BIT_R_WMAC_RXFIFO_FULL_TH_1_8814B(v))\n\n#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8814B BIT(23)\n#define BIT_R_WMAC_RXRST_DLY_1_8814B BIT(22)\n#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1_8814B BIT(21)\n#define BIT_R_WMAC_SRCH_TXRPT_UA1_1_8814B BIT(20)\n#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1_8814B BIT(19)\n#define BIT_R_WMAC_NDP_RST_1_8814B BIT(18)\n#define BIT_R_WMAC_POWINT_EN_1_8814B BIT(17)\n#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1_8814B BIT(16)\n#define BIT_R_WMAC_SRCH_TXRPT_MID_1_8814B BIT(15)\n#define BIT_R_WMAC_PFIN_TOEN_1_8814B BIT(14)\n#define BIT_R_WMAC_FIL_SECERR_1_8814B BIT(13)\n#define BIT_R_WMAC_FIL_CTLPKTLEN_1_8814B BIT(12)\n#define BIT_R_WMAC_FIL_FCTYPE_1_8814B BIT(11)\n#define BIT_R_WMAC_FIL_FCPROVER_1_8814B BIT(10)\n#define BIT_R_WMAC_PHYSTS_SNIF_1_8814B BIT(9)\n#define BIT_R_WMAC_PHYSTS_PLCP_1_8814B BIT(8)\n#define BIT_R_MAC_TCR_VBONF_RD_1_8814B BIT(7)\n#define BIT_R_WMAC_TCR_MPAR_NDP_1_8814B BIT(6)\n#define BIT_R_WMAC_NDP_FILTER_1_8814B BIT(5)\n#define BIT_R_WMAC_RXLEN_SEL_1_8814B BIT(4)\n#define BIT_R_WMAC_RXLEN_SEL1_1_8814B BIT(3)\n#define BIT_R_OFDM_FILTER_1_8814B BIT(2)\n#define BIT_R_WMAC_CHK_OFDM_LEN_1_8814B BIT(1)\n#define BIT_R_WMAC_CHK_CCK_LEN_1_8814B BIT(0)\n\n/* 2 REG_WMAC_OPTION_FUNCTION_2_8814B */\n\n#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B 0\n#define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B 0xffff\n#define BIT_R_WMAC_RX_FIL_LEN_2_8814B(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B)                            \\\n\t << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B)\n#define BITS_R_WMAC_RX_FIL_LEN_2_8814B                                         \\\n\t(BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B                                    \\\n\t << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B)\n#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8814B(x)                                 \\\n\t((x) & (~BITS_R_WMAC_RX_FIL_LEN_2_8814B))\n#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B) &                        \\\n\t BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B)\n#define BIT_SET_R_WMAC_RX_FIL_LEN_2_8814B(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8814B(x) |                              \\\n\t BIT_R_WMAC_RX_FIL_LEN_2_8814B(v))\n\n/* 2 REG_RX_FILTER_FUNCTION_8814B */\n#define BIT_R_WMAC_MHRDDY_LATCH_8814B BIT(14)\n#define BIT_R_WMAC_MHRDDY_CLR_8814B BIT(13)\n#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8814B BIT(12)\n#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU_8814B BIT(11)\n#define BIT_R_CHK_DELIMIT_LEN_8814B BIT(10)\n#define BIT_R_REAPTER_ADDR_MATCH_8814B BIT(9)\n#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8814B BIT(8)\n#define BIT_R_LATCH_MACHRDY_8814B BIT(7)\n#define BIT_R_WMAC_RXFIL_REND_8814B BIT(6)\n#define BIT_R_WMAC_MPDURDY_CLR_8814B BIT(5)\n#define BIT_R_WMAC_CLRRXSEC_8814B BIT(4)\n#define BIT_R_WMAC_RXFIL_RDEL_8814B BIT(3)\n#define BIT_R_WMAC_RXFIL_FCSE_8814B BIT(2)\n#define BIT_R_WMAC_RXFIL_MESH_DEL_8814B BIT(1)\n#define BIT_R_WMAC_RXFIL_MASKM_8814B BIT(0)\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NDP_SIG_8814B */\n\n#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B 0\n#define BIT_MASK_R_WMAC_TXNDP_SIGB_8814B 0x1fffff\n#define BIT_R_WMAC_TXNDP_SIGB_8814B(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8814B)                              \\\n\t << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B)\n#define BITS_R_WMAC_TXNDP_SIGB_8814B                                           \\\n\t(BIT_MASK_R_WMAC_TXNDP_SIGB_8814B << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B)\n#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8814B(x)                                   \\\n\t((x) & (~BITS_R_WMAC_TXNDP_SIGB_8814B))\n#define BIT_GET_R_WMAC_TXNDP_SIGB_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B) &                          \\\n\t BIT_MASK_R_WMAC_TXNDP_SIGB_8814B)\n#define BIT_SET_R_WMAC_TXNDP_SIGB_8814B(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_TXNDP_SIGB_8814B(x) | BIT_R_WMAC_TXNDP_SIGB_8814B(v))\n\n/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8814B */\n\n#define BIT_SHIFT_R_MAC_DBG_SHIFT_8814B 8\n#define BIT_MASK_R_MAC_DBG_SHIFT_8814B 0x7\n#define BIT_R_MAC_DBG_SHIFT_8814B(x)                                           \\\n\t(((x) & BIT_MASK_R_MAC_DBG_SHIFT_8814B)                                \\\n\t << BIT_SHIFT_R_MAC_DBG_SHIFT_8814B)\n#define BITS_R_MAC_DBG_SHIFT_8814B                                             \\\n\t(BIT_MASK_R_MAC_DBG_SHIFT_8814B << BIT_SHIFT_R_MAC_DBG_SHIFT_8814B)\n#define BIT_CLEAR_R_MAC_DBG_SHIFT_8814B(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8814B))\n#define BIT_GET_R_MAC_DBG_SHIFT_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8814B) &                            \\\n\t BIT_MASK_R_MAC_DBG_SHIFT_8814B)\n#define BIT_SET_R_MAC_DBG_SHIFT_8814B(x, v)                                    \\\n\t(BIT_CLEAR_R_MAC_DBG_SHIFT_8814B(x) | BIT_R_MAC_DBG_SHIFT_8814B(v))\n\n#define BIT_SHIFT_R_MAC_DBG_SEL_8814B 0\n#define BIT_MASK_R_MAC_DBG_SEL_8814B 0x3\n#define BIT_R_MAC_DBG_SEL_8814B(x)                                             \\\n\t(((x) & BIT_MASK_R_MAC_DBG_SEL_8814B) << BIT_SHIFT_R_MAC_DBG_SEL_8814B)\n#define BITS_R_MAC_DBG_SEL_8814B                                               \\\n\t(BIT_MASK_R_MAC_DBG_SEL_8814B << BIT_SHIFT_R_MAC_DBG_SEL_8814B)\n#define BIT_CLEAR_R_MAC_DBG_SEL_8814B(x) ((x) & (~BITS_R_MAC_DBG_SEL_8814B))\n#define BIT_GET_R_MAC_DBG_SEL_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8814B) & BIT_MASK_R_MAC_DBG_SEL_8814B)\n#define BIT_SET_R_MAC_DBG_SEL_8814B(x, v)                                      \\\n\t(BIT_CLEAR_R_MAC_DBG_SEL_8814B(x) | BIT_R_MAC_DBG_SEL_8814B(v))\n\n/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8814B */\n\n#define BIT_SHIFT_R_MAC_DEBUG_1_8814B 0\n#define BIT_MASK_R_MAC_DEBUG_1_8814B 0xffffffffL\n#define BIT_R_MAC_DEBUG_1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_R_MAC_DEBUG_1_8814B) << BIT_SHIFT_R_MAC_DEBUG_1_8814B)\n#define BITS_R_MAC_DEBUG_1_8814B                                               \\\n\t(BIT_MASK_R_MAC_DEBUG_1_8814B << BIT_SHIFT_R_MAC_DEBUG_1_8814B)\n#define BIT_CLEAR_R_MAC_DEBUG_1_8814B(x) ((x) & (~BITS_R_MAC_DEBUG_1_8814B))\n#define BIT_GET_R_MAC_DEBUG_1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8814B) & BIT_MASK_R_MAC_DEBUG_1_8814B)\n#define BIT_SET_R_MAC_DEBUG_1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_R_MAC_DEBUG_1_8814B(x) | BIT_R_MAC_DEBUG_1_8814B(v))\n\n/* 2 REG_WSEC_OPTION_8814B */\n#define BIT_RXDEC_BM_MGNT_8814B BIT(22)\n#define BIT_TXENC_BM_MGNT_8814B BIT(21)\n#define BIT_RXDEC_UNI_MGNT_8814B BIT(20)\n#define BIT_TXENC_UNI_MGNT_8814B BIT(19)\n\n/* 2 REG_RTS_ADDRESS_0_8814B */\n\n/* 2 REG_RTS_ADDRESS_0_1_8814B */\n\n/* 2 REG_RTS_ADDRESS_1_8814B */\n\n/* 2 REG_RTS_ADDRESS_1_1_8814B */\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8814B */\n#define BIT_LTECOEX_ACCESS_START_V1_8814B BIT(31)\n#define BIT_LTECOEX_WRITE_MODE_V1_8814B BIT(30)\n#define BIT_LTECOEX_READY_BIT_V1_8814B BIT(29)\n\n#define BIT_SHIFT_WRITE_BYTE_EN_V1_8814B 16\n#define BIT_MASK_WRITE_BYTE_EN_V1_8814B 0xf\n#define BIT_WRITE_BYTE_EN_V1_8814B(x)                                          \\\n\t(((x) & BIT_MASK_WRITE_BYTE_EN_V1_8814B)                               \\\n\t << BIT_SHIFT_WRITE_BYTE_EN_V1_8814B)\n#define BITS_WRITE_BYTE_EN_V1_8814B                                            \\\n\t(BIT_MASK_WRITE_BYTE_EN_V1_8814B << BIT_SHIFT_WRITE_BYTE_EN_V1_8814B)\n#define BIT_CLEAR_WRITE_BYTE_EN_V1_8814B(x)                                    \\\n\t((x) & (~BITS_WRITE_BYTE_EN_V1_8814B))\n#define BIT_GET_WRITE_BYTE_EN_V1_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8814B) &                           \\\n\t BIT_MASK_WRITE_BYTE_EN_V1_8814B)\n#define BIT_SET_WRITE_BYTE_EN_V1_8814B(x, v)                                   \\\n\t(BIT_CLEAR_WRITE_BYTE_EN_V1_8814B(x) | BIT_WRITE_BYTE_EN_V1_8814B(v))\n\n#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B 0\n#define BIT_MASK_LTECOEX_REG_ADDR_V1_8814B 0xffff\n#define BIT_LTECOEX_REG_ADDR_V1_8814B(x)                                       \\\n\t(((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8814B)                            \\\n\t << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B)\n#define BITS_LTECOEX_REG_ADDR_V1_8814B                                         \\\n\t(BIT_MASK_LTECOEX_REG_ADDR_V1_8814B                                    \\\n\t << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B)\n#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8814B(x)                                 \\\n\t((x) & (~BITS_LTECOEX_REG_ADDR_V1_8814B))\n#define BIT_GET_LTECOEX_REG_ADDR_V1_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B) &                        \\\n\t BIT_MASK_LTECOEX_REG_ADDR_V1_8814B)\n#define BIT_SET_LTECOEX_REG_ADDR_V1_8814B(x, v)                                \\\n\t(BIT_CLEAR_LTECOEX_REG_ADDR_V1_8814B(x) |                              \\\n\t BIT_LTECOEX_REG_ADDR_V1_8814B(v))\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8814B */\n\n#define BIT_SHIFT_LTECOEX_W_DATA_V1_8814B 0\n#define BIT_MASK_LTECOEX_W_DATA_V1_8814B 0xffffffffL\n#define BIT_LTECOEX_W_DATA_V1_8814B(x)                                         \\\n\t(((x) & BIT_MASK_LTECOEX_W_DATA_V1_8814B)                              \\\n\t << BIT_SHIFT_LTECOEX_W_DATA_V1_8814B)\n#define BITS_LTECOEX_W_DATA_V1_8814B                                           \\\n\t(BIT_MASK_LTECOEX_W_DATA_V1_8814B << BIT_SHIFT_LTECOEX_W_DATA_V1_8814B)\n#define BIT_CLEAR_LTECOEX_W_DATA_V1_8814B(x)                                   \\\n\t((x) & (~BITS_LTECOEX_W_DATA_V1_8814B))\n#define BIT_GET_LTECOEX_W_DATA_V1_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8814B) &                          \\\n\t BIT_MASK_LTECOEX_W_DATA_V1_8814B)\n#define BIT_SET_LTECOEX_W_DATA_V1_8814B(x, v)                                  \\\n\t(BIT_CLEAR_LTECOEX_W_DATA_V1_8814B(x) | BIT_LTECOEX_W_DATA_V1_8814B(v))\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8814B */\n\n#define BIT_SHIFT_LTECOEX_R_DATA_V1_8814B 0\n#define BIT_MASK_LTECOEX_R_DATA_V1_8814B 0xffffffffL\n#define BIT_LTECOEX_R_DATA_V1_8814B(x)                                         \\\n\t(((x) & BIT_MASK_LTECOEX_R_DATA_V1_8814B)                              \\\n\t << BIT_SHIFT_LTECOEX_R_DATA_V1_8814B)\n#define BITS_LTECOEX_R_DATA_V1_8814B                                           \\\n\t(BIT_MASK_LTECOEX_R_DATA_V1_8814B << BIT_SHIFT_LTECOEX_R_DATA_V1_8814B)\n#define BIT_CLEAR_LTECOEX_R_DATA_V1_8814B(x)                                   \\\n\t((x) & (~BITS_LTECOEX_R_DATA_V1_8814B))\n#define BIT_GET_LTECOEX_R_DATA_V1_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8814B) &                          \\\n\t BIT_MASK_LTECOEX_R_DATA_V1_8814B)\n#define BIT_SET_LTECOEX_R_DATA_V1_8814B(x, v)                                  \\\n\t(BIT_CLEAR_LTECOEX_R_DATA_V1_8814B(x) | BIT_LTECOEX_R_DATA_V1_8814B(v))\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_NOT_VALID_8814B */\n\n/* 2 REG_PCIE_CFG_FORCE_LINK_L_8814B */\n#define BIT_PCIE_CFG_FORCE_EN_8814B BIT(7)\n\n/* 2 REG_PCIE_CFG_FORCE_LINK_H_8814B */\n#define BIT_PCIE_CFG_TRXACT_DIS_IDLE_TIMER_8814B BIT(6)\n\n#define BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B 0\n#define BIT_MASK_PCIE_CFG_LINK_STATE_8814B 0x3f\n#define BIT_PCIE_CFG_LINK_STATE_8814B(x)                                       \\\n\t(((x) & BIT_MASK_PCIE_CFG_LINK_STATE_8814B)                            \\\n\t << BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B)\n#define BITS_PCIE_CFG_LINK_STATE_8814B                                         \\\n\t(BIT_MASK_PCIE_CFG_LINK_STATE_8814B                                    \\\n\t << BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B)\n#define BIT_CLEAR_PCIE_CFG_LINK_STATE_8814B(x)                                 \\\n\t((x) & (~BITS_PCIE_CFG_LINK_STATE_8814B))\n#define BIT_GET_PCIE_CFG_LINK_STATE_8814B(x)                                   \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B) &                        \\\n\t BIT_MASK_PCIE_CFG_LINK_STATE_8814B)\n#define BIT_SET_PCIE_CFG_LINK_STATE_8814B(x, v)                                \\\n\t(BIT_CLEAR_PCIE_CFG_LINK_STATE_8814B(x) |                              \\\n\t BIT_PCIE_CFG_LINK_STATE_8814B(v))\n\n/* 2 REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B */\n\n#define BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B 0\n#define BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B 0xff\n#define BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x)                            \\\n\t(((x) & BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B)                 \\\n\t << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B)\n#define BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B                              \\\n\t(BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B                         \\\n\t << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B)\n#define BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x)                      \\\n\t((x) & (~BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B))\n#define BIT_GET_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x)                        \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B) &             \\\n\t BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B)\n#define BIT_SET_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x, v)                     \\\n\t(BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x) |                   \\\n\t BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(v))\n\n/* 2 REG_PCIE_CFG_CX_NFTS_8814B */\n\n#define BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B 0\n#define BIT_MASK_PCIE_CFG_CX_NFTS_8814B 0xff\n#define BIT_PCIE_CFG_CX_NFTS_8814B(x)                                          \\\n\t(((x) & BIT_MASK_PCIE_CFG_CX_NFTS_8814B)                               \\\n\t << BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B)\n#define BITS_PCIE_CFG_CX_NFTS_8814B                                            \\\n\t(BIT_MASK_PCIE_CFG_CX_NFTS_8814B << BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B)\n#define BIT_CLEAR_PCIE_CFG_CX_NFTS_8814B(x)                                    \\\n\t((x) & (~BITS_PCIE_CFG_CX_NFTS_8814B))\n#define BIT_GET_PCIE_CFG_CX_NFTS_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B) &                           \\\n\t BIT_MASK_PCIE_CFG_CX_NFTS_8814B)\n#define BIT_SET_PCIE_CFG_CX_NFTS_8814B(x, v)                                   \\\n\t(BIT_CLEAR_PCIE_CFG_CX_NFTS_8814B(x) | BIT_PCIE_CFG_CX_NFTS_8814B(v))\n\n/* 2 REG_PCIE_CFG_DEFAULT_ENTR_LATENCY_8814B */\n#define BIT_PCIE_CFG_REAL_EN_L0S_8814B BIT(7)\n#define BIT_PCIE_CFG_ENTER_ASPM_8814B BIT(6)\n\n#define BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B 3\n#define BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B 0x7\n#define BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x)                          \\\n\t(((x) & BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B)               \\\n\t << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B)\n#define BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B                            \\\n\t(BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B                       \\\n\t << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B)\n#define BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x)                    \\\n\t((x) & (~BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B))\n#define BIT_GET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x)                      \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B) &           \\\n\t BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B)\n#define BIT_SET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x, v)                   \\\n\t(BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x) |                 \\\n\t BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(v))\n\n#define BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B 0\n#define BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B 0x7\n#define BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x)                         \\\n\t(((x) & BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B)              \\\n\t << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B)\n#define BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B                           \\\n\t(BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B                      \\\n\t << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B)\n#define BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x)                   \\\n\t((x) & (~BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B))\n#define BIT_GET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x)                     \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B) &          \\\n\t BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B)\n#define BIT_SET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x, v)                  \\\n\t(BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x) |                \\\n\t BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(v))\n\n/* 2 REG_PCIE_CFG_L1_MISC_SEL_8814B */\n#define BIT_PCIE_CFG_L1_RIDLE_SEL_8814B BIT(6)\n#define BIT_PCIE_CFG_L1_TIMEOUT_SEL_8814B BIT(5)\n#define BIT_PCIE_CFG_L1_EIDLE_SEL_8814B BIT(4)\n\n#define BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B 0\n#define BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B 0xf\n#define BIT_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x)                                \\\n\t(((x) & BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B)                     \\\n\t << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B)\n#define BITS_PCIE_CFG_DEFAULT_LINK_RATE_8814B                                  \\\n\t(BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B                             \\\n\t << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B)\n#define BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x)                          \\\n\t((x) & (~BITS_PCIE_CFG_DEFAULT_LINK_RATE_8814B))\n#define BIT_GET_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x)                            \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B) &                 \\\n\t BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B)\n#define BIT_SET_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x, v)                         \\\n\t(BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x) |                       \\\n\t BIT_PCIE_CFG_DEFAULT_LINK_RATE_8814B(v))\n\n/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF_8814B */\n#define BIT_PCIE_CFG_REAL_PTM_ENABLE_8814B BIT(6)\n#define BIT_PCIE_CFG_REAL_EN_L1SUB_8814B BIT(5)\n\n#define BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B 0\n#define BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B 0x7\n#define BIT_PCIE_CFG_MAX_FUNC_NUM_8814B(x)                                     \\\n\t(((x) & BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B)                          \\\n\t << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B)\n#define BITS_PCIE_CFG_MAX_FUNC_NUM_8814B                                       \\\n\t(BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B                                  \\\n\t << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B)\n#define BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM_8814B(x)                               \\\n\t((x) & (~BITS_PCIE_CFG_MAX_FUNC_NUM_8814B))\n#define BIT_GET_PCIE_CFG_MAX_FUNC_NUM_8814B(x)                                 \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B) &                      \\\n\t BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B)\n#define BIT_SET_PCIE_CFG_MAX_FUNC_NUM_8814B(x, v)                              \\\n\t(BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM_8814B(x) |                            \\\n\t BIT_PCIE_CFG_MAX_FUNC_NUM_8814B(v))\n\n/* 2 REG_PCIE_CFG_FORCE_CLKREQ_N_PAD_8814B */\n#define BIT_PCIE_CFG_REAL_EN_64BITS_8814B BIT(5)\n#define BIT_PCIE_CFG_REAL_EN_CLKREQ_8814B BIT(4)\n#define BIT_PCIE_CFG_REAL_EN_L1_8814B BIT(3)\n#define BIT_PCIE_CFG_WAKE_N_EN_8814B BIT(2)\n#define BIT_PCIE_CFG_BYPASS_LTR_OPTION_8814B BIT(1)\n#define BIT_PCIE_CFG_FORCE_CLKREQ_N_PAD_8814B BIT(0)\n\n/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY_8814B */\n\n#define BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B 0\n#define BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B 0xff\n#define BIT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x)                                \\\n\t(((x) & BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B)                     \\\n\t << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B)\n#define BITS_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B                                  \\\n\t(BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B                             \\\n\t << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B)\n#define BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x)                          \\\n\t((x) & (~BITS_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B))\n#define BIT_GET_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x)                            \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B) &                 \\\n\t BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B)\n#define BIT_SET_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x, v)                         \\\n\t(BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x) |                       \\\n\t BIT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(v))\n\n/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG_8814B */\n#define BIT_PCIE_CFG_BYPASS_L1_SUBSTATE_OPTION_8814B BIT(7)\n\n#define BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B 5\n#define BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B 0x3\n#define BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x)                         \\\n\t(((x) & BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B)              \\\n\t << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B)\n#define BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B                           \\\n\t(BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B                      \\\n\t << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B)\n#define BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x)                   \\\n\t((x) & (~BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B))\n#define BIT_GET_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x)                     \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B) &          \\\n\t BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B)\n#define BIT_SET_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x, v)                  \\\n\t(BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x) |                \\\n\t BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(v))\n\n#define BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B 0\n#define BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B 0x1f\n#define BIT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x)                                \\\n\t(((x) & BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B)                     \\\n\t << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B)\n#define BITS_PCIE_CFG_UPDATE_FREQ_TIMER_8814B                                  \\\n\t(BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B                             \\\n\t << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B)\n#define BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x)                          \\\n\t((x) & (~BITS_PCIE_CFG_UPDATE_FREQ_TIMER_8814B))\n#define BIT_GET_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x)                            \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B) &                 \\\n\t BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B)\n#define BIT_SET_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x, v)                         \\\n\t(BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x) |                       \\\n\t BIT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(v))\n\n/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B */\n\n#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B 0\n#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B 0xff\n#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x)                             \\\n\t(((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B)                  \\\n\t << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B)\n#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B                               \\\n\t(BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B                          \\\n\t << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B)\n#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x)                       \\\n\t((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B))\n#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x)                         \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B) &              \\\n\t BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B)\n#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x, v)                      \\\n\t(BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x) |                    \\\n\t BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(v))\n\n/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B */\n#define BIT_PCIE_CFG_DISABLE_FC_WATCHDOG_TIMER_8814B BIT(7)\n\n#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B 0\n#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B 0x7\n#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x)                             \\\n\t(((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B)                  \\\n\t << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B)\n#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B                               \\\n\t(BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B                          \\\n\t << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B)\n#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x)                       \\\n\t((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B))\n#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x)                         \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B) &              \\\n\t BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B)\n#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x, v)                      \\\n\t(BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x) |                    \\\n\t BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(v))\n\n/* 2 REG_PCIE_CFG_L1_UNIT_SEL_8814B */\n\n#define BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B 0\n#define BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B 0xff\n#define BIT_PCIE_CFG_L1_UNIT_SEL_8814B(x)                                      \\\n\t(((x) & BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B)                           \\\n\t << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B)\n#define BITS_PCIE_CFG_L1_UNIT_SEL_8814B                                        \\\n\t(BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B                                   \\\n\t << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B)\n#define BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL_8814B(x)                                \\\n\t((x) & (~BITS_PCIE_CFG_L1_UNIT_SEL_8814B))\n#define BIT_GET_PCIE_CFG_L1_UNIT_SEL_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B) &                       \\\n\t BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B)\n#define BIT_SET_PCIE_CFG_L1_UNIT_SEL_8814B(x, v)                               \\\n\t(BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL_8814B(x) |                             \\\n\t BIT_PCIE_CFG_L1_UNIT_SEL_8814B(v))\n\n/* 2 REG_PCIE_CFG_MIN_CLKREQ_SEL_8814B */\n\n#define BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B 0\n#define BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B 0xf\n#define BIT_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x)                                   \\\n\t(((x) & BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B)                        \\\n\t << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B)\n#define BITS_PCIE_CFG_MIN_CLKREQ_SEL_8814B                                     \\\n\t(BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B                                \\\n\t << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B)\n#define BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x)                             \\\n\t((x) & (~BITS_PCIE_CFG_MIN_CLKREQ_SEL_8814B))\n#define BIT_GET_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x)                               \\\n\t(((x) >> BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B) &                    \\\n\t BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B)\n#define BIT_SET_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x, v)                            \\\n\t(BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x) |                          \\\n\t BIT_PCIE_CFG_MIN_CLKREQ_SEL_8814B(v))\n\n/* 2 REG_SDIO_TX_CTRL_8814B */\n\n#define BIT_SHIFT_SDIO_INT_TIMEOUT_8814B 16\n#define BIT_MASK_SDIO_INT_TIMEOUT_8814B 0xffff\n#define BIT_SDIO_INT_TIMEOUT_8814B(x)                                          \\\n\t(((x) & BIT_MASK_SDIO_INT_TIMEOUT_8814B)                               \\\n\t << BIT_SHIFT_SDIO_INT_TIMEOUT_8814B)\n#define BITS_SDIO_INT_TIMEOUT_8814B                                            \\\n\t(BIT_MASK_SDIO_INT_TIMEOUT_8814B << BIT_SHIFT_SDIO_INT_TIMEOUT_8814B)\n#define BIT_CLEAR_SDIO_INT_TIMEOUT_8814B(x)                                    \\\n\t((x) & (~BITS_SDIO_INT_TIMEOUT_8814B))\n#define BIT_GET_SDIO_INT_TIMEOUT_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8814B) &                           \\\n\t BIT_MASK_SDIO_INT_TIMEOUT_8814B)\n#define BIT_SET_SDIO_INT_TIMEOUT_8814B(x, v)                                   \\\n\t(BIT_CLEAR_SDIO_INT_TIMEOUT_8814B(x) | BIT_SDIO_INT_TIMEOUT_8814B(v))\n\n#define BIT_IO_ERR_STATUS_8814B BIT(15)\n#define BIT_REPLY_ERRCRC_IN_DATA_8814B BIT(9)\n#define BIT_EN_CMD53_OVERLAP_8814B BIT(8)\n#define BIT_REPLY_ERR_IN_R5_8814B BIT(7)\n#define BIT_R18A_EN_8814B BIT(6)\n#define BIT_SDIO_CMD_FORCE_VLD_8814B BIT(5)\n#define BIT_INIT_CMD_EN_8814B BIT(4)\n#define BIT_EN_RXDMA_MASK_INT_8814B BIT(2)\n#define BIT_EN_MASK_TIMER_8814B BIT(1)\n#define BIT_CMD_ERR_STOP_INT_EN_8814B BIT(0)\n\n/* 2 REG_SDIO_HIMR_8814B */\n#define BIT_SDIO_CRCERR_MSK_8814B BIT(31)\n#define BIT_SDIO_HSISR3_IND_MSK_8814B BIT(30)\n#define BIT_SDIO_HSISR2_IND_MSK_8814B BIT(29)\n#define BIT_SDIO_HEISR_IND_MSK_8814B BIT(28)\n#define BIT_SDIO_CTWEND_MSK_8814B BIT(27)\n#define BIT_SDIO_ATIMEND_E_MSK_8814B BIT(26)\n#define BIT_SDIIO_ATIMEND_MSK_8814B BIT(25)\n#define BIT_SDIO_OCPINT_MSK_8814B BIT(24)\n#define BIT_SDIO_PSTIMEOUT_MSK_8814B BIT(23)\n#define BIT_SDIO_GTINT4_MSK_8814B BIT(22)\n#define BIT_SDIO_GTINT3_MSK_8814B BIT(21)\n#define BIT_SDIO_HSISR_IND_MSK_8814B BIT(20)\n#define BIT_SDIO_CPWM2_MSK_8814B BIT(19)\n#define BIT_SDIO_CPWM1_MSK_8814B BIT(18)\n#define BIT_SDIO_C2HCMD_INT_MSK_8814B BIT(17)\n#define BIT_SDIO_BCNERLY_INT_MSK_8814B BIT(16)\n#define BIT_SDIO_TXBCNERR_MSK_8814B BIT(7)\n#define BIT_SDIO_TXBCNOK_MSK_8814B BIT(6)\n#define BIT_SDIO_RXFOVW_MSK_8814B BIT(5)\n#define BIT_SDIO_TXFOVW_MSK_8814B BIT(4)\n#define BIT_SDIO_RXERR_MSK_8814B BIT(3)\n#define BIT_SDIO_TXERR_MSK_8814B BIT(2)\n#define BIT_SDIO_AVAL_MSK_8814B BIT(1)\n#define BIT_RX_REQUEST_MSK_8814B BIT(0)\n\n/* 2 REG_SDIO_HISR_8814B */\n#define BIT_SDIO_CRCERR_8814B BIT(31)\n#define BIT_SDIO_HSISR3_IND_8814B BIT(30)\n#define BIT_SDIO_HSISR2_IND_8814B BIT(29)\n#define BIT_SDIO_HEISR_IND_8814B BIT(28)\n#define BIT_SDIO_CTWEND_8814B BIT(27)\n#define BIT_SDIO_ATIMEND_E_8814B BIT(26)\n#define BIT_SDIO_ATIMEND_8814B BIT(25)\n#define BIT_SDIO_OCPINT_8814B BIT(24)\n#define BIT_SDIO_PSTIMEOUT_8814B BIT(23)\n#define BIT_SDIO_GTINT4_8814B BIT(22)\n#define BIT_SDIO_GTINT3_8814B BIT(21)\n#define BIT_SDIO_HSISR_IND_8814B BIT(20)\n#define BIT_SDIO_CPWM2_8814B BIT(19)\n#define BIT_SDIO_CPWM1_8814B BIT(18)\n#define BIT_SDIO_C2HCMD_INT_8814B BIT(17)\n#define BIT_SDIO_BCNERLY_INT_8814B BIT(16)\n#define BIT_SDIO_TXBCNERR_8814B BIT(7)\n#define BIT_SDIO_TXBCNOK_8814B BIT(6)\n#define BIT_SDIO_RXFOVW_8814B BIT(5)\n#define BIT_SDIO_TXFOVW_8814B BIT(4)\n#define BIT_SDIO_RXERR_8814B BIT(3)\n#define BIT_SDIO_TXERR_8814B BIT(2)\n#define BIT_SDIO_AVAL_8814B BIT(1)\n#define BIT_RX_REQUEST_8814B BIT(0)\n\n/* 2 REG_SDIO_RX_REQ_LEN_8814B */\n\n#define BIT_SHIFT_RX_REQ_LEN_V1_8814B 0\n#define BIT_MASK_RX_REQ_LEN_V1_8814B 0x3ffff\n#define BIT_RX_REQ_LEN_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_RX_REQ_LEN_V1_8814B) << BIT_SHIFT_RX_REQ_LEN_V1_8814B)\n#define BITS_RX_REQ_LEN_V1_8814B                                               \\\n\t(BIT_MASK_RX_REQ_LEN_V1_8814B << BIT_SHIFT_RX_REQ_LEN_V1_8814B)\n#define BIT_CLEAR_RX_REQ_LEN_V1_8814B(x) ((x) & (~BITS_RX_REQ_LEN_V1_8814B))\n#define BIT_GET_RX_REQ_LEN_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8814B) & BIT_MASK_RX_REQ_LEN_V1_8814B)\n#define BIT_SET_RX_REQ_LEN_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_RX_REQ_LEN_V1_8814B(x) | BIT_RX_REQ_LEN_V1_8814B(v))\n\n/* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8814B */\n\n#define BIT_SHIFT_FREE_TXPG_SEQ_8814B 0\n#define BIT_MASK_FREE_TXPG_SEQ_8814B 0xff\n#define BIT_FREE_TXPG_SEQ_8814B(x)                                             \\\n\t(((x) & BIT_MASK_FREE_TXPG_SEQ_8814B) << BIT_SHIFT_FREE_TXPG_SEQ_8814B)\n#define BITS_FREE_TXPG_SEQ_8814B                                               \\\n\t(BIT_MASK_FREE_TXPG_SEQ_8814B << BIT_SHIFT_FREE_TXPG_SEQ_8814B)\n#define BIT_CLEAR_FREE_TXPG_SEQ_8814B(x) ((x) & (~BITS_FREE_TXPG_SEQ_8814B))\n#define BIT_GET_FREE_TXPG_SEQ_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8814B) & BIT_MASK_FREE_TXPG_SEQ_8814B)\n#define BIT_SET_FREE_TXPG_SEQ_8814B(x, v)                                      \\\n\t(BIT_CLEAR_FREE_TXPG_SEQ_8814B(x) | BIT_FREE_TXPG_SEQ_8814B(v))\n\n/* 2 REG_SDIO_FREE_TXPG_8814B */\n\n#define BIT_SHIFT_MID_FREEPG_V1_8814B 16\n#define BIT_MASK_MID_FREEPG_V1_8814B 0xfff\n#define BIT_MID_FREEPG_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_MID_FREEPG_V1_8814B) << BIT_SHIFT_MID_FREEPG_V1_8814B)\n#define BITS_MID_FREEPG_V1_8814B                                               \\\n\t(BIT_MASK_MID_FREEPG_V1_8814B << BIT_SHIFT_MID_FREEPG_V1_8814B)\n#define BIT_CLEAR_MID_FREEPG_V1_8814B(x) ((x) & (~BITS_MID_FREEPG_V1_8814B))\n#define BIT_GET_MID_FREEPG_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MID_FREEPG_V1_8814B) & BIT_MASK_MID_FREEPG_V1_8814B)\n#define BIT_SET_MID_FREEPG_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_MID_FREEPG_V1_8814B(x) | BIT_MID_FREEPG_V1_8814B(v))\n\n#define BIT_SHIFT_HIQ_FREEPG_V1_8814B 0\n#define BIT_MASK_HIQ_FREEPG_V1_8814B 0xfff\n#define BIT_HIQ_FREEPG_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_HIQ_FREEPG_V1_8814B) << BIT_SHIFT_HIQ_FREEPG_V1_8814B)\n#define BITS_HIQ_FREEPG_V1_8814B                                               \\\n\t(BIT_MASK_HIQ_FREEPG_V1_8814B << BIT_SHIFT_HIQ_FREEPG_V1_8814B)\n#define BIT_CLEAR_HIQ_FREEPG_V1_8814B(x) ((x) & (~BITS_HIQ_FREEPG_V1_8814B))\n#define BIT_GET_HIQ_FREEPG_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8814B) & BIT_MASK_HIQ_FREEPG_V1_8814B)\n#define BIT_SET_HIQ_FREEPG_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_HIQ_FREEPG_V1_8814B(x) | BIT_HIQ_FREEPG_V1_8814B(v))\n\n/* 2 REG_SDIO_FREE_TXPG2_8814B */\n\n#define BIT_SHIFT_PUB_FREEPG_V1_8814B 16\n#define BIT_MASK_PUB_FREEPG_V1_8814B 0xfff\n#define BIT_PUB_FREEPG_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_PUB_FREEPG_V1_8814B) << BIT_SHIFT_PUB_FREEPG_V1_8814B)\n#define BITS_PUB_FREEPG_V1_8814B                                               \\\n\t(BIT_MASK_PUB_FREEPG_V1_8814B << BIT_SHIFT_PUB_FREEPG_V1_8814B)\n#define BIT_CLEAR_PUB_FREEPG_V1_8814B(x) ((x) & (~BITS_PUB_FREEPG_V1_8814B))\n#define BIT_GET_PUB_FREEPG_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PUB_FREEPG_V1_8814B) & BIT_MASK_PUB_FREEPG_V1_8814B)\n#define BIT_SET_PUB_FREEPG_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_PUB_FREEPG_V1_8814B(x) | BIT_PUB_FREEPG_V1_8814B(v))\n\n#define BIT_SHIFT_LOW_FREEPG_V1_8814B 0\n#define BIT_MASK_LOW_FREEPG_V1_8814B 0xfff\n#define BIT_LOW_FREEPG_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_LOW_FREEPG_V1_8814B) << BIT_SHIFT_LOW_FREEPG_V1_8814B)\n#define BITS_LOW_FREEPG_V1_8814B                                               \\\n\t(BIT_MASK_LOW_FREEPG_V1_8814B << BIT_SHIFT_LOW_FREEPG_V1_8814B)\n#define BIT_CLEAR_LOW_FREEPG_V1_8814B(x) ((x) & (~BITS_LOW_FREEPG_V1_8814B))\n#define BIT_GET_LOW_FREEPG_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_LOW_FREEPG_V1_8814B) & BIT_MASK_LOW_FREEPG_V1_8814B)\n#define BIT_SET_LOW_FREEPG_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_LOW_FREEPG_V1_8814B(x) | BIT_LOW_FREEPG_V1_8814B(v))\n\n/* 2 REG_SDIO_OQT_FREE_TXPG_V1_8814B */\n\n#define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B 24\n#define BIT_MASK_NOAC_OQT_FREEPG_V1_8814B 0xff\n#define BIT_NOAC_OQT_FREEPG_V1_8814B(x)                                        \\\n\t(((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8814B)                             \\\n\t << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B)\n#define BITS_NOAC_OQT_FREEPG_V1_8814B                                          \\\n\t(BIT_MASK_NOAC_OQT_FREEPG_V1_8814B                                     \\\n\t << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B)\n#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8814B(x)                                  \\\n\t((x) & (~BITS_NOAC_OQT_FREEPG_V1_8814B))\n#define BIT_GET_NOAC_OQT_FREEPG_V1_8814B(x)                                    \\\n\t(((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B) &                         \\\n\t BIT_MASK_NOAC_OQT_FREEPG_V1_8814B)\n#define BIT_SET_NOAC_OQT_FREEPG_V1_8814B(x, v)                                 \\\n\t(BIT_CLEAR_NOAC_OQT_FREEPG_V1_8814B(x) |                               \\\n\t BIT_NOAC_OQT_FREEPG_V1_8814B(v))\n\n#define BIT_SHIFT_AC_OQT_FREEPG_V1_8814B 16\n#define BIT_MASK_AC_OQT_FREEPG_V1_8814B 0xff\n#define BIT_AC_OQT_FREEPG_V1_8814B(x)                                          \\\n\t(((x) & BIT_MASK_AC_OQT_FREEPG_V1_8814B)                               \\\n\t << BIT_SHIFT_AC_OQT_FREEPG_V1_8814B)\n#define BITS_AC_OQT_FREEPG_V1_8814B                                            \\\n\t(BIT_MASK_AC_OQT_FREEPG_V1_8814B << BIT_SHIFT_AC_OQT_FREEPG_V1_8814B)\n#define BIT_CLEAR_AC_OQT_FREEPG_V1_8814B(x)                                    \\\n\t((x) & (~BITS_AC_OQT_FREEPG_V1_8814B))\n#define BIT_GET_AC_OQT_FREEPG_V1_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8814B) &                           \\\n\t BIT_MASK_AC_OQT_FREEPG_V1_8814B)\n#define BIT_SET_AC_OQT_FREEPG_V1_8814B(x, v)                                   \\\n\t(BIT_CLEAR_AC_OQT_FREEPG_V1_8814B(x) | BIT_AC_OQT_FREEPG_V1_8814B(v))\n\n#define BIT_SHIFT_EXQ_FREEPG_V1_8814B 0\n#define BIT_MASK_EXQ_FREEPG_V1_8814B 0xfff\n#define BIT_EXQ_FREEPG_V1_8814B(x)                                             \\\n\t(((x) & BIT_MASK_EXQ_FREEPG_V1_8814B) << BIT_SHIFT_EXQ_FREEPG_V1_8814B)\n#define BITS_EXQ_FREEPG_V1_8814B                                               \\\n\t(BIT_MASK_EXQ_FREEPG_V1_8814B << BIT_SHIFT_EXQ_FREEPG_V1_8814B)\n#define BIT_CLEAR_EXQ_FREEPG_V1_8814B(x) ((x) & (~BITS_EXQ_FREEPG_V1_8814B))\n#define BIT_GET_EXQ_FREEPG_V1_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8814B) & BIT_MASK_EXQ_FREEPG_V1_8814B)\n#define BIT_SET_EXQ_FREEPG_V1_8814B(x, v)                                      \\\n\t(BIT_CLEAR_EXQ_FREEPG_V1_8814B(x) | BIT_EXQ_FREEPG_V1_8814B(v))\n\n/* 2 REG_SDIO_HTSFR_INFO_8814B */\n\n#define BIT_SHIFT_HTSFR1_8814B 16\n#define BIT_MASK_HTSFR1_8814B 0xffff\n#define BIT_HTSFR1_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_HTSFR1_8814B) << BIT_SHIFT_HTSFR1_8814B)\n#define BITS_HTSFR1_8814B (BIT_MASK_HTSFR1_8814B << BIT_SHIFT_HTSFR1_8814B)\n#define BIT_CLEAR_HTSFR1_8814B(x) ((x) & (~BITS_HTSFR1_8814B))\n#define BIT_GET_HTSFR1_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_HTSFR1_8814B) & BIT_MASK_HTSFR1_8814B)\n#define BIT_SET_HTSFR1_8814B(x, v)                                             \\\n\t(BIT_CLEAR_HTSFR1_8814B(x) | BIT_HTSFR1_8814B(v))\n\n#define BIT_SHIFT_HTSFR0_8814B 0\n#define BIT_MASK_HTSFR0_8814B 0xffff\n#define BIT_HTSFR0_8814B(x)                                                    \\\n\t(((x) & BIT_MASK_HTSFR0_8814B) << BIT_SHIFT_HTSFR0_8814B)\n#define BITS_HTSFR0_8814B (BIT_MASK_HTSFR0_8814B << BIT_SHIFT_HTSFR0_8814B)\n#define BIT_CLEAR_HTSFR0_8814B(x) ((x) & (~BITS_HTSFR0_8814B))\n#define BIT_GET_HTSFR0_8814B(x)                                                \\\n\t(((x) >> BIT_SHIFT_HTSFR0_8814B) & BIT_MASK_HTSFR0_8814B)\n#define BIT_SET_HTSFR0_8814B(x, v)                                             \\\n\t(BIT_CLEAR_HTSFR0_8814B(x) | BIT_HTSFR0_8814B(v))\n\n/* 2 REG_SDIO_HCPWM1_V2_8814B */\n#define BIT_TOGGLE_8814B BIT(7)\n#define BIT_CUR_PS_8814B BIT(0)\n\n/* 2 REG_SDIO_HCPWM2_V2_8814B */\n\n/* 2 REG_SDIO_INDIRECT_REG_CFG_8814B */\n#define BIT_INDIRECT_REG_RDY_8814B BIT(20)\n#define BIT_INDIRECT_REG_R_8814B BIT(19)\n#define BIT_INDIRECT_REG_W_8814B BIT(18)\n\n#define BIT_SHIFT_INDIRECT_REG_SIZE_8814B 16\n#define BIT_MASK_INDIRECT_REG_SIZE_8814B 0x3\n#define BIT_INDIRECT_REG_SIZE_8814B(x)                                         \\\n\t(((x) & BIT_MASK_INDIRECT_REG_SIZE_8814B)                              \\\n\t << BIT_SHIFT_INDIRECT_REG_SIZE_8814B)\n#define BITS_INDIRECT_REG_SIZE_8814B                                           \\\n\t(BIT_MASK_INDIRECT_REG_SIZE_8814B << BIT_SHIFT_INDIRECT_REG_SIZE_8814B)\n#define BIT_CLEAR_INDIRECT_REG_SIZE_8814B(x)                                   \\\n\t((x) & (~BITS_INDIRECT_REG_SIZE_8814B))\n#define BIT_GET_INDIRECT_REG_SIZE_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8814B) &                          \\\n\t BIT_MASK_INDIRECT_REG_SIZE_8814B)\n#define BIT_SET_INDIRECT_REG_SIZE_8814B(x, v)                                  \\\n\t(BIT_CLEAR_INDIRECT_REG_SIZE_8814B(x) | BIT_INDIRECT_REG_SIZE_8814B(v))\n\n#define BIT_SHIFT_INDIRECT_REG_ADDR_8814B 0\n#define BIT_MASK_INDIRECT_REG_ADDR_8814B 0xffff\n#define BIT_INDIRECT_REG_ADDR_8814B(x)                                         \\\n\t(((x) & BIT_MASK_INDIRECT_REG_ADDR_8814B)                              \\\n\t << BIT_SHIFT_INDIRECT_REG_ADDR_8814B)\n#define BITS_INDIRECT_REG_ADDR_8814B                                           \\\n\t(BIT_MASK_INDIRECT_REG_ADDR_8814B << BIT_SHIFT_INDIRECT_REG_ADDR_8814B)\n#define BIT_CLEAR_INDIRECT_REG_ADDR_8814B(x)                                   \\\n\t((x) & (~BITS_INDIRECT_REG_ADDR_8814B))\n#define BIT_GET_INDIRECT_REG_ADDR_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8814B) &                          \\\n\t BIT_MASK_INDIRECT_REG_ADDR_8814B)\n#define BIT_SET_INDIRECT_REG_ADDR_8814B(x, v)                                  \\\n\t(BIT_CLEAR_INDIRECT_REG_ADDR_8814B(x) | BIT_INDIRECT_REG_ADDR_8814B(v))\n\n/* 2 REG_SDIO_INDIRECT_REG_DATA_8814B */\n\n#define BIT_SHIFT_INDIRECT_REG_DATA_8814B 0\n#define BIT_MASK_INDIRECT_REG_DATA_8814B 0xffffffffL\n#define BIT_INDIRECT_REG_DATA_8814B(x)                                         \\\n\t(((x) & BIT_MASK_INDIRECT_REG_DATA_8814B)                              \\\n\t << BIT_SHIFT_INDIRECT_REG_DATA_8814B)\n#define BITS_INDIRECT_REG_DATA_8814B                                           \\\n\t(BIT_MASK_INDIRECT_REG_DATA_8814B << BIT_SHIFT_INDIRECT_REG_DATA_8814B)\n#define BIT_CLEAR_INDIRECT_REG_DATA_8814B(x)                                   \\\n\t((x) & (~BITS_INDIRECT_REG_DATA_8814B))\n#define BIT_GET_INDIRECT_REG_DATA_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8814B) &                          \\\n\t BIT_MASK_INDIRECT_REG_DATA_8814B)\n#define BIT_SET_INDIRECT_REG_DATA_8814B(x, v)                                  \\\n\t(BIT_CLEAR_INDIRECT_REG_DATA_8814B(x) | BIT_INDIRECT_REG_DATA_8814B(v))\n\n/* 2 REG_SDIO_H2C_8814B */\n\n#define BIT_SHIFT_SDIO_H2C_MSG_8814B 0\n#define BIT_MASK_SDIO_H2C_MSG_8814B 0xffffffffL\n#define BIT_SDIO_H2C_MSG_8814B(x)                                              \\\n\t(((x) & BIT_MASK_SDIO_H2C_MSG_8814B) << BIT_SHIFT_SDIO_H2C_MSG_8814B)\n#define BITS_SDIO_H2C_MSG_8814B                                                \\\n\t(BIT_MASK_SDIO_H2C_MSG_8814B << BIT_SHIFT_SDIO_H2C_MSG_8814B)\n#define BIT_CLEAR_SDIO_H2C_MSG_8814B(x) ((x) & (~BITS_SDIO_H2C_MSG_8814B))\n#define BIT_GET_SDIO_H2C_MSG_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SDIO_H2C_MSG_8814B) & BIT_MASK_SDIO_H2C_MSG_8814B)\n#define BIT_SET_SDIO_H2C_MSG_8814B(x, v)                                       \\\n\t(BIT_CLEAR_SDIO_H2C_MSG_8814B(x) | BIT_SDIO_H2C_MSG_8814B(v))\n\n/* 2 REG_SDIO_C2H_8814B */\n\n#define BIT_SHIFT_SDIO_C2H_MSG_8814B 0\n#define BIT_MASK_SDIO_C2H_MSG_8814B 0xffffffffL\n#define BIT_SDIO_C2H_MSG_8814B(x)                                              \\\n\t(((x) & BIT_MASK_SDIO_C2H_MSG_8814B) << BIT_SHIFT_SDIO_C2H_MSG_8814B)\n#define BITS_SDIO_C2H_MSG_8814B                                                \\\n\t(BIT_MASK_SDIO_C2H_MSG_8814B << BIT_SHIFT_SDIO_C2H_MSG_8814B)\n#define BIT_CLEAR_SDIO_C2H_MSG_8814B(x) ((x) & (~BITS_SDIO_C2H_MSG_8814B))\n#define BIT_GET_SDIO_C2H_MSG_8814B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SDIO_C2H_MSG_8814B) & BIT_MASK_SDIO_C2H_MSG_8814B)\n#define BIT_SET_SDIO_C2H_MSG_8814B(x, v)                                       \\\n\t(BIT_CLEAR_SDIO_C2H_MSG_8814B(x) | BIT_SDIO_C2H_MSG_8814B(v))\n\n/* 2 REG_SDIO_HRPWM1_8814B */\n#define BIT_TOGGLE_8814B BIT(7)\n#define BIT_ACK_8814B BIT(6)\n#define BIT_REQ_PS_8814B BIT(0)\n\n/* 2 REG_SDIO_HRPWM2_8814B */\n\n/* 2 REG_SDIO_HPS_CLKR_8814B */\n\n/* 2 REG_SDIO_BUS_CTRL_8814B */\n#define BIT_PAD_CLK_XHGE_EN_8814B BIT(3)\n#define BIT_INTER_CLK_EN_8814B BIT(2)\n#define BIT_EN_RPT_TXCRC_8814B BIT(1)\n#define BIT_DIS_RXDMA_STS_8814B BIT(0)\n\n/* 2 REG_SDIO_HSUS_CTRL_8814B */\n#define BIT_INTR_CTRL_8814B BIT(4)\n#define BIT_SDIO_VOLTAGE_8814B BIT(3)\n#define BIT_BYPASS_INIT_8814B BIT(2)\n#define BIT_HCI_RESUME_RDY_8814B BIT(1)\n#define BIT_HCI_SUS_REQ_8814B BIT(0)\n\n/* 2 REG_SDIO_RESPONSE_TIMER_8814B */\n\n#define BIT_SHIFT_CMDIN_2RESP_TIMER_8814B 0\n#define BIT_MASK_CMDIN_2RESP_TIMER_8814B 0xffff\n#define BIT_CMDIN_2RESP_TIMER_8814B(x)                                         \\\n\t(((x) & BIT_MASK_CMDIN_2RESP_TIMER_8814B)                              \\\n\t << BIT_SHIFT_CMDIN_2RESP_TIMER_8814B)\n#define BITS_CMDIN_2RESP_TIMER_8814B                                           \\\n\t(BIT_MASK_CMDIN_2RESP_TIMER_8814B << BIT_SHIFT_CMDIN_2RESP_TIMER_8814B)\n#define BIT_CLEAR_CMDIN_2RESP_TIMER_8814B(x)                                   \\\n\t((x) & (~BITS_CMDIN_2RESP_TIMER_8814B))\n#define BIT_GET_CMDIN_2RESP_TIMER_8814B(x)                                     \\\n\t(((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8814B) &                          \\\n\t BIT_MASK_CMDIN_2RESP_TIMER_8814B)\n#define BIT_SET_CMDIN_2RESP_TIMER_8814B(x, v)                                  \\\n\t(BIT_CLEAR_CMDIN_2RESP_TIMER_8814B(x) | BIT_CMDIN_2RESP_TIMER_8814B(v))\n\n/* 2 REG_SDIO_CMD_CRC_8814B */\n\n#define BIT_SHIFT_SDIO_CMD_CRC_V1_8814B 0\n#define BIT_MASK_SDIO_CMD_CRC_V1_8814B 0xff\n#define BIT_SDIO_CMD_CRC_V1_8814B(x)                                           \\\n\t(((x) & BIT_MASK_SDIO_CMD_CRC_V1_8814B)                                \\\n\t << BIT_SHIFT_SDIO_CMD_CRC_V1_8814B)\n#define BITS_SDIO_CMD_CRC_V1_8814B                                             \\\n\t(BIT_MASK_SDIO_CMD_CRC_V1_8814B << BIT_SHIFT_SDIO_CMD_CRC_V1_8814B)\n#define BIT_CLEAR_SDIO_CMD_CRC_V1_8814B(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8814B))\n#define BIT_GET_SDIO_CMD_CRC_V1_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8814B) &                            \\\n\t BIT_MASK_SDIO_CMD_CRC_V1_8814B)\n#define BIT_SET_SDIO_CMD_CRC_V1_8814B(x, v)                                    \\\n\t(BIT_CLEAR_SDIO_CMD_CRC_V1_8814B(x) | BIT_SDIO_CMD_CRC_V1_8814B(v))\n\n/* 2 REG_SDIO_HSISR_8814B */\n#define BIT_DRV_WLAN_INT_CLR_8814B BIT(1)\n#define BIT_DRV_WLAN_INT_8814B BIT(0)\n\n/* 2 REG_SDIO_ERR_RPT_8814B */\n#define BIT_HR_FF_OVF_8814B BIT(6)\n#define BIT_HR_FF_UDN_8814B BIT(5)\n#define BIT_TXDMA_BUSY_ERR_8814B BIT(4)\n#define BIT_TXDMA_VLD_ERR_8814B BIT(3)\n#define BIT_QSEL_UNKNOWN_ERR_8814B BIT(2)\n#define BIT_QSEL_MIS_ERR_8814B BIT(1)\n#define BIT_SDIO_OVERRD_ERR_8814B BIT(0)\n\n/* 2 REG_SDIO_CMD_ERRCNT_8814B */\n\n#define BIT_SHIFT_CMD_CRC_ERR_CNT_8814B 0\n#define BIT_MASK_CMD_CRC_ERR_CNT_8814B 0xff\n#define BIT_CMD_CRC_ERR_CNT_8814B(x)                                           \\\n\t(((x) & BIT_MASK_CMD_CRC_ERR_CNT_8814B)                                \\\n\t << BIT_SHIFT_CMD_CRC_ERR_CNT_8814B)\n#define BITS_CMD_CRC_ERR_CNT_8814B                                             \\\n\t(BIT_MASK_CMD_CRC_ERR_CNT_8814B << BIT_SHIFT_CMD_CRC_ERR_CNT_8814B)\n#define BIT_CLEAR_CMD_CRC_ERR_CNT_8814B(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8814B))\n#define BIT_GET_CMD_CRC_ERR_CNT_8814B(x)                                       \\\n\t(((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8814B) &                            \\\n\t BIT_MASK_CMD_CRC_ERR_CNT_8814B)\n#define BIT_SET_CMD_CRC_ERR_CNT_8814B(x, v)                                    \\\n\t(BIT_CLEAR_CMD_CRC_ERR_CNT_8814B(x) | BIT_CMD_CRC_ERR_CNT_8814B(v))\n\n/* 2 REG_SDIO_DATA_ERRCNT_8814B */\n\n#define BIT_SHIFT_DATA_CRC_ERR_CNT_8814B 0\n#define BIT_MASK_DATA_CRC_ERR_CNT_8814B 0xff\n#define BIT_DATA_CRC_ERR_CNT_8814B(x)                                          \\\n\t(((x) & BIT_MASK_DATA_CRC_ERR_CNT_8814B)                               \\\n\t << BIT_SHIFT_DATA_CRC_ERR_CNT_8814B)\n#define BITS_DATA_CRC_ERR_CNT_8814B                                            \\\n\t(BIT_MASK_DATA_CRC_ERR_CNT_8814B << BIT_SHIFT_DATA_CRC_ERR_CNT_8814B)\n#define BIT_CLEAR_DATA_CRC_ERR_CNT_8814B(x)                                    \\\n\t((x) & (~BITS_DATA_CRC_ERR_CNT_8814B))\n#define BIT_GET_DATA_CRC_ERR_CNT_8814B(x)                                      \\\n\t(((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8814B) &                           \\\n\t BIT_MASK_DATA_CRC_ERR_CNT_8814B)\n#define BIT_SET_DATA_CRC_ERR_CNT_8814B(x, v)                                   \\\n\t(BIT_CLEAR_DATA_CRC_ERR_CNT_8814B(x) | BIT_DATA_CRC_ERR_CNT_8814B(v))\n\n/* 2 REG_SDIO_CMD_ERR_CONTENT_8814B */\n\n#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B 0\n#define BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B 0xffffffffffL\n#define BIT_SDIO_CMD_ERR_CONTENT_8814B(x)                                      \\\n\t(((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B)                           \\\n\t << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B)\n#define BITS_SDIO_CMD_ERR_CONTENT_8814B                                        \\\n\t(BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B                                   \\\n\t << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B)\n#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8814B(x)                                \\\n\t((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8814B))\n#define BIT_GET_SDIO_CMD_ERR_CONTENT_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B) &                       \\\n\t BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B)\n#define BIT_SET_SDIO_CMD_ERR_CONTENT_8814B(x, v)                               \\\n\t(BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8814B(x) |                             \\\n\t BIT_SDIO_CMD_ERR_CONTENT_8814B(v))\n\n/* 2 REG_SDIO_CRC_ERR_IDX_8814B */\n#define BIT_D3_CRC_ERR_8814B BIT(4)\n#define BIT_D2_CRC_ERR_8814B BIT(3)\n#define BIT_D1_CRC_ERR_8814B BIT(2)\n#define BIT_D0_CRC_ERR_8814B BIT(1)\n#define BIT_CMD_CRC_ERR_8814B BIT(0)\n\n/* 2 REG_SDIO_DATA_CRC_8814B */\n\n#define BIT_SHIFT_SDIO_DATA_CRC_8814B 0\n#define BIT_MASK_SDIO_DATA_CRC_8814B 0xffff\n#define BIT_SDIO_DATA_CRC_8814B(x)                                             \\\n\t(((x) & BIT_MASK_SDIO_DATA_CRC_8814B) << BIT_SHIFT_SDIO_DATA_CRC_8814B)\n#define BITS_SDIO_DATA_CRC_8814B                                               \\\n\t(BIT_MASK_SDIO_DATA_CRC_8814B << BIT_SHIFT_SDIO_DATA_CRC_8814B)\n#define BIT_CLEAR_SDIO_DATA_CRC_8814B(x) ((x) & (~BITS_SDIO_DATA_CRC_8814B))\n#define BIT_GET_SDIO_DATA_CRC_8814B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SDIO_DATA_CRC_8814B) & BIT_MASK_SDIO_DATA_CRC_8814B)\n#define BIT_SET_SDIO_DATA_CRC_8814B(x, v)                                      \\\n\t(BIT_CLEAR_SDIO_DATA_CRC_8814B(x) | BIT_SDIO_DATA_CRC_8814B(v))\n\n/* 2 REG_SDIO_DATA_REPLY_TIME_8814B */\n\n#define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B 0\n#define BIT_MASK_SDIO_DATA_REPLY_TIME_8814B 0x7\n#define BIT_SDIO_DATA_REPLY_TIME_8814B(x)                                      \\\n\t(((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8814B)                           \\\n\t << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B)\n#define BITS_SDIO_DATA_REPLY_TIME_8814B                                        \\\n\t(BIT_MASK_SDIO_DATA_REPLY_TIME_8814B                                   \\\n\t << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B)\n#define BIT_CLEAR_SDIO_DATA_REPLY_TIME_8814B(x)                                \\\n\t((x) & (~BITS_SDIO_DATA_REPLY_TIME_8814B))\n#define BIT_GET_SDIO_DATA_REPLY_TIME_8814B(x)                                  \\\n\t(((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B) &                       \\\n\t BIT_MASK_SDIO_DATA_REPLY_TIME_8814B)\n#define BIT_SET_SDIO_DATA_REPLY_TIME_8814B(x, v)                               \\\n\t(BIT_CLEAR_SDIO_DATA_REPLY_TIME_8814B(x) |                             \\\n\t BIT_SDIO_DATA_REPLY_TIME_8814B(v))\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_bit_8821c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef __INC_HALMAC_BIT_8821C_H\n#define __INC_HALMAC_BIT_8821C_H\n\n#define CPU_OPT_WIDTH 0x1F\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_SYS_ISO_CTRL_8821C */\n#define BIT_PWC_EV12V_8821C BIT(15)\n#define BIT_PWC_EV25V_8821C BIT(14)\n#define BIT_PA33V_EN_8821C BIT(13)\n#define BIT_PA12V_EN_8821C BIT(12)\n#define BIT_UA33V_EN_8821C BIT(11)\n#define BIT_UA12V_EN_8821C BIT(10)\n#define BIT_ISO_RFDIO_8821C BIT(9)\n#define BIT_ISO_EB2CORE_8821C BIT(8)\n#define BIT_ISO_DIOE_8821C BIT(7)\n#define BIT_ISO_WLPON2PP_8821C BIT(6)\n#define BIT_ISO_IP2MAC_WA2PP_8821C BIT(5)\n#define BIT_ISO_PD2CORE_8821C BIT(4)\n#define BIT_ISO_PA2PCIE_8821C BIT(3)\n#define BIT_ISO_UD2CORE_8821C BIT(2)\n#define BIT_ISO_UA2USB_8821C BIT(1)\n#define BIT_ISO_WD2PP_8821C BIT(0)\n\n/* 2 REG_SYS_FUNC_EN_8821C */\n#define BIT_FEN_MREGEN_8821C BIT(15)\n#define BIT_FEN_HWPDN_8821C BIT(14)\n#define BIT_EN_25_1_8821C BIT(13)\n#define BIT_FEN_ELDR_8821C BIT(12)\n#define BIT_FEN_DCORE_8821C BIT(11)\n#define BIT_FEN_CPUEN_8821C BIT(10)\n#define BIT_FEN_DIOE_8821C BIT(9)\n#define BIT_FEN_PCIED_8821C BIT(8)\n#define BIT_FEN_PPLL_8821C BIT(7)\n#define BIT_FEN_PCIEA_8821C BIT(6)\n#define BIT_FEN_DIO_PCIE_8821C BIT(5)\n#define BIT_FEN_USBD_8821C BIT(4)\n#define BIT_FEN_UPLL_8821C BIT(3)\n#define BIT_FEN_USBA_8821C BIT(2)\n#define BIT_FEN_BB_GLB_RSTN_8821C BIT(1)\n#define BIT_FEN_BBRSTB_8821C BIT(0)\n\n/* 2 REG_SYS_PW_CTRL_8821C */\n#define BIT_SOP_EABM_8821C BIT(31)\n#define BIT_SOP_ACKF_8821C BIT(30)\n#define BIT_SOP_ERCK_8821C BIT(29)\n#define BIT_SOP_ESWR_8821C BIT(28)\n#define BIT_SOP_PWMM_8821C BIT(27)\n#define BIT_SOP_EECK_8821C BIT(26)\n#define BIT_SOP_EXTL_8821C BIT(24)\n#define BIT_SYM_OP_RING_12M_8821C BIT(22)\n#define BIT_ROP_SWPR_8821C BIT(21)\n#define BIT_DIS_HW_LPLDM_8821C BIT(20)\n#define BIT_OPT_SWRST_WLMCU_8821C BIT(19)\n#define BIT_RDY_SYSPWR_8821C BIT(17)\n#define BIT_EN_WLON_8821C BIT(16)\n#define BIT_APDM_HPDN_8821C BIT(15)\n#define BIT_AFSM_PCIE_SUS_EN_8821C BIT(12)\n#define BIT_AFSM_WLSUS_EN_8821C BIT(11)\n#define BIT_APFM_SWLPS_8821C BIT(10)\n#define BIT_APFM_OFFMAC_8821C BIT(9)\n#define BIT_APFN_ONMAC_8821C BIT(8)\n#define BIT_CHIP_PDN_EN_8821C BIT(7)\n#define BIT_RDY_MACDIS_8821C BIT(6)\n#define BIT_RING_CLK_12M_EN_8821C BIT(4)\n#define BIT_PFM_WOWL_8821C BIT(3)\n#define BIT_PFM_LDKP_8821C BIT(2)\n#define BIT_WL_HCI_ALD_8821C BIT(1)\n#define BIT_PFM_LDALL_8821C BIT(0)\n\n/* 2 REG_SYS_CLK_CTRL_8821C */\n#define BIT_LDO_DUMMY_8821C BIT(15)\n#define BIT_CPU_CLK_EN_8821C BIT(14)\n#define BIT_SYMREG_CLK_EN_8821C BIT(13)\n#define BIT_HCI_CLK_EN_8821C BIT(12)\n#define BIT_MAC_CLK_EN_8821C BIT(11)\n#define BIT_SEC_CLK_EN_8821C BIT(10)\n#define BIT_PHY_SSC_RSTB_8821C BIT(9)\n#define BIT_EXT_32K_EN_8821C BIT(8)\n#define BIT_WL_CLK_TEST_8821C BIT(7)\n#define BIT_OP_SPS_PWM_EN_8821C BIT(6)\n#define BIT_LOADER_CLK_EN_8821C BIT(5)\n#define BIT_MACSLP_8821C BIT(4)\n#define BIT_WAKEPAD_EN_8821C BIT(3)\n#define BIT_ROMD16V_EN_8821C BIT(2)\n#define BIT_CKANA12M_EN_8821C BIT(1)\n#define BIT_CNTD16V_EN_8821C BIT(0)\n\n/* 2 REG_SYS_EEPROM_CTRL_8821C */\n\n#define BIT_SHIFT_VPDIDX_8821C 8\n#define BIT_MASK_VPDIDX_8821C 0xff\n#define BIT_VPDIDX_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_VPDIDX_8821C) << BIT_SHIFT_VPDIDX_8821C)\n#define BITS_VPDIDX_8821C (BIT_MASK_VPDIDX_8821C << BIT_SHIFT_VPDIDX_8821C)\n#define BIT_CLEAR_VPDIDX_8821C(x) ((x) & (~BITS_VPDIDX_8821C))\n#define BIT_GET_VPDIDX_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_VPDIDX_8821C) & BIT_MASK_VPDIDX_8821C)\n#define BIT_SET_VPDIDX_8821C(x, v)                                             \\\n\t(BIT_CLEAR_VPDIDX_8821C(x) | BIT_VPDIDX_8821C(v))\n\n#define BIT_SHIFT_EEM1_0_8821C 6\n#define BIT_MASK_EEM1_0_8821C 0x3\n#define BIT_EEM1_0_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_EEM1_0_8821C) << BIT_SHIFT_EEM1_0_8821C)\n#define BITS_EEM1_0_8821C (BIT_MASK_EEM1_0_8821C << BIT_SHIFT_EEM1_0_8821C)\n#define BIT_CLEAR_EEM1_0_8821C(x) ((x) & (~BITS_EEM1_0_8821C))\n#define BIT_GET_EEM1_0_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_EEM1_0_8821C) & BIT_MASK_EEM1_0_8821C)\n#define BIT_SET_EEM1_0_8821C(x, v)                                             \\\n\t(BIT_CLEAR_EEM1_0_8821C(x) | BIT_EEM1_0_8821C(v))\n\n#define BIT_AUTOLOAD_SUS_8821C BIT(5)\n#define BIT_EERPOMSEL_8821C BIT(4)\n#define BIT_EECS_V1_8821C BIT(3)\n#define BIT_EESK_V1_8821C BIT(2)\n#define BIT_EEDI_V1_8821C BIT(1)\n#define BIT_EEDO_V1_8821C BIT(0)\n\n/* 2 REG_EE_VPD_8821C */\n\n#define BIT_SHIFT_VPD_DATA_8821C 0\n#define BIT_MASK_VPD_DATA_8821C 0xffffffffL\n#define BIT_VPD_DATA_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_VPD_DATA_8821C) << BIT_SHIFT_VPD_DATA_8821C)\n#define BITS_VPD_DATA_8821C                                                    \\\n\t(BIT_MASK_VPD_DATA_8821C << BIT_SHIFT_VPD_DATA_8821C)\n#define BIT_CLEAR_VPD_DATA_8821C(x) ((x) & (~BITS_VPD_DATA_8821C))\n#define BIT_GET_VPD_DATA_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_VPD_DATA_8821C) & BIT_MASK_VPD_DATA_8821C)\n#define BIT_SET_VPD_DATA_8821C(x, v)                                           \\\n\t(BIT_CLEAR_VPD_DATA_8821C(x) | BIT_VPD_DATA_8821C(v))\n\n/* 2 REG_SYS_SWR_CTRL1_8821C */\n#define BIT_C2_L_BIT0_8821C BIT(31)\n\n#define BIT_SHIFT_C1_L_8821C 29\n#define BIT_MASK_C1_L_8821C 0x3\n#define BIT_C1_L_8821C(x) (((x) & BIT_MASK_C1_L_8821C) << BIT_SHIFT_C1_L_8821C)\n#define BITS_C1_L_8821C (BIT_MASK_C1_L_8821C << BIT_SHIFT_C1_L_8821C)\n#define BIT_CLEAR_C1_L_8821C(x) ((x) & (~BITS_C1_L_8821C))\n#define BIT_GET_C1_L_8821C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_C1_L_8821C) & BIT_MASK_C1_L_8821C)\n#define BIT_SET_C1_L_8821C(x, v) (BIT_CLEAR_C1_L_8821C(x) | BIT_C1_L_8821C(v))\n\n#define BIT_SHIFT_REG_FREQ_L_8821C 25\n#define BIT_MASK_REG_FREQ_L_8821C 0x7\n#define BIT_REG_FREQ_L_8821C(x)                                                \\\n\t(((x) & BIT_MASK_REG_FREQ_L_8821C) << BIT_SHIFT_REG_FREQ_L_8821C)\n#define BITS_REG_FREQ_L_8821C                                                  \\\n\t(BIT_MASK_REG_FREQ_L_8821C << BIT_SHIFT_REG_FREQ_L_8821C)\n#define BIT_CLEAR_REG_FREQ_L_8821C(x) ((x) & (~BITS_REG_FREQ_L_8821C))\n#define BIT_GET_REG_FREQ_L_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_REG_FREQ_L_8821C) & BIT_MASK_REG_FREQ_L_8821C)\n#define BIT_SET_REG_FREQ_L_8821C(x, v)                                         \\\n\t(BIT_CLEAR_REG_FREQ_L_8821C(x) | BIT_REG_FREQ_L_8821C(v))\n\n#define BIT_REG_EN_DUTY_8821C BIT(24)\n\n#define BIT_SHIFT_REG_MODE_8821C 22\n#define BIT_MASK_REG_MODE_8821C 0x3\n#define BIT_REG_MODE_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_REG_MODE_8821C) << BIT_SHIFT_REG_MODE_8821C)\n#define BITS_REG_MODE_8821C                                                    \\\n\t(BIT_MASK_REG_MODE_8821C << BIT_SHIFT_REG_MODE_8821C)\n#define BIT_CLEAR_REG_MODE_8821C(x) ((x) & (~BITS_REG_MODE_8821C))\n#define BIT_GET_REG_MODE_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_REG_MODE_8821C) & BIT_MASK_REG_MODE_8821C)\n#define BIT_SET_REG_MODE_8821C(x, v)                                           \\\n\t(BIT_CLEAR_REG_MODE_8821C(x) | BIT_REG_MODE_8821C(v))\n\n#define BIT_REG_EN_SP_8821C BIT(21)\n#define BIT_REG_AUTO_L_8821C BIT(20)\n#define BIT_SW18_SELD_BIT0_8821C BIT(19)\n#define BIT_SW18_POWOCP_8821C BIT(18)\n\n#define BIT_SHIFT_OCP_L1_8821C 15\n#define BIT_MASK_OCP_L1_8821C 0x7\n#define BIT_OCP_L1_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_OCP_L1_8821C) << BIT_SHIFT_OCP_L1_8821C)\n#define BITS_OCP_L1_8821C (BIT_MASK_OCP_L1_8821C << BIT_SHIFT_OCP_L1_8821C)\n#define BIT_CLEAR_OCP_L1_8821C(x) ((x) & (~BITS_OCP_L1_8821C))\n#define BIT_GET_OCP_L1_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_OCP_L1_8821C) & BIT_MASK_OCP_L1_8821C)\n#define BIT_SET_OCP_L1_8821C(x, v)                                             \\\n\t(BIT_CLEAR_OCP_L1_8821C(x) | BIT_OCP_L1_8821C(v))\n\n#define BIT_SHIFT_CF_L_8821C 13\n#define BIT_MASK_CF_L_8821C 0x3\n#define BIT_CF_L_8821C(x) (((x) & BIT_MASK_CF_L_8821C) << BIT_SHIFT_CF_L_8821C)\n#define BITS_CF_L_8821C (BIT_MASK_CF_L_8821C << BIT_SHIFT_CF_L_8821C)\n#define BIT_CLEAR_CF_L_8821C(x) ((x) & (~BITS_CF_L_8821C))\n#define BIT_GET_CF_L_8821C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_CF_L_8821C) & BIT_MASK_CF_L_8821C)\n#define BIT_SET_CF_L_8821C(x, v) (BIT_CLEAR_CF_L_8821C(x) | BIT_CF_L_8821C(v))\n\n#define BIT_SW18_FPWM_8821C BIT(11)\n#define BIT_SW18_SWEN_8821C BIT(9)\n#define BIT_SW18_LDEN_8821C BIT(8)\n#define BIT_MAC_ID_EN_8821C BIT(7)\n#define BIT_AFE_BGEN_8821C BIT(0)\n\n/* 2 REG_SYS_SWR_CTRL2_8821C */\n#define BIT_POW_ZCD_L_8821C BIT(31)\n#define BIT_AUTOZCD_L_8821C BIT(30)\n\n#define BIT_SHIFT_REG_DELAY_8821C 28\n#define BIT_MASK_REG_DELAY_8821C 0x3\n#define BIT_REG_DELAY_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_REG_DELAY_8821C) << BIT_SHIFT_REG_DELAY_8821C)\n#define BITS_REG_DELAY_8821C                                                   \\\n\t(BIT_MASK_REG_DELAY_8821C << BIT_SHIFT_REG_DELAY_8821C)\n#define BIT_CLEAR_REG_DELAY_8821C(x) ((x) & (~BITS_REG_DELAY_8821C))\n#define BIT_GET_REG_DELAY_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_REG_DELAY_8821C) & BIT_MASK_REG_DELAY_8821C)\n#define BIT_SET_REG_DELAY_8821C(x, v)                                          \\\n\t(BIT_CLEAR_REG_DELAY_8821C(x) | BIT_REG_DELAY_8821C(v))\n\n#define BIT_SHIFT_V15ADJ_L1_V1_8821C 24\n#define BIT_MASK_V15ADJ_L1_V1_8821C 0x7\n#define BIT_V15ADJ_L1_V1_8821C(x)                                              \\\n\t(((x) & BIT_MASK_V15ADJ_L1_V1_8821C) << BIT_SHIFT_V15ADJ_L1_V1_8821C)\n#define BITS_V15ADJ_L1_V1_8821C                                                \\\n\t(BIT_MASK_V15ADJ_L1_V1_8821C << BIT_SHIFT_V15ADJ_L1_V1_8821C)\n#define BIT_CLEAR_V15ADJ_L1_V1_8821C(x) ((x) & (~BITS_V15ADJ_L1_V1_8821C))\n#define BIT_GET_V15ADJ_L1_V1_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_V15ADJ_L1_V1_8821C) & BIT_MASK_V15ADJ_L1_V1_8821C)\n#define BIT_SET_V15ADJ_L1_V1_8821C(x, v)                                       \\\n\t(BIT_CLEAR_V15ADJ_L1_V1_8821C(x) | BIT_V15ADJ_L1_V1_8821C(v))\n\n#define BIT_SHIFT_VOL_L1_V1_8821C 20\n#define BIT_MASK_VOL_L1_V1_8821C 0xf\n#define BIT_VOL_L1_V1_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_VOL_L1_V1_8821C) << BIT_SHIFT_VOL_L1_V1_8821C)\n#define BITS_VOL_L1_V1_8821C                                                   \\\n\t(BIT_MASK_VOL_L1_V1_8821C << BIT_SHIFT_VOL_L1_V1_8821C)\n#define BIT_CLEAR_VOL_L1_V1_8821C(x) ((x) & (~BITS_VOL_L1_V1_8821C))\n#define BIT_GET_VOL_L1_V1_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_VOL_L1_V1_8821C) & BIT_MASK_VOL_L1_V1_8821C)\n#define BIT_SET_VOL_L1_V1_8821C(x, v)                                          \\\n\t(BIT_CLEAR_VOL_L1_V1_8821C(x) | BIT_VOL_L1_V1_8821C(v))\n\n#define BIT_SHIFT_IN_L1_V1_8821C 17\n#define BIT_MASK_IN_L1_V1_8821C 0x7\n#define BIT_IN_L1_V1_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_IN_L1_V1_8821C) << BIT_SHIFT_IN_L1_V1_8821C)\n#define BITS_IN_L1_V1_8821C                                                    \\\n\t(BIT_MASK_IN_L1_V1_8821C << BIT_SHIFT_IN_L1_V1_8821C)\n#define BIT_CLEAR_IN_L1_V1_8821C(x) ((x) & (~BITS_IN_L1_V1_8821C))\n#define BIT_GET_IN_L1_V1_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_IN_L1_V1_8821C) & BIT_MASK_IN_L1_V1_8821C)\n#define BIT_SET_IN_L1_V1_8821C(x, v)                                           \\\n\t(BIT_CLEAR_IN_L1_V1_8821C(x) | BIT_IN_L1_V1_8821C(v))\n\n#define BIT_SHIFT_TBOX_L1_8821C 15\n#define BIT_MASK_TBOX_L1_8821C 0x3\n#define BIT_TBOX_L1_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_TBOX_L1_8821C) << BIT_SHIFT_TBOX_L1_8821C)\n#define BITS_TBOX_L1_8821C (BIT_MASK_TBOX_L1_8821C << BIT_SHIFT_TBOX_L1_8821C)\n#define BIT_CLEAR_TBOX_L1_8821C(x) ((x) & (~BITS_TBOX_L1_8821C))\n#define BIT_GET_TBOX_L1_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TBOX_L1_8821C) & BIT_MASK_TBOX_L1_8821C)\n#define BIT_SET_TBOX_L1_8821C(x, v)                                            \\\n\t(BIT_CLEAR_TBOX_L1_8821C(x) | BIT_TBOX_L1_8821C(v))\n\n#define BIT_SW18_SEL_8821C BIT(13)\n\n/* 2 REG_NOT_VALID_8821C */\n#define BIT_SW18_SD_8821C BIT(10)\n\n#define BIT_SHIFT_R3_L_8821C 7\n#define BIT_MASK_R3_L_8821C 0x3\n#define BIT_R3_L_8821C(x) (((x) & BIT_MASK_R3_L_8821C) << BIT_SHIFT_R3_L_8821C)\n#define BITS_R3_L_8821C (BIT_MASK_R3_L_8821C << BIT_SHIFT_R3_L_8821C)\n#define BIT_CLEAR_R3_L_8821C(x) ((x) & (~BITS_R3_L_8821C))\n#define BIT_GET_R3_L_8821C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_R3_L_8821C) & BIT_MASK_R3_L_8821C)\n#define BIT_SET_R3_L_8821C(x, v) (BIT_CLEAR_R3_L_8821C(x) | BIT_R3_L_8821C(v))\n\n#define BIT_SHIFT_SW18_R2_8821C 5\n#define BIT_MASK_SW18_R2_8821C 0x3\n#define BIT_SW18_R2_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_SW18_R2_8821C) << BIT_SHIFT_SW18_R2_8821C)\n#define BITS_SW18_R2_8821C (BIT_MASK_SW18_R2_8821C << BIT_SHIFT_SW18_R2_8821C)\n#define BIT_CLEAR_SW18_R2_8821C(x) ((x) & (~BITS_SW18_R2_8821C))\n#define BIT_GET_SW18_R2_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_SW18_R2_8821C) & BIT_MASK_SW18_R2_8821C)\n#define BIT_SET_SW18_R2_8821C(x, v)                                            \\\n\t(BIT_CLEAR_SW18_R2_8821C(x) | BIT_SW18_R2_8821C(v))\n\n#define BIT_SHIFT_SW18_R1_8821C 3\n#define BIT_MASK_SW18_R1_8821C 0x3\n#define BIT_SW18_R1_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_SW18_R1_8821C) << BIT_SHIFT_SW18_R1_8821C)\n#define BITS_SW18_R1_8821C (BIT_MASK_SW18_R1_8821C << BIT_SHIFT_SW18_R1_8821C)\n#define BIT_CLEAR_SW18_R1_8821C(x) ((x) & (~BITS_SW18_R1_8821C))\n#define BIT_GET_SW18_R1_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_SW18_R1_8821C) & BIT_MASK_SW18_R1_8821C)\n#define BIT_SET_SW18_R1_8821C(x, v)                                            \\\n\t(BIT_CLEAR_SW18_R1_8821C(x) | BIT_SW18_R1_8821C(v))\n\n#define BIT_SHIFT_C3_L_C3_8821C 1\n#define BIT_MASK_C3_L_C3_8821C 0x3\n#define BIT_C3_L_C3_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_C3_L_C3_8821C) << BIT_SHIFT_C3_L_C3_8821C)\n#define BITS_C3_L_C3_8821C (BIT_MASK_C3_L_C3_8821C << BIT_SHIFT_C3_L_C3_8821C)\n#define BIT_CLEAR_C3_L_C3_8821C(x) ((x) & (~BITS_C3_L_C3_8821C))\n#define BIT_GET_C3_L_C3_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_C3_L_C3_8821C) & BIT_MASK_C3_L_C3_8821C)\n#define BIT_SET_C3_L_C3_8821C(x, v)                                            \\\n\t(BIT_CLEAR_C3_L_C3_8821C(x) | BIT_C3_L_C3_8821C(v))\n\n#define BIT_C2_L_BIT1_8821C BIT(0)\n\n/* 2 REG_SYS_SWR_CTRL3_8821C */\n#define BIT_SPS18_OCP_DIS_8821C BIT(31)\n\n#define BIT_SHIFT_SPS18_OCP_TH_8821C 16\n#define BIT_MASK_SPS18_OCP_TH_8821C 0x7fff\n#define BIT_SPS18_OCP_TH_8821C(x)                                              \\\n\t(((x) & BIT_MASK_SPS18_OCP_TH_8821C) << BIT_SHIFT_SPS18_OCP_TH_8821C)\n#define BITS_SPS18_OCP_TH_8821C                                                \\\n\t(BIT_MASK_SPS18_OCP_TH_8821C << BIT_SHIFT_SPS18_OCP_TH_8821C)\n#define BIT_CLEAR_SPS18_OCP_TH_8821C(x) ((x) & (~BITS_SPS18_OCP_TH_8821C))\n#define BIT_GET_SPS18_OCP_TH_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_SPS18_OCP_TH_8821C) & BIT_MASK_SPS18_OCP_TH_8821C)\n#define BIT_SET_SPS18_OCP_TH_8821C(x, v)                                       \\\n\t(BIT_CLEAR_SPS18_OCP_TH_8821C(x) | BIT_SPS18_OCP_TH_8821C(v))\n\n#define BIT_SHIFT_OCP_WINDOW_8821C 0\n#define BIT_MASK_OCP_WINDOW_8821C 0xffff\n#define BIT_OCP_WINDOW_8821C(x)                                                \\\n\t(((x) & BIT_MASK_OCP_WINDOW_8821C) << BIT_SHIFT_OCP_WINDOW_8821C)\n#define BITS_OCP_WINDOW_8821C                                                  \\\n\t(BIT_MASK_OCP_WINDOW_8821C << BIT_SHIFT_OCP_WINDOW_8821C)\n#define BIT_CLEAR_OCP_WINDOW_8821C(x) ((x) & (~BITS_OCP_WINDOW_8821C))\n#define BIT_GET_OCP_WINDOW_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_OCP_WINDOW_8821C) & BIT_MASK_OCP_WINDOW_8821C)\n#define BIT_SET_OCP_WINDOW_8821C(x, v)                                         \\\n\t(BIT_CLEAR_OCP_WINDOW_8821C(x) | BIT_OCP_WINDOW_8821C(v))\n\n/* 2 REG_RSV_CTRL_8821C */\n#define BIT_HREG_DBG_8821C BIT(23)\n#define BIT_WLMCUIOIF_8821C BIT(8)\n#define BIT_LOCK_ALL_EN_8821C BIT(7)\n#define BIT_R_DIS_PRST_8821C BIT(6)\n#define BIT_WLOCK_1C_B6_8821C BIT(5)\n#define BIT_WLOCK_40_8821C BIT(4)\n#define BIT_WLOCK_08_8821C BIT(3)\n#define BIT_WLOCK_04_8821C BIT(2)\n#define BIT_WLOCK_00_8821C BIT(1)\n#define BIT_WLOCK_ALL_8821C BIT(0)\n\n/* 2 REG_RF_CTRL_8821C */\n#define BIT_RF_SDMRSTB_8821C BIT(2)\n#define BIT_RF_RSTB_8821C BIT(1)\n#define BIT_RF_EN_8821C BIT(0)\n\n/* 2 REG_AFE_LDO_CTRL_8821C */\n\n#define BIT_SHIFT_LPLDH12_RSV_8821C 29\n#define BIT_MASK_LPLDH12_RSV_8821C 0x7\n#define BIT_LPLDH12_RSV_8821C(x)                                               \\\n\t(((x) & BIT_MASK_LPLDH12_RSV_8821C) << BIT_SHIFT_LPLDH12_RSV_8821C)\n#define BITS_LPLDH12_RSV_8821C                                                 \\\n\t(BIT_MASK_LPLDH12_RSV_8821C << BIT_SHIFT_LPLDH12_RSV_8821C)\n#define BIT_CLEAR_LPLDH12_RSV_8821C(x) ((x) & (~BITS_LPLDH12_RSV_8821C))\n#define BIT_GET_LPLDH12_RSV_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_LPLDH12_RSV_8821C) & BIT_MASK_LPLDH12_RSV_8821C)\n#define BIT_SET_LPLDH12_RSV_8821C(x, v)                                        \\\n\t(BIT_CLEAR_LPLDH12_RSV_8821C(x) | BIT_LPLDH12_RSV_8821C(v))\n\n#define BIT_LPLDH12_SLP_8821C BIT(28)\n\n#define BIT_SHIFT_LPLDH12_VADJ_8821C 24\n#define BIT_MASK_LPLDH12_VADJ_8821C 0xf\n#define BIT_LPLDH12_VADJ_8821C(x)                                              \\\n\t(((x) & BIT_MASK_LPLDH12_VADJ_8821C) << BIT_SHIFT_LPLDH12_VADJ_8821C)\n#define BITS_LPLDH12_VADJ_8821C                                                \\\n\t(BIT_MASK_LPLDH12_VADJ_8821C << BIT_SHIFT_LPLDH12_VADJ_8821C)\n#define BIT_CLEAR_LPLDH12_VADJ_8821C(x) ((x) & (~BITS_LPLDH12_VADJ_8821C))\n#define BIT_GET_LPLDH12_VADJ_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_LPLDH12_VADJ_8821C) & BIT_MASK_LPLDH12_VADJ_8821C)\n#define BIT_SET_LPLDH12_VADJ_8821C(x, v)                                       \\\n\t(BIT_CLEAR_LPLDH12_VADJ_8821C(x) | BIT_LPLDH12_VADJ_8821C(v))\n\n#define BIT_PCIE_CALIB_EN_8821C BIT(17)\n#define BIT_LDH12_EN_8821C BIT(16)\n#define BIT_WLBBOFF_BIG_PWC_EN_8821C BIT(14)\n#define BIT_WLBBOFF_SMALL_PWC_EN_8821C BIT(13)\n#define BIT_WLMACOFF_BIG_PWC_EN_8821C BIT(12)\n#define BIT_WLPON_PWC_EN_8821C BIT(11)\n#define BIT_POW_REGU_P1_8821C BIT(10)\n#define BIT_LDOV12W_EN_8821C BIT(8)\n#define BIT_EX_XTAL_DRV_DIGI_8821C BIT(7)\n#define BIT_EX_XTAL_DRV_USB_8821C BIT(6)\n#define BIT_EX_XTAL_DRV_AFE_8821C BIT(5)\n#define BIT_EX_XTAL_DRV_RF2_8821C BIT(4)\n#define BIT_EX_XTAL_DRV_RF1_8821C BIT(3)\n#define BIT_POW_REGU_P0_8821C BIT(2)\n\n/* 2 REG_NOT_VALID_8821C */\n#define BIT_POW_PLL_LDO_8821C BIT(0)\n\n/* 2 REG_AFE_CTRL1_8821C */\n#define BIT_AGPIO_GPE_8821C BIT(31)\n\n#define BIT_SHIFT_XTAL_CAP_XI_8821C 25\n#define BIT_MASK_XTAL_CAP_XI_8821C 0x3f\n#define BIT_XTAL_CAP_XI_8821C(x)                                               \\\n\t(((x) & BIT_MASK_XTAL_CAP_XI_8821C) << BIT_SHIFT_XTAL_CAP_XI_8821C)\n#define BITS_XTAL_CAP_XI_8821C                                                 \\\n\t(BIT_MASK_XTAL_CAP_XI_8821C << BIT_SHIFT_XTAL_CAP_XI_8821C)\n#define BIT_CLEAR_XTAL_CAP_XI_8821C(x) ((x) & (~BITS_XTAL_CAP_XI_8821C))\n#define BIT_GET_XTAL_CAP_XI_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_XTAL_CAP_XI_8821C) & BIT_MASK_XTAL_CAP_XI_8821C)\n#define BIT_SET_XTAL_CAP_XI_8821C(x, v)                                        \\\n\t(BIT_CLEAR_XTAL_CAP_XI_8821C(x) | BIT_XTAL_CAP_XI_8821C(v))\n\n#define BIT_SHIFT_XTAL_DRV_DIGI_8821C 23\n#define BIT_MASK_XTAL_DRV_DIGI_8821C 0x3\n#define BIT_XTAL_DRV_DIGI_8821C(x)                                             \\\n\t(((x) & BIT_MASK_XTAL_DRV_DIGI_8821C) << BIT_SHIFT_XTAL_DRV_DIGI_8821C)\n#define BITS_XTAL_DRV_DIGI_8821C                                               \\\n\t(BIT_MASK_XTAL_DRV_DIGI_8821C << BIT_SHIFT_XTAL_DRV_DIGI_8821C)\n#define BIT_CLEAR_XTAL_DRV_DIGI_8821C(x) ((x) & (~BITS_XTAL_DRV_DIGI_8821C))\n#define BIT_GET_XTAL_DRV_DIGI_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8821C) & BIT_MASK_XTAL_DRV_DIGI_8821C)\n#define BIT_SET_XTAL_DRV_DIGI_8821C(x, v)                                      \\\n\t(BIT_CLEAR_XTAL_DRV_DIGI_8821C(x) | BIT_XTAL_DRV_DIGI_8821C(v))\n\n#define BIT_XTAL_DRV_USB_BIT1_8821C BIT(22)\n\n#define BIT_SHIFT_MAC_CLK_SEL_8821C 20\n#define BIT_MASK_MAC_CLK_SEL_8821C 0x3\n#define BIT_MAC_CLK_SEL_8821C(x)                                               \\\n\t(((x) & BIT_MASK_MAC_CLK_SEL_8821C) << BIT_SHIFT_MAC_CLK_SEL_8821C)\n#define BITS_MAC_CLK_SEL_8821C                                                 \\\n\t(BIT_MASK_MAC_CLK_SEL_8821C << BIT_SHIFT_MAC_CLK_SEL_8821C)\n#define BIT_CLEAR_MAC_CLK_SEL_8821C(x) ((x) & (~BITS_MAC_CLK_SEL_8821C))\n#define BIT_GET_MAC_CLK_SEL_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_MAC_CLK_SEL_8821C) & BIT_MASK_MAC_CLK_SEL_8821C)\n#define BIT_SET_MAC_CLK_SEL_8821C(x, v)                                        \\\n\t(BIT_CLEAR_MAC_CLK_SEL_8821C(x) | BIT_MAC_CLK_SEL_8821C(v))\n\n#define BIT_XTAL_DRV_USB_BIT0_8821C BIT(19)\n\n#define BIT_SHIFT_XTAL_DRV_AFE_8821C 17\n#define BIT_MASK_XTAL_DRV_AFE_8821C 0x3\n#define BIT_XTAL_DRV_AFE_8821C(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_DRV_AFE_8821C) << BIT_SHIFT_XTAL_DRV_AFE_8821C)\n#define BITS_XTAL_DRV_AFE_8821C                                                \\\n\t(BIT_MASK_XTAL_DRV_AFE_8821C << BIT_SHIFT_XTAL_DRV_AFE_8821C)\n#define BIT_CLEAR_XTAL_DRV_AFE_8821C(x) ((x) & (~BITS_XTAL_DRV_AFE_8821C))\n#define BIT_GET_XTAL_DRV_AFE_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_AFE_8821C) & BIT_MASK_XTAL_DRV_AFE_8821C)\n#define BIT_SET_XTAL_DRV_AFE_8821C(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_DRV_AFE_8821C(x) | BIT_XTAL_DRV_AFE_8821C(v))\n\n#define BIT_SHIFT_XTAL_DRV_RF2_8821C 15\n#define BIT_MASK_XTAL_DRV_RF2_8821C 0x3\n#define BIT_XTAL_DRV_RF2_8821C(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_DRV_RF2_8821C) << BIT_SHIFT_XTAL_DRV_RF2_8821C)\n#define BITS_XTAL_DRV_RF2_8821C                                                \\\n\t(BIT_MASK_XTAL_DRV_RF2_8821C << BIT_SHIFT_XTAL_DRV_RF2_8821C)\n#define BIT_CLEAR_XTAL_DRV_RF2_8821C(x) ((x) & (~BITS_XTAL_DRV_RF2_8821C))\n#define BIT_GET_XTAL_DRV_RF2_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_RF2_8821C) & BIT_MASK_XTAL_DRV_RF2_8821C)\n#define BIT_SET_XTAL_DRV_RF2_8821C(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_DRV_RF2_8821C(x) | BIT_XTAL_DRV_RF2_8821C(v))\n\n#define BIT_SHIFT_XTAL_DRV_RF1_8821C 13\n#define BIT_MASK_XTAL_DRV_RF1_8821C 0x3\n#define BIT_XTAL_DRV_RF1_8821C(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_DRV_RF1_8821C) << BIT_SHIFT_XTAL_DRV_RF1_8821C)\n#define BITS_XTAL_DRV_RF1_8821C                                                \\\n\t(BIT_MASK_XTAL_DRV_RF1_8821C << BIT_SHIFT_XTAL_DRV_RF1_8821C)\n#define BIT_CLEAR_XTAL_DRV_RF1_8821C(x) ((x) & (~BITS_XTAL_DRV_RF1_8821C))\n#define BIT_GET_XTAL_DRV_RF1_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_RF1_8821C) & BIT_MASK_XTAL_DRV_RF1_8821C)\n#define BIT_SET_XTAL_DRV_RF1_8821C(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_DRV_RF1_8821C(x) | BIT_XTAL_DRV_RF1_8821C(v))\n\n#define BIT_XTAL_DELAY_DIGI_8821C BIT(12)\n#define BIT_XTAL_DELAY_USB_8821C BIT(11)\n#define BIT_XTAL_DELAY_AFE_8821C BIT(10)\n\n#define BIT_SHIFT_XTAL_LDO_VREF_8821C 7\n#define BIT_MASK_XTAL_LDO_VREF_8821C 0x7\n#define BIT_XTAL_LDO_VREF_8821C(x)                                             \\\n\t(((x) & BIT_MASK_XTAL_LDO_VREF_8821C) << BIT_SHIFT_XTAL_LDO_VREF_8821C)\n#define BITS_XTAL_LDO_VREF_8821C                                               \\\n\t(BIT_MASK_XTAL_LDO_VREF_8821C << BIT_SHIFT_XTAL_LDO_VREF_8821C)\n#define BIT_CLEAR_XTAL_LDO_VREF_8821C(x) ((x) & (~BITS_XTAL_LDO_VREF_8821C))\n#define BIT_GET_XTAL_LDO_VREF_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_XTAL_LDO_VREF_8821C) & BIT_MASK_XTAL_LDO_VREF_8821C)\n#define BIT_SET_XTAL_LDO_VREF_8821C(x, v)                                      \\\n\t(BIT_CLEAR_XTAL_LDO_VREF_8821C(x) | BIT_XTAL_LDO_VREF_8821C(v))\n\n#define BIT_XTAL_XQSEL_RF_8821C BIT(6)\n#define BIT_XTAL_XQSEL_8821C BIT(5)\n\n#define BIT_SHIFT_XTAL_GMN_V2_8821C 3\n#define BIT_MASK_XTAL_GMN_V2_8821C 0x3\n#define BIT_XTAL_GMN_V2_8821C(x)                                               \\\n\t(((x) & BIT_MASK_XTAL_GMN_V2_8821C) << BIT_SHIFT_XTAL_GMN_V2_8821C)\n#define BITS_XTAL_GMN_V2_8821C                                                 \\\n\t(BIT_MASK_XTAL_GMN_V2_8821C << BIT_SHIFT_XTAL_GMN_V2_8821C)\n#define BIT_CLEAR_XTAL_GMN_V2_8821C(x) ((x) & (~BITS_XTAL_GMN_V2_8821C))\n#define BIT_GET_XTAL_GMN_V2_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_XTAL_GMN_V2_8821C) & BIT_MASK_XTAL_GMN_V2_8821C)\n#define BIT_SET_XTAL_GMN_V2_8821C(x, v)                                        \\\n\t(BIT_CLEAR_XTAL_GMN_V2_8821C(x) | BIT_XTAL_GMN_V2_8821C(v))\n\n#define BIT_SHIFT_XTAL_GMP_V2_8821C 1\n#define BIT_MASK_XTAL_GMP_V2_8821C 0x3\n#define BIT_XTAL_GMP_V2_8821C(x)                                               \\\n\t(((x) & BIT_MASK_XTAL_GMP_V2_8821C) << BIT_SHIFT_XTAL_GMP_V2_8821C)\n#define BITS_XTAL_GMP_V2_8821C                                                 \\\n\t(BIT_MASK_XTAL_GMP_V2_8821C << BIT_SHIFT_XTAL_GMP_V2_8821C)\n#define BIT_CLEAR_XTAL_GMP_V2_8821C(x) ((x) & (~BITS_XTAL_GMP_V2_8821C))\n#define BIT_GET_XTAL_GMP_V2_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_XTAL_GMP_V2_8821C) & BIT_MASK_XTAL_GMP_V2_8821C)\n#define BIT_SET_XTAL_GMP_V2_8821C(x, v)                                        \\\n\t(BIT_CLEAR_XTAL_GMP_V2_8821C(x) | BIT_XTAL_GMP_V2_8821C(v))\n\n#define BIT_XTAL_EN_8821C BIT(0)\n\n/* 2 REG_AFE_CTRL2_8821C */\n\n#define BIT_SHIFT_REG_C3_V4_8821C 30\n#define BIT_MASK_REG_C3_V4_8821C 0x3\n#define BIT_REG_C3_V4_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_REG_C3_V4_8821C) << BIT_SHIFT_REG_C3_V4_8821C)\n#define BITS_REG_C3_V4_8821C                                                   \\\n\t(BIT_MASK_REG_C3_V4_8821C << BIT_SHIFT_REG_C3_V4_8821C)\n#define BIT_CLEAR_REG_C3_V4_8821C(x) ((x) & (~BITS_REG_C3_V4_8821C))\n#define BIT_GET_REG_C3_V4_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_REG_C3_V4_8821C) & BIT_MASK_REG_C3_V4_8821C)\n#define BIT_SET_REG_C3_V4_8821C(x, v)                                          \\\n\t(BIT_CLEAR_REG_C3_V4_8821C(x) | BIT_REG_C3_V4_8821C(v))\n\n#define BIT_REG_CP_BIT1_8821C BIT(29)\n\n#define BIT_SHIFT_REG_RS_V4_8821C 26\n#define BIT_MASK_REG_RS_V4_8821C 0x7\n#define BIT_REG_RS_V4_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_REG_RS_V4_8821C) << BIT_SHIFT_REG_RS_V4_8821C)\n#define BITS_REG_RS_V4_8821C                                                   \\\n\t(BIT_MASK_REG_RS_V4_8821C << BIT_SHIFT_REG_RS_V4_8821C)\n#define BIT_CLEAR_REG_RS_V4_8821C(x) ((x) & (~BITS_REG_RS_V4_8821C))\n#define BIT_GET_REG_RS_V4_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_REG_RS_V4_8821C) & BIT_MASK_REG_RS_V4_8821C)\n#define BIT_SET_REG_RS_V4_8821C(x, v)                                          \\\n\t(BIT_CLEAR_REG_RS_V4_8821C(x) | BIT_REG_RS_V4_8821C(v))\n\n#define BIT_SHIFT_REG__CS_8821C 24\n#define BIT_MASK_REG__CS_8821C 0x3\n#define BIT_REG__CS_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_REG__CS_8821C) << BIT_SHIFT_REG__CS_8821C)\n#define BITS_REG__CS_8821C (BIT_MASK_REG__CS_8821C << BIT_SHIFT_REG__CS_8821C)\n#define BIT_CLEAR_REG__CS_8821C(x) ((x) & (~BITS_REG__CS_8821C))\n#define BIT_GET_REG__CS_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_REG__CS_8821C) & BIT_MASK_REG__CS_8821C)\n#define BIT_SET_REG__CS_8821C(x, v)                                            \\\n\t(BIT_CLEAR_REG__CS_8821C(x) | BIT_REG__CS_8821C(v))\n\n#define BIT_SHIFT_REG_CP_OFFSET_8821C 21\n#define BIT_MASK_REG_CP_OFFSET_8821C 0x7\n#define BIT_REG_CP_OFFSET_8821C(x)                                             \\\n\t(((x) & BIT_MASK_REG_CP_OFFSET_8821C) << BIT_SHIFT_REG_CP_OFFSET_8821C)\n#define BITS_REG_CP_OFFSET_8821C                                               \\\n\t(BIT_MASK_REG_CP_OFFSET_8821C << BIT_SHIFT_REG_CP_OFFSET_8821C)\n#define BIT_CLEAR_REG_CP_OFFSET_8821C(x) ((x) & (~BITS_REG_CP_OFFSET_8821C))\n#define BIT_GET_REG_CP_OFFSET_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_REG_CP_OFFSET_8821C) & BIT_MASK_REG_CP_OFFSET_8821C)\n#define BIT_SET_REG_CP_OFFSET_8821C(x, v)                                      \\\n\t(BIT_CLEAR_REG_CP_OFFSET_8821C(x) | BIT_REG_CP_OFFSET_8821C(v))\n\n#define BIT_SHIFT_CP_BIAS_8821C 18\n#define BIT_MASK_CP_BIAS_8821C 0x7\n#define BIT_CP_BIAS_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_CP_BIAS_8821C) << BIT_SHIFT_CP_BIAS_8821C)\n#define BITS_CP_BIAS_8821C (BIT_MASK_CP_BIAS_8821C << BIT_SHIFT_CP_BIAS_8821C)\n#define BIT_CLEAR_CP_BIAS_8821C(x) ((x) & (~BITS_CP_BIAS_8821C))\n#define BIT_GET_CP_BIAS_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_CP_BIAS_8821C) & BIT_MASK_CP_BIAS_8821C)\n#define BIT_SET_CP_BIAS_8821C(x, v)                                            \\\n\t(BIT_CLEAR_CP_BIAS_8821C(x) | BIT_CP_BIAS_8821C(v))\n\n#define BIT_REG_IDOUBLE_V2_8821C BIT(17)\n#define BIT_EN_SYN_8821C BIT(16)\n\n#define BIT_SHIFT_MCCO_8821C 14\n#define BIT_MASK_MCCO_8821C 0x3\n#define BIT_MCCO_8821C(x) (((x) & BIT_MASK_MCCO_8821C) << BIT_SHIFT_MCCO_8821C)\n#define BITS_MCCO_8821C (BIT_MASK_MCCO_8821C << BIT_SHIFT_MCCO_8821C)\n#define BIT_CLEAR_MCCO_8821C(x) ((x) & (~BITS_MCCO_8821C))\n#define BIT_GET_MCCO_8821C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_MCCO_8821C) & BIT_MASK_MCCO_8821C)\n#define BIT_SET_MCCO_8821C(x, v) (BIT_CLEAR_MCCO_8821C(x) | BIT_MCCO_8821C(v))\n\n#define BIT_SHIFT_REG_LDO_SEL_8821C 12\n#define BIT_MASK_REG_LDO_SEL_8821C 0x3\n#define BIT_REG_LDO_SEL_8821C(x)                                               \\\n\t(((x) & BIT_MASK_REG_LDO_SEL_8821C) << BIT_SHIFT_REG_LDO_SEL_8821C)\n#define BITS_REG_LDO_SEL_8821C                                                 \\\n\t(BIT_MASK_REG_LDO_SEL_8821C << BIT_SHIFT_REG_LDO_SEL_8821C)\n#define BIT_CLEAR_REG_LDO_SEL_8821C(x) ((x) & (~BITS_REG_LDO_SEL_8821C))\n#define BIT_GET_REG_LDO_SEL_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_REG_LDO_SEL_8821C) & BIT_MASK_REG_LDO_SEL_8821C)\n#define BIT_SET_REG_LDO_SEL_8821C(x, v)                                        \\\n\t(BIT_CLEAR_REG_LDO_SEL_8821C(x) | BIT_REG_LDO_SEL_8821C(v))\n\n#define BIT_REG_KVCO_V2_8821C BIT(10)\n#define BIT_AGPIO_GPO_8821C BIT(9)\n\n#define BIT_SHIFT_AGPIO_DRV_8821C 7\n#define BIT_MASK_AGPIO_DRV_8821C 0x3\n#define BIT_AGPIO_DRV_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_AGPIO_DRV_8821C) << BIT_SHIFT_AGPIO_DRV_8821C)\n#define BITS_AGPIO_DRV_8821C                                                   \\\n\t(BIT_MASK_AGPIO_DRV_8821C << BIT_SHIFT_AGPIO_DRV_8821C)\n#define BIT_CLEAR_AGPIO_DRV_8821C(x) ((x) & (~BITS_AGPIO_DRV_8821C))\n#define BIT_GET_AGPIO_DRV_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_AGPIO_DRV_8821C) & BIT_MASK_AGPIO_DRV_8821C)\n#define BIT_SET_AGPIO_DRV_8821C(x, v)                                          \\\n\t(BIT_CLEAR_AGPIO_DRV_8821C(x) | BIT_AGPIO_DRV_8821C(v))\n\n#define BIT_SHIFT_XTAL_CAP_XO_8821C 1\n#define BIT_MASK_XTAL_CAP_XO_8821C 0x3f\n#define BIT_XTAL_CAP_XO_8821C(x)                                               \\\n\t(((x) & BIT_MASK_XTAL_CAP_XO_8821C) << BIT_SHIFT_XTAL_CAP_XO_8821C)\n#define BITS_XTAL_CAP_XO_8821C                                                 \\\n\t(BIT_MASK_XTAL_CAP_XO_8821C << BIT_SHIFT_XTAL_CAP_XO_8821C)\n#define BIT_CLEAR_XTAL_CAP_XO_8821C(x) ((x) & (~BITS_XTAL_CAP_XO_8821C))\n#define BIT_GET_XTAL_CAP_XO_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_XTAL_CAP_XO_8821C) & BIT_MASK_XTAL_CAP_XO_8821C)\n#define BIT_SET_XTAL_CAP_XO_8821C(x, v)                                        \\\n\t(BIT_CLEAR_XTAL_CAP_XO_8821C(x) | BIT_XTAL_CAP_XO_8821C(v))\n\n#define BIT_POW_PLL_8821C BIT(0)\n\n/* 2 REG_AFE_CTRL3_8821C */\n\n#define BIT_SHIFT_PS_8821C 7\n#define BIT_MASK_PS_8821C 0x7\n#define BIT_PS_8821C(x) (((x) & BIT_MASK_PS_8821C) << BIT_SHIFT_PS_8821C)\n#define BITS_PS_8821C (BIT_MASK_PS_8821C << BIT_SHIFT_PS_8821C)\n#define BIT_CLEAR_PS_8821C(x) ((x) & (~BITS_PS_8821C))\n#define BIT_GET_PS_8821C(x) (((x) >> BIT_SHIFT_PS_8821C) & BIT_MASK_PS_8821C)\n#define BIT_SET_PS_8821C(x, v) (BIT_CLEAR_PS_8821C(x) | BIT_PS_8821C(v))\n\n#define BIT_PSEN_8821C BIT(6)\n#define BIT_DOGENB_8821C BIT(5)\n#define BIT_REG_MBIAS_8821C BIT(4)\n\n#define BIT_SHIFT_REG_R3_V4_8821C 1\n#define BIT_MASK_REG_R3_V4_8821C 0x7\n#define BIT_REG_R3_V4_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_REG_R3_V4_8821C) << BIT_SHIFT_REG_R3_V4_8821C)\n#define BITS_REG_R3_V4_8821C                                                   \\\n\t(BIT_MASK_REG_R3_V4_8821C << BIT_SHIFT_REG_R3_V4_8821C)\n#define BIT_CLEAR_REG_R3_V4_8821C(x) ((x) & (~BITS_REG_R3_V4_8821C))\n#define BIT_GET_REG_R3_V4_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_REG_R3_V4_8821C) & BIT_MASK_REG_R3_V4_8821C)\n#define BIT_SET_REG_R3_V4_8821C(x, v)                                          \\\n\t(BIT_CLEAR_REG_R3_V4_8821C(x) | BIT_REG_R3_V4_8821C(v))\n\n#define BIT_REG_CP_BIT0_8821C BIT(0)\n\n/* 2 REG_EFUSE_CTRL_8821C */\n#define BIT_EF_FLAG_8821C BIT(31)\n\n#define BIT_SHIFT_EF_PGPD_8821C 28\n#define BIT_MASK_EF_PGPD_8821C 0x7\n#define BIT_EF_PGPD_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_EF_PGPD_8821C) << BIT_SHIFT_EF_PGPD_8821C)\n#define BITS_EF_PGPD_8821C (BIT_MASK_EF_PGPD_8821C << BIT_SHIFT_EF_PGPD_8821C)\n#define BIT_CLEAR_EF_PGPD_8821C(x) ((x) & (~BITS_EF_PGPD_8821C))\n#define BIT_GET_EF_PGPD_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_PGPD_8821C) & BIT_MASK_EF_PGPD_8821C)\n#define BIT_SET_EF_PGPD_8821C(x, v)                                            \\\n\t(BIT_CLEAR_EF_PGPD_8821C(x) | BIT_EF_PGPD_8821C(v))\n\n#define BIT_SHIFT_EF_RDT_8821C 24\n#define BIT_MASK_EF_RDT_8821C 0xf\n#define BIT_EF_RDT_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_EF_RDT_8821C) << BIT_SHIFT_EF_RDT_8821C)\n#define BITS_EF_RDT_8821C (BIT_MASK_EF_RDT_8821C << BIT_SHIFT_EF_RDT_8821C)\n#define BIT_CLEAR_EF_RDT_8821C(x) ((x) & (~BITS_EF_RDT_8821C))\n#define BIT_GET_EF_RDT_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_EF_RDT_8821C) & BIT_MASK_EF_RDT_8821C)\n#define BIT_SET_EF_RDT_8821C(x, v)                                             \\\n\t(BIT_CLEAR_EF_RDT_8821C(x) | BIT_EF_RDT_8821C(v))\n\n#define BIT_SHIFT_EF_PGTS_8821C 20\n#define BIT_MASK_EF_PGTS_8821C 0xf\n#define BIT_EF_PGTS_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_EF_PGTS_8821C) << BIT_SHIFT_EF_PGTS_8821C)\n#define BITS_EF_PGTS_8821C (BIT_MASK_EF_PGTS_8821C << BIT_SHIFT_EF_PGTS_8821C)\n#define BIT_CLEAR_EF_PGTS_8821C(x) ((x) & (~BITS_EF_PGTS_8821C))\n#define BIT_GET_EF_PGTS_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_PGTS_8821C) & BIT_MASK_EF_PGTS_8821C)\n#define BIT_SET_EF_PGTS_8821C(x, v)                                            \\\n\t(BIT_CLEAR_EF_PGTS_8821C(x) | BIT_EF_PGTS_8821C(v))\n\n#define BIT_EF_PDWN_8821C BIT(19)\n#define BIT_EF_ALDEN_8821C BIT(18)\n\n#define BIT_SHIFT_EF_ADDR_8821C 8\n#define BIT_MASK_EF_ADDR_8821C 0x3ff\n#define BIT_EF_ADDR_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_EF_ADDR_8821C) << BIT_SHIFT_EF_ADDR_8821C)\n#define BITS_EF_ADDR_8821C (BIT_MASK_EF_ADDR_8821C << BIT_SHIFT_EF_ADDR_8821C)\n#define BIT_CLEAR_EF_ADDR_8821C(x) ((x) & (~BITS_EF_ADDR_8821C))\n#define BIT_GET_EF_ADDR_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_ADDR_8821C) & BIT_MASK_EF_ADDR_8821C)\n#define BIT_SET_EF_ADDR_8821C(x, v)                                            \\\n\t(BIT_CLEAR_EF_ADDR_8821C(x) | BIT_EF_ADDR_8821C(v))\n\n#define BIT_SHIFT_EF_DATA_8821C 0\n#define BIT_MASK_EF_DATA_8821C 0xff\n#define BIT_EF_DATA_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_EF_DATA_8821C) << BIT_SHIFT_EF_DATA_8821C)\n#define BITS_EF_DATA_8821C (BIT_MASK_EF_DATA_8821C << BIT_SHIFT_EF_DATA_8821C)\n#define BIT_CLEAR_EF_DATA_8821C(x) ((x) & (~BITS_EF_DATA_8821C))\n#define BIT_GET_EF_DATA_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_DATA_8821C) & BIT_MASK_EF_DATA_8821C)\n#define BIT_SET_EF_DATA_8821C(x, v)                                            \\\n\t(BIT_CLEAR_EF_DATA_8821C(x) | BIT_EF_DATA_8821C(v))\n\n/* 2 REG_LDO_EFUSE_CTRL_8821C */\n#define BIT_LDOE25_EN_8821C BIT(31)\n\n#define BIT_SHIFT_LDOE25_V12ADJ_L_8821C 27\n#define BIT_MASK_LDOE25_V12ADJ_L_8821C 0xf\n#define BIT_LDOE25_V12ADJ_L_8821C(x)                                           \\\n\t(((x) & BIT_MASK_LDOE25_V12ADJ_L_8821C)                                \\\n\t << BIT_SHIFT_LDOE25_V12ADJ_L_8821C)\n#define BITS_LDOE25_V12ADJ_L_8821C                                             \\\n\t(BIT_MASK_LDOE25_V12ADJ_L_8821C << BIT_SHIFT_LDOE25_V12ADJ_L_8821C)\n#define BIT_CLEAR_LDOE25_V12ADJ_L_8821C(x) ((x) & (~BITS_LDOE25_V12ADJ_L_8821C))\n#define BIT_GET_LDOE25_V12ADJ_L_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8821C) &                            \\\n\t BIT_MASK_LDOE25_V12ADJ_L_8821C)\n#define BIT_SET_LDOE25_V12ADJ_L_8821C(x, v)                                    \\\n\t(BIT_CLEAR_LDOE25_V12ADJ_L_8821C(x) | BIT_LDOE25_V12ADJ_L_8821C(v))\n\n#define BIT_EF_CRES_SEL_8821C BIT(26)\n\n#define BIT_SHIFT_EF_SCAN_START_V1_8821C 16\n#define BIT_MASK_EF_SCAN_START_V1_8821C 0x3ff\n#define BIT_EF_SCAN_START_V1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_EF_SCAN_START_V1_8821C)                               \\\n\t << BIT_SHIFT_EF_SCAN_START_V1_8821C)\n#define BITS_EF_SCAN_START_V1_8821C                                            \\\n\t(BIT_MASK_EF_SCAN_START_V1_8821C << BIT_SHIFT_EF_SCAN_START_V1_8821C)\n#define BIT_CLEAR_EF_SCAN_START_V1_8821C(x)                                    \\\n\t((x) & (~BITS_EF_SCAN_START_V1_8821C))\n#define BIT_GET_EF_SCAN_START_V1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_EF_SCAN_START_V1_8821C) &                           \\\n\t BIT_MASK_EF_SCAN_START_V1_8821C)\n#define BIT_SET_EF_SCAN_START_V1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_EF_SCAN_START_V1_8821C(x) | BIT_EF_SCAN_START_V1_8821C(v))\n\n#define BIT_SHIFT_EF_SCAN_END_8821C 12\n#define BIT_MASK_EF_SCAN_END_8821C 0xf\n#define BIT_EF_SCAN_END_8821C(x)                                               \\\n\t(((x) & BIT_MASK_EF_SCAN_END_8821C) << BIT_SHIFT_EF_SCAN_END_8821C)\n#define BITS_EF_SCAN_END_8821C                                                 \\\n\t(BIT_MASK_EF_SCAN_END_8821C << BIT_SHIFT_EF_SCAN_END_8821C)\n#define BIT_CLEAR_EF_SCAN_END_8821C(x) ((x) & (~BITS_EF_SCAN_END_8821C))\n#define BIT_GET_EF_SCAN_END_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_EF_SCAN_END_8821C) & BIT_MASK_EF_SCAN_END_8821C)\n#define BIT_SET_EF_SCAN_END_8821C(x, v)                                        \\\n\t(BIT_CLEAR_EF_SCAN_END_8821C(x) | BIT_EF_SCAN_END_8821C(v))\n\n#define BIT_EF_PD_DIS_8821C BIT(11)\n\n#define BIT_SHIFT_EF_CELL_SEL_8821C 8\n#define BIT_MASK_EF_CELL_SEL_8821C 0x3\n#define BIT_EF_CELL_SEL_8821C(x)                                               \\\n\t(((x) & BIT_MASK_EF_CELL_SEL_8821C) << BIT_SHIFT_EF_CELL_SEL_8821C)\n#define BITS_EF_CELL_SEL_8821C                                                 \\\n\t(BIT_MASK_EF_CELL_SEL_8821C << BIT_SHIFT_EF_CELL_SEL_8821C)\n#define BIT_CLEAR_EF_CELL_SEL_8821C(x) ((x) & (~BITS_EF_CELL_SEL_8821C))\n#define BIT_GET_EF_CELL_SEL_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_EF_CELL_SEL_8821C) & BIT_MASK_EF_CELL_SEL_8821C)\n#define BIT_SET_EF_CELL_SEL_8821C(x, v)                                        \\\n\t(BIT_CLEAR_EF_CELL_SEL_8821C(x) | BIT_EF_CELL_SEL_8821C(v))\n\n#define BIT_EF_TRPT_8821C BIT(7)\n\n#define BIT_SHIFT_EF_TTHD_8821C 0\n#define BIT_MASK_EF_TTHD_8821C 0x7f\n#define BIT_EF_TTHD_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_EF_TTHD_8821C) << BIT_SHIFT_EF_TTHD_8821C)\n#define BITS_EF_TTHD_8821C (BIT_MASK_EF_TTHD_8821C << BIT_SHIFT_EF_TTHD_8821C)\n#define BIT_CLEAR_EF_TTHD_8821C(x) ((x) & (~BITS_EF_TTHD_8821C))\n#define BIT_GET_EF_TTHD_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_TTHD_8821C) & BIT_MASK_EF_TTHD_8821C)\n#define BIT_SET_EF_TTHD_8821C(x, v)                                            \\\n\t(BIT_CLEAR_EF_TTHD_8821C(x) | BIT_EF_TTHD_8821C(v))\n\n/* 2 REG_PWR_OPTION_CTRL_8821C */\n\n#define BIT_SHIFT_DBG_SEL_V1_8821C 16\n#define BIT_MASK_DBG_SEL_V1_8821C 0xff\n#define BIT_DBG_SEL_V1_8821C(x)                                                \\\n\t(((x) & BIT_MASK_DBG_SEL_V1_8821C) << BIT_SHIFT_DBG_SEL_V1_8821C)\n#define BITS_DBG_SEL_V1_8821C                                                  \\\n\t(BIT_MASK_DBG_SEL_V1_8821C << BIT_SHIFT_DBG_SEL_V1_8821C)\n#define BIT_CLEAR_DBG_SEL_V1_8821C(x) ((x) & (~BITS_DBG_SEL_V1_8821C))\n#define BIT_GET_DBG_SEL_V1_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DBG_SEL_V1_8821C) & BIT_MASK_DBG_SEL_V1_8821C)\n#define BIT_SET_DBG_SEL_V1_8821C(x, v)                                         \\\n\t(BIT_CLEAR_DBG_SEL_V1_8821C(x) | BIT_DBG_SEL_V1_8821C(v))\n\n#define BIT_SHIFT_DBG_SEL_BYTE_8821C 14\n#define BIT_MASK_DBG_SEL_BYTE_8821C 0x3\n#define BIT_DBG_SEL_BYTE_8821C(x)                                              \\\n\t(((x) & BIT_MASK_DBG_SEL_BYTE_8821C) << BIT_SHIFT_DBG_SEL_BYTE_8821C)\n#define BITS_DBG_SEL_BYTE_8821C                                                \\\n\t(BIT_MASK_DBG_SEL_BYTE_8821C << BIT_SHIFT_DBG_SEL_BYTE_8821C)\n#define BIT_CLEAR_DBG_SEL_BYTE_8821C(x) ((x) & (~BITS_DBG_SEL_BYTE_8821C))\n#define BIT_GET_DBG_SEL_BYTE_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DBG_SEL_BYTE_8821C) & BIT_MASK_DBG_SEL_BYTE_8821C)\n#define BIT_SET_DBG_SEL_BYTE_8821C(x, v)                                       \\\n\t(BIT_CLEAR_DBG_SEL_BYTE_8821C(x) | BIT_DBG_SEL_BYTE_8821C(v))\n\n#define BIT_SHIFT_STD_L1_V1_8821C 12\n#define BIT_MASK_STD_L1_V1_8821C 0x3\n#define BIT_STD_L1_V1_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_STD_L1_V1_8821C) << BIT_SHIFT_STD_L1_V1_8821C)\n#define BITS_STD_L1_V1_8821C                                                   \\\n\t(BIT_MASK_STD_L1_V1_8821C << BIT_SHIFT_STD_L1_V1_8821C)\n#define BIT_CLEAR_STD_L1_V1_8821C(x) ((x) & (~BITS_STD_L1_V1_8821C))\n#define BIT_GET_STD_L1_V1_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_STD_L1_V1_8821C) & BIT_MASK_STD_L1_V1_8821C)\n#define BIT_SET_STD_L1_V1_8821C(x, v)                                          \\\n\t(BIT_CLEAR_STD_L1_V1_8821C(x) | BIT_STD_L1_V1_8821C(v))\n\n#define BIT_SYSON_DBG_PAD_E2_8821C BIT(11)\n#define BIT_SYSON_LED_PAD_E2_8821C BIT(10)\n#define BIT_SYSON_GPEE_PAD_E2_8821C BIT(9)\n#define BIT_SYSON_PCI_PAD_E2_8821C BIT(8)\n#define BIT_AUTO_SW_LDO_VOL_EN_8821C BIT(7)\n\n#define BIT_SHIFT_SYSON_SPS0WWV_WT_8821C 4\n#define BIT_MASK_SYSON_SPS0WWV_WT_8821C 0x3\n#define BIT_SYSON_SPS0WWV_WT_8821C(x)                                          \\\n\t(((x) & BIT_MASK_SYSON_SPS0WWV_WT_8821C)                               \\\n\t << BIT_SHIFT_SYSON_SPS0WWV_WT_8821C)\n#define BITS_SYSON_SPS0WWV_WT_8821C                                            \\\n\t(BIT_MASK_SYSON_SPS0WWV_WT_8821C << BIT_SHIFT_SYSON_SPS0WWV_WT_8821C)\n#define BIT_CLEAR_SYSON_SPS0WWV_WT_8821C(x)                                    \\\n\t((x) & (~BITS_SYSON_SPS0WWV_WT_8821C))\n#define BIT_GET_SYSON_SPS0WWV_WT_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8821C) &                           \\\n\t BIT_MASK_SYSON_SPS0WWV_WT_8821C)\n#define BIT_SET_SYSON_SPS0WWV_WT_8821C(x, v)                                   \\\n\t(BIT_CLEAR_SYSON_SPS0WWV_WT_8821C(x) | BIT_SYSON_SPS0WWV_WT_8821C(v))\n\n#define BIT_SHIFT_SYSON_SPS0LDO_WT_8821C 2\n#define BIT_MASK_SYSON_SPS0LDO_WT_8821C 0x3\n#define BIT_SYSON_SPS0LDO_WT_8821C(x)                                          \\\n\t(((x) & BIT_MASK_SYSON_SPS0LDO_WT_8821C)                               \\\n\t << BIT_SHIFT_SYSON_SPS0LDO_WT_8821C)\n#define BITS_SYSON_SPS0LDO_WT_8821C                                            \\\n\t(BIT_MASK_SYSON_SPS0LDO_WT_8821C << BIT_SHIFT_SYSON_SPS0LDO_WT_8821C)\n#define BIT_CLEAR_SYSON_SPS0LDO_WT_8821C(x)                                    \\\n\t((x) & (~BITS_SYSON_SPS0LDO_WT_8821C))\n#define BIT_GET_SYSON_SPS0LDO_WT_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) &                           \\\n\t BIT_MASK_SYSON_SPS0LDO_WT_8821C)\n#define BIT_SET_SYSON_SPS0LDO_WT_8821C(x, v)                                   \\\n\t(BIT_CLEAR_SYSON_SPS0LDO_WT_8821C(x) | BIT_SYSON_SPS0LDO_WT_8821C(v))\n\n#define BIT_SHIFT_SYSON_RCLK_SCALE_8821C 0\n#define BIT_MASK_SYSON_RCLK_SCALE_8821C 0x3\n#define BIT_SYSON_RCLK_SCALE_8821C(x)                                          \\\n\t(((x) & BIT_MASK_SYSON_RCLK_SCALE_8821C)                               \\\n\t << BIT_SHIFT_SYSON_RCLK_SCALE_8821C)\n#define BITS_SYSON_RCLK_SCALE_8821C                                            \\\n\t(BIT_MASK_SYSON_RCLK_SCALE_8821C << BIT_SHIFT_SYSON_RCLK_SCALE_8821C)\n#define BIT_CLEAR_SYSON_RCLK_SCALE_8821C(x)                                    \\\n\t((x) & (~BITS_SYSON_RCLK_SCALE_8821C))\n#define BIT_GET_SYSON_RCLK_SCALE_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8821C) &                           \\\n\t BIT_MASK_SYSON_RCLK_SCALE_8821C)\n#define BIT_SET_SYSON_RCLK_SCALE_8821C(x, v)                                   \\\n\t(BIT_CLEAR_SYSON_RCLK_SCALE_8821C(x) | BIT_SYSON_RCLK_SCALE_8821C(v))\n\n/* 2 REG_CAL_TIMER_8821C */\n\n#define BIT_SHIFT_MATCH_CNT_8821C 8\n#define BIT_MASK_MATCH_CNT_8821C 0xff\n#define BIT_MATCH_CNT_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C)\n#define BITS_MATCH_CNT_8821C                                                   \\\n\t(BIT_MASK_MATCH_CNT_8821C << BIT_SHIFT_MATCH_CNT_8821C)\n#define BIT_CLEAR_MATCH_CNT_8821C(x) ((x) & (~BITS_MATCH_CNT_8821C))\n#define BIT_GET_MATCH_CNT_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C)\n#define BIT_SET_MATCH_CNT_8821C(x, v)                                          \\\n\t(BIT_CLEAR_MATCH_CNT_8821C(x) | BIT_MATCH_CNT_8821C(v))\n\n#define BIT_SHIFT_CAL_SCAL_8821C 0\n#define BIT_MASK_CAL_SCAL_8821C 0xff\n#define BIT_CAL_SCAL_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_CAL_SCAL_8821C) << BIT_SHIFT_CAL_SCAL_8821C)\n#define BITS_CAL_SCAL_8821C                                                    \\\n\t(BIT_MASK_CAL_SCAL_8821C << BIT_SHIFT_CAL_SCAL_8821C)\n#define BIT_CLEAR_CAL_SCAL_8821C(x) ((x) & (~BITS_CAL_SCAL_8821C))\n#define BIT_GET_CAL_SCAL_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_CAL_SCAL_8821C) & BIT_MASK_CAL_SCAL_8821C)\n#define BIT_SET_CAL_SCAL_8821C(x, v)                                           \\\n\t(BIT_CLEAR_CAL_SCAL_8821C(x) | BIT_CAL_SCAL_8821C(v))\n\n/* 2 REG_ACLK_MON_8821C */\n\n#define BIT_SHIFT_RCLK_MON_8821C 5\n#define BIT_MASK_RCLK_MON_8821C 0x7ff\n#define BIT_RCLK_MON_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_RCLK_MON_8821C) << BIT_SHIFT_RCLK_MON_8821C)\n#define BITS_RCLK_MON_8821C                                                    \\\n\t(BIT_MASK_RCLK_MON_8821C << BIT_SHIFT_RCLK_MON_8821C)\n#define BIT_CLEAR_RCLK_MON_8821C(x) ((x) & (~BITS_RCLK_MON_8821C))\n#define BIT_GET_RCLK_MON_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RCLK_MON_8821C) & BIT_MASK_RCLK_MON_8821C)\n#define BIT_SET_RCLK_MON_8821C(x, v)                                           \\\n\t(BIT_CLEAR_RCLK_MON_8821C(x) | BIT_RCLK_MON_8821C(v))\n\n#define BIT_CAL_EN_8821C BIT(4)\n\n#define BIT_SHIFT_DPSTU_8821C 2\n#define BIT_MASK_DPSTU_8821C 0x3\n#define BIT_DPSTU_8821C(x)                                                     \\\n\t(((x) & BIT_MASK_DPSTU_8821C) << BIT_SHIFT_DPSTU_8821C)\n#define BITS_DPSTU_8821C (BIT_MASK_DPSTU_8821C << BIT_SHIFT_DPSTU_8821C)\n#define BIT_CLEAR_DPSTU_8821C(x) ((x) & (~BITS_DPSTU_8821C))\n#define BIT_GET_DPSTU_8821C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DPSTU_8821C) & BIT_MASK_DPSTU_8821C)\n#define BIT_SET_DPSTU_8821C(x, v)                                              \\\n\t(BIT_CLEAR_DPSTU_8821C(x) | BIT_DPSTU_8821C(v))\n\n#define BIT_SUS_16X_8821C BIT(1)\n\n/* 2 REG_GPIO_MUXCFG_8821C */\n#define BIT_FSPI_EN_8821C BIT(19)\n#define BIT_WL_RTS_EXT_32K_SEL_8821C BIT(18)\n#define BIT_WLGP_SPI_EN_8821C BIT(16)\n#define BIT_SIC_LBK_8821C BIT(15)\n#define BIT_ENHTP_8821C BIT(14)\n#define BIT_ENSIC_8821C BIT(12)\n#define BIT_SIC_SWRST_8821C BIT(11)\n#define BIT_PO_WIFI_PTA_PINS_8821C BIT(10)\n#define BIT_PO_BT_PTA_PINS_8821C BIT(9)\n#define BIT_ENUART_8821C BIT(8)\n\n#define BIT_SHIFT_BTMODE_8821C 6\n#define BIT_MASK_BTMODE_8821C 0x3\n#define BIT_BTMODE_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_BTMODE_8821C) << BIT_SHIFT_BTMODE_8821C)\n#define BITS_BTMODE_8821C (BIT_MASK_BTMODE_8821C << BIT_SHIFT_BTMODE_8821C)\n#define BIT_CLEAR_BTMODE_8821C(x) ((x) & (~BITS_BTMODE_8821C))\n#define BIT_GET_BTMODE_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_BTMODE_8821C) & BIT_MASK_BTMODE_8821C)\n#define BIT_SET_BTMODE_8821C(x, v)                                             \\\n\t(BIT_CLEAR_BTMODE_8821C(x) | BIT_BTMODE_8821C(v))\n\n#define BIT_ENBT_8821C BIT(5)\n#define BIT_EROM_EN_8821C BIT(4)\n#define BIT_WLRFE_6_7_EN_8821C BIT(3)\n#define BIT_WLRFE_4_5_EN_8821C BIT(2)\n\n#define BIT_SHIFT_GPIOSEL_8821C 0\n#define BIT_MASK_GPIOSEL_8821C 0x3\n#define BIT_GPIOSEL_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_GPIOSEL_8821C) << BIT_SHIFT_GPIOSEL_8821C)\n#define BITS_GPIOSEL_8821C (BIT_MASK_GPIOSEL_8821C << BIT_SHIFT_GPIOSEL_8821C)\n#define BIT_CLEAR_GPIOSEL_8821C(x) ((x) & (~BITS_GPIOSEL_8821C))\n#define BIT_GET_GPIOSEL_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_GPIOSEL_8821C) & BIT_MASK_GPIOSEL_8821C)\n#define BIT_SET_GPIOSEL_8821C(x, v)                                            \\\n\t(BIT_CLEAR_GPIOSEL_8821C(x) | BIT_GPIOSEL_8821C(v))\n\n/* 2 REG_GPIO_PIN_CTRL_8821C */\n\n#define BIT_SHIFT_GPIO_MOD_7_TO_0_8821C 24\n#define BIT_MASK_GPIO_MOD_7_TO_0_8821C 0xff\n#define BIT_GPIO_MOD_7_TO_0_8821C(x)                                           \\\n\t(((x) & BIT_MASK_GPIO_MOD_7_TO_0_8821C)                                \\\n\t << BIT_SHIFT_GPIO_MOD_7_TO_0_8821C)\n#define BITS_GPIO_MOD_7_TO_0_8821C                                             \\\n\t(BIT_MASK_GPIO_MOD_7_TO_0_8821C << BIT_SHIFT_GPIO_MOD_7_TO_0_8821C)\n#define BIT_CLEAR_GPIO_MOD_7_TO_0_8821C(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8821C))\n#define BIT_GET_GPIO_MOD_7_TO_0_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8821C) &                            \\\n\t BIT_MASK_GPIO_MOD_7_TO_0_8821C)\n#define BIT_SET_GPIO_MOD_7_TO_0_8821C(x, v)                                    \\\n\t(BIT_CLEAR_GPIO_MOD_7_TO_0_8821C(x) | BIT_GPIO_MOD_7_TO_0_8821C(v))\n\n#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C 16\n#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C 0xff\n#define BIT_GPIO_IO_SEL_7_TO_0_8821C(x)                                        \\\n\t(((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C)                             \\\n\t << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C)\n#define BITS_GPIO_IO_SEL_7_TO_0_8821C                                          \\\n\t(BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C                                     \\\n\t << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C)\n#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8821C(x)                                  \\\n\t((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8821C))\n#define BIT_GET_GPIO_IO_SEL_7_TO_0_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) &                         \\\n\t BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C)\n#define BIT_SET_GPIO_IO_SEL_7_TO_0_8821C(x, v)                                 \\\n\t(BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8821C(x) |                               \\\n\t BIT_GPIO_IO_SEL_7_TO_0_8821C(v))\n\n#define BIT_SHIFT_GPIO_OUT_7_TO_0_8821C 8\n#define BIT_MASK_GPIO_OUT_7_TO_0_8821C 0xff\n#define BIT_GPIO_OUT_7_TO_0_8821C(x)                                           \\\n\t(((x) & BIT_MASK_GPIO_OUT_7_TO_0_8821C)                                \\\n\t << BIT_SHIFT_GPIO_OUT_7_TO_0_8821C)\n#define BITS_GPIO_OUT_7_TO_0_8821C                                             \\\n\t(BIT_MASK_GPIO_OUT_7_TO_0_8821C << BIT_SHIFT_GPIO_OUT_7_TO_0_8821C)\n#define BIT_CLEAR_GPIO_OUT_7_TO_0_8821C(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8821C))\n#define BIT_GET_GPIO_OUT_7_TO_0_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) &                            \\\n\t BIT_MASK_GPIO_OUT_7_TO_0_8821C)\n#define BIT_SET_GPIO_OUT_7_TO_0_8821C(x, v)                                    \\\n\t(BIT_CLEAR_GPIO_OUT_7_TO_0_8821C(x) | BIT_GPIO_OUT_7_TO_0_8821C(v))\n\n#define BIT_SHIFT_GPIO_IN_7_TO_0_8821C 0\n#define BIT_MASK_GPIO_IN_7_TO_0_8821C 0xff\n#define BIT_GPIO_IN_7_TO_0_8821C(x)                                            \\\n\t(((x) & BIT_MASK_GPIO_IN_7_TO_0_8821C)                                 \\\n\t << BIT_SHIFT_GPIO_IN_7_TO_0_8821C)\n#define BITS_GPIO_IN_7_TO_0_8821C                                              \\\n\t(BIT_MASK_GPIO_IN_7_TO_0_8821C << BIT_SHIFT_GPIO_IN_7_TO_0_8821C)\n#define BIT_CLEAR_GPIO_IN_7_TO_0_8821C(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8821C))\n#define BIT_GET_GPIO_IN_7_TO_0_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8821C) &                             \\\n\t BIT_MASK_GPIO_IN_7_TO_0_8821C)\n#define BIT_SET_GPIO_IN_7_TO_0_8821C(x, v)                                     \\\n\t(BIT_CLEAR_GPIO_IN_7_TO_0_8821C(x) | BIT_GPIO_IN_7_TO_0_8821C(v))\n\n/* 2 REG_GPIO_INTM_8821C */\n\n#define BIT_SHIFT_MUXDBG_SEL_8821C 30\n#define BIT_MASK_MUXDBG_SEL_8821C 0x3\n#define BIT_MUXDBG_SEL_8821C(x)                                                \\\n\t(((x) & BIT_MASK_MUXDBG_SEL_8821C) << BIT_SHIFT_MUXDBG_SEL_8821C)\n#define BITS_MUXDBG_SEL_8821C                                                  \\\n\t(BIT_MASK_MUXDBG_SEL_8821C << BIT_SHIFT_MUXDBG_SEL_8821C)\n#define BIT_CLEAR_MUXDBG_SEL_8821C(x) ((x) & (~BITS_MUXDBG_SEL_8821C))\n#define BIT_GET_MUXDBG_SEL_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_MUXDBG_SEL_8821C) & BIT_MASK_MUXDBG_SEL_8821C)\n#define BIT_SET_MUXDBG_SEL_8821C(x, v)                                         \\\n\t(BIT_CLEAR_MUXDBG_SEL_8821C(x) | BIT_MUXDBG_SEL_8821C(v))\n\n#define BIT_EXTWOL_SEL_8821C BIT(17)\n#define BIT_EXTWOL_EN_8821C BIT(16)\n#define BIT_GPIOF_INT_MD_8821C BIT(15)\n#define BIT_GPIOE_INT_MD_8821C BIT(14)\n#define BIT_GPIOD_INT_MD_8821C BIT(13)\n#define BIT_GPIOF_INT_MD_8821C BIT(15)\n#define BIT_GPIOE_INT_MD_8821C BIT(14)\n#define BIT_GPIOD_INT_MD_8821C BIT(13)\n#define BIT_GPIOC_INT_MD_8821C BIT(12)\n#define BIT_GPIOB_INT_MD_8821C BIT(11)\n#define BIT_GPIOA_INT_MD_8821C BIT(10)\n#define BIT_GPIO9_INT_MD_8821C BIT(9)\n#define BIT_GPIO8_INT_MD_8821C BIT(8)\n#define BIT_GPIO7_INT_MD_8821C BIT(7)\n#define BIT_GPIO6_INT_MD_8821C BIT(6)\n#define BIT_GPIO5_INT_MD_8821C BIT(5)\n#define BIT_GPIO4_INT_MD_8821C BIT(4)\n#define BIT_GPIO3_INT_MD_8821C BIT(3)\n#define BIT_GPIO2_INT_MD_8821C BIT(2)\n#define BIT_GPIO1_INT_MD_8821C BIT(1)\n#define BIT_GPIO0_INT_MD_8821C BIT(0)\n\n/* 2 REG_LED_CFG_8821C */\n#define BIT_GPIO3_WL_CTRL_EN_8821C BIT(27)\n#define BIT_LNAON_SEL_EN_8821C BIT(26)\n#define BIT_PAPE_SEL_EN_8821C BIT(25)\n#define BIT_DPDT_WLBT_SEL_8821C BIT(24)\n#define BIT_DPDT_SEL_EN_8821C BIT(23)\n#define BIT_GPIO13_14_WL_CTRL_EN_8821C BIT(22)\n#define BIT_LED2DIS_8821C BIT(21)\n#define BIT_LED2PL_8821C BIT(20)\n#define BIT_LED2SV_8821C BIT(19)\n\n#define BIT_SHIFT_LED2CM_8821C 16\n#define BIT_MASK_LED2CM_8821C 0x7\n#define BIT_LED2CM_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_LED2CM_8821C) << BIT_SHIFT_LED2CM_8821C)\n#define BITS_LED2CM_8821C (BIT_MASK_LED2CM_8821C << BIT_SHIFT_LED2CM_8821C)\n#define BIT_CLEAR_LED2CM_8821C(x) ((x) & (~BITS_LED2CM_8821C))\n#define BIT_GET_LED2CM_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_LED2CM_8821C) & BIT_MASK_LED2CM_8821C)\n#define BIT_SET_LED2CM_8821C(x, v)                                             \\\n\t(BIT_CLEAR_LED2CM_8821C(x) | BIT_LED2CM_8821C(v))\n\n#define BIT_LED1DIS_8821C BIT(15)\n#define BIT_LED1PL_8821C BIT(12)\n#define BIT_LED1SV_8821C BIT(11)\n\n#define BIT_SHIFT_LED1CM_8821C 8\n#define BIT_MASK_LED1CM_8821C 0x7\n#define BIT_LED1CM_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_LED1CM_8821C) << BIT_SHIFT_LED1CM_8821C)\n#define BITS_LED1CM_8821C (BIT_MASK_LED1CM_8821C << BIT_SHIFT_LED1CM_8821C)\n#define BIT_CLEAR_LED1CM_8821C(x) ((x) & (~BITS_LED1CM_8821C))\n#define BIT_GET_LED1CM_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_LED1CM_8821C) & BIT_MASK_LED1CM_8821C)\n#define BIT_SET_LED1CM_8821C(x, v)                                             \\\n\t(BIT_CLEAR_LED1CM_8821C(x) | BIT_LED1CM_8821C(v))\n\n#define BIT_LED0DIS_8821C BIT(7)\n\n#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C 5\n#define BIT_MASK_AFE_LDO_SWR_CHECK_8821C 0x3\n#define BIT_AFE_LDO_SWR_CHECK_8821C(x)                                         \\\n\t(((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8821C)                              \\\n\t << BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C)\n#define BITS_AFE_LDO_SWR_CHECK_8821C                                           \\\n\t(BIT_MASK_AFE_LDO_SWR_CHECK_8821C << BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C)\n#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8821C(x)                                   \\\n\t((x) & (~BITS_AFE_LDO_SWR_CHECK_8821C))\n#define BIT_GET_AFE_LDO_SWR_CHECK_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) &                          \\\n\t BIT_MASK_AFE_LDO_SWR_CHECK_8821C)\n#define BIT_SET_AFE_LDO_SWR_CHECK_8821C(x, v)                                  \\\n\t(BIT_CLEAR_AFE_LDO_SWR_CHECK_8821C(x) | BIT_AFE_LDO_SWR_CHECK_8821C(v))\n\n#define BIT_LED0PL_8821C BIT(4)\n#define BIT_LED0SV_8821C BIT(3)\n\n#define BIT_SHIFT_LED0CM_8821C 0\n#define BIT_MASK_LED0CM_8821C 0x7\n#define BIT_LED0CM_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_LED0CM_8821C) << BIT_SHIFT_LED0CM_8821C)\n#define BITS_LED0CM_8821C (BIT_MASK_LED0CM_8821C << BIT_SHIFT_LED0CM_8821C)\n#define BIT_CLEAR_LED0CM_8821C(x) ((x) & (~BITS_LED0CM_8821C))\n#define BIT_GET_LED0CM_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_LED0CM_8821C) & BIT_MASK_LED0CM_8821C)\n#define BIT_SET_LED0CM_8821C(x, v)                                             \\\n\t(BIT_CLEAR_LED0CM_8821C(x) | BIT_LED0CM_8821C(v))\n\n/* 2 REG_FSIMR_8821C */\n#define BIT_FS_PDNINT_EN_8821C BIT(31)\n#define BIT_NFC_INT_PAD_EN_8821C BIT(30)\n#define BIT_FS_SPS_OCP_INT_EN_8821C BIT(29)\n#define BIT_FS_PWMERR_INT_EN_8821C BIT(28)\n#define BIT_FS_GPIOF_INT_EN_8821C BIT(27)\n#define BIT_FS_GPIOE_INT_EN_8821C BIT(26)\n#define BIT_FS_GPIOD_INT_EN_8821C BIT(25)\n#define BIT_FS_GPIOC_INT_EN_8821C BIT(24)\n#define BIT_FS_GPIOB_INT_EN_8821C BIT(23)\n#define BIT_FS_GPIOA_INT_EN_8821C BIT(22)\n#define BIT_FS_GPIO9_INT_EN_8821C BIT(21)\n#define BIT_FS_GPIO8_INT_EN_8821C BIT(20)\n#define BIT_FS_GPIO7_INT_EN_8821C BIT(19)\n#define BIT_FS_GPIO6_INT_EN_8821C BIT(18)\n#define BIT_FS_GPIO5_INT_EN_8821C BIT(17)\n#define BIT_FS_GPIO4_INT_EN_8821C BIT(16)\n#define BIT_FS_GPIO3_INT_EN_8821C BIT(15)\n#define BIT_FS_GPIO2_INT_EN_8821C BIT(14)\n#define BIT_FS_GPIO1_INT_EN_8821C BIT(13)\n#define BIT_FS_GPIO0_INT_EN_8821C BIT(12)\n#define BIT_FS_HCI_SUS_EN_8821C BIT(11)\n#define BIT_FS_HCI_RES_EN_8821C BIT(10)\n#define BIT_FS_HCI_RESET_EN_8821C BIT(9)\n#define BIT_USB_SCSI_CMD_EN_8821C BIT(8)\n#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8821C BIT(7)\n#define BIT_ACT2RECOVERY_INT_EN_V1_8821C BIT(6)\n#define BIT_GEN1GEN2_SWITCH_8821C BIT(5)\n#define BIT_HCI_TXDMA_REQ_HIMR_8821C BIT(4)\n#define BIT_FS_32K_LEAVE_SETTING_MAK_8821C BIT(3)\n#define BIT_FS_32K_ENTER_SETTING_MAK_8821C BIT(2)\n#define BIT_FS_USB_LPMRSM_MSK_8821C BIT(1)\n#define BIT_FS_USB_LPMINT_MSK_8821C BIT(0)\n\n/* 2 REG_FSISR_8821C */\n#define BIT_FS_PDNINT_8821C BIT(31)\n#define BIT_FS_SPS_OCP_INT_8821C BIT(29)\n#define BIT_FS_PWMERR_INT_8821C BIT(28)\n#define BIT_FS_GPIOF_INT_8821C BIT(27)\n#define BIT_FS_GPIOE_INT_8821C BIT(26)\n#define BIT_FS_GPIOD_INT_8821C BIT(25)\n#define BIT_FS_GPIOC_INT_8821C BIT(24)\n#define BIT_FS_GPIOB_INT_8821C BIT(23)\n#define BIT_FS_GPIOA_INT_8821C BIT(22)\n#define BIT_FS_GPIO9_INT_8821C BIT(21)\n#define BIT_FS_GPIO8_INT_8821C BIT(20)\n#define BIT_FS_GPIO7_INT_8821C BIT(19)\n#define BIT_FS_GPIO6_INT_8821C BIT(18)\n#define BIT_FS_GPIO5_INT_8821C BIT(17)\n#define BIT_FS_GPIO4_INT_8821C BIT(16)\n#define BIT_FS_GPIO3_INT_8821C BIT(15)\n#define BIT_FS_GPIO2_INT_8821C BIT(14)\n#define BIT_FS_GPIO1_INT_8821C BIT(13)\n#define BIT_FS_GPIO0_INT_8821C BIT(12)\n#define BIT_FS_HCI_SUS_INT_8821C BIT(11)\n#define BIT_FS_HCI_RES_INT_8821C BIT(10)\n#define BIT_FS_HCI_RESET_INT_8821C BIT(9)\n#define BIT_USB_SCSI_CMD_INT_8821C BIT(8)\n#define BIT_ACT2RECOVERY_8821C BIT(6)\n#define BIT_GEN1GEN2_SWITCH_8821C BIT(5)\n#define BIT_HCI_TXDMA_REQ_HISR_8821C BIT(4)\n#define BIT_FS_32K_LEAVE_SETTING_INT_8821C BIT(3)\n#define BIT_FS_32K_ENTER_SETTING_INT_8821C BIT(2)\n#define BIT_FS_USB_LPMRSM_INT_8821C BIT(1)\n#define BIT_FS_USB_LPMINT_INT_8821C BIT(0)\n\n/* 2 REG_HSIMR_8821C */\n#define BIT_GPIOF_INT_EN_8821C BIT(31)\n#define BIT_GPIOE_INT_EN_8821C BIT(30)\n#define BIT_GPIOD_INT_EN_8821C BIT(29)\n#define BIT_GPIOC_INT_EN_8821C BIT(28)\n#define BIT_GPIOB_INT_EN_8821C BIT(27)\n#define BIT_GPIOA_INT_EN_8821C BIT(26)\n#define BIT_GPIO9_INT_EN_8821C BIT(25)\n#define BIT_GPIO8_INT_EN_8821C BIT(24)\n#define BIT_GPIO7_INT_EN_8821C BIT(23)\n#define BIT_GPIO6_INT_EN_8821C BIT(22)\n#define BIT_GPIO5_INT_EN_8821C BIT(21)\n#define BIT_GPIO4_INT_EN_8821C BIT(20)\n#define BIT_GPIO3_INT_EN_8821C BIT(19)\n#define BIT_GPIO2_INT_EN_V1_8821C BIT(18)\n#define BIT_GPIO1_INT_EN_8821C BIT(17)\n#define BIT_GPIO0_INT_EN_8821C BIT(16)\n#define BIT_PDNINT_EN_8821C BIT(7)\n#define BIT_RON_INT_EN_8821C BIT(6)\n#define BIT_SPS_OCP_INT_EN_8821C BIT(5)\n#define BIT_GPIO15_0_INT_EN_8821C BIT(0)\n\n/* 2 REG_HSISR_8821C */\n#define BIT_GPIOF_INT_8821C BIT(31)\n#define BIT_GPIOE_INT_8821C BIT(30)\n#define BIT_GPIOD_INT_8821C BIT(29)\n#define BIT_GPIOC_INT_8821C BIT(28)\n#define BIT_GPIOB_INT_8821C BIT(27)\n#define BIT_GPIOA_INT_8821C BIT(26)\n#define BIT_GPIO9_INT_8821C BIT(25)\n#define BIT_GPIO8_INT_8821C BIT(24)\n#define BIT_GPIO7_INT_8821C BIT(23)\n#define BIT_GPIO6_INT_8821C BIT(22)\n#define BIT_GPIO5_INT_8821C BIT(21)\n#define BIT_GPIO4_INT_8821C BIT(20)\n#define BIT_GPIO3_INT_8821C BIT(19)\n#define BIT_GPIO2_INT_V1_8821C BIT(18)\n#define BIT_GPIO1_INT_8821C BIT(17)\n#define BIT_GPIO0_INT_8821C BIT(16)\n#define BIT_PDNINT_8821C BIT(7)\n#define BIT_RON_INT_8821C BIT(6)\n#define BIT_SPS_OCP_INT_8821C BIT(5)\n#define BIT_GPIO15_0_INT_8821C BIT(0)\n\n/* 2 REG_GPIO_EXT_CTRL_8821C */\n\n#define BIT_SHIFT_GPIO_MOD_15_TO_8_8821C 24\n#define BIT_MASK_GPIO_MOD_15_TO_8_8821C 0xff\n#define BIT_GPIO_MOD_15_TO_8_8821C(x)                                          \\\n\t(((x) & BIT_MASK_GPIO_MOD_15_TO_8_8821C)                               \\\n\t << BIT_SHIFT_GPIO_MOD_15_TO_8_8821C)\n#define BITS_GPIO_MOD_15_TO_8_8821C                                            \\\n\t(BIT_MASK_GPIO_MOD_15_TO_8_8821C << BIT_SHIFT_GPIO_MOD_15_TO_8_8821C)\n#define BIT_CLEAR_GPIO_MOD_15_TO_8_8821C(x)                                    \\\n\t((x) & (~BITS_GPIO_MOD_15_TO_8_8821C))\n#define BIT_GET_GPIO_MOD_15_TO_8_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8821C) &                           \\\n\t BIT_MASK_GPIO_MOD_15_TO_8_8821C)\n#define BIT_SET_GPIO_MOD_15_TO_8_8821C(x, v)                                   \\\n\t(BIT_CLEAR_GPIO_MOD_15_TO_8_8821C(x) | BIT_GPIO_MOD_15_TO_8_8821C(v))\n\n#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C 16\n#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C 0xff\n#define BIT_GPIO_IO_SEL_15_TO_8_8821C(x)                                       \\\n\t(((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C)                            \\\n\t << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C)\n#define BITS_GPIO_IO_SEL_15_TO_8_8821C                                         \\\n\t(BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C                                    \\\n\t << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C)\n#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8821C(x)                                 \\\n\t((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8821C))\n#define BIT_GET_GPIO_IO_SEL_15_TO_8_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) &                        \\\n\t BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C)\n#define BIT_SET_GPIO_IO_SEL_15_TO_8_8821C(x, v)                                \\\n\t(BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8821C(x) |                              \\\n\t BIT_GPIO_IO_SEL_15_TO_8_8821C(v))\n\n#define BIT_SHIFT_GPIO_OUT_15_TO_8_8821C 8\n#define BIT_MASK_GPIO_OUT_15_TO_8_8821C 0xff\n#define BIT_GPIO_OUT_15_TO_8_8821C(x)                                          \\\n\t(((x) & BIT_MASK_GPIO_OUT_15_TO_8_8821C)                               \\\n\t << BIT_SHIFT_GPIO_OUT_15_TO_8_8821C)\n#define BITS_GPIO_OUT_15_TO_8_8821C                                            \\\n\t(BIT_MASK_GPIO_OUT_15_TO_8_8821C << BIT_SHIFT_GPIO_OUT_15_TO_8_8821C)\n#define BIT_CLEAR_GPIO_OUT_15_TO_8_8821C(x)                                    \\\n\t((x) & (~BITS_GPIO_OUT_15_TO_8_8821C))\n#define BIT_GET_GPIO_OUT_15_TO_8_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) &                           \\\n\t BIT_MASK_GPIO_OUT_15_TO_8_8821C)\n#define BIT_SET_GPIO_OUT_15_TO_8_8821C(x, v)                                   \\\n\t(BIT_CLEAR_GPIO_OUT_15_TO_8_8821C(x) | BIT_GPIO_OUT_15_TO_8_8821C(v))\n\n#define BIT_SHIFT_GPIO_IN_15_TO_8_8821C 0\n#define BIT_MASK_GPIO_IN_15_TO_8_8821C 0xff\n#define BIT_GPIO_IN_15_TO_8_8821C(x)                                           \\\n\t(((x) & BIT_MASK_GPIO_IN_15_TO_8_8821C)                                \\\n\t << BIT_SHIFT_GPIO_IN_15_TO_8_8821C)\n#define BITS_GPIO_IN_15_TO_8_8821C                                             \\\n\t(BIT_MASK_GPIO_IN_15_TO_8_8821C << BIT_SHIFT_GPIO_IN_15_TO_8_8821C)\n#define BIT_CLEAR_GPIO_IN_15_TO_8_8821C(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8821C))\n#define BIT_GET_GPIO_IN_15_TO_8_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8821C) &                            \\\n\t BIT_MASK_GPIO_IN_15_TO_8_8821C)\n#define BIT_SET_GPIO_IN_15_TO_8_8821C(x, v)                                    \\\n\t(BIT_CLEAR_GPIO_IN_15_TO_8_8821C(x) | BIT_GPIO_IN_15_TO_8_8821C(v))\n\n/* 2 REG_PAD_CTRL1_8821C */\n#define BIT_PAPE_WLBT_SEL_8821C BIT(29)\n#define BIT_LNAON_WLBT_SEL_8821C BIT(28)\n#define BIT_BTGP_GPG3_FEN_8821C BIT(26)\n#define BIT_BTGP_GPG2_FEN_8821C BIT(25)\n#define BIT_BTGP_JTAG_EN_8821C BIT(24)\n#define BIT_XTAL_CLK_EXTARNAL_EN_8821C BIT(23)\n#define BIT_BTGP_UART0_EN_8821C BIT(22)\n#define BIT_BTGP_UART1_EN_8821C BIT(21)\n#define BIT_BTGP_SPI_EN_8821C BIT(20)\n#define BIT_BTGP_GPIO_E2_8821C BIT(19)\n#define BIT_BTGP_GPIO_EN_8821C BIT(18)\n\n#define BIT_SHIFT_BTGP_GPIO_SL_8821C 16\n#define BIT_MASK_BTGP_GPIO_SL_8821C 0x3\n#define BIT_BTGP_GPIO_SL_8821C(x)                                              \\\n\t(((x) & BIT_MASK_BTGP_GPIO_SL_8821C) << BIT_SHIFT_BTGP_GPIO_SL_8821C)\n#define BITS_BTGP_GPIO_SL_8821C                                                \\\n\t(BIT_MASK_BTGP_GPIO_SL_8821C << BIT_SHIFT_BTGP_GPIO_SL_8821C)\n#define BIT_CLEAR_BTGP_GPIO_SL_8821C(x) ((x) & (~BITS_BTGP_GPIO_SL_8821C))\n#define BIT_GET_BTGP_GPIO_SL_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BTGP_GPIO_SL_8821C) & BIT_MASK_BTGP_GPIO_SL_8821C)\n#define BIT_SET_BTGP_GPIO_SL_8821C(x, v)                                       \\\n\t(BIT_CLEAR_BTGP_GPIO_SL_8821C(x) | BIT_BTGP_GPIO_SL_8821C(v))\n\n#define BIT_PAD_SDIO_SR_8821C BIT(14)\n#define BIT_GPIO14_OUTPUT_PL_8821C BIT(13)\n#define BIT_HOST_WAKE_PAD_PULL_EN_8821C BIT(12)\n#define BIT_HOST_WAKE_PAD_SL_8821C BIT(11)\n#define BIT_PAD_LNAON_SR_8821C BIT(10)\n#define BIT_PAD_LNAON_E2_8821C BIT(9)\n#define BIT_SW_LNAON_G_SEL_DATA_8821C BIT(8)\n#define BIT_SW_LNAON_A_SEL_DATA_8821C BIT(7)\n#define BIT_PAD_PAPE_SR_8821C BIT(6)\n#define BIT_PAD_PAPE_E2_8821C BIT(5)\n#define BIT_SW_PAPE_G_SEL_DATA_8821C BIT(4)\n#define BIT_SW_PAPE_A_SEL_DATA_8821C BIT(3)\n#define BIT_PAD_DPDT_SR_8821C BIT(2)\n#define BIT_PAD_DPDT_PAD_E2_8821C BIT(1)\n#define BIT_SW_DPDT_SEL_DATA_8821C BIT(0)\n\n/* 2 REG_WL_BT_PWR_CTRL_8821C */\n#define BIT_ISO_BD2PP_8821C BIT(31)\n#define BIT_LDOV12B_EN_8821C BIT(30)\n#define BIT_CKEN_BTGPS_8821C BIT(29)\n#define BIT_FEN_BTGPS_8821C BIT(28)\n#define BIT_BTCPU_BOOTSEL_8821C BIT(27)\n#define BIT_SPI_SPEEDUP_8821C BIT(26)\n#define BIT_DEVWAKE_PAD_TYPE_SEL_8821C BIT(24)\n#define BIT_CLKREQ_PAD_TYPE_SEL_8821C BIT(23)\n#define BIT_ISO_BTPON2PP_8821C BIT(22)\n#define BIT_BT_HWROF_EN_8821C BIT(19)\n#define BIT_BT_FUNC_EN_8821C BIT(18)\n#define BIT_BT_HWPDN_SL_8821C BIT(17)\n#define BIT_BT_DISN_EN_8821C BIT(16)\n#define BIT_BT_PDN_PULL_EN_8821C BIT(15)\n#define BIT_WL_PDN_PULL_EN_8821C BIT(14)\n#define BIT_EXTERNAL_REQUEST_PL_8821C BIT(13)\n#define BIT_GPIO0_2_3_PULL_LOW_EN_8821C BIT(12)\n#define BIT_ISO_BA2PP_8821C BIT(11)\n#define BIT_BT_AFE_LDO_EN_8821C BIT(10)\n#define BIT_BT_AFE_PLL_EN_8821C BIT(9)\n#define BIT_BT_DIG_CLK_EN_8821C BIT(8)\n#define BIT_WL_DRV_EXIST_IDX_8821C BIT(5)\n#define BIT_DOP_EHPAD_8821C BIT(4)\n#define BIT_WL_HWROF_EN_8821C BIT(3)\n#define BIT_WL_FUNC_EN_8821C BIT(2)\n#define BIT_WL_HWPDN_SL_8821C BIT(1)\n#define BIT_WL_HWPDN_EN_8821C BIT(0)\n\n/* 2 REG_SDM_DEBUG_8821C */\n\n#define BIT_SHIFT_WLCLK_PHASE_8821C 0\n#define BIT_MASK_WLCLK_PHASE_8821C 0x1f\n#define BIT_WLCLK_PHASE_8821C(x)                                               \\\n\t(((x) & BIT_MASK_WLCLK_PHASE_8821C) << BIT_SHIFT_WLCLK_PHASE_8821C)\n#define BITS_WLCLK_PHASE_8821C                                                 \\\n\t(BIT_MASK_WLCLK_PHASE_8821C << BIT_SHIFT_WLCLK_PHASE_8821C)\n#define BIT_CLEAR_WLCLK_PHASE_8821C(x) ((x) & (~BITS_WLCLK_PHASE_8821C))\n#define BIT_GET_WLCLK_PHASE_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_WLCLK_PHASE_8821C) & BIT_MASK_WLCLK_PHASE_8821C)\n#define BIT_SET_WLCLK_PHASE_8821C(x, v)                                        \\\n\t(BIT_CLEAR_WLCLK_PHASE_8821C(x) | BIT_WLCLK_PHASE_8821C(v))\n\n/* 2 REG_SYS_SDIO_CTRL_8821C */\n#define BIT_DBG_GNT_WL_BT_8821C BIT(27)\n#define BIT_LTE_MUX_CTRL_PATH_8821C BIT(26)\n#define BIT_LTE_COEX_UART_8821C BIT(25)\n#define BIT_3W_LTE_WL_GPIO_8821C BIT(24)\n#define BIT_SDIO_INT_POLARITY_8821C BIT(19)\n#define BIT_SDIO_INT_8821C BIT(18)\n#define BIT_SDIO_OFF_EN_8821C BIT(17)\n#define BIT_SDIO_ON_EN_8821C BIT(16)\n#define BIT_PCIE_WAIT_TIMEOUT_EVENT_8821C BIT(10)\n#define BIT_PCIE_WAIT_TIME_8821C BIT(9)\n#define BIT_MPCIE_REFCLK_XTAL_SEL_8821C BIT(8)\n#define BIT_RES_USB_MASS_STORAGE_DESC_8821C BIT(1)\n#define BIT_USB_WAIT_TIME_8821C BIT(0)\n\n/* 2 REG_HCI_OPT_CTRL_8821C */\n\n#define BIT_SHIFT_TSFT_SEL_8821C 29\n#define BIT_MASK_TSFT_SEL_8821C 0x7\n#define BIT_TSFT_SEL_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_TSFT_SEL_8821C) << BIT_SHIFT_TSFT_SEL_8821C)\n#define BITS_TSFT_SEL_8821C                                                    \\\n\t(BIT_MASK_TSFT_SEL_8821C << BIT_SHIFT_TSFT_SEL_8821C)\n#define BIT_CLEAR_TSFT_SEL_8821C(x) ((x) & (~BITS_TSFT_SEL_8821C))\n#define BIT_GET_TSFT_SEL_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TSFT_SEL_8821C) & BIT_MASK_TSFT_SEL_8821C)\n#define BIT_SET_TSFT_SEL_8821C(x, v)                                           \\\n\t(BIT_CLEAR_TSFT_SEL_8821C(x) | BIT_TSFT_SEL_8821C(v))\n\n#define BIT_SDIO_PAD_E5_8821C BIT(18)\n#define BIT_USB_HOST_PWR_OFF_EN_8821C BIT(12)\n#define BIT_SYM_LPS_BLOCK_EN_8821C BIT(11)\n#define BIT_USB_LPM_ACT_EN_8821C BIT(10)\n#define BIT_USB_LPM_NY_8821C BIT(9)\n#define BIT_USB_SUS_DIS_8821C BIT(8)\n\n#define BIT_SHIFT_SDIO_PAD_E_8821C 5\n#define BIT_MASK_SDIO_PAD_E_8821C 0x7\n#define BIT_SDIO_PAD_E_8821C(x)                                                \\\n\t(((x) & BIT_MASK_SDIO_PAD_E_8821C) << BIT_SHIFT_SDIO_PAD_E_8821C)\n#define BITS_SDIO_PAD_E_8821C                                                  \\\n\t(BIT_MASK_SDIO_PAD_E_8821C << BIT_SHIFT_SDIO_PAD_E_8821C)\n#define BIT_CLEAR_SDIO_PAD_E_8821C(x) ((x) & (~BITS_SDIO_PAD_E_8821C))\n#define BIT_GET_SDIO_PAD_E_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_SDIO_PAD_E_8821C) & BIT_MASK_SDIO_PAD_E_8821C)\n#define BIT_SET_SDIO_PAD_E_8821C(x, v)                                         \\\n\t(BIT_CLEAR_SDIO_PAD_E_8821C(x) | BIT_SDIO_PAD_E_8821C(v))\n\n#define BIT_USB_LPPLL_EN_8821C BIT(4)\n#define BIT_ROP_SW15_8821C BIT(2)\n#define BIT_PCI_CKRDY_OPT_8821C BIT(1)\n#define BIT_PCI_VAUX_EN_8821C BIT(0)\n\n/* 2 REG_AFE_CTRL4_8821C */\n\n/* 2 REG_LDO_SWR_CTRL_8821C */\n#define BIT_ZCD_HW_AUTO_EN_8821C BIT(27)\n#define BIT_ZCD_REGSEL_8821C BIT(26)\n\n#define BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C 21\n#define BIT_MASK_AUTO_ZCD_IN_CODE_8821C 0x1f\n#define BIT_AUTO_ZCD_IN_CODE_8821C(x)                                          \\\n\t(((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8821C)                               \\\n\t << BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C)\n#define BITS_AUTO_ZCD_IN_CODE_8821C                                            \\\n\t(BIT_MASK_AUTO_ZCD_IN_CODE_8821C << BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C)\n#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8821C(x)                                    \\\n\t((x) & (~BITS_AUTO_ZCD_IN_CODE_8821C))\n#define BIT_GET_AUTO_ZCD_IN_CODE_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C) &                           \\\n\t BIT_MASK_AUTO_ZCD_IN_CODE_8821C)\n#define BIT_SET_AUTO_ZCD_IN_CODE_8821C(x, v)                                   \\\n\t(BIT_CLEAR_AUTO_ZCD_IN_CODE_8821C(x) | BIT_AUTO_ZCD_IN_CODE_8821C(v))\n\n#define BIT_SHIFT_ZCD_CODE_IN_L_8821C 16\n#define BIT_MASK_ZCD_CODE_IN_L_8821C 0x1f\n#define BIT_ZCD_CODE_IN_L_8821C(x)                                             \\\n\t(((x) & BIT_MASK_ZCD_CODE_IN_L_8821C) << BIT_SHIFT_ZCD_CODE_IN_L_8821C)\n#define BITS_ZCD_CODE_IN_L_8821C                                               \\\n\t(BIT_MASK_ZCD_CODE_IN_L_8821C << BIT_SHIFT_ZCD_CODE_IN_L_8821C)\n#define BIT_CLEAR_ZCD_CODE_IN_L_8821C(x) ((x) & (~BITS_ZCD_CODE_IN_L_8821C))\n#define BIT_GET_ZCD_CODE_IN_L_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8821C) & BIT_MASK_ZCD_CODE_IN_L_8821C)\n#define BIT_SET_ZCD_CODE_IN_L_8821C(x, v)                                      \\\n\t(BIT_CLEAR_ZCD_CODE_IN_L_8821C(x) | BIT_ZCD_CODE_IN_L_8821C(v))\n\n#define BIT_SHIFT_LDO_HV5_DUMMY_8821C 14\n#define BIT_MASK_LDO_HV5_DUMMY_8821C 0x3\n#define BIT_LDO_HV5_DUMMY_8821C(x)                                             \\\n\t(((x) & BIT_MASK_LDO_HV5_DUMMY_8821C) << BIT_SHIFT_LDO_HV5_DUMMY_8821C)\n#define BITS_LDO_HV5_DUMMY_8821C                                               \\\n\t(BIT_MASK_LDO_HV5_DUMMY_8821C << BIT_SHIFT_LDO_HV5_DUMMY_8821C)\n#define BIT_CLEAR_LDO_HV5_DUMMY_8821C(x) ((x) & (~BITS_LDO_HV5_DUMMY_8821C))\n#define BIT_GET_LDO_HV5_DUMMY_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8821C) & BIT_MASK_LDO_HV5_DUMMY_8821C)\n#define BIT_SET_LDO_HV5_DUMMY_8821C(x, v)                                      \\\n\t(BIT_CLEAR_LDO_HV5_DUMMY_8821C(x) | BIT_LDO_HV5_DUMMY_8821C(v))\n\n#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C 12\n#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C 0x3\n#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8821C(x)                                  \\\n\t(((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C)                       \\\n\t << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C)\n#define BITS_REG_VTUNE33_BIT0_TO_BIT1_8821C                                    \\\n\t(BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C                               \\\n\t << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C)\n#define BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8821C(x)                            \\\n\t((x) & (~BITS_REG_VTUNE33_BIT0_TO_BIT1_8821C))\n#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8821C(x)                              \\\n\t(((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) &                   \\\n\t BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C)\n#define BIT_SET_REG_VTUNE33_BIT0_TO_BIT1_8821C(x, v)                           \\\n\t(BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) |                         \\\n\t BIT_REG_VTUNE33_BIT0_TO_BIT1_8821C(v))\n\n#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C 10\n#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C 0x3\n#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8821C(x)                                \\\n\t(((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C)                     \\\n\t << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C)\n#define BITS_REG_STANDBY33_BIT0_TO_BIT1_8821C                                  \\\n\t(BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C                             \\\n\t << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C)\n#define BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8821C(x)                          \\\n\t((x) & (~BITS_REG_STANDBY33_BIT0_TO_BIT1_8821C))\n#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8821C(x)                            \\\n\t(((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) &                 \\\n\t BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C)\n#define BIT_SET_REG_STANDBY33_BIT0_TO_BIT1_8821C(x, v)                         \\\n\t(BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) |                       \\\n\t BIT_REG_STANDBY33_BIT0_TO_BIT1_8821C(v))\n\n#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C 8\n#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C 0x3\n#define BIT_REG_LOAD33_BIT0_TO_BIT1_8821C(x)                                   \\\n\t(((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C)                        \\\n\t << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C)\n#define BITS_REG_LOAD33_BIT0_TO_BIT1_8821C                                     \\\n\t(BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C                                \\\n\t << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C)\n#define BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8821C(x)                             \\\n\t((x) & (~BITS_REG_LOAD33_BIT0_TO_BIT1_8821C))\n#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8821C(x)                               \\\n\t(((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) &                    \\\n\t BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C)\n#define BIT_SET_REG_LOAD33_BIT0_TO_BIT1_8821C(x, v)                            \\\n\t(BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8821C(x) |                          \\\n\t BIT_REG_LOAD33_BIT0_TO_BIT1_8821C(v))\n\n#define BIT_REG_BYPASS_L_8821C BIT(7)\n#define BIT_REG_LDOF_L_8821C BIT(6)\n#define BIT_REG_OCPS_L_8821C BIT(5)\n#define BIT_ARENB_L_8821C BIT(3)\n\n#define BIT_SHIFT_CFC_L_8821C 1\n#define BIT_MASK_CFC_L_8821C 0x3\n#define BIT_CFC_L_8821C(x)                                                     \\\n\t(((x) & BIT_MASK_CFC_L_8821C) << BIT_SHIFT_CFC_L_8821C)\n#define BITS_CFC_L_8821C (BIT_MASK_CFC_L_8821C << BIT_SHIFT_CFC_L_8821C)\n#define BIT_CLEAR_CFC_L_8821C(x) ((x) & (~BITS_CFC_L_8821C))\n#define BIT_GET_CFC_L_8821C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CFC_L_8821C) & BIT_MASK_CFC_L_8821C)\n#define BIT_SET_CFC_L_8821C(x, v)                                              \\\n\t(BIT_CLEAR_CFC_L_8821C(x) | BIT_CFC_L_8821C(v))\n\n#define BIT_REG_TYPE_L_8821C BIT(0)\n\n/* 2 REG_MCUFW_CTRL_8821C */\n\n#define BIT_SHIFT_RPWM_8821C 24\n#define BIT_MASK_RPWM_8821C 0xff\n#define BIT_RPWM_8821C(x) (((x) & BIT_MASK_RPWM_8821C) << BIT_SHIFT_RPWM_8821C)\n#define BITS_RPWM_8821C (BIT_MASK_RPWM_8821C << BIT_SHIFT_RPWM_8821C)\n#define BIT_CLEAR_RPWM_8821C(x) ((x) & (~BITS_RPWM_8821C))\n#define BIT_GET_RPWM_8821C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_RPWM_8821C) & BIT_MASK_RPWM_8821C)\n#define BIT_SET_RPWM_8821C(x, v) (BIT_CLEAR_RPWM_8821C(x) | BIT_RPWM_8821C(v))\n\n#define BIT_ANA_PORT_EN_8821C BIT(22)\n#define BIT_MAC_PORT_EN_8821C BIT(21)\n#define BIT_BOOT_FSPI_EN_8821C BIT(20)\n#define BIT_ROM_DLEN_8821C BIT(19)\n\n#define BIT_SHIFT_ROM_PGE_8821C 16\n#define BIT_MASK_ROM_PGE_8821C 0x7\n#define BIT_ROM_PGE_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_ROM_PGE_8821C) << BIT_SHIFT_ROM_PGE_8821C)\n#define BITS_ROM_PGE_8821C (BIT_MASK_ROM_PGE_8821C << BIT_SHIFT_ROM_PGE_8821C)\n#define BIT_CLEAR_ROM_PGE_8821C(x) ((x) & (~BITS_ROM_PGE_8821C))\n#define BIT_GET_ROM_PGE_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_ROM_PGE_8821C) & BIT_MASK_ROM_PGE_8821C)\n#define BIT_SET_ROM_PGE_8821C(x, v)                                            \\\n\t(BIT_CLEAR_ROM_PGE_8821C(x) | BIT_ROM_PGE_8821C(v))\n\n#define BIT_FW_INIT_RDY_8821C BIT(15)\n#define BIT_FW_DW_RDY_8821C BIT(14)\n\n#define BIT_SHIFT_CPU_CLK_SEL_8821C 12\n#define BIT_MASK_CPU_CLK_SEL_8821C 0x3\n#define BIT_CPU_CLK_SEL_8821C(x)                                               \\\n\t(((x) & BIT_MASK_CPU_CLK_SEL_8821C) << BIT_SHIFT_CPU_CLK_SEL_8821C)\n#define BITS_CPU_CLK_SEL_8821C                                                 \\\n\t(BIT_MASK_CPU_CLK_SEL_8821C << BIT_SHIFT_CPU_CLK_SEL_8821C)\n#define BIT_CLEAR_CPU_CLK_SEL_8821C(x) ((x) & (~BITS_CPU_CLK_SEL_8821C))\n#define BIT_GET_CPU_CLK_SEL_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_CPU_CLK_SEL_8821C) & BIT_MASK_CPU_CLK_SEL_8821C)\n#define BIT_SET_CPU_CLK_SEL_8821C(x, v)                                        \\\n\t(BIT_CLEAR_CPU_CLK_SEL_8821C(x) | BIT_CPU_CLK_SEL_8821C(v))\n\n#define BIT_CCLK_CHG_MASK_8821C BIT(11)\n#define BIT_EMEM__TXBUF_CHKSUM_OK_8821C BIT(10)\n#define BIT_EMEM_TXBUF_DW_RDY_8821C BIT(9)\n#define BIT_EMEM_CHKSUM_OK_8821C BIT(8)\n#define BIT_EMEM_DW_OK_8821C BIT(7)\n#define BIT_DMEM_CHKSUM_OK_8821C BIT(6)\n#define BIT_DMEM_DW_OK_8821C BIT(5)\n#define BIT_IMEM_CHKSUM_OK_8821C BIT(4)\n#define BIT_IMEM_DW_OK_8821C BIT(3)\n#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK_8821C BIT(2)\n#define BIT_IMEM_BOOT_LOAD_DW_OK_8821C BIT(1)\n#define BIT_MCUFWDL_EN_8821C BIT(0)\n\n/* 2 REG_MCU_TST_CFG_8821C */\n\n#define BIT_SHIFT_C2H_MSG_8821C 0\n#define BIT_MASK_C2H_MSG_8821C 0xffff\n#define BIT_C2H_MSG_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_C2H_MSG_8821C) << BIT_SHIFT_C2H_MSG_8821C)\n#define BITS_C2H_MSG_8821C (BIT_MASK_C2H_MSG_8821C << BIT_SHIFT_C2H_MSG_8821C)\n#define BIT_CLEAR_C2H_MSG_8821C(x) ((x) & (~BITS_C2H_MSG_8821C))\n#define BIT_GET_C2H_MSG_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_C2H_MSG_8821C) & BIT_MASK_C2H_MSG_8821C)\n#define BIT_SET_C2H_MSG_8821C(x, v)                                            \\\n\t(BIT_CLEAR_C2H_MSG_8821C(x) | BIT_C2H_MSG_8821C(v))\n\n/* 2 REG_HMEBOX_E0_E1_8821C */\n\n#define BIT_SHIFT_HOST_MSG_E1_8821C 16\n#define BIT_MASK_HOST_MSG_E1_8821C 0xffff\n#define BIT_HOST_MSG_E1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E1_8821C) << BIT_SHIFT_HOST_MSG_E1_8821C)\n#define BITS_HOST_MSG_E1_8821C                                                 \\\n\t(BIT_MASK_HOST_MSG_E1_8821C << BIT_SHIFT_HOST_MSG_E1_8821C)\n#define BIT_CLEAR_HOST_MSG_E1_8821C(x) ((x) & (~BITS_HOST_MSG_E1_8821C))\n#define BIT_GET_HOST_MSG_E1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E1_8821C) & BIT_MASK_HOST_MSG_E1_8821C)\n#define BIT_SET_HOST_MSG_E1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E1_8821C(x) | BIT_HOST_MSG_E1_8821C(v))\n\n#define BIT_SHIFT_HOST_MSG_E0_8821C 0\n#define BIT_MASK_HOST_MSG_E0_8821C 0xffff\n#define BIT_HOST_MSG_E0_8821C(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E0_8821C) << BIT_SHIFT_HOST_MSG_E0_8821C)\n#define BITS_HOST_MSG_E0_8821C                                                 \\\n\t(BIT_MASK_HOST_MSG_E0_8821C << BIT_SHIFT_HOST_MSG_E0_8821C)\n#define BIT_CLEAR_HOST_MSG_E0_8821C(x) ((x) & (~BITS_HOST_MSG_E0_8821C))\n#define BIT_GET_HOST_MSG_E0_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E0_8821C) & BIT_MASK_HOST_MSG_E0_8821C)\n#define BIT_SET_HOST_MSG_E0_8821C(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E0_8821C(x) | BIT_HOST_MSG_E0_8821C(v))\n\n/* 2 REG_HMEBOX_E2_E3_8821C */\n\n#define BIT_SHIFT_HOST_MSG_E3_8821C 16\n#define BIT_MASK_HOST_MSG_E3_8821C 0xffff\n#define BIT_HOST_MSG_E3_8821C(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E3_8821C) << BIT_SHIFT_HOST_MSG_E3_8821C)\n#define BITS_HOST_MSG_E3_8821C                                                 \\\n\t(BIT_MASK_HOST_MSG_E3_8821C << BIT_SHIFT_HOST_MSG_E3_8821C)\n#define BIT_CLEAR_HOST_MSG_E3_8821C(x) ((x) & (~BITS_HOST_MSG_E3_8821C))\n#define BIT_GET_HOST_MSG_E3_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E3_8821C) & BIT_MASK_HOST_MSG_E3_8821C)\n#define BIT_SET_HOST_MSG_E3_8821C(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E3_8821C(x) | BIT_HOST_MSG_E3_8821C(v))\n\n#define BIT_SHIFT_HOST_MSG_E2_8821C 0\n#define BIT_MASK_HOST_MSG_E2_8821C 0xffff\n#define BIT_HOST_MSG_E2_8821C(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E2_8821C) << BIT_SHIFT_HOST_MSG_E2_8821C)\n#define BITS_HOST_MSG_E2_8821C                                                 \\\n\t(BIT_MASK_HOST_MSG_E2_8821C << BIT_SHIFT_HOST_MSG_E2_8821C)\n#define BIT_CLEAR_HOST_MSG_E2_8821C(x) ((x) & (~BITS_HOST_MSG_E2_8821C))\n#define BIT_GET_HOST_MSG_E2_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E2_8821C) & BIT_MASK_HOST_MSG_E2_8821C)\n#define BIT_SET_HOST_MSG_E2_8821C(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E2_8821C(x) | BIT_HOST_MSG_E2_8821C(v))\n\n/* 2 REG_WLLPS_CTRL_8821C */\n#define BIT_WLLPSOP_EABM_8821C BIT(31)\n#define BIT_WLLPSOP_ACKF_8821C BIT(30)\n#define BIT_WLLPSOP_DLDM_8821C BIT(29)\n#define BIT_WLLPSOP_ESWR_8821C BIT(28)\n#define BIT_WLLPSOP_PWMM_8821C BIT(27)\n#define BIT_WLLPSOP_EECK_8821C BIT(26)\n#define BIT_WLLPSOP_WLMACOFF_8821C BIT(25)\n#define BIT_WLLPSOP_EXTAL_8821C BIT(24)\n#define BIT_WL_SYNPON_VOLTSPDN_8821C BIT(23)\n#define BIT_WLLPSOP_WLBBOFF_8821C BIT(22)\n#define BIT_WLLPSOP_WLMEM_DS_8821C BIT(21)\n\n#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C 12\n#define BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C 0xf\n#define BIT_LPLDH12_VADJ_STEP_DN_8821C(x)                                      \\\n\t(((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C)                           \\\n\t << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C)\n#define BITS_LPLDH12_VADJ_STEP_DN_8821C                                        \\\n\t(BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C                                   \\\n\t << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C)\n#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8821C(x)                                \\\n\t((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8821C))\n#define BIT_GET_LPLDH12_VADJ_STEP_DN_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C) &                       \\\n\t BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C)\n#define BIT_SET_LPLDH12_VADJ_STEP_DN_8821C(x, v)                               \\\n\t(BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8821C(x) |                             \\\n\t BIT_LPLDH12_VADJ_STEP_DN_8821C(v))\n\n#define BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C 8\n#define BIT_MASK_V15ADJ_L1_STEP_DN_8821C 0x7\n#define BIT_V15ADJ_L1_STEP_DN_8821C(x)                                         \\\n\t(((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8821C)                              \\\n\t << BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C)\n#define BITS_V15ADJ_L1_STEP_DN_8821C                                           \\\n\t(BIT_MASK_V15ADJ_L1_STEP_DN_8821C << BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C)\n#define BIT_CLEAR_V15ADJ_L1_STEP_DN_8821C(x)                                   \\\n\t((x) & (~BITS_V15ADJ_L1_STEP_DN_8821C))\n#define BIT_GET_V15ADJ_L1_STEP_DN_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) &                          \\\n\t BIT_MASK_V15ADJ_L1_STEP_DN_8821C)\n#define BIT_SET_V15ADJ_L1_STEP_DN_8821C(x, v)                                  \\\n\t(BIT_CLEAR_V15ADJ_L1_STEP_DN_8821C(x) | BIT_V15ADJ_L1_STEP_DN_8821C(v))\n\n#define BIT_REGU_32K_CLK_EN_8821C BIT(1)\n#define BIT_WL_LPS_EN_8821C BIT(0)\n\n/* 2 REG_AFE_CTRL5_8821C */\n#define BIT_BB_DBG_SEL_AFE_SDM_BIT0_8821C BIT(31)\n#define BIT_ORDER_SDM_8821C BIT(30)\n#define BIT_RFE_SEL_SDM_8821C BIT(29)\n\n#define BIT_SHIFT_REF_SEL_8821C 25\n#define BIT_MASK_REF_SEL_8821C 0xf\n#define BIT_REF_SEL_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_REF_SEL_8821C) << BIT_SHIFT_REF_SEL_8821C)\n#define BITS_REF_SEL_8821C (BIT_MASK_REF_SEL_8821C << BIT_SHIFT_REF_SEL_8821C)\n#define BIT_CLEAR_REF_SEL_8821C(x) ((x) & (~BITS_REF_SEL_8821C))\n#define BIT_GET_REF_SEL_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_REF_SEL_8821C) & BIT_MASK_REF_SEL_8821C)\n#define BIT_SET_REF_SEL_8821C(x, v)                                            \\\n\t(BIT_CLEAR_REF_SEL_8821C(x) | BIT_REF_SEL_8821C(v))\n\n#define BIT_SHIFT_F0F_SDM_8821C 12\n#define BIT_MASK_F0F_SDM_8821C 0x1fff\n#define BIT_F0F_SDM_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_F0F_SDM_8821C) << BIT_SHIFT_F0F_SDM_8821C)\n#define BITS_F0F_SDM_8821C (BIT_MASK_F0F_SDM_8821C << BIT_SHIFT_F0F_SDM_8821C)\n#define BIT_CLEAR_F0F_SDM_8821C(x) ((x) & (~BITS_F0F_SDM_8821C))\n#define BIT_GET_F0F_SDM_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_F0F_SDM_8821C) & BIT_MASK_F0F_SDM_8821C)\n#define BIT_SET_F0F_SDM_8821C(x, v)                                            \\\n\t(BIT_CLEAR_F0F_SDM_8821C(x) | BIT_F0F_SDM_8821C(v))\n\n#define BIT_SHIFT_F0N_SDM_8821C 9\n#define BIT_MASK_F0N_SDM_8821C 0x7\n#define BIT_F0N_SDM_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_F0N_SDM_8821C) << BIT_SHIFT_F0N_SDM_8821C)\n#define BITS_F0N_SDM_8821C (BIT_MASK_F0N_SDM_8821C << BIT_SHIFT_F0N_SDM_8821C)\n#define BIT_CLEAR_F0N_SDM_8821C(x) ((x) & (~BITS_F0N_SDM_8821C))\n#define BIT_GET_F0N_SDM_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_F0N_SDM_8821C) & BIT_MASK_F0N_SDM_8821C)\n#define BIT_SET_F0N_SDM_8821C(x, v)                                            \\\n\t(BIT_CLEAR_F0N_SDM_8821C(x) | BIT_F0N_SDM_8821C(v))\n\n#define BIT_SHIFT_DIVN_SDM_8821C 3\n#define BIT_MASK_DIVN_SDM_8821C 0x3f\n#define BIT_DIVN_SDM_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_DIVN_SDM_8821C) << BIT_SHIFT_DIVN_SDM_8821C)\n#define BITS_DIVN_SDM_8821C                                                    \\\n\t(BIT_MASK_DIVN_SDM_8821C << BIT_SHIFT_DIVN_SDM_8821C)\n#define BIT_CLEAR_DIVN_SDM_8821C(x) ((x) & (~BITS_DIVN_SDM_8821C))\n#define BIT_GET_DIVN_SDM_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_DIVN_SDM_8821C) & BIT_MASK_DIVN_SDM_8821C)\n#define BIT_SET_DIVN_SDM_8821C(x, v)                                           \\\n\t(BIT_CLEAR_DIVN_SDM_8821C(x) | BIT_DIVN_SDM_8821C(v))\n\n/* 2 REG_GPIO_DEBOUNCE_CTRL_8821C */\n#define BIT_WLGP_DBC1EN_8821C BIT(15)\n\n#define BIT_SHIFT_WLGP_DBC1_8821C 8\n#define BIT_MASK_WLGP_DBC1_8821C 0xf\n#define BIT_WLGP_DBC1_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_WLGP_DBC1_8821C) << BIT_SHIFT_WLGP_DBC1_8821C)\n#define BITS_WLGP_DBC1_8821C                                                   \\\n\t(BIT_MASK_WLGP_DBC1_8821C << BIT_SHIFT_WLGP_DBC1_8821C)\n#define BIT_CLEAR_WLGP_DBC1_8821C(x) ((x) & (~BITS_WLGP_DBC1_8821C))\n#define BIT_GET_WLGP_DBC1_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_WLGP_DBC1_8821C) & BIT_MASK_WLGP_DBC1_8821C)\n#define BIT_SET_WLGP_DBC1_8821C(x, v)                                          \\\n\t(BIT_CLEAR_WLGP_DBC1_8821C(x) | BIT_WLGP_DBC1_8821C(v))\n\n#define BIT_WLGP_DBC0EN_8821C BIT(7)\n\n#define BIT_SHIFT_WLGP_DBC0_8821C 0\n#define BIT_MASK_WLGP_DBC0_8821C 0xf\n#define BIT_WLGP_DBC0_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_WLGP_DBC0_8821C) << BIT_SHIFT_WLGP_DBC0_8821C)\n#define BITS_WLGP_DBC0_8821C                                                   \\\n\t(BIT_MASK_WLGP_DBC0_8821C << BIT_SHIFT_WLGP_DBC0_8821C)\n#define BIT_CLEAR_WLGP_DBC0_8821C(x) ((x) & (~BITS_WLGP_DBC0_8821C))\n#define BIT_GET_WLGP_DBC0_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_WLGP_DBC0_8821C) & BIT_MASK_WLGP_DBC0_8821C)\n#define BIT_SET_WLGP_DBC0_8821C(x, v)                                          \\\n\t(BIT_CLEAR_WLGP_DBC0_8821C(x) | BIT_WLGP_DBC0_8821C(v))\n\n/* 2 REG_RPWM2_8821C */\n\n#define BIT_SHIFT_RPWM2_8821C 16\n#define BIT_MASK_RPWM2_8821C 0xffff\n#define BIT_RPWM2_8821C(x)                                                     \\\n\t(((x) & BIT_MASK_RPWM2_8821C) << BIT_SHIFT_RPWM2_8821C)\n#define BITS_RPWM2_8821C (BIT_MASK_RPWM2_8821C << BIT_SHIFT_RPWM2_8821C)\n#define BIT_CLEAR_RPWM2_8821C(x) ((x) & (~BITS_RPWM2_8821C))\n#define BIT_GET_RPWM2_8821C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RPWM2_8821C) & BIT_MASK_RPWM2_8821C)\n#define BIT_SET_RPWM2_8821C(x, v)                                              \\\n\t(BIT_CLEAR_RPWM2_8821C(x) | BIT_RPWM2_8821C(v))\n\n/* 2 REG_SYSON_FSM_MON_8821C */\n\n#define BIT_SHIFT_FSM_MON_SEL_8821C 24\n#define BIT_MASK_FSM_MON_SEL_8821C 0x7\n#define BIT_FSM_MON_SEL_8821C(x)                                               \\\n\t(((x) & BIT_MASK_FSM_MON_SEL_8821C) << BIT_SHIFT_FSM_MON_SEL_8821C)\n#define BITS_FSM_MON_SEL_8821C                                                 \\\n\t(BIT_MASK_FSM_MON_SEL_8821C << BIT_SHIFT_FSM_MON_SEL_8821C)\n#define BIT_CLEAR_FSM_MON_SEL_8821C(x) ((x) & (~BITS_FSM_MON_SEL_8821C))\n#define BIT_GET_FSM_MON_SEL_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_FSM_MON_SEL_8821C) & BIT_MASK_FSM_MON_SEL_8821C)\n#define BIT_SET_FSM_MON_SEL_8821C(x, v)                                        \\\n\t(BIT_CLEAR_FSM_MON_SEL_8821C(x) | BIT_FSM_MON_SEL_8821C(v))\n\n#define BIT_DOP_ELDO_8821C BIT(23)\n#define BIT_FSM_MON_UPD_8821C BIT(15)\n\n#define BIT_SHIFT_FSM_PAR_8821C 0\n#define BIT_MASK_FSM_PAR_8821C 0x7fff\n#define BIT_FSM_PAR_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_FSM_PAR_8821C) << BIT_SHIFT_FSM_PAR_8821C)\n#define BITS_FSM_PAR_8821C (BIT_MASK_FSM_PAR_8821C << BIT_SHIFT_FSM_PAR_8821C)\n#define BIT_CLEAR_FSM_PAR_8821C(x) ((x) & (~BITS_FSM_PAR_8821C))\n#define BIT_GET_FSM_PAR_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_FSM_PAR_8821C) & BIT_MASK_FSM_PAR_8821C)\n#define BIT_SET_FSM_PAR_8821C(x, v)                                            \\\n\t(BIT_CLEAR_FSM_PAR_8821C(x) | BIT_FSM_PAR_8821C(v))\n\n/* 2 REG_AFE_CTRL6_8821C */\n\n#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C 0\n#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C 0x7\n#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x)                                 \\\n\t(((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C)                      \\\n\t << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C)\n#define BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C                                   \\\n\t(BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C                              \\\n\t << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C)\n#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x)                           \\\n\t((x) & (~BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C))\n#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x)                             \\\n\t(((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) &                  \\\n\t BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C)\n#define BIT_SET_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x, v)                          \\\n\t(BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) |                        \\\n\t BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(v))\n\n/* 2 REG_PMC_DBG_CTRL1_8821C */\n#define BIT_BT_INT_EN_8821C BIT(31)\n\n#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C 16\n#define BIT_MASK_RD_WR_WIFI_BT_INFO_8821C 0x7fff\n#define BIT_RD_WR_WIFI_BT_INFO_8821C(x)                                        \\\n\t(((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8821C)                             \\\n\t << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C)\n#define BITS_RD_WR_WIFI_BT_INFO_8821C                                          \\\n\t(BIT_MASK_RD_WR_WIFI_BT_INFO_8821C                                     \\\n\t << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C)\n#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8821C(x)                                  \\\n\t((x) & (~BITS_RD_WR_WIFI_BT_INFO_8821C))\n#define BIT_GET_RD_WR_WIFI_BT_INFO_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) &                         \\\n\t BIT_MASK_RD_WR_WIFI_BT_INFO_8821C)\n#define BIT_SET_RD_WR_WIFI_BT_INFO_8821C(x, v)                                 \\\n\t(BIT_CLEAR_RD_WR_WIFI_BT_INFO_8821C(x) |                               \\\n\t BIT_RD_WR_WIFI_BT_INFO_8821C(v))\n\n#define BIT_PMC_WR_OVF_8821C BIT(8)\n\n#define BIT_SHIFT_WLPMC_ERRINT_8821C 0\n#define BIT_MASK_WLPMC_ERRINT_8821C 0xff\n#define BIT_WLPMC_ERRINT_8821C(x)                                              \\\n\t(((x) & BIT_MASK_WLPMC_ERRINT_8821C) << BIT_SHIFT_WLPMC_ERRINT_8821C)\n#define BITS_WLPMC_ERRINT_8821C                                                \\\n\t(BIT_MASK_WLPMC_ERRINT_8821C << BIT_SHIFT_WLPMC_ERRINT_8821C)\n#define BIT_CLEAR_WLPMC_ERRINT_8821C(x) ((x) & (~BITS_WLPMC_ERRINT_8821C))\n#define BIT_GET_WLPMC_ERRINT_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_WLPMC_ERRINT_8821C) & BIT_MASK_WLPMC_ERRINT_8821C)\n#define BIT_SET_WLPMC_ERRINT_8821C(x, v)                                       \\\n\t(BIT_CLEAR_WLPMC_ERRINT_8821C(x) | BIT_WLPMC_ERRINT_8821C(v))\n\n/* 2 REG_AFE_CTRL7_8821C */\n\n#define BIT_SHIFT_SEL_V_8821C 30\n#define BIT_MASK_SEL_V_8821C 0x3\n#define BIT_SEL_V_8821C(x)                                                     \\\n\t(((x) & BIT_MASK_SEL_V_8821C) << BIT_SHIFT_SEL_V_8821C)\n#define BITS_SEL_V_8821C (BIT_MASK_SEL_V_8821C << BIT_SHIFT_SEL_V_8821C)\n#define BIT_CLEAR_SEL_V_8821C(x) ((x) & (~BITS_SEL_V_8821C))\n#define BIT_GET_SEL_V_8821C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_SEL_V_8821C) & BIT_MASK_SEL_V_8821C)\n#define BIT_SET_SEL_V_8821C(x, v)                                              \\\n\t(BIT_CLEAR_SEL_V_8821C(x) | BIT_SEL_V_8821C(v))\n\n#define BIT_SEL_LDO_PC_8821C BIT(29)\n\n#define BIT_SHIFT_CK_MON_SEL_8821C 26\n#define BIT_MASK_CK_MON_SEL_8821C 0x7\n#define BIT_CK_MON_SEL_8821C(x)                                                \\\n\t(((x) & BIT_MASK_CK_MON_SEL_8821C) << BIT_SHIFT_CK_MON_SEL_8821C)\n#define BITS_CK_MON_SEL_8821C                                                  \\\n\t(BIT_MASK_CK_MON_SEL_8821C << BIT_SHIFT_CK_MON_SEL_8821C)\n#define BIT_CLEAR_CK_MON_SEL_8821C(x) ((x) & (~BITS_CK_MON_SEL_8821C))\n#define BIT_GET_CK_MON_SEL_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_CK_MON_SEL_8821C) & BIT_MASK_CK_MON_SEL_8821C)\n#define BIT_SET_CK_MON_SEL_8821C(x, v)                                         \\\n\t(BIT_CLEAR_CK_MON_SEL_8821C(x) | BIT_CK_MON_SEL_8821C(v))\n\n#define BIT_CK_MON_EN_8821C BIT(25)\n#define BIT_FREF_EDGE_8821C BIT(24)\n#define BIT_CK320M_EN_8821C BIT(23)\n#define BIT_CK_5M_EN_8821C BIT(22)\n#define BIT_TESTEN_8821C BIT(21)\n\n/* 2 REG_HIMR0_8821C */\n#define BIT_TIMEOUT_INTERRUPT2_MASK_8821C BIT(31)\n#define BIT_TIMEOUT_INTERRUTP1_MASK_8821C BIT(30)\n#define BIT_PSTIMEOUT_MSK_8821C BIT(29)\n#define BIT_GTINT4_MSK_8821C BIT(28)\n#define BIT_GTINT3_MSK_8821C BIT(27)\n#define BIT_TXBCN0ERR_MSK_8821C BIT(26)\n#define BIT_TXBCN0OK_MSK_8821C BIT(25)\n#define BIT_TSF_BIT32_TOGGLE_MSK_8821C BIT(24)\n#define BIT_BCNDMAINT0_MSK_8821C BIT(20)\n#define BIT_BCNDERR0_MSK_8821C BIT(16)\n#define BIT_HSISR_IND_ON_INT_MSK_8821C BIT(15)\n#define BIT_BCNDMAINT_E_MSK_8821C BIT(14)\n#define BIT_CTWEND_MSK_8821C BIT(12)\n#define BIT_HISR1_IND_MSK_8821C BIT(11)\n#define BIT_C2HCMD_MSK_8821C BIT(10)\n#define BIT_CPWM2_MSK_8821C BIT(9)\n#define BIT_CPWM_MSK_8821C BIT(8)\n#define BIT_HIGHDOK_MSK_8821C BIT(7)\n#define BIT_MGTDOK_MSK_8821C BIT(6)\n#define BIT_BKDOK_MSK_8821C BIT(5)\n#define BIT_BEDOK_MSK_8821C BIT(4)\n#define BIT_VIDOK_MSK_8821C BIT(3)\n#define BIT_VODOK_MSK_8821C BIT(2)\n#define BIT_RDU_MSK_8821C BIT(1)\n#define BIT_RXOK_MSK_8821C BIT(0)\n\n/* 2 REG_HISR0_8821C */\n#define BIT_PSTIMEOUT2_8821C BIT(31)\n#define BIT_PSTIMEOUT1_8821C BIT(30)\n#define BIT_PSTIMEOUT_8821C BIT(29)\n#define BIT_GTINT4_8821C BIT(28)\n#define BIT_GTINT3_8821C BIT(27)\n#define BIT_TXBCN0ERR_8821C BIT(26)\n#define BIT_TXBCN0OK_8821C BIT(25)\n#define BIT_TSF_BIT32_TOGGLE_8821C BIT(24)\n#define BIT_BCNDMAINT0_8821C BIT(20)\n#define BIT_BCNDERR0_8821C BIT(16)\n#define BIT_HSISR_IND_ON_INT_8821C BIT(15)\n#define BIT_BCNDMAINT_E_8821C BIT(14)\n#define BIT_CTWEND_8821C BIT(12)\n#define BIT_HISR1_IND_INT_8821C BIT(11)\n#define BIT_C2HCMD_8821C BIT(10)\n#define BIT_CPWM2_8821C BIT(9)\n#define BIT_CPWM_8821C BIT(8)\n#define BIT_HIGHDOK_8821C BIT(7)\n#define BIT_MGTDOK_8821C BIT(6)\n#define BIT_BKDOK_8821C BIT(5)\n#define BIT_BEDOK_8821C BIT(4)\n#define BIT_VIDOK_8821C BIT(3)\n#define BIT_VODOK_8821C BIT(2)\n#define BIT_RDU_8821C BIT(1)\n#define BIT_RXOK_8821C BIT(0)\n\n/* 2 REG_HIMR1_8821C */\n#define BIT_TXFIFO_TH_INT_8821C BIT(30)\n#define BIT_BTON_STS_UPDATE_MASK_8821C BIT(29)\n#define BIT_MCU_ERR_MASK_8821C BIT(28)\n#define BIT_BCNDMAINT7__MSK_8821C BIT(27)\n#define BIT_BCNDMAINT6__MSK_8821C BIT(26)\n#define BIT_BCNDMAINT5__MSK_8821C BIT(25)\n#define BIT_BCNDMAINT4__MSK_8821C BIT(24)\n#define BIT_BCNDMAINT3_MSK_8821C BIT(23)\n#define BIT_BCNDMAINT2_MSK_8821C BIT(22)\n#define BIT_BCNDMAINT1_MSK_8821C BIT(21)\n#define BIT_BCNDERR7_MSK_8821C BIT(20)\n#define BIT_BCNDERR6_MSK_8821C BIT(19)\n#define BIT_BCNDERR5_MSK_8821C BIT(18)\n#define BIT_BCNDERR4_MSK_8821C BIT(17)\n#define BIT_BCNDERR3_MSK_8821C BIT(16)\n#define BIT_BCNDERR2_MSK_8821C BIT(15)\n#define BIT_BCNDERR1_MSK_8821C BIT(14)\n#define BIT_ATIMEND_E_MSK_8821C BIT(13)\n#define BIT_ATIMEND__MSK_8821C BIT(12)\n#define BIT_TXERR_MSK_8821C BIT(11)\n#define BIT_RXERR_MSK_8821C BIT(10)\n#define BIT_TXFOVW_MSK_8821C BIT(9)\n#define BIT_FOVW_MSK_8821C BIT(8)\n#define BIT_CPU_MGQ_TXDONE_MSK_8821C BIT(5)\n#define BIT_PS_TIMER_C_MSK_8821C BIT(4)\n#define BIT_PS_TIMER_B_MSK_8821C BIT(3)\n#define BIT_PS_TIMER_A_MSK_8821C BIT(2)\n#define BIT_CPUMGQ_TX_TIMER_MSK_8821C BIT(1)\n\n/* 2 REG_HISR1_8821C */\n#define BIT_TXFIFO_TH_INT_8821C BIT(30)\n#define BIT_BTON_STS_UPDATE_INT_8821C BIT(29)\n#define BIT_MCU_ERR_8821C BIT(28)\n#define BIT_BCNDMAINT7_8821C BIT(27)\n#define BIT_BCNDMAINT6_8821C BIT(26)\n#define BIT_BCNDMAINT5_8821C BIT(25)\n#define BIT_BCNDMAINT4_8821C BIT(24)\n#define BIT_BCNDMAINT3_8821C BIT(23)\n#define BIT_BCNDMAINT2_8821C BIT(22)\n#define BIT_BCNDMAINT1_8821C BIT(21)\n#define BIT_BCNDERR7_8821C BIT(20)\n#define BIT_BCNDERR6_8821C BIT(19)\n#define BIT_BCNDERR5_8821C BIT(18)\n#define BIT_BCNDERR4_8821C BIT(17)\n#define BIT_BCNDERR3_8821C BIT(16)\n#define BIT_BCNDERR2_8821C BIT(15)\n#define BIT_BCNDERR1_8821C BIT(14)\n#define BIT_ATIMEND_E_8821C BIT(13)\n#define BIT_ATIMEND_8821C BIT(12)\n#define BIT_TXERR_INT_8821C BIT(11)\n#define BIT_RXERR_INT_8821C BIT(10)\n#define BIT_TXFOVW_8821C BIT(9)\n#define BIT_FOVW_8821C BIT(8)\n\n/* 2 REG_NOT_VALID_8821C */\n#define BIT_CPU_MGQ_TXDONE_8821C BIT(5)\n#define BIT_PS_TIMER_C_8821C BIT(4)\n#define BIT_PS_TIMER_B_8821C BIT(3)\n#define BIT_PS_TIMER_A_8821C BIT(2)\n#define BIT_CPUMGQ_TX_TIMER_8821C BIT(1)\n\n/* 2 REG_DBG_PORT_SEL_8821C */\n\n#define BIT_SHIFT_DEBUG_ST_8821C 0\n#define BIT_MASK_DEBUG_ST_8821C 0xffffffffL\n#define BIT_DEBUG_ST_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_DEBUG_ST_8821C) << BIT_SHIFT_DEBUG_ST_8821C)\n#define BITS_DEBUG_ST_8821C                                                    \\\n\t(BIT_MASK_DEBUG_ST_8821C << BIT_SHIFT_DEBUG_ST_8821C)\n#define BIT_CLEAR_DEBUG_ST_8821C(x) ((x) & (~BITS_DEBUG_ST_8821C))\n#define BIT_GET_DEBUG_ST_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_DEBUG_ST_8821C) & BIT_MASK_DEBUG_ST_8821C)\n#define BIT_SET_DEBUG_ST_8821C(x, v)                                           \\\n\t(BIT_CLEAR_DEBUG_ST_8821C(x) | BIT_DEBUG_ST_8821C(v))\n\n/* 2 REG_PAD_CTRL2_8821C */\n#define BIT_USB3_USB2_TRANSITION_8821C BIT(20)\n\n#define BIT_SHIFT_USB23_SW_MODE_V1_8821C 18\n#define BIT_MASK_USB23_SW_MODE_V1_8821C 0x3\n#define BIT_USB23_SW_MODE_V1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_USB23_SW_MODE_V1_8821C)                               \\\n\t << BIT_SHIFT_USB23_SW_MODE_V1_8821C)\n#define BITS_USB23_SW_MODE_V1_8821C                                            \\\n\t(BIT_MASK_USB23_SW_MODE_V1_8821C << BIT_SHIFT_USB23_SW_MODE_V1_8821C)\n#define BIT_CLEAR_USB23_SW_MODE_V1_8821C(x)                                    \\\n\t((x) & (~BITS_USB23_SW_MODE_V1_8821C))\n#define BIT_GET_USB23_SW_MODE_V1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8821C) &                           \\\n\t BIT_MASK_USB23_SW_MODE_V1_8821C)\n#define BIT_SET_USB23_SW_MODE_V1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_USB23_SW_MODE_V1_8821C(x) | BIT_USB23_SW_MODE_V1_8821C(v))\n\n#define BIT_NO_PDN_CHIPOFF_V1_8821C BIT(17)\n#define BIT_RSM_EN_V1_8821C BIT(16)\n\n#define BIT_SHIFT_MATCH_CNT_8821C 8\n#define BIT_MASK_MATCH_CNT_8821C 0xff\n#define BIT_MATCH_CNT_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C)\n#define BITS_MATCH_CNT_8821C                                                   \\\n\t(BIT_MASK_MATCH_CNT_8821C << BIT_SHIFT_MATCH_CNT_8821C)\n#define BIT_CLEAR_MATCH_CNT_8821C(x) ((x) & (~BITS_MATCH_CNT_8821C))\n#define BIT_GET_MATCH_CNT_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C)\n#define BIT_SET_MATCH_CNT_8821C(x, v)                                          \\\n\t(BIT_CLEAR_MATCH_CNT_8821C(x) | BIT_MATCH_CNT_8821C(v))\n\n#define BIT_LD_B12V_EN_8821C BIT(7)\n#define BIT_EECS_IOSEL_V1_8821C BIT(6)\n#define BIT_EECS_DATA_O_V1_8821C BIT(5)\n#define BIT_EECS_DATA_I_V1_8821C BIT(4)\n#define BIT_EESK_IOSEL_V1_8821C BIT(2)\n#define BIT_EESK_DATA_O_V1_8821C BIT(1)\n#define BIT_EESK_DATA_I_V1_8821C BIT(0)\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_PMC_DBG_CTRL2_8821C */\n\n#define BIT_SHIFT_EFUSE_BURN_GNT_8821C 24\n#define BIT_MASK_EFUSE_BURN_GNT_8821C 0xff\n#define BIT_EFUSE_BURN_GNT_8821C(x)                                            \\\n\t(((x) & BIT_MASK_EFUSE_BURN_GNT_8821C)                                 \\\n\t << BIT_SHIFT_EFUSE_BURN_GNT_8821C)\n#define BITS_EFUSE_BURN_GNT_8821C                                              \\\n\t(BIT_MASK_EFUSE_BURN_GNT_8821C << BIT_SHIFT_EFUSE_BURN_GNT_8821C)\n#define BIT_CLEAR_EFUSE_BURN_GNT_8821C(x) ((x) & (~BITS_EFUSE_BURN_GNT_8821C))\n#define BIT_GET_EFUSE_BURN_GNT_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8821C) &                             \\\n\t BIT_MASK_EFUSE_BURN_GNT_8821C)\n#define BIT_SET_EFUSE_BURN_GNT_8821C(x, v)                                     \\\n\t(BIT_CLEAR_EFUSE_BURN_GNT_8821C(x) | BIT_EFUSE_BURN_GNT_8821C(v))\n\n#define BIT_STOP_WL_PMC_8821C BIT(9)\n#define BIT_STOP_SYM_PMC_8821C BIT(8)\n#define BIT_BT_ACCESS_WL_PAGE0_8821C BIT(6)\n#define BIT_REG_RST_WLPMC_8821C BIT(5)\n#define BIT_REG_RST_PD12N_8821C BIT(4)\n#define BIT_SYSON_DIS_WLREG_WRMSK_8821C BIT(3)\n#define BIT_SYSON_DIS_PMCREG_WRMSK_8821C BIT(2)\n\n#define BIT_SHIFT_SYSON_REG_ARB_8821C 0\n#define BIT_MASK_SYSON_REG_ARB_8821C 0x3\n#define BIT_SYSON_REG_ARB_8821C(x)                                             \\\n\t(((x) & BIT_MASK_SYSON_REG_ARB_8821C) << BIT_SHIFT_SYSON_REG_ARB_8821C)\n#define BITS_SYSON_REG_ARB_8821C                                               \\\n\t(BIT_MASK_SYSON_REG_ARB_8821C << BIT_SHIFT_SYSON_REG_ARB_8821C)\n#define BIT_CLEAR_SYSON_REG_ARB_8821C(x) ((x) & (~BITS_SYSON_REG_ARB_8821C))\n#define BIT_GET_SYSON_REG_ARB_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SYSON_REG_ARB_8821C) & BIT_MASK_SYSON_REG_ARB_8821C)\n#define BIT_SET_SYSON_REG_ARB_8821C(x, v)                                      \\\n\t(BIT_CLEAR_SYSON_REG_ARB_8821C(x) | BIT_SYSON_REG_ARB_8821C(v))\n\n/* 2 REG_BIST_CTRL_8821C */\n#define BIT_BIST_USB_DIS_8821C BIT(27)\n#define BIT_BIST_PCI_DIS_8821C BIT(26)\n#define BIT_BIST_BT_DIS_8821C BIT(25)\n#define BIT_BIST_WL_DIS_8821C BIT(24)\n\n#define BIT_SHIFT_BIST_RPT_SEL_8821C 16\n#define BIT_MASK_BIST_RPT_SEL_8821C 0xf\n#define BIT_BIST_RPT_SEL_8821C(x)                                              \\\n\t(((x) & BIT_MASK_BIST_RPT_SEL_8821C) << BIT_SHIFT_BIST_RPT_SEL_8821C)\n#define BITS_BIST_RPT_SEL_8821C                                                \\\n\t(BIT_MASK_BIST_RPT_SEL_8821C << BIT_SHIFT_BIST_RPT_SEL_8821C)\n#define BIT_CLEAR_BIST_RPT_SEL_8821C(x) ((x) & (~BITS_BIST_RPT_SEL_8821C))\n#define BIT_GET_BIST_RPT_SEL_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BIST_RPT_SEL_8821C) & BIT_MASK_BIST_RPT_SEL_8821C)\n#define BIT_SET_BIST_RPT_SEL_8821C(x, v)                                       \\\n\t(BIT_CLEAR_BIST_RPT_SEL_8821C(x) | BIT_BIST_RPT_SEL_8821C(v))\n\n#define BIT_BIST_RESUME_PS_8821C BIT(4)\n#define BIT_BIST_RESUME_8821C BIT(3)\n#define BIT_BIST_NORMAL_8821C BIT(2)\n#define BIT_BIST_RSTN_8821C BIT(1)\n#define BIT_BIST_CLK_EN_8821C BIT(0)\n\n/* 2 REG_BIST_RPT_8821C */\n\n#define BIT_SHIFT_MBIST_REPORT_8821C 0\n#define BIT_MASK_MBIST_REPORT_8821C 0xffffffffL\n#define BIT_MBIST_REPORT_8821C(x)                                              \\\n\t(((x) & BIT_MASK_MBIST_REPORT_8821C) << BIT_SHIFT_MBIST_REPORT_8821C)\n#define BITS_MBIST_REPORT_8821C                                                \\\n\t(BIT_MASK_MBIST_REPORT_8821C << BIT_SHIFT_MBIST_REPORT_8821C)\n#define BIT_CLEAR_MBIST_REPORT_8821C(x) ((x) & (~BITS_MBIST_REPORT_8821C))\n#define BIT_GET_MBIST_REPORT_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_MBIST_REPORT_8821C) & BIT_MASK_MBIST_REPORT_8821C)\n#define BIT_SET_MBIST_REPORT_8821C(x, v)                                       \\\n\t(BIT_CLEAR_MBIST_REPORT_8821C(x) | BIT_MBIST_REPORT_8821C(v))\n\n/* 2 REG_MEM_CTRL_8821C */\n#define BIT_UMEM_RME_8821C BIT(31)\n\n#define BIT_SHIFT_BT_SPRAM_8821C 28\n#define BIT_MASK_BT_SPRAM_8821C 0x3\n#define BIT_BT_SPRAM_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_BT_SPRAM_8821C) << BIT_SHIFT_BT_SPRAM_8821C)\n#define BITS_BT_SPRAM_8821C                                                    \\\n\t(BIT_MASK_BT_SPRAM_8821C << BIT_SHIFT_BT_SPRAM_8821C)\n#define BIT_CLEAR_BT_SPRAM_8821C(x) ((x) & (~BITS_BT_SPRAM_8821C))\n#define BIT_GET_BT_SPRAM_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_BT_SPRAM_8821C) & BIT_MASK_BT_SPRAM_8821C)\n#define BIT_SET_BT_SPRAM_8821C(x, v)                                           \\\n\t(BIT_CLEAR_BT_SPRAM_8821C(x) | BIT_BT_SPRAM_8821C(v))\n\n#define BIT_SHIFT_BT_ROM_8821C 24\n#define BIT_MASK_BT_ROM_8821C 0xf\n#define BIT_BT_ROM_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_BT_ROM_8821C) << BIT_SHIFT_BT_ROM_8821C)\n#define BITS_BT_ROM_8821C (BIT_MASK_BT_ROM_8821C << BIT_SHIFT_BT_ROM_8821C)\n#define BIT_CLEAR_BT_ROM_8821C(x) ((x) & (~BITS_BT_ROM_8821C))\n#define BIT_GET_BT_ROM_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_BT_ROM_8821C) & BIT_MASK_BT_ROM_8821C)\n#define BIT_SET_BT_ROM_8821C(x, v)                                             \\\n\t(BIT_CLEAR_BT_ROM_8821C(x) | BIT_BT_ROM_8821C(v))\n\n#define BIT_SHIFT_PCI_DPRAM_8821C 10\n#define BIT_MASK_PCI_DPRAM_8821C 0x3\n#define BIT_PCI_DPRAM_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_PCI_DPRAM_8821C) << BIT_SHIFT_PCI_DPRAM_8821C)\n#define BITS_PCI_DPRAM_8821C                                                   \\\n\t(BIT_MASK_PCI_DPRAM_8821C << BIT_SHIFT_PCI_DPRAM_8821C)\n#define BIT_CLEAR_PCI_DPRAM_8821C(x) ((x) & (~BITS_PCI_DPRAM_8821C))\n#define BIT_GET_PCI_DPRAM_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_PCI_DPRAM_8821C) & BIT_MASK_PCI_DPRAM_8821C)\n#define BIT_SET_PCI_DPRAM_8821C(x, v)                                          \\\n\t(BIT_CLEAR_PCI_DPRAM_8821C(x) | BIT_PCI_DPRAM_8821C(v))\n\n#define BIT_SHIFT_PCI_SPRAM_8821C 8\n#define BIT_MASK_PCI_SPRAM_8821C 0x3\n#define BIT_PCI_SPRAM_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_PCI_SPRAM_8821C) << BIT_SHIFT_PCI_SPRAM_8821C)\n#define BITS_PCI_SPRAM_8821C                                                   \\\n\t(BIT_MASK_PCI_SPRAM_8821C << BIT_SHIFT_PCI_SPRAM_8821C)\n#define BIT_CLEAR_PCI_SPRAM_8821C(x) ((x) & (~BITS_PCI_SPRAM_8821C))\n#define BIT_GET_PCI_SPRAM_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_PCI_SPRAM_8821C) & BIT_MASK_PCI_SPRAM_8821C)\n#define BIT_SET_PCI_SPRAM_8821C(x, v)                                          \\\n\t(BIT_CLEAR_PCI_SPRAM_8821C(x) | BIT_PCI_SPRAM_8821C(v))\n\n#define BIT_SHIFT_USB_SPRAM_8821C 6\n#define BIT_MASK_USB_SPRAM_8821C 0x3\n#define BIT_USB_SPRAM_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_USB_SPRAM_8821C) << BIT_SHIFT_USB_SPRAM_8821C)\n#define BITS_USB_SPRAM_8821C                                                   \\\n\t(BIT_MASK_USB_SPRAM_8821C << BIT_SHIFT_USB_SPRAM_8821C)\n#define BIT_CLEAR_USB_SPRAM_8821C(x) ((x) & (~BITS_USB_SPRAM_8821C))\n#define BIT_GET_USB_SPRAM_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_USB_SPRAM_8821C) & BIT_MASK_USB_SPRAM_8821C)\n#define BIT_SET_USB_SPRAM_8821C(x, v)                                          \\\n\t(BIT_CLEAR_USB_SPRAM_8821C(x) | BIT_USB_SPRAM_8821C(v))\n\n#define BIT_SHIFT_USB_SPRF_8821C 4\n#define BIT_MASK_USB_SPRF_8821C 0x3\n#define BIT_USB_SPRF_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_USB_SPRF_8821C) << BIT_SHIFT_USB_SPRF_8821C)\n#define BITS_USB_SPRF_8821C                                                    \\\n\t(BIT_MASK_USB_SPRF_8821C << BIT_SHIFT_USB_SPRF_8821C)\n#define BIT_CLEAR_USB_SPRF_8821C(x) ((x) & (~BITS_USB_SPRF_8821C))\n#define BIT_GET_USB_SPRF_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_USB_SPRF_8821C) & BIT_MASK_USB_SPRF_8821C)\n#define BIT_SET_USB_SPRF_8821C(x, v)                                           \\\n\t(BIT_CLEAR_USB_SPRF_8821C(x) | BIT_USB_SPRF_8821C(v))\n\n#define BIT_SHIFT_MCU_ROM_8821C 0\n#define BIT_MASK_MCU_ROM_8821C 0xf\n#define BIT_MCU_ROM_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_MCU_ROM_8821C) << BIT_SHIFT_MCU_ROM_8821C)\n#define BITS_MCU_ROM_8821C (BIT_MASK_MCU_ROM_8821C << BIT_SHIFT_MCU_ROM_8821C)\n#define BIT_CLEAR_MCU_ROM_8821C(x) ((x) & (~BITS_MCU_ROM_8821C))\n#define BIT_GET_MCU_ROM_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_MCU_ROM_8821C) & BIT_MASK_MCU_ROM_8821C)\n#define BIT_SET_MCU_ROM_8821C(x, v)                                            \\\n\t(BIT_CLEAR_MCU_ROM_8821C(x) | BIT_MCU_ROM_8821C(v))\n\n/* 2 REG_AFE_CTRL8_8821C */\n#define BIT_SYN_AGPIO_8821C BIT(20)\n#define BIT_XTAL_LP_8821C BIT(4)\n#define BIT_XTAL_GM_SEP_8821C BIT(3)\n\n#define BIT_SHIFT_XTAL_SEL_TOK_8821C 0\n#define BIT_MASK_XTAL_SEL_TOK_8821C 0x7\n#define BIT_XTAL_SEL_TOK_8821C(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_SEL_TOK_8821C) << BIT_SHIFT_XTAL_SEL_TOK_8821C)\n#define BITS_XTAL_SEL_TOK_8821C                                                \\\n\t(BIT_MASK_XTAL_SEL_TOK_8821C << BIT_SHIFT_XTAL_SEL_TOK_8821C)\n#define BIT_CLEAR_XTAL_SEL_TOK_8821C(x) ((x) & (~BITS_XTAL_SEL_TOK_8821C))\n#define BIT_GET_XTAL_SEL_TOK_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_SEL_TOK_8821C) & BIT_MASK_XTAL_SEL_TOK_8821C)\n#define BIT_SET_XTAL_SEL_TOK_8821C(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_SEL_TOK_8821C(x) | BIT_XTAL_SEL_TOK_8821C(v))\n\n/* 2 REG_USB_SIE_INTF_8821C */\n#define BIT_RD_SEL_8821C BIT(31)\n#define BIT_USB_SIE_INTF_WE_V1_8821C BIT(30)\n#define BIT_USB_SIE_INTF_BYIOREG_V1_8821C BIT(29)\n#define BIT_USB_SIE_SELECT_8821C BIT(28)\n\n#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C 16\n#define BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C 0x1ff\n#define BIT_USB_SIE_INTF_ADDR_V1_8821C(x)                                      \\\n\t(((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C)                           \\\n\t << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C)\n#define BITS_USB_SIE_INTF_ADDR_V1_8821C                                        \\\n\t(BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C                                   \\\n\t << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C)\n#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8821C(x)                                \\\n\t((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8821C))\n#define BIT_GET_USB_SIE_INTF_ADDR_V1_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C) &                       \\\n\t BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C)\n#define BIT_SET_USB_SIE_INTF_ADDR_V1_8821C(x, v)                               \\\n\t(BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8821C(x) |                             \\\n\t BIT_USB_SIE_INTF_ADDR_V1_8821C(v))\n\n#define BIT_SHIFT_USB_SIE_INTF_RD_8821C 8\n#define BIT_MASK_USB_SIE_INTF_RD_8821C 0xff\n#define BIT_USB_SIE_INTF_RD_8821C(x)                                           \\\n\t(((x) & BIT_MASK_USB_SIE_INTF_RD_8821C)                                \\\n\t << BIT_SHIFT_USB_SIE_INTF_RD_8821C)\n#define BITS_USB_SIE_INTF_RD_8821C                                             \\\n\t(BIT_MASK_USB_SIE_INTF_RD_8821C << BIT_SHIFT_USB_SIE_INTF_RD_8821C)\n#define BIT_CLEAR_USB_SIE_INTF_RD_8821C(x) ((x) & (~BITS_USB_SIE_INTF_RD_8821C))\n#define BIT_GET_USB_SIE_INTF_RD_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8821C) &                            \\\n\t BIT_MASK_USB_SIE_INTF_RD_8821C)\n#define BIT_SET_USB_SIE_INTF_RD_8821C(x, v)                                    \\\n\t(BIT_CLEAR_USB_SIE_INTF_RD_8821C(x) | BIT_USB_SIE_INTF_RD_8821C(v))\n\n#define BIT_SHIFT_USB_SIE_INTF_WD_8821C 0\n#define BIT_MASK_USB_SIE_INTF_WD_8821C 0xff\n#define BIT_USB_SIE_INTF_WD_8821C(x)                                           \\\n\t(((x) & BIT_MASK_USB_SIE_INTF_WD_8821C)                                \\\n\t << BIT_SHIFT_USB_SIE_INTF_WD_8821C)\n#define BITS_USB_SIE_INTF_WD_8821C                                             \\\n\t(BIT_MASK_USB_SIE_INTF_WD_8821C << BIT_SHIFT_USB_SIE_INTF_WD_8821C)\n#define BIT_CLEAR_USB_SIE_INTF_WD_8821C(x) ((x) & (~BITS_USB_SIE_INTF_WD_8821C))\n#define BIT_GET_USB_SIE_INTF_WD_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8821C) &                            \\\n\t BIT_MASK_USB_SIE_INTF_WD_8821C)\n#define BIT_SET_USB_SIE_INTF_WD_8821C(x, v)                                    \\\n\t(BIT_CLEAR_USB_SIE_INTF_WD_8821C(x) | BIT_USB_SIE_INTF_WD_8821C(v))\n\n/* 2 REG_PCIE_MIO_INTF_8821C */\n\n#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C 16\n#define BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C 0x3\n#define BIT_PCIE_MIO_ADDR_PAGE_8821C(x)                                        \\\n\t(((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C)                             \\\n\t << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C)\n#define BITS_PCIE_MIO_ADDR_PAGE_8821C                                          \\\n\t(BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C                                     \\\n\t << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C)\n#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8821C(x)                                  \\\n\t((x) & (~BITS_PCIE_MIO_ADDR_PAGE_8821C))\n#define BIT_GET_PCIE_MIO_ADDR_PAGE_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C) &                         \\\n\t BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C)\n#define BIT_SET_PCIE_MIO_ADDR_PAGE_8821C(x, v)                                 \\\n\t(BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8821C(x) |                               \\\n\t BIT_PCIE_MIO_ADDR_PAGE_8821C(v))\n\n#define BIT_PCIE_MIO_BYIOREG_8821C BIT(13)\n#define BIT_PCIE_MIO_RE_8821C BIT(12)\n\n#define BIT_SHIFT_PCIE_MIO_WE_8821C 8\n#define BIT_MASK_PCIE_MIO_WE_8821C 0xf\n#define BIT_PCIE_MIO_WE_8821C(x)                                               \\\n\t(((x) & BIT_MASK_PCIE_MIO_WE_8821C) << BIT_SHIFT_PCIE_MIO_WE_8821C)\n#define BITS_PCIE_MIO_WE_8821C                                                 \\\n\t(BIT_MASK_PCIE_MIO_WE_8821C << BIT_SHIFT_PCIE_MIO_WE_8821C)\n#define BIT_CLEAR_PCIE_MIO_WE_8821C(x) ((x) & (~BITS_PCIE_MIO_WE_8821C))\n#define BIT_GET_PCIE_MIO_WE_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_WE_8821C) & BIT_MASK_PCIE_MIO_WE_8821C)\n#define BIT_SET_PCIE_MIO_WE_8821C(x, v)                                        \\\n\t(BIT_CLEAR_PCIE_MIO_WE_8821C(x) | BIT_PCIE_MIO_WE_8821C(v))\n\n#define BIT_SHIFT_PCIE_MIO_ADDR_8821C 0\n#define BIT_MASK_PCIE_MIO_ADDR_8821C 0xff\n#define BIT_PCIE_MIO_ADDR_8821C(x)                                             \\\n\t(((x) & BIT_MASK_PCIE_MIO_ADDR_8821C) << BIT_SHIFT_PCIE_MIO_ADDR_8821C)\n#define BITS_PCIE_MIO_ADDR_8821C                                               \\\n\t(BIT_MASK_PCIE_MIO_ADDR_8821C << BIT_SHIFT_PCIE_MIO_ADDR_8821C)\n#define BIT_CLEAR_PCIE_MIO_ADDR_8821C(x) ((x) & (~BITS_PCIE_MIO_ADDR_8821C))\n#define BIT_GET_PCIE_MIO_ADDR_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8821C) & BIT_MASK_PCIE_MIO_ADDR_8821C)\n#define BIT_SET_PCIE_MIO_ADDR_8821C(x, v)                                      \\\n\t(BIT_CLEAR_PCIE_MIO_ADDR_8821C(x) | BIT_PCIE_MIO_ADDR_8821C(v))\n\n/* 2 REG_PCIE_MIO_INTD_8821C */\n\n#define BIT_SHIFT_PCIE_MIO_DATA_8821C 0\n#define BIT_MASK_PCIE_MIO_DATA_8821C 0xffffffffL\n#define BIT_PCIE_MIO_DATA_8821C(x)                                             \\\n\t(((x) & BIT_MASK_PCIE_MIO_DATA_8821C) << BIT_SHIFT_PCIE_MIO_DATA_8821C)\n#define BITS_PCIE_MIO_DATA_8821C                                               \\\n\t(BIT_MASK_PCIE_MIO_DATA_8821C << BIT_SHIFT_PCIE_MIO_DATA_8821C)\n#define BIT_CLEAR_PCIE_MIO_DATA_8821C(x) ((x) & (~BITS_PCIE_MIO_DATA_8821C))\n#define BIT_GET_PCIE_MIO_DATA_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_DATA_8821C) & BIT_MASK_PCIE_MIO_DATA_8821C)\n#define BIT_SET_PCIE_MIO_DATA_8821C(x, v)                                      \\\n\t(BIT_CLEAR_PCIE_MIO_DATA_8821C(x) | BIT_PCIE_MIO_DATA_8821C(v))\n\n/* 2 REG_WLRF1_8821C */\n\n#define BIT_SHIFT_WLRF1_CTRL_8821C 24\n#define BIT_MASK_WLRF1_CTRL_8821C 0xff\n#define BIT_WLRF1_CTRL_8821C(x)                                                \\\n\t(((x) & BIT_MASK_WLRF1_CTRL_8821C) << BIT_SHIFT_WLRF1_CTRL_8821C)\n#define BITS_WLRF1_CTRL_8821C                                                  \\\n\t(BIT_MASK_WLRF1_CTRL_8821C << BIT_SHIFT_WLRF1_CTRL_8821C)\n#define BIT_CLEAR_WLRF1_CTRL_8821C(x) ((x) & (~BITS_WLRF1_CTRL_8821C))\n#define BIT_GET_WLRF1_CTRL_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_WLRF1_CTRL_8821C) & BIT_MASK_WLRF1_CTRL_8821C)\n#define BIT_SET_WLRF1_CTRL_8821C(x, v)                                         \\\n\t(BIT_CLEAR_WLRF1_CTRL_8821C(x) | BIT_WLRF1_CTRL_8821C(v))\n\n/* 2 REG_SYS_CFG1_8821C */\n\n#define BIT_SHIFT_TRP_ICFG_8821C 28\n#define BIT_MASK_TRP_ICFG_8821C 0xf\n#define BIT_TRP_ICFG_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_TRP_ICFG_8821C) << BIT_SHIFT_TRP_ICFG_8821C)\n#define BITS_TRP_ICFG_8821C                                                    \\\n\t(BIT_MASK_TRP_ICFG_8821C << BIT_SHIFT_TRP_ICFG_8821C)\n#define BIT_CLEAR_TRP_ICFG_8821C(x) ((x) & (~BITS_TRP_ICFG_8821C))\n#define BIT_GET_TRP_ICFG_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TRP_ICFG_8821C) & BIT_MASK_TRP_ICFG_8821C)\n#define BIT_SET_TRP_ICFG_8821C(x, v)                                           \\\n\t(BIT_CLEAR_TRP_ICFG_8821C(x) | BIT_TRP_ICFG_8821C(v))\n\n#define BIT_RF_TYPE_ID_8821C BIT(27)\n#define BIT_BD_HCI_SEL_8821C BIT(26)\n#define BIT_BD_PKG_SEL_8821C BIT(25)\n#define BIT_SPSLDO_SEL_8821C BIT(24)\n#define BIT_RTL_ID_8821C BIT(23)\n#define BIT_PAD_HWPD_IDN_8821C BIT(22)\n#define BIT_TESTMODE_8821C BIT(20)\n\n#define BIT_SHIFT_VENDOR_ID_8821C 16\n#define BIT_MASK_VENDOR_ID_8821C 0xf\n#define BIT_VENDOR_ID_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_VENDOR_ID_8821C) << BIT_SHIFT_VENDOR_ID_8821C)\n#define BITS_VENDOR_ID_8821C                                                   \\\n\t(BIT_MASK_VENDOR_ID_8821C << BIT_SHIFT_VENDOR_ID_8821C)\n#define BIT_CLEAR_VENDOR_ID_8821C(x) ((x) & (~BITS_VENDOR_ID_8821C))\n#define BIT_GET_VENDOR_ID_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_VENDOR_ID_8821C) & BIT_MASK_VENDOR_ID_8821C)\n#define BIT_SET_VENDOR_ID_8821C(x, v)                                          \\\n\t(BIT_CLEAR_VENDOR_ID_8821C(x) | BIT_VENDOR_ID_8821C(v))\n\n#define BIT_SHIFT_CHIP_VER_8821C 12\n#define BIT_MASK_CHIP_VER_8821C 0xf\n#define BIT_CHIP_VER_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_CHIP_VER_8821C) << BIT_SHIFT_CHIP_VER_8821C)\n#define BITS_CHIP_VER_8821C                                                    \\\n\t(BIT_MASK_CHIP_VER_8821C << BIT_SHIFT_CHIP_VER_8821C)\n#define BIT_CLEAR_CHIP_VER_8821C(x) ((x) & (~BITS_CHIP_VER_8821C))\n#define BIT_GET_CHIP_VER_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_CHIP_VER_8821C) & BIT_MASK_CHIP_VER_8821C)\n#define BIT_SET_CHIP_VER_8821C(x, v)                                           \\\n\t(BIT_CLEAR_CHIP_VER_8821C(x) | BIT_CHIP_VER_8821C(v))\n\n#define BIT_BD_MAC3_8821C BIT(11)\n#define BIT_BD_MAC1_8821C BIT(10)\n#define BIT_BD_MAC2_8821C BIT(9)\n#define BIT_SIC_IDLE_8821C BIT(8)\n#define BIT_SW_OFFLOAD_EN_8821C BIT(7)\n#define BIT_OCP_SHUTDN_8821C BIT(6)\n#define BIT_V15_VLD_8821C BIT(5)\n#define BIT_PCIRSTB_8821C BIT(4)\n#define BIT_PCLK_VLD_8821C BIT(3)\n#define BIT_UCLK_VLD_8821C BIT(2)\n#define BIT_ACLK_VLD_8821C BIT(1)\n#define BIT_XCLK_VLD_8821C BIT(0)\n\n/* 2 REG_SYS_STATUS1_8821C */\n\n#define BIT_SHIFT_RF_RL_ID_8821C 28\n#define BIT_MASK_RF_RL_ID_8821C 0xf\n#define BIT_RF_RL_ID_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_RF_RL_ID_8821C) << BIT_SHIFT_RF_RL_ID_8821C)\n#define BITS_RF_RL_ID_8821C                                                    \\\n\t(BIT_MASK_RF_RL_ID_8821C << BIT_SHIFT_RF_RL_ID_8821C)\n#define BIT_CLEAR_RF_RL_ID_8821C(x) ((x) & (~BITS_RF_RL_ID_8821C))\n#define BIT_GET_RF_RL_ID_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RF_RL_ID_8821C) & BIT_MASK_RF_RL_ID_8821C)\n#define BIT_SET_RF_RL_ID_8821C(x, v)                                           \\\n\t(BIT_CLEAR_RF_RL_ID_8821C(x) | BIT_RF_RL_ID_8821C(v))\n\n#define BIT_HPHY_ICFG_8821C BIT(19)\n\n#define BIT_SHIFT_SEL_0XC0_8821C 16\n#define BIT_MASK_SEL_0XC0_8821C 0x3\n#define BIT_SEL_0XC0_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_SEL_0XC0_8821C) << BIT_SHIFT_SEL_0XC0_8821C)\n#define BITS_SEL_0XC0_8821C                                                    \\\n\t(BIT_MASK_SEL_0XC0_8821C << BIT_SHIFT_SEL_0XC0_8821C)\n#define BIT_CLEAR_SEL_0XC0_8821C(x) ((x) & (~BITS_SEL_0XC0_8821C))\n#define BIT_GET_SEL_0XC0_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_SEL_0XC0_8821C) & BIT_MASK_SEL_0XC0_8821C)\n#define BIT_SET_SEL_0XC0_8821C(x, v)                                           \\\n\t(BIT_CLEAR_SEL_0XC0_8821C(x) | BIT_SEL_0XC0_8821C(v))\n\n#define BIT_SHIFT_HCI_SEL_V4_8821C 12\n#define BIT_MASK_HCI_SEL_V4_8821C 0x3\n#define BIT_HCI_SEL_V4_8821C(x)                                                \\\n\t(((x) & BIT_MASK_HCI_SEL_V4_8821C) << BIT_SHIFT_HCI_SEL_V4_8821C)\n#define BITS_HCI_SEL_V4_8821C                                                  \\\n\t(BIT_MASK_HCI_SEL_V4_8821C << BIT_SHIFT_HCI_SEL_V4_8821C)\n#define BIT_CLEAR_HCI_SEL_V4_8821C(x) ((x) & (~BITS_HCI_SEL_V4_8821C))\n#define BIT_GET_HCI_SEL_V4_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_HCI_SEL_V4_8821C) & BIT_MASK_HCI_SEL_V4_8821C)\n#define BIT_SET_HCI_SEL_V4_8821C(x, v)                                         \\\n\t(BIT_CLEAR_HCI_SEL_V4_8821C(x) | BIT_HCI_SEL_V4_8821C(v))\n\n#define BIT_USB_OPERATION_MODE_8821C BIT(10)\n#define BIT_BT_PDN_8821C BIT(9)\n#define BIT_AUTO_WLPON_8821C BIT(8)\n#define BIT_WL_MODE_8821C BIT(7)\n#define BIT_PKG_SEL_HCI_8821C BIT(6)\n\n#define BIT_SHIFT_PAD_HCI_SEL_V2_8821C 3\n#define BIT_MASK_PAD_HCI_SEL_V2_8821C 0x3\n#define BIT_PAD_HCI_SEL_V2_8821C(x)                                            \\\n\t(((x) & BIT_MASK_PAD_HCI_SEL_V2_8821C)                                 \\\n\t << BIT_SHIFT_PAD_HCI_SEL_V2_8821C)\n#define BITS_PAD_HCI_SEL_V2_8821C                                              \\\n\t(BIT_MASK_PAD_HCI_SEL_V2_8821C << BIT_SHIFT_PAD_HCI_SEL_V2_8821C)\n#define BIT_CLEAR_PAD_HCI_SEL_V2_8821C(x) ((x) & (~BITS_PAD_HCI_SEL_V2_8821C))\n#define BIT_GET_PAD_HCI_SEL_V2_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_PAD_HCI_SEL_V2_8821C) &                             \\\n\t BIT_MASK_PAD_HCI_SEL_V2_8821C)\n#define BIT_SET_PAD_HCI_SEL_V2_8821C(x, v)                                     \\\n\t(BIT_CLEAR_PAD_HCI_SEL_V2_8821C(x) | BIT_PAD_HCI_SEL_V2_8821C(v))\n\n#define BIT_SHIFT_EFS_HCI_SEL_8821C 0\n#define BIT_MASK_EFS_HCI_SEL_8821C 0x3\n#define BIT_EFS_HCI_SEL_8821C(x)                                               \\\n\t(((x) & BIT_MASK_EFS_HCI_SEL_8821C) << BIT_SHIFT_EFS_HCI_SEL_8821C)\n#define BITS_EFS_HCI_SEL_8821C                                                 \\\n\t(BIT_MASK_EFS_HCI_SEL_8821C << BIT_SHIFT_EFS_HCI_SEL_8821C)\n#define BIT_CLEAR_EFS_HCI_SEL_8821C(x) ((x) & (~BITS_EFS_HCI_SEL_8821C))\n#define BIT_GET_EFS_HCI_SEL_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_EFS_HCI_SEL_8821C) & BIT_MASK_EFS_HCI_SEL_8821C)\n#define BIT_SET_EFS_HCI_SEL_8821C(x, v)                                        \\\n\t(BIT_CLEAR_EFS_HCI_SEL_8821C(x) | BIT_EFS_HCI_SEL_8821C(v))\n\n/* 2 REG_SYS_STATUS2_8821C */\n#define BIT_SIO_ALDN_8821C BIT(19)\n#define BIT_USB_ALDN_8821C BIT(18)\n#define BIT_PCI_ALDN_8821C BIT(17)\n#define BIT_SYS_ALDN_8821C BIT(16)\n\n#define BIT_SHIFT_EPVID1_8821C 8\n#define BIT_MASK_EPVID1_8821C 0xff\n#define BIT_EPVID1_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_EPVID1_8821C) << BIT_SHIFT_EPVID1_8821C)\n#define BITS_EPVID1_8821C (BIT_MASK_EPVID1_8821C << BIT_SHIFT_EPVID1_8821C)\n#define BIT_CLEAR_EPVID1_8821C(x) ((x) & (~BITS_EPVID1_8821C))\n#define BIT_GET_EPVID1_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_EPVID1_8821C) & BIT_MASK_EPVID1_8821C)\n#define BIT_SET_EPVID1_8821C(x, v)                                             \\\n\t(BIT_CLEAR_EPVID1_8821C(x) | BIT_EPVID1_8821C(v))\n\n#define BIT_SHIFT_EPVID0_8821C 0\n#define BIT_MASK_EPVID0_8821C 0xff\n#define BIT_EPVID0_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_EPVID0_8821C) << BIT_SHIFT_EPVID0_8821C)\n#define BITS_EPVID0_8821C (BIT_MASK_EPVID0_8821C << BIT_SHIFT_EPVID0_8821C)\n#define BIT_CLEAR_EPVID0_8821C(x) ((x) & (~BITS_EPVID0_8821C))\n#define BIT_GET_EPVID0_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_EPVID0_8821C) & BIT_MASK_EPVID0_8821C)\n#define BIT_SET_EPVID0_8821C(x, v)                                             \\\n\t(BIT_CLEAR_EPVID0_8821C(x) | BIT_EPVID0_8821C(v))\n\n/* 2 REG_SYS_CFG2_8821C */\n#define BIT_HCI_SEL_EMBEDDED_8821C BIT(8)\n\n#define BIT_SHIFT_HW_ID_8821C 0\n#define BIT_MASK_HW_ID_8821C 0xff\n#define BIT_HW_ID_8821C(x)                                                     \\\n\t(((x) & BIT_MASK_HW_ID_8821C) << BIT_SHIFT_HW_ID_8821C)\n#define BITS_HW_ID_8821C (BIT_MASK_HW_ID_8821C << BIT_SHIFT_HW_ID_8821C)\n#define BIT_CLEAR_HW_ID_8821C(x) ((x) & (~BITS_HW_ID_8821C))\n#define BIT_GET_HW_ID_8821C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HW_ID_8821C) & BIT_MASK_HW_ID_8821C)\n#define BIT_SET_HW_ID_8821C(x, v)                                              \\\n\t(BIT_CLEAR_HW_ID_8821C(x) | BIT_HW_ID_8821C(v))\n\n/* 2 REG_SYS_CFG3_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_SYS_CFG5_8821C */\n#define BIT_LPS_STATUS_8821C BIT(3)\n#define BIT_HCI_TXDMA_BUSY_8821C BIT(2)\n#define BIT_HCI_TXDMA_ALLOW_8821C BIT(1)\n#define BIT_FW_CTRL_HCI_TXDMA_EN_8821C BIT(0)\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_CPU_DMEM_CON_8821C */\n#define BIT_WDT_AUTO_MODE_8821C BIT(22)\n#define BIT_WDT_PLATFORM_EN_8821C BIT(21)\n#define BIT_WDT_CPU_EN_8821C BIT(20)\n#define BIT_WDT_OPT_IOWRAPPER_8821C BIT(19)\n#define BIT_ANA_PORT_IDLE_8821C BIT(18)\n#define BIT_MAC_PORT_IDLE_8821C BIT(17)\n#define BIT_WL_PLATFORM_RST_8821C BIT(16)\n#define BIT_WL_SECURITY_CLK_8821C BIT(15)\n\n#define BIT_SHIFT_CPU_DMEM_CON_8821C 0\n#define BIT_MASK_CPU_DMEM_CON_8821C 0xff\n#define BIT_CPU_DMEM_CON_8821C(x)                                              \\\n\t(((x) & BIT_MASK_CPU_DMEM_CON_8821C) << BIT_SHIFT_CPU_DMEM_CON_8821C)\n#define BITS_CPU_DMEM_CON_8821C                                                \\\n\t(BIT_MASK_CPU_DMEM_CON_8821C << BIT_SHIFT_CPU_DMEM_CON_8821C)\n#define BIT_CLEAR_CPU_DMEM_CON_8821C(x) ((x) & (~BITS_CPU_DMEM_CON_8821C))\n#define BIT_GET_CPU_DMEM_CON_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_CPU_DMEM_CON_8821C) & BIT_MASK_CPU_DMEM_CON_8821C)\n#define BIT_SET_CPU_DMEM_CON_8821C(x, v)                                       \\\n\t(BIT_CLEAR_CPU_DMEM_CON_8821C(x) | BIT_CPU_DMEM_CON_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_BOOT_REASON_8821C */\n\n#define BIT_SHIFT_BOOT_REASON_V1_8821C 0\n#define BIT_MASK_BOOT_REASON_V1_8821C 0x7\n#define BIT_BOOT_REASON_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_BOOT_REASON_V1_8821C)                                 \\\n\t << BIT_SHIFT_BOOT_REASON_V1_8821C)\n#define BITS_BOOT_REASON_V1_8821C                                              \\\n\t(BIT_MASK_BOOT_REASON_V1_8821C << BIT_SHIFT_BOOT_REASON_V1_8821C)\n#define BIT_CLEAR_BOOT_REASON_V1_8821C(x) ((x) & (~BITS_BOOT_REASON_V1_8821C))\n#define BIT_GET_BOOT_REASON_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_BOOT_REASON_V1_8821C) &                             \\\n\t BIT_MASK_BOOT_REASON_V1_8821C)\n#define BIT_SET_BOOT_REASON_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_BOOT_REASON_V1_8821C(x) | BIT_BOOT_REASON_V1_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NFCPAD_CTRL_8821C */\n#define BIT_PAD_SHUTDW_8821C BIT(18)\n#define BIT_SYSON_NFC_PAD_8821C BIT(17)\n#define BIT_NFC_INT_PAD_CTRL_8821C BIT(16)\n#define BIT_NFC_RFDIS_PAD_CTRL_8821C BIT(15)\n#define BIT_NFC_CLK_PAD_CTRL_8821C BIT(14)\n#define BIT_NFC_DATA_PAD_CTRL_8821C BIT(13)\n#define BIT_NFC_PAD_PULL_CTRL_8821C BIT(12)\n\n#define BIT_SHIFT_NFCPAD_IO_SEL_8821C 8\n#define BIT_MASK_NFCPAD_IO_SEL_8821C 0xf\n#define BIT_NFCPAD_IO_SEL_8821C(x)                                             \\\n\t(((x) & BIT_MASK_NFCPAD_IO_SEL_8821C) << BIT_SHIFT_NFCPAD_IO_SEL_8821C)\n#define BITS_NFCPAD_IO_SEL_8821C                                               \\\n\t(BIT_MASK_NFCPAD_IO_SEL_8821C << BIT_SHIFT_NFCPAD_IO_SEL_8821C)\n#define BIT_CLEAR_NFCPAD_IO_SEL_8821C(x) ((x) & (~BITS_NFCPAD_IO_SEL_8821C))\n#define BIT_GET_NFCPAD_IO_SEL_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8821C) & BIT_MASK_NFCPAD_IO_SEL_8821C)\n#define BIT_SET_NFCPAD_IO_SEL_8821C(x, v)                                      \\\n\t(BIT_CLEAR_NFCPAD_IO_SEL_8821C(x) | BIT_NFCPAD_IO_SEL_8821C(v))\n\n#define BIT_SHIFT_NFCPAD_OUT_8821C 4\n#define BIT_MASK_NFCPAD_OUT_8821C 0xf\n#define BIT_NFCPAD_OUT_8821C(x)                                                \\\n\t(((x) & BIT_MASK_NFCPAD_OUT_8821C) << BIT_SHIFT_NFCPAD_OUT_8821C)\n#define BITS_NFCPAD_OUT_8821C                                                  \\\n\t(BIT_MASK_NFCPAD_OUT_8821C << BIT_SHIFT_NFCPAD_OUT_8821C)\n#define BIT_CLEAR_NFCPAD_OUT_8821C(x) ((x) & (~BITS_NFCPAD_OUT_8821C))\n#define BIT_GET_NFCPAD_OUT_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_NFCPAD_OUT_8821C) & BIT_MASK_NFCPAD_OUT_8821C)\n#define BIT_SET_NFCPAD_OUT_8821C(x, v)                                         \\\n\t(BIT_CLEAR_NFCPAD_OUT_8821C(x) | BIT_NFCPAD_OUT_8821C(v))\n\n#define BIT_SHIFT_NFCPAD_IN_8821C 0\n#define BIT_MASK_NFCPAD_IN_8821C 0xf\n#define BIT_NFCPAD_IN_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_NFCPAD_IN_8821C) << BIT_SHIFT_NFCPAD_IN_8821C)\n#define BITS_NFCPAD_IN_8821C                                                   \\\n\t(BIT_MASK_NFCPAD_IN_8821C << BIT_SHIFT_NFCPAD_IN_8821C)\n#define BIT_CLEAR_NFCPAD_IN_8821C(x) ((x) & (~BITS_NFCPAD_IN_8821C))\n#define BIT_GET_NFCPAD_IN_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_NFCPAD_IN_8821C) & BIT_MASK_NFCPAD_IN_8821C)\n#define BIT_SET_NFCPAD_IN_8821C(x, v)                                          \\\n\t(BIT_CLEAR_NFCPAD_IN_8821C(x) | BIT_NFCPAD_IN_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_HIMR2_8821C */\n#define BIT_BCNDMAINT_P4_MSK_8821C BIT(31)\n#define BIT_BCNDMAINT_P3_MSK_8821C BIT(30)\n#define BIT_BCNDMAINT_P2_MSK_8821C BIT(29)\n#define BIT_BCNDMAINT_P1_MSK_8821C BIT(28)\n#define BIT_ATIMEND7_MSK_8821C BIT(22)\n#define BIT_ATIMEND6_MSK_8821C BIT(21)\n#define BIT_ATIMEND5_MSK_8821C BIT(20)\n#define BIT_ATIMEND4_MSK_8821C BIT(19)\n#define BIT_ATIMEND3_MSK_8821C BIT(18)\n#define BIT_ATIMEND2_MSK_8821C BIT(17)\n#define BIT_ATIMEND1_MSK_8821C BIT(16)\n#define BIT_TXBCN7OK_MSK_8821C BIT(14)\n#define BIT_TXBCN6OK_MSK_8821C BIT(13)\n#define BIT_TXBCN5OK_MSK_8821C BIT(12)\n#define BIT_TXBCN4OK_MSK_8821C BIT(11)\n#define BIT_TXBCN3OK_MSK_8821C BIT(10)\n#define BIT_TXBCN2OK_MSK_8821C BIT(9)\n#define BIT_TXBCN1OK_MSK_V1_8821C BIT(8)\n#define BIT_TXBCN7ERR_MSK_8821C BIT(6)\n#define BIT_TXBCN6ERR_MSK_8821C BIT(5)\n#define BIT_TXBCN5ERR_MSK_8821C BIT(4)\n#define BIT_TXBCN4ERR_MSK_8821C BIT(3)\n#define BIT_TXBCN3ERR_MSK_8821C BIT(2)\n#define BIT_TXBCN2ERR_MSK_8821C BIT(1)\n#define BIT_TXBCN1ERR_MSK_V1_8821C BIT(0)\n\n/* 2 REG_HISR2_8821C */\n#define BIT_BCNDMAINT_P4_8821C BIT(31)\n#define BIT_BCNDMAINT_P3_8821C BIT(30)\n#define BIT_BCNDMAINT_P2_8821C BIT(29)\n#define BIT_BCNDMAINT_P1_8821C BIT(28)\n#define BIT_ATIMEND7_8821C BIT(22)\n#define BIT_ATIMEND6_8821C BIT(21)\n#define BIT_ATIMEND5_8821C BIT(20)\n#define BIT_ATIMEND4_8821C BIT(19)\n#define BIT_ATIMEND3_8821C BIT(18)\n#define BIT_ATIMEND2_8821C BIT(17)\n#define BIT_ATIMEND1_8821C BIT(16)\n#define BIT_TXBCN7OK_8821C BIT(14)\n#define BIT_TXBCN6OK_8821C BIT(13)\n#define BIT_TXBCN5OK_8821C BIT(12)\n#define BIT_TXBCN4OK_8821C BIT(11)\n#define BIT_TXBCN3OK_8821C BIT(10)\n#define BIT_TXBCN2OK_8821C BIT(9)\n#define BIT_TXBCN1OK_8821C BIT(8)\n#define BIT_TXBCN7ERR_8821C BIT(6)\n#define BIT_TXBCN6ERR_8821C BIT(5)\n#define BIT_TXBCN5ERR_8821C BIT(4)\n#define BIT_TXBCN4ERR_8821C BIT(3)\n#define BIT_TXBCN3ERR_8821C BIT(2)\n#define BIT_TXBCN2ERR_8821C BIT(1)\n#define BIT_TXBCN1ERR_8821C BIT(0)\n\n/* 2 REG_HIMR3_8821C */\n#define BIT_WDT_PLATFORM_INT_MSK_8821C BIT(18)\n#define BIT_WDT_CPU_INT_MSK_8821C BIT(17)\n#define BIT_SETH2CDOK_MASK_8821C BIT(16)\n#define BIT_H2C_CMD_FULL_MASK_8821C BIT(15)\n#define BIT_PWR_INT_127_MASK_8821C BIT(14)\n#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8821C BIT(13)\n#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8821C BIT(12)\n#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8821C BIT(11)\n#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8821C BIT(10)\n#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8821C BIT(9)\n#define BIT_PWR_INT_127_MASK_V1_8821C BIT(8)\n#define BIT_PWR_INT_126TO96_MASK_8821C BIT(7)\n#define BIT_PWR_INT_95TO64_MASK_8821C BIT(6)\n#define BIT_PWR_INT_63TO32_MASK_8821C BIT(5)\n#define BIT_PWR_INT_31TO0_MASK_8821C BIT(4)\n#define BIT_DDMA0_LP_INT_MSK_8821C BIT(1)\n#define BIT_DDMA0_HP_INT_MSK_8821C BIT(0)\n\n/* 2 REG_HISR3_8821C */\n#define BIT_WDT_PLATFORM_INT_8821C BIT(18)\n#define BIT_WDT_CPU_INT_8821C BIT(17)\n#define BIT_SETH2CDOK_8821C BIT(16)\n#define BIT_H2C_CMD_FULL_8821C BIT(15)\n#define BIT_PWR_INT_127_8821C BIT(14)\n#define BIT_TXSHORTCUT_TXDESUPDATEOK_8821C BIT(13)\n#define BIT_TXSHORTCUT_BKUPDATEOK_8821C BIT(12)\n#define BIT_TXSHORTCUT_BEUPDATEOK_8821C BIT(11)\n#define BIT_TXSHORTCUT_VIUPDATEOK_8821C BIT(10)\n#define BIT_TXSHORTCUT_VOUPDATEOK_8821C BIT(9)\n#define BIT_PWR_INT_127_V1_8821C BIT(8)\n#define BIT_PWR_INT_126TO96_8821C BIT(7)\n#define BIT_PWR_INT_95TO64_8821C BIT(6)\n#define BIT_PWR_INT_63TO32_8821C BIT(5)\n#define BIT_PWR_INT_31TO0_8821C BIT(4)\n#define BIT_DDMA0_LP_INT_8821C BIT(1)\n#define BIT_DDMA0_HP_INT_8821C BIT(0)\n\n/* 2 REG_SW_MDIO_8821C */\n#define BIT_DIS_TIMEOUT_IO_8821C BIT(24)\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_H2C_PKT_READADDR_8821C */\n\n#define BIT_SHIFT_H2C_PKT_READADDR_8821C 0\n#define BIT_MASK_H2C_PKT_READADDR_8821C 0x3ffff\n#define BIT_H2C_PKT_READADDR_8821C(x)                                          \\\n\t(((x) & BIT_MASK_H2C_PKT_READADDR_8821C)                               \\\n\t << BIT_SHIFT_H2C_PKT_READADDR_8821C)\n#define BITS_H2C_PKT_READADDR_8821C                                            \\\n\t(BIT_MASK_H2C_PKT_READADDR_8821C << BIT_SHIFT_H2C_PKT_READADDR_8821C)\n#define BIT_CLEAR_H2C_PKT_READADDR_8821C(x)                                    \\\n\t((x) & (~BITS_H2C_PKT_READADDR_8821C))\n#define BIT_GET_H2C_PKT_READADDR_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_H2C_PKT_READADDR_8821C) &                           \\\n\t BIT_MASK_H2C_PKT_READADDR_8821C)\n#define BIT_SET_H2C_PKT_READADDR_8821C(x, v)                                   \\\n\t(BIT_CLEAR_H2C_PKT_READADDR_8821C(x) | BIT_H2C_PKT_READADDR_8821C(v))\n\n/* 2 REG_H2C_PKT_WRITEADDR_8821C */\n\n#define BIT_SHIFT_H2C_PKT_WRITEADDR_8821C 0\n#define BIT_MASK_H2C_PKT_WRITEADDR_8821C 0x3ffff\n#define BIT_H2C_PKT_WRITEADDR_8821C(x)                                         \\\n\t(((x) & BIT_MASK_H2C_PKT_WRITEADDR_8821C)                              \\\n\t << BIT_SHIFT_H2C_PKT_WRITEADDR_8821C)\n#define BITS_H2C_PKT_WRITEADDR_8821C                                           \\\n\t(BIT_MASK_H2C_PKT_WRITEADDR_8821C << BIT_SHIFT_H2C_PKT_WRITEADDR_8821C)\n#define BIT_CLEAR_H2C_PKT_WRITEADDR_8821C(x)                                   \\\n\t((x) & (~BITS_H2C_PKT_WRITEADDR_8821C))\n#define BIT_GET_H2C_PKT_WRITEADDR_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8821C) &                          \\\n\t BIT_MASK_H2C_PKT_WRITEADDR_8821C)\n#define BIT_SET_H2C_PKT_WRITEADDR_8821C(x, v)                                  \\\n\t(BIT_CLEAR_H2C_PKT_WRITEADDR_8821C(x) | BIT_H2C_PKT_WRITEADDR_8821C(v))\n\n/* 2 REG_MEM_PWR_CRTL_8821C */\n#define BIT_MEM_BB_SD_8821C BIT(17)\n#define BIT_MEM_BB_DS_8821C BIT(16)\n#define BIT_MEM_BT_DS_8821C BIT(10)\n#define BIT_MEM_SDIO_LS_8821C BIT(9)\n#define BIT_MEM_SDIO_DS_8821C BIT(8)\n#define BIT_MEM_USB_LS_8821C BIT(7)\n#define BIT_MEM_USB_DS_8821C BIT(6)\n#define BIT_MEM_PCI_LS_8821C BIT(5)\n#define BIT_MEM_PCI_DS_8821C BIT(4)\n#define BIT_MEM_WLMAC_LS_8821C BIT(3)\n#define BIT_MEM_WLMAC_DS_8821C BIT(2)\n#define BIT_MEM_WLMCU_LS_8821C BIT(1)\n#define BIT_MEM_WLMCU_DS_8821C BIT(0)\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_FW_DBG6_8821C */\n\n#define BIT_SHIFT_FW_DBG6_8821C 0\n#define BIT_MASK_FW_DBG6_8821C 0xffffffffL\n#define BIT_FW_DBG6_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG6_8821C) << BIT_SHIFT_FW_DBG6_8821C)\n#define BITS_FW_DBG6_8821C (BIT_MASK_FW_DBG6_8821C << BIT_SHIFT_FW_DBG6_8821C)\n#define BIT_CLEAR_FW_DBG6_8821C(x) ((x) & (~BITS_FW_DBG6_8821C))\n#define BIT_GET_FW_DBG6_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG6_8821C) & BIT_MASK_FW_DBG6_8821C)\n#define BIT_SET_FW_DBG6_8821C(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG6_8821C(x) | BIT_FW_DBG6_8821C(v))\n\n/* 2 REG_FW_DBG7_8821C */\n\n#define BIT_SHIFT_FW_DBG7_8821C 0\n#define BIT_MASK_FW_DBG7_8821C 0xffffffffL\n#define BIT_FW_DBG7_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG7_8821C) << BIT_SHIFT_FW_DBG7_8821C)\n#define BITS_FW_DBG7_8821C (BIT_MASK_FW_DBG7_8821C << BIT_SHIFT_FW_DBG7_8821C)\n#define BIT_CLEAR_FW_DBG7_8821C(x) ((x) & (~BITS_FW_DBG7_8821C))\n#define BIT_GET_FW_DBG7_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG7_8821C) & BIT_MASK_FW_DBG7_8821C)\n#define BIT_SET_FW_DBG7_8821C(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG7_8821C(x) | BIT_FW_DBG7_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_CR_8821C */\n\n#define BIT_SHIFT_LBMODE_8821C 24\n#define BIT_MASK_LBMODE_8821C 0x1f\n#define BIT_LBMODE_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_LBMODE_8821C) << BIT_SHIFT_LBMODE_8821C)\n#define BITS_LBMODE_8821C (BIT_MASK_LBMODE_8821C << BIT_SHIFT_LBMODE_8821C)\n#define BIT_CLEAR_LBMODE_8821C(x) ((x) & (~BITS_LBMODE_8821C))\n#define BIT_GET_LBMODE_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_LBMODE_8821C) & BIT_MASK_LBMODE_8821C)\n#define BIT_SET_LBMODE_8821C(x, v)                                             \\\n\t(BIT_CLEAR_LBMODE_8821C(x) | BIT_LBMODE_8821C(v))\n\n#define BIT_SHIFT_NETYPE1_8821C 18\n#define BIT_MASK_NETYPE1_8821C 0x3\n#define BIT_NETYPE1_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE1_8821C) << BIT_SHIFT_NETYPE1_8821C)\n#define BITS_NETYPE1_8821C (BIT_MASK_NETYPE1_8821C << BIT_SHIFT_NETYPE1_8821C)\n#define BIT_CLEAR_NETYPE1_8821C(x) ((x) & (~BITS_NETYPE1_8821C))\n#define BIT_GET_NETYPE1_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE1_8821C) & BIT_MASK_NETYPE1_8821C)\n#define BIT_SET_NETYPE1_8821C(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE1_8821C(x) | BIT_NETYPE1_8821C(v))\n\n#define BIT_SHIFT_NETYPE0_8821C 16\n#define BIT_MASK_NETYPE0_8821C 0x3\n#define BIT_NETYPE0_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE0_8821C) << BIT_SHIFT_NETYPE0_8821C)\n#define BITS_NETYPE0_8821C (BIT_MASK_NETYPE0_8821C << BIT_SHIFT_NETYPE0_8821C)\n#define BIT_CLEAR_NETYPE0_8821C(x) ((x) & (~BITS_NETYPE0_8821C))\n#define BIT_GET_NETYPE0_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE0_8821C) & BIT_MASK_NETYPE0_8821C)\n#define BIT_SET_NETYPE0_8821C(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE0_8821C(x) | BIT_NETYPE0_8821C(v))\n\n#define BIT_COUNTER_STS_EN_8821C BIT(13)\n#define BIT_I2C_MAILBOX_EN_8821C BIT(12)\n#define BIT_SHCUT_EN_8821C BIT(11)\n#define BIT_32K_CAL_TMR_EN_8821C BIT(10)\n#define BIT_MAC_SEC_EN_8821C BIT(9)\n#define BIT_ENSWBCN_8821C BIT(8)\n#define BIT_MACRXEN_8821C BIT(7)\n#define BIT_MACTXEN_8821C BIT(6)\n#define BIT_SCHEDULE_EN_8821C BIT(5)\n#define BIT_PROTOCOL_EN_8821C BIT(4)\n#define BIT_RXDMA_EN_8821C BIT(3)\n#define BIT_TXDMA_EN_8821C BIT(2)\n#define BIT_HCI_RXDMA_EN_8821C BIT(1)\n#define BIT_HCI_TXDMA_EN_8821C BIT(0)\n\n/* 2 REG_PG_SIZE_8821C */\n\n#define BIT_SHIFT_DBG_FIFO_SEL_8821C 16\n#define BIT_MASK_DBG_FIFO_SEL_8821C 0xff\n#define BIT_DBG_FIFO_SEL_8821C(x)                                              \\\n\t(((x) & BIT_MASK_DBG_FIFO_SEL_8821C) << BIT_SHIFT_DBG_FIFO_SEL_8821C)\n#define BITS_DBG_FIFO_SEL_8821C                                                \\\n\t(BIT_MASK_DBG_FIFO_SEL_8821C << BIT_SHIFT_DBG_FIFO_SEL_8821C)\n#define BIT_CLEAR_DBG_FIFO_SEL_8821C(x) ((x) & (~BITS_DBG_FIFO_SEL_8821C))\n#define BIT_GET_DBG_FIFO_SEL_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DBG_FIFO_SEL_8821C) & BIT_MASK_DBG_FIFO_SEL_8821C)\n#define BIT_SET_DBG_FIFO_SEL_8821C(x, v)                                       \\\n\t(BIT_CLEAR_DBG_FIFO_SEL_8821C(x) | BIT_DBG_FIFO_SEL_8821C(v))\n\n/* 2 REG_PKT_BUFF_ACCESS_CTRL_8821C */\n\n#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C 0\n#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C 0xff\n#define BIT_PKT_BUFF_ACCESS_CTRL_8821C(x)                                      \\\n\t(((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C)                           \\\n\t << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C)\n#define BITS_PKT_BUFF_ACCESS_CTRL_8821C                                        \\\n\t(BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C                                   \\\n\t << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C)\n#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8821C(x)                                \\\n\t((x) & (~BITS_PKT_BUFF_ACCESS_CTRL_8821C))\n#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C) &                       \\\n\t BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C)\n#define BIT_SET_PKT_BUFF_ACCESS_CTRL_8821C(x, v)                               \\\n\t(BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8821C(x) |                             \\\n\t BIT_PKT_BUFF_ACCESS_CTRL_8821C(v))\n\n/* 2 REG_TSF_CLK_STATE_8821C */\n#define BIT_TSF_CLK_STABLE_8821C BIT(15)\n\n/* 2 REG_TXDMA_PQ_MAP_8821C */\n\n#define BIT_SHIFT_TXDMA_H2C_MAP_8821C 16\n#define BIT_MASK_TXDMA_H2C_MAP_8821C 0x3\n#define BIT_TXDMA_H2C_MAP_8821C(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_H2C_MAP_8821C) << BIT_SHIFT_TXDMA_H2C_MAP_8821C)\n#define BITS_TXDMA_H2C_MAP_8821C                                               \\\n\t(BIT_MASK_TXDMA_H2C_MAP_8821C << BIT_SHIFT_TXDMA_H2C_MAP_8821C)\n#define BIT_CLEAR_TXDMA_H2C_MAP_8821C(x) ((x) & (~BITS_TXDMA_H2C_MAP_8821C))\n#define BIT_GET_TXDMA_H2C_MAP_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_H2C_MAP_8821C) & BIT_MASK_TXDMA_H2C_MAP_8821C)\n#define BIT_SET_TXDMA_H2C_MAP_8821C(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_H2C_MAP_8821C(x) | BIT_TXDMA_H2C_MAP_8821C(v))\n\n#define BIT_SHIFT_TXDMA_HIQ_MAP_8821C 14\n#define BIT_MASK_TXDMA_HIQ_MAP_8821C 0x3\n#define BIT_TXDMA_HIQ_MAP_8821C(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_HIQ_MAP_8821C) << BIT_SHIFT_TXDMA_HIQ_MAP_8821C)\n#define BITS_TXDMA_HIQ_MAP_8821C                                               \\\n\t(BIT_MASK_TXDMA_HIQ_MAP_8821C << BIT_SHIFT_TXDMA_HIQ_MAP_8821C)\n#define BIT_CLEAR_TXDMA_HIQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8821C))\n#define BIT_GET_TXDMA_HIQ_MAP_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8821C) & BIT_MASK_TXDMA_HIQ_MAP_8821C)\n#define BIT_SET_TXDMA_HIQ_MAP_8821C(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_HIQ_MAP_8821C(x) | BIT_TXDMA_HIQ_MAP_8821C(v))\n\n#define BIT_SHIFT_TXDMA_MGQ_MAP_8821C 12\n#define BIT_MASK_TXDMA_MGQ_MAP_8821C 0x3\n#define BIT_TXDMA_MGQ_MAP_8821C(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_MGQ_MAP_8821C) << BIT_SHIFT_TXDMA_MGQ_MAP_8821C)\n#define BITS_TXDMA_MGQ_MAP_8821C                                               \\\n\t(BIT_MASK_TXDMA_MGQ_MAP_8821C << BIT_SHIFT_TXDMA_MGQ_MAP_8821C)\n#define BIT_CLEAR_TXDMA_MGQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8821C))\n#define BIT_GET_TXDMA_MGQ_MAP_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8821C) & BIT_MASK_TXDMA_MGQ_MAP_8821C)\n#define BIT_SET_TXDMA_MGQ_MAP_8821C(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_MGQ_MAP_8821C(x) | BIT_TXDMA_MGQ_MAP_8821C(v))\n\n#define BIT_SHIFT_TXDMA_BKQ_MAP_8821C 10\n#define BIT_MASK_TXDMA_BKQ_MAP_8821C 0x3\n#define BIT_TXDMA_BKQ_MAP_8821C(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_BKQ_MAP_8821C) << BIT_SHIFT_TXDMA_BKQ_MAP_8821C)\n#define BITS_TXDMA_BKQ_MAP_8821C                                               \\\n\t(BIT_MASK_TXDMA_BKQ_MAP_8821C << BIT_SHIFT_TXDMA_BKQ_MAP_8821C)\n#define BIT_CLEAR_TXDMA_BKQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8821C))\n#define BIT_GET_TXDMA_BKQ_MAP_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8821C) & BIT_MASK_TXDMA_BKQ_MAP_8821C)\n#define BIT_SET_TXDMA_BKQ_MAP_8821C(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_BKQ_MAP_8821C(x) | BIT_TXDMA_BKQ_MAP_8821C(v))\n\n#define BIT_SHIFT_TXDMA_BEQ_MAP_8821C 8\n#define BIT_MASK_TXDMA_BEQ_MAP_8821C 0x3\n#define BIT_TXDMA_BEQ_MAP_8821C(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_BEQ_MAP_8821C) << BIT_SHIFT_TXDMA_BEQ_MAP_8821C)\n#define BITS_TXDMA_BEQ_MAP_8821C                                               \\\n\t(BIT_MASK_TXDMA_BEQ_MAP_8821C << BIT_SHIFT_TXDMA_BEQ_MAP_8821C)\n#define BIT_CLEAR_TXDMA_BEQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8821C))\n#define BIT_GET_TXDMA_BEQ_MAP_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8821C) & BIT_MASK_TXDMA_BEQ_MAP_8821C)\n#define BIT_SET_TXDMA_BEQ_MAP_8821C(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_BEQ_MAP_8821C(x) | BIT_TXDMA_BEQ_MAP_8821C(v))\n\n#define BIT_SHIFT_TXDMA_VIQ_MAP_8821C 6\n#define BIT_MASK_TXDMA_VIQ_MAP_8821C 0x3\n#define BIT_TXDMA_VIQ_MAP_8821C(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_VIQ_MAP_8821C) << BIT_SHIFT_TXDMA_VIQ_MAP_8821C)\n#define BITS_TXDMA_VIQ_MAP_8821C                                               \\\n\t(BIT_MASK_TXDMA_VIQ_MAP_8821C << BIT_SHIFT_TXDMA_VIQ_MAP_8821C)\n#define BIT_CLEAR_TXDMA_VIQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8821C))\n#define BIT_GET_TXDMA_VIQ_MAP_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8821C) & BIT_MASK_TXDMA_VIQ_MAP_8821C)\n#define BIT_SET_TXDMA_VIQ_MAP_8821C(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_VIQ_MAP_8821C(x) | BIT_TXDMA_VIQ_MAP_8821C(v))\n\n#define BIT_SHIFT_TXDMA_VOQ_MAP_8821C 4\n#define BIT_MASK_TXDMA_VOQ_MAP_8821C 0x3\n#define BIT_TXDMA_VOQ_MAP_8821C(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_VOQ_MAP_8821C) << BIT_SHIFT_TXDMA_VOQ_MAP_8821C)\n#define BITS_TXDMA_VOQ_MAP_8821C                                               \\\n\t(BIT_MASK_TXDMA_VOQ_MAP_8821C << BIT_SHIFT_TXDMA_VOQ_MAP_8821C)\n#define BIT_CLEAR_TXDMA_VOQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8821C))\n#define BIT_GET_TXDMA_VOQ_MAP_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8821C) & BIT_MASK_TXDMA_VOQ_MAP_8821C)\n#define BIT_SET_TXDMA_VOQ_MAP_8821C(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_VOQ_MAP_8821C(x) | BIT_TXDMA_VOQ_MAP_8821C(v))\n\n#define BIT_RXDMA_AGG_EN_8821C BIT(2)\n#define BIT_RXSHFT_EN_8821C BIT(1)\n#define BIT_RXDMA_ARBBW_EN_8821C BIT(0)\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_TRXFF_BNDY_8821C */\n\n#define BIT_SHIFT_RXFFOVFL_RSV_V2_8821C 8\n#define BIT_MASK_RXFFOVFL_RSV_V2_8821C 0xf\n#define BIT_RXFFOVFL_RSV_V2_8821C(x)                                           \\\n\t(((x) & BIT_MASK_RXFFOVFL_RSV_V2_8821C)                                \\\n\t << BIT_SHIFT_RXFFOVFL_RSV_V2_8821C)\n#define BITS_RXFFOVFL_RSV_V2_8821C                                             \\\n\t(BIT_MASK_RXFFOVFL_RSV_V2_8821C << BIT_SHIFT_RXFFOVFL_RSV_V2_8821C)\n#define BIT_CLEAR_RXFFOVFL_RSV_V2_8821C(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8821C))\n#define BIT_GET_RXFFOVFL_RSV_V2_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8821C) &                            \\\n\t BIT_MASK_RXFFOVFL_RSV_V2_8821C)\n#define BIT_SET_RXFFOVFL_RSV_V2_8821C(x, v)                                    \\\n\t(BIT_CLEAR_RXFFOVFL_RSV_V2_8821C(x) | BIT_RXFFOVFL_RSV_V2_8821C(v))\n\n/* 2 REG_PTA_I2C_MBOX_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n#define BIT_SHIFT_I2C_M_STATUS_8821C 8\n#define BIT_MASK_I2C_M_STATUS_8821C 0xf\n#define BIT_I2C_M_STATUS_8821C(x)                                              \\\n\t(((x) & BIT_MASK_I2C_M_STATUS_8821C) << BIT_SHIFT_I2C_M_STATUS_8821C)\n#define BITS_I2C_M_STATUS_8821C                                                \\\n\t(BIT_MASK_I2C_M_STATUS_8821C << BIT_SHIFT_I2C_M_STATUS_8821C)\n#define BIT_CLEAR_I2C_M_STATUS_8821C(x) ((x) & (~BITS_I2C_M_STATUS_8821C))\n#define BIT_GET_I2C_M_STATUS_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_I2C_M_STATUS_8821C) & BIT_MASK_I2C_M_STATUS_8821C)\n#define BIT_SET_I2C_M_STATUS_8821C(x, v)                                       \\\n\t(BIT_CLEAR_I2C_M_STATUS_8821C(x) | BIT_I2C_M_STATUS_8821C(v))\n\n#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C 4\n#define BIT_MASK_I2C_M_BUS_GNT_FW_8821C 0x7\n#define BIT_I2C_M_BUS_GNT_FW_8821C(x)                                          \\\n\t(((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8821C)                               \\\n\t << BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C)\n#define BITS_I2C_M_BUS_GNT_FW_8821C                                            \\\n\t(BIT_MASK_I2C_M_BUS_GNT_FW_8821C << BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C)\n#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8821C(x)                                    \\\n\t((x) & (~BITS_I2C_M_BUS_GNT_FW_8821C))\n#define BIT_GET_I2C_M_BUS_GNT_FW_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) &                           \\\n\t BIT_MASK_I2C_M_BUS_GNT_FW_8821C)\n#define BIT_SET_I2C_M_BUS_GNT_FW_8821C(x, v)                                   \\\n\t(BIT_CLEAR_I2C_M_BUS_GNT_FW_8821C(x) | BIT_I2C_M_BUS_GNT_FW_8821C(v))\n\n#define BIT_I2C_M_GNT_FW_8821C BIT(3)\n\n#define BIT_SHIFT_I2C_M_SPEED_8821C 1\n#define BIT_MASK_I2C_M_SPEED_8821C 0x3\n#define BIT_I2C_M_SPEED_8821C(x)                                               \\\n\t(((x) & BIT_MASK_I2C_M_SPEED_8821C) << BIT_SHIFT_I2C_M_SPEED_8821C)\n#define BITS_I2C_M_SPEED_8821C                                                 \\\n\t(BIT_MASK_I2C_M_SPEED_8821C << BIT_SHIFT_I2C_M_SPEED_8821C)\n#define BIT_CLEAR_I2C_M_SPEED_8821C(x) ((x) & (~BITS_I2C_M_SPEED_8821C))\n#define BIT_GET_I2C_M_SPEED_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_I2C_M_SPEED_8821C) & BIT_MASK_I2C_M_SPEED_8821C)\n#define BIT_SET_I2C_M_SPEED_8821C(x, v)                                        \\\n\t(BIT_CLEAR_I2C_M_SPEED_8821C(x) | BIT_I2C_M_SPEED_8821C(v))\n\n#define BIT_I2C_M_UNLOCK_8821C BIT(0)\n\n/* 2 REG_RXFF_BNDY_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n#define BIT_SHIFT_RXFF0_BNDY_V2_8821C 0\n#define BIT_MASK_RXFF0_BNDY_V2_8821C 0x3ffff\n#define BIT_RXFF0_BNDY_V2_8821C(x)                                             \\\n\t(((x) & BIT_MASK_RXFF0_BNDY_V2_8821C) << BIT_SHIFT_RXFF0_BNDY_V2_8821C)\n#define BITS_RXFF0_BNDY_V2_8821C                                               \\\n\t(BIT_MASK_RXFF0_BNDY_V2_8821C << BIT_SHIFT_RXFF0_BNDY_V2_8821C)\n#define BIT_CLEAR_RXFF0_BNDY_V2_8821C(x) ((x) & (~BITS_RXFF0_BNDY_V2_8821C))\n#define BIT_GET_RXFF0_BNDY_V2_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8821C) & BIT_MASK_RXFF0_BNDY_V2_8821C)\n#define BIT_SET_RXFF0_BNDY_V2_8821C(x, v)                                      \\\n\t(BIT_CLEAR_RXFF0_BNDY_V2_8821C(x) | BIT_RXFF0_BNDY_V2_8821C(v))\n\n/* 2 REG_FE1IMR_8821C */\n#define BIT_FS_RXDMA2_DONE_INT_EN_8821C BIT(28)\n#define BIT_FS_RXDONE3_INT_EN_8821C BIT(27)\n#define BIT_FS_RXDONE2_INT_EN_8821C BIT(26)\n#define BIT_FS_RX_BCN_P4_INT_EN_8821C BIT(25)\n#define BIT_FS_RX_BCN_P3_INT_EN_8821C BIT(24)\n#define BIT_FS_RX_BCN_P2_INT_EN_8821C BIT(23)\n#define BIT_FS_RX_BCN_P1_INT_EN_8821C BIT(22)\n#define BIT_FS_RX_BCN_P0_INT_EN_8821C BIT(21)\n#define BIT_FS_RX_UMD0_INT_EN_8821C BIT(20)\n#define BIT_FS_RX_UMD1_INT_EN_8821C BIT(19)\n#define BIT_FS_RX_BMD0_INT_EN_8821C BIT(18)\n#define BIT_FS_RX_BMD1_INT_EN_8821C BIT(17)\n#define BIT_FS_RXDONE_INT_EN_8821C BIT(16)\n#define BIT_FS_WWLAN_INT_EN_8821C BIT(15)\n#define BIT_FS_SOUND_DONE_INT_EN_8821C BIT(14)\n#define BIT_FS_LP_STBY_INT_EN_8821C BIT(13)\n#define BIT_FS_TRL_MTR_INT_EN_8821C BIT(12)\n#define BIT_FS_BF1_PRETO_INT_EN_8821C BIT(11)\n#define BIT_FS_BF0_PRETO_INT_EN_8821C BIT(10)\n#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8821C BIT(9)\n#define BIT_FS_LTE_COEX_EN_8821C BIT(6)\n#define BIT_FS_WLACTOFF_INT_EN_8821C BIT(5)\n#define BIT_FS_WLACTON_INT_EN_8821C BIT(4)\n#define BIT_FS_BTCMD_INT_EN_8821C BIT(3)\n#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8821C BIT(2)\n#define BIT_FS_TRPC_TO_INT_EN_V1_8821C BIT(1)\n#define BIT_FS_RPC_O_T_INT_EN_V1_8821C BIT(0)\n\n/* 2 REG_FE1ISR_8821C */\n#define BIT_FS_RXDMA2_DONE_INT_8821C BIT(28)\n#define BIT_FS_RXDONE3_INT_8821C BIT(27)\n#define BIT_FS_RXDONE2_INT_8821C BIT(26)\n#define BIT_FS_RX_BCN_P4_INT_8821C BIT(25)\n#define BIT_FS_RX_BCN_P3_INT_8821C BIT(24)\n#define BIT_FS_RX_BCN_P2_INT_8821C BIT(23)\n#define BIT_FS_RX_BCN_P1_INT_8821C BIT(22)\n#define BIT_FS_RX_BCN_P0_INT_8821C BIT(21)\n#define BIT_FS_RX_UMD0_INT_8821C BIT(20)\n#define BIT_FS_RX_UMD1_INT_8821C BIT(19)\n#define BIT_FS_RX_BMD0_INT_8821C BIT(18)\n#define BIT_FS_RX_BMD1_INT_8821C BIT(17)\n#define BIT_FS_RXDONE_INT_8821C BIT(16)\n#define BIT_FS_WWLAN_INT_8821C BIT(15)\n#define BIT_FS_SOUND_DONE_INT_8821C BIT(14)\n#define BIT_FS_LP_STBY_INT_8821C BIT(13)\n#define BIT_FS_TRL_MTR_INT_8821C BIT(12)\n#define BIT_FS_BF1_PRETO_INT_8821C BIT(11)\n#define BIT_FS_BF0_PRETO_INT_8821C BIT(10)\n#define BIT_FS_PTCL_RELEASE_MACID_INT_8821C BIT(9)\n#define BIT_FS_LTE_COEX_INT_8821C BIT(6)\n#define BIT_FS_WLACTOFF_INT_8821C BIT(5)\n#define BIT_FS_WLACTON_INT_8821C BIT(4)\n#define BIT_FS_BCN_RX_INT_INT_8821C BIT(3)\n#define BIT_FS_MAILBOX_TO_I2C_INT_8821C BIT(2)\n#define BIT_FS_TRPC_TO_INT_8821C BIT(1)\n#define BIT_FS_RPC_O_T_INT_8821C BIT(0)\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_CPWM_8821C */\n#define BIT_CPWM_TOGGLING_8821C BIT(31)\n\n#define BIT_SHIFT_CPWM_MOD_8821C 24\n#define BIT_MASK_CPWM_MOD_8821C 0x7f\n#define BIT_CPWM_MOD_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_CPWM_MOD_8821C) << BIT_SHIFT_CPWM_MOD_8821C)\n#define BITS_CPWM_MOD_8821C                                                    \\\n\t(BIT_MASK_CPWM_MOD_8821C << BIT_SHIFT_CPWM_MOD_8821C)\n#define BIT_CLEAR_CPWM_MOD_8821C(x) ((x) & (~BITS_CPWM_MOD_8821C))\n#define BIT_GET_CPWM_MOD_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_CPWM_MOD_8821C) & BIT_MASK_CPWM_MOD_8821C)\n#define BIT_SET_CPWM_MOD_8821C(x, v)                                           \\\n\t(BIT_CLEAR_CPWM_MOD_8821C(x) | BIT_CPWM_MOD_8821C(v))\n\n/* 2 REG_FWIMR_8821C */\n#define BIT_FS_TXBCNOK_MB7_INT_EN_8821C BIT(31)\n#define BIT_FS_TXBCNOK_MB6_INT_EN_8821C BIT(30)\n#define BIT_FS_TXBCNOK_MB5_INT_EN_8821C BIT(29)\n#define BIT_FS_TXBCNOK_MB4_INT_EN_8821C BIT(28)\n#define BIT_FS_TXBCNOK_MB3_INT_EN_8821C BIT(27)\n#define BIT_FS_TXBCNOK_MB2_INT_EN_8821C BIT(26)\n#define BIT_FS_TXBCNOK_MB1_INT_EN_8821C BIT(25)\n#define BIT_FS_TXBCNOK_MB0_INT_EN_8821C BIT(24)\n#define BIT_FS_TXBCNERR_MB7_INT_EN_8821C BIT(23)\n#define BIT_FS_TXBCNERR_MB6_INT_EN_8821C BIT(22)\n#define BIT_FS_TXBCNERR_MB5_INT_EN_8821C BIT(21)\n#define BIT_FS_TXBCNERR_MB4_INT_EN_8821C BIT(20)\n#define BIT_FS_TXBCNERR_MB3_INT_EN_8821C BIT(19)\n#define BIT_FS_TXBCNERR_MB2_INT_EN_8821C BIT(18)\n#define BIT_FS_TXBCNERR_MB1_INT_EN_8821C BIT(17)\n#define BIT_FS_TXBCNERR_MB0_INT_EN_8821C BIT(16)\n#define BIT_CPU_MGQ_TXDONE_INT_EN_8821C BIT(15)\n#define BIT_SIFS_OVERSPEC_INT_EN_8821C BIT(14)\n#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8821C BIT(13)\n#define BIT_FS_MGNTQFF_TO_INT_EN_8821C BIT(12)\n#define BIT_FS_DDMA1_LP_INT_EN_8821C BIT(11)\n#define BIT_FS_DDMA1_HP_INT_EN_8821C BIT(10)\n#define BIT_FS_DDMA0_LP_INT_EN_8821C BIT(9)\n#define BIT_FS_DDMA0_HP_INT_EN_8821C BIT(8)\n#define BIT_FS_TRXRPT_INT_EN_8821C BIT(7)\n#define BIT_FS_C2H_W_READY_INT_EN_8821C BIT(6)\n#define BIT_FS_HRCV_INT_EN_8821C BIT(5)\n#define BIT_FS_H2CCMD_INT_EN_8821C BIT(4)\n#define BIT_FS_TXPKTIN_INT_EN_8821C BIT(3)\n#define BIT_FS_ERRORHDL_INT_EN_8821C BIT(2)\n#define BIT_FS_TXCCX_INT_EN_8821C BIT(1)\n#define BIT_FS_TXCLOSE_INT_EN_8821C BIT(0)\n\n/* 2 REG_FWISR_8821C */\n#define BIT_FS_TXBCNOK_MB7_INT_8821C BIT(31)\n#define BIT_FS_TXBCNOK_MB6_INT_8821C BIT(30)\n#define BIT_FS_TXBCNOK_MB5_INT_8821C BIT(29)\n#define BIT_FS_TXBCNOK_MB4_INT_8821C BIT(28)\n#define BIT_FS_TXBCNOK_MB3_INT_8821C BIT(27)\n#define BIT_FS_TXBCNOK_MB2_INT_8821C BIT(26)\n#define BIT_FS_TXBCNOK_MB1_INT_8821C BIT(25)\n#define BIT_FS_TXBCNOK_MB0_INT_8821C BIT(24)\n#define BIT_FS_TXBCNERR_MB7_INT_8821C BIT(23)\n#define BIT_FS_TXBCNERR_MB6_INT_8821C BIT(22)\n#define BIT_FS_TXBCNERR_MB5_INT_8821C BIT(21)\n#define BIT_FS_TXBCNERR_MB4_INT_8821C BIT(20)\n#define BIT_FS_TXBCNERR_MB3_INT_8821C BIT(19)\n#define BIT_FS_TXBCNERR_MB2_INT_8821C BIT(18)\n#define BIT_FS_TXBCNERR_MB1_INT_8821C BIT(17)\n#define BIT_FS_TXBCNERR_MB0_INT_8821C BIT(16)\n#define BIT_CPU_MGQ_TXDONE_INT_8821C BIT(15)\n#define BIT_SIFS_OVERSPEC_INT_8821C BIT(14)\n#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8821C BIT(13)\n#define BIT_FS_MGNTQFF_TO_INT_8821C BIT(12)\n#define BIT_FS_DDMA1_LP_INT_8821C BIT(11)\n#define BIT_FS_DDMA1_HP_INT_8821C BIT(10)\n#define BIT_FS_DDMA0_LP_INT_8821C BIT(9)\n#define BIT_FS_DDMA0_HP_INT_8821C BIT(8)\n#define BIT_FS_TRXRPT_INT_8821C BIT(7)\n#define BIT_FS_C2H_W_READY_INT_8821C BIT(6)\n#define BIT_FS_HRCV_INT_8821C BIT(5)\n#define BIT_FS_H2CCMD_INT_8821C BIT(4)\n#define BIT_FS_TXPKTIN_INT_8821C BIT(3)\n#define BIT_FS_ERRORHDL_INT_8821C BIT(2)\n#define BIT_FS_TXCCX_INT_8821C BIT(1)\n#define BIT_FS_TXCLOSE_INT_8821C BIT(0)\n\n/* 2 REG_FTIMR_8821C */\n#define BIT_PS_TIMER_C_EARLY_INT_EN_8821C BIT(23)\n#define BIT_PS_TIMER_B_EARLY_INT_EN_8821C BIT(22)\n#define BIT_PS_TIMER_A_EARLY_INT_EN_8821C BIT(21)\n#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8821C BIT(20)\n#define BIT_PS_TIMER_C_INT_EN_8821C BIT(19)\n#define BIT_PS_TIMER_B_INT_EN_8821C BIT(18)\n#define BIT_PS_TIMER_A_INT_EN_8821C BIT(17)\n#define BIT_CPUMGQ_TX_TIMER_INT_EN_8821C BIT(16)\n#define BIT_FS_PS_TIMEOUT2_EN_8821C BIT(15)\n#define BIT_FS_PS_TIMEOUT1_EN_8821C BIT(14)\n#define BIT_FS_PS_TIMEOUT0_EN_8821C BIT(13)\n#define BIT_FS_GTINT8_EN_8821C BIT(8)\n#define BIT_FS_GTINT7_EN_8821C BIT(7)\n#define BIT_FS_GTINT6_EN_8821C BIT(6)\n#define BIT_FS_GTINT5_EN_8821C BIT(5)\n#define BIT_FS_GTINT4_EN_8821C BIT(4)\n#define BIT_FS_GTINT3_EN_8821C BIT(3)\n#define BIT_FS_GTINT2_EN_8821C BIT(2)\n#define BIT_FS_GTINT1_EN_8821C BIT(1)\n#define BIT_FS_GTINT0_EN_8821C BIT(0)\n\n/* 2 REG_FTISR_8821C */\n#define BIT_PS_TIMER_C_EARLY__INT_8821C BIT(23)\n#define BIT_PS_TIMER_B_EARLY__INT_8821C BIT(22)\n#define BIT_PS_TIMER_A_EARLY__INT_8821C BIT(21)\n#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8821C BIT(20)\n#define BIT_PS_TIMER_C_INT_8821C BIT(19)\n#define BIT_PS_TIMER_B_INT_8821C BIT(18)\n#define BIT_PS_TIMER_A_INT_8821C BIT(17)\n#define BIT_CPUMGQ_TX_TIMER_INT_8821C BIT(16)\n#define BIT_FS_PS_TIMEOUT2_INT_8821C BIT(15)\n#define BIT_FS_PS_TIMEOUT1_INT_8821C BIT(14)\n#define BIT_FS_PS_TIMEOUT0_INT_8821C BIT(13)\n#define BIT_FS_GTINT8_INT_8821C BIT(8)\n#define BIT_FS_GTINT7_INT_8821C BIT(7)\n#define BIT_FS_GTINT6_INT_8821C BIT(6)\n#define BIT_FS_GTINT5_INT_8821C BIT(5)\n#define BIT_FS_GTINT4_INT_8821C BIT(4)\n#define BIT_FS_GTINT3_INT_8821C BIT(3)\n#define BIT_FS_GTINT2_INT_8821C BIT(2)\n#define BIT_FS_GTINT1_INT_8821C BIT(1)\n#define BIT_FS_GTINT0_INT_8821C BIT(0)\n\n/* 2 REG_PKTBUF_DBG_CTRL_8821C */\n\n#define BIT_SHIFT_PKTBUF_WRITE_EN_8821C 24\n#define BIT_MASK_PKTBUF_WRITE_EN_8821C 0xff\n#define BIT_PKTBUF_WRITE_EN_8821C(x)                                           \\\n\t(((x) & BIT_MASK_PKTBUF_WRITE_EN_8821C)                                \\\n\t << BIT_SHIFT_PKTBUF_WRITE_EN_8821C)\n#define BITS_PKTBUF_WRITE_EN_8821C                                             \\\n\t(BIT_MASK_PKTBUF_WRITE_EN_8821C << BIT_SHIFT_PKTBUF_WRITE_EN_8821C)\n#define BIT_CLEAR_PKTBUF_WRITE_EN_8821C(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8821C))\n#define BIT_GET_PKTBUF_WRITE_EN_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8821C) &                            \\\n\t BIT_MASK_PKTBUF_WRITE_EN_8821C)\n#define BIT_SET_PKTBUF_WRITE_EN_8821C(x, v)                                    \\\n\t(BIT_CLEAR_PKTBUF_WRITE_EN_8821C(x) | BIT_PKTBUF_WRITE_EN_8821C(v))\n\n#define BIT_TXRPTBUF_DBG_8821C BIT(23)\n\n/* 2 REG_NOT_VALID_8821C */\n#define BIT_TXPKTBUF_DBG_V2_8821C BIT(20)\n#define BIT_RXPKTBUF_DBG_8821C BIT(16)\n\n#define BIT_SHIFT_PKTBUF_DBG_ADDR_8821C 0\n#define BIT_MASK_PKTBUF_DBG_ADDR_8821C 0x1fff\n#define BIT_PKTBUF_DBG_ADDR_8821C(x)                                           \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_ADDR_8821C)                                \\\n\t << BIT_SHIFT_PKTBUF_DBG_ADDR_8821C)\n#define BITS_PKTBUF_DBG_ADDR_8821C                                             \\\n\t(BIT_MASK_PKTBUF_DBG_ADDR_8821C << BIT_SHIFT_PKTBUF_DBG_ADDR_8821C)\n#define BIT_CLEAR_PKTBUF_DBG_ADDR_8821C(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8821C))\n#define BIT_GET_PKTBUF_DBG_ADDR_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8821C) &                            \\\n\t BIT_MASK_PKTBUF_DBG_ADDR_8821C)\n#define BIT_SET_PKTBUF_DBG_ADDR_8821C(x, v)                                    \\\n\t(BIT_CLEAR_PKTBUF_DBG_ADDR_8821C(x) | BIT_PKTBUF_DBG_ADDR_8821C(v))\n\n/* 2 REG_PKTBUF_DBG_DATA_L_8821C */\n\n#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C 0\n#define BIT_MASK_PKTBUF_DBG_DATA_L_8821C 0xffffffffL\n#define BIT_PKTBUF_DBG_DATA_L_8821C(x)                                         \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8821C)                              \\\n\t << BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C)\n#define BITS_PKTBUF_DBG_DATA_L_8821C                                           \\\n\t(BIT_MASK_PKTBUF_DBG_DATA_L_8821C << BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C)\n#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8821C(x)                                   \\\n\t((x) & (~BITS_PKTBUF_DBG_DATA_L_8821C))\n#define BIT_GET_PKTBUF_DBG_DATA_L_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C) &                          \\\n\t BIT_MASK_PKTBUF_DBG_DATA_L_8821C)\n#define BIT_SET_PKTBUF_DBG_DATA_L_8821C(x, v)                                  \\\n\t(BIT_CLEAR_PKTBUF_DBG_DATA_L_8821C(x) | BIT_PKTBUF_DBG_DATA_L_8821C(v))\n\n/* 2 REG_PKTBUF_DBG_DATA_H_8821C */\n\n#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C 0\n#define BIT_MASK_PKTBUF_DBG_DATA_H_8821C 0xffffffffL\n#define BIT_PKTBUF_DBG_DATA_H_8821C(x)                                         \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8821C)                              \\\n\t << BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C)\n#define BITS_PKTBUF_DBG_DATA_H_8821C                                           \\\n\t(BIT_MASK_PKTBUF_DBG_DATA_H_8821C << BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C)\n#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8821C(x)                                   \\\n\t((x) & (~BITS_PKTBUF_DBG_DATA_H_8821C))\n#define BIT_GET_PKTBUF_DBG_DATA_H_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C) &                          \\\n\t BIT_MASK_PKTBUF_DBG_DATA_H_8821C)\n#define BIT_SET_PKTBUF_DBG_DATA_H_8821C(x, v)                                  \\\n\t(BIT_CLEAR_PKTBUF_DBG_DATA_H_8821C(x) | BIT_PKTBUF_DBG_DATA_H_8821C(v))\n\n/* 2 REG_CPWM2_8821C */\n\n#define BIT_SHIFT_L0S_TO_RCVY_NUM_8821C 16\n#define BIT_MASK_L0S_TO_RCVY_NUM_8821C 0xff\n#define BIT_L0S_TO_RCVY_NUM_8821C(x)                                           \\\n\t(((x) & BIT_MASK_L0S_TO_RCVY_NUM_8821C)                                \\\n\t << BIT_SHIFT_L0S_TO_RCVY_NUM_8821C)\n#define BITS_L0S_TO_RCVY_NUM_8821C                                             \\\n\t(BIT_MASK_L0S_TO_RCVY_NUM_8821C << BIT_SHIFT_L0S_TO_RCVY_NUM_8821C)\n#define BIT_CLEAR_L0S_TO_RCVY_NUM_8821C(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8821C))\n#define BIT_GET_L0S_TO_RCVY_NUM_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) &                            \\\n\t BIT_MASK_L0S_TO_RCVY_NUM_8821C)\n#define BIT_SET_L0S_TO_RCVY_NUM_8821C(x, v)                                    \\\n\t(BIT_CLEAR_L0S_TO_RCVY_NUM_8821C(x) | BIT_L0S_TO_RCVY_NUM_8821C(v))\n\n#define BIT_CPWM2_TOGGLING_8821C BIT(15)\n\n#define BIT_SHIFT_CPWM2_MOD_8821C 0\n#define BIT_MASK_CPWM2_MOD_8821C 0x7fff\n#define BIT_CPWM2_MOD_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_CPWM2_MOD_8821C) << BIT_SHIFT_CPWM2_MOD_8821C)\n#define BITS_CPWM2_MOD_8821C                                                   \\\n\t(BIT_MASK_CPWM2_MOD_8821C << BIT_SHIFT_CPWM2_MOD_8821C)\n#define BIT_CLEAR_CPWM2_MOD_8821C(x) ((x) & (~BITS_CPWM2_MOD_8821C))\n#define BIT_GET_CPWM2_MOD_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_CPWM2_MOD_8821C) & BIT_MASK_CPWM2_MOD_8821C)\n#define BIT_SET_CPWM2_MOD_8821C(x, v)                                          \\\n\t(BIT_CLEAR_CPWM2_MOD_8821C(x) | BIT_CPWM2_MOD_8821C(v))\n\n/* 2 REG_TC0_CTRL_8821C */\n#define BIT_TC0INT_EN_8821C BIT(26)\n#define BIT_TC0MODE_8821C BIT(25)\n#define BIT_TC0EN_8821C BIT(24)\n\n#define BIT_SHIFT_TC0DATA_8821C 0\n#define BIT_MASK_TC0DATA_8821C 0xffffff\n#define BIT_TC0DATA_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_TC0DATA_8821C) << BIT_SHIFT_TC0DATA_8821C)\n#define BITS_TC0DATA_8821C (BIT_MASK_TC0DATA_8821C << BIT_SHIFT_TC0DATA_8821C)\n#define BIT_CLEAR_TC0DATA_8821C(x) ((x) & (~BITS_TC0DATA_8821C))\n#define BIT_GET_TC0DATA_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC0DATA_8821C) & BIT_MASK_TC0DATA_8821C)\n#define BIT_SET_TC0DATA_8821C(x, v)                                            \\\n\t(BIT_CLEAR_TC0DATA_8821C(x) | BIT_TC0DATA_8821C(v))\n\n/* 2 REG_TC1_CTRL_8821C */\n#define BIT_TC1INT_EN_8821C BIT(26)\n#define BIT_TC1MODE_8821C BIT(25)\n#define BIT_TC1EN_8821C BIT(24)\n\n#define BIT_SHIFT_TC1DATA_8821C 0\n#define BIT_MASK_TC1DATA_8821C 0xffffff\n#define BIT_TC1DATA_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_TC1DATA_8821C) << BIT_SHIFT_TC1DATA_8821C)\n#define BITS_TC1DATA_8821C (BIT_MASK_TC1DATA_8821C << BIT_SHIFT_TC1DATA_8821C)\n#define BIT_CLEAR_TC1DATA_8821C(x) ((x) & (~BITS_TC1DATA_8821C))\n#define BIT_GET_TC1DATA_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC1DATA_8821C) & BIT_MASK_TC1DATA_8821C)\n#define BIT_SET_TC1DATA_8821C(x, v)                                            \\\n\t(BIT_CLEAR_TC1DATA_8821C(x) | BIT_TC1DATA_8821C(v))\n\n/* 2 REG_TC2_CTRL_8821C */\n#define BIT_TC2INT_EN_8821C BIT(26)\n#define BIT_TC2MODE_8821C BIT(25)\n#define BIT_TC2EN_8821C BIT(24)\n\n#define BIT_SHIFT_TC2DATA_8821C 0\n#define BIT_MASK_TC2DATA_8821C 0xffffff\n#define BIT_TC2DATA_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_TC2DATA_8821C) << BIT_SHIFT_TC2DATA_8821C)\n#define BITS_TC2DATA_8821C (BIT_MASK_TC2DATA_8821C << BIT_SHIFT_TC2DATA_8821C)\n#define BIT_CLEAR_TC2DATA_8821C(x) ((x) & (~BITS_TC2DATA_8821C))\n#define BIT_GET_TC2DATA_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC2DATA_8821C) & BIT_MASK_TC2DATA_8821C)\n#define BIT_SET_TC2DATA_8821C(x, v)                                            \\\n\t(BIT_CLEAR_TC2DATA_8821C(x) | BIT_TC2DATA_8821C(v))\n\n/* 2 REG_TC3_CTRL_8821C */\n#define BIT_TC3INT_EN_8821C BIT(26)\n#define BIT_TC3MODE_8821C BIT(25)\n#define BIT_TC3EN_8821C BIT(24)\n\n#define BIT_SHIFT_TC3DATA_8821C 0\n#define BIT_MASK_TC3DATA_8821C 0xffffff\n#define BIT_TC3DATA_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_TC3DATA_8821C) << BIT_SHIFT_TC3DATA_8821C)\n#define BITS_TC3DATA_8821C (BIT_MASK_TC3DATA_8821C << BIT_SHIFT_TC3DATA_8821C)\n#define BIT_CLEAR_TC3DATA_8821C(x) ((x) & (~BITS_TC3DATA_8821C))\n#define BIT_GET_TC3DATA_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC3DATA_8821C) & BIT_MASK_TC3DATA_8821C)\n#define BIT_SET_TC3DATA_8821C(x, v)                                            \\\n\t(BIT_CLEAR_TC3DATA_8821C(x) | BIT_TC3DATA_8821C(v))\n\n/* 2 REG_TC4_CTRL_8821C */\n#define BIT_TC4INT_EN_8821C BIT(26)\n#define BIT_TC4MODE_8821C BIT(25)\n#define BIT_TC4EN_8821C BIT(24)\n\n#define BIT_SHIFT_TC4DATA_8821C 0\n#define BIT_MASK_TC4DATA_8821C 0xffffff\n#define BIT_TC4DATA_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_TC4DATA_8821C) << BIT_SHIFT_TC4DATA_8821C)\n#define BITS_TC4DATA_8821C (BIT_MASK_TC4DATA_8821C << BIT_SHIFT_TC4DATA_8821C)\n#define BIT_CLEAR_TC4DATA_8821C(x) ((x) & (~BITS_TC4DATA_8821C))\n#define BIT_GET_TC4DATA_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC4DATA_8821C) & BIT_MASK_TC4DATA_8821C)\n#define BIT_SET_TC4DATA_8821C(x, v)                                            \\\n\t(BIT_CLEAR_TC4DATA_8821C(x) | BIT_TC4DATA_8821C(v))\n\n/* 2 REG_TCUNIT_BASE_8821C */\n\n#define BIT_SHIFT_TCUNIT_BASE_8821C 0\n#define BIT_MASK_TCUNIT_BASE_8821C 0x3fff\n#define BIT_TCUNIT_BASE_8821C(x)                                               \\\n\t(((x) & BIT_MASK_TCUNIT_BASE_8821C) << BIT_SHIFT_TCUNIT_BASE_8821C)\n#define BITS_TCUNIT_BASE_8821C                                                 \\\n\t(BIT_MASK_TCUNIT_BASE_8821C << BIT_SHIFT_TCUNIT_BASE_8821C)\n#define BIT_CLEAR_TCUNIT_BASE_8821C(x) ((x) & (~BITS_TCUNIT_BASE_8821C))\n#define BIT_GET_TCUNIT_BASE_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_TCUNIT_BASE_8821C) & BIT_MASK_TCUNIT_BASE_8821C)\n#define BIT_SET_TCUNIT_BASE_8821C(x, v)                                        \\\n\t(BIT_CLEAR_TCUNIT_BASE_8821C(x) | BIT_TCUNIT_BASE_8821C(v))\n\n/* 2 REG_TC5_CTRL_8821C */\n#define BIT_TC5INT_EN_8821C BIT(26)\n#define BIT_TC5MODE_8821C BIT(25)\n#define BIT_TC5EN_8821C BIT(24)\n\n#define BIT_SHIFT_TC5DATA_8821C 0\n#define BIT_MASK_TC5DATA_8821C 0xffffff\n#define BIT_TC5DATA_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_TC5DATA_8821C) << BIT_SHIFT_TC5DATA_8821C)\n#define BITS_TC5DATA_8821C (BIT_MASK_TC5DATA_8821C << BIT_SHIFT_TC5DATA_8821C)\n#define BIT_CLEAR_TC5DATA_8821C(x) ((x) & (~BITS_TC5DATA_8821C))\n#define BIT_GET_TC5DATA_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC5DATA_8821C) & BIT_MASK_TC5DATA_8821C)\n#define BIT_SET_TC5DATA_8821C(x, v)                                            \\\n\t(BIT_CLEAR_TC5DATA_8821C(x) | BIT_TC5DATA_8821C(v))\n\n/* 2 REG_TC6_CTRL_8821C */\n#define BIT_TC6INT_EN_8821C BIT(26)\n#define BIT_TC6MODE_8821C BIT(25)\n#define BIT_TC6EN_8821C BIT(24)\n\n#define BIT_SHIFT_TC6DATA_8821C 0\n#define BIT_MASK_TC6DATA_8821C 0xffffff\n#define BIT_TC6DATA_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_TC6DATA_8821C) << BIT_SHIFT_TC6DATA_8821C)\n#define BITS_TC6DATA_8821C (BIT_MASK_TC6DATA_8821C << BIT_SHIFT_TC6DATA_8821C)\n#define BIT_CLEAR_TC6DATA_8821C(x) ((x) & (~BITS_TC6DATA_8821C))\n#define BIT_GET_TC6DATA_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC6DATA_8821C) & BIT_MASK_TC6DATA_8821C)\n#define BIT_SET_TC6DATA_8821C(x, v)                                            \\\n\t(BIT_CLEAR_TC6DATA_8821C(x) | BIT_TC6DATA_8821C(v))\n\n/* 2 REG_MBIST_DRF_FAIL_8821C */\n\n#define BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C 26\n#define BIT_MASK_8051_MBIST_DRF_FAIL_8821C 0x3f\n#define BIT_8051_MBIST_DRF_FAIL_8821C(x)                                       \\\n\t(((x) & BIT_MASK_8051_MBIST_DRF_FAIL_8821C)                            \\\n\t << BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C)\n#define BITS_8051_MBIST_DRF_FAIL_8821C                                         \\\n\t(BIT_MASK_8051_MBIST_DRF_FAIL_8821C                                    \\\n\t << BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C)\n#define BIT_CLEAR_8051_MBIST_DRF_FAIL_8821C(x)                                 \\\n\t((x) & (~BITS_8051_MBIST_DRF_FAIL_8821C))\n#define BIT_GET_8051_MBIST_DRF_FAIL_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C) &                        \\\n\t BIT_MASK_8051_MBIST_DRF_FAIL_8821C)\n#define BIT_SET_8051_MBIST_DRF_FAIL_8821C(x, v)                                \\\n\t(BIT_CLEAR_8051_MBIST_DRF_FAIL_8821C(x) |                              \\\n\t BIT_8051_MBIST_DRF_FAIL_8821C(v))\n\n#define BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C 24\n#define BIT_MASK_USB_MBIST_DRF_FAIL_8821C 0x3\n#define BIT_USB_MBIST_DRF_FAIL_8821C(x)                                        \\\n\t(((x) & BIT_MASK_USB_MBIST_DRF_FAIL_8821C)                             \\\n\t << BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C)\n#define BITS_USB_MBIST_DRF_FAIL_8821C                                          \\\n\t(BIT_MASK_USB_MBIST_DRF_FAIL_8821C                                     \\\n\t << BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C)\n#define BIT_CLEAR_USB_MBIST_DRF_FAIL_8821C(x)                                  \\\n\t((x) & (~BITS_USB_MBIST_DRF_FAIL_8821C))\n#define BIT_GET_USB_MBIST_DRF_FAIL_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C) &                         \\\n\t BIT_MASK_USB_MBIST_DRF_FAIL_8821C)\n#define BIT_SET_USB_MBIST_DRF_FAIL_8821C(x, v)                                 \\\n\t(BIT_CLEAR_USB_MBIST_DRF_FAIL_8821C(x) |                               \\\n\t BIT_USB_MBIST_DRF_FAIL_8821C(v))\n\n#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C 18\n#define BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C 0x3f\n#define BIT_PCIE_MBIST_DRF_FAIL_8821C(x)                                       \\\n\t(((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C)                            \\\n\t << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C)\n#define BITS_PCIE_MBIST_DRF_FAIL_8821C                                         \\\n\t(BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C                                    \\\n\t << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C)\n#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8821C(x)                                 \\\n\t((x) & (~BITS_PCIE_MBIST_DRF_FAIL_8821C))\n#define BIT_GET_PCIE_MBIST_DRF_FAIL_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C) &                        \\\n\t BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C)\n#define BIT_SET_PCIE_MBIST_DRF_FAIL_8821C(x, v)                                \\\n\t(BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8821C(x) |                              \\\n\t BIT_PCIE_MBIST_DRF_FAIL_8821C(v))\n\n#define BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C 0\n#define BIT_MASK_MAC_MBIST_DRF_FAIL_8821C 0x3ffff\n#define BIT_MAC_MBIST_DRF_FAIL_8821C(x)                                        \\\n\t(((x) & BIT_MASK_MAC_MBIST_DRF_FAIL_8821C)                             \\\n\t << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C)\n#define BITS_MAC_MBIST_DRF_FAIL_8821C                                          \\\n\t(BIT_MASK_MAC_MBIST_DRF_FAIL_8821C                                     \\\n\t << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C)\n#define BIT_CLEAR_MAC_MBIST_DRF_FAIL_8821C(x)                                  \\\n\t((x) & (~BITS_MAC_MBIST_DRF_FAIL_8821C))\n#define BIT_GET_MAC_MBIST_DRF_FAIL_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C) &                         \\\n\t BIT_MASK_MAC_MBIST_DRF_FAIL_8821C)\n#define BIT_SET_MAC_MBIST_DRF_FAIL_8821C(x, v)                                 \\\n\t(BIT_CLEAR_MAC_MBIST_DRF_FAIL_8821C(x) |                               \\\n\t BIT_MAC_MBIST_DRF_FAIL_8821C(v))\n\n/* 2 REG_MBIST_START_PAUSE_8821C */\n\n#define BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C 26\n#define BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C 0x3f\n#define BIT_8051_MBIST_START_PAUSE_V1_8821C(x)                                 \\\n\t(((x) & BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C)                      \\\n\t << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C)\n#define BITS_8051_MBIST_START_PAUSE_V1_8821C                                   \\\n\t(BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C                              \\\n\t << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C)\n#define BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8821C(x)                           \\\n\t((x) & (~BITS_8051_MBIST_START_PAUSE_V1_8821C))\n#define BIT_GET_8051_MBIST_START_PAUSE_V1_8821C(x)                             \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C) &                  \\\n\t BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C)\n#define BIT_SET_8051_MBIST_START_PAUSE_V1_8821C(x, v)                          \\\n\t(BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8821C(x) |                        \\\n\t BIT_8051_MBIST_START_PAUSE_V1_8821C(v))\n\n#define BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C 24\n#define BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C 0x3\n#define BIT_USB_MBIST_START_PAUSE_V1_8821C(x)                                  \\\n\t(((x) & BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C)                       \\\n\t << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C)\n#define BITS_USB_MBIST_START_PAUSE_V1_8821C                                    \\\n\t(BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C                               \\\n\t << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C)\n#define BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8821C(x)                            \\\n\t((x) & (~BITS_USB_MBIST_START_PAUSE_V1_8821C))\n#define BIT_GET_USB_MBIST_START_PAUSE_V1_8821C(x)                              \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C) &                   \\\n\t BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C)\n#define BIT_SET_USB_MBIST_START_PAUSE_V1_8821C(x, v)                           \\\n\t(BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8821C(x) |                         \\\n\t BIT_USB_MBIST_START_PAUSE_V1_8821C(v))\n\n#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C 18\n#define BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C 0x3f\n#define BIT_PCIE_MBIST_START_PAUSE_V1_8821C(x)                                 \\\n\t(((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C)                      \\\n\t << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C)\n#define BITS_PCIE_MBIST_START_PAUSE_V1_8821C                                   \\\n\t(BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C                              \\\n\t << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C)\n#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8821C(x)                           \\\n\t((x) & (~BITS_PCIE_MBIST_START_PAUSE_V1_8821C))\n#define BIT_GET_PCIE_MBIST_START_PAUSE_V1_8821C(x)                             \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C) &                  \\\n\t BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C)\n#define BIT_SET_PCIE_MBIST_START_PAUSE_V1_8821C(x, v)                          \\\n\t(BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8821C(x) |                        \\\n\t BIT_PCIE_MBIST_START_PAUSE_V1_8821C(v))\n\n#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C 0\n#define BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C 0x3ffff\n#define BIT_MAC_MBIST_START_PAUSE_V1_8821C(x)                                  \\\n\t(((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C)                       \\\n\t << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C)\n#define BITS_MAC_MBIST_START_PAUSE_V1_8821C                                    \\\n\t(BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C                               \\\n\t << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C)\n#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8821C(x)                            \\\n\t((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8821C))\n#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8821C(x)                              \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C) &                   \\\n\t BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C)\n#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8821C(x, v)                           \\\n\t(BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8821C(x) |                         \\\n\t BIT_MAC_MBIST_START_PAUSE_V1_8821C(v))\n\n/* 2 REG_MBIST_DONE_8821C */\n\n#define BIT_SHIFT_8051_MBIST_DONE_V1_8821C 26\n#define BIT_MASK_8051_MBIST_DONE_V1_8821C 0x3f\n#define BIT_8051_MBIST_DONE_V1_8821C(x)                                        \\\n\t(((x) & BIT_MASK_8051_MBIST_DONE_V1_8821C)                             \\\n\t << BIT_SHIFT_8051_MBIST_DONE_V1_8821C)\n#define BITS_8051_MBIST_DONE_V1_8821C                                          \\\n\t(BIT_MASK_8051_MBIST_DONE_V1_8821C                                     \\\n\t << BIT_SHIFT_8051_MBIST_DONE_V1_8821C)\n#define BIT_CLEAR_8051_MBIST_DONE_V1_8821C(x)                                  \\\n\t((x) & (~BITS_8051_MBIST_DONE_V1_8821C))\n#define BIT_GET_8051_MBIST_DONE_V1_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_DONE_V1_8821C) &                         \\\n\t BIT_MASK_8051_MBIST_DONE_V1_8821C)\n#define BIT_SET_8051_MBIST_DONE_V1_8821C(x, v)                                 \\\n\t(BIT_CLEAR_8051_MBIST_DONE_V1_8821C(x) |                               \\\n\t BIT_8051_MBIST_DONE_V1_8821C(v))\n\n#define BIT_SHIFT_USB_MBIST_DONE_V1_8821C 24\n#define BIT_MASK_USB_MBIST_DONE_V1_8821C 0x3\n#define BIT_USB_MBIST_DONE_V1_8821C(x)                                         \\\n\t(((x) & BIT_MASK_USB_MBIST_DONE_V1_8821C)                              \\\n\t << BIT_SHIFT_USB_MBIST_DONE_V1_8821C)\n#define BITS_USB_MBIST_DONE_V1_8821C                                           \\\n\t(BIT_MASK_USB_MBIST_DONE_V1_8821C << BIT_SHIFT_USB_MBIST_DONE_V1_8821C)\n#define BIT_CLEAR_USB_MBIST_DONE_V1_8821C(x)                                   \\\n\t((x) & (~BITS_USB_MBIST_DONE_V1_8821C))\n#define BIT_GET_USB_MBIST_DONE_V1_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_DONE_V1_8821C) &                          \\\n\t BIT_MASK_USB_MBIST_DONE_V1_8821C)\n#define BIT_SET_USB_MBIST_DONE_V1_8821C(x, v)                                  \\\n\t(BIT_CLEAR_USB_MBIST_DONE_V1_8821C(x) | BIT_USB_MBIST_DONE_V1_8821C(v))\n\n#define BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C 18\n#define BIT_MASK_PCIE_MBIST_DONE_V1_8821C 0x3f\n#define BIT_PCIE_MBIST_DONE_V1_8821C(x)                                        \\\n\t(((x) & BIT_MASK_PCIE_MBIST_DONE_V1_8821C)                             \\\n\t << BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C)\n#define BITS_PCIE_MBIST_DONE_V1_8821C                                          \\\n\t(BIT_MASK_PCIE_MBIST_DONE_V1_8821C                                     \\\n\t << BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C)\n#define BIT_CLEAR_PCIE_MBIST_DONE_V1_8821C(x)                                  \\\n\t((x) & (~BITS_PCIE_MBIST_DONE_V1_8821C))\n#define BIT_GET_PCIE_MBIST_DONE_V1_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C) &                         \\\n\t BIT_MASK_PCIE_MBIST_DONE_V1_8821C)\n#define BIT_SET_PCIE_MBIST_DONE_V1_8821C(x, v)                                 \\\n\t(BIT_CLEAR_PCIE_MBIST_DONE_V1_8821C(x) |                               \\\n\t BIT_PCIE_MBIST_DONE_V1_8821C(v))\n\n#define BIT_SHIFT_MAC_MBIST_DONE_V1_8821C 0\n#define BIT_MASK_MAC_MBIST_DONE_V1_8821C 0x3ffff\n#define BIT_MAC_MBIST_DONE_V1_8821C(x)                                         \\\n\t(((x) & BIT_MASK_MAC_MBIST_DONE_V1_8821C)                              \\\n\t << BIT_SHIFT_MAC_MBIST_DONE_V1_8821C)\n#define BITS_MAC_MBIST_DONE_V1_8821C                                           \\\n\t(BIT_MASK_MAC_MBIST_DONE_V1_8821C << BIT_SHIFT_MAC_MBIST_DONE_V1_8821C)\n#define BIT_CLEAR_MAC_MBIST_DONE_V1_8821C(x)                                   \\\n\t((x) & (~BITS_MAC_MBIST_DONE_V1_8821C))\n#define BIT_GET_MAC_MBIST_DONE_V1_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8821C) &                          \\\n\t BIT_MASK_MAC_MBIST_DONE_V1_8821C)\n#define BIT_SET_MAC_MBIST_DONE_V1_8821C(x, v)                                  \\\n\t(BIT_CLEAR_MAC_MBIST_DONE_V1_8821C(x) | BIT_MAC_MBIST_DONE_V1_8821C(v))\n\n/* 2 REG_MBIST_READ_BIST_RPT_8821C */\n\n#define BIT_SHIFT_MBIST_READ_BIST_RPT_8821C 0\n#define BIT_MASK_MBIST_READ_BIST_RPT_8821C 0xffffffffL\n#define BIT_MBIST_READ_BIST_RPT_8821C(x)                                       \\\n\t(((x) & BIT_MASK_MBIST_READ_BIST_RPT_8821C)                            \\\n\t << BIT_SHIFT_MBIST_READ_BIST_RPT_8821C)\n#define BITS_MBIST_READ_BIST_RPT_8821C                                         \\\n\t(BIT_MASK_MBIST_READ_BIST_RPT_8821C                                    \\\n\t << BIT_SHIFT_MBIST_READ_BIST_RPT_8821C)\n#define BIT_CLEAR_MBIST_READ_BIST_RPT_8821C(x)                                 \\\n\t((x) & (~BITS_MBIST_READ_BIST_RPT_8821C))\n#define BIT_GET_MBIST_READ_BIST_RPT_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_MBIST_READ_BIST_RPT_8821C) &                        \\\n\t BIT_MASK_MBIST_READ_BIST_RPT_8821C)\n#define BIT_SET_MBIST_READ_BIST_RPT_8821C(x, v)                                \\\n\t(BIT_CLEAR_MBIST_READ_BIST_RPT_8821C(x) |                              \\\n\t BIT_MBIST_READ_BIST_RPT_8821C(v))\n\n/* 2 REG_AES_DECRPT_DATA_8821C */\n\n#define BIT_SHIFT_IPS_CFG_ADDR_8821C 0\n#define BIT_MASK_IPS_CFG_ADDR_8821C 0xff\n#define BIT_IPS_CFG_ADDR_8821C(x)                                              \\\n\t(((x) & BIT_MASK_IPS_CFG_ADDR_8821C) << BIT_SHIFT_IPS_CFG_ADDR_8821C)\n#define BITS_IPS_CFG_ADDR_8821C                                                \\\n\t(BIT_MASK_IPS_CFG_ADDR_8821C << BIT_SHIFT_IPS_CFG_ADDR_8821C)\n#define BIT_CLEAR_IPS_CFG_ADDR_8821C(x) ((x) & (~BITS_IPS_CFG_ADDR_8821C))\n#define BIT_GET_IPS_CFG_ADDR_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_IPS_CFG_ADDR_8821C) & BIT_MASK_IPS_CFG_ADDR_8821C)\n#define BIT_SET_IPS_CFG_ADDR_8821C(x, v)                                       \\\n\t(BIT_CLEAR_IPS_CFG_ADDR_8821C(x) | BIT_IPS_CFG_ADDR_8821C(v))\n\n/* 2 REG_AES_DECRPT_CFG_8821C */\n\n#define BIT_SHIFT_IPS_CFG_DATA_8821C 0\n#define BIT_MASK_IPS_CFG_DATA_8821C 0xffffffffL\n#define BIT_IPS_CFG_DATA_8821C(x)                                              \\\n\t(((x) & BIT_MASK_IPS_CFG_DATA_8821C) << BIT_SHIFT_IPS_CFG_DATA_8821C)\n#define BITS_IPS_CFG_DATA_8821C                                                \\\n\t(BIT_MASK_IPS_CFG_DATA_8821C << BIT_SHIFT_IPS_CFG_DATA_8821C)\n#define BIT_CLEAR_IPS_CFG_DATA_8821C(x) ((x) & (~BITS_IPS_CFG_DATA_8821C))\n#define BIT_GET_IPS_CFG_DATA_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_IPS_CFG_DATA_8821C) & BIT_MASK_IPS_CFG_DATA_8821C)\n#define BIT_SET_IPS_CFG_DATA_8821C(x, v)                                       \\\n\t(BIT_CLEAR_IPS_CFG_DATA_8821C(x) | BIT_IPS_CFG_DATA_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_TMETER_8821C */\n#define BIT_TEMP_VALID_8821C BIT(31)\n\n#define BIT_SHIFT_TEMP_VALUE_8821C 24\n#define BIT_MASK_TEMP_VALUE_8821C 0x3f\n#define BIT_TEMP_VALUE_8821C(x)                                                \\\n\t(((x) & BIT_MASK_TEMP_VALUE_8821C) << BIT_SHIFT_TEMP_VALUE_8821C)\n#define BITS_TEMP_VALUE_8821C                                                  \\\n\t(BIT_MASK_TEMP_VALUE_8821C << BIT_SHIFT_TEMP_VALUE_8821C)\n#define BIT_CLEAR_TEMP_VALUE_8821C(x) ((x) & (~BITS_TEMP_VALUE_8821C))\n#define BIT_GET_TEMP_VALUE_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_TEMP_VALUE_8821C) & BIT_MASK_TEMP_VALUE_8821C)\n#define BIT_SET_TEMP_VALUE_8821C(x, v)                                         \\\n\t(BIT_CLEAR_TEMP_VALUE_8821C(x) | BIT_TEMP_VALUE_8821C(v))\n\n#define BIT_SHIFT_REG_TMETER_TIMER_8821C 8\n#define BIT_MASK_REG_TMETER_TIMER_8821C 0xfff\n#define BIT_REG_TMETER_TIMER_8821C(x)                                          \\\n\t(((x) & BIT_MASK_REG_TMETER_TIMER_8821C)                               \\\n\t << BIT_SHIFT_REG_TMETER_TIMER_8821C)\n#define BITS_REG_TMETER_TIMER_8821C                                            \\\n\t(BIT_MASK_REG_TMETER_TIMER_8821C << BIT_SHIFT_REG_TMETER_TIMER_8821C)\n#define BIT_CLEAR_REG_TMETER_TIMER_8821C(x)                                    \\\n\t((x) & (~BITS_REG_TMETER_TIMER_8821C))\n#define BIT_GET_REG_TMETER_TIMER_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_REG_TMETER_TIMER_8821C) &                           \\\n\t BIT_MASK_REG_TMETER_TIMER_8821C)\n#define BIT_SET_REG_TMETER_TIMER_8821C(x, v)                                   \\\n\t(BIT_CLEAR_REG_TMETER_TIMER_8821C(x) | BIT_REG_TMETER_TIMER_8821C(v))\n\n#define BIT_SHIFT_REG_TEMP_DELTA_8821C 2\n#define BIT_MASK_REG_TEMP_DELTA_8821C 0x3f\n#define BIT_REG_TEMP_DELTA_8821C(x)                                            \\\n\t(((x) & BIT_MASK_REG_TEMP_DELTA_8821C)                                 \\\n\t << BIT_SHIFT_REG_TEMP_DELTA_8821C)\n#define BITS_REG_TEMP_DELTA_8821C                                              \\\n\t(BIT_MASK_REG_TEMP_DELTA_8821C << BIT_SHIFT_REG_TEMP_DELTA_8821C)\n#define BIT_CLEAR_REG_TEMP_DELTA_8821C(x) ((x) & (~BITS_REG_TEMP_DELTA_8821C))\n#define BIT_GET_REG_TEMP_DELTA_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_REG_TEMP_DELTA_8821C) &                             \\\n\t BIT_MASK_REG_TEMP_DELTA_8821C)\n#define BIT_SET_REG_TEMP_DELTA_8821C(x, v)                                     \\\n\t(BIT_CLEAR_REG_TEMP_DELTA_8821C(x) | BIT_REG_TEMP_DELTA_8821C(v))\n\n#define BIT_REG_TMETER_EN_8821C BIT(0)\n\n/* 2 REG_OSC_32K_CTRL_8821C */\n\n#define BIT_SHIFT_OSC_32K_CLKGEN_0_8821C 16\n#define BIT_MASK_OSC_32K_CLKGEN_0_8821C 0xffff\n#define BIT_OSC_32K_CLKGEN_0_8821C(x)                                          \\\n\t(((x) & BIT_MASK_OSC_32K_CLKGEN_0_8821C)                               \\\n\t << BIT_SHIFT_OSC_32K_CLKGEN_0_8821C)\n#define BITS_OSC_32K_CLKGEN_0_8821C                                            \\\n\t(BIT_MASK_OSC_32K_CLKGEN_0_8821C << BIT_SHIFT_OSC_32K_CLKGEN_0_8821C)\n#define BIT_CLEAR_OSC_32K_CLKGEN_0_8821C(x)                                    \\\n\t((x) & (~BITS_OSC_32K_CLKGEN_0_8821C))\n#define BIT_GET_OSC_32K_CLKGEN_0_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8821C) &                           \\\n\t BIT_MASK_OSC_32K_CLKGEN_0_8821C)\n#define BIT_SET_OSC_32K_CLKGEN_0_8821C(x, v)                                   \\\n\t(BIT_CLEAR_OSC_32K_CLKGEN_0_8821C(x) | BIT_OSC_32K_CLKGEN_0_8821C(v))\n\n#define BIT_SHIFT_OSC_32K_RES_COMP_8821C 4\n#define BIT_MASK_OSC_32K_RES_COMP_8821C 0x3\n#define BIT_OSC_32K_RES_COMP_8821C(x)                                          \\\n\t(((x) & BIT_MASK_OSC_32K_RES_COMP_8821C)                               \\\n\t << BIT_SHIFT_OSC_32K_RES_COMP_8821C)\n#define BITS_OSC_32K_RES_COMP_8821C                                            \\\n\t(BIT_MASK_OSC_32K_RES_COMP_8821C << BIT_SHIFT_OSC_32K_RES_COMP_8821C)\n#define BIT_CLEAR_OSC_32K_RES_COMP_8821C(x)                                    \\\n\t((x) & (~BITS_OSC_32K_RES_COMP_8821C))\n#define BIT_GET_OSC_32K_RES_COMP_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8821C) &                           \\\n\t BIT_MASK_OSC_32K_RES_COMP_8821C)\n#define BIT_SET_OSC_32K_RES_COMP_8821C(x, v)                                   \\\n\t(BIT_CLEAR_OSC_32K_RES_COMP_8821C(x) | BIT_OSC_32K_RES_COMP_8821C(v))\n\n#define BIT_OSC_32K_OUT_SEL_8821C BIT(3)\n#define BIT_ISO_WL_2_OSC_32K_8821C BIT(1)\n#define BIT_POW_CKGEN_8821C BIT(0)\n\n/* 2 REG_32K_CAL_REG1_8821C */\n#define BIT_CAL_32K_REG_WR_8821C BIT(31)\n#define BIT_CAL_32K_DBG_SEL_8821C BIT(22)\n\n#define BIT_SHIFT_CAL_32K_REG_ADDR_8821C 16\n#define BIT_MASK_CAL_32K_REG_ADDR_8821C 0x3f\n#define BIT_CAL_32K_REG_ADDR_8821C(x)                                          \\\n\t(((x) & BIT_MASK_CAL_32K_REG_ADDR_8821C)                               \\\n\t << BIT_SHIFT_CAL_32K_REG_ADDR_8821C)\n#define BITS_CAL_32K_REG_ADDR_8821C                                            \\\n\t(BIT_MASK_CAL_32K_REG_ADDR_8821C << BIT_SHIFT_CAL_32K_REG_ADDR_8821C)\n#define BIT_CLEAR_CAL_32K_REG_ADDR_8821C(x)                                    \\\n\t((x) & (~BITS_CAL_32K_REG_ADDR_8821C))\n#define BIT_GET_CAL_32K_REG_ADDR_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8821C) &                           \\\n\t BIT_MASK_CAL_32K_REG_ADDR_8821C)\n#define BIT_SET_CAL_32K_REG_ADDR_8821C(x, v)                                   \\\n\t(BIT_CLEAR_CAL_32K_REG_ADDR_8821C(x) | BIT_CAL_32K_REG_ADDR_8821C(v))\n\n#define BIT_SHIFT_CAL_32K_REG_DATA_8821C 0\n#define BIT_MASK_CAL_32K_REG_DATA_8821C 0xffff\n#define BIT_CAL_32K_REG_DATA_8821C(x)                                          \\\n\t(((x) & BIT_MASK_CAL_32K_REG_DATA_8821C)                               \\\n\t << BIT_SHIFT_CAL_32K_REG_DATA_8821C)\n#define BITS_CAL_32K_REG_DATA_8821C                                            \\\n\t(BIT_MASK_CAL_32K_REG_DATA_8821C << BIT_SHIFT_CAL_32K_REG_DATA_8821C)\n#define BIT_CLEAR_CAL_32K_REG_DATA_8821C(x)                                    \\\n\t((x) & (~BITS_CAL_32K_REG_DATA_8821C))\n#define BIT_GET_CAL_32K_REG_DATA_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8821C) &                           \\\n\t BIT_MASK_CAL_32K_REG_DATA_8821C)\n#define BIT_SET_CAL_32K_REG_DATA_8821C(x, v)                                   \\\n\t(BIT_CLEAR_CAL_32K_REG_DATA_8821C(x) | BIT_CAL_32K_REG_DATA_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_C2HEVT_8821C */\n\n#define BIT_SHIFT_C2HEVT_MSG_V1_8821C 0\n#define BIT_MASK_C2HEVT_MSG_V1_8821C 0xffffffffL\n#define BIT_C2HEVT_MSG_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_V1_8821C) << BIT_SHIFT_C2HEVT_MSG_V1_8821C)\n#define BITS_C2HEVT_MSG_V1_8821C                                               \\\n\t(BIT_MASK_C2HEVT_MSG_V1_8821C << BIT_SHIFT_C2HEVT_MSG_V1_8821C)\n#define BIT_CLEAR_C2HEVT_MSG_V1_8821C(x) ((x) & (~BITS_C2HEVT_MSG_V1_8821C))\n#define BIT_GET_C2HEVT_MSG_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8821C) & BIT_MASK_C2HEVT_MSG_V1_8821C)\n#define BIT_SET_C2HEVT_MSG_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_C2HEVT_MSG_V1_8821C(x) | BIT_C2HEVT_MSG_V1_8821C(v))\n\n/* 2 REG_C2HEVT_1_8821C */\n\n#define BIT_SHIFT_C2HEVT_MSG_1_8821C 0\n#define BIT_MASK_C2HEVT_MSG_1_8821C 0xffffffffL\n#define BIT_C2HEVT_MSG_1_8821C(x)                                              \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_1_8821C) << BIT_SHIFT_C2HEVT_MSG_1_8821C)\n#define BITS_C2HEVT_MSG_1_8821C                                                \\\n\t(BIT_MASK_C2HEVT_MSG_1_8821C << BIT_SHIFT_C2HEVT_MSG_1_8821C)\n#define BIT_CLEAR_C2HEVT_MSG_1_8821C(x) ((x) & (~BITS_C2HEVT_MSG_1_8821C))\n#define BIT_GET_C2HEVT_MSG_1_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_1_8821C) & BIT_MASK_C2HEVT_MSG_1_8821C)\n#define BIT_SET_C2HEVT_MSG_1_8821C(x, v)                                       \\\n\t(BIT_CLEAR_C2HEVT_MSG_1_8821C(x) | BIT_C2HEVT_MSG_1_8821C(v))\n\n/* 2 REG_C2HEVT_2_8821C */\n\n#define BIT_SHIFT_C2HEVT_MSG_2_8821C 0\n#define BIT_MASK_C2HEVT_MSG_2_8821C 0xffffffffL\n#define BIT_C2HEVT_MSG_2_8821C(x)                                              \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_2_8821C) << BIT_SHIFT_C2HEVT_MSG_2_8821C)\n#define BITS_C2HEVT_MSG_2_8821C                                                \\\n\t(BIT_MASK_C2HEVT_MSG_2_8821C << BIT_SHIFT_C2HEVT_MSG_2_8821C)\n#define BIT_CLEAR_C2HEVT_MSG_2_8821C(x) ((x) & (~BITS_C2HEVT_MSG_2_8821C))\n#define BIT_GET_C2HEVT_MSG_2_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_2_8821C) & BIT_MASK_C2HEVT_MSG_2_8821C)\n#define BIT_SET_C2HEVT_MSG_2_8821C(x, v)                                       \\\n\t(BIT_CLEAR_C2HEVT_MSG_2_8821C(x) | BIT_C2HEVT_MSG_2_8821C(v))\n\n/* 2 REG_C2HEVT_3_8821C */\n\n#define BIT_SHIFT_C2HEVT_MSG_3_8821C 0\n#define BIT_MASK_C2HEVT_MSG_3_8821C 0xffffffffL\n#define BIT_C2HEVT_MSG_3_8821C(x)                                              \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_3_8821C) << BIT_SHIFT_C2HEVT_MSG_3_8821C)\n#define BITS_C2HEVT_MSG_3_8821C                                                \\\n\t(BIT_MASK_C2HEVT_MSG_3_8821C << BIT_SHIFT_C2HEVT_MSG_3_8821C)\n#define BIT_CLEAR_C2HEVT_MSG_3_8821C(x) ((x) & (~BITS_C2HEVT_MSG_3_8821C))\n#define BIT_GET_C2HEVT_MSG_3_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_3_8821C) & BIT_MASK_C2HEVT_MSG_3_8821C)\n#define BIT_SET_C2HEVT_MSG_3_8821C(x, v)                                       \\\n\t(BIT_CLEAR_C2HEVT_MSG_3_8821C(x) | BIT_C2HEVT_MSG_3_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_SW_DEFINED_PAGE1_8821C */\n\n#define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C 0\n#define BIT_MASK_SW_DEFINED_PAGE1_V1_8821C 0xffffffffL\n#define BIT_SW_DEFINED_PAGE1_V1_8821C(x)                                       \\\n\t(((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8821C)                            \\\n\t << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C)\n#define BITS_SW_DEFINED_PAGE1_V1_8821C                                         \\\n\t(BIT_MASK_SW_DEFINED_PAGE1_V1_8821C                                    \\\n\t << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C)\n#define BIT_CLEAR_SW_DEFINED_PAGE1_V1_8821C(x)                                 \\\n\t((x) & (~BITS_SW_DEFINED_PAGE1_V1_8821C))\n#define BIT_GET_SW_DEFINED_PAGE1_V1_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C) &                        \\\n\t BIT_MASK_SW_DEFINED_PAGE1_V1_8821C)\n#define BIT_SET_SW_DEFINED_PAGE1_V1_8821C(x, v)                                \\\n\t(BIT_CLEAR_SW_DEFINED_PAGE1_V1_8821C(x) |                              \\\n\t BIT_SW_DEFINED_PAGE1_V1_8821C(v))\n\n/* 2 REG_SW_DEFINED_PAGE2_8821C */\n\n#define BIT_SHIFT_SW_DEFINED_PAGE2_8821C 0\n#define BIT_MASK_SW_DEFINED_PAGE2_8821C 0xffffffffL\n#define BIT_SW_DEFINED_PAGE2_8821C(x)                                          \\\n\t(((x) & BIT_MASK_SW_DEFINED_PAGE2_8821C)                               \\\n\t << BIT_SHIFT_SW_DEFINED_PAGE2_8821C)\n#define BITS_SW_DEFINED_PAGE2_8821C                                            \\\n\t(BIT_MASK_SW_DEFINED_PAGE2_8821C << BIT_SHIFT_SW_DEFINED_PAGE2_8821C)\n#define BIT_CLEAR_SW_DEFINED_PAGE2_8821C(x)                                    \\\n\t((x) & (~BITS_SW_DEFINED_PAGE2_8821C))\n#define BIT_GET_SW_DEFINED_PAGE2_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8821C) &                           \\\n\t BIT_MASK_SW_DEFINED_PAGE2_8821C)\n#define BIT_SET_SW_DEFINED_PAGE2_8821C(x, v)                                   \\\n\t(BIT_CLEAR_SW_DEFINED_PAGE2_8821C(x) | BIT_SW_DEFINED_PAGE2_8821C(v))\n\n/* 2 REG_MCUTST_I_8821C */\n\n#define BIT_SHIFT_MCUDMSG_I_8821C 0\n#define BIT_MASK_MCUDMSG_I_8821C 0xffffffffL\n#define BIT_MCUDMSG_I_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_MCUDMSG_I_8821C) << BIT_SHIFT_MCUDMSG_I_8821C)\n#define BITS_MCUDMSG_I_8821C                                                   \\\n\t(BIT_MASK_MCUDMSG_I_8821C << BIT_SHIFT_MCUDMSG_I_8821C)\n#define BIT_CLEAR_MCUDMSG_I_8821C(x) ((x) & (~BITS_MCUDMSG_I_8821C))\n#define BIT_GET_MCUDMSG_I_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MCUDMSG_I_8821C) & BIT_MASK_MCUDMSG_I_8821C)\n#define BIT_SET_MCUDMSG_I_8821C(x, v)                                          \\\n\t(BIT_CLEAR_MCUDMSG_I_8821C(x) | BIT_MCUDMSG_I_8821C(v))\n\n/* 2 REG_MCUTST_II_8821C */\n\n#define BIT_SHIFT_MCUDMSG_II_8821C 0\n#define BIT_MASK_MCUDMSG_II_8821C 0xffffffffL\n#define BIT_MCUDMSG_II_8821C(x)                                                \\\n\t(((x) & BIT_MASK_MCUDMSG_II_8821C) << BIT_SHIFT_MCUDMSG_II_8821C)\n#define BITS_MCUDMSG_II_8821C                                                  \\\n\t(BIT_MASK_MCUDMSG_II_8821C << BIT_SHIFT_MCUDMSG_II_8821C)\n#define BIT_CLEAR_MCUDMSG_II_8821C(x) ((x) & (~BITS_MCUDMSG_II_8821C))\n#define BIT_GET_MCUDMSG_II_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_MCUDMSG_II_8821C) & BIT_MASK_MCUDMSG_II_8821C)\n#define BIT_SET_MCUDMSG_II_8821C(x, v)                                         \\\n\t(BIT_CLEAR_MCUDMSG_II_8821C(x) | BIT_MCUDMSG_II_8821C(v))\n\n/* 2 REG_FMETHR_8821C */\n#define BIT_FMSG_INT_8821C BIT(31)\n\n#define BIT_SHIFT_FW_MSG_8821C 0\n#define BIT_MASK_FW_MSG_8821C 0xffffffffL\n#define BIT_FW_MSG_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_FW_MSG_8821C) << BIT_SHIFT_FW_MSG_8821C)\n#define BITS_FW_MSG_8821C (BIT_MASK_FW_MSG_8821C << BIT_SHIFT_FW_MSG_8821C)\n#define BIT_CLEAR_FW_MSG_8821C(x) ((x) & (~BITS_FW_MSG_8821C))\n#define BIT_GET_FW_MSG_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_FW_MSG_8821C) & BIT_MASK_FW_MSG_8821C)\n#define BIT_SET_FW_MSG_8821C(x, v)                                             \\\n\t(BIT_CLEAR_FW_MSG_8821C(x) | BIT_FW_MSG_8821C(v))\n\n/* 2 REG_HMETFR_8821C */\n\n#define BIT_SHIFT_HRCV_MSG_8821C 24\n#define BIT_MASK_HRCV_MSG_8821C 0xff\n#define BIT_HRCV_MSG_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_HRCV_MSG_8821C) << BIT_SHIFT_HRCV_MSG_8821C)\n#define BITS_HRCV_MSG_8821C                                                    \\\n\t(BIT_MASK_HRCV_MSG_8821C << BIT_SHIFT_HRCV_MSG_8821C)\n#define BIT_CLEAR_HRCV_MSG_8821C(x) ((x) & (~BITS_HRCV_MSG_8821C))\n#define BIT_GET_HRCV_MSG_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_HRCV_MSG_8821C) & BIT_MASK_HRCV_MSG_8821C)\n#define BIT_SET_HRCV_MSG_8821C(x, v)                                           \\\n\t(BIT_CLEAR_HRCV_MSG_8821C(x) | BIT_HRCV_MSG_8821C(v))\n\n#define BIT_INT_BOX3_8821C BIT(3)\n#define BIT_INT_BOX2_8821C BIT(2)\n#define BIT_INT_BOX1_8821C BIT(1)\n#define BIT_INT_BOX0_8821C BIT(0)\n\n/* 2 REG_HMEBOX0_8821C */\n\n#define BIT_SHIFT_HOST_MSG_0_8821C 0\n#define BIT_MASK_HOST_MSG_0_8821C 0xffffffffL\n#define BIT_HOST_MSG_0_8821C(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_0_8821C) << BIT_SHIFT_HOST_MSG_0_8821C)\n#define BITS_HOST_MSG_0_8821C                                                  \\\n\t(BIT_MASK_HOST_MSG_0_8821C << BIT_SHIFT_HOST_MSG_0_8821C)\n#define BIT_CLEAR_HOST_MSG_0_8821C(x) ((x) & (~BITS_HOST_MSG_0_8821C))\n#define BIT_GET_HOST_MSG_0_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_0_8821C) & BIT_MASK_HOST_MSG_0_8821C)\n#define BIT_SET_HOST_MSG_0_8821C(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_0_8821C(x) | BIT_HOST_MSG_0_8821C(v))\n\n/* 2 REG_HMEBOX1_8821C */\n\n#define BIT_SHIFT_HOST_MSG_1_8821C 0\n#define BIT_MASK_HOST_MSG_1_8821C 0xffffffffL\n#define BIT_HOST_MSG_1_8821C(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_1_8821C) << BIT_SHIFT_HOST_MSG_1_8821C)\n#define BITS_HOST_MSG_1_8821C                                                  \\\n\t(BIT_MASK_HOST_MSG_1_8821C << BIT_SHIFT_HOST_MSG_1_8821C)\n#define BIT_CLEAR_HOST_MSG_1_8821C(x) ((x) & (~BITS_HOST_MSG_1_8821C))\n#define BIT_GET_HOST_MSG_1_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_1_8821C) & BIT_MASK_HOST_MSG_1_8821C)\n#define BIT_SET_HOST_MSG_1_8821C(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_1_8821C(x) | BIT_HOST_MSG_1_8821C(v))\n\n/* 2 REG_HMEBOX2_8821C */\n\n#define BIT_SHIFT_HOST_MSG_2_8821C 0\n#define BIT_MASK_HOST_MSG_2_8821C 0xffffffffL\n#define BIT_HOST_MSG_2_8821C(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_2_8821C) << BIT_SHIFT_HOST_MSG_2_8821C)\n#define BITS_HOST_MSG_2_8821C                                                  \\\n\t(BIT_MASK_HOST_MSG_2_8821C << BIT_SHIFT_HOST_MSG_2_8821C)\n#define BIT_CLEAR_HOST_MSG_2_8821C(x) ((x) & (~BITS_HOST_MSG_2_8821C))\n#define BIT_GET_HOST_MSG_2_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_2_8821C) & BIT_MASK_HOST_MSG_2_8821C)\n#define BIT_SET_HOST_MSG_2_8821C(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_2_8821C(x) | BIT_HOST_MSG_2_8821C(v))\n\n/* 2 REG_HMEBOX3_8821C */\n\n#define BIT_SHIFT_HOST_MSG_3_8821C 0\n#define BIT_MASK_HOST_MSG_3_8821C 0xffffffffL\n#define BIT_HOST_MSG_3_8821C(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_3_8821C) << BIT_SHIFT_HOST_MSG_3_8821C)\n#define BITS_HOST_MSG_3_8821C                                                  \\\n\t(BIT_MASK_HOST_MSG_3_8821C << BIT_SHIFT_HOST_MSG_3_8821C)\n#define BIT_CLEAR_HOST_MSG_3_8821C(x) ((x) & (~BITS_HOST_MSG_3_8821C))\n#define BIT_GET_HOST_MSG_3_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_3_8821C) & BIT_MASK_HOST_MSG_3_8821C)\n#define BIT_SET_HOST_MSG_3_8821C(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_3_8821C(x) | BIT_HOST_MSG_3_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_BB_ACCESS_CTRL_8821C */\n\n#define BIT_SHIFT_BB_WRITE_READ_8821C 30\n#define BIT_MASK_BB_WRITE_READ_8821C 0x3\n#define BIT_BB_WRITE_READ_8821C(x)                                             \\\n\t(((x) & BIT_MASK_BB_WRITE_READ_8821C) << BIT_SHIFT_BB_WRITE_READ_8821C)\n#define BITS_BB_WRITE_READ_8821C                                               \\\n\t(BIT_MASK_BB_WRITE_READ_8821C << BIT_SHIFT_BB_WRITE_READ_8821C)\n#define BIT_CLEAR_BB_WRITE_READ_8821C(x) ((x) & (~BITS_BB_WRITE_READ_8821C))\n#define BIT_GET_BB_WRITE_READ_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BB_WRITE_READ_8821C) & BIT_MASK_BB_WRITE_READ_8821C)\n#define BIT_SET_BB_WRITE_READ_8821C(x, v)                                      \\\n\t(BIT_CLEAR_BB_WRITE_READ_8821C(x) | BIT_BB_WRITE_READ_8821C(v))\n\n#define BIT_SHIFT_BB_WRITE_EN_8821C 12\n#define BIT_MASK_BB_WRITE_EN_8821C 0xf\n#define BIT_BB_WRITE_EN_8821C(x)                                               \\\n\t(((x) & BIT_MASK_BB_WRITE_EN_8821C) << BIT_SHIFT_BB_WRITE_EN_8821C)\n#define BITS_BB_WRITE_EN_8821C                                                 \\\n\t(BIT_MASK_BB_WRITE_EN_8821C << BIT_SHIFT_BB_WRITE_EN_8821C)\n#define BIT_CLEAR_BB_WRITE_EN_8821C(x) ((x) & (~BITS_BB_WRITE_EN_8821C))\n#define BIT_GET_BB_WRITE_EN_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_BB_WRITE_EN_8821C) & BIT_MASK_BB_WRITE_EN_8821C)\n#define BIT_SET_BB_WRITE_EN_8821C(x, v)                                        \\\n\t(BIT_CLEAR_BB_WRITE_EN_8821C(x) | BIT_BB_WRITE_EN_8821C(v))\n\n#define BIT_SHIFT_BB_ADDR_8821C 2\n#define BIT_MASK_BB_ADDR_8821C 0x1ff\n#define BIT_BB_ADDR_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_BB_ADDR_8821C) << BIT_SHIFT_BB_ADDR_8821C)\n#define BITS_BB_ADDR_8821C (BIT_MASK_BB_ADDR_8821C << BIT_SHIFT_BB_ADDR_8821C)\n#define BIT_CLEAR_BB_ADDR_8821C(x) ((x) & (~BITS_BB_ADDR_8821C))\n#define BIT_GET_BB_ADDR_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_BB_ADDR_8821C) & BIT_MASK_BB_ADDR_8821C)\n#define BIT_SET_BB_ADDR_8821C(x, v)                                            \\\n\t(BIT_CLEAR_BB_ADDR_8821C(x) | BIT_BB_ADDR_8821C(v))\n\n#define BIT_BB_ERRACC_8821C BIT(0)\n\n/* 2 REG_BB_ACCESS_DATA_8821C */\n\n#define BIT_SHIFT_BB_DATA_8821C 0\n#define BIT_MASK_BB_DATA_8821C 0xffffffffL\n#define BIT_BB_DATA_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_BB_DATA_8821C) << BIT_SHIFT_BB_DATA_8821C)\n#define BITS_BB_DATA_8821C (BIT_MASK_BB_DATA_8821C << BIT_SHIFT_BB_DATA_8821C)\n#define BIT_CLEAR_BB_DATA_8821C(x) ((x) & (~BITS_BB_DATA_8821C))\n#define BIT_GET_BB_DATA_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_BB_DATA_8821C) & BIT_MASK_BB_DATA_8821C)\n#define BIT_SET_BB_DATA_8821C(x, v)                                            \\\n\t(BIT_CLEAR_BB_DATA_8821C(x) | BIT_BB_DATA_8821C(v))\n\n/* 2 REG_HMEBOX_E0_8821C */\n\n#define BIT_SHIFT_HMEBOX_E0_8821C 0\n#define BIT_MASK_HMEBOX_E0_8821C 0xffffffffL\n#define BIT_HMEBOX_E0_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E0_8821C) << BIT_SHIFT_HMEBOX_E0_8821C)\n#define BITS_HMEBOX_E0_8821C                                                   \\\n\t(BIT_MASK_HMEBOX_E0_8821C << BIT_SHIFT_HMEBOX_E0_8821C)\n#define BIT_CLEAR_HMEBOX_E0_8821C(x) ((x) & (~BITS_HMEBOX_E0_8821C))\n#define BIT_GET_HMEBOX_E0_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E0_8821C) & BIT_MASK_HMEBOX_E0_8821C)\n#define BIT_SET_HMEBOX_E0_8821C(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E0_8821C(x) | BIT_HMEBOX_E0_8821C(v))\n\n/* 2 REG_HMEBOX_E1_8821C */\n\n#define BIT_SHIFT_HMEBOX_E1_8821C 0\n#define BIT_MASK_HMEBOX_E1_8821C 0xffffffffL\n#define BIT_HMEBOX_E1_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E1_8821C) << BIT_SHIFT_HMEBOX_E1_8821C)\n#define BITS_HMEBOX_E1_8821C                                                   \\\n\t(BIT_MASK_HMEBOX_E1_8821C << BIT_SHIFT_HMEBOX_E1_8821C)\n#define BIT_CLEAR_HMEBOX_E1_8821C(x) ((x) & (~BITS_HMEBOX_E1_8821C))\n#define BIT_GET_HMEBOX_E1_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E1_8821C) & BIT_MASK_HMEBOX_E1_8821C)\n#define BIT_SET_HMEBOX_E1_8821C(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E1_8821C(x) | BIT_HMEBOX_E1_8821C(v))\n\n/* 2 REG_HMEBOX_E2_8821C */\n\n#define BIT_SHIFT_HMEBOX_E2_8821C 0\n#define BIT_MASK_HMEBOX_E2_8821C 0xffffffffL\n#define BIT_HMEBOX_E2_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E2_8821C) << BIT_SHIFT_HMEBOX_E2_8821C)\n#define BITS_HMEBOX_E2_8821C                                                   \\\n\t(BIT_MASK_HMEBOX_E2_8821C << BIT_SHIFT_HMEBOX_E2_8821C)\n#define BIT_CLEAR_HMEBOX_E2_8821C(x) ((x) & (~BITS_HMEBOX_E2_8821C))\n#define BIT_GET_HMEBOX_E2_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E2_8821C) & BIT_MASK_HMEBOX_E2_8821C)\n#define BIT_SET_HMEBOX_E2_8821C(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E2_8821C(x) | BIT_HMEBOX_E2_8821C(v))\n\n/* 2 REG_HMEBOX_E3_8821C */\n\n#define BIT_SHIFT_HMEBOX_E3_8821C 0\n#define BIT_MASK_HMEBOX_E3_8821C 0xffffffffL\n#define BIT_HMEBOX_E3_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E3_8821C) << BIT_SHIFT_HMEBOX_E3_8821C)\n#define BITS_HMEBOX_E3_8821C                                                   \\\n\t(BIT_MASK_HMEBOX_E3_8821C << BIT_SHIFT_HMEBOX_E3_8821C)\n#define BIT_CLEAR_HMEBOX_E3_8821C(x) ((x) & (~BITS_HMEBOX_E3_8821C))\n#define BIT_GET_HMEBOX_E3_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E3_8821C) & BIT_MASK_HMEBOX_E3_8821C)\n#define BIT_SET_HMEBOX_E3_8821C(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E3_8821C(x) | BIT_HMEBOX_E3_8821C(v))\n\n/* 2 REG_CR_EXT_8821C */\n\n#define BIT_SHIFT_PHY_REQ_DELAY_8821C 24\n#define BIT_MASK_PHY_REQ_DELAY_8821C 0xf\n#define BIT_PHY_REQ_DELAY_8821C(x)                                             \\\n\t(((x) & BIT_MASK_PHY_REQ_DELAY_8821C) << BIT_SHIFT_PHY_REQ_DELAY_8821C)\n#define BITS_PHY_REQ_DELAY_8821C                                               \\\n\t(BIT_MASK_PHY_REQ_DELAY_8821C << BIT_SHIFT_PHY_REQ_DELAY_8821C)\n#define BIT_CLEAR_PHY_REQ_DELAY_8821C(x) ((x) & (~BITS_PHY_REQ_DELAY_8821C))\n#define BIT_GET_PHY_REQ_DELAY_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PHY_REQ_DELAY_8821C) & BIT_MASK_PHY_REQ_DELAY_8821C)\n#define BIT_SET_PHY_REQ_DELAY_8821C(x, v)                                      \\\n\t(BIT_CLEAR_PHY_REQ_DELAY_8821C(x) | BIT_PHY_REQ_DELAY_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n#define BIT_SPD_DOWN_8821C BIT(16)\n\n/* 2 REG_NOT_VALID_8821C */\n\n#define BIT_SHIFT_NETYPE4_8821C 4\n#define BIT_MASK_NETYPE4_8821C 0x3\n#define BIT_NETYPE4_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE4_8821C) << BIT_SHIFT_NETYPE4_8821C)\n#define BITS_NETYPE4_8821C (BIT_MASK_NETYPE4_8821C << BIT_SHIFT_NETYPE4_8821C)\n#define BIT_CLEAR_NETYPE4_8821C(x) ((x) & (~BITS_NETYPE4_8821C))\n#define BIT_GET_NETYPE4_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE4_8821C) & BIT_MASK_NETYPE4_8821C)\n#define BIT_SET_NETYPE4_8821C(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE4_8821C(x) | BIT_NETYPE4_8821C(v))\n\n#define BIT_SHIFT_NETYPE3_8821C 2\n#define BIT_MASK_NETYPE3_8821C 0x3\n#define BIT_NETYPE3_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE3_8821C) << BIT_SHIFT_NETYPE3_8821C)\n#define BITS_NETYPE3_8821C (BIT_MASK_NETYPE3_8821C << BIT_SHIFT_NETYPE3_8821C)\n#define BIT_CLEAR_NETYPE3_8821C(x) ((x) & (~BITS_NETYPE3_8821C))\n#define BIT_GET_NETYPE3_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE3_8821C) & BIT_MASK_NETYPE3_8821C)\n#define BIT_SET_NETYPE3_8821C(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE3_8821C(x) | BIT_NETYPE3_8821C(v))\n\n#define BIT_SHIFT_NETYPE2_8821C 0\n#define BIT_MASK_NETYPE2_8821C 0x3\n#define BIT_NETYPE2_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE2_8821C) << BIT_SHIFT_NETYPE2_8821C)\n#define BITS_NETYPE2_8821C (BIT_MASK_NETYPE2_8821C << BIT_SHIFT_NETYPE2_8821C)\n#define BIT_CLEAR_NETYPE2_8821C(x) ((x) & (~BITS_NETYPE2_8821C))\n#define BIT_GET_NETYPE2_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE2_8821C) & BIT_MASK_NETYPE2_8821C)\n#define BIT_SET_NETYPE2_8821C(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE2_8821C(x) | BIT_NETYPE2_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_FWFF_8821C */\n\n#define BIT_SHIFT_PKTNUM_TH_V1_8821C 24\n#define BIT_MASK_PKTNUM_TH_V1_8821C 0xff\n#define BIT_PKTNUM_TH_V1_8821C(x)                                              \\\n\t(((x) & BIT_MASK_PKTNUM_TH_V1_8821C) << BIT_SHIFT_PKTNUM_TH_V1_8821C)\n#define BITS_PKTNUM_TH_V1_8821C                                                \\\n\t(BIT_MASK_PKTNUM_TH_V1_8821C << BIT_SHIFT_PKTNUM_TH_V1_8821C)\n#define BIT_CLEAR_PKTNUM_TH_V1_8821C(x) ((x) & (~BITS_PKTNUM_TH_V1_8821C))\n#define BIT_GET_PKTNUM_TH_V1_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_PKTNUM_TH_V1_8821C) & BIT_MASK_PKTNUM_TH_V1_8821C)\n#define BIT_SET_PKTNUM_TH_V1_8821C(x, v)                                       \\\n\t(BIT_CLEAR_PKTNUM_TH_V1_8821C(x) | BIT_PKTNUM_TH_V1_8821C(v))\n\n#define BIT_SHIFT_TIMER_TH_8821C 16\n#define BIT_MASK_TIMER_TH_8821C 0xff\n#define BIT_TIMER_TH_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_TIMER_TH_8821C) << BIT_SHIFT_TIMER_TH_8821C)\n#define BITS_TIMER_TH_8821C                                                    \\\n\t(BIT_MASK_TIMER_TH_8821C << BIT_SHIFT_TIMER_TH_8821C)\n#define BIT_CLEAR_TIMER_TH_8821C(x) ((x) & (~BITS_TIMER_TH_8821C))\n#define BIT_GET_TIMER_TH_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TIMER_TH_8821C) & BIT_MASK_TIMER_TH_8821C)\n#define BIT_SET_TIMER_TH_8821C(x, v)                                           \\\n\t(BIT_CLEAR_TIMER_TH_8821C(x) | BIT_TIMER_TH_8821C(v))\n\n#define BIT_SHIFT_RXPKT1ENADDR_8821C 0\n#define BIT_MASK_RXPKT1ENADDR_8821C 0xffff\n#define BIT_RXPKT1ENADDR_8821C(x)                                              \\\n\t(((x) & BIT_MASK_RXPKT1ENADDR_8821C) << BIT_SHIFT_RXPKT1ENADDR_8821C)\n#define BITS_RXPKT1ENADDR_8821C                                                \\\n\t(BIT_MASK_RXPKT1ENADDR_8821C << BIT_SHIFT_RXPKT1ENADDR_8821C)\n#define BIT_CLEAR_RXPKT1ENADDR_8821C(x) ((x) & (~BITS_RXPKT1ENADDR_8821C))\n#define BIT_GET_RXPKT1ENADDR_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXPKT1ENADDR_8821C) & BIT_MASK_RXPKT1ENADDR_8821C)\n#define BIT_SET_RXPKT1ENADDR_8821C(x, v)                                       \\\n\t(BIT_CLEAR_RXPKT1ENADDR_8821C(x) | BIT_RXPKT1ENADDR_8821C(v))\n\n/* 2 REG_RXFF_PTR_V1_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n#define BIT_SHIFT_RXFF0_RDPTR_V2_8821C 0\n#define BIT_MASK_RXFF0_RDPTR_V2_8821C 0x3ffff\n#define BIT_RXFF0_RDPTR_V2_8821C(x)                                            \\\n\t(((x) & BIT_MASK_RXFF0_RDPTR_V2_8821C)                                 \\\n\t << BIT_SHIFT_RXFF0_RDPTR_V2_8821C)\n#define BITS_RXFF0_RDPTR_V2_8821C                                              \\\n\t(BIT_MASK_RXFF0_RDPTR_V2_8821C << BIT_SHIFT_RXFF0_RDPTR_V2_8821C)\n#define BIT_CLEAR_RXFF0_RDPTR_V2_8821C(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8821C))\n#define BIT_GET_RXFF0_RDPTR_V2_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8821C) &                             \\\n\t BIT_MASK_RXFF0_RDPTR_V2_8821C)\n#define BIT_SET_RXFF0_RDPTR_V2_8821C(x, v)                                     \\\n\t(BIT_CLEAR_RXFF0_RDPTR_V2_8821C(x) | BIT_RXFF0_RDPTR_V2_8821C(v))\n\n/* 2 REG_RXFF_WTR_V1_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n#define BIT_SHIFT_RXFF0_WTPTR_V2_8821C 0\n#define BIT_MASK_RXFF0_WTPTR_V2_8821C 0x3ffff\n#define BIT_RXFF0_WTPTR_V2_8821C(x)                                            \\\n\t(((x) & BIT_MASK_RXFF0_WTPTR_V2_8821C)                                 \\\n\t << BIT_SHIFT_RXFF0_WTPTR_V2_8821C)\n#define BITS_RXFF0_WTPTR_V2_8821C                                              \\\n\t(BIT_MASK_RXFF0_WTPTR_V2_8821C << BIT_SHIFT_RXFF0_WTPTR_V2_8821C)\n#define BIT_CLEAR_RXFF0_WTPTR_V2_8821C(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8821C))\n#define BIT_GET_RXFF0_WTPTR_V2_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8821C) &                             \\\n\t BIT_MASK_RXFF0_WTPTR_V2_8821C)\n#define BIT_SET_RXFF0_WTPTR_V2_8821C(x, v)                                     \\\n\t(BIT_CLEAR_RXFF0_WTPTR_V2_8821C(x) | BIT_RXFF0_WTPTR_V2_8821C(v))\n\n/* 2 REG_FE2IMR_8821C */\n#define BIT__FE4ISR__IND_MSK_8821C BIT(29)\n#define BIT_FS_TXSC_DESC_DONE_INT_EN_8821C BIT(28)\n#define BIT_FS_TXSC_BKDONE_INT_EN_8821C BIT(27)\n#define BIT_FS_TXSC_BEDONE_INT_EN_8821C BIT(26)\n#define BIT_FS_TXSC_VIDONE_INT_EN_8821C BIT(25)\n#define BIT_FS_TXSC_VODONE_INT_EN_8821C BIT(24)\n#define BIT_FS_ATIM_MB7_INT_EN_8821C BIT(23)\n#define BIT_FS_ATIM_MB6_INT_EN_8821C BIT(22)\n#define BIT_FS_ATIM_MB5_INT_EN_8821C BIT(21)\n#define BIT_FS_ATIM_MB4_INT_EN_8821C BIT(20)\n#define BIT_FS_ATIM_MB3_INT_EN_8821C BIT(19)\n#define BIT_FS_ATIM_MB2_INT_EN_8821C BIT(18)\n#define BIT_FS_ATIM_MB1_INT_EN_8821C BIT(17)\n#define BIT_FS_ATIM_MB0_INT_EN_8821C BIT(16)\n#define BIT_FS_TBTT4INT_EN_8821C BIT(11)\n#define BIT_FS_TBTT3INT_EN_8821C BIT(10)\n#define BIT_FS_TBTT2INT_EN_8821C BIT(9)\n#define BIT_FS_TBTT1INT_EN_8821C BIT(8)\n#define BIT_FS_TBTT0_MB7INT_EN_8821C BIT(7)\n#define BIT_FS_TBTT0_MB6INT_EN_8821C BIT(6)\n#define BIT_FS_TBTT0_MB5INT_EN_8821C BIT(5)\n#define BIT_FS_TBTT0_MB4INT_EN_8821C BIT(4)\n#define BIT_FS_TBTT0_MB3INT_EN_8821C BIT(3)\n#define BIT_FS_TBTT0_MB2INT_EN_8821C BIT(2)\n#define BIT_FS_TBTT0_MB1INT_EN_8821C BIT(1)\n#define BIT_FS_TBTT0_INT_EN_8821C BIT(0)\n\n/* 2 REG_FE2ISR_8821C */\n#define BIT__FE4ISR__IND_INT_8821C BIT(29)\n#define BIT_FS_TXSC_DESC_DONE_INT_8821C BIT(28)\n#define BIT_FS_TXSC_BKDONE_INT_8821C BIT(27)\n#define BIT_FS_TXSC_BEDONE_INT_8821C BIT(26)\n#define BIT_FS_TXSC_VIDONE_INT_8821C BIT(25)\n#define BIT_FS_TXSC_VODONE_INT_8821C BIT(24)\n#define BIT_FS_ATIM_MB7_INT_8821C BIT(23)\n#define BIT_FS_ATIM_MB6_INT_8821C BIT(22)\n#define BIT_FS_ATIM_MB5_INT_8821C BIT(21)\n#define BIT_FS_ATIM_MB4_INT_8821C BIT(20)\n#define BIT_FS_ATIM_MB3_INT_8821C BIT(19)\n#define BIT_FS_ATIM_MB2_INT_8821C BIT(18)\n#define BIT_FS_ATIM_MB1_INT_8821C BIT(17)\n#define BIT_FS_ATIM_MB0_INT_8821C BIT(16)\n#define BIT_FS_TBTT4INT_8821C BIT(11)\n#define BIT_FS_TBTT3INT_8821C BIT(10)\n#define BIT_FS_TBTT2INT_8821C BIT(9)\n#define BIT_FS_TBTT1INT_8821C BIT(8)\n#define BIT_FS_TBTT0_MB7INT_8821C BIT(7)\n#define BIT_FS_TBTT0_MB6INT_8821C BIT(6)\n#define BIT_FS_TBTT0_MB5INT_8821C BIT(5)\n#define BIT_FS_TBTT0_MB4INT_8821C BIT(4)\n#define BIT_FS_TBTT0_MB3INT_8821C BIT(3)\n#define BIT_FS_TBTT0_MB2INT_8821C BIT(2)\n#define BIT_FS_TBTT0_MB1INT_8821C BIT(1)\n#define BIT_FS_TBTT0_INT_8821C BIT(0)\n\n/* 2 REG_FE3IMR_8821C */\n#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN_8821C BIT(31)\n#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN_8821C BIT(30)\n#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN_8821C BIT(29)\n#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN_8821C BIT(28)\n#define BIT_FS_BCNDMA4_INT_EN_8821C BIT(27)\n#define BIT_FS_BCNDMA3_INT_EN_8821C BIT(26)\n#define BIT_FS_BCNDMA2_INT_EN_8821C BIT(25)\n#define BIT_FS_BCNDMA1_INT_EN_8821C BIT(24)\n#define BIT_FS_BCNDMA0_MB7_INT_EN_8821C BIT(23)\n#define BIT_FS_BCNDMA0_MB6_INT_EN_8821C BIT(22)\n#define BIT_FS_BCNDMA0_MB5_INT_EN_8821C BIT(21)\n#define BIT_FS_BCNDMA0_MB4_INT_EN_8821C BIT(20)\n#define BIT_FS_BCNDMA0_MB3_INT_EN_8821C BIT(19)\n#define BIT_FS_BCNDMA0_MB2_INT_EN_8821C BIT(18)\n#define BIT_FS_BCNDMA0_MB1_INT_EN_8821C BIT(17)\n#define BIT_FS_BCNDMA0_INT_EN_8821C BIT(16)\n#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8821C BIT(15)\n#define BIT_FS_BCNERLY4_INT_EN_8821C BIT(11)\n#define BIT_FS_BCNERLY3_INT_EN_8821C BIT(10)\n#define BIT_FS_BCNERLY2_INT_EN_8821C BIT(9)\n#define BIT_FS_BCNERLY1_INT_EN_8821C BIT(8)\n#define BIT_FS_BCNERLY0_MB7INT_EN_8821C BIT(7)\n#define BIT_FS_BCNERLY0_MB6INT_EN_8821C BIT(6)\n#define BIT_FS_BCNERLY0_MB5INT_EN_8821C BIT(5)\n#define BIT_FS_BCNERLY0_MB4INT_EN_8821C BIT(4)\n#define BIT_FS_BCNERLY0_MB3INT_EN_8821C BIT(3)\n#define BIT_FS_BCNERLY0_MB2INT_EN_8821C BIT(2)\n#define BIT_FS_BCNERLY0_MB1INT_EN_8821C BIT(1)\n#define BIT_FS_BCNERLY0_INT_EN_8821C BIT(0)\n\n/* 2 REG_FE3ISR_8821C */\n#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT_8821C BIT(31)\n#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT_8821C BIT(30)\n#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT_8821C BIT(29)\n#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT_8821C BIT(28)\n#define BIT_FS_BCNDMA4_INT_8821C BIT(27)\n#define BIT_FS_BCNDMA3_INT_8821C BIT(26)\n#define BIT_FS_BCNDMA2_INT_8821C BIT(25)\n#define BIT_FS_BCNDMA1_INT_8821C BIT(24)\n#define BIT_FS_BCNDMA0_MB7_INT_8821C BIT(23)\n#define BIT_FS_BCNDMA0_MB6_INT_8821C BIT(22)\n#define BIT_FS_BCNDMA0_MB5_INT_8821C BIT(21)\n#define BIT_FS_BCNDMA0_MB4_INT_8821C BIT(20)\n#define BIT_FS_BCNDMA0_MB3_INT_8821C BIT(19)\n#define BIT_FS_BCNDMA0_MB2_INT_8821C BIT(18)\n#define BIT_FS_BCNDMA0_MB1_INT_8821C BIT(17)\n#define BIT_FS_BCNDMA0_INT_8821C BIT(16)\n#define BIT_FS_MTI_BCNIVLEAR_INT_8821C BIT(15)\n#define BIT_FS_BCNERLY4_INT_8821C BIT(11)\n#define BIT_FS_BCNERLY3_INT_8821C BIT(10)\n#define BIT_FS_BCNERLY2_INT_8821C BIT(9)\n#define BIT_FS_BCNERLY1_INT_8821C BIT(8)\n#define BIT_FS_BCNERLY0_MB7INT_8821C BIT(7)\n#define BIT_FS_BCNERLY0_MB6INT_8821C BIT(6)\n#define BIT_FS_BCNERLY0_MB5INT_8821C BIT(5)\n#define BIT_FS_BCNERLY0_MB4INT_8821C BIT(4)\n#define BIT_FS_BCNERLY0_MB3INT_8821C BIT(3)\n#define BIT_FS_BCNERLY0_MB2INT_8821C BIT(2)\n#define BIT_FS_BCNERLY0_MB1INT_8821C BIT(1)\n#define BIT_FS_BCNERLY0_INT_8821C BIT(0)\n\n/* 2 REG_FE4IMR_8821C */\n#define BIT_FS_CLI3_TXPKTIN_INT_EN_8821C BIT(19)\n#define BIT_FS_CLI2_TXPKTIN_INT_EN_8821C BIT(18)\n#define BIT_FS_CLI1_TXPKTIN_INT_EN_8821C BIT(17)\n#define BIT_FS_CLI0_TXPKTIN_INT_EN_8821C BIT(16)\n#define BIT_FS_CLI3_RX_UMD0_INT_EN_8821C BIT(15)\n#define BIT_FS_CLI3_RX_UMD1_INT_EN_8821C BIT(14)\n#define BIT_FS_CLI3_RX_BMD0_INT_EN_8821C BIT(13)\n#define BIT_FS_CLI3_RX_BMD1_INT_EN_8821C BIT(12)\n#define BIT_FS_CLI2_RX_UMD0_INT_EN_8821C BIT(11)\n#define BIT_FS_CLI2_RX_UMD1_INT_EN_8821C BIT(10)\n#define BIT_FS_CLI2_RX_BMD0_INT_EN_8821C BIT(9)\n#define BIT_FS_CLI2_RX_BMD1_INT_EN_8821C BIT(8)\n#define BIT_FS_CLI1_RX_UMD0_INT_EN_8821C BIT(7)\n#define BIT_FS_CLI1_RX_UMD1_INT_EN_8821C BIT(6)\n#define BIT_FS_CLI1_RX_BMD0_INT_EN_8821C BIT(5)\n#define BIT_FS_CLI1_RX_BMD1_INT_EN_8821C BIT(4)\n#define BIT_FS_CLI0_RX_UMD0_INT_EN_8821C BIT(3)\n#define BIT_FS_CLI0_RX_UMD1_INT_EN_8821C BIT(2)\n#define BIT_FS_CLI0_RX_BMD0_INT_EN_8821C BIT(1)\n#define BIT_FS_CLI0_RX_BMD1_INT_EN_8821C BIT(0)\n\n/* 2 REG_FE4ISR_8821C */\n#define BIT_FS_CLI3_TXPKTIN_INT_8821C BIT(19)\n#define BIT_FS_CLI2_TXPKTIN_INT_8821C BIT(18)\n#define BIT_FS_CLI1_TXPKTIN_INT_8821C BIT(17)\n#define BIT_FS_CLI0_TXPKTIN_INT_8821C BIT(16)\n#define BIT_FS_CLI3_RX_UMD0_INT_8821C BIT(15)\n#define BIT_FS_CLI3_RX_UMD1_INT_8821C BIT(14)\n#define BIT_FS_CLI3_RX_BMD0_INT_8821C BIT(13)\n#define BIT_FS_CLI3_RX_BMD1_INT_8821C BIT(12)\n#define BIT_FS_CLI2_RX_UMD0_INT_8821C BIT(11)\n#define BIT_FS_CLI2_RX_UMD1_INT_8821C BIT(10)\n#define BIT_FS_CLI2_RX_BMD0_INT_8821C BIT(9)\n#define BIT_FS_CLI2_RX_BMD1_INT_8821C BIT(8)\n#define BIT_FS_CLI1_RX_UMD0_INT_8821C BIT(7)\n#define BIT_FS_CLI1_RX_UMD1_INT_8821C BIT(6)\n#define BIT_FS_CLI1_RX_BMD0_INT_8821C BIT(5)\n#define BIT_FS_CLI1_RX_BMD1_INT_8821C BIT(4)\n#define BIT_FS_CLI0_RX_UMD0_INT_8821C BIT(3)\n#define BIT_FS_CLI0_RX_UMD1_INT_8821C BIT(2)\n#define BIT_FS_CLI0_RX_BMD0_INT_8821C BIT(1)\n#define BIT_FS_CLI0_RX_BMD1_INT_8821C BIT(0)\n\n/* 2 REG_FT1IMR_8821C */\n#define BIT__FT2ISR__IND_MSK_8821C BIT(30)\n#define BIT_FTM_PTT_INT_EN_8821C BIT(29)\n#define BIT_RXFTMREQ_INT_EN_8821C BIT(28)\n#define BIT_RXFTM_INT_EN_8821C BIT(27)\n#define BIT_TXFTM_INT_EN_8821C BIT(26)\n#define BIT_FS_H2C_CMD_OK_INT_EN_8821C BIT(25)\n#define BIT_FS_H2C_CMD_FULL_INT_EN_8821C BIT(24)\n#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8821C BIT(23)\n#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8821C BIT(22)\n#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8821C BIT(21)\n#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8821C BIT(20)\n#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8821C BIT(19)\n#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8821C BIT(18)\n#define BIT_FS_CTWEND2_INT_EN_8821C BIT(17)\n#define BIT_FS_CTWEND1_INT_EN_8821C BIT(16)\n#define BIT_FS_CTWEND0_INT_EN_8821C BIT(15)\n#define BIT_FS_TX_NULL1_INT_EN_8821C BIT(14)\n#define BIT_FS_TX_NULL0_INT_EN_8821C BIT(13)\n#define BIT_FS_TSF_BIT32_TOGGLE_EN_8821C BIT(12)\n#define BIT_FS_P2P_RFON2_INT_EN_8821C BIT(11)\n#define BIT_FS_P2P_RFOFF2_INT_EN_8821C BIT(10)\n#define BIT_FS_P2P_RFON1_INT_EN_8821C BIT(9)\n#define BIT_FS_P2P_RFOFF1_INT_EN_8821C BIT(8)\n#define BIT_FS_P2P_RFON0_INT_EN_8821C BIT(7)\n#define BIT_FS_P2P_RFOFF0_INT_EN_8821C BIT(6)\n#define BIT_FS_RX_UAPSDMD1_EN_8821C BIT(5)\n#define BIT_FS_RX_UAPSDMD0_EN_8821C BIT(4)\n#define BIT_FS_TRIGGER_PKT_EN_8821C BIT(3)\n#define BIT_FS_EOSP_INT_EN_8821C BIT(2)\n#define BIT_FS_RPWM2_INT_EN_8821C BIT(1)\n#define BIT_FS_RPWM_INT_EN_8821C BIT(0)\n\n/* 2 REG_FT1ISR_8821C */\n#define BIT__FT2ISR__IND_INT_8821C BIT(30)\n#define BIT_FTM_PTT_INT_8821C BIT(29)\n#define BIT_RXFTMREQ_INT_8821C BIT(28)\n#define BIT_RXFTM_INT_8821C BIT(27)\n#define BIT_TXFTM_INT_8821C BIT(26)\n#define BIT_FS_H2C_CMD_OK_INT_8821C BIT(25)\n#define BIT_FS_H2C_CMD_FULL_INT_8821C BIT(24)\n#define BIT_FS_MACID_PWRCHANGE5_INT_8821C BIT(23)\n#define BIT_FS_MACID_PWRCHANGE4_INT_8821C BIT(22)\n#define BIT_FS_MACID_PWRCHANGE3_INT_8821C BIT(21)\n#define BIT_FS_MACID_PWRCHANGE2_INT_8821C BIT(20)\n#define BIT_FS_MACID_PWRCHANGE1_INT_8821C BIT(19)\n#define BIT_FS_MACID_PWRCHANGE0_INT_8821C BIT(18)\n#define BIT_FS_CTWEND2_INT_8821C BIT(17)\n#define BIT_FS_CTWEND1_INT_8821C BIT(16)\n#define BIT_FS_CTWEND0_INT_8821C BIT(15)\n#define BIT_FS_TX_NULL1_INT_8821C BIT(14)\n#define BIT_FS_TX_NULL0_INT_8821C BIT(13)\n#define BIT_FS_TSF_BIT32_TOGGLE_INT_8821C BIT(12)\n#define BIT_FS_P2P_RFON2_INT_8821C BIT(11)\n#define BIT_FS_P2P_RFOFF2_INT_8821C BIT(10)\n#define BIT_FS_P2P_RFON1_INT_8821C BIT(9)\n#define BIT_FS_P2P_RFOFF1_INT_8821C BIT(8)\n#define BIT_FS_P2P_RFON0_INT_8821C BIT(7)\n#define BIT_FS_P2P_RFOFF0_INT_8821C BIT(6)\n#define BIT_FS_RX_UAPSDMD1_INT_8821C BIT(5)\n#define BIT_FS_RX_UAPSDMD0_INT_8821C BIT(4)\n#define BIT_FS_TRIGGER_PKT_INT_8821C BIT(3)\n#define BIT_FS_EOSP_INT_8821C BIT(2)\n#define BIT_FS_RPWM2_INT_8821C BIT(1)\n#define BIT_FS_RPWM_INT_8821C BIT(0)\n\n/* 2 REG_SPWR0_8821C */\n\n#define BIT_SHIFT_MID_31TO0_8821C 0\n#define BIT_MASK_MID_31TO0_8821C 0xffffffffL\n#define BIT_MID_31TO0_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_MID_31TO0_8821C) << BIT_SHIFT_MID_31TO0_8821C)\n#define BITS_MID_31TO0_8821C                                                   \\\n\t(BIT_MASK_MID_31TO0_8821C << BIT_SHIFT_MID_31TO0_8821C)\n#define BIT_CLEAR_MID_31TO0_8821C(x) ((x) & (~BITS_MID_31TO0_8821C))\n#define BIT_GET_MID_31TO0_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MID_31TO0_8821C) & BIT_MASK_MID_31TO0_8821C)\n#define BIT_SET_MID_31TO0_8821C(x, v)                                          \\\n\t(BIT_CLEAR_MID_31TO0_8821C(x) | BIT_MID_31TO0_8821C(v))\n\n/* 2 REG_SPWR1_8821C */\n\n#define BIT_SHIFT_MID_63TO32_8821C 0\n#define BIT_MASK_MID_63TO32_8821C 0xffffffffL\n#define BIT_MID_63TO32_8821C(x)                                                \\\n\t(((x) & BIT_MASK_MID_63TO32_8821C) << BIT_SHIFT_MID_63TO32_8821C)\n#define BITS_MID_63TO32_8821C                                                  \\\n\t(BIT_MASK_MID_63TO32_8821C << BIT_SHIFT_MID_63TO32_8821C)\n#define BIT_CLEAR_MID_63TO32_8821C(x) ((x) & (~BITS_MID_63TO32_8821C))\n#define BIT_GET_MID_63TO32_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_MID_63TO32_8821C) & BIT_MASK_MID_63TO32_8821C)\n#define BIT_SET_MID_63TO32_8821C(x, v)                                         \\\n\t(BIT_CLEAR_MID_63TO32_8821C(x) | BIT_MID_63TO32_8821C(v))\n\n/* 2 REG_SPWR2_8821C */\n\n#define BIT_SHIFT_MID_95O64_8821C 0\n#define BIT_MASK_MID_95O64_8821C 0xffffffffL\n#define BIT_MID_95O64_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_MID_95O64_8821C) << BIT_SHIFT_MID_95O64_8821C)\n#define BITS_MID_95O64_8821C                                                   \\\n\t(BIT_MASK_MID_95O64_8821C << BIT_SHIFT_MID_95O64_8821C)\n#define BIT_CLEAR_MID_95O64_8821C(x) ((x) & (~BITS_MID_95O64_8821C))\n#define BIT_GET_MID_95O64_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MID_95O64_8821C) & BIT_MASK_MID_95O64_8821C)\n#define BIT_SET_MID_95O64_8821C(x, v)                                          \\\n\t(BIT_CLEAR_MID_95O64_8821C(x) | BIT_MID_95O64_8821C(v))\n\n/* 2 REG_SPWR3_8821C */\n\n#define BIT_SHIFT_MID_127TO96_8821C 0\n#define BIT_MASK_MID_127TO96_8821C 0xffffffffL\n#define BIT_MID_127TO96_8821C(x)                                               \\\n\t(((x) & BIT_MASK_MID_127TO96_8821C) << BIT_SHIFT_MID_127TO96_8821C)\n#define BITS_MID_127TO96_8821C                                                 \\\n\t(BIT_MASK_MID_127TO96_8821C << BIT_SHIFT_MID_127TO96_8821C)\n#define BIT_CLEAR_MID_127TO96_8821C(x) ((x) & (~BITS_MID_127TO96_8821C))\n#define BIT_GET_MID_127TO96_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_MID_127TO96_8821C) & BIT_MASK_MID_127TO96_8821C)\n#define BIT_SET_MID_127TO96_8821C(x, v)                                        \\\n\t(BIT_CLEAR_MID_127TO96_8821C(x) | BIT_MID_127TO96_8821C(v))\n\n/* 2 REG_POWSEQ_8821C */\n\n#define BIT_SHIFT_SEQNUM_MID_8821C 16\n#define BIT_MASK_SEQNUM_MID_8821C 0xffff\n#define BIT_SEQNUM_MID_8821C(x)                                                \\\n\t(((x) & BIT_MASK_SEQNUM_MID_8821C) << BIT_SHIFT_SEQNUM_MID_8821C)\n#define BITS_SEQNUM_MID_8821C                                                  \\\n\t(BIT_MASK_SEQNUM_MID_8821C << BIT_SHIFT_SEQNUM_MID_8821C)\n#define BIT_CLEAR_SEQNUM_MID_8821C(x) ((x) & (~BITS_SEQNUM_MID_8821C))\n#define BIT_GET_SEQNUM_MID_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_SEQNUM_MID_8821C) & BIT_MASK_SEQNUM_MID_8821C)\n#define BIT_SET_SEQNUM_MID_8821C(x, v)                                         \\\n\t(BIT_CLEAR_SEQNUM_MID_8821C(x) | BIT_SEQNUM_MID_8821C(v))\n\n#define BIT_SHIFT_REF_MID_8821C 0\n#define BIT_MASK_REF_MID_8821C 0x7f\n#define BIT_REF_MID_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_REF_MID_8821C) << BIT_SHIFT_REF_MID_8821C)\n#define BITS_REF_MID_8821C (BIT_MASK_REF_MID_8821C << BIT_SHIFT_REF_MID_8821C)\n#define BIT_CLEAR_REF_MID_8821C(x) ((x) & (~BITS_REF_MID_8821C))\n#define BIT_GET_REF_MID_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_REF_MID_8821C) & BIT_MASK_REF_MID_8821C)\n#define BIT_SET_REF_MID_8821C(x, v)                                            \\\n\t(BIT_CLEAR_REF_MID_8821C(x) | BIT_REF_MID_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_TC7_CTRL_V1_8821C */\n#define BIT_TC7INT_EN_8821C BIT(26)\n#define BIT_TC7MODE_8821C BIT(25)\n#define BIT_TC7EN_8821C BIT(24)\n\n#define BIT_SHIFT_TC7DATA_8821C 0\n#define BIT_MASK_TC7DATA_8821C 0xffffff\n#define BIT_TC7DATA_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_TC7DATA_8821C) << BIT_SHIFT_TC7DATA_8821C)\n#define BITS_TC7DATA_8821C (BIT_MASK_TC7DATA_8821C << BIT_SHIFT_TC7DATA_8821C)\n#define BIT_CLEAR_TC7DATA_8821C(x) ((x) & (~BITS_TC7DATA_8821C))\n#define BIT_GET_TC7DATA_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC7DATA_8821C) & BIT_MASK_TC7DATA_8821C)\n#define BIT_SET_TC7DATA_8821C(x, v)                                            \\\n\t(BIT_CLEAR_TC7DATA_8821C(x) | BIT_TC7DATA_8821C(v))\n\n/* 2 REG_TC8_CTRL_V1_8821C */\n#define BIT_TC8INT_EN_8821C BIT(26)\n#define BIT_TC8MODE_8821C BIT(25)\n#define BIT_TC8EN_8821C BIT(24)\n\n#define BIT_SHIFT_TC8DATA_8821C 0\n#define BIT_MASK_TC8DATA_8821C 0xffffff\n#define BIT_TC8DATA_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_TC8DATA_8821C) << BIT_SHIFT_TC8DATA_8821C)\n#define BITS_TC8DATA_8821C (BIT_MASK_TC8DATA_8821C << BIT_SHIFT_TC8DATA_8821C)\n#define BIT_CLEAR_TC8DATA_8821C(x) ((x) & (~BITS_TC8DATA_8821C))\n#define BIT_GET_TC8DATA_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC8DATA_8821C) & BIT_MASK_TC8DATA_8821C)\n#define BIT_SET_TC8DATA_8821C(x, v)                                            \\\n\t(BIT_CLEAR_TC8DATA_8821C(x) | BIT_TC8DATA_8821C(v))\n\n/* 2 REG_RX_BCN_TBTT_ITVL0_8821C */\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C 24\n#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C 0xff\n#define BIT_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x)                                  \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C)                       \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C)\n#define BITS_RX_BCN_TBTT_ITVL_CLIENT2_8821C                                    \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C                               \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x)                            \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2_8821C))\n#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x)                              \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C) &                   \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C)\n#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x, v)                           \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x) |                         \\\n\t BIT_RX_BCN_TBTT_ITVL_CLIENT2_8821C(v))\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C 16\n#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C 0xff\n#define BIT_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x)                                  \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C)                       \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C)\n#define BITS_RX_BCN_TBTT_ITVL_CLIENT1_8821C                                    \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C                               \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x)                            \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1_8821C))\n#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x)                              \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C) &                   \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C)\n#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x, v)                           \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x) |                         \\\n\t BIT_RX_BCN_TBTT_ITVL_CLIENT1_8821C(v))\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C 8\n#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C 0xff\n#define BIT_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x)                                  \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C)                       \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C)\n#define BITS_RX_BCN_TBTT_ITVL_CLIENT0_8821C                                    \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C                               \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x)                            \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0_8821C))\n#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x)                              \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C) &                   \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C)\n#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x, v)                           \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x) |                         \\\n\t BIT_RX_BCN_TBTT_ITVL_CLIENT0_8821C(v))\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C 0\n#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C 0xff\n#define BIT_RX_BCN_TBTT_ITVL_PORT0_8821C(x)                                    \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C)                         \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C)\n#define BITS_RX_BCN_TBTT_ITVL_PORT0_8821C                                      \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C                                 \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8821C(x)                              \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0_8821C))\n#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0_8821C(x)                                \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C) &                     \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C)\n#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0_8821C(x, v)                             \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8821C(x) |                           \\\n\t BIT_RX_BCN_TBTT_ITVL_PORT0_8821C(v))\n\n/* 2 REG_RX_BCN_TBTT_ITVL1_8821C */\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C 0\n#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C 0xff\n#define BIT_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x)                                  \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C)                       \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C)\n#define BITS_RX_BCN_TBTT_ITVL_CLIENT3_8821C                                    \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C                               \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x)                            \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3_8821C))\n#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x)                              \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C) &                   \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C)\n#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x, v)                           \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x) |                         \\\n\t BIT_RX_BCN_TBTT_ITVL_CLIENT3_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_IO_WRAP_ERR_FLAG_8821C */\n#define BIT_IO_WRAP_ERR_8821C BIT(0)\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_SPEED_SENSOR_8821C */\n#define BIT_DSS_1_RST_N_8821C BIT(31)\n#define BIT_DSS_1_SPEED_EN_8821C BIT(30)\n#define BIT_DSS_1_WIRE_SEL_8821C BIT(29)\n#define BIT_DSS_ENCLK_8821C BIT(28)\n\n#define BIT_SHIFT_DSS_1_RO_SEL_8821C 24\n#define BIT_MASK_DSS_1_RO_SEL_8821C 0x7\n#define BIT_DSS_1_RO_SEL_8821C(x)                                              \\\n\t(((x) & BIT_MASK_DSS_1_RO_SEL_8821C) << BIT_SHIFT_DSS_1_RO_SEL_8821C)\n#define BITS_DSS_1_RO_SEL_8821C                                                \\\n\t(BIT_MASK_DSS_1_RO_SEL_8821C << BIT_SHIFT_DSS_1_RO_SEL_8821C)\n#define BIT_CLEAR_DSS_1_RO_SEL_8821C(x) ((x) & (~BITS_DSS_1_RO_SEL_8821C))\n#define BIT_GET_DSS_1_RO_SEL_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DSS_1_RO_SEL_8821C) & BIT_MASK_DSS_1_RO_SEL_8821C)\n#define BIT_SET_DSS_1_RO_SEL_8821C(x, v)                                       \\\n\t(BIT_CLEAR_DSS_1_RO_SEL_8821C(x) | BIT_DSS_1_RO_SEL_8821C(v))\n\n#define BIT_SHIFT_DSS_1_DATA_IN_8821C 0\n#define BIT_MASK_DSS_1_DATA_IN_8821C 0xfffff\n#define BIT_DSS_1_DATA_IN_8821C(x)                                             \\\n\t(((x) & BIT_MASK_DSS_1_DATA_IN_8821C) << BIT_SHIFT_DSS_1_DATA_IN_8821C)\n#define BITS_DSS_1_DATA_IN_8821C                                               \\\n\t(BIT_MASK_DSS_1_DATA_IN_8821C << BIT_SHIFT_DSS_1_DATA_IN_8821C)\n#define BIT_CLEAR_DSS_1_DATA_IN_8821C(x) ((x) & (~BITS_DSS_1_DATA_IN_8821C))\n#define BIT_GET_DSS_1_DATA_IN_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_DSS_1_DATA_IN_8821C) & BIT_MASK_DSS_1_DATA_IN_8821C)\n#define BIT_SET_DSS_1_DATA_IN_8821C(x, v)                                      \\\n\t(BIT_CLEAR_DSS_1_DATA_IN_8821C(x) | BIT_DSS_1_DATA_IN_8821C(v))\n\n/* 2 REG_SPEED_SENSOR1_8821C */\n#define BIT_DSS_1_READY_8821C BIT(31)\n#define BIT_DSS_1_WSORT_GO_8821C BIT(30)\n\n#define BIT_SHIFT_DSS_1_COUNT_OUT_8821C 0\n#define BIT_MASK_DSS_1_COUNT_OUT_8821C 0xfffff\n#define BIT_DSS_1_COUNT_OUT_8821C(x)                                           \\\n\t(((x) & BIT_MASK_DSS_1_COUNT_OUT_8821C)                                \\\n\t << BIT_SHIFT_DSS_1_COUNT_OUT_8821C)\n#define BITS_DSS_1_COUNT_OUT_8821C                                             \\\n\t(BIT_MASK_DSS_1_COUNT_OUT_8821C << BIT_SHIFT_DSS_1_COUNT_OUT_8821C)\n#define BIT_CLEAR_DSS_1_COUNT_OUT_8821C(x) ((x) & (~BITS_DSS_1_COUNT_OUT_8821C))\n#define BIT_GET_DSS_1_COUNT_OUT_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DSS_1_COUNT_OUT_8821C) &                            \\\n\t BIT_MASK_DSS_1_COUNT_OUT_8821C)\n#define BIT_SET_DSS_1_COUNT_OUT_8821C(x, v)                                    \\\n\t(BIT_CLEAR_DSS_1_COUNT_OUT_8821C(x) | BIT_DSS_1_COUNT_OUT_8821C(v))\n\n/* 2 REG_SPEED_SENSOR2_8821C */\n#define BIT_DSS_2_RST_N_8821C BIT(31)\n#define BIT_DSS_2_SPEED_EN_8821C BIT(30)\n#define BIT_DSS_2_WIRE_SEL_8821C BIT(29)\n#define BIT_DSS_ENCLK_8821C BIT(28)\n\n#define BIT_SHIFT_DSS_2_RO_SEL_8821C 24\n#define BIT_MASK_DSS_2_RO_SEL_8821C 0x7\n#define BIT_DSS_2_RO_SEL_8821C(x)                                              \\\n\t(((x) & BIT_MASK_DSS_2_RO_SEL_8821C) << BIT_SHIFT_DSS_2_RO_SEL_8821C)\n#define BITS_DSS_2_RO_SEL_8821C                                                \\\n\t(BIT_MASK_DSS_2_RO_SEL_8821C << BIT_SHIFT_DSS_2_RO_SEL_8821C)\n#define BIT_CLEAR_DSS_2_RO_SEL_8821C(x) ((x) & (~BITS_DSS_2_RO_SEL_8821C))\n#define BIT_GET_DSS_2_RO_SEL_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DSS_2_RO_SEL_8821C) & BIT_MASK_DSS_2_RO_SEL_8821C)\n#define BIT_SET_DSS_2_RO_SEL_8821C(x, v)                                       \\\n\t(BIT_CLEAR_DSS_2_RO_SEL_8821C(x) | BIT_DSS_2_RO_SEL_8821C(v))\n\n#define BIT_SHIFT_DSS_2_DATA_IN_8821C 0\n#define BIT_MASK_DSS_2_DATA_IN_8821C 0xfffff\n#define BIT_DSS_2_DATA_IN_8821C(x)                                             \\\n\t(((x) & BIT_MASK_DSS_2_DATA_IN_8821C) << BIT_SHIFT_DSS_2_DATA_IN_8821C)\n#define BITS_DSS_2_DATA_IN_8821C                                               \\\n\t(BIT_MASK_DSS_2_DATA_IN_8821C << BIT_SHIFT_DSS_2_DATA_IN_8821C)\n#define BIT_CLEAR_DSS_2_DATA_IN_8821C(x) ((x) & (~BITS_DSS_2_DATA_IN_8821C))\n#define BIT_GET_DSS_2_DATA_IN_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_DSS_2_DATA_IN_8821C) & BIT_MASK_DSS_2_DATA_IN_8821C)\n#define BIT_SET_DSS_2_DATA_IN_8821C(x, v)                                      \\\n\t(BIT_CLEAR_DSS_2_DATA_IN_8821C(x) | BIT_DSS_2_DATA_IN_8821C(v))\n\n/* 2 REG_SPEED_SENSOR3_8821C */\n#define BIT_DSS_2_READY_8821C BIT(31)\n#define BIT_DSS_2_WSORT_GO_8821C BIT(30)\n\n#define BIT_SHIFT_DSS_2_COUNT_OUT_8821C 0\n#define BIT_MASK_DSS_2_COUNT_OUT_8821C 0xfffff\n#define BIT_DSS_2_COUNT_OUT_8821C(x)                                           \\\n\t(((x) & BIT_MASK_DSS_2_COUNT_OUT_8821C)                                \\\n\t << BIT_SHIFT_DSS_2_COUNT_OUT_8821C)\n#define BITS_DSS_2_COUNT_OUT_8821C                                             \\\n\t(BIT_MASK_DSS_2_COUNT_OUT_8821C << BIT_SHIFT_DSS_2_COUNT_OUT_8821C)\n#define BIT_CLEAR_DSS_2_COUNT_OUT_8821C(x) ((x) & (~BITS_DSS_2_COUNT_OUT_8821C))\n#define BIT_GET_DSS_2_COUNT_OUT_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DSS_2_COUNT_OUT_8821C) &                            \\\n\t BIT_MASK_DSS_2_COUNT_OUT_8821C)\n#define BIT_SET_DSS_2_COUNT_OUT_8821C(x, v)                                    \\\n\t(BIT_CLEAR_DSS_2_COUNT_OUT_8821C(x) | BIT_DSS_2_COUNT_OUT_8821C(v))\n\n/* 2 REG_SPEED_SENSOR4_8821C */\n#define BIT_DSS_3_RST_N_8821C BIT(31)\n#define BIT_DSS_3_SPEED_EN_8821C BIT(30)\n#define BIT_DSS_3_WIRE_SEL_8821C BIT(29)\n#define BIT_DSS_ENCLK_8821C BIT(28)\n\n#define BIT_SHIFT_DSS_3_RO_SEL_8821C 24\n#define BIT_MASK_DSS_3_RO_SEL_8821C 0x7\n#define BIT_DSS_3_RO_SEL_8821C(x)                                              \\\n\t(((x) & BIT_MASK_DSS_3_RO_SEL_8821C) << BIT_SHIFT_DSS_3_RO_SEL_8821C)\n#define BITS_DSS_3_RO_SEL_8821C                                                \\\n\t(BIT_MASK_DSS_3_RO_SEL_8821C << BIT_SHIFT_DSS_3_RO_SEL_8821C)\n#define BIT_CLEAR_DSS_3_RO_SEL_8821C(x) ((x) & (~BITS_DSS_3_RO_SEL_8821C))\n#define BIT_GET_DSS_3_RO_SEL_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DSS_3_RO_SEL_8821C) & BIT_MASK_DSS_3_RO_SEL_8821C)\n#define BIT_SET_DSS_3_RO_SEL_8821C(x, v)                                       \\\n\t(BIT_CLEAR_DSS_3_RO_SEL_8821C(x) | BIT_DSS_3_RO_SEL_8821C(v))\n\n#define BIT_SHIFT_DSS_3_DATA_IN_8821C 0\n#define BIT_MASK_DSS_3_DATA_IN_8821C 0xfffff\n#define BIT_DSS_3_DATA_IN_8821C(x)                                             \\\n\t(((x) & BIT_MASK_DSS_3_DATA_IN_8821C) << BIT_SHIFT_DSS_3_DATA_IN_8821C)\n#define BITS_DSS_3_DATA_IN_8821C                                               \\\n\t(BIT_MASK_DSS_3_DATA_IN_8821C << BIT_SHIFT_DSS_3_DATA_IN_8821C)\n#define BIT_CLEAR_DSS_3_DATA_IN_8821C(x) ((x) & (~BITS_DSS_3_DATA_IN_8821C))\n#define BIT_GET_DSS_3_DATA_IN_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_DSS_3_DATA_IN_8821C) & BIT_MASK_DSS_3_DATA_IN_8821C)\n#define BIT_SET_DSS_3_DATA_IN_8821C(x, v)                                      \\\n\t(BIT_CLEAR_DSS_3_DATA_IN_8821C(x) | BIT_DSS_3_DATA_IN_8821C(v))\n\n/* 2 REG_SPEED_SENSOR5_8821C */\n#define BIT_DSS_3_READY_8821C BIT(31)\n#define BIT_DSS_3_WSORT_GO_8821C BIT(30)\n\n#define BIT_SHIFT_DSS_3_COUNT_OUT_8821C 0\n#define BIT_MASK_DSS_3_COUNT_OUT_8821C 0xfffff\n#define BIT_DSS_3_COUNT_OUT_8821C(x)                                           \\\n\t(((x) & BIT_MASK_DSS_3_COUNT_OUT_8821C)                                \\\n\t << BIT_SHIFT_DSS_3_COUNT_OUT_8821C)\n#define BITS_DSS_3_COUNT_OUT_8821C                                             \\\n\t(BIT_MASK_DSS_3_COUNT_OUT_8821C << BIT_SHIFT_DSS_3_COUNT_OUT_8821C)\n#define BIT_CLEAR_DSS_3_COUNT_OUT_8821C(x) ((x) & (~BITS_DSS_3_COUNT_OUT_8821C))\n#define BIT_GET_DSS_3_COUNT_OUT_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DSS_3_COUNT_OUT_8821C) &                            \\\n\t BIT_MASK_DSS_3_COUNT_OUT_8821C)\n#define BIT_SET_DSS_3_COUNT_OUT_8821C(x, v)                                    \\\n\t(BIT_CLEAR_DSS_3_COUNT_OUT_8821C(x) | BIT_DSS_3_COUNT_OUT_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_COUNTER_CTRL_8821C */\n\n#define BIT_SHIFT_COUNTER_BASE_8821C 16\n#define BIT_MASK_COUNTER_BASE_8821C 0x1fff\n#define BIT_COUNTER_BASE_8821C(x)                                              \\\n\t(((x) & BIT_MASK_COUNTER_BASE_8821C) << BIT_SHIFT_COUNTER_BASE_8821C)\n#define BITS_COUNTER_BASE_8821C                                                \\\n\t(BIT_MASK_COUNTER_BASE_8821C << BIT_SHIFT_COUNTER_BASE_8821C)\n#define BIT_CLEAR_COUNTER_BASE_8821C(x) ((x) & (~BITS_COUNTER_BASE_8821C))\n#define BIT_GET_COUNTER_BASE_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_COUNTER_BASE_8821C) & BIT_MASK_COUNTER_BASE_8821C)\n#define BIT_SET_COUNTER_BASE_8821C(x, v)                                       \\\n\t(BIT_CLEAR_COUNTER_BASE_8821C(x) | BIT_COUNTER_BASE_8821C(v))\n\n#define BIT_EN_RTS_REQ_8821C BIT(9)\n#define BIT_EN_EDCA_REQ_8821C BIT(8)\n#define BIT_EN_PTCL_REQ_8821C BIT(7)\n#define BIT_EN_SCH_REQ_8821C BIT(6)\n#define BIT_USB_COUNT_EN_8821C BIT(5)\n#define BIT_PCIE_COUNT_EN_8821C BIT(4)\n#define BIT_RQPN_COUNT_EN_8821C BIT(3)\n#define BIT_RDE_COUNT_EN_8821C BIT(2)\n#define BIT_TDE_COUNT_EN_8821C BIT(1)\n#define BIT_DISABLE_COUNTER_8821C BIT(0)\n\n/* 2 REG_COUNTER_THRESHOLD_8821C */\n#define BIT_SEL_ALL_MACID_8821C BIT(31)\n\n#define BIT_SHIFT_COUNTER_MACID_8821C 24\n#define BIT_MASK_COUNTER_MACID_8821C 0x7f\n#define BIT_COUNTER_MACID_8821C(x)                                             \\\n\t(((x) & BIT_MASK_COUNTER_MACID_8821C) << BIT_SHIFT_COUNTER_MACID_8821C)\n#define BITS_COUNTER_MACID_8821C                                               \\\n\t(BIT_MASK_COUNTER_MACID_8821C << BIT_SHIFT_COUNTER_MACID_8821C)\n#define BIT_CLEAR_COUNTER_MACID_8821C(x) ((x) & (~BITS_COUNTER_MACID_8821C))\n#define BIT_GET_COUNTER_MACID_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_COUNTER_MACID_8821C) & BIT_MASK_COUNTER_MACID_8821C)\n#define BIT_SET_COUNTER_MACID_8821C(x, v)                                      \\\n\t(BIT_CLEAR_COUNTER_MACID_8821C(x) | BIT_COUNTER_MACID_8821C(v))\n\n#define BIT_SHIFT_AGG_VALUE2_8821C 16\n#define BIT_MASK_AGG_VALUE2_8821C 0x7f\n#define BIT_AGG_VALUE2_8821C(x)                                                \\\n\t(((x) & BIT_MASK_AGG_VALUE2_8821C) << BIT_SHIFT_AGG_VALUE2_8821C)\n#define BITS_AGG_VALUE2_8821C                                                  \\\n\t(BIT_MASK_AGG_VALUE2_8821C << BIT_SHIFT_AGG_VALUE2_8821C)\n#define BIT_CLEAR_AGG_VALUE2_8821C(x) ((x) & (~BITS_AGG_VALUE2_8821C))\n#define BIT_GET_AGG_VALUE2_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_AGG_VALUE2_8821C) & BIT_MASK_AGG_VALUE2_8821C)\n#define BIT_SET_AGG_VALUE2_8821C(x, v)                                         \\\n\t(BIT_CLEAR_AGG_VALUE2_8821C(x) | BIT_AGG_VALUE2_8821C(v))\n\n#define BIT_SHIFT_AGG_VALUE1_8821C 8\n#define BIT_MASK_AGG_VALUE1_8821C 0x7f\n#define BIT_AGG_VALUE1_8821C(x)                                                \\\n\t(((x) & BIT_MASK_AGG_VALUE1_8821C) << BIT_SHIFT_AGG_VALUE1_8821C)\n#define BITS_AGG_VALUE1_8821C                                                  \\\n\t(BIT_MASK_AGG_VALUE1_8821C << BIT_SHIFT_AGG_VALUE1_8821C)\n#define BIT_CLEAR_AGG_VALUE1_8821C(x) ((x) & (~BITS_AGG_VALUE1_8821C))\n#define BIT_GET_AGG_VALUE1_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_AGG_VALUE1_8821C) & BIT_MASK_AGG_VALUE1_8821C)\n#define BIT_SET_AGG_VALUE1_8821C(x, v)                                         \\\n\t(BIT_CLEAR_AGG_VALUE1_8821C(x) | BIT_AGG_VALUE1_8821C(v))\n\n#define BIT_SHIFT_AGG_VALUE0_8821C 0\n#define BIT_MASK_AGG_VALUE0_8821C 0x7f\n#define BIT_AGG_VALUE0_8821C(x)                                                \\\n\t(((x) & BIT_MASK_AGG_VALUE0_8821C) << BIT_SHIFT_AGG_VALUE0_8821C)\n#define BITS_AGG_VALUE0_8821C                                                  \\\n\t(BIT_MASK_AGG_VALUE0_8821C << BIT_SHIFT_AGG_VALUE0_8821C)\n#define BIT_CLEAR_AGG_VALUE0_8821C(x) ((x) & (~BITS_AGG_VALUE0_8821C))\n#define BIT_GET_AGG_VALUE0_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_AGG_VALUE0_8821C) & BIT_MASK_AGG_VALUE0_8821C)\n#define BIT_SET_AGG_VALUE0_8821C(x, v)                                         \\\n\t(BIT_CLEAR_AGG_VALUE0_8821C(x) | BIT_AGG_VALUE0_8821C(v))\n\n/* 2 REG_COUNTER_SET_8821C */\n\n#define BIT_SHIFT_REQUEST_RESET_8821C 16\n#define BIT_MASK_REQUEST_RESET_8821C 0xffff\n#define BIT_REQUEST_RESET_8821C(x)                                             \\\n\t(((x) & BIT_MASK_REQUEST_RESET_8821C) << BIT_SHIFT_REQUEST_RESET_8821C)\n#define BITS_REQUEST_RESET_8821C                                               \\\n\t(BIT_MASK_REQUEST_RESET_8821C << BIT_SHIFT_REQUEST_RESET_8821C)\n#define BIT_CLEAR_REQUEST_RESET_8821C(x) ((x) & (~BITS_REQUEST_RESET_8821C))\n#define BIT_GET_REQUEST_RESET_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_REQUEST_RESET_8821C) & BIT_MASK_REQUEST_RESET_8821C)\n#define BIT_SET_REQUEST_RESET_8821C(x, v)                                      \\\n\t(BIT_CLEAR_REQUEST_RESET_8821C(x) | BIT_REQUEST_RESET_8821C(v))\n\n#define BIT_SHIFT_REQUEST_START_8821C 0\n#define BIT_MASK_REQUEST_START_8821C 0xffff\n#define BIT_REQUEST_START_8821C(x)                                             \\\n\t(((x) & BIT_MASK_REQUEST_START_8821C) << BIT_SHIFT_REQUEST_START_8821C)\n#define BITS_REQUEST_START_8821C                                               \\\n\t(BIT_MASK_REQUEST_START_8821C << BIT_SHIFT_REQUEST_START_8821C)\n#define BIT_CLEAR_REQUEST_START_8821C(x) ((x) & (~BITS_REQUEST_START_8821C))\n#define BIT_GET_REQUEST_START_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_REQUEST_START_8821C) & BIT_MASK_REQUEST_START_8821C)\n#define BIT_SET_REQUEST_START_8821C(x, v)                                      \\\n\t(BIT_CLEAR_REQUEST_START_8821C(x) | BIT_REQUEST_START_8821C(v))\n\n/* 2 REG_COUNTER_OVERFLOW_8821C */\n\n#define BIT_SHIFT_CNT_OVF_REG_8821C 0\n#define BIT_MASK_CNT_OVF_REG_8821C 0xffff\n#define BIT_CNT_OVF_REG_8821C(x)                                               \\\n\t(((x) & BIT_MASK_CNT_OVF_REG_8821C) << BIT_SHIFT_CNT_OVF_REG_8821C)\n#define BITS_CNT_OVF_REG_8821C                                                 \\\n\t(BIT_MASK_CNT_OVF_REG_8821C << BIT_SHIFT_CNT_OVF_REG_8821C)\n#define BIT_CLEAR_CNT_OVF_REG_8821C(x) ((x) & (~BITS_CNT_OVF_REG_8821C))\n#define BIT_GET_CNT_OVF_REG_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_CNT_OVF_REG_8821C) & BIT_MASK_CNT_OVF_REG_8821C)\n#define BIT_SET_CNT_OVF_REG_8821C(x, v)                                        \\\n\t(BIT_CLEAR_CNT_OVF_REG_8821C(x) | BIT_CNT_OVF_REG_8821C(v))\n\n/* 2 REG_TXDMA_LEN_THRESHOLD_8821C */\n\n#define BIT_SHIFT_TDE_LEN_TH1_8821C 16\n#define BIT_MASK_TDE_LEN_TH1_8821C 0xffff\n#define BIT_TDE_LEN_TH1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_TDE_LEN_TH1_8821C) << BIT_SHIFT_TDE_LEN_TH1_8821C)\n#define BITS_TDE_LEN_TH1_8821C                                                 \\\n\t(BIT_MASK_TDE_LEN_TH1_8821C << BIT_SHIFT_TDE_LEN_TH1_8821C)\n#define BIT_CLEAR_TDE_LEN_TH1_8821C(x) ((x) & (~BITS_TDE_LEN_TH1_8821C))\n#define BIT_GET_TDE_LEN_TH1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_TDE_LEN_TH1_8821C) & BIT_MASK_TDE_LEN_TH1_8821C)\n#define BIT_SET_TDE_LEN_TH1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_TDE_LEN_TH1_8821C(x) | BIT_TDE_LEN_TH1_8821C(v))\n\n#define BIT_SHIFT_TDE_LEN_TH0_8821C 0\n#define BIT_MASK_TDE_LEN_TH0_8821C 0xffff\n#define BIT_TDE_LEN_TH0_8821C(x)                                               \\\n\t(((x) & BIT_MASK_TDE_LEN_TH0_8821C) << BIT_SHIFT_TDE_LEN_TH0_8821C)\n#define BITS_TDE_LEN_TH0_8821C                                                 \\\n\t(BIT_MASK_TDE_LEN_TH0_8821C << BIT_SHIFT_TDE_LEN_TH0_8821C)\n#define BIT_CLEAR_TDE_LEN_TH0_8821C(x) ((x) & (~BITS_TDE_LEN_TH0_8821C))\n#define BIT_GET_TDE_LEN_TH0_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_TDE_LEN_TH0_8821C) & BIT_MASK_TDE_LEN_TH0_8821C)\n#define BIT_SET_TDE_LEN_TH0_8821C(x, v)                                        \\\n\t(BIT_CLEAR_TDE_LEN_TH0_8821C(x) | BIT_TDE_LEN_TH0_8821C(v))\n\n/* 2 REG_RXDMA_LEN_THRESHOLD_8821C */\n\n#define BIT_SHIFT_RDE_LEN_TH1_8821C 16\n#define BIT_MASK_RDE_LEN_TH1_8821C 0xffff\n#define BIT_RDE_LEN_TH1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_RDE_LEN_TH1_8821C) << BIT_SHIFT_RDE_LEN_TH1_8821C)\n#define BITS_RDE_LEN_TH1_8821C                                                 \\\n\t(BIT_MASK_RDE_LEN_TH1_8821C << BIT_SHIFT_RDE_LEN_TH1_8821C)\n#define BIT_CLEAR_RDE_LEN_TH1_8821C(x) ((x) & (~BITS_RDE_LEN_TH1_8821C))\n#define BIT_GET_RDE_LEN_TH1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RDE_LEN_TH1_8821C) & BIT_MASK_RDE_LEN_TH1_8821C)\n#define BIT_SET_RDE_LEN_TH1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_RDE_LEN_TH1_8821C(x) | BIT_RDE_LEN_TH1_8821C(v))\n\n#define BIT_SHIFT_RDE_LEN_TH0_8821C 0\n#define BIT_MASK_RDE_LEN_TH0_8821C 0xffff\n#define BIT_RDE_LEN_TH0_8821C(x)                                               \\\n\t(((x) & BIT_MASK_RDE_LEN_TH0_8821C) << BIT_SHIFT_RDE_LEN_TH0_8821C)\n#define BITS_RDE_LEN_TH0_8821C                                                 \\\n\t(BIT_MASK_RDE_LEN_TH0_8821C << BIT_SHIFT_RDE_LEN_TH0_8821C)\n#define BIT_CLEAR_RDE_LEN_TH0_8821C(x) ((x) & (~BITS_RDE_LEN_TH0_8821C))\n#define BIT_GET_RDE_LEN_TH0_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RDE_LEN_TH0_8821C) & BIT_MASK_RDE_LEN_TH0_8821C)\n#define BIT_SET_RDE_LEN_TH0_8821C(x, v)                                        \\\n\t(BIT_CLEAR_RDE_LEN_TH0_8821C(x) | BIT_RDE_LEN_TH0_8821C(v))\n\n/* 2 REG_PCIE_EXEC_TIME_THRESHOLD_8821C */\n\n#define BIT_SHIFT_COUNT_INT_SEL_8821C 16\n#define BIT_MASK_COUNT_INT_SEL_8821C 0x3\n#define BIT_COUNT_INT_SEL_8821C(x)                                             \\\n\t(((x) & BIT_MASK_COUNT_INT_SEL_8821C) << BIT_SHIFT_COUNT_INT_SEL_8821C)\n#define BITS_COUNT_INT_SEL_8821C                                               \\\n\t(BIT_MASK_COUNT_INT_SEL_8821C << BIT_SHIFT_COUNT_INT_SEL_8821C)\n#define BIT_CLEAR_COUNT_INT_SEL_8821C(x) ((x) & (~BITS_COUNT_INT_SEL_8821C))\n#define BIT_GET_COUNT_INT_SEL_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_COUNT_INT_SEL_8821C) & BIT_MASK_COUNT_INT_SEL_8821C)\n#define BIT_SET_COUNT_INT_SEL_8821C(x, v)                                      \\\n\t(BIT_CLEAR_COUNT_INT_SEL_8821C(x) | BIT_COUNT_INT_SEL_8821C(v))\n\n#define BIT_SHIFT_EXEC_TIME_TH_8821C 0\n#define BIT_MASK_EXEC_TIME_TH_8821C 0xffff\n#define BIT_EXEC_TIME_TH_8821C(x)                                              \\\n\t(((x) & BIT_MASK_EXEC_TIME_TH_8821C) << BIT_SHIFT_EXEC_TIME_TH_8821C)\n#define BITS_EXEC_TIME_TH_8821C                                                \\\n\t(BIT_MASK_EXEC_TIME_TH_8821C << BIT_SHIFT_EXEC_TIME_TH_8821C)\n#define BIT_CLEAR_EXEC_TIME_TH_8821C(x) ((x) & (~BITS_EXEC_TIME_TH_8821C))\n#define BIT_GET_EXEC_TIME_TH_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_EXEC_TIME_TH_8821C) & BIT_MASK_EXEC_TIME_TH_8821C)\n#define BIT_SET_EXEC_TIME_TH_8821C(x, v)                                       \\\n\t(BIT_CLEAR_EXEC_TIME_TH_8821C(x) | BIT_EXEC_TIME_TH_8821C(v))\n\n/* 2 REG_FT2IMR_8821C */\n#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8821C BIT(31)\n#define BIT_FS_CLI3_RX_UAPSDMD0_EN_8821C BIT(30)\n#define BIT_FS_CLI3_TRIGGER_PKT_EN_8821C BIT(29)\n#define BIT_FS_CLI3_EOSP_INT_EN_8821C BIT(28)\n#define BIT_FS_CLI2_RX_UAPSDMD1_EN_8821C BIT(27)\n#define BIT_FS_CLI2_RX_UAPSDMD0_EN_8821C BIT(26)\n#define BIT_FS_CLI2_TRIGGER_PKT_EN_8821C BIT(25)\n#define BIT_FS_CLI2_EOSP_INT_EN_8821C BIT(24)\n#define BIT_FS_CLI1_RX_UAPSDMD1_EN_8821C BIT(23)\n#define BIT_FS_CLI1_RX_UAPSDMD0_EN_8821C BIT(22)\n#define BIT_FS_CLI1_TRIGGER_PKT_EN_8821C BIT(21)\n#define BIT_FS_CLI1_EOSP_INT_EN_8821C BIT(20)\n#define BIT_FS_CLI0_RX_UAPSDMD1_EN_8821C BIT(19)\n#define BIT_FS_CLI0_RX_UAPSDMD0_EN_8821C BIT(18)\n#define BIT_FS_CLI0_TRIGGER_PKT_EN_8821C BIT(17)\n#define BIT_FS_CLI0_EOSP_INT_EN_8821C BIT(16)\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN_8821C BIT(9)\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN_8821C BIT(8)\n#define BIT_FS_CLI3_TX_NULL1_INT_EN_8821C BIT(7)\n#define BIT_FS_CLI3_TX_NULL0_INT_EN_8821C BIT(6)\n#define BIT_FS_CLI2_TX_NULL1_INT_EN_8821C BIT(5)\n#define BIT_FS_CLI2_TX_NULL0_INT_EN_8821C BIT(4)\n#define BIT_FS_CLI1_TX_NULL1_INT_EN_8821C BIT(3)\n#define BIT_FS_CLI1_TX_NULL0_INT_EN_8821C BIT(2)\n#define BIT_FS_CLI0_TX_NULL1_INT_EN_8821C BIT(1)\n#define BIT_FS_CLI0_TX_NULL0_INT_EN_8821C BIT(0)\n\n/* 2 REG_FT2ISR_8821C */\n#define BIT_FS_CLI3_RX_UAPSDMD1_INT_8821C BIT(31)\n#define BIT_FS_CLI3_RX_UAPSDMD0_INT_8821C BIT(30)\n#define BIT_FS_CLI3_TRIGGER_PKT_INT_8821C BIT(29)\n#define BIT_FS_CLI3_EOSP_INT_8821C BIT(28)\n#define BIT_FS_CLI2_RX_UAPSDMD1_INT_8821C BIT(27)\n#define BIT_FS_CLI2_RX_UAPSDMD0_INT_8821C BIT(26)\n#define BIT_FS_CLI2_TRIGGER_PKT_INT_8821C BIT(25)\n#define BIT_FS_CLI2_EOSP_INT_8821C BIT(24)\n#define BIT_FS_CLI1_RX_UAPSDMD1_INT_8821C BIT(23)\n#define BIT_FS_CLI1_RX_UAPSDMD0_INT_8821C BIT(22)\n#define BIT_FS_CLI1_TRIGGER_PKT_INT_8821C BIT(21)\n#define BIT_FS_CLI1_EOSP_INT_8821C BIT(20)\n#define BIT_FS_CLI0_RX_UAPSDMD1_INT_8821C BIT(19)\n#define BIT_FS_CLI0_RX_UAPSDMD0_INT_8821C BIT(18)\n#define BIT_FS_CLI0_TRIGGER_PKT_INT_8821C BIT(17)\n#define BIT_FS_CLI0_EOSP_INT_8821C BIT(16)\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT_8821C BIT(9)\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT_8821C BIT(8)\n#define BIT_FS_CLI3_TX_NULL1_INT_8821C BIT(7)\n#define BIT_FS_CLI3_TX_NULL0_INT_8821C BIT(6)\n#define BIT_FS_CLI2_TX_NULL1_INT_8821C BIT(5)\n#define BIT_FS_CLI2_TX_NULL0_INT_8821C BIT(4)\n#define BIT_FS_CLI1_TX_NULL1_INT_8821C BIT(3)\n#define BIT_FS_CLI1_TX_NULL0_INT_8821C BIT(2)\n#define BIT_FS_CLI0_TX_NULL1_INT_8821C BIT(1)\n#define BIT_FS_CLI0_TX_NULL0_INT_8821C BIT(0)\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_MSG2_8821C */\n\n#define BIT_SHIFT_FW_MSG2_8821C 0\n#define BIT_MASK_FW_MSG2_8821C 0xffffffffL\n#define BIT_FW_MSG2_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG2_8821C) << BIT_SHIFT_FW_MSG2_8821C)\n#define BITS_FW_MSG2_8821C (BIT_MASK_FW_MSG2_8821C << BIT_SHIFT_FW_MSG2_8821C)\n#define BIT_CLEAR_FW_MSG2_8821C(x) ((x) & (~BITS_FW_MSG2_8821C))\n#define BIT_GET_FW_MSG2_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG2_8821C) & BIT_MASK_FW_MSG2_8821C)\n#define BIT_SET_FW_MSG2_8821C(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG2_8821C(x) | BIT_FW_MSG2_8821C(v))\n\n/* 2 REG_MSG3_8821C */\n\n#define BIT_SHIFT_FW_MSG3_8821C 0\n#define BIT_MASK_FW_MSG3_8821C 0xffffffffL\n#define BIT_FW_MSG3_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG3_8821C) << BIT_SHIFT_FW_MSG3_8821C)\n#define BITS_FW_MSG3_8821C (BIT_MASK_FW_MSG3_8821C << BIT_SHIFT_FW_MSG3_8821C)\n#define BIT_CLEAR_FW_MSG3_8821C(x) ((x) & (~BITS_FW_MSG3_8821C))\n#define BIT_GET_FW_MSG3_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG3_8821C) & BIT_MASK_FW_MSG3_8821C)\n#define BIT_SET_FW_MSG3_8821C(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG3_8821C(x) | BIT_FW_MSG3_8821C(v))\n\n/* 2 REG_MSG4_8821C */\n\n#define BIT_SHIFT_FW_MSG4_8821C 0\n#define BIT_MASK_FW_MSG4_8821C 0xffffffffL\n#define BIT_FW_MSG4_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG4_8821C) << BIT_SHIFT_FW_MSG4_8821C)\n#define BITS_FW_MSG4_8821C (BIT_MASK_FW_MSG4_8821C << BIT_SHIFT_FW_MSG4_8821C)\n#define BIT_CLEAR_FW_MSG4_8821C(x) ((x) & (~BITS_FW_MSG4_8821C))\n#define BIT_GET_FW_MSG4_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG4_8821C) & BIT_MASK_FW_MSG4_8821C)\n#define BIT_SET_FW_MSG4_8821C(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG4_8821C(x) | BIT_FW_MSG4_8821C(v))\n\n/* 2 REG_MSG5_8821C */\n\n#define BIT_SHIFT_FW_MSG5_8821C 0\n#define BIT_MASK_FW_MSG5_8821C 0xffffffffL\n#define BIT_FW_MSG5_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG5_8821C) << BIT_SHIFT_FW_MSG5_8821C)\n#define BITS_FW_MSG5_8821C (BIT_MASK_FW_MSG5_8821C << BIT_SHIFT_FW_MSG5_8821C)\n#define BIT_CLEAR_FW_MSG5_8821C(x) ((x) & (~BITS_FW_MSG5_8821C))\n#define BIT_GET_FW_MSG5_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG5_8821C) & BIT_MASK_FW_MSG5_8821C)\n#define BIT_SET_FW_MSG5_8821C(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG5_8821C(x) | BIT_FW_MSG5_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_FIFOPAGE_CTRL_1_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C 16\n#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C 0xff\n#define BIT_TX_OQT_HE_FREE_SPACE_V1_8821C(x)                                   \\\n\t(((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C)                        \\\n\t << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C)\n#define BITS_TX_OQT_HE_FREE_SPACE_V1_8821C                                     \\\n\t(BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C                                \\\n\t << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C)\n#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8821C(x)                             \\\n\t((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8821C))\n#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8821C(x)                               \\\n\t(((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) &                    \\\n\t BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C)\n#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8821C(x, v)                            \\\n\t(BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8821C(x) |                          \\\n\t BIT_TX_OQT_HE_FREE_SPACE_V1_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C 0\n#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C 0xff\n#define BIT_TX_OQT_NL_FREE_SPACE_V1_8821C(x)                                   \\\n\t(((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C)                        \\\n\t << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C)\n#define BITS_TX_OQT_NL_FREE_SPACE_V1_8821C                                     \\\n\t(BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C                                \\\n\t << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C)\n#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8821C(x)                             \\\n\t((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8821C))\n#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8821C(x)                               \\\n\t(((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) &                    \\\n\t BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C)\n#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8821C(x, v)                            \\\n\t(BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8821C(x) |                          \\\n\t BIT_TX_OQT_NL_FREE_SPACE_V1_8821C(v))\n\n/* 2 REG_FIFOPAGE_CTRL_2_8821C */\n#define BIT_BCN_VALID_1_V1_8821C BIT(31)\n\n/* 2 REG_NOT_VALID_8821C */\n\n#define BIT_SHIFT_BCN_HEAD_1_V1_8821C 16\n#define BIT_MASK_BCN_HEAD_1_V1_8821C 0xfff\n#define BIT_BCN_HEAD_1_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_BCN_HEAD_1_V1_8821C) << BIT_SHIFT_BCN_HEAD_1_V1_8821C)\n#define BITS_BCN_HEAD_1_V1_8821C                                               \\\n\t(BIT_MASK_BCN_HEAD_1_V1_8821C << BIT_SHIFT_BCN_HEAD_1_V1_8821C)\n#define BIT_CLEAR_BCN_HEAD_1_V1_8821C(x) ((x) & (~BITS_BCN_HEAD_1_V1_8821C))\n#define BIT_GET_BCN_HEAD_1_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8821C) & BIT_MASK_BCN_HEAD_1_V1_8821C)\n#define BIT_SET_BCN_HEAD_1_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_BCN_HEAD_1_V1_8821C(x) | BIT_BCN_HEAD_1_V1_8821C(v))\n\n#define BIT_BCN_VALID_V1_8821C BIT(15)\n\n/* 2 REG_NOT_VALID_8821C */\n\n#define BIT_SHIFT_BCN_HEAD_V1_8821C 0\n#define BIT_MASK_BCN_HEAD_V1_8821C 0xfff\n#define BIT_BCN_HEAD_V1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_BCN_HEAD_V1_8821C) << BIT_SHIFT_BCN_HEAD_V1_8821C)\n#define BITS_BCN_HEAD_V1_8821C                                                 \\\n\t(BIT_MASK_BCN_HEAD_V1_8821C << BIT_SHIFT_BCN_HEAD_V1_8821C)\n#define BIT_CLEAR_BCN_HEAD_V1_8821C(x) ((x) & (~BITS_BCN_HEAD_V1_8821C))\n#define BIT_GET_BCN_HEAD_V1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_BCN_HEAD_V1_8821C) & BIT_MASK_BCN_HEAD_V1_8821C)\n#define BIT_SET_BCN_HEAD_V1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_BCN_HEAD_V1_8821C(x) | BIT_BCN_HEAD_V1_8821C(v))\n\n/* 2 REG_AUTO_LLT_V1_8821C */\n\n#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C 24\n#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C 0xff\n#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x)                            \\\n\t(((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C)                 \\\n\t << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C)\n#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C                              \\\n\t(BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C                         \\\n\t << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C)\n#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x)                      \\\n\t((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C))\n#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x)                        \\\n\t(((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) &             \\\n\t BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C)\n#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x, v)                     \\\n\t(BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) |                   \\\n\t BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(v))\n\n#define BIT_SHIFT_LLT_FREE_PAGE_V1_8821C 8\n#define BIT_MASK_LLT_FREE_PAGE_V1_8821C 0xffff\n#define BIT_LLT_FREE_PAGE_V1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_LLT_FREE_PAGE_V1_8821C)                               \\\n\t << BIT_SHIFT_LLT_FREE_PAGE_V1_8821C)\n#define BITS_LLT_FREE_PAGE_V1_8821C                                            \\\n\t(BIT_MASK_LLT_FREE_PAGE_V1_8821C << BIT_SHIFT_LLT_FREE_PAGE_V1_8821C)\n#define BIT_CLEAR_LLT_FREE_PAGE_V1_8821C(x)                                    \\\n\t((x) & (~BITS_LLT_FREE_PAGE_V1_8821C))\n#define BIT_GET_LLT_FREE_PAGE_V1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) &                           \\\n\t BIT_MASK_LLT_FREE_PAGE_V1_8821C)\n#define BIT_SET_LLT_FREE_PAGE_V1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_LLT_FREE_PAGE_V1_8821C(x) | BIT_LLT_FREE_PAGE_V1_8821C(v))\n\n#define BIT_SHIFT_BLK_DESC_NUM_8821C 4\n#define BIT_MASK_BLK_DESC_NUM_8821C 0xf\n#define BIT_BLK_DESC_NUM_8821C(x)                                              \\\n\t(((x) & BIT_MASK_BLK_DESC_NUM_8821C) << BIT_SHIFT_BLK_DESC_NUM_8821C)\n#define BITS_BLK_DESC_NUM_8821C                                                \\\n\t(BIT_MASK_BLK_DESC_NUM_8821C << BIT_SHIFT_BLK_DESC_NUM_8821C)\n#define BIT_CLEAR_BLK_DESC_NUM_8821C(x) ((x) & (~BITS_BLK_DESC_NUM_8821C))\n#define BIT_GET_BLK_DESC_NUM_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BLK_DESC_NUM_8821C) & BIT_MASK_BLK_DESC_NUM_8821C)\n#define BIT_SET_BLK_DESC_NUM_8821C(x, v)                                       \\\n\t(BIT_CLEAR_BLK_DESC_NUM_8821C(x) | BIT_BLK_DESC_NUM_8821C(v))\n\n#define BIT_R_BCN_HEAD_SEL_8821C BIT(3)\n#define BIT_R_EN_BCN_SW_HEAD_SEL_8821C BIT(2)\n#define BIT_LLT_DBG_SEL_8821C BIT(1)\n#define BIT_AUTO_INIT_LLT_V1_8821C BIT(0)\n\n/* 2 REG_TXDMA_OFFSET_CHK_8821C */\n#define BIT_EM_CHKSUM_FIN_8821C BIT(31)\n#define BIT_EMN_PCIE_DMA_MOD_8821C BIT(30)\n#define BIT_EN_TXQUE_CLR_8821C BIT(29)\n#define BIT_EN_PCIE_FIFO_MODE_8821C BIT(28)\n\n#define BIT_SHIFT_PG_UNDER_TH_V1_8821C 16\n#define BIT_MASK_PG_UNDER_TH_V1_8821C 0xfff\n#define BIT_PG_UNDER_TH_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_PG_UNDER_TH_V1_8821C)                                 \\\n\t << BIT_SHIFT_PG_UNDER_TH_V1_8821C)\n#define BITS_PG_UNDER_TH_V1_8821C                                              \\\n\t(BIT_MASK_PG_UNDER_TH_V1_8821C << BIT_SHIFT_PG_UNDER_TH_V1_8821C)\n#define BIT_CLEAR_PG_UNDER_TH_V1_8821C(x) ((x) & (~BITS_PG_UNDER_TH_V1_8821C))\n#define BIT_GET_PG_UNDER_TH_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8821C) &                             \\\n\t BIT_MASK_PG_UNDER_TH_V1_8821C)\n#define BIT_SET_PG_UNDER_TH_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_PG_UNDER_TH_V1_8821C(x) | BIT_PG_UNDER_TH_V1_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n#define BIT_SDIO_TXDESC_CHKSUM_EN_8821C BIT(13)\n#define BIT_RST_RDPTR_8821C BIT(12)\n#define BIT_RST_WRPTR_8821C BIT(11)\n#define BIT_CHK_PG_TH_EN_8821C BIT(10)\n#define BIT_DROP_DATA_EN_8821C BIT(9)\n#define BIT_CHECK_OFFSET_EN_8821C BIT(8)\n\n#define BIT_SHIFT_CHECK_OFFSET_8821C 0\n#define BIT_MASK_CHECK_OFFSET_8821C 0xff\n#define BIT_CHECK_OFFSET_8821C(x)                                              \\\n\t(((x) & BIT_MASK_CHECK_OFFSET_8821C) << BIT_SHIFT_CHECK_OFFSET_8821C)\n#define BITS_CHECK_OFFSET_8821C                                                \\\n\t(BIT_MASK_CHECK_OFFSET_8821C << BIT_SHIFT_CHECK_OFFSET_8821C)\n#define BIT_CLEAR_CHECK_OFFSET_8821C(x) ((x) & (~BITS_CHECK_OFFSET_8821C))\n#define BIT_GET_CHECK_OFFSET_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_CHECK_OFFSET_8821C) & BIT_MASK_CHECK_OFFSET_8821C)\n#define BIT_SET_CHECK_OFFSET_8821C(x, v)                                       \\\n\t(BIT_CLEAR_CHECK_OFFSET_8821C(x) | BIT_CHECK_OFFSET_8821C(v))\n\n/* 2 REG_TXDMA_STATUS_8821C */\n#define BIT_TXPKTBUF_REQ_ERR_8821C BIT(18)\n#define BIT_HI_OQT_UDN_8821C BIT(17)\n#define BIT_HI_OQT_OVF_8821C BIT(16)\n#define BIT_PAYLOAD_CHKSUM_ERR_8821C BIT(15)\n#define BIT_PAYLOAD_UDN_8821C BIT(14)\n#define BIT_PAYLOAD_OVF_8821C BIT(13)\n#define BIT_DSC_CHKSUM_FAIL_8821C BIT(12)\n#define BIT_UNKNOWN_QSEL_8821C BIT(11)\n#define BIT_EP_QSEL_DIFF_8821C BIT(10)\n#define BIT_TX_OFFS_UNMATCH_8821C BIT(9)\n#define BIT_TXOQT_UDN_8821C BIT(8)\n#define BIT_TXOQT_OVF_8821C BIT(7)\n#define BIT_TXDMA_SFF_UDN_8821C BIT(6)\n#define BIT_TXDMA_SFF_OVF_8821C BIT(5)\n#define BIT_LLT_NULL_PG_8821C BIT(4)\n#define BIT_PAGE_UDN_8821C BIT(3)\n#define BIT_PAGE_OVF_8821C BIT(2)\n#define BIT_TXFF_PG_UDN_8821C BIT(1)\n#define BIT_TXFF_PG_OVF_8821C BIT(0)\n\n/* 2 REG_TX_DMA_DBG_8821C */\n\n/* 2 REG_TQPNT1_8821C */\n#define BIT_HPQ_INT_EN_8821C BIT(31)\n\n#define BIT_SHIFT_HPQ_HIGH_TH_V1_8821C 16\n#define BIT_MASK_HPQ_HIGH_TH_V1_8821C 0xfff\n#define BIT_HPQ_HIGH_TH_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HPQ_HIGH_TH_V1_8821C)                                 \\\n\t << BIT_SHIFT_HPQ_HIGH_TH_V1_8821C)\n#define BITS_HPQ_HIGH_TH_V1_8821C                                              \\\n\t(BIT_MASK_HPQ_HIGH_TH_V1_8821C << BIT_SHIFT_HPQ_HIGH_TH_V1_8821C)\n#define BIT_CLEAR_HPQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8821C))\n#define BIT_GET_HPQ_HIGH_TH_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8821C) &                             \\\n\t BIT_MASK_HPQ_HIGH_TH_V1_8821C)\n#define BIT_SET_HPQ_HIGH_TH_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HPQ_HIGH_TH_V1_8821C(x) | BIT_HPQ_HIGH_TH_V1_8821C(v))\n\n#define BIT_SHIFT_HPQ_LOW_TH_V1_8821C 0\n#define BIT_MASK_HPQ_LOW_TH_V1_8821C 0xfff\n#define BIT_HPQ_LOW_TH_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HPQ_LOW_TH_V1_8821C) << BIT_SHIFT_HPQ_LOW_TH_V1_8821C)\n#define BITS_HPQ_LOW_TH_V1_8821C                                               \\\n\t(BIT_MASK_HPQ_LOW_TH_V1_8821C << BIT_SHIFT_HPQ_LOW_TH_V1_8821C)\n#define BIT_CLEAR_HPQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8821C))\n#define BIT_GET_HPQ_LOW_TH_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8821C) & BIT_MASK_HPQ_LOW_TH_V1_8821C)\n#define BIT_SET_HPQ_LOW_TH_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HPQ_LOW_TH_V1_8821C(x) | BIT_HPQ_LOW_TH_V1_8821C(v))\n\n/* 2 REG_TQPNT2_8821C */\n#define BIT_NPQ_INT_EN_8821C BIT(31)\n\n#define BIT_SHIFT_NPQ_HIGH_TH_V1_8821C 16\n#define BIT_MASK_NPQ_HIGH_TH_V1_8821C 0xfff\n#define BIT_NPQ_HIGH_TH_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_NPQ_HIGH_TH_V1_8821C)                                 \\\n\t << BIT_SHIFT_NPQ_HIGH_TH_V1_8821C)\n#define BITS_NPQ_HIGH_TH_V1_8821C                                              \\\n\t(BIT_MASK_NPQ_HIGH_TH_V1_8821C << BIT_SHIFT_NPQ_HIGH_TH_V1_8821C)\n#define BIT_CLEAR_NPQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8821C))\n#define BIT_GET_NPQ_HIGH_TH_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8821C) &                             \\\n\t BIT_MASK_NPQ_HIGH_TH_V1_8821C)\n#define BIT_SET_NPQ_HIGH_TH_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_NPQ_HIGH_TH_V1_8821C(x) | BIT_NPQ_HIGH_TH_V1_8821C(v))\n\n#define BIT_SHIFT_NPQ_LOW_TH_V1_8821C 0\n#define BIT_MASK_NPQ_LOW_TH_V1_8821C 0xfff\n#define BIT_NPQ_LOW_TH_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_NPQ_LOW_TH_V1_8821C) << BIT_SHIFT_NPQ_LOW_TH_V1_8821C)\n#define BITS_NPQ_LOW_TH_V1_8821C                                               \\\n\t(BIT_MASK_NPQ_LOW_TH_V1_8821C << BIT_SHIFT_NPQ_LOW_TH_V1_8821C)\n#define BIT_CLEAR_NPQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8821C))\n#define BIT_GET_NPQ_LOW_TH_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8821C) & BIT_MASK_NPQ_LOW_TH_V1_8821C)\n#define BIT_SET_NPQ_LOW_TH_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_NPQ_LOW_TH_V1_8821C(x) | BIT_NPQ_LOW_TH_V1_8821C(v))\n\n/* 2 REG_TQPNT3_8821C */\n#define BIT_LPQ_INT_EN_8821C BIT(31)\n\n#define BIT_SHIFT_LPQ_HIGH_TH_V1_8821C 16\n#define BIT_MASK_LPQ_HIGH_TH_V1_8821C 0xfff\n#define BIT_LPQ_HIGH_TH_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_LPQ_HIGH_TH_V1_8821C)                                 \\\n\t << BIT_SHIFT_LPQ_HIGH_TH_V1_8821C)\n#define BITS_LPQ_HIGH_TH_V1_8821C                                              \\\n\t(BIT_MASK_LPQ_HIGH_TH_V1_8821C << BIT_SHIFT_LPQ_HIGH_TH_V1_8821C)\n#define BIT_CLEAR_LPQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8821C))\n#define BIT_GET_LPQ_HIGH_TH_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8821C) &                             \\\n\t BIT_MASK_LPQ_HIGH_TH_V1_8821C)\n#define BIT_SET_LPQ_HIGH_TH_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_LPQ_HIGH_TH_V1_8821C(x) | BIT_LPQ_HIGH_TH_V1_8821C(v))\n\n#define BIT_SHIFT_LPQ_LOW_TH_V1_8821C 0\n#define BIT_MASK_LPQ_LOW_TH_V1_8821C 0xfff\n#define BIT_LPQ_LOW_TH_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_LPQ_LOW_TH_V1_8821C) << BIT_SHIFT_LPQ_LOW_TH_V1_8821C)\n#define BITS_LPQ_LOW_TH_V1_8821C                                               \\\n\t(BIT_MASK_LPQ_LOW_TH_V1_8821C << BIT_SHIFT_LPQ_LOW_TH_V1_8821C)\n#define BIT_CLEAR_LPQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8821C))\n#define BIT_GET_LPQ_LOW_TH_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8821C) & BIT_MASK_LPQ_LOW_TH_V1_8821C)\n#define BIT_SET_LPQ_LOW_TH_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_LPQ_LOW_TH_V1_8821C(x) | BIT_LPQ_LOW_TH_V1_8821C(v))\n\n/* 2 REG_TQPNT4_8821C */\n#define BIT_EXQ_INT_EN_8821C BIT(31)\n\n#define BIT_SHIFT_EXQ_HIGH_TH_V1_8821C 16\n#define BIT_MASK_EXQ_HIGH_TH_V1_8821C 0xfff\n#define BIT_EXQ_HIGH_TH_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_EXQ_HIGH_TH_V1_8821C)                                 \\\n\t << BIT_SHIFT_EXQ_HIGH_TH_V1_8821C)\n#define BITS_EXQ_HIGH_TH_V1_8821C                                              \\\n\t(BIT_MASK_EXQ_HIGH_TH_V1_8821C << BIT_SHIFT_EXQ_HIGH_TH_V1_8821C)\n#define BIT_CLEAR_EXQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8821C))\n#define BIT_GET_EXQ_HIGH_TH_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8821C) &                             \\\n\t BIT_MASK_EXQ_HIGH_TH_V1_8821C)\n#define BIT_SET_EXQ_HIGH_TH_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_EXQ_HIGH_TH_V1_8821C(x) | BIT_EXQ_HIGH_TH_V1_8821C(v))\n\n#define BIT_SHIFT_EXQ_LOW_TH_V1_8821C 0\n#define BIT_MASK_EXQ_LOW_TH_V1_8821C 0xfff\n#define BIT_EXQ_LOW_TH_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_EXQ_LOW_TH_V1_8821C) << BIT_SHIFT_EXQ_LOW_TH_V1_8821C)\n#define BITS_EXQ_LOW_TH_V1_8821C                                               \\\n\t(BIT_MASK_EXQ_LOW_TH_V1_8821C << BIT_SHIFT_EXQ_LOW_TH_V1_8821C)\n#define BIT_CLEAR_EXQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8821C))\n#define BIT_GET_EXQ_LOW_TH_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8821C) & BIT_MASK_EXQ_LOW_TH_V1_8821C)\n#define BIT_SET_EXQ_LOW_TH_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_EXQ_LOW_TH_V1_8821C(x) | BIT_EXQ_LOW_TH_V1_8821C(v))\n\n/* 2 REG_RQPN_CTRL_1_8821C */\n\n#define BIT_SHIFT_TXPKTNUM_H_8821C 16\n#define BIT_MASK_TXPKTNUM_H_8821C 0xffff\n#define BIT_TXPKTNUM_H_8821C(x)                                                \\\n\t(((x) & BIT_MASK_TXPKTNUM_H_8821C) << BIT_SHIFT_TXPKTNUM_H_8821C)\n#define BITS_TXPKTNUM_H_8821C                                                  \\\n\t(BIT_MASK_TXPKTNUM_H_8821C << BIT_SHIFT_TXPKTNUM_H_8821C)\n#define BIT_CLEAR_TXPKTNUM_H_8821C(x) ((x) & (~BITS_TXPKTNUM_H_8821C))\n#define BIT_GET_TXPKTNUM_H_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_H_8821C) & BIT_MASK_TXPKTNUM_H_8821C)\n#define BIT_SET_TXPKTNUM_H_8821C(x, v)                                         \\\n\t(BIT_CLEAR_TXPKTNUM_H_8821C(x) | BIT_TXPKTNUM_H_8821C(v))\n\n#define BIT_SHIFT_TXPKTNUM_V2_8821C 0\n#define BIT_MASK_TXPKTNUM_V2_8821C 0xffff\n#define BIT_TXPKTNUM_V2_8821C(x)                                               \\\n\t(((x) & BIT_MASK_TXPKTNUM_V2_8821C) << BIT_SHIFT_TXPKTNUM_V2_8821C)\n#define BITS_TXPKTNUM_V2_8821C                                                 \\\n\t(BIT_MASK_TXPKTNUM_V2_8821C << BIT_SHIFT_TXPKTNUM_V2_8821C)\n#define BIT_CLEAR_TXPKTNUM_V2_8821C(x) ((x) & (~BITS_TXPKTNUM_V2_8821C))\n#define BIT_GET_TXPKTNUM_V2_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_V2_8821C) & BIT_MASK_TXPKTNUM_V2_8821C)\n#define BIT_SET_TXPKTNUM_V2_8821C(x, v)                                        \\\n\t(BIT_CLEAR_TXPKTNUM_V2_8821C(x) | BIT_TXPKTNUM_V2_8821C(v))\n\n/* 2 REG_RQPN_CTRL_2_8821C */\n#define BIT_LD_RQPN_8821C BIT(31)\n#define BIT_EXQ_PUBLIC_DIS_V1_8821C BIT(19)\n#define BIT_NPQ_PUBLIC_DIS_V1_8821C BIT(18)\n#define BIT_LPQ_PUBLIC_DIS_V1_8821C BIT(17)\n#define BIT_HPQ_PUBLIC_DIS_V1_8821C BIT(16)\n#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_8821C BIT(15)\n\n#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C 0\n#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C 0xfff\n#define BIT_SDIO_TXAGG_ALIGN_SIZE_8821C(x)                                     \\\n\t(((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C)                          \\\n\t << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C)\n#define BITS_SDIO_TXAGG_ALIGN_SIZE_8821C                                       \\\n\t(BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C                                  \\\n\t << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C)\n#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8821C(x)                               \\\n\t((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_8821C))\n#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8821C(x)                                 \\\n\t(((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C) &                      \\\n\t BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C)\n#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_8821C(x, v)                              \\\n\t(BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8821C(x) |                            \\\n\t BIT_SDIO_TXAGG_ALIGN_SIZE_8821C(v))\n\n/* 2 REG_FIFOPAGE_INFO_1_8821C */\n\n#define BIT_SHIFT_HPQ_AVAL_PG_V1_8821C 16\n#define BIT_MASK_HPQ_AVAL_PG_V1_8821C 0xfff\n#define BIT_HPQ_AVAL_PG_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HPQ_AVAL_PG_V1_8821C)                                 \\\n\t << BIT_SHIFT_HPQ_AVAL_PG_V1_8821C)\n#define BITS_HPQ_AVAL_PG_V1_8821C                                              \\\n\t(BIT_MASK_HPQ_AVAL_PG_V1_8821C << BIT_SHIFT_HPQ_AVAL_PG_V1_8821C)\n#define BIT_CLEAR_HPQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8821C))\n#define BIT_GET_HPQ_AVAL_PG_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8821C) &                             \\\n\t BIT_MASK_HPQ_AVAL_PG_V1_8821C)\n#define BIT_SET_HPQ_AVAL_PG_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HPQ_AVAL_PG_V1_8821C(x) | BIT_HPQ_AVAL_PG_V1_8821C(v))\n\n#define BIT_SHIFT_HPQ_V1_8821C 0\n#define BIT_MASK_HPQ_V1_8821C 0xfff\n#define BIT_HPQ_V1_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_HPQ_V1_8821C) << BIT_SHIFT_HPQ_V1_8821C)\n#define BITS_HPQ_V1_8821C (BIT_MASK_HPQ_V1_8821C << BIT_SHIFT_HPQ_V1_8821C)\n#define BIT_CLEAR_HPQ_V1_8821C(x) ((x) & (~BITS_HPQ_V1_8821C))\n#define BIT_GET_HPQ_V1_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_HPQ_V1_8821C) & BIT_MASK_HPQ_V1_8821C)\n#define BIT_SET_HPQ_V1_8821C(x, v)                                             \\\n\t(BIT_CLEAR_HPQ_V1_8821C(x) | BIT_HPQ_V1_8821C(v))\n\n/* 2 REG_FIFOPAGE_INFO_2_8821C */\n\n#define BIT_SHIFT_LPQ_AVAL_PG_V1_8821C 16\n#define BIT_MASK_LPQ_AVAL_PG_V1_8821C 0xfff\n#define BIT_LPQ_AVAL_PG_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_LPQ_AVAL_PG_V1_8821C)                                 \\\n\t << BIT_SHIFT_LPQ_AVAL_PG_V1_8821C)\n#define BITS_LPQ_AVAL_PG_V1_8821C                                              \\\n\t(BIT_MASK_LPQ_AVAL_PG_V1_8821C << BIT_SHIFT_LPQ_AVAL_PG_V1_8821C)\n#define BIT_CLEAR_LPQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8821C))\n#define BIT_GET_LPQ_AVAL_PG_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8821C) &                             \\\n\t BIT_MASK_LPQ_AVAL_PG_V1_8821C)\n#define BIT_SET_LPQ_AVAL_PG_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_LPQ_AVAL_PG_V1_8821C(x) | BIT_LPQ_AVAL_PG_V1_8821C(v))\n\n#define BIT_SHIFT_LPQ_V1_8821C 0\n#define BIT_MASK_LPQ_V1_8821C 0xfff\n#define BIT_LPQ_V1_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_LPQ_V1_8821C) << BIT_SHIFT_LPQ_V1_8821C)\n#define BITS_LPQ_V1_8821C (BIT_MASK_LPQ_V1_8821C << BIT_SHIFT_LPQ_V1_8821C)\n#define BIT_CLEAR_LPQ_V1_8821C(x) ((x) & (~BITS_LPQ_V1_8821C))\n#define BIT_GET_LPQ_V1_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_LPQ_V1_8821C) & BIT_MASK_LPQ_V1_8821C)\n#define BIT_SET_LPQ_V1_8821C(x, v)                                             \\\n\t(BIT_CLEAR_LPQ_V1_8821C(x) | BIT_LPQ_V1_8821C(v))\n\n/* 2 REG_FIFOPAGE_INFO_3_8821C */\n\n#define BIT_SHIFT_NPQ_AVAL_PG_V1_8821C 16\n#define BIT_MASK_NPQ_AVAL_PG_V1_8821C 0xfff\n#define BIT_NPQ_AVAL_PG_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_NPQ_AVAL_PG_V1_8821C)                                 \\\n\t << BIT_SHIFT_NPQ_AVAL_PG_V1_8821C)\n#define BITS_NPQ_AVAL_PG_V1_8821C                                              \\\n\t(BIT_MASK_NPQ_AVAL_PG_V1_8821C << BIT_SHIFT_NPQ_AVAL_PG_V1_8821C)\n#define BIT_CLEAR_NPQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8821C))\n#define BIT_GET_NPQ_AVAL_PG_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8821C) &                             \\\n\t BIT_MASK_NPQ_AVAL_PG_V1_8821C)\n#define BIT_SET_NPQ_AVAL_PG_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_NPQ_AVAL_PG_V1_8821C(x) | BIT_NPQ_AVAL_PG_V1_8821C(v))\n\n#define BIT_SHIFT_NPQ_V1_8821C 0\n#define BIT_MASK_NPQ_V1_8821C 0xfff\n#define BIT_NPQ_V1_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_NPQ_V1_8821C) << BIT_SHIFT_NPQ_V1_8821C)\n#define BITS_NPQ_V1_8821C (BIT_MASK_NPQ_V1_8821C << BIT_SHIFT_NPQ_V1_8821C)\n#define BIT_CLEAR_NPQ_V1_8821C(x) ((x) & (~BITS_NPQ_V1_8821C))\n#define BIT_GET_NPQ_V1_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_NPQ_V1_8821C) & BIT_MASK_NPQ_V1_8821C)\n#define BIT_SET_NPQ_V1_8821C(x, v)                                             \\\n\t(BIT_CLEAR_NPQ_V1_8821C(x) | BIT_NPQ_V1_8821C(v))\n\n/* 2 REG_FIFOPAGE_INFO_4_8821C */\n\n#define BIT_SHIFT_EXQ_AVAL_PG_V1_8821C 16\n#define BIT_MASK_EXQ_AVAL_PG_V1_8821C 0xfff\n#define BIT_EXQ_AVAL_PG_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_EXQ_AVAL_PG_V1_8821C)                                 \\\n\t << BIT_SHIFT_EXQ_AVAL_PG_V1_8821C)\n#define BITS_EXQ_AVAL_PG_V1_8821C                                              \\\n\t(BIT_MASK_EXQ_AVAL_PG_V1_8821C << BIT_SHIFT_EXQ_AVAL_PG_V1_8821C)\n#define BIT_CLEAR_EXQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8821C))\n#define BIT_GET_EXQ_AVAL_PG_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8821C) &                             \\\n\t BIT_MASK_EXQ_AVAL_PG_V1_8821C)\n#define BIT_SET_EXQ_AVAL_PG_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_EXQ_AVAL_PG_V1_8821C(x) | BIT_EXQ_AVAL_PG_V1_8821C(v))\n\n#define BIT_SHIFT_EXQ_V1_8821C 0\n#define BIT_MASK_EXQ_V1_8821C 0xfff\n#define BIT_EXQ_V1_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_EXQ_V1_8821C) << BIT_SHIFT_EXQ_V1_8821C)\n#define BITS_EXQ_V1_8821C (BIT_MASK_EXQ_V1_8821C << BIT_SHIFT_EXQ_V1_8821C)\n#define BIT_CLEAR_EXQ_V1_8821C(x) ((x) & (~BITS_EXQ_V1_8821C))\n#define BIT_GET_EXQ_V1_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_EXQ_V1_8821C) & BIT_MASK_EXQ_V1_8821C)\n#define BIT_SET_EXQ_V1_8821C(x, v)                                             \\\n\t(BIT_CLEAR_EXQ_V1_8821C(x) | BIT_EXQ_V1_8821C(v))\n\n/* 2 REG_FIFOPAGE_INFO_5_8821C */\n\n#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C 16\n#define BIT_MASK_PUBQ_AVAL_PG_V1_8821C 0xfff\n#define BIT_PUBQ_AVAL_PG_V1_8821C(x)                                           \\\n\t(((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8821C)                                \\\n\t << BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C)\n#define BITS_PUBQ_AVAL_PG_V1_8821C                                             \\\n\t(BIT_MASK_PUBQ_AVAL_PG_V1_8821C << BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C)\n#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8821C))\n#define BIT_GET_PUBQ_AVAL_PG_V1_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C) &                            \\\n\t BIT_MASK_PUBQ_AVAL_PG_V1_8821C)\n#define BIT_SET_PUBQ_AVAL_PG_V1_8821C(x, v)                                    \\\n\t(BIT_CLEAR_PUBQ_AVAL_PG_V1_8821C(x) | BIT_PUBQ_AVAL_PG_V1_8821C(v))\n\n#define BIT_SHIFT_PUBQ_V1_8821C 0\n#define BIT_MASK_PUBQ_V1_8821C 0xfff\n#define BIT_PUBQ_V1_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_PUBQ_V1_8821C) << BIT_SHIFT_PUBQ_V1_8821C)\n#define BITS_PUBQ_V1_8821C (BIT_MASK_PUBQ_V1_8821C << BIT_SHIFT_PUBQ_V1_8821C)\n#define BIT_CLEAR_PUBQ_V1_8821C(x) ((x) & (~BITS_PUBQ_V1_8821C))\n#define BIT_GET_PUBQ_V1_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_PUBQ_V1_8821C) & BIT_MASK_PUBQ_V1_8821C)\n#define BIT_SET_PUBQ_V1_8821C(x, v)                                            \\\n\t(BIT_CLEAR_PUBQ_V1_8821C(x) | BIT_PUBQ_V1_8821C(v))\n\n/* 2 REG_H2C_HEAD_8821C */\n\n#define BIT_SHIFT_H2C_HEAD_8821C 0\n#define BIT_MASK_H2C_HEAD_8821C 0x3ffff\n#define BIT_H2C_HEAD_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_H2C_HEAD_8821C) << BIT_SHIFT_H2C_HEAD_8821C)\n#define BITS_H2C_HEAD_8821C                                                    \\\n\t(BIT_MASK_H2C_HEAD_8821C << BIT_SHIFT_H2C_HEAD_8821C)\n#define BIT_CLEAR_H2C_HEAD_8821C(x) ((x) & (~BITS_H2C_HEAD_8821C))\n#define BIT_GET_H2C_HEAD_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_H2C_HEAD_8821C) & BIT_MASK_H2C_HEAD_8821C)\n#define BIT_SET_H2C_HEAD_8821C(x, v)                                           \\\n\t(BIT_CLEAR_H2C_HEAD_8821C(x) | BIT_H2C_HEAD_8821C(v))\n\n/* 2 REG_H2C_TAIL_8821C */\n\n#define BIT_SHIFT_H2C_TAIL_8821C 0\n#define BIT_MASK_H2C_TAIL_8821C 0x3ffff\n#define BIT_H2C_TAIL_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_H2C_TAIL_8821C) << BIT_SHIFT_H2C_TAIL_8821C)\n#define BITS_H2C_TAIL_8821C                                                    \\\n\t(BIT_MASK_H2C_TAIL_8821C << BIT_SHIFT_H2C_TAIL_8821C)\n#define BIT_CLEAR_H2C_TAIL_8821C(x) ((x) & (~BITS_H2C_TAIL_8821C))\n#define BIT_GET_H2C_TAIL_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_H2C_TAIL_8821C) & BIT_MASK_H2C_TAIL_8821C)\n#define BIT_SET_H2C_TAIL_8821C(x, v)                                           \\\n\t(BIT_CLEAR_H2C_TAIL_8821C(x) | BIT_H2C_TAIL_8821C(v))\n\n/* 2 REG_H2C_READ_ADDR_8821C */\n\n#define BIT_SHIFT_H2C_READ_ADDR_8821C 0\n#define BIT_MASK_H2C_READ_ADDR_8821C 0x3ffff\n#define BIT_H2C_READ_ADDR_8821C(x)                                             \\\n\t(((x) & BIT_MASK_H2C_READ_ADDR_8821C) << BIT_SHIFT_H2C_READ_ADDR_8821C)\n#define BITS_H2C_READ_ADDR_8821C                                               \\\n\t(BIT_MASK_H2C_READ_ADDR_8821C << BIT_SHIFT_H2C_READ_ADDR_8821C)\n#define BIT_CLEAR_H2C_READ_ADDR_8821C(x) ((x) & (~BITS_H2C_READ_ADDR_8821C))\n#define BIT_GET_H2C_READ_ADDR_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_H2C_READ_ADDR_8821C) & BIT_MASK_H2C_READ_ADDR_8821C)\n#define BIT_SET_H2C_READ_ADDR_8821C(x, v)                                      \\\n\t(BIT_CLEAR_H2C_READ_ADDR_8821C(x) | BIT_H2C_READ_ADDR_8821C(v))\n\n/* 2 REG_H2C_WR_ADDR_8821C */\n\n#define BIT_SHIFT_H2C_WR_ADDR_8821C 0\n#define BIT_MASK_H2C_WR_ADDR_8821C 0x3ffff\n#define BIT_H2C_WR_ADDR_8821C(x)                                               \\\n\t(((x) & BIT_MASK_H2C_WR_ADDR_8821C) << BIT_SHIFT_H2C_WR_ADDR_8821C)\n#define BITS_H2C_WR_ADDR_8821C                                                 \\\n\t(BIT_MASK_H2C_WR_ADDR_8821C << BIT_SHIFT_H2C_WR_ADDR_8821C)\n#define BIT_CLEAR_H2C_WR_ADDR_8821C(x) ((x) & (~BITS_H2C_WR_ADDR_8821C))\n#define BIT_GET_H2C_WR_ADDR_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_H2C_WR_ADDR_8821C) & BIT_MASK_H2C_WR_ADDR_8821C)\n#define BIT_SET_H2C_WR_ADDR_8821C(x, v)                                        \\\n\t(BIT_CLEAR_H2C_WR_ADDR_8821C(x) | BIT_H2C_WR_ADDR_8821C(v))\n\n/* 2 REG_H2C_INFO_8821C */\n#define BIT_H2C_SPACE_VLD_8821C BIT(3)\n#define BIT_H2C_WR_ADDR_RST_8821C BIT(2)\n\n#define BIT_SHIFT_H2C_LEN_SEL_8821C 0\n#define BIT_MASK_H2C_LEN_SEL_8821C 0x3\n#define BIT_H2C_LEN_SEL_8821C(x)                                               \\\n\t(((x) & BIT_MASK_H2C_LEN_SEL_8821C) << BIT_SHIFT_H2C_LEN_SEL_8821C)\n#define BITS_H2C_LEN_SEL_8821C                                                 \\\n\t(BIT_MASK_H2C_LEN_SEL_8821C << BIT_SHIFT_H2C_LEN_SEL_8821C)\n#define BIT_CLEAR_H2C_LEN_SEL_8821C(x) ((x) & (~BITS_H2C_LEN_SEL_8821C))\n#define BIT_GET_H2C_LEN_SEL_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_H2C_LEN_SEL_8821C) & BIT_MASK_H2C_LEN_SEL_8821C)\n#define BIT_SET_H2C_LEN_SEL_8821C(x, v)                                        \\\n\t(BIT_CLEAR_H2C_LEN_SEL_8821C(x) | BIT_H2C_LEN_SEL_8821C(v))\n\n/* 2 REG_RXDMA_AGG_PG_TH_8821C */\n#define BIT_USB_RXDMA_AGG_EN_8821C BIT(31)\n#define BIT_EN_PRE_CALC_8821C BIT(29)\n#define BIT_RXAGG_SW_EN_8821C BIT(28)\n#define BIT_RXAGG_SW_TRIG_8821C BIT(27)\n\n/* 2 REG_NOT_VALID_8821C */\n\n#define BIT_SHIFT_PKT_NUM_WOL_8821C 16\n#define BIT_MASK_PKT_NUM_WOL_8821C 0xff\n#define BIT_PKT_NUM_WOL_8821C(x)                                               \\\n\t(((x) & BIT_MASK_PKT_NUM_WOL_8821C) << BIT_SHIFT_PKT_NUM_WOL_8821C)\n#define BITS_PKT_NUM_WOL_8821C                                                 \\\n\t(BIT_MASK_PKT_NUM_WOL_8821C << BIT_SHIFT_PKT_NUM_WOL_8821C)\n#define BIT_CLEAR_PKT_NUM_WOL_8821C(x) ((x) & (~BITS_PKT_NUM_WOL_8821C))\n#define BIT_GET_PKT_NUM_WOL_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_WOL_8821C) & BIT_MASK_PKT_NUM_WOL_8821C)\n#define BIT_SET_PKT_NUM_WOL_8821C(x, v)                                        \\\n\t(BIT_CLEAR_PKT_NUM_WOL_8821C(x) | BIT_PKT_NUM_WOL_8821C(v))\n\n#define BIT_SHIFT_DMA_AGG_TO_V1_8821C 8\n#define BIT_MASK_DMA_AGG_TO_V1_8821C 0xff\n#define BIT_DMA_AGG_TO_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_DMA_AGG_TO_V1_8821C) << BIT_SHIFT_DMA_AGG_TO_V1_8821C)\n#define BITS_DMA_AGG_TO_V1_8821C                                               \\\n\t(BIT_MASK_DMA_AGG_TO_V1_8821C << BIT_SHIFT_DMA_AGG_TO_V1_8821C)\n#define BIT_CLEAR_DMA_AGG_TO_V1_8821C(x) ((x) & (~BITS_DMA_AGG_TO_V1_8821C))\n#define BIT_GET_DMA_AGG_TO_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8821C) & BIT_MASK_DMA_AGG_TO_V1_8821C)\n#define BIT_SET_DMA_AGG_TO_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_DMA_AGG_TO_V1_8821C(x) | BIT_DMA_AGG_TO_V1_8821C(v))\n\n#define BIT_SHIFT_RXDMA_AGG_PG_TH_8821C 0\n#define BIT_MASK_RXDMA_AGG_PG_TH_8821C 0xff\n#define BIT_RXDMA_AGG_PG_TH_8821C(x)                                           \\\n\t(((x) & BIT_MASK_RXDMA_AGG_PG_TH_8821C)                                \\\n\t << BIT_SHIFT_RXDMA_AGG_PG_TH_8821C)\n#define BITS_RXDMA_AGG_PG_TH_8821C                                             \\\n\t(BIT_MASK_RXDMA_AGG_PG_TH_8821C << BIT_SHIFT_RXDMA_AGG_PG_TH_8821C)\n#define BIT_CLEAR_RXDMA_AGG_PG_TH_8821C(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8821C))\n#define BIT_GET_RXDMA_AGG_PG_TH_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8821C) &                            \\\n\t BIT_MASK_RXDMA_AGG_PG_TH_8821C)\n#define BIT_SET_RXDMA_AGG_PG_TH_8821C(x, v)                                    \\\n\t(BIT_CLEAR_RXDMA_AGG_PG_TH_8821C(x) | BIT_RXDMA_AGG_PG_TH_8821C(v))\n\n/* 2 REG_RXPKT_NUM_8821C */\n\n#define BIT_SHIFT_RXPKT_NUM_8821C 24\n#define BIT_MASK_RXPKT_NUM_8821C 0xff\n#define BIT_RXPKT_NUM_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_RXPKT_NUM_8821C) << BIT_SHIFT_RXPKT_NUM_8821C)\n#define BITS_RXPKT_NUM_8821C                                                   \\\n\t(BIT_MASK_RXPKT_NUM_8821C << BIT_SHIFT_RXPKT_NUM_8821C)\n#define BIT_CLEAR_RXPKT_NUM_8821C(x) ((x) & (~BITS_RXPKT_NUM_8821C))\n#define BIT_GET_RXPKT_NUM_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_RXPKT_NUM_8821C) & BIT_MASK_RXPKT_NUM_8821C)\n#define BIT_SET_RXPKT_NUM_8821C(x, v)                                          \\\n\t(BIT_CLEAR_RXPKT_NUM_8821C(x) | BIT_RXPKT_NUM_8821C(v))\n\n#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C 20\n#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C 0xf\n#define BIT_FW_UPD_RDPTR19_TO_16_8821C(x)                                      \\\n\t(((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C)                           \\\n\t << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C)\n#define BITS_FW_UPD_RDPTR19_TO_16_8821C                                        \\\n\t(BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C                                   \\\n\t << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C)\n#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8821C(x)                                \\\n\t((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8821C))\n#define BIT_GET_FW_UPD_RDPTR19_TO_16_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) &                       \\\n\t BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C)\n#define BIT_SET_FW_UPD_RDPTR19_TO_16_8821C(x, v)                               \\\n\t(BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8821C(x) |                             \\\n\t BIT_FW_UPD_RDPTR19_TO_16_8821C(v))\n\n#define BIT_RXDMA_REQ_8821C BIT(19)\n#define BIT_RW_RELEASE_EN_8821C BIT(18)\n#define BIT_RXDMA_IDLE_8821C BIT(17)\n#define BIT_RXPKT_RELEASE_POLL_8821C BIT(16)\n\n#define BIT_SHIFT_FW_UPD_RDPTR_8821C 0\n#define BIT_MASK_FW_UPD_RDPTR_8821C 0xffff\n#define BIT_FW_UPD_RDPTR_8821C(x)                                              \\\n\t(((x) & BIT_MASK_FW_UPD_RDPTR_8821C) << BIT_SHIFT_FW_UPD_RDPTR_8821C)\n#define BITS_FW_UPD_RDPTR_8821C                                                \\\n\t(BIT_MASK_FW_UPD_RDPTR_8821C << BIT_SHIFT_FW_UPD_RDPTR_8821C)\n#define BIT_CLEAR_FW_UPD_RDPTR_8821C(x) ((x) & (~BITS_FW_UPD_RDPTR_8821C))\n#define BIT_GET_FW_UPD_RDPTR_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_FW_UPD_RDPTR_8821C) & BIT_MASK_FW_UPD_RDPTR_8821C)\n#define BIT_SET_FW_UPD_RDPTR_8821C(x, v)                                       \\\n\t(BIT_CLEAR_FW_UPD_RDPTR_8821C(x) | BIT_FW_UPD_RDPTR_8821C(v))\n\n/* 2 REG_RXDMA_STATUS_8821C */\n#define BIT_C2H_PKT_OVF_8821C BIT(7)\n#define BIT_AGG_CONFGI_ISSUE_8821C BIT(6)\n#define BIT_FW_POLL_ISSUE_8821C BIT(5)\n#define BIT_RX_DATA_UDN_8821C BIT(4)\n#define BIT_RX_SFF_UDN_8821C BIT(3)\n#define BIT_RX_SFF_OVF_8821C BIT(2)\n#define BIT_RXPKT_OVF_8821C BIT(0)\n\n/* 2 REG_RXDMA_DPR_8821C */\n\n#define BIT_SHIFT_RDE_DEBUG_8821C 0\n#define BIT_MASK_RDE_DEBUG_8821C 0xffffffffL\n#define BIT_RDE_DEBUG_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_RDE_DEBUG_8821C) << BIT_SHIFT_RDE_DEBUG_8821C)\n#define BITS_RDE_DEBUG_8821C                                                   \\\n\t(BIT_MASK_RDE_DEBUG_8821C << BIT_SHIFT_RDE_DEBUG_8821C)\n#define BIT_CLEAR_RDE_DEBUG_8821C(x) ((x) & (~BITS_RDE_DEBUG_8821C))\n#define BIT_GET_RDE_DEBUG_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_RDE_DEBUG_8821C) & BIT_MASK_RDE_DEBUG_8821C)\n#define BIT_SET_RDE_DEBUG_8821C(x, v)                                          \\\n\t(BIT_CLEAR_RDE_DEBUG_8821C(x) | BIT_RDE_DEBUG_8821C(v))\n\n/* 2 REG_RXDMA_MODE_8821C */\n\n#define BIT_SHIFT_PKTNUM_TH_V2_8821C 24\n#define BIT_MASK_PKTNUM_TH_V2_8821C 0x1f\n#define BIT_PKTNUM_TH_V2_8821C(x)                                              \\\n\t(((x) & BIT_MASK_PKTNUM_TH_V2_8821C) << BIT_SHIFT_PKTNUM_TH_V2_8821C)\n#define BITS_PKTNUM_TH_V2_8821C                                                \\\n\t(BIT_MASK_PKTNUM_TH_V2_8821C << BIT_SHIFT_PKTNUM_TH_V2_8821C)\n#define BIT_CLEAR_PKTNUM_TH_V2_8821C(x) ((x) & (~BITS_PKTNUM_TH_V2_8821C))\n#define BIT_GET_PKTNUM_TH_V2_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_PKTNUM_TH_V2_8821C) & BIT_MASK_PKTNUM_TH_V2_8821C)\n#define BIT_SET_PKTNUM_TH_V2_8821C(x, v)                                       \\\n\t(BIT_CLEAR_PKTNUM_TH_V2_8821C(x) | BIT_PKTNUM_TH_V2_8821C(v))\n\n#define BIT_TXBA_BREAK_USBAGG_8821C BIT(23)\n\n#define BIT_SHIFT_PKTLEN_PARA_8821C 16\n#define BIT_MASK_PKTLEN_PARA_8821C 0x7\n#define BIT_PKTLEN_PARA_8821C(x)                                               \\\n\t(((x) & BIT_MASK_PKTLEN_PARA_8821C) << BIT_SHIFT_PKTLEN_PARA_8821C)\n#define BITS_PKTLEN_PARA_8821C                                                 \\\n\t(BIT_MASK_PKTLEN_PARA_8821C << BIT_SHIFT_PKTLEN_PARA_8821C)\n#define BIT_CLEAR_PKTLEN_PARA_8821C(x) ((x) & (~BITS_PKTLEN_PARA_8821C))\n#define BIT_GET_PKTLEN_PARA_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_PKTLEN_PARA_8821C) & BIT_MASK_PKTLEN_PARA_8821C)\n#define BIT_SET_PKTLEN_PARA_8821C(x, v)                                        \\\n\t(BIT_CLEAR_PKTLEN_PARA_8821C(x) | BIT_PKTLEN_PARA_8821C(v))\n\n#define BIT_SHIFT_BURST_SIZE_8821C 4\n#define BIT_MASK_BURST_SIZE_8821C 0x3\n#define BIT_BURST_SIZE_8821C(x)                                                \\\n\t(((x) & BIT_MASK_BURST_SIZE_8821C) << BIT_SHIFT_BURST_SIZE_8821C)\n#define BITS_BURST_SIZE_8821C                                                  \\\n\t(BIT_MASK_BURST_SIZE_8821C << BIT_SHIFT_BURST_SIZE_8821C)\n#define BIT_CLEAR_BURST_SIZE_8821C(x) ((x) & (~BITS_BURST_SIZE_8821C))\n#define BIT_GET_BURST_SIZE_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BURST_SIZE_8821C) & BIT_MASK_BURST_SIZE_8821C)\n#define BIT_SET_BURST_SIZE_8821C(x, v)                                         \\\n\t(BIT_CLEAR_BURST_SIZE_8821C(x) | BIT_BURST_SIZE_8821C(v))\n\n#define BIT_SHIFT_BURST_CNT_8821C 2\n#define BIT_MASK_BURST_CNT_8821C 0x3\n#define BIT_BURST_CNT_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_BURST_CNT_8821C) << BIT_SHIFT_BURST_CNT_8821C)\n#define BITS_BURST_CNT_8821C                                                   \\\n\t(BIT_MASK_BURST_CNT_8821C << BIT_SHIFT_BURST_CNT_8821C)\n#define BIT_CLEAR_BURST_CNT_8821C(x) ((x) & (~BITS_BURST_CNT_8821C))\n#define BIT_GET_BURST_CNT_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_BURST_CNT_8821C) & BIT_MASK_BURST_CNT_8821C)\n#define BIT_SET_BURST_CNT_8821C(x, v)                                          \\\n\t(BIT_CLEAR_BURST_CNT_8821C(x) | BIT_BURST_CNT_8821C(v))\n\n#define BIT_DMA_MODE_8821C BIT(1)\n\n/* 2 REG_C2H_PKT_8821C */\n\n#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C 24\n#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C 0xf\n#define BIT_R_C2H_STR_ADDR_16_TO_19_8821C(x)                                   \\\n\t(((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C)                        \\\n\t << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C)\n#define BITS_R_C2H_STR_ADDR_16_TO_19_8821C                                     \\\n\t(BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C                                \\\n\t << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C)\n#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8821C(x)                             \\\n\t((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8821C))\n#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8821C(x)                               \\\n\t(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) &                    \\\n\t BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C)\n#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8821C(x, v)                            \\\n\t(BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8821C(x) |                          \\\n\t BIT_R_C2H_STR_ADDR_16_TO_19_8821C(v))\n\n#define BIT_R_C2H_PKT_REQ_8821C BIT(16)\n\n#define BIT_SHIFT_R_C2H_STR_ADDR_8821C 0\n#define BIT_MASK_R_C2H_STR_ADDR_8821C 0xffff\n#define BIT_R_C2H_STR_ADDR_8821C(x)                                            \\\n\t(((x) & BIT_MASK_R_C2H_STR_ADDR_8821C)                                 \\\n\t << BIT_SHIFT_R_C2H_STR_ADDR_8821C)\n#define BITS_R_C2H_STR_ADDR_8821C                                              \\\n\t(BIT_MASK_R_C2H_STR_ADDR_8821C << BIT_SHIFT_R_C2H_STR_ADDR_8821C)\n#define BIT_CLEAR_R_C2H_STR_ADDR_8821C(x) ((x) & (~BITS_R_C2H_STR_ADDR_8821C))\n#define BIT_GET_R_C2H_STR_ADDR_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8821C) &                             \\\n\t BIT_MASK_R_C2H_STR_ADDR_8821C)\n#define BIT_SET_R_C2H_STR_ADDR_8821C(x, v)                                     \\\n\t(BIT_CLEAR_R_C2H_STR_ADDR_8821C(x) | BIT_R_C2H_STR_ADDR_8821C(v))\n\n/* 2 REG_FWFF_C2H_8821C */\n\n#define BIT_SHIFT_C2H_DMA_ADDR_8821C 0\n#define BIT_MASK_C2H_DMA_ADDR_8821C 0x3ffff\n#define BIT_C2H_DMA_ADDR_8821C(x)                                              \\\n\t(((x) & BIT_MASK_C2H_DMA_ADDR_8821C) << BIT_SHIFT_C2H_DMA_ADDR_8821C)\n#define BITS_C2H_DMA_ADDR_8821C                                                \\\n\t(BIT_MASK_C2H_DMA_ADDR_8821C << BIT_SHIFT_C2H_DMA_ADDR_8821C)\n#define BIT_CLEAR_C2H_DMA_ADDR_8821C(x) ((x) & (~BITS_C2H_DMA_ADDR_8821C))\n#define BIT_GET_C2H_DMA_ADDR_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_C2H_DMA_ADDR_8821C) & BIT_MASK_C2H_DMA_ADDR_8821C)\n#define BIT_SET_C2H_DMA_ADDR_8821C(x, v)                                       \\\n\t(BIT_CLEAR_C2H_DMA_ADDR_8821C(x) | BIT_C2H_DMA_ADDR_8821C(v))\n\n/* 2 REG_FWFF_CTRL_8821C */\n#define BIT_FWFF_DMAPKT_REQ_8821C BIT(31)\n\n#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C 16\n#define BIT_MASK_FWFF_DMA_PKT_NUM_8821C 0xff\n#define BIT_FWFF_DMA_PKT_NUM_8821C(x)                                          \\\n\t(((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8821C)                               \\\n\t << BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C)\n#define BITS_FWFF_DMA_PKT_NUM_8821C                                            \\\n\t(BIT_MASK_FWFF_DMA_PKT_NUM_8821C << BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C)\n#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8821C(x)                                    \\\n\t((x) & (~BITS_FWFF_DMA_PKT_NUM_8821C))\n#define BIT_GET_FWFF_DMA_PKT_NUM_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C) &                           \\\n\t BIT_MASK_FWFF_DMA_PKT_NUM_8821C)\n#define BIT_SET_FWFF_DMA_PKT_NUM_8821C(x, v)                                   \\\n\t(BIT_CLEAR_FWFF_DMA_PKT_NUM_8821C(x) | BIT_FWFF_DMA_PKT_NUM_8821C(v))\n\n#define BIT_SHIFT_FWFF_STR_ADDR_8821C 0\n#define BIT_MASK_FWFF_STR_ADDR_8821C 0xffff\n#define BIT_FWFF_STR_ADDR_8821C(x)                                             \\\n\t(((x) & BIT_MASK_FWFF_STR_ADDR_8821C) << BIT_SHIFT_FWFF_STR_ADDR_8821C)\n#define BITS_FWFF_STR_ADDR_8821C                                               \\\n\t(BIT_MASK_FWFF_STR_ADDR_8821C << BIT_SHIFT_FWFF_STR_ADDR_8821C)\n#define BIT_CLEAR_FWFF_STR_ADDR_8821C(x) ((x) & (~BITS_FWFF_STR_ADDR_8821C))\n#define BIT_GET_FWFF_STR_ADDR_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_FWFF_STR_ADDR_8821C) & BIT_MASK_FWFF_STR_ADDR_8821C)\n#define BIT_SET_FWFF_STR_ADDR_8821C(x, v)                                      \\\n\t(BIT_CLEAR_FWFF_STR_ADDR_8821C(x) | BIT_FWFF_STR_ADDR_8821C(v))\n\n/* 2 REG_FWFF_PKT_INFO_8821C */\n\n#define BIT_SHIFT_FWFF_PKT_QUEUED_8821C 16\n#define BIT_MASK_FWFF_PKT_QUEUED_8821C 0xff\n#define BIT_FWFF_PKT_QUEUED_8821C(x)                                           \\\n\t(((x) & BIT_MASK_FWFF_PKT_QUEUED_8821C)                                \\\n\t << BIT_SHIFT_FWFF_PKT_QUEUED_8821C)\n#define BITS_FWFF_PKT_QUEUED_8821C                                             \\\n\t(BIT_MASK_FWFF_PKT_QUEUED_8821C << BIT_SHIFT_FWFF_PKT_QUEUED_8821C)\n#define BIT_CLEAR_FWFF_PKT_QUEUED_8821C(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8821C))\n#define BIT_GET_FWFF_PKT_QUEUED_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8821C) &                            \\\n\t BIT_MASK_FWFF_PKT_QUEUED_8821C)\n#define BIT_SET_FWFF_PKT_QUEUED_8821C(x, v)                                    \\\n\t(BIT_CLEAR_FWFF_PKT_QUEUED_8821C(x) | BIT_FWFF_PKT_QUEUED_8821C(v))\n\n#define BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C 0\n#define BIT_MASK_FWFF_PKT_STR_ADDR_8821C 0xffff\n#define BIT_FWFF_PKT_STR_ADDR_8821C(x)                                         \\\n\t(((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8821C)                              \\\n\t << BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C)\n#define BITS_FWFF_PKT_STR_ADDR_8821C                                           \\\n\t(BIT_MASK_FWFF_PKT_STR_ADDR_8821C << BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C)\n#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8821C(x)                                   \\\n\t((x) & (~BITS_FWFF_PKT_STR_ADDR_8821C))\n#define BIT_GET_FWFF_PKT_STR_ADDR_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) &                          \\\n\t BIT_MASK_FWFF_PKT_STR_ADDR_8821C)\n#define BIT_SET_FWFF_PKT_STR_ADDR_8821C(x, v)                                  \\\n\t(BIT_CLEAR_FWFF_PKT_STR_ADDR_8821C(x) | BIT_FWFF_PKT_STR_ADDR_8821C(v))\n\n/* 2 REG_DDMA_CH0SA_8821C */\n\n#define BIT_SHIFT_DDMACH0_SA_8821C 0\n#define BIT_MASK_DDMACH0_SA_8821C 0xffffffffL\n#define BIT_DDMACH0_SA_8821C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH0_SA_8821C) << BIT_SHIFT_DDMACH0_SA_8821C)\n#define BITS_DDMACH0_SA_8821C                                                  \\\n\t(BIT_MASK_DDMACH0_SA_8821C << BIT_SHIFT_DDMACH0_SA_8821C)\n#define BIT_CLEAR_DDMACH0_SA_8821C(x) ((x) & (~BITS_DDMACH0_SA_8821C))\n#define BIT_GET_DDMACH0_SA_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH0_SA_8821C) & BIT_MASK_DDMACH0_SA_8821C)\n#define BIT_SET_DDMACH0_SA_8821C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH0_SA_8821C(x) | BIT_DDMACH0_SA_8821C(v))\n\n/* 2 REG_DDMA_CH0DA_8821C */\n\n#define BIT_SHIFT_DDMACH0_DA_8821C 0\n#define BIT_MASK_DDMACH0_DA_8821C 0xffffffffL\n#define BIT_DDMACH0_DA_8821C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH0_DA_8821C) << BIT_SHIFT_DDMACH0_DA_8821C)\n#define BITS_DDMACH0_DA_8821C                                                  \\\n\t(BIT_MASK_DDMACH0_DA_8821C << BIT_SHIFT_DDMACH0_DA_8821C)\n#define BIT_CLEAR_DDMACH0_DA_8821C(x) ((x) & (~BITS_DDMACH0_DA_8821C))\n#define BIT_GET_DDMACH0_DA_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH0_DA_8821C) & BIT_MASK_DDMACH0_DA_8821C)\n#define BIT_SET_DDMACH0_DA_8821C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH0_DA_8821C(x) | BIT_DDMACH0_DA_8821C(v))\n\n/* 2 REG_DDMA_CH0CTRL_8821C */\n#define BIT_DDMACH0_OWN_8821C BIT(31)\n#define BIT_DDMACH0_IDMEM_ERR_8821C BIT(30)\n#define BIT_DDMACH0_CHKSUM_EN_8821C BIT(29)\n#define BIT_DDMACH0_DA_W_DISABLE_8821C BIT(28)\n#define BIT_DDMACH0_CHKSUM_STS_8821C BIT(27)\n#define BIT_DDMACH0_DDMA_MODE_8821C BIT(26)\n#define BIT_DDMACH0_RESET_CHKSUM_STS_8821C BIT(25)\n#define BIT_DDMACH0_CHKSUM_CONT_8821C BIT(24)\n\n#define BIT_SHIFT_DDMACH0_DLEN_8821C 0\n#define BIT_MASK_DDMACH0_DLEN_8821C 0x3ffff\n#define BIT_DDMACH0_DLEN_8821C(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH0_DLEN_8821C) << BIT_SHIFT_DDMACH0_DLEN_8821C)\n#define BITS_DDMACH0_DLEN_8821C                                                \\\n\t(BIT_MASK_DDMACH0_DLEN_8821C << BIT_SHIFT_DDMACH0_DLEN_8821C)\n#define BIT_CLEAR_DDMACH0_DLEN_8821C(x) ((x) & (~BITS_DDMACH0_DLEN_8821C))\n#define BIT_GET_DDMACH0_DLEN_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH0_DLEN_8821C) & BIT_MASK_DDMACH0_DLEN_8821C)\n#define BIT_SET_DDMACH0_DLEN_8821C(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH0_DLEN_8821C(x) | BIT_DDMACH0_DLEN_8821C(v))\n\n/* 2 REG_DDMA_CH1SA_8821C */\n\n#define BIT_SHIFT_DDMACH1_SA_8821C 0\n#define BIT_MASK_DDMACH1_SA_8821C 0xffffffffL\n#define BIT_DDMACH1_SA_8821C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH1_SA_8821C) << BIT_SHIFT_DDMACH1_SA_8821C)\n#define BITS_DDMACH1_SA_8821C                                                  \\\n\t(BIT_MASK_DDMACH1_SA_8821C << BIT_SHIFT_DDMACH1_SA_8821C)\n#define BIT_CLEAR_DDMACH1_SA_8821C(x) ((x) & (~BITS_DDMACH1_SA_8821C))\n#define BIT_GET_DDMACH1_SA_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH1_SA_8821C) & BIT_MASK_DDMACH1_SA_8821C)\n#define BIT_SET_DDMACH1_SA_8821C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH1_SA_8821C(x) | BIT_DDMACH1_SA_8821C(v))\n\n/* 2 REG_DDMA_CH1DA_8821C */\n\n#define BIT_SHIFT_DDMACH1_DA_8821C 0\n#define BIT_MASK_DDMACH1_DA_8821C 0xffffffffL\n#define BIT_DDMACH1_DA_8821C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH1_DA_8821C) << BIT_SHIFT_DDMACH1_DA_8821C)\n#define BITS_DDMACH1_DA_8821C                                                  \\\n\t(BIT_MASK_DDMACH1_DA_8821C << BIT_SHIFT_DDMACH1_DA_8821C)\n#define BIT_CLEAR_DDMACH1_DA_8821C(x) ((x) & (~BITS_DDMACH1_DA_8821C))\n#define BIT_GET_DDMACH1_DA_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH1_DA_8821C) & BIT_MASK_DDMACH1_DA_8821C)\n#define BIT_SET_DDMACH1_DA_8821C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH1_DA_8821C(x) | BIT_DDMACH1_DA_8821C(v))\n\n/* 2 REG_DDMA_CH1CTRL_8821C */\n#define BIT_DDMACH1_OWN_8821C BIT(31)\n#define BIT_DDMACH1_IDMEM_ERR_8821C BIT(30)\n#define BIT_DDMACH1_CHKSUM_EN_8821C BIT(29)\n#define BIT_DDMACH1_DA_W_DISABLE_8821C BIT(28)\n#define BIT_DDMACH1_CHKSUM_STS_8821C BIT(27)\n#define BIT_DDMACH1_DDMA_MODE_8821C BIT(26)\n#define BIT_DDMACH1_RESET_CHKSUM_STS_8821C BIT(25)\n#define BIT_DDMACH1_CHKSUM_CONT_8821C BIT(24)\n\n#define BIT_SHIFT_DDMACH1_DLEN_8821C 0\n#define BIT_MASK_DDMACH1_DLEN_8821C 0x3ffff\n#define BIT_DDMACH1_DLEN_8821C(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH1_DLEN_8821C) << BIT_SHIFT_DDMACH1_DLEN_8821C)\n#define BITS_DDMACH1_DLEN_8821C                                                \\\n\t(BIT_MASK_DDMACH1_DLEN_8821C << BIT_SHIFT_DDMACH1_DLEN_8821C)\n#define BIT_CLEAR_DDMACH1_DLEN_8821C(x) ((x) & (~BITS_DDMACH1_DLEN_8821C))\n#define BIT_GET_DDMACH1_DLEN_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH1_DLEN_8821C) & BIT_MASK_DDMACH1_DLEN_8821C)\n#define BIT_SET_DDMACH1_DLEN_8821C(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH1_DLEN_8821C(x) | BIT_DDMACH1_DLEN_8821C(v))\n\n/* 2 REG_DDMA_CH2SA_8821C */\n\n#define BIT_SHIFT_DDMACH2_SA_8821C 0\n#define BIT_MASK_DDMACH2_SA_8821C 0xffffffffL\n#define BIT_DDMACH2_SA_8821C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH2_SA_8821C) << BIT_SHIFT_DDMACH2_SA_8821C)\n#define BITS_DDMACH2_SA_8821C                                                  \\\n\t(BIT_MASK_DDMACH2_SA_8821C << BIT_SHIFT_DDMACH2_SA_8821C)\n#define BIT_CLEAR_DDMACH2_SA_8821C(x) ((x) & (~BITS_DDMACH2_SA_8821C))\n#define BIT_GET_DDMACH2_SA_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH2_SA_8821C) & BIT_MASK_DDMACH2_SA_8821C)\n#define BIT_SET_DDMACH2_SA_8821C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH2_SA_8821C(x) | BIT_DDMACH2_SA_8821C(v))\n\n/* 2 REG_DDMA_CH2DA_8821C */\n\n#define BIT_SHIFT_DDMACH2_DA_8821C 0\n#define BIT_MASK_DDMACH2_DA_8821C 0xffffffffL\n#define BIT_DDMACH2_DA_8821C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH2_DA_8821C) << BIT_SHIFT_DDMACH2_DA_8821C)\n#define BITS_DDMACH2_DA_8821C                                                  \\\n\t(BIT_MASK_DDMACH2_DA_8821C << BIT_SHIFT_DDMACH2_DA_8821C)\n#define BIT_CLEAR_DDMACH2_DA_8821C(x) ((x) & (~BITS_DDMACH2_DA_8821C))\n#define BIT_GET_DDMACH2_DA_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH2_DA_8821C) & BIT_MASK_DDMACH2_DA_8821C)\n#define BIT_SET_DDMACH2_DA_8821C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH2_DA_8821C(x) | BIT_DDMACH2_DA_8821C(v))\n\n/* 2 REG_DDMA_CH2CTRL_8821C */\n#define BIT_DDMACH2_OWN_8821C BIT(31)\n#define BIT_DDMACH2_IDMEM_ERR_8821C BIT(30)\n#define BIT_DDMACH2_CHKSUM_EN_8821C BIT(29)\n#define BIT_DDMACH2_DA_W_DISABLE_8821C BIT(28)\n#define BIT_DDMACH2_CHKSUM_STS_8821C BIT(27)\n#define BIT_DDMACH2_DDMA_MODE_8821C BIT(26)\n#define BIT_DDMACH2_RESET_CHKSUM_STS_8821C BIT(25)\n#define BIT_DDMACH2_CHKSUM_CONT_8821C BIT(24)\n\n#define BIT_SHIFT_DDMACH2_DLEN_8821C 0\n#define BIT_MASK_DDMACH2_DLEN_8821C 0x3ffff\n#define BIT_DDMACH2_DLEN_8821C(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH2_DLEN_8821C) << BIT_SHIFT_DDMACH2_DLEN_8821C)\n#define BITS_DDMACH2_DLEN_8821C                                                \\\n\t(BIT_MASK_DDMACH2_DLEN_8821C << BIT_SHIFT_DDMACH2_DLEN_8821C)\n#define BIT_CLEAR_DDMACH2_DLEN_8821C(x) ((x) & (~BITS_DDMACH2_DLEN_8821C))\n#define BIT_GET_DDMACH2_DLEN_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH2_DLEN_8821C) & BIT_MASK_DDMACH2_DLEN_8821C)\n#define BIT_SET_DDMACH2_DLEN_8821C(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH2_DLEN_8821C(x) | BIT_DDMACH2_DLEN_8821C(v))\n\n/* 2 REG_DDMA_CH3SA_8821C */\n\n#define BIT_SHIFT_DDMACH3_SA_8821C 0\n#define BIT_MASK_DDMACH3_SA_8821C 0xffffffffL\n#define BIT_DDMACH3_SA_8821C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH3_SA_8821C) << BIT_SHIFT_DDMACH3_SA_8821C)\n#define BITS_DDMACH3_SA_8821C                                                  \\\n\t(BIT_MASK_DDMACH3_SA_8821C << BIT_SHIFT_DDMACH3_SA_8821C)\n#define BIT_CLEAR_DDMACH3_SA_8821C(x) ((x) & (~BITS_DDMACH3_SA_8821C))\n#define BIT_GET_DDMACH3_SA_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH3_SA_8821C) & BIT_MASK_DDMACH3_SA_8821C)\n#define BIT_SET_DDMACH3_SA_8821C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH3_SA_8821C(x) | BIT_DDMACH3_SA_8821C(v))\n\n/* 2 REG_DDMA_CH3DA_8821C */\n\n#define BIT_SHIFT_DDMACH3_DA_8821C 0\n#define BIT_MASK_DDMACH3_DA_8821C 0xffffffffL\n#define BIT_DDMACH3_DA_8821C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH3_DA_8821C) << BIT_SHIFT_DDMACH3_DA_8821C)\n#define BITS_DDMACH3_DA_8821C                                                  \\\n\t(BIT_MASK_DDMACH3_DA_8821C << BIT_SHIFT_DDMACH3_DA_8821C)\n#define BIT_CLEAR_DDMACH3_DA_8821C(x) ((x) & (~BITS_DDMACH3_DA_8821C))\n#define BIT_GET_DDMACH3_DA_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH3_DA_8821C) & BIT_MASK_DDMACH3_DA_8821C)\n#define BIT_SET_DDMACH3_DA_8821C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH3_DA_8821C(x) | BIT_DDMACH3_DA_8821C(v))\n\n/* 2 REG_DDMA_CH3CTRL_8821C */\n#define BIT_DDMACH3_OWN_8821C BIT(31)\n#define BIT_DDMACH3_IDMEM_ERR_8821C BIT(30)\n#define BIT_DDMACH3_CHKSUM_EN_8821C BIT(29)\n#define BIT_DDMACH3_DA_W_DISABLE_8821C BIT(28)\n#define BIT_DDMACH3_CHKSUM_STS_8821C BIT(27)\n#define BIT_DDMACH3_DDMA_MODE_8821C BIT(26)\n#define BIT_DDMACH3_RESET_CHKSUM_STS_8821C BIT(25)\n#define BIT_DDMACH3_CHKSUM_CONT_8821C BIT(24)\n\n#define BIT_SHIFT_DDMACH3_DLEN_8821C 0\n#define BIT_MASK_DDMACH3_DLEN_8821C 0x3ffff\n#define BIT_DDMACH3_DLEN_8821C(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH3_DLEN_8821C) << BIT_SHIFT_DDMACH3_DLEN_8821C)\n#define BITS_DDMACH3_DLEN_8821C                                                \\\n\t(BIT_MASK_DDMACH3_DLEN_8821C << BIT_SHIFT_DDMACH3_DLEN_8821C)\n#define BIT_CLEAR_DDMACH3_DLEN_8821C(x) ((x) & (~BITS_DDMACH3_DLEN_8821C))\n#define BIT_GET_DDMACH3_DLEN_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH3_DLEN_8821C) & BIT_MASK_DDMACH3_DLEN_8821C)\n#define BIT_SET_DDMACH3_DLEN_8821C(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH3_DLEN_8821C(x) | BIT_DDMACH3_DLEN_8821C(v))\n\n/* 2 REG_DDMA_CH4SA_8821C */\n\n#define BIT_SHIFT_DDMACH4_SA_8821C 0\n#define BIT_MASK_DDMACH4_SA_8821C 0xffffffffL\n#define BIT_DDMACH4_SA_8821C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH4_SA_8821C) << BIT_SHIFT_DDMACH4_SA_8821C)\n#define BITS_DDMACH4_SA_8821C                                                  \\\n\t(BIT_MASK_DDMACH4_SA_8821C << BIT_SHIFT_DDMACH4_SA_8821C)\n#define BIT_CLEAR_DDMACH4_SA_8821C(x) ((x) & (~BITS_DDMACH4_SA_8821C))\n#define BIT_GET_DDMACH4_SA_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH4_SA_8821C) & BIT_MASK_DDMACH4_SA_8821C)\n#define BIT_SET_DDMACH4_SA_8821C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH4_SA_8821C(x) | BIT_DDMACH4_SA_8821C(v))\n\n/* 2 REG_DDMA_CH4DA_8821C */\n\n#define BIT_SHIFT_DDMACH4_DA_8821C 0\n#define BIT_MASK_DDMACH4_DA_8821C 0xffffffffL\n#define BIT_DDMACH4_DA_8821C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH4_DA_8821C) << BIT_SHIFT_DDMACH4_DA_8821C)\n#define BITS_DDMACH4_DA_8821C                                                  \\\n\t(BIT_MASK_DDMACH4_DA_8821C << BIT_SHIFT_DDMACH4_DA_8821C)\n#define BIT_CLEAR_DDMACH4_DA_8821C(x) ((x) & (~BITS_DDMACH4_DA_8821C))\n#define BIT_GET_DDMACH4_DA_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH4_DA_8821C) & BIT_MASK_DDMACH4_DA_8821C)\n#define BIT_SET_DDMACH4_DA_8821C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH4_DA_8821C(x) | BIT_DDMACH4_DA_8821C(v))\n\n/* 2 REG_DDMA_CH4CTRL_8821C */\n#define BIT_DDMACH4_OWN_8821C BIT(31)\n#define BIT_DDMACH4_IDMEM_ERR_8821C BIT(30)\n#define BIT_DDMACH4_CHKSUM_EN_8821C BIT(29)\n#define BIT_DDMACH4_DA_W_DISABLE_8821C BIT(28)\n#define BIT_DDMACH4_CHKSUM_STS_8821C BIT(27)\n#define BIT_DDMACH4_DDMA_MODE_8821C BIT(26)\n#define BIT_DDMACH4_RESET_CHKSUM_STS_8821C BIT(25)\n#define BIT_DDMACH4_CHKSUM_CONT_8821C BIT(24)\n\n#define BIT_SHIFT_DDMACH4_DLEN_8821C 0\n#define BIT_MASK_DDMACH4_DLEN_8821C 0x3ffff\n#define BIT_DDMACH4_DLEN_8821C(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH4_DLEN_8821C) << BIT_SHIFT_DDMACH4_DLEN_8821C)\n#define BITS_DDMACH4_DLEN_8821C                                                \\\n\t(BIT_MASK_DDMACH4_DLEN_8821C << BIT_SHIFT_DDMACH4_DLEN_8821C)\n#define BIT_CLEAR_DDMACH4_DLEN_8821C(x) ((x) & (~BITS_DDMACH4_DLEN_8821C))\n#define BIT_GET_DDMACH4_DLEN_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH4_DLEN_8821C) & BIT_MASK_DDMACH4_DLEN_8821C)\n#define BIT_SET_DDMACH4_DLEN_8821C(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH4_DLEN_8821C(x) | BIT_DDMACH4_DLEN_8821C(v))\n\n/* 2 REG_DDMA_CH5SA_8821C */\n\n#define BIT_SHIFT_DDMACH5_SA_8821C 0\n#define BIT_MASK_DDMACH5_SA_8821C 0xffffffffL\n#define BIT_DDMACH5_SA_8821C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH5_SA_8821C) << BIT_SHIFT_DDMACH5_SA_8821C)\n#define BITS_DDMACH5_SA_8821C                                                  \\\n\t(BIT_MASK_DDMACH5_SA_8821C << BIT_SHIFT_DDMACH5_SA_8821C)\n#define BIT_CLEAR_DDMACH5_SA_8821C(x) ((x) & (~BITS_DDMACH5_SA_8821C))\n#define BIT_GET_DDMACH5_SA_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH5_SA_8821C) & BIT_MASK_DDMACH5_SA_8821C)\n#define BIT_SET_DDMACH5_SA_8821C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH5_SA_8821C(x) | BIT_DDMACH5_SA_8821C(v))\n\n/* 2 REG_DDMA_CH5DA_8821C */\n\n#define BIT_SHIFT_DDMACH5_DA_8821C 0\n#define BIT_MASK_DDMACH5_DA_8821C 0xffffffffL\n#define BIT_DDMACH5_DA_8821C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH5_DA_8821C) << BIT_SHIFT_DDMACH5_DA_8821C)\n#define BITS_DDMACH5_DA_8821C                                                  \\\n\t(BIT_MASK_DDMACH5_DA_8821C << BIT_SHIFT_DDMACH5_DA_8821C)\n#define BIT_CLEAR_DDMACH5_DA_8821C(x) ((x) & (~BITS_DDMACH5_DA_8821C))\n#define BIT_GET_DDMACH5_DA_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH5_DA_8821C) & BIT_MASK_DDMACH5_DA_8821C)\n#define BIT_SET_DDMACH5_DA_8821C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH5_DA_8821C(x) | BIT_DDMACH5_DA_8821C(v))\n\n/* 2 REG_DDMA_CH5CTRL_8821C */\n#define BIT_DDMACH5_OWN_8821C BIT(31)\n#define BIT_DDMACH5_IDMEM_ERR_8821C BIT(30)\n#define BIT_DDMACH5_CHKSUM_EN_8821C BIT(29)\n#define BIT_DDMACH5_DA_W_DISABLE_8821C BIT(28)\n#define BIT_DDMACH5_CHKSUM_STS_8821C BIT(27)\n#define BIT_DDMACH5_DDMA_MODE_8821C BIT(26)\n#define BIT_DDMACH5_RESET_CHKSUM_STS_8821C BIT(25)\n#define BIT_DDMACH5_CHKSUM_CONT_8821C BIT(24)\n\n#define BIT_SHIFT_DDMACH5_DLEN_8821C 0\n#define BIT_MASK_DDMACH5_DLEN_8821C 0x3ffff\n#define BIT_DDMACH5_DLEN_8821C(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH5_DLEN_8821C) << BIT_SHIFT_DDMACH5_DLEN_8821C)\n#define BITS_DDMACH5_DLEN_8821C                                                \\\n\t(BIT_MASK_DDMACH5_DLEN_8821C << BIT_SHIFT_DDMACH5_DLEN_8821C)\n#define BIT_CLEAR_DDMACH5_DLEN_8821C(x) ((x) & (~BITS_DDMACH5_DLEN_8821C))\n#define BIT_GET_DDMACH5_DLEN_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH5_DLEN_8821C) & BIT_MASK_DDMACH5_DLEN_8821C)\n#define BIT_SET_DDMACH5_DLEN_8821C(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH5_DLEN_8821C(x) | BIT_DDMACH5_DLEN_8821C(v))\n\n/* 2 REG_DDMA_INT_MSK_8821C */\n#define BIT_DDMACH5_MSK_8821C BIT(5)\n#define BIT_DDMACH4_MSK_8821C BIT(4)\n#define BIT_DDMACH3_MSK_8821C BIT(3)\n#define BIT_DDMACH2_MSK_8821C BIT(2)\n#define BIT_DDMACH1_MSK_8821C BIT(1)\n#define BIT_DDMACH0_MSK_8821C BIT(0)\n\n/* 2 REG_DDMA_CHSTATUS_8821C */\n#define BIT_DDMACH5_BUSY_8821C BIT(5)\n#define BIT_DDMACH4_BUSY_8821C BIT(4)\n#define BIT_DDMACH3_BUSY_8821C BIT(3)\n#define BIT_DDMACH2_BUSY_8821C BIT(2)\n#define BIT_DDMACH1_BUSY_8821C BIT(1)\n#define BIT_DDMACH0_BUSY_8821C BIT(0)\n\n/* 2 REG_DDMA_CHKSUM_8821C */\n\n#define BIT_SHIFT_IDDMA0_CHKSUM_8821C 0\n#define BIT_MASK_IDDMA0_CHKSUM_8821C 0xffff\n#define BIT_IDDMA0_CHKSUM_8821C(x)                                             \\\n\t(((x) & BIT_MASK_IDDMA0_CHKSUM_8821C) << BIT_SHIFT_IDDMA0_CHKSUM_8821C)\n#define BITS_IDDMA0_CHKSUM_8821C                                               \\\n\t(BIT_MASK_IDDMA0_CHKSUM_8821C << BIT_SHIFT_IDDMA0_CHKSUM_8821C)\n#define BIT_CLEAR_IDDMA0_CHKSUM_8821C(x) ((x) & (~BITS_IDDMA0_CHKSUM_8821C))\n#define BIT_GET_IDDMA0_CHKSUM_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8821C) & BIT_MASK_IDDMA0_CHKSUM_8821C)\n#define BIT_SET_IDDMA0_CHKSUM_8821C(x, v)                                      \\\n\t(BIT_CLEAR_IDDMA0_CHKSUM_8821C(x) | BIT_IDDMA0_CHKSUM_8821C(v))\n\n/* 2 REG_DDMA_MONITOR_8821C */\n#define BIT_IDDMA0_PERMU_UNDERFLOW_8821C BIT(14)\n#define BIT_IDDMA0_FIFO_UNDERFLOW_8821C BIT(13)\n#define BIT_IDDMA0_FIFO_OVERFLOW_8821C BIT(12)\n#define BIT_CH5_ERR_8821C BIT(5)\n#define BIT_CH4_ERR_8821C BIT(4)\n#define BIT_CH3_ERR_8821C BIT(3)\n#define BIT_CH2_ERR_8821C BIT(2)\n#define BIT_CH1_ERR_8821C BIT(1)\n#define BIT_CH0_ERR_8821C BIT(0)\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_PCIE_CTRL_8821C */\n#define BIT_PCIEIO_PERSTB_SEL_8821C BIT(31)\n\n#define BIT_SHIFT_PCIE_MAX_RXDMA_8821C 28\n#define BIT_MASK_PCIE_MAX_RXDMA_8821C 0x7\n#define BIT_PCIE_MAX_RXDMA_8821C(x)                                            \\\n\t(((x) & BIT_MASK_PCIE_MAX_RXDMA_8821C)                                 \\\n\t << BIT_SHIFT_PCIE_MAX_RXDMA_8821C)\n#define BITS_PCIE_MAX_RXDMA_8821C                                              \\\n\t(BIT_MASK_PCIE_MAX_RXDMA_8821C << BIT_SHIFT_PCIE_MAX_RXDMA_8821C)\n#define BIT_CLEAR_PCIE_MAX_RXDMA_8821C(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8821C))\n#define BIT_GET_PCIE_MAX_RXDMA_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8821C) &                             \\\n\t BIT_MASK_PCIE_MAX_RXDMA_8821C)\n#define BIT_SET_PCIE_MAX_RXDMA_8821C(x, v)                                     \\\n\t(BIT_CLEAR_PCIE_MAX_RXDMA_8821C(x) | BIT_PCIE_MAX_RXDMA_8821C(v))\n\n#define BIT_MULRW_8821C BIT(27)\n\n#define BIT_SHIFT_PCIE_MAX_TXDMA_8821C 24\n#define BIT_MASK_PCIE_MAX_TXDMA_8821C 0x7\n#define BIT_PCIE_MAX_TXDMA_8821C(x)                                            \\\n\t(((x) & BIT_MASK_PCIE_MAX_TXDMA_8821C)                                 \\\n\t << BIT_SHIFT_PCIE_MAX_TXDMA_8821C)\n#define BITS_PCIE_MAX_TXDMA_8821C                                              \\\n\t(BIT_MASK_PCIE_MAX_TXDMA_8821C << BIT_SHIFT_PCIE_MAX_TXDMA_8821C)\n#define BIT_CLEAR_PCIE_MAX_TXDMA_8821C(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8821C))\n#define BIT_GET_PCIE_MAX_TXDMA_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8821C) &                             \\\n\t BIT_MASK_PCIE_MAX_TXDMA_8821C)\n#define BIT_SET_PCIE_MAX_TXDMA_8821C(x, v)                                     \\\n\t(BIT_CLEAR_PCIE_MAX_TXDMA_8821C(x) | BIT_PCIE_MAX_TXDMA_8821C(v))\n\n#define BIT_EN_CPL_TIMEOUT_PS_8821C BIT(22)\n#define BIT_REG_TXDMA_FAIL_PS_8821C BIT(21)\n#define BIT_PCIE_RST_TRXDMA_INTF_8821C BIT(20)\n#define BIT_EN_HWENTR_L1_8821C BIT(19)\n#define BIT_EN_ADV_CLKGATE_8821C BIT(18)\n#define BIT_PCIE_EN_SWENT_L23_8821C BIT(17)\n#define BIT_PCIE_EN_HWEXT_L1_8821C BIT(16)\n#define BIT_RX_CLOSE_EN_8821C BIT(15)\n#define BIT_STOP_BCNQ_8821C BIT(14)\n#define BIT_STOP_MGQ_8821C BIT(13)\n#define BIT_STOP_VOQ_8821C BIT(12)\n#define BIT_STOP_VIQ_8821C BIT(11)\n#define BIT_STOP_BEQ_8821C BIT(10)\n#define BIT_STOP_BKQ_8821C BIT(9)\n#define BIT_STOP_RXQ_8821C BIT(8)\n#define BIT_STOP_HI7Q_8821C BIT(7)\n#define BIT_STOP_HI6Q_8821C BIT(6)\n#define BIT_STOP_HI5Q_8821C BIT(5)\n#define BIT_STOP_HI4Q_8821C BIT(4)\n#define BIT_STOP_HI3Q_8821C BIT(3)\n#define BIT_STOP_HI2Q_8821C BIT(2)\n#define BIT_STOP_HI1Q_8821C BIT(1)\n#define BIT_STOP_HI0Q_8821C BIT(0)\n\n/* 2 REG_INT_MIG_8821C */\n\n#define BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C 28\n#define BIT_MASK_TXTTIMER_MATCH_NUM_8821C 0xf\n#define BIT_TXTTIMER_MATCH_NUM_8821C(x)                                        \\\n\t(((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8821C)                             \\\n\t << BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C)\n#define BITS_TXTTIMER_MATCH_NUM_8821C                                          \\\n\t(BIT_MASK_TXTTIMER_MATCH_NUM_8821C                                     \\\n\t << BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C)\n#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8821C(x)                                  \\\n\t((x) & (~BITS_TXTTIMER_MATCH_NUM_8821C))\n#define BIT_GET_TXTTIMER_MATCH_NUM_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C) &                         \\\n\t BIT_MASK_TXTTIMER_MATCH_NUM_8821C)\n#define BIT_SET_TXTTIMER_MATCH_NUM_8821C(x, v)                                 \\\n\t(BIT_CLEAR_TXTTIMER_MATCH_NUM_8821C(x) |                               \\\n\t BIT_TXTTIMER_MATCH_NUM_8821C(v))\n\n#define BIT_SHIFT_TXPKT_NUM_MATCH_8821C 24\n#define BIT_MASK_TXPKT_NUM_MATCH_8821C 0xf\n#define BIT_TXPKT_NUM_MATCH_8821C(x)                                           \\\n\t(((x) & BIT_MASK_TXPKT_NUM_MATCH_8821C)                                \\\n\t << BIT_SHIFT_TXPKT_NUM_MATCH_8821C)\n#define BITS_TXPKT_NUM_MATCH_8821C                                             \\\n\t(BIT_MASK_TXPKT_NUM_MATCH_8821C << BIT_SHIFT_TXPKT_NUM_MATCH_8821C)\n#define BIT_CLEAR_TXPKT_NUM_MATCH_8821C(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8821C))\n#define BIT_GET_TXPKT_NUM_MATCH_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8821C) &                            \\\n\t BIT_MASK_TXPKT_NUM_MATCH_8821C)\n#define BIT_SET_TXPKT_NUM_MATCH_8821C(x, v)                                    \\\n\t(BIT_CLEAR_TXPKT_NUM_MATCH_8821C(x) | BIT_TXPKT_NUM_MATCH_8821C(v))\n\n#define BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C 20\n#define BIT_MASK_RXTTIMER_MATCH_NUM_8821C 0xf\n#define BIT_RXTTIMER_MATCH_NUM_8821C(x)                                        \\\n\t(((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8821C)                             \\\n\t << BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C)\n#define BITS_RXTTIMER_MATCH_NUM_8821C                                          \\\n\t(BIT_MASK_RXTTIMER_MATCH_NUM_8821C                                     \\\n\t << BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C)\n#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8821C(x)                                  \\\n\t((x) & (~BITS_RXTTIMER_MATCH_NUM_8821C))\n#define BIT_GET_RXTTIMER_MATCH_NUM_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) &                         \\\n\t BIT_MASK_RXTTIMER_MATCH_NUM_8821C)\n#define BIT_SET_RXTTIMER_MATCH_NUM_8821C(x, v)                                 \\\n\t(BIT_CLEAR_RXTTIMER_MATCH_NUM_8821C(x) |                               \\\n\t BIT_RXTTIMER_MATCH_NUM_8821C(v))\n\n#define BIT_SHIFT_RXPKT_NUM_MATCH_8821C 16\n#define BIT_MASK_RXPKT_NUM_MATCH_8821C 0xf\n#define BIT_RXPKT_NUM_MATCH_8821C(x)                                           \\\n\t(((x) & BIT_MASK_RXPKT_NUM_MATCH_8821C)                                \\\n\t << BIT_SHIFT_RXPKT_NUM_MATCH_8821C)\n#define BITS_RXPKT_NUM_MATCH_8821C                                             \\\n\t(BIT_MASK_RXPKT_NUM_MATCH_8821C << BIT_SHIFT_RXPKT_NUM_MATCH_8821C)\n#define BIT_CLEAR_RXPKT_NUM_MATCH_8821C(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8821C))\n#define BIT_GET_RXPKT_NUM_MATCH_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8821C) &                            \\\n\t BIT_MASK_RXPKT_NUM_MATCH_8821C)\n#define BIT_SET_RXPKT_NUM_MATCH_8821C(x, v)                                    \\\n\t(BIT_CLEAR_RXPKT_NUM_MATCH_8821C(x) | BIT_RXPKT_NUM_MATCH_8821C(v))\n\n#define BIT_SHIFT_MIGRATE_TIMER_8821C 0\n#define BIT_MASK_MIGRATE_TIMER_8821C 0xffff\n#define BIT_MIGRATE_TIMER_8821C(x)                                             \\\n\t(((x) & BIT_MASK_MIGRATE_TIMER_8821C) << BIT_SHIFT_MIGRATE_TIMER_8821C)\n#define BITS_MIGRATE_TIMER_8821C                                               \\\n\t(BIT_MASK_MIGRATE_TIMER_8821C << BIT_SHIFT_MIGRATE_TIMER_8821C)\n#define BIT_CLEAR_MIGRATE_TIMER_8821C(x) ((x) & (~BITS_MIGRATE_TIMER_8821C))\n#define BIT_GET_MIGRATE_TIMER_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MIGRATE_TIMER_8821C) & BIT_MASK_MIGRATE_TIMER_8821C)\n#define BIT_SET_MIGRATE_TIMER_8821C(x, v)                                      \\\n\t(BIT_CLEAR_MIGRATE_TIMER_8821C(x) | BIT_MIGRATE_TIMER_8821C(v))\n\n/* 2 REG_BCNQ_TXBD_DESA_8821C */\n\n#define BIT_SHIFT_BCNQ_TXBD_DESA_8821C 0\n#define BIT_MASK_BCNQ_TXBD_DESA_8821C 0xffffffffffffffffL\n#define BIT_BCNQ_TXBD_DESA_8821C(x)                                            \\\n\t(((x) & BIT_MASK_BCNQ_TXBD_DESA_8821C)                                 \\\n\t << BIT_SHIFT_BCNQ_TXBD_DESA_8821C)\n#define BITS_BCNQ_TXBD_DESA_8821C                                              \\\n\t(BIT_MASK_BCNQ_TXBD_DESA_8821C << BIT_SHIFT_BCNQ_TXBD_DESA_8821C)\n#define BIT_CLEAR_BCNQ_TXBD_DESA_8821C(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8821C))\n#define BIT_GET_BCNQ_TXBD_DESA_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8821C) &                             \\\n\t BIT_MASK_BCNQ_TXBD_DESA_8821C)\n#define BIT_SET_BCNQ_TXBD_DESA_8821C(x, v)                                     \\\n\t(BIT_CLEAR_BCNQ_TXBD_DESA_8821C(x) | BIT_BCNQ_TXBD_DESA_8821C(v))\n\n/* 2 REG_MGQ_TXBD_DESA_8821C */\n\n#define BIT_SHIFT_MGQ_TXBD_DESA_8821C 0\n#define BIT_MASK_MGQ_TXBD_DESA_8821C 0xffffffffffffffffL\n#define BIT_MGQ_TXBD_DESA_8821C(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_TXBD_DESA_8821C) << BIT_SHIFT_MGQ_TXBD_DESA_8821C)\n#define BITS_MGQ_TXBD_DESA_8821C                                               \\\n\t(BIT_MASK_MGQ_TXBD_DESA_8821C << BIT_SHIFT_MGQ_TXBD_DESA_8821C)\n#define BIT_CLEAR_MGQ_TXBD_DESA_8821C(x) ((x) & (~BITS_MGQ_TXBD_DESA_8821C))\n#define BIT_GET_MGQ_TXBD_DESA_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8821C) & BIT_MASK_MGQ_TXBD_DESA_8821C)\n#define BIT_SET_MGQ_TXBD_DESA_8821C(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_TXBD_DESA_8821C(x) | BIT_MGQ_TXBD_DESA_8821C(v))\n\n/* 2 REG_VOQ_TXBD_DESA_8821C */\n\n#define BIT_SHIFT_VOQ_TXBD_DESA_8821C 0\n#define BIT_MASK_VOQ_TXBD_DESA_8821C 0xffffffffffffffffL\n#define BIT_VOQ_TXBD_DESA_8821C(x)                                             \\\n\t(((x) & BIT_MASK_VOQ_TXBD_DESA_8821C) << BIT_SHIFT_VOQ_TXBD_DESA_8821C)\n#define BITS_VOQ_TXBD_DESA_8821C                                               \\\n\t(BIT_MASK_VOQ_TXBD_DESA_8821C << BIT_SHIFT_VOQ_TXBD_DESA_8821C)\n#define BIT_CLEAR_VOQ_TXBD_DESA_8821C(x) ((x) & (~BITS_VOQ_TXBD_DESA_8821C))\n#define BIT_GET_VOQ_TXBD_DESA_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8821C) & BIT_MASK_VOQ_TXBD_DESA_8821C)\n#define BIT_SET_VOQ_TXBD_DESA_8821C(x, v)                                      \\\n\t(BIT_CLEAR_VOQ_TXBD_DESA_8821C(x) | BIT_VOQ_TXBD_DESA_8821C(v))\n\n/* 2 REG_VIQ_TXBD_DESA_8821C */\n\n#define BIT_SHIFT_VIQ_TXBD_DESA_8821C 0\n#define BIT_MASK_VIQ_TXBD_DESA_8821C 0xffffffffffffffffL\n#define BIT_VIQ_TXBD_DESA_8821C(x)                                             \\\n\t(((x) & BIT_MASK_VIQ_TXBD_DESA_8821C) << BIT_SHIFT_VIQ_TXBD_DESA_8821C)\n#define BITS_VIQ_TXBD_DESA_8821C                                               \\\n\t(BIT_MASK_VIQ_TXBD_DESA_8821C << BIT_SHIFT_VIQ_TXBD_DESA_8821C)\n#define BIT_CLEAR_VIQ_TXBD_DESA_8821C(x) ((x) & (~BITS_VIQ_TXBD_DESA_8821C))\n#define BIT_GET_VIQ_TXBD_DESA_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8821C) & BIT_MASK_VIQ_TXBD_DESA_8821C)\n#define BIT_SET_VIQ_TXBD_DESA_8821C(x, v)                                      \\\n\t(BIT_CLEAR_VIQ_TXBD_DESA_8821C(x) | BIT_VIQ_TXBD_DESA_8821C(v))\n\n/* 2 REG_BEQ_TXBD_DESA_8821C */\n\n#define BIT_SHIFT_BEQ_TXBD_DESA_8821C 0\n#define BIT_MASK_BEQ_TXBD_DESA_8821C 0xffffffffffffffffL\n#define BIT_BEQ_TXBD_DESA_8821C(x)                                             \\\n\t(((x) & BIT_MASK_BEQ_TXBD_DESA_8821C) << BIT_SHIFT_BEQ_TXBD_DESA_8821C)\n#define BITS_BEQ_TXBD_DESA_8821C                                               \\\n\t(BIT_MASK_BEQ_TXBD_DESA_8821C << BIT_SHIFT_BEQ_TXBD_DESA_8821C)\n#define BIT_CLEAR_BEQ_TXBD_DESA_8821C(x) ((x) & (~BITS_BEQ_TXBD_DESA_8821C))\n#define BIT_GET_BEQ_TXBD_DESA_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8821C) & BIT_MASK_BEQ_TXBD_DESA_8821C)\n#define BIT_SET_BEQ_TXBD_DESA_8821C(x, v)                                      \\\n\t(BIT_CLEAR_BEQ_TXBD_DESA_8821C(x) | BIT_BEQ_TXBD_DESA_8821C(v))\n\n/* 2 REG_BKQ_TXBD_DESA_8821C */\n\n#define BIT_SHIFT_BKQ_TXBD_DESA_8821C 0\n#define BIT_MASK_BKQ_TXBD_DESA_8821C 0xffffffffffffffffL\n#define BIT_BKQ_TXBD_DESA_8821C(x)                                             \\\n\t(((x) & BIT_MASK_BKQ_TXBD_DESA_8821C) << BIT_SHIFT_BKQ_TXBD_DESA_8821C)\n#define BITS_BKQ_TXBD_DESA_8821C                                               \\\n\t(BIT_MASK_BKQ_TXBD_DESA_8821C << BIT_SHIFT_BKQ_TXBD_DESA_8821C)\n#define BIT_CLEAR_BKQ_TXBD_DESA_8821C(x) ((x) & (~BITS_BKQ_TXBD_DESA_8821C))\n#define BIT_GET_BKQ_TXBD_DESA_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8821C) & BIT_MASK_BKQ_TXBD_DESA_8821C)\n#define BIT_SET_BKQ_TXBD_DESA_8821C(x, v)                                      \\\n\t(BIT_CLEAR_BKQ_TXBD_DESA_8821C(x) | BIT_BKQ_TXBD_DESA_8821C(v))\n\n/* 2 REG_RXQ_RXBD_DESA_8821C */\n\n#define BIT_SHIFT_RXQ_RXBD_DESA_8821C 0\n#define BIT_MASK_RXQ_RXBD_DESA_8821C 0xffffffffffffffffL\n#define BIT_RXQ_RXBD_DESA_8821C(x)                                             \\\n\t(((x) & BIT_MASK_RXQ_RXBD_DESA_8821C) << BIT_SHIFT_RXQ_RXBD_DESA_8821C)\n#define BITS_RXQ_RXBD_DESA_8821C                                               \\\n\t(BIT_MASK_RXQ_RXBD_DESA_8821C << BIT_SHIFT_RXQ_RXBD_DESA_8821C)\n#define BIT_CLEAR_RXQ_RXBD_DESA_8821C(x) ((x) & (~BITS_RXQ_RXBD_DESA_8821C))\n#define BIT_GET_RXQ_RXBD_DESA_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8821C) & BIT_MASK_RXQ_RXBD_DESA_8821C)\n#define BIT_SET_RXQ_RXBD_DESA_8821C(x, v)                                      \\\n\t(BIT_CLEAR_RXQ_RXBD_DESA_8821C(x) | BIT_RXQ_RXBD_DESA_8821C(v))\n\n/* 2 REG_HI0Q_TXBD_DESA_8821C */\n\n#define BIT_SHIFT_HI0Q_TXBD_DESA_8821C 0\n#define BIT_MASK_HI0Q_TXBD_DESA_8821C 0xffffffffffffffffL\n#define BIT_HI0Q_TXBD_DESA_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HI0Q_TXBD_DESA_8821C)                                 \\\n\t << BIT_SHIFT_HI0Q_TXBD_DESA_8821C)\n#define BITS_HI0Q_TXBD_DESA_8821C                                              \\\n\t(BIT_MASK_HI0Q_TXBD_DESA_8821C << BIT_SHIFT_HI0Q_TXBD_DESA_8821C)\n#define BIT_CLEAR_HI0Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8821C))\n#define BIT_GET_HI0Q_TXBD_DESA_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8821C) &                             \\\n\t BIT_MASK_HI0Q_TXBD_DESA_8821C)\n#define BIT_SET_HI0Q_TXBD_DESA_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HI0Q_TXBD_DESA_8821C(x) | BIT_HI0Q_TXBD_DESA_8821C(v))\n\n/* 2 REG_HI1Q_TXBD_DESA_8821C */\n\n#define BIT_SHIFT_HI1Q_TXBD_DESA_8821C 0\n#define BIT_MASK_HI1Q_TXBD_DESA_8821C 0xffffffffffffffffL\n#define BIT_HI1Q_TXBD_DESA_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HI1Q_TXBD_DESA_8821C)                                 \\\n\t << BIT_SHIFT_HI1Q_TXBD_DESA_8821C)\n#define BITS_HI1Q_TXBD_DESA_8821C                                              \\\n\t(BIT_MASK_HI1Q_TXBD_DESA_8821C << BIT_SHIFT_HI1Q_TXBD_DESA_8821C)\n#define BIT_CLEAR_HI1Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8821C))\n#define BIT_GET_HI1Q_TXBD_DESA_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8821C) &                             \\\n\t BIT_MASK_HI1Q_TXBD_DESA_8821C)\n#define BIT_SET_HI1Q_TXBD_DESA_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HI1Q_TXBD_DESA_8821C(x) | BIT_HI1Q_TXBD_DESA_8821C(v))\n\n/* 2 REG_HI2Q_TXBD_DESA_8821C */\n\n#define BIT_SHIFT_HI2Q_TXBD_DESA_8821C 0\n#define BIT_MASK_HI2Q_TXBD_DESA_8821C 0xffffffffffffffffL\n#define BIT_HI2Q_TXBD_DESA_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HI2Q_TXBD_DESA_8821C)                                 \\\n\t << BIT_SHIFT_HI2Q_TXBD_DESA_8821C)\n#define BITS_HI2Q_TXBD_DESA_8821C                                              \\\n\t(BIT_MASK_HI2Q_TXBD_DESA_8821C << BIT_SHIFT_HI2Q_TXBD_DESA_8821C)\n#define BIT_CLEAR_HI2Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8821C))\n#define BIT_GET_HI2Q_TXBD_DESA_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8821C) &                             \\\n\t BIT_MASK_HI2Q_TXBD_DESA_8821C)\n#define BIT_SET_HI2Q_TXBD_DESA_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HI2Q_TXBD_DESA_8821C(x) | BIT_HI2Q_TXBD_DESA_8821C(v))\n\n/* 2 REG_HI3Q_TXBD_DESA_8821C */\n\n#define BIT_SHIFT_HI3Q_TXBD_DESA_8821C 0\n#define BIT_MASK_HI3Q_TXBD_DESA_8821C 0xffffffffffffffffL\n#define BIT_HI3Q_TXBD_DESA_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HI3Q_TXBD_DESA_8821C)                                 \\\n\t << BIT_SHIFT_HI3Q_TXBD_DESA_8821C)\n#define BITS_HI3Q_TXBD_DESA_8821C                                              \\\n\t(BIT_MASK_HI3Q_TXBD_DESA_8821C << BIT_SHIFT_HI3Q_TXBD_DESA_8821C)\n#define BIT_CLEAR_HI3Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8821C))\n#define BIT_GET_HI3Q_TXBD_DESA_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8821C) &                             \\\n\t BIT_MASK_HI3Q_TXBD_DESA_8821C)\n#define BIT_SET_HI3Q_TXBD_DESA_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HI3Q_TXBD_DESA_8821C(x) | BIT_HI3Q_TXBD_DESA_8821C(v))\n\n/* 2 REG_HI4Q_TXBD_DESA_8821C */\n\n#define BIT_SHIFT_HI4Q_TXBD_DESA_8821C 0\n#define BIT_MASK_HI4Q_TXBD_DESA_8821C 0xffffffffffffffffL\n#define BIT_HI4Q_TXBD_DESA_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HI4Q_TXBD_DESA_8821C)                                 \\\n\t << BIT_SHIFT_HI4Q_TXBD_DESA_8821C)\n#define BITS_HI4Q_TXBD_DESA_8821C                                              \\\n\t(BIT_MASK_HI4Q_TXBD_DESA_8821C << BIT_SHIFT_HI4Q_TXBD_DESA_8821C)\n#define BIT_CLEAR_HI4Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8821C))\n#define BIT_GET_HI4Q_TXBD_DESA_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8821C) &                             \\\n\t BIT_MASK_HI4Q_TXBD_DESA_8821C)\n#define BIT_SET_HI4Q_TXBD_DESA_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HI4Q_TXBD_DESA_8821C(x) | BIT_HI4Q_TXBD_DESA_8821C(v))\n\n/* 2 REG_HI5Q_TXBD_DESA_8821C */\n\n#define BIT_SHIFT_HI5Q_TXBD_DESA_8821C 0\n#define BIT_MASK_HI5Q_TXBD_DESA_8821C 0xffffffffffffffffL\n#define BIT_HI5Q_TXBD_DESA_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HI5Q_TXBD_DESA_8821C)                                 \\\n\t << BIT_SHIFT_HI5Q_TXBD_DESA_8821C)\n#define BITS_HI5Q_TXBD_DESA_8821C                                              \\\n\t(BIT_MASK_HI5Q_TXBD_DESA_8821C << BIT_SHIFT_HI5Q_TXBD_DESA_8821C)\n#define BIT_CLEAR_HI5Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8821C))\n#define BIT_GET_HI5Q_TXBD_DESA_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8821C) &                             \\\n\t BIT_MASK_HI5Q_TXBD_DESA_8821C)\n#define BIT_SET_HI5Q_TXBD_DESA_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HI5Q_TXBD_DESA_8821C(x) | BIT_HI5Q_TXBD_DESA_8821C(v))\n\n/* 2 REG_HI6Q_TXBD_DESA_8821C */\n\n#define BIT_SHIFT_HI6Q_TXBD_DESA_8821C 0\n#define BIT_MASK_HI6Q_TXBD_DESA_8821C 0xffffffffffffffffL\n#define BIT_HI6Q_TXBD_DESA_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HI6Q_TXBD_DESA_8821C)                                 \\\n\t << BIT_SHIFT_HI6Q_TXBD_DESA_8821C)\n#define BITS_HI6Q_TXBD_DESA_8821C                                              \\\n\t(BIT_MASK_HI6Q_TXBD_DESA_8821C << BIT_SHIFT_HI6Q_TXBD_DESA_8821C)\n#define BIT_CLEAR_HI6Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8821C))\n#define BIT_GET_HI6Q_TXBD_DESA_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8821C) &                             \\\n\t BIT_MASK_HI6Q_TXBD_DESA_8821C)\n#define BIT_SET_HI6Q_TXBD_DESA_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HI6Q_TXBD_DESA_8821C(x) | BIT_HI6Q_TXBD_DESA_8821C(v))\n\n/* 2 REG_HI7Q_TXBD_DESA_8821C */\n\n#define BIT_SHIFT_HI7Q_TXBD_DESA_8821C 0\n#define BIT_MASK_HI7Q_TXBD_DESA_8821C 0xffffffffffffffffL\n#define BIT_HI7Q_TXBD_DESA_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HI7Q_TXBD_DESA_8821C)                                 \\\n\t << BIT_SHIFT_HI7Q_TXBD_DESA_8821C)\n#define BITS_HI7Q_TXBD_DESA_8821C                                              \\\n\t(BIT_MASK_HI7Q_TXBD_DESA_8821C << BIT_SHIFT_HI7Q_TXBD_DESA_8821C)\n#define BIT_CLEAR_HI7Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8821C))\n#define BIT_GET_HI7Q_TXBD_DESA_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8821C) &                             \\\n\t BIT_MASK_HI7Q_TXBD_DESA_8821C)\n#define BIT_SET_HI7Q_TXBD_DESA_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HI7Q_TXBD_DESA_8821C(x) | BIT_HI7Q_TXBD_DESA_8821C(v))\n\n/* 2 REG_MGQ_TXBD_NUM_8821C */\n#define BIT_PCIE_MGQ_FLAG_8821C BIT(14)\n\n#define BIT_SHIFT_MGQ_DESC_MODE_8821C 12\n#define BIT_MASK_MGQ_DESC_MODE_8821C 0x3\n#define BIT_MGQ_DESC_MODE_8821C(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_DESC_MODE_8821C) << BIT_SHIFT_MGQ_DESC_MODE_8821C)\n#define BITS_MGQ_DESC_MODE_8821C                                               \\\n\t(BIT_MASK_MGQ_DESC_MODE_8821C << BIT_SHIFT_MGQ_DESC_MODE_8821C)\n#define BIT_CLEAR_MGQ_DESC_MODE_8821C(x) ((x) & (~BITS_MGQ_DESC_MODE_8821C))\n#define BIT_GET_MGQ_DESC_MODE_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_DESC_MODE_8821C) & BIT_MASK_MGQ_DESC_MODE_8821C)\n#define BIT_SET_MGQ_DESC_MODE_8821C(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_DESC_MODE_8821C(x) | BIT_MGQ_DESC_MODE_8821C(v))\n\n#define BIT_SHIFT_MGQ_DESC_NUM_8821C 0\n#define BIT_MASK_MGQ_DESC_NUM_8821C 0xfff\n#define BIT_MGQ_DESC_NUM_8821C(x)                                              \\\n\t(((x) & BIT_MASK_MGQ_DESC_NUM_8821C) << BIT_SHIFT_MGQ_DESC_NUM_8821C)\n#define BITS_MGQ_DESC_NUM_8821C                                                \\\n\t(BIT_MASK_MGQ_DESC_NUM_8821C << BIT_SHIFT_MGQ_DESC_NUM_8821C)\n#define BIT_CLEAR_MGQ_DESC_NUM_8821C(x) ((x) & (~BITS_MGQ_DESC_NUM_8821C))\n#define BIT_GET_MGQ_DESC_NUM_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_MGQ_DESC_NUM_8821C) & BIT_MASK_MGQ_DESC_NUM_8821C)\n#define BIT_SET_MGQ_DESC_NUM_8821C(x, v)                                       \\\n\t(BIT_CLEAR_MGQ_DESC_NUM_8821C(x) | BIT_MGQ_DESC_NUM_8821C(v))\n\n/* 2 REG_RX_RXBD_NUM_8821C */\n#define BIT_SYS_32_64_8821C BIT(15)\n\n#define BIT_SHIFT_BCNQ_DESC_MODE_8821C 13\n#define BIT_MASK_BCNQ_DESC_MODE_8821C 0x3\n#define BIT_BCNQ_DESC_MODE_8821C(x)                                            \\\n\t(((x) & BIT_MASK_BCNQ_DESC_MODE_8821C)                                 \\\n\t << BIT_SHIFT_BCNQ_DESC_MODE_8821C)\n#define BITS_BCNQ_DESC_MODE_8821C                                              \\\n\t(BIT_MASK_BCNQ_DESC_MODE_8821C << BIT_SHIFT_BCNQ_DESC_MODE_8821C)\n#define BIT_CLEAR_BCNQ_DESC_MODE_8821C(x) ((x) & (~BITS_BCNQ_DESC_MODE_8821C))\n#define BIT_GET_BCNQ_DESC_MODE_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8821C) &                             \\\n\t BIT_MASK_BCNQ_DESC_MODE_8821C)\n#define BIT_SET_BCNQ_DESC_MODE_8821C(x, v)                                     \\\n\t(BIT_CLEAR_BCNQ_DESC_MODE_8821C(x) | BIT_BCNQ_DESC_MODE_8821C(v))\n\n#define BIT_PCIE_BCNQ_FLAG_8821C BIT(12)\n\n#define BIT_SHIFT_RXQ_DESC_NUM_8821C 0\n#define BIT_MASK_RXQ_DESC_NUM_8821C 0xfff\n#define BIT_RXQ_DESC_NUM_8821C(x)                                              \\\n\t(((x) & BIT_MASK_RXQ_DESC_NUM_8821C) << BIT_SHIFT_RXQ_DESC_NUM_8821C)\n#define BITS_RXQ_DESC_NUM_8821C                                                \\\n\t(BIT_MASK_RXQ_DESC_NUM_8821C << BIT_SHIFT_RXQ_DESC_NUM_8821C)\n#define BIT_CLEAR_RXQ_DESC_NUM_8821C(x) ((x) & (~BITS_RXQ_DESC_NUM_8821C))\n#define BIT_GET_RXQ_DESC_NUM_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXQ_DESC_NUM_8821C) & BIT_MASK_RXQ_DESC_NUM_8821C)\n#define BIT_SET_RXQ_DESC_NUM_8821C(x, v)                                       \\\n\t(BIT_CLEAR_RXQ_DESC_NUM_8821C(x) | BIT_RXQ_DESC_NUM_8821C(v))\n\n/* 2 REG_VOQ_TXBD_NUM_8821C */\n#define BIT_PCIE_VOQ_FLAG_8821C BIT(14)\n\n#define BIT_SHIFT_VOQ_DESC_MODE_8821C 12\n#define BIT_MASK_VOQ_DESC_MODE_8821C 0x3\n#define BIT_VOQ_DESC_MODE_8821C(x)                                             \\\n\t(((x) & BIT_MASK_VOQ_DESC_MODE_8821C) << BIT_SHIFT_VOQ_DESC_MODE_8821C)\n#define BITS_VOQ_DESC_MODE_8821C                                               \\\n\t(BIT_MASK_VOQ_DESC_MODE_8821C << BIT_SHIFT_VOQ_DESC_MODE_8821C)\n#define BIT_CLEAR_VOQ_DESC_MODE_8821C(x) ((x) & (~BITS_VOQ_DESC_MODE_8821C))\n#define BIT_GET_VOQ_DESC_MODE_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_VOQ_DESC_MODE_8821C) & BIT_MASK_VOQ_DESC_MODE_8821C)\n#define BIT_SET_VOQ_DESC_MODE_8821C(x, v)                                      \\\n\t(BIT_CLEAR_VOQ_DESC_MODE_8821C(x) | BIT_VOQ_DESC_MODE_8821C(v))\n\n#define BIT_SHIFT_VOQ_DESC_NUM_8821C 0\n#define BIT_MASK_VOQ_DESC_NUM_8821C 0xfff\n#define BIT_VOQ_DESC_NUM_8821C(x)                                              \\\n\t(((x) & BIT_MASK_VOQ_DESC_NUM_8821C) << BIT_SHIFT_VOQ_DESC_NUM_8821C)\n#define BITS_VOQ_DESC_NUM_8821C                                                \\\n\t(BIT_MASK_VOQ_DESC_NUM_8821C << BIT_SHIFT_VOQ_DESC_NUM_8821C)\n#define BIT_CLEAR_VOQ_DESC_NUM_8821C(x) ((x) & (~BITS_VOQ_DESC_NUM_8821C))\n#define BIT_GET_VOQ_DESC_NUM_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_VOQ_DESC_NUM_8821C) & BIT_MASK_VOQ_DESC_NUM_8821C)\n#define BIT_SET_VOQ_DESC_NUM_8821C(x, v)                                       \\\n\t(BIT_CLEAR_VOQ_DESC_NUM_8821C(x) | BIT_VOQ_DESC_NUM_8821C(v))\n\n/* 2 REG_VIQ_TXBD_NUM_8821C */\n#define BIT_PCIE_VIQ_FLAG_8821C BIT(14)\n\n#define BIT_SHIFT_VIQ_DESC_MODE_8821C 12\n#define BIT_MASK_VIQ_DESC_MODE_8821C 0x3\n#define BIT_VIQ_DESC_MODE_8821C(x)                                             \\\n\t(((x) & BIT_MASK_VIQ_DESC_MODE_8821C) << BIT_SHIFT_VIQ_DESC_MODE_8821C)\n#define BITS_VIQ_DESC_MODE_8821C                                               \\\n\t(BIT_MASK_VIQ_DESC_MODE_8821C << BIT_SHIFT_VIQ_DESC_MODE_8821C)\n#define BIT_CLEAR_VIQ_DESC_MODE_8821C(x) ((x) & (~BITS_VIQ_DESC_MODE_8821C))\n#define BIT_GET_VIQ_DESC_MODE_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_VIQ_DESC_MODE_8821C) & BIT_MASK_VIQ_DESC_MODE_8821C)\n#define BIT_SET_VIQ_DESC_MODE_8821C(x, v)                                      \\\n\t(BIT_CLEAR_VIQ_DESC_MODE_8821C(x) | BIT_VIQ_DESC_MODE_8821C(v))\n\n#define BIT_SHIFT_VIQ_DESC_NUM_8821C 0\n#define BIT_MASK_VIQ_DESC_NUM_8821C 0xfff\n#define BIT_VIQ_DESC_NUM_8821C(x)                                              \\\n\t(((x) & BIT_MASK_VIQ_DESC_NUM_8821C) << BIT_SHIFT_VIQ_DESC_NUM_8821C)\n#define BITS_VIQ_DESC_NUM_8821C                                                \\\n\t(BIT_MASK_VIQ_DESC_NUM_8821C << BIT_SHIFT_VIQ_DESC_NUM_8821C)\n#define BIT_CLEAR_VIQ_DESC_NUM_8821C(x) ((x) & (~BITS_VIQ_DESC_NUM_8821C))\n#define BIT_GET_VIQ_DESC_NUM_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_VIQ_DESC_NUM_8821C) & BIT_MASK_VIQ_DESC_NUM_8821C)\n#define BIT_SET_VIQ_DESC_NUM_8821C(x, v)                                       \\\n\t(BIT_CLEAR_VIQ_DESC_NUM_8821C(x) | BIT_VIQ_DESC_NUM_8821C(v))\n\n/* 2 REG_BEQ_TXBD_NUM_8821C */\n#define BIT_PCIE_BEQ_FLAG_8821C BIT(14)\n\n#define BIT_SHIFT_BEQ_DESC_MODE_8821C 12\n#define BIT_MASK_BEQ_DESC_MODE_8821C 0x3\n#define BIT_BEQ_DESC_MODE_8821C(x)                                             \\\n\t(((x) & BIT_MASK_BEQ_DESC_MODE_8821C) << BIT_SHIFT_BEQ_DESC_MODE_8821C)\n#define BITS_BEQ_DESC_MODE_8821C                                               \\\n\t(BIT_MASK_BEQ_DESC_MODE_8821C << BIT_SHIFT_BEQ_DESC_MODE_8821C)\n#define BIT_CLEAR_BEQ_DESC_MODE_8821C(x) ((x) & (~BITS_BEQ_DESC_MODE_8821C))\n#define BIT_GET_BEQ_DESC_MODE_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BEQ_DESC_MODE_8821C) & BIT_MASK_BEQ_DESC_MODE_8821C)\n#define BIT_SET_BEQ_DESC_MODE_8821C(x, v)                                      \\\n\t(BIT_CLEAR_BEQ_DESC_MODE_8821C(x) | BIT_BEQ_DESC_MODE_8821C(v))\n\n#define BIT_SHIFT_BEQ_DESC_NUM_8821C 0\n#define BIT_MASK_BEQ_DESC_NUM_8821C 0xfff\n#define BIT_BEQ_DESC_NUM_8821C(x)                                              \\\n\t(((x) & BIT_MASK_BEQ_DESC_NUM_8821C) << BIT_SHIFT_BEQ_DESC_NUM_8821C)\n#define BITS_BEQ_DESC_NUM_8821C                                                \\\n\t(BIT_MASK_BEQ_DESC_NUM_8821C << BIT_SHIFT_BEQ_DESC_NUM_8821C)\n#define BIT_CLEAR_BEQ_DESC_NUM_8821C(x) ((x) & (~BITS_BEQ_DESC_NUM_8821C))\n#define BIT_GET_BEQ_DESC_NUM_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BEQ_DESC_NUM_8821C) & BIT_MASK_BEQ_DESC_NUM_8821C)\n#define BIT_SET_BEQ_DESC_NUM_8821C(x, v)                                       \\\n\t(BIT_CLEAR_BEQ_DESC_NUM_8821C(x) | BIT_BEQ_DESC_NUM_8821C(v))\n\n/* 2 REG_BKQ_TXBD_NUM_8821C */\n#define BIT_PCIE_BKQ_FLAG_8821C BIT(14)\n\n#define BIT_SHIFT_BKQ_DESC_MODE_8821C 12\n#define BIT_MASK_BKQ_DESC_MODE_8821C 0x3\n#define BIT_BKQ_DESC_MODE_8821C(x)                                             \\\n\t(((x) & BIT_MASK_BKQ_DESC_MODE_8821C) << BIT_SHIFT_BKQ_DESC_MODE_8821C)\n#define BITS_BKQ_DESC_MODE_8821C                                               \\\n\t(BIT_MASK_BKQ_DESC_MODE_8821C << BIT_SHIFT_BKQ_DESC_MODE_8821C)\n#define BIT_CLEAR_BKQ_DESC_MODE_8821C(x) ((x) & (~BITS_BKQ_DESC_MODE_8821C))\n#define BIT_GET_BKQ_DESC_MODE_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BKQ_DESC_MODE_8821C) & BIT_MASK_BKQ_DESC_MODE_8821C)\n#define BIT_SET_BKQ_DESC_MODE_8821C(x, v)                                      \\\n\t(BIT_CLEAR_BKQ_DESC_MODE_8821C(x) | BIT_BKQ_DESC_MODE_8821C(v))\n\n#define BIT_SHIFT_BKQ_DESC_NUM_8821C 0\n#define BIT_MASK_BKQ_DESC_NUM_8821C 0xfff\n#define BIT_BKQ_DESC_NUM_8821C(x)                                              \\\n\t(((x) & BIT_MASK_BKQ_DESC_NUM_8821C) << BIT_SHIFT_BKQ_DESC_NUM_8821C)\n#define BITS_BKQ_DESC_NUM_8821C                                                \\\n\t(BIT_MASK_BKQ_DESC_NUM_8821C << BIT_SHIFT_BKQ_DESC_NUM_8821C)\n#define BIT_CLEAR_BKQ_DESC_NUM_8821C(x) ((x) & (~BITS_BKQ_DESC_NUM_8821C))\n#define BIT_GET_BKQ_DESC_NUM_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BKQ_DESC_NUM_8821C) & BIT_MASK_BKQ_DESC_NUM_8821C)\n#define BIT_SET_BKQ_DESC_NUM_8821C(x, v)                                       \\\n\t(BIT_CLEAR_BKQ_DESC_NUM_8821C(x) | BIT_BKQ_DESC_NUM_8821C(v))\n\n/* 2 REG_HI0Q_TXBD_NUM_8821C */\n#define BIT_HI0Q_FLAG_8821C BIT(14)\n\n#define BIT_SHIFT_HI0Q_DESC_MODE_8821C 12\n#define BIT_MASK_HI0Q_DESC_MODE_8821C 0x3\n#define BIT_HI0Q_DESC_MODE_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HI0Q_DESC_MODE_8821C)                                 \\\n\t << BIT_SHIFT_HI0Q_DESC_MODE_8821C)\n#define BITS_HI0Q_DESC_MODE_8821C                                              \\\n\t(BIT_MASK_HI0Q_DESC_MODE_8821C << BIT_SHIFT_HI0Q_DESC_MODE_8821C)\n#define BIT_CLEAR_HI0Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI0Q_DESC_MODE_8821C))\n#define BIT_GET_HI0Q_DESC_MODE_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8821C) &                             \\\n\t BIT_MASK_HI0Q_DESC_MODE_8821C)\n#define BIT_SET_HI0Q_DESC_MODE_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HI0Q_DESC_MODE_8821C(x) | BIT_HI0Q_DESC_MODE_8821C(v))\n\n#define BIT_SHIFT_HI0Q_DESC_NUM_8821C 0\n#define BIT_MASK_HI0Q_DESC_NUM_8821C 0xfff\n#define BIT_HI0Q_DESC_NUM_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HI0Q_DESC_NUM_8821C) << BIT_SHIFT_HI0Q_DESC_NUM_8821C)\n#define BITS_HI0Q_DESC_NUM_8821C                                               \\\n\t(BIT_MASK_HI0Q_DESC_NUM_8821C << BIT_SHIFT_HI0Q_DESC_NUM_8821C)\n#define BIT_CLEAR_HI0Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI0Q_DESC_NUM_8821C))\n#define BIT_GET_HI0Q_DESC_NUM_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8821C) & BIT_MASK_HI0Q_DESC_NUM_8821C)\n#define BIT_SET_HI0Q_DESC_NUM_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HI0Q_DESC_NUM_8821C(x) | BIT_HI0Q_DESC_NUM_8821C(v))\n\n/* 2 REG_HI1Q_TXBD_NUM_8821C */\n#define BIT_HI1Q_FLAG_8821C BIT(14)\n\n#define BIT_SHIFT_HI1Q_DESC_MODE_8821C 12\n#define BIT_MASK_HI1Q_DESC_MODE_8821C 0x3\n#define BIT_HI1Q_DESC_MODE_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HI1Q_DESC_MODE_8821C)                                 \\\n\t << BIT_SHIFT_HI1Q_DESC_MODE_8821C)\n#define BITS_HI1Q_DESC_MODE_8821C                                              \\\n\t(BIT_MASK_HI1Q_DESC_MODE_8821C << BIT_SHIFT_HI1Q_DESC_MODE_8821C)\n#define BIT_CLEAR_HI1Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI1Q_DESC_MODE_8821C))\n#define BIT_GET_HI1Q_DESC_MODE_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8821C) &                             \\\n\t BIT_MASK_HI1Q_DESC_MODE_8821C)\n#define BIT_SET_HI1Q_DESC_MODE_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HI1Q_DESC_MODE_8821C(x) | BIT_HI1Q_DESC_MODE_8821C(v))\n\n#define BIT_SHIFT_HI1Q_DESC_NUM_8821C 0\n#define BIT_MASK_HI1Q_DESC_NUM_8821C 0xfff\n#define BIT_HI1Q_DESC_NUM_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HI1Q_DESC_NUM_8821C) << BIT_SHIFT_HI1Q_DESC_NUM_8821C)\n#define BITS_HI1Q_DESC_NUM_8821C                                               \\\n\t(BIT_MASK_HI1Q_DESC_NUM_8821C << BIT_SHIFT_HI1Q_DESC_NUM_8821C)\n#define BIT_CLEAR_HI1Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI1Q_DESC_NUM_8821C))\n#define BIT_GET_HI1Q_DESC_NUM_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8821C) & BIT_MASK_HI1Q_DESC_NUM_8821C)\n#define BIT_SET_HI1Q_DESC_NUM_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HI1Q_DESC_NUM_8821C(x) | BIT_HI1Q_DESC_NUM_8821C(v))\n\n/* 2 REG_HI2Q_TXBD_NUM_8821C */\n#define BIT_HI2Q_FLAG_8821C BIT(14)\n\n#define BIT_SHIFT_HI2Q_DESC_MODE_8821C 12\n#define BIT_MASK_HI2Q_DESC_MODE_8821C 0x3\n#define BIT_HI2Q_DESC_MODE_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HI2Q_DESC_MODE_8821C)                                 \\\n\t << BIT_SHIFT_HI2Q_DESC_MODE_8821C)\n#define BITS_HI2Q_DESC_MODE_8821C                                              \\\n\t(BIT_MASK_HI2Q_DESC_MODE_8821C << BIT_SHIFT_HI2Q_DESC_MODE_8821C)\n#define BIT_CLEAR_HI2Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI2Q_DESC_MODE_8821C))\n#define BIT_GET_HI2Q_DESC_MODE_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8821C) &                             \\\n\t BIT_MASK_HI2Q_DESC_MODE_8821C)\n#define BIT_SET_HI2Q_DESC_MODE_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HI2Q_DESC_MODE_8821C(x) | BIT_HI2Q_DESC_MODE_8821C(v))\n\n#define BIT_SHIFT_HI2Q_DESC_NUM_8821C 0\n#define BIT_MASK_HI2Q_DESC_NUM_8821C 0xfff\n#define BIT_HI2Q_DESC_NUM_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HI2Q_DESC_NUM_8821C) << BIT_SHIFT_HI2Q_DESC_NUM_8821C)\n#define BITS_HI2Q_DESC_NUM_8821C                                               \\\n\t(BIT_MASK_HI2Q_DESC_NUM_8821C << BIT_SHIFT_HI2Q_DESC_NUM_8821C)\n#define BIT_CLEAR_HI2Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI2Q_DESC_NUM_8821C))\n#define BIT_GET_HI2Q_DESC_NUM_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8821C) & BIT_MASK_HI2Q_DESC_NUM_8821C)\n#define BIT_SET_HI2Q_DESC_NUM_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HI2Q_DESC_NUM_8821C(x) | BIT_HI2Q_DESC_NUM_8821C(v))\n\n/* 2 REG_HI3Q_TXBD_NUM_8821C */\n#define BIT_HI3Q_FLAG_8821C BIT(14)\n\n#define BIT_SHIFT_HI3Q_DESC_MODE_8821C 12\n#define BIT_MASK_HI3Q_DESC_MODE_8821C 0x3\n#define BIT_HI3Q_DESC_MODE_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HI3Q_DESC_MODE_8821C)                                 \\\n\t << BIT_SHIFT_HI3Q_DESC_MODE_8821C)\n#define BITS_HI3Q_DESC_MODE_8821C                                              \\\n\t(BIT_MASK_HI3Q_DESC_MODE_8821C << BIT_SHIFT_HI3Q_DESC_MODE_8821C)\n#define BIT_CLEAR_HI3Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI3Q_DESC_MODE_8821C))\n#define BIT_GET_HI3Q_DESC_MODE_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8821C) &                             \\\n\t BIT_MASK_HI3Q_DESC_MODE_8821C)\n#define BIT_SET_HI3Q_DESC_MODE_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HI3Q_DESC_MODE_8821C(x) | BIT_HI3Q_DESC_MODE_8821C(v))\n\n#define BIT_SHIFT_HI3Q_DESC_NUM_8821C 0\n#define BIT_MASK_HI3Q_DESC_NUM_8821C 0xfff\n#define BIT_HI3Q_DESC_NUM_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HI3Q_DESC_NUM_8821C) << BIT_SHIFT_HI3Q_DESC_NUM_8821C)\n#define BITS_HI3Q_DESC_NUM_8821C                                               \\\n\t(BIT_MASK_HI3Q_DESC_NUM_8821C << BIT_SHIFT_HI3Q_DESC_NUM_8821C)\n#define BIT_CLEAR_HI3Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI3Q_DESC_NUM_8821C))\n#define BIT_GET_HI3Q_DESC_NUM_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8821C) & BIT_MASK_HI3Q_DESC_NUM_8821C)\n#define BIT_SET_HI3Q_DESC_NUM_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HI3Q_DESC_NUM_8821C(x) | BIT_HI3Q_DESC_NUM_8821C(v))\n\n/* 2 REG_HI4Q_TXBD_NUM_8821C */\n#define BIT_HI4Q_FLAG_8821C BIT(14)\n\n#define BIT_SHIFT_HI4Q_DESC_MODE_8821C 12\n#define BIT_MASK_HI4Q_DESC_MODE_8821C 0x3\n#define BIT_HI4Q_DESC_MODE_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HI4Q_DESC_MODE_8821C)                                 \\\n\t << BIT_SHIFT_HI4Q_DESC_MODE_8821C)\n#define BITS_HI4Q_DESC_MODE_8821C                                              \\\n\t(BIT_MASK_HI4Q_DESC_MODE_8821C << BIT_SHIFT_HI4Q_DESC_MODE_8821C)\n#define BIT_CLEAR_HI4Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI4Q_DESC_MODE_8821C))\n#define BIT_GET_HI4Q_DESC_MODE_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8821C) &                             \\\n\t BIT_MASK_HI4Q_DESC_MODE_8821C)\n#define BIT_SET_HI4Q_DESC_MODE_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HI4Q_DESC_MODE_8821C(x) | BIT_HI4Q_DESC_MODE_8821C(v))\n\n#define BIT_SHIFT_HI4Q_DESC_NUM_8821C 0\n#define BIT_MASK_HI4Q_DESC_NUM_8821C 0xfff\n#define BIT_HI4Q_DESC_NUM_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HI4Q_DESC_NUM_8821C) << BIT_SHIFT_HI4Q_DESC_NUM_8821C)\n#define BITS_HI4Q_DESC_NUM_8821C                                               \\\n\t(BIT_MASK_HI4Q_DESC_NUM_8821C << BIT_SHIFT_HI4Q_DESC_NUM_8821C)\n#define BIT_CLEAR_HI4Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI4Q_DESC_NUM_8821C))\n#define BIT_GET_HI4Q_DESC_NUM_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8821C) & BIT_MASK_HI4Q_DESC_NUM_8821C)\n#define BIT_SET_HI4Q_DESC_NUM_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HI4Q_DESC_NUM_8821C(x) | BIT_HI4Q_DESC_NUM_8821C(v))\n\n/* 2 REG_HI5Q_TXBD_NUM_8821C */\n#define BIT_HI5Q_FLAG_8821C BIT(14)\n\n#define BIT_SHIFT_HI5Q_DESC_MODE_8821C 12\n#define BIT_MASK_HI5Q_DESC_MODE_8821C 0x3\n#define BIT_HI5Q_DESC_MODE_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HI5Q_DESC_MODE_8821C)                                 \\\n\t << BIT_SHIFT_HI5Q_DESC_MODE_8821C)\n#define BITS_HI5Q_DESC_MODE_8821C                                              \\\n\t(BIT_MASK_HI5Q_DESC_MODE_8821C << BIT_SHIFT_HI5Q_DESC_MODE_8821C)\n#define BIT_CLEAR_HI5Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI5Q_DESC_MODE_8821C))\n#define BIT_GET_HI5Q_DESC_MODE_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8821C) &                             \\\n\t BIT_MASK_HI5Q_DESC_MODE_8821C)\n#define BIT_SET_HI5Q_DESC_MODE_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HI5Q_DESC_MODE_8821C(x) | BIT_HI5Q_DESC_MODE_8821C(v))\n\n#define BIT_SHIFT_HI5Q_DESC_NUM_8821C 0\n#define BIT_MASK_HI5Q_DESC_NUM_8821C 0xfff\n#define BIT_HI5Q_DESC_NUM_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HI5Q_DESC_NUM_8821C) << BIT_SHIFT_HI5Q_DESC_NUM_8821C)\n#define BITS_HI5Q_DESC_NUM_8821C                                               \\\n\t(BIT_MASK_HI5Q_DESC_NUM_8821C << BIT_SHIFT_HI5Q_DESC_NUM_8821C)\n#define BIT_CLEAR_HI5Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI5Q_DESC_NUM_8821C))\n#define BIT_GET_HI5Q_DESC_NUM_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8821C) & BIT_MASK_HI5Q_DESC_NUM_8821C)\n#define BIT_SET_HI5Q_DESC_NUM_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HI5Q_DESC_NUM_8821C(x) | BIT_HI5Q_DESC_NUM_8821C(v))\n\n/* 2 REG_HI6Q_TXBD_NUM_8821C */\n#define BIT_HI6Q_FLAG_8821C BIT(14)\n\n#define BIT_SHIFT_HI6Q_DESC_MODE_8821C 12\n#define BIT_MASK_HI6Q_DESC_MODE_8821C 0x3\n#define BIT_HI6Q_DESC_MODE_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HI6Q_DESC_MODE_8821C)                                 \\\n\t << BIT_SHIFT_HI6Q_DESC_MODE_8821C)\n#define BITS_HI6Q_DESC_MODE_8821C                                              \\\n\t(BIT_MASK_HI6Q_DESC_MODE_8821C << BIT_SHIFT_HI6Q_DESC_MODE_8821C)\n#define BIT_CLEAR_HI6Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI6Q_DESC_MODE_8821C))\n#define BIT_GET_HI6Q_DESC_MODE_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8821C) &                             \\\n\t BIT_MASK_HI6Q_DESC_MODE_8821C)\n#define BIT_SET_HI6Q_DESC_MODE_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HI6Q_DESC_MODE_8821C(x) | BIT_HI6Q_DESC_MODE_8821C(v))\n\n#define BIT_SHIFT_HI6Q_DESC_NUM_8821C 0\n#define BIT_MASK_HI6Q_DESC_NUM_8821C 0xfff\n#define BIT_HI6Q_DESC_NUM_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HI6Q_DESC_NUM_8821C) << BIT_SHIFT_HI6Q_DESC_NUM_8821C)\n#define BITS_HI6Q_DESC_NUM_8821C                                               \\\n\t(BIT_MASK_HI6Q_DESC_NUM_8821C << BIT_SHIFT_HI6Q_DESC_NUM_8821C)\n#define BIT_CLEAR_HI6Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI6Q_DESC_NUM_8821C))\n#define BIT_GET_HI6Q_DESC_NUM_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8821C) & BIT_MASK_HI6Q_DESC_NUM_8821C)\n#define BIT_SET_HI6Q_DESC_NUM_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HI6Q_DESC_NUM_8821C(x) | BIT_HI6Q_DESC_NUM_8821C(v))\n\n/* 2 REG_HI7Q_TXBD_NUM_8821C */\n#define BIT_HI7Q_FLAG_8821C BIT(14)\n\n#define BIT_SHIFT_HI7Q_DESC_MODE_8821C 12\n#define BIT_MASK_HI7Q_DESC_MODE_8821C 0x3\n#define BIT_HI7Q_DESC_MODE_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HI7Q_DESC_MODE_8821C)                                 \\\n\t << BIT_SHIFT_HI7Q_DESC_MODE_8821C)\n#define BITS_HI7Q_DESC_MODE_8821C                                              \\\n\t(BIT_MASK_HI7Q_DESC_MODE_8821C << BIT_SHIFT_HI7Q_DESC_MODE_8821C)\n#define BIT_CLEAR_HI7Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI7Q_DESC_MODE_8821C))\n#define BIT_GET_HI7Q_DESC_MODE_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8821C) &                             \\\n\t BIT_MASK_HI7Q_DESC_MODE_8821C)\n#define BIT_SET_HI7Q_DESC_MODE_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HI7Q_DESC_MODE_8821C(x) | BIT_HI7Q_DESC_MODE_8821C(v))\n\n#define BIT_SHIFT_HI7Q_DESC_NUM_8821C 0\n#define BIT_MASK_HI7Q_DESC_NUM_8821C 0xfff\n#define BIT_HI7Q_DESC_NUM_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HI7Q_DESC_NUM_8821C) << BIT_SHIFT_HI7Q_DESC_NUM_8821C)\n#define BITS_HI7Q_DESC_NUM_8821C                                               \\\n\t(BIT_MASK_HI7Q_DESC_NUM_8821C << BIT_SHIFT_HI7Q_DESC_NUM_8821C)\n#define BIT_CLEAR_HI7Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI7Q_DESC_NUM_8821C))\n#define BIT_GET_HI7Q_DESC_NUM_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8821C) & BIT_MASK_HI7Q_DESC_NUM_8821C)\n#define BIT_SET_HI7Q_DESC_NUM_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HI7Q_DESC_NUM_8821C(x) | BIT_HI7Q_DESC_NUM_8821C(v))\n\n/* 2 REG_TSFTIMER_HCI_8821C */\n\n#define BIT_SHIFT_TSFT2_HCI_8821C 16\n#define BIT_MASK_TSFT2_HCI_8821C 0xffff\n#define BIT_TSFT2_HCI_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_TSFT2_HCI_8821C) << BIT_SHIFT_TSFT2_HCI_8821C)\n#define BITS_TSFT2_HCI_8821C                                                   \\\n\t(BIT_MASK_TSFT2_HCI_8821C << BIT_SHIFT_TSFT2_HCI_8821C)\n#define BIT_CLEAR_TSFT2_HCI_8821C(x) ((x) & (~BITS_TSFT2_HCI_8821C))\n#define BIT_GET_TSFT2_HCI_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_TSFT2_HCI_8821C) & BIT_MASK_TSFT2_HCI_8821C)\n#define BIT_SET_TSFT2_HCI_8821C(x, v)                                          \\\n\t(BIT_CLEAR_TSFT2_HCI_8821C(x) | BIT_TSFT2_HCI_8821C(v))\n\n#define BIT_SHIFT_TSFT1_HCI_8821C 0\n#define BIT_MASK_TSFT1_HCI_8821C 0xffff\n#define BIT_TSFT1_HCI_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_TSFT1_HCI_8821C) << BIT_SHIFT_TSFT1_HCI_8821C)\n#define BITS_TSFT1_HCI_8821C                                                   \\\n\t(BIT_MASK_TSFT1_HCI_8821C << BIT_SHIFT_TSFT1_HCI_8821C)\n#define BIT_CLEAR_TSFT1_HCI_8821C(x) ((x) & (~BITS_TSFT1_HCI_8821C))\n#define BIT_GET_TSFT1_HCI_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_TSFT1_HCI_8821C) & BIT_MASK_TSFT1_HCI_8821C)\n#define BIT_SET_TSFT1_HCI_8821C(x, v)                                          \\\n\t(BIT_CLEAR_TSFT1_HCI_8821C(x) | BIT_TSFT1_HCI_8821C(v))\n\n/* 2 REG_BD_RWPTR_CLR_8821C */\n#define BIT_CLR_HI7Q_HW_IDX_8821C BIT(29)\n#define BIT_CLR_HI6Q_HW_IDX_8821C BIT(28)\n#define BIT_CLR_HI5Q_HW_IDX_8821C BIT(27)\n#define BIT_CLR_HI4Q_HW_IDX_8821C BIT(26)\n#define BIT_CLR_HI3Q_HW_IDX_8821C BIT(25)\n#define BIT_CLR_HI2Q_HW_IDX_8821C BIT(24)\n#define BIT_CLR_HI1Q_HW_IDX_8821C BIT(23)\n#define BIT_CLR_HI0Q_HW_IDX_8821C BIT(22)\n#define BIT_CLR_BKQ_HW_IDX_8821C BIT(21)\n#define BIT_CLR_BEQ_HW_IDX_8821C BIT(20)\n#define BIT_CLR_VIQ_HW_IDX_8821C BIT(19)\n#define BIT_CLR_VOQ_HW_IDX_8821C BIT(18)\n#define BIT_CLR_MGQ_HW_IDX_8821C BIT(17)\n#define BIT_CLR_RXQ_HW_IDX_8821C BIT(16)\n#define BIT_CLR_HI7Q_HOST_IDX_8821C BIT(13)\n#define BIT_CLR_HI6Q_HOST_IDX_8821C BIT(12)\n#define BIT_CLR_HI5Q_HOST_IDX_8821C BIT(11)\n#define BIT_CLR_HI4Q_HOST_IDX_8821C BIT(10)\n#define BIT_CLR_HI3Q_HOST_IDX_8821C BIT(9)\n#define BIT_CLR_HI2Q_HOST_IDX_8821C BIT(8)\n#define BIT_CLR_HI1Q_HOST_IDX_8821C BIT(7)\n#define BIT_CLR_HI0Q_HOST_IDX_8821C BIT(6)\n#define BIT_CLR_BKQ_HOST_IDX_8821C BIT(5)\n#define BIT_CLR_BEQ_HOST_IDX_8821C BIT(4)\n#define BIT_CLR_VIQ_HOST_IDX_8821C BIT(3)\n#define BIT_CLR_VOQ_HOST_IDX_8821C BIT(2)\n#define BIT_CLR_MGQ_HOST_IDX_8821C BIT(1)\n#define BIT_CLR_RXQ_HOST_IDX_8821C BIT(0)\n\n/* 2 REG_VOQ_TXBD_IDX_8821C */\n\n#define BIT_SHIFT_VOQ_HW_IDX_8821C 16\n#define BIT_MASK_VOQ_HW_IDX_8821C 0xfff\n#define BIT_VOQ_HW_IDX_8821C(x)                                                \\\n\t(((x) & BIT_MASK_VOQ_HW_IDX_8821C) << BIT_SHIFT_VOQ_HW_IDX_8821C)\n#define BITS_VOQ_HW_IDX_8821C                                                  \\\n\t(BIT_MASK_VOQ_HW_IDX_8821C << BIT_SHIFT_VOQ_HW_IDX_8821C)\n#define BIT_CLEAR_VOQ_HW_IDX_8821C(x) ((x) & (~BITS_VOQ_HW_IDX_8821C))\n#define BIT_GET_VOQ_HW_IDX_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_VOQ_HW_IDX_8821C) & BIT_MASK_VOQ_HW_IDX_8821C)\n#define BIT_SET_VOQ_HW_IDX_8821C(x, v)                                         \\\n\t(BIT_CLEAR_VOQ_HW_IDX_8821C(x) | BIT_VOQ_HW_IDX_8821C(v))\n\n#define BIT_SHIFT_VOQ_HOST_IDX_8821C 0\n#define BIT_MASK_VOQ_HOST_IDX_8821C 0xfff\n#define BIT_VOQ_HOST_IDX_8821C(x)                                              \\\n\t(((x) & BIT_MASK_VOQ_HOST_IDX_8821C) << BIT_SHIFT_VOQ_HOST_IDX_8821C)\n#define BITS_VOQ_HOST_IDX_8821C                                                \\\n\t(BIT_MASK_VOQ_HOST_IDX_8821C << BIT_SHIFT_VOQ_HOST_IDX_8821C)\n#define BIT_CLEAR_VOQ_HOST_IDX_8821C(x) ((x) & (~BITS_VOQ_HOST_IDX_8821C))\n#define BIT_GET_VOQ_HOST_IDX_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_VOQ_HOST_IDX_8821C) & BIT_MASK_VOQ_HOST_IDX_8821C)\n#define BIT_SET_VOQ_HOST_IDX_8821C(x, v)                                       \\\n\t(BIT_CLEAR_VOQ_HOST_IDX_8821C(x) | BIT_VOQ_HOST_IDX_8821C(v))\n\n/* 2 REG_VIQ_TXBD_IDX_8821C */\n\n#define BIT_SHIFT_VIQ_HW_IDX_8821C 16\n#define BIT_MASK_VIQ_HW_IDX_8821C 0xfff\n#define BIT_VIQ_HW_IDX_8821C(x)                                                \\\n\t(((x) & BIT_MASK_VIQ_HW_IDX_8821C) << BIT_SHIFT_VIQ_HW_IDX_8821C)\n#define BITS_VIQ_HW_IDX_8821C                                                  \\\n\t(BIT_MASK_VIQ_HW_IDX_8821C << BIT_SHIFT_VIQ_HW_IDX_8821C)\n#define BIT_CLEAR_VIQ_HW_IDX_8821C(x) ((x) & (~BITS_VIQ_HW_IDX_8821C))\n#define BIT_GET_VIQ_HW_IDX_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_VIQ_HW_IDX_8821C) & BIT_MASK_VIQ_HW_IDX_8821C)\n#define BIT_SET_VIQ_HW_IDX_8821C(x, v)                                         \\\n\t(BIT_CLEAR_VIQ_HW_IDX_8821C(x) | BIT_VIQ_HW_IDX_8821C(v))\n\n#define BIT_SHIFT_VIQ_HOST_IDX_8821C 0\n#define BIT_MASK_VIQ_HOST_IDX_8821C 0xfff\n#define BIT_VIQ_HOST_IDX_8821C(x)                                              \\\n\t(((x) & BIT_MASK_VIQ_HOST_IDX_8821C) << BIT_SHIFT_VIQ_HOST_IDX_8821C)\n#define BITS_VIQ_HOST_IDX_8821C                                                \\\n\t(BIT_MASK_VIQ_HOST_IDX_8821C << BIT_SHIFT_VIQ_HOST_IDX_8821C)\n#define BIT_CLEAR_VIQ_HOST_IDX_8821C(x) ((x) & (~BITS_VIQ_HOST_IDX_8821C))\n#define BIT_GET_VIQ_HOST_IDX_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_VIQ_HOST_IDX_8821C) & BIT_MASK_VIQ_HOST_IDX_8821C)\n#define BIT_SET_VIQ_HOST_IDX_8821C(x, v)                                       \\\n\t(BIT_CLEAR_VIQ_HOST_IDX_8821C(x) | BIT_VIQ_HOST_IDX_8821C(v))\n\n/* 2 REG_BEQ_TXBD_IDX_8821C */\n\n#define BIT_SHIFT_BEQ_HW_IDX_8821C 16\n#define BIT_MASK_BEQ_HW_IDX_8821C 0xfff\n#define BIT_BEQ_HW_IDX_8821C(x)                                                \\\n\t(((x) & BIT_MASK_BEQ_HW_IDX_8821C) << BIT_SHIFT_BEQ_HW_IDX_8821C)\n#define BITS_BEQ_HW_IDX_8821C                                                  \\\n\t(BIT_MASK_BEQ_HW_IDX_8821C << BIT_SHIFT_BEQ_HW_IDX_8821C)\n#define BIT_CLEAR_BEQ_HW_IDX_8821C(x) ((x) & (~BITS_BEQ_HW_IDX_8821C))\n#define BIT_GET_BEQ_HW_IDX_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BEQ_HW_IDX_8821C) & BIT_MASK_BEQ_HW_IDX_8821C)\n#define BIT_SET_BEQ_HW_IDX_8821C(x, v)                                         \\\n\t(BIT_CLEAR_BEQ_HW_IDX_8821C(x) | BIT_BEQ_HW_IDX_8821C(v))\n\n#define BIT_SHIFT_BEQ_HOST_IDX_8821C 0\n#define BIT_MASK_BEQ_HOST_IDX_8821C 0xfff\n#define BIT_BEQ_HOST_IDX_8821C(x)                                              \\\n\t(((x) & BIT_MASK_BEQ_HOST_IDX_8821C) << BIT_SHIFT_BEQ_HOST_IDX_8821C)\n#define BITS_BEQ_HOST_IDX_8821C                                                \\\n\t(BIT_MASK_BEQ_HOST_IDX_8821C << BIT_SHIFT_BEQ_HOST_IDX_8821C)\n#define BIT_CLEAR_BEQ_HOST_IDX_8821C(x) ((x) & (~BITS_BEQ_HOST_IDX_8821C))\n#define BIT_GET_BEQ_HOST_IDX_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BEQ_HOST_IDX_8821C) & BIT_MASK_BEQ_HOST_IDX_8821C)\n#define BIT_SET_BEQ_HOST_IDX_8821C(x, v)                                       \\\n\t(BIT_CLEAR_BEQ_HOST_IDX_8821C(x) | BIT_BEQ_HOST_IDX_8821C(v))\n\n/* 2 REG_BKQ_TXBD_IDX_8821C */\n\n#define BIT_SHIFT_BKQ_HW_IDX_8821C 16\n#define BIT_MASK_BKQ_HW_IDX_8821C 0xfff\n#define BIT_BKQ_HW_IDX_8821C(x)                                                \\\n\t(((x) & BIT_MASK_BKQ_HW_IDX_8821C) << BIT_SHIFT_BKQ_HW_IDX_8821C)\n#define BITS_BKQ_HW_IDX_8821C                                                  \\\n\t(BIT_MASK_BKQ_HW_IDX_8821C << BIT_SHIFT_BKQ_HW_IDX_8821C)\n#define BIT_CLEAR_BKQ_HW_IDX_8821C(x) ((x) & (~BITS_BKQ_HW_IDX_8821C))\n#define BIT_GET_BKQ_HW_IDX_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BKQ_HW_IDX_8821C) & BIT_MASK_BKQ_HW_IDX_8821C)\n#define BIT_SET_BKQ_HW_IDX_8821C(x, v)                                         \\\n\t(BIT_CLEAR_BKQ_HW_IDX_8821C(x) | BIT_BKQ_HW_IDX_8821C(v))\n\n#define BIT_SHIFT_BKQ_HOST_IDX_8821C 0\n#define BIT_MASK_BKQ_HOST_IDX_8821C 0xfff\n#define BIT_BKQ_HOST_IDX_8821C(x)                                              \\\n\t(((x) & BIT_MASK_BKQ_HOST_IDX_8821C) << BIT_SHIFT_BKQ_HOST_IDX_8821C)\n#define BITS_BKQ_HOST_IDX_8821C                                                \\\n\t(BIT_MASK_BKQ_HOST_IDX_8821C << BIT_SHIFT_BKQ_HOST_IDX_8821C)\n#define BIT_CLEAR_BKQ_HOST_IDX_8821C(x) ((x) & (~BITS_BKQ_HOST_IDX_8821C))\n#define BIT_GET_BKQ_HOST_IDX_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BKQ_HOST_IDX_8821C) & BIT_MASK_BKQ_HOST_IDX_8821C)\n#define BIT_SET_BKQ_HOST_IDX_8821C(x, v)                                       \\\n\t(BIT_CLEAR_BKQ_HOST_IDX_8821C(x) | BIT_BKQ_HOST_IDX_8821C(v))\n\n/* 2 REG_MGQ_TXBD_IDX_8821C */\n\n#define BIT_SHIFT_MGQ_HW_IDX_8821C 16\n#define BIT_MASK_MGQ_HW_IDX_8821C 0xfff\n#define BIT_MGQ_HW_IDX_8821C(x)                                                \\\n\t(((x) & BIT_MASK_MGQ_HW_IDX_8821C) << BIT_SHIFT_MGQ_HW_IDX_8821C)\n#define BITS_MGQ_HW_IDX_8821C                                                  \\\n\t(BIT_MASK_MGQ_HW_IDX_8821C << BIT_SHIFT_MGQ_HW_IDX_8821C)\n#define BIT_CLEAR_MGQ_HW_IDX_8821C(x) ((x) & (~BITS_MGQ_HW_IDX_8821C))\n#define BIT_GET_MGQ_HW_IDX_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_MGQ_HW_IDX_8821C) & BIT_MASK_MGQ_HW_IDX_8821C)\n#define BIT_SET_MGQ_HW_IDX_8821C(x, v)                                         \\\n\t(BIT_CLEAR_MGQ_HW_IDX_8821C(x) | BIT_MGQ_HW_IDX_8821C(v))\n\n#define BIT_SHIFT_MGQ_HOST_IDX_8821C 0\n#define BIT_MASK_MGQ_HOST_IDX_8821C 0xfff\n#define BIT_MGQ_HOST_IDX_8821C(x)                                              \\\n\t(((x) & BIT_MASK_MGQ_HOST_IDX_8821C) << BIT_SHIFT_MGQ_HOST_IDX_8821C)\n#define BITS_MGQ_HOST_IDX_8821C                                                \\\n\t(BIT_MASK_MGQ_HOST_IDX_8821C << BIT_SHIFT_MGQ_HOST_IDX_8821C)\n#define BIT_CLEAR_MGQ_HOST_IDX_8821C(x) ((x) & (~BITS_MGQ_HOST_IDX_8821C))\n#define BIT_GET_MGQ_HOST_IDX_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_MGQ_HOST_IDX_8821C) & BIT_MASK_MGQ_HOST_IDX_8821C)\n#define BIT_SET_MGQ_HOST_IDX_8821C(x, v)                                       \\\n\t(BIT_CLEAR_MGQ_HOST_IDX_8821C(x) | BIT_MGQ_HOST_IDX_8821C(v))\n\n/* 2 REG_RXQ_RXBD_IDX_8821C */\n\n#define BIT_SHIFT_RXQ_HW_IDX_8821C 16\n#define BIT_MASK_RXQ_HW_IDX_8821C 0xfff\n#define BIT_RXQ_HW_IDX_8821C(x)                                                \\\n\t(((x) & BIT_MASK_RXQ_HW_IDX_8821C) << BIT_SHIFT_RXQ_HW_IDX_8821C)\n#define BITS_RXQ_HW_IDX_8821C                                                  \\\n\t(BIT_MASK_RXQ_HW_IDX_8821C << BIT_SHIFT_RXQ_HW_IDX_8821C)\n#define BIT_CLEAR_RXQ_HW_IDX_8821C(x) ((x) & (~BITS_RXQ_HW_IDX_8821C))\n#define BIT_GET_RXQ_HW_IDX_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXQ_HW_IDX_8821C) & BIT_MASK_RXQ_HW_IDX_8821C)\n#define BIT_SET_RXQ_HW_IDX_8821C(x, v)                                         \\\n\t(BIT_CLEAR_RXQ_HW_IDX_8821C(x) | BIT_RXQ_HW_IDX_8821C(v))\n\n#define BIT_SHIFT_RXQ_HOST_IDX_8821C 0\n#define BIT_MASK_RXQ_HOST_IDX_8821C 0xfff\n#define BIT_RXQ_HOST_IDX_8821C(x)                                              \\\n\t(((x) & BIT_MASK_RXQ_HOST_IDX_8821C) << BIT_SHIFT_RXQ_HOST_IDX_8821C)\n#define BITS_RXQ_HOST_IDX_8821C                                                \\\n\t(BIT_MASK_RXQ_HOST_IDX_8821C << BIT_SHIFT_RXQ_HOST_IDX_8821C)\n#define BIT_CLEAR_RXQ_HOST_IDX_8821C(x) ((x) & (~BITS_RXQ_HOST_IDX_8821C))\n#define BIT_GET_RXQ_HOST_IDX_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXQ_HOST_IDX_8821C) & BIT_MASK_RXQ_HOST_IDX_8821C)\n#define BIT_SET_RXQ_HOST_IDX_8821C(x, v)                                       \\\n\t(BIT_CLEAR_RXQ_HOST_IDX_8821C(x) | BIT_RXQ_HOST_IDX_8821C(v))\n\n/* 2 REG_HI0Q_TXBD_IDX_8821C */\n\n#define BIT_SHIFT_HI0Q_HW_IDX_8821C 16\n#define BIT_MASK_HI0Q_HW_IDX_8821C 0xfff\n#define BIT_HI0Q_HW_IDX_8821C(x)                                               \\\n\t(((x) & BIT_MASK_HI0Q_HW_IDX_8821C) << BIT_SHIFT_HI0Q_HW_IDX_8821C)\n#define BITS_HI0Q_HW_IDX_8821C                                                 \\\n\t(BIT_MASK_HI0Q_HW_IDX_8821C << BIT_SHIFT_HI0Q_HW_IDX_8821C)\n#define BIT_CLEAR_HI0Q_HW_IDX_8821C(x) ((x) & (~BITS_HI0Q_HW_IDX_8821C))\n#define BIT_GET_HI0Q_HW_IDX_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI0Q_HW_IDX_8821C) & BIT_MASK_HI0Q_HW_IDX_8821C)\n#define BIT_SET_HI0Q_HW_IDX_8821C(x, v)                                        \\\n\t(BIT_CLEAR_HI0Q_HW_IDX_8821C(x) | BIT_HI0Q_HW_IDX_8821C(v))\n\n#define BIT_SHIFT_HI0Q_HOST_IDX_8821C 0\n#define BIT_MASK_HI0Q_HOST_IDX_8821C 0xfff\n#define BIT_HI0Q_HOST_IDX_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HI0Q_HOST_IDX_8821C) << BIT_SHIFT_HI0Q_HOST_IDX_8821C)\n#define BITS_HI0Q_HOST_IDX_8821C                                               \\\n\t(BIT_MASK_HI0Q_HOST_IDX_8821C << BIT_SHIFT_HI0Q_HOST_IDX_8821C)\n#define BIT_CLEAR_HI0Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI0Q_HOST_IDX_8821C))\n#define BIT_GET_HI0Q_HOST_IDX_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8821C) & BIT_MASK_HI0Q_HOST_IDX_8821C)\n#define BIT_SET_HI0Q_HOST_IDX_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HI0Q_HOST_IDX_8821C(x) | BIT_HI0Q_HOST_IDX_8821C(v))\n\n/* 2 REG_HI1Q_TXBD_IDX_8821C */\n\n#define BIT_SHIFT_HI1Q_HW_IDX_8821C 16\n#define BIT_MASK_HI1Q_HW_IDX_8821C 0xfff\n#define BIT_HI1Q_HW_IDX_8821C(x)                                               \\\n\t(((x) & BIT_MASK_HI1Q_HW_IDX_8821C) << BIT_SHIFT_HI1Q_HW_IDX_8821C)\n#define BITS_HI1Q_HW_IDX_8821C                                                 \\\n\t(BIT_MASK_HI1Q_HW_IDX_8821C << BIT_SHIFT_HI1Q_HW_IDX_8821C)\n#define BIT_CLEAR_HI1Q_HW_IDX_8821C(x) ((x) & (~BITS_HI1Q_HW_IDX_8821C))\n#define BIT_GET_HI1Q_HW_IDX_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI1Q_HW_IDX_8821C) & BIT_MASK_HI1Q_HW_IDX_8821C)\n#define BIT_SET_HI1Q_HW_IDX_8821C(x, v)                                        \\\n\t(BIT_CLEAR_HI1Q_HW_IDX_8821C(x) | BIT_HI1Q_HW_IDX_8821C(v))\n\n#define BIT_SHIFT_HI1Q_HOST_IDX_8821C 0\n#define BIT_MASK_HI1Q_HOST_IDX_8821C 0xfff\n#define BIT_HI1Q_HOST_IDX_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HI1Q_HOST_IDX_8821C) << BIT_SHIFT_HI1Q_HOST_IDX_8821C)\n#define BITS_HI1Q_HOST_IDX_8821C                                               \\\n\t(BIT_MASK_HI1Q_HOST_IDX_8821C << BIT_SHIFT_HI1Q_HOST_IDX_8821C)\n#define BIT_CLEAR_HI1Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI1Q_HOST_IDX_8821C))\n#define BIT_GET_HI1Q_HOST_IDX_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8821C) & BIT_MASK_HI1Q_HOST_IDX_8821C)\n#define BIT_SET_HI1Q_HOST_IDX_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HI1Q_HOST_IDX_8821C(x) | BIT_HI1Q_HOST_IDX_8821C(v))\n\n/* 2 REG_HI2Q_TXBD_IDX_8821C */\n\n#define BIT_SHIFT_HI2Q_HW_IDX_8821C 16\n#define BIT_MASK_HI2Q_HW_IDX_8821C 0xfff\n#define BIT_HI2Q_HW_IDX_8821C(x)                                               \\\n\t(((x) & BIT_MASK_HI2Q_HW_IDX_8821C) << BIT_SHIFT_HI2Q_HW_IDX_8821C)\n#define BITS_HI2Q_HW_IDX_8821C                                                 \\\n\t(BIT_MASK_HI2Q_HW_IDX_8821C << BIT_SHIFT_HI2Q_HW_IDX_8821C)\n#define BIT_CLEAR_HI2Q_HW_IDX_8821C(x) ((x) & (~BITS_HI2Q_HW_IDX_8821C))\n#define BIT_GET_HI2Q_HW_IDX_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI2Q_HW_IDX_8821C) & BIT_MASK_HI2Q_HW_IDX_8821C)\n#define BIT_SET_HI2Q_HW_IDX_8821C(x, v)                                        \\\n\t(BIT_CLEAR_HI2Q_HW_IDX_8821C(x) | BIT_HI2Q_HW_IDX_8821C(v))\n\n#define BIT_SHIFT_HI2Q_HOST_IDX_8821C 0\n#define BIT_MASK_HI2Q_HOST_IDX_8821C 0xfff\n#define BIT_HI2Q_HOST_IDX_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HI2Q_HOST_IDX_8821C) << BIT_SHIFT_HI2Q_HOST_IDX_8821C)\n#define BITS_HI2Q_HOST_IDX_8821C                                               \\\n\t(BIT_MASK_HI2Q_HOST_IDX_8821C << BIT_SHIFT_HI2Q_HOST_IDX_8821C)\n#define BIT_CLEAR_HI2Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI2Q_HOST_IDX_8821C))\n#define BIT_GET_HI2Q_HOST_IDX_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8821C) & BIT_MASK_HI2Q_HOST_IDX_8821C)\n#define BIT_SET_HI2Q_HOST_IDX_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HI2Q_HOST_IDX_8821C(x) | BIT_HI2Q_HOST_IDX_8821C(v))\n\n/* 2 REG_HI3Q_TXBD_IDX_8821C */\n\n#define BIT_SHIFT_HI3Q_HW_IDX_8821C 16\n#define BIT_MASK_HI3Q_HW_IDX_8821C 0xfff\n#define BIT_HI3Q_HW_IDX_8821C(x)                                               \\\n\t(((x) & BIT_MASK_HI3Q_HW_IDX_8821C) << BIT_SHIFT_HI3Q_HW_IDX_8821C)\n#define BITS_HI3Q_HW_IDX_8821C                                                 \\\n\t(BIT_MASK_HI3Q_HW_IDX_8821C << BIT_SHIFT_HI3Q_HW_IDX_8821C)\n#define BIT_CLEAR_HI3Q_HW_IDX_8821C(x) ((x) & (~BITS_HI3Q_HW_IDX_8821C))\n#define BIT_GET_HI3Q_HW_IDX_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI3Q_HW_IDX_8821C) & BIT_MASK_HI3Q_HW_IDX_8821C)\n#define BIT_SET_HI3Q_HW_IDX_8821C(x, v)                                        \\\n\t(BIT_CLEAR_HI3Q_HW_IDX_8821C(x) | BIT_HI3Q_HW_IDX_8821C(v))\n\n#define BIT_SHIFT_HI3Q_HOST_IDX_8821C 0\n#define BIT_MASK_HI3Q_HOST_IDX_8821C 0xfff\n#define BIT_HI3Q_HOST_IDX_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HI3Q_HOST_IDX_8821C) << BIT_SHIFT_HI3Q_HOST_IDX_8821C)\n#define BITS_HI3Q_HOST_IDX_8821C                                               \\\n\t(BIT_MASK_HI3Q_HOST_IDX_8821C << BIT_SHIFT_HI3Q_HOST_IDX_8821C)\n#define BIT_CLEAR_HI3Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI3Q_HOST_IDX_8821C))\n#define BIT_GET_HI3Q_HOST_IDX_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8821C) & BIT_MASK_HI3Q_HOST_IDX_8821C)\n#define BIT_SET_HI3Q_HOST_IDX_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HI3Q_HOST_IDX_8821C(x) | BIT_HI3Q_HOST_IDX_8821C(v))\n\n/* 2 REG_HI4Q_TXBD_IDX_8821C */\n\n#define BIT_SHIFT_HI4Q_HW_IDX_8821C 16\n#define BIT_MASK_HI4Q_HW_IDX_8821C 0xfff\n#define BIT_HI4Q_HW_IDX_8821C(x)                                               \\\n\t(((x) & BIT_MASK_HI4Q_HW_IDX_8821C) << BIT_SHIFT_HI4Q_HW_IDX_8821C)\n#define BITS_HI4Q_HW_IDX_8821C                                                 \\\n\t(BIT_MASK_HI4Q_HW_IDX_8821C << BIT_SHIFT_HI4Q_HW_IDX_8821C)\n#define BIT_CLEAR_HI4Q_HW_IDX_8821C(x) ((x) & (~BITS_HI4Q_HW_IDX_8821C))\n#define BIT_GET_HI4Q_HW_IDX_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI4Q_HW_IDX_8821C) & BIT_MASK_HI4Q_HW_IDX_8821C)\n#define BIT_SET_HI4Q_HW_IDX_8821C(x, v)                                        \\\n\t(BIT_CLEAR_HI4Q_HW_IDX_8821C(x) | BIT_HI4Q_HW_IDX_8821C(v))\n\n#define BIT_SHIFT_HI4Q_HOST_IDX_8821C 0\n#define BIT_MASK_HI4Q_HOST_IDX_8821C 0xfff\n#define BIT_HI4Q_HOST_IDX_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HI4Q_HOST_IDX_8821C) << BIT_SHIFT_HI4Q_HOST_IDX_8821C)\n#define BITS_HI4Q_HOST_IDX_8821C                                               \\\n\t(BIT_MASK_HI4Q_HOST_IDX_8821C << BIT_SHIFT_HI4Q_HOST_IDX_8821C)\n#define BIT_CLEAR_HI4Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI4Q_HOST_IDX_8821C))\n#define BIT_GET_HI4Q_HOST_IDX_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8821C) & BIT_MASK_HI4Q_HOST_IDX_8821C)\n#define BIT_SET_HI4Q_HOST_IDX_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HI4Q_HOST_IDX_8821C(x) | BIT_HI4Q_HOST_IDX_8821C(v))\n\n/* 2 REG_HI5Q_TXBD_IDX_8821C */\n\n#define BIT_SHIFT_HI5Q_HW_IDX_8821C 16\n#define BIT_MASK_HI5Q_HW_IDX_8821C 0xfff\n#define BIT_HI5Q_HW_IDX_8821C(x)                                               \\\n\t(((x) & BIT_MASK_HI5Q_HW_IDX_8821C) << BIT_SHIFT_HI5Q_HW_IDX_8821C)\n#define BITS_HI5Q_HW_IDX_8821C                                                 \\\n\t(BIT_MASK_HI5Q_HW_IDX_8821C << BIT_SHIFT_HI5Q_HW_IDX_8821C)\n#define BIT_CLEAR_HI5Q_HW_IDX_8821C(x) ((x) & (~BITS_HI5Q_HW_IDX_8821C))\n#define BIT_GET_HI5Q_HW_IDX_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI5Q_HW_IDX_8821C) & BIT_MASK_HI5Q_HW_IDX_8821C)\n#define BIT_SET_HI5Q_HW_IDX_8821C(x, v)                                        \\\n\t(BIT_CLEAR_HI5Q_HW_IDX_8821C(x) | BIT_HI5Q_HW_IDX_8821C(v))\n\n#define BIT_SHIFT_HI5Q_HOST_IDX_8821C 0\n#define BIT_MASK_HI5Q_HOST_IDX_8821C 0xfff\n#define BIT_HI5Q_HOST_IDX_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HI5Q_HOST_IDX_8821C) << BIT_SHIFT_HI5Q_HOST_IDX_8821C)\n#define BITS_HI5Q_HOST_IDX_8821C                                               \\\n\t(BIT_MASK_HI5Q_HOST_IDX_8821C << BIT_SHIFT_HI5Q_HOST_IDX_8821C)\n#define BIT_CLEAR_HI5Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI5Q_HOST_IDX_8821C))\n#define BIT_GET_HI5Q_HOST_IDX_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8821C) & BIT_MASK_HI5Q_HOST_IDX_8821C)\n#define BIT_SET_HI5Q_HOST_IDX_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HI5Q_HOST_IDX_8821C(x) | BIT_HI5Q_HOST_IDX_8821C(v))\n\n/* 2 REG_HI6Q_TXBD_IDX_8821C */\n\n#define BIT_SHIFT_HI6Q_HW_IDX_8821C 16\n#define BIT_MASK_HI6Q_HW_IDX_8821C 0xfff\n#define BIT_HI6Q_HW_IDX_8821C(x)                                               \\\n\t(((x) & BIT_MASK_HI6Q_HW_IDX_8821C) << BIT_SHIFT_HI6Q_HW_IDX_8821C)\n#define BITS_HI6Q_HW_IDX_8821C                                                 \\\n\t(BIT_MASK_HI6Q_HW_IDX_8821C << BIT_SHIFT_HI6Q_HW_IDX_8821C)\n#define BIT_CLEAR_HI6Q_HW_IDX_8821C(x) ((x) & (~BITS_HI6Q_HW_IDX_8821C))\n#define BIT_GET_HI6Q_HW_IDX_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI6Q_HW_IDX_8821C) & BIT_MASK_HI6Q_HW_IDX_8821C)\n#define BIT_SET_HI6Q_HW_IDX_8821C(x, v)                                        \\\n\t(BIT_CLEAR_HI6Q_HW_IDX_8821C(x) | BIT_HI6Q_HW_IDX_8821C(v))\n\n#define BIT_SHIFT_HI6Q_HOST_IDX_8821C 0\n#define BIT_MASK_HI6Q_HOST_IDX_8821C 0xfff\n#define BIT_HI6Q_HOST_IDX_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HI6Q_HOST_IDX_8821C) << BIT_SHIFT_HI6Q_HOST_IDX_8821C)\n#define BITS_HI6Q_HOST_IDX_8821C                                               \\\n\t(BIT_MASK_HI6Q_HOST_IDX_8821C << BIT_SHIFT_HI6Q_HOST_IDX_8821C)\n#define BIT_CLEAR_HI6Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI6Q_HOST_IDX_8821C))\n#define BIT_GET_HI6Q_HOST_IDX_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8821C) & BIT_MASK_HI6Q_HOST_IDX_8821C)\n#define BIT_SET_HI6Q_HOST_IDX_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HI6Q_HOST_IDX_8821C(x) | BIT_HI6Q_HOST_IDX_8821C(v))\n\n/* 2 REG_HI7Q_TXBD_IDX_8821C */\n\n#define BIT_SHIFT_HI7Q_HW_IDX_8821C 16\n#define BIT_MASK_HI7Q_HW_IDX_8821C 0xfff\n#define BIT_HI7Q_HW_IDX_8821C(x)                                               \\\n\t(((x) & BIT_MASK_HI7Q_HW_IDX_8821C) << BIT_SHIFT_HI7Q_HW_IDX_8821C)\n#define BITS_HI7Q_HW_IDX_8821C                                                 \\\n\t(BIT_MASK_HI7Q_HW_IDX_8821C << BIT_SHIFT_HI7Q_HW_IDX_8821C)\n#define BIT_CLEAR_HI7Q_HW_IDX_8821C(x) ((x) & (~BITS_HI7Q_HW_IDX_8821C))\n#define BIT_GET_HI7Q_HW_IDX_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI7Q_HW_IDX_8821C) & BIT_MASK_HI7Q_HW_IDX_8821C)\n#define BIT_SET_HI7Q_HW_IDX_8821C(x, v)                                        \\\n\t(BIT_CLEAR_HI7Q_HW_IDX_8821C(x) | BIT_HI7Q_HW_IDX_8821C(v))\n\n#define BIT_SHIFT_HI7Q_HOST_IDX_8821C 0\n#define BIT_MASK_HI7Q_HOST_IDX_8821C 0xfff\n#define BIT_HI7Q_HOST_IDX_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HI7Q_HOST_IDX_8821C) << BIT_SHIFT_HI7Q_HOST_IDX_8821C)\n#define BITS_HI7Q_HOST_IDX_8821C                                               \\\n\t(BIT_MASK_HI7Q_HOST_IDX_8821C << BIT_SHIFT_HI7Q_HOST_IDX_8821C)\n#define BIT_CLEAR_HI7Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI7Q_HOST_IDX_8821C))\n#define BIT_GET_HI7Q_HOST_IDX_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8821C) & BIT_MASK_HI7Q_HOST_IDX_8821C)\n#define BIT_SET_HI7Q_HOST_IDX_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HI7Q_HOST_IDX_8821C(x) | BIT_HI7Q_HOST_IDX_8821C(v))\n\n/* 2 REG_DBG_SEL_V1_8821C */\n\n#define BIT_SHIFT_DBG_SEL_8821C 0\n#define BIT_MASK_DBG_SEL_8821C 0xff\n#define BIT_DBG_SEL_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_DBG_SEL_8821C) << BIT_SHIFT_DBG_SEL_8821C)\n#define BITS_DBG_SEL_8821C (BIT_MASK_DBG_SEL_8821C << BIT_SHIFT_DBG_SEL_8821C)\n#define BIT_CLEAR_DBG_SEL_8821C(x) ((x) & (~BITS_DBG_SEL_8821C))\n#define BIT_GET_DBG_SEL_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_DBG_SEL_8821C) & BIT_MASK_DBG_SEL_8821C)\n#define BIT_SET_DBG_SEL_8821C(x, v)                                            \\\n\t(BIT_CLEAR_DBG_SEL_8821C(x) | BIT_DBG_SEL_8821C(v))\n\n/* 2 REG_PCIE_HRPWM1_V1_8821C */\n\n#define BIT_SHIFT_PCIE_HRPWM_8821C 0\n#define BIT_MASK_PCIE_HRPWM_8821C 0xff\n#define BIT_PCIE_HRPWM_8821C(x)                                                \\\n\t(((x) & BIT_MASK_PCIE_HRPWM_8821C) << BIT_SHIFT_PCIE_HRPWM_8821C)\n#define BITS_PCIE_HRPWM_8821C                                                  \\\n\t(BIT_MASK_PCIE_HRPWM_8821C << BIT_SHIFT_PCIE_HRPWM_8821C)\n#define BIT_CLEAR_PCIE_HRPWM_8821C(x) ((x) & (~BITS_PCIE_HRPWM_8821C))\n#define BIT_GET_PCIE_HRPWM_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_PCIE_HRPWM_8821C) & BIT_MASK_PCIE_HRPWM_8821C)\n#define BIT_SET_PCIE_HRPWM_8821C(x, v)                                         \\\n\t(BIT_CLEAR_PCIE_HRPWM_8821C(x) | BIT_PCIE_HRPWM_8821C(v))\n\n/* 2 REG_PCIE_HCPWM1_V1_8821C */\n\n#define BIT_SHIFT_PCIE_HCPWM_8821C 0\n#define BIT_MASK_PCIE_HCPWM_8821C 0xff\n#define BIT_PCIE_HCPWM_8821C(x)                                                \\\n\t(((x) & BIT_MASK_PCIE_HCPWM_8821C) << BIT_SHIFT_PCIE_HCPWM_8821C)\n#define BITS_PCIE_HCPWM_8821C                                                  \\\n\t(BIT_MASK_PCIE_HCPWM_8821C << BIT_SHIFT_PCIE_HCPWM_8821C)\n#define BIT_CLEAR_PCIE_HCPWM_8821C(x) ((x) & (~BITS_PCIE_HCPWM_8821C))\n#define BIT_GET_PCIE_HCPWM_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_PCIE_HCPWM_8821C) & BIT_MASK_PCIE_HCPWM_8821C)\n#define BIT_SET_PCIE_HCPWM_8821C(x, v)                                         \\\n\t(BIT_CLEAR_PCIE_HCPWM_8821C(x) | BIT_PCIE_HCPWM_8821C(v))\n\n/* 2 REG_PCIE_CTRL2_8821C */\n#define BIT_DIS_TXDMA_PRE_8821C BIT(7)\n#define BIT_DIS_RXDMA_PRE_8821C BIT(6)\n\n#define BIT_SHIFT_HPS_CLKR_PCIE_8821C 4\n#define BIT_MASK_HPS_CLKR_PCIE_8821C 0x3\n#define BIT_HPS_CLKR_PCIE_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HPS_CLKR_PCIE_8821C) << BIT_SHIFT_HPS_CLKR_PCIE_8821C)\n#define BITS_HPS_CLKR_PCIE_8821C                                               \\\n\t(BIT_MASK_HPS_CLKR_PCIE_8821C << BIT_SHIFT_HPS_CLKR_PCIE_8821C)\n#define BIT_CLEAR_HPS_CLKR_PCIE_8821C(x) ((x) & (~BITS_HPS_CLKR_PCIE_8821C))\n#define BIT_GET_HPS_CLKR_PCIE_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8821C) & BIT_MASK_HPS_CLKR_PCIE_8821C)\n#define BIT_SET_HPS_CLKR_PCIE_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HPS_CLKR_PCIE_8821C(x) | BIT_HPS_CLKR_PCIE_8821C(v))\n\n#define BIT_PCIE_INT_8821C BIT(3)\n#define BIT_TXFLAG_EXIT_L1_EN_8821C BIT(2)\n#define BIT_EN_RXDMA_ALIGN_8821C BIT(1)\n#define BIT_EN_TXDMA_ALIGN_8821C BIT(0)\n\n/* 2 REG_PCIE_HRPWM2_V1_8821C */\n\n#define BIT_SHIFT_PCIE_HRPWM2_8821C 0\n#define BIT_MASK_PCIE_HRPWM2_8821C 0xffff\n#define BIT_PCIE_HRPWM2_8821C(x)                                               \\\n\t(((x) & BIT_MASK_PCIE_HRPWM2_8821C) << BIT_SHIFT_PCIE_HRPWM2_8821C)\n#define BITS_PCIE_HRPWM2_8821C                                                 \\\n\t(BIT_MASK_PCIE_HRPWM2_8821C << BIT_SHIFT_PCIE_HRPWM2_8821C)\n#define BIT_CLEAR_PCIE_HRPWM2_8821C(x) ((x) & (~BITS_PCIE_HRPWM2_8821C))\n#define BIT_GET_PCIE_HRPWM2_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_PCIE_HRPWM2_8821C) & BIT_MASK_PCIE_HRPWM2_8821C)\n#define BIT_SET_PCIE_HRPWM2_8821C(x, v)                                        \\\n\t(BIT_CLEAR_PCIE_HRPWM2_8821C(x) | BIT_PCIE_HRPWM2_8821C(v))\n\n/* 2 REG_PCIE_HCPWM2_V1_8821C */\n\n#define BIT_SHIFT_PCIE_HCPWM2_8821C 0\n#define BIT_MASK_PCIE_HCPWM2_8821C 0xffff\n#define BIT_PCIE_HCPWM2_8821C(x)                                               \\\n\t(((x) & BIT_MASK_PCIE_HCPWM2_8821C) << BIT_SHIFT_PCIE_HCPWM2_8821C)\n#define BITS_PCIE_HCPWM2_8821C                                                 \\\n\t(BIT_MASK_PCIE_HCPWM2_8821C << BIT_SHIFT_PCIE_HCPWM2_8821C)\n#define BIT_CLEAR_PCIE_HCPWM2_8821C(x) ((x) & (~BITS_PCIE_HCPWM2_8821C))\n#define BIT_GET_PCIE_HCPWM2_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_PCIE_HCPWM2_8821C) & BIT_MASK_PCIE_HCPWM2_8821C)\n#define BIT_SET_PCIE_HCPWM2_8821C(x, v)                                        \\\n\t(BIT_CLEAR_PCIE_HCPWM2_8821C(x) | BIT_PCIE_HCPWM2_8821C(v))\n\n/* 2 REG_PCIE_H2C_MSG_V1_8821C */\n\n#define BIT_SHIFT_DRV2FW_INFO_8821C 0\n#define BIT_MASK_DRV2FW_INFO_8821C 0xffffffffL\n#define BIT_DRV2FW_INFO_8821C(x)                                               \\\n\t(((x) & BIT_MASK_DRV2FW_INFO_8821C) << BIT_SHIFT_DRV2FW_INFO_8821C)\n#define BITS_DRV2FW_INFO_8821C                                                 \\\n\t(BIT_MASK_DRV2FW_INFO_8821C << BIT_SHIFT_DRV2FW_INFO_8821C)\n#define BIT_CLEAR_DRV2FW_INFO_8821C(x) ((x) & (~BITS_DRV2FW_INFO_8821C))\n#define BIT_GET_DRV2FW_INFO_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_DRV2FW_INFO_8821C) & BIT_MASK_DRV2FW_INFO_8821C)\n#define BIT_SET_DRV2FW_INFO_8821C(x, v)                                        \\\n\t(BIT_CLEAR_DRV2FW_INFO_8821C(x) | BIT_DRV2FW_INFO_8821C(v))\n\n/* 2 REG_PCIE_C2H_MSG_V1_8821C */\n\n#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C 0\n#define BIT_MASK_HCI_PCIE_C2H_MSG_8821C 0xffffffffL\n#define BIT_HCI_PCIE_C2H_MSG_8821C(x)                                          \\\n\t(((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8821C)                               \\\n\t << BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C)\n#define BITS_HCI_PCIE_C2H_MSG_8821C                                            \\\n\t(BIT_MASK_HCI_PCIE_C2H_MSG_8821C << BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C)\n#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8821C(x)                                    \\\n\t((x) & (~BITS_HCI_PCIE_C2H_MSG_8821C))\n#define BIT_GET_HCI_PCIE_C2H_MSG_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C) &                           \\\n\t BIT_MASK_HCI_PCIE_C2H_MSG_8821C)\n#define BIT_SET_HCI_PCIE_C2H_MSG_8821C(x, v)                                   \\\n\t(BIT_CLEAR_HCI_PCIE_C2H_MSG_8821C(x) | BIT_HCI_PCIE_C2H_MSG_8821C(v))\n\n/* 2 REG_DBI_WDATA_V1_8821C */\n\n#define BIT_SHIFT_DBI_WDATA_8821C 0\n#define BIT_MASK_DBI_WDATA_8821C 0xffffffffL\n#define BIT_DBI_WDATA_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_DBI_WDATA_8821C) << BIT_SHIFT_DBI_WDATA_8821C)\n#define BITS_DBI_WDATA_8821C                                                   \\\n\t(BIT_MASK_DBI_WDATA_8821C << BIT_SHIFT_DBI_WDATA_8821C)\n#define BIT_CLEAR_DBI_WDATA_8821C(x) ((x) & (~BITS_DBI_WDATA_8821C))\n#define BIT_GET_DBI_WDATA_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBI_WDATA_8821C) & BIT_MASK_DBI_WDATA_8821C)\n#define BIT_SET_DBI_WDATA_8821C(x, v)                                          \\\n\t(BIT_CLEAR_DBI_WDATA_8821C(x) | BIT_DBI_WDATA_8821C(v))\n\n/* 2 REG_DBI_RDATA_V1_8821C */\n\n#define BIT_SHIFT_DBI_RDATA_8821C 0\n#define BIT_MASK_DBI_RDATA_8821C 0xffffffffL\n#define BIT_DBI_RDATA_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_DBI_RDATA_8821C) << BIT_SHIFT_DBI_RDATA_8821C)\n#define BITS_DBI_RDATA_8821C                                                   \\\n\t(BIT_MASK_DBI_RDATA_8821C << BIT_SHIFT_DBI_RDATA_8821C)\n#define BIT_CLEAR_DBI_RDATA_8821C(x) ((x) & (~BITS_DBI_RDATA_8821C))\n#define BIT_GET_DBI_RDATA_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBI_RDATA_8821C) & BIT_MASK_DBI_RDATA_8821C)\n#define BIT_SET_DBI_RDATA_8821C(x, v)                                          \\\n\t(BIT_CLEAR_DBI_RDATA_8821C(x) | BIT_DBI_RDATA_8821C(v))\n\n/* 2 REG_DBI_FLAG_V1_8821C */\n#define BIT_EN_STUCK_DBG_8821C BIT(26)\n#define BIT_RX_STUCK_8821C BIT(25)\n#define BIT_TX_STUCK_8821C BIT(24)\n#define BIT_DBI_RFLAG_8821C BIT(17)\n#define BIT_DBI_WFLAG_8821C BIT(16)\n\n#define BIT_SHIFT_DBI_WREN_8821C 12\n#define BIT_MASK_DBI_WREN_8821C 0xf\n#define BIT_DBI_WREN_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_DBI_WREN_8821C) << BIT_SHIFT_DBI_WREN_8821C)\n#define BITS_DBI_WREN_8821C                                                    \\\n\t(BIT_MASK_DBI_WREN_8821C << BIT_SHIFT_DBI_WREN_8821C)\n#define BIT_CLEAR_DBI_WREN_8821C(x) ((x) & (~BITS_DBI_WREN_8821C))\n#define BIT_GET_DBI_WREN_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_DBI_WREN_8821C) & BIT_MASK_DBI_WREN_8821C)\n#define BIT_SET_DBI_WREN_8821C(x, v)                                           \\\n\t(BIT_CLEAR_DBI_WREN_8821C(x) | BIT_DBI_WREN_8821C(v))\n\n#define BIT_SHIFT_DBI_ADDR_8821C 0\n#define BIT_MASK_DBI_ADDR_8821C 0xfff\n#define BIT_DBI_ADDR_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_DBI_ADDR_8821C) << BIT_SHIFT_DBI_ADDR_8821C)\n#define BITS_DBI_ADDR_8821C                                                    \\\n\t(BIT_MASK_DBI_ADDR_8821C << BIT_SHIFT_DBI_ADDR_8821C)\n#define BIT_CLEAR_DBI_ADDR_8821C(x) ((x) & (~BITS_DBI_ADDR_8821C))\n#define BIT_GET_DBI_ADDR_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_DBI_ADDR_8821C) & BIT_MASK_DBI_ADDR_8821C)\n#define BIT_SET_DBI_ADDR_8821C(x, v)                                           \\\n\t(BIT_CLEAR_DBI_ADDR_8821C(x) | BIT_DBI_ADDR_8821C(v))\n\n/* 2 REG_MDIO_V1_8821C */\n\n#define BIT_SHIFT_MDIO_RDATA_8821C 16\n#define BIT_MASK_MDIO_RDATA_8821C 0xffff\n#define BIT_MDIO_RDATA_8821C(x)                                                \\\n\t(((x) & BIT_MASK_MDIO_RDATA_8821C) << BIT_SHIFT_MDIO_RDATA_8821C)\n#define BITS_MDIO_RDATA_8821C                                                  \\\n\t(BIT_MASK_MDIO_RDATA_8821C << BIT_SHIFT_MDIO_RDATA_8821C)\n#define BIT_CLEAR_MDIO_RDATA_8821C(x) ((x) & (~BITS_MDIO_RDATA_8821C))\n#define BIT_GET_MDIO_RDATA_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_MDIO_RDATA_8821C) & BIT_MASK_MDIO_RDATA_8821C)\n#define BIT_SET_MDIO_RDATA_8821C(x, v)                                         \\\n\t(BIT_CLEAR_MDIO_RDATA_8821C(x) | BIT_MDIO_RDATA_8821C(v))\n\n#define BIT_SHIFT_MDIO_WDATA_8821C 0\n#define BIT_MASK_MDIO_WDATA_8821C 0xffff\n#define BIT_MDIO_WDATA_8821C(x)                                                \\\n\t(((x) & BIT_MASK_MDIO_WDATA_8821C) << BIT_SHIFT_MDIO_WDATA_8821C)\n#define BITS_MDIO_WDATA_8821C                                                  \\\n\t(BIT_MASK_MDIO_WDATA_8821C << BIT_SHIFT_MDIO_WDATA_8821C)\n#define BIT_CLEAR_MDIO_WDATA_8821C(x) ((x) & (~BITS_MDIO_WDATA_8821C))\n#define BIT_GET_MDIO_WDATA_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_MDIO_WDATA_8821C) & BIT_MASK_MDIO_WDATA_8821C)\n#define BIT_SET_MDIO_WDATA_8821C(x, v)                                         \\\n\t(BIT_CLEAR_MDIO_WDATA_8821C(x) | BIT_MDIO_WDATA_8821C(v))\n\n/* 2 REG_PCIE_MIX_CFG_8821C */\n\n#define BIT_SHIFT_MDIO_PHY_ADDR_8821C 24\n#define BIT_MASK_MDIO_PHY_ADDR_8821C 0x1f\n#define BIT_MDIO_PHY_ADDR_8821C(x)                                             \\\n\t(((x) & BIT_MASK_MDIO_PHY_ADDR_8821C) << BIT_SHIFT_MDIO_PHY_ADDR_8821C)\n#define BITS_MDIO_PHY_ADDR_8821C                                               \\\n\t(BIT_MASK_MDIO_PHY_ADDR_8821C << BIT_SHIFT_MDIO_PHY_ADDR_8821C)\n#define BIT_CLEAR_MDIO_PHY_ADDR_8821C(x) ((x) & (~BITS_MDIO_PHY_ADDR_8821C))\n#define BIT_GET_MDIO_PHY_ADDR_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8821C) & BIT_MASK_MDIO_PHY_ADDR_8821C)\n#define BIT_SET_MDIO_PHY_ADDR_8821C(x, v)                                      \\\n\t(BIT_CLEAR_MDIO_PHY_ADDR_8821C(x) | BIT_MDIO_PHY_ADDR_8821C(v))\n\n#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C 10\n#define BIT_MASK_WATCH_DOG_RECORD_V1_8821C 0x3fff\n#define BIT_WATCH_DOG_RECORD_V1_8821C(x)                                       \\\n\t(((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8821C)                            \\\n\t << BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C)\n#define BITS_WATCH_DOG_RECORD_V1_8821C                                         \\\n\t(BIT_MASK_WATCH_DOG_RECORD_V1_8821C                                    \\\n\t << BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C)\n#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8821C(x)                                 \\\n\t((x) & (~BITS_WATCH_DOG_RECORD_V1_8821C))\n#define BIT_GET_WATCH_DOG_RECORD_V1_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) &                        \\\n\t BIT_MASK_WATCH_DOG_RECORD_V1_8821C)\n#define BIT_SET_WATCH_DOG_RECORD_V1_8821C(x, v)                                \\\n\t(BIT_CLEAR_WATCH_DOG_RECORD_V1_8821C(x) |                              \\\n\t BIT_WATCH_DOG_RECORD_V1_8821C(v))\n\n#define BIT_R_IO_TIMEOUT_FLAG_V1_8821C BIT(9)\n#define BIT_EN_WATCH_DOG_8821C BIT(8)\n#define BIT_ECRC_EN_V1_8821C BIT(7)\n#define BIT_MDIO_RFLAG_V1_8821C BIT(6)\n#define BIT_MDIO_WFLAG_V1_8821C BIT(5)\n\n#define BIT_SHIFT_MDIO_REG_ADDR_V1_8821C 0\n#define BIT_MASK_MDIO_REG_ADDR_V1_8821C 0x1f\n#define BIT_MDIO_REG_ADDR_V1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_MDIO_REG_ADDR_V1_8821C)                               \\\n\t << BIT_SHIFT_MDIO_REG_ADDR_V1_8821C)\n#define BITS_MDIO_REG_ADDR_V1_8821C                                            \\\n\t(BIT_MASK_MDIO_REG_ADDR_V1_8821C << BIT_SHIFT_MDIO_REG_ADDR_V1_8821C)\n#define BIT_CLEAR_MDIO_REG_ADDR_V1_8821C(x)                                    \\\n\t((x) & (~BITS_MDIO_REG_ADDR_V1_8821C))\n#define BIT_GET_MDIO_REG_ADDR_V1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8821C) &                           \\\n\t BIT_MASK_MDIO_REG_ADDR_V1_8821C)\n#define BIT_SET_MDIO_REG_ADDR_V1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_MDIO_REG_ADDR_V1_8821C(x) | BIT_MDIO_REG_ADDR_V1_8821C(v))\n\n/* 2 REG_HCI_MIX_CFG_8821C */\n#define BIT_HOST_GEN2_SUPPORT_8821C BIT(20)\n\n#define BIT_SHIFT_TXDMA_ERR_FLAG_8821C 16\n#define BIT_MASK_TXDMA_ERR_FLAG_8821C 0xf\n#define BIT_TXDMA_ERR_FLAG_8821C(x)                                            \\\n\t(((x) & BIT_MASK_TXDMA_ERR_FLAG_8821C)                                 \\\n\t << BIT_SHIFT_TXDMA_ERR_FLAG_8821C)\n#define BITS_TXDMA_ERR_FLAG_8821C                                              \\\n\t(BIT_MASK_TXDMA_ERR_FLAG_8821C << BIT_SHIFT_TXDMA_ERR_FLAG_8821C)\n#define BIT_CLEAR_TXDMA_ERR_FLAG_8821C(x) ((x) & (~BITS_TXDMA_ERR_FLAG_8821C))\n#define BIT_GET_TXDMA_ERR_FLAG_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8821C) &                             \\\n\t BIT_MASK_TXDMA_ERR_FLAG_8821C)\n#define BIT_SET_TXDMA_ERR_FLAG_8821C(x, v)                                     \\\n\t(BIT_CLEAR_TXDMA_ERR_FLAG_8821C(x) | BIT_TXDMA_ERR_FLAG_8821C(v))\n\n#define BIT_SHIFT_EARLY_MODE_SEL_8821C 12\n#define BIT_MASK_EARLY_MODE_SEL_8821C 0xf\n#define BIT_EARLY_MODE_SEL_8821C(x)                                            \\\n\t(((x) & BIT_MASK_EARLY_MODE_SEL_8821C)                                 \\\n\t << BIT_SHIFT_EARLY_MODE_SEL_8821C)\n#define BITS_EARLY_MODE_SEL_8821C                                              \\\n\t(BIT_MASK_EARLY_MODE_SEL_8821C << BIT_SHIFT_EARLY_MODE_SEL_8821C)\n#define BIT_CLEAR_EARLY_MODE_SEL_8821C(x) ((x) & (~BITS_EARLY_MODE_SEL_8821C))\n#define BIT_GET_EARLY_MODE_SEL_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_EARLY_MODE_SEL_8821C) &                             \\\n\t BIT_MASK_EARLY_MODE_SEL_8821C)\n#define BIT_SET_EARLY_MODE_SEL_8821C(x, v)                                     \\\n\t(BIT_CLEAR_EARLY_MODE_SEL_8821C(x) | BIT_EARLY_MODE_SEL_8821C(v))\n\n#define BIT_EPHY_RX50_EN_8821C BIT(11)\n\n#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C 8\n#define BIT_MASK_MSI_TIMEOUT_ID_V1_8821C 0x7\n#define BIT_MSI_TIMEOUT_ID_V1_8821C(x)                                         \\\n\t(((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8821C)                              \\\n\t << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C)\n#define BITS_MSI_TIMEOUT_ID_V1_8821C                                           \\\n\t(BIT_MASK_MSI_TIMEOUT_ID_V1_8821C << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C)\n#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8821C(x)                                   \\\n\t((x) & (~BITS_MSI_TIMEOUT_ID_V1_8821C))\n#define BIT_GET_MSI_TIMEOUT_ID_V1_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) &                          \\\n\t BIT_MASK_MSI_TIMEOUT_ID_V1_8821C)\n#define BIT_SET_MSI_TIMEOUT_ID_V1_8821C(x, v)                                  \\\n\t(BIT_CLEAR_MSI_TIMEOUT_ID_V1_8821C(x) | BIT_MSI_TIMEOUT_ID_V1_8821C(v))\n\n#define BIT_RADDR_RD_8821C BIT(7)\n#define BIT_EN_MUL_TAG_8821C BIT(6)\n#define BIT_EN_EARLY_MODE_8821C BIT(5)\n#define BIT_L0S_LINK_OFF_8821C BIT(4)\n#define BIT_ACT_LINK_OFF_8821C BIT(3)\n#define BIT_EN_SLOW_MAC_TX_8821C BIT(2)\n#define BIT_EN_SLOW_MAC_RX_8821C BIT(1)\n\n/* 2 REG_STC_INT_CS_8821C(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */\n#define BIT_STC_INT_EN_8821C BIT(31)\n\n#define BIT_SHIFT_STC_INT_FLAG_8821C 16\n#define BIT_MASK_STC_INT_FLAG_8821C 0xff\n#define BIT_STC_INT_FLAG_8821C(x)                                              \\\n\t(((x) & BIT_MASK_STC_INT_FLAG_8821C) << BIT_SHIFT_STC_INT_FLAG_8821C)\n#define BITS_STC_INT_FLAG_8821C                                                \\\n\t(BIT_MASK_STC_INT_FLAG_8821C << BIT_SHIFT_STC_INT_FLAG_8821C)\n#define BIT_CLEAR_STC_INT_FLAG_8821C(x) ((x) & (~BITS_STC_INT_FLAG_8821C))\n#define BIT_GET_STC_INT_FLAG_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_STC_INT_FLAG_8821C) & BIT_MASK_STC_INT_FLAG_8821C)\n#define BIT_SET_STC_INT_FLAG_8821C(x, v)                                       \\\n\t(BIT_CLEAR_STC_INT_FLAG_8821C(x) | BIT_STC_INT_FLAG_8821C(v))\n\n#define BIT_SHIFT_STC_INT_IDX_8821C 8\n#define BIT_MASK_STC_INT_IDX_8821C 0x7\n#define BIT_STC_INT_IDX_8821C(x)                                               \\\n\t(((x) & BIT_MASK_STC_INT_IDX_8821C) << BIT_SHIFT_STC_INT_IDX_8821C)\n#define BITS_STC_INT_IDX_8821C                                                 \\\n\t(BIT_MASK_STC_INT_IDX_8821C << BIT_SHIFT_STC_INT_IDX_8821C)\n#define BIT_CLEAR_STC_INT_IDX_8821C(x) ((x) & (~BITS_STC_INT_IDX_8821C))\n#define BIT_GET_STC_INT_IDX_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_STC_INT_IDX_8821C) & BIT_MASK_STC_INT_IDX_8821C)\n#define BIT_SET_STC_INT_IDX_8821C(x, v)                                        \\\n\t(BIT_CLEAR_STC_INT_IDX_8821C(x) | BIT_STC_INT_IDX_8821C(v))\n\n#define BIT_SHIFT_STC_INT_REALTIME_CS_8821C 0\n#define BIT_MASK_STC_INT_REALTIME_CS_8821C 0x3f\n#define BIT_STC_INT_REALTIME_CS_8821C(x)                                       \\\n\t(((x) & BIT_MASK_STC_INT_REALTIME_CS_8821C)                            \\\n\t << BIT_SHIFT_STC_INT_REALTIME_CS_8821C)\n#define BITS_STC_INT_REALTIME_CS_8821C                                         \\\n\t(BIT_MASK_STC_INT_REALTIME_CS_8821C                                    \\\n\t << BIT_SHIFT_STC_INT_REALTIME_CS_8821C)\n#define BIT_CLEAR_STC_INT_REALTIME_CS_8821C(x)                                 \\\n\t((x) & (~BITS_STC_INT_REALTIME_CS_8821C))\n#define BIT_GET_STC_INT_REALTIME_CS_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8821C) &                        \\\n\t BIT_MASK_STC_INT_REALTIME_CS_8821C)\n#define BIT_SET_STC_INT_REALTIME_CS_8821C(x, v)                                \\\n\t(BIT_CLEAR_STC_INT_REALTIME_CS_8821C(x) |                              \\\n\t BIT_STC_INT_REALTIME_CS_8821C(v))\n\n/* 2 REG_ST_INT_CFG_8821C(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */\n#define BIT_STC_INT_GRP_EN_8821C BIT(31)\n\n#define BIT_SHIFT_STC_INT_EXPECT_LS_8821C 8\n#define BIT_MASK_STC_INT_EXPECT_LS_8821C 0x3f\n#define BIT_STC_INT_EXPECT_LS_8821C(x)                                         \\\n\t(((x) & BIT_MASK_STC_INT_EXPECT_LS_8821C)                              \\\n\t << BIT_SHIFT_STC_INT_EXPECT_LS_8821C)\n#define BITS_STC_INT_EXPECT_LS_8821C                                           \\\n\t(BIT_MASK_STC_INT_EXPECT_LS_8821C << BIT_SHIFT_STC_INT_EXPECT_LS_8821C)\n#define BIT_CLEAR_STC_INT_EXPECT_LS_8821C(x)                                   \\\n\t((x) & (~BITS_STC_INT_EXPECT_LS_8821C))\n#define BIT_GET_STC_INT_EXPECT_LS_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8821C) &                          \\\n\t BIT_MASK_STC_INT_EXPECT_LS_8821C)\n#define BIT_SET_STC_INT_EXPECT_LS_8821C(x, v)                                  \\\n\t(BIT_CLEAR_STC_INT_EXPECT_LS_8821C(x) | BIT_STC_INT_EXPECT_LS_8821C(v))\n\n#define BIT_SHIFT_STC_INT_EXPECT_CS_8821C 0\n#define BIT_MASK_STC_INT_EXPECT_CS_8821C 0x3f\n#define BIT_STC_INT_EXPECT_CS_8821C(x)                                         \\\n\t(((x) & BIT_MASK_STC_INT_EXPECT_CS_8821C)                              \\\n\t << BIT_SHIFT_STC_INT_EXPECT_CS_8821C)\n#define BITS_STC_INT_EXPECT_CS_8821C                                           \\\n\t(BIT_MASK_STC_INT_EXPECT_CS_8821C << BIT_SHIFT_STC_INT_EXPECT_CS_8821C)\n#define BIT_CLEAR_STC_INT_EXPECT_CS_8821C(x)                                   \\\n\t((x) & (~BITS_STC_INT_EXPECT_CS_8821C))\n#define BIT_GET_STC_INT_EXPECT_CS_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8821C) &                          \\\n\t BIT_MASK_STC_INT_EXPECT_CS_8821C)\n#define BIT_SET_STC_INT_EXPECT_CS_8821C(x, v)                                  \\\n\t(BIT_CLEAR_STC_INT_EXPECT_CS_8821C(x) | BIT_STC_INT_EXPECT_CS_8821C(v))\n\n/* 2 REG_CMU_DLY_CTRL_8821C(PCIE PHY CLOCK MGT UNIT DELAY CONTROL ) */\n#define BIT_CMU_DLY_EN_8821C BIT(31)\n#define BIT_CMU_DLY_MODE_8821C BIT(30)\n\n#define BIT_SHIFT_CMU_DLY_PRE_DIV_8821C 0\n#define BIT_MASK_CMU_DLY_PRE_DIV_8821C 0xff\n#define BIT_CMU_DLY_PRE_DIV_8821C(x)                                           \\\n\t(((x) & BIT_MASK_CMU_DLY_PRE_DIV_8821C)                                \\\n\t << BIT_SHIFT_CMU_DLY_PRE_DIV_8821C)\n#define BITS_CMU_DLY_PRE_DIV_8821C                                             \\\n\t(BIT_MASK_CMU_DLY_PRE_DIV_8821C << BIT_SHIFT_CMU_DLY_PRE_DIV_8821C)\n#define BIT_CLEAR_CMU_DLY_PRE_DIV_8821C(x) ((x) & (~BITS_CMU_DLY_PRE_DIV_8821C))\n#define BIT_GET_CMU_DLY_PRE_DIV_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8821C) &                            \\\n\t BIT_MASK_CMU_DLY_PRE_DIV_8821C)\n#define BIT_SET_CMU_DLY_PRE_DIV_8821C(x, v)                                    \\\n\t(BIT_CLEAR_CMU_DLY_PRE_DIV_8821C(x) | BIT_CMU_DLY_PRE_DIV_8821C(v))\n\n/* 2 REG_CMU_DLY_CFG_8821C(PCIE PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */\n\n#define BIT_SHIFT_CMU_DLY_LTR_A2I_8821C 24\n#define BIT_MASK_CMU_DLY_LTR_A2I_8821C 0xff\n#define BIT_CMU_DLY_LTR_A2I_8821C(x)                                           \\\n\t(((x) & BIT_MASK_CMU_DLY_LTR_A2I_8821C)                                \\\n\t << BIT_SHIFT_CMU_DLY_LTR_A2I_8821C)\n#define BITS_CMU_DLY_LTR_A2I_8821C                                             \\\n\t(BIT_MASK_CMU_DLY_LTR_A2I_8821C << BIT_SHIFT_CMU_DLY_LTR_A2I_8821C)\n#define BIT_CLEAR_CMU_DLY_LTR_A2I_8821C(x) ((x) & (~BITS_CMU_DLY_LTR_A2I_8821C))\n#define BIT_GET_CMU_DLY_LTR_A2I_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8821C) &                            \\\n\t BIT_MASK_CMU_DLY_LTR_A2I_8821C)\n#define BIT_SET_CMU_DLY_LTR_A2I_8821C(x, v)                                    \\\n\t(BIT_CLEAR_CMU_DLY_LTR_A2I_8821C(x) | BIT_CMU_DLY_LTR_A2I_8821C(v))\n\n#define BIT_SHIFT_CMU_DLY_LTR_I2A_8821C 16\n#define BIT_MASK_CMU_DLY_LTR_I2A_8821C 0xff\n#define BIT_CMU_DLY_LTR_I2A_8821C(x)                                           \\\n\t(((x) & BIT_MASK_CMU_DLY_LTR_I2A_8821C)                                \\\n\t << BIT_SHIFT_CMU_DLY_LTR_I2A_8821C)\n#define BITS_CMU_DLY_LTR_I2A_8821C                                             \\\n\t(BIT_MASK_CMU_DLY_LTR_I2A_8821C << BIT_SHIFT_CMU_DLY_LTR_I2A_8821C)\n#define BIT_CLEAR_CMU_DLY_LTR_I2A_8821C(x) ((x) & (~BITS_CMU_DLY_LTR_I2A_8821C))\n#define BIT_GET_CMU_DLY_LTR_I2A_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) &                            \\\n\t BIT_MASK_CMU_DLY_LTR_I2A_8821C)\n#define BIT_SET_CMU_DLY_LTR_I2A_8821C(x, v)                                    \\\n\t(BIT_CLEAR_CMU_DLY_LTR_I2A_8821C(x) | BIT_CMU_DLY_LTR_I2A_8821C(v))\n\n#define BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C 8\n#define BIT_MASK_CMU_DLY_LTR_IDLE_8821C 0xff\n#define BIT_CMU_DLY_LTR_IDLE_8821C(x)                                          \\\n\t(((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8821C)                               \\\n\t << BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C)\n#define BITS_CMU_DLY_LTR_IDLE_8821C                                            \\\n\t(BIT_MASK_CMU_DLY_LTR_IDLE_8821C << BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C)\n#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8821C(x)                                    \\\n\t((x) & (~BITS_CMU_DLY_LTR_IDLE_8821C))\n#define BIT_GET_CMU_DLY_LTR_IDLE_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) &                           \\\n\t BIT_MASK_CMU_DLY_LTR_IDLE_8821C)\n#define BIT_SET_CMU_DLY_LTR_IDLE_8821C(x, v)                                   \\\n\t(BIT_CLEAR_CMU_DLY_LTR_IDLE_8821C(x) | BIT_CMU_DLY_LTR_IDLE_8821C(v))\n\n#define BIT_SHIFT_CMU_DLY_LTR_ACT_8821C 0\n#define BIT_MASK_CMU_DLY_LTR_ACT_8821C 0xff\n#define BIT_CMU_DLY_LTR_ACT_8821C(x)                                           \\\n\t(((x) & BIT_MASK_CMU_DLY_LTR_ACT_8821C)                                \\\n\t << BIT_SHIFT_CMU_DLY_LTR_ACT_8821C)\n#define BITS_CMU_DLY_LTR_ACT_8821C                                             \\\n\t(BIT_MASK_CMU_DLY_LTR_ACT_8821C << BIT_SHIFT_CMU_DLY_LTR_ACT_8821C)\n#define BIT_CLEAR_CMU_DLY_LTR_ACT_8821C(x) ((x) & (~BITS_CMU_DLY_LTR_ACT_8821C))\n#define BIT_GET_CMU_DLY_LTR_ACT_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) &                            \\\n\t BIT_MASK_CMU_DLY_LTR_ACT_8821C)\n#define BIT_SET_CMU_DLY_LTR_ACT_8821C(x, v)                                    \\\n\t(BIT_CLEAR_CMU_DLY_LTR_ACT_8821C(x) | BIT_CMU_DLY_LTR_ACT_8821C(v))\n\n/* 2 REG_H2CQ_TXBD_DESA_8821C */\n\n#define BIT_SHIFT_H2CQ_TXBD_DESA_8821C 0\n#define BIT_MASK_H2CQ_TXBD_DESA_8821C 0xffffffffffffffffL\n#define BIT_H2CQ_TXBD_DESA_8821C(x)                                            \\\n\t(((x) & BIT_MASK_H2CQ_TXBD_DESA_8821C)                                 \\\n\t << BIT_SHIFT_H2CQ_TXBD_DESA_8821C)\n#define BITS_H2CQ_TXBD_DESA_8821C                                              \\\n\t(BIT_MASK_H2CQ_TXBD_DESA_8821C << BIT_SHIFT_H2CQ_TXBD_DESA_8821C)\n#define BIT_CLEAR_H2CQ_TXBD_DESA_8821C(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8821C))\n#define BIT_GET_H2CQ_TXBD_DESA_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8821C) &                             \\\n\t BIT_MASK_H2CQ_TXBD_DESA_8821C)\n#define BIT_SET_H2CQ_TXBD_DESA_8821C(x, v)                                     \\\n\t(BIT_CLEAR_H2CQ_TXBD_DESA_8821C(x) | BIT_H2CQ_TXBD_DESA_8821C(v))\n\n/* 2 REG_H2CQ_TXBD_NUM_8821C */\n#define BIT_PCIE_H2CQ_FLAG_8821C BIT(14)\n\n#define BIT_SHIFT_H2CQ_DESC_MODE_8821C 12\n#define BIT_MASK_H2CQ_DESC_MODE_8821C 0x3\n#define BIT_H2CQ_DESC_MODE_8821C(x)                                            \\\n\t(((x) & BIT_MASK_H2CQ_DESC_MODE_8821C)                                 \\\n\t << BIT_SHIFT_H2CQ_DESC_MODE_8821C)\n#define BITS_H2CQ_DESC_MODE_8821C                                              \\\n\t(BIT_MASK_H2CQ_DESC_MODE_8821C << BIT_SHIFT_H2CQ_DESC_MODE_8821C)\n#define BIT_CLEAR_H2CQ_DESC_MODE_8821C(x) ((x) & (~BITS_H2CQ_DESC_MODE_8821C))\n#define BIT_GET_H2CQ_DESC_MODE_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8821C) &                             \\\n\t BIT_MASK_H2CQ_DESC_MODE_8821C)\n#define BIT_SET_H2CQ_DESC_MODE_8821C(x, v)                                     \\\n\t(BIT_CLEAR_H2CQ_DESC_MODE_8821C(x) | BIT_H2CQ_DESC_MODE_8821C(v))\n\n#define BIT_SHIFT_H2CQ_DESC_NUM_8821C 0\n#define BIT_MASK_H2CQ_DESC_NUM_8821C 0xfff\n#define BIT_H2CQ_DESC_NUM_8821C(x)                                             \\\n\t(((x) & BIT_MASK_H2CQ_DESC_NUM_8821C) << BIT_SHIFT_H2CQ_DESC_NUM_8821C)\n#define BITS_H2CQ_DESC_NUM_8821C                                               \\\n\t(BIT_MASK_H2CQ_DESC_NUM_8821C << BIT_SHIFT_H2CQ_DESC_NUM_8821C)\n#define BIT_CLEAR_H2CQ_DESC_NUM_8821C(x) ((x) & (~BITS_H2CQ_DESC_NUM_8821C))\n#define BIT_GET_H2CQ_DESC_NUM_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8821C) & BIT_MASK_H2CQ_DESC_NUM_8821C)\n#define BIT_SET_H2CQ_DESC_NUM_8821C(x, v)                                      \\\n\t(BIT_CLEAR_H2CQ_DESC_NUM_8821C(x) | BIT_H2CQ_DESC_NUM_8821C(v))\n\n/* 2 REG_H2CQ_TXBD_IDX_8821C */\n\n#define BIT_SHIFT_H2CQ_HW_IDX_8821C 16\n#define BIT_MASK_H2CQ_HW_IDX_8821C 0xfff\n#define BIT_H2CQ_HW_IDX_8821C(x)                                               \\\n\t(((x) & BIT_MASK_H2CQ_HW_IDX_8821C) << BIT_SHIFT_H2CQ_HW_IDX_8821C)\n#define BITS_H2CQ_HW_IDX_8821C                                                 \\\n\t(BIT_MASK_H2CQ_HW_IDX_8821C << BIT_SHIFT_H2CQ_HW_IDX_8821C)\n#define BIT_CLEAR_H2CQ_HW_IDX_8821C(x) ((x) & (~BITS_H2CQ_HW_IDX_8821C))\n#define BIT_GET_H2CQ_HW_IDX_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_H2CQ_HW_IDX_8821C) & BIT_MASK_H2CQ_HW_IDX_8821C)\n#define BIT_SET_H2CQ_HW_IDX_8821C(x, v)                                        \\\n\t(BIT_CLEAR_H2CQ_HW_IDX_8821C(x) | BIT_H2CQ_HW_IDX_8821C(v))\n\n#define BIT_SHIFT_H2CQ_HOST_IDX_8821C 0\n#define BIT_MASK_H2CQ_HOST_IDX_8821C 0xfff\n#define BIT_H2CQ_HOST_IDX_8821C(x)                                             \\\n\t(((x) & BIT_MASK_H2CQ_HOST_IDX_8821C) << BIT_SHIFT_H2CQ_HOST_IDX_8821C)\n#define BITS_H2CQ_HOST_IDX_8821C                                               \\\n\t(BIT_MASK_H2CQ_HOST_IDX_8821C << BIT_SHIFT_H2CQ_HOST_IDX_8821C)\n#define BIT_CLEAR_H2CQ_HOST_IDX_8821C(x) ((x) & (~BITS_H2CQ_HOST_IDX_8821C))\n#define BIT_GET_H2CQ_HOST_IDX_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8821C) & BIT_MASK_H2CQ_HOST_IDX_8821C)\n#define BIT_SET_H2CQ_HOST_IDX_8821C(x, v)                                      \\\n\t(BIT_CLEAR_H2CQ_HOST_IDX_8821C(x) | BIT_H2CQ_HOST_IDX_8821C(v))\n\n/* 2 REG_H2CQ_CSR_8821C[31:0] (H2CQ CONTROL AND STATUS) */\n#define BIT_H2CQ_FULL_8821C BIT(31)\n#define BIT_CLR_H2CQ_HOST_IDX_8821C BIT(16)\n#define BIT_CLR_H2CQ_HW_IDX_8821C BIT(8)\n#define BIT_STOP_H2CQ_8821C BIT(0)\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_Q0_INFO_8821C */\n\n#define BIT_SHIFT_QUEUEMACID_Q0_V1_8821C 25\n#define BIT_MASK_QUEUEMACID_Q0_V1_8821C 0x7f\n#define BIT_QUEUEMACID_Q0_V1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q0_V1_8821C)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q0_V1_8821C)\n#define BITS_QUEUEMACID_Q0_V1_8821C                                            \\\n\t(BIT_MASK_QUEUEMACID_Q0_V1_8821C << BIT_SHIFT_QUEUEMACID_Q0_V1_8821C)\n#define BIT_CLEAR_QUEUEMACID_Q0_V1_8821C(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q0_V1_8821C))\n#define BIT_GET_QUEUEMACID_Q0_V1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8821C) &                           \\\n\t BIT_MASK_QUEUEMACID_Q0_V1_8821C)\n#define BIT_SET_QUEUEMACID_Q0_V1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q0_V1_8821C(x) | BIT_QUEUEMACID_Q0_V1_8821C(v))\n\n#define BIT_SHIFT_QUEUEAC_Q0_V1_8821C 23\n#define BIT_MASK_QUEUEAC_Q0_V1_8821C 0x3\n#define BIT_QUEUEAC_Q0_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q0_V1_8821C) << BIT_SHIFT_QUEUEAC_Q0_V1_8821C)\n#define BITS_QUEUEAC_Q0_V1_8821C                                               \\\n\t(BIT_MASK_QUEUEAC_Q0_V1_8821C << BIT_SHIFT_QUEUEAC_Q0_V1_8821C)\n#define BIT_CLEAR_QUEUEAC_Q0_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8821C))\n#define BIT_GET_QUEUEAC_Q0_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8821C) & BIT_MASK_QUEUEAC_Q0_V1_8821C)\n#define BIT_SET_QUEUEAC_Q0_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q0_V1_8821C(x) | BIT_QUEUEAC_Q0_V1_8821C(v))\n\n#define BIT_TIDEMPTY_Q0_V1_8821C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q0_V2_8821C 11\n#define BIT_MASK_TAIL_PKT_Q0_V2_8821C 0x7ff\n#define BIT_TAIL_PKT_Q0_V2_8821C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q0_V2_8821C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q0_V2_8821C)\n#define BITS_TAIL_PKT_Q0_V2_8821C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q0_V2_8821C << BIT_SHIFT_TAIL_PKT_Q0_V2_8821C)\n#define BIT_CLEAR_TAIL_PKT_Q0_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8821C))\n#define BIT_GET_TAIL_PKT_Q0_V2_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8821C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q0_V2_8821C)\n#define BIT_SET_TAIL_PKT_Q0_V2_8821C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q0_V2_8821C(x) | BIT_TAIL_PKT_Q0_V2_8821C(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q0_V1_8821C 0\n#define BIT_MASK_HEAD_PKT_Q0_V1_8821C 0x7ff\n#define BIT_HEAD_PKT_Q0_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q0_V1_8821C)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q0_V1_8821C)\n#define BITS_HEAD_PKT_Q0_V1_8821C                                              \\\n\t(BIT_MASK_HEAD_PKT_Q0_V1_8821C << BIT_SHIFT_HEAD_PKT_Q0_V1_8821C)\n#define BIT_CLEAR_HEAD_PKT_Q0_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8821C))\n#define BIT_GET_HEAD_PKT_Q0_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) &                             \\\n\t BIT_MASK_HEAD_PKT_Q0_V1_8821C)\n#define BIT_SET_HEAD_PKT_Q0_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q0_V1_8821C(x) | BIT_HEAD_PKT_Q0_V1_8821C(v))\n\n/* 2 REG_Q1_INFO_8821C */\n\n#define BIT_SHIFT_QUEUEMACID_Q1_V1_8821C 25\n#define BIT_MASK_QUEUEMACID_Q1_V1_8821C 0x7f\n#define BIT_QUEUEMACID_Q1_V1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q1_V1_8821C)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q1_V1_8821C)\n#define BITS_QUEUEMACID_Q1_V1_8821C                                            \\\n\t(BIT_MASK_QUEUEMACID_Q1_V1_8821C << BIT_SHIFT_QUEUEMACID_Q1_V1_8821C)\n#define BIT_CLEAR_QUEUEMACID_Q1_V1_8821C(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q1_V1_8821C))\n#define BIT_GET_QUEUEMACID_Q1_V1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8821C) &                           \\\n\t BIT_MASK_QUEUEMACID_Q1_V1_8821C)\n#define BIT_SET_QUEUEMACID_Q1_V1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q1_V1_8821C(x) | BIT_QUEUEMACID_Q1_V1_8821C(v))\n\n#define BIT_SHIFT_QUEUEAC_Q1_V1_8821C 23\n#define BIT_MASK_QUEUEAC_Q1_V1_8821C 0x3\n#define BIT_QUEUEAC_Q1_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q1_V1_8821C) << BIT_SHIFT_QUEUEAC_Q1_V1_8821C)\n#define BITS_QUEUEAC_Q1_V1_8821C                                               \\\n\t(BIT_MASK_QUEUEAC_Q1_V1_8821C << BIT_SHIFT_QUEUEAC_Q1_V1_8821C)\n#define BIT_CLEAR_QUEUEAC_Q1_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8821C))\n#define BIT_GET_QUEUEAC_Q1_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8821C) & BIT_MASK_QUEUEAC_Q1_V1_8821C)\n#define BIT_SET_QUEUEAC_Q1_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q1_V1_8821C(x) | BIT_QUEUEAC_Q1_V1_8821C(v))\n\n#define BIT_TIDEMPTY_Q1_V1_8821C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q1_V2_8821C 11\n#define BIT_MASK_TAIL_PKT_Q1_V2_8821C 0x7ff\n#define BIT_TAIL_PKT_Q1_V2_8821C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q1_V2_8821C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q1_V2_8821C)\n#define BITS_TAIL_PKT_Q1_V2_8821C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q1_V2_8821C << BIT_SHIFT_TAIL_PKT_Q1_V2_8821C)\n#define BIT_CLEAR_TAIL_PKT_Q1_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8821C))\n#define BIT_GET_TAIL_PKT_Q1_V2_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8821C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q1_V2_8821C)\n#define BIT_SET_TAIL_PKT_Q1_V2_8821C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q1_V2_8821C(x) | BIT_TAIL_PKT_Q1_V2_8821C(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q1_V1_8821C 0\n#define BIT_MASK_HEAD_PKT_Q1_V1_8821C 0x7ff\n#define BIT_HEAD_PKT_Q1_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q1_V1_8821C)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q1_V1_8821C)\n#define BITS_HEAD_PKT_Q1_V1_8821C                                              \\\n\t(BIT_MASK_HEAD_PKT_Q1_V1_8821C << BIT_SHIFT_HEAD_PKT_Q1_V1_8821C)\n#define BIT_CLEAR_HEAD_PKT_Q1_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8821C))\n#define BIT_GET_HEAD_PKT_Q1_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) &                             \\\n\t BIT_MASK_HEAD_PKT_Q1_V1_8821C)\n#define BIT_SET_HEAD_PKT_Q1_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q1_V1_8821C(x) | BIT_HEAD_PKT_Q1_V1_8821C(v))\n\n/* 2 REG_Q2_INFO_8821C */\n\n#define BIT_SHIFT_QUEUEMACID_Q2_V1_8821C 25\n#define BIT_MASK_QUEUEMACID_Q2_V1_8821C 0x7f\n#define BIT_QUEUEMACID_Q2_V1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q2_V1_8821C)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q2_V1_8821C)\n#define BITS_QUEUEMACID_Q2_V1_8821C                                            \\\n\t(BIT_MASK_QUEUEMACID_Q2_V1_8821C << BIT_SHIFT_QUEUEMACID_Q2_V1_8821C)\n#define BIT_CLEAR_QUEUEMACID_Q2_V1_8821C(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q2_V1_8821C))\n#define BIT_GET_QUEUEMACID_Q2_V1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8821C) &                           \\\n\t BIT_MASK_QUEUEMACID_Q2_V1_8821C)\n#define BIT_SET_QUEUEMACID_Q2_V1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q2_V1_8821C(x) | BIT_QUEUEMACID_Q2_V1_8821C(v))\n\n#define BIT_SHIFT_QUEUEAC_Q2_V1_8821C 23\n#define BIT_MASK_QUEUEAC_Q2_V1_8821C 0x3\n#define BIT_QUEUEAC_Q2_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q2_V1_8821C) << BIT_SHIFT_QUEUEAC_Q2_V1_8821C)\n#define BITS_QUEUEAC_Q2_V1_8821C                                               \\\n\t(BIT_MASK_QUEUEAC_Q2_V1_8821C << BIT_SHIFT_QUEUEAC_Q2_V1_8821C)\n#define BIT_CLEAR_QUEUEAC_Q2_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8821C))\n#define BIT_GET_QUEUEAC_Q2_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8821C) & BIT_MASK_QUEUEAC_Q2_V1_8821C)\n#define BIT_SET_QUEUEAC_Q2_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q2_V1_8821C(x) | BIT_QUEUEAC_Q2_V1_8821C(v))\n\n#define BIT_TIDEMPTY_Q2_V1_8821C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q2_V2_8821C 11\n#define BIT_MASK_TAIL_PKT_Q2_V2_8821C 0x7ff\n#define BIT_TAIL_PKT_Q2_V2_8821C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q2_V2_8821C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q2_V2_8821C)\n#define BITS_TAIL_PKT_Q2_V2_8821C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q2_V2_8821C << BIT_SHIFT_TAIL_PKT_Q2_V2_8821C)\n#define BIT_CLEAR_TAIL_PKT_Q2_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8821C))\n#define BIT_GET_TAIL_PKT_Q2_V2_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8821C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q2_V2_8821C)\n#define BIT_SET_TAIL_PKT_Q2_V2_8821C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q2_V2_8821C(x) | BIT_TAIL_PKT_Q2_V2_8821C(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q2_V1_8821C 0\n#define BIT_MASK_HEAD_PKT_Q2_V1_8821C 0x7ff\n#define BIT_HEAD_PKT_Q2_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q2_V1_8821C)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q2_V1_8821C)\n#define BITS_HEAD_PKT_Q2_V1_8821C                                              \\\n\t(BIT_MASK_HEAD_PKT_Q2_V1_8821C << BIT_SHIFT_HEAD_PKT_Q2_V1_8821C)\n#define BIT_CLEAR_HEAD_PKT_Q2_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8821C))\n#define BIT_GET_HEAD_PKT_Q2_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) &                             \\\n\t BIT_MASK_HEAD_PKT_Q2_V1_8821C)\n#define BIT_SET_HEAD_PKT_Q2_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q2_V1_8821C(x) | BIT_HEAD_PKT_Q2_V1_8821C(v))\n\n/* 2 REG_Q3_INFO_8821C */\n\n#define BIT_SHIFT_QUEUEMACID_Q3_V1_8821C 25\n#define BIT_MASK_QUEUEMACID_Q3_V1_8821C 0x7f\n#define BIT_QUEUEMACID_Q3_V1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q3_V1_8821C)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q3_V1_8821C)\n#define BITS_QUEUEMACID_Q3_V1_8821C                                            \\\n\t(BIT_MASK_QUEUEMACID_Q3_V1_8821C << BIT_SHIFT_QUEUEMACID_Q3_V1_8821C)\n#define BIT_CLEAR_QUEUEMACID_Q3_V1_8821C(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q3_V1_8821C))\n#define BIT_GET_QUEUEMACID_Q3_V1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8821C) &                           \\\n\t BIT_MASK_QUEUEMACID_Q3_V1_8821C)\n#define BIT_SET_QUEUEMACID_Q3_V1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q3_V1_8821C(x) | BIT_QUEUEMACID_Q3_V1_8821C(v))\n\n#define BIT_SHIFT_QUEUEAC_Q3_V1_8821C 23\n#define BIT_MASK_QUEUEAC_Q3_V1_8821C 0x3\n#define BIT_QUEUEAC_Q3_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q3_V1_8821C) << BIT_SHIFT_QUEUEAC_Q3_V1_8821C)\n#define BITS_QUEUEAC_Q3_V1_8821C                                               \\\n\t(BIT_MASK_QUEUEAC_Q3_V1_8821C << BIT_SHIFT_QUEUEAC_Q3_V1_8821C)\n#define BIT_CLEAR_QUEUEAC_Q3_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8821C))\n#define BIT_GET_QUEUEAC_Q3_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8821C) & BIT_MASK_QUEUEAC_Q3_V1_8821C)\n#define BIT_SET_QUEUEAC_Q3_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q3_V1_8821C(x) | BIT_QUEUEAC_Q3_V1_8821C(v))\n\n#define BIT_TIDEMPTY_Q3_V1_8821C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q3_V2_8821C 11\n#define BIT_MASK_TAIL_PKT_Q3_V2_8821C 0x7ff\n#define BIT_TAIL_PKT_Q3_V2_8821C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q3_V2_8821C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q3_V2_8821C)\n#define BITS_TAIL_PKT_Q3_V2_8821C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q3_V2_8821C << BIT_SHIFT_TAIL_PKT_Q3_V2_8821C)\n#define BIT_CLEAR_TAIL_PKT_Q3_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8821C))\n#define BIT_GET_TAIL_PKT_Q3_V2_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8821C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q3_V2_8821C)\n#define BIT_SET_TAIL_PKT_Q3_V2_8821C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q3_V2_8821C(x) | BIT_TAIL_PKT_Q3_V2_8821C(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q3_V1_8821C 0\n#define BIT_MASK_HEAD_PKT_Q3_V1_8821C 0x7ff\n#define BIT_HEAD_PKT_Q3_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q3_V1_8821C)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q3_V1_8821C)\n#define BITS_HEAD_PKT_Q3_V1_8821C                                              \\\n\t(BIT_MASK_HEAD_PKT_Q3_V1_8821C << BIT_SHIFT_HEAD_PKT_Q3_V1_8821C)\n#define BIT_CLEAR_HEAD_PKT_Q3_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8821C))\n#define BIT_GET_HEAD_PKT_Q3_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) &                             \\\n\t BIT_MASK_HEAD_PKT_Q3_V1_8821C)\n#define BIT_SET_HEAD_PKT_Q3_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q3_V1_8821C(x) | BIT_HEAD_PKT_Q3_V1_8821C(v))\n\n/* 2 REG_MGQ_INFO_8821C */\n\n#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C 25\n#define BIT_MASK_QUEUEMACID_MGQ_V1_8821C 0x7f\n#define BIT_QUEUEMACID_MGQ_V1_8821C(x)                                         \\\n\t(((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8821C)                              \\\n\t << BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C)\n#define BITS_QUEUEMACID_MGQ_V1_8821C                                           \\\n\t(BIT_MASK_QUEUEMACID_MGQ_V1_8821C << BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C)\n#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8821C(x)                                   \\\n\t((x) & (~BITS_QUEUEMACID_MGQ_V1_8821C))\n#define BIT_GET_QUEUEMACID_MGQ_V1_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C) &                          \\\n\t BIT_MASK_QUEUEMACID_MGQ_V1_8821C)\n#define BIT_SET_QUEUEMACID_MGQ_V1_8821C(x, v)                                  \\\n\t(BIT_CLEAR_QUEUEMACID_MGQ_V1_8821C(x) | BIT_QUEUEMACID_MGQ_V1_8821C(v))\n\n#define BIT_SHIFT_QUEUEAC_MGQ_V1_8821C 23\n#define BIT_MASK_QUEUEAC_MGQ_V1_8821C 0x3\n#define BIT_QUEUEAC_MGQ_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_QUEUEAC_MGQ_V1_8821C)                                 \\\n\t << BIT_SHIFT_QUEUEAC_MGQ_V1_8821C)\n#define BITS_QUEUEAC_MGQ_V1_8821C                                              \\\n\t(BIT_MASK_QUEUEAC_MGQ_V1_8821C << BIT_SHIFT_QUEUEAC_MGQ_V1_8821C)\n#define BIT_CLEAR_QUEUEAC_MGQ_V1_8821C(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8821C))\n#define BIT_GET_QUEUEAC_MGQ_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) &                             \\\n\t BIT_MASK_QUEUEAC_MGQ_V1_8821C)\n#define BIT_SET_QUEUEAC_MGQ_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_QUEUEAC_MGQ_V1_8821C(x) | BIT_QUEUEAC_MGQ_V1_8821C(v))\n\n#define BIT_TIDEMPTY_MGQ_V1_8821C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C 11\n#define BIT_MASK_TAIL_PKT_MGQ_V2_8821C 0x7ff\n#define BIT_TAIL_PKT_MGQ_V2_8821C(x)                                           \\\n\t(((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8821C)                                \\\n\t << BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C)\n#define BITS_TAIL_PKT_MGQ_V2_8821C                                             \\\n\t(BIT_MASK_TAIL_PKT_MGQ_V2_8821C << BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C)\n#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8821C))\n#define BIT_GET_TAIL_PKT_MGQ_V2_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C) &                            \\\n\t BIT_MASK_TAIL_PKT_MGQ_V2_8821C)\n#define BIT_SET_TAIL_PKT_MGQ_V2_8821C(x, v)                                    \\\n\t(BIT_CLEAR_TAIL_PKT_MGQ_V2_8821C(x) | BIT_TAIL_PKT_MGQ_V2_8821C(v))\n\n#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C 0\n#define BIT_MASK_HEAD_PKT_MGQ_V1_8821C 0x7ff\n#define BIT_HEAD_PKT_MGQ_V1_8821C(x)                                           \\\n\t(((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8821C)                                \\\n\t << BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C)\n#define BITS_HEAD_PKT_MGQ_V1_8821C                                             \\\n\t(BIT_MASK_HEAD_PKT_MGQ_V1_8821C << BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C)\n#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8821C))\n#define BIT_GET_HEAD_PKT_MGQ_V1_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) &                            \\\n\t BIT_MASK_HEAD_PKT_MGQ_V1_8821C)\n#define BIT_SET_HEAD_PKT_MGQ_V1_8821C(x, v)                                    \\\n\t(BIT_CLEAR_HEAD_PKT_MGQ_V1_8821C(x) | BIT_HEAD_PKT_MGQ_V1_8821C(v))\n\n/* 2 REG_HIQ_INFO_8821C */\n\n#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C 25\n#define BIT_MASK_QUEUEMACID_HIQ_V1_8821C 0x7f\n#define BIT_QUEUEMACID_HIQ_V1_8821C(x)                                         \\\n\t(((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8821C)                              \\\n\t << BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C)\n#define BITS_QUEUEMACID_HIQ_V1_8821C                                           \\\n\t(BIT_MASK_QUEUEMACID_HIQ_V1_8821C << BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C)\n#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8821C(x)                                   \\\n\t((x) & (~BITS_QUEUEMACID_HIQ_V1_8821C))\n#define BIT_GET_QUEUEMACID_HIQ_V1_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C) &                          \\\n\t BIT_MASK_QUEUEMACID_HIQ_V1_8821C)\n#define BIT_SET_QUEUEMACID_HIQ_V1_8821C(x, v)                                  \\\n\t(BIT_CLEAR_QUEUEMACID_HIQ_V1_8821C(x) | BIT_QUEUEMACID_HIQ_V1_8821C(v))\n\n#define BIT_SHIFT_QUEUEAC_HIQ_V1_8821C 23\n#define BIT_MASK_QUEUEAC_HIQ_V1_8821C 0x3\n#define BIT_QUEUEAC_HIQ_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_QUEUEAC_HIQ_V1_8821C)                                 \\\n\t << BIT_SHIFT_QUEUEAC_HIQ_V1_8821C)\n#define BITS_QUEUEAC_HIQ_V1_8821C                                              \\\n\t(BIT_MASK_QUEUEAC_HIQ_V1_8821C << BIT_SHIFT_QUEUEAC_HIQ_V1_8821C)\n#define BIT_CLEAR_QUEUEAC_HIQ_V1_8821C(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8821C))\n#define BIT_GET_QUEUEAC_HIQ_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) &                             \\\n\t BIT_MASK_QUEUEAC_HIQ_V1_8821C)\n#define BIT_SET_QUEUEAC_HIQ_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_QUEUEAC_HIQ_V1_8821C(x) | BIT_QUEUEAC_HIQ_V1_8821C(v))\n\n#define BIT_TIDEMPTY_HIQ_V1_8821C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C 11\n#define BIT_MASK_TAIL_PKT_HIQ_V2_8821C 0x7ff\n#define BIT_TAIL_PKT_HIQ_V2_8821C(x)                                           \\\n\t(((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8821C)                                \\\n\t << BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C)\n#define BITS_TAIL_PKT_HIQ_V2_8821C                                             \\\n\t(BIT_MASK_TAIL_PKT_HIQ_V2_8821C << BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C)\n#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8821C))\n#define BIT_GET_TAIL_PKT_HIQ_V2_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C) &                            \\\n\t BIT_MASK_TAIL_PKT_HIQ_V2_8821C)\n#define BIT_SET_TAIL_PKT_HIQ_V2_8821C(x, v)                                    \\\n\t(BIT_CLEAR_TAIL_PKT_HIQ_V2_8821C(x) | BIT_TAIL_PKT_HIQ_V2_8821C(v))\n\n#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C 0\n#define BIT_MASK_HEAD_PKT_HIQ_V1_8821C 0x7ff\n#define BIT_HEAD_PKT_HIQ_V1_8821C(x)                                           \\\n\t(((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8821C)                                \\\n\t << BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C)\n#define BITS_HEAD_PKT_HIQ_V1_8821C                                             \\\n\t(BIT_MASK_HEAD_PKT_HIQ_V1_8821C << BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C)\n#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8821C))\n#define BIT_GET_HEAD_PKT_HIQ_V1_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) &                            \\\n\t BIT_MASK_HEAD_PKT_HIQ_V1_8821C)\n#define BIT_SET_HEAD_PKT_HIQ_V1_8821C(x, v)                                    \\\n\t(BIT_CLEAR_HEAD_PKT_HIQ_V1_8821C(x) | BIT_HEAD_PKT_HIQ_V1_8821C(v))\n\n/* 2 REG_BCNQ_INFO_8821C */\n\n#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C 0\n#define BIT_MASK_BCNQ_HEAD_PG_V1_8821C 0xfff\n#define BIT_BCNQ_HEAD_PG_V1_8821C(x)                                           \\\n\t(((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8821C)                                \\\n\t << BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C)\n#define BITS_BCNQ_HEAD_PG_V1_8821C                                             \\\n\t(BIT_MASK_BCNQ_HEAD_PG_V1_8821C << BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C)\n#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8821C(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8821C))\n#define BIT_GET_BCNQ_HEAD_PG_V1_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C) &                            \\\n\t BIT_MASK_BCNQ_HEAD_PG_V1_8821C)\n#define BIT_SET_BCNQ_HEAD_PG_V1_8821C(x, v)                                    \\\n\t(BIT_CLEAR_BCNQ_HEAD_PG_V1_8821C(x) | BIT_BCNQ_HEAD_PG_V1_8821C(v))\n\n/* 2 REG_TXPKT_EMPTY_8821C */\n#define BIT_BCNQ_EMPTY_8821C BIT(11)\n#define BIT_HQQ_EMPTY_8821C BIT(10)\n#define BIT_MQQ_EMPTY_8821C BIT(9)\n#define BIT_MGQ_CPU_EMPTY_8821C BIT(8)\n#define BIT_AC7Q_EMPTY_8821C BIT(7)\n#define BIT_AC6Q_EMPTY_8821C BIT(6)\n#define BIT_AC5Q_EMPTY_8821C BIT(5)\n#define BIT_AC4Q_EMPTY_8821C BIT(4)\n#define BIT_AC3Q_EMPTY_8821C BIT(3)\n#define BIT_AC2Q_EMPTY_8821C BIT(2)\n#define BIT_AC1Q_EMPTY_8821C BIT(1)\n#define BIT_AC0Q_EMPTY_8821C BIT(0)\n\n/* 2 REG_CPU_MGQ_INFO_8821C */\n#define BIT_BCN1_POLL_8821C BIT(30)\n#define BIT_CPUMGT_POLL_8821C BIT(29)\n#define BIT_BCN_POLL_8821C BIT(28)\n#define BIT_CPUMGQ_FW_NUM_V1_8821C BIT(12)\n\n#define BIT_SHIFT_FW_FREE_TAIL_V1_8821C 0\n#define BIT_MASK_FW_FREE_TAIL_V1_8821C 0xfff\n#define BIT_FW_FREE_TAIL_V1_8821C(x)                                           \\\n\t(((x) & BIT_MASK_FW_FREE_TAIL_V1_8821C)                                \\\n\t << BIT_SHIFT_FW_FREE_TAIL_V1_8821C)\n#define BITS_FW_FREE_TAIL_V1_8821C                                             \\\n\t(BIT_MASK_FW_FREE_TAIL_V1_8821C << BIT_SHIFT_FW_FREE_TAIL_V1_8821C)\n#define BIT_CLEAR_FW_FREE_TAIL_V1_8821C(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8821C))\n#define BIT_GET_FW_FREE_TAIL_V1_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8821C) &                            \\\n\t BIT_MASK_FW_FREE_TAIL_V1_8821C)\n#define BIT_SET_FW_FREE_TAIL_V1_8821C(x, v)                                    \\\n\t(BIT_CLEAR_FW_FREE_TAIL_V1_8821C(x) | BIT_FW_FREE_TAIL_V1_8821C(v))\n\n/* 2 REG_FWHW_TXQ_CTRL_8821C */\n#define BIT_RTS_LIMIT_IN_OFDM_8821C BIT(23)\n#define BIT_EN_BCNQ_DL_8821C BIT(22)\n#define BIT_EN_RD_RESP_NAV_BK_8821C BIT(21)\n#define BIT_EN_WR_FREE_TAIL_8821C BIT(20)\n\n#define BIT_SHIFT_EN_QUEUE_RPT_8821C 8\n#define BIT_MASK_EN_QUEUE_RPT_8821C 0xff\n#define BIT_EN_QUEUE_RPT_8821C(x)                                              \\\n\t(((x) & BIT_MASK_EN_QUEUE_RPT_8821C) << BIT_SHIFT_EN_QUEUE_RPT_8821C)\n#define BITS_EN_QUEUE_RPT_8821C                                                \\\n\t(BIT_MASK_EN_QUEUE_RPT_8821C << BIT_SHIFT_EN_QUEUE_RPT_8821C)\n#define BIT_CLEAR_EN_QUEUE_RPT_8821C(x) ((x) & (~BITS_EN_QUEUE_RPT_8821C))\n#define BIT_GET_EN_QUEUE_RPT_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_EN_QUEUE_RPT_8821C) & BIT_MASK_EN_QUEUE_RPT_8821C)\n#define BIT_SET_EN_QUEUE_RPT_8821C(x, v)                                       \\\n\t(BIT_CLEAR_EN_QUEUE_RPT_8821C(x) | BIT_EN_QUEUE_RPT_8821C(v))\n\n#define BIT_EN_RTY_BK_8821C BIT(7)\n#define BIT_EN_USE_INI_RAT_8821C BIT(6)\n#define BIT_EN_RTS_NAV_BK_8821C BIT(5)\n#define BIT_DIS_SSN_CHECK_8821C BIT(4)\n#define BIT_MACID_MATCH_RTS_8821C BIT(3)\n#define BIT_EN_BCN_TRXRPT_V1_8821C BIT(2)\n#define BIT_R_EN_FTMRPT_V1_8821C BIT(1)\n#define BIT_R_BMC_NAV_PROTECT_8821C BIT(0)\n\n/* 2 REG_DATAFB_SEL_8821C */\n#define BIT_BROADCAST_RTY_EN_8821C BIT(3)\n#define BIT_EN_RTY_BK_COD_8821C BIT(2)\n\n#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C 0\n#define BIT_MASK__R_DATA_FALLBACK_SEL_8821C 0x3\n#define BIT__R_DATA_FALLBACK_SEL_8821C(x)                                      \\\n\t(((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8821C)                           \\\n\t << BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C)\n#define BITS__R_DATA_FALLBACK_SEL_8821C                                        \\\n\t(BIT_MASK__R_DATA_FALLBACK_SEL_8821C                                   \\\n\t << BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C)\n#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8821C(x)                                \\\n\t((x) & (~BITS__R_DATA_FALLBACK_SEL_8821C))\n#define BIT_GET__R_DATA_FALLBACK_SEL_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C) &                       \\\n\t BIT_MASK__R_DATA_FALLBACK_SEL_8821C)\n#define BIT_SET__R_DATA_FALLBACK_SEL_8821C(x, v)                               \\\n\t(BIT_CLEAR__R_DATA_FALLBACK_SEL_8821C(x) |                             \\\n\t BIT__R_DATA_FALLBACK_SEL_8821C(v))\n\n/* 2 REG_BCNQ_BDNY_V1_8821C */\n\n#define BIT_SHIFT_BCNQ_PGBNDY_V1_8821C 0\n#define BIT_MASK_BCNQ_PGBNDY_V1_8821C 0xfff\n#define BIT_BCNQ_PGBNDY_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_BCNQ_PGBNDY_V1_8821C)                                 \\\n\t << BIT_SHIFT_BCNQ_PGBNDY_V1_8821C)\n#define BITS_BCNQ_PGBNDY_V1_8821C                                              \\\n\t(BIT_MASK_BCNQ_PGBNDY_V1_8821C << BIT_SHIFT_BCNQ_PGBNDY_V1_8821C)\n#define BIT_CLEAR_BCNQ_PGBNDY_V1_8821C(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8821C))\n#define BIT_GET_BCNQ_PGBNDY_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8821C) &                             \\\n\t BIT_MASK_BCNQ_PGBNDY_V1_8821C)\n#define BIT_SET_BCNQ_PGBNDY_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_BCNQ_PGBNDY_V1_8821C(x) | BIT_BCNQ_PGBNDY_V1_8821C(v))\n\n/* 2 REG_LIFETIME_EN_8821C */\n#define BIT_BT_INT_CPU_8821C BIT(7)\n#define BIT_BT_INT_PTA_8821C BIT(6)\n#define BIT_EN_CTRL_RTYBIT_8821C BIT(4)\n#define BIT_LIFETIME_BK_EN_8821C BIT(3)\n#define BIT_LIFETIME_BE_EN_8821C BIT(2)\n#define BIT_LIFETIME_VI_EN_8821C BIT(1)\n#define BIT_LIFETIME_VO_EN_8821C BIT(0)\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_SPEC_SIFS_8821C */\n\n#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C 8\n#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C 0xff\n#define BIT_SPEC_SIFS_OFDM_PTCL_8821C(x)                                       \\\n\t(((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C)                            \\\n\t << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C)\n#define BITS_SPEC_SIFS_OFDM_PTCL_8821C                                         \\\n\t(BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C                                    \\\n\t << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C)\n#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8821C(x)                                 \\\n\t((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8821C))\n#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C) &                        \\\n\t BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C)\n#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8821C(x, v)                                \\\n\t(BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8821C(x) |                              \\\n\t BIT_SPEC_SIFS_OFDM_PTCL_8821C(v))\n\n#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C 0\n#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C 0xff\n#define BIT_SPEC_SIFS_CCK_PTCL_8821C(x)                                        \\\n\t(((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C)                             \\\n\t << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C)\n#define BITS_SPEC_SIFS_CCK_PTCL_8821C                                          \\\n\t(BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C                                     \\\n\t << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C)\n#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8821C(x)                                  \\\n\t((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8821C))\n#define BIT_GET_SPEC_SIFS_CCK_PTCL_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) &                         \\\n\t BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C)\n#define BIT_SET_SPEC_SIFS_CCK_PTCL_8821C(x, v)                                 \\\n\t(BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8821C(x) |                               \\\n\t BIT_SPEC_SIFS_CCK_PTCL_8821C(v))\n\n/* 2 REG_RETRY_LIMIT_8821C */\n\n#define BIT_SHIFT_SRL_8821C 8\n#define BIT_MASK_SRL_8821C 0x3f\n#define BIT_SRL_8821C(x) (((x) & BIT_MASK_SRL_8821C) << BIT_SHIFT_SRL_8821C)\n#define BITS_SRL_8821C (BIT_MASK_SRL_8821C << BIT_SHIFT_SRL_8821C)\n#define BIT_CLEAR_SRL_8821C(x) ((x) & (~BITS_SRL_8821C))\n#define BIT_GET_SRL_8821C(x) (((x) >> BIT_SHIFT_SRL_8821C) & BIT_MASK_SRL_8821C)\n#define BIT_SET_SRL_8821C(x, v) (BIT_CLEAR_SRL_8821C(x) | BIT_SRL_8821C(v))\n\n#define BIT_SHIFT_LRL_8821C 0\n#define BIT_MASK_LRL_8821C 0x3f\n#define BIT_LRL_8821C(x) (((x) & BIT_MASK_LRL_8821C) << BIT_SHIFT_LRL_8821C)\n#define BITS_LRL_8821C (BIT_MASK_LRL_8821C << BIT_SHIFT_LRL_8821C)\n#define BIT_CLEAR_LRL_8821C(x) ((x) & (~BITS_LRL_8821C))\n#define BIT_GET_LRL_8821C(x) (((x) >> BIT_SHIFT_LRL_8821C) & BIT_MASK_LRL_8821C)\n#define BIT_SET_LRL_8821C(x, v) (BIT_CLEAR_LRL_8821C(x) | BIT_LRL_8821C(v))\n\n/* 2 REG_TXBF_CTRL_8821C */\n#define BIT_R_ENABLE_NDPA_8821C BIT(31)\n#define BIT_USE_NDPA_PARAMETER_8821C BIT(30)\n#define BIT_R_PROP_TXBF_8821C BIT(29)\n#define BIT_R_EN_NDPA_INT_8821C BIT(28)\n#define BIT_R_TXBF1_80M_8821C BIT(27)\n#define BIT_R_TXBF1_40M_8821C BIT(26)\n#define BIT_R_TXBF1_20M_8821C BIT(25)\n\n#define BIT_SHIFT_R_TXBF1_AID_8821C 16\n#define BIT_MASK_R_TXBF1_AID_8821C 0x1ff\n#define BIT_R_TXBF1_AID_8821C(x)                                               \\\n\t(((x) & BIT_MASK_R_TXBF1_AID_8821C) << BIT_SHIFT_R_TXBF1_AID_8821C)\n#define BITS_R_TXBF1_AID_8821C                                                 \\\n\t(BIT_MASK_R_TXBF1_AID_8821C << BIT_SHIFT_R_TXBF1_AID_8821C)\n#define BIT_CLEAR_R_TXBF1_AID_8821C(x) ((x) & (~BITS_R_TXBF1_AID_8821C))\n#define BIT_GET_R_TXBF1_AID_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_R_TXBF1_AID_8821C) & BIT_MASK_R_TXBF1_AID_8821C)\n#define BIT_SET_R_TXBF1_AID_8821C(x, v)                                        \\\n\t(BIT_CLEAR_R_TXBF1_AID_8821C(x) | BIT_R_TXBF1_AID_8821C(v))\n\n#define BIT_DIS_NDP_BFEN_8821C BIT(15)\n#define BIT_R_TXBCN_NOBLOCK_NDP_8821C BIT(14)\n#define BIT_R_TXBF0_80M_8821C BIT(11)\n#define BIT_R_TXBF0_40M_8821C BIT(10)\n#define BIT_R_TXBF0_20M_8821C BIT(9)\n\n#define BIT_SHIFT_R_TXBF0_AID_8821C 0\n#define BIT_MASK_R_TXBF0_AID_8821C 0x1ff\n#define BIT_R_TXBF0_AID_8821C(x)                                               \\\n\t(((x) & BIT_MASK_R_TXBF0_AID_8821C) << BIT_SHIFT_R_TXBF0_AID_8821C)\n#define BITS_R_TXBF0_AID_8821C                                                 \\\n\t(BIT_MASK_R_TXBF0_AID_8821C << BIT_SHIFT_R_TXBF0_AID_8821C)\n#define BIT_CLEAR_R_TXBF0_AID_8821C(x) ((x) & (~BITS_R_TXBF0_AID_8821C))\n#define BIT_GET_R_TXBF0_AID_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_R_TXBF0_AID_8821C) & BIT_MASK_R_TXBF0_AID_8821C)\n#define BIT_SET_R_TXBF0_AID_8821C(x, v)                                        \\\n\t(BIT_CLEAR_R_TXBF0_AID_8821C(x) | BIT_R_TXBF0_AID_8821C(v))\n\n/* 2 REG_DARFRC_8821C */\n\n#define BIT_SHIFT_DARF_RC4_8821C 24\n#define BIT_MASK_DARF_RC4_8821C 0x1f\n#define BIT_DARF_RC4_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_DARF_RC4_8821C) << BIT_SHIFT_DARF_RC4_8821C)\n#define BITS_DARF_RC4_8821C                                                    \\\n\t(BIT_MASK_DARF_RC4_8821C << BIT_SHIFT_DARF_RC4_8821C)\n#define BIT_CLEAR_DARF_RC4_8821C(x) ((x) & (~BITS_DARF_RC4_8821C))\n#define BIT_GET_DARF_RC4_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_DARF_RC4_8821C) & BIT_MASK_DARF_RC4_8821C)\n#define BIT_SET_DARF_RC4_8821C(x, v)                                           \\\n\t(BIT_CLEAR_DARF_RC4_8821C(x) | BIT_DARF_RC4_8821C(v))\n\n#define BIT_SHIFT_DARF_RC3_8821C 16\n#define BIT_MASK_DARF_RC3_8821C 0x1f\n#define BIT_DARF_RC3_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_DARF_RC3_8821C) << BIT_SHIFT_DARF_RC3_8821C)\n#define BITS_DARF_RC3_8821C                                                    \\\n\t(BIT_MASK_DARF_RC3_8821C << BIT_SHIFT_DARF_RC3_8821C)\n#define BIT_CLEAR_DARF_RC3_8821C(x) ((x) & (~BITS_DARF_RC3_8821C))\n#define BIT_GET_DARF_RC3_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_DARF_RC3_8821C) & BIT_MASK_DARF_RC3_8821C)\n#define BIT_SET_DARF_RC3_8821C(x, v)                                           \\\n\t(BIT_CLEAR_DARF_RC3_8821C(x) | BIT_DARF_RC3_8821C(v))\n\n#define BIT_SHIFT_DARF_RC2_8821C 8\n#define BIT_MASK_DARF_RC2_8821C 0x1f\n#define BIT_DARF_RC2_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_DARF_RC2_8821C) << BIT_SHIFT_DARF_RC2_8821C)\n#define BITS_DARF_RC2_8821C                                                    \\\n\t(BIT_MASK_DARF_RC2_8821C << BIT_SHIFT_DARF_RC2_8821C)\n#define BIT_CLEAR_DARF_RC2_8821C(x) ((x) & (~BITS_DARF_RC2_8821C))\n#define BIT_GET_DARF_RC2_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_DARF_RC2_8821C) & BIT_MASK_DARF_RC2_8821C)\n#define BIT_SET_DARF_RC2_8821C(x, v)                                           \\\n\t(BIT_CLEAR_DARF_RC2_8821C(x) | BIT_DARF_RC2_8821C(v))\n\n#define BIT_SHIFT_DARF_RC1_8821C 0\n#define BIT_MASK_DARF_RC1_8821C 0x1f\n#define BIT_DARF_RC1_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_DARF_RC1_8821C) << BIT_SHIFT_DARF_RC1_8821C)\n#define BITS_DARF_RC1_8821C                                                    \\\n\t(BIT_MASK_DARF_RC1_8821C << BIT_SHIFT_DARF_RC1_8821C)\n#define BIT_CLEAR_DARF_RC1_8821C(x) ((x) & (~BITS_DARF_RC1_8821C))\n#define BIT_GET_DARF_RC1_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_DARF_RC1_8821C) & BIT_MASK_DARF_RC1_8821C)\n#define BIT_SET_DARF_RC1_8821C(x, v)                                           \\\n\t(BIT_CLEAR_DARF_RC1_8821C(x) | BIT_DARF_RC1_8821C(v))\n\n/* 2 REG_DARFRCH_8821C */\n\n#define BIT_SHIFT_DARF_RC8_V1_8821C 24\n#define BIT_MASK_DARF_RC8_V1_8821C 0x1f\n#define BIT_DARF_RC8_V1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC8_V1_8821C) << BIT_SHIFT_DARF_RC8_V1_8821C)\n#define BITS_DARF_RC8_V1_8821C                                                 \\\n\t(BIT_MASK_DARF_RC8_V1_8821C << BIT_SHIFT_DARF_RC8_V1_8821C)\n#define BIT_CLEAR_DARF_RC8_V1_8821C(x) ((x) & (~BITS_DARF_RC8_V1_8821C))\n#define BIT_GET_DARF_RC8_V1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC8_V1_8821C) & BIT_MASK_DARF_RC8_V1_8821C)\n#define BIT_SET_DARF_RC8_V1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC8_V1_8821C(x) | BIT_DARF_RC8_V1_8821C(v))\n\n#define BIT_SHIFT_DARF_RC7_V1_8821C 16\n#define BIT_MASK_DARF_RC7_V1_8821C 0x1f\n#define BIT_DARF_RC7_V1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC7_V1_8821C) << BIT_SHIFT_DARF_RC7_V1_8821C)\n#define BITS_DARF_RC7_V1_8821C                                                 \\\n\t(BIT_MASK_DARF_RC7_V1_8821C << BIT_SHIFT_DARF_RC7_V1_8821C)\n#define BIT_CLEAR_DARF_RC7_V1_8821C(x) ((x) & (~BITS_DARF_RC7_V1_8821C))\n#define BIT_GET_DARF_RC7_V1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC7_V1_8821C) & BIT_MASK_DARF_RC7_V1_8821C)\n#define BIT_SET_DARF_RC7_V1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC7_V1_8821C(x) | BIT_DARF_RC7_V1_8821C(v))\n\n#define BIT_SHIFT_DARF_RC6_V1_8821C 8\n#define BIT_MASK_DARF_RC6_V1_8821C 0x1f\n#define BIT_DARF_RC6_V1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC6_V1_8821C) << BIT_SHIFT_DARF_RC6_V1_8821C)\n#define BITS_DARF_RC6_V1_8821C                                                 \\\n\t(BIT_MASK_DARF_RC6_V1_8821C << BIT_SHIFT_DARF_RC6_V1_8821C)\n#define BIT_CLEAR_DARF_RC6_V1_8821C(x) ((x) & (~BITS_DARF_RC6_V1_8821C))\n#define BIT_GET_DARF_RC6_V1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC6_V1_8821C) & BIT_MASK_DARF_RC6_V1_8821C)\n#define BIT_SET_DARF_RC6_V1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC6_V1_8821C(x) | BIT_DARF_RC6_V1_8821C(v))\n\n#define BIT_SHIFT_DARF_RC5_V1_8821C 0\n#define BIT_MASK_DARF_RC5_V1_8821C 0x1f\n#define BIT_DARF_RC5_V1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC5_V1_8821C) << BIT_SHIFT_DARF_RC5_V1_8821C)\n#define BITS_DARF_RC5_V1_8821C                                                 \\\n\t(BIT_MASK_DARF_RC5_V1_8821C << BIT_SHIFT_DARF_RC5_V1_8821C)\n#define BIT_CLEAR_DARF_RC5_V1_8821C(x) ((x) & (~BITS_DARF_RC5_V1_8821C))\n#define BIT_GET_DARF_RC5_V1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC5_V1_8821C) & BIT_MASK_DARF_RC5_V1_8821C)\n#define BIT_SET_DARF_RC5_V1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC5_V1_8821C(x) | BIT_DARF_RC5_V1_8821C(v))\n\n/* 2 REG_RARFRC_8821C */\n\n#define BIT_SHIFT_RARF_RC4_8821C 24\n#define BIT_MASK_RARF_RC4_8821C 0x1f\n#define BIT_RARF_RC4_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC4_8821C) << BIT_SHIFT_RARF_RC4_8821C)\n#define BITS_RARF_RC4_8821C                                                    \\\n\t(BIT_MASK_RARF_RC4_8821C << BIT_SHIFT_RARF_RC4_8821C)\n#define BIT_CLEAR_RARF_RC4_8821C(x) ((x) & (~BITS_RARF_RC4_8821C))\n#define BIT_GET_RARF_RC4_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC4_8821C) & BIT_MASK_RARF_RC4_8821C)\n#define BIT_SET_RARF_RC4_8821C(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC4_8821C(x) | BIT_RARF_RC4_8821C(v))\n\n#define BIT_SHIFT_RARF_RC3_8821C 16\n#define BIT_MASK_RARF_RC3_8821C 0x1f\n#define BIT_RARF_RC3_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC3_8821C) << BIT_SHIFT_RARF_RC3_8821C)\n#define BITS_RARF_RC3_8821C                                                    \\\n\t(BIT_MASK_RARF_RC3_8821C << BIT_SHIFT_RARF_RC3_8821C)\n#define BIT_CLEAR_RARF_RC3_8821C(x) ((x) & (~BITS_RARF_RC3_8821C))\n#define BIT_GET_RARF_RC3_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC3_8821C) & BIT_MASK_RARF_RC3_8821C)\n#define BIT_SET_RARF_RC3_8821C(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC3_8821C(x) | BIT_RARF_RC3_8821C(v))\n\n#define BIT_SHIFT_RARF_RC2_8821C 8\n#define BIT_MASK_RARF_RC2_8821C 0x1f\n#define BIT_RARF_RC2_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC2_8821C) << BIT_SHIFT_RARF_RC2_8821C)\n#define BITS_RARF_RC2_8821C                                                    \\\n\t(BIT_MASK_RARF_RC2_8821C << BIT_SHIFT_RARF_RC2_8821C)\n#define BIT_CLEAR_RARF_RC2_8821C(x) ((x) & (~BITS_RARF_RC2_8821C))\n#define BIT_GET_RARF_RC2_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC2_8821C) & BIT_MASK_RARF_RC2_8821C)\n#define BIT_SET_RARF_RC2_8821C(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC2_8821C(x) | BIT_RARF_RC2_8821C(v))\n\n#define BIT_SHIFT_RARF_RC1_8821C 0\n#define BIT_MASK_RARF_RC1_8821C 0x1f\n#define BIT_RARF_RC1_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC1_8821C) << BIT_SHIFT_RARF_RC1_8821C)\n#define BITS_RARF_RC1_8821C                                                    \\\n\t(BIT_MASK_RARF_RC1_8821C << BIT_SHIFT_RARF_RC1_8821C)\n#define BIT_CLEAR_RARF_RC1_8821C(x) ((x) & (~BITS_RARF_RC1_8821C))\n#define BIT_GET_RARF_RC1_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC1_8821C) & BIT_MASK_RARF_RC1_8821C)\n#define BIT_SET_RARF_RC1_8821C(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC1_8821C(x) | BIT_RARF_RC1_8821C(v))\n\n/* 2 REG_RARFRCH_8821C */\n\n#define BIT_SHIFT_RARF_RC8_V1_8821C 24\n#define BIT_MASK_RARF_RC8_V1_8821C 0x1f\n#define BIT_RARF_RC8_V1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_RARF_RC8_V1_8821C) << BIT_SHIFT_RARF_RC8_V1_8821C)\n#define BITS_RARF_RC8_V1_8821C                                                 \\\n\t(BIT_MASK_RARF_RC8_V1_8821C << BIT_SHIFT_RARF_RC8_V1_8821C)\n#define BIT_CLEAR_RARF_RC8_V1_8821C(x) ((x) & (~BITS_RARF_RC8_V1_8821C))\n#define BIT_GET_RARF_RC8_V1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RARF_RC8_V1_8821C) & BIT_MASK_RARF_RC8_V1_8821C)\n#define BIT_SET_RARF_RC8_V1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_RARF_RC8_V1_8821C(x) | BIT_RARF_RC8_V1_8821C(v))\n\n#define BIT_SHIFT_RARF_RC7_V1_8821C 16\n#define BIT_MASK_RARF_RC7_V1_8821C 0x1f\n#define BIT_RARF_RC7_V1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_RARF_RC7_V1_8821C) << BIT_SHIFT_RARF_RC7_V1_8821C)\n#define BITS_RARF_RC7_V1_8821C                                                 \\\n\t(BIT_MASK_RARF_RC7_V1_8821C << BIT_SHIFT_RARF_RC7_V1_8821C)\n#define BIT_CLEAR_RARF_RC7_V1_8821C(x) ((x) & (~BITS_RARF_RC7_V1_8821C))\n#define BIT_GET_RARF_RC7_V1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RARF_RC7_V1_8821C) & BIT_MASK_RARF_RC7_V1_8821C)\n#define BIT_SET_RARF_RC7_V1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_RARF_RC7_V1_8821C(x) | BIT_RARF_RC7_V1_8821C(v))\n\n#define BIT_SHIFT_RARF_RC6_V1_8821C 8\n#define BIT_MASK_RARF_RC6_V1_8821C 0x1f\n#define BIT_RARF_RC6_V1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_RARF_RC6_V1_8821C) << BIT_SHIFT_RARF_RC6_V1_8821C)\n#define BITS_RARF_RC6_V1_8821C                                                 \\\n\t(BIT_MASK_RARF_RC6_V1_8821C << BIT_SHIFT_RARF_RC6_V1_8821C)\n#define BIT_CLEAR_RARF_RC6_V1_8821C(x) ((x) & (~BITS_RARF_RC6_V1_8821C))\n#define BIT_GET_RARF_RC6_V1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RARF_RC6_V1_8821C) & BIT_MASK_RARF_RC6_V1_8821C)\n#define BIT_SET_RARF_RC6_V1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_RARF_RC6_V1_8821C(x) | BIT_RARF_RC6_V1_8821C(v))\n\n#define BIT_SHIFT_RARF_RC5_V1_8821C 0\n#define BIT_MASK_RARF_RC5_V1_8821C 0x1f\n#define BIT_RARF_RC5_V1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_RARF_RC5_V1_8821C) << BIT_SHIFT_RARF_RC5_V1_8821C)\n#define BITS_RARF_RC5_V1_8821C                                                 \\\n\t(BIT_MASK_RARF_RC5_V1_8821C << BIT_SHIFT_RARF_RC5_V1_8821C)\n#define BIT_CLEAR_RARF_RC5_V1_8821C(x) ((x) & (~BITS_RARF_RC5_V1_8821C))\n#define BIT_GET_RARF_RC5_V1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RARF_RC5_V1_8821C) & BIT_MASK_RARF_RC5_V1_8821C)\n#define BIT_SET_RARF_RC5_V1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_RARF_RC5_V1_8821C(x) | BIT_RARF_RC5_V1_8821C(v))\n\n/* 2 REG_RRSR_8821C */\n\n#define BIT_SHIFT_RRSR_RSC_8821C 21\n#define BIT_MASK_RRSR_RSC_8821C 0x3\n#define BIT_RRSR_RSC_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_RRSR_RSC_8821C) << BIT_SHIFT_RRSR_RSC_8821C)\n#define BITS_RRSR_RSC_8821C                                                    \\\n\t(BIT_MASK_RRSR_RSC_8821C << BIT_SHIFT_RRSR_RSC_8821C)\n#define BIT_CLEAR_RRSR_RSC_8821C(x) ((x) & (~BITS_RRSR_RSC_8821C))\n#define BIT_GET_RRSR_RSC_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RRSR_RSC_8821C) & BIT_MASK_RRSR_RSC_8821C)\n#define BIT_SET_RRSR_RSC_8821C(x, v)                                           \\\n\t(BIT_CLEAR_RRSR_RSC_8821C(x) | BIT_RRSR_RSC_8821C(v))\n\n#define BIT_SHIFT_RRSC_BITMAP_8821C 0\n#define BIT_MASK_RRSC_BITMAP_8821C 0xfffff\n#define BIT_RRSC_BITMAP_8821C(x)                                               \\\n\t(((x) & BIT_MASK_RRSC_BITMAP_8821C) << BIT_SHIFT_RRSC_BITMAP_8821C)\n#define BITS_RRSC_BITMAP_8821C                                                 \\\n\t(BIT_MASK_RRSC_BITMAP_8821C << BIT_SHIFT_RRSC_BITMAP_8821C)\n#define BIT_CLEAR_RRSC_BITMAP_8821C(x) ((x) & (~BITS_RRSC_BITMAP_8821C))\n#define BIT_GET_RRSC_BITMAP_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RRSC_BITMAP_8821C) & BIT_MASK_RRSC_BITMAP_8821C)\n#define BIT_SET_RRSC_BITMAP_8821C(x, v)                                        \\\n\t(BIT_CLEAR_RRSC_BITMAP_8821C(x) | BIT_RRSC_BITMAP_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_ARFR0_8821C */\n\n#define BIT_SHIFT_ARFRL0_8821C 0\n#define BIT_MASK_ARFRL0_8821C 0xffffffffL\n#define BIT_ARFRL0_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRL0_8821C) << BIT_SHIFT_ARFRL0_8821C)\n#define BITS_ARFRL0_8821C (BIT_MASK_ARFRL0_8821C << BIT_SHIFT_ARFRL0_8821C)\n#define BIT_CLEAR_ARFRL0_8821C(x) ((x) & (~BITS_ARFRL0_8821C))\n#define BIT_GET_ARFRL0_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRL0_8821C) & BIT_MASK_ARFRL0_8821C)\n#define BIT_SET_ARFRL0_8821C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRL0_8821C(x) | BIT_ARFRL0_8821C(v))\n\n/* 2 REG_ARFRH0_8821C */\n\n#define BIT_SHIFT_ARFRH0_8821C 0\n#define BIT_MASK_ARFRH0_8821C 0xffffffffL\n#define BIT_ARFRH0_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRH0_8821C) << BIT_SHIFT_ARFRH0_8821C)\n#define BITS_ARFRH0_8821C (BIT_MASK_ARFRH0_8821C << BIT_SHIFT_ARFRH0_8821C)\n#define BIT_CLEAR_ARFRH0_8821C(x) ((x) & (~BITS_ARFRH0_8821C))\n#define BIT_GET_ARFRH0_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRH0_8821C) & BIT_MASK_ARFRH0_8821C)\n#define BIT_SET_ARFRH0_8821C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRH0_8821C(x) | BIT_ARFRH0_8821C(v))\n\n/* 2 REG_ARFR1_V1_8821C */\n\n#define BIT_SHIFT_ARFRL1_8821C 0\n#define BIT_MASK_ARFRL1_8821C 0xffffffffL\n#define BIT_ARFRL1_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRL1_8821C) << BIT_SHIFT_ARFRL1_8821C)\n#define BITS_ARFRL1_8821C (BIT_MASK_ARFRL1_8821C << BIT_SHIFT_ARFRL1_8821C)\n#define BIT_CLEAR_ARFRL1_8821C(x) ((x) & (~BITS_ARFRL1_8821C))\n#define BIT_GET_ARFRL1_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRL1_8821C) & BIT_MASK_ARFRL1_8821C)\n#define BIT_SET_ARFRL1_8821C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRL1_8821C(x) | BIT_ARFRL1_8821C(v))\n\n/* 2 REG_ARFRH1_V1_8821C */\n\n#define BIT_SHIFT_ARFRH1_8821C 0\n#define BIT_MASK_ARFRH1_8821C 0xffffffffL\n#define BIT_ARFRH1_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRH1_8821C) << BIT_SHIFT_ARFRH1_8821C)\n#define BITS_ARFRH1_8821C (BIT_MASK_ARFRH1_8821C << BIT_SHIFT_ARFRH1_8821C)\n#define BIT_CLEAR_ARFRH1_8821C(x) ((x) & (~BITS_ARFRH1_8821C))\n#define BIT_GET_ARFRH1_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRH1_8821C) & BIT_MASK_ARFRH1_8821C)\n#define BIT_SET_ARFRH1_8821C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRH1_8821C(x) | BIT_ARFRH1_8821C(v))\n\n/* 2 REG_CCK_CHECK_8821C */\n#define BIT_CHECK_CCK_EN_8821C BIT(7)\n#define BIT_EN_BCN_PKT_REL_8821C BIT(6)\n#define BIT_BCN_PORT_SEL_8821C BIT(5)\n#define BIT_MOREDATA_BYPASS_8821C BIT(4)\n#define BIT_EN_CLR_CMD_REL_BCN_PKT_8821C BIT(3)\n#define BIT_R_EN_SET_MOREDATA_8821C BIT(2)\n#define BIT__R_DIS_CLEAR_MACID_RELEASE_8821C BIT(1)\n#define BIT__R_MACID_RELEASE_EN_8821C BIT(0)\n\n/* 2 REG_AMPDU_MAX_TIME_V1_8821C */\n\n#define BIT_SHIFT_AMPDU_MAX_TIME_8821C 0\n#define BIT_MASK_AMPDU_MAX_TIME_8821C 0xff\n#define BIT_AMPDU_MAX_TIME_8821C(x)                                            \\\n\t(((x) & BIT_MASK_AMPDU_MAX_TIME_8821C)                                 \\\n\t << BIT_SHIFT_AMPDU_MAX_TIME_8821C)\n#define BITS_AMPDU_MAX_TIME_8821C                                              \\\n\t(BIT_MASK_AMPDU_MAX_TIME_8821C << BIT_SHIFT_AMPDU_MAX_TIME_8821C)\n#define BIT_CLEAR_AMPDU_MAX_TIME_8821C(x) ((x) & (~BITS_AMPDU_MAX_TIME_8821C))\n#define BIT_GET_AMPDU_MAX_TIME_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8821C) &                             \\\n\t BIT_MASK_AMPDU_MAX_TIME_8821C)\n#define BIT_SET_AMPDU_MAX_TIME_8821C(x, v)                                     \\\n\t(BIT_CLEAR_AMPDU_MAX_TIME_8821C(x) | BIT_AMPDU_MAX_TIME_8821C(v))\n\n/* 2 REG_BCNQ1_BDNY_V1_8821C */\n\n#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C 0\n#define BIT_MASK_BCNQ1_PGBNDY_V1_8821C 0xfff\n#define BIT_BCNQ1_PGBNDY_V1_8821C(x)                                           \\\n\t(((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8821C)                                \\\n\t << BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C)\n#define BITS_BCNQ1_PGBNDY_V1_8821C                                             \\\n\t(BIT_MASK_BCNQ1_PGBNDY_V1_8821C << BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C)\n#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8821C(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8821C))\n#define BIT_GET_BCNQ1_PGBNDY_V1_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C) &                            \\\n\t BIT_MASK_BCNQ1_PGBNDY_V1_8821C)\n#define BIT_SET_BCNQ1_PGBNDY_V1_8821C(x, v)                                    \\\n\t(BIT_CLEAR_BCNQ1_PGBNDY_V1_8821C(x) | BIT_BCNQ1_PGBNDY_V1_8821C(v))\n\n/* 2 REG_AMPDU_MAX_LENGTH_8821C */\n\n#define BIT_SHIFT_AMPDU_MAX_LENGTH_8821C 0\n#define BIT_MASK_AMPDU_MAX_LENGTH_8821C 0xffffffffL\n#define BIT_AMPDU_MAX_LENGTH_8821C(x)                                          \\\n\t(((x) & BIT_MASK_AMPDU_MAX_LENGTH_8821C)                               \\\n\t << BIT_SHIFT_AMPDU_MAX_LENGTH_8821C)\n#define BITS_AMPDU_MAX_LENGTH_8821C                                            \\\n\t(BIT_MASK_AMPDU_MAX_LENGTH_8821C << BIT_SHIFT_AMPDU_MAX_LENGTH_8821C)\n#define BIT_CLEAR_AMPDU_MAX_LENGTH_8821C(x)                                    \\\n\t((x) & (~BITS_AMPDU_MAX_LENGTH_8821C))\n#define BIT_GET_AMPDU_MAX_LENGTH_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8821C) &                           \\\n\t BIT_MASK_AMPDU_MAX_LENGTH_8821C)\n#define BIT_SET_AMPDU_MAX_LENGTH_8821C(x, v)                                   \\\n\t(BIT_CLEAR_AMPDU_MAX_LENGTH_8821C(x) | BIT_AMPDU_MAX_LENGTH_8821C(v))\n\n/* 2 REG_ACQ_STOP_8821C */\n#define BIT_AC7Q_STOP_8821C BIT(7)\n#define BIT_AC6Q_STOP_8821C BIT(6)\n#define BIT_AC5Q_STOP_8821C BIT(5)\n#define BIT_AC4Q_STOP_8821C BIT(4)\n#define BIT_AC3Q_STOP_8821C BIT(3)\n#define BIT_AC2Q_STOP_8821C BIT(2)\n#define BIT_AC1Q_STOP_8821C BIT(1)\n#define BIT_AC0Q_STOP_8821C BIT(0)\n\n/* 2 REG_NDPA_RATE_8821C */\n\n#define BIT_SHIFT_R_NDPA_RATE_V1_8821C 0\n#define BIT_MASK_R_NDPA_RATE_V1_8821C 0xff\n#define BIT_R_NDPA_RATE_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_R_NDPA_RATE_V1_8821C)                                 \\\n\t << BIT_SHIFT_R_NDPA_RATE_V1_8821C)\n#define BITS_R_NDPA_RATE_V1_8821C                                              \\\n\t(BIT_MASK_R_NDPA_RATE_V1_8821C << BIT_SHIFT_R_NDPA_RATE_V1_8821C)\n#define BIT_CLEAR_R_NDPA_RATE_V1_8821C(x) ((x) & (~BITS_R_NDPA_RATE_V1_8821C))\n#define BIT_GET_R_NDPA_RATE_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8821C) &                             \\\n\t BIT_MASK_R_NDPA_RATE_V1_8821C)\n#define BIT_SET_R_NDPA_RATE_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_R_NDPA_RATE_V1_8821C(x) | BIT_R_NDPA_RATE_V1_8821C(v))\n\n/* 2 REG_TX_HANG_CTRL_8821C */\n#define BIT_R_EN_GNT_BT_AWAKE_8821C BIT(3)\n#define BIT_EN_EOF_V1_8821C BIT(2)\n#define BIT_DIS_OQT_BLOCK_8821C BIT(1)\n#define BIT_SEARCH_QUEUE_EN_8821C BIT(0)\n\n/* 2 REG_NDPA_OPT_CTRL_8821C */\n#define BIT_R_DIS_MACID_RELEASE_RTY_8821C BIT(5)\n\n#define BIT_SHIFT_BW_SIGTA_8821C 3\n#define BIT_MASK_BW_SIGTA_8821C 0x3\n#define BIT_BW_SIGTA_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_BW_SIGTA_8821C) << BIT_SHIFT_BW_SIGTA_8821C)\n#define BITS_BW_SIGTA_8821C                                                    \\\n\t(BIT_MASK_BW_SIGTA_8821C << BIT_SHIFT_BW_SIGTA_8821C)\n#define BIT_CLEAR_BW_SIGTA_8821C(x) ((x) & (~BITS_BW_SIGTA_8821C))\n#define BIT_GET_BW_SIGTA_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_BW_SIGTA_8821C) & BIT_MASK_BW_SIGTA_8821C)\n#define BIT_SET_BW_SIGTA_8821C(x, v)                                           \\\n\t(BIT_CLEAR_BW_SIGTA_8821C(x) | BIT_BW_SIGTA_8821C(v))\n\n#define BIT_EN_BAR_SIGTA_8821C BIT(2)\n\n#define BIT_SHIFT_R_NDPA_BW_8821C 0\n#define BIT_MASK_R_NDPA_BW_8821C 0x3\n#define BIT_R_NDPA_BW_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_R_NDPA_BW_8821C) << BIT_SHIFT_R_NDPA_BW_8821C)\n#define BITS_R_NDPA_BW_8821C                                                   \\\n\t(BIT_MASK_R_NDPA_BW_8821C << BIT_SHIFT_R_NDPA_BW_8821C)\n#define BIT_CLEAR_R_NDPA_BW_8821C(x) ((x) & (~BITS_R_NDPA_BW_8821C))\n#define BIT_GET_R_NDPA_BW_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_R_NDPA_BW_8821C) & BIT_MASK_R_NDPA_BW_8821C)\n#define BIT_SET_R_NDPA_BW_8821C(x, v)                                          \\\n\t(BIT_CLEAR_R_NDPA_BW_8821C(x) | BIT_R_NDPA_BW_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_RD_RESP_PKT_TH_8821C */\n\n#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C 0\n#define BIT_MASK_RD_RESP_PKT_TH_V1_8821C 0x3f\n#define BIT_RD_RESP_PKT_TH_V1_8821C(x)                                         \\\n\t(((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8821C)                              \\\n\t << BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C)\n#define BITS_RD_RESP_PKT_TH_V1_8821C                                           \\\n\t(BIT_MASK_RD_RESP_PKT_TH_V1_8821C << BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C)\n#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8821C(x)                                   \\\n\t((x) & (~BITS_RD_RESP_PKT_TH_V1_8821C))\n#define BIT_GET_RD_RESP_PKT_TH_V1_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C) &                          \\\n\t BIT_MASK_RD_RESP_PKT_TH_V1_8821C)\n#define BIT_SET_RD_RESP_PKT_TH_V1_8821C(x, v)                                  \\\n\t(BIT_CLEAR_RD_RESP_PKT_TH_V1_8821C(x) | BIT_RD_RESP_PKT_TH_V1_8821C(v))\n\n/* 2 REG_CMDQ_INFO_8821C */\n\n#define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C 25\n#define BIT_MASK_QUEUEMACID_CMDQ_V1_8821C 0x7f\n#define BIT_QUEUEMACID_CMDQ_V1_8821C(x)                                        \\\n\t(((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8821C)                             \\\n\t << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C)\n#define BITS_QUEUEMACID_CMDQ_V1_8821C                                          \\\n\t(BIT_MASK_QUEUEMACID_CMDQ_V1_8821C                                     \\\n\t << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C)\n#define BIT_CLEAR_QUEUEMACID_CMDQ_V1_8821C(x)                                  \\\n\t((x) & (~BITS_QUEUEMACID_CMDQ_V1_8821C))\n#define BIT_GET_QUEUEMACID_CMDQ_V1_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C) &                         \\\n\t BIT_MASK_QUEUEMACID_CMDQ_V1_8821C)\n#define BIT_SET_QUEUEMACID_CMDQ_V1_8821C(x, v)                                 \\\n\t(BIT_CLEAR_QUEUEMACID_CMDQ_V1_8821C(x) |                               \\\n\t BIT_QUEUEMACID_CMDQ_V1_8821C(v))\n\n#define BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C 23\n#define BIT_MASK_QUEUEAC_CMDQ_V1_8821C 0x3\n#define BIT_QUEUEAC_CMDQ_V1_8821C(x)                                           \\\n\t(((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8821C)                                \\\n\t << BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C)\n#define BITS_QUEUEAC_CMDQ_V1_8821C                                             \\\n\t(BIT_MASK_QUEUEAC_CMDQ_V1_8821C << BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C)\n#define BIT_CLEAR_QUEUEAC_CMDQ_V1_8821C(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1_8821C))\n#define BIT_GET_QUEUEAC_CMDQ_V1_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) &                            \\\n\t BIT_MASK_QUEUEAC_CMDQ_V1_8821C)\n#define BIT_SET_QUEUEAC_CMDQ_V1_8821C(x, v)                                    \\\n\t(BIT_CLEAR_QUEUEAC_CMDQ_V1_8821C(x) | BIT_QUEUEAC_CMDQ_V1_8821C(v))\n\n#define BIT_TIDEMPTY_CMDQ_V1_8821C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q4_V2_8821C 11\n#define BIT_MASK_TAIL_PKT_Q4_V2_8821C 0x7ff\n#define BIT_TAIL_PKT_Q4_V2_8821C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q4_V2_8821C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C)\n#define BITS_TAIL_PKT_Q4_V2_8821C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q4_V2_8821C << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C)\n#define BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8821C))\n#define BIT_GET_TAIL_PKT_Q4_V2_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q4_V2_8821C)\n#define BIT_SET_TAIL_PKT_Q4_V2_8821C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) | BIT_TAIL_PKT_Q4_V2_8821C(v))\n\n#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C 0\n#define BIT_MASK_HEAD_PKT_CMDQ_V1_8821C 0x7ff\n#define BIT_HEAD_PKT_CMDQ_V1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8821C)                               \\\n\t << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C)\n#define BITS_HEAD_PKT_CMDQ_V1_8821C                                            \\\n\t(BIT_MASK_HEAD_PKT_CMDQ_V1_8821C << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C)\n#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8821C(x)                                    \\\n\t((x) & (~BITS_HEAD_PKT_CMDQ_V1_8821C))\n#define BIT_GET_HEAD_PKT_CMDQ_V1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) &                           \\\n\t BIT_MASK_HEAD_PKT_CMDQ_V1_8821C)\n#define BIT_SET_HEAD_PKT_CMDQ_V1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_HEAD_PKT_CMDQ_V1_8821C(x) | BIT_HEAD_PKT_CMDQ_V1_8821C(v))\n\n/* 2 REG_Q4_INFO_8821C */\n\n#define BIT_SHIFT_QUEUEMACID_Q4_V1_8821C 25\n#define BIT_MASK_QUEUEMACID_Q4_V1_8821C 0x7f\n#define BIT_QUEUEMACID_Q4_V1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q4_V1_8821C)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q4_V1_8821C)\n#define BITS_QUEUEMACID_Q4_V1_8821C                                            \\\n\t(BIT_MASK_QUEUEMACID_Q4_V1_8821C << BIT_SHIFT_QUEUEMACID_Q4_V1_8821C)\n#define BIT_CLEAR_QUEUEMACID_Q4_V1_8821C(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q4_V1_8821C))\n#define BIT_GET_QUEUEMACID_Q4_V1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8821C) &                           \\\n\t BIT_MASK_QUEUEMACID_Q4_V1_8821C)\n#define BIT_SET_QUEUEMACID_Q4_V1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q4_V1_8821C(x) | BIT_QUEUEMACID_Q4_V1_8821C(v))\n\n#define BIT_SHIFT_QUEUEAC_Q4_V1_8821C 23\n#define BIT_MASK_QUEUEAC_Q4_V1_8821C 0x3\n#define BIT_QUEUEAC_Q4_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q4_V1_8821C) << BIT_SHIFT_QUEUEAC_Q4_V1_8821C)\n#define BITS_QUEUEAC_Q4_V1_8821C                                               \\\n\t(BIT_MASK_QUEUEAC_Q4_V1_8821C << BIT_SHIFT_QUEUEAC_Q4_V1_8821C)\n#define BIT_CLEAR_QUEUEAC_Q4_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8821C))\n#define BIT_GET_QUEUEAC_Q4_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8821C) & BIT_MASK_QUEUEAC_Q4_V1_8821C)\n#define BIT_SET_QUEUEAC_Q4_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q4_V1_8821C(x) | BIT_QUEUEAC_Q4_V1_8821C(v))\n\n#define BIT_TIDEMPTY_Q4_V1_8821C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q4_V2_8821C 11\n#define BIT_MASK_TAIL_PKT_Q4_V2_8821C 0x7ff\n#define BIT_TAIL_PKT_Q4_V2_8821C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q4_V2_8821C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C)\n#define BITS_TAIL_PKT_Q4_V2_8821C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q4_V2_8821C << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C)\n#define BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8821C))\n#define BIT_GET_TAIL_PKT_Q4_V2_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q4_V2_8821C)\n#define BIT_SET_TAIL_PKT_Q4_V2_8821C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) | BIT_TAIL_PKT_Q4_V2_8821C(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q4_V1_8821C 0\n#define BIT_MASK_HEAD_PKT_Q4_V1_8821C 0x7ff\n#define BIT_HEAD_PKT_Q4_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q4_V1_8821C)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q4_V1_8821C)\n#define BITS_HEAD_PKT_Q4_V1_8821C                                              \\\n\t(BIT_MASK_HEAD_PKT_Q4_V1_8821C << BIT_SHIFT_HEAD_PKT_Q4_V1_8821C)\n#define BIT_CLEAR_HEAD_PKT_Q4_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8821C))\n#define BIT_GET_HEAD_PKT_Q4_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) &                             \\\n\t BIT_MASK_HEAD_PKT_Q4_V1_8821C)\n#define BIT_SET_HEAD_PKT_Q4_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q4_V1_8821C(x) | BIT_HEAD_PKT_Q4_V1_8821C(v))\n\n/* 2 REG_Q5_INFO_8821C */\n\n#define BIT_SHIFT_QUEUEMACID_Q5_V1_8821C 25\n#define BIT_MASK_QUEUEMACID_Q5_V1_8821C 0x7f\n#define BIT_QUEUEMACID_Q5_V1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q5_V1_8821C)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q5_V1_8821C)\n#define BITS_QUEUEMACID_Q5_V1_8821C                                            \\\n\t(BIT_MASK_QUEUEMACID_Q5_V1_8821C << BIT_SHIFT_QUEUEMACID_Q5_V1_8821C)\n#define BIT_CLEAR_QUEUEMACID_Q5_V1_8821C(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q5_V1_8821C))\n#define BIT_GET_QUEUEMACID_Q5_V1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8821C) &                           \\\n\t BIT_MASK_QUEUEMACID_Q5_V1_8821C)\n#define BIT_SET_QUEUEMACID_Q5_V1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q5_V1_8821C(x) | BIT_QUEUEMACID_Q5_V1_8821C(v))\n\n#define BIT_SHIFT_QUEUEAC_Q5_V1_8821C 23\n#define BIT_MASK_QUEUEAC_Q5_V1_8821C 0x3\n#define BIT_QUEUEAC_Q5_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q5_V1_8821C) << BIT_SHIFT_QUEUEAC_Q5_V1_8821C)\n#define BITS_QUEUEAC_Q5_V1_8821C                                               \\\n\t(BIT_MASK_QUEUEAC_Q5_V1_8821C << BIT_SHIFT_QUEUEAC_Q5_V1_8821C)\n#define BIT_CLEAR_QUEUEAC_Q5_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8821C))\n#define BIT_GET_QUEUEAC_Q5_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8821C) & BIT_MASK_QUEUEAC_Q5_V1_8821C)\n#define BIT_SET_QUEUEAC_Q5_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q5_V1_8821C(x) | BIT_QUEUEAC_Q5_V1_8821C(v))\n\n#define BIT_TIDEMPTY_Q5_V1_8821C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q5_V2_8821C 11\n#define BIT_MASK_TAIL_PKT_Q5_V2_8821C 0x7ff\n#define BIT_TAIL_PKT_Q5_V2_8821C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q5_V2_8821C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q5_V2_8821C)\n#define BITS_TAIL_PKT_Q5_V2_8821C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q5_V2_8821C << BIT_SHIFT_TAIL_PKT_Q5_V2_8821C)\n#define BIT_CLEAR_TAIL_PKT_Q5_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8821C))\n#define BIT_GET_TAIL_PKT_Q5_V2_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8821C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q5_V2_8821C)\n#define BIT_SET_TAIL_PKT_Q5_V2_8821C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q5_V2_8821C(x) | BIT_TAIL_PKT_Q5_V2_8821C(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q5_V1_8821C 0\n#define BIT_MASK_HEAD_PKT_Q5_V1_8821C 0x7ff\n#define BIT_HEAD_PKT_Q5_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q5_V1_8821C)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q5_V1_8821C)\n#define BITS_HEAD_PKT_Q5_V1_8821C                                              \\\n\t(BIT_MASK_HEAD_PKT_Q5_V1_8821C << BIT_SHIFT_HEAD_PKT_Q5_V1_8821C)\n#define BIT_CLEAR_HEAD_PKT_Q5_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8821C))\n#define BIT_GET_HEAD_PKT_Q5_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) &                             \\\n\t BIT_MASK_HEAD_PKT_Q5_V1_8821C)\n#define BIT_SET_HEAD_PKT_Q5_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q5_V1_8821C(x) | BIT_HEAD_PKT_Q5_V1_8821C(v))\n\n/* 2 REG_Q6_INFO_8821C */\n\n#define BIT_SHIFT_QUEUEMACID_Q6_V1_8821C 25\n#define BIT_MASK_QUEUEMACID_Q6_V1_8821C 0x7f\n#define BIT_QUEUEMACID_Q6_V1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q6_V1_8821C)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q6_V1_8821C)\n#define BITS_QUEUEMACID_Q6_V1_8821C                                            \\\n\t(BIT_MASK_QUEUEMACID_Q6_V1_8821C << BIT_SHIFT_QUEUEMACID_Q6_V1_8821C)\n#define BIT_CLEAR_QUEUEMACID_Q6_V1_8821C(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q6_V1_8821C))\n#define BIT_GET_QUEUEMACID_Q6_V1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8821C) &                           \\\n\t BIT_MASK_QUEUEMACID_Q6_V1_8821C)\n#define BIT_SET_QUEUEMACID_Q6_V1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q6_V1_8821C(x) | BIT_QUEUEMACID_Q6_V1_8821C(v))\n\n#define BIT_SHIFT_QUEUEAC_Q6_V1_8821C 23\n#define BIT_MASK_QUEUEAC_Q6_V1_8821C 0x3\n#define BIT_QUEUEAC_Q6_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q6_V1_8821C) << BIT_SHIFT_QUEUEAC_Q6_V1_8821C)\n#define BITS_QUEUEAC_Q6_V1_8821C                                               \\\n\t(BIT_MASK_QUEUEAC_Q6_V1_8821C << BIT_SHIFT_QUEUEAC_Q6_V1_8821C)\n#define BIT_CLEAR_QUEUEAC_Q6_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8821C))\n#define BIT_GET_QUEUEAC_Q6_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8821C) & BIT_MASK_QUEUEAC_Q6_V1_8821C)\n#define BIT_SET_QUEUEAC_Q6_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q6_V1_8821C(x) | BIT_QUEUEAC_Q6_V1_8821C(v))\n\n#define BIT_TIDEMPTY_Q6_V1_8821C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q6_V2_8821C 11\n#define BIT_MASK_TAIL_PKT_Q6_V2_8821C 0x7ff\n#define BIT_TAIL_PKT_Q6_V2_8821C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q6_V2_8821C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q6_V2_8821C)\n#define BITS_TAIL_PKT_Q6_V2_8821C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q6_V2_8821C << BIT_SHIFT_TAIL_PKT_Q6_V2_8821C)\n#define BIT_CLEAR_TAIL_PKT_Q6_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8821C))\n#define BIT_GET_TAIL_PKT_Q6_V2_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8821C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q6_V2_8821C)\n#define BIT_SET_TAIL_PKT_Q6_V2_8821C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q6_V2_8821C(x) | BIT_TAIL_PKT_Q6_V2_8821C(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q6_V1_8821C 0\n#define BIT_MASK_HEAD_PKT_Q6_V1_8821C 0x7ff\n#define BIT_HEAD_PKT_Q6_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q6_V1_8821C)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q6_V1_8821C)\n#define BITS_HEAD_PKT_Q6_V1_8821C                                              \\\n\t(BIT_MASK_HEAD_PKT_Q6_V1_8821C << BIT_SHIFT_HEAD_PKT_Q6_V1_8821C)\n#define BIT_CLEAR_HEAD_PKT_Q6_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8821C))\n#define BIT_GET_HEAD_PKT_Q6_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) &                             \\\n\t BIT_MASK_HEAD_PKT_Q6_V1_8821C)\n#define BIT_SET_HEAD_PKT_Q6_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q6_V1_8821C(x) | BIT_HEAD_PKT_Q6_V1_8821C(v))\n\n/* 2 REG_Q7_INFO_8821C */\n\n#define BIT_SHIFT_QUEUEMACID_Q7_V1_8821C 25\n#define BIT_MASK_QUEUEMACID_Q7_V1_8821C 0x7f\n#define BIT_QUEUEMACID_Q7_V1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q7_V1_8821C)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q7_V1_8821C)\n#define BITS_QUEUEMACID_Q7_V1_8821C                                            \\\n\t(BIT_MASK_QUEUEMACID_Q7_V1_8821C << BIT_SHIFT_QUEUEMACID_Q7_V1_8821C)\n#define BIT_CLEAR_QUEUEMACID_Q7_V1_8821C(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q7_V1_8821C))\n#define BIT_GET_QUEUEMACID_Q7_V1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8821C) &                           \\\n\t BIT_MASK_QUEUEMACID_Q7_V1_8821C)\n#define BIT_SET_QUEUEMACID_Q7_V1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q7_V1_8821C(x) | BIT_QUEUEMACID_Q7_V1_8821C(v))\n\n#define BIT_SHIFT_QUEUEAC_Q7_V1_8821C 23\n#define BIT_MASK_QUEUEAC_Q7_V1_8821C 0x3\n#define BIT_QUEUEAC_Q7_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q7_V1_8821C) << BIT_SHIFT_QUEUEAC_Q7_V1_8821C)\n#define BITS_QUEUEAC_Q7_V1_8821C                                               \\\n\t(BIT_MASK_QUEUEAC_Q7_V1_8821C << BIT_SHIFT_QUEUEAC_Q7_V1_8821C)\n#define BIT_CLEAR_QUEUEAC_Q7_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8821C))\n#define BIT_GET_QUEUEAC_Q7_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8821C) & BIT_MASK_QUEUEAC_Q7_V1_8821C)\n#define BIT_SET_QUEUEAC_Q7_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q7_V1_8821C(x) | BIT_QUEUEAC_Q7_V1_8821C(v))\n\n#define BIT_TIDEMPTY_Q7_V1_8821C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q7_V2_8821C 11\n#define BIT_MASK_TAIL_PKT_Q7_V2_8821C 0x7ff\n#define BIT_TAIL_PKT_Q7_V2_8821C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q7_V2_8821C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q7_V2_8821C)\n#define BITS_TAIL_PKT_Q7_V2_8821C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q7_V2_8821C << BIT_SHIFT_TAIL_PKT_Q7_V2_8821C)\n#define BIT_CLEAR_TAIL_PKT_Q7_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8821C))\n#define BIT_GET_TAIL_PKT_Q7_V2_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8821C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q7_V2_8821C)\n#define BIT_SET_TAIL_PKT_Q7_V2_8821C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q7_V2_8821C(x) | BIT_TAIL_PKT_Q7_V2_8821C(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q7_V1_8821C 0\n#define BIT_MASK_HEAD_PKT_Q7_V1_8821C 0x7ff\n#define BIT_HEAD_PKT_Q7_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q7_V1_8821C)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q7_V1_8821C)\n#define BITS_HEAD_PKT_Q7_V1_8821C                                              \\\n\t(BIT_MASK_HEAD_PKT_Q7_V1_8821C << BIT_SHIFT_HEAD_PKT_Q7_V1_8821C)\n#define BIT_CLEAR_HEAD_PKT_Q7_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8821C))\n#define BIT_GET_HEAD_PKT_Q7_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) &                             \\\n\t BIT_MASK_HEAD_PKT_Q7_V1_8821C)\n#define BIT_SET_HEAD_PKT_Q7_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q7_V1_8821C(x) | BIT_HEAD_PKT_Q7_V1_8821C(v))\n\n/* 2 REG_WMAC_LBK_BUF_HD_V1_8821C */\n\n#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C 0\n#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C 0xfff\n#define BIT_WMAC_LBK_BUF_HEAD_V1_8821C(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C)                           \\\n\t << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C)\n#define BITS_WMAC_LBK_BUF_HEAD_V1_8821C                                        \\\n\t(BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C                                   \\\n\t << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C)\n#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8821C(x)                                \\\n\t((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8821C))\n#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C) &                       \\\n\t BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C)\n#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8821C(x, v)                               \\\n\t(BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8821C(x) |                             \\\n\t BIT_WMAC_LBK_BUF_HEAD_V1_8821C(v))\n\n/* 2 REG_MGQ_BDNY_V1_8821C */\n\n#define BIT_SHIFT_MGQ_PGBNDY_V1_8821C 0\n#define BIT_MASK_MGQ_PGBNDY_V1_8821C 0xfff\n#define BIT_MGQ_PGBNDY_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_PGBNDY_V1_8821C) << BIT_SHIFT_MGQ_PGBNDY_V1_8821C)\n#define BITS_MGQ_PGBNDY_V1_8821C                                               \\\n\t(BIT_MASK_MGQ_PGBNDY_V1_8821C << BIT_SHIFT_MGQ_PGBNDY_V1_8821C)\n#define BIT_CLEAR_MGQ_PGBNDY_V1_8821C(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8821C))\n#define BIT_GET_MGQ_PGBNDY_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8821C) & BIT_MASK_MGQ_PGBNDY_V1_8821C)\n#define BIT_SET_MGQ_PGBNDY_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_PGBNDY_V1_8821C(x) | BIT_MGQ_PGBNDY_V1_8821C(v))\n\n/* 2 REG_TXRPT_CTRL_8821C */\n\n#define BIT_SHIFT_TRXRPT_TIMER_TH_8821C 24\n#define BIT_MASK_TRXRPT_TIMER_TH_8821C 0xff\n#define BIT_TRXRPT_TIMER_TH_8821C(x)                                           \\\n\t(((x) & BIT_MASK_TRXRPT_TIMER_TH_8821C)                                \\\n\t << BIT_SHIFT_TRXRPT_TIMER_TH_8821C)\n#define BITS_TRXRPT_TIMER_TH_8821C                                             \\\n\t(BIT_MASK_TRXRPT_TIMER_TH_8821C << BIT_SHIFT_TRXRPT_TIMER_TH_8821C)\n#define BIT_CLEAR_TRXRPT_TIMER_TH_8821C(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8821C))\n#define BIT_GET_TRXRPT_TIMER_TH_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8821C) &                            \\\n\t BIT_MASK_TRXRPT_TIMER_TH_8821C)\n#define BIT_SET_TRXRPT_TIMER_TH_8821C(x, v)                                    \\\n\t(BIT_CLEAR_TRXRPT_TIMER_TH_8821C(x) | BIT_TRXRPT_TIMER_TH_8821C(v))\n\n#define BIT_SHIFT_TRXRPT_LEN_TH_8821C 16\n#define BIT_MASK_TRXRPT_LEN_TH_8821C 0xff\n#define BIT_TRXRPT_LEN_TH_8821C(x)                                             \\\n\t(((x) & BIT_MASK_TRXRPT_LEN_TH_8821C) << BIT_SHIFT_TRXRPT_LEN_TH_8821C)\n#define BITS_TRXRPT_LEN_TH_8821C                                               \\\n\t(BIT_MASK_TRXRPT_LEN_TH_8821C << BIT_SHIFT_TRXRPT_LEN_TH_8821C)\n#define BIT_CLEAR_TRXRPT_LEN_TH_8821C(x) ((x) & (~BITS_TRXRPT_LEN_TH_8821C))\n#define BIT_GET_TRXRPT_LEN_TH_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8821C) & BIT_MASK_TRXRPT_LEN_TH_8821C)\n#define BIT_SET_TRXRPT_LEN_TH_8821C(x, v)                                      \\\n\t(BIT_CLEAR_TRXRPT_LEN_TH_8821C(x) | BIT_TRXRPT_LEN_TH_8821C(v))\n\n#define BIT_SHIFT_TRXRPT_READ_PTR_8821C 8\n#define BIT_MASK_TRXRPT_READ_PTR_8821C 0xff\n#define BIT_TRXRPT_READ_PTR_8821C(x)                                           \\\n\t(((x) & BIT_MASK_TRXRPT_READ_PTR_8821C)                                \\\n\t << BIT_SHIFT_TRXRPT_READ_PTR_8821C)\n#define BITS_TRXRPT_READ_PTR_8821C                                             \\\n\t(BIT_MASK_TRXRPT_READ_PTR_8821C << BIT_SHIFT_TRXRPT_READ_PTR_8821C)\n#define BIT_CLEAR_TRXRPT_READ_PTR_8821C(x) ((x) & (~BITS_TRXRPT_READ_PTR_8821C))\n#define BIT_GET_TRXRPT_READ_PTR_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8821C) &                            \\\n\t BIT_MASK_TRXRPT_READ_PTR_8821C)\n#define BIT_SET_TRXRPT_READ_PTR_8821C(x, v)                                    \\\n\t(BIT_CLEAR_TRXRPT_READ_PTR_8821C(x) | BIT_TRXRPT_READ_PTR_8821C(v))\n\n#define BIT_SHIFT_TRXRPT_WRITE_PTR_8821C 0\n#define BIT_MASK_TRXRPT_WRITE_PTR_8821C 0xff\n#define BIT_TRXRPT_WRITE_PTR_8821C(x)                                          \\\n\t(((x) & BIT_MASK_TRXRPT_WRITE_PTR_8821C)                               \\\n\t << BIT_SHIFT_TRXRPT_WRITE_PTR_8821C)\n#define BITS_TRXRPT_WRITE_PTR_8821C                                            \\\n\t(BIT_MASK_TRXRPT_WRITE_PTR_8821C << BIT_SHIFT_TRXRPT_WRITE_PTR_8821C)\n#define BIT_CLEAR_TRXRPT_WRITE_PTR_8821C(x)                                    \\\n\t((x) & (~BITS_TRXRPT_WRITE_PTR_8821C))\n#define BIT_GET_TRXRPT_WRITE_PTR_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) &                           \\\n\t BIT_MASK_TRXRPT_WRITE_PTR_8821C)\n#define BIT_SET_TRXRPT_WRITE_PTR_8821C(x, v)                                   \\\n\t(BIT_CLEAR_TRXRPT_WRITE_PTR_8821C(x) | BIT_TRXRPT_WRITE_PTR_8821C(v))\n\n/* 2 REG_INIRTS_RATE_SEL_8821C */\n#define BIT_LEAG_RTS_BW_DUP_8821C BIT(5)\n\n/* 2 REG_BASIC_CFEND_RATE_8821C */\n\n#define BIT_SHIFT_BASIC_CFEND_RATE_8821C 0\n#define BIT_MASK_BASIC_CFEND_RATE_8821C 0x1f\n#define BIT_BASIC_CFEND_RATE_8821C(x)                                          \\\n\t(((x) & BIT_MASK_BASIC_CFEND_RATE_8821C)                               \\\n\t << BIT_SHIFT_BASIC_CFEND_RATE_8821C)\n#define BITS_BASIC_CFEND_RATE_8821C                                            \\\n\t(BIT_MASK_BASIC_CFEND_RATE_8821C << BIT_SHIFT_BASIC_CFEND_RATE_8821C)\n#define BIT_CLEAR_BASIC_CFEND_RATE_8821C(x)                                    \\\n\t((x) & (~BITS_BASIC_CFEND_RATE_8821C))\n#define BIT_GET_BASIC_CFEND_RATE_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8821C) &                           \\\n\t BIT_MASK_BASIC_CFEND_RATE_8821C)\n#define BIT_SET_BASIC_CFEND_RATE_8821C(x, v)                                   \\\n\t(BIT_CLEAR_BASIC_CFEND_RATE_8821C(x) | BIT_BASIC_CFEND_RATE_8821C(v))\n\n/* 2 REG_STBC_CFEND_RATE_8821C */\n\n#define BIT_SHIFT_STBC_CFEND_RATE_8821C 0\n#define BIT_MASK_STBC_CFEND_RATE_8821C 0x1f\n#define BIT_STBC_CFEND_RATE_8821C(x)                                           \\\n\t(((x) & BIT_MASK_STBC_CFEND_RATE_8821C)                                \\\n\t << BIT_SHIFT_STBC_CFEND_RATE_8821C)\n#define BITS_STBC_CFEND_RATE_8821C                                             \\\n\t(BIT_MASK_STBC_CFEND_RATE_8821C << BIT_SHIFT_STBC_CFEND_RATE_8821C)\n#define BIT_CLEAR_STBC_CFEND_RATE_8821C(x) ((x) & (~BITS_STBC_CFEND_RATE_8821C))\n#define BIT_GET_STBC_CFEND_RATE_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_STBC_CFEND_RATE_8821C) &                            \\\n\t BIT_MASK_STBC_CFEND_RATE_8821C)\n#define BIT_SET_STBC_CFEND_RATE_8821C(x, v)                                    \\\n\t(BIT_CLEAR_STBC_CFEND_RATE_8821C(x) | BIT_STBC_CFEND_RATE_8821C(v))\n\n/* 2 REG_DATA_SC_8821C */\n\n#define BIT_SHIFT_TXSC_40M_8821C 4\n#define BIT_MASK_TXSC_40M_8821C 0xf\n#define BIT_TXSC_40M_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_TXSC_40M_8821C) << BIT_SHIFT_TXSC_40M_8821C)\n#define BITS_TXSC_40M_8821C                                                    \\\n\t(BIT_MASK_TXSC_40M_8821C << BIT_SHIFT_TXSC_40M_8821C)\n#define BIT_CLEAR_TXSC_40M_8821C(x) ((x) & (~BITS_TXSC_40M_8821C))\n#define BIT_GET_TXSC_40M_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXSC_40M_8821C) & BIT_MASK_TXSC_40M_8821C)\n#define BIT_SET_TXSC_40M_8821C(x, v)                                           \\\n\t(BIT_CLEAR_TXSC_40M_8821C(x) | BIT_TXSC_40M_8821C(v))\n\n#define BIT_SHIFT_TXSC_20M_8821C 0\n#define BIT_MASK_TXSC_20M_8821C 0xf\n#define BIT_TXSC_20M_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_TXSC_20M_8821C) << BIT_SHIFT_TXSC_20M_8821C)\n#define BITS_TXSC_20M_8821C                                                    \\\n\t(BIT_MASK_TXSC_20M_8821C << BIT_SHIFT_TXSC_20M_8821C)\n#define BIT_CLEAR_TXSC_20M_8821C(x) ((x) & (~BITS_TXSC_20M_8821C))\n#define BIT_GET_TXSC_20M_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXSC_20M_8821C) & BIT_MASK_TXSC_20M_8821C)\n#define BIT_SET_TXSC_20M_8821C(x, v)                                           \\\n\t(BIT_CLEAR_TXSC_20M_8821C(x) | BIT_TXSC_20M_8821C(v))\n\n/* 2 REG_MACID_SLEEP3_8821C */\n\n#define BIT_SHIFT_MACID127_96_PKTSLEEP_8821C 0\n#define BIT_MASK_MACID127_96_PKTSLEEP_8821C 0xffffffffL\n#define BIT_MACID127_96_PKTSLEEP_8821C(x)                                      \\\n\t(((x) & BIT_MASK_MACID127_96_PKTSLEEP_8821C)                           \\\n\t << BIT_SHIFT_MACID127_96_PKTSLEEP_8821C)\n#define BITS_MACID127_96_PKTSLEEP_8821C                                        \\\n\t(BIT_MASK_MACID127_96_PKTSLEEP_8821C                                   \\\n\t << BIT_SHIFT_MACID127_96_PKTSLEEP_8821C)\n#define BIT_CLEAR_MACID127_96_PKTSLEEP_8821C(x)                                \\\n\t((x) & (~BITS_MACID127_96_PKTSLEEP_8821C))\n#define BIT_GET_MACID127_96_PKTSLEEP_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8821C) &                       \\\n\t BIT_MASK_MACID127_96_PKTSLEEP_8821C)\n#define BIT_SET_MACID127_96_PKTSLEEP_8821C(x, v)                               \\\n\t(BIT_CLEAR_MACID127_96_PKTSLEEP_8821C(x) |                             \\\n\t BIT_MACID127_96_PKTSLEEP_8821C(v))\n\n/* 2 REG_MACID_SLEEP1_8821C */\n\n#define BIT_SHIFT_MACID63_32_PKTSLEEP_8821C 0\n#define BIT_MASK_MACID63_32_PKTSLEEP_8821C 0xffffffffL\n#define BIT_MACID63_32_PKTSLEEP_8821C(x)                                       \\\n\t(((x) & BIT_MASK_MACID63_32_PKTSLEEP_8821C)                            \\\n\t << BIT_SHIFT_MACID63_32_PKTSLEEP_8821C)\n#define BITS_MACID63_32_PKTSLEEP_8821C                                         \\\n\t(BIT_MASK_MACID63_32_PKTSLEEP_8821C                                    \\\n\t << BIT_SHIFT_MACID63_32_PKTSLEEP_8821C)\n#define BIT_CLEAR_MACID63_32_PKTSLEEP_8821C(x)                                 \\\n\t((x) & (~BITS_MACID63_32_PKTSLEEP_8821C))\n#define BIT_GET_MACID63_32_PKTSLEEP_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8821C) &                        \\\n\t BIT_MASK_MACID63_32_PKTSLEEP_8821C)\n#define BIT_SET_MACID63_32_PKTSLEEP_8821C(x, v)                                \\\n\t(BIT_CLEAR_MACID63_32_PKTSLEEP_8821C(x) |                              \\\n\t BIT_MACID63_32_PKTSLEEP_8821C(v))\n\n/* 2 REG_ARFR2_V1_8821C */\n\n#define BIT_SHIFT_ARFRL2_8821C 0\n#define BIT_MASK_ARFRL2_8821C 0xffffffffL\n#define BIT_ARFRL2_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRL2_8821C) << BIT_SHIFT_ARFRL2_8821C)\n#define BITS_ARFRL2_8821C (BIT_MASK_ARFRL2_8821C << BIT_SHIFT_ARFRL2_8821C)\n#define BIT_CLEAR_ARFRL2_8821C(x) ((x) & (~BITS_ARFRL2_8821C))\n#define BIT_GET_ARFRL2_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRL2_8821C) & BIT_MASK_ARFRL2_8821C)\n#define BIT_SET_ARFRL2_8821C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRL2_8821C(x) | BIT_ARFRL2_8821C(v))\n\n/* 2 REG_ARFRH2_V1_8821C */\n\n#define BIT_SHIFT_ARFRH2_8821C 0\n#define BIT_MASK_ARFRH2_8821C 0xffffffffL\n#define BIT_ARFRH2_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRH2_8821C) << BIT_SHIFT_ARFRH2_8821C)\n#define BITS_ARFRH2_8821C (BIT_MASK_ARFRH2_8821C << BIT_SHIFT_ARFRH2_8821C)\n#define BIT_CLEAR_ARFRH2_8821C(x) ((x) & (~BITS_ARFRH2_8821C))\n#define BIT_GET_ARFRH2_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRH2_8821C) & BIT_MASK_ARFRH2_8821C)\n#define BIT_SET_ARFRH2_8821C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRH2_8821C(x) | BIT_ARFRH2_8821C(v))\n\n/* 2 REG_ARFR3_V1_8821C */\n\n#define BIT_SHIFT_ARFRL3_8821C 0\n#define BIT_MASK_ARFRL3_8821C 0xffffffffL\n#define BIT_ARFRL3_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRL3_8821C) << BIT_SHIFT_ARFRL3_8821C)\n#define BITS_ARFRL3_8821C (BIT_MASK_ARFRL3_8821C << BIT_SHIFT_ARFRL3_8821C)\n#define BIT_CLEAR_ARFRL3_8821C(x) ((x) & (~BITS_ARFRL3_8821C))\n#define BIT_GET_ARFRL3_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRL3_8821C) & BIT_MASK_ARFRL3_8821C)\n#define BIT_SET_ARFRL3_8821C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRL3_8821C(x) | BIT_ARFRL3_8821C(v))\n\n/* 2 REG_ARFRH3_V1_8821C */\n\n#define BIT_SHIFT_ARFRH3_8821C 0\n#define BIT_MASK_ARFRH3_8821C 0xffffffffL\n#define BIT_ARFRH3_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRH3_8821C) << BIT_SHIFT_ARFRH3_8821C)\n#define BITS_ARFRH3_8821C (BIT_MASK_ARFRH3_8821C << BIT_SHIFT_ARFRH3_8821C)\n#define BIT_CLEAR_ARFRH3_8821C(x) ((x) & (~BITS_ARFRH3_8821C))\n#define BIT_GET_ARFRH3_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRH3_8821C) & BIT_MASK_ARFRH3_8821C)\n#define BIT_SET_ARFRH3_8821C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRH3_8821C(x) | BIT_ARFRH3_8821C(v))\n\n/* 2 REG_ARFR4_8821C */\n\n#define BIT_SHIFT_ARFRL4_8821C 0\n#define BIT_MASK_ARFRL4_8821C 0xffffffffL\n#define BIT_ARFRL4_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRL4_8821C) << BIT_SHIFT_ARFRL4_8821C)\n#define BITS_ARFRL4_8821C (BIT_MASK_ARFRL4_8821C << BIT_SHIFT_ARFRL4_8821C)\n#define BIT_CLEAR_ARFRL4_8821C(x) ((x) & (~BITS_ARFRL4_8821C))\n#define BIT_GET_ARFRL4_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRL4_8821C) & BIT_MASK_ARFRL4_8821C)\n#define BIT_SET_ARFRL4_8821C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRL4_8821C(x) | BIT_ARFRL4_8821C(v))\n\n/* 2 REG_ARFRH4_8821C */\n\n#define BIT_SHIFT_ARFRH4_8821C 0\n#define BIT_MASK_ARFRH4_8821C 0xffffffffL\n#define BIT_ARFRH4_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRH4_8821C) << BIT_SHIFT_ARFRH4_8821C)\n#define BITS_ARFRH4_8821C (BIT_MASK_ARFRH4_8821C << BIT_SHIFT_ARFRH4_8821C)\n#define BIT_CLEAR_ARFRH4_8821C(x) ((x) & (~BITS_ARFRH4_8821C))\n#define BIT_GET_ARFRH4_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRH4_8821C) & BIT_MASK_ARFRH4_8821C)\n#define BIT_SET_ARFRH4_8821C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRH4_8821C(x) | BIT_ARFRH4_8821C(v))\n\n/* 2 REG_ARFR5_8821C */\n\n#define BIT_SHIFT_ARFRL5_8821C 0\n#define BIT_MASK_ARFRL5_8821C 0xffffffffL\n#define BIT_ARFRL5_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRL5_8821C) << BIT_SHIFT_ARFRL5_8821C)\n#define BITS_ARFRL5_8821C (BIT_MASK_ARFRL5_8821C << BIT_SHIFT_ARFRL5_8821C)\n#define BIT_CLEAR_ARFRL5_8821C(x) ((x) & (~BITS_ARFRL5_8821C))\n#define BIT_GET_ARFRL5_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRL5_8821C) & BIT_MASK_ARFRL5_8821C)\n#define BIT_SET_ARFRL5_8821C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRL5_8821C(x) | BIT_ARFRL5_8821C(v))\n\n/* 2 REG_ARFRH5_8821C */\n\n#define BIT_SHIFT_ARFRH5_8821C 0\n#define BIT_MASK_ARFRH5_8821C 0xffffffffL\n#define BIT_ARFRH5_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRH5_8821C) << BIT_SHIFT_ARFRH5_8821C)\n#define BITS_ARFRH5_8821C (BIT_MASK_ARFRH5_8821C << BIT_SHIFT_ARFRH5_8821C)\n#define BIT_CLEAR_ARFRH5_8821C(x) ((x) & (~BITS_ARFRH5_8821C))\n#define BIT_GET_ARFRH5_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRH5_8821C) & BIT_MASK_ARFRH5_8821C)\n#define BIT_SET_ARFRH5_8821C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRH5_8821C(x) | BIT_ARFRH5_8821C(v))\n\n/* 2 REG_TXRPT_START_OFFSET_8821C */\n\n#define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C 24\n#define BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C 0xff\n#define BIT_R_MUTAB_TXRPT_OFFSET_8821C(x)                                      \\\n\t(((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C)                           \\\n\t << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C)\n#define BITS_R_MUTAB_TXRPT_OFFSET_8821C                                        \\\n\t(BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C                                   \\\n\t << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C)\n#define BIT_CLEAR_R_MUTAB_TXRPT_OFFSET_8821C(x)                                \\\n\t((x) & (~BITS_R_MUTAB_TXRPT_OFFSET_8821C))\n#define BIT_GET_R_MUTAB_TXRPT_OFFSET_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) &                       \\\n\t BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C)\n#define BIT_SET_R_MUTAB_TXRPT_OFFSET_8821C(x, v)                               \\\n\t(BIT_CLEAR_R_MUTAB_TXRPT_OFFSET_8821C(x) |                             \\\n\t BIT_R_MUTAB_TXRPT_OFFSET_8821C(v))\n\n#define BIT__R_RPTFIFO_1K_8821C BIT(16)\n\n#define BIT_SHIFT_MACID_CTRL_OFFSET_8821C 8\n#define BIT_MASK_MACID_CTRL_OFFSET_8821C 0xff\n#define BIT_MACID_CTRL_OFFSET_8821C(x)                                         \\\n\t(((x) & BIT_MASK_MACID_CTRL_OFFSET_8821C)                              \\\n\t << BIT_SHIFT_MACID_CTRL_OFFSET_8821C)\n#define BITS_MACID_CTRL_OFFSET_8821C                                           \\\n\t(BIT_MASK_MACID_CTRL_OFFSET_8821C << BIT_SHIFT_MACID_CTRL_OFFSET_8821C)\n#define BIT_CLEAR_MACID_CTRL_OFFSET_8821C(x)                                   \\\n\t((x) & (~BITS_MACID_CTRL_OFFSET_8821C))\n#define BIT_GET_MACID_CTRL_OFFSET_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8821C) &                          \\\n\t BIT_MASK_MACID_CTRL_OFFSET_8821C)\n#define BIT_SET_MACID_CTRL_OFFSET_8821C(x, v)                                  \\\n\t(BIT_CLEAR_MACID_CTRL_OFFSET_8821C(x) | BIT_MACID_CTRL_OFFSET_8821C(v))\n\n#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C 0\n#define BIT_MASK_AMPDU_TXRPT_OFFSET_8821C 0xff\n#define BIT_AMPDU_TXRPT_OFFSET_8821C(x)                                        \\\n\t(((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8821C)                             \\\n\t << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C)\n#define BITS_AMPDU_TXRPT_OFFSET_8821C                                          \\\n\t(BIT_MASK_AMPDU_TXRPT_OFFSET_8821C                                     \\\n\t << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C)\n#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8821C(x)                                  \\\n\t((x) & (~BITS_AMPDU_TXRPT_OFFSET_8821C))\n#define BIT_GET_AMPDU_TXRPT_OFFSET_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) &                         \\\n\t BIT_MASK_AMPDU_TXRPT_OFFSET_8821C)\n#define BIT_SET_AMPDU_TXRPT_OFFSET_8821C(x, v)                                 \\\n\t(BIT_CLEAR_AMPDU_TXRPT_OFFSET_8821C(x) |                               \\\n\t BIT_AMPDU_TXRPT_OFFSET_8821C(v))\n\n/* 2 REG_POWER_STAGE1_8821C */\n#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8821C BIT(31)\n#define BIT_PTA_WL_PRI_MASK_BCNQ_8821C BIT(30)\n#define BIT_PTA_WL_PRI_MASK_HIQ_8821C BIT(29)\n#define BIT_PTA_WL_PRI_MASK_MGQ_8821C BIT(28)\n#define BIT_PTA_WL_PRI_MASK_BK_8821C BIT(27)\n#define BIT_PTA_WL_PRI_MASK_BE_8821C BIT(26)\n#define BIT_PTA_WL_PRI_MASK_VI_8821C BIT(25)\n#define BIT_PTA_WL_PRI_MASK_VO_8821C BIT(24)\n\n#define BIT_SHIFT_POWER_STAGE1_8821C 0\n#define BIT_MASK_POWER_STAGE1_8821C 0xffffff\n#define BIT_POWER_STAGE1_8821C(x)                                              \\\n\t(((x) & BIT_MASK_POWER_STAGE1_8821C) << BIT_SHIFT_POWER_STAGE1_8821C)\n#define BITS_POWER_STAGE1_8821C                                                \\\n\t(BIT_MASK_POWER_STAGE1_8821C << BIT_SHIFT_POWER_STAGE1_8821C)\n#define BIT_CLEAR_POWER_STAGE1_8821C(x) ((x) & (~BITS_POWER_STAGE1_8821C))\n#define BIT_GET_POWER_STAGE1_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_POWER_STAGE1_8821C) & BIT_MASK_POWER_STAGE1_8821C)\n#define BIT_SET_POWER_STAGE1_8821C(x, v)                                       \\\n\t(BIT_CLEAR_POWER_STAGE1_8821C(x) | BIT_POWER_STAGE1_8821C(v))\n\n/* 2 REG_POWER_STAGE2_8821C */\n#define BIT__R_CTRL_PKT_POW_ADJ_8821C BIT(24)\n\n#define BIT_SHIFT_POWER_STAGE2_8821C 0\n#define BIT_MASK_POWER_STAGE2_8821C 0xffffff\n#define BIT_POWER_STAGE2_8821C(x)                                              \\\n\t(((x) & BIT_MASK_POWER_STAGE2_8821C) << BIT_SHIFT_POWER_STAGE2_8821C)\n#define BITS_POWER_STAGE2_8821C                                                \\\n\t(BIT_MASK_POWER_STAGE2_8821C << BIT_SHIFT_POWER_STAGE2_8821C)\n#define BIT_CLEAR_POWER_STAGE2_8821C(x) ((x) & (~BITS_POWER_STAGE2_8821C))\n#define BIT_GET_POWER_STAGE2_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_POWER_STAGE2_8821C) & BIT_MASK_POWER_STAGE2_8821C)\n#define BIT_SET_POWER_STAGE2_8821C(x, v)                                       \\\n\t(BIT_CLEAR_POWER_STAGE2_8821C(x) | BIT_POWER_STAGE2_8821C(v))\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8821C */\n\n#define BIT_SHIFT_PAD_NUM_THRES_8821C 24\n#define BIT_MASK_PAD_NUM_THRES_8821C 0x3f\n#define BIT_PAD_NUM_THRES_8821C(x)                                             \\\n\t(((x) & BIT_MASK_PAD_NUM_THRES_8821C) << BIT_SHIFT_PAD_NUM_THRES_8821C)\n#define BITS_PAD_NUM_THRES_8821C                                               \\\n\t(BIT_MASK_PAD_NUM_THRES_8821C << BIT_SHIFT_PAD_NUM_THRES_8821C)\n#define BIT_CLEAR_PAD_NUM_THRES_8821C(x) ((x) & (~BITS_PAD_NUM_THRES_8821C))\n#define BIT_GET_PAD_NUM_THRES_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PAD_NUM_THRES_8821C) & BIT_MASK_PAD_NUM_THRES_8821C)\n#define BIT_SET_PAD_NUM_THRES_8821C(x, v)                                      \\\n\t(BIT_CLEAR_PAD_NUM_THRES_8821C(x) | BIT_PAD_NUM_THRES_8821C(v))\n\n#define BIT_R_DMA_THIS_QUEUE_BK_8821C BIT(23)\n#define BIT_R_DMA_THIS_QUEUE_BE_8821C BIT(22)\n#define BIT_R_DMA_THIS_QUEUE_VI_8821C BIT(21)\n#define BIT_R_DMA_THIS_QUEUE_VO_8821C BIT(20)\n\n#define BIT_SHIFT_R_TOTAL_LEN_TH_8821C 8\n#define BIT_MASK_R_TOTAL_LEN_TH_8821C 0xfff\n#define BIT_R_TOTAL_LEN_TH_8821C(x)                                            \\\n\t(((x) & BIT_MASK_R_TOTAL_LEN_TH_8821C)                                 \\\n\t << BIT_SHIFT_R_TOTAL_LEN_TH_8821C)\n#define BITS_R_TOTAL_LEN_TH_8821C                                              \\\n\t(BIT_MASK_R_TOTAL_LEN_TH_8821C << BIT_SHIFT_R_TOTAL_LEN_TH_8821C)\n#define BIT_CLEAR_R_TOTAL_LEN_TH_8821C(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8821C))\n#define BIT_GET_R_TOTAL_LEN_TH_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8821C) &                             \\\n\t BIT_MASK_R_TOTAL_LEN_TH_8821C)\n#define BIT_SET_R_TOTAL_LEN_TH_8821C(x, v)                                     \\\n\t(BIT_CLEAR_R_TOTAL_LEN_TH_8821C(x) | BIT_R_TOTAL_LEN_TH_8821C(v))\n\n#define BIT_EN_NEW_EARLY_8821C BIT(7)\n#define BIT_PRE_TX_CMD_8821C BIT(6)\n\n#define BIT_SHIFT_NUM_SCL_EN_8821C 4\n#define BIT_MASK_NUM_SCL_EN_8821C 0x3\n#define BIT_NUM_SCL_EN_8821C(x)                                                \\\n\t(((x) & BIT_MASK_NUM_SCL_EN_8821C) << BIT_SHIFT_NUM_SCL_EN_8821C)\n#define BITS_NUM_SCL_EN_8821C                                                  \\\n\t(BIT_MASK_NUM_SCL_EN_8821C << BIT_SHIFT_NUM_SCL_EN_8821C)\n#define BIT_CLEAR_NUM_SCL_EN_8821C(x) ((x) & (~BITS_NUM_SCL_EN_8821C))\n#define BIT_GET_NUM_SCL_EN_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_NUM_SCL_EN_8821C) & BIT_MASK_NUM_SCL_EN_8821C)\n#define BIT_SET_NUM_SCL_EN_8821C(x, v)                                         \\\n\t(BIT_CLEAR_NUM_SCL_EN_8821C(x) | BIT_NUM_SCL_EN_8821C(v))\n\n#define BIT_BK_EN_8821C BIT(3)\n#define BIT_BE_EN_8821C BIT(2)\n#define BIT_VI_EN_8821C BIT(1)\n#define BIT_VO_EN_8821C BIT(0)\n\n/* 2 REG_PKT_LIFE_TIME_8821C */\n\n#define BIT_SHIFT_PKT_LIFTIME_BEBK_8821C 16\n#define BIT_MASK_PKT_LIFTIME_BEBK_8821C 0xffff\n#define BIT_PKT_LIFTIME_BEBK_8821C(x)                                          \\\n\t(((x) & BIT_MASK_PKT_LIFTIME_BEBK_8821C)                               \\\n\t << BIT_SHIFT_PKT_LIFTIME_BEBK_8821C)\n#define BITS_PKT_LIFTIME_BEBK_8821C                                            \\\n\t(BIT_MASK_PKT_LIFTIME_BEBK_8821C << BIT_SHIFT_PKT_LIFTIME_BEBK_8821C)\n#define BIT_CLEAR_PKT_LIFTIME_BEBK_8821C(x)                                    \\\n\t((x) & (~BITS_PKT_LIFTIME_BEBK_8821C))\n#define BIT_GET_PKT_LIFTIME_BEBK_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8821C) &                           \\\n\t BIT_MASK_PKT_LIFTIME_BEBK_8821C)\n#define BIT_SET_PKT_LIFTIME_BEBK_8821C(x, v)                                   \\\n\t(BIT_CLEAR_PKT_LIFTIME_BEBK_8821C(x) | BIT_PKT_LIFTIME_BEBK_8821C(v))\n\n#define BIT_SHIFT_PKT_LIFTIME_VOVI_8821C 0\n#define BIT_MASK_PKT_LIFTIME_VOVI_8821C 0xffff\n#define BIT_PKT_LIFTIME_VOVI_8821C(x)                                          \\\n\t(((x) & BIT_MASK_PKT_LIFTIME_VOVI_8821C)                               \\\n\t << BIT_SHIFT_PKT_LIFTIME_VOVI_8821C)\n#define BITS_PKT_LIFTIME_VOVI_8821C                                            \\\n\t(BIT_MASK_PKT_LIFTIME_VOVI_8821C << BIT_SHIFT_PKT_LIFTIME_VOVI_8821C)\n#define BIT_CLEAR_PKT_LIFTIME_VOVI_8821C(x)                                    \\\n\t((x) & (~BITS_PKT_LIFTIME_VOVI_8821C))\n#define BIT_GET_PKT_LIFTIME_VOVI_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) &                           \\\n\t BIT_MASK_PKT_LIFTIME_VOVI_8821C)\n#define BIT_SET_PKT_LIFTIME_VOVI_8821C(x, v)                                   \\\n\t(BIT_CLEAR_PKT_LIFTIME_VOVI_8821C(x) | BIT_PKT_LIFTIME_VOVI_8821C(v))\n\n/* 2 REG_STBC_SETTING_8821C */\n\n#define BIT_SHIFT_CDEND_TXTIME_L_8821C 4\n#define BIT_MASK_CDEND_TXTIME_L_8821C 0xf\n#define BIT_CDEND_TXTIME_L_8821C(x)                                            \\\n\t(((x) & BIT_MASK_CDEND_TXTIME_L_8821C)                                 \\\n\t << BIT_SHIFT_CDEND_TXTIME_L_8821C)\n#define BITS_CDEND_TXTIME_L_8821C                                              \\\n\t(BIT_MASK_CDEND_TXTIME_L_8821C << BIT_SHIFT_CDEND_TXTIME_L_8821C)\n#define BIT_CLEAR_CDEND_TXTIME_L_8821C(x) ((x) & (~BITS_CDEND_TXTIME_L_8821C))\n#define BIT_GET_CDEND_TXTIME_L_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_CDEND_TXTIME_L_8821C) &                             \\\n\t BIT_MASK_CDEND_TXTIME_L_8821C)\n#define BIT_SET_CDEND_TXTIME_L_8821C(x, v)                                     \\\n\t(BIT_CLEAR_CDEND_TXTIME_L_8821C(x) | BIT_CDEND_TXTIME_L_8821C(v))\n\n#define BIT_SHIFT_NESS_8821C 2\n#define BIT_MASK_NESS_8821C 0x3\n#define BIT_NESS_8821C(x) (((x) & BIT_MASK_NESS_8821C) << BIT_SHIFT_NESS_8821C)\n#define BITS_NESS_8821C (BIT_MASK_NESS_8821C << BIT_SHIFT_NESS_8821C)\n#define BIT_CLEAR_NESS_8821C(x) ((x) & (~BITS_NESS_8821C))\n#define BIT_GET_NESS_8821C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_NESS_8821C) & BIT_MASK_NESS_8821C)\n#define BIT_SET_NESS_8821C(x, v) (BIT_CLEAR_NESS_8821C(x) | BIT_NESS_8821C(v))\n\n#define BIT_SHIFT_STBC_CFEND_8821C 0\n#define BIT_MASK_STBC_CFEND_8821C 0x3\n#define BIT_STBC_CFEND_8821C(x)                                                \\\n\t(((x) & BIT_MASK_STBC_CFEND_8821C) << BIT_SHIFT_STBC_CFEND_8821C)\n#define BITS_STBC_CFEND_8821C                                                  \\\n\t(BIT_MASK_STBC_CFEND_8821C << BIT_SHIFT_STBC_CFEND_8821C)\n#define BIT_CLEAR_STBC_CFEND_8821C(x) ((x) & (~BITS_STBC_CFEND_8821C))\n#define BIT_GET_STBC_CFEND_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_STBC_CFEND_8821C) & BIT_MASK_STBC_CFEND_8821C)\n#define BIT_SET_STBC_CFEND_8821C(x, v)                                         \\\n\t(BIT_CLEAR_STBC_CFEND_8821C(x) | BIT_STBC_CFEND_8821C(v))\n\n/* 2 REG_STBC_SETTING2_8821C */\n\n#define BIT_SHIFT_CDEND_TXTIME_H_8821C 0\n#define BIT_MASK_CDEND_TXTIME_H_8821C 0x1f\n#define BIT_CDEND_TXTIME_H_8821C(x)                                            \\\n\t(((x) & BIT_MASK_CDEND_TXTIME_H_8821C)                                 \\\n\t << BIT_SHIFT_CDEND_TXTIME_H_8821C)\n#define BITS_CDEND_TXTIME_H_8821C                                              \\\n\t(BIT_MASK_CDEND_TXTIME_H_8821C << BIT_SHIFT_CDEND_TXTIME_H_8821C)\n#define BIT_CLEAR_CDEND_TXTIME_H_8821C(x) ((x) & (~BITS_CDEND_TXTIME_H_8821C))\n#define BIT_GET_CDEND_TXTIME_H_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_CDEND_TXTIME_H_8821C) &                             \\\n\t BIT_MASK_CDEND_TXTIME_H_8821C)\n#define BIT_SET_CDEND_TXTIME_H_8821C(x, v)                                     \\\n\t(BIT_CLEAR_CDEND_TXTIME_H_8821C(x) | BIT_CDEND_TXTIME_H_8821C(v))\n\n/* 2 REG_QUEUE_CTRL_8821C */\n#define BIT_PTA_EDCCA_EN_8821C BIT(5)\n#define BIT_PTA_WL_TX_EN_8821C BIT(4)\n#define BIT_R_USE_DATA_BW_8821C BIT(3)\n#define BIT_TRI_PKT_INT_MODE1_8821C BIT(2)\n#define BIT_TRI_PKT_INT_MODE0_8821C BIT(1)\n#define BIT_ACQ_MODE_SEL_8821C BIT(0)\n\n/* 2 REG_SINGLE_AMPDU_CTRL_8821C */\n#define BIT_EN_SINGLE_APMDU_8821C BIT(7)\n\n/* 2 REG_PROT_MODE_CTRL_8821C */\n\n#define BIT_SHIFT_RTS_MAX_AGG_NUM_8821C 24\n#define BIT_MASK_RTS_MAX_AGG_NUM_8821C 0x3f\n#define BIT_RTS_MAX_AGG_NUM_8821C(x)                                           \\\n\t(((x) & BIT_MASK_RTS_MAX_AGG_NUM_8821C)                                \\\n\t << BIT_SHIFT_RTS_MAX_AGG_NUM_8821C)\n#define BITS_RTS_MAX_AGG_NUM_8821C                                             \\\n\t(BIT_MASK_RTS_MAX_AGG_NUM_8821C << BIT_SHIFT_RTS_MAX_AGG_NUM_8821C)\n#define BIT_CLEAR_RTS_MAX_AGG_NUM_8821C(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8821C))\n#define BIT_GET_RTS_MAX_AGG_NUM_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8821C) &                            \\\n\t BIT_MASK_RTS_MAX_AGG_NUM_8821C)\n#define BIT_SET_RTS_MAX_AGG_NUM_8821C(x, v)                                    \\\n\t(BIT_CLEAR_RTS_MAX_AGG_NUM_8821C(x) | BIT_RTS_MAX_AGG_NUM_8821C(v))\n\n#define BIT_SHIFT_MAX_AGG_NUM_8821C 16\n#define BIT_MASK_MAX_AGG_NUM_8821C 0x3f\n#define BIT_MAX_AGG_NUM_8821C(x)                                               \\\n\t(((x) & BIT_MASK_MAX_AGG_NUM_8821C) << BIT_SHIFT_MAX_AGG_NUM_8821C)\n#define BITS_MAX_AGG_NUM_8821C                                                 \\\n\t(BIT_MASK_MAX_AGG_NUM_8821C << BIT_SHIFT_MAX_AGG_NUM_8821C)\n#define BIT_CLEAR_MAX_AGG_NUM_8821C(x) ((x) & (~BITS_MAX_AGG_NUM_8821C))\n#define BIT_GET_MAX_AGG_NUM_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_MAX_AGG_NUM_8821C) & BIT_MASK_MAX_AGG_NUM_8821C)\n#define BIT_SET_MAX_AGG_NUM_8821C(x, v)                                        \\\n\t(BIT_CLEAR_MAX_AGG_NUM_8821C(x) | BIT_MAX_AGG_NUM_8821C(v))\n\n#define BIT_SHIFT_RTS_TXTIME_TH_8821C 8\n#define BIT_MASK_RTS_TXTIME_TH_8821C 0xff\n#define BIT_RTS_TXTIME_TH_8821C(x)                                             \\\n\t(((x) & BIT_MASK_RTS_TXTIME_TH_8821C) << BIT_SHIFT_RTS_TXTIME_TH_8821C)\n#define BITS_RTS_TXTIME_TH_8821C                                               \\\n\t(BIT_MASK_RTS_TXTIME_TH_8821C << BIT_SHIFT_RTS_TXTIME_TH_8821C)\n#define BIT_CLEAR_RTS_TXTIME_TH_8821C(x) ((x) & (~BITS_RTS_TXTIME_TH_8821C))\n#define BIT_GET_RTS_TXTIME_TH_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_RTS_TXTIME_TH_8821C) & BIT_MASK_RTS_TXTIME_TH_8821C)\n#define BIT_SET_RTS_TXTIME_TH_8821C(x, v)                                      \\\n\t(BIT_CLEAR_RTS_TXTIME_TH_8821C(x) | BIT_RTS_TXTIME_TH_8821C(v))\n\n#define BIT_SHIFT_RTS_LEN_TH_8821C 0\n#define BIT_MASK_RTS_LEN_TH_8821C 0xff\n#define BIT_RTS_LEN_TH_8821C(x)                                                \\\n\t(((x) & BIT_MASK_RTS_LEN_TH_8821C) << BIT_SHIFT_RTS_LEN_TH_8821C)\n#define BITS_RTS_LEN_TH_8821C                                                  \\\n\t(BIT_MASK_RTS_LEN_TH_8821C << BIT_SHIFT_RTS_LEN_TH_8821C)\n#define BIT_CLEAR_RTS_LEN_TH_8821C(x) ((x) & (~BITS_RTS_LEN_TH_8821C))\n#define BIT_GET_RTS_LEN_TH_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_RTS_LEN_TH_8821C) & BIT_MASK_RTS_LEN_TH_8821C)\n#define BIT_SET_RTS_LEN_TH_8821C(x, v)                                         \\\n\t(BIT_CLEAR_RTS_LEN_TH_8821C(x) | BIT_RTS_LEN_TH_8821C(v))\n\n/* 2 REG_BAR_MODE_CTRL_8821C */\n\n#define BIT_SHIFT_BAR_RTY_LMT_8821C 16\n#define BIT_MASK_BAR_RTY_LMT_8821C 0x3\n#define BIT_BAR_RTY_LMT_8821C(x)                                               \\\n\t(((x) & BIT_MASK_BAR_RTY_LMT_8821C) << BIT_SHIFT_BAR_RTY_LMT_8821C)\n#define BITS_BAR_RTY_LMT_8821C                                                 \\\n\t(BIT_MASK_BAR_RTY_LMT_8821C << BIT_SHIFT_BAR_RTY_LMT_8821C)\n#define BIT_CLEAR_BAR_RTY_LMT_8821C(x) ((x) & (~BITS_BAR_RTY_LMT_8821C))\n#define BIT_GET_BAR_RTY_LMT_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_BAR_RTY_LMT_8821C) & BIT_MASK_BAR_RTY_LMT_8821C)\n#define BIT_SET_BAR_RTY_LMT_8821C(x, v)                                        \\\n\t(BIT_CLEAR_BAR_RTY_LMT_8821C(x) | BIT_BAR_RTY_LMT_8821C(v))\n\n#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C 8\n#define BIT_MASK_BAR_PKT_TXTIME_TH_8821C 0xff\n#define BIT_BAR_PKT_TXTIME_TH_8821C(x)                                         \\\n\t(((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8821C)                              \\\n\t << BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C)\n#define BITS_BAR_PKT_TXTIME_TH_8821C                                           \\\n\t(BIT_MASK_BAR_PKT_TXTIME_TH_8821C << BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C)\n#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8821C(x)                                   \\\n\t((x) & (~BITS_BAR_PKT_TXTIME_TH_8821C))\n#define BIT_GET_BAR_PKT_TXTIME_TH_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) &                          \\\n\t BIT_MASK_BAR_PKT_TXTIME_TH_8821C)\n#define BIT_SET_BAR_PKT_TXTIME_TH_8821C(x, v)                                  \\\n\t(BIT_CLEAR_BAR_PKT_TXTIME_TH_8821C(x) | BIT_BAR_PKT_TXTIME_TH_8821C(v))\n\n#define BIT_BAR_EN_V1_8821C BIT(6)\n\n#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C 0\n#define BIT_MASK_BAR_PKTNUM_TH_V1_8821C 0x3f\n#define BIT_BAR_PKTNUM_TH_V1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8821C)                               \\\n\t << BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C)\n#define BITS_BAR_PKTNUM_TH_V1_8821C                                            \\\n\t(BIT_MASK_BAR_PKTNUM_TH_V1_8821C << BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C)\n#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8821C(x)                                    \\\n\t((x) & (~BITS_BAR_PKTNUM_TH_V1_8821C))\n#define BIT_GET_BAR_PKTNUM_TH_V1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C) &                           \\\n\t BIT_MASK_BAR_PKTNUM_TH_V1_8821C)\n#define BIT_SET_BAR_PKTNUM_TH_V1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_BAR_PKTNUM_TH_V1_8821C(x) | BIT_BAR_PKTNUM_TH_V1_8821C(v))\n\n/* 2 REG_RA_TRY_RATE_AGG_LMT_8821C */\n\n#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C 0\n#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C 0x3f\n#define BIT_RA_TRY_RATE_AGG_LMT_V1_8821C(x)                                    \\\n\t(((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C)                         \\\n\t << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C)\n#define BITS_RA_TRY_RATE_AGG_LMT_V1_8821C                                      \\\n\t(BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C                                 \\\n\t << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C)\n#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8821C(x)                              \\\n\t((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8821C))\n#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8821C(x)                                \\\n\t(((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C) &                     \\\n\t BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C)\n#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8821C(x, v)                             \\\n\t(BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8821C(x) |                           \\\n\t BIT_RA_TRY_RATE_AGG_LMT_V1_8821C(v))\n\n/* 2 REG_MACID_SLEEP2_8821C */\n\n#define BIT_SHIFT_MACID95_64PKTSLEEP_8821C 0\n#define BIT_MASK_MACID95_64PKTSLEEP_8821C 0xffffffffL\n#define BIT_MACID95_64PKTSLEEP_8821C(x)                                        \\\n\t(((x) & BIT_MASK_MACID95_64PKTSLEEP_8821C)                             \\\n\t << BIT_SHIFT_MACID95_64PKTSLEEP_8821C)\n#define BITS_MACID95_64PKTSLEEP_8821C                                          \\\n\t(BIT_MASK_MACID95_64PKTSLEEP_8821C                                     \\\n\t << BIT_SHIFT_MACID95_64PKTSLEEP_8821C)\n#define BIT_CLEAR_MACID95_64PKTSLEEP_8821C(x)                                  \\\n\t((x) & (~BITS_MACID95_64PKTSLEEP_8821C))\n#define BIT_GET_MACID95_64PKTSLEEP_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8821C) &                         \\\n\t BIT_MASK_MACID95_64PKTSLEEP_8821C)\n#define BIT_SET_MACID95_64PKTSLEEP_8821C(x, v)                                 \\\n\t(BIT_CLEAR_MACID95_64PKTSLEEP_8821C(x) |                               \\\n\t BIT_MACID95_64PKTSLEEP_8821C(v))\n\n/* 2 REG_MACID_SLEEP_8821C */\n\n#define BIT_SHIFT_MACID31_0_PKTSLEEP_8821C 0\n#define BIT_MASK_MACID31_0_PKTSLEEP_8821C 0xffffffffL\n#define BIT_MACID31_0_PKTSLEEP_8821C(x)                                        \\\n\t(((x) & BIT_MASK_MACID31_0_PKTSLEEP_8821C)                             \\\n\t << BIT_SHIFT_MACID31_0_PKTSLEEP_8821C)\n#define BITS_MACID31_0_PKTSLEEP_8821C                                          \\\n\t(BIT_MASK_MACID31_0_PKTSLEEP_8821C                                     \\\n\t << BIT_SHIFT_MACID31_0_PKTSLEEP_8821C)\n#define BIT_CLEAR_MACID31_0_PKTSLEEP_8821C(x)                                  \\\n\t((x) & (~BITS_MACID31_0_PKTSLEEP_8821C))\n#define BIT_GET_MACID31_0_PKTSLEEP_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8821C) &                         \\\n\t BIT_MASK_MACID31_0_PKTSLEEP_8821C)\n#define BIT_SET_MACID31_0_PKTSLEEP_8821C(x, v)                                 \\\n\t(BIT_CLEAR_MACID31_0_PKTSLEEP_8821C(x) |                               \\\n\t BIT_MACID31_0_PKTSLEEP_8821C(v))\n\n/* 2 REG_HW_SEQ0_8821C */\n\n#define BIT_SHIFT_HW_SSN_SEQ0_8821C 0\n#define BIT_MASK_HW_SSN_SEQ0_8821C 0xfff\n#define BIT_HW_SSN_SEQ0_8821C(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ0_8821C) << BIT_SHIFT_HW_SSN_SEQ0_8821C)\n#define BITS_HW_SSN_SEQ0_8821C                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ0_8821C << BIT_SHIFT_HW_SSN_SEQ0_8821C)\n#define BIT_CLEAR_HW_SSN_SEQ0_8821C(x) ((x) & (~BITS_HW_SSN_SEQ0_8821C))\n#define BIT_GET_HW_SSN_SEQ0_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ0_8821C) & BIT_MASK_HW_SSN_SEQ0_8821C)\n#define BIT_SET_HW_SSN_SEQ0_8821C(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ0_8821C(x) | BIT_HW_SSN_SEQ0_8821C(v))\n\n/* 2 REG_HW_SEQ1_8821C */\n\n#define BIT_SHIFT_HW_SSN_SEQ1_8821C 0\n#define BIT_MASK_HW_SSN_SEQ1_8821C 0xfff\n#define BIT_HW_SSN_SEQ1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ1_8821C) << BIT_SHIFT_HW_SSN_SEQ1_8821C)\n#define BITS_HW_SSN_SEQ1_8821C                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ1_8821C << BIT_SHIFT_HW_SSN_SEQ1_8821C)\n#define BIT_CLEAR_HW_SSN_SEQ1_8821C(x) ((x) & (~BITS_HW_SSN_SEQ1_8821C))\n#define BIT_GET_HW_SSN_SEQ1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ1_8821C) & BIT_MASK_HW_SSN_SEQ1_8821C)\n#define BIT_SET_HW_SSN_SEQ1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ1_8821C(x) | BIT_HW_SSN_SEQ1_8821C(v))\n\n/* 2 REG_HW_SEQ2_8821C */\n\n#define BIT_SHIFT_HW_SSN_SEQ2_8821C 0\n#define BIT_MASK_HW_SSN_SEQ2_8821C 0xfff\n#define BIT_HW_SSN_SEQ2_8821C(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ2_8821C) << BIT_SHIFT_HW_SSN_SEQ2_8821C)\n#define BITS_HW_SSN_SEQ2_8821C                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ2_8821C << BIT_SHIFT_HW_SSN_SEQ2_8821C)\n#define BIT_CLEAR_HW_SSN_SEQ2_8821C(x) ((x) & (~BITS_HW_SSN_SEQ2_8821C))\n#define BIT_GET_HW_SSN_SEQ2_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ2_8821C) & BIT_MASK_HW_SSN_SEQ2_8821C)\n#define BIT_SET_HW_SSN_SEQ2_8821C(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ2_8821C(x) | BIT_HW_SSN_SEQ2_8821C(v))\n\n/* 2 REG_HW_SEQ3_8821C */\n\n#define BIT_SHIFT_CSI_HWSEQ_SEL_8821C 12\n#define BIT_MASK_CSI_HWSEQ_SEL_8821C 0x3\n#define BIT_CSI_HWSEQ_SEL_8821C(x)                                             \\\n\t(((x) & BIT_MASK_CSI_HWSEQ_SEL_8821C) << BIT_SHIFT_CSI_HWSEQ_SEL_8821C)\n#define BITS_CSI_HWSEQ_SEL_8821C                                               \\\n\t(BIT_MASK_CSI_HWSEQ_SEL_8821C << BIT_SHIFT_CSI_HWSEQ_SEL_8821C)\n#define BIT_CLEAR_CSI_HWSEQ_SEL_8821C(x) ((x) & (~BITS_CSI_HWSEQ_SEL_8821C))\n#define BIT_GET_CSI_HWSEQ_SEL_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_CSI_HWSEQ_SEL_8821C) & BIT_MASK_CSI_HWSEQ_SEL_8821C)\n#define BIT_SET_CSI_HWSEQ_SEL_8821C(x, v)                                      \\\n\t(BIT_CLEAR_CSI_HWSEQ_SEL_8821C(x) | BIT_CSI_HWSEQ_SEL_8821C(v))\n\n#define BIT_SHIFT_HW_SSN_SEQ3_8821C 0\n#define BIT_MASK_HW_SSN_SEQ3_8821C 0xfff\n#define BIT_HW_SSN_SEQ3_8821C(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ3_8821C) << BIT_SHIFT_HW_SSN_SEQ3_8821C)\n#define BITS_HW_SSN_SEQ3_8821C                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ3_8821C << BIT_SHIFT_HW_SSN_SEQ3_8821C)\n#define BIT_CLEAR_HW_SSN_SEQ3_8821C(x) ((x) & (~BITS_HW_SSN_SEQ3_8821C))\n#define BIT_GET_HW_SSN_SEQ3_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ3_8821C) & BIT_MASK_HW_SSN_SEQ3_8821C)\n#define BIT_SET_HW_SSN_SEQ3_8821C(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ3_8821C(x) | BIT_HW_SSN_SEQ3_8821C(v))\n\n/* 2 REG_NULL_PKT_STATUS_V1_8821C */\n\n#define BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C 2\n#define BIT_MASK_PTCL_TOTAL_PG_V2_8821C 0x3fff\n#define BIT_PTCL_TOTAL_PG_V2_8821C(x)                                          \\\n\t(((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8821C)                               \\\n\t << BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C)\n#define BITS_PTCL_TOTAL_PG_V2_8821C                                            \\\n\t(BIT_MASK_PTCL_TOTAL_PG_V2_8821C << BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C)\n#define BIT_CLEAR_PTCL_TOTAL_PG_V2_8821C(x)                                    \\\n\t((x) & (~BITS_PTCL_TOTAL_PG_V2_8821C))\n#define BIT_GET_PTCL_TOTAL_PG_V2_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) &                           \\\n\t BIT_MASK_PTCL_TOTAL_PG_V2_8821C)\n#define BIT_SET_PTCL_TOTAL_PG_V2_8821C(x, v)                                   \\\n\t(BIT_CLEAR_PTCL_TOTAL_PG_V2_8821C(x) | BIT_PTCL_TOTAL_PG_V2_8821C(v))\n\n#define BIT_TX_NULL_1_8821C BIT(1)\n#define BIT_TX_NULL_0_8821C BIT(0)\n\n/* 2 REG_PTCL_ERR_STATUS_8821C */\n#define BIT_PTCL_RATE_TABLE_INVALID_8821C BIT(7)\n#define BIT_FTM_T2R_ERROR_8821C BIT(6)\n#define BIT_PTCL_ERR0_8821C BIT(5)\n#define BIT_PTCL_ERR1_8821C BIT(4)\n#define BIT_PTCL_ERR2_8821C BIT(3)\n#define BIT_PTCL_ERR3_8821C BIT(2)\n#define BIT_PTCL_ERR4_8821C BIT(1)\n#define BIT_PTCL_ERR5_8821C BIT(0)\n\n/* 2 REG_NULL_PKT_STATUS_EXTEND_8821C */\n#define BIT_CLI3_TX_NULL_1_8821C BIT(7)\n#define BIT_CLI3_TX_NULL_0_8821C BIT(6)\n#define BIT_CLI2_TX_NULL_1_8821C BIT(5)\n#define BIT_CLI2_TX_NULL_0_8821C BIT(4)\n#define BIT_CLI1_TX_NULL_1_8821C BIT(3)\n#define BIT_CLI1_TX_NULL_0_8821C BIT(2)\n#define BIT_CLI0_TX_NULL_1_8821C BIT(1)\n#define BIT_CLI0_TX_NULL_0_8821C BIT(0)\n\n/* 2 REG_VIDEO_ENHANCEMENT_FUN_8821C */\n#define BIT_HIQ_DROP_8821C BIT(7)\n#define BIT_MGQ_DROP_8821C BIT(6)\n#define BIT_VIDEO_JUST_DROP_8821C BIT(1)\n#define BIT_VIDEO_ENHANCEMENT_FUN_EN_8821C BIT(0)\n\n/* 2 REG_PRECNT_CTRL_8821C */\n#define BIT_EN_PRECNT_8821C BIT(11)\n\n#define BIT_SHIFT_PRECNT_TH_8821C 0\n#define BIT_MASK_PRECNT_TH_8821C 0x7ff\n#define BIT_PRECNT_TH_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_PRECNT_TH_8821C) << BIT_SHIFT_PRECNT_TH_8821C)\n#define BITS_PRECNT_TH_8821C                                                   \\\n\t(BIT_MASK_PRECNT_TH_8821C << BIT_SHIFT_PRECNT_TH_8821C)\n#define BIT_CLEAR_PRECNT_TH_8821C(x) ((x) & (~BITS_PRECNT_TH_8821C))\n#define BIT_GET_PRECNT_TH_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_PRECNT_TH_8821C) & BIT_MASK_PRECNT_TH_8821C)\n#define BIT_SET_PRECNT_TH_8821C(x, v)                                          \\\n\t(BIT_CLEAR_PRECNT_TH_8821C(x) | BIT_PRECNT_TH_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_BT_POLLUTE_PKT_CNT_8821C */\n\n#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C 0\n#define BIT_MASK_BT_POLLUTE_PKT_CNT_8821C 0xffff\n#define BIT_BT_POLLUTE_PKT_CNT_8821C(x)                                        \\\n\t(((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8821C)                             \\\n\t << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C)\n#define BITS_BT_POLLUTE_PKT_CNT_8821C                                          \\\n\t(BIT_MASK_BT_POLLUTE_PKT_CNT_8821C                                     \\\n\t << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C)\n#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8821C(x)                                  \\\n\t((x) & (~BITS_BT_POLLUTE_PKT_CNT_8821C))\n#define BIT_GET_BT_POLLUTE_PKT_CNT_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C) &                         \\\n\t BIT_MASK_BT_POLLUTE_PKT_CNT_8821C)\n#define BIT_SET_BT_POLLUTE_PKT_CNT_8821C(x, v)                                 \\\n\t(BIT_CLEAR_BT_POLLUTE_PKT_CNT_8821C(x) |                               \\\n\t BIT_BT_POLLUTE_PKT_CNT_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_PTCL_DBG_8821C */\n\n#define BIT_SHIFT_PTCL_DBG_8821C 0\n#define BIT_MASK_PTCL_DBG_8821C 0xffffffffL\n#define BIT_PTCL_DBG_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_PTCL_DBG_8821C) << BIT_SHIFT_PTCL_DBG_8821C)\n#define BITS_PTCL_DBG_8821C                                                    \\\n\t(BIT_MASK_PTCL_DBG_8821C << BIT_SHIFT_PTCL_DBG_8821C)\n#define BIT_CLEAR_PTCL_DBG_8821C(x) ((x) & (~BITS_PTCL_DBG_8821C))\n#define BIT_GET_PTCL_DBG_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_PTCL_DBG_8821C) & BIT_MASK_PTCL_DBG_8821C)\n#define BIT_SET_PTCL_DBG_8821C(x, v)                                           \\\n\t(BIT_CLEAR_PTCL_DBG_8821C(x) | BIT_PTCL_DBG_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_CPUMGQ_TIMER_CTRL2_8821C */\n\n#define BIT_SHIFT_TRI_HEAD_ADDR_8821C 16\n#define BIT_MASK_TRI_HEAD_ADDR_8821C 0xfff\n#define BIT_TRI_HEAD_ADDR_8821C(x)                                             \\\n\t(((x) & BIT_MASK_TRI_HEAD_ADDR_8821C) << BIT_SHIFT_TRI_HEAD_ADDR_8821C)\n#define BITS_TRI_HEAD_ADDR_8821C                                               \\\n\t(BIT_MASK_TRI_HEAD_ADDR_8821C << BIT_SHIFT_TRI_HEAD_ADDR_8821C)\n#define BIT_CLEAR_TRI_HEAD_ADDR_8821C(x) ((x) & (~BITS_TRI_HEAD_ADDR_8821C))\n#define BIT_GET_TRI_HEAD_ADDR_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8821C) & BIT_MASK_TRI_HEAD_ADDR_8821C)\n#define BIT_SET_TRI_HEAD_ADDR_8821C(x, v)                                      \\\n\t(BIT_CLEAR_TRI_HEAD_ADDR_8821C(x) | BIT_TRI_HEAD_ADDR_8821C(v))\n\n#define BIT_DROP_TH_EN_8821C BIT(8)\n\n#define BIT_SHIFT_DROP_TH_8821C 0\n#define BIT_MASK_DROP_TH_8821C 0xff\n#define BIT_DROP_TH_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_DROP_TH_8821C) << BIT_SHIFT_DROP_TH_8821C)\n#define BITS_DROP_TH_8821C (BIT_MASK_DROP_TH_8821C << BIT_SHIFT_DROP_TH_8821C)\n#define BIT_CLEAR_DROP_TH_8821C(x) ((x) & (~BITS_DROP_TH_8821C))\n#define BIT_GET_DROP_TH_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_DROP_TH_8821C) & BIT_MASK_DROP_TH_8821C)\n#define BIT_SET_DROP_TH_8821C(x, v)                                            \\\n\t(BIT_CLEAR_DROP_TH_8821C(x) | BIT_DROP_TH_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_DUMMY_PAGE4_V1_8821C */\n\n/* 2 REG_MOREDATA_8821C */\n#define BIT_MOREDATA_CTRL2_EN_V1_8821C BIT(3)\n#define BIT_MOREDATA_CTRL1_EN_V1_8821C BIT(2)\n#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8821C BIT(0)\n\n/* 2 REG_Q0_Q1_INFO_8821C */\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31)\n\n#define BIT_SHIFT_GTAB_ID_8821C 28\n#define BIT_MASK_GTAB_ID_8821C 0x7\n#define BIT_GTAB_ID_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C)\n#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C)\n#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C))\n#define BIT_GET_GTAB_ID_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C)\n#define BIT_SET_GTAB_ID_8821C(x, v)                                            \\\n\t(BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v))\n\n#define BIT_SHIFT_AC1_PKT_INFO_8821C 16\n#define BIT_MASK_AC1_PKT_INFO_8821C 0xfff\n#define BIT_AC1_PKT_INFO_8821C(x)                                              \\\n\t(((x) & BIT_MASK_AC1_PKT_INFO_8821C) << BIT_SHIFT_AC1_PKT_INFO_8821C)\n#define BITS_AC1_PKT_INFO_8821C                                                \\\n\t(BIT_MASK_AC1_PKT_INFO_8821C << BIT_SHIFT_AC1_PKT_INFO_8821C)\n#define BIT_CLEAR_AC1_PKT_INFO_8821C(x) ((x) & (~BITS_AC1_PKT_INFO_8821C))\n#define BIT_GET_AC1_PKT_INFO_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC1_PKT_INFO_8821C) & BIT_MASK_AC1_PKT_INFO_8821C)\n#define BIT_SET_AC1_PKT_INFO_8821C(x, v)                                       \\\n\t(BIT_CLEAR_AC1_PKT_INFO_8821C(x) | BIT_AC1_PKT_INFO_8821C(v))\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15)\n\n#define BIT_SHIFT_GTAB_ID_V1_8821C 12\n#define BIT_MASK_GTAB_ID_V1_8821C 0x7\n#define BIT_GTAB_ID_V1_8821C(x)                                                \\\n\t(((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C)\n#define BITS_GTAB_ID_V1_8821C                                                  \\\n\t(BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C)\n#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C))\n#define BIT_GET_GTAB_ID_V1_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C)\n#define BIT_SET_GTAB_ID_V1_8821C(x, v)                                         \\\n\t(BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v))\n\n#define BIT_SHIFT_AC0_PKT_INFO_8821C 0\n#define BIT_MASK_AC0_PKT_INFO_8821C 0xfff\n#define BIT_AC0_PKT_INFO_8821C(x)                                              \\\n\t(((x) & BIT_MASK_AC0_PKT_INFO_8821C) << BIT_SHIFT_AC0_PKT_INFO_8821C)\n#define BITS_AC0_PKT_INFO_8821C                                                \\\n\t(BIT_MASK_AC0_PKT_INFO_8821C << BIT_SHIFT_AC0_PKT_INFO_8821C)\n#define BIT_CLEAR_AC0_PKT_INFO_8821C(x) ((x) & (~BITS_AC0_PKT_INFO_8821C))\n#define BIT_GET_AC0_PKT_INFO_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC0_PKT_INFO_8821C) & BIT_MASK_AC0_PKT_INFO_8821C)\n#define BIT_SET_AC0_PKT_INFO_8821C(x, v)                                       \\\n\t(BIT_CLEAR_AC0_PKT_INFO_8821C(x) | BIT_AC0_PKT_INFO_8821C(v))\n\n/* 2 REG_Q2_Q3_INFO_8821C */\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31)\n\n#define BIT_SHIFT_GTAB_ID_8821C 28\n#define BIT_MASK_GTAB_ID_8821C 0x7\n#define BIT_GTAB_ID_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C)\n#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C)\n#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C))\n#define BIT_GET_GTAB_ID_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C)\n#define BIT_SET_GTAB_ID_8821C(x, v)                                            \\\n\t(BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v))\n\n#define BIT_SHIFT_AC3_PKT_INFO_8821C 16\n#define BIT_MASK_AC3_PKT_INFO_8821C 0xfff\n#define BIT_AC3_PKT_INFO_8821C(x)                                              \\\n\t(((x) & BIT_MASK_AC3_PKT_INFO_8821C) << BIT_SHIFT_AC3_PKT_INFO_8821C)\n#define BITS_AC3_PKT_INFO_8821C                                                \\\n\t(BIT_MASK_AC3_PKT_INFO_8821C << BIT_SHIFT_AC3_PKT_INFO_8821C)\n#define BIT_CLEAR_AC3_PKT_INFO_8821C(x) ((x) & (~BITS_AC3_PKT_INFO_8821C))\n#define BIT_GET_AC3_PKT_INFO_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC3_PKT_INFO_8821C) & BIT_MASK_AC3_PKT_INFO_8821C)\n#define BIT_SET_AC3_PKT_INFO_8821C(x, v)                                       \\\n\t(BIT_CLEAR_AC3_PKT_INFO_8821C(x) | BIT_AC3_PKT_INFO_8821C(v))\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15)\n\n#define BIT_SHIFT_GTAB_ID_V1_8821C 12\n#define BIT_MASK_GTAB_ID_V1_8821C 0x7\n#define BIT_GTAB_ID_V1_8821C(x)                                                \\\n\t(((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C)\n#define BITS_GTAB_ID_V1_8821C                                                  \\\n\t(BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C)\n#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C))\n#define BIT_GET_GTAB_ID_V1_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C)\n#define BIT_SET_GTAB_ID_V1_8821C(x, v)                                         \\\n\t(BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v))\n\n#define BIT_SHIFT_AC2_PKT_INFO_8821C 0\n#define BIT_MASK_AC2_PKT_INFO_8821C 0xfff\n#define BIT_AC2_PKT_INFO_8821C(x)                                              \\\n\t(((x) & BIT_MASK_AC2_PKT_INFO_8821C) << BIT_SHIFT_AC2_PKT_INFO_8821C)\n#define BITS_AC2_PKT_INFO_8821C                                                \\\n\t(BIT_MASK_AC2_PKT_INFO_8821C << BIT_SHIFT_AC2_PKT_INFO_8821C)\n#define BIT_CLEAR_AC2_PKT_INFO_8821C(x) ((x) & (~BITS_AC2_PKT_INFO_8821C))\n#define BIT_GET_AC2_PKT_INFO_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC2_PKT_INFO_8821C) & BIT_MASK_AC2_PKT_INFO_8821C)\n#define BIT_SET_AC2_PKT_INFO_8821C(x, v)                                       \\\n\t(BIT_CLEAR_AC2_PKT_INFO_8821C(x) | BIT_AC2_PKT_INFO_8821C(v))\n\n/* 2 REG_Q4_Q5_INFO_8821C */\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31)\n\n#define BIT_SHIFT_GTAB_ID_8821C 28\n#define BIT_MASK_GTAB_ID_8821C 0x7\n#define BIT_GTAB_ID_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C)\n#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C)\n#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C))\n#define BIT_GET_GTAB_ID_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C)\n#define BIT_SET_GTAB_ID_8821C(x, v)                                            \\\n\t(BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v))\n\n#define BIT_SHIFT_AC5_PKT_INFO_8821C 16\n#define BIT_MASK_AC5_PKT_INFO_8821C 0xfff\n#define BIT_AC5_PKT_INFO_8821C(x)                                              \\\n\t(((x) & BIT_MASK_AC5_PKT_INFO_8821C) << BIT_SHIFT_AC5_PKT_INFO_8821C)\n#define BITS_AC5_PKT_INFO_8821C                                                \\\n\t(BIT_MASK_AC5_PKT_INFO_8821C << BIT_SHIFT_AC5_PKT_INFO_8821C)\n#define BIT_CLEAR_AC5_PKT_INFO_8821C(x) ((x) & (~BITS_AC5_PKT_INFO_8821C))\n#define BIT_GET_AC5_PKT_INFO_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC5_PKT_INFO_8821C) & BIT_MASK_AC5_PKT_INFO_8821C)\n#define BIT_SET_AC5_PKT_INFO_8821C(x, v)                                       \\\n\t(BIT_CLEAR_AC5_PKT_INFO_8821C(x) | BIT_AC5_PKT_INFO_8821C(v))\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15)\n\n#define BIT_SHIFT_GTAB_ID_V1_8821C 12\n#define BIT_MASK_GTAB_ID_V1_8821C 0x7\n#define BIT_GTAB_ID_V1_8821C(x)                                                \\\n\t(((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C)\n#define BITS_GTAB_ID_V1_8821C                                                  \\\n\t(BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C)\n#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C))\n#define BIT_GET_GTAB_ID_V1_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C)\n#define BIT_SET_GTAB_ID_V1_8821C(x, v)                                         \\\n\t(BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v))\n\n#define BIT_SHIFT_AC4_PKT_INFO_8821C 0\n#define BIT_MASK_AC4_PKT_INFO_8821C 0xfff\n#define BIT_AC4_PKT_INFO_8821C(x)                                              \\\n\t(((x) & BIT_MASK_AC4_PKT_INFO_8821C) << BIT_SHIFT_AC4_PKT_INFO_8821C)\n#define BITS_AC4_PKT_INFO_8821C                                                \\\n\t(BIT_MASK_AC4_PKT_INFO_8821C << BIT_SHIFT_AC4_PKT_INFO_8821C)\n#define BIT_CLEAR_AC4_PKT_INFO_8821C(x) ((x) & (~BITS_AC4_PKT_INFO_8821C))\n#define BIT_GET_AC4_PKT_INFO_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC4_PKT_INFO_8821C) & BIT_MASK_AC4_PKT_INFO_8821C)\n#define BIT_SET_AC4_PKT_INFO_8821C(x, v)                                       \\\n\t(BIT_CLEAR_AC4_PKT_INFO_8821C(x) | BIT_AC4_PKT_INFO_8821C(v))\n\n/* 2 REG_Q6_Q7_INFO_8821C */\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31)\n\n#define BIT_SHIFT_GTAB_ID_8821C 28\n#define BIT_MASK_GTAB_ID_8821C 0x7\n#define BIT_GTAB_ID_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C)\n#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C)\n#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C))\n#define BIT_GET_GTAB_ID_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C)\n#define BIT_SET_GTAB_ID_8821C(x, v)                                            \\\n\t(BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v))\n\n#define BIT_SHIFT_AC7_PKT_INFO_8821C 16\n#define BIT_MASK_AC7_PKT_INFO_8821C 0xfff\n#define BIT_AC7_PKT_INFO_8821C(x)                                              \\\n\t(((x) & BIT_MASK_AC7_PKT_INFO_8821C) << BIT_SHIFT_AC7_PKT_INFO_8821C)\n#define BITS_AC7_PKT_INFO_8821C                                                \\\n\t(BIT_MASK_AC7_PKT_INFO_8821C << BIT_SHIFT_AC7_PKT_INFO_8821C)\n#define BIT_CLEAR_AC7_PKT_INFO_8821C(x) ((x) & (~BITS_AC7_PKT_INFO_8821C))\n#define BIT_GET_AC7_PKT_INFO_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC7_PKT_INFO_8821C) & BIT_MASK_AC7_PKT_INFO_8821C)\n#define BIT_SET_AC7_PKT_INFO_8821C(x, v)                                       \\\n\t(BIT_CLEAR_AC7_PKT_INFO_8821C(x) | BIT_AC7_PKT_INFO_8821C(v))\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15)\n\n#define BIT_SHIFT_GTAB_ID_V1_8821C 12\n#define BIT_MASK_GTAB_ID_V1_8821C 0x7\n#define BIT_GTAB_ID_V1_8821C(x)                                                \\\n\t(((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C)\n#define BITS_GTAB_ID_V1_8821C                                                  \\\n\t(BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C)\n#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C))\n#define BIT_GET_GTAB_ID_V1_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C)\n#define BIT_SET_GTAB_ID_V1_8821C(x, v)                                         \\\n\t(BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v))\n\n#define BIT_SHIFT_AC6_PKT_INFO_8821C 0\n#define BIT_MASK_AC6_PKT_INFO_8821C 0xfff\n#define BIT_AC6_PKT_INFO_8821C(x)                                              \\\n\t(((x) & BIT_MASK_AC6_PKT_INFO_8821C) << BIT_SHIFT_AC6_PKT_INFO_8821C)\n#define BITS_AC6_PKT_INFO_8821C                                                \\\n\t(BIT_MASK_AC6_PKT_INFO_8821C << BIT_SHIFT_AC6_PKT_INFO_8821C)\n#define BIT_CLEAR_AC6_PKT_INFO_8821C(x) ((x) & (~BITS_AC6_PKT_INFO_8821C))\n#define BIT_GET_AC6_PKT_INFO_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC6_PKT_INFO_8821C) & BIT_MASK_AC6_PKT_INFO_8821C)\n#define BIT_SET_AC6_PKT_INFO_8821C(x, v)                                       \\\n\t(BIT_CLEAR_AC6_PKT_INFO_8821C(x) | BIT_AC6_PKT_INFO_8821C(v))\n\n/* 2 REG_MGQ_HIQ_INFO_8821C */\n\n#define BIT_SHIFT_HIQ_PKT_INFO_8821C 16\n#define BIT_MASK_HIQ_PKT_INFO_8821C 0xfff\n#define BIT_HIQ_PKT_INFO_8821C(x)                                              \\\n\t(((x) & BIT_MASK_HIQ_PKT_INFO_8821C) << BIT_SHIFT_HIQ_PKT_INFO_8821C)\n#define BITS_HIQ_PKT_INFO_8821C                                                \\\n\t(BIT_MASK_HIQ_PKT_INFO_8821C << BIT_SHIFT_HIQ_PKT_INFO_8821C)\n#define BIT_CLEAR_HIQ_PKT_INFO_8821C(x) ((x) & (~BITS_HIQ_PKT_INFO_8821C))\n#define BIT_GET_HIQ_PKT_INFO_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_HIQ_PKT_INFO_8821C) & BIT_MASK_HIQ_PKT_INFO_8821C)\n#define BIT_SET_HIQ_PKT_INFO_8821C(x, v)                                       \\\n\t(BIT_CLEAR_HIQ_PKT_INFO_8821C(x) | BIT_HIQ_PKT_INFO_8821C(v))\n\n#define BIT_SHIFT_MGQ_PKT_INFO_8821C 0\n#define BIT_MASK_MGQ_PKT_INFO_8821C 0xfff\n#define BIT_MGQ_PKT_INFO_8821C(x)                                              \\\n\t(((x) & BIT_MASK_MGQ_PKT_INFO_8821C) << BIT_SHIFT_MGQ_PKT_INFO_8821C)\n#define BITS_MGQ_PKT_INFO_8821C                                                \\\n\t(BIT_MASK_MGQ_PKT_INFO_8821C << BIT_SHIFT_MGQ_PKT_INFO_8821C)\n#define BIT_CLEAR_MGQ_PKT_INFO_8821C(x) ((x) & (~BITS_MGQ_PKT_INFO_8821C))\n#define BIT_GET_MGQ_PKT_INFO_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_MGQ_PKT_INFO_8821C) & BIT_MASK_MGQ_PKT_INFO_8821C)\n#define BIT_SET_MGQ_PKT_INFO_8821C(x, v)                                       \\\n\t(BIT_CLEAR_MGQ_PKT_INFO_8821C(x) | BIT_MGQ_PKT_INFO_8821C(v))\n\n/* 2 REG_CMDQ_BCNQ_INFO_8821C */\n\n#define BIT_SHIFT_CMDQ_PKT_INFO_8821C 16\n#define BIT_MASK_CMDQ_PKT_INFO_8821C 0xfff\n#define BIT_CMDQ_PKT_INFO_8821C(x)                                             \\\n\t(((x) & BIT_MASK_CMDQ_PKT_INFO_8821C) << BIT_SHIFT_CMDQ_PKT_INFO_8821C)\n#define BITS_CMDQ_PKT_INFO_8821C                                               \\\n\t(BIT_MASK_CMDQ_PKT_INFO_8821C << BIT_SHIFT_CMDQ_PKT_INFO_8821C)\n#define BIT_CLEAR_CMDQ_PKT_INFO_8821C(x) ((x) & (~BITS_CMDQ_PKT_INFO_8821C))\n#define BIT_GET_CMDQ_PKT_INFO_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8821C) & BIT_MASK_CMDQ_PKT_INFO_8821C)\n#define BIT_SET_CMDQ_PKT_INFO_8821C(x, v)                                      \\\n\t(BIT_CLEAR_CMDQ_PKT_INFO_8821C(x) | BIT_CMDQ_PKT_INFO_8821C(v))\n\n#define BIT_SHIFT_BCNQ_PKT_INFO_8821C 0\n#define BIT_MASK_BCNQ_PKT_INFO_8821C 0xfff\n#define BIT_BCNQ_PKT_INFO_8821C(x)                                             \\\n\t(((x) & BIT_MASK_BCNQ_PKT_INFO_8821C) << BIT_SHIFT_BCNQ_PKT_INFO_8821C)\n#define BITS_BCNQ_PKT_INFO_8821C                                               \\\n\t(BIT_MASK_BCNQ_PKT_INFO_8821C << BIT_SHIFT_BCNQ_PKT_INFO_8821C)\n#define BIT_CLEAR_BCNQ_PKT_INFO_8821C(x) ((x) & (~BITS_BCNQ_PKT_INFO_8821C))\n#define BIT_GET_BCNQ_PKT_INFO_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8821C) & BIT_MASK_BCNQ_PKT_INFO_8821C)\n#define BIT_SET_BCNQ_PKT_INFO_8821C(x, v)                                      \\\n\t(BIT_CLEAR_BCNQ_PKT_INFO_8821C(x) | BIT_BCNQ_PKT_INFO_8821C(v))\n\n/* 2 REG_USEREG_SETTING_8821C */\n#define BIT_NDPA_USEREG_8821C BIT(21)\n\n#define BIT_SHIFT_RETRY_USEREG_8821C 19\n#define BIT_MASK_RETRY_USEREG_8821C 0x3\n#define BIT_RETRY_USEREG_8821C(x)                                              \\\n\t(((x) & BIT_MASK_RETRY_USEREG_8821C) << BIT_SHIFT_RETRY_USEREG_8821C)\n#define BITS_RETRY_USEREG_8821C                                                \\\n\t(BIT_MASK_RETRY_USEREG_8821C << BIT_SHIFT_RETRY_USEREG_8821C)\n#define BIT_CLEAR_RETRY_USEREG_8821C(x) ((x) & (~BITS_RETRY_USEREG_8821C))\n#define BIT_GET_RETRY_USEREG_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RETRY_USEREG_8821C) & BIT_MASK_RETRY_USEREG_8821C)\n#define BIT_SET_RETRY_USEREG_8821C(x, v)                                       \\\n\t(BIT_CLEAR_RETRY_USEREG_8821C(x) | BIT_RETRY_USEREG_8821C(v))\n\n#define BIT_SHIFT_TRYPKT_USEREG_8821C 17\n#define BIT_MASK_TRYPKT_USEREG_8821C 0x3\n#define BIT_TRYPKT_USEREG_8821C(x)                                             \\\n\t(((x) & BIT_MASK_TRYPKT_USEREG_8821C) << BIT_SHIFT_TRYPKT_USEREG_8821C)\n#define BITS_TRYPKT_USEREG_8821C                                               \\\n\t(BIT_MASK_TRYPKT_USEREG_8821C << BIT_SHIFT_TRYPKT_USEREG_8821C)\n#define BIT_CLEAR_TRYPKT_USEREG_8821C(x) ((x) & (~BITS_TRYPKT_USEREG_8821C))\n#define BIT_GET_TRYPKT_USEREG_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TRYPKT_USEREG_8821C) & BIT_MASK_TRYPKT_USEREG_8821C)\n#define BIT_SET_TRYPKT_USEREG_8821C(x, v)                                      \\\n\t(BIT_CLEAR_TRYPKT_USEREG_8821C(x) | BIT_TRYPKT_USEREG_8821C(v))\n\n#define BIT_CTLPKT_USEREG_8821C BIT(16)\n\n/* 2 REG_AESIV_SETTING_8821C */\n\n#define BIT_SHIFT_AESIV_OFFSET_8821C 0\n#define BIT_MASK_AESIV_OFFSET_8821C 0xfff\n#define BIT_AESIV_OFFSET_8821C(x)                                              \\\n\t(((x) & BIT_MASK_AESIV_OFFSET_8821C) << BIT_SHIFT_AESIV_OFFSET_8821C)\n#define BITS_AESIV_OFFSET_8821C                                                \\\n\t(BIT_MASK_AESIV_OFFSET_8821C << BIT_SHIFT_AESIV_OFFSET_8821C)\n#define BIT_CLEAR_AESIV_OFFSET_8821C(x) ((x) & (~BITS_AESIV_OFFSET_8821C))\n#define BIT_GET_AESIV_OFFSET_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AESIV_OFFSET_8821C) & BIT_MASK_AESIV_OFFSET_8821C)\n#define BIT_SET_AESIV_OFFSET_8821C(x, v)                                       \\\n\t(BIT_CLEAR_AESIV_OFFSET_8821C(x) | BIT_AESIV_OFFSET_8821C(v))\n\n/* 2 REG_BF0_TIME_SETTING_8821C */\n#define BIT_BF0_TIMER_SET_8821C BIT(31)\n#define BIT_BF0_TIMER_CLR_8821C BIT(30)\n#define BIT_BF0_UPDATE_EN_8821C BIT(29)\n#define BIT_BF0_TIMER_EN_8821C BIT(28)\n\n#define BIT_SHIFT_BF0_PRETIME_OVER_8821C 16\n#define BIT_MASK_BF0_PRETIME_OVER_8821C 0xfff\n#define BIT_BF0_PRETIME_OVER_8821C(x)                                          \\\n\t(((x) & BIT_MASK_BF0_PRETIME_OVER_8821C)                               \\\n\t << BIT_SHIFT_BF0_PRETIME_OVER_8821C)\n#define BITS_BF0_PRETIME_OVER_8821C                                            \\\n\t(BIT_MASK_BF0_PRETIME_OVER_8821C << BIT_SHIFT_BF0_PRETIME_OVER_8821C)\n#define BIT_CLEAR_BF0_PRETIME_OVER_8821C(x)                                    \\\n\t((x) & (~BITS_BF0_PRETIME_OVER_8821C))\n#define BIT_GET_BF0_PRETIME_OVER_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8821C) &                           \\\n\t BIT_MASK_BF0_PRETIME_OVER_8821C)\n#define BIT_SET_BF0_PRETIME_OVER_8821C(x, v)                                   \\\n\t(BIT_CLEAR_BF0_PRETIME_OVER_8821C(x) | BIT_BF0_PRETIME_OVER_8821C(v))\n\n#define BIT_SHIFT_BF0_LIFETIME_8821C 0\n#define BIT_MASK_BF0_LIFETIME_8821C 0xffff\n#define BIT_BF0_LIFETIME_8821C(x)                                              \\\n\t(((x) & BIT_MASK_BF0_LIFETIME_8821C) << BIT_SHIFT_BF0_LIFETIME_8821C)\n#define BITS_BF0_LIFETIME_8821C                                                \\\n\t(BIT_MASK_BF0_LIFETIME_8821C << BIT_SHIFT_BF0_LIFETIME_8821C)\n#define BIT_CLEAR_BF0_LIFETIME_8821C(x) ((x) & (~BITS_BF0_LIFETIME_8821C))\n#define BIT_GET_BF0_LIFETIME_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BF0_LIFETIME_8821C) & BIT_MASK_BF0_LIFETIME_8821C)\n#define BIT_SET_BF0_LIFETIME_8821C(x, v)                                       \\\n\t(BIT_CLEAR_BF0_LIFETIME_8821C(x) | BIT_BF0_LIFETIME_8821C(v))\n\n/* 2 REG_BF1_TIME_SETTING_8821C */\n#define BIT_BF1_TIMER_SET_8821C BIT(31)\n#define BIT_BF1_TIMER_CLR_8821C BIT(30)\n#define BIT_BF1_UPDATE_EN_8821C BIT(29)\n#define BIT_BF1_TIMER_EN_8821C BIT(28)\n\n#define BIT_SHIFT_BF1_PRETIME_OVER_8821C 16\n#define BIT_MASK_BF1_PRETIME_OVER_8821C 0xfff\n#define BIT_BF1_PRETIME_OVER_8821C(x)                                          \\\n\t(((x) & BIT_MASK_BF1_PRETIME_OVER_8821C)                               \\\n\t << BIT_SHIFT_BF1_PRETIME_OVER_8821C)\n#define BITS_BF1_PRETIME_OVER_8821C                                            \\\n\t(BIT_MASK_BF1_PRETIME_OVER_8821C << BIT_SHIFT_BF1_PRETIME_OVER_8821C)\n#define BIT_CLEAR_BF1_PRETIME_OVER_8821C(x)                                    \\\n\t((x) & (~BITS_BF1_PRETIME_OVER_8821C))\n#define BIT_GET_BF1_PRETIME_OVER_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8821C) &                           \\\n\t BIT_MASK_BF1_PRETIME_OVER_8821C)\n#define BIT_SET_BF1_PRETIME_OVER_8821C(x, v)                                   \\\n\t(BIT_CLEAR_BF1_PRETIME_OVER_8821C(x) | BIT_BF1_PRETIME_OVER_8821C(v))\n\n#define BIT_SHIFT_BF1_LIFETIME_8821C 0\n#define BIT_MASK_BF1_LIFETIME_8821C 0xffff\n#define BIT_BF1_LIFETIME_8821C(x)                                              \\\n\t(((x) & BIT_MASK_BF1_LIFETIME_8821C) << BIT_SHIFT_BF1_LIFETIME_8821C)\n#define BITS_BF1_LIFETIME_8821C                                                \\\n\t(BIT_MASK_BF1_LIFETIME_8821C << BIT_SHIFT_BF1_LIFETIME_8821C)\n#define BIT_CLEAR_BF1_LIFETIME_8821C(x) ((x) & (~BITS_BF1_LIFETIME_8821C))\n#define BIT_GET_BF1_LIFETIME_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BF1_LIFETIME_8821C) & BIT_MASK_BF1_LIFETIME_8821C)\n#define BIT_SET_BF1_LIFETIME_8821C(x, v)                                       \\\n\t(BIT_CLEAR_BF1_LIFETIME_8821C(x) | BIT_BF1_LIFETIME_8821C(v))\n\n/* 2 REG_BF_TIMEOUT_EN_8821C */\n#define BIT_EN_VHT_LDPC_8821C BIT(9)\n#define BIT_EN_HT_LDPC_8821C BIT(8)\n#define BIT_BF1_TIMEOUT_EN_8821C BIT(1)\n#define BIT_BF0_TIMEOUT_EN_8821C BIT(0)\n\n/* 2 REG_MACID_RELEASE0_8821C */\n\n#define BIT_SHIFT_MACID31_0_RELEASE_8821C 0\n#define BIT_MASK_MACID31_0_RELEASE_8821C 0xffffffffL\n#define BIT_MACID31_0_RELEASE_8821C(x)                                         \\\n\t(((x) & BIT_MASK_MACID31_0_RELEASE_8821C)                              \\\n\t << BIT_SHIFT_MACID31_0_RELEASE_8821C)\n#define BITS_MACID31_0_RELEASE_8821C                                           \\\n\t(BIT_MASK_MACID31_0_RELEASE_8821C << BIT_SHIFT_MACID31_0_RELEASE_8821C)\n#define BIT_CLEAR_MACID31_0_RELEASE_8821C(x)                                   \\\n\t((x) & (~BITS_MACID31_0_RELEASE_8821C))\n#define BIT_GET_MACID31_0_RELEASE_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_MACID31_0_RELEASE_8821C) &                          \\\n\t BIT_MASK_MACID31_0_RELEASE_8821C)\n#define BIT_SET_MACID31_0_RELEASE_8821C(x, v)                                  \\\n\t(BIT_CLEAR_MACID31_0_RELEASE_8821C(x) | BIT_MACID31_0_RELEASE_8821C(v))\n\n/* 2 REG_MACID_RELEASE1_8821C */\n\n#define BIT_SHIFT_MACID63_32_RELEASE_8821C 0\n#define BIT_MASK_MACID63_32_RELEASE_8821C 0xffffffffL\n#define BIT_MACID63_32_RELEASE_8821C(x)                                        \\\n\t(((x) & BIT_MASK_MACID63_32_RELEASE_8821C)                             \\\n\t << BIT_SHIFT_MACID63_32_RELEASE_8821C)\n#define BITS_MACID63_32_RELEASE_8821C                                          \\\n\t(BIT_MASK_MACID63_32_RELEASE_8821C                                     \\\n\t << BIT_SHIFT_MACID63_32_RELEASE_8821C)\n#define BIT_CLEAR_MACID63_32_RELEASE_8821C(x)                                  \\\n\t((x) & (~BITS_MACID63_32_RELEASE_8821C))\n#define BIT_GET_MACID63_32_RELEASE_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACID63_32_RELEASE_8821C) &                         \\\n\t BIT_MASK_MACID63_32_RELEASE_8821C)\n#define BIT_SET_MACID63_32_RELEASE_8821C(x, v)                                 \\\n\t(BIT_CLEAR_MACID63_32_RELEASE_8821C(x) |                               \\\n\t BIT_MACID63_32_RELEASE_8821C(v))\n\n/* 2 REG_MACID_RELEASE2_8821C */\n\n#define BIT_SHIFT_MACID95_64_RELEASE_8821C 0\n#define BIT_MASK_MACID95_64_RELEASE_8821C 0xffffffffL\n#define BIT_MACID95_64_RELEASE_8821C(x)                                        \\\n\t(((x) & BIT_MASK_MACID95_64_RELEASE_8821C)                             \\\n\t << BIT_SHIFT_MACID95_64_RELEASE_8821C)\n#define BITS_MACID95_64_RELEASE_8821C                                          \\\n\t(BIT_MASK_MACID95_64_RELEASE_8821C                                     \\\n\t << BIT_SHIFT_MACID95_64_RELEASE_8821C)\n#define BIT_CLEAR_MACID95_64_RELEASE_8821C(x)                                  \\\n\t((x) & (~BITS_MACID95_64_RELEASE_8821C))\n#define BIT_GET_MACID95_64_RELEASE_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACID95_64_RELEASE_8821C) &                         \\\n\t BIT_MASK_MACID95_64_RELEASE_8821C)\n#define BIT_SET_MACID95_64_RELEASE_8821C(x, v)                                 \\\n\t(BIT_CLEAR_MACID95_64_RELEASE_8821C(x) |                               \\\n\t BIT_MACID95_64_RELEASE_8821C(v))\n\n/* 2 REG_MACID_RELEASE3_8821C */\n\n#define BIT_SHIFT_MACID127_96_RELEASE_8821C 0\n#define BIT_MASK_MACID127_96_RELEASE_8821C 0xffffffffL\n#define BIT_MACID127_96_RELEASE_8821C(x)                                       \\\n\t(((x) & BIT_MASK_MACID127_96_RELEASE_8821C)                            \\\n\t << BIT_SHIFT_MACID127_96_RELEASE_8821C)\n#define BITS_MACID127_96_RELEASE_8821C                                         \\\n\t(BIT_MASK_MACID127_96_RELEASE_8821C                                    \\\n\t << BIT_SHIFT_MACID127_96_RELEASE_8821C)\n#define BIT_CLEAR_MACID127_96_RELEASE_8821C(x)                                 \\\n\t((x) & (~BITS_MACID127_96_RELEASE_8821C))\n#define BIT_GET_MACID127_96_RELEASE_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_MACID127_96_RELEASE_8821C) &                        \\\n\t BIT_MASK_MACID127_96_RELEASE_8821C)\n#define BIT_SET_MACID127_96_RELEASE_8821C(x, v)                                \\\n\t(BIT_CLEAR_MACID127_96_RELEASE_8821C(x) |                              \\\n\t BIT_MACID127_96_RELEASE_8821C(v))\n\n/* 2 REG_MACID_RELEASE_SETTING_8821C */\n#define BIT_MACID_VALUE_8821C BIT(7)\n\n#define BIT_SHIFT_MACID_OFFSET_8821C 0\n#define BIT_MASK_MACID_OFFSET_8821C 0x7f\n#define BIT_MACID_OFFSET_8821C(x)                                              \\\n\t(((x) & BIT_MASK_MACID_OFFSET_8821C) << BIT_SHIFT_MACID_OFFSET_8821C)\n#define BITS_MACID_OFFSET_8821C                                                \\\n\t(BIT_MASK_MACID_OFFSET_8821C << BIT_SHIFT_MACID_OFFSET_8821C)\n#define BIT_CLEAR_MACID_OFFSET_8821C(x) ((x) & (~BITS_MACID_OFFSET_8821C))\n#define BIT_GET_MACID_OFFSET_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_MACID_OFFSET_8821C) & BIT_MASK_MACID_OFFSET_8821C)\n#define BIT_SET_MACID_OFFSET_8821C(x, v)                                       \\\n\t(BIT_CLEAR_MACID_OFFSET_8821C(x) | BIT_MACID_OFFSET_8821C(v))\n\n/* 2 REG_FAST_EDCA_VOVI_SETTING_8821C */\n\n#define BIT_SHIFT_VI_FAST_EDCA_TO_8821C 24\n#define BIT_MASK_VI_FAST_EDCA_TO_8821C 0xff\n#define BIT_VI_FAST_EDCA_TO_8821C(x)                                           \\\n\t(((x) & BIT_MASK_VI_FAST_EDCA_TO_8821C)                                \\\n\t << BIT_SHIFT_VI_FAST_EDCA_TO_8821C)\n#define BITS_VI_FAST_EDCA_TO_8821C                                             \\\n\t(BIT_MASK_VI_FAST_EDCA_TO_8821C << BIT_SHIFT_VI_FAST_EDCA_TO_8821C)\n#define BIT_CLEAR_VI_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8821C))\n#define BIT_GET_VI_FAST_EDCA_TO_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8821C) &                            \\\n\t BIT_MASK_VI_FAST_EDCA_TO_8821C)\n#define BIT_SET_VI_FAST_EDCA_TO_8821C(x, v)                                    \\\n\t(BIT_CLEAR_VI_FAST_EDCA_TO_8821C(x) | BIT_VI_FAST_EDCA_TO_8821C(v))\n\n#define BIT_VI_THRESHOLD_SEL_8821C BIT(23)\n\n#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C 16\n#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C 0x7f\n#define BIT_VI_FAST_EDCA_PKT_TH_8821C(x)                                       \\\n\t(((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C)                            \\\n\t << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C)\n#define BITS_VI_FAST_EDCA_PKT_TH_8821C                                         \\\n\t(BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C                                    \\\n\t << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C)\n#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8821C(x)                                 \\\n\t((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8821C))\n#define BIT_GET_VI_FAST_EDCA_PKT_TH_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C) &                        \\\n\t BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C)\n#define BIT_SET_VI_FAST_EDCA_PKT_TH_8821C(x, v)                                \\\n\t(BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8821C(x) |                              \\\n\t BIT_VI_FAST_EDCA_PKT_TH_8821C(v))\n\n#define BIT_SHIFT_VO_FAST_EDCA_TO_8821C 8\n#define BIT_MASK_VO_FAST_EDCA_TO_8821C 0xff\n#define BIT_VO_FAST_EDCA_TO_8821C(x)                                           \\\n\t(((x) & BIT_MASK_VO_FAST_EDCA_TO_8821C)                                \\\n\t << BIT_SHIFT_VO_FAST_EDCA_TO_8821C)\n#define BITS_VO_FAST_EDCA_TO_8821C                                             \\\n\t(BIT_MASK_VO_FAST_EDCA_TO_8821C << BIT_SHIFT_VO_FAST_EDCA_TO_8821C)\n#define BIT_CLEAR_VO_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8821C))\n#define BIT_GET_VO_FAST_EDCA_TO_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8821C) &                            \\\n\t BIT_MASK_VO_FAST_EDCA_TO_8821C)\n#define BIT_SET_VO_FAST_EDCA_TO_8821C(x, v)                                    \\\n\t(BIT_CLEAR_VO_FAST_EDCA_TO_8821C(x) | BIT_VO_FAST_EDCA_TO_8821C(v))\n\n#define BIT_VO_THRESHOLD_SEL_8821C BIT(7)\n\n#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C 0\n#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C 0x7f\n#define BIT_VO_FAST_EDCA_PKT_TH_8821C(x)                                       \\\n\t(((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C)                            \\\n\t << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C)\n#define BITS_VO_FAST_EDCA_PKT_TH_8821C                                         \\\n\t(BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C                                    \\\n\t << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C)\n#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8821C(x)                                 \\\n\t((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8821C))\n#define BIT_GET_VO_FAST_EDCA_PKT_TH_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C) &                        \\\n\t BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C)\n#define BIT_SET_VO_FAST_EDCA_PKT_TH_8821C(x, v)                                \\\n\t(BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8821C(x) |                              \\\n\t BIT_VO_FAST_EDCA_PKT_TH_8821C(v))\n\n/* 2 REG_FAST_EDCA_BEBK_SETTING_8821C */\n\n#define BIT_SHIFT_BK_FAST_EDCA_TO_8821C 24\n#define BIT_MASK_BK_FAST_EDCA_TO_8821C 0xff\n#define BIT_BK_FAST_EDCA_TO_8821C(x)                                           \\\n\t(((x) & BIT_MASK_BK_FAST_EDCA_TO_8821C)                                \\\n\t << BIT_SHIFT_BK_FAST_EDCA_TO_8821C)\n#define BITS_BK_FAST_EDCA_TO_8821C                                             \\\n\t(BIT_MASK_BK_FAST_EDCA_TO_8821C << BIT_SHIFT_BK_FAST_EDCA_TO_8821C)\n#define BIT_CLEAR_BK_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8821C))\n#define BIT_GET_BK_FAST_EDCA_TO_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8821C) &                            \\\n\t BIT_MASK_BK_FAST_EDCA_TO_8821C)\n#define BIT_SET_BK_FAST_EDCA_TO_8821C(x, v)                                    \\\n\t(BIT_CLEAR_BK_FAST_EDCA_TO_8821C(x) | BIT_BK_FAST_EDCA_TO_8821C(v))\n\n#define BIT_BK_THRESHOLD_SEL_8821C BIT(23)\n\n#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C 16\n#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C 0x7f\n#define BIT_BK_FAST_EDCA_PKT_TH_8821C(x)                                       \\\n\t(((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C)                            \\\n\t << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C)\n#define BITS_BK_FAST_EDCA_PKT_TH_8821C                                         \\\n\t(BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C                                    \\\n\t << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C)\n#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8821C(x)                                 \\\n\t((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8821C))\n#define BIT_GET_BK_FAST_EDCA_PKT_TH_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C) &                        \\\n\t BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C)\n#define BIT_SET_BK_FAST_EDCA_PKT_TH_8821C(x, v)                                \\\n\t(BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8821C(x) |                              \\\n\t BIT_BK_FAST_EDCA_PKT_TH_8821C(v))\n\n#define BIT_SHIFT_BE_FAST_EDCA_TO_8821C 8\n#define BIT_MASK_BE_FAST_EDCA_TO_8821C 0xff\n#define BIT_BE_FAST_EDCA_TO_8821C(x)                                           \\\n\t(((x) & BIT_MASK_BE_FAST_EDCA_TO_8821C)                                \\\n\t << BIT_SHIFT_BE_FAST_EDCA_TO_8821C)\n#define BITS_BE_FAST_EDCA_TO_8821C                                             \\\n\t(BIT_MASK_BE_FAST_EDCA_TO_8821C << BIT_SHIFT_BE_FAST_EDCA_TO_8821C)\n#define BIT_CLEAR_BE_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8821C))\n#define BIT_GET_BE_FAST_EDCA_TO_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8821C) &                            \\\n\t BIT_MASK_BE_FAST_EDCA_TO_8821C)\n#define BIT_SET_BE_FAST_EDCA_TO_8821C(x, v)                                    \\\n\t(BIT_CLEAR_BE_FAST_EDCA_TO_8821C(x) | BIT_BE_FAST_EDCA_TO_8821C(v))\n\n#define BIT_BE_THRESHOLD_SEL_8821C BIT(7)\n\n#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C 0\n#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C 0x7f\n#define BIT_BE_FAST_EDCA_PKT_TH_8821C(x)                                       \\\n\t(((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C)                            \\\n\t << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C)\n#define BITS_BE_FAST_EDCA_PKT_TH_8821C                                         \\\n\t(BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C                                    \\\n\t << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C)\n#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8821C(x)                                 \\\n\t((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8821C))\n#define BIT_GET_BE_FAST_EDCA_PKT_TH_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C) &                        \\\n\t BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C)\n#define BIT_SET_BE_FAST_EDCA_PKT_TH_8821C(x, v)                                \\\n\t(BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8821C(x) |                              \\\n\t BIT_BE_FAST_EDCA_PKT_TH_8821C(v))\n\n/* 2 REG_MACID_DROP0_8821C */\n\n#define BIT_SHIFT_MACID31_0_DROP_8821C 0\n#define BIT_MASK_MACID31_0_DROP_8821C 0xffffffffL\n#define BIT_MACID31_0_DROP_8821C(x)                                            \\\n\t(((x) & BIT_MASK_MACID31_0_DROP_8821C)                                 \\\n\t << BIT_SHIFT_MACID31_0_DROP_8821C)\n#define BITS_MACID31_0_DROP_8821C                                              \\\n\t(BIT_MASK_MACID31_0_DROP_8821C << BIT_SHIFT_MACID31_0_DROP_8821C)\n#define BIT_CLEAR_MACID31_0_DROP_8821C(x) ((x) & (~BITS_MACID31_0_DROP_8821C))\n#define BIT_GET_MACID31_0_DROP_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_MACID31_0_DROP_8821C) &                             \\\n\t BIT_MASK_MACID31_0_DROP_8821C)\n#define BIT_SET_MACID31_0_DROP_8821C(x, v)                                     \\\n\t(BIT_CLEAR_MACID31_0_DROP_8821C(x) | BIT_MACID31_0_DROP_8821C(v))\n\n/* 2 REG_MACID_DROP1_8821C */\n\n#define BIT_SHIFT_MACID63_32_DROP_8821C 0\n#define BIT_MASK_MACID63_32_DROP_8821C 0xffffffffL\n#define BIT_MACID63_32_DROP_8821C(x)                                           \\\n\t(((x) & BIT_MASK_MACID63_32_DROP_8821C)                                \\\n\t << BIT_SHIFT_MACID63_32_DROP_8821C)\n#define BITS_MACID63_32_DROP_8821C                                             \\\n\t(BIT_MASK_MACID63_32_DROP_8821C << BIT_SHIFT_MACID63_32_DROP_8821C)\n#define BIT_CLEAR_MACID63_32_DROP_8821C(x) ((x) & (~BITS_MACID63_32_DROP_8821C))\n#define BIT_GET_MACID63_32_DROP_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_MACID63_32_DROP_8821C) &                            \\\n\t BIT_MASK_MACID63_32_DROP_8821C)\n#define BIT_SET_MACID63_32_DROP_8821C(x, v)                                    \\\n\t(BIT_CLEAR_MACID63_32_DROP_8821C(x) | BIT_MACID63_32_DROP_8821C(v))\n\n/* 2 REG_MACID_DROP2_8821C */\n\n#define BIT_SHIFT_MACID95_64_DROP_8821C 0\n#define BIT_MASK_MACID95_64_DROP_8821C 0xffffffffL\n#define BIT_MACID95_64_DROP_8821C(x)                                           \\\n\t(((x) & BIT_MASK_MACID95_64_DROP_8821C)                                \\\n\t << BIT_SHIFT_MACID95_64_DROP_8821C)\n#define BITS_MACID95_64_DROP_8821C                                             \\\n\t(BIT_MASK_MACID95_64_DROP_8821C << BIT_SHIFT_MACID95_64_DROP_8821C)\n#define BIT_CLEAR_MACID95_64_DROP_8821C(x) ((x) & (~BITS_MACID95_64_DROP_8821C))\n#define BIT_GET_MACID95_64_DROP_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_MACID95_64_DROP_8821C) &                            \\\n\t BIT_MASK_MACID95_64_DROP_8821C)\n#define BIT_SET_MACID95_64_DROP_8821C(x, v)                                    \\\n\t(BIT_CLEAR_MACID95_64_DROP_8821C(x) | BIT_MACID95_64_DROP_8821C(v))\n\n/* 2 REG_MACID_DROP3_8821C */\n\n#define BIT_SHIFT_MACID127_96_DROP_8821C 0\n#define BIT_MASK_MACID127_96_DROP_8821C 0xffffffffL\n#define BIT_MACID127_96_DROP_8821C(x)                                          \\\n\t(((x) & BIT_MASK_MACID127_96_DROP_8821C)                               \\\n\t << BIT_SHIFT_MACID127_96_DROP_8821C)\n#define BITS_MACID127_96_DROP_8821C                                            \\\n\t(BIT_MASK_MACID127_96_DROP_8821C << BIT_SHIFT_MACID127_96_DROP_8821C)\n#define BIT_CLEAR_MACID127_96_DROP_8821C(x)                                    \\\n\t((x) & (~BITS_MACID127_96_DROP_8821C))\n#define BIT_GET_MACID127_96_DROP_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_MACID127_96_DROP_8821C) &                           \\\n\t BIT_MASK_MACID127_96_DROP_8821C)\n#define BIT_SET_MACID127_96_DROP_8821C(x, v)                                   \\\n\t(BIT_CLEAR_MACID127_96_DROP_8821C(x) | BIT_MACID127_96_DROP_8821C(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8821C */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_0_8821C(x)                                 \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C)                      \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C)\n#define BITS_R_MACID_RELEASE_SUCCESS_0_8821C                                   \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C                              \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8821C(x)                           \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8821C))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8821C(x)                             \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C) &                  \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8821C(x, v)                          \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8821C(x) |                        \\\n\t BIT_R_MACID_RELEASE_SUCCESS_0_8821C(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8821C */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_1_8821C(x)                                 \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C)                      \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C)\n#define BITS_R_MACID_RELEASE_SUCCESS_1_8821C                                   \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C                              \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8821C(x)                           \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8821C))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8821C(x)                             \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C) &                  \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8821C(x, v)                          \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8821C(x) |                        \\\n\t BIT_R_MACID_RELEASE_SUCCESS_1_8821C(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8821C */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_2_8821C(x)                                 \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C)                      \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C)\n#define BITS_R_MACID_RELEASE_SUCCESS_2_8821C                                   \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C                              \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8821C(x)                           \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8821C))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8821C(x)                             \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C) &                  \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8821C(x, v)                          \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8821C(x) |                        \\\n\t BIT_R_MACID_RELEASE_SUCCESS_2_8821C(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8821C */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_3_8821C(x)                                 \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C)                      \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C)\n#define BITS_R_MACID_RELEASE_SUCCESS_3_8821C                                   \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C                              \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8821C(x)                           \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8821C))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8821C(x)                             \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C) &                  \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8821C(x, v)                          \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8821C(x) |                        \\\n\t BIT_R_MACID_RELEASE_SUCCESS_3_8821C(v))\n\n/* 2 REG_MGQ_FIFO_WRITE_POINTER_8821C */\n#define BIT_MGQ_FIFO_OV_8821C BIT(7)\n#define BIT_MGQ_FIFO_WPTR_ERROR_8821C BIT(6)\n#define BIT_EN_MGQ_FIFO_LIFETIME_8821C BIT(5)\n\n#define BIT_SHIFT_MGQ_FIFO_WPTR_8821C 0\n#define BIT_MASK_MGQ_FIFO_WPTR_8821C 0x1f\n#define BIT_MGQ_FIFO_WPTR_8821C(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_FIFO_WPTR_8821C) << BIT_SHIFT_MGQ_FIFO_WPTR_8821C)\n#define BITS_MGQ_FIFO_WPTR_8821C                                               \\\n\t(BIT_MASK_MGQ_FIFO_WPTR_8821C << BIT_SHIFT_MGQ_FIFO_WPTR_8821C)\n#define BIT_CLEAR_MGQ_FIFO_WPTR_8821C(x) ((x) & (~BITS_MGQ_FIFO_WPTR_8821C))\n#define BIT_GET_MGQ_FIFO_WPTR_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_WPTR_8821C) & BIT_MASK_MGQ_FIFO_WPTR_8821C)\n#define BIT_SET_MGQ_FIFO_WPTR_8821C(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_FIFO_WPTR_8821C(x) | BIT_MGQ_FIFO_WPTR_8821C(v))\n\n/* 2 REG_MGQ_FIFO_READ_POINTER_8821C */\n\n#define BIT_SHIFT_MGQ_FIFO_SIZE_8821C 14\n#define BIT_MASK_MGQ_FIFO_SIZE_8821C 0x3\n#define BIT_MGQ_FIFO_SIZE_8821C(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_FIFO_SIZE_8821C) << BIT_SHIFT_MGQ_FIFO_SIZE_8821C)\n#define BITS_MGQ_FIFO_SIZE_8821C                                               \\\n\t(BIT_MASK_MGQ_FIFO_SIZE_8821C << BIT_SHIFT_MGQ_FIFO_SIZE_8821C)\n#define BIT_CLEAR_MGQ_FIFO_SIZE_8821C(x) ((x) & (~BITS_MGQ_FIFO_SIZE_8821C))\n#define BIT_GET_MGQ_FIFO_SIZE_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_SIZE_8821C) & BIT_MASK_MGQ_FIFO_SIZE_8821C)\n#define BIT_SET_MGQ_FIFO_SIZE_8821C(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_FIFO_SIZE_8821C(x) | BIT_MGQ_FIFO_SIZE_8821C(v))\n\n#define BIT_MGQ_FIFO_PAUSE_8821C BIT(13)\n\n#define BIT_SHIFT_MGQ_FIFO_RPTR_8821C 8\n#define BIT_MASK_MGQ_FIFO_RPTR_8821C 0x1f\n#define BIT_MGQ_FIFO_RPTR_8821C(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_FIFO_RPTR_8821C) << BIT_SHIFT_MGQ_FIFO_RPTR_8821C)\n#define BITS_MGQ_FIFO_RPTR_8821C                                               \\\n\t(BIT_MASK_MGQ_FIFO_RPTR_8821C << BIT_SHIFT_MGQ_FIFO_RPTR_8821C)\n#define BIT_CLEAR_MGQ_FIFO_RPTR_8821C(x) ((x) & (~BITS_MGQ_FIFO_RPTR_8821C))\n#define BIT_GET_MGQ_FIFO_RPTR_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_RPTR_8821C) & BIT_MASK_MGQ_FIFO_RPTR_8821C)\n#define BIT_SET_MGQ_FIFO_RPTR_8821C(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_FIFO_RPTR_8821C(x) | BIT_MGQ_FIFO_RPTR_8821C(v))\n\n/* 2 REG_MGQ_FIFO_ENABLE_8821C */\n#define BIT_MGQ_FIFO_EN_8821C BIT(15)\n\n#define BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C 12\n#define BIT_MASK_MGQ_FIFO_PG_SIZE_8821C 0x7\n#define BIT_MGQ_FIFO_PG_SIZE_8821C(x)                                          \\\n\t(((x) & BIT_MASK_MGQ_FIFO_PG_SIZE_8821C)                               \\\n\t << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C)\n#define BITS_MGQ_FIFO_PG_SIZE_8821C                                            \\\n\t(BIT_MASK_MGQ_FIFO_PG_SIZE_8821C << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C)\n#define BIT_CLEAR_MGQ_FIFO_PG_SIZE_8821C(x)                                    \\\n\t((x) & (~BITS_MGQ_FIFO_PG_SIZE_8821C))\n#define BIT_GET_MGQ_FIFO_PG_SIZE_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C) &                           \\\n\t BIT_MASK_MGQ_FIFO_PG_SIZE_8821C)\n#define BIT_SET_MGQ_FIFO_PG_SIZE_8821C(x, v)                                   \\\n\t(BIT_CLEAR_MGQ_FIFO_PG_SIZE_8821C(x) | BIT_MGQ_FIFO_PG_SIZE_8821C(v))\n\n#define BIT_SHIFT_MGQ_FIFO_START_PG_8821C 0\n#define BIT_MASK_MGQ_FIFO_START_PG_8821C 0xfff\n#define BIT_MGQ_FIFO_START_PG_8821C(x)                                         \\\n\t(((x) & BIT_MASK_MGQ_FIFO_START_PG_8821C)                              \\\n\t << BIT_SHIFT_MGQ_FIFO_START_PG_8821C)\n#define BITS_MGQ_FIFO_START_PG_8821C                                           \\\n\t(BIT_MASK_MGQ_FIFO_START_PG_8821C << BIT_SHIFT_MGQ_FIFO_START_PG_8821C)\n#define BIT_CLEAR_MGQ_FIFO_START_PG_8821C(x)                                   \\\n\t((x) & (~BITS_MGQ_FIFO_START_PG_8821C))\n#define BIT_GET_MGQ_FIFO_START_PG_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_START_PG_8821C) &                          \\\n\t BIT_MASK_MGQ_FIFO_START_PG_8821C)\n#define BIT_SET_MGQ_FIFO_START_PG_8821C(x, v)                                  \\\n\t(BIT_CLEAR_MGQ_FIFO_START_PG_8821C(x) | BIT_MGQ_FIFO_START_PG_8821C(v))\n\n/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK_8821C */\n\n#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C 0\n#define BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C 0xffff\n#define BIT_MGQ_FIFO_REL_INT_MASK_8821C(x)                                     \\\n\t(((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C)                          \\\n\t << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C)\n#define BITS_MGQ_FIFO_REL_INT_MASK_8821C                                       \\\n\t(BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C                                  \\\n\t << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C)\n#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8821C(x)                               \\\n\t((x) & (~BITS_MGQ_FIFO_REL_INT_MASK_8821C))\n#define BIT_GET_MGQ_FIFO_REL_INT_MASK_8821C(x)                                 \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C) &                      \\\n\t BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C)\n#define BIT_SET_MGQ_FIFO_REL_INT_MASK_8821C(x, v)                              \\\n\t(BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8821C(x) |                            \\\n\t BIT_MGQ_FIFO_REL_INT_MASK_8821C(v))\n\n/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG_8821C */\n\n#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C 0\n#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C 0xffff\n#define BIT_MGQ_FIFO_REL_INT_FLAG_8821C(x)                                     \\\n\t(((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C)                          \\\n\t << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C)\n#define BITS_MGQ_FIFO_REL_INT_FLAG_8821C                                       \\\n\t(BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C                                  \\\n\t << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C)\n#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8821C(x)                               \\\n\t((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG_8821C))\n#define BIT_GET_MGQ_FIFO_REL_INT_FLAG_8821C(x)                                 \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C) &                      \\\n\t BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C)\n#define BIT_SET_MGQ_FIFO_REL_INT_FLAG_8821C(x, v)                              \\\n\t(BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8821C(x) |                            \\\n\t BIT_MGQ_FIFO_REL_INT_FLAG_8821C(v))\n\n/* 2 REG_MGQ_FIFO_VALID_MAP_8821C */\n\n#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C 0\n#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C 0xffff\n#define BIT_MGQ_FIFO_PKT_VALID_MAP_8821C(x)                                    \\\n\t(((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C)                         \\\n\t << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C)\n#define BITS_MGQ_FIFO_PKT_VALID_MAP_8821C                                      \\\n\t(BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C                                 \\\n\t << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C)\n#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8821C(x)                              \\\n\t((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP_8821C))\n#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP_8821C(x)                                \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C) &                     \\\n\t BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C)\n#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP_8821C(x, v)                             \\\n\t(BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8821C(x) |                           \\\n\t BIT_MGQ_FIFO_PKT_VALID_MAP_8821C(v))\n\n/* 2 REG_MGQ_FIFO_LIFETIME_8821C */\n\n#define BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C 0\n#define BIT_MASK_MGQ_FIFO_LIFETIME_8821C 0xffff\n#define BIT_MGQ_FIFO_LIFETIME_8821C(x)                                         \\\n\t(((x) & BIT_MASK_MGQ_FIFO_LIFETIME_8821C)                              \\\n\t << BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C)\n#define BITS_MGQ_FIFO_LIFETIME_8821C                                           \\\n\t(BIT_MASK_MGQ_FIFO_LIFETIME_8821C << BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C)\n#define BIT_CLEAR_MGQ_FIFO_LIFETIME_8821C(x)                                   \\\n\t((x) & (~BITS_MGQ_FIFO_LIFETIME_8821C))\n#define BIT_GET_MGQ_FIFO_LIFETIME_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C) &                          \\\n\t BIT_MASK_MGQ_FIFO_LIFETIME_8821C)\n#define BIT_SET_MGQ_FIFO_LIFETIME_8821C(x, v)                                  \\\n\t(BIT_CLEAR_MGQ_FIFO_LIFETIME_8821C(x) | BIT_MGQ_FIFO_LIFETIME_8821C(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0x7f\n#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x)                      \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C)           \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C)\n#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C                        \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C                   \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x)                \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x)                  \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) &       \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x, v)               \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) |             \\\n\t BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(v))\n\n/* 2 REG_SHCUT_SETTING_8821C */\n\n/* 2 REG_SHCUT_LLC_ETH_TYPE0_8821C */\n\n/* 2 REG_SHCUT_LLC_ETH_TYPE1_8821C */\n\n/* 2 REG_SHCUT_LLC_OUI0_8821C */\n\n/* 2 REG_SHCUT_LLC_OUI1_8821C */\n\n/* 2 REG_SHCUT_LLC_OUI2_8821C */\n\n/* 2 REG_MU_TX_CTL_8821C */\n#define BIT_R_MU_P1_WAIT_STATE_EN_8821C BIT(16)\n\n#define BIT_SHIFT_R_MU_RL_8821C 12\n#define BIT_MASK_R_MU_RL_8821C 0xf\n#define BIT_R_MU_RL_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_R_MU_RL_8821C) << BIT_SHIFT_R_MU_RL_8821C)\n#define BITS_R_MU_RL_8821C (BIT_MASK_R_MU_RL_8821C << BIT_SHIFT_R_MU_RL_8821C)\n#define BIT_CLEAR_R_MU_RL_8821C(x) ((x) & (~BITS_R_MU_RL_8821C))\n#define BIT_GET_R_MU_RL_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_R_MU_RL_8821C) & BIT_MASK_R_MU_RL_8821C)\n#define BIT_SET_R_MU_RL_8821C(x, v)                                            \\\n\t(BIT_CLEAR_R_MU_RL_8821C(x) | BIT_R_MU_RL_8821C(v))\n\n#define BIT_R_FORCE_P1_RATEDOWN_8821C BIT(11)\n\n#define BIT_SHIFT_R_MU_TAB_SEL_8821C 8\n#define BIT_MASK_R_MU_TAB_SEL_8821C 0x7\n#define BIT_R_MU_TAB_SEL_8821C(x)                                              \\\n\t(((x) & BIT_MASK_R_MU_TAB_SEL_8821C) << BIT_SHIFT_R_MU_TAB_SEL_8821C)\n#define BITS_R_MU_TAB_SEL_8821C                                                \\\n\t(BIT_MASK_R_MU_TAB_SEL_8821C << BIT_SHIFT_R_MU_TAB_SEL_8821C)\n#define BIT_CLEAR_R_MU_TAB_SEL_8821C(x) ((x) & (~BITS_R_MU_TAB_SEL_8821C))\n#define BIT_GET_R_MU_TAB_SEL_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_MU_TAB_SEL_8821C) & BIT_MASK_R_MU_TAB_SEL_8821C)\n#define BIT_SET_R_MU_TAB_SEL_8821C(x, v)                                       \\\n\t(BIT_CLEAR_R_MU_TAB_SEL_8821C(x) | BIT_R_MU_TAB_SEL_8821C(v))\n\n#define BIT_R_EN_MU_MIMO_8821C BIT(7)\n#define BIT_R_EN_REVERS_GTAB_8821C BIT(6)\n\n#define BIT_SHIFT_R_MU_TABLE_VALID_8821C 0\n#define BIT_MASK_R_MU_TABLE_VALID_8821C 0x3f\n#define BIT_R_MU_TABLE_VALID_8821C(x)                                          \\\n\t(((x) & BIT_MASK_R_MU_TABLE_VALID_8821C)                               \\\n\t << BIT_SHIFT_R_MU_TABLE_VALID_8821C)\n#define BITS_R_MU_TABLE_VALID_8821C                                            \\\n\t(BIT_MASK_R_MU_TABLE_VALID_8821C << BIT_SHIFT_R_MU_TABLE_VALID_8821C)\n#define BIT_CLEAR_R_MU_TABLE_VALID_8821C(x)                                    \\\n\t((x) & (~BITS_R_MU_TABLE_VALID_8821C))\n#define BIT_GET_R_MU_TABLE_VALID_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8821C) &                           \\\n\t BIT_MASK_R_MU_TABLE_VALID_8821C)\n#define BIT_SET_R_MU_TABLE_VALID_8821C(x, v)                                   \\\n\t(BIT_CLEAR_R_MU_TABLE_VALID_8821C(x) | BIT_R_MU_TABLE_VALID_8821C(v))\n\n/* 2 REG_MU_STA_GID_VLD_8821C */\n\n#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C 0\n#define BIT_MASK_R_MU_STA_GTAB_VALID_8821C 0xffffffffL\n#define BIT_R_MU_STA_GTAB_VALID_8821C(x)                                       \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C)                            \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C)\n#define BITS_R_MU_STA_GTAB_VALID_8821C                                         \\\n\t(BIT_MASK_R_MU_STA_GTAB_VALID_8821C                                    \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C)\n#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8821C(x)                                 \\\n\t((x) & (~BITS_R_MU_STA_GTAB_VALID_8821C))\n#define BIT_GET_R_MU_STA_GTAB_VALID_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) &                        \\\n\t BIT_MASK_R_MU_STA_GTAB_VALID_8821C)\n#define BIT_SET_R_MU_STA_GTAB_VALID_8821C(x, v)                                \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_VALID_8821C(x) |                              \\\n\t BIT_R_MU_STA_GTAB_VALID_8821C(v))\n\n/* 2 REG_MU_STA_USER_POS_INFO_8821C */\n\n#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C 0\n#define BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C 0xffffffffL\n#define BIT_R_MU_STA_GTAB_POSITION_L_8821C(x)                                  \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C)                       \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C)\n#define BITS_R_MU_STA_GTAB_POSITION_L_8821C                                    \\\n\t(BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C                               \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C)\n#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8821C(x)                            \\\n\t((x) & (~BITS_R_MU_STA_GTAB_POSITION_L_8821C))\n#define BIT_GET_R_MU_STA_GTAB_POSITION_L_8821C(x)                              \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C) &                   \\\n\t BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C)\n#define BIT_SET_R_MU_STA_GTAB_POSITION_L_8821C(x, v)                           \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8821C(x) |                         \\\n\t BIT_R_MU_STA_GTAB_POSITION_L_8821C(v))\n\n/* 2 REG_MU_STA_USER_POS_INFO_H_8821C */\n\n#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C 0\n#define BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C 0xffffffffL\n#define BIT_R_MU_STA_GTAB_POSITION_H_8821C(x)                                  \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C)                       \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C)\n#define BITS_R_MU_STA_GTAB_POSITION_H_8821C                                    \\\n\t(BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C                               \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C)\n#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8821C(x)                            \\\n\t((x) & (~BITS_R_MU_STA_GTAB_POSITION_H_8821C))\n#define BIT_GET_R_MU_STA_GTAB_POSITION_H_8821C(x)                              \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C) &                   \\\n\t BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C)\n#define BIT_SET_R_MU_STA_GTAB_POSITION_H_8821C(x, v)                           \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8821C(x) |                         \\\n\t BIT_R_MU_STA_GTAB_POSITION_H_8821C(v))\n\n/* 2 REG_MU_TRX_DBG_CNT_8821C */\n#define BIT_MU_DNGCNT_RST_8821C BIT(20)\n\n#define BIT_SHIFT_MU_DBGCNT_SEL_8821C 16\n#define BIT_MASK_MU_DBGCNT_SEL_8821C 0xf\n#define BIT_MU_DBGCNT_SEL_8821C(x)                                             \\\n\t(((x) & BIT_MASK_MU_DBGCNT_SEL_8821C) << BIT_SHIFT_MU_DBGCNT_SEL_8821C)\n#define BITS_MU_DBGCNT_SEL_8821C                                               \\\n\t(BIT_MASK_MU_DBGCNT_SEL_8821C << BIT_SHIFT_MU_DBGCNT_SEL_8821C)\n#define BIT_CLEAR_MU_DBGCNT_SEL_8821C(x) ((x) & (~BITS_MU_DBGCNT_SEL_8821C))\n#define BIT_GET_MU_DBGCNT_SEL_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8821C) & BIT_MASK_MU_DBGCNT_SEL_8821C)\n#define BIT_SET_MU_DBGCNT_SEL_8821C(x, v)                                      \\\n\t(BIT_CLEAR_MU_DBGCNT_SEL_8821C(x) | BIT_MU_DBGCNT_SEL_8821C(v))\n\n#define BIT_SHIFT_MU_DNGCNT_8821C 0\n#define BIT_MASK_MU_DNGCNT_8821C 0xffff\n#define BIT_MU_DNGCNT_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_MU_DNGCNT_8821C) << BIT_SHIFT_MU_DNGCNT_8821C)\n#define BITS_MU_DNGCNT_8821C                                                   \\\n\t(BIT_MASK_MU_DNGCNT_8821C << BIT_SHIFT_MU_DNGCNT_8821C)\n#define BIT_CLEAR_MU_DNGCNT_8821C(x) ((x) & (~BITS_MU_DNGCNT_8821C))\n#define BIT_GET_MU_DNGCNT_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MU_DNGCNT_8821C) & BIT_MASK_MU_DNGCNT_8821C)\n#define BIT_SET_MU_DNGCNT_8821C(x, v)                                          \\\n\t(BIT_CLEAR_MU_DNGCNT_8821C(x) | BIT_MU_DNGCNT_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_EDCA_VO_PARAM_8821C */\n\n#define BIT_SHIFT_TXOPLIMIT_8821C 16\n#define BIT_MASK_TXOPLIMIT_8821C 0x7ff\n#define BIT_TXOPLIMIT_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C)\n#define BITS_TXOPLIMIT_8821C                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C)\n#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C))\n#define BIT_GET_TXOPLIMIT_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C)\n#define BIT_SET_TXOPLIMIT_8821C(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v))\n\n#define BIT_SHIFT_CW_8821C 8\n#define BIT_MASK_CW_8821C 0xff\n#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C)\n#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C)\n#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C))\n#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C)\n#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v))\n\n#define BIT_SHIFT_AIFS_8821C 0\n#define BIT_MASK_AIFS_8821C 0xff\n#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C)\n#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C)\n#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C))\n#define BIT_GET_AIFS_8821C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)\n#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v))\n\n/* 2 REG_EDCA_VI_PARAM_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n#define BIT_SHIFT_TXOPLIMIT_8821C 16\n#define BIT_MASK_TXOPLIMIT_8821C 0x7ff\n#define BIT_TXOPLIMIT_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C)\n#define BITS_TXOPLIMIT_8821C                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C)\n#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C))\n#define BIT_GET_TXOPLIMIT_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C)\n#define BIT_SET_TXOPLIMIT_8821C(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v))\n\n#define BIT_SHIFT_CW_8821C 8\n#define BIT_MASK_CW_8821C 0xff\n#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C)\n#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C)\n#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C))\n#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C)\n#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v))\n\n#define BIT_SHIFT_AIFS_8821C 0\n#define BIT_MASK_AIFS_8821C 0xff\n#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C)\n#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C)\n#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C))\n#define BIT_GET_AIFS_8821C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)\n#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v))\n\n/* 2 REG_EDCA_BE_PARAM_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n#define BIT_SHIFT_TXOPLIMIT_8821C 16\n#define BIT_MASK_TXOPLIMIT_8821C 0x7ff\n#define BIT_TXOPLIMIT_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C)\n#define BITS_TXOPLIMIT_8821C                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C)\n#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C))\n#define BIT_GET_TXOPLIMIT_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C)\n#define BIT_SET_TXOPLIMIT_8821C(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v))\n\n#define BIT_SHIFT_CW_8821C 8\n#define BIT_MASK_CW_8821C 0xff\n#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C)\n#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C)\n#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C))\n#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C)\n#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v))\n\n#define BIT_SHIFT_AIFS_8821C 0\n#define BIT_MASK_AIFS_8821C 0xff\n#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C)\n#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C)\n#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C))\n#define BIT_GET_AIFS_8821C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)\n#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v))\n\n/* 2 REG_EDCA_BK_PARAM_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n#define BIT_SHIFT_TXOPLIMIT_8821C 16\n#define BIT_MASK_TXOPLIMIT_8821C 0x7ff\n#define BIT_TXOPLIMIT_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C)\n#define BITS_TXOPLIMIT_8821C                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C)\n#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C))\n#define BIT_GET_TXOPLIMIT_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C)\n#define BIT_SET_TXOPLIMIT_8821C(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v))\n\n#define BIT_SHIFT_CW_8821C 8\n#define BIT_MASK_CW_8821C 0xff\n#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C)\n#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C)\n#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C))\n#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C)\n#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v))\n\n#define BIT_SHIFT_AIFS_8821C 0\n#define BIT_MASK_AIFS_8821C 0xff\n#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C)\n#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C)\n#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C))\n#define BIT_GET_AIFS_8821C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)\n#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v))\n\n/* 2 REG_BCNTCFG_8821C */\n\n#define BIT_SHIFT_BCNCW_MAX_8821C 12\n#define BIT_MASK_BCNCW_MAX_8821C 0xf\n#define BIT_BCNCW_MAX_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_BCNCW_MAX_8821C) << BIT_SHIFT_BCNCW_MAX_8821C)\n#define BITS_BCNCW_MAX_8821C                                                   \\\n\t(BIT_MASK_BCNCW_MAX_8821C << BIT_SHIFT_BCNCW_MAX_8821C)\n#define BIT_CLEAR_BCNCW_MAX_8821C(x) ((x) & (~BITS_BCNCW_MAX_8821C))\n#define BIT_GET_BCNCW_MAX_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNCW_MAX_8821C) & BIT_MASK_BCNCW_MAX_8821C)\n#define BIT_SET_BCNCW_MAX_8821C(x, v)                                          \\\n\t(BIT_CLEAR_BCNCW_MAX_8821C(x) | BIT_BCNCW_MAX_8821C(v))\n\n#define BIT_SHIFT_BCNCW_MIN_8821C 8\n#define BIT_MASK_BCNCW_MIN_8821C 0xf\n#define BIT_BCNCW_MIN_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_BCNCW_MIN_8821C) << BIT_SHIFT_BCNCW_MIN_8821C)\n#define BITS_BCNCW_MIN_8821C                                                   \\\n\t(BIT_MASK_BCNCW_MIN_8821C << BIT_SHIFT_BCNCW_MIN_8821C)\n#define BIT_CLEAR_BCNCW_MIN_8821C(x) ((x) & (~BITS_BCNCW_MIN_8821C))\n#define BIT_GET_BCNCW_MIN_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNCW_MIN_8821C) & BIT_MASK_BCNCW_MIN_8821C)\n#define BIT_SET_BCNCW_MIN_8821C(x, v)                                          \\\n\t(BIT_CLEAR_BCNCW_MIN_8821C(x) | BIT_BCNCW_MIN_8821C(v))\n\n#define BIT_SHIFT_BCNIFS_8821C 0\n#define BIT_MASK_BCNIFS_8821C 0xff\n#define BIT_BCNIFS_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_BCNIFS_8821C) << BIT_SHIFT_BCNIFS_8821C)\n#define BITS_BCNIFS_8821C (BIT_MASK_BCNIFS_8821C << BIT_SHIFT_BCNIFS_8821C)\n#define BIT_CLEAR_BCNIFS_8821C(x) ((x) & (~BITS_BCNIFS_8821C))\n#define BIT_GET_BCNIFS_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_BCNIFS_8821C) & BIT_MASK_BCNIFS_8821C)\n#define BIT_SET_BCNIFS_8821C(x, v)                                             \\\n\t(BIT_CLEAR_BCNIFS_8821C(x) | BIT_BCNIFS_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_PIFS_8821C */\n\n#define BIT_SHIFT_PIFS_8821C 0\n#define BIT_MASK_PIFS_8821C 0xff\n#define BIT_PIFS_8821C(x) (((x) & BIT_MASK_PIFS_8821C) << BIT_SHIFT_PIFS_8821C)\n#define BITS_PIFS_8821C (BIT_MASK_PIFS_8821C << BIT_SHIFT_PIFS_8821C)\n#define BIT_CLEAR_PIFS_8821C(x) ((x) & (~BITS_PIFS_8821C))\n#define BIT_GET_PIFS_8821C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_PIFS_8821C) & BIT_MASK_PIFS_8821C)\n#define BIT_SET_PIFS_8821C(x, v) (BIT_CLEAR_PIFS_8821C(x) | BIT_PIFS_8821C(v))\n\n/* 2 REG_RDG_PIFS_8821C */\n\n#define BIT_SHIFT_RDG_PIFS_8821C 0\n#define BIT_MASK_RDG_PIFS_8821C 0xff\n#define BIT_RDG_PIFS_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_RDG_PIFS_8821C) << BIT_SHIFT_RDG_PIFS_8821C)\n#define BITS_RDG_PIFS_8821C                                                    \\\n\t(BIT_MASK_RDG_PIFS_8821C << BIT_SHIFT_RDG_PIFS_8821C)\n#define BIT_CLEAR_RDG_PIFS_8821C(x) ((x) & (~BITS_RDG_PIFS_8821C))\n#define BIT_GET_RDG_PIFS_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RDG_PIFS_8821C) & BIT_MASK_RDG_PIFS_8821C)\n#define BIT_SET_RDG_PIFS_8821C(x, v)                                           \\\n\t(BIT_CLEAR_RDG_PIFS_8821C(x) | BIT_RDG_PIFS_8821C(v))\n\n/* 2 REG_SIFS_8821C */\n\n#define BIT_SHIFT_SIFS_OFDM_TRX_8821C 24\n#define BIT_MASK_SIFS_OFDM_TRX_8821C 0xff\n#define BIT_SIFS_OFDM_TRX_8821C(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_OFDM_TRX_8821C) << BIT_SHIFT_SIFS_OFDM_TRX_8821C)\n#define BITS_SIFS_OFDM_TRX_8821C                                               \\\n\t(BIT_MASK_SIFS_OFDM_TRX_8821C << BIT_SHIFT_SIFS_OFDM_TRX_8821C)\n#define BIT_CLEAR_SIFS_OFDM_TRX_8821C(x) ((x) & (~BITS_SIFS_OFDM_TRX_8821C))\n#define BIT_GET_SIFS_OFDM_TRX_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8821C) & BIT_MASK_SIFS_OFDM_TRX_8821C)\n#define BIT_SET_SIFS_OFDM_TRX_8821C(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_OFDM_TRX_8821C(x) | BIT_SIFS_OFDM_TRX_8821C(v))\n\n#define BIT_SHIFT_SIFS_CCK_TRX_8821C 16\n#define BIT_MASK_SIFS_CCK_TRX_8821C 0xff\n#define BIT_SIFS_CCK_TRX_8821C(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_CCK_TRX_8821C) << BIT_SHIFT_SIFS_CCK_TRX_8821C)\n#define BITS_SIFS_CCK_TRX_8821C                                                \\\n\t(BIT_MASK_SIFS_CCK_TRX_8821C << BIT_SHIFT_SIFS_CCK_TRX_8821C)\n#define BIT_CLEAR_SIFS_CCK_TRX_8821C(x) ((x) & (~BITS_SIFS_CCK_TRX_8821C))\n#define BIT_GET_SIFS_CCK_TRX_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_CCK_TRX_8821C) & BIT_MASK_SIFS_CCK_TRX_8821C)\n#define BIT_SET_SIFS_CCK_TRX_8821C(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_CCK_TRX_8821C(x) | BIT_SIFS_CCK_TRX_8821C(v))\n\n#define BIT_SHIFT_SIFS_OFDM_CTX_8821C 8\n#define BIT_MASK_SIFS_OFDM_CTX_8821C 0xff\n#define BIT_SIFS_OFDM_CTX_8821C(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_OFDM_CTX_8821C) << BIT_SHIFT_SIFS_OFDM_CTX_8821C)\n#define BITS_SIFS_OFDM_CTX_8821C                                               \\\n\t(BIT_MASK_SIFS_OFDM_CTX_8821C << BIT_SHIFT_SIFS_OFDM_CTX_8821C)\n#define BIT_CLEAR_SIFS_OFDM_CTX_8821C(x) ((x) & (~BITS_SIFS_OFDM_CTX_8821C))\n#define BIT_GET_SIFS_OFDM_CTX_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8821C) & BIT_MASK_SIFS_OFDM_CTX_8821C)\n#define BIT_SET_SIFS_OFDM_CTX_8821C(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_OFDM_CTX_8821C(x) | BIT_SIFS_OFDM_CTX_8821C(v))\n\n#define BIT_SHIFT_SIFS_CCK_CTX_8821C 0\n#define BIT_MASK_SIFS_CCK_CTX_8821C 0xff\n#define BIT_SIFS_CCK_CTX_8821C(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_CCK_CTX_8821C) << BIT_SHIFT_SIFS_CCK_CTX_8821C)\n#define BITS_SIFS_CCK_CTX_8821C                                                \\\n\t(BIT_MASK_SIFS_CCK_CTX_8821C << BIT_SHIFT_SIFS_CCK_CTX_8821C)\n#define BIT_CLEAR_SIFS_CCK_CTX_8821C(x) ((x) & (~BITS_SIFS_CCK_CTX_8821C))\n#define BIT_GET_SIFS_CCK_CTX_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_CCK_CTX_8821C) & BIT_MASK_SIFS_CCK_CTX_8821C)\n#define BIT_SET_SIFS_CCK_CTX_8821C(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_CCK_CTX_8821C(x) | BIT_SIFS_CCK_CTX_8821C(v))\n\n/* 2 REG_TSFTR_SYN_OFFSET_8821C */\n\n#define BIT_SHIFT_TSFTR_SNC_OFFSET_8821C 0\n#define BIT_MASK_TSFTR_SNC_OFFSET_8821C 0xffff\n#define BIT_TSFTR_SNC_OFFSET_8821C(x)                                          \\\n\t(((x) & BIT_MASK_TSFTR_SNC_OFFSET_8821C)                               \\\n\t << BIT_SHIFT_TSFTR_SNC_OFFSET_8821C)\n#define BITS_TSFTR_SNC_OFFSET_8821C                                            \\\n\t(BIT_MASK_TSFTR_SNC_OFFSET_8821C << BIT_SHIFT_TSFTR_SNC_OFFSET_8821C)\n#define BIT_CLEAR_TSFTR_SNC_OFFSET_8821C(x)                                    \\\n\t((x) & (~BITS_TSFTR_SNC_OFFSET_8821C))\n#define BIT_GET_TSFTR_SNC_OFFSET_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8821C) &                           \\\n\t BIT_MASK_TSFTR_SNC_OFFSET_8821C)\n#define BIT_SET_TSFTR_SNC_OFFSET_8821C(x, v)                                   \\\n\t(BIT_CLEAR_TSFTR_SNC_OFFSET_8821C(x) | BIT_TSFTR_SNC_OFFSET_8821C(v))\n\n/* 2 REG_AGGR_BREAK_TIME_8821C */\n\n#define BIT_SHIFT_AGGR_BK_TIME_8821C 0\n#define BIT_MASK_AGGR_BK_TIME_8821C 0xff\n#define BIT_AGGR_BK_TIME_8821C(x)                                              \\\n\t(((x) & BIT_MASK_AGGR_BK_TIME_8821C) << BIT_SHIFT_AGGR_BK_TIME_8821C)\n#define BITS_AGGR_BK_TIME_8821C                                                \\\n\t(BIT_MASK_AGGR_BK_TIME_8821C << BIT_SHIFT_AGGR_BK_TIME_8821C)\n#define BIT_CLEAR_AGGR_BK_TIME_8821C(x) ((x) & (~BITS_AGGR_BK_TIME_8821C))\n#define BIT_GET_AGGR_BK_TIME_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AGGR_BK_TIME_8821C) & BIT_MASK_AGGR_BK_TIME_8821C)\n#define BIT_SET_AGGR_BK_TIME_8821C(x, v)                                       \\\n\t(BIT_CLEAR_AGGR_BK_TIME_8821C(x) | BIT_AGGR_BK_TIME_8821C(v))\n\n/* 2 REG_SLOT_8821C */\n\n#define BIT_SHIFT_SLOT_8821C 0\n#define BIT_MASK_SLOT_8821C 0xff\n#define BIT_SLOT_8821C(x) (((x) & BIT_MASK_SLOT_8821C) << BIT_SHIFT_SLOT_8821C)\n#define BITS_SLOT_8821C (BIT_MASK_SLOT_8821C << BIT_SHIFT_SLOT_8821C)\n#define BIT_CLEAR_SLOT_8821C(x) ((x) & (~BITS_SLOT_8821C))\n#define BIT_GET_SLOT_8821C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_SLOT_8821C) & BIT_MASK_SLOT_8821C)\n#define BIT_SET_SLOT_8821C(x, v) (BIT_CLEAR_SLOT_8821C(x) | BIT_SLOT_8821C(v))\n\n/* 2 REG_NOA_ON_ERLY_TIME_8821C */\n\n#define BIT_SHIFT__NOA_ON_ERLY_TIME_8821C 0\n#define BIT_MASK__NOA_ON_ERLY_TIME_8821C 0xff\n#define BIT__NOA_ON_ERLY_TIME_8821C(x)                                         \\\n\t(((x) & BIT_MASK__NOA_ON_ERLY_TIME_8821C)                              \\\n\t << BIT_SHIFT__NOA_ON_ERLY_TIME_8821C)\n#define BITS__NOA_ON_ERLY_TIME_8821C                                           \\\n\t(BIT_MASK__NOA_ON_ERLY_TIME_8821C << BIT_SHIFT__NOA_ON_ERLY_TIME_8821C)\n#define BIT_CLEAR__NOA_ON_ERLY_TIME_8821C(x)                                   \\\n\t((x) & (~BITS__NOA_ON_ERLY_TIME_8821C))\n#define BIT_GET__NOA_ON_ERLY_TIME_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME_8821C) &                          \\\n\t BIT_MASK__NOA_ON_ERLY_TIME_8821C)\n#define BIT_SET__NOA_ON_ERLY_TIME_8821C(x, v)                                  \\\n\t(BIT_CLEAR__NOA_ON_ERLY_TIME_8821C(x) | BIT__NOA_ON_ERLY_TIME_8821C(v))\n\n/* 2 REG_NOA_OFF_ERLY_TIME_8821C */\n\n#define BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C 0\n#define BIT_MASK__NOA_OFF_ERLY_TIME_8821C 0xff\n#define BIT__NOA_OFF_ERLY_TIME_8821C(x)                                        \\\n\t(((x) & BIT_MASK__NOA_OFF_ERLY_TIME_8821C)                             \\\n\t << BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C)\n#define BITS__NOA_OFF_ERLY_TIME_8821C                                          \\\n\t(BIT_MASK__NOA_OFF_ERLY_TIME_8821C                                     \\\n\t << BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C)\n#define BIT_CLEAR__NOA_OFF_ERLY_TIME_8821C(x)                                  \\\n\t((x) & (~BITS__NOA_OFF_ERLY_TIME_8821C))\n#define BIT_GET__NOA_OFF_ERLY_TIME_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C) &                         \\\n\t BIT_MASK__NOA_OFF_ERLY_TIME_8821C)\n#define BIT_SET__NOA_OFF_ERLY_TIME_8821C(x, v)                                 \\\n\t(BIT_CLEAR__NOA_OFF_ERLY_TIME_8821C(x) |                               \\\n\t BIT__NOA_OFF_ERLY_TIME_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_TX_PTCL_CTRL_8821C */\n#define BIT_DIS_EDCCA_8821C BIT(15)\n#define BIT_DIS_CCA_8821C BIT(14)\n#define BIT_LSIG_TXOP_TXCMD_NAV_8821C BIT(13)\n#define BIT_SIFS_BK_EN_8821C BIT(12)\n\n#define BIT_SHIFT_TXQ_NAV_MSK_8821C 8\n#define BIT_MASK_TXQ_NAV_MSK_8821C 0xf\n#define BIT_TXQ_NAV_MSK_8821C(x)                                               \\\n\t(((x) & BIT_MASK_TXQ_NAV_MSK_8821C) << BIT_SHIFT_TXQ_NAV_MSK_8821C)\n#define BITS_TXQ_NAV_MSK_8821C                                                 \\\n\t(BIT_MASK_TXQ_NAV_MSK_8821C << BIT_SHIFT_TXQ_NAV_MSK_8821C)\n#define BIT_CLEAR_TXQ_NAV_MSK_8821C(x) ((x) & (~BITS_TXQ_NAV_MSK_8821C))\n#define BIT_GET_TXQ_NAV_MSK_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_TXQ_NAV_MSK_8821C) & BIT_MASK_TXQ_NAV_MSK_8821C)\n#define BIT_SET_TXQ_NAV_MSK_8821C(x, v)                                        \\\n\t(BIT_CLEAR_TXQ_NAV_MSK_8821C(x) | BIT_TXQ_NAV_MSK_8821C(v))\n\n#define BIT_DIS_CW_8821C BIT(7)\n#define BIT_NAV_END_TXOP_8821C BIT(6)\n#define BIT_RDG_END_TXOP_8821C BIT(5)\n#define BIT_AC_INBCN_HOLD_8821C BIT(4)\n#define BIT_MGTQ_TXOP_EN_8821C BIT(3)\n#define BIT_MGTQ_RTSMF_EN_8821C BIT(2)\n#define BIT_HIQ_RTSMF_EN_8821C BIT(1)\n#define BIT_BCN_RTSMF_EN_8821C BIT(0)\n\n/* 2 REG_TXPAUSE_8821C */\n#define BIT_STOP_BCN_HI_MGT_8821C BIT(7)\n#define BIT_MAC_STOPBCNQ_8821C BIT(6)\n#define BIT_MAC_STOPHIQ_8821C BIT(5)\n#define BIT_MAC_STOPMGQ_8821C BIT(4)\n#define BIT_MAC_STOPBK_8821C BIT(3)\n#define BIT_MAC_STOPBE_8821C BIT(2)\n#define BIT_MAC_STOPVI_8821C BIT(1)\n#define BIT_MAC_STOPVO_8821C BIT(0)\n\n/* 2 REG_DIS_TXREQ_CLR_8821C */\n#define BIT_DIS_BT_CCA_8821C BIT(7)\n#define BIT_DIS_TXREQ_CLR_HI_8821C BIT(5)\n#define BIT_DIS_TXREQ_CLR_MGQ_8821C BIT(4)\n#define BIT_DIS_TXREQ_CLR_VO_8821C BIT(3)\n#define BIT_DIS_TXREQ_CLR_VI_8821C BIT(2)\n#define BIT_DIS_TXREQ_CLR_BE_8821C BIT(1)\n#define BIT_DIS_TXREQ_CLR_BK_8821C BIT(0)\n\n/* 2 REG_RD_CTRL_8821C */\n#define BIT_EN_CLR_TXREQ_INCCA_8821C BIT(15)\n#define BIT_DIS_TX_OVER_BCNQ_8821C BIT(14)\n#define BIT_EN_BCNERR_INCCCA_8821C BIT(13)\n#define BIT_EDCCA_MSK_CNTDOWN_EN_8821C BIT(11)\n#define BIT_DIS_TXOP_CFE_8821C BIT(10)\n#define BIT_DIS_LSIG_CFE_8821C BIT(9)\n#define BIT_DIS_STBC_CFE_8821C BIT(8)\n#define BIT_BKQ_RD_INIT_EN_8821C BIT(7)\n#define BIT_BEQ_RD_INIT_EN_8821C BIT(6)\n#define BIT_VIQ_RD_INIT_EN_8821C BIT(5)\n#define BIT_VOQ_RD_INIT_EN_8821C BIT(4)\n#define BIT_BKQ_RD_RESP_EN_8821C BIT(3)\n#define BIT_BEQ_RD_RESP_EN_8821C BIT(2)\n#define BIT_VIQ_RD_RESP_EN_8821C BIT(1)\n#define BIT_VOQ_RD_RESP_EN_8821C BIT(0)\n\n/* 2 REG_MBSSID_CTRL_8821C */\n#define BIT_MBID_BCNQ7_EN_8821C BIT(7)\n#define BIT_MBID_BCNQ6_EN_8821C BIT(6)\n#define BIT_MBID_BCNQ5_EN_8821C BIT(5)\n#define BIT_MBID_BCNQ4_EN_8821C BIT(4)\n#define BIT_MBID_BCNQ3_EN_8821C BIT(3)\n#define BIT_MBID_BCNQ2_EN_8821C BIT(2)\n#define BIT_MBID_BCNQ1_EN_8821C BIT(1)\n#define BIT_MBID_BCNQ0_EN_8821C BIT(0)\n\n/* 2 REG_P2PPS_CTRL_8821C */\n#define BIT_P2P_CTW_ALLSTASLEEP_8821C BIT(7)\n#define BIT_P2P_OFF_DISTX_EN_8821C BIT(6)\n#define BIT_PWR_MGT_EN_8821C BIT(5)\n#define BIT_P2P_NOA1_EN_8821C BIT(2)\n#define BIT_P2P_NOA0_EN_8821C BIT(1)\n\n/* 2 REG_PKT_LIFETIME_CTRL_8821C */\n#define BIT_EN_P2P_CTWND1_8821C BIT(23)\n#define BIT_EN_BKF_CLR_TXREQ_8821C BIT(22)\n#define BIT_EN_TSFBIT32_RST_P2P_8821C BIT(21)\n#define BIT_EN_BCN_TX_BTCCA_8821C BIT(20)\n#define BIT_DIS_PKT_TX_ATIM_8821C BIT(19)\n#define BIT_DIS_BCN_DIS_CTN_8821C BIT(18)\n#define BIT_EN_NAVEND_RST_TXOP_8821C BIT(17)\n#define BIT_EN_FILTER_CCA_8821C BIT(16)\n\n#define BIT_SHIFT_CCA_FILTER_THRS_8821C 8\n#define BIT_MASK_CCA_FILTER_THRS_8821C 0xff\n#define BIT_CCA_FILTER_THRS_8821C(x)                                           \\\n\t(((x) & BIT_MASK_CCA_FILTER_THRS_8821C)                                \\\n\t << BIT_SHIFT_CCA_FILTER_THRS_8821C)\n#define BITS_CCA_FILTER_THRS_8821C                                             \\\n\t(BIT_MASK_CCA_FILTER_THRS_8821C << BIT_SHIFT_CCA_FILTER_THRS_8821C)\n#define BIT_CLEAR_CCA_FILTER_THRS_8821C(x) ((x) & (~BITS_CCA_FILTER_THRS_8821C))\n#define BIT_GET_CCA_FILTER_THRS_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_CCA_FILTER_THRS_8821C) &                            \\\n\t BIT_MASK_CCA_FILTER_THRS_8821C)\n#define BIT_SET_CCA_FILTER_THRS_8821C(x, v)                                    \\\n\t(BIT_CLEAR_CCA_FILTER_THRS_8821C(x) | BIT_CCA_FILTER_THRS_8821C(v))\n\n#define BIT_SHIFT_EDCCA_THRS_8821C 0\n#define BIT_MASK_EDCCA_THRS_8821C 0xff\n#define BIT_EDCCA_THRS_8821C(x)                                                \\\n\t(((x) & BIT_MASK_EDCCA_THRS_8821C) << BIT_SHIFT_EDCCA_THRS_8821C)\n#define BITS_EDCCA_THRS_8821C                                                  \\\n\t(BIT_MASK_EDCCA_THRS_8821C << BIT_SHIFT_EDCCA_THRS_8821C)\n#define BIT_CLEAR_EDCCA_THRS_8821C(x) ((x) & (~BITS_EDCCA_THRS_8821C))\n#define BIT_GET_EDCCA_THRS_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_EDCCA_THRS_8821C) & BIT_MASK_EDCCA_THRS_8821C)\n#define BIT_SET_EDCCA_THRS_8821C(x, v)                                         \\\n\t(BIT_CLEAR_EDCCA_THRS_8821C(x) | BIT_EDCCA_THRS_8821C(v))\n\n/* 2 REG_P2PPS_SPEC_STATE_8821C */\n#define BIT_SPEC_POWER_STATE_8821C BIT(7)\n#define BIT_SPEC_CTWINDOW_ON_8821C BIT(6)\n#define BIT_SPEC_BEACON_AREA_ON_8821C BIT(5)\n#define BIT_SPEC_CTWIN_EARLY_DISTX_8821C BIT(4)\n#define BIT_SPEC_NOA1_OFF_PERIOD_8821C BIT(3)\n#define BIT_SPEC_FORCE_DOZE1_8821C BIT(2)\n#define BIT_SPEC_NOA0_OFF_PERIOD_8821C BIT(1)\n#define BIT_SPEC_FORCE_DOZE0_8821C BIT(0)\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_BAR_TX_CTRL_8821C */\n\n/* 2 REG_P2PON_DIS_TXTIME_8821C */\n\n#define BIT_SHIFT_P2PON_DIS_TXTIME_8821C 0\n#define BIT_MASK_P2PON_DIS_TXTIME_8821C 0xff\n#define BIT_P2PON_DIS_TXTIME_8821C(x)                                          \\\n\t(((x) & BIT_MASK_P2PON_DIS_TXTIME_8821C)                               \\\n\t << BIT_SHIFT_P2PON_DIS_TXTIME_8821C)\n#define BITS_P2PON_DIS_TXTIME_8821C                                            \\\n\t(BIT_MASK_P2PON_DIS_TXTIME_8821C << BIT_SHIFT_P2PON_DIS_TXTIME_8821C)\n#define BIT_CLEAR_P2PON_DIS_TXTIME_8821C(x)                                    \\\n\t((x) & (~BITS_P2PON_DIS_TXTIME_8821C))\n#define BIT_GET_P2PON_DIS_TXTIME_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8821C) &                           \\\n\t BIT_MASK_P2PON_DIS_TXTIME_8821C)\n#define BIT_SET_P2PON_DIS_TXTIME_8821C(x, v)                                   \\\n\t(BIT_CLEAR_P2PON_DIS_TXTIME_8821C(x) | BIT_P2PON_DIS_TXTIME_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_TBTT_PROHIBIT_8821C */\n\n#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C 8\n#define BIT_MASK_TBTT_HOLD_TIME_AP_8821C 0xfff\n#define BIT_TBTT_HOLD_TIME_AP_8821C(x)                                         \\\n\t(((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8821C)                              \\\n\t << BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C)\n#define BITS_TBTT_HOLD_TIME_AP_8821C                                           \\\n\t(BIT_MASK_TBTT_HOLD_TIME_AP_8821C << BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C)\n#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8821C(x)                                   \\\n\t((x) & (~BITS_TBTT_HOLD_TIME_AP_8821C))\n#define BIT_GET_TBTT_HOLD_TIME_AP_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C) &                          \\\n\t BIT_MASK_TBTT_HOLD_TIME_AP_8821C)\n#define BIT_SET_TBTT_HOLD_TIME_AP_8821C(x, v)                                  \\\n\t(BIT_CLEAR_TBTT_HOLD_TIME_AP_8821C(x) | BIT_TBTT_HOLD_TIME_AP_8821C(v))\n\n#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C 0\n#define BIT_MASK_TBTT_PROHIBIT_SETUP_8821C 0xf\n#define BIT_TBTT_PROHIBIT_SETUP_8821C(x)                                       \\\n\t(((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8821C)                            \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C)\n#define BITS_TBTT_PROHIBIT_SETUP_8821C                                         \\\n\t(BIT_MASK_TBTT_PROHIBIT_SETUP_8821C                                    \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C)\n#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8821C(x)                                 \\\n\t((x) & (~BITS_TBTT_PROHIBIT_SETUP_8821C))\n#define BIT_GET_TBTT_PROHIBIT_SETUP_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) &                        \\\n\t BIT_MASK_TBTT_PROHIBIT_SETUP_8821C)\n#define BIT_SET_TBTT_PROHIBIT_SETUP_8821C(x, v)                                \\\n\t(BIT_CLEAR_TBTT_PROHIBIT_SETUP_8821C(x) |                              \\\n\t BIT_TBTT_PROHIBIT_SETUP_8821C(v))\n\n/* 2 REG_P2PPS_STATE_8821C */\n#define BIT_POWER_STATE_8821C BIT(7)\n#define BIT_CTWINDOW_ON_8821C BIT(6)\n#define BIT_BEACON_AREA_ON_8821C BIT(5)\n#define BIT_CTWIN_EARLY_DISTX_8821C BIT(4)\n#define BIT_NOA1_OFF_PERIOD_8821C BIT(3)\n#define BIT_FORCE_DOZE1_8821C BIT(2)\n#define BIT_NOA0_OFF_PERIOD_8821C BIT(1)\n#define BIT_FORCE_DOZE0_8821C BIT(0)\n\n/* 2 REG_RD_NAV_NXT_8821C */\n\n#define BIT_SHIFT_RD_NAV_PROT_NXT_8821C 0\n#define BIT_MASK_RD_NAV_PROT_NXT_8821C 0xffff\n#define BIT_RD_NAV_PROT_NXT_8821C(x)                                           \\\n\t(((x) & BIT_MASK_RD_NAV_PROT_NXT_8821C)                                \\\n\t << BIT_SHIFT_RD_NAV_PROT_NXT_8821C)\n#define BITS_RD_NAV_PROT_NXT_8821C                                             \\\n\t(BIT_MASK_RD_NAV_PROT_NXT_8821C << BIT_SHIFT_RD_NAV_PROT_NXT_8821C)\n#define BIT_CLEAR_RD_NAV_PROT_NXT_8821C(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8821C))\n#define BIT_GET_RD_NAV_PROT_NXT_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8821C) &                            \\\n\t BIT_MASK_RD_NAV_PROT_NXT_8821C)\n#define BIT_SET_RD_NAV_PROT_NXT_8821C(x, v)                                    \\\n\t(BIT_CLEAR_RD_NAV_PROT_NXT_8821C(x) | BIT_RD_NAV_PROT_NXT_8821C(v))\n\n/* 2 REG_NAV_PROT_LEN_8821C */\n\n#define BIT_SHIFT_NAV_PROT_LEN_8821C 0\n#define BIT_MASK_NAV_PROT_LEN_8821C 0xffff\n#define BIT_NAV_PROT_LEN_8821C(x)                                              \\\n\t(((x) & BIT_MASK_NAV_PROT_LEN_8821C) << BIT_SHIFT_NAV_PROT_LEN_8821C)\n#define BITS_NAV_PROT_LEN_8821C                                                \\\n\t(BIT_MASK_NAV_PROT_LEN_8821C << BIT_SHIFT_NAV_PROT_LEN_8821C)\n#define BIT_CLEAR_NAV_PROT_LEN_8821C(x) ((x) & (~BITS_NAV_PROT_LEN_8821C))\n#define BIT_GET_NAV_PROT_LEN_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_NAV_PROT_LEN_8821C) & BIT_MASK_NAV_PROT_LEN_8821C)\n#define BIT_SET_NAV_PROT_LEN_8821C(x, v)                                       \\\n\t(BIT_CLEAR_NAV_PROT_LEN_8821C(x) | BIT_NAV_PROT_LEN_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_BCN_CTRL_8821C */\n#define BIT_DIS_RX_BSSID_FIT_8821C BIT(6)\n#define BIT_P0_EN_TXBCN_RPT_8821C BIT(5)\n#define BIT_DIS_TSF_UDT_8821C BIT(4)\n#define BIT_EN_BCN_FUNCTION_8821C BIT(3)\n#define BIT_P0_EN_RXBCN_RPT_8821C BIT(2)\n#define BIT_EN_P2P_CTWINDOW_8821C BIT(1)\n#define BIT_EN_P2P_BCNQ_AREA_8821C BIT(0)\n\n/* 2 REG_BCN_CTRL_CLINT0_8821C */\n#define BIT_CLI0_DIS_RX_BSSID_FIT_8821C BIT(6)\n#define BIT_CLI0_DIS_TSF_UDT_8821C BIT(4)\n#define BIT_CLI0_EN_BCN_FUNCTION_8821C BIT(3)\n#define BIT_CLI0_EN_RXBCN_RPT_8821C BIT(2)\n#define BIT_CLI0_ENP2P_CTWINDOW_8821C BIT(1)\n#define BIT_CLI0_ENP2P_BCNQ_AREA_8821C BIT(0)\n\n/* 2 REG_MBID_NUM_8821C */\n#define BIT_EN_PRE_DL_BEACON_8821C BIT(3)\n\n#define BIT_SHIFT_MBID_BCN_NUM_8821C 0\n#define BIT_MASK_MBID_BCN_NUM_8821C 0x7\n#define BIT_MBID_BCN_NUM_8821C(x)                                              \\\n\t(((x) & BIT_MASK_MBID_BCN_NUM_8821C) << BIT_SHIFT_MBID_BCN_NUM_8821C)\n#define BITS_MBID_BCN_NUM_8821C                                                \\\n\t(BIT_MASK_MBID_BCN_NUM_8821C << BIT_SHIFT_MBID_BCN_NUM_8821C)\n#define BIT_CLEAR_MBID_BCN_NUM_8821C(x) ((x) & (~BITS_MBID_BCN_NUM_8821C))\n#define BIT_GET_MBID_BCN_NUM_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_MBID_BCN_NUM_8821C) & BIT_MASK_MBID_BCN_NUM_8821C)\n#define BIT_SET_MBID_BCN_NUM_8821C(x, v)                                       \\\n\t(BIT_CLEAR_MBID_BCN_NUM_8821C(x) | BIT_MBID_BCN_NUM_8821C(v))\n\n/* 2 REG_DUAL_TSF_RST_8821C */\n#define BIT_FREECNT_RST_8821C BIT(5)\n#define BIT_TSFTR_CLI3_RST_8821C BIT(4)\n#define BIT_TSFTR_CLI2_RST_8821C BIT(3)\n#define BIT_TSFTR_CLI1_RST_8821C BIT(2)\n#define BIT_TSFTR_CLI0_RST_8821C BIT(1)\n#define BIT_TSFTR_RST_8821C BIT(0)\n\n/* 2 REG_MBSSID_BCN_SPACE_8821C */\n\n#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C 28\n#define BIT_MASK_BCN_TIMER_SEL_FWRD_8821C 0x7\n#define BIT_BCN_TIMER_SEL_FWRD_8821C(x)                                        \\\n\t(((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8821C)                             \\\n\t << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C)\n#define BITS_BCN_TIMER_SEL_FWRD_8821C                                          \\\n\t(BIT_MASK_BCN_TIMER_SEL_FWRD_8821C                                     \\\n\t << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C)\n#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8821C(x)                                  \\\n\t((x) & (~BITS_BCN_TIMER_SEL_FWRD_8821C))\n#define BIT_GET_BCN_TIMER_SEL_FWRD_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C) &                         \\\n\t BIT_MASK_BCN_TIMER_SEL_FWRD_8821C)\n#define BIT_SET_BCN_TIMER_SEL_FWRD_8821C(x, v)                                 \\\n\t(BIT_CLEAR_BCN_TIMER_SEL_FWRD_8821C(x) |                               \\\n\t BIT_BCN_TIMER_SEL_FWRD_8821C(v))\n\n#define BIT_SHIFT_BCN_SPACE_CLINT0_8821C 16\n#define BIT_MASK_BCN_SPACE_CLINT0_8821C 0xfff\n#define BIT_BCN_SPACE_CLINT0_8821C(x)                                          \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT0_8821C)                               \\\n\t << BIT_SHIFT_BCN_SPACE_CLINT0_8821C)\n#define BITS_BCN_SPACE_CLINT0_8821C                                            \\\n\t(BIT_MASK_BCN_SPACE_CLINT0_8821C << BIT_SHIFT_BCN_SPACE_CLINT0_8821C)\n#define BIT_CLEAR_BCN_SPACE_CLINT0_8821C(x)                                    \\\n\t((x) & (~BITS_BCN_SPACE_CLINT0_8821C))\n#define BIT_GET_BCN_SPACE_CLINT0_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8821C) &                           \\\n\t BIT_MASK_BCN_SPACE_CLINT0_8821C)\n#define BIT_SET_BCN_SPACE_CLINT0_8821C(x, v)                                   \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT0_8821C(x) | BIT_BCN_SPACE_CLINT0_8821C(v))\n\n#define BIT_SHIFT_BCN_SPACE0_8821C 0\n#define BIT_MASK_BCN_SPACE0_8821C 0xffff\n#define BIT_BCN_SPACE0_8821C(x)                                                \\\n\t(((x) & BIT_MASK_BCN_SPACE0_8821C) << BIT_SHIFT_BCN_SPACE0_8821C)\n#define BITS_BCN_SPACE0_8821C                                                  \\\n\t(BIT_MASK_BCN_SPACE0_8821C << BIT_SHIFT_BCN_SPACE0_8821C)\n#define BIT_CLEAR_BCN_SPACE0_8821C(x) ((x) & (~BITS_BCN_SPACE0_8821C))\n#define BIT_GET_BCN_SPACE0_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE0_8821C) & BIT_MASK_BCN_SPACE0_8821C)\n#define BIT_SET_BCN_SPACE0_8821C(x, v)                                         \\\n\t(BIT_CLEAR_BCN_SPACE0_8821C(x) | BIT_BCN_SPACE0_8821C(v))\n\n/* 2 REG_DRVERLYINT_8821C */\n\n#define BIT_SHIFT_DRVERLYITV_8821C 0\n#define BIT_MASK_DRVERLYITV_8821C 0xff\n#define BIT_DRVERLYITV_8821C(x)                                                \\\n\t(((x) & BIT_MASK_DRVERLYITV_8821C) << BIT_SHIFT_DRVERLYITV_8821C)\n#define BITS_DRVERLYITV_8821C                                                  \\\n\t(BIT_MASK_DRVERLYITV_8821C << BIT_SHIFT_DRVERLYITV_8821C)\n#define BIT_CLEAR_DRVERLYITV_8821C(x) ((x) & (~BITS_DRVERLYITV_8821C))\n#define BIT_GET_DRVERLYITV_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DRVERLYITV_8821C) & BIT_MASK_DRVERLYITV_8821C)\n#define BIT_SET_DRVERLYITV_8821C(x, v)                                         \\\n\t(BIT_CLEAR_DRVERLYITV_8821C(x) | BIT_DRVERLYITV_8821C(v))\n\n/* 2 REG_BCNDMATIM_8821C */\n\n#define BIT_SHIFT_BCNDMATIM_8821C 0\n#define BIT_MASK_BCNDMATIM_8821C 0xff\n#define BIT_BCNDMATIM_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_BCNDMATIM_8821C) << BIT_SHIFT_BCNDMATIM_8821C)\n#define BITS_BCNDMATIM_8821C                                                   \\\n\t(BIT_MASK_BCNDMATIM_8821C << BIT_SHIFT_BCNDMATIM_8821C)\n#define BIT_CLEAR_BCNDMATIM_8821C(x) ((x) & (~BITS_BCNDMATIM_8821C))\n#define BIT_GET_BCNDMATIM_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNDMATIM_8821C) & BIT_MASK_BCNDMATIM_8821C)\n#define BIT_SET_BCNDMATIM_8821C(x, v)                                          \\\n\t(BIT_CLEAR_BCNDMATIM_8821C(x) | BIT_BCNDMATIM_8821C(v))\n\n/* 2 REG_ATIMWND_8821C */\n\n#define BIT_SHIFT_ATIMWND0_8821C 0\n#define BIT_MASK_ATIMWND0_8821C 0xffff\n#define BIT_ATIMWND0_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND0_8821C) << BIT_SHIFT_ATIMWND0_8821C)\n#define BITS_ATIMWND0_8821C                                                    \\\n\t(BIT_MASK_ATIMWND0_8821C << BIT_SHIFT_ATIMWND0_8821C)\n#define BIT_CLEAR_ATIMWND0_8821C(x) ((x) & (~BITS_ATIMWND0_8821C))\n#define BIT_GET_ATIMWND0_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND0_8821C) & BIT_MASK_ATIMWND0_8821C)\n#define BIT_SET_ATIMWND0_8821C(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND0_8821C(x) | BIT_ATIMWND0_8821C(v))\n\n/* 2 REG_USTIME_TSF_8821C */\n\n#define BIT_SHIFT_USTIME_TSF_V1_8821C 0\n#define BIT_MASK_USTIME_TSF_V1_8821C 0xff\n#define BIT_USTIME_TSF_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_USTIME_TSF_V1_8821C) << BIT_SHIFT_USTIME_TSF_V1_8821C)\n#define BITS_USTIME_TSF_V1_8821C                                               \\\n\t(BIT_MASK_USTIME_TSF_V1_8821C << BIT_SHIFT_USTIME_TSF_V1_8821C)\n#define BIT_CLEAR_USTIME_TSF_V1_8821C(x) ((x) & (~BITS_USTIME_TSF_V1_8821C))\n#define BIT_GET_USTIME_TSF_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_USTIME_TSF_V1_8821C) & BIT_MASK_USTIME_TSF_V1_8821C)\n#define BIT_SET_USTIME_TSF_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_USTIME_TSF_V1_8821C(x) | BIT_USTIME_TSF_V1_8821C(v))\n\n/* 2 REG_BCN_MAX_ERR_8821C */\n\n#define BIT_SHIFT_BCN_MAX_ERR_8821C 0\n#define BIT_MASK_BCN_MAX_ERR_8821C 0xff\n#define BIT_BCN_MAX_ERR_8821C(x)                                               \\\n\t(((x) & BIT_MASK_BCN_MAX_ERR_8821C) << BIT_SHIFT_BCN_MAX_ERR_8821C)\n#define BITS_BCN_MAX_ERR_8821C                                                 \\\n\t(BIT_MASK_BCN_MAX_ERR_8821C << BIT_SHIFT_BCN_MAX_ERR_8821C)\n#define BIT_CLEAR_BCN_MAX_ERR_8821C(x) ((x) & (~BITS_BCN_MAX_ERR_8821C))\n#define BIT_GET_BCN_MAX_ERR_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_BCN_MAX_ERR_8821C) & BIT_MASK_BCN_MAX_ERR_8821C)\n#define BIT_SET_BCN_MAX_ERR_8821C(x, v)                                        \\\n\t(BIT_CLEAR_BCN_MAX_ERR_8821C(x) | BIT_BCN_MAX_ERR_8821C(v))\n\n/* 2 REG_RXTSF_OFFSET_CCK_8821C */\n\n#define BIT_SHIFT_CCK_RXTSF_OFFSET_8821C 0\n#define BIT_MASK_CCK_RXTSF_OFFSET_8821C 0xff\n#define BIT_CCK_RXTSF_OFFSET_8821C(x)                                          \\\n\t(((x) & BIT_MASK_CCK_RXTSF_OFFSET_8821C)                               \\\n\t << BIT_SHIFT_CCK_RXTSF_OFFSET_8821C)\n#define BITS_CCK_RXTSF_OFFSET_8821C                                            \\\n\t(BIT_MASK_CCK_RXTSF_OFFSET_8821C << BIT_SHIFT_CCK_RXTSF_OFFSET_8821C)\n#define BIT_CLEAR_CCK_RXTSF_OFFSET_8821C(x)                                    \\\n\t((x) & (~BITS_CCK_RXTSF_OFFSET_8821C))\n#define BIT_GET_CCK_RXTSF_OFFSET_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8821C) &                           \\\n\t BIT_MASK_CCK_RXTSF_OFFSET_8821C)\n#define BIT_SET_CCK_RXTSF_OFFSET_8821C(x, v)                                   \\\n\t(BIT_CLEAR_CCK_RXTSF_OFFSET_8821C(x) | BIT_CCK_RXTSF_OFFSET_8821C(v))\n\n/* 2 REG_RXTSF_OFFSET_OFDM_8821C */\n\n#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C 0\n#define BIT_MASK_OFDM_RXTSF_OFFSET_8821C 0xff\n#define BIT_OFDM_RXTSF_OFFSET_8821C(x)                                         \\\n\t(((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8821C)                              \\\n\t << BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C)\n#define BITS_OFDM_RXTSF_OFFSET_8821C                                           \\\n\t(BIT_MASK_OFDM_RXTSF_OFFSET_8821C << BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C)\n#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8821C(x)                                   \\\n\t((x) & (~BITS_OFDM_RXTSF_OFFSET_8821C))\n#define BIT_GET_OFDM_RXTSF_OFFSET_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C) &                          \\\n\t BIT_MASK_OFDM_RXTSF_OFFSET_8821C)\n#define BIT_SET_OFDM_RXTSF_OFFSET_8821C(x, v)                                  \\\n\t(BIT_CLEAR_OFDM_RXTSF_OFFSET_8821C(x) | BIT_OFDM_RXTSF_OFFSET_8821C(v))\n\n/* 2 REG_TSFTR_8821C */\n\n#define BIT_SHIFT_TSF_TIMER_V1_8821C 0\n#define BIT_MASK_TSF_TIMER_V1_8821C 0xffffffffL\n#define BIT_TSF_TIMER_V1_8821C(x)                                              \\\n\t(((x) & BIT_MASK_TSF_TIMER_V1_8821C) << BIT_SHIFT_TSF_TIMER_V1_8821C)\n#define BITS_TSF_TIMER_V1_8821C                                                \\\n\t(BIT_MASK_TSF_TIMER_V1_8821C << BIT_SHIFT_TSF_TIMER_V1_8821C)\n#define BIT_CLEAR_TSF_TIMER_V1_8821C(x) ((x) & (~BITS_TSF_TIMER_V1_8821C))\n#define BIT_GET_TSF_TIMER_V1_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_TSF_TIMER_V1_8821C) & BIT_MASK_TSF_TIMER_V1_8821C)\n#define BIT_SET_TSF_TIMER_V1_8821C(x, v)                                       \\\n\t(BIT_CLEAR_TSF_TIMER_V1_8821C(x) | BIT_TSF_TIMER_V1_8821C(v))\n\n/* 2 REG_TSFTR_1_8821C */\n\n#define BIT_SHIFT_TSF_TIMER_V2_8821C 0\n#define BIT_MASK_TSF_TIMER_V2_8821C 0xffffffffL\n#define BIT_TSF_TIMER_V2_8821C(x)                                              \\\n\t(((x) & BIT_MASK_TSF_TIMER_V2_8821C) << BIT_SHIFT_TSF_TIMER_V2_8821C)\n#define BITS_TSF_TIMER_V2_8821C                                                \\\n\t(BIT_MASK_TSF_TIMER_V2_8821C << BIT_SHIFT_TSF_TIMER_V2_8821C)\n#define BIT_CLEAR_TSF_TIMER_V2_8821C(x) ((x) & (~BITS_TSF_TIMER_V2_8821C))\n#define BIT_GET_TSF_TIMER_V2_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_TSF_TIMER_V2_8821C) & BIT_MASK_TSF_TIMER_V2_8821C)\n#define BIT_SET_TSF_TIMER_V2_8821C(x, v)                                       \\\n\t(BIT_CLEAR_TSF_TIMER_V2_8821C(x) | BIT_TSF_TIMER_V2_8821C(v))\n\n/* 2 REG_FREERUN_CNT_8821C */\n\n#define BIT_SHIFT_FREERUN_CNT_V1_8821C 0\n#define BIT_MASK_FREERUN_CNT_V1_8821C 0xffffffffL\n#define BIT_FREERUN_CNT_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_FREERUN_CNT_V1_8821C)                                 \\\n\t << BIT_SHIFT_FREERUN_CNT_V1_8821C)\n#define BITS_FREERUN_CNT_V1_8821C                                              \\\n\t(BIT_MASK_FREERUN_CNT_V1_8821C << BIT_SHIFT_FREERUN_CNT_V1_8821C)\n#define BIT_CLEAR_FREERUN_CNT_V1_8821C(x) ((x) & (~BITS_FREERUN_CNT_V1_8821C))\n#define BIT_GET_FREERUN_CNT_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_FREERUN_CNT_V1_8821C) &                             \\\n\t BIT_MASK_FREERUN_CNT_V1_8821C)\n#define BIT_SET_FREERUN_CNT_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_FREERUN_CNT_V1_8821C(x) | BIT_FREERUN_CNT_V1_8821C(v))\n\n/* 2 REG_FREERUN_CNT_1_8821C */\n\n#define BIT_SHIFT_FREERUN_CNT_V2_8821C 0\n#define BIT_MASK_FREERUN_CNT_V2_8821C 0xffffffffL\n#define BIT_FREERUN_CNT_V2_8821C(x)                                            \\\n\t(((x) & BIT_MASK_FREERUN_CNT_V2_8821C)                                 \\\n\t << BIT_SHIFT_FREERUN_CNT_V2_8821C)\n#define BITS_FREERUN_CNT_V2_8821C                                              \\\n\t(BIT_MASK_FREERUN_CNT_V2_8821C << BIT_SHIFT_FREERUN_CNT_V2_8821C)\n#define BIT_CLEAR_FREERUN_CNT_V2_8821C(x) ((x) & (~BITS_FREERUN_CNT_V2_8821C))\n#define BIT_GET_FREERUN_CNT_V2_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_FREERUN_CNT_V2_8821C) &                             \\\n\t BIT_MASK_FREERUN_CNT_V2_8821C)\n#define BIT_SET_FREERUN_CNT_V2_8821C(x, v)                                     \\\n\t(BIT_CLEAR_FREERUN_CNT_V2_8821C(x) | BIT_FREERUN_CNT_V2_8821C(v))\n\n/* 2 REG_ATIMWND1_V1_8821C */\n\n#define BIT_SHIFT_ATIMWND1_V1_8821C 0\n#define BIT_MASK_ATIMWND1_V1_8821C 0xff\n#define BIT_ATIMWND1_V1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_ATIMWND1_V1_8821C) << BIT_SHIFT_ATIMWND1_V1_8821C)\n#define BITS_ATIMWND1_V1_8821C                                                 \\\n\t(BIT_MASK_ATIMWND1_V1_8821C << BIT_SHIFT_ATIMWND1_V1_8821C)\n#define BIT_CLEAR_ATIMWND1_V1_8821C(x) ((x) & (~BITS_ATIMWND1_V1_8821C))\n#define BIT_GET_ATIMWND1_V1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_ATIMWND1_V1_8821C) & BIT_MASK_ATIMWND1_V1_8821C)\n#define BIT_SET_ATIMWND1_V1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_ATIMWND1_V1_8821C(x) | BIT_ATIMWND1_V1_8821C(v))\n\n/* 2 REG_TBTT_PROHIBIT_INFRA_8821C */\n\n#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C 0\n#define BIT_MASK_TBTT_PROHIBIT_INFRA_8821C 0xff\n#define BIT_TBTT_PROHIBIT_INFRA_8821C(x)                                       \\\n\t(((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8821C)                            \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C)\n#define BITS_TBTT_PROHIBIT_INFRA_8821C                                         \\\n\t(BIT_MASK_TBTT_PROHIBIT_INFRA_8821C                                    \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C)\n#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8821C(x)                                 \\\n\t((x) & (~BITS_TBTT_PROHIBIT_INFRA_8821C))\n#define BIT_GET_TBTT_PROHIBIT_INFRA_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C) &                        \\\n\t BIT_MASK_TBTT_PROHIBIT_INFRA_8821C)\n#define BIT_SET_TBTT_PROHIBIT_INFRA_8821C(x, v)                                \\\n\t(BIT_CLEAR_TBTT_PROHIBIT_INFRA_8821C(x) |                              \\\n\t BIT_TBTT_PROHIBIT_INFRA_8821C(v))\n\n/* 2 REG_CTWND_8821C */\n\n#define BIT_SHIFT_CTWND_8821C 0\n#define BIT_MASK_CTWND_8821C 0xff\n#define BIT_CTWND_8821C(x)                                                     \\\n\t(((x) & BIT_MASK_CTWND_8821C) << BIT_SHIFT_CTWND_8821C)\n#define BITS_CTWND_8821C (BIT_MASK_CTWND_8821C << BIT_SHIFT_CTWND_8821C)\n#define BIT_CLEAR_CTWND_8821C(x) ((x) & (~BITS_CTWND_8821C))\n#define BIT_GET_CTWND_8821C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CTWND_8821C) & BIT_MASK_CTWND_8821C)\n#define BIT_SET_CTWND_8821C(x, v)                                              \\\n\t(BIT_CLEAR_CTWND_8821C(x) | BIT_CTWND_8821C(v))\n\n/* 2 REG_BCNIVLCUNT_8821C */\n\n#define BIT_SHIFT_BCNIVLCUNT_8821C 0\n#define BIT_MASK_BCNIVLCUNT_8821C 0x7f\n#define BIT_BCNIVLCUNT_8821C(x)                                                \\\n\t(((x) & BIT_MASK_BCNIVLCUNT_8821C) << BIT_SHIFT_BCNIVLCUNT_8821C)\n#define BITS_BCNIVLCUNT_8821C                                                  \\\n\t(BIT_MASK_BCNIVLCUNT_8821C << BIT_SHIFT_BCNIVLCUNT_8821C)\n#define BIT_CLEAR_BCNIVLCUNT_8821C(x) ((x) & (~BITS_BCNIVLCUNT_8821C))\n#define BIT_GET_BCNIVLCUNT_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BCNIVLCUNT_8821C) & BIT_MASK_BCNIVLCUNT_8821C)\n#define BIT_SET_BCNIVLCUNT_8821C(x, v)                                         \\\n\t(BIT_CLEAR_BCNIVLCUNT_8821C(x) | BIT_BCNIVLCUNT_8821C(v))\n\n/* 2 REG_BCNDROPCTRL_8821C */\n#define BIT_BEACON_DROP_EN_8821C BIT(7)\n\n#define BIT_SHIFT_BEACON_DROP_IVL_8821C 0\n#define BIT_MASK_BEACON_DROP_IVL_8821C 0x7f\n#define BIT_BEACON_DROP_IVL_8821C(x)                                           \\\n\t(((x) & BIT_MASK_BEACON_DROP_IVL_8821C)                                \\\n\t << BIT_SHIFT_BEACON_DROP_IVL_8821C)\n#define BITS_BEACON_DROP_IVL_8821C                                             \\\n\t(BIT_MASK_BEACON_DROP_IVL_8821C << BIT_SHIFT_BEACON_DROP_IVL_8821C)\n#define BIT_CLEAR_BEACON_DROP_IVL_8821C(x) ((x) & (~BITS_BEACON_DROP_IVL_8821C))\n#define BIT_GET_BEACON_DROP_IVL_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_BEACON_DROP_IVL_8821C) &                            \\\n\t BIT_MASK_BEACON_DROP_IVL_8821C)\n#define BIT_SET_BEACON_DROP_IVL_8821C(x, v)                                    \\\n\t(BIT_CLEAR_BEACON_DROP_IVL_8821C(x) | BIT_BEACON_DROP_IVL_8821C(v))\n\n/* 2 REG_HGQ_TIMEOUT_PERIOD_8821C */\n\n#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C 0\n#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C 0xff\n#define BIT_HGQ_TIMEOUT_PERIOD_8821C(x)                                        \\\n\t(((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C)                             \\\n\t << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C)\n#define BITS_HGQ_TIMEOUT_PERIOD_8821C                                          \\\n\t(BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C                                     \\\n\t << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C)\n#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8821C(x)                                  \\\n\t((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8821C))\n#define BIT_GET_HGQ_TIMEOUT_PERIOD_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C) &                         \\\n\t BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C)\n#define BIT_SET_HGQ_TIMEOUT_PERIOD_8821C(x, v)                                 \\\n\t(BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8821C(x) |                               \\\n\t BIT_HGQ_TIMEOUT_PERIOD_8821C(v))\n\n/* 2 REG_TXCMD_TIMEOUT_PERIOD_8821C */\n\n#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C 0\n#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C 0xff\n#define BIT_TXCMD_TIMEOUT_PERIOD_8821C(x)                                      \\\n\t(((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C)                           \\\n\t << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C)\n#define BITS_TXCMD_TIMEOUT_PERIOD_8821C                                        \\\n\t(BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C                                   \\\n\t << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C)\n#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8821C(x)                                \\\n\t((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8821C))\n#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C) &                       \\\n\t BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C)\n#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8821C(x, v)                               \\\n\t(BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8821C(x) |                             \\\n\t BIT_TXCMD_TIMEOUT_PERIOD_8821C(v))\n\n/* 2 REG_MISC_CTRL_8821C */\n#define BIT_AUTO_SYNC_BY_TBTT_8821C BIT(6)\n#define BIT_DIS_TRX_CAL_BCN_8821C BIT(5)\n#define BIT_DIS_TX_CAL_TBTT_8821C BIT(4)\n#define BIT_EN_FREECNT_8821C BIT(3)\n#define BIT_BCN_AGGRESSION_8821C BIT(2)\n\n#define BIT_SHIFT_DIS_SECONDARY_CCA_8821C 0\n#define BIT_MASK_DIS_SECONDARY_CCA_8821C 0x3\n#define BIT_DIS_SECONDARY_CCA_8821C(x)                                         \\\n\t(((x) & BIT_MASK_DIS_SECONDARY_CCA_8821C)                              \\\n\t << BIT_SHIFT_DIS_SECONDARY_CCA_8821C)\n#define BITS_DIS_SECONDARY_CCA_8821C                                           \\\n\t(BIT_MASK_DIS_SECONDARY_CCA_8821C << BIT_SHIFT_DIS_SECONDARY_CCA_8821C)\n#define BIT_CLEAR_DIS_SECONDARY_CCA_8821C(x)                                   \\\n\t((x) & (~BITS_DIS_SECONDARY_CCA_8821C))\n#define BIT_GET_DIS_SECONDARY_CCA_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8821C) &                          \\\n\t BIT_MASK_DIS_SECONDARY_CCA_8821C)\n#define BIT_SET_DIS_SECONDARY_CCA_8821C(x, v)                                  \\\n\t(BIT_CLEAR_DIS_SECONDARY_CCA_8821C(x) | BIT_DIS_SECONDARY_CCA_8821C(v))\n\n/* 2 REG_BCN_CTRL_CLINT1_8821C */\n#define BIT_CLI1_DIS_RX_BSSID_FIT_8821C BIT(6)\n#define BIT_CLI1_DIS_TSF_UDT_8821C BIT(4)\n#define BIT_CLI1_EN_BCN_FUNCTION_8821C BIT(3)\n#define BIT_CLI1_EN_RXBCN_RPT_8821C BIT(2)\n#define BIT_CLI1_ENP2P_CTWINDOW_8821C BIT(1)\n#define BIT_CLI1_ENP2P_BCNQ_AREA_8821C BIT(0)\n\n/* 2 REG_BCN_CTRL_CLINT2_8821C */\n#define BIT_CLI2_DIS_RX_BSSID_FIT_8821C BIT(6)\n#define BIT_CLI2_DIS_TSF_UDT_8821C BIT(4)\n#define BIT_CLI2_EN_BCN_FUNCTION_8821C BIT(3)\n#define BIT_CLI2_EN_RXBCN_RPT_8821C BIT(2)\n#define BIT_CLI2_ENP2P_CTWINDOW_8821C BIT(1)\n#define BIT_CLI2_ENP2P_BCNQ_AREA_8821C BIT(0)\n\n/* 2 REG_BCN_CTRL_CLINT3_8821C */\n#define BIT_CLI3_DIS_RX_BSSID_FIT_8821C BIT(6)\n#define BIT_CLI3_DIS_TSF_UDT_8821C BIT(4)\n#define BIT_CLI3_EN_BCN_FUNCTION_8821C BIT(3)\n#define BIT_CLI3_EN_RXBCN_RPT_8821C BIT(2)\n#define BIT_CLI3_ENP2P_CTWINDOW_8821C BIT(1)\n#define BIT_CLI3_ENP2P_BCNQ_AREA_8821C BIT(0)\n\n/* 2 REG_EXTEND_CTRL_8821C */\n#define BIT_EN_TSFBIT32_RST_P2P2_8821C BIT(5)\n#define BIT_EN_TSFBIT32_RST_P2P1_8821C BIT(4)\n\n#define BIT_SHIFT_PORT_SEL_8821C 0\n#define BIT_MASK_PORT_SEL_8821C 0x7\n#define BIT_PORT_SEL_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_PORT_SEL_8821C) << BIT_SHIFT_PORT_SEL_8821C)\n#define BITS_PORT_SEL_8821C                                                    \\\n\t(BIT_MASK_PORT_SEL_8821C << BIT_SHIFT_PORT_SEL_8821C)\n#define BIT_CLEAR_PORT_SEL_8821C(x) ((x) & (~BITS_PORT_SEL_8821C))\n#define BIT_GET_PORT_SEL_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_PORT_SEL_8821C) & BIT_MASK_PORT_SEL_8821C)\n#define BIT_SET_PORT_SEL_8821C(x, v)                                           \\\n\t(BIT_CLEAR_PORT_SEL_8821C(x) | BIT_PORT_SEL_8821C(v))\n\n/* 2 REG_P2PPS1_SPEC_STATE_8821C */\n#define BIT_P2P1_SPEC_POWER_STATE_8821C BIT(7)\n#define BIT_P2P1_SPEC_CTWINDOW_ON_8821C BIT(6)\n#define BIT_P2P1_SPEC_BCN_AREA_ON_8821C BIT(5)\n#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8821C BIT(4)\n#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8821C BIT(3)\n#define BIT_P2P1_SPEC_FORCE_DOZE1_8821C BIT(2)\n#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8821C BIT(1)\n#define BIT_P2P1_SPEC_FORCE_DOZE0_8821C BIT(0)\n\n/* 2 REG_P2PPS1_STATE_8821C */\n#define BIT_P2P1_POWER_STATE_8821C BIT(7)\n#define BIT_P2P1_CTWINDOW_ON_8821C BIT(6)\n#define BIT_P2P1_BEACON_AREA_ON_8821C BIT(5)\n#define BIT_P2P1_CTWIN_EARLY_DISTX_8821C BIT(4)\n#define BIT_P2P1_NOA1_OFF_PERIOD_8821C BIT(3)\n#define BIT_P2P1_FORCE_DOZE1_8821C BIT(2)\n#define BIT_P2P1_NOA0_OFF_PERIOD_8821C BIT(1)\n#define BIT_P2P1_FORCE_DOZE0_8821C BIT(0)\n\n/* 2 REG_P2PPS2_SPEC_STATE_8821C */\n#define BIT_P2P2_SPEC_POWER_STATE_8821C BIT(7)\n#define BIT_P2P2_SPEC_CTWINDOW_ON_8821C BIT(6)\n#define BIT_P2P2_SPEC_BCN_AREA_ON_8821C BIT(5)\n#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8821C BIT(4)\n#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8821C BIT(3)\n#define BIT_P2P2_SPEC_FORCE_DOZE1_8821C BIT(2)\n#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8821C BIT(1)\n#define BIT_P2P2_SPEC_FORCE_DOZE0_8821C BIT(0)\n\n/* 2 REG_P2PPS2_STATE_8821C */\n#define BIT_P2P2_POWER_STATE_8821C BIT(7)\n#define BIT_P2P2_CTWINDOW_ON_8821C BIT(6)\n#define BIT_P2P2_BEACON_AREA_ON_8821C BIT(5)\n#define BIT_P2P2_CTWIN_EARLY_DISTX_8821C BIT(4)\n#define BIT_P2P2_NOA1_OFF_PERIOD_8821C BIT(3)\n#define BIT_P2P2_FORCE_DOZE1_8821C BIT(2)\n#define BIT_P2P2_NOA0_OFF_PERIOD_8821C BIT(1)\n#define BIT_P2P2_FORCE_DOZE0_8821C BIT(0)\n\n/* 2 REG_PS_TIMER0_8821C */\n\n#define BIT_SHIFT_PSTIMER0_INT_8821C 5\n#define BIT_MASK_PSTIMER0_INT_8821C 0x7ffffff\n#define BIT_PSTIMER0_INT_8821C(x)                                              \\\n\t(((x) & BIT_MASK_PSTIMER0_INT_8821C) << BIT_SHIFT_PSTIMER0_INT_8821C)\n#define BITS_PSTIMER0_INT_8821C                                                \\\n\t(BIT_MASK_PSTIMER0_INT_8821C << BIT_SHIFT_PSTIMER0_INT_8821C)\n#define BIT_CLEAR_PSTIMER0_INT_8821C(x) ((x) & (~BITS_PSTIMER0_INT_8821C))\n#define BIT_GET_PSTIMER0_INT_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_PSTIMER0_INT_8821C) & BIT_MASK_PSTIMER0_INT_8821C)\n#define BIT_SET_PSTIMER0_INT_8821C(x, v)                                       \\\n\t(BIT_CLEAR_PSTIMER0_INT_8821C(x) | BIT_PSTIMER0_INT_8821C(v))\n\n/* 2 REG_PS_TIMER1_8821C */\n\n#define BIT_SHIFT_PSTIMER1_INT_8821C 5\n#define BIT_MASK_PSTIMER1_INT_8821C 0x7ffffff\n#define BIT_PSTIMER1_INT_8821C(x)                                              \\\n\t(((x) & BIT_MASK_PSTIMER1_INT_8821C) << BIT_SHIFT_PSTIMER1_INT_8821C)\n#define BITS_PSTIMER1_INT_8821C                                                \\\n\t(BIT_MASK_PSTIMER1_INT_8821C << BIT_SHIFT_PSTIMER1_INT_8821C)\n#define BIT_CLEAR_PSTIMER1_INT_8821C(x) ((x) & (~BITS_PSTIMER1_INT_8821C))\n#define BIT_GET_PSTIMER1_INT_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_PSTIMER1_INT_8821C) & BIT_MASK_PSTIMER1_INT_8821C)\n#define BIT_SET_PSTIMER1_INT_8821C(x, v)                                       \\\n\t(BIT_CLEAR_PSTIMER1_INT_8821C(x) | BIT_PSTIMER1_INT_8821C(v))\n\n/* 2 REG_PS_TIMER2_8821C */\n\n#define BIT_SHIFT_PSTIMER2_INT_8821C 5\n#define BIT_MASK_PSTIMER2_INT_8821C 0x7ffffff\n#define BIT_PSTIMER2_INT_8821C(x)                                              \\\n\t(((x) & BIT_MASK_PSTIMER2_INT_8821C) << BIT_SHIFT_PSTIMER2_INT_8821C)\n#define BITS_PSTIMER2_INT_8821C                                                \\\n\t(BIT_MASK_PSTIMER2_INT_8821C << BIT_SHIFT_PSTIMER2_INT_8821C)\n#define BIT_CLEAR_PSTIMER2_INT_8821C(x) ((x) & (~BITS_PSTIMER2_INT_8821C))\n#define BIT_GET_PSTIMER2_INT_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_PSTIMER2_INT_8821C) & BIT_MASK_PSTIMER2_INT_8821C)\n#define BIT_SET_PSTIMER2_INT_8821C(x, v)                                       \\\n\t(BIT_CLEAR_PSTIMER2_INT_8821C(x) | BIT_PSTIMER2_INT_8821C(v))\n\n/* 2 REG_TBTT_CTN_AREA_8821C */\n\n#define BIT_SHIFT_TBTT_CTN_AREA_8821C 0\n#define BIT_MASK_TBTT_CTN_AREA_8821C 0xff\n#define BIT_TBTT_CTN_AREA_8821C(x)                                             \\\n\t(((x) & BIT_MASK_TBTT_CTN_AREA_8821C) << BIT_SHIFT_TBTT_CTN_AREA_8821C)\n#define BITS_TBTT_CTN_AREA_8821C                                               \\\n\t(BIT_MASK_TBTT_CTN_AREA_8821C << BIT_SHIFT_TBTT_CTN_AREA_8821C)\n#define BIT_CLEAR_TBTT_CTN_AREA_8821C(x) ((x) & (~BITS_TBTT_CTN_AREA_8821C))\n#define BIT_GET_TBTT_CTN_AREA_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TBTT_CTN_AREA_8821C) & BIT_MASK_TBTT_CTN_AREA_8821C)\n#define BIT_SET_TBTT_CTN_AREA_8821C(x, v)                                      \\\n\t(BIT_CLEAR_TBTT_CTN_AREA_8821C(x) | BIT_TBTT_CTN_AREA_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_FORCE_BCN_IFS_8821C */\n\n#define BIT_SHIFT_FORCE_BCN_IFS_8821C 0\n#define BIT_MASK_FORCE_BCN_IFS_8821C 0xff\n#define BIT_FORCE_BCN_IFS_8821C(x)                                             \\\n\t(((x) & BIT_MASK_FORCE_BCN_IFS_8821C) << BIT_SHIFT_FORCE_BCN_IFS_8821C)\n#define BITS_FORCE_BCN_IFS_8821C                                               \\\n\t(BIT_MASK_FORCE_BCN_IFS_8821C << BIT_SHIFT_FORCE_BCN_IFS_8821C)\n#define BIT_CLEAR_FORCE_BCN_IFS_8821C(x) ((x) & (~BITS_FORCE_BCN_IFS_8821C))\n#define BIT_GET_FORCE_BCN_IFS_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_FORCE_BCN_IFS_8821C) & BIT_MASK_FORCE_BCN_IFS_8821C)\n#define BIT_SET_FORCE_BCN_IFS_8821C(x, v)                                      \\\n\t(BIT_CLEAR_FORCE_BCN_IFS_8821C(x) | BIT_FORCE_BCN_IFS_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_TXOP_MIN_8821C */\n\n#define BIT_SHIFT_TXOP_MIN_8821C 0\n#define BIT_MASK_TXOP_MIN_8821C 0x3fff\n#define BIT_TXOP_MIN_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_TXOP_MIN_8821C) << BIT_SHIFT_TXOP_MIN_8821C)\n#define BITS_TXOP_MIN_8821C                                                    \\\n\t(BIT_MASK_TXOP_MIN_8821C << BIT_SHIFT_TXOP_MIN_8821C)\n#define BIT_CLEAR_TXOP_MIN_8821C(x) ((x) & (~BITS_TXOP_MIN_8821C))\n#define BIT_GET_TXOP_MIN_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXOP_MIN_8821C) & BIT_MASK_TXOP_MIN_8821C)\n#define BIT_SET_TXOP_MIN_8821C(x, v)                                           \\\n\t(BIT_CLEAR_TXOP_MIN_8821C(x) | BIT_TXOP_MIN_8821C(v))\n\n/* 2 REG_PRE_BKF_TIME_8821C */\n\n#define BIT_SHIFT_PRE_BKF_TIME_8821C 0\n#define BIT_MASK_PRE_BKF_TIME_8821C 0xff\n#define BIT_PRE_BKF_TIME_8821C(x)                                              \\\n\t(((x) & BIT_MASK_PRE_BKF_TIME_8821C) << BIT_SHIFT_PRE_BKF_TIME_8821C)\n#define BITS_PRE_BKF_TIME_8821C                                                \\\n\t(BIT_MASK_PRE_BKF_TIME_8821C << BIT_SHIFT_PRE_BKF_TIME_8821C)\n#define BIT_CLEAR_PRE_BKF_TIME_8821C(x) ((x) & (~BITS_PRE_BKF_TIME_8821C))\n#define BIT_GET_PRE_BKF_TIME_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_PRE_BKF_TIME_8821C) & BIT_MASK_PRE_BKF_TIME_8821C)\n#define BIT_SET_PRE_BKF_TIME_8821C(x, v)                                       \\\n\t(BIT_CLEAR_PRE_BKF_TIME_8821C(x) | BIT_PRE_BKF_TIME_8821C(v))\n\n/* 2 REG_CROSS_TXOP_CTRL_8821C */\n#define BIT_TXFAIL_BREACK_TXOP_EN_8821C BIT(3)\n#define BIT_DTIM_BYPASS_8821C BIT(2)\n#define BIT_RTS_NAV_TXOP_8821C BIT(1)\n#define BIT_NOT_CROSS_TXOP_8821C BIT(0)\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_ATIMWND2_8821C */\n\n#define BIT_SHIFT_ATIMWND2_8821C 0\n#define BIT_MASK_ATIMWND2_8821C 0xff\n#define BIT_ATIMWND2_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND2_8821C) << BIT_SHIFT_ATIMWND2_8821C)\n#define BITS_ATIMWND2_8821C                                                    \\\n\t(BIT_MASK_ATIMWND2_8821C << BIT_SHIFT_ATIMWND2_8821C)\n#define BIT_CLEAR_ATIMWND2_8821C(x) ((x) & (~BITS_ATIMWND2_8821C))\n#define BIT_GET_ATIMWND2_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND2_8821C) & BIT_MASK_ATIMWND2_8821C)\n#define BIT_SET_ATIMWND2_8821C(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND2_8821C(x) | BIT_ATIMWND2_8821C(v))\n\n/* 2 REG_ATIMWND3_8821C */\n\n#define BIT_SHIFT_ATIMWND3_8821C 0\n#define BIT_MASK_ATIMWND3_8821C 0xff\n#define BIT_ATIMWND3_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND3_8821C) << BIT_SHIFT_ATIMWND3_8821C)\n#define BITS_ATIMWND3_8821C                                                    \\\n\t(BIT_MASK_ATIMWND3_8821C << BIT_SHIFT_ATIMWND3_8821C)\n#define BIT_CLEAR_ATIMWND3_8821C(x) ((x) & (~BITS_ATIMWND3_8821C))\n#define BIT_GET_ATIMWND3_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND3_8821C) & BIT_MASK_ATIMWND3_8821C)\n#define BIT_SET_ATIMWND3_8821C(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND3_8821C(x) | BIT_ATIMWND3_8821C(v))\n\n/* 2 REG_ATIMWND4_8821C */\n\n#define BIT_SHIFT_ATIMWND4_8821C 0\n#define BIT_MASK_ATIMWND4_8821C 0xff\n#define BIT_ATIMWND4_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND4_8821C) << BIT_SHIFT_ATIMWND4_8821C)\n#define BITS_ATIMWND4_8821C                                                    \\\n\t(BIT_MASK_ATIMWND4_8821C << BIT_SHIFT_ATIMWND4_8821C)\n#define BIT_CLEAR_ATIMWND4_8821C(x) ((x) & (~BITS_ATIMWND4_8821C))\n#define BIT_GET_ATIMWND4_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND4_8821C) & BIT_MASK_ATIMWND4_8821C)\n#define BIT_SET_ATIMWND4_8821C(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND4_8821C(x) | BIT_ATIMWND4_8821C(v))\n\n/* 2 REG_ATIMWND5_8821C */\n\n#define BIT_SHIFT_ATIMWND5_8821C 0\n#define BIT_MASK_ATIMWND5_8821C 0xff\n#define BIT_ATIMWND5_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND5_8821C) << BIT_SHIFT_ATIMWND5_8821C)\n#define BITS_ATIMWND5_8821C                                                    \\\n\t(BIT_MASK_ATIMWND5_8821C << BIT_SHIFT_ATIMWND5_8821C)\n#define BIT_CLEAR_ATIMWND5_8821C(x) ((x) & (~BITS_ATIMWND5_8821C))\n#define BIT_GET_ATIMWND5_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND5_8821C) & BIT_MASK_ATIMWND5_8821C)\n#define BIT_SET_ATIMWND5_8821C(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND5_8821C(x) | BIT_ATIMWND5_8821C(v))\n\n/* 2 REG_ATIMWND6_8821C */\n\n#define BIT_SHIFT_ATIMWND6_8821C 0\n#define BIT_MASK_ATIMWND6_8821C 0xff\n#define BIT_ATIMWND6_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND6_8821C) << BIT_SHIFT_ATIMWND6_8821C)\n#define BITS_ATIMWND6_8821C                                                    \\\n\t(BIT_MASK_ATIMWND6_8821C << BIT_SHIFT_ATIMWND6_8821C)\n#define BIT_CLEAR_ATIMWND6_8821C(x) ((x) & (~BITS_ATIMWND6_8821C))\n#define BIT_GET_ATIMWND6_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND6_8821C) & BIT_MASK_ATIMWND6_8821C)\n#define BIT_SET_ATIMWND6_8821C(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND6_8821C(x) | BIT_ATIMWND6_8821C(v))\n\n/* 2 REG_ATIMWND7_8821C */\n\n#define BIT_SHIFT_ATIMWND7_8821C 0\n#define BIT_MASK_ATIMWND7_8821C 0xff\n#define BIT_ATIMWND7_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND7_8821C) << BIT_SHIFT_ATIMWND7_8821C)\n#define BITS_ATIMWND7_8821C                                                    \\\n\t(BIT_MASK_ATIMWND7_8821C << BIT_SHIFT_ATIMWND7_8821C)\n#define BIT_CLEAR_ATIMWND7_8821C(x) ((x) & (~BITS_ATIMWND7_8821C))\n#define BIT_GET_ATIMWND7_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND7_8821C) & BIT_MASK_ATIMWND7_8821C)\n#define BIT_SET_ATIMWND7_8821C(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND7_8821C(x) | BIT_ATIMWND7_8821C(v))\n\n/* 2 REG_ATIMUGT_8821C */\n\n#define BIT_SHIFT_ATIM_URGENT_8821C 0\n#define BIT_MASK_ATIM_URGENT_8821C 0xff\n#define BIT_ATIM_URGENT_8821C(x)                                               \\\n\t(((x) & BIT_MASK_ATIM_URGENT_8821C) << BIT_SHIFT_ATIM_URGENT_8821C)\n#define BITS_ATIM_URGENT_8821C                                                 \\\n\t(BIT_MASK_ATIM_URGENT_8821C << BIT_SHIFT_ATIM_URGENT_8821C)\n#define BIT_CLEAR_ATIM_URGENT_8821C(x) ((x) & (~BITS_ATIM_URGENT_8821C))\n#define BIT_GET_ATIM_URGENT_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_ATIM_URGENT_8821C) & BIT_MASK_ATIM_URGENT_8821C)\n#define BIT_SET_ATIM_URGENT_8821C(x, v)                                        \\\n\t(BIT_CLEAR_ATIM_URGENT_8821C(x) | BIT_ATIM_URGENT_8821C(v))\n\n/* 2 REG_HIQ_NO_LMT_EN_8821C */\n#define BIT_HIQ_NO_LMT_EN_VAP7_8821C BIT(7)\n#define BIT_HIQ_NO_LMT_EN_VAP6_8821C BIT(6)\n#define BIT_HIQ_NO_LMT_EN_VAP5_8821C BIT(5)\n#define BIT_HIQ_NO_LMT_EN_VAP4_8821C BIT(4)\n#define BIT_HIQ_NO_LMT_EN_VAP3_8821C BIT(3)\n#define BIT_HIQ_NO_LMT_EN_VAP2_8821C BIT(2)\n#define BIT_HIQ_NO_LMT_EN_VAP1_8821C BIT(1)\n#define BIT_HIQ_NO_LMT_EN_ROOT_8821C BIT(0)\n\n/* 2 REG_DTIM_COUNTER_ROOT_8821C */\n\n#define BIT_SHIFT_DTIM_COUNT_ROOT_8821C 0\n#define BIT_MASK_DTIM_COUNT_ROOT_8821C 0xff\n#define BIT_DTIM_COUNT_ROOT_8821C(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_ROOT_8821C)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_ROOT_8821C)\n#define BITS_DTIM_COUNT_ROOT_8821C                                             \\\n\t(BIT_MASK_DTIM_COUNT_ROOT_8821C << BIT_SHIFT_DTIM_COUNT_ROOT_8821C)\n#define BIT_CLEAR_DTIM_COUNT_ROOT_8821C(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8821C))\n#define BIT_GET_DTIM_COUNT_ROOT_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8821C) &                            \\\n\t BIT_MASK_DTIM_COUNT_ROOT_8821C)\n#define BIT_SET_DTIM_COUNT_ROOT_8821C(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_ROOT_8821C(x) | BIT_DTIM_COUNT_ROOT_8821C(v))\n\n/* 2 REG_DTIM_COUNTER_VAP1_8821C */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP1_8821C 0\n#define BIT_MASK_DTIM_COUNT_VAP1_8821C 0xff\n#define BIT_DTIM_COUNT_VAP1_8821C(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP1_8821C)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP1_8821C)\n#define BITS_DTIM_COUNT_VAP1_8821C                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP1_8821C << BIT_SHIFT_DTIM_COUNT_VAP1_8821C)\n#define BIT_CLEAR_DTIM_COUNT_VAP1_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8821C))\n#define BIT_GET_DTIM_COUNT_VAP1_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8821C) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP1_8821C)\n#define BIT_SET_DTIM_COUNT_VAP1_8821C(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP1_8821C(x) | BIT_DTIM_COUNT_VAP1_8821C(v))\n\n/* 2 REG_DTIM_COUNTER_VAP2_8821C */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP2_8821C 0\n#define BIT_MASK_DTIM_COUNT_VAP2_8821C 0xff\n#define BIT_DTIM_COUNT_VAP2_8821C(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP2_8821C)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP2_8821C)\n#define BITS_DTIM_COUNT_VAP2_8821C                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP2_8821C << BIT_SHIFT_DTIM_COUNT_VAP2_8821C)\n#define BIT_CLEAR_DTIM_COUNT_VAP2_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8821C))\n#define BIT_GET_DTIM_COUNT_VAP2_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8821C) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP2_8821C)\n#define BIT_SET_DTIM_COUNT_VAP2_8821C(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP2_8821C(x) | BIT_DTIM_COUNT_VAP2_8821C(v))\n\n/* 2 REG_DTIM_COUNTER_VAP3_8821C */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP3_8821C 0\n#define BIT_MASK_DTIM_COUNT_VAP3_8821C 0xff\n#define BIT_DTIM_COUNT_VAP3_8821C(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP3_8821C)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP3_8821C)\n#define BITS_DTIM_COUNT_VAP3_8821C                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP3_8821C << BIT_SHIFT_DTIM_COUNT_VAP3_8821C)\n#define BIT_CLEAR_DTIM_COUNT_VAP3_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8821C))\n#define BIT_GET_DTIM_COUNT_VAP3_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8821C) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP3_8821C)\n#define BIT_SET_DTIM_COUNT_VAP3_8821C(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP3_8821C(x) | BIT_DTIM_COUNT_VAP3_8821C(v))\n\n/* 2 REG_DTIM_COUNTER_VAP4_8821C */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP4_8821C 0\n#define BIT_MASK_DTIM_COUNT_VAP4_8821C 0xff\n#define BIT_DTIM_COUNT_VAP4_8821C(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP4_8821C)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP4_8821C)\n#define BITS_DTIM_COUNT_VAP4_8821C                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP4_8821C << BIT_SHIFT_DTIM_COUNT_VAP4_8821C)\n#define BIT_CLEAR_DTIM_COUNT_VAP4_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8821C))\n#define BIT_GET_DTIM_COUNT_VAP4_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8821C) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP4_8821C)\n#define BIT_SET_DTIM_COUNT_VAP4_8821C(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP4_8821C(x) | BIT_DTIM_COUNT_VAP4_8821C(v))\n\n/* 2 REG_DTIM_COUNTER_VAP5_8821C */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP5_8821C 0\n#define BIT_MASK_DTIM_COUNT_VAP5_8821C 0xff\n#define BIT_DTIM_COUNT_VAP5_8821C(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP5_8821C)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP5_8821C)\n#define BITS_DTIM_COUNT_VAP5_8821C                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP5_8821C << BIT_SHIFT_DTIM_COUNT_VAP5_8821C)\n#define BIT_CLEAR_DTIM_COUNT_VAP5_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8821C))\n#define BIT_GET_DTIM_COUNT_VAP5_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8821C) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP5_8821C)\n#define BIT_SET_DTIM_COUNT_VAP5_8821C(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP5_8821C(x) | BIT_DTIM_COUNT_VAP5_8821C(v))\n\n/* 2 REG_DTIM_COUNTER_VAP6_8821C */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP6_8821C 0\n#define BIT_MASK_DTIM_COUNT_VAP6_8821C 0xff\n#define BIT_DTIM_COUNT_VAP6_8821C(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP6_8821C)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP6_8821C)\n#define BITS_DTIM_COUNT_VAP6_8821C                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP6_8821C << BIT_SHIFT_DTIM_COUNT_VAP6_8821C)\n#define BIT_CLEAR_DTIM_COUNT_VAP6_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8821C))\n#define BIT_GET_DTIM_COUNT_VAP6_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8821C) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP6_8821C)\n#define BIT_SET_DTIM_COUNT_VAP6_8821C(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP6_8821C(x) | BIT_DTIM_COUNT_VAP6_8821C(v))\n\n/* 2 REG_DTIM_COUNTER_VAP7_8821C */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP7_8821C 0\n#define BIT_MASK_DTIM_COUNT_VAP7_8821C 0xff\n#define BIT_DTIM_COUNT_VAP7_8821C(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP7_8821C)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP7_8821C)\n#define BITS_DTIM_COUNT_VAP7_8821C                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP7_8821C << BIT_SHIFT_DTIM_COUNT_VAP7_8821C)\n#define BIT_CLEAR_DTIM_COUNT_VAP7_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8821C))\n#define BIT_GET_DTIM_COUNT_VAP7_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8821C) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP7_8821C)\n#define BIT_SET_DTIM_COUNT_VAP7_8821C(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP7_8821C(x) | BIT_DTIM_COUNT_VAP7_8821C(v))\n\n/* 2 REG_DIS_ATIM_8821C */\n#define BIT_DIS_ATIM_VAP7_8821C BIT(7)\n#define BIT_DIS_ATIM_VAP6_8821C BIT(6)\n#define BIT_DIS_ATIM_VAP5_8821C BIT(5)\n#define BIT_DIS_ATIM_VAP4_8821C BIT(4)\n#define BIT_DIS_ATIM_VAP3_8821C BIT(3)\n#define BIT_DIS_ATIM_VAP2_8821C BIT(2)\n#define BIT_DIS_ATIM_VAP1_8821C BIT(1)\n#define BIT_DIS_ATIM_ROOT_8821C BIT(0)\n\n/* 2 REG_EARLY_128US_8821C */\n\n#define BIT_SHIFT_TSFT_SEL_TIMER1_8821C 3\n#define BIT_MASK_TSFT_SEL_TIMER1_8821C 0x7\n#define BIT_TSFT_SEL_TIMER1_8821C(x)                                           \\\n\t(((x) & BIT_MASK_TSFT_SEL_TIMER1_8821C)                                \\\n\t << BIT_SHIFT_TSFT_SEL_TIMER1_8821C)\n#define BITS_TSFT_SEL_TIMER1_8821C                                             \\\n\t(BIT_MASK_TSFT_SEL_TIMER1_8821C << BIT_SHIFT_TSFT_SEL_TIMER1_8821C)\n#define BIT_CLEAR_TSFT_SEL_TIMER1_8821C(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8821C))\n#define BIT_GET_TSFT_SEL_TIMER1_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8821C) &                            \\\n\t BIT_MASK_TSFT_SEL_TIMER1_8821C)\n#define BIT_SET_TSFT_SEL_TIMER1_8821C(x, v)                                    \\\n\t(BIT_CLEAR_TSFT_SEL_TIMER1_8821C(x) | BIT_TSFT_SEL_TIMER1_8821C(v))\n\n#define BIT_SHIFT_EARLY_128US_8821C 0\n#define BIT_MASK_EARLY_128US_8821C 0x7\n#define BIT_EARLY_128US_8821C(x)                                               \\\n\t(((x) & BIT_MASK_EARLY_128US_8821C) << BIT_SHIFT_EARLY_128US_8821C)\n#define BITS_EARLY_128US_8821C                                                 \\\n\t(BIT_MASK_EARLY_128US_8821C << BIT_SHIFT_EARLY_128US_8821C)\n#define BIT_CLEAR_EARLY_128US_8821C(x) ((x) & (~BITS_EARLY_128US_8821C))\n#define BIT_GET_EARLY_128US_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_EARLY_128US_8821C) & BIT_MASK_EARLY_128US_8821C)\n#define BIT_SET_EARLY_128US_8821C(x, v)                                        \\\n\t(BIT_CLEAR_EARLY_128US_8821C(x) | BIT_EARLY_128US_8821C(v))\n\n/* 2 REG_P2PPS1_CTRL_8821C */\n#define BIT_P2P1_CTW_ALLSTASLEEP_8821C BIT(7)\n#define BIT_P2P1_OFF_DISTX_EN_8821C BIT(6)\n#define BIT_P2P1_PWR_MGT_EN_8821C BIT(5)\n#define BIT_P2P1_NOA1_EN_8821C BIT(2)\n#define BIT_P2P1_NOA0_EN_8821C BIT(1)\n\n/* 2 REG_P2PPS2_CTRL_8821C */\n#define BIT_P2P2_CTW_ALLSTASLEEP_8821C BIT(7)\n#define BIT_P2P2_OFF_DISTX_EN_8821C BIT(6)\n#define BIT_P2P2_PWR_MGT_EN_8821C BIT(5)\n#define BIT_P2P2_NOA1_EN_8821C BIT(2)\n#define BIT_P2P2_NOA0_EN_8821C BIT(1)\n\n/* 2 REG_TIMER0_SRC_SEL_8821C */\n\n#define BIT_SHIFT_SYNC_CLI_SEL_8821C 4\n#define BIT_MASK_SYNC_CLI_SEL_8821C 0x7\n#define BIT_SYNC_CLI_SEL_8821C(x)                                              \\\n\t(((x) & BIT_MASK_SYNC_CLI_SEL_8821C) << BIT_SHIFT_SYNC_CLI_SEL_8821C)\n#define BITS_SYNC_CLI_SEL_8821C                                                \\\n\t(BIT_MASK_SYNC_CLI_SEL_8821C << BIT_SHIFT_SYNC_CLI_SEL_8821C)\n#define BIT_CLEAR_SYNC_CLI_SEL_8821C(x) ((x) & (~BITS_SYNC_CLI_SEL_8821C))\n#define BIT_GET_SYNC_CLI_SEL_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_SYNC_CLI_SEL_8821C) & BIT_MASK_SYNC_CLI_SEL_8821C)\n#define BIT_SET_SYNC_CLI_SEL_8821C(x, v)                                       \\\n\t(BIT_CLEAR_SYNC_CLI_SEL_8821C(x) | BIT_SYNC_CLI_SEL_8821C(v))\n\n#define BIT_SHIFT_TSFT_SEL_TIMER0_8821C 0\n#define BIT_MASK_TSFT_SEL_TIMER0_8821C 0x7\n#define BIT_TSFT_SEL_TIMER0_8821C(x)                                           \\\n\t(((x) & BIT_MASK_TSFT_SEL_TIMER0_8821C)                                \\\n\t << BIT_SHIFT_TSFT_SEL_TIMER0_8821C)\n#define BITS_TSFT_SEL_TIMER0_8821C                                             \\\n\t(BIT_MASK_TSFT_SEL_TIMER0_8821C << BIT_SHIFT_TSFT_SEL_TIMER0_8821C)\n#define BIT_CLEAR_TSFT_SEL_TIMER0_8821C(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8821C))\n#define BIT_GET_TSFT_SEL_TIMER0_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8821C) &                            \\\n\t BIT_MASK_TSFT_SEL_TIMER0_8821C)\n#define BIT_SET_TSFT_SEL_TIMER0_8821C(x, v)                                    \\\n\t(BIT_CLEAR_TSFT_SEL_TIMER0_8821C(x) | BIT_TSFT_SEL_TIMER0_8821C(v))\n\n/* 2 REG_NOA_UNIT_SEL_8821C */\n\n#define BIT_SHIFT_NOA_UNIT2_SEL_8821C 8\n#define BIT_MASK_NOA_UNIT2_SEL_8821C 0x7\n#define BIT_NOA_UNIT2_SEL_8821C(x)                                             \\\n\t(((x) & BIT_MASK_NOA_UNIT2_SEL_8821C) << BIT_SHIFT_NOA_UNIT2_SEL_8821C)\n#define BITS_NOA_UNIT2_SEL_8821C                                               \\\n\t(BIT_MASK_NOA_UNIT2_SEL_8821C << BIT_SHIFT_NOA_UNIT2_SEL_8821C)\n#define BIT_CLEAR_NOA_UNIT2_SEL_8821C(x) ((x) & (~BITS_NOA_UNIT2_SEL_8821C))\n#define BIT_GET_NOA_UNIT2_SEL_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8821C) & BIT_MASK_NOA_UNIT2_SEL_8821C)\n#define BIT_SET_NOA_UNIT2_SEL_8821C(x, v)                                      \\\n\t(BIT_CLEAR_NOA_UNIT2_SEL_8821C(x) | BIT_NOA_UNIT2_SEL_8821C(v))\n\n#define BIT_SHIFT_NOA_UNIT1_SEL_8821C 4\n#define BIT_MASK_NOA_UNIT1_SEL_8821C 0x7\n#define BIT_NOA_UNIT1_SEL_8821C(x)                                             \\\n\t(((x) & BIT_MASK_NOA_UNIT1_SEL_8821C) << BIT_SHIFT_NOA_UNIT1_SEL_8821C)\n#define BITS_NOA_UNIT1_SEL_8821C                                               \\\n\t(BIT_MASK_NOA_UNIT1_SEL_8821C << BIT_SHIFT_NOA_UNIT1_SEL_8821C)\n#define BIT_CLEAR_NOA_UNIT1_SEL_8821C(x) ((x) & (~BITS_NOA_UNIT1_SEL_8821C))\n#define BIT_GET_NOA_UNIT1_SEL_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8821C) & BIT_MASK_NOA_UNIT1_SEL_8821C)\n#define BIT_SET_NOA_UNIT1_SEL_8821C(x, v)                                      \\\n\t(BIT_CLEAR_NOA_UNIT1_SEL_8821C(x) | BIT_NOA_UNIT1_SEL_8821C(v))\n\n#define BIT_SHIFT_NOA_UNIT0_SEL_8821C 0\n#define BIT_MASK_NOA_UNIT0_SEL_8821C 0x7\n#define BIT_NOA_UNIT0_SEL_8821C(x)                                             \\\n\t(((x) & BIT_MASK_NOA_UNIT0_SEL_8821C) << BIT_SHIFT_NOA_UNIT0_SEL_8821C)\n#define BITS_NOA_UNIT0_SEL_8821C                                               \\\n\t(BIT_MASK_NOA_UNIT0_SEL_8821C << BIT_SHIFT_NOA_UNIT0_SEL_8821C)\n#define BIT_CLEAR_NOA_UNIT0_SEL_8821C(x) ((x) & (~BITS_NOA_UNIT0_SEL_8821C))\n#define BIT_GET_NOA_UNIT0_SEL_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8821C) & BIT_MASK_NOA_UNIT0_SEL_8821C)\n#define BIT_SET_NOA_UNIT0_SEL_8821C(x, v)                                      \\\n\t(BIT_CLEAR_NOA_UNIT0_SEL_8821C(x) | BIT_NOA_UNIT0_SEL_8821C(v))\n\n/* 2 REG_P2POFF_DIS_TXTIME_8821C */\n\n#define BIT_SHIFT_P2POFF_DIS_TXTIME_8821C 0\n#define BIT_MASK_P2POFF_DIS_TXTIME_8821C 0xff\n#define BIT_P2POFF_DIS_TXTIME_8821C(x)                                         \\\n\t(((x) & BIT_MASK_P2POFF_DIS_TXTIME_8821C)                              \\\n\t << BIT_SHIFT_P2POFF_DIS_TXTIME_8821C)\n#define BITS_P2POFF_DIS_TXTIME_8821C                                           \\\n\t(BIT_MASK_P2POFF_DIS_TXTIME_8821C << BIT_SHIFT_P2POFF_DIS_TXTIME_8821C)\n#define BIT_CLEAR_P2POFF_DIS_TXTIME_8821C(x)                                   \\\n\t((x) & (~BITS_P2POFF_DIS_TXTIME_8821C))\n#define BIT_GET_P2POFF_DIS_TXTIME_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8821C) &                          \\\n\t BIT_MASK_P2POFF_DIS_TXTIME_8821C)\n#define BIT_SET_P2POFF_DIS_TXTIME_8821C(x, v)                                  \\\n\t(BIT_CLEAR_P2POFF_DIS_TXTIME_8821C(x) | BIT_P2POFF_DIS_TXTIME_8821C(v))\n\n/* 2 REG_MBSSID_BCN_SPACE2_8821C */\n\n#define BIT_SHIFT_BCN_SPACE_CLINT2_8821C 16\n#define BIT_MASK_BCN_SPACE_CLINT2_8821C 0xfff\n#define BIT_BCN_SPACE_CLINT2_8821C(x)                                          \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT2_8821C)                               \\\n\t << BIT_SHIFT_BCN_SPACE_CLINT2_8821C)\n#define BITS_BCN_SPACE_CLINT2_8821C                                            \\\n\t(BIT_MASK_BCN_SPACE_CLINT2_8821C << BIT_SHIFT_BCN_SPACE_CLINT2_8821C)\n#define BIT_CLEAR_BCN_SPACE_CLINT2_8821C(x)                                    \\\n\t((x) & (~BITS_BCN_SPACE_CLINT2_8821C))\n#define BIT_GET_BCN_SPACE_CLINT2_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8821C) &                           \\\n\t BIT_MASK_BCN_SPACE_CLINT2_8821C)\n#define BIT_SET_BCN_SPACE_CLINT2_8821C(x, v)                                   \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT2_8821C(x) | BIT_BCN_SPACE_CLINT2_8821C(v))\n\n#define BIT_SHIFT_BCN_SPACE_CLINT1_8821C 0\n#define BIT_MASK_BCN_SPACE_CLINT1_8821C 0xfff\n#define BIT_BCN_SPACE_CLINT1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT1_8821C)                               \\\n\t << BIT_SHIFT_BCN_SPACE_CLINT1_8821C)\n#define BITS_BCN_SPACE_CLINT1_8821C                                            \\\n\t(BIT_MASK_BCN_SPACE_CLINT1_8821C << BIT_SHIFT_BCN_SPACE_CLINT1_8821C)\n#define BIT_CLEAR_BCN_SPACE_CLINT1_8821C(x)                                    \\\n\t((x) & (~BITS_BCN_SPACE_CLINT1_8821C))\n#define BIT_GET_BCN_SPACE_CLINT1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8821C) &                           \\\n\t BIT_MASK_BCN_SPACE_CLINT1_8821C)\n#define BIT_SET_BCN_SPACE_CLINT1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT1_8821C(x) | BIT_BCN_SPACE_CLINT1_8821C(v))\n\n/* 2 REG_MBSSID_BCN_SPACE3_8821C */\n\n#define BIT_SHIFT_SUB_BCN_SPACE_8821C 16\n#define BIT_MASK_SUB_BCN_SPACE_8821C 0xff\n#define BIT_SUB_BCN_SPACE_8821C(x)                                             \\\n\t(((x) & BIT_MASK_SUB_BCN_SPACE_8821C) << BIT_SHIFT_SUB_BCN_SPACE_8821C)\n#define BITS_SUB_BCN_SPACE_8821C                                               \\\n\t(BIT_MASK_SUB_BCN_SPACE_8821C << BIT_SHIFT_SUB_BCN_SPACE_8821C)\n#define BIT_CLEAR_SUB_BCN_SPACE_8821C(x) ((x) & (~BITS_SUB_BCN_SPACE_8821C))\n#define BIT_GET_SUB_BCN_SPACE_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SUB_BCN_SPACE_8821C) & BIT_MASK_SUB_BCN_SPACE_8821C)\n#define BIT_SET_SUB_BCN_SPACE_8821C(x, v)                                      \\\n\t(BIT_CLEAR_SUB_BCN_SPACE_8821C(x) | BIT_SUB_BCN_SPACE_8821C(v))\n\n#define BIT_SHIFT_BCN_SPACE_CLINT3_8821C 0\n#define BIT_MASK_BCN_SPACE_CLINT3_8821C 0xfff\n#define BIT_BCN_SPACE_CLINT3_8821C(x)                                          \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT3_8821C)                               \\\n\t << BIT_SHIFT_BCN_SPACE_CLINT3_8821C)\n#define BITS_BCN_SPACE_CLINT3_8821C                                            \\\n\t(BIT_MASK_BCN_SPACE_CLINT3_8821C << BIT_SHIFT_BCN_SPACE_CLINT3_8821C)\n#define BIT_CLEAR_BCN_SPACE_CLINT3_8821C(x)                                    \\\n\t((x) & (~BITS_BCN_SPACE_CLINT3_8821C))\n#define BIT_GET_BCN_SPACE_CLINT3_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8821C) &                           \\\n\t BIT_MASK_BCN_SPACE_CLINT3_8821C)\n#define BIT_SET_BCN_SPACE_CLINT3_8821C(x, v)                                   \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT3_8821C(x) | BIT_BCN_SPACE_CLINT3_8821C(v))\n\n/* 2 REG_ACMHWCTRL_8821C */\n#define BIT_BEQ_ACM_STATUS_8821C BIT(7)\n#define BIT_VIQ_ACM_STATUS_8821C BIT(6)\n#define BIT_VOQ_ACM_STATUS_8821C BIT(5)\n#define BIT_BEQ_ACM_EN_8821C BIT(3)\n#define BIT_VIQ_ACM_EN_8821C BIT(2)\n#define BIT_VOQ_ACM_EN_8821C BIT(1)\n#define BIT_ACMHWEN_8821C BIT(0)\n\n/* 2 REG_ACMRSTCTRL_8821C */\n#define BIT_BE_ACM_RESET_USED_TIME_8821C BIT(2)\n#define BIT_VI_ACM_RESET_USED_TIME_8821C BIT(1)\n#define BIT_VO_ACM_RESET_USED_TIME_8821C BIT(0)\n\n/* 2 REG_ACMAVG_8821C */\n\n#define BIT_SHIFT_AVGPERIOD_8821C 0\n#define BIT_MASK_AVGPERIOD_8821C 0xffff\n#define BIT_AVGPERIOD_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_AVGPERIOD_8821C) << BIT_SHIFT_AVGPERIOD_8821C)\n#define BITS_AVGPERIOD_8821C                                                   \\\n\t(BIT_MASK_AVGPERIOD_8821C << BIT_SHIFT_AVGPERIOD_8821C)\n#define BIT_CLEAR_AVGPERIOD_8821C(x) ((x) & (~BITS_AVGPERIOD_8821C))\n#define BIT_GET_AVGPERIOD_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_AVGPERIOD_8821C) & BIT_MASK_AVGPERIOD_8821C)\n#define BIT_SET_AVGPERIOD_8821C(x, v)                                          \\\n\t(BIT_CLEAR_AVGPERIOD_8821C(x) | BIT_AVGPERIOD_8821C(v))\n\n/* 2 REG_VO_ADMTIME_8821C */\n\n#define BIT_SHIFT_VO_ADMITTED_TIME_8821C 0\n#define BIT_MASK_VO_ADMITTED_TIME_8821C 0xffff\n#define BIT_VO_ADMITTED_TIME_8821C(x)                                          \\\n\t(((x) & BIT_MASK_VO_ADMITTED_TIME_8821C)                               \\\n\t << BIT_SHIFT_VO_ADMITTED_TIME_8821C)\n#define BITS_VO_ADMITTED_TIME_8821C                                            \\\n\t(BIT_MASK_VO_ADMITTED_TIME_8821C << BIT_SHIFT_VO_ADMITTED_TIME_8821C)\n#define BIT_CLEAR_VO_ADMITTED_TIME_8821C(x)                                    \\\n\t((x) & (~BITS_VO_ADMITTED_TIME_8821C))\n#define BIT_GET_VO_ADMITTED_TIME_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8821C) &                           \\\n\t BIT_MASK_VO_ADMITTED_TIME_8821C)\n#define BIT_SET_VO_ADMITTED_TIME_8821C(x, v)                                   \\\n\t(BIT_CLEAR_VO_ADMITTED_TIME_8821C(x) | BIT_VO_ADMITTED_TIME_8821C(v))\n\n/* 2 REG_VI_ADMTIME_8821C */\n\n#define BIT_SHIFT_VI_ADMITTED_TIME_8821C 0\n#define BIT_MASK_VI_ADMITTED_TIME_8821C 0xffff\n#define BIT_VI_ADMITTED_TIME_8821C(x)                                          \\\n\t(((x) & BIT_MASK_VI_ADMITTED_TIME_8821C)                               \\\n\t << BIT_SHIFT_VI_ADMITTED_TIME_8821C)\n#define BITS_VI_ADMITTED_TIME_8821C                                            \\\n\t(BIT_MASK_VI_ADMITTED_TIME_8821C << BIT_SHIFT_VI_ADMITTED_TIME_8821C)\n#define BIT_CLEAR_VI_ADMITTED_TIME_8821C(x)                                    \\\n\t((x) & (~BITS_VI_ADMITTED_TIME_8821C))\n#define BIT_GET_VI_ADMITTED_TIME_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8821C) &                           \\\n\t BIT_MASK_VI_ADMITTED_TIME_8821C)\n#define BIT_SET_VI_ADMITTED_TIME_8821C(x, v)                                   \\\n\t(BIT_CLEAR_VI_ADMITTED_TIME_8821C(x) | BIT_VI_ADMITTED_TIME_8821C(v))\n\n/* 2 REG_BE_ADMTIME_8821C */\n\n#define BIT_SHIFT_BE_ADMITTED_TIME_8821C 0\n#define BIT_MASK_BE_ADMITTED_TIME_8821C 0xffff\n#define BIT_BE_ADMITTED_TIME_8821C(x)                                          \\\n\t(((x) & BIT_MASK_BE_ADMITTED_TIME_8821C)                               \\\n\t << BIT_SHIFT_BE_ADMITTED_TIME_8821C)\n#define BITS_BE_ADMITTED_TIME_8821C                                            \\\n\t(BIT_MASK_BE_ADMITTED_TIME_8821C << BIT_SHIFT_BE_ADMITTED_TIME_8821C)\n#define BIT_CLEAR_BE_ADMITTED_TIME_8821C(x)                                    \\\n\t((x) & (~BITS_BE_ADMITTED_TIME_8821C))\n#define BIT_GET_BE_ADMITTED_TIME_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8821C) &                           \\\n\t BIT_MASK_BE_ADMITTED_TIME_8821C)\n#define BIT_SET_BE_ADMITTED_TIME_8821C(x, v)                                   \\\n\t(BIT_CLEAR_BE_ADMITTED_TIME_8821C(x) | BIT_BE_ADMITTED_TIME_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_EDCA_RANDOM_GEN_8821C */\n\n#define BIT_SHIFT_RANDOM_GEN_8821C 0\n#define BIT_MASK_RANDOM_GEN_8821C 0xffffff\n#define BIT_RANDOM_GEN_8821C(x)                                                \\\n\t(((x) & BIT_MASK_RANDOM_GEN_8821C) << BIT_SHIFT_RANDOM_GEN_8821C)\n#define BITS_RANDOM_GEN_8821C                                                  \\\n\t(BIT_MASK_RANDOM_GEN_8821C << BIT_SHIFT_RANDOM_GEN_8821C)\n#define BIT_CLEAR_RANDOM_GEN_8821C(x) ((x) & (~BITS_RANDOM_GEN_8821C))\n#define BIT_GET_RANDOM_GEN_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_RANDOM_GEN_8821C) & BIT_MASK_RANDOM_GEN_8821C)\n#define BIT_SET_RANDOM_GEN_8821C(x, v)                                         \\\n\t(BIT_CLEAR_RANDOM_GEN_8821C(x) | BIT_RANDOM_GEN_8821C(v))\n\n/* 2 REG_TXCMD_NOA_SEL_8821C */\n\n#define BIT_SHIFT_NOA_SEL_V2_8821C 4\n#define BIT_MASK_NOA_SEL_V2_8821C 0x7\n#define BIT_NOA_SEL_V2_8821C(x)                                                \\\n\t(((x) & BIT_MASK_NOA_SEL_V2_8821C) << BIT_SHIFT_NOA_SEL_V2_8821C)\n#define BITS_NOA_SEL_V2_8821C                                                  \\\n\t(BIT_MASK_NOA_SEL_V2_8821C << BIT_SHIFT_NOA_SEL_V2_8821C)\n#define BIT_CLEAR_NOA_SEL_V2_8821C(x) ((x) & (~BITS_NOA_SEL_V2_8821C))\n#define BIT_GET_NOA_SEL_V2_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_NOA_SEL_V2_8821C) & BIT_MASK_NOA_SEL_V2_8821C)\n#define BIT_SET_NOA_SEL_V2_8821C(x, v)                                         \\\n\t(BIT_CLEAR_NOA_SEL_V2_8821C(x) | BIT_NOA_SEL_V2_8821C(v))\n\n#define BIT_SHIFT_TXCMD_SEG_SEL_8821C 0\n#define BIT_MASK_TXCMD_SEG_SEL_8821C 0xf\n#define BIT_TXCMD_SEG_SEL_8821C(x)                                             \\\n\t(((x) & BIT_MASK_TXCMD_SEG_SEL_8821C) << BIT_SHIFT_TXCMD_SEG_SEL_8821C)\n#define BITS_TXCMD_SEG_SEL_8821C                                               \\\n\t(BIT_MASK_TXCMD_SEG_SEL_8821C << BIT_SHIFT_TXCMD_SEG_SEL_8821C)\n#define BIT_CLEAR_TXCMD_SEG_SEL_8821C(x) ((x) & (~BITS_TXCMD_SEG_SEL_8821C))\n#define BIT_GET_TXCMD_SEG_SEL_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8821C) & BIT_MASK_TXCMD_SEG_SEL_8821C)\n#define BIT_SET_TXCMD_SEG_SEL_8821C(x, v)                                      \\\n\t(BIT_CLEAR_TXCMD_SEG_SEL_8821C(x) | BIT_TXCMD_SEG_SEL_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOA_PARAM_8821C */\n\n#define BIT_SHIFT_NOA_DURATION_V1_8821C 0\n#define BIT_MASK_NOA_DURATION_V1_8821C 0xffffffffL\n#define BIT_NOA_DURATION_V1_8821C(x)                                           \\\n\t(((x) & BIT_MASK_NOA_DURATION_V1_8821C)                                \\\n\t << BIT_SHIFT_NOA_DURATION_V1_8821C)\n#define BITS_NOA_DURATION_V1_8821C                                             \\\n\t(BIT_MASK_NOA_DURATION_V1_8821C << BIT_SHIFT_NOA_DURATION_V1_8821C)\n#define BIT_CLEAR_NOA_DURATION_V1_8821C(x) ((x) & (~BITS_NOA_DURATION_V1_8821C))\n#define BIT_GET_NOA_DURATION_V1_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_NOA_DURATION_V1_8821C) &                            \\\n\t BIT_MASK_NOA_DURATION_V1_8821C)\n#define BIT_SET_NOA_DURATION_V1_8821C(x, v)                                    \\\n\t(BIT_CLEAR_NOA_DURATION_V1_8821C(x) | BIT_NOA_DURATION_V1_8821C(v))\n\n/* 2 REG_NOA_PARAM_1_8821C */\n\n#define BIT_SHIFT_NOA_INTERVAL_V1_8821C 0\n#define BIT_MASK_NOA_INTERVAL_V1_8821C 0xffffffffL\n#define BIT_NOA_INTERVAL_V1_8821C(x)                                           \\\n\t(((x) & BIT_MASK_NOA_INTERVAL_V1_8821C)                                \\\n\t << BIT_SHIFT_NOA_INTERVAL_V1_8821C)\n#define BITS_NOA_INTERVAL_V1_8821C                                             \\\n\t(BIT_MASK_NOA_INTERVAL_V1_8821C << BIT_SHIFT_NOA_INTERVAL_V1_8821C)\n#define BIT_CLEAR_NOA_INTERVAL_V1_8821C(x) ((x) & (~BITS_NOA_INTERVAL_V1_8821C))\n#define BIT_GET_NOA_INTERVAL_V1_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_NOA_INTERVAL_V1_8821C) &                            \\\n\t BIT_MASK_NOA_INTERVAL_V1_8821C)\n#define BIT_SET_NOA_INTERVAL_V1_8821C(x, v)                                    \\\n\t(BIT_CLEAR_NOA_INTERVAL_V1_8821C(x) | BIT_NOA_INTERVAL_V1_8821C(v))\n\n/* 2 REG_NOA_PARAM_2_8821C */\n\n#define BIT_SHIFT_NOA_START_TIME_V1_8821C 0\n#define BIT_MASK_NOA_START_TIME_V1_8821C 0xffffffffL\n#define BIT_NOA_START_TIME_V1_8821C(x)                                         \\\n\t(((x) & BIT_MASK_NOA_START_TIME_V1_8821C)                              \\\n\t << BIT_SHIFT_NOA_START_TIME_V1_8821C)\n#define BITS_NOA_START_TIME_V1_8821C                                           \\\n\t(BIT_MASK_NOA_START_TIME_V1_8821C << BIT_SHIFT_NOA_START_TIME_V1_8821C)\n#define BIT_CLEAR_NOA_START_TIME_V1_8821C(x)                                   \\\n\t((x) & (~BITS_NOA_START_TIME_V1_8821C))\n#define BIT_GET_NOA_START_TIME_V1_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_NOA_START_TIME_V1_8821C) &                          \\\n\t BIT_MASK_NOA_START_TIME_V1_8821C)\n#define BIT_SET_NOA_START_TIME_V1_8821C(x, v)                                  \\\n\t(BIT_CLEAR_NOA_START_TIME_V1_8821C(x) | BIT_NOA_START_TIME_V1_8821C(v))\n\n/* 2 REG_NOA_PARAM_3_8821C */\n\n#define BIT_SHIFT_NOA_COUNT_V1_8821C 0\n#define BIT_MASK_NOA_COUNT_V1_8821C 0xffffffffL\n#define BIT_NOA_COUNT_V1_8821C(x)                                              \\\n\t(((x) & BIT_MASK_NOA_COUNT_V1_8821C) << BIT_SHIFT_NOA_COUNT_V1_8821C)\n#define BITS_NOA_COUNT_V1_8821C                                                \\\n\t(BIT_MASK_NOA_COUNT_V1_8821C << BIT_SHIFT_NOA_COUNT_V1_8821C)\n#define BIT_CLEAR_NOA_COUNT_V1_8821C(x) ((x) & (~BITS_NOA_COUNT_V1_8821C))\n#define BIT_GET_NOA_COUNT_V1_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_NOA_COUNT_V1_8821C) & BIT_MASK_NOA_COUNT_V1_8821C)\n#define BIT_SET_NOA_COUNT_V1_8821C(x, v)                                       \\\n\t(BIT_CLEAR_NOA_COUNT_V1_8821C(x) | BIT_NOA_COUNT_V1_8821C(v))\n\n/* 2 REG_P2P_RST_8821C */\n#define BIT_P2P2_PWR_RST1_8821C BIT(5)\n#define BIT_P2P2_PWR_RST0_8821C BIT(4)\n#define BIT_P2P1_PWR_RST1_8821C BIT(3)\n#define BIT_P2P1_PWR_RST0_8821C BIT(2)\n#define BIT_P2P_PWR_RST1_V1_8821C BIT(1)\n#define BIT_P2P_PWR_RST0_V1_8821C BIT(0)\n\n/* 2 REG_SCHEDULER_RST_8821C */\n#define BIT_SYNC_CLI_ONCE_RIGHT_NOW_8821C BIT(2)\n#define BIT_SYNC_CLI_ONCE_BY_TBTT_8821C BIT(1)\n#define BIT_SCHEDULER_RST_V1_8821C BIT(0)\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_SCH_TXCMD_8821C */\n\n#define BIT_SHIFT_SCH_TXCMD_8821C 0\n#define BIT_MASK_SCH_TXCMD_8821C 0xffffffffL\n#define BIT_SCH_TXCMD_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_SCH_TXCMD_8821C) << BIT_SHIFT_SCH_TXCMD_8821C)\n#define BITS_SCH_TXCMD_8821C                                                   \\\n\t(BIT_MASK_SCH_TXCMD_8821C << BIT_SHIFT_SCH_TXCMD_8821C)\n#define BIT_CLEAR_SCH_TXCMD_8821C(x) ((x) & (~BITS_SCH_TXCMD_8821C))\n#define BIT_GET_SCH_TXCMD_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_SCH_TXCMD_8821C) & BIT_MASK_SCH_TXCMD_8821C)\n#define BIT_SET_SCH_TXCMD_8821C(x, v)                                          \\\n\t(BIT_CLEAR_SCH_TXCMD_8821C(x) | BIT_SCH_TXCMD_8821C(v))\n\n/* 2 REG_PAGE5_DUMMY_8821C */\n#define BIT_ECO_TXOP_BREAK_FORCE_CFEND_8821C BIT(0)\n\n/* 2 REG_CPUMGQ_TX_TIMER_8821C */\n\n#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C 0\n#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C 0xffffffffL\n#define BIT_CPUMGQ_TX_TIMER_V1_8821C(x)                                        \\\n\t(((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C)                             \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C)\n#define BITS_CPUMGQ_TX_TIMER_V1_8821C                                          \\\n\t(BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C                                     \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C)\n#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8821C(x)                                  \\\n\t((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8821C))\n#define BIT_GET_CPUMGQ_TX_TIMER_V1_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C) &                         \\\n\t BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C)\n#define BIT_SET_CPUMGQ_TX_TIMER_V1_8821C(x, v)                                 \\\n\t(BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8821C(x) |                               \\\n\t BIT_CPUMGQ_TX_TIMER_V1_8821C(v))\n\n/* 2 REG_PS_TIMER_A_8821C */\n\n#define BIT_SHIFT_PS_TIMER_A_V1_8821C 0\n#define BIT_MASK_PS_TIMER_A_V1_8821C 0xffffffffL\n#define BIT_PS_TIMER_A_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_PS_TIMER_A_V1_8821C) << BIT_SHIFT_PS_TIMER_A_V1_8821C)\n#define BITS_PS_TIMER_A_V1_8821C                                               \\\n\t(BIT_MASK_PS_TIMER_A_V1_8821C << BIT_SHIFT_PS_TIMER_A_V1_8821C)\n#define BIT_CLEAR_PS_TIMER_A_V1_8821C(x) ((x) & (~BITS_PS_TIMER_A_V1_8821C))\n#define BIT_GET_PS_TIMER_A_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_A_V1_8821C) & BIT_MASK_PS_TIMER_A_V1_8821C)\n#define BIT_SET_PS_TIMER_A_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_PS_TIMER_A_V1_8821C(x) | BIT_PS_TIMER_A_V1_8821C(v))\n\n/* 2 REG_PS_TIMER_B_8821C */\n\n#define BIT_SHIFT_PS_TIMER_B_V1_8821C 0\n#define BIT_MASK_PS_TIMER_B_V1_8821C 0xffffffffL\n#define BIT_PS_TIMER_B_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_PS_TIMER_B_V1_8821C) << BIT_SHIFT_PS_TIMER_B_V1_8821C)\n#define BITS_PS_TIMER_B_V1_8821C                                               \\\n\t(BIT_MASK_PS_TIMER_B_V1_8821C << BIT_SHIFT_PS_TIMER_B_V1_8821C)\n#define BIT_CLEAR_PS_TIMER_B_V1_8821C(x) ((x) & (~BITS_PS_TIMER_B_V1_8821C))\n#define BIT_GET_PS_TIMER_B_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_B_V1_8821C) & BIT_MASK_PS_TIMER_B_V1_8821C)\n#define BIT_SET_PS_TIMER_B_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_PS_TIMER_B_V1_8821C(x) | BIT_PS_TIMER_B_V1_8821C(v))\n\n/* 2 REG_PS_TIMER_C_8821C */\n\n#define BIT_SHIFT_PS_TIMER_C_V1_8821C 0\n#define BIT_MASK_PS_TIMER_C_V1_8821C 0xffffffffL\n#define BIT_PS_TIMER_C_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_PS_TIMER_C_V1_8821C) << BIT_SHIFT_PS_TIMER_C_V1_8821C)\n#define BITS_PS_TIMER_C_V1_8821C                                               \\\n\t(BIT_MASK_PS_TIMER_C_V1_8821C << BIT_SHIFT_PS_TIMER_C_V1_8821C)\n#define BIT_CLEAR_PS_TIMER_C_V1_8821C(x) ((x) & (~BITS_PS_TIMER_C_V1_8821C))\n#define BIT_GET_PS_TIMER_C_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_C_V1_8821C) & BIT_MASK_PS_TIMER_C_V1_8821C)\n#define BIT_SET_PS_TIMER_C_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_PS_TIMER_C_V1_8821C(x) | BIT_PS_TIMER_C_V1_8821C(v))\n\n/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8821C */\n#define BIT_CPUMGQ_TIMER_EN_8821C BIT(31)\n#define BIT_CPUMGQ_TX_EN_8821C BIT(28)\n\n#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C 24\n#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C 0x7\n#define BIT_CPUMGQ_TIMER_TSF_SEL_8821C(x)                                      \\\n\t(((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C)                           \\\n\t << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C)\n#define BITS_CPUMGQ_TIMER_TSF_SEL_8821C                                        \\\n\t(BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C                                   \\\n\t << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C)\n#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8821C(x)                                \\\n\t((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8821C))\n#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) &                       \\\n\t BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C)\n#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8821C(x, v)                               \\\n\t(BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8821C(x) |                             \\\n\t BIT_CPUMGQ_TIMER_TSF_SEL_8821C(v))\n\n#define BIT_PS_TIMER_C_EN_8821C BIT(23)\n\n#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C 16\n#define BIT_MASK_PS_TIMER_C_TSF_SEL_8821C 0x7\n#define BIT_PS_TIMER_C_TSF_SEL_8821C(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8821C)                             \\\n\t << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C)\n#define BITS_PS_TIMER_C_TSF_SEL_8821C                                          \\\n\t(BIT_MASK_PS_TIMER_C_TSF_SEL_8821C                                     \\\n\t << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C)\n#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8821C(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_C_TSF_SEL_8821C))\n#define BIT_GET_PS_TIMER_C_TSF_SEL_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) &                         \\\n\t BIT_MASK_PS_TIMER_C_TSF_SEL_8821C)\n#define BIT_SET_PS_TIMER_C_TSF_SEL_8821C(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_C_TSF_SEL_8821C(x) |                               \\\n\t BIT_PS_TIMER_C_TSF_SEL_8821C(v))\n\n#define BIT_PS_TIMER_B_EN_8821C BIT(15)\n\n#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C 8\n#define BIT_MASK_PS_TIMER_B_TSF_SEL_8821C 0x7\n#define BIT_PS_TIMER_B_TSF_SEL_8821C(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8821C)                             \\\n\t << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C)\n#define BITS_PS_TIMER_B_TSF_SEL_8821C                                          \\\n\t(BIT_MASK_PS_TIMER_B_TSF_SEL_8821C                                     \\\n\t << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C)\n#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8821C(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_B_TSF_SEL_8821C))\n#define BIT_GET_PS_TIMER_B_TSF_SEL_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) &                         \\\n\t BIT_MASK_PS_TIMER_B_TSF_SEL_8821C)\n#define BIT_SET_PS_TIMER_B_TSF_SEL_8821C(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_B_TSF_SEL_8821C(x) |                               \\\n\t BIT_PS_TIMER_B_TSF_SEL_8821C(v))\n\n#define BIT_PS_TIMER_A_EN_8821C BIT(7)\n\n#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C 0\n#define BIT_MASK_PS_TIMER_A_TSF_SEL_8821C 0x7\n#define BIT_PS_TIMER_A_TSF_SEL_8821C(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8821C)                             \\\n\t << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C)\n#define BITS_PS_TIMER_A_TSF_SEL_8821C                                          \\\n\t(BIT_MASK_PS_TIMER_A_TSF_SEL_8821C                                     \\\n\t << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C)\n#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8821C(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_A_TSF_SEL_8821C))\n#define BIT_GET_PS_TIMER_A_TSF_SEL_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C) &                         \\\n\t BIT_MASK_PS_TIMER_A_TSF_SEL_8821C)\n#define BIT_SET_PS_TIMER_A_TSF_SEL_8821C(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_A_TSF_SEL_8821C(x) |                               \\\n\t BIT_PS_TIMER_A_TSF_SEL_8821C(v))\n\n/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8821C */\n\n#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C 0\n#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C 0xff\n#define BIT_CPUMGQ_TX_TIMER_EARLY_8821C(x)                                     \\\n\t(((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C)                          \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C)\n#define BITS_CPUMGQ_TX_TIMER_EARLY_8821C                                       \\\n\t(BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C                                  \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C)\n#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8821C(x)                               \\\n\t((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8821C))\n#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8821C(x)                                 \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C) &                      \\\n\t BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C)\n#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8821C(x, v)                              \\\n\t(BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8821C(x) |                            \\\n\t BIT_CPUMGQ_TX_TIMER_EARLY_8821C(v))\n\n/* 2 REG_PS_TIMER_A_EARLY_8821C */\n\n#define BIT_SHIFT_PS_TIMER_A_EARLY_8821C 0\n#define BIT_MASK_PS_TIMER_A_EARLY_8821C 0xff\n#define BIT_PS_TIMER_A_EARLY_8821C(x)                                          \\\n\t(((x) & BIT_MASK_PS_TIMER_A_EARLY_8821C)                               \\\n\t << BIT_SHIFT_PS_TIMER_A_EARLY_8821C)\n#define BITS_PS_TIMER_A_EARLY_8821C                                            \\\n\t(BIT_MASK_PS_TIMER_A_EARLY_8821C << BIT_SHIFT_PS_TIMER_A_EARLY_8821C)\n#define BIT_CLEAR_PS_TIMER_A_EARLY_8821C(x)                                    \\\n\t((x) & (~BITS_PS_TIMER_A_EARLY_8821C))\n#define BIT_GET_PS_TIMER_A_EARLY_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8821C) &                           \\\n\t BIT_MASK_PS_TIMER_A_EARLY_8821C)\n#define BIT_SET_PS_TIMER_A_EARLY_8821C(x, v)                                   \\\n\t(BIT_CLEAR_PS_TIMER_A_EARLY_8821C(x) | BIT_PS_TIMER_A_EARLY_8821C(v))\n\n/* 2 REG_PS_TIMER_B_EARLY_8821C */\n\n#define BIT_SHIFT_PS_TIMER_B_EARLY_8821C 0\n#define BIT_MASK_PS_TIMER_B_EARLY_8821C 0xff\n#define BIT_PS_TIMER_B_EARLY_8821C(x)                                          \\\n\t(((x) & BIT_MASK_PS_TIMER_B_EARLY_8821C)                               \\\n\t << BIT_SHIFT_PS_TIMER_B_EARLY_8821C)\n#define BITS_PS_TIMER_B_EARLY_8821C                                            \\\n\t(BIT_MASK_PS_TIMER_B_EARLY_8821C << BIT_SHIFT_PS_TIMER_B_EARLY_8821C)\n#define BIT_CLEAR_PS_TIMER_B_EARLY_8821C(x)                                    \\\n\t((x) & (~BITS_PS_TIMER_B_EARLY_8821C))\n#define BIT_GET_PS_TIMER_B_EARLY_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8821C) &                           \\\n\t BIT_MASK_PS_TIMER_B_EARLY_8821C)\n#define BIT_SET_PS_TIMER_B_EARLY_8821C(x, v)                                   \\\n\t(BIT_CLEAR_PS_TIMER_B_EARLY_8821C(x) | BIT_PS_TIMER_B_EARLY_8821C(v))\n\n/* 2 REG_PS_TIMER_C_EARLY_8821C */\n\n#define BIT_SHIFT_PS_TIMER_C_EARLY_8821C 0\n#define BIT_MASK_PS_TIMER_C_EARLY_8821C 0xff\n#define BIT_PS_TIMER_C_EARLY_8821C(x)                                          \\\n\t(((x) & BIT_MASK_PS_TIMER_C_EARLY_8821C)                               \\\n\t << BIT_SHIFT_PS_TIMER_C_EARLY_8821C)\n#define BITS_PS_TIMER_C_EARLY_8821C                                            \\\n\t(BIT_MASK_PS_TIMER_C_EARLY_8821C << BIT_SHIFT_PS_TIMER_C_EARLY_8821C)\n#define BIT_CLEAR_PS_TIMER_C_EARLY_8821C(x)                                    \\\n\t((x) & (~BITS_PS_TIMER_C_EARLY_8821C))\n#define BIT_GET_PS_TIMER_C_EARLY_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8821C) &                           \\\n\t BIT_MASK_PS_TIMER_C_EARLY_8821C)\n#define BIT_SET_PS_TIMER_C_EARLY_8821C(x, v)                                   \\\n\t(BIT_CLEAR_PS_TIMER_C_EARLY_8821C(x) | BIT_PS_TIMER_C_EARLY_8821C(v))\n\n/* 2 REG_CPUMGQ_PARAMETER_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n#define BIT_MAC_STOP_CPUMGQ_8821C BIT(16)\n\n#define BIT_SHIFT_CW_8821C 8\n#define BIT_MASK_CW_8821C 0xff\n#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C)\n#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C)\n#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C))\n#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C)\n#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v))\n\n#define BIT_SHIFT_AIFS_8821C 0\n#define BIT_MASK_AIFS_8821C 0xff\n#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C)\n#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C)\n#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C))\n#define BIT_GET_AIFS_8821C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)\n#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_WMAC_CR_8821C (WMAC CR AND APSD CONTROL REGISTER) */\n#define BIT_IC_MACPHY_M_8821C BIT(0)\n\n/* 2 REG_WMAC_FWPKT_CR_8821C */\n#define BIT_FWEN_8821C BIT(7)\n#define BIT_PHYSTS_PKT_CTRL_8821C BIT(6)\n#define BIT_FWFULL_TO_RXFF_EN_8821C BIT(5)\n#define BIT_APPHDR_MIDSRCH_FAIL_8821C BIT(4)\n#define BIT_FWPARSING_EN_8821C BIT(3)\n\n#define BIT_SHIFT_APPEND_MHDR_LEN_8821C 0\n#define BIT_MASK_APPEND_MHDR_LEN_8821C 0x7\n#define BIT_APPEND_MHDR_LEN_8821C(x)                                           \\\n\t(((x) & BIT_MASK_APPEND_MHDR_LEN_8821C)                                \\\n\t << BIT_SHIFT_APPEND_MHDR_LEN_8821C)\n#define BITS_APPEND_MHDR_LEN_8821C                                             \\\n\t(BIT_MASK_APPEND_MHDR_LEN_8821C << BIT_SHIFT_APPEND_MHDR_LEN_8821C)\n#define BIT_CLEAR_APPEND_MHDR_LEN_8821C(x) ((x) & (~BITS_APPEND_MHDR_LEN_8821C))\n#define BIT_GET_APPEND_MHDR_LEN_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8821C) &                            \\\n\t BIT_MASK_APPEND_MHDR_LEN_8821C)\n#define BIT_SET_APPEND_MHDR_LEN_8821C(x, v)                                    \\\n\t(BIT_CLEAR_APPEND_MHDR_LEN_8821C(x) | BIT_APPEND_MHDR_LEN_8821C(v))\n\n/* 2 REG_FW_STS_FILTER_8821C */\n#define BIT_DATA_FW_STS_FILTER_8821C BIT(2)\n#define BIT_CTRL_FW_STS_FILTER_8821C BIT(1)\n#define BIT_MGNT_FW_STS_FILTER_8821C BIT(0)\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_TCR_8821C (TRANSMISSION CONFIGURATION REGISTER) */\n#define BIT_WMAC_EN_RTS_ADDR_8821C BIT(31)\n#define BIT_WMAC_DISABLE_CCK_8821C BIT(30)\n#define BIT_WMAC_RAW_LEN_8821C BIT(29)\n#define BIT_WMAC_NOTX_IN_RXNDP_8821C BIT(28)\n#define BIT_WMAC_EN_EOF_8821C BIT(27)\n#define BIT_WMAC_BF_SEL_8821C BIT(26)\n#define BIT_WMAC_ANTMODE_SEL_8821C BIT(25)\n#define BIT_WMAC_TCRPWRMGT_HWCTL_8821C BIT(24)\n#define BIT_WMAC_SMOOTH_VAL_8821C BIT(23)\n#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8821C BIT(20)\n#define BIT_WMAC_TCR_EN_20MST_8821C BIT(19)\n#define BIT_WMAC_DIS_SIGTA_8821C BIT(18)\n#define BIT_WMAC_DIS_A2B0_8821C BIT(17)\n#define BIT_WMAC_MSK_SIGBCRC_8821C BIT(16)\n#define BIT_WMAC_TCR_ERRSTEN_3_8821C BIT(15)\n#define BIT_WMAC_TCR_ERRSTEN_2_8821C BIT(14)\n#define BIT_WMAC_TCR_ERRSTEN_1_8821C BIT(13)\n#define BIT_WMAC_TCR_ERRSTEN_0_8821C BIT(12)\n#define BIT_WMAC_TCR_TXSK_PERPKT_8821C BIT(11)\n#define BIT_ICV_8821C BIT(10)\n#define BIT_CFEND_FORMAT_8821C BIT(9)\n#define BIT_CRC_8821C BIT(8)\n#define BIT_PWRBIT_OW_EN_8821C BIT(7)\n#define BIT_PWR_ST_8821C BIT(6)\n#define BIT_WMAC_TCR_UPD_TIMIE_8821C BIT(5)\n#define BIT_WMAC_TCR_UPD_HGQMD_8821C BIT(4)\n#define BIT_VHTSIGA1_TXPS_8821C BIT(3)\n#define BIT_PAD_SEL_8821C BIT(2)\n#define BIT_DIS_GCLK_8821C BIT(1)\n\n/* 2 REG_RCR_8821C (RECEIVE CONFIGURATION REGISTER) */\n#define BIT_APP_FCS_8821C BIT(31)\n#define BIT_APP_MIC_8821C BIT(30)\n#define BIT_APP_ICV_8821C BIT(29)\n#define BIT_APP_PHYSTS_8821C BIT(28)\n#define BIT_APP_BASSN_8821C BIT(27)\n#define BIT_VHT_DACK_8821C BIT(26)\n#define BIT_TCPOFLD_EN_8821C BIT(25)\n#define BIT_ENMBID_8821C BIT(24)\n#define BIT_LSIGEN_8821C BIT(23)\n#define BIT_MFBEN_8821C BIT(22)\n#define BIT_DISCHKPPDLLEN_8821C BIT(21)\n#define BIT_PKTCTL_DLEN_8821C BIT(20)\n#define BIT_TIM_PARSER_EN_8821C BIT(18)\n#define BIT_BC_MD_EN_8821C BIT(17)\n#define BIT_UC_MD_EN_8821C BIT(16)\n#define BIT_RXSK_PERPKT_8821C BIT(15)\n#define BIT_HTC_LOC_CTRL_8821C BIT(14)\n#define BIT_RPFM_CAM_ENABLE_8821C BIT(12)\n#define BIT_TA_BCN_8821C BIT(11)\n#define BIT_DISDECMYPKT_8821C BIT(10)\n#define BIT_AICV_8821C BIT(9)\n#define BIT_ACRC32_8821C BIT(8)\n#define BIT_CBSSID_BCN_8821C BIT(7)\n#define BIT_CBSSID_DATA_8821C BIT(6)\n#define BIT_APWRMGT_8821C BIT(5)\n#define BIT_ADD3_8821C BIT(4)\n#define BIT_AB_8821C BIT(3)\n#define BIT_AM_8821C BIT(2)\n#define BIT_APM_8821C BIT(1)\n#define BIT_AAP_8821C BIT(0)\n\n/* 2 REG_RX_PKT_LIMIT_8821C (RX PACKET LENGTH LIMIT REGISTER) */\n\n#define BIT_SHIFT_RXPKTLMT_8821C 0\n#define BIT_MASK_RXPKTLMT_8821C 0x3f\n#define BIT_RXPKTLMT_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_RXPKTLMT_8821C) << BIT_SHIFT_RXPKTLMT_8821C)\n#define BITS_RXPKTLMT_8821C                                                    \\\n\t(BIT_MASK_RXPKTLMT_8821C << BIT_SHIFT_RXPKTLMT_8821C)\n#define BIT_CLEAR_RXPKTLMT_8821C(x) ((x) & (~BITS_RXPKTLMT_8821C))\n#define BIT_GET_RXPKTLMT_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RXPKTLMT_8821C) & BIT_MASK_RXPKTLMT_8821C)\n#define BIT_SET_RXPKTLMT_8821C(x, v)                                           \\\n\t(BIT_CLEAR_RXPKTLMT_8821C(x) | BIT_RXPKTLMT_8821C(v))\n\n/* 2 REG_RX_DLK_TIME_8821C (RX DEADLOCK TIME REGISTER) */\n\n#define BIT_SHIFT_RX_DLK_TIME_8821C 0\n#define BIT_MASK_RX_DLK_TIME_8821C 0xff\n#define BIT_RX_DLK_TIME_8821C(x)                                               \\\n\t(((x) & BIT_MASK_RX_DLK_TIME_8821C) << BIT_SHIFT_RX_DLK_TIME_8821C)\n#define BITS_RX_DLK_TIME_8821C                                                 \\\n\t(BIT_MASK_RX_DLK_TIME_8821C << BIT_SHIFT_RX_DLK_TIME_8821C)\n#define BIT_CLEAR_RX_DLK_TIME_8821C(x) ((x) & (~BITS_RX_DLK_TIME_8821C))\n#define BIT_GET_RX_DLK_TIME_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RX_DLK_TIME_8821C) & BIT_MASK_RX_DLK_TIME_8821C)\n#define BIT_SET_RX_DLK_TIME_8821C(x, v)                                        \\\n\t(BIT_CLEAR_RX_DLK_TIME_8821C(x) | BIT_RX_DLK_TIME_8821C(v))\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RX_DRVINFO_SZ_8821C (RX DRIVER INFO SIZE REGISTER) */\n#define BIT_PHYSTS_PER_PKT_MODE_8821C BIT(7)\n\n#define BIT_SHIFT_DRVINFO_SZ_V1_8821C 0\n#define BIT_MASK_DRVINFO_SZ_V1_8821C 0xf\n#define BIT_DRVINFO_SZ_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_DRVINFO_SZ_V1_8821C) << BIT_SHIFT_DRVINFO_SZ_V1_8821C)\n#define BITS_DRVINFO_SZ_V1_8821C                                               \\\n\t(BIT_MASK_DRVINFO_SZ_V1_8821C << BIT_SHIFT_DRVINFO_SZ_V1_8821C)\n#define BIT_CLEAR_DRVINFO_SZ_V1_8821C(x) ((x) & (~BITS_DRVINFO_SZ_V1_8821C))\n#define BIT_GET_DRVINFO_SZ_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8821C) & BIT_MASK_DRVINFO_SZ_V1_8821C)\n#define BIT_SET_DRVINFO_SZ_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_DRVINFO_SZ_V1_8821C(x) | BIT_DRVINFO_SZ_V1_8821C(v))\n\n/* 2 REG_MACID_8821C\t(MAC ID REGISTER) */\n\n#define BIT_SHIFT_MACID_V1_8821C 0\n#define BIT_MASK_MACID_V1_8821C 0xffffffffL\n#define BIT_MACID_V1_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_MACID_V1_8821C) << BIT_SHIFT_MACID_V1_8821C)\n#define BITS_MACID_V1_8821C                                                    \\\n\t(BIT_MASK_MACID_V1_8821C << BIT_SHIFT_MACID_V1_8821C)\n#define BIT_CLEAR_MACID_V1_8821C(x) ((x) & (~BITS_MACID_V1_8821C))\n#define BIT_GET_MACID_V1_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_MACID_V1_8821C) & BIT_MASK_MACID_V1_8821C)\n#define BIT_SET_MACID_V1_8821C(x, v)                                           \\\n\t(BIT_CLEAR_MACID_V1_8821C(x) | BIT_MACID_V1_8821C(v))\n\n/* 2 REG_MACID_H_8821C\t(MAC ID REGISTER) */\n\n#define BIT_SHIFT_MACID_H_V1_8821C 0\n#define BIT_MASK_MACID_H_V1_8821C 0xffff\n#define BIT_MACID_H_V1_8821C(x)                                                \\\n\t(((x) & BIT_MASK_MACID_H_V1_8821C) << BIT_SHIFT_MACID_H_V1_8821C)\n#define BITS_MACID_H_V1_8821C                                                  \\\n\t(BIT_MASK_MACID_H_V1_8821C << BIT_SHIFT_MACID_H_V1_8821C)\n#define BIT_CLEAR_MACID_H_V1_8821C(x) ((x) & (~BITS_MACID_H_V1_8821C))\n#define BIT_GET_MACID_H_V1_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_MACID_H_V1_8821C) & BIT_MASK_MACID_H_V1_8821C)\n#define BIT_SET_MACID_H_V1_8821C(x, v)                                         \\\n\t(BIT_CLEAR_MACID_H_V1_8821C(x) | BIT_MACID_H_V1_8821C(v))\n\n/* 2 REG_BSSID_8821C (BSSID REGISTER) */\n\n#define BIT_SHIFT_BSSID_V1_8821C 0\n#define BIT_MASK_BSSID_V1_8821C 0xffffffffL\n#define BIT_BSSID_V1_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_BSSID_V1_8821C) << BIT_SHIFT_BSSID_V1_8821C)\n#define BITS_BSSID_V1_8821C                                                    \\\n\t(BIT_MASK_BSSID_V1_8821C << BIT_SHIFT_BSSID_V1_8821C)\n#define BIT_CLEAR_BSSID_V1_8821C(x) ((x) & (~BITS_BSSID_V1_8821C))\n#define BIT_GET_BSSID_V1_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_BSSID_V1_8821C) & BIT_MASK_BSSID_V1_8821C)\n#define BIT_SET_BSSID_V1_8821C(x, v)                                           \\\n\t(BIT_CLEAR_BSSID_V1_8821C(x) | BIT_BSSID_V1_8821C(v))\n\n/* 2 REG_BSSID_H_8821C\t(BSSID REGISTER) */\n\n/* 2 REG_NOT_VALID_8821C */\n\n#define BIT_SHIFT_BSSID_H_V1_8821C 0\n#define BIT_MASK_BSSID_H_V1_8821C 0xffff\n#define BIT_BSSID_H_V1_8821C(x)                                                \\\n\t(((x) & BIT_MASK_BSSID_H_V1_8821C) << BIT_SHIFT_BSSID_H_V1_8821C)\n#define BITS_BSSID_H_V1_8821C                                                  \\\n\t(BIT_MASK_BSSID_H_V1_8821C << BIT_SHIFT_BSSID_H_V1_8821C)\n#define BIT_CLEAR_BSSID_H_V1_8821C(x) ((x) & (~BITS_BSSID_H_V1_8821C))\n#define BIT_GET_BSSID_H_V1_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BSSID_H_V1_8821C) & BIT_MASK_BSSID_H_V1_8821C)\n#define BIT_SET_BSSID_H_V1_8821C(x, v)                                         \\\n\t(BIT_CLEAR_BSSID_H_V1_8821C(x) | BIT_BSSID_H_V1_8821C(v))\n\n/* 2 REG_MAR_8821C (MULTICAST ADDRESS REGISTER) */\n\n#define BIT_SHIFT_MAR_V1_8821C 0\n#define BIT_MASK_MAR_V1_8821C 0xffffffffL\n#define BIT_MAR_V1_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_MAR_V1_8821C) << BIT_SHIFT_MAR_V1_8821C)\n#define BITS_MAR_V1_8821C (BIT_MASK_MAR_V1_8821C << BIT_SHIFT_MAR_V1_8821C)\n#define BIT_CLEAR_MAR_V1_8821C(x) ((x) & (~BITS_MAR_V1_8821C))\n#define BIT_GET_MAR_V1_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_MAR_V1_8821C) & BIT_MASK_MAR_V1_8821C)\n#define BIT_SET_MAR_V1_8821C(x, v)                                             \\\n\t(BIT_CLEAR_MAR_V1_8821C(x) | BIT_MAR_V1_8821C(v))\n\n/* 2 REG_MAR_H_8821C (MULTICAST ADDRESS REGISTER) */\n\n#define BIT_SHIFT_MAR_H_V1_8821C 0\n#define BIT_MASK_MAR_H_V1_8821C 0xffffffffL\n#define BIT_MAR_H_V1_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_MAR_H_V1_8821C) << BIT_SHIFT_MAR_H_V1_8821C)\n#define BITS_MAR_H_V1_8821C                                                    \\\n\t(BIT_MASK_MAR_H_V1_8821C << BIT_SHIFT_MAR_H_V1_8821C)\n#define BIT_CLEAR_MAR_H_V1_8821C(x) ((x) & (~BITS_MAR_H_V1_8821C))\n#define BIT_GET_MAR_H_V1_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_MAR_H_V1_8821C) & BIT_MASK_MAR_H_V1_8821C)\n#define BIT_SET_MAR_H_V1_8821C(x, v)                                           \\\n\t(BIT_CLEAR_MAR_H_V1_8821C(x) | BIT_MAR_H_V1_8821C(v))\n\n/* 2 REG_MBIDCAMCFG_1_8821C (MBSSID CAM CONFIGURATION REGISTER) */\n\n#define BIT_SHIFT_MBIDCAM_RWDATA_L_8821C 0\n#define BIT_MASK_MBIDCAM_RWDATA_L_8821C 0xffffffffL\n#define BIT_MBIDCAM_RWDATA_L_8821C(x)                                          \\\n\t(((x) & BIT_MASK_MBIDCAM_RWDATA_L_8821C)                               \\\n\t << BIT_SHIFT_MBIDCAM_RWDATA_L_8821C)\n#define BITS_MBIDCAM_RWDATA_L_8821C                                            \\\n\t(BIT_MASK_MBIDCAM_RWDATA_L_8821C << BIT_SHIFT_MBIDCAM_RWDATA_L_8821C)\n#define BIT_CLEAR_MBIDCAM_RWDATA_L_8821C(x)                                    \\\n\t((x) & (~BITS_MBIDCAM_RWDATA_L_8821C))\n#define BIT_GET_MBIDCAM_RWDATA_L_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8821C) &                           \\\n\t BIT_MASK_MBIDCAM_RWDATA_L_8821C)\n#define BIT_SET_MBIDCAM_RWDATA_L_8821C(x, v)                                   \\\n\t(BIT_CLEAR_MBIDCAM_RWDATA_L_8821C(x) | BIT_MBIDCAM_RWDATA_L_8821C(v))\n\n/* 2 REG_MBIDCAMCFG_2_8821C (MBSSID CAM CONFIGURATION REGISTER) */\n#define BIT_MBIDCAM_POLL_8821C BIT(31)\n#define BIT_MBIDCAM_WT_EN_8821C BIT(30)\n\n#define BIT_SHIFT_MBIDCAM_ADDR_8821C 24\n#define BIT_MASK_MBIDCAM_ADDR_8821C 0x1f\n#define BIT_MBIDCAM_ADDR_8821C(x)                                              \\\n\t(((x) & BIT_MASK_MBIDCAM_ADDR_8821C) << BIT_SHIFT_MBIDCAM_ADDR_8821C)\n#define BITS_MBIDCAM_ADDR_8821C                                                \\\n\t(BIT_MASK_MBIDCAM_ADDR_8821C << BIT_SHIFT_MBIDCAM_ADDR_8821C)\n#define BIT_CLEAR_MBIDCAM_ADDR_8821C(x) ((x) & (~BITS_MBIDCAM_ADDR_8821C))\n#define BIT_GET_MBIDCAM_ADDR_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_MBIDCAM_ADDR_8821C) & BIT_MASK_MBIDCAM_ADDR_8821C)\n#define BIT_SET_MBIDCAM_ADDR_8821C(x, v)                                       \\\n\t(BIT_CLEAR_MBIDCAM_ADDR_8821C(x) | BIT_MBIDCAM_ADDR_8821C(v))\n\n#define BIT_MBIDCAM_VALID_8821C BIT(23)\n#define BIT_LSIC_TXOP_EN_8821C BIT(17)\n#define BIT_CTS_EN_8821C BIT(16)\n\n#define BIT_SHIFT_MBIDCAM_RWDATA_H_8821C 0\n#define BIT_MASK_MBIDCAM_RWDATA_H_8821C 0xffff\n#define BIT_MBIDCAM_RWDATA_H_8821C(x)                                          \\\n\t(((x) & BIT_MASK_MBIDCAM_RWDATA_H_8821C)                               \\\n\t << BIT_SHIFT_MBIDCAM_RWDATA_H_8821C)\n#define BITS_MBIDCAM_RWDATA_H_8821C                                            \\\n\t(BIT_MASK_MBIDCAM_RWDATA_H_8821C << BIT_SHIFT_MBIDCAM_RWDATA_H_8821C)\n#define BIT_CLEAR_MBIDCAM_RWDATA_H_8821C(x)                                    \\\n\t((x) & (~BITS_MBIDCAM_RWDATA_H_8821C))\n#define BIT_GET_MBIDCAM_RWDATA_H_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8821C) &                           \\\n\t BIT_MASK_MBIDCAM_RWDATA_H_8821C)\n#define BIT_SET_MBIDCAM_RWDATA_H_8821C(x, v)                                   \\\n\t(BIT_CLEAR_MBIDCAM_RWDATA_H_8821C(x) | BIT_MBIDCAM_RWDATA_H_8821C(v))\n\n/* 2 REG_WMAC_TCR_TSFT_OFS_8821C */\n\n#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C 0\n#define BIT_MASK_WMAC_TCR_TSFT_OFS_8821C 0xffff\n#define BIT_WMAC_TCR_TSFT_OFS_8821C(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8821C)                              \\\n\t << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C)\n#define BITS_WMAC_TCR_TSFT_OFS_8821C                                           \\\n\t(BIT_MASK_WMAC_TCR_TSFT_OFS_8821C << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C)\n#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8821C(x)                                   \\\n\t((x) & (~BITS_WMAC_TCR_TSFT_OFS_8821C))\n#define BIT_GET_WMAC_TCR_TSFT_OFS_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C) &                          \\\n\t BIT_MASK_WMAC_TCR_TSFT_OFS_8821C)\n#define BIT_SET_WMAC_TCR_TSFT_OFS_8821C(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_TCR_TSFT_OFS_8821C(x) | BIT_WMAC_TCR_TSFT_OFS_8821C(v))\n\n/* 2 REG_UDF_THSD_8821C */\n\n#define BIT_SHIFT_UDF_THSD_8821C 0\n#define BIT_MASK_UDF_THSD_8821C 0xff\n#define BIT_UDF_THSD_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_UDF_THSD_8821C) << BIT_SHIFT_UDF_THSD_8821C)\n#define BITS_UDF_THSD_8821C                                                    \\\n\t(BIT_MASK_UDF_THSD_8821C << BIT_SHIFT_UDF_THSD_8821C)\n#define BIT_CLEAR_UDF_THSD_8821C(x) ((x) & (~BITS_UDF_THSD_8821C))\n#define BIT_GET_UDF_THSD_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_UDF_THSD_8821C) & BIT_MASK_UDF_THSD_8821C)\n#define BIT_SET_UDF_THSD_8821C(x, v)                                           \\\n\t(BIT_CLEAR_UDF_THSD_8821C(x) | BIT_UDF_THSD_8821C(v))\n\n/* 2 REG_ZLD_NUM_8821C */\n\n#define BIT_SHIFT_ZLD_NUM_8821C 0\n#define BIT_MASK_ZLD_NUM_8821C 0xff\n#define BIT_ZLD_NUM_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_ZLD_NUM_8821C) << BIT_SHIFT_ZLD_NUM_8821C)\n#define BITS_ZLD_NUM_8821C (BIT_MASK_ZLD_NUM_8821C << BIT_SHIFT_ZLD_NUM_8821C)\n#define BIT_CLEAR_ZLD_NUM_8821C(x) ((x) & (~BITS_ZLD_NUM_8821C))\n#define BIT_GET_ZLD_NUM_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_ZLD_NUM_8821C) & BIT_MASK_ZLD_NUM_8821C)\n#define BIT_SET_ZLD_NUM_8821C(x, v)                                            \\\n\t(BIT_CLEAR_ZLD_NUM_8821C(x) | BIT_ZLD_NUM_8821C(v))\n\n/* 2 REG_STMP_THSD_8821C */\n\n#define BIT_SHIFT_STMP_THSD_8821C 0\n#define BIT_MASK_STMP_THSD_8821C 0xff\n#define BIT_STMP_THSD_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_STMP_THSD_8821C) << BIT_SHIFT_STMP_THSD_8821C)\n#define BITS_STMP_THSD_8821C                                                   \\\n\t(BIT_MASK_STMP_THSD_8821C << BIT_SHIFT_STMP_THSD_8821C)\n#define BIT_CLEAR_STMP_THSD_8821C(x) ((x) & (~BITS_STMP_THSD_8821C))\n#define BIT_GET_STMP_THSD_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_STMP_THSD_8821C) & BIT_MASK_STMP_THSD_8821C)\n#define BIT_SET_STMP_THSD_8821C(x, v)                                          \\\n\t(BIT_CLEAR_STMP_THSD_8821C(x) | BIT_STMP_THSD_8821C(v))\n\n/* 2 REG_WMAC_TXTIMEOUT_8821C */\n\n#define BIT_SHIFT_WMAC_TXTIMEOUT_8821C 0\n#define BIT_MASK_WMAC_TXTIMEOUT_8821C 0xff\n#define BIT_WMAC_TXTIMEOUT_8821C(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_TXTIMEOUT_8821C)                                 \\\n\t << BIT_SHIFT_WMAC_TXTIMEOUT_8821C)\n#define BITS_WMAC_TXTIMEOUT_8821C                                              \\\n\t(BIT_MASK_WMAC_TXTIMEOUT_8821C << BIT_SHIFT_WMAC_TXTIMEOUT_8821C)\n#define BIT_CLEAR_WMAC_TXTIMEOUT_8821C(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8821C))\n#define BIT_GET_WMAC_TXTIMEOUT_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8821C) &                             \\\n\t BIT_MASK_WMAC_TXTIMEOUT_8821C)\n#define BIT_SET_WMAC_TXTIMEOUT_8821C(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_TXTIMEOUT_8821C(x) | BIT_WMAC_TXTIMEOUT_8821C(v))\n\n/* 2 REG_MCU_TEST_2_V1_8821C */\n\n#define BIT_SHIFT_MCU_RSVD_2_V1_8821C 0\n#define BIT_MASK_MCU_RSVD_2_V1_8821C 0xffff\n#define BIT_MCU_RSVD_2_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_MCU_RSVD_2_V1_8821C) << BIT_SHIFT_MCU_RSVD_2_V1_8821C)\n#define BITS_MCU_RSVD_2_V1_8821C                                               \\\n\t(BIT_MASK_MCU_RSVD_2_V1_8821C << BIT_SHIFT_MCU_RSVD_2_V1_8821C)\n#define BIT_CLEAR_MCU_RSVD_2_V1_8821C(x) ((x) & (~BITS_MCU_RSVD_2_V1_8821C))\n#define BIT_GET_MCU_RSVD_2_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8821C) & BIT_MASK_MCU_RSVD_2_V1_8821C)\n#define BIT_SET_MCU_RSVD_2_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_MCU_RSVD_2_V1_8821C(x) | BIT_MCU_RSVD_2_V1_8821C(v))\n\n/* 2 REG_USTIME_EDCA_8821C (US TIME TUNING FOR EDCA REGISTER) */\n\n#define BIT_SHIFT_USTIME_EDCA_8821C 0\n#define BIT_MASK_USTIME_EDCA_8821C 0xff\n#define BIT_USTIME_EDCA_8821C(x)                                               \\\n\t(((x) & BIT_MASK_USTIME_EDCA_8821C) << BIT_SHIFT_USTIME_EDCA_8821C)\n#define BITS_USTIME_EDCA_8821C                                                 \\\n\t(BIT_MASK_USTIME_EDCA_8821C << BIT_SHIFT_USTIME_EDCA_8821C)\n#define BIT_CLEAR_USTIME_EDCA_8821C(x) ((x) & (~BITS_USTIME_EDCA_8821C))\n#define BIT_GET_USTIME_EDCA_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_USTIME_EDCA_8821C) & BIT_MASK_USTIME_EDCA_8821C)\n#define BIT_SET_USTIME_EDCA_8821C(x, v)                                        \\\n\t(BIT_CLEAR_USTIME_EDCA_8821C(x) | BIT_USTIME_EDCA_8821C(v))\n\n/* 2 REG_ACKTO_CCK_8821C (ACK TIMEOUT REGISTER FOR CCK RATE) */\n\n#define BIT_SHIFT_ACKTO_CCK_8821C 0\n#define BIT_MASK_ACKTO_CCK_8821C 0xff\n#define BIT_ACKTO_CCK_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_ACKTO_CCK_8821C) << BIT_SHIFT_ACKTO_CCK_8821C)\n#define BITS_ACKTO_CCK_8821C                                                   \\\n\t(BIT_MASK_ACKTO_CCK_8821C << BIT_SHIFT_ACKTO_CCK_8821C)\n#define BIT_CLEAR_ACKTO_CCK_8821C(x) ((x) & (~BITS_ACKTO_CCK_8821C))\n#define BIT_GET_ACKTO_CCK_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_ACKTO_CCK_8821C) & BIT_MASK_ACKTO_CCK_8821C)\n#define BIT_SET_ACKTO_CCK_8821C(x, v)                                          \\\n\t(BIT_CLEAR_ACKTO_CCK_8821C(x) | BIT_ACKTO_CCK_8821C(v))\n\n/* 2 REG_MAC_SPEC_SIFS_8821C (SPECIFICATION SIFS REGISTER) */\n\n#define BIT_SHIFT_SPEC_SIFS_OFDM_8821C 8\n#define BIT_MASK_SPEC_SIFS_OFDM_8821C 0xff\n#define BIT_SPEC_SIFS_OFDM_8821C(x)                                            \\\n\t(((x) & BIT_MASK_SPEC_SIFS_OFDM_8821C)                                 \\\n\t << BIT_SHIFT_SPEC_SIFS_OFDM_8821C)\n#define BITS_SPEC_SIFS_OFDM_8821C                                              \\\n\t(BIT_MASK_SPEC_SIFS_OFDM_8821C << BIT_SHIFT_SPEC_SIFS_OFDM_8821C)\n#define BIT_CLEAR_SPEC_SIFS_OFDM_8821C(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8821C))\n#define BIT_GET_SPEC_SIFS_OFDM_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8821C) &                             \\\n\t BIT_MASK_SPEC_SIFS_OFDM_8821C)\n#define BIT_SET_SPEC_SIFS_OFDM_8821C(x, v)                                     \\\n\t(BIT_CLEAR_SPEC_SIFS_OFDM_8821C(x) | BIT_SPEC_SIFS_OFDM_8821C(v))\n\n#define BIT_SHIFT_SPEC_SIFS_CCK_8821C 0\n#define BIT_MASK_SPEC_SIFS_CCK_8821C 0xff\n#define BIT_SPEC_SIFS_CCK_8821C(x)                                             \\\n\t(((x) & BIT_MASK_SPEC_SIFS_CCK_8821C) << BIT_SHIFT_SPEC_SIFS_CCK_8821C)\n#define BITS_SPEC_SIFS_CCK_8821C                                               \\\n\t(BIT_MASK_SPEC_SIFS_CCK_8821C << BIT_SHIFT_SPEC_SIFS_CCK_8821C)\n#define BIT_CLEAR_SPEC_SIFS_CCK_8821C(x) ((x) & (~BITS_SPEC_SIFS_CCK_8821C))\n#define BIT_GET_SPEC_SIFS_CCK_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8821C) & BIT_MASK_SPEC_SIFS_CCK_8821C)\n#define BIT_SET_SPEC_SIFS_CCK_8821C(x, v)                                      \\\n\t(BIT_CLEAR_SPEC_SIFS_CCK_8821C(x) | BIT_SPEC_SIFS_CCK_8821C(v))\n\n/* 2 REG_RESP_SIFS_CCK_8821C (RESPONSE SIFS FOR CCK REGISTER) */\n\n#define BIT_SHIFT_SIFS_R2T_CCK_8821C 8\n#define BIT_MASK_SIFS_R2T_CCK_8821C 0xff\n#define BIT_SIFS_R2T_CCK_8821C(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_R2T_CCK_8821C) << BIT_SHIFT_SIFS_R2T_CCK_8821C)\n#define BITS_SIFS_R2T_CCK_8821C                                                \\\n\t(BIT_MASK_SIFS_R2T_CCK_8821C << BIT_SHIFT_SIFS_R2T_CCK_8821C)\n#define BIT_CLEAR_SIFS_R2T_CCK_8821C(x) ((x) & (~BITS_SIFS_R2T_CCK_8821C))\n#define BIT_GET_SIFS_R2T_CCK_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_R2T_CCK_8821C) & BIT_MASK_SIFS_R2T_CCK_8821C)\n#define BIT_SET_SIFS_R2T_CCK_8821C(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_R2T_CCK_8821C(x) | BIT_SIFS_R2T_CCK_8821C(v))\n\n#define BIT_SHIFT_SIFS_T2T_CCK_8821C 0\n#define BIT_MASK_SIFS_T2T_CCK_8821C 0xff\n#define BIT_SIFS_T2T_CCK_8821C(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_T2T_CCK_8821C) << BIT_SHIFT_SIFS_T2T_CCK_8821C)\n#define BITS_SIFS_T2T_CCK_8821C                                                \\\n\t(BIT_MASK_SIFS_T2T_CCK_8821C << BIT_SHIFT_SIFS_T2T_CCK_8821C)\n#define BIT_CLEAR_SIFS_T2T_CCK_8821C(x) ((x) & (~BITS_SIFS_T2T_CCK_8821C))\n#define BIT_GET_SIFS_T2T_CCK_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_T2T_CCK_8821C) & BIT_MASK_SIFS_T2T_CCK_8821C)\n#define BIT_SET_SIFS_T2T_CCK_8821C(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_T2T_CCK_8821C(x) | BIT_SIFS_T2T_CCK_8821C(v))\n\n/* 2 REG_RESP_SIFS_OFDM_8821C (RESPONSE SIFS FOR OFDM REGISTER) */\n\n#define BIT_SHIFT_SIFS_R2T_OFDM_8821C 8\n#define BIT_MASK_SIFS_R2T_OFDM_8821C 0xff\n#define BIT_SIFS_R2T_OFDM_8821C(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_R2T_OFDM_8821C) << BIT_SHIFT_SIFS_R2T_OFDM_8821C)\n#define BITS_SIFS_R2T_OFDM_8821C                                               \\\n\t(BIT_MASK_SIFS_R2T_OFDM_8821C << BIT_SHIFT_SIFS_R2T_OFDM_8821C)\n#define BIT_CLEAR_SIFS_R2T_OFDM_8821C(x) ((x) & (~BITS_SIFS_R2T_OFDM_8821C))\n#define BIT_GET_SIFS_R2T_OFDM_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8821C) & BIT_MASK_SIFS_R2T_OFDM_8821C)\n#define BIT_SET_SIFS_R2T_OFDM_8821C(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_R2T_OFDM_8821C(x) | BIT_SIFS_R2T_OFDM_8821C(v))\n\n#define BIT_SHIFT_SIFS_T2T_OFDM_8821C 0\n#define BIT_MASK_SIFS_T2T_OFDM_8821C 0xff\n#define BIT_SIFS_T2T_OFDM_8821C(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_T2T_OFDM_8821C) << BIT_SHIFT_SIFS_T2T_OFDM_8821C)\n#define BITS_SIFS_T2T_OFDM_8821C                                               \\\n\t(BIT_MASK_SIFS_T2T_OFDM_8821C << BIT_SHIFT_SIFS_T2T_OFDM_8821C)\n#define BIT_CLEAR_SIFS_T2T_OFDM_8821C(x) ((x) & (~BITS_SIFS_T2T_OFDM_8821C))\n#define BIT_GET_SIFS_T2T_OFDM_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8821C) & BIT_MASK_SIFS_T2T_OFDM_8821C)\n#define BIT_SET_SIFS_T2T_OFDM_8821C(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_T2T_OFDM_8821C(x) | BIT_SIFS_T2T_OFDM_8821C(v))\n\n/* 2 REG_ACKTO_8821C (ACK TIMEOUT REGISTER) */\n\n#define BIT_SHIFT_ACKTO_8821C 0\n#define BIT_MASK_ACKTO_8821C 0xff\n#define BIT_ACKTO_8821C(x)                                                     \\\n\t(((x) & BIT_MASK_ACKTO_8821C) << BIT_SHIFT_ACKTO_8821C)\n#define BITS_ACKTO_8821C (BIT_MASK_ACKTO_8821C << BIT_SHIFT_ACKTO_8821C)\n#define BIT_CLEAR_ACKTO_8821C(x) ((x) & (~BITS_ACKTO_8821C))\n#define BIT_GET_ACKTO_8821C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ACKTO_8821C) & BIT_MASK_ACKTO_8821C)\n#define BIT_SET_ACKTO_8821C(x, v)                                              \\\n\t(BIT_CLEAR_ACKTO_8821C(x) | BIT_ACKTO_8821C(v))\n\n/* 2 REG_CTS2TO_8821C (CTS2 TIMEOUT REGISTER) */\n\n#define BIT_SHIFT_CTS2TO_8821C 0\n#define BIT_MASK_CTS2TO_8821C 0xff\n#define BIT_CTS2TO_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_CTS2TO_8821C) << BIT_SHIFT_CTS2TO_8821C)\n#define BITS_CTS2TO_8821C (BIT_MASK_CTS2TO_8821C << BIT_SHIFT_CTS2TO_8821C)\n#define BIT_CLEAR_CTS2TO_8821C(x) ((x) & (~BITS_CTS2TO_8821C))\n#define BIT_GET_CTS2TO_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_CTS2TO_8821C) & BIT_MASK_CTS2TO_8821C)\n#define BIT_SET_CTS2TO_8821C(x, v)                                             \\\n\t(BIT_CLEAR_CTS2TO_8821C(x) | BIT_CTS2TO_8821C(v))\n\n/* 2 REG_EIFS_8821C (EIFS REGISTER) */\n\n#define BIT_SHIFT_EIFS_8821C 0\n#define BIT_MASK_EIFS_8821C 0xffff\n#define BIT_EIFS_8821C(x) (((x) & BIT_MASK_EIFS_8821C) << BIT_SHIFT_EIFS_8821C)\n#define BITS_EIFS_8821C (BIT_MASK_EIFS_8821C << BIT_SHIFT_EIFS_8821C)\n#define BIT_CLEAR_EIFS_8821C(x) ((x) & (~BITS_EIFS_8821C))\n#define BIT_GET_EIFS_8821C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_EIFS_8821C) & BIT_MASK_EIFS_8821C)\n#define BIT_SET_EIFS_8821C(x, v) (BIT_CLEAR_EIFS_8821C(x) | BIT_EIFS_8821C(v))\n\n/* 2 REG_RPFM_MAP0_8821C */\n#define BIT_MGT_RPFM15EN_8821C BIT(15)\n#define BIT_MGT_RPFM14EN_8821C BIT(14)\n#define BIT_MGT_RPFM13EN_8821C BIT(13)\n#define BIT_MGT_RPFM12EN_8821C BIT(12)\n#define BIT_MGT_RPFM11EN_8821C BIT(11)\n#define BIT_MGT_RPFM10EN_8821C BIT(10)\n#define BIT_MGT_RPFM9EN_8821C BIT(9)\n#define BIT_MGT_RPFM8EN_8821C BIT(8)\n#define BIT_MGT_RPFM7EN_8821C BIT(7)\n#define BIT_MGT_RPFM6EN_8821C BIT(6)\n#define BIT_MGT_RPFM5EN_8821C BIT(5)\n#define BIT_MGT_RPFM4EN_8821C BIT(4)\n#define BIT_MGT_RPFM3EN_8821C BIT(3)\n#define BIT_MGT_RPFM2EN_8821C BIT(2)\n#define BIT_MGT_RPFM1EN_8821C BIT(1)\n#define BIT_MGT_RPFM0EN_8821C BIT(0)\n\n/* 2 REG_RPFM_MAP1_V1_8821C */\n#define BIT_DATA_RPFM15EN_8821C BIT(15)\n#define BIT_DATA_RPFM14EN_8821C BIT(14)\n#define BIT_DATA_RPFM13EN_8821C BIT(13)\n#define BIT_DATA_RPFM12EN_8821C BIT(12)\n#define BIT_DATA_RPFM11EN_8821C BIT(11)\n#define BIT_DATA_RPFM10EN_8821C BIT(10)\n#define BIT_DATA_RPFM9EN_8821C BIT(9)\n#define BIT_DATA_RPFM8EN_8821C BIT(8)\n#define BIT_DATA_RPFM7EN_8821C BIT(7)\n#define BIT_DATA_RPFM6EN_8821C BIT(6)\n#define BIT_DATA_RPFM5EN_8821C BIT(5)\n#define BIT_DATA_RPFM4EN_8821C BIT(4)\n#define BIT_DATA_RPFM3EN_8821C BIT(3)\n#define BIT_DATA_RPFM2EN_8821C BIT(2)\n#define BIT_DATA_RPFM1EN_8821C BIT(1)\n#define BIT_DATA_RPFM0EN_8821C BIT(0)\n\n/* 2 REG_RPFM_CAM_CMD_8821C (RX PAYLOAD FRAME MASK CAM COMMAND REGISTER) */\n#define BIT_RPFM_CAM_POLLING_8821C BIT(31)\n#define BIT_RPFM_CAM_CLR_8821C BIT(30)\n#define BIT_RPFM_CAM_WE_8821C BIT(16)\n\n#define BIT_SHIFT_RPFM_CAM_ADDR_8821C 0\n#define BIT_MASK_RPFM_CAM_ADDR_8821C 0x7f\n#define BIT_RPFM_CAM_ADDR_8821C(x)                                             \\\n\t(((x) & BIT_MASK_RPFM_CAM_ADDR_8821C) << BIT_SHIFT_RPFM_CAM_ADDR_8821C)\n#define BITS_RPFM_CAM_ADDR_8821C                                               \\\n\t(BIT_MASK_RPFM_CAM_ADDR_8821C << BIT_SHIFT_RPFM_CAM_ADDR_8821C)\n#define BIT_CLEAR_RPFM_CAM_ADDR_8821C(x) ((x) & (~BITS_RPFM_CAM_ADDR_8821C))\n#define BIT_GET_RPFM_CAM_ADDR_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8821C) & BIT_MASK_RPFM_CAM_ADDR_8821C)\n#define BIT_SET_RPFM_CAM_ADDR_8821C(x, v)                                      \\\n\t(BIT_CLEAR_RPFM_CAM_ADDR_8821C(x) | BIT_RPFM_CAM_ADDR_8821C(v))\n\n/* 2 REG_RPFM_CAM_RWD_8821C (ACK TIMEOUT REGISTER) */\n\n#define BIT_SHIFT_RPFM_CAM_RWD_8821C 0\n#define BIT_MASK_RPFM_CAM_RWD_8821C 0xffffffffL\n#define BIT_RPFM_CAM_RWD_8821C(x)                                              \\\n\t(((x) & BIT_MASK_RPFM_CAM_RWD_8821C) << BIT_SHIFT_RPFM_CAM_RWD_8821C)\n#define BITS_RPFM_CAM_RWD_8821C                                                \\\n\t(BIT_MASK_RPFM_CAM_RWD_8821C << BIT_SHIFT_RPFM_CAM_RWD_8821C)\n#define BIT_CLEAR_RPFM_CAM_RWD_8821C(x) ((x) & (~BITS_RPFM_CAM_RWD_8821C))\n#define BIT_GET_RPFM_CAM_RWD_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RPFM_CAM_RWD_8821C) & BIT_MASK_RPFM_CAM_RWD_8821C)\n#define BIT_SET_RPFM_CAM_RWD_8821C(x, v)                                       \\\n\t(BIT_CLEAR_RPFM_CAM_RWD_8821C(x) | BIT_RPFM_CAM_RWD_8821C(v))\n\n/* 2 REG_NAV_CTRL_8821C (NAV CONTROL REGISTER) */\n\n#define BIT_SHIFT_NAV_UPPER_8821C 16\n#define BIT_MASK_NAV_UPPER_8821C 0xff\n#define BIT_NAV_UPPER_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_NAV_UPPER_8821C) << BIT_SHIFT_NAV_UPPER_8821C)\n#define BITS_NAV_UPPER_8821C                                                   \\\n\t(BIT_MASK_NAV_UPPER_8821C << BIT_SHIFT_NAV_UPPER_8821C)\n#define BIT_CLEAR_NAV_UPPER_8821C(x) ((x) & (~BITS_NAV_UPPER_8821C))\n#define BIT_GET_NAV_UPPER_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_NAV_UPPER_8821C) & BIT_MASK_NAV_UPPER_8821C)\n#define BIT_SET_NAV_UPPER_8821C(x, v)                                          \\\n\t(BIT_CLEAR_NAV_UPPER_8821C(x) | BIT_NAV_UPPER_8821C(v))\n\n#define BIT_SHIFT_RXMYRTS_NAV_8821C 8\n#define BIT_MASK_RXMYRTS_NAV_8821C 0xf\n#define BIT_RXMYRTS_NAV_8821C(x)                                               \\\n\t(((x) & BIT_MASK_RXMYRTS_NAV_8821C) << BIT_SHIFT_RXMYRTS_NAV_8821C)\n#define BITS_RXMYRTS_NAV_8821C                                                 \\\n\t(BIT_MASK_RXMYRTS_NAV_8821C << BIT_SHIFT_RXMYRTS_NAV_8821C)\n#define BIT_CLEAR_RXMYRTS_NAV_8821C(x) ((x) & (~BITS_RXMYRTS_NAV_8821C))\n#define BIT_GET_RXMYRTS_NAV_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RXMYRTS_NAV_8821C) & BIT_MASK_RXMYRTS_NAV_8821C)\n#define BIT_SET_RXMYRTS_NAV_8821C(x, v)                                        \\\n\t(BIT_CLEAR_RXMYRTS_NAV_8821C(x) | BIT_RXMYRTS_NAV_8821C(v))\n\n#define BIT_SHIFT_RTSRST_8821C 0\n#define BIT_MASK_RTSRST_8821C 0xff\n#define BIT_RTSRST_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_RTSRST_8821C) << BIT_SHIFT_RTSRST_8821C)\n#define BITS_RTSRST_8821C (BIT_MASK_RTSRST_8821C << BIT_SHIFT_RTSRST_8821C)\n#define BIT_CLEAR_RTSRST_8821C(x) ((x) & (~BITS_RTSRST_8821C))\n#define BIT_GET_RTSRST_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_RTSRST_8821C) & BIT_MASK_RTSRST_8821C)\n#define BIT_SET_RTSRST_8821C(x, v)                                             \\\n\t(BIT_CLEAR_RTSRST_8821C(x) | BIT_RTSRST_8821C(v))\n\n/* 2 REG_BACAMCMD_8821C (BLOCK ACK CAM COMMAND REGISTER) */\n#define BIT_BACAM_POLL_8821C BIT(31)\n#define BIT_BACAM_RST_8821C BIT(17)\n#define BIT_BACAM_RW_8821C BIT(16)\n\n#define BIT_SHIFT_TXSBM_8821C 14\n#define BIT_MASK_TXSBM_8821C 0x3\n#define BIT_TXSBM_8821C(x)                                                     \\\n\t(((x) & BIT_MASK_TXSBM_8821C) << BIT_SHIFT_TXSBM_8821C)\n#define BITS_TXSBM_8821C (BIT_MASK_TXSBM_8821C << BIT_SHIFT_TXSBM_8821C)\n#define BIT_CLEAR_TXSBM_8821C(x) ((x) & (~BITS_TXSBM_8821C))\n#define BIT_GET_TXSBM_8821C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TXSBM_8821C) & BIT_MASK_TXSBM_8821C)\n#define BIT_SET_TXSBM_8821C(x, v)                                              \\\n\t(BIT_CLEAR_TXSBM_8821C(x) | BIT_TXSBM_8821C(v))\n\n#define BIT_SHIFT_BACAM_ADDR_8821C 0\n#define BIT_MASK_BACAM_ADDR_8821C 0x3f\n#define BIT_BACAM_ADDR_8821C(x)                                                \\\n\t(((x) & BIT_MASK_BACAM_ADDR_8821C) << BIT_SHIFT_BACAM_ADDR_8821C)\n#define BITS_BACAM_ADDR_8821C                                                  \\\n\t(BIT_MASK_BACAM_ADDR_8821C << BIT_SHIFT_BACAM_ADDR_8821C)\n#define BIT_CLEAR_BACAM_ADDR_8821C(x) ((x) & (~BITS_BACAM_ADDR_8821C))\n#define BIT_GET_BACAM_ADDR_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BACAM_ADDR_8821C) & BIT_MASK_BACAM_ADDR_8821C)\n#define BIT_SET_BACAM_ADDR_8821C(x, v)                                         \\\n\t(BIT_CLEAR_BACAM_ADDR_8821C(x) | BIT_BACAM_ADDR_8821C(v))\n\n/* 2 REG_BACAMCONTENT_8821C (BLOCK ACK CAM CONTENT REGISTER) */\n\n#define BIT_SHIFT_BA_CONTENT_L_8821C 0\n#define BIT_MASK_BA_CONTENT_L_8821C 0xffffffffL\n#define BIT_BA_CONTENT_L_8821C(x)                                              \\\n\t(((x) & BIT_MASK_BA_CONTENT_L_8821C) << BIT_SHIFT_BA_CONTENT_L_8821C)\n#define BITS_BA_CONTENT_L_8821C                                                \\\n\t(BIT_MASK_BA_CONTENT_L_8821C << BIT_SHIFT_BA_CONTENT_L_8821C)\n#define BIT_CLEAR_BA_CONTENT_L_8821C(x) ((x) & (~BITS_BA_CONTENT_L_8821C))\n#define BIT_GET_BA_CONTENT_L_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BA_CONTENT_L_8821C) & BIT_MASK_BA_CONTENT_L_8821C)\n#define BIT_SET_BA_CONTENT_L_8821C(x, v)                                       \\\n\t(BIT_CLEAR_BA_CONTENT_L_8821C(x) | BIT_BA_CONTENT_L_8821C(v))\n\n/* 2 REG_BACAMCONTENT_H_8821C (BLOCK ACK CAM CONTENT REGISTER) */\n\n#define BIT_SHIFT_BA_CONTENT_H_8821C 0\n#define BIT_MASK_BA_CONTENT_H_8821C 0xffffffffL\n#define BIT_BA_CONTENT_H_8821C(x)                                              \\\n\t(((x) & BIT_MASK_BA_CONTENT_H_8821C) << BIT_SHIFT_BA_CONTENT_H_8821C)\n#define BITS_BA_CONTENT_H_8821C                                                \\\n\t(BIT_MASK_BA_CONTENT_H_8821C << BIT_SHIFT_BA_CONTENT_H_8821C)\n#define BIT_CLEAR_BA_CONTENT_H_8821C(x) ((x) & (~BITS_BA_CONTENT_H_8821C))\n#define BIT_GET_BA_CONTENT_H_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BA_CONTENT_H_8821C) & BIT_MASK_BA_CONTENT_H_8821C)\n#define BIT_SET_BA_CONTENT_H_8821C(x, v)                                       \\\n\t(BIT_CLEAR_BA_CONTENT_H_8821C(x) | BIT_BA_CONTENT_H_8821C(v))\n\n/* 2 REG_LBDLY_8821C (LOOPBACK DELAY REGISTER) */\n\n#define BIT_SHIFT_LBDLY_8821C 0\n#define BIT_MASK_LBDLY_8821C 0x1f\n#define BIT_LBDLY_8821C(x)                                                     \\\n\t(((x) & BIT_MASK_LBDLY_8821C) << BIT_SHIFT_LBDLY_8821C)\n#define BITS_LBDLY_8821C (BIT_MASK_LBDLY_8821C << BIT_SHIFT_LBDLY_8821C)\n#define BIT_CLEAR_LBDLY_8821C(x) ((x) & (~BITS_LBDLY_8821C))\n#define BIT_GET_LBDLY_8821C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_LBDLY_8821C) & BIT_MASK_LBDLY_8821C)\n#define BIT_SET_LBDLY_8821C(x, v)                                              \\\n\t(BIT_CLEAR_LBDLY_8821C(x) | BIT_LBDLY_8821C(v))\n\n/* 2 REG_WMAC_BACAM_RPMEN_8821C */\n\n#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C 2\n#define BIT_MASK_BITMAP_SSNBK_COUNTER_8821C 0x3f\n#define BIT_BITMAP_SSNBK_COUNTER_8821C(x)                                      \\\n\t(((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8821C)                           \\\n\t << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C)\n#define BITS_BITMAP_SSNBK_COUNTER_8821C                                        \\\n\t(BIT_MASK_BITMAP_SSNBK_COUNTER_8821C                                   \\\n\t << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C)\n#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8821C(x)                                \\\n\t((x) & (~BITS_BITMAP_SSNBK_COUNTER_8821C))\n#define BIT_GET_BITMAP_SSNBK_COUNTER_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) &                       \\\n\t BIT_MASK_BITMAP_SSNBK_COUNTER_8821C)\n#define BIT_SET_BITMAP_SSNBK_COUNTER_8821C(x, v)                               \\\n\t(BIT_CLEAR_BITMAP_SSNBK_COUNTER_8821C(x) |                             \\\n\t BIT_BITMAP_SSNBK_COUNTER_8821C(v))\n\n#define BIT_BITMAP_EN_8821C BIT(1)\n#define BIT_WMAC_BACAM_RPMEN_8821C BIT(0)\n\n/* 2 REG_TX_RX_8821C STATUS */\n\n#define BIT_SHIFT_RXPKT_TYPE_8821C 2\n#define BIT_MASK_RXPKT_TYPE_8821C 0x3f\n#define BIT_RXPKT_TYPE_8821C(x)                                                \\\n\t(((x) & BIT_MASK_RXPKT_TYPE_8821C) << BIT_SHIFT_RXPKT_TYPE_8821C)\n#define BITS_RXPKT_TYPE_8821C                                                  \\\n\t(BIT_MASK_RXPKT_TYPE_8821C << BIT_SHIFT_RXPKT_TYPE_8821C)\n#define BIT_CLEAR_RXPKT_TYPE_8821C(x) ((x) & (~BITS_RXPKT_TYPE_8821C))\n#define BIT_GET_RXPKT_TYPE_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXPKT_TYPE_8821C) & BIT_MASK_RXPKT_TYPE_8821C)\n#define BIT_SET_RXPKT_TYPE_8821C(x, v)                                         \\\n\t(BIT_CLEAR_RXPKT_TYPE_8821C(x) | BIT_RXPKT_TYPE_8821C(v))\n\n#define BIT_TXACT_IND_8821C BIT(1)\n#define BIT_RXACT_IND_8821C BIT(0)\n\n/* 2 REG_WMAC_BITMAP_CTL_8821C */\n#define BIT_BITMAP_VO_8821C BIT(7)\n#define BIT_BITMAP_VI_8821C BIT(6)\n#define BIT_BITMAP_BE_8821C BIT(5)\n#define BIT_BITMAP_BK_8821C BIT(4)\n\n#define BIT_SHIFT_BITMAP_CONDITION_8821C 2\n#define BIT_MASK_BITMAP_CONDITION_8821C 0x3\n#define BIT_BITMAP_CONDITION_8821C(x)                                          \\\n\t(((x) & BIT_MASK_BITMAP_CONDITION_8821C)                               \\\n\t << BIT_SHIFT_BITMAP_CONDITION_8821C)\n#define BITS_BITMAP_CONDITION_8821C                                            \\\n\t(BIT_MASK_BITMAP_CONDITION_8821C << BIT_SHIFT_BITMAP_CONDITION_8821C)\n#define BIT_CLEAR_BITMAP_CONDITION_8821C(x)                                    \\\n\t((x) & (~BITS_BITMAP_CONDITION_8821C))\n#define BIT_GET_BITMAP_CONDITION_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BITMAP_CONDITION_8821C) &                           \\\n\t BIT_MASK_BITMAP_CONDITION_8821C)\n#define BIT_SET_BITMAP_CONDITION_8821C(x, v)                                   \\\n\t(BIT_CLEAR_BITMAP_CONDITION_8821C(x) | BIT_BITMAP_CONDITION_8821C(v))\n\n#define BIT_BITMAP_SSNBK_COUNTER_CLR_8821C BIT(1)\n#define BIT_BITMAP_FORCE_8821C BIT(0)\n\n/* 2 REG_RXERR_RPT_8821C (RX ERROR REPORT REGISTER) */\n\n#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C 28\n#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C 0xf\n#define BIT_RXERR_RPT_SEL_V1_3_0_8821C(x)                                      \\\n\t(((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C)                           \\\n\t << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C)\n#define BITS_RXERR_RPT_SEL_V1_3_0_8821C                                        \\\n\t(BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C                                   \\\n\t << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C)\n#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8821C(x)                                \\\n\t((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8821C))\n#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) &                       \\\n\t BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C)\n#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8821C(x, v)                               \\\n\t(BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8821C(x) |                             \\\n\t BIT_RXERR_RPT_SEL_V1_3_0_8821C(v))\n\n#define BIT_RXERR_RPT_RST_8821C BIT(27)\n#define BIT_RXERR_RPT_SEL_V1_4_8821C BIT(26)\n#define BIT_W1S_8821C BIT(23)\n#define BIT_UD_SELECT_BSSID_8821C BIT(22)\n\n#define BIT_SHIFT_UD_SUB_TYPE_8821C 18\n#define BIT_MASK_UD_SUB_TYPE_8821C 0xf\n#define BIT_UD_SUB_TYPE_8821C(x)                                               \\\n\t(((x) & BIT_MASK_UD_SUB_TYPE_8821C) << BIT_SHIFT_UD_SUB_TYPE_8821C)\n#define BITS_UD_SUB_TYPE_8821C                                                 \\\n\t(BIT_MASK_UD_SUB_TYPE_8821C << BIT_SHIFT_UD_SUB_TYPE_8821C)\n#define BIT_CLEAR_UD_SUB_TYPE_8821C(x) ((x) & (~BITS_UD_SUB_TYPE_8821C))\n#define BIT_GET_UD_SUB_TYPE_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_UD_SUB_TYPE_8821C) & BIT_MASK_UD_SUB_TYPE_8821C)\n#define BIT_SET_UD_SUB_TYPE_8821C(x, v)                                        \\\n\t(BIT_CLEAR_UD_SUB_TYPE_8821C(x) | BIT_UD_SUB_TYPE_8821C(v))\n\n#define BIT_SHIFT_UD_TYPE_8821C 16\n#define BIT_MASK_UD_TYPE_8821C 0x3\n#define BIT_UD_TYPE_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_UD_TYPE_8821C) << BIT_SHIFT_UD_TYPE_8821C)\n#define BITS_UD_TYPE_8821C (BIT_MASK_UD_TYPE_8821C << BIT_SHIFT_UD_TYPE_8821C)\n#define BIT_CLEAR_UD_TYPE_8821C(x) ((x) & (~BITS_UD_TYPE_8821C))\n#define BIT_GET_UD_TYPE_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_UD_TYPE_8821C) & BIT_MASK_UD_TYPE_8821C)\n#define BIT_SET_UD_TYPE_8821C(x, v)                                            \\\n\t(BIT_CLEAR_UD_TYPE_8821C(x) | BIT_UD_TYPE_8821C(v))\n\n#define BIT_SHIFT_RPT_COUNTER_8821C 0\n#define BIT_MASK_RPT_COUNTER_8821C 0xffff\n#define BIT_RPT_COUNTER_8821C(x)                                               \\\n\t(((x) & BIT_MASK_RPT_COUNTER_8821C) << BIT_SHIFT_RPT_COUNTER_8821C)\n#define BITS_RPT_COUNTER_8821C                                                 \\\n\t(BIT_MASK_RPT_COUNTER_8821C << BIT_SHIFT_RPT_COUNTER_8821C)\n#define BIT_CLEAR_RPT_COUNTER_8821C(x) ((x) & (~BITS_RPT_COUNTER_8821C))\n#define BIT_GET_RPT_COUNTER_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RPT_COUNTER_8821C) & BIT_MASK_RPT_COUNTER_8821C)\n#define BIT_SET_RPT_COUNTER_8821C(x, v)                                        \\\n\t(BIT_CLEAR_RPT_COUNTER_8821C(x) | BIT_RPT_COUNTER_8821C(v))\n\n/* 2 REG_WMAC_TRXPTCL_CTL_8821C\t(WMAC TX/RX PROTOCOL CONTROL REGISTER) */\n#define BIT_EN_TXCTS_INTXOP_8821C BIT(32)\n#define BIT_BLK_EDCA_BBSLP_8821C BIT(31)\n#define BIT_BLK_EDCA_BBSBY_8821C BIT(30)\n#define BIT_ACKTO_BLOCK_SCH_EN_8821C BIT(27)\n#define BIT_EIFS_BLOCK_SCH_EN_8821C BIT(26)\n#define BIT_PLCPCHK_RST_EIFS_8821C BIT(25)\n#define BIT_CCA_RST_EIFS_8821C BIT(24)\n#define BIT_DIS_UPD_MYRXPKTNAV_8821C BIT(23)\n#define BIT_EARLY_TXBA_8821C BIT(22)\n\n#define BIT_SHIFT_RESP_CHNBUSY_8821C 20\n#define BIT_MASK_RESP_CHNBUSY_8821C 0x3\n#define BIT_RESP_CHNBUSY_8821C(x)                                              \\\n\t(((x) & BIT_MASK_RESP_CHNBUSY_8821C) << BIT_SHIFT_RESP_CHNBUSY_8821C)\n#define BITS_RESP_CHNBUSY_8821C                                                \\\n\t(BIT_MASK_RESP_CHNBUSY_8821C << BIT_SHIFT_RESP_CHNBUSY_8821C)\n#define BIT_CLEAR_RESP_CHNBUSY_8821C(x) ((x) & (~BITS_RESP_CHNBUSY_8821C))\n#define BIT_GET_RESP_CHNBUSY_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RESP_CHNBUSY_8821C) & BIT_MASK_RESP_CHNBUSY_8821C)\n#define BIT_SET_RESP_CHNBUSY_8821C(x, v)                                       \\\n\t(BIT_CLEAR_RESP_CHNBUSY_8821C(x) | BIT_RESP_CHNBUSY_8821C(v))\n\n#define BIT_RESP_DCTS_EN_8821C BIT(19)\n#define BIT_RESP_DCFE_EN_8821C BIT(18)\n#define BIT_RESP_SPLCPEN_8821C BIT(17)\n#define BIT_RESP_SGIEN_8821C BIT(16)\n#define BIT_RESP_LDPC_EN_8821C BIT(15)\n#define BIT_DIS_RESP_ACKINCCA_8821C BIT(14)\n#define BIT_DIS_RESP_CTSINCCA_8821C BIT(13)\n\n#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C 10\n#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C 0x7\n#define BIT_R_WMAC_SECOND_CCA_TIMER_8821C(x)                                   \\\n\t(((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C)                        \\\n\t << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C)\n#define BITS_R_WMAC_SECOND_CCA_TIMER_8821C                                     \\\n\t(BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C                                \\\n\t << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C)\n#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8821C(x)                             \\\n\t((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8821C))\n#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8821C(x)                               \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C) &                    \\\n\t BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C)\n#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8821C(x, v)                            \\\n\t(BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8821C(x) |                          \\\n\t BIT_R_WMAC_SECOND_CCA_TIMER_8821C(v))\n\n#define BIT_SHIFT_RFMOD_8821C 7\n#define BIT_MASK_RFMOD_8821C 0x3\n#define BIT_RFMOD_8821C(x)                                                     \\\n\t(((x) & BIT_MASK_RFMOD_8821C) << BIT_SHIFT_RFMOD_8821C)\n#define BITS_RFMOD_8821C (BIT_MASK_RFMOD_8821C << BIT_SHIFT_RFMOD_8821C)\n#define BIT_CLEAR_RFMOD_8821C(x) ((x) & (~BITS_RFMOD_8821C))\n#define BIT_GET_RFMOD_8821C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RFMOD_8821C) & BIT_MASK_RFMOD_8821C)\n#define BIT_SET_RFMOD_8821C(x, v)                                              \\\n\t(BIT_CLEAR_RFMOD_8821C(x) | BIT_RFMOD_8821C(v))\n\n#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C 5\n#define BIT_MASK_RESP_CTS_DYNBW_SEL_8821C 0x3\n#define BIT_RESP_CTS_DYNBW_SEL_8821C(x)                                        \\\n\t(((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8821C)                             \\\n\t << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C)\n#define BITS_RESP_CTS_DYNBW_SEL_8821C                                          \\\n\t(BIT_MASK_RESP_CTS_DYNBW_SEL_8821C                                     \\\n\t << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C)\n#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8821C(x)                                  \\\n\t((x) & (~BITS_RESP_CTS_DYNBW_SEL_8821C))\n#define BIT_GET_RESP_CTS_DYNBW_SEL_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) &                         \\\n\t BIT_MASK_RESP_CTS_DYNBW_SEL_8821C)\n#define BIT_SET_RESP_CTS_DYNBW_SEL_8821C(x, v)                                 \\\n\t(BIT_CLEAR_RESP_CTS_DYNBW_SEL_8821C(x) |                               \\\n\t BIT_RESP_CTS_DYNBW_SEL_8821C(v))\n\n#define BIT_DLY_TX_WAIT_RXANTSEL_8821C BIT(4)\n#define BIT_TXRESP_BY_RXANTSEL_8821C BIT(3)\n\n#define BIT_SHIFT_ORIG_DCTS_CHK_8821C 0\n#define BIT_MASK_ORIG_DCTS_CHK_8821C 0x3\n#define BIT_ORIG_DCTS_CHK_8821C(x)                                             \\\n\t(((x) & BIT_MASK_ORIG_DCTS_CHK_8821C) << BIT_SHIFT_ORIG_DCTS_CHK_8821C)\n#define BITS_ORIG_DCTS_CHK_8821C                                               \\\n\t(BIT_MASK_ORIG_DCTS_CHK_8821C << BIT_SHIFT_ORIG_DCTS_CHK_8821C)\n#define BIT_CLEAR_ORIG_DCTS_CHK_8821C(x) ((x) & (~BITS_ORIG_DCTS_CHK_8821C))\n#define BIT_GET_ORIG_DCTS_CHK_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8821C) & BIT_MASK_ORIG_DCTS_CHK_8821C)\n#define BIT_SET_ORIG_DCTS_CHK_8821C(x, v)                                      \\\n\t(BIT_CLEAR_ORIG_DCTS_CHK_8821C(x) | BIT_ORIG_DCTS_CHK_8821C(v))\n\n/* 2 REG_WMAC_TRXPTCL_CTL_H_8821C */\n\n#define BIT_SHIFT_ACKBA_TYPSEL_8821C 28\n#define BIT_MASK_ACKBA_TYPSEL_8821C 0xf\n#define BIT_ACKBA_TYPSEL_8821C(x)                                              \\\n\t(((x) & BIT_MASK_ACKBA_TYPSEL_8821C) << BIT_SHIFT_ACKBA_TYPSEL_8821C)\n#define BITS_ACKBA_TYPSEL_8821C                                                \\\n\t(BIT_MASK_ACKBA_TYPSEL_8821C << BIT_SHIFT_ACKBA_TYPSEL_8821C)\n#define BIT_CLEAR_ACKBA_TYPSEL_8821C(x) ((x) & (~BITS_ACKBA_TYPSEL_8821C))\n#define BIT_GET_ACKBA_TYPSEL_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_ACKBA_TYPSEL_8821C) & BIT_MASK_ACKBA_TYPSEL_8821C)\n#define BIT_SET_ACKBA_TYPSEL_8821C(x, v)                                       \\\n\t(BIT_CLEAR_ACKBA_TYPSEL_8821C(x) | BIT_ACKBA_TYPSEL_8821C(v))\n\n#define BIT_SHIFT_ACKBA_ACKPCHK_8821C 24\n#define BIT_MASK_ACKBA_ACKPCHK_8821C 0xf\n#define BIT_ACKBA_ACKPCHK_8821C(x)                                             \\\n\t(((x) & BIT_MASK_ACKBA_ACKPCHK_8821C) << BIT_SHIFT_ACKBA_ACKPCHK_8821C)\n#define BITS_ACKBA_ACKPCHK_8821C                                               \\\n\t(BIT_MASK_ACKBA_ACKPCHK_8821C << BIT_SHIFT_ACKBA_ACKPCHK_8821C)\n#define BIT_CLEAR_ACKBA_ACKPCHK_8821C(x) ((x) & (~BITS_ACKBA_ACKPCHK_8821C))\n#define BIT_GET_ACKBA_ACKPCHK_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8821C) & BIT_MASK_ACKBA_ACKPCHK_8821C)\n#define BIT_SET_ACKBA_ACKPCHK_8821C(x, v)                                      \\\n\t(BIT_CLEAR_ACKBA_ACKPCHK_8821C(x) | BIT_ACKBA_ACKPCHK_8821C(v))\n\n#define BIT_SHIFT_ACKBAR_TYPESEL_8821C 16\n#define BIT_MASK_ACKBAR_TYPESEL_8821C 0xff\n#define BIT_ACKBAR_TYPESEL_8821C(x)                                            \\\n\t(((x) & BIT_MASK_ACKBAR_TYPESEL_8821C)                                 \\\n\t << BIT_SHIFT_ACKBAR_TYPESEL_8821C)\n#define BITS_ACKBAR_TYPESEL_8821C                                              \\\n\t(BIT_MASK_ACKBAR_TYPESEL_8821C << BIT_SHIFT_ACKBAR_TYPESEL_8821C)\n#define BIT_CLEAR_ACKBAR_TYPESEL_8821C(x) ((x) & (~BITS_ACKBAR_TYPESEL_8821C))\n#define BIT_GET_ACKBAR_TYPESEL_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8821C) &                             \\\n\t BIT_MASK_ACKBAR_TYPESEL_8821C)\n#define BIT_SET_ACKBAR_TYPESEL_8821C(x, v)                                     \\\n\t(BIT_CLEAR_ACKBAR_TYPESEL_8821C(x) | BIT_ACKBAR_TYPESEL_8821C(v))\n\n#define BIT_SHIFT_ACKBAR_ACKPCHK_8821C 12\n#define BIT_MASK_ACKBAR_ACKPCHK_8821C 0xf\n#define BIT_ACKBAR_ACKPCHK_8821C(x)                                            \\\n\t(((x) & BIT_MASK_ACKBAR_ACKPCHK_8821C)                                 \\\n\t << BIT_SHIFT_ACKBAR_ACKPCHK_8821C)\n#define BITS_ACKBAR_ACKPCHK_8821C                                              \\\n\t(BIT_MASK_ACKBAR_ACKPCHK_8821C << BIT_SHIFT_ACKBAR_ACKPCHK_8821C)\n#define BIT_CLEAR_ACKBAR_ACKPCHK_8821C(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8821C))\n#define BIT_GET_ACKBAR_ACKPCHK_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8821C) &                             \\\n\t BIT_MASK_ACKBAR_ACKPCHK_8821C)\n#define BIT_SET_ACKBAR_ACKPCHK_8821C(x, v)                                     \\\n\t(BIT_CLEAR_ACKBAR_ACKPCHK_8821C(x) | BIT_ACKBAR_ACKPCHK_8821C(v))\n\n#define BIT_RXBA_IGNOREA2_V1_8821C BIT(10)\n#define BIT_EN_SAVE_ALL_TXOPADDR_V1_8821C BIT(9)\n#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1_8821C BIT(8)\n#define BIT_DIS_TXBA_AMPDUFCSERR_V1_8821C BIT(7)\n#define BIT_DIS_TXBA_RXBARINFULL_V1_8821C BIT(6)\n#define BIT_DIS_TXCFE_INFULL_V1_8821C BIT(5)\n#define BIT_DIS_TXCTS_INFULL_V1_8821C BIT(4)\n#define BIT_EN_TXACKBA_IN_TX_RDG_V1_8821C BIT(3)\n#define BIT_EN_TXACKBA_IN_TXOP_V1_8821C BIT(2)\n#define BIT_EN_TXCTS_IN_RXNAV_V1_8821C BIT(1)\n#define BIT_EN_TXCTS_INTXOP_V1_8821C BIT(0)\n\n/* 2 REG_CAMCMD_8821C (CAM COMMAND REGISTER) */\n#define BIT_SECCAM_POLLING_8821C BIT(31)\n#define BIT_SECCAM_CLR_8821C BIT(30)\n#define BIT_MFBCAM_CLR_8821C BIT(29)\n#define BIT_SECCAM_WE_8821C BIT(16)\n\n#define BIT_SHIFT_SECCAM_ADDR_V2_8821C 0\n#define BIT_MASK_SECCAM_ADDR_V2_8821C 0x3ff\n#define BIT_SECCAM_ADDR_V2_8821C(x)                                            \\\n\t(((x) & BIT_MASK_SECCAM_ADDR_V2_8821C)                                 \\\n\t << BIT_SHIFT_SECCAM_ADDR_V2_8821C)\n#define BITS_SECCAM_ADDR_V2_8821C                                              \\\n\t(BIT_MASK_SECCAM_ADDR_V2_8821C << BIT_SHIFT_SECCAM_ADDR_V2_8821C)\n#define BIT_CLEAR_SECCAM_ADDR_V2_8821C(x) ((x) & (~BITS_SECCAM_ADDR_V2_8821C))\n#define BIT_GET_SECCAM_ADDR_V2_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8821C) &                             \\\n\t BIT_MASK_SECCAM_ADDR_V2_8821C)\n#define BIT_SET_SECCAM_ADDR_V2_8821C(x, v)                                     \\\n\t(BIT_CLEAR_SECCAM_ADDR_V2_8821C(x) | BIT_SECCAM_ADDR_V2_8821C(v))\n\n/* 2 REG_CAMWRITE_8821C (CAM WRITE REGISTER) */\n\n#define BIT_SHIFT_CAMW_DATA_8821C 0\n#define BIT_MASK_CAMW_DATA_8821C 0xffffffffL\n#define BIT_CAMW_DATA_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_CAMW_DATA_8821C) << BIT_SHIFT_CAMW_DATA_8821C)\n#define BITS_CAMW_DATA_8821C                                                   \\\n\t(BIT_MASK_CAMW_DATA_8821C << BIT_SHIFT_CAMW_DATA_8821C)\n#define BIT_CLEAR_CAMW_DATA_8821C(x) ((x) & (~BITS_CAMW_DATA_8821C))\n#define BIT_GET_CAMW_DATA_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_CAMW_DATA_8821C) & BIT_MASK_CAMW_DATA_8821C)\n#define BIT_SET_CAMW_DATA_8821C(x, v)                                          \\\n\t(BIT_CLEAR_CAMW_DATA_8821C(x) | BIT_CAMW_DATA_8821C(v))\n\n/* 2 REG_CAMREAD_8821C (CAM READ REGISTER) */\n\n#define BIT_SHIFT_CAMR_DATA_8821C 0\n#define BIT_MASK_CAMR_DATA_8821C 0xffffffffL\n#define BIT_CAMR_DATA_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_CAMR_DATA_8821C) << BIT_SHIFT_CAMR_DATA_8821C)\n#define BITS_CAMR_DATA_8821C                                                   \\\n\t(BIT_MASK_CAMR_DATA_8821C << BIT_SHIFT_CAMR_DATA_8821C)\n#define BIT_CLEAR_CAMR_DATA_8821C(x) ((x) & (~BITS_CAMR_DATA_8821C))\n#define BIT_GET_CAMR_DATA_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_CAMR_DATA_8821C) & BIT_MASK_CAMR_DATA_8821C)\n#define BIT_SET_CAMR_DATA_8821C(x, v)                                          \\\n\t(BIT_CLEAR_CAMR_DATA_8821C(x) | BIT_CAMR_DATA_8821C(v))\n\n/* 2 REG_CAMDBG_8821C (CAM DEBUG REGISTER) */\n#define BIT_SECCAM_INFO_8821C BIT(31)\n#define BIT_SEC_KEYFOUND_8821C BIT(15)\n\n#define BIT_SHIFT_CAMDBG_SEC_TYPE_8821C 12\n#define BIT_MASK_CAMDBG_SEC_TYPE_8821C 0x7\n#define BIT_CAMDBG_SEC_TYPE_8821C(x)                                           \\\n\t(((x) & BIT_MASK_CAMDBG_SEC_TYPE_8821C)                                \\\n\t << BIT_SHIFT_CAMDBG_SEC_TYPE_8821C)\n#define BITS_CAMDBG_SEC_TYPE_8821C                                             \\\n\t(BIT_MASK_CAMDBG_SEC_TYPE_8821C << BIT_SHIFT_CAMDBG_SEC_TYPE_8821C)\n#define BIT_CLEAR_CAMDBG_SEC_TYPE_8821C(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8821C))\n#define BIT_GET_CAMDBG_SEC_TYPE_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) &                            \\\n\t BIT_MASK_CAMDBG_SEC_TYPE_8821C)\n#define BIT_SET_CAMDBG_SEC_TYPE_8821C(x, v)                                    \\\n\t(BIT_CLEAR_CAMDBG_SEC_TYPE_8821C(x) | BIT_CAMDBG_SEC_TYPE_8821C(v))\n\n#define BIT_CAMDBG_EXT_SECTYPE_8821C BIT(11)\n\n#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C 5\n#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C 0x1f\n#define BIT_CAMDBG_MIC_KEY_IDX_8821C(x)                                        \\\n\t(((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C)                             \\\n\t << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C)\n#define BITS_CAMDBG_MIC_KEY_IDX_8821C                                          \\\n\t(BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C                                     \\\n\t << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C)\n#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8821C(x)                                  \\\n\t((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8821C))\n#define BIT_GET_CAMDBG_MIC_KEY_IDX_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C) &                         \\\n\t BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C)\n#define BIT_SET_CAMDBG_MIC_KEY_IDX_8821C(x, v)                                 \\\n\t(BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8821C(x) |                               \\\n\t BIT_CAMDBG_MIC_KEY_IDX_8821C(v))\n\n#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C 0\n#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C 0x1f\n#define BIT_CAMDBG_SEC_KEY_IDX_8821C(x)                                        \\\n\t(((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C)                             \\\n\t << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C)\n#define BITS_CAMDBG_SEC_KEY_IDX_8821C                                          \\\n\t(BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C                                     \\\n\t << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C)\n#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8821C(x)                                  \\\n\t((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8821C))\n#define BIT_GET_CAMDBG_SEC_KEY_IDX_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) &                         \\\n\t BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C)\n#define BIT_SET_CAMDBG_SEC_KEY_IDX_8821C(x, v)                                 \\\n\t(BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8821C(x) |                               \\\n\t BIT_CAMDBG_SEC_KEY_IDX_8821C(v))\n\n/* 2 REG_SECCFG_8821C (SECURITY CONFIGURATION REGISTER) */\n#define BIT_DIS_GCLK_WAPI_8821C BIT(15)\n#define BIT_DIS_GCLK_AES_8821C BIT(14)\n#define BIT_DIS_GCLK_TKIP_8821C BIT(13)\n#define BIT_AES_SEL_QC_1_8821C BIT(12)\n#define BIT_AES_SEL_QC_0_8821C BIT(11)\n#define BIT_CHK_BMC_8821C BIT(9)\n#define BIT_CHK_KEYID_8821C BIT(8)\n#define BIT_RXBCUSEDK_8821C BIT(7)\n#define BIT_TXBCUSEDK_8821C BIT(6)\n#define BIT_NOSKMC_8821C BIT(5)\n#define BIT_SKBYA2_8821C BIT(4)\n#define BIT_RXDEC_8821C BIT(3)\n#define BIT_TXENC_8821C BIT(2)\n#define BIT_RXUHUSEDK_8821C BIT(1)\n#define BIT_TXUHUSEDK_8821C BIT(0)\n\n/* 2 REG_RXFILTER_CATEGORY_1_8821C */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_1_8821C 0\n#define BIT_MASK_RXFILTER_CATEGORY_1_8821C 0xff\n#define BIT_RXFILTER_CATEGORY_1_8821C(x)                                       \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_1_8821C)                            \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_1_8821C)\n#define BITS_RXFILTER_CATEGORY_1_8821C                                         \\\n\t(BIT_MASK_RXFILTER_CATEGORY_1_8821C                                    \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_1_8821C)\n#define BIT_CLEAR_RXFILTER_CATEGORY_1_8821C(x)                                 \\\n\t((x) & (~BITS_RXFILTER_CATEGORY_1_8821C))\n#define BIT_GET_RXFILTER_CATEGORY_1_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8821C) &                        \\\n\t BIT_MASK_RXFILTER_CATEGORY_1_8821C)\n#define BIT_SET_RXFILTER_CATEGORY_1_8821C(x, v)                                \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_1_8821C(x) |                              \\\n\t BIT_RXFILTER_CATEGORY_1_8821C(v))\n\n/* 2 REG_RXFILTER_ACTION_1_8821C */\n\n#define BIT_SHIFT_RXFILTER_ACTION_1_8821C 0\n#define BIT_MASK_RXFILTER_ACTION_1_8821C 0xff\n#define BIT_RXFILTER_ACTION_1_8821C(x)                                         \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_1_8821C)                              \\\n\t << BIT_SHIFT_RXFILTER_ACTION_1_8821C)\n#define BITS_RXFILTER_ACTION_1_8821C                                           \\\n\t(BIT_MASK_RXFILTER_ACTION_1_8821C << BIT_SHIFT_RXFILTER_ACTION_1_8821C)\n#define BIT_CLEAR_RXFILTER_ACTION_1_8821C(x)                                   \\\n\t((x) & (~BITS_RXFILTER_ACTION_1_8821C))\n#define BIT_GET_RXFILTER_ACTION_1_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8821C) &                          \\\n\t BIT_MASK_RXFILTER_ACTION_1_8821C)\n#define BIT_SET_RXFILTER_ACTION_1_8821C(x, v)                                  \\\n\t(BIT_CLEAR_RXFILTER_ACTION_1_8821C(x) | BIT_RXFILTER_ACTION_1_8821C(v))\n\n/* 2 REG_RXFILTER_CATEGORY_2_8821C */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_2_8821C 0\n#define BIT_MASK_RXFILTER_CATEGORY_2_8821C 0xff\n#define BIT_RXFILTER_CATEGORY_2_8821C(x)                                       \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_2_8821C)                            \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_2_8821C)\n#define BITS_RXFILTER_CATEGORY_2_8821C                                         \\\n\t(BIT_MASK_RXFILTER_CATEGORY_2_8821C                                    \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_2_8821C)\n#define BIT_CLEAR_RXFILTER_CATEGORY_2_8821C(x)                                 \\\n\t((x) & (~BITS_RXFILTER_CATEGORY_2_8821C))\n#define BIT_GET_RXFILTER_CATEGORY_2_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8821C) &                        \\\n\t BIT_MASK_RXFILTER_CATEGORY_2_8821C)\n#define BIT_SET_RXFILTER_CATEGORY_2_8821C(x, v)                                \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_2_8821C(x) |                              \\\n\t BIT_RXFILTER_CATEGORY_2_8821C(v))\n\n/* 2 REG_RXFILTER_ACTION_2_8821C */\n\n#define BIT_SHIFT_RXFILTER_ACTION_2_8821C 0\n#define BIT_MASK_RXFILTER_ACTION_2_8821C 0xff\n#define BIT_RXFILTER_ACTION_2_8821C(x)                                         \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_2_8821C)                              \\\n\t << BIT_SHIFT_RXFILTER_ACTION_2_8821C)\n#define BITS_RXFILTER_ACTION_2_8821C                                           \\\n\t(BIT_MASK_RXFILTER_ACTION_2_8821C << BIT_SHIFT_RXFILTER_ACTION_2_8821C)\n#define BIT_CLEAR_RXFILTER_ACTION_2_8821C(x)                                   \\\n\t((x) & (~BITS_RXFILTER_ACTION_2_8821C))\n#define BIT_GET_RXFILTER_ACTION_2_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8821C) &                          \\\n\t BIT_MASK_RXFILTER_ACTION_2_8821C)\n#define BIT_SET_RXFILTER_ACTION_2_8821C(x, v)                                  \\\n\t(BIT_CLEAR_RXFILTER_ACTION_2_8821C(x) | BIT_RXFILTER_ACTION_2_8821C(v))\n\n/* 2 REG_RXFILTER_CATEGORY_3_8821C */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_3_8821C 0\n#define BIT_MASK_RXFILTER_CATEGORY_3_8821C 0xff\n#define BIT_RXFILTER_CATEGORY_3_8821C(x)                                       \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_3_8821C)                            \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_3_8821C)\n#define BITS_RXFILTER_CATEGORY_3_8821C                                         \\\n\t(BIT_MASK_RXFILTER_CATEGORY_3_8821C                                    \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_3_8821C)\n#define BIT_CLEAR_RXFILTER_CATEGORY_3_8821C(x)                                 \\\n\t((x) & (~BITS_RXFILTER_CATEGORY_3_8821C))\n#define BIT_GET_RXFILTER_CATEGORY_3_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8821C) &                        \\\n\t BIT_MASK_RXFILTER_CATEGORY_3_8821C)\n#define BIT_SET_RXFILTER_CATEGORY_3_8821C(x, v)                                \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_3_8821C(x) |                              \\\n\t BIT_RXFILTER_CATEGORY_3_8821C(v))\n\n/* 2 REG_RXFILTER_ACTION_3_8821C */\n\n#define BIT_SHIFT_RXFILTER_ACTION_3_8821C 0\n#define BIT_MASK_RXFILTER_ACTION_3_8821C 0xff\n#define BIT_RXFILTER_ACTION_3_8821C(x)                                         \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_3_8821C)                              \\\n\t << BIT_SHIFT_RXFILTER_ACTION_3_8821C)\n#define BITS_RXFILTER_ACTION_3_8821C                                           \\\n\t(BIT_MASK_RXFILTER_ACTION_3_8821C << BIT_SHIFT_RXFILTER_ACTION_3_8821C)\n#define BIT_CLEAR_RXFILTER_ACTION_3_8821C(x)                                   \\\n\t((x) & (~BITS_RXFILTER_ACTION_3_8821C))\n#define BIT_GET_RXFILTER_ACTION_3_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8821C) &                          \\\n\t BIT_MASK_RXFILTER_ACTION_3_8821C)\n#define BIT_SET_RXFILTER_ACTION_3_8821C(x, v)                                  \\\n\t(BIT_CLEAR_RXFILTER_ACTION_3_8821C(x) | BIT_RXFILTER_ACTION_3_8821C(v))\n\n/* 2 REG_RXFLTMAP3_8821C (RX FILTER MAP GROUP 3) */\n#define BIT_MGTFLT15EN_FW_8821C BIT(15)\n#define BIT_MGTFLT14EN_FW_8821C BIT(14)\n#define BIT_MGTFLT13EN_FW_8821C BIT(13)\n#define BIT_MGTFLT12EN_FW_8821C BIT(12)\n#define BIT_MGTFLT11EN_FW_8821C BIT(11)\n#define BIT_MGTFLT10EN_FW_8821C BIT(10)\n#define BIT_MGTFLT9EN_FW_8821C BIT(9)\n#define BIT_MGTFLT8EN_FW_8821C BIT(8)\n#define BIT_MGTFLT7EN_FW_8821C BIT(7)\n#define BIT_MGTFLT6EN_FW_8821C BIT(6)\n#define BIT_MGTFLT5EN_FW_8821C BIT(5)\n#define BIT_MGTFLT4EN_FW_8821C BIT(4)\n#define BIT_MGTFLT3EN_FW_8821C BIT(3)\n#define BIT_MGTFLT2EN_FW_8821C BIT(2)\n#define BIT_MGTFLT1EN_FW_8821C BIT(1)\n#define BIT_MGTFLT0EN_FW_8821C BIT(0)\n\n/* 2 REG_RXFLTMAP4_8821C (RX FILTER MAP GROUP 4) */\n#define BIT_CTRLFLT15EN_FW_8821C BIT(15)\n#define BIT_CTRLFLT14EN_FW_8821C BIT(14)\n#define BIT_CTRLFLT13EN_FW_8821C BIT(13)\n#define BIT_CTRLFLT12EN_FW_8821C BIT(12)\n#define BIT_CTRLFLT11EN_FW_8821C BIT(11)\n#define BIT_CTRLFLT10EN_FW_8821C BIT(10)\n#define BIT_CTRLFLT9EN_FW_8821C BIT(9)\n#define BIT_CTRLFLT8EN_FW_8821C BIT(8)\n#define BIT_CTRLFLT7EN_FW_8821C BIT(7)\n#define BIT_CTRLFLT6EN_FW_8821C BIT(6)\n#define BIT_CTRLFLT5EN_FW_8821C BIT(5)\n#define BIT_CTRLFLT4EN_FW_8821C BIT(4)\n#define BIT_CTRLFLT3EN_FW_8821C BIT(3)\n#define BIT_CTRLFLT2EN_FW_8821C BIT(2)\n#define BIT_CTRLFLT1EN_FW_8821C BIT(1)\n#define BIT_CTRLFLT0EN_FW_8821C BIT(0)\n\n/* 2 REG_RXFLTMAP5_8821C (RX FILTER MAP GROUP 5) */\n#define BIT_DATAFLT15EN_FW_8821C BIT(15)\n#define BIT_DATAFLT14EN_FW_8821C BIT(14)\n#define BIT_DATAFLT13EN_FW_8821C BIT(13)\n#define BIT_DATAFLT12EN_FW_8821C BIT(12)\n#define BIT_DATAFLT11EN_FW_8821C BIT(11)\n#define BIT_DATAFLT10EN_FW_8821C BIT(10)\n#define BIT_DATAFLT9EN_FW_8821C BIT(9)\n#define BIT_DATAFLT8EN_FW_8821C BIT(8)\n#define BIT_DATAFLT7EN_FW_8821C BIT(7)\n#define BIT_DATAFLT6EN_FW_8821C BIT(6)\n#define BIT_DATAFLT5EN_FW_8821C BIT(5)\n#define BIT_DATAFLT4EN_FW_8821C BIT(4)\n#define BIT_DATAFLT3EN_FW_8821C BIT(3)\n#define BIT_DATAFLT2EN_FW_8821C BIT(2)\n#define BIT_DATAFLT1EN_FW_8821C BIT(1)\n#define BIT_DATAFLT0EN_FW_8821C BIT(0)\n\n/* 2 REG_RXFLTMAP6_8821C (RX FILTER MAP GROUP 6) */\n#define BIT_ACTIONFLT15EN_FW_8821C BIT(15)\n#define BIT_ACTIONFLT14EN_FW_8821C BIT(14)\n#define BIT_ACTIONFLT13EN_FW_8821C BIT(13)\n#define BIT_ACTIONFLT12EN_FW_8821C BIT(12)\n#define BIT_ACTIONFLT11EN_FW_8821C BIT(11)\n#define BIT_ACTIONFLT10EN_FW_8821C BIT(10)\n#define BIT_ACTIONFLT9EN_FW_8821C BIT(9)\n#define BIT_ACTIONFLT8EN_FW_8821C BIT(8)\n#define BIT_ACTIONFLT7EN_FW_8821C BIT(7)\n#define BIT_ACTIONFLT6EN_FW_8821C BIT(6)\n#define BIT_ACTIONFLT5EN_FW_8821C BIT(5)\n#define BIT_ACTIONFLT4EN_FW_8821C BIT(4)\n#define BIT_ACTIONFLT3EN_FW_8821C BIT(3)\n#define BIT_ACTIONFLT2EN_FW_8821C BIT(2)\n#define BIT_ACTIONFLT1EN_FW_8821C BIT(1)\n#define BIT_ACTIONFLT0EN_FW_8821C BIT(0)\n\n/* 2 REG_WOW_CTRL_8821C (WAKE ON WLAN CONTROL REGISTER) */\n\n#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C 6\n#define BIT_MASK_PSF_BSSIDSEL_B2B1_8821C 0x3\n#define BIT_PSF_BSSIDSEL_B2B1_8821C(x)                                         \\\n\t(((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8821C)                              \\\n\t << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C)\n#define BITS_PSF_BSSIDSEL_B2B1_8821C                                           \\\n\t(BIT_MASK_PSF_BSSIDSEL_B2B1_8821C << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C)\n#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8821C(x)                                   \\\n\t((x) & (~BITS_PSF_BSSIDSEL_B2B1_8821C))\n#define BIT_GET_PSF_BSSIDSEL_B2B1_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) &                          \\\n\t BIT_MASK_PSF_BSSIDSEL_B2B1_8821C)\n#define BIT_SET_PSF_BSSIDSEL_B2B1_8821C(x, v)                                  \\\n\t(BIT_CLEAR_PSF_BSSIDSEL_B2B1_8821C(x) | BIT_PSF_BSSIDSEL_B2B1_8821C(v))\n\n#define BIT_WOWHCI_8821C BIT(5)\n#define BIT_PSF_BSSIDSEL_B0_8821C BIT(4)\n#define BIT_UWF_8821C BIT(3)\n#define BIT_MAGIC_8821C BIT(2)\n#define BIT_WOWEN_8821C BIT(1)\n#define BIT_FORCE_WAKEUP_8821C BIT(0)\n\n/* 2 REG_NAN_RX_TSF_FILTER_8821C(NAN_RX_TSF_ADDRESS_FILTER) */\n#define BIT_CHK_TSF_TA_8821C BIT(2)\n#define BIT_CHK_TSF_CBSSID_8821C BIT(1)\n#define BIT_CHK_TSF_EN_8821C BIT(0)\n\n/* 2 REG_PS_RX_INFO_8821C (POWER SAVE RX INFORMATION REGISTER) */\n\n#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C 5\n#define BIT_MASK_PORTSEL__PS_RX_INFO_8821C 0x7\n#define BIT_PORTSEL__PS_RX_INFO_8821C(x)                                       \\\n\t(((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8821C)                            \\\n\t << BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C)\n#define BITS_PORTSEL__PS_RX_INFO_8821C                                         \\\n\t(BIT_MASK_PORTSEL__PS_RX_INFO_8821C                                    \\\n\t << BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C)\n#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8821C(x)                                 \\\n\t((x) & (~BITS_PORTSEL__PS_RX_INFO_8821C))\n#define BIT_GET_PORTSEL__PS_RX_INFO_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) &                        \\\n\t BIT_MASK_PORTSEL__PS_RX_INFO_8821C)\n#define BIT_SET_PORTSEL__PS_RX_INFO_8821C(x, v)                                \\\n\t(BIT_CLEAR_PORTSEL__PS_RX_INFO_8821C(x) |                              \\\n\t BIT_PORTSEL__PS_RX_INFO_8821C(v))\n\n#define BIT_RXCTRLIN0_8821C BIT(4)\n#define BIT_RXMGTIN0_8821C BIT(3)\n#define BIT_RXDATAIN2_8821C BIT(2)\n#define BIT_RXDATAIN1_8821C BIT(1)\n#define BIT_RXDATAIN0_8821C BIT(0)\n\n/* 2 REG_WMMPS_UAPSD_TID_8821C (WMM POWER SAVE UAPSD TID REGISTER) */\n#define BIT_WMMPS_UAPSD_TID7_8821C BIT(7)\n#define BIT_WMMPS_UAPSD_TID6_8821C BIT(6)\n#define BIT_WMMPS_UAPSD_TID5_8821C BIT(5)\n#define BIT_WMMPS_UAPSD_TID4_8821C BIT(4)\n#define BIT_WMMPS_UAPSD_TID3_8821C BIT(3)\n#define BIT_WMMPS_UAPSD_TID2_8821C BIT(2)\n#define BIT_WMMPS_UAPSD_TID1_8821C BIT(1)\n#define BIT_WMMPS_UAPSD_TID0_8821C BIT(0)\n\n/* 2 REG_LPNAV_CTRL_8821C (LOW POWER NAV CONTROL REGISTER) */\n#define BIT_LPNAV_EN_8821C BIT(31)\n\n#define BIT_SHIFT_LPNAV_EARLY_8821C 16\n#define BIT_MASK_LPNAV_EARLY_8821C 0x7fff\n#define BIT_LPNAV_EARLY_8821C(x)                                               \\\n\t(((x) & BIT_MASK_LPNAV_EARLY_8821C) << BIT_SHIFT_LPNAV_EARLY_8821C)\n#define BITS_LPNAV_EARLY_8821C                                                 \\\n\t(BIT_MASK_LPNAV_EARLY_8821C << BIT_SHIFT_LPNAV_EARLY_8821C)\n#define BIT_CLEAR_LPNAV_EARLY_8821C(x) ((x) & (~BITS_LPNAV_EARLY_8821C))\n#define BIT_GET_LPNAV_EARLY_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_LPNAV_EARLY_8821C) & BIT_MASK_LPNAV_EARLY_8821C)\n#define BIT_SET_LPNAV_EARLY_8821C(x, v)                                        \\\n\t(BIT_CLEAR_LPNAV_EARLY_8821C(x) | BIT_LPNAV_EARLY_8821C(v))\n\n#define BIT_SHIFT_LPNAV_TH_8821C 0\n#define BIT_MASK_LPNAV_TH_8821C 0xffff\n#define BIT_LPNAV_TH_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_LPNAV_TH_8821C) << BIT_SHIFT_LPNAV_TH_8821C)\n#define BITS_LPNAV_TH_8821C                                                    \\\n\t(BIT_MASK_LPNAV_TH_8821C << BIT_SHIFT_LPNAV_TH_8821C)\n#define BIT_CLEAR_LPNAV_TH_8821C(x) ((x) & (~BITS_LPNAV_TH_8821C))\n#define BIT_GET_LPNAV_TH_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_LPNAV_TH_8821C) & BIT_MASK_LPNAV_TH_8821C)\n#define BIT_SET_LPNAV_TH_8821C(x, v)                                           \\\n\t(BIT_CLEAR_LPNAV_TH_8821C(x) | BIT_LPNAV_TH_8821C(v))\n\n/* 2 REG_WKFMCAM_CMD_8821C (WAKEUP FRAME CAM COMMAND REGISTER) */\n#define BIT_WKFCAM_POLLING_V1_8821C BIT(31)\n#define BIT_WKFCAM_CLR_V1_8821C BIT(30)\n#define BIT_WKFCAM_WE_8821C BIT(16)\n\n#define BIT_SHIFT_WKFCAM_ADDR_V2_8821C 8\n#define BIT_MASK_WKFCAM_ADDR_V2_8821C 0xff\n#define BIT_WKFCAM_ADDR_V2_8821C(x)                                            \\\n\t(((x) & BIT_MASK_WKFCAM_ADDR_V2_8821C)                                 \\\n\t << BIT_SHIFT_WKFCAM_ADDR_V2_8821C)\n#define BITS_WKFCAM_ADDR_V2_8821C                                              \\\n\t(BIT_MASK_WKFCAM_ADDR_V2_8821C << BIT_SHIFT_WKFCAM_ADDR_V2_8821C)\n#define BIT_CLEAR_WKFCAM_ADDR_V2_8821C(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8821C))\n#define BIT_GET_WKFCAM_ADDR_V2_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8821C) &                             \\\n\t BIT_MASK_WKFCAM_ADDR_V2_8821C)\n#define BIT_SET_WKFCAM_ADDR_V2_8821C(x, v)                                     \\\n\t(BIT_CLEAR_WKFCAM_ADDR_V2_8821C(x) | BIT_WKFCAM_ADDR_V2_8821C(v))\n\n#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C 0\n#define BIT_MASK_WKFCAM_CAM_NUM_V1_8821C 0xff\n#define BIT_WKFCAM_CAM_NUM_V1_8821C(x)                                         \\\n\t(((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8821C)                              \\\n\t << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C)\n#define BITS_WKFCAM_CAM_NUM_V1_8821C                                           \\\n\t(BIT_MASK_WKFCAM_CAM_NUM_V1_8821C << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C)\n#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8821C(x)                                   \\\n\t((x) & (~BITS_WKFCAM_CAM_NUM_V1_8821C))\n#define BIT_GET_WKFCAM_CAM_NUM_V1_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C) &                          \\\n\t BIT_MASK_WKFCAM_CAM_NUM_V1_8821C)\n#define BIT_SET_WKFCAM_CAM_NUM_V1_8821C(x, v)                                  \\\n\t(BIT_CLEAR_WKFCAM_CAM_NUM_V1_8821C(x) | BIT_WKFCAM_CAM_NUM_V1_8821C(v))\n\n/* 2 REG_WKFMCAM_RWD_8821C (WAKEUP FRAME READ/WRITE DATA) */\n\n#define BIT_SHIFT_WKFMCAM_RWD_8821C 0\n#define BIT_MASK_WKFMCAM_RWD_8821C 0xffffffffL\n#define BIT_WKFMCAM_RWD_8821C(x)                                               \\\n\t(((x) & BIT_MASK_WKFMCAM_RWD_8821C) << BIT_SHIFT_WKFMCAM_RWD_8821C)\n#define BITS_WKFMCAM_RWD_8821C                                                 \\\n\t(BIT_MASK_WKFMCAM_RWD_8821C << BIT_SHIFT_WKFMCAM_RWD_8821C)\n#define BIT_CLEAR_WKFMCAM_RWD_8821C(x) ((x) & (~BITS_WKFMCAM_RWD_8821C))\n#define BIT_GET_WKFMCAM_RWD_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_WKFMCAM_RWD_8821C) & BIT_MASK_WKFMCAM_RWD_8821C)\n#define BIT_SET_WKFMCAM_RWD_8821C(x, v)                                        \\\n\t(BIT_CLEAR_WKFMCAM_RWD_8821C(x) | BIT_WKFMCAM_RWD_8821C(v))\n\n/* 2 REG_RXFLTMAP0_8821C (RX FILTER MAP GROUP 0) */\n#define BIT_MGTFLT15EN_8821C BIT(15)\n#define BIT_MGTFLT14EN_8821C BIT(14)\n#define BIT_MGTFLT13EN_8821C BIT(13)\n#define BIT_MGTFLT12EN_8821C BIT(12)\n#define BIT_MGTFLT11EN_8821C BIT(11)\n#define BIT_MGTFLT10EN_8821C BIT(10)\n#define BIT_MGTFLT9EN_8821C BIT(9)\n#define BIT_MGTFLT8EN_8821C BIT(8)\n#define BIT_MGTFLT7EN_8821C BIT(7)\n#define BIT_MGTFLT6EN_8821C BIT(6)\n#define BIT_MGTFLT5EN_8821C BIT(5)\n#define BIT_MGTFLT4EN_8821C BIT(4)\n#define BIT_MGTFLT3EN_8821C BIT(3)\n#define BIT_MGTFLT2EN_8821C BIT(2)\n#define BIT_MGTFLT1EN_8821C BIT(1)\n#define BIT_MGTFLT0EN_8821C BIT(0)\n\n/* 2 REG_RXFLTMAP1_8821C (RX FILTER MAP GROUP 1) */\n#define BIT_CTRLFLT15EN_8821C BIT(15)\n#define BIT_CTRLFLT14EN_8821C BIT(14)\n#define BIT_CTRLFLT13EN_8821C BIT(13)\n#define BIT_CTRLFLT12EN_8821C BIT(12)\n#define BIT_CTRLFLT11EN_8821C BIT(11)\n#define BIT_CTRLFLT10EN_8821C BIT(10)\n#define BIT_CTRLFLT9EN_8821C BIT(9)\n#define BIT_CTRLFLT8EN_8821C BIT(8)\n#define BIT_CTRLFLT7EN_8821C BIT(7)\n#define BIT_CTRLFLT6EN_8821C BIT(6)\n#define BIT_CTRLFLT5EN_8821C BIT(5)\n#define BIT_CTRLFLT4EN_8821C BIT(4)\n#define BIT_CTRLFLT3EN_8821C BIT(3)\n#define BIT_CTRLFLT2EN_8821C BIT(2)\n#define BIT_CTRLFLT1EN_8821C BIT(1)\n#define BIT_CTRLFLT0EN_8821C BIT(0)\n\n/* 2 REG_RXFLTMAP2_8821C (RX FILTER MAP GROUP 2) */\n#define BIT_DATAFLT15EN_8821C BIT(15)\n#define BIT_DATAFLT14EN_8821C BIT(14)\n#define BIT_DATAFLT13EN_8821C BIT(13)\n#define BIT_DATAFLT12EN_8821C BIT(12)\n#define BIT_DATAFLT11EN_8821C BIT(11)\n#define BIT_DATAFLT10EN_8821C BIT(10)\n#define BIT_DATAFLT9EN_8821C BIT(9)\n#define BIT_DATAFLT8EN_8821C BIT(8)\n#define BIT_DATAFLT7EN_8821C BIT(7)\n#define BIT_DATAFLT6EN_8821C BIT(6)\n#define BIT_DATAFLT5EN_8821C BIT(5)\n#define BIT_DATAFLT4EN_8821C BIT(4)\n#define BIT_DATAFLT3EN_8821C BIT(3)\n#define BIT_DATAFLT2EN_8821C BIT(2)\n#define BIT_DATAFLT1EN_8821C BIT(1)\n#define BIT_DATAFLT0EN_8821C BIT(0)\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_BCN_PSR_RPT_8821C (BEACON PARSER REPORT REGISTER) */\n\n#define BIT_SHIFT_DTIM_CNT_8821C 24\n#define BIT_MASK_DTIM_CNT_8821C 0xff\n#define BIT_DTIM_CNT_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_DTIM_CNT_8821C) << BIT_SHIFT_DTIM_CNT_8821C)\n#define BITS_DTIM_CNT_8821C                                                    \\\n\t(BIT_MASK_DTIM_CNT_8821C << BIT_SHIFT_DTIM_CNT_8821C)\n#define BIT_CLEAR_DTIM_CNT_8821C(x) ((x) & (~BITS_DTIM_CNT_8821C))\n#define BIT_GET_DTIM_CNT_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT_8821C) & BIT_MASK_DTIM_CNT_8821C)\n#define BIT_SET_DTIM_CNT_8821C(x, v)                                           \\\n\t(BIT_CLEAR_DTIM_CNT_8821C(x) | BIT_DTIM_CNT_8821C(v))\n\n#define BIT_SHIFT_DTIM_PERIOD_8821C 16\n#define BIT_MASK_DTIM_PERIOD_8821C 0xff\n#define BIT_DTIM_PERIOD_8821C(x)                                               \\\n\t(((x) & BIT_MASK_DTIM_PERIOD_8821C) << BIT_SHIFT_DTIM_PERIOD_8821C)\n#define BITS_DTIM_PERIOD_8821C                                                 \\\n\t(BIT_MASK_DTIM_PERIOD_8821C << BIT_SHIFT_DTIM_PERIOD_8821C)\n#define BIT_CLEAR_DTIM_PERIOD_8821C(x) ((x) & (~BITS_DTIM_PERIOD_8821C))\n#define BIT_GET_DTIM_PERIOD_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD_8821C) & BIT_MASK_DTIM_PERIOD_8821C)\n#define BIT_SET_DTIM_PERIOD_8821C(x, v)                                        \\\n\t(BIT_CLEAR_DTIM_PERIOD_8821C(x) | BIT_DTIM_PERIOD_8821C(v))\n\n#define BIT_DTIM_8821C BIT(15)\n#define BIT_TIM_8821C BIT(14)\n#define BIT_RPT_VALID_8821C BIT(13)\n\n#define BIT_SHIFT_PS_AID_0_8821C 0\n#define BIT_MASK_PS_AID_0_8821C 0x7ff\n#define BIT_PS_AID_0_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_0_8821C) << BIT_SHIFT_PS_AID_0_8821C)\n#define BITS_PS_AID_0_8821C                                                    \\\n\t(BIT_MASK_PS_AID_0_8821C << BIT_SHIFT_PS_AID_0_8821C)\n#define BIT_CLEAR_PS_AID_0_8821C(x) ((x) & (~BITS_PS_AID_0_8821C))\n#define BIT_GET_PS_AID_0_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_0_8821C) & BIT_MASK_PS_AID_0_8821C)\n#define BIT_SET_PS_AID_0_8821C(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_0_8821C(x) | BIT_PS_AID_0_8821C(v))\n\n/* 2 REG_FLC_RPC_8821C (FW LPS CONDITION -- RX PKT COUNTER) */\n\n#define BIT_SHIFT_FLC_RPC_8821C 0\n#define BIT_MASK_FLC_RPC_8821C 0xff\n#define BIT_FLC_RPC_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_FLC_RPC_8821C) << BIT_SHIFT_FLC_RPC_8821C)\n#define BITS_FLC_RPC_8821C (BIT_MASK_FLC_RPC_8821C << BIT_SHIFT_FLC_RPC_8821C)\n#define BIT_CLEAR_FLC_RPC_8821C(x) ((x) & (~BITS_FLC_RPC_8821C))\n#define BIT_GET_FLC_RPC_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_FLC_RPC_8821C) & BIT_MASK_FLC_RPC_8821C)\n#define BIT_SET_FLC_RPC_8821C(x, v)                                            \\\n\t(BIT_CLEAR_FLC_RPC_8821C(x) | BIT_FLC_RPC_8821C(v))\n\n/* 2 REG_FLC_RPCT_8821C (FLC_RPC THRESHOLD) */\n\n#define BIT_SHIFT_FLC_RPCT_8821C 0\n#define BIT_MASK_FLC_RPCT_8821C 0xff\n#define BIT_FLC_RPCT_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_FLC_RPCT_8821C) << BIT_SHIFT_FLC_RPCT_8821C)\n#define BITS_FLC_RPCT_8821C                                                    \\\n\t(BIT_MASK_FLC_RPCT_8821C << BIT_SHIFT_FLC_RPCT_8821C)\n#define BIT_CLEAR_FLC_RPCT_8821C(x) ((x) & (~BITS_FLC_RPCT_8821C))\n#define BIT_GET_FLC_RPCT_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_FLC_RPCT_8821C) & BIT_MASK_FLC_RPCT_8821C)\n#define BIT_SET_FLC_RPCT_8821C(x, v)                                           \\\n\t(BIT_CLEAR_FLC_RPCT_8821C(x) | BIT_FLC_RPCT_8821C(v))\n\n/* 2 REG_FLC_PTS_8821C (PKT TYPE SELECTION OF FLC_RPC T) */\n#define BIT_CMF_8821C BIT(2)\n#define BIT_CCF_8821C BIT(1)\n#define BIT_CDF_8821C BIT(0)\n\n/* 2 REG_FLC_TRPC_8821C (TIMER OF FLC_RPC) */\n#define BIT_FLC_RPCT_V1_8821C BIT(7)\n#define BIT_MODE_8821C BIT(6)\n\n#define BIT_SHIFT_TRPCD_8821C 0\n#define BIT_MASK_TRPCD_8821C 0x3f\n#define BIT_TRPCD_8821C(x)                                                     \\\n\t(((x) & BIT_MASK_TRPCD_8821C) << BIT_SHIFT_TRPCD_8821C)\n#define BITS_TRPCD_8821C (BIT_MASK_TRPCD_8821C << BIT_SHIFT_TRPCD_8821C)\n#define BIT_CLEAR_TRPCD_8821C(x) ((x) & (~BITS_TRPCD_8821C))\n#define BIT_GET_TRPCD_8821C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TRPCD_8821C) & BIT_MASK_TRPCD_8821C)\n#define BIT_SET_TRPCD_8821C(x, v)                                              \\\n\t(BIT_CLEAR_TRPCD_8821C(x) | BIT_TRPCD_8821C(v))\n\n/* 2 REG_RXPKTMON_CTRL_8821C */\n\n#define BIT_SHIFT_RXBKQPKT_SEQ_8821C 20\n#define BIT_MASK_RXBKQPKT_SEQ_8821C 0xf\n#define BIT_RXBKQPKT_SEQ_8821C(x)                                              \\\n\t(((x) & BIT_MASK_RXBKQPKT_SEQ_8821C) << BIT_SHIFT_RXBKQPKT_SEQ_8821C)\n#define BITS_RXBKQPKT_SEQ_8821C                                                \\\n\t(BIT_MASK_RXBKQPKT_SEQ_8821C << BIT_SHIFT_RXBKQPKT_SEQ_8821C)\n#define BIT_CLEAR_RXBKQPKT_SEQ_8821C(x) ((x) & (~BITS_RXBKQPKT_SEQ_8821C))\n#define BIT_GET_RXBKQPKT_SEQ_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8821C) & BIT_MASK_RXBKQPKT_SEQ_8821C)\n#define BIT_SET_RXBKQPKT_SEQ_8821C(x, v)                                       \\\n\t(BIT_CLEAR_RXBKQPKT_SEQ_8821C(x) | BIT_RXBKQPKT_SEQ_8821C(v))\n\n#define BIT_SHIFT_RXBEQPKT_SEQ_8821C 16\n#define BIT_MASK_RXBEQPKT_SEQ_8821C 0xf\n#define BIT_RXBEQPKT_SEQ_8821C(x)                                              \\\n\t(((x) & BIT_MASK_RXBEQPKT_SEQ_8821C) << BIT_SHIFT_RXBEQPKT_SEQ_8821C)\n#define BITS_RXBEQPKT_SEQ_8821C                                                \\\n\t(BIT_MASK_RXBEQPKT_SEQ_8821C << BIT_SHIFT_RXBEQPKT_SEQ_8821C)\n#define BIT_CLEAR_RXBEQPKT_SEQ_8821C(x) ((x) & (~BITS_RXBEQPKT_SEQ_8821C))\n#define BIT_GET_RXBEQPKT_SEQ_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8821C) & BIT_MASK_RXBEQPKT_SEQ_8821C)\n#define BIT_SET_RXBEQPKT_SEQ_8821C(x, v)                                       \\\n\t(BIT_CLEAR_RXBEQPKT_SEQ_8821C(x) | BIT_RXBEQPKT_SEQ_8821C(v))\n\n#define BIT_SHIFT_RXVIQPKT_SEQ_8821C 12\n#define BIT_MASK_RXVIQPKT_SEQ_8821C 0xf\n#define BIT_RXVIQPKT_SEQ_8821C(x)                                              \\\n\t(((x) & BIT_MASK_RXVIQPKT_SEQ_8821C) << BIT_SHIFT_RXVIQPKT_SEQ_8821C)\n#define BITS_RXVIQPKT_SEQ_8821C                                                \\\n\t(BIT_MASK_RXVIQPKT_SEQ_8821C << BIT_SHIFT_RXVIQPKT_SEQ_8821C)\n#define BIT_CLEAR_RXVIQPKT_SEQ_8821C(x) ((x) & (~BITS_RXVIQPKT_SEQ_8821C))\n#define BIT_GET_RXVIQPKT_SEQ_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8821C) & BIT_MASK_RXVIQPKT_SEQ_8821C)\n#define BIT_SET_RXVIQPKT_SEQ_8821C(x, v)                                       \\\n\t(BIT_CLEAR_RXVIQPKT_SEQ_8821C(x) | BIT_RXVIQPKT_SEQ_8821C(v))\n\n#define BIT_SHIFT_RXVOQPKT_SEQ_8821C 8\n#define BIT_MASK_RXVOQPKT_SEQ_8821C 0xf\n#define BIT_RXVOQPKT_SEQ_8821C(x)                                              \\\n\t(((x) & BIT_MASK_RXVOQPKT_SEQ_8821C) << BIT_SHIFT_RXVOQPKT_SEQ_8821C)\n#define BITS_RXVOQPKT_SEQ_8821C                                                \\\n\t(BIT_MASK_RXVOQPKT_SEQ_8821C << BIT_SHIFT_RXVOQPKT_SEQ_8821C)\n#define BIT_CLEAR_RXVOQPKT_SEQ_8821C(x) ((x) & (~BITS_RXVOQPKT_SEQ_8821C))\n#define BIT_GET_RXVOQPKT_SEQ_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8821C) & BIT_MASK_RXVOQPKT_SEQ_8821C)\n#define BIT_SET_RXVOQPKT_SEQ_8821C(x, v)                                       \\\n\t(BIT_CLEAR_RXVOQPKT_SEQ_8821C(x) | BIT_RXVOQPKT_SEQ_8821C(v))\n\n#define BIT_RXBKQPKT_ERR_8821C BIT(7)\n#define BIT_RXBEQPKT_ERR_8821C BIT(6)\n#define BIT_RXVIQPKT_ERR_8821C BIT(5)\n#define BIT_RXVOQPKT_ERR_8821C BIT(4)\n#define BIT_RXDMA_MON_EN_8821C BIT(2)\n#define BIT_RXPKT_MON_RST_8821C BIT(1)\n#define BIT_RXPKT_MON_EN_8821C BIT(0)\n\n/* 2 REG_STATE_MON_8821C */\n\n#define BIT_SHIFT_STATE_SEL_8821C 24\n#define BIT_MASK_STATE_SEL_8821C 0x1f\n#define BIT_STATE_SEL_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_STATE_SEL_8821C) << BIT_SHIFT_STATE_SEL_8821C)\n#define BITS_STATE_SEL_8821C                                                   \\\n\t(BIT_MASK_STATE_SEL_8821C << BIT_SHIFT_STATE_SEL_8821C)\n#define BIT_CLEAR_STATE_SEL_8821C(x) ((x) & (~BITS_STATE_SEL_8821C))\n#define BIT_GET_STATE_SEL_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_STATE_SEL_8821C) & BIT_MASK_STATE_SEL_8821C)\n#define BIT_SET_STATE_SEL_8821C(x, v)                                          \\\n\t(BIT_CLEAR_STATE_SEL_8821C(x) | BIT_STATE_SEL_8821C(v))\n\n#define BIT_SHIFT_STATE_INFO_8821C 8\n#define BIT_MASK_STATE_INFO_8821C 0xff\n#define BIT_STATE_INFO_8821C(x)                                                \\\n\t(((x) & BIT_MASK_STATE_INFO_8821C) << BIT_SHIFT_STATE_INFO_8821C)\n#define BITS_STATE_INFO_8821C                                                  \\\n\t(BIT_MASK_STATE_INFO_8821C << BIT_SHIFT_STATE_INFO_8821C)\n#define BIT_CLEAR_STATE_INFO_8821C(x) ((x) & (~BITS_STATE_INFO_8821C))\n#define BIT_GET_STATE_INFO_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_STATE_INFO_8821C) & BIT_MASK_STATE_INFO_8821C)\n#define BIT_SET_STATE_INFO_8821C(x, v)                                         \\\n\t(BIT_CLEAR_STATE_INFO_8821C(x) | BIT_STATE_INFO_8821C(v))\n\n#define BIT_UPD_NXT_STATE_8821C BIT(7)\n\n#define BIT_SHIFT_CUR_STATE_8821C 0\n#define BIT_MASK_CUR_STATE_8821C 0x7f\n#define BIT_CUR_STATE_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_CUR_STATE_8821C) << BIT_SHIFT_CUR_STATE_8821C)\n#define BITS_CUR_STATE_8821C                                                   \\\n\t(BIT_MASK_CUR_STATE_8821C << BIT_SHIFT_CUR_STATE_8821C)\n#define BIT_CLEAR_CUR_STATE_8821C(x) ((x) & (~BITS_CUR_STATE_8821C))\n#define BIT_GET_CUR_STATE_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_CUR_STATE_8821C) & BIT_MASK_CUR_STATE_8821C)\n#define BIT_SET_CUR_STATE_8821C(x, v)                                          \\\n\t(BIT_CLEAR_CUR_STATE_8821C(x) | BIT_CUR_STATE_8821C(v))\n\n/* 2 REG_ERROR_MON_8821C */\n#define BIT_MACRX_ERR_1_8821C BIT(17)\n#define BIT_MACRX_ERR_0_8821C BIT(16)\n#define BIT_MACTX_ERR_3_8821C BIT(3)\n#define BIT_MACTX_ERR_2_8821C BIT(2)\n#define BIT_MACTX_ERR_1_8821C BIT(1)\n#define BIT_MACTX_ERR_0_8821C BIT(0)\n\n/* 2 REG_SEARCH_MACID_8821C */\n#define BIT_EN_TXRPTBUF_CLK_8821C BIT(31)\n\n#define BIT_SHIFT_INFO_INDEX_OFFSET_8821C 16\n#define BIT_MASK_INFO_INDEX_OFFSET_8821C 0x1fff\n#define BIT_INFO_INDEX_OFFSET_8821C(x)                                         \\\n\t(((x) & BIT_MASK_INFO_INDEX_OFFSET_8821C)                              \\\n\t << BIT_SHIFT_INFO_INDEX_OFFSET_8821C)\n#define BITS_INFO_INDEX_OFFSET_8821C                                           \\\n\t(BIT_MASK_INFO_INDEX_OFFSET_8821C << BIT_SHIFT_INFO_INDEX_OFFSET_8821C)\n#define BIT_CLEAR_INFO_INDEX_OFFSET_8821C(x)                                   \\\n\t((x) & (~BITS_INFO_INDEX_OFFSET_8821C))\n#define BIT_GET_INFO_INDEX_OFFSET_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8821C) &                          \\\n\t BIT_MASK_INFO_INDEX_OFFSET_8821C)\n#define BIT_SET_INFO_INDEX_OFFSET_8821C(x, v)                                  \\\n\t(BIT_CLEAR_INFO_INDEX_OFFSET_8821C(x) | BIT_INFO_INDEX_OFFSET_8821C(v))\n\n#define BIT_WMAC_SRCH_FIFOFULL_8821C BIT(15)\n#define BIT_DIS_INFOSRCH_8821C BIT(14)\n#define BIT_DISABLE_B0_8821C BIT(13)\n\n#define BIT_SHIFT_INFO_ADDR_OFFSET_8821C 0\n#define BIT_MASK_INFO_ADDR_OFFSET_8821C 0x1fff\n#define BIT_INFO_ADDR_OFFSET_8821C(x)                                          \\\n\t(((x) & BIT_MASK_INFO_ADDR_OFFSET_8821C)                               \\\n\t << BIT_SHIFT_INFO_ADDR_OFFSET_8821C)\n#define BITS_INFO_ADDR_OFFSET_8821C                                            \\\n\t(BIT_MASK_INFO_ADDR_OFFSET_8821C << BIT_SHIFT_INFO_ADDR_OFFSET_8821C)\n#define BIT_CLEAR_INFO_ADDR_OFFSET_8821C(x)                                    \\\n\t((x) & (~BITS_INFO_ADDR_OFFSET_8821C))\n#define BIT_GET_INFO_ADDR_OFFSET_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8821C) &                           \\\n\t BIT_MASK_INFO_ADDR_OFFSET_8821C)\n#define BIT_SET_INFO_ADDR_OFFSET_8821C(x, v)                                   \\\n\t(BIT_CLEAR_INFO_ADDR_OFFSET_8821C(x) | BIT_INFO_ADDR_OFFSET_8821C(v))\n\n/* 2 REG_BT_COEX_TABLE_8821C (BT-COEXISTENCE CONTROL REGISTER) */\n\n#define BIT_SHIFT_COEX_TABLE_1_8821C 0\n#define BIT_MASK_COEX_TABLE_1_8821C 0xffffffffL\n#define BIT_COEX_TABLE_1_8821C(x)                                              \\\n\t(((x) & BIT_MASK_COEX_TABLE_1_8821C) << BIT_SHIFT_COEX_TABLE_1_8821C)\n#define BITS_COEX_TABLE_1_8821C                                                \\\n\t(BIT_MASK_COEX_TABLE_1_8821C << BIT_SHIFT_COEX_TABLE_1_8821C)\n#define BIT_CLEAR_COEX_TABLE_1_8821C(x) ((x) & (~BITS_COEX_TABLE_1_8821C))\n#define BIT_GET_COEX_TABLE_1_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_COEX_TABLE_1_8821C) & BIT_MASK_COEX_TABLE_1_8821C)\n#define BIT_SET_COEX_TABLE_1_8821C(x, v)                                       \\\n\t(BIT_CLEAR_COEX_TABLE_1_8821C(x) | BIT_COEX_TABLE_1_8821C(v))\n\n/* 2 REG_BT_COEX_TABLE2_8821C (BT-COEXISTENCE CONTROL REGISTER) */\n\n#define BIT_SHIFT_COEX_TABLE_2_8821C 0\n#define BIT_MASK_COEX_TABLE_2_8821C 0xffffffffL\n#define BIT_COEX_TABLE_2_8821C(x)                                              \\\n\t(((x) & BIT_MASK_COEX_TABLE_2_8821C) << BIT_SHIFT_COEX_TABLE_2_8821C)\n#define BITS_COEX_TABLE_2_8821C                                                \\\n\t(BIT_MASK_COEX_TABLE_2_8821C << BIT_SHIFT_COEX_TABLE_2_8821C)\n#define BIT_CLEAR_COEX_TABLE_2_8821C(x) ((x) & (~BITS_COEX_TABLE_2_8821C))\n#define BIT_GET_COEX_TABLE_2_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_COEX_TABLE_2_8821C) & BIT_MASK_COEX_TABLE_2_8821C)\n#define BIT_SET_COEX_TABLE_2_8821C(x, v)                                       \\\n\t(BIT_CLEAR_COEX_TABLE_2_8821C(x) | BIT_COEX_TABLE_2_8821C(v))\n\n/* 2 REG_BT_COEX_BREAK_TABLE_8821C (BT-COEXISTENCE CONTROL REGISTER) */\n\n#define BIT_SHIFT_BREAK_TABLE_2_8821C 16\n#define BIT_MASK_BREAK_TABLE_2_8821C 0xffff\n#define BIT_BREAK_TABLE_2_8821C(x)                                             \\\n\t(((x) & BIT_MASK_BREAK_TABLE_2_8821C) << BIT_SHIFT_BREAK_TABLE_2_8821C)\n#define BITS_BREAK_TABLE_2_8821C                                               \\\n\t(BIT_MASK_BREAK_TABLE_2_8821C << BIT_SHIFT_BREAK_TABLE_2_8821C)\n#define BIT_CLEAR_BREAK_TABLE_2_8821C(x) ((x) & (~BITS_BREAK_TABLE_2_8821C))\n#define BIT_GET_BREAK_TABLE_2_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BREAK_TABLE_2_8821C) & BIT_MASK_BREAK_TABLE_2_8821C)\n#define BIT_SET_BREAK_TABLE_2_8821C(x, v)                                      \\\n\t(BIT_CLEAR_BREAK_TABLE_2_8821C(x) | BIT_BREAK_TABLE_2_8821C(v))\n\n#define BIT_SHIFT_BREAK_TABLE_1_8821C 0\n#define BIT_MASK_BREAK_TABLE_1_8821C 0xffff\n#define BIT_BREAK_TABLE_1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_BREAK_TABLE_1_8821C) << BIT_SHIFT_BREAK_TABLE_1_8821C)\n#define BITS_BREAK_TABLE_1_8821C                                               \\\n\t(BIT_MASK_BREAK_TABLE_1_8821C << BIT_SHIFT_BREAK_TABLE_1_8821C)\n#define BIT_CLEAR_BREAK_TABLE_1_8821C(x) ((x) & (~BITS_BREAK_TABLE_1_8821C))\n#define BIT_GET_BREAK_TABLE_1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BREAK_TABLE_1_8821C) & BIT_MASK_BREAK_TABLE_1_8821C)\n#define BIT_SET_BREAK_TABLE_1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_BREAK_TABLE_1_8821C(x) | BIT_BREAK_TABLE_1_8821C(v))\n\n/* 2 REG_BT_COEX_TABLE_H_8821C (BT-COEXISTENCE CONTROL REGISTER) */\n#define BIT_PRI_MASK_RX_RESP_V1_8821C BIT(30)\n#define BIT_PRI_MASK_RXOFDM_V1_8821C BIT(29)\n#define BIT_PRI_MASK_RXCCK_V1_8821C BIT(28)\n\n#define BIT_SHIFT_PRI_MASK_TXAC_8821C 21\n#define BIT_MASK_PRI_MASK_TXAC_8821C 0x7f\n#define BIT_PRI_MASK_TXAC_8821C(x)                                             \\\n\t(((x) & BIT_MASK_PRI_MASK_TXAC_8821C) << BIT_SHIFT_PRI_MASK_TXAC_8821C)\n#define BITS_PRI_MASK_TXAC_8821C                                               \\\n\t(BIT_MASK_PRI_MASK_TXAC_8821C << BIT_SHIFT_PRI_MASK_TXAC_8821C)\n#define BIT_CLEAR_PRI_MASK_TXAC_8821C(x) ((x) & (~BITS_PRI_MASK_TXAC_8821C))\n#define BIT_GET_PRI_MASK_TXAC_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_TXAC_8821C) & BIT_MASK_PRI_MASK_TXAC_8821C)\n#define BIT_SET_PRI_MASK_TXAC_8821C(x, v)                                      \\\n\t(BIT_CLEAR_PRI_MASK_TXAC_8821C(x) | BIT_PRI_MASK_TXAC_8821C(v))\n\n#define BIT_SHIFT_PRI_MASK_NAV_8821C 13\n#define BIT_MASK_PRI_MASK_NAV_8821C 0xff\n#define BIT_PRI_MASK_NAV_8821C(x)                                              \\\n\t(((x) & BIT_MASK_PRI_MASK_NAV_8821C) << BIT_SHIFT_PRI_MASK_NAV_8821C)\n#define BITS_PRI_MASK_NAV_8821C                                                \\\n\t(BIT_MASK_PRI_MASK_NAV_8821C << BIT_SHIFT_PRI_MASK_NAV_8821C)\n#define BIT_CLEAR_PRI_MASK_NAV_8821C(x) ((x) & (~BITS_PRI_MASK_NAV_8821C))\n#define BIT_GET_PRI_MASK_NAV_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_NAV_8821C) & BIT_MASK_PRI_MASK_NAV_8821C)\n#define BIT_SET_PRI_MASK_NAV_8821C(x, v)                                       \\\n\t(BIT_CLEAR_PRI_MASK_NAV_8821C(x) | BIT_PRI_MASK_NAV_8821C(v))\n\n#define BIT_PRI_MASK_CCK_V1_8821C BIT(12)\n#define BIT_PRI_MASK_OFDM_V1_8821C BIT(11)\n#define BIT_PRI_MASK_RTY_V1_8821C BIT(10)\n\n#define BIT_SHIFT_PRI_MASK_NUM_8821C 6\n#define BIT_MASK_PRI_MASK_NUM_8821C 0xf\n#define BIT_PRI_MASK_NUM_8821C(x)                                              \\\n\t(((x) & BIT_MASK_PRI_MASK_NUM_8821C) << BIT_SHIFT_PRI_MASK_NUM_8821C)\n#define BITS_PRI_MASK_NUM_8821C                                                \\\n\t(BIT_MASK_PRI_MASK_NUM_8821C << BIT_SHIFT_PRI_MASK_NUM_8821C)\n#define BIT_CLEAR_PRI_MASK_NUM_8821C(x) ((x) & (~BITS_PRI_MASK_NUM_8821C))\n#define BIT_GET_PRI_MASK_NUM_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_NUM_8821C) & BIT_MASK_PRI_MASK_NUM_8821C)\n#define BIT_SET_PRI_MASK_NUM_8821C(x, v)                                       \\\n\t(BIT_CLEAR_PRI_MASK_NUM_8821C(x) | BIT_PRI_MASK_NUM_8821C(v))\n\n#define BIT_SHIFT_PRI_MASK_TYPE_8821C 2\n#define BIT_MASK_PRI_MASK_TYPE_8821C 0xf\n#define BIT_PRI_MASK_TYPE_8821C(x)                                             \\\n\t(((x) & BIT_MASK_PRI_MASK_TYPE_8821C) << BIT_SHIFT_PRI_MASK_TYPE_8821C)\n#define BITS_PRI_MASK_TYPE_8821C                                               \\\n\t(BIT_MASK_PRI_MASK_TYPE_8821C << BIT_SHIFT_PRI_MASK_TYPE_8821C)\n#define BIT_CLEAR_PRI_MASK_TYPE_8821C(x) ((x) & (~BITS_PRI_MASK_TYPE_8821C))\n#define BIT_GET_PRI_MASK_TYPE_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_TYPE_8821C) & BIT_MASK_PRI_MASK_TYPE_8821C)\n#define BIT_SET_PRI_MASK_TYPE_8821C(x, v)                                      \\\n\t(BIT_CLEAR_PRI_MASK_TYPE_8821C(x) | BIT_PRI_MASK_TYPE_8821C(v))\n\n#define BIT_OOB_V1_8821C BIT(1)\n#define BIT_ANT_SEL_V1_8821C BIT(0)\n\n/* 2 REG_RXCMD_0_8821C */\n#define BIT_RXCMD_EN_8821C BIT(31)\n\n#define BIT_SHIFT_RXCMD_INFO_8821C 0\n#define BIT_MASK_RXCMD_INFO_8821C 0x7fffffffL\n#define BIT_RXCMD_INFO_8821C(x)                                                \\\n\t(((x) & BIT_MASK_RXCMD_INFO_8821C) << BIT_SHIFT_RXCMD_INFO_8821C)\n#define BITS_RXCMD_INFO_8821C                                                  \\\n\t(BIT_MASK_RXCMD_INFO_8821C << BIT_SHIFT_RXCMD_INFO_8821C)\n#define BIT_CLEAR_RXCMD_INFO_8821C(x) ((x) & (~BITS_RXCMD_INFO_8821C))\n#define BIT_GET_RXCMD_INFO_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXCMD_INFO_8821C) & BIT_MASK_RXCMD_INFO_8821C)\n#define BIT_SET_RXCMD_INFO_8821C(x, v)                                         \\\n\t(BIT_CLEAR_RXCMD_INFO_8821C(x) | BIT_RXCMD_INFO_8821C(v))\n\n/* 2 REG_RXCMD_1_8821C */\n\n#define BIT_SHIFT_CSI_RADDR_LATCH_8821C 24\n#define BIT_MASK_CSI_RADDR_LATCH_8821C 0xff\n#define BIT_CSI_RADDR_LATCH_8821C(x)                                           \\\n\t(((x) & BIT_MASK_CSI_RADDR_LATCH_8821C)                                \\\n\t << BIT_SHIFT_CSI_RADDR_LATCH_8821C)\n#define BITS_CSI_RADDR_LATCH_8821C                                             \\\n\t(BIT_MASK_CSI_RADDR_LATCH_8821C << BIT_SHIFT_CSI_RADDR_LATCH_8821C)\n#define BIT_CLEAR_CSI_RADDR_LATCH_8821C(x) ((x) & (~BITS_CSI_RADDR_LATCH_8821C))\n#define BIT_GET_CSI_RADDR_LATCH_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_CSI_RADDR_LATCH_8821C) &                            \\\n\t BIT_MASK_CSI_RADDR_LATCH_8821C)\n#define BIT_SET_CSI_RADDR_LATCH_8821C(x, v)                                    \\\n\t(BIT_CLEAR_CSI_RADDR_LATCH_8821C(x) | BIT_CSI_RADDR_LATCH_8821C(v))\n\n#define BIT_SHIFT_CSI_WADDR_LATCH_8821C 16\n#define BIT_MASK_CSI_WADDR_LATCH_8821C 0xff\n#define BIT_CSI_WADDR_LATCH_8821C(x)                                           \\\n\t(((x) & BIT_MASK_CSI_WADDR_LATCH_8821C)                                \\\n\t << BIT_SHIFT_CSI_WADDR_LATCH_8821C)\n#define BITS_CSI_WADDR_LATCH_8821C                                             \\\n\t(BIT_MASK_CSI_WADDR_LATCH_8821C << BIT_SHIFT_CSI_WADDR_LATCH_8821C)\n#define BIT_CLEAR_CSI_WADDR_LATCH_8821C(x) ((x) & (~BITS_CSI_WADDR_LATCH_8821C))\n#define BIT_GET_CSI_WADDR_LATCH_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_CSI_WADDR_LATCH_8821C) &                            \\\n\t BIT_MASK_CSI_WADDR_LATCH_8821C)\n#define BIT_SET_CSI_WADDR_LATCH_8821C(x, v)                                    \\\n\t(BIT_CLEAR_CSI_WADDR_LATCH_8821C(x) | BIT_CSI_WADDR_LATCH_8821C(v))\n\n#define BIT_SHIFT_RXCMD_PRD_8821C 0\n#define BIT_MASK_RXCMD_PRD_8821C 0xffff\n#define BIT_RXCMD_PRD_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_RXCMD_PRD_8821C) << BIT_SHIFT_RXCMD_PRD_8821C)\n#define BITS_RXCMD_PRD_8821C                                                   \\\n\t(BIT_MASK_RXCMD_PRD_8821C << BIT_SHIFT_RXCMD_PRD_8821C)\n#define BIT_CLEAR_RXCMD_PRD_8821C(x) ((x) & (~BITS_RXCMD_PRD_8821C))\n#define BIT_GET_RXCMD_PRD_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_RXCMD_PRD_8821C) & BIT_MASK_RXCMD_PRD_8821C)\n#define BIT_SET_RXCMD_PRD_8821C(x, v)                                          \\\n\t(BIT_CLEAR_RXCMD_PRD_8821C(x) | BIT_RXCMD_PRD_8821C(v))\n\n/* 2 REG_WMAC_RESP_TXINFO_8821C (RESPONSE TXINFO REGISTER) */\n\n#define BIT_SHIFT_WMAC_RESP_MFB_8821C 25\n#define BIT_MASK_WMAC_RESP_MFB_8821C 0x7f\n#define BIT_WMAC_RESP_MFB_8821C(x)                                             \\\n\t(((x) & BIT_MASK_WMAC_RESP_MFB_8821C) << BIT_SHIFT_WMAC_RESP_MFB_8821C)\n#define BITS_WMAC_RESP_MFB_8821C                                               \\\n\t(BIT_MASK_WMAC_RESP_MFB_8821C << BIT_SHIFT_WMAC_RESP_MFB_8821C)\n#define BIT_CLEAR_WMAC_RESP_MFB_8821C(x) ((x) & (~BITS_WMAC_RESP_MFB_8821C))\n#define BIT_GET_WMAC_RESP_MFB_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_MFB_8821C) & BIT_MASK_WMAC_RESP_MFB_8821C)\n#define BIT_SET_WMAC_RESP_MFB_8821C(x, v)                                      \\\n\t(BIT_CLEAR_WMAC_RESP_MFB_8821C(x) | BIT_WMAC_RESP_MFB_8821C(v))\n\n#define BIT_SHIFT_WMAC_ANTINF_SEL_8821C 23\n#define BIT_MASK_WMAC_ANTINF_SEL_8821C 0x3\n#define BIT_WMAC_ANTINF_SEL_8821C(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_ANTINF_SEL_8821C)                                \\\n\t << BIT_SHIFT_WMAC_ANTINF_SEL_8821C)\n#define BITS_WMAC_ANTINF_SEL_8821C                                             \\\n\t(BIT_MASK_WMAC_ANTINF_SEL_8821C << BIT_SHIFT_WMAC_ANTINF_SEL_8821C)\n#define BIT_CLEAR_WMAC_ANTINF_SEL_8821C(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8821C))\n#define BIT_GET_WMAC_ANTINF_SEL_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8821C) &                            \\\n\t BIT_MASK_WMAC_ANTINF_SEL_8821C)\n#define BIT_SET_WMAC_ANTINF_SEL_8821C(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_ANTINF_SEL_8821C(x) | BIT_WMAC_ANTINF_SEL_8821C(v))\n\n#define BIT_SHIFT_WMAC_ANTSEL_SEL_8821C 21\n#define BIT_MASK_WMAC_ANTSEL_SEL_8821C 0x3\n#define BIT_WMAC_ANTSEL_SEL_8821C(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_ANTSEL_SEL_8821C)                                \\\n\t << BIT_SHIFT_WMAC_ANTSEL_SEL_8821C)\n#define BITS_WMAC_ANTSEL_SEL_8821C                                             \\\n\t(BIT_MASK_WMAC_ANTSEL_SEL_8821C << BIT_SHIFT_WMAC_ANTSEL_SEL_8821C)\n#define BIT_CLEAR_WMAC_ANTSEL_SEL_8821C(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8821C))\n#define BIT_GET_WMAC_ANTSEL_SEL_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) &                            \\\n\t BIT_MASK_WMAC_ANTSEL_SEL_8821C)\n#define BIT_SET_WMAC_ANTSEL_SEL_8821C(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_ANTSEL_SEL_8821C(x) | BIT_WMAC_ANTSEL_SEL_8821C(v))\n\n#define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C 18\n#define BIT_MASK_R_WMAC_RESP_TXPOWER_8821C 0x7\n#define BIT_R_WMAC_RESP_TXPOWER_8821C(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8821C)                            \\\n\t << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C)\n#define BITS_R_WMAC_RESP_TXPOWER_8821C                                         \\\n\t(BIT_MASK_R_WMAC_RESP_TXPOWER_8821C                                    \\\n\t << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C)\n#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8821C(x)                                 \\\n\t((x) & (~BITS_R_WMAC_RESP_TXPOWER_8821C))\n#define BIT_GET_R_WMAC_RESP_TXPOWER_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) &                        \\\n\t BIT_MASK_R_WMAC_RESP_TXPOWER_8821C)\n#define BIT_SET_R_WMAC_RESP_TXPOWER_8821C(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_RESP_TXPOWER_8821C(x) |                              \\\n\t BIT_R_WMAC_RESP_TXPOWER_8821C(v))\n\n#define BIT_SHIFT_WMAC_RESP_TXANT_8821C 0\n#define BIT_MASK_WMAC_RESP_TXANT_8821C 0x3ffff\n#define BIT_WMAC_RESP_TXANT_8821C(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_RESP_TXANT_8821C)                                \\\n\t << BIT_SHIFT_WMAC_RESP_TXANT_8821C)\n#define BITS_WMAC_RESP_TXANT_8821C                                             \\\n\t(BIT_MASK_WMAC_RESP_TXANT_8821C << BIT_SHIFT_WMAC_RESP_TXANT_8821C)\n#define BIT_CLEAR_WMAC_RESP_TXANT_8821C(x) ((x) & (~BITS_WMAC_RESP_TXANT_8821C))\n#define BIT_GET_WMAC_RESP_TXANT_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8821C) &                            \\\n\t BIT_MASK_WMAC_RESP_TXANT_8821C)\n#define BIT_SET_WMAC_RESP_TXANT_8821C(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_RESP_TXANT_8821C(x) | BIT_WMAC_RESP_TXANT_8821C(v))\n\n/* 2 REG_BBPSF_CTRL_8821C */\n#define BIT_CTL_IDLE_CLR_CSI_RPT_8821C BIT(31)\n#define BIT_WMAC_USE_NDPARATE_8821C BIT(30)\n\n#define BIT_SHIFT_WMAC_CSI_RATE_8821C 24\n#define BIT_MASK_WMAC_CSI_RATE_8821C 0x3f\n#define BIT_WMAC_CSI_RATE_8821C(x)                                             \\\n\t(((x) & BIT_MASK_WMAC_CSI_RATE_8821C) << BIT_SHIFT_WMAC_CSI_RATE_8821C)\n#define BITS_WMAC_CSI_RATE_8821C                                               \\\n\t(BIT_MASK_WMAC_CSI_RATE_8821C << BIT_SHIFT_WMAC_CSI_RATE_8821C)\n#define BIT_CLEAR_WMAC_CSI_RATE_8821C(x) ((x) & (~BITS_WMAC_CSI_RATE_8821C))\n#define BIT_GET_WMAC_CSI_RATE_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_WMAC_CSI_RATE_8821C) & BIT_MASK_WMAC_CSI_RATE_8821C)\n#define BIT_SET_WMAC_CSI_RATE_8821C(x, v)                                      \\\n\t(BIT_CLEAR_WMAC_CSI_RATE_8821C(x) | BIT_WMAC_CSI_RATE_8821C(v))\n\n#define BIT_SHIFT_WMAC_RESP_TXRATE_8821C 16\n#define BIT_MASK_WMAC_RESP_TXRATE_8821C 0xff\n#define BIT_WMAC_RESP_TXRATE_8821C(x)                                          \\\n\t(((x) & BIT_MASK_WMAC_RESP_TXRATE_8821C)                               \\\n\t << BIT_SHIFT_WMAC_RESP_TXRATE_8821C)\n#define BITS_WMAC_RESP_TXRATE_8821C                                            \\\n\t(BIT_MASK_WMAC_RESP_TXRATE_8821C << BIT_SHIFT_WMAC_RESP_TXRATE_8821C)\n#define BIT_CLEAR_WMAC_RESP_TXRATE_8821C(x)                                    \\\n\t((x) & (~BITS_WMAC_RESP_TXRATE_8821C))\n#define BIT_GET_WMAC_RESP_TXRATE_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8821C) &                           \\\n\t BIT_MASK_WMAC_RESP_TXRATE_8821C)\n#define BIT_SET_WMAC_RESP_TXRATE_8821C(x, v)                                   \\\n\t(BIT_CLEAR_WMAC_RESP_TXRATE_8821C(x) | BIT_WMAC_RESP_TXRATE_8821C(v))\n\n#define BIT_CSI_FORCE_RATE_EN_8821C BIT(15)\n\n#define BIT_SHIFT_CSI_RSC_8821C 13\n#define BIT_MASK_CSI_RSC_8821C 0x3\n#define BIT_CSI_RSC_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_CSI_RSC_8821C) << BIT_SHIFT_CSI_RSC_8821C)\n#define BITS_CSI_RSC_8821C (BIT_MASK_CSI_RSC_8821C << BIT_SHIFT_CSI_RSC_8821C)\n#define BIT_CLEAR_CSI_RSC_8821C(x) ((x) & (~BITS_CSI_RSC_8821C))\n#define BIT_GET_CSI_RSC_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_CSI_RSC_8821C) & BIT_MASK_CSI_RSC_8821C)\n#define BIT_SET_CSI_RSC_8821C(x, v)                                            \\\n\t(BIT_CLEAR_CSI_RSC_8821C(x) | BIT_CSI_RSC_8821C(v))\n\n#define BIT_CSI_GID_SEL_8821C BIT(12)\n#define BIT_RDCSIMD_FLAG_TRIG_SEL_8821C BIT(11)\n#define BIT_NDPVLD_POS_RST_FFPTR_DIS_V1_8821C BIT(10)\n#define BIT_NDPVLD_PROTECT_RDRDY_DIS_8821C BIT(9)\n#define BIT_RDCSI_EMPTY_APPZERO_8821C BIT(8)\n#define BIT_BBPSF_MPDUCHKEN_8821C BIT(5)\n#define BIT_BBPSF_MHCHKEN_8821C BIT(4)\n#define BIT_BBPSF_ERRCHKEN_8821C BIT(3)\n\n#define BIT_SHIFT_BBPSF_ERRTHR_8821C 0\n#define BIT_MASK_BBPSF_ERRTHR_8821C 0x7\n#define BIT_BBPSF_ERRTHR_8821C(x)                                              \\\n\t(((x) & BIT_MASK_BBPSF_ERRTHR_8821C) << BIT_SHIFT_BBPSF_ERRTHR_8821C)\n#define BITS_BBPSF_ERRTHR_8821C                                                \\\n\t(BIT_MASK_BBPSF_ERRTHR_8821C << BIT_SHIFT_BBPSF_ERRTHR_8821C)\n#define BIT_CLEAR_BBPSF_ERRTHR_8821C(x) ((x) & (~BITS_BBPSF_ERRTHR_8821C))\n#define BIT_GET_BBPSF_ERRTHR_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BBPSF_ERRTHR_8821C) & BIT_MASK_BBPSF_ERRTHR_8821C)\n#define BIT_SET_BBPSF_ERRTHR_8821C(x, v)                                       \\\n\t(BIT_CLEAR_BBPSF_ERRTHR_8821C(x) | BIT_BBPSF_ERRTHR_8821C(v))\n\n/* 2 REG_P2P_RX_BCN_NOA_8821C (P2P RX BEACON NOA REGISTER) */\n#define BIT_NOA_PARSER_EN_8821C BIT(15)\n#define BIT_BSSID_SEL_8821C BIT(14)\n\n#define BIT_SHIFT_P2P_OUI_TYPE_8821C 0\n#define BIT_MASK_P2P_OUI_TYPE_8821C 0xff\n#define BIT_P2P_OUI_TYPE_8821C(x)                                              \\\n\t(((x) & BIT_MASK_P2P_OUI_TYPE_8821C) << BIT_SHIFT_P2P_OUI_TYPE_8821C)\n#define BITS_P2P_OUI_TYPE_8821C                                                \\\n\t(BIT_MASK_P2P_OUI_TYPE_8821C << BIT_SHIFT_P2P_OUI_TYPE_8821C)\n#define BIT_CLEAR_P2P_OUI_TYPE_8821C(x) ((x) & (~BITS_P2P_OUI_TYPE_8821C))\n#define BIT_GET_P2P_OUI_TYPE_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_P2P_OUI_TYPE_8821C) & BIT_MASK_P2P_OUI_TYPE_8821C)\n#define BIT_SET_P2P_OUI_TYPE_8821C(x, v)                                       \\\n\t(BIT_CLEAR_P2P_OUI_TYPE_8821C(x) | BIT_P2P_OUI_TYPE_8821C(v))\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_ASSOCIATED_BFMER0_INFO_8821C (ASSOCIATED BEAMFORMER0 INFO REGISTER) */\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C 0xffffffffL\n#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x)                               \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C)                    \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C)\n#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8821C                                 \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C                            \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x)                         \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8821C))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x)                           \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C) &                \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x, v)                        \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x) |                      \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(v))\n\n/* 2 REG_ASSOCIATED_BFMER0_INFO_H_8821C */\n\n#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C 16\n#define BIT_MASK_R_WMAC_TXCSI_AID0_8821C 0x1ff\n#define BIT_R_WMAC_TXCSI_AID0_8821C(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8821C)                              \\\n\t << BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C)\n#define BITS_R_WMAC_TXCSI_AID0_8821C                                           \\\n\t(BIT_MASK_R_WMAC_TXCSI_AID0_8821C << BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C)\n#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8821C(x)                                   \\\n\t((x) & (~BITS_R_WMAC_TXCSI_AID0_8821C))\n#define BIT_GET_R_WMAC_TXCSI_AID0_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C) &                          \\\n\t BIT_MASK_R_WMAC_TXCSI_AID0_8821C)\n#define BIT_SET_R_WMAC_TXCSI_AID0_8821C(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_TXCSI_AID0_8821C(x) | BIT_R_WMAC_TXCSI_AID0_8821C(v))\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C 0xffff\n#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x)                             \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C)                  \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C)\n#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C                               \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C                          \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x)                       \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x)                         \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C) &              \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x, v)                      \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x) |                    \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(v))\n\n/* 2 REG_ASSOCIATED_BFMER1_INFO_8821C (ASSOCIATED BEAMFORMER1 INFO REGISTER) */\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C 0xffffffffL\n#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x)                               \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C)                    \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C)\n#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8821C                                 \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C                            \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x)                         \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8821C))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x)                           \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C) &                \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x, v)                        \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x) |                      \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(v))\n\n/* 2 REG_ASSOCIATED_BFMER1_INFO_H_8821C */\n\n#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C 16\n#define BIT_MASK_R_WMAC_TXCSI_AID1_8821C 0x1ff\n#define BIT_R_WMAC_TXCSI_AID1_8821C(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8821C)                              \\\n\t << BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C)\n#define BITS_R_WMAC_TXCSI_AID1_8821C                                           \\\n\t(BIT_MASK_R_WMAC_TXCSI_AID1_8821C << BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C)\n#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8821C(x)                                   \\\n\t((x) & (~BITS_R_WMAC_TXCSI_AID1_8821C))\n#define BIT_GET_R_WMAC_TXCSI_AID1_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C) &                          \\\n\t BIT_MASK_R_WMAC_TXCSI_AID1_8821C)\n#define BIT_SET_R_WMAC_TXCSI_AID1_8821C(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_TXCSI_AID1_8821C(x) | BIT_R_WMAC_TXCSI_AID1_8821C(v))\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C 0xffff\n#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x)                             \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C)                  \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C)\n#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C                               \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C                          \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x)                       \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x)                         \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C) &              \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x, v)                      \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x) |                    \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(v))\n\n/* 2 REG_TX_CSI_RPT_PARAM_BW20_8821C (TX CSI REPORT PARAMETER REGISTER) */\n\n#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C 16\n#define BIT_MASK_R_WMAC_BFINFO_20M_1_8821C 0xfff\n#define BIT_R_WMAC_BFINFO_20M_1_8821C(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8821C)                            \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C)\n#define BITS_R_WMAC_BFINFO_20M_1_8821C                                         \\\n\t(BIT_MASK_R_WMAC_BFINFO_20M_1_8821C                                    \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C)\n#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8821C(x)                                 \\\n\t((x) & (~BITS_R_WMAC_BFINFO_20M_1_8821C))\n#define BIT_GET_R_WMAC_BFINFO_20M_1_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C) &                        \\\n\t BIT_MASK_R_WMAC_BFINFO_20M_1_8821C)\n#define BIT_SET_R_WMAC_BFINFO_20M_1_8821C(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_BFINFO_20M_1_8821C(x) |                              \\\n\t BIT_R_WMAC_BFINFO_20M_1_8821C(v))\n\n#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C 0\n#define BIT_MASK_R_WMAC_BFINFO_20M_0_8821C 0xfff\n#define BIT_R_WMAC_BFINFO_20M_0_8821C(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8821C)                            \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C)\n#define BITS_R_WMAC_BFINFO_20M_0_8821C                                         \\\n\t(BIT_MASK_R_WMAC_BFINFO_20M_0_8821C                                    \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C)\n#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8821C(x)                                 \\\n\t((x) & (~BITS_R_WMAC_BFINFO_20M_0_8821C))\n#define BIT_GET_R_WMAC_BFINFO_20M_0_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) &                        \\\n\t BIT_MASK_R_WMAC_BFINFO_20M_0_8821C)\n#define BIT_SET_R_WMAC_BFINFO_20M_0_8821C(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_BFINFO_20M_0_8821C(x) |                              \\\n\t BIT_R_WMAC_BFINFO_20M_0_8821C(v))\n\n/* 2 REG_TX_CSI_RPT_PARAM_BW40_8821C (TX CSI REPORT PARAMETER_BW40 REGISTER) */\n\n#define BIT_SHIFT_WMAC_RESP_ANTCD_8821C 0\n#define BIT_MASK_WMAC_RESP_ANTCD_8821C 0xf\n#define BIT_WMAC_RESP_ANTCD_8821C(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_RESP_ANTCD_8821C)                                \\\n\t << BIT_SHIFT_WMAC_RESP_ANTCD_8821C)\n#define BITS_WMAC_RESP_ANTCD_8821C                                             \\\n\t(BIT_MASK_WMAC_RESP_ANTCD_8821C << BIT_SHIFT_WMAC_RESP_ANTCD_8821C)\n#define BIT_CLEAR_WMAC_RESP_ANTCD_8821C(x) ((x) & (~BITS_WMAC_RESP_ANTCD_8821C))\n#define BIT_GET_WMAC_RESP_ANTCD_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8821C) &                            \\\n\t BIT_MASK_WMAC_RESP_ANTCD_8821C)\n#define BIT_SET_WMAC_RESP_ANTCD_8821C(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_RESP_ANTCD_8821C(x) | BIT_WMAC_RESP_ANTCD_8821C(v))\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_BCN_PSR_RPT2_8821C (BEACON PARSER REPORT REGISTER2) */\n\n#define BIT_SHIFT_DTIM_CNT2_8821C 24\n#define BIT_MASK_DTIM_CNT2_8821C 0xff\n#define BIT_DTIM_CNT2_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT2_8821C) << BIT_SHIFT_DTIM_CNT2_8821C)\n#define BITS_DTIM_CNT2_8821C                                                   \\\n\t(BIT_MASK_DTIM_CNT2_8821C << BIT_SHIFT_DTIM_CNT2_8821C)\n#define BIT_CLEAR_DTIM_CNT2_8821C(x) ((x) & (~BITS_DTIM_CNT2_8821C))\n#define BIT_GET_DTIM_CNT2_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT2_8821C) & BIT_MASK_DTIM_CNT2_8821C)\n#define BIT_SET_DTIM_CNT2_8821C(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT2_8821C(x) | BIT_DTIM_CNT2_8821C(v))\n\n#define BIT_SHIFT_DTIM_PERIOD2_8821C 16\n#define BIT_MASK_DTIM_PERIOD2_8821C 0xff\n#define BIT_DTIM_PERIOD2_8821C(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD2_8821C) << BIT_SHIFT_DTIM_PERIOD2_8821C)\n#define BITS_DTIM_PERIOD2_8821C                                                \\\n\t(BIT_MASK_DTIM_PERIOD2_8821C << BIT_SHIFT_DTIM_PERIOD2_8821C)\n#define BIT_CLEAR_DTIM_PERIOD2_8821C(x) ((x) & (~BITS_DTIM_PERIOD2_8821C))\n#define BIT_GET_DTIM_PERIOD2_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD2_8821C) & BIT_MASK_DTIM_PERIOD2_8821C)\n#define BIT_SET_DTIM_PERIOD2_8821C(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD2_8821C(x) | BIT_DTIM_PERIOD2_8821C(v))\n\n#define BIT_DTIM2_8821C BIT(15)\n#define BIT_TIM2_8821C BIT(14)\n\n#define BIT_SHIFT_PS_AID_2_8821C 0\n#define BIT_MASK_PS_AID_2_8821C 0x7ff\n#define BIT_PS_AID_2_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_2_8821C) << BIT_SHIFT_PS_AID_2_8821C)\n#define BITS_PS_AID_2_8821C                                                    \\\n\t(BIT_MASK_PS_AID_2_8821C << BIT_SHIFT_PS_AID_2_8821C)\n#define BIT_CLEAR_PS_AID_2_8821C(x) ((x) & (~BITS_PS_AID_2_8821C))\n#define BIT_GET_PS_AID_2_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_2_8821C) & BIT_MASK_PS_AID_2_8821C)\n#define BIT_SET_PS_AID_2_8821C(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_2_8821C(x) | BIT_PS_AID_2_8821C(v))\n\n/* 2 REG_BCN_PSR_RPT3_8821C (BEACON PARSER REPORT REGISTER3) */\n\n#define BIT_SHIFT_DTIM_CNT3_8821C 24\n#define BIT_MASK_DTIM_CNT3_8821C 0xff\n#define BIT_DTIM_CNT3_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT3_8821C) << BIT_SHIFT_DTIM_CNT3_8821C)\n#define BITS_DTIM_CNT3_8821C                                                   \\\n\t(BIT_MASK_DTIM_CNT3_8821C << BIT_SHIFT_DTIM_CNT3_8821C)\n#define BIT_CLEAR_DTIM_CNT3_8821C(x) ((x) & (~BITS_DTIM_CNT3_8821C))\n#define BIT_GET_DTIM_CNT3_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT3_8821C) & BIT_MASK_DTIM_CNT3_8821C)\n#define BIT_SET_DTIM_CNT3_8821C(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT3_8821C(x) | BIT_DTIM_CNT3_8821C(v))\n\n#define BIT_SHIFT_DTIM_PERIOD3_8821C 16\n#define BIT_MASK_DTIM_PERIOD3_8821C 0xff\n#define BIT_DTIM_PERIOD3_8821C(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD3_8821C) << BIT_SHIFT_DTIM_PERIOD3_8821C)\n#define BITS_DTIM_PERIOD3_8821C                                                \\\n\t(BIT_MASK_DTIM_PERIOD3_8821C << BIT_SHIFT_DTIM_PERIOD3_8821C)\n#define BIT_CLEAR_DTIM_PERIOD3_8821C(x) ((x) & (~BITS_DTIM_PERIOD3_8821C))\n#define BIT_GET_DTIM_PERIOD3_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD3_8821C) & BIT_MASK_DTIM_PERIOD3_8821C)\n#define BIT_SET_DTIM_PERIOD3_8821C(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD3_8821C(x) | BIT_DTIM_PERIOD3_8821C(v))\n\n#define BIT_DTIM3_8821C BIT(15)\n#define BIT_TIM3_8821C BIT(14)\n\n#define BIT_SHIFT_PS_AID_3_8821C 0\n#define BIT_MASK_PS_AID_3_8821C 0x7ff\n#define BIT_PS_AID_3_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_3_8821C) << BIT_SHIFT_PS_AID_3_8821C)\n#define BITS_PS_AID_3_8821C                                                    \\\n\t(BIT_MASK_PS_AID_3_8821C << BIT_SHIFT_PS_AID_3_8821C)\n#define BIT_CLEAR_PS_AID_3_8821C(x) ((x) & (~BITS_PS_AID_3_8821C))\n#define BIT_GET_PS_AID_3_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_3_8821C) & BIT_MASK_PS_AID_3_8821C)\n#define BIT_SET_PS_AID_3_8821C(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_3_8821C(x) | BIT_PS_AID_3_8821C(v))\n\n/* 2 REG_BCN_PSR_RPT4_8821C (BEACON PARSER REPORT REGISTER4) */\n\n#define BIT_SHIFT_DTIM_CNT4_8821C 24\n#define BIT_MASK_DTIM_CNT4_8821C 0xff\n#define BIT_DTIM_CNT4_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT4_8821C) << BIT_SHIFT_DTIM_CNT4_8821C)\n#define BITS_DTIM_CNT4_8821C                                                   \\\n\t(BIT_MASK_DTIM_CNT4_8821C << BIT_SHIFT_DTIM_CNT4_8821C)\n#define BIT_CLEAR_DTIM_CNT4_8821C(x) ((x) & (~BITS_DTIM_CNT4_8821C))\n#define BIT_GET_DTIM_CNT4_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT4_8821C) & BIT_MASK_DTIM_CNT4_8821C)\n#define BIT_SET_DTIM_CNT4_8821C(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT4_8821C(x) | BIT_DTIM_CNT4_8821C(v))\n\n#define BIT_SHIFT_DTIM_PERIOD4_8821C 16\n#define BIT_MASK_DTIM_PERIOD4_8821C 0xff\n#define BIT_DTIM_PERIOD4_8821C(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD4_8821C) << BIT_SHIFT_DTIM_PERIOD4_8821C)\n#define BITS_DTIM_PERIOD4_8821C                                                \\\n\t(BIT_MASK_DTIM_PERIOD4_8821C << BIT_SHIFT_DTIM_PERIOD4_8821C)\n#define BIT_CLEAR_DTIM_PERIOD4_8821C(x) ((x) & (~BITS_DTIM_PERIOD4_8821C))\n#define BIT_GET_DTIM_PERIOD4_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD4_8821C) & BIT_MASK_DTIM_PERIOD4_8821C)\n#define BIT_SET_DTIM_PERIOD4_8821C(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD4_8821C(x) | BIT_DTIM_PERIOD4_8821C(v))\n\n#define BIT_DTIM4_8821C BIT(15)\n#define BIT_TIM4_8821C BIT(14)\n\n#define BIT_SHIFT_PS_AID_4_8821C 0\n#define BIT_MASK_PS_AID_4_8821C 0x7ff\n#define BIT_PS_AID_4_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_4_8821C) << BIT_SHIFT_PS_AID_4_8821C)\n#define BITS_PS_AID_4_8821C                                                    \\\n\t(BIT_MASK_PS_AID_4_8821C << BIT_SHIFT_PS_AID_4_8821C)\n#define BIT_CLEAR_PS_AID_4_8821C(x) ((x) & (~BITS_PS_AID_4_8821C))\n#define BIT_GET_PS_AID_4_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_4_8821C) & BIT_MASK_PS_AID_4_8821C)\n#define BIT_SET_PS_AID_4_8821C(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_4_8821C(x) | BIT_PS_AID_4_8821C(v))\n\n/* 2 REG_A1_ADDR_MASK_8821C (A1 ADDR MASK REGISTER) */\n\n#define BIT_SHIFT_A1_ADDR_MASK_8821C 0\n#define BIT_MASK_A1_ADDR_MASK_8821C 0xffffffffL\n#define BIT_A1_ADDR_MASK_8821C(x)                                              \\\n\t(((x) & BIT_MASK_A1_ADDR_MASK_8821C) << BIT_SHIFT_A1_ADDR_MASK_8821C)\n#define BITS_A1_ADDR_MASK_8821C                                                \\\n\t(BIT_MASK_A1_ADDR_MASK_8821C << BIT_SHIFT_A1_ADDR_MASK_8821C)\n#define BIT_CLEAR_A1_ADDR_MASK_8821C(x) ((x) & (~BITS_A1_ADDR_MASK_8821C))\n#define BIT_GET_A1_ADDR_MASK_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_A1_ADDR_MASK_8821C) & BIT_MASK_A1_ADDR_MASK_8821C)\n#define BIT_SET_A1_ADDR_MASK_8821C(x, v)                                       \\\n\t(BIT_CLEAR_A1_ADDR_MASK_8821C(x) | BIT_A1_ADDR_MASK_8821C(v))\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_MACID2_8821C (MAC ID2 REGISTER) */\n\n#define BIT_SHIFT_MACID2_V1_8821C 0\n#define BIT_MASK_MACID2_V1_8821C 0xffffffffL\n#define BIT_MACID2_V1_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_MACID2_V1_8821C) << BIT_SHIFT_MACID2_V1_8821C)\n#define BITS_MACID2_V1_8821C                                                   \\\n\t(BIT_MASK_MACID2_V1_8821C << BIT_SHIFT_MACID2_V1_8821C)\n#define BIT_CLEAR_MACID2_V1_8821C(x) ((x) & (~BITS_MACID2_V1_8821C))\n#define BIT_GET_MACID2_V1_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MACID2_V1_8821C) & BIT_MASK_MACID2_V1_8821C)\n#define BIT_SET_MACID2_V1_8821C(x, v)                                          \\\n\t(BIT_CLEAR_MACID2_V1_8821C(x) | BIT_MACID2_V1_8821C(v))\n\n/* 2 REG_MACID2_H_8821C (MAC ID2 REGISTER) */\n\n#define BIT_SHIFT_MACID2_H_V1_8821C 0\n#define BIT_MASK_MACID2_H_V1_8821C 0xffff\n#define BIT_MACID2_H_V1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_MACID2_H_V1_8821C) << BIT_SHIFT_MACID2_H_V1_8821C)\n#define BITS_MACID2_H_V1_8821C                                                 \\\n\t(BIT_MASK_MACID2_H_V1_8821C << BIT_SHIFT_MACID2_H_V1_8821C)\n#define BIT_CLEAR_MACID2_H_V1_8821C(x) ((x) & (~BITS_MACID2_H_V1_8821C))\n#define BIT_GET_MACID2_H_V1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_MACID2_H_V1_8821C) & BIT_MASK_MACID2_H_V1_8821C)\n#define BIT_SET_MACID2_H_V1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_MACID2_H_V1_8821C(x) | BIT_MACID2_H_V1_8821C(v))\n\n/* 2 REG_BSSID2_8821C (BSSID2 REGISTER) */\n\n#define BIT_SHIFT_BSSID2_V1_8821C 0\n#define BIT_MASK_BSSID2_V1_8821C 0xffffffffL\n#define BIT_BSSID2_V1_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_BSSID2_V1_8821C) << BIT_SHIFT_BSSID2_V1_8821C)\n#define BITS_BSSID2_V1_8821C                                                   \\\n\t(BIT_MASK_BSSID2_V1_8821C << BIT_SHIFT_BSSID2_V1_8821C)\n#define BIT_CLEAR_BSSID2_V1_8821C(x) ((x) & (~BITS_BSSID2_V1_8821C))\n#define BIT_GET_BSSID2_V1_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_BSSID2_V1_8821C) & BIT_MASK_BSSID2_V1_8821C)\n#define BIT_SET_BSSID2_V1_8821C(x, v)                                          \\\n\t(BIT_CLEAR_BSSID2_V1_8821C(x) | BIT_BSSID2_V1_8821C(v))\n\n/* 2 REG_BSSID2_H_8821C (BSSID2 REGISTER) */\n\n#define BIT_SHIFT_BSSID2_H_V1_8821C 0\n#define BIT_MASK_BSSID2_H_V1_8821C 0xffff\n#define BIT_BSSID2_H_V1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_BSSID2_H_V1_8821C) << BIT_SHIFT_BSSID2_H_V1_8821C)\n#define BITS_BSSID2_H_V1_8821C                                                 \\\n\t(BIT_MASK_BSSID2_H_V1_8821C << BIT_SHIFT_BSSID2_H_V1_8821C)\n#define BIT_CLEAR_BSSID2_H_V1_8821C(x) ((x) & (~BITS_BSSID2_H_V1_8821C))\n#define BIT_GET_BSSID2_H_V1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_BSSID2_H_V1_8821C) & BIT_MASK_BSSID2_H_V1_8821C)\n#define BIT_SET_BSSID2_H_V1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_BSSID2_H_V1_8821C(x) | BIT_BSSID2_H_V1_8821C(v))\n\n/* 2 REG_MACID3_8821C (MAC ID3 REGISTER) */\n\n#define BIT_SHIFT_MACID3_V1_8821C 0\n#define BIT_MASK_MACID3_V1_8821C 0xffffffffL\n#define BIT_MACID3_V1_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_MACID3_V1_8821C) << BIT_SHIFT_MACID3_V1_8821C)\n#define BITS_MACID3_V1_8821C                                                   \\\n\t(BIT_MASK_MACID3_V1_8821C << BIT_SHIFT_MACID3_V1_8821C)\n#define BIT_CLEAR_MACID3_V1_8821C(x) ((x) & (~BITS_MACID3_V1_8821C))\n#define BIT_GET_MACID3_V1_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MACID3_V1_8821C) & BIT_MASK_MACID3_V1_8821C)\n#define BIT_SET_MACID3_V1_8821C(x, v)                                          \\\n\t(BIT_CLEAR_MACID3_V1_8821C(x) | BIT_MACID3_V1_8821C(v))\n\n/* 2 REG_MACID3_H_8821C (MAC ID3 REGISTER) */\n\n#define BIT_SHIFT_MACID3_H_V1_8821C 0\n#define BIT_MASK_MACID3_H_V1_8821C 0xffff\n#define BIT_MACID3_H_V1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_MACID3_H_V1_8821C) << BIT_SHIFT_MACID3_H_V1_8821C)\n#define BITS_MACID3_H_V1_8821C                                                 \\\n\t(BIT_MASK_MACID3_H_V1_8821C << BIT_SHIFT_MACID3_H_V1_8821C)\n#define BIT_CLEAR_MACID3_H_V1_8821C(x) ((x) & (~BITS_MACID3_H_V1_8821C))\n#define BIT_GET_MACID3_H_V1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_MACID3_H_V1_8821C) & BIT_MASK_MACID3_H_V1_8821C)\n#define BIT_SET_MACID3_H_V1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_MACID3_H_V1_8821C(x) | BIT_MACID3_H_V1_8821C(v))\n\n/* 2 REG_BSSID3_8821C (BSSID3 REGISTER) */\n\n#define BIT_SHIFT_BSSID3_V1_8821C 0\n#define BIT_MASK_BSSID3_V1_8821C 0xffffffffL\n#define BIT_BSSID3_V1_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_BSSID3_V1_8821C) << BIT_SHIFT_BSSID3_V1_8821C)\n#define BITS_BSSID3_V1_8821C                                                   \\\n\t(BIT_MASK_BSSID3_V1_8821C << BIT_SHIFT_BSSID3_V1_8821C)\n#define BIT_CLEAR_BSSID3_V1_8821C(x) ((x) & (~BITS_BSSID3_V1_8821C))\n#define BIT_GET_BSSID3_V1_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_BSSID3_V1_8821C) & BIT_MASK_BSSID3_V1_8821C)\n#define BIT_SET_BSSID3_V1_8821C(x, v)                                          \\\n\t(BIT_CLEAR_BSSID3_V1_8821C(x) | BIT_BSSID3_V1_8821C(v))\n\n/* 2 REG_BSSID3_H_8821C (BSSID3 REGISTER) */\n\n#define BIT_SHIFT_BSSID3_H_V1_8821C 0\n#define BIT_MASK_BSSID3_H_V1_8821C 0xffff\n#define BIT_BSSID3_H_V1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_BSSID3_H_V1_8821C) << BIT_SHIFT_BSSID3_H_V1_8821C)\n#define BITS_BSSID3_H_V1_8821C                                                 \\\n\t(BIT_MASK_BSSID3_H_V1_8821C << BIT_SHIFT_BSSID3_H_V1_8821C)\n#define BIT_CLEAR_BSSID3_H_V1_8821C(x) ((x) & (~BITS_BSSID3_H_V1_8821C))\n#define BIT_GET_BSSID3_H_V1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_BSSID3_H_V1_8821C) & BIT_MASK_BSSID3_H_V1_8821C)\n#define BIT_SET_BSSID3_H_V1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_BSSID3_H_V1_8821C(x) | BIT_BSSID3_H_V1_8821C(v))\n\n/* 2 REG_MACID4_8821C (MAC ID4 REGISTER) */\n\n#define BIT_SHIFT_MACID4_V1_8821C 0\n#define BIT_MASK_MACID4_V1_8821C 0xffffffffL\n#define BIT_MACID4_V1_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_MACID4_V1_8821C) << BIT_SHIFT_MACID4_V1_8821C)\n#define BITS_MACID4_V1_8821C                                                   \\\n\t(BIT_MASK_MACID4_V1_8821C << BIT_SHIFT_MACID4_V1_8821C)\n#define BIT_CLEAR_MACID4_V1_8821C(x) ((x) & (~BITS_MACID4_V1_8821C))\n#define BIT_GET_MACID4_V1_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MACID4_V1_8821C) & BIT_MASK_MACID4_V1_8821C)\n#define BIT_SET_MACID4_V1_8821C(x, v)                                          \\\n\t(BIT_CLEAR_MACID4_V1_8821C(x) | BIT_MACID4_V1_8821C(v))\n\n/* 2 REG_MACID4_H_8821C (MAC ID4 REGISTER) */\n\n#define BIT_SHIFT_MACID4_H_V1_8821C 0\n#define BIT_MASK_MACID4_H_V1_8821C 0xffff\n#define BIT_MACID4_H_V1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_MACID4_H_V1_8821C) << BIT_SHIFT_MACID4_H_V1_8821C)\n#define BITS_MACID4_H_V1_8821C                                                 \\\n\t(BIT_MASK_MACID4_H_V1_8821C << BIT_SHIFT_MACID4_H_V1_8821C)\n#define BIT_CLEAR_MACID4_H_V1_8821C(x) ((x) & (~BITS_MACID4_H_V1_8821C))\n#define BIT_GET_MACID4_H_V1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_MACID4_H_V1_8821C) & BIT_MASK_MACID4_H_V1_8821C)\n#define BIT_SET_MACID4_H_V1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_MACID4_H_V1_8821C(x) | BIT_MACID4_H_V1_8821C(v))\n\n/* 2 REG_BSSID4_8821C (BSSID4 REGISTER) */\n\n#define BIT_SHIFT_BSSID4_V1_8821C 0\n#define BIT_MASK_BSSID4_V1_8821C 0xffffffffL\n#define BIT_BSSID4_V1_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_BSSID4_V1_8821C) << BIT_SHIFT_BSSID4_V1_8821C)\n#define BITS_BSSID4_V1_8821C                                                   \\\n\t(BIT_MASK_BSSID4_V1_8821C << BIT_SHIFT_BSSID4_V1_8821C)\n#define BIT_CLEAR_BSSID4_V1_8821C(x) ((x) & (~BITS_BSSID4_V1_8821C))\n#define BIT_GET_BSSID4_V1_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_BSSID4_V1_8821C) & BIT_MASK_BSSID4_V1_8821C)\n#define BIT_SET_BSSID4_V1_8821C(x, v)                                          \\\n\t(BIT_CLEAR_BSSID4_V1_8821C(x) | BIT_BSSID4_V1_8821C(v))\n\n/* 2 REG_BSSID4_H_8821C (BSSID4 REGISTER) */\n\n#define BIT_SHIFT_BSSID4_H_V1_8821C 0\n#define BIT_MASK_BSSID4_H_V1_8821C 0xffff\n#define BIT_BSSID4_H_V1_8821C(x)                                               \\\n\t(((x) & BIT_MASK_BSSID4_H_V1_8821C) << BIT_SHIFT_BSSID4_H_V1_8821C)\n#define BITS_BSSID4_H_V1_8821C                                                 \\\n\t(BIT_MASK_BSSID4_H_V1_8821C << BIT_SHIFT_BSSID4_H_V1_8821C)\n#define BIT_CLEAR_BSSID4_H_V1_8821C(x) ((x) & (~BITS_BSSID4_H_V1_8821C))\n#define BIT_GET_BSSID4_H_V1_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_BSSID4_H_V1_8821C) & BIT_MASK_BSSID4_H_V1_8821C)\n#define BIT_SET_BSSID4_H_V1_8821C(x, v)                                        \\\n\t(BIT_CLEAR_BSSID4_H_V1_8821C(x) | BIT_BSSID4_H_V1_8821C(v))\n\n/* 2 REG_NOA_REPORT_8821C */\n\n/* 2 REG_NOA_REPORT_1_8821C */\n\n/* 2 REG_NOA_REPORT_2_8821C */\n\n/* 2 REG_NOA_REPORT_3_8821C */\n\n/* 2 REG_PWRBIT_SETTING_8821C */\n#define BIT_CLI3_PWRBIT_OW_EN_8821C BIT(7)\n#define BIT_CLI3_PWR_ST_8821C BIT(6)\n#define BIT_CLI2_PWRBIT_OW_EN_8821C BIT(5)\n#define BIT_CLI2_PWR_ST_8821C BIT(4)\n#define BIT_CLI1_PWRBIT_OW_EN_8821C BIT(3)\n#define BIT_CLI1_PWR_ST_8821C BIT(2)\n#define BIT_CLI0_PWRBIT_OW_EN_8821C BIT(1)\n#define BIT_CLI0_PWR_ST_8821C BIT(0)\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_MU_BF_OPTION_8821C */\n#define BIT_WMAC_RESP_NONSTA1_DIS_8821C BIT(7)\n#define BIT_WMAC_TXMU_ACKPOLICY_EN_8821C BIT(6)\n\n#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C 4\n#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C 0x3\n#define BIT_WMAC_TXMU_ACKPOLICY_8821C(x)                                       \\\n\t(((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C)                            \\\n\t << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C)\n#define BITS_WMAC_TXMU_ACKPOLICY_8821C                                         \\\n\t(BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C                                    \\\n\t << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C)\n#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8821C(x)                                 \\\n\t((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8821C))\n#define BIT_GET_WMAC_TXMU_ACKPOLICY_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C) &                        \\\n\t BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C)\n#define BIT_SET_WMAC_TXMU_ACKPOLICY_8821C(x, v)                                \\\n\t(BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8821C(x) |                              \\\n\t BIT_WMAC_TXMU_ACKPOLICY_8821C(v))\n\n#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C 1\n#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C 0x7\n#define BIT_WMAC_MU_BFEE_PORT_SEL_8821C(x)                                     \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C)                          \\\n\t << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C)\n#define BITS_WMAC_MU_BFEE_PORT_SEL_8821C                                       \\\n\t(BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C                                  \\\n\t << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C)\n#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8821C(x)                               \\\n\t((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8821C))\n#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8821C(x)                                 \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C) &                      \\\n\t BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C)\n#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8821C(x, v)                              \\\n\t(BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8821C(x) |                            \\\n\t BIT_WMAC_MU_BFEE_PORT_SEL_8821C(v))\n\n#define BIT_WMAC_MU_BFEE_DIS_8821C BIT(0)\n\n/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8821C */\n\n#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C 0\n#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C 0xff\n#define BIT_WMAC_PAUSE_BB_CLR_TH_8821C(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C)                           \\\n\t << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C)\n#define BITS_WMAC_PAUSE_BB_CLR_TH_8821C                                        \\\n\t(BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C                                   \\\n\t << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C)\n#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8821C(x)                                \\\n\t((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8821C))\n#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C) &                       \\\n\t BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C)\n#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8821C(x, v)                               \\\n\t(BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8821C(x) |                             \\\n\t BIT_WMAC_PAUSE_BB_CLR_TH_8821C(v))\n\n/* 2 REG_WMAC_MU_ARB_8821C */\n#define BIT_WMAC_ARB_HW_ADAPT_EN_8821C BIT(7)\n#define BIT_WMAC_ARB_SW_EN_8821C BIT(6)\n\n#define BIT_SHIFT_WMAC_ARB_SW_STATE_8821C 0\n#define BIT_MASK_WMAC_ARB_SW_STATE_8821C 0x3f\n#define BIT_WMAC_ARB_SW_STATE_8821C(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_ARB_SW_STATE_8821C)                              \\\n\t << BIT_SHIFT_WMAC_ARB_SW_STATE_8821C)\n#define BITS_WMAC_ARB_SW_STATE_8821C                                           \\\n\t(BIT_MASK_WMAC_ARB_SW_STATE_8821C << BIT_SHIFT_WMAC_ARB_SW_STATE_8821C)\n#define BIT_CLEAR_WMAC_ARB_SW_STATE_8821C(x)                                   \\\n\t((x) & (~BITS_WMAC_ARB_SW_STATE_8821C))\n#define BIT_GET_WMAC_ARB_SW_STATE_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8821C) &                          \\\n\t BIT_MASK_WMAC_ARB_SW_STATE_8821C)\n#define BIT_SET_WMAC_ARB_SW_STATE_8821C(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_ARB_SW_STATE_8821C(x) | BIT_WMAC_ARB_SW_STATE_8821C(v))\n\n/* 2 REG_WMAC_MU_OPTION_8821C */\n\n#define BIT_SHIFT_WMAC_MU_DBGSEL_8821C 5\n#define BIT_MASK_WMAC_MU_DBGSEL_8821C 0x3\n#define BIT_WMAC_MU_DBGSEL_8821C(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_MU_DBGSEL_8821C)                                 \\\n\t << BIT_SHIFT_WMAC_MU_DBGSEL_8821C)\n#define BITS_WMAC_MU_DBGSEL_8821C                                              \\\n\t(BIT_MASK_WMAC_MU_DBGSEL_8821C << BIT_SHIFT_WMAC_MU_DBGSEL_8821C)\n#define BIT_CLEAR_WMAC_MU_DBGSEL_8821C(x) ((x) & (~BITS_WMAC_MU_DBGSEL_8821C))\n#define BIT_GET_WMAC_MU_DBGSEL_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8821C) &                             \\\n\t BIT_MASK_WMAC_MU_DBGSEL_8821C)\n#define BIT_SET_WMAC_MU_DBGSEL_8821C(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_MU_DBGSEL_8821C(x) | BIT_WMAC_MU_DBGSEL_8821C(v))\n\n#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C 0\n#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C 0x1f\n#define BIT_WMAC_MU_CPRD_TIMEOUT_8821C(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C)                           \\\n\t << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C)\n#define BITS_WMAC_MU_CPRD_TIMEOUT_8821C                                        \\\n\t(BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C                                   \\\n\t << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C)\n#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8821C(x)                                \\\n\t((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8821C))\n#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C) &                       \\\n\t BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C)\n#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8821C(x, v)                               \\\n\t(BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8821C(x) |                             \\\n\t BIT_WMAC_MU_CPRD_TIMEOUT_8821C(v))\n\n/* 2 REG_WMAC_MU_BF_CTL_8821C */\n#define BIT_WMAC_INVLD_BFPRT_CHK_8821C BIT(15)\n#define BIT_WMAC_RETXBFRPTSEQ_UPD_8821C BIT(14)\n\n#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C 12\n#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C 0x3\n#define BIT_WMAC_MU_BFRPTSEG_SEL_8821C(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C)                           \\\n\t << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C)\n#define BITS_WMAC_MU_BFRPTSEG_SEL_8821C                                        \\\n\t(BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C                                   \\\n\t << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C)\n#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8821C(x)                                \\\n\t((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8821C))\n#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) &                       \\\n\t BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C)\n#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8821C(x, v)                               \\\n\t(BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8821C(x) |                             \\\n\t BIT_WMAC_MU_BFRPTSEG_SEL_8821C(v))\n\n#define BIT_SHIFT_WMAC_MU_BF_MYAID_8821C 0\n#define BIT_MASK_WMAC_MU_BF_MYAID_8821C 0xfff\n#define BIT_WMAC_MU_BF_MYAID_8821C(x)                                          \\\n\t(((x) & BIT_MASK_WMAC_MU_BF_MYAID_8821C)                               \\\n\t << BIT_SHIFT_WMAC_MU_BF_MYAID_8821C)\n#define BITS_WMAC_MU_BF_MYAID_8821C                                            \\\n\t(BIT_MASK_WMAC_MU_BF_MYAID_8821C << BIT_SHIFT_WMAC_MU_BF_MYAID_8821C)\n#define BIT_CLEAR_WMAC_MU_BF_MYAID_8821C(x)                                    \\\n\t((x) & (~BITS_WMAC_MU_BF_MYAID_8821C))\n#define BIT_GET_WMAC_MU_BF_MYAID_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) &                           \\\n\t BIT_MASK_WMAC_MU_BF_MYAID_8821C)\n#define BIT_SET_WMAC_MU_BF_MYAID_8821C(x, v)                                   \\\n\t(BIT_CLEAR_WMAC_MU_BF_MYAID_8821C(x) | BIT_WMAC_MU_BF_MYAID_8821C(v))\n\n/* 2 REG_WMAC_MU_BFRPT_PARA_8821C */\n\n#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C 12\n#define BIT_MASK_BFRPT_PARA_USERID_SEL_8821C 0x7\n#define BIT_BFRPT_PARA_USERID_SEL_8821C(x)                                     \\\n\t(((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8821C)                          \\\n\t << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C)\n#define BITS_BFRPT_PARA_USERID_SEL_8821C                                       \\\n\t(BIT_MASK_BFRPT_PARA_USERID_SEL_8821C                                  \\\n\t << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C)\n#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_8821C(x)                               \\\n\t((x) & (~BITS_BFRPT_PARA_USERID_SEL_8821C))\n#define BIT_GET_BFRPT_PARA_USERID_SEL_8821C(x)                                 \\\n\t(((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C) &                      \\\n\t BIT_MASK_BFRPT_PARA_USERID_SEL_8821C)\n#define BIT_SET_BFRPT_PARA_USERID_SEL_8821C(x, v)                              \\\n\t(BIT_CLEAR_BFRPT_PARA_USERID_SEL_8821C(x) |                            \\\n\t BIT_BFRPT_PARA_USERID_SEL_8821C(v))\n\n#define BIT_SHIFT_BFRPT_PARA_8821C 0\n#define BIT_MASK_BFRPT_PARA_8821C 0xfff\n#define BIT_BFRPT_PARA_8821C(x)                                                \\\n\t(((x) & BIT_MASK_BFRPT_PARA_8821C) << BIT_SHIFT_BFRPT_PARA_8821C)\n#define BITS_BFRPT_PARA_8821C                                                  \\\n\t(BIT_MASK_BFRPT_PARA_8821C << BIT_SHIFT_BFRPT_PARA_8821C)\n#define BIT_CLEAR_BFRPT_PARA_8821C(x) ((x) & (~BITS_BFRPT_PARA_8821C))\n#define BIT_GET_BFRPT_PARA_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BFRPT_PARA_8821C) & BIT_MASK_BFRPT_PARA_8821C)\n#define BIT_SET_BFRPT_PARA_8821C(x, v)                                         \\\n\t(BIT_CLEAR_BFRPT_PARA_8821C(x) | BIT_BFRPT_PARA_8821C(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8821C */\n#define BIT_STATUS_BFEE2_8821C BIT(10)\n#define BIT_WMAC_MU_BFEE2_EN_8821C BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C 0\n#define BIT_MASK_WMAC_MU_BFEE2_AID_8821C 0x1ff\n#define BIT_WMAC_MU_BFEE2_AID_8821C(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8821C)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C)\n#define BITS_WMAC_MU_BFEE2_AID_8821C                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE2_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C)\n#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8821C(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE2_AID_8821C))\n#define BIT_GET_WMAC_MU_BFEE2_AID_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE2_AID_8821C)\n#define BIT_SET_WMAC_MU_BFEE2_AID_8821C(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE2_AID_8821C(x) | BIT_WMAC_MU_BFEE2_AID_8821C(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8821C */\n#define BIT_STATUS_BFEE3_8821C BIT(10)\n#define BIT_WMAC_MU_BFEE3_EN_8821C BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C 0\n#define BIT_MASK_WMAC_MU_BFEE3_AID_8821C 0x1ff\n#define BIT_WMAC_MU_BFEE3_AID_8821C(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8821C)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C)\n#define BITS_WMAC_MU_BFEE3_AID_8821C                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE3_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C)\n#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8821C(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE3_AID_8821C))\n#define BIT_GET_WMAC_MU_BFEE3_AID_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE3_AID_8821C)\n#define BIT_SET_WMAC_MU_BFEE3_AID_8821C(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE3_AID_8821C(x) | BIT_WMAC_MU_BFEE3_AID_8821C(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8821C */\n#define BIT_STATUS_BFEE4_8821C BIT(10)\n#define BIT_WMAC_MU_BFEE4_EN_8821C BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C 0\n#define BIT_MASK_WMAC_MU_BFEE4_AID_8821C 0x1ff\n#define BIT_WMAC_MU_BFEE4_AID_8821C(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8821C)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C)\n#define BITS_WMAC_MU_BFEE4_AID_8821C                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE4_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C)\n#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8821C(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE4_AID_8821C))\n#define BIT_GET_WMAC_MU_BFEE4_AID_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE4_AID_8821C)\n#define BIT_SET_WMAC_MU_BFEE4_AID_8821C(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE4_AID_8821C(x) | BIT_WMAC_MU_BFEE4_AID_8821C(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8821C */\n#define BIT_BIT_STATUS_BFEE5_8821C BIT(10)\n#define BIT_WMAC_MU_BFEE5_EN_8821C BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C 0\n#define BIT_MASK_WMAC_MU_BFEE5_AID_8821C 0x1ff\n#define BIT_WMAC_MU_BFEE5_AID_8821C(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8821C)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C)\n#define BITS_WMAC_MU_BFEE5_AID_8821C                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE5_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C)\n#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8821C(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE5_AID_8821C))\n#define BIT_GET_WMAC_MU_BFEE5_AID_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE5_AID_8821C)\n#define BIT_SET_WMAC_MU_BFEE5_AID_8821C(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE5_AID_8821C(x) | BIT_WMAC_MU_BFEE5_AID_8821C(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8821C */\n#define BIT_STATUS_BFEE6_8821C BIT(10)\n#define BIT_WMAC_MU_BFEE6_EN_8821C BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C 0\n#define BIT_MASK_WMAC_MU_BFEE6_AID_8821C 0x1ff\n#define BIT_WMAC_MU_BFEE6_AID_8821C(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8821C)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C)\n#define BITS_WMAC_MU_BFEE6_AID_8821C                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE6_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C)\n#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8821C(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE6_AID_8821C))\n#define BIT_GET_WMAC_MU_BFEE6_AID_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE6_AID_8821C)\n#define BIT_SET_WMAC_MU_BFEE6_AID_8821C(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE6_AID_8821C(x) | BIT_WMAC_MU_BFEE6_AID_8821C(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8821C */\n#define BIT_STATUS_BFEE7_8821C BIT(10)\n#define BIT_WMAC_MU_BFEE7_EN_8821C BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C 0\n#define BIT_MASK_WMAC_MU_BFEE7_AID_8821C 0x1ff\n#define BIT_WMAC_MU_BFEE7_AID_8821C(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8821C)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C)\n#define BITS_WMAC_MU_BFEE7_AID_8821C                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE7_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C)\n#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8821C(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE7_AID_8821C))\n#define BIT_GET_WMAC_MU_BFEE7_AID_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE7_AID_8821C)\n#define BIT_SET_WMAC_MU_BFEE7_AID_8821C(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE7_AID_8821C(x) | BIT_WMAC_MU_BFEE7_AID_8821C(v))\n\n/* 2 REG_WMAC_BB_STOP_RX_COUNTER_8821C */\n#define BIT_RST_ALL_COUNTER_8821C BIT(31)\n\n#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C 16\n#define BIT_MASK_ABORT_RX_VBON_COUNTER_8821C 0xff\n#define BIT_ABORT_RX_VBON_COUNTER_8821C(x)                                     \\\n\t(((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8821C)                          \\\n\t << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C)\n#define BITS_ABORT_RX_VBON_COUNTER_8821C                                       \\\n\t(BIT_MASK_ABORT_RX_VBON_COUNTER_8821C                                  \\\n\t << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C)\n#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8821C(x)                               \\\n\t((x) & (~BITS_ABORT_RX_VBON_COUNTER_8821C))\n#define BIT_GET_ABORT_RX_VBON_COUNTER_8821C(x)                                 \\\n\t(((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C) &                      \\\n\t BIT_MASK_ABORT_RX_VBON_COUNTER_8821C)\n#define BIT_SET_ABORT_RX_VBON_COUNTER_8821C(x, v)                              \\\n\t(BIT_CLEAR_ABORT_RX_VBON_COUNTER_8821C(x) |                            \\\n\t BIT_ABORT_RX_VBON_COUNTER_8821C(v))\n\n#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C 8\n#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C 0xff\n#define BIT_ABORT_RX_RDRDY_COUNTER_8821C(x)                                    \\\n\t(((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C)                         \\\n\t << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C)\n#define BITS_ABORT_RX_RDRDY_COUNTER_8821C                                      \\\n\t(BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C                                 \\\n\t << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C)\n#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8821C(x)                              \\\n\t((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8821C))\n#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8821C(x)                                \\\n\t(((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C) &                     \\\n\t BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C)\n#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8821C(x, v)                             \\\n\t(BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8821C(x) |                           \\\n\t BIT_ABORT_RX_RDRDY_COUNTER_8821C(v))\n\n#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C 0\n#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C 0xff\n#define BIT_VBON_EARLY_FALLING_COUNTER_8821C(x)                                \\\n\t(((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C)                     \\\n\t << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C)\n#define BITS_VBON_EARLY_FALLING_COUNTER_8821C                                  \\\n\t(BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C                             \\\n\t << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C)\n#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8821C(x)                          \\\n\t((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8821C))\n#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8821C(x)                            \\\n\t(((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C) &                 \\\n\t BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C)\n#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8821C(x, v)                         \\\n\t(BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8821C(x) |                       \\\n\t BIT_VBON_EARLY_FALLING_COUNTER_8821C(v))\n\n/* 2 REG_WMAC_PLCP_MONITOR_8821C */\n#define BIT_WMAC_PLCP_TRX_SEL_8821C BIT(31)\n\n#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C 28\n#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C 0x7\n#define BIT_WMAC_PLCP_RDSIG_SEL_8821C(x)                                       \\\n\t(((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C)                            \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C)\n#define BITS_WMAC_PLCP_RDSIG_SEL_8821C                                         \\\n\t(BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C                                    \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C)\n#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8821C(x)                                 \\\n\t((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8821C))\n#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C) &                        \\\n\t BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C)\n#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8821C(x, v)                                \\\n\t(BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8821C(x) |                              \\\n\t BIT_WMAC_PLCP_RDSIG_SEL_8821C(v))\n\n#define BIT_SHIFT_WMAC_RATE_IDX_8821C 24\n#define BIT_MASK_WMAC_RATE_IDX_8821C 0xf\n#define BIT_WMAC_RATE_IDX_8821C(x)                                             \\\n\t(((x) & BIT_MASK_WMAC_RATE_IDX_8821C) << BIT_SHIFT_WMAC_RATE_IDX_8821C)\n#define BITS_WMAC_RATE_IDX_8821C                                               \\\n\t(BIT_MASK_WMAC_RATE_IDX_8821C << BIT_SHIFT_WMAC_RATE_IDX_8821C)\n#define BIT_CLEAR_WMAC_RATE_IDX_8821C(x) ((x) & (~BITS_WMAC_RATE_IDX_8821C))\n#define BIT_GET_WMAC_RATE_IDX_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_WMAC_RATE_IDX_8821C) & BIT_MASK_WMAC_RATE_IDX_8821C)\n#define BIT_SET_WMAC_RATE_IDX_8821C(x, v)                                      \\\n\t(BIT_CLEAR_WMAC_RATE_IDX_8821C(x) | BIT_WMAC_RATE_IDX_8821C(v))\n\n#define BIT_SHIFT_WMAC_PLCP_RDSIG_8821C 0\n#define BIT_MASK_WMAC_PLCP_RDSIG_8821C 0xffffff\n#define BIT_WMAC_PLCP_RDSIG_8821C(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C)                                \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C)\n#define BITS_WMAC_PLCP_RDSIG_8821C                                             \\\n\t(BIT_MASK_WMAC_PLCP_RDSIG_8821C << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C)\n#define BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8821C))\n#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) &                            \\\n\t BIT_MASK_WMAC_PLCP_RDSIG_8821C)\n#define BIT_SET_WMAC_PLCP_RDSIG_8821C(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) | BIT_WMAC_PLCP_RDSIG_8821C(v))\n\n/* 2 REG_WMAC_PLCP_MONITOR_MUTX_8821C */\n#define BIT_WMAC_MUTX_IDX_8821C BIT(24)\n\n#define BIT_SHIFT_WMAC_PLCP_RDSIG_8821C 0\n#define BIT_MASK_WMAC_PLCP_RDSIG_8821C 0xffffff\n#define BIT_WMAC_PLCP_RDSIG_8821C(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C)                                \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C)\n#define BITS_WMAC_PLCP_RDSIG_8821C                                             \\\n\t(BIT_MASK_WMAC_PLCP_RDSIG_8821C << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C)\n#define BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8821C))\n#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) &                            \\\n\t BIT_MASK_WMAC_PLCP_RDSIG_8821C)\n#define BIT_SET_WMAC_PLCP_RDSIG_8821C(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) | BIT_WMAC_PLCP_RDSIG_8821C(v))\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_TRANSMIT_ADDRSS_0_8821C (TA0 REGISTER) */\n\n#define BIT_SHIFT_TA0_V1_8821C 0\n#define BIT_MASK_TA0_V1_8821C 0xffffffffL\n#define BIT_TA0_V1_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_TA0_V1_8821C) << BIT_SHIFT_TA0_V1_8821C)\n#define BITS_TA0_V1_8821C (BIT_MASK_TA0_V1_8821C << BIT_SHIFT_TA0_V1_8821C)\n#define BIT_CLEAR_TA0_V1_8821C(x) ((x) & (~BITS_TA0_V1_8821C))\n#define BIT_GET_TA0_V1_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_TA0_V1_8821C) & BIT_MASK_TA0_V1_8821C)\n#define BIT_SET_TA0_V1_8821C(x, v)                                             \\\n\t(BIT_CLEAR_TA0_V1_8821C(x) | BIT_TA0_V1_8821C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_0_H_8821C (TA0 REGISTER) */\n\n#define BIT_SHIFT_TA0_H_V1_8821C 0\n#define BIT_MASK_TA0_H_V1_8821C 0xffff\n#define BIT_TA0_H_V1_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_TA0_H_V1_8821C) << BIT_SHIFT_TA0_H_V1_8821C)\n#define BITS_TA0_H_V1_8821C                                                    \\\n\t(BIT_MASK_TA0_H_V1_8821C << BIT_SHIFT_TA0_H_V1_8821C)\n#define BIT_CLEAR_TA0_H_V1_8821C(x) ((x) & (~BITS_TA0_H_V1_8821C))\n#define BIT_GET_TA0_H_V1_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TA0_H_V1_8821C) & BIT_MASK_TA0_H_V1_8821C)\n#define BIT_SET_TA0_H_V1_8821C(x, v)                                           \\\n\t(BIT_CLEAR_TA0_H_V1_8821C(x) | BIT_TA0_H_V1_8821C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_1_8821C (TA1 REGISTER) */\n\n#define BIT_SHIFT_TA1_V1_8821C 0\n#define BIT_MASK_TA1_V1_8821C 0xffffffffL\n#define BIT_TA1_V1_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_TA1_V1_8821C) << BIT_SHIFT_TA1_V1_8821C)\n#define BITS_TA1_V1_8821C (BIT_MASK_TA1_V1_8821C << BIT_SHIFT_TA1_V1_8821C)\n#define BIT_CLEAR_TA1_V1_8821C(x) ((x) & (~BITS_TA1_V1_8821C))\n#define BIT_GET_TA1_V1_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_TA1_V1_8821C) & BIT_MASK_TA1_V1_8821C)\n#define BIT_SET_TA1_V1_8821C(x, v)                                             \\\n\t(BIT_CLEAR_TA1_V1_8821C(x) | BIT_TA1_V1_8821C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_1_H_8821C (TA1 REGISTER) */\n\n#define BIT_SHIFT_TA1_H_V1_8821C 0\n#define BIT_MASK_TA1_H_V1_8821C 0xffff\n#define BIT_TA1_H_V1_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_TA1_H_V1_8821C) << BIT_SHIFT_TA1_H_V1_8821C)\n#define BITS_TA1_H_V1_8821C                                                    \\\n\t(BIT_MASK_TA1_H_V1_8821C << BIT_SHIFT_TA1_H_V1_8821C)\n#define BIT_CLEAR_TA1_H_V1_8821C(x) ((x) & (~BITS_TA1_H_V1_8821C))\n#define BIT_GET_TA1_H_V1_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TA1_H_V1_8821C) & BIT_MASK_TA1_H_V1_8821C)\n#define BIT_SET_TA1_H_V1_8821C(x, v)                                           \\\n\t(BIT_CLEAR_TA1_H_V1_8821C(x) | BIT_TA1_H_V1_8821C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_2_8821C (TA2 REGISTER) */\n\n#define BIT_SHIFT_TA2_V1_8821C 0\n#define BIT_MASK_TA2_V1_8821C 0xffffffffL\n#define BIT_TA2_V1_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_TA2_V1_8821C) << BIT_SHIFT_TA2_V1_8821C)\n#define BITS_TA2_V1_8821C (BIT_MASK_TA2_V1_8821C << BIT_SHIFT_TA2_V1_8821C)\n#define BIT_CLEAR_TA2_V1_8821C(x) ((x) & (~BITS_TA2_V1_8821C))\n#define BIT_GET_TA2_V1_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_TA2_V1_8821C) & BIT_MASK_TA2_V1_8821C)\n#define BIT_SET_TA2_V1_8821C(x, v)                                             \\\n\t(BIT_CLEAR_TA2_V1_8821C(x) | BIT_TA2_V1_8821C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_2_H_8821C (TA2 REGISTER) */\n\n#define BIT_SHIFT_TA2_H_V1_8821C 0\n#define BIT_MASK_TA2_H_V1_8821C 0xffff\n#define BIT_TA2_H_V1_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_TA2_H_V1_8821C) << BIT_SHIFT_TA2_H_V1_8821C)\n#define BITS_TA2_H_V1_8821C                                                    \\\n\t(BIT_MASK_TA2_H_V1_8821C << BIT_SHIFT_TA2_H_V1_8821C)\n#define BIT_CLEAR_TA2_H_V1_8821C(x) ((x) & (~BITS_TA2_H_V1_8821C))\n#define BIT_GET_TA2_H_V1_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TA2_H_V1_8821C) & BIT_MASK_TA2_H_V1_8821C)\n#define BIT_SET_TA2_H_V1_8821C(x, v)                                           \\\n\t(BIT_CLEAR_TA2_H_V1_8821C(x) | BIT_TA2_H_V1_8821C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_3_8821C (TA3 REGISTER) */\n\n#define BIT_SHIFT_TA2_V1_8821C 0\n#define BIT_MASK_TA2_V1_8821C 0xffffffffL\n#define BIT_TA2_V1_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_TA2_V1_8821C) << BIT_SHIFT_TA2_V1_8821C)\n#define BITS_TA2_V1_8821C (BIT_MASK_TA2_V1_8821C << BIT_SHIFT_TA2_V1_8821C)\n#define BIT_CLEAR_TA2_V1_8821C(x) ((x) & (~BITS_TA2_V1_8821C))\n#define BIT_GET_TA2_V1_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_TA2_V1_8821C) & BIT_MASK_TA2_V1_8821C)\n#define BIT_SET_TA2_V1_8821C(x, v)                                             \\\n\t(BIT_CLEAR_TA2_V1_8821C(x) | BIT_TA2_V1_8821C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_3_H_8821C (TA3 REGISTER) */\n\n#define BIT_SHIFT_TA3_H_V1_8821C 0\n#define BIT_MASK_TA3_H_V1_8821C 0xffff\n#define BIT_TA3_H_V1_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_TA3_H_V1_8821C) << BIT_SHIFT_TA3_H_V1_8821C)\n#define BITS_TA3_H_V1_8821C                                                    \\\n\t(BIT_MASK_TA3_H_V1_8821C << BIT_SHIFT_TA3_H_V1_8821C)\n#define BIT_CLEAR_TA3_H_V1_8821C(x) ((x) & (~BITS_TA3_H_V1_8821C))\n#define BIT_GET_TA3_H_V1_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TA3_H_V1_8821C) & BIT_MASK_TA3_H_V1_8821C)\n#define BIT_SET_TA3_H_V1_8821C(x, v)                                           \\\n\t(BIT_CLEAR_TA3_H_V1_8821C(x) | BIT_TA3_H_V1_8821C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_4_8821C (TA4 REGISTER) */\n\n#define BIT_SHIFT_TA4_V1_8821C 0\n#define BIT_MASK_TA4_V1_8821C 0xffffffffL\n#define BIT_TA4_V1_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_TA4_V1_8821C) << BIT_SHIFT_TA4_V1_8821C)\n#define BITS_TA4_V1_8821C (BIT_MASK_TA4_V1_8821C << BIT_SHIFT_TA4_V1_8821C)\n#define BIT_CLEAR_TA4_V1_8821C(x) ((x) & (~BITS_TA4_V1_8821C))\n#define BIT_GET_TA4_V1_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_TA4_V1_8821C) & BIT_MASK_TA4_V1_8821C)\n#define BIT_SET_TA4_V1_8821C(x, v)                                             \\\n\t(BIT_CLEAR_TA4_V1_8821C(x) | BIT_TA4_V1_8821C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_4_H_8821C (TA4 REGISTER) */\n\n#define BIT_SHIFT_TA4_H_V1_8821C 0\n#define BIT_MASK_TA4_H_V1_8821C 0xffff\n#define BIT_TA4_H_V1_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_TA4_H_V1_8821C) << BIT_SHIFT_TA4_H_V1_8821C)\n#define BITS_TA4_H_V1_8821C                                                    \\\n\t(BIT_MASK_TA4_H_V1_8821C << BIT_SHIFT_TA4_H_V1_8821C)\n#define BIT_CLEAR_TA4_H_V1_8821C(x) ((x) & (~BITS_TA4_H_V1_8821C))\n#define BIT_GET_TA4_H_V1_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TA4_H_V1_8821C) & BIT_MASK_TA4_H_V1_8821C)\n#define BIT_SET_TA4_H_V1_8821C(x, v)                                           \\\n\t(BIT_CLEAR_TA4_H_V1_8821C(x) | BIT_TA4_H_V1_8821C(v))\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_RSVD_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_MACID1_8821C */\n\n#define BIT_SHIFT_MACID1_0_8821C 0\n#define BIT_MASK_MACID1_0_8821C 0xffffffffL\n#define BIT_MACID1_0_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_MACID1_0_8821C) << BIT_SHIFT_MACID1_0_8821C)\n#define BITS_MACID1_0_8821C                                                    \\\n\t(BIT_MASK_MACID1_0_8821C << BIT_SHIFT_MACID1_0_8821C)\n#define BIT_CLEAR_MACID1_0_8821C(x) ((x) & (~BITS_MACID1_0_8821C))\n#define BIT_GET_MACID1_0_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_MACID1_0_8821C) & BIT_MASK_MACID1_0_8821C)\n#define BIT_SET_MACID1_0_8821C(x, v)                                           \\\n\t(BIT_CLEAR_MACID1_0_8821C(x) | BIT_MACID1_0_8821C(v))\n\n/* 2 REG_MACID1_1_8821C */\n\n#define BIT_SHIFT_MACID1_1_8821C 0\n#define BIT_MASK_MACID1_1_8821C 0xffff\n#define BIT_MACID1_1_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_MACID1_1_8821C) << BIT_SHIFT_MACID1_1_8821C)\n#define BITS_MACID1_1_8821C                                                    \\\n\t(BIT_MASK_MACID1_1_8821C << BIT_SHIFT_MACID1_1_8821C)\n#define BIT_CLEAR_MACID1_1_8821C(x) ((x) & (~BITS_MACID1_1_8821C))\n#define BIT_GET_MACID1_1_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_MACID1_1_8821C) & BIT_MASK_MACID1_1_8821C)\n#define BIT_SET_MACID1_1_8821C(x, v)                                           \\\n\t(BIT_CLEAR_MACID1_1_8821C(x) | BIT_MACID1_1_8821C(v))\n\n/* 2 REG_BSSID1_8821C */\n\n#define BIT_SHIFT_BSSID1_0_8821C 0\n#define BIT_MASK_BSSID1_0_8821C 0xffffffffL\n#define BIT_BSSID1_0_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_BSSID1_0_8821C) << BIT_SHIFT_BSSID1_0_8821C)\n#define BITS_BSSID1_0_8821C                                                    \\\n\t(BIT_MASK_BSSID1_0_8821C << BIT_SHIFT_BSSID1_0_8821C)\n#define BIT_CLEAR_BSSID1_0_8821C(x) ((x) & (~BITS_BSSID1_0_8821C))\n#define BIT_GET_BSSID1_0_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_BSSID1_0_8821C) & BIT_MASK_BSSID1_0_8821C)\n#define BIT_SET_BSSID1_0_8821C(x, v)                                           \\\n\t(BIT_CLEAR_BSSID1_0_8821C(x) | BIT_BSSID1_0_8821C(v))\n\n/* 2 REG_BSSID1_1_8821C */\n\n#define BIT_SHIFT_BSSID1_1_8821C 0\n#define BIT_MASK_BSSID1_1_8821C 0xffff\n#define BIT_BSSID1_1_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_BSSID1_1_8821C) << BIT_SHIFT_BSSID1_1_8821C)\n#define BITS_BSSID1_1_8821C                                                    \\\n\t(BIT_MASK_BSSID1_1_8821C << BIT_SHIFT_BSSID1_1_8821C)\n#define BIT_CLEAR_BSSID1_1_8821C(x) ((x) & (~BITS_BSSID1_1_8821C))\n#define BIT_GET_BSSID1_1_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_BSSID1_1_8821C) & BIT_MASK_BSSID1_1_8821C)\n#define BIT_SET_BSSID1_1_8821C(x, v)                                           \\\n\t(BIT_CLEAR_BSSID1_1_8821C(x) | BIT_BSSID1_1_8821C(v))\n\n/* 2 REG_BCN_PSR_RPT1_8821C */\n\n#define BIT_SHIFT_DTIM_CNT1_8821C 24\n#define BIT_MASK_DTIM_CNT1_8821C 0xff\n#define BIT_DTIM_CNT1_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT1_8821C) << BIT_SHIFT_DTIM_CNT1_8821C)\n#define BITS_DTIM_CNT1_8821C                                                   \\\n\t(BIT_MASK_DTIM_CNT1_8821C << BIT_SHIFT_DTIM_CNT1_8821C)\n#define BIT_CLEAR_DTIM_CNT1_8821C(x) ((x) & (~BITS_DTIM_CNT1_8821C))\n#define BIT_GET_DTIM_CNT1_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT1_8821C) & BIT_MASK_DTIM_CNT1_8821C)\n#define BIT_SET_DTIM_CNT1_8821C(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT1_8821C(x) | BIT_DTIM_CNT1_8821C(v))\n\n#define BIT_SHIFT_DTIM_PERIOD1_8821C 16\n#define BIT_MASK_DTIM_PERIOD1_8821C 0xff\n#define BIT_DTIM_PERIOD1_8821C(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD1_8821C) << BIT_SHIFT_DTIM_PERIOD1_8821C)\n#define BITS_DTIM_PERIOD1_8821C                                                \\\n\t(BIT_MASK_DTIM_PERIOD1_8821C << BIT_SHIFT_DTIM_PERIOD1_8821C)\n#define BIT_CLEAR_DTIM_PERIOD1_8821C(x) ((x) & (~BITS_DTIM_PERIOD1_8821C))\n#define BIT_GET_DTIM_PERIOD1_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD1_8821C) & BIT_MASK_DTIM_PERIOD1_8821C)\n#define BIT_SET_DTIM_PERIOD1_8821C(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD1_8821C(x) | BIT_DTIM_PERIOD1_8821C(v))\n\n#define BIT_DTIM1_8821C BIT(15)\n#define BIT_TIM1_8821C BIT(14)\n\n#define BIT_SHIFT_PS_AID_1_8821C 0\n#define BIT_MASK_PS_AID_1_8821C 0x7ff\n#define BIT_PS_AID_1_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_1_8821C) << BIT_SHIFT_PS_AID_1_8821C)\n#define BITS_PS_AID_1_8821C                                                    \\\n\t(BIT_MASK_PS_AID_1_8821C << BIT_SHIFT_PS_AID_1_8821C)\n#define BIT_CLEAR_PS_AID_1_8821C(x) ((x) & (~BITS_PS_AID_1_8821C))\n#define BIT_GET_PS_AID_1_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_1_8821C) & BIT_MASK_PS_AID_1_8821C)\n#define BIT_SET_PS_AID_1_8821C(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_1_8821C(x) | BIT_PS_AID_1_8821C(v))\n\n/* 2 REG_ASSOCIATED_BFMEE_SEL_8821C */\n#define BIT_TXUSER_ID1_8821C BIT(25)\n\n#define BIT_SHIFT_AID1_8821C 16\n#define BIT_MASK_AID1_8821C 0x1ff\n#define BIT_AID1_8821C(x) (((x) & BIT_MASK_AID1_8821C) << BIT_SHIFT_AID1_8821C)\n#define BITS_AID1_8821C (BIT_MASK_AID1_8821C << BIT_SHIFT_AID1_8821C)\n#define BIT_CLEAR_AID1_8821C(x) ((x) & (~BITS_AID1_8821C))\n#define BIT_GET_AID1_8821C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AID1_8821C) & BIT_MASK_AID1_8821C)\n#define BIT_SET_AID1_8821C(x, v) (BIT_CLEAR_AID1_8821C(x) | BIT_AID1_8821C(v))\n\n#define BIT_TXUSER_ID0_8821C BIT(9)\n\n#define BIT_SHIFT_AID0_8821C 0\n#define BIT_MASK_AID0_8821C 0x1ff\n#define BIT_AID0_8821C(x) (((x) & BIT_MASK_AID0_8821C) << BIT_SHIFT_AID0_8821C)\n#define BITS_AID0_8821C (BIT_MASK_AID0_8821C << BIT_SHIFT_AID0_8821C)\n#define BIT_CLEAR_AID0_8821C(x) ((x) & (~BITS_AID0_8821C))\n#define BIT_GET_AID0_8821C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AID0_8821C) & BIT_MASK_AID0_8821C)\n#define BIT_SET_AID0_8821C(x, v) (BIT_CLEAR_AID0_8821C(x) | BIT_AID0_8821C(v))\n\n/* 2 REG_SND_PTCL_CTRL_8821C */\n\n#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C 24\n#define BIT_MASK_NDP_RX_STANDBY_TIMER_8821C 0xff\n#define BIT_NDP_RX_STANDBY_TIMER_8821C(x)                                      \\\n\t(((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8821C)                           \\\n\t << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C)\n#define BITS_NDP_RX_STANDBY_TIMER_8821C                                        \\\n\t(BIT_MASK_NDP_RX_STANDBY_TIMER_8821C                                   \\\n\t << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C)\n#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8821C(x)                                \\\n\t((x) & (~BITS_NDP_RX_STANDBY_TIMER_8821C))\n#define BIT_GET_NDP_RX_STANDBY_TIMER_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C) &                       \\\n\t BIT_MASK_NDP_RX_STANDBY_TIMER_8821C)\n#define BIT_SET_NDP_RX_STANDBY_TIMER_8821C(x, v)                               \\\n\t(BIT_CLEAR_NDP_RX_STANDBY_TIMER_8821C(x) |                             \\\n\t BIT_NDP_RX_STANDBY_TIMER_8821C(v))\n\n#define BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C 16\n#define BIT_MASK_CSI_RPT_OFFSET_HT_8821C 0xff\n#define BIT_CSI_RPT_OFFSET_HT_8821C(x)                                         \\\n\t(((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8821C)                              \\\n\t << BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C)\n#define BITS_CSI_RPT_OFFSET_HT_8821C                                           \\\n\t(BIT_MASK_CSI_RPT_OFFSET_HT_8821C << BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C)\n#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8821C(x)                                   \\\n\t((x) & (~BITS_CSI_RPT_OFFSET_HT_8821C))\n#define BIT_GET_CSI_RPT_OFFSET_HT_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) &                          \\\n\t BIT_MASK_CSI_RPT_OFFSET_HT_8821C)\n#define BIT_SET_CSI_RPT_OFFSET_HT_8821C(x, v)                                  \\\n\t(BIT_CLEAR_CSI_RPT_OFFSET_HT_8821C(x) | BIT_CSI_RPT_OFFSET_HT_8821C(v))\n\n#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C 8\n#define BIT_MASK_R_WMAC_VHT_CATEGORY_8821C 0xff\n#define BIT_R_WMAC_VHT_CATEGORY_8821C(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8821C)                            \\\n\t << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C)\n#define BITS_R_WMAC_VHT_CATEGORY_8821C                                         \\\n\t(BIT_MASK_R_WMAC_VHT_CATEGORY_8821C                                    \\\n\t << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C)\n#define BIT_CLEAR_R_WMAC_VHT_CATEGORY_8821C(x)                                 \\\n\t((x) & (~BITS_R_WMAC_VHT_CATEGORY_8821C))\n#define BIT_GET_R_WMAC_VHT_CATEGORY_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) &                        \\\n\t BIT_MASK_R_WMAC_VHT_CATEGORY_8821C)\n#define BIT_SET_R_WMAC_VHT_CATEGORY_8821C(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_VHT_CATEGORY_8821C(x) |                              \\\n\t BIT_R_WMAC_VHT_CATEGORY_8821C(v))\n\n#define BIT_R_WMAC_USE_NSTS_8821C BIT(7)\n#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8821C BIT(6)\n#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8821C BIT(5)\n#define BIT_R_WMAC_BFPARAM_SEL_8821C BIT(4)\n#define BIT_R_WMAC_CSISEQ_SEL_8821C BIT(3)\n#define BIT_R_WMAC_CSI_WITHHTC_EN_8821C BIT(2)\n#define BIT_R_WMAC_HT_NDPA_EN_8821C BIT(1)\n#define BIT_R_WMAC_VHT_NDPA_EN_8821C BIT(0)\n\n/* 2 REG_RX_CSI_RPT_INFO_8821C */\n\n/* 2 REG_NS_ARP_CTRL_8821C */\n#define BIT_R_WMAC_NSARP_RSPEN_8821C BIT(15)\n#define BIT_R_WMAC_NSARP_RARP_8821C BIT(9)\n#define BIT_R_WMAC_NSARP_RIPV6_8821C BIT(8)\n\n#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C 6\n#define BIT_MASK_R_WMAC_NSARP_MODEN_8821C 0x3\n#define BIT_R_WMAC_NSARP_MODEN_8821C(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8821C)                             \\\n\t << BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C)\n#define BITS_R_WMAC_NSARP_MODEN_8821C                                          \\\n\t(BIT_MASK_R_WMAC_NSARP_MODEN_8821C                                     \\\n\t << BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C)\n#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8821C(x)                                  \\\n\t((x) & (~BITS_R_WMAC_NSARP_MODEN_8821C))\n#define BIT_GET_R_WMAC_NSARP_MODEN_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C) &                         \\\n\t BIT_MASK_R_WMAC_NSARP_MODEN_8821C)\n#define BIT_SET_R_WMAC_NSARP_MODEN_8821C(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_NSARP_MODEN_8821C(x) |                               \\\n\t BIT_R_WMAC_NSARP_MODEN_8821C(v))\n\n#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C 4\n#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C 0x3\n#define BIT_R_WMAC_NSARP_RSPFTP_8821C(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C)                            \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C)\n#define BITS_R_WMAC_NSARP_RSPFTP_8821C                                         \\\n\t(BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C                                    \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C)\n#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8821C(x)                                 \\\n\t((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8821C))\n#define BIT_GET_R_WMAC_NSARP_RSPFTP_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) &                        \\\n\t BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C)\n#define BIT_SET_R_WMAC_NSARP_RSPFTP_8821C(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8821C(x) |                              \\\n\t BIT_R_WMAC_NSARP_RSPFTP_8821C(v))\n\n#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C 0\n#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C 0xf\n#define BIT_R_WMAC_NSARP_RSPSEC_8821C(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C)                            \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C)\n#define BITS_R_WMAC_NSARP_RSPSEC_8821C                                         \\\n\t(BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C                                    \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C)\n#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8821C(x)                                 \\\n\t((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8821C))\n#define BIT_GET_R_WMAC_NSARP_RSPSEC_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) &                        \\\n\t BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C)\n#define BIT_SET_R_WMAC_NSARP_RSPSEC_8821C(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8821C(x) |                              \\\n\t BIT_R_WMAC_NSARP_RSPSEC_8821C(v))\n\n/* 2 REG_NS_ARP_INFO_8821C */\n#define BIT_REQ_IS_MCNS_8821C BIT(23)\n#define BIT_REQ_IS_UCNS_8821C BIT(22)\n#define BIT_REQ_IS_USNS_8821C BIT(21)\n#define BIT_REQ_IS_ARP_8821C BIT(20)\n#define BIT_EXPRSP_MH_WITHQC_8821C BIT(19)\n\n#define BIT_SHIFT_EXPRSP_SECTYPE_8821C 16\n#define BIT_MASK_EXPRSP_SECTYPE_8821C 0x7\n#define BIT_EXPRSP_SECTYPE_8821C(x)                                            \\\n\t(((x) & BIT_MASK_EXPRSP_SECTYPE_8821C)                                 \\\n\t << BIT_SHIFT_EXPRSP_SECTYPE_8821C)\n#define BITS_EXPRSP_SECTYPE_8821C                                              \\\n\t(BIT_MASK_EXPRSP_SECTYPE_8821C << BIT_SHIFT_EXPRSP_SECTYPE_8821C)\n#define BIT_CLEAR_EXPRSP_SECTYPE_8821C(x) ((x) & (~BITS_EXPRSP_SECTYPE_8821C))\n#define BIT_GET_EXPRSP_SECTYPE_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8821C) &                             \\\n\t BIT_MASK_EXPRSP_SECTYPE_8821C)\n#define BIT_SET_EXPRSP_SECTYPE_8821C(x, v)                                     \\\n\t(BIT_CLEAR_EXPRSP_SECTYPE_8821C(x) | BIT_EXPRSP_SECTYPE_8821C(v))\n\n#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C 8\n#define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C 0xff\n#define BIT_EXPRSP_CHKSM_7_TO_0_8821C(x)                                       \\\n\t(((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C)                            \\\n\t << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C)\n#define BITS_EXPRSP_CHKSM_7_TO_0_8821C                                         \\\n\t(BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C                                    \\\n\t << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C)\n#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8821C(x)                                 \\\n\t((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8821C))\n#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) &                        \\\n\t BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C)\n#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8821C(x, v)                                \\\n\t(BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8821C(x) |                              \\\n\t BIT_EXPRSP_CHKSM_7_TO_0_8821C(v))\n\n#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C 0\n#define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C 0xff\n#define BIT_EXPRSP_CHKSM_15_TO_8_8821C(x)                                      \\\n\t(((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C)                           \\\n\t << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C)\n#define BITS_EXPRSP_CHKSM_15_TO_8_8821C                                        \\\n\t(BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C                                   \\\n\t << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C)\n#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8821C(x)                                \\\n\t((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8821C))\n#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) &                       \\\n\t BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C)\n#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8821C(x, v)                               \\\n\t(BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8821C(x) |                             \\\n\t BIT_EXPRSP_CHKSM_15_TO_8_8821C(v))\n\n/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8821C */\n\n#define BIT_SHIFT_WMAC_ARPIP_8821C 0\n#define BIT_MASK_WMAC_ARPIP_8821C 0xffffffffL\n#define BIT_WMAC_ARPIP_8821C(x)                                                \\\n\t(((x) & BIT_MASK_WMAC_ARPIP_8821C) << BIT_SHIFT_WMAC_ARPIP_8821C)\n#define BITS_WMAC_ARPIP_8821C                                                  \\\n\t(BIT_MASK_WMAC_ARPIP_8821C << BIT_SHIFT_WMAC_ARPIP_8821C)\n#define BIT_CLEAR_WMAC_ARPIP_8821C(x) ((x) & (~BITS_WMAC_ARPIP_8821C))\n#define BIT_GET_WMAC_ARPIP_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_WMAC_ARPIP_8821C) & BIT_MASK_WMAC_ARPIP_8821C)\n#define BIT_SET_WMAC_ARPIP_8821C(x, v)                                         \\\n\t(BIT_CLEAR_WMAC_ARPIP_8821C(x) | BIT_WMAC_ARPIP_8821C(v))\n\n/* 2 REG_BEAMFORMING_INFO_NSARP_8821C */\n\n#define BIT_SHIFT_BEAMFORMING_INFO_8821C 0\n#define BIT_MASK_BEAMFORMING_INFO_8821C 0xffffffffL\n#define BIT_BEAMFORMING_INFO_8821C(x)                                          \\\n\t(((x) & BIT_MASK_BEAMFORMING_INFO_8821C)                               \\\n\t << BIT_SHIFT_BEAMFORMING_INFO_8821C)\n#define BITS_BEAMFORMING_INFO_8821C                                            \\\n\t(BIT_MASK_BEAMFORMING_INFO_8821C << BIT_SHIFT_BEAMFORMING_INFO_8821C)\n#define BIT_CLEAR_BEAMFORMING_INFO_8821C(x)                                    \\\n\t((x) & (~BITS_BEAMFORMING_INFO_8821C))\n#define BIT_GET_BEAMFORMING_INFO_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BEAMFORMING_INFO_8821C) &                           \\\n\t BIT_MASK_BEAMFORMING_INFO_8821C)\n#define BIT_SET_BEAMFORMING_INFO_8821C(x, v)                                   \\\n\t(BIT_CLEAR_BEAMFORMING_INFO_8821C(x) | BIT_BEAMFORMING_INFO_8821C(v))\n\n/* 2 REG_IPV6_8821C */\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C 0xffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD_0_8821C(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C)                           \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C)\n#define BITS_R_WMAC_IPV6_MYIPAD_0_8821C                                        \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C                                   \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8821C(x)                                \\\n\t((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0_8821C))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C) &                       \\\n\t BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD_0_8821C(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8821C(x) |                             \\\n\t BIT_R_WMAC_IPV6_MYIPAD_0_8821C(v))\n\n/* 2 REG_IPV6_1_8821C */\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C 0xffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD_1_8821C(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C)                           \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C)\n#define BITS_R_WMAC_IPV6_MYIPAD_1_8821C                                        \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C                                   \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8821C(x)                                \\\n\t((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1_8821C))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C) &                       \\\n\t BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD_1_8821C(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8821C(x) |                             \\\n\t BIT_R_WMAC_IPV6_MYIPAD_1_8821C(v))\n\n/* 2 REG_IPV6_2_8821C */\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C 0xffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD_2_8821C(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C)                           \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C)\n#define BITS_R_WMAC_IPV6_MYIPAD_2_8821C                                        \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C                                   \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8821C(x)                                \\\n\t((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2_8821C))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C) &                       \\\n\t BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD_2_8821C(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8821C(x) |                             \\\n\t BIT_R_WMAC_IPV6_MYIPAD_2_8821C(v))\n\n/* 2 REG_IPV6_3_8821C */\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C 0xffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD_3_8821C(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C)                           \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C)\n#define BITS_R_WMAC_IPV6_MYIPAD_3_8821C                                        \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C                                   \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8821C(x)                                \\\n\t((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3_8821C))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C) &                       \\\n\t BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD_3_8821C(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8821C(x) |                             \\\n\t BIT_R_WMAC_IPV6_MYIPAD_3_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8821C */\n\n#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C 4\n#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C 0xf\n#define BIT_R_WMAC_CTX_SUBTYPE_8821C(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C)                             \\\n\t << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C)\n#define BITS_R_WMAC_CTX_SUBTYPE_8821C                                          \\\n\t(BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C                                     \\\n\t << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C)\n#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8821C(x)                                  \\\n\t((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8821C))\n#define BIT_GET_R_WMAC_CTX_SUBTYPE_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C) &                         \\\n\t BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C)\n#define BIT_SET_R_WMAC_CTX_SUBTYPE_8821C(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8821C(x) |                               \\\n\t BIT_R_WMAC_CTX_SUBTYPE_8821C(v))\n\n#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C 0\n#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C 0xf\n#define BIT_R_WMAC_RTX_SUBTYPE_8821C(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C)                             \\\n\t << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C)\n#define BITS_R_WMAC_RTX_SUBTYPE_8821C                                          \\\n\t(BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C                                     \\\n\t << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C)\n#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8821C(x)                                  \\\n\t((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8821C))\n#define BIT_GET_R_WMAC_RTX_SUBTYPE_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) &                         \\\n\t BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C)\n#define BIT_SET_R_WMAC_RTX_SUBTYPE_8821C(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8821C(x) |                               \\\n\t BIT_R_WMAC_RTX_SUBTYPE_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_WMAC_SWAES_CFG_8821C */\n\n/* 2 REG_BT_COEX_V2_8821C */\n#define BIT_GNT_BT_POLARITY_8821C BIT(12)\n#define BIT_GNT_BT_BYPASS_PRIORITY_8821C BIT(8)\n\n#define BIT_SHIFT_TIMER_8821C 0\n#define BIT_MASK_TIMER_8821C 0xff\n#define BIT_TIMER_8821C(x)                                                     \\\n\t(((x) & BIT_MASK_TIMER_8821C) << BIT_SHIFT_TIMER_8821C)\n#define BITS_TIMER_8821C (BIT_MASK_TIMER_8821C << BIT_SHIFT_TIMER_8821C)\n#define BIT_CLEAR_TIMER_8821C(x) ((x) & (~BITS_TIMER_8821C))\n#define BIT_GET_TIMER_8821C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TIMER_8821C) & BIT_MASK_TIMER_8821C)\n#define BIT_SET_TIMER_8821C(x, v)                                              \\\n\t(BIT_CLEAR_TIMER_8821C(x) | BIT_TIMER_8821C(v))\n\n/* 2 REG_BT_COEX_8821C */\n#define BIT_R_GNT_BT_RFC_SW_8821C BIT(12)\n#define BIT_R_GNT_BT_RFC_SW_EN_8821C BIT(11)\n#define BIT_R_GNT_BT_BB_SW_8821C BIT(10)\n#define BIT_R_GNT_BT_BB_SW_EN_8821C BIT(9)\n#define BIT_R_BT_CNT_THREN_8821C BIT(8)\n\n#define BIT_SHIFT_R_BT_CNT_THR_8821C 0\n#define BIT_MASK_R_BT_CNT_THR_8821C 0xff\n#define BIT_R_BT_CNT_THR_8821C(x)                                              \\\n\t(((x) & BIT_MASK_R_BT_CNT_THR_8821C) << BIT_SHIFT_R_BT_CNT_THR_8821C)\n#define BITS_R_BT_CNT_THR_8821C                                                \\\n\t(BIT_MASK_R_BT_CNT_THR_8821C << BIT_SHIFT_R_BT_CNT_THR_8821C)\n#define BIT_CLEAR_R_BT_CNT_THR_8821C(x) ((x) & (~BITS_R_BT_CNT_THR_8821C))\n#define BIT_GET_R_BT_CNT_THR_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_BT_CNT_THR_8821C) & BIT_MASK_R_BT_CNT_THR_8821C)\n#define BIT_SET_R_BT_CNT_THR_8821C(x, v)                                       \\\n\t(BIT_CLEAR_R_BT_CNT_THR_8821C(x) | BIT_R_BT_CNT_THR_8821C(v))\n\n/* 2 REG_WLAN_ACT_MASK_CTRL_8821C */\n\n#define BIT_SHIFT_RXMYRTS_NAV_V1_8821C 8\n#define BIT_MASK_RXMYRTS_NAV_V1_8821C 0xff\n#define BIT_RXMYRTS_NAV_V1_8821C(x)                                            \\\n\t(((x) & BIT_MASK_RXMYRTS_NAV_V1_8821C)                                 \\\n\t << BIT_SHIFT_RXMYRTS_NAV_V1_8821C)\n#define BITS_RXMYRTS_NAV_V1_8821C                                              \\\n\t(BIT_MASK_RXMYRTS_NAV_V1_8821C << BIT_SHIFT_RXMYRTS_NAV_V1_8821C)\n#define BIT_CLEAR_RXMYRTS_NAV_V1_8821C(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8821C))\n#define BIT_GET_RXMYRTS_NAV_V1_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8821C) &                             \\\n\t BIT_MASK_RXMYRTS_NAV_V1_8821C)\n#define BIT_SET_RXMYRTS_NAV_V1_8821C(x, v)                                     \\\n\t(BIT_CLEAR_RXMYRTS_NAV_V1_8821C(x) | BIT_RXMYRTS_NAV_V1_8821C(v))\n\n#define BIT_SHIFT_RTSRST_V1_8821C 0\n#define BIT_MASK_RTSRST_V1_8821C 0xff\n#define BIT_RTSRST_V1_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_RTSRST_V1_8821C) << BIT_SHIFT_RTSRST_V1_8821C)\n#define BITS_RTSRST_V1_8821C                                                   \\\n\t(BIT_MASK_RTSRST_V1_8821C << BIT_SHIFT_RTSRST_V1_8821C)\n#define BIT_CLEAR_RTSRST_V1_8821C(x) ((x) & (~BITS_RTSRST_V1_8821C))\n#define BIT_GET_RTSRST_V1_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_RTSRST_V1_8821C) & BIT_MASK_RTSRST_V1_8821C)\n#define BIT_SET_RTSRST_V1_8821C(x, v)                                          \\\n\t(BIT_CLEAR_RTSRST_V1_8821C(x) | BIT_RTSRST_V1_8821C(v))\n\n/* 2 REG_WLAN_ACT_MASK_CTRL_1_8821C */\n#define BIT_WLRX_TER_BY_CTL_1_8821C BIT(11)\n#define BIT_WLRX_TER_BY_AD_1_8821C BIT(10)\n#define BIT_ANT_DIVERSITY_SEL_1_8821C BIT(9)\n#define BIT_ANTSEL_FOR_BT_CTRL_EN_1_8821C BIT(8)\n#define BIT_WLACT_LOW_GNTWL_EN_1_8821C BIT(2)\n#define BIT_WLACT_HIGH_GNTBT_EN_1_8821C BIT(1)\n#define BIT_NAV_UPPER_1_V1_8821C BIT(0)\n\n/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8821C */\n\n#define BIT_SHIFT_BT_STAT_DELAY_8821C 12\n#define BIT_MASK_BT_STAT_DELAY_8821C 0xf\n#define BIT_BT_STAT_DELAY_8821C(x)                                             \\\n\t(((x) & BIT_MASK_BT_STAT_DELAY_8821C) << BIT_SHIFT_BT_STAT_DELAY_8821C)\n#define BITS_BT_STAT_DELAY_8821C                                               \\\n\t(BIT_MASK_BT_STAT_DELAY_8821C << BIT_SHIFT_BT_STAT_DELAY_8821C)\n#define BIT_CLEAR_BT_STAT_DELAY_8821C(x) ((x) & (~BITS_BT_STAT_DELAY_8821C))\n#define BIT_GET_BT_STAT_DELAY_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BT_STAT_DELAY_8821C) & BIT_MASK_BT_STAT_DELAY_8821C)\n#define BIT_SET_BT_STAT_DELAY_8821C(x, v)                                      \\\n\t(BIT_CLEAR_BT_STAT_DELAY_8821C(x) | BIT_BT_STAT_DELAY_8821C(v))\n\n#define BIT_SHIFT_BT_TRX_INIT_DETECT_8821C 8\n#define BIT_MASK_BT_TRX_INIT_DETECT_8821C 0xf\n#define BIT_BT_TRX_INIT_DETECT_8821C(x)                                        \\\n\t(((x) & BIT_MASK_BT_TRX_INIT_DETECT_8821C)                             \\\n\t << BIT_SHIFT_BT_TRX_INIT_DETECT_8821C)\n#define BITS_BT_TRX_INIT_DETECT_8821C                                          \\\n\t(BIT_MASK_BT_TRX_INIT_DETECT_8821C                                     \\\n\t << BIT_SHIFT_BT_TRX_INIT_DETECT_8821C)\n#define BIT_CLEAR_BT_TRX_INIT_DETECT_8821C(x)                                  \\\n\t((x) & (~BITS_BT_TRX_INIT_DETECT_8821C))\n#define BIT_GET_BT_TRX_INIT_DETECT_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) &                         \\\n\t BIT_MASK_BT_TRX_INIT_DETECT_8821C)\n#define BIT_SET_BT_TRX_INIT_DETECT_8821C(x, v)                                 \\\n\t(BIT_CLEAR_BT_TRX_INIT_DETECT_8821C(x) |                               \\\n\t BIT_BT_TRX_INIT_DETECT_8821C(v))\n\n#define BIT_SHIFT_BT_PRI_DETECT_TO_8821C 4\n#define BIT_MASK_BT_PRI_DETECT_TO_8821C 0xf\n#define BIT_BT_PRI_DETECT_TO_8821C(x)                                          \\\n\t(((x) & BIT_MASK_BT_PRI_DETECT_TO_8821C)                               \\\n\t << BIT_SHIFT_BT_PRI_DETECT_TO_8821C)\n#define BITS_BT_PRI_DETECT_TO_8821C                                            \\\n\t(BIT_MASK_BT_PRI_DETECT_TO_8821C << BIT_SHIFT_BT_PRI_DETECT_TO_8821C)\n#define BIT_CLEAR_BT_PRI_DETECT_TO_8821C(x)                                    \\\n\t((x) & (~BITS_BT_PRI_DETECT_TO_8821C))\n#define BIT_GET_BT_PRI_DETECT_TO_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8821C) &                           \\\n\t BIT_MASK_BT_PRI_DETECT_TO_8821C)\n#define BIT_SET_BT_PRI_DETECT_TO_8821C(x, v)                                   \\\n\t(BIT_CLEAR_BT_PRI_DETECT_TO_8821C(x) | BIT_BT_PRI_DETECT_TO_8821C(v))\n\n#define BIT_R_GRANTALL_WLMASK_8821C BIT(3)\n#define BIT_STATIS_BT_EN_8821C BIT(2)\n#define BIT_WL_ACT_MASK_ENABLE_8821C BIT(1)\n#define BIT_ENHANCED_BT_8821C BIT(0)\n\n/* 2 REG_BT_ACT_STATISTICS_8821C */\n\n#define BIT_SHIFT_STATIS_BT_HI_RX_8821C 16\n#define BIT_MASK_STATIS_BT_HI_RX_8821C 0xffff\n#define BIT_STATIS_BT_HI_RX_8821C(x)                                           \\\n\t(((x) & BIT_MASK_STATIS_BT_HI_RX_8821C)                                \\\n\t << BIT_SHIFT_STATIS_BT_HI_RX_8821C)\n#define BITS_STATIS_BT_HI_RX_8821C                                             \\\n\t(BIT_MASK_STATIS_BT_HI_RX_8821C << BIT_SHIFT_STATIS_BT_HI_RX_8821C)\n#define BIT_CLEAR_STATIS_BT_HI_RX_8821C(x) ((x) & (~BITS_STATIS_BT_HI_RX_8821C))\n#define BIT_GET_STATIS_BT_HI_RX_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8821C) &                            \\\n\t BIT_MASK_STATIS_BT_HI_RX_8821C)\n#define BIT_SET_STATIS_BT_HI_RX_8821C(x, v)                                    \\\n\t(BIT_CLEAR_STATIS_BT_HI_RX_8821C(x) | BIT_STATIS_BT_HI_RX_8821C(v))\n\n#define BIT_SHIFT_STATIS_BT_HI_TX_8821C 0\n#define BIT_MASK_STATIS_BT_HI_TX_8821C 0xffff\n#define BIT_STATIS_BT_HI_TX_8821C(x)                                           \\\n\t(((x) & BIT_MASK_STATIS_BT_HI_TX_8821C)                                \\\n\t << BIT_SHIFT_STATIS_BT_HI_TX_8821C)\n#define BITS_STATIS_BT_HI_TX_8821C                                             \\\n\t(BIT_MASK_STATIS_BT_HI_TX_8821C << BIT_SHIFT_STATIS_BT_HI_TX_8821C)\n#define BIT_CLEAR_STATIS_BT_HI_TX_8821C(x) ((x) & (~BITS_STATIS_BT_HI_TX_8821C))\n#define BIT_GET_STATIS_BT_HI_TX_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8821C) &                            \\\n\t BIT_MASK_STATIS_BT_HI_TX_8821C)\n#define BIT_SET_STATIS_BT_HI_TX_8821C(x, v)                                    \\\n\t(BIT_CLEAR_STATIS_BT_HI_TX_8821C(x) | BIT_STATIS_BT_HI_TX_8821C(v))\n\n/* 2 REG_BT_ACT_STATISTICS_1_8821C */\n\n#define BIT_SHIFT_STATIS_BT_LO_RX_1_8821C 16\n#define BIT_MASK_STATIS_BT_LO_RX_1_8821C 0xffff\n#define BIT_STATIS_BT_LO_RX_1_8821C(x)                                         \\\n\t(((x) & BIT_MASK_STATIS_BT_LO_RX_1_8821C)                              \\\n\t << BIT_SHIFT_STATIS_BT_LO_RX_1_8821C)\n#define BITS_STATIS_BT_LO_RX_1_8821C                                           \\\n\t(BIT_MASK_STATIS_BT_LO_RX_1_8821C << BIT_SHIFT_STATIS_BT_LO_RX_1_8821C)\n#define BIT_CLEAR_STATIS_BT_LO_RX_1_8821C(x)                                   \\\n\t((x) & (~BITS_STATIS_BT_LO_RX_1_8821C))\n#define BIT_GET_STATIS_BT_LO_RX_1_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8821C) &                          \\\n\t BIT_MASK_STATIS_BT_LO_RX_1_8821C)\n#define BIT_SET_STATIS_BT_LO_RX_1_8821C(x, v)                                  \\\n\t(BIT_CLEAR_STATIS_BT_LO_RX_1_8821C(x) | BIT_STATIS_BT_LO_RX_1_8821C(v))\n\n#define BIT_SHIFT_STATIS_BT_LO_TX_1_8821C 0\n#define BIT_MASK_STATIS_BT_LO_TX_1_8821C 0xffff\n#define BIT_STATIS_BT_LO_TX_1_8821C(x)                                         \\\n\t(((x) & BIT_MASK_STATIS_BT_LO_TX_1_8821C)                              \\\n\t << BIT_SHIFT_STATIS_BT_LO_TX_1_8821C)\n#define BITS_STATIS_BT_LO_TX_1_8821C                                           \\\n\t(BIT_MASK_STATIS_BT_LO_TX_1_8821C << BIT_SHIFT_STATIS_BT_LO_TX_1_8821C)\n#define BIT_CLEAR_STATIS_BT_LO_TX_1_8821C(x)                                   \\\n\t((x) & (~BITS_STATIS_BT_LO_TX_1_8821C))\n#define BIT_GET_STATIS_BT_LO_TX_1_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8821C) &                          \\\n\t BIT_MASK_STATIS_BT_LO_TX_1_8821C)\n#define BIT_SET_STATIS_BT_LO_TX_1_8821C(x, v)                                  \\\n\t(BIT_CLEAR_STATIS_BT_LO_TX_1_8821C(x) | BIT_STATIS_BT_LO_TX_1_8821C(v))\n\n/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8821C */\n\n#define BIT_SHIFT_R_BT_CMD_RPT_8821C 16\n#define BIT_MASK_R_BT_CMD_RPT_8821C 0xffff\n#define BIT_R_BT_CMD_RPT_8821C(x)                                              \\\n\t(((x) & BIT_MASK_R_BT_CMD_RPT_8821C) << BIT_SHIFT_R_BT_CMD_RPT_8821C)\n#define BITS_R_BT_CMD_RPT_8821C                                                \\\n\t(BIT_MASK_R_BT_CMD_RPT_8821C << BIT_SHIFT_R_BT_CMD_RPT_8821C)\n#define BIT_CLEAR_R_BT_CMD_RPT_8821C(x) ((x) & (~BITS_R_BT_CMD_RPT_8821C))\n#define BIT_GET_R_BT_CMD_RPT_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_BT_CMD_RPT_8821C) & BIT_MASK_R_BT_CMD_RPT_8821C)\n#define BIT_SET_R_BT_CMD_RPT_8821C(x, v)                                       \\\n\t(BIT_CLEAR_R_BT_CMD_RPT_8821C(x) | BIT_R_BT_CMD_RPT_8821C(v))\n\n#define BIT_SHIFT_R_RPT_FROM_BT_8821C 8\n#define BIT_MASK_R_RPT_FROM_BT_8821C 0xff\n#define BIT_R_RPT_FROM_BT_8821C(x)                                             \\\n\t(((x) & BIT_MASK_R_RPT_FROM_BT_8821C) << BIT_SHIFT_R_RPT_FROM_BT_8821C)\n#define BITS_R_RPT_FROM_BT_8821C                                               \\\n\t(BIT_MASK_R_RPT_FROM_BT_8821C << BIT_SHIFT_R_RPT_FROM_BT_8821C)\n#define BIT_CLEAR_R_RPT_FROM_BT_8821C(x) ((x) & (~BITS_R_RPT_FROM_BT_8821C))\n#define BIT_GET_R_RPT_FROM_BT_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_RPT_FROM_BT_8821C) & BIT_MASK_R_RPT_FROM_BT_8821C)\n#define BIT_SET_R_RPT_FROM_BT_8821C(x, v)                                      \\\n\t(BIT_CLEAR_R_RPT_FROM_BT_8821C(x) | BIT_R_RPT_FROM_BT_8821C(v))\n\n#define BIT_SHIFT_BT_HID_ISR_SET_8821C 6\n#define BIT_MASK_BT_HID_ISR_SET_8821C 0x3\n#define BIT_BT_HID_ISR_SET_8821C(x)                                            \\\n\t(((x) & BIT_MASK_BT_HID_ISR_SET_8821C)                                 \\\n\t << BIT_SHIFT_BT_HID_ISR_SET_8821C)\n#define BITS_BT_HID_ISR_SET_8821C                                              \\\n\t(BIT_MASK_BT_HID_ISR_SET_8821C << BIT_SHIFT_BT_HID_ISR_SET_8821C)\n#define BIT_CLEAR_BT_HID_ISR_SET_8821C(x) ((x) & (~BITS_BT_HID_ISR_SET_8821C))\n#define BIT_GET_BT_HID_ISR_SET_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_BT_HID_ISR_SET_8821C) &                             \\\n\t BIT_MASK_BT_HID_ISR_SET_8821C)\n#define BIT_SET_BT_HID_ISR_SET_8821C(x, v)                                     \\\n\t(BIT_CLEAR_BT_HID_ISR_SET_8821C(x) | BIT_BT_HID_ISR_SET_8821C(v))\n\n#define BIT_TDMA_BT_START_NOTIFY_8821C BIT(5)\n#define BIT_ENABLE_TDMA_FW_MODE_8821C BIT(4)\n#define BIT_ENABLE_PTA_TDMA_MODE_8821C BIT(3)\n#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8821C BIT(2)\n#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8821C BIT(1)\n#define BIT_RTK_BT_ENABLE_8821C BIT(0)\n\n/* 2 REG_BT_STATUS_REPORT_REGISTER_8821C */\n\n#define BIT_SHIFT_BT_PROFILE_8821C 24\n#define BIT_MASK_BT_PROFILE_8821C 0xff\n#define BIT_BT_PROFILE_8821C(x)                                                \\\n\t(((x) & BIT_MASK_BT_PROFILE_8821C) << BIT_SHIFT_BT_PROFILE_8821C)\n#define BITS_BT_PROFILE_8821C                                                  \\\n\t(BIT_MASK_BT_PROFILE_8821C << BIT_SHIFT_BT_PROFILE_8821C)\n#define BIT_CLEAR_BT_PROFILE_8821C(x) ((x) & (~BITS_BT_PROFILE_8821C))\n#define BIT_GET_BT_PROFILE_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BT_PROFILE_8821C) & BIT_MASK_BT_PROFILE_8821C)\n#define BIT_SET_BT_PROFILE_8821C(x, v)                                         \\\n\t(BIT_CLEAR_BT_PROFILE_8821C(x) | BIT_BT_PROFILE_8821C(v))\n\n#define BIT_SHIFT_BT_POWER_8821C 16\n#define BIT_MASK_BT_POWER_8821C 0xff\n#define BIT_BT_POWER_8821C(x)                                                  \\\n\t(((x) & BIT_MASK_BT_POWER_8821C) << BIT_SHIFT_BT_POWER_8821C)\n#define BITS_BT_POWER_8821C                                                    \\\n\t(BIT_MASK_BT_POWER_8821C << BIT_SHIFT_BT_POWER_8821C)\n#define BIT_CLEAR_BT_POWER_8821C(x) ((x) & (~BITS_BT_POWER_8821C))\n#define BIT_GET_BT_POWER_8821C(x)                                              \\\n\t(((x) >> BIT_SHIFT_BT_POWER_8821C) & BIT_MASK_BT_POWER_8821C)\n#define BIT_SET_BT_POWER_8821C(x, v)                                           \\\n\t(BIT_CLEAR_BT_POWER_8821C(x) | BIT_BT_POWER_8821C(v))\n\n#define BIT_SHIFT_BT_PREDECT_STATUS_8821C 8\n#define BIT_MASK_BT_PREDECT_STATUS_8821C 0xff\n#define BIT_BT_PREDECT_STATUS_8821C(x)                                         \\\n\t(((x) & BIT_MASK_BT_PREDECT_STATUS_8821C)                              \\\n\t << BIT_SHIFT_BT_PREDECT_STATUS_8821C)\n#define BITS_BT_PREDECT_STATUS_8821C                                           \\\n\t(BIT_MASK_BT_PREDECT_STATUS_8821C << BIT_SHIFT_BT_PREDECT_STATUS_8821C)\n#define BIT_CLEAR_BT_PREDECT_STATUS_8821C(x)                                   \\\n\t((x) & (~BITS_BT_PREDECT_STATUS_8821C))\n#define BIT_GET_BT_PREDECT_STATUS_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8821C) &                          \\\n\t BIT_MASK_BT_PREDECT_STATUS_8821C)\n#define BIT_SET_BT_PREDECT_STATUS_8821C(x, v)                                  \\\n\t(BIT_CLEAR_BT_PREDECT_STATUS_8821C(x) | BIT_BT_PREDECT_STATUS_8821C(v))\n\n#define BIT_SHIFT_BT_CMD_INFO_8821C 0\n#define BIT_MASK_BT_CMD_INFO_8821C 0xff\n#define BIT_BT_CMD_INFO_8821C(x)                                               \\\n\t(((x) & BIT_MASK_BT_CMD_INFO_8821C) << BIT_SHIFT_BT_CMD_INFO_8821C)\n#define BITS_BT_CMD_INFO_8821C                                                 \\\n\t(BIT_MASK_BT_CMD_INFO_8821C << BIT_SHIFT_BT_CMD_INFO_8821C)\n#define BIT_CLEAR_BT_CMD_INFO_8821C(x) ((x) & (~BITS_BT_CMD_INFO_8821C))\n#define BIT_GET_BT_CMD_INFO_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_BT_CMD_INFO_8821C) & BIT_MASK_BT_CMD_INFO_8821C)\n#define BIT_SET_BT_CMD_INFO_8821C(x, v)                                        \\\n\t(BIT_CLEAR_BT_CMD_INFO_8821C(x) | BIT_BT_CMD_INFO_8821C(v))\n\n/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8821C */\n#define BIT_EN_MAC_NULL_PKT_NOTIFY_8821C BIT(31)\n#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8821C BIT(30)\n#define BIT_EN_BT_STSTUS_RPT_8821C BIT(29)\n#define BIT_EN_BT_POWER_8821C BIT(28)\n#define BIT_EN_BT_CHANNEL_8821C BIT(27)\n#define BIT_EN_BT_SLOT_CHANGE_8821C BIT(26)\n#define BIT_EN_BT_PROFILE_OR_HID_8821C BIT(25)\n#define BIT_WLAN_RPT_NOTIFY_8821C BIT(24)\n\n#define BIT_SHIFT_WLAN_RPT_DATA_8821C 16\n#define BIT_MASK_WLAN_RPT_DATA_8821C 0xff\n#define BIT_WLAN_RPT_DATA_8821C(x)                                             \\\n\t(((x) & BIT_MASK_WLAN_RPT_DATA_8821C) << BIT_SHIFT_WLAN_RPT_DATA_8821C)\n#define BITS_WLAN_RPT_DATA_8821C                                               \\\n\t(BIT_MASK_WLAN_RPT_DATA_8821C << BIT_SHIFT_WLAN_RPT_DATA_8821C)\n#define BIT_CLEAR_WLAN_RPT_DATA_8821C(x) ((x) & (~BITS_WLAN_RPT_DATA_8821C))\n#define BIT_GET_WLAN_RPT_DATA_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_WLAN_RPT_DATA_8821C) & BIT_MASK_WLAN_RPT_DATA_8821C)\n#define BIT_SET_WLAN_RPT_DATA_8821C(x, v)                                      \\\n\t(BIT_CLEAR_WLAN_RPT_DATA_8821C(x) | BIT_WLAN_RPT_DATA_8821C(v))\n\n#define BIT_SHIFT_CMD_ID_8821C 8\n#define BIT_MASK_CMD_ID_8821C 0xff\n#define BIT_CMD_ID_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_CMD_ID_8821C) << BIT_SHIFT_CMD_ID_8821C)\n#define BITS_CMD_ID_8821C (BIT_MASK_CMD_ID_8821C << BIT_SHIFT_CMD_ID_8821C)\n#define BIT_CLEAR_CMD_ID_8821C(x) ((x) & (~BITS_CMD_ID_8821C))\n#define BIT_GET_CMD_ID_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_CMD_ID_8821C) & BIT_MASK_CMD_ID_8821C)\n#define BIT_SET_CMD_ID_8821C(x, v)                                             \\\n\t(BIT_CLEAR_CMD_ID_8821C(x) | BIT_CMD_ID_8821C(v))\n\n#define BIT_SHIFT_BT_DATA_8821C 0\n#define BIT_MASK_BT_DATA_8821C 0xff\n#define BIT_BT_DATA_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_BT_DATA_8821C) << BIT_SHIFT_BT_DATA_8821C)\n#define BITS_BT_DATA_8821C (BIT_MASK_BT_DATA_8821C << BIT_SHIFT_BT_DATA_8821C)\n#define BIT_CLEAR_BT_DATA_8821C(x) ((x) & (~BITS_BT_DATA_8821C))\n#define BIT_GET_BT_DATA_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_BT_DATA_8821C) & BIT_MASK_BT_DATA_8821C)\n#define BIT_SET_BT_DATA_8821C(x, v)                                            \\\n\t(BIT_CLEAR_BT_DATA_8821C(x) | BIT_BT_DATA_8821C(v))\n\n/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8821C */\n\n#define BIT_SHIFT_WLAN_RPT_TO_8821C 0\n#define BIT_MASK_WLAN_RPT_TO_8821C 0xff\n#define BIT_WLAN_RPT_TO_8821C(x)                                               \\\n\t(((x) & BIT_MASK_WLAN_RPT_TO_8821C) << BIT_SHIFT_WLAN_RPT_TO_8821C)\n#define BITS_WLAN_RPT_TO_8821C                                                 \\\n\t(BIT_MASK_WLAN_RPT_TO_8821C << BIT_SHIFT_WLAN_RPT_TO_8821C)\n#define BIT_CLEAR_WLAN_RPT_TO_8821C(x) ((x) & (~BITS_WLAN_RPT_TO_8821C))\n#define BIT_GET_WLAN_RPT_TO_8821C(x)                                           \\\n\t(((x) >> BIT_SHIFT_WLAN_RPT_TO_8821C) & BIT_MASK_WLAN_RPT_TO_8821C)\n#define BIT_SET_WLAN_RPT_TO_8821C(x, v)                                        \\\n\t(BIT_CLEAR_WLAN_RPT_TO_8821C(x) | BIT_WLAN_RPT_TO_8821C(v))\n\n/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8821C */\n\n#define BIT_SHIFT_ISOLATION_CHK_0_8821C 1\n#define BIT_MASK_ISOLATION_CHK_0_8821C 0x7fffff\n#define BIT_ISOLATION_CHK_0_8821C(x)                                           \\\n\t(((x) & BIT_MASK_ISOLATION_CHK_0_8821C)                                \\\n\t << BIT_SHIFT_ISOLATION_CHK_0_8821C)\n#define BITS_ISOLATION_CHK_0_8821C                                             \\\n\t(BIT_MASK_ISOLATION_CHK_0_8821C << BIT_SHIFT_ISOLATION_CHK_0_8821C)\n#define BIT_CLEAR_ISOLATION_CHK_0_8821C(x) ((x) & (~BITS_ISOLATION_CHK_0_8821C))\n#define BIT_GET_ISOLATION_CHK_0_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_ISOLATION_CHK_0_8821C) &                            \\\n\t BIT_MASK_ISOLATION_CHK_0_8821C)\n#define BIT_SET_ISOLATION_CHK_0_8821C(x, v)                                    \\\n\t(BIT_CLEAR_ISOLATION_CHK_0_8821C(x) | BIT_ISOLATION_CHK_0_8821C(v))\n\n#define BIT_ISOLATION_EN_8821C BIT(0)\n\n/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8821C */\n\n#define BIT_SHIFT_ISOLATION_CHK_1_8821C 0\n#define BIT_MASK_ISOLATION_CHK_1_8821C 0xffffffffL\n#define BIT_ISOLATION_CHK_1_8821C(x)                                           \\\n\t(((x) & BIT_MASK_ISOLATION_CHK_1_8821C)                                \\\n\t << BIT_SHIFT_ISOLATION_CHK_1_8821C)\n#define BITS_ISOLATION_CHK_1_8821C                                             \\\n\t(BIT_MASK_ISOLATION_CHK_1_8821C << BIT_SHIFT_ISOLATION_CHK_1_8821C)\n#define BIT_CLEAR_ISOLATION_CHK_1_8821C(x) ((x) & (~BITS_ISOLATION_CHK_1_8821C))\n#define BIT_GET_ISOLATION_CHK_1_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_ISOLATION_CHK_1_8821C) &                            \\\n\t BIT_MASK_ISOLATION_CHK_1_8821C)\n#define BIT_SET_ISOLATION_CHK_1_8821C(x, v)                                    \\\n\t(BIT_CLEAR_ISOLATION_CHK_1_8821C(x) | BIT_ISOLATION_CHK_1_8821C(v))\n\n/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8821C */\n\n#define BIT_SHIFT_ISOLATION_CHK_2_8821C 0\n#define BIT_MASK_ISOLATION_CHK_2_8821C 0xffffff\n#define BIT_ISOLATION_CHK_2_8821C(x)                                           \\\n\t(((x) & BIT_MASK_ISOLATION_CHK_2_8821C)                                \\\n\t << BIT_SHIFT_ISOLATION_CHK_2_8821C)\n#define BITS_ISOLATION_CHK_2_8821C                                             \\\n\t(BIT_MASK_ISOLATION_CHK_2_8821C << BIT_SHIFT_ISOLATION_CHK_2_8821C)\n#define BIT_CLEAR_ISOLATION_CHK_2_8821C(x) ((x) & (~BITS_ISOLATION_CHK_2_8821C))\n#define BIT_GET_ISOLATION_CHK_2_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_ISOLATION_CHK_2_8821C) &                            \\\n\t BIT_MASK_ISOLATION_CHK_2_8821C)\n#define BIT_SET_ISOLATION_CHK_2_8821C(x, v)                                    \\\n\t(BIT_CLEAR_ISOLATION_CHK_2_8821C(x) | BIT_ISOLATION_CHK_2_8821C(v))\n\n/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8821C */\n#define BIT_BT_HID_ISR_8821C BIT(7)\n#define BIT_BT_QUERY_ISR_8821C BIT(6)\n#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8821C BIT(5)\n#define BIT_WLAN_RPT_ISR_8821C BIT(4)\n#define BIT_BT_POWER_ISR_8821C BIT(3)\n#define BIT_BT_CHANNEL_ISR_8821C BIT(2)\n#define BIT_BT_SLOT_CHANGE_ISR_8821C BIT(1)\n#define BIT_BT_PROFILE_ISR_8821C BIT(0)\n\n/* 2 REG_BT_TDMA_TIME_REGISTER_8821C */\n\n#define BIT_SHIFT_BT_TIME_8821C 6\n#define BIT_MASK_BT_TIME_8821C 0x3ffffff\n#define BIT_BT_TIME_8821C(x)                                                   \\\n\t(((x) & BIT_MASK_BT_TIME_8821C) << BIT_SHIFT_BT_TIME_8821C)\n#define BITS_BT_TIME_8821C (BIT_MASK_BT_TIME_8821C << BIT_SHIFT_BT_TIME_8821C)\n#define BIT_CLEAR_BT_TIME_8821C(x) ((x) & (~BITS_BT_TIME_8821C))\n#define BIT_GET_BT_TIME_8821C(x)                                               \\\n\t(((x) >> BIT_SHIFT_BT_TIME_8821C) & BIT_MASK_BT_TIME_8821C)\n#define BIT_SET_BT_TIME_8821C(x, v)                                            \\\n\t(BIT_CLEAR_BT_TIME_8821C(x) | BIT_BT_TIME_8821C(v))\n\n#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C 0\n#define BIT_MASK_BT_RPT_SAMPLE_RATE_8821C 0x3f\n#define BIT_BT_RPT_SAMPLE_RATE_8821C(x)                                        \\\n\t(((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8821C)                             \\\n\t << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C)\n#define BITS_BT_RPT_SAMPLE_RATE_8821C                                          \\\n\t(BIT_MASK_BT_RPT_SAMPLE_RATE_8821C                                     \\\n\t << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C)\n#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8821C(x)                                  \\\n\t((x) & (~BITS_BT_RPT_SAMPLE_RATE_8821C))\n#define BIT_GET_BT_RPT_SAMPLE_RATE_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) &                         \\\n\t BIT_MASK_BT_RPT_SAMPLE_RATE_8821C)\n#define BIT_SET_BT_RPT_SAMPLE_RATE_8821C(x, v)                                 \\\n\t(BIT_CLEAR_BT_RPT_SAMPLE_RATE_8821C(x) |                               \\\n\t BIT_BT_RPT_SAMPLE_RATE_8821C(v))\n\n/* 2 REG_BT_ACT_REGISTER_8821C */\n\n#define BIT_SHIFT_BT_EISR_EN_8821C 16\n#define BIT_MASK_BT_EISR_EN_8821C 0xff\n#define BIT_BT_EISR_EN_8821C(x)                                                \\\n\t(((x) & BIT_MASK_BT_EISR_EN_8821C) << BIT_SHIFT_BT_EISR_EN_8821C)\n#define BITS_BT_EISR_EN_8821C                                                  \\\n\t(BIT_MASK_BT_EISR_EN_8821C << BIT_SHIFT_BT_EISR_EN_8821C)\n#define BIT_CLEAR_BT_EISR_EN_8821C(x) ((x) & (~BITS_BT_EISR_EN_8821C))\n#define BIT_GET_BT_EISR_EN_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BT_EISR_EN_8821C) & BIT_MASK_BT_EISR_EN_8821C)\n#define BIT_SET_BT_EISR_EN_8821C(x, v)                                         \\\n\t(BIT_CLEAR_BT_EISR_EN_8821C(x) | BIT_BT_EISR_EN_8821C(v))\n\n#define BIT_BT_ACT_FALLING_ISR_8821C BIT(10)\n#define BIT_BT_ACT_RISING_ISR_8821C BIT(9)\n#define BIT_TDMA_TO_ISR_8821C BIT(8)\n\n#define BIT_SHIFT_BT_CH_8821C 0\n#define BIT_MASK_BT_CH_8821C 0xff\n#define BIT_BT_CH_8821C(x)                                                     \\\n\t(((x) & BIT_MASK_BT_CH_8821C) << BIT_SHIFT_BT_CH_8821C)\n#define BITS_BT_CH_8821C (BIT_MASK_BT_CH_8821C << BIT_SHIFT_BT_CH_8821C)\n#define BIT_CLEAR_BT_CH_8821C(x) ((x) & (~BITS_BT_CH_8821C))\n#define BIT_GET_BT_CH_8821C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_BT_CH_8821C) & BIT_MASK_BT_CH_8821C)\n#define BIT_SET_BT_CH_8821C(x, v)                                              \\\n\t(BIT_CLEAR_BT_CH_8821C(x) | BIT_BT_CH_8821C(v))\n\n/* 2 REG_OBFF_CTRL_BASIC_8821C */\n#define BIT_OBFF_EN_V1_8821C BIT(31)\n\n#define BIT_SHIFT_OBFF_STATE_V1_8821C 28\n#define BIT_MASK_OBFF_STATE_V1_8821C 0x3\n#define BIT_OBFF_STATE_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_OBFF_STATE_V1_8821C) << BIT_SHIFT_OBFF_STATE_V1_8821C)\n#define BITS_OBFF_STATE_V1_8821C                                               \\\n\t(BIT_MASK_OBFF_STATE_V1_8821C << BIT_SHIFT_OBFF_STATE_V1_8821C)\n#define BIT_CLEAR_OBFF_STATE_V1_8821C(x) ((x) & (~BITS_OBFF_STATE_V1_8821C))\n#define BIT_GET_OBFF_STATE_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_OBFF_STATE_V1_8821C) & BIT_MASK_OBFF_STATE_V1_8821C)\n#define BIT_SET_OBFF_STATE_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_OBFF_STATE_V1_8821C(x) | BIT_OBFF_STATE_V1_8821C(v))\n\n#define BIT_OBFF_ACT_RXDMA_EN_8821C BIT(27)\n#define BIT_OBFF_BLOCK_INT_EN_8821C BIT(26)\n#define BIT_OBFF_AUTOACT_EN_8821C BIT(25)\n#define BIT_OBFF_AUTOIDLE_EN_8821C BIT(24)\n\n#define BIT_SHIFT_WAKE_MAX_PLS_8821C 20\n#define BIT_MASK_WAKE_MAX_PLS_8821C 0x7\n#define BIT_WAKE_MAX_PLS_8821C(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MAX_PLS_8821C) << BIT_SHIFT_WAKE_MAX_PLS_8821C)\n#define BITS_WAKE_MAX_PLS_8821C                                                \\\n\t(BIT_MASK_WAKE_MAX_PLS_8821C << BIT_SHIFT_WAKE_MAX_PLS_8821C)\n#define BIT_CLEAR_WAKE_MAX_PLS_8821C(x) ((x) & (~BITS_WAKE_MAX_PLS_8821C))\n#define BIT_GET_WAKE_MAX_PLS_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MAX_PLS_8821C) & BIT_MASK_WAKE_MAX_PLS_8821C)\n#define BIT_SET_WAKE_MAX_PLS_8821C(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MAX_PLS_8821C(x) | BIT_WAKE_MAX_PLS_8821C(v))\n\n#define BIT_SHIFT_WAKE_MIN_PLS_8821C 16\n#define BIT_MASK_WAKE_MIN_PLS_8821C 0x7\n#define BIT_WAKE_MIN_PLS_8821C(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MIN_PLS_8821C) << BIT_SHIFT_WAKE_MIN_PLS_8821C)\n#define BITS_WAKE_MIN_PLS_8821C                                                \\\n\t(BIT_MASK_WAKE_MIN_PLS_8821C << BIT_SHIFT_WAKE_MIN_PLS_8821C)\n#define BIT_CLEAR_WAKE_MIN_PLS_8821C(x) ((x) & (~BITS_WAKE_MIN_PLS_8821C))\n#define BIT_GET_WAKE_MIN_PLS_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MIN_PLS_8821C) & BIT_MASK_WAKE_MIN_PLS_8821C)\n#define BIT_SET_WAKE_MIN_PLS_8821C(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MIN_PLS_8821C(x) | BIT_WAKE_MIN_PLS_8821C(v))\n\n#define BIT_SHIFT_WAKE_MAX_F2F_8821C 12\n#define BIT_MASK_WAKE_MAX_F2F_8821C 0x7\n#define BIT_WAKE_MAX_F2F_8821C(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MAX_F2F_8821C) << BIT_SHIFT_WAKE_MAX_F2F_8821C)\n#define BITS_WAKE_MAX_F2F_8821C                                                \\\n\t(BIT_MASK_WAKE_MAX_F2F_8821C << BIT_SHIFT_WAKE_MAX_F2F_8821C)\n#define BIT_CLEAR_WAKE_MAX_F2F_8821C(x) ((x) & (~BITS_WAKE_MAX_F2F_8821C))\n#define BIT_GET_WAKE_MAX_F2F_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MAX_F2F_8821C) & BIT_MASK_WAKE_MAX_F2F_8821C)\n#define BIT_SET_WAKE_MAX_F2F_8821C(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MAX_F2F_8821C(x) | BIT_WAKE_MAX_F2F_8821C(v))\n\n#define BIT_SHIFT_WAKE_MIN_F2F_8821C 8\n#define BIT_MASK_WAKE_MIN_F2F_8821C 0x7\n#define BIT_WAKE_MIN_F2F_8821C(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MIN_F2F_8821C) << BIT_SHIFT_WAKE_MIN_F2F_8821C)\n#define BITS_WAKE_MIN_F2F_8821C                                                \\\n\t(BIT_MASK_WAKE_MIN_F2F_8821C << BIT_SHIFT_WAKE_MIN_F2F_8821C)\n#define BIT_CLEAR_WAKE_MIN_F2F_8821C(x) ((x) & (~BITS_WAKE_MIN_F2F_8821C))\n#define BIT_GET_WAKE_MIN_F2F_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MIN_F2F_8821C) & BIT_MASK_WAKE_MIN_F2F_8821C)\n#define BIT_SET_WAKE_MIN_F2F_8821C(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MIN_F2F_8821C(x) | BIT_WAKE_MIN_F2F_8821C(v))\n\n#define BIT_APP_CPU_ACT_V1_8821C BIT(3)\n#define BIT_APP_OBFF_V1_8821C BIT(2)\n#define BIT_APP_IDLE_V1_8821C BIT(1)\n#define BIT_APP_INIT_V1_8821C BIT(0)\n\n/* 2 REG_OBFF_CTRL2_TIMER_8821C */\n\n#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C 24\n#define BIT_MASK_RX_HIGH_TIMER_IDX_8821C 0x7\n#define BIT_RX_HIGH_TIMER_IDX_8821C(x)                                         \\\n\t(((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8821C)                              \\\n\t << BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C)\n#define BITS_RX_HIGH_TIMER_IDX_8821C                                           \\\n\t(BIT_MASK_RX_HIGH_TIMER_IDX_8821C << BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C)\n#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8821C(x)                                   \\\n\t((x) & (~BITS_RX_HIGH_TIMER_IDX_8821C))\n#define BIT_GET_RX_HIGH_TIMER_IDX_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C) &                          \\\n\t BIT_MASK_RX_HIGH_TIMER_IDX_8821C)\n#define BIT_SET_RX_HIGH_TIMER_IDX_8821C(x, v)                                  \\\n\t(BIT_CLEAR_RX_HIGH_TIMER_IDX_8821C(x) | BIT_RX_HIGH_TIMER_IDX_8821C(v))\n\n#define BIT_SHIFT_RX_MED_TIMER_IDX_8821C 16\n#define BIT_MASK_RX_MED_TIMER_IDX_8821C 0x7\n#define BIT_RX_MED_TIMER_IDX_8821C(x)                                          \\\n\t(((x) & BIT_MASK_RX_MED_TIMER_IDX_8821C)                               \\\n\t << BIT_SHIFT_RX_MED_TIMER_IDX_8821C)\n#define BITS_RX_MED_TIMER_IDX_8821C                                            \\\n\t(BIT_MASK_RX_MED_TIMER_IDX_8821C << BIT_SHIFT_RX_MED_TIMER_IDX_8821C)\n#define BIT_CLEAR_RX_MED_TIMER_IDX_8821C(x)                                    \\\n\t((x) & (~BITS_RX_MED_TIMER_IDX_8821C))\n#define BIT_GET_RX_MED_TIMER_IDX_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8821C) &                           \\\n\t BIT_MASK_RX_MED_TIMER_IDX_8821C)\n#define BIT_SET_RX_MED_TIMER_IDX_8821C(x, v)                                   \\\n\t(BIT_CLEAR_RX_MED_TIMER_IDX_8821C(x) | BIT_RX_MED_TIMER_IDX_8821C(v))\n\n#define BIT_SHIFT_RX_LOW_TIMER_IDX_8821C 8\n#define BIT_MASK_RX_LOW_TIMER_IDX_8821C 0x7\n#define BIT_RX_LOW_TIMER_IDX_8821C(x)                                          \\\n\t(((x) & BIT_MASK_RX_LOW_TIMER_IDX_8821C)                               \\\n\t << BIT_SHIFT_RX_LOW_TIMER_IDX_8821C)\n#define BITS_RX_LOW_TIMER_IDX_8821C                                            \\\n\t(BIT_MASK_RX_LOW_TIMER_IDX_8821C << BIT_SHIFT_RX_LOW_TIMER_IDX_8821C)\n#define BIT_CLEAR_RX_LOW_TIMER_IDX_8821C(x)                                    \\\n\t((x) & (~BITS_RX_LOW_TIMER_IDX_8821C))\n#define BIT_GET_RX_LOW_TIMER_IDX_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) &                           \\\n\t BIT_MASK_RX_LOW_TIMER_IDX_8821C)\n#define BIT_SET_RX_LOW_TIMER_IDX_8821C(x, v)                                   \\\n\t(BIT_CLEAR_RX_LOW_TIMER_IDX_8821C(x) | BIT_RX_LOW_TIMER_IDX_8821C(v))\n\n#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C 0\n#define BIT_MASK_OBFF_INT_TIMER_IDX_8821C 0x7\n#define BIT_OBFF_INT_TIMER_IDX_8821C(x)                                        \\\n\t(((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8821C)                             \\\n\t << BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C)\n#define BITS_OBFF_INT_TIMER_IDX_8821C                                          \\\n\t(BIT_MASK_OBFF_INT_TIMER_IDX_8821C                                     \\\n\t << BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C)\n#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8821C(x)                                  \\\n\t((x) & (~BITS_OBFF_INT_TIMER_IDX_8821C))\n#define BIT_GET_OBFF_INT_TIMER_IDX_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) &                         \\\n\t BIT_MASK_OBFF_INT_TIMER_IDX_8821C)\n#define BIT_SET_OBFF_INT_TIMER_IDX_8821C(x, v)                                 \\\n\t(BIT_CLEAR_OBFF_INT_TIMER_IDX_8821C(x) |                               \\\n\t BIT_OBFF_INT_TIMER_IDX_8821C(v))\n\n/* 2 REG_LTR_CTRL_BASIC_8821C */\n#define BIT_LTR_EN_V1_8821C BIT(31)\n#define BIT_LTR_HW_EN_V1_8821C BIT(30)\n#define BIT_LRT_ACT_CTS_EN_8821C BIT(29)\n#define BIT_LTR_ACT_RXPKT_EN_8821C BIT(28)\n#define BIT_LTR_ACT_RXDMA_EN_8821C BIT(27)\n#define BIT_LTR_IDLE_NO_SNOOP_8821C BIT(26)\n#define BIT_SPDUP_MGTPKT_8821C BIT(25)\n#define BIT_RX_AGG_EN_8821C BIT(24)\n#define BIT_APP_LTR_ACT_8821C BIT(23)\n#define BIT_APP_LTR_IDLE_8821C BIT(22)\n\n#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C 20\n#define BIT_MASK_HIGH_RATE_TRIG_SEL_8821C 0x3\n#define BIT_HIGH_RATE_TRIG_SEL_8821C(x)                                        \\\n\t(((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8821C)                             \\\n\t << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C)\n#define BITS_HIGH_RATE_TRIG_SEL_8821C                                          \\\n\t(BIT_MASK_HIGH_RATE_TRIG_SEL_8821C                                     \\\n\t << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C)\n#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8821C(x)                                  \\\n\t((x) & (~BITS_HIGH_RATE_TRIG_SEL_8821C))\n#define BIT_GET_HIGH_RATE_TRIG_SEL_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C) &                         \\\n\t BIT_MASK_HIGH_RATE_TRIG_SEL_8821C)\n#define BIT_SET_HIGH_RATE_TRIG_SEL_8821C(x, v)                                 \\\n\t(BIT_CLEAR_HIGH_RATE_TRIG_SEL_8821C(x) |                               \\\n\t BIT_HIGH_RATE_TRIG_SEL_8821C(v))\n\n#define BIT_SHIFT_MED_RATE_TRIG_SEL_8821C 18\n#define BIT_MASK_MED_RATE_TRIG_SEL_8821C 0x3\n#define BIT_MED_RATE_TRIG_SEL_8821C(x)                                         \\\n\t(((x) & BIT_MASK_MED_RATE_TRIG_SEL_8821C)                              \\\n\t << BIT_SHIFT_MED_RATE_TRIG_SEL_8821C)\n#define BITS_MED_RATE_TRIG_SEL_8821C                                           \\\n\t(BIT_MASK_MED_RATE_TRIG_SEL_8821C << BIT_SHIFT_MED_RATE_TRIG_SEL_8821C)\n#define BIT_CLEAR_MED_RATE_TRIG_SEL_8821C(x)                                   \\\n\t((x) & (~BITS_MED_RATE_TRIG_SEL_8821C))\n#define BIT_GET_MED_RATE_TRIG_SEL_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) &                          \\\n\t BIT_MASK_MED_RATE_TRIG_SEL_8821C)\n#define BIT_SET_MED_RATE_TRIG_SEL_8821C(x, v)                                  \\\n\t(BIT_CLEAR_MED_RATE_TRIG_SEL_8821C(x) | BIT_MED_RATE_TRIG_SEL_8821C(v))\n\n#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C 16\n#define BIT_MASK_LOW_RATE_TRIG_SEL_8821C 0x3\n#define BIT_LOW_RATE_TRIG_SEL_8821C(x)                                         \\\n\t(((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8821C)                              \\\n\t << BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C)\n#define BITS_LOW_RATE_TRIG_SEL_8821C                                           \\\n\t(BIT_MASK_LOW_RATE_TRIG_SEL_8821C << BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C)\n#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8821C(x)                                   \\\n\t((x) & (~BITS_LOW_RATE_TRIG_SEL_8821C))\n#define BIT_GET_LOW_RATE_TRIG_SEL_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) &                          \\\n\t BIT_MASK_LOW_RATE_TRIG_SEL_8821C)\n#define BIT_SET_LOW_RATE_TRIG_SEL_8821C(x, v)                                  \\\n\t(BIT_CLEAR_LOW_RATE_TRIG_SEL_8821C(x) | BIT_LOW_RATE_TRIG_SEL_8821C(v))\n\n#define BIT_SHIFT_HIGH_RATE_BD_IDX_8821C 8\n#define BIT_MASK_HIGH_RATE_BD_IDX_8821C 0x7f\n#define BIT_HIGH_RATE_BD_IDX_8821C(x)                                          \\\n\t(((x) & BIT_MASK_HIGH_RATE_BD_IDX_8821C)                               \\\n\t << BIT_SHIFT_HIGH_RATE_BD_IDX_8821C)\n#define BITS_HIGH_RATE_BD_IDX_8821C                                            \\\n\t(BIT_MASK_HIGH_RATE_BD_IDX_8821C << BIT_SHIFT_HIGH_RATE_BD_IDX_8821C)\n#define BIT_CLEAR_HIGH_RATE_BD_IDX_8821C(x)                                    \\\n\t((x) & (~BITS_HIGH_RATE_BD_IDX_8821C))\n#define BIT_GET_HIGH_RATE_BD_IDX_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) &                           \\\n\t BIT_MASK_HIGH_RATE_BD_IDX_8821C)\n#define BIT_SET_HIGH_RATE_BD_IDX_8821C(x, v)                                   \\\n\t(BIT_CLEAR_HIGH_RATE_BD_IDX_8821C(x) | BIT_HIGH_RATE_BD_IDX_8821C(v))\n\n#define BIT_SHIFT_LOW_RATE_BD_IDX_8821C 0\n#define BIT_MASK_LOW_RATE_BD_IDX_8821C 0x7f\n#define BIT_LOW_RATE_BD_IDX_8821C(x)                                           \\\n\t(((x) & BIT_MASK_LOW_RATE_BD_IDX_8821C)                                \\\n\t << BIT_SHIFT_LOW_RATE_BD_IDX_8821C)\n#define BITS_LOW_RATE_BD_IDX_8821C                                             \\\n\t(BIT_MASK_LOW_RATE_BD_IDX_8821C << BIT_SHIFT_LOW_RATE_BD_IDX_8821C)\n#define BIT_CLEAR_LOW_RATE_BD_IDX_8821C(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8821C))\n#define BIT_GET_LOW_RATE_BD_IDX_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8821C) &                            \\\n\t BIT_MASK_LOW_RATE_BD_IDX_8821C)\n#define BIT_SET_LOW_RATE_BD_IDX_8821C(x, v)                                    \\\n\t(BIT_CLEAR_LOW_RATE_BD_IDX_8821C(x) | BIT_LOW_RATE_BD_IDX_8821C(v))\n\n/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8821C */\n\n#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C 24\n#define BIT_MASK_RX_EMPTY_TIMER_IDX_8821C 0x7\n#define BIT_RX_EMPTY_TIMER_IDX_8821C(x)                                        \\\n\t(((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8821C)                             \\\n\t << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C)\n#define BITS_RX_EMPTY_TIMER_IDX_8821C                                          \\\n\t(BIT_MASK_RX_EMPTY_TIMER_IDX_8821C                                     \\\n\t << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C)\n#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8821C(x)                                  \\\n\t((x) & (~BITS_RX_EMPTY_TIMER_IDX_8821C))\n#define BIT_GET_RX_EMPTY_TIMER_IDX_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C) &                         \\\n\t BIT_MASK_RX_EMPTY_TIMER_IDX_8821C)\n#define BIT_SET_RX_EMPTY_TIMER_IDX_8821C(x, v)                                 \\\n\t(BIT_CLEAR_RX_EMPTY_TIMER_IDX_8821C(x) |                               \\\n\t BIT_RX_EMPTY_TIMER_IDX_8821C(v))\n\n#define BIT_SHIFT_RX_AFULL_TH_IDX_8821C 20\n#define BIT_MASK_RX_AFULL_TH_IDX_8821C 0x7\n#define BIT_RX_AFULL_TH_IDX_8821C(x)                                           \\\n\t(((x) & BIT_MASK_RX_AFULL_TH_IDX_8821C)                                \\\n\t << BIT_SHIFT_RX_AFULL_TH_IDX_8821C)\n#define BITS_RX_AFULL_TH_IDX_8821C                                             \\\n\t(BIT_MASK_RX_AFULL_TH_IDX_8821C << BIT_SHIFT_RX_AFULL_TH_IDX_8821C)\n#define BIT_CLEAR_RX_AFULL_TH_IDX_8821C(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8821C))\n#define BIT_GET_RX_AFULL_TH_IDX_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8821C) &                            \\\n\t BIT_MASK_RX_AFULL_TH_IDX_8821C)\n#define BIT_SET_RX_AFULL_TH_IDX_8821C(x, v)                                    \\\n\t(BIT_CLEAR_RX_AFULL_TH_IDX_8821C(x) | BIT_RX_AFULL_TH_IDX_8821C(v))\n\n#define BIT_SHIFT_RX_HIGH_TH_IDX_8821C 16\n#define BIT_MASK_RX_HIGH_TH_IDX_8821C 0x7\n#define BIT_RX_HIGH_TH_IDX_8821C(x)                                            \\\n\t(((x) & BIT_MASK_RX_HIGH_TH_IDX_8821C)                                 \\\n\t << BIT_SHIFT_RX_HIGH_TH_IDX_8821C)\n#define BITS_RX_HIGH_TH_IDX_8821C                                              \\\n\t(BIT_MASK_RX_HIGH_TH_IDX_8821C << BIT_SHIFT_RX_HIGH_TH_IDX_8821C)\n#define BIT_CLEAR_RX_HIGH_TH_IDX_8821C(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8821C))\n#define BIT_GET_RX_HIGH_TH_IDX_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8821C) &                             \\\n\t BIT_MASK_RX_HIGH_TH_IDX_8821C)\n#define BIT_SET_RX_HIGH_TH_IDX_8821C(x, v)                                     \\\n\t(BIT_CLEAR_RX_HIGH_TH_IDX_8821C(x) | BIT_RX_HIGH_TH_IDX_8821C(v))\n\n#define BIT_SHIFT_RX_MED_TH_IDX_8821C 12\n#define BIT_MASK_RX_MED_TH_IDX_8821C 0x7\n#define BIT_RX_MED_TH_IDX_8821C(x)                                             \\\n\t(((x) & BIT_MASK_RX_MED_TH_IDX_8821C) << BIT_SHIFT_RX_MED_TH_IDX_8821C)\n#define BITS_RX_MED_TH_IDX_8821C                                               \\\n\t(BIT_MASK_RX_MED_TH_IDX_8821C << BIT_SHIFT_RX_MED_TH_IDX_8821C)\n#define BIT_CLEAR_RX_MED_TH_IDX_8821C(x) ((x) & (~BITS_RX_MED_TH_IDX_8821C))\n#define BIT_GET_RX_MED_TH_IDX_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_RX_MED_TH_IDX_8821C) & BIT_MASK_RX_MED_TH_IDX_8821C)\n#define BIT_SET_RX_MED_TH_IDX_8821C(x, v)                                      \\\n\t(BIT_CLEAR_RX_MED_TH_IDX_8821C(x) | BIT_RX_MED_TH_IDX_8821C(v))\n\n#define BIT_SHIFT_RX_LOW_TH_IDX_8821C 8\n#define BIT_MASK_RX_LOW_TH_IDX_8821C 0x7\n#define BIT_RX_LOW_TH_IDX_8821C(x)                                             \\\n\t(((x) & BIT_MASK_RX_LOW_TH_IDX_8821C) << BIT_SHIFT_RX_LOW_TH_IDX_8821C)\n#define BITS_RX_LOW_TH_IDX_8821C                                               \\\n\t(BIT_MASK_RX_LOW_TH_IDX_8821C << BIT_SHIFT_RX_LOW_TH_IDX_8821C)\n#define BIT_CLEAR_RX_LOW_TH_IDX_8821C(x) ((x) & (~BITS_RX_LOW_TH_IDX_8821C))\n#define BIT_GET_RX_LOW_TH_IDX_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8821C) & BIT_MASK_RX_LOW_TH_IDX_8821C)\n#define BIT_SET_RX_LOW_TH_IDX_8821C(x, v)                                      \\\n\t(BIT_CLEAR_RX_LOW_TH_IDX_8821C(x) | BIT_RX_LOW_TH_IDX_8821C(v))\n\n#define BIT_SHIFT_LTR_SPACE_IDX_8821C 4\n#define BIT_MASK_LTR_SPACE_IDX_8821C 0x3\n#define BIT_LTR_SPACE_IDX_8821C(x)                                             \\\n\t(((x) & BIT_MASK_LTR_SPACE_IDX_8821C) << BIT_SHIFT_LTR_SPACE_IDX_8821C)\n#define BITS_LTR_SPACE_IDX_8821C                                               \\\n\t(BIT_MASK_LTR_SPACE_IDX_8821C << BIT_SHIFT_LTR_SPACE_IDX_8821C)\n#define BIT_CLEAR_LTR_SPACE_IDX_8821C(x) ((x) & (~BITS_LTR_SPACE_IDX_8821C))\n#define BIT_GET_LTR_SPACE_IDX_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_LTR_SPACE_IDX_8821C) & BIT_MASK_LTR_SPACE_IDX_8821C)\n#define BIT_SET_LTR_SPACE_IDX_8821C(x, v)                                      \\\n\t(BIT_CLEAR_LTR_SPACE_IDX_8821C(x) | BIT_LTR_SPACE_IDX_8821C(v))\n\n#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C 0\n#define BIT_MASK_LTR_IDLE_TIMER_IDX_8821C 0x7\n#define BIT_LTR_IDLE_TIMER_IDX_8821C(x)                                        \\\n\t(((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8821C)                             \\\n\t << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C)\n#define BITS_LTR_IDLE_TIMER_IDX_8821C                                          \\\n\t(BIT_MASK_LTR_IDLE_TIMER_IDX_8821C                                     \\\n\t << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C)\n#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8821C(x)                                  \\\n\t((x) & (~BITS_LTR_IDLE_TIMER_IDX_8821C))\n#define BIT_GET_LTR_IDLE_TIMER_IDX_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) &                         \\\n\t BIT_MASK_LTR_IDLE_TIMER_IDX_8821C)\n#define BIT_SET_LTR_IDLE_TIMER_IDX_8821C(x, v)                                 \\\n\t(BIT_CLEAR_LTR_IDLE_TIMER_IDX_8821C(x) |                               \\\n\t BIT_LTR_IDLE_TIMER_IDX_8821C(v))\n\n/* 2 REG_LTR_IDLE_LATENCY_V1_8821C */\n\n#define BIT_SHIFT_LTR_IDLE_L_8821C 0\n#define BIT_MASK_LTR_IDLE_L_8821C 0xffffffffL\n#define BIT_LTR_IDLE_L_8821C(x)                                                \\\n\t(((x) & BIT_MASK_LTR_IDLE_L_8821C) << BIT_SHIFT_LTR_IDLE_L_8821C)\n#define BITS_LTR_IDLE_L_8821C                                                  \\\n\t(BIT_MASK_LTR_IDLE_L_8821C << BIT_SHIFT_LTR_IDLE_L_8821C)\n#define BIT_CLEAR_LTR_IDLE_L_8821C(x) ((x) & (~BITS_LTR_IDLE_L_8821C))\n#define BIT_GET_LTR_IDLE_L_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_LTR_IDLE_L_8821C) & BIT_MASK_LTR_IDLE_L_8821C)\n#define BIT_SET_LTR_IDLE_L_8821C(x, v)                                         \\\n\t(BIT_CLEAR_LTR_IDLE_L_8821C(x) | BIT_LTR_IDLE_L_8821C(v))\n\n/* 2 REG_LTR_ACTIVE_LATENCY_V1_8821C */\n\n#define BIT_SHIFT_LTR_ACT_L_8821C 0\n#define BIT_MASK_LTR_ACT_L_8821C 0xffffffffL\n#define BIT_LTR_ACT_L_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_LTR_ACT_L_8821C) << BIT_SHIFT_LTR_ACT_L_8821C)\n#define BITS_LTR_ACT_L_8821C                                                   \\\n\t(BIT_MASK_LTR_ACT_L_8821C << BIT_SHIFT_LTR_ACT_L_8821C)\n#define BIT_CLEAR_LTR_ACT_L_8821C(x) ((x) & (~BITS_LTR_ACT_L_8821C))\n#define BIT_GET_LTR_ACT_L_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_LTR_ACT_L_8821C) & BIT_MASK_LTR_ACT_L_8821C)\n#define BIT_SET_LTR_ACT_L_8821C(x, v)                                          \\\n\t(BIT_CLEAR_LTR_ACT_L_8821C(x) | BIT_LTR_ACT_L_8821C(v))\n\n/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8821C */\n\n#define BIT_SHIFT_TRAIN_STA_ADDR_0_8821C 0\n#define BIT_MASK_TRAIN_STA_ADDR_0_8821C 0xffffffffL\n#define BIT_TRAIN_STA_ADDR_0_8821C(x)                                          \\\n\t(((x) & BIT_MASK_TRAIN_STA_ADDR_0_8821C)                               \\\n\t << BIT_SHIFT_TRAIN_STA_ADDR_0_8821C)\n#define BITS_TRAIN_STA_ADDR_0_8821C                                            \\\n\t(BIT_MASK_TRAIN_STA_ADDR_0_8821C << BIT_SHIFT_TRAIN_STA_ADDR_0_8821C)\n#define BIT_CLEAR_TRAIN_STA_ADDR_0_8821C(x)                                    \\\n\t((x) & (~BITS_TRAIN_STA_ADDR_0_8821C))\n#define BIT_GET_TRAIN_STA_ADDR_0_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0_8821C) &                           \\\n\t BIT_MASK_TRAIN_STA_ADDR_0_8821C)\n#define BIT_SET_TRAIN_STA_ADDR_0_8821C(x, v)                                   \\\n\t(BIT_CLEAR_TRAIN_STA_ADDR_0_8821C(x) | BIT_TRAIN_STA_ADDR_0_8821C(v))\n\n/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8821C */\n#define BIT_APPEND_MACID_IN_RESP_EN_1_8821C BIT(18)\n#define BIT_ADDR2_MATCH_EN_1_8821C BIT(17)\n#define BIT_ANTTRN_EN_1_8821C BIT(16)\n\n#define BIT_SHIFT_TRAIN_STA_ADDR_1_8821C 0\n#define BIT_MASK_TRAIN_STA_ADDR_1_8821C 0xffff\n#define BIT_TRAIN_STA_ADDR_1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_TRAIN_STA_ADDR_1_8821C)                               \\\n\t << BIT_SHIFT_TRAIN_STA_ADDR_1_8821C)\n#define BITS_TRAIN_STA_ADDR_1_8821C                                            \\\n\t(BIT_MASK_TRAIN_STA_ADDR_1_8821C << BIT_SHIFT_TRAIN_STA_ADDR_1_8821C)\n#define BIT_CLEAR_TRAIN_STA_ADDR_1_8821C(x)                                    \\\n\t((x) & (~BITS_TRAIN_STA_ADDR_1_8821C))\n#define BIT_GET_TRAIN_STA_ADDR_1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1_8821C) &                           \\\n\t BIT_MASK_TRAIN_STA_ADDR_1_8821C)\n#define BIT_SET_TRAIN_STA_ADDR_1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_TRAIN_STA_ADDR_1_8821C(x) | BIT_TRAIN_STA_ADDR_1_8821C(v))\n\n/* 2 REG_WMAC_PKTCNT_RWD_8821C */\n\n#define BIT_SHIFT_PKTCNT_BSSIDMAP_8821C 4\n#define BIT_MASK_PKTCNT_BSSIDMAP_8821C 0xf\n#define BIT_PKTCNT_BSSIDMAP_8821C(x)                                           \\\n\t(((x) & BIT_MASK_PKTCNT_BSSIDMAP_8821C)                                \\\n\t << BIT_SHIFT_PKTCNT_BSSIDMAP_8821C)\n#define BITS_PKTCNT_BSSIDMAP_8821C                                             \\\n\t(BIT_MASK_PKTCNT_BSSIDMAP_8821C << BIT_SHIFT_PKTCNT_BSSIDMAP_8821C)\n#define BIT_CLEAR_PKTCNT_BSSIDMAP_8821C(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8821C))\n#define BIT_GET_PKTCNT_BSSIDMAP_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) &                            \\\n\t BIT_MASK_PKTCNT_BSSIDMAP_8821C)\n#define BIT_SET_PKTCNT_BSSIDMAP_8821C(x, v)                                    \\\n\t(BIT_CLEAR_PKTCNT_BSSIDMAP_8821C(x) | BIT_PKTCNT_BSSIDMAP_8821C(v))\n\n#define BIT_PKTCNT_CNTRST_8821C BIT(1)\n#define BIT_PKTCNT_CNTEN_8821C BIT(0)\n\n/* 2 REG_WMAC_PKTCNT_CTRL_8821C */\n#define BIT_WMAC_PKTCNT_TRST_8821C BIT(9)\n#define BIT_WMAC_PKTCNT_FEN_8821C BIT(8)\n\n#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C 0\n#define BIT_MASK_WMAC_PKTCNT_CFGAD_8821C 0xff\n#define BIT_WMAC_PKTCNT_CFGAD_8821C(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8821C)                              \\\n\t << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C)\n#define BITS_WMAC_PKTCNT_CFGAD_8821C                                           \\\n\t(BIT_MASK_WMAC_PKTCNT_CFGAD_8821C << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C)\n#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8821C(x)                                   \\\n\t((x) & (~BITS_WMAC_PKTCNT_CFGAD_8821C))\n#define BIT_GET_WMAC_PKTCNT_CFGAD_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C) &                          \\\n\t BIT_MASK_WMAC_PKTCNT_CFGAD_8821C)\n#define BIT_SET_WMAC_PKTCNT_CFGAD_8821C(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_PKTCNT_CFGAD_8821C(x) | BIT_WMAC_PKTCNT_CFGAD_8821C(v))\n\n/* 2 REG_IQ_DUMP_8821C */\n\n#define BIT_SHIFT_DUMP_OK_ADDR_8821C 16\n#define BIT_MASK_DUMP_OK_ADDR_8821C 0xffff\n#define BIT_DUMP_OK_ADDR_8821C(x)                                              \\\n\t(((x) & BIT_MASK_DUMP_OK_ADDR_8821C) << BIT_SHIFT_DUMP_OK_ADDR_8821C)\n#define BITS_DUMP_OK_ADDR_8821C                                                \\\n\t(BIT_MASK_DUMP_OK_ADDR_8821C << BIT_SHIFT_DUMP_OK_ADDR_8821C)\n#define BIT_CLEAR_DUMP_OK_ADDR_8821C(x) ((x) & (~BITS_DUMP_OK_ADDR_8821C))\n#define BIT_GET_DUMP_OK_ADDR_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DUMP_OK_ADDR_8821C) & BIT_MASK_DUMP_OK_ADDR_8821C)\n#define BIT_SET_DUMP_OK_ADDR_8821C(x, v)                                       \\\n\t(BIT_CLEAR_DUMP_OK_ADDR_8821C(x) | BIT_DUMP_OK_ADDR_8821C(v))\n\n#define BIT_SHIFT_R_TRIG_TIME_SEL_8821C 8\n#define BIT_MASK_R_TRIG_TIME_SEL_8821C 0x7f\n#define BIT_R_TRIG_TIME_SEL_8821C(x)                                           \\\n\t(((x) & BIT_MASK_R_TRIG_TIME_SEL_8821C)                                \\\n\t << BIT_SHIFT_R_TRIG_TIME_SEL_8821C)\n#define BITS_R_TRIG_TIME_SEL_8821C                                             \\\n\t(BIT_MASK_R_TRIG_TIME_SEL_8821C << BIT_SHIFT_R_TRIG_TIME_SEL_8821C)\n#define BIT_CLEAR_R_TRIG_TIME_SEL_8821C(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8821C))\n#define BIT_GET_R_TRIG_TIME_SEL_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8821C) &                            \\\n\t BIT_MASK_R_TRIG_TIME_SEL_8821C)\n#define BIT_SET_R_TRIG_TIME_SEL_8821C(x, v)                                    \\\n\t(BIT_CLEAR_R_TRIG_TIME_SEL_8821C(x) | BIT_R_TRIG_TIME_SEL_8821C(v))\n\n#define BIT_SHIFT_R_MAC_TRIG_SEL_8821C 6\n#define BIT_MASK_R_MAC_TRIG_SEL_8821C 0x3\n#define BIT_R_MAC_TRIG_SEL_8821C(x)                                            \\\n\t(((x) & BIT_MASK_R_MAC_TRIG_SEL_8821C)                                 \\\n\t << BIT_SHIFT_R_MAC_TRIG_SEL_8821C)\n#define BITS_R_MAC_TRIG_SEL_8821C                                              \\\n\t(BIT_MASK_R_MAC_TRIG_SEL_8821C << BIT_SHIFT_R_MAC_TRIG_SEL_8821C)\n#define BIT_CLEAR_R_MAC_TRIG_SEL_8821C(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8821C))\n#define BIT_GET_R_MAC_TRIG_SEL_8821C(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8821C) &                             \\\n\t BIT_MASK_R_MAC_TRIG_SEL_8821C)\n#define BIT_SET_R_MAC_TRIG_SEL_8821C(x, v)                                     \\\n\t(BIT_CLEAR_R_MAC_TRIG_SEL_8821C(x) | BIT_R_MAC_TRIG_SEL_8821C(v))\n\n#define BIT_MAC_TRIG_REG_8821C BIT(5)\n\n#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C 3\n#define BIT_MASK_R_LEVEL_PULSE_SEL_8821C 0x3\n#define BIT_R_LEVEL_PULSE_SEL_8821C(x)                                         \\\n\t(((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8821C)                              \\\n\t << BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C)\n#define BITS_R_LEVEL_PULSE_SEL_8821C                                           \\\n\t(BIT_MASK_R_LEVEL_PULSE_SEL_8821C << BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C)\n#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8821C(x)                                   \\\n\t((x) & (~BITS_R_LEVEL_PULSE_SEL_8821C))\n#define BIT_GET_R_LEVEL_PULSE_SEL_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) &                          \\\n\t BIT_MASK_R_LEVEL_PULSE_SEL_8821C)\n#define BIT_SET_R_LEVEL_PULSE_SEL_8821C(x, v)                                  \\\n\t(BIT_CLEAR_R_LEVEL_PULSE_SEL_8821C(x) | BIT_R_LEVEL_PULSE_SEL_8821C(v))\n\n#define BIT_EN_LA_MAC_8821C BIT(2)\n#define BIT_R_EN_IQDUMP_8821C BIT(1)\n#define BIT_R_IQDATA_DUMP_8821C BIT(0)\n\n/* 2 REG_IQ_DUMP_1_8821C */\n\n#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C 0\n#define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C 0xffffffffL\n#define BIT_R_WMAC_MASK_LA_MAC_1_8821C(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C)                           \\\n\t << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C)\n#define BITS_R_WMAC_MASK_LA_MAC_1_8821C                                        \\\n\t(BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C                                   \\\n\t << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C)\n#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8821C(x)                                \\\n\t((x) & (~BITS_R_WMAC_MASK_LA_MAC_1_8821C))\n#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C) &                       \\\n\t BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C)\n#define BIT_SET_R_WMAC_MASK_LA_MAC_1_8821C(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8821C(x) |                             \\\n\t BIT_R_WMAC_MASK_LA_MAC_1_8821C(v))\n\n/* 2 REG_IQ_DUMP_2_8821C */\n\n#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C 0\n#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C 0xffffffffL\n#define BIT_R_WMAC_MATCH_REF_MAC_2_8821C(x)                                    \\\n\t(((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C)                         \\\n\t << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C)\n#define BITS_R_WMAC_MATCH_REF_MAC_2_8821C                                      \\\n\t(BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C                                 \\\n\t << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C)\n#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8821C(x)                              \\\n\t((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2_8821C))\n#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8821C(x)                                \\\n\t(((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C) &                     \\\n\t BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C)\n#define BIT_SET_R_WMAC_MATCH_REF_MAC_2_8821C(x, v)                             \\\n\t(BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8821C(x) |                           \\\n\t BIT_R_WMAC_MATCH_REF_MAC_2_8821C(v))\n\n/* 2 REG_WMAC_FTM_CTL_8821C */\n#define BIT_RXFTM_TXACK_SC_8821C BIT(6)\n#define BIT_RXFTM_TXACK_BW_8821C BIT(5)\n#define BIT_RXFTM_EN_8821C BIT(3)\n#define BIT_RXFTMREQ_BYDRV_8821C BIT(2)\n#define BIT_RXFTMREQ_EN_8821C BIT(1)\n#define BIT_FTM_EN_8821C BIT(0)\n\n/* 2 REG_WMAC_IQ_MDPK_FUNC_8821C */\n\n/* 2 REG_WMAC_OPTION_FUNCTION_8821C */\n\n#define BIT_SHIFT_R_OFDM_LEN_8821C 26\n#define BIT_MASK_R_OFDM_LEN_8821C 0x3f\n#define BIT_R_OFDM_LEN_8821C(x)                                                \\\n\t(((x) & BIT_MASK_R_OFDM_LEN_8821C) << BIT_SHIFT_R_OFDM_LEN_8821C)\n#define BITS_R_OFDM_LEN_8821C                                                  \\\n\t(BIT_MASK_R_OFDM_LEN_8821C << BIT_SHIFT_R_OFDM_LEN_8821C)\n#define BIT_CLEAR_R_OFDM_LEN_8821C(x) ((x) & (~BITS_R_OFDM_LEN_8821C))\n#define BIT_GET_R_OFDM_LEN_8821C(x)                                            \\\n\t(((x) >> BIT_SHIFT_R_OFDM_LEN_8821C) & BIT_MASK_R_OFDM_LEN_8821C)\n#define BIT_SET_R_OFDM_LEN_8821C(x, v)                                         \\\n\t(BIT_CLEAR_R_OFDM_LEN_8821C(x) | BIT_R_OFDM_LEN_8821C(v))\n\n#define BIT_SHIFT_R_CCK_LEN_8821C 0\n#define BIT_MASK_R_CCK_LEN_8821C 0xffff\n#define BIT_R_CCK_LEN_8821C(x)                                                 \\\n\t(((x) & BIT_MASK_R_CCK_LEN_8821C) << BIT_SHIFT_R_CCK_LEN_8821C)\n#define BITS_R_CCK_LEN_8821C                                                   \\\n\t(BIT_MASK_R_CCK_LEN_8821C << BIT_SHIFT_R_CCK_LEN_8821C)\n#define BIT_CLEAR_R_CCK_LEN_8821C(x) ((x) & (~BITS_R_CCK_LEN_8821C))\n#define BIT_GET_R_CCK_LEN_8821C(x)                                             \\\n\t(((x) >> BIT_SHIFT_R_CCK_LEN_8821C) & BIT_MASK_R_CCK_LEN_8821C)\n#define BIT_SET_R_CCK_LEN_8821C(x, v)                                          \\\n\t(BIT_CLEAR_R_CCK_LEN_8821C(x) | BIT_R_CCK_LEN_8821C(v))\n\n/* 2 REG_WMAC_OPTION_FUNCTION_1_8821C */\n\n#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C 24\n#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C 0xff\n#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8821C(x)                                   \\\n\t(((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C)                        \\\n\t << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C)\n#define BITS_R_WMAC_RXFIFO_FULL_TH_1_8821C                                     \\\n\t(BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C                                \\\n\t << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C)\n#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8821C(x)                             \\\n\t((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1_8821C))\n#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8821C(x)                               \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C) &                    \\\n\t BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C)\n#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1_8821C(x, v)                            \\\n\t(BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) |                          \\\n\t BIT_R_WMAC_RXFIFO_FULL_TH_1_8821C(v))\n\n#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8821C BIT(23)\n#define BIT_R_WMAC_RXRST_DLY_1_8821C BIT(22)\n#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1_8821C BIT(21)\n#define BIT_R_WMAC_SRCH_TXRPT_UA1_1_8821C BIT(20)\n#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1_8821C BIT(19)\n#define BIT_R_WMAC_NDP_RST_1_8821C BIT(18)\n#define BIT_R_WMAC_POWINT_EN_1_8821C BIT(17)\n#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1_8821C BIT(16)\n#define BIT_R_WMAC_SRCH_TXRPT_MID_1_8821C BIT(15)\n#define BIT_R_WMAC_PFIN_TOEN_1_8821C BIT(14)\n#define BIT_R_WMAC_FIL_SECERR_1_8821C BIT(13)\n#define BIT_R_WMAC_FIL_CTLPKTLEN_1_8821C BIT(12)\n#define BIT_R_WMAC_FIL_FCTYPE_1_8821C BIT(11)\n#define BIT_R_WMAC_FIL_FCPROVER_1_8821C BIT(10)\n#define BIT_R_WMAC_PHYSTS_SNIF_1_8821C BIT(9)\n#define BIT_R_WMAC_PHYSTS_PLCP_1_8821C BIT(8)\n#define BIT_R_MAC_TCR_VBONF_RD_1_8821C BIT(7)\n#define BIT_R_WMAC_TCR_MPAR_NDP_1_8821C BIT(6)\n#define BIT_R_WMAC_NDP_FILTER_1_8821C BIT(5)\n#define BIT_R_WMAC_RXLEN_SEL_1_8821C BIT(4)\n#define BIT_R_WMAC_RXLEN_SEL1_1_8821C BIT(3)\n#define BIT_R_OFDM_FILTER_1_8821C BIT(2)\n#define BIT_R_WMAC_CHK_OFDM_LEN_1_8821C BIT(1)\n#define BIT_R_WMAC_CHK_CCK_LEN_1_8821C BIT(0)\n\n/* 2 REG_WMAC_OPTION_FUNCTION_2_8821C */\n\n#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C 0\n#define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C 0xffff\n#define BIT_R_WMAC_RX_FIL_LEN_2_8821C(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C)                            \\\n\t << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C)\n#define BITS_R_WMAC_RX_FIL_LEN_2_8821C                                         \\\n\t(BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C                                    \\\n\t << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C)\n#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8821C(x)                                 \\\n\t((x) & (~BITS_R_WMAC_RX_FIL_LEN_2_8821C))\n#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C) &                        \\\n\t BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C)\n#define BIT_SET_R_WMAC_RX_FIL_LEN_2_8821C(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8821C(x) |                              \\\n\t BIT_R_WMAC_RX_FIL_LEN_2_8821C(v))\n\n/* 2 REG_RX_FILTER_FUNCTION_8821C */\n#define BIT_R_WMAC_MHRDDY_LATCH_8821C BIT(14)\n#define BIT_R_WMAC_MHRDDY_CLR_8821C BIT(13)\n#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8821C BIT(12)\n#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU_8821C BIT(11)\n#define BIT_R_CHK_DELIMIT_LEN_8821C BIT(10)\n#define BIT_R_REAPTER_ADDR_MATCH_8821C BIT(9)\n#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8821C BIT(8)\n#define BIT_R_LATCH_MACHRDY_8821C BIT(7)\n#define BIT_R_WMAC_RXFIL_REND_8821C BIT(6)\n#define BIT_R_WMAC_MPDURDY_CLR_8821C BIT(5)\n#define BIT_R_WMAC_CLRRXSEC_8821C BIT(4)\n#define BIT_R_WMAC_RXFIL_RDEL_8821C BIT(3)\n#define BIT_R_WMAC_RXFIL_FCSE_8821C BIT(2)\n#define BIT_R_WMAC_RXFIL_MESH_DEL_8821C BIT(1)\n#define BIT_R_WMAC_RXFIL_MASKM_8821C BIT(0)\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NDP_SIG_8821C */\n\n#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C 0\n#define BIT_MASK_R_WMAC_TXNDP_SIGB_8821C 0x1fffff\n#define BIT_R_WMAC_TXNDP_SIGB_8821C(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8821C)                              \\\n\t << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C)\n#define BITS_R_WMAC_TXNDP_SIGB_8821C                                           \\\n\t(BIT_MASK_R_WMAC_TXNDP_SIGB_8821C << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C)\n#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8821C(x)                                   \\\n\t((x) & (~BITS_R_WMAC_TXNDP_SIGB_8821C))\n#define BIT_GET_R_WMAC_TXNDP_SIGB_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C) &                          \\\n\t BIT_MASK_R_WMAC_TXNDP_SIGB_8821C)\n#define BIT_SET_R_WMAC_TXNDP_SIGB_8821C(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_TXNDP_SIGB_8821C(x) | BIT_R_WMAC_TXNDP_SIGB_8821C(v))\n\n/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8821C */\n\n#define BIT_SHIFT_R_MAC_DBG_SHIFT_8821C 8\n#define BIT_MASK_R_MAC_DBG_SHIFT_8821C 0x7\n#define BIT_R_MAC_DBG_SHIFT_8821C(x)                                           \\\n\t(((x) & BIT_MASK_R_MAC_DBG_SHIFT_8821C)                                \\\n\t << BIT_SHIFT_R_MAC_DBG_SHIFT_8821C)\n#define BITS_R_MAC_DBG_SHIFT_8821C                                             \\\n\t(BIT_MASK_R_MAC_DBG_SHIFT_8821C << BIT_SHIFT_R_MAC_DBG_SHIFT_8821C)\n#define BIT_CLEAR_R_MAC_DBG_SHIFT_8821C(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8821C))\n#define BIT_GET_R_MAC_DBG_SHIFT_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8821C) &                            \\\n\t BIT_MASK_R_MAC_DBG_SHIFT_8821C)\n#define BIT_SET_R_MAC_DBG_SHIFT_8821C(x, v)                                    \\\n\t(BIT_CLEAR_R_MAC_DBG_SHIFT_8821C(x) | BIT_R_MAC_DBG_SHIFT_8821C(v))\n\n#define BIT_SHIFT_R_MAC_DBG_SEL_8821C 0\n#define BIT_MASK_R_MAC_DBG_SEL_8821C 0x3\n#define BIT_R_MAC_DBG_SEL_8821C(x)                                             \\\n\t(((x) & BIT_MASK_R_MAC_DBG_SEL_8821C) << BIT_SHIFT_R_MAC_DBG_SEL_8821C)\n#define BITS_R_MAC_DBG_SEL_8821C                                               \\\n\t(BIT_MASK_R_MAC_DBG_SEL_8821C << BIT_SHIFT_R_MAC_DBG_SEL_8821C)\n#define BIT_CLEAR_R_MAC_DBG_SEL_8821C(x) ((x) & (~BITS_R_MAC_DBG_SEL_8821C))\n#define BIT_GET_R_MAC_DBG_SEL_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8821C) & BIT_MASK_R_MAC_DBG_SEL_8821C)\n#define BIT_SET_R_MAC_DBG_SEL_8821C(x, v)                                      \\\n\t(BIT_CLEAR_R_MAC_DBG_SEL_8821C(x) | BIT_R_MAC_DBG_SEL_8821C(v))\n\n/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8821C */\n\n#define BIT_SHIFT_R_MAC_DEBUG_1_8821C 0\n#define BIT_MASK_R_MAC_DEBUG_1_8821C 0xffffffffL\n#define BIT_R_MAC_DEBUG_1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_R_MAC_DEBUG_1_8821C) << BIT_SHIFT_R_MAC_DEBUG_1_8821C)\n#define BITS_R_MAC_DEBUG_1_8821C                                               \\\n\t(BIT_MASK_R_MAC_DEBUG_1_8821C << BIT_SHIFT_R_MAC_DEBUG_1_8821C)\n#define BIT_CLEAR_R_MAC_DEBUG_1_8821C(x) ((x) & (~BITS_R_MAC_DEBUG_1_8821C))\n#define BIT_GET_R_MAC_DEBUG_1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8821C) & BIT_MASK_R_MAC_DEBUG_1_8821C)\n#define BIT_SET_R_MAC_DEBUG_1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_R_MAC_DEBUG_1_8821C(x) | BIT_R_MAC_DEBUG_1_8821C(v))\n\n/* 2 REG_WSEC_OPTION_8821C */\n#define BIT_RXDEC_BM_MGNT_8821C BIT(22)\n#define BIT_TXENC_BM_MGNT_8821C BIT(21)\n#define BIT_RXDEC_UNI_MGNT_8821C BIT(20)\n#define BIT_TXENC_UNI_MGNT_8821C BIT(19)\n\n/* 2 REG_RTS_ADDRESS_0_8821C */\n\n/* 2 REG_RTS_ADDRESS_0_1_8821C */\n\n/* 2 REG_RTS_ADDRESS_1_8821C */\n\n/* 2 REG_RTS_ADDRESS_1_1_8821C */\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8821C */\n#define BIT_LTECOEX_ACCESS_START_V1_8821C BIT(31)\n#define BIT_LTECOEX_WRITE_MODE_V1_8821C BIT(30)\n#define BIT_LTECOEX_READY_BIT_V1_8821C BIT(29)\n\n#define BIT_SHIFT_WRITE_BYTE_EN_V1_8821C 16\n#define BIT_MASK_WRITE_BYTE_EN_V1_8821C 0xf\n#define BIT_WRITE_BYTE_EN_V1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_WRITE_BYTE_EN_V1_8821C)                               \\\n\t << BIT_SHIFT_WRITE_BYTE_EN_V1_8821C)\n#define BITS_WRITE_BYTE_EN_V1_8821C                                            \\\n\t(BIT_MASK_WRITE_BYTE_EN_V1_8821C << BIT_SHIFT_WRITE_BYTE_EN_V1_8821C)\n#define BIT_CLEAR_WRITE_BYTE_EN_V1_8821C(x)                                    \\\n\t((x) & (~BITS_WRITE_BYTE_EN_V1_8821C))\n#define BIT_GET_WRITE_BYTE_EN_V1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8821C) &                           \\\n\t BIT_MASK_WRITE_BYTE_EN_V1_8821C)\n#define BIT_SET_WRITE_BYTE_EN_V1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_WRITE_BYTE_EN_V1_8821C(x) | BIT_WRITE_BYTE_EN_V1_8821C(v))\n\n#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C 0\n#define BIT_MASK_LTECOEX_REG_ADDR_V1_8821C 0xffff\n#define BIT_LTECOEX_REG_ADDR_V1_8821C(x)                                       \\\n\t(((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8821C)                            \\\n\t << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C)\n#define BITS_LTECOEX_REG_ADDR_V1_8821C                                         \\\n\t(BIT_MASK_LTECOEX_REG_ADDR_V1_8821C                                    \\\n\t << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C)\n#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8821C(x)                                 \\\n\t((x) & (~BITS_LTECOEX_REG_ADDR_V1_8821C))\n#define BIT_GET_LTECOEX_REG_ADDR_V1_8821C(x)                                   \\\n\t(((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) &                        \\\n\t BIT_MASK_LTECOEX_REG_ADDR_V1_8821C)\n#define BIT_SET_LTECOEX_REG_ADDR_V1_8821C(x, v)                                \\\n\t(BIT_CLEAR_LTECOEX_REG_ADDR_V1_8821C(x) |                              \\\n\t BIT_LTECOEX_REG_ADDR_V1_8821C(v))\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8821C */\n\n#define BIT_SHIFT_LTECOEX_W_DATA_V1_8821C 0\n#define BIT_MASK_LTECOEX_W_DATA_V1_8821C 0xffffffffL\n#define BIT_LTECOEX_W_DATA_V1_8821C(x)                                         \\\n\t(((x) & BIT_MASK_LTECOEX_W_DATA_V1_8821C)                              \\\n\t << BIT_SHIFT_LTECOEX_W_DATA_V1_8821C)\n#define BITS_LTECOEX_W_DATA_V1_8821C                                           \\\n\t(BIT_MASK_LTECOEX_W_DATA_V1_8821C << BIT_SHIFT_LTECOEX_W_DATA_V1_8821C)\n#define BIT_CLEAR_LTECOEX_W_DATA_V1_8821C(x)                                   \\\n\t((x) & (~BITS_LTECOEX_W_DATA_V1_8821C))\n#define BIT_GET_LTECOEX_W_DATA_V1_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8821C) &                          \\\n\t BIT_MASK_LTECOEX_W_DATA_V1_8821C)\n#define BIT_SET_LTECOEX_W_DATA_V1_8821C(x, v)                                  \\\n\t(BIT_CLEAR_LTECOEX_W_DATA_V1_8821C(x) | BIT_LTECOEX_W_DATA_V1_8821C(v))\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8821C */\n\n#define BIT_SHIFT_LTECOEX_R_DATA_V1_8821C 0\n#define BIT_MASK_LTECOEX_R_DATA_V1_8821C 0xffffffffL\n#define BIT_LTECOEX_R_DATA_V1_8821C(x)                                         \\\n\t(((x) & BIT_MASK_LTECOEX_R_DATA_V1_8821C)                              \\\n\t << BIT_SHIFT_LTECOEX_R_DATA_V1_8821C)\n#define BITS_LTECOEX_R_DATA_V1_8821C                                           \\\n\t(BIT_MASK_LTECOEX_R_DATA_V1_8821C << BIT_SHIFT_LTECOEX_R_DATA_V1_8821C)\n#define BIT_CLEAR_LTECOEX_R_DATA_V1_8821C(x)                                   \\\n\t((x) & (~BITS_LTECOEX_R_DATA_V1_8821C))\n#define BIT_GET_LTECOEX_R_DATA_V1_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8821C) &                          \\\n\t BIT_MASK_LTECOEX_R_DATA_V1_8821C)\n#define BIT_SET_LTECOEX_R_DATA_V1_8821C(x, v)                                  \\\n\t(BIT_CLEAR_LTECOEX_R_DATA_V1_8821C(x) | BIT_LTECOEX_R_DATA_V1_8821C(v))\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_NOT_VALID_8821C */\n\n/* 2 REG_SDIO_TX_CTRL_8821C */\n\n#define BIT_SHIFT_SDIO_INT_TIMEOUT_8821C 16\n#define BIT_MASK_SDIO_INT_TIMEOUT_8821C 0xffff\n#define BIT_SDIO_INT_TIMEOUT_8821C(x)                                          \\\n\t(((x) & BIT_MASK_SDIO_INT_TIMEOUT_8821C)                               \\\n\t << BIT_SHIFT_SDIO_INT_TIMEOUT_8821C)\n#define BITS_SDIO_INT_TIMEOUT_8821C                                            \\\n\t(BIT_MASK_SDIO_INT_TIMEOUT_8821C << BIT_SHIFT_SDIO_INT_TIMEOUT_8821C)\n#define BIT_CLEAR_SDIO_INT_TIMEOUT_8821C(x)                                    \\\n\t((x) & (~BITS_SDIO_INT_TIMEOUT_8821C))\n#define BIT_GET_SDIO_INT_TIMEOUT_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) &                           \\\n\t BIT_MASK_SDIO_INT_TIMEOUT_8821C)\n#define BIT_SET_SDIO_INT_TIMEOUT_8821C(x, v)                                   \\\n\t(BIT_CLEAR_SDIO_INT_TIMEOUT_8821C(x) | BIT_SDIO_INT_TIMEOUT_8821C(v))\n\n#define BIT_IO_ERR_STATUS_8821C BIT(15)\n#define BIT_REPLY_ERRCRC_IN_DATA_8821C BIT(9)\n#define BIT_EN_CMD53_OVERLAP_8821C BIT(8)\n#define BIT_REPLY_ERR_IN_R5_8821C BIT(7)\n#define BIT_R18A_EN_8821C BIT(6)\n#define BIT_SDIO_CMD_FORCE_VLD_8821C BIT(5)\n#define BIT_INIT_CMD_EN_8821C BIT(4)\n#define BIT_EN_RXDMA_MASK_INT_8821C BIT(2)\n#define BIT_EN_MASK_TIMER_8821C BIT(1)\n#define BIT_CMD_ERR_STOP_INT_EN_8821C BIT(0)\n\n/* 2 REG_SDIO_HIMR_8821C */\n#define BIT_SDIO_CRCERR_MSK_8821C BIT(31)\n#define BIT_SDIO_HSISR3_IND_MSK_8821C BIT(30)\n#define BIT_SDIO_HSISR2_IND_MSK_8821C BIT(29)\n#define BIT_SDIO_HEISR_IND_MSK_8821C BIT(28)\n#define BIT_SDIO_CTWEND_MSK_8821C BIT(27)\n#define BIT_SDIO_ATIMEND_E_MSK_8821C BIT(26)\n#define BIT_SDIIO_ATIMEND_MSK_8821C BIT(25)\n#define BIT_SDIO_OCPINT_MSK_8821C BIT(24)\n#define BIT_SDIO_PSTIMEOUT_MSK_8821C BIT(23)\n#define BIT_SDIO_GTINT4_MSK_8821C BIT(22)\n#define BIT_SDIO_GTINT3_MSK_8821C BIT(21)\n#define BIT_SDIO_HSISR_IND_MSK_8821C BIT(20)\n#define BIT_SDIO_CPWM2_MSK_8821C BIT(19)\n#define BIT_SDIO_CPWM1_MSK_8821C BIT(18)\n#define BIT_SDIO_C2HCMD_INT_MSK_8821C BIT(17)\n#define BIT_SDIO_BCNERLY_INT_MSK_8821C BIT(16)\n#define BIT_SDIO_TXBCNERR_MSK_8821C BIT(7)\n#define BIT_SDIO_TXBCNOK_MSK_8821C BIT(6)\n#define BIT_SDIO_RXFOVW_MSK_8821C BIT(5)\n#define BIT_SDIO_TXFOVW_MSK_8821C BIT(4)\n#define BIT_SDIO_RXERR_MSK_8821C BIT(3)\n#define BIT_SDIO_TXERR_MSK_8821C BIT(2)\n#define BIT_SDIO_AVAL_MSK_8821C BIT(1)\n#define BIT_RX_REQUEST_MSK_8821C BIT(0)\n\n/* 2 REG_SDIO_HISR_8821C */\n#define BIT_SDIO_CRCERR_8821C BIT(31)\n#define BIT_SDIO_HSISR3_IND_8821C BIT(30)\n#define BIT_SDIO_HSISR2_IND_8821C BIT(29)\n#define BIT_SDIO_HEISR_IND_8821C BIT(28)\n#define BIT_SDIO_CTWEND_8821C BIT(27)\n#define BIT_SDIO_ATIMEND_E_8821C BIT(26)\n#define BIT_SDIO_ATIMEND_8821C BIT(25)\n#define BIT_SDIO_OCPINT_8821C BIT(24)\n#define BIT_SDIO_PSTIMEOUT_8821C BIT(23)\n#define BIT_SDIO_GTINT4_8821C BIT(22)\n#define BIT_SDIO_GTINT3_8821C BIT(21)\n#define BIT_SDIO_HSISR_IND_8821C BIT(20)\n#define BIT_SDIO_CPWM2_8821C BIT(19)\n#define BIT_SDIO_CPWM1_8821C BIT(18)\n#define BIT_SDIO_C2HCMD_INT_8821C BIT(17)\n#define BIT_SDIO_BCNERLY_INT_8821C BIT(16)\n#define BIT_SDIO_TXBCNERR_8821C BIT(7)\n#define BIT_SDIO_TXBCNOK_8821C BIT(6)\n#define BIT_SDIO_RXFOVW_8821C BIT(5)\n#define BIT_SDIO_TXFOVW_8821C BIT(4)\n#define BIT_SDIO_RXERR_8821C BIT(3)\n#define BIT_SDIO_TXERR_8821C BIT(2)\n#define BIT_SDIO_AVAL_8821C BIT(1)\n#define BIT_RX_REQUEST_8821C BIT(0)\n\n/* 2 REG_SDIO_RX_REQ_LEN_8821C */\n\n#define BIT_SHIFT_RX_REQ_LEN_V1_8821C 0\n#define BIT_MASK_RX_REQ_LEN_V1_8821C 0x3ffff\n#define BIT_RX_REQ_LEN_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_RX_REQ_LEN_V1_8821C) << BIT_SHIFT_RX_REQ_LEN_V1_8821C)\n#define BITS_RX_REQ_LEN_V1_8821C                                               \\\n\t(BIT_MASK_RX_REQ_LEN_V1_8821C << BIT_SHIFT_RX_REQ_LEN_V1_8821C)\n#define BIT_CLEAR_RX_REQ_LEN_V1_8821C(x) ((x) & (~BITS_RX_REQ_LEN_V1_8821C))\n#define BIT_GET_RX_REQ_LEN_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8821C) & BIT_MASK_RX_REQ_LEN_V1_8821C)\n#define BIT_SET_RX_REQ_LEN_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_RX_REQ_LEN_V1_8821C(x) | BIT_RX_REQ_LEN_V1_8821C(v))\n\n/* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8821C */\n\n#define BIT_SHIFT_FREE_TXPG_SEQ_8821C 0\n#define BIT_MASK_FREE_TXPG_SEQ_8821C 0xff\n#define BIT_FREE_TXPG_SEQ_8821C(x)                                             \\\n\t(((x) & BIT_MASK_FREE_TXPG_SEQ_8821C) << BIT_SHIFT_FREE_TXPG_SEQ_8821C)\n#define BITS_FREE_TXPG_SEQ_8821C                                               \\\n\t(BIT_MASK_FREE_TXPG_SEQ_8821C << BIT_SHIFT_FREE_TXPG_SEQ_8821C)\n#define BIT_CLEAR_FREE_TXPG_SEQ_8821C(x) ((x) & (~BITS_FREE_TXPG_SEQ_8821C))\n#define BIT_GET_FREE_TXPG_SEQ_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8821C) & BIT_MASK_FREE_TXPG_SEQ_8821C)\n#define BIT_SET_FREE_TXPG_SEQ_8821C(x, v)                                      \\\n\t(BIT_CLEAR_FREE_TXPG_SEQ_8821C(x) | BIT_FREE_TXPG_SEQ_8821C(v))\n\n/* 2 REG_SDIO_FREE_TXPG_8821C */\n\n#define BIT_SHIFT_MID_FREEPG_V1_8821C 16\n#define BIT_MASK_MID_FREEPG_V1_8821C 0xfff\n#define BIT_MID_FREEPG_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_MID_FREEPG_V1_8821C) << BIT_SHIFT_MID_FREEPG_V1_8821C)\n#define BITS_MID_FREEPG_V1_8821C                                               \\\n\t(BIT_MASK_MID_FREEPG_V1_8821C << BIT_SHIFT_MID_FREEPG_V1_8821C)\n#define BIT_CLEAR_MID_FREEPG_V1_8821C(x) ((x) & (~BITS_MID_FREEPG_V1_8821C))\n#define BIT_GET_MID_FREEPG_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MID_FREEPG_V1_8821C) & BIT_MASK_MID_FREEPG_V1_8821C)\n#define BIT_SET_MID_FREEPG_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_MID_FREEPG_V1_8821C(x) | BIT_MID_FREEPG_V1_8821C(v))\n\n#define BIT_SHIFT_HIQ_FREEPG_V1_8821C 0\n#define BIT_MASK_HIQ_FREEPG_V1_8821C 0xfff\n#define BIT_HIQ_FREEPG_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_HIQ_FREEPG_V1_8821C) << BIT_SHIFT_HIQ_FREEPG_V1_8821C)\n#define BITS_HIQ_FREEPG_V1_8821C                                               \\\n\t(BIT_MASK_HIQ_FREEPG_V1_8821C << BIT_SHIFT_HIQ_FREEPG_V1_8821C)\n#define BIT_CLEAR_HIQ_FREEPG_V1_8821C(x) ((x) & (~BITS_HIQ_FREEPG_V1_8821C))\n#define BIT_GET_HIQ_FREEPG_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8821C) & BIT_MASK_HIQ_FREEPG_V1_8821C)\n#define BIT_SET_HIQ_FREEPG_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_HIQ_FREEPG_V1_8821C(x) | BIT_HIQ_FREEPG_V1_8821C(v))\n\n/* 2 REG_SDIO_FREE_TXPG2_8821C */\n\n#define BIT_SHIFT_PUB_FREEPG_V1_8821C 16\n#define BIT_MASK_PUB_FREEPG_V1_8821C 0xfff\n#define BIT_PUB_FREEPG_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_PUB_FREEPG_V1_8821C) << BIT_SHIFT_PUB_FREEPG_V1_8821C)\n#define BITS_PUB_FREEPG_V1_8821C                                               \\\n\t(BIT_MASK_PUB_FREEPG_V1_8821C << BIT_SHIFT_PUB_FREEPG_V1_8821C)\n#define BIT_CLEAR_PUB_FREEPG_V1_8821C(x) ((x) & (~BITS_PUB_FREEPG_V1_8821C))\n#define BIT_GET_PUB_FREEPG_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PUB_FREEPG_V1_8821C) & BIT_MASK_PUB_FREEPG_V1_8821C)\n#define BIT_SET_PUB_FREEPG_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_PUB_FREEPG_V1_8821C(x) | BIT_PUB_FREEPG_V1_8821C(v))\n\n#define BIT_SHIFT_LOW_FREEPG_V1_8821C 0\n#define BIT_MASK_LOW_FREEPG_V1_8821C 0xfff\n#define BIT_LOW_FREEPG_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_LOW_FREEPG_V1_8821C) << BIT_SHIFT_LOW_FREEPG_V1_8821C)\n#define BITS_LOW_FREEPG_V1_8821C                                               \\\n\t(BIT_MASK_LOW_FREEPG_V1_8821C << BIT_SHIFT_LOW_FREEPG_V1_8821C)\n#define BIT_CLEAR_LOW_FREEPG_V1_8821C(x) ((x) & (~BITS_LOW_FREEPG_V1_8821C))\n#define BIT_GET_LOW_FREEPG_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_LOW_FREEPG_V1_8821C) & BIT_MASK_LOW_FREEPG_V1_8821C)\n#define BIT_SET_LOW_FREEPG_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_LOW_FREEPG_V1_8821C(x) | BIT_LOW_FREEPG_V1_8821C(v))\n\n/* 2 REG_SDIO_OQT_FREE_TXPG_V1_8821C */\n\n#define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C 24\n#define BIT_MASK_NOAC_OQT_FREEPG_V1_8821C 0xff\n#define BIT_NOAC_OQT_FREEPG_V1_8821C(x)                                        \\\n\t(((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8821C)                             \\\n\t << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C)\n#define BITS_NOAC_OQT_FREEPG_V1_8821C                                          \\\n\t(BIT_MASK_NOAC_OQT_FREEPG_V1_8821C                                     \\\n\t << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C)\n#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8821C(x)                                  \\\n\t((x) & (~BITS_NOAC_OQT_FREEPG_V1_8821C))\n#define BIT_GET_NOAC_OQT_FREEPG_V1_8821C(x)                                    \\\n\t(((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C) &                         \\\n\t BIT_MASK_NOAC_OQT_FREEPG_V1_8821C)\n#define BIT_SET_NOAC_OQT_FREEPG_V1_8821C(x, v)                                 \\\n\t(BIT_CLEAR_NOAC_OQT_FREEPG_V1_8821C(x) |                               \\\n\t BIT_NOAC_OQT_FREEPG_V1_8821C(v))\n\n#define BIT_SHIFT_AC_OQT_FREEPG_V1_8821C 16\n#define BIT_MASK_AC_OQT_FREEPG_V1_8821C 0xff\n#define BIT_AC_OQT_FREEPG_V1_8821C(x)                                          \\\n\t(((x) & BIT_MASK_AC_OQT_FREEPG_V1_8821C)                               \\\n\t << BIT_SHIFT_AC_OQT_FREEPG_V1_8821C)\n#define BITS_AC_OQT_FREEPG_V1_8821C                                            \\\n\t(BIT_MASK_AC_OQT_FREEPG_V1_8821C << BIT_SHIFT_AC_OQT_FREEPG_V1_8821C)\n#define BIT_CLEAR_AC_OQT_FREEPG_V1_8821C(x)                                    \\\n\t((x) & (~BITS_AC_OQT_FREEPG_V1_8821C))\n#define BIT_GET_AC_OQT_FREEPG_V1_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) &                           \\\n\t BIT_MASK_AC_OQT_FREEPG_V1_8821C)\n#define BIT_SET_AC_OQT_FREEPG_V1_8821C(x, v)                                   \\\n\t(BIT_CLEAR_AC_OQT_FREEPG_V1_8821C(x) | BIT_AC_OQT_FREEPG_V1_8821C(v))\n\n#define BIT_SHIFT_EXQ_FREEPG_V1_8821C 0\n#define BIT_MASK_EXQ_FREEPG_V1_8821C 0xfff\n#define BIT_EXQ_FREEPG_V1_8821C(x)                                             \\\n\t(((x) & BIT_MASK_EXQ_FREEPG_V1_8821C) << BIT_SHIFT_EXQ_FREEPG_V1_8821C)\n#define BITS_EXQ_FREEPG_V1_8821C                                               \\\n\t(BIT_MASK_EXQ_FREEPG_V1_8821C << BIT_SHIFT_EXQ_FREEPG_V1_8821C)\n#define BIT_CLEAR_EXQ_FREEPG_V1_8821C(x) ((x) & (~BITS_EXQ_FREEPG_V1_8821C))\n#define BIT_GET_EXQ_FREEPG_V1_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8821C) & BIT_MASK_EXQ_FREEPG_V1_8821C)\n#define BIT_SET_EXQ_FREEPG_V1_8821C(x, v)                                      \\\n\t(BIT_CLEAR_EXQ_FREEPG_V1_8821C(x) | BIT_EXQ_FREEPG_V1_8821C(v))\n\n/* 2 REG_SDIO_HTSFR_INFO_8821C */\n\n#define BIT_SHIFT_HTSFR1_8821C 16\n#define BIT_MASK_HTSFR1_8821C 0xffff\n#define BIT_HTSFR1_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_HTSFR1_8821C) << BIT_SHIFT_HTSFR1_8821C)\n#define BITS_HTSFR1_8821C (BIT_MASK_HTSFR1_8821C << BIT_SHIFT_HTSFR1_8821C)\n#define BIT_CLEAR_HTSFR1_8821C(x) ((x) & (~BITS_HTSFR1_8821C))\n#define BIT_GET_HTSFR1_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_HTSFR1_8821C) & BIT_MASK_HTSFR1_8821C)\n#define BIT_SET_HTSFR1_8821C(x, v)                                             \\\n\t(BIT_CLEAR_HTSFR1_8821C(x) | BIT_HTSFR1_8821C(v))\n\n#define BIT_SHIFT_HTSFR0_8821C 0\n#define BIT_MASK_HTSFR0_8821C 0xffff\n#define BIT_HTSFR0_8821C(x)                                                    \\\n\t(((x) & BIT_MASK_HTSFR0_8821C) << BIT_SHIFT_HTSFR0_8821C)\n#define BITS_HTSFR0_8821C (BIT_MASK_HTSFR0_8821C << BIT_SHIFT_HTSFR0_8821C)\n#define BIT_CLEAR_HTSFR0_8821C(x) ((x) & (~BITS_HTSFR0_8821C))\n#define BIT_GET_HTSFR0_8821C(x)                                                \\\n\t(((x) >> BIT_SHIFT_HTSFR0_8821C) & BIT_MASK_HTSFR0_8821C)\n#define BIT_SET_HTSFR0_8821C(x, v)                                             \\\n\t(BIT_CLEAR_HTSFR0_8821C(x) | BIT_HTSFR0_8821C(v))\n\n/* 2 REG_SDIO_HCPWM1_V2_8821C */\n#define BIT_TOGGLE_8821C BIT(7)\n#define BIT_CUR_PS_8821C BIT(0)\n\n/* 2 REG_SDIO_HCPWM2_V2_8821C */\n\n/* 2 REG_SDIO_INDIRECT_REG_CFG_8821C */\n#define BIT_INDIRECT_REG_RDY_8821C BIT(20)\n#define BIT_INDIRECT_REG_R_8821C BIT(19)\n#define BIT_INDIRECT_REG_W_8821C BIT(18)\n\n#define BIT_SHIFT_INDIRECT_REG_SIZE_8821C 16\n#define BIT_MASK_INDIRECT_REG_SIZE_8821C 0x3\n#define BIT_INDIRECT_REG_SIZE_8821C(x)                                         \\\n\t(((x) & BIT_MASK_INDIRECT_REG_SIZE_8821C)                              \\\n\t << BIT_SHIFT_INDIRECT_REG_SIZE_8821C)\n#define BITS_INDIRECT_REG_SIZE_8821C                                           \\\n\t(BIT_MASK_INDIRECT_REG_SIZE_8821C << BIT_SHIFT_INDIRECT_REG_SIZE_8821C)\n#define BIT_CLEAR_INDIRECT_REG_SIZE_8821C(x)                                   \\\n\t((x) & (~BITS_INDIRECT_REG_SIZE_8821C))\n#define BIT_GET_INDIRECT_REG_SIZE_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8821C) &                          \\\n\t BIT_MASK_INDIRECT_REG_SIZE_8821C)\n#define BIT_SET_INDIRECT_REG_SIZE_8821C(x, v)                                  \\\n\t(BIT_CLEAR_INDIRECT_REG_SIZE_8821C(x) | BIT_INDIRECT_REG_SIZE_8821C(v))\n\n#define BIT_SHIFT_INDIRECT_REG_ADDR_8821C 0\n#define BIT_MASK_INDIRECT_REG_ADDR_8821C 0xffff\n#define BIT_INDIRECT_REG_ADDR_8821C(x)                                         \\\n\t(((x) & BIT_MASK_INDIRECT_REG_ADDR_8821C)                              \\\n\t << BIT_SHIFT_INDIRECT_REG_ADDR_8821C)\n#define BITS_INDIRECT_REG_ADDR_8821C                                           \\\n\t(BIT_MASK_INDIRECT_REG_ADDR_8821C << BIT_SHIFT_INDIRECT_REG_ADDR_8821C)\n#define BIT_CLEAR_INDIRECT_REG_ADDR_8821C(x)                                   \\\n\t((x) & (~BITS_INDIRECT_REG_ADDR_8821C))\n#define BIT_GET_INDIRECT_REG_ADDR_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8821C) &                          \\\n\t BIT_MASK_INDIRECT_REG_ADDR_8821C)\n#define BIT_SET_INDIRECT_REG_ADDR_8821C(x, v)                                  \\\n\t(BIT_CLEAR_INDIRECT_REG_ADDR_8821C(x) | BIT_INDIRECT_REG_ADDR_8821C(v))\n\n/* 2 REG_SDIO_INDIRECT_REG_DATA_8821C */\n\n#define BIT_SHIFT_INDIRECT_REG_DATA_8821C 0\n#define BIT_MASK_INDIRECT_REG_DATA_8821C 0xffffffffL\n#define BIT_INDIRECT_REG_DATA_8821C(x)                                         \\\n\t(((x) & BIT_MASK_INDIRECT_REG_DATA_8821C)                              \\\n\t << BIT_SHIFT_INDIRECT_REG_DATA_8821C)\n#define BITS_INDIRECT_REG_DATA_8821C                                           \\\n\t(BIT_MASK_INDIRECT_REG_DATA_8821C << BIT_SHIFT_INDIRECT_REG_DATA_8821C)\n#define BIT_CLEAR_INDIRECT_REG_DATA_8821C(x)                                   \\\n\t((x) & (~BITS_INDIRECT_REG_DATA_8821C))\n#define BIT_GET_INDIRECT_REG_DATA_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8821C) &                          \\\n\t BIT_MASK_INDIRECT_REG_DATA_8821C)\n#define BIT_SET_INDIRECT_REG_DATA_8821C(x, v)                                  \\\n\t(BIT_CLEAR_INDIRECT_REG_DATA_8821C(x) | BIT_INDIRECT_REG_DATA_8821C(v))\n\n/* 2 REG_SDIO_H2C_8821C */\n\n#define BIT_SHIFT_SDIO_H2C_MSG_8821C 0\n#define BIT_MASK_SDIO_H2C_MSG_8821C 0xffffffffL\n#define BIT_SDIO_H2C_MSG_8821C(x)                                              \\\n\t(((x) & BIT_MASK_SDIO_H2C_MSG_8821C) << BIT_SHIFT_SDIO_H2C_MSG_8821C)\n#define BITS_SDIO_H2C_MSG_8821C                                                \\\n\t(BIT_MASK_SDIO_H2C_MSG_8821C << BIT_SHIFT_SDIO_H2C_MSG_8821C)\n#define BIT_CLEAR_SDIO_H2C_MSG_8821C(x) ((x) & (~BITS_SDIO_H2C_MSG_8821C))\n#define BIT_GET_SDIO_H2C_MSG_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_SDIO_H2C_MSG_8821C) & BIT_MASK_SDIO_H2C_MSG_8821C)\n#define BIT_SET_SDIO_H2C_MSG_8821C(x, v)                                       \\\n\t(BIT_CLEAR_SDIO_H2C_MSG_8821C(x) | BIT_SDIO_H2C_MSG_8821C(v))\n\n/* 2 REG_SDIO_C2H_8821C */\n\n#define BIT_SHIFT_SDIO_C2H_MSG_8821C 0\n#define BIT_MASK_SDIO_C2H_MSG_8821C 0xffffffffL\n#define BIT_SDIO_C2H_MSG_8821C(x)                                              \\\n\t(((x) & BIT_MASK_SDIO_C2H_MSG_8821C) << BIT_SHIFT_SDIO_C2H_MSG_8821C)\n#define BITS_SDIO_C2H_MSG_8821C                                                \\\n\t(BIT_MASK_SDIO_C2H_MSG_8821C << BIT_SHIFT_SDIO_C2H_MSG_8821C)\n#define BIT_CLEAR_SDIO_C2H_MSG_8821C(x) ((x) & (~BITS_SDIO_C2H_MSG_8821C))\n#define BIT_GET_SDIO_C2H_MSG_8821C(x)                                          \\\n\t(((x) >> BIT_SHIFT_SDIO_C2H_MSG_8821C) & BIT_MASK_SDIO_C2H_MSG_8821C)\n#define BIT_SET_SDIO_C2H_MSG_8821C(x, v)                                       \\\n\t(BIT_CLEAR_SDIO_C2H_MSG_8821C(x) | BIT_SDIO_C2H_MSG_8821C(v))\n\n/* 2 REG_SDIO_HRPWM1_8821C */\n#define BIT_TOGGLE_8821C BIT(7)\n#define BIT_ACK_8821C BIT(6)\n#define BIT_REQ_PS_8821C BIT(0)\n\n/* 2 REG_SDIO_HRPWM2_8821C */\n\n/* 2 REG_SDIO_HPS_CLKR_8821C */\n\n/* 2 REG_SDIO_BUS_CTRL_8821C */\n#define BIT_PAD_CLK_XHGE_EN_8821C BIT(3)\n#define BIT_INTER_CLK_EN_8821C BIT(2)\n#define BIT_EN_RPT_TXCRC_8821C BIT(1)\n#define BIT_DIS_RXDMA_STS_8821C BIT(0)\n\n/* 2 REG_SDIO_HSUS_CTRL_8821C */\n#define BIT_INTR_CTRL_8821C BIT(4)\n#define BIT_SDIO_VOLTAGE_8821C BIT(3)\n#define BIT_BYPASS_INIT_8821C BIT(2)\n#define BIT_HCI_RESUME_RDY_8821C BIT(1)\n#define BIT_HCI_SUS_REQ_8821C BIT(0)\n\n/* 2 REG_SDIO_RESPONSE_TIMER_8821C */\n\n#define BIT_SHIFT_CMDIN_2RESP_TIMER_8821C 0\n#define BIT_MASK_CMDIN_2RESP_TIMER_8821C 0xffff\n#define BIT_CMDIN_2RESP_TIMER_8821C(x)                                         \\\n\t(((x) & BIT_MASK_CMDIN_2RESP_TIMER_8821C)                              \\\n\t << BIT_SHIFT_CMDIN_2RESP_TIMER_8821C)\n#define BITS_CMDIN_2RESP_TIMER_8821C                                           \\\n\t(BIT_MASK_CMDIN_2RESP_TIMER_8821C << BIT_SHIFT_CMDIN_2RESP_TIMER_8821C)\n#define BIT_CLEAR_CMDIN_2RESP_TIMER_8821C(x)                                   \\\n\t((x) & (~BITS_CMDIN_2RESP_TIMER_8821C))\n#define BIT_GET_CMDIN_2RESP_TIMER_8821C(x)                                     \\\n\t(((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8821C) &                          \\\n\t BIT_MASK_CMDIN_2RESP_TIMER_8821C)\n#define BIT_SET_CMDIN_2RESP_TIMER_8821C(x, v)                                  \\\n\t(BIT_CLEAR_CMDIN_2RESP_TIMER_8821C(x) | BIT_CMDIN_2RESP_TIMER_8821C(v))\n\n/* 2 REG_SDIO_CMD_CRC_8821C */\n\n#define BIT_SHIFT_SDIO_CMD_CRC_V1_8821C 0\n#define BIT_MASK_SDIO_CMD_CRC_V1_8821C 0xff\n#define BIT_SDIO_CMD_CRC_V1_8821C(x)                                           \\\n\t(((x) & BIT_MASK_SDIO_CMD_CRC_V1_8821C)                                \\\n\t << BIT_SHIFT_SDIO_CMD_CRC_V1_8821C)\n#define BITS_SDIO_CMD_CRC_V1_8821C                                             \\\n\t(BIT_MASK_SDIO_CMD_CRC_V1_8821C << BIT_SHIFT_SDIO_CMD_CRC_V1_8821C)\n#define BIT_CLEAR_SDIO_CMD_CRC_V1_8821C(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8821C))\n#define BIT_GET_SDIO_CMD_CRC_V1_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8821C) &                            \\\n\t BIT_MASK_SDIO_CMD_CRC_V1_8821C)\n#define BIT_SET_SDIO_CMD_CRC_V1_8821C(x, v)                                    \\\n\t(BIT_CLEAR_SDIO_CMD_CRC_V1_8821C(x) | BIT_SDIO_CMD_CRC_V1_8821C(v))\n\n/* 2 REG_SDIO_HSISR_8821C */\n#define BIT_DRV_WLAN_INT_CLR_8821C BIT(1)\n#define BIT_DRV_WLAN_INT_8821C BIT(0)\n\n/* 2 REG_SDIO_ERR_RPT_8821C */\n#define BIT_HR_FF_OVF_8821C BIT(6)\n#define BIT_HR_FF_UDN_8821C BIT(5)\n#define BIT_TXDMA_BUSY_ERR_8821C BIT(4)\n#define BIT_TXDMA_VLD_ERR_8821C BIT(3)\n#define BIT_QSEL_UNKNOWN_ERR_8821C BIT(2)\n#define BIT_QSEL_MIS_ERR_8821C BIT(1)\n#define BIT_SDIO_OVERRD_ERR_8821C BIT(0)\n\n/* 2 REG_SDIO_CMD_ERRCNT_8821C */\n\n#define BIT_SHIFT_CMD_CRC_ERR_CNT_8821C 0\n#define BIT_MASK_CMD_CRC_ERR_CNT_8821C 0xff\n#define BIT_CMD_CRC_ERR_CNT_8821C(x)                                           \\\n\t(((x) & BIT_MASK_CMD_CRC_ERR_CNT_8821C)                                \\\n\t << BIT_SHIFT_CMD_CRC_ERR_CNT_8821C)\n#define BITS_CMD_CRC_ERR_CNT_8821C                                             \\\n\t(BIT_MASK_CMD_CRC_ERR_CNT_8821C << BIT_SHIFT_CMD_CRC_ERR_CNT_8821C)\n#define BIT_CLEAR_CMD_CRC_ERR_CNT_8821C(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8821C))\n#define BIT_GET_CMD_CRC_ERR_CNT_8821C(x)                                       \\\n\t(((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8821C) &                            \\\n\t BIT_MASK_CMD_CRC_ERR_CNT_8821C)\n#define BIT_SET_CMD_CRC_ERR_CNT_8821C(x, v)                                    \\\n\t(BIT_CLEAR_CMD_CRC_ERR_CNT_8821C(x) | BIT_CMD_CRC_ERR_CNT_8821C(v))\n\n/* 2 REG_SDIO_DATA_ERRCNT_8821C */\n\n#define BIT_SHIFT_DATA_CRC_ERR_CNT_8821C 0\n#define BIT_MASK_DATA_CRC_ERR_CNT_8821C 0xff\n#define BIT_DATA_CRC_ERR_CNT_8821C(x)                                          \\\n\t(((x) & BIT_MASK_DATA_CRC_ERR_CNT_8821C)                               \\\n\t << BIT_SHIFT_DATA_CRC_ERR_CNT_8821C)\n#define BITS_DATA_CRC_ERR_CNT_8821C                                            \\\n\t(BIT_MASK_DATA_CRC_ERR_CNT_8821C << BIT_SHIFT_DATA_CRC_ERR_CNT_8821C)\n#define BIT_CLEAR_DATA_CRC_ERR_CNT_8821C(x)                                    \\\n\t((x) & (~BITS_DATA_CRC_ERR_CNT_8821C))\n#define BIT_GET_DATA_CRC_ERR_CNT_8821C(x)                                      \\\n\t(((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8821C) &                           \\\n\t BIT_MASK_DATA_CRC_ERR_CNT_8821C)\n#define BIT_SET_DATA_CRC_ERR_CNT_8821C(x, v)                                   \\\n\t(BIT_CLEAR_DATA_CRC_ERR_CNT_8821C(x) | BIT_DATA_CRC_ERR_CNT_8821C(v))\n\n/* 2 REG_SDIO_CMD_ERR_CONTENT_8821C */\n\n#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C 0\n#define BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C 0xffffffffffL\n#define BIT_SDIO_CMD_ERR_CONTENT_8821C(x)                                      \\\n\t(((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C)                           \\\n\t << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C)\n#define BITS_SDIO_CMD_ERR_CONTENT_8821C                                        \\\n\t(BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C                                   \\\n\t << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C)\n#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8821C(x)                                \\\n\t((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8821C))\n#define BIT_GET_SDIO_CMD_ERR_CONTENT_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C) &                       \\\n\t BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C)\n#define BIT_SET_SDIO_CMD_ERR_CONTENT_8821C(x, v)                               \\\n\t(BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8821C(x) |                             \\\n\t BIT_SDIO_CMD_ERR_CONTENT_8821C(v))\n\n/* 2 REG_SDIO_CRC_ERR_IDX_8821C */\n#define BIT_D3_CRC_ERR_8821C BIT(4)\n#define BIT_D2_CRC_ERR_8821C BIT(3)\n#define BIT_D1_CRC_ERR_8821C BIT(2)\n#define BIT_D0_CRC_ERR_8821C BIT(1)\n#define BIT_CMD_CRC_ERR_8821C BIT(0)\n\n/* 2 REG_SDIO_DATA_CRC_8821C */\n\n#define BIT_SHIFT_SDIO_DATA_CRC_8821C 0\n#define BIT_MASK_SDIO_DATA_CRC_8821C 0xffff\n#define BIT_SDIO_DATA_CRC_8821C(x)                                             \\\n\t(((x) & BIT_MASK_SDIO_DATA_CRC_8821C) << BIT_SHIFT_SDIO_DATA_CRC_8821C)\n#define BITS_SDIO_DATA_CRC_8821C                                               \\\n\t(BIT_MASK_SDIO_DATA_CRC_8821C << BIT_SHIFT_SDIO_DATA_CRC_8821C)\n#define BIT_CLEAR_SDIO_DATA_CRC_8821C(x) ((x) & (~BITS_SDIO_DATA_CRC_8821C))\n#define BIT_GET_SDIO_DATA_CRC_8821C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SDIO_DATA_CRC_8821C) & BIT_MASK_SDIO_DATA_CRC_8821C)\n#define BIT_SET_SDIO_DATA_CRC_8821C(x, v)                                      \\\n\t(BIT_CLEAR_SDIO_DATA_CRC_8821C(x) | BIT_SDIO_DATA_CRC_8821C(v))\n\n/* 2 REG_SDIO_DATA_REPLY_TIME_8821C */\n\n#define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C 0\n#define BIT_MASK_SDIO_DATA_REPLY_TIME_8821C 0x7\n#define BIT_SDIO_DATA_REPLY_TIME_8821C(x)                                      \\\n\t(((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8821C)                           \\\n\t << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C)\n#define BITS_SDIO_DATA_REPLY_TIME_8821C                                        \\\n\t(BIT_MASK_SDIO_DATA_REPLY_TIME_8821C                                   \\\n\t << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C)\n#define BIT_CLEAR_SDIO_DATA_REPLY_TIME_8821C(x)                                \\\n\t((x) & (~BITS_SDIO_DATA_REPLY_TIME_8821C))\n#define BIT_GET_SDIO_DATA_REPLY_TIME_8821C(x)                                  \\\n\t(((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C) &                       \\\n\t BIT_MASK_SDIO_DATA_REPLY_TIME_8821C)\n#define BIT_SET_SDIO_DATA_REPLY_TIME_8821C(x, v)                               \\\n\t(BIT_CLEAR_SDIO_DATA_REPLY_TIME_8821C(x) |                             \\\n\t BIT_SDIO_DATA_REPLY_TIME_8821C(v))\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_bit_8822b.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef __INC_HALMAC_BIT_8822B_H\n#define __INC_HALMAC_BIT_8822B_H\n\n#define CPU_OPT_WIDTH 0x1F\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_SYS_ISO_CTRL_8822B */\n#define BIT_PWC_EV12V_8822B BIT(15)\n#define BIT_PWC_EV25V_8822B BIT(14)\n#define BIT_PA33V_EN_8822B BIT(13)\n#define BIT_PA12V_EN_8822B BIT(12)\n#define BIT_UA33V_EN_8822B BIT(11)\n#define BIT_UA12V_EN_8822B BIT(10)\n#define BIT_ISO_RFDIO_8822B BIT(9)\n#define BIT_ISO_EB2CORE_8822B BIT(8)\n#define BIT_ISO_DIOE_8822B BIT(7)\n#define BIT_ISO_WLPON2PP_8822B BIT(6)\n#define BIT_ISO_IP2MAC_WA2PP_8822B BIT(5)\n#define BIT_ISO_PD2CORE_8822B BIT(4)\n#define BIT_ISO_PA2PCIE_8822B BIT(3)\n#define BIT_ISO_UD2CORE_8822B BIT(2)\n#define BIT_ISO_UA2USB_8822B BIT(1)\n#define BIT_ISO_WD2PP_8822B BIT(0)\n\n/* 2 REG_SYS_FUNC_EN_8822B */\n#define BIT_FEN_MREGEN_8822B BIT(15)\n#define BIT_FEN_HWPDN_8822B BIT(14)\n#define BIT_EN_25_1_8822B BIT(13)\n#define BIT_FEN_ELDR_8822B BIT(12)\n#define BIT_FEN_DCORE_8822B BIT(11)\n#define BIT_FEN_CPUEN_8822B BIT(10)\n#define BIT_FEN_DIOE_8822B BIT(9)\n#define BIT_FEN_PCIED_8822B BIT(8)\n#define BIT_FEN_PPLL_8822B BIT(7)\n#define BIT_FEN_PCIEA_8822B BIT(6)\n#define BIT_FEN_DIO_PCIE_8822B BIT(5)\n#define BIT_FEN_USBD_8822B BIT(4)\n#define BIT_FEN_UPLL_8822B BIT(3)\n#define BIT_FEN_USBA_8822B BIT(2)\n#define BIT_FEN_BB_GLB_RSTN_8822B BIT(1)\n#define BIT_FEN_BBRSTB_8822B BIT(0)\n\n/* 2 REG_SYS_PW_CTRL_8822B */\n#define BIT_SOP_EABM_8822B BIT(31)\n#define BIT_SOP_ACKF_8822B BIT(30)\n#define BIT_SOP_ERCK_8822B BIT(29)\n#define BIT_SOP_ESWR_8822B BIT(28)\n#define BIT_SOP_PWMM_8822B BIT(27)\n#define BIT_SOP_EECK_8822B BIT(26)\n#define BIT_SOP_EXTL_8822B BIT(24)\n#define BIT_SYM_OP_RING_12M_8822B BIT(22)\n#define BIT_ROP_SWPR_8822B BIT(21)\n#define BIT_DIS_HW_LPLDM_8822B BIT(20)\n#define BIT_OPT_SWRST_WLMCU_8822B BIT(19)\n#define BIT_RDY_SYSPWR_8822B BIT(17)\n#define BIT_EN_WLON_8822B BIT(16)\n#define BIT_APDM_HPDN_8822B BIT(15)\n#define BIT_AFSM_PCIE_SUS_EN_8822B BIT(12)\n#define BIT_AFSM_WLSUS_EN_8822B BIT(11)\n#define BIT_APFM_SWLPS_8822B BIT(10)\n#define BIT_APFM_OFFMAC_8822B BIT(9)\n#define BIT_APFN_ONMAC_8822B BIT(8)\n#define BIT_CHIP_PDN_EN_8822B BIT(7)\n#define BIT_RDY_MACDIS_8822B BIT(6)\n#define BIT_RING_CLK_12M_EN_8822B BIT(4)\n#define BIT_PFM_WOWL_8822B BIT(3)\n#define BIT_PFM_LDKP_8822B BIT(2)\n#define BIT_WL_HCI_ALD_8822B BIT(1)\n#define BIT_PFM_LDALL_8822B BIT(0)\n\n/* 2 REG_SYS_CLK_CTRL_8822B */\n#define BIT_LDO_DUMMY_8822B BIT(15)\n#define BIT_CPU_CLK_EN_8822B BIT(14)\n#define BIT_SYMREG_CLK_EN_8822B BIT(13)\n#define BIT_HCI_CLK_EN_8822B BIT(12)\n#define BIT_MAC_CLK_EN_8822B BIT(11)\n#define BIT_SEC_CLK_EN_8822B BIT(10)\n#define BIT_PHY_SSC_RSTB_8822B BIT(9)\n#define BIT_EXT_32K_EN_8822B BIT(8)\n#define BIT_WL_CLK_TEST_8822B BIT(7)\n#define BIT_OP_SPS_PWM_EN_8822B BIT(6)\n#define BIT_LOADER_CLK_EN_8822B BIT(5)\n#define BIT_MACSLP_8822B BIT(4)\n#define BIT_WAKEPAD_EN_8822B BIT(3)\n#define BIT_ROMD16V_EN_8822B BIT(2)\n#define BIT_CKANA12M_EN_8822B BIT(1)\n#define BIT_CNTD16V_EN_8822B BIT(0)\n\n/* 2 REG_SYS_EEPROM_CTRL_8822B */\n\n#define BIT_SHIFT_VPDIDX_8822B 8\n#define BIT_MASK_VPDIDX_8822B 0xff\n#define BIT_VPDIDX_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_VPDIDX_8822B) << BIT_SHIFT_VPDIDX_8822B)\n#define BITS_VPDIDX_8822B (BIT_MASK_VPDIDX_8822B << BIT_SHIFT_VPDIDX_8822B)\n#define BIT_CLEAR_VPDIDX_8822B(x) ((x) & (~BITS_VPDIDX_8822B))\n#define BIT_GET_VPDIDX_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_VPDIDX_8822B) & BIT_MASK_VPDIDX_8822B)\n#define BIT_SET_VPDIDX_8822B(x, v)                                             \\\n\t(BIT_CLEAR_VPDIDX_8822B(x) | BIT_VPDIDX_8822B(v))\n\n#define BIT_SHIFT_EEM1_0_8822B 6\n#define BIT_MASK_EEM1_0_8822B 0x3\n#define BIT_EEM1_0_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_EEM1_0_8822B) << BIT_SHIFT_EEM1_0_8822B)\n#define BITS_EEM1_0_8822B (BIT_MASK_EEM1_0_8822B << BIT_SHIFT_EEM1_0_8822B)\n#define BIT_CLEAR_EEM1_0_8822B(x) ((x) & (~BITS_EEM1_0_8822B))\n#define BIT_GET_EEM1_0_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_EEM1_0_8822B) & BIT_MASK_EEM1_0_8822B)\n#define BIT_SET_EEM1_0_8822B(x, v)                                             \\\n\t(BIT_CLEAR_EEM1_0_8822B(x) | BIT_EEM1_0_8822B(v))\n\n#define BIT_AUTOLOAD_SUS_8822B BIT(5)\n#define BIT_EERPOMSEL_8822B BIT(4)\n#define BIT_EECS_V1_8822B BIT(3)\n#define BIT_EESK_V1_8822B BIT(2)\n#define BIT_EEDI_V1_8822B BIT(1)\n#define BIT_EEDO_V1_8822B BIT(0)\n\n/* 2 REG_EE_VPD_8822B */\n\n#define BIT_SHIFT_VPD_DATA_8822B 0\n#define BIT_MASK_VPD_DATA_8822B 0xffffffffL\n#define BIT_VPD_DATA_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_VPD_DATA_8822B) << BIT_SHIFT_VPD_DATA_8822B)\n#define BITS_VPD_DATA_8822B                                                    \\\n\t(BIT_MASK_VPD_DATA_8822B << BIT_SHIFT_VPD_DATA_8822B)\n#define BIT_CLEAR_VPD_DATA_8822B(x) ((x) & (~BITS_VPD_DATA_8822B))\n#define BIT_GET_VPD_DATA_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_VPD_DATA_8822B) & BIT_MASK_VPD_DATA_8822B)\n#define BIT_SET_VPD_DATA_8822B(x, v)                                           \\\n\t(BIT_CLEAR_VPD_DATA_8822B(x) | BIT_VPD_DATA_8822B(v))\n\n/* 2 REG_SYS_SWR_CTRL1_8822B */\n#define BIT_C2_L_BIT0_8822B BIT(31)\n\n#define BIT_SHIFT_C1_L_8822B 29\n#define BIT_MASK_C1_L_8822B 0x3\n#define BIT_C1_L_8822B(x) (((x) & BIT_MASK_C1_L_8822B) << BIT_SHIFT_C1_L_8822B)\n#define BITS_C1_L_8822B (BIT_MASK_C1_L_8822B << BIT_SHIFT_C1_L_8822B)\n#define BIT_CLEAR_C1_L_8822B(x) ((x) & (~BITS_C1_L_8822B))\n#define BIT_GET_C1_L_8822B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_C1_L_8822B) & BIT_MASK_C1_L_8822B)\n#define BIT_SET_C1_L_8822B(x, v) (BIT_CLEAR_C1_L_8822B(x) | BIT_C1_L_8822B(v))\n\n#define BIT_SHIFT_REG_FREQ_L_8822B 25\n#define BIT_MASK_REG_FREQ_L_8822B 0x7\n#define BIT_REG_FREQ_L_8822B(x)                                                \\\n\t(((x) & BIT_MASK_REG_FREQ_L_8822B) << BIT_SHIFT_REG_FREQ_L_8822B)\n#define BITS_REG_FREQ_L_8822B                                                  \\\n\t(BIT_MASK_REG_FREQ_L_8822B << BIT_SHIFT_REG_FREQ_L_8822B)\n#define BIT_CLEAR_REG_FREQ_L_8822B(x) ((x) & (~BITS_REG_FREQ_L_8822B))\n#define BIT_GET_REG_FREQ_L_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_REG_FREQ_L_8822B) & BIT_MASK_REG_FREQ_L_8822B)\n#define BIT_SET_REG_FREQ_L_8822B(x, v)                                         \\\n\t(BIT_CLEAR_REG_FREQ_L_8822B(x) | BIT_REG_FREQ_L_8822B(v))\n\n#define BIT_REG_EN_DUTY_8822B BIT(24)\n\n#define BIT_SHIFT_REG_MODE_8822B 22\n#define BIT_MASK_REG_MODE_8822B 0x3\n#define BIT_REG_MODE_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_REG_MODE_8822B) << BIT_SHIFT_REG_MODE_8822B)\n#define BITS_REG_MODE_8822B                                                    \\\n\t(BIT_MASK_REG_MODE_8822B << BIT_SHIFT_REG_MODE_8822B)\n#define BIT_CLEAR_REG_MODE_8822B(x) ((x) & (~BITS_REG_MODE_8822B))\n#define BIT_GET_REG_MODE_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_REG_MODE_8822B) & BIT_MASK_REG_MODE_8822B)\n#define BIT_SET_REG_MODE_8822B(x, v)                                           \\\n\t(BIT_CLEAR_REG_MODE_8822B(x) | BIT_REG_MODE_8822B(v))\n\n#define BIT_REG_EN_SP_8822B BIT(21)\n#define BIT_REG_AUTO_L_8822B BIT(20)\n#define BIT_SW18_SELD_BIT0_8822B BIT(19)\n#define BIT_SW18_POWOCP_8822B BIT(18)\n\n#define BIT_SHIFT_OCP_L1_8822B 15\n#define BIT_MASK_OCP_L1_8822B 0x7\n#define BIT_OCP_L1_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_OCP_L1_8822B) << BIT_SHIFT_OCP_L1_8822B)\n#define BITS_OCP_L1_8822B (BIT_MASK_OCP_L1_8822B << BIT_SHIFT_OCP_L1_8822B)\n#define BIT_CLEAR_OCP_L1_8822B(x) ((x) & (~BITS_OCP_L1_8822B))\n#define BIT_GET_OCP_L1_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_OCP_L1_8822B) & BIT_MASK_OCP_L1_8822B)\n#define BIT_SET_OCP_L1_8822B(x, v)                                             \\\n\t(BIT_CLEAR_OCP_L1_8822B(x) | BIT_OCP_L1_8822B(v))\n\n#define BIT_SHIFT_CF_L_8822B 13\n#define BIT_MASK_CF_L_8822B 0x3\n#define BIT_CF_L_8822B(x) (((x) & BIT_MASK_CF_L_8822B) << BIT_SHIFT_CF_L_8822B)\n#define BITS_CF_L_8822B (BIT_MASK_CF_L_8822B << BIT_SHIFT_CF_L_8822B)\n#define BIT_CLEAR_CF_L_8822B(x) ((x) & (~BITS_CF_L_8822B))\n#define BIT_GET_CF_L_8822B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_CF_L_8822B) & BIT_MASK_CF_L_8822B)\n#define BIT_SET_CF_L_8822B(x, v) (BIT_CLEAR_CF_L_8822B(x) | BIT_CF_L_8822B(v))\n\n#define BIT_SW18_FPWM_8822B BIT(11)\n#define BIT_SW18_SWEN_8822B BIT(9)\n#define BIT_SW18_LDEN_8822B BIT(8)\n#define BIT_MAC_ID_EN_8822B BIT(7)\n#define BIT_AFE_BGEN_8822B BIT(0)\n\n/* 2 REG_SYS_SWR_CTRL2_8822B */\n#define BIT_POW_ZCD_L_8822B BIT(31)\n#define BIT_AUTOZCD_L_8822B BIT(30)\n\n#define BIT_SHIFT_REG_DELAY_8822B 28\n#define BIT_MASK_REG_DELAY_8822B 0x3\n#define BIT_REG_DELAY_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_REG_DELAY_8822B) << BIT_SHIFT_REG_DELAY_8822B)\n#define BITS_REG_DELAY_8822B                                                   \\\n\t(BIT_MASK_REG_DELAY_8822B << BIT_SHIFT_REG_DELAY_8822B)\n#define BIT_CLEAR_REG_DELAY_8822B(x) ((x) & (~BITS_REG_DELAY_8822B))\n#define BIT_GET_REG_DELAY_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_REG_DELAY_8822B) & BIT_MASK_REG_DELAY_8822B)\n#define BIT_SET_REG_DELAY_8822B(x, v)                                          \\\n\t(BIT_CLEAR_REG_DELAY_8822B(x) | BIT_REG_DELAY_8822B(v))\n\n#define BIT_SHIFT_V15ADJ_L1_V1_8822B 24\n#define BIT_MASK_V15ADJ_L1_V1_8822B 0x7\n#define BIT_V15ADJ_L1_V1_8822B(x)                                              \\\n\t(((x) & BIT_MASK_V15ADJ_L1_V1_8822B) << BIT_SHIFT_V15ADJ_L1_V1_8822B)\n#define BITS_V15ADJ_L1_V1_8822B                                                \\\n\t(BIT_MASK_V15ADJ_L1_V1_8822B << BIT_SHIFT_V15ADJ_L1_V1_8822B)\n#define BIT_CLEAR_V15ADJ_L1_V1_8822B(x) ((x) & (~BITS_V15ADJ_L1_V1_8822B))\n#define BIT_GET_V15ADJ_L1_V1_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_V15ADJ_L1_V1_8822B) & BIT_MASK_V15ADJ_L1_V1_8822B)\n#define BIT_SET_V15ADJ_L1_V1_8822B(x, v)                                       \\\n\t(BIT_CLEAR_V15ADJ_L1_V1_8822B(x) | BIT_V15ADJ_L1_V1_8822B(v))\n\n#define BIT_SHIFT_VOL_L1_V1_8822B 20\n#define BIT_MASK_VOL_L1_V1_8822B 0xf\n#define BIT_VOL_L1_V1_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_VOL_L1_V1_8822B) << BIT_SHIFT_VOL_L1_V1_8822B)\n#define BITS_VOL_L1_V1_8822B                                                   \\\n\t(BIT_MASK_VOL_L1_V1_8822B << BIT_SHIFT_VOL_L1_V1_8822B)\n#define BIT_CLEAR_VOL_L1_V1_8822B(x) ((x) & (~BITS_VOL_L1_V1_8822B))\n#define BIT_GET_VOL_L1_V1_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_VOL_L1_V1_8822B) & BIT_MASK_VOL_L1_V1_8822B)\n#define BIT_SET_VOL_L1_V1_8822B(x, v)                                          \\\n\t(BIT_CLEAR_VOL_L1_V1_8822B(x) | BIT_VOL_L1_V1_8822B(v))\n\n#define BIT_SHIFT_IN_L1_V1_8822B 17\n#define BIT_MASK_IN_L1_V1_8822B 0x7\n#define BIT_IN_L1_V1_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_IN_L1_V1_8822B) << BIT_SHIFT_IN_L1_V1_8822B)\n#define BITS_IN_L1_V1_8822B                                                    \\\n\t(BIT_MASK_IN_L1_V1_8822B << BIT_SHIFT_IN_L1_V1_8822B)\n#define BIT_CLEAR_IN_L1_V1_8822B(x) ((x) & (~BITS_IN_L1_V1_8822B))\n#define BIT_GET_IN_L1_V1_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_IN_L1_V1_8822B) & BIT_MASK_IN_L1_V1_8822B)\n#define BIT_SET_IN_L1_V1_8822B(x, v)                                           \\\n\t(BIT_CLEAR_IN_L1_V1_8822B(x) | BIT_IN_L1_V1_8822B(v))\n\n#define BIT_SHIFT_TBOX_L1_8822B 15\n#define BIT_MASK_TBOX_L1_8822B 0x3\n#define BIT_TBOX_L1_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_TBOX_L1_8822B) << BIT_SHIFT_TBOX_L1_8822B)\n#define BITS_TBOX_L1_8822B (BIT_MASK_TBOX_L1_8822B << BIT_SHIFT_TBOX_L1_8822B)\n#define BIT_CLEAR_TBOX_L1_8822B(x) ((x) & (~BITS_TBOX_L1_8822B))\n#define BIT_GET_TBOX_L1_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TBOX_L1_8822B) & BIT_MASK_TBOX_L1_8822B)\n#define BIT_SET_TBOX_L1_8822B(x, v)                                            \\\n\t(BIT_CLEAR_TBOX_L1_8822B(x) | BIT_TBOX_L1_8822B(v))\n\n#define BIT_SW18_SEL_8822B BIT(13)\n\n/* 2 REG_NOT_VALID_8822B */\n#define BIT_SW18_SD_8822B BIT(10)\n\n#define BIT_SHIFT_R3_L_8822B 7\n#define BIT_MASK_R3_L_8822B 0x3\n#define BIT_R3_L_8822B(x) (((x) & BIT_MASK_R3_L_8822B) << BIT_SHIFT_R3_L_8822B)\n#define BITS_R3_L_8822B (BIT_MASK_R3_L_8822B << BIT_SHIFT_R3_L_8822B)\n#define BIT_CLEAR_R3_L_8822B(x) ((x) & (~BITS_R3_L_8822B))\n#define BIT_GET_R3_L_8822B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_R3_L_8822B) & BIT_MASK_R3_L_8822B)\n#define BIT_SET_R3_L_8822B(x, v) (BIT_CLEAR_R3_L_8822B(x) | BIT_R3_L_8822B(v))\n\n#define BIT_SHIFT_SW18_R2_8822B 5\n#define BIT_MASK_SW18_R2_8822B 0x3\n#define BIT_SW18_R2_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_SW18_R2_8822B) << BIT_SHIFT_SW18_R2_8822B)\n#define BITS_SW18_R2_8822B (BIT_MASK_SW18_R2_8822B << BIT_SHIFT_SW18_R2_8822B)\n#define BIT_CLEAR_SW18_R2_8822B(x) ((x) & (~BITS_SW18_R2_8822B))\n#define BIT_GET_SW18_R2_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_SW18_R2_8822B) & BIT_MASK_SW18_R2_8822B)\n#define BIT_SET_SW18_R2_8822B(x, v)                                            \\\n\t(BIT_CLEAR_SW18_R2_8822B(x) | BIT_SW18_R2_8822B(v))\n\n#define BIT_SHIFT_SW18_R1_8822B 3\n#define BIT_MASK_SW18_R1_8822B 0x3\n#define BIT_SW18_R1_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_SW18_R1_8822B) << BIT_SHIFT_SW18_R1_8822B)\n#define BITS_SW18_R1_8822B (BIT_MASK_SW18_R1_8822B << BIT_SHIFT_SW18_R1_8822B)\n#define BIT_CLEAR_SW18_R1_8822B(x) ((x) & (~BITS_SW18_R1_8822B))\n#define BIT_GET_SW18_R1_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_SW18_R1_8822B) & BIT_MASK_SW18_R1_8822B)\n#define BIT_SET_SW18_R1_8822B(x, v)                                            \\\n\t(BIT_CLEAR_SW18_R1_8822B(x) | BIT_SW18_R1_8822B(v))\n\n#define BIT_SHIFT_C3_L_C3_8822B 1\n#define BIT_MASK_C3_L_C3_8822B 0x3\n#define BIT_C3_L_C3_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_C3_L_C3_8822B) << BIT_SHIFT_C3_L_C3_8822B)\n#define BITS_C3_L_C3_8822B (BIT_MASK_C3_L_C3_8822B << BIT_SHIFT_C3_L_C3_8822B)\n#define BIT_CLEAR_C3_L_C3_8822B(x) ((x) & (~BITS_C3_L_C3_8822B))\n#define BIT_GET_C3_L_C3_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_C3_L_C3_8822B) & BIT_MASK_C3_L_C3_8822B)\n#define BIT_SET_C3_L_C3_8822B(x, v)                                            \\\n\t(BIT_CLEAR_C3_L_C3_8822B(x) | BIT_C3_L_C3_8822B(v))\n\n#define BIT_C2_L_BIT1_8822B BIT(0)\n\n/* 2 REG_SYS_SWR_CTRL3_8822B */\n#define BIT_SPS18_OCP_DIS_8822B BIT(31)\n\n#define BIT_SHIFT_SPS18_OCP_TH_8822B 16\n#define BIT_MASK_SPS18_OCP_TH_8822B 0x7fff\n#define BIT_SPS18_OCP_TH_8822B(x)                                              \\\n\t(((x) & BIT_MASK_SPS18_OCP_TH_8822B) << BIT_SHIFT_SPS18_OCP_TH_8822B)\n#define BITS_SPS18_OCP_TH_8822B                                                \\\n\t(BIT_MASK_SPS18_OCP_TH_8822B << BIT_SHIFT_SPS18_OCP_TH_8822B)\n#define BIT_CLEAR_SPS18_OCP_TH_8822B(x) ((x) & (~BITS_SPS18_OCP_TH_8822B))\n#define BIT_GET_SPS18_OCP_TH_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SPS18_OCP_TH_8822B) & BIT_MASK_SPS18_OCP_TH_8822B)\n#define BIT_SET_SPS18_OCP_TH_8822B(x, v)                                       \\\n\t(BIT_CLEAR_SPS18_OCP_TH_8822B(x) | BIT_SPS18_OCP_TH_8822B(v))\n\n#define BIT_SHIFT_OCP_WINDOW_8822B 0\n#define BIT_MASK_OCP_WINDOW_8822B 0xffff\n#define BIT_OCP_WINDOW_8822B(x)                                                \\\n\t(((x) & BIT_MASK_OCP_WINDOW_8822B) << BIT_SHIFT_OCP_WINDOW_8822B)\n#define BITS_OCP_WINDOW_8822B                                                  \\\n\t(BIT_MASK_OCP_WINDOW_8822B << BIT_SHIFT_OCP_WINDOW_8822B)\n#define BIT_CLEAR_OCP_WINDOW_8822B(x) ((x) & (~BITS_OCP_WINDOW_8822B))\n#define BIT_GET_OCP_WINDOW_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_OCP_WINDOW_8822B) & BIT_MASK_OCP_WINDOW_8822B)\n#define BIT_SET_OCP_WINDOW_8822B(x, v)                                         \\\n\t(BIT_CLEAR_OCP_WINDOW_8822B(x) | BIT_OCP_WINDOW_8822B(v))\n\n/* 2 REG_RSV_CTRL_8822B */\n#define BIT_HREG_DBG_8822B BIT(23)\n#define BIT_WLMCUIOIF_8822B BIT(8)\n#define BIT_LOCK_ALL_EN_8822B BIT(7)\n#define BIT_R_DIS_PRST_8822B BIT(6)\n#define BIT_WLOCK_1C_B6_8822B BIT(5)\n#define BIT_WLOCK_40_8822B BIT(4)\n#define BIT_WLOCK_08_8822B BIT(3)\n#define BIT_WLOCK_04_8822B BIT(2)\n#define BIT_WLOCK_00_8822B BIT(1)\n#define BIT_WLOCK_ALL_8822B BIT(0)\n\n/* 2 REG_RF_CTRL_8822B */\n#define BIT_RF_SDMRSTB_8822B BIT(2)\n#define BIT_RF_RSTB_8822B BIT(1)\n#define BIT_RF_EN_8822B BIT(0)\n\n/* 2 REG_AFE_LDO_CTRL_8822B */\n\n#define BIT_SHIFT_LPLDH12_RSV_8822B 29\n#define BIT_MASK_LPLDH12_RSV_8822B 0x7\n#define BIT_LPLDH12_RSV_8822B(x)                                               \\\n\t(((x) & BIT_MASK_LPLDH12_RSV_8822B) << BIT_SHIFT_LPLDH12_RSV_8822B)\n#define BITS_LPLDH12_RSV_8822B                                                 \\\n\t(BIT_MASK_LPLDH12_RSV_8822B << BIT_SHIFT_LPLDH12_RSV_8822B)\n#define BIT_CLEAR_LPLDH12_RSV_8822B(x) ((x) & (~BITS_LPLDH12_RSV_8822B))\n#define BIT_GET_LPLDH12_RSV_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_LPLDH12_RSV_8822B) & BIT_MASK_LPLDH12_RSV_8822B)\n#define BIT_SET_LPLDH12_RSV_8822B(x, v)                                        \\\n\t(BIT_CLEAR_LPLDH12_RSV_8822B(x) | BIT_LPLDH12_RSV_8822B(v))\n\n#define BIT_LPLDH12_SLP_8822B BIT(28)\n\n#define BIT_SHIFT_LPLDH12_VADJ_8822B 24\n#define BIT_MASK_LPLDH12_VADJ_8822B 0xf\n#define BIT_LPLDH12_VADJ_8822B(x)                                              \\\n\t(((x) & BIT_MASK_LPLDH12_VADJ_8822B) << BIT_SHIFT_LPLDH12_VADJ_8822B)\n#define BITS_LPLDH12_VADJ_8822B                                                \\\n\t(BIT_MASK_LPLDH12_VADJ_8822B << BIT_SHIFT_LPLDH12_VADJ_8822B)\n#define BIT_CLEAR_LPLDH12_VADJ_8822B(x) ((x) & (~BITS_LPLDH12_VADJ_8822B))\n#define BIT_GET_LPLDH12_VADJ_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_LPLDH12_VADJ_8822B) & BIT_MASK_LPLDH12_VADJ_8822B)\n#define BIT_SET_LPLDH12_VADJ_8822B(x, v)                                       \\\n\t(BIT_CLEAR_LPLDH12_VADJ_8822B(x) | BIT_LPLDH12_VADJ_8822B(v))\n\n#define BIT_LDH12_EN_8822B BIT(16)\n#define BIT_WLBBOFF_BIG_PWC_EN_8822B BIT(14)\n#define BIT_WLBBOFF_SMALL_PWC_EN_8822B BIT(13)\n#define BIT_WLMACOFF_BIG_PWC_EN_8822B BIT(12)\n#define BIT_WLPON_PWC_EN_8822B BIT(11)\n#define BIT_POW_REGU_P1_8822B BIT(10)\n#define BIT_LDOV12W_EN_8822B BIT(8)\n#define BIT_EX_XTAL_DRV_DIGI_8822B BIT(7)\n#define BIT_EX_XTAL_DRV_USB_8822B BIT(6)\n#define BIT_EX_XTAL_DRV_AFE_8822B BIT(5)\n#define BIT_EX_XTAL_DRV_RF2_8822B BIT(4)\n#define BIT_EX_XTAL_DRV_RF1_8822B BIT(3)\n#define BIT_POW_REGU_P0_8822B BIT(2)\n\n/* 2 REG_NOT_VALID_8822B */\n#define BIT_POW_PLL_LDO_8822B BIT(0)\n\n/* 2 REG_AFE_CTRL1_8822B */\n#define BIT_AGPIO_GPE_8822B BIT(31)\n\n#define BIT_SHIFT_XTAL_CAP_XI_8822B 25\n#define BIT_MASK_XTAL_CAP_XI_8822B 0x3f\n#define BIT_XTAL_CAP_XI_8822B(x)                                               \\\n\t(((x) & BIT_MASK_XTAL_CAP_XI_8822B) << BIT_SHIFT_XTAL_CAP_XI_8822B)\n#define BITS_XTAL_CAP_XI_8822B                                                 \\\n\t(BIT_MASK_XTAL_CAP_XI_8822B << BIT_SHIFT_XTAL_CAP_XI_8822B)\n#define BIT_CLEAR_XTAL_CAP_XI_8822B(x) ((x) & (~BITS_XTAL_CAP_XI_8822B))\n#define BIT_GET_XTAL_CAP_XI_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_XTAL_CAP_XI_8822B) & BIT_MASK_XTAL_CAP_XI_8822B)\n#define BIT_SET_XTAL_CAP_XI_8822B(x, v)                                        \\\n\t(BIT_CLEAR_XTAL_CAP_XI_8822B(x) | BIT_XTAL_CAP_XI_8822B(v))\n\n#define BIT_SHIFT_XTAL_DRV_DIGI_8822B 23\n#define BIT_MASK_XTAL_DRV_DIGI_8822B 0x3\n#define BIT_XTAL_DRV_DIGI_8822B(x)                                             \\\n\t(((x) & BIT_MASK_XTAL_DRV_DIGI_8822B) << BIT_SHIFT_XTAL_DRV_DIGI_8822B)\n#define BITS_XTAL_DRV_DIGI_8822B                                               \\\n\t(BIT_MASK_XTAL_DRV_DIGI_8822B << BIT_SHIFT_XTAL_DRV_DIGI_8822B)\n#define BIT_CLEAR_XTAL_DRV_DIGI_8822B(x) ((x) & (~BITS_XTAL_DRV_DIGI_8822B))\n#define BIT_GET_XTAL_DRV_DIGI_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8822B) & BIT_MASK_XTAL_DRV_DIGI_8822B)\n#define BIT_SET_XTAL_DRV_DIGI_8822B(x, v)                                      \\\n\t(BIT_CLEAR_XTAL_DRV_DIGI_8822B(x) | BIT_XTAL_DRV_DIGI_8822B(v))\n\n#define BIT_XTAL_DRV_USB_BIT1_8822B BIT(22)\n\n#define BIT_SHIFT_MAC_CLK_SEL_8822B 20\n#define BIT_MASK_MAC_CLK_SEL_8822B 0x3\n#define BIT_MAC_CLK_SEL_8822B(x)                                               \\\n\t(((x) & BIT_MASK_MAC_CLK_SEL_8822B) << BIT_SHIFT_MAC_CLK_SEL_8822B)\n#define BITS_MAC_CLK_SEL_8822B                                                 \\\n\t(BIT_MASK_MAC_CLK_SEL_8822B << BIT_SHIFT_MAC_CLK_SEL_8822B)\n#define BIT_CLEAR_MAC_CLK_SEL_8822B(x) ((x) & (~BITS_MAC_CLK_SEL_8822B))\n#define BIT_GET_MAC_CLK_SEL_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_MAC_CLK_SEL_8822B) & BIT_MASK_MAC_CLK_SEL_8822B)\n#define BIT_SET_MAC_CLK_SEL_8822B(x, v)                                        \\\n\t(BIT_CLEAR_MAC_CLK_SEL_8822B(x) | BIT_MAC_CLK_SEL_8822B(v))\n\n#define BIT_XTAL_DRV_USB_BIT0_8822B BIT(19)\n\n#define BIT_SHIFT_XTAL_DRV_AFE_8822B 17\n#define BIT_MASK_XTAL_DRV_AFE_8822B 0x3\n#define BIT_XTAL_DRV_AFE_8822B(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_DRV_AFE_8822B) << BIT_SHIFT_XTAL_DRV_AFE_8822B)\n#define BITS_XTAL_DRV_AFE_8822B                                                \\\n\t(BIT_MASK_XTAL_DRV_AFE_8822B << BIT_SHIFT_XTAL_DRV_AFE_8822B)\n#define BIT_CLEAR_XTAL_DRV_AFE_8822B(x) ((x) & (~BITS_XTAL_DRV_AFE_8822B))\n#define BIT_GET_XTAL_DRV_AFE_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_AFE_8822B) & BIT_MASK_XTAL_DRV_AFE_8822B)\n#define BIT_SET_XTAL_DRV_AFE_8822B(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_DRV_AFE_8822B(x) | BIT_XTAL_DRV_AFE_8822B(v))\n\n#define BIT_SHIFT_XTAL_DRV_RF2_8822B 15\n#define BIT_MASK_XTAL_DRV_RF2_8822B 0x3\n#define BIT_XTAL_DRV_RF2_8822B(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_DRV_RF2_8822B) << BIT_SHIFT_XTAL_DRV_RF2_8822B)\n#define BITS_XTAL_DRV_RF2_8822B                                                \\\n\t(BIT_MASK_XTAL_DRV_RF2_8822B << BIT_SHIFT_XTAL_DRV_RF2_8822B)\n#define BIT_CLEAR_XTAL_DRV_RF2_8822B(x) ((x) & (~BITS_XTAL_DRV_RF2_8822B))\n#define BIT_GET_XTAL_DRV_RF2_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_RF2_8822B) & BIT_MASK_XTAL_DRV_RF2_8822B)\n#define BIT_SET_XTAL_DRV_RF2_8822B(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_DRV_RF2_8822B(x) | BIT_XTAL_DRV_RF2_8822B(v))\n\n#define BIT_SHIFT_XTAL_DRV_RF1_8822B 13\n#define BIT_MASK_XTAL_DRV_RF1_8822B 0x3\n#define BIT_XTAL_DRV_RF1_8822B(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_DRV_RF1_8822B) << BIT_SHIFT_XTAL_DRV_RF1_8822B)\n#define BITS_XTAL_DRV_RF1_8822B                                                \\\n\t(BIT_MASK_XTAL_DRV_RF1_8822B << BIT_SHIFT_XTAL_DRV_RF1_8822B)\n#define BIT_CLEAR_XTAL_DRV_RF1_8822B(x) ((x) & (~BITS_XTAL_DRV_RF1_8822B))\n#define BIT_GET_XTAL_DRV_RF1_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_RF1_8822B) & BIT_MASK_XTAL_DRV_RF1_8822B)\n#define BIT_SET_XTAL_DRV_RF1_8822B(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_DRV_RF1_8822B(x) | BIT_XTAL_DRV_RF1_8822B(v))\n\n#define BIT_XTAL_DELAY_DIGI_8822B BIT(12)\n#define BIT_XTAL_DELAY_USB_8822B BIT(11)\n#define BIT_XTAL_DELAY_AFE_8822B BIT(10)\n\n#define BIT_SHIFT_XTAL_LDO_VREF_8822B 7\n#define BIT_MASK_XTAL_LDO_VREF_8822B 0x7\n#define BIT_XTAL_LDO_VREF_8822B(x)                                             \\\n\t(((x) & BIT_MASK_XTAL_LDO_VREF_8822B) << BIT_SHIFT_XTAL_LDO_VREF_8822B)\n#define BITS_XTAL_LDO_VREF_8822B                                               \\\n\t(BIT_MASK_XTAL_LDO_VREF_8822B << BIT_SHIFT_XTAL_LDO_VREF_8822B)\n#define BIT_CLEAR_XTAL_LDO_VREF_8822B(x) ((x) & (~BITS_XTAL_LDO_VREF_8822B))\n#define BIT_GET_XTAL_LDO_VREF_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_XTAL_LDO_VREF_8822B) & BIT_MASK_XTAL_LDO_VREF_8822B)\n#define BIT_SET_XTAL_LDO_VREF_8822B(x, v)                                      \\\n\t(BIT_CLEAR_XTAL_LDO_VREF_8822B(x) | BIT_XTAL_LDO_VREF_8822B(v))\n\n#define BIT_XTAL_XQSEL_RF_8822B BIT(6)\n#define BIT_XTAL_XQSEL_8822B BIT(5)\n\n#define BIT_SHIFT_XTAL_GMN_V2_8822B 3\n#define BIT_MASK_XTAL_GMN_V2_8822B 0x3\n#define BIT_XTAL_GMN_V2_8822B(x)                                               \\\n\t(((x) & BIT_MASK_XTAL_GMN_V2_8822B) << BIT_SHIFT_XTAL_GMN_V2_8822B)\n#define BITS_XTAL_GMN_V2_8822B                                                 \\\n\t(BIT_MASK_XTAL_GMN_V2_8822B << BIT_SHIFT_XTAL_GMN_V2_8822B)\n#define BIT_CLEAR_XTAL_GMN_V2_8822B(x) ((x) & (~BITS_XTAL_GMN_V2_8822B))\n#define BIT_GET_XTAL_GMN_V2_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_XTAL_GMN_V2_8822B) & BIT_MASK_XTAL_GMN_V2_8822B)\n#define BIT_SET_XTAL_GMN_V2_8822B(x, v)                                        \\\n\t(BIT_CLEAR_XTAL_GMN_V2_8822B(x) | BIT_XTAL_GMN_V2_8822B(v))\n\n#define BIT_SHIFT_XTAL_GMP_V2_8822B 1\n#define BIT_MASK_XTAL_GMP_V2_8822B 0x3\n#define BIT_XTAL_GMP_V2_8822B(x)                                               \\\n\t(((x) & BIT_MASK_XTAL_GMP_V2_8822B) << BIT_SHIFT_XTAL_GMP_V2_8822B)\n#define BITS_XTAL_GMP_V2_8822B                                                 \\\n\t(BIT_MASK_XTAL_GMP_V2_8822B << BIT_SHIFT_XTAL_GMP_V2_8822B)\n#define BIT_CLEAR_XTAL_GMP_V2_8822B(x) ((x) & (~BITS_XTAL_GMP_V2_8822B))\n#define BIT_GET_XTAL_GMP_V2_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_XTAL_GMP_V2_8822B) & BIT_MASK_XTAL_GMP_V2_8822B)\n#define BIT_SET_XTAL_GMP_V2_8822B(x, v)                                        \\\n\t(BIT_CLEAR_XTAL_GMP_V2_8822B(x) | BIT_XTAL_GMP_V2_8822B(v))\n\n#define BIT_XTAL_EN_8822B BIT(0)\n\n/* 2 REG_AFE_CTRL2_8822B */\n\n#define BIT_SHIFT_REG_C3_V4_8822B 30\n#define BIT_MASK_REG_C3_V4_8822B 0x3\n#define BIT_REG_C3_V4_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_REG_C3_V4_8822B) << BIT_SHIFT_REG_C3_V4_8822B)\n#define BITS_REG_C3_V4_8822B                                                   \\\n\t(BIT_MASK_REG_C3_V4_8822B << BIT_SHIFT_REG_C3_V4_8822B)\n#define BIT_CLEAR_REG_C3_V4_8822B(x) ((x) & (~BITS_REG_C3_V4_8822B))\n#define BIT_GET_REG_C3_V4_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_REG_C3_V4_8822B) & BIT_MASK_REG_C3_V4_8822B)\n#define BIT_SET_REG_C3_V4_8822B(x, v)                                          \\\n\t(BIT_CLEAR_REG_C3_V4_8822B(x) | BIT_REG_C3_V4_8822B(v))\n\n#define BIT_REG_CP_BIT1_8822B BIT(29)\n\n#define BIT_SHIFT_REG_RS_V4_8822B 26\n#define BIT_MASK_REG_RS_V4_8822B 0x7\n#define BIT_REG_RS_V4_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_REG_RS_V4_8822B) << BIT_SHIFT_REG_RS_V4_8822B)\n#define BITS_REG_RS_V4_8822B                                                   \\\n\t(BIT_MASK_REG_RS_V4_8822B << BIT_SHIFT_REG_RS_V4_8822B)\n#define BIT_CLEAR_REG_RS_V4_8822B(x) ((x) & (~BITS_REG_RS_V4_8822B))\n#define BIT_GET_REG_RS_V4_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_REG_RS_V4_8822B) & BIT_MASK_REG_RS_V4_8822B)\n#define BIT_SET_REG_RS_V4_8822B(x, v)                                          \\\n\t(BIT_CLEAR_REG_RS_V4_8822B(x) | BIT_REG_RS_V4_8822B(v))\n\n#define BIT_SHIFT_REG__CS_8822B 24\n#define BIT_MASK_REG__CS_8822B 0x3\n#define BIT_REG__CS_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_REG__CS_8822B) << BIT_SHIFT_REG__CS_8822B)\n#define BITS_REG__CS_8822B (BIT_MASK_REG__CS_8822B << BIT_SHIFT_REG__CS_8822B)\n#define BIT_CLEAR_REG__CS_8822B(x) ((x) & (~BITS_REG__CS_8822B))\n#define BIT_GET_REG__CS_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_REG__CS_8822B) & BIT_MASK_REG__CS_8822B)\n#define BIT_SET_REG__CS_8822B(x, v)                                            \\\n\t(BIT_CLEAR_REG__CS_8822B(x) | BIT_REG__CS_8822B(v))\n\n#define BIT_SHIFT_REG_CP_OFFSET_8822B 21\n#define BIT_MASK_REG_CP_OFFSET_8822B 0x7\n#define BIT_REG_CP_OFFSET_8822B(x)                                             \\\n\t(((x) & BIT_MASK_REG_CP_OFFSET_8822B) << BIT_SHIFT_REG_CP_OFFSET_8822B)\n#define BITS_REG_CP_OFFSET_8822B                                               \\\n\t(BIT_MASK_REG_CP_OFFSET_8822B << BIT_SHIFT_REG_CP_OFFSET_8822B)\n#define BIT_CLEAR_REG_CP_OFFSET_8822B(x) ((x) & (~BITS_REG_CP_OFFSET_8822B))\n#define BIT_GET_REG_CP_OFFSET_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_REG_CP_OFFSET_8822B) & BIT_MASK_REG_CP_OFFSET_8822B)\n#define BIT_SET_REG_CP_OFFSET_8822B(x, v)                                      \\\n\t(BIT_CLEAR_REG_CP_OFFSET_8822B(x) | BIT_REG_CP_OFFSET_8822B(v))\n\n#define BIT_SHIFT_CP_BIAS_8822B 18\n#define BIT_MASK_CP_BIAS_8822B 0x7\n#define BIT_CP_BIAS_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_CP_BIAS_8822B) << BIT_SHIFT_CP_BIAS_8822B)\n#define BITS_CP_BIAS_8822B (BIT_MASK_CP_BIAS_8822B << BIT_SHIFT_CP_BIAS_8822B)\n#define BIT_CLEAR_CP_BIAS_8822B(x) ((x) & (~BITS_CP_BIAS_8822B))\n#define BIT_GET_CP_BIAS_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_CP_BIAS_8822B) & BIT_MASK_CP_BIAS_8822B)\n#define BIT_SET_CP_BIAS_8822B(x, v)                                            \\\n\t(BIT_CLEAR_CP_BIAS_8822B(x) | BIT_CP_BIAS_8822B(v))\n\n#define BIT_REG_IDOUBLE_V2_8822B BIT(17)\n#define BIT_EN_SYN_8822B BIT(16)\n\n#define BIT_SHIFT_MCCO_8822B 14\n#define BIT_MASK_MCCO_8822B 0x3\n#define BIT_MCCO_8822B(x) (((x) & BIT_MASK_MCCO_8822B) << BIT_SHIFT_MCCO_8822B)\n#define BITS_MCCO_8822B (BIT_MASK_MCCO_8822B << BIT_SHIFT_MCCO_8822B)\n#define BIT_CLEAR_MCCO_8822B(x) ((x) & (~BITS_MCCO_8822B))\n#define BIT_GET_MCCO_8822B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_MCCO_8822B) & BIT_MASK_MCCO_8822B)\n#define BIT_SET_MCCO_8822B(x, v) (BIT_CLEAR_MCCO_8822B(x) | BIT_MCCO_8822B(v))\n\n#define BIT_SHIFT_REG_LDO_SEL_8822B 12\n#define BIT_MASK_REG_LDO_SEL_8822B 0x3\n#define BIT_REG_LDO_SEL_8822B(x)                                               \\\n\t(((x) & BIT_MASK_REG_LDO_SEL_8822B) << BIT_SHIFT_REG_LDO_SEL_8822B)\n#define BITS_REG_LDO_SEL_8822B                                                 \\\n\t(BIT_MASK_REG_LDO_SEL_8822B << BIT_SHIFT_REG_LDO_SEL_8822B)\n#define BIT_CLEAR_REG_LDO_SEL_8822B(x) ((x) & (~BITS_REG_LDO_SEL_8822B))\n#define BIT_GET_REG_LDO_SEL_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_REG_LDO_SEL_8822B) & BIT_MASK_REG_LDO_SEL_8822B)\n#define BIT_SET_REG_LDO_SEL_8822B(x, v)                                        \\\n\t(BIT_CLEAR_REG_LDO_SEL_8822B(x) | BIT_REG_LDO_SEL_8822B(v))\n\n#define BIT_REG_KVCO_V2_8822B BIT(10)\n#define BIT_AGPIO_GPO_8822B BIT(9)\n\n#define BIT_SHIFT_AGPIO_DRV_8822B 7\n#define BIT_MASK_AGPIO_DRV_8822B 0x3\n#define BIT_AGPIO_DRV_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_AGPIO_DRV_8822B) << BIT_SHIFT_AGPIO_DRV_8822B)\n#define BITS_AGPIO_DRV_8822B                                                   \\\n\t(BIT_MASK_AGPIO_DRV_8822B << BIT_SHIFT_AGPIO_DRV_8822B)\n#define BIT_CLEAR_AGPIO_DRV_8822B(x) ((x) & (~BITS_AGPIO_DRV_8822B))\n#define BIT_GET_AGPIO_DRV_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_AGPIO_DRV_8822B) & BIT_MASK_AGPIO_DRV_8822B)\n#define BIT_SET_AGPIO_DRV_8822B(x, v)                                          \\\n\t(BIT_CLEAR_AGPIO_DRV_8822B(x) | BIT_AGPIO_DRV_8822B(v))\n\n#define BIT_SHIFT_XTAL_CAP_XO_8822B 1\n#define BIT_MASK_XTAL_CAP_XO_8822B 0x3f\n#define BIT_XTAL_CAP_XO_8822B(x)                                               \\\n\t(((x) & BIT_MASK_XTAL_CAP_XO_8822B) << BIT_SHIFT_XTAL_CAP_XO_8822B)\n#define BITS_XTAL_CAP_XO_8822B                                                 \\\n\t(BIT_MASK_XTAL_CAP_XO_8822B << BIT_SHIFT_XTAL_CAP_XO_8822B)\n#define BIT_CLEAR_XTAL_CAP_XO_8822B(x) ((x) & (~BITS_XTAL_CAP_XO_8822B))\n#define BIT_GET_XTAL_CAP_XO_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_XTAL_CAP_XO_8822B) & BIT_MASK_XTAL_CAP_XO_8822B)\n#define BIT_SET_XTAL_CAP_XO_8822B(x, v)                                        \\\n\t(BIT_CLEAR_XTAL_CAP_XO_8822B(x) | BIT_XTAL_CAP_XO_8822B(v))\n\n#define BIT_POW_PLL_8822B BIT(0)\n\n/* 2 REG_AFE_CTRL3_8822B */\n\n#define BIT_SHIFT_PS_8822B 7\n#define BIT_MASK_PS_8822B 0x7\n#define BIT_PS_8822B(x) (((x) & BIT_MASK_PS_8822B) << BIT_SHIFT_PS_8822B)\n#define BITS_PS_8822B (BIT_MASK_PS_8822B << BIT_SHIFT_PS_8822B)\n#define BIT_CLEAR_PS_8822B(x) ((x) & (~BITS_PS_8822B))\n#define BIT_GET_PS_8822B(x) (((x) >> BIT_SHIFT_PS_8822B) & BIT_MASK_PS_8822B)\n#define BIT_SET_PS_8822B(x, v) (BIT_CLEAR_PS_8822B(x) | BIT_PS_8822B(v))\n\n#define BIT_PSEN_8822B BIT(6)\n#define BIT_DOGENB_8822B BIT(5)\n#define BIT_REG_MBIAS_8822B BIT(4)\n\n#define BIT_SHIFT_REG_R3_V4_8822B 1\n#define BIT_MASK_REG_R3_V4_8822B 0x7\n#define BIT_REG_R3_V4_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_REG_R3_V4_8822B) << BIT_SHIFT_REG_R3_V4_8822B)\n#define BITS_REG_R3_V4_8822B                                                   \\\n\t(BIT_MASK_REG_R3_V4_8822B << BIT_SHIFT_REG_R3_V4_8822B)\n#define BIT_CLEAR_REG_R3_V4_8822B(x) ((x) & (~BITS_REG_R3_V4_8822B))\n#define BIT_GET_REG_R3_V4_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_REG_R3_V4_8822B) & BIT_MASK_REG_R3_V4_8822B)\n#define BIT_SET_REG_R3_V4_8822B(x, v)                                          \\\n\t(BIT_CLEAR_REG_R3_V4_8822B(x) | BIT_REG_R3_V4_8822B(v))\n\n#define BIT_REG_CP_BIT0_8822B BIT(0)\n\n/* 2 REG_EFUSE_CTRL_8822B */\n#define BIT_EF_FLAG_8822B BIT(31)\n\n#define BIT_SHIFT_EF_PGPD_8822B 28\n#define BIT_MASK_EF_PGPD_8822B 0x7\n#define BIT_EF_PGPD_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_EF_PGPD_8822B) << BIT_SHIFT_EF_PGPD_8822B)\n#define BITS_EF_PGPD_8822B (BIT_MASK_EF_PGPD_8822B << BIT_SHIFT_EF_PGPD_8822B)\n#define BIT_CLEAR_EF_PGPD_8822B(x) ((x) & (~BITS_EF_PGPD_8822B))\n#define BIT_GET_EF_PGPD_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_PGPD_8822B) & BIT_MASK_EF_PGPD_8822B)\n#define BIT_SET_EF_PGPD_8822B(x, v)                                            \\\n\t(BIT_CLEAR_EF_PGPD_8822B(x) | BIT_EF_PGPD_8822B(v))\n\n#define BIT_SHIFT_EF_RDT_8822B 24\n#define BIT_MASK_EF_RDT_8822B 0xf\n#define BIT_EF_RDT_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_EF_RDT_8822B) << BIT_SHIFT_EF_RDT_8822B)\n#define BITS_EF_RDT_8822B (BIT_MASK_EF_RDT_8822B << BIT_SHIFT_EF_RDT_8822B)\n#define BIT_CLEAR_EF_RDT_8822B(x) ((x) & (~BITS_EF_RDT_8822B))\n#define BIT_GET_EF_RDT_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_EF_RDT_8822B) & BIT_MASK_EF_RDT_8822B)\n#define BIT_SET_EF_RDT_8822B(x, v)                                             \\\n\t(BIT_CLEAR_EF_RDT_8822B(x) | BIT_EF_RDT_8822B(v))\n\n#define BIT_SHIFT_EF_PGTS_8822B 20\n#define BIT_MASK_EF_PGTS_8822B 0xf\n#define BIT_EF_PGTS_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_EF_PGTS_8822B) << BIT_SHIFT_EF_PGTS_8822B)\n#define BITS_EF_PGTS_8822B (BIT_MASK_EF_PGTS_8822B << BIT_SHIFT_EF_PGTS_8822B)\n#define BIT_CLEAR_EF_PGTS_8822B(x) ((x) & (~BITS_EF_PGTS_8822B))\n#define BIT_GET_EF_PGTS_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_PGTS_8822B) & BIT_MASK_EF_PGTS_8822B)\n#define BIT_SET_EF_PGTS_8822B(x, v)                                            \\\n\t(BIT_CLEAR_EF_PGTS_8822B(x) | BIT_EF_PGTS_8822B(v))\n\n#define BIT_EF_PDWN_8822B BIT(19)\n#define BIT_EF_ALDEN_8822B BIT(18)\n\n#define BIT_SHIFT_EF_ADDR_8822B 8\n#define BIT_MASK_EF_ADDR_8822B 0x3ff\n#define BIT_EF_ADDR_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_EF_ADDR_8822B) << BIT_SHIFT_EF_ADDR_8822B)\n#define BITS_EF_ADDR_8822B (BIT_MASK_EF_ADDR_8822B << BIT_SHIFT_EF_ADDR_8822B)\n#define BIT_CLEAR_EF_ADDR_8822B(x) ((x) & (~BITS_EF_ADDR_8822B))\n#define BIT_GET_EF_ADDR_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_ADDR_8822B) & BIT_MASK_EF_ADDR_8822B)\n#define BIT_SET_EF_ADDR_8822B(x, v)                                            \\\n\t(BIT_CLEAR_EF_ADDR_8822B(x) | BIT_EF_ADDR_8822B(v))\n\n#define BIT_SHIFT_EF_DATA_8822B 0\n#define BIT_MASK_EF_DATA_8822B 0xff\n#define BIT_EF_DATA_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_EF_DATA_8822B) << BIT_SHIFT_EF_DATA_8822B)\n#define BITS_EF_DATA_8822B (BIT_MASK_EF_DATA_8822B << BIT_SHIFT_EF_DATA_8822B)\n#define BIT_CLEAR_EF_DATA_8822B(x) ((x) & (~BITS_EF_DATA_8822B))\n#define BIT_GET_EF_DATA_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_DATA_8822B) & BIT_MASK_EF_DATA_8822B)\n#define BIT_SET_EF_DATA_8822B(x, v)                                            \\\n\t(BIT_CLEAR_EF_DATA_8822B(x) | BIT_EF_DATA_8822B(v))\n\n/* 2 REG_LDO_EFUSE_CTRL_8822B */\n#define BIT_LDOE25_EN_8822B BIT(31)\n\n#define BIT_SHIFT_LDOE25_V12ADJ_L_8822B 27\n#define BIT_MASK_LDOE25_V12ADJ_L_8822B 0xf\n#define BIT_LDOE25_V12ADJ_L_8822B(x)                                           \\\n\t(((x) & BIT_MASK_LDOE25_V12ADJ_L_8822B)                                \\\n\t << BIT_SHIFT_LDOE25_V12ADJ_L_8822B)\n#define BITS_LDOE25_V12ADJ_L_8822B                                             \\\n\t(BIT_MASK_LDOE25_V12ADJ_L_8822B << BIT_SHIFT_LDOE25_V12ADJ_L_8822B)\n#define BIT_CLEAR_LDOE25_V12ADJ_L_8822B(x) ((x) & (~BITS_LDOE25_V12ADJ_L_8822B))\n#define BIT_GET_LDOE25_V12ADJ_L_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8822B) &                            \\\n\t BIT_MASK_LDOE25_V12ADJ_L_8822B)\n#define BIT_SET_LDOE25_V12ADJ_L_8822B(x, v)                                    \\\n\t(BIT_CLEAR_LDOE25_V12ADJ_L_8822B(x) | BIT_LDOE25_V12ADJ_L_8822B(v))\n\n#define BIT_EF_CRES_SEL_8822B BIT(26)\n\n#define BIT_SHIFT_EF_SCAN_START_V1_8822B 16\n#define BIT_MASK_EF_SCAN_START_V1_8822B 0x3ff\n#define BIT_EF_SCAN_START_V1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_EF_SCAN_START_V1_8822B)                               \\\n\t << BIT_SHIFT_EF_SCAN_START_V1_8822B)\n#define BITS_EF_SCAN_START_V1_8822B                                            \\\n\t(BIT_MASK_EF_SCAN_START_V1_8822B << BIT_SHIFT_EF_SCAN_START_V1_8822B)\n#define BIT_CLEAR_EF_SCAN_START_V1_8822B(x)                                    \\\n\t((x) & (~BITS_EF_SCAN_START_V1_8822B))\n#define BIT_GET_EF_SCAN_START_V1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_EF_SCAN_START_V1_8822B) &                           \\\n\t BIT_MASK_EF_SCAN_START_V1_8822B)\n#define BIT_SET_EF_SCAN_START_V1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_EF_SCAN_START_V1_8822B(x) | BIT_EF_SCAN_START_V1_8822B(v))\n\n#define BIT_SHIFT_EF_SCAN_END_8822B 12\n#define BIT_MASK_EF_SCAN_END_8822B 0xf\n#define BIT_EF_SCAN_END_8822B(x)                                               \\\n\t(((x) & BIT_MASK_EF_SCAN_END_8822B) << BIT_SHIFT_EF_SCAN_END_8822B)\n#define BITS_EF_SCAN_END_8822B                                                 \\\n\t(BIT_MASK_EF_SCAN_END_8822B << BIT_SHIFT_EF_SCAN_END_8822B)\n#define BIT_CLEAR_EF_SCAN_END_8822B(x) ((x) & (~BITS_EF_SCAN_END_8822B))\n#define BIT_GET_EF_SCAN_END_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_EF_SCAN_END_8822B) & BIT_MASK_EF_SCAN_END_8822B)\n#define BIT_SET_EF_SCAN_END_8822B(x, v)                                        \\\n\t(BIT_CLEAR_EF_SCAN_END_8822B(x) | BIT_EF_SCAN_END_8822B(v))\n\n#define BIT_EF_PD_DIS_8822B BIT(11)\n\n#define BIT_SHIFT_EF_CELL_SEL_8822B 8\n#define BIT_MASK_EF_CELL_SEL_8822B 0x3\n#define BIT_EF_CELL_SEL_8822B(x)                                               \\\n\t(((x) & BIT_MASK_EF_CELL_SEL_8822B) << BIT_SHIFT_EF_CELL_SEL_8822B)\n#define BITS_EF_CELL_SEL_8822B                                                 \\\n\t(BIT_MASK_EF_CELL_SEL_8822B << BIT_SHIFT_EF_CELL_SEL_8822B)\n#define BIT_CLEAR_EF_CELL_SEL_8822B(x) ((x) & (~BITS_EF_CELL_SEL_8822B))\n#define BIT_GET_EF_CELL_SEL_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_EF_CELL_SEL_8822B) & BIT_MASK_EF_CELL_SEL_8822B)\n#define BIT_SET_EF_CELL_SEL_8822B(x, v)                                        \\\n\t(BIT_CLEAR_EF_CELL_SEL_8822B(x) | BIT_EF_CELL_SEL_8822B(v))\n\n#define BIT_EF_TRPT_8822B BIT(7)\n\n#define BIT_SHIFT_EF_TTHD_8822B 0\n#define BIT_MASK_EF_TTHD_8822B 0x7f\n#define BIT_EF_TTHD_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_EF_TTHD_8822B) << BIT_SHIFT_EF_TTHD_8822B)\n#define BITS_EF_TTHD_8822B (BIT_MASK_EF_TTHD_8822B << BIT_SHIFT_EF_TTHD_8822B)\n#define BIT_CLEAR_EF_TTHD_8822B(x) ((x) & (~BITS_EF_TTHD_8822B))\n#define BIT_GET_EF_TTHD_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_TTHD_8822B) & BIT_MASK_EF_TTHD_8822B)\n#define BIT_SET_EF_TTHD_8822B(x, v)                                            \\\n\t(BIT_CLEAR_EF_TTHD_8822B(x) | BIT_EF_TTHD_8822B(v))\n\n/* 2 REG_PWR_OPTION_CTRL_8822B */\n\n#define BIT_SHIFT_DBG_SEL_V1_8822B 16\n#define BIT_MASK_DBG_SEL_V1_8822B 0xff\n#define BIT_DBG_SEL_V1_8822B(x)                                                \\\n\t(((x) & BIT_MASK_DBG_SEL_V1_8822B) << BIT_SHIFT_DBG_SEL_V1_8822B)\n#define BITS_DBG_SEL_V1_8822B                                                  \\\n\t(BIT_MASK_DBG_SEL_V1_8822B << BIT_SHIFT_DBG_SEL_V1_8822B)\n#define BIT_CLEAR_DBG_SEL_V1_8822B(x) ((x) & (~BITS_DBG_SEL_V1_8822B))\n#define BIT_GET_DBG_SEL_V1_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DBG_SEL_V1_8822B) & BIT_MASK_DBG_SEL_V1_8822B)\n#define BIT_SET_DBG_SEL_V1_8822B(x, v)                                         \\\n\t(BIT_CLEAR_DBG_SEL_V1_8822B(x) | BIT_DBG_SEL_V1_8822B(v))\n\n#define BIT_SHIFT_DBG_SEL_BYTE_8822B 14\n#define BIT_MASK_DBG_SEL_BYTE_8822B 0x3\n#define BIT_DBG_SEL_BYTE_8822B(x)                                              \\\n\t(((x) & BIT_MASK_DBG_SEL_BYTE_8822B) << BIT_SHIFT_DBG_SEL_BYTE_8822B)\n#define BITS_DBG_SEL_BYTE_8822B                                                \\\n\t(BIT_MASK_DBG_SEL_BYTE_8822B << BIT_SHIFT_DBG_SEL_BYTE_8822B)\n#define BIT_CLEAR_DBG_SEL_BYTE_8822B(x) ((x) & (~BITS_DBG_SEL_BYTE_8822B))\n#define BIT_GET_DBG_SEL_BYTE_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DBG_SEL_BYTE_8822B) & BIT_MASK_DBG_SEL_BYTE_8822B)\n#define BIT_SET_DBG_SEL_BYTE_8822B(x, v)                                       \\\n\t(BIT_CLEAR_DBG_SEL_BYTE_8822B(x) | BIT_DBG_SEL_BYTE_8822B(v))\n\n#define BIT_SHIFT_STD_L1_V1_8822B 12\n#define BIT_MASK_STD_L1_V1_8822B 0x3\n#define BIT_STD_L1_V1_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_STD_L1_V1_8822B) << BIT_SHIFT_STD_L1_V1_8822B)\n#define BITS_STD_L1_V1_8822B                                                   \\\n\t(BIT_MASK_STD_L1_V1_8822B << BIT_SHIFT_STD_L1_V1_8822B)\n#define BIT_CLEAR_STD_L1_V1_8822B(x) ((x) & (~BITS_STD_L1_V1_8822B))\n#define BIT_GET_STD_L1_V1_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_STD_L1_V1_8822B) & BIT_MASK_STD_L1_V1_8822B)\n#define BIT_SET_STD_L1_V1_8822B(x, v)                                          \\\n\t(BIT_CLEAR_STD_L1_V1_8822B(x) | BIT_STD_L1_V1_8822B(v))\n\n#define BIT_SYSON_DBG_PAD_E2_8822B BIT(11)\n#define BIT_SYSON_LED_PAD_E2_8822B BIT(10)\n#define BIT_SYSON_GPEE_PAD_E2_8822B BIT(9)\n#define BIT_SYSON_PCI_PAD_E2_8822B BIT(8)\n#define BIT_AUTO_SW_LDO_VOL_EN_8822B BIT(7)\n\n#define BIT_SHIFT_SYSON_SPS0WWV_WT_8822B 4\n#define BIT_MASK_SYSON_SPS0WWV_WT_8822B 0x3\n#define BIT_SYSON_SPS0WWV_WT_8822B(x)                                          \\\n\t(((x) & BIT_MASK_SYSON_SPS0WWV_WT_8822B)                               \\\n\t << BIT_SHIFT_SYSON_SPS0WWV_WT_8822B)\n#define BITS_SYSON_SPS0WWV_WT_8822B                                            \\\n\t(BIT_MASK_SYSON_SPS0WWV_WT_8822B << BIT_SHIFT_SYSON_SPS0WWV_WT_8822B)\n#define BIT_CLEAR_SYSON_SPS0WWV_WT_8822B(x)                                    \\\n\t((x) & (~BITS_SYSON_SPS0WWV_WT_8822B))\n#define BIT_GET_SYSON_SPS0WWV_WT_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8822B) &                           \\\n\t BIT_MASK_SYSON_SPS0WWV_WT_8822B)\n#define BIT_SET_SYSON_SPS0WWV_WT_8822B(x, v)                                   \\\n\t(BIT_CLEAR_SYSON_SPS0WWV_WT_8822B(x) | BIT_SYSON_SPS0WWV_WT_8822B(v))\n\n#define BIT_SHIFT_SYSON_SPS0LDO_WT_8822B 2\n#define BIT_MASK_SYSON_SPS0LDO_WT_8822B 0x3\n#define BIT_SYSON_SPS0LDO_WT_8822B(x)                                          \\\n\t(((x) & BIT_MASK_SYSON_SPS0LDO_WT_8822B)                               \\\n\t << BIT_SHIFT_SYSON_SPS0LDO_WT_8822B)\n#define BITS_SYSON_SPS0LDO_WT_8822B                                            \\\n\t(BIT_MASK_SYSON_SPS0LDO_WT_8822B << BIT_SHIFT_SYSON_SPS0LDO_WT_8822B)\n#define BIT_CLEAR_SYSON_SPS0LDO_WT_8822B(x)                                    \\\n\t((x) & (~BITS_SYSON_SPS0LDO_WT_8822B))\n#define BIT_GET_SYSON_SPS0LDO_WT_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8822B) &                           \\\n\t BIT_MASK_SYSON_SPS0LDO_WT_8822B)\n#define BIT_SET_SYSON_SPS0LDO_WT_8822B(x, v)                                   \\\n\t(BIT_CLEAR_SYSON_SPS0LDO_WT_8822B(x) | BIT_SYSON_SPS0LDO_WT_8822B(v))\n\n#define BIT_SHIFT_SYSON_RCLK_SCALE_8822B 0\n#define BIT_MASK_SYSON_RCLK_SCALE_8822B 0x3\n#define BIT_SYSON_RCLK_SCALE_8822B(x)                                          \\\n\t(((x) & BIT_MASK_SYSON_RCLK_SCALE_8822B)                               \\\n\t << BIT_SHIFT_SYSON_RCLK_SCALE_8822B)\n#define BITS_SYSON_RCLK_SCALE_8822B                                            \\\n\t(BIT_MASK_SYSON_RCLK_SCALE_8822B << BIT_SHIFT_SYSON_RCLK_SCALE_8822B)\n#define BIT_CLEAR_SYSON_RCLK_SCALE_8822B(x)                                    \\\n\t((x) & (~BITS_SYSON_RCLK_SCALE_8822B))\n#define BIT_GET_SYSON_RCLK_SCALE_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8822B) &                           \\\n\t BIT_MASK_SYSON_RCLK_SCALE_8822B)\n#define BIT_SET_SYSON_RCLK_SCALE_8822B(x, v)                                   \\\n\t(BIT_CLEAR_SYSON_RCLK_SCALE_8822B(x) | BIT_SYSON_RCLK_SCALE_8822B(v))\n\n/* 2 REG_CAL_TIMER_8822B */\n\n#define BIT_SHIFT_MATCH_CNT_8822B 8\n#define BIT_MASK_MATCH_CNT_8822B 0xff\n#define BIT_MATCH_CNT_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B)\n#define BITS_MATCH_CNT_8822B                                                   \\\n\t(BIT_MASK_MATCH_CNT_8822B << BIT_SHIFT_MATCH_CNT_8822B)\n#define BIT_CLEAR_MATCH_CNT_8822B(x) ((x) & (~BITS_MATCH_CNT_8822B))\n#define BIT_GET_MATCH_CNT_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B)\n#define BIT_SET_MATCH_CNT_8822B(x, v)                                          \\\n\t(BIT_CLEAR_MATCH_CNT_8822B(x) | BIT_MATCH_CNT_8822B(v))\n\n#define BIT_SHIFT_CAL_SCAL_8822B 0\n#define BIT_MASK_CAL_SCAL_8822B 0xff\n#define BIT_CAL_SCAL_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_CAL_SCAL_8822B) << BIT_SHIFT_CAL_SCAL_8822B)\n#define BITS_CAL_SCAL_8822B                                                    \\\n\t(BIT_MASK_CAL_SCAL_8822B << BIT_SHIFT_CAL_SCAL_8822B)\n#define BIT_CLEAR_CAL_SCAL_8822B(x) ((x) & (~BITS_CAL_SCAL_8822B))\n#define BIT_GET_CAL_SCAL_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_CAL_SCAL_8822B) & BIT_MASK_CAL_SCAL_8822B)\n#define BIT_SET_CAL_SCAL_8822B(x, v)                                           \\\n\t(BIT_CLEAR_CAL_SCAL_8822B(x) | BIT_CAL_SCAL_8822B(v))\n\n/* 2 REG_ACLK_MON_8822B */\n\n#define BIT_SHIFT_RCLK_MON_8822B 5\n#define BIT_MASK_RCLK_MON_8822B 0x7ff\n#define BIT_RCLK_MON_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_RCLK_MON_8822B) << BIT_SHIFT_RCLK_MON_8822B)\n#define BITS_RCLK_MON_8822B                                                    \\\n\t(BIT_MASK_RCLK_MON_8822B << BIT_SHIFT_RCLK_MON_8822B)\n#define BIT_CLEAR_RCLK_MON_8822B(x) ((x) & (~BITS_RCLK_MON_8822B))\n#define BIT_GET_RCLK_MON_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RCLK_MON_8822B) & BIT_MASK_RCLK_MON_8822B)\n#define BIT_SET_RCLK_MON_8822B(x, v)                                           \\\n\t(BIT_CLEAR_RCLK_MON_8822B(x) | BIT_RCLK_MON_8822B(v))\n\n#define BIT_CAL_EN_8822B BIT(4)\n\n#define BIT_SHIFT_DPSTU_8822B 2\n#define BIT_MASK_DPSTU_8822B 0x3\n#define BIT_DPSTU_8822B(x)                                                     \\\n\t(((x) & BIT_MASK_DPSTU_8822B) << BIT_SHIFT_DPSTU_8822B)\n#define BITS_DPSTU_8822B (BIT_MASK_DPSTU_8822B << BIT_SHIFT_DPSTU_8822B)\n#define BIT_CLEAR_DPSTU_8822B(x) ((x) & (~BITS_DPSTU_8822B))\n#define BIT_GET_DPSTU_8822B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DPSTU_8822B) & BIT_MASK_DPSTU_8822B)\n#define BIT_SET_DPSTU_8822B(x, v)                                              \\\n\t(BIT_CLEAR_DPSTU_8822B(x) | BIT_DPSTU_8822B(v))\n\n#define BIT_SUS_16X_8822B BIT(1)\n\n/* 2 REG_GPIO_MUXCFG_8822B */\n#define BIT_FSPI_EN_8822B BIT(19)\n#define BIT_WL_RTS_EXT_32K_SEL_8822B BIT(18)\n#define BIT_WLGP_SPI_EN_8822B BIT(16)\n#define BIT_SIC_LBK_8822B BIT(15)\n#define BIT_ENHTP_8822B BIT(14)\n#define BIT_ENSIC_8822B BIT(12)\n#define BIT_SIC_SWRST_8822B BIT(11)\n#define BIT_PO_WIFI_PTA_PINS_8822B BIT(10)\n#define BIT_PO_BT_PTA_PINS_8822B BIT(9)\n#define BIT_ENUART_8822B BIT(8)\n\n#define BIT_SHIFT_BTMODE_8822B 6\n#define BIT_MASK_BTMODE_8822B 0x3\n#define BIT_BTMODE_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_BTMODE_8822B) << BIT_SHIFT_BTMODE_8822B)\n#define BITS_BTMODE_8822B (BIT_MASK_BTMODE_8822B << BIT_SHIFT_BTMODE_8822B)\n#define BIT_CLEAR_BTMODE_8822B(x) ((x) & (~BITS_BTMODE_8822B))\n#define BIT_GET_BTMODE_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_BTMODE_8822B) & BIT_MASK_BTMODE_8822B)\n#define BIT_SET_BTMODE_8822B(x, v)                                             \\\n\t(BIT_CLEAR_BTMODE_8822B(x) | BIT_BTMODE_8822B(v))\n\n#define BIT_ENBT_8822B BIT(5)\n#define BIT_EROM_EN_8822B BIT(4)\n#define BIT_WLRFE_6_7_EN_8822B BIT(3)\n#define BIT_WLRFE_4_5_EN_8822B BIT(2)\n\n#define BIT_SHIFT_GPIOSEL_8822B 0\n#define BIT_MASK_GPIOSEL_8822B 0x3\n#define BIT_GPIOSEL_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_GPIOSEL_8822B) << BIT_SHIFT_GPIOSEL_8822B)\n#define BITS_GPIOSEL_8822B (BIT_MASK_GPIOSEL_8822B << BIT_SHIFT_GPIOSEL_8822B)\n#define BIT_CLEAR_GPIOSEL_8822B(x) ((x) & (~BITS_GPIOSEL_8822B))\n#define BIT_GET_GPIOSEL_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_GPIOSEL_8822B) & BIT_MASK_GPIOSEL_8822B)\n#define BIT_SET_GPIOSEL_8822B(x, v)                                            \\\n\t(BIT_CLEAR_GPIOSEL_8822B(x) | BIT_GPIOSEL_8822B(v))\n\n/* 2 REG_GPIO_PIN_CTRL_8822B */\n\n#define BIT_SHIFT_GPIO_MOD_7_TO_0_8822B 24\n#define BIT_MASK_GPIO_MOD_7_TO_0_8822B 0xff\n#define BIT_GPIO_MOD_7_TO_0_8822B(x)                                           \\\n\t(((x) & BIT_MASK_GPIO_MOD_7_TO_0_8822B)                                \\\n\t << BIT_SHIFT_GPIO_MOD_7_TO_0_8822B)\n#define BITS_GPIO_MOD_7_TO_0_8822B                                             \\\n\t(BIT_MASK_GPIO_MOD_7_TO_0_8822B << BIT_SHIFT_GPIO_MOD_7_TO_0_8822B)\n#define BIT_CLEAR_GPIO_MOD_7_TO_0_8822B(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8822B))\n#define BIT_GET_GPIO_MOD_7_TO_0_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8822B) &                            \\\n\t BIT_MASK_GPIO_MOD_7_TO_0_8822B)\n#define BIT_SET_GPIO_MOD_7_TO_0_8822B(x, v)                                    \\\n\t(BIT_CLEAR_GPIO_MOD_7_TO_0_8822B(x) | BIT_GPIO_MOD_7_TO_0_8822B(v))\n\n#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B 16\n#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B 0xff\n#define BIT_GPIO_IO_SEL_7_TO_0_8822B(x)                                        \\\n\t(((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B)                             \\\n\t << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B)\n#define BITS_GPIO_IO_SEL_7_TO_0_8822B                                          \\\n\t(BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B                                     \\\n\t << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B)\n#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822B(x)                                  \\\n\t((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8822B))\n#define BIT_GET_GPIO_IO_SEL_7_TO_0_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B) &                         \\\n\t BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B)\n#define BIT_SET_GPIO_IO_SEL_7_TO_0_8822B(x, v)                                 \\\n\t(BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822B(x) |                               \\\n\t BIT_GPIO_IO_SEL_7_TO_0_8822B(v))\n\n#define BIT_SHIFT_GPIO_OUT_7_TO_0_8822B 8\n#define BIT_MASK_GPIO_OUT_7_TO_0_8822B 0xff\n#define BIT_GPIO_OUT_7_TO_0_8822B(x)                                           \\\n\t(((x) & BIT_MASK_GPIO_OUT_7_TO_0_8822B)                                \\\n\t << BIT_SHIFT_GPIO_OUT_7_TO_0_8822B)\n#define BITS_GPIO_OUT_7_TO_0_8822B                                             \\\n\t(BIT_MASK_GPIO_OUT_7_TO_0_8822B << BIT_SHIFT_GPIO_OUT_7_TO_0_8822B)\n#define BIT_CLEAR_GPIO_OUT_7_TO_0_8822B(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8822B))\n#define BIT_GET_GPIO_OUT_7_TO_0_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8822B) &                            \\\n\t BIT_MASK_GPIO_OUT_7_TO_0_8822B)\n#define BIT_SET_GPIO_OUT_7_TO_0_8822B(x, v)                                    \\\n\t(BIT_CLEAR_GPIO_OUT_7_TO_0_8822B(x) | BIT_GPIO_OUT_7_TO_0_8822B(v))\n\n#define BIT_SHIFT_GPIO_IN_7_TO_0_8822B 0\n#define BIT_MASK_GPIO_IN_7_TO_0_8822B 0xff\n#define BIT_GPIO_IN_7_TO_0_8822B(x)                                            \\\n\t(((x) & BIT_MASK_GPIO_IN_7_TO_0_8822B)                                 \\\n\t << BIT_SHIFT_GPIO_IN_7_TO_0_8822B)\n#define BITS_GPIO_IN_7_TO_0_8822B                                              \\\n\t(BIT_MASK_GPIO_IN_7_TO_0_8822B << BIT_SHIFT_GPIO_IN_7_TO_0_8822B)\n#define BIT_CLEAR_GPIO_IN_7_TO_0_8822B(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8822B))\n#define BIT_GET_GPIO_IN_7_TO_0_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8822B) &                             \\\n\t BIT_MASK_GPIO_IN_7_TO_0_8822B)\n#define BIT_SET_GPIO_IN_7_TO_0_8822B(x, v)                                     \\\n\t(BIT_CLEAR_GPIO_IN_7_TO_0_8822B(x) | BIT_GPIO_IN_7_TO_0_8822B(v))\n\n/* 2 REG_GPIO_INTM_8822B */\n\n#define BIT_SHIFT_MUXDBG_SEL_8822B 30\n#define BIT_MASK_MUXDBG_SEL_8822B 0x3\n#define BIT_MUXDBG_SEL_8822B(x)                                                \\\n\t(((x) & BIT_MASK_MUXDBG_SEL_8822B) << BIT_SHIFT_MUXDBG_SEL_8822B)\n#define BITS_MUXDBG_SEL_8822B                                                  \\\n\t(BIT_MASK_MUXDBG_SEL_8822B << BIT_SHIFT_MUXDBG_SEL_8822B)\n#define BIT_CLEAR_MUXDBG_SEL_8822B(x) ((x) & (~BITS_MUXDBG_SEL_8822B))\n#define BIT_GET_MUXDBG_SEL_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_MUXDBG_SEL_8822B) & BIT_MASK_MUXDBG_SEL_8822B)\n#define BIT_SET_MUXDBG_SEL_8822B(x, v)                                         \\\n\t(BIT_CLEAR_MUXDBG_SEL_8822B(x) | BIT_MUXDBG_SEL_8822B(v))\n\n#define BIT_EXTWOL_SEL_8822B BIT(17)\n#define BIT_EXTWOL_EN_8822B BIT(16)\n#define BIT_GPIOF_INT_MD_8822B BIT(15)\n#define BIT_GPIOE_INT_MD_8822B BIT(14)\n#define BIT_GPIOD_INT_MD_8822B BIT(13)\n#define BIT_GPIOF_INT_MD_8822B BIT(15)\n#define BIT_GPIOE_INT_MD_8822B BIT(14)\n#define BIT_GPIOD_INT_MD_8822B BIT(13)\n#define BIT_GPIOC_INT_MD_8822B BIT(12)\n#define BIT_GPIOB_INT_MD_8822B BIT(11)\n#define BIT_GPIOA_INT_MD_8822B BIT(10)\n#define BIT_GPIO9_INT_MD_8822B BIT(9)\n#define BIT_GPIO8_INT_MD_8822B BIT(8)\n#define BIT_GPIO7_INT_MD_8822B BIT(7)\n#define BIT_GPIO6_INT_MD_8822B BIT(6)\n#define BIT_GPIO5_INT_MD_8822B BIT(5)\n#define BIT_GPIO4_INT_MD_8822B BIT(4)\n#define BIT_GPIO3_INT_MD_8822B BIT(3)\n#define BIT_GPIO2_INT_MD_8822B BIT(2)\n#define BIT_GPIO1_INT_MD_8822B BIT(1)\n#define BIT_GPIO0_INT_MD_8822B BIT(0)\n\n/* 2 REG_LED_CFG_8822B */\n#define BIT_GPIO3_WL_CTRL_EN_8822B BIT(27)\n#define BIT_LNAON_SEL_EN_8822B BIT(26)\n#define BIT_PAPE_SEL_EN_8822B BIT(25)\n#define BIT_DPDT_WLBT_SEL_8822B BIT(24)\n#define BIT_DPDT_SEL_EN_8822B BIT(23)\n#define BIT_GPIO13_14_WL_CTRL_EN_8822B BIT(22)\n#define BIT_GPIO13_14_WL_CTRL_EN_8822B BIT(22)\n#define BIT_LED2DIS_8822B BIT(21)\n#define BIT_LED2PL_8822B BIT(20)\n#define BIT_LED2SV_8822B BIT(19)\n\n#define BIT_SHIFT_LED2CM_8822B 16\n#define BIT_MASK_LED2CM_8822B 0x7\n#define BIT_LED2CM_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_LED2CM_8822B) << BIT_SHIFT_LED2CM_8822B)\n#define BITS_LED2CM_8822B (BIT_MASK_LED2CM_8822B << BIT_SHIFT_LED2CM_8822B)\n#define BIT_CLEAR_LED2CM_8822B(x) ((x) & (~BITS_LED2CM_8822B))\n#define BIT_GET_LED2CM_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_LED2CM_8822B) & BIT_MASK_LED2CM_8822B)\n#define BIT_SET_LED2CM_8822B(x, v)                                             \\\n\t(BIT_CLEAR_LED2CM_8822B(x) | BIT_LED2CM_8822B(v))\n\n#define BIT_LED1DIS_8822B BIT(15)\n#define BIT_LED1PL_8822B BIT(12)\n#define BIT_LED1SV_8822B BIT(11)\n\n#define BIT_SHIFT_LED1CM_8822B 8\n#define BIT_MASK_LED1CM_8822B 0x7\n#define BIT_LED1CM_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_LED1CM_8822B) << BIT_SHIFT_LED1CM_8822B)\n#define BITS_LED1CM_8822B (BIT_MASK_LED1CM_8822B << BIT_SHIFT_LED1CM_8822B)\n#define BIT_CLEAR_LED1CM_8822B(x) ((x) & (~BITS_LED1CM_8822B))\n#define BIT_GET_LED1CM_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_LED1CM_8822B) & BIT_MASK_LED1CM_8822B)\n#define BIT_SET_LED1CM_8822B(x, v)                                             \\\n\t(BIT_CLEAR_LED1CM_8822B(x) | BIT_LED1CM_8822B(v))\n\n#define BIT_LED0DIS_8822B BIT(7)\n\n#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B 5\n#define BIT_MASK_AFE_LDO_SWR_CHECK_8822B 0x3\n#define BIT_AFE_LDO_SWR_CHECK_8822B(x)                                         \\\n\t(((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8822B)                              \\\n\t << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B)\n#define BITS_AFE_LDO_SWR_CHECK_8822B                                           \\\n\t(BIT_MASK_AFE_LDO_SWR_CHECK_8822B << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B)\n#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8822B(x)                                   \\\n\t((x) & (~BITS_AFE_LDO_SWR_CHECK_8822B))\n#define BIT_GET_AFE_LDO_SWR_CHECK_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B) &                          \\\n\t BIT_MASK_AFE_LDO_SWR_CHECK_8822B)\n#define BIT_SET_AFE_LDO_SWR_CHECK_8822B(x, v)                                  \\\n\t(BIT_CLEAR_AFE_LDO_SWR_CHECK_8822B(x) | BIT_AFE_LDO_SWR_CHECK_8822B(v))\n\n#define BIT_LED0PL_8822B BIT(4)\n#define BIT_LED0SV_8822B BIT(3)\n\n#define BIT_SHIFT_LED0CM_8822B 0\n#define BIT_MASK_LED0CM_8822B 0x7\n#define BIT_LED0CM_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_LED0CM_8822B) << BIT_SHIFT_LED0CM_8822B)\n#define BITS_LED0CM_8822B (BIT_MASK_LED0CM_8822B << BIT_SHIFT_LED0CM_8822B)\n#define BIT_CLEAR_LED0CM_8822B(x) ((x) & (~BITS_LED0CM_8822B))\n#define BIT_GET_LED0CM_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_LED0CM_8822B) & BIT_MASK_LED0CM_8822B)\n#define BIT_SET_LED0CM_8822B(x, v)                                             \\\n\t(BIT_CLEAR_LED0CM_8822B(x) | BIT_LED0CM_8822B(v))\n\n/* 2 REG_FSIMR_8822B */\n#define BIT_FS_PDNINT_EN_8822B BIT(31)\n#define BIT_NFC_INT_PAD_EN_8822B BIT(30)\n#define BIT_FS_SPS_OCP_INT_EN_8822B BIT(29)\n#define BIT_FS_PWMERR_INT_EN_8822B BIT(28)\n#define BIT_FS_GPIOF_INT_EN_8822B BIT(27)\n#define BIT_FS_GPIOE_INT_EN_8822B BIT(26)\n#define BIT_FS_GPIOD_INT_EN_8822B BIT(25)\n#define BIT_FS_GPIOC_INT_EN_8822B BIT(24)\n#define BIT_FS_GPIOB_INT_EN_8822B BIT(23)\n#define BIT_FS_GPIOA_INT_EN_8822B BIT(22)\n#define BIT_FS_GPIO9_INT_EN_8822B BIT(21)\n#define BIT_FS_GPIO8_INT_EN_8822B BIT(20)\n#define BIT_FS_GPIO7_INT_EN_8822B BIT(19)\n#define BIT_FS_GPIO6_INT_EN_8822B BIT(18)\n#define BIT_FS_GPIO5_INT_EN_8822B BIT(17)\n#define BIT_FS_GPIO4_INT_EN_8822B BIT(16)\n#define BIT_FS_GPIO3_INT_EN_8822B BIT(15)\n#define BIT_FS_GPIO2_INT_EN_8822B BIT(14)\n#define BIT_FS_GPIO1_INT_EN_8822B BIT(13)\n#define BIT_FS_GPIO0_INT_EN_8822B BIT(12)\n#define BIT_FS_HCI_SUS_EN_8822B BIT(11)\n#define BIT_FS_HCI_RES_EN_8822B BIT(10)\n#define BIT_FS_HCI_RESET_EN_8822B BIT(9)\n#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8822B BIT(7)\n#define BIT_ACT2RECOVERY_INT_EN_V1_8822B BIT(6)\n#define BIT_GEN1GEN2_SWITCH_8822B BIT(5)\n#define BIT_HCI_TXDMA_REQ_HIMR_8822B BIT(4)\n#define BIT_FS_32K_LEAVE_SETTING_MAK_8822B BIT(3)\n#define BIT_FS_32K_ENTER_SETTING_MAK_8822B BIT(2)\n#define BIT_FS_USB_LPMRSM_MSK_8822B BIT(1)\n#define BIT_FS_USB_LPMINT_MSK_8822B BIT(0)\n\n/* 2 REG_FSISR_8822B */\n#define BIT_FS_PDNINT_8822B BIT(31)\n#define BIT_FS_SPS_OCP_INT_8822B BIT(29)\n#define BIT_FS_PWMERR_INT_8822B BIT(28)\n#define BIT_FS_GPIOF_INT_8822B BIT(27)\n#define BIT_FS_GPIOE_INT_8822B BIT(26)\n#define BIT_FS_GPIOD_INT_8822B BIT(25)\n#define BIT_FS_GPIOC_INT_8822B BIT(24)\n#define BIT_FS_GPIOB_INT_8822B BIT(23)\n#define BIT_FS_GPIOA_INT_8822B BIT(22)\n#define BIT_FS_GPIO9_INT_8822B BIT(21)\n#define BIT_FS_GPIO8_INT_8822B BIT(20)\n#define BIT_FS_GPIO7_INT_8822B BIT(19)\n#define BIT_FS_GPIO6_INT_8822B BIT(18)\n#define BIT_FS_GPIO5_INT_8822B BIT(17)\n#define BIT_FS_GPIO4_INT_8822B BIT(16)\n#define BIT_FS_GPIO3_INT_8822B BIT(15)\n#define BIT_FS_GPIO2_INT_8822B BIT(14)\n#define BIT_FS_GPIO1_INT_8822B BIT(13)\n#define BIT_FS_GPIO0_INT_8822B BIT(12)\n#define BIT_FS_HCI_SUS_INT_8822B BIT(11)\n#define BIT_FS_HCI_RES_INT_8822B BIT(10)\n#define BIT_FS_HCI_RESET_INT_8822B BIT(9)\n#define BIT_ACT2RECOVERY_8822B BIT(6)\n#define BIT_GEN1GEN2_SWITCH_8822B BIT(5)\n#define BIT_HCI_TXDMA_REQ_HISR_8822B BIT(4)\n#define BIT_FS_32K_LEAVE_SETTING_INT_8822B BIT(3)\n#define BIT_FS_32K_ENTER_SETTING_INT_8822B BIT(2)\n#define BIT_FS_USB_LPMRSM_INT_8822B BIT(1)\n#define BIT_FS_USB_LPMINT_INT_8822B BIT(0)\n\n/* 2 REG_HSIMR_8822B */\n#define BIT_GPIOF_INT_EN_8822B BIT(31)\n#define BIT_GPIOE_INT_EN_8822B BIT(30)\n#define BIT_GPIOD_INT_EN_8822B BIT(29)\n#define BIT_GPIOC_INT_EN_8822B BIT(28)\n#define BIT_GPIOB_INT_EN_8822B BIT(27)\n#define BIT_GPIOA_INT_EN_8822B BIT(26)\n#define BIT_GPIO9_INT_EN_8822B BIT(25)\n#define BIT_GPIO8_INT_EN_8822B BIT(24)\n#define BIT_GPIO7_INT_EN_8822B BIT(23)\n#define BIT_GPIO6_INT_EN_8822B BIT(22)\n#define BIT_GPIO5_INT_EN_8822B BIT(21)\n#define BIT_GPIO4_INT_EN_8822B BIT(20)\n#define BIT_GPIO3_INT_EN_8822B BIT(19)\n#define BIT_GPIO2_INT_EN_V1_8822B BIT(18)\n#define BIT_GPIO1_INT_EN_8822B BIT(17)\n#define BIT_GPIO0_INT_EN_8822B BIT(16)\n#define BIT_PDNINT_EN_8822B BIT(7)\n#define BIT_RON_INT_EN_8822B BIT(6)\n#define BIT_SPS_OCP_INT_EN_8822B BIT(5)\n#define BIT_GPIO15_0_INT_EN_8822B BIT(0)\n\n/* 2 REG_HSISR_8822B */\n#define BIT_GPIOF_INT_8822B BIT(31)\n#define BIT_GPIOE_INT_8822B BIT(30)\n#define BIT_GPIOD_INT_8822B BIT(29)\n#define BIT_GPIOC_INT_8822B BIT(28)\n#define BIT_GPIOB_INT_8822B BIT(27)\n#define BIT_GPIOA_INT_8822B BIT(26)\n#define BIT_GPIO9_INT_8822B BIT(25)\n#define BIT_GPIO8_INT_8822B BIT(24)\n#define BIT_GPIO7_INT_8822B BIT(23)\n#define BIT_GPIO6_INT_8822B BIT(22)\n#define BIT_GPIO5_INT_8822B BIT(21)\n#define BIT_GPIO4_INT_8822B BIT(20)\n#define BIT_GPIO3_INT_8822B BIT(19)\n#define BIT_GPIO2_INT_V1_8822B BIT(18)\n#define BIT_GPIO1_INT_8822B BIT(17)\n#define BIT_GPIO0_INT_8822B BIT(16)\n#define BIT_PDNINT_8822B BIT(7)\n#define BIT_RON_INT_8822B BIT(6)\n#define BIT_SPS_OCP_INT_8822B BIT(5)\n#define BIT_GPIO15_0_INT_8822B BIT(0)\n\n/* 2 REG_GPIO_EXT_CTRL_8822B */\n\n#define BIT_SHIFT_GPIO_MOD_15_TO_8_8822B 24\n#define BIT_MASK_GPIO_MOD_15_TO_8_8822B 0xff\n#define BIT_GPIO_MOD_15_TO_8_8822B(x)                                          \\\n\t(((x) & BIT_MASK_GPIO_MOD_15_TO_8_8822B)                               \\\n\t << BIT_SHIFT_GPIO_MOD_15_TO_8_8822B)\n#define BITS_GPIO_MOD_15_TO_8_8822B                                            \\\n\t(BIT_MASK_GPIO_MOD_15_TO_8_8822B << BIT_SHIFT_GPIO_MOD_15_TO_8_8822B)\n#define BIT_CLEAR_GPIO_MOD_15_TO_8_8822B(x)                                    \\\n\t((x) & (~BITS_GPIO_MOD_15_TO_8_8822B))\n#define BIT_GET_GPIO_MOD_15_TO_8_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8822B) &                           \\\n\t BIT_MASK_GPIO_MOD_15_TO_8_8822B)\n#define BIT_SET_GPIO_MOD_15_TO_8_8822B(x, v)                                   \\\n\t(BIT_CLEAR_GPIO_MOD_15_TO_8_8822B(x) | BIT_GPIO_MOD_15_TO_8_8822B(v))\n\n#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B 16\n#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B 0xff\n#define BIT_GPIO_IO_SEL_15_TO_8_8822B(x)                                       \\\n\t(((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B)                            \\\n\t << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B)\n#define BITS_GPIO_IO_SEL_15_TO_8_8822B                                         \\\n\t(BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B                                    \\\n\t << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B)\n#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822B(x)                                 \\\n\t((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8822B))\n#define BIT_GET_GPIO_IO_SEL_15_TO_8_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B) &                        \\\n\t BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B)\n#define BIT_SET_GPIO_IO_SEL_15_TO_8_8822B(x, v)                                \\\n\t(BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822B(x) |                              \\\n\t BIT_GPIO_IO_SEL_15_TO_8_8822B(v))\n\n#define BIT_SHIFT_GPIO_OUT_15_TO_8_8822B 8\n#define BIT_MASK_GPIO_OUT_15_TO_8_8822B 0xff\n#define BIT_GPIO_OUT_15_TO_8_8822B(x)                                          \\\n\t(((x) & BIT_MASK_GPIO_OUT_15_TO_8_8822B)                               \\\n\t << BIT_SHIFT_GPIO_OUT_15_TO_8_8822B)\n#define BITS_GPIO_OUT_15_TO_8_8822B                                            \\\n\t(BIT_MASK_GPIO_OUT_15_TO_8_8822B << BIT_SHIFT_GPIO_OUT_15_TO_8_8822B)\n#define BIT_CLEAR_GPIO_OUT_15_TO_8_8822B(x)                                    \\\n\t((x) & (~BITS_GPIO_OUT_15_TO_8_8822B))\n#define BIT_GET_GPIO_OUT_15_TO_8_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8822B) &                           \\\n\t BIT_MASK_GPIO_OUT_15_TO_8_8822B)\n#define BIT_SET_GPIO_OUT_15_TO_8_8822B(x, v)                                   \\\n\t(BIT_CLEAR_GPIO_OUT_15_TO_8_8822B(x) | BIT_GPIO_OUT_15_TO_8_8822B(v))\n\n#define BIT_SHIFT_GPIO_IN_15_TO_8_8822B 0\n#define BIT_MASK_GPIO_IN_15_TO_8_8822B 0xff\n#define BIT_GPIO_IN_15_TO_8_8822B(x)                                           \\\n\t(((x) & BIT_MASK_GPIO_IN_15_TO_8_8822B)                                \\\n\t << BIT_SHIFT_GPIO_IN_15_TO_8_8822B)\n#define BITS_GPIO_IN_15_TO_8_8822B                                             \\\n\t(BIT_MASK_GPIO_IN_15_TO_8_8822B << BIT_SHIFT_GPIO_IN_15_TO_8_8822B)\n#define BIT_CLEAR_GPIO_IN_15_TO_8_8822B(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8822B))\n#define BIT_GET_GPIO_IN_15_TO_8_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8822B) &                            \\\n\t BIT_MASK_GPIO_IN_15_TO_8_8822B)\n#define BIT_SET_GPIO_IN_15_TO_8_8822B(x, v)                                    \\\n\t(BIT_CLEAR_GPIO_IN_15_TO_8_8822B(x) | BIT_GPIO_IN_15_TO_8_8822B(v))\n\n/* 2 REG_PAD_CTRL1_8822B */\n#define BIT_PAPE_WLBT_SEL_8822B BIT(29)\n#define BIT_LNAON_WLBT_SEL_8822B BIT(28)\n#define BIT_BTGP_GPG3_FEN_8822B BIT(26)\n#define BIT_BTGP_GPG2_FEN_8822B BIT(25)\n#define BIT_BTGP_JTAG_EN_8822B BIT(24)\n#define BIT_XTAL_CLK_EXTARNAL_EN_8822B BIT(23)\n#define BIT_BTGP_UART0_EN_8822B BIT(22)\n#define BIT_BTGP_UART1_EN_8822B BIT(21)\n#define BIT_BTGP_SPI_EN_8822B BIT(20)\n#define BIT_BTGP_GPIO_E2_8822B BIT(19)\n#define BIT_BTGP_GPIO_EN_8822B BIT(18)\n\n#define BIT_SHIFT_BTGP_GPIO_SL_8822B 16\n#define BIT_MASK_BTGP_GPIO_SL_8822B 0x3\n#define BIT_BTGP_GPIO_SL_8822B(x)                                              \\\n\t(((x) & BIT_MASK_BTGP_GPIO_SL_8822B) << BIT_SHIFT_BTGP_GPIO_SL_8822B)\n#define BITS_BTGP_GPIO_SL_8822B                                                \\\n\t(BIT_MASK_BTGP_GPIO_SL_8822B << BIT_SHIFT_BTGP_GPIO_SL_8822B)\n#define BIT_CLEAR_BTGP_GPIO_SL_8822B(x) ((x) & (~BITS_BTGP_GPIO_SL_8822B))\n#define BIT_GET_BTGP_GPIO_SL_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BTGP_GPIO_SL_8822B) & BIT_MASK_BTGP_GPIO_SL_8822B)\n#define BIT_SET_BTGP_GPIO_SL_8822B(x, v)                                       \\\n\t(BIT_CLEAR_BTGP_GPIO_SL_8822B(x) | BIT_BTGP_GPIO_SL_8822B(v))\n\n#define BIT_PAD_SDIO_SR_8822B BIT(14)\n#define BIT_GPIO14_OUTPUT_PL_8822B BIT(13)\n#define BIT_HOST_WAKE_PAD_PULL_EN_8822B BIT(12)\n#define BIT_HOST_WAKE_PAD_SL_8822B BIT(11)\n#define BIT_PAD_LNAON_SR_8822B BIT(10)\n#define BIT_PAD_LNAON_E2_8822B BIT(9)\n#define BIT_SW_LNAON_G_SEL_DATA_8822B BIT(8)\n#define BIT_SW_LNAON_A_SEL_DATA_8822B BIT(7)\n#define BIT_PAD_PAPE_SR_8822B BIT(6)\n#define BIT_PAD_PAPE_E2_8822B BIT(5)\n#define BIT_SW_PAPE_G_SEL_DATA_8822B BIT(4)\n#define BIT_SW_PAPE_A_SEL_DATA_8822B BIT(3)\n#define BIT_PAD_DPDT_SR_8822B BIT(2)\n#define BIT_PAD_DPDT_PAD_E2_8822B BIT(1)\n#define BIT_SW_DPDT_SEL_DATA_8822B BIT(0)\n\n/* 2 REG_WL_BT_PWR_CTRL_8822B */\n#define BIT_ISO_BD2PP_8822B BIT(31)\n#define BIT_LDOV12B_EN_8822B BIT(30)\n#define BIT_CKEN_BTGPS_8822B BIT(29)\n#define BIT_FEN_BTGPS_8822B BIT(28)\n#define BIT_BTCPU_BOOTSEL_8822B BIT(27)\n#define BIT_SPI_SPEEDUP_8822B BIT(26)\n#define BIT_DEVWAKE_PAD_TYPE_SEL_8822B BIT(24)\n#define BIT_CLKREQ_PAD_TYPE_SEL_8822B BIT(23)\n#define BIT_ISO_BTPON2PP_8822B BIT(22)\n#define BIT_BT_HWROF_EN_8822B BIT(19)\n#define BIT_BT_FUNC_EN_8822B BIT(18)\n#define BIT_BT_HWPDN_SL_8822B BIT(17)\n#define BIT_BT_DISN_EN_8822B BIT(16)\n#define BIT_BT_PDN_PULL_EN_8822B BIT(15)\n#define BIT_WL_PDN_PULL_EN_8822B BIT(14)\n#define BIT_EXTERNAL_REQUEST_PL_8822B BIT(13)\n#define BIT_GPIO0_2_3_PULL_LOW_EN_8822B BIT(12)\n#define BIT_ISO_BA2PP_8822B BIT(11)\n#define BIT_BT_AFE_LDO_EN_8822B BIT(10)\n#define BIT_BT_AFE_PLL_EN_8822B BIT(9)\n#define BIT_BT_DIG_CLK_EN_8822B BIT(8)\n#define BIT_WL_DRV_EXIST_IDX_8822B BIT(5)\n#define BIT_DOP_EHPAD_8822B BIT(4)\n#define BIT_WL_HWROF_EN_8822B BIT(3)\n#define BIT_WL_FUNC_EN_8822B BIT(2)\n#define BIT_WL_HWPDN_SL_8822B BIT(1)\n#define BIT_WL_HWPDN_EN_8822B BIT(0)\n\n/* 2 REG_SDM_DEBUG_8822B */\n\n#define BIT_SHIFT_WLCLK_PHASE_8822B 0\n#define BIT_MASK_WLCLK_PHASE_8822B 0x1f\n#define BIT_WLCLK_PHASE_8822B(x)                                               \\\n\t(((x) & BIT_MASK_WLCLK_PHASE_8822B) << BIT_SHIFT_WLCLK_PHASE_8822B)\n#define BITS_WLCLK_PHASE_8822B                                                 \\\n\t(BIT_MASK_WLCLK_PHASE_8822B << BIT_SHIFT_WLCLK_PHASE_8822B)\n#define BIT_CLEAR_WLCLK_PHASE_8822B(x) ((x) & (~BITS_WLCLK_PHASE_8822B))\n#define BIT_GET_WLCLK_PHASE_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_WLCLK_PHASE_8822B) & BIT_MASK_WLCLK_PHASE_8822B)\n#define BIT_SET_WLCLK_PHASE_8822B(x, v)                                        \\\n\t(BIT_CLEAR_WLCLK_PHASE_8822B(x) | BIT_WLCLK_PHASE_8822B(v))\n\n/* 2 REG_SYS_SDIO_CTRL_8822B */\n#define BIT_DBG_GNT_WL_BT_8822B BIT(27)\n#define BIT_LTE_MUX_CTRL_PATH_8822B BIT(26)\n#define BIT_LTE_COEX_UART_8822B BIT(25)\n#define BIT_3W_LTE_WL_GPIO_8822B BIT(24)\n#define BIT_SDIO_INT_POLARITY_8822B BIT(19)\n#define BIT_SDIO_INT_8822B BIT(18)\n#define BIT_SDIO_OFF_EN_8822B BIT(17)\n#define BIT_SDIO_ON_EN_8822B BIT(16)\n#define BIT_PCIE_WAIT_TIMEOUT_EVENT_8822B BIT(10)\n#define BIT_PCIE_WAIT_TIME_8822B BIT(9)\n#define BIT_MPCIE_REFCLK_XTAL_SEL_8822B BIT(8)\n\n#define BIT_SHIFT_SI_AUTHORIZATION_8822B 0\n#define BIT_MASK_SI_AUTHORIZATION_8822B 0xff\n#define BIT_SI_AUTHORIZATION_8822B(x)                                          \\\n\t(((x) & BIT_MASK_SI_AUTHORIZATION_8822B)                               \\\n\t << BIT_SHIFT_SI_AUTHORIZATION_8822B)\n#define BITS_SI_AUTHORIZATION_8822B                                            \\\n\t(BIT_MASK_SI_AUTHORIZATION_8822B << BIT_SHIFT_SI_AUTHORIZATION_8822B)\n#define BIT_CLEAR_SI_AUTHORIZATION_8822B(x)                                    \\\n\t((x) & (~BITS_SI_AUTHORIZATION_8822B))\n#define BIT_GET_SI_AUTHORIZATION_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_SI_AUTHORIZATION_8822B) &                           \\\n\t BIT_MASK_SI_AUTHORIZATION_8822B)\n#define BIT_SET_SI_AUTHORIZATION_8822B(x, v)                                   \\\n\t(BIT_CLEAR_SI_AUTHORIZATION_8822B(x) | BIT_SI_AUTHORIZATION_8822B(v))\n\n/* 2 REG_HCI_OPT_CTRL_8822B */\n\n#define BIT_SHIFT_TSFT_SEL_8822B 29\n#define BIT_MASK_TSFT_SEL_8822B 0x7\n#define BIT_TSFT_SEL_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_TSFT_SEL_8822B) << BIT_SHIFT_TSFT_SEL_8822B)\n#define BITS_TSFT_SEL_8822B                                                    \\\n\t(BIT_MASK_TSFT_SEL_8822B << BIT_SHIFT_TSFT_SEL_8822B)\n#define BIT_CLEAR_TSFT_SEL_8822B(x) ((x) & (~BITS_TSFT_SEL_8822B))\n#define BIT_GET_TSFT_SEL_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TSFT_SEL_8822B) & BIT_MASK_TSFT_SEL_8822B)\n#define BIT_SET_TSFT_SEL_8822B(x, v)                                           \\\n\t(BIT_CLEAR_TSFT_SEL_8822B(x) | BIT_TSFT_SEL_8822B(v))\n\n#define BIT_USB_HOST_PWR_OFF_EN_8822B BIT(12)\n#define BIT_SYM_LPS_BLOCK_EN_8822B BIT(11)\n#define BIT_USB_LPM_ACT_EN_8822B BIT(10)\n#define BIT_USB_LPM_NY_8822B BIT(9)\n#define BIT_USB_SUS_DIS_8822B BIT(8)\n\n#define BIT_SHIFT_SDIO_PAD_E_8822B 5\n#define BIT_MASK_SDIO_PAD_E_8822B 0x7\n#define BIT_SDIO_PAD_E_8822B(x)                                                \\\n\t(((x) & BIT_MASK_SDIO_PAD_E_8822B) << BIT_SHIFT_SDIO_PAD_E_8822B)\n#define BITS_SDIO_PAD_E_8822B                                                  \\\n\t(BIT_MASK_SDIO_PAD_E_8822B << BIT_SHIFT_SDIO_PAD_E_8822B)\n#define BIT_CLEAR_SDIO_PAD_E_8822B(x) ((x) & (~BITS_SDIO_PAD_E_8822B))\n#define BIT_GET_SDIO_PAD_E_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_SDIO_PAD_E_8822B) & BIT_MASK_SDIO_PAD_E_8822B)\n#define BIT_SET_SDIO_PAD_E_8822B(x, v)                                         \\\n\t(BIT_CLEAR_SDIO_PAD_E_8822B(x) | BIT_SDIO_PAD_E_8822B(v))\n\n#define BIT_USB_LPPLL_EN_8822B BIT(4)\n#define BIT_ROP_SW15_8822B BIT(2)\n#define BIT_PCI_CKRDY_OPT_8822B BIT(1)\n#define BIT_PCI_VAUX_EN_8822B BIT(0)\n\n/* 2 REG_AFE_CTRL4_8822B */\n\n/* 2 REG_LDO_SWR_CTRL_8822B */\n#define BIT_ZCD_HW_AUTO_EN_8822B BIT(27)\n#define BIT_ZCD_REGSEL_8822B BIT(26)\n\n#define BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B 21\n#define BIT_MASK_AUTO_ZCD_IN_CODE_8822B 0x1f\n#define BIT_AUTO_ZCD_IN_CODE_8822B(x)                                          \\\n\t(((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8822B)                               \\\n\t << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B)\n#define BITS_AUTO_ZCD_IN_CODE_8822B                                            \\\n\t(BIT_MASK_AUTO_ZCD_IN_CODE_8822B << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B)\n#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8822B(x)                                    \\\n\t((x) & (~BITS_AUTO_ZCD_IN_CODE_8822B))\n#define BIT_GET_AUTO_ZCD_IN_CODE_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B) &                           \\\n\t BIT_MASK_AUTO_ZCD_IN_CODE_8822B)\n#define BIT_SET_AUTO_ZCD_IN_CODE_8822B(x, v)                                   \\\n\t(BIT_CLEAR_AUTO_ZCD_IN_CODE_8822B(x) | BIT_AUTO_ZCD_IN_CODE_8822B(v))\n\n#define BIT_SHIFT_ZCD_CODE_IN_L_8822B 16\n#define BIT_MASK_ZCD_CODE_IN_L_8822B 0x1f\n#define BIT_ZCD_CODE_IN_L_8822B(x)                                             \\\n\t(((x) & BIT_MASK_ZCD_CODE_IN_L_8822B) << BIT_SHIFT_ZCD_CODE_IN_L_8822B)\n#define BITS_ZCD_CODE_IN_L_8822B                                               \\\n\t(BIT_MASK_ZCD_CODE_IN_L_8822B << BIT_SHIFT_ZCD_CODE_IN_L_8822B)\n#define BIT_CLEAR_ZCD_CODE_IN_L_8822B(x) ((x) & (~BITS_ZCD_CODE_IN_L_8822B))\n#define BIT_GET_ZCD_CODE_IN_L_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8822B) & BIT_MASK_ZCD_CODE_IN_L_8822B)\n#define BIT_SET_ZCD_CODE_IN_L_8822B(x, v)                                      \\\n\t(BIT_CLEAR_ZCD_CODE_IN_L_8822B(x) | BIT_ZCD_CODE_IN_L_8822B(v))\n\n#define BIT_SHIFT_LDO_HV5_DUMMY_8822B 14\n#define BIT_MASK_LDO_HV5_DUMMY_8822B 0x3\n#define BIT_LDO_HV5_DUMMY_8822B(x)                                             \\\n\t(((x) & BIT_MASK_LDO_HV5_DUMMY_8822B) << BIT_SHIFT_LDO_HV5_DUMMY_8822B)\n#define BITS_LDO_HV5_DUMMY_8822B                                               \\\n\t(BIT_MASK_LDO_HV5_DUMMY_8822B << BIT_SHIFT_LDO_HV5_DUMMY_8822B)\n#define BIT_CLEAR_LDO_HV5_DUMMY_8822B(x) ((x) & (~BITS_LDO_HV5_DUMMY_8822B))\n#define BIT_GET_LDO_HV5_DUMMY_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8822B) & BIT_MASK_LDO_HV5_DUMMY_8822B)\n#define BIT_SET_LDO_HV5_DUMMY_8822B(x, v)                                      \\\n\t(BIT_CLEAR_LDO_HV5_DUMMY_8822B(x) | BIT_LDO_HV5_DUMMY_8822B(v))\n\n#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B 12\n#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B 0x3\n#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8822B(x)                                  \\\n\t(((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B)                       \\\n\t << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B)\n#define BITS_REG_VTUNE33_BIT0_TO_BIT1_8822B                                    \\\n\t(BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B                               \\\n\t << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B)\n#define BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8822B(x)                            \\\n\t((x) & (~BITS_REG_VTUNE33_BIT0_TO_BIT1_8822B))\n#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8822B(x)                              \\\n\t(((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B) &                   \\\n\t BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B)\n#define BIT_SET_REG_VTUNE33_BIT0_TO_BIT1_8822B(x, v)                           \\\n\t(BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) |                         \\\n\t BIT_REG_VTUNE33_BIT0_TO_BIT1_8822B(v))\n\n#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B 10\n#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B 0x3\n#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8822B(x)                                \\\n\t(((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B)                     \\\n\t << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B)\n#define BITS_REG_STANDBY33_BIT0_TO_BIT1_8822B                                  \\\n\t(BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B                             \\\n\t << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B)\n#define BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8822B(x)                          \\\n\t((x) & (~BITS_REG_STANDBY33_BIT0_TO_BIT1_8822B))\n#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8822B(x)                            \\\n\t(((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B) &                 \\\n\t BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B)\n#define BIT_SET_REG_STANDBY33_BIT0_TO_BIT1_8822B(x, v)                         \\\n\t(BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) |                       \\\n\t BIT_REG_STANDBY33_BIT0_TO_BIT1_8822B(v))\n\n#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B 8\n#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B 0x3\n#define BIT_REG_LOAD33_BIT0_TO_BIT1_8822B(x)                                   \\\n\t(((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B)                        \\\n\t << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B)\n#define BITS_REG_LOAD33_BIT0_TO_BIT1_8822B                                     \\\n\t(BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B                                \\\n\t << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B)\n#define BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8822B(x)                             \\\n\t((x) & (~BITS_REG_LOAD33_BIT0_TO_BIT1_8822B))\n#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8822B(x)                               \\\n\t(((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B) &                    \\\n\t BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B)\n#define BIT_SET_REG_LOAD33_BIT0_TO_BIT1_8822B(x, v)                            \\\n\t(BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8822B(x) |                          \\\n\t BIT_REG_LOAD33_BIT0_TO_BIT1_8822B(v))\n\n#define BIT_REG_BYPASS_L_8822B BIT(7)\n#define BIT_REG_LDOF_L_8822B BIT(6)\n#define BIT_REG_TYPE_L_V1_8822B BIT(5)\n#define BIT_ARENB_L_8822B BIT(3)\n\n#define BIT_SHIFT_CFC_L_8822B 1\n#define BIT_MASK_CFC_L_8822B 0x3\n#define BIT_CFC_L_8822B(x)                                                     \\\n\t(((x) & BIT_MASK_CFC_L_8822B) << BIT_SHIFT_CFC_L_8822B)\n#define BITS_CFC_L_8822B (BIT_MASK_CFC_L_8822B << BIT_SHIFT_CFC_L_8822B)\n#define BIT_CLEAR_CFC_L_8822B(x) ((x) & (~BITS_CFC_L_8822B))\n#define BIT_GET_CFC_L_8822B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CFC_L_8822B) & BIT_MASK_CFC_L_8822B)\n#define BIT_SET_CFC_L_8822B(x, v)                                              \\\n\t(BIT_CLEAR_CFC_L_8822B(x) | BIT_CFC_L_8822B(v))\n\n#define BIT_REG_OCPS_L_V1_8822B BIT(0)\n\n/* 2 REG_MCUFW_CTRL_8822B */\n\n#define BIT_SHIFT_RPWM_8822B 24\n#define BIT_MASK_RPWM_8822B 0xff\n#define BIT_RPWM_8822B(x) (((x) & BIT_MASK_RPWM_8822B) << BIT_SHIFT_RPWM_8822B)\n#define BITS_RPWM_8822B (BIT_MASK_RPWM_8822B << BIT_SHIFT_RPWM_8822B)\n#define BIT_CLEAR_RPWM_8822B(x) ((x) & (~BITS_RPWM_8822B))\n#define BIT_GET_RPWM_8822B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_RPWM_8822B) & BIT_MASK_RPWM_8822B)\n#define BIT_SET_RPWM_8822B(x, v) (BIT_CLEAR_RPWM_8822B(x) | BIT_RPWM_8822B(v))\n\n#define BIT_ANA_PORT_EN_8822B BIT(22)\n#define BIT_MAC_PORT_EN_8822B BIT(21)\n#define BIT_BOOT_FSPI_EN_8822B BIT(20)\n#define BIT_ROM_DLEN_8822B BIT(19)\n\n#define BIT_SHIFT_ROM_PGE_8822B 16\n#define BIT_MASK_ROM_PGE_8822B 0x7\n#define BIT_ROM_PGE_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_ROM_PGE_8822B) << BIT_SHIFT_ROM_PGE_8822B)\n#define BITS_ROM_PGE_8822B (BIT_MASK_ROM_PGE_8822B << BIT_SHIFT_ROM_PGE_8822B)\n#define BIT_CLEAR_ROM_PGE_8822B(x) ((x) & (~BITS_ROM_PGE_8822B))\n#define BIT_GET_ROM_PGE_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_ROM_PGE_8822B) & BIT_MASK_ROM_PGE_8822B)\n#define BIT_SET_ROM_PGE_8822B(x, v)                                            \\\n\t(BIT_CLEAR_ROM_PGE_8822B(x) | BIT_ROM_PGE_8822B(v))\n\n#define BIT_FW_INIT_RDY_8822B BIT(15)\n#define BIT_FW_DW_RDY_8822B BIT(14)\n\n#define BIT_SHIFT_CPU_CLK_SEL_8822B 12\n#define BIT_MASK_CPU_CLK_SEL_8822B 0x3\n#define BIT_CPU_CLK_SEL_8822B(x)                                               \\\n\t(((x) & BIT_MASK_CPU_CLK_SEL_8822B) << BIT_SHIFT_CPU_CLK_SEL_8822B)\n#define BITS_CPU_CLK_SEL_8822B                                                 \\\n\t(BIT_MASK_CPU_CLK_SEL_8822B << BIT_SHIFT_CPU_CLK_SEL_8822B)\n#define BIT_CLEAR_CPU_CLK_SEL_8822B(x) ((x) & (~BITS_CPU_CLK_SEL_8822B))\n#define BIT_GET_CPU_CLK_SEL_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_CPU_CLK_SEL_8822B) & BIT_MASK_CPU_CLK_SEL_8822B)\n#define BIT_SET_CPU_CLK_SEL_8822B(x, v)                                        \\\n\t(BIT_CLEAR_CPU_CLK_SEL_8822B(x) | BIT_CPU_CLK_SEL_8822B(v))\n\n#define BIT_CCLK_CHG_MASK_8822B BIT(11)\n#define BIT_EMEM__TXBUF_CHKSUM_OK_8822B BIT(10)\n#define BIT_EMEM_TXBUF_DW_RDY_8822B BIT(9)\n#define BIT_EMEM_CHKSUM_OK_8822B BIT(8)\n#define BIT_EMEM_DW_OK_8822B BIT(7)\n#define BIT_DMEM_CHKSUM_OK_8822B BIT(6)\n#define BIT_DMEM_DW_OK_8822B BIT(5)\n#define BIT_IMEM_CHKSUM_OK_8822B BIT(4)\n#define BIT_IMEM_DW_OK_8822B BIT(3)\n#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK_8822B BIT(2)\n#define BIT_IMEM_BOOT_LOAD_DW_OK_8822B BIT(1)\n#define BIT_MCUFWDL_EN_8822B BIT(0)\n\n/* 2 REG_MCU_TST_CFG_8822B */\n\n#define BIT_SHIFT_C2H_MSG_8822B 0\n#define BIT_MASK_C2H_MSG_8822B 0xffff\n#define BIT_C2H_MSG_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_C2H_MSG_8822B) << BIT_SHIFT_C2H_MSG_8822B)\n#define BITS_C2H_MSG_8822B (BIT_MASK_C2H_MSG_8822B << BIT_SHIFT_C2H_MSG_8822B)\n#define BIT_CLEAR_C2H_MSG_8822B(x) ((x) & (~BITS_C2H_MSG_8822B))\n#define BIT_GET_C2H_MSG_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_C2H_MSG_8822B) & BIT_MASK_C2H_MSG_8822B)\n#define BIT_SET_C2H_MSG_8822B(x, v)                                            \\\n\t(BIT_CLEAR_C2H_MSG_8822B(x) | BIT_C2H_MSG_8822B(v))\n\n/* 2 REG_HMEBOX_E0_E1_8822B */\n\n#define BIT_SHIFT_HOST_MSG_E1_8822B 16\n#define BIT_MASK_HOST_MSG_E1_8822B 0xffff\n#define BIT_HOST_MSG_E1_8822B(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E1_8822B) << BIT_SHIFT_HOST_MSG_E1_8822B)\n#define BITS_HOST_MSG_E1_8822B                                                 \\\n\t(BIT_MASK_HOST_MSG_E1_8822B << BIT_SHIFT_HOST_MSG_E1_8822B)\n#define BIT_CLEAR_HOST_MSG_E1_8822B(x) ((x) & (~BITS_HOST_MSG_E1_8822B))\n#define BIT_GET_HOST_MSG_E1_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E1_8822B) & BIT_MASK_HOST_MSG_E1_8822B)\n#define BIT_SET_HOST_MSG_E1_8822B(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E1_8822B(x) | BIT_HOST_MSG_E1_8822B(v))\n\n#define BIT_SHIFT_HOST_MSG_E0_8822B 0\n#define BIT_MASK_HOST_MSG_E0_8822B 0xffff\n#define BIT_HOST_MSG_E0_8822B(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E0_8822B) << BIT_SHIFT_HOST_MSG_E0_8822B)\n#define BITS_HOST_MSG_E0_8822B                                                 \\\n\t(BIT_MASK_HOST_MSG_E0_8822B << BIT_SHIFT_HOST_MSG_E0_8822B)\n#define BIT_CLEAR_HOST_MSG_E0_8822B(x) ((x) & (~BITS_HOST_MSG_E0_8822B))\n#define BIT_GET_HOST_MSG_E0_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E0_8822B) & BIT_MASK_HOST_MSG_E0_8822B)\n#define BIT_SET_HOST_MSG_E0_8822B(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E0_8822B(x) | BIT_HOST_MSG_E0_8822B(v))\n\n/* 2 REG_HMEBOX_E2_E3_8822B */\n\n#define BIT_SHIFT_HOST_MSG_E3_8822B 16\n#define BIT_MASK_HOST_MSG_E3_8822B 0xffff\n#define BIT_HOST_MSG_E3_8822B(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E3_8822B) << BIT_SHIFT_HOST_MSG_E3_8822B)\n#define BITS_HOST_MSG_E3_8822B                                                 \\\n\t(BIT_MASK_HOST_MSG_E3_8822B << BIT_SHIFT_HOST_MSG_E3_8822B)\n#define BIT_CLEAR_HOST_MSG_E3_8822B(x) ((x) & (~BITS_HOST_MSG_E3_8822B))\n#define BIT_GET_HOST_MSG_E3_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E3_8822B) & BIT_MASK_HOST_MSG_E3_8822B)\n#define BIT_SET_HOST_MSG_E3_8822B(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E3_8822B(x) | BIT_HOST_MSG_E3_8822B(v))\n\n#define BIT_SHIFT_HOST_MSG_E2_8822B 0\n#define BIT_MASK_HOST_MSG_E2_8822B 0xffff\n#define BIT_HOST_MSG_E2_8822B(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E2_8822B) << BIT_SHIFT_HOST_MSG_E2_8822B)\n#define BITS_HOST_MSG_E2_8822B                                                 \\\n\t(BIT_MASK_HOST_MSG_E2_8822B << BIT_SHIFT_HOST_MSG_E2_8822B)\n#define BIT_CLEAR_HOST_MSG_E2_8822B(x) ((x) & (~BITS_HOST_MSG_E2_8822B))\n#define BIT_GET_HOST_MSG_E2_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E2_8822B) & BIT_MASK_HOST_MSG_E2_8822B)\n#define BIT_SET_HOST_MSG_E2_8822B(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E2_8822B(x) | BIT_HOST_MSG_E2_8822B(v))\n\n/* 2 REG_WLLPS_CTRL_8822B */\n#define BIT_WLLPSOP_EABM_8822B BIT(31)\n#define BIT_WLLPSOP_ACKF_8822B BIT(30)\n#define BIT_WLLPSOP_DLDM_8822B BIT(29)\n#define BIT_WLLPSOP_ESWR_8822B BIT(28)\n#define BIT_WLLPSOP_PWMM_8822B BIT(27)\n#define BIT_WLLPSOP_EECK_8822B BIT(26)\n#define BIT_WLLPSOP_WLMACOFF_8822B BIT(25)\n#define BIT_WLLPSOP_EXTAL_8822B BIT(24)\n#define BIT_WL_SYNPON_VOLTSPDN_8822B BIT(23)\n#define BIT_WLLPSOP_WLBBOFF_8822B BIT(22)\n#define BIT_WLLPSOP_WLMEM_DS_8822B BIT(21)\n\n#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B 12\n#define BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B 0xf\n#define BIT_LPLDH12_VADJ_STEP_DN_8822B(x)                                      \\\n\t(((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B)                           \\\n\t << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B)\n#define BITS_LPLDH12_VADJ_STEP_DN_8822B                                        \\\n\t(BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B                                   \\\n\t << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B)\n#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822B(x)                                \\\n\t((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8822B))\n#define BIT_GET_LPLDH12_VADJ_STEP_DN_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B) &                       \\\n\t BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B)\n#define BIT_SET_LPLDH12_VADJ_STEP_DN_8822B(x, v)                               \\\n\t(BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822B(x) |                             \\\n\t BIT_LPLDH12_VADJ_STEP_DN_8822B(v))\n\n#define BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B 8\n#define BIT_MASK_V15ADJ_L1_STEP_DN_8822B 0x7\n#define BIT_V15ADJ_L1_STEP_DN_8822B(x)                                         \\\n\t(((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8822B)                              \\\n\t << BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B)\n#define BITS_V15ADJ_L1_STEP_DN_8822B                                           \\\n\t(BIT_MASK_V15ADJ_L1_STEP_DN_8822B << BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B)\n#define BIT_CLEAR_V15ADJ_L1_STEP_DN_8822B(x)                                   \\\n\t((x) & (~BITS_V15ADJ_L1_STEP_DN_8822B))\n#define BIT_GET_V15ADJ_L1_STEP_DN_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B) &                          \\\n\t BIT_MASK_V15ADJ_L1_STEP_DN_8822B)\n#define BIT_SET_V15ADJ_L1_STEP_DN_8822B(x, v)                                  \\\n\t(BIT_CLEAR_V15ADJ_L1_STEP_DN_8822B(x) | BIT_V15ADJ_L1_STEP_DN_8822B(v))\n\n#define BIT_REGU_32K_CLK_EN_8822B BIT(1)\n#define BIT_WL_LPS_EN_8822B BIT(0)\n\n/* 2 REG_AFE_CTRL5_8822B */\n#define BIT_BB_DBG_SEL_AFE_SDM_BIT0_8822B BIT(31)\n#define BIT_ORDER_SDM_8822B BIT(30)\n#define BIT_RFE_SEL_SDM_8822B BIT(29)\n\n#define BIT_SHIFT_REF_SEL_8822B 25\n#define BIT_MASK_REF_SEL_8822B 0xf\n#define BIT_REF_SEL_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_REF_SEL_8822B) << BIT_SHIFT_REF_SEL_8822B)\n#define BITS_REF_SEL_8822B (BIT_MASK_REF_SEL_8822B << BIT_SHIFT_REF_SEL_8822B)\n#define BIT_CLEAR_REF_SEL_8822B(x) ((x) & (~BITS_REF_SEL_8822B))\n#define BIT_GET_REF_SEL_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_REF_SEL_8822B) & BIT_MASK_REF_SEL_8822B)\n#define BIT_SET_REF_SEL_8822B(x, v)                                            \\\n\t(BIT_CLEAR_REF_SEL_8822B(x) | BIT_REF_SEL_8822B(v))\n\n#define BIT_SHIFT_F0F_SDM_8822B 12\n#define BIT_MASK_F0F_SDM_8822B 0x1fff\n#define BIT_F0F_SDM_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_F0F_SDM_8822B) << BIT_SHIFT_F0F_SDM_8822B)\n#define BITS_F0F_SDM_8822B (BIT_MASK_F0F_SDM_8822B << BIT_SHIFT_F0F_SDM_8822B)\n#define BIT_CLEAR_F0F_SDM_8822B(x) ((x) & (~BITS_F0F_SDM_8822B))\n#define BIT_GET_F0F_SDM_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_F0F_SDM_8822B) & BIT_MASK_F0F_SDM_8822B)\n#define BIT_SET_F0F_SDM_8822B(x, v)                                            \\\n\t(BIT_CLEAR_F0F_SDM_8822B(x) | BIT_F0F_SDM_8822B(v))\n\n#define BIT_SHIFT_F0N_SDM_8822B 9\n#define BIT_MASK_F0N_SDM_8822B 0x7\n#define BIT_F0N_SDM_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_F0N_SDM_8822B) << BIT_SHIFT_F0N_SDM_8822B)\n#define BITS_F0N_SDM_8822B (BIT_MASK_F0N_SDM_8822B << BIT_SHIFT_F0N_SDM_8822B)\n#define BIT_CLEAR_F0N_SDM_8822B(x) ((x) & (~BITS_F0N_SDM_8822B))\n#define BIT_GET_F0N_SDM_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_F0N_SDM_8822B) & BIT_MASK_F0N_SDM_8822B)\n#define BIT_SET_F0N_SDM_8822B(x, v)                                            \\\n\t(BIT_CLEAR_F0N_SDM_8822B(x) | BIT_F0N_SDM_8822B(v))\n\n#define BIT_SHIFT_DIVN_SDM_8822B 3\n#define BIT_MASK_DIVN_SDM_8822B 0x3f\n#define BIT_DIVN_SDM_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_DIVN_SDM_8822B) << BIT_SHIFT_DIVN_SDM_8822B)\n#define BITS_DIVN_SDM_8822B                                                    \\\n\t(BIT_MASK_DIVN_SDM_8822B << BIT_SHIFT_DIVN_SDM_8822B)\n#define BIT_CLEAR_DIVN_SDM_8822B(x) ((x) & (~BITS_DIVN_SDM_8822B))\n#define BIT_GET_DIVN_SDM_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_DIVN_SDM_8822B) & BIT_MASK_DIVN_SDM_8822B)\n#define BIT_SET_DIVN_SDM_8822B(x, v)                                           \\\n\t(BIT_CLEAR_DIVN_SDM_8822B(x) | BIT_DIVN_SDM_8822B(v))\n\n/* 2 REG_GPIO_DEBOUNCE_CTRL_8822B */\n#define BIT_WLGP_DBC1EN_8822B BIT(15)\n\n#define BIT_SHIFT_WLGP_DBC1_8822B 8\n#define BIT_MASK_WLGP_DBC1_8822B 0xf\n#define BIT_WLGP_DBC1_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_WLGP_DBC1_8822B) << BIT_SHIFT_WLGP_DBC1_8822B)\n#define BITS_WLGP_DBC1_8822B                                                   \\\n\t(BIT_MASK_WLGP_DBC1_8822B << BIT_SHIFT_WLGP_DBC1_8822B)\n#define BIT_CLEAR_WLGP_DBC1_8822B(x) ((x) & (~BITS_WLGP_DBC1_8822B))\n#define BIT_GET_WLGP_DBC1_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_WLGP_DBC1_8822B) & BIT_MASK_WLGP_DBC1_8822B)\n#define BIT_SET_WLGP_DBC1_8822B(x, v)                                          \\\n\t(BIT_CLEAR_WLGP_DBC1_8822B(x) | BIT_WLGP_DBC1_8822B(v))\n\n#define BIT_WLGP_DBC0EN_8822B BIT(7)\n\n#define BIT_SHIFT_WLGP_DBC0_8822B 0\n#define BIT_MASK_WLGP_DBC0_8822B 0xf\n#define BIT_WLGP_DBC0_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_WLGP_DBC0_8822B) << BIT_SHIFT_WLGP_DBC0_8822B)\n#define BITS_WLGP_DBC0_8822B                                                   \\\n\t(BIT_MASK_WLGP_DBC0_8822B << BIT_SHIFT_WLGP_DBC0_8822B)\n#define BIT_CLEAR_WLGP_DBC0_8822B(x) ((x) & (~BITS_WLGP_DBC0_8822B))\n#define BIT_GET_WLGP_DBC0_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_WLGP_DBC0_8822B) & BIT_MASK_WLGP_DBC0_8822B)\n#define BIT_SET_WLGP_DBC0_8822B(x, v)                                          \\\n\t(BIT_CLEAR_WLGP_DBC0_8822B(x) | BIT_WLGP_DBC0_8822B(v))\n\n/* 2 REG_RPWM2_8822B */\n\n#define BIT_SHIFT_RPWM2_8822B 16\n#define BIT_MASK_RPWM2_8822B 0xffff\n#define BIT_RPWM2_8822B(x)                                                     \\\n\t(((x) & BIT_MASK_RPWM2_8822B) << BIT_SHIFT_RPWM2_8822B)\n#define BITS_RPWM2_8822B (BIT_MASK_RPWM2_8822B << BIT_SHIFT_RPWM2_8822B)\n#define BIT_CLEAR_RPWM2_8822B(x) ((x) & (~BITS_RPWM2_8822B))\n#define BIT_GET_RPWM2_8822B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RPWM2_8822B) & BIT_MASK_RPWM2_8822B)\n#define BIT_SET_RPWM2_8822B(x, v)                                              \\\n\t(BIT_CLEAR_RPWM2_8822B(x) | BIT_RPWM2_8822B(v))\n\n/* 2 REG_SYSON_FSM_MON_8822B */\n\n#define BIT_SHIFT_FSM_MON_SEL_8822B 24\n#define BIT_MASK_FSM_MON_SEL_8822B 0x7\n#define BIT_FSM_MON_SEL_8822B(x)                                               \\\n\t(((x) & BIT_MASK_FSM_MON_SEL_8822B) << BIT_SHIFT_FSM_MON_SEL_8822B)\n#define BITS_FSM_MON_SEL_8822B                                                 \\\n\t(BIT_MASK_FSM_MON_SEL_8822B << BIT_SHIFT_FSM_MON_SEL_8822B)\n#define BIT_CLEAR_FSM_MON_SEL_8822B(x) ((x) & (~BITS_FSM_MON_SEL_8822B))\n#define BIT_GET_FSM_MON_SEL_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_FSM_MON_SEL_8822B) & BIT_MASK_FSM_MON_SEL_8822B)\n#define BIT_SET_FSM_MON_SEL_8822B(x, v)                                        \\\n\t(BIT_CLEAR_FSM_MON_SEL_8822B(x) | BIT_FSM_MON_SEL_8822B(v))\n\n#define BIT_DOP_ELDO_8822B BIT(23)\n#define BIT_FSM_MON_UPD_8822B BIT(15)\n\n#define BIT_SHIFT_FSM_PAR_8822B 0\n#define BIT_MASK_FSM_PAR_8822B 0x7fff\n#define BIT_FSM_PAR_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_FSM_PAR_8822B) << BIT_SHIFT_FSM_PAR_8822B)\n#define BITS_FSM_PAR_8822B (BIT_MASK_FSM_PAR_8822B << BIT_SHIFT_FSM_PAR_8822B)\n#define BIT_CLEAR_FSM_PAR_8822B(x) ((x) & (~BITS_FSM_PAR_8822B))\n#define BIT_GET_FSM_PAR_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FSM_PAR_8822B) & BIT_MASK_FSM_PAR_8822B)\n#define BIT_SET_FSM_PAR_8822B(x, v)                                            \\\n\t(BIT_CLEAR_FSM_PAR_8822B(x) | BIT_FSM_PAR_8822B(v))\n\n/* 2 REG_AFE_CTRL6_8822B */\n\n#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B 0\n#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B 0x7\n#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x)                                 \\\n\t(((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B)                      \\\n\t << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B)\n#define BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B                                   \\\n\t(BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B                              \\\n\t << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B)\n#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x)                           \\\n\t((x) & (~BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B))\n#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x)                             \\\n\t(((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) &                  \\\n\t BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B)\n#define BIT_SET_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x, v)                          \\\n\t(BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) |                        \\\n\t BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(v))\n\n/* 2 REG_PMC_DBG_CTRL1_8822B */\n#define BIT_BT_INT_EN_8822B BIT(31)\n\n#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B 16\n#define BIT_MASK_RD_WR_WIFI_BT_INFO_8822B 0x7fff\n#define BIT_RD_WR_WIFI_BT_INFO_8822B(x)                                        \\\n\t(((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822B)                             \\\n\t << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B)\n#define BITS_RD_WR_WIFI_BT_INFO_8822B                                          \\\n\t(BIT_MASK_RD_WR_WIFI_BT_INFO_8822B                                     \\\n\t << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B)\n#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822B(x)                                  \\\n\t((x) & (~BITS_RD_WR_WIFI_BT_INFO_8822B))\n#define BIT_GET_RD_WR_WIFI_BT_INFO_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B) &                         \\\n\t BIT_MASK_RD_WR_WIFI_BT_INFO_8822B)\n#define BIT_SET_RD_WR_WIFI_BT_INFO_8822B(x, v)                                 \\\n\t(BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822B(x) |                               \\\n\t BIT_RD_WR_WIFI_BT_INFO_8822B(v))\n\n#define BIT_PMC_WR_OVF_8822B BIT(8)\n\n#define BIT_SHIFT_WLPMC_ERRINT_8822B 0\n#define BIT_MASK_WLPMC_ERRINT_8822B 0xff\n#define BIT_WLPMC_ERRINT_8822B(x)                                              \\\n\t(((x) & BIT_MASK_WLPMC_ERRINT_8822B) << BIT_SHIFT_WLPMC_ERRINT_8822B)\n#define BITS_WLPMC_ERRINT_8822B                                                \\\n\t(BIT_MASK_WLPMC_ERRINT_8822B << BIT_SHIFT_WLPMC_ERRINT_8822B)\n#define BIT_CLEAR_WLPMC_ERRINT_8822B(x) ((x) & (~BITS_WLPMC_ERRINT_8822B))\n#define BIT_GET_WLPMC_ERRINT_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_WLPMC_ERRINT_8822B) & BIT_MASK_WLPMC_ERRINT_8822B)\n#define BIT_SET_WLPMC_ERRINT_8822B(x, v)                                       \\\n\t(BIT_CLEAR_WLPMC_ERRINT_8822B(x) | BIT_WLPMC_ERRINT_8822B(v))\n\n/* 2 REG_AFE_CTRL7_8822B */\n\n#define BIT_SHIFT_SEL_V_8822B 30\n#define BIT_MASK_SEL_V_8822B 0x3\n#define BIT_SEL_V_8822B(x)                                                     \\\n\t(((x) & BIT_MASK_SEL_V_8822B) << BIT_SHIFT_SEL_V_8822B)\n#define BITS_SEL_V_8822B (BIT_MASK_SEL_V_8822B << BIT_SHIFT_SEL_V_8822B)\n#define BIT_CLEAR_SEL_V_8822B(x) ((x) & (~BITS_SEL_V_8822B))\n#define BIT_GET_SEL_V_8822B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_SEL_V_8822B) & BIT_MASK_SEL_V_8822B)\n#define BIT_SET_SEL_V_8822B(x, v)                                              \\\n\t(BIT_CLEAR_SEL_V_8822B(x) | BIT_SEL_V_8822B(v))\n\n#define BIT_SEL_LDO_PC_8822B BIT(29)\n\n#define BIT_SHIFT_CK_MON_SEL_8822B 26\n#define BIT_MASK_CK_MON_SEL_8822B 0x7\n#define BIT_CK_MON_SEL_8822B(x)                                                \\\n\t(((x) & BIT_MASK_CK_MON_SEL_8822B) << BIT_SHIFT_CK_MON_SEL_8822B)\n#define BITS_CK_MON_SEL_8822B                                                  \\\n\t(BIT_MASK_CK_MON_SEL_8822B << BIT_SHIFT_CK_MON_SEL_8822B)\n#define BIT_CLEAR_CK_MON_SEL_8822B(x) ((x) & (~BITS_CK_MON_SEL_8822B))\n#define BIT_GET_CK_MON_SEL_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_CK_MON_SEL_8822B) & BIT_MASK_CK_MON_SEL_8822B)\n#define BIT_SET_CK_MON_SEL_8822B(x, v)                                         \\\n\t(BIT_CLEAR_CK_MON_SEL_8822B(x) | BIT_CK_MON_SEL_8822B(v))\n\n#define BIT_CK_MON_EN_8822B BIT(25)\n#define BIT_FREF_EDGE_8822B BIT(24)\n#define BIT_CK320M_EN_8822B BIT(23)\n#define BIT_CK_5M_EN_8822B BIT(22)\n#define BIT_TESTEN_8822B BIT(21)\n\n/* 2 REG_HIMR0_8822B */\n#define BIT_TIMEOUT_INTERRUPT2_MASK_8822B BIT(31)\n#define BIT_TIMEOUT_INTERRUTP1_MASK_8822B BIT(30)\n#define BIT_PSTIMEOUT_MSK_8822B BIT(29)\n#define BIT_GTINT4_MSK_8822B BIT(28)\n#define BIT_GTINT3_MSK_8822B BIT(27)\n#define BIT_TXBCN0ERR_MSK_8822B BIT(26)\n#define BIT_TXBCN0OK_MSK_8822B BIT(25)\n#define BIT_TSF_BIT32_TOGGLE_MSK_8822B BIT(24)\n#define BIT_BCNDMAINT0_MSK_8822B BIT(20)\n#define BIT_BCNDERR0_MSK_8822B BIT(16)\n#define BIT_HSISR_IND_ON_INT_MSK_8822B BIT(15)\n#define BIT_HISR3_IND_INT_MSK_8822B BIT(14)\n#define BIT_HISR2_IND_INT_MSK_8822B BIT(13)\n#define BIT_HISR1_IND_MSK_8822B BIT(11)\n#define BIT_C2HCMD_MSK_8822B BIT(10)\n#define BIT_CPWM2_MSK_8822B BIT(9)\n#define BIT_CPWM_MSK_8822B BIT(8)\n#define BIT_HIGHDOK_MSK_8822B BIT(7)\n#define BIT_MGTDOK_MSK_8822B BIT(6)\n#define BIT_BKDOK_MSK_8822B BIT(5)\n#define BIT_BEDOK_MSK_8822B BIT(4)\n#define BIT_VIDOK_MSK_8822B BIT(3)\n#define BIT_VODOK_MSK_8822B BIT(2)\n#define BIT_RDU_MSK_8822B BIT(1)\n#define BIT_RXOK_MSK_8822B BIT(0)\n\n/* 2 REG_HISR0_8822B */\n#define BIT_PSTIMEOUT2_8822B BIT(31)\n#define BIT_PSTIMEOUT1_8822B BIT(30)\n#define BIT_PSTIMEOUT_8822B BIT(29)\n#define BIT_GTINT4_8822B BIT(28)\n#define BIT_GTINT3_8822B BIT(27)\n#define BIT_TXBCN0ERR_8822B BIT(26)\n#define BIT_TXBCN0OK_8822B BIT(25)\n#define BIT_TSF_BIT32_TOGGLE_8822B BIT(24)\n#define BIT_BCNDMAINT0_8822B BIT(20)\n#define BIT_BCNDERR0_8822B BIT(16)\n#define BIT_HSISR_IND_ON_INT_8822B BIT(15)\n#define BIT_HISR3_IND_INT_8822B BIT(14)\n#define BIT_HISR2_IND_INT_8822B BIT(13)\n#define BIT_HISR1_IND_INT_8822B BIT(11)\n#define BIT_C2HCMD_8822B BIT(10)\n#define BIT_CPWM2_8822B BIT(9)\n#define BIT_CPWM_8822B BIT(8)\n#define BIT_HIGHDOK_8822B BIT(7)\n#define BIT_MGTDOK_8822B BIT(6)\n#define BIT_BKDOK_8822B BIT(5)\n#define BIT_BEDOK_8822B BIT(4)\n#define BIT_VIDOK_8822B BIT(3)\n#define BIT_VODOK_8822B BIT(2)\n#define BIT_RDU_8822B BIT(1)\n#define BIT_RXOK_8822B BIT(0)\n\n/* 2 REG_HIMR1_8822B */\n#define BIT_TXFIFO_TH_INT_8822B BIT(30)\n#define BIT_BTON_STS_UPDATE_MASK_8822B BIT(29)\n#define BIT_BCNDMAINT7__MSK_8822B BIT(27)\n#define BIT_BCNDMAINT6__MSK_8822B BIT(26)\n#define BIT_BCNDMAINT5__MSK_8822B BIT(25)\n#define BIT_BCNDMAINT4__MSK_8822B BIT(24)\n#define BIT_BCNDMAINT3_MSK_8822B BIT(23)\n#define BIT_BCNDMAINT2_MSK_8822B BIT(22)\n#define BIT_BCNDMAINT1_MSK_8822B BIT(21)\n#define BIT_BCNDERR7_MSK_8822B BIT(20)\n#define BIT_BCNDERR6_MSK_8822B BIT(19)\n#define BIT_BCNDERR5_MSK_8822B BIT(18)\n#define BIT_BCNDERR4_MSK_8822B BIT(17)\n#define BIT_BCNDERR3_MSK_8822B BIT(16)\n#define BIT_BCNDERR2_MSK_8822B BIT(15)\n#define BIT_BCNDERR1_MSK_8822B BIT(14)\n#define BIT_ATIMEND_E_V1_MSK_8822B BIT(12)\n#define BIT_TXERR_MSK_8822B BIT(11)\n#define BIT_RXERR_MSK_8822B BIT(10)\n#define BIT_TXFOVW_MSK_8822B BIT(9)\n#define BIT_FOVW_MSK_8822B BIT(8)\n#define BIT_CPU_MGQ_TXDONE_MSK_8822B BIT(5)\n#define BIT_PS_TIMER_C_MSK_8822B BIT(4)\n#define BIT_PS_TIMER_B_MSK_8822B BIT(3)\n#define BIT_PS_TIMER_A_MSK_8822B BIT(2)\n#define BIT_CPUMGQ_TX_TIMER_MSK_8822B BIT(1)\n\n/* 2 REG_HISR1_8822B */\n#define BIT_TXFIFO_TH_INT_8822B BIT(30)\n#define BIT_BTON_STS_UPDATE_INT_8822B BIT(29)\n#define BIT_BCNDMAINT7_8822B BIT(27)\n#define BIT_BCNDMAINT6_8822B BIT(26)\n#define BIT_BCNDMAINT5_8822B BIT(25)\n#define BIT_BCNDMAINT4_8822B BIT(24)\n#define BIT_BCNDMAINT3_8822B BIT(23)\n#define BIT_BCNDMAINT2_8822B BIT(22)\n#define BIT_BCNDMAINT1_8822B BIT(21)\n#define BIT_BCNDERR7_8822B BIT(20)\n#define BIT_BCNDERR6_8822B BIT(19)\n#define BIT_BCNDERR5_8822B BIT(18)\n#define BIT_BCNDERR4_8822B BIT(17)\n#define BIT_BCNDERR3_8822B BIT(16)\n#define BIT_BCNDERR2_8822B BIT(15)\n#define BIT_BCNDERR1_8822B BIT(14)\n#define BIT_ATIMEND_E_V1_INT_8822B BIT(12)\n#define BIT_TXERR_INT_8822B BIT(11)\n#define BIT_RXERR_INT_8822B BIT(10)\n#define BIT_TXFOVW_8822B BIT(9)\n#define BIT_FOVW_8822B BIT(8)\n#define BIT_CPU_MGQ_TXDONE_8822B BIT(5)\n#define BIT_PS_TIMER_C_8822B BIT(4)\n#define BIT_PS_TIMER_B_8822B BIT(3)\n#define BIT_PS_TIMER_A_8822B BIT(2)\n#define BIT_CPUMGQ_TX_TIMER_8822B BIT(1)\n\n/* 2 REG_DBG_PORT_SEL_8822B */\n\n#define BIT_SHIFT_DEBUG_ST_8822B 0\n#define BIT_MASK_DEBUG_ST_8822B 0xffffffffL\n#define BIT_DEBUG_ST_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_DEBUG_ST_8822B) << BIT_SHIFT_DEBUG_ST_8822B)\n#define BITS_DEBUG_ST_8822B                                                    \\\n\t(BIT_MASK_DEBUG_ST_8822B << BIT_SHIFT_DEBUG_ST_8822B)\n#define BIT_CLEAR_DEBUG_ST_8822B(x) ((x) & (~BITS_DEBUG_ST_8822B))\n#define BIT_GET_DEBUG_ST_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_DEBUG_ST_8822B) & BIT_MASK_DEBUG_ST_8822B)\n#define BIT_SET_DEBUG_ST_8822B(x, v)                                           \\\n\t(BIT_CLEAR_DEBUG_ST_8822B(x) | BIT_DEBUG_ST_8822B(v))\n\n/* 2 REG_PAD_CTRL2_8822B */\n#define BIT_USB3_USB2_TRANSITION_8822B BIT(20)\n\n#define BIT_SHIFT_USB23_SW_MODE_V1_8822B 18\n#define BIT_MASK_USB23_SW_MODE_V1_8822B 0x3\n#define BIT_USB23_SW_MODE_V1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_USB23_SW_MODE_V1_8822B)                               \\\n\t << BIT_SHIFT_USB23_SW_MODE_V1_8822B)\n#define BITS_USB23_SW_MODE_V1_8822B                                            \\\n\t(BIT_MASK_USB23_SW_MODE_V1_8822B << BIT_SHIFT_USB23_SW_MODE_V1_8822B)\n#define BIT_CLEAR_USB23_SW_MODE_V1_8822B(x)                                    \\\n\t((x) & (~BITS_USB23_SW_MODE_V1_8822B))\n#define BIT_GET_USB23_SW_MODE_V1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8822B) &                           \\\n\t BIT_MASK_USB23_SW_MODE_V1_8822B)\n#define BIT_SET_USB23_SW_MODE_V1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_USB23_SW_MODE_V1_8822B(x) | BIT_USB23_SW_MODE_V1_8822B(v))\n\n#define BIT_NO_PDN_CHIPOFF_V1_8822B BIT(17)\n#define BIT_RSM_EN_V1_8822B BIT(16)\n\n#define BIT_SHIFT_MATCH_CNT_8822B 8\n#define BIT_MASK_MATCH_CNT_8822B 0xff\n#define BIT_MATCH_CNT_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B)\n#define BITS_MATCH_CNT_8822B                                                   \\\n\t(BIT_MASK_MATCH_CNT_8822B << BIT_SHIFT_MATCH_CNT_8822B)\n#define BIT_CLEAR_MATCH_CNT_8822B(x) ((x) & (~BITS_MATCH_CNT_8822B))\n#define BIT_GET_MATCH_CNT_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B)\n#define BIT_SET_MATCH_CNT_8822B(x, v)                                          \\\n\t(BIT_CLEAR_MATCH_CNT_8822B(x) | BIT_MATCH_CNT_8822B(v))\n\n#define BIT_LD_B12V_EN_8822B BIT(7)\n#define BIT_EECS_IOSEL_V1_8822B BIT(6)\n#define BIT_EECS_DATA_O_V1_8822B BIT(5)\n#define BIT_EECS_DATA_I_V1_8822B BIT(4)\n#define BIT_EESK_IOSEL_V1_8822B BIT(2)\n#define BIT_EESK_DATA_O_V1_8822B BIT(1)\n#define BIT_EESK_DATA_I_V1_8822B BIT(0)\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_PMC_DBG_CTRL2_8822B */\n\n#define BIT_SHIFT_EFUSE_BURN_GNT_8822B 24\n#define BIT_MASK_EFUSE_BURN_GNT_8822B 0xff\n#define BIT_EFUSE_BURN_GNT_8822B(x)                                            \\\n\t(((x) & BIT_MASK_EFUSE_BURN_GNT_8822B)                                 \\\n\t << BIT_SHIFT_EFUSE_BURN_GNT_8822B)\n#define BITS_EFUSE_BURN_GNT_8822B                                              \\\n\t(BIT_MASK_EFUSE_BURN_GNT_8822B << BIT_SHIFT_EFUSE_BURN_GNT_8822B)\n#define BIT_CLEAR_EFUSE_BURN_GNT_8822B(x) ((x) & (~BITS_EFUSE_BURN_GNT_8822B))\n#define BIT_GET_EFUSE_BURN_GNT_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8822B) &                             \\\n\t BIT_MASK_EFUSE_BURN_GNT_8822B)\n#define BIT_SET_EFUSE_BURN_GNT_8822B(x, v)                                     \\\n\t(BIT_CLEAR_EFUSE_BURN_GNT_8822B(x) | BIT_EFUSE_BURN_GNT_8822B(v))\n\n#define BIT_STOP_WL_PMC_8822B BIT(9)\n#define BIT_STOP_SYM_PMC_8822B BIT(8)\n#define BIT_REG_RST_WLPMC_8822B BIT(5)\n#define BIT_REG_RST_PD12N_8822B BIT(4)\n#define BIT_SYSON_DIS_WLREG_WRMSK_8822B BIT(3)\n#define BIT_SYSON_DIS_PMCREG_WRMSK_8822B BIT(2)\n\n#define BIT_SHIFT_SYSON_REG_ARB_8822B 0\n#define BIT_MASK_SYSON_REG_ARB_8822B 0x3\n#define BIT_SYSON_REG_ARB_8822B(x)                                             \\\n\t(((x) & BIT_MASK_SYSON_REG_ARB_8822B) << BIT_SHIFT_SYSON_REG_ARB_8822B)\n#define BITS_SYSON_REG_ARB_8822B                                               \\\n\t(BIT_MASK_SYSON_REG_ARB_8822B << BIT_SHIFT_SYSON_REG_ARB_8822B)\n#define BIT_CLEAR_SYSON_REG_ARB_8822B(x) ((x) & (~BITS_SYSON_REG_ARB_8822B))\n#define BIT_GET_SYSON_REG_ARB_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SYSON_REG_ARB_8822B) & BIT_MASK_SYSON_REG_ARB_8822B)\n#define BIT_SET_SYSON_REG_ARB_8822B(x, v)                                      \\\n\t(BIT_CLEAR_SYSON_REG_ARB_8822B(x) | BIT_SYSON_REG_ARB_8822B(v))\n\n/* 2 REG_BIST_CTRL_8822B */\n#define BIT_BIST_USB_DIS_8822B BIT(27)\n#define BIT_BIST_PCI_DIS_8822B BIT(26)\n#define BIT_BIST_BT_DIS_8822B BIT(25)\n#define BIT_BIST_WL_DIS_8822B BIT(24)\n\n#define BIT_SHIFT_BIST_RPT_SEL_8822B 16\n#define BIT_MASK_BIST_RPT_SEL_8822B 0xf\n#define BIT_BIST_RPT_SEL_8822B(x)                                              \\\n\t(((x) & BIT_MASK_BIST_RPT_SEL_8822B) << BIT_SHIFT_BIST_RPT_SEL_8822B)\n#define BITS_BIST_RPT_SEL_8822B                                                \\\n\t(BIT_MASK_BIST_RPT_SEL_8822B << BIT_SHIFT_BIST_RPT_SEL_8822B)\n#define BIT_CLEAR_BIST_RPT_SEL_8822B(x) ((x) & (~BITS_BIST_RPT_SEL_8822B))\n#define BIT_GET_BIST_RPT_SEL_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BIST_RPT_SEL_8822B) & BIT_MASK_BIST_RPT_SEL_8822B)\n#define BIT_SET_BIST_RPT_SEL_8822B(x, v)                                       \\\n\t(BIT_CLEAR_BIST_RPT_SEL_8822B(x) | BIT_BIST_RPT_SEL_8822B(v))\n\n#define BIT_BIST_RESUME_PS_8822B BIT(4)\n#define BIT_BIST_RESUME_8822B BIT(3)\n#define BIT_BIST_NORMAL_8822B BIT(2)\n#define BIT_BIST_RSTN_8822B BIT(1)\n#define BIT_BIST_CLK_EN_8822B BIT(0)\n\n/* 2 REG_BIST_RPT_8822B */\n\n#define BIT_SHIFT_MBIST_REPORT_8822B 0\n#define BIT_MASK_MBIST_REPORT_8822B 0xffffffffL\n#define BIT_MBIST_REPORT_8822B(x)                                              \\\n\t(((x) & BIT_MASK_MBIST_REPORT_8822B) << BIT_SHIFT_MBIST_REPORT_8822B)\n#define BITS_MBIST_REPORT_8822B                                                \\\n\t(BIT_MASK_MBIST_REPORT_8822B << BIT_SHIFT_MBIST_REPORT_8822B)\n#define BIT_CLEAR_MBIST_REPORT_8822B(x) ((x) & (~BITS_MBIST_REPORT_8822B))\n#define BIT_GET_MBIST_REPORT_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_MBIST_REPORT_8822B) & BIT_MASK_MBIST_REPORT_8822B)\n#define BIT_SET_MBIST_REPORT_8822B(x, v)                                       \\\n\t(BIT_CLEAR_MBIST_REPORT_8822B(x) | BIT_MBIST_REPORT_8822B(v))\n\n/* 2 REG_MEM_CTRL_8822B */\n#define BIT_UMEM_RME_8822B BIT(31)\n\n#define BIT_SHIFT_BT_SPRAM_8822B 28\n#define BIT_MASK_BT_SPRAM_8822B 0x3\n#define BIT_BT_SPRAM_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_BT_SPRAM_8822B) << BIT_SHIFT_BT_SPRAM_8822B)\n#define BITS_BT_SPRAM_8822B                                                    \\\n\t(BIT_MASK_BT_SPRAM_8822B << BIT_SHIFT_BT_SPRAM_8822B)\n#define BIT_CLEAR_BT_SPRAM_8822B(x) ((x) & (~BITS_BT_SPRAM_8822B))\n#define BIT_GET_BT_SPRAM_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_BT_SPRAM_8822B) & BIT_MASK_BT_SPRAM_8822B)\n#define BIT_SET_BT_SPRAM_8822B(x, v)                                           \\\n\t(BIT_CLEAR_BT_SPRAM_8822B(x) | BIT_BT_SPRAM_8822B(v))\n\n#define BIT_SHIFT_BT_ROM_8822B 24\n#define BIT_MASK_BT_ROM_8822B 0xf\n#define BIT_BT_ROM_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_BT_ROM_8822B) << BIT_SHIFT_BT_ROM_8822B)\n#define BITS_BT_ROM_8822B (BIT_MASK_BT_ROM_8822B << BIT_SHIFT_BT_ROM_8822B)\n#define BIT_CLEAR_BT_ROM_8822B(x) ((x) & (~BITS_BT_ROM_8822B))\n#define BIT_GET_BT_ROM_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_BT_ROM_8822B) & BIT_MASK_BT_ROM_8822B)\n#define BIT_SET_BT_ROM_8822B(x, v)                                             \\\n\t(BIT_CLEAR_BT_ROM_8822B(x) | BIT_BT_ROM_8822B(v))\n\n#define BIT_SHIFT_PCI_DPRAM_8822B 10\n#define BIT_MASK_PCI_DPRAM_8822B 0x3\n#define BIT_PCI_DPRAM_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_PCI_DPRAM_8822B) << BIT_SHIFT_PCI_DPRAM_8822B)\n#define BITS_PCI_DPRAM_8822B                                                   \\\n\t(BIT_MASK_PCI_DPRAM_8822B << BIT_SHIFT_PCI_DPRAM_8822B)\n#define BIT_CLEAR_PCI_DPRAM_8822B(x) ((x) & (~BITS_PCI_DPRAM_8822B))\n#define BIT_GET_PCI_DPRAM_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_PCI_DPRAM_8822B) & BIT_MASK_PCI_DPRAM_8822B)\n#define BIT_SET_PCI_DPRAM_8822B(x, v)                                          \\\n\t(BIT_CLEAR_PCI_DPRAM_8822B(x) | BIT_PCI_DPRAM_8822B(v))\n\n#define BIT_SHIFT_PCI_SPRAM_8822B 8\n#define BIT_MASK_PCI_SPRAM_8822B 0x3\n#define BIT_PCI_SPRAM_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_PCI_SPRAM_8822B) << BIT_SHIFT_PCI_SPRAM_8822B)\n#define BITS_PCI_SPRAM_8822B                                                   \\\n\t(BIT_MASK_PCI_SPRAM_8822B << BIT_SHIFT_PCI_SPRAM_8822B)\n#define BIT_CLEAR_PCI_SPRAM_8822B(x) ((x) & (~BITS_PCI_SPRAM_8822B))\n#define BIT_GET_PCI_SPRAM_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_PCI_SPRAM_8822B) & BIT_MASK_PCI_SPRAM_8822B)\n#define BIT_SET_PCI_SPRAM_8822B(x, v)                                          \\\n\t(BIT_CLEAR_PCI_SPRAM_8822B(x) | BIT_PCI_SPRAM_8822B(v))\n\n#define BIT_SHIFT_USB_SPRAM_8822B 6\n#define BIT_MASK_USB_SPRAM_8822B 0x3\n#define BIT_USB_SPRAM_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_USB_SPRAM_8822B) << BIT_SHIFT_USB_SPRAM_8822B)\n#define BITS_USB_SPRAM_8822B                                                   \\\n\t(BIT_MASK_USB_SPRAM_8822B << BIT_SHIFT_USB_SPRAM_8822B)\n#define BIT_CLEAR_USB_SPRAM_8822B(x) ((x) & (~BITS_USB_SPRAM_8822B))\n#define BIT_GET_USB_SPRAM_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_USB_SPRAM_8822B) & BIT_MASK_USB_SPRAM_8822B)\n#define BIT_SET_USB_SPRAM_8822B(x, v)                                          \\\n\t(BIT_CLEAR_USB_SPRAM_8822B(x) | BIT_USB_SPRAM_8822B(v))\n\n#define BIT_SHIFT_USB_SPRF_8822B 4\n#define BIT_MASK_USB_SPRF_8822B 0x3\n#define BIT_USB_SPRF_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_USB_SPRF_8822B) << BIT_SHIFT_USB_SPRF_8822B)\n#define BITS_USB_SPRF_8822B                                                    \\\n\t(BIT_MASK_USB_SPRF_8822B << BIT_SHIFT_USB_SPRF_8822B)\n#define BIT_CLEAR_USB_SPRF_8822B(x) ((x) & (~BITS_USB_SPRF_8822B))\n#define BIT_GET_USB_SPRF_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_USB_SPRF_8822B) & BIT_MASK_USB_SPRF_8822B)\n#define BIT_SET_USB_SPRF_8822B(x, v)                                           \\\n\t(BIT_CLEAR_USB_SPRF_8822B(x) | BIT_USB_SPRF_8822B(v))\n\n#define BIT_SHIFT_MCU_ROM_8822B 0\n#define BIT_MASK_MCU_ROM_8822B 0xf\n#define BIT_MCU_ROM_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_MCU_ROM_8822B) << BIT_SHIFT_MCU_ROM_8822B)\n#define BITS_MCU_ROM_8822B (BIT_MASK_MCU_ROM_8822B << BIT_SHIFT_MCU_ROM_8822B)\n#define BIT_CLEAR_MCU_ROM_8822B(x) ((x) & (~BITS_MCU_ROM_8822B))\n#define BIT_GET_MCU_ROM_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_MCU_ROM_8822B) & BIT_MASK_MCU_ROM_8822B)\n#define BIT_SET_MCU_ROM_8822B(x, v)                                            \\\n\t(BIT_CLEAR_MCU_ROM_8822B(x) | BIT_MCU_ROM_8822B(v))\n\n/* 2 REG_AFE_CTRL8_8822B */\n#define BIT_SYN_AGPIO_8822B BIT(20)\n#define BIT_XTAL_LP_8822B BIT(4)\n#define BIT_XTAL_GM_SEP_8822B BIT(3)\n\n#define BIT_SHIFT_XTAL_SEL_TOK_8822B 0\n#define BIT_MASK_XTAL_SEL_TOK_8822B 0x7\n#define BIT_XTAL_SEL_TOK_8822B(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_SEL_TOK_8822B) << BIT_SHIFT_XTAL_SEL_TOK_8822B)\n#define BITS_XTAL_SEL_TOK_8822B                                                \\\n\t(BIT_MASK_XTAL_SEL_TOK_8822B << BIT_SHIFT_XTAL_SEL_TOK_8822B)\n#define BIT_CLEAR_XTAL_SEL_TOK_8822B(x) ((x) & (~BITS_XTAL_SEL_TOK_8822B))\n#define BIT_GET_XTAL_SEL_TOK_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_SEL_TOK_8822B) & BIT_MASK_XTAL_SEL_TOK_8822B)\n#define BIT_SET_XTAL_SEL_TOK_8822B(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_SEL_TOK_8822B(x) | BIT_XTAL_SEL_TOK_8822B(v))\n\n/* 2 REG_USB_SIE_INTF_8822B */\n#define BIT_RD_SEL_8822B BIT(31)\n#define BIT_USB_SIE_INTF_WE_V1_8822B BIT(30)\n#define BIT_USB_SIE_INTF_BYIOREG_V1_8822B BIT(29)\n#define BIT_USB_SIE_SELECT_8822B BIT(28)\n\n#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B 16\n#define BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B 0x1ff\n#define BIT_USB_SIE_INTF_ADDR_V1_8822B(x)                                      \\\n\t(((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B)                           \\\n\t << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B)\n#define BITS_USB_SIE_INTF_ADDR_V1_8822B                                        \\\n\t(BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B                                   \\\n\t << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B)\n#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822B(x)                                \\\n\t((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8822B))\n#define BIT_GET_USB_SIE_INTF_ADDR_V1_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B) &                       \\\n\t BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B)\n#define BIT_SET_USB_SIE_INTF_ADDR_V1_8822B(x, v)                               \\\n\t(BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822B(x) |                             \\\n\t BIT_USB_SIE_INTF_ADDR_V1_8822B(v))\n\n#define BIT_SHIFT_USB_SIE_INTF_RD_8822B 8\n#define BIT_MASK_USB_SIE_INTF_RD_8822B 0xff\n#define BIT_USB_SIE_INTF_RD_8822B(x)                                           \\\n\t(((x) & BIT_MASK_USB_SIE_INTF_RD_8822B)                                \\\n\t << BIT_SHIFT_USB_SIE_INTF_RD_8822B)\n#define BITS_USB_SIE_INTF_RD_8822B                                             \\\n\t(BIT_MASK_USB_SIE_INTF_RD_8822B << BIT_SHIFT_USB_SIE_INTF_RD_8822B)\n#define BIT_CLEAR_USB_SIE_INTF_RD_8822B(x) ((x) & (~BITS_USB_SIE_INTF_RD_8822B))\n#define BIT_GET_USB_SIE_INTF_RD_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8822B) &                            \\\n\t BIT_MASK_USB_SIE_INTF_RD_8822B)\n#define BIT_SET_USB_SIE_INTF_RD_8822B(x, v)                                    \\\n\t(BIT_CLEAR_USB_SIE_INTF_RD_8822B(x) | BIT_USB_SIE_INTF_RD_8822B(v))\n\n#define BIT_SHIFT_USB_SIE_INTF_WD_8822B 0\n#define BIT_MASK_USB_SIE_INTF_WD_8822B 0xff\n#define BIT_USB_SIE_INTF_WD_8822B(x)                                           \\\n\t(((x) & BIT_MASK_USB_SIE_INTF_WD_8822B)                                \\\n\t << BIT_SHIFT_USB_SIE_INTF_WD_8822B)\n#define BITS_USB_SIE_INTF_WD_8822B                                             \\\n\t(BIT_MASK_USB_SIE_INTF_WD_8822B << BIT_SHIFT_USB_SIE_INTF_WD_8822B)\n#define BIT_CLEAR_USB_SIE_INTF_WD_8822B(x) ((x) & (~BITS_USB_SIE_INTF_WD_8822B))\n#define BIT_GET_USB_SIE_INTF_WD_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8822B) &                            \\\n\t BIT_MASK_USB_SIE_INTF_WD_8822B)\n#define BIT_SET_USB_SIE_INTF_WD_8822B(x, v)                                    \\\n\t(BIT_CLEAR_USB_SIE_INTF_WD_8822B(x) | BIT_USB_SIE_INTF_WD_8822B(v))\n\n/* 2 REG_PCIE_MIO_INTF_8822B */\n#define BIT_PCIE_MIO_BYIOREG_8822B BIT(13)\n#define BIT_PCIE_MIO_RE_8822B BIT(12)\n\n#define BIT_SHIFT_PCIE_MIO_WE_8822B 8\n#define BIT_MASK_PCIE_MIO_WE_8822B 0xf\n#define BIT_PCIE_MIO_WE_8822B(x)                                               \\\n\t(((x) & BIT_MASK_PCIE_MIO_WE_8822B) << BIT_SHIFT_PCIE_MIO_WE_8822B)\n#define BITS_PCIE_MIO_WE_8822B                                                 \\\n\t(BIT_MASK_PCIE_MIO_WE_8822B << BIT_SHIFT_PCIE_MIO_WE_8822B)\n#define BIT_CLEAR_PCIE_MIO_WE_8822B(x) ((x) & (~BITS_PCIE_MIO_WE_8822B))\n#define BIT_GET_PCIE_MIO_WE_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_WE_8822B) & BIT_MASK_PCIE_MIO_WE_8822B)\n#define BIT_SET_PCIE_MIO_WE_8822B(x, v)                                        \\\n\t(BIT_CLEAR_PCIE_MIO_WE_8822B(x) | BIT_PCIE_MIO_WE_8822B(v))\n\n#define BIT_SHIFT_PCIE_MIO_ADDR_8822B 0\n#define BIT_MASK_PCIE_MIO_ADDR_8822B 0xff\n#define BIT_PCIE_MIO_ADDR_8822B(x)                                             \\\n\t(((x) & BIT_MASK_PCIE_MIO_ADDR_8822B) << BIT_SHIFT_PCIE_MIO_ADDR_8822B)\n#define BITS_PCIE_MIO_ADDR_8822B                                               \\\n\t(BIT_MASK_PCIE_MIO_ADDR_8822B << BIT_SHIFT_PCIE_MIO_ADDR_8822B)\n#define BIT_CLEAR_PCIE_MIO_ADDR_8822B(x) ((x) & (~BITS_PCIE_MIO_ADDR_8822B))\n#define BIT_GET_PCIE_MIO_ADDR_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8822B) & BIT_MASK_PCIE_MIO_ADDR_8822B)\n#define BIT_SET_PCIE_MIO_ADDR_8822B(x, v)                                      \\\n\t(BIT_CLEAR_PCIE_MIO_ADDR_8822B(x) | BIT_PCIE_MIO_ADDR_8822B(v))\n\n/* 2 REG_PCIE_MIO_INTD_8822B */\n\n#define BIT_SHIFT_PCIE_MIO_DATA_8822B 0\n#define BIT_MASK_PCIE_MIO_DATA_8822B 0xffffffffL\n#define BIT_PCIE_MIO_DATA_8822B(x)                                             \\\n\t(((x) & BIT_MASK_PCIE_MIO_DATA_8822B) << BIT_SHIFT_PCIE_MIO_DATA_8822B)\n#define BITS_PCIE_MIO_DATA_8822B                                               \\\n\t(BIT_MASK_PCIE_MIO_DATA_8822B << BIT_SHIFT_PCIE_MIO_DATA_8822B)\n#define BIT_CLEAR_PCIE_MIO_DATA_8822B(x) ((x) & (~BITS_PCIE_MIO_DATA_8822B))\n#define BIT_GET_PCIE_MIO_DATA_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_DATA_8822B) & BIT_MASK_PCIE_MIO_DATA_8822B)\n#define BIT_SET_PCIE_MIO_DATA_8822B(x, v)                                      \\\n\t(BIT_CLEAR_PCIE_MIO_DATA_8822B(x) | BIT_PCIE_MIO_DATA_8822B(v))\n\n/* 2 REG_WLRF1_8822B */\n\n#define BIT_SHIFT_WLRF1_CTRL_8822B 24\n#define BIT_MASK_WLRF1_CTRL_8822B 0xff\n#define BIT_WLRF1_CTRL_8822B(x)                                                \\\n\t(((x) & BIT_MASK_WLRF1_CTRL_8822B) << BIT_SHIFT_WLRF1_CTRL_8822B)\n#define BITS_WLRF1_CTRL_8822B                                                  \\\n\t(BIT_MASK_WLRF1_CTRL_8822B << BIT_SHIFT_WLRF1_CTRL_8822B)\n#define BIT_CLEAR_WLRF1_CTRL_8822B(x) ((x) & (~BITS_WLRF1_CTRL_8822B))\n#define BIT_GET_WLRF1_CTRL_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_WLRF1_CTRL_8822B) & BIT_MASK_WLRF1_CTRL_8822B)\n#define BIT_SET_WLRF1_CTRL_8822B(x, v)                                         \\\n\t(BIT_CLEAR_WLRF1_CTRL_8822B(x) | BIT_WLRF1_CTRL_8822B(v))\n\n/* 2 REG_SYS_CFG1_8822B */\n\n#define BIT_SHIFT_TRP_ICFG_8822B 28\n#define BIT_MASK_TRP_ICFG_8822B 0xf\n#define BIT_TRP_ICFG_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_TRP_ICFG_8822B) << BIT_SHIFT_TRP_ICFG_8822B)\n#define BITS_TRP_ICFG_8822B                                                    \\\n\t(BIT_MASK_TRP_ICFG_8822B << BIT_SHIFT_TRP_ICFG_8822B)\n#define BIT_CLEAR_TRP_ICFG_8822B(x) ((x) & (~BITS_TRP_ICFG_8822B))\n#define BIT_GET_TRP_ICFG_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TRP_ICFG_8822B) & BIT_MASK_TRP_ICFG_8822B)\n#define BIT_SET_TRP_ICFG_8822B(x, v)                                           \\\n\t(BIT_CLEAR_TRP_ICFG_8822B(x) | BIT_TRP_ICFG_8822B(v))\n\n#define BIT_RF_TYPE_ID_8822B BIT(27)\n#define BIT_BD_HCI_SEL_8822B BIT(26)\n#define BIT_BD_PKG_SEL_8822B BIT(25)\n#define BIT_SPSLDO_SEL_8822B BIT(24)\n#define BIT_RTL_ID_8822B BIT(23)\n#define BIT_PAD_HWPD_IDN_8822B BIT(22)\n#define BIT_TESTMODE_8822B BIT(20)\n\n#define BIT_SHIFT_VENDOR_ID_8822B 16\n#define BIT_MASK_VENDOR_ID_8822B 0xf\n#define BIT_VENDOR_ID_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_VENDOR_ID_8822B) << BIT_SHIFT_VENDOR_ID_8822B)\n#define BITS_VENDOR_ID_8822B                                                   \\\n\t(BIT_MASK_VENDOR_ID_8822B << BIT_SHIFT_VENDOR_ID_8822B)\n#define BIT_CLEAR_VENDOR_ID_8822B(x) ((x) & (~BITS_VENDOR_ID_8822B))\n#define BIT_GET_VENDOR_ID_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_VENDOR_ID_8822B) & BIT_MASK_VENDOR_ID_8822B)\n#define BIT_SET_VENDOR_ID_8822B(x, v)                                          \\\n\t(BIT_CLEAR_VENDOR_ID_8822B(x) | BIT_VENDOR_ID_8822B(v))\n\n#define BIT_SHIFT_CHIP_VER_8822B 12\n#define BIT_MASK_CHIP_VER_8822B 0xf\n#define BIT_CHIP_VER_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_CHIP_VER_8822B) << BIT_SHIFT_CHIP_VER_8822B)\n#define BITS_CHIP_VER_8822B                                                    \\\n\t(BIT_MASK_CHIP_VER_8822B << BIT_SHIFT_CHIP_VER_8822B)\n#define BIT_CLEAR_CHIP_VER_8822B(x) ((x) & (~BITS_CHIP_VER_8822B))\n#define BIT_GET_CHIP_VER_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_CHIP_VER_8822B) & BIT_MASK_CHIP_VER_8822B)\n#define BIT_SET_CHIP_VER_8822B(x, v)                                           \\\n\t(BIT_CLEAR_CHIP_VER_8822B(x) | BIT_CHIP_VER_8822B(v))\n\n#define BIT_BD_MAC3_8822B BIT(11)\n#define BIT_BD_MAC1_8822B BIT(10)\n#define BIT_BD_MAC2_8822B BIT(9)\n#define BIT_SIC_IDLE_8822B BIT(8)\n#define BIT_SW_OFFLOAD_EN_8822B BIT(7)\n#define BIT_OCP_SHUTDN_8822B BIT(6)\n#define BIT_V15_VLD_8822B BIT(5)\n#define BIT_PCIRSTB_8822B BIT(4)\n#define BIT_PCLK_VLD_8822B BIT(3)\n#define BIT_UCLK_VLD_8822B BIT(2)\n#define BIT_ACLK_VLD_8822B BIT(1)\n#define BIT_XCLK_VLD_8822B BIT(0)\n\n/* 2 REG_SYS_STATUS1_8822B */\n\n#define BIT_SHIFT_RF_RL_ID_8822B 28\n#define BIT_MASK_RF_RL_ID_8822B 0xf\n#define BIT_RF_RL_ID_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_RF_RL_ID_8822B) << BIT_SHIFT_RF_RL_ID_8822B)\n#define BITS_RF_RL_ID_8822B                                                    \\\n\t(BIT_MASK_RF_RL_ID_8822B << BIT_SHIFT_RF_RL_ID_8822B)\n#define BIT_CLEAR_RF_RL_ID_8822B(x) ((x) & (~BITS_RF_RL_ID_8822B))\n#define BIT_GET_RF_RL_ID_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RF_RL_ID_8822B) & BIT_MASK_RF_RL_ID_8822B)\n#define BIT_SET_RF_RL_ID_8822B(x, v)                                           \\\n\t(BIT_CLEAR_RF_RL_ID_8822B(x) | BIT_RF_RL_ID_8822B(v))\n\n#define BIT_HPHY_ICFG_8822B BIT(19)\n\n#define BIT_SHIFT_SEL_0XC0_8822B 16\n#define BIT_MASK_SEL_0XC0_8822B 0x3\n#define BIT_SEL_0XC0_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_SEL_0XC0_8822B) << BIT_SHIFT_SEL_0XC0_8822B)\n#define BITS_SEL_0XC0_8822B                                                    \\\n\t(BIT_MASK_SEL_0XC0_8822B << BIT_SHIFT_SEL_0XC0_8822B)\n#define BIT_CLEAR_SEL_0XC0_8822B(x) ((x) & (~BITS_SEL_0XC0_8822B))\n#define BIT_GET_SEL_0XC0_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_SEL_0XC0_8822B) & BIT_MASK_SEL_0XC0_8822B)\n#define BIT_SET_SEL_0XC0_8822B(x, v)                                           \\\n\t(BIT_CLEAR_SEL_0XC0_8822B(x) | BIT_SEL_0XC0_8822B(v))\n\n#define BIT_SHIFT_HCI_SEL_V3_8822B 12\n#define BIT_MASK_HCI_SEL_V3_8822B 0x7\n#define BIT_HCI_SEL_V3_8822B(x)                                                \\\n\t(((x) & BIT_MASK_HCI_SEL_V3_8822B) << BIT_SHIFT_HCI_SEL_V3_8822B)\n#define BITS_HCI_SEL_V3_8822B                                                  \\\n\t(BIT_MASK_HCI_SEL_V3_8822B << BIT_SHIFT_HCI_SEL_V3_8822B)\n#define BIT_CLEAR_HCI_SEL_V3_8822B(x) ((x) & (~BITS_HCI_SEL_V3_8822B))\n#define BIT_GET_HCI_SEL_V3_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_HCI_SEL_V3_8822B) & BIT_MASK_HCI_SEL_V3_8822B)\n#define BIT_SET_HCI_SEL_V3_8822B(x, v)                                         \\\n\t(BIT_CLEAR_HCI_SEL_V3_8822B(x) | BIT_HCI_SEL_V3_8822B(v))\n\n#define BIT_USB_OPERATION_MODE_8822B BIT(10)\n#define BIT_BT_PDN_8822B BIT(9)\n#define BIT_AUTO_WLPON_8822B BIT(8)\n#define BIT_WL_MODE_8822B BIT(7)\n#define BIT_PKG_SEL_HCI_8822B BIT(6)\n\n#define BIT_SHIFT_PAD_HCI_SEL_V1_8822B 3\n#define BIT_MASK_PAD_HCI_SEL_V1_8822B 0x7\n#define BIT_PAD_HCI_SEL_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_PAD_HCI_SEL_V1_8822B)                                 \\\n\t << BIT_SHIFT_PAD_HCI_SEL_V1_8822B)\n#define BITS_PAD_HCI_SEL_V1_8822B                                              \\\n\t(BIT_MASK_PAD_HCI_SEL_V1_8822B << BIT_SHIFT_PAD_HCI_SEL_V1_8822B)\n#define BIT_CLEAR_PAD_HCI_SEL_V1_8822B(x) ((x) & (~BITS_PAD_HCI_SEL_V1_8822B))\n#define BIT_GET_PAD_HCI_SEL_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_PAD_HCI_SEL_V1_8822B) &                             \\\n\t BIT_MASK_PAD_HCI_SEL_V1_8822B)\n#define BIT_SET_PAD_HCI_SEL_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_PAD_HCI_SEL_V1_8822B(x) | BIT_PAD_HCI_SEL_V1_8822B(v))\n\n#define BIT_SHIFT_EFS_HCI_SEL_V1_8822B 0\n#define BIT_MASK_EFS_HCI_SEL_V1_8822B 0x7\n#define BIT_EFS_HCI_SEL_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_EFS_HCI_SEL_V1_8822B)                                 \\\n\t << BIT_SHIFT_EFS_HCI_SEL_V1_8822B)\n#define BITS_EFS_HCI_SEL_V1_8822B                                              \\\n\t(BIT_MASK_EFS_HCI_SEL_V1_8822B << BIT_SHIFT_EFS_HCI_SEL_V1_8822B)\n#define BIT_CLEAR_EFS_HCI_SEL_V1_8822B(x) ((x) & (~BITS_EFS_HCI_SEL_V1_8822B))\n#define BIT_GET_EFS_HCI_SEL_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_EFS_HCI_SEL_V1_8822B) &                             \\\n\t BIT_MASK_EFS_HCI_SEL_V1_8822B)\n#define BIT_SET_EFS_HCI_SEL_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_EFS_HCI_SEL_V1_8822B(x) | BIT_EFS_HCI_SEL_V1_8822B(v))\n\n/* 2 REG_SYS_STATUS2_8822B */\n#define BIT_SIO_ALDN_8822B BIT(19)\n#define BIT_USB_ALDN_8822B BIT(18)\n#define BIT_PCI_ALDN_8822B BIT(17)\n#define BIT_SYS_ALDN_8822B BIT(16)\n\n#define BIT_SHIFT_EPVID1_8822B 8\n#define BIT_MASK_EPVID1_8822B 0xff\n#define BIT_EPVID1_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_EPVID1_8822B) << BIT_SHIFT_EPVID1_8822B)\n#define BITS_EPVID1_8822B (BIT_MASK_EPVID1_8822B << BIT_SHIFT_EPVID1_8822B)\n#define BIT_CLEAR_EPVID1_8822B(x) ((x) & (~BITS_EPVID1_8822B))\n#define BIT_GET_EPVID1_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_EPVID1_8822B) & BIT_MASK_EPVID1_8822B)\n#define BIT_SET_EPVID1_8822B(x, v)                                             \\\n\t(BIT_CLEAR_EPVID1_8822B(x) | BIT_EPVID1_8822B(v))\n\n#define BIT_SHIFT_EPVID0_8822B 0\n#define BIT_MASK_EPVID0_8822B 0xff\n#define BIT_EPVID0_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_EPVID0_8822B) << BIT_SHIFT_EPVID0_8822B)\n#define BITS_EPVID0_8822B (BIT_MASK_EPVID0_8822B << BIT_SHIFT_EPVID0_8822B)\n#define BIT_CLEAR_EPVID0_8822B(x) ((x) & (~BITS_EPVID0_8822B))\n#define BIT_GET_EPVID0_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_EPVID0_8822B) & BIT_MASK_EPVID0_8822B)\n#define BIT_SET_EPVID0_8822B(x, v)                                             \\\n\t(BIT_CLEAR_EPVID0_8822B(x) | BIT_EPVID0_8822B(v))\n\n/* 2 REG_SYS_CFG2_8822B */\n#define BIT_HCI_SEL_EMBEDDED_8822B BIT(8)\n\n#define BIT_SHIFT_HW_ID_8822B 0\n#define BIT_MASK_HW_ID_8822B 0xff\n#define BIT_HW_ID_8822B(x)                                                     \\\n\t(((x) & BIT_MASK_HW_ID_8822B) << BIT_SHIFT_HW_ID_8822B)\n#define BITS_HW_ID_8822B (BIT_MASK_HW_ID_8822B << BIT_SHIFT_HW_ID_8822B)\n#define BIT_CLEAR_HW_ID_8822B(x) ((x) & (~BITS_HW_ID_8822B))\n#define BIT_GET_HW_ID_8822B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HW_ID_8822B) & BIT_MASK_HW_ID_8822B)\n#define BIT_SET_HW_ID_8822B(x, v)                                              \\\n\t(BIT_CLEAR_HW_ID_8822B(x) | BIT_HW_ID_8822B(v))\n\n/* 2 REG_SYS_CFG3_8822B */\n#define BIT_PWC_MA33V_8822B BIT(15)\n#define BIT_PWC_MA12V_8822B BIT(14)\n#define BIT_PWC_MD12V_8822B BIT(13)\n#define BIT_PWC_PD12V_8822B BIT(12)\n#define BIT_PWC_UD12V_8822B BIT(11)\n#define BIT_ISO_MA2MD_8822B BIT(1)\n#define BIT_ISO_MD2PP_8822B BIT(0)\n\n/* 2 REG_SYS_CFG4_8822B */\n\n/* 2 REG_SYS_CFG5_8822B */\n#define BIT_LPS_STATUS_8822B BIT(3)\n#define BIT_HCI_TXDMA_BUSY_8822B BIT(2)\n#define BIT_HCI_TXDMA_ALLOW_8822B BIT(1)\n#define BIT_FW_CTRL_HCI_TXDMA_EN_8822B BIT(0)\n\n/* 2 REG_CPU_DMEM_CON_8822B */\n#define BIT_WDT_OPT_IOWRAPPER_8822B BIT(19)\n#define BIT_ANA_PORT_IDLE_8822B BIT(18)\n#define BIT_MAC_PORT_IDLE_8822B BIT(17)\n#define BIT_WL_PLATFORM_RST_8822B BIT(16)\n#define BIT_WL_SECURITY_CLK_8822B BIT(15)\n\n#define BIT_SHIFT_CPU_DMEM_CON_8822B 0\n#define BIT_MASK_CPU_DMEM_CON_8822B 0xff\n#define BIT_CPU_DMEM_CON_8822B(x)                                              \\\n\t(((x) & BIT_MASK_CPU_DMEM_CON_8822B) << BIT_SHIFT_CPU_DMEM_CON_8822B)\n#define BITS_CPU_DMEM_CON_8822B                                                \\\n\t(BIT_MASK_CPU_DMEM_CON_8822B << BIT_SHIFT_CPU_DMEM_CON_8822B)\n#define BIT_CLEAR_CPU_DMEM_CON_8822B(x) ((x) & (~BITS_CPU_DMEM_CON_8822B))\n#define BIT_GET_CPU_DMEM_CON_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CPU_DMEM_CON_8822B) & BIT_MASK_CPU_DMEM_CON_8822B)\n#define BIT_SET_CPU_DMEM_CON_8822B(x, v)                                       \\\n\t(BIT_CLEAR_CPU_DMEM_CON_8822B(x) | BIT_CPU_DMEM_CON_8822B(v))\n\n/* 2 REG_BOOT_REASON_8822B */\n\n#define BIT_SHIFT_BOOT_REASON_V1_8822B 0\n#define BIT_MASK_BOOT_REASON_V1_8822B 0x7\n#define BIT_BOOT_REASON_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_BOOT_REASON_V1_8822B)                                 \\\n\t << BIT_SHIFT_BOOT_REASON_V1_8822B)\n#define BITS_BOOT_REASON_V1_8822B                                              \\\n\t(BIT_MASK_BOOT_REASON_V1_8822B << BIT_SHIFT_BOOT_REASON_V1_8822B)\n#define BIT_CLEAR_BOOT_REASON_V1_8822B(x) ((x) & (~BITS_BOOT_REASON_V1_8822B))\n#define BIT_GET_BOOT_REASON_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_BOOT_REASON_V1_8822B) &                             \\\n\t BIT_MASK_BOOT_REASON_V1_8822B)\n#define BIT_SET_BOOT_REASON_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_BOOT_REASON_V1_8822B(x) | BIT_BOOT_REASON_V1_8822B(v))\n\n/* 2 REG_NFCPAD_CTRL_8822B */\n#define BIT_PAD_SHUTDW_8822B BIT(18)\n#define BIT_SYSON_NFC_PAD_8822B BIT(17)\n#define BIT_NFC_INT_PAD_CTRL_8822B BIT(16)\n#define BIT_NFC_RFDIS_PAD_CTRL_8822B BIT(15)\n#define BIT_NFC_CLK_PAD_CTRL_8822B BIT(14)\n#define BIT_NFC_DATA_PAD_CTRL_8822B BIT(13)\n#define BIT_NFC_PAD_PULL_CTRL_8822B BIT(12)\n\n#define BIT_SHIFT_NFCPAD_IO_SEL_8822B 8\n#define BIT_MASK_NFCPAD_IO_SEL_8822B 0xf\n#define BIT_NFCPAD_IO_SEL_8822B(x)                                             \\\n\t(((x) & BIT_MASK_NFCPAD_IO_SEL_8822B) << BIT_SHIFT_NFCPAD_IO_SEL_8822B)\n#define BITS_NFCPAD_IO_SEL_8822B                                               \\\n\t(BIT_MASK_NFCPAD_IO_SEL_8822B << BIT_SHIFT_NFCPAD_IO_SEL_8822B)\n#define BIT_CLEAR_NFCPAD_IO_SEL_8822B(x) ((x) & (~BITS_NFCPAD_IO_SEL_8822B))\n#define BIT_GET_NFCPAD_IO_SEL_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8822B) & BIT_MASK_NFCPAD_IO_SEL_8822B)\n#define BIT_SET_NFCPAD_IO_SEL_8822B(x, v)                                      \\\n\t(BIT_CLEAR_NFCPAD_IO_SEL_8822B(x) | BIT_NFCPAD_IO_SEL_8822B(v))\n\n#define BIT_SHIFT_NFCPAD_OUT_8822B 4\n#define BIT_MASK_NFCPAD_OUT_8822B 0xf\n#define BIT_NFCPAD_OUT_8822B(x)                                                \\\n\t(((x) & BIT_MASK_NFCPAD_OUT_8822B) << BIT_SHIFT_NFCPAD_OUT_8822B)\n#define BITS_NFCPAD_OUT_8822B                                                  \\\n\t(BIT_MASK_NFCPAD_OUT_8822B << BIT_SHIFT_NFCPAD_OUT_8822B)\n#define BIT_CLEAR_NFCPAD_OUT_8822B(x) ((x) & (~BITS_NFCPAD_OUT_8822B))\n#define BIT_GET_NFCPAD_OUT_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_NFCPAD_OUT_8822B) & BIT_MASK_NFCPAD_OUT_8822B)\n#define BIT_SET_NFCPAD_OUT_8822B(x, v)                                         \\\n\t(BIT_CLEAR_NFCPAD_OUT_8822B(x) | BIT_NFCPAD_OUT_8822B(v))\n\n#define BIT_SHIFT_NFCPAD_IN_8822B 0\n#define BIT_MASK_NFCPAD_IN_8822B 0xf\n#define BIT_NFCPAD_IN_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_NFCPAD_IN_8822B) << BIT_SHIFT_NFCPAD_IN_8822B)\n#define BITS_NFCPAD_IN_8822B                                                   \\\n\t(BIT_MASK_NFCPAD_IN_8822B << BIT_SHIFT_NFCPAD_IN_8822B)\n#define BIT_CLEAR_NFCPAD_IN_8822B(x) ((x) & (~BITS_NFCPAD_IN_8822B))\n#define BIT_GET_NFCPAD_IN_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_NFCPAD_IN_8822B) & BIT_MASK_NFCPAD_IN_8822B)\n#define BIT_SET_NFCPAD_IN_8822B(x, v)                                          \\\n\t(BIT_CLEAR_NFCPAD_IN_8822B(x) | BIT_NFCPAD_IN_8822B(v))\n\n/* 2 REG_HIMR2_8822B */\n#define BIT_BCNDMAINT_P4_MSK_8822B BIT(31)\n#define BIT_BCNDMAINT_P3_MSK_8822B BIT(30)\n#define BIT_BCNDMAINT_P2_MSK_8822B BIT(29)\n#define BIT_BCNDMAINT_P1_MSK_8822B BIT(28)\n#define BIT_ATIMEND7_MSK_8822B BIT(22)\n#define BIT_ATIMEND6_MSK_8822B BIT(21)\n#define BIT_ATIMEND5_MSK_8822B BIT(20)\n#define BIT_ATIMEND4_MSK_8822B BIT(19)\n#define BIT_ATIMEND3_MSK_8822B BIT(18)\n#define BIT_ATIMEND2_MSK_8822B BIT(17)\n#define BIT_ATIMEND1_MSK_8822B BIT(16)\n#define BIT_TXBCN7OK_MSK_8822B BIT(14)\n#define BIT_TXBCN6OK_MSK_8822B BIT(13)\n#define BIT_TXBCN5OK_MSK_8822B BIT(12)\n#define BIT_TXBCN4OK_MSK_8822B BIT(11)\n#define BIT_TXBCN3OK_MSK_8822B BIT(10)\n#define BIT_TXBCN2OK_MSK_8822B BIT(9)\n#define BIT_TXBCN1OK_MSK_V1_8822B BIT(8)\n#define BIT_TXBCN7ERR_MSK_8822B BIT(6)\n#define BIT_TXBCN6ERR_MSK_8822B BIT(5)\n#define BIT_TXBCN5ERR_MSK_8822B BIT(4)\n#define BIT_TXBCN4ERR_MSK_8822B BIT(3)\n#define BIT_TXBCN3ERR_MSK_8822B BIT(2)\n#define BIT_TXBCN2ERR_MSK_8822B BIT(1)\n#define BIT_TXBCN1ERR_MSK_V1_8822B BIT(0)\n\n/* 2 REG_HISR2_8822B */\n#define BIT_BCNDMAINT_P4_8822B BIT(31)\n#define BIT_BCNDMAINT_P3_8822B BIT(30)\n#define BIT_BCNDMAINT_P2_8822B BIT(29)\n#define BIT_BCNDMAINT_P1_8822B BIT(28)\n#define BIT_ATIMEND7_8822B BIT(22)\n#define BIT_ATIMEND6_8822B BIT(21)\n#define BIT_ATIMEND5_8822B BIT(20)\n#define BIT_ATIMEND4_8822B BIT(19)\n#define BIT_ATIMEND3_8822B BIT(18)\n#define BIT_ATIMEND2_8822B BIT(17)\n#define BIT_ATIMEND1_8822B BIT(16)\n#define BIT_TXBCN7OK_8822B BIT(14)\n#define BIT_TXBCN6OK_8822B BIT(13)\n#define BIT_TXBCN5OK_8822B BIT(12)\n#define BIT_TXBCN4OK_8822B BIT(11)\n#define BIT_TXBCN3OK_8822B BIT(10)\n#define BIT_TXBCN2OK_8822B BIT(9)\n#define BIT_TXBCN1OK_8822B BIT(8)\n#define BIT_TXBCN7ERR_8822B BIT(6)\n#define BIT_TXBCN6ERR_8822B BIT(5)\n#define BIT_TXBCN5ERR_8822B BIT(4)\n#define BIT_TXBCN4ERR_8822B BIT(3)\n#define BIT_TXBCN3ERR_8822B BIT(2)\n#define BIT_TXBCN2ERR_8822B BIT(1)\n#define BIT_TXBCN1ERR_8822B BIT(0)\n\n/* 2 REG_HIMR3_8822B */\n#define BIT_WDT_PLATFORM_INT_MSK_8822B BIT(18)\n#define BIT_WDT_CPU_INT_MSK_8822B BIT(17)\n#define BIT_SETH2CDOK_MASK_8822B BIT(16)\n#define BIT_H2C_CMD_FULL_MASK_8822B BIT(15)\n#define BIT_PWR_INT_127_MASK_8822B BIT(14)\n#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8822B BIT(13)\n#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8822B BIT(12)\n#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8822B BIT(11)\n#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8822B BIT(10)\n#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8822B BIT(9)\n#define BIT_PWR_INT_127_MASK_V1_8822B BIT(8)\n#define BIT_PWR_INT_126TO96_MASK_8822B BIT(7)\n#define BIT_PWR_INT_95TO64_MASK_8822B BIT(6)\n#define BIT_PWR_INT_63TO32_MASK_8822B BIT(5)\n#define BIT_PWR_INT_31TO0_MASK_8822B BIT(4)\n#define BIT_DDMA0_LP_INT_MSK_8822B BIT(1)\n#define BIT_DDMA0_HP_INT_MSK_8822B BIT(0)\n\n/* 2 REG_HISR3_8822B */\n#define BIT_WDT_PLATFORM_INT_8822B BIT(18)\n#define BIT_WDT_CPU_INT_8822B BIT(17)\n#define BIT_SETH2CDOK_8822B BIT(16)\n#define BIT_H2C_CMD_FULL_8822B BIT(15)\n#define BIT_PWR_INT_127_8822B BIT(14)\n#define BIT_TXSHORTCUT_TXDESUPDATEOK_8822B BIT(13)\n#define BIT_TXSHORTCUT_BKUPDATEOK_8822B BIT(12)\n#define BIT_TXSHORTCUT_BEUPDATEOK_8822B BIT(11)\n#define BIT_TXSHORTCUT_VIUPDATEOK_8822B BIT(10)\n#define BIT_TXSHORTCUT_VOUPDATEOK_8822B BIT(9)\n#define BIT_PWR_INT_127_V1_8822B BIT(8)\n#define BIT_PWR_INT_126TO96_8822B BIT(7)\n#define BIT_PWR_INT_95TO64_8822B BIT(6)\n#define BIT_PWR_INT_63TO32_8822B BIT(5)\n#define BIT_PWR_INT_31TO0_8822B BIT(4)\n#define BIT_DDMA0_LP_INT_8822B BIT(1)\n#define BIT_DDMA0_HP_INT_8822B BIT(0)\n\n/* 2 REG_SW_MDIO_8822B */\n#define BIT_DIS_TIMEOUT_IO_8822B BIT(24)\n\n/* 2 REG_SW_FLUSH_8822B */\n#define BIT_FLUSH_HOLDN_EN_8822B BIT(25)\n#define BIT_FLUSH_WR_EN_8822B BIT(24)\n#define BIT_SW_FLASH_CONTROL_8822B BIT(23)\n#define BIT_SW_FLASH_WEN_E_8822B BIT(19)\n#define BIT_SW_FLASH_HOLDN_E_8822B BIT(18)\n#define BIT_SW_FLASH_SO_E_8822B BIT(17)\n#define BIT_SW_FLASH_SI_E_8822B BIT(16)\n#define BIT_SW_FLASH_SK_O_8822B BIT(13)\n#define BIT_SW_FLASH_CEN_O_8822B BIT(12)\n#define BIT_SW_FLASH_WEN_O_8822B BIT(11)\n#define BIT_SW_FLASH_HOLDN_O_8822B BIT(10)\n#define BIT_SW_FLASH_SO_O_8822B BIT(9)\n#define BIT_SW_FLASH_SI_O_8822B BIT(8)\n#define BIT_SW_FLASH_WEN_I_8822B BIT(3)\n#define BIT_SW_FLASH_HOLDN_I_8822B BIT(2)\n#define BIT_SW_FLASH_SO_I_8822B BIT(1)\n#define BIT_SW_FLASH_SI_I_8822B BIT(0)\n\n/* 2 REG_H2C_PKT_READADDR_8822B */\n\n#define BIT_SHIFT_H2C_PKT_READADDR_8822B 0\n#define BIT_MASK_H2C_PKT_READADDR_8822B 0x3ffff\n#define BIT_H2C_PKT_READADDR_8822B(x)                                          \\\n\t(((x) & BIT_MASK_H2C_PKT_READADDR_8822B)                               \\\n\t << BIT_SHIFT_H2C_PKT_READADDR_8822B)\n#define BITS_H2C_PKT_READADDR_8822B                                            \\\n\t(BIT_MASK_H2C_PKT_READADDR_8822B << BIT_SHIFT_H2C_PKT_READADDR_8822B)\n#define BIT_CLEAR_H2C_PKT_READADDR_8822B(x)                                    \\\n\t((x) & (~BITS_H2C_PKT_READADDR_8822B))\n#define BIT_GET_H2C_PKT_READADDR_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_H2C_PKT_READADDR_8822B) &                           \\\n\t BIT_MASK_H2C_PKT_READADDR_8822B)\n#define BIT_SET_H2C_PKT_READADDR_8822B(x, v)                                   \\\n\t(BIT_CLEAR_H2C_PKT_READADDR_8822B(x) | BIT_H2C_PKT_READADDR_8822B(v))\n\n/* 2 REG_H2C_PKT_WRITEADDR_8822B */\n\n#define BIT_SHIFT_H2C_PKT_WRITEADDR_8822B 0\n#define BIT_MASK_H2C_PKT_WRITEADDR_8822B 0x3ffff\n#define BIT_H2C_PKT_WRITEADDR_8822B(x)                                         \\\n\t(((x) & BIT_MASK_H2C_PKT_WRITEADDR_8822B)                              \\\n\t << BIT_SHIFT_H2C_PKT_WRITEADDR_8822B)\n#define BITS_H2C_PKT_WRITEADDR_8822B                                           \\\n\t(BIT_MASK_H2C_PKT_WRITEADDR_8822B << BIT_SHIFT_H2C_PKT_WRITEADDR_8822B)\n#define BIT_CLEAR_H2C_PKT_WRITEADDR_8822B(x)                                   \\\n\t((x) & (~BITS_H2C_PKT_WRITEADDR_8822B))\n#define BIT_GET_H2C_PKT_WRITEADDR_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8822B) &                          \\\n\t BIT_MASK_H2C_PKT_WRITEADDR_8822B)\n#define BIT_SET_H2C_PKT_WRITEADDR_8822B(x, v)                                  \\\n\t(BIT_CLEAR_H2C_PKT_WRITEADDR_8822B(x) | BIT_H2C_PKT_WRITEADDR_8822B(v))\n\n/* 2 REG_MEM_PWR_CRTL_8822B */\n#define BIT_MEM_BB_SD_8822B BIT(17)\n#define BIT_MEM_BB_DS_8822B BIT(16)\n#define BIT_MEM_BT_DS_8822B BIT(10)\n#define BIT_MEM_SDIO_LS_8822B BIT(9)\n#define BIT_MEM_SDIO_DS_8822B BIT(8)\n#define BIT_MEM_USB_LS_8822B BIT(7)\n#define BIT_MEM_USB_DS_8822B BIT(6)\n#define BIT_MEM_PCI_LS_8822B BIT(5)\n#define BIT_MEM_PCI_DS_8822B BIT(4)\n#define BIT_MEM_WLMAC_LS_8822B BIT(3)\n#define BIT_MEM_WLMAC_DS_8822B BIT(2)\n#define BIT_MEM_WLMCU_LS_8822B BIT(1)\n#define BIT_MEM_WLMCU_DS_8822B BIT(0)\n\n/* 2 REG_FW_DBG0_8822B */\n\n#define BIT_SHIFT_FW_DBG0_8822B 0\n#define BIT_MASK_FW_DBG0_8822B 0xffffffffL\n#define BIT_FW_DBG0_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG0_8822B) << BIT_SHIFT_FW_DBG0_8822B)\n#define BITS_FW_DBG0_8822B (BIT_MASK_FW_DBG0_8822B << BIT_SHIFT_FW_DBG0_8822B)\n#define BIT_CLEAR_FW_DBG0_8822B(x) ((x) & (~BITS_FW_DBG0_8822B))\n#define BIT_GET_FW_DBG0_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG0_8822B) & BIT_MASK_FW_DBG0_8822B)\n#define BIT_SET_FW_DBG0_8822B(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG0_8822B(x) | BIT_FW_DBG0_8822B(v))\n\n/* 2 REG_FW_DBG1_8822B */\n\n#define BIT_SHIFT_FW_DBG1_8822B 0\n#define BIT_MASK_FW_DBG1_8822B 0xffffffffL\n#define BIT_FW_DBG1_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG1_8822B) << BIT_SHIFT_FW_DBG1_8822B)\n#define BITS_FW_DBG1_8822B (BIT_MASK_FW_DBG1_8822B << BIT_SHIFT_FW_DBG1_8822B)\n#define BIT_CLEAR_FW_DBG1_8822B(x) ((x) & (~BITS_FW_DBG1_8822B))\n#define BIT_GET_FW_DBG1_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG1_8822B) & BIT_MASK_FW_DBG1_8822B)\n#define BIT_SET_FW_DBG1_8822B(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG1_8822B(x) | BIT_FW_DBG1_8822B(v))\n\n/* 2 REG_FW_DBG2_8822B */\n\n#define BIT_SHIFT_FW_DBG2_8822B 0\n#define BIT_MASK_FW_DBG2_8822B 0xffffffffL\n#define BIT_FW_DBG2_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG2_8822B) << BIT_SHIFT_FW_DBG2_8822B)\n#define BITS_FW_DBG2_8822B (BIT_MASK_FW_DBG2_8822B << BIT_SHIFT_FW_DBG2_8822B)\n#define BIT_CLEAR_FW_DBG2_8822B(x) ((x) & (~BITS_FW_DBG2_8822B))\n#define BIT_GET_FW_DBG2_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG2_8822B) & BIT_MASK_FW_DBG2_8822B)\n#define BIT_SET_FW_DBG2_8822B(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG2_8822B(x) | BIT_FW_DBG2_8822B(v))\n\n/* 2 REG_FW_DBG3_8822B */\n\n#define BIT_SHIFT_FW_DBG3_8822B 0\n#define BIT_MASK_FW_DBG3_8822B 0xffffffffL\n#define BIT_FW_DBG3_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG3_8822B) << BIT_SHIFT_FW_DBG3_8822B)\n#define BITS_FW_DBG3_8822B (BIT_MASK_FW_DBG3_8822B << BIT_SHIFT_FW_DBG3_8822B)\n#define BIT_CLEAR_FW_DBG3_8822B(x) ((x) & (~BITS_FW_DBG3_8822B))\n#define BIT_GET_FW_DBG3_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG3_8822B) & BIT_MASK_FW_DBG3_8822B)\n#define BIT_SET_FW_DBG3_8822B(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG3_8822B(x) | BIT_FW_DBG3_8822B(v))\n\n/* 2 REG_FW_DBG4_8822B */\n\n#define BIT_SHIFT_FW_DBG4_8822B 0\n#define BIT_MASK_FW_DBG4_8822B 0xffffffffL\n#define BIT_FW_DBG4_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG4_8822B) << BIT_SHIFT_FW_DBG4_8822B)\n#define BITS_FW_DBG4_8822B (BIT_MASK_FW_DBG4_8822B << BIT_SHIFT_FW_DBG4_8822B)\n#define BIT_CLEAR_FW_DBG4_8822B(x) ((x) & (~BITS_FW_DBG4_8822B))\n#define BIT_GET_FW_DBG4_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG4_8822B) & BIT_MASK_FW_DBG4_8822B)\n#define BIT_SET_FW_DBG4_8822B(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG4_8822B(x) | BIT_FW_DBG4_8822B(v))\n\n/* 2 REG_FW_DBG5_8822B */\n\n#define BIT_SHIFT_FW_DBG5_8822B 0\n#define BIT_MASK_FW_DBG5_8822B 0xffffffffL\n#define BIT_FW_DBG5_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG5_8822B) << BIT_SHIFT_FW_DBG5_8822B)\n#define BITS_FW_DBG5_8822B (BIT_MASK_FW_DBG5_8822B << BIT_SHIFT_FW_DBG5_8822B)\n#define BIT_CLEAR_FW_DBG5_8822B(x) ((x) & (~BITS_FW_DBG5_8822B))\n#define BIT_GET_FW_DBG5_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG5_8822B) & BIT_MASK_FW_DBG5_8822B)\n#define BIT_SET_FW_DBG5_8822B(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG5_8822B(x) | BIT_FW_DBG5_8822B(v))\n\n/* 2 REG_FW_DBG6_8822B */\n\n#define BIT_SHIFT_FW_DBG6_8822B 0\n#define BIT_MASK_FW_DBG6_8822B 0xffffffffL\n#define BIT_FW_DBG6_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG6_8822B) << BIT_SHIFT_FW_DBG6_8822B)\n#define BITS_FW_DBG6_8822B (BIT_MASK_FW_DBG6_8822B << BIT_SHIFT_FW_DBG6_8822B)\n#define BIT_CLEAR_FW_DBG6_8822B(x) ((x) & (~BITS_FW_DBG6_8822B))\n#define BIT_GET_FW_DBG6_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG6_8822B) & BIT_MASK_FW_DBG6_8822B)\n#define BIT_SET_FW_DBG6_8822B(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG6_8822B(x) | BIT_FW_DBG6_8822B(v))\n\n/* 2 REG_FW_DBG7_8822B */\n\n#define BIT_SHIFT_FW_DBG7_8822B 0\n#define BIT_MASK_FW_DBG7_8822B 0xffffffffL\n#define BIT_FW_DBG7_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG7_8822B) << BIT_SHIFT_FW_DBG7_8822B)\n#define BITS_FW_DBG7_8822B (BIT_MASK_FW_DBG7_8822B << BIT_SHIFT_FW_DBG7_8822B)\n#define BIT_CLEAR_FW_DBG7_8822B(x) ((x) & (~BITS_FW_DBG7_8822B))\n#define BIT_GET_FW_DBG7_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG7_8822B) & BIT_MASK_FW_DBG7_8822B)\n#define BIT_SET_FW_DBG7_8822B(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG7_8822B(x) | BIT_FW_DBG7_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_CR_8822B */\n\n#define BIT_SHIFT_LBMODE_8822B 24\n#define BIT_MASK_LBMODE_8822B 0x1f\n#define BIT_LBMODE_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_LBMODE_8822B) << BIT_SHIFT_LBMODE_8822B)\n#define BITS_LBMODE_8822B (BIT_MASK_LBMODE_8822B << BIT_SHIFT_LBMODE_8822B)\n#define BIT_CLEAR_LBMODE_8822B(x) ((x) & (~BITS_LBMODE_8822B))\n#define BIT_GET_LBMODE_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_LBMODE_8822B) & BIT_MASK_LBMODE_8822B)\n#define BIT_SET_LBMODE_8822B(x, v)                                             \\\n\t(BIT_CLEAR_LBMODE_8822B(x) | BIT_LBMODE_8822B(v))\n\n#define BIT_SHIFT_NETYPE1_8822B 18\n#define BIT_MASK_NETYPE1_8822B 0x3\n#define BIT_NETYPE1_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE1_8822B) << BIT_SHIFT_NETYPE1_8822B)\n#define BITS_NETYPE1_8822B (BIT_MASK_NETYPE1_8822B << BIT_SHIFT_NETYPE1_8822B)\n#define BIT_CLEAR_NETYPE1_8822B(x) ((x) & (~BITS_NETYPE1_8822B))\n#define BIT_GET_NETYPE1_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE1_8822B) & BIT_MASK_NETYPE1_8822B)\n#define BIT_SET_NETYPE1_8822B(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE1_8822B(x) | BIT_NETYPE1_8822B(v))\n\n#define BIT_SHIFT_NETYPE0_8822B 16\n#define BIT_MASK_NETYPE0_8822B 0x3\n#define BIT_NETYPE0_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE0_8822B) << BIT_SHIFT_NETYPE0_8822B)\n#define BITS_NETYPE0_8822B (BIT_MASK_NETYPE0_8822B << BIT_SHIFT_NETYPE0_8822B)\n#define BIT_CLEAR_NETYPE0_8822B(x) ((x) & (~BITS_NETYPE0_8822B))\n#define BIT_GET_NETYPE0_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE0_8822B) & BIT_MASK_NETYPE0_8822B)\n#define BIT_SET_NETYPE0_8822B(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE0_8822B(x) | BIT_NETYPE0_8822B(v))\n\n#define BIT_I2C_MAILBOX_EN_8822B BIT(12)\n#define BIT_SHCUT_EN_8822B BIT(11)\n#define BIT_32K_CAL_TMR_EN_8822B BIT(10)\n#define BIT_MAC_SEC_EN_8822B BIT(9)\n#define BIT_ENSWBCN_8822B BIT(8)\n#define BIT_MACRXEN_8822B BIT(7)\n#define BIT_MACTXEN_8822B BIT(6)\n#define BIT_SCHEDULE_EN_8822B BIT(5)\n#define BIT_PROTOCOL_EN_8822B BIT(4)\n#define BIT_RXDMA_EN_8822B BIT(3)\n#define BIT_TXDMA_EN_8822B BIT(2)\n#define BIT_HCI_RXDMA_EN_8822B BIT(1)\n#define BIT_HCI_TXDMA_EN_8822B BIT(0)\n\n/* 2 REG_TSF_CLK_STATE_8822B */\n#define BIT_TSF_CLK_STABLE_8822B BIT(15)\n\n/* 2 REG_TXDMA_PQ_MAP_8822B */\n\n#define BIT_SHIFT_TXDMA_HIQ_MAP_8822B 14\n#define BIT_MASK_TXDMA_HIQ_MAP_8822B 0x3\n#define BIT_TXDMA_HIQ_MAP_8822B(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_HIQ_MAP_8822B) << BIT_SHIFT_TXDMA_HIQ_MAP_8822B)\n#define BITS_TXDMA_HIQ_MAP_8822B                                               \\\n\t(BIT_MASK_TXDMA_HIQ_MAP_8822B << BIT_SHIFT_TXDMA_HIQ_MAP_8822B)\n#define BIT_CLEAR_TXDMA_HIQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8822B))\n#define BIT_GET_TXDMA_HIQ_MAP_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8822B) & BIT_MASK_TXDMA_HIQ_MAP_8822B)\n#define BIT_SET_TXDMA_HIQ_MAP_8822B(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_HIQ_MAP_8822B(x) | BIT_TXDMA_HIQ_MAP_8822B(v))\n\n#define BIT_SHIFT_TXDMA_MGQ_MAP_8822B 12\n#define BIT_MASK_TXDMA_MGQ_MAP_8822B 0x3\n#define BIT_TXDMA_MGQ_MAP_8822B(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_MGQ_MAP_8822B) << BIT_SHIFT_TXDMA_MGQ_MAP_8822B)\n#define BITS_TXDMA_MGQ_MAP_8822B                                               \\\n\t(BIT_MASK_TXDMA_MGQ_MAP_8822B << BIT_SHIFT_TXDMA_MGQ_MAP_8822B)\n#define BIT_CLEAR_TXDMA_MGQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8822B))\n#define BIT_GET_TXDMA_MGQ_MAP_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8822B) & BIT_MASK_TXDMA_MGQ_MAP_8822B)\n#define BIT_SET_TXDMA_MGQ_MAP_8822B(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_MGQ_MAP_8822B(x) | BIT_TXDMA_MGQ_MAP_8822B(v))\n\n#define BIT_SHIFT_TXDMA_BKQ_MAP_8822B 10\n#define BIT_MASK_TXDMA_BKQ_MAP_8822B 0x3\n#define BIT_TXDMA_BKQ_MAP_8822B(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_BKQ_MAP_8822B) << BIT_SHIFT_TXDMA_BKQ_MAP_8822B)\n#define BITS_TXDMA_BKQ_MAP_8822B                                               \\\n\t(BIT_MASK_TXDMA_BKQ_MAP_8822B << BIT_SHIFT_TXDMA_BKQ_MAP_8822B)\n#define BIT_CLEAR_TXDMA_BKQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8822B))\n#define BIT_GET_TXDMA_BKQ_MAP_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8822B) & BIT_MASK_TXDMA_BKQ_MAP_8822B)\n#define BIT_SET_TXDMA_BKQ_MAP_8822B(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_BKQ_MAP_8822B(x) | BIT_TXDMA_BKQ_MAP_8822B(v))\n\n#define BIT_SHIFT_TXDMA_BEQ_MAP_8822B 8\n#define BIT_MASK_TXDMA_BEQ_MAP_8822B 0x3\n#define BIT_TXDMA_BEQ_MAP_8822B(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_BEQ_MAP_8822B) << BIT_SHIFT_TXDMA_BEQ_MAP_8822B)\n#define BITS_TXDMA_BEQ_MAP_8822B                                               \\\n\t(BIT_MASK_TXDMA_BEQ_MAP_8822B << BIT_SHIFT_TXDMA_BEQ_MAP_8822B)\n#define BIT_CLEAR_TXDMA_BEQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8822B))\n#define BIT_GET_TXDMA_BEQ_MAP_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8822B) & BIT_MASK_TXDMA_BEQ_MAP_8822B)\n#define BIT_SET_TXDMA_BEQ_MAP_8822B(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_BEQ_MAP_8822B(x) | BIT_TXDMA_BEQ_MAP_8822B(v))\n\n#define BIT_SHIFT_TXDMA_VIQ_MAP_8822B 6\n#define BIT_MASK_TXDMA_VIQ_MAP_8822B 0x3\n#define BIT_TXDMA_VIQ_MAP_8822B(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_VIQ_MAP_8822B) << BIT_SHIFT_TXDMA_VIQ_MAP_8822B)\n#define BITS_TXDMA_VIQ_MAP_8822B                                               \\\n\t(BIT_MASK_TXDMA_VIQ_MAP_8822B << BIT_SHIFT_TXDMA_VIQ_MAP_8822B)\n#define BIT_CLEAR_TXDMA_VIQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8822B))\n#define BIT_GET_TXDMA_VIQ_MAP_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8822B) & BIT_MASK_TXDMA_VIQ_MAP_8822B)\n#define BIT_SET_TXDMA_VIQ_MAP_8822B(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_VIQ_MAP_8822B(x) | BIT_TXDMA_VIQ_MAP_8822B(v))\n\n#define BIT_SHIFT_TXDMA_VOQ_MAP_8822B 4\n#define BIT_MASK_TXDMA_VOQ_MAP_8822B 0x3\n#define BIT_TXDMA_VOQ_MAP_8822B(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_VOQ_MAP_8822B) << BIT_SHIFT_TXDMA_VOQ_MAP_8822B)\n#define BITS_TXDMA_VOQ_MAP_8822B                                               \\\n\t(BIT_MASK_TXDMA_VOQ_MAP_8822B << BIT_SHIFT_TXDMA_VOQ_MAP_8822B)\n#define BIT_CLEAR_TXDMA_VOQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8822B))\n#define BIT_GET_TXDMA_VOQ_MAP_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8822B) & BIT_MASK_TXDMA_VOQ_MAP_8822B)\n#define BIT_SET_TXDMA_VOQ_MAP_8822B(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_VOQ_MAP_8822B(x) | BIT_TXDMA_VOQ_MAP_8822B(v))\n\n#define BIT_RXDMA_AGG_EN_8822B BIT(2)\n#define BIT_RXSHFT_EN_8822B BIT(1)\n#define BIT_RXDMA_ARBBW_EN_8822B BIT(0)\n\n/* 2 REG_TRXFF_BNDY_8822B */\n\n#define BIT_SHIFT_RXFFOVFL_RSV_V2_8822B 8\n#define BIT_MASK_RXFFOVFL_RSV_V2_8822B 0xf\n#define BIT_RXFFOVFL_RSV_V2_8822B(x)                                           \\\n\t(((x) & BIT_MASK_RXFFOVFL_RSV_V2_8822B)                                \\\n\t << BIT_SHIFT_RXFFOVFL_RSV_V2_8822B)\n#define BITS_RXFFOVFL_RSV_V2_8822B                                             \\\n\t(BIT_MASK_RXFFOVFL_RSV_V2_8822B << BIT_SHIFT_RXFFOVFL_RSV_V2_8822B)\n#define BIT_CLEAR_RXFFOVFL_RSV_V2_8822B(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8822B))\n#define BIT_GET_RXFFOVFL_RSV_V2_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8822B) &                            \\\n\t BIT_MASK_RXFFOVFL_RSV_V2_8822B)\n#define BIT_SET_RXFFOVFL_RSV_V2_8822B(x, v)                                    \\\n\t(BIT_CLEAR_RXFFOVFL_RSV_V2_8822B(x) | BIT_RXFFOVFL_RSV_V2_8822B(v))\n\n#define BIT_SHIFT_TXPKTBUF_PGBNDY_8822B 0\n#define BIT_MASK_TXPKTBUF_PGBNDY_8822B 0xff\n#define BIT_TXPKTBUF_PGBNDY_8822B(x)                                           \\\n\t(((x) & BIT_MASK_TXPKTBUF_PGBNDY_8822B)                                \\\n\t << BIT_SHIFT_TXPKTBUF_PGBNDY_8822B)\n#define BITS_TXPKTBUF_PGBNDY_8822B                                             \\\n\t(BIT_MASK_TXPKTBUF_PGBNDY_8822B << BIT_SHIFT_TXPKTBUF_PGBNDY_8822B)\n#define BIT_CLEAR_TXPKTBUF_PGBNDY_8822B(x) ((x) & (~BITS_TXPKTBUF_PGBNDY_8822B))\n#define BIT_GET_TXPKTBUF_PGBNDY_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8822B) &                            \\\n\t BIT_MASK_TXPKTBUF_PGBNDY_8822B)\n#define BIT_SET_TXPKTBUF_PGBNDY_8822B(x, v)                                    \\\n\t(BIT_CLEAR_TXPKTBUF_PGBNDY_8822B(x) | BIT_TXPKTBUF_PGBNDY_8822B(v))\n\n/* 2 REG_PTA_I2C_MBOX_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n#define BIT_SHIFT_I2C_M_STATUS_8822B 8\n#define BIT_MASK_I2C_M_STATUS_8822B 0xf\n#define BIT_I2C_M_STATUS_8822B(x)                                              \\\n\t(((x) & BIT_MASK_I2C_M_STATUS_8822B) << BIT_SHIFT_I2C_M_STATUS_8822B)\n#define BITS_I2C_M_STATUS_8822B                                                \\\n\t(BIT_MASK_I2C_M_STATUS_8822B << BIT_SHIFT_I2C_M_STATUS_8822B)\n#define BIT_CLEAR_I2C_M_STATUS_8822B(x) ((x) & (~BITS_I2C_M_STATUS_8822B))\n#define BIT_GET_I2C_M_STATUS_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_I2C_M_STATUS_8822B) & BIT_MASK_I2C_M_STATUS_8822B)\n#define BIT_SET_I2C_M_STATUS_8822B(x, v)                                       \\\n\t(BIT_CLEAR_I2C_M_STATUS_8822B(x) | BIT_I2C_M_STATUS_8822B(v))\n\n#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B 4\n#define BIT_MASK_I2C_M_BUS_GNT_FW_8822B 0x7\n#define BIT_I2C_M_BUS_GNT_FW_8822B(x)                                          \\\n\t(((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8822B)                               \\\n\t << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B)\n#define BITS_I2C_M_BUS_GNT_FW_8822B                                            \\\n\t(BIT_MASK_I2C_M_BUS_GNT_FW_8822B << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B)\n#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8822B(x)                                    \\\n\t((x) & (~BITS_I2C_M_BUS_GNT_FW_8822B))\n#define BIT_GET_I2C_M_BUS_GNT_FW_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B) &                           \\\n\t BIT_MASK_I2C_M_BUS_GNT_FW_8822B)\n#define BIT_SET_I2C_M_BUS_GNT_FW_8822B(x, v)                                   \\\n\t(BIT_CLEAR_I2C_M_BUS_GNT_FW_8822B(x) | BIT_I2C_M_BUS_GNT_FW_8822B(v))\n\n#define BIT_I2C_M_GNT_FW_8822B BIT(3)\n\n#define BIT_SHIFT_I2C_M_SPEED_8822B 1\n#define BIT_MASK_I2C_M_SPEED_8822B 0x3\n#define BIT_I2C_M_SPEED_8822B(x)                                               \\\n\t(((x) & BIT_MASK_I2C_M_SPEED_8822B) << BIT_SHIFT_I2C_M_SPEED_8822B)\n#define BITS_I2C_M_SPEED_8822B                                                 \\\n\t(BIT_MASK_I2C_M_SPEED_8822B << BIT_SHIFT_I2C_M_SPEED_8822B)\n#define BIT_CLEAR_I2C_M_SPEED_8822B(x) ((x) & (~BITS_I2C_M_SPEED_8822B))\n#define BIT_GET_I2C_M_SPEED_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_I2C_M_SPEED_8822B) & BIT_MASK_I2C_M_SPEED_8822B)\n#define BIT_SET_I2C_M_SPEED_8822B(x, v)                                        \\\n\t(BIT_CLEAR_I2C_M_SPEED_8822B(x) | BIT_I2C_M_SPEED_8822B(v))\n\n#define BIT_I2C_M_UNLOCK_8822B BIT(0)\n\n/* 2 REG_RXFF_BNDY_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n#define BIT_SHIFT_RXFF0_BNDY_V2_8822B 0\n#define BIT_MASK_RXFF0_BNDY_V2_8822B 0x3ffff\n#define BIT_RXFF0_BNDY_V2_8822B(x)                                             \\\n\t(((x) & BIT_MASK_RXFF0_BNDY_V2_8822B) << BIT_SHIFT_RXFF0_BNDY_V2_8822B)\n#define BITS_RXFF0_BNDY_V2_8822B                                               \\\n\t(BIT_MASK_RXFF0_BNDY_V2_8822B << BIT_SHIFT_RXFF0_BNDY_V2_8822B)\n#define BIT_CLEAR_RXFF0_BNDY_V2_8822B(x) ((x) & (~BITS_RXFF0_BNDY_V2_8822B))\n#define BIT_GET_RXFF0_BNDY_V2_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8822B) & BIT_MASK_RXFF0_BNDY_V2_8822B)\n#define BIT_SET_RXFF0_BNDY_V2_8822B(x, v)                                      \\\n\t(BIT_CLEAR_RXFF0_BNDY_V2_8822B(x) | BIT_RXFF0_BNDY_V2_8822B(v))\n\n/* 2 REG_FE1IMR_8822B */\n#define BIT_FS_RXDMA2_DONE_INT_EN_8822B BIT(28)\n#define BIT_FS_RXDONE3_INT_EN_8822B BIT(27)\n#define BIT_FS_RXDONE2_INT_EN_8822B BIT(26)\n#define BIT_FS_RX_BCN_P4_INT_EN_8822B BIT(25)\n#define BIT_FS_RX_BCN_P3_INT_EN_8822B BIT(24)\n#define BIT_FS_RX_BCN_P2_INT_EN_8822B BIT(23)\n#define BIT_FS_RX_BCN_P1_INT_EN_8822B BIT(22)\n#define BIT_FS_RX_BCN_P0_INT_EN_8822B BIT(21)\n#define BIT_FS_RX_UMD0_INT_EN_8822B BIT(20)\n#define BIT_FS_RX_UMD1_INT_EN_8822B BIT(19)\n#define BIT_FS_RX_BMD0_INT_EN_8822B BIT(18)\n#define BIT_FS_RX_BMD1_INT_EN_8822B BIT(17)\n#define BIT_FS_RXDONE_INT_EN_8822B BIT(16)\n#define BIT_FS_WWLAN_INT_EN_8822B BIT(15)\n#define BIT_FS_SOUND_DONE_INT_EN_8822B BIT(14)\n#define BIT_FS_LP_STBY_INT_EN_8822B BIT(13)\n#define BIT_FS_TRL_MTR_INT_EN_8822B BIT(12)\n#define BIT_FS_BF1_PRETO_INT_EN_8822B BIT(11)\n#define BIT_FS_BF0_PRETO_INT_EN_8822B BIT(10)\n#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8822B BIT(9)\n#define BIT_FS_LTE_COEX_EN_8822B BIT(6)\n#define BIT_FS_WLACTOFF_INT_EN_8822B BIT(5)\n#define BIT_FS_WLACTON_INT_EN_8822B BIT(4)\n#define BIT_FS_BTCMD_INT_EN_8822B BIT(3)\n#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8822B BIT(2)\n#define BIT_FS_TRPC_TO_INT_EN_V1_8822B BIT(1)\n#define BIT_FS_RPC_O_T_INT_EN_V1_8822B BIT(0)\n\n/* 2 REG_FE1ISR_8822B */\n#define BIT_FS_RXDMA2_DONE_INT_8822B BIT(28)\n#define BIT_FS_RXDONE3_INT_8822B BIT(27)\n#define BIT_FS_RXDONE2_INT_8822B BIT(26)\n#define BIT_FS_RX_BCN_P4_INT_8822B BIT(25)\n#define BIT_FS_RX_BCN_P3_INT_8822B BIT(24)\n#define BIT_FS_RX_BCN_P2_INT_8822B BIT(23)\n#define BIT_FS_RX_BCN_P1_INT_8822B BIT(22)\n#define BIT_FS_RX_BCN_P0_INT_8822B BIT(21)\n#define BIT_FS_RX_UMD0_INT_8822B BIT(20)\n#define BIT_FS_RX_UMD1_INT_8822B BIT(19)\n#define BIT_FS_RX_BMD0_INT_8822B BIT(18)\n#define BIT_FS_RX_BMD1_INT_8822B BIT(17)\n#define BIT_FS_RXDONE_INT_8822B BIT(16)\n#define BIT_FS_WWLAN_INT_8822B BIT(15)\n#define BIT_FS_SOUND_DONE_INT_8822B BIT(14)\n#define BIT_FS_LP_STBY_INT_8822B BIT(13)\n#define BIT_FS_TRL_MTR_INT_8822B BIT(12)\n#define BIT_FS_BF1_PRETO_INT_8822B BIT(11)\n#define BIT_FS_BF0_PRETO_INT_8822B BIT(10)\n#define BIT_FS_PTCL_RELEASE_MACID_INT_8822B BIT(9)\n#define BIT_FS_LTE_COEX_INT_8822B BIT(6)\n#define BIT_FS_WLACTOFF_INT_8822B BIT(5)\n#define BIT_FS_WLACTON_INT_8822B BIT(4)\n#define BIT_FS_BCN_RX_INT_INT_8822B BIT(3)\n#define BIT_FS_MAILBOX_TO_I2C_INT_8822B BIT(2)\n#define BIT_FS_TRPC_TO_INT_8822B BIT(1)\n#define BIT_FS_RPC_O_T_INT_8822B BIT(0)\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_CPWM_8822B */\n#define BIT_CPWM_TOGGLING_8822B BIT(31)\n\n#define BIT_SHIFT_CPWM_MOD_8822B 24\n#define BIT_MASK_CPWM_MOD_8822B 0x7f\n#define BIT_CPWM_MOD_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_CPWM_MOD_8822B) << BIT_SHIFT_CPWM_MOD_8822B)\n#define BITS_CPWM_MOD_8822B                                                    \\\n\t(BIT_MASK_CPWM_MOD_8822B << BIT_SHIFT_CPWM_MOD_8822B)\n#define BIT_CLEAR_CPWM_MOD_8822B(x) ((x) & (~BITS_CPWM_MOD_8822B))\n#define BIT_GET_CPWM_MOD_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_CPWM_MOD_8822B) & BIT_MASK_CPWM_MOD_8822B)\n#define BIT_SET_CPWM_MOD_8822B(x, v)                                           \\\n\t(BIT_CLEAR_CPWM_MOD_8822B(x) | BIT_CPWM_MOD_8822B(v))\n\n/* 2 REG_FWIMR_8822B */\n#define BIT_FS_TXBCNOK_MB7_INT_EN_8822B BIT(31)\n#define BIT_FS_TXBCNOK_MB6_INT_EN_8822B BIT(30)\n#define BIT_FS_TXBCNOK_MB5_INT_EN_8822B BIT(29)\n#define BIT_FS_TXBCNOK_MB4_INT_EN_8822B BIT(28)\n#define BIT_FS_TXBCNOK_MB3_INT_EN_8822B BIT(27)\n#define BIT_FS_TXBCNOK_MB2_INT_EN_8822B BIT(26)\n#define BIT_FS_TXBCNOK_MB1_INT_EN_8822B BIT(25)\n#define BIT_FS_TXBCNOK_MB0_INT_EN_8822B BIT(24)\n#define BIT_FS_TXBCNERR_MB7_INT_EN_8822B BIT(23)\n#define BIT_FS_TXBCNERR_MB6_INT_EN_8822B BIT(22)\n#define BIT_FS_TXBCNERR_MB5_INT_EN_8822B BIT(21)\n#define BIT_FS_TXBCNERR_MB4_INT_EN_8822B BIT(20)\n#define BIT_FS_TXBCNERR_MB3_INT_EN_8822B BIT(19)\n#define BIT_FS_TXBCNERR_MB2_INT_EN_8822B BIT(18)\n#define BIT_FS_TXBCNERR_MB1_INT_EN_8822B BIT(17)\n#define BIT_FS_TXBCNERR_MB0_INT_EN_8822B BIT(16)\n#define BIT_CPU_MGQ_TXDONE_INT_EN_8822B BIT(15)\n#define BIT_SIFS_OVERSPEC_INT_EN_8822B BIT(14)\n#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8822B BIT(13)\n#define BIT_FS_MGNTQFF_TO_INT_EN_8822B BIT(12)\n#define BIT_FS_CPUMGQ_ERR_INT_EN_8822B BIT(11)\n#define BIT_FS_DDMA0_LP_INT_EN_8822B BIT(9)\n#define BIT_FS_DDMA0_HP_INT_EN_8822B BIT(8)\n#define BIT_FS_TRXRPT_INT_EN_8822B BIT(7)\n#define BIT_FS_C2H_W_READY_INT_EN_8822B BIT(6)\n#define BIT_FS_HRCV_INT_EN_8822B BIT(5)\n#define BIT_FS_H2CCMD_INT_EN_8822B BIT(4)\n#define BIT_FS_TXPKTIN_INT_EN_8822B BIT(3)\n#define BIT_FS_ERRORHDL_INT_EN_8822B BIT(2)\n#define BIT_FS_TXCCX_INT_EN_8822B BIT(1)\n#define BIT_FS_TXCLOSE_INT_EN_8822B BIT(0)\n\n/* 2 REG_FWISR_8822B */\n#define BIT_FS_TXBCNOK_MB7_INT_8822B BIT(31)\n#define BIT_FS_TXBCNOK_MB6_INT_8822B BIT(30)\n#define BIT_FS_TXBCNOK_MB5_INT_8822B BIT(29)\n#define BIT_FS_TXBCNOK_MB4_INT_8822B BIT(28)\n#define BIT_FS_TXBCNOK_MB3_INT_8822B BIT(27)\n#define BIT_FS_TXBCNOK_MB2_INT_8822B BIT(26)\n#define BIT_FS_TXBCNOK_MB1_INT_8822B BIT(25)\n#define BIT_FS_TXBCNOK_MB0_INT_8822B BIT(24)\n#define BIT_FS_TXBCNERR_MB7_INT_8822B BIT(23)\n#define BIT_FS_TXBCNERR_MB6_INT_8822B BIT(22)\n#define BIT_FS_TXBCNERR_MB5_INT_8822B BIT(21)\n#define BIT_FS_TXBCNERR_MB4_INT_8822B BIT(20)\n#define BIT_FS_TXBCNERR_MB3_INT_8822B BIT(19)\n#define BIT_FS_TXBCNERR_MB2_INT_8822B BIT(18)\n#define BIT_FS_TXBCNERR_MB1_INT_8822B BIT(17)\n#define BIT_FS_TXBCNERR_MB0_INT_8822B BIT(16)\n#define BIT_CPU_MGQ_TXDONE_INT_8822B BIT(15)\n#define BIT_SIFS_OVERSPEC_INT_8822B BIT(14)\n#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8822B BIT(13)\n#define BIT_FS_MGNTQFF_TO_INT_8822B BIT(12)\n#define BIT_FS_CPUMGQ_ERR_INT_8822B BIT(11)\n#define BIT_FS_DDMA0_LP_INT_8822B BIT(9)\n#define BIT_FS_DDMA0_HP_INT_8822B BIT(8)\n#define BIT_FS_TRXRPT_INT_8822B BIT(7)\n#define BIT_FS_C2H_W_READY_INT_8822B BIT(6)\n#define BIT_FS_HRCV_INT_8822B BIT(5)\n#define BIT_FS_H2CCMD_INT_8822B BIT(4)\n#define BIT_FS_TXPKTIN_INT_8822B BIT(3)\n#define BIT_FS_ERRORHDL_INT_8822B BIT(2)\n#define BIT_FS_TXCCX_INT_8822B BIT(1)\n#define BIT_FS_TXCLOSE_INT_8822B BIT(0)\n\n/* 2 REG_FTIMR_8822B */\n#define BIT_PS_TIMER_C_EARLY_INT_EN_8822B BIT(23)\n#define BIT_PS_TIMER_B_EARLY_INT_EN_8822B BIT(22)\n#define BIT_PS_TIMER_A_EARLY_INT_EN_8822B BIT(21)\n#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8822B BIT(20)\n#define BIT_PS_TIMER_C_INT_EN_8822B BIT(19)\n#define BIT_PS_TIMER_B_INT_EN_8822B BIT(18)\n#define BIT_PS_TIMER_A_INT_EN_8822B BIT(17)\n#define BIT_CPUMGQ_TX_TIMER_INT_EN_8822B BIT(16)\n#define BIT_FS_PS_TIMEOUT2_EN_8822B BIT(15)\n#define BIT_FS_PS_TIMEOUT1_EN_8822B BIT(14)\n#define BIT_FS_PS_TIMEOUT0_EN_8822B BIT(13)\n#define BIT_FS_GTINT8_EN_8822B BIT(8)\n#define BIT_FS_GTINT7_EN_8822B BIT(7)\n#define BIT_FS_GTINT6_EN_8822B BIT(6)\n#define BIT_FS_GTINT5_EN_8822B BIT(5)\n#define BIT_FS_GTINT4_EN_8822B BIT(4)\n#define BIT_FS_GTINT3_EN_8822B BIT(3)\n#define BIT_FS_GTINT2_EN_8822B BIT(2)\n#define BIT_FS_GTINT1_EN_8822B BIT(1)\n#define BIT_FS_GTINT0_EN_8822B BIT(0)\n\n/* 2 REG_FTISR_8822B */\n#define BIT_PS_TIMER_C_EARLY__INT_8822B BIT(23)\n#define BIT_PS_TIMER_B_EARLY__INT_8822B BIT(22)\n#define BIT_PS_TIMER_A_EARLY__INT_8822B BIT(21)\n#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8822B BIT(20)\n#define BIT_PS_TIMER_C_INT_8822B BIT(19)\n#define BIT_PS_TIMER_B_INT_8822B BIT(18)\n#define BIT_PS_TIMER_A_INT_8822B BIT(17)\n#define BIT_CPUMGQ_TX_TIMER_INT_8822B BIT(16)\n#define BIT_FS_PS_TIMEOUT2_INT_8822B BIT(15)\n#define BIT_FS_PS_TIMEOUT1_INT_8822B BIT(14)\n#define BIT_FS_PS_TIMEOUT0_INT_8822B BIT(13)\n#define BIT_FS_GTINT8_INT_8822B BIT(8)\n#define BIT_FS_GTINT7_INT_8822B BIT(7)\n#define BIT_FS_GTINT6_INT_8822B BIT(6)\n#define BIT_FS_GTINT5_INT_8822B BIT(5)\n#define BIT_FS_GTINT4_INT_8822B BIT(4)\n#define BIT_FS_GTINT3_INT_8822B BIT(3)\n#define BIT_FS_GTINT2_INT_8822B BIT(2)\n#define BIT_FS_GTINT1_INT_8822B BIT(1)\n#define BIT_FS_GTINT0_INT_8822B BIT(0)\n\n/* 2 REG_PKTBUF_DBG_CTRL_8822B */\n\n#define BIT_SHIFT_PKTBUF_WRITE_EN_8822B 24\n#define BIT_MASK_PKTBUF_WRITE_EN_8822B 0xff\n#define BIT_PKTBUF_WRITE_EN_8822B(x)                                           \\\n\t(((x) & BIT_MASK_PKTBUF_WRITE_EN_8822B)                                \\\n\t << BIT_SHIFT_PKTBUF_WRITE_EN_8822B)\n#define BITS_PKTBUF_WRITE_EN_8822B                                             \\\n\t(BIT_MASK_PKTBUF_WRITE_EN_8822B << BIT_SHIFT_PKTBUF_WRITE_EN_8822B)\n#define BIT_CLEAR_PKTBUF_WRITE_EN_8822B(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8822B))\n#define BIT_GET_PKTBUF_WRITE_EN_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8822B) &                            \\\n\t BIT_MASK_PKTBUF_WRITE_EN_8822B)\n#define BIT_SET_PKTBUF_WRITE_EN_8822B(x, v)                                    \\\n\t(BIT_CLEAR_PKTBUF_WRITE_EN_8822B(x) | BIT_PKTBUF_WRITE_EN_8822B(v))\n\n#define BIT_TXRPTBUF_DBG_8822B BIT(23)\n\n/* 2 REG_NOT_VALID_8822B */\n#define BIT_TXPKTBUF_DBG_V2_8822B BIT(20)\n#define BIT_RXPKTBUF_DBG_8822B BIT(16)\n\n#define BIT_SHIFT_PKTBUF_DBG_ADDR_8822B 0\n#define BIT_MASK_PKTBUF_DBG_ADDR_8822B 0x1fff\n#define BIT_PKTBUF_DBG_ADDR_8822B(x)                                           \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_ADDR_8822B)                                \\\n\t << BIT_SHIFT_PKTBUF_DBG_ADDR_8822B)\n#define BITS_PKTBUF_DBG_ADDR_8822B                                             \\\n\t(BIT_MASK_PKTBUF_DBG_ADDR_8822B << BIT_SHIFT_PKTBUF_DBG_ADDR_8822B)\n#define BIT_CLEAR_PKTBUF_DBG_ADDR_8822B(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8822B))\n#define BIT_GET_PKTBUF_DBG_ADDR_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8822B) &                            \\\n\t BIT_MASK_PKTBUF_DBG_ADDR_8822B)\n#define BIT_SET_PKTBUF_DBG_ADDR_8822B(x, v)                                    \\\n\t(BIT_CLEAR_PKTBUF_DBG_ADDR_8822B(x) | BIT_PKTBUF_DBG_ADDR_8822B(v))\n\n/* 2 REG_PKTBUF_DBG_DATA_L_8822B */\n\n#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B 0\n#define BIT_MASK_PKTBUF_DBG_DATA_L_8822B 0xffffffffL\n#define BIT_PKTBUF_DBG_DATA_L_8822B(x)                                         \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8822B)                              \\\n\t << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B)\n#define BITS_PKTBUF_DBG_DATA_L_8822B                                           \\\n\t(BIT_MASK_PKTBUF_DBG_DATA_L_8822B << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B)\n#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8822B(x)                                   \\\n\t((x) & (~BITS_PKTBUF_DBG_DATA_L_8822B))\n#define BIT_GET_PKTBUF_DBG_DATA_L_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B) &                          \\\n\t BIT_MASK_PKTBUF_DBG_DATA_L_8822B)\n#define BIT_SET_PKTBUF_DBG_DATA_L_8822B(x, v)                                  \\\n\t(BIT_CLEAR_PKTBUF_DBG_DATA_L_8822B(x) | BIT_PKTBUF_DBG_DATA_L_8822B(v))\n\n/* 2 REG_PKTBUF_DBG_DATA_H_8822B */\n\n#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B 0\n#define BIT_MASK_PKTBUF_DBG_DATA_H_8822B 0xffffffffL\n#define BIT_PKTBUF_DBG_DATA_H_8822B(x)                                         \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8822B)                              \\\n\t << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B)\n#define BITS_PKTBUF_DBG_DATA_H_8822B                                           \\\n\t(BIT_MASK_PKTBUF_DBG_DATA_H_8822B << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B)\n#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8822B(x)                                   \\\n\t((x) & (~BITS_PKTBUF_DBG_DATA_H_8822B))\n#define BIT_GET_PKTBUF_DBG_DATA_H_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B) &                          \\\n\t BIT_MASK_PKTBUF_DBG_DATA_H_8822B)\n#define BIT_SET_PKTBUF_DBG_DATA_H_8822B(x, v)                                  \\\n\t(BIT_CLEAR_PKTBUF_DBG_DATA_H_8822B(x) | BIT_PKTBUF_DBG_DATA_H_8822B(v))\n\n/* 2 REG_CPWM2_8822B */\n\n#define BIT_SHIFT_L0S_TO_RCVY_NUM_8822B 16\n#define BIT_MASK_L0S_TO_RCVY_NUM_8822B 0xff\n#define BIT_L0S_TO_RCVY_NUM_8822B(x)                                           \\\n\t(((x) & BIT_MASK_L0S_TO_RCVY_NUM_8822B)                                \\\n\t << BIT_SHIFT_L0S_TO_RCVY_NUM_8822B)\n#define BITS_L0S_TO_RCVY_NUM_8822B                                             \\\n\t(BIT_MASK_L0S_TO_RCVY_NUM_8822B << BIT_SHIFT_L0S_TO_RCVY_NUM_8822B)\n#define BIT_CLEAR_L0S_TO_RCVY_NUM_8822B(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8822B))\n#define BIT_GET_L0S_TO_RCVY_NUM_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8822B) &                            \\\n\t BIT_MASK_L0S_TO_RCVY_NUM_8822B)\n#define BIT_SET_L0S_TO_RCVY_NUM_8822B(x, v)                                    \\\n\t(BIT_CLEAR_L0S_TO_RCVY_NUM_8822B(x) | BIT_L0S_TO_RCVY_NUM_8822B(v))\n\n#define BIT_CPWM2_TOGGLING_8822B BIT(15)\n\n#define BIT_SHIFT_CPWM2_MOD_8822B 0\n#define BIT_MASK_CPWM2_MOD_8822B 0x7fff\n#define BIT_CPWM2_MOD_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_CPWM2_MOD_8822B) << BIT_SHIFT_CPWM2_MOD_8822B)\n#define BITS_CPWM2_MOD_8822B                                                   \\\n\t(BIT_MASK_CPWM2_MOD_8822B << BIT_SHIFT_CPWM2_MOD_8822B)\n#define BIT_CLEAR_CPWM2_MOD_8822B(x) ((x) & (~BITS_CPWM2_MOD_8822B))\n#define BIT_GET_CPWM2_MOD_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_CPWM2_MOD_8822B) & BIT_MASK_CPWM2_MOD_8822B)\n#define BIT_SET_CPWM2_MOD_8822B(x, v)                                          \\\n\t(BIT_CLEAR_CPWM2_MOD_8822B(x) | BIT_CPWM2_MOD_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_TC0_CTRL_8822B */\n#define BIT_TC0INT_EN_8822B BIT(26)\n#define BIT_TC0MODE_8822B BIT(25)\n#define BIT_TC0EN_8822B BIT(24)\n\n#define BIT_SHIFT_TC0DATA_8822B 0\n#define BIT_MASK_TC0DATA_8822B 0xffffff\n#define BIT_TC0DATA_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_TC0DATA_8822B) << BIT_SHIFT_TC0DATA_8822B)\n#define BITS_TC0DATA_8822B (BIT_MASK_TC0DATA_8822B << BIT_SHIFT_TC0DATA_8822B)\n#define BIT_CLEAR_TC0DATA_8822B(x) ((x) & (~BITS_TC0DATA_8822B))\n#define BIT_GET_TC0DATA_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC0DATA_8822B) & BIT_MASK_TC0DATA_8822B)\n#define BIT_SET_TC0DATA_8822B(x, v)                                            \\\n\t(BIT_CLEAR_TC0DATA_8822B(x) | BIT_TC0DATA_8822B(v))\n\n/* 2 REG_TC1_CTRL_8822B */\n#define BIT_TC1INT_EN_8822B BIT(26)\n#define BIT_TC1MODE_8822B BIT(25)\n#define BIT_TC1EN_8822B BIT(24)\n\n#define BIT_SHIFT_TC1DATA_8822B 0\n#define BIT_MASK_TC1DATA_8822B 0xffffff\n#define BIT_TC1DATA_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_TC1DATA_8822B) << BIT_SHIFT_TC1DATA_8822B)\n#define BITS_TC1DATA_8822B (BIT_MASK_TC1DATA_8822B << BIT_SHIFT_TC1DATA_8822B)\n#define BIT_CLEAR_TC1DATA_8822B(x) ((x) & (~BITS_TC1DATA_8822B))\n#define BIT_GET_TC1DATA_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC1DATA_8822B) & BIT_MASK_TC1DATA_8822B)\n#define BIT_SET_TC1DATA_8822B(x, v)                                            \\\n\t(BIT_CLEAR_TC1DATA_8822B(x) | BIT_TC1DATA_8822B(v))\n\n/* 2 REG_TC2_CTRL_8822B */\n#define BIT_TC2INT_EN_8822B BIT(26)\n#define BIT_TC2MODE_8822B BIT(25)\n#define BIT_TC2EN_8822B BIT(24)\n\n#define BIT_SHIFT_TC2DATA_8822B 0\n#define BIT_MASK_TC2DATA_8822B 0xffffff\n#define BIT_TC2DATA_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_TC2DATA_8822B) << BIT_SHIFT_TC2DATA_8822B)\n#define BITS_TC2DATA_8822B (BIT_MASK_TC2DATA_8822B << BIT_SHIFT_TC2DATA_8822B)\n#define BIT_CLEAR_TC2DATA_8822B(x) ((x) & (~BITS_TC2DATA_8822B))\n#define BIT_GET_TC2DATA_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC2DATA_8822B) & BIT_MASK_TC2DATA_8822B)\n#define BIT_SET_TC2DATA_8822B(x, v)                                            \\\n\t(BIT_CLEAR_TC2DATA_8822B(x) | BIT_TC2DATA_8822B(v))\n\n/* 2 REG_TC3_CTRL_8822B */\n#define BIT_TC3INT_EN_8822B BIT(26)\n#define BIT_TC3MODE_8822B BIT(25)\n#define BIT_TC3EN_8822B BIT(24)\n\n#define BIT_SHIFT_TC3DATA_8822B 0\n#define BIT_MASK_TC3DATA_8822B 0xffffff\n#define BIT_TC3DATA_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_TC3DATA_8822B) << BIT_SHIFT_TC3DATA_8822B)\n#define BITS_TC3DATA_8822B (BIT_MASK_TC3DATA_8822B << BIT_SHIFT_TC3DATA_8822B)\n#define BIT_CLEAR_TC3DATA_8822B(x) ((x) & (~BITS_TC3DATA_8822B))\n#define BIT_GET_TC3DATA_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC3DATA_8822B) & BIT_MASK_TC3DATA_8822B)\n#define BIT_SET_TC3DATA_8822B(x, v)                                            \\\n\t(BIT_CLEAR_TC3DATA_8822B(x) | BIT_TC3DATA_8822B(v))\n\n/* 2 REG_TC4_CTRL_8822B */\n#define BIT_TC4INT_EN_8822B BIT(26)\n#define BIT_TC4MODE_8822B BIT(25)\n#define BIT_TC4EN_8822B BIT(24)\n\n#define BIT_SHIFT_TC4DATA_8822B 0\n#define BIT_MASK_TC4DATA_8822B 0xffffff\n#define BIT_TC4DATA_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_TC4DATA_8822B) << BIT_SHIFT_TC4DATA_8822B)\n#define BITS_TC4DATA_8822B (BIT_MASK_TC4DATA_8822B << BIT_SHIFT_TC4DATA_8822B)\n#define BIT_CLEAR_TC4DATA_8822B(x) ((x) & (~BITS_TC4DATA_8822B))\n#define BIT_GET_TC4DATA_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC4DATA_8822B) & BIT_MASK_TC4DATA_8822B)\n#define BIT_SET_TC4DATA_8822B(x, v)                                            \\\n\t(BIT_CLEAR_TC4DATA_8822B(x) | BIT_TC4DATA_8822B(v))\n\n/* 2 REG_TCUNIT_BASE_8822B */\n\n#define BIT_SHIFT_TCUNIT_BASE_8822B 0\n#define BIT_MASK_TCUNIT_BASE_8822B 0x3fff\n#define BIT_TCUNIT_BASE_8822B(x)                                               \\\n\t(((x) & BIT_MASK_TCUNIT_BASE_8822B) << BIT_SHIFT_TCUNIT_BASE_8822B)\n#define BITS_TCUNIT_BASE_8822B                                                 \\\n\t(BIT_MASK_TCUNIT_BASE_8822B << BIT_SHIFT_TCUNIT_BASE_8822B)\n#define BIT_CLEAR_TCUNIT_BASE_8822B(x) ((x) & (~BITS_TCUNIT_BASE_8822B))\n#define BIT_GET_TCUNIT_BASE_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_TCUNIT_BASE_8822B) & BIT_MASK_TCUNIT_BASE_8822B)\n#define BIT_SET_TCUNIT_BASE_8822B(x, v)                                        \\\n\t(BIT_CLEAR_TCUNIT_BASE_8822B(x) | BIT_TCUNIT_BASE_8822B(v))\n\n/* 2 REG_TC5_CTRL_8822B */\n#define BIT_TC5INT_EN_8822B BIT(26)\n#define BIT_TC5MODE_8822B BIT(25)\n#define BIT_TC5EN_8822B BIT(24)\n\n#define BIT_SHIFT_TC5DATA_8822B 0\n#define BIT_MASK_TC5DATA_8822B 0xffffff\n#define BIT_TC5DATA_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_TC5DATA_8822B) << BIT_SHIFT_TC5DATA_8822B)\n#define BITS_TC5DATA_8822B (BIT_MASK_TC5DATA_8822B << BIT_SHIFT_TC5DATA_8822B)\n#define BIT_CLEAR_TC5DATA_8822B(x) ((x) & (~BITS_TC5DATA_8822B))\n#define BIT_GET_TC5DATA_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC5DATA_8822B) & BIT_MASK_TC5DATA_8822B)\n#define BIT_SET_TC5DATA_8822B(x, v)                                            \\\n\t(BIT_CLEAR_TC5DATA_8822B(x) | BIT_TC5DATA_8822B(v))\n\n/* 2 REG_TC6_CTRL_8822B */\n#define BIT_TC6INT_EN_8822B BIT(26)\n#define BIT_TC6MODE_8822B BIT(25)\n#define BIT_TC6EN_8822B BIT(24)\n\n#define BIT_SHIFT_TC6DATA_8822B 0\n#define BIT_MASK_TC6DATA_8822B 0xffffff\n#define BIT_TC6DATA_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_TC6DATA_8822B) << BIT_SHIFT_TC6DATA_8822B)\n#define BITS_TC6DATA_8822B (BIT_MASK_TC6DATA_8822B << BIT_SHIFT_TC6DATA_8822B)\n#define BIT_CLEAR_TC6DATA_8822B(x) ((x) & (~BITS_TC6DATA_8822B))\n#define BIT_GET_TC6DATA_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC6DATA_8822B) & BIT_MASK_TC6DATA_8822B)\n#define BIT_SET_TC6DATA_8822B(x, v)                                            \\\n\t(BIT_CLEAR_TC6DATA_8822B(x) | BIT_TC6DATA_8822B(v))\n\n/* 2 REG_MBIST_FAIL_8822B */\n\n#define BIT_SHIFT_8051_MBIST_FAIL_8822B 26\n#define BIT_MASK_8051_MBIST_FAIL_8822B 0x7\n#define BIT_8051_MBIST_FAIL_8822B(x)                                           \\\n\t(((x) & BIT_MASK_8051_MBIST_FAIL_8822B)                                \\\n\t << BIT_SHIFT_8051_MBIST_FAIL_8822B)\n#define BITS_8051_MBIST_FAIL_8822B                                             \\\n\t(BIT_MASK_8051_MBIST_FAIL_8822B << BIT_SHIFT_8051_MBIST_FAIL_8822B)\n#define BIT_CLEAR_8051_MBIST_FAIL_8822B(x) ((x) & (~BITS_8051_MBIST_FAIL_8822B))\n#define BIT_GET_8051_MBIST_FAIL_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_FAIL_8822B) &                            \\\n\t BIT_MASK_8051_MBIST_FAIL_8822B)\n#define BIT_SET_8051_MBIST_FAIL_8822B(x, v)                                    \\\n\t(BIT_CLEAR_8051_MBIST_FAIL_8822B(x) | BIT_8051_MBIST_FAIL_8822B(v))\n\n#define BIT_SHIFT_USB_MBIST_FAIL_8822B 24\n#define BIT_MASK_USB_MBIST_FAIL_8822B 0x3\n#define BIT_USB_MBIST_FAIL_8822B(x)                                            \\\n\t(((x) & BIT_MASK_USB_MBIST_FAIL_8822B)                                 \\\n\t << BIT_SHIFT_USB_MBIST_FAIL_8822B)\n#define BITS_USB_MBIST_FAIL_8822B                                              \\\n\t(BIT_MASK_USB_MBIST_FAIL_8822B << BIT_SHIFT_USB_MBIST_FAIL_8822B)\n#define BIT_CLEAR_USB_MBIST_FAIL_8822B(x) ((x) & (~BITS_USB_MBIST_FAIL_8822B))\n#define BIT_GET_USB_MBIST_FAIL_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_FAIL_8822B) &                             \\\n\t BIT_MASK_USB_MBIST_FAIL_8822B)\n#define BIT_SET_USB_MBIST_FAIL_8822B(x, v)                                     \\\n\t(BIT_CLEAR_USB_MBIST_FAIL_8822B(x) | BIT_USB_MBIST_FAIL_8822B(v))\n\n#define BIT_SHIFT_PCIE_MBIST_FAIL_8822B 16\n#define BIT_MASK_PCIE_MBIST_FAIL_8822B 0x3f\n#define BIT_PCIE_MBIST_FAIL_8822B(x)                                           \\\n\t(((x) & BIT_MASK_PCIE_MBIST_FAIL_8822B)                                \\\n\t << BIT_SHIFT_PCIE_MBIST_FAIL_8822B)\n#define BITS_PCIE_MBIST_FAIL_8822B                                             \\\n\t(BIT_MASK_PCIE_MBIST_FAIL_8822B << BIT_SHIFT_PCIE_MBIST_FAIL_8822B)\n#define BIT_CLEAR_PCIE_MBIST_FAIL_8822B(x) ((x) & (~BITS_PCIE_MBIST_FAIL_8822B))\n#define BIT_GET_PCIE_MBIST_FAIL_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8822B) &                            \\\n\t BIT_MASK_PCIE_MBIST_FAIL_8822B)\n#define BIT_SET_PCIE_MBIST_FAIL_8822B(x, v)                                    \\\n\t(BIT_CLEAR_PCIE_MBIST_FAIL_8822B(x) | BIT_PCIE_MBIST_FAIL_8822B(v))\n\n#define BIT_SHIFT_MAC_MBIST_FAIL_8822B 0\n#define BIT_MASK_MAC_MBIST_FAIL_8822B 0xfff\n#define BIT_MAC_MBIST_FAIL_8822B(x)                                            \\\n\t(((x) & BIT_MASK_MAC_MBIST_FAIL_8822B)                                 \\\n\t << BIT_SHIFT_MAC_MBIST_FAIL_8822B)\n#define BITS_MAC_MBIST_FAIL_8822B                                              \\\n\t(BIT_MASK_MAC_MBIST_FAIL_8822B << BIT_SHIFT_MAC_MBIST_FAIL_8822B)\n#define BIT_CLEAR_MAC_MBIST_FAIL_8822B(x) ((x) & (~BITS_MAC_MBIST_FAIL_8822B))\n#define BIT_GET_MAC_MBIST_FAIL_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8822B) &                             \\\n\t BIT_MASK_MAC_MBIST_FAIL_8822B)\n#define BIT_SET_MAC_MBIST_FAIL_8822B(x, v)                                     \\\n\t(BIT_CLEAR_MAC_MBIST_FAIL_8822B(x) | BIT_MAC_MBIST_FAIL_8822B(v))\n\n/* 2 REG_MBIST_START_PAUSE_8822B */\n\n#define BIT_SHIFT_8051_MBIST_START_PAUSE_8822B 26\n#define BIT_MASK_8051_MBIST_START_PAUSE_8822B 0x7\n#define BIT_8051_MBIST_START_PAUSE_8822B(x)                                    \\\n\t(((x) & BIT_MASK_8051_MBIST_START_PAUSE_8822B)                         \\\n\t << BIT_SHIFT_8051_MBIST_START_PAUSE_8822B)\n#define BITS_8051_MBIST_START_PAUSE_8822B                                      \\\n\t(BIT_MASK_8051_MBIST_START_PAUSE_8822B                                 \\\n\t << BIT_SHIFT_8051_MBIST_START_PAUSE_8822B)\n#define BIT_CLEAR_8051_MBIST_START_PAUSE_8822B(x)                              \\\n\t((x) & (~BITS_8051_MBIST_START_PAUSE_8822B))\n#define BIT_GET_8051_MBIST_START_PAUSE_8822B(x)                                \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8822B) &                     \\\n\t BIT_MASK_8051_MBIST_START_PAUSE_8822B)\n#define BIT_SET_8051_MBIST_START_PAUSE_8822B(x, v)                             \\\n\t(BIT_CLEAR_8051_MBIST_START_PAUSE_8822B(x) |                           \\\n\t BIT_8051_MBIST_START_PAUSE_8822B(v))\n\n#define BIT_SHIFT_USB_MBIST_START_PAUSE_8822B 24\n#define BIT_MASK_USB_MBIST_START_PAUSE_8822B 0x3\n#define BIT_USB_MBIST_START_PAUSE_8822B(x)                                     \\\n\t(((x) & BIT_MASK_USB_MBIST_START_PAUSE_8822B)                          \\\n\t << BIT_SHIFT_USB_MBIST_START_PAUSE_8822B)\n#define BITS_USB_MBIST_START_PAUSE_8822B                                       \\\n\t(BIT_MASK_USB_MBIST_START_PAUSE_8822B                                  \\\n\t << BIT_SHIFT_USB_MBIST_START_PAUSE_8822B)\n#define BIT_CLEAR_USB_MBIST_START_PAUSE_8822B(x)                               \\\n\t((x) & (~BITS_USB_MBIST_START_PAUSE_8822B))\n#define BIT_GET_USB_MBIST_START_PAUSE_8822B(x)                                 \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8822B) &                      \\\n\t BIT_MASK_USB_MBIST_START_PAUSE_8822B)\n#define BIT_SET_USB_MBIST_START_PAUSE_8822B(x, v)                              \\\n\t(BIT_CLEAR_USB_MBIST_START_PAUSE_8822B(x) |                            \\\n\t BIT_USB_MBIST_START_PAUSE_8822B(v))\n\n#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B 16\n#define BIT_MASK_PCIE_MBIST_START_PAUSE_8822B 0x3f\n#define BIT_PCIE_MBIST_START_PAUSE_8822B(x)                                    \\\n\t(((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8822B)                         \\\n\t << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B)\n#define BITS_PCIE_MBIST_START_PAUSE_8822B                                      \\\n\t(BIT_MASK_PCIE_MBIST_START_PAUSE_8822B                                 \\\n\t << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B)\n#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_8822B(x)                              \\\n\t((x) & (~BITS_PCIE_MBIST_START_PAUSE_8822B))\n#define BIT_GET_PCIE_MBIST_START_PAUSE_8822B(x)                                \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B) &                     \\\n\t BIT_MASK_PCIE_MBIST_START_PAUSE_8822B)\n#define BIT_SET_PCIE_MBIST_START_PAUSE_8822B(x, v)                             \\\n\t(BIT_CLEAR_PCIE_MBIST_START_PAUSE_8822B(x) |                           \\\n\t BIT_PCIE_MBIST_START_PAUSE_8822B(v))\n\n#define BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B 0\n#define BIT_MASK_MAC_MBIST_START_PAUSE_8822B 0xfff\n#define BIT_MAC_MBIST_START_PAUSE_8822B(x)                                     \\\n\t(((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8822B)                          \\\n\t << BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B)\n#define BITS_MAC_MBIST_START_PAUSE_8822B                                       \\\n\t(BIT_MASK_MAC_MBIST_START_PAUSE_8822B                                  \\\n\t << BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B)\n#define BIT_CLEAR_MAC_MBIST_START_PAUSE_8822B(x)                               \\\n\t((x) & (~BITS_MAC_MBIST_START_PAUSE_8822B))\n#define BIT_GET_MAC_MBIST_START_PAUSE_8822B(x)                                 \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B) &                      \\\n\t BIT_MASK_MAC_MBIST_START_PAUSE_8822B)\n#define BIT_SET_MAC_MBIST_START_PAUSE_8822B(x, v)                              \\\n\t(BIT_CLEAR_MAC_MBIST_START_PAUSE_8822B(x) |                            \\\n\t BIT_MAC_MBIST_START_PAUSE_8822B(v))\n\n/* 2 REG_MBIST_DONE_8822B */\n\n#define BIT_SHIFT_8051_MBIST_DONE_8822B 26\n#define BIT_MASK_8051_MBIST_DONE_8822B 0x7\n#define BIT_8051_MBIST_DONE_8822B(x)                                           \\\n\t(((x) & BIT_MASK_8051_MBIST_DONE_8822B)                                \\\n\t << BIT_SHIFT_8051_MBIST_DONE_8822B)\n#define BITS_8051_MBIST_DONE_8822B                                             \\\n\t(BIT_MASK_8051_MBIST_DONE_8822B << BIT_SHIFT_8051_MBIST_DONE_8822B)\n#define BIT_CLEAR_8051_MBIST_DONE_8822B(x) ((x) & (~BITS_8051_MBIST_DONE_8822B))\n#define BIT_GET_8051_MBIST_DONE_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_DONE_8822B) &                            \\\n\t BIT_MASK_8051_MBIST_DONE_8822B)\n#define BIT_SET_8051_MBIST_DONE_8822B(x, v)                                    \\\n\t(BIT_CLEAR_8051_MBIST_DONE_8822B(x) | BIT_8051_MBIST_DONE_8822B(v))\n\n#define BIT_SHIFT_USB_MBIST_DONE_8822B 24\n#define BIT_MASK_USB_MBIST_DONE_8822B 0x3\n#define BIT_USB_MBIST_DONE_8822B(x)                                            \\\n\t(((x) & BIT_MASK_USB_MBIST_DONE_8822B)                                 \\\n\t << BIT_SHIFT_USB_MBIST_DONE_8822B)\n#define BITS_USB_MBIST_DONE_8822B                                              \\\n\t(BIT_MASK_USB_MBIST_DONE_8822B << BIT_SHIFT_USB_MBIST_DONE_8822B)\n#define BIT_CLEAR_USB_MBIST_DONE_8822B(x) ((x) & (~BITS_USB_MBIST_DONE_8822B))\n#define BIT_GET_USB_MBIST_DONE_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_DONE_8822B) &                             \\\n\t BIT_MASK_USB_MBIST_DONE_8822B)\n#define BIT_SET_USB_MBIST_DONE_8822B(x, v)                                     \\\n\t(BIT_CLEAR_USB_MBIST_DONE_8822B(x) | BIT_USB_MBIST_DONE_8822B(v))\n\n#define BIT_SHIFT_PCIE_MBIST_DONE_8822B 16\n#define BIT_MASK_PCIE_MBIST_DONE_8822B 0x3f\n#define BIT_PCIE_MBIST_DONE_8822B(x)                                           \\\n\t(((x) & BIT_MASK_PCIE_MBIST_DONE_8822B)                                \\\n\t << BIT_SHIFT_PCIE_MBIST_DONE_8822B)\n#define BITS_PCIE_MBIST_DONE_8822B                                             \\\n\t(BIT_MASK_PCIE_MBIST_DONE_8822B << BIT_SHIFT_PCIE_MBIST_DONE_8822B)\n#define BIT_CLEAR_PCIE_MBIST_DONE_8822B(x) ((x) & (~BITS_PCIE_MBIST_DONE_8822B))\n#define BIT_GET_PCIE_MBIST_DONE_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8822B) &                            \\\n\t BIT_MASK_PCIE_MBIST_DONE_8822B)\n#define BIT_SET_PCIE_MBIST_DONE_8822B(x, v)                                    \\\n\t(BIT_CLEAR_PCIE_MBIST_DONE_8822B(x) | BIT_PCIE_MBIST_DONE_8822B(v))\n\n#define BIT_SHIFT_MAC_MBIST_DONE_8822B 0\n#define BIT_MASK_MAC_MBIST_DONE_8822B 0xfff\n#define BIT_MAC_MBIST_DONE_8822B(x)                                            \\\n\t(((x) & BIT_MASK_MAC_MBIST_DONE_8822B)                                 \\\n\t << BIT_SHIFT_MAC_MBIST_DONE_8822B)\n#define BITS_MAC_MBIST_DONE_8822B                                              \\\n\t(BIT_MASK_MAC_MBIST_DONE_8822B << BIT_SHIFT_MAC_MBIST_DONE_8822B)\n#define BIT_CLEAR_MAC_MBIST_DONE_8822B(x) ((x) & (~BITS_MAC_MBIST_DONE_8822B))\n#define BIT_GET_MAC_MBIST_DONE_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_DONE_8822B) &                             \\\n\t BIT_MASK_MAC_MBIST_DONE_8822B)\n#define BIT_SET_MAC_MBIST_DONE_8822B(x, v)                                     \\\n\t(BIT_CLEAR_MAC_MBIST_DONE_8822B(x) | BIT_MAC_MBIST_DONE_8822B(v))\n\n/* 2 REG_MBIST_FAIL_NRML_8822B */\n\n#define BIT_SHIFT_MBIST_FAIL_NRML_8822B 0\n#define BIT_MASK_MBIST_FAIL_NRML_8822B 0xffffffffL\n#define BIT_MBIST_FAIL_NRML_8822B(x)                                           \\\n\t(((x) & BIT_MASK_MBIST_FAIL_NRML_8822B)                                \\\n\t << BIT_SHIFT_MBIST_FAIL_NRML_8822B)\n#define BITS_MBIST_FAIL_NRML_8822B                                             \\\n\t(BIT_MASK_MBIST_FAIL_NRML_8822B << BIT_SHIFT_MBIST_FAIL_NRML_8822B)\n#define BIT_CLEAR_MBIST_FAIL_NRML_8822B(x) ((x) & (~BITS_MBIST_FAIL_NRML_8822B))\n#define BIT_GET_MBIST_FAIL_NRML_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8822B) &                            \\\n\t BIT_MASK_MBIST_FAIL_NRML_8822B)\n#define BIT_SET_MBIST_FAIL_NRML_8822B(x, v)                                    \\\n\t(BIT_CLEAR_MBIST_FAIL_NRML_8822B(x) | BIT_MBIST_FAIL_NRML_8822B(v))\n\n/* 2 REG_AES_DECRPT_DATA_8822B */\n\n#define BIT_SHIFT_IPS_CFG_ADDR_8822B 0\n#define BIT_MASK_IPS_CFG_ADDR_8822B 0xff\n#define BIT_IPS_CFG_ADDR_8822B(x)                                              \\\n\t(((x) & BIT_MASK_IPS_CFG_ADDR_8822B) << BIT_SHIFT_IPS_CFG_ADDR_8822B)\n#define BITS_IPS_CFG_ADDR_8822B                                                \\\n\t(BIT_MASK_IPS_CFG_ADDR_8822B << BIT_SHIFT_IPS_CFG_ADDR_8822B)\n#define BIT_CLEAR_IPS_CFG_ADDR_8822B(x) ((x) & (~BITS_IPS_CFG_ADDR_8822B))\n#define BIT_GET_IPS_CFG_ADDR_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_IPS_CFG_ADDR_8822B) & BIT_MASK_IPS_CFG_ADDR_8822B)\n#define BIT_SET_IPS_CFG_ADDR_8822B(x, v)                                       \\\n\t(BIT_CLEAR_IPS_CFG_ADDR_8822B(x) | BIT_IPS_CFG_ADDR_8822B(v))\n\n/* 2 REG_AES_DECRPT_CFG_8822B */\n\n#define BIT_SHIFT_IPS_CFG_DATA_8822B 0\n#define BIT_MASK_IPS_CFG_DATA_8822B 0xffffffffL\n#define BIT_IPS_CFG_DATA_8822B(x)                                              \\\n\t(((x) & BIT_MASK_IPS_CFG_DATA_8822B) << BIT_SHIFT_IPS_CFG_DATA_8822B)\n#define BITS_IPS_CFG_DATA_8822B                                                \\\n\t(BIT_MASK_IPS_CFG_DATA_8822B << BIT_SHIFT_IPS_CFG_DATA_8822B)\n#define BIT_CLEAR_IPS_CFG_DATA_8822B(x) ((x) & (~BITS_IPS_CFG_DATA_8822B))\n#define BIT_GET_IPS_CFG_DATA_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_IPS_CFG_DATA_8822B) & BIT_MASK_IPS_CFG_DATA_8822B)\n#define BIT_SET_IPS_CFG_DATA_8822B(x, v)                                       \\\n\t(BIT_CLEAR_IPS_CFG_DATA_8822B(x) | BIT_IPS_CFG_DATA_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_TMETER_8822B */\n#define BIT_TEMP_VALID_8822B BIT(31)\n\n#define BIT_SHIFT_TEMP_VALUE_8822B 24\n#define BIT_MASK_TEMP_VALUE_8822B 0x3f\n#define BIT_TEMP_VALUE_8822B(x)                                                \\\n\t(((x) & BIT_MASK_TEMP_VALUE_8822B) << BIT_SHIFT_TEMP_VALUE_8822B)\n#define BITS_TEMP_VALUE_8822B                                                  \\\n\t(BIT_MASK_TEMP_VALUE_8822B << BIT_SHIFT_TEMP_VALUE_8822B)\n#define BIT_CLEAR_TEMP_VALUE_8822B(x) ((x) & (~BITS_TEMP_VALUE_8822B))\n#define BIT_GET_TEMP_VALUE_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_TEMP_VALUE_8822B) & BIT_MASK_TEMP_VALUE_8822B)\n#define BIT_SET_TEMP_VALUE_8822B(x, v)                                         \\\n\t(BIT_CLEAR_TEMP_VALUE_8822B(x) | BIT_TEMP_VALUE_8822B(v))\n\n#define BIT_SHIFT_REG_TMETER_TIMER_8822B 8\n#define BIT_MASK_REG_TMETER_TIMER_8822B 0xfff\n#define BIT_REG_TMETER_TIMER_8822B(x)                                          \\\n\t(((x) & BIT_MASK_REG_TMETER_TIMER_8822B)                               \\\n\t << BIT_SHIFT_REG_TMETER_TIMER_8822B)\n#define BITS_REG_TMETER_TIMER_8822B                                            \\\n\t(BIT_MASK_REG_TMETER_TIMER_8822B << BIT_SHIFT_REG_TMETER_TIMER_8822B)\n#define BIT_CLEAR_REG_TMETER_TIMER_8822B(x)                                    \\\n\t((x) & (~BITS_REG_TMETER_TIMER_8822B))\n#define BIT_GET_REG_TMETER_TIMER_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_REG_TMETER_TIMER_8822B) &                           \\\n\t BIT_MASK_REG_TMETER_TIMER_8822B)\n#define BIT_SET_REG_TMETER_TIMER_8822B(x, v)                                   \\\n\t(BIT_CLEAR_REG_TMETER_TIMER_8822B(x) | BIT_REG_TMETER_TIMER_8822B(v))\n\n#define BIT_SHIFT_REG_TEMP_DELTA_8822B 2\n#define BIT_MASK_REG_TEMP_DELTA_8822B 0x3f\n#define BIT_REG_TEMP_DELTA_8822B(x)                                            \\\n\t(((x) & BIT_MASK_REG_TEMP_DELTA_8822B)                                 \\\n\t << BIT_SHIFT_REG_TEMP_DELTA_8822B)\n#define BITS_REG_TEMP_DELTA_8822B                                              \\\n\t(BIT_MASK_REG_TEMP_DELTA_8822B << BIT_SHIFT_REG_TEMP_DELTA_8822B)\n#define BIT_CLEAR_REG_TEMP_DELTA_8822B(x) ((x) & (~BITS_REG_TEMP_DELTA_8822B))\n#define BIT_GET_REG_TEMP_DELTA_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_REG_TEMP_DELTA_8822B) &                             \\\n\t BIT_MASK_REG_TEMP_DELTA_8822B)\n#define BIT_SET_REG_TEMP_DELTA_8822B(x, v)                                     \\\n\t(BIT_CLEAR_REG_TEMP_DELTA_8822B(x) | BIT_REG_TEMP_DELTA_8822B(v))\n\n#define BIT_REG_TMETER_EN_8822B BIT(0)\n\n/* 2 REG_OSC_32K_CTRL_8822B */\n\n#define BIT_SHIFT_OSC_32K_CLKGEN_0_8822B 16\n#define BIT_MASK_OSC_32K_CLKGEN_0_8822B 0xffff\n#define BIT_OSC_32K_CLKGEN_0_8822B(x)                                          \\\n\t(((x) & BIT_MASK_OSC_32K_CLKGEN_0_8822B)                               \\\n\t << BIT_SHIFT_OSC_32K_CLKGEN_0_8822B)\n#define BITS_OSC_32K_CLKGEN_0_8822B                                            \\\n\t(BIT_MASK_OSC_32K_CLKGEN_0_8822B << BIT_SHIFT_OSC_32K_CLKGEN_0_8822B)\n#define BIT_CLEAR_OSC_32K_CLKGEN_0_8822B(x)                                    \\\n\t((x) & (~BITS_OSC_32K_CLKGEN_0_8822B))\n#define BIT_GET_OSC_32K_CLKGEN_0_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8822B) &                           \\\n\t BIT_MASK_OSC_32K_CLKGEN_0_8822B)\n#define BIT_SET_OSC_32K_CLKGEN_0_8822B(x, v)                                   \\\n\t(BIT_CLEAR_OSC_32K_CLKGEN_0_8822B(x) | BIT_OSC_32K_CLKGEN_0_8822B(v))\n\n#define BIT_SHIFT_OSC_32K_RES_COMP_8822B 4\n#define BIT_MASK_OSC_32K_RES_COMP_8822B 0x3\n#define BIT_OSC_32K_RES_COMP_8822B(x)                                          \\\n\t(((x) & BIT_MASK_OSC_32K_RES_COMP_8822B)                               \\\n\t << BIT_SHIFT_OSC_32K_RES_COMP_8822B)\n#define BITS_OSC_32K_RES_COMP_8822B                                            \\\n\t(BIT_MASK_OSC_32K_RES_COMP_8822B << BIT_SHIFT_OSC_32K_RES_COMP_8822B)\n#define BIT_CLEAR_OSC_32K_RES_COMP_8822B(x)                                    \\\n\t((x) & (~BITS_OSC_32K_RES_COMP_8822B))\n#define BIT_GET_OSC_32K_RES_COMP_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8822B) &                           \\\n\t BIT_MASK_OSC_32K_RES_COMP_8822B)\n#define BIT_SET_OSC_32K_RES_COMP_8822B(x, v)                                   \\\n\t(BIT_CLEAR_OSC_32K_RES_COMP_8822B(x) | BIT_OSC_32K_RES_COMP_8822B(v))\n\n#define BIT_OSC_32K_OUT_SEL_8822B BIT(3)\n#define BIT_ISO_WL_2_OSC_32K_8822B BIT(1)\n#define BIT_POW_CKGEN_8822B BIT(0)\n\n/* 2 REG_32K_CAL_REG1_8822B */\n#define BIT_CAL_32K_REG_WR_8822B BIT(31)\n#define BIT_CAL_32K_DBG_SEL_8822B BIT(22)\n\n#define BIT_SHIFT_CAL_32K_REG_ADDR_8822B 16\n#define BIT_MASK_CAL_32K_REG_ADDR_8822B 0x3f\n#define BIT_CAL_32K_REG_ADDR_8822B(x)                                          \\\n\t(((x) & BIT_MASK_CAL_32K_REG_ADDR_8822B)                               \\\n\t << BIT_SHIFT_CAL_32K_REG_ADDR_8822B)\n#define BITS_CAL_32K_REG_ADDR_8822B                                            \\\n\t(BIT_MASK_CAL_32K_REG_ADDR_8822B << BIT_SHIFT_CAL_32K_REG_ADDR_8822B)\n#define BIT_CLEAR_CAL_32K_REG_ADDR_8822B(x)                                    \\\n\t((x) & (~BITS_CAL_32K_REG_ADDR_8822B))\n#define BIT_GET_CAL_32K_REG_ADDR_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8822B) &                           \\\n\t BIT_MASK_CAL_32K_REG_ADDR_8822B)\n#define BIT_SET_CAL_32K_REG_ADDR_8822B(x, v)                                   \\\n\t(BIT_CLEAR_CAL_32K_REG_ADDR_8822B(x) | BIT_CAL_32K_REG_ADDR_8822B(v))\n\n#define BIT_SHIFT_CAL_32K_REG_DATA_8822B 0\n#define BIT_MASK_CAL_32K_REG_DATA_8822B 0xffff\n#define BIT_CAL_32K_REG_DATA_8822B(x)                                          \\\n\t(((x) & BIT_MASK_CAL_32K_REG_DATA_8822B)                               \\\n\t << BIT_SHIFT_CAL_32K_REG_DATA_8822B)\n#define BITS_CAL_32K_REG_DATA_8822B                                            \\\n\t(BIT_MASK_CAL_32K_REG_DATA_8822B << BIT_SHIFT_CAL_32K_REG_DATA_8822B)\n#define BIT_CLEAR_CAL_32K_REG_DATA_8822B(x)                                    \\\n\t((x) & (~BITS_CAL_32K_REG_DATA_8822B))\n#define BIT_GET_CAL_32K_REG_DATA_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8822B) &                           \\\n\t BIT_MASK_CAL_32K_REG_DATA_8822B)\n#define BIT_SET_CAL_32K_REG_DATA_8822B(x, v)                                   \\\n\t(BIT_CLEAR_CAL_32K_REG_DATA_8822B(x) | BIT_CAL_32K_REG_DATA_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_C2HEVT_8822B */\n\n#define BIT_SHIFT_C2HEVT_MSG_V1_8822B 0\n#define BIT_MASK_C2HEVT_MSG_V1_8822B 0xffffffffL\n#define BIT_C2HEVT_MSG_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_V1_8822B) << BIT_SHIFT_C2HEVT_MSG_V1_8822B)\n#define BITS_C2HEVT_MSG_V1_8822B                                               \\\n\t(BIT_MASK_C2HEVT_MSG_V1_8822B << BIT_SHIFT_C2HEVT_MSG_V1_8822B)\n#define BIT_CLEAR_C2HEVT_MSG_V1_8822B(x) ((x) & (~BITS_C2HEVT_MSG_V1_8822B))\n#define BIT_GET_C2HEVT_MSG_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8822B) & BIT_MASK_C2HEVT_MSG_V1_8822B)\n#define BIT_SET_C2HEVT_MSG_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_C2HEVT_MSG_V1_8822B(x) | BIT_C2HEVT_MSG_V1_8822B(v))\n\n/* 2 REG_C2HEVT_1_8822B */\n\n#define BIT_SHIFT_C2HEVT_MSG_1_8822B 0\n#define BIT_MASK_C2HEVT_MSG_1_8822B 0xffffffffL\n#define BIT_C2HEVT_MSG_1_8822B(x)                                              \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_1_8822B) << BIT_SHIFT_C2HEVT_MSG_1_8822B)\n#define BITS_C2HEVT_MSG_1_8822B                                                \\\n\t(BIT_MASK_C2HEVT_MSG_1_8822B << BIT_SHIFT_C2HEVT_MSG_1_8822B)\n#define BIT_CLEAR_C2HEVT_MSG_1_8822B(x) ((x) & (~BITS_C2HEVT_MSG_1_8822B))\n#define BIT_GET_C2HEVT_MSG_1_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_1_8822B) & BIT_MASK_C2HEVT_MSG_1_8822B)\n#define BIT_SET_C2HEVT_MSG_1_8822B(x, v)                                       \\\n\t(BIT_CLEAR_C2HEVT_MSG_1_8822B(x) | BIT_C2HEVT_MSG_1_8822B(v))\n\n/* 2 REG_C2HEVT_2_8822B */\n\n#define BIT_SHIFT_C2HEVT_MSG_2_8822B 0\n#define BIT_MASK_C2HEVT_MSG_2_8822B 0xffffffffL\n#define BIT_C2HEVT_MSG_2_8822B(x)                                              \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_2_8822B) << BIT_SHIFT_C2HEVT_MSG_2_8822B)\n#define BITS_C2HEVT_MSG_2_8822B                                                \\\n\t(BIT_MASK_C2HEVT_MSG_2_8822B << BIT_SHIFT_C2HEVT_MSG_2_8822B)\n#define BIT_CLEAR_C2HEVT_MSG_2_8822B(x) ((x) & (~BITS_C2HEVT_MSG_2_8822B))\n#define BIT_GET_C2HEVT_MSG_2_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_2_8822B) & BIT_MASK_C2HEVT_MSG_2_8822B)\n#define BIT_SET_C2HEVT_MSG_2_8822B(x, v)                                       \\\n\t(BIT_CLEAR_C2HEVT_MSG_2_8822B(x) | BIT_C2HEVT_MSG_2_8822B(v))\n\n/* 2 REG_C2HEVT_3_8822B */\n\n#define BIT_SHIFT_C2HEVT_MSG_3_8822B 0\n#define BIT_MASK_C2HEVT_MSG_3_8822B 0xffffffffL\n#define BIT_C2HEVT_MSG_3_8822B(x)                                              \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_3_8822B) << BIT_SHIFT_C2HEVT_MSG_3_8822B)\n#define BITS_C2HEVT_MSG_3_8822B                                                \\\n\t(BIT_MASK_C2HEVT_MSG_3_8822B << BIT_SHIFT_C2HEVT_MSG_3_8822B)\n#define BIT_CLEAR_C2HEVT_MSG_3_8822B(x) ((x) & (~BITS_C2HEVT_MSG_3_8822B))\n#define BIT_GET_C2HEVT_MSG_3_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_3_8822B) & BIT_MASK_C2HEVT_MSG_3_8822B)\n#define BIT_SET_C2HEVT_MSG_3_8822B(x, v)                                       \\\n\t(BIT_CLEAR_C2HEVT_MSG_3_8822B(x) | BIT_C2HEVT_MSG_3_8822B(v))\n\n/* 2 REG_SW_DEFINED_PAGE1_8822B */\n\n#define BIT_SHIFT_SW_DEFINED_PAGE1_8822B 0\n#define BIT_MASK_SW_DEFINED_PAGE1_8822B 0xffffffffffffffffL\n#define BIT_SW_DEFINED_PAGE1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_SW_DEFINED_PAGE1_8822B)                               \\\n\t << BIT_SHIFT_SW_DEFINED_PAGE1_8822B)\n#define BITS_SW_DEFINED_PAGE1_8822B                                            \\\n\t(BIT_MASK_SW_DEFINED_PAGE1_8822B << BIT_SHIFT_SW_DEFINED_PAGE1_8822B)\n#define BIT_CLEAR_SW_DEFINED_PAGE1_8822B(x)                                    \\\n\t((x) & (~BITS_SW_DEFINED_PAGE1_8822B))\n#define BIT_GET_SW_DEFINED_PAGE1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8822B) &                           \\\n\t BIT_MASK_SW_DEFINED_PAGE1_8822B)\n#define BIT_SET_SW_DEFINED_PAGE1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_SW_DEFINED_PAGE1_8822B(x) | BIT_SW_DEFINED_PAGE1_8822B(v))\n\n/* 2 REG_MCUTST_I_8822B */\n\n#define BIT_SHIFT_MCUDMSG_I_8822B 0\n#define BIT_MASK_MCUDMSG_I_8822B 0xffffffffL\n#define BIT_MCUDMSG_I_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_MCUDMSG_I_8822B) << BIT_SHIFT_MCUDMSG_I_8822B)\n#define BITS_MCUDMSG_I_8822B                                                   \\\n\t(BIT_MASK_MCUDMSG_I_8822B << BIT_SHIFT_MCUDMSG_I_8822B)\n#define BIT_CLEAR_MCUDMSG_I_8822B(x) ((x) & (~BITS_MCUDMSG_I_8822B))\n#define BIT_GET_MCUDMSG_I_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_MCUDMSG_I_8822B) & BIT_MASK_MCUDMSG_I_8822B)\n#define BIT_SET_MCUDMSG_I_8822B(x, v)                                          \\\n\t(BIT_CLEAR_MCUDMSG_I_8822B(x) | BIT_MCUDMSG_I_8822B(v))\n\n/* 2 REG_MCUTST_II_8822B */\n\n#define BIT_SHIFT_MCUDMSG_II_8822B 0\n#define BIT_MASK_MCUDMSG_II_8822B 0xffffffffL\n#define BIT_MCUDMSG_II_8822B(x)                                                \\\n\t(((x) & BIT_MASK_MCUDMSG_II_8822B) << BIT_SHIFT_MCUDMSG_II_8822B)\n#define BITS_MCUDMSG_II_8822B                                                  \\\n\t(BIT_MASK_MCUDMSG_II_8822B << BIT_SHIFT_MCUDMSG_II_8822B)\n#define BIT_CLEAR_MCUDMSG_II_8822B(x) ((x) & (~BITS_MCUDMSG_II_8822B))\n#define BIT_GET_MCUDMSG_II_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_MCUDMSG_II_8822B) & BIT_MASK_MCUDMSG_II_8822B)\n#define BIT_SET_MCUDMSG_II_8822B(x, v)                                         \\\n\t(BIT_CLEAR_MCUDMSG_II_8822B(x) | BIT_MCUDMSG_II_8822B(v))\n\n/* 2 REG_FMETHR_8822B */\n#define BIT_FMSG_INT_8822B BIT(31)\n\n#define BIT_SHIFT_FW_MSG_8822B 0\n#define BIT_MASK_FW_MSG_8822B 0xffffffffL\n#define BIT_FW_MSG_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_FW_MSG_8822B) << BIT_SHIFT_FW_MSG_8822B)\n#define BITS_FW_MSG_8822B (BIT_MASK_FW_MSG_8822B << BIT_SHIFT_FW_MSG_8822B)\n#define BIT_CLEAR_FW_MSG_8822B(x) ((x) & (~BITS_FW_MSG_8822B))\n#define BIT_GET_FW_MSG_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_FW_MSG_8822B) & BIT_MASK_FW_MSG_8822B)\n#define BIT_SET_FW_MSG_8822B(x, v)                                             \\\n\t(BIT_CLEAR_FW_MSG_8822B(x) | BIT_FW_MSG_8822B(v))\n\n/* 2 REG_HMETFR_8822B */\n\n#define BIT_SHIFT_HRCV_MSG_8822B 24\n#define BIT_MASK_HRCV_MSG_8822B 0xff\n#define BIT_HRCV_MSG_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_HRCV_MSG_8822B) << BIT_SHIFT_HRCV_MSG_8822B)\n#define BITS_HRCV_MSG_8822B                                                    \\\n\t(BIT_MASK_HRCV_MSG_8822B << BIT_SHIFT_HRCV_MSG_8822B)\n#define BIT_CLEAR_HRCV_MSG_8822B(x) ((x) & (~BITS_HRCV_MSG_8822B))\n#define BIT_GET_HRCV_MSG_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_HRCV_MSG_8822B) & BIT_MASK_HRCV_MSG_8822B)\n#define BIT_SET_HRCV_MSG_8822B(x, v)                                           \\\n\t(BIT_CLEAR_HRCV_MSG_8822B(x) | BIT_HRCV_MSG_8822B(v))\n\n#define BIT_INT_BOX3_8822B BIT(3)\n#define BIT_INT_BOX2_8822B BIT(2)\n#define BIT_INT_BOX1_8822B BIT(1)\n#define BIT_INT_BOX0_8822B BIT(0)\n\n/* 2 REG_HMEBOX0_8822B */\n\n#define BIT_SHIFT_HOST_MSG_0_8822B 0\n#define BIT_MASK_HOST_MSG_0_8822B 0xffffffffL\n#define BIT_HOST_MSG_0_8822B(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_0_8822B) << BIT_SHIFT_HOST_MSG_0_8822B)\n#define BITS_HOST_MSG_0_8822B                                                  \\\n\t(BIT_MASK_HOST_MSG_0_8822B << BIT_SHIFT_HOST_MSG_0_8822B)\n#define BIT_CLEAR_HOST_MSG_0_8822B(x) ((x) & (~BITS_HOST_MSG_0_8822B))\n#define BIT_GET_HOST_MSG_0_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_0_8822B) & BIT_MASK_HOST_MSG_0_8822B)\n#define BIT_SET_HOST_MSG_0_8822B(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_0_8822B(x) | BIT_HOST_MSG_0_8822B(v))\n\n/* 2 REG_HMEBOX1_8822B */\n\n#define BIT_SHIFT_HOST_MSG_1_8822B 0\n#define BIT_MASK_HOST_MSG_1_8822B 0xffffffffL\n#define BIT_HOST_MSG_1_8822B(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_1_8822B) << BIT_SHIFT_HOST_MSG_1_8822B)\n#define BITS_HOST_MSG_1_8822B                                                  \\\n\t(BIT_MASK_HOST_MSG_1_8822B << BIT_SHIFT_HOST_MSG_1_8822B)\n#define BIT_CLEAR_HOST_MSG_1_8822B(x) ((x) & (~BITS_HOST_MSG_1_8822B))\n#define BIT_GET_HOST_MSG_1_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_1_8822B) & BIT_MASK_HOST_MSG_1_8822B)\n#define BIT_SET_HOST_MSG_1_8822B(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_1_8822B(x) | BIT_HOST_MSG_1_8822B(v))\n\n/* 2 REG_HMEBOX2_8822B */\n\n#define BIT_SHIFT_HOST_MSG_2_8822B 0\n#define BIT_MASK_HOST_MSG_2_8822B 0xffffffffL\n#define BIT_HOST_MSG_2_8822B(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_2_8822B) << BIT_SHIFT_HOST_MSG_2_8822B)\n#define BITS_HOST_MSG_2_8822B                                                  \\\n\t(BIT_MASK_HOST_MSG_2_8822B << BIT_SHIFT_HOST_MSG_2_8822B)\n#define BIT_CLEAR_HOST_MSG_2_8822B(x) ((x) & (~BITS_HOST_MSG_2_8822B))\n#define BIT_GET_HOST_MSG_2_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_2_8822B) & BIT_MASK_HOST_MSG_2_8822B)\n#define BIT_SET_HOST_MSG_2_8822B(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_2_8822B(x) | BIT_HOST_MSG_2_8822B(v))\n\n/* 2 REG_HMEBOX3_8822B */\n\n#define BIT_SHIFT_HOST_MSG_3_8822B 0\n#define BIT_MASK_HOST_MSG_3_8822B 0xffffffffL\n#define BIT_HOST_MSG_3_8822B(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_3_8822B) << BIT_SHIFT_HOST_MSG_3_8822B)\n#define BITS_HOST_MSG_3_8822B                                                  \\\n\t(BIT_MASK_HOST_MSG_3_8822B << BIT_SHIFT_HOST_MSG_3_8822B)\n#define BIT_CLEAR_HOST_MSG_3_8822B(x) ((x) & (~BITS_HOST_MSG_3_8822B))\n#define BIT_GET_HOST_MSG_3_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_3_8822B) & BIT_MASK_HOST_MSG_3_8822B)\n#define BIT_SET_HOST_MSG_3_8822B(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_3_8822B(x) | BIT_HOST_MSG_3_8822B(v))\n\n/* 2 REG_LLT_INIT_8822B */\n\n#define BIT_SHIFT_LLTE_RWM_8822B 30\n#define BIT_MASK_LLTE_RWM_8822B 0x3\n#define BIT_LLTE_RWM_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_LLTE_RWM_8822B) << BIT_SHIFT_LLTE_RWM_8822B)\n#define BITS_LLTE_RWM_8822B                                                    \\\n\t(BIT_MASK_LLTE_RWM_8822B << BIT_SHIFT_LLTE_RWM_8822B)\n#define BIT_CLEAR_LLTE_RWM_8822B(x) ((x) & (~BITS_LLTE_RWM_8822B))\n#define BIT_GET_LLTE_RWM_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_LLTE_RWM_8822B) & BIT_MASK_LLTE_RWM_8822B)\n#define BIT_SET_LLTE_RWM_8822B(x, v)                                           \\\n\t(BIT_CLEAR_LLTE_RWM_8822B(x) | BIT_LLTE_RWM_8822B(v))\n\n#define BIT_SHIFT_LLTINI_PDATA_V1_8822B 16\n#define BIT_MASK_LLTINI_PDATA_V1_8822B 0xfff\n#define BIT_LLTINI_PDATA_V1_8822B(x)                                           \\\n\t(((x) & BIT_MASK_LLTINI_PDATA_V1_8822B)                                \\\n\t << BIT_SHIFT_LLTINI_PDATA_V1_8822B)\n#define BITS_LLTINI_PDATA_V1_8822B                                             \\\n\t(BIT_MASK_LLTINI_PDATA_V1_8822B << BIT_SHIFT_LLTINI_PDATA_V1_8822B)\n#define BIT_CLEAR_LLTINI_PDATA_V1_8822B(x) ((x) & (~BITS_LLTINI_PDATA_V1_8822B))\n#define BIT_GET_LLTINI_PDATA_V1_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8822B) &                            \\\n\t BIT_MASK_LLTINI_PDATA_V1_8822B)\n#define BIT_SET_LLTINI_PDATA_V1_8822B(x, v)                                    \\\n\t(BIT_CLEAR_LLTINI_PDATA_V1_8822B(x) | BIT_LLTINI_PDATA_V1_8822B(v))\n\n#define BIT_SHIFT_LLTINI_HDATA_V1_8822B 0\n#define BIT_MASK_LLTINI_HDATA_V1_8822B 0xfff\n#define BIT_LLTINI_HDATA_V1_8822B(x)                                           \\\n\t(((x) & BIT_MASK_LLTINI_HDATA_V1_8822B)                                \\\n\t << BIT_SHIFT_LLTINI_HDATA_V1_8822B)\n#define BITS_LLTINI_HDATA_V1_8822B                                             \\\n\t(BIT_MASK_LLTINI_HDATA_V1_8822B << BIT_SHIFT_LLTINI_HDATA_V1_8822B)\n#define BIT_CLEAR_LLTINI_HDATA_V1_8822B(x) ((x) & (~BITS_LLTINI_HDATA_V1_8822B))\n#define BIT_GET_LLTINI_HDATA_V1_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8822B) &                            \\\n\t BIT_MASK_LLTINI_HDATA_V1_8822B)\n#define BIT_SET_LLTINI_HDATA_V1_8822B(x, v)                                    \\\n\t(BIT_CLEAR_LLTINI_HDATA_V1_8822B(x) | BIT_LLTINI_HDATA_V1_8822B(v))\n\n/* 2 REG_LLT_INIT_ADDR_8822B */\n\n#define BIT_SHIFT_LLTINI_ADDR_V1_8822B 0\n#define BIT_MASK_LLTINI_ADDR_V1_8822B 0xfff\n#define BIT_LLTINI_ADDR_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_LLTINI_ADDR_V1_8822B)                                 \\\n\t << BIT_SHIFT_LLTINI_ADDR_V1_8822B)\n#define BITS_LLTINI_ADDR_V1_8822B                                              \\\n\t(BIT_MASK_LLTINI_ADDR_V1_8822B << BIT_SHIFT_LLTINI_ADDR_V1_8822B)\n#define BIT_CLEAR_LLTINI_ADDR_V1_8822B(x) ((x) & (~BITS_LLTINI_ADDR_V1_8822B))\n#define BIT_GET_LLTINI_ADDR_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8822B) &                             \\\n\t BIT_MASK_LLTINI_ADDR_V1_8822B)\n#define BIT_SET_LLTINI_ADDR_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_LLTINI_ADDR_V1_8822B(x) | BIT_LLTINI_ADDR_V1_8822B(v))\n\n/* 2 REG_BB_ACCESS_CTRL_8822B */\n\n#define BIT_SHIFT_BB_WRITE_READ_8822B 30\n#define BIT_MASK_BB_WRITE_READ_8822B 0x3\n#define BIT_BB_WRITE_READ_8822B(x)                                             \\\n\t(((x) & BIT_MASK_BB_WRITE_READ_8822B) << BIT_SHIFT_BB_WRITE_READ_8822B)\n#define BITS_BB_WRITE_READ_8822B                                               \\\n\t(BIT_MASK_BB_WRITE_READ_8822B << BIT_SHIFT_BB_WRITE_READ_8822B)\n#define BIT_CLEAR_BB_WRITE_READ_8822B(x) ((x) & (~BITS_BB_WRITE_READ_8822B))\n#define BIT_GET_BB_WRITE_READ_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_BB_WRITE_READ_8822B) & BIT_MASK_BB_WRITE_READ_8822B)\n#define BIT_SET_BB_WRITE_READ_8822B(x, v)                                      \\\n\t(BIT_CLEAR_BB_WRITE_READ_8822B(x) | BIT_BB_WRITE_READ_8822B(v))\n\n#define BIT_SHIFT_BB_WRITE_EN_8822B 12\n#define BIT_MASK_BB_WRITE_EN_8822B 0xf\n#define BIT_BB_WRITE_EN_8822B(x)                                               \\\n\t(((x) & BIT_MASK_BB_WRITE_EN_8822B) << BIT_SHIFT_BB_WRITE_EN_8822B)\n#define BITS_BB_WRITE_EN_8822B                                                 \\\n\t(BIT_MASK_BB_WRITE_EN_8822B << BIT_SHIFT_BB_WRITE_EN_8822B)\n#define BIT_CLEAR_BB_WRITE_EN_8822B(x) ((x) & (~BITS_BB_WRITE_EN_8822B))\n#define BIT_GET_BB_WRITE_EN_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_BB_WRITE_EN_8822B) & BIT_MASK_BB_WRITE_EN_8822B)\n#define BIT_SET_BB_WRITE_EN_8822B(x, v)                                        \\\n\t(BIT_CLEAR_BB_WRITE_EN_8822B(x) | BIT_BB_WRITE_EN_8822B(v))\n\n#define BIT_SHIFT_BB_ADDR_8822B 2\n#define BIT_MASK_BB_ADDR_8822B 0x1ff\n#define BIT_BB_ADDR_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_BB_ADDR_8822B) << BIT_SHIFT_BB_ADDR_8822B)\n#define BITS_BB_ADDR_8822B (BIT_MASK_BB_ADDR_8822B << BIT_SHIFT_BB_ADDR_8822B)\n#define BIT_CLEAR_BB_ADDR_8822B(x) ((x) & (~BITS_BB_ADDR_8822B))\n#define BIT_GET_BB_ADDR_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_BB_ADDR_8822B) & BIT_MASK_BB_ADDR_8822B)\n#define BIT_SET_BB_ADDR_8822B(x, v)                                            \\\n\t(BIT_CLEAR_BB_ADDR_8822B(x) | BIT_BB_ADDR_8822B(v))\n\n#define BIT_BB_ERRACC_8822B BIT(0)\n\n/* 2 REG_BB_ACCESS_DATA_8822B */\n\n#define BIT_SHIFT_BB_DATA_8822B 0\n#define BIT_MASK_BB_DATA_8822B 0xffffffffL\n#define BIT_BB_DATA_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_BB_DATA_8822B) << BIT_SHIFT_BB_DATA_8822B)\n#define BITS_BB_DATA_8822B (BIT_MASK_BB_DATA_8822B << BIT_SHIFT_BB_DATA_8822B)\n#define BIT_CLEAR_BB_DATA_8822B(x) ((x) & (~BITS_BB_DATA_8822B))\n#define BIT_GET_BB_DATA_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_BB_DATA_8822B) & BIT_MASK_BB_DATA_8822B)\n#define BIT_SET_BB_DATA_8822B(x, v)                                            \\\n\t(BIT_CLEAR_BB_DATA_8822B(x) | BIT_BB_DATA_8822B(v))\n\n/* 2 REG_HMEBOX_E0_8822B */\n\n#define BIT_SHIFT_HMEBOX_E0_8822B 0\n#define BIT_MASK_HMEBOX_E0_8822B 0xffffffffL\n#define BIT_HMEBOX_E0_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E0_8822B) << BIT_SHIFT_HMEBOX_E0_8822B)\n#define BITS_HMEBOX_E0_8822B                                                   \\\n\t(BIT_MASK_HMEBOX_E0_8822B << BIT_SHIFT_HMEBOX_E0_8822B)\n#define BIT_CLEAR_HMEBOX_E0_8822B(x) ((x) & (~BITS_HMEBOX_E0_8822B))\n#define BIT_GET_HMEBOX_E0_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E0_8822B) & BIT_MASK_HMEBOX_E0_8822B)\n#define BIT_SET_HMEBOX_E0_8822B(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E0_8822B(x) | BIT_HMEBOX_E0_8822B(v))\n\n/* 2 REG_HMEBOX_E1_8822B */\n\n#define BIT_SHIFT_HMEBOX_E1_8822B 0\n#define BIT_MASK_HMEBOX_E1_8822B 0xffffffffL\n#define BIT_HMEBOX_E1_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E1_8822B) << BIT_SHIFT_HMEBOX_E1_8822B)\n#define BITS_HMEBOX_E1_8822B                                                   \\\n\t(BIT_MASK_HMEBOX_E1_8822B << BIT_SHIFT_HMEBOX_E1_8822B)\n#define BIT_CLEAR_HMEBOX_E1_8822B(x) ((x) & (~BITS_HMEBOX_E1_8822B))\n#define BIT_GET_HMEBOX_E1_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E1_8822B) & BIT_MASK_HMEBOX_E1_8822B)\n#define BIT_SET_HMEBOX_E1_8822B(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E1_8822B(x) | BIT_HMEBOX_E1_8822B(v))\n\n/* 2 REG_HMEBOX_E2_8822B */\n\n#define BIT_SHIFT_HMEBOX_E2_8822B 0\n#define BIT_MASK_HMEBOX_E2_8822B 0xffffffffL\n#define BIT_HMEBOX_E2_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E2_8822B) << BIT_SHIFT_HMEBOX_E2_8822B)\n#define BITS_HMEBOX_E2_8822B                                                   \\\n\t(BIT_MASK_HMEBOX_E2_8822B << BIT_SHIFT_HMEBOX_E2_8822B)\n#define BIT_CLEAR_HMEBOX_E2_8822B(x) ((x) & (~BITS_HMEBOX_E2_8822B))\n#define BIT_GET_HMEBOX_E2_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E2_8822B) & BIT_MASK_HMEBOX_E2_8822B)\n#define BIT_SET_HMEBOX_E2_8822B(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E2_8822B(x) | BIT_HMEBOX_E2_8822B(v))\n\n/* 2 REG_HMEBOX_E3_8822B */\n\n#define BIT_SHIFT_HMEBOX_E3_8822B 0\n#define BIT_MASK_HMEBOX_E3_8822B 0xffffffffL\n#define BIT_HMEBOX_E3_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E3_8822B) << BIT_SHIFT_HMEBOX_E3_8822B)\n#define BITS_HMEBOX_E3_8822B                                                   \\\n\t(BIT_MASK_HMEBOX_E3_8822B << BIT_SHIFT_HMEBOX_E3_8822B)\n#define BIT_CLEAR_HMEBOX_E3_8822B(x) ((x) & (~BITS_HMEBOX_E3_8822B))\n#define BIT_GET_HMEBOX_E3_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E3_8822B) & BIT_MASK_HMEBOX_E3_8822B)\n#define BIT_SET_HMEBOX_E3_8822B(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E3_8822B(x) | BIT_HMEBOX_E3_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_CR_EXT_8822B */\n\n#define BIT_SHIFT_PHY_REQ_DELAY_8822B 24\n#define BIT_MASK_PHY_REQ_DELAY_8822B 0xf\n#define BIT_PHY_REQ_DELAY_8822B(x)                                             \\\n\t(((x) & BIT_MASK_PHY_REQ_DELAY_8822B) << BIT_SHIFT_PHY_REQ_DELAY_8822B)\n#define BITS_PHY_REQ_DELAY_8822B                                               \\\n\t(BIT_MASK_PHY_REQ_DELAY_8822B << BIT_SHIFT_PHY_REQ_DELAY_8822B)\n#define BIT_CLEAR_PHY_REQ_DELAY_8822B(x) ((x) & (~BITS_PHY_REQ_DELAY_8822B))\n#define BIT_GET_PHY_REQ_DELAY_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PHY_REQ_DELAY_8822B) & BIT_MASK_PHY_REQ_DELAY_8822B)\n#define BIT_SET_PHY_REQ_DELAY_8822B(x, v)                                      \\\n\t(BIT_CLEAR_PHY_REQ_DELAY_8822B(x) | BIT_PHY_REQ_DELAY_8822B(v))\n\n#define BIT_SPD_DOWN_8822B BIT(16)\n\n#define BIT_SHIFT_NETYPE4_8822B 4\n#define BIT_MASK_NETYPE4_8822B 0x3\n#define BIT_NETYPE4_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE4_8822B) << BIT_SHIFT_NETYPE4_8822B)\n#define BITS_NETYPE4_8822B (BIT_MASK_NETYPE4_8822B << BIT_SHIFT_NETYPE4_8822B)\n#define BIT_CLEAR_NETYPE4_8822B(x) ((x) & (~BITS_NETYPE4_8822B))\n#define BIT_GET_NETYPE4_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE4_8822B) & BIT_MASK_NETYPE4_8822B)\n#define BIT_SET_NETYPE4_8822B(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE4_8822B(x) | BIT_NETYPE4_8822B(v))\n\n#define BIT_SHIFT_NETYPE3_8822B 2\n#define BIT_MASK_NETYPE3_8822B 0x3\n#define BIT_NETYPE3_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE3_8822B) << BIT_SHIFT_NETYPE3_8822B)\n#define BITS_NETYPE3_8822B (BIT_MASK_NETYPE3_8822B << BIT_SHIFT_NETYPE3_8822B)\n#define BIT_CLEAR_NETYPE3_8822B(x) ((x) & (~BITS_NETYPE3_8822B))\n#define BIT_GET_NETYPE3_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE3_8822B) & BIT_MASK_NETYPE3_8822B)\n#define BIT_SET_NETYPE3_8822B(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE3_8822B(x) | BIT_NETYPE3_8822B(v))\n\n#define BIT_SHIFT_NETYPE2_8822B 0\n#define BIT_MASK_NETYPE2_8822B 0x3\n#define BIT_NETYPE2_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE2_8822B) << BIT_SHIFT_NETYPE2_8822B)\n#define BITS_NETYPE2_8822B (BIT_MASK_NETYPE2_8822B << BIT_SHIFT_NETYPE2_8822B)\n#define BIT_CLEAR_NETYPE2_8822B(x) ((x) & (~BITS_NETYPE2_8822B))\n#define BIT_GET_NETYPE2_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE2_8822B) & BIT_MASK_NETYPE2_8822B)\n#define BIT_SET_NETYPE2_8822B(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE2_8822B(x) | BIT_NETYPE2_8822B(v))\n\n/* 2 REG_FWFF_8822B */\n\n#define BIT_SHIFT_PKTNUM_TH_V1_8822B 24\n#define BIT_MASK_PKTNUM_TH_V1_8822B 0xff\n#define BIT_PKTNUM_TH_V1_8822B(x)                                              \\\n\t(((x) & BIT_MASK_PKTNUM_TH_V1_8822B) << BIT_SHIFT_PKTNUM_TH_V1_8822B)\n#define BITS_PKTNUM_TH_V1_8822B                                                \\\n\t(BIT_MASK_PKTNUM_TH_V1_8822B << BIT_SHIFT_PKTNUM_TH_V1_8822B)\n#define BIT_CLEAR_PKTNUM_TH_V1_8822B(x) ((x) & (~BITS_PKTNUM_TH_V1_8822B))\n#define BIT_GET_PKTNUM_TH_V1_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_PKTNUM_TH_V1_8822B) & BIT_MASK_PKTNUM_TH_V1_8822B)\n#define BIT_SET_PKTNUM_TH_V1_8822B(x, v)                                       \\\n\t(BIT_CLEAR_PKTNUM_TH_V1_8822B(x) | BIT_PKTNUM_TH_V1_8822B(v))\n\n#define BIT_SHIFT_TIMER_TH_8822B 16\n#define BIT_MASK_TIMER_TH_8822B 0xff\n#define BIT_TIMER_TH_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_TIMER_TH_8822B) << BIT_SHIFT_TIMER_TH_8822B)\n#define BITS_TIMER_TH_8822B                                                    \\\n\t(BIT_MASK_TIMER_TH_8822B << BIT_SHIFT_TIMER_TH_8822B)\n#define BIT_CLEAR_TIMER_TH_8822B(x) ((x) & (~BITS_TIMER_TH_8822B))\n#define BIT_GET_TIMER_TH_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TIMER_TH_8822B) & BIT_MASK_TIMER_TH_8822B)\n#define BIT_SET_TIMER_TH_8822B(x, v)                                           \\\n\t(BIT_CLEAR_TIMER_TH_8822B(x) | BIT_TIMER_TH_8822B(v))\n\n#define BIT_SHIFT_RXPKT1ENADDR_8822B 0\n#define BIT_MASK_RXPKT1ENADDR_8822B 0xffff\n#define BIT_RXPKT1ENADDR_8822B(x)                                              \\\n\t(((x) & BIT_MASK_RXPKT1ENADDR_8822B) << BIT_SHIFT_RXPKT1ENADDR_8822B)\n#define BITS_RXPKT1ENADDR_8822B                                                \\\n\t(BIT_MASK_RXPKT1ENADDR_8822B << BIT_SHIFT_RXPKT1ENADDR_8822B)\n#define BIT_CLEAR_RXPKT1ENADDR_8822B(x) ((x) & (~BITS_RXPKT1ENADDR_8822B))\n#define BIT_GET_RXPKT1ENADDR_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXPKT1ENADDR_8822B) & BIT_MASK_RXPKT1ENADDR_8822B)\n#define BIT_SET_RXPKT1ENADDR_8822B(x, v)                                       \\\n\t(BIT_CLEAR_RXPKT1ENADDR_8822B(x) | BIT_RXPKT1ENADDR_8822B(v))\n\n/* 2 REG_RXFF_PTR_V1_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n#define BIT_SHIFT_RXFF0_RDPTR_V2_8822B 0\n#define BIT_MASK_RXFF0_RDPTR_V2_8822B 0x3ffff\n#define BIT_RXFF0_RDPTR_V2_8822B(x)                                            \\\n\t(((x) & BIT_MASK_RXFF0_RDPTR_V2_8822B)                                 \\\n\t << BIT_SHIFT_RXFF0_RDPTR_V2_8822B)\n#define BITS_RXFF0_RDPTR_V2_8822B                                              \\\n\t(BIT_MASK_RXFF0_RDPTR_V2_8822B << BIT_SHIFT_RXFF0_RDPTR_V2_8822B)\n#define BIT_CLEAR_RXFF0_RDPTR_V2_8822B(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8822B))\n#define BIT_GET_RXFF0_RDPTR_V2_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8822B) &                             \\\n\t BIT_MASK_RXFF0_RDPTR_V2_8822B)\n#define BIT_SET_RXFF0_RDPTR_V2_8822B(x, v)                                     \\\n\t(BIT_CLEAR_RXFF0_RDPTR_V2_8822B(x) | BIT_RXFF0_RDPTR_V2_8822B(v))\n\n/* 2 REG_RXFF_WTR_V1_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n#define BIT_SHIFT_RXFF0_WTPTR_V2_8822B 0\n#define BIT_MASK_RXFF0_WTPTR_V2_8822B 0x3ffff\n#define BIT_RXFF0_WTPTR_V2_8822B(x)                                            \\\n\t(((x) & BIT_MASK_RXFF0_WTPTR_V2_8822B)                                 \\\n\t << BIT_SHIFT_RXFF0_WTPTR_V2_8822B)\n#define BITS_RXFF0_WTPTR_V2_8822B                                              \\\n\t(BIT_MASK_RXFF0_WTPTR_V2_8822B << BIT_SHIFT_RXFF0_WTPTR_V2_8822B)\n#define BIT_CLEAR_RXFF0_WTPTR_V2_8822B(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8822B))\n#define BIT_GET_RXFF0_WTPTR_V2_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8822B) &                             \\\n\t BIT_MASK_RXFF0_WTPTR_V2_8822B)\n#define BIT_SET_RXFF0_WTPTR_V2_8822B(x, v)                                     \\\n\t(BIT_CLEAR_RXFF0_WTPTR_V2_8822B(x) | BIT_RXFF0_WTPTR_V2_8822B(v))\n\n/* 2 REG_FE2IMR_8822B */\n#define BIT__FE4ISR__IND_MSK_8822B BIT(29)\n#define BIT_FS_TXSC_DESC_DONE_INT_EN_8822B BIT(28)\n#define BIT_FS_TXSC_BKDONE_INT_EN_8822B BIT(27)\n#define BIT_FS_TXSC_BEDONE_INT_EN_8822B BIT(26)\n#define BIT_FS_TXSC_VIDONE_INT_EN_8822B BIT(25)\n#define BIT_FS_TXSC_VODONE_INT_EN_8822B BIT(24)\n#define BIT_FS_ATIM_MB7_INT_EN_8822B BIT(23)\n#define BIT_FS_ATIM_MB6_INT_EN_8822B BIT(22)\n#define BIT_FS_ATIM_MB5_INT_EN_8822B BIT(21)\n#define BIT_FS_ATIM_MB4_INT_EN_8822B BIT(20)\n#define BIT_FS_ATIM_MB3_INT_EN_8822B BIT(19)\n#define BIT_FS_ATIM_MB2_INT_EN_8822B BIT(18)\n#define BIT_FS_ATIM_MB1_INT_EN_8822B BIT(17)\n#define BIT_FS_ATIM_MB0_INT_EN_8822B BIT(16)\n#define BIT_FS_TBTT4INT_EN_8822B BIT(11)\n#define BIT_FS_TBTT3INT_EN_8822B BIT(10)\n#define BIT_FS_TBTT2INT_EN_8822B BIT(9)\n#define BIT_FS_TBTT1INT_EN_8822B BIT(8)\n#define BIT_FS_TBTT0_MB7INT_EN_8822B BIT(7)\n#define BIT_FS_TBTT0_MB6INT_EN_8822B BIT(6)\n#define BIT_FS_TBTT0_MB5INT_EN_8822B BIT(5)\n#define BIT_FS_TBTT0_MB4INT_EN_8822B BIT(4)\n#define BIT_FS_TBTT0_MB3INT_EN_8822B BIT(3)\n#define BIT_FS_TBTT0_MB2INT_EN_8822B BIT(2)\n#define BIT_FS_TBTT0_MB1INT_EN_8822B BIT(1)\n#define BIT_FS_TBTT0_INT_EN_8822B BIT(0)\n\n/* 2 REG_FE2ISR_8822B */\n#define BIT__FE4ISR__IND_INT_8822B BIT(29)\n#define BIT_FS_TXSC_DESC_DONE_INT_8822B BIT(28)\n#define BIT_FS_TXSC_BKDONE_INT_8822B BIT(27)\n#define BIT_FS_TXSC_BEDONE_INT_8822B BIT(26)\n#define BIT_FS_TXSC_VIDONE_INT_8822B BIT(25)\n#define BIT_FS_TXSC_VODONE_INT_8822B BIT(24)\n#define BIT_FS_ATIM_MB7_INT_8822B BIT(23)\n#define BIT_FS_ATIM_MB6_INT_8822B BIT(22)\n#define BIT_FS_ATIM_MB5_INT_8822B BIT(21)\n#define BIT_FS_ATIM_MB4_INT_8822B BIT(20)\n#define BIT_FS_ATIM_MB3_INT_8822B BIT(19)\n#define BIT_FS_ATIM_MB2_INT_8822B BIT(18)\n#define BIT_FS_ATIM_MB1_INT_8822B BIT(17)\n#define BIT_FS_ATIM_MB0_INT_8822B BIT(16)\n#define BIT_FS_TBTT4INT_8822B BIT(11)\n#define BIT_FS_TBTT3INT_8822B BIT(10)\n#define BIT_FS_TBTT2INT_8822B BIT(9)\n#define BIT_FS_TBTT1INT_8822B BIT(8)\n#define BIT_FS_TBTT0_MB7INT_8822B BIT(7)\n#define BIT_FS_TBTT0_MB6INT_8822B BIT(6)\n#define BIT_FS_TBTT0_MB5INT_8822B BIT(5)\n#define BIT_FS_TBTT0_MB4INT_8822B BIT(4)\n#define BIT_FS_TBTT0_MB3INT_8822B BIT(3)\n#define BIT_FS_TBTT0_MB2INT_8822B BIT(2)\n#define BIT_FS_TBTT0_MB1INT_8822B BIT(1)\n#define BIT_FS_TBTT0_INT_8822B BIT(0)\n\n/* 2 REG_FE3IMR_8822B */\n#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN_8822B BIT(31)\n#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN_8822B BIT(30)\n#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN_8822B BIT(29)\n#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN_8822B BIT(28)\n#define BIT_FS_BCNDMA4_INT_EN_8822B BIT(27)\n#define BIT_FS_BCNDMA3_INT_EN_8822B BIT(26)\n#define BIT_FS_BCNDMA2_INT_EN_8822B BIT(25)\n#define BIT_FS_BCNDMA1_INT_EN_8822B BIT(24)\n#define BIT_FS_BCNDMA0_MB7_INT_EN_8822B BIT(23)\n#define BIT_FS_BCNDMA0_MB6_INT_EN_8822B BIT(22)\n#define BIT_FS_BCNDMA0_MB5_INT_EN_8822B BIT(21)\n#define BIT_FS_BCNDMA0_MB4_INT_EN_8822B BIT(20)\n#define BIT_FS_BCNDMA0_MB3_INT_EN_8822B BIT(19)\n#define BIT_FS_BCNDMA0_MB2_INT_EN_8822B BIT(18)\n#define BIT_FS_BCNDMA0_MB1_INT_EN_8822B BIT(17)\n#define BIT_FS_BCNDMA0_INT_EN_8822B BIT(16)\n#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8822B BIT(15)\n#define BIT_FS_BCNERLY4_INT_EN_8822B BIT(11)\n#define BIT_FS_BCNERLY3_INT_EN_8822B BIT(10)\n#define BIT_FS_BCNERLY2_INT_EN_8822B BIT(9)\n#define BIT_FS_BCNERLY1_INT_EN_8822B BIT(8)\n#define BIT_FS_BCNERLY0_MB7INT_EN_8822B BIT(7)\n#define BIT_FS_BCNERLY0_MB6INT_EN_8822B BIT(6)\n#define BIT_FS_BCNERLY0_MB5INT_EN_8822B BIT(5)\n#define BIT_FS_BCNERLY0_MB4INT_EN_8822B BIT(4)\n#define BIT_FS_BCNERLY0_MB3INT_EN_8822B BIT(3)\n#define BIT_FS_BCNERLY0_MB2INT_EN_8822B BIT(2)\n#define BIT_FS_BCNERLY0_MB1INT_EN_8822B BIT(1)\n#define BIT_FS_BCNERLY0_INT_EN_8822B BIT(0)\n\n/* 2 REG_FE3ISR_8822B */\n#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT_8822B BIT(31)\n#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT_8822B BIT(30)\n#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT_8822B BIT(29)\n#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT_8822B BIT(28)\n#define BIT_FS_BCNDMA4_INT_8822B BIT(27)\n#define BIT_FS_BCNDMA3_INT_8822B BIT(26)\n#define BIT_FS_BCNDMA2_INT_8822B BIT(25)\n#define BIT_FS_BCNDMA1_INT_8822B BIT(24)\n#define BIT_FS_BCNDMA0_MB7_INT_8822B BIT(23)\n#define BIT_FS_BCNDMA0_MB6_INT_8822B BIT(22)\n#define BIT_FS_BCNDMA0_MB5_INT_8822B BIT(21)\n#define BIT_FS_BCNDMA0_MB4_INT_8822B BIT(20)\n#define BIT_FS_BCNDMA0_MB3_INT_8822B BIT(19)\n#define BIT_FS_BCNDMA0_MB2_INT_8822B BIT(18)\n#define BIT_FS_BCNDMA0_MB1_INT_8822B BIT(17)\n#define BIT_FS_BCNDMA0_INT_8822B BIT(16)\n#define BIT_FS_MTI_BCNIVLEAR_INT_8822B BIT(15)\n#define BIT_FS_BCNERLY4_INT_8822B BIT(11)\n#define BIT_FS_BCNERLY3_INT_8822B BIT(10)\n#define BIT_FS_BCNERLY2_INT_8822B BIT(9)\n#define BIT_FS_BCNERLY1_INT_8822B BIT(8)\n#define BIT_FS_BCNERLY0_MB7INT_8822B BIT(7)\n#define BIT_FS_BCNERLY0_MB6INT_8822B BIT(6)\n#define BIT_FS_BCNERLY0_MB5INT_8822B BIT(5)\n#define BIT_FS_BCNERLY0_MB4INT_8822B BIT(4)\n#define BIT_FS_BCNERLY0_MB3INT_8822B BIT(3)\n#define BIT_FS_BCNERLY0_MB2INT_8822B BIT(2)\n#define BIT_FS_BCNERLY0_MB1INT_8822B BIT(1)\n#define BIT_FS_BCNERLY0_INT_8822B BIT(0)\n\n/* 2 REG_FE4IMR_8822B */\n#define BIT_FS_CLI3_TXPKTIN_INT_EN_8822B BIT(19)\n#define BIT_FS_CLI2_TXPKTIN_INT_EN_8822B BIT(18)\n#define BIT_FS_CLI1_TXPKTIN_INT_EN_8822B BIT(17)\n#define BIT_FS_CLI0_TXPKTIN_INT_EN_8822B BIT(16)\n#define BIT_FS_CLI3_RX_UMD0_INT_EN_8822B BIT(15)\n#define BIT_FS_CLI3_RX_UMD1_INT_EN_8822B BIT(14)\n#define BIT_FS_CLI3_RX_BMD0_INT_EN_8822B BIT(13)\n#define BIT_FS_CLI3_RX_BMD1_INT_EN_8822B BIT(12)\n#define BIT_FS_CLI2_RX_UMD0_INT_EN_8822B BIT(11)\n#define BIT_FS_CLI2_RX_UMD1_INT_EN_8822B BIT(10)\n#define BIT_FS_CLI2_RX_BMD0_INT_EN_8822B BIT(9)\n#define BIT_FS_CLI2_RX_BMD1_INT_EN_8822B BIT(8)\n#define BIT_FS_CLI1_RX_UMD0_INT_EN_8822B BIT(7)\n#define BIT_FS_CLI1_RX_UMD1_INT_EN_8822B BIT(6)\n#define BIT_FS_CLI1_RX_BMD0_INT_EN_8822B BIT(5)\n#define BIT_FS_CLI1_RX_BMD1_INT_EN_8822B BIT(4)\n#define BIT_FS_CLI0_RX_UMD0_INT_EN_8822B BIT(3)\n#define BIT_FS_CLI0_RX_UMD1_INT_EN_8822B BIT(2)\n#define BIT_FS_CLI0_RX_BMD0_INT_EN_8822B BIT(1)\n#define BIT_FS_CLI0_RX_BMD1_INT_EN_8822B BIT(0)\n\n/* 2 REG_FE4ISR_8822B */\n#define BIT_FS_CLI3_TXPKTIN_INT_8822B BIT(19)\n#define BIT_FS_CLI2_TXPKTIN_INT_8822B BIT(18)\n#define BIT_FS_CLI1_TXPKTIN_INT_8822B BIT(17)\n#define BIT_FS_CLI0_TXPKTIN_INT_8822B BIT(16)\n#define BIT_FS_CLI3_RX_UMD0_INT_8822B BIT(15)\n#define BIT_FS_CLI3_RX_UMD1_INT_8822B BIT(14)\n#define BIT_FS_CLI3_RX_BMD0_INT_8822B BIT(13)\n#define BIT_FS_CLI3_RX_BMD1_INT_8822B BIT(12)\n#define BIT_FS_CLI2_RX_UMD0_INT_8822B BIT(11)\n#define BIT_FS_CLI2_RX_UMD1_INT_8822B BIT(10)\n#define BIT_FS_CLI2_RX_BMD0_INT_8822B BIT(9)\n#define BIT_FS_CLI2_RX_BMD1_INT_8822B BIT(8)\n#define BIT_FS_CLI1_RX_UMD0_INT_8822B BIT(7)\n#define BIT_FS_CLI1_RX_UMD1_INT_8822B BIT(6)\n#define BIT_FS_CLI1_RX_BMD0_INT_8822B BIT(5)\n#define BIT_FS_CLI1_RX_BMD1_INT_8822B BIT(4)\n#define BIT_FS_CLI0_RX_UMD0_INT_8822B BIT(3)\n#define BIT_FS_CLI0_RX_UMD1_INT_8822B BIT(2)\n#define BIT_FS_CLI0_RX_BMD0_INT_8822B BIT(1)\n#define BIT_FS_CLI0_RX_BMD1_INT_8822B BIT(0)\n\n/* 2 REG_FT1IMR_8822B */\n#define BIT__FT2ISR__IND_MSK_8822B BIT(30)\n#define BIT_FTM_PTT_INT_EN_8822B BIT(29)\n#define BIT_RXFTMREQ_INT_EN_8822B BIT(28)\n#define BIT_RXFTM_INT_EN_8822B BIT(27)\n#define BIT_TXFTM_INT_EN_8822B BIT(26)\n#define BIT_FS_H2C_CMD_OK_INT_EN_8822B BIT(25)\n#define BIT_FS_H2C_CMD_FULL_INT_EN_8822B BIT(24)\n#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8822B BIT(23)\n#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8822B BIT(22)\n#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8822B BIT(21)\n#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8822B BIT(20)\n#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8822B BIT(19)\n#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8822B BIT(18)\n#define BIT_FS_CTWEND2_INT_EN_8822B BIT(17)\n#define BIT_FS_CTWEND1_INT_EN_8822B BIT(16)\n#define BIT_FS_CTWEND0_INT_EN_8822B BIT(15)\n#define BIT_FS_TX_NULL1_INT_EN_8822B BIT(14)\n#define BIT_FS_TX_NULL0_INT_EN_8822B BIT(13)\n#define BIT_FS_TSF_BIT32_TOGGLE_EN_8822B BIT(12)\n#define BIT_FS_P2P_RFON2_INT_EN_8822B BIT(11)\n#define BIT_FS_P2P_RFOFF2_INT_EN_8822B BIT(10)\n#define BIT_FS_P2P_RFON1_INT_EN_8822B BIT(9)\n#define BIT_FS_P2P_RFOFF1_INT_EN_8822B BIT(8)\n#define BIT_FS_P2P_RFON0_INT_EN_8822B BIT(7)\n#define BIT_FS_P2P_RFOFF0_INT_EN_8822B BIT(6)\n#define BIT_FS_RX_UAPSDMD1_EN_8822B BIT(5)\n#define BIT_FS_RX_UAPSDMD0_EN_8822B BIT(4)\n#define BIT_FS_TRIGGER_PKT_EN_8822B BIT(3)\n#define BIT_FS_EOSP_INT_EN_8822B BIT(2)\n#define BIT_FS_RPWM2_INT_EN_8822B BIT(1)\n#define BIT_FS_RPWM_INT_EN_8822B BIT(0)\n\n/* 2 REG_FT1ISR_8822B */\n#define BIT__FT2ISR__IND_INT_8822B BIT(30)\n#define BIT_FTM_PTT_INT_8822B BIT(29)\n#define BIT_RXFTMREQ_INT_8822B BIT(28)\n#define BIT_RXFTM_INT_8822B BIT(27)\n#define BIT_TXFTM_INT_8822B BIT(26)\n#define BIT_FS_H2C_CMD_OK_INT_8822B BIT(25)\n#define BIT_FS_H2C_CMD_FULL_INT_8822B BIT(24)\n#define BIT_FS_MACID_PWRCHANGE5_INT_8822B BIT(23)\n#define BIT_FS_MACID_PWRCHANGE4_INT_8822B BIT(22)\n#define BIT_FS_MACID_PWRCHANGE3_INT_8822B BIT(21)\n#define BIT_FS_MACID_PWRCHANGE2_INT_8822B BIT(20)\n#define BIT_FS_MACID_PWRCHANGE1_INT_8822B BIT(19)\n#define BIT_FS_MACID_PWRCHANGE0_INT_8822B BIT(18)\n#define BIT_FS_CTWEND2_INT_8822B BIT(17)\n#define BIT_FS_CTWEND1_INT_8822B BIT(16)\n#define BIT_FS_CTWEND0_INT_8822B BIT(15)\n#define BIT_FS_TX_NULL1_INT_8822B BIT(14)\n#define BIT_FS_TX_NULL0_INT_8822B BIT(13)\n#define BIT_FS_TSF_BIT32_TOGGLE_INT_8822B BIT(12)\n#define BIT_FS_P2P_RFON2_INT_8822B BIT(11)\n#define BIT_FS_P2P_RFOFF2_INT_8822B BIT(10)\n#define BIT_FS_P2P_RFON1_INT_8822B BIT(9)\n#define BIT_FS_P2P_RFOFF1_INT_8822B BIT(8)\n#define BIT_FS_P2P_RFON0_INT_8822B BIT(7)\n#define BIT_FS_P2P_RFOFF0_INT_8822B BIT(6)\n#define BIT_FS_RX_UAPSDMD1_INT_8822B BIT(5)\n#define BIT_FS_RX_UAPSDMD0_INT_8822B BIT(4)\n#define BIT_FS_TRIGGER_PKT_INT_8822B BIT(3)\n#define BIT_FS_EOSP_INT_8822B BIT(2)\n#define BIT_FS_RPWM2_INT_8822B BIT(1)\n#define BIT_FS_RPWM_INT_8822B BIT(0)\n\n/* 2 REG_SPWR0_8822B */\n\n#define BIT_SHIFT_MID_31TO0_8822B 0\n#define BIT_MASK_MID_31TO0_8822B 0xffffffffL\n#define BIT_MID_31TO0_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_MID_31TO0_8822B) << BIT_SHIFT_MID_31TO0_8822B)\n#define BITS_MID_31TO0_8822B                                                   \\\n\t(BIT_MASK_MID_31TO0_8822B << BIT_SHIFT_MID_31TO0_8822B)\n#define BIT_CLEAR_MID_31TO0_8822B(x) ((x) & (~BITS_MID_31TO0_8822B))\n#define BIT_GET_MID_31TO0_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_MID_31TO0_8822B) & BIT_MASK_MID_31TO0_8822B)\n#define BIT_SET_MID_31TO0_8822B(x, v)                                          \\\n\t(BIT_CLEAR_MID_31TO0_8822B(x) | BIT_MID_31TO0_8822B(v))\n\n/* 2 REG_SPWR1_8822B */\n\n#define BIT_SHIFT_MID_63TO32_8822B 0\n#define BIT_MASK_MID_63TO32_8822B 0xffffffffL\n#define BIT_MID_63TO32_8822B(x)                                                \\\n\t(((x) & BIT_MASK_MID_63TO32_8822B) << BIT_SHIFT_MID_63TO32_8822B)\n#define BITS_MID_63TO32_8822B                                                  \\\n\t(BIT_MASK_MID_63TO32_8822B << BIT_SHIFT_MID_63TO32_8822B)\n#define BIT_CLEAR_MID_63TO32_8822B(x) ((x) & (~BITS_MID_63TO32_8822B))\n#define BIT_GET_MID_63TO32_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_MID_63TO32_8822B) & BIT_MASK_MID_63TO32_8822B)\n#define BIT_SET_MID_63TO32_8822B(x, v)                                         \\\n\t(BIT_CLEAR_MID_63TO32_8822B(x) | BIT_MID_63TO32_8822B(v))\n\n/* 2 REG_SPWR2_8822B */\n\n#define BIT_SHIFT_MID_95O64_8822B 0\n#define BIT_MASK_MID_95O64_8822B 0xffffffffL\n#define BIT_MID_95O64_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_MID_95O64_8822B) << BIT_SHIFT_MID_95O64_8822B)\n#define BITS_MID_95O64_8822B                                                   \\\n\t(BIT_MASK_MID_95O64_8822B << BIT_SHIFT_MID_95O64_8822B)\n#define BIT_CLEAR_MID_95O64_8822B(x) ((x) & (~BITS_MID_95O64_8822B))\n#define BIT_GET_MID_95O64_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_MID_95O64_8822B) & BIT_MASK_MID_95O64_8822B)\n#define BIT_SET_MID_95O64_8822B(x, v)                                          \\\n\t(BIT_CLEAR_MID_95O64_8822B(x) | BIT_MID_95O64_8822B(v))\n\n/* 2 REG_SPWR3_8822B */\n\n#define BIT_SHIFT_MID_127TO96_8822B 0\n#define BIT_MASK_MID_127TO96_8822B 0xffffffffL\n#define BIT_MID_127TO96_8822B(x)                                               \\\n\t(((x) & BIT_MASK_MID_127TO96_8822B) << BIT_SHIFT_MID_127TO96_8822B)\n#define BITS_MID_127TO96_8822B                                                 \\\n\t(BIT_MASK_MID_127TO96_8822B << BIT_SHIFT_MID_127TO96_8822B)\n#define BIT_CLEAR_MID_127TO96_8822B(x) ((x) & (~BITS_MID_127TO96_8822B))\n#define BIT_GET_MID_127TO96_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_MID_127TO96_8822B) & BIT_MASK_MID_127TO96_8822B)\n#define BIT_SET_MID_127TO96_8822B(x, v)                                        \\\n\t(BIT_CLEAR_MID_127TO96_8822B(x) | BIT_MID_127TO96_8822B(v))\n\n/* 2 REG_POWSEQ_8822B */\n\n#define BIT_SHIFT_SEQNUM_MID_8822B 16\n#define BIT_MASK_SEQNUM_MID_8822B 0xffff\n#define BIT_SEQNUM_MID_8822B(x)                                                \\\n\t(((x) & BIT_MASK_SEQNUM_MID_8822B) << BIT_SHIFT_SEQNUM_MID_8822B)\n#define BITS_SEQNUM_MID_8822B                                                  \\\n\t(BIT_MASK_SEQNUM_MID_8822B << BIT_SHIFT_SEQNUM_MID_8822B)\n#define BIT_CLEAR_SEQNUM_MID_8822B(x) ((x) & (~BITS_SEQNUM_MID_8822B))\n#define BIT_GET_SEQNUM_MID_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_SEQNUM_MID_8822B) & BIT_MASK_SEQNUM_MID_8822B)\n#define BIT_SET_SEQNUM_MID_8822B(x, v)                                         \\\n\t(BIT_CLEAR_SEQNUM_MID_8822B(x) | BIT_SEQNUM_MID_8822B(v))\n\n#define BIT_SHIFT_REF_MID_8822B 0\n#define BIT_MASK_REF_MID_8822B 0x7f\n#define BIT_REF_MID_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_REF_MID_8822B) << BIT_SHIFT_REF_MID_8822B)\n#define BITS_REF_MID_8822B (BIT_MASK_REF_MID_8822B << BIT_SHIFT_REF_MID_8822B)\n#define BIT_CLEAR_REF_MID_8822B(x) ((x) & (~BITS_REF_MID_8822B))\n#define BIT_GET_REF_MID_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_REF_MID_8822B) & BIT_MASK_REF_MID_8822B)\n#define BIT_SET_REF_MID_8822B(x, v)                                            \\\n\t(BIT_CLEAR_REF_MID_8822B(x) | BIT_REF_MID_8822B(v))\n\n/* 2 REG_TC7_CTRL_V1_8822B */\n#define BIT_TC7INT_EN_8822B BIT(26)\n#define BIT_TC7MODE_8822B BIT(25)\n#define BIT_TC7EN_8822B BIT(24)\n\n#define BIT_SHIFT_TC7DATA_8822B 0\n#define BIT_MASK_TC7DATA_8822B 0xffffff\n#define BIT_TC7DATA_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_TC7DATA_8822B) << BIT_SHIFT_TC7DATA_8822B)\n#define BITS_TC7DATA_8822B (BIT_MASK_TC7DATA_8822B << BIT_SHIFT_TC7DATA_8822B)\n#define BIT_CLEAR_TC7DATA_8822B(x) ((x) & (~BITS_TC7DATA_8822B))\n#define BIT_GET_TC7DATA_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC7DATA_8822B) & BIT_MASK_TC7DATA_8822B)\n#define BIT_SET_TC7DATA_8822B(x, v)                                            \\\n\t(BIT_CLEAR_TC7DATA_8822B(x) | BIT_TC7DATA_8822B(v))\n\n/* 2 REG_TC8_CTRL_V1_8822B */\n#define BIT_TC8INT_EN_8822B BIT(26)\n#define BIT_TC8MODE_8822B BIT(25)\n#define BIT_TC8EN_8822B BIT(24)\n\n#define BIT_SHIFT_TC8DATA_8822B 0\n#define BIT_MASK_TC8DATA_8822B 0xffffff\n#define BIT_TC8DATA_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_TC8DATA_8822B) << BIT_SHIFT_TC8DATA_8822B)\n#define BITS_TC8DATA_8822B (BIT_MASK_TC8DATA_8822B << BIT_SHIFT_TC8DATA_8822B)\n#define BIT_CLEAR_TC8DATA_8822B(x) ((x) & (~BITS_TC8DATA_8822B))\n#define BIT_GET_TC8DATA_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC8DATA_8822B) & BIT_MASK_TC8DATA_8822B)\n#define BIT_SET_TC8DATA_8822B(x, v)                                            \\\n\t(BIT_CLEAR_TC8DATA_8822B(x) | BIT_TC8DATA_8822B(v))\n\n/* 2 REG_FT2IMR_8822B */\n#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8822B BIT(31)\n#define BIT_FS_CLI3_RX_UAPSDMD0_EN_8822B BIT(30)\n#define BIT_FS_CLI3_TRIGGER_PKT_EN_8822B BIT(29)\n#define BIT_FS_CLI3_EOSP_INT_EN_8822B BIT(28)\n#define BIT_FS_CLI2_RX_UAPSDMD1_EN_8822B BIT(27)\n#define BIT_FS_CLI2_RX_UAPSDMD0_EN_8822B BIT(26)\n#define BIT_FS_CLI2_TRIGGER_PKT_EN_8822B BIT(25)\n#define BIT_FS_CLI2_EOSP_INT_EN_8822B BIT(24)\n#define BIT_FS_CLI1_RX_UAPSDMD1_EN_8822B BIT(23)\n#define BIT_FS_CLI1_RX_UAPSDMD0_EN_8822B BIT(22)\n#define BIT_FS_CLI1_TRIGGER_PKT_EN_8822B BIT(21)\n#define BIT_FS_CLI1_EOSP_INT_EN_8822B BIT(20)\n#define BIT_FS_CLI0_RX_UAPSDMD1_EN_8822B BIT(19)\n#define BIT_FS_CLI0_RX_UAPSDMD0_EN_8822B BIT(18)\n#define BIT_FS_CLI0_TRIGGER_PKT_EN_8822B BIT(17)\n#define BIT_FS_CLI0_EOSP_INT_EN_8822B BIT(16)\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN_8822B BIT(9)\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN_8822B BIT(8)\n#define BIT_FS_CLI3_TX_NULL1_INT_EN_8822B BIT(7)\n#define BIT_FS_CLI3_TX_NULL0_INT_EN_8822B BIT(6)\n#define BIT_FS_CLI2_TX_NULL1_INT_EN_8822B BIT(5)\n#define BIT_FS_CLI2_TX_NULL0_INT_EN_8822B BIT(4)\n#define BIT_FS_CLI1_TX_NULL1_INT_EN_8822B BIT(3)\n#define BIT_FS_CLI1_TX_NULL0_INT_EN_8822B BIT(2)\n#define BIT_FS_CLI0_TX_NULL1_INT_EN_8822B BIT(1)\n#define BIT_FS_CLI0_TX_NULL0_INT_EN_8822B BIT(0)\n\n/* 2 REG_FT2ISR_8822B */\n#define BIT_FS_CLI3_RX_UAPSDMD1_INT_8822B BIT(31)\n#define BIT_FS_CLI3_RX_UAPSDMD0_INT_8822B BIT(30)\n#define BIT_FS_CLI3_TRIGGER_PKT_INT_8822B BIT(29)\n#define BIT_FS_CLI3_EOSP_INT_8822B BIT(28)\n#define BIT_FS_CLI2_RX_UAPSDMD1_INT_8822B BIT(27)\n#define BIT_FS_CLI2_RX_UAPSDMD0_INT_8822B BIT(26)\n#define BIT_FS_CLI2_TRIGGER_PKT_INT_8822B BIT(25)\n#define BIT_FS_CLI2_EOSP_INT_8822B BIT(24)\n#define BIT_FS_CLI1_RX_UAPSDMD1_INT_8822B BIT(23)\n#define BIT_FS_CLI1_RX_UAPSDMD0_INT_8822B BIT(22)\n#define BIT_FS_CLI1_TRIGGER_PKT_INT_8822B BIT(21)\n#define BIT_FS_CLI1_EOSP_INT_8822B BIT(20)\n#define BIT_FS_CLI0_RX_UAPSDMD1_INT_8822B BIT(19)\n#define BIT_FS_CLI0_RX_UAPSDMD0_INT_8822B BIT(18)\n#define BIT_FS_CLI0_TRIGGER_PKT_INT_8822B BIT(17)\n#define BIT_FS_CLI0_EOSP_INT_8822B BIT(16)\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT_8822B BIT(9)\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT_8822B BIT(8)\n#define BIT_FS_CLI3_TX_NULL1_INT_8822B BIT(7)\n#define BIT_FS_CLI3_TX_NULL0_INT_8822B BIT(6)\n#define BIT_FS_CLI2_TX_NULL1_INT_8822B BIT(5)\n#define BIT_FS_CLI2_TX_NULL0_INT_8822B BIT(4)\n#define BIT_FS_CLI1_TX_NULL1_INT_8822B BIT(3)\n#define BIT_FS_CLI1_TX_NULL0_INT_8822B BIT(2)\n#define BIT_FS_CLI0_TX_NULL1_INT_8822B BIT(1)\n#define BIT_FS_CLI0_TX_NULL0_INT_8822B BIT(0)\n\n/* 2 REG_MSG2_8822B */\n\n#define BIT_SHIFT_FW_MSG2_8822B 0\n#define BIT_MASK_FW_MSG2_8822B 0xffffffffL\n#define BIT_FW_MSG2_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG2_8822B) << BIT_SHIFT_FW_MSG2_8822B)\n#define BITS_FW_MSG2_8822B (BIT_MASK_FW_MSG2_8822B << BIT_SHIFT_FW_MSG2_8822B)\n#define BIT_CLEAR_FW_MSG2_8822B(x) ((x) & (~BITS_FW_MSG2_8822B))\n#define BIT_GET_FW_MSG2_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG2_8822B) & BIT_MASK_FW_MSG2_8822B)\n#define BIT_SET_FW_MSG2_8822B(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG2_8822B(x) | BIT_FW_MSG2_8822B(v))\n\n/* 2 REG_MSG3_8822B */\n\n#define BIT_SHIFT_FW_MSG3_8822B 0\n#define BIT_MASK_FW_MSG3_8822B 0xffffffffL\n#define BIT_FW_MSG3_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG3_8822B) << BIT_SHIFT_FW_MSG3_8822B)\n#define BITS_FW_MSG3_8822B (BIT_MASK_FW_MSG3_8822B << BIT_SHIFT_FW_MSG3_8822B)\n#define BIT_CLEAR_FW_MSG3_8822B(x) ((x) & (~BITS_FW_MSG3_8822B))\n#define BIT_GET_FW_MSG3_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG3_8822B) & BIT_MASK_FW_MSG3_8822B)\n#define BIT_SET_FW_MSG3_8822B(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG3_8822B(x) | BIT_FW_MSG3_8822B(v))\n\n/* 2 REG_MSG4_8822B */\n\n#define BIT_SHIFT_FW_MSG4_8822B 0\n#define BIT_MASK_FW_MSG4_8822B 0xffffffffL\n#define BIT_FW_MSG4_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG4_8822B) << BIT_SHIFT_FW_MSG4_8822B)\n#define BITS_FW_MSG4_8822B (BIT_MASK_FW_MSG4_8822B << BIT_SHIFT_FW_MSG4_8822B)\n#define BIT_CLEAR_FW_MSG4_8822B(x) ((x) & (~BITS_FW_MSG4_8822B))\n#define BIT_GET_FW_MSG4_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG4_8822B) & BIT_MASK_FW_MSG4_8822B)\n#define BIT_SET_FW_MSG4_8822B(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG4_8822B(x) | BIT_FW_MSG4_8822B(v))\n\n/* 2 REG_MSG5_8822B */\n\n#define BIT_SHIFT_FW_MSG5_8822B 0\n#define BIT_MASK_FW_MSG5_8822B 0xffffffffL\n#define BIT_FW_MSG5_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG5_8822B) << BIT_SHIFT_FW_MSG5_8822B)\n#define BITS_FW_MSG5_8822B (BIT_MASK_FW_MSG5_8822B << BIT_SHIFT_FW_MSG5_8822B)\n#define BIT_CLEAR_FW_MSG5_8822B(x) ((x) & (~BITS_FW_MSG5_8822B))\n#define BIT_GET_FW_MSG5_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG5_8822B) & BIT_MASK_FW_MSG5_8822B)\n#define BIT_SET_FW_MSG5_8822B(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG5_8822B(x) | BIT_FW_MSG5_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_FIFOPAGE_CTRL_1_8822B */\n\n#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B 16\n#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B 0xff\n#define BIT_TX_OQT_HE_FREE_SPACE_V1_8822B(x)                                   \\\n\t(((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B)                        \\\n\t << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B)\n#define BITS_TX_OQT_HE_FREE_SPACE_V1_8822B                                     \\\n\t(BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B                                \\\n\t << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B)\n#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822B(x)                             \\\n\t((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8822B))\n#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8822B(x)                               \\\n\t(((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B) &                    \\\n\t BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B)\n#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8822B(x, v)                            \\\n\t(BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822B(x) |                          \\\n\t BIT_TX_OQT_HE_FREE_SPACE_V1_8822B(v))\n\n#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B 0\n#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B 0xff\n#define BIT_TX_OQT_NL_FREE_SPACE_V1_8822B(x)                                   \\\n\t(((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B)                        \\\n\t << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B)\n#define BITS_TX_OQT_NL_FREE_SPACE_V1_8822B                                     \\\n\t(BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B                                \\\n\t << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B)\n#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822B(x)                             \\\n\t((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8822B))\n#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8822B(x)                               \\\n\t(((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B) &                    \\\n\t BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B)\n#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8822B(x, v)                            \\\n\t(BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822B(x) |                          \\\n\t BIT_TX_OQT_NL_FREE_SPACE_V1_8822B(v))\n\n/* 2 REG_FIFOPAGE_CTRL_2_8822B */\n#define BIT_BCN_VALID_1_V1_8822B BIT(31)\n\n#define BIT_SHIFT_BCN_HEAD_1_V1_8822B 16\n#define BIT_MASK_BCN_HEAD_1_V1_8822B 0xfff\n#define BIT_BCN_HEAD_1_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_BCN_HEAD_1_V1_8822B) << BIT_SHIFT_BCN_HEAD_1_V1_8822B)\n#define BITS_BCN_HEAD_1_V1_8822B                                               \\\n\t(BIT_MASK_BCN_HEAD_1_V1_8822B << BIT_SHIFT_BCN_HEAD_1_V1_8822B)\n#define BIT_CLEAR_BCN_HEAD_1_V1_8822B(x) ((x) & (~BITS_BCN_HEAD_1_V1_8822B))\n#define BIT_GET_BCN_HEAD_1_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8822B) & BIT_MASK_BCN_HEAD_1_V1_8822B)\n#define BIT_SET_BCN_HEAD_1_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_BCN_HEAD_1_V1_8822B(x) | BIT_BCN_HEAD_1_V1_8822B(v))\n\n#define BIT_BCN_VALID_V1_8822B BIT(15)\n\n#define BIT_SHIFT_BCN_HEAD_V1_8822B 0\n#define BIT_MASK_BCN_HEAD_V1_8822B 0xfff\n#define BIT_BCN_HEAD_V1_8822B(x)                                               \\\n\t(((x) & BIT_MASK_BCN_HEAD_V1_8822B) << BIT_SHIFT_BCN_HEAD_V1_8822B)\n#define BITS_BCN_HEAD_V1_8822B                                                 \\\n\t(BIT_MASK_BCN_HEAD_V1_8822B << BIT_SHIFT_BCN_HEAD_V1_8822B)\n#define BIT_CLEAR_BCN_HEAD_V1_8822B(x) ((x) & (~BITS_BCN_HEAD_V1_8822B))\n#define BIT_GET_BCN_HEAD_V1_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_BCN_HEAD_V1_8822B) & BIT_MASK_BCN_HEAD_V1_8822B)\n#define BIT_SET_BCN_HEAD_V1_8822B(x, v)                                        \\\n\t(BIT_CLEAR_BCN_HEAD_V1_8822B(x) | BIT_BCN_HEAD_V1_8822B(v))\n\n/* 2 REG_AUTO_LLT_V1_8822B */\n\n#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B 24\n#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B 0xff\n#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x)                            \\\n\t(((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B)                 \\\n\t << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B)\n#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B                              \\\n\t(BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B                         \\\n\t << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B)\n#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x)                      \\\n\t((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B))\n#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x)                        \\\n\t(((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) &             \\\n\t BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B)\n#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x, v)                     \\\n\t(BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) |                   \\\n\t BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(v))\n\n#define BIT_SHIFT_LLT_FREE_PAGE_V1_8822B 8\n#define BIT_MASK_LLT_FREE_PAGE_V1_8822B 0xffff\n#define BIT_LLT_FREE_PAGE_V1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_LLT_FREE_PAGE_V1_8822B)                               \\\n\t << BIT_SHIFT_LLT_FREE_PAGE_V1_8822B)\n#define BITS_LLT_FREE_PAGE_V1_8822B                                            \\\n\t(BIT_MASK_LLT_FREE_PAGE_V1_8822B << BIT_SHIFT_LLT_FREE_PAGE_V1_8822B)\n#define BIT_CLEAR_LLT_FREE_PAGE_V1_8822B(x)                                    \\\n\t((x) & (~BITS_LLT_FREE_PAGE_V1_8822B))\n#define BIT_GET_LLT_FREE_PAGE_V1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8822B) &                           \\\n\t BIT_MASK_LLT_FREE_PAGE_V1_8822B)\n#define BIT_SET_LLT_FREE_PAGE_V1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_LLT_FREE_PAGE_V1_8822B(x) | BIT_LLT_FREE_PAGE_V1_8822B(v))\n\n#define BIT_SHIFT_BLK_DESC_NUM_8822B 4\n#define BIT_MASK_BLK_DESC_NUM_8822B 0xf\n#define BIT_BLK_DESC_NUM_8822B(x)                                              \\\n\t(((x) & BIT_MASK_BLK_DESC_NUM_8822B) << BIT_SHIFT_BLK_DESC_NUM_8822B)\n#define BITS_BLK_DESC_NUM_8822B                                                \\\n\t(BIT_MASK_BLK_DESC_NUM_8822B << BIT_SHIFT_BLK_DESC_NUM_8822B)\n#define BIT_CLEAR_BLK_DESC_NUM_8822B(x) ((x) & (~BITS_BLK_DESC_NUM_8822B))\n#define BIT_GET_BLK_DESC_NUM_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BLK_DESC_NUM_8822B) & BIT_MASK_BLK_DESC_NUM_8822B)\n#define BIT_SET_BLK_DESC_NUM_8822B(x, v)                                       \\\n\t(BIT_CLEAR_BLK_DESC_NUM_8822B(x) | BIT_BLK_DESC_NUM_8822B(v))\n\n#define BIT_R_BCN_HEAD_SEL_8822B BIT(3)\n#define BIT_R_EN_BCN_SW_HEAD_SEL_8822B BIT(2)\n#define BIT_LLT_DBG_SEL_8822B BIT(1)\n#define BIT_AUTO_INIT_LLT_V1_8822B BIT(0)\n\n/* 2 REG_TXDMA_OFFSET_CHK_8822B */\n#define BIT_EM_CHKSUM_FIN_8822B BIT(31)\n#define BIT_EMN_PCIE_DMA_MOD_8822B BIT(30)\n#define BIT_EN_TXQUE_CLR_8822B BIT(29)\n#define BIT_EN_PCIE_FIFO_MODE_8822B BIT(28)\n\n#define BIT_SHIFT_PG_UNDER_TH_V1_8822B 16\n#define BIT_MASK_PG_UNDER_TH_V1_8822B 0xfff\n#define BIT_PG_UNDER_TH_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_PG_UNDER_TH_V1_8822B)                                 \\\n\t << BIT_SHIFT_PG_UNDER_TH_V1_8822B)\n#define BITS_PG_UNDER_TH_V1_8822B                                              \\\n\t(BIT_MASK_PG_UNDER_TH_V1_8822B << BIT_SHIFT_PG_UNDER_TH_V1_8822B)\n#define BIT_CLEAR_PG_UNDER_TH_V1_8822B(x) ((x) & (~BITS_PG_UNDER_TH_V1_8822B))\n#define BIT_GET_PG_UNDER_TH_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8822B) &                             \\\n\t BIT_MASK_PG_UNDER_TH_V1_8822B)\n#define BIT_SET_PG_UNDER_TH_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_PG_UNDER_TH_V1_8822B(x) | BIT_PG_UNDER_TH_V1_8822B(v))\n\n#define BIT_RESTORE_H2C_ADDRESS_8822B BIT(15)\n#define BIT_SDIO_TXDESC_CHKSUM_EN_8822B BIT(13)\n#define BIT_RST_RDPTR_8822B BIT(12)\n#define BIT_RST_WRPTR_8822B BIT(11)\n#define BIT_CHK_PG_TH_EN_8822B BIT(10)\n#define BIT_DROP_DATA_EN_8822B BIT(9)\n#define BIT_CHECK_OFFSET_EN_8822B BIT(8)\n\n#define BIT_SHIFT_CHECK_OFFSET_8822B 0\n#define BIT_MASK_CHECK_OFFSET_8822B 0xff\n#define BIT_CHECK_OFFSET_8822B(x)                                              \\\n\t(((x) & BIT_MASK_CHECK_OFFSET_8822B) << BIT_SHIFT_CHECK_OFFSET_8822B)\n#define BITS_CHECK_OFFSET_8822B                                                \\\n\t(BIT_MASK_CHECK_OFFSET_8822B << BIT_SHIFT_CHECK_OFFSET_8822B)\n#define BIT_CLEAR_CHECK_OFFSET_8822B(x) ((x) & (~BITS_CHECK_OFFSET_8822B))\n#define BIT_GET_CHECK_OFFSET_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_CHECK_OFFSET_8822B) & BIT_MASK_CHECK_OFFSET_8822B)\n#define BIT_SET_CHECK_OFFSET_8822B(x, v)                                       \\\n\t(BIT_CLEAR_CHECK_OFFSET_8822B(x) | BIT_CHECK_OFFSET_8822B(v))\n\n/* 2 REG_TXDMA_STATUS_8822B */\n#define BIT_HI_OQT_UDN_8822B BIT(17)\n#define BIT_HI_OQT_OVF_8822B BIT(16)\n#define BIT_PAYLOAD_CHKSUM_ERR_8822B BIT(15)\n#define BIT_PAYLOAD_UDN_8822B BIT(14)\n#define BIT_PAYLOAD_OVF_8822B BIT(13)\n#define BIT_DSC_CHKSUM_FAIL_8822B BIT(12)\n#define BIT_UNKNOWN_QSEL_8822B BIT(11)\n#define BIT_EP_QSEL_DIFF_8822B BIT(10)\n#define BIT_TX_OFFS_UNMATCH_8822B BIT(9)\n#define BIT_TXOQT_UDN_8822B BIT(8)\n#define BIT_TXOQT_OVF_8822B BIT(7)\n#define BIT_TXDMA_SFF_UDN_8822B BIT(6)\n#define BIT_TXDMA_SFF_OVF_8822B BIT(5)\n#define BIT_LLT_NULL_PG_8822B BIT(4)\n#define BIT_PAGE_UDN_8822B BIT(3)\n#define BIT_PAGE_OVF_8822B BIT(2)\n#define BIT_TXFF_PG_UDN_8822B BIT(1)\n#define BIT_TXFF_PG_OVF_8822B BIT(0)\n\n/* 2 REG_TX_DMA_DBG_8822B */\n\n/* 2 REG_TQPNT1_8822B */\n\n#define BIT_SHIFT_HPQ_HIGH_TH_V1_8822B 16\n#define BIT_MASK_HPQ_HIGH_TH_V1_8822B 0xfff\n#define BIT_HPQ_HIGH_TH_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HPQ_HIGH_TH_V1_8822B)                                 \\\n\t << BIT_SHIFT_HPQ_HIGH_TH_V1_8822B)\n#define BITS_HPQ_HIGH_TH_V1_8822B                                              \\\n\t(BIT_MASK_HPQ_HIGH_TH_V1_8822B << BIT_SHIFT_HPQ_HIGH_TH_V1_8822B)\n#define BIT_CLEAR_HPQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8822B))\n#define BIT_GET_HPQ_HIGH_TH_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8822B) &                             \\\n\t BIT_MASK_HPQ_HIGH_TH_V1_8822B)\n#define BIT_SET_HPQ_HIGH_TH_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HPQ_HIGH_TH_V1_8822B(x) | BIT_HPQ_HIGH_TH_V1_8822B(v))\n\n#define BIT_SHIFT_HPQ_LOW_TH_V1_8822B 0\n#define BIT_MASK_HPQ_LOW_TH_V1_8822B 0xfff\n#define BIT_HPQ_LOW_TH_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HPQ_LOW_TH_V1_8822B) << BIT_SHIFT_HPQ_LOW_TH_V1_8822B)\n#define BITS_HPQ_LOW_TH_V1_8822B                                               \\\n\t(BIT_MASK_HPQ_LOW_TH_V1_8822B << BIT_SHIFT_HPQ_LOW_TH_V1_8822B)\n#define BIT_CLEAR_HPQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8822B))\n#define BIT_GET_HPQ_LOW_TH_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8822B) & BIT_MASK_HPQ_LOW_TH_V1_8822B)\n#define BIT_SET_HPQ_LOW_TH_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HPQ_LOW_TH_V1_8822B(x) | BIT_HPQ_LOW_TH_V1_8822B(v))\n\n/* 2 REG_TQPNT2_8822B */\n\n#define BIT_SHIFT_NPQ_HIGH_TH_V1_8822B 16\n#define BIT_MASK_NPQ_HIGH_TH_V1_8822B 0xfff\n#define BIT_NPQ_HIGH_TH_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_NPQ_HIGH_TH_V1_8822B)                                 \\\n\t << BIT_SHIFT_NPQ_HIGH_TH_V1_8822B)\n#define BITS_NPQ_HIGH_TH_V1_8822B                                              \\\n\t(BIT_MASK_NPQ_HIGH_TH_V1_8822B << BIT_SHIFT_NPQ_HIGH_TH_V1_8822B)\n#define BIT_CLEAR_NPQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8822B))\n#define BIT_GET_NPQ_HIGH_TH_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8822B) &                             \\\n\t BIT_MASK_NPQ_HIGH_TH_V1_8822B)\n#define BIT_SET_NPQ_HIGH_TH_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_NPQ_HIGH_TH_V1_8822B(x) | BIT_NPQ_HIGH_TH_V1_8822B(v))\n\n#define BIT_SHIFT_NPQ_LOW_TH_V1_8822B 0\n#define BIT_MASK_NPQ_LOW_TH_V1_8822B 0xfff\n#define BIT_NPQ_LOW_TH_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_NPQ_LOW_TH_V1_8822B) << BIT_SHIFT_NPQ_LOW_TH_V1_8822B)\n#define BITS_NPQ_LOW_TH_V1_8822B                                               \\\n\t(BIT_MASK_NPQ_LOW_TH_V1_8822B << BIT_SHIFT_NPQ_LOW_TH_V1_8822B)\n#define BIT_CLEAR_NPQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8822B))\n#define BIT_GET_NPQ_LOW_TH_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8822B) & BIT_MASK_NPQ_LOW_TH_V1_8822B)\n#define BIT_SET_NPQ_LOW_TH_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_NPQ_LOW_TH_V1_8822B(x) | BIT_NPQ_LOW_TH_V1_8822B(v))\n\n/* 2 REG_TQPNT3_8822B */\n\n#define BIT_SHIFT_LPQ_HIGH_TH_V1_8822B 16\n#define BIT_MASK_LPQ_HIGH_TH_V1_8822B 0xfff\n#define BIT_LPQ_HIGH_TH_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_LPQ_HIGH_TH_V1_8822B)                                 \\\n\t << BIT_SHIFT_LPQ_HIGH_TH_V1_8822B)\n#define BITS_LPQ_HIGH_TH_V1_8822B                                              \\\n\t(BIT_MASK_LPQ_HIGH_TH_V1_8822B << BIT_SHIFT_LPQ_HIGH_TH_V1_8822B)\n#define BIT_CLEAR_LPQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8822B))\n#define BIT_GET_LPQ_HIGH_TH_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8822B) &                             \\\n\t BIT_MASK_LPQ_HIGH_TH_V1_8822B)\n#define BIT_SET_LPQ_HIGH_TH_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_LPQ_HIGH_TH_V1_8822B(x) | BIT_LPQ_HIGH_TH_V1_8822B(v))\n\n#define BIT_SHIFT_LPQ_LOW_TH_V1_8822B 0\n#define BIT_MASK_LPQ_LOW_TH_V1_8822B 0xfff\n#define BIT_LPQ_LOW_TH_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_LPQ_LOW_TH_V1_8822B) << BIT_SHIFT_LPQ_LOW_TH_V1_8822B)\n#define BITS_LPQ_LOW_TH_V1_8822B                                               \\\n\t(BIT_MASK_LPQ_LOW_TH_V1_8822B << BIT_SHIFT_LPQ_LOW_TH_V1_8822B)\n#define BIT_CLEAR_LPQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8822B))\n#define BIT_GET_LPQ_LOW_TH_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8822B) & BIT_MASK_LPQ_LOW_TH_V1_8822B)\n#define BIT_SET_LPQ_LOW_TH_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_LPQ_LOW_TH_V1_8822B(x) | BIT_LPQ_LOW_TH_V1_8822B(v))\n\n/* 2 REG_TQPNT4_8822B */\n\n#define BIT_SHIFT_EXQ_HIGH_TH_V1_8822B 16\n#define BIT_MASK_EXQ_HIGH_TH_V1_8822B 0xfff\n#define BIT_EXQ_HIGH_TH_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_EXQ_HIGH_TH_V1_8822B)                                 \\\n\t << BIT_SHIFT_EXQ_HIGH_TH_V1_8822B)\n#define BITS_EXQ_HIGH_TH_V1_8822B                                              \\\n\t(BIT_MASK_EXQ_HIGH_TH_V1_8822B << BIT_SHIFT_EXQ_HIGH_TH_V1_8822B)\n#define BIT_CLEAR_EXQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8822B))\n#define BIT_GET_EXQ_HIGH_TH_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8822B) &                             \\\n\t BIT_MASK_EXQ_HIGH_TH_V1_8822B)\n#define BIT_SET_EXQ_HIGH_TH_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_EXQ_HIGH_TH_V1_8822B(x) | BIT_EXQ_HIGH_TH_V1_8822B(v))\n\n#define BIT_SHIFT_EXQ_LOW_TH_V1_8822B 0\n#define BIT_MASK_EXQ_LOW_TH_V1_8822B 0xfff\n#define BIT_EXQ_LOW_TH_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_EXQ_LOW_TH_V1_8822B) << BIT_SHIFT_EXQ_LOW_TH_V1_8822B)\n#define BITS_EXQ_LOW_TH_V1_8822B                                               \\\n\t(BIT_MASK_EXQ_LOW_TH_V1_8822B << BIT_SHIFT_EXQ_LOW_TH_V1_8822B)\n#define BIT_CLEAR_EXQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8822B))\n#define BIT_GET_EXQ_LOW_TH_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8822B) & BIT_MASK_EXQ_LOW_TH_V1_8822B)\n#define BIT_SET_EXQ_LOW_TH_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_EXQ_LOW_TH_V1_8822B(x) | BIT_EXQ_LOW_TH_V1_8822B(v))\n\n/* 2 REG_RQPN_CTRL_1_8822B */\n\n#define BIT_SHIFT_TXPKTNUM_H_8822B 16\n#define BIT_MASK_TXPKTNUM_H_8822B 0xffff\n#define BIT_TXPKTNUM_H_8822B(x)                                                \\\n\t(((x) & BIT_MASK_TXPKTNUM_H_8822B) << BIT_SHIFT_TXPKTNUM_H_8822B)\n#define BITS_TXPKTNUM_H_8822B                                                  \\\n\t(BIT_MASK_TXPKTNUM_H_8822B << BIT_SHIFT_TXPKTNUM_H_8822B)\n#define BIT_CLEAR_TXPKTNUM_H_8822B(x) ((x) & (~BITS_TXPKTNUM_H_8822B))\n#define BIT_GET_TXPKTNUM_H_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_H_8822B) & BIT_MASK_TXPKTNUM_H_8822B)\n#define BIT_SET_TXPKTNUM_H_8822B(x, v)                                         \\\n\t(BIT_CLEAR_TXPKTNUM_H_8822B(x) | BIT_TXPKTNUM_H_8822B(v))\n\n#define BIT_SHIFT_TXPKTNUM_V2_8822B 0\n#define BIT_MASK_TXPKTNUM_V2_8822B 0xffff\n#define BIT_TXPKTNUM_V2_8822B(x)                                               \\\n\t(((x) & BIT_MASK_TXPKTNUM_V2_8822B) << BIT_SHIFT_TXPKTNUM_V2_8822B)\n#define BITS_TXPKTNUM_V2_8822B                                                 \\\n\t(BIT_MASK_TXPKTNUM_V2_8822B << BIT_SHIFT_TXPKTNUM_V2_8822B)\n#define BIT_CLEAR_TXPKTNUM_V2_8822B(x) ((x) & (~BITS_TXPKTNUM_V2_8822B))\n#define BIT_GET_TXPKTNUM_V2_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_V2_8822B) & BIT_MASK_TXPKTNUM_V2_8822B)\n#define BIT_SET_TXPKTNUM_V2_8822B(x, v)                                        \\\n\t(BIT_CLEAR_TXPKTNUM_V2_8822B(x) | BIT_TXPKTNUM_V2_8822B(v))\n\n/* 2 REG_RQPN_CTRL_2_8822B */\n#define BIT_LD_RQPN_8822B BIT(31)\n#define BIT_EXQ_PUBLIC_DIS_V1_8822B BIT(19)\n#define BIT_NPQ_PUBLIC_DIS_V1_8822B BIT(18)\n#define BIT_LPQ_PUBLIC_DIS_V1_8822B BIT(17)\n#define BIT_HPQ_PUBLIC_DIS_V1_8822B BIT(16)\n\n/* 2 REG_FIFOPAGE_INFO_1_8822B */\n\n#define BIT_SHIFT_HPQ_AVAL_PG_V1_8822B 16\n#define BIT_MASK_HPQ_AVAL_PG_V1_8822B 0xfff\n#define BIT_HPQ_AVAL_PG_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HPQ_AVAL_PG_V1_8822B)                                 \\\n\t << BIT_SHIFT_HPQ_AVAL_PG_V1_8822B)\n#define BITS_HPQ_AVAL_PG_V1_8822B                                              \\\n\t(BIT_MASK_HPQ_AVAL_PG_V1_8822B << BIT_SHIFT_HPQ_AVAL_PG_V1_8822B)\n#define BIT_CLEAR_HPQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8822B))\n#define BIT_GET_HPQ_AVAL_PG_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8822B) &                             \\\n\t BIT_MASK_HPQ_AVAL_PG_V1_8822B)\n#define BIT_SET_HPQ_AVAL_PG_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HPQ_AVAL_PG_V1_8822B(x) | BIT_HPQ_AVAL_PG_V1_8822B(v))\n\n#define BIT_SHIFT_HPQ_V1_8822B 0\n#define BIT_MASK_HPQ_V1_8822B 0xfff\n#define BIT_HPQ_V1_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_HPQ_V1_8822B) << BIT_SHIFT_HPQ_V1_8822B)\n#define BITS_HPQ_V1_8822B (BIT_MASK_HPQ_V1_8822B << BIT_SHIFT_HPQ_V1_8822B)\n#define BIT_CLEAR_HPQ_V1_8822B(x) ((x) & (~BITS_HPQ_V1_8822B))\n#define BIT_GET_HPQ_V1_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_HPQ_V1_8822B) & BIT_MASK_HPQ_V1_8822B)\n#define BIT_SET_HPQ_V1_8822B(x, v)                                             \\\n\t(BIT_CLEAR_HPQ_V1_8822B(x) | BIT_HPQ_V1_8822B(v))\n\n/* 2 REG_FIFOPAGE_INFO_2_8822B */\n\n#define BIT_SHIFT_LPQ_AVAL_PG_V1_8822B 16\n#define BIT_MASK_LPQ_AVAL_PG_V1_8822B 0xfff\n#define BIT_LPQ_AVAL_PG_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_LPQ_AVAL_PG_V1_8822B)                                 \\\n\t << BIT_SHIFT_LPQ_AVAL_PG_V1_8822B)\n#define BITS_LPQ_AVAL_PG_V1_8822B                                              \\\n\t(BIT_MASK_LPQ_AVAL_PG_V1_8822B << BIT_SHIFT_LPQ_AVAL_PG_V1_8822B)\n#define BIT_CLEAR_LPQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8822B))\n#define BIT_GET_LPQ_AVAL_PG_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8822B) &                             \\\n\t BIT_MASK_LPQ_AVAL_PG_V1_8822B)\n#define BIT_SET_LPQ_AVAL_PG_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_LPQ_AVAL_PG_V1_8822B(x) | BIT_LPQ_AVAL_PG_V1_8822B(v))\n\n#define BIT_SHIFT_LPQ_V1_8822B 0\n#define BIT_MASK_LPQ_V1_8822B 0xfff\n#define BIT_LPQ_V1_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_LPQ_V1_8822B) << BIT_SHIFT_LPQ_V1_8822B)\n#define BITS_LPQ_V1_8822B (BIT_MASK_LPQ_V1_8822B << BIT_SHIFT_LPQ_V1_8822B)\n#define BIT_CLEAR_LPQ_V1_8822B(x) ((x) & (~BITS_LPQ_V1_8822B))\n#define BIT_GET_LPQ_V1_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_LPQ_V1_8822B) & BIT_MASK_LPQ_V1_8822B)\n#define BIT_SET_LPQ_V1_8822B(x, v)                                             \\\n\t(BIT_CLEAR_LPQ_V1_8822B(x) | BIT_LPQ_V1_8822B(v))\n\n/* 2 REG_FIFOPAGE_INFO_3_8822B */\n\n#define BIT_SHIFT_NPQ_AVAL_PG_V1_8822B 16\n#define BIT_MASK_NPQ_AVAL_PG_V1_8822B 0xfff\n#define BIT_NPQ_AVAL_PG_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_NPQ_AVAL_PG_V1_8822B)                                 \\\n\t << BIT_SHIFT_NPQ_AVAL_PG_V1_8822B)\n#define BITS_NPQ_AVAL_PG_V1_8822B                                              \\\n\t(BIT_MASK_NPQ_AVAL_PG_V1_8822B << BIT_SHIFT_NPQ_AVAL_PG_V1_8822B)\n#define BIT_CLEAR_NPQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8822B))\n#define BIT_GET_NPQ_AVAL_PG_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8822B) &                             \\\n\t BIT_MASK_NPQ_AVAL_PG_V1_8822B)\n#define BIT_SET_NPQ_AVAL_PG_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_NPQ_AVAL_PG_V1_8822B(x) | BIT_NPQ_AVAL_PG_V1_8822B(v))\n\n#define BIT_SHIFT_NPQ_V1_8822B 0\n#define BIT_MASK_NPQ_V1_8822B 0xfff\n#define BIT_NPQ_V1_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_NPQ_V1_8822B) << BIT_SHIFT_NPQ_V1_8822B)\n#define BITS_NPQ_V1_8822B (BIT_MASK_NPQ_V1_8822B << BIT_SHIFT_NPQ_V1_8822B)\n#define BIT_CLEAR_NPQ_V1_8822B(x) ((x) & (~BITS_NPQ_V1_8822B))\n#define BIT_GET_NPQ_V1_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_NPQ_V1_8822B) & BIT_MASK_NPQ_V1_8822B)\n#define BIT_SET_NPQ_V1_8822B(x, v)                                             \\\n\t(BIT_CLEAR_NPQ_V1_8822B(x) | BIT_NPQ_V1_8822B(v))\n\n/* 2 REG_FIFOPAGE_INFO_4_8822B */\n\n#define BIT_SHIFT_EXQ_AVAL_PG_V1_8822B 16\n#define BIT_MASK_EXQ_AVAL_PG_V1_8822B 0xfff\n#define BIT_EXQ_AVAL_PG_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_EXQ_AVAL_PG_V1_8822B)                                 \\\n\t << BIT_SHIFT_EXQ_AVAL_PG_V1_8822B)\n#define BITS_EXQ_AVAL_PG_V1_8822B                                              \\\n\t(BIT_MASK_EXQ_AVAL_PG_V1_8822B << BIT_SHIFT_EXQ_AVAL_PG_V1_8822B)\n#define BIT_CLEAR_EXQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8822B))\n#define BIT_GET_EXQ_AVAL_PG_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8822B) &                             \\\n\t BIT_MASK_EXQ_AVAL_PG_V1_8822B)\n#define BIT_SET_EXQ_AVAL_PG_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_EXQ_AVAL_PG_V1_8822B(x) | BIT_EXQ_AVAL_PG_V1_8822B(v))\n\n#define BIT_SHIFT_EXQ_V1_8822B 0\n#define BIT_MASK_EXQ_V1_8822B 0xfff\n#define BIT_EXQ_V1_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_EXQ_V1_8822B) << BIT_SHIFT_EXQ_V1_8822B)\n#define BITS_EXQ_V1_8822B (BIT_MASK_EXQ_V1_8822B << BIT_SHIFT_EXQ_V1_8822B)\n#define BIT_CLEAR_EXQ_V1_8822B(x) ((x) & (~BITS_EXQ_V1_8822B))\n#define BIT_GET_EXQ_V1_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_EXQ_V1_8822B) & BIT_MASK_EXQ_V1_8822B)\n#define BIT_SET_EXQ_V1_8822B(x, v)                                             \\\n\t(BIT_CLEAR_EXQ_V1_8822B(x) | BIT_EXQ_V1_8822B(v))\n\n/* 2 REG_FIFOPAGE_INFO_5_8822B */\n\n#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B 16\n#define BIT_MASK_PUBQ_AVAL_PG_V1_8822B 0xfff\n#define BIT_PUBQ_AVAL_PG_V1_8822B(x)                                           \\\n\t(((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8822B)                                \\\n\t << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B)\n#define BITS_PUBQ_AVAL_PG_V1_8822B                                             \\\n\t(BIT_MASK_PUBQ_AVAL_PG_V1_8822B << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B)\n#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8822B))\n#define BIT_GET_PUBQ_AVAL_PG_V1_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B) &                            \\\n\t BIT_MASK_PUBQ_AVAL_PG_V1_8822B)\n#define BIT_SET_PUBQ_AVAL_PG_V1_8822B(x, v)                                    \\\n\t(BIT_CLEAR_PUBQ_AVAL_PG_V1_8822B(x) | BIT_PUBQ_AVAL_PG_V1_8822B(v))\n\n#define BIT_SHIFT_PUBQ_V1_8822B 0\n#define BIT_MASK_PUBQ_V1_8822B 0xfff\n#define BIT_PUBQ_V1_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_PUBQ_V1_8822B) << BIT_SHIFT_PUBQ_V1_8822B)\n#define BITS_PUBQ_V1_8822B (BIT_MASK_PUBQ_V1_8822B << BIT_SHIFT_PUBQ_V1_8822B)\n#define BIT_CLEAR_PUBQ_V1_8822B(x) ((x) & (~BITS_PUBQ_V1_8822B))\n#define BIT_GET_PUBQ_V1_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_PUBQ_V1_8822B) & BIT_MASK_PUBQ_V1_8822B)\n#define BIT_SET_PUBQ_V1_8822B(x, v)                                            \\\n\t(BIT_CLEAR_PUBQ_V1_8822B(x) | BIT_PUBQ_V1_8822B(v))\n\n/* 2 REG_H2C_HEAD_8822B */\n\n#define BIT_SHIFT_H2C_HEAD_8822B 0\n#define BIT_MASK_H2C_HEAD_8822B 0x3ffff\n#define BIT_H2C_HEAD_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_H2C_HEAD_8822B) << BIT_SHIFT_H2C_HEAD_8822B)\n#define BITS_H2C_HEAD_8822B                                                    \\\n\t(BIT_MASK_H2C_HEAD_8822B << BIT_SHIFT_H2C_HEAD_8822B)\n#define BIT_CLEAR_H2C_HEAD_8822B(x) ((x) & (~BITS_H2C_HEAD_8822B))\n#define BIT_GET_H2C_HEAD_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_H2C_HEAD_8822B) & BIT_MASK_H2C_HEAD_8822B)\n#define BIT_SET_H2C_HEAD_8822B(x, v)                                           \\\n\t(BIT_CLEAR_H2C_HEAD_8822B(x) | BIT_H2C_HEAD_8822B(v))\n\n/* 2 REG_H2C_TAIL_8822B */\n\n#define BIT_SHIFT_H2C_TAIL_8822B 0\n#define BIT_MASK_H2C_TAIL_8822B 0x3ffff\n#define BIT_H2C_TAIL_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_H2C_TAIL_8822B) << BIT_SHIFT_H2C_TAIL_8822B)\n#define BITS_H2C_TAIL_8822B                                                    \\\n\t(BIT_MASK_H2C_TAIL_8822B << BIT_SHIFT_H2C_TAIL_8822B)\n#define BIT_CLEAR_H2C_TAIL_8822B(x) ((x) & (~BITS_H2C_TAIL_8822B))\n#define BIT_GET_H2C_TAIL_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_H2C_TAIL_8822B) & BIT_MASK_H2C_TAIL_8822B)\n#define BIT_SET_H2C_TAIL_8822B(x, v)                                           \\\n\t(BIT_CLEAR_H2C_TAIL_8822B(x) | BIT_H2C_TAIL_8822B(v))\n\n/* 2 REG_H2C_READ_ADDR_8822B */\n\n#define BIT_SHIFT_H2C_READ_ADDR_8822B 0\n#define BIT_MASK_H2C_READ_ADDR_8822B 0x3ffff\n#define BIT_H2C_READ_ADDR_8822B(x)                                             \\\n\t(((x) & BIT_MASK_H2C_READ_ADDR_8822B) << BIT_SHIFT_H2C_READ_ADDR_8822B)\n#define BITS_H2C_READ_ADDR_8822B                                               \\\n\t(BIT_MASK_H2C_READ_ADDR_8822B << BIT_SHIFT_H2C_READ_ADDR_8822B)\n#define BIT_CLEAR_H2C_READ_ADDR_8822B(x) ((x) & (~BITS_H2C_READ_ADDR_8822B))\n#define BIT_GET_H2C_READ_ADDR_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_H2C_READ_ADDR_8822B) & BIT_MASK_H2C_READ_ADDR_8822B)\n#define BIT_SET_H2C_READ_ADDR_8822B(x, v)                                      \\\n\t(BIT_CLEAR_H2C_READ_ADDR_8822B(x) | BIT_H2C_READ_ADDR_8822B(v))\n\n/* 2 REG_H2C_WR_ADDR_8822B */\n\n#define BIT_SHIFT_H2C_WR_ADDR_8822B 0\n#define BIT_MASK_H2C_WR_ADDR_8822B 0x3ffff\n#define BIT_H2C_WR_ADDR_8822B(x)                                               \\\n\t(((x) & BIT_MASK_H2C_WR_ADDR_8822B) << BIT_SHIFT_H2C_WR_ADDR_8822B)\n#define BITS_H2C_WR_ADDR_8822B                                                 \\\n\t(BIT_MASK_H2C_WR_ADDR_8822B << BIT_SHIFT_H2C_WR_ADDR_8822B)\n#define BIT_CLEAR_H2C_WR_ADDR_8822B(x) ((x) & (~BITS_H2C_WR_ADDR_8822B))\n#define BIT_GET_H2C_WR_ADDR_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_H2C_WR_ADDR_8822B) & BIT_MASK_H2C_WR_ADDR_8822B)\n#define BIT_SET_H2C_WR_ADDR_8822B(x, v)                                        \\\n\t(BIT_CLEAR_H2C_WR_ADDR_8822B(x) | BIT_H2C_WR_ADDR_8822B(v))\n\n/* 2 REG_H2C_INFO_8822B */\n#define BIT_H2C_SPACE_VLD_8822B BIT(3)\n#define BIT_H2C_WR_ADDR_RST_8822B BIT(2)\n\n#define BIT_SHIFT_H2C_LEN_SEL_8822B 0\n#define BIT_MASK_H2C_LEN_SEL_8822B 0x3\n#define BIT_H2C_LEN_SEL_8822B(x)                                               \\\n\t(((x) & BIT_MASK_H2C_LEN_SEL_8822B) << BIT_SHIFT_H2C_LEN_SEL_8822B)\n#define BITS_H2C_LEN_SEL_8822B                                                 \\\n\t(BIT_MASK_H2C_LEN_SEL_8822B << BIT_SHIFT_H2C_LEN_SEL_8822B)\n#define BIT_CLEAR_H2C_LEN_SEL_8822B(x) ((x) & (~BITS_H2C_LEN_SEL_8822B))\n#define BIT_GET_H2C_LEN_SEL_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_H2C_LEN_SEL_8822B) & BIT_MASK_H2C_LEN_SEL_8822B)\n#define BIT_SET_H2C_LEN_SEL_8822B(x, v)                                        \\\n\t(BIT_CLEAR_H2C_LEN_SEL_8822B(x) | BIT_H2C_LEN_SEL_8822B(v))\n\n/* 2 REG_RXDMA_AGG_PG_TH_8822B */\n#define BIT_USB_RXDMA_AGG_EN_8822B BIT(31)\n#define BIT_EN_PRE_CALC_8822B BIT(29)\n#define BIT_RXAGG_SW_EN_8822B BIT(28)\n#define BIT_RXAGG_SW_TRIG_8822B BIT(27)\n\n#define BIT_SHIFT_PKT_NUM_WOL_8822B 16\n#define BIT_MASK_PKT_NUM_WOL_8822B 0xff\n#define BIT_PKT_NUM_WOL_8822B(x)                                               \\\n\t(((x) & BIT_MASK_PKT_NUM_WOL_8822B) << BIT_SHIFT_PKT_NUM_WOL_8822B)\n#define BITS_PKT_NUM_WOL_8822B                                                 \\\n\t(BIT_MASK_PKT_NUM_WOL_8822B << BIT_SHIFT_PKT_NUM_WOL_8822B)\n#define BIT_CLEAR_PKT_NUM_WOL_8822B(x) ((x) & (~BITS_PKT_NUM_WOL_8822B))\n#define BIT_GET_PKT_NUM_WOL_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_WOL_8822B) & BIT_MASK_PKT_NUM_WOL_8822B)\n#define BIT_SET_PKT_NUM_WOL_8822B(x, v)                                        \\\n\t(BIT_CLEAR_PKT_NUM_WOL_8822B(x) | BIT_PKT_NUM_WOL_8822B(v))\n\n#define BIT_SHIFT_DMA_AGG_TO_V1_8822B 8\n#define BIT_MASK_DMA_AGG_TO_V1_8822B 0xff\n#define BIT_DMA_AGG_TO_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_DMA_AGG_TO_V1_8822B) << BIT_SHIFT_DMA_AGG_TO_V1_8822B)\n#define BITS_DMA_AGG_TO_V1_8822B                                               \\\n\t(BIT_MASK_DMA_AGG_TO_V1_8822B << BIT_SHIFT_DMA_AGG_TO_V1_8822B)\n#define BIT_CLEAR_DMA_AGG_TO_V1_8822B(x) ((x) & (~BITS_DMA_AGG_TO_V1_8822B))\n#define BIT_GET_DMA_AGG_TO_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8822B) & BIT_MASK_DMA_AGG_TO_V1_8822B)\n#define BIT_SET_DMA_AGG_TO_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_DMA_AGG_TO_V1_8822B(x) | BIT_DMA_AGG_TO_V1_8822B(v))\n\n#define BIT_SHIFT_RXDMA_AGG_PG_TH_8822B 0\n#define BIT_MASK_RXDMA_AGG_PG_TH_8822B 0xff\n#define BIT_RXDMA_AGG_PG_TH_8822B(x)                                           \\\n\t(((x) & BIT_MASK_RXDMA_AGG_PG_TH_8822B)                                \\\n\t << BIT_SHIFT_RXDMA_AGG_PG_TH_8822B)\n#define BITS_RXDMA_AGG_PG_TH_8822B                                             \\\n\t(BIT_MASK_RXDMA_AGG_PG_TH_8822B << BIT_SHIFT_RXDMA_AGG_PG_TH_8822B)\n#define BIT_CLEAR_RXDMA_AGG_PG_TH_8822B(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8822B))\n#define BIT_GET_RXDMA_AGG_PG_TH_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8822B) &                            \\\n\t BIT_MASK_RXDMA_AGG_PG_TH_8822B)\n#define BIT_SET_RXDMA_AGG_PG_TH_8822B(x, v)                                    \\\n\t(BIT_CLEAR_RXDMA_AGG_PG_TH_8822B(x) | BIT_RXDMA_AGG_PG_TH_8822B(v))\n\n/* 2 REG_RXPKT_NUM_8822B */\n\n#define BIT_SHIFT_RXPKT_NUM_8822B 24\n#define BIT_MASK_RXPKT_NUM_8822B 0xff\n#define BIT_RXPKT_NUM_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_RXPKT_NUM_8822B) << BIT_SHIFT_RXPKT_NUM_8822B)\n#define BITS_RXPKT_NUM_8822B                                                   \\\n\t(BIT_MASK_RXPKT_NUM_8822B << BIT_SHIFT_RXPKT_NUM_8822B)\n#define BIT_CLEAR_RXPKT_NUM_8822B(x) ((x) & (~BITS_RXPKT_NUM_8822B))\n#define BIT_GET_RXPKT_NUM_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_RXPKT_NUM_8822B) & BIT_MASK_RXPKT_NUM_8822B)\n#define BIT_SET_RXPKT_NUM_8822B(x, v)                                          \\\n\t(BIT_CLEAR_RXPKT_NUM_8822B(x) | BIT_RXPKT_NUM_8822B(v))\n\n#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B 20\n#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B 0xf\n#define BIT_FW_UPD_RDPTR19_TO_16_8822B(x)                                      \\\n\t(((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B)                           \\\n\t << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B)\n#define BITS_FW_UPD_RDPTR19_TO_16_8822B                                        \\\n\t(BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B                                   \\\n\t << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B)\n#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822B(x)                                \\\n\t((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8822B))\n#define BIT_GET_FW_UPD_RDPTR19_TO_16_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B) &                       \\\n\t BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B)\n#define BIT_SET_FW_UPD_RDPTR19_TO_16_8822B(x, v)                               \\\n\t(BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822B(x) |                             \\\n\t BIT_FW_UPD_RDPTR19_TO_16_8822B(v))\n\n#define BIT_RXDMA_REQ_8822B BIT(19)\n#define BIT_RW_RELEASE_EN_8822B BIT(18)\n#define BIT_RXDMA_IDLE_8822B BIT(17)\n#define BIT_RXPKT_RELEASE_POLL_8822B BIT(16)\n\n#define BIT_SHIFT_FW_UPD_RDPTR_8822B 0\n#define BIT_MASK_FW_UPD_RDPTR_8822B 0xffff\n#define BIT_FW_UPD_RDPTR_8822B(x)                                              \\\n\t(((x) & BIT_MASK_FW_UPD_RDPTR_8822B) << BIT_SHIFT_FW_UPD_RDPTR_8822B)\n#define BITS_FW_UPD_RDPTR_8822B                                                \\\n\t(BIT_MASK_FW_UPD_RDPTR_8822B << BIT_SHIFT_FW_UPD_RDPTR_8822B)\n#define BIT_CLEAR_FW_UPD_RDPTR_8822B(x) ((x) & (~BITS_FW_UPD_RDPTR_8822B))\n#define BIT_GET_FW_UPD_RDPTR_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_FW_UPD_RDPTR_8822B) & BIT_MASK_FW_UPD_RDPTR_8822B)\n#define BIT_SET_FW_UPD_RDPTR_8822B(x, v)                                       \\\n\t(BIT_CLEAR_FW_UPD_RDPTR_8822B(x) | BIT_FW_UPD_RDPTR_8822B(v))\n\n/* 2 REG_RXDMA_STATUS_8822B */\n#define BIT_C2H_PKT_OVF_8822B BIT(7)\n#define BIT_AGG_CONFGI_ISSUE_8822B BIT(6)\n#define BIT_FW_POLL_ISSUE_8822B BIT(5)\n#define BIT_RX_DATA_UDN_8822B BIT(4)\n#define BIT_RX_SFF_UDN_8822B BIT(3)\n#define BIT_RX_SFF_OVF_8822B BIT(2)\n#define BIT_RXPKT_OVF_8822B BIT(0)\n\n/* 2 REG_RXDMA_DPR_8822B */\n\n#define BIT_SHIFT_RDE_DEBUG_8822B 0\n#define BIT_MASK_RDE_DEBUG_8822B 0xffffffffL\n#define BIT_RDE_DEBUG_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_RDE_DEBUG_8822B) << BIT_SHIFT_RDE_DEBUG_8822B)\n#define BITS_RDE_DEBUG_8822B                                                   \\\n\t(BIT_MASK_RDE_DEBUG_8822B << BIT_SHIFT_RDE_DEBUG_8822B)\n#define BIT_CLEAR_RDE_DEBUG_8822B(x) ((x) & (~BITS_RDE_DEBUG_8822B))\n#define BIT_GET_RDE_DEBUG_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_RDE_DEBUG_8822B) & BIT_MASK_RDE_DEBUG_8822B)\n#define BIT_SET_RDE_DEBUG_8822B(x, v)                                          \\\n\t(BIT_CLEAR_RDE_DEBUG_8822B(x) | BIT_RDE_DEBUG_8822B(v))\n\n/* 2 REG_RXDMA_MODE_8822B */\n\n#define BIT_SHIFT_PKTNUM_TH_V2_8822B 24\n#define BIT_MASK_PKTNUM_TH_V2_8822B 0x1f\n#define BIT_PKTNUM_TH_V2_8822B(x)                                              \\\n\t(((x) & BIT_MASK_PKTNUM_TH_V2_8822B) << BIT_SHIFT_PKTNUM_TH_V2_8822B)\n#define BITS_PKTNUM_TH_V2_8822B                                                \\\n\t(BIT_MASK_PKTNUM_TH_V2_8822B << BIT_SHIFT_PKTNUM_TH_V2_8822B)\n#define BIT_CLEAR_PKTNUM_TH_V2_8822B(x) ((x) & (~BITS_PKTNUM_TH_V2_8822B))\n#define BIT_GET_PKTNUM_TH_V2_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_PKTNUM_TH_V2_8822B) & BIT_MASK_PKTNUM_TH_V2_8822B)\n#define BIT_SET_PKTNUM_TH_V2_8822B(x, v)                                       \\\n\t(BIT_CLEAR_PKTNUM_TH_V2_8822B(x) | BIT_PKTNUM_TH_V2_8822B(v))\n\n#define BIT_TXBA_BREAK_USBAGG_8822B BIT(23)\n\n#define BIT_SHIFT_PKTLEN_PARA_8822B 16\n#define BIT_MASK_PKTLEN_PARA_8822B 0x7\n#define BIT_PKTLEN_PARA_8822B(x)                                               \\\n\t(((x) & BIT_MASK_PKTLEN_PARA_8822B) << BIT_SHIFT_PKTLEN_PARA_8822B)\n#define BITS_PKTLEN_PARA_8822B                                                 \\\n\t(BIT_MASK_PKTLEN_PARA_8822B << BIT_SHIFT_PKTLEN_PARA_8822B)\n#define BIT_CLEAR_PKTLEN_PARA_8822B(x) ((x) & (~BITS_PKTLEN_PARA_8822B))\n#define BIT_GET_PKTLEN_PARA_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_PKTLEN_PARA_8822B) & BIT_MASK_PKTLEN_PARA_8822B)\n#define BIT_SET_PKTLEN_PARA_8822B(x, v)                                        \\\n\t(BIT_CLEAR_PKTLEN_PARA_8822B(x) | BIT_PKTLEN_PARA_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n#define BIT_SHIFT_BURST_SIZE_8822B 4\n#define BIT_MASK_BURST_SIZE_8822B 0x3\n#define BIT_BURST_SIZE_8822B(x)                                                \\\n\t(((x) & BIT_MASK_BURST_SIZE_8822B) << BIT_SHIFT_BURST_SIZE_8822B)\n#define BITS_BURST_SIZE_8822B                                                  \\\n\t(BIT_MASK_BURST_SIZE_8822B << BIT_SHIFT_BURST_SIZE_8822B)\n#define BIT_CLEAR_BURST_SIZE_8822B(x) ((x) & (~BITS_BURST_SIZE_8822B))\n#define BIT_GET_BURST_SIZE_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_BURST_SIZE_8822B) & BIT_MASK_BURST_SIZE_8822B)\n#define BIT_SET_BURST_SIZE_8822B(x, v)                                         \\\n\t(BIT_CLEAR_BURST_SIZE_8822B(x) | BIT_BURST_SIZE_8822B(v))\n\n#define BIT_SHIFT_BURST_CNT_8822B 2\n#define BIT_MASK_BURST_CNT_8822B 0x3\n#define BIT_BURST_CNT_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_BURST_CNT_8822B) << BIT_SHIFT_BURST_CNT_8822B)\n#define BITS_BURST_CNT_8822B                                                   \\\n\t(BIT_MASK_BURST_CNT_8822B << BIT_SHIFT_BURST_CNT_8822B)\n#define BIT_CLEAR_BURST_CNT_8822B(x) ((x) & (~BITS_BURST_CNT_8822B))\n#define BIT_GET_BURST_CNT_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_BURST_CNT_8822B) & BIT_MASK_BURST_CNT_8822B)\n#define BIT_SET_BURST_CNT_8822B(x, v)                                          \\\n\t(BIT_CLEAR_BURST_CNT_8822B(x) | BIT_BURST_CNT_8822B(v))\n\n#define BIT_DMA_MODE_8822B BIT(1)\n\n/* 2 REG_C2H_PKT_8822B */\n\n#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B 24\n#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B 0xf\n#define BIT_R_C2H_STR_ADDR_16_TO_19_8822B(x)                                   \\\n\t(((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B)                        \\\n\t << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B)\n#define BITS_R_C2H_STR_ADDR_16_TO_19_8822B                                     \\\n\t(BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B                                \\\n\t << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B)\n#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822B(x)                             \\\n\t((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8822B))\n#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8822B(x)                               \\\n\t(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B) &                    \\\n\t BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B)\n#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8822B(x, v)                            \\\n\t(BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822B(x) |                          \\\n\t BIT_R_C2H_STR_ADDR_16_TO_19_8822B(v))\n\n#define BIT_R_C2H_PKT_REQ_8822B BIT(16)\n\n#define BIT_SHIFT_R_C2H_STR_ADDR_8822B 0\n#define BIT_MASK_R_C2H_STR_ADDR_8822B 0xffff\n#define BIT_R_C2H_STR_ADDR_8822B(x)                                            \\\n\t(((x) & BIT_MASK_R_C2H_STR_ADDR_8822B)                                 \\\n\t << BIT_SHIFT_R_C2H_STR_ADDR_8822B)\n#define BITS_R_C2H_STR_ADDR_8822B                                              \\\n\t(BIT_MASK_R_C2H_STR_ADDR_8822B << BIT_SHIFT_R_C2H_STR_ADDR_8822B)\n#define BIT_CLEAR_R_C2H_STR_ADDR_8822B(x) ((x) & (~BITS_R_C2H_STR_ADDR_8822B))\n#define BIT_GET_R_C2H_STR_ADDR_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8822B) &                             \\\n\t BIT_MASK_R_C2H_STR_ADDR_8822B)\n#define BIT_SET_R_C2H_STR_ADDR_8822B(x, v)                                     \\\n\t(BIT_CLEAR_R_C2H_STR_ADDR_8822B(x) | BIT_R_C2H_STR_ADDR_8822B(v))\n\n/* 2 REG_FWFF_C2H_8822B */\n\n#define BIT_SHIFT_C2H_DMA_ADDR_8822B 0\n#define BIT_MASK_C2H_DMA_ADDR_8822B 0x3ffff\n#define BIT_C2H_DMA_ADDR_8822B(x)                                              \\\n\t(((x) & BIT_MASK_C2H_DMA_ADDR_8822B) << BIT_SHIFT_C2H_DMA_ADDR_8822B)\n#define BITS_C2H_DMA_ADDR_8822B                                                \\\n\t(BIT_MASK_C2H_DMA_ADDR_8822B << BIT_SHIFT_C2H_DMA_ADDR_8822B)\n#define BIT_CLEAR_C2H_DMA_ADDR_8822B(x) ((x) & (~BITS_C2H_DMA_ADDR_8822B))\n#define BIT_GET_C2H_DMA_ADDR_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_C2H_DMA_ADDR_8822B) & BIT_MASK_C2H_DMA_ADDR_8822B)\n#define BIT_SET_C2H_DMA_ADDR_8822B(x, v)                                       \\\n\t(BIT_CLEAR_C2H_DMA_ADDR_8822B(x) | BIT_C2H_DMA_ADDR_8822B(v))\n\n/* 2 REG_FWFF_CTRL_8822B */\n#define BIT_FWFF_DMAPKT_REQ_8822B BIT(31)\n\n#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B 16\n#define BIT_MASK_FWFF_DMA_PKT_NUM_8822B 0xff\n#define BIT_FWFF_DMA_PKT_NUM_8822B(x)                                          \\\n\t(((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8822B)                               \\\n\t << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B)\n#define BITS_FWFF_DMA_PKT_NUM_8822B                                            \\\n\t(BIT_MASK_FWFF_DMA_PKT_NUM_8822B << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B)\n#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8822B(x)                                    \\\n\t((x) & (~BITS_FWFF_DMA_PKT_NUM_8822B))\n#define BIT_GET_FWFF_DMA_PKT_NUM_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B) &                           \\\n\t BIT_MASK_FWFF_DMA_PKT_NUM_8822B)\n#define BIT_SET_FWFF_DMA_PKT_NUM_8822B(x, v)                                   \\\n\t(BIT_CLEAR_FWFF_DMA_PKT_NUM_8822B(x) | BIT_FWFF_DMA_PKT_NUM_8822B(v))\n\n#define BIT_SHIFT_FWFF_STR_ADDR_8822B 0\n#define BIT_MASK_FWFF_STR_ADDR_8822B 0xffff\n#define BIT_FWFF_STR_ADDR_8822B(x)                                             \\\n\t(((x) & BIT_MASK_FWFF_STR_ADDR_8822B) << BIT_SHIFT_FWFF_STR_ADDR_8822B)\n#define BITS_FWFF_STR_ADDR_8822B                                               \\\n\t(BIT_MASK_FWFF_STR_ADDR_8822B << BIT_SHIFT_FWFF_STR_ADDR_8822B)\n#define BIT_CLEAR_FWFF_STR_ADDR_8822B(x) ((x) & (~BITS_FWFF_STR_ADDR_8822B))\n#define BIT_GET_FWFF_STR_ADDR_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_FWFF_STR_ADDR_8822B) & BIT_MASK_FWFF_STR_ADDR_8822B)\n#define BIT_SET_FWFF_STR_ADDR_8822B(x, v)                                      \\\n\t(BIT_CLEAR_FWFF_STR_ADDR_8822B(x) | BIT_FWFF_STR_ADDR_8822B(v))\n\n/* 2 REG_FWFF_PKT_INFO_8822B */\n\n#define BIT_SHIFT_FWFF_PKT_QUEUED_8822B 16\n#define BIT_MASK_FWFF_PKT_QUEUED_8822B 0xff\n#define BIT_FWFF_PKT_QUEUED_8822B(x)                                           \\\n\t(((x) & BIT_MASK_FWFF_PKT_QUEUED_8822B)                                \\\n\t << BIT_SHIFT_FWFF_PKT_QUEUED_8822B)\n#define BITS_FWFF_PKT_QUEUED_8822B                                             \\\n\t(BIT_MASK_FWFF_PKT_QUEUED_8822B << BIT_SHIFT_FWFF_PKT_QUEUED_8822B)\n#define BIT_CLEAR_FWFF_PKT_QUEUED_8822B(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8822B))\n#define BIT_GET_FWFF_PKT_QUEUED_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8822B) &                            \\\n\t BIT_MASK_FWFF_PKT_QUEUED_8822B)\n#define BIT_SET_FWFF_PKT_QUEUED_8822B(x, v)                                    \\\n\t(BIT_CLEAR_FWFF_PKT_QUEUED_8822B(x) | BIT_FWFF_PKT_QUEUED_8822B(v))\n\n#define BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B 0\n#define BIT_MASK_FWFF_PKT_STR_ADDR_8822B 0xffff\n#define BIT_FWFF_PKT_STR_ADDR_8822B(x)                                         \\\n\t(((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8822B)                              \\\n\t << BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B)\n#define BITS_FWFF_PKT_STR_ADDR_8822B                                           \\\n\t(BIT_MASK_FWFF_PKT_STR_ADDR_8822B << BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B)\n#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8822B(x)                                   \\\n\t((x) & (~BITS_FWFF_PKT_STR_ADDR_8822B))\n#define BIT_GET_FWFF_PKT_STR_ADDR_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B) &                          \\\n\t BIT_MASK_FWFF_PKT_STR_ADDR_8822B)\n#define BIT_SET_FWFF_PKT_STR_ADDR_8822B(x, v)                                  \\\n\t(BIT_CLEAR_FWFF_PKT_STR_ADDR_8822B(x) | BIT_FWFF_PKT_STR_ADDR_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_DDMA_CH0SA_8822B */\n\n#define BIT_SHIFT_DDMACH0_SA_8822B 0\n#define BIT_MASK_DDMACH0_SA_8822B 0xffffffffL\n#define BIT_DDMACH0_SA_8822B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH0_SA_8822B) << BIT_SHIFT_DDMACH0_SA_8822B)\n#define BITS_DDMACH0_SA_8822B                                                  \\\n\t(BIT_MASK_DDMACH0_SA_8822B << BIT_SHIFT_DDMACH0_SA_8822B)\n#define BIT_CLEAR_DDMACH0_SA_8822B(x) ((x) & (~BITS_DDMACH0_SA_8822B))\n#define BIT_GET_DDMACH0_SA_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH0_SA_8822B) & BIT_MASK_DDMACH0_SA_8822B)\n#define BIT_SET_DDMACH0_SA_8822B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH0_SA_8822B(x) | BIT_DDMACH0_SA_8822B(v))\n\n/* 2 REG_DDMA_CH0DA_8822B */\n\n#define BIT_SHIFT_DDMACH0_DA_8822B 0\n#define BIT_MASK_DDMACH0_DA_8822B 0xffffffffL\n#define BIT_DDMACH0_DA_8822B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH0_DA_8822B) << BIT_SHIFT_DDMACH0_DA_8822B)\n#define BITS_DDMACH0_DA_8822B                                                  \\\n\t(BIT_MASK_DDMACH0_DA_8822B << BIT_SHIFT_DDMACH0_DA_8822B)\n#define BIT_CLEAR_DDMACH0_DA_8822B(x) ((x) & (~BITS_DDMACH0_DA_8822B))\n#define BIT_GET_DDMACH0_DA_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH0_DA_8822B) & BIT_MASK_DDMACH0_DA_8822B)\n#define BIT_SET_DDMACH0_DA_8822B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH0_DA_8822B(x) | BIT_DDMACH0_DA_8822B(v))\n\n/* 2 REG_DDMA_CH0CTRL_8822B */\n#define BIT_DDMACH0_OWN_8822B BIT(31)\n#define BIT_DDMACH0_IDMEM_ERR_8822B BIT(30)\n#define BIT_DDMACH0_CHKSUM_EN_8822B BIT(29)\n#define BIT_DDMACH0_DA_W_DISABLE_8822B BIT(28)\n#define BIT_DDMACH0_CHKSUM_STS_8822B BIT(27)\n#define BIT_DDMACH0_DDMA_MODE_8822B BIT(26)\n#define BIT_DDMACH0_RESET_CHKSUM_STS_8822B BIT(25)\n#define BIT_DDMACH0_CHKSUM_CONT_8822B BIT(24)\n\n#define BIT_SHIFT_DDMACH0_DLEN_8822B 0\n#define BIT_MASK_DDMACH0_DLEN_8822B 0x3ffff\n#define BIT_DDMACH0_DLEN_8822B(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH0_DLEN_8822B) << BIT_SHIFT_DDMACH0_DLEN_8822B)\n#define BITS_DDMACH0_DLEN_8822B                                                \\\n\t(BIT_MASK_DDMACH0_DLEN_8822B << BIT_SHIFT_DDMACH0_DLEN_8822B)\n#define BIT_CLEAR_DDMACH0_DLEN_8822B(x) ((x) & (~BITS_DDMACH0_DLEN_8822B))\n#define BIT_GET_DDMACH0_DLEN_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH0_DLEN_8822B) & BIT_MASK_DDMACH0_DLEN_8822B)\n#define BIT_SET_DDMACH0_DLEN_8822B(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH0_DLEN_8822B(x) | BIT_DDMACH0_DLEN_8822B(v))\n\n/* 2 REG_DDMA_CH1SA_8822B */\n\n#define BIT_SHIFT_DDMACH1_SA_8822B 0\n#define BIT_MASK_DDMACH1_SA_8822B 0xffffffffL\n#define BIT_DDMACH1_SA_8822B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH1_SA_8822B) << BIT_SHIFT_DDMACH1_SA_8822B)\n#define BITS_DDMACH1_SA_8822B                                                  \\\n\t(BIT_MASK_DDMACH1_SA_8822B << BIT_SHIFT_DDMACH1_SA_8822B)\n#define BIT_CLEAR_DDMACH1_SA_8822B(x) ((x) & (~BITS_DDMACH1_SA_8822B))\n#define BIT_GET_DDMACH1_SA_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH1_SA_8822B) & BIT_MASK_DDMACH1_SA_8822B)\n#define BIT_SET_DDMACH1_SA_8822B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH1_SA_8822B(x) | BIT_DDMACH1_SA_8822B(v))\n\n/* 2 REG_DDMA_CH1DA_8822B */\n\n#define BIT_SHIFT_DDMACH1_DA_8822B 0\n#define BIT_MASK_DDMACH1_DA_8822B 0xffffffffL\n#define BIT_DDMACH1_DA_8822B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH1_DA_8822B) << BIT_SHIFT_DDMACH1_DA_8822B)\n#define BITS_DDMACH1_DA_8822B                                                  \\\n\t(BIT_MASK_DDMACH1_DA_8822B << BIT_SHIFT_DDMACH1_DA_8822B)\n#define BIT_CLEAR_DDMACH1_DA_8822B(x) ((x) & (~BITS_DDMACH1_DA_8822B))\n#define BIT_GET_DDMACH1_DA_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH1_DA_8822B) & BIT_MASK_DDMACH1_DA_8822B)\n#define BIT_SET_DDMACH1_DA_8822B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH1_DA_8822B(x) | BIT_DDMACH1_DA_8822B(v))\n\n/* 2 REG_DDMA_CH1CTRL_8822B */\n#define BIT_DDMACH1_OWN_8822B BIT(31)\n#define BIT_DDMACH1_IDMEM_ERR_8822B BIT(30)\n#define BIT_DDMACH1_CHKSUM_EN_8822B BIT(29)\n#define BIT_DDMACH1_DA_W_DISABLE_8822B BIT(28)\n#define BIT_DDMACH1_CHKSUM_STS_8822B BIT(27)\n#define BIT_DDMACH1_DDMA_MODE_8822B BIT(26)\n#define BIT_DDMACH1_RESET_CHKSUM_STS_8822B BIT(25)\n#define BIT_DDMACH1_CHKSUM_CONT_8822B BIT(24)\n\n#define BIT_SHIFT_DDMACH1_DLEN_8822B 0\n#define BIT_MASK_DDMACH1_DLEN_8822B 0x3ffff\n#define BIT_DDMACH1_DLEN_8822B(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH1_DLEN_8822B) << BIT_SHIFT_DDMACH1_DLEN_8822B)\n#define BITS_DDMACH1_DLEN_8822B                                                \\\n\t(BIT_MASK_DDMACH1_DLEN_8822B << BIT_SHIFT_DDMACH1_DLEN_8822B)\n#define BIT_CLEAR_DDMACH1_DLEN_8822B(x) ((x) & (~BITS_DDMACH1_DLEN_8822B))\n#define BIT_GET_DDMACH1_DLEN_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH1_DLEN_8822B) & BIT_MASK_DDMACH1_DLEN_8822B)\n#define BIT_SET_DDMACH1_DLEN_8822B(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH1_DLEN_8822B(x) | BIT_DDMACH1_DLEN_8822B(v))\n\n/* 2 REG_DDMA_CH2SA_8822B */\n\n#define BIT_SHIFT_DDMACH2_SA_8822B 0\n#define BIT_MASK_DDMACH2_SA_8822B 0xffffffffL\n#define BIT_DDMACH2_SA_8822B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH2_SA_8822B) << BIT_SHIFT_DDMACH2_SA_8822B)\n#define BITS_DDMACH2_SA_8822B                                                  \\\n\t(BIT_MASK_DDMACH2_SA_8822B << BIT_SHIFT_DDMACH2_SA_8822B)\n#define BIT_CLEAR_DDMACH2_SA_8822B(x) ((x) & (~BITS_DDMACH2_SA_8822B))\n#define BIT_GET_DDMACH2_SA_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH2_SA_8822B) & BIT_MASK_DDMACH2_SA_8822B)\n#define BIT_SET_DDMACH2_SA_8822B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH2_SA_8822B(x) | BIT_DDMACH2_SA_8822B(v))\n\n/* 2 REG_DDMA_CH2DA_8822B */\n\n#define BIT_SHIFT_DDMACH2_DA_8822B 0\n#define BIT_MASK_DDMACH2_DA_8822B 0xffffffffL\n#define BIT_DDMACH2_DA_8822B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH2_DA_8822B) << BIT_SHIFT_DDMACH2_DA_8822B)\n#define BITS_DDMACH2_DA_8822B                                                  \\\n\t(BIT_MASK_DDMACH2_DA_8822B << BIT_SHIFT_DDMACH2_DA_8822B)\n#define BIT_CLEAR_DDMACH2_DA_8822B(x) ((x) & (~BITS_DDMACH2_DA_8822B))\n#define BIT_GET_DDMACH2_DA_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH2_DA_8822B) & BIT_MASK_DDMACH2_DA_8822B)\n#define BIT_SET_DDMACH2_DA_8822B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH2_DA_8822B(x) | BIT_DDMACH2_DA_8822B(v))\n\n/* 2 REG_DDMA_CH2CTRL_8822B */\n#define BIT_DDMACH2_OWN_8822B BIT(31)\n#define BIT_DDMACH2_IDMEM_ERR_8822B BIT(30)\n#define BIT_DDMACH2_CHKSUM_EN_8822B BIT(29)\n#define BIT_DDMACH2_DA_W_DISABLE_8822B BIT(28)\n#define BIT_DDMACH2_CHKSUM_STS_8822B BIT(27)\n#define BIT_DDMACH2_DDMA_MODE_8822B BIT(26)\n#define BIT_DDMACH2_RESET_CHKSUM_STS_8822B BIT(25)\n#define BIT_DDMACH2_CHKSUM_CONT_8822B BIT(24)\n\n#define BIT_SHIFT_DDMACH2_DLEN_8822B 0\n#define BIT_MASK_DDMACH2_DLEN_8822B 0x3ffff\n#define BIT_DDMACH2_DLEN_8822B(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH2_DLEN_8822B) << BIT_SHIFT_DDMACH2_DLEN_8822B)\n#define BITS_DDMACH2_DLEN_8822B                                                \\\n\t(BIT_MASK_DDMACH2_DLEN_8822B << BIT_SHIFT_DDMACH2_DLEN_8822B)\n#define BIT_CLEAR_DDMACH2_DLEN_8822B(x) ((x) & (~BITS_DDMACH2_DLEN_8822B))\n#define BIT_GET_DDMACH2_DLEN_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH2_DLEN_8822B) & BIT_MASK_DDMACH2_DLEN_8822B)\n#define BIT_SET_DDMACH2_DLEN_8822B(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH2_DLEN_8822B(x) | BIT_DDMACH2_DLEN_8822B(v))\n\n/* 2 REG_DDMA_CH3SA_8822B */\n\n#define BIT_SHIFT_DDMACH3_SA_8822B 0\n#define BIT_MASK_DDMACH3_SA_8822B 0xffffffffL\n#define BIT_DDMACH3_SA_8822B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH3_SA_8822B) << BIT_SHIFT_DDMACH3_SA_8822B)\n#define BITS_DDMACH3_SA_8822B                                                  \\\n\t(BIT_MASK_DDMACH3_SA_8822B << BIT_SHIFT_DDMACH3_SA_8822B)\n#define BIT_CLEAR_DDMACH3_SA_8822B(x) ((x) & (~BITS_DDMACH3_SA_8822B))\n#define BIT_GET_DDMACH3_SA_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH3_SA_8822B) & BIT_MASK_DDMACH3_SA_8822B)\n#define BIT_SET_DDMACH3_SA_8822B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH3_SA_8822B(x) | BIT_DDMACH3_SA_8822B(v))\n\n/* 2 REG_DDMA_CH3DA_8822B */\n\n#define BIT_SHIFT_DDMACH3_DA_8822B 0\n#define BIT_MASK_DDMACH3_DA_8822B 0xffffffffL\n#define BIT_DDMACH3_DA_8822B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH3_DA_8822B) << BIT_SHIFT_DDMACH3_DA_8822B)\n#define BITS_DDMACH3_DA_8822B                                                  \\\n\t(BIT_MASK_DDMACH3_DA_8822B << BIT_SHIFT_DDMACH3_DA_8822B)\n#define BIT_CLEAR_DDMACH3_DA_8822B(x) ((x) & (~BITS_DDMACH3_DA_8822B))\n#define BIT_GET_DDMACH3_DA_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH3_DA_8822B) & BIT_MASK_DDMACH3_DA_8822B)\n#define BIT_SET_DDMACH3_DA_8822B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH3_DA_8822B(x) | BIT_DDMACH3_DA_8822B(v))\n\n/* 2 REG_DDMA_CH3CTRL_8822B */\n#define BIT_DDMACH3_OWN_8822B BIT(31)\n#define BIT_DDMACH3_IDMEM_ERR_8822B BIT(30)\n#define BIT_DDMACH3_CHKSUM_EN_8822B BIT(29)\n#define BIT_DDMACH3_DA_W_DISABLE_8822B BIT(28)\n#define BIT_DDMACH3_CHKSUM_STS_8822B BIT(27)\n#define BIT_DDMACH3_DDMA_MODE_8822B BIT(26)\n#define BIT_DDMACH3_RESET_CHKSUM_STS_8822B BIT(25)\n#define BIT_DDMACH3_CHKSUM_CONT_8822B BIT(24)\n\n#define BIT_SHIFT_DDMACH3_DLEN_8822B 0\n#define BIT_MASK_DDMACH3_DLEN_8822B 0x3ffff\n#define BIT_DDMACH3_DLEN_8822B(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH3_DLEN_8822B) << BIT_SHIFT_DDMACH3_DLEN_8822B)\n#define BITS_DDMACH3_DLEN_8822B                                                \\\n\t(BIT_MASK_DDMACH3_DLEN_8822B << BIT_SHIFT_DDMACH3_DLEN_8822B)\n#define BIT_CLEAR_DDMACH3_DLEN_8822B(x) ((x) & (~BITS_DDMACH3_DLEN_8822B))\n#define BIT_GET_DDMACH3_DLEN_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH3_DLEN_8822B) & BIT_MASK_DDMACH3_DLEN_8822B)\n#define BIT_SET_DDMACH3_DLEN_8822B(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH3_DLEN_8822B(x) | BIT_DDMACH3_DLEN_8822B(v))\n\n/* 2 REG_DDMA_CH4SA_8822B */\n\n#define BIT_SHIFT_DDMACH4_SA_8822B 0\n#define BIT_MASK_DDMACH4_SA_8822B 0xffffffffL\n#define BIT_DDMACH4_SA_8822B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH4_SA_8822B) << BIT_SHIFT_DDMACH4_SA_8822B)\n#define BITS_DDMACH4_SA_8822B                                                  \\\n\t(BIT_MASK_DDMACH4_SA_8822B << BIT_SHIFT_DDMACH4_SA_8822B)\n#define BIT_CLEAR_DDMACH4_SA_8822B(x) ((x) & (~BITS_DDMACH4_SA_8822B))\n#define BIT_GET_DDMACH4_SA_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH4_SA_8822B) & BIT_MASK_DDMACH4_SA_8822B)\n#define BIT_SET_DDMACH4_SA_8822B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH4_SA_8822B(x) | BIT_DDMACH4_SA_8822B(v))\n\n/* 2 REG_DDMA_CH4DA_8822B */\n\n#define BIT_SHIFT_DDMACH4_DA_8822B 0\n#define BIT_MASK_DDMACH4_DA_8822B 0xffffffffL\n#define BIT_DDMACH4_DA_8822B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH4_DA_8822B) << BIT_SHIFT_DDMACH4_DA_8822B)\n#define BITS_DDMACH4_DA_8822B                                                  \\\n\t(BIT_MASK_DDMACH4_DA_8822B << BIT_SHIFT_DDMACH4_DA_8822B)\n#define BIT_CLEAR_DDMACH4_DA_8822B(x) ((x) & (~BITS_DDMACH4_DA_8822B))\n#define BIT_GET_DDMACH4_DA_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH4_DA_8822B) & BIT_MASK_DDMACH4_DA_8822B)\n#define BIT_SET_DDMACH4_DA_8822B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH4_DA_8822B(x) | BIT_DDMACH4_DA_8822B(v))\n\n/* 2 REG_DDMA_CH4CTRL_8822B */\n#define BIT_DDMACH4_OWN_8822B BIT(31)\n#define BIT_DDMACH4_IDMEM_ERR_8822B BIT(30)\n#define BIT_DDMACH4_CHKSUM_EN_8822B BIT(29)\n#define BIT_DDMACH4_DA_W_DISABLE_8822B BIT(28)\n#define BIT_DDMACH4_CHKSUM_STS_8822B BIT(27)\n#define BIT_DDMACH4_DDMA_MODE_8822B BIT(26)\n#define BIT_DDMACH4_RESET_CHKSUM_STS_8822B BIT(25)\n#define BIT_DDMACH4_CHKSUM_CONT_8822B BIT(24)\n\n#define BIT_SHIFT_DDMACH4_DLEN_8822B 0\n#define BIT_MASK_DDMACH4_DLEN_8822B 0x3ffff\n#define BIT_DDMACH4_DLEN_8822B(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH4_DLEN_8822B) << BIT_SHIFT_DDMACH4_DLEN_8822B)\n#define BITS_DDMACH4_DLEN_8822B                                                \\\n\t(BIT_MASK_DDMACH4_DLEN_8822B << BIT_SHIFT_DDMACH4_DLEN_8822B)\n#define BIT_CLEAR_DDMACH4_DLEN_8822B(x) ((x) & (~BITS_DDMACH4_DLEN_8822B))\n#define BIT_GET_DDMACH4_DLEN_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH4_DLEN_8822B) & BIT_MASK_DDMACH4_DLEN_8822B)\n#define BIT_SET_DDMACH4_DLEN_8822B(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH4_DLEN_8822B(x) | BIT_DDMACH4_DLEN_8822B(v))\n\n/* 2 REG_DDMA_CH5SA_8822B */\n\n#define BIT_SHIFT_DDMACH5_SA_8822B 0\n#define BIT_MASK_DDMACH5_SA_8822B 0xffffffffL\n#define BIT_DDMACH5_SA_8822B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH5_SA_8822B) << BIT_SHIFT_DDMACH5_SA_8822B)\n#define BITS_DDMACH5_SA_8822B                                                  \\\n\t(BIT_MASK_DDMACH5_SA_8822B << BIT_SHIFT_DDMACH5_SA_8822B)\n#define BIT_CLEAR_DDMACH5_SA_8822B(x) ((x) & (~BITS_DDMACH5_SA_8822B))\n#define BIT_GET_DDMACH5_SA_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH5_SA_8822B) & BIT_MASK_DDMACH5_SA_8822B)\n#define BIT_SET_DDMACH5_SA_8822B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH5_SA_8822B(x) | BIT_DDMACH5_SA_8822B(v))\n\n/* 2 REG_DDMA_CH5DA_8822B */\n\n#define BIT_SHIFT_DDMACH5_DA_8822B 0\n#define BIT_MASK_DDMACH5_DA_8822B 0xffffffffL\n#define BIT_DDMACH5_DA_8822B(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH5_DA_8822B) << BIT_SHIFT_DDMACH5_DA_8822B)\n#define BITS_DDMACH5_DA_8822B                                                  \\\n\t(BIT_MASK_DDMACH5_DA_8822B << BIT_SHIFT_DDMACH5_DA_8822B)\n#define BIT_CLEAR_DDMACH5_DA_8822B(x) ((x) & (~BITS_DDMACH5_DA_8822B))\n#define BIT_GET_DDMACH5_DA_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH5_DA_8822B) & BIT_MASK_DDMACH5_DA_8822B)\n#define BIT_SET_DDMACH5_DA_8822B(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH5_DA_8822B(x) | BIT_DDMACH5_DA_8822B(v))\n\n/* 2 REG_REG_DDMA_CH5CTRL_8822B */\n#define BIT_DDMACH5_OWN_8822B BIT(31)\n#define BIT_DDMACH5_IDMEM_ERR_8822B BIT(30)\n#define BIT_DDMACH5_CHKSUM_EN_8822B BIT(29)\n#define BIT_DDMACH5_DA_W_DISABLE_8822B BIT(28)\n#define BIT_DDMACH5_CHKSUM_STS_8822B BIT(27)\n#define BIT_DDMACH5_DDMA_MODE_8822B BIT(26)\n#define BIT_DDMACH5_RESET_CHKSUM_STS_8822B BIT(25)\n#define BIT_DDMACH5_CHKSUM_CONT_8822B BIT(24)\n\n#define BIT_SHIFT_DDMACH5_DLEN_8822B 0\n#define BIT_MASK_DDMACH5_DLEN_8822B 0x3ffff\n#define BIT_DDMACH5_DLEN_8822B(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH5_DLEN_8822B) << BIT_SHIFT_DDMACH5_DLEN_8822B)\n#define BITS_DDMACH5_DLEN_8822B                                                \\\n\t(BIT_MASK_DDMACH5_DLEN_8822B << BIT_SHIFT_DDMACH5_DLEN_8822B)\n#define BIT_CLEAR_DDMACH5_DLEN_8822B(x) ((x) & (~BITS_DDMACH5_DLEN_8822B))\n#define BIT_GET_DDMACH5_DLEN_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH5_DLEN_8822B) & BIT_MASK_DDMACH5_DLEN_8822B)\n#define BIT_SET_DDMACH5_DLEN_8822B(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH5_DLEN_8822B(x) | BIT_DDMACH5_DLEN_8822B(v))\n\n/* 2 REG_DDMA_INT_MSK_8822B */\n#define BIT_DDMACH5_MSK_8822B BIT(5)\n#define BIT_DDMACH4_MSK_8822B BIT(4)\n#define BIT_DDMACH3_MSK_8822B BIT(3)\n#define BIT_DDMACH2_MSK_8822B BIT(2)\n#define BIT_DDMACH1_MSK_8822B BIT(1)\n#define BIT_DDMACH0_MSK_8822B BIT(0)\n\n/* 2 REG_DDMA_CHSTATUS_8822B */\n#define BIT_DDMACH5_BUSY_8822B BIT(5)\n#define BIT_DDMACH4_BUSY_8822B BIT(4)\n#define BIT_DDMACH3_BUSY_8822B BIT(3)\n#define BIT_DDMACH2_BUSY_8822B BIT(2)\n#define BIT_DDMACH1_BUSY_8822B BIT(1)\n#define BIT_DDMACH0_BUSY_8822B BIT(0)\n\n/* 2 REG_DDMA_CHKSUM_8822B */\n\n#define BIT_SHIFT_IDDMA0_CHKSUM_8822B 0\n#define BIT_MASK_IDDMA0_CHKSUM_8822B 0xffff\n#define BIT_IDDMA0_CHKSUM_8822B(x)                                             \\\n\t(((x) & BIT_MASK_IDDMA0_CHKSUM_8822B) << BIT_SHIFT_IDDMA0_CHKSUM_8822B)\n#define BITS_IDDMA0_CHKSUM_8822B                                               \\\n\t(BIT_MASK_IDDMA0_CHKSUM_8822B << BIT_SHIFT_IDDMA0_CHKSUM_8822B)\n#define BIT_CLEAR_IDDMA0_CHKSUM_8822B(x) ((x) & (~BITS_IDDMA0_CHKSUM_8822B))\n#define BIT_GET_IDDMA0_CHKSUM_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8822B) & BIT_MASK_IDDMA0_CHKSUM_8822B)\n#define BIT_SET_IDDMA0_CHKSUM_8822B(x, v)                                      \\\n\t(BIT_CLEAR_IDDMA0_CHKSUM_8822B(x) | BIT_IDDMA0_CHKSUM_8822B(v))\n\n/* 2 REG_DDMA_MONITOR_8822B */\n#define BIT_IDDMA0_PERMU_UNDERFLOW_8822B BIT(14)\n#define BIT_IDDMA0_FIFO_UNDERFLOW_8822B BIT(13)\n#define BIT_IDDMA0_FIFO_OVERFLOW_8822B BIT(12)\n#define BIT_CH5_ERR_8822B BIT(5)\n#define BIT_CH4_ERR_8822B BIT(4)\n#define BIT_CH3_ERR_8822B BIT(3)\n#define BIT_CH2_ERR_8822B BIT(2)\n#define BIT_CH1_ERR_8822B BIT(1)\n#define BIT_CH0_ERR_8822B BIT(0)\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_PCIE_CTRL_8822B */\n#define BIT_PCIEIO_PERSTB_SEL_8822B BIT(31)\n\n#define BIT_SHIFT_PCIE_MAX_RXDMA_8822B 28\n#define BIT_MASK_PCIE_MAX_RXDMA_8822B 0x7\n#define BIT_PCIE_MAX_RXDMA_8822B(x)                                            \\\n\t(((x) & BIT_MASK_PCIE_MAX_RXDMA_8822B)                                 \\\n\t << BIT_SHIFT_PCIE_MAX_RXDMA_8822B)\n#define BITS_PCIE_MAX_RXDMA_8822B                                              \\\n\t(BIT_MASK_PCIE_MAX_RXDMA_8822B << BIT_SHIFT_PCIE_MAX_RXDMA_8822B)\n#define BIT_CLEAR_PCIE_MAX_RXDMA_8822B(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8822B))\n#define BIT_GET_PCIE_MAX_RXDMA_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8822B) &                             \\\n\t BIT_MASK_PCIE_MAX_RXDMA_8822B)\n#define BIT_SET_PCIE_MAX_RXDMA_8822B(x, v)                                     \\\n\t(BIT_CLEAR_PCIE_MAX_RXDMA_8822B(x) | BIT_PCIE_MAX_RXDMA_8822B(v))\n\n#define BIT_MULRW_8822B BIT(27)\n\n#define BIT_SHIFT_PCIE_MAX_TXDMA_8822B 24\n#define BIT_MASK_PCIE_MAX_TXDMA_8822B 0x7\n#define BIT_PCIE_MAX_TXDMA_8822B(x)                                            \\\n\t(((x) & BIT_MASK_PCIE_MAX_TXDMA_8822B)                                 \\\n\t << BIT_SHIFT_PCIE_MAX_TXDMA_8822B)\n#define BITS_PCIE_MAX_TXDMA_8822B                                              \\\n\t(BIT_MASK_PCIE_MAX_TXDMA_8822B << BIT_SHIFT_PCIE_MAX_TXDMA_8822B)\n#define BIT_CLEAR_PCIE_MAX_TXDMA_8822B(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8822B))\n#define BIT_GET_PCIE_MAX_TXDMA_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8822B) &                             \\\n\t BIT_MASK_PCIE_MAX_TXDMA_8822B)\n#define BIT_SET_PCIE_MAX_TXDMA_8822B(x, v)                                     \\\n\t(BIT_CLEAR_PCIE_MAX_TXDMA_8822B(x) | BIT_PCIE_MAX_TXDMA_8822B(v))\n\n#define BIT_EN_CPL_TIMEOUT_PS_8822B BIT(22)\n#define BIT_REG_TXDMA_FAIL_PS_8822B BIT(21)\n#define BIT_PCIE_RST_TRXDMA_INTF_8822B BIT(20)\n#define BIT_EN_HWENTR_L1_8822B BIT(19)\n#define BIT_EN_ADV_CLKGATE_8822B BIT(18)\n#define BIT_PCIE_EN_SWENT_L23_8822B BIT(17)\n#define BIT_PCIE_EN_HWEXT_L1_8822B BIT(16)\n#define BIT_RX_CLOSE_EN_8822B BIT(15)\n#define BIT_STOP_BCNQ_8822B BIT(14)\n#define BIT_STOP_MGQ_8822B BIT(13)\n#define BIT_STOP_VOQ_8822B BIT(12)\n#define BIT_STOP_VIQ_8822B BIT(11)\n#define BIT_STOP_BEQ_8822B BIT(10)\n#define BIT_STOP_BKQ_8822B BIT(9)\n#define BIT_STOP_RXQ_8822B BIT(8)\n#define BIT_STOP_HI7Q_8822B BIT(7)\n#define BIT_STOP_HI6Q_8822B BIT(6)\n#define BIT_STOP_HI5Q_8822B BIT(5)\n#define BIT_STOP_HI4Q_8822B BIT(4)\n#define BIT_STOP_HI3Q_8822B BIT(3)\n#define BIT_STOP_HI2Q_8822B BIT(2)\n#define BIT_STOP_HI1Q_8822B BIT(1)\n#define BIT_STOP_HI0Q_8822B BIT(0)\n\n/* 2 REG_INT_MIG_8822B */\n\n#define BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B 28\n#define BIT_MASK_TXTTIMER_MATCH_NUM_8822B 0xf\n#define BIT_TXTTIMER_MATCH_NUM_8822B(x)                                        \\\n\t(((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8822B)                             \\\n\t << BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B)\n#define BITS_TXTTIMER_MATCH_NUM_8822B                                          \\\n\t(BIT_MASK_TXTTIMER_MATCH_NUM_8822B                                     \\\n\t << BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B)\n#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8822B(x)                                  \\\n\t((x) & (~BITS_TXTTIMER_MATCH_NUM_8822B))\n#define BIT_GET_TXTTIMER_MATCH_NUM_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B) &                         \\\n\t BIT_MASK_TXTTIMER_MATCH_NUM_8822B)\n#define BIT_SET_TXTTIMER_MATCH_NUM_8822B(x, v)                                 \\\n\t(BIT_CLEAR_TXTTIMER_MATCH_NUM_8822B(x) |                               \\\n\t BIT_TXTTIMER_MATCH_NUM_8822B(v))\n\n#define BIT_SHIFT_TXPKT_NUM_MATCH_8822B 24\n#define BIT_MASK_TXPKT_NUM_MATCH_8822B 0xf\n#define BIT_TXPKT_NUM_MATCH_8822B(x)                                           \\\n\t(((x) & BIT_MASK_TXPKT_NUM_MATCH_8822B)                                \\\n\t << BIT_SHIFT_TXPKT_NUM_MATCH_8822B)\n#define BITS_TXPKT_NUM_MATCH_8822B                                             \\\n\t(BIT_MASK_TXPKT_NUM_MATCH_8822B << BIT_SHIFT_TXPKT_NUM_MATCH_8822B)\n#define BIT_CLEAR_TXPKT_NUM_MATCH_8822B(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8822B))\n#define BIT_GET_TXPKT_NUM_MATCH_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8822B) &                            \\\n\t BIT_MASK_TXPKT_NUM_MATCH_8822B)\n#define BIT_SET_TXPKT_NUM_MATCH_8822B(x, v)                                    \\\n\t(BIT_CLEAR_TXPKT_NUM_MATCH_8822B(x) | BIT_TXPKT_NUM_MATCH_8822B(v))\n\n#define BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B 20\n#define BIT_MASK_RXTTIMER_MATCH_NUM_8822B 0xf\n#define BIT_RXTTIMER_MATCH_NUM_8822B(x)                                        \\\n\t(((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8822B)                             \\\n\t << BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B)\n#define BITS_RXTTIMER_MATCH_NUM_8822B                                          \\\n\t(BIT_MASK_RXTTIMER_MATCH_NUM_8822B                                     \\\n\t << BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B)\n#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8822B(x)                                  \\\n\t((x) & (~BITS_RXTTIMER_MATCH_NUM_8822B))\n#define BIT_GET_RXTTIMER_MATCH_NUM_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B) &                         \\\n\t BIT_MASK_RXTTIMER_MATCH_NUM_8822B)\n#define BIT_SET_RXTTIMER_MATCH_NUM_8822B(x, v)                                 \\\n\t(BIT_CLEAR_RXTTIMER_MATCH_NUM_8822B(x) |                               \\\n\t BIT_RXTTIMER_MATCH_NUM_8822B(v))\n\n#define BIT_SHIFT_RXPKT_NUM_MATCH_8822B 16\n#define BIT_MASK_RXPKT_NUM_MATCH_8822B 0xf\n#define BIT_RXPKT_NUM_MATCH_8822B(x)                                           \\\n\t(((x) & BIT_MASK_RXPKT_NUM_MATCH_8822B)                                \\\n\t << BIT_SHIFT_RXPKT_NUM_MATCH_8822B)\n#define BITS_RXPKT_NUM_MATCH_8822B                                             \\\n\t(BIT_MASK_RXPKT_NUM_MATCH_8822B << BIT_SHIFT_RXPKT_NUM_MATCH_8822B)\n#define BIT_CLEAR_RXPKT_NUM_MATCH_8822B(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8822B))\n#define BIT_GET_RXPKT_NUM_MATCH_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8822B) &                            \\\n\t BIT_MASK_RXPKT_NUM_MATCH_8822B)\n#define BIT_SET_RXPKT_NUM_MATCH_8822B(x, v)                                    \\\n\t(BIT_CLEAR_RXPKT_NUM_MATCH_8822B(x) | BIT_RXPKT_NUM_MATCH_8822B(v))\n\n#define BIT_SHIFT_MIGRATE_TIMER_8822B 0\n#define BIT_MASK_MIGRATE_TIMER_8822B 0xffff\n#define BIT_MIGRATE_TIMER_8822B(x)                                             \\\n\t(((x) & BIT_MASK_MIGRATE_TIMER_8822B) << BIT_SHIFT_MIGRATE_TIMER_8822B)\n#define BITS_MIGRATE_TIMER_8822B                                               \\\n\t(BIT_MASK_MIGRATE_TIMER_8822B << BIT_SHIFT_MIGRATE_TIMER_8822B)\n#define BIT_CLEAR_MIGRATE_TIMER_8822B(x) ((x) & (~BITS_MIGRATE_TIMER_8822B))\n#define BIT_GET_MIGRATE_TIMER_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MIGRATE_TIMER_8822B) & BIT_MASK_MIGRATE_TIMER_8822B)\n#define BIT_SET_MIGRATE_TIMER_8822B(x, v)                                      \\\n\t(BIT_CLEAR_MIGRATE_TIMER_8822B(x) | BIT_MIGRATE_TIMER_8822B(v))\n\n/* 2 REG_BCNQ_TXBD_DESA_8822B */\n\n#define BIT_SHIFT_BCNQ_TXBD_DESA_8822B 0\n#define BIT_MASK_BCNQ_TXBD_DESA_8822B 0xffffffffffffffffL\n#define BIT_BCNQ_TXBD_DESA_8822B(x)                                            \\\n\t(((x) & BIT_MASK_BCNQ_TXBD_DESA_8822B)                                 \\\n\t << BIT_SHIFT_BCNQ_TXBD_DESA_8822B)\n#define BITS_BCNQ_TXBD_DESA_8822B                                              \\\n\t(BIT_MASK_BCNQ_TXBD_DESA_8822B << BIT_SHIFT_BCNQ_TXBD_DESA_8822B)\n#define BIT_CLEAR_BCNQ_TXBD_DESA_8822B(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8822B))\n#define BIT_GET_BCNQ_TXBD_DESA_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8822B) &                             \\\n\t BIT_MASK_BCNQ_TXBD_DESA_8822B)\n#define BIT_SET_BCNQ_TXBD_DESA_8822B(x, v)                                     \\\n\t(BIT_CLEAR_BCNQ_TXBD_DESA_8822B(x) | BIT_BCNQ_TXBD_DESA_8822B(v))\n\n/* 2 REG_MGQ_TXBD_DESA_8822B */\n\n#define BIT_SHIFT_MGQ_TXBD_DESA_8822B 0\n#define BIT_MASK_MGQ_TXBD_DESA_8822B 0xffffffffffffffffL\n#define BIT_MGQ_TXBD_DESA_8822B(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_TXBD_DESA_8822B) << BIT_SHIFT_MGQ_TXBD_DESA_8822B)\n#define BITS_MGQ_TXBD_DESA_8822B                                               \\\n\t(BIT_MASK_MGQ_TXBD_DESA_8822B << BIT_SHIFT_MGQ_TXBD_DESA_8822B)\n#define BIT_CLEAR_MGQ_TXBD_DESA_8822B(x) ((x) & (~BITS_MGQ_TXBD_DESA_8822B))\n#define BIT_GET_MGQ_TXBD_DESA_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8822B) & BIT_MASK_MGQ_TXBD_DESA_8822B)\n#define BIT_SET_MGQ_TXBD_DESA_8822B(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_TXBD_DESA_8822B(x) | BIT_MGQ_TXBD_DESA_8822B(v))\n\n/* 2 REG_VOQ_TXBD_DESA_8822B */\n\n#define BIT_SHIFT_VOQ_TXBD_DESA_8822B 0\n#define BIT_MASK_VOQ_TXBD_DESA_8822B 0xffffffffffffffffL\n#define BIT_VOQ_TXBD_DESA_8822B(x)                                             \\\n\t(((x) & BIT_MASK_VOQ_TXBD_DESA_8822B) << BIT_SHIFT_VOQ_TXBD_DESA_8822B)\n#define BITS_VOQ_TXBD_DESA_8822B                                               \\\n\t(BIT_MASK_VOQ_TXBD_DESA_8822B << BIT_SHIFT_VOQ_TXBD_DESA_8822B)\n#define BIT_CLEAR_VOQ_TXBD_DESA_8822B(x) ((x) & (~BITS_VOQ_TXBD_DESA_8822B))\n#define BIT_GET_VOQ_TXBD_DESA_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8822B) & BIT_MASK_VOQ_TXBD_DESA_8822B)\n#define BIT_SET_VOQ_TXBD_DESA_8822B(x, v)                                      \\\n\t(BIT_CLEAR_VOQ_TXBD_DESA_8822B(x) | BIT_VOQ_TXBD_DESA_8822B(v))\n\n/* 2 REG_VIQ_TXBD_DESA_8822B */\n\n#define BIT_SHIFT_VIQ_TXBD_DESA_8822B 0\n#define BIT_MASK_VIQ_TXBD_DESA_8822B 0xffffffffffffffffL\n#define BIT_VIQ_TXBD_DESA_8822B(x)                                             \\\n\t(((x) & BIT_MASK_VIQ_TXBD_DESA_8822B) << BIT_SHIFT_VIQ_TXBD_DESA_8822B)\n#define BITS_VIQ_TXBD_DESA_8822B                                               \\\n\t(BIT_MASK_VIQ_TXBD_DESA_8822B << BIT_SHIFT_VIQ_TXBD_DESA_8822B)\n#define BIT_CLEAR_VIQ_TXBD_DESA_8822B(x) ((x) & (~BITS_VIQ_TXBD_DESA_8822B))\n#define BIT_GET_VIQ_TXBD_DESA_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8822B) & BIT_MASK_VIQ_TXBD_DESA_8822B)\n#define BIT_SET_VIQ_TXBD_DESA_8822B(x, v)                                      \\\n\t(BIT_CLEAR_VIQ_TXBD_DESA_8822B(x) | BIT_VIQ_TXBD_DESA_8822B(v))\n\n/* 2 REG_BEQ_TXBD_DESA_8822B */\n\n#define BIT_SHIFT_BEQ_TXBD_DESA_8822B 0\n#define BIT_MASK_BEQ_TXBD_DESA_8822B 0xffffffffffffffffL\n#define BIT_BEQ_TXBD_DESA_8822B(x)                                             \\\n\t(((x) & BIT_MASK_BEQ_TXBD_DESA_8822B) << BIT_SHIFT_BEQ_TXBD_DESA_8822B)\n#define BITS_BEQ_TXBD_DESA_8822B                                               \\\n\t(BIT_MASK_BEQ_TXBD_DESA_8822B << BIT_SHIFT_BEQ_TXBD_DESA_8822B)\n#define BIT_CLEAR_BEQ_TXBD_DESA_8822B(x) ((x) & (~BITS_BEQ_TXBD_DESA_8822B))\n#define BIT_GET_BEQ_TXBD_DESA_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8822B) & BIT_MASK_BEQ_TXBD_DESA_8822B)\n#define BIT_SET_BEQ_TXBD_DESA_8822B(x, v)                                      \\\n\t(BIT_CLEAR_BEQ_TXBD_DESA_8822B(x) | BIT_BEQ_TXBD_DESA_8822B(v))\n\n/* 2 REG_BKQ_TXBD_DESA_8822B */\n\n#define BIT_SHIFT_BKQ_TXBD_DESA_8822B 0\n#define BIT_MASK_BKQ_TXBD_DESA_8822B 0xffffffffffffffffL\n#define BIT_BKQ_TXBD_DESA_8822B(x)                                             \\\n\t(((x) & BIT_MASK_BKQ_TXBD_DESA_8822B) << BIT_SHIFT_BKQ_TXBD_DESA_8822B)\n#define BITS_BKQ_TXBD_DESA_8822B                                               \\\n\t(BIT_MASK_BKQ_TXBD_DESA_8822B << BIT_SHIFT_BKQ_TXBD_DESA_8822B)\n#define BIT_CLEAR_BKQ_TXBD_DESA_8822B(x) ((x) & (~BITS_BKQ_TXBD_DESA_8822B))\n#define BIT_GET_BKQ_TXBD_DESA_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8822B) & BIT_MASK_BKQ_TXBD_DESA_8822B)\n#define BIT_SET_BKQ_TXBD_DESA_8822B(x, v)                                      \\\n\t(BIT_CLEAR_BKQ_TXBD_DESA_8822B(x) | BIT_BKQ_TXBD_DESA_8822B(v))\n\n/* 2 REG_RXQ_RXBD_DESA_8822B */\n\n#define BIT_SHIFT_RXQ_RXBD_DESA_8822B 0\n#define BIT_MASK_RXQ_RXBD_DESA_8822B 0xffffffffffffffffL\n#define BIT_RXQ_RXBD_DESA_8822B(x)                                             \\\n\t(((x) & BIT_MASK_RXQ_RXBD_DESA_8822B) << BIT_SHIFT_RXQ_RXBD_DESA_8822B)\n#define BITS_RXQ_RXBD_DESA_8822B                                               \\\n\t(BIT_MASK_RXQ_RXBD_DESA_8822B << BIT_SHIFT_RXQ_RXBD_DESA_8822B)\n#define BIT_CLEAR_RXQ_RXBD_DESA_8822B(x) ((x) & (~BITS_RXQ_RXBD_DESA_8822B))\n#define BIT_GET_RXQ_RXBD_DESA_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8822B) & BIT_MASK_RXQ_RXBD_DESA_8822B)\n#define BIT_SET_RXQ_RXBD_DESA_8822B(x, v)                                      \\\n\t(BIT_CLEAR_RXQ_RXBD_DESA_8822B(x) | BIT_RXQ_RXBD_DESA_8822B(v))\n\n/* 2 REG_HI0Q_TXBD_DESA_8822B */\n\n#define BIT_SHIFT_HI0Q_TXBD_DESA_8822B 0\n#define BIT_MASK_HI0Q_TXBD_DESA_8822B 0xffffffffffffffffL\n#define BIT_HI0Q_TXBD_DESA_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HI0Q_TXBD_DESA_8822B)                                 \\\n\t << BIT_SHIFT_HI0Q_TXBD_DESA_8822B)\n#define BITS_HI0Q_TXBD_DESA_8822B                                              \\\n\t(BIT_MASK_HI0Q_TXBD_DESA_8822B << BIT_SHIFT_HI0Q_TXBD_DESA_8822B)\n#define BIT_CLEAR_HI0Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8822B))\n#define BIT_GET_HI0Q_TXBD_DESA_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8822B) &                             \\\n\t BIT_MASK_HI0Q_TXBD_DESA_8822B)\n#define BIT_SET_HI0Q_TXBD_DESA_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HI0Q_TXBD_DESA_8822B(x) | BIT_HI0Q_TXBD_DESA_8822B(v))\n\n/* 2 REG_HI1Q_TXBD_DESA_8822B */\n\n#define BIT_SHIFT_HI1Q_TXBD_DESA_8822B 0\n#define BIT_MASK_HI1Q_TXBD_DESA_8822B 0xffffffffffffffffL\n#define BIT_HI1Q_TXBD_DESA_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HI1Q_TXBD_DESA_8822B)                                 \\\n\t << BIT_SHIFT_HI1Q_TXBD_DESA_8822B)\n#define BITS_HI1Q_TXBD_DESA_8822B                                              \\\n\t(BIT_MASK_HI1Q_TXBD_DESA_8822B << BIT_SHIFT_HI1Q_TXBD_DESA_8822B)\n#define BIT_CLEAR_HI1Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8822B))\n#define BIT_GET_HI1Q_TXBD_DESA_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8822B) &                             \\\n\t BIT_MASK_HI1Q_TXBD_DESA_8822B)\n#define BIT_SET_HI1Q_TXBD_DESA_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HI1Q_TXBD_DESA_8822B(x) | BIT_HI1Q_TXBD_DESA_8822B(v))\n\n/* 2 REG_HI2Q_TXBD_DESA_8822B */\n\n#define BIT_SHIFT_HI2Q_TXBD_DESA_8822B 0\n#define BIT_MASK_HI2Q_TXBD_DESA_8822B 0xffffffffffffffffL\n#define BIT_HI2Q_TXBD_DESA_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HI2Q_TXBD_DESA_8822B)                                 \\\n\t << BIT_SHIFT_HI2Q_TXBD_DESA_8822B)\n#define BITS_HI2Q_TXBD_DESA_8822B                                              \\\n\t(BIT_MASK_HI2Q_TXBD_DESA_8822B << BIT_SHIFT_HI2Q_TXBD_DESA_8822B)\n#define BIT_CLEAR_HI2Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8822B))\n#define BIT_GET_HI2Q_TXBD_DESA_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8822B) &                             \\\n\t BIT_MASK_HI2Q_TXBD_DESA_8822B)\n#define BIT_SET_HI2Q_TXBD_DESA_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HI2Q_TXBD_DESA_8822B(x) | BIT_HI2Q_TXBD_DESA_8822B(v))\n\n/* 2 REG_HI3Q_TXBD_DESA_8822B */\n\n#define BIT_SHIFT_HI3Q_TXBD_DESA_8822B 0\n#define BIT_MASK_HI3Q_TXBD_DESA_8822B 0xffffffffffffffffL\n#define BIT_HI3Q_TXBD_DESA_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HI3Q_TXBD_DESA_8822B)                                 \\\n\t << BIT_SHIFT_HI3Q_TXBD_DESA_8822B)\n#define BITS_HI3Q_TXBD_DESA_8822B                                              \\\n\t(BIT_MASK_HI3Q_TXBD_DESA_8822B << BIT_SHIFT_HI3Q_TXBD_DESA_8822B)\n#define BIT_CLEAR_HI3Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8822B))\n#define BIT_GET_HI3Q_TXBD_DESA_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8822B) &                             \\\n\t BIT_MASK_HI3Q_TXBD_DESA_8822B)\n#define BIT_SET_HI3Q_TXBD_DESA_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HI3Q_TXBD_DESA_8822B(x) | BIT_HI3Q_TXBD_DESA_8822B(v))\n\n/* 2 REG_HI4Q_TXBD_DESA_8822B */\n\n#define BIT_SHIFT_HI4Q_TXBD_DESA_8822B 0\n#define BIT_MASK_HI4Q_TXBD_DESA_8822B 0xffffffffffffffffL\n#define BIT_HI4Q_TXBD_DESA_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HI4Q_TXBD_DESA_8822B)                                 \\\n\t << BIT_SHIFT_HI4Q_TXBD_DESA_8822B)\n#define BITS_HI4Q_TXBD_DESA_8822B                                              \\\n\t(BIT_MASK_HI4Q_TXBD_DESA_8822B << BIT_SHIFT_HI4Q_TXBD_DESA_8822B)\n#define BIT_CLEAR_HI4Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8822B))\n#define BIT_GET_HI4Q_TXBD_DESA_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8822B) &                             \\\n\t BIT_MASK_HI4Q_TXBD_DESA_8822B)\n#define BIT_SET_HI4Q_TXBD_DESA_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HI4Q_TXBD_DESA_8822B(x) | BIT_HI4Q_TXBD_DESA_8822B(v))\n\n/* 2 REG_HI5Q_TXBD_DESA_8822B */\n\n#define BIT_SHIFT_HI5Q_TXBD_DESA_8822B 0\n#define BIT_MASK_HI5Q_TXBD_DESA_8822B 0xffffffffffffffffL\n#define BIT_HI5Q_TXBD_DESA_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HI5Q_TXBD_DESA_8822B)                                 \\\n\t << BIT_SHIFT_HI5Q_TXBD_DESA_8822B)\n#define BITS_HI5Q_TXBD_DESA_8822B                                              \\\n\t(BIT_MASK_HI5Q_TXBD_DESA_8822B << BIT_SHIFT_HI5Q_TXBD_DESA_8822B)\n#define BIT_CLEAR_HI5Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8822B))\n#define BIT_GET_HI5Q_TXBD_DESA_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8822B) &                             \\\n\t BIT_MASK_HI5Q_TXBD_DESA_8822B)\n#define BIT_SET_HI5Q_TXBD_DESA_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HI5Q_TXBD_DESA_8822B(x) | BIT_HI5Q_TXBD_DESA_8822B(v))\n\n/* 2 REG_HI6Q_TXBD_DESA_8822B */\n\n#define BIT_SHIFT_HI6Q_TXBD_DESA_8822B 0\n#define BIT_MASK_HI6Q_TXBD_DESA_8822B 0xffffffffffffffffL\n#define BIT_HI6Q_TXBD_DESA_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HI6Q_TXBD_DESA_8822B)                                 \\\n\t << BIT_SHIFT_HI6Q_TXBD_DESA_8822B)\n#define BITS_HI6Q_TXBD_DESA_8822B                                              \\\n\t(BIT_MASK_HI6Q_TXBD_DESA_8822B << BIT_SHIFT_HI6Q_TXBD_DESA_8822B)\n#define BIT_CLEAR_HI6Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8822B))\n#define BIT_GET_HI6Q_TXBD_DESA_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8822B) &                             \\\n\t BIT_MASK_HI6Q_TXBD_DESA_8822B)\n#define BIT_SET_HI6Q_TXBD_DESA_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HI6Q_TXBD_DESA_8822B(x) | BIT_HI6Q_TXBD_DESA_8822B(v))\n\n/* 2 REG_HI7Q_TXBD_DESA_8822B */\n\n#define BIT_SHIFT_HI7Q_TXBD_DESA_8822B 0\n#define BIT_MASK_HI7Q_TXBD_DESA_8822B 0xffffffffffffffffL\n#define BIT_HI7Q_TXBD_DESA_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HI7Q_TXBD_DESA_8822B)                                 \\\n\t << BIT_SHIFT_HI7Q_TXBD_DESA_8822B)\n#define BITS_HI7Q_TXBD_DESA_8822B                                              \\\n\t(BIT_MASK_HI7Q_TXBD_DESA_8822B << BIT_SHIFT_HI7Q_TXBD_DESA_8822B)\n#define BIT_CLEAR_HI7Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8822B))\n#define BIT_GET_HI7Q_TXBD_DESA_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8822B) &                             \\\n\t BIT_MASK_HI7Q_TXBD_DESA_8822B)\n#define BIT_SET_HI7Q_TXBD_DESA_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HI7Q_TXBD_DESA_8822B(x) | BIT_HI7Q_TXBD_DESA_8822B(v))\n\n/* 2 REG_MGQ_TXBD_NUM_8822B */\n#define BIT_PCIE_MGQ_FLAG_8822B BIT(14)\n\n#define BIT_SHIFT_MGQ_DESC_MODE_8822B 12\n#define BIT_MASK_MGQ_DESC_MODE_8822B 0x3\n#define BIT_MGQ_DESC_MODE_8822B(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_DESC_MODE_8822B) << BIT_SHIFT_MGQ_DESC_MODE_8822B)\n#define BITS_MGQ_DESC_MODE_8822B                                               \\\n\t(BIT_MASK_MGQ_DESC_MODE_8822B << BIT_SHIFT_MGQ_DESC_MODE_8822B)\n#define BIT_CLEAR_MGQ_DESC_MODE_8822B(x) ((x) & (~BITS_MGQ_DESC_MODE_8822B))\n#define BIT_GET_MGQ_DESC_MODE_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_DESC_MODE_8822B) & BIT_MASK_MGQ_DESC_MODE_8822B)\n#define BIT_SET_MGQ_DESC_MODE_8822B(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_DESC_MODE_8822B(x) | BIT_MGQ_DESC_MODE_8822B(v))\n\n#define BIT_SHIFT_MGQ_DESC_NUM_8822B 0\n#define BIT_MASK_MGQ_DESC_NUM_8822B 0xfff\n#define BIT_MGQ_DESC_NUM_8822B(x)                                              \\\n\t(((x) & BIT_MASK_MGQ_DESC_NUM_8822B) << BIT_SHIFT_MGQ_DESC_NUM_8822B)\n#define BITS_MGQ_DESC_NUM_8822B                                                \\\n\t(BIT_MASK_MGQ_DESC_NUM_8822B << BIT_SHIFT_MGQ_DESC_NUM_8822B)\n#define BIT_CLEAR_MGQ_DESC_NUM_8822B(x) ((x) & (~BITS_MGQ_DESC_NUM_8822B))\n#define BIT_GET_MGQ_DESC_NUM_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_MGQ_DESC_NUM_8822B) & BIT_MASK_MGQ_DESC_NUM_8822B)\n#define BIT_SET_MGQ_DESC_NUM_8822B(x, v)                                       \\\n\t(BIT_CLEAR_MGQ_DESC_NUM_8822B(x) | BIT_MGQ_DESC_NUM_8822B(v))\n\n/* 2 REG_RX_RXBD_NUM_8822B */\n#define BIT_SYS_32_64_8822B BIT(15)\n\n#define BIT_SHIFT_BCNQ_DESC_MODE_8822B 13\n#define BIT_MASK_BCNQ_DESC_MODE_8822B 0x3\n#define BIT_BCNQ_DESC_MODE_8822B(x)                                            \\\n\t(((x) & BIT_MASK_BCNQ_DESC_MODE_8822B)                                 \\\n\t << BIT_SHIFT_BCNQ_DESC_MODE_8822B)\n#define BITS_BCNQ_DESC_MODE_8822B                                              \\\n\t(BIT_MASK_BCNQ_DESC_MODE_8822B << BIT_SHIFT_BCNQ_DESC_MODE_8822B)\n#define BIT_CLEAR_BCNQ_DESC_MODE_8822B(x) ((x) & (~BITS_BCNQ_DESC_MODE_8822B))\n#define BIT_GET_BCNQ_DESC_MODE_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8822B) &                             \\\n\t BIT_MASK_BCNQ_DESC_MODE_8822B)\n#define BIT_SET_BCNQ_DESC_MODE_8822B(x, v)                                     \\\n\t(BIT_CLEAR_BCNQ_DESC_MODE_8822B(x) | BIT_BCNQ_DESC_MODE_8822B(v))\n\n#define BIT_PCIE_BCNQ_FLAG_8822B BIT(12)\n\n#define BIT_SHIFT_RXQ_DESC_NUM_8822B 0\n#define BIT_MASK_RXQ_DESC_NUM_8822B 0xfff\n#define BIT_RXQ_DESC_NUM_8822B(x)                                              \\\n\t(((x) & BIT_MASK_RXQ_DESC_NUM_8822B) << BIT_SHIFT_RXQ_DESC_NUM_8822B)\n#define BITS_RXQ_DESC_NUM_8822B                                                \\\n\t(BIT_MASK_RXQ_DESC_NUM_8822B << BIT_SHIFT_RXQ_DESC_NUM_8822B)\n#define BIT_CLEAR_RXQ_DESC_NUM_8822B(x) ((x) & (~BITS_RXQ_DESC_NUM_8822B))\n#define BIT_GET_RXQ_DESC_NUM_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXQ_DESC_NUM_8822B) & BIT_MASK_RXQ_DESC_NUM_8822B)\n#define BIT_SET_RXQ_DESC_NUM_8822B(x, v)                                       \\\n\t(BIT_CLEAR_RXQ_DESC_NUM_8822B(x) | BIT_RXQ_DESC_NUM_8822B(v))\n\n/* 2 REG_VOQ_TXBD_NUM_8822B */\n#define BIT_PCIE_VOQ_FLAG_8822B BIT(14)\n\n#define BIT_SHIFT_VOQ_DESC_MODE_8822B 12\n#define BIT_MASK_VOQ_DESC_MODE_8822B 0x3\n#define BIT_VOQ_DESC_MODE_8822B(x)                                             \\\n\t(((x) & BIT_MASK_VOQ_DESC_MODE_8822B) << BIT_SHIFT_VOQ_DESC_MODE_8822B)\n#define BITS_VOQ_DESC_MODE_8822B                                               \\\n\t(BIT_MASK_VOQ_DESC_MODE_8822B << BIT_SHIFT_VOQ_DESC_MODE_8822B)\n#define BIT_CLEAR_VOQ_DESC_MODE_8822B(x) ((x) & (~BITS_VOQ_DESC_MODE_8822B))\n#define BIT_GET_VOQ_DESC_MODE_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_VOQ_DESC_MODE_8822B) & BIT_MASK_VOQ_DESC_MODE_8822B)\n#define BIT_SET_VOQ_DESC_MODE_8822B(x, v)                                      \\\n\t(BIT_CLEAR_VOQ_DESC_MODE_8822B(x) | BIT_VOQ_DESC_MODE_8822B(v))\n\n#define BIT_SHIFT_VOQ_DESC_NUM_8822B 0\n#define BIT_MASK_VOQ_DESC_NUM_8822B 0xfff\n#define BIT_VOQ_DESC_NUM_8822B(x)                                              \\\n\t(((x) & BIT_MASK_VOQ_DESC_NUM_8822B) << BIT_SHIFT_VOQ_DESC_NUM_8822B)\n#define BITS_VOQ_DESC_NUM_8822B                                                \\\n\t(BIT_MASK_VOQ_DESC_NUM_8822B << BIT_SHIFT_VOQ_DESC_NUM_8822B)\n#define BIT_CLEAR_VOQ_DESC_NUM_8822B(x) ((x) & (~BITS_VOQ_DESC_NUM_8822B))\n#define BIT_GET_VOQ_DESC_NUM_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_VOQ_DESC_NUM_8822B) & BIT_MASK_VOQ_DESC_NUM_8822B)\n#define BIT_SET_VOQ_DESC_NUM_8822B(x, v)                                       \\\n\t(BIT_CLEAR_VOQ_DESC_NUM_8822B(x) | BIT_VOQ_DESC_NUM_8822B(v))\n\n/* 2 REG_VIQ_TXBD_NUM_8822B */\n#define BIT_PCIE_VIQ_FLAG_8822B BIT(14)\n\n#define BIT_SHIFT_VIQ_DESC_MODE_8822B 12\n#define BIT_MASK_VIQ_DESC_MODE_8822B 0x3\n#define BIT_VIQ_DESC_MODE_8822B(x)                                             \\\n\t(((x) & BIT_MASK_VIQ_DESC_MODE_8822B) << BIT_SHIFT_VIQ_DESC_MODE_8822B)\n#define BITS_VIQ_DESC_MODE_8822B                                               \\\n\t(BIT_MASK_VIQ_DESC_MODE_8822B << BIT_SHIFT_VIQ_DESC_MODE_8822B)\n#define BIT_CLEAR_VIQ_DESC_MODE_8822B(x) ((x) & (~BITS_VIQ_DESC_MODE_8822B))\n#define BIT_GET_VIQ_DESC_MODE_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_VIQ_DESC_MODE_8822B) & BIT_MASK_VIQ_DESC_MODE_8822B)\n#define BIT_SET_VIQ_DESC_MODE_8822B(x, v)                                      \\\n\t(BIT_CLEAR_VIQ_DESC_MODE_8822B(x) | BIT_VIQ_DESC_MODE_8822B(v))\n\n#define BIT_SHIFT_VIQ_DESC_NUM_8822B 0\n#define BIT_MASK_VIQ_DESC_NUM_8822B 0xfff\n#define BIT_VIQ_DESC_NUM_8822B(x)                                              \\\n\t(((x) & BIT_MASK_VIQ_DESC_NUM_8822B) << BIT_SHIFT_VIQ_DESC_NUM_8822B)\n#define BITS_VIQ_DESC_NUM_8822B                                                \\\n\t(BIT_MASK_VIQ_DESC_NUM_8822B << BIT_SHIFT_VIQ_DESC_NUM_8822B)\n#define BIT_CLEAR_VIQ_DESC_NUM_8822B(x) ((x) & (~BITS_VIQ_DESC_NUM_8822B))\n#define BIT_GET_VIQ_DESC_NUM_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_VIQ_DESC_NUM_8822B) & BIT_MASK_VIQ_DESC_NUM_8822B)\n#define BIT_SET_VIQ_DESC_NUM_8822B(x, v)                                       \\\n\t(BIT_CLEAR_VIQ_DESC_NUM_8822B(x) | BIT_VIQ_DESC_NUM_8822B(v))\n\n/* 2 REG_BEQ_TXBD_NUM_8822B */\n#define BIT_PCIE_BEQ_FLAG_8822B BIT(14)\n\n#define BIT_SHIFT_BEQ_DESC_MODE_8822B 12\n#define BIT_MASK_BEQ_DESC_MODE_8822B 0x3\n#define BIT_BEQ_DESC_MODE_8822B(x)                                             \\\n\t(((x) & BIT_MASK_BEQ_DESC_MODE_8822B) << BIT_SHIFT_BEQ_DESC_MODE_8822B)\n#define BITS_BEQ_DESC_MODE_8822B                                               \\\n\t(BIT_MASK_BEQ_DESC_MODE_8822B << BIT_SHIFT_BEQ_DESC_MODE_8822B)\n#define BIT_CLEAR_BEQ_DESC_MODE_8822B(x) ((x) & (~BITS_BEQ_DESC_MODE_8822B))\n#define BIT_GET_BEQ_DESC_MODE_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_BEQ_DESC_MODE_8822B) & BIT_MASK_BEQ_DESC_MODE_8822B)\n#define BIT_SET_BEQ_DESC_MODE_8822B(x, v)                                      \\\n\t(BIT_CLEAR_BEQ_DESC_MODE_8822B(x) | BIT_BEQ_DESC_MODE_8822B(v))\n\n#define BIT_SHIFT_BEQ_DESC_NUM_8822B 0\n#define BIT_MASK_BEQ_DESC_NUM_8822B 0xfff\n#define BIT_BEQ_DESC_NUM_8822B(x)                                              \\\n\t(((x) & BIT_MASK_BEQ_DESC_NUM_8822B) << BIT_SHIFT_BEQ_DESC_NUM_8822B)\n#define BITS_BEQ_DESC_NUM_8822B                                                \\\n\t(BIT_MASK_BEQ_DESC_NUM_8822B << BIT_SHIFT_BEQ_DESC_NUM_8822B)\n#define BIT_CLEAR_BEQ_DESC_NUM_8822B(x) ((x) & (~BITS_BEQ_DESC_NUM_8822B))\n#define BIT_GET_BEQ_DESC_NUM_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BEQ_DESC_NUM_8822B) & BIT_MASK_BEQ_DESC_NUM_8822B)\n#define BIT_SET_BEQ_DESC_NUM_8822B(x, v)                                       \\\n\t(BIT_CLEAR_BEQ_DESC_NUM_8822B(x) | BIT_BEQ_DESC_NUM_8822B(v))\n\n/* 2 REG_BKQ_TXBD_NUM_8822B */\n#define BIT_PCIE_BKQ_FLAG_8822B BIT(14)\n\n#define BIT_SHIFT_BKQ_DESC_MODE_8822B 12\n#define BIT_MASK_BKQ_DESC_MODE_8822B 0x3\n#define BIT_BKQ_DESC_MODE_8822B(x)                                             \\\n\t(((x) & BIT_MASK_BKQ_DESC_MODE_8822B) << BIT_SHIFT_BKQ_DESC_MODE_8822B)\n#define BITS_BKQ_DESC_MODE_8822B                                               \\\n\t(BIT_MASK_BKQ_DESC_MODE_8822B << BIT_SHIFT_BKQ_DESC_MODE_8822B)\n#define BIT_CLEAR_BKQ_DESC_MODE_8822B(x) ((x) & (~BITS_BKQ_DESC_MODE_8822B))\n#define BIT_GET_BKQ_DESC_MODE_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_BKQ_DESC_MODE_8822B) & BIT_MASK_BKQ_DESC_MODE_8822B)\n#define BIT_SET_BKQ_DESC_MODE_8822B(x, v)                                      \\\n\t(BIT_CLEAR_BKQ_DESC_MODE_8822B(x) | BIT_BKQ_DESC_MODE_8822B(v))\n\n#define BIT_SHIFT_BKQ_DESC_NUM_8822B 0\n#define BIT_MASK_BKQ_DESC_NUM_8822B 0xfff\n#define BIT_BKQ_DESC_NUM_8822B(x)                                              \\\n\t(((x) & BIT_MASK_BKQ_DESC_NUM_8822B) << BIT_SHIFT_BKQ_DESC_NUM_8822B)\n#define BITS_BKQ_DESC_NUM_8822B                                                \\\n\t(BIT_MASK_BKQ_DESC_NUM_8822B << BIT_SHIFT_BKQ_DESC_NUM_8822B)\n#define BIT_CLEAR_BKQ_DESC_NUM_8822B(x) ((x) & (~BITS_BKQ_DESC_NUM_8822B))\n#define BIT_GET_BKQ_DESC_NUM_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BKQ_DESC_NUM_8822B) & BIT_MASK_BKQ_DESC_NUM_8822B)\n#define BIT_SET_BKQ_DESC_NUM_8822B(x, v)                                       \\\n\t(BIT_CLEAR_BKQ_DESC_NUM_8822B(x) | BIT_BKQ_DESC_NUM_8822B(v))\n\n/* 2 REG_HI0Q_TXBD_NUM_8822B */\n#define BIT_HI0Q_FLAG_8822B BIT(14)\n\n#define BIT_SHIFT_HI0Q_DESC_MODE_8822B 12\n#define BIT_MASK_HI0Q_DESC_MODE_8822B 0x3\n#define BIT_HI0Q_DESC_MODE_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HI0Q_DESC_MODE_8822B)                                 \\\n\t << BIT_SHIFT_HI0Q_DESC_MODE_8822B)\n#define BITS_HI0Q_DESC_MODE_8822B                                              \\\n\t(BIT_MASK_HI0Q_DESC_MODE_8822B << BIT_SHIFT_HI0Q_DESC_MODE_8822B)\n#define BIT_CLEAR_HI0Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI0Q_DESC_MODE_8822B))\n#define BIT_GET_HI0Q_DESC_MODE_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8822B) &                             \\\n\t BIT_MASK_HI0Q_DESC_MODE_8822B)\n#define BIT_SET_HI0Q_DESC_MODE_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HI0Q_DESC_MODE_8822B(x) | BIT_HI0Q_DESC_MODE_8822B(v))\n\n#define BIT_SHIFT_HI0Q_DESC_NUM_8822B 0\n#define BIT_MASK_HI0Q_DESC_NUM_8822B 0xfff\n#define BIT_HI0Q_DESC_NUM_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HI0Q_DESC_NUM_8822B) << BIT_SHIFT_HI0Q_DESC_NUM_8822B)\n#define BITS_HI0Q_DESC_NUM_8822B                                               \\\n\t(BIT_MASK_HI0Q_DESC_NUM_8822B << BIT_SHIFT_HI0Q_DESC_NUM_8822B)\n#define BIT_CLEAR_HI0Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI0Q_DESC_NUM_8822B))\n#define BIT_GET_HI0Q_DESC_NUM_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8822B) & BIT_MASK_HI0Q_DESC_NUM_8822B)\n#define BIT_SET_HI0Q_DESC_NUM_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HI0Q_DESC_NUM_8822B(x) | BIT_HI0Q_DESC_NUM_8822B(v))\n\n/* 2 REG_HI1Q_TXBD_NUM_8822B */\n#define BIT_HI1Q_FLAG_8822B BIT(14)\n\n#define BIT_SHIFT_HI1Q_DESC_MODE_8822B 12\n#define BIT_MASK_HI1Q_DESC_MODE_8822B 0x3\n#define BIT_HI1Q_DESC_MODE_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HI1Q_DESC_MODE_8822B)                                 \\\n\t << BIT_SHIFT_HI1Q_DESC_MODE_8822B)\n#define BITS_HI1Q_DESC_MODE_8822B                                              \\\n\t(BIT_MASK_HI1Q_DESC_MODE_8822B << BIT_SHIFT_HI1Q_DESC_MODE_8822B)\n#define BIT_CLEAR_HI1Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI1Q_DESC_MODE_8822B))\n#define BIT_GET_HI1Q_DESC_MODE_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8822B) &                             \\\n\t BIT_MASK_HI1Q_DESC_MODE_8822B)\n#define BIT_SET_HI1Q_DESC_MODE_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HI1Q_DESC_MODE_8822B(x) | BIT_HI1Q_DESC_MODE_8822B(v))\n\n#define BIT_SHIFT_HI1Q_DESC_NUM_8822B 0\n#define BIT_MASK_HI1Q_DESC_NUM_8822B 0xfff\n#define BIT_HI1Q_DESC_NUM_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HI1Q_DESC_NUM_8822B) << BIT_SHIFT_HI1Q_DESC_NUM_8822B)\n#define BITS_HI1Q_DESC_NUM_8822B                                               \\\n\t(BIT_MASK_HI1Q_DESC_NUM_8822B << BIT_SHIFT_HI1Q_DESC_NUM_8822B)\n#define BIT_CLEAR_HI1Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI1Q_DESC_NUM_8822B))\n#define BIT_GET_HI1Q_DESC_NUM_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8822B) & BIT_MASK_HI1Q_DESC_NUM_8822B)\n#define BIT_SET_HI1Q_DESC_NUM_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HI1Q_DESC_NUM_8822B(x) | BIT_HI1Q_DESC_NUM_8822B(v))\n\n/* 2 REG_HI2Q_TXBD_NUM_8822B */\n#define BIT_HI2Q_FLAG_8822B BIT(14)\n\n#define BIT_SHIFT_HI2Q_DESC_MODE_8822B 12\n#define BIT_MASK_HI2Q_DESC_MODE_8822B 0x3\n#define BIT_HI2Q_DESC_MODE_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HI2Q_DESC_MODE_8822B)                                 \\\n\t << BIT_SHIFT_HI2Q_DESC_MODE_8822B)\n#define BITS_HI2Q_DESC_MODE_8822B                                              \\\n\t(BIT_MASK_HI2Q_DESC_MODE_8822B << BIT_SHIFT_HI2Q_DESC_MODE_8822B)\n#define BIT_CLEAR_HI2Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI2Q_DESC_MODE_8822B))\n#define BIT_GET_HI2Q_DESC_MODE_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8822B) &                             \\\n\t BIT_MASK_HI2Q_DESC_MODE_8822B)\n#define BIT_SET_HI2Q_DESC_MODE_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HI2Q_DESC_MODE_8822B(x) | BIT_HI2Q_DESC_MODE_8822B(v))\n\n#define BIT_SHIFT_HI2Q_DESC_NUM_8822B 0\n#define BIT_MASK_HI2Q_DESC_NUM_8822B 0xfff\n#define BIT_HI2Q_DESC_NUM_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HI2Q_DESC_NUM_8822B) << BIT_SHIFT_HI2Q_DESC_NUM_8822B)\n#define BITS_HI2Q_DESC_NUM_8822B                                               \\\n\t(BIT_MASK_HI2Q_DESC_NUM_8822B << BIT_SHIFT_HI2Q_DESC_NUM_8822B)\n#define BIT_CLEAR_HI2Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI2Q_DESC_NUM_8822B))\n#define BIT_GET_HI2Q_DESC_NUM_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8822B) & BIT_MASK_HI2Q_DESC_NUM_8822B)\n#define BIT_SET_HI2Q_DESC_NUM_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HI2Q_DESC_NUM_8822B(x) | BIT_HI2Q_DESC_NUM_8822B(v))\n\n/* 2 REG_HI3Q_TXBD_NUM_8822B */\n#define BIT_HI3Q_FLAG_8822B BIT(14)\n\n#define BIT_SHIFT_HI3Q_DESC_MODE_8822B 12\n#define BIT_MASK_HI3Q_DESC_MODE_8822B 0x3\n#define BIT_HI3Q_DESC_MODE_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HI3Q_DESC_MODE_8822B)                                 \\\n\t << BIT_SHIFT_HI3Q_DESC_MODE_8822B)\n#define BITS_HI3Q_DESC_MODE_8822B                                              \\\n\t(BIT_MASK_HI3Q_DESC_MODE_8822B << BIT_SHIFT_HI3Q_DESC_MODE_8822B)\n#define BIT_CLEAR_HI3Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI3Q_DESC_MODE_8822B))\n#define BIT_GET_HI3Q_DESC_MODE_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8822B) &                             \\\n\t BIT_MASK_HI3Q_DESC_MODE_8822B)\n#define BIT_SET_HI3Q_DESC_MODE_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HI3Q_DESC_MODE_8822B(x) | BIT_HI3Q_DESC_MODE_8822B(v))\n\n#define BIT_SHIFT_HI3Q_DESC_NUM_8822B 0\n#define BIT_MASK_HI3Q_DESC_NUM_8822B 0xfff\n#define BIT_HI3Q_DESC_NUM_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HI3Q_DESC_NUM_8822B) << BIT_SHIFT_HI3Q_DESC_NUM_8822B)\n#define BITS_HI3Q_DESC_NUM_8822B                                               \\\n\t(BIT_MASK_HI3Q_DESC_NUM_8822B << BIT_SHIFT_HI3Q_DESC_NUM_8822B)\n#define BIT_CLEAR_HI3Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI3Q_DESC_NUM_8822B))\n#define BIT_GET_HI3Q_DESC_NUM_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8822B) & BIT_MASK_HI3Q_DESC_NUM_8822B)\n#define BIT_SET_HI3Q_DESC_NUM_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HI3Q_DESC_NUM_8822B(x) | BIT_HI3Q_DESC_NUM_8822B(v))\n\n/* 2 REG_HI4Q_TXBD_NUM_8822B */\n#define BIT_HI4Q_FLAG_8822B BIT(14)\n\n#define BIT_SHIFT_HI4Q_DESC_MODE_8822B 12\n#define BIT_MASK_HI4Q_DESC_MODE_8822B 0x3\n#define BIT_HI4Q_DESC_MODE_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HI4Q_DESC_MODE_8822B)                                 \\\n\t << BIT_SHIFT_HI4Q_DESC_MODE_8822B)\n#define BITS_HI4Q_DESC_MODE_8822B                                              \\\n\t(BIT_MASK_HI4Q_DESC_MODE_8822B << BIT_SHIFT_HI4Q_DESC_MODE_8822B)\n#define BIT_CLEAR_HI4Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI4Q_DESC_MODE_8822B))\n#define BIT_GET_HI4Q_DESC_MODE_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8822B) &                             \\\n\t BIT_MASK_HI4Q_DESC_MODE_8822B)\n#define BIT_SET_HI4Q_DESC_MODE_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HI4Q_DESC_MODE_8822B(x) | BIT_HI4Q_DESC_MODE_8822B(v))\n\n#define BIT_SHIFT_HI4Q_DESC_NUM_8822B 0\n#define BIT_MASK_HI4Q_DESC_NUM_8822B 0xfff\n#define BIT_HI4Q_DESC_NUM_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HI4Q_DESC_NUM_8822B) << BIT_SHIFT_HI4Q_DESC_NUM_8822B)\n#define BITS_HI4Q_DESC_NUM_8822B                                               \\\n\t(BIT_MASK_HI4Q_DESC_NUM_8822B << BIT_SHIFT_HI4Q_DESC_NUM_8822B)\n#define BIT_CLEAR_HI4Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI4Q_DESC_NUM_8822B))\n#define BIT_GET_HI4Q_DESC_NUM_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8822B) & BIT_MASK_HI4Q_DESC_NUM_8822B)\n#define BIT_SET_HI4Q_DESC_NUM_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HI4Q_DESC_NUM_8822B(x) | BIT_HI4Q_DESC_NUM_8822B(v))\n\n/* 2 REG_HI5Q_TXBD_NUM_8822B */\n#define BIT_HI5Q_FLAG_8822B BIT(14)\n\n#define BIT_SHIFT_HI5Q_DESC_MODE_8822B 12\n#define BIT_MASK_HI5Q_DESC_MODE_8822B 0x3\n#define BIT_HI5Q_DESC_MODE_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HI5Q_DESC_MODE_8822B)                                 \\\n\t << BIT_SHIFT_HI5Q_DESC_MODE_8822B)\n#define BITS_HI5Q_DESC_MODE_8822B                                              \\\n\t(BIT_MASK_HI5Q_DESC_MODE_8822B << BIT_SHIFT_HI5Q_DESC_MODE_8822B)\n#define BIT_CLEAR_HI5Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI5Q_DESC_MODE_8822B))\n#define BIT_GET_HI5Q_DESC_MODE_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8822B) &                             \\\n\t BIT_MASK_HI5Q_DESC_MODE_8822B)\n#define BIT_SET_HI5Q_DESC_MODE_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HI5Q_DESC_MODE_8822B(x) | BIT_HI5Q_DESC_MODE_8822B(v))\n\n#define BIT_SHIFT_HI5Q_DESC_NUM_8822B 0\n#define BIT_MASK_HI5Q_DESC_NUM_8822B 0xfff\n#define BIT_HI5Q_DESC_NUM_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HI5Q_DESC_NUM_8822B) << BIT_SHIFT_HI5Q_DESC_NUM_8822B)\n#define BITS_HI5Q_DESC_NUM_8822B                                               \\\n\t(BIT_MASK_HI5Q_DESC_NUM_8822B << BIT_SHIFT_HI5Q_DESC_NUM_8822B)\n#define BIT_CLEAR_HI5Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI5Q_DESC_NUM_8822B))\n#define BIT_GET_HI5Q_DESC_NUM_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8822B) & BIT_MASK_HI5Q_DESC_NUM_8822B)\n#define BIT_SET_HI5Q_DESC_NUM_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HI5Q_DESC_NUM_8822B(x) | BIT_HI5Q_DESC_NUM_8822B(v))\n\n/* 2 REG_HI6Q_TXBD_NUM_8822B */\n#define BIT_HI6Q_FLAG_8822B BIT(14)\n\n#define BIT_SHIFT_HI6Q_DESC_MODE_8822B 12\n#define BIT_MASK_HI6Q_DESC_MODE_8822B 0x3\n#define BIT_HI6Q_DESC_MODE_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HI6Q_DESC_MODE_8822B)                                 \\\n\t << BIT_SHIFT_HI6Q_DESC_MODE_8822B)\n#define BITS_HI6Q_DESC_MODE_8822B                                              \\\n\t(BIT_MASK_HI6Q_DESC_MODE_8822B << BIT_SHIFT_HI6Q_DESC_MODE_8822B)\n#define BIT_CLEAR_HI6Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI6Q_DESC_MODE_8822B))\n#define BIT_GET_HI6Q_DESC_MODE_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8822B) &                             \\\n\t BIT_MASK_HI6Q_DESC_MODE_8822B)\n#define BIT_SET_HI6Q_DESC_MODE_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HI6Q_DESC_MODE_8822B(x) | BIT_HI6Q_DESC_MODE_8822B(v))\n\n#define BIT_SHIFT_HI6Q_DESC_NUM_8822B 0\n#define BIT_MASK_HI6Q_DESC_NUM_8822B 0xfff\n#define BIT_HI6Q_DESC_NUM_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HI6Q_DESC_NUM_8822B) << BIT_SHIFT_HI6Q_DESC_NUM_8822B)\n#define BITS_HI6Q_DESC_NUM_8822B                                               \\\n\t(BIT_MASK_HI6Q_DESC_NUM_8822B << BIT_SHIFT_HI6Q_DESC_NUM_8822B)\n#define BIT_CLEAR_HI6Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI6Q_DESC_NUM_8822B))\n#define BIT_GET_HI6Q_DESC_NUM_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8822B) & BIT_MASK_HI6Q_DESC_NUM_8822B)\n#define BIT_SET_HI6Q_DESC_NUM_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HI6Q_DESC_NUM_8822B(x) | BIT_HI6Q_DESC_NUM_8822B(v))\n\n/* 2 REG_HI7Q_TXBD_NUM_8822B */\n#define BIT_HI7Q_FLAG_8822B BIT(14)\n\n#define BIT_SHIFT_HI7Q_DESC_MODE_8822B 12\n#define BIT_MASK_HI7Q_DESC_MODE_8822B 0x3\n#define BIT_HI7Q_DESC_MODE_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HI7Q_DESC_MODE_8822B)                                 \\\n\t << BIT_SHIFT_HI7Q_DESC_MODE_8822B)\n#define BITS_HI7Q_DESC_MODE_8822B                                              \\\n\t(BIT_MASK_HI7Q_DESC_MODE_8822B << BIT_SHIFT_HI7Q_DESC_MODE_8822B)\n#define BIT_CLEAR_HI7Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI7Q_DESC_MODE_8822B))\n#define BIT_GET_HI7Q_DESC_MODE_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8822B) &                             \\\n\t BIT_MASK_HI7Q_DESC_MODE_8822B)\n#define BIT_SET_HI7Q_DESC_MODE_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HI7Q_DESC_MODE_8822B(x) | BIT_HI7Q_DESC_MODE_8822B(v))\n\n#define BIT_SHIFT_HI7Q_DESC_NUM_8822B 0\n#define BIT_MASK_HI7Q_DESC_NUM_8822B 0xfff\n#define BIT_HI7Q_DESC_NUM_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HI7Q_DESC_NUM_8822B) << BIT_SHIFT_HI7Q_DESC_NUM_8822B)\n#define BITS_HI7Q_DESC_NUM_8822B                                               \\\n\t(BIT_MASK_HI7Q_DESC_NUM_8822B << BIT_SHIFT_HI7Q_DESC_NUM_8822B)\n#define BIT_CLEAR_HI7Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI7Q_DESC_NUM_8822B))\n#define BIT_GET_HI7Q_DESC_NUM_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8822B) & BIT_MASK_HI7Q_DESC_NUM_8822B)\n#define BIT_SET_HI7Q_DESC_NUM_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HI7Q_DESC_NUM_8822B(x) | BIT_HI7Q_DESC_NUM_8822B(v))\n\n/* 2 REG_TSFTIMER_HCI_8822B */\n\n#define BIT_SHIFT_TSFT2_HCI_8822B 16\n#define BIT_MASK_TSFT2_HCI_8822B 0xffff\n#define BIT_TSFT2_HCI_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_TSFT2_HCI_8822B) << BIT_SHIFT_TSFT2_HCI_8822B)\n#define BITS_TSFT2_HCI_8822B                                                   \\\n\t(BIT_MASK_TSFT2_HCI_8822B << BIT_SHIFT_TSFT2_HCI_8822B)\n#define BIT_CLEAR_TSFT2_HCI_8822B(x) ((x) & (~BITS_TSFT2_HCI_8822B))\n#define BIT_GET_TSFT2_HCI_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_TSFT2_HCI_8822B) & BIT_MASK_TSFT2_HCI_8822B)\n#define BIT_SET_TSFT2_HCI_8822B(x, v)                                          \\\n\t(BIT_CLEAR_TSFT2_HCI_8822B(x) | BIT_TSFT2_HCI_8822B(v))\n\n#define BIT_SHIFT_TSFT1_HCI_8822B 0\n#define BIT_MASK_TSFT1_HCI_8822B 0xffff\n#define BIT_TSFT1_HCI_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_TSFT1_HCI_8822B) << BIT_SHIFT_TSFT1_HCI_8822B)\n#define BITS_TSFT1_HCI_8822B                                                   \\\n\t(BIT_MASK_TSFT1_HCI_8822B << BIT_SHIFT_TSFT1_HCI_8822B)\n#define BIT_CLEAR_TSFT1_HCI_8822B(x) ((x) & (~BITS_TSFT1_HCI_8822B))\n#define BIT_GET_TSFT1_HCI_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_TSFT1_HCI_8822B) & BIT_MASK_TSFT1_HCI_8822B)\n#define BIT_SET_TSFT1_HCI_8822B(x, v)                                          \\\n\t(BIT_CLEAR_TSFT1_HCI_8822B(x) | BIT_TSFT1_HCI_8822B(v))\n\n/* 2 REG_BD_RWPTR_CLR_8822B */\n#define BIT_CLR_HI7Q_HW_IDX_8822B BIT(29)\n#define BIT_CLR_HI6Q_HW_IDX_8822B BIT(28)\n#define BIT_CLR_HI5Q_HW_IDX_8822B BIT(27)\n#define BIT_CLR_HI4Q_HW_IDX_8822B BIT(26)\n#define BIT_CLR_HI3Q_HW_IDX_8822B BIT(25)\n#define BIT_CLR_HI2Q_HW_IDX_8822B BIT(24)\n#define BIT_CLR_HI1Q_HW_IDX_8822B BIT(23)\n#define BIT_CLR_HI0Q_HW_IDX_8822B BIT(22)\n#define BIT_CLR_BKQ_HW_IDX_8822B BIT(21)\n#define BIT_CLR_BEQ_HW_IDX_8822B BIT(20)\n#define BIT_CLR_VIQ_HW_IDX_8822B BIT(19)\n#define BIT_CLR_VOQ_HW_IDX_8822B BIT(18)\n#define BIT_CLR_MGQ_HW_IDX_8822B BIT(17)\n#define BIT_CLR_RXQ_HW_IDX_8822B BIT(16)\n#define BIT_CLR_HI7Q_HOST_IDX_8822B BIT(13)\n#define BIT_CLR_HI6Q_HOST_IDX_8822B BIT(12)\n#define BIT_CLR_HI5Q_HOST_IDX_8822B BIT(11)\n#define BIT_CLR_HI4Q_HOST_IDX_8822B BIT(10)\n#define BIT_CLR_HI3Q_HOST_IDX_8822B BIT(9)\n#define BIT_CLR_HI2Q_HOST_IDX_8822B BIT(8)\n#define BIT_CLR_HI1Q_HOST_IDX_8822B BIT(7)\n#define BIT_CLR_HI0Q_HOST_IDX_8822B BIT(6)\n#define BIT_CLR_BKQ_HOST_IDX_8822B BIT(5)\n#define BIT_CLR_BEQ_HOST_IDX_8822B BIT(4)\n#define BIT_CLR_VIQ_HOST_IDX_8822B BIT(3)\n#define BIT_CLR_VOQ_HOST_IDX_8822B BIT(2)\n#define BIT_CLR_MGQ_HOST_IDX_8822B BIT(1)\n#define BIT_CLR_RXQ_HOST_IDX_8822B BIT(0)\n\n/* 2 REG_VOQ_TXBD_IDX_8822B */\n\n#define BIT_SHIFT_VOQ_HW_IDX_8822B 16\n#define BIT_MASK_VOQ_HW_IDX_8822B 0xfff\n#define BIT_VOQ_HW_IDX_8822B(x)                                                \\\n\t(((x) & BIT_MASK_VOQ_HW_IDX_8822B) << BIT_SHIFT_VOQ_HW_IDX_8822B)\n#define BITS_VOQ_HW_IDX_8822B                                                  \\\n\t(BIT_MASK_VOQ_HW_IDX_8822B << BIT_SHIFT_VOQ_HW_IDX_8822B)\n#define BIT_CLEAR_VOQ_HW_IDX_8822B(x) ((x) & (~BITS_VOQ_HW_IDX_8822B))\n#define BIT_GET_VOQ_HW_IDX_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_VOQ_HW_IDX_8822B) & BIT_MASK_VOQ_HW_IDX_8822B)\n#define BIT_SET_VOQ_HW_IDX_8822B(x, v)                                         \\\n\t(BIT_CLEAR_VOQ_HW_IDX_8822B(x) | BIT_VOQ_HW_IDX_8822B(v))\n\n#define BIT_SHIFT_VOQ_HOST_IDX_8822B 0\n#define BIT_MASK_VOQ_HOST_IDX_8822B 0xfff\n#define BIT_VOQ_HOST_IDX_8822B(x)                                              \\\n\t(((x) & BIT_MASK_VOQ_HOST_IDX_8822B) << BIT_SHIFT_VOQ_HOST_IDX_8822B)\n#define BITS_VOQ_HOST_IDX_8822B                                                \\\n\t(BIT_MASK_VOQ_HOST_IDX_8822B << BIT_SHIFT_VOQ_HOST_IDX_8822B)\n#define BIT_CLEAR_VOQ_HOST_IDX_8822B(x) ((x) & (~BITS_VOQ_HOST_IDX_8822B))\n#define BIT_GET_VOQ_HOST_IDX_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_VOQ_HOST_IDX_8822B) & BIT_MASK_VOQ_HOST_IDX_8822B)\n#define BIT_SET_VOQ_HOST_IDX_8822B(x, v)                                       \\\n\t(BIT_CLEAR_VOQ_HOST_IDX_8822B(x) | BIT_VOQ_HOST_IDX_8822B(v))\n\n/* 2 REG_VIQ_TXBD_IDX_8822B */\n\n#define BIT_SHIFT_VIQ_HW_IDX_8822B 16\n#define BIT_MASK_VIQ_HW_IDX_8822B 0xfff\n#define BIT_VIQ_HW_IDX_8822B(x)                                                \\\n\t(((x) & BIT_MASK_VIQ_HW_IDX_8822B) << BIT_SHIFT_VIQ_HW_IDX_8822B)\n#define BITS_VIQ_HW_IDX_8822B                                                  \\\n\t(BIT_MASK_VIQ_HW_IDX_8822B << BIT_SHIFT_VIQ_HW_IDX_8822B)\n#define BIT_CLEAR_VIQ_HW_IDX_8822B(x) ((x) & (~BITS_VIQ_HW_IDX_8822B))\n#define BIT_GET_VIQ_HW_IDX_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_VIQ_HW_IDX_8822B) & BIT_MASK_VIQ_HW_IDX_8822B)\n#define BIT_SET_VIQ_HW_IDX_8822B(x, v)                                         \\\n\t(BIT_CLEAR_VIQ_HW_IDX_8822B(x) | BIT_VIQ_HW_IDX_8822B(v))\n\n#define BIT_SHIFT_VIQ_HOST_IDX_8822B 0\n#define BIT_MASK_VIQ_HOST_IDX_8822B 0xfff\n#define BIT_VIQ_HOST_IDX_8822B(x)                                              \\\n\t(((x) & BIT_MASK_VIQ_HOST_IDX_8822B) << BIT_SHIFT_VIQ_HOST_IDX_8822B)\n#define BITS_VIQ_HOST_IDX_8822B                                                \\\n\t(BIT_MASK_VIQ_HOST_IDX_8822B << BIT_SHIFT_VIQ_HOST_IDX_8822B)\n#define BIT_CLEAR_VIQ_HOST_IDX_8822B(x) ((x) & (~BITS_VIQ_HOST_IDX_8822B))\n#define BIT_GET_VIQ_HOST_IDX_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_VIQ_HOST_IDX_8822B) & BIT_MASK_VIQ_HOST_IDX_8822B)\n#define BIT_SET_VIQ_HOST_IDX_8822B(x, v)                                       \\\n\t(BIT_CLEAR_VIQ_HOST_IDX_8822B(x) | BIT_VIQ_HOST_IDX_8822B(v))\n\n/* 2 REG_BEQ_TXBD_IDX_8822B */\n\n#define BIT_SHIFT_BEQ_HW_IDX_8822B 16\n#define BIT_MASK_BEQ_HW_IDX_8822B 0xfff\n#define BIT_BEQ_HW_IDX_8822B(x)                                                \\\n\t(((x) & BIT_MASK_BEQ_HW_IDX_8822B) << BIT_SHIFT_BEQ_HW_IDX_8822B)\n#define BITS_BEQ_HW_IDX_8822B                                                  \\\n\t(BIT_MASK_BEQ_HW_IDX_8822B << BIT_SHIFT_BEQ_HW_IDX_8822B)\n#define BIT_CLEAR_BEQ_HW_IDX_8822B(x) ((x) & (~BITS_BEQ_HW_IDX_8822B))\n#define BIT_GET_BEQ_HW_IDX_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_BEQ_HW_IDX_8822B) & BIT_MASK_BEQ_HW_IDX_8822B)\n#define BIT_SET_BEQ_HW_IDX_8822B(x, v)                                         \\\n\t(BIT_CLEAR_BEQ_HW_IDX_8822B(x) | BIT_BEQ_HW_IDX_8822B(v))\n\n#define BIT_SHIFT_BEQ_HOST_IDX_8822B 0\n#define BIT_MASK_BEQ_HOST_IDX_8822B 0xfff\n#define BIT_BEQ_HOST_IDX_8822B(x)                                              \\\n\t(((x) & BIT_MASK_BEQ_HOST_IDX_8822B) << BIT_SHIFT_BEQ_HOST_IDX_8822B)\n#define BITS_BEQ_HOST_IDX_8822B                                                \\\n\t(BIT_MASK_BEQ_HOST_IDX_8822B << BIT_SHIFT_BEQ_HOST_IDX_8822B)\n#define BIT_CLEAR_BEQ_HOST_IDX_8822B(x) ((x) & (~BITS_BEQ_HOST_IDX_8822B))\n#define BIT_GET_BEQ_HOST_IDX_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BEQ_HOST_IDX_8822B) & BIT_MASK_BEQ_HOST_IDX_8822B)\n#define BIT_SET_BEQ_HOST_IDX_8822B(x, v)                                       \\\n\t(BIT_CLEAR_BEQ_HOST_IDX_8822B(x) | BIT_BEQ_HOST_IDX_8822B(v))\n\n/* 2 REG_BKQ_TXBD_IDX_8822B */\n\n#define BIT_SHIFT_BKQ_HW_IDX_8822B 16\n#define BIT_MASK_BKQ_HW_IDX_8822B 0xfff\n#define BIT_BKQ_HW_IDX_8822B(x)                                                \\\n\t(((x) & BIT_MASK_BKQ_HW_IDX_8822B) << BIT_SHIFT_BKQ_HW_IDX_8822B)\n#define BITS_BKQ_HW_IDX_8822B                                                  \\\n\t(BIT_MASK_BKQ_HW_IDX_8822B << BIT_SHIFT_BKQ_HW_IDX_8822B)\n#define BIT_CLEAR_BKQ_HW_IDX_8822B(x) ((x) & (~BITS_BKQ_HW_IDX_8822B))\n#define BIT_GET_BKQ_HW_IDX_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_BKQ_HW_IDX_8822B) & BIT_MASK_BKQ_HW_IDX_8822B)\n#define BIT_SET_BKQ_HW_IDX_8822B(x, v)                                         \\\n\t(BIT_CLEAR_BKQ_HW_IDX_8822B(x) | BIT_BKQ_HW_IDX_8822B(v))\n\n#define BIT_SHIFT_BKQ_HOST_IDX_8822B 0\n#define BIT_MASK_BKQ_HOST_IDX_8822B 0xfff\n#define BIT_BKQ_HOST_IDX_8822B(x)                                              \\\n\t(((x) & BIT_MASK_BKQ_HOST_IDX_8822B) << BIT_SHIFT_BKQ_HOST_IDX_8822B)\n#define BITS_BKQ_HOST_IDX_8822B                                                \\\n\t(BIT_MASK_BKQ_HOST_IDX_8822B << BIT_SHIFT_BKQ_HOST_IDX_8822B)\n#define BIT_CLEAR_BKQ_HOST_IDX_8822B(x) ((x) & (~BITS_BKQ_HOST_IDX_8822B))\n#define BIT_GET_BKQ_HOST_IDX_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BKQ_HOST_IDX_8822B) & BIT_MASK_BKQ_HOST_IDX_8822B)\n#define BIT_SET_BKQ_HOST_IDX_8822B(x, v)                                       \\\n\t(BIT_CLEAR_BKQ_HOST_IDX_8822B(x) | BIT_BKQ_HOST_IDX_8822B(v))\n\n/* 2 REG_MGQ_TXBD_IDX_8822B */\n\n#define BIT_SHIFT_MGQ_HW_IDX_8822B 16\n#define BIT_MASK_MGQ_HW_IDX_8822B 0xfff\n#define BIT_MGQ_HW_IDX_8822B(x)                                                \\\n\t(((x) & BIT_MASK_MGQ_HW_IDX_8822B) << BIT_SHIFT_MGQ_HW_IDX_8822B)\n#define BITS_MGQ_HW_IDX_8822B                                                  \\\n\t(BIT_MASK_MGQ_HW_IDX_8822B << BIT_SHIFT_MGQ_HW_IDX_8822B)\n#define BIT_CLEAR_MGQ_HW_IDX_8822B(x) ((x) & (~BITS_MGQ_HW_IDX_8822B))\n#define BIT_GET_MGQ_HW_IDX_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_MGQ_HW_IDX_8822B) & BIT_MASK_MGQ_HW_IDX_8822B)\n#define BIT_SET_MGQ_HW_IDX_8822B(x, v)                                         \\\n\t(BIT_CLEAR_MGQ_HW_IDX_8822B(x) | BIT_MGQ_HW_IDX_8822B(v))\n\n#define BIT_SHIFT_MGQ_HOST_IDX_8822B 0\n#define BIT_MASK_MGQ_HOST_IDX_8822B 0xfff\n#define BIT_MGQ_HOST_IDX_8822B(x)                                              \\\n\t(((x) & BIT_MASK_MGQ_HOST_IDX_8822B) << BIT_SHIFT_MGQ_HOST_IDX_8822B)\n#define BITS_MGQ_HOST_IDX_8822B                                                \\\n\t(BIT_MASK_MGQ_HOST_IDX_8822B << BIT_SHIFT_MGQ_HOST_IDX_8822B)\n#define BIT_CLEAR_MGQ_HOST_IDX_8822B(x) ((x) & (~BITS_MGQ_HOST_IDX_8822B))\n#define BIT_GET_MGQ_HOST_IDX_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_MGQ_HOST_IDX_8822B) & BIT_MASK_MGQ_HOST_IDX_8822B)\n#define BIT_SET_MGQ_HOST_IDX_8822B(x, v)                                       \\\n\t(BIT_CLEAR_MGQ_HOST_IDX_8822B(x) | BIT_MGQ_HOST_IDX_8822B(v))\n\n/* 2 REG_RXQ_RXBD_IDX_8822B */\n\n#define BIT_SHIFT_RXQ_HW_IDX_8822B 16\n#define BIT_MASK_RXQ_HW_IDX_8822B 0xfff\n#define BIT_RXQ_HW_IDX_8822B(x)                                                \\\n\t(((x) & BIT_MASK_RXQ_HW_IDX_8822B) << BIT_SHIFT_RXQ_HW_IDX_8822B)\n#define BITS_RXQ_HW_IDX_8822B                                                  \\\n\t(BIT_MASK_RXQ_HW_IDX_8822B << BIT_SHIFT_RXQ_HW_IDX_8822B)\n#define BIT_CLEAR_RXQ_HW_IDX_8822B(x) ((x) & (~BITS_RXQ_HW_IDX_8822B))\n#define BIT_GET_RXQ_HW_IDX_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXQ_HW_IDX_8822B) & BIT_MASK_RXQ_HW_IDX_8822B)\n#define BIT_SET_RXQ_HW_IDX_8822B(x, v)                                         \\\n\t(BIT_CLEAR_RXQ_HW_IDX_8822B(x) | BIT_RXQ_HW_IDX_8822B(v))\n\n#define BIT_SHIFT_RXQ_HOST_IDX_8822B 0\n#define BIT_MASK_RXQ_HOST_IDX_8822B 0xfff\n#define BIT_RXQ_HOST_IDX_8822B(x)                                              \\\n\t(((x) & BIT_MASK_RXQ_HOST_IDX_8822B) << BIT_SHIFT_RXQ_HOST_IDX_8822B)\n#define BITS_RXQ_HOST_IDX_8822B                                                \\\n\t(BIT_MASK_RXQ_HOST_IDX_8822B << BIT_SHIFT_RXQ_HOST_IDX_8822B)\n#define BIT_CLEAR_RXQ_HOST_IDX_8822B(x) ((x) & (~BITS_RXQ_HOST_IDX_8822B))\n#define BIT_GET_RXQ_HOST_IDX_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXQ_HOST_IDX_8822B) & BIT_MASK_RXQ_HOST_IDX_8822B)\n#define BIT_SET_RXQ_HOST_IDX_8822B(x, v)                                       \\\n\t(BIT_CLEAR_RXQ_HOST_IDX_8822B(x) | BIT_RXQ_HOST_IDX_8822B(v))\n\n/* 2 REG_HI0Q_TXBD_IDX_8822B */\n\n#define BIT_SHIFT_HI0Q_HW_IDX_8822B 16\n#define BIT_MASK_HI0Q_HW_IDX_8822B 0xfff\n#define BIT_HI0Q_HW_IDX_8822B(x)                                               \\\n\t(((x) & BIT_MASK_HI0Q_HW_IDX_8822B) << BIT_SHIFT_HI0Q_HW_IDX_8822B)\n#define BITS_HI0Q_HW_IDX_8822B                                                 \\\n\t(BIT_MASK_HI0Q_HW_IDX_8822B << BIT_SHIFT_HI0Q_HW_IDX_8822B)\n#define BIT_CLEAR_HI0Q_HW_IDX_8822B(x) ((x) & (~BITS_HI0Q_HW_IDX_8822B))\n#define BIT_GET_HI0Q_HW_IDX_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI0Q_HW_IDX_8822B) & BIT_MASK_HI0Q_HW_IDX_8822B)\n#define BIT_SET_HI0Q_HW_IDX_8822B(x, v)                                        \\\n\t(BIT_CLEAR_HI0Q_HW_IDX_8822B(x) | BIT_HI0Q_HW_IDX_8822B(v))\n\n#define BIT_SHIFT_HI0Q_HOST_IDX_8822B 0\n#define BIT_MASK_HI0Q_HOST_IDX_8822B 0xfff\n#define BIT_HI0Q_HOST_IDX_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HI0Q_HOST_IDX_8822B) << BIT_SHIFT_HI0Q_HOST_IDX_8822B)\n#define BITS_HI0Q_HOST_IDX_8822B                                               \\\n\t(BIT_MASK_HI0Q_HOST_IDX_8822B << BIT_SHIFT_HI0Q_HOST_IDX_8822B)\n#define BIT_CLEAR_HI0Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI0Q_HOST_IDX_8822B))\n#define BIT_GET_HI0Q_HOST_IDX_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8822B) & BIT_MASK_HI0Q_HOST_IDX_8822B)\n#define BIT_SET_HI0Q_HOST_IDX_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HI0Q_HOST_IDX_8822B(x) | BIT_HI0Q_HOST_IDX_8822B(v))\n\n/* 2 REG_HI1Q_TXBD_IDX_8822B */\n\n#define BIT_SHIFT_HI1Q_HW_IDX_8822B 16\n#define BIT_MASK_HI1Q_HW_IDX_8822B 0xfff\n#define BIT_HI1Q_HW_IDX_8822B(x)                                               \\\n\t(((x) & BIT_MASK_HI1Q_HW_IDX_8822B) << BIT_SHIFT_HI1Q_HW_IDX_8822B)\n#define BITS_HI1Q_HW_IDX_8822B                                                 \\\n\t(BIT_MASK_HI1Q_HW_IDX_8822B << BIT_SHIFT_HI1Q_HW_IDX_8822B)\n#define BIT_CLEAR_HI1Q_HW_IDX_8822B(x) ((x) & (~BITS_HI1Q_HW_IDX_8822B))\n#define BIT_GET_HI1Q_HW_IDX_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI1Q_HW_IDX_8822B) & BIT_MASK_HI1Q_HW_IDX_8822B)\n#define BIT_SET_HI1Q_HW_IDX_8822B(x, v)                                        \\\n\t(BIT_CLEAR_HI1Q_HW_IDX_8822B(x) | BIT_HI1Q_HW_IDX_8822B(v))\n\n#define BIT_SHIFT_HI1Q_HOST_IDX_8822B 0\n#define BIT_MASK_HI1Q_HOST_IDX_8822B 0xfff\n#define BIT_HI1Q_HOST_IDX_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HI1Q_HOST_IDX_8822B) << BIT_SHIFT_HI1Q_HOST_IDX_8822B)\n#define BITS_HI1Q_HOST_IDX_8822B                                               \\\n\t(BIT_MASK_HI1Q_HOST_IDX_8822B << BIT_SHIFT_HI1Q_HOST_IDX_8822B)\n#define BIT_CLEAR_HI1Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI1Q_HOST_IDX_8822B))\n#define BIT_GET_HI1Q_HOST_IDX_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8822B) & BIT_MASK_HI1Q_HOST_IDX_8822B)\n#define BIT_SET_HI1Q_HOST_IDX_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HI1Q_HOST_IDX_8822B(x) | BIT_HI1Q_HOST_IDX_8822B(v))\n\n/* 2 REG_HI2Q_TXBD_IDX_8822B */\n\n#define BIT_SHIFT_HI2Q_HW_IDX_8822B 16\n#define BIT_MASK_HI2Q_HW_IDX_8822B 0xfff\n#define BIT_HI2Q_HW_IDX_8822B(x)                                               \\\n\t(((x) & BIT_MASK_HI2Q_HW_IDX_8822B) << BIT_SHIFT_HI2Q_HW_IDX_8822B)\n#define BITS_HI2Q_HW_IDX_8822B                                                 \\\n\t(BIT_MASK_HI2Q_HW_IDX_8822B << BIT_SHIFT_HI2Q_HW_IDX_8822B)\n#define BIT_CLEAR_HI2Q_HW_IDX_8822B(x) ((x) & (~BITS_HI2Q_HW_IDX_8822B))\n#define BIT_GET_HI2Q_HW_IDX_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI2Q_HW_IDX_8822B) & BIT_MASK_HI2Q_HW_IDX_8822B)\n#define BIT_SET_HI2Q_HW_IDX_8822B(x, v)                                        \\\n\t(BIT_CLEAR_HI2Q_HW_IDX_8822B(x) | BIT_HI2Q_HW_IDX_8822B(v))\n\n#define BIT_SHIFT_HI2Q_HOST_IDX_8822B 0\n#define BIT_MASK_HI2Q_HOST_IDX_8822B 0xfff\n#define BIT_HI2Q_HOST_IDX_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HI2Q_HOST_IDX_8822B) << BIT_SHIFT_HI2Q_HOST_IDX_8822B)\n#define BITS_HI2Q_HOST_IDX_8822B                                               \\\n\t(BIT_MASK_HI2Q_HOST_IDX_8822B << BIT_SHIFT_HI2Q_HOST_IDX_8822B)\n#define BIT_CLEAR_HI2Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI2Q_HOST_IDX_8822B))\n#define BIT_GET_HI2Q_HOST_IDX_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8822B) & BIT_MASK_HI2Q_HOST_IDX_8822B)\n#define BIT_SET_HI2Q_HOST_IDX_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HI2Q_HOST_IDX_8822B(x) | BIT_HI2Q_HOST_IDX_8822B(v))\n\n/* 2 REG_HI3Q_TXBD_IDX_8822B */\n\n#define BIT_SHIFT_HI3Q_HW_IDX_8822B 16\n#define BIT_MASK_HI3Q_HW_IDX_8822B 0xfff\n#define BIT_HI3Q_HW_IDX_8822B(x)                                               \\\n\t(((x) & BIT_MASK_HI3Q_HW_IDX_8822B) << BIT_SHIFT_HI3Q_HW_IDX_8822B)\n#define BITS_HI3Q_HW_IDX_8822B                                                 \\\n\t(BIT_MASK_HI3Q_HW_IDX_8822B << BIT_SHIFT_HI3Q_HW_IDX_8822B)\n#define BIT_CLEAR_HI3Q_HW_IDX_8822B(x) ((x) & (~BITS_HI3Q_HW_IDX_8822B))\n#define BIT_GET_HI3Q_HW_IDX_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI3Q_HW_IDX_8822B) & BIT_MASK_HI3Q_HW_IDX_8822B)\n#define BIT_SET_HI3Q_HW_IDX_8822B(x, v)                                        \\\n\t(BIT_CLEAR_HI3Q_HW_IDX_8822B(x) | BIT_HI3Q_HW_IDX_8822B(v))\n\n#define BIT_SHIFT_HI3Q_HOST_IDX_8822B 0\n#define BIT_MASK_HI3Q_HOST_IDX_8822B 0xfff\n#define BIT_HI3Q_HOST_IDX_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HI3Q_HOST_IDX_8822B) << BIT_SHIFT_HI3Q_HOST_IDX_8822B)\n#define BITS_HI3Q_HOST_IDX_8822B                                               \\\n\t(BIT_MASK_HI3Q_HOST_IDX_8822B << BIT_SHIFT_HI3Q_HOST_IDX_8822B)\n#define BIT_CLEAR_HI3Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI3Q_HOST_IDX_8822B))\n#define BIT_GET_HI3Q_HOST_IDX_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8822B) & BIT_MASK_HI3Q_HOST_IDX_8822B)\n#define BIT_SET_HI3Q_HOST_IDX_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HI3Q_HOST_IDX_8822B(x) | BIT_HI3Q_HOST_IDX_8822B(v))\n\n/* 2 REG_HI4Q_TXBD_IDX_8822B */\n\n#define BIT_SHIFT_HI4Q_HW_IDX_8822B 16\n#define BIT_MASK_HI4Q_HW_IDX_8822B 0xfff\n#define BIT_HI4Q_HW_IDX_8822B(x)                                               \\\n\t(((x) & BIT_MASK_HI4Q_HW_IDX_8822B) << BIT_SHIFT_HI4Q_HW_IDX_8822B)\n#define BITS_HI4Q_HW_IDX_8822B                                                 \\\n\t(BIT_MASK_HI4Q_HW_IDX_8822B << BIT_SHIFT_HI4Q_HW_IDX_8822B)\n#define BIT_CLEAR_HI4Q_HW_IDX_8822B(x) ((x) & (~BITS_HI4Q_HW_IDX_8822B))\n#define BIT_GET_HI4Q_HW_IDX_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI4Q_HW_IDX_8822B) & BIT_MASK_HI4Q_HW_IDX_8822B)\n#define BIT_SET_HI4Q_HW_IDX_8822B(x, v)                                        \\\n\t(BIT_CLEAR_HI4Q_HW_IDX_8822B(x) | BIT_HI4Q_HW_IDX_8822B(v))\n\n#define BIT_SHIFT_HI4Q_HOST_IDX_8822B 0\n#define BIT_MASK_HI4Q_HOST_IDX_8822B 0xfff\n#define BIT_HI4Q_HOST_IDX_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HI4Q_HOST_IDX_8822B) << BIT_SHIFT_HI4Q_HOST_IDX_8822B)\n#define BITS_HI4Q_HOST_IDX_8822B                                               \\\n\t(BIT_MASK_HI4Q_HOST_IDX_8822B << BIT_SHIFT_HI4Q_HOST_IDX_8822B)\n#define BIT_CLEAR_HI4Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI4Q_HOST_IDX_8822B))\n#define BIT_GET_HI4Q_HOST_IDX_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8822B) & BIT_MASK_HI4Q_HOST_IDX_8822B)\n#define BIT_SET_HI4Q_HOST_IDX_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HI4Q_HOST_IDX_8822B(x) | BIT_HI4Q_HOST_IDX_8822B(v))\n\n/* 2 REG_HI5Q_TXBD_IDX_8822B */\n\n#define BIT_SHIFT_HI5Q_HW_IDX_8822B 16\n#define BIT_MASK_HI5Q_HW_IDX_8822B 0xfff\n#define BIT_HI5Q_HW_IDX_8822B(x)                                               \\\n\t(((x) & BIT_MASK_HI5Q_HW_IDX_8822B) << BIT_SHIFT_HI5Q_HW_IDX_8822B)\n#define BITS_HI5Q_HW_IDX_8822B                                                 \\\n\t(BIT_MASK_HI5Q_HW_IDX_8822B << BIT_SHIFT_HI5Q_HW_IDX_8822B)\n#define BIT_CLEAR_HI5Q_HW_IDX_8822B(x) ((x) & (~BITS_HI5Q_HW_IDX_8822B))\n#define BIT_GET_HI5Q_HW_IDX_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI5Q_HW_IDX_8822B) & BIT_MASK_HI5Q_HW_IDX_8822B)\n#define BIT_SET_HI5Q_HW_IDX_8822B(x, v)                                        \\\n\t(BIT_CLEAR_HI5Q_HW_IDX_8822B(x) | BIT_HI5Q_HW_IDX_8822B(v))\n\n#define BIT_SHIFT_HI5Q_HOST_IDX_8822B 0\n#define BIT_MASK_HI5Q_HOST_IDX_8822B 0xfff\n#define BIT_HI5Q_HOST_IDX_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HI5Q_HOST_IDX_8822B) << BIT_SHIFT_HI5Q_HOST_IDX_8822B)\n#define BITS_HI5Q_HOST_IDX_8822B                                               \\\n\t(BIT_MASK_HI5Q_HOST_IDX_8822B << BIT_SHIFT_HI5Q_HOST_IDX_8822B)\n#define BIT_CLEAR_HI5Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI5Q_HOST_IDX_8822B))\n#define BIT_GET_HI5Q_HOST_IDX_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8822B) & BIT_MASK_HI5Q_HOST_IDX_8822B)\n#define BIT_SET_HI5Q_HOST_IDX_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HI5Q_HOST_IDX_8822B(x) | BIT_HI5Q_HOST_IDX_8822B(v))\n\n/* 2 REG_HI6Q_TXBD_IDX_8822B */\n\n#define BIT_SHIFT_HI6Q_HW_IDX_8822B 16\n#define BIT_MASK_HI6Q_HW_IDX_8822B 0xfff\n#define BIT_HI6Q_HW_IDX_8822B(x)                                               \\\n\t(((x) & BIT_MASK_HI6Q_HW_IDX_8822B) << BIT_SHIFT_HI6Q_HW_IDX_8822B)\n#define BITS_HI6Q_HW_IDX_8822B                                                 \\\n\t(BIT_MASK_HI6Q_HW_IDX_8822B << BIT_SHIFT_HI6Q_HW_IDX_8822B)\n#define BIT_CLEAR_HI6Q_HW_IDX_8822B(x) ((x) & (~BITS_HI6Q_HW_IDX_8822B))\n#define BIT_GET_HI6Q_HW_IDX_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI6Q_HW_IDX_8822B) & BIT_MASK_HI6Q_HW_IDX_8822B)\n#define BIT_SET_HI6Q_HW_IDX_8822B(x, v)                                        \\\n\t(BIT_CLEAR_HI6Q_HW_IDX_8822B(x) | BIT_HI6Q_HW_IDX_8822B(v))\n\n#define BIT_SHIFT_HI6Q_HOST_IDX_8822B 0\n#define BIT_MASK_HI6Q_HOST_IDX_8822B 0xfff\n#define BIT_HI6Q_HOST_IDX_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HI6Q_HOST_IDX_8822B) << BIT_SHIFT_HI6Q_HOST_IDX_8822B)\n#define BITS_HI6Q_HOST_IDX_8822B                                               \\\n\t(BIT_MASK_HI6Q_HOST_IDX_8822B << BIT_SHIFT_HI6Q_HOST_IDX_8822B)\n#define BIT_CLEAR_HI6Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI6Q_HOST_IDX_8822B))\n#define BIT_GET_HI6Q_HOST_IDX_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8822B) & BIT_MASK_HI6Q_HOST_IDX_8822B)\n#define BIT_SET_HI6Q_HOST_IDX_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HI6Q_HOST_IDX_8822B(x) | BIT_HI6Q_HOST_IDX_8822B(v))\n\n/* 2 REG_HI7Q_TXBD_IDX_8822B */\n\n#define BIT_SHIFT_HI7Q_HW_IDX_8822B 16\n#define BIT_MASK_HI7Q_HW_IDX_8822B 0xfff\n#define BIT_HI7Q_HW_IDX_8822B(x)                                               \\\n\t(((x) & BIT_MASK_HI7Q_HW_IDX_8822B) << BIT_SHIFT_HI7Q_HW_IDX_8822B)\n#define BITS_HI7Q_HW_IDX_8822B                                                 \\\n\t(BIT_MASK_HI7Q_HW_IDX_8822B << BIT_SHIFT_HI7Q_HW_IDX_8822B)\n#define BIT_CLEAR_HI7Q_HW_IDX_8822B(x) ((x) & (~BITS_HI7Q_HW_IDX_8822B))\n#define BIT_GET_HI7Q_HW_IDX_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI7Q_HW_IDX_8822B) & BIT_MASK_HI7Q_HW_IDX_8822B)\n#define BIT_SET_HI7Q_HW_IDX_8822B(x, v)                                        \\\n\t(BIT_CLEAR_HI7Q_HW_IDX_8822B(x) | BIT_HI7Q_HW_IDX_8822B(v))\n\n#define BIT_SHIFT_HI7Q_HOST_IDX_8822B 0\n#define BIT_MASK_HI7Q_HOST_IDX_8822B 0xfff\n#define BIT_HI7Q_HOST_IDX_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HI7Q_HOST_IDX_8822B) << BIT_SHIFT_HI7Q_HOST_IDX_8822B)\n#define BITS_HI7Q_HOST_IDX_8822B                                               \\\n\t(BIT_MASK_HI7Q_HOST_IDX_8822B << BIT_SHIFT_HI7Q_HOST_IDX_8822B)\n#define BIT_CLEAR_HI7Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI7Q_HOST_IDX_8822B))\n#define BIT_GET_HI7Q_HOST_IDX_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8822B) & BIT_MASK_HI7Q_HOST_IDX_8822B)\n#define BIT_SET_HI7Q_HOST_IDX_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HI7Q_HOST_IDX_8822B(x) | BIT_HI7Q_HOST_IDX_8822B(v))\n\n/* 2 REG_DBG_SEL_V1_8822B */\n\n#define BIT_SHIFT_DBG_SEL_8822B 0\n#define BIT_MASK_DBG_SEL_8822B 0xff\n#define BIT_DBG_SEL_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_DBG_SEL_8822B) << BIT_SHIFT_DBG_SEL_8822B)\n#define BITS_DBG_SEL_8822B (BIT_MASK_DBG_SEL_8822B << BIT_SHIFT_DBG_SEL_8822B)\n#define BIT_CLEAR_DBG_SEL_8822B(x) ((x) & (~BITS_DBG_SEL_8822B))\n#define BIT_GET_DBG_SEL_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_DBG_SEL_8822B) & BIT_MASK_DBG_SEL_8822B)\n#define BIT_SET_DBG_SEL_8822B(x, v)                                            \\\n\t(BIT_CLEAR_DBG_SEL_8822B(x) | BIT_DBG_SEL_8822B(v))\n\n/* 2 REG_PCIE_HRPWM1_V1_8822B */\n\n#define BIT_SHIFT_PCIE_HRPWM_8822B 0\n#define BIT_MASK_PCIE_HRPWM_8822B 0xff\n#define BIT_PCIE_HRPWM_8822B(x)                                                \\\n\t(((x) & BIT_MASK_PCIE_HRPWM_8822B) << BIT_SHIFT_PCIE_HRPWM_8822B)\n#define BITS_PCIE_HRPWM_8822B                                                  \\\n\t(BIT_MASK_PCIE_HRPWM_8822B << BIT_SHIFT_PCIE_HRPWM_8822B)\n#define BIT_CLEAR_PCIE_HRPWM_8822B(x) ((x) & (~BITS_PCIE_HRPWM_8822B))\n#define BIT_GET_PCIE_HRPWM_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_PCIE_HRPWM_8822B) & BIT_MASK_PCIE_HRPWM_8822B)\n#define BIT_SET_PCIE_HRPWM_8822B(x, v)                                         \\\n\t(BIT_CLEAR_PCIE_HRPWM_8822B(x) | BIT_PCIE_HRPWM_8822B(v))\n\n/* 2 REG_PCIE_HCPWM1_V1_8822B */\n\n#define BIT_SHIFT_PCIE_HCPWM_8822B 0\n#define BIT_MASK_PCIE_HCPWM_8822B 0xff\n#define BIT_PCIE_HCPWM_8822B(x)                                                \\\n\t(((x) & BIT_MASK_PCIE_HCPWM_8822B) << BIT_SHIFT_PCIE_HCPWM_8822B)\n#define BITS_PCIE_HCPWM_8822B                                                  \\\n\t(BIT_MASK_PCIE_HCPWM_8822B << BIT_SHIFT_PCIE_HCPWM_8822B)\n#define BIT_CLEAR_PCIE_HCPWM_8822B(x) ((x) & (~BITS_PCIE_HCPWM_8822B))\n#define BIT_GET_PCIE_HCPWM_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_PCIE_HCPWM_8822B) & BIT_MASK_PCIE_HCPWM_8822B)\n#define BIT_SET_PCIE_HCPWM_8822B(x, v)                                         \\\n\t(BIT_CLEAR_PCIE_HCPWM_8822B(x) | BIT_PCIE_HCPWM_8822B(v))\n\n/* 2 REG_PCIE_CTRL2_8822B */\n#define BIT_DIS_TXDMA_PRE_8822B BIT(7)\n#define BIT_DIS_RXDMA_PRE_8822B BIT(6)\n\n#define BIT_SHIFT_HPS_CLKR_PCIE_8822B 4\n#define BIT_MASK_HPS_CLKR_PCIE_8822B 0x3\n#define BIT_HPS_CLKR_PCIE_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HPS_CLKR_PCIE_8822B) << BIT_SHIFT_HPS_CLKR_PCIE_8822B)\n#define BITS_HPS_CLKR_PCIE_8822B                                               \\\n\t(BIT_MASK_HPS_CLKR_PCIE_8822B << BIT_SHIFT_HPS_CLKR_PCIE_8822B)\n#define BIT_CLEAR_HPS_CLKR_PCIE_8822B(x) ((x) & (~BITS_HPS_CLKR_PCIE_8822B))\n#define BIT_GET_HPS_CLKR_PCIE_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8822B) & BIT_MASK_HPS_CLKR_PCIE_8822B)\n#define BIT_SET_HPS_CLKR_PCIE_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HPS_CLKR_PCIE_8822B(x) | BIT_HPS_CLKR_PCIE_8822B(v))\n\n#define BIT_PCIE_INT_8822B BIT(3)\n#define BIT_TXFLAG_EXIT_L1_EN_8822B BIT(2)\n#define BIT_EN_RXDMA_ALIGN_8822B BIT(1)\n#define BIT_EN_TXDMA_ALIGN_8822B BIT(0)\n\n/* 2 REG_PCIE_HRPWM2_V1_8822B */\n\n#define BIT_SHIFT_PCIE_HRPWM2_8822B 0\n#define BIT_MASK_PCIE_HRPWM2_8822B 0xffff\n#define BIT_PCIE_HRPWM2_8822B(x)                                               \\\n\t(((x) & BIT_MASK_PCIE_HRPWM2_8822B) << BIT_SHIFT_PCIE_HRPWM2_8822B)\n#define BITS_PCIE_HRPWM2_8822B                                                 \\\n\t(BIT_MASK_PCIE_HRPWM2_8822B << BIT_SHIFT_PCIE_HRPWM2_8822B)\n#define BIT_CLEAR_PCIE_HRPWM2_8822B(x) ((x) & (~BITS_PCIE_HRPWM2_8822B))\n#define BIT_GET_PCIE_HRPWM2_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_PCIE_HRPWM2_8822B) & BIT_MASK_PCIE_HRPWM2_8822B)\n#define BIT_SET_PCIE_HRPWM2_8822B(x, v)                                        \\\n\t(BIT_CLEAR_PCIE_HRPWM2_8822B(x) | BIT_PCIE_HRPWM2_8822B(v))\n\n/* 2 REG_PCIE_HCPWM2_V1_8822B */\n\n#define BIT_SHIFT_PCIE_HCPWM2_8822B 0\n#define BIT_MASK_PCIE_HCPWM2_8822B 0xffff\n#define BIT_PCIE_HCPWM2_8822B(x)                                               \\\n\t(((x) & BIT_MASK_PCIE_HCPWM2_8822B) << BIT_SHIFT_PCIE_HCPWM2_8822B)\n#define BITS_PCIE_HCPWM2_8822B                                                 \\\n\t(BIT_MASK_PCIE_HCPWM2_8822B << BIT_SHIFT_PCIE_HCPWM2_8822B)\n#define BIT_CLEAR_PCIE_HCPWM2_8822B(x) ((x) & (~BITS_PCIE_HCPWM2_8822B))\n#define BIT_GET_PCIE_HCPWM2_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_PCIE_HCPWM2_8822B) & BIT_MASK_PCIE_HCPWM2_8822B)\n#define BIT_SET_PCIE_HCPWM2_8822B(x, v)                                        \\\n\t(BIT_CLEAR_PCIE_HCPWM2_8822B(x) | BIT_PCIE_HCPWM2_8822B(v))\n\n/* 2 REG_PCIE_H2C_MSG_V1_8822B */\n\n#define BIT_SHIFT_DRV2FW_INFO_8822B 0\n#define BIT_MASK_DRV2FW_INFO_8822B 0xffffffffL\n#define BIT_DRV2FW_INFO_8822B(x)                                               \\\n\t(((x) & BIT_MASK_DRV2FW_INFO_8822B) << BIT_SHIFT_DRV2FW_INFO_8822B)\n#define BITS_DRV2FW_INFO_8822B                                                 \\\n\t(BIT_MASK_DRV2FW_INFO_8822B << BIT_SHIFT_DRV2FW_INFO_8822B)\n#define BIT_CLEAR_DRV2FW_INFO_8822B(x) ((x) & (~BITS_DRV2FW_INFO_8822B))\n#define BIT_GET_DRV2FW_INFO_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_DRV2FW_INFO_8822B) & BIT_MASK_DRV2FW_INFO_8822B)\n#define BIT_SET_DRV2FW_INFO_8822B(x, v)                                        \\\n\t(BIT_CLEAR_DRV2FW_INFO_8822B(x) | BIT_DRV2FW_INFO_8822B(v))\n\n/* 2 REG_PCIE_C2H_MSG_V1_8822B */\n\n#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B 0\n#define BIT_MASK_HCI_PCIE_C2H_MSG_8822B 0xffffffffL\n#define BIT_HCI_PCIE_C2H_MSG_8822B(x)                                          \\\n\t(((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8822B)                               \\\n\t << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B)\n#define BITS_HCI_PCIE_C2H_MSG_8822B                                            \\\n\t(BIT_MASK_HCI_PCIE_C2H_MSG_8822B << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B)\n#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8822B(x)                                    \\\n\t((x) & (~BITS_HCI_PCIE_C2H_MSG_8822B))\n#define BIT_GET_HCI_PCIE_C2H_MSG_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B) &                           \\\n\t BIT_MASK_HCI_PCIE_C2H_MSG_8822B)\n#define BIT_SET_HCI_PCIE_C2H_MSG_8822B(x, v)                                   \\\n\t(BIT_CLEAR_HCI_PCIE_C2H_MSG_8822B(x) | BIT_HCI_PCIE_C2H_MSG_8822B(v))\n\n/* 2 REG_DBI_WDATA_V1_8822B */\n\n#define BIT_SHIFT_DBI_WDATA_8822B 0\n#define BIT_MASK_DBI_WDATA_8822B 0xffffffffL\n#define BIT_DBI_WDATA_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_DBI_WDATA_8822B) << BIT_SHIFT_DBI_WDATA_8822B)\n#define BITS_DBI_WDATA_8822B                                                   \\\n\t(BIT_MASK_DBI_WDATA_8822B << BIT_SHIFT_DBI_WDATA_8822B)\n#define BIT_CLEAR_DBI_WDATA_8822B(x) ((x) & (~BITS_DBI_WDATA_8822B))\n#define BIT_GET_DBI_WDATA_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBI_WDATA_8822B) & BIT_MASK_DBI_WDATA_8822B)\n#define BIT_SET_DBI_WDATA_8822B(x, v)                                          \\\n\t(BIT_CLEAR_DBI_WDATA_8822B(x) | BIT_DBI_WDATA_8822B(v))\n\n/* 2 REG_DBI_RDATA_V1_8822B */\n\n#define BIT_SHIFT_DBI_RDATA_8822B 0\n#define BIT_MASK_DBI_RDATA_8822B 0xffffffffL\n#define BIT_DBI_RDATA_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_DBI_RDATA_8822B) << BIT_SHIFT_DBI_RDATA_8822B)\n#define BITS_DBI_RDATA_8822B                                                   \\\n\t(BIT_MASK_DBI_RDATA_8822B << BIT_SHIFT_DBI_RDATA_8822B)\n#define BIT_CLEAR_DBI_RDATA_8822B(x) ((x) & (~BITS_DBI_RDATA_8822B))\n#define BIT_GET_DBI_RDATA_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBI_RDATA_8822B) & BIT_MASK_DBI_RDATA_8822B)\n#define BIT_SET_DBI_RDATA_8822B(x, v)                                          \\\n\t(BIT_CLEAR_DBI_RDATA_8822B(x) | BIT_DBI_RDATA_8822B(v))\n\n/* 2 REG_DBI_FLAG_V1_8822B */\n#define BIT_EN_STUCK_DBG_8822B BIT(26)\n#define BIT_RX_STUCK_8822B BIT(25)\n#define BIT_TX_STUCK_8822B BIT(24)\n#define BIT_DBI_RFLAG_8822B BIT(17)\n#define BIT_DBI_WFLAG_8822B BIT(16)\n\n#define BIT_SHIFT_DBI_WREN_8822B 12\n#define BIT_MASK_DBI_WREN_8822B 0xf\n#define BIT_DBI_WREN_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_DBI_WREN_8822B) << BIT_SHIFT_DBI_WREN_8822B)\n#define BITS_DBI_WREN_8822B                                                    \\\n\t(BIT_MASK_DBI_WREN_8822B << BIT_SHIFT_DBI_WREN_8822B)\n#define BIT_CLEAR_DBI_WREN_8822B(x) ((x) & (~BITS_DBI_WREN_8822B))\n#define BIT_GET_DBI_WREN_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_DBI_WREN_8822B) & BIT_MASK_DBI_WREN_8822B)\n#define BIT_SET_DBI_WREN_8822B(x, v)                                           \\\n\t(BIT_CLEAR_DBI_WREN_8822B(x) | BIT_DBI_WREN_8822B(v))\n\n#define BIT_SHIFT_DBI_ADDR_8822B 0\n#define BIT_MASK_DBI_ADDR_8822B 0xfff\n#define BIT_DBI_ADDR_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_DBI_ADDR_8822B) << BIT_SHIFT_DBI_ADDR_8822B)\n#define BITS_DBI_ADDR_8822B                                                    \\\n\t(BIT_MASK_DBI_ADDR_8822B << BIT_SHIFT_DBI_ADDR_8822B)\n#define BIT_CLEAR_DBI_ADDR_8822B(x) ((x) & (~BITS_DBI_ADDR_8822B))\n#define BIT_GET_DBI_ADDR_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_DBI_ADDR_8822B) & BIT_MASK_DBI_ADDR_8822B)\n#define BIT_SET_DBI_ADDR_8822B(x, v)                                           \\\n\t(BIT_CLEAR_DBI_ADDR_8822B(x) | BIT_DBI_ADDR_8822B(v))\n\n/* 2 REG_MDIO_V1_8822B */\n\n#define BIT_SHIFT_MDIO_RDATA_8822B 16\n#define BIT_MASK_MDIO_RDATA_8822B 0xffff\n#define BIT_MDIO_RDATA_8822B(x)                                                \\\n\t(((x) & BIT_MASK_MDIO_RDATA_8822B) << BIT_SHIFT_MDIO_RDATA_8822B)\n#define BITS_MDIO_RDATA_8822B                                                  \\\n\t(BIT_MASK_MDIO_RDATA_8822B << BIT_SHIFT_MDIO_RDATA_8822B)\n#define BIT_CLEAR_MDIO_RDATA_8822B(x) ((x) & (~BITS_MDIO_RDATA_8822B))\n#define BIT_GET_MDIO_RDATA_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_MDIO_RDATA_8822B) & BIT_MASK_MDIO_RDATA_8822B)\n#define BIT_SET_MDIO_RDATA_8822B(x, v)                                         \\\n\t(BIT_CLEAR_MDIO_RDATA_8822B(x) | BIT_MDIO_RDATA_8822B(v))\n\n#define BIT_SHIFT_MDIO_WDATA_8822B 0\n#define BIT_MASK_MDIO_WDATA_8822B 0xffff\n#define BIT_MDIO_WDATA_8822B(x)                                                \\\n\t(((x) & BIT_MASK_MDIO_WDATA_8822B) << BIT_SHIFT_MDIO_WDATA_8822B)\n#define BITS_MDIO_WDATA_8822B                                                  \\\n\t(BIT_MASK_MDIO_WDATA_8822B << BIT_SHIFT_MDIO_WDATA_8822B)\n#define BIT_CLEAR_MDIO_WDATA_8822B(x) ((x) & (~BITS_MDIO_WDATA_8822B))\n#define BIT_GET_MDIO_WDATA_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_MDIO_WDATA_8822B) & BIT_MASK_MDIO_WDATA_8822B)\n#define BIT_SET_MDIO_WDATA_8822B(x, v)                                         \\\n\t(BIT_CLEAR_MDIO_WDATA_8822B(x) | BIT_MDIO_WDATA_8822B(v))\n\n/* 2 REG_PCIE_MIX_CFG_8822B */\n\n#define BIT_SHIFT_MDIO_PHY_ADDR_8822B 24\n#define BIT_MASK_MDIO_PHY_ADDR_8822B 0x1f\n#define BIT_MDIO_PHY_ADDR_8822B(x)                                             \\\n\t(((x) & BIT_MASK_MDIO_PHY_ADDR_8822B) << BIT_SHIFT_MDIO_PHY_ADDR_8822B)\n#define BITS_MDIO_PHY_ADDR_8822B                                               \\\n\t(BIT_MASK_MDIO_PHY_ADDR_8822B << BIT_SHIFT_MDIO_PHY_ADDR_8822B)\n#define BIT_CLEAR_MDIO_PHY_ADDR_8822B(x) ((x) & (~BITS_MDIO_PHY_ADDR_8822B))\n#define BIT_GET_MDIO_PHY_ADDR_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8822B) & BIT_MASK_MDIO_PHY_ADDR_8822B)\n#define BIT_SET_MDIO_PHY_ADDR_8822B(x, v)                                      \\\n\t(BIT_CLEAR_MDIO_PHY_ADDR_8822B(x) | BIT_MDIO_PHY_ADDR_8822B(v))\n\n#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B 10\n#define BIT_MASK_WATCH_DOG_RECORD_V1_8822B 0x3fff\n#define BIT_WATCH_DOG_RECORD_V1_8822B(x)                                       \\\n\t(((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8822B)                            \\\n\t << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B)\n#define BITS_WATCH_DOG_RECORD_V1_8822B                                         \\\n\t(BIT_MASK_WATCH_DOG_RECORD_V1_8822B                                    \\\n\t << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B)\n#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8822B(x)                                 \\\n\t((x) & (~BITS_WATCH_DOG_RECORD_V1_8822B))\n#define BIT_GET_WATCH_DOG_RECORD_V1_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B) &                        \\\n\t BIT_MASK_WATCH_DOG_RECORD_V1_8822B)\n#define BIT_SET_WATCH_DOG_RECORD_V1_8822B(x, v)                                \\\n\t(BIT_CLEAR_WATCH_DOG_RECORD_V1_8822B(x) |                              \\\n\t BIT_WATCH_DOG_RECORD_V1_8822B(v))\n\n#define BIT_R_IO_TIMEOUT_FLAG_V1_8822B BIT(9)\n#define BIT_EN_WATCH_DOG_8822B BIT(8)\n#define BIT_ECRC_EN_V1_8822B BIT(7)\n#define BIT_MDIO_RFLAG_V1_8822B BIT(6)\n#define BIT_MDIO_WFLAG_V1_8822B BIT(5)\n\n#define BIT_SHIFT_MDIO_REG_ADDR_V1_8822B 0\n#define BIT_MASK_MDIO_REG_ADDR_V1_8822B 0x1f\n#define BIT_MDIO_REG_ADDR_V1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_MDIO_REG_ADDR_V1_8822B)                               \\\n\t << BIT_SHIFT_MDIO_REG_ADDR_V1_8822B)\n#define BITS_MDIO_REG_ADDR_V1_8822B                                            \\\n\t(BIT_MASK_MDIO_REG_ADDR_V1_8822B << BIT_SHIFT_MDIO_REG_ADDR_V1_8822B)\n#define BIT_CLEAR_MDIO_REG_ADDR_V1_8822B(x)                                    \\\n\t((x) & (~BITS_MDIO_REG_ADDR_V1_8822B))\n#define BIT_GET_MDIO_REG_ADDR_V1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8822B) &                           \\\n\t BIT_MASK_MDIO_REG_ADDR_V1_8822B)\n#define BIT_SET_MDIO_REG_ADDR_V1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_MDIO_REG_ADDR_V1_8822B(x) | BIT_MDIO_REG_ADDR_V1_8822B(v))\n\n/* 2 REG_HCI_MIX_CFG_8822B */\n#define BIT_HOST_GEN2_SUPPORT_8822B BIT(20)\n\n#define BIT_SHIFT_TXDMA_ERR_FLAG_8822B 16\n#define BIT_MASK_TXDMA_ERR_FLAG_8822B 0xf\n#define BIT_TXDMA_ERR_FLAG_8822B(x)                                            \\\n\t(((x) & BIT_MASK_TXDMA_ERR_FLAG_8822B)                                 \\\n\t << BIT_SHIFT_TXDMA_ERR_FLAG_8822B)\n#define BITS_TXDMA_ERR_FLAG_8822B                                              \\\n\t(BIT_MASK_TXDMA_ERR_FLAG_8822B << BIT_SHIFT_TXDMA_ERR_FLAG_8822B)\n#define BIT_CLEAR_TXDMA_ERR_FLAG_8822B(x) ((x) & (~BITS_TXDMA_ERR_FLAG_8822B))\n#define BIT_GET_TXDMA_ERR_FLAG_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8822B) &                             \\\n\t BIT_MASK_TXDMA_ERR_FLAG_8822B)\n#define BIT_SET_TXDMA_ERR_FLAG_8822B(x, v)                                     \\\n\t(BIT_CLEAR_TXDMA_ERR_FLAG_8822B(x) | BIT_TXDMA_ERR_FLAG_8822B(v))\n\n#define BIT_SHIFT_EARLY_MODE_SEL_8822B 12\n#define BIT_MASK_EARLY_MODE_SEL_8822B 0xf\n#define BIT_EARLY_MODE_SEL_8822B(x)                                            \\\n\t(((x) & BIT_MASK_EARLY_MODE_SEL_8822B)                                 \\\n\t << BIT_SHIFT_EARLY_MODE_SEL_8822B)\n#define BITS_EARLY_MODE_SEL_8822B                                              \\\n\t(BIT_MASK_EARLY_MODE_SEL_8822B << BIT_SHIFT_EARLY_MODE_SEL_8822B)\n#define BIT_CLEAR_EARLY_MODE_SEL_8822B(x) ((x) & (~BITS_EARLY_MODE_SEL_8822B))\n#define BIT_GET_EARLY_MODE_SEL_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_EARLY_MODE_SEL_8822B) &                             \\\n\t BIT_MASK_EARLY_MODE_SEL_8822B)\n#define BIT_SET_EARLY_MODE_SEL_8822B(x, v)                                     \\\n\t(BIT_CLEAR_EARLY_MODE_SEL_8822B(x) | BIT_EARLY_MODE_SEL_8822B(v))\n\n#define BIT_EPHY_RX50_EN_8822B BIT(11)\n\n#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B 8\n#define BIT_MASK_MSI_TIMEOUT_ID_V1_8822B 0x7\n#define BIT_MSI_TIMEOUT_ID_V1_8822B(x)                                         \\\n\t(((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822B)                              \\\n\t << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B)\n#define BITS_MSI_TIMEOUT_ID_V1_8822B                                           \\\n\t(BIT_MASK_MSI_TIMEOUT_ID_V1_8822B << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B)\n#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822B(x)                                   \\\n\t((x) & (~BITS_MSI_TIMEOUT_ID_V1_8822B))\n#define BIT_GET_MSI_TIMEOUT_ID_V1_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B) &                          \\\n\t BIT_MASK_MSI_TIMEOUT_ID_V1_8822B)\n#define BIT_SET_MSI_TIMEOUT_ID_V1_8822B(x, v)                                  \\\n\t(BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822B(x) | BIT_MSI_TIMEOUT_ID_V1_8822B(v))\n\n#define BIT_RADDR_RD_8822B BIT(7)\n#define BIT_EN_MUL_TAG_8822B BIT(6)\n#define BIT_EN_EARLY_MODE_8822B BIT(5)\n#define BIT_L0S_LINK_OFF_8822B BIT(4)\n#define BIT_ACT_LINK_OFF_8822B BIT(3)\n#define BIT_EN_SLOW_MAC_TX_8822B BIT(2)\n#define BIT_EN_SLOW_MAC_RX_8822B BIT(1)\n\n/* 2 REG_STC_INT_CS_8822B(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */\n#define BIT_STC_INT_EN_8822B BIT(31)\n\n#define BIT_SHIFT_STC_INT_FLAG_8822B 16\n#define BIT_MASK_STC_INT_FLAG_8822B 0xff\n#define BIT_STC_INT_FLAG_8822B(x)                                              \\\n\t(((x) & BIT_MASK_STC_INT_FLAG_8822B) << BIT_SHIFT_STC_INT_FLAG_8822B)\n#define BITS_STC_INT_FLAG_8822B                                                \\\n\t(BIT_MASK_STC_INT_FLAG_8822B << BIT_SHIFT_STC_INT_FLAG_8822B)\n#define BIT_CLEAR_STC_INT_FLAG_8822B(x) ((x) & (~BITS_STC_INT_FLAG_8822B))\n#define BIT_GET_STC_INT_FLAG_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_STC_INT_FLAG_8822B) & BIT_MASK_STC_INT_FLAG_8822B)\n#define BIT_SET_STC_INT_FLAG_8822B(x, v)                                       \\\n\t(BIT_CLEAR_STC_INT_FLAG_8822B(x) | BIT_STC_INT_FLAG_8822B(v))\n\n#define BIT_SHIFT_STC_INT_IDX_8822B 8\n#define BIT_MASK_STC_INT_IDX_8822B 0x7\n#define BIT_STC_INT_IDX_8822B(x)                                               \\\n\t(((x) & BIT_MASK_STC_INT_IDX_8822B) << BIT_SHIFT_STC_INT_IDX_8822B)\n#define BITS_STC_INT_IDX_8822B                                                 \\\n\t(BIT_MASK_STC_INT_IDX_8822B << BIT_SHIFT_STC_INT_IDX_8822B)\n#define BIT_CLEAR_STC_INT_IDX_8822B(x) ((x) & (~BITS_STC_INT_IDX_8822B))\n#define BIT_GET_STC_INT_IDX_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_STC_INT_IDX_8822B) & BIT_MASK_STC_INT_IDX_8822B)\n#define BIT_SET_STC_INT_IDX_8822B(x, v)                                        \\\n\t(BIT_CLEAR_STC_INT_IDX_8822B(x) | BIT_STC_INT_IDX_8822B(v))\n\n#define BIT_SHIFT_STC_INT_REALTIME_CS_8822B 0\n#define BIT_MASK_STC_INT_REALTIME_CS_8822B 0x3f\n#define BIT_STC_INT_REALTIME_CS_8822B(x)                                       \\\n\t(((x) & BIT_MASK_STC_INT_REALTIME_CS_8822B)                            \\\n\t << BIT_SHIFT_STC_INT_REALTIME_CS_8822B)\n#define BITS_STC_INT_REALTIME_CS_8822B                                         \\\n\t(BIT_MASK_STC_INT_REALTIME_CS_8822B                                    \\\n\t << BIT_SHIFT_STC_INT_REALTIME_CS_8822B)\n#define BIT_CLEAR_STC_INT_REALTIME_CS_8822B(x)                                 \\\n\t((x) & (~BITS_STC_INT_REALTIME_CS_8822B))\n#define BIT_GET_STC_INT_REALTIME_CS_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8822B) &                        \\\n\t BIT_MASK_STC_INT_REALTIME_CS_8822B)\n#define BIT_SET_STC_INT_REALTIME_CS_8822B(x, v)                                \\\n\t(BIT_CLEAR_STC_INT_REALTIME_CS_8822B(x) |                              \\\n\t BIT_STC_INT_REALTIME_CS_8822B(v))\n\n/* 2 REG_ST_INT_CFG_8822B(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */\n#define BIT_STC_INT_GRP_EN_8822B BIT(31)\n\n#define BIT_SHIFT_STC_INT_EXPECT_LS_8822B 8\n#define BIT_MASK_STC_INT_EXPECT_LS_8822B 0x3f\n#define BIT_STC_INT_EXPECT_LS_8822B(x)                                         \\\n\t(((x) & BIT_MASK_STC_INT_EXPECT_LS_8822B)                              \\\n\t << BIT_SHIFT_STC_INT_EXPECT_LS_8822B)\n#define BITS_STC_INT_EXPECT_LS_8822B                                           \\\n\t(BIT_MASK_STC_INT_EXPECT_LS_8822B << BIT_SHIFT_STC_INT_EXPECT_LS_8822B)\n#define BIT_CLEAR_STC_INT_EXPECT_LS_8822B(x)                                   \\\n\t((x) & (~BITS_STC_INT_EXPECT_LS_8822B))\n#define BIT_GET_STC_INT_EXPECT_LS_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8822B) &                          \\\n\t BIT_MASK_STC_INT_EXPECT_LS_8822B)\n#define BIT_SET_STC_INT_EXPECT_LS_8822B(x, v)                                  \\\n\t(BIT_CLEAR_STC_INT_EXPECT_LS_8822B(x) | BIT_STC_INT_EXPECT_LS_8822B(v))\n\n#define BIT_SHIFT_STC_INT_EXPECT_CS_8822B 0\n#define BIT_MASK_STC_INT_EXPECT_CS_8822B 0x3f\n#define BIT_STC_INT_EXPECT_CS_8822B(x)                                         \\\n\t(((x) & BIT_MASK_STC_INT_EXPECT_CS_8822B)                              \\\n\t << BIT_SHIFT_STC_INT_EXPECT_CS_8822B)\n#define BITS_STC_INT_EXPECT_CS_8822B                                           \\\n\t(BIT_MASK_STC_INT_EXPECT_CS_8822B << BIT_SHIFT_STC_INT_EXPECT_CS_8822B)\n#define BIT_CLEAR_STC_INT_EXPECT_CS_8822B(x)                                   \\\n\t((x) & (~BITS_STC_INT_EXPECT_CS_8822B))\n#define BIT_GET_STC_INT_EXPECT_CS_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8822B) &                          \\\n\t BIT_MASK_STC_INT_EXPECT_CS_8822B)\n#define BIT_SET_STC_INT_EXPECT_CS_8822B(x, v)                                  \\\n\t(BIT_CLEAR_STC_INT_EXPECT_CS_8822B(x) | BIT_STC_INT_EXPECT_CS_8822B(v))\n\n/* 2 REG_CMU_DLY_CTRL_8822B(PCIE PHY CLOCK MGT UNIT DELAY CONTROL ) */\n#define BIT_CMU_DLY_EN_8822B BIT(31)\n#define BIT_CMU_DLY_MODE_8822B BIT(30)\n\n#define BIT_SHIFT_CMU_DLY_PRE_DIV_8822B 0\n#define BIT_MASK_CMU_DLY_PRE_DIV_8822B 0xff\n#define BIT_CMU_DLY_PRE_DIV_8822B(x)                                           \\\n\t(((x) & BIT_MASK_CMU_DLY_PRE_DIV_8822B)                                \\\n\t << BIT_SHIFT_CMU_DLY_PRE_DIV_8822B)\n#define BITS_CMU_DLY_PRE_DIV_8822B                                             \\\n\t(BIT_MASK_CMU_DLY_PRE_DIV_8822B << BIT_SHIFT_CMU_DLY_PRE_DIV_8822B)\n#define BIT_CLEAR_CMU_DLY_PRE_DIV_8822B(x) ((x) & (~BITS_CMU_DLY_PRE_DIV_8822B))\n#define BIT_GET_CMU_DLY_PRE_DIV_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8822B) &                            \\\n\t BIT_MASK_CMU_DLY_PRE_DIV_8822B)\n#define BIT_SET_CMU_DLY_PRE_DIV_8822B(x, v)                                    \\\n\t(BIT_CLEAR_CMU_DLY_PRE_DIV_8822B(x) | BIT_CMU_DLY_PRE_DIV_8822B(v))\n\n/* 2 REG_CMU_DLY_CFG_8822B(PCIE PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */\n\n#define BIT_SHIFT_CMU_DLY_LTR_A2I_8822B 24\n#define BIT_MASK_CMU_DLY_LTR_A2I_8822B 0xff\n#define BIT_CMU_DLY_LTR_A2I_8822B(x)                                           \\\n\t(((x) & BIT_MASK_CMU_DLY_LTR_A2I_8822B)                                \\\n\t << BIT_SHIFT_CMU_DLY_LTR_A2I_8822B)\n#define BITS_CMU_DLY_LTR_A2I_8822B                                             \\\n\t(BIT_MASK_CMU_DLY_LTR_A2I_8822B << BIT_SHIFT_CMU_DLY_LTR_A2I_8822B)\n#define BIT_CLEAR_CMU_DLY_LTR_A2I_8822B(x) ((x) & (~BITS_CMU_DLY_LTR_A2I_8822B))\n#define BIT_GET_CMU_DLY_LTR_A2I_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8822B) &                            \\\n\t BIT_MASK_CMU_DLY_LTR_A2I_8822B)\n#define BIT_SET_CMU_DLY_LTR_A2I_8822B(x, v)                                    \\\n\t(BIT_CLEAR_CMU_DLY_LTR_A2I_8822B(x) | BIT_CMU_DLY_LTR_A2I_8822B(v))\n\n#define BIT_SHIFT_CMU_DLY_LTR_I2A_8822B 16\n#define BIT_MASK_CMU_DLY_LTR_I2A_8822B 0xff\n#define BIT_CMU_DLY_LTR_I2A_8822B(x)                                           \\\n\t(((x) & BIT_MASK_CMU_DLY_LTR_I2A_8822B)                                \\\n\t << BIT_SHIFT_CMU_DLY_LTR_I2A_8822B)\n#define BITS_CMU_DLY_LTR_I2A_8822B                                             \\\n\t(BIT_MASK_CMU_DLY_LTR_I2A_8822B << BIT_SHIFT_CMU_DLY_LTR_I2A_8822B)\n#define BIT_CLEAR_CMU_DLY_LTR_I2A_8822B(x) ((x) & (~BITS_CMU_DLY_LTR_I2A_8822B))\n#define BIT_GET_CMU_DLY_LTR_I2A_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8822B) &                            \\\n\t BIT_MASK_CMU_DLY_LTR_I2A_8822B)\n#define BIT_SET_CMU_DLY_LTR_I2A_8822B(x, v)                                    \\\n\t(BIT_CLEAR_CMU_DLY_LTR_I2A_8822B(x) | BIT_CMU_DLY_LTR_I2A_8822B(v))\n\n#define BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B 8\n#define BIT_MASK_CMU_DLY_LTR_IDLE_8822B 0xff\n#define BIT_CMU_DLY_LTR_IDLE_8822B(x)                                          \\\n\t(((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8822B)                               \\\n\t << BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B)\n#define BITS_CMU_DLY_LTR_IDLE_8822B                                            \\\n\t(BIT_MASK_CMU_DLY_LTR_IDLE_8822B << BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B)\n#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8822B(x)                                    \\\n\t((x) & (~BITS_CMU_DLY_LTR_IDLE_8822B))\n#define BIT_GET_CMU_DLY_LTR_IDLE_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B) &                           \\\n\t BIT_MASK_CMU_DLY_LTR_IDLE_8822B)\n#define BIT_SET_CMU_DLY_LTR_IDLE_8822B(x, v)                                   \\\n\t(BIT_CLEAR_CMU_DLY_LTR_IDLE_8822B(x) | BIT_CMU_DLY_LTR_IDLE_8822B(v))\n\n#define BIT_SHIFT_CMU_DLY_LTR_ACT_8822B 0\n#define BIT_MASK_CMU_DLY_LTR_ACT_8822B 0xff\n#define BIT_CMU_DLY_LTR_ACT_8822B(x)                                           \\\n\t(((x) & BIT_MASK_CMU_DLY_LTR_ACT_8822B)                                \\\n\t << BIT_SHIFT_CMU_DLY_LTR_ACT_8822B)\n#define BITS_CMU_DLY_LTR_ACT_8822B                                             \\\n\t(BIT_MASK_CMU_DLY_LTR_ACT_8822B << BIT_SHIFT_CMU_DLY_LTR_ACT_8822B)\n#define BIT_CLEAR_CMU_DLY_LTR_ACT_8822B(x) ((x) & (~BITS_CMU_DLY_LTR_ACT_8822B))\n#define BIT_GET_CMU_DLY_LTR_ACT_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8822B) &                            \\\n\t BIT_MASK_CMU_DLY_LTR_ACT_8822B)\n#define BIT_SET_CMU_DLY_LTR_ACT_8822B(x, v)                                    \\\n\t(BIT_CLEAR_CMU_DLY_LTR_ACT_8822B(x) | BIT_CMU_DLY_LTR_ACT_8822B(v))\n\n/* 2 REG_H2CQ_TXBD_DESA_8822B */\n\n#define BIT_SHIFT_H2CQ_TXBD_DESA_8822B 0\n#define BIT_MASK_H2CQ_TXBD_DESA_8822B 0xffffffffffffffffL\n#define BIT_H2CQ_TXBD_DESA_8822B(x)                                            \\\n\t(((x) & BIT_MASK_H2CQ_TXBD_DESA_8822B)                                 \\\n\t << BIT_SHIFT_H2CQ_TXBD_DESA_8822B)\n#define BITS_H2CQ_TXBD_DESA_8822B                                              \\\n\t(BIT_MASK_H2CQ_TXBD_DESA_8822B << BIT_SHIFT_H2CQ_TXBD_DESA_8822B)\n#define BIT_CLEAR_H2CQ_TXBD_DESA_8822B(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8822B))\n#define BIT_GET_H2CQ_TXBD_DESA_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8822B) &                             \\\n\t BIT_MASK_H2CQ_TXBD_DESA_8822B)\n#define BIT_SET_H2CQ_TXBD_DESA_8822B(x, v)                                     \\\n\t(BIT_CLEAR_H2CQ_TXBD_DESA_8822B(x) | BIT_H2CQ_TXBD_DESA_8822B(v))\n\n/* 2 REG_H2CQ_TXBD_NUM_8822B */\n#define BIT_PCIE_H2CQ_FLAG_8822B BIT(14)\n\n#define BIT_SHIFT_H2CQ_DESC_MODE_8822B 12\n#define BIT_MASK_H2CQ_DESC_MODE_8822B 0x3\n#define BIT_H2CQ_DESC_MODE_8822B(x)                                            \\\n\t(((x) & BIT_MASK_H2CQ_DESC_MODE_8822B)                                 \\\n\t << BIT_SHIFT_H2CQ_DESC_MODE_8822B)\n#define BITS_H2CQ_DESC_MODE_8822B                                              \\\n\t(BIT_MASK_H2CQ_DESC_MODE_8822B << BIT_SHIFT_H2CQ_DESC_MODE_8822B)\n#define BIT_CLEAR_H2CQ_DESC_MODE_8822B(x) ((x) & (~BITS_H2CQ_DESC_MODE_8822B))\n#define BIT_GET_H2CQ_DESC_MODE_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8822B) &                             \\\n\t BIT_MASK_H2CQ_DESC_MODE_8822B)\n#define BIT_SET_H2CQ_DESC_MODE_8822B(x, v)                                     \\\n\t(BIT_CLEAR_H2CQ_DESC_MODE_8822B(x) | BIT_H2CQ_DESC_MODE_8822B(v))\n\n#define BIT_SHIFT_H2CQ_DESC_NUM_8822B 0\n#define BIT_MASK_H2CQ_DESC_NUM_8822B 0xfff\n#define BIT_H2CQ_DESC_NUM_8822B(x)                                             \\\n\t(((x) & BIT_MASK_H2CQ_DESC_NUM_8822B) << BIT_SHIFT_H2CQ_DESC_NUM_8822B)\n#define BITS_H2CQ_DESC_NUM_8822B                                               \\\n\t(BIT_MASK_H2CQ_DESC_NUM_8822B << BIT_SHIFT_H2CQ_DESC_NUM_8822B)\n#define BIT_CLEAR_H2CQ_DESC_NUM_8822B(x) ((x) & (~BITS_H2CQ_DESC_NUM_8822B))\n#define BIT_GET_H2CQ_DESC_NUM_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8822B) & BIT_MASK_H2CQ_DESC_NUM_8822B)\n#define BIT_SET_H2CQ_DESC_NUM_8822B(x, v)                                      \\\n\t(BIT_CLEAR_H2CQ_DESC_NUM_8822B(x) | BIT_H2CQ_DESC_NUM_8822B(v))\n\n/* 2 REG_H2CQ_TXBD_IDX_8822B */\n\n#define BIT_SHIFT_H2CQ_HW_IDX_8822B 16\n#define BIT_MASK_H2CQ_HW_IDX_8822B 0xfff\n#define BIT_H2CQ_HW_IDX_8822B(x)                                               \\\n\t(((x) & BIT_MASK_H2CQ_HW_IDX_8822B) << BIT_SHIFT_H2CQ_HW_IDX_8822B)\n#define BITS_H2CQ_HW_IDX_8822B                                                 \\\n\t(BIT_MASK_H2CQ_HW_IDX_8822B << BIT_SHIFT_H2CQ_HW_IDX_8822B)\n#define BIT_CLEAR_H2CQ_HW_IDX_8822B(x) ((x) & (~BITS_H2CQ_HW_IDX_8822B))\n#define BIT_GET_H2CQ_HW_IDX_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_H2CQ_HW_IDX_8822B) & BIT_MASK_H2CQ_HW_IDX_8822B)\n#define BIT_SET_H2CQ_HW_IDX_8822B(x, v)                                        \\\n\t(BIT_CLEAR_H2CQ_HW_IDX_8822B(x) | BIT_H2CQ_HW_IDX_8822B(v))\n\n#define BIT_SHIFT_H2CQ_HOST_IDX_8822B 0\n#define BIT_MASK_H2CQ_HOST_IDX_8822B 0xfff\n#define BIT_H2CQ_HOST_IDX_8822B(x)                                             \\\n\t(((x) & BIT_MASK_H2CQ_HOST_IDX_8822B) << BIT_SHIFT_H2CQ_HOST_IDX_8822B)\n#define BITS_H2CQ_HOST_IDX_8822B                                               \\\n\t(BIT_MASK_H2CQ_HOST_IDX_8822B << BIT_SHIFT_H2CQ_HOST_IDX_8822B)\n#define BIT_CLEAR_H2CQ_HOST_IDX_8822B(x) ((x) & (~BITS_H2CQ_HOST_IDX_8822B))\n#define BIT_GET_H2CQ_HOST_IDX_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8822B) & BIT_MASK_H2CQ_HOST_IDX_8822B)\n#define BIT_SET_H2CQ_HOST_IDX_8822B(x, v)                                      \\\n\t(BIT_CLEAR_H2CQ_HOST_IDX_8822B(x) | BIT_H2CQ_HOST_IDX_8822B(v))\n\n/* 2 REG_H2CQ_CSR_8822B[31:0] (H2CQ CONTROL AND STATUS) */\n#define BIT_H2CQ_FULL_8822B BIT(31)\n#define BIT_CLR_H2CQ_HOST_IDX_8822B BIT(16)\n#define BIT_CLR_H2CQ_HW_IDX_8822B BIT(8)\n#define BIT_STOP_H2CQ_8822B BIT(0)\n\n/* 2 REG_CHANGE_PCIE_SPEED_8822B */\n#define BIT_CHANGE_PCIE_SPEED_8822B BIT(18)\n\n#define BIT_SHIFT_GEN1_GEN2_8822B 16\n#define BIT_MASK_GEN1_GEN2_8822B 0x3\n#define BIT_GEN1_GEN2_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_GEN1_GEN2_8822B) << BIT_SHIFT_GEN1_GEN2_8822B)\n#define BITS_GEN1_GEN2_8822B                                                   \\\n\t(BIT_MASK_GEN1_GEN2_8822B << BIT_SHIFT_GEN1_GEN2_8822B)\n#define BIT_CLEAR_GEN1_GEN2_8822B(x) ((x) & (~BITS_GEN1_GEN2_8822B))\n#define BIT_GET_GEN1_GEN2_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_GEN1_GEN2_8822B) & BIT_MASK_GEN1_GEN2_8822B)\n#define BIT_SET_GEN1_GEN2_8822B(x, v)                                          \\\n\t(BIT_CLEAR_GEN1_GEN2_8822B(x) | BIT_GEN1_GEN2_8822B(v))\n\n#define BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B 8\n#define BIT_MASK_RXDMA_ERROR_COUNTER_8822B 0xff\n#define BIT_RXDMA_ERROR_COUNTER_8822B(x)                                       \\\n\t(((x) & BIT_MASK_RXDMA_ERROR_COUNTER_8822B)                            \\\n\t << BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B)\n#define BITS_RXDMA_ERROR_COUNTER_8822B                                         \\\n\t(BIT_MASK_RXDMA_ERROR_COUNTER_8822B                                    \\\n\t << BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B)\n#define BIT_CLEAR_RXDMA_ERROR_COUNTER_8822B(x)                                 \\\n\t((x) & (~BITS_RXDMA_ERROR_COUNTER_8822B))\n#define BIT_GET_RXDMA_ERROR_COUNTER_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B) &                        \\\n\t BIT_MASK_RXDMA_ERROR_COUNTER_8822B)\n#define BIT_SET_RXDMA_ERROR_COUNTER_8822B(x, v)                                \\\n\t(BIT_CLEAR_RXDMA_ERROR_COUNTER_8822B(x) |                              \\\n\t BIT_RXDMA_ERROR_COUNTER_8822B(v))\n\n#define BIT_TXDMA_ERROR_HANDLE_STATUS_8822B BIT(7)\n#define BIT_TXDMA_ERROR_PULSE_8822B BIT(6)\n#define BIT_TXDMA_STUCK_ERROR_HANDLE_ENABLE_8822B BIT(5)\n#define BIT_TXDMA_RETURN_ERROR_ENABLE_8822B BIT(4)\n#define BIT_RXDMA_ERROR_HANDLE_STATUS_8822B BIT(3)\n\n#define BIT_SHIFT_AUTO_HANG_RELEASE_8822B 0\n#define BIT_MASK_AUTO_HANG_RELEASE_8822B 0x7\n#define BIT_AUTO_HANG_RELEASE_8822B(x)                                         \\\n\t(((x) & BIT_MASK_AUTO_HANG_RELEASE_8822B)                              \\\n\t << BIT_SHIFT_AUTO_HANG_RELEASE_8822B)\n#define BITS_AUTO_HANG_RELEASE_8822B                                           \\\n\t(BIT_MASK_AUTO_HANG_RELEASE_8822B << BIT_SHIFT_AUTO_HANG_RELEASE_8822B)\n#define BIT_CLEAR_AUTO_HANG_RELEASE_8822B(x)                                   \\\n\t((x) & (~BITS_AUTO_HANG_RELEASE_8822B))\n#define BIT_GET_AUTO_HANG_RELEASE_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_AUTO_HANG_RELEASE_8822B) &                          \\\n\t BIT_MASK_AUTO_HANG_RELEASE_8822B)\n#define BIT_SET_AUTO_HANG_RELEASE_8822B(x, v)                                  \\\n\t(BIT_CLEAR_AUTO_HANG_RELEASE_8822B(x) | BIT_AUTO_HANG_RELEASE_8822B(v))\n\n/* 2 REG_OLD_DEHANG_8822B */\n#define BIT_OLD_DEHANG_8822B BIT(1)\n\n/* 2 REG_Q0_INFO_8822B */\n\n#define BIT_SHIFT_QUEUEMACID_Q0_V1_8822B 25\n#define BIT_MASK_QUEUEMACID_Q0_V1_8822B 0x7f\n#define BIT_QUEUEMACID_Q0_V1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q0_V1_8822B)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q0_V1_8822B)\n#define BITS_QUEUEMACID_Q0_V1_8822B                                            \\\n\t(BIT_MASK_QUEUEMACID_Q0_V1_8822B << BIT_SHIFT_QUEUEMACID_Q0_V1_8822B)\n#define BIT_CLEAR_QUEUEMACID_Q0_V1_8822B(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q0_V1_8822B))\n#define BIT_GET_QUEUEMACID_Q0_V1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8822B) &                           \\\n\t BIT_MASK_QUEUEMACID_Q0_V1_8822B)\n#define BIT_SET_QUEUEMACID_Q0_V1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q0_V1_8822B(x) | BIT_QUEUEMACID_Q0_V1_8822B(v))\n\n#define BIT_SHIFT_QUEUEAC_Q0_V1_8822B 23\n#define BIT_MASK_QUEUEAC_Q0_V1_8822B 0x3\n#define BIT_QUEUEAC_Q0_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q0_V1_8822B) << BIT_SHIFT_QUEUEAC_Q0_V1_8822B)\n#define BITS_QUEUEAC_Q0_V1_8822B                                               \\\n\t(BIT_MASK_QUEUEAC_Q0_V1_8822B << BIT_SHIFT_QUEUEAC_Q0_V1_8822B)\n#define BIT_CLEAR_QUEUEAC_Q0_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8822B))\n#define BIT_GET_QUEUEAC_Q0_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8822B) & BIT_MASK_QUEUEAC_Q0_V1_8822B)\n#define BIT_SET_QUEUEAC_Q0_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q0_V1_8822B(x) | BIT_QUEUEAC_Q0_V1_8822B(v))\n\n#define BIT_TIDEMPTY_Q0_V1_8822B BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q0_V2_8822B 11\n#define BIT_MASK_TAIL_PKT_Q0_V2_8822B 0x7ff\n#define BIT_TAIL_PKT_Q0_V2_8822B(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q0_V2_8822B)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q0_V2_8822B)\n#define BITS_TAIL_PKT_Q0_V2_8822B                                              \\\n\t(BIT_MASK_TAIL_PKT_Q0_V2_8822B << BIT_SHIFT_TAIL_PKT_Q0_V2_8822B)\n#define BIT_CLEAR_TAIL_PKT_Q0_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8822B))\n#define BIT_GET_TAIL_PKT_Q0_V2_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8822B) &                             \\\n\t BIT_MASK_TAIL_PKT_Q0_V2_8822B)\n#define BIT_SET_TAIL_PKT_Q0_V2_8822B(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q0_V2_8822B(x) | BIT_TAIL_PKT_Q0_V2_8822B(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q0_V1_8822B 0\n#define BIT_MASK_HEAD_PKT_Q0_V1_8822B 0x7ff\n#define BIT_HEAD_PKT_Q0_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q0_V1_8822B)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q0_V1_8822B)\n#define BITS_HEAD_PKT_Q0_V1_8822B                                              \\\n\t(BIT_MASK_HEAD_PKT_Q0_V1_8822B << BIT_SHIFT_HEAD_PKT_Q0_V1_8822B)\n#define BIT_CLEAR_HEAD_PKT_Q0_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8822B))\n#define BIT_GET_HEAD_PKT_Q0_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8822B) &                             \\\n\t BIT_MASK_HEAD_PKT_Q0_V1_8822B)\n#define BIT_SET_HEAD_PKT_Q0_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q0_V1_8822B(x) | BIT_HEAD_PKT_Q0_V1_8822B(v))\n\n/* 2 REG_Q1_INFO_8822B */\n\n#define BIT_SHIFT_QUEUEMACID_Q1_V1_8822B 25\n#define BIT_MASK_QUEUEMACID_Q1_V1_8822B 0x7f\n#define BIT_QUEUEMACID_Q1_V1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q1_V1_8822B)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q1_V1_8822B)\n#define BITS_QUEUEMACID_Q1_V1_8822B                                            \\\n\t(BIT_MASK_QUEUEMACID_Q1_V1_8822B << BIT_SHIFT_QUEUEMACID_Q1_V1_8822B)\n#define BIT_CLEAR_QUEUEMACID_Q1_V1_8822B(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q1_V1_8822B))\n#define BIT_GET_QUEUEMACID_Q1_V1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8822B) &                           \\\n\t BIT_MASK_QUEUEMACID_Q1_V1_8822B)\n#define BIT_SET_QUEUEMACID_Q1_V1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q1_V1_8822B(x) | BIT_QUEUEMACID_Q1_V1_8822B(v))\n\n#define BIT_SHIFT_QUEUEAC_Q1_V1_8822B 23\n#define BIT_MASK_QUEUEAC_Q1_V1_8822B 0x3\n#define BIT_QUEUEAC_Q1_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q1_V1_8822B) << BIT_SHIFT_QUEUEAC_Q1_V1_8822B)\n#define BITS_QUEUEAC_Q1_V1_8822B                                               \\\n\t(BIT_MASK_QUEUEAC_Q1_V1_8822B << BIT_SHIFT_QUEUEAC_Q1_V1_8822B)\n#define BIT_CLEAR_QUEUEAC_Q1_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8822B))\n#define BIT_GET_QUEUEAC_Q1_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8822B) & BIT_MASK_QUEUEAC_Q1_V1_8822B)\n#define BIT_SET_QUEUEAC_Q1_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q1_V1_8822B(x) | BIT_QUEUEAC_Q1_V1_8822B(v))\n\n#define BIT_TIDEMPTY_Q1_V1_8822B BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q1_V2_8822B 11\n#define BIT_MASK_TAIL_PKT_Q1_V2_8822B 0x7ff\n#define BIT_TAIL_PKT_Q1_V2_8822B(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q1_V2_8822B)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q1_V2_8822B)\n#define BITS_TAIL_PKT_Q1_V2_8822B                                              \\\n\t(BIT_MASK_TAIL_PKT_Q1_V2_8822B << BIT_SHIFT_TAIL_PKT_Q1_V2_8822B)\n#define BIT_CLEAR_TAIL_PKT_Q1_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8822B))\n#define BIT_GET_TAIL_PKT_Q1_V2_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8822B) &                             \\\n\t BIT_MASK_TAIL_PKT_Q1_V2_8822B)\n#define BIT_SET_TAIL_PKT_Q1_V2_8822B(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q1_V2_8822B(x) | BIT_TAIL_PKT_Q1_V2_8822B(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q1_V1_8822B 0\n#define BIT_MASK_HEAD_PKT_Q1_V1_8822B 0x7ff\n#define BIT_HEAD_PKT_Q1_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q1_V1_8822B)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q1_V1_8822B)\n#define BITS_HEAD_PKT_Q1_V1_8822B                                              \\\n\t(BIT_MASK_HEAD_PKT_Q1_V1_8822B << BIT_SHIFT_HEAD_PKT_Q1_V1_8822B)\n#define BIT_CLEAR_HEAD_PKT_Q1_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8822B))\n#define BIT_GET_HEAD_PKT_Q1_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8822B) &                             \\\n\t BIT_MASK_HEAD_PKT_Q1_V1_8822B)\n#define BIT_SET_HEAD_PKT_Q1_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q1_V1_8822B(x) | BIT_HEAD_PKT_Q1_V1_8822B(v))\n\n/* 2 REG_Q2_INFO_8822B */\n\n#define BIT_SHIFT_QUEUEMACID_Q2_V1_8822B 25\n#define BIT_MASK_QUEUEMACID_Q2_V1_8822B 0x7f\n#define BIT_QUEUEMACID_Q2_V1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q2_V1_8822B)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q2_V1_8822B)\n#define BITS_QUEUEMACID_Q2_V1_8822B                                            \\\n\t(BIT_MASK_QUEUEMACID_Q2_V1_8822B << BIT_SHIFT_QUEUEMACID_Q2_V1_8822B)\n#define BIT_CLEAR_QUEUEMACID_Q2_V1_8822B(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q2_V1_8822B))\n#define BIT_GET_QUEUEMACID_Q2_V1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8822B) &                           \\\n\t BIT_MASK_QUEUEMACID_Q2_V1_8822B)\n#define BIT_SET_QUEUEMACID_Q2_V1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q2_V1_8822B(x) | BIT_QUEUEMACID_Q2_V1_8822B(v))\n\n#define BIT_SHIFT_QUEUEAC_Q2_V1_8822B 23\n#define BIT_MASK_QUEUEAC_Q2_V1_8822B 0x3\n#define BIT_QUEUEAC_Q2_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q2_V1_8822B) << BIT_SHIFT_QUEUEAC_Q2_V1_8822B)\n#define BITS_QUEUEAC_Q2_V1_8822B                                               \\\n\t(BIT_MASK_QUEUEAC_Q2_V1_8822B << BIT_SHIFT_QUEUEAC_Q2_V1_8822B)\n#define BIT_CLEAR_QUEUEAC_Q2_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8822B))\n#define BIT_GET_QUEUEAC_Q2_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8822B) & BIT_MASK_QUEUEAC_Q2_V1_8822B)\n#define BIT_SET_QUEUEAC_Q2_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q2_V1_8822B(x) | BIT_QUEUEAC_Q2_V1_8822B(v))\n\n#define BIT_TIDEMPTY_Q2_V1_8822B BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q2_V2_8822B 11\n#define BIT_MASK_TAIL_PKT_Q2_V2_8822B 0x7ff\n#define BIT_TAIL_PKT_Q2_V2_8822B(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q2_V2_8822B)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q2_V2_8822B)\n#define BITS_TAIL_PKT_Q2_V2_8822B                                              \\\n\t(BIT_MASK_TAIL_PKT_Q2_V2_8822B << BIT_SHIFT_TAIL_PKT_Q2_V2_8822B)\n#define BIT_CLEAR_TAIL_PKT_Q2_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8822B))\n#define BIT_GET_TAIL_PKT_Q2_V2_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8822B) &                             \\\n\t BIT_MASK_TAIL_PKT_Q2_V2_8822B)\n#define BIT_SET_TAIL_PKT_Q2_V2_8822B(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q2_V2_8822B(x) | BIT_TAIL_PKT_Q2_V2_8822B(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q2_V1_8822B 0\n#define BIT_MASK_HEAD_PKT_Q2_V1_8822B 0x7ff\n#define BIT_HEAD_PKT_Q2_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q2_V1_8822B)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q2_V1_8822B)\n#define BITS_HEAD_PKT_Q2_V1_8822B                                              \\\n\t(BIT_MASK_HEAD_PKT_Q2_V1_8822B << BIT_SHIFT_HEAD_PKT_Q2_V1_8822B)\n#define BIT_CLEAR_HEAD_PKT_Q2_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8822B))\n#define BIT_GET_HEAD_PKT_Q2_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8822B) &                             \\\n\t BIT_MASK_HEAD_PKT_Q2_V1_8822B)\n#define BIT_SET_HEAD_PKT_Q2_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q2_V1_8822B(x) | BIT_HEAD_PKT_Q2_V1_8822B(v))\n\n/* 2 REG_Q3_INFO_8822B */\n\n#define BIT_SHIFT_QUEUEMACID_Q3_V1_8822B 25\n#define BIT_MASK_QUEUEMACID_Q3_V1_8822B 0x7f\n#define BIT_QUEUEMACID_Q3_V1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q3_V1_8822B)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q3_V1_8822B)\n#define BITS_QUEUEMACID_Q3_V1_8822B                                            \\\n\t(BIT_MASK_QUEUEMACID_Q3_V1_8822B << BIT_SHIFT_QUEUEMACID_Q3_V1_8822B)\n#define BIT_CLEAR_QUEUEMACID_Q3_V1_8822B(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q3_V1_8822B))\n#define BIT_GET_QUEUEMACID_Q3_V1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8822B) &                           \\\n\t BIT_MASK_QUEUEMACID_Q3_V1_8822B)\n#define BIT_SET_QUEUEMACID_Q3_V1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q3_V1_8822B(x) | BIT_QUEUEMACID_Q3_V1_8822B(v))\n\n#define BIT_SHIFT_QUEUEAC_Q3_V1_8822B 23\n#define BIT_MASK_QUEUEAC_Q3_V1_8822B 0x3\n#define BIT_QUEUEAC_Q3_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q3_V1_8822B) << BIT_SHIFT_QUEUEAC_Q3_V1_8822B)\n#define BITS_QUEUEAC_Q3_V1_8822B                                               \\\n\t(BIT_MASK_QUEUEAC_Q3_V1_8822B << BIT_SHIFT_QUEUEAC_Q3_V1_8822B)\n#define BIT_CLEAR_QUEUEAC_Q3_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8822B))\n#define BIT_GET_QUEUEAC_Q3_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8822B) & BIT_MASK_QUEUEAC_Q3_V1_8822B)\n#define BIT_SET_QUEUEAC_Q3_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q3_V1_8822B(x) | BIT_QUEUEAC_Q3_V1_8822B(v))\n\n#define BIT_TIDEMPTY_Q3_V1_8822B BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q3_V2_8822B 11\n#define BIT_MASK_TAIL_PKT_Q3_V2_8822B 0x7ff\n#define BIT_TAIL_PKT_Q3_V2_8822B(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q3_V2_8822B)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q3_V2_8822B)\n#define BITS_TAIL_PKT_Q3_V2_8822B                                              \\\n\t(BIT_MASK_TAIL_PKT_Q3_V2_8822B << BIT_SHIFT_TAIL_PKT_Q3_V2_8822B)\n#define BIT_CLEAR_TAIL_PKT_Q3_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8822B))\n#define BIT_GET_TAIL_PKT_Q3_V2_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8822B) &                             \\\n\t BIT_MASK_TAIL_PKT_Q3_V2_8822B)\n#define BIT_SET_TAIL_PKT_Q3_V2_8822B(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q3_V2_8822B(x) | BIT_TAIL_PKT_Q3_V2_8822B(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q3_V1_8822B 0\n#define BIT_MASK_HEAD_PKT_Q3_V1_8822B 0x7ff\n#define BIT_HEAD_PKT_Q3_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q3_V1_8822B)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q3_V1_8822B)\n#define BITS_HEAD_PKT_Q3_V1_8822B                                              \\\n\t(BIT_MASK_HEAD_PKT_Q3_V1_8822B << BIT_SHIFT_HEAD_PKT_Q3_V1_8822B)\n#define BIT_CLEAR_HEAD_PKT_Q3_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8822B))\n#define BIT_GET_HEAD_PKT_Q3_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8822B) &                             \\\n\t BIT_MASK_HEAD_PKT_Q3_V1_8822B)\n#define BIT_SET_HEAD_PKT_Q3_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q3_V1_8822B(x) | BIT_HEAD_PKT_Q3_V1_8822B(v))\n\n/* 2 REG_MGQ_INFO_8822B */\n\n#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B 25\n#define BIT_MASK_QUEUEMACID_MGQ_V1_8822B 0x7f\n#define BIT_QUEUEMACID_MGQ_V1_8822B(x)                                         \\\n\t(((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8822B)                              \\\n\t << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B)\n#define BITS_QUEUEMACID_MGQ_V1_8822B                                           \\\n\t(BIT_MASK_QUEUEMACID_MGQ_V1_8822B << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B)\n#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8822B(x)                                   \\\n\t((x) & (~BITS_QUEUEMACID_MGQ_V1_8822B))\n#define BIT_GET_QUEUEMACID_MGQ_V1_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B) &                          \\\n\t BIT_MASK_QUEUEMACID_MGQ_V1_8822B)\n#define BIT_SET_QUEUEMACID_MGQ_V1_8822B(x, v)                                  \\\n\t(BIT_CLEAR_QUEUEMACID_MGQ_V1_8822B(x) | BIT_QUEUEMACID_MGQ_V1_8822B(v))\n\n#define BIT_SHIFT_QUEUEAC_MGQ_V1_8822B 23\n#define BIT_MASK_QUEUEAC_MGQ_V1_8822B 0x3\n#define BIT_QUEUEAC_MGQ_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_QUEUEAC_MGQ_V1_8822B)                                 \\\n\t << BIT_SHIFT_QUEUEAC_MGQ_V1_8822B)\n#define BITS_QUEUEAC_MGQ_V1_8822B                                              \\\n\t(BIT_MASK_QUEUEAC_MGQ_V1_8822B << BIT_SHIFT_QUEUEAC_MGQ_V1_8822B)\n#define BIT_CLEAR_QUEUEAC_MGQ_V1_8822B(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8822B))\n#define BIT_GET_QUEUEAC_MGQ_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8822B) &                             \\\n\t BIT_MASK_QUEUEAC_MGQ_V1_8822B)\n#define BIT_SET_QUEUEAC_MGQ_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_QUEUEAC_MGQ_V1_8822B(x) | BIT_QUEUEAC_MGQ_V1_8822B(v))\n\n#define BIT_TIDEMPTY_MGQ_V1_8822B BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B 11\n#define BIT_MASK_TAIL_PKT_MGQ_V2_8822B 0x7ff\n#define BIT_TAIL_PKT_MGQ_V2_8822B(x)                                           \\\n\t(((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8822B)                                \\\n\t << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B)\n#define BITS_TAIL_PKT_MGQ_V2_8822B                                             \\\n\t(BIT_MASK_TAIL_PKT_MGQ_V2_8822B << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B)\n#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8822B))\n#define BIT_GET_TAIL_PKT_MGQ_V2_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B) &                            \\\n\t BIT_MASK_TAIL_PKT_MGQ_V2_8822B)\n#define BIT_SET_TAIL_PKT_MGQ_V2_8822B(x, v)                                    \\\n\t(BIT_CLEAR_TAIL_PKT_MGQ_V2_8822B(x) | BIT_TAIL_PKT_MGQ_V2_8822B(v))\n\n#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B 0\n#define BIT_MASK_HEAD_PKT_MGQ_V1_8822B 0x7ff\n#define BIT_HEAD_PKT_MGQ_V1_8822B(x)                                           \\\n\t(((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8822B)                                \\\n\t << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B)\n#define BITS_HEAD_PKT_MGQ_V1_8822B                                             \\\n\t(BIT_MASK_HEAD_PKT_MGQ_V1_8822B << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B)\n#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8822B))\n#define BIT_GET_HEAD_PKT_MGQ_V1_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B) &                            \\\n\t BIT_MASK_HEAD_PKT_MGQ_V1_8822B)\n#define BIT_SET_HEAD_PKT_MGQ_V1_8822B(x, v)                                    \\\n\t(BIT_CLEAR_HEAD_PKT_MGQ_V1_8822B(x) | BIT_HEAD_PKT_MGQ_V1_8822B(v))\n\n/* 2 REG_HIQ_INFO_8822B */\n\n#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B 25\n#define BIT_MASK_QUEUEMACID_HIQ_V1_8822B 0x7f\n#define BIT_QUEUEMACID_HIQ_V1_8822B(x)                                         \\\n\t(((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8822B)                              \\\n\t << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B)\n#define BITS_QUEUEMACID_HIQ_V1_8822B                                           \\\n\t(BIT_MASK_QUEUEMACID_HIQ_V1_8822B << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B)\n#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8822B(x)                                   \\\n\t((x) & (~BITS_QUEUEMACID_HIQ_V1_8822B))\n#define BIT_GET_QUEUEMACID_HIQ_V1_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B) &                          \\\n\t BIT_MASK_QUEUEMACID_HIQ_V1_8822B)\n#define BIT_SET_QUEUEMACID_HIQ_V1_8822B(x, v)                                  \\\n\t(BIT_CLEAR_QUEUEMACID_HIQ_V1_8822B(x) | BIT_QUEUEMACID_HIQ_V1_8822B(v))\n\n#define BIT_SHIFT_QUEUEAC_HIQ_V1_8822B 23\n#define BIT_MASK_QUEUEAC_HIQ_V1_8822B 0x3\n#define BIT_QUEUEAC_HIQ_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_QUEUEAC_HIQ_V1_8822B)                                 \\\n\t << BIT_SHIFT_QUEUEAC_HIQ_V1_8822B)\n#define BITS_QUEUEAC_HIQ_V1_8822B                                              \\\n\t(BIT_MASK_QUEUEAC_HIQ_V1_8822B << BIT_SHIFT_QUEUEAC_HIQ_V1_8822B)\n#define BIT_CLEAR_QUEUEAC_HIQ_V1_8822B(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8822B))\n#define BIT_GET_QUEUEAC_HIQ_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8822B) &                             \\\n\t BIT_MASK_QUEUEAC_HIQ_V1_8822B)\n#define BIT_SET_QUEUEAC_HIQ_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_QUEUEAC_HIQ_V1_8822B(x) | BIT_QUEUEAC_HIQ_V1_8822B(v))\n\n#define BIT_TIDEMPTY_HIQ_V1_8822B BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B 11\n#define BIT_MASK_TAIL_PKT_HIQ_V2_8822B 0x7ff\n#define BIT_TAIL_PKT_HIQ_V2_8822B(x)                                           \\\n\t(((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8822B)                                \\\n\t << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B)\n#define BITS_TAIL_PKT_HIQ_V2_8822B                                             \\\n\t(BIT_MASK_TAIL_PKT_HIQ_V2_8822B << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B)\n#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8822B))\n#define BIT_GET_TAIL_PKT_HIQ_V2_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B) &                            \\\n\t BIT_MASK_TAIL_PKT_HIQ_V2_8822B)\n#define BIT_SET_TAIL_PKT_HIQ_V2_8822B(x, v)                                    \\\n\t(BIT_CLEAR_TAIL_PKT_HIQ_V2_8822B(x) | BIT_TAIL_PKT_HIQ_V2_8822B(v))\n\n#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B 0\n#define BIT_MASK_HEAD_PKT_HIQ_V1_8822B 0x7ff\n#define BIT_HEAD_PKT_HIQ_V1_8822B(x)                                           \\\n\t(((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8822B)                                \\\n\t << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B)\n#define BITS_HEAD_PKT_HIQ_V1_8822B                                             \\\n\t(BIT_MASK_HEAD_PKT_HIQ_V1_8822B << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B)\n#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8822B))\n#define BIT_GET_HEAD_PKT_HIQ_V1_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B) &                            \\\n\t BIT_MASK_HEAD_PKT_HIQ_V1_8822B)\n#define BIT_SET_HEAD_PKT_HIQ_V1_8822B(x, v)                                    \\\n\t(BIT_CLEAR_HEAD_PKT_HIQ_V1_8822B(x) | BIT_HEAD_PKT_HIQ_V1_8822B(v))\n\n/* 2 REG_BCNQ_INFO_8822B */\n\n#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B 0\n#define BIT_MASK_BCNQ_HEAD_PG_V1_8822B 0xfff\n#define BIT_BCNQ_HEAD_PG_V1_8822B(x)                                           \\\n\t(((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8822B)                                \\\n\t << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B)\n#define BITS_BCNQ_HEAD_PG_V1_8822B                                             \\\n\t(BIT_MASK_BCNQ_HEAD_PG_V1_8822B << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B)\n#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8822B(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8822B))\n#define BIT_GET_BCNQ_HEAD_PG_V1_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B) &                            \\\n\t BIT_MASK_BCNQ_HEAD_PG_V1_8822B)\n#define BIT_SET_BCNQ_HEAD_PG_V1_8822B(x, v)                                    \\\n\t(BIT_CLEAR_BCNQ_HEAD_PG_V1_8822B(x) | BIT_BCNQ_HEAD_PG_V1_8822B(v))\n\n/* 2 REG_TXPKT_EMPTY_8822B */\n#define BIT_BCNQ_EMPTY_8822B BIT(11)\n#define BIT_HQQ_EMPTY_8822B BIT(10)\n#define BIT_MQQ_EMPTY_8822B BIT(9)\n#define BIT_MGQ_CPU_EMPTY_8822B BIT(8)\n#define BIT_AC7Q_EMPTY_8822B BIT(7)\n#define BIT_AC6Q_EMPTY_8822B BIT(6)\n#define BIT_AC5Q_EMPTY_8822B BIT(5)\n#define BIT_AC4Q_EMPTY_8822B BIT(4)\n#define BIT_AC3Q_EMPTY_8822B BIT(3)\n#define BIT_AC2Q_EMPTY_8822B BIT(2)\n#define BIT_AC1Q_EMPTY_8822B BIT(1)\n#define BIT_AC0Q_EMPTY_8822B BIT(0)\n\n/* 2 REG_CPU_MGQ_INFO_8822B */\n#define BIT_BCN1_POLL_8822B BIT(30)\n#define BIT_CPUMGT_POLL_8822B BIT(29)\n#define BIT_BCN_POLL_8822B BIT(28)\n#define BIT_CPUMGQ_FW_NUM_V1_8822B BIT(12)\n\n#define BIT_SHIFT_FW_FREE_TAIL_V1_8822B 0\n#define BIT_MASK_FW_FREE_TAIL_V1_8822B 0xfff\n#define BIT_FW_FREE_TAIL_V1_8822B(x)                                           \\\n\t(((x) & BIT_MASK_FW_FREE_TAIL_V1_8822B)                                \\\n\t << BIT_SHIFT_FW_FREE_TAIL_V1_8822B)\n#define BITS_FW_FREE_TAIL_V1_8822B                                             \\\n\t(BIT_MASK_FW_FREE_TAIL_V1_8822B << BIT_SHIFT_FW_FREE_TAIL_V1_8822B)\n#define BIT_CLEAR_FW_FREE_TAIL_V1_8822B(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8822B))\n#define BIT_GET_FW_FREE_TAIL_V1_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8822B) &                            \\\n\t BIT_MASK_FW_FREE_TAIL_V1_8822B)\n#define BIT_SET_FW_FREE_TAIL_V1_8822B(x, v)                                    \\\n\t(BIT_CLEAR_FW_FREE_TAIL_V1_8822B(x) | BIT_FW_FREE_TAIL_V1_8822B(v))\n\n/* 2 REG_FWHW_TXQ_CTRL_8822B */\n#define BIT_RTS_LIMIT_IN_OFDM_8822B BIT(23)\n#define BIT_EN_BCNQ_DL_8822B BIT(22)\n#define BIT_EN_RD_RESP_NAV_BK_8822B BIT(21)\n#define BIT_EN_WR_FREE_TAIL_8822B BIT(20)\n\n#define BIT_SHIFT_EN_QUEUE_RPT_8822B 8\n#define BIT_MASK_EN_QUEUE_RPT_8822B 0xff\n#define BIT_EN_QUEUE_RPT_8822B(x)                                              \\\n\t(((x) & BIT_MASK_EN_QUEUE_RPT_8822B) << BIT_SHIFT_EN_QUEUE_RPT_8822B)\n#define BITS_EN_QUEUE_RPT_8822B                                                \\\n\t(BIT_MASK_EN_QUEUE_RPT_8822B << BIT_SHIFT_EN_QUEUE_RPT_8822B)\n#define BIT_CLEAR_EN_QUEUE_RPT_8822B(x) ((x) & (~BITS_EN_QUEUE_RPT_8822B))\n#define BIT_GET_EN_QUEUE_RPT_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_EN_QUEUE_RPT_8822B) & BIT_MASK_EN_QUEUE_RPT_8822B)\n#define BIT_SET_EN_QUEUE_RPT_8822B(x, v)                                       \\\n\t(BIT_CLEAR_EN_QUEUE_RPT_8822B(x) | BIT_EN_QUEUE_RPT_8822B(v))\n\n#define BIT_EN_RTY_BK_8822B BIT(7)\n#define BIT_EN_USE_INI_RAT_8822B BIT(6)\n#define BIT_EN_RTS_NAV_BK_8822B BIT(5)\n#define BIT_DIS_SSN_CHECK_8822B BIT(4)\n#define BIT_MACID_MATCH_RTS_8822B BIT(3)\n#define BIT_EN_BCN_TRXRPT_V1_8822B BIT(2)\n#define BIT_EN_FTMACKRPT_8822B BIT(1)\n#define BIT_EN_FTMRPT_8822B BIT(0)\n\n/* 2 REG_DATAFB_SEL_8822B */\n\n#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B 0\n#define BIT_MASK__R_DATA_FALLBACK_SEL_8822B 0x3\n#define BIT__R_DATA_FALLBACK_SEL_8822B(x)                                      \\\n\t(((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8822B)                           \\\n\t << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B)\n#define BITS__R_DATA_FALLBACK_SEL_8822B                                        \\\n\t(BIT_MASK__R_DATA_FALLBACK_SEL_8822B                                   \\\n\t << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B)\n#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8822B(x)                                \\\n\t((x) & (~BITS__R_DATA_FALLBACK_SEL_8822B))\n#define BIT_GET__R_DATA_FALLBACK_SEL_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B) &                       \\\n\t BIT_MASK__R_DATA_FALLBACK_SEL_8822B)\n#define BIT_SET__R_DATA_FALLBACK_SEL_8822B(x, v)                               \\\n\t(BIT_CLEAR__R_DATA_FALLBACK_SEL_8822B(x) |                             \\\n\t BIT__R_DATA_FALLBACK_SEL_8822B(v))\n\n/* 2 REG_BCNQ_BDNY_V1_8822B */\n\n#define BIT_SHIFT_BCNQ_PGBNDY_V1_8822B 0\n#define BIT_MASK_BCNQ_PGBNDY_V1_8822B 0xfff\n#define BIT_BCNQ_PGBNDY_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_BCNQ_PGBNDY_V1_8822B)                                 \\\n\t << BIT_SHIFT_BCNQ_PGBNDY_V1_8822B)\n#define BITS_BCNQ_PGBNDY_V1_8822B                                              \\\n\t(BIT_MASK_BCNQ_PGBNDY_V1_8822B << BIT_SHIFT_BCNQ_PGBNDY_V1_8822B)\n#define BIT_CLEAR_BCNQ_PGBNDY_V1_8822B(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8822B))\n#define BIT_GET_BCNQ_PGBNDY_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8822B) &                             \\\n\t BIT_MASK_BCNQ_PGBNDY_V1_8822B)\n#define BIT_SET_BCNQ_PGBNDY_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_BCNQ_PGBNDY_V1_8822B(x) | BIT_BCNQ_PGBNDY_V1_8822B(v))\n\n/* 2 REG_LIFETIME_EN_8822B */\n#define BIT_BT_INT_CPU_8822B BIT(7)\n#define BIT_BT_INT_PTA_8822B BIT(6)\n#define BIT_EN_CTRL_RTYBIT_8822B BIT(4)\n#define BIT_LIFETIME_BK_EN_8822B BIT(3)\n#define BIT_LIFETIME_BE_EN_8822B BIT(2)\n#define BIT_LIFETIME_VI_EN_8822B BIT(1)\n#define BIT_LIFETIME_VO_EN_8822B BIT(0)\n\n/* 2 REG_SPEC_SIFS_8822B */\n\n#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B 8\n#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B 0xff\n#define BIT_SPEC_SIFS_OFDM_PTCL_8822B(x)                                       \\\n\t(((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B)                            \\\n\t << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B)\n#define BITS_SPEC_SIFS_OFDM_PTCL_8822B                                         \\\n\t(BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B                                    \\\n\t << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B)\n#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822B(x)                                 \\\n\t((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8822B))\n#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B) &                        \\\n\t BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B)\n#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8822B(x, v)                                \\\n\t(BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822B(x) |                              \\\n\t BIT_SPEC_SIFS_OFDM_PTCL_8822B(v))\n\n#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B 0\n#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B 0xff\n#define BIT_SPEC_SIFS_CCK_PTCL_8822B(x)                                        \\\n\t(((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B)                             \\\n\t << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B)\n#define BITS_SPEC_SIFS_CCK_PTCL_8822B                                          \\\n\t(BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B                                     \\\n\t << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B)\n#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822B(x)                                  \\\n\t((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8822B))\n#define BIT_GET_SPEC_SIFS_CCK_PTCL_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B) &                         \\\n\t BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B)\n#define BIT_SET_SPEC_SIFS_CCK_PTCL_8822B(x, v)                                 \\\n\t(BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822B(x) |                               \\\n\t BIT_SPEC_SIFS_CCK_PTCL_8822B(v))\n\n/* 2 REG_RETRY_LIMIT_8822B */\n\n#define BIT_SHIFT_SRL_8822B 8\n#define BIT_MASK_SRL_8822B 0x3f\n#define BIT_SRL_8822B(x) (((x) & BIT_MASK_SRL_8822B) << BIT_SHIFT_SRL_8822B)\n#define BITS_SRL_8822B (BIT_MASK_SRL_8822B << BIT_SHIFT_SRL_8822B)\n#define BIT_CLEAR_SRL_8822B(x) ((x) & (~BITS_SRL_8822B))\n#define BIT_GET_SRL_8822B(x) (((x) >> BIT_SHIFT_SRL_8822B) & BIT_MASK_SRL_8822B)\n#define BIT_SET_SRL_8822B(x, v) (BIT_CLEAR_SRL_8822B(x) | BIT_SRL_8822B(v))\n\n#define BIT_SHIFT_LRL_8822B 0\n#define BIT_MASK_LRL_8822B 0x3f\n#define BIT_LRL_8822B(x) (((x) & BIT_MASK_LRL_8822B) << BIT_SHIFT_LRL_8822B)\n#define BITS_LRL_8822B (BIT_MASK_LRL_8822B << BIT_SHIFT_LRL_8822B)\n#define BIT_CLEAR_LRL_8822B(x) ((x) & (~BITS_LRL_8822B))\n#define BIT_GET_LRL_8822B(x) (((x) >> BIT_SHIFT_LRL_8822B) & BIT_MASK_LRL_8822B)\n#define BIT_SET_LRL_8822B(x, v) (BIT_CLEAR_LRL_8822B(x) | BIT_LRL_8822B(v))\n\n/* 2 REG_TXBF_CTRL_8822B */\n#define BIT_R_ENABLE_NDPA_8822B BIT(31)\n#define BIT_USE_NDPA_PARAMETER_8822B BIT(30)\n#define BIT_R_PROP_TXBF_8822B BIT(29)\n#define BIT_R_EN_NDPA_INT_8822B BIT(28)\n#define BIT_R_TXBF1_80M_8822B BIT(27)\n#define BIT_R_TXBF1_40M_8822B BIT(26)\n#define BIT_R_TXBF1_20M_8822B BIT(25)\n\n#define BIT_SHIFT_R_TXBF1_AID_8822B 16\n#define BIT_MASK_R_TXBF1_AID_8822B 0x1ff\n#define BIT_R_TXBF1_AID_8822B(x)                                               \\\n\t(((x) & BIT_MASK_R_TXBF1_AID_8822B) << BIT_SHIFT_R_TXBF1_AID_8822B)\n#define BITS_R_TXBF1_AID_8822B                                                 \\\n\t(BIT_MASK_R_TXBF1_AID_8822B << BIT_SHIFT_R_TXBF1_AID_8822B)\n#define BIT_CLEAR_R_TXBF1_AID_8822B(x) ((x) & (~BITS_R_TXBF1_AID_8822B))\n#define BIT_GET_R_TXBF1_AID_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_R_TXBF1_AID_8822B) & BIT_MASK_R_TXBF1_AID_8822B)\n#define BIT_SET_R_TXBF1_AID_8822B(x, v)                                        \\\n\t(BIT_CLEAR_R_TXBF1_AID_8822B(x) | BIT_R_TXBF1_AID_8822B(v))\n\n#define BIT_DIS_NDP_BFEN_8822B BIT(15)\n#define BIT_R_TXBCN_NOBLOCK_NDP_8822B BIT(14)\n#define BIT_R_TXBF0_80M_8822B BIT(11)\n#define BIT_R_TXBF0_40M_8822B BIT(10)\n#define BIT_R_TXBF0_20M_8822B BIT(9)\n\n#define BIT_SHIFT_R_TXBF0_AID_8822B 0\n#define BIT_MASK_R_TXBF0_AID_8822B 0x1ff\n#define BIT_R_TXBF0_AID_8822B(x)                                               \\\n\t(((x) & BIT_MASK_R_TXBF0_AID_8822B) << BIT_SHIFT_R_TXBF0_AID_8822B)\n#define BITS_R_TXBF0_AID_8822B                                                 \\\n\t(BIT_MASK_R_TXBF0_AID_8822B << BIT_SHIFT_R_TXBF0_AID_8822B)\n#define BIT_CLEAR_R_TXBF0_AID_8822B(x) ((x) & (~BITS_R_TXBF0_AID_8822B))\n#define BIT_GET_R_TXBF0_AID_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_R_TXBF0_AID_8822B) & BIT_MASK_R_TXBF0_AID_8822B)\n#define BIT_SET_R_TXBF0_AID_8822B(x, v)                                        \\\n\t(BIT_CLEAR_R_TXBF0_AID_8822B(x) | BIT_R_TXBF0_AID_8822B(v))\n\n/* 2 REG_DARFRC_8822B */\n\n#define BIT_SHIFT_DARF_RC8_8822B (56 & CPU_OPT_WIDTH)\n#define BIT_MASK_DARF_RC8_8822B 0x1f\n#define BIT_DARF_RC8_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_DARF_RC8_8822B) << BIT_SHIFT_DARF_RC8_8822B)\n#define BITS_DARF_RC8_8822B                                                    \\\n\t(BIT_MASK_DARF_RC8_8822B << BIT_SHIFT_DARF_RC8_8822B)\n#define BIT_CLEAR_DARF_RC8_8822B(x) ((x) & (~BITS_DARF_RC8_8822B))\n#define BIT_GET_DARF_RC8_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_DARF_RC8_8822B) & BIT_MASK_DARF_RC8_8822B)\n#define BIT_SET_DARF_RC8_8822B(x, v)                                           \\\n\t(BIT_CLEAR_DARF_RC8_8822B(x) | BIT_DARF_RC8_8822B(v))\n\n#define BIT_SHIFT_DARF_RC7_8822B (48 & CPU_OPT_WIDTH)\n#define BIT_MASK_DARF_RC7_8822B 0x1f\n#define BIT_DARF_RC7_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_DARF_RC7_8822B) << BIT_SHIFT_DARF_RC7_8822B)\n#define BITS_DARF_RC7_8822B                                                    \\\n\t(BIT_MASK_DARF_RC7_8822B << BIT_SHIFT_DARF_RC7_8822B)\n#define BIT_CLEAR_DARF_RC7_8822B(x) ((x) & (~BITS_DARF_RC7_8822B))\n#define BIT_GET_DARF_RC7_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_DARF_RC7_8822B) & BIT_MASK_DARF_RC7_8822B)\n#define BIT_SET_DARF_RC7_8822B(x, v)                                           \\\n\t(BIT_CLEAR_DARF_RC7_8822B(x) | BIT_DARF_RC7_8822B(v))\n\n#define BIT_SHIFT_DARF_RC6_8822B (40 & CPU_OPT_WIDTH)\n#define BIT_MASK_DARF_RC6_8822B 0x1f\n#define BIT_DARF_RC6_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_DARF_RC6_8822B) << BIT_SHIFT_DARF_RC6_8822B)\n#define BITS_DARF_RC6_8822B                                                    \\\n\t(BIT_MASK_DARF_RC6_8822B << BIT_SHIFT_DARF_RC6_8822B)\n#define BIT_CLEAR_DARF_RC6_8822B(x) ((x) & (~BITS_DARF_RC6_8822B))\n#define BIT_GET_DARF_RC6_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_DARF_RC6_8822B) & BIT_MASK_DARF_RC6_8822B)\n#define BIT_SET_DARF_RC6_8822B(x, v)                                           \\\n\t(BIT_CLEAR_DARF_RC6_8822B(x) | BIT_DARF_RC6_8822B(v))\n\n#define BIT_SHIFT_DARF_RC5_8822B (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_DARF_RC5_8822B 0x1f\n#define BIT_DARF_RC5_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_DARF_RC5_8822B) << BIT_SHIFT_DARF_RC5_8822B)\n#define BITS_DARF_RC5_8822B                                                    \\\n\t(BIT_MASK_DARF_RC5_8822B << BIT_SHIFT_DARF_RC5_8822B)\n#define BIT_CLEAR_DARF_RC5_8822B(x) ((x) & (~BITS_DARF_RC5_8822B))\n#define BIT_GET_DARF_RC5_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_DARF_RC5_8822B) & BIT_MASK_DARF_RC5_8822B)\n#define BIT_SET_DARF_RC5_8822B(x, v)                                           \\\n\t(BIT_CLEAR_DARF_RC5_8822B(x) | BIT_DARF_RC5_8822B(v))\n\n#define BIT_SHIFT_DARF_RC4_8822B 24\n#define BIT_MASK_DARF_RC4_8822B 0x1f\n#define BIT_DARF_RC4_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_DARF_RC4_8822B) << BIT_SHIFT_DARF_RC4_8822B)\n#define BITS_DARF_RC4_8822B                                                    \\\n\t(BIT_MASK_DARF_RC4_8822B << BIT_SHIFT_DARF_RC4_8822B)\n#define BIT_CLEAR_DARF_RC4_8822B(x) ((x) & (~BITS_DARF_RC4_8822B))\n#define BIT_GET_DARF_RC4_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_DARF_RC4_8822B) & BIT_MASK_DARF_RC4_8822B)\n#define BIT_SET_DARF_RC4_8822B(x, v)                                           \\\n\t(BIT_CLEAR_DARF_RC4_8822B(x) | BIT_DARF_RC4_8822B(v))\n\n#define BIT_SHIFT_DARF_RC3_8822B 16\n#define BIT_MASK_DARF_RC3_8822B 0x1f\n#define BIT_DARF_RC3_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_DARF_RC3_8822B) << BIT_SHIFT_DARF_RC3_8822B)\n#define BITS_DARF_RC3_8822B                                                    \\\n\t(BIT_MASK_DARF_RC3_8822B << BIT_SHIFT_DARF_RC3_8822B)\n#define BIT_CLEAR_DARF_RC3_8822B(x) ((x) & (~BITS_DARF_RC3_8822B))\n#define BIT_GET_DARF_RC3_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_DARF_RC3_8822B) & BIT_MASK_DARF_RC3_8822B)\n#define BIT_SET_DARF_RC3_8822B(x, v)                                           \\\n\t(BIT_CLEAR_DARF_RC3_8822B(x) | BIT_DARF_RC3_8822B(v))\n\n#define BIT_SHIFT_DARF_RC2_8822B 8\n#define BIT_MASK_DARF_RC2_8822B 0x1f\n#define BIT_DARF_RC2_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_DARF_RC2_8822B) << BIT_SHIFT_DARF_RC2_8822B)\n#define BITS_DARF_RC2_8822B                                                    \\\n\t(BIT_MASK_DARF_RC2_8822B << BIT_SHIFT_DARF_RC2_8822B)\n#define BIT_CLEAR_DARF_RC2_8822B(x) ((x) & (~BITS_DARF_RC2_8822B))\n#define BIT_GET_DARF_RC2_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_DARF_RC2_8822B) & BIT_MASK_DARF_RC2_8822B)\n#define BIT_SET_DARF_RC2_8822B(x, v)                                           \\\n\t(BIT_CLEAR_DARF_RC2_8822B(x) | BIT_DARF_RC2_8822B(v))\n\n#define BIT_SHIFT_DARF_RC1_8822B 0\n#define BIT_MASK_DARF_RC1_8822B 0x1f\n#define BIT_DARF_RC1_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_DARF_RC1_8822B) << BIT_SHIFT_DARF_RC1_8822B)\n#define BITS_DARF_RC1_8822B                                                    \\\n\t(BIT_MASK_DARF_RC1_8822B << BIT_SHIFT_DARF_RC1_8822B)\n#define BIT_CLEAR_DARF_RC1_8822B(x) ((x) & (~BITS_DARF_RC1_8822B))\n#define BIT_GET_DARF_RC1_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_DARF_RC1_8822B) & BIT_MASK_DARF_RC1_8822B)\n#define BIT_SET_DARF_RC1_8822B(x, v)                                           \\\n\t(BIT_CLEAR_DARF_RC1_8822B(x) | BIT_DARF_RC1_8822B(v))\n\n/* 2 REG_RARFRC_8822B */\n\n#define BIT_SHIFT_RARF_RC8_8822B (56 & CPU_OPT_WIDTH)\n#define BIT_MASK_RARF_RC8_8822B 0x1f\n#define BIT_RARF_RC8_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC8_8822B) << BIT_SHIFT_RARF_RC8_8822B)\n#define BITS_RARF_RC8_8822B                                                    \\\n\t(BIT_MASK_RARF_RC8_8822B << BIT_SHIFT_RARF_RC8_8822B)\n#define BIT_CLEAR_RARF_RC8_8822B(x) ((x) & (~BITS_RARF_RC8_8822B))\n#define BIT_GET_RARF_RC8_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC8_8822B) & BIT_MASK_RARF_RC8_8822B)\n#define BIT_SET_RARF_RC8_8822B(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC8_8822B(x) | BIT_RARF_RC8_8822B(v))\n\n#define BIT_SHIFT_RARF_RC7_8822B (48 & CPU_OPT_WIDTH)\n#define BIT_MASK_RARF_RC7_8822B 0x1f\n#define BIT_RARF_RC7_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC7_8822B) << BIT_SHIFT_RARF_RC7_8822B)\n#define BITS_RARF_RC7_8822B                                                    \\\n\t(BIT_MASK_RARF_RC7_8822B << BIT_SHIFT_RARF_RC7_8822B)\n#define BIT_CLEAR_RARF_RC7_8822B(x) ((x) & (~BITS_RARF_RC7_8822B))\n#define BIT_GET_RARF_RC7_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC7_8822B) & BIT_MASK_RARF_RC7_8822B)\n#define BIT_SET_RARF_RC7_8822B(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC7_8822B(x) | BIT_RARF_RC7_8822B(v))\n\n#define BIT_SHIFT_RARF_RC6_8822B (40 & CPU_OPT_WIDTH)\n#define BIT_MASK_RARF_RC6_8822B 0x1f\n#define BIT_RARF_RC6_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC6_8822B) << BIT_SHIFT_RARF_RC6_8822B)\n#define BITS_RARF_RC6_8822B                                                    \\\n\t(BIT_MASK_RARF_RC6_8822B << BIT_SHIFT_RARF_RC6_8822B)\n#define BIT_CLEAR_RARF_RC6_8822B(x) ((x) & (~BITS_RARF_RC6_8822B))\n#define BIT_GET_RARF_RC6_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC6_8822B) & BIT_MASK_RARF_RC6_8822B)\n#define BIT_SET_RARF_RC6_8822B(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC6_8822B(x) | BIT_RARF_RC6_8822B(v))\n\n#define BIT_SHIFT_RARF_RC5_8822B (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_RARF_RC5_8822B 0x1f\n#define BIT_RARF_RC5_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC5_8822B) << BIT_SHIFT_RARF_RC5_8822B)\n#define BITS_RARF_RC5_8822B                                                    \\\n\t(BIT_MASK_RARF_RC5_8822B << BIT_SHIFT_RARF_RC5_8822B)\n#define BIT_CLEAR_RARF_RC5_8822B(x) ((x) & (~BITS_RARF_RC5_8822B))\n#define BIT_GET_RARF_RC5_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC5_8822B) & BIT_MASK_RARF_RC5_8822B)\n#define BIT_SET_RARF_RC5_8822B(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC5_8822B(x) | BIT_RARF_RC5_8822B(v))\n\n#define BIT_SHIFT_RARF_RC4_8822B 24\n#define BIT_MASK_RARF_RC4_8822B 0x1f\n#define BIT_RARF_RC4_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC4_8822B) << BIT_SHIFT_RARF_RC4_8822B)\n#define BITS_RARF_RC4_8822B                                                    \\\n\t(BIT_MASK_RARF_RC4_8822B << BIT_SHIFT_RARF_RC4_8822B)\n#define BIT_CLEAR_RARF_RC4_8822B(x) ((x) & (~BITS_RARF_RC4_8822B))\n#define BIT_GET_RARF_RC4_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC4_8822B) & BIT_MASK_RARF_RC4_8822B)\n#define BIT_SET_RARF_RC4_8822B(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC4_8822B(x) | BIT_RARF_RC4_8822B(v))\n\n#define BIT_SHIFT_RARF_RC3_8822B 16\n#define BIT_MASK_RARF_RC3_8822B 0x1f\n#define BIT_RARF_RC3_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC3_8822B) << BIT_SHIFT_RARF_RC3_8822B)\n#define BITS_RARF_RC3_8822B                                                    \\\n\t(BIT_MASK_RARF_RC3_8822B << BIT_SHIFT_RARF_RC3_8822B)\n#define BIT_CLEAR_RARF_RC3_8822B(x) ((x) & (~BITS_RARF_RC3_8822B))\n#define BIT_GET_RARF_RC3_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC3_8822B) & BIT_MASK_RARF_RC3_8822B)\n#define BIT_SET_RARF_RC3_8822B(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC3_8822B(x) | BIT_RARF_RC3_8822B(v))\n\n#define BIT_SHIFT_RARF_RC2_8822B 8\n#define BIT_MASK_RARF_RC2_8822B 0x1f\n#define BIT_RARF_RC2_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC2_8822B) << BIT_SHIFT_RARF_RC2_8822B)\n#define BITS_RARF_RC2_8822B                                                    \\\n\t(BIT_MASK_RARF_RC2_8822B << BIT_SHIFT_RARF_RC2_8822B)\n#define BIT_CLEAR_RARF_RC2_8822B(x) ((x) & (~BITS_RARF_RC2_8822B))\n#define BIT_GET_RARF_RC2_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC2_8822B) & BIT_MASK_RARF_RC2_8822B)\n#define BIT_SET_RARF_RC2_8822B(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC2_8822B(x) | BIT_RARF_RC2_8822B(v))\n\n#define BIT_SHIFT_RARF_RC1_8822B 0\n#define BIT_MASK_RARF_RC1_8822B 0x1f\n#define BIT_RARF_RC1_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC1_8822B) << BIT_SHIFT_RARF_RC1_8822B)\n#define BITS_RARF_RC1_8822B                                                    \\\n\t(BIT_MASK_RARF_RC1_8822B << BIT_SHIFT_RARF_RC1_8822B)\n#define BIT_CLEAR_RARF_RC1_8822B(x) ((x) & (~BITS_RARF_RC1_8822B))\n#define BIT_GET_RARF_RC1_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC1_8822B) & BIT_MASK_RARF_RC1_8822B)\n#define BIT_SET_RARF_RC1_8822B(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC1_8822B(x) | BIT_RARF_RC1_8822B(v))\n\n/* 2 REG_RRSR_8822B */\n\n#define BIT_SHIFT_RRSR_RSC_8822B 21\n#define BIT_MASK_RRSR_RSC_8822B 0x3\n#define BIT_RRSR_RSC_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_RRSR_RSC_8822B) << BIT_SHIFT_RRSR_RSC_8822B)\n#define BITS_RRSR_RSC_8822B                                                    \\\n\t(BIT_MASK_RRSR_RSC_8822B << BIT_SHIFT_RRSR_RSC_8822B)\n#define BIT_CLEAR_RRSR_RSC_8822B(x) ((x) & (~BITS_RRSR_RSC_8822B))\n#define BIT_GET_RRSR_RSC_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RRSR_RSC_8822B) & BIT_MASK_RRSR_RSC_8822B)\n#define BIT_SET_RRSR_RSC_8822B(x, v)                                           \\\n\t(BIT_CLEAR_RRSR_RSC_8822B(x) | BIT_RRSR_RSC_8822B(v))\n\n#define BIT_RRSR_BW_8822B BIT(20)\n\n#define BIT_SHIFT_RRSC_BITMAP_8822B 0\n#define BIT_MASK_RRSC_BITMAP_8822B 0xfffff\n#define BIT_RRSC_BITMAP_8822B(x)                                               \\\n\t(((x) & BIT_MASK_RRSC_BITMAP_8822B) << BIT_SHIFT_RRSC_BITMAP_8822B)\n#define BITS_RRSC_BITMAP_8822B                                                 \\\n\t(BIT_MASK_RRSC_BITMAP_8822B << BIT_SHIFT_RRSC_BITMAP_8822B)\n#define BIT_CLEAR_RRSC_BITMAP_8822B(x) ((x) & (~BITS_RRSC_BITMAP_8822B))\n#define BIT_GET_RRSC_BITMAP_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_RRSC_BITMAP_8822B) & BIT_MASK_RRSC_BITMAP_8822B)\n#define BIT_SET_RRSC_BITMAP_8822B(x, v)                                        \\\n\t(BIT_CLEAR_RRSC_BITMAP_8822B(x) | BIT_RRSC_BITMAP_8822B(v))\n\n/* 2 REG_ARFR0_8822B */\n\n#define BIT_SHIFT_ARFR0_V1_8822B 0\n#define BIT_MASK_ARFR0_V1_8822B 0xffffffffffffffffL\n#define BIT_ARFR0_V1_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_ARFR0_V1_8822B) << BIT_SHIFT_ARFR0_V1_8822B)\n#define BITS_ARFR0_V1_8822B                                                    \\\n\t(BIT_MASK_ARFR0_V1_8822B << BIT_SHIFT_ARFR0_V1_8822B)\n#define BIT_CLEAR_ARFR0_V1_8822B(x) ((x) & (~BITS_ARFR0_V1_8822B))\n#define BIT_GET_ARFR0_V1_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_ARFR0_V1_8822B) & BIT_MASK_ARFR0_V1_8822B)\n#define BIT_SET_ARFR0_V1_8822B(x, v)                                           \\\n\t(BIT_CLEAR_ARFR0_V1_8822B(x) | BIT_ARFR0_V1_8822B(v))\n\n/* 2 REG_ARFR1_V1_8822B */\n\n#define BIT_SHIFT_ARFR1_V1_8822B 0\n#define BIT_MASK_ARFR1_V1_8822B 0xffffffffffffffffL\n#define BIT_ARFR1_V1_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_ARFR1_V1_8822B) << BIT_SHIFT_ARFR1_V1_8822B)\n#define BITS_ARFR1_V1_8822B                                                    \\\n\t(BIT_MASK_ARFR1_V1_8822B << BIT_SHIFT_ARFR1_V1_8822B)\n#define BIT_CLEAR_ARFR1_V1_8822B(x) ((x) & (~BITS_ARFR1_V1_8822B))\n#define BIT_GET_ARFR1_V1_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_ARFR1_V1_8822B) & BIT_MASK_ARFR1_V1_8822B)\n#define BIT_SET_ARFR1_V1_8822B(x, v)                                           \\\n\t(BIT_CLEAR_ARFR1_V1_8822B(x) | BIT_ARFR1_V1_8822B(v))\n\n/* 2 REG_CCK_CHECK_8822B */\n#define BIT_CHECK_CCK_EN_8822B BIT(7)\n#define BIT_EN_BCN_PKT_REL_8822B BIT(6)\n#define BIT_BCN_PORT_SEL_8822B BIT(5)\n#define BIT_MOREDATA_BYPASS_8822B BIT(4)\n#define BIT_EN_CLR_CMD_REL_BCN_PKT_8822B BIT(3)\n#define BIT_R_EN_SET_MOREDATA_8822B BIT(2)\n#define BIT__R_DIS_CLEAR_MACID_RELEASE_8822B BIT(1)\n#define BIT__R_MACID_RELEASE_EN_8822B BIT(0)\n\n/* 2 REG_AMPDU_MAX_TIME_V1_8822B */\n\n#define BIT_SHIFT_AMPDU_MAX_TIME_8822B 0\n#define BIT_MASK_AMPDU_MAX_TIME_8822B 0xff\n#define BIT_AMPDU_MAX_TIME_8822B(x)                                            \\\n\t(((x) & BIT_MASK_AMPDU_MAX_TIME_8822B)                                 \\\n\t << BIT_SHIFT_AMPDU_MAX_TIME_8822B)\n#define BITS_AMPDU_MAX_TIME_8822B                                              \\\n\t(BIT_MASK_AMPDU_MAX_TIME_8822B << BIT_SHIFT_AMPDU_MAX_TIME_8822B)\n#define BIT_CLEAR_AMPDU_MAX_TIME_8822B(x) ((x) & (~BITS_AMPDU_MAX_TIME_8822B))\n#define BIT_GET_AMPDU_MAX_TIME_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8822B) &                             \\\n\t BIT_MASK_AMPDU_MAX_TIME_8822B)\n#define BIT_SET_AMPDU_MAX_TIME_8822B(x, v)                                     \\\n\t(BIT_CLEAR_AMPDU_MAX_TIME_8822B(x) | BIT_AMPDU_MAX_TIME_8822B(v))\n\n/* 2 REG_BCNQ1_BDNY_V1_8822B */\n\n#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B 0\n#define BIT_MASK_BCNQ1_PGBNDY_V1_8822B 0xfff\n#define BIT_BCNQ1_PGBNDY_V1_8822B(x)                                           \\\n\t(((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8822B)                                \\\n\t << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B)\n#define BITS_BCNQ1_PGBNDY_V1_8822B                                             \\\n\t(BIT_MASK_BCNQ1_PGBNDY_V1_8822B << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B)\n#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8822B(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8822B))\n#define BIT_GET_BCNQ1_PGBNDY_V1_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B) &                            \\\n\t BIT_MASK_BCNQ1_PGBNDY_V1_8822B)\n#define BIT_SET_BCNQ1_PGBNDY_V1_8822B(x, v)                                    \\\n\t(BIT_CLEAR_BCNQ1_PGBNDY_V1_8822B(x) | BIT_BCNQ1_PGBNDY_V1_8822B(v))\n\n/* 2 REG_AMPDU_MAX_LENGTH_8822B */\n\n#define BIT_SHIFT_AMPDU_MAX_LENGTH_8822B 0\n#define BIT_MASK_AMPDU_MAX_LENGTH_8822B 0xffffffffL\n#define BIT_AMPDU_MAX_LENGTH_8822B(x)                                          \\\n\t(((x) & BIT_MASK_AMPDU_MAX_LENGTH_8822B)                               \\\n\t << BIT_SHIFT_AMPDU_MAX_LENGTH_8822B)\n#define BITS_AMPDU_MAX_LENGTH_8822B                                            \\\n\t(BIT_MASK_AMPDU_MAX_LENGTH_8822B << BIT_SHIFT_AMPDU_MAX_LENGTH_8822B)\n#define BIT_CLEAR_AMPDU_MAX_LENGTH_8822B(x)                                    \\\n\t((x) & (~BITS_AMPDU_MAX_LENGTH_8822B))\n#define BIT_GET_AMPDU_MAX_LENGTH_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8822B) &                           \\\n\t BIT_MASK_AMPDU_MAX_LENGTH_8822B)\n#define BIT_SET_AMPDU_MAX_LENGTH_8822B(x, v)                                   \\\n\t(BIT_CLEAR_AMPDU_MAX_LENGTH_8822B(x) | BIT_AMPDU_MAX_LENGTH_8822B(v))\n\n/* 2 REG_ACQ_STOP_8822B */\n#define BIT_AC7Q_STOP_8822B BIT(7)\n#define BIT_AC6Q_STOP_8822B BIT(6)\n#define BIT_AC5Q_STOP_8822B BIT(5)\n#define BIT_AC4Q_STOP_8822B BIT(4)\n#define BIT_AC3Q_STOP_8822B BIT(3)\n#define BIT_AC2Q_STOP_8822B BIT(2)\n#define BIT_AC1Q_STOP_8822B BIT(1)\n#define BIT_AC0Q_STOP_8822B BIT(0)\n\n/* 2 REG_NDPA_RATE_8822B */\n\n#define BIT_SHIFT_R_NDPA_RATE_V1_8822B 0\n#define BIT_MASK_R_NDPA_RATE_V1_8822B 0xff\n#define BIT_R_NDPA_RATE_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_R_NDPA_RATE_V1_8822B)                                 \\\n\t << BIT_SHIFT_R_NDPA_RATE_V1_8822B)\n#define BITS_R_NDPA_RATE_V1_8822B                                              \\\n\t(BIT_MASK_R_NDPA_RATE_V1_8822B << BIT_SHIFT_R_NDPA_RATE_V1_8822B)\n#define BIT_CLEAR_R_NDPA_RATE_V1_8822B(x) ((x) & (~BITS_R_NDPA_RATE_V1_8822B))\n#define BIT_GET_R_NDPA_RATE_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8822B) &                             \\\n\t BIT_MASK_R_NDPA_RATE_V1_8822B)\n#define BIT_SET_R_NDPA_RATE_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_R_NDPA_RATE_V1_8822B(x) | BIT_R_NDPA_RATE_V1_8822B(v))\n\n/* 2 REG_TX_HANG_CTRL_8822B */\n#define BIT_R_EN_GNT_BT_AWAKE_8822B BIT(3)\n#define BIT_EN_EOF_V1_8822B BIT(2)\n#define BIT_DIS_OQT_BLOCK_8822B BIT(1)\n#define BIT_SEARCH_QUEUE_EN_8822B BIT(0)\n\n/* 2 REG_NDPA_OPT_CTRL_8822B */\n#define BIT_R_DIS_MACID_RELEASE_RTY_8822B BIT(5)\n\n#define BIT_SHIFT_BW_SIGTA_8822B 3\n#define BIT_MASK_BW_SIGTA_8822B 0x3\n#define BIT_BW_SIGTA_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_BW_SIGTA_8822B) << BIT_SHIFT_BW_SIGTA_8822B)\n#define BITS_BW_SIGTA_8822B                                                    \\\n\t(BIT_MASK_BW_SIGTA_8822B << BIT_SHIFT_BW_SIGTA_8822B)\n#define BIT_CLEAR_BW_SIGTA_8822B(x) ((x) & (~BITS_BW_SIGTA_8822B))\n#define BIT_GET_BW_SIGTA_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_BW_SIGTA_8822B) & BIT_MASK_BW_SIGTA_8822B)\n#define BIT_SET_BW_SIGTA_8822B(x, v)                                           \\\n\t(BIT_CLEAR_BW_SIGTA_8822B(x) | BIT_BW_SIGTA_8822B(v))\n\n#define BIT_EN_BAR_SIGTA_8822B BIT(2)\n\n#define BIT_SHIFT_R_NDPA_BW_8822B 0\n#define BIT_MASK_R_NDPA_BW_8822B 0x3\n#define BIT_R_NDPA_BW_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_R_NDPA_BW_8822B) << BIT_SHIFT_R_NDPA_BW_8822B)\n#define BITS_R_NDPA_BW_8822B                                                   \\\n\t(BIT_MASK_R_NDPA_BW_8822B << BIT_SHIFT_R_NDPA_BW_8822B)\n#define BIT_CLEAR_R_NDPA_BW_8822B(x) ((x) & (~BITS_R_NDPA_BW_8822B))\n#define BIT_GET_R_NDPA_BW_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_R_NDPA_BW_8822B) & BIT_MASK_R_NDPA_BW_8822B)\n#define BIT_SET_R_NDPA_BW_8822B(x, v)                                          \\\n\t(BIT_CLEAR_R_NDPA_BW_8822B(x) | BIT_R_NDPA_BW_8822B(v))\n\n/* 2 REG_RD_RESP_PKT_TH_8822B */\n\n#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B 0\n#define BIT_MASK_RD_RESP_PKT_TH_V1_8822B 0x3f\n#define BIT_RD_RESP_PKT_TH_V1_8822B(x)                                         \\\n\t(((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8822B)                              \\\n\t << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B)\n#define BITS_RD_RESP_PKT_TH_V1_8822B                                           \\\n\t(BIT_MASK_RD_RESP_PKT_TH_V1_8822B << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B)\n#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8822B(x)                                   \\\n\t((x) & (~BITS_RD_RESP_PKT_TH_V1_8822B))\n#define BIT_GET_RD_RESP_PKT_TH_V1_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B) &                          \\\n\t BIT_MASK_RD_RESP_PKT_TH_V1_8822B)\n#define BIT_SET_RD_RESP_PKT_TH_V1_8822B(x, v)                                  \\\n\t(BIT_CLEAR_RD_RESP_PKT_TH_V1_8822B(x) | BIT_RD_RESP_PKT_TH_V1_8822B(v))\n\n/* 2 REG_CMDQ_INFO_8822B */\n\n#define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B 25\n#define BIT_MASK_QUEUEMACID_CMDQ_V1_8822B 0x7f\n#define BIT_QUEUEMACID_CMDQ_V1_8822B(x)                                        \\\n\t(((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822B)                             \\\n\t << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B)\n#define BITS_QUEUEMACID_CMDQ_V1_8822B                                          \\\n\t(BIT_MASK_QUEUEMACID_CMDQ_V1_8822B                                     \\\n\t << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B)\n#define BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822B(x)                                  \\\n\t((x) & (~BITS_QUEUEMACID_CMDQ_V1_8822B))\n#define BIT_GET_QUEUEMACID_CMDQ_V1_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B) &                         \\\n\t BIT_MASK_QUEUEMACID_CMDQ_V1_8822B)\n#define BIT_SET_QUEUEMACID_CMDQ_V1_8822B(x, v)                                 \\\n\t(BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822B(x) |                               \\\n\t BIT_QUEUEMACID_CMDQ_V1_8822B(v))\n\n#define BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B 23\n#define BIT_MASK_QUEUEAC_CMDQ_V1_8822B 0x3\n#define BIT_QUEUEAC_CMDQ_V1_8822B(x)                                           \\\n\t(((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8822B)                                \\\n\t << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B)\n#define BITS_QUEUEAC_CMDQ_V1_8822B                                             \\\n\t(BIT_MASK_QUEUEAC_CMDQ_V1_8822B << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B)\n#define BIT_CLEAR_QUEUEAC_CMDQ_V1_8822B(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1_8822B))\n#define BIT_GET_QUEUEAC_CMDQ_V1_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B) &                            \\\n\t BIT_MASK_QUEUEAC_CMDQ_V1_8822B)\n#define BIT_SET_QUEUEAC_CMDQ_V1_8822B(x, v)                                    \\\n\t(BIT_CLEAR_QUEUEAC_CMDQ_V1_8822B(x) | BIT_QUEUEAC_CMDQ_V1_8822B(v))\n\n#define BIT_TIDEMPTY_CMDQ_V1_8822B BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B 11\n#define BIT_MASK_TAIL_PKT_CMDQ_V2_8822B 0x7ff\n#define BIT_TAIL_PKT_CMDQ_V2_8822B(x)                                          \\\n\t(((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8822B)                               \\\n\t << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B)\n#define BITS_TAIL_PKT_CMDQ_V2_8822B                                            \\\n\t(BIT_MASK_TAIL_PKT_CMDQ_V2_8822B << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B)\n#define BIT_CLEAR_TAIL_PKT_CMDQ_V2_8822B(x)                                    \\\n\t((x) & (~BITS_TAIL_PKT_CMDQ_V2_8822B))\n#define BIT_GET_TAIL_PKT_CMDQ_V2_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B) &                           \\\n\t BIT_MASK_TAIL_PKT_CMDQ_V2_8822B)\n#define BIT_SET_TAIL_PKT_CMDQ_V2_8822B(x, v)                                   \\\n\t(BIT_CLEAR_TAIL_PKT_CMDQ_V2_8822B(x) | BIT_TAIL_PKT_CMDQ_V2_8822B(v))\n\n#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B 0\n#define BIT_MASK_HEAD_PKT_CMDQ_V1_8822B 0x7ff\n#define BIT_HEAD_PKT_CMDQ_V1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822B)                               \\\n\t << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B)\n#define BITS_HEAD_PKT_CMDQ_V1_8822B                                            \\\n\t(BIT_MASK_HEAD_PKT_CMDQ_V1_8822B << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B)\n#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822B(x)                                    \\\n\t((x) & (~BITS_HEAD_PKT_CMDQ_V1_8822B))\n#define BIT_GET_HEAD_PKT_CMDQ_V1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B) &                           \\\n\t BIT_MASK_HEAD_PKT_CMDQ_V1_8822B)\n#define BIT_SET_HEAD_PKT_CMDQ_V1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822B(x) | BIT_HEAD_PKT_CMDQ_V1_8822B(v))\n\n/* 2 REG_Q4_INFO_8822B */\n\n#define BIT_SHIFT_QUEUEMACID_Q4_V1_8822B 25\n#define BIT_MASK_QUEUEMACID_Q4_V1_8822B 0x7f\n#define BIT_QUEUEMACID_Q4_V1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q4_V1_8822B)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q4_V1_8822B)\n#define BITS_QUEUEMACID_Q4_V1_8822B                                            \\\n\t(BIT_MASK_QUEUEMACID_Q4_V1_8822B << BIT_SHIFT_QUEUEMACID_Q4_V1_8822B)\n#define BIT_CLEAR_QUEUEMACID_Q4_V1_8822B(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q4_V1_8822B))\n#define BIT_GET_QUEUEMACID_Q4_V1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8822B) &                           \\\n\t BIT_MASK_QUEUEMACID_Q4_V1_8822B)\n#define BIT_SET_QUEUEMACID_Q4_V1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q4_V1_8822B(x) | BIT_QUEUEMACID_Q4_V1_8822B(v))\n\n#define BIT_SHIFT_QUEUEAC_Q4_V1_8822B 23\n#define BIT_MASK_QUEUEAC_Q4_V1_8822B 0x3\n#define BIT_QUEUEAC_Q4_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q4_V1_8822B) << BIT_SHIFT_QUEUEAC_Q4_V1_8822B)\n#define BITS_QUEUEAC_Q4_V1_8822B                                               \\\n\t(BIT_MASK_QUEUEAC_Q4_V1_8822B << BIT_SHIFT_QUEUEAC_Q4_V1_8822B)\n#define BIT_CLEAR_QUEUEAC_Q4_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8822B))\n#define BIT_GET_QUEUEAC_Q4_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8822B) & BIT_MASK_QUEUEAC_Q4_V1_8822B)\n#define BIT_SET_QUEUEAC_Q4_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q4_V1_8822B(x) | BIT_QUEUEAC_Q4_V1_8822B(v))\n\n#define BIT_TIDEMPTY_Q4_V1_8822B BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q4_V2_8822B 11\n#define BIT_MASK_TAIL_PKT_Q4_V2_8822B 0x7ff\n#define BIT_TAIL_PKT_Q4_V2_8822B(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822B)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q4_V2_8822B)\n#define BITS_TAIL_PKT_Q4_V2_8822B                                              \\\n\t(BIT_MASK_TAIL_PKT_Q4_V2_8822B << BIT_SHIFT_TAIL_PKT_Q4_V2_8822B)\n#define BIT_CLEAR_TAIL_PKT_Q4_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8822B))\n#define BIT_GET_TAIL_PKT_Q4_V2_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822B) &                             \\\n\t BIT_MASK_TAIL_PKT_Q4_V2_8822B)\n#define BIT_SET_TAIL_PKT_Q4_V2_8822B(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q4_V2_8822B(x) | BIT_TAIL_PKT_Q4_V2_8822B(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q4_V1_8822B 0\n#define BIT_MASK_HEAD_PKT_Q4_V1_8822B 0x7ff\n#define BIT_HEAD_PKT_Q4_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q4_V1_8822B)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q4_V1_8822B)\n#define BITS_HEAD_PKT_Q4_V1_8822B                                              \\\n\t(BIT_MASK_HEAD_PKT_Q4_V1_8822B << BIT_SHIFT_HEAD_PKT_Q4_V1_8822B)\n#define BIT_CLEAR_HEAD_PKT_Q4_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8822B))\n#define BIT_GET_HEAD_PKT_Q4_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8822B) &                             \\\n\t BIT_MASK_HEAD_PKT_Q4_V1_8822B)\n#define BIT_SET_HEAD_PKT_Q4_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q4_V1_8822B(x) | BIT_HEAD_PKT_Q4_V1_8822B(v))\n\n/* 2 REG_Q5_INFO_8822B */\n\n#define BIT_SHIFT_QUEUEMACID_Q5_V1_8822B 25\n#define BIT_MASK_QUEUEMACID_Q5_V1_8822B 0x7f\n#define BIT_QUEUEMACID_Q5_V1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q5_V1_8822B)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q5_V1_8822B)\n#define BITS_QUEUEMACID_Q5_V1_8822B                                            \\\n\t(BIT_MASK_QUEUEMACID_Q5_V1_8822B << BIT_SHIFT_QUEUEMACID_Q5_V1_8822B)\n#define BIT_CLEAR_QUEUEMACID_Q5_V1_8822B(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q5_V1_8822B))\n#define BIT_GET_QUEUEMACID_Q5_V1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8822B) &                           \\\n\t BIT_MASK_QUEUEMACID_Q5_V1_8822B)\n#define BIT_SET_QUEUEMACID_Q5_V1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q5_V1_8822B(x) | BIT_QUEUEMACID_Q5_V1_8822B(v))\n\n#define BIT_SHIFT_QUEUEAC_Q5_V1_8822B 23\n#define BIT_MASK_QUEUEAC_Q5_V1_8822B 0x3\n#define BIT_QUEUEAC_Q5_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q5_V1_8822B) << BIT_SHIFT_QUEUEAC_Q5_V1_8822B)\n#define BITS_QUEUEAC_Q5_V1_8822B                                               \\\n\t(BIT_MASK_QUEUEAC_Q5_V1_8822B << BIT_SHIFT_QUEUEAC_Q5_V1_8822B)\n#define BIT_CLEAR_QUEUEAC_Q5_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8822B))\n#define BIT_GET_QUEUEAC_Q5_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8822B) & BIT_MASK_QUEUEAC_Q5_V1_8822B)\n#define BIT_SET_QUEUEAC_Q5_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q5_V1_8822B(x) | BIT_QUEUEAC_Q5_V1_8822B(v))\n\n#define BIT_TIDEMPTY_Q5_V1_8822B BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q5_V2_8822B 11\n#define BIT_MASK_TAIL_PKT_Q5_V2_8822B 0x7ff\n#define BIT_TAIL_PKT_Q5_V2_8822B(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q5_V2_8822B)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q5_V2_8822B)\n#define BITS_TAIL_PKT_Q5_V2_8822B                                              \\\n\t(BIT_MASK_TAIL_PKT_Q5_V2_8822B << BIT_SHIFT_TAIL_PKT_Q5_V2_8822B)\n#define BIT_CLEAR_TAIL_PKT_Q5_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8822B))\n#define BIT_GET_TAIL_PKT_Q5_V2_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8822B) &                             \\\n\t BIT_MASK_TAIL_PKT_Q5_V2_8822B)\n#define BIT_SET_TAIL_PKT_Q5_V2_8822B(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q5_V2_8822B(x) | BIT_TAIL_PKT_Q5_V2_8822B(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q5_V1_8822B 0\n#define BIT_MASK_HEAD_PKT_Q5_V1_8822B 0x7ff\n#define BIT_HEAD_PKT_Q5_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q5_V1_8822B)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q5_V1_8822B)\n#define BITS_HEAD_PKT_Q5_V1_8822B                                              \\\n\t(BIT_MASK_HEAD_PKT_Q5_V1_8822B << BIT_SHIFT_HEAD_PKT_Q5_V1_8822B)\n#define BIT_CLEAR_HEAD_PKT_Q5_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8822B))\n#define BIT_GET_HEAD_PKT_Q5_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8822B) &                             \\\n\t BIT_MASK_HEAD_PKT_Q5_V1_8822B)\n#define BIT_SET_HEAD_PKT_Q5_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q5_V1_8822B(x) | BIT_HEAD_PKT_Q5_V1_8822B(v))\n\n/* 2 REG_Q6_INFO_8822B */\n\n#define BIT_SHIFT_QUEUEMACID_Q6_V1_8822B 25\n#define BIT_MASK_QUEUEMACID_Q6_V1_8822B 0x7f\n#define BIT_QUEUEMACID_Q6_V1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q6_V1_8822B)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q6_V1_8822B)\n#define BITS_QUEUEMACID_Q6_V1_8822B                                            \\\n\t(BIT_MASK_QUEUEMACID_Q6_V1_8822B << BIT_SHIFT_QUEUEMACID_Q6_V1_8822B)\n#define BIT_CLEAR_QUEUEMACID_Q6_V1_8822B(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q6_V1_8822B))\n#define BIT_GET_QUEUEMACID_Q6_V1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8822B) &                           \\\n\t BIT_MASK_QUEUEMACID_Q6_V1_8822B)\n#define BIT_SET_QUEUEMACID_Q6_V1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q6_V1_8822B(x) | BIT_QUEUEMACID_Q6_V1_8822B(v))\n\n#define BIT_SHIFT_QUEUEAC_Q6_V1_8822B 23\n#define BIT_MASK_QUEUEAC_Q6_V1_8822B 0x3\n#define BIT_QUEUEAC_Q6_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q6_V1_8822B) << BIT_SHIFT_QUEUEAC_Q6_V1_8822B)\n#define BITS_QUEUEAC_Q6_V1_8822B                                               \\\n\t(BIT_MASK_QUEUEAC_Q6_V1_8822B << BIT_SHIFT_QUEUEAC_Q6_V1_8822B)\n#define BIT_CLEAR_QUEUEAC_Q6_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8822B))\n#define BIT_GET_QUEUEAC_Q6_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8822B) & BIT_MASK_QUEUEAC_Q6_V1_8822B)\n#define BIT_SET_QUEUEAC_Q6_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q6_V1_8822B(x) | BIT_QUEUEAC_Q6_V1_8822B(v))\n\n#define BIT_TIDEMPTY_Q6_V1_8822B BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q6_V2_8822B 11\n#define BIT_MASK_TAIL_PKT_Q6_V2_8822B 0x7ff\n#define BIT_TAIL_PKT_Q6_V2_8822B(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q6_V2_8822B)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q6_V2_8822B)\n#define BITS_TAIL_PKT_Q6_V2_8822B                                              \\\n\t(BIT_MASK_TAIL_PKT_Q6_V2_8822B << BIT_SHIFT_TAIL_PKT_Q6_V2_8822B)\n#define BIT_CLEAR_TAIL_PKT_Q6_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8822B))\n#define BIT_GET_TAIL_PKT_Q6_V2_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8822B) &                             \\\n\t BIT_MASK_TAIL_PKT_Q6_V2_8822B)\n#define BIT_SET_TAIL_PKT_Q6_V2_8822B(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q6_V2_8822B(x) | BIT_TAIL_PKT_Q6_V2_8822B(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q6_V1_8822B 0\n#define BIT_MASK_HEAD_PKT_Q6_V1_8822B 0x7ff\n#define BIT_HEAD_PKT_Q6_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q6_V1_8822B)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q6_V1_8822B)\n#define BITS_HEAD_PKT_Q6_V1_8822B                                              \\\n\t(BIT_MASK_HEAD_PKT_Q6_V1_8822B << BIT_SHIFT_HEAD_PKT_Q6_V1_8822B)\n#define BIT_CLEAR_HEAD_PKT_Q6_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8822B))\n#define BIT_GET_HEAD_PKT_Q6_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8822B) &                             \\\n\t BIT_MASK_HEAD_PKT_Q6_V1_8822B)\n#define BIT_SET_HEAD_PKT_Q6_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q6_V1_8822B(x) | BIT_HEAD_PKT_Q6_V1_8822B(v))\n\n/* 2 REG_Q7_INFO_8822B */\n\n#define BIT_SHIFT_QUEUEMACID_Q7_V1_8822B 25\n#define BIT_MASK_QUEUEMACID_Q7_V1_8822B 0x7f\n#define BIT_QUEUEMACID_Q7_V1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q7_V1_8822B)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q7_V1_8822B)\n#define BITS_QUEUEMACID_Q7_V1_8822B                                            \\\n\t(BIT_MASK_QUEUEMACID_Q7_V1_8822B << BIT_SHIFT_QUEUEMACID_Q7_V1_8822B)\n#define BIT_CLEAR_QUEUEMACID_Q7_V1_8822B(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q7_V1_8822B))\n#define BIT_GET_QUEUEMACID_Q7_V1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8822B) &                           \\\n\t BIT_MASK_QUEUEMACID_Q7_V1_8822B)\n#define BIT_SET_QUEUEMACID_Q7_V1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q7_V1_8822B(x) | BIT_QUEUEMACID_Q7_V1_8822B(v))\n\n#define BIT_SHIFT_QUEUEAC_Q7_V1_8822B 23\n#define BIT_MASK_QUEUEAC_Q7_V1_8822B 0x3\n#define BIT_QUEUEAC_Q7_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q7_V1_8822B) << BIT_SHIFT_QUEUEAC_Q7_V1_8822B)\n#define BITS_QUEUEAC_Q7_V1_8822B                                               \\\n\t(BIT_MASK_QUEUEAC_Q7_V1_8822B << BIT_SHIFT_QUEUEAC_Q7_V1_8822B)\n#define BIT_CLEAR_QUEUEAC_Q7_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8822B))\n#define BIT_GET_QUEUEAC_Q7_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8822B) & BIT_MASK_QUEUEAC_Q7_V1_8822B)\n#define BIT_SET_QUEUEAC_Q7_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q7_V1_8822B(x) | BIT_QUEUEAC_Q7_V1_8822B(v))\n\n#define BIT_TIDEMPTY_Q7_V1_8822B BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q7_V2_8822B 11\n#define BIT_MASK_TAIL_PKT_Q7_V2_8822B 0x7ff\n#define BIT_TAIL_PKT_Q7_V2_8822B(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q7_V2_8822B)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q7_V2_8822B)\n#define BITS_TAIL_PKT_Q7_V2_8822B                                              \\\n\t(BIT_MASK_TAIL_PKT_Q7_V2_8822B << BIT_SHIFT_TAIL_PKT_Q7_V2_8822B)\n#define BIT_CLEAR_TAIL_PKT_Q7_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8822B))\n#define BIT_GET_TAIL_PKT_Q7_V2_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8822B) &                             \\\n\t BIT_MASK_TAIL_PKT_Q7_V2_8822B)\n#define BIT_SET_TAIL_PKT_Q7_V2_8822B(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q7_V2_8822B(x) | BIT_TAIL_PKT_Q7_V2_8822B(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q7_V1_8822B 0\n#define BIT_MASK_HEAD_PKT_Q7_V1_8822B 0x7ff\n#define BIT_HEAD_PKT_Q7_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q7_V1_8822B)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q7_V1_8822B)\n#define BITS_HEAD_PKT_Q7_V1_8822B                                              \\\n\t(BIT_MASK_HEAD_PKT_Q7_V1_8822B << BIT_SHIFT_HEAD_PKT_Q7_V1_8822B)\n#define BIT_CLEAR_HEAD_PKT_Q7_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8822B))\n#define BIT_GET_HEAD_PKT_Q7_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8822B) &                             \\\n\t BIT_MASK_HEAD_PKT_Q7_V1_8822B)\n#define BIT_SET_HEAD_PKT_Q7_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q7_V1_8822B(x) | BIT_HEAD_PKT_Q7_V1_8822B(v))\n\n/* 2 REG_WMAC_LBK_BUF_HD_V1_8822B */\n\n#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B 0\n#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B 0xfff\n#define BIT_WMAC_LBK_BUF_HEAD_V1_8822B(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B)                           \\\n\t << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B)\n#define BITS_WMAC_LBK_BUF_HEAD_V1_8822B                                        \\\n\t(BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B                                   \\\n\t << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B)\n#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822B(x)                                \\\n\t((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8822B))\n#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B) &                       \\\n\t BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B)\n#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8822B(x, v)                               \\\n\t(BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822B(x) |                             \\\n\t BIT_WMAC_LBK_BUF_HEAD_V1_8822B(v))\n\n/* 2 REG_MGQ_BDNY_V1_8822B */\n\n#define BIT_SHIFT_MGQ_PGBNDY_V1_8822B 0\n#define BIT_MASK_MGQ_PGBNDY_V1_8822B 0xfff\n#define BIT_MGQ_PGBNDY_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_PGBNDY_V1_8822B) << BIT_SHIFT_MGQ_PGBNDY_V1_8822B)\n#define BITS_MGQ_PGBNDY_V1_8822B                                               \\\n\t(BIT_MASK_MGQ_PGBNDY_V1_8822B << BIT_SHIFT_MGQ_PGBNDY_V1_8822B)\n#define BIT_CLEAR_MGQ_PGBNDY_V1_8822B(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8822B))\n#define BIT_GET_MGQ_PGBNDY_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8822B) & BIT_MASK_MGQ_PGBNDY_V1_8822B)\n#define BIT_SET_MGQ_PGBNDY_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_PGBNDY_V1_8822B(x) | BIT_MGQ_PGBNDY_V1_8822B(v))\n\n/* 2 REG_TXRPT_CTRL_8822B */\n\n#define BIT_SHIFT_TRXRPT_TIMER_TH_8822B 24\n#define BIT_MASK_TRXRPT_TIMER_TH_8822B 0xff\n#define BIT_TRXRPT_TIMER_TH_8822B(x)                                           \\\n\t(((x) & BIT_MASK_TRXRPT_TIMER_TH_8822B)                                \\\n\t << BIT_SHIFT_TRXRPT_TIMER_TH_8822B)\n#define BITS_TRXRPT_TIMER_TH_8822B                                             \\\n\t(BIT_MASK_TRXRPT_TIMER_TH_8822B << BIT_SHIFT_TRXRPT_TIMER_TH_8822B)\n#define BIT_CLEAR_TRXRPT_TIMER_TH_8822B(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8822B))\n#define BIT_GET_TRXRPT_TIMER_TH_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8822B) &                            \\\n\t BIT_MASK_TRXRPT_TIMER_TH_8822B)\n#define BIT_SET_TRXRPT_TIMER_TH_8822B(x, v)                                    \\\n\t(BIT_CLEAR_TRXRPT_TIMER_TH_8822B(x) | BIT_TRXRPT_TIMER_TH_8822B(v))\n\n#define BIT_SHIFT_TRXRPT_LEN_TH_8822B 16\n#define BIT_MASK_TRXRPT_LEN_TH_8822B 0xff\n#define BIT_TRXRPT_LEN_TH_8822B(x)                                             \\\n\t(((x) & BIT_MASK_TRXRPT_LEN_TH_8822B) << BIT_SHIFT_TRXRPT_LEN_TH_8822B)\n#define BITS_TRXRPT_LEN_TH_8822B                                               \\\n\t(BIT_MASK_TRXRPT_LEN_TH_8822B << BIT_SHIFT_TRXRPT_LEN_TH_8822B)\n#define BIT_CLEAR_TRXRPT_LEN_TH_8822B(x) ((x) & (~BITS_TRXRPT_LEN_TH_8822B))\n#define BIT_GET_TRXRPT_LEN_TH_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8822B) & BIT_MASK_TRXRPT_LEN_TH_8822B)\n#define BIT_SET_TRXRPT_LEN_TH_8822B(x, v)                                      \\\n\t(BIT_CLEAR_TRXRPT_LEN_TH_8822B(x) | BIT_TRXRPT_LEN_TH_8822B(v))\n\n#define BIT_SHIFT_TRXRPT_READ_PTR_8822B 8\n#define BIT_MASK_TRXRPT_READ_PTR_8822B 0xff\n#define BIT_TRXRPT_READ_PTR_8822B(x)                                           \\\n\t(((x) & BIT_MASK_TRXRPT_READ_PTR_8822B)                                \\\n\t << BIT_SHIFT_TRXRPT_READ_PTR_8822B)\n#define BITS_TRXRPT_READ_PTR_8822B                                             \\\n\t(BIT_MASK_TRXRPT_READ_PTR_8822B << BIT_SHIFT_TRXRPT_READ_PTR_8822B)\n#define BIT_CLEAR_TRXRPT_READ_PTR_8822B(x) ((x) & (~BITS_TRXRPT_READ_PTR_8822B))\n#define BIT_GET_TRXRPT_READ_PTR_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8822B) &                            \\\n\t BIT_MASK_TRXRPT_READ_PTR_8822B)\n#define BIT_SET_TRXRPT_READ_PTR_8822B(x, v)                                    \\\n\t(BIT_CLEAR_TRXRPT_READ_PTR_8822B(x) | BIT_TRXRPT_READ_PTR_8822B(v))\n\n#define BIT_SHIFT_TRXRPT_WRITE_PTR_8822B 0\n#define BIT_MASK_TRXRPT_WRITE_PTR_8822B 0xff\n#define BIT_TRXRPT_WRITE_PTR_8822B(x)                                          \\\n\t(((x) & BIT_MASK_TRXRPT_WRITE_PTR_8822B)                               \\\n\t << BIT_SHIFT_TRXRPT_WRITE_PTR_8822B)\n#define BITS_TRXRPT_WRITE_PTR_8822B                                            \\\n\t(BIT_MASK_TRXRPT_WRITE_PTR_8822B << BIT_SHIFT_TRXRPT_WRITE_PTR_8822B)\n#define BIT_CLEAR_TRXRPT_WRITE_PTR_8822B(x)                                    \\\n\t((x) & (~BITS_TRXRPT_WRITE_PTR_8822B))\n#define BIT_GET_TRXRPT_WRITE_PTR_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8822B) &                           \\\n\t BIT_MASK_TRXRPT_WRITE_PTR_8822B)\n#define BIT_SET_TRXRPT_WRITE_PTR_8822B(x, v)                                   \\\n\t(BIT_CLEAR_TRXRPT_WRITE_PTR_8822B(x) | BIT_TRXRPT_WRITE_PTR_8822B(v))\n\n/* 2 REG_INIRTS_RATE_SEL_8822B */\n#define BIT_LEAG_RTS_BW_DUP_8822B BIT(5)\n\n/* 2 REG_BASIC_CFEND_RATE_8822B */\n\n#define BIT_SHIFT_BASIC_CFEND_RATE_8822B 0\n#define BIT_MASK_BASIC_CFEND_RATE_8822B 0x1f\n#define BIT_BASIC_CFEND_RATE_8822B(x)                                          \\\n\t(((x) & BIT_MASK_BASIC_CFEND_RATE_8822B)                               \\\n\t << BIT_SHIFT_BASIC_CFEND_RATE_8822B)\n#define BITS_BASIC_CFEND_RATE_8822B                                            \\\n\t(BIT_MASK_BASIC_CFEND_RATE_8822B << BIT_SHIFT_BASIC_CFEND_RATE_8822B)\n#define BIT_CLEAR_BASIC_CFEND_RATE_8822B(x)                                    \\\n\t((x) & (~BITS_BASIC_CFEND_RATE_8822B))\n#define BIT_GET_BASIC_CFEND_RATE_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8822B) &                           \\\n\t BIT_MASK_BASIC_CFEND_RATE_8822B)\n#define BIT_SET_BASIC_CFEND_RATE_8822B(x, v)                                   \\\n\t(BIT_CLEAR_BASIC_CFEND_RATE_8822B(x) | BIT_BASIC_CFEND_RATE_8822B(v))\n\n/* 2 REG_STBC_CFEND_RATE_8822B */\n\n#define BIT_SHIFT_STBC_CFEND_RATE_8822B 0\n#define BIT_MASK_STBC_CFEND_RATE_8822B 0x1f\n#define BIT_STBC_CFEND_RATE_8822B(x)                                           \\\n\t(((x) & BIT_MASK_STBC_CFEND_RATE_8822B)                                \\\n\t << BIT_SHIFT_STBC_CFEND_RATE_8822B)\n#define BITS_STBC_CFEND_RATE_8822B                                             \\\n\t(BIT_MASK_STBC_CFEND_RATE_8822B << BIT_SHIFT_STBC_CFEND_RATE_8822B)\n#define BIT_CLEAR_STBC_CFEND_RATE_8822B(x) ((x) & (~BITS_STBC_CFEND_RATE_8822B))\n#define BIT_GET_STBC_CFEND_RATE_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_STBC_CFEND_RATE_8822B) &                            \\\n\t BIT_MASK_STBC_CFEND_RATE_8822B)\n#define BIT_SET_STBC_CFEND_RATE_8822B(x, v)                                    \\\n\t(BIT_CLEAR_STBC_CFEND_RATE_8822B(x) | BIT_STBC_CFEND_RATE_8822B(v))\n\n/* 2 REG_DATA_SC_8822B */\n\n#define BIT_SHIFT_TXSC_40M_8822B 4\n#define BIT_MASK_TXSC_40M_8822B 0xf\n#define BIT_TXSC_40M_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_TXSC_40M_8822B) << BIT_SHIFT_TXSC_40M_8822B)\n#define BITS_TXSC_40M_8822B                                                    \\\n\t(BIT_MASK_TXSC_40M_8822B << BIT_SHIFT_TXSC_40M_8822B)\n#define BIT_CLEAR_TXSC_40M_8822B(x) ((x) & (~BITS_TXSC_40M_8822B))\n#define BIT_GET_TXSC_40M_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXSC_40M_8822B) & BIT_MASK_TXSC_40M_8822B)\n#define BIT_SET_TXSC_40M_8822B(x, v)                                           \\\n\t(BIT_CLEAR_TXSC_40M_8822B(x) | BIT_TXSC_40M_8822B(v))\n\n#define BIT_SHIFT_TXSC_20M_8822B 0\n#define BIT_MASK_TXSC_20M_8822B 0xf\n#define BIT_TXSC_20M_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_TXSC_20M_8822B) << BIT_SHIFT_TXSC_20M_8822B)\n#define BITS_TXSC_20M_8822B                                                    \\\n\t(BIT_MASK_TXSC_20M_8822B << BIT_SHIFT_TXSC_20M_8822B)\n#define BIT_CLEAR_TXSC_20M_8822B(x) ((x) & (~BITS_TXSC_20M_8822B))\n#define BIT_GET_TXSC_20M_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXSC_20M_8822B) & BIT_MASK_TXSC_20M_8822B)\n#define BIT_SET_TXSC_20M_8822B(x, v)                                           \\\n\t(BIT_CLEAR_TXSC_20M_8822B(x) | BIT_TXSC_20M_8822B(v))\n\n/* 2 REG_MACID_SLEEP3_8822B */\n\n#define BIT_SHIFT_MACID127_96_PKTSLEEP_8822B 0\n#define BIT_MASK_MACID127_96_PKTSLEEP_8822B 0xffffffffL\n#define BIT_MACID127_96_PKTSLEEP_8822B(x)                                      \\\n\t(((x) & BIT_MASK_MACID127_96_PKTSLEEP_8822B)                           \\\n\t << BIT_SHIFT_MACID127_96_PKTSLEEP_8822B)\n#define BITS_MACID127_96_PKTSLEEP_8822B                                        \\\n\t(BIT_MASK_MACID127_96_PKTSLEEP_8822B                                   \\\n\t << BIT_SHIFT_MACID127_96_PKTSLEEP_8822B)\n#define BIT_CLEAR_MACID127_96_PKTSLEEP_8822B(x)                                \\\n\t((x) & (~BITS_MACID127_96_PKTSLEEP_8822B))\n#define BIT_GET_MACID127_96_PKTSLEEP_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8822B) &                       \\\n\t BIT_MASK_MACID127_96_PKTSLEEP_8822B)\n#define BIT_SET_MACID127_96_PKTSLEEP_8822B(x, v)                               \\\n\t(BIT_CLEAR_MACID127_96_PKTSLEEP_8822B(x) |                             \\\n\t BIT_MACID127_96_PKTSLEEP_8822B(v))\n\n/* 2 REG_MACID_SLEEP1_8822B */\n\n#define BIT_SHIFT_MACID63_32_PKTSLEEP_8822B 0\n#define BIT_MASK_MACID63_32_PKTSLEEP_8822B 0xffffffffL\n#define BIT_MACID63_32_PKTSLEEP_8822B(x)                                       \\\n\t(((x) & BIT_MASK_MACID63_32_PKTSLEEP_8822B)                            \\\n\t << BIT_SHIFT_MACID63_32_PKTSLEEP_8822B)\n#define BITS_MACID63_32_PKTSLEEP_8822B                                         \\\n\t(BIT_MASK_MACID63_32_PKTSLEEP_8822B                                    \\\n\t << BIT_SHIFT_MACID63_32_PKTSLEEP_8822B)\n#define BIT_CLEAR_MACID63_32_PKTSLEEP_8822B(x)                                 \\\n\t((x) & (~BITS_MACID63_32_PKTSLEEP_8822B))\n#define BIT_GET_MACID63_32_PKTSLEEP_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8822B) &                        \\\n\t BIT_MASK_MACID63_32_PKTSLEEP_8822B)\n#define BIT_SET_MACID63_32_PKTSLEEP_8822B(x, v)                                \\\n\t(BIT_CLEAR_MACID63_32_PKTSLEEP_8822B(x) |                              \\\n\t BIT_MACID63_32_PKTSLEEP_8822B(v))\n\n/* 2 REG_ARFR2_V1_8822B */\n\n#define BIT_SHIFT_ARFR2_V1_8822B 0\n#define BIT_MASK_ARFR2_V1_8822B 0xffffffffffffffffL\n#define BIT_ARFR2_V1_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_ARFR2_V1_8822B) << BIT_SHIFT_ARFR2_V1_8822B)\n#define BITS_ARFR2_V1_8822B                                                    \\\n\t(BIT_MASK_ARFR2_V1_8822B << BIT_SHIFT_ARFR2_V1_8822B)\n#define BIT_CLEAR_ARFR2_V1_8822B(x) ((x) & (~BITS_ARFR2_V1_8822B))\n#define BIT_GET_ARFR2_V1_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_ARFR2_V1_8822B) & BIT_MASK_ARFR2_V1_8822B)\n#define BIT_SET_ARFR2_V1_8822B(x, v)                                           \\\n\t(BIT_CLEAR_ARFR2_V1_8822B(x) | BIT_ARFR2_V1_8822B(v))\n\n/* 2 REG_ARFR3_V1_8822B */\n\n#define BIT_SHIFT_ARFR3_V1_8822B 0\n#define BIT_MASK_ARFR3_V1_8822B 0xffffffffffffffffL\n#define BIT_ARFR3_V1_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_ARFR3_V1_8822B) << BIT_SHIFT_ARFR3_V1_8822B)\n#define BITS_ARFR3_V1_8822B                                                    \\\n\t(BIT_MASK_ARFR3_V1_8822B << BIT_SHIFT_ARFR3_V1_8822B)\n#define BIT_CLEAR_ARFR3_V1_8822B(x) ((x) & (~BITS_ARFR3_V1_8822B))\n#define BIT_GET_ARFR3_V1_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_ARFR3_V1_8822B) & BIT_MASK_ARFR3_V1_8822B)\n#define BIT_SET_ARFR3_V1_8822B(x, v)                                           \\\n\t(BIT_CLEAR_ARFR3_V1_8822B(x) | BIT_ARFR3_V1_8822B(v))\n\n/* 2 REG_ARFR4_8822B */\n\n#define BIT_SHIFT_ARFR4_8822B 0\n#define BIT_MASK_ARFR4_8822B 0xffffffffffffffffL\n#define BIT_ARFR4_8822B(x)                                                     \\\n\t(((x) & BIT_MASK_ARFR4_8822B) << BIT_SHIFT_ARFR4_8822B)\n#define BITS_ARFR4_8822B (BIT_MASK_ARFR4_8822B << BIT_SHIFT_ARFR4_8822B)\n#define BIT_CLEAR_ARFR4_8822B(x) ((x) & (~BITS_ARFR4_8822B))\n#define BIT_GET_ARFR4_8822B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ARFR4_8822B) & BIT_MASK_ARFR4_8822B)\n#define BIT_SET_ARFR4_8822B(x, v)                                              \\\n\t(BIT_CLEAR_ARFR4_8822B(x) | BIT_ARFR4_8822B(v))\n\n/* 2 REG_ARFR5_8822B */\n\n#define BIT_SHIFT_ARFR5_8822B 0\n#define BIT_MASK_ARFR5_8822B 0xffffffffffffffffL\n#define BIT_ARFR5_8822B(x)                                                     \\\n\t(((x) & BIT_MASK_ARFR5_8822B) << BIT_SHIFT_ARFR5_8822B)\n#define BITS_ARFR5_8822B (BIT_MASK_ARFR5_8822B << BIT_SHIFT_ARFR5_8822B)\n#define BIT_CLEAR_ARFR5_8822B(x) ((x) & (~BITS_ARFR5_8822B))\n#define BIT_GET_ARFR5_8822B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ARFR5_8822B) & BIT_MASK_ARFR5_8822B)\n#define BIT_SET_ARFR5_8822B(x, v)                                              \\\n\t(BIT_CLEAR_ARFR5_8822B(x) | BIT_ARFR5_8822B(v))\n\n/* 2 REG_TXRPT_START_OFFSET_8822B */\n\n#define BIT_SHIFT_MACID_MURATE_OFFSET_8822B 24\n#define BIT_MASK_MACID_MURATE_OFFSET_8822B 0xff\n#define BIT_MACID_MURATE_OFFSET_8822B(x)                                       \\\n\t(((x) & BIT_MASK_MACID_MURATE_OFFSET_8822B)                            \\\n\t << BIT_SHIFT_MACID_MURATE_OFFSET_8822B)\n#define BITS_MACID_MURATE_OFFSET_8822B                                         \\\n\t(BIT_MASK_MACID_MURATE_OFFSET_8822B                                    \\\n\t << BIT_SHIFT_MACID_MURATE_OFFSET_8822B)\n#define BIT_CLEAR_MACID_MURATE_OFFSET_8822B(x)                                 \\\n\t((x) & (~BITS_MACID_MURATE_OFFSET_8822B))\n#define BIT_GET_MACID_MURATE_OFFSET_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_MACID_MURATE_OFFSET_8822B) &                        \\\n\t BIT_MASK_MACID_MURATE_OFFSET_8822B)\n#define BIT_SET_MACID_MURATE_OFFSET_8822B(x, v)                                \\\n\t(BIT_CLEAR_MACID_MURATE_OFFSET_8822B(x) |                              \\\n\t BIT_MACID_MURATE_OFFSET_8822B(v))\n\n#define BIT_RPTFIFO_SIZE_OPT_8822B BIT(16)\n\n#define BIT_SHIFT_MACID_CTRL_OFFSET_8822B 8\n#define BIT_MASK_MACID_CTRL_OFFSET_8822B 0xff\n#define BIT_MACID_CTRL_OFFSET_8822B(x)                                         \\\n\t(((x) & BIT_MASK_MACID_CTRL_OFFSET_8822B)                              \\\n\t << BIT_SHIFT_MACID_CTRL_OFFSET_8822B)\n#define BITS_MACID_CTRL_OFFSET_8822B                                           \\\n\t(BIT_MASK_MACID_CTRL_OFFSET_8822B << BIT_SHIFT_MACID_CTRL_OFFSET_8822B)\n#define BIT_CLEAR_MACID_CTRL_OFFSET_8822B(x)                                   \\\n\t((x) & (~BITS_MACID_CTRL_OFFSET_8822B))\n#define BIT_GET_MACID_CTRL_OFFSET_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8822B) &                          \\\n\t BIT_MASK_MACID_CTRL_OFFSET_8822B)\n#define BIT_SET_MACID_CTRL_OFFSET_8822B(x, v)                                  \\\n\t(BIT_CLEAR_MACID_CTRL_OFFSET_8822B(x) | BIT_MACID_CTRL_OFFSET_8822B(v))\n\n#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B 0\n#define BIT_MASK_AMPDU_TXRPT_OFFSET_8822B 0xff\n#define BIT_AMPDU_TXRPT_OFFSET_8822B(x)                                        \\\n\t(((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822B)                             \\\n\t << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B)\n#define BITS_AMPDU_TXRPT_OFFSET_8822B                                          \\\n\t(BIT_MASK_AMPDU_TXRPT_OFFSET_8822B                                     \\\n\t << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B)\n#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822B(x)                                  \\\n\t((x) & (~BITS_AMPDU_TXRPT_OFFSET_8822B))\n#define BIT_GET_AMPDU_TXRPT_OFFSET_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B) &                         \\\n\t BIT_MASK_AMPDU_TXRPT_OFFSET_8822B)\n#define BIT_SET_AMPDU_TXRPT_OFFSET_8822B(x, v)                                 \\\n\t(BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822B(x) |                               \\\n\t BIT_AMPDU_TXRPT_OFFSET_8822B(v))\n\n/* 2 REG_POWER_STAGE1_8822B */\n#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8822B BIT(31)\n#define BIT_PTA_WL_PRI_MASK_BCNQ_8822B BIT(30)\n#define BIT_PTA_WL_PRI_MASK_HIQ_8822B BIT(29)\n#define BIT_PTA_WL_PRI_MASK_MGQ_8822B BIT(28)\n#define BIT_PTA_WL_PRI_MASK_BK_8822B BIT(27)\n#define BIT_PTA_WL_PRI_MASK_BE_8822B BIT(26)\n#define BIT_PTA_WL_PRI_MASK_VI_8822B BIT(25)\n#define BIT_PTA_WL_PRI_MASK_VO_8822B BIT(24)\n\n#define BIT_SHIFT_POWER_STAGE1_8822B 0\n#define BIT_MASK_POWER_STAGE1_8822B 0xffffff\n#define BIT_POWER_STAGE1_8822B(x)                                              \\\n\t(((x) & BIT_MASK_POWER_STAGE1_8822B) << BIT_SHIFT_POWER_STAGE1_8822B)\n#define BITS_POWER_STAGE1_8822B                                                \\\n\t(BIT_MASK_POWER_STAGE1_8822B << BIT_SHIFT_POWER_STAGE1_8822B)\n#define BIT_CLEAR_POWER_STAGE1_8822B(x) ((x) & (~BITS_POWER_STAGE1_8822B))\n#define BIT_GET_POWER_STAGE1_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_POWER_STAGE1_8822B) & BIT_MASK_POWER_STAGE1_8822B)\n#define BIT_SET_POWER_STAGE1_8822B(x, v)                                       \\\n\t(BIT_CLEAR_POWER_STAGE1_8822B(x) | BIT_POWER_STAGE1_8822B(v))\n\n/* 2 REG_POWER_STAGE2_8822B */\n#define BIT__R_CTRL_PKT_POW_ADJ_8822B BIT(24)\n\n#define BIT_SHIFT_POWER_STAGE2_8822B 0\n#define BIT_MASK_POWER_STAGE2_8822B 0xffffff\n#define BIT_POWER_STAGE2_8822B(x)                                              \\\n\t(((x) & BIT_MASK_POWER_STAGE2_8822B) << BIT_SHIFT_POWER_STAGE2_8822B)\n#define BITS_POWER_STAGE2_8822B                                                \\\n\t(BIT_MASK_POWER_STAGE2_8822B << BIT_SHIFT_POWER_STAGE2_8822B)\n#define BIT_CLEAR_POWER_STAGE2_8822B(x) ((x) & (~BITS_POWER_STAGE2_8822B))\n#define BIT_GET_POWER_STAGE2_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_POWER_STAGE2_8822B) & BIT_MASK_POWER_STAGE2_8822B)\n#define BIT_SET_POWER_STAGE2_8822B(x, v)                                       \\\n\t(BIT_CLEAR_POWER_STAGE2_8822B(x) | BIT_POWER_STAGE2_8822B(v))\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8822B */\n\n#define BIT_SHIFT_PAD_NUM_THRES_8822B 24\n#define BIT_MASK_PAD_NUM_THRES_8822B 0x3f\n#define BIT_PAD_NUM_THRES_8822B(x)                                             \\\n\t(((x) & BIT_MASK_PAD_NUM_THRES_8822B) << BIT_SHIFT_PAD_NUM_THRES_8822B)\n#define BITS_PAD_NUM_THRES_8822B                                               \\\n\t(BIT_MASK_PAD_NUM_THRES_8822B << BIT_SHIFT_PAD_NUM_THRES_8822B)\n#define BIT_CLEAR_PAD_NUM_THRES_8822B(x) ((x) & (~BITS_PAD_NUM_THRES_8822B))\n#define BIT_GET_PAD_NUM_THRES_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PAD_NUM_THRES_8822B) & BIT_MASK_PAD_NUM_THRES_8822B)\n#define BIT_SET_PAD_NUM_THRES_8822B(x, v)                                      \\\n\t(BIT_CLEAR_PAD_NUM_THRES_8822B(x) | BIT_PAD_NUM_THRES_8822B(v))\n\n#define BIT_R_DMA_THIS_QUEUE_BK_8822B BIT(23)\n#define BIT_R_DMA_THIS_QUEUE_BE_8822B BIT(22)\n#define BIT_R_DMA_THIS_QUEUE_VI_8822B BIT(21)\n#define BIT_R_DMA_THIS_QUEUE_VO_8822B BIT(20)\n\n#define BIT_SHIFT_R_TOTAL_LEN_TH_8822B 8\n#define BIT_MASK_R_TOTAL_LEN_TH_8822B 0xfff\n#define BIT_R_TOTAL_LEN_TH_8822B(x)                                            \\\n\t(((x) & BIT_MASK_R_TOTAL_LEN_TH_8822B)                                 \\\n\t << BIT_SHIFT_R_TOTAL_LEN_TH_8822B)\n#define BITS_R_TOTAL_LEN_TH_8822B                                              \\\n\t(BIT_MASK_R_TOTAL_LEN_TH_8822B << BIT_SHIFT_R_TOTAL_LEN_TH_8822B)\n#define BIT_CLEAR_R_TOTAL_LEN_TH_8822B(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8822B))\n#define BIT_GET_R_TOTAL_LEN_TH_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8822B) &                             \\\n\t BIT_MASK_R_TOTAL_LEN_TH_8822B)\n#define BIT_SET_R_TOTAL_LEN_TH_8822B(x, v)                                     \\\n\t(BIT_CLEAR_R_TOTAL_LEN_TH_8822B(x) | BIT_R_TOTAL_LEN_TH_8822B(v))\n\n#define BIT_EN_NEW_EARLY_8822B BIT(7)\n#define BIT_PRE_TX_CMD_8822B BIT(6)\n\n#define BIT_SHIFT_NUM_SCL_EN_8822B 4\n#define BIT_MASK_NUM_SCL_EN_8822B 0x3\n#define BIT_NUM_SCL_EN_8822B(x)                                                \\\n\t(((x) & BIT_MASK_NUM_SCL_EN_8822B) << BIT_SHIFT_NUM_SCL_EN_8822B)\n#define BITS_NUM_SCL_EN_8822B                                                  \\\n\t(BIT_MASK_NUM_SCL_EN_8822B << BIT_SHIFT_NUM_SCL_EN_8822B)\n#define BIT_CLEAR_NUM_SCL_EN_8822B(x) ((x) & (~BITS_NUM_SCL_EN_8822B))\n#define BIT_GET_NUM_SCL_EN_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_NUM_SCL_EN_8822B) & BIT_MASK_NUM_SCL_EN_8822B)\n#define BIT_SET_NUM_SCL_EN_8822B(x, v)                                         \\\n\t(BIT_CLEAR_NUM_SCL_EN_8822B(x) | BIT_NUM_SCL_EN_8822B(v))\n\n#define BIT_BK_EN_8822B BIT(3)\n#define BIT_BE_EN_8822B BIT(2)\n#define BIT_VI_EN_8822B BIT(1)\n#define BIT_VO_EN_8822B BIT(0)\n\n/* 2 REG_PKT_LIFE_TIME_8822B */\n\n#define BIT_SHIFT_PKT_LIFTIME_BEBK_8822B 16\n#define BIT_MASK_PKT_LIFTIME_BEBK_8822B 0xffff\n#define BIT_PKT_LIFTIME_BEBK_8822B(x)                                          \\\n\t(((x) & BIT_MASK_PKT_LIFTIME_BEBK_8822B)                               \\\n\t << BIT_SHIFT_PKT_LIFTIME_BEBK_8822B)\n#define BITS_PKT_LIFTIME_BEBK_8822B                                            \\\n\t(BIT_MASK_PKT_LIFTIME_BEBK_8822B << BIT_SHIFT_PKT_LIFTIME_BEBK_8822B)\n#define BIT_CLEAR_PKT_LIFTIME_BEBK_8822B(x)                                    \\\n\t((x) & (~BITS_PKT_LIFTIME_BEBK_8822B))\n#define BIT_GET_PKT_LIFTIME_BEBK_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8822B) &                           \\\n\t BIT_MASK_PKT_LIFTIME_BEBK_8822B)\n#define BIT_SET_PKT_LIFTIME_BEBK_8822B(x, v)                                   \\\n\t(BIT_CLEAR_PKT_LIFTIME_BEBK_8822B(x) | BIT_PKT_LIFTIME_BEBK_8822B(v))\n\n#define BIT_SHIFT_PKT_LIFTIME_VOVI_8822B 0\n#define BIT_MASK_PKT_LIFTIME_VOVI_8822B 0xffff\n#define BIT_PKT_LIFTIME_VOVI_8822B(x)                                          \\\n\t(((x) & BIT_MASK_PKT_LIFTIME_VOVI_8822B)                               \\\n\t << BIT_SHIFT_PKT_LIFTIME_VOVI_8822B)\n#define BITS_PKT_LIFTIME_VOVI_8822B                                            \\\n\t(BIT_MASK_PKT_LIFTIME_VOVI_8822B << BIT_SHIFT_PKT_LIFTIME_VOVI_8822B)\n#define BIT_CLEAR_PKT_LIFTIME_VOVI_8822B(x)                                    \\\n\t((x) & (~BITS_PKT_LIFTIME_VOVI_8822B))\n#define BIT_GET_PKT_LIFTIME_VOVI_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8822B) &                           \\\n\t BIT_MASK_PKT_LIFTIME_VOVI_8822B)\n#define BIT_SET_PKT_LIFTIME_VOVI_8822B(x, v)                                   \\\n\t(BIT_CLEAR_PKT_LIFTIME_VOVI_8822B(x) | BIT_PKT_LIFTIME_VOVI_8822B(v))\n\n/* 2 REG_STBC_SETTING_8822B */\n\n#define BIT_SHIFT_CDEND_TXTIME_L_8822B 4\n#define BIT_MASK_CDEND_TXTIME_L_8822B 0xf\n#define BIT_CDEND_TXTIME_L_8822B(x)                                            \\\n\t(((x) & BIT_MASK_CDEND_TXTIME_L_8822B)                                 \\\n\t << BIT_SHIFT_CDEND_TXTIME_L_8822B)\n#define BITS_CDEND_TXTIME_L_8822B                                              \\\n\t(BIT_MASK_CDEND_TXTIME_L_8822B << BIT_SHIFT_CDEND_TXTIME_L_8822B)\n#define BIT_CLEAR_CDEND_TXTIME_L_8822B(x) ((x) & (~BITS_CDEND_TXTIME_L_8822B))\n#define BIT_GET_CDEND_TXTIME_L_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_CDEND_TXTIME_L_8822B) &                             \\\n\t BIT_MASK_CDEND_TXTIME_L_8822B)\n#define BIT_SET_CDEND_TXTIME_L_8822B(x, v)                                     \\\n\t(BIT_CLEAR_CDEND_TXTIME_L_8822B(x) | BIT_CDEND_TXTIME_L_8822B(v))\n\n#define BIT_SHIFT_NESS_8822B 2\n#define BIT_MASK_NESS_8822B 0x3\n#define BIT_NESS_8822B(x) (((x) & BIT_MASK_NESS_8822B) << BIT_SHIFT_NESS_8822B)\n#define BITS_NESS_8822B (BIT_MASK_NESS_8822B << BIT_SHIFT_NESS_8822B)\n#define BIT_CLEAR_NESS_8822B(x) ((x) & (~BITS_NESS_8822B))\n#define BIT_GET_NESS_8822B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_NESS_8822B) & BIT_MASK_NESS_8822B)\n#define BIT_SET_NESS_8822B(x, v) (BIT_CLEAR_NESS_8822B(x) | BIT_NESS_8822B(v))\n\n#define BIT_SHIFT_STBC_CFEND_8822B 0\n#define BIT_MASK_STBC_CFEND_8822B 0x3\n#define BIT_STBC_CFEND_8822B(x)                                                \\\n\t(((x) & BIT_MASK_STBC_CFEND_8822B) << BIT_SHIFT_STBC_CFEND_8822B)\n#define BITS_STBC_CFEND_8822B                                                  \\\n\t(BIT_MASK_STBC_CFEND_8822B << BIT_SHIFT_STBC_CFEND_8822B)\n#define BIT_CLEAR_STBC_CFEND_8822B(x) ((x) & (~BITS_STBC_CFEND_8822B))\n#define BIT_GET_STBC_CFEND_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_STBC_CFEND_8822B) & BIT_MASK_STBC_CFEND_8822B)\n#define BIT_SET_STBC_CFEND_8822B(x, v)                                         \\\n\t(BIT_CLEAR_STBC_CFEND_8822B(x) | BIT_STBC_CFEND_8822B(v))\n\n/* 2 REG_STBC_SETTING2_8822B */\n\n#define BIT_SHIFT_CDEND_TXTIME_H_8822B 0\n#define BIT_MASK_CDEND_TXTIME_H_8822B 0x1f\n#define BIT_CDEND_TXTIME_H_8822B(x)                                            \\\n\t(((x) & BIT_MASK_CDEND_TXTIME_H_8822B)                                 \\\n\t << BIT_SHIFT_CDEND_TXTIME_H_8822B)\n#define BITS_CDEND_TXTIME_H_8822B                                              \\\n\t(BIT_MASK_CDEND_TXTIME_H_8822B << BIT_SHIFT_CDEND_TXTIME_H_8822B)\n#define BIT_CLEAR_CDEND_TXTIME_H_8822B(x) ((x) & (~BITS_CDEND_TXTIME_H_8822B))\n#define BIT_GET_CDEND_TXTIME_H_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_CDEND_TXTIME_H_8822B) &                             \\\n\t BIT_MASK_CDEND_TXTIME_H_8822B)\n#define BIT_SET_CDEND_TXTIME_H_8822B(x, v)                                     \\\n\t(BIT_CLEAR_CDEND_TXTIME_H_8822B(x) | BIT_CDEND_TXTIME_H_8822B(v))\n\n/* 2 REG_QUEUE_CTRL_8822B */\n#define BIT_PTA_EDCCA_EN_8822B BIT(5)\n#define BIT_PTA_WL_TX_EN_8822B BIT(4)\n#define BIT_R_USE_DATA_BW_8822B BIT(3)\n#define BIT_TRI_PKT_INT_MODE1_8822B BIT(2)\n#define BIT_TRI_PKT_INT_MODE0_8822B BIT(1)\n#define BIT_ACQ_MODE_SEL_8822B BIT(0)\n\n/* 2 REG_SINGLE_AMPDU_CTRL_8822B */\n#define BIT_EN_SINGLE_APMDU_8822B BIT(7)\n\n/* 2 REG_PROT_MODE_CTRL_8822B */\n\n#define BIT_SHIFT_RTS_MAX_AGG_NUM_8822B 24\n#define BIT_MASK_RTS_MAX_AGG_NUM_8822B 0x3f\n#define BIT_RTS_MAX_AGG_NUM_8822B(x)                                           \\\n\t(((x) & BIT_MASK_RTS_MAX_AGG_NUM_8822B)                                \\\n\t << BIT_SHIFT_RTS_MAX_AGG_NUM_8822B)\n#define BITS_RTS_MAX_AGG_NUM_8822B                                             \\\n\t(BIT_MASK_RTS_MAX_AGG_NUM_8822B << BIT_SHIFT_RTS_MAX_AGG_NUM_8822B)\n#define BIT_CLEAR_RTS_MAX_AGG_NUM_8822B(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8822B))\n#define BIT_GET_RTS_MAX_AGG_NUM_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8822B) &                            \\\n\t BIT_MASK_RTS_MAX_AGG_NUM_8822B)\n#define BIT_SET_RTS_MAX_AGG_NUM_8822B(x, v)                                    \\\n\t(BIT_CLEAR_RTS_MAX_AGG_NUM_8822B(x) | BIT_RTS_MAX_AGG_NUM_8822B(v))\n\n#define BIT_SHIFT_MAX_AGG_NUM_8822B 16\n#define BIT_MASK_MAX_AGG_NUM_8822B 0x3f\n#define BIT_MAX_AGG_NUM_8822B(x)                                               \\\n\t(((x) & BIT_MASK_MAX_AGG_NUM_8822B) << BIT_SHIFT_MAX_AGG_NUM_8822B)\n#define BITS_MAX_AGG_NUM_8822B                                                 \\\n\t(BIT_MASK_MAX_AGG_NUM_8822B << BIT_SHIFT_MAX_AGG_NUM_8822B)\n#define BIT_CLEAR_MAX_AGG_NUM_8822B(x) ((x) & (~BITS_MAX_AGG_NUM_8822B))\n#define BIT_GET_MAX_AGG_NUM_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_MAX_AGG_NUM_8822B) & BIT_MASK_MAX_AGG_NUM_8822B)\n#define BIT_SET_MAX_AGG_NUM_8822B(x, v)                                        \\\n\t(BIT_CLEAR_MAX_AGG_NUM_8822B(x) | BIT_MAX_AGG_NUM_8822B(v))\n\n#define BIT_SHIFT_RTS_TXTIME_TH_8822B 8\n#define BIT_MASK_RTS_TXTIME_TH_8822B 0xff\n#define BIT_RTS_TXTIME_TH_8822B(x)                                             \\\n\t(((x) & BIT_MASK_RTS_TXTIME_TH_8822B) << BIT_SHIFT_RTS_TXTIME_TH_8822B)\n#define BITS_RTS_TXTIME_TH_8822B                                               \\\n\t(BIT_MASK_RTS_TXTIME_TH_8822B << BIT_SHIFT_RTS_TXTIME_TH_8822B)\n#define BIT_CLEAR_RTS_TXTIME_TH_8822B(x) ((x) & (~BITS_RTS_TXTIME_TH_8822B))\n#define BIT_GET_RTS_TXTIME_TH_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_RTS_TXTIME_TH_8822B) & BIT_MASK_RTS_TXTIME_TH_8822B)\n#define BIT_SET_RTS_TXTIME_TH_8822B(x, v)                                      \\\n\t(BIT_CLEAR_RTS_TXTIME_TH_8822B(x) | BIT_RTS_TXTIME_TH_8822B(v))\n\n#define BIT_SHIFT_RTS_LEN_TH_8822B 0\n#define BIT_MASK_RTS_LEN_TH_8822B 0xff\n#define BIT_RTS_LEN_TH_8822B(x)                                                \\\n\t(((x) & BIT_MASK_RTS_LEN_TH_8822B) << BIT_SHIFT_RTS_LEN_TH_8822B)\n#define BITS_RTS_LEN_TH_8822B                                                  \\\n\t(BIT_MASK_RTS_LEN_TH_8822B << BIT_SHIFT_RTS_LEN_TH_8822B)\n#define BIT_CLEAR_RTS_LEN_TH_8822B(x) ((x) & (~BITS_RTS_LEN_TH_8822B))\n#define BIT_GET_RTS_LEN_TH_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_RTS_LEN_TH_8822B) & BIT_MASK_RTS_LEN_TH_8822B)\n#define BIT_SET_RTS_LEN_TH_8822B(x, v)                                         \\\n\t(BIT_CLEAR_RTS_LEN_TH_8822B(x) | BIT_RTS_LEN_TH_8822B(v))\n\n/* 2 REG_BAR_MODE_CTRL_8822B */\n\n#define BIT_SHIFT_BAR_RTY_LMT_8822B 16\n#define BIT_MASK_BAR_RTY_LMT_8822B 0x3\n#define BIT_BAR_RTY_LMT_8822B(x)                                               \\\n\t(((x) & BIT_MASK_BAR_RTY_LMT_8822B) << BIT_SHIFT_BAR_RTY_LMT_8822B)\n#define BITS_BAR_RTY_LMT_8822B                                                 \\\n\t(BIT_MASK_BAR_RTY_LMT_8822B << BIT_SHIFT_BAR_RTY_LMT_8822B)\n#define BIT_CLEAR_BAR_RTY_LMT_8822B(x) ((x) & (~BITS_BAR_RTY_LMT_8822B))\n#define BIT_GET_BAR_RTY_LMT_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_BAR_RTY_LMT_8822B) & BIT_MASK_BAR_RTY_LMT_8822B)\n#define BIT_SET_BAR_RTY_LMT_8822B(x, v)                                        \\\n\t(BIT_CLEAR_BAR_RTY_LMT_8822B(x) | BIT_BAR_RTY_LMT_8822B(v))\n\n#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B 8\n#define BIT_MASK_BAR_PKT_TXTIME_TH_8822B 0xff\n#define BIT_BAR_PKT_TXTIME_TH_8822B(x)                                         \\\n\t(((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8822B)                              \\\n\t << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B)\n#define BITS_BAR_PKT_TXTIME_TH_8822B                                           \\\n\t(BIT_MASK_BAR_PKT_TXTIME_TH_8822B << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B)\n#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8822B(x)                                   \\\n\t((x) & (~BITS_BAR_PKT_TXTIME_TH_8822B))\n#define BIT_GET_BAR_PKT_TXTIME_TH_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B) &                          \\\n\t BIT_MASK_BAR_PKT_TXTIME_TH_8822B)\n#define BIT_SET_BAR_PKT_TXTIME_TH_8822B(x, v)                                  \\\n\t(BIT_CLEAR_BAR_PKT_TXTIME_TH_8822B(x) | BIT_BAR_PKT_TXTIME_TH_8822B(v))\n\n#define BIT_BAR_EN_V1_8822B BIT(6)\n\n#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B 0\n#define BIT_MASK_BAR_PKTNUM_TH_V1_8822B 0x3f\n#define BIT_BAR_PKTNUM_TH_V1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8822B)                               \\\n\t << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B)\n#define BITS_BAR_PKTNUM_TH_V1_8822B                                            \\\n\t(BIT_MASK_BAR_PKTNUM_TH_V1_8822B << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B)\n#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8822B(x)                                    \\\n\t((x) & (~BITS_BAR_PKTNUM_TH_V1_8822B))\n#define BIT_GET_BAR_PKTNUM_TH_V1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B) &                           \\\n\t BIT_MASK_BAR_PKTNUM_TH_V1_8822B)\n#define BIT_SET_BAR_PKTNUM_TH_V1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_BAR_PKTNUM_TH_V1_8822B(x) | BIT_BAR_PKTNUM_TH_V1_8822B(v))\n\n/* 2 REG_RA_TRY_RATE_AGG_LMT_8822B */\n\n#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B 0\n#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B 0x3f\n#define BIT_RA_TRY_RATE_AGG_LMT_V1_8822B(x)                                    \\\n\t(((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B)                         \\\n\t << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B)\n#define BITS_RA_TRY_RATE_AGG_LMT_V1_8822B                                      \\\n\t(BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B                                 \\\n\t << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B)\n#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822B(x)                              \\\n\t((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8822B))\n#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8822B(x)                                \\\n\t(((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B) &                     \\\n\t BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B)\n#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8822B(x, v)                             \\\n\t(BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822B(x) |                           \\\n\t BIT_RA_TRY_RATE_AGG_LMT_V1_8822B(v))\n\n/* 2 REG_MACID_SLEEP2_8822B */\n\n#define BIT_SHIFT_MACID95_64PKTSLEEP_8822B 0\n#define BIT_MASK_MACID95_64PKTSLEEP_8822B 0xffffffffL\n#define BIT_MACID95_64PKTSLEEP_8822B(x)                                        \\\n\t(((x) & BIT_MASK_MACID95_64PKTSLEEP_8822B)                             \\\n\t << BIT_SHIFT_MACID95_64PKTSLEEP_8822B)\n#define BITS_MACID95_64PKTSLEEP_8822B                                          \\\n\t(BIT_MASK_MACID95_64PKTSLEEP_8822B                                     \\\n\t << BIT_SHIFT_MACID95_64PKTSLEEP_8822B)\n#define BIT_CLEAR_MACID95_64PKTSLEEP_8822B(x)                                  \\\n\t((x) & (~BITS_MACID95_64PKTSLEEP_8822B))\n#define BIT_GET_MACID95_64PKTSLEEP_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8822B) &                         \\\n\t BIT_MASK_MACID95_64PKTSLEEP_8822B)\n#define BIT_SET_MACID95_64PKTSLEEP_8822B(x, v)                                 \\\n\t(BIT_CLEAR_MACID95_64PKTSLEEP_8822B(x) |                               \\\n\t BIT_MACID95_64PKTSLEEP_8822B(v))\n\n/* 2 REG_MACID_SLEEP_8822B */\n\n#define BIT_SHIFT_MACID31_0_PKTSLEEP_8822B 0\n#define BIT_MASK_MACID31_0_PKTSLEEP_8822B 0xffffffffL\n#define BIT_MACID31_0_PKTSLEEP_8822B(x)                                        \\\n\t(((x) & BIT_MASK_MACID31_0_PKTSLEEP_8822B)                             \\\n\t << BIT_SHIFT_MACID31_0_PKTSLEEP_8822B)\n#define BITS_MACID31_0_PKTSLEEP_8822B                                          \\\n\t(BIT_MASK_MACID31_0_PKTSLEEP_8822B                                     \\\n\t << BIT_SHIFT_MACID31_0_PKTSLEEP_8822B)\n#define BIT_CLEAR_MACID31_0_PKTSLEEP_8822B(x)                                  \\\n\t((x) & (~BITS_MACID31_0_PKTSLEEP_8822B))\n#define BIT_GET_MACID31_0_PKTSLEEP_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8822B) &                         \\\n\t BIT_MASK_MACID31_0_PKTSLEEP_8822B)\n#define BIT_SET_MACID31_0_PKTSLEEP_8822B(x, v)                                 \\\n\t(BIT_CLEAR_MACID31_0_PKTSLEEP_8822B(x) |                               \\\n\t BIT_MACID31_0_PKTSLEEP_8822B(v))\n\n/* 2 REG_HW_SEQ0_8822B */\n\n#define BIT_SHIFT_HW_SSN_SEQ0_8822B 0\n#define BIT_MASK_HW_SSN_SEQ0_8822B 0xfff\n#define BIT_HW_SSN_SEQ0_8822B(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ0_8822B) << BIT_SHIFT_HW_SSN_SEQ0_8822B)\n#define BITS_HW_SSN_SEQ0_8822B                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ0_8822B << BIT_SHIFT_HW_SSN_SEQ0_8822B)\n#define BIT_CLEAR_HW_SSN_SEQ0_8822B(x) ((x) & (~BITS_HW_SSN_SEQ0_8822B))\n#define BIT_GET_HW_SSN_SEQ0_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ0_8822B) & BIT_MASK_HW_SSN_SEQ0_8822B)\n#define BIT_SET_HW_SSN_SEQ0_8822B(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ0_8822B(x) | BIT_HW_SSN_SEQ0_8822B(v))\n\n/* 2 REG_HW_SEQ1_8822B */\n\n#define BIT_SHIFT_HW_SSN_SEQ1_8822B 0\n#define BIT_MASK_HW_SSN_SEQ1_8822B 0xfff\n#define BIT_HW_SSN_SEQ1_8822B(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ1_8822B) << BIT_SHIFT_HW_SSN_SEQ1_8822B)\n#define BITS_HW_SSN_SEQ1_8822B                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ1_8822B << BIT_SHIFT_HW_SSN_SEQ1_8822B)\n#define BIT_CLEAR_HW_SSN_SEQ1_8822B(x) ((x) & (~BITS_HW_SSN_SEQ1_8822B))\n#define BIT_GET_HW_SSN_SEQ1_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ1_8822B) & BIT_MASK_HW_SSN_SEQ1_8822B)\n#define BIT_SET_HW_SSN_SEQ1_8822B(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ1_8822B(x) | BIT_HW_SSN_SEQ1_8822B(v))\n\n/* 2 REG_HW_SEQ2_8822B */\n\n#define BIT_SHIFT_HW_SSN_SEQ2_8822B 0\n#define BIT_MASK_HW_SSN_SEQ2_8822B 0xfff\n#define BIT_HW_SSN_SEQ2_8822B(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ2_8822B) << BIT_SHIFT_HW_SSN_SEQ2_8822B)\n#define BITS_HW_SSN_SEQ2_8822B                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ2_8822B << BIT_SHIFT_HW_SSN_SEQ2_8822B)\n#define BIT_CLEAR_HW_SSN_SEQ2_8822B(x) ((x) & (~BITS_HW_SSN_SEQ2_8822B))\n#define BIT_GET_HW_SSN_SEQ2_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ2_8822B) & BIT_MASK_HW_SSN_SEQ2_8822B)\n#define BIT_SET_HW_SSN_SEQ2_8822B(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ2_8822B(x) | BIT_HW_SSN_SEQ2_8822B(v))\n\n/* 2 REG_HW_SEQ3_8822B */\n\n#define BIT_SHIFT_HW_SSN_SEQ3_8822B 0\n#define BIT_MASK_HW_SSN_SEQ3_8822B 0xfff\n#define BIT_HW_SSN_SEQ3_8822B(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ3_8822B) << BIT_SHIFT_HW_SSN_SEQ3_8822B)\n#define BITS_HW_SSN_SEQ3_8822B                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ3_8822B << BIT_SHIFT_HW_SSN_SEQ3_8822B)\n#define BIT_CLEAR_HW_SSN_SEQ3_8822B(x) ((x) & (~BITS_HW_SSN_SEQ3_8822B))\n#define BIT_GET_HW_SSN_SEQ3_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ3_8822B) & BIT_MASK_HW_SSN_SEQ3_8822B)\n#define BIT_SET_HW_SSN_SEQ3_8822B(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ3_8822B(x) | BIT_HW_SSN_SEQ3_8822B(v))\n\n/* 2 REG_NULL_PKT_STATUS_V1_8822B */\n\n#define BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B 2\n#define BIT_MASK_PTCL_TOTAL_PG_V2_8822B 0x3fff\n#define BIT_PTCL_TOTAL_PG_V2_8822B(x)                                          \\\n\t(((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8822B)                               \\\n\t << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B)\n#define BITS_PTCL_TOTAL_PG_V2_8822B                                            \\\n\t(BIT_MASK_PTCL_TOTAL_PG_V2_8822B << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B)\n#define BIT_CLEAR_PTCL_TOTAL_PG_V2_8822B(x)                                    \\\n\t((x) & (~BITS_PTCL_TOTAL_PG_V2_8822B))\n#define BIT_GET_PTCL_TOTAL_PG_V2_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B) &                           \\\n\t BIT_MASK_PTCL_TOTAL_PG_V2_8822B)\n#define BIT_SET_PTCL_TOTAL_PG_V2_8822B(x, v)                                   \\\n\t(BIT_CLEAR_PTCL_TOTAL_PG_V2_8822B(x) | BIT_PTCL_TOTAL_PG_V2_8822B(v))\n\n#define BIT_TX_NULL_1_8822B BIT(1)\n#define BIT_TX_NULL_0_8822B BIT(0)\n\n/* 2 REG_PTCL_ERR_STATUS_8822B */\n#define BIT_PTCL_RATE_TABLE_INVALID_8822B BIT(7)\n#define BIT_FTM_T2R_ERROR_8822B BIT(6)\n#define BIT_PTCL_ERR0_8822B BIT(5)\n#define BIT_PTCL_ERR1_8822B BIT(4)\n#define BIT_PTCL_ERR2_8822B BIT(3)\n#define BIT_PTCL_ERR3_8822B BIT(2)\n#define BIT_PTCL_ERR4_8822B BIT(1)\n#define BIT_PTCL_ERR5_8822B BIT(0)\n\n/* 2 REG_NULL_PKT_STATUS_EXTEND_8822B */\n#define BIT_CLI3_TX_NULL_1_8822B BIT(7)\n#define BIT_CLI3_TX_NULL_0_8822B BIT(6)\n#define BIT_CLI2_TX_NULL_1_8822B BIT(5)\n#define BIT_CLI2_TX_NULL_0_8822B BIT(4)\n#define BIT_CLI1_TX_NULL_1_8822B BIT(3)\n#define BIT_CLI1_TX_NULL_0_8822B BIT(2)\n#define BIT_CLI0_TX_NULL_1_8822B BIT(1)\n#define BIT_CLI0_TX_NULL_0_8822B BIT(0)\n\n/* 2 REG_VIDEO_ENHANCEMENT_FUN_8822B */\n#define BIT_VIDEO_JUST_DROP_8822B BIT(1)\n#define BIT_VIDEO_ENHANCEMENT_FUN_EN_8822B BIT(0)\n\n/* 2 REG_BT_POLLUTE_PKT_CNT_8822B */\n\n#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B 0\n#define BIT_MASK_BT_POLLUTE_PKT_CNT_8822B 0xffff\n#define BIT_BT_POLLUTE_PKT_CNT_8822B(x)                                        \\\n\t(((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822B)                             \\\n\t << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B)\n#define BITS_BT_POLLUTE_PKT_CNT_8822B                                          \\\n\t(BIT_MASK_BT_POLLUTE_PKT_CNT_8822B                                     \\\n\t << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B)\n#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822B(x)                                  \\\n\t((x) & (~BITS_BT_POLLUTE_PKT_CNT_8822B))\n#define BIT_GET_BT_POLLUTE_PKT_CNT_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B) &                         \\\n\t BIT_MASK_BT_POLLUTE_PKT_CNT_8822B)\n#define BIT_SET_BT_POLLUTE_PKT_CNT_8822B(x, v)                                 \\\n\t(BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822B(x) |                               \\\n\t BIT_BT_POLLUTE_PKT_CNT_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_PTCL_DBG_8822B */\n\n#define BIT_SHIFT_PTCL_DBG_8822B 0\n#define BIT_MASK_PTCL_DBG_8822B 0xffffffffL\n#define BIT_PTCL_DBG_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_PTCL_DBG_8822B) << BIT_SHIFT_PTCL_DBG_8822B)\n#define BITS_PTCL_DBG_8822B                                                    \\\n\t(BIT_MASK_PTCL_DBG_8822B << BIT_SHIFT_PTCL_DBG_8822B)\n#define BIT_CLEAR_PTCL_DBG_8822B(x) ((x) & (~BITS_PTCL_DBG_8822B))\n#define BIT_GET_PTCL_DBG_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_PTCL_DBG_8822B) & BIT_MASK_PTCL_DBG_8822B)\n#define BIT_SET_PTCL_DBG_8822B(x, v)                                           \\\n\t(BIT_CLEAR_PTCL_DBG_8822B(x) | BIT_PTCL_DBG_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_CPUMGQ_TIMER_CTRL2_8822B */\n\n#define BIT_SHIFT_TRI_HEAD_ADDR_8822B 16\n#define BIT_MASK_TRI_HEAD_ADDR_8822B 0xfff\n#define BIT_TRI_HEAD_ADDR_8822B(x)                                             \\\n\t(((x) & BIT_MASK_TRI_HEAD_ADDR_8822B) << BIT_SHIFT_TRI_HEAD_ADDR_8822B)\n#define BITS_TRI_HEAD_ADDR_8822B                                               \\\n\t(BIT_MASK_TRI_HEAD_ADDR_8822B << BIT_SHIFT_TRI_HEAD_ADDR_8822B)\n#define BIT_CLEAR_TRI_HEAD_ADDR_8822B(x) ((x) & (~BITS_TRI_HEAD_ADDR_8822B))\n#define BIT_GET_TRI_HEAD_ADDR_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8822B) & BIT_MASK_TRI_HEAD_ADDR_8822B)\n#define BIT_SET_TRI_HEAD_ADDR_8822B(x, v)                                      \\\n\t(BIT_CLEAR_TRI_HEAD_ADDR_8822B(x) | BIT_TRI_HEAD_ADDR_8822B(v))\n\n#define BIT_DROP_TH_EN_8822B BIT(8)\n\n#define BIT_SHIFT_DROP_TH_8822B 0\n#define BIT_MASK_DROP_TH_8822B 0xff\n#define BIT_DROP_TH_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_DROP_TH_8822B) << BIT_SHIFT_DROP_TH_8822B)\n#define BITS_DROP_TH_8822B (BIT_MASK_DROP_TH_8822B << BIT_SHIFT_DROP_TH_8822B)\n#define BIT_CLEAR_DROP_TH_8822B(x) ((x) & (~BITS_DROP_TH_8822B))\n#define BIT_GET_DROP_TH_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_DROP_TH_8822B) & BIT_MASK_DROP_TH_8822B)\n#define BIT_SET_DROP_TH_8822B(x, v)                                            \\\n\t(BIT_CLEAR_DROP_TH_8822B(x) | BIT_DROP_TH_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_DUMMY_PAGE4_V1_8822B */\n#define BIT_BCN_EN_EXTHWSEQ_8822B BIT(1)\n#define BIT_BCN_EN_HWSEQ_8822B BIT(0)\n\n/* 2 REG_MOREDATA_8822B */\n#define BIT_MOREDATA_CTRL2_EN_V1_8822B BIT(3)\n#define BIT_MOREDATA_CTRL1_EN_V1_8822B BIT(2)\n#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8822B BIT(0)\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_Q0_Q1_INFO_8822B */\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31)\n\n#define BIT_SHIFT_GTAB_ID_8822B 28\n#define BIT_MASK_GTAB_ID_8822B 0x7\n#define BIT_GTAB_ID_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)\n#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B)\n#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B))\n#define BIT_GET_GTAB_ID_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)\n#define BIT_SET_GTAB_ID_8822B(x, v)                                            \\\n\t(BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v))\n\n#define BIT_SHIFT_AC1_PKT_INFO_8822B 16\n#define BIT_MASK_AC1_PKT_INFO_8822B 0xfff\n#define BIT_AC1_PKT_INFO_8822B(x)                                              \\\n\t(((x) & BIT_MASK_AC1_PKT_INFO_8822B) << BIT_SHIFT_AC1_PKT_INFO_8822B)\n#define BITS_AC1_PKT_INFO_8822B                                                \\\n\t(BIT_MASK_AC1_PKT_INFO_8822B << BIT_SHIFT_AC1_PKT_INFO_8822B)\n#define BIT_CLEAR_AC1_PKT_INFO_8822B(x) ((x) & (~BITS_AC1_PKT_INFO_8822B))\n#define BIT_GET_AC1_PKT_INFO_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC1_PKT_INFO_8822B) & BIT_MASK_AC1_PKT_INFO_8822B)\n#define BIT_SET_AC1_PKT_INFO_8822B(x, v)                                       \\\n\t(BIT_CLEAR_AC1_PKT_INFO_8822B(x) | BIT_AC1_PKT_INFO_8822B(v))\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15)\n\n#define BIT_SHIFT_GTAB_ID_V1_8822B 12\n#define BIT_MASK_GTAB_ID_V1_8822B 0x7\n#define BIT_GTAB_ID_V1_8822B(x)                                                \\\n\t(((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)\n#define BITS_GTAB_ID_V1_8822B                                                  \\\n\t(BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B)\n#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B))\n#define BIT_GET_GTAB_ID_V1_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)\n#define BIT_SET_GTAB_ID_V1_8822B(x, v)                                         \\\n\t(BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v))\n\n#define BIT_SHIFT_AC0_PKT_INFO_8822B 0\n#define BIT_MASK_AC0_PKT_INFO_8822B 0xfff\n#define BIT_AC0_PKT_INFO_8822B(x)                                              \\\n\t(((x) & BIT_MASK_AC0_PKT_INFO_8822B) << BIT_SHIFT_AC0_PKT_INFO_8822B)\n#define BITS_AC0_PKT_INFO_8822B                                                \\\n\t(BIT_MASK_AC0_PKT_INFO_8822B << BIT_SHIFT_AC0_PKT_INFO_8822B)\n#define BIT_CLEAR_AC0_PKT_INFO_8822B(x) ((x) & (~BITS_AC0_PKT_INFO_8822B))\n#define BIT_GET_AC0_PKT_INFO_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC0_PKT_INFO_8822B) & BIT_MASK_AC0_PKT_INFO_8822B)\n#define BIT_SET_AC0_PKT_INFO_8822B(x, v)                                       \\\n\t(BIT_CLEAR_AC0_PKT_INFO_8822B(x) | BIT_AC0_PKT_INFO_8822B(v))\n\n/* 2 REG_Q2_Q3_INFO_8822B */\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31)\n\n#define BIT_SHIFT_GTAB_ID_8822B 28\n#define BIT_MASK_GTAB_ID_8822B 0x7\n#define BIT_GTAB_ID_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)\n#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B)\n#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B))\n#define BIT_GET_GTAB_ID_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)\n#define BIT_SET_GTAB_ID_8822B(x, v)                                            \\\n\t(BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v))\n\n#define BIT_SHIFT_AC3_PKT_INFO_8822B 16\n#define BIT_MASK_AC3_PKT_INFO_8822B 0xfff\n#define BIT_AC3_PKT_INFO_8822B(x)                                              \\\n\t(((x) & BIT_MASK_AC3_PKT_INFO_8822B) << BIT_SHIFT_AC3_PKT_INFO_8822B)\n#define BITS_AC3_PKT_INFO_8822B                                                \\\n\t(BIT_MASK_AC3_PKT_INFO_8822B << BIT_SHIFT_AC3_PKT_INFO_8822B)\n#define BIT_CLEAR_AC3_PKT_INFO_8822B(x) ((x) & (~BITS_AC3_PKT_INFO_8822B))\n#define BIT_GET_AC3_PKT_INFO_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC3_PKT_INFO_8822B) & BIT_MASK_AC3_PKT_INFO_8822B)\n#define BIT_SET_AC3_PKT_INFO_8822B(x, v)                                       \\\n\t(BIT_CLEAR_AC3_PKT_INFO_8822B(x) | BIT_AC3_PKT_INFO_8822B(v))\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15)\n\n#define BIT_SHIFT_GTAB_ID_V1_8822B 12\n#define BIT_MASK_GTAB_ID_V1_8822B 0x7\n#define BIT_GTAB_ID_V1_8822B(x)                                                \\\n\t(((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)\n#define BITS_GTAB_ID_V1_8822B                                                  \\\n\t(BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B)\n#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B))\n#define BIT_GET_GTAB_ID_V1_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)\n#define BIT_SET_GTAB_ID_V1_8822B(x, v)                                         \\\n\t(BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v))\n\n#define BIT_SHIFT_AC2_PKT_INFO_8822B 0\n#define BIT_MASK_AC2_PKT_INFO_8822B 0xfff\n#define BIT_AC2_PKT_INFO_8822B(x)                                              \\\n\t(((x) & BIT_MASK_AC2_PKT_INFO_8822B) << BIT_SHIFT_AC2_PKT_INFO_8822B)\n#define BITS_AC2_PKT_INFO_8822B                                                \\\n\t(BIT_MASK_AC2_PKT_INFO_8822B << BIT_SHIFT_AC2_PKT_INFO_8822B)\n#define BIT_CLEAR_AC2_PKT_INFO_8822B(x) ((x) & (~BITS_AC2_PKT_INFO_8822B))\n#define BIT_GET_AC2_PKT_INFO_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC2_PKT_INFO_8822B) & BIT_MASK_AC2_PKT_INFO_8822B)\n#define BIT_SET_AC2_PKT_INFO_8822B(x, v)                                       \\\n\t(BIT_CLEAR_AC2_PKT_INFO_8822B(x) | BIT_AC2_PKT_INFO_8822B(v))\n\n/* 2 REG_Q4_Q5_INFO_8822B */\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31)\n\n#define BIT_SHIFT_GTAB_ID_8822B 28\n#define BIT_MASK_GTAB_ID_8822B 0x7\n#define BIT_GTAB_ID_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)\n#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B)\n#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B))\n#define BIT_GET_GTAB_ID_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)\n#define BIT_SET_GTAB_ID_8822B(x, v)                                            \\\n\t(BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v))\n\n#define BIT_SHIFT_AC5_PKT_INFO_8822B 16\n#define BIT_MASK_AC5_PKT_INFO_8822B 0xfff\n#define BIT_AC5_PKT_INFO_8822B(x)                                              \\\n\t(((x) & BIT_MASK_AC5_PKT_INFO_8822B) << BIT_SHIFT_AC5_PKT_INFO_8822B)\n#define BITS_AC5_PKT_INFO_8822B                                                \\\n\t(BIT_MASK_AC5_PKT_INFO_8822B << BIT_SHIFT_AC5_PKT_INFO_8822B)\n#define BIT_CLEAR_AC5_PKT_INFO_8822B(x) ((x) & (~BITS_AC5_PKT_INFO_8822B))\n#define BIT_GET_AC5_PKT_INFO_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC5_PKT_INFO_8822B) & BIT_MASK_AC5_PKT_INFO_8822B)\n#define BIT_SET_AC5_PKT_INFO_8822B(x, v)                                       \\\n\t(BIT_CLEAR_AC5_PKT_INFO_8822B(x) | BIT_AC5_PKT_INFO_8822B(v))\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15)\n\n#define BIT_SHIFT_GTAB_ID_V1_8822B 12\n#define BIT_MASK_GTAB_ID_V1_8822B 0x7\n#define BIT_GTAB_ID_V1_8822B(x)                                                \\\n\t(((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)\n#define BITS_GTAB_ID_V1_8822B                                                  \\\n\t(BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B)\n#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B))\n#define BIT_GET_GTAB_ID_V1_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)\n#define BIT_SET_GTAB_ID_V1_8822B(x, v)                                         \\\n\t(BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v))\n\n#define BIT_SHIFT_AC4_PKT_INFO_8822B 0\n#define BIT_MASK_AC4_PKT_INFO_8822B 0xfff\n#define BIT_AC4_PKT_INFO_8822B(x)                                              \\\n\t(((x) & BIT_MASK_AC4_PKT_INFO_8822B) << BIT_SHIFT_AC4_PKT_INFO_8822B)\n#define BITS_AC4_PKT_INFO_8822B                                                \\\n\t(BIT_MASK_AC4_PKT_INFO_8822B << BIT_SHIFT_AC4_PKT_INFO_8822B)\n#define BIT_CLEAR_AC4_PKT_INFO_8822B(x) ((x) & (~BITS_AC4_PKT_INFO_8822B))\n#define BIT_GET_AC4_PKT_INFO_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC4_PKT_INFO_8822B) & BIT_MASK_AC4_PKT_INFO_8822B)\n#define BIT_SET_AC4_PKT_INFO_8822B(x, v)                                       \\\n\t(BIT_CLEAR_AC4_PKT_INFO_8822B(x) | BIT_AC4_PKT_INFO_8822B(v))\n\n/* 2 REG_Q6_Q7_INFO_8822B */\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31)\n\n#define BIT_SHIFT_GTAB_ID_8822B 28\n#define BIT_MASK_GTAB_ID_8822B 0x7\n#define BIT_GTAB_ID_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)\n#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B)\n#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B))\n#define BIT_GET_GTAB_ID_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)\n#define BIT_SET_GTAB_ID_8822B(x, v)                                            \\\n\t(BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v))\n\n#define BIT_SHIFT_AC7_PKT_INFO_8822B 16\n#define BIT_MASK_AC7_PKT_INFO_8822B 0xfff\n#define BIT_AC7_PKT_INFO_8822B(x)                                              \\\n\t(((x) & BIT_MASK_AC7_PKT_INFO_8822B) << BIT_SHIFT_AC7_PKT_INFO_8822B)\n#define BITS_AC7_PKT_INFO_8822B                                                \\\n\t(BIT_MASK_AC7_PKT_INFO_8822B << BIT_SHIFT_AC7_PKT_INFO_8822B)\n#define BIT_CLEAR_AC7_PKT_INFO_8822B(x) ((x) & (~BITS_AC7_PKT_INFO_8822B))\n#define BIT_GET_AC7_PKT_INFO_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC7_PKT_INFO_8822B) & BIT_MASK_AC7_PKT_INFO_8822B)\n#define BIT_SET_AC7_PKT_INFO_8822B(x, v)                                       \\\n\t(BIT_CLEAR_AC7_PKT_INFO_8822B(x) | BIT_AC7_PKT_INFO_8822B(v))\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15)\n\n#define BIT_SHIFT_GTAB_ID_V1_8822B 12\n#define BIT_MASK_GTAB_ID_V1_8822B 0x7\n#define BIT_GTAB_ID_V1_8822B(x)                                                \\\n\t(((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)\n#define BITS_GTAB_ID_V1_8822B                                                  \\\n\t(BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B)\n#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B))\n#define BIT_GET_GTAB_ID_V1_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)\n#define BIT_SET_GTAB_ID_V1_8822B(x, v)                                         \\\n\t(BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v))\n\n#define BIT_SHIFT_AC6_PKT_INFO_8822B 0\n#define BIT_MASK_AC6_PKT_INFO_8822B 0xfff\n#define BIT_AC6_PKT_INFO_8822B(x)                                              \\\n\t(((x) & BIT_MASK_AC6_PKT_INFO_8822B) << BIT_SHIFT_AC6_PKT_INFO_8822B)\n#define BITS_AC6_PKT_INFO_8822B                                                \\\n\t(BIT_MASK_AC6_PKT_INFO_8822B << BIT_SHIFT_AC6_PKT_INFO_8822B)\n#define BIT_CLEAR_AC6_PKT_INFO_8822B(x) ((x) & (~BITS_AC6_PKT_INFO_8822B))\n#define BIT_GET_AC6_PKT_INFO_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC6_PKT_INFO_8822B) & BIT_MASK_AC6_PKT_INFO_8822B)\n#define BIT_SET_AC6_PKT_INFO_8822B(x, v)                                       \\\n\t(BIT_CLEAR_AC6_PKT_INFO_8822B(x) | BIT_AC6_PKT_INFO_8822B(v))\n\n/* 2 REG_MGQ_HIQ_INFO_8822B */\n\n#define BIT_SHIFT_HIQ_PKT_INFO_8822B 16\n#define BIT_MASK_HIQ_PKT_INFO_8822B 0xfff\n#define BIT_HIQ_PKT_INFO_8822B(x)                                              \\\n\t(((x) & BIT_MASK_HIQ_PKT_INFO_8822B) << BIT_SHIFT_HIQ_PKT_INFO_8822B)\n#define BITS_HIQ_PKT_INFO_8822B                                                \\\n\t(BIT_MASK_HIQ_PKT_INFO_8822B << BIT_SHIFT_HIQ_PKT_INFO_8822B)\n#define BIT_CLEAR_HIQ_PKT_INFO_8822B(x) ((x) & (~BITS_HIQ_PKT_INFO_8822B))\n#define BIT_GET_HIQ_PKT_INFO_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_HIQ_PKT_INFO_8822B) & BIT_MASK_HIQ_PKT_INFO_8822B)\n#define BIT_SET_HIQ_PKT_INFO_8822B(x, v)                                       \\\n\t(BIT_CLEAR_HIQ_PKT_INFO_8822B(x) | BIT_HIQ_PKT_INFO_8822B(v))\n\n#define BIT_SHIFT_MGQ_PKT_INFO_8822B 0\n#define BIT_MASK_MGQ_PKT_INFO_8822B 0xfff\n#define BIT_MGQ_PKT_INFO_8822B(x)                                              \\\n\t(((x) & BIT_MASK_MGQ_PKT_INFO_8822B) << BIT_SHIFT_MGQ_PKT_INFO_8822B)\n#define BITS_MGQ_PKT_INFO_8822B                                                \\\n\t(BIT_MASK_MGQ_PKT_INFO_8822B << BIT_SHIFT_MGQ_PKT_INFO_8822B)\n#define BIT_CLEAR_MGQ_PKT_INFO_8822B(x) ((x) & (~BITS_MGQ_PKT_INFO_8822B))\n#define BIT_GET_MGQ_PKT_INFO_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_MGQ_PKT_INFO_8822B) & BIT_MASK_MGQ_PKT_INFO_8822B)\n#define BIT_SET_MGQ_PKT_INFO_8822B(x, v)                                       \\\n\t(BIT_CLEAR_MGQ_PKT_INFO_8822B(x) | BIT_MGQ_PKT_INFO_8822B(v))\n\n/* 2 REG_CMDQ_BCNQ_INFO_8822B */\n\n#define BIT_SHIFT_CMDQ_PKT_INFO_8822B 16\n#define BIT_MASK_CMDQ_PKT_INFO_8822B 0xfff\n#define BIT_CMDQ_PKT_INFO_8822B(x)                                             \\\n\t(((x) & BIT_MASK_CMDQ_PKT_INFO_8822B) << BIT_SHIFT_CMDQ_PKT_INFO_8822B)\n#define BITS_CMDQ_PKT_INFO_8822B                                               \\\n\t(BIT_MASK_CMDQ_PKT_INFO_8822B << BIT_SHIFT_CMDQ_PKT_INFO_8822B)\n#define BIT_CLEAR_CMDQ_PKT_INFO_8822B(x) ((x) & (~BITS_CMDQ_PKT_INFO_8822B))\n#define BIT_GET_CMDQ_PKT_INFO_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8822B) & BIT_MASK_CMDQ_PKT_INFO_8822B)\n#define BIT_SET_CMDQ_PKT_INFO_8822B(x, v)                                      \\\n\t(BIT_CLEAR_CMDQ_PKT_INFO_8822B(x) | BIT_CMDQ_PKT_INFO_8822B(v))\n\n#define BIT_SHIFT_BCNQ_PKT_INFO_8822B 0\n#define BIT_MASK_BCNQ_PKT_INFO_8822B 0xfff\n#define BIT_BCNQ_PKT_INFO_8822B(x)                                             \\\n\t(((x) & BIT_MASK_BCNQ_PKT_INFO_8822B) << BIT_SHIFT_BCNQ_PKT_INFO_8822B)\n#define BITS_BCNQ_PKT_INFO_8822B                                               \\\n\t(BIT_MASK_BCNQ_PKT_INFO_8822B << BIT_SHIFT_BCNQ_PKT_INFO_8822B)\n#define BIT_CLEAR_BCNQ_PKT_INFO_8822B(x) ((x) & (~BITS_BCNQ_PKT_INFO_8822B))\n#define BIT_GET_BCNQ_PKT_INFO_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8822B) & BIT_MASK_BCNQ_PKT_INFO_8822B)\n#define BIT_SET_BCNQ_PKT_INFO_8822B(x, v)                                      \\\n\t(BIT_CLEAR_BCNQ_PKT_INFO_8822B(x) | BIT_BCNQ_PKT_INFO_8822B(v))\n\n/* 2 REG_USEREG_SETTING_8822B */\n#define BIT_NDPA_USEREG_8822B BIT(21)\n\n#define BIT_SHIFT_RETRY_USEREG_8822B 19\n#define BIT_MASK_RETRY_USEREG_8822B 0x3\n#define BIT_RETRY_USEREG_8822B(x)                                              \\\n\t(((x) & BIT_MASK_RETRY_USEREG_8822B) << BIT_SHIFT_RETRY_USEREG_8822B)\n#define BITS_RETRY_USEREG_8822B                                                \\\n\t(BIT_MASK_RETRY_USEREG_8822B << BIT_SHIFT_RETRY_USEREG_8822B)\n#define BIT_CLEAR_RETRY_USEREG_8822B(x) ((x) & (~BITS_RETRY_USEREG_8822B))\n#define BIT_GET_RETRY_USEREG_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RETRY_USEREG_8822B) & BIT_MASK_RETRY_USEREG_8822B)\n#define BIT_SET_RETRY_USEREG_8822B(x, v)                                       \\\n\t(BIT_CLEAR_RETRY_USEREG_8822B(x) | BIT_RETRY_USEREG_8822B(v))\n\n#define BIT_SHIFT_TRYPKT_USEREG_8822B 17\n#define BIT_MASK_TRYPKT_USEREG_8822B 0x3\n#define BIT_TRYPKT_USEREG_8822B(x)                                             \\\n\t(((x) & BIT_MASK_TRYPKT_USEREG_8822B) << BIT_SHIFT_TRYPKT_USEREG_8822B)\n#define BITS_TRYPKT_USEREG_8822B                                               \\\n\t(BIT_MASK_TRYPKT_USEREG_8822B << BIT_SHIFT_TRYPKT_USEREG_8822B)\n#define BIT_CLEAR_TRYPKT_USEREG_8822B(x) ((x) & (~BITS_TRYPKT_USEREG_8822B))\n#define BIT_GET_TRYPKT_USEREG_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TRYPKT_USEREG_8822B) & BIT_MASK_TRYPKT_USEREG_8822B)\n#define BIT_SET_TRYPKT_USEREG_8822B(x, v)                                      \\\n\t(BIT_CLEAR_TRYPKT_USEREG_8822B(x) | BIT_TRYPKT_USEREG_8822B(v))\n\n#define BIT_CTLPKT_USEREG_8822B BIT(16)\n\n/* 2 REG_AESIV_SETTING_8822B */\n\n#define BIT_SHIFT_AESIV_OFFSET_8822B 0\n#define BIT_MASK_AESIV_OFFSET_8822B 0xfff\n#define BIT_AESIV_OFFSET_8822B(x)                                              \\\n\t(((x) & BIT_MASK_AESIV_OFFSET_8822B) << BIT_SHIFT_AESIV_OFFSET_8822B)\n#define BITS_AESIV_OFFSET_8822B                                                \\\n\t(BIT_MASK_AESIV_OFFSET_8822B << BIT_SHIFT_AESIV_OFFSET_8822B)\n#define BIT_CLEAR_AESIV_OFFSET_8822B(x) ((x) & (~BITS_AESIV_OFFSET_8822B))\n#define BIT_GET_AESIV_OFFSET_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_AESIV_OFFSET_8822B) & BIT_MASK_AESIV_OFFSET_8822B)\n#define BIT_SET_AESIV_OFFSET_8822B(x, v)                                       \\\n\t(BIT_CLEAR_AESIV_OFFSET_8822B(x) | BIT_AESIV_OFFSET_8822B(v))\n\n/* 2 REG_BF0_TIME_SETTING_8822B */\n#define BIT_BF0_TIMER_SET_8822B BIT(31)\n#define BIT_BF0_TIMER_CLR_8822B BIT(30)\n#define BIT_BF0_UPDATE_EN_8822B BIT(29)\n#define BIT_BF0_TIMER_EN_8822B BIT(28)\n\n#define BIT_SHIFT_BF0_PRETIME_OVER_8822B 16\n#define BIT_MASK_BF0_PRETIME_OVER_8822B 0xfff\n#define BIT_BF0_PRETIME_OVER_8822B(x)                                          \\\n\t(((x) & BIT_MASK_BF0_PRETIME_OVER_8822B)                               \\\n\t << BIT_SHIFT_BF0_PRETIME_OVER_8822B)\n#define BITS_BF0_PRETIME_OVER_8822B                                            \\\n\t(BIT_MASK_BF0_PRETIME_OVER_8822B << BIT_SHIFT_BF0_PRETIME_OVER_8822B)\n#define BIT_CLEAR_BF0_PRETIME_OVER_8822B(x)                                    \\\n\t((x) & (~BITS_BF0_PRETIME_OVER_8822B))\n#define BIT_GET_BF0_PRETIME_OVER_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8822B) &                           \\\n\t BIT_MASK_BF0_PRETIME_OVER_8822B)\n#define BIT_SET_BF0_PRETIME_OVER_8822B(x, v)                                   \\\n\t(BIT_CLEAR_BF0_PRETIME_OVER_8822B(x) | BIT_BF0_PRETIME_OVER_8822B(v))\n\n#define BIT_SHIFT_BF0_LIFETIME_8822B 0\n#define BIT_MASK_BF0_LIFETIME_8822B 0xffff\n#define BIT_BF0_LIFETIME_8822B(x)                                              \\\n\t(((x) & BIT_MASK_BF0_LIFETIME_8822B) << BIT_SHIFT_BF0_LIFETIME_8822B)\n#define BITS_BF0_LIFETIME_8822B                                                \\\n\t(BIT_MASK_BF0_LIFETIME_8822B << BIT_SHIFT_BF0_LIFETIME_8822B)\n#define BIT_CLEAR_BF0_LIFETIME_8822B(x) ((x) & (~BITS_BF0_LIFETIME_8822B))\n#define BIT_GET_BF0_LIFETIME_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BF0_LIFETIME_8822B) & BIT_MASK_BF0_LIFETIME_8822B)\n#define BIT_SET_BF0_LIFETIME_8822B(x, v)                                       \\\n\t(BIT_CLEAR_BF0_LIFETIME_8822B(x) | BIT_BF0_LIFETIME_8822B(v))\n\n/* 2 REG_BF1_TIME_SETTING_8822B */\n#define BIT_BF1_TIMER_SET_8822B BIT(31)\n#define BIT_BF1_TIMER_CLR_8822B BIT(30)\n#define BIT_BF1_UPDATE_EN_8822B BIT(29)\n#define BIT_BF1_TIMER_EN_8822B BIT(28)\n\n#define BIT_SHIFT_BF1_PRETIME_OVER_8822B 16\n#define BIT_MASK_BF1_PRETIME_OVER_8822B 0xfff\n#define BIT_BF1_PRETIME_OVER_8822B(x)                                          \\\n\t(((x) & BIT_MASK_BF1_PRETIME_OVER_8822B)                               \\\n\t << BIT_SHIFT_BF1_PRETIME_OVER_8822B)\n#define BITS_BF1_PRETIME_OVER_8822B                                            \\\n\t(BIT_MASK_BF1_PRETIME_OVER_8822B << BIT_SHIFT_BF1_PRETIME_OVER_8822B)\n#define BIT_CLEAR_BF1_PRETIME_OVER_8822B(x)                                    \\\n\t((x) & (~BITS_BF1_PRETIME_OVER_8822B))\n#define BIT_GET_BF1_PRETIME_OVER_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8822B) &                           \\\n\t BIT_MASK_BF1_PRETIME_OVER_8822B)\n#define BIT_SET_BF1_PRETIME_OVER_8822B(x, v)                                   \\\n\t(BIT_CLEAR_BF1_PRETIME_OVER_8822B(x) | BIT_BF1_PRETIME_OVER_8822B(v))\n\n#define BIT_SHIFT_BF1_LIFETIME_8822B 0\n#define BIT_MASK_BF1_LIFETIME_8822B 0xffff\n#define BIT_BF1_LIFETIME_8822B(x)                                              \\\n\t(((x) & BIT_MASK_BF1_LIFETIME_8822B) << BIT_SHIFT_BF1_LIFETIME_8822B)\n#define BITS_BF1_LIFETIME_8822B                                                \\\n\t(BIT_MASK_BF1_LIFETIME_8822B << BIT_SHIFT_BF1_LIFETIME_8822B)\n#define BIT_CLEAR_BF1_LIFETIME_8822B(x) ((x) & (~BITS_BF1_LIFETIME_8822B))\n#define BIT_GET_BF1_LIFETIME_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BF1_LIFETIME_8822B) & BIT_MASK_BF1_LIFETIME_8822B)\n#define BIT_SET_BF1_LIFETIME_8822B(x, v)                                       \\\n\t(BIT_CLEAR_BF1_LIFETIME_8822B(x) | BIT_BF1_LIFETIME_8822B(v))\n\n/* 2 REG_BF_TIMEOUT_EN_8822B */\n#define BIT_EN_VHT_LDPC_8822B BIT(9)\n#define BIT_EN_HT_LDPC_8822B BIT(8)\n#define BIT_BF1_TIMEOUT_EN_8822B BIT(1)\n#define BIT_BF0_TIMEOUT_EN_8822B BIT(0)\n\n/* 2 REG_MACID_RELEASE0_8822B */\n\n#define BIT_SHIFT_MACID31_0_RELEASE_8822B 0\n#define BIT_MASK_MACID31_0_RELEASE_8822B 0xffffffffL\n#define BIT_MACID31_0_RELEASE_8822B(x)                                         \\\n\t(((x) & BIT_MASK_MACID31_0_RELEASE_8822B)                              \\\n\t << BIT_SHIFT_MACID31_0_RELEASE_8822B)\n#define BITS_MACID31_0_RELEASE_8822B                                           \\\n\t(BIT_MASK_MACID31_0_RELEASE_8822B << BIT_SHIFT_MACID31_0_RELEASE_8822B)\n#define BIT_CLEAR_MACID31_0_RELEASE_8822B(x)                                   \\\n\t((x) & (~BITS_MACID31_0_RELEASE_8822B))\n#define BIT_GET_MACID31_0_RELEASE_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_MACID31_0_RELEASE_8822B) &                          \\\n\t BIT_MASK_MACID31_0_RELEASE_8822B)\n#define BIT_SET_MACID31_0_RELEASE_8822B(x, v)                                  \\\n\t(BIT_CLEAR_MACID31_0_RELEASE_8822B(x) | BIT_MACID31_0_RELEASE_8822B(v))\n\n/* 2 REG_MACID_RELEASE1_8822B */\n\n#define BIT_SHIFT_MACID63_32_RELEASE_8822B 0\n#define BIT_MASK_MACID63_32_RELEASE_8822B 0xffffffffL\n#define BIT_MACID63_32_RELEASE_8822B(x)                                        \\\n\t(((x) & BIT_MASK_MACID63_32_RELEASE_8822B)                             \\\n\t << BIT_SHIFT_MACID63_32_RELEASE_8822B)\n#define BITS_MACID63_32_RELEASE_8822B                                          \\\n\t(BIT_MASK_MACID63_32_RELEASE_8822B                                     \\\n\t << BIT_SHIFT_MACID63_32_RELEASE_8822B)\n#define BIT_CLEAR_MACID63_32_RELEASE_8822B(x)                                  \\\n\t((x) & (~BITS_MACID63_32_RELEASE_8822B))\n#define BIT_GET_MACID63_32_RELEASE_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACID63_32_RELEASE_8822B) &                         \\\n\t BIT_MASK_MACID63_32_RELEASE_8822B)\n#define BIT_SET_MACID63_32_RELEASE_8822B(x, v)                                 \\\n\t(BIT_CLEAR_MACID63_32_RELEASE_8822B(x) |                               \\\n\t BIT_MACID63_32_RELEASE_8822B(v))\n\n/* 2 REG_MACID_RELEASE2_8822B */\n\n#define BIT_SHIFT_MACID95_64_RELEASE_8822B 0\n#define BIT_MASK_MACID95_64_RELEASE_8822B 0xffffffffL\n#define BIT_MACID95_64_RELEASE_8822B(x)                                        \\\n\t(((x) & BIT_MASK_MACID95_64_RELEASE_8822B)                             \\\n\t << BIT_SHIFT_MACID95_64_RELEASE_8822B)\n#define BITS_MACID95_64_RELEASE_8822B                                          \\\n\t(BIT_MASK_MACID95_64_RELEASE_8822B                                     \\\n\t << BIT_SHIFT_MACID95_64_RELEASE_8822B)\n#define BIT_CLEAR_MACID95_64_RELEASE_8822B(x)                                  \\\n\t((x) & (~BITS_MACID95_64_RELEASE_8822B))\n#define BIT_GET_MACID95_64_RELEASE_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACID95_64_RELEASE_8822B) &                         \\\n\t BIT_MASK_MACID95_64_RELEASE_8822B)\n#define BIT_SET_MACID95_64_RELEASE_8822B(x, v)                                 \\\n\t(BIT_CLEAR_MACID95_64_RELEASE_8822B(x) |                               \\\n\t BIT_MACID95_64_RELEASE_8822B(v))\n\n/* 2 REG_MACID_RELEASE3_8822B */\n\n#define BIT_SHIFT_MACID127_96_RELEASE_8822B 0\n#define BIT_MASK_MACID127_96_RELEASE_8822B 0xffffffffL\n#define BIT_MACID127_96_RELEASE_8822B(x)                                       \\\n\t(((x) & BIT_MASK_MACID127_96_RELEASE_8822B)                            \\\n\t << BIT_SHIFT_MACID127_96_RELEASE_8822B)\n#define BITS_MACID127_96_RELEASE_8822B                                         \\\n\t(BIT_MASK_MACID127_96_RELEASE_8822B                                    \\\n\t << BIT_SHIFT_MACID127_96_RELEASE_8822B)\n#define BIT_CLEAR_MACID127_96_RELEASE_8822B(x)                                 \\\n\t((x) & (~BITS_MACID127_96_RELEASE_8822B))\n#define BIT_GET_MACID127_96_RELEASE_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_MACID127_96_RELEASE_8822B) &                        \\\n\t BIT_MASK_MACID127_96_RELEASE_8822B)\n#define BIT_SET_MACID127_96_RELEASE_8822B(x, v)                                \\\n\t(BIT_CLEAR_MACID127_96_RELEASE_8822B(x) |                              \\\n\t BIT_MACID127_96_RELEASE_8822B(v))\n\n/* 2 REG_MACID_RELEASE_SETTING_8822B */\n#define BIT_MACID_VALUE_8822B BIT(7)\n\n#define BIT_SHIFT_MACID_OFFSET_8822B 0\n#define BIT_MASK_MACID_OFFSET_8822B 0x7f\n#define BIT_MACID_OFFSET_8822B(x)                                              \\\n\t(((x) & BIT_MASK_MACID_OFFSET_8822B) << BIT_SHIFT_MACID_OFFSET_8822B)\n#define BITS_MACID_OFFSET_8822B                                                \\\n\t(BIT_MASK_MACID_OFFSET_8822B << BIT_SHIFT_MACID_OFFSET_8822B)\n#define BIT_CLEAR_MACID_OFFSET_8822B(x) ((x) & (~BITS_MACID_OFFSET_8822B))\n#define BIT_GET_MACID_OFFSET_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_MACID_OFFSET_8822B) & BIT_MASK_MACID_OFFSET_8822B)\n#define BIT_SET_MACID_OFFSET_8822B(x, v)                                       \\\n\t(BIT_CLEAR_MACID_OFFSET_8822B(x) | BIT_MACID_OFFSET_8822B(v))\n\n/* 2 REG_FAST_EDCA_VOVI_SETTING_8822B */\n\n#define BIT_SHIFT_VI_FAST_EDCA_TO_8822B 24\n#define BIT_MASK_VI_FAST_EDCA_TO_8822B 0xff\n#define BIT_VI_FAST_EDCA_TO_8822B(x)                                           \\\n\t(((x) & BIT_MASK_VI_FAST_EDCA_TO_8822B)                                \\\n\t << BIT_SHIFT_VI_FAST_EDCA_TO_8822B)\n#define BITS_VI_FAST_EDCA_TO_8822B                                             \\\n\t(BIT_MASK_VI_FAST_EDCA_TO_8822B << BIT_SHIFT_VI_FAST_EDCA_TO_8822B)\n#define BIT_CLEAR_VI_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8822B))\n#define BIT_GET_VI_FAST_EDCA_TO_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8822B) &                            \\\n\t BIT_MASK_VI_FAST_EDCA_TO_8822B)\n#define BIT_SET_VI_FAST_EDCA_TO_8822B(x, v)                                    \\\n\t(BIT_CLEAR_VI_FAST_EDCA_TO_8822B(x) | BIT_VI_FAST_EDCA_TO_8822B(v))\n\n#define BIT_VI_THRESHOLD_SEL_8822B BIT(23)\n\n#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B 16\n#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B 0x7f\n#define BIT_VI_FAST_EDCA_PKT_TH_8822B(x)                                       \\\n\t(((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B)                            \\\n\t << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B)\n#define BITS_VI_FAST_EDCA_PKT_TH_8822B                                         \\\n\t(BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B                                    \\\n\t << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B)\n#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822B(x)                                 \\\n\t((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8822B))\n#define BIT_GET_VI_FAST_EDCA_PKT_TH_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B) &                        \\\n\t BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B)\n#define BIT_SET_VI_FAST_EDCA_PKT_TH_8822B(x, v)                                \\\n\t(BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822B(x) |                              \\\n\t BIT_VI_FAST_EDCA_PKT_TH_8822B(v))\n\n#define BIT_SHIFT_VO_FAST_EDCA_TO_8822B 8\n#define BIT_MASK_VO_FAST_EDCA_TO_8822B 0xff\n#define BIT_VO_FAST_EDCA_TO_8822B(x)                                           \\\n\t(((x) & BIT_MASK_VO_FAST_EDCA_TO_8822B)                                \\\n\t << BIT_SHIFT_VO_FAST_EDCA_TO_8822B)\n#define BITS_VO_FAST_EDCA_TO_8822B                                             \\\n\t(BIT_MASK_VO_FAST_EDCA_TO_8822B << BIT_SHIFT_VO_FAST_EDCA_TO_8822B)\n#define BIT_CLEAR_VO_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8822B))\n#define BIT_GET_VO_FAST_EDCA_TO_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8822B) &                            \\\n\t BIT_MASK_VO_FAST_EDCA_TO_8822B)\n#define BIT_SET_VO_FAST_EDCA_TO_8822B(x, v)                                    \\\n\t(BIT_CLEAR_VO_FAST_EDCA_TO_8822B(x) | BIT_VO_FAST_EDCA_TO_8822B(v))\n\n#define BIT_VO_THRESHOLD_SEL_8822B BIT(7)\n\n#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B 0\n#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B 0x7f\n#define BIT_VO_FAST_EDCA_PKT_TH_8822B(x)                                       \\\n\t(((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B)                            \\\n\t << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B)\n#define BITS_VO_FAST_EDCA_PKT_TH_8822B                                         \\\n\t(BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B                                    \\\n\t << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B)\n#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822B(x)                                 \\\n\t((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8822B))\n#define BIT_GET_VO_FAST_EDCA_PKT_TH_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B) &                        \\\n\t BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B)\n#define BIT_SET_VO_FAST_EDCA_PKT_TH_8822B(x, v)                                \\\n\t(BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822B(x) |                              \\\n\t BIT_VO_FAST_EDCA_PKT_TH_8822B(v))\n\n/* 2 REG_FAST_EDCA_BEBK_SETTING_8822B */\n\n#define BIT_SHIFT_BK_FAST_EDCA_TO_8822B 24\n#define BIT_MASK_BK_FAST_EDCA_TO_8822B 0xff\n#define BIT_BK_FAST_EDCA_TO_8822B(x)                                           \\\n\t(((x) & BIT_MASK_BK_FAST_EDCA_TO_8822B)                                \\\n\t << BIT_SHIFT_BK_FAST_EDCA_TO_8822B)\n#define BITS_BK_FAST_EDCA_TO_8822B                                             \\\n\t(BIT_MASK_BK_FAST_EDCA_TO_8822B << BIT_SHIFT_BK_FAST_EDCA_TO_8822B)\n#define BIT_CLEAR_BK_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8822B))\n#define BIT_GET_BK_FAST_EDCA_TO_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8822B) &                            \\\n\t BIT_MASK_BK_FAST_EDCA_TO_8822B)\n#define BIT_SET_BK_FAST_EDCA_TO_8822B(x, v)                                    \\\n\t(BIT_CLEAR_BK_FAST_EDCA_TO_8822B(x) | BIT_BK_FAST_EDCA_TO_8822B(v))\n\n#define BIT_BK_THRESHOLD_SEL_8822B BIT(23)\n\n#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B 16\n#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B 0x7f\n#define BIT_BK_FAST_EDCA_PKT_TH_8822B(x)                                       \\\n\t(((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B)                            \\\n\t << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B)\n#define BITS_BK_FAST_EDCA_PKT_TH_8822B                                         \\\n\t(BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B                                    \\\n\t << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B)\n#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822B(x)                                 \\\n\t((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8822B))\n#define BIT_GET_BK_FAST_EDCA_PKT_TH_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B) &                        \\\n\t BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B)\n#define BIT_SET_BK_FAST_EDCA_PKT_TH_8822B(x, v)                                \\\n\t(BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822B(x) |                              \\\n\t BIT_BK_FAST_EDCA_PKT_TH_8822B(v))\n\n#define BIT_SHIFT_BE_FAST_EDCA_TO_8822B 8\n#define BIT_MASK_BE_FAST_EDCA_TO_8822B 0xff\n#define BIT_BE_FAST_EDCA_TO_8822B(x)                                           \\\n\t(((x) & BIT_MASK_BE_FAST_EDCA_TO_8822B)                                \\\n\t << BIT_SHIFT_BE_FAST_EDCA_TO_8822B)\n#define BITS_BE_FAST_EDCA_TO_8822B                                             \\\n\t(BIT_MASK_BE_FAST_EDCA_TO_8822B << BIT_SHIFT_BE_FAST_EDCA_TO_8822B)\n#define BIT_CLEAR_BE_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8822B))\n#define BIT_GET_BE_FAST_EDCA_TO_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8822B) &                            \\\n\t BIT_MASK_BE_FAST_EDCA_TO_8822B)\n#define BIT_SET_BE_FAST_EDCA_TO_8822B(x, v)                                    \\\n\t(BIT_CLEAR_BE_FAST_EDCA_TO_8822B(x) | BIT_BE_FAST_EDCA_TO_8822B(v))\n\n#define BIT_BE_THRESHOLD_SEL_8822B BIT(7)\n\n#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B 0\n#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B 0x7f\n#define BIT_BE_FAST_EDCA_PKT_TH_8822B(x)                                       \\\n\t(((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B)                            \\\n\t << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B)\n#define BITS_BE_FAST_EDCA_PKT_TH_8822B                                         \\\n\t(BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B                                    \\\n\t << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B)\n#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822B(x)                                 \\\n\t((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8822B))\n#define BIT_GET_BE_FAST_EDCA_PKT_TH_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B) &                        \\\n\t BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B)\n#define BIT_SET_BE_FAST_EDCA_PKT_TH_8822B(x, v)                                \\\n\t(BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822B(x) |                              \\\n\t BIT_BE_FAST_EDCA_PKT_TH_8822B(v))\n\n/* 2 REG_MACID_DROP0_8822B */\n\n#define BIT_SHIFT_MACID31_0_DROP_8822B 0\n#define BIT_MASK_MACID31_0_DROP_8822B 0xffffffffL\n#define BIT_MACID31_0_DROP_8822B(x)                                            \\\n\t(((x) & BIT_MASK_MACID31_0_DROP_8822B)                                 \\\n\t << BIT_SHIFT_MACID31_0_DROP_8822B)\n#define BITS_MACID31_0_DROP_8822B                                              \\\n\t(BIT_MASK_MACID31_0_DROP_8822B << BIT_SHIFT_MACID31_0_DROP_8822B)\n#define BIT_CLEAR_MACID31_0_DROP_8822B(x) ((x) & (~BITS_MACID31_0_DROP_8822B))\n#define BIT_GET_MACID31_0_DROP_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_MACID31_0_DROP_8822B) &                             \\\n\t BIT_MASK_MACID31_0_DROP_8822B)\n#define BIT_SET_MACID31_0_DROP_8822B(x, v)                                     \\\n\t(BIT_CLEAR_MACID31_0_DROP_8822B(x) | BIT_MACID31_0_DROP_8822B(v))\n\n/* 2 REG_MACID_DROP1_8822B */\n\n#define BIT_SHIFT_MACID63_32_DROP_8822B 0\n#define BIT_MASK_MACID63_32_DROP_8822B 0xffffffffL\n#define BIT_MACID63_32_DROP_8822B(x)                                           \\\n\t(((x) & BIT_MASK_MACID63_32_DROP_8822B)                                \\\n\t << BIT_SHIFT_MACID63_32_DROP_8822B)\n#define BITS_MACID63_32_DROP_8822B                                             \\\n\t(BIT_MASK_MACID63_32_DROP_8822B << BIT_SHIFT_MACID63_32_DROP_8822B)\n#define BIT_CLEAR_MACID63_32_DROP_8822B(x) ((x) & (~BITS_MACID63_32_DROP_8822B))\n#define BIT_GET_MACID63_32_DROP_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_MACID63_32_DROP_8822B) &                            \\\n\t BIT_MASK_MACID63_32_DROP_8822B)\n#define BIT_SET_MACID63_32_DROP_8822B(x, v)                                    \\\n\t(BIT_CLEAR_MACID63_32_DROP_8822B(x) | BIT_MACID63_32_DROP_8822B(v))\n\n/* 2 REG_MACID_DROP2_8822B */\n\n#define BIT_SHIFT_MACID95_64_DROP_8822B 0\n#define BIT_MASK_MACID95_64_DROP_8822B 0xffffffffL\n#define BIT_MACID95_64_DROP_8822B(x)                                           \\\n\t(((x) & BIT_MASK_MACID95_64_DROP_8822B)                                \\\n\t << BIT_SHIFT_MACID95_64_DROP_8822B)\n#define BITS_MACID95_64_DROP_8822B                                             \\\n\t(BIT_MASK_MACID95_64_DROP_8822B << BIT_SHIFT_MACID95_64_DROP_8822B)\n#define BIT_CLEAR_MACID95_64_DROP_8822B(x) ((x) & (~BITS_MACID95_64_DROP_8822B))\n#define BIT_GET_MACID95_64_DROP_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_MACID95_64_DROP_8822B) &                            \\\n\t BIT_MASK_MACID95_64_DROP_8822B)\n#define BIT_SET_MACID95_64_DROP_8822B(x, v)                                    \\\n\t(BIT_CLEAR_MACID95_64_DROP_8822B(x) | BIT_MACID95_64_DROP_8822B(v))\n\n/* 2 REG_MACID_DROP3_8822B */\n\n#define BIT_SHIFT_MACID127_96_DROP_8822B 0\n#define BIT_MASK_MACID127_96_DROP_8822B 0xffffffffL\n#define BIT_MACID127_96_DROP_8822B(x)                                          \\\n\t(((x) & BIT_MASK_MACID127_96_DROP_8822B)                               \\\n\t << BIT_SHIFT_MACID127_96_DROP_8822B)\n#define BITS_MACID127_96_DROP_8822B                                            \\\n\t(BIT_MASK_MACID127_96_DROP_8822B << BIT_SHIFT_MACID127_96_DROP_8822B)\n#define BIT_CLEAR_MACID127_96_DROP_8822B(x)                                    \\\n\t((x) & (~BITS_MACID127_96_DROP_8822B))\n#define BIT_GET_MACID127_96_DROP_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_MACID127_96_DROP_8822B) &                           \\\n\t BIT_MASK_MACID127_96_DROP_8822B)\n#define BIT_SET_MACID127_96_DROP_8822B(x, v)                                   \\\n\t(BIT_CLEAR_MACID127_96_DROP_8822B(x) | BIT_MACID127_96_DROP_8822B(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8822B */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_0_8822B(x)                                 \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B)                      \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B)\n#define BITS_R_MACID_RELEASE_SUCCESS_0_8822B                                   \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B                              \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822B(x)                           \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8822B))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8822B(x)                             \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B) &                  \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8822B(x, v)                          \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822B(x) |                        \\\n\t BIT_R_MACID_RELEASE_SUCCESS_0_8822B(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8822B */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_1_8822B(x)                                 \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B)                      \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B)\n#define BITS_R_MACID_RELEASE_SUCCESS_1_8822B                                   \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B                              \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822B(x)                           \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8822B))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8822B(x)                             \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B) &                  \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8822B(x, v)                          \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822B(x) |                        \\\n\t BIT_R_MACID_RELEASE_SUCCESS_1_8822B(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8822B */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_2_8822B(x)                                 \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B)                      \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B)\n#define BITS_R_MACID_RELEASE_SUCCESS_2_8822B                                   \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B                              \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822B(x)                           \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8822B))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8822B(x)                             \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B) &                  \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8822B(x, v)                          \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822B(x) |                        \\\n\t BIT_R_MACID_RELEASE_SUCCESS_2_8822B(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8822B */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_3_8822B(x)                                 \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B)                      \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B)\n#define BITS_R_MACID_RELEASE_SUCCESS_3_8822B                                   \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B                              \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822B(x)                           \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8822B))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8822B(x)                             \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B) &                  \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8822B(x, v)                          \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822B(x) |                        \\\n\t BIT_R_MACID_RELEASE_SUCCESS_3_8822B(v))\n\n/* 2 REG_MGG_FIFO_CRTL_8822B */\n#define BIT_R_MGG_FIFO_EN_8822B BIT(31)\n\n#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B 28\n#define BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B 0x7\n#define BIT_R_MGG_FIFO_PG_SIZE_8822B(x)                                        \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B)                             \\\n\t << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B)\n#define BITS_R_MGG_FIFO_PG_SIZE_8822B                                          \\\n\t(BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B                                     \\\n\t << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B)\n#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8822B(x)                                  \\\n\t((x) & (~BITS_R_MGG_FIFO_PG_SIZE_8822B))\n#define BIT_GET_R_MGG_FIFO_PG_SIZE_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B) &                         \\\n\t BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B)\n#define BIT_SET_R_MGG_FIFO_PG_SIZE_8822B(x, v)                                 \\\n\t(BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8822B(x) |                               \\\n\t BIT_R_MGG_FIFO_PG_SIZE_8822B(v))\n\n#define BIT_SHIFT_R_MGG_FIFO_START_PG_8822B 16\n#define BIT_MASK_R_MGG_FIFO_START_PG_8822B 0xfff\n#define BIT_R_MGG_FIFO_START_PG_8822B(x)                                       \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_START_PG_8822B)                            \\\n\t << BIT_SHIFT_R_MGG_FIFO_START_PG_8822B)\n#define BITS_R_MGG_FIFO_START_PG_8822B                                         \\\n\t(BIT_MASK_R_MGG_FIFO_START_PG_8822B                                    \\\n\t << BIT_SHIFT_R_MGG_FIFO_START_PG_8822B)\n#define BIT_CLEAR_R_MGG_FIFO_START_PG_8822B(x)                                 \\\n\t((x) & (~BITS_R_MGG_FIFO_START_PG_8822B))\n#define BIT_GET_R_MGG_FIFO_START_PG_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8822B) &                        \\\n\t BIT_MASK_R_MGG_FIFO_START_PG_8822B)\n#define BIT_SET_R_MGG_FIFO_START_PG_8822B(x, v)                                \\\n\t(BIT_CLEAR_R_MGG_FIFO_START_PG_8822B(x) |                              \\\n\t BIT_R_MGG_FIFO_START_PG_8822B(v))\n\n#define BIT_SHIFT_R_MGG_FIFO_SIZE_8822B 14\n#define BIT_MASK_R_MGG_FIFO_SIZE_8822B 0x3\n#define BIT_R_MGG_FIFO_SIZE_8822B(x)                                           \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_SIZE_8822B)                                \\\n\t << BIT_SHIFT_R_MGG_FIFO_SIZE_8822B)\n#define BITS_R_MGG_FIFO_SIZE_8822B                                             \\\n\t(BIT_MASK_R_MGG_FIFO_SIZE_8822B << BIT_SHIFT_R_MGG_FIFO_SIZE_8822B)\n#define BIT_CLEAR_R_MGG_FIFO_SIZE_8822B(x) ((x) & (~BITS_R_MGG_FIFO_SIZE_8822B))\n#define BIT_GET_R_MGG_FIFO_SIZE_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8822B) &                            \\\n\t BIT_MASK_R_MGG_FIFO_SIZE_8822B)\n#define BIT_SET_R_MGG_FIFO_SIZE_8822B(x, v)                                    \\\n\t(BIT_CLEAR_R_MGG_FIFO_SIZE_8822B(x) | BIT_R_MGG_FIFO_SIZE_8822B(v))\n\n#define BIT_R_MGG_FIFO_PAUSE_8822B BIT(13)\n\n#define BIT_SHIFT_R_MGG_FIFO_RPTR_8822B 8\n#define BIT_MASK_R_MGG_FIFO_RPTR_8822B 0x1f\n#define BIT_R_MGG_FIFO_RPTR_8822B(x)                                           \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_RPTR_8822B)                                \\\n\t << BIT_SHIFT_R_MGG_FIFO_RPTR_8822B)\n#define BITS_R_MGG_FIFO_RPTR_8822B                                             \\\n\t(BIT_MASK_R_MGG_FIFO_RPTR_8822B << BIT_SHIFT_R_MGG_FIFO_RPTR_8822B)\n#define BIT_CLEAR_R_MGG_FIFO_RPTR_8822B(x) ((x) & (~BITS_R_MGG_FIFO_RPTR_8822B))\n#define BIT_GET_R_MGG_FIFO_RPTR_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8822B) &                            \\\n\t BIT_MASK_R_MGG_FIFO_RPTR_8822B)\n#define BIT_SET_R_MGG_FIFO_RPTR_8822B(x, v)                                    \\\n\t(BIT_CLEAR_R_MGG_FIFO_RPTR_8822B(x) | BIT_R_MGG_FIFO_RPTR_8822B(v))\n\n#define BIT_R_MGG_FIFO_OV_8822B BIT(7)\n#define BIT_R_MGG_FIFO_WPTR_ERROR_8822B BIT(6)\n#define BIT_R_EN_CPU_LIFETIME_8822B BIT(5)\n\n#define BIT_SHIFT_R_MGG_FIFO_WPTR_8822B 0\n#define BIT_MASK_R_MGG_FIFO_WPTR_8822B 0x1f\n#define BIT_R_MGG_FIFO_WPTR_8822B(x)                                           \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_WPTR_8822B)                                \\\n\t << BIT_SHIFT_R_MGG_FIFO_WPTR_8822B)\n#define BITS_R_MGG_FIFO_WPTR_8822B                                             \\\n\t(BIT_MASK_R_MGG_FIFO_WPTR_8822B << BIT_SHIFT_R_MGG_FIFO_WPTR_8822B)\n#define BIT_CLEAR_R_MGG_FIFO_WPTR_8822B(x) ((x) & (~BITS_R_MGG_FIFO_WPTR_8822B))\n#define BIT_GET_R_MGG_FIFO_WPTR_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8822B) &                            \\\n\t BIT_MASK_R_MGG_FIFO_WPTR_8822B)\n#define BIT_SET_R_MGG_FIFO_WPTR_8822B(x, v)                                    \\\n\t(BIT_CLEAR_R_MGG_FIFO_WPTR_8822B(x) | BIT_R_MGG_FIFO_WPTR_8822B(v))\n\n/* 2 REG_MGG_FIFO_INT_8822B */\n\n#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B 16\n#define BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B 0xffff\n#define BIT_R_MGG_FIFO_INT_FLAG_8822B(x)                                       \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B)                            \\\n\t << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B)\n#define BITS_R_MGG_FIFO_INT_FLAG_8822B                                         \\\n\t(BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B                                    \\\n\t << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B)\n#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8822B(x)                                 \\\n\t((x) & (~BITS_R_MGG_FIFO_INT_FLAG_8822B))\n#define BIT_GET_R_MGG_FIFO_INT_FLAG_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B) &                        \\\n\t BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B)\n#define BIT_SET_R_MGG_FIFO_INT_FLAG_8822B(x, v)                                \\\n\t(BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8822B(x) |                              \\\n\t BIT_R_MGG_FIFO_INT_FLAG_8822B(v))\n\n#define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B 0\n#define BIT_MASK_R_MGG_FIFO_INT_MASK_8822B 0xffff\n#define BIT_R_MGG_FIFO_INT_MASK_8822B(x)                                       \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8822B)                            \\\n\t << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B)\n#define BITS_R_MGG_FIFO_INT_MASK_8822B                                         \\\n\t(BIT_MASK_R_MGG_FIFO_INT_MASK_8822B                                    \\\n\t << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B)\n#define BIT_CLEAR_R_MGG_FIFO_INT_MASK_8822B(x)                                 \\\n\t((x) & (~BITS_R_MGG_FIFO_INT_MASK_8822B))\n#define BIT_GET_R_MGG_FIFO_INT_MASK_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B) &                        \\\n\t BIT_MASK_R_MGG_FIFO_INT_MASK_8822B)\n#define BIT_SET_R_MGG_FIFO_INT_MASK_8822B(x, v)                                \\\n\t(BIT_CLEAR_R_MGG_FIFO_INT_MASK_8822B(x) |                              \\\n\t BIT_R_MGG_FIFO_INT_MASK_8822B(v))\n\n/* 2 REG_MGG_FIFO_LIFETIME_8822B */\n\n#define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B 16\n#define BIT_MASK_R_MGG_FIFO_LIFETIME_8822B 0xffff\n#define BIT_R_MGG_FIFO_LIFETIME_8822B(x)                                       \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8822B)                            \\\n\t << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B)\n#define BITS_R_MGG_FIFO_LIFETIME_8822B                                         \\\n\t(BIT_MASK_R_MGG_FIFO_LIFETIME_8822B                                    \\\n\t << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B)\n#define BIT_CLEAR_R_MGG_FIFO_LIFETIME_8822B(x)                                 \\\n\t((x) & (~BITS_R_MGG_FIFO_LIFETIME_8822B))\n#define BIT_GET_R_MGG_FIFO_LIFETIME_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B) &                        \\\n\t BIT_MASK_R_MGG_FIFO_LIFETIME_8822B)\n#define BIT_SET_R_MGG_FIFO_LIFETIME_8822B(x, v)                                \\\n\t(BIT_CLEAR_R_MGG_FIFO_LIFETIME_8822B(x) |                              \\\n\t BIT_R_MGG_FIFO_LIFETIME_8822B(v))\n\n#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B 0\n#define BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B 0xffff\n#define BIT_R_MGG_FIFO_VALID_MAP_8822B(x)                                      \\\n\t(((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B)                           \\\n\t << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B)\n#define BITS_R_MGG_FIFO_VALID_MAP_8822B                                        \\\n\t(BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B                                   \\\n\t << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B)\n#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8822B(x)                                \\\n\t((x) & (~BITS_R_MGG_FIFO_VALID_MAP_8822B))\n#define BIT_GET_R_MGG_FIFO_VALID_MAP_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B) &                       \\\n\t BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B)\n#define BIT_SET_R_MGG_FIFO_VALID_MAP_8822B(x, v)                               \\\n\t(BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8822B(x) |                             \\\n\t BIT_R_MGG_FIFO_VALID_MAP_8822B(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0x7f\n#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x)                      \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B)           \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B)\n#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B                        \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B                   \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x)                \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x)                  \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) &       \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x, v)               \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) |             \\\n\t BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(v))\n\n/* 2 REG_SHCUT_SETTING_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_SHCUT_LLC_ETH_TYPE0_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_SHCUT_LLC_ETH_TYPE1_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_SHCUT_LLC_OUI0_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_SHCUT_LLC_OUI1_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_SHCUT_LLC_OUI2_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_SHCUT_LLC_OUI3_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_MU_TX_CTL_8822B */\n#define BIT_R_EN_REVERS_GTAB_8822B BIT(6)\n\n#define BIT_SHIFT_R_MU_TABLE_VALID_8822B 0\n#define BIT_MASK_R_MU_TABLE_VALID_8822B 0x3f\n#define BIT_R_MU_TABLE_VALID_8822B(x)                                          \\\n\t(((x) & BIT_MASK_R_MU_TABLE_VALID_8822B)                               \\\n\t << BIT_SHIFT_R_MU_TABLE_VALID_8822B)\n#define BITS_R_MU_TABLE_VALID_8822B                                            \\\n\t(BIT_MASK_R_MU_TABLE_VALID_8822B << BIT_SHIFT_R_MU_TABLE_VALID_8822B)\n#define BIT_CLEAR_R_MU_TABLE_VALID_8822B(x)                                    \\\n\t((x) & (~BITS_R_MU_TABLE_VALID_8822B))\n#define BIT_GET_R_MU_TABLE_VALID_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822B) &                           \\\n\t BIT_MASK_R_MU_TABLE_VALID_8822B)\n#define BIT_SET_R_MU_TABLE_VALID_8822B(x, v)                                   \\\n\t(BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) | BIT_R_MU_TABLE_VALID_8822B(v))\n\n/* 2 REG_MU_STA_GID_VLD_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0\n#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL\n#define BIT_R_MU_STA_GTAB_VALID_8822B(x)                                       \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B)                            \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)\n#define BITS_R_MU_STA_GTAB_VALID_8822B                                         \\\n\t(BIT_MASK_R_MU_STA_GTAB_VALID_8822B                                    \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)\n#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x)                                 \\\n\t((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B))\n#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) &                        \\\n\t BIT_MASK_R_MU_STA_GTAB_VALID_8822B)\n#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v)                                \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) |                              \\\n\t BIT_R_MU_STA_GTAB_VALID_8822B(v))\n\n#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0\n#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL\n#define BIT_R_MU_STA_GTAB_VALID_8822B(x)                                       \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B)                            \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)\n#define BITS_R_MU_STA_GTAB_VALID_8822B                                         \\\n\t(BIT_MASK_R_MU_STA_GTAB_VALID_8822B                                    \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)\n#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x)                                 \\\n\t((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B))\n#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) &                        \\\n\t BIT_MASK_R_MU_STA_GTAB_VALID_8822B)\n#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v)                                \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) |                              \\\n\t BIT_R_MU_STA_GTAB_VALID_8822B(v))\n\n/* 2 REG_MU_STA_USER_POS_INFO_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0\n#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL\n#define BIT_R_MU_STA_GTAB_POSITION_8822B(x)                                    \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)                         \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)\n#define BITS_R_MU_STA_GTAB_POSITION_8822B                                      \\\n\t(BIT_MASK_R_MU_STA_GTAB_POSITION_8822B                                 \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)\n#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x)                              \\\n\t((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B))\n#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x)                                \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) &                     \\\n\t BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)\n#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v)                             \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) |                           \\\n\t BIT_R_MU_STA_GTAB_POSITION_8822B(v))\n\n#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0\n#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL\n#define BIT_R_MU_STA_GTAB_POSITION_8822B(x)                                    \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)                         \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)\n#define BITS_R_MU_STA_GTAB_POSITION_8822B                                      \\\n\t(BIT_MASK_R_MU_STA_GTAB_POSITION_8822B                                 \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)\n#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x)                              \\\n\t((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B))\n#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x)                                \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) &                     \\\n\t BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)\n#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v)                             \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) |                           \\\n\t BIT_R_MU_STA_GTAB_POSITION_8822B(v))\n\n/* 2 REG_MU_TRX_DBG_CNT_8822B */\n#define BIT_MU_DNGCNT_RST_8822B BIT(20)\n\n#define BIT_SHIFT_MU_DBGCNT_SEL_8822B 16\n#define BIT_MASK_MU_DBGCNT_SEL_8822B 0xf\n#define BIT_MU_DBGCNT_SEL_8822B(x)                                             \\\n\t(((x) & BIT_MASK_MU_DBGCNT_SEL_8822B) << BIT_SHIFT_MU_DBGCNT_SEL_8822B)\n#define BITS_MU_DBGCNT_SEL_8822B                                               \\\n\t(BIT_MASK_MU_DBGCNT_SEL_8822B << BIT_SHIFT_MU_DBGCNT_SEL_8822B)\n#define BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) ((x) & (~BITS_MU_DBGCNT_SEL_8822B))\n#define BIT_GET_MU_DBGCNT_SEL_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8822B) & BIT_MASK_MU_DBGCNT_SEL_8822B)\n#define BIT_SET_MU_DBGCNT_SEL_8822B(x, v)                                      \\\n\t(BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) | BIT_MU_DBGCNT_SEL_8822B(v))\n\n#define BIT_SHIFT_MU_DNGCNT_8822B 0\n#define BIT_MASK_MU_DNGCNT_8822B 0xffff\n#define BIT_MU_DNGCNT_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_MU_DNGCNT_8822B) << BIT_SHIFT_MU_DNGCNT_8822B)\n#define BITS_MU_DNGCNT_8822B                                                   \\\n\t(BIT_MASK_MU_DNGCNT_8822B << BIT_SHIFT_MU_DNGCNT_8822B)\n#define BIT_CLEAR_MU_DNGCNT_8822B(x) ((x) & (~BITS_MU_DNGCNT_8822B))\n#define BIT_GET_MU_DNGCNT_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_MU_DNGCNT_8822B) & BIT_MASK_MU_DNGCNT_8822B)\n#define BIT_SET_MU_DNGCNT_8822B(x, v)                                          \\\n\t(BIT_CLEAR_MU_DNGCNT_8822B(x) | BIT_MU_DNGCNT_8822B(v))\n\n/* 2 REG_MU_TX_CTL_8822B */\n#define BIT_R_EN_REVERS_GTAB_8822B BIT(6)\n\n#define BIT_SHIFT_R_MU_TABLE_VALID_8822B 0\n#define BIT_MASK_R_MU_TABLE_VALID_8822B 0x3f\n#define BIT_R_MU_TABLE_VALID_8822B(x)                                          \\\n\t(((x) & BIT_MASK_R_MU_TABLE_VALID_8822B)                               \\\n\t << BIT_SHIFT_R_MU_TABLE_VALID_8822B)\n#define BITS_R_MU_TABLE_VALID_8822B                                            \\\n\t(BIT_MASK_R_MU_TABLE_VALID_8822B << BIT_SHIFT_R_MU_TABLE_VALID_8822B)\n#define BIT_CLEAR_R_MU_TABLE_VALID_8822B(x)                                    \\\n\t((x) & (~BITS_R_MU_TABLE_VALID_8822B))\n#define BIT_GET_R_MU_TABLE_VALID_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822B) &                           \\\n\t BIT_MASK_R_MU_TABLE_VALID_8822B)\n#define BIT_SET_R_MU_TABLE_VALID_8822B(x, v)                                   \\\n\t(BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) | BIT_R_MU_TABLE_VALID_8822B(v))\n\n/* 2 REG_MU_STA_GID_VLD_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0\n#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL\n#define BIT_R_MU_STA_GTAB_VALID_8822B(x)                                       \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B)                            \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)\n#define BITS_R_MU_STA_GTAB_VALID_8822B                                         \\\n\t(BIT_MASK_R_MU_STA_GTAB_VALID_8822B                                    \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)\n#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x)                                 \\\n\t((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B))\n#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) &                        \\\n\t BIT_MASK_R_MU_STA_GTAB_VALID_8822B)\n#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v)                                \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) |                              \\\n\t BIT_R_MU_STA_GTAB_VALID_8822B(v))\n\n#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0\n#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL\n#define BIT_R_MU_STA_GTAB_VALID_8822B(x)                                       \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B)                            \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)\n#define BITS_R_MU_STA_GTAB_VALID_8822B                                         \\\n\t(BIT_MASK_R_MU_STA_GTAB_VALID_8822B                                    \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)\n#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x)                                 \\\n\t((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B))\n#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) &                        \\\n\t BIT_MASK_R_MU_STA_GTAB_VALID_8822B)\n#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v)                                \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) |                              \\\n\t BIT_R_MU_STA_GTAB_VALID_8822B(v))\n\n/* 2 REG_MU_STA_USER_POS_INFO_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0\n#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL\n#define BIT_R_MU_STA_GTAB_POSITION_8822B(x)                                    \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)                         \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)\n#define BITS_R_MU_STA_GTAB_POSITION_8822B                                      \\\n\t(BIT_MASK_R_MU_STA_GTAB_POSITION_8822B                                 \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)\n#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x)                              \\\n\t((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B))\n#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x)                                \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) &                     \\\n\t BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)\n#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v)                             \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) |                           \\\n\t BIT_R_MU_STA_GTAB_POSITION_8822B(v))\n\n#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0\n#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL\n#define BIT_R_MU_STA_GTAB_POSITION_8822B(x)                                    \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)                         \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)\n#define BITS_R_MU_STA_GTAB_POSITION_8822B                                      \\\n\t(BIT_MASK_R_MU_STA_GTAB_POSITION_8822B                                 \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)\n#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x)                              \\\n\t((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B))\n#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x)                                \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) &                     \\\n\t BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)\n#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v)                             \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) |                           \\\n\t BIT_R_MU_STA_GTAB_POSITION_8822B(v))\n\n/* 2 REG_MU_TRX_DBG_CNT_8822B */\n#define BIT_MU_DNGCNT_RST_8822B BIT(20)\n\n#define BIT_SHIFT_MU_DBGCNT_SEL_8822B 16\n#define BIT_MASK_MU_DBGCNT_SEL_8822B 0xf\n#define BIT_MU_DBGCNT_SEL_8822B(x)                                             \\\n\t(((x) & BIT_MASK_MU_DBGCNT_SEL_8822B) << BIT_SHIFT_MU_DBGCNT_SEL_8822B)\n#define BITS_MU_DBGCNT_SEL_8822B                                               \\\n\t(BIT_MASK_MU_DBGCNT_SEL_8822B << BIT_SHIFT_MU_DBGCNT_SEL_8822B)\n#define BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) ((x) & (~BITS_MU_DBGCNT_SEL_8822B))\n#define BIT_GET_MU_DBGCNT_SEL_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8822B) & BIT_MASK_MU_DBGCNT_SEL_8822B)\n#define BIT_SET_MU_DBGCNT_SEL_8822B(x, v)                                      \\\n\t(BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) | BIT_MU_DBGCNT_SEL_8822B(v))\n\n#define BIT_SHIFT_MU_DNGCNT_8822B 0\n#define BIT_MASK_MU_DNGCNT_8822B 0xffff\n#define BIT_MU_DNGCNT_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_MU_DNGCNT_8822B) << BIT_SHIFT_MU_DNGCNT_8822B)\n#define BITS_MU_DNGCNT_8822B                                                   \\\n\t(BIT_MASK_MU_DNGCNT_8822B << BIT_SHIFT_MU_DNGCNT_8822B)\n#define BIT_CLEAR_MU_DNGCNT_8822B(x) ((x) & (~BITS_MU_DNGCNT_8822B))\n#define BIT_GET_MU_DNGCNT_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_MU_DNGCNT_8822B) & BIT_MASK_MU_DNGCNT_8822B)\n#define BIT_SET_MU_DNGCNT_8822B(x, v)                                          \\\n\t(BIT_CLEAR_MU_DNGCNT_8822B(x) | BIT_MU_DNGCNT_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_EDCA_VO_PARAM_8822B */\n\n#define BIT_SHIFT_TXOPLIMIT_8822B 16\n#define BIT_MASK_TXOPLIMIT_8822B 0x7ff\n#define BIT_TXOPLIMIT_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)\n#define BITS_TXOPLIMIT_8822B                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B)\n#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B))\n#define BIT_GET_TXOPLIMIT_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)\n#define BIT_SET_TXOPLIMIT_8822B(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v))\n\n#define BIT_SHIFT_CW_8822B 8\n#define BIT_MASK_CW_8822B 0xff\n#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)\n#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B)\n#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B))\n#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)\n#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v))\n\n#define BIT_SHIFT_AIFS_8822B 0\n#define BIT_MASK_AIFS_8822B 0xff\n#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)\n#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B)\n#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B))\n#define BIT_GET_AIFS_8822B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)\n#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v))\n\n/* 2 REG_EDCA_VI_PARAM_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n#define BIT_SHIFT_TXOPLIMIT_8822B 16\n#define BIT_MASK_TXOPLIMIT_8822B 0x7ff\n#define BIT_TXOPLIMIT_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)\n#define BITS_TXOPLIMIT_8822B                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B)\n#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B))\n#define BIT_GET_TXOPLIMIT_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)\n#define BIT_SET_TXOPLIMIT_8822B(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v))\n\n#define BIT_SHIFT_CW_8822B 8\n#define BIT_MASK_CW_8822B 0xff\n#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)\n#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B)\n#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B))\n#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)\n#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v))\n\n#define BIT_SHIFT_AIFS_8822B 0\n#define BIT_MASK_AIFS_8822B 0xff\n#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)\n#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B)\n#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B))\n#define BIT_GET_AIFS_8822B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)\n#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v))\n\n/* 2 REG_EDCA_BE_PARAM_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n#define BIT_SHIFT_TXOPLIMIT_8822B 16\n#define BIT_MASK_TXOPLIMIT_8822B 0x7ff\n#define BIT_TXOPLIMIT_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)\n#define BITS_TXOPLIMIT_8822B                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B)\n#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B))\n#define BIT_GET_TXOPLIMIT_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)\n#define BIT_SET_TXOPLIMIT_8822B(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v))\n\n#define BIT_SHIFT_CW_8822B 8\n#define BIT_MASK_CW_8822B 0xff\n#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)\n#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B)\n#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B))\n#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)\n#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v))\n\n#define BIT_SHIFT_AIFS_8822B 0\n#define BIT_MASK_AIFS_8822B 0xff\n#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)\n#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B)\n#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B))\n#define BIT_GET_AIFS_8822B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)\n#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v))\n\n/* 2 REG_EDCA_BK_PARAM_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n\n#define BIT_SHIFT_TXOPLIMIT_8822B 16\n#define BIT_MASK_TXOPLIMIT_8822B 0x7ff\n#define BIT_TXOPLIMIT_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)\n#define BITS_TXOPLIMIT_8822B                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B)\n#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B))\n#define BIT_GET_TXOPLIMIT_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)\n#define BIT_SET_TXOPLIMIT_8822B(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v))\n\n#define BIT_SHIFT_CW_8822B 8\n#define BIT_MASK_CW_8822B 0xff\n#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)\n#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B)\n#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B))\n#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)\n#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v))\n\n#define BIT_SHIFT_AIFS_8822B 0\n#define BIT_MASK_AIFS_8822B 0xff\n#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)\n#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B)\n#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B))\n#define BIT_GET_AIFS_8822B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)\n#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v))\n\n/* 2 REG_BCNTCFG_8822B */\n\n#define BIT_SHIFT_BCNCW_MAX_8822B 12\n#define BIT_MASK_BCNCW_MAX_8822B 0xf\n#define BIT_BCNCW_MAX_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_BCNCW_MAX_8822B) << BIT_SHIFT_BCNCW_MAX_8822B)\n#define BITS_BCNCW_MAX_8822B                                                   \\\n\t(BIT_MASK_BCNCW_MAX_8822B << BIT_SHIFT_BCNCW_MAX_8822B)\n#define BIT_CLEAR_BCNCW_MAX_8822B(x) ((x) & (~BITS_BCNCW_MAX_8822B))\n#define BIT_GET_BCNCW_MAX_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNCW_MAX_8822B) & BIT_MASK_BCNCW_MAX_8822B)\n#define BIT_SET_BCNCW_MAX_8822B(x, v)                                          \\\n\t(BIT_CLEAR_BCNCW_MAX_8822B(x) | BIT_BCNCW_MAX_8822B(v))\n\n#define BIT_SHIFT_BCNCW_MIN_8822B 8\n#define BIT_MASK_BCNCW_MIN_8822B 0xf\n#define BIT_BCNCW_MIN_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_BCNCW_MIN_8822B) << BIT_SHIFT_BCNCW_MIN_8822B)\n#define BITS_BCNCW_MIN_8822B                                                   \\\n\t(BIT_MASK_BCNCW_MIN_8822B << BIT_SHIFT_BCNCW_MIN_8822B)\n#define BIT_CLEAR_BCNCW_MIN_8822B(x) ((x) & (~BITS_BCNCW_MIN_8822B))\n#define BIT_GET_BCNCW_MIN_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNCW_MIN_8822B) & BIT_MASK_BCNCW_MIN_8822B)\n#define BIT_SET_BCNCW_MIN_8822B(x, v)                                          \\\n\t(BIT_CLEAR_BCNCW_MIN_8822B(x) | BIT_BCNCW_MIN_8822B(v))\n\n#define BIT_SHIFT_BCNIFS_8822B 0\n#define BIT_MASK_BCNIFS_8822B 0xff\n#define BIT_BCNIFS_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_BCNIFS_8822B) << BIT_SHIFT_BCNIFS_8822B)\n#define BITS_BCNIFS_8822B (BIT_MASK_BCNIFS_8822B << BIT_SHIFT_BCNIFS_8822B)\n#define BIT_CLEAR_BCNIFS_8822B(x) ((x) & (~BITS_BCNIFS_8822B))\n#define BIT_GET_BCNIFS_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_BCNIFS_8822B) & BIT_MASK_BCNIFS_8822B)\n#define BIT_SET_BCNIFS_8822B(x, v)                                             \\\n\t(BIT_CLEAR_BCNIFS_8822B(x) | BIT_BCNIFS_8822B(v))\n\n/* 2 REG_PIFS_8822B */\n\n#define BIT_SHIFT_PIFS_8822B 0\n#define BIT_MASK_PIFS_8822B 0xff\n#define BIT_PIFS_8822B(x) (((x) & BIT_MASK_PIFS_8822B) << BIT_SHIFT_PIFS_8822B)\n#define BITS_PIFS_8822B (BIT_MASK_PIFS_8822B << BIT_SHIFT_PIFS_8822B)\n#define BIT_CLEAR_PIFS_8822B(x) ((x) & (~BITS_PIFS_8822B))\n#define BIT_GET_PIFS_8822B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_PIFS_8822B) & BIT_MASK_PIFS_8822B)\n#define BIT_SET_PIFS_8822B(x, v) (BIT_CLEAR_PIFS_8822B(x) | BIT_PIFS_8822B(v))\n\n/* 2 REG_RDG_PIFS_8822B */\n\n#define BIT_SHIFT_RDG_PIFS_8822B 0\n#define BIT_MASK_RDG_PIFS_8822B 0xff\n#define BIT_RDG_PIFS_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_RDG_PIFS_8822B) << BIT_SHIFT_RDG_PIFS_8822B)\n#define BITS_RDG_PIFS_8822B                                                    \\\n\t(BIT_MASK_RDG_PIFS_8822B << BIT_SHIFT_RDG_PIFS_8822B)\n#define BIT_CLEAR_RDG_PIFS_8822B(x) ((x) & (~BITS_RDG_PIFS_8822B))\n#define BIT_GET_RDG_PIFS_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RDG_PIFS_8822B) & BIT_MASK_RDG_PIFS_8822B)\n#define BIT_SET_RDG_PIFS_8822B(x, v)                                           \\\n\t(BIT_CLEAR_RDG_PIFS_8822B(x) | BIT_RDG_PIFS_8822B(v))\n\n/* 2 REG_SIFS_8822B */\n\n#define BIT_SHIFT_SIFS_OFDM_TRX_8822B 24\n#define BIT_MASK_SIFS_OFDM_TRX_8822B 0xff\n#define BIT_SIFS_OFDM_TRX_8822B(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_OFDM_TRX_8822B) << BIT_SHIFT_SIFS_OFDM_TRX_8822B)\n#define BITS_SIFS_OFDM_TRX_8822B                                               \\\n\t(BIT_MASK_SIFS_OFDM_TRX_8822B << BIT_SHIFT_SIFS_OFDM_TRX_8822B)\n#define BIT_CLEAR_SIFS_OFDM_TRX_8822B(x) ((x) & (~BITS_SIFS_OFDM_TRX_8822B))\n#define BIT_GET_SIFS_OFDM_TRX_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8822B) & BIT_MASK_SIFS_OFDM_TRX_8822B)\n#define BIT_SET_SIFS_OFDM_TRX_8822B(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_OFDM_TRX_8822B(x) | BIT_SIFS_OFDM_TRX_8822B(v))\n\n#define BIT_SHIFT_SIFS_CCK_TRX_8822B 16\n#define BIT_MASK_SIFS_CCK_TRX_8822B 0xff\n#define BIT_SIFS_CCK_TRX_8822B(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_CCK_TRX_8822B) << BIT_SHIFT_SIFS_CCK_TRX_8822B)\n#define BITS_SIFS_CCK_TRX_8822B                                                \\\n\t(BIT_MASK_SIFS_CCK_TRX_8822B << BIT_SHIFT_SIFS_CCK_TRX_8822B)\n#define BIT_CLEAR_SIFS_CCK_TRX_8822B(x) ((x) & (~BITS_SIFS_CCK_TRX_8822B))\n#define BIT_GET_SIFS_CCK_TRX_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_CCK_TRX_8822B) & BIT_MASK_SIFS_CCK_TRX_8822B)\n#define BIT_SET_SIFS_CCK_TRX_8822B(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_CCK_TRX_8822B(x) | BIT_SIFS_CCK_TRX_8822B(v))\n\n#define BIT_SHIFT_SIFS_OFDM_CTX_8822B 8\n#define BIT_MASK_SIFS_OFDM_CTX_8822B 0xff\n#define BIT_SIFS_OFDM_CTX_8822B(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_OFDM_CTX_8822B) << BIT_SHIFT_SIFS_OFDM_CTX_8822B)\n#define BITS_SIFS_OFDM_CTX_8822B                                               \\\n\t(BIT_MASK_SIFS_OFDM_CTX_8822B << BIT_SHIFT_SIFS_OFDM_CTX_8822B)\n#define BIT_CLEAR_SIFS_OFDM_CTX_8822B(x) ((x) & (~BITS_SIFS_OFDM_CTX_8822B))\n#define BIT_GET_SIFS_OFDM_CTX_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8822B) & BIT_MASK_SIFS_OFDM_CTX_8822B)\n#define BIT_SET_SIFS_OFDM_CTX_8822B(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_OFDM_CTX_8822B(x) | BIT_SIFS_OFDM_CTX_8822B(v))\n\n#define BIT_SHIFT_SIFS_CCK_CTX_8822B 0\n#define BIT_MASK_SIFS_CCK_CTX_8822B 0xff\n#define BIT_SIFS_CCK_CTX_8822B(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_CCK_CTX_8822B) << BIT_SHIFT_SIFS_CCK_CTX_8822B)\n#define BITS_SIFS_CCK_CTX_8822B                                                \\\n\t(BIT_MASK_SIFS_CCK_CTX_8822B << BIT_SHIFT_SIFS_CCK_CTX_8822B)\n#define BIT_CLEAR_SIFS_CCK_CTX_8822B(x) ((x) & (~BITS_SIFS_CCK_CTX_8822B))\n#define BIT_GET_SIFS_CCK_CTX_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_CCK_CTX_8822B) & BIT_MASK_SIFS_CCK_CTX_8822B)\n#define BIT_SET_SIFS_CCK_CTX_8822B(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_CCK_CTX_8822B(x) | BIT_SIFS_CCK_CTX_8822B(v))\n\n/* 2 REG_TSFTR_SYN_OFFSET_8822B */\n\n#define BIT_SHIFT_TSFTR_SNC_OFFSET_8822B 0\n#define BIT_MASK_TSFTR_SNC_OFFSET_8822B 0xffff\n#define BIT_TSFTR_SNC_OFFSET_8822B(x)                                          \\\n\t(((x) & BIT_MASK_TSFTR_SNC_OFFSET_8822B)                               \\\n\t << BIT_SHIFT_TSFTR_SNC_OFFSET_8822B)\n#define BITS_TSFTR_SNC_OFFSET_8822B                                            \\\n\t(BIT_MASK_TSFTR_SNC_OFFSET_8822B << BIT_SHIFT_TSFTR_SNC_OFFSET_8822B)\n#define BIT_CLEAR_TSFTR_SNC_OFFSET_8822B(x)                                    \\\n\t((x) & (~BITS_TSFTR_SNC_OFFSET_8822B))\n#define BIT_GET_TSFTR_SNC_OFFSET_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8822B) &                           \\\n\t BIT_MASK_TSFTR_SNC_OFFSET_8822B)\n#define BIT_SET_TSFTR_SNC_OFFSET_8822B(x, v)                                   \\\n\t(BIT_CLEAR_TSFTR_SNC_OFFSET_8822B(x) | BIT_TSFTR_SNC_OFFSET_8822B(v))\n\n/* 2 REG_AGGR_BREAK_TIME_8822B */\n\n#define BIT_SHIFT_AGGR_BK_TIME_8822B 0\n#define BIT_MASK_AGGR_BK_TIME_8822B 0xff\n#define BIT_AGGR_BK_TIME_8822B(x)                                              \\\n\t(((x) & BIT_MASK_AGGR_BK_TIME_8822B) << BIT_SHIFT_AGGR_BK_TIME_8822B)\n#define BITS_AGGR_BK_TIME_8822B                                                \\\n\t(BIT_MASK_AGGR_BK_TIME_8822B << BIT_SHIFT_AGGR_BK_TIME_8822B)\n#define BIT_CLEAR_AGGR_BK_TIME_8822B(x) ((x) & (~BITS_AGGR_BK_TIME_8822B))\n#define BIT_GET_AGGR_BK_TIME_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_AGGR_BK_TIME_8822B) & BIT_MASK_AGGR_BK_TIME_8822B)\n#define BIT_SET_AGGR_BK_TIME_8822B(x, v)                                       \\\n\t(BIT_CLEAR_AGGR_BK_TIME_8822B(x) | BIT_AGGR_BK_TIME_8822B(v))\n\n/* 2 REG_SLOT_8822B */\n\n#define BIT_SHIFT_SLOT_8822B 0\n#define BIT_MASK_SLOT_8822B 0xff\n#define BIT_SLOT_8822B(x) (((x) & BIT_MASK_SLOT_8822B) << BIT_SHIFT_SLOT_8822B)\n#define BITS_SLOT_8822B (BIT_MASK_SLOT_8822B << BIT_SHIFT_SLOT_8822B)\n#define BIT_CLEAR_SLOT_8822B(x) ((x) & (~BITS_SLOT_8822B))\n#define BIT_GET_SLOT_8822B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_SLOT_8822B) & BIT_MASK_SLOT_8822B)\n#define BIT_SET_SLOT_8822B(x, v) (BIT_CLEAR_SLOT_8822B(x) | BIT_SLOT_8822B(v))\n\n/* 2 REG_TX_PTCL_CTRL_8822B */\n#define BIT_DIS_EDCCA_8822B BIT(15)\n#define BIT_DIS_CCA_8822B BIT(14)\n#define BIT_LSIG_TXOP_TXCMD_NAV_8822B BIT(13)\n#define BIT_SIFS_BK_EN_8822B BIT(12)\n\n#define BIT_SHIFT_TXQ_NAV_MSK_8822B 8\n#define BIT_MASK_TXQ_NAV_MSK_8822B 0xf\n#define BIT_TXQ_NAV_MSK_8822B(x)                                               \\\n\t(((x) & BIT_MASK_TXQ_NAV_MSK_8822B) << BIT_SHIFT_TXQ_NAV_MSK_8822B)\n#define BITS_TXQ_NAV_MSK_8822B                                                 \\\n\t(BIT_MASK_TXQ_NAV_MSK_8822B << BIT_SHIFT_TXQ_NAV_MSK_8822B)\n#define BIT_CLEAR_TXQ_NAV_MSK_8822B(x) ((x) & (~BITS_TXQ_NAV_MSK_8822B))\n#define BIT_GET_TXQ_NAV_MSK_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_TXQ_NAV_MSK_8822B) & BIT_MASK_TXQ_NAV_MSK_8822B)\n#define BIT_SET_TXQ_NAV_MSK_8822B(x, v)                                        \\\n\t(BIT_CLEAR_TXQ_NAV_MSK_8822B(x) | BIT_TXQ_NAV_MSK_8822B(v))\n\n#define BIT_DIS_CW_8822B BIT(7)\n#define BIT_NAV_END_TXOP_8822B BIT(6)\n#define BIT_RDG_END_TXOP_8822B BIT(5)\n#define BIT_AC_INBCN_HOLD_8822B BIT(4)\n#define BIT_MGTQ_TXOP_EN_8822B BIT(3)\n#define BIT_MGTQ_RTSMF_EN_8822B BIT(2)\n#define BIT_HIQ_RTSMF_EN_8822B BIT(1)\n#define BIT_BCN_RTSMF_EN_8822B BIT(0)\n\n/* 2 REG_TXPAUSE_8822B */\n#define BIT_STOP_BCN_HI_MGT_8822B BIT(7)\n#define BIT_MAC_STOPBCNQ_8822B BIT(6)\n#define BIT_MAC_STOPHIQ_8822B BIT(5)\n#define BIT_MAC_STOPMGQ_8822B BIT(4)\n#define BIT_MAC_STOPBK_8822B BIT(3)\n#define BIT_MAC_STOPBE_8822B BIT(2)\n#define BIT_MAC_STOPVI_8822B BIT(1)\n#define BIT_MAC_STOPVO_8822B BIT(0)\n\n/* 2 REG_DIS_TXREQ_CLR_8822B */\n#define BIT_DIS_BT_CCA_8822B BIT(7)\n#define BIT_DIS_TXREQ_CLR_HI_8822B BIT(5)\n#define BIT_DIS_TXREQ_CLR_MGQ_8822B BIT(4)\n#define BIT_DIS_TXREQ_CLR_VO_8822B BIT(3)\n#define BIT_DIS_TXREQ_CLR_VI_8822B BIT(2)\n#define BIT_DIS_TXREQ_CLR_BE_8822B BIT(1)\n#define BIT_DIS_TXREQ_CLR_BK_8822B BIT(0)\n\n/* 2 REG_RD_CTRL_8822B */\n#define BIT_EN_CLR_TXREQ_INCCA_8822B BIT(15)\n#define BIT_DIS_TX_OVER_BCNQ_8822B BIT(14)\n#define BIT_EN_BCNERR_INCCCA_8822B BIT(13)\n#define BIT_EDCCA_MSK_CNTDOWN_EN_8822B BIT(11)\n#define BIT_DIS_TXOP_CFE_8822B BIT(10)\n#define BIT_DIS_LSIG_CFE_8822B BIT(9)\n#define BIT_DIS_STBC_CFE_8822B BIT(8)\n#define BIT_BKQ_RD_INIT_EN_8822B BIT(7)\n#define BIT_BEQ_RD_INIT_EN_8822B BIT(6)\n#define BIT_VIQ_RD_INIT_EN_8822B BIT(5)\n#define BIT_VOQ_RD_INIT_EN_8822B BIT(4)\n#define BIT_BKQ_RD_RESP_EN_8822B BIT(3)\n#define BIT_BEQ_RD_RESP_EN_8822B BIT(2)\n#define BIT_VIQ_RD_RESP_EN_8822B BIT(1)\n#define BIT_VOQ_RD_RESP_EN_8822B BIT(0)\n\n/* 2 REG_MBSSID_CTRL_8822B */\n#define BIT_MBID_BCNQ7_EN_8822B BIT(7)\n#define BIT_MBID_BCNQ6_EN_8822B BIT(6)\n#define BIT_MBID_BCNQ5_EN_8822B BIT(5)\n#define BIT_MBID_BCNQ4_EN_8822B BIT(4)\n#define BIT_MBID_BCNQ3_EN_8822B BIT(3)\n#define BIT_MBID_BCNQ2_EN_8822B BIT(2)\n#define BIT_MBID_BCNQ1_EN_8822B BIT(1)\n#define BIT_MBID_BCNQ0_EN_8822B BIT(0)\n\n/* 2 REG_P2PPS_CTRL_8822B */\n#define BIT_P2P_CTW_ALLSTASLEEP_8822B BIT(7)\n#define BIT_P2P_OFF_DISTX_EN_8822B BIT(6)\n#define BIT_PWR_MGT_EN_8822B BIT(5)\n#define BIT_P2P_NOA1_EN_8822B BIT(2)\n#define BIT_P2P_NOA0_EN_8822B BIT(1)\n\n/* 2 REG_PKT_LIFETIME_CTRL_8822B */\n#define BIT_EN_P2P_CTWND1_8822B BIT(23)\n#define BIT_EN_BKF_CLR_TXREQ_8822B BIT(22)\n#define BIT_EN_TSFBIT32_RST_P2P_8822B BIT(21)\n#define BIT_EN_BCN_TX_BTCCA_8822B BIT(20)\n#define BIT_DIS_PKT_TX_ATIM_8822B BIT(19)\n#define BIT_DIS_BCN_DIS_CTN_8822B BIT(18)\n#define BIT_EN_NAVEND_RST_TXOP_8822B BIT(17)\n#define BIT_EN_FILTER_CCA_8822B BIT(16)\n\n#define BIT_SHIFT_CCA_FILTER_THRS_8822B 8\n#define BIT_MASK_CCA_FILTER_THRS_8822B 0xff\n#define BIT_CCA_FILTER_THRS_8822B(x)                                           \\\n\t(((x) & BIT_MASK_CCA_FILTER_THRS_8822B)                                \\\n\t << BIT_SHIFT_CCA_FILTER_THRS_8822B)\n#define BITS_CCA_FILTER_THRS_8822B                                             \\\n\t(BIT_MASK_CCA_FILTER_THRS_8822B << BIT_SHIFT_CCA_FILTER_THRS_8822B)\n#define BIT_CLEAR_CCA_FILTER_THRS_8822B(x) ((x) & (~BITS_CCA_FILTER_THRS_8822B))\n#define BIT_GET_CCA_FILTER_THRS_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_CCA_FILTER_THRS_8822B) &                            \\\n\t BIT_MASK_CCA_FILTER_THRS_8822B)\n#define BIT_SET_CCA_FILTER_THRS_8822B(x, v)                                    \\\n\t(BIT_CLEAR_CCA_FILTER_THRS_8822B(x) | BIT_CCA_FILTER_THRS_8822B(v))\n\n#define BIT_SHIFT_EDCCA_THRS_8822B 0\n#define BIT_MASK_EDCCA_THRS_8822B 0xff\n#define BIT_EDCCA_THRS_8822B(x)                                                \\\n\t(((x) & BIT_MASK_EDCCA_THRS_8822B) << BIT_SHIFT_EDCCA_THRS_8822B)\n#define BITS_EDCCA_THRS_8822B                                                  \\\n\t(BIT_MASK_EDCCA_THRS_8822B << BIT_SHIFT_EDCCA_THRS_8822B)\n#define BIT_CLEAR_EDCCA_THRS_8822B(x) ((x) & (~BITS_EDCCA_THRS_8822B))\n#define BIT_GET_EDCCA_THRS_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_EDCCA_THRS_8822B) & BIT_MASK_EDCCA_THRS_8822B)\n#define BIT_SET_EDCCA_THRS_8822B(x, v)                                         \\\n\t(BIT_CLEAR_EDCCA_THRS_8822B(x) | BIT_EDCCA_THRS_8822B(v))\n\n/* 2 REG_P2PPS_SPEC_STATE_8822B */\n#define BIT_SPEC_POWER_STATE_8822B BIT(7)\n#define BIT_SPEC_CTWINDOW_ON_8822B BIT(6)\n#define BIT_SPEC_BEACON_AREA_ON_8822B BIT(5)\n#define BIT_SPEC_CTWIN_EARLY_DISTX_8822B BIT(4)\n#define BIT_SPEC_NOA1_OFF_PERIOD_8822B BIT(3)\n#define BIT_SPEC_FORCE_DOZE1_8822B BIT(2)\n#define BIT_SPEC_NOA0_OFF_PERIOD_8822B BIT(1)\n#define BIT_SPEC_FORCE_DOZE0_8822B BIT(0)\n\n/* 2 REG_TXOP_LIMIT_CTRL_8822B */\n\n#define BIT_SHIFT_TXOP_TBTT_CNT_8822B 24\n#define BIT_MASK_TXOP_TBTT_CNT_8822B 0xff\n#define BIT_TXOP_TBTT_CNT_8822B(x)                                             \\\n\t(((x) & BIT_MASK_TXOP_TBTT_CNT_8822B) << BIT_SHIFT_TXOP_TBTT_CNT_8822B)\n#define BITS_TXOP_TBTT_CNT_8822B                                               \\\n\t(BIT_MASK_TXOP_TBTT_CNT_8822B << BIT_SHIFT_TXOP_TBTT_CNT_8822B)\n#define BIT_CLEAR_TXOP_TBTT_CNT_8822B(x) ((x) & (~BITS_TXOP_TBTT_CNT_8822B))\n#define BIT_GET_TXOP_TBTT_CNT_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXOP_TBTT_CNT_8822B) & BIT_MASK_TXOP_TBTT_CNT_8822B)\n#define BIT_SET_TXOP_TBTT_CNT_8822B(x, v)                                      \\\n\t(BIT_CLEAR_TXOP_TBTT_CNT_8822B(x) | BIT_TXOP_TBTT_CNT_8822B(v))\n\n#define BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B 20\n#define BIT_MASK_TXOP_TBTT_CNT_SEL_8822B 0xf\n#define BIT_TXOP_TBTT_CNT_SEL_8822B(x)                                         \\\n\t(((x) & BIT_MASK_TXOP_TBTT_CNT_SEL_8822B)                              \\\n\t << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B)\n#define BITS_TXOP_TBTT_CNT_SEL_8822B                                           \\\n\t(BIT_MASK_TXOP_TBTT_CNT_SEL_8822B << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B)\n#define BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822B(x)                                   \\\n\t((x) & (~BITS_TXOP_TBTT_CNT_SEL_8822B))\n#define BIT_GET_TXOP_TBTT_CNT_SEL_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B) &                          \\\n\t BIT_MASK_TXOP_TBTT_CNT_SEL_8822B)\n#define BIT_SET_TXOP_TBTT_CNT_SEL_8822B(x, v)                                  \\\n\t(BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822B(x) | BIT_TXOP_TBTT_CNT_SEL_8822B(v))\n\n#define BIT_SHIFT_TXOP_LMT_EN_8822B 16\n#define BIT_MASK_TXOP_LMT_EN_8822B 0xf\n#define BIT_TXOP_LMT_EN_8822B(x)                                               \\\n\t(((x) & BIT_MASK_TXOP_LMT_EN_8822B) << BIT_SHIFT_TXOP_LMT_EN_8822B)\n#define BITS_TXOP_LMT_EN_8822B                                                 \\\n\t(BIT_MASK_TXOP_LMT_EN_8822B << BIT_SHIFT_TXOP_LMT_EN_8822B)\n#define BIT_CLEAR_TXOP_LMT_EN_8822B(x) ((x) & (~BITS_TXOP_LMT_EN_8822B))\n#define BIT_GET_TXOP_LMT_EN_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_TXOP_LMT_EN_8822B) & BIT_MASK_TXOP_LMT_EN_8822B)\n#define BIT_SET_TXOP_LMT_EN_8822B(x, v)                                        \\\n\t(BIT_CLEAR_TXOP_LMT_EN_8822B(x) | BIT_TXOP_LMT_EN_8822B(v))\n\n#define BIT_SHIFT_TXOP_LMT_TX_TIME_8822B 8\n#define BIT_MASK_TXOP_LMT_TX_TIME_8822B 0xff\n#define BIT_TXOP_LMT_TX_TIME_8822B(x)                                          \\\n\t(((x) & BIT_MASK_TXOP_LMT_TX_TIME_8822B)                               \\\n\t << BIT_SHIFT_TXOP_LMT_TX_TIME_8822B)\n#define BITS_TXOP_LMT_TX_TIME_8822B                                            \\\n\t(BIT_MASK_TXOP_LMT_TX_TIME_8822B << BIT_SHIFT_TXOP_LMT_TX_TIME_8822B)\n#define BIT_CLEAR_TXOP_LMT_TX_TIME_8822B(x)                                    \\\n\t((x) & (~BITS_TXOP_LMT_TX_TIME_8822B))\n#define BIT_GET_TXOP_LMT_TX_TIME_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME_8822B) &                           \\\n\t BIT_MASK_TXOP_LMT_TX_TIME_8822B)\n#define BIT_SET_TXOP_LMT_TX_TIME_8822B(x, v)                                   \\\n\t(BIT_CLEAR_TXOP_LMT_TX_TIME_8822B(x) | BIT_TXOP_LMT_TX_TIME_8822B(v))\n\n#define BIT_TXOP_CNT_TRIGGER_RESET_8822B BIT(7)\n\n#define BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B 0\n#define BIT_MASK_TXOP_LMT_PKT_NUM_8822B 0x3f\n#define BIT_TXOP_LMT_PKT_NUM_8822B(x)                                          \\\n\t(((x) & BIT_MASK_TXOP_LMT_PKT_NUM_8822B)                               \\\n\t << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B)\n#define BITS_TXOP_LMT_PKT_NUM_8822B                                            \\\n\t(BIT_MASK_TXOP_LMT_PKT_NUM_8822B << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B)\n#define BIT_CLEAR_TXOP_LMT_PKT_NUM_8822B(x)                                    \\\n\t((x) & (~BITS_TXOP_LMT_PKT_NUM_8822B))\n#define BIT_GET_TXOP_LMT_PKT_NUM_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B) &                           \\\n\t BIT_MASK_TXOP_LMT_PKT_NUM_8822B)\n#define BIT_SET_TXOP_LMT_PKT_NUM_8822B(x, v)                                   \\\n\t(BIT_CLEAR_TXOP_LMT_PKT_NUM_8822B(x) | BIT_TXOP_LMT_PKT_NUM_8822B(v))\n\n/* 2 REG_BAR_TX_CTRL_8822B */\n\n/* 2 REG_P2PON_DIS_TXTIME_8822B */\n\n#define BIT_SHIFT_P2PON_DIS_TXTIME_8822B 0\n#define BIT_MASK_P2PON_DIS_TXTIME_8822B 0xff\n#define BIT_P2PON_DIS_TXTIME_8822B(x)                                          \\\n\t(((x) & BIT_MASK_P2PON_DIS_TXTIME_8822B)                               \\\n\t << BIT_SHIFT_P2PON_DIS_TXTIME_8822B)\n#define BITS_P2PON_DIS_TXTIME_8822B                                            \\\n\t(BIT_MASK_P2PON_DIS_TXTIME_8822B << BIT_SHIFT_P2PON_DIS_TXTIME_8822B)\n#define BIT_CLEAR_P2PON_DIS_TXTIME_8822B(x)                                    \\\n\t((x) & (~BITS_P2PON_DIS_TXTIME_8822B))\n#define BIT_GET_P2PON_DIS_TXTIME_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8822B) &                           \\\n\t BIT_MASK_P2PON_DIS_TXTIME_8822B)\n#define BIT_SET_P2PON_DIS_TXTIME_8822B(x, v)                                   \\\n\t(BIT_CLEAR_P2PON_DIS_TXTIME_8822B(x) | BIT_P2PON_DIS_TXTIME_8822B(v))\n\n/* 2 REG_QUEUE_INCOL_THR_8822B */\n\n#define BIT_SHIFT_BK_QUEUE_THR_8822B 24\n#define BIT_MASK_BK_QUEUE_THR_8822B 0xff\n#define BIT_BK_QUEUE_THR_8822B(x)                                              \\\n\t(((x) & BIT_MASK_BK_QUEUE_THR_8822B) << BIT_SHIFT_BK_QUEUE_THR_8822B)\n#define BITS_BK_QUEUE_THR_8822B                                                \\\n\t(BIT_MASK_BK_QUEUE_THR_8822B << BIT_SHIFT_BK_QUEUE_THR_8822B)\n#define BIT_CLEAR_BK_QUEUE_THR_8822B(x) ((x) & (~BITS_BK_QUEUE_THR_8822B))\n#define BIT_GET_BK_QUEUE_THR_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BK_QUEUE_THR_8822B) & BIT_MASK_BK_QUEUE_THR_8822B)\n#define BIT_SET_BK_QUEUE_THR_8822B(x, v)                                       \\\n\t(BIT_CLEAR_BK_QUEUE_THR_8822B(x) | BIT_BK_QUEUE_THR_8822B(v))\n\n#define BIT_SHIFT_BE_QUEUE_THR_8822B 16\n#define BIT_MASK_BE_QUEUE_THR_8822B 0xff\n#define BIT_BE_QUEUE_THR_8822B(x)                                              \\\n\t(((x) & BIT_MASK_BE_QUEUE_THR_8822B) << BIT_SHIFT_BE_QUEUE_THR_8822B)\n#define BITS_BE_QUEUE_THR_8822B                                                \\\n\t(BIT_MASK_BE_QUEUE_THR_8822B << BIT_SHIFT_BE_QUEUE_THR_8822B)\n#define BIT_CLEAR_BE_QUEUE_THR_8822B(x) ((x) & (~BITS_BE_QUEUE_THR_8822B))\n#define BIT_GET_BE_QUEUE_THR_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BE_QUEUE_THR_8822B) & BIT_MASK_BE_QUEUE_THR_8822B)\n#define BIT_SET_BE_QUEUE_THR_8822B(x, v)                                       \\\n\t(BIT_CLEAR_BE_QUEUE_THR_8822B(x) | BIT_BE_QUEUE_THR_8822B(v))\n\n#define BIT_SHIFT_VI_QUEUE_THR_8822B 8\n#define BIT_MASK_VI_QUEUE_THR_8822B 0xff\n#define BIT_VI_QUEUE_THR_8822B(x)                                              \\\n\t(((x) & BIT_MASK_VI_QUEUE_THR_8822B) << BIT_SHIFT_VI_QUEUE_THR_8822B)\n#define BITS_VI_QUEUE_THR_8822B                                                \\\n\t(BIT_MASK_VI_QUEUE_THR_8822B << BIT_SHIFT_VI_QUEUE_THR_8822B)\n#define BIT_CLEAR_VI_QUEUE_THR_8822B(x) ((x) & (~BITS_VI_QUEUE_THR_8822B))\n#define BIT_GET_VI_QUEUE_THR_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_VI_QUEUE_THR_8822B) & BIT_MASK_VI_QUEUE_THR_8822B)\n#define BIT_SET_VI_QUEUE_THR_8822B(x, v)                                       \\\n\t(BIT_CLEAR_VI_QUEUE_THR_8822B(x) | BIT_VI_QUEUE_THR_8822B(v))\n\n#define BIT_SHIFT_VO_QUEUE_THR_8822B 0\n#define BIT_MASK_VO_QUEUE_THR_8822B 0xff\n#define BIT_VO_QUEUE_THR_8822B(x)                                              \\\n\t(((x) & BIT_MASK_VO_QUEUE_THR_8822B) << BIT_SHIFT_VO_QUEUE_THR_8822B)\n#define BITS_VO_QUEUE_THR_8822B                                                \\\n\t(BIT_MASK_VO_QUEUE_THR_8822B << BIT_SHIFT_VO_QUEUE_THR_8822B)\n#define BIT_CLEAR_VO_QUEUE_THR_8822B(x) ((x) & (~BITS_VO_QUEUE_THR_8822B))\n#define BIT_GET_VO_QUEUE_THR_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_VO_QUEUE_THR_8822B) & BIT_MASK_VO_QUEUE_THR_8822B)\n#define BIT_SET_VO_QUEUE_THR_8822B(x, v)                                       \\\n\t(BIT_CLEAR_VO_QUEUE_THR_8822B(x) | BIT_VO_QUEUE_THR_8822B(v))\n\n/* 2 REG_QUEUE_INCOL_EN_8822B */\n#define BIT_QUEUE_INCOL_EN_8822B BIT(16)\n\n#define BIT_SHIFT_BE_TRIGGER_NUM_8822B 12\n#define BIT_MASK_BE_TRIGGER_NUM_8822B 0xf\n#define BIT_BE_TRIGGER_NUM_8822B(x)                                            \\\n\t(((x) & BIT_MASK_BE_TRIGGER_NUM_8822B)                                 \\\n\t << BIT_SHIFT_BE_TRIGGER_NUM_8822B)\n#define BITS_BE_TRIGGER_NUM_8822B                                              \\\n\t(BIT_MASK_BE_TRIGGER_NUM_8822B << BIT_SHIFT_BE_TRIGGER_NUM_8822B)\n#define BIT_CLEAR_BE_TRIGGER_NUM_8822B(x) ((x) & (~BITS_BE_TRIGGER_NUM_8822B))\n#define BIT_GET_BE_TRIGGER_NUM_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_BE_TRIGGER_NUM_8822B) &                             \\\n\t BIT_MASK_BE_TRIGGER_NUM_8822B)\n#define BIT_SET_BE_TRIGGER_NUM_8822B(x, v)                                     \\\n\t(BIT_CLEAR_BE_TRIGGER_NUM_8822B(x) | BIT_BE_TRIGGER_NUM_8822B(v))\n\n#define BIT_SHIFT_BK_TRIGGER_NUM_8822B 8\n#define BIT_MASK_BK_TRIGGER_NUM_8822B 0xf\n#define BIT_BK_TRIGGER_NUM_8822B(x)                                            \\\n\t(((x) & BIT_MASK_BK_TRIGGER_NUM_8822B)                                 \\\n\t << BIT_SHIFT_BK_TRIGGER_NUM_8822B)\n#define BITS_BK_TRIGGER_NUM_8822B                                              \\\n\t(BIT_MASK_BK_TRIGGER_NUM_8822B << BIT_SHIFT_BK_TRIGGER_NUM_8822B)\n#define BIT_CLEAR_BK_TRIGGER_NUM_8822B(x) ((x) & (~BITS_BK_TRIGGER_NUM_8822B))\n#define BIT_GET_BK_TRIGGER_NUM_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_BK_TRIGGER_NUM_8822B) &                             \\\n\t BIT_MASK_BK_TRIGGER_NUM_8822B)\n#define BIT_SET_BK_TRIGGER_NUM_8822B(x, v)                                     \\\n\t(BIT_CLEAR_BK_TRIGGER_NUM_8822B(x) | BIT_BK_TRIGGER_NUM_8822B(v))\n\n#define BIT_SHIFT_VI_TRIGGER_NUM_8822B 4\n#define BIT_MASK_VI_TRIGGER_NUM_8822B 0xf\n#define BIT_VI_TRIGGER_NUM_8822B(x)                                            \\\n\t(((x) & BIT_MASK_VI_TRIGGER_NUM_8822B)                                 \\\n\t << BIT_SHIFT_VI_TRIGGER_NUM_8822B)\n#define BITS_VI_TRIGGER_NUM_8822B                                              \\\n\t(BIT_MASK_VI_TRIGGER_NUM_8822B << BIT_SHIFT_VI_TRIGGER_NUM_8822B)\n#define BIT_CLEAR_VI_TRIGGER_NUM_8822B(x) ((x) & (~BITS_VI_TRIGGER_NUM_8822B))\n#define BIT_GET_VI_TRIGGER_NUM_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8822B) &                             \\\n\t BIT_MASK_VI_TRIGGER_NUM_8822B)\n#define BIT_SET_VI_TRIGGER_NUM_8822B(x, v)                                     \\\n\t(BIT_CLEAR_VI_TRIGGER_NUM_8822B(x) | BIT_VI_TRIGGER_NUM_8822B(v))\n\n#define BIT_SHIFT_VO_TRIGGER_NUM_8822B 0\n#define BIT_MASK_VO_TRIGGER_NUM_8822B 0xf\n#define BIT_VO_TRIGGER_NUM_8822B(x)                                            \\\n\t(((x) & BIT_MASK_VO_TRIGGER_NUM_8822B)                                 \\\n\t << BIT_SHIFT_VO_TRIGGER_NUM_8822B)\n#define BITS_VO_TRIGGER_NUM_8822B                                              \\\n\t(BIT_MASK_VO_TRIGGER_NUM_8822B << BIT_SHIFT_VO_TRIGGER_NUM_8822B)\n#define BIT_CLEAR_VO_TRIGGER_NUM_8822B(x) ((x) & (~BITS_VO_TRIGGER_NUM_8822B))\n#define BIT_GET_VO_TRIGGER_NUM_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8822B) &                             \\\n\t BIT_MASK_VO_TRIGGER_NUM_8822B)\n#define BIT_SET_VO_TRIGGER_NUM_8822B(x, v)                                     \\\n\t(BIT_CLEAR_VO_TRIGGER_NUM_8822B(x) | BIT_VO_TRIGGER_NUM_8822B(v))\n\n/* 2 REG_TBTT_PROHIBIT_8822B */\n\n#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B 8\n#define BIT_MASK_TBTT_HOLD_TIME_AP_8822B 0xfff\n#define BIT_TBTT_HOLD_TIME_AP_8822B(x)                                         \\\n\t(((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8822B)                              \\\n\t << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B)\n#define BITS_TBTT_HOLD_TIME_AP_8822B                                           \\\n\t(BIT_MASK_TBTT_HOLD_TIME_AP_8822B << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B)\n#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8822B(x)                                   \\\n\t((x) & (~BITS_TBTT_HOLD_TIME_AP_8822B))\n#define BIT_GET_TBTT_HOLD_TIME_AP_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B) &                          \\\n\t BIT_MASK_TBTT_HOLD_TIME_AP_8822B)\n#define BIT_SET_TBTT_HOLD_TIME_AP_8822B(x, v)                                  \\\n\t(BIT_CLEAR_TBTT_HOLD_TIME_AP_8822B(x) | BIT_TBTT_HOLD_TIME_AP_8822B(v))\n\n#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B 0\n#define BIT_MASK_TBTT_PROHIBIT_SETUP_8822B 0xf\n#define BIT_TBTT_PROHIBIT_SETUP_8822B(x)                                       \\\n\t(((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822B)                            \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B)\n#define BITS_TBTT_PROHIBIT_SETUP_8822B                                         \\\n\t(BIT_MASK_TBTT_PROHIBIT_SETUP_8822B                                    \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B)\n#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822B(x)                                 \\\n\t((x) & (~BITS_TBTT_PROHIBIT_SETUP_8822B))\n#define BIT_GET_TBTT_PROHIBIT_SETUP_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B) &                        \\\n\t BIT_MASK_TBTT_PROHIBIT_SETUP_8822B)\n#define BIT_SET_TBTT_PROHIBIT_SETUP_8822B(x, v)                                \\\n\t(BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822B(x) |                              \\\n\t BIT_TBTT_PROHIBIT_SETUP_8822B(v))\n\n/* 2 REG_P2PPS_STATE_8822B */\n#define BIT_POWER_STATE_8822B BIT(7)\n#define BIT_CTWINDOW_ON_8822B BIT(6)\n#define BIT_BEACON_AREA_ON_8822B BIT(5)\n#define BIT_CTWIN_EARLY_DISTX_8822B BIT(4)\n#define BIT_NOA1_OFF_PERIOD_8822B BIT(3)\n#define BIT_FORCE_DOZE1_8822B BIT(2)\n#define BIT_NOA0_OFF_PERIOD_8822B BIT(1)\n#define BIT_FORCE_DOZE0_8822B BIT(0)\n\n/* 2 REG_RD_NAV_NXT_8822B */\n\n#define BIT_SHIFT_RD_NAV_PROT_NXT_8822B 0\n#define BIT_MASK_RD_NAV_PROT_NXT_8822B 0xffff\n#define BIT_RD_NAV_PROT_NXT_8822B(x)                                           \\\n\t(((x) & BIT_MASK_RD_NAV_PROT_NXT_8822B)                                \\\n\t << BIT_SHIFT_RD_NAV_PROT_NXT_8822B)\n#define BITS_RD_NAV_PROT_NXT_8822B                                             \\\n\t(BIT_MASK_RD_NAV_PROT_NXT_8822B << BIT_SHIFT_RD_NAV_PROT_NXT_8822B)\n#define BIT_CLEAR_RD_NAV_PROT_NXT_8822B(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8822B))\n#define BIT_GET_RD_NAV_PROT_NXT_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8822B) &                            \\\n\t BIT_MASK_RD_NAV_PROT_NXT_8822B)\n#define BIT_SET_RD_NAV_PROT_NXT_8822B(x, v)                                    \\\n\t(BIT_CLEAR_RD_NAV_PROT_NXT_8822B(x) | BIT_RD_NAV_PROT_NXT_8822B(v))\n\n/* 2 REG_NAV_PROT_LEN_8822B */\n\n#define BIT_SHIFT_NAV_PROT_LEN_8822B 0\n#define BIT_MASK_NAV_PROT_LEN_8822B 0xffff\n#define BIT_NAV_PROT_LEN_8822B(x)                                              \\\n\t(((x) & BIT_MASK_NAV_PROT_LEN_8822B) << BIT_SHIFT_NAV_PROT_LEN_8822B)\n#define BITS_NAV_PROT_LEN_8822B                                                \\\n\t(BIT_MASK_NAV_PROT_LEN_8822B << BIT_SHIFT_NAV_PROT_LEN_8822B)\n#define BIT_CLEAR_NAV_PROT_LEN_8822B(x) ((x) & (~BITS_NAV_PROT_LEN_8822B))\n#define BIT_GET_NAV_PROT_LEN_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_NAV_PROT_LEN_8822B) & BIT_MASK_NAV_PROT_LEN_8822B)\n#define BIT_SET_NAV_PROT_LEN_8822B(x, v)                                       \\\n\t(BIT_CLEAR_NAV_PROT_LEN_8822B(x) | BIT_NAV_PROT_LEN_8822B(v))\n\n/* 2 REG_BCN_CTRL_8822B */\n#define BIT_DIS_RX_BSSID_FIT_8822B BIT(6)\n#define BIT_P0_EN_TXBCN_RPT_8822B BIT(5)\n#define BIT_DIS_TSF_UDT_8822B BIT(4)\n#define BIT_EN_BCN_FUNCTION_8822B BIT(3)\n#define BIT_P0_EN_RXBCN_RPT_8822B BIT(2)\n#define BIT_EN_P2P_CTWINDOW_8822B BIT(1)\n#define BIT_EN_P2P_BCNQ_AREA_8822B BIT(0)\n\n/* 2 REG_BCN_CTRL_CLINT0_8822B */\n#define BIT_CLI0_DIS_RX_BSSID_FIT_8822B BIT(6)\n#define BIT_CLI0_DIS_TSF_UDT_8822B BIT(4)\n#define BIT_CLI0_EN_BCN_FUNCTION_8822B BIT(3)\n#define BIT_CLI0_EN_RXBCN_RPT_8822B BIT(2)\n#define BIT_CLI0_ENP2P_CTWINDOW_8822B BIT(1)\n#define BIT_CLI0_ENP2P_BCNQ_AREA_8822B BIT(0)\n\n/* 2 REG_MBID_NUM_8822B */\n#define BIT_EN_PRE_DL_BEACON_8822B BIT(3)\n\n#define BIT_SHIFT_MBID_BCN_NUM_8822B 0\n#define BIT_MASK_MBID_BCN_NUM_8822B 0x7\n#define BIT_MBID_BCN_NUM_8822B(x)                                              \\\n\t(((x) & BIT_MASK_MBID_BCN_NUM_8822B) << BIT_SHIFT_MBID_BCN_NUM_8822B)\n#define BITS_MBID_BCN_NUM_8822B                                                \\\n\t(BIT_MASK_MBID_BCN_NUM_8822B << BIT_SHIFT_MBID_BCN_NUM_8822B)\n#define BIT_CLEAR_MBID_BCN_NUM_8822B(x) ((x) & (~BITS_MBID_BCN_NUM_8822B))\n#define BIT_GET_MBID_BCN_NUM_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_MBID_BCN_NUM_8822B) & BIT_MASK_MBID_BCN_NUM_8822B)\n#define BIT_SET_MBID_BCN_NUM_8822B(x, v)                                       \\\n\t(BIT_CLEAR_MBID_BCN_NUM_8822B(x) | BIT_MBID_BCN_NUM_8822B(v))\n\n/* 2 REG_DUAL_TSF_RST_8822B */\n#define BIT_FREECNT_RST_8822B BIT(5)\n#define BIT_TSFTR_CLI3_RST_8822B BIT(4)\n#define BIT_TSFTR_CLI2_RST_8822B BIT(3)\n#define BIT_TSFTR_CLI1_RST_8822B BIT(2)\n#define BIT_TSFTR_CLI0_RST_8822B BIT(1)\n#define BIT_TSFTR_RST_8822B BIT(0)\n\n/* 2 REG_MBSSID_BCN_SPACE_8822B */\n\n#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B 28\n#define BIT_MASK_BCN_TIMER_SEL_FWRD_8822B 0x7\n#define BIT_BCN_TIMER_SEL_FWRD_8822B(x)                                        \\\n\t(((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822B)                             \\\n\t << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B)\n#define BITS_BCN_TIMER_SEL_FWRD_8822B                                          \\\n\t(BIT_MASK_BCN_TIMER_SEL_FWRD_8822B                                     \\\n\t << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B)\n#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822B(x)                                  \\\n\t((x) & (~BITS_BCN_TIMER_SEL_FWRD_8822B))\n#define BIT_GET_BCN_TIMER_SEL_FWRD_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B) &                         \\\n\t BIT_MASK_BCN_TIMER_SEL_FWRD_8822B)\n#define BIT_SET_BCN_TIMER_SEL_FWRD_8822B(x, v)                                 \\\n\t(BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822B(x) |                               \\\n\t BIT_BCN_TIMER_SEL_FWRD_8822B(v))\n\n#define BIT_SHIFT_BCN_SPACE_CLINT0_8822B 16\n#define BIT_MASK_BCN_SPACE_CLINT0_8822B 0xfff\n#define BIT_BCN_SPACE_CLINT0_8822B(x)                                          \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT0_8822B)                               \\\n\t << BIT_SHIFT_BCN_SPACE_CLINT0_8822B)\n#define BITS_BCN_SPACE_CLINT0_8822B                                            \\\n\t(BIT_MASK_BCN_SPACE_CLINT0_8822B << BIT_SHIFT_BCN_SPACE_CLINT0_8822B)\n#define BIT_CLEAR_BCN_SPACE_CLINT0_8822B(x)                                    \\\n\t((x) & (~BITS_BCN_SPACE_CLINT0_8822B))\n#define BIT_GET_BCN_SPACE_CLINT0_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8822B) &                           \\\n\t BIT_MASK_BCN_SPACE_CLINT0_8822B)\n#define BIT_SET_BCN_SPACE_CLINT0_8822B(x, v)                                   \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT0_8822B(x) | BIT_BCN_SPACE_CLINT0_8822B(v))\n\n#define BIT_SHIFT_BCN_SPACE0_8822B 0\n#define BIT_MASK_BCN_SPACE0_8822B 0xffff\n#define BIT_BCN_SPACE0_8822B(x)                                                \\\n\t(((x) & BIT_MASK_BCN_SPACE0_8822B) << BIT_SHIFT_BCN_SPACE0_8822B)\n#define BITS_BCN_SPACE0_8822B                                                  \\\n\t(BIT_MASK_BCN_SPACE0_8822B << BIT_SHIFT_BCN_SPACE0_8822B)\n#define BIT_CLEAR_BCN_SPACE0_8822B(x) ((x) & (~BITS_BCN_SPACE0_8822B))\n#define BIT_GET_BCN_SPACE0_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE0_8822B) & BIT_MASK_BCN_SPACE0_8822B)\n#define BIT_SET_BCN_SPACE0_8822B(x, v)                                         \\\n\t(BIT_CLEAR_BCN_SPACE0_8822B(x) | BIT_BCN_SPACE0_8822B(v))\n\n/* 2 REG_DRVERLYINT_8822B */\n\n#define BIT_SHIFT_DRVERLYITV_8822B 0\n#define BIT_MASK_DRVERLYITV_8822B 0xff\n#define BIT_DRVERLYITV_8822B(x)                                                \\\n\t(((x) & BIT_MASK_DRVERLYITV_8822B) << BIT_SHIFT_DRVERLYITV_8822B)\n#define BITS_DRVERLYITV_8822B                                                  \\\n\t(BIT_MASK_DRVERLYITV_8822B << BIT_SHIFT_DRVERLYITV_8822B)\n#define BIT_CLEAR_DRVERLYITV_8822B(x) ((x) & (~BITS_DRVERLYITV_8822B))\n#define BIT_GET_DRVERLYITV_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_DRVERLYITV_8822B) & BIT_MASK_DRVERLYITV_8822B)\n#define BIT_SET_DRVERLYITV_8822B(x, v)                                         \\\n\t(BIT_CLEAR_DRVERLYITV_8822B(x) | BIT_DRVERLYITV_8822B(v))\n\n/* 2 REG_BCNDMATIM_8822B */\n\n#define BIT_SHIFT_BCNDMATIM_8822B 0\n#define BIT_MASK_BCNDMATIM_8822B 0xff\n#define BIT_BCNDMATIM_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_BCNDMATIM_8822B) << BIT_SHIFT_BCNDMATIM_8822B)\n#define BITS_BCNDMATIM_8822B                                                   \\\n\t(BIT_MASK_BCNDMATIM_8822B << BIT_SHIFT_BCNDMATIM_8822B)\n#define BIT_CLEAR_BCNDMATIM_8822B(x) ((x) & (~BITS_BCNDMATIM_8822B))\n#define BIT_GET_BCNDMATIM_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNDMATIM_8822B) & BIT_MASK_BCNDMATIM_8822B)\n#define BIT_SET_BCNDMATIM_8822B(x, v)                                          \\\n\t(BIT_CLEAR_BCNDMATIM_8822B(x) | BIT_BCNDMATIM_8822B(v))\n\n/* 2 REG_ATIMWND_8822B */\n\n#define BIT_SHIFT_ATIMWND0_8822B 0\n#define BIT_MASK_ATIMWND0_8822B 0xffff\n#define BIT_ATIMWND0_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND0_8822B) << BIT_SHIFT_ATIMWND0_8822B)\n#define BITS_ATIMWND0_8822B                                                    \\\n\t(BIT_MASK_ATIMWND0_8822B << BIT_SHIFT_ATIMWND0_8822B)\n#define BIT_CLEAR_ATIMWND0_8822B(x) ((x) & (~BITS_ATIMWND0_8822B))\n#define BIT_GET_ATIMWND0_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND0_8822B) & BIT_MASK_ATIMWND0_8822B)\n#define BIT_SET_ATIMWND0_8822B(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND0_8822B(x) | BIT_ATIMWND0_8822B(v))\n\n/* 2 REG_USTIME_TSF_8822B */\n\n#define BIT_SHIFT_USTIME_TSF_V1_8822B 0\n#define BIT_MASK_USTIME_TSF_V1_8822B 0xff\n#define BIT_USTIME_TSF_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_USTIME_TSF_V1_8822B) << BIT_SHIFT_USTIME_TSF_V1_8822B)\n#define BITS_USTIME_TSF_V1_8822B                                               \\\n\t(BIT_MASK_USTIME_TSF_V1_8822B << BIT_SHIFT_USTIME_TSF_V1_8822B)\n#define BIT_CLEAR_USTIME_TSF_V1_8822B(x) ((x) & (~BITS_USTIME_TSF_V1_8822B))\n#define BIT_GET_USTIME_TSF_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_USTIME_TSF_V1_8822B) & BIT_MASK_USTIME_TSF_V1_8822B)\n#define BIT_SET_USTIME_TSF_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_USTIME_TSF_V1_8822B(x) | BIT_USTIME_TSF_V1_8822B(v))\n\n/* 2 REG_BCN_MAX_ERR_8822B */\n\n#define BIT_SHIFT_BCN_MAX_ERR_8822B 0\n#define BIT_MASK_BCN_MAX_ERR_8822B 0xff\n#define BIT_BCN_MAX_ERR_8822B(x)                                               \\\n\t(((x) & BIT_MASK_BCN_MAX_ERR_8822B) << BIT_SHIFT_BCN_MAX_ERR_8822B)\n#define BITS_BCN_MAX_ERR_8822B                                                 \\\n\t(BIT_MASK_BCN_MAX_ERR_8822B << BIT_SHIFT_BCN_MAX_ERR_8822B)\n#define BIT_CLEAR_BCN_MAX_ERR_8822B(x) ((x) & (~BITS_BCN_MAX_ERR_8822B))\n#define BIT_GET_BCN_MAX_ERR_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_BCN_MAX_ERR_8822B) & BIT_MASK_BCN_MAX_ERR_8822B)\n#define BIT_SET_BCN_MAX_ERR_8822B(x, v)                                        \\\n\t(BIT_CLEAR_BCN_MAX_ERR_8822B(x) | BIT_BCN_MAX_ERR_8822B(v))\n\n/* 2 REG_RXTSF_OFFSET_CCK_8822B */\n\n#define BIT_SHIFT_CCK_RXTSF_OFFSET_8822B 0\n#define BIT_MASK_CCK_RXTSF_OFFSET_8822B 0xff\n#define BIT_CCK_RXTSF_OFFSET_8822B(x)                                          \\\n\t(((x) & BIT_MASK_CCK_RXTSF_OFFSET_8822B)                               \\\n\t << BIT_SHIFT_CCK_RXTSF_OFFSET_8822B)\n#define BITS_CCK_RXTSF_OFFSET_8822B                                            \\\n\t(BIT_MASK_CCK_RXTSF_OFFSET_8822B << BIT_SHIFT_CCK_RXTSF_OFFSET_8822B)\n#define BIT_CLEAR_CCK_RXTSF_OFFSET_8822B(x)                                    \\\n\t((x) & (~BITS_CCK_RXTSF_OFFSET_8822B))\n#define BIT_GET_CCK_RXTSF_OFFSET_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8822B) &                           \\\n\t BIT_MASK_CCK_RXTSF_OFFSET_8822B)\n#define BIT_SET_CCK_RXTSF_OFFSET_8822B(x, v)                                   \\\n\t(BIT_CLEAR_CCK_RXTSF_OFFSET_8822B(x) | BIT_CCK_RXTSF_OFFSET_8822B(v))\n\n/* 2 REG_RXTSF_OFFSET_OFDM_8822B */\n\n#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B 0\n#define BIT_MASK_OFDM_RXTSF_OFFSET_8822B 0xff\n#define BIT_OFDM_RXTSF_OFFSET_8822B(x)                                         \\\n\t(((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8822B)                              \\\n\t << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B)\n#define BITS_OFDM_RXTSF_OFFSET_8822B                                           \\\n\t(BIT_MASK_OFDM_RXTSF_OFFSET_8822B << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B)\n#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8822B(x)                                   \\\n\t((x) & (~BITS_OFDM_RXTSF_OFFSET_8822B))\n#define BIT_GET_OFDM_RXTSF_OFFSET_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B) &                          \\\n\t BIT_MASK_OFDM_RXTSF_OFFSET_8822B)\n#define BIT_SET_OFDM_RXTSF_OFFSET_8822B(x, v)                                  \\\n\t(BIT_CLEAR_OFDM_RXTSF_OFFSET_8822B(x) | BIT_OFDM_RXTSF_OFFSET_8822B(v))\n\n/* 2 REG_TSFTR_8822B */\n\n#define BIT_SHIFT_TSF_TIMER_8822B 0\n#define BIT_MASK_TSF_TIMER_8822B 0xffffffffffffffffL\n#define BIT_TSF_TIMER_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_TSF_TIMER_8822B) << BIT_SHIFT_TSF_TIMER_8822B)\n#define BITS_TSF_TIMER_8822B                                                   \\\n\t(BIT_MASK_TSF_TIMER_8822B << BIT_SHIFT_TSF_TIMER_8822B)\n#define BIT_CLEAR_TSF_TIMER_8822B(x) ((x) & (~BITS_TSF_TIMER_8822B))\n#define BIT_GET_TSF_TIMER_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_TSF_TIMER_8822B) & BIT_MASK_TSF_TIMER_8822B)\n#define BIT_SET_TSF_TIMER_8822B(x, v)                                          \\\n\t(BIT_CLEAR_TSF_TIMER_8822B(x) | BIT_TSF_TIMER_8822B(v))\n\n/* 2 REG_FREERUN_CNT_8822B */\n\n#define BIT_SHIFT_FREERUN_CNT_8822B 0\n#define BIT_MASK_FREERUN_CNT_8822B 0xffffffffffffffffL\n#define BIT_FREERUN_CNT_8822B(x)                                               \\\n\t(((x) & BIT_MASK_FREERUN_CNT_8822B) << BIT_SHIFT_FREERUN_CNT_8822B)\n#define BITS_FREERUN_CNT_8822B                                                 \\\n\t(BIT_MASK_FREERUN_CNT_8822B << BIT_SHIFT_FREERUN_CNT_8822B)\n#define BIT_CLEAR_FREERUN_CNT_8822B(x) ((x) & (~BITS_FREERUN_CNT_8822B))\n#define BIT_GET_FREERUN_CNT_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_FREERUN_CNT_8822B) & BIT_MASK_FREERUN_CNT_8822B)\n#define BIT_SET_FREERUN_CNT_8822B(x, v)                                        \\\n\t(BIT_CLEAR_FREERUN_CNT_8822B(x) | BIT_FREERUN_CNT_8822B(v))\n\n/* 2 REG_ATIMWND1_V1_8822B */\n\n#define BIT_SHIFT_ATIMWND1_V1_8822B 0\n#define BIT_MASK_ATIMWND1_V1_8822B 0xff\n#define BIT_ATIMWND1_V1_8822B(x)                                               \\\n\t(((x) & BIT_MASK_ATIMWND1_V1_8822B) << BIT_SHIFT_ATIMWND1_V1_8822B)\n#define BITS_ATIMWND1_V1_8822B                                                 \\\n\t(BIT_MASK_ATIMWND1_V1_8822B << BIT_SHIFT_ATIMWND1_V1_8822B)\n#define BIT_CLEAR_ATIMWND1_V1_8822B(x) ((x) & (~BITS_ATIMWND1_V1_8822B))\n#define BIT_GET_ATIMWND1_V1_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_ATIMWND1_V1_8822B) & BIT_MASK_ATIMWND1_V1_8822B)\n#define BIT_SET_ATIMWND1_V1_8822B(x, v)                                        \\\n\t(BIT_CLEAR_ATIMWND1_V1_8822B(x) | BIT_ATIMWND1_V1_8822B(v))\n\n/* 2 REG_TBTT_PROHIBIT_INFRA_8822B */\n\n#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B 0\n#define BIT_MASK_TBTT_PROHIBIT_INFRA_8822B 0xff\n#define BIT_TBTT_PROHIBIT_INFRA_8822B(x)                                       \\\n\t(((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822B)                            \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B)\n#define BITS_TBTT_PROHIBIT_INFRA_8822B                                         \\\n\t(BIT_MASK_TBTT_PROHIBIT_INFRA_8822B                                    \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B)\n#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822B(x)                                 \\\n\t((x) & (~BITS_TBTT_PROHIBIT_INFRA_8822B))\n#define BIT_GET_TBTT_PROHIBIT_INFRA_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B) &                        \\\n\t BIT_MASK_TBTT_PROHIBIT_INFRA_8822B)\n#define BIT_SET_TBTT_PROHIBIT_INFRA_8822B(x, v)                                \\\n\t(BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822B(x) |                              \\\n\t BIT_TBTT_PROHIBIT_INFRA_8822B(v))\n\n/* 2 REG_CTWND_8822B */\n\n#define BIT_SHIFT_CTWND_8822B 0\n#define BIT_MASK_CTWND_8822B 0xff\n#define BIT_CTWND_8822B(x)                                                     \\\n\t(((x) & BIT_MASK_CTWND_8822B) << BIT_SHIFT_CTWND_8822B)\n#define BITS_CTWND_8822B (BIT_MASK_CTWND_8822B << BIT_SHIFT_CTWND_8822B)\n#define BIT_CLEAR_CTWND_8822B(x) ((x) & (~BITS_CTWND_8822B))\n#define BIT_GET_CTWND_8822B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CTWND_8822B) & BIT_MASK_CTWND_8822B)\n#define BIT_SET_CTWND_8822B(x, v)                                              \\\n\t(BIT_CLEAR_CTWND_8822B(x) | BIT_CTWND_8822B(v))\n\n/* 2 REG_BCNIVLCUNT_8822B */\n\n#define BIT_SHIFT_BCNIVLCUNT_8822B 0\n#define BIT_MASK_BCNIVLCUNT_8822B 0x7f\n#define BIT_BCNIVLCUNT_8822B(x)                                                \\\n\t(((x) & BIT_MASK_BCNIVLCUNT_8822B) << BIT_SHIFT_BCNIVLCUNT_8822B)\n#define BITS_BCNIVLCUNT_8822B                                                  \\\n\t(BIT_MASK_BCNIVLCUNT_8822B << BIT_SHIFT_BCNIVLCUNT_8822B)\n#define BIT_CLEAR_BCNIVLCUNT_8822B(x) ((x) & (~BITS_BCNIVLCUNT_8822B))\n#define BIT_GET_BCNIVLCUNT_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_BCNIVLCUNT_8822B) & BIT_MASK_BCNIVLCUNT_8822B)\n#define BIT_SET_BCNIVLCUNT_8822B(x, v)                                         \\\n\t(BIT_CLEAR_BCNIVLCUNT_8822B(x) | BIT_BCNIVLCUNT_8822B(v))\n\n/* 2 REG_BCNDROPCTRL_8822B */\n#define BIT_BEACON_DROP_EN_8822B BIT(7)\n\n#define BIT_SHIFT_BEACON_DROP_IVL_8822B 0\n#define BIT_MASK_BEACON_DROP_IVL_8822B 0x7f\n#define BIT_BEACON_DROP_IVL_8822B(x)                                           \\\n\t(((x) & BIT_MASK_BEACON_DROP_IVL_8822B)                                \\\n\t << BIT_SHIFT_BEACON_DROP_IVL_8822B)\n#define BITS_BEACON_DROP_IVL_8822B                                             \\\n\t(BIT_MASK_BEACON_DROP_IVL_8822B << BIT_SHIFT_BEACON_DROP_IVL_8822B)\n#define BIT_CLEAR_BEACON_DROP_IVL_8822B(x) ((x) & (~BITS_BEACON_DROP_IVL_8822B))\n#define BIT_GET_BEACON_DROP_IVL_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_BEACON_DROP_IVL_8822B) &                            \\\n\t BIT_MASK_BEACON_DROP_IVL_8822B)\n#define BIT_SET_BEACON_DROP_IVL_8822B(x, v)                                    \\\n\t(BIT_CLEAR_BEACON_DROP_IVL_8822B(x) | BIT_BEACON_DROP_IVL_8822B(v))\n\n/* 2 REG_HGQ_TIMEOUT_PERIOD_8822B */\n\n#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B 0\n#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B 0xff\n#define BIT_HGQ_TIMEOUT_PERIOD_8822B(x)                                        \\\n\t(((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B)                             \\\n\t << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B)\n#define BITS_HGQ_TIMEOUT_PERIOD_8822B                                          \\\n\t(BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B                                     \\\n\t << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B)\n#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822B(x)                                  \\\n\t((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8822B))\n#define BIT_GET_HGQ_TIMEOUT_PERIOD_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B) &                         \\\n\t BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B)\n#define BIT_SET_HGQ_TIMEOUT_PERIOD_8822B(x, v)                                 \\\n\t(BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822B(x) |                               \\\n\t BIT_HGQ_TIMEOUT_PERIOD_8822B(v))\n\n/* 2 REG_TXCMD_TIMEOUT_PERIOD_8822B */\n\n#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B 0\n#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B 0xff\n#define BIT_TXCMD_TIMEOUT_PERIOD_8822B(x)                                      \\\n\t(((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B)                           \\\n\t << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B)\n#define BITS_TXCMD_TIMEOUT_PERIOD_8822B                                        \\\n\t(BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B                                   \\\n\t << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B)\n#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822B(x)                                \\\n\t((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8822B))\n#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B) &                       \\\n\t BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B)\n#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8822B(x, v)                               \\\n\t(BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822B(x) |                             \\\n\t BIT_TXCMD_TIMEOUT_PERIOD_8822B(v))\n\n/* 2 REG_MISC_CTRL_8822B */\n#define BIT_AUTO_SYNC_BY_TBTT_8822B BIT(6)\n#define BIT_DIS_TRX_CAL_BCN_8822B BIT(5)\n#define BIT_DIS_TX_CAL_TBTT_8822B BIT(4)\n#define BIT_EN_FREECNT_8822B BIT(3)\n#define BIT_BCN_AGGRESSION_8822B BIT(2)\n\n#define BIT_SHIFT_DIS_SECONDARY_CCA_8822B 0\n#define BIT_MASK_DIS_SECONDARY_CCA_8822B 0x3\n#define BIT_DIS_SECONDARY_CCA_8822B(x)                                         \\\n\t(((x) & BIT_MASK_DIS_SECONDARY_CCA_8822B)                              \\\n\t << BIT_SHIFT_DIS_SECONDARY_CCA_8822B)\n#define BITS_DIS_SECONDARY_CCA_8822B                                           \\\n\t(BIT_MASK_DIS_SECONDARY_CCA_8822B << BIT_SHIFT_DIS_SECONDARY_CCA_8822B)\n#define BIT_CLEAR_DIS_SECONDARY_CCA_8822B(x)                                   \\\n\t((x) & (~BITS_DIS_SECONDARY_CCA_8822B))\n#define BIT_GET_DIS_SECONDARY_CCA_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8822B) &                          \\\n\t BIT_MASK_DIS_SECONDARY_CCA_8822B)\n#define BIT_SET_DIS_SECONDARY_CCA_8822B(x, v)                                  \\\n\t(BIT_CLEAR_DIS_SECONDARY_CCA_8822B(x) | BIT_DIS_SECONDARY_CCA_8822B(v))\n\n/* 2 REG_BCN_CTRL_CLINT1_8822B */\n#define BIT_CLI1_DIS_RX_BSSID_FIT_8822B BIT(6)\n#define BIT_CLI1_DIS_TSF_UDT_8822B BIT(4)\n#define BIT_CLI1_EN_BCN_FUNCTION_8822B BIT(3)\n#define BIT_CLI1_EN_RXBCN_RPT_8822B BIT(2)\n#define BIT_CLI1_ENP2P_CTWINDOW_8822B BIT(1)\n#define BIT_CLI1_ENP2P_BCNQ_AREA_8822B BIT(0)\n\n/* 2 REG_BCN_CTRL_CLINT2_8822B */\n#define BIT_CLI2_DIS_RX_BSSID_FIT_8822B BIT(6)\n#define BIT_CLI2_DIS_TSF_UDT_8822B BIT(4)\n#define BIT_CLI2_EN_BCN_FUNCTION_8822B BIT(3)\n#define BIT_CLI2_EN_RXBCN_RPT_8822B BIT(2)\n#define BIT_CLI2_ENP2P_CTWINDOW_8822B BIT(1)\n#define BIT_CLI2_ENP2P_BCNQ_AREA_8822B BIT(0)\n\n/* 2 REG_BCN_CTRL_CLINT3_8822B */\n#define BIT_CLI3_DIS_RX_BSSID_FIT_8822B BIT(6)\n#define BIT_CLI3_DIS_TSF_UDT_8822B BIT(4)\n#define BIT_CLI3_EN_BCN_FUNCTION_8822B BIT(3)\n#define BIT_CLI3_EN_RXBCN_RPT_8822B BIT(2)\n#define BIT_CLI3_ENP2P_CTWINDOW_8822B BIT(1)\n#define BIT_CLI3_ENP2P_BCNQ_AREA_8822B BIT(0)\n\n/* 2 REG_EXTEND_CTRL_8822B */\n#define BIT_EN_TSFBIT32_RST_P2P2_8822B BIT(5)\n#define BIT_EN_TSFBIT32_RST_P2P1_8822B BIT(4)\n\n#define BIT_SHIFT_PORT_SEL_8822B 0\n#define BIT_MASK_PORT_SEL_8822B 0x7\n#define BIT_PORT_SEL_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_PORT_SEL_8822B) << BIT_SHIFT_PORT_SEL_8822B)\n#define BITS_PORT_SEL_8822B                                                    \\\n\t(BIT_MASK_PORT_SEL_8822B << BIT_SHIFT_PORT_SEL_8822B)\n#define BIT_CLEAR_PORT_SEL_8822B(x) ((x) & (~BITS_PORT_SEL_8822B))\n#define BIT_GET_PORT_SEL_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_PORT_SEL_8822B) & BIT_MASK_PORT_SEL_8822B)\n#define BIT_SET_PORT_SEL_8822B(x, v)                                           \\\n\t(BIT_CLEAR_PORT_SEL_8822B(x) | BIT_PORT_SEL_8822B(v))\n\n/* 2 REG_P2PPS1_SPEC_STATE_8822B */\n#define BIT_P2P1_SPEC_POWER_STATE_8822B BIT(7)\n#define BIT_P2P1_SPEC_CTWINDOW_ON_8822B BIT(6)\n#define BIT_P2P1_SPEC_BCN_AREA_ON_8822B BIT(5)\n#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8822B BIT(4)\n#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8822B BIT(3)\n#define BIT_P2P1_SPEC_FORCE_DOZE1_8822B BIT(2)\n#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8822B BIT(1)\n#define BIT_P2P1_SPEC_FORCE_DOZE0_8822B BIT(0)\n\n/* 2 REG_P2PPS1_STATE_8822B */\n#define BIT_P2P1_POWER_STATE_8822B BIT(7)\n#define BIT_P2P1_CTWINDOW_ON_8822B BIT(6)\n#define BIT_P2P1_BEACON_AREA_ON_8822B BIT(5)\n#define BIT_P2P1_CTWIN_EARLY_DISTX_8822B BIT(4)\n#define BIT_P2P1_NOA1_OFF_PERIOD_8822B BIT(3)\n#define BIT_P2P1_FORCE_DOZE1_8822B BIT(2)\n#define BIT_P2P1_NOA0_OFF_PERIOD_8822B BIT(1)\n#define BIT_P2P1_FORCE_DOZE0_8822B BIT(0)\n\n/* 2 REG_P2PPS2_SPEC_STATE_8822B */\n#define BIT_P2P2_SPEC_POWER_STATE_8822B BIT(7)\n#define BIT_P2P2_SPEC_CTWINDOW_ON_8822B BIT(6)\n#define BIT_P2P2_SPEC_BCN_AREA_ON_8822B BIT(5)\n#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8822B BIT(4)\n#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8822B BIT(3)\n#define BIT_P2P2_SPEC_FORCE_DOZE1_8822B BIT(2)\n#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8822B BIT(1)\n#define BIT_P2P2_SPEC_FORCE_DOZE0_8822B BIT(0)\n\n/* 2 REG_P2PPS2_STATE_8822B */\n#define BIT_P2P2_POWER_STATE_8822B BIT(7)\n#define BIT_P2P2_CTWINDOW_ON_8822B BIT(6)\n#define BIT_P2P2_BEACON_AREA_ON_8822B BIT(5)\n#define BIT_P2P2_CTWIN_EARLY_DISTX_8822B BIT(4)\n#define BIT_P2P2_NOA1_OFF_PERIOD_8822B BIT(3)\n#define BIT_P2P2_FORCE_DOZE1_8822B BIT(2)\n#define BIT_P2P2_NOA0_OFF_PERIOD_8822B BIT(1)\n#define BIT_P2P2_FORCE_DOZE0_8822B BIT(0)\n\n/* 2 REG_PS_TIMER0_8822B */\n\n#define BIT_SHIFT_PSTIMER0_INT_8822B 5\n#define BIT_MASK_PSTIMER0_INT_8822B 0x7ffffff\n#define BIT_PSTIMER0_INT_8822B(x)                                              \\\n\t(((x) & BIT_MASK_PSTIMER0_INT_8822B) << BIT_SHIFT_PSTIMER0_INT_8822B)\n#define BITS_PSTIMER0_INT_8822B                                                \\\n\t(BIT_MASK_PSTIMER0_INT_8822B << BIT_SHIFT_PSTIMER0_INT_8822B)\n#define BIT_CLEAR_PSTIMER0_INT_8822B(x) ((x) & (~BITS_PSTIMER0_INT_8822B))\n#define BIT_GET_PSTIMER0_INT_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_PSTIMER0_INT_8822B) & BIT_MASK_PSTIMER0_INT_8822B)\n#define BIT_SET_PSTIMER0_INT_8822B(x, v)                                       \\\n\t(BIT_CLEAR_PSTIMER0_INT_8822B(x) | BIT_PSTIMER0_INT_8822B(v))\n\n/* 2 REG_PS_TIMER1_8822B */\n\n#define BIT_SHIFT_PSTIMER1_INT_8822B 5\n#define BIT_MASK_PSTIMER1_INT_8822B 0x7ffffff\n#define BIT_PSTIMER1_INT_8822B(x)                                              \\\n\t(((x) & BIT_MASK_PSTIMER1_INT_8822B) << BIT_SHIFT_PSTIMER1_INT_8822B)\n#define BITS_PSTIMER1_INT_8822B                                                \\\n\t(BIT_MASK_PSTIMER1_INT_8822B << BIT_SHIFT_PSTIMER1_INT_8822B)\n#define BIT_CLEAR_PSTIMER1_INT_8822B(x) ((x) & (~BITS_PSTIMER1_INT_8822B))\n#define BIT_GET_PSTIMER1_INT_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_PSTIMER1_INT_8822B) & BIT_MASK_PSTIMER1_INT_8822B)\n#define BIT_SET_PSTIMER1_INT_8822B(x, v)                                       \\\n\t(BIT_CLEAR_PSTIMER1_INT_8822B(x) | BIT_PSTIMER1_INT_8822B(v))\n\n/* 2 REG_PS_TIMER2_8822B */\n\n#define BIT_SHIFT_PSTIMER2_INT_8822B 5\n#define BIT_MASK_PSTIMER2_INT_8822B 0x7ffffff\n#define BIT_PSTIMER2_INT_8822B(x)                                              \\\n\t(((x) & BIT_MASK_PSTIMER2_INT_8822B) << BIT_SHIFT_PSTIMER2_INT_8822B)\n#define BITS_PSTIMER2_INT_8822B                                                \\\n\t(BIT_MASK_PSTIMER2_INT_8822B << BIT_SHIFT_PSTIMER2_INT_8822B)\n#define BIT_CLEAR_PSTIMER2_INT_8822B(x) ((x) & (~BITS_PSTIMER2_INT_8822B))\n#define BIT_GET_PSTIMER2_INT_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_PSTIMER2_INT_8822B) & BIT_MASK_PSTIMER2_INT_8822B)\n#define BIT_SET_PSTIMER2_INT_8822B(x, v)                                       \\\n\t(BIT_CLEAR_PSTIMER2_INT_8822B(x) | BIT_PSTIMER2_INT_8822B(v))\n\n/* 2 REG_TBTT_CTN_AREA_8822B */\n\n#define BIT_SHIFT_TBTT_CTN_AREA_8822B 0\n#define BIT_MASK_TBTT_CTN_AREA_8822B 0xff\n#define BIT_TBTT_CTN_AREA_8822B(x)                                             \\\n\t(((x) & BIT_MASK_TBTT_CTN_AREA_8822B) << BIT_SHIFT_TBTT_CTN_AREA_8822B)\n#define BITS_TBTT_CTN_AREA_8822B                                               \\\n\t(BIT_MASK_TBTT_CTN_AREA_8822B << BIT_SHIFT_TBTT_CTN_AREA_8822B)\n#define BIT_CLEAR_TBTT_CTN_AREA_8822B(x) ((x) & (~BITS_TBTT_CTN_AREA_8822B))\n#define BIT_GET_TBTT_CTN_AREA_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TBTT_CTN_AREA_8822B) & BIT_MASK_TBTT_CTN_AREA_8822B)\n#define BIT_SET_TBTT_CTN_AREA_8822B(x, v)                                      \\\n\t(BIT_CLEAR_TBTT_CTN_AREA_8822B(x) | BIT_TBTT_CTN_AREA_8822B(v))\n\n/* 2 REG_FORCE_BCN_IFS_8822B */\n\n#define BIT_SHIFT_FORCE_BCN_IFS_8822B 0\n#define BIT_MASK_FORCE_BCN_IFS_8822B 0xff\n#define BIT_FORCE_BCN_IFS_8822B(x)                                             \\\n\t(((x) & BIT_MASK_FORCE_BCN_IFS_8822B) << BIT_SHIFT_FORCE_BCN_IFS_8822B)\n#define BITS_FORCE_BCN_IFS_8822B                                               \\\n\t(BIT_MASK_FORCE_BCN_IFS_8822B << BIT_SHIFT_FORCE_BCN_IFS_8822B)\n#define BIT_CLEAR_FORCE_BCN_IFS_8822B(x) ((x) & (~BITS_FORCE_BCN_IFS_8822B))\n#define BIT_GET_FORCE_BCN_IFS_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_FORCE_BCN_IFS_8822B) & BIT_MASK_FORCE_BCN_IFS_8822B)\n#define BIT_SET_FORCE_BCN_IFS_8822B(x, v)                                      \\\n\t(BIT_CLEAR_FORCE_BCN_IFS_8822B(x) | BIT_FORCE_BCN_IFS_8822B(v))\n\n/* 2 REG_TXOP_MIN_8822B */\n\n#define BIT_SHIFT_TXOP_MIN_8822B 0\n#define BIT_MASK_TXOP_MIN_8822B 0x3fff\n#define BIT_TXOP_MIN_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_TXOP_MIN_8822B) << BIT_SHIFT_TXOP_MIN_8822B)\n#define BITS_TXOP_MIN_8822B                                                    \\\n\t(BIT_MASK_TXOP_MIN_8822B << BIT_SHIFT_TXOP_MIN_8822B)\n#define BIT_CLEAR_TXOP_MIN_8822B(x) ((x) & (~BITS_TXOP_MIN_8822B))\n#define BIT_GET_TXOP_MIN_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXOP_MIN_8822B) & BIT_MASK_TXOP_MIN_8822B)\n#define BIT_SET_TXOP_MIN_8822B(x, v)                                           \\\n\t(BIT_CLEAR_TXOP_MIN_8822B(x) | BIT_TXOP_MIN_8822B(v))\n\n/* 2 REG_PRE_BKF_TIME_8822B */\n\n#define BIT_SHIFT_PRE_BKF_TIME_8822B 0\n#define BIT_MASK_PRE_BKF_TIME_8822B 0xff\n#define BIT_PRE_BKF_TIME_8822B(x)                                              \\\n\t(((x) & BIT_MASK_PRE_BKF_TIME_8822B) << BIT_SHIFT_PRE_BKF_TIME_8822B)\n#define BITS_PRE_BKF_TIME_8822B                                                \\\n\t(BIT_MASK_PRE_BKF_TIME_8822B << BIT_SHIFT_PRE_BKF_TIME_8822B)\n#define BIT_CLEAR_PRE_BKF_TIME_8822B(x) ((x) & (~BITS_PRE_BKF_TIME_8822B))\n#define BIT_GET_PRE_BKF_TIME_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_PRE_BKF_TIME_8822B) & BIT_MASK_PRE_BKF_TIME_8822B)\n#define BIT_SET_PRE_BKF_TIME_8822B(x, v)                                       \\\n\t(BIT_CLEAR_PRE_BKF_TIME_8822B(x) | BIT_PRE_BKF_TIME_8822B(v))\n\n/* 2 REG_CROSS_TXOP_CTRL_8822B */\n#define BIT_DTIM_BYPASS_8822B BIT(2)\n#define BIT_RTS_NAV_TXOP_8822B BIT(1)\n#define BIT_NOT_CROSS_TXOP_8822B BIT(0)\n\n/* 2 REG_ATIMWND2_8822B */\n\n#define BIT_SHIFT_ATIMWND2_8822B 0\n#define BIT_MASK_ATIMWND2_8822B 0xff\n#define BIT_ATIMWND2_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND2_8822B) << BIT_SHIFT_ATIMWND2_8822B)\n#define BITS_ATIMWND2_8822B                                                    \\\n\t(BIT_MASK_ATIMWND2_8822B << BIT_SHIFT_ATIMWND2_8822B)\n#define BIT_CLEAR_ATIMWND2_8822B(x) ((x) & (~BITS_ATIMWND2_8822B))\n#define BIT_GET_ATIMWND2_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND2_8822B) & BIT_MASK_ATIMWND2_8822B)\n#define BIT_SET_ATIMWND2_8822B(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND2_8822B(x) | BIT_ATIMWND2_8822B(v))\n\n/* 2 REG_ATIMWND3_8822B */\n\n#define BIT_SHIFT_ATIMWND3_8822B 0\n#define BIT_MASK_ATIMWND3_8822B 0xff\n#define BIT_ATIMWND3_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND3_8822B) << BIT_SHIFT_ATIMWND3_8822B)\n#define BITS_ATIMWND3_8822B                                                    \\\n\t(BIT_MASK_ATIMWND3_8822B << BIT_SHIFT_ATIMWND3_8822B)\n#define BIT_CLEAR_ATIMWND3_8822B(x) ((x) & (~BITS_ATIMWND3_8822B))\n#define BIT_GET_ATIMWND3_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND3_8822B) & BIT_MASK_ATIMWND3_8822B)\n#define BIT_SET_ATIMWND3_8822B(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND3_8822B(x) | BIT_ATIMWND3_8822B(v))\n\n/* 2 REG_ATIMWND4_8822B */\n\n#define BIT_SHIFT_ATIMWND4_8822B 0\n#define BIT_MASK_ATIMWND4_8822B 0xff\n#define BIT_ATIMWND4_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND4_8822B) << BIT_SHIFT_ATIMWND4_8822B)\n#define BITS_ATIMWND4_8822B                                                    \\\n\t(BIT_MASK_ATIMWND4_8822B << BIT_SHIFT_ATIMWND4_8822B)\n#define BIT_CLEAR_ATIMWND4_8822B(x) ((x) & (~BITS_ATIMWND4_8822B))\n#define BIT_GET_ATIMWND4_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND4_8822B) & BIT_MASK_ATIMWND4_8822B)\n#define BIT_SET_ATIMWND4_8822B(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND4_8822B(x) | BIT_ATIMWND4_8822B(v))\n\n/* 2 REG_ATIMWND5_8822B */\n\n#define BIT_SHIFT_ATIMWND5_8822B 0\n#define BIT_MASK_ATIMWND5_8822B 0xff\n#define BIT_ATIMWND5_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND5_8822B) << BIT_SHIFT_ATIMWND5_8822B)\n#define BITS_ATIMWND5_8822B                                                    \\\n\t(BIT_MASK_ATIMWND5_8822B << BIT_SHIFT_ATIMWND5_8822B)\n#define BIT_CLEAR_ATIMWND5_8822B(x) ((x) & (~BITS_ATIMWND5_8822B))\n#define BIT_GET_ATIMWND5_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND5_8822B) & BIT_MASK_ATIMWND5_8822B)\n#define BIT_SET_ATIMWND5_8822B(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND5_8822B(x) | BIT_ATIMWND5_8822B(v))\n\n/* 2 REG_ATIMWND6_8822B */\n\n#define BIT_SHIFT_ATIMWND6_8822B 0\n#define BIT_MASK_ATIMWND6_8822B 0xff\n#define BIT_ATIMWND6_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND6_8822B) << BIT_SHIFT_ATIMWND6_8822B)\n#define BITS_ATIMWND6_8822B                                                    \\\n\t(BIT_MASK_ATIMWND6_8822B << BIT_SHIFT_ATIMWND6_8822B)\n#define BIT_CLEAR_ATIMWND6_8822B(x) ((x) & (~BITS_ATIMWND6_8822B))\n#define BIT_GET_ATIMWND6_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND6_8822B) & BIT_MASK_ATIMWND6_8822B)\n#define BIT_SET_ATIMWND6_8822B(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND6_8822B(x) | BIT_ATIMWND6_8822B(v))\n\n/* 2 REG_ATIMWND7_8822B */\n\n#define BIT_SHIFT_ATIMWND7_8822B 0\n#define BIT_MASK_ATIMWND7_8822B 0xff\n#define BIT_ATIMWND7_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND7_8822B) << BIT_SHIFT_ATIMWND7_8822B)\n#define BITS_ATIMWND7_8822B                                                    \\\n\t(BIT_MASK_ATIMWND7_8822B << BIT_SHIFT_ATIMWND7_8822B)\n#define BIT_CLEAR_ATIMWND7_8822B(x) ((x) & (~BITS_ATIMWND7_8822B))\n#define BIT_GET_ATIMWND7_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND7_8822B) & BIT_MASK_ATIMWND7_8822B)\n#define BIT_SET_ATIMWND7_8822B(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND7_8822B(x) | BIT_ATIMWND7_8822B(v))\n\n/* 2 REG_ATIMUGT_8822B */\n\n#define BIT_SHIFT_ATIM_URGENT_8822B 0\n#define BIT_MASK_ATIM_URGENT_8822B 0xff\n#define BIT_ATIM_URGENT_8822B(x)                                               \\\n\t(((x) & BIT_MASK_ATIM_URGENT_8822B) << BIT_SHIFT_ATIM_URGENT_8822B)\n#define BITS_ATIM_URGENT_8822B                                                 \\\n\t(BIT_MASK_ATIM_URGENT_8822B << BIT_SHIFT_ATIM_URGENT_8822B)\n#define BIT_CLEAR_ATIM_URGENT_8822B(x) ((x) & (~BITS_ATIM_URGENT_8822B))\n#define BIT_GET_ATIM_URGENT_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_ATIM_URGENT_8822B) & BIT_MASK_ATIM_URGENT_8822B)\n#define BIT_SET_ATIM_URGENT_8822B(x, v)                                        \\\n\t(BIT_CLEAR_ATIM_URGENT_8822B(x) | BIT_ATIM_URGENT_8822B(v))\n\n/* 2 REG_HIQ_NO_LMT_EN_8822B */\n#define BIT_HIQ_NO_LMT_EN_VAP7_8822B BIT(7)\n#define BIT_HIQ_NO_LMT_EN_VAP6_8822B BIT(6)\n#define BIT_HIQ_NO_LMT_EN_VAP5_8822B BIT(5)\n#define BIT_HIQ_NO_LMT_EN_VAP4_8822B BIT(4)\n#define BIT_HIQ_NO_LMT_EN_VAP3_8822B BIT(3)\n#define BIT_HIQ_NO_LMT_EN_VAP2_8822B BIT(2)\n#define BIT_HIQ_NO_LMT_EN_VAP1_8822B BIT(1)\n#define BIT_HIQ_NO_LMT_EN_ROOT_8822B BIT(0)\n\n/* 2 REG_DTIM_COUNTER_ROOT_8822B */\n\n#define BIT_SHIFT_DTIM_COUNT_ROOT_8822B 0\n#define BIT_MASK_DTIM_COUNT_ROOT_8822B 0xff\n#define BIT_DTIM_COUNT_ROOT_8822B(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_ROOT_8822B)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_ROOT_8822B)\n#define BITS_DTIM_COUNT_ROOT_8822B                                             \\\n\t(BIT_MASK_DTIM_COUNT_ROOT_8822B << BIT_SHIFT_DTIM_COUNT_ROOT_8822B)\n#define BIT_CLEAR_DTIM_COUNT_ROOT_8822B(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8822B))\n#define BIT_GET_DTIM_COUNT_ROOT_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8822B) &                            \\\n\t BIT_MASK_DTIM_COUNT_ROOT_8822B)\n#define BIT_SET_DTIM_COUNT_ROOT_8822B(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_ROOT_8822B(x) | BIT_DTIM_COUNT_ROOT_8822B(v))\n\n/* 2 REG_DTIM_COUNTER_VAP1_8822B */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP1_8822B 0\n#define BIT_MASK_DTIM_COUNT_VAP1_8822B 0xff\n#define BIT_DTIM_COUNT_VAP1_8822B(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP1_8822B)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP1_8822B)\n#define BITS_DTIM_COUNT_VAP1_8822B                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP1_8822B << BIT_SHIFT_DTIM_COUNT_VAP1_8822B)\n#define BIT_CLEAR_DTIM_COUNT_VAP1_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8822B))\n#define BIT_GET_DTIM_COUNT_VAP1_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8822B) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP1_8822B)\n#define BIT_SET_DTIM_COUNT_VAP1_8822B(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP1_8822B(x) | BIT_DTIM_COUNT_VAP1_8822B(v))\n\n/* 2 REG_DTIM_COUNTER_VAP2_8822B */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP2_8822B 0\n#define BIT_MASK_DTIM_COUNT_VAP2_8822B 0xff\n#define BIT_DTIM_COUNT_VAP2_8822B(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP2_8822B)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP2_8822B)\n#define BITS_DTIM_COUNT_VAP2_8822B                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP2_8822B << BIT_SHIFT_DTIM_COUNT_VAP2_8822B)\n#define BIT_CLEAR_DTIM_COUNT_VAP2_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8822B))\n#define BIT_GET_DTIM_COUNT_VAP2_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8822B) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP2_8822B)\n#define BIT_SET_DTIM_COUNT_VAP2_8822B(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP2_8822B(x) | BIT_DTIM_COUNT_VAP2_8822B(v))\n\n/* 2 REG_DTIM_COUNTER_VAP3_8822B */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP3_8822B 0\n#define BIT_MASK_DTIM_COUNT_VAP3_8822B 0xff\n#define BIT_DTIM_COUNT_VAP3_8822B(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP3_8822B)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP3_8822B)\n#define BITS_DTIM_COUNT_VAP3_8822B                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP3_8822B << BIT_SHIFT_DTIM_COUNT_VAP3_8822B)\n#define BIT_CLEAR_DTIM_COUNT_VAP3_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8822B))\n#define BIT_GET_DTIM_COUNT_VAP3_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8822B) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP3_8822B)\n#define BIT_SET_DTIM_COUNT_VAP3_8822B(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP3_8822B(x) | BIT_DTIM_COUNT_VAP3_8822B(v))\n\n/* 2 REG_DTIM_COUNTER_VAP4_8822B */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP4_8822B 0\n#define BIT_MASK_DTIM_COUNT_VAP4_8822B 0xff\n#define BIT_DTIM_COUNT_VAP4_8822B(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP4_8822B)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP4_8822B)\n#define BITS_DTIM_COUNT_VAP4_8822B                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP4_8822B << BIT_SHIFT_DTIM_COUNT_VAP4_8822B)\n#define BIT_CLEAR_DTIM_COUNT_VAP4_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8822B))\n#define BIT_GET_DTIM_COUNT_VAP4_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8822B) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP4_8822B)\n#define BIT_SET_DTIM_COUNT_VAP4_8822B(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP4_8822B(x) | BIT_DTIM_COUNT_VAP4_8822B(v))\n\n/* 2 REG_DTIM_COUNTER_VAP5_8822B */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP5_8822B 0\n#define BIT_MASK_DTIM_COUNT_VAP5_8822B 0xff\n#define BIT_DTIM_COUNT_VAP5_8822B(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP5_8822B)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP5_8822B)\n#define BITS_DTIM_COUNT_VAP5_8822B                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP5_8822B << BIT_SHIFT_DTIM_COUNT_VAP5_8822B)\n#define BIT_CLEAR_DTIM_COUNT_VAP5_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8822B))\n#define BIT_GET_DTIM_COUNT_VAP5_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8822B) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP5_8822B)\n#define BIT_SET_DTIM_COUNT_VAP5_8822B(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP5_8822B(x) | BIT_DTIM_COUNT_VAP5_8822B(v))\n\n/* 2 REG_DTIM_COUNTER_VAP6_8822B */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP6_8822B 0\n#define BIT_MASK_DTIM_COUNT_VAP6_8822B 0xff\n#define BIT_DTIM_COUNT_VAP6_8822B(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP6_8822B)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP6_8822B)\n#define BITS_DTIM_COUNT_VAP6_8822B                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP6_8822B << BIT_SHIFT_DTIM_COUNT_VAP6_8822B)\n#define BIT_CLEAR_DTIM_COUNT_VAP6_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8822B))\n#define BIT_GET_DTIM_COUNT_VAP6_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8822B) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP6_8822B)\n#define BIT_SET_DTIM_COUNT_VAP6_8822B(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP6_8822B(x) | BIT_DTIM_COUNT_VAP6_8822B(v))\n\n/* 2 REG_DTIM_COUNTER_VAP7_8822B */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP7_8822B 0\n#define BIT_MASK_DTIM_COUNT_VAP7_8822B 0xff\n#define BIT_DTIM_COUNT_VAP7_8822B(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP7_8822B)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP7_8822B)\n#define BITS_DTIM_COUNT_VAP7_8822B                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP7_8822B << BIT_SHIFT_DTIM_COUNT_VAP7_8822B)\n#define BIT_CLEAR_DTIM_COUNT_VAP7_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8822B))\n#define BIT_GET_DTIM_COUNT_VAP7_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8822B) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP7_8822B)\n#define BIT_SET_DTIM_COUNT_VAP7_8822B(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP7_8822B(x) | BIT_DTIM_COUNT_VAP7_8822B(v))\n\n/* 2 REG_DIS_ATIM_8822B */\n#define BIT_DIS_ATIM_VAP7_8822B BIT(7)\n#define BIT_DIS_ATIM_VAP6_8822B BIT(6)\n#define BIT_DIS_ATIM_VAP5_8822B BIT(5)\n#define BIT_DIS_ATIM_VAP4_8822B BIT(4)\n#define BIT_DIS_ATIM_VAP3_8822B BIT(3)\n#define BIT_DIS_ATIM_VAP2_8822B BIT(2)\n#define BIT_DIS_ATIM_VAP1_8822B BIT(1)\n#define BIT_DIS_ATIM_ROOT_8822B BIT(0)\n\n/* 2 REG_EARLY_128US_8822B */\n\n#define BIT_SHIFT_TSFT_SEL_TIMER1_8822B 3\n#define BIT_MASK_TSFT_SEL_TIMER1_8822B 0x7\n#define BIT_TSFT_SEL_TIMER1_8822B(x)                                           \\\n\t(((x) & BIT_MASK_TSFT_SEL_TIMER1_8822B)                                \\\n\t << BIT_SHIFT_TSFT_SEL_TIMER1_8822B)\n#define BITS_TSFT_SEL_TIMER1_8822B                                             \\\n\t(BIT_MASK_TSFT_SEL_TIMER1_8822B << BIT_SHIFT_TSFT_SEL_TIMER1_8822B)\n#define BIT_CLEAR_TSFT_SEL_TIMER1_8822B(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8822B))\n#define BIT_GET_TSFT_SEL_TIMER1_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8822B) &                            \\\n\t BIT_MASK_TSFT_SEL_TIMER1_8822B)\n#define BIT_SET_TSFT_SEL_TIMER1_8822B(x, v)                                    \\\n\t(BIT_CLEAR_TSFT_SEL_TIMER1_8822B(x) | BIT_TSFT_SEL_TIMER1_8822B(v))\n\n#define BIT_SHIFT_EARLY_128US_8822B 0\n#define BIT_MASK_EARLY_128US_8822B 0x7\n#define BIT_EARLY_128US_8822B(x)                                               \\\n\t(((x) & BIT_MASK_EARLY_128US_8822B) << BIT_SHIFT_EARLY_128US_8822B)\n#define BITS_EARLY_128US_8822B                                                 \\\n\t(BIT_MASK_EARLY_128US_8822B << BIT_SHIFT_EARLY_128US_8822B)\n#define BIT_CLEAR_EARLY_128US_8822B(x) ((x) & (~BITS_EARLY_128US_8822B))\n#define BIT_GET_EARLY_128US_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_EARLY_128US_8822B) & BIT_MASK_EARLY_128US_8822B)\n#define BIT_SET_EARLY_128US_8822B(x, v)                                        \\\n\t(BIT_CLEAR_EARLY_128US_8822B(x) | BIT_EARLY_128US_8822B(v))\n\n/* 2 REG_P2PPS1_CTRL_8822B */\n#define BIT_P2P1_CTW_ALLSTASLEEP_8822B BIT(7)\n#define BIT_P2P1_OFF_DISTX_EN_8822B BIT(6)\n#define BIT_P2P1_PWR_MGT_EN_8822B BIT(5)\n#define BIT_P2P1_NOA1_EN_8822B BIT(2)\n#define BIT_P2P1_NOA0_EN_8822B BIT(1)\n\n/* 2 REG_P2PPS2_CTRL_8822B */\n#define BIT_P2P2_CTW_ALLSTASLEEP_8822B BIT(7)\n#define BIT_P2P2_OFF_DISTX_EN_8822B BIT(6)\n#define BIT_P2P2_PWR_MGT_EN_8822B BIT(5)\n#define BIT_P2P2_NOA1_EN_8822B BIT(2)\n#define BIT_P2P2_NOA0_EN_8822B BIT(1)\n\n/* 2 REG_TIMER0_SRC_SEL_8822B */\n\n#define BIT_SHIFT_SYNC_CLI_SEL_8822B 4\n#define BIT_MASK_SYNC_CLI_SEL_8822B 0x7\n#define BIT_SYNC_CLI_SEL_8822B(x)                                              \\\n\t(((x) & BIT_MASK_SYNC_CLI_SEL_8822B) << BIT_SHIFT_SYNC_CLI_SEL_8822B)\n#define BITS_SYNC_CLI_SEL_8822B                                                \\\n\t(BIT_MASK_SYNC_CLI_SEL_8822B << BIT_SHIFT_SYNC_CLI_SEL_8822B)\n#define BIT_CLEAR_SYNC_CLI_SEL_8822B(x) ((x) & (~BITS_SYNC_CLI_SEL_8822B))\n#define BIT_GET_SYNC_CLI_SEL_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SYNC_CLI_SEL_8822B) & BIT_MASK_SYNC_CLI_SEL_8822B)\n#define BIT_SET_SYNC_CLI_SEL_8822B(x, v)                                       \\\n\t(BIT_CLEAR_SYNC_CLI_SEL_8822B(x) | BIT_SYNC_CLI_SEL_8822B(v))\n\n#define BIT_SHIFT_TSFT_SEL_TIMER0_8822B 0\n#define BIT_MASK_TSFT_SEL_TIMER0_8822B 0x7\n#define BIT_TSFT_SEL_TIMER0_8822B(x)                                           \\\n\t(((x) & BIT_MASK_TSFT_SEL_TIMER0_8822B)                                \\\n\t << BIT_SHIFT_TSFT_SEL_TIMER0_8822B)\n#define BITS_TSFT_SEL_TIMER0_8822B                                             \\\n\t(BIT_MASK_TSFT_SEL_TIMER0_8822B << BIT_SHIFT_TSFT_SEL_TIMER0_8822B)\n#define BIT_CLEAR_TSFT_SEL_TIMER0_8822B(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8822B))\n#define BIT_GET_TSFT_SEL_TIMER0_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8822B) &                            \\\n\t BIT_MASK_TSFT_SEL_TIMER0_8822B)\n#define BIT_SET_TSFT_SEL_TIMER0_8822B(x, v)                                    \\\n\t(BIT_CLEAR_TSFT_SEL_TIMER0_8822B(x) | BIT_TSFT_SEL_TIMER0_8822B(v))\n\n/* 2 REG_NOA_UNIT_SEL_8822B */\n\n#define BIT_SHIFT_NOA_UNIT2_SEL_8822B 8\n#define BIT_MASK_NOA_UNIT2_SEL_8822B 0x7\n#define BIT_NOA_UNIT2_SEL_8822B(x)                                             \\\n\t(((x) & BIT_MASK_NOA_UNIT2_SEL_8822B) << BIT_SHIFT_NOA_UNIT2_SEL_8822B)\n#define BITS_NOA_UNIT2_SEL_8822B                                               \\\n\t(BIT_MASK_NOA_UNIT2_SEL_8822B << BIT_SHIFT_NOA_UNIT2_SEL_8822B)\n#define BIT_CLEAR_NOA_UNIT2_SEL_8822B(x) ((x) & (~BITS_NOA_UNIT2_SEL_8822B))\n#define BIT_GET_NOA_UNIT2_SEL_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8822B) & BIT_MASK_NOA_UNIT2_SEL_8822B)\n#define BIT_SET_NOA_UNIT2_SEL_8822B(x, v)                                      \\\n\t(BIT_CLEAR_NOA_UNIT2_SEL_8822B(x) | BIT_NOA_UNIT2_SEL_8822B(v))\n\n#define BIT_SHIFT_NOA_UNIT1_SEL_8822B 4\n#define BIT_MASK_NOA_UNIT1_SEL_8822B 0x7\n#define BIT_NOA_UNIT1_SEL_8822B(x)                                             \\\n\t(((x) & BIT_MASK_NOA_UNIT1_SEL_8822B) << BIT_SHIFT_NOA_UNIT1_SEL_8822B)\n#define BITS_NOA_UNIT1_SEL_8822B                                               \\\n\t(BIT_MASK_NOA_UNIT1_SEL_8822B << BIT_SHIFT_NOA_UNIT1_SEL_8822B)\n#define BIT_CLEAR_NOA_UNIT1_SEL_8822B(x) ((x) & (~BITS_NOA_UNIT1_SEL_8822B))\n#define BIT_GET_NOA_UNIT1_SEL_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8822B) & BIT_MASK_NOA_UNIT1_SEL_8822B)\n#define BIT_SET_NOA_UNIT1_SEL_8822B(x, v)                                      \\\n\t(BIT_CLEAR_NOA_UNIT1_SEL_8822B(x) | BIT_NOA_UNIT1_SEL_8822B(v))\n\n#define BIT_SHIFT_NOA_UNIT0_SEL_8822B 0\n#define BIT_MASK_NOA_UNIT0_SEL_8822B 0x7\n#define BIT_NOA_UNIT0_SEL_8822B(x)                                             \\\n\t(((x) & BIT_MASK_NOA_UNIT0_SEL_8822B) << BIT_SHIFT_NOA_UNIT0_SEL_8822B)\n#define BITS_NOA_UNIT0_SEL_8822B                                               \\\n\t(BIT_MASK_NOA_UNIT0_SEL_8822B << BIT_SHIFT_NOA_UNIT0_SEL_8822B)\n#define BIT_CLEAR_NOA_UNIT0_SEL_8822B(x) ((x) & (~BITS_NOA_UNIT0_SEL_8822B))\n#define BIT_GET_NOA_UNIT0_SEL_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8822B) & BIT_MASK_NOA_UNIT0_SEL_8822B)\n#define BIT_SET_NOA_UNIT0_SEL_8822B(x, v)                                      \\\n\t(BIT_CLEAR_NOA_UNIT0_SEL_8822B(x) | BIT_NOA_UNIT0_SEL_8822B(v))\n\n/* 2 REG_P2POFF_DIS_TXTIME_8822B */\n\n#define BIT_SHIFT_P2POFF_DIS_TXTIME_8822B 0\n#define BIT_MASK_P2POFF_DIS_TXTIME_8822B 0xff\n#define BIT_P2POFF_DIS_TXTIME_8822B(x)                                         \\\n\t(((x) & BIT_MASK_P2POFF_DIS_TXTIME_8822B)                              \\\n\t << BIT_SHIFT_P2POFF_DIS_TXTIME_8822B)\n#define BITS_P2POFF_DIS_TXTIME_8822B                                           \\\n\t(BIT_MASK_P2POFF_DIS_TXTIME_8822B << BIT_SHIFT_P2POFF_DIS_TXTIME_8822B)\n#define BIT_CLEAR_P2POFF_DIS_TXTIME_8822B(x)                                   \\\n\t((x) & (~BITS_P2POFF_DIS_TXTIME_8822B))\n#define BIT_GET_P2POFF_DIS_TXTIME_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8822B) &                          \\\n\t BIT_MASK_P2POFF_DIS_TXTIME_8822B)\n#define BIT_SET_P2POFF_DIS_TXTIME_8822B(x, v)                                  \\\n\t(BIT_CLEAR_P2POFF_DIS_TXTIME_8822B(x) | BIT_P2POFF_DIS_TXTIME_8822B(v))\n\n/* 2 REG_MBSSID_BCN_SPACE2_8822B */\n\n#define BIT_SHIFT_BCN_SPACE_CLINT2_8822B 16\n#define BIT_MASK_BCN_SPACE_CLINT2_8822B 0xfff\n#define BIT_BCN_SPACE_CLINT2_8822B(x)                                          \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT2_8822B)                               \\\n\t << BIT_SHIFT_BCN_SPACE_CLINT2_8822B)\n#define BITS_BCN_SPACE_CLINT2_8822B                                            \\\n\t(BIT_MASK_BCN_SPACE_CLINT2_8822B << BIT_SHIFT_BCN_SPACE_CLINT2_8822B)\n#define BIT_CLEAR_BCN_SPACE_CLINT2_8822B(x)                                    \\\n\t((x) & (~BITS_BCN_SPACE_CLINT2_8822B))\n#define BIT_GET_BCN_SPACE_CLINT2_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8822B) &                           \\\n\t BIT_MASK_BCN_SPACE_CLINT2_8822B)\n#define BIT_SET_BCN_SPACE_CLINT2_8822B(x, v)                                   \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT2_8822B(x) | BIT_BCN_SPACE_CLINT2_8822B(v))\n\n#define BIT_SHIFT_BCN_SPACE_CLINT1_8822B 0\n#define BIT_MASK_BCN_SPACE_CLINT1_8822B 0xfff\n#define BIT_BCN_SPACE_CLINT1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT1_8822B)                               \\\n\t << BIT_SHIFT_BCN_SPACE_CLINT1_8822B)\n#define BITS_BCN_SPACE_CLINT1_8822B                                            \\\n\t(BIT_MASK_BCN_SPACE_CLINT1_8822B << BIT_SHIFT_BCN_SPACE_CLINT1_8822B)\n#define BIT_CLEAR_BCN_SPACE_CLINT1_8822B(x)                                    \\\n\t((x) & (~BITS_BCN_SPACE_CLINT1_8822B))\n#define BIT_GET_BCN_SPACE_CLINT1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8822B) &                           \\\n\t BIT_MASK_BCN_SPACE_CLINT1_8822B)\n#define BIT_SET_BCN_SPACE_CLINT1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT1_8822B(x) | BIT_BCN_SPACE_CLINT1_8822B(v))\n\n/* 2 REG_MBSSID_BCN_SPACE3_8822B */\n\n#define BIT_SHIFT_SUB_BCN_SPACE_8822B 16\n#define BIT_MASK_SUB_BCN_SPACE_8822B 0xff\n#define BIT_SUB_BCN_SPACE_8822B(x)                                             \\\n\t(((x) & BIT_MASK_SUB_BCN_SPACE_8822B) << BIT_SHIFT_SUB_BCN_SPACE_8822B)\n#define BITS_SUB_BCN_SPACE_8822B                                               \\\n\t(BIT_MASK_SUB_BCN_SPACE_8822B << BIT_SHIFT_SUB_BCN_SPACE_8822B)\n#define BIT_CLEAR_SUB_BCN_SPACE_8822B(x) ((x) & (~BITS_SUB_BCN_SPACE_8822B))\n#define BIT_GET_SUB_BCN_SPACE_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SUB_BCN_SPACE_8822B) & BIT_MASK_SUB_BCN_SPACE_8822B)\n#define BIT_SET_SUB_BCN_SPACE_8822B(x, v)                                      \\\n\t(BIT_CLEAR_SUB_BCN_SPACE_8822B(x) | BIT_SUB_BCN_SPACE_8822B(v))\n\n#define BIT_SHIFT_BCN_SPACE_CLINT3_8822B 0\n#define BIT_MASK_BCN_SPACE_CLINT3_8822B 0xfff\n#define BIT_BCN_SPACE_CLINT3_8822B(x)                                          \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT3_8822B)                               \\\n\t << BIT_SHIFT_BCN_SPACE_CLINT3_8822B)\n#define BITS_BCN_SPACE_CLINT3_8822B                                            \\\n\t(BIT_MASK_BCN_SPACE_CLINT3_8822B << BIT_SHIFT_BCN_SPACE_CLINT3_8822B)\n#define BIT_CLEAR_BCN_SPACE_CLINT3_8822B(x)                                    \\\n\t((x) & (~BITS_BCN_SPACE_CLINT3_8822B))\n#define BIT_GET_BCN_SPACE_CLINT3_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8822B) &                           \\\n\t BIT_MASK_BCN_SPACE_CLINT3_8822B)\n#define BIT_SET_BCN_SPACE_CLINT3_8822B(x, v)                                   \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT3_8822B(x) | BIT_BCN_SPACE_CLINT3_8822B(v))\n\n/* 2 REG_ACMHWCTRL_8822B */\n#define BIT_BEQ_ACM_STATUS_8822B BIT(7)\n#define BIT_VIQ_ACM_STATUS_8822B BIT(6)\n#define BIT_VOQ_ACM_STATUS_8822B BIT(5)\n#define BIT_BEQ_ACM_EN_8822B BIT(3)\n#define BIT_VIQ_ACM_EN_8822B BIT(2)\n#define BIT_VOQ_ACM_EN_8822B BIT(1)\n#define BIT_ACMHWEN_8822B BIT(0)\n\n/* 2 REG_ACMRSTCTRL_8822B */\n#define BIT_BE_ACM_RESET_USED_TIME_8822B BIT(2)\n#define BIT_VI_ACM_RESET_USED_TIME_8822B BIT(1)\n#define BIT_VO_ACM_RESET_USED_TIME_8822B BIT(0)\n\n/* 2 REG_ACMAVG_8822B */\n\n#define BIT_SHIFT_AVGPERIOD_8822B 0\n#define BIT_MASK_AVGPERIOD_8822B 0xffff\n#define BIT_AVGPERIOD_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_AVGPERIOD_8822B) << BIT_SHIFT_AVGPERIOD_8822B)\n#define BITS_AVGPERIOD_8822B                                                   \\\n\t(BIT_MASK_AVGPERIOD_8822B << BIT_SHIFT_AVGPERIOD_8822B)\n#define BIT_CLEAR_AVGPERIOD_8822B(x) ((x) & (~BITS_AVGPERIOD_8822B))\n#define BIT_GET_AVGPERIOD_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_AVGPERIOD_8822B) & BIT_MASK_AVGPERIOD_8822B)\n#define BIT_SET_AVGPERIOD_8822B(x, v)                                          \\\n\t(BIT_CLEAR_AVGPERIOD_8822B(x) | BIT_AVGPERIOD_8822B(v))\n\n/* 2 REG_VO_ADMTIME_8822B */\n\n#define BIT_SHIFT_VO_ADMITTED_TIME_8822B 0\n#define BIT_MASK_VO_ADMITTED_TIME_8822B 0xffff\n#define BIT_VO_ADMITTED_TIME_8822B(x)                                          \\\n\t(((x) & BIT_MASK_VO_ADMITTED_TIME_8822B)                               \\\n\t << BIT_SHIFT_VO_ADMITTED_TIME_8822B)\n#define BITS_VO_ADMITTED_TIME_8822B                                            \\\n\t(BIT_MASK_VO_ADMITTED_TIME_8822B << BIT_SHIFT_VO_ADMITTED_TIME_8822B)\n#define BIT_CLEAR_VO_ADMITTED_TIME_8822B(x)                                    \\\n\t((x) & (~BITS_VO_ADMITTED_TIME_8822B))\n#define BIT_GET_VO_ADMITTED_TIME_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8822B) &                           \\\n\t BIT_MASK_VO_ADMITTED_TIME_8822B)\n#define BIT_SET_VO_ADMITTED_TIME_8822B(x, v)                                   \\\n\t(BIT_CLEAR_VO_ADMITTED_TIME_8822B(x) | BIT_VO_ADMITTED_TIME_8822B(v))\n\n/* 2 REG_VI_ADMTIME_8822B */\n\n#define BIT_SHIFT_VI_ADMITTED_TIME_8822B 0\n#define BIT_MASK_VI_ADMITTED_TIME_8822B 0xffff\n#define BIT_VI_ADMITTED_TIME_8822B(x)                                          \\\n\t(((x) & BIT_MASK_VI_ADMITTED_TIME_8822B)                               \\\n\t << BIT_SHIFT_VI_ADMITTED_TIME_8822B)\n#define BITS_VI_ADMITTED_TIME_8822B                                            \\\n\t(BIT_MASK_VI_ADMITTED_TIME_8822B << BIT_SHIFT_VI_ADMITTED_TIME_8822B)\n#define BIT_CLEAR_VI_ADMITTED_TIME_8822B(x)                                    \\\n\t((x) & (~BITS_VI_ADMITTED_TIME_8822B))\n#define BIT_GET_VI_ADMITTED_TIME_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8822B) &                           \\\n\t BIT_MASK_VI_ADMITTED_TIME_8822B)\n#define BIT_SET_VI_ADMITTED_TIME_8822B(x, v)                                   \\\n\t(BIT_CLEAR_VI_ADMITTED_TIME_8822B(x) | BIT_VI_ADMITTED_TIME_8822B(v))\n\n/* 2 REG_BE_ADMTIME_8822B */\n\n#define BIT_SHIFT_BE_ADMITTED_TIME_8822B 0\n#define BIT_MASK_BE_ADMITTED_TIME_8822B 0xffff\n#define BIT_BE_ADMITTED_TIME_8822B(x)                                          \\\n\t(((x) & BIT_MASK_BE_ADMITTED_TIME_8822B)                               \\\n\t << BIT_SHIFT_BE_ADMITTED_TIME_8822B)\n#define BITS_BE_ADMITTED_TIME_8822B                                            \\\n\t(BIT_MASK_BE_ADMITTED_TIME_8822B << BIT_SHIFT_BE_ADMITTED_TIME_8822B)\n#define BIT_CLEAR_BE_ADMITTED_TIME_8822B(x)                                    \\\n\t((x) & (~BITS_BE_ADMITTED_TIME_8822B))\n#define BIT_GET_BE_ADMITTED_TIME_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8822B) &                           \\\n\t BIT_MASK_BE_ADMITTED_TIME_8822B)\n#define BIT_SET_BE_ADMITTED_TIME_8822B(x, v)                                   \\\n\t(BIT_CLEAR_BE_ADMITTED_TIME_8822B(x) | BIT_BE_ADMITTED_TIME_8822B(v))\n\n/* 2 REG_EDCA_RANDOM_GEN_8822B */\n\n#define BIT_SHIFT_RANDOM_GEN_8822B 0\n#define BIT_MASK_RANDOM_GEN_8822B 0xffffff\n#define BIT_RANDOM_GEN_8822B(x)                                                \\\n\t(((x) & BIT_MASK_RANDOM_GEN_8822B) << BIT_SHIFT_RANDOM_GEN_8822B)\n#define BITS_RANDOM_GEN_8822B                                                  \\\n\t(BIT_MASK_RANDOM_GEN_8822B << BIT_SHIFT_RANDOM_GEN_8822B)\n#define BIT_CLEAR_RANDOM_GEN_8822B(x) ((x) & (~BITS_RANDOM_GEN_8822B))\n#define BIT_GET_RANDOM_GEN_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_RANDOM_GEN_8822B) & BIT_MASK_RANDOM_GEN_8822B)\n#define BIT_SET_RANDOM_GEN_8822B(x, v)                                         \\\n\t(BIT_CLEAR_RANDOM_GEN_8822B(x) | BIT_RANDOM_GEN_8822B(v))\n\n/* 2 REG_TXCMD_NOA_SEL_8822B */\n\n#define BIT_SHIFT_NOA_SEL_V2_8822B 4\n#define BIT_MASK_NOA_SEL_V2_8822B 0x7\n#define BIT_NOA_SEL_V2_8822B(x)                                                \\\n\t(((x) & BIT_MASK_NOA_SEL_V2_8822B) << BIT_SHIFT_NOA_SEL_V2_8822B)\n#define BITS_NOA_SEL_V2_8822B                                                  \\\n\t(BIT_MASK_NOA_SEL_V2_8822B << BIT_SHIFT_NOA_SEL_V2_8822B)\n#define BIT_CLEAR_NOA_SEL_V2_8822B(x) ((x) & (~BITS_NOA_SEL_V2_8822B))\n#define BIT_GET_NOA_SEL_V2_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_NOA_SEL_V2_8822B) & BIT_MASK_NOA_SEL_V2_8822B)\n#define BIT_SET_NOA_SEL_V2_8822B(x, v)                                         \\\n\t(BIT_CLEAR_NOA_SEL_V2_8822B(x) | BIT_NOA_SEL_V2_8822B(v))\n\n#define BIT_SHIFT_TXCMD_SEG_SEL_8822B 0\n#define BIT_MASK_TXCMD_SEG_SEL_8822B 0xf\n#define BIT_TXCMD_SEG_SEL_8822B(x)                                             \\\n\t(((x) & BIT_MASK_TXCMD_SEG_SEL_8822B) << BIT_SHIFT_TXCMD_SEG_SEL_8822B)\n#define BITS_TXCMD_SEG_SEL_8822B                                               \\\n\t(BIT_MASK_TXCMD_SEG_SEL_8822B << BIT_SHIFT_TXCMD_SEG_SEL_8822B)\n#define BIT_CLEAR_TXCMD_SEG_SEL_8822B(x) ((x) & (~BITS_TXCMD_SEG_SEL_8822B))\n#define BIT_GET_TXCMD_SEG_SEL_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8822B) & BIT_MASK_TXCMD_SEG_SEL_8822B)\n#define BIT_SET_TXCMD_SEG_SEL_8822B(x, v)                                      \\\n\t(BIT_CLEAR_TXCMD_SEG_SEL_8822B(x) | BIT_TXCMD_SEG_SEL_8822B(v))\n\n/* 2 REG_NOA_PARAM_8822B */\n\n#define BIT_SHIFT_NOA_COUNT_8822B (96 & CPU_OPT_WIDTH)\n#define BIT_MASK_NOA_COUNT_8822B 0xff\n#define BIT_NOA_COUNT_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_NOA_COUNT_8822B) << BIT_SHIFT_NOA_COUNT_8822B)\n#define BITS_NOA_COUNT_8822B                                                   \\\n\t(BIT_MASK_NOA_COUNT_8822B << BIT_SHIFT_NOA_COUNT_8822B)\n#define BIT_CLEAR_NOA_COUNT_8822B(x) ((x) & (~BITS_NOA_COUNT_8822B))\n#define BIT_GET_NOA_COUNT_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_NOA_COUNT_8822B) & BIT_MASK_NOA_COUNT_8822B)\n#define BIT_SET_NOA_COUNT_8822B(x, v)                                          \\\n\t(BIT_CLEAR_NOA_COUNT_8822B(x) | BIT_NOA_COUNT_8822B(v))\n\n#define BIT_SHIFT_NOA_START_TIME_8822B (64 & CPU_OPT_WIDTH)\n#define BIT_MASK_NOA_START_TIME_8822B 0xffffffffL\n#define BIT_NOA_START_TIME_8822B(x)                                            \\\n\t(((x) & BIT_MASK_NOA_START_TIME_8822B)                                 \\\n\t << BIT_SHIFT_NOA_START_TIME_8822B)\n#define BITS_NOA_START_TIME_8822B                                              \\\n\t(BIT_MASK_NOA_START_TIME_8822B << BIT_SHIFT_NOA_START_TIME_8822B)\n#define BIT_CLEAR_NOA_START_TIME_8822B(x) ((x) & (~BITS_NOA_START_TIME_8822B))\n#define BIT_GET_NOA_START_TIME_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_NOA_START_TIME_8822B) &                             \\\n\t BIT_MASK_NOA_START_TIME_8822B)\n#define BIT_SET_NOA_START_TIME_8822B(x, v)                                     \\\n\t(BIT_CLEAR_NOA_START_TIME_8822B(x) | BIT_NOA_START_TIME_8822B(v))\n\n#define BIT_SHIFT_NOA_INTERVAL_8822B (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_NOA_INTERVAL_8822B 0xffffffffL\n#define BIT_NOA_INTERVAL_8822B(x)                                              \\\n\t(((x) & BIT_MASK_NOA_INTERVAL_8822B) << BIT_SHIFT_NOA_INTERVAL_8822B)\n#define BITS_NOA_INTERVAL_8822B                                                \\\n\t(BIT_MASK_NOA_INTERVAL_8822B << BIT_SHIFT_NOA_INTERVAL_8822B)\n#define BIT_CLEAR_NOA_INTERVAL_8822B(x) ((x) & (~BITS_NOA_INTERVAL_8822B))\n#define BIT_GET_NOA_INTERVAL_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_NOA_INTERVAL_8822B) & BIT_MASK_NOA_INTERVAL_8822B)\n#define BIT_SET_NOA_INTERVAL_8822B(x, v)                                       \\\n\t(BIT_CLEAR_NOA_INTERVAL_8822B(x) | BIT_NOA_INTERVAL_8822B(v))\n\n#define BIT_SHIFT_NOA_DURATION_8822B 0\n#define BIT_MASK_NOA_DURATION_8822B 0xffffffffL\n#define BIT_NOA_DURATION_8822B(x)                                              \\\n\t(((x) & BIT_MASK_NOA_DURATION_8822B) << BIT_SHIFT_NOA_DURATION_8822B)\n#define BITS_NOA_DURATION_8822B                                                \\\n\t(BIT_MASK_NOA_DURATION_8822B << BIT_SHIFT_NOA_DURATION_8822B)\n#define BIT_CLEAR_NOA_DURATION_8822B(x) ((x) & (~BITS_NOA_DURATION_8822B))\n#define BIT_GET_NOA_DURATION_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_NOA_DURATION_8822B) & BIT_MASK_NOA_DURATION_8822B)\n#define BIT_SET_NOA_DURATION_8822B(x, v)                                       \\\n\t(BIT_CLEAR_NOA_DURATION_8822B(x) | BIT_NOA_DURATION_8822B(v))\n\n/* 2 REG_P2P_RST_8822B */\n#define BIT_P2P2_PWR_RST1_8822B BIT(5)\n#define BIT_P2P2_PWR_RST0_8822B BIT(4)\n#define BIT_P2P1_PWR_RST1_8822B BIT(3)\n#define BIT_P2P1_PWR_RST0_8822B BIT(2)\n#define BIT_P2P_PWR_RST1_V1_8822B BIT(1)\n#define BIT_P2P_PWR_RST0_V1_8822B BIT(0)\n\n/* 2 REG_SCHEDULER_RST_8822B */\n#define BIT_SYNC_CLI_ONCE_RIGHT_NOW_8822B BIT(2)\n#define BIT_SYNC_CLI_ONCE_BY_TBTT_8822B BIT(1)\n#define BIT_SCHEDULER_RST_V1_8822B BIT(0)\n\n/* 2 REG_SCH_TXCMD_8822B */\n\n#define BIT_SHIFT_SCH_TXCMD_8822B 0\n#define BIT_MASK_SCH_TXCMD_8822B 0xffffffffL\n#define BIT_SCH_TXCMD_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_SCH_TXCMD_8822B) << BIT_SHIFT_SCH_TXCMD_8822B)\n#define BITS_SCH_TXCMD_8822B                                                   \\\n\t(BIT_MASK_SCH_TXCMD_8822B << BIT_SHIFT_SCH_TXCMD_8822B)\n#define BIT_CLEAR_SCH_TXCMD_8822B(x) ((x) & (~BITS_SCH_TXCMD_8822B))\n#define BIT_GET_SCH_TXCMD_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_SCH_TXCMD_8822B) & BIT_MASK_SCH_TXCMD_8822B)\n#define BIT_SET_SCH_TXCMD_8822B(x, v)                                          \\\n\t(BIT_CLEAR_SCH_TXCMD_8822B(x) | BIT_SCH_TXCMD_8822B(v))\n\n/* 2 REG_PAGE5_DUMMY_8822B */\n\n/* 2 REG_CPUMGQ_TX_TIMER_8822B */\n\n#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B 0\n#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B 0xffffffffL\n#define BIT_CPUMGQ_TX_TIMER_V1_8822B(x)                                        \\\n\t(((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B)                             \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B)\n#define BITS_CPUMGQ_TX_TIMER_V1_8822B                                          \\\n\t(BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B                                     \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B)\n#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822B(x)                                  \\\n\t((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8822B))\n#define BIT_GET_CPUMGQ_TX_TIMER_V1_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B) &                         \\\n\t BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B)\n#define BIT_SET_CPUMGQ_TX_TIMER_V1_8822B(x, v)                                 \\\n\t(BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822B(x) |                               \\\n\t BIT_CPUMGQ_TX_TIMER_V1_8822B(v))\n\n/* 2 REG_PS_TIMER_A_8822B */\n\n#define BIT_SHIFT_PS_TIMER_A_V1_8822B 0\n#define BIT_MASK_PS_TIMER_A_V1_8822B 0xffffffffL\n#define BIT_PS_TIMER_A_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_PS_TIMER_A_V1_8822B) << BIT_SHIFT_PS_TIMER_A_V1_8822B)\n#define BITS_PS_TIMER_A_V1_8822B                                               \\\n\t(BIT_MASK_PS_TIMER_A_V1_8822B << BIT_SHIFT_PS_TIMER_A_V1_8822B)\n#define BIT_CLEAR_PS_TIMER_A_V1_8822B(x) ((x) & (~BITS_PS_TIMER_A_V1_8822B))\n#define BIT_GET_PS_TIMER_A_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_A_V1_8822B) & BIT_MASK_PS_TIMER_A_V1_8822B)\n#define BIT_SET_PS_TIMER_A_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_PS_TIMER_A_V1_8822B(x) | BIT_PS_TIMER_A_V1_8822B(v))\n\n/* 2 REG_PS_TIMER_B_8822B */\n\n#define BIT_SHIFT_PS_TIMER_B_V1_8822B 0\n#define BIT_MASK_PS_TIMER_B_V1_8822B 0xffffffffL\n#define BIT_PS_TIMER_B_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_PS_TIMER_B_V1_8822B) << BIT_SHIFT_PS_TIMER_B_V1_8822B)\n#define BITS_PS_TIMER_B_V1_8822B                                               \\\n\t(BIT_MASK_PS_TIMER_B_V1_8822B << BIT_SHIFT_PS_TIMER_B_V1_8822B)\n#define BIT_CLEAR_PS_TIMER_B_V1_8822B(x) ((x) & (~BITS_PS_TIMER_B_V1_8822B))\n#define BIT_GET_PS_TIMER_B_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_B_V1_8822B) & BIT_MASK_PS_TIMER_B_V1_8822B)\n#define BIT_SET_PS_TIMER_B_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_PS_TIMER_B_V1_8822B(x) | BIT_PS_TIMER_B_V1_8822B(v))\n\n/* 2 REG_PS_TIMER_C_8822B */\n\n#define BIT_SHIFT_PS_TIMER_C_V1_8822B 0\n#define BIT_MASK_PS_TIMER_C_V1_8822B 0xffffffffL\n#define BIT_PS_TIMER_C_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_PS_TIMER_C_V1_8822B) << BIT_SHIFT_PS_TIMER_C_V1_8822B)\n#define BITS_PS_TIMER_C_V1_8822B                                               \\\n\t(BIT_MASK_PS_TIMER_C_V1_8822B << BIT_SHIFT_PS_TIMER_C_V1_8822B)\n#define BIT_CLEAR_PS_TIMER_C_V1_8822B(x) ((x) & (~BITS_PS_TIMER_C_V1_8822B))\n#define BIT_GET_PS_TIMER_C_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_C_V1_8822B) & BIT_MASK_PS_TIMER_C_V1_8822B)\n#define BIT_SET_PS_TIMER_C_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_PS_TIMER_C_V1_8822B(x) | BIT_PS_TIMER_C_V1_8822B(v))\n\n/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822B */\n#define BIT_CPUMGQ_TIMER_EN_8822B BIT(31)\n#define BIT_CPUMGQ_TX_EN_8822B BIT(28)\n\n#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B 24\n#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B 0x7\n#define BIT_CPUMGQ_TIMER_TSF_SEL_8822B(x)                                      \\\n\t(((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B)                           \\\n\t << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B)\n#define BITS_CPUMGQ_TIMER_TSF_SEL_8822B                                        \\\n\t(BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B                                   \\\n\t << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B)\n#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822B(x)                                \\\n\t((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8822B))\n#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B) &                       \\\n\t BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B)\n#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8822B(x, v)                               \\\n\t(BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822B(x) |                             \\\n\t BIT_CPUMGQ_TIMER_TSF_SEL_8822B(v))\n\n#define BIT_PS_TIMER_C_EN_8822B BIT(23)\n\n#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B 16\n#define BIT_MASK_PS_TIMER_C_TSF_SEL_8822B 0x7\n#define BIT_PS_TIMER_C_TSF_SEL_8822B(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822B)                             \\\n\t << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B)\n#define BITS_PS_TIMER_C_TSF_SEL_8822B                                          \\\n\t(BIT_MASK_PS_TIMER_C_TSF_SEL_8822B                                     \\\n\t << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B)\n#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822B(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_C_TSF_SEL_8822B))\n#define BIT_GET_PS_TIMER_C_TSF_SEL_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B) &                         \\\n\t BIT_MASK_PS_TIMER_C_TSF_SEL_8822B)\n#define BIT_SET_PS_TIMER_C_TSF_SEL_8822B(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822B(x) |                               \\\n\t BIT_PS_TIMER_C_TSF_SEL_8822B(v))\n\n#define BIT_PS_TIMER_B_EN_8822B BIT(15)\n\n#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B 8\n#define BIT_MASK_PS_TIMER_B_TSF_SEL_8822B 0x7\n#define BIT_PS_TIMER_B_TSF_SEL_8822B(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822B)                             \\\n\t << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B)\n#define BITS_PS_TIMER_B_TSF_SEL_8822B                                          \\\n\t(BIT_MASK_PS_TIMER_B_TSF_SEL_8822B                                     \\\n\t << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B)\n#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822B(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_B_TSF_SEL_8822B))\n#define BIT_GET_PS_TIMER_B_TSF_SEL_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B) &                         \\\n\t BIT_MASK_PS_TIMER_B_TSF_SEL_8822B)\n#define BIT_SET_PS_TIMER_B_TSF_SEL_8822B(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822B(x) |                               \\\n\t BIT_PS_TIMER_B_TSF_SEL_8822B(v))\n\n#define BIT_PS_TIMER_A_EN_8822B BIT(7)\n\n#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B 0\n#define BIT_MASK_PS_TIMER_A_TSF_SEL_8822B 0x7\n#define BIT_PS_TIMER_A_TSF_SEL_8822B(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822B)                             \\\n\t << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B)\n#define BITS_PS_TIMER_A_TSF_SEL_8822B                                          \\\n\t(BIT_MASK_PS_TIMER_A_TSF_SEL_8822B                                     \\\n\t << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B)\n#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822B(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_A_TSF_SEL_8822B))\n#define BIT_GET_PS_TIMER_A_TSF_SEL_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B) &                         \\\n\t BIT_MASK_PS_TIMER_A_TSF_SEL_8822B)\n#define BIT_SET_PS_TIMER_A_TSF_SEL_8822B(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822B(x) |                               \\\n\t BIT_PS_TIMER_A_TSF_SEL_8822B(v))\n\n/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8822B */\n\n#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B 0\n#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B 0xff\n#define BIT_CPUMGQ_TX_TIMER_EARLY_8822B(x)                                     \\\n\t(((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B)                          \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B)\n#define BITS_CPUMGQ_TX_TIMER_EARLY_8822B                                       \\\n\t(BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B                                  \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B)\n#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822B(x)                               \\\n\t((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8822B))\n#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8822B(x)                                 \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B) &                      \\\n\t BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B)\n#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8822B(x, v)                              \\\n\t(BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822B(x) |                            \\\n\t BIT_CPUMGQ_TX_TIMER_EARLY_8822B(v))\n\n/* 2 REG_PS_TIMER_A_EARLY_8822B */\n\n#define BIT_SHIFT_PS_TIMER_A_EARLY_8822B 0\n#define BIT_MASK_PS_TIMER_A_EARLY_8822B 0xff\n#define BIT_PS_TIMER_A_EARLY_8822B(x)                                          \\\n\t(((x) & BIT_MASK_PS_TIMER_A_EARLY_8822B)                               \\\n\t << BIT_SHIFT_PS_TIMER_A_EARLY_8822B)\n#define BITS_PS_TIMER_A_EARLY_8822B                                            \\\n\t(BIT_MASK_PS_TIMER_A_EARLY_8822B << BIT_SHIFT_PS_TIMER_A_EARLY_8822B)\n#define BIT_CLEAR_PS_TIMER_A_EARLY_8822B(x)                                    \\\n\t((x) & (~BITS_PS_TIMER_A_EARLY_8822B))\n#define BIT_GET_PS_TIMER_A_EARLY_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8822B) &                           \\\n\t BIT_MASK_PS_TIMER_A_EARLY_8822B)\n#define BIT_SET_PS_TIMER_A_EARLY_8822B(x, v)                                   \\\n\t(BIT_CLEAR_PS_TIMER_A_EARLY_8822B(x) | BIT_PS_TIMER_A_EARLY_8822B(v))\n\n/* 2 REG_PS_TIMER_B_EARLY_8822B */\n\n#define BIT_SHIFT_PS_TIMER_B_EARLY_8822B 0\n#define BIT_MASK_PS_TIMER_B_EARLY_8822B 0xff\n#define BIT_PS_TIMER_B_EARLY_8822B(x)                                          \\\n\t(((x) & BIT_MASK_PS_TIMER_B_EARLY_8822B)                               \\\n\t << BIT_SHIFT_PS_TIMER_B_EARLY_8822B)\n#define BITS_PS_TIMER_B_EARLY_8822B                                            \\\n\t(BIT_MASK_PS_TIMER_B_EARLY_8822B << BIT_SHIFT_PS_TIMER_B_EARLY_8822B)\n#define BIT_CLEAR_PS_TIMER_B_EARLY_8822B(x)                                    \\\n\t((x) & (~BITS_PS_TIMER_B_EARLY_8822B))\n#define BIT_GET_PS_TIMER_B_EARLY_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8822B) &                           \\\n\t BIT_MASK_PS_TIMER_B_EARLY_8822B)\n#define BIT_SET_PS_TIMER_B_EARLY_8822B(x, v)                                   \\\n\t(BIT_CLEAR_PS_TIMER_B_EARLY_8822B(x) | BIT_PS_TIMER_B_EARLY_8822B(v))\n\n/* 2 REG_PS_TIMER_C_EARLY_8822B */\n\n#define BIT_SHIFT_PS_TIMER_C_EARLY_8822B 0\n#define BIT_MASK_PS_TIMER_C_EARLY_8822B 0xff\n#define BIT_PS_TIMER_C_EARLY_8822B(x)                                          \\\n\t(((x) & BIT_MASK_PS_TIMER_C_EARLY_8822B)                               \\\n\t << BIT_SHIFT_PS_TIMER_C_EARLY_8822B)\n#define BITS_PS_TIMER_C_EARLY_8822B                                            \\\n\t(BIT_MASK_PS_TIMER_C_EARLY_8822B << BIT_SHIFT_PS_TIMER_C_EARLY_8822B)\n#define BIT_CLEAR_PS_TIMER_C_EARLY_8822B(x)                                    \\\n\t((x) & (~BITS_PS_TIMER_C_EARLY_8822B))\n#define BIT_GET_PS_TIMER_C_EARLY_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8822B) &                           \\\n\t BIT_MASK_PS_TIMER_C_EARLY_8822B)\n#define BIT_SET_PS_TIMER_C_EARLY_8822B(x, v)                                   \\\n\t(BIT_CLEAR_PS_TIMER_C_EARLY_8822B(x) | BIT_PS_TIMER_C_EARLY_8822B(v))\n\n/* 2 REG_CPUMGQ_PARAMETER_8822B */\n\n/* 2 REG_NOT_VALID_8822B */\n#define BIT_MAC_STOP_CPUMGQ_8822B BIT(16)\n\n#define BIT_SHIFT_CW_8822B 8\n#define BIT_MASK_CW_8822B 0xff\n#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)\n#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B)\n#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B))\n#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)\n#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v))\n\n#define BIT_SHIFT_AIFS_8822B 0\n#define BIT_MASK_AIFS_8822B 0xff\n#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)\n#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B)\n#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B))\n#define BIT_GET_AIFS_8822B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)\n#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_BWOPMODE_8822B (BW OPERATION MODE REGISTER) */\n\n/* 2 REG_WMAC_FWPKT_CR_8822B */\n#define BIT_FWEN_8822B BIT(7)\n#define BIT_PHYSTS_PKT_CTRL_8822B BIT(6)\n#define BIT_APPHDR_MIDSRCH_FAIL_8822B BIT(4)\n#define BIT_FWPARSING_EN_8822B BIT(3)\n\n#define BIT_SHIFT_APPEND_MHDR_LEN_8822B 0\n#define BIT_MASK_APPEND_MHDR_LEN_8822B 0x7\n#define BIT_APPEND_MHDR_LEN_8822B(x)                                           \\\n\t(((x) & BIT_MASK_APPEND_MHDR_LEN_8822B)                                \\\n\t << BIT_SHIFT_APPEND_MHDR_LEN_8822B)\n#define BITS_APPEND_MHDR_LEN_8822B                                             \\\n\t(BIT_MASK_APPEND_MHDR_LEN_8822B << BIT_SHIFT_APPEND_MHDR_LEN_8822B)\n#define BIT_CLEAR_APPEND_MHDR_LEN_8822B(x) ((x) & (~BITS_APPEND_MHDR_LEN_8822B))\n#define BIT_GET_APPEND_MHDR_LEN_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8822B) &                            \\\n\t BIT_MASK_APPEND_MHDR_LEN_8822B)\n#define BIT_SET_APPEND_MHDR_LEN_8822B(x, v)                                    \\\n\t(BIT_CLEAR_APPEND_MHDR_LEN_8822B(x) | BIT_APPEND_MHDR_LEN_8822B(v))\n\n/* 2 REG_WMAC_CR_8822B (WMAC CR AND APSD CONTROL REGISTER) */\n#define BIT_IC_MACPHY_M_8822B BIT(0)\n\n/* 2 REG_TCR_8822B (TRANSMISSION CONFIGURATION REGISTER) */\n#define BIT_WMAC_EN_RTS_ADDR_8822B BIT(31)\n#define BIT_WMAC_DISABLE_CCK_8822B BIT(30)\n#define BIT_WMAC_RAW_LEN_8822B BIT(29)\n#define BIT_WMAC_NOTX_IN_RXNDP_8822B BIT(28)\n#define BIT_WMAC_EN_EOF_8822B BIT(27)\n#define BIT_WMAC_BF_SEL_8822B BIT(26)\n#define BIT_WMAC_ANTMODE_SEL_8822B BIT(25)\n#define BIT_WMAC_TCRPWRMGT_HWCTL_8822B BIT(24)\n#define BIT_WMAC_SMOOTH_VAL_8822B BIT(23)\n#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8822B BIT(20)\n#define BIT_WMAC_TCR_EN_20MST_8822B BIT(19)\n#define BIT_WMAC_DIS_SIGTA_8822B BIT(18)\n#define BIT_WMAC_DIS_A2B0_8822B BIT(17)\n#define BIT_WMAC_MSK_SIGBCRC_8822B BIT(16)\n#define BIT_WMAC_TCR_ERRSTEN_3_8822B BIT(15)\n#define BIT_WMAC_TCR_ERRSTEN_2_8822B BIT(14)\n#define BIT_WMAC_TCR_ERRSTEN_1_8822B BIT(13)\n#define BIT_WMAC_TCR_ERRSTEN_0_8822B BIT(12)\n#define BIT_WMAC_TCR_TXSK_PERPKT_8822B BIT(11)\n#define BIT_ICV_8822B BIT(10)\n#define BIT_CFEND_FORMAT_8822B BIT(9)\n#define BIT_CRC_8822B BIT(8)\n#define BIT_PWRBIT_OW_EN_8822B BIT(7)\n#define BIT_PWR_ST_8822B BIT(6)\n#define BIT_WMAC_TCR_UPD_TIMIE_8822B BIT(5)\n#define BIT_WMAC_TCR_UPD_HGQMD_8822B BIT(4)\n#define BIT_VHTSIGA1_TXPS_8822B BIT(3)\n#define BIT_PAD_SEL_8822B BIT(2)\n#define BIT_DIS_GCLK_8822B BIT(1)\n\n/* 2 REG_RCR_8822B (RECEIVE CONFIGURATION REGISTER) */\n#define BIT_APP_FCS_8822B BIT(31)\n#define BIT_APP_MIC_8822B BIT(30)\n#define BIT_APP_ICV_8822B BIT(29)\n#define BIT_APP_PHYSTS_8822B BIT(28)\n#define BIT_APP_BASSN_8822B BIT(27)\n#define BIT_VHT_DACK_8822B BIT(26)\n#define BIT_TCPOFLD_EN_8822B BIT(25)\n#define BIT_ENMBID_8822B BIT(24)\n#define BIT_LSIGEN_8822B BIT(23)\n#define BIT_MFBEN_8822B BIT(22)\n#define BIT_DISCHKPPDLLEN_8822B BIT(21)\n#define BIT_PKTCTL_DLEN_8822B BIT(20)\n#define BIT_TIM_PARSER_EN_8822B BIT(18)\n#define BIT_BC_MD_EN_8822B BIT(17)\n#define BIT_UC_MD_EN_8822B BIT(16)\n#define BIT_RXSK_PERPKT_8822B BIT(15)\n#define BIT_HTC_LOC_CTRL_8822B BIT(14)\n#define BIT_RPFM_CAM_ENABLE_8822B BIT(12)\n#define BIT_TA_BCN_8822B BIT(11)\n#define BIT_DISDECMYPKT_8822B BIT(10)\n#define BIT_AICV_8822B BIT(9)\n#define BIT_ACRC32_8822B BIT(8)\n#define BIT_CBSSID_BCN_8822B BIT(7)\n#define BIT_CBSSID_DATA_8822B BIT(6)\n#define BIT_APWRMGT_8822B BIT(5)\n#define BIT_ADD3_8822B BIT(4)\n#define BIT_AB_8822B BIT(3)\n#define BIT_AM_8822B BIT(2)\n#define BIT_APM_8822B BIT(1)\n#define BIT_AAP_8822B BIT(0)\n\n/* 2 REG_RX_DRVINFO_SZ_8822B (RX DRIVER INFO SIZE REGISTER) */\n#define BIT_PHYSTS_PER_PKT_MODE_8822B BIT(7)\n\n#define BIT_SHIFT_DRVINFO_SZ_V1_8822B 0\n#define BIT_MASK_DRVINFO_SZ_V1_8822B 0xf\n#define BIT_DRVINFO_SZ_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_DRVINFO_SZ_V1_8822B) << BIT_SHIFT_DRVINFO_SZ_V1_8822B)\n#define BITS_DRVINFO_SZ_V1_8822B                                               \\\n\t(BIT_MASK_DRVINFO_SZ_V1_8822B << BIT_SHIFT_DRVINFO_SZ_V1_8822B)\n#define BIT_CLEAR_DRVINFO_SZ_V1_8822B(x) ((x) & (~BITS_DRVINFO_SZ_V1_8822B))\n#define BIT_GET_DRVINFO_SZ_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8822B) & BIT_MASK_DRVINFO_SZ_V1_8822B)\n#define BIT_SET_DRVINFO_SZ_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_DRVINFO_SZ_V1_8822B(x) | BIT_DRVINFO_SZ_V1_8822B(v))\n\n/* 2 REG_RX_DLK_TIME_8822B (RX DEADLOCK TIME REGISTER) */\n\n#define BIT_SHIFT_RX_DLK_TIME_8822B 0\n#define BIT_MASK_RX_DLK_TIME_8822B 0xff\n#define BIT_RX_DLK_TIME_8822B(x)                                               \\\n\t(((x) & BIT_MASK_RX_DLK_TIME_8822B) << BIT_SHIFT_RX_DLK_TIME_8822B)\n#define BITS_RX_DLK_TIME_8822B                                                 \\\n\t(BIT_MASK_RX_DLK_TIME_8822B << BIT_SHIFT_RX_DLK_TIME_8822B)\n#define BIT_CLEAR_RX_DLK_TIME_8822B(x) ((x) & (~BITS_RX_DLK_TIME_8822B))\n#define BIT_GET_RX_DLK_TIME_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_RX_DLK_TIME_8822B) & BIT_MASK_RX_DLK_TIME_8822B)\n#define BIT_SET_RX_DLK_TIME_8822B(x, v)                                        \\\n\t(BIT_CLEAR_RX_DLK_TIME_8822B(x) | BIT_RX_DLK_TIME_8822B(v))\n\n/* 2 REG_RX_PKT_LIMIT_8822B (RX PACKET LENGTH LIMIT REGISTER) */\n\n#define BIT_SHIFT_RXPKTLMT_8822B 0\n#define BIT_MASK_RXPKTLMT_8822B 0x3f\n#define BIT_RXPKTLMT_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_RXPKTLMT_8822B) << BIT_SHIFT_RXPKTLMT_8822B)\n#define BITS_RXPKTLMT_8822B                                                    \\\n\t(BIT_MASK_RXPKTLMT_8822B << BIT_SHIFT_RXPKTLMT_8822B)\n#define BIT_CLEAR_RXPKTLMT_8822B(x) ((x) & (~BITS_RXPKTLMT_8822B))\n#define BIT_GET_RXPKTLMT_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_RXPKTLMT_8822B) & BIT_MASK_RXPKTLMT_8822B)\n#define BIT_SET_RXPKTLMT_8822B(x, v)                                           \\\n\t(BIT_CLEAR_RXPKTLMT_8822B(x) | BIT_RXPKTLMT_8822B(v))\n\n/* 2 REG_MACID_8822B (MAC ID REGISTER) */\n\n#define BIT_SHIFT_MACID_8822B 0\n#define BIT_MASK_MACID_8822B 0xffffffffffffL\n#define BIT_MACID_8822B(x)                                                     \\\n\t(((x) & BIT_MASK_MACID_8822B) << BIT_SHIFT_MACID_8822B)\n#define BITS_MACID_8822B (BIT_MASK_MACID_8822B << BIT_SHIFT_MACID_8822B)\n#define BIT_CLEAR_MACID_8822B(x) ((x) & (~BITS_MACID_8822B))\n#define BIT_GET_MACID_8822B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_MACID_8822B) & BIT_MASK_MACID_8822B)\n#define BIT_SET_MACID_8822B(x, v)                                              \\\n\t(BIT_CLEAR_MACID_8822B(x) | BIT_MACID_8822B(v))\n\n/* 2 REG_BSSID_8822B (BSSID REGISTER) */\n\n#define BIT_SHIFT_BSSID_8822B 0\n#define BIT_MASK_BSSID_8822B 0xffffffffffffL\n#define BIT_BSSID_8822B(x)                                                     \\\n\t(((x) & BIT_MASK_BSSID_8822B) << BIT_SHIFT_BSSID_8822B)\n#define BITS_BSSID_8822B (BIT_MASK_BSSID_8822B << BIT_SHIFT_BSSID_8822B)\n#define BIT_CLEAR_BSSID_8822B(x) ((x) & (~BITS_BSSID_8822B))\n#define BIT_GET_BSSID_8822B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_BSSID_8822B) & BIT_MASK_BSSID_8822B)\n#define BIT_SET_BSSID_8822B(x, v)                                              \\\n\t(BIT_CLEAR_BSSID_8822B(x) | BIT_BSSID_8822B(v))\n\n/* 2 REG_MAR_8822B (MULTICAST ADDRESS REGISTER) */\n\n#define BIT_SHIFT_MAR_8822B 0\n#define BIT_MASK_MAR_8822B 0xffffffffffffffffL\n#define BIT_MAR_8822B(x) (((x) & BIT_MASK_MAR_8822B) << BIT_SHIFT_MAR_8822B)\n#define BITS_MAR_8822B (BIT_MASK_MAR_8822B << BIT_SHIFT_MAR_8822B)\n#define BIT_CLEAR_MAR_8822B(x) ((x) & (~BITS_MAR_8822B))\n#define BIT_GET_MAR_8822B(x) (((x) >> BIT_SHIFT_MAR_8822B) & BIT_MASK_MAR_8822B)\n#define BIT_SET_MAR_8822B(x, v) (BIT_CLEAR_MAR_8822B(x) | BIT_MAR_8822B(v))\n\n/* 2 REG_MBIDCAMCFG_1_8822B (MBSSID CAM CONFIGURATION REGISTER) */\n\n#define BIT_SHIFT_MBIDCAM_RWDATA_L_8822B 0\n#define BIT_MASK_MBIDCAM_RWDATA_L_8822B 0xffffffffL\n#define BIT_MBIDCAM_RWDATA_L_8822B(x)                                          \\\n\t(((x) & BIT_MASK_MBIDCAM_RWDATA_L_8822B)                               \\\n\t << BIT_SHIFT_MBIDCAM_RWDATA_L_8822B)\n#define BITS_MBIDCAM_RWDATA_L_8822B                                            \\\n\t(BIT_MASK_MBIDCAM_RWDATA_L_8822B << BIT_SHIFT_MBIDCAM_RWDATA_L_8822B)\n#define BIT_CLEAR_MBIDCAM_RWDATA_L_8822B(x)                                    \\\n\t((x) & (~BITS_MBIDCAM_RWDATA_L_8822B))\n#define BIT_GET_MBIDCAM_RWDATA_L_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8822B) &                           \\\n\t BIT_MASK_MBIDCAM_RWDATA_L_8822B)\n#define BIT_SET_MBIDCAM_RWDATA_L_8822B(x, v)                                   \\\n\t(BIT_CLEAR_MBIDCAM_RWDATA_L_8822B(x) | BIT_MBIDCAM_RWDATA_L_8822B(v))\n\n/* 2 REG_MBIDCAMCFG_2_8822B (MBSSID CAM CONFIGURATION REGISTER) */\n#define BIT_MBIDCAM_POLL_8822B BIT(31)\n#define BIT_MBIDCAM_WT_EN_8822B BIT(30)\n\n#define BIT_SHIFT_MBIDCAM_ADDR_8822B 24\n#define BIT_MASK_MBIDCAM_ADDR_8822B 0x1f\n#define BIT_MBIDCAM_ADDR_8822B(x)                                              \\\n\t(((x) & BIT_MASK_MBIDCAM_ADDR_8822B) << BIT_SHIFT_MBIDCAM_ADDR_8822B)\n#define BITS_MBIDCAM_ADDR_8822B                                                \\\n\t(BIT_MASK_MBIDCAM_ADDR_8822B << BIT_SHIFT_MBIDCAM_ADDR_8822B)\n#define BIT_CLEAR_MBIDCAM_ADDR_8822B(x) ((x) & (~BITS_MBIDCAM_ADDR_8822B))\n#define BIT_GET_MBIDCAM_ADDR_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_MBIDCAM_ADDR_8822B) & BIT_MASK_MBIDCAM_ADDR_8822B)\n#define BIT_SET_MBIDCAM_ADDR_8822B(x, v)                                       \\\n\t(BIT_CLEAR_MBIDCAM_ADDR_8822B(x) | BIT_MBIDCAM_ADDR_8822B(v))\n\n#define BIT_MBIDCAM_VALID_8822B BIT(23)\n#define BIT_LSIC_TXOP_EN_8822B BIT(17)\n#define BIT_CTS_EN_8822B BIT(16)\n\n#define BIT_SHIFT_MBIDCAM_RWDATA_H_8822B 0\n#define BIT_MASK_MBIDCAM_RWDATA_H_8822B 0xffff\n#define BIT_MBIDCAM_RWDATA_H_8822B(x)                                          \\\n\t(((x) & BIT_MASK_MBIDCAM_RWDATA_H_8822B)                               \\\n\t << BIT_SHIFT_MBIDCAM_RWDATA_H_8822B)\n#define BITS_MBIDCAM_RWDATA_H_8822B                                            \\\n\t(BIT_MASK_MBIDCAM_RWDATA_H_8822B << BIT_SHIFT_MBIDCAM_RWDATA_H_8822B)\n#define BIT_CLEAR_MBIDCAM_RWDATA_H_8822B(x)                                    \\\n\t((x) & (~BITS_MBIDCAM_RWDATA_H_8822B))\n#define BIT_GET_MBIDCAM_RWDATA_H_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8822B) &                           \\\n\t BIT_MASK_MBIDCAM_RWDATA_H_8822B)\n#define BIT_SET_MBIDCAM_RWDATA_H_8822B(x, v)                                   \\\n\t(BIT_CLEAR_MBIDCAM_RWDATA_H_8822B(x) | BIT_MBIDCAM_RWDATA_H_8822B(v))\n\n/* 2 REG_ZLD_NUM_8822B */\n\n#define BIT_SHIFT_ZLD_NUM_8822B 0\n#define BIT_MASK_ZLD_NUM_8822B 0xff\n#define BIT_ZLD_NUM_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_ZLD_NUM_8822B) << BIT_SHIFT_ZLD_NUM_8822B)\n#define BITS_ZLD_NUM_8822B (BIT_MASK_ZLD_NUM_8822B << BIT_SHIFT_ZLD_NUM_8822B)\n#define BIT_CLEAR_ZLD_NUM_8822B(x) ((x) & (~BITS_ZLD_NUM_8822B))\n#define BIT_GET_ZLD_NUM_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_ZLD_NUM_8822B) & BIT_MASK_ZLD_NUM_8822B)\n#define BIT_SET_ZLD_NUM_8822B(x, v)                                            \\\n\t(BIT_CLEAR_ZLD_NUM_8822B(x) | BIT_ZLD_NUM_8822B(v))\n\n/* 2 REG_UDF_THSD_8822B */\n\n#define BIT_SHIFT_UDF_THSD_8822B 0\n#define BIT_MASK_UDF_THSD_8822B 0xff\n#define BIT_UDF_THSD_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_UDF_THSD_8822B) << BIT_SHIFT_UDF_THSD_8822B)\n#define BITS_UDF_THSD_8822B                                                    \\\n\t(BIT_MASK_UDF_THSD_8822B << BIT_SHIFT_UDF_THSD_8822B)\n#define BIT_CLEAR_UDF_THSD_8822B(x) ((x) & (~BITS_UDF_THSD_8822B))\n#define BIT_GET_UDF_THSD_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_UDF_THSD_8822B) & BIT_MASK_UDF_THSD_8822B)\n#define BIT_SET_UDF_THSD_8822B(x, v)                                           \\\n\t(BIT_CLEAR_UDF_THSD_8822B(x) | BIT_UDF_THSD_8822B(v))\n\n/* 2 REG_WMAC_TCR_TSFT_OFS_8822B */\n\n#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B 0\n#define BIT_MASK_WMAC_TCR_TSFT_OFS_8822B 0xffff\n#define BIT_WMAC_TCR_TSFT_OFS_8822B(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822B)                              \\\n\t << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B)\n#define BITS_WMAC_TCR_TSFT_OFS_8822B                                           \\\n\t(BIT_MASK_WMAC_TCR_TSFT_OFS_8822B << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B)\n#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822B(x)                                   \\\n\t((x) & (~BITS_WMAC_TCR_TSFT_OFS_8822B))\n#define BIT_GET_WMAC_TCR_TSFT_OFS_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B) &                          \\\n\t BIT_MASK_WMAC_TCR_TSFT_OFS_8822B)\n#define BIT_SET_WMAC_TCR_TSFT_OFS_8822B(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822B(x) | BIT_WMAC_TCR_TSFT_OFS_8822B(v))\n\n/* 2 REG_MCU_TEST_2_V1_8822B */\n\n#define BIT_SHIFT_MCU_RSVD_2_V1_8822B 0\n#define BIT_MASK_MCU_RSVD_2_V1_8822B 0xffff\n#define BIT_MCU_RSVD_2_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_MCU_RSVD_2_V1_8822B) << BIT_SHIFT_MCU_RSVD_2_V1_8822B)\n#define BITS_MCU_RSVD_2_V1_8822B                                               \\\n\t(BIT_MASK_MCU_RSVD_2_V1_8822B << BIT_SHIFT_MCU_RSVD_2_V1_8822B)\n#define BIT_CLEAR_MCU_RSVD_2_V1_8822B(x) ((x) & (~BITS_MCU_RSVD_2_V1_8822B))\n#define BIT_GET_MCU_RSVD_2_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8822B) & BIT_MASK_MCU_RSVD_2_V1_8822B)\n#define BIT_SET_MCU_RSVD_2_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_MCU_RSVD_2_V1_8822B(x) | BIT_MCU_RSVD_2_V1_8822B(v))\n\n/* 2 REG_WMAC_TXTIMEOUT_8822B */\n\n#define BIT_SHIFT_WMAC_TXTIMEOUT_8822B 0\n#define BIT_MASK_WMAC_TXTIMEOUT_8822B 0xff\n#define BIT_WMAC_TXTIMEOUT_8822B(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_TXTIMEOUT_8822B)                                 \\\n\t << BIT_SHIFT_WMAC_TXTIMEOUT_8822B)\n#define BITS_WMAC_TXTIMEOUT_8822B                                              \\\n\t(BIT_MASK_WMAC_TXTIMEOUT_8822B << BIT_SHIFT_WMAC_TXTIMEOUT_8822B)\n#define BIT_CLEAR_WMAC_TXTIMEOUT_8822B(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8822B))\n#define BIT_GET_WMAC_TXTIMEOUT_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8822B) &                             \\\n\t BIT_MASK_WMAC_TXTIMEOUT_8822B)\n#define BIT_SET_WMAC_TXTIMEOUT_8822B(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_TXTIMEOUT_8822B(x) | BIT_WMAC_TXTIMEOUT_8822B(v))\n\n/* 2 REG_STMP_THSD_8822B */\n\n#define BIT_SHIFT_STMP_THSD_8822B 0\n#define BIT_MASK_STMP_THSD_8822B 0xff\n#define BIT_STMP_THSD_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_STMP_THSD_8822B) << BIT_SHIFT_STMP_THSD_8822B)\n#define BITS_STMP_THSD_8822B                                                   \\\n\t(BIT_MASK_STMP_THSD_8822B << BIT_SHIFT_STMP_THSD_8822B)\n#define BIT_CLEAR_STMP_THSD_8822B(x) ((x) & (~BITS_STMP_THSD_8822B))\n#define BIT_GET_STMP_THSD_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_STMP_THSD_8822B) & BIT_MASK_STMP_THSD_8822B)\n#define BIT_SET_STMP_THSD_8822B(x, v)                                          \\\n\t(BIT_CLEAR_STMP_THSD_8822B(x) | BIT_STMP_THSD_8822B(v))\n\n/* 2 REG_MAC_SPEC_SIFS_8822B (SPECIFICATION SIFS REGISTER) */\n\n#define BIT_SHIFT_SPEC_SIFS_OFDM_8822B 8\n#define BIT_MASK_SPEC_SIFS_OFDM_8822B 0xff\n#define BIT_SPEC_SIFS_OFDM_8822B(x)                                            \\\n\t(((x) & BIT_MASK_SPEC_SIFS_OFDM_8822B)                                 \\\n\t << BIT_SHIFT_SPEC_SIFS_OFDM_8822B)\n#define BITS_SPEC_SIFS_OFDM_8822B                                              \\\n\t(BIT_MASK_SPEC_SIFS_OFDM_8822B << BIT_SHIFT_SPEC_SIFS_OFDM_8822B)\n#define BIT_CLEAR_SPEC_SIFS_OFDM_8822B(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8822B))\n#define BIT_GET_SPEC_SIFS_OFDM_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8822B) &                             \\\n\t BIT_MASK_SPEC_SIFS_OFDM_8822B)\n#define BIT_SET_SPEC_SIFS_OFDM_8822B(x, v)                                     \\\n\t(BIT_CLEAR_SPEC_SIFS_OFDM_8822B(x) | BIT_SPEC_SIFS_OFDM_8822B(v))\n\n#define BIT_SHIFT_SPEC_SIFS_CCK_8822B 0\n#define BIT_MASK_SPEC_SIFS_CCK_8822B 0xff\n#define BIT_SPEC_SIFS_CCK_8822B(x)                                             \\\n\t(((x) & BIT_MASK_SPEC_SIFS_CCK_8822B) << BIT_SHIFT_SPEC_SIFS_CCK_8822B)\n#define BITS_SPEC_SIFS_CCK_8822B                                               \\\n\t(BIT_MASK_SPEC_SIFS_CCK_8822B << BIT_SHIFT_SPEC_SIFS_CCK_8822B)\n#define BIT_CLEAR_SPEC_SIFS_CCK_8822B(x) ((x) & (~BITS_SPEC_SIFS_CCK_8822B))\n#define BIT_GET_SPEC_SIFS_CCK_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8822B) & BIT_MASK_SPEC_SIFS_CCK_8822B)\n#define BIT_SET_SPEC_SIFS_CCK_8822B(x, v)                                      \\\n\t(BIT_CLEAR_SPEC_SIFS_CCK_8822B(x) | BIT_SPEC_SIFS_CCK_8822B(v))\n\n/* 2 REG_USTIME_EDCA_8822B (US TIME TUNING FOR EDCA REGISTER) */\n\n#define BIT_SHIFT_USTIME_EDCA_V1_8822B 0\n#define BIT_MASK_USTIME_EDCA_V1_8822B 0x1ff\n#define BIT_USTIME_EDCA_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_USTIME_EDCA_V1_8822B)                                 \\\n\t << BIT_SHIFT_USTIME_EDCA_V1_8822B)\n#define BITS_USTIME_EDCA_V1_8822B                                              \\\n\t(BIT_MASK_USTIME_EDCA_V1_8822B << BIT_SHIFT_USTIME_EDCA_V1_8822B)\n#define BIT_CLEAR_USTIME_EDCA_V1_8822B(x) ((x) & (~BITS_USTIME_EDCA_V1_8822B))\n#define BIT_GET_USTIME_EDCA_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_USTIME_EDCA_V1_8822B) &                             \\\n\t BIT_MASK_USTIME_EDCA_V1_8822B)\n#define BIT_SET_USTIME_EDCA_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_USTIME_EDCA_V1_8822B(x) | BIT_USTIME_EDCA_V1_8822B(v))\n\n/* 2 REG_RESP_SIFS_OFDM_8822B (RESPONSE SIFS FOR OFDM REGISTER) */\n\n#define BIT_SHIFT_SIFS_R2T_OFDM_8822B 8\n#define BIT_MASK_SIFS_R2T_OFDM_8822B 0xff\n#define BIT_SIFS_R2T_OFDM_8822B(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_R2T_OFDM_8822B) << BIT_SHIFT_SIFS_R2T_OFDM_8822B)\n#define BITS_SIFS_R2T_OFDM_8822B                                               \\\n\t(BIT_MASK_SIFS_R2T_OFDM_8822B << BIT_SHIFT_SIFS_R2T_OFDM_8822B)\n#define BIT_CLEAR_SIFS_R2T_OFDM_8822B(x) ((x) & (~BITS_SIFS_R2T_OFDM_8822B))\n#define BIT_GET_SIFS_R2T_OFDM_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8822B) & BIT_MASK_SIFS_R2T_OFDM_8822B)\n#define BIT_SET_SIFS_R2T_OFDM_8822B(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_R2T_OFDM_8822B(x) | BIT_SIFS_R2T_OFDM_8822B(v))\n\n#define BIT_SHIFT_SIFS_T2T_OFDM_8822B 0\n#define BIT_MASK_SIFS_T2T_OFDM_8822B 0xff\n#define BIT_SIFS_T2T_OFDM_8822B(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_T2T_OFDM_8822B) << BIT_SHIFT_SIFS_T2T_OFDM_8822B)\n#define BITS_SIFS_T2T_OFDM_8822B                                               \\\n\t(BIT_MASK_SIFS_T2T_OFDM_8822B << BIT_SHIFT_SIFS_T2T_OFDM_8822B)\n#define BIT_CLEAR_SIFS_T2T_OFDM_8822B(x) ((x) & (~BITS_SIFS_T2T_OFDM_8822B))\n#define BIT_GET_SIFS_T2T_OFDM_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8822B) & BIT_MASK_SIFS_T2T_OFDM_8822B)\n#define BIT_SET_SIFS_T2T_OFDM_8822B(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_T2T_OFDM_8822B(x) | BIT_SIFS_T2T_OFDM_8822B(v))\n\n/* 2 REG_RESP_SIFS_CCK_8822B (RESPONSE SIFS FOR CCK REGISTER) */\n\n#define BIT_SHIFT_SIFS_R2T_CCK_8822B 8\n#define BIT_MASK_SIFS_R2T_CCK_8822B 0xff\n#define BIT_SIFS_R2T_CCK_8822B(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_R2T_CCK_8822B) << BIT_SHIFT_SIFS_R2T_CCK_8822B)\n#define BITS_SIFS_R2T_CCK_8822B                                                \\\n\t(BIT_MASK_SIFS_R2T_CCK_8822B << BIT_SHIFT_SIFS_R2T_CCK_8822B)\n#define BIT_CLEAR_SIFS_R2T_CCK_8822B(x) ((x) & (~BITS_SIFS_R2T_CCK_8822B))\n#define BIT_GET_SIFS_R2T_CCK_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_R2T_CCK_8822B) & BIT_MASK_SIFS_R2T_CCK_8822B)\n#define BIT_SET_SIFS_R2T_CCK_8822B(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_R2T_CCK_8822B(x) | BIT_SIFS_R2T_CCK_8822B(v))\n\n#define BIT_SHIFT_SIFS_T2T_CCK_8822B 0\n#define BIT_MASK_SIFS_T2T_CCK_8822B 0xff\n#define BIT_SIFS_T2T_CCK_8822B(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_T2T_CCK_8822B) << BIT_SHIFT_SIFS_T2T_CCK_8822B)\n#define BITS_SIFS_T2T_CCK_8822B                                                \\\n\t(BIT_MASK_SIFS_T2T_CCK_8822B << BIT_SHIFT_SIFS_T2T_CCK_8822B)\n#define BIT_CLEAR_SIFS_T2T_CCK_8822B(x) ((x) & (~BITS_SIFS_T2T_CCK_8822B))\n#define BIT_GET_SIFS_T2T_CCK_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_T2T_CCK_8822B) & BIT_MASK_SIFS_T2T_CCK_8822B)\n#define BIT_SET_SIFS_T2T_CCK_8822B(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_T2T_CCK_8822B(x) | BIT_SIFS_T2T_CCK_8822B(v))\n\n/* 2 REG_EIFS_8822B (EIFS REGISTER) */\n\n#define BIT_SHIFT_EIFS_8822B 0\n#define BIT_MASK_EIFS_8822B 0xffff\n#define BIT_EIFS_8822B(x) (((x) & BIT_MASK_EIFS_8822B) << BIT_SHIFT_EIFS_8822B)\n#define BITS_EIFS_8822B (BIT_MASK_EIFS_8822B << BIT_SHIFT_EIFS_8822B)\n#define BIT_CLEAR_EIFS_8822B(x) ((x) & (~BITS_EIFS_8822B))\n#define BIT_GET_EIFS_8822B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_EIFS_8822B) & BIT_MASK_EIFS_8822B)\n#define BIT_SET_EIFS_8822B(x, v) (BIT_CLEAR_EIFS_8822B(x) | BIT_EIFS_8822B(v))\n\n/* 2 REG_CTS2TO_8822B (CTS2 TIMEOUT REGISTER) */\n\n#define BIT_SHIFT_CTS2TO_8822B 0\n#define BIT_MASK_CTS2TO_8822B 0xff\n#define BIT_CTS2TO_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_CTS2TO_8822B) << BIT_SHIFT_CTS2TO_8822B)\n#define BITS_CTS2TO_8822B (BIT_MASK_CTS2TO_8822B << BIT_SHIFT_CTS2TO_8822B)\n#define BIT_CLEAR_CTS2TO_8822B(x) ((x) & (~BITS_CTS2TO_8822B))\n#define BIT_GET_CTS2TO_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_CTS2TO_8822B) & BIT_MASK_CTS2TO_8822B)\n#define BIT_SET_CTS2TO_8822B(x, v)                                             \\\n\t(BIT_CLEAR_CTS2TO_8822B(x) | BIT_CTS2TO_8822B(v))\n\n/* 2 REG_ACKTO_8822B (ACK TIMEOUT REGISTER) */\n\n#define BIT_SHIFT_ACKTO_8822B 0\n#define BIT_MASK_ACKTO_8822B 0xff\n#define BIT_ACKTO_8822B(x)                                                     \\\n\t(((x) & BIT_MASK_ACKTO_8822B) << BIT_SHIFT_ACKTO_8822B)\n#define BITS_ACKTO_8822B (BIT_MASK_ACKTO_8822B << BIT_SHIFT_ACKTO_8822B)\n#define BIT_CLEAR_ACKTO_8822B(x) ((x) & (~BITS_ACKTO_8822B))\n#define BIT_GET_ACKTO_8822B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ACKTO_8822B) & BIT_MASK_ACKTO_8822B)\n#define BIT_SET_ACKTO_8822B(x, v)                                              \\\n\t(BIT_CLEAR_ACKTO_8822B(x) | BIT_ACKTO_8822B(v))\n\n/* 2 REG_NAV_CTRL_8822B (NAV CONTROL REGISTER) */\n\n#define BIT_SHIFT_NAV_UPPER_8822B 16\n#define BIT_MASK_NAV_UPPER_8822B 0xff\n#define BIT_NAV_UPPER_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_NAV_UPPER_8822B) << BIT_SHIFT_NAV_UPPER_8822B)\n#define BITS_NAV_UPPER_8822B                                                   \\\n\t(BIT_MASK_NAV_UPPER_8822B << BIT_SHIFT_NAV_UPPER_8822B)\n#define BIT_CLEAR_NAV_UPPER_8822B(x) ((x) & (~BITS_NAV_UPPER_8822B))\n#define BIT_GET_NAV_UPPER_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_NAV_UPPER_8822B) & BIT_MASK_NAV_UPPER_8822B)\n#define BIT_SET_NAV_UPPER_8822B(x, v)                                          \\\n\t(BIT_CLEAR_NAV_UPPER_8822B(x) | BIT_NAV_UPPER_8822B(v))\n\n#define BIT_SHIFT_RXMYRTS_NAV_8822B 8\n#define BIT_MASK_RXMYRTS_NAV_8822B 0xf\n#define BIT_RXMYRTS_NAV_8822B(x)                                               \\\n\t(((x) & BIT_MASK_RXMYRTS_NAV_8822B) << BIT_SHIFT_RXMYRTS_NAV_8822B)\n#define BITS_RXMYRTS_NAV_8822B                                                 \\\n\t(BIT_MASK_RXMYRTS_NAV_8822B << BIT_SHIFT_RXMYRTS_NAV_8822B)\n#define BIT_CLEAR_RXMYRTS_NAV_8822B(x) ((x) & (~BITS_RXMYRTS_NAV_8822B))\n#define BIT_GET_RXMYRTS_NAV_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_RXMYRTS_NAV_8822B) & BIT_MASK_RXMYRTS_NAV_8822B)\n#define BIT_SET_RXMYRTS_NAV_8822B(x, v)                                        \\\n\t(BIT_CLEAR_RXMYRTS_NAV_8822B(x) | BIT_RXMYRTS_NAV_8822B(v))\n\n#define BIT_SHIFT_RTSRST_8822B 0\n#define BIT_MASK_RTSRST_8822B 0xff\n#define BIT_RTSRST_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_RTSRST_8822B) << BIT_SHIFT_RTSRST_8822B)\n#define BITS_RTSRST_8822B (BIT_MASK_RTSRST_8822B << BIT_SHIFT_RTSRST_8822B)\n#define BIT_CLEAR_RTSRST_8822B(x) ((x) & (~BITS_RTSRST_8822B))\n#define BIT_GET_RTSRST_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_RTSRST_8822B) & BIT_MASK_RTSRST_8822B)\n#define BIT_SET_RTSRST_8822B(x, v)                                             \\\n\t(BIT_CLEAR_RTSRST_8822B(x) | BIT_RTSRST_8822B(v))\n\n/* 2 REG_BACAMCMD_8822B (BLOCK ACK CAM COMMAND REGISTER) */\n#define BIT_BACAM_POLL_8822B BIT(31)\n#define BIT_BACAM_RST_8822B BIT(17)\n#define BIT_BACAM_RW_8822B BIT(16)\n\n#define BIT_SHIFT_TXSBM_8822B 14\n#define BIT_MASK_TXSBM_8822B 0x3\n#define BIT_TXSBM_8822B(x)                                                     \\\n\t(((x) & BIT_MASK_TXSBM_8822B) << BIT_SHIFT_TXSBM_8822B)\n#define BITS_TXSBM_8822B (BIT_MASK_TXSBM_8822B << BIT_SHIFT_TXSBM_8822B)\n#define BIT_CLEAR_TXSBM_8822B(x) ((x) & (~BITS_TXSBM_8822B))\n#define BIT_GET_TXSBM_8822B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TXSBM_8822B) & BIT_MASK_TXSBM_8822B)\n#define BIT_SET_TXSBM_8822B(x, v)                                              \\\n\t(BIT_CLEAR_TXSBM_8822B(x) | BIT_TXSBM_8822B(v))\n\n#define BIT_SHIFT_BACAM_ADDR_8822B 0\n#define BIT_MASK_BACAM_ADDR_8822B 0x3f\n#define BIT_BACAM_ADDR_8822B(x)                                                \\\n\t(((x) & BIT_MASK_BACAM_ADDR_8822B) << BIT_SHIFT_BACAM_ADDR_8822B)\n#define BITS_BACAM_ADDR_8822B                                                  \\\n\t(BIT_MASK_BACAM_ADDR_8822B << BIT_SHIFT_BACAM_ADDR_8822B)\n#define BIT_CLEAR_BACAM_ADDR_8822B(x) ((x) & (~BITS_BACAM_ADDR_8822B))\n#define BIT_GET_BACAM_ADDR_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_BACAM_ADDR_8822B) & BIT_MASK_BACAM_ADDR_8822B)\n#define BIT_SET_BACAM_ADDR_8822B(x, v)                                         \\\n\t(BIT_CLEAR_BACAM_ADDR_8822B(x) | BIT_BACAM_ADDR_8822B(v))\n\n/* 2 REG_BACAMCONTENT_8822B (BLOCK ACK CAM CONTENT REGISTER) */\n\n#define BIT_SHIFT_BA_CONTENT_H_8822B (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_BA_CONTENT_H_8822B 0xffffffffL\n#define BIT_BA_CONTENT_H_8822B(x)                                              \\\n\t(((x) & BIT_MASK_BA_CONTENT_H_8822B) << BIT_SHIFT_BA_CONTENT_H_8822B)\n#define BITS_BA_CONTENT_H_8822B                                                \\\n\t(BIT_MASK_BA_CONTENT_H_8822B << BIT_SHIFT_BA_CONTENT_H_8822B)\n#define BIT_CLEAR_BA_CONTENT_H_8822B(x) ((x) & (~BITS_BA_CONTENT_H_8822B))\n#define BIT_GET_BA_CONTENT_H_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BA_CONTENT_H_8822B) & BIT_MASK_BA_CONTENT_H_8822B)\n#define BIT_SET_BA_CONTENT_H_8822B(x, v)                                       \\\n\t(BIT_CLEAR_BA_CONTENT_H_8822B(x) | BIT_BA_CONTENT_H_8822B(v))\n\n#define BIT_SHIFT_BA_CONTENT_L_8822B 0\n#define BIT_MASK_BA_CONTENT_L_8822B 0xffffffffL\n#define BIT_BA_CONTENT_L_8822B(x)                                              \\\n\t(((x) & BIT_MASK_BA_CONTENT_L_8822B) << BIT_SHIFT_BA_CONTENT_L_8822B)\n#define BITS_BA_CONTENT_L_8822B                                                \\\n\t(BIT_MASK_BA_CONTENT_L_8822B << BIT_SHIFT_BA_CONTENT_L_8822B)\n#define BIT_CLEAR_BA_CONTENT_L_8822B(x) ((x) & (~BITS_BA_CONTENT_L_8822B))\n#define BIT_GET_BA_CONTENT_L_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BA_CONTENT_L_8822B) & BIT_MASK_BA_CONTENT_L_8822B)\n#define BIT_SET_BA_CONTENT_L_8822B(x, v)                                       \\\n\t(BIT_CLEAR_BA_CONTENT_L_8822B(x) | BIT_BA_CONTENT_L_8822B(v))\n\n/* 2 REG_WMAC_BITMAP_CTL_8822B */\n#define BIT_BITMAP_VO_8822B BIT(7)\n#define BIT_BITMAP_VI_8822B BIT(6)\n#define BIT_BITMAP_BE_8822B BIT(5)\n#define BIT_BITMAP_BK_8822B BIT(4)\n\n#define BIT_SHIFT_BITMAP_CONDITION_8822B 2\n#define BIT_MASK_BITMAP_CONDITION_8822B 0x3\n#define BIT_BITMAP_CONDITION_8822B(x)                                          \\\n\t(((x) & BIT_MASK_BITMAP_CONDITION_8822B)                               \\\n\t << BIT_SHIFT_BITMAP_CONDITION_8822B)\n#define BITS_BITMAP_CONDITION_8822B                                            \\\n\t(BIT_MASK_BITMAP_CONDITION_8822B << BIT_SHIFT_BITMAP_CONDITION_8822B)\n#define BIT_CLEAR_BITMAP_CONDITION_8822B(x)                                    \\\n\t((x) & (~BITS_BITMAP_CONDITION_8822B))\n#define BIT_GET_BITMAP_CONDITION_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BITMAP_CONDITION_8822B) &                           \\\n\t BIT_MASK_BITMAP_CONDITION_8822B)\n#define BIT_SET_BITMAP_CONDITION_8822B(x, v)                                   \\\n\t(BIT_CLEAR_BITMAP_CONDITION_8822B(x) | BIT_BITMAP_CONDITION_8822B(v))\n\n#define BIT_BITMAP_SSNBK_COUNTER_CLR_8822B BIT(1)\n#define BIT_BITMAP_FORCE_8822B BIT(0)\n\n/* 2 REG_TX_RX_8822B STATUS */\n\n#define BIT_SHIFT_RXPKT_TYPE_8822B 2\n#define BIT_MASK_RXPKT_TYPE_8822B 0x3f\n#define BIT_RXPKT_TYPE_8822B(x)                                                \\\n\t(((x) & BIT_MASK_RXPKT_TYPE_8822B) << BIT_SHIFT_RXPKT_TYPE_8822B)\n#define BITS_RXPKT_TYPE_8822B                                                  \\\n\t(BIT_MASK_RXPKT_TYPE_8822B << BIT_SHIFT_RXPKT_TYPE_8822B)\n#define BIT_CLEAR_RXPKT_TYPE_8822B(x) ((x) & (~BITS_RXPKT_TYPE_8822B))\n#define BIT_GET_RXPKT_TYPE_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXPKT_TYPE_8822B) & BIT_MASK_RXPKT_TYPE_8822B)\n#define BIT_SET_RXPKT_TYPE_8822B(x, v)                                         \\\n\t(BIT_CLEAR_RXPKT_TYPE_8822B(x) | BIT_RXPKT_TYPE_8822B(v))\n\n#define BIT_TXACT_IND_8822B BIT(1)\n#define BIT_RXACT_IND_8822B BIT(0)\n\n/* 2 REG_WMAC_BACAM_RPMEN_8822B */\n\n#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B 2\n#define BIT_MASK_BITMAP_SSNBK_COUNTER_8822B 0x3f\n#define BIT_BITMAP_SSNBK_COUNTER_8822B(x)                                      \\\n\t(((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822B)                           \\\n\t << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B)\n#define BITS_BITMAP_SSNBK_COUNTER_8822B                                        \\\n\t(BIT_MASK_BITMAP_SSNBK_COUNTER_8822B                                   \\\n\t << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B)\n#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822B(x)                                \\\n\t((x) & (~BITS_BITMAP_SSNBK_COUNTER_8822B))\n#define BIT_GET_BITMAP_SSNBK_COUNTER_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B) &                       \\\n\t BIT_MASK_BITMAP_SSNBK_COUNTER_8822B)\n#define BIT_SET_BITMAP_SSNBK_COUNTER_8822B(x, v)                               \\\n\t(BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822B(x) |                             \\\n\t BIT_BITMAP_SSNBK_COUNTER_8822B(v))\n\n#define BIT_BITMAP_EN_8822B BIT(1)\n#define BIT_WMAC_BACAM_RPMEN_8822B BIT(0)\n\n/* 2 REG_LBDLY_8822B (LOOPBACK DELAY REGISTER) */\n\n#define BIT_SHIFT_LBDLY_8822B 0\n#define BIT_MASK_LBDLY_8822B 0x1f\n#define BIT_LBDLY_8822B(x)                                                     \\\n\t(((x) & BIT_MASK_LBDLY_8822B) << BIT_SHIFT_LBDLY_8822B)\n#define BITS_LBDLY_8822B (BIT_MASK_LBDLY_8822B << BIT_SHIFT_LBDLY_8822B)\n#define BIT_CLEAR_LBDLY_8822B(x) ((x) & (~BITS_LBDLY_8822B))\n#define BIT_GET_LBDLY_8822B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_LBDLY_8822B) & BIT_MASK_LBDLY_8822B)\n#define BIT_SET_LBDLY_8822B(x, v)                                              \\\n\t(BIT_CLEAR_LBDLY_8822B(x) | BIT_LBDLY_8822B(v))\n\n/* 2 REG_RXERR_RPT_8822B (RX ERROR REPORT REGISTER) */\n\n#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B 28\n#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B 0xf\n#define BIT_RXERR_RPT_SEL_V1_3_0_8822B(x)                                      \\\n\t(((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B)                           \\\n\t << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B)\n#define BITS_RXERR_RPT_SEL_V1_3_0_8822B                                        \\\n\t(BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B                                   \\\n\t << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B)\n#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822B(x)                                \\\n\t((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8822B))\n#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B) &                       \\\n\t BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B)\n#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8822B(x, v)                               \\\n\t(BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822B(x) |                             \\\n\t BIT_RXERR_RPT_SEL_V1_3_0_8822B(v))\n\n#define BIT_RXERR_RPT_RST_8822B BIT(27)\n#define BIT_RXERR_RPT_SEL_V1_4_8822B BIT(26)\n#define BIT_W1S_8822B BIT(23)\n#define BIT_UD_SELECT_BSSID_8822B BIT(22)\n\n#define BIT_SHIFT_UD_SUB_TYPE_8822B 18\n#define BIT_MASK_UD_SUB_TYPE_8822B 0xf\n#define BIT_UD_SUB_TYPE_8822B(x)                                               \\\n\t(((x) & BIT_MASK_UD_SUB_TYPE_8822B) << BIT_SHIFT_UD_SUB_TYPE_8822B)\n#define BITS_UD_SUB_TYPE_8822B                                                 \\\n\t(BIT_MASK_UD_SUB_TYPE_8822B << BIT_SHIFT_UD_SUB_TYPE_8822B)\n#define BIT_CLEAR_UD_SUB_TYPE_8822B(x) ((x) & (~BITS_UD_SUB_TYPE_8822B))\n#define BIT_GET_UD_SUB_TYPE_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_UD_SUB_TYPE_8822B) & BIT_MASK_UD_SUB_TYPE_8822B)\n#define BIT_SET_UD_SUB_TYPE_8822B(x, v)                                        \\\n\t(BIT_CLEAR_UD_SUB_TYPE_8822B(x) | BIT_UD_SUB_TYPE_8822B(v))\n\n#define BIT_SHIFT_UD_TYPE_8822B 16\n#define BIT_MASK_UD_TYPE_8822B 0x3\n#define BIT_UD_TYPE_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_UD_TYPE_8822B) << BIT_SHIFT_UD_TYPE_8822B)\n#define BITS_UD_TYPE_8822B (BIT_MASK_UD_TYPE_8822B << BIT_SHIFT_UD_TYPE_8822B)\n#define BIT_CLEAR_UD_TYPE_8822B(x) ((x) & (~BITS_UD_TYPE_8822B))\n#define BIT_GET_UD_TYPE_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_UD_TYPE_8822B) & BIT_MASK_UD_TYPE_8822B)\n#define BIT_SET_UD_TYPE_8822B(x, v)                                            \\\n\t(BIT_CLEAR_UD_TYPE_8822B(x) | BIT_UD_TYPE_8822B(v))\n\n#define BIT_SHIFT_RPT_COUNTER_8822B 0\n#define BIT_MASK_RPT_COUNTER_8822B 0xffff\n#define BIT_RPT_COUNTER_8822B(x)                                               \\\n\t(((x) & BIT_MASK_RPT_COUNTER_8822B) << BIT_SHIFT_RPT_COUNTER_8822B)\n#define BITS_RPT_COUNTER_8822B                                                 \\\n\t(BIT_MASK_RPT_COUNTER_8822B << BIT_SHIFT_RPT_COUNTER_8822B)\n#define BIT_CLEAR_RPT_COUNTER_8822B(x) ((x) & (~BITS_RPT_COUNTER_8822B))\n#define BIT_GET_RPT_COUNTER_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_RPT_COUNTER_8822B) & BIT_MASK_RPT_COUNTER_8822B)\n#define BIT_SET_RPT_COUNTER_8822B(x, v)                                        \\\n\t(BIT_CLEAR_RPT_COUNTER_8822B(x) | BIT_RPT_COUNTER_8822B(v))\n\n/* 2 REG_WMAC_TRXPTCL_CTL_8822B (WMAC TX/RX PROTOCOL CONTROL REGISTER) */\n\n#define BIT_SHIFT_ACKBA_TYPSEL_8822B (60 & CPU_OPT_WIDTH)\n#define BIT_MASK_ACKBA_TYPSEL_8822B 0xf\n#define BIT_ACKBA_TYPSEL_8822B(x)                                              \\\n\t(((x) & BIT_MASK_ACKBA_TYPSEL_8822B) << BIT_SHIFT_ACKBA_TYPSEL_8822B)\n#define BITS_ACKBA_TYPSEL_8822B                                                \\\n\t(BIT_MASK_ACKBA_TYPSEL_8822B << BIT_SHIFT_ACKBA_TYPSEL_8822B)\n#define BIT_CLEAR_ACKBA_TYPSEL_8822B(x) ((x) & (~BITS_ACKBA_TYPSEL_8822B))\n#define BIT_GET_ACKBA_TYPSEL_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_ACKBA_TYPSEL_8822B) & BIT_MASK_ACKBA_TYPSEL_8822B)\n#define BIT_SET_ACKBA_TYPSEL_8822B(x, v)                                       \\\n\t(BIT_CLEAR_ACKBA_TYPSEL_8822B(x) | BIT_ACKBA_TYPSEL_8822B(v))\n\n#define BIT_SHIFT_ACKBA_ACKPCHK_8822B (56 & CPU_OPT_WIDTH)\n#define BIT_MASK_ACKBA_ACKPCHK_8822B 0xf\n#define BIT_ACKBA_ACKPCHK_8822B(x)                                             \\\n\t(((x) & BIT_MASK_ACKBA_ACKPCHK_8822B) << BIT_SHIFT_ACKBA_ACKPCHK_8822B)\n#define BITS_ACKBA_ACKPCHK_8822B                                               \\\n\t(BIT_MASK_ACKBA_ACKPCHK_8822B << BIT_SHIFT_ACKBA_ACKPCHK_8822B)\n#define BIT_CLEAR_ACKBA_ACKPCHK_8822B(x) ((x) & (~BITS_ACKBA_ACKPCHK_8822B))\n#define BIT_GET_ACKBA_ACKPCHK_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8822B) & BIT_MASK_ACKBA_ACKPCHK_8822B)\n#define BIT_SET_ACKBA_ACKPCHK_8822B(x, v)                                      \\\n\t(BIT_CLEAR_ACKBA_ACKPCHK_8822B(x) | BIT_ACKBA_ACKPCHK_8822B(v))\n\n#define BIT_SHIFT_ACKBAR_TYPESEL_8822B (48 & CPU_OPT_WIDTH)\n#define BIT_MASK_ACKBAR_TYPESEL_8822B 0xff\n#define BIT_ACKBAR_TYPESEL_8822B(x)                                            \\\n\t(((x) & BIT_MASK_ACKBAR_TYPESEL_8822B)                                 \\\n\t << BIT_SHIFT_ACKBAR_TYPESEL_8822B)\n#define BITS_ACKBAR_TYPESEL_8822B                                              \\\n\t(BIT_MASK_ACKBAR_TYPESEL_8822B << BIT_SHIFT_ACKBAR_TYPESEL_8822B)\n#define BIT_CLEAR_ACKBAR_TYPESEL_8822B(x) ((x) & (~BITS_ACKBAR_TYPESEL_8822B))\n#define BIT_GET_ACKBAR_TYPESEL_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8822B) &                             \\\n\t BIT_MASK_ACKBAR_TYPESEL_8822B)\n#define BIT_SET_ACKBAR_TYPESEL_8822B(x, v)                                     \\\n\t(BIT_CLEAR_ACKBAR_TYPESEL_8822B(x) | BIT_ACKBAR_TYPESEL_8822B(v))\n\n#define BIT_SHIFT_ACKBAR_ACKPCHK_8822B (44 & CPU_OPT_WIDTH)\n#define BIT_MASK_ACKBAR_ACKPCHK_8822B 0xf\n#define BIT_ACKBAR_ACKPCHK_8822B(x)                                            \\\n\t(((x) & BIT_MASK_ACKBAR_ACKPCHK_8822B)                                 \\\n\t << BIT_SHIFT_ACKBAR_ACKPCHK_8822B)\n#define BITS_ACKBAR_ACKPCHK_8822B                                              \\\n\t(BIT_MASK_ACKBAR_ACKPCHK_8822B << BIT_SHIFT_ACKBAR_ACKPCHK_8822B)\n#define BIT_CLEAR_ACKBAR_ACKPCHK_8822B(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8822B))\n#define BIT_GET_ACKBAR_ACKPCHK_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8822B) &                             \\\n\t BIT_MASK_ACKBAR_ACKPCHK_8822B)\n#define BIT_SET_ACKBAR_ACKPCHK_8822B(x, v)                                     \\\n\t(BIT_CLEAR_ACKBAR_ACKPCHK_8822B(x) | BIT_ACKBAR_ACKPCHK_8822B(v))\n\n#define BIT_RXBA_IGNOREA2_8822B BIT(42)\n#define BIT_EN_SAVE_ALL_TXOPADDR_8822B BIT(41)\n#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_8822B BIT(40)\n#define BIT_DIS_TXBA_AMPDUFCSERR_8822B BIT(39)\n#define BIT_DIS_TXBA_RXBARINFULL_8822B BIT(38)\n#define BIT_DIS_TXCFE_INFULL_8822B BIT(37)\n#define BIT_DIS_TXCTS_INFULL_8822B BIT(36)\n#define BIT_EN_TXACKBA_IN_TX_RDG_8822B BIT(35)\n#define BIT_EN_TXACKBA_IN_TXOP_8822B BIT(34)\n#define BIT_EN_TXCTS_IN_RXNAV_8822B BIT(33)\n#define BIT_EN_TXCTS_INTXOP_8822B BIT(32)\n#define BIT_BLK_EDCA_BBSLP_8822B BIT(31)\n#define BIT_BLK_EDCA_BBSBY_8822B BIT(30)\n#define BIT_ACKTO_BLOCK_SCH_EN_8822B BIT(27)\n#define BIT_EIFS_BLOCK_SCH_EN_8822B BIT(26)\n#define BIT_PLCPCHK_RST_EIFS_8822B BIT(25)\n#define BIT_CCA_RST_EIFS_8822B BIT(24)\n#define BIT_DIS_UPD_MYRXPKTNAV_8822B BIT(23)\n#define BIT_EARLY_TXBA_8822B BIT(22)\n\n#define BIT_SHIFT_RESP_CHNBUSY_8822B 20\n#define BIT_MASK_RESP_CHNBUSY_8822B 0x3\n#define BIT_RESP_CHNBUSY_8822B(x)                                              \\\n\t(((x) & BIT_MASK_RESP_CHNBUSY_8822B) << BIT_SHIFT_RESP_CHNBUSY_8822B)\n#define BITS_RESP_CHNBUSY_8822B                                                \\\n\t(BIT_MASK_RESP_CHNBUSY_8822B << BIT_SHIFT_RESP_CHNBUSY_8822B)\n#define BIT_CLEAR_RESP_CHNBUSY_8822B(x) ((x) & (~BITS_RESP_CHNBUSY_8822B))\n#define BIT_GET_RESP_CHNBUSY_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RESP_CHNBUSY_8822B) & BIT_MASK_RESP_CHNBUSY_8822B)\n#define BIT_SET_RESP_CHNBUSY_8822B(x, v)                                       \\\n\t(BIT_CLEAR_RESP_CHNBUSY_8822B(x) | BIT_RESP_CHNBUSY_8822B(v))\n\n#define BIT_RESP_DCTS_EN_8822B BIT(19)\n#define BIT_RESP_DCFE_EN_8822B BIT(18)\n#define BIT_RESP_SPLCPEN_8822B BIT(17)\n#define BIT_RESP_SGIEN_8822B BIT(16)\n#define BIT_RESP_LDPC_EN_8822B BIT(15)\n#define BIT_DIS_RESP_ACKINCCA_8822B BIT(14)\n#define BIT_DIS_RESP_CTSINCCA_8822B BIT(13)\n\n#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B 10\n#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B 0x7\n#define BIT_R_WMAC_SECOND_CCA_TIMER_8822B(x)                                   \\\n\t(((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B)                        \\\n\t << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B)\n#define BITS_R_WMAC_SECOND_CCA_TIMER_8822B                                     \\\n\t(BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B                                \\\n\t << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B)\n#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822B(x)                             \\\n\t((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8822B))\n#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8822B(x)                               \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B) &                    \\\n\t BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B)\n#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8822B(x, v)                            \\\n\t(BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822B(x) |                          \\\n\t BIT_R_WMAC_SECOND_CCA_TIMER_8822B(v))\n\n#define BIT_SHIFT_RFMOD_8822B 7\n#define BIT_MASK_RFMOD_8822B 0x3\n#define BIT_RFMOD_8822B(x)                                                     \\\n\t(((x) & BIT_MASK_RFMOD_8822B) << BIT_SHIFT_RFMOD_8822B)\n#define BITS_RFMOD_8822B (BIT_MASK_RFMOD_8822B << BIT_SHIFT_RFMOD_8822B)\n#define BIT_CLEAR_RFMOD_8822B(x) ((x) & (~BITS_RFMOD_8822B))\n#define BIT_GET_RFMOD_8822B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RFMOD_8822B) & BIT_MASK_RFMOD_8822B)\n#define BIT_SET_RFMOD_8822B(x, v)                                              \\\n\t(BIT_CLEAR_RFMOD_8822B(x) | BIT_RFMOD_8822B(v))\n\n#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B 5\n#define BIT_MASK_RESP_CTS_DYNBW_SEL_8822B 0x3\n#define BIT_RESP_CTS_DYNBW_SEL_8822B(x)                                        \\\n\t(((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822B)                             \\\n\t << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B)\n#define BITS_RESP_CTS_DYNBW_SEL_8822B                                          \\\n\t(BIT_MASK_RESP_CTS_DYNBW_SEL_8822B                                     \\\n\t << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B)\n#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822B(x)                                  \\\n\t((x) & (~BITS_RESP_CTS_DYNBW_SEL_8822B))\n#define BIT_GET_RESP_CTS_DYNBW_SEL_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B) &                         \\\n\t BIT_MASK_RESP_CTS_DYNBW_SEL_8822B)\n#define BIT_SET_RESP_CTS_DYNBW_SEL_8822B(x, v)                                 \\\n\t(BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822B(x) |                               \\\n\t BIT_RESP_CTS_DYNBW_SEL_8822B(v))\n\n#define BIT_DLY_TX_WAIT_RXANTSEL_8822B BIT(4)\n#define BIT_TXRESP_BY_RXANTSEL_8822B BIT(3)\n\n#define BIT_SHIFT_ORIG_DCTS_CHK_8822B 0\n#define BIT_MASK_ORIG_DCTS_CHK_8822B 0x3\n#define BIT_ORIG_DCTS_CHK_8822B(x)                                             \\\n\t(((x) & BIT_MASK_ORIG_DCTS_CHK_8822B) << BIT_SHIFT_ORIG_DCTS_CHK_8822B)\n#define BITS_ORIG_DCTS_CHK_8822B                                               \\\n\t(BIT_MASK_ORIG_DCTS_CHK_8822B << BIT_SHIFT_ORIG_DCTS_CHK_8822B)\n#define BIT_CLEAR_ORIG_DCTS_CHK_8822B(x) ((x) & (~BITS_ORIG_DCTS_CHK_8822B))\n#define BIT_GET_ORIG_DCTS_CHK_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8822B) & BIT_MASK_ORIG_DCTS_CHK_8822B)\n#define BIT_SET_ORIG_DCTS_CHK_8822B(x, v)                                      \\\n\t(BIT_CLEAR_ORIG_DCTS_CHK_8822B(x) | BIT_ORIG_DCTS_CHK_8822B(v))\n\n/* 2 REG_CAMCMD_8822B (CAM COMMAND REGISTER) */\n#define BIT_SECCAM_POLLING_8822B BIT(31)\n#define BIT_SECCAM_CLR_8822B BIT(30)\n#define BIT_MFBCAM_CLR_8822B BIT(29)\n#define BIT_SECCAM_WE_8822B BIT(16)\n\n#define BIT_SHIFT_SECCAM_ADDR_V2_8822B 0\n#define BIT_MASK_SECCAM_ADDR_V2_8822B 0x3ff\n#define BIT_SECCAM_ADDR_V2_8822B(x)                                            \\\n\t(((x) & BIT_MASK_SECCAM_ADDR_V2_8822B)                                 \\\n\t << BIT_SHIFT_SECCAM_ADDR_V2_8822B)\n#define BITS_SECCAM_ADDR_V2_8822B                                              \\\n\t(BIT_MASK_SECCAM_ADDR_V2_8822B << BIT_SHIFT_SECCAM_ADDR_V2_8822B)\n#define BIT_CLEAR_SECCAM_ADDR_V2_8822B(x) ((x) & (~BITS_SECCAM_ADDR_V2_8822B))\n#define BIT_GET_SECCAM_ADDR_V2_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8822B) &                             \\\n\t BIT_MASK_SECCAM_ADDR_V2_8822B)\n#define BIT_SET_SECCAM_ADDR_V2_8822B(x, v)                                     \\\n\t(BIT_CLEAR_SECCAM_ADDR_V2_8822B(x) | BIT_SECCAM_ADDR_V2_8822B(v))\n\n/* 2 REG_CAMWRITE_8822B (CAM WRITE REGISTER) */\n\n#define BIT_SHIFT_CAMW_DATA_8822B 0\n#define BIT_MASK_CAMW_DATA_8822B 0xffffffffL\n#define BIT_CAMW_DATA_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_CAMW_DATA_8822B) << BIT_SHIFT_CAMW_DATA_8822B)\n#define BITS_CAMW_DATA_8822B                                                   \\\n\t(BIT_MASK_CAMW_DATA_8822B << BIT_SHIFT_CAMW_DATA_8822B)\n#define BIT_CLEAR_CAMW_DATA_8822B(x) ((x) & (~BITS_CAMW_DATA_8822B))\n#define BIT_GET_CAMW_DATA_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_CAMW_DATA_8822B) & BIT_MASK_CAMW_DATA_8822B)\n#define BIT_SET_CAMW_DATA_8822B(x, v)                                          \\\n\t(BIT_CLEAR_CAMW_DATA_8822B(x) | BIT_CAMW_DATA_8822B(v))\n\n/* 2 REG_CAMREAD_8822B (CAM READ REGISTER) */\n\n#define BIT_SHIFT_CAMR_DATA_8822B 0\n#define BIT_MASK_CAMR_DATA_8822B 0xffffffffL\n#define BIT_CAMR_DATA_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_CAMR_DATA_8822B) << BIT_SHIFT_CAMR_DATA_8822B)\n#define BITS_CAMR_DATA_8822B                                                   \\\n\t(BIT_MASK_CAMR_DATA_8822B << BIT_SHIFT_CAMR_DATA_8822B)\n#define BIT_CLEAR_CAMR_DATA_8822B(x) ((x) & (~BITS_CAMR_DATA_8822B))\n#define BIT_GET_CAMR_DATA_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_CAMR_DATA_8822B) & BIT_MASK_CAMR_DATA_8822B)\n#define BIT_SET_CAMR_DATA_8822B(x, v)                                          \\\n\t(BIT_CLEAR_CAMR_DATA_8822B(x) | BIT_CAMR_DATA_8822B(v))\n\n/* 2 REG_CAMDBG_8822B (CAM DEBUG REGISTER) */\n#define BIT_SECCAM_INFO_8822B BIT(31)\n#define BIT_SEC_KEYFOUND_8822B BIT(15)\n\n#define BIT_SHIFT_CAMDBG_SEC_TYPE_8822B 12\n#define BIT_MASK_CAMDBG_SEC_TYPE_8822B 0x7\n#define BIT_CAMDBG_SEC_TYPE_8822B(x)                                           \\\n\t(((x) & BIT_MASK_CAMDBG_SEC_TYPE_8822B)                                \\\n\t << BIT_SHIFT_CAMDBG_SEC_TYPE_8822B)\n#define BITS_CAMDBG_SEC_TYPE_8822B                                             \\\n\t(BIT_MASK_CAMDBG_SEC_TYPE_8822B << BIT_SHIFT_CAMDBG_SEC_TYPE_8822B)\n#define BIT_CLEAR_CAMDBG_SEC_TYPE_8822B(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8822B))\n#define BIT_GET_CAMDBG_SEC_TYPE_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8822B) &                            \\\n\t BIT_MASK_CAMDBG_SEC_TYPE_8822B)\n#define BIT_SET_CAMDBG_SEC_TYPE_8822B(x, v)                                    \\\n\t(BIT_CLEAR_CAMDBG_SEC_TYPE_8822B(x) | BIT_CAMDBG_SEC_TYPE_8822B(v))\n\n#define BIT_CAMDBG_EXT_SECTYPE_8822B BIT(11)\n\n#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B 5\n#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B 0x1f\n#define BIT_CAMDBG_MIC_KEY_IDX_8822B(x)                                        \\\n\t(((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B)                             \\\n\t << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B)\n#define BITS_CAMDBG_MIC_KEY_IDX_8822B                                          \\\n\t(BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B                                     \\\n\t << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B)\n#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822B(x)                                  \\\n\t((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8822B))\n#define BIT_GET_CAMDBG_MIC_KEY_IDX_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B) &                         \\\n\t BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B)\n#define BIT_SET_CAMDBG_MIC_KEY_IDX_8822B(x, v)                                 \\\n\t(BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822B(x) |                               \\\n\t BIT_CAMDBG_MIC_KEY_IDX_8822B(v))\n\n#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B 0\n#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B 0x1f\n#define BIT_CAMDBG_SEC_KEY_IDX_8822B(x)                                        \\\n\t(((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B)                             \\\n\t << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B)\n#define BITS_CAMDBG_SEC_KEY_IDX_8822B                                          \\\n\t(BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B                                     \\\n\t << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B)\n#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822B(x)                                  \\\n\t((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8822B))\n#define BIT_GET_CAMDBG_SEC_KEY_IDX_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B) &                         \\\n\t BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B)\n#define BIT_SET_CAMDBG_SEC_KEY_IDX_8822B(x, v)                                 \\\n\t(BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822B(x) |                               \\\n\t BIT_CAMDBG_SEC_KEY_IDX_8822B(v))\n\n/* 2 REG_RXFILTER_ACTION_1_8822B */\n\n#define BIT_SHIFT_RXFILTER_ACTION_1_8822B 0\n#define BIT_MASK_RXFILTER_ACTION_1_8822B 0xff\n#define BIT_RXFILTER_ACTION_1_8822B(x)                                         \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_1_8822B)                              \\\n\t << BIT_SHIFT_RXFILTER_ACTION_1_8822B)\n#define BITS_RXFILTER_ACTION_1_8822B                                           \\\n\t(BIT_MASK_RXFILTER_ACTION_1_8822B << BIT_SHIFT_RXFILTER_ACTION_1_8822B)\n#define BIT_CLEAR_RXFILTER_ACTION_1_8822B(x)                                   \\\n\t((x) & (~BITS_RXFILTER_ACTION_1_8822B))\n#define BIT_GET_RXFILTER_ACTION_1_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8822B) &                          \\\n\t BIT_MASK_RXFILTER_ACTION_1_8822B)\n#define BIT_SET_RXFILTER_ACTION_1_8822B(x, v)                                  \\\n\t(BIT_CLEAR_RXFILTER_ACTION_1_8822B(x) | BIT_RXFILTER_ACTION_1_8822B(v))\n\n/* 2 REG_RXFILTER_CATEGORY_1_8822B */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_1_8822B 0\n#define BIT_MASK_RXFILTER_CATEGORY_1_8822B 0xff\n#define BIT_RXFILTER_CATEGORY_1_8822B(x)                                       \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_1_8822B)                            \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_1_8822B)\n#define BITS_RXFILTER_CATEGORY_1_8822B                                         \\\n\t(BIT_MASK_RXFILTER_CATEGORY_1_8822B                                    \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_1_8822B)\n#define BIT_CLEAR_RXFILTER_CATEGORY_1_8822B(x)                                 \\\n\t((x) & (~BITS_RXFILTER_CATEGORY_1_8822B))\n#define BIT_GET_RXFILTER_CATEGORY_1_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8822B) &                        \\\n\t BIT_MASK_RXFILTER_CATEGORY_1_8822B)\n#define BIT_SET_RXFILTER_CATEGORY_1_8822B(x, v)                                \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_1_8822B(x) |                              \\\n\t BIT_RXFILTER_CATEGORY_1_8822B(v))\n\n/* 2 REG_SECCFG_8822B (SECURITY CONFIGURATION REGISTER) */\n#define BIT_DIS_GCLK_WAPI_8822B BIT(15)\n#define BIT_DIS_GCLK_AES_8822B BIT(14)\n#define BIT_DIS_GCLK_TKIP_8822B BIT(13)\n#define BIT_AES_SEL_QC_1_8822B BIT(12)\n#define BIT_AES_SEL_QC_0_8822B BIT(11)\n#define BIT_CHK_BMC_8822B BIT(9)\n#define BIT_CHK_KEYID_8822B BIT(8)\n#define BIT_RXBCUSEDK_8822B BIT(7)\n#define BIT_TXBCUSEDK_8822B BIT(6)\n#define BIT_NOSKMC_8822B BIT(5)\n#define BIT_SKBYA2_8822B BIT(4)\n#define BIT_RXDEC_8822B BIT(3)\n#define BIT_TXENC_8822B BIT(2)\n#define BIT_RXUHUSEDK_8822B BIT(1)\n#define BIT_TXUHUSEDK_8822B BIT(0)\n\n/* 2 REG_RXFILTER_ACTION_3_8822B */\n\n#define BIT_SHIFT_RXFILTER_ACTION_3_8822B 0\n#define BIT_MASK_RXFILTER_ACTION_3_8822B 0xff\n#define BIT_RXFILTER_ACTION_3_8822B(x)                                         \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_3_8822B)                              \\\n\t << BIT_SHIFT_RXFILTER_ACTION_3_8822B)\n#define BITS_RXFILTER_ACTION_3_8822B                                           \\\n\t(BIT_MASK_RXFILTER_ACTION_3_8822B << BIT_SHIFT_RXFILTER_ACTION_3_8822B)\n#define BIT_CLEAR_RXFILTER_ACTION_3_8822B(x)                                   \\\n\t((x) & (~BITS_RXFILTER_ACTION_3_8822B))\n#define BIT_GET_RXFILTER_ACTION_3_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8822B) &                          \\\n\t BIT_MASK_RXFILTER_ACTION_3_8822B)\n#define BIT_SET_RXFILTER_ACTION_3_8822B(x, v)                                  \\\n\t(BIT_CLEAR_RXFILTER_ACTION_3_8822B(x) | BIT_RXFILTER_ACTION_3_8822B(v))\n\n/* 2 REG_RXFILTER_CATEGORY_3_8822B */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_3_8822B 0\n#define BIT_MASK_RXFILTER_CATEGORY_3_8822B 0xff\n#define BIT_RXFILTER_CATEGORY_3_8822B(x)                                       \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_3_8822B)                            \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_3_8822B)\n#define BITS_RXFILTER_CATEGORY_3_8822B                                         \\\n\t(BIT_MASK_RXFILTER_CATEGORY_3_8822B                                    \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_3_8822B)\n#define BIT_CLEAR_RXFILTER_CATEGORY_3_8822B(x)                                 \\\n\t((x) & (~BITS_RXFILTER_CATEGORY_3_8822B))\n#define BIT_GET_RXFILTER_CATEGORY_3_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8822B) &                        \\\n\t BIT_MASK_RXFILTER_CATEGORY_3_8822B)\n#define BIT_SET_RXFILTER_CATEGORY_3_8822B(x, v)                                \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_3_8822B(x) |                              \\\n\t BIT_RXFILTER_CATEGORY_3_8822B(v))\n\n/* 2 REG_RXFILTER_ACTION_2_8822B */\n\n#define BIT_SHIFT_RXFILTER_ACTION_2_8822B 0\n#define BIT_MASK_RXFILTER_ACTION_2_8822B 0xff\n#define BIT_RXFILTER_ACTION_2_8822B(x)                                         \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_2_8822B)                              \\\n\t << BIT_SHIFT_RXFILTER_ACTION_2_8822B)\n#define BITS_RXFILTER_ACTION_2_8822B                                           \\\n\t(BIT_MASK_RXFILTER_ACTION_2_8822B << BIT_SHIFT_RXFILTER_ACTION_2_8822B)\n#define BIT_CLEAR_RXFILTER_ACTION_2_8822B(x)                                   \\\n\t((x) & (~BITS_RXFILTER_ACTION_2_8822B))\n#define BIT_GET_RXFILTER_ACTION_2_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8822B) &                          \\\n\t BIT_MASK_RXFILTER_ACTION_2_8822B)\n#define BIT_SET_RXFILTER_ACTION_2_8822B(x, v)                                  \\\n\t(BIT_CLEAR_RXFILTER_ACTION_2_8822B(x) | BIT_RXFILTER_ACTION_2_8822B(v))\n\n/* 2 REG_RXFILTER_CATEGORY_2_8822B */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_2_8822B 0\n#define BIT_MASK_RXFILTER_CATEGORY_2_8822B 0xff\n#define BIT_RXFILTER_CATEGORY_2_8822B(x)                                       \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_2_8822B)                            \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_2_8822B)\n#define BITS_RXFILTER_CATEGORY_2_8822B                                         \\\n\t(BIT_MASK_RXFILTER_CATEGORY_2_8822B                                    \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_2_8822B)\n#define BIT_CLEAR_RXFILTER_CATEGORY_2_8822B(x)                                 \\\n\t((x) & (~BITS_RXFILTER_CATEGORY_2_8822B))\n#define BIT_GET_RXFILTER_CATEGORY_2_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8822B) &                        \\\n\t BIT_MASK_RXFILTER_CATEGORY_2_8822B)\n#define BIT_SET_RXFILTER_CATEGORY_2_8822B(x, v)                                \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_2_8822B(x) |                              \\\n\t BIT_RXFILTER_CATEGORY_2_8822B(v))\n\n/* 2 REG_RXFLTMAP4_8822B (RX FILTER MAP GROUP 4) */\n#define BIT_CTRLFLT15EN_FW_8822B BIT(15)\n#define BIT_CTRLFLT14EN_FW_8822B BIT(14)\n#define BIT_CTRLFLT13EN_FW_8822B BIT(13)\n#define BIT_CTRLFLT12EN_FW_8822B BIT(12)\n#define BIT_CTRLFLT11EN_FW_8822B BIT(11)\n#define BIT_CTRLFLT10EN_FW_8822B BIT(10)\n#define BIT_CTRLFLT9EN_FW_8822B BIT(9)\n#define BIT_CTRLFLT8EN_FW_8822B BIT(8)\n#define BIT_CTRLFLT7EN_FW_8822B BIT(7)\n#define BIT_CTRLFLT6EN_FW_8822B BIT(6)\n#define BIT_CTRLFLT5EN_FW_8822B BIT(5)\n#define BIT_CTRLFLT4EN_FW_8822B BIT(4)\n#define BIT_CTRLFLT3EN_FW_8822B BIT(3)\n#define BIT_CTRLFLT2EN_FW_8822B BIT(2)\n#define BIT_CTRLFLT1EN_FW_8822B BIT(1)\n#define BIT_CTRLFLT0EN_FW_8822B BIT(0)\n\n/* 2 REG_RXFLTMAP3_8822B (RX FILTER MAP GROUP 3) */\n#define BIT_MGTFLT15EN_FW_8822B BIT(15)\n#define BIT_MGTFLT14EN_FW_8822B BIT(14)\n#define BIT_MGTFLT13EN_FW_8822B BIT(13)\n#define BIT_MGTFLT12EN_FW_8822B BIT(12)\n#define BIT_MGTFLT11EN_FW_8822B BIT(11)\n#define BIT_MGTFLT10EN_FW_8822B BIT(10)\n#define BIT_MGTFLT9EN_FW_8822B BIT(9)\n#define BIT_MGTFLT8EN_FW_8822B BIT(8)\n#define BIT_MGTFLT7EN_FW_8822B BIT(7)\n#define BIT_MGTFLT6EN_FW_8822B BIT(6)\n#define BIT_MGTFLT5EN_FW_8822B BIT(5)\n#define BIT_MGTFLT4EN_FW_8822B BIT(4)\n#define BIT_MGTFLT3EN_FW_8822B BIT(3)\n#define BIT_MGTFLT2EN_FW_8822B BIT(2)\n#define BIT_MGTFLT1EN_FW_8822B BIT(1)\n#define BIT_MGTFLT0EN_FW_8822B BIT(0)\n\n/* 2 REG_RXFLTMAP6_8822B (RX FILTER MAP GROUP 6) */\n#define BIT_ACTIONFLT15EN_FW_8822B BIT(15)\n#define BIT_ACTIONFLT14EN_FW_8822B BIT(14)\n#define BIT_ACTIONFLT13EN_FW_8822B BIT(13)\n#define BIT_ACTIONFLT12EN_FW_8822B BIT(12)\n#define BIT_ACTIONFLT11EN_FW_8822B BIT(11)\n#define BIT_ACTIONFLT10EN_FW_8822B BIT(10)\n#define BIT_ACTIONFLT9EN_FW_8822B BIT(9)\n#define BIT_ACTIONFLT8EN_FW_8822B BIT(8)\n#define BIT_ACTIONFLT7EN_FW_8822B BIT(7)\n#define BIT_ACTIONFLT6EN_FW_8822B BIT(6)\n#define BIT_ACTIONFLT5EN_FW_8822B BIT(5)\n#define BIT_ACTIONFLT4EN_FW_8822B BIT(4)\n#define BIT_ACTIONFLT3EN_FW_8822B BIT(3)\n#define BIT_ACTIONFLT2EN_FW_8822B BIT(2)\n#define BIT_ACTIONFLT1EN_FW_8822B BIT(1)\n#define BIT_ACTIONFLT0EN_FW_8822B BIT(0)\n\n/* 2 REG_RXFLTMAP5_8822B (RX FILTER MAP GROUP 5) */\n#define BIT_DATAFLT15EN_FW_8822B BIT(15)\n#define BIT_DATAFLT14EN_FW_8822B BIT(14)\n#define BIT_DATAFLT13EN_FW_8822B BIT(13)\n#define BIT_DATAFLT12EN_FW_8822B BIT(12)\n#define BIT_DATAFLT11EN_FW_8822B BIT(11)\n#define BIT_DATAFLT10EN_FW_8822B BIT(10)\n#define BIT_DATAFLT9EN_FW_8822B BIT(9)\n#define BIT_DATAFLT8EN_FW_8822B BIT(8)\n#define BIT_DATAFLT7EN_FW_8822B BIT(7)\n#define BIT_DATAFLT6EN_FW_8822B BIT(6)\n#define BIT_DATAFLT5EN_FW_8822B BIT(5)\n#define BIT_DATAFLT4EN_FW_8822B BIT(4)\n#define BIT_DATAFLT3EN_FW_8822B BIT(3)\n#define BIT_DATAFLT2EN_FW_8822B BIT(2)\n#define BIT_DATAFLT1EN_FW_8822B BIT(1)\n#define BIT_DATAFLT0EN_FW_8822B BIT(0)\n\n/* 2 REG_WMMPS_UAPSD_TID_8822B (WMM POWER SAVE UAPSD TID REGISTER) */\n#define BIT_WMMPS_UAPSD_TID7_8822B BIT(7)\n#define BIT_WMMPS_UAPSD_TID6_8822B BIT(6)\n#define BIT_WMMPS_UAPSD_TID5_8822B BIT(5)\n#define BIT_WMMPS_UAPSD_TID4_8822B BIT(4)\n#define BIT_WMMPS_UAPSD_TID3_8822B BIT(3)\n#define BIT_WMMPS_UAPSD_TID2_8822B BIT(2)\n#define BIT_WMMPS_UAPSD_TID1_8822B BIT(1)\n#define BIT_WMMPS_UAPSD_TID0_8822B BIT(0)\n\n/* 2 REG_PS_RX_INFO_8822B (POWER SAVE RX INFORMATION REGISTER) */\n\n#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B 5\n#define BIT_MASK_PORTSEL__PS_RX_INFO_8822B 0x7\n#define BIT_PORTSEL__PS_RX_INFO_8822B(x)                                       \\\n\t(((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8822B)                            \\\n\t << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B)\n#define BITS_PORTSEL__PS_RX_INFO_8822B                                         \\\n\t(BIT_MASK_PORTSEL__PS_RX_INFO_8822B                                    \\\n\t << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B)\n#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8822B(x)                                 \\\n\t((x) & (~BITS_PORTSEL__PS_RX_INFO_8822B))\n#define BIT_GET_PORTSEL__PS_RX_INFO_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B) &                        \\\n\t BIT_MASK_PORTSEL__PS_RX_INFO_8822B)\n#define BIT_SET_PORTSEL__PS_RX_INFO_8822B(x, v)                                \\\n\t(BIT_CLEAR_PORTSEL__PS_RX_INFO_8822B(x) |                              \\\n\t BIT_PORTSEL__PS_RX_INFO_8822B(v))\n\n#define BIT_RXCTRLIN0_8822B BIT(4)\n#define BIT_RXMGTIN0_8822B BIT(3)\n#define BIT_RXDATAIN2_8822B BIT(2)\n#define BIT_RXDATAIN1_8822B BIT(1)\n#define BIT_RXDATAIN0_8822B BIT(0)\n\n/* 2 REG_NAN_RX_TSF_FILTER_8822B(NAN_RX_TSF_ADDRESS_FILTER) */\n#define BIT_CHK_TSF_TA_8822B BIT(2)\n#define BIT_CHK_TSF_CBSSID_8822B BIT(1)\n#define BIT_CHK_TSF_EN_8822B BIT(0)\n\n/* 2 REG_WOW_CTRL_8822B (WAKE ON WLAN CONTROL REGISTER) */\n\n#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B 6\n#define BIT_MASK_PSF_BSSIDSEL_B2B1_8822B 0x3\n#define BIT_PSF_BSSIDSEL_B2B1_8822B(x)                                         \\\n\t(((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822B)                              \\\n\t << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B)\n#define BITS_PSF_BSSIDSEL_B2B1_8822B                                           \\\n\t(BIT_MASK_PSF_BSSIDSEL_B2B1_8822B << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B)\n#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822B(x)                                   \\\n\t((x) & (~BITS_PSF_BSSIDSEL_B2B1_8822B))\n#define BIT_GET_PSF_BSSIDSEL_B2B1_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B) &                          \\\n\t BIT_MASK_PSF_BSSIDSEL_B2B1_8822B)\n#define BIT_SET_PSF_BSSIDSEL_B2B1_8822B(x, v)                                  \\\n\t(BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822B(x) | BIT_PSF_BSSIDSEL_B2B1_8822B(v))\n\n#define BIT_WOWHCI_8822B BIT(5)\n#define BIT_PSF_BSSIDSEL_B0_8822B BIT(4)\n#define BIT_UWF_8822B BIT(3)\n#define BIT_MAGIC_8822B BIT(2)\n#define BIT_WOWEN_8822B BIT(1)\n#define BIT_FORCE_WAKEUP_8822B BIT(0)\n\n/* 2 REG_LPNAV_CTRL_8822B (LOW POWER NAV CONTROL REGISTER) */\n#define BIT_LPNAV_EN_8822B BIT(31)\n\n#define BIT_SHIFT_LPNAV_EARLY_8822B 16\n#define BIT_MASK_LPNAV_EARLY_8822B 0x7fff\n#define BIT_LPNAV_EARLY_8822B(x)                                               \\\n\t(((x) & BIT_MASK_LPNAV_EARLY_8822B) << BIT_SHIFT_LPNAV_EARLY_8822B)\n#define BITS_LPNAV_EARLY_8822B                                                 \\\n\t(BIT_MASK_LPNAV_EARLY_8822B << BIT_SHIFT_LPNAV_EARLY_8822B)\n#define BIT_CLEAR_LPNAV_EARLY_8822B(x) ((x) & (~BITS_LPNAV_EARLY_8822B))\n#define BIT_GET_LPNAV_EARLY_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_LPNAV_EARLY_8822B) & BIT_MASK_LPNAV_EARLY_8822B)\n#define BIT_SET_LPNAV_EARLY_8822B(x, v)                                        \\\n\t(BIT_CLEAR_LPNAV_EARLY_8822B(x) | BIT_LPNAV_EARLY_8822B(v))\n\n#define BIT_SHIFT_LPNAV_TH_8822B 0\n#define BIT_MASK_LPNAV_TH_8822B 0xffff\n#define BIT_LPNAV_TH_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_LPNAV_TH_8822B) << BIT_SHIFT_LPNAV_TH_8822B)\n#define BITS_LPNAV_TH_8822B                                                    \\\n\t(BIT_MASK_LPNAV_TH_8822B << BIT_SHIFT_LPNAV_TH_8822B)\n#define BIT_CLEAR_LPNAV_TH_8822B(x) ((x) & (~BITS_LPNAV_TH_8822B))\n#define BIT_GET_LPNAV_TH_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_LPNAV_TH_8822B) & BIT_MASK_LPNAV_TH_8822B)\n#define BIT_SET_LPNAV_TH_8822B(x, v)                                           \\\n\t(BIT_CLEAR_LPNAV_TH_8822B(x) | BIT_LPNAV_TH_8822B(v))\n\n/* 2 REG_WKFMCAM_CMD_8822B (WAKEUP FRAME CAM COMMAND REGISTER) */\n#define BIT_WKFCAM_POLLING_V1_8822B BIT(31)\n#define BIT_WKFCAM_CLR_V1_8822B BIT(30)\n#define BIT_WKFCAM_WE_8822B BIT(16)\n\n#define BIT_SHIFT_WKFCAM_ADDR_V2_8822B 8\n#define BIT_MASK_WKFCAM_ADDR_V2_8822B 0xff\n#define BIT_WKFCAM_ADDR_V2_8822B(x)                                            \\\n\t(((x) & BIT_MASK_WKFCAM_ADDR_V2_8822B)                                 \\\n\t << BIT_SHIFT_WKFCAM_ADDR_V2_8822B)\n#define BITS_WKFCAM_ADDR_V2_8822B                                              \\\n\t(BIT_MASK_WKFCAM_ADDR_V2_8822B << BIT_SHIFT_WKFCAM_ADDR_V2_8822B)\n#define BIT_CLEAR_WKFCAM_ADDR_V2_8822B(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8822B))\n#define BIT_GET_WKFCAM_ADDR_V2_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8822B) &                             \\\n\t BIT_MASK_WKFCAM_ADDR_V2_8822B)\n#define BIT_SET_WKFCAM_ADDR_V2_8822B(x, v)                                     \\\n\t(BIT_CLEAR_WKFCAM_ADDR_V2_8822B(x) | BIT_WKFCAM_ADDR_V2_8822B(v))\n\n#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B 0\n#define BIT_MASK_WKFCAM_CAM_NUM_V1_8822B 0xff\n#define BIT_WKFCAM_CAM_NUM_V1_8822B(x)                                         \\\n\t(((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822B)                              \\\n\t << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B)\n#define BITS_WKFCAM_CAM_NUM_V1_8822B                                           \\\n\t(BIT_MASK_WKFCAM_CAM_NUM_V1_8822B << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B)\n#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822B(x)                                   \\\n\t((x) & (~BITS_WKFCAM_CAM_NUM_V1_8822B))\n#define BIT_GET_WKFCAM_CAM_NUM_V1_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B) &                          \\\n\t BIT_MASK_WKFCAM_CAM_NUM_V1_8822B)\n#define BIT_SET_WKFCAM_CAM_NUM_V1_8822B(x, v)                                  \\\n\t(BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822B(x) | BIT_WKFCAM_CAM_NUM_V1_8822B(v))\n\n/* 2 REG_WKFMCAM_RWD_8822B (WAKEUP FRAME READ/WRITE DATA) */\n\n#define BIT_SHIFT_WKFMCAM_RWD_8822B 0\n#define BIT_MASK_WKFMCAM_RWD_8822B 0xffffffffL\n#define BIT_WKFMCAM_RWD_8822B(x)                                               \\\n\t(((x) & BIT_MASK_WKFMCAM_RWD_8822B) << BIT_SHIFT_WKFMCAM_RWD_8822B)\n#define BITS_WKFMCAM_RWD_8822B                                                 \\\n\t(BIT_MASK_WKFMCAM_RWD_8822B << BIT_SHIFT_WKFMCAM_RWD_8822B)\n#define BIT_CLEAR_WKFMCAM_RWD_8822B(x) ((x) & (~BITS_WKFMCAM_RWD_8822B))\n#define BIT_GET_WKFMCAM_RWD_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_WKFMCAM_RWD_8822B) & BIT_MASK_WKFMCAM_RWD_8822B)\n#define BIT_SET_WKFMCAM_RWD_8822B(x, v)                                        \\\n\t(BIT_CLEAR_WKFMCAM_RWD_8822B(x) | BIT_WKFMCAM_RWD_8822B(v))\n\n/* 2 REG_RXFLTMAP1_8822B (RX FILTER MAP GROUP 1) */\n#define BIT_CTRLFLT15EN_8822B BIT(15)\n#define BIT_CTRLFLT14EN_8822B BIT(14)\n#define BIT_CTRLFLT13EN_8822B BIT(13)\n#define BIT_CTRLFLT12EN_8822B BIT(12)\n#define BIT_CTRLFLT11EN_8822B BIT(11)\n#define BIT_CTRLFLT10EN_8822B BIT(10)\n#define BIT_CTRLFLT9EN_8822B BIT(9)\n#define BIT_CTRLFLT8EN_8822B BIT(8)\n#define BIT_CTRLFLT7EN_8822B BIT(7)\n#define BIT_CTRLFLT6EN_8822B BIT(6)\n#define BIT_CTRLFLT5EN_8822B BIT(5)\n#define BIT_CTRLFLT4EN_8822B BIT(4)\n#define BIT_CTRLFLT3EN_8822B BIT(3)\n#define BIT_CTRLFLT2EN_8822B BIT(2)\n#define BIT_CTRLFLT1EN_8822B BIT(1)\n#define BIT_CTRLFLT0EN_8822B BIT(0)\n\n/* 2 REG_RXFLTMAP0_8822B (RX FILTER MAP GROUP 0) */\n#define BIT_MGTFLT15EN_8822B BIT(15)\n#define BIT_MGTFLT14EN_8822B BIT(14)\n#define BIT_MGTFLT13EN_8822B BIT(13)\n#define BIT_MGTFLT12EN_8822B BIT(12)\n#define BIT_MGTFLT11EN_8822B BIT(11)\n#define BIT_MGTFLT10EN_8822B BIT(10)\n#define BIT_MGTFLT9EN_8822B BIT(9)\n#define BIT_MGTFLT8EN_8822B BIT(8)\n#define BIT_MGTFLT7EN_8822B BIT(7)\n#define BIT_MGTFLT6EN_8822B BIT(6)\n#define BIT_MGTFLT5EN_8822B BIT(5)\n#define BIT_MGTFLT4EN_8822B BIT(4)\n#define BIT_MGTFLT3EN_8822B BIT(3)\n#define BIT_MGTFLT2EN_8822B BIT(2)\n#define BIT_MGTFLT1EN_8822B BIT(1)\n#define BIT_MGTFLT0EN_8822B BIT(0)\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_RXFLTMAP2_8822B (RX FILTER MAP GROUP 2) */\n#define BIT_DATAFLT15EN_8822B BIT(15)\n#define BIT_DATAFLT14EN_8822B BIT(14)\n#define BIT_DATAFLT13EN_8822B BIT(13)\n#define BIT_DATAFLT12EN_8822B BIT(12)\n#define BIT_DATAFLT11EN_8822B BIT(11)\n#define BIT_DATAFLT10EN_8822B BIT(10)\n#define BIT_DATAFLT9EN_8822B BIT(9)\n#define BIT_DATAFLT8EN_8822B BIT(8)\n#define BIT_DATAFLT7EN_8822B BIT(7)\n#define BIT_DATAFLT6EN_8822B BIT(6)\n#define BIT_DATAFLT5EN_8822B BIT(5)\n#define BIT_DATAFLT4EN_8822B BIT(4)\n#define BIT_DATAFLT3EN_8822B BIT(3)\n#define BIT_DATAFLT2EN_8822B BIT(2)\n#define BIT_DATAFLT1EN_8822B BIT(1)\n#define BIT_DATAFLT0EN_8822B BIT(0)\n\n/* 2 REG_BCN_PSR_RPT_8822B (BEACON PARSER REPORT REGISTER) */\n\n#define BIT_SHIFT_DTIM_CNT_8822B 24\n#define BIT_MASK_DTIM_CNT_8822B 0xff\n#define BIT_DTIM_CNT_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_DTIM_CNT_8822B) << BIT_SHIFT_DTIM_CNT_8822B)\n#define BITS_DTIM_CNT_8822B                                                    \\\n\t(BIT_MASK_DTIM_CNT_8822B << BIT_SHIFT_DTIM_CNT_8822B)\n#define BIT_CLEAR_DTIM_CNT_8822B(x) ((x) & (~BITS_DTIM_CNT_8822B))\n#define BIT_GET_DTIM_CNT_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT_8822B) & BIT_MASK_DTIM_CNT_8822B)\n#define BIT_SET_DTIM_CNT_8822B(x, v)                                           \\\n\t(BIT_CLEAR_DTIM_CNT_8822B(x) | BIT_DTIM_CNT_8822B(v))\n\n#define BIT_SHIFT_DTIM_PERIOD_8822B 16\n#define BIT_MASK_DTIM_PERIOD_8822B 0xff\n#define BIT_DTIM_PERIOD_8822B(x)                                               \\\n\t(((x) & BIT_MASK_DTIM_PERIOD_8822B) << BIT_SHIFT_DTIM_PERIOD_8822B)\n#define BITS_DTIM_PERIOD_8822B                                                 \\\n\t(BIT_MASK_DTIM_PERIOD_8822B << BIT_SHIFT_DTIM_PERIOD_8822B)\n#define BIT_CLEAR_DTIM_PERIOD_8822B(x) ((x) & (~BITS_DTIM_PERIOD_8822B))\n#define BIT_GET_DTIM_PERIOD_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD_8822B) & BIT_MASK_DTIM_PERIOD_8822B)\n#define BIT_SET_DTIM_PERIOD_8822B(x, v)                                        \\\n\t(BIT_CLEAR_DTIM_PERIOD_8822B(x) | BIT_DTIM_PERIOD_8822B(v))\n\n#define BIT_DTIM_8822B BIT(15)\n#define BIT_TIM_8822B BIT(14)\n\n#define BIT_SHIFT_PS_AID_0_8822B 0\n#define BIT_MASK_PS_AID_0_8822B 0x7ff\n#define BIT_PS_AID_0_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_0_8822B) << BIT_SHIFT_PS_AID_0_8822B)\n#define BITS_PS_AID_0_8822B                                                    \\\n\t(BIT_MASK_PS_AID_0_8822B << BIT_SHIFT_PS_AID_0_8822B)\n#define BIT_CLEAR_PS_AID_0_8822B(x) ((x) & (~BITS_PS_AID_0_8822B))\n#define BIT_GET_PS_AID_0_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_0_8822B) & BIT_MASK_PS_AID_0_8822B)\n#define BIT_SET_PS_AID_0_8822B(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_0_8822B(x) | BIT_PS_AID_0_8822B(v))\n\n/* 2 REG_FLC_TRPC_8822B (TIMER OF FLC_RPC) */\n#define BIT_FLC_RPCT_V1_8822B BIT(7)\n#define BIT_MODE_8822B BIT(6)\n\n#define BIT_SHIFT_TRPCD_8822B 0\n#define BIT_MASK_TRPCD_8822B 0x3f\n#define BIT_TRPCD_8822B(x)                                                     \\\n\t(((x) & BIT_MASK_TRPCD_8822B) << BIT_SHIFT_TRPCD_8822B)\n#define BITS_TRPCD_8822B (BIT_MASK_TRPCD_8822B << BIT_SHIFT_TRPCD_8822B)\n#define BIT_CLEAR_TRPCD_8822B(x) ((x) & (~BITS_TRPCD_8822B))\n#define BIT_GET_TRPCD_8822B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TRPCD_8822B) & BIT_MASK_TRPCD_8822B)\n#define BIT_SET_TRPCD_8822B(x, v)                                              \\\n\t(BIT_CLEAR_TRPCD_8822B(x) | BIT_TRPCD_8822B(v))\n\n/* 2 REG_FLC_PTS_8822B (PKT TYPE SELECTION OF FLC_RPC T) */\n#define BIT_CMF_8822B BIT(2)\n#define BIT_CCF_8822B BIT(1)\n#define BIT_CDF_8822B BIT(0)\n\n/* 2 REG_FLC_RPCT_8822B (FLC_RPC THRESHOLD) */\n\n#define BIT_SHIFT_FLC_RPCT_8822B 0\n#define BIT_MASK_FLC_RPCT_8822B 0xff\n#define BIT_FLC_RPCT_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_FLC_RPCT_8822B) << BIT_SHIFT_FLC_RPCT_8822B)\n#define BITS_FLC_RPCT_8822B                                                    \\\n\t(BIT_MASK_FLC_RPCT_8822B << BIT_SHIFT_FLC_RPCT_8822B)\n#define BIT_CLEAR_FLC_RPCT_8822B(x) ((x) & (~BITS_FLC_RPCT_8822B))\n#define BIT_GET_FLC_RPCT_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_FLC_RPCT_8822B) & BIT_MASK_FLC_RPCT_8822B)\n#define BIT_SET_FLC_RPCT_8822B(x, v)                                           \\\n\t(BIT_CLEAR_FLC_RPCT_8822B(x) | BIT_FLC_RPCT_8822B(v))\n\n/* 2 REG_FLC_RPC_8822B (FW LPS CONDITION -- RX PKT COUNTER) */\n\n#define BIT_SHIFT_FLC_RPC_8822B 0\n#define BIT_MASK_FLC_RPC_8822B 0xff\n#define BIT_FLC_RPC_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_FLC_RPC_8822B) << BIT_SHIFT_FLC_RPC_8822B)\n#define BITS_FLC_RPC_8822B (BIT_MASK_FLC_RPC_8822B << BIT_SHIFT_FLC_RPC_8822B)\n#define BIT_CLEAR_FLC_RPC_8822B(x) ((x) & (~BITS_FLC_RPC_8822B))\n#define BIT_GET_FLC_RPC_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_FLC_RPC_8822B) & BIT_MASK_FLC_RPC_8822B)\n#define BIT_SET_FLC_RPC_8822B(x, v)                                            \\\n\t(BIT_CLEAR_FLC_RPC_8822B(x) | BIT_FLC_RPC_8822B(v))\n\n/* 2 REG_RXPKTMON_CTRL_8822B */\n\n#define BIT_SHIFT_RXBKQPKT_SEQ_8822B 20\n#define BIT_MASK_RXBKQPKT_SEQ_8822B 0xf\n#define BIT_RXBKQPKT_SEQ_8822B(x)                                              \\\n\t(((x) & BIT_MASK_RXBKQPKT_SEQ_8822B) << BIT_SHIFT_RXBKQPKT_SEQ_8822B)\n#define BITS_RXBKQPKT_SEQ_8822B                                                \\\n\t(BIT_MASK_RXBKQPKT_SEQ_8822B << BIT_SHIFT_RXBKQPKT_SEQ_8822B)\n#define BIT_CLEAR_RXBKQPKT_SEQ_8822B(x) ((x) & (~BITS_RXBKQPKT_SEQ_8822B))\n#define BIT_GET_RXBKQPKT_SEQ_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8822B) & BIT_MASK_RXBKQPKT_SEQ_8822B)\n#define BIT_SET_RXBKQPKT_SEQ_8822B(x, v)                                       \\\n\t(BIT_CLEAR_RXBKQPKT_SEQ_8822B(x) | BIT_RXBKQPKT_SEQ_8822B(v))\n\n#define BIT_SHIFT_RXBEQPKT_SEQ_8822B 16\n#define BIT_MASK_RXBEQPKT_SEQ_8822B 0xf\n#define BIT_RXBEQPKT_SEQ_8822B(x)                                              \\\n\t(((x) & BIT_MASK_RXBEQPKT_SEQ_8822B) << BIT_SHIFT_RXBEQPKT_SEQ_8822B)\n#define BITS_RXBEQPKT_SEQ_8822B                                                \\\n\t(BIT_MASK_RXBEQPKT_SEQ_8822B << BIT_SHIFT_RXBEQPKT_SEQ_8822B)\n#define BIT_CLEAR_RXBEQPKT_SEQ_8822B(x) ((x) & (~BITS_RXBEQPKT_SEQ_8822B))\n#define BIT_GET_RXBEQPKT_SEQ_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8822B) & BIT_MASK_RXBEQPKT_SEQ_8822B)\n#define BIT_SET_RXBEQPKT_SEQ_8822B(x, v)                                       \\\n\t(BIT_CLEAR_RXBEQPKT_SEQ_8822B(x) | BIT_RXBEQPKT_SEQ_8822B(v))\n\n#define BIT_SHIFT_RXVIQPKT_SEQ_8822B 12\n#define BIT_MASK_RXVIQPKT_SEQ_8822B 0xf\n#define BIT_RXVIQPKT_SEQ_8822B(x)                                              \\\n\t(((x) & BIT_MASK_RXVIQPKT_SEQ_8822B) << BIT_SHIFT_RXVIQPKT_SEQ_8822B)\n#define BITS_RXVIQPKT_SEQ_8822B                                                \\\n\t(BIT_MASK_RXVIQPKT_SEQ_8822B << BIT_SHIFT_RXVIQPKT_SEQ_8822B)\n#define BIT_CLEAR_RXVIQPKT_SEQ_8822B(x) ((x) & (~BITS_RXVIQPKT_SEQ_8822B))\n#define BIT_GET_RXVIQPKT_SEQ_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8822B) & BIT_MASK_RXVIQPKT_SEQ_8822B)\n#define BIT_SET_RXVIQPKT_SEQ_8822B(x, v)                                       \\\n\t(BIT_CLEAR_RXVIQPKT_SEQ_8822B(x) | BIT_RXVIQPKT_SEQ_8822B(v))\n\n#define BIT_SHIFT_RXVOQPKT_SEQ_8822B 8\n#define BIT_MASK_RXVOQPKT_SEQ_8822B 0xf\n#define BIT_RXVOQPKT_SEQ_8822B(x)                                              \\\n\t(((x) & BIT_MASK_RXVOQPKT_SEQ_8822B) << BIT_SHIFT_RXVOQPKT_SEQ_8822B)\n#define BITS_RXVOQPKT_SEQ_8822B                                                \\\n\t(BIT_MASK_RXVOQPKT_SEQ_8822B << BIT_SHIFT_RXVOQPKT_SEQ_8822B)\n#define BIT_CLEAR_RXVOQPKT_SEQ_8822B(x) ((x) & (~BITS_RXVOQPKT_SEQ_8822B))\n#define BIT_GET_RXVOQPKT_SEQ_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8822B) & BIT_MASK_RXVOQPKT_SEQ_8822B)\n#define BIT_SET_RXVOQPKT_SEQ_8822B(x, v)                                       \\\n\t(BIT_CLEAR_RXVOQPKT_SEQ_8822B(x) | BIT_RXVOQPKT_SEQ_8822B(v))\n\n#define BIT_RXBKQPKT_ERR_8822B BIT(7)\n#define BIT_RXBEQPKT_ERR_8822B BIT(6)\n#define BIT_RXVIQPKT_ERR_8822B BIT(5)\n#define BIT_RXVOQPKT_ERR_8822B BIT(4)\n#define BIT_RXDMA_MON_EN_8822B BIT(2)\n#define BIT_RXPKT_MON_RST_8822B BIT(1)\n#define BIT_RXPKT_MON_EN_8822B BIT(0)\n\n/* 2 REG_STATE_MON_8822B */\n\n#define BIT_SHIFT_STATE_SEL_8822B 24\n#define BIT_MASK_STATE_SEL_8822B 0x1f\n#define BIT_STATE_SEL_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_STATE_SEL_8822B) << BIT_SHIFT_STATE_SEL_8822B)\n#define BITS_STATE_SEL_8822B                                                   \\\n\t(BIT_MASK_STATE_SEL_8822B << BIT_SHIFT_STATE_SEL_8822B)\n#define BIT_CLEAR_STATE_SEL_8822B(x) ((x) & (~BITS_STATE_SEL_8822B))\n#define BIT_GET_STATE_SEL_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_STATE_SEL_8822B) & BIT_MASK_STATE_SEL_8822B)\n#define BIT_SET_STATE_SEL_8822B(x, v)                                          \\\n\t(BIT_CLEAR_STATE_SEL_8822B(x) | BIT_STATE_SEL_8822B(v))\n\n#define BIT_SHIFT_STATE_INFO_8822B 8\n#define BIT_MASK_STATE_INFO_8822B 0xff\n#define BIT_STATE_INFO_8822B(x)                                                \\\n\t(((x) & BIT_MASK_STATE_INFO_8822B) << BIT_SHIFT_STATE_INFO_8822B)\n#define BITS_STATE_INFO_8822B                                                  \\\n\t(BIT_MASK_STATE_INFO_8822B << BIT_SHIFT_STATE_INFO_8822B)\n#define BIT_CLEAR_STATE_INFO_8822B(x) ((x) & (~BITS_STATE_INFO_8822B))\n#define BIT_GET_STATE_INFO_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_STATE_INFO_8822B) & BIT_MASK_STATE_INFO_8822B)\n#define BIT_SET_STATE_INFO_8822B(x, v)                                         \\\n\t(BIT_CLEAR_STATE_INFO_8822B(x) | BIT_STATE_INFO_8822B(v))\n\n#define BIT_UPD_NXT_STATE_8822B BIT(7)\n\n#define BIT_SHIFT_CUR_STATE_8822B 0\n#define BIT_MASK_CUR_STATE_8822B 0x7f\n#define BIT_CUR_STATE_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_CUR_STATE_8822B) << BIT_SHIFT_CUR_STATE_8822B)\n#define BITS_CUR_STATE_8822B                                                   \\\n\t(BIT_MASK_CUR_STATE_8822B << BIT_SHIFT_CUR_STATE_8822B)\n#define BIT_CLEAR_CUR_STATE_8822B(x) ((x) & (~BITS_CUR_STATE_8822B))\n#define BIT_GET_CUR_STATE_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_CUR_STATE_8822B) & BIT_MASK_CUR_STATE_8822B)\n#define BIT_SET_CUR_STATE_8822B(x, v)                                          \\\n\t(BIT_CLEAR_CUR_STATE_8822B(x) | BIT_CUR_STATE_8822B(v))\n\n/* 2 REG_ERROR_MON_8822B */\n#define BIT_MACRX_ERR_1_8822B BIT(17)\n#define BIT_MACRX_ERR_0_8822B BIT(16)\n#define BIT_MACTX_ERR_3_8822B BIT(3)\n#define BIT_MACTX_ERR_2_8822B BIT(2)\n#define BIT_MACTX_ERR_1_8822B BIT(1)\n#define BIT_MACTX_ERR_0_8822B BIT(0)\n\n/* 2 REG_SEARCH_MACID_8822B */\n#define BIT_EN_TXRPTBUF_CLK_8822B BIT(31)\n\n#define BIT_SHIFT_INFO_INDEX_OFFSET_8822B 16\n#define BIT_MASK_INFO_INDEX_OFFSET_8822B 0x1fff\n#define BIT_INFO_INDEX_OFFSET_8822B(x)                                         \\\n\t(((x) & BIT_MASK_INFO_INDEX_OFFSET_8822B)                              \\\n\t << BIT_SHIFT_INFO_INDEX_OFFSET_8822B)\n#define BITS_INFO_INDEX_OFFSET_8822B                                           \\\n\t(BIT_MASK_INFO_INDEX_OFFSET_8822B << BIT_SHIFT_INFO_INDEX_OFFSET_8822B)\n#define BIT_CLEAR_INFO_INDEX_OFFSET_8822B(x)                                   \\\n\t((x) & (~BITS_INFO_INDEX_OFFSET_8822B))\n#define BIT_GET_INFO_INDEX_OFFSET_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8822B) &                          \\\n\t BIT_MASK_INFO_INDEX_OFFSET_8822B)\n#define BIT_SET_INFO_INDEX_OFFSET_8822B(x, v)                                  \\\n\t(BIT_CLEAR_INFO_INDEX_OFFSET_8822B(x) | BIT_INFO_INDEX_OFFSET_8822B(v))\n\n#define BIT_WMAC_SRCH_FIFOFULL_8822B BIT(15)\n#define BIT_DIS_INFOSRCH_8822B BIT(14)\n#define BIT_DISABLE_B0_8822B BIT(13)\n\n#define BIT_SHIFT_INFO_ADDR_OFFSET_8822B 0\n#define BIT_MASK_INFO_ADDR_OFFSET_8822B 0x1fff\n#define BIT_INFO_ADDR_OFFSET_8822B(x)                                          \\\n\t(((x) & BIT_MASK_INFO_ADDR_OFFSET_8822B)                               \\\n\t << BIT_SHIFT_INFO_ADDR_OFFSET_8822B)\n#define BITS_INFO_ADDR_OFFSET_8822B                                            \\\n\t(BIT_MASK_INFO_ADDR_OFFSET_8822B << BIT_SHIFT_INFO_ADDR_OFFSET_8822B)\n#define BIT_CLEAR_INFO_ADDR_OFFSET_8822B(x)                                    \\\n\t((x) & (~BITS_INFO_ADDR_OFFSET_8822B))\n#define BIT_GET_INFO_ADDR_OFFSET_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8822B) &                           \\\n\t BIT_MASK_INFO_ADDR_OFFSET_8822B)\n#define BIT_SET_INFO_ADDR_OFFSET_8822B(x, v)                                   \\\n\t(BIT_CLEAR_INFO_ADDR_OFFSET_8822B(x) | BIT_INFO_ADDR_OFFSET_8822B(v))\n\n/* 2 REG_BT_COEX_TABLE_8822B (BT-COEXISTENCE CONTROL REGISTER) */\n#define BIT_PRI_MASK_RX_RESP_8822B BIT(126)\n#define BIT_PRI_MASK_RXOFDM_8822B BIT(125)\n#define BIT_PRI_MASK_RXCCK_8822B BIT(124)\n\n#define BIT_SHIFT_PRI_MASK_TXAC_8822B (117 & CPU_OPT_WIDTH)\n#define BIT_MASK_PRI_MASK_TXAC_8822B 0x7f\n#define BIT_PRI_MASK_TXAC_8822B(x)                                             \\\n\t(((x) & BIT_MASK_PRI_MASK_TXAC_8822B) << BIT_SHIFT_PRI_MASK_TXAC_8822B)\n#define BITS_PRI_MASK_TXAC_8822B                                               \\\n\t(BIT_MASK_PRI_MASK_TXAC_8822B << BIT_SHIFT_PRI_MASK_TXAC_8822B)\n#define BIT_CLEAR_PRI_MASK_TXAC_8822B(x) ((x) & (~BITS_PRI_MASK_TXAC_8822B))\n#define BIT_GET_PRI_MASK_TXAC_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_TXAC_8822B) & BIT_MASK_PRI_MASK_TXAC_8822B)\n#define BIT_SET_PRI_MASK_TXAC_8822B(x, v)                                      \\\n\t(BIT_CLEAR_PRI_MASK_TXAC_8822B(x) | BIT_PRI_MASK_TXAC_8822B(v))\n\n#define BIT_SHIFT_PRI_MASK_NAV_8822B (109 & CPU_OPT_WIDTH)\n#define BIT_MASK_PRI_MASK_NAV_8822B 0xff\n#define BIT_PRI_MASK_NAV_8822B(x)                                              \\\n\t(((x) & BIT_MASK_PRI_MASK_NAV_8822B) << BIT_SHIFT_PRI_MASK_NAV_8822B)\n#define BITS_PRI_MASK_NAV_8822B                                                \\\n\t(BIT_MASK_PRI_MASK_NAV_8822B << BIT_SHIFT_PRI_MASK_NAV_8822B)\n#define BIT_CLEAR_PRI_MASK_NAV_8822B(x) ((x) & (~BITS_PRI_MASK_NAV_8822B))\n#define BIT_GET_PRI_MASK_NAV_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_NAV_8822B) & BIT_MASK_PRI_MASK_NAV_8822B)\n#define BIT_SET_PRI_MASK_NAV_8822B(x, v)                                       \\\n\t(BIT_CLEAR_PRI_MASK_NAV_8822B(x) | BIT_PRI_MASK_NAV_8822B(v))\n\n#define BIT_PRI_MASK_CCK_8822B BIT(108)\n#define BIT_PRI_MASK_OFDM_8822B BIT(107)\n#define BIT_PRI_MASK_RTY_8822B BIT(106)\n\n#define BIT_SHIFT_PRI_MASK_NUM_8822B (102 & CPU_OPT_WIDTH)\n#define BIT_MASK_PRI_MASK_NUM_8822B 0xf\n#define BIT_PRI_MASK_NUM_8822B(x)                                              \\\n\t(((x) & BIT_MASK_PRI_MASK_NUM_8822B) << BIT_SHIFT_PRI_MASK_NUM_8822B)\n#define BITS_PRI_MASK_NUM_8822B                                                \\\n\t(BIT_MASK_PRI_MASK_NUM_8822B << BIT_SHIFT_PRI_MASK_NUM_8822B)\n#define BIT_CLEAR_PRI_MASK_NUM_8822B(x) ((x) & (~BITS_PRI_MASK_NUM_8822B))\n#define BIT_GET_PRI_MASK_NUM_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_NUM_8822B) & BIT_MASK_PRI_MASK_NUM_8822B)\n#define BIT_SET_PRI_MASK_NUM_8822B(x, v)                                       \\\n\t(BIT_CLEAR_PRI_MASK_NUM_8822B(x) | BIT_PRI_MASK_NUM_8822B(v))\n\n#define BIT_SHIFT_PRI_MASK_TYPE_8822B (98 & CPU_OPT_WIDTH)\n#define BIT_MASK_PRI_MASK_TYPE_8822B 0xf\n#define BIT_PRI_MASK_TYPE_8822B(x)                                             \\\n\t(((x) & BIT_MASK_PRI_MASK_TYPE_8822B) << BIT_SHIFT_PRI_MASK_TYPE_8822B)\n#define BITS_PRI_MASK_TYPE_8822B                                               \\\n\t(BIT_MASK_PRI_MASK_TYPE_8822B << BIT_SHIFT_PRI_MASK_TYPE_8822B)\n#define BIT_CLEAR_PRI_MASK_TYPE_8822B(x) ((x) & (~BITS_PRI_MASK_TYPE_8822B))\n#define BIT_GET_PRI_MASK_TYPE_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_TYPE_8822B) & BIT_MASK_PRI_MASK_TYPE_8822B)\n#define BIT_SET_PRI_MASK_TYPE_8822B(x, v)                                      \\\n\t(BIT_CLEAR_PRI_MASK_TYPE_8822B(x) | BIT_PRI_MASK_TYPE_8822B(v))\n\n#define BIT_OOB_8822B BIT(97)\n#define BIT_ANT_SEL_8822B BIT(96)\n\n#define BIT_SHIFT_BREAK_TABLE_2_8822B (80 & CPU_OPT_WIDTH)\n#define BIT_MASK_BREAK_TABLE_2_8822B 0xffff\n#define BIT_BREAK_TABLE_2_8822B(x)                                             \\\n\t(((x) & BIT_MASK_BREAK_TABLE_2_8822B) << BIT_SHIFT_BREAK_TABLE_2_8822B)\n#define BITS_BREAK_TABLE_2_8822B                                               \\\n\t(BIT_MASK_BREAK_TABLE_2_8822B << BIT_SHIFT_BREAK_TABLE_2_8822B)\n#define BIT_CLEAR_BREAK_TABLE_2_8822B(x) ((x) & (~BITS_BREAK_TABLE_2_8822B))\n#define BIT_GET_BREAK_TABLE_2_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_BREAK_TABLE_2_8822B) & BIT_MASK_BREAK_TABLE_2_8822B)\n#define BIT_SET_BREAK_TABLE_2_8822B(x, v)                                      \\\n\t(BIT_CLEAR_BREAK_TABLE_2_8822B(x) | BIT_BREAK_TABLE_2_8822B(v))\n\n#define BIT_SHIFT_BREAK_TABLE_1_8822B (64 & CPU_OPT_WIDTH)\n#define BIT_MASK_BREAK_TABLE_1_8822B 0xffff\n#define BIT_BREAK_TABLE_1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_BREAK_TABLE_1_8822B) << BIT_SHIFT_BREAK_TABLE_1_8822B)\n#define BITS_BREAK_TABLE_1_8822B                                               \\\n\t(BIT_MASK_BREAK_TABLE_1_8822B << BIT_SHIFT_BREAK_TABLE_1_8822B)\n#define BIT_CLEAR_BREAK_TABLE_1_8822B(x) ((x) & (~BITS_BREAK_TABLE_1_8822B))\n#define BIT_GET_BREAK_TABLE_1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_BREAK_TABLE_1_8822B) & BIT_MASK_BREAK_TABLE_1_8822B)\n#define BIT_SET_BREAK_TABLE_1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_BREAK_TABLE_1_8822B(x) | BIT_BREAK_TABLE_1_8822B(v))\n\n#define BIT_SHIFT_COEX_TABLE_2_8822B (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_COEX_TABLE_2_8822B 0xffffffffL\n#define BIT_COEX_TABLE_2_8822B(x)                                              \\\n\t(((x) & BIT_MASK_COEX_TABLE_2_8822B) << BIT_SHIFT_COEX_TABLE_2_8822B)\n#define BITS_COEX_TABLE_2_8822B                                                \\\n\t(BIT_MASK_COEX_TABLE_2_8822B << BIT_SHIFT_COEX_TABLE_2_8822B)\n#define BIT_CLEAR_COEX_TABLE_2_8822B(x) ((x) & (~BITS_COEX_TABLE_2_8822B))\n#define BIT_GET_COEX_TABLE_2_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_COEX_TABLE_2_8822B) & BIT_MASK_COEX_TABLE_2_8822B)\n#define BIT_SET_COEX_TABLE_2_8822B(x, v)                                       \\\n\t(BIT_CLEAR_COEX_TABLE_2_8822B(x) | BIT_COEX_TABLE_2_8822B(v))\n\n#define BIT_SHIFT_COEX_TABLE_1_8822B 0\n#define BIT_MASK_COEX_TABLE_1_8822B 0xffffffffL\n#define BIT_COEX_TABLE_1_8822B(x)                                              \\\n\t(((x) & BIT_MASK_COEX_TABLE_1_8822B) << BIT_SHIFT_COEX_TABLE_1_8822B)\n#define BITS_COEX_TABLE_1_8822B                                                \\\n\t(BIT_MASK_COEX_TABLE_1_8822B << BIT_SHIFT_COEX_TABLE_1_8822B)\n#define BIT_CLEAR_COEX_TABLE_1_8822B(x) ((x) & (~BITS_COEX_TABLE_1_8822B))\n#define BIT_GET_COEX_TABLE_1_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_COEX_TABLE_1_8822B) & BIT_MASK_COEX_TABLE_1_8822B)\n#define BIT_SET_COEX_TABLE_1_8822B(x, v)                                       \\\n\t(BIT_CLEAR_COEX_TABLE_1_8822B(x) | BIT_COEX_TABLE_1_8822B(v))\n\n/* 2 REG_RXCMD_0_8822B */\n#define BIT_RXCMD_EN_8822B BIT(31)\n\n#define BIT_SHIFT_RXCMD_INFO_8822B 0\n#define BIT_MASK_RXCMD_INFO_8822B 0x7fffffffL\n#define BIT_RXCMD_INFO_8822B(x)                                                \\\n\t(((x) & BIT_MASK_RXCMD_INFO_8822B) << BIT_SHIFT_RXCMD_INFO_8822B)\n#define BITS_RXCMD_INFO_8822B                                                  \\\n\t(BIT_MASK_RXCMD_INFO_8822B << BIT_SHIFT_RXCMD_INFO_8822B)\n#define BIT_CLEAR_RXCMD_INFO_8822B(x) ((x) & (~BITS_RXCMD_INFO_8822B))\n#define BIT_GET_RXCMD_INFO_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXCMD_INFO_8822B) & BIT_MASK_RXCMD_INFO_8822B)\n#define BIT_SET_RXCMD_INFO_8822B(x, v)                                         \\\n\t(BIT_CLEAR_RXCMD_INFO_8822B(x) | BIT_RXCMD_INFO_8822B(v))\n\n/* 2 REG_RXCMD_1_8822B */\n\n#define BIT_SHIFT_RXCMD_PRD_8822B 0\n#define BIT_MASK_RXCMD_PRD_8822B 0xffff\n#define BIT_RXCMD_PRD_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_RXCMD_PRD_8822B) << BIT_SHIFT_RXCMD_PRD_8822B)\n#define BITS_RXCMD_PRD_8822B                                                   \\\n\t(BIT_MASK_RXCMD_PRD_8822B << BIT_SHIFT_RXCMD_PRD_8822B)\n#define BIT_CLEAR_RXCMD_PRD_8822B(x) ((x) & (~BITS_RXCMD_PRD_8822B))\n#define BIT_GET_RXCMD_PRD_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_RXCMD_PRD_8822B) & BIT_MASK_RXCMD_PRD_8822B)\n#define BIT_SET_RXCMD_PRD_8822B(x, v)                                          \\\n\t(BIT_CLEAR_RXCMD_PRD_8822B(x) | BIT_RXCMD_PRD_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_WMAC_RESP_TXINFO_8822B (RESPONSE TXINFO REGISTER) */\n\n#define BIT_SHIFT_WMAC_RESP_MFB_8822B 25\n#define BIT_MASK_WMAC_RESP_MFB_8822B 0x7f\n#define BIT_WMAC_RESP_MFB_8822B(x)                                             \\\n\t(((x) & BIT_MASK_WMAC_RESP_MFB_8822B) << BIT_SHIFT_WMAC_RESP_MFB_8822B)\n#define BITS_WMAC_RESP_MFB_8822B                                               \\\n\t(BIT_MASK_WMAC_RESP_MFB_8822B << BIT_SHIFT_WMAC_RESP_MFB_8822B)\n#define BIT_CLEAR_WMAC_RESP_MFB_8822B(x) ((x) & (~BITS_WMAC_RESP_MFB_8822B))\n#define BIT_GET_WMAC_RESP_MFB_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_MFB_8822B) & BIT_MASK_WMAC_RESP_MFB_8822B)\n#define BIT_SET_WMAC_RESP_MFB_8822B(x, v)                                      \\\n\t(BIT_CLEAR_WMAC_RESP_MFB_8822B(x) | BIT_WMAC_RESP_MFB_8822B(v))\n\n#define BIT_SHIFT_WMAC_ANTINF_SEL_8822B 23\n#define BIT_MASK_WMAC_ANTINF_SEL_8822B 0x3\n#define BIT_WMAC_ANTINF_SEL_8822B(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_ANTINF_SEL_8822B)                                \\\n\t << BIT_SHIFT_WMAC_ANTINF_SEL_8822B)\n#define BITS_WMAC_ANTINF_SEL_8822B                                             \\\n\t(BIT_MASK_WMAC_ANTINF_SEL_8822B << BIT_SHIFT_WMAC_ANTINF_SEL_8822B)\n#define BIT_CLEAR_WMAC_ANTINF_SEL_8822B(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8822B))\n#define BIT_GET_WMAC_ANTINF_SEL_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8822B) &                            \\\n\t BIT_MASK_WMAC_ANTINF_SEL_8822B)\n#define BIT_SET_WMAC_ANTINF_SEL_8822B(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_ANTINF_SEL_8822B(x) | BIT_WMAC_ANTINF_SEL_8822B(v))\n\n#define BIT_SHIFT_WMAC_ANTSEL_SEL_8822B 21\n#define BIT_MASK_WMAC_ANTSEL_SEL_8822B 0x3\n#define BIT_WMAC_ANTSEL_SEL_8822B(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_ANTSEL_SEL_8822B)                                \\\n\t << BIT_SHIFT_WMAC_ANTSEL_SEL_8822B)\n#define BITS_WMAC_ANTSEL_SEL_8822B                                             \\\n\t(BIT_MASK_WMAC_ANTSEL_SEL_8822B << BIT_SHIFT_WMAC_ANTSEL_SEL_8822B)\n#define BIT_CLEAR_WMAC_ANTSEL_SEL_8822B(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8822B))\n#define BIT_GET_WMAC_ANTSEL_SEL_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8822B) &                            \\\n\t BIT_MASK_WMAC_ANTSEL_SEL_8822B)\n#define BIT_SET_WMAC_ANTSEL_SEL_8822B(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_ANTSEL_SEL_8822B(x) | BIT_WMAC_ANTSEL_SEL_8822B(v))\n\n#define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B 18\n#define BIT_MASK_R_WMAC_RESP_TXPOWER_8822B 0x7\n#define BIT_R_WMAC_RESP_TXPOWER_8822B(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8822B)                            \\\n\t << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B)\n#define BITS_R_WMAC_RESP_TXPOWER_8822B                                         \\\n\t(BIT_MASK_R_WMAC_RESP_TXPOWER_8822B                                    \\\n\t << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B)\n#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8822B(x)                                 \\\n\t((x) & (~BITS_R_WMAC_RESP_TXPOWER_8822B))\n#define BIT_GET_R_WMAC_RESP_TXPOWER_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B) &                        \\\n\t BIT_MASK_R_WMAC_RESP_TXPOWER_8822B)\n#define BIT_SET_R_WMAC_RESP_TXPOWER_8822B(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_RESP_TXPOWER_8822B(x) |                              \\\n\t BIT_R_WMAC_RESP_TXPOWER_8822B(v))\n\n#define BIT_SHIFT_WMAC_RESP_TXANT_8822B 0\n#define BIT_MASK_WMAC_RESP_TXANT_8822B 0x3ffff\n#define BIT_WMAC_RESP_TXANT_8822B(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_RESP_TXANT_8822B)                                \\\n\t << BIT_SHIFT_WMAC_RESP_TXANT_8822B)\n#define BITS_WMAC_RESP_TXANT_8822B                                             \\\n\t(BIT_MASK_WMAC_RESP_TXANT_8822B << BIT_SHIFT_WMAC_RESP_TXANT_8822B)\n#define BIT_CLEAR_WMAC_RESP_TXANT_8822B(x) ((x) & (~BITS_WMAC_RESP_TXANT_8822B))\n#define BIT_GET_WMAC_RESP_TXANT_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8822B) &                            \\\n\t BIT_MASK_WMAC_RESP_TXANT_8822B)\n#define BIT_SET_WMAC_RESP_TXANT_8822B(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_RESP_TXANT_8822B(x) | BIT_WMAC_RESP_TXANT_8822B(v))\n\n/* 2 REG_BBPSF_CTRL_8822B */\n#define BIT_CTL_IDLE_CLR_CSI_RPT_8822B BIT(31)\n#define BIT_WMAC_USE_NDPARATE_8822B BIT(30)\n\n#define BIT_SHIFT_WMAC_CSI_RATE_8822B 24\n#define BIT_MASK_WMAC_CSI_RATE_8822B 0x3f\n#define BIT_WMAC_CSI_RATE_8822B(x)                                             \\\n\t(((x) & BIT_MASK_WMAC_CSI_RATE_8822B) << BIT_SHIFT_WMAC_CSI_RATE_8822B)\n#define BITS_WMAC_CSI_RATE_8822B                                               \\\n\t(BIT_MASK_WMAC_CSI_RATE_8822B << BIT_SHIFT_WMAC_CSI_RATE_8822B)\n#define BIT_CLEAR_WMAC_CSI_RATE_8822B(x) ((x) & (~BITS_WMAC_CSI_RATE_8822B))\n#define BIT_GET_WMAC_CSI_RATE_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_WMAC_CSI_RATE_8822B) & BIT_MASK_WMAC_CSI_RATE_8822B)\n#define BIT_SET_WMAC_CSI_RATE_8822B(x, v)                                      \\\n\t(BIT_CLEAR_WMAC_CSI_RATE_8822B(x) | BIT_WMAC_CSI_RATE_8822B(v))\n\n#define BIT_SHIFT_WMAC_RESP_TXRATE_8822B 16\n#define BIT_MASK_WMAC_RESP_TXRATE_8822B 0xff\n#define BIT_WMAC_RESP_TXRATE_8822B(x)                                          \\\n\t(((x) & BIT_MASK_WMAC_RESP_TXRATE_8822B)                               \\\n\t << BIT_SHIFT_WMAC_RESP_TXRATE_8822B)\n#define BITS_WMAC_RESP_TXRATE_8822B                                            \\\n\t(BIT_MASK_WMAC_RESP_TXRATE_8822B << BIT_SHIFT_WMAC_RESP_TXRATE_8822B)\n#define BIT_CLEAR_WMAC_RESP_TXRATE_8822B(x)                                    \\\n\t((x) & (~BITS_WMAC_RESP_TXRATE_8822B))\n#define BIT_GET_WMAC_RESP_TXRATE_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8822B) &                           \\\n\t BIT_MASK_WMAC_RESP_TXRATE_8822B)\n#define BIT_SET_WMAC_RESP_TXRATE_8822B(x, v)                                   \\\n\t(BIT_CLEAR_WMAC_RESP_TXRATE_8822B(x) | BIT_WMAC_RESP_TXRATE_8822B(v))\n\n#define BIT_BBPSF_MPDUCHKEN_8822B BIT(5)\n#define BIT_BBPSF_MHCHKEN_8822B BIT(4)\n#define BIT_BBPSF_ERRCHKEN_8822B BIT(3)\n\n#define BIT_SHIFT_BBPSF_ERRTHR_8822B 0\n#define BIT_MASK_BBPSF_ERRTHR_8822B 0x7\n#define BIT_BBPSF_ERRTHR_8822B(x)                                              \\\n\t(((x) & BIT_MASK_BBPSF_ERRTHR_8822B) << BIT_SHIFT_BBPSF_ERRTHR_8822B)\n#define BITS_BBPSF_ERRTHR_8822B                                                \\\n\t(BIT_MASK_BBPSF_ERRTHR_8822B << BIT_SHIFT_BBPSF_ERRTHR_8822B)\n#define BIT_CLEAR_BBPSF_ERRTHR_8822B(x) ((x) & (~BITS_BBPSF_ERRTHR_8822B))\n#define BIT_GET_BBPSF_ERRTHR_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_BBPSF_ERRTHR_8822B) & BIT_MASK_BBPSF_ERRTHR_8822B)\n#define BIT_SET_BBPSF_ERRTHR_8822B(x, v)                                       \\\n\t(BIT_CLEAR_BBPSF_ERRTHR_8822B(x) | BIT_BBPSF_ERRTHR_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_P2P_RX_BCN_NOA_8822B (P2P RX BEACON NOA REGISTER) */\n#define BIT_NOA_PARSER_EN_8822B BIT(15)\n#define BIT_BSSID_SEL_8822B BIT(14)\n\n#define BIT_SHIFT_P2P_OUI_TYPE_8822B 0\n#define BIT_MASK_P2P_OUI_TYPE_8822B 0xff\n#define BIT_P2P_OUI_TYPE_8822B(x)                                              \\\n\t(((x) & BIT_MASK_P2P_OUI_TYPE_8822B) << BIT_SHIFT_P2P_OUI_TYPE_8822B)\n#define BITS_P2P_OUI_TYPE_8822B                                                \\\n\t(BIT_MASK_P2P_OUI_TYPE_8822B << BIT_SHIFT_P2P_OUI_TYPE_8822B)\n#define BIT_CLEAR_P2P_OUI_TYPE_8822B(x) ((x) & (~BITS_P2P_OUI_TYPE_8822B))\n#define BIT_GET_P2P_OUI_TYPE_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_P2P_OUI_TYPE_8822B) & BIT_MASK_P2P_OUI_TYPE_8822B)\n#define BIT_SET_P2P_OUI_TYPE_8822B(x, v)                                       \\\n\t(BIT_CLEAR_P2P_OUI_TYPE_8822B(x) | BIT_P2P_OUI_TYPE_8822B(v))\n\n/* 2 REG_ASSOCIATED_BFMER0_INFO_8822B (ASSOCIATED BEAMFORMER0 INFO REGISTER) */\n\n#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B (48 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_WMAC_TXCSI_AID0_8822B 0x1ff\n#define BIT_R_WMAC_TXCSI_AID0_8822B(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8822B)                              \\\n\t << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B)\n#define BITS_R_WMAC_TXCSI_AID0_8822B                                           \\\n\t(BIT_MASK_R_WMAC_TXCSI_AID0_8822B << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B)\n#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8822B(x)                                   \\\n\t((x) & (~BITS_R_WMAC_TXCSI_AID0_8822B))\n#define BIT_GET_R_WMAC_TXCSI_AID0_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B) &                          \\\n\t BIT_MASK_R_WMAC_TXCSI_AID0_8822B)\n#define BIT_SET_R_WMAC_TXCSI_AID0_8822B(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_TXCSI_AID0_8822B(x) | BIT_R_WMAC_TXCSI_AID0_8822B(v))\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B 0xffffffffffffL\n#define BIT_R_WMAC_SOUNDING_RXADD_R0_8822B(x)                                  \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B)                       \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B)\n#define BITS_R_WMAC_SOUNDING_RXADD_R0_8822B                                    \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B                               \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8822B(x)                            \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_8822B))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8822B(x)                              \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B) &                   \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_8822B(x, v)                           \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8822B(x) |                         \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R0_8822B(v))\n\n/* 2 REG_ASSOCIATED_BFMER1_INFO_8822B (ASSOCIATED BEAMFORMER1 INFO REGISTER) */\n\n#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B (48 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_WMAC_TXCSI_AID1_8822B 0x1ff\n#define BIT_R_WMAC_TXCSI_AID1_8822B(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8822B)                              \\\n\t << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B)\n#define BITS_R_WMAC_TXCSI_AID1_8822B                                           \\\n\t(BIT_MASK_R_WMAC_TXCSI_AID1_8822B << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B)\n#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8822B(x)                                   \\\n\t((x) & (~BITS_R_WMAC_TXCSI_AID1_8822B))\n#define BIT_GET_R_WMAC_TXCSI_AID1_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B) &                          \\\n\t BIT_MASK_R_WMAC_TXCSI_AID1_8822B)\n#define BIT_SET_R_WMAC_TXCSI_AID1_8822B(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_TXCSI_AID1_8822B(x) | BIT_R_WMAC_TXCSI_AID1_8822B(v))\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B 0xffffffffffffL\n#define BIT_R_WMAC_SOUNDING_RXADD_R1_8822B(x)                                  \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B)                       \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B)\n#define BITS_R_WMAC_SOUNDING_RXADD_R1_8822B                                    \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B                               \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8822B(x)                            \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_8822B))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8822B(x)                              \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B) &                   \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_8822B(x, v)                           \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8822B(x) |                         \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R1_8822B(v))\n\n/* 2 REG_TX_CSI_RPT_PARAM_BW20_8822B (TX CSI REPORT PARAMETER REGISTER) */\n\n#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B 16\n#define BIT_MASK_R_WMAC_BFINFO_20M_1_8822B 0xfff\n#define BIT_R_WMAC_BFINFO_20M_1_8822B(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822B)                            \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B)\n#define BITS_R_WMAC_BFINFO_20M_1_8822B                                         \\\n\t(BIT_MASK_R_WMAC_BFINFO_20M_1_8822B                                    \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B)\n#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822B(x)                                 \\\n\t((x) & (~BITS_R_WMAC_BFINFO_20M_1_8822B))\n#define BIT_GET_R_WMAC_BFINFO_20M_1_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B) &                        \\\n\t BIT_MASK_R_WMAC_BFINFO_20M_1_8822B)\n#define BIT_SET_R_WMAC_BFINFO_20M_1_8822B(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822B(x) |                              \\\n\t BIT_R_WMAC_BFINFO_20M_1_8822B(v))\n\n#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B 0\n#define BIT_MASK_R_WMAC_BFINFO_20M_0_8822B 0xfff\n#define BIT_R_WMAC_BFINFO_20M_0_8822B(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822B)                            \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B)\n#define BITS_R_WMAC_BFINFO_20M_0_8822B                                         \\\n\t(BIT_MASK_R_WMAC_BFINFO_20M_0_8822B                                    \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B)\n#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822B(x)                                 \\\n\t((x) & (~BITS_R_WMAC_BFINFO_20M_0_8822B))\n#define BIT_GET_R_WMAC_BFINFO_20M_0_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B) &                        \\\n\t BIT_MASK_R_WMAC_BFINFO_20M_0_8822B)\n#define BIT_SET_R_WMAC_BFINFO_20M_0_8822B(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822B(x) |                              \\\n\t BIT_R_WMAC_BFINFO_20M_0_8822B(v))\n\n/* 2 REG_TX_CSI_RPT_PARAM_BW40_8822B (TX CSI REPORT PARAMETER_BW40 REGISTER) */\n\n#define BIT_SHIFT_WMAC_RESP_ANTCD_8822B 0\n#define BIT_MASK_WMAC_RESP_ANTCD_8822B 0xf\n#define BIT_WMAC_RESP_ANTCD_8822B(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_RESP_ANTCD_8822B)                                \\\n\t << BIT_SHIFT_WMAC_RESP_ANTCD_8822B)\n#define BITS_WMAC_RESP_ANTCD_8822B                                             \\\n\t(BIT_MASK_WMAC_RESP_ANTCD_8822B << BIT_SHIFT_WMAC_RESP_ANTCD_8822B)\n#define BIT_CLEAR_WMAC_RESP_ANTCD_8822B(x) ((x) & (~BITS_WMAC_RESP_ANTCD_8822B))\n#define BIT_GET_WMAC_RESP_ANTCD_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8822B) &                            \\\n\t BIT_MASK_WMAC_RESP_ANTCD_8822B)\n#define BIT_SET_WMAC_RESP_ANTCD_8822B(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_RESP_ANTCD_8822B(x) | BIT_WMAC_RESP_ANTCD_8822B(v))\n\n/* 2 REG_TX_CSI_RPT_PARAM_BW80_8822B (TX CSI REPORT PARAMETER_BW80 REGISTER) */\n\n/* 2 REG_BCN_PSR_RPT2_8822B (BEACON PARSER REPORT REGISTER2) */\n\n#define BIT_SHIFT_DTIM_CNT2_8822B 24\n#define BIT_MASK_DTIM_CNT2_8822B 0xff\n#define BIT_DTIM_CNT2_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT2_8822B) << BIT_SHIFT_DTIM_CNT2_8822B)\n#define BITS_DTIM_CNT2_8822B                                                   \\\n\t(BIT_MASK_DTIM_CNT2_8822B << BIT_SHIFT_DTIM_CNT2_8822B)\n#define BIT_CLEAR_DTIM_CNT2_8822B(x) ((x) & (~BITS_DTIM_CNT2_8822B))\n#define BIT_GET_DTIM_CNT2_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT2_8822B) & BIT_MASK_DTIM_CNT2_8822B)\n#define BIT_SET_DTIM_CNT2_8822B(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT2_8822B(x) | BIT_DTIM_CNT2_8822B(v))\n\n#define BIT_SHIFT_DTIM_PERIOD2_8822B 16\n#define BIT_MASK_DTIM_PERIOD2_8822B 0xff\n#define BIT_DTIM_PERIOD2_8822B(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD2_8822B) << BIT_SHIFT_DTIM_PERIOD2_8822B)\n#define BITS_DTIM_PERIOD2_8822B                                                \\\n\t(BIT_MASK_DTIM_PERIOD2_8822B << BIT_SHIFT_DTIM_PERIOD2_8822B)\n#define BIT_CLEAR_DTIM_PERIOD2_8822B(x) ((x) & (~BITS_DTIM_PERIOD2_8822B))\n#define BIT_GET_DTIM_PERIOD2_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD2_8822B) & BIT_MASK_DTIM_PERIOD2_8822B)\n#define BIT_SET_DTIM_PERIOD2_8822B(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD2_8822B(x) | BIT_DTIM_PERIOD2_8822B(v))\n\n#define BIT_DTIM2_8822B BIT(15)\n#define BIT_TIM2_8822B BIT(14)\n\n#define BIT_SHIFT_PS_AID_2_8822B 0\n#define BIT_MASK_PS_AID_2_8822B 0x7ff\n#define BIT_PS_AID_2_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_2_8822B) << BIT_SHIFT_PS_AID_2_8822B)\n#define BITS_PS_AID_2_8822B                                                    \\\n\t(BIT_MASK_PS_AID_2_8822B << BIT_SHIFT_PS_AID_2_8822B)\n#define BIT_CLEAR_PS_AID_2_8822B(x) ((x) & (~BITS_PS_AID_2_8822B))\n#define BIT_GET_PS_AID_2_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_2_8822B) & BIT_MASK_PS_AID_2_8822B)\n#define BIT_SET_PS_AID_2_8822B(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_2_8822B(x) | BIT_PS_AID_2_8822B(v))\n\n/* 2 REG_BCN_PSR_RPT3_8822B (BEACON PARSER REPORT REGISTER3) */\n\n#define BIT_SHIFT_DTIM_CNT3_8822B 24\n#define BIT_MASK_DTIM_CNT3_8822B 0xff\n#define BIT_DTIM_CNT3_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT3_8822B) << BIT_SHIFT_DTIM_CNT3_8822B)\n#define BITS_DTIM_CNT3_8822B                                                   \\\n\t(BIT_MASK_DTIM_CNT3_8822B << BIT_SHIFT_DTIM_CNT3_8822B)\n#define BIT_CLEAR_DTIM_CNT3_8822B(x) ((x) & (~BITS_DTIM_CNT3_8822B))\n#define BIT_GET_DTIM_CNT3_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT3_8822B) & BIT_MASK_DTIM_CNT3_8822B)\n#define BIT_SET_DTIM_CNT3_8822B(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT3_8822B(x) | BIT_DTIM_CNT3_8822B(v))\n\n#define BIT_SHIFT_DTIM_PERIOD3_8822B 16\n#define BIT_MASK_DTIM_PERIOD3_8822B 0xff\n#define BIT_DTIM_PERIOD3_8822B(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD3_8822B) << BIT_SHIFT_DTIM_PERIOD3_8822B)\n#define BITS_DTIM_PERIOD3_8822B                                                \\\n\t(BIT_MASK_DTIM_PERIOD3_8822B << BIT_SHIFT_DTIM_PERIOD3_8822B)\n#define BIT_CLEAR_DTIM_PERIOD3_8822B(x) ((x) & (~BITS_DTIM_PERIOD3_8822B))\n#define BIT_GET_DTIM_PERIOD3_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD3_8822B) & BIT_MASK_DTIM_PERIOD3_8822B)\n#define BIT_SET_DTIM_PERIOD3_8822B(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD3_8822B(x) | BIT_DTIM_PERIOD3_8822B(v))\n\n#define BIT_DTIM3_8822B BIT(15)\n#define BIT_TIM3_8822B BIT(14)\n\n#define BIT_SHIFT_PS_AID_3_8822B 0\n#define BIT_MASK_PS_AID_3_8822B 0x7ff\n#define BIT_PS_AID_3_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_3_8822B) << BIT_SHIFT_PS_AID_3_8822B)\n#define BITS_PS_AID_3_8822B                                                    \\\n\t(BIT_MASK_PS_AID_3_8822B << BIT_SHIFT_PS_AID_3_8822B)\n#define BIT_CLEAR_PS_AID_3_8822B(x) ((x) & (~BITS_PS_AID_3_8822B))\n#define BIT_GET_PS_AID_3_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_3_8822B) & BIT_MASK_PS_AID_3_8822B)\n#define BIT_SET_PS_AID_3_8822B(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_3_8822B(x) | BIT_PS_AID_3_8822B(v))\n\n/* 2 REG_BCN_PSR_RPT4_8822B (BEACON PARSER REPORT REGISTER4) */\n\n#define BIT_SHIFT_DTIM_CNT4_8822B 24\n#define BIT_MASK_DTIM_CNT4_8822B 0xff\n#define BIT_DTIM_CNT4_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT4_8822B) << BIT_SHIFT_DTIM_CNT4_8822B)\n#define BITS_DTIM_CNT4_8822B                                                   \\\n\t(BIT_MASK_DTIM_CNT4_8822B << BIT_SHIFT_DTIM_CNT4_8822B)\n#define BIT_CLEAR_DTIM_CNT4_8822B(x) ((x) & (~BITS_DTIM_CNT4_8822B))\n#define BIT_GET_DTIM_CNT4_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT4_8822B) & BIT_MASK_DTIM_CNT4_8822B)\n#define BIT_SET_DTIM_CNT4_8822B(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT4_8822B(x) | BIT_DTIM_CNT4_8822B(v))\n\n#define BIT_SHIFT_DTIM_PERIOD4_8822B 16\n#define BIT_MASK_DTIM_PERIOD4_8822B 0xff\n#define BIT_DTIM_PERIOD4_8822B(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD4_8822B) << BIT_SHIFT_DTIM_PERIOD4_8822B)\n#define BITS_DTIM_PERIOD4_8822B                                                \\\n\t(BIT_MASK_DTIM_PERIOD4_8822B << BIT_SHIFT_DTIM_PERIOD4_8822B)\n#define BIT_CLEAR_DTIM_PERIOD4_8822B(x) ((x) & (~BITS_DTIM_PERIOD4_8822B))\n#define BIT_GET_DTIM_PERIOD4_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD4_8822B) & BIT_MASK_DTIM_PERIOD4_8822B)\n#define BIT_SET_DTIM_PERIOD4_8822B(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD4_8822B(x) | BIT_DTIM_PERIOD4_8822B(v))\n\n#define BIT_DTIM4_8822B BIT(15)\n#define BIT_TIM4_8822B BIT(14)\n\n#define BIT_SHIFT_PS_AID_4_8822B 0\n#define BIT_MASK_PS_AID_4_8822B 0x7ff\n#define BIT_PS_AID_4_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_4_8822B) << BIT_SHIFT_PS_AID_4_8822B)\n#define BITS_PS_AID_4_8822B                                                    \\\n\t(BIT_MASK_PS_AID_4_8822B << BIT_SHIFT_PS_AID_4_8822B)\n#define BIT_CLEAR_PS_AID_4_8822B(x) ((x) & (~BITS_PS_AID_4_8822B))\n#define BIT_GET_PS_AID_4_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_4_8822B) & BIT_MASK_PS_AID_4_8822B)\n#define BIT_SET_PS_AID_4_8822B(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_4_8822B(x) | BIT_PS_AID_4_8822B(v))\n\n/* 2 REG_A1_ADDR_MASK_8822B (A1 ADDR MASK REGISTER) */\n\n#define BIT_SHIFT_A1_ADDR_MASK_8822B 0\n#define BIT_MASK_A1_ADDR_MASK_8822B 0xffffffffL\n#define BIT_A1_ADDR_MASK_8822B(x)                                              \\\n\t(((x) & BIT_MASK_A1_ADDR_MASK_8822B) << BIT_SHIFT_A1_ADDR_MASK_8822B)\n#define BITS_A1_ADDR_MASK_8822B                                                \\\n\t(BIT_MASK_A1_ADDR_MASK_8822B << BIT_SHIFT_A1_ADDR_MASK_8822B)\n#define BIT_CLEAR_A1_ADDR_MASK_8822B(x) ((x) & (~BITS_A1_ADDR_MASK_8822B))\n#define BIT_GET_A1_ADDR_MASK_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_A1_ADDR_MASK_8822B) & BIT_MASK_A1_ADDR_MASK_8822B)\n#define BIT_SET_A1_ADDR_MASK_8822B(x, v)                                       \\\n\t(BIT_CLEAR_A1_ADDR_MASK_8822B(x) | BIT_A1_ADDR_MASK_8822B(v))\n\n/* 2 REG_MACID2_8822B (MAC ID2 REGISTER) */\n\n#define BIT_SHIFT_MACID2_8822B 0\n#define BIT_MASK_MACID2_8822B 0xffffffffffffL\n#define BIT_MACID2_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_MACID2_8822B) << BIT_SHIFT_MACID2_8822B)\n#define BITS_MACID2_8822B (BIT_MASK_MACID2_8822B << BIT_SHIFT_MACID2_8822B)\n#define BIT_CLEAR_MACID2_8822B(x) ((x) & (~BITS_MACID2_8822B))\n#define BIT_GET_MACID2_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_MACID2_8822B) & BIT_MASK_MACID2_8822B)\n#define BIT_SET_MACID2_8822B(x, v)                                             \\\n\t(BIT_CLEAR_MACID2_8822B(x) | BIT_MACID2_8822B(v))\n\n/* 2 REG_BSSID2_8822B (BSSID2 REGISTER) */\n\n#define BIT_SHIFT_BSSID2_8822B 0\n#define BIT_MASK_BSSID2_8822B 0xffffffffffffL\n#define BIT_BSSID2_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_BSSID2_8822B) << BIT_SHIFT_BSSID2_8822B)\n#define BITS_BSSID2_8822B (BIT_MASK_BSSID2_8822B << BIT_SHIFT_BSSID2_8822B)\n#define BIT_CLEAR_BSSID2_8822B(x) ((x) & (~BITS_BSSID2_8822B))\n#define BIT_GET_BSSID2_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_BSSID2_8822B) & BIT_MASK_BSSID2_8822B)\n#define BIT_SET_BSSID2_8822B(x, v)                                             \\\n\t(BIT_CLEAR_BSSID2_8822B(x) | BIT_BSSID2_8822B(v))\n\n/* 2 REG_MACID3_8822B (MAC ID3 REGISTER) */\n\n#define BIT_SHIFT_MACID3_8822B 0\n#define BIT_MASK_MACID3_8822B 0xffffffffffffL\n#define BIT_MACID3_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_MACID3_8822B) << BIT_SHIFT_MACID3_8822B)\n#define BITS_MACID3_8822B (BIT_MASK_MACID3_8822B << BIT_SHIFT_MACID3_8822B)\n#define BIT_CLEAR_MACID3_8822B(x) ((x) & (~BITS_MACID3_8822B))\n#define BIT_GET_MACID3_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_MACID3_8822B) & BIT_MASK_MACID3_8822B)\n#define BIT_SET_MACID3_8822B(x, v)                                             \\\n\t(BIT_CLEAR_MACID3_8822B(x) | BIT_MACID3_8822B(v))\n\n/* 2 REG_BSSID3_8822B (BSSID3 REGISTER) */\n\n#define BIT_SHIFT_BSSID3_8822B 0\n#define BIT_MASK_BSSID3_8822B 0xffffffffffffL\n#define BIT_BSSID3_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_BSSID3_8822B) << BIT_SHIFT_BSSID3_8822B)\n#define BITS_BSSID3_8822B (BIT_MASK_BSSID3_8822B << BIT_SHIFT_BSSID3_8822B)\n#define BIT_CLEAR_BSSID3_8822B(x) ((x) & (~BITS_BSSID3_8822B))\n#define BIT_GET_BSSID3_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_BSSID3_8822B) & BIT_MASK_BSSID3_8822B)\n#define BIT_SET_BSSID3_8822B(x, v)                                             \\\n\t(BIT_CLEAR_BSSID3_8822B(x) | BIT_BSSID3_8822B(v))\n\n/* 2 REG_MACID4_8822B (MAC ID4 REGISTER) */\n\n#define BIT_SHIFT_MACID4_8822B 0\n#define BIT_MASK_MACID4_8822B 0xffffffffffffL\n#define BIT_MACID4_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_MACID4_8822B) << BIT_SHIFT_MACID4_8822B)\n#define BITS_MACID4_8822B (BIT_MASK_MACID4_8822B << BIT_SHIFT_MACID4_8822B)\n#define BIT_CLEAR_MACID4_8822B(x) ((x) & (~BITS_MACID4_8822B))\n#define BIT_GET_MACID4_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_MACID4_8822B) & BIT_MASK_MACID4_8822B)\n#define BIT_SET_MACID4_8822B(x, v)                                             \\\n\t(BIT_CLEAR_MACID4_8822B(x) | BIT_MACID4_8822B(v))\n\n/* 2 REG_BSSID4_8822B (BSSID4 REGISTER) */\n\n#define BIT_SHIFT_BSSID4_8822B 0\n#define BIT_MASK_BSSID4_8822B 0xffffffffffffL\n#define BIT_BSSID4_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_BSSID4_8822B) << BIT_SHIFT_BSSID4_8822B)\n#define BITS_BSSID4_8822B (BIT_MASK_BSSID4_8822B << BIT_SHIFT_BSSID4_8822B)\n#define BIT_CLEAR_BSSID4_8822B(x) ((x) & (~BITS_BSSID4_8822B))\n#define BIT_GET_BSSID4_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_BSSID4_8822B) & BIT_MASK_BSSID4_8822B)\n#define BIT_SET_BSSID4_8822B(x, v)                                             \\\n\t(BIT_CLEAR_BSSID4_8822B(x) | BIT_BSSID4_8822B(v))\n\n/* 2 REG_NOA_REPORT_8822B */\n\n/* 2 REG_PWRBIT_SETTING_8822B */\n#define BIT_CLI3_PWRBIT_OW_EN_8822B BIT(7)\n#define BIT_CLI3_PWR_ST_8822B BIT(6)\n#define BIT_CLI2_PWRBIT_OW_EN_8822B BIT(5)\n#define BIT_CLI2_PWR_ST_8822B BIT(4)\n#define BIT_CLI1_PWRBIT_OW_EN_8822B BIT(3)\n#define BIT_CLI1_PWR_ST_8822B BIT(2)\n#define BIT_CLI0_PWRBIT_OW_EN_8822B BIT(1)\n#define BIT_CLI0_PWR_ST_8822B BIT(0)\n\n/* 2 REG_WMAC_MU_BF_OPTION_8822B */\n#define BIT_WMAC_RESP_NONSTA1_DIS_8822B BIT(7)\n#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN_8822B BIT(6)\n\n#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B 4\n#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B 0x3\n#define BIT_WMAC_TXMU_ACKPOLICY_8822B(x)                                       \\\n\t(((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B)                            \\\n\t << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B)\n#define BITS_WMAC_TXMU_ACKPOLICY_8822B                                         \\\n\t(BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B                                    \\\n\t << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B)\n#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822B(x)                                 \\\n\t((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8822B))\n#define BIT_GET_WMAC_TXMU_ACKPOLICY_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B) &                        \\\n\t BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B)\n#define BIT_SET_WMAC_TXMU_ACKPOLICY_8822B(x, v)                                \\\n\t(BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822B(x) |                              \\\n\t BIT_WMAC_TXMU_ACKPOLICY_8822B(v))\n\n#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B 1\n#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B 0x7\n#define BIT_WMAC_MU_BFEE_PORT_SEL_8822B(x)                                     \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B)                          \\\n\t << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B)\n#define BITS_WMAC_MU_BFEE_PORT_SEL_8822B                                       \\\n\t(BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B                                  \\\n\t << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B)\n#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822B(x)                               \\\n\t((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8822B))\n#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8822B(x)                                 \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B) &                      \\\n\t BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B)\n#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8822B(x, v)                              \\\n\t(BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822B(x) |                            \\\n\t BIT_WMAC_MU_BFEE_PORT_SEL_8822B(v))\n\n#define BIT_WMAC_MU_BFEE_DIS_8822B BIT(0)\n\n/* 2 REG_NOT_VALID_8822B */\n\n#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B 0\n#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B 0xff\n#define BIT_WMAC_PAUSE_BB_CLR_TH_8822B(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B)                           \\\n\t << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B)\n#define BITS_WMAC_PAUSE_BB_CLR_TH_8822B                                        \\\n\t(BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B                                   \\\n\t << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B)\n#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822B(x)                                \\\n\t((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8822B))\n#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B) &                       \\\n\t BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B)\n#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8822B(x, v)                               \\\n\t(BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822B(x) |                             \\\n\t BIT_WMAC_PAUSE_BB_CLR_TH_8822B(v))\n\n/* 2 REG_WMAC_MU_ARB_8822B */\n#define BIT_WMAC_ARB_HW_ADAPT_EN_8822B BIT(7)\n#define BIT_WMAC_ARB_SW_EN_8822B BIT(6)\n\n#define BIT_SHIFT_WMAC_ARB_SW_STATE_8822B 0\n#define BIT_MASK_WMAC_ARB_SW_STATE_8822B 0x3f\n#define BIT_WMAC_ARB_SW_STATE_8822B(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_ARB_SW_STATE_8822B)                              \\\n\t << BIT_SHIFT_WMAC_ARB_SW_STATE_8822B)\n#define BITS_WMAC_ARB_SW_STATE_8822B                                           \\\n\t(BIT_MASK_WMAC_ARB_SW_STATE_8822B << BIT_SHIFT_WMAC_ARB_SW_STATE_8822B)\n#define BIT_CLEAR_WMAC_ARB_SW_STATE_8822B(x)                                   \\\n\t((x) & (~BITS_WMAC_ARB_SW_STATE_8822B))\n#define BIT_GET_WMAC_ARB_SW_STATE_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8822B) &                          \\\n\t BIT_MASK_WMAC_ARB_SW_STATE_8822B)\n#define BIT_SET_WMAC_ARB_SW_STATE_8822B(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_ARB_SW_STATE_8822B(x) | BIT_WMAC_ARB_SW_STATE_8822B(v))\n\n/* 2 REG_WMAC_MU_OPTION_8822B */\n\n#define BIT_SHIFT_WMAC_MU_DBGSEL_8822B 5\n#define BIT_MASK_WMAC_MU_DBGSEL_8822B 0x3\n#define BIT_WMAC_MU_DBGSEL_8822B(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_MU_DBGSEL_8822B)                                 \\\n\t << BIT_SHIFT_WMAC_MU_DBGSEL_8822B)\n#define BITS_WMAC_MU_DBGSEL_8822B                                              \\\n\t(BIT_MASK_WMAC_MU_DBGSEL_8822B << BIT_SHIFT_WMAC_MU_DBGSEL_8822B)\n#define BIT_CLEAR_WMAC_MU_DBGSEL_8822B(x) ((x) & (~BITS_WMAC_MU_DBGSEL_8822B))\n#define BIT_GET_WMAC_MU_DBGSEL_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8822B) &                             \\\n\t BIT_MASK_WMAC_MU_DBGSEL_8822B)\n#define BIT_SET_WMAC_MU_DBGSEL_8822B(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_MU_DBGSEL_8822B(x) | BIT_WMAC_MU_DBGSEL_8822B(v))\n\n#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B 0\n#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B 0x1f\n#define BIT_WMAC_MU_CPRD_TIMEOUT_8822B(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B)                           \\\n\t << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B)\n#define BITS_WMAC_MU_CPRD_TIMEOUT_8822B                                        \\\n\t(BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B                                   \\\n\t << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B)\n#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8822B(x)                                \\\n\t((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8822B))\n#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B) &                       \\\n\t BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B)\n#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8822B(x, v)                               \\\n\t(BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8822B(x) |                             \\\n\t BIT_WMAC_MU_CPRD_TIMEOUT_8822B(v))\n\n/* 2 REG_WMAC_MU_BF_CTL_8822B */\n#define BIT_WMAC_INVLD_BFPRT_CHK_8822B BIT(15)\n#define BIT_WMAC_RETXBFRPTSEQ_UPD_8822B BIT(14)\n\n#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B 12\n#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B 0x3\n#define BIT_WMAC_MU_BFRPTSEG_SEL_8822B(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B)                           \\\n\t << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B)\n#define BITS_WMAC_MU_BFRPTSEG_SEL_8822B                                        \\\n\t(BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B                                   \\\n\t << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B)\n#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822B(x)                                \\\n\t((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8822B))\n#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B) &                       \\\n\t BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B)\n#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8822B(x, v)                               \\\n\t(BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822B(x) |                             \\\n\t BIT_WMAC_MU_BFRPTSEG_SEL_8822B(v))\n\n#define BIT_SHIFT_WMAC_MU_BF_MYAID_8822B 0\n#define BIT_MASK_WMAC_MU_BF_MYAID_8822B 0xfff\n#define BIT_WMAC_MU_BF_MYAID_8822B(x)                                          \\\n\t(((x) & BIT_MASK_WMAC_MU_BF_MYAID_8822B)                               \\\n\t << BIT_SHIFT_WMAC_MU_BF_MYAID_8822B)\n#define BITS_WMAC_MU_BF_MYAID_8822B                                            \\\n\t(BIT_MASK_WMAC_MU_BF_MYAID_8822B << BIT_SHIFT_WMAC_MU_BF_MYAID_8822B)\n#define BIT_CLEAR_WMAC_MU_BF_MYAID_8822B(x)                                    \\\n\t((x) & (~BITS_WMAC_MU_BF_MYAID_8822B))\n#define BIT_GET_WMAC_MU_BF_MYAID_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8822B) &                           \\\n\t BIT_MASK_WMAC_MU_BF_MYAID_8822B)\n#define BIT_SET_WMAC_MU_BF_MYAID_8822B(x, v)                                   \\\n\t(BIT_CLEAR_WMAC_MU_BF_MYAID_8822B(x) | BIT_WMAC_MU_BF_MYAID_8822B(v))\n\n/* 2 REG_WMAC_MU_BFRPT_PARA_8822B */\n\n#define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B 12\n#define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B 0x7\n#define BIT_BIT_BFRPT_PARA_USERID_SEL_8822B(x)                                 \\\n\t(((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B)                      \\\n\t << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B)\n#define BITS_BIT_BFRPT_PARA_USERID_SEL_8822B                                   \\\n\t(BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B                              \\\n\t << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B)\n#define BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL_8822B(x)                           \\\n\t((x) & (~BITS_BIT_BFRPT_PARA_USERID_SEL_8822B))\n#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL_8822B(x)                             \\\n\t(((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B) &                  \\\n\t BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B)\n#define BIT_SET_BIT_BFRPT_PARA_USERID_SEL_8822B(x, v)                          \\\n\t(BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL_8822B(x) |                        \\\n\t BIT_BIT_BFRPT_PARA_USERID_SEL_8822B(v))\n\n#define BIT_SHIFT_BFRPT_PARA_8822B 0\n#define BIT_MASK_BFRPT_PARA_8822B 0xfff\n#define BIT_BFRPT_PARA_8822B(x)                                                \\\n\t(((x) & BIT_MASK_BFRPT_PARA_8822B) << BIT_SHIFT_BFRPT_PARA_8822B)\n#define BITS_BFRPT_PARA_8822B                                                  \\\n\t(BIT_MASK_BFRPT_PARA_8822B << BIT_SHIFT_BFRPT_PARA_8822B)\n#define BIT_CLEAR_BFRPT_PARA_8822B(x) ((x) & (~BITS_BFRPT_PARA_8822B))\n#define BIT_GET_BFRPT_PARA_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_BFRPT_PARA_8822B) & BIT_MASK_BFRPT_PARA_8822B)\n#define BIT_SET_BFRPT_PARA_8822B(x, v)                                         \\\n\t(BIT_CLEAR_BFRPT_PARA_8822B(x) | BIT_BFRPT_PARA_8822B(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B */\n#define BIT_STATUS_BFEE2_8822B BIT(10)\n#define BIT_WMAC_MU_BFEE2_EN_8822B BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B 0\n#define BIT_MASK_WMAC_MU_BFEE2_AID_8822B 0x1ff\n#define BIT_WMAC_MU_BFEE2_AID_8822B(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8822B)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B)\n#define BITS_WMAC_MU_BFEE2_AID_8822B                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE2_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B)\n#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8822B(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE2_AID_8822B))\n#define BIT_GET_WMAC_MU_BFEE2_AID_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE2_AID_8822B)\n#define BIT_SET_WMAC_MU_BFEE2_AID_8822B(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE2_AID_8822B(x) | BIT_WMAC_MU_BFEE2_AID_8822B(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8822B */\n#define BIT_STATUS_BFEE3_8822B BIT(10)\n#define BIT_WMAC_MU_BFEE3_EN_8822B BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B 0\n#define BIT_MASK_WMAC_MU_BFEE3_AID_8822B 0x1ff\n#define BIT_WMAC_MU_BFEE3_AID_8822B(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8822B)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B)\n#define BITS_WMAC_MU_BFEE3_AID_8822B                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE3_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B)\n#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8822B(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE3_AID_8822B))\n#define BIT_GET_WMAC_MU_BFEE3_AID_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE3_AID_8822B)\n#define BIT_SET_WMAC_MU_BFEE3_AID_8822B(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE3_AID_8822B(x) | BIT_WMAC_MU_BFEE3_AID_8822B(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B */\n#define BIT_STATUS_BFEE4_8822B BIT(10)\n#define BIT_WMAC_MU_BFEE4_EN_8822B BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B 0\n#define BIT_MASK_WMAC_MU_BFEE4_AID_8822B 0x1ff\n#define BIT_WMAC_MU_BFEE4_AID_8822B(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8822B)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B)\n#define BITS_WMAC_MU_BFEE4_AID_8822B                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE4_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B)\n#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8822B(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE4_AID_8822B))\n#define BIT_GET_WMAC_MU_BFEE4_AID_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE4_AID_8822B)\n#define BIT_SET_WMAC_MU_BFEE4_AID_8822B(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE4_AID_8822B(x) | BIT_WMAC_MU_BFEE4_AID_8822B(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8822B */\n#define BIT_STATUS_BFEE5_8822B BIT(10)\n#define BIT_WMAC_MU_BFEE5_EN_8822B BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B 0\n#define BIT_MASK_WMAC_MU_BFEE5_AID_8822B 0x1ff\n#define BIT_WMAC_MU_BFEE5_AID_8822B(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8822B)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B)\n#define BITS_WMAC_MU_BFEE5_AID_8822B                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE5_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B)\n#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8822B(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE5_AID_8822B))\n#define BIT_GET_WMAC_MU_BFEE5_AID_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE5_AID_8822B)\n#define BIT_SET_WMAC_MU_BFEE5_AID_8822B(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE5_AID_8822B(x) | BIT_WMAC_MU_BFEE5_AID_8822B(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B */\n#define BIT_STATUS_BFEE6_8822B BIT(10)\n#define BIT_WMAC_MU_BFEE6_EN_8822B BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B 0\n#define BIT_MASK_WMAC_MU_BFEE6_AID_8822B 0x1ff\n#define BIT_WMAC_MU_BFEE6_AID_8822B(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8822B)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B)\n#define BITS_WMAC_MU_BFEE6_AID_8822B                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE6_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B)\n#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8822B(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE6_AID_8822B))\n#define BIT_GET_WMAC_MU_BFEE6_AID_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE6_AID_8822B)\n#define BIT_SET_WMAC_MU_BFEE6_AID_8822B(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE6_AID_8822B(x) | BIT_WMAC_MU_BFEE6_AID_8822B(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8822B */\n#define BIT_STATUS_BFEE7_8822B BIT(10)\n#define BIT_WMAC_MU_BFEE7_EN_8822B BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B 0\n#define BIT_MASK_WMAC_MU_BFEE7_AID_8822B 0x1ff\n#define BIT_WMAC_MU_BFEE7_AID_8822B(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8822B)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B)\n#define BITS_WMAC_MU_BFEE7_AID_8822B                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE7_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B)\n#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8822B(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE7_AID_8822B))\n#define BIT_GET_WMAC_MU_BFEE7_AID_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE7_AID_8822B)\n#define BIT_SET_WMAC_MU_BFEE7_AID_8822B(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE7_AID_8822B(x) | BIT_WMAC_MU_BFEE7_AID_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n#define BIT_RST_ALL_COUNTER_8822B BIT(31)\n\n#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B 16\n#define BIT_MASK_ABORT_RX_VBON_COUNTER_8822B 0xff\n#define BIT_ABORT_RX_VBON_COUNTER_8822B(x)                                     \\\n\t(((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8822B)                          \\\n\t << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B)\n#define BITS_ABORT_RX_VBON_COUNTER_8822B                                       \\\n\t(BIT_MASK_ABORT_RX_VBON_COUNTER_8822B                                  \\\n\t << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B)\n#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822B(x)                               \\\n\t((x) & (~BITS_ABORT_RX_VBON_COUNTER_8822B))\n#define BIT_GET_ABORT_RX_VBON_COUNTER_8822B(x)                                 \\\n\t(((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B) &                      \\\n\t BIT_MASK_ABORT_RX_VBON_COUNTER_8822B)\n#define BIT_SET_ABORT_RX_VBON_COUNTER_8822B(x, v)                              \\\n\t(BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822B(x) |                            \\\n\t BIT_ABORT_RX_VBON_COUNTER_8822B(v))\n\n#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B 8\n#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B 0xff\n#define BIT_ABORT_RX_RDRDY_COUNTER_8822B(x)                                    \\\n\t(((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B)                         \\\n\t << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B)\n#define BITS_ABORT_RX_RDRDY_COUNTER_8822B                                      \\\n\t(BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B                                 \\\n\t << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B)\n#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822B(x)                              \\\n\t((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8822B))\n#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8822B(x)                                \\\n\t(((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B) &                     \\\n\t BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B)\n#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8822B(x, v)                             \\\n\t(BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822B(x) |                           \\\n\t BIT_ABORT_RX_RDRDY_COUNTER_8822B(v))\n\n#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B 0\n#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B 0xff\n#define BIT_VBON_EARLY_FALLING_COUNTER_8822B(x)                                \\\n\t(((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B)                     \\\n\t << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B)\n#define BITS_VBON_EARLY_FALLING_COUNTER_8822B                                  \\\n\t(BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B                             \\\n\t << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B)\n#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822B(x)                          \\\n\t((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8822B))\n#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8822B(x)                            \\\n\t(((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B) &                 \\\n\t BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B)\n#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8822B(x, v)                         \\\n\t(BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822B(x) |                       \\\n\t BIT_VBON_EARLY_FALLING_COUNTER_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n#define BIT_WMAC_PLCP_TRX_SEL_8822B BIT(31)\n\n#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B 28\n#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B 0x7\n#define BIT_WMAC_PLCP_RDSIG_SEL_8822B(x)                                       \\\n\t(((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B)                            \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B)\n#define BITS_WMAC_PLCP_RDSIG_SEL_8822B                                         \\\n\t(BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B                                    \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B)\n#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822B(x)                                 \\\n\t((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8822B))\n#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B) &                        \\\n\t BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B)\n#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8822B(x, v)                                \\\n\t(BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822B(x) |                              \\\n\t BIT_WMAC_PLCP_RDSIG_SEL_8822B(v))\n\n#define BIT_SHIFT_WMAC_RATE_IDX_8822B 24\n#define BIT_MASK_WMAC_RATE_IDX_8822B 0xf\n#define BIT_WMAC_RATE_IDX_8822B(x)                                             \\\n\t(((x) & BIT_MASK_WMAC_RATE_IDX_8822B) << BIT_SHIFT_WMAC_RATE_IDX_8822B)\n#define BITS_WMAC_RATE_IDX_8822B                                               \\\n\t(BIT_MASK_WMAC_RATE_IDX_8822B << BIT_SHIFT_WMAC_RATE_IDX_8822B)\n#define BIT_CLEAR_WMAC_RATE_IDX_8822B(x) ((x) & (~BITS_WMAC_RATE_IDX_8822B))\n#define BIT_GET_WMAC_RATE_IDX_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_WMAC_RATE_IDX_8822B) & BIT_MASK_WMAC_RATE_IDX_8822B)\n#define BIT_SET_WMAC_RATE_IDX_8822B(x, v)                                      \\\n\t(BIT_CLEAR_WMAC_RATE_IDX_8822B(x) | BIT_WMAC_RATE_IDX_8822B(v))\n\n#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822B 0\n#define BIT_MASK_WMAC_PLCP_RDSIG_8822B 0xffffff\n#define BIT_WMAC_PLCP_RDSIG_8822B(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B)                                \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B)\n#define BITS_WMAC_PLCP_RDSIG_8822B                                             \\\n\t(BIT_MASK_WMAC_PLCP_RDSIG_8822B << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B)\n#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822B))\n#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) &                            \\\n\t BIT_MASK_WMAC_PLCP_RDSIG_8822B)\n#define BIT_SET_WMAC_PLCP_RDSIG_8822B(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) | BIT_WMAC_PLCP_RDSIG_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n#define BIT_WMAC_MUTX_IDX_8822B BIT(24)\n\n#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822B 0\n#define BIT_MASK_WMAC_PLCP_RDSIG_8822B 0xffffff\n#define BIT_WMAC_PLCP_RDSIG_8822B(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B)                                \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B)\n#define BITS_WMAC_PLCP_RDSIG_8822B                                             \\\n\t(BIT_MASK_WMAC_PLCP_RDSIG_8822B << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B)\n#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822B))\n#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) &                            \\\n\t BIT_MASK_WMAC_PLCP_RDSIG_8822B)\n#define BIT_SET_WMAC_PLCP_RDSIG_8822B(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) | BIT_WMAC_PLCP_RDSIG_8822B(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_0_8822B (TA0 REGISTER) */\n\n#define BIT_SHIFT_TA0_8822B 0\n#define BIT_MASK_TA0_8822B 0xffffffffffffL\n#define BIT_TA0_8822B(x) (((x) & BIT_MASK_TA0_8822B) << BIT_SHIFT_TA0_8822B)\n#define BITS_TA0_8822B (BIT_MASK_TA0_8822B << BIT_SHIFT_TA0_8822B)\n#define BIT_CLEAR_TA0_8822B(x) ((x) & (~BITS_TA0_8822B))\n#define BIT_GET_TA0_8822B(x) (((x) >> BIT_SHIFT_TA0_8822B) & BIT_MASK_TA0_8822B)\n#define BIT_SET_TA0_8822B(x, v) (BIT_CLEAR_TA0_8822B(x) | BIT_TA0_8822B(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_1_8822B (TA1 REGISTER) */\n\n#define BIT_SHIFT_TA1_8822B 0\n#define BIT_MASK_TA1_8822B 0xffffffffffffL\n#define BIT_TA1_8822B(x) (((x) & BIT_MASK_TA1_8822B) << BIT_SHIFT_TA1_8822B)\n#define BITS_TA1_8822B (BIT_MASK_TA1_8822B << BIT_SHIFT_TA1_8822B)\n#define BIT_CLEAR_TA1_8822B(x) ((x) & (~BITS_TA1_8822B))\n#define BIT_GET_TA1_8822B(x) (((x) >> BIT_SHIFT_TA1_8822B) & BIT_MASK_TA1_8822B)\n#define BIT_SET_TA1_8822B(x, v) (BIT_CLEAR_TA1_8822B(x) | BIT_TA1_8822B(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_2_8822B (TA2 REGISTER) */\n\n#define BIT_SHIFT_TA2_8822B 0\n#define BIT_MASK_TA2_8822B 0xffffffffffffL\n#define BIT_TA2_8822B(x) (((x) & BIT_MASK_TA2_8822B) << BIT_SHIFT_TA2_8822B)\n#define BITS_TA2_8822B (BIT_MASK_TA2_8822B << BIT_SHIFT_TA2_8822B)\n#define BIT_CLEAR_TA2_8822B(x) ((x) & (~BITS_TA2_8822B))\n#define BIT_GET_TA2_8822B(x) (((x) >> BIT_SHIFT_TA2_8822B) & BIT_MASK_TA2_8822B)\n#define BIT_SET_TA2_8822B(x, v) (BIT_CLEAR_TA2_8822B(x) | BIT_TA2_8822B(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_3_8822B (TA3 REGISTER) */\n\n#define BIT_SHIFT_TA3_8822B 0\n#define BIT_MASK_TA3_8822B 0xffffffffffffL\n#define BIT_TA3_8822B(x) (((x) & BIT_MASK_TA3_8822B) << BIT_SHIFT_TA3_8822B)\n#define BITS_TA3_8822B (BIT_MASK_TA3_8822B << BIT_SHIFT_TA3_8822B)\n#define BIT_CLEAR_TA3_8822B(x) ((x) & (~BITS_TA3_8822B))\n#define BIT_GET_TA3_8822B(x) (((x) >> BIT_SHIFT_TA3_8822B) & BIT_MASK_TA3_8822B)\n#define BIT_SET_TA3_8822B(x, v) (BIT_CLEAR_TA3_8822B(x) | BIT_TA3_8822B(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_4_8822B (TA4 REGISTER) */\n\n#define BIT_SHIFT_TA4_8822B 0\n#define BIT_MASK_TA4_8822B 0xffffffffffffL\n#define BIT_TA4_8822B(x) (((x) & BIT_MASK_TA4_8822B) << BIT_SHIFT_TA4_8822B)\n#define BITS_TA4_8822B (BIT_MASK_TA4_8822B << BIT_SHIFT_TA4_8822B)\n#define BIT_CLEAR_TA4_8822B(x) ((x) & (~BITS_TA4_8822B))\n#define BIT_GET_TA4_8822B(x) (((x) >> BIT_SHIFT_TA4_8822B) & BIT_MASK_TA4_8822B)\n#define BIT_SET_TA4_8822B(x, v) (BIT_CLEAR_TA4_8822B(x) | BIT_TA4_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_MACID1_8822B */\n\n#define BIT_SHIFT_MACID1_8822B 0\n#define BIT_MASK_MACID1_8822B 0xffffffffffffL\n#define BIT_MACID1_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_MACID1_8822B) << BIT_SHIFT_MACID1_8822B)\n#define BITS_MACID1_8822B (BIT_MASK_MACID1_8822B << BIT_SHIFT_MACID1_8822B)\n#define BIT_CLEAR_MACID1_8822B(x) ((x) & (~BITS_MACID1_8822B))\n#define BIT_GET_MACID1_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_MACID1_8822B) & BIT_MASK_MACID1_8822B)\n#define BIT_SET_MACID1_8822B(x, v)                                             \\\n\t(BIT_CLEAR_MACID1_8822B(x) | BIT_MACID1_8822B(v))\n\n/* 2 REG_BSSID1_8822B */\n\n#define BIT_SHIFT_BSSID1_8822B 0\n#define BIT_MASK_BSSID1_8822B 0xffffffffffffL\n#define BIT_BSSID1_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_BSSID1_8822B) << BIT_SHIFT_BSSID1_8822B)\n#define BITS_BSSID1_8822B (BIT_MASK_BSSID1_8822B << BIT_SHIFT_BSSID1_8822B)\n#define BIT_CLEAR_BSSID1_8822B(x) ((x) & (~BITS_BSSID1_8822B))\n#define BIT_GET_BSSID1_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_BSSID1_8822B) & BIT_MASK_BSSID1_8822B)\n#define BIT_SET_BSSID1_8822B(x, v)                                             \\\n\t(BIT_CLEAR_BSSID1_8822B(x) | BIT_BSSID1_8822B(v))\n\n/* 2 REG_BCN_PSR_RPT1_8822B */\n\n#define BIT_SHIFT_DTIM_CNT1_8822B 24\n#define BIT_MASK_DTIM_CNT1_8822B 0xff\n#define BIT_DTIM_CNT1_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT1_8822B) << BIT_SHIFT_DTIM_CNT1_8822B)\n#define BITS_DTIM_CNT1_8822B                                                   \\\n\t(BIT_MASK_DTIM_CNT1_8822B << BIT_SHIFT_DTIM_CNT1_8822B)\n#define BIT_CLEAR_DTIM_CNT1_8822B(x) ((x) & (~BITS_DTIM_CNT1_8822B))\n#define BIT_GET_DTIM_CNT1_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT1_8822B) & BIT_MASK_DTIM_CNT1_8822B)\n#define BIT_SET_DTIM_CNT1_8822B(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT1_8822B(x) | BIT_DTIM_CNT1_8822B(v))\n\n#define BIT_SHIFT_DTIM_PERIOD1_8822B 16\n#define BIT_MASK_DTIM_PERIOD1_8822B 0xff\n#define BIT_DTIM_PERIOD1_8822B(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD1_8822B) << BIT_SHIFT_DTIM_PERIOD1_8822B)\n#define BITS_DTIM_PERIOD1_8822B                                                \\\n\t(BIT_MASK_DTIM_PERIOD1_8822B << BIT_SHIFT_DTIM_PERIOD1_8822B)\n#define BIT_CLEAR_DTIM_PERIOD1_8822B(x) ((x) & (~BITS_DTIM_PERIOD1_8822B))\n#define BIT_GET_DTIM_PERIOD1_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD1_8822B) & BIT_MASK_DTIM_PERIOD1_8822B)\n#define BIT_SET_DTIM_PERIOD1_8822B(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD1_8822B(x) | BIT_DTIM_PERIOD1_8822B(v))\n\n#define BIT_DTIM1_8822B BIT(15)\n#define BIT_TIM1_8822B BIT(14)\n\n#define BIT_SHIFT_PS_AID_1_8822B 0\n#define BIT_MASK_PS_AID_1_8822B 0x7ff\n#define BIT_PS_AID_1_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_1_8822B) << BIT_SHIFT_PS_AID_1_8822B)\n#define BITS_PS_AID_1_8822B                                                    \\\n\t(BIT_MASK_PS_AID_1_8822B << BIT_SHIFT_PS_AID_1_8822B)\n#define BIT_CLEAR_PS_AID_1_8822B(x) ((x) & (~BITS_PS_AID_1_8822B))\n#define BIT_GET_PS_AID_1_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_1_8822B) & BIT_MASK_PS_AID_1_8822B)\n#define BIT_SET_PS_AID_1_8822B(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_1_8822B(x) | BIT_PS_AID_1_8822B(v))\n\n/* 2 REG_ASSOCIATED_BFMEE_SEL_8822B */\n#define BIT_TXUSER_ID1_8822B BIT(25)\n\n#define BIT_SHIFT_AID1_8822B 16\n#define BIT_MASK_AID1_8822B 0x1ff\n#define BIT_AID1_8822B(x) (((x) & BIT_MASK_AID1_8822B) << BIT_SHIFT_AID1_8822B)\n#define BITS_AID1_8822B (BIT_MASK_AID1_8822B << BIT_SHIFT_AID1_8822B)\n#define BIT_CLEAR_AID1_8822B(x) ((x) & (~BITS_AID1_8822B))\n#define BIT_GET_AID1_8822B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AID1_8822B) & BIT_MASK_AID1_8822B)\n#define BIT_SET_AID1_8822B(x, v) (BIT_CLEAR_AID1_8822B(x) | BIT_AID1_8822B(v))\n\n#define BIT_TXUSER_ID0_8822B BIT(9)\n\n#define BIT_SHIFT_AID0_8822B 0\n#define BIT_MASK_AID0_8822B 0x1ff\n#define BIT_AID0_8822B(x) (((x) & BIT_MASK_AID0_8822B) << BIT_SHIFT_AID0_8822B)\n#define BITS_AID0_8822B (BIT_MASK_AID0_8822B << BIT_SHIFT_AID0_8822B)\n#define BIT_CLEAR_AID0_8822B(x) ((x) & (~BITS_AID0_8822B))\n#define BIT_GET_AID0_8822B(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AID0_8822B) & BIT_MASK_AID0_8822B)\n#define BIT_SET_AID0_8822B(x, v) (BIT_CLEAR_AID0_8822B(x) | BIT_AID0_8822B(v))\n\n/* 2 REG_SND_PTCL_CTRL_8822B */\n\n#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B 24\n#define BIT_MASK_NDP_RX_STANDBY_TIMER_8822B 0xff\n#define BIT_NDP_RX_STANDBY_TIMER_8822B(x)                                      \\\n\t(((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822B)                           \\\n\t << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B)\n#define BITS_NDP_RX_STANDBY_TIMER_8822B                                        \\\n\t(BIT_MASK_NDP_RX_STANDBY_TIMER_8822B                                   \\\n\t << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B)\n#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822B(x)                                \\\n\t((x) & (~BITS_NDP_RX_STANDBY_TIMER_8822B))\n#define BIT_GET_NDP_RX_STANDBY_TIMER_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B) &                       \\\n\t BIT_MASK_NDP_RX_STANDBY_TIMER_8822B)\n#define BIT_SET_NDP_RX_STANDBY_TIMER_8822B(x, v)                               \\\n\t(BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822B(x) |                             \\\n\t BIT_NDP_RX_STANDBY_TIMER_8822B(v))\n\n#define BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B 16\n#define BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B 0x3f\n#define BIT_CSI_RPT_OFFSET_HT_V1_8822B(x)                                      \\\n\t(((x) & BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B)                           \\\n\t << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B)\n#define BITS_CSI_RPT_OFFSET_HT_V1_8822B                                        \\\n\t(BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B                                   \\\n\t << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B)\n#define BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822B(x)                                \\\n\t((x) & (~BITS_CSI_RPT_OFFSET_HT_V1_8822B))\n#define BIT_GET_CSI_RPT_OFFSET_HT_V1_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B) &                       \\\n\t BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B)\n#define BIT_SET_CSI_RPT_OFFSET_HT_V1_8822B(x, v)                               \\\n\t(BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822B(x) |                             \\\n\t BIT_CSI_RPT_OFFSET_HT_V1_8822B(v))\n\n#define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL_8822B BIT(15)\n#define BIT_NDPVLD_POS_RST_FFPTR_DIS_8822B BIT(14)\n\n#define BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B 8\n#define BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B 0x3f\n#define BIT_R_CSI_RPT_OFFSET_VHT_V1_8822B(x)                                   \\\n\t(((x) & BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B)                        \\\n\t << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B)\n#define BITS_R_CSI_RPT_OFFSET_VHT_V1_8822B                                     \\\n\t(BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B                                \\\n\t << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B)\n#define BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8822B(x)                             \\\n\t((x) & (~BITS_R_CSI_RPT_OFFSET_VHT_V1_8822B))\n#define BIT_GET_R_CSI_RPT_OFFSET_VHT_V1_8822B(x)                               \\\n\t(((x) >> BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B) &                    \\\n\t BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B)\n#define BIT_SET_R_CSI_RPT_OFFSET_VHT_V1_8822B(x, v)                            \\\n\t(BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8822B(x) |                          \\\n\t BIT_R_CSI_RPT_OFFSET_VHT_V1_8822B(v))\n\n#define BIT_R_WMAC_USE_NSTS_8822B BIT(7)\n#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8822B BIT(6)\n#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8822B BIT(5)\n#define BIT_R_WMAC_BFPARAM_SEL_8822B BIT(4)\n#define BIT_R_WMAC_CSISEQ_SEL_8822B BIT(3)\n#define BIT_R_WMAC_CSI_WITHHTC_EN_8822B BIT(2)\n#define BIT_R_WMAC_HT_NDPA_EN_8822B BIT(1)\n#define BIT_R_WMAC_VHT_NDPA_EN_8822B BIT(0)\n\n/* 2 REG_RX_CSI_RPT_INFO_8822B */\n\n/* 2 REG_NS_ARP_CTRL_8822B */\n#define BIT_R_WMAC_NSARP_RSPEN_8822B BIT(15)\n#define BIT_R_WMAC_NSARP_RARP_8822B BIT(9)\n#define BIT_R_WMAC_NSARP_RIPV6_8822B BIT(8)\n\n#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B 6\n#define BIT_MASK_R_WMAC_NSARP_MODEN_8822B 0x3\n#define BIT_R_WMAC_NSARP_MODEN_8822B(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8822B)                             \\\n\t << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B)\n#define BITS_R_WMAC_NSARP_MODEN_8822B                                          \\\n\t(BIT_MASK_R_WMAC_NSARP_MODEN_8822B                                     \\\n\t << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B)\n#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8822B(x)                                  \\\n\t((x) & (~BITS_R_WMAC_NSARP_MODEN_8822B))\n#define BIT_GET_R_WMAC_NSARP_MODEN_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B) &                         \\\n\t BIT_MASK_R_WMAC_NSARP_MODEN_8822B)\n#define BIT_SET_R_WMAC_NSARP_MODEN_8822B(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_NSARP_MODEN_8822B(x) |                               \\\n\t BIT_R_WMAC_NSARP_MODEN_8822B(v))\n\n#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B 4\n#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B 0x3\n#define BIT_R_WMAC_NSARP_RSPFTP_8822B(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B)                            \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B)\n#define BITS_R_WMAC_NSARP_RSPFTP_8822B                                         \\\n\t(BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B                                    \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B)\n#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822B(x)                                 \\\n\t((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8822B))\n#define BIT_GET_R_WMAC_NSARP_RSPFTP_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B) &                        \\\n\t BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B)\n#define BIT_SET_R_WMAC_NSARP_RSPFTP_8822B(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822B(x) |                              \\\n\t BIT_R_WMAC_NSARP_RSPFTP_8822B(v))\n\n#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B 0\n#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B 0xf\n#define BIT_R_WMAC_NSARP_RSPSEC_8822B(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B)                            \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B)\n#define BITS_R_WMAC_NSARP_RSPSEC_8822B                                         \\\n\t(BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B                                    \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B)\n#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822B(x)                                 \\\n\t((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8822B))\n#define BIT_GET_R_WMAC_NSARP_RSPSEC_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B) &                        \\\n\t BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B)\n#define BIT_SET_R_WMAC_NSARP_RSPSEC_8822B(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822B(x) |                              \\\n\t BIT_R_WMAC_NSARP_RSPSEC_8822B(v))\n\n/* 2 REG_NS_ARP_INFO_8822B */\n#define BIT_REQ_IS_MCNS_8822B BIT(23)\n#define BIT_REQ_IS_UCNS_8822B BIT(22)\n#define BIT_REQ_IS_USNS_8822B BIT(21)\n#define BIT_REQ_IS_ARP_8822B BIT(20)\n#define BIT_EXPRSP_MH_WITHQC_8822B BIT(19)\n\n#define BIT_SHIFT_EXPRSP_SECTYPE_8822B 16\n#define BIT_MASK_EXPRSP_SECTYPE_8822B 0x7\n#define BIT_EXPRSP_SECTYPE_8822B(x)                                            \\\n\t(((x) & BIT_MASK_EXPRSP_SECTYPE_8822B)                                 \\\n\t << BIT_SHIFT_EXPRSP_SECTYPE_8822B)\n#define BITS_EXPRSP_SECTYPE_8822B                                              \\\n\t(BIT_MASK_EXPRSP_SECTYPE_8822B << BIT_SHIFT_EXPRSP_SECTYPE_8822B)\n#define BIT_CLEAR_EXPRSP_SECTYPE_8822B(x) ((x) & (~BITS_EXPRSP_SECTYPE_8822B))\n#define BIT_GET_EXPRSP_SECTYPE_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8822B) &                             \\\n\t BIT_MASK_EXPRSP_SECTYPE_8822B)\n#define BIT_SET_EXPRSP_SECTYPE_8822B(x, v)                                     \\\n\t(BIT_CLEAR_EXPRSP_SECTYPE_8822B(x) | BIT_EXPRSP_SECTYPE_8822B(v))\n\n#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B 8\n#define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B 0xff\n#define BIT_EXPRSP_CHKSM_7_TO_0_8822B(x)                                       \\\n\t(((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B)                            \\\n\t << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B)\n#define BITS_EXPRSP_CHKSM_7_TO_0_8822B                                         \\\n\t(BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B                                    \\\n\t << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B)\n#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822B(x)                                 \\\n\t((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8822B))\n#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B) &                        \\\n\t BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B)\n#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8822B(x, v)                                \\\n\t(BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822B(x) |                              \\\n\t BIT_EXPRSP_CHKSM_7_TO_0_8822B(v))\n\n#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B 0\n#define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B 0xff\n#define BIT_EXPRSP_CHKSM_15_TO_8_8822B(x)                                      \\\n\t(((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B)                           \\\n\t << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B)\n#define BITS_EXPRSP_CHKSM_15_TO_8_8822B                                        \\\n\t(BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B                                   \\\n\t << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B)\n#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822B(x)                                \\\n\t((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8822B))\n#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B) &                       \\\n\t BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B)\n#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8822B(x, v)                               \\\n\t(BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822B(x) |                             \\\n\t BIT_EXPRSP_CHKSM_15_TO_8_8822B(v))\n\n/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8822B */\n\n#define BIT_SHIFT_WMAC_ARPIP_8822B 0\n#define BIT_MASK_WMAC_ARPIP_8822B 0xffffffffL\n#define BIT_WMAC_ARPIP_8822B(x)                                                \\\n\t(((x) & BIT_MASK_WMAC_ARPIP_8822B) << BIT_SHIFT_WMAC_ARPIP_8822B)\n#define BITS_WMAC_ARPIP_8822B                                                  \\\n\t(BIT_MASK_WMAC_ARPIP_8822B << BIT_SHIFT_WMAC_ARPIP_8822B)\n#define BIT_CLEAR_WMAC_ARPIP_8822B(x) ((x) & (~BITS_WMAC_ARPIP_8822B))\n#define BIT_GET_WMAC_ARPIP_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_WMAC_ARPIP_8822B) & BIT_MASK_WMAC_ARPIP_8822B)\n#define BIT_SET_WMAC_ARPIP_8822B(x, v)                                         \\\n\t(BIT_CLEAR_WMAC_ARPIP_8822B(x) | BIT_WMAC_ARPIP_8822B(v))\n\n/* 2 REG_BEAMFORMING_INFO_NSARP_8822B */\n\n#define BIT_SHIFT_BEAMFORMING_INFO_8822B 0\n#define BIT_MASK_BEAMFORMING_INFO_8822B 0xffffffffL\n#define BIT_BEAMFORMING_INFO_8822B(x)                                          \\\n\t(((x) & BIT_MASK_BEAMFORMING_INFO_8822B)                               \\\n\t << BIT_SHIFT_BEAMFORMING_INFO_8822B)\n#define BITS_BEAMFORMING_INFO_8822B                                            \\\n\t(BIT_MASK_BEAMFORMING_INFO_8822B << BIT_SHIFT_BEAMFORMING_INFO_8822B)\n#define BIT_CLEAR_BEAMFORMING_INFO_8822B(x)                                    \\\n\t((x) & (~BITS_BEAMFORMING_INFO_8822B))\n#define BIT_GET_BEAMFORMING_INFO_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BEAMFORMING_INFO_8822B) &                           \\\n\t BIT_MASK_BEAMFORMING_INFO_8822B)\n#define BIT_SET_BEAMFORMING_INFO_8822B(x, v)                                   \\\n\t(BIT_CLEAR_BEAMFORMING_INFO_8822B(x) | BIT_BEAMFORMING_INFO_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B 0xffffffffffffffffffffffffffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD_8822B(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B)                             \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B)\n#define BITS_R_WMAC_IPV6_MYIPAD_8822B                                          \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B                                     \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_8822B(x)                                  \\\n\t((x) & (~BITS_R_WMAC_IPV6_MYIPAD_8822B))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B) &                         \\\n\t BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD_8822B(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_8822B(x) |                               \\\n\t BIT_R_WMAC_IPV6_MYIPAD_8822B(v))\n\n/* 2 REG_RSVD_0X740_8822B */\n\n/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822B */\n\n#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B 4\n#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B 0xf\n#define BIT_R_WMAC_CTX_SUBTYPE_8822B(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B)                             \\\n\t << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B)\n#define BITS_R_WMAC_CTX_SUBTYPE_8822B                                          \\\n\t(BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B                                     \\\n\t << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B)\n#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822B(x)                                  \\\n\t((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8822B))\n#define BIT_GET_R_WMAC_CTX_SUBTYPE_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B) &                         \\\n\t BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B)\n#define BIT_SET_R_WMAC_CTX_SUBTYPE_8822B(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822B(x) |                               \\\n\t BIT_R_WMAC_CTX_SUBTYPE_8822B(v))\n\n#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B 0\n#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B 0xf\n#define BIT_R_WMAC_RTX_SUBTYPE_8822B(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B)                             \\\n\t << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B)\n#define BITS_R_WMAC_RTX_SUBTYPE_8822B                                          \\\n\t(BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B                                     \\\n\t << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B)\n#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822B(x)                                  \\\n\t((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8822B))\n#define BIT_GET_R_WMAC_RTX_SUBTYPE_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B) &                         \\\n\t BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B)\n#define BIT_SET_R_WMAC_RTX_SUBTYPE_8822B(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822B(x) |                               \\\n\t BIT_R_WMAC_RTX_SUBTYPE_8822B(v))\n\n/* 2 REG_WMAC_SWAES_CFG_8822B */\n\n/* 2 REG_BT_COEX_V2_8822B */\n#define BIT_GNT_BT_POLARITY_8822B BIT(12)\n#define BIT_GNT_BT_BYPASS_PRIORITY_8822B BIT(8)\n\n#define BIT_SHIFT_TIMER_8822B 0\n#define BIT_MASK_TIMER_8822B 0xff\n#define BIT_TIMER_8822B(x)                                                     \\\n\t(((x) & BIT_MASK_TIMER_8822B) << BIT_SHIFT_TIMER_8822B)\n#define BITS_TIMER_8822B (BIT_MASK_TIMER_8822B << BIT_SHIFT_TIMER_8822B)\n#define BIT_CLEAR_TIMER_8822B(x) ((x) & (~BITS_TIMER_8822B))\n#define BIT_GET_TIMER_8822B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TIMER_8822B) & BIT_MASK_TIMER_8822B)\n#define BIT_SET_TIMER_8822B(x, v)                                              \\\n\t(BIT_CLEAR_TIMER_8822B(x) | BIT_TIMER_8822B(v))\n\n/* 2 REG_BT_COEX_8822B */\n#define BIT_R_GNT_BT_RFC_SW_8822B BIT(12)\n#define BIT_R_GNT_BT_RFC_SW_EN_8822B BIT(11)\n#define BIT_R_GNT_BT_BB_SW_8822B BIT(10)\n#define BIT_R_GNT_BT_BB_SW_EN_8822B BIT(9)\n#define BIT_R_BT_CNT_THREN_8822B BIT(8)\n\n#define BIT_SHIFT_R_BT_CNT_THR_8822B 0\n#define BIT_MASK_R_BT_CNT_THR_8822B 0xff\n#define BIT_R_BT_CNT_THR_8822B(x)                                              \\\n\t(((x) & BIT_MASK_R_BT_CNT_THR_8822B) << BIT_SHIFT_R_BT_CNT_THR_8822B)\n#define BITS_R_BT_CNT_THR_8822B                                                \\\n\t(BIT_MASK_R_BT_CNT_THR_8822B << BIT_SHIFT_R_BT_CNT_THR_8822B)\n#define BIT_CLEAR_R_BT_CNT_THR_8822B(x) ((x) & (~BITS_R_BT_CNT_THR_8822B))\n#define BIT_GET_R_BT_CNT_THR_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_BT_CNT_THR_8822B) & BIT_MASK_R_BT_CNT_THR_8822B)\n#define BIT_SET_R_BT_CNT_THR_8822B(x, v)                                       \\\n\t(BIT_CLEAR_R_BT_CNT_THR_8822B(x) | BIT_R_BT_CNT_THR_8822B(v))\n\n/* 2 REG_WLAN_ACT_MASK_CTRL_8822B */\n#define BIT_WLRX_TER_BY_CTL_8822B BIT(43)\n#define BIT_WLRX_TER_BY_AD_8822B BIT(42)\n#define BIT_ANT_DIVERSITY_SEL_8822B BIT(41)\n#define BIT_ANTSEL_FOR_BT_CTRL_EN_8822B BIT(40)\n#define BIT_WLACT_LOW_GNTWL_EN_8822B BIT(34)\n#define BIT_WLACT_HIGH_GNTBT_EN_8822B BIT(33)\n#define BIT_NAV_UPPER_V1_8822B BIT(32)\n\n#define BIT_SHIFT_RXMYRTS_NAV_V1_8822B 8\n#define BIT_MASK_RXMYRTS_NAV_V1_8822B 0xff\n#define BIT_RXMYRTS_NAV_V1_8822B(x)                                            \\\n\t(((x) & BIT_MASK_RXMYRTS_NAV_V1_8822B)                                 \\\n\t << BIT_SHIFT_RXMYRTS_NAV_V1_8822B)\n#define BITS_RXMYRTS_NAV_V1_8822B                                              \\\n\t(BIT_MASK_RXMYRTS_NAV_V1_8822B << BIT_SHIFT_RXMYRTS_NAV_V1_8822B)\n#define BIT_CLEAR_RXMYRTS_NAV_V1_8822B(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8822B))\n#define BIT_GET_RXMYRTS_NAV_V1_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8822B) &                             \\\n\t BIT_MASK_RXMYRTS_NAV_V1_8822B)\n#define BIT_SET_RXMYRTS_NAV_V1_8822B(x, v)                                     \\\n\t(BIT_CLEAR_RXMYRTS_NAV_V1_8822B(x) | BIT_RXMYRTS_NAV_V1_8822B(v))\n\n#define BIT_SHIFT_RTSRST_V1_8822B 0\n#define BIT_MASK_RTSRST_V1_8822B 0xff\n#define BIT_RTSRST_V1_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_RTSRST_V1_8822B) << BIT_SHIFT_RTSRST_V1_8822B)\n#define BITS_RTSRST_V1_8822B                                                   \\\n\t(BIT_MASK_RTSRST_V1_8822B << BIT_SHIFT_RTSRST_V1_8822B)\n#define BIT_CLEAR_RTSRST_V1_8822B(x) ((x) & (~BITS_RTSRST_V1_8822B))\n#define BIT_GET_RTSRST_V1_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_RTSRST_V1_8822B) & BIT_MASK_RTSRST_V1_8822B)\n#define BIT_SET_RTSRST_V1_8822B(x, v)                                          \\\n\t(BIT_CLEAR_RTSRST_V1_8822B(x) | BIT_RTSRST_V1_8822B(v))\n\n/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8822B */\n\n#define BIT_SHIFT_BT_STAT_DELAY_8822B 12\n#define BIT_MASK_BT_STAT_DELAY_8822B 0xf\n#define BIT_BT_STAT_DELAY_8822B(x)                                             \\\n\t(((x) & BIT_MASK_BT_STAT_DELAY_8822B) << BIT_SHIFT_BT_STAT_DELAY_8822B)\n#define BITS_BT_STAT_DELAY_8822B                                               \\\n\t(BIT_MASK_BT_STAT_DELAY_8822B << BIT_SHIFT_BT_STAT_DELAY_8822B)\n#define BIT_CLEAR_BT_STAT_DELAY_8822B(x) ((x) & (~BITS_BT_STAT_DELAY_8822B))\n#define BIT_GET_BT_STAT_DELAY_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_BT_STAT_DELAY_8822B) & BIT_MASK_BT_STAT_DELAY_8822B)\n#define BIT_SET_BT_STAT_DELAY_8822B(x, v)                                      \\\n\t(BIT_CLEAR_BT_STAT_DELAY_8822B(x) | BIT_BT_STAT_DELAY_8822B(v))\n\n#define BIT_SHIFT_BT_TRX_INIT_DETECT_8822B 8\n#define BIT_MASK_BT_TRX_INIT_DETECT_8822B 0xf\n#define BIT_BT_TRX_INIT_DETECT_8822B(x)                                        \\\n\t(((x) & BIT_MASK_BT_TRX_INIT_DETECT_8822B)                             \\\n\t << BIT_SHIFT_BT_TRX_INIT_DETECT_8822B)\n#define BITS_BT_TRX_INIT_DETECT_8822B                                          \\\n\t(BIT_MASK_BT_TRX_INIT_DETECT_8822B                                     \\\n\t << BIT_SHIFT_BT_TRX_INIT_DETECT_8822B)\n#define BIT_CLEAR_BT_TRX_INIT_DETECT_8822B(x)                                  \\\n\t((x) & (~BITS_BT_TRX_INIT_DETECT_8822B))\n#define BIT_GET_BT_TRX_INIT_DETECT_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8822B) &                         \\\n\t BIT_MASK_BT_TRX_INIT_DETECT_8822B)\n#define BIT_SET_BT_TRX_INIT_DETECT_8822B(x, v)                                 \\\n\t(BIT_CLEAR_BT_TRX_INIT_DETECT_8822B(x) |                               \\\n\t BIT_BT_TRX_INIT_DETECT_8822B(v))\n\n#define BIT_SHIFT_BT_PRI_DETECT_TO_8822B 4\n#define BIT_MASK_BT_PRI_DETECT_TO_8822B 0xf\n#define BIT_BT_PRI_DETECT_TO_8822B(x)                                          \\\n\t(((x) & BIT_MASK_BT_PRI_DETECT_TO_8822B)                               \\\n\t << BIT_SHIFT_BT_PRI_DETECT_TO_8822B)\n#define BITS_BT_PRI_DETECT_TO_8822B                                            \\\n\t(BIT_MASK_BT_PRI_DETECT_TO_8822B << BIT_SHIFT_BT_PRI_DETECT_TO_8822B)\n#define BIT_CLEAR_BT_PRI_DETECT_TO_8822B(x)                                    \\\n\t((x) & (~BITS_BT_PRI_DETECT_TO_8822B))\n#define BIT_GET_BT_PRI_DETECT_TO_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8822B) &                           \\\n\t BIT_MASK_BT_PRI_DETECT_TO_8822B)\n#define BIT_SET_BT_PRI_DETECT_TO_8822B(x, v)                                   \\\n\t(BIT_CLEAR_BT_PRI_DETECT_TO_8822B(x) | BIT_BT_PRI_DETECT_TO_8822B(v))\n\n#define BIT_R_GRANTALL_WLMASK_8822B BIT(3)\n#define BIT_STATIS_BT_EN_8822B BIT(2)\n#define BIT_WL_ACT_MASK_ENABLE_8822B BIT(1)\n#define BIT_ENHANCED_BT_8822B BIT(0)\n\n/* 2 REG_BT_ACT_STATISTICS_8822B */\n\n#define BIT_SHIFT_STATIS_BT_LO_RX_8822B (48 & CPU_OPT_WIDTH)\n#define BIT_MASK_STATIS_BT_LO_RX_8822B 0xffff\n#define BIT_STATIS_BT_LO_RX_8822B(x)                                           \\\n\t(((x) & BIT_MASK_STATIS_BT_LO_RX_8822B)                                \\\n\t << BIT_SHIFT_STATIS_BT_LO_RX_8822B)\n#define BITS_STATIS_BT_LO_RX_8822B                                             \\\n\t(BIT_MASK_STATIS_BT_LO_RX_8822B << BIT_SHIFT_STATIS_BT_LO_RX_8822B)\n#define BIT_CLEAR_STATIS_BT_LO_RX_8822B(x) ((x) & (~BITS_STATIS_BT_LO_RX_8822B))\n#define BIT_GET_STATIS_BT_LO_RX_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8822B) &                            \\\n\t BIT_MASK_STATIS_BT_LO_RX_8822B)\n#define BIT_SET_STATIS_BT_LO_RX_8822B(x, v)                                    \\\n\t(BIT_CLEAR_STATIS_BT_LO_RX_8822B(x) | BIT_STATIS_BT_LO_RX_8822B(v))\n\n#define BIT_SHIFT_STATIS_BT_LO_TX_8822B (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_STATIS_BT_LO_TX_8822B 0xffff\n#define BIT_STATIS_BT_LO_TX_8822B(x)                                           \\\n\t(((x) & BIT_MASK_STATIS_BT_LO_TX_8822B)                                \\\n\t << BIT_SHIFT_STATIS_BT_LO_TX_8822B)\n#define BITS_STATIS_BT_LO_TX_8822B                                             \\\n\t(BIT_MASK_STATIS_BT_LO_TX_8822B << BIT_SHIFT_STATIS_BT_LO_TX_8822B)\n#define BIT_CLEAR_STATIS_BT_LO_TX_8822B(x) ((x) & (~BITS_STATIS_BT_LO_TX_8822B))\n#define BIT_GET_STATIS_BT_LO_TX_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8822B) &                            \\\n\t BIT_MASK_STATIS_BT_LO_TX_8822B)\n#define BIT_SET_STATIS_BT_LO_TX_8822B(x, v)                                    \\\n\t(BIT_CLEAR_STATIS_BT_LO_TX_8822B(x) | BIT_STATIS_BT_LO_TX_8822B(v))\n\n#define BIT_SHIFT_STATIS_BT_HI_RX_8822B 16\n#define BIT_MASK_STATIS_BT_HI_RX_8822B 0xffff\n#define BIT_STATIS_BT_HI_RX_8822B(x)                                           \\\n\t(((x) & BIT_MASK_STATIS_BT_HI_RX_8822B)                                \\\n\t << BIT_SHIFT_STATIS_BT_HI_RX_8822B)\n#define BITS_STATIS_BT_HI_RX_8822B                                             \\\n\t(BIT_MASK_STATIS_BT_HI_RX_8822B << BIT_SHIFT_STATIS_BT_HI_RX_8822B)\n#define BIT_CLEAR_STATIS_BT_HI_RX_8822B(x) ((x) & (~BITS_STATIS_BT_HI_RX_8822B))\n#define BIT_GET_STATIS_BT_HI_RX_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8822B) &                            \\\n\t BIT_MASK_STATIS_BT_HI_RX_8822B)\n#define BIT_SET_STATIS_BT_HI_RX_8822B(x, v)                                    \\\n\t(BIT_CLEAR_STATIS_BT_HI_RX_8822B(x) | BIT_STATIS_BT_HI_RX_8822B(v))\n\n#define BIT_SHIFT_STATIS_BT_HI_TX_8822B 0\n#define BIT_MASK_STATIS_BT_HI_TX_8822B 0xffff\n#define BIT_STATIS_BT_HI_TX_8822B(x)                                           \\\n\t(((x) & BIT_MASK_STATIS_BT_HI_TX_8822B)                                \\\n\t << BIT_SHIFT_STATIS_BT_HI_TX_8822B)\n#define BITS_STATIS_BT_HI_TX_8822B                                             \\\n\t(BIT_MASK_STATIS_BT_HI_TX_8822B << BIT_SHIFT_STATIS_BT_HI_TX_8822B)\n#define BIT_CLEAR_STATIS_BT_HI_TX_8822B(x) ((x) & (~BITS_STATIS_BT_HI_TX_8822B))\n#define BIT_GET_STATIS_BT_HI_TX_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8822B) &                            \\\n\t BIT_MASK_STATIS_BT_HI_TX_8822B)\n#define BIT_SET_STATIS_BT_HI_TX_8822B(x, v)                                    \\\n\t(BIT_CLEAR_STATIS_BT_HI_TX_8822B(x) | BIT_STATIS_BT_HI_TX_8822B(v))\n\n/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8822B */\n\n#define BIT_SHIFT_R_BT_CMD_RPT_8822B 16\n#define BIT_MASK_R_BT_CMD_RPT_8822B 0xffff\n#define BIT_R_BT_CMD_RPT_8822B(x)                                              \\\n\t(((x) & BIT_MASK_R_BT_CMD_RPT_8822B) << BIT_SHIFT_R_BT_CMD_RPT_8822B)\n#define BITS_R_BT_CMD_RPT_8822B                                                \\\n\t(BIT_MASK_R_BT_CMD_RPT_8822B << BIT_SHIFT_R_BT_CMD_RPT_8822B)\n#define BIT_CLEAR_R_BT_CMD_RPT_8822B(x) ((x) & (~BITS_R_BT_CMD_RPT_8822B))\n#define BIT_GET_R_BT_CMD_RPT_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_BT_CMD_RPT_8822B) & BIT_MASK_R_BT_CMD_RPT_8822B)\n#define BIT_SET_R_BT_CMD_RPT_8822B(x, v)                                       \\\n\t(BIT_CLEAR_R_BT_CMD_RPT_8822B(x) | BIT_R_BT_CMD_RPT_8822B(v))\n\n#define BIT_SHIFT_R_RPT_FROM_BT_8822B 8\n#define BIT_MASK_R_RPT_FROM_BT_8822B 0xff\n#define BIT_R_RPT_FROM_BT_8822B(x)                                             \\\n\t(((x) & BIT_MASK_R_RPT_FROM_BT_8822B) << BIT_SHIFT_R_RPT_FROM_BT_8822B)\n#define BITS_R_RPT_FROM_BT_8822B                                               \\\n\t(BIT_MASK_R_RPT_FROM_BT_8822B << BIT_SHIFT_R_RPT_FROM_BT_8822B)\n#define BIT_CLEAR_R_RPT_FROM_BT_8822B(x) ((x) & (~BITS_R_RPT_FROM_BT_8822B))\n#define BIT_GET_R_RPT_FROM_BT_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_RPT_FROM_BT_8822B) & BIT_MASK_R_RPT_FROM_BT_8822B)\n#define BIT_SET_R_RPT_FROM_BT_8822B(x, v)                                      \\\n\t(BIT_CLEAR_R_RPT_FROM_BT_8822B(x) | BIT_R_RPT_FROM_BT_8822B(v))\n\n#define BIT_SHIFT_BT_HID_ISR_SET_8822B 6\n#define BIT_MASK_BT_HID_ISR_SET_8822B 0x3\n#define BIT_BT_HID_ISR_SET_8822B(x)                                            \\\n\t(((x) & BIT_MASK_BT_HID_ISR_SET_8822B)                                 \\\n\t << BIT_SHIFT_BT_HID_ISR_SET_8822B)\n#define BITS_BT_HID_ISR_SET_8822B                                              \\\n\t(BIT_MASK_BT_HID_ISR_SET_8822B << BIT_SHIFT_BT_HID_ISR_SET_8822B)\n#define BIT_CLEAR_BT_HID_ISR_SET_8822B(x) ((x) & (~BITS_BT_HID_ISR_SET_8822B))\n#define BIT_GET_BT_HID_ISR_SET_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_BT_HID_ISR_SET_8822B) &                             \\\n\t BIT_MASK_BT_HID_ISR_SET_8822B)\n#define BIT_SET_BT_HID_ISR_SET_8822B(x, v)                                     \\\n\t(BIT_CLEAR_BT_HID_ISR_SET_8822B(x) | BIT_BT_HID_ISR_SET_8822B(v))\n\n#define BIT_TDMA_BT_START_NOTIFY_8822B BIT(5)\n#define BIT_ENABLE_TDMA_FW_MODE_8822B BIT(4)\n#define BIT_ENABLE_PTA_TDMA_MODE_8822B BIT(3)\n#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8822B BIT(2)\n#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8822B BIT(1)\n#define BIT_RTK_BT_ENABLE_8822B BIT(0)\n\n/* 2 REG_BT_STATUS_REPORT_REGISTER_8822B */\n\n#define BIT_SHIFT_BT_PROFILE_8822B 24\n#define BIT_MASK_BT_PROFILE_8822B 0xff\n#define BIT_BT_PROFILE_8822B(x)                                                \\\n\t(((x) & BIT_MASK_BT_PROFILE_8822B) << BIT_SHIFT_BT_PROFILE_8822B)\n#define BITS_BT_PROFILE_8822B                                                  \\\n\t(BIT_MASK_BT_PROFILE_8822B << BIT_SHIFT_BT_PROFILE_8822B)\n#define BIT_CLEAR_BT_PROFILE_8822B(x) ((x) & (~BITS_BT_PROFILE_8822B))\n#define BIT_GET_BT_PROFILE_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_BT_PROFILE_8822B) & BIT_MASK_BT_PROFILE_8822B)\n#define BIT_SET_BT_PROFILE_8822B(x, v)                                         \\\n\t(BIT_CLEAR_BT_PROFILE_8822B(x) | BIT_BT_PROFILE_8822B(v))\n\n#define BIT_SHIFT_BT_POWER_8822B 16\n#define BIT_MASK_BT_POWER_8822B 0xff\n#define BIT_BT_POWER_8822B(x)                                                  \\\n\t(((x) & BIT_MASK_BT_POWER_8822B) << BIT_SHIFT_BT_POWER_8822B)\n#define BITS_BT_POWER_8822B                                                    \\\n\t(BIT_MASK_BT_POWER_8822B << BIT_SHIFT_BT_POWER_8822B)\n#define BIT_CLEAR_BT_POWER_8822B(x) ((x) & (~BITS_BT_POWER_8822B))\n#define BIT_GET_BT_POWER_8822B(x)                                              \\\n\t(((x) >> BIT_SHIFT_BT_POWER_8822B) & BIT_MASK_BT_POWER_8822B)\n#define BIT_SET_BT_POWER_8822B(x, v)                                           \\\n\t(BIT_CLEAR_BT_POWER_8822B(x) | BIT_BT_POWER_8822B(v))\n\n#define BIT_SHIFT_BT_PREDECT_STATUS_8822B 8\n#define BIT_MASK_BT_PREDECT_STATUS_8822B 0xff\n#define BIT_BT_PREDECT_STATUS_8822B(x)                                         \\\n\t(((x) & BIT_MASK_BT_PREDECT_STATUS_8822B)                              \\\n\t << BIT_SHIFT_BT_PREDECT_STATUS_8822B)\n#define BITS_BT_PREDECT_STATUS_8822B                                           \\\n\t(BIT_MASK_BT_PREDECT_STATUS_8822B << BIT_SHIFT_BT_PREDECT_STATUS_8822B)\n#define BIT_CLEAR_BT_PREDECT_STATUS_8822B(x)                                   \\\n\t((x) & (~BITS_BT_PREDECT_STATUS_8822B))\n#define BIT_GET_BT_PREDECT_STATUS_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8822B) &                          \\\n\t BIT_MASK_BT_PREDECT_STATUS_8822B)\n#define BIT_SET_BT_PREDECT_STATUS_8822B(x, v)                                  \\\n\t(BIT_CLEAR_BT_PREDECT_STATUS_8822B(x) | BIT_BT_PREDECT_STATUS_8822B(v))\n\n#define BIT_SHIFT_BT_CMD_INFO_8822B 0\n#define BIT_MASK_BT_CMD_INFO_8822B 0xff\n#define BIT_BT_CMD_INFO_8822B(x)                                               \\\n\t(((x) & BIT_MASK_BT_CMD_INFO_8822B) << BIT_SHIFT_BT_CMD_INFO_8822B)\n#define BITS_BT_CMD_INFO_8822B                                                 \\\n\t(BIT_MASK_BT_CMD_INFO_8822B << BIT_SHIFT_BT_CMD_INFO_8822B)\n#define BIT_CLEAR_BT_CMD_INFO_8822B(x) ((x) & (~BITS_BT_CMD_INFO_8822B))\n#define BIT_GET_BT_CMD_INFO_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_BT_CMD_INFO_8822B) & BIT_MASK_BT_CMD_INFO_8822B)\n#define BIT_SET_BT_CMD_INFO_8822B(x, v)                                        \\\n\t(BIT_CLEAR_BT_CMD_INFO_8822B(x) | BIT_BT_CMD_INFO_8822B(v))\n\n/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8822B */\n#define BIT_EN_MAC_NULL_PKT_NOTIFY_8822B BIT(31)\n#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8822B BIT(30)\n#define BIT_EN_BT_STSTUS_RPT_8822B BIT(29)\n#define BIT_EN_BT_POWER_8822B BIT(28)\n#define BIT_EN_BT_CHANNEL_8822B BIT(27)\n#define BIT_EN_BT_SLOT_CHANGE_8822B BIT(26)\n#define BIT_EN_BT_PROFILE_OR_HID_8822B BIT(25)\n#define BIT_WLAN_RPT_NOTIFY_8822B BIT(24)\n\n#define BIT_SHIFT_WLAN_RPT_DATA_8822B 16\n#define BIT_MASK_WLAN_RPT_DATA_8822B 0xff\n#define BIT_WLAN_RPT_DATA_8822B(x)                                             \\\n\t(((x) & BIT_MASK_WLAN_RPT_DATA_8822B) << BIT_SHIFT_WLAN_RPT_DATA_8822B)\n#define BITS_WLAN_RPT_DATA_8822B                                               \\\n\t(BIT_MASK_WLAN_RPT_DATA_8822B << BIT_SHIFT_WLAN_RPT_DATA_8822B)\n#define BIT_CLEAR_WLAN_RPT_DATA_8822B(x) ((x) & (~BITS_WLAN_RPT_DATA_8822B))\n#define BIT_GET_WLAN_RPT_DATA_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_WLAN_RPT_DATA_8822B) & BIT_MASK_WLAN_RPT_DATA_8822B)\n#define BIT_SET_WLAN_RPT_DATA_8822B(x, v)                                      \\\n\t(BIT_CLEAR_WLAN_RPT_DATA_8822B(x) | BIT_WLAN_RPT_DATA_8822B(v))\n\n#define BIT_SHIFT_CMD_ID_8822B 8\n#define BIT_MASK_CMD_ID_8822B 0xff\n#define BIT_CMD_ID_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_CMD_ID_8822B) << BIT_SHIFT_CMD_ID_8822B)\n#define BITS_CMD_ID_8822B (BIT_MASK_CMD_ID_8822B << BIT_SHIFT_CMD_ID_8822B)\n#define BIT_CLEAR_CMD_ID_8822B(x) ((x) & (~BITS_CMD_ID_8822B))\n#define BIT_GET_CMD_ID_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_CMD_ID_8822B) & BIT_MASK_CMD_ID_8822B)\n#define BIT_SET_CMD_ID_8822B(x, v)                                             \\\n\t(BIT_CLEAR_CMD_ID_8822B(x) | BIT_CMD_ID_8822B(v))\n\n#define BIT_SHIFT_BT_DATA_8822B 0\n#define BIT_MASK_BT_DATA_8822B 0xff\n#define BIT_BT_DATA_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_BT_DATA_8822B) << BIT_SHIFT_BT_DATA_8822B)\n#define BITS_BT_DATA_8822B (BIT_MASK_BT_DATA_8822B << BIT_SHIFT_BT_DATA_8822B)\n#define BIT_CLEAR_BT_DATA_8822B(x) ((x) & (~BITS_BT_DATA_8822B))\n#define BIT_GET_BT_DATA_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_BT_DATA_8822B) & BIT_MASK_BT_DATA_8822B)\n#define BIT_SET_BT_DATA_8822B(x, v)                                            \\\n\t(BIT_CLEAR_BT_DATA_8822B(x) | BIT_BT_DATA_8822B(v))\n\n/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822B */\n\n#define BIT_SHIFT_WLAN_RPT_TO_8822B 0\n#define BIT_MASK_WLAN_RPT_TO_8822B 0xff\n#define BIT_WLAN_RPT_TO_8822B(x)                                               \\\n\t(((x) & BIT_MASK_WLAN_RPT_TO_8822B) << BIT_SHIFT_WLAN_RPT_TO_8822B)\n#define BITS_WLAN_RPT_TO_8822B                                                 \\\n\t(BIT_MASK_WLAN_RPT_TO_8822B << BIT_SHIFT_WLAN_RPT_TO_8822B)\n#define BIT_CLEAR_WLAN_RPT_TO_8822B(x) ((x) & (~BITS_WLAN_RPT_TO_8822B))\n#define BIT_GET_WLAN_RPT_TO_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_WLAN_RPT_TO_8822B) & BIT_MASK_WLAN_RPT_TO_8822B)\n#define BIT_SET_WLAN_RPT_TO_8822B(x, v)                                        \\\n\t(BIT_CLEAR_WLAN_RPT_TO_8822B(x) | BIT_WLAN_RPT_TO_8822B(v))\n\n/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822B */\n\n#define BIT_SHIFT_ISOLATION_CHK_8822B 1\n#define BIT_MASK_ISOLATION_CHK_8822B 0x7fffffffffffffffffffL\n#define BIT_ISOLATION_CHK_8822B(x)                                             \\\n\t(((x) & BIT_MASK_ISOLATION_CHK_8822B) << BIT_SHIFT_ISOLATION_CHK_8822B)\n#define BITS_ISOLATION_CHK_8822B                                               \\\n\t(BIT_MASK_ISOLATION_CHK_8822B << BIT_SHIFT_ISOLATION_CHK_8822B)\n#define BIT_CLEAR_ISOLATION_CHK_8822B(x) ((x) & (~BITS_ISOLATION_CHK_8822B))\n#define BIT_GET_ISOLATION_CHK_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_ISOLATION_CHK_8822B) & BIT_MASK_ISOLATION_CHK_8822B)\n#define BIT_SET_ISOLATION_CHK_8822B(x, v)                                      \\\n\t(BIT_CLEAR_ISOLATION_CHK_8822B(x) | BIT_ISOLATION_CHK_8822B(v))\n\n#define BIT_ISOLATION_EN_8822B BIT(0)\n\n/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8822B */\n#define BIT_BT_HID_ISR_8822B BIT(7)\n#define BIT_BT_QUERY_ISR_8822B BIT(6)\n#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8822B BIT(5)\n#define BIT_WLAN_RPT_ISR_8822B BIT(4)\n#define BIT_BT_POWER_ISR_8822B BIT(3)\n#define BIT_BT_CHANNEL_ISR_8822B BIT(2)\n#define BIT_BT_SLOT_CHANGE_ISR_8822B BIT(1)\n#define BIT_BT_PROFILE_ISR_8822B BIT(0)\n\n/* 2 REG_BT_TDMA_TIME_REGISTER_8822B */\n\n#define BIT_SHIFT_BT_TIME_8822B 6\n#define BIT_MASK_BT_TIME_8822B 0x3ffffff\n#define BIT_BT_TIME_8822B(x)                                                   \\\n\t(((x) & BIT_MASK_BT_TIME_8822B) << BIT_SHIFT_BT_TIME_8822B)\n#define BITS_BT_TIME_8822B (BIT_MASK_BT_TIME_8822B << BIT_SHIFT_BT_TIME_8822B)\n#define BIT_CLEAR_BT_TIME_8822B(x) ((x) & (~BITS_BT_TIME_8822B))\n#define BIT_GET_BT_TIME_8822B(x)                                               \\\n\t(((x) >> BIT_SHIFT_BT_TIME_8822B) & BIT_MASK_BT_TIME_8822B)\n#define BIT_SET_BT_TIME_8822B(x, v)                                            \\\n\t(BIT_CLEAR_BT_TIME_8822B(x) | BIT_BT_TIME_8822B(v))\n\n#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B 0\n#define BIT_MASK_BT_RPT_SAMPLE_RATE_8822B 0x3f\n#define BIT_BT_RPT_SAMPLE_RATE_8822B(x)                                        \\\n\t(((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822B)                             \\\n\t << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B)\n#define BITS_BT_RPT_SAMPLE_RATE_8822B                                          \\\n\t(BIT_MASK_BT_RPT_SAMPLE_RATE_8822B                                     \\\n\t << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B)\n#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822B(x)                                  \\\n\t((x) & (~BITS_BT_RPT_SAMPLE_RATE_8822B))\n#define BIT_GET_BT_RPT_SAMPLE_RATE_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B) &                         \\\n\t BIT_MASK_BT_RPT_SAMPLE_RATE_8822B)\n#define BIT_SET_BT_RPT_SAMPLE_RATE_8822B(x, v)                                 \\\n\t(BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822B(x) |                               \\\n\t BIT_BT_RPT_SAMPLE_RATE_8822B(v))\n\n/* 2 REG_BT_ACT_REGISTER_8822B */\n\n#define BIT_SHIFT_BT_EISR_EN_8822B 16\n#define BIT_MASK_BT_EISR_EN_8822B 0xff\n#define BIT_BT_EISR_EN_8822B(x)                                                \\\n\t(((x) & BIT_MASK_BT_EISR_EN_8822B) << BIT_SHIFT_BT_EISR_EN_8822B)\n#define BITS_BT_EISR_EN_8822B                                                  \\\n\t(BIT_MASK_BT_EISR_EN_8822B << BIT_SHIFT_BT_EISR_EN_8822B)\n#define BIT_CLEAR_BT_EISR_EN_8822B(x) ((x) & (~BITS_BT_EISR_EN_8822B))\n#define BIT_GET_BT_EISR_EN_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_BT_EISR_EN_8822B) & BIT_MASK_BT_EISR_EN_8822B)\n#define BIT_SET_BT_EISR_EN_8822B(x, v)                                         \\\n\t(BIT_CLEAR_BT_EISR_EN_8822B(x) | BIT_BT_EISR_EN_8822B(v))\n\n#define BIT_BT_ACT_FALLING_ISR_8822B BIT(10)\n#define BIT_BT_ACT_RISING_ISR_8822B BIT(9)\n#define BIT_TDMA_TO_ISR_8822B BIT(8)\n\n#define BIT_SHIFT_BT_CH_8822B 0\n#define BIT_MASK_BT_CH_8822B 0xff\n#define BIT_BT_CH_8822B(x)                                                     \\\n\t(((x) & BIT_MASK_BT_CH_8822B) << BIT_SHIFT_BT_CH_8822B)\n#define BITS_BT_CH_8822B (BIT_MASK_BT_CH_8822B << BIT_SHIFT_BT_CH_8822B)\n#define BIT_CLEAR_BT_CH_8822B(x) ((x) & (~BITS_BT_CH_8822B))\n#define BIT_GET_BT_CH_8822B(x)                                                 \\\n\t(((x) >> BIT_SHIFT_BT_CH_8822B) & BIT_MASK_BT_CH_8822B)\n#define BIT_SET_BT_CH_8822B(x, v)                                              \\\n\t(BIT_CLEAR_BT_CH_8822B(x) | BIT_BT_CH_8822B(v))\n\n/* 2 REG_OBFF_CTRL_BASIC_8822B */\n#define BIT_OBFF_EN_V1_8822B BIT(31)\n\n#define BIT_SHIFT_OBFF_STATE_V1_8822B 28\n#define BIT_MASK_OBFF_STATE_V1_8822B 0x3\n#define BIT_OBFF_STATE_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_OBFF_STATE_V1_8822B) << BIT_SHIFT_OBFF_STATE_V1_8822B)\n#define BITS_OBFF_STATE_V1_8822B                                               \\\n\t(BIT_MASK_OBFF_STATE_V1_8822B << BIT_SHIFT_OBFF_STATE_V1_8822B)\n#define BIT_CLEAR_OBFF_STATE_V1_8822B(x) ((x) & (~BITS_OBFF_STATE_V1_8822B))\n#define BIT_GET_OBFF_STATE_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_OBFF_STATE_V1_8822B) & BIT_MASK_OBFF_STATE_V1_8822B)\n#define BIT_SET_OBFF_STATE_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_OBFF_STATE_V1_8822B(x) | BIT_OBFF_STATE_V1_8822B(v))\n\n#define BIT_OBFF_ACT_RXDMA_EN_8822B BIT(27)\n#define BIT_OBFF_BLOCK_INT_EN_8822B BIT(26)\n#define BIT_OBFF_AUTOACT_EN_8822B BIT(25)\n#define BIT_OBFF_AUTOIDLE_EN_8822B BIT(24)\n\n#define BIT_SHIFT_WAKE_MAX_PLS_8822B 20\n#define BIT_MASK_WAKE_MAX_PLS_8822B 0x7\n#define BIT_WAKE_MAX_PLS_8822B(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MAX_PLS_8822B) << BIT_SHIFT_WAKE_MAX_PLS_8822B)\n#define BITS_WAKE_MAX_PLS_8822B                                                \\\n\t(BIT_MASK_WAKE_MAX_PLS_8822B << BIT_SHIFT_WAKE_MAX_PLS_8822B)\n#define BIT_CLEAR_WAKE_MAX_PLS_8822B(x) ((x) & (~BITS_WAKE_MAX_PLS_8822B))\n#define BIT_GET_WAKE_MAX_PLS_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MAX_PLS_8822B) & BIT_MASK_WAKE_MAX_PLS_8822B)\n#define BIT_SET_WAKE_MAX_PLS_8822B(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MAX_PLS_8822B(x) | BIT_WAKE_MAX_PLS_8822B(v))\n\n#define BIT_SHIFT_WAKE_MIN_PLS_8822B 16\n#define BIT_MASK_WAKE_MIN_PLS_8822B 0x7\n#define BIT_WAKE_MIN_PLS_8822B(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MIN_PLS_8822B) << BIT_SHIFT_WAKE_MIN_PLS_8822B)\n#define BITS_WAKE_MIN_PLS_8822B                                                \\\n\t(BIT_MASK_WAKE_MIN_PLS_8822B << BIT_SHIFT_WAKE_MIN_PLS_8822B)\n#define BIT_CLEAR_WAKE_MIN_PLS_8822B(x) ((x) & (~BITS_WAKE_MIN_PLS_8822B))\n#define BIT_GET_WAKE_MIN_PLS_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MIN_PLS_8822B) & BIT_MASK_WAKE_MIN_PLS_8822B)\n#define BIT_SET_WAKE_MIN_PLS_8822B(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MIN_PLS_8822B(x) | BIT_WAKE_MIN_PLS_8822B(v))\n\n#define BIT_SHIFT_WAKE_MAX_F2F_8822B 12\n#define BIT_MASK_WAKE_MAX_F2F_8822B 0x7\n#define BIT_WAKE_MAX_F2F_8822B(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MAX_F2F_8822B) << BIT_SHIFT_WAKE_MAX_F2F_8822B)\n#define BITS_WAKE_MAX_F2F_8822B                                                \\\n\t(BIT_MASK_WAKE_MAX_F2F_8822B << BIT_SHIFT_WAKE_MAX_F2F_8822B)\n#define BIT_CLEAR_WAKE_MAX_F2F_8822B(x) ((x) & (~BITS_WAKE_MAX_F2F_8822B))\n#define BIT_GET_WAKE_MAX_F2F_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MAX_F2F_8822B) & BIT_MASK_WAKE_MAX_F2F_8822B)\n#define BIT_SET_WAKE_MAX_F2F_8822B(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MAX_F2F_8822B(x) | BIT_WAKE_MAX_F2F_8822B(v))\n\n#define BIT_SHIFT_WAKE_MIN_F2F_8822B 8\n#define BIT_MASK_WAKE_MIN_F2F_8822B 0x7\n#define BIT_WAKE_MIN_F2F_8822B(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MIN_F2F_8822B) << BIT_SHIFT_WAKE_MIN_F2F_8822B)\n#define BITS_WAKE_MIN_F2F_8822B                                                \\\n\t(BIT_MASK_WAKE_MIN_F2F_8822B << BIT_SHIFT_WAKE_MIN_F2F_8822B)\n#define BIT_CLEAR_WAKE_MIN_F2F_8822B(x) ((x) & (~BITS_WAKE_MIN_F2F_8822B))\n#define BIT_GET_WAKE_MIN_F2F_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MIN_F2F_8822B) & BIT_MASK_WAKE_MIN_F2F_8822B)\n#define BIT_SET_WAKE_MIN_F2F_8822B(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MIN_F2F_8822B(x) | BIT_WAKE_MIN_F2F_8822B(v))\n\n#define BIT_APP_CPU_ACT_V1_8822B BIT(3)\n#define BIT_APP_OBFF_V1_8822B BIT(2)\n#define BIT_APP_IDLE_V1_8822B BIT(1)\n#define BIT_APP_INIT_V1_8822B BIT(0)\n\n/* 2 REG_OBFF_CTRL2_TIMER_8822B */\n\n#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B 24\n#define BIT_MASK_RX_HIGH_TIMER_IDX_8822B 0x7\n#define BIT_RX_HIGH_TIMER_IDX_8822B(x)                                         \\\n\t(((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8822B)                              \\\n\t << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B)\n#define BITS_RX_HIGH_TIMER_IDX_8822B                                           \\\n\t(BIT_MASK_RX_HIGH_TIMER_IDX_8822B << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B)\n#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8822B(x)                                   \\\n\t((x) & (~BITS_RX_HIGH_TIMER_IDX_8822B))\n#define BIT_GET_RX_HIGH_TIMER_IDX_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B) &                          \\\n\t BIT_MASK_RX_HIGH_TIMER_IDX_8822B)\n#define BIT_SET_RX_HIGH_TIMER_IDX_8822B(x, v)                                  \\\n\t(BIT_CLEAR_RX_HIGH_TIMER_IDX_8822B(x) | BIT_RX_HIGH_TIMER_IDX_8822B(v))\n\n#define BIT_SHIFT_RX_MED_TIMER_IDX_8822B 16\n#define BIT_MASK_RX_MED_TIMER_IDX_8822B 0x7\n#define BIT_RX_MED_TIMER_IDX_8822B(x)                                          \\\n\t(((x) & BIT_MASK_RX_MED_TIMER_IDX_8822B)                               \\\n\t << BIT_SHIFT_RX_MED_TIMER_IDX_8822B)\n#define BITS_RX_MED_TIMER_IDX_8822B                                            \\\n\t(BIT_MASK_RX_MED_TIMER_IDX_8822B << BIT_SHIFT_RX_MED_TIMER_IDX_8822B)\n#define BIT_CLEAR_RX_MED_TIMER_IDX_8822B(x)                                    \\\n\t((x) & (~BITS_RX_MED_TIMER_IDX_8822B))\n#define BIT_GET_RX_MED_TIMER_IDX_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8822B) &                           \\\n\t BIT_MASK_RX_MED_TIMER_IDX_8822B)\n#define BIT_SET_RX_MED_TIMER_IDX_8822B(x, v)                                   \\\n\t(BIT_CLEAR_RX_MED_TIMER_IDX_8822B(x) | BIT_RX_MED_TIMER_IDX_8822B(v))\n\n#define BIT_SHIFT_RX_LOW_TIMER_IDX_8822B 8\n#define BIT_MASK_RX_LOW_TIMER_IDX_8822B 0x7\n#define BIT_RX_LOW_TIMER_IDX_8822B(x)                                          \\\n\t(((x) & BIT_MASK_RX_LOW_TIMER_IDX_8822B)                               \\\n\t << BIT_SHIFT_RX_LOW_TIMER_IDX_8822B)\n#define BITS_RX_LOW_TIMER_IDX_8822B                                            \\\n\t(BIT_MASK_RX_LOW_TIMER_IDX_8822B << BIT_SHIFT_RX_LOW_TIMER_IDX_8822B)\n#define BIT_CLEAR_RX_LOW_TIMER_IDX_8822B(x)                                    \\\n\t((x) & (~BITS_RX_LOW_TIMER_IDX_8822B))\n#define BIT_GET_RX_LOW_TIMER_IDX_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8822B) &                           \\\n\t BIT_MASK_RX_LOW_TIMER_IDX_8822B)\n#define BIT_SET_RX_LOW_TIMER_IDX_8822B(x, v)                                   \\\n\t(BIT_CLEAR_RX_LOW_TIMER_IDX_8822B(x) | BIT_RX_LOW_TIMER_IDX_8822B(v))\n\n#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B 0\n#define BIT_MASK_OBFF_INT_TIMER_IDX_8822B 0x7\n#define BIT_OBFF_INT_TIMER_IDX_8822B(x)                                        \\\n\t(((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8822B)                             \\\n\t << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B)\n#define BITS_OBFF_INT_TIMER_IDX_8822B                                          \\\n\t(BIT_MASK_OBFF_INT_TIMER_IDX_8822B                                     \\\n\t << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B)\n#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8822B(x)                                  \\\n\t((x) & (~BITS_OBFF_INT_TIMER_IDX_8822B))\n#define BIT_GET_OBFF_INT_TIMER_IDX_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B) &                         \\\n\t BIT_MASK_OBFF_INT_TIMER_IDX_8822B)\n#define BIT_SET_OBFF_INT_TIMER_IDX_8822B(x, v)                                 \\\n\t(BIT_CLEAR_OBFF_INT_TIMER_IDX_8822B(x) |                               \\\n\t BIT_OBFF_INT_TIMER_IDX_8822B(v))\n\n/* 2 REG_LTR_CTRL_BASIC_8822B */\n#define BIT_LTR_EN_V1_8822B BIT(31)\n#define BIT_LTR_HW_EN_V1_8822B BIT(30)\n#define BIT_LRT_ACT_CTS_EN_8822B BIT(29)\n#define BIT_LTR_ACT_RXPKT_EN_8822B BIT(28)\n#define BIT_LTR_ACT_RXDMA_EN_8822B BIT(27)\n#define BIT_LTR_IDLE_NO_SNOOP_8822B BIT(26)\n#define BIT_SPDUP_MGTPKT_8822B BIT(25)\n#define BIT_RX_AGG_EN_8822B BIT(24)\n#define BIT_APP_LTR_ACT_8822B BIT(23)\n#define BIT_APP_LTR_IDLE_8822B BIT(22)\n\n#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B 20\n#define BIT_MASK_HIGH_RATE_TRIG_SEL_8822B 0x3\n#define BIT_HIGH_RATE_TRIG_SEL_8822B(x)                                        \\\n\t(((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822B)                             \\\n\t << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B)\n#define BITS_HIGH_RATE_TRIG_SEL_8822B                                          \\\n\t(BIT_MASK_HIGH_RATE_TRIG_SEL_8822B                                     \\\n\t << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B)\n#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822B(x)                                  \\\n\t((x) & (~BITS_HIGH_RATE_TRIG_SEL_8822B))\n#define BIT_GET_HIGH_RATE_TRIG_SEL_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B) &                         \\\n\t BIT_MASK_HIGH_RATE_TRIG_SEL_8822B)\n#define BIT_SET_HIGH_RATE_TRIG_SEL_8822B(x, v)                                 \\\n\t(BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822B(x) |                               \\\n\t BIT_HIGH_RATE_TRIG_SEL_8822B(v))\n\n#define BIT_SHIFT_MED_RATE_TRIG_SEL_8822B 18\n#define BIT_MASK_MED_RATE_TRIG_SEL_8822B 0x3\n#define BIT_MED_RATE_TRIG_SEL_8822B(x)                                         \\\n\t(((x) & BIT_MASK_MED_RATE_TRIG_SEL_8822B)                              \\\n\t << BIT_SHIFT_MED_RATE_TRIG_SEL_8822B)\n#define BITS_MED_RATE_TRIG_SEL_8822B                                           \\\n\t(BIT_MASK_MED_RATE_TRIG_SEL_8822B << BIT_SHIFT_MED_RATE_TRIG_SEL_8822B)\n#define BIT_CLEAR_MED_RATE_TRIG_SEL_8822B(x)                                   \\\n\t((x) & (~BITS_MED_RATE_TRIG_SEL_8822B))\n#define BIT_GET_MED_RATE_TRIG_SEL_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8822B) &                          \\\n\t BIT_MASK_MED_RATE_TRIG_SEL_8822B)\n#define BIT_SET_MED_RATE_TRIG_SEL_8822B(x, v)                                  \\\n\t(BIT_CLEAR_MED_RATE_TRIG_SEL_8822B(x) | BIT_MED_RATE_TRIG_SEL_8822B(v))\n\n#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B 16\n#define BIT_MASK_LOW_RATE_TRIG_SEL_8822B 0x3\n#define BIT_LOW_RATE_TRIG_SEL_8822B(x)                                         \\\n\t(((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8822B)                              \\\n\t << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B)\n#define BITS_LOW_RATE_TRIG_SEL_8822B                                           \\\n\t(BIT_MASK_LOW_RATE_TRIG_SEL_8822B << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B)\n#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8822B(x)                                   \\\n\t((x) & (~BITS_LOW_RATE_TRIG_SEL_8822B))\n#define BIT_GET_LOW_RATE_TRIG_SEL_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B) &                          \\\n\t BIT_MASK_LOW_RATE_TRIG_SEL_8822B)\n#define BIT_SET_LOW_RATE_TRIG_SEL_8822B(x, v)                                  \\\n\t(BIT_CLEAR_LOW_RATE_TRIG_SEL_8822B(x) | BIT_LOW_RATE_TRIG_SEL_8822B(v))\n\n#define BIT_SHIFT_HIGH_RATE_BD_IDX_8822B 8\n#define BIT_MASK_HIGH_RATE_BD_IDX_8822B 0x7f\n#define BIT_HIGH_RATE_BD_IDX_8822B(x)                                          \\\n\t(((x) & BIT_MASK_HIGH_RATE_BD_IDX_8822B)                               \\\n\t << BIT_SHIFT_HIGH_RATE_BD_IDX_8822B)\n#define BITS_HIGH_RATE_BD_IDX_8822B                                            \\\n\t(BIT_MASK_HIGH_RATE_BD_IDX_8822B << BIT_SHIFT_HIGH_RATE_BD_IDX_8822B)\n#define BIT_CLEAR_HIGH_RATE_BD_IDX_8822B(x)                                    \\\n\t((x) & (~BITS_HIGH_RATE_BD_IDX_8822B))\n#define BIT_GET_HIGH_RATE_BD_IDX_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8822B) &                           \\\n\t BIT_MASK_HIGH_RATE_BD_IDX_8822B)\n#define BIT_SET_HIGH_RATE_BD_IDX_8822B(x, v)                                   \\\n\t(BIT_CLEAR_HIGH_RATE_BD_IDX_8822B(x) | BIT_HIGH_RATE_BD_IDX_8822B(v))\n\n#define BIT_SHIFT_LOW_RATE_BD_IDX_8822B 0\n#define BIT_MASK_LOW_RATE_BD_IDX_8822B 0x7f\n#define BIT_LOW_RATE_BD_IDX_8822B(x)                                           \\\n\t(((x) & BIT_MASK_LOW_RATE_BD_IDX_8822B)                                \\\n\t << BIT_SHIFT_LOW_RATE_BD_IDX_8822B)\n#define BITS_LOW_RATE_BD_IDX_8822B                                             \\\n\t(BIT_MASK_LOW_RATE_BD_IDX_8822B << BIT_SHIFT_LOW_RATE_BD_IDX_8822B)\n#define BIT_CLEAR_LOW_RATE_BD_IDX_8822B(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8822B))\n#define BIT_GET_LOW_RATE_BD_IDX_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8822B) &                            \\\n\t BIT_MASK_LOW_RATE_BD_IDX_8822B)\n#define BIT_SET_LOW_RATE_BD_IDX_8822B(x, v)                                    \\\n\t(BIT_CLEAR_LOW_RATE_BD_IDX_8822B(x) | BIT_LOW_RATE_BD_IDX_8822B(v))\n\n/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8822B */\n\n#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B 24\n#define BIT_MASK_RX_EMPTY_TIMER_IDX_8822B 0x7\n#define BIT_RX_EMPTY_TIMER_IDX_8822B(x)                                        \\\n\t(((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822B)                             \\\n\t << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B)\n#define BITS_RX_EMPTY_TIMER_IDX_8822B                                          \\\n\t(BIT_MASK_RX_EMPTY_TIMER_IDX_8822B                                     \\\n\t << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B)\n#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822B(x)                                  \\\n\t((x) & (~BITS_RX_EMPTY_TIMER_IDX_8822B))\n#define BIT_GET_RX_EMPTY_TIMER_IDX_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B) &                         \\\n\t BIT_MASK_RX_EMPTY_TIMER_IDX_8822B)\n#define BIT_SET_RX_EMPTY_TIMER_IDX_8822B(x, v)                                 \\\n\t(BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822B(x) |                               \\\n\t BIT_RX_EMPTY_TIMER_IDX_8822B(v))\n\n#define BIT_SHIFT_RX_AFULL_TH_IDX_8822B 20\n#define BIT_MASK_RX_AFULL_TH_IDX_8822B 0x7\n#define BIT_RX_AFULL_TH_IDX_8822B(x)                                           \\\n\t(((x) & BIT_MASK_RX_AFULL_TH_IDX_8822B)                                \\\n\t << BIT_SHIFT_RX_AFULL_TH_IDX_8822B)\n#define BITS_RX_AFULL_TH_IDX_8822B                                             \\\n\t(BIT_MASK_RX_AFULL_TH_IDX_8822B << BIT_SHIFT_RX_AFULL_TH_IDX_8822B)\n#define BIT_CLEAR_RX_AFULL_TH_IDX_8822B(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8822B))\n#define BIT_GET_RX_AFULL_TH_IDX_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8822B) &                            \\\n\t BIT_MASK_RX_AFULL_TH_IDX_8822B)\n#define BIT_SET_RX_AFULL_TH_IDX_8822B(x, v)                                    \\\n\t(BIT_CLEAR_RX_AFULL_TH_IDX_8822B(x) | BIT_RX_AFULL_TH_IDX_8822B(v))\n\n#define BIT_SHIFT_RX_HIGH_TH_IDX_8822B 16\n#define BIT_MASK_RX_HIGH_TH_IDX_8822B 0x7\n#define BIT_RX_HIGH_TH_IDX_8822B(x)                                            \\\n\t(((x) & BIT_MASK_RX_HIGH_TH_IDX_8822B)                                 \\\n\t << BIT_SHIFT_RX_HIGH_TH_IDX_8822B)\n#define BITS_RX_HIGH_TH_IDX_8822B                                              \\\n\t(BIT_MASK_RX_HIGH_TH_IDX_8822B << BIT_SHIFT_RX_HIGH_TH_IDX_8822B)\n#define BIT_CLEAR_RX_HIGH_TH_IDX_8822B(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8822B))\n#define BIT_GET_RX_HIGH_TH_IDX_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8822B) &                             \\\n\t BIT_MASK_RX_HIGH_TH_IDX_8822B)\n#define BIT_SET_RX_HIGH_TH_IDX_8822B(x, v)                                     \\\n\t(BIT_CLEAR_RX_HIGH_TH_IDX_8822B(x) | BIT_RX_HIGH_TH_IDX_8822B(v))\n\n#define BIT_SHIFT_RX_MED_TH_IDX_8822B 12\n#define BIT_MASK_RX_MED_TH_IDX_8822B 0x7\n#define BIT_RX_MED_TH_IDX_8822B(x)                                             \\\n\t(((x) & BIT_MASK_RX_MED_TH_IDX_8822B) << BIT_SHIFT_RX_MED_TH_IDX_8822B)\n#define BITS_RX_MED_TH_IDX_8822B                                               \\\n\t(BIT_MASK_RX_MED_TH_IDX_8822B << BIT_SHIFT_RX_MED_TH_IDX_8822B)\n#define BIT_CLEAR_RX_MED_TH_IDX_8822B(x) ((x) & (~BITS_RX_MED_TH_IDX_8822B))\n#define BIT_GET_RX_MED_TH_IDX_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_RX_MED_TH_IDX_8822B) & BIT_MASK_RX_MED_TH_IDX_8822B)\n#define BIT_SET_RX_MED_TH_IDX_8822B(x, v)                                      \\\n\t(BIT_CLEAR_RX_MED_TH_IDX_8822B(x) | BIT_RX_MED_TH_IDX_8822B(v))\n\n#define BIT_SHIFT_RX_LOW_TH_IDX_8822B 8\n#define BIT_MASK_RX_LOW_TH_IDX_8822B 0x7\n#define BIT_RX_LOW_TH_IDX_8822B(x)                                             \\\n\t(((x) & BIT_MASK_RX_LOW_TH_IDX_8822B) << BIT_SHIFT_RX_LOW_TH_IDX_8822B)\n#define BITS_RX_LOW_TH_IDX_8822B                                               \\\n\t(BIT_MASK_RX_LOW_TH_IDX_8822B << BIT_SHIFT_RX_LOW_TH_IDX_8822B)\n#define BIT_CLEAR_RX_LOW_TH_IDX_8822B(x) ((x) & (~BITS_RX_LOW_TH_IDX_8822B))\n#define BIT_GET_RX_LOW_TH_IDX_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8822B) & BIT_MASK_RX_LOW_TH_IDX_8822B)\n#define BIT_SET_RX_LOW_TH_IDX_8822B(x, v)                                      \\\n\t(BIT_CLEAR_RX_LOW_TH_IDX_8822B(x) | BIT_RX_LOW_TH_IDX_8822B(v))\n\n#define BIT_SHIFT_LTR_SPACE_IDX_8822B 4\n#define BIT_MASK_LTR_SPACE_IDX_8822B 0x3\n#define BIT_LTR_SPACE_IDX_8822B(x)                                             \\\n\t(((x) & BIT_MASK_LTR_SPACE_IDX_8822B) << BIT_SHIFT_LTR_SPACE_IDX_8822B)\n#define BITS_LTR_SPACE_IDX_8822B                                               \\\n\t(BIT_MASK_LTR_SPACE_IDX_8822B << BIT_SHIFT_LTR_SPACE_IDX_8822B)\n#define BIT_CLEAR_LTR_SPACE_IDX_8822B(x) ((x) & (~BITS_LTR_SPACE_IDX_8822B))\n#define BIT_GET_LTR_SPACE_IDX_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_LTR_SPACE_IDX_8822B) & BIT_MASK_LTR_SPACE_IDX_8822B)\n#define BIT_SET_LTR_SPACE_IDX_8822B(x, v)                                      \\\n\t(BIT_CLEAR_LTR_SPACE_IDX_8822B(x) | BIT_LTR_SPACE_IDX_8822B(v))\n\n#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B 0\n#define BIT_MASK_LTR_IDLE_TIMER_IDX_8822B 0x7\n#define BIT_LTR_IDLE_TIMER_IDX_8822B(x)                                        \\\n\t(((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822B)                             \\\n\t << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B)\n#define BITS_LTR_IDLE_TIMER_IDX_8822B                                          \\\n\t(BIT_MASK_LTR_IDLE_TIMER_IDX_8822B                                     \\\n\t << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B)\n#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822B(x)                                  \\\n\t((x) & (~BITS_LTR_IDLE_TIMER_IDX_8822B))\n#define BIT_GET_LTR_IDLE_TIMER_IDX_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B) &                         \\\n\t BIT_MASK_LTR_IDLE_TIMER_IDX_8822B)\n#define BIT_SET_LTR_IDLE_TIMER_IDX_8822B(x, v)                                 \\\n\t(BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822B(x) |                               \\\n\t BIT_LTR_IDLE_TIMER_IDX_8822B(v))\n\n/* 2 REG_LTR_IDLE_LATENCY_V1_8822B */\n\n#define BIT_SHIFT_LTR_IDLE_L_8822B 0\n#define BIT_MASK_LTR_IDLE_L_8822B 0xffffffffL\n#define BIT_LTR_IDLE_L_8822B(x)                                                \\\n\t(((x) & BIT_MASK_LTR_IDLE_L_8822B) << BIT_SHIFT_LTR_IDLE_L_8822B)\n#define BITS_LTR_IDLE_L_8822B                                                  \\\n\t(BIT_MASK_LTR_IDLE_L_8822B << BIT_SHIFT_LTR_IDLE_L_8822B)\n#define BIT_CLEAR_LTR_IDLE_L_8822B(x) ((x) & (~BITS_LTR_IDLE_L_8822B))\n#define BIT_GET_LTR_IDLE_L_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_LTR_IDLE_L_8822B) & BIT_MASK_LTR_IDLE_L_8822B)\n#define BIT_SET_LTR_IDLE_L_8822B(x, v)                                         \\\n\t(BIT_CLEAR_LTR_IDLE_L_8822B(x) | BIT_LTR_IDLE_L_8822B(v))\n\n/* 2 REG_LTR_ACTIVE_LATENCY_V1_8822B */\n\n#define BIT_SHIFT_LTR_ACT_L_8822B 0\n#define BIT_MASK_LTR_ACT_L_8822B 0xffffffffL\n#define BIT_LTR_ACT_L_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_LTR_ACT_L_8822B) << BIT_SHIFT_LTR_ACT_L_8822B)\n#define BITS_LTR_ACT_L_8822B                                                   \\\n\t(BIT_MASK_LTR_ACT_L_8822B << BIT_SHIFT_LTR_ACT_L_8822B)\n#define BIT_CLEAR_LTR_ACT_L_8822B(x) ((x) & (~BITS_LTR_ACT_L_8822B))\n#define BIT_GET_LTR_ACT_L_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_LTR_ACT_L_8822B) & BIT_MASK_LTR_ACT_L_8822B)\n#define BIT_SET_LTR_ACT_L_8822B(x, v)                                          \\\n\t(BIT_CLEAR_LTR_ACT_L_8822B(x) | BIT_LTR_ACT_L_8822B(v))\n\n/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822B */\n#define BIT_APPEND_MACID_IN_RESP_EN_8822B BIT(50)\n#define BIT_ADDR2_MATCH_EN_8822B BIT(49)\n#define BIT_ANTTRN_EN_8822B BIT(48)\n\n#define BIT_SHIFT_TRAIN_STA_ADDR_8822B 0\n#define BIT_MASK_TRAIN_STA_ADDR_8822B 0xffffffffffffL\n#define BIT_TRAIN_STA_ADDR_8822B(x)                                            \\\n\t(((x) & BIT_MASK_TRAIN_STA_ADDR_8822B)                                 \\\n\t << BIT_SHIFT_TRAIN_STA_ADDR_8822B)\n#define BITS_TRAIN_STA_ADDR_8822B                                              \\\n\t(BIT_MASK_TRAIN_STA_ADDR_8822B << BIT_SHIFT_TRAIN_STA_ADDR_8822B)\n#define BIT_CLEAR_TRAIN_STA_ADDR_8822B(x) ((x) & (~BITS_TRAIN_STA_ADDR_8822B))\n#define BIT_GET_TRAIN_STA_ADDR_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8822B) &                             \\\n\t BIT_MASK_TRAIN_STA_ADDR_8822B)\n#define BIT_SET_TRAIN_STA_ADDR_8822B(x, v)                                     \\\n\t(BIT_CLEAR_TRAIN_STA_ADDR_8822B(x) | BIT_TRAIN_STA_ADDR_8822B(v))\n\n/* 2 REG_RSVD_0X7B4_8822B */\n\n/* 2 REG_WMAC_PKTCNT_RWD_8822B */\n\n#define BIT_SHIFT_PKTCNT_BSSIDMAP_8822B 4\n#define BIT_MASK_PKTCNT_BSSIDMAP_8822B 0xf\n#define BIT_PKTCNT_BSSIDMAP_8822B(x)                                           \\\n\t(((x) & BIT_MASK_PKTCNT_BSSIDMAP_8822B)                                \\\n\t << BIT_SHIFT_PKTCNT_BSSIDMAP_8822B)\n#define BITS_PKTCNT_BSSIDMAP_8822B                                             \\\n\t(BIT_MASK_PKTCNT_BSSIDMAP_8822B << BIT_SHIFT_PKTCNT_BSSIDMAP_8822B)\n#define BIT_CLEAR_PKTCNT_BSSIDMAP_8822B(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8822B))\n#define BIT_GET_PKTCNT_BSSIDMAP_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8822B) &                            \\\n\t BIT_MASK_PKTCNT_BSSIDMAP_8822B)\n#define BIT_SET_PKTCNT_BSSIDMAP_8822B(x, v)                                    \\\n\t(BIT_CLEAR_PKTCNT_BSSIDMAP_8822B(x) | BIT_PKTCNT_BSSIDMAP_8822B(v))\n\n#define BIT_PKTCNT_CNTRST_8822B BIT(1)\n#define BIT_PKTCNT_CNTEN_8822B BIT(0)\n\n/* 2 REG_WMAC_PKTCNT_CTRL_8822B */\n#define BIT_WMAC_PKTCNT_TRST_8822B BIT(9)\n#define BIT_WMAC_PKTCNT_FEN_8822B BIT(8)\n\n#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B 0\n#define BIT_MASK_WMAC_PKTCNT_CFGAD_8822B 0xff\n#define BIT_WMAC_PKTCNT_CFGAD_8822B(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822B)                              \\\n\t << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B)\n#define BITS_WMAC_PKTCNT_CFGAD_8822B                                           \\\n\t(BIT_MASK_WMAC_PKTCNT_CFGAD_8822B << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B)\n#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822B(x)                                   \\\n\t((x) & (~BITS_WMAC_PKTCNT_CFGAD_8822B))\n#define BIT_GET_WMAC_PKTCNT_CFGAD_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B) &                          \\\n\t BIT_MASK_WMAC_PKTCNT_CFGAD_8822B)\n#define BIT_SET_WMAC_PKTCNT_CFGAD_8822B(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822B(x) | BIT_WMAC_PKTCNT_CFGAD_8822B(v))\n\n/* 2 REG_IQ_DUMP_8822B */\n\n#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B (64 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B 0xffffffffL\n#define BIT_R_WMAC_MATCH_REF_MAC_8822B(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B)                           \\\n\t << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B)\n#define BITS_R_WMAC_MATCH_REF_MAC_8822B                                        \\\n\t(BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B                                   \\\n\t << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B)\n#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8822B(x)                                \\\n\t((x) & (~BITS_R_WMAC_MATCH_REF_MAC_8822B))\n#define BIT_GET_R_WMAC_MATCH_REF_MAC_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B) &                       \\\n\t BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B)\n#define BIT_SET_R_WMAC_MATCH_REF_MAC_8822B(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8822B(x) |                             \\\n\t BIT_R_WMAC_MATCH_REF_MAC_8822B(v))\n\n#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_WMAC_MASK_LA_MAC_8822B 0xffffffffL\n#define BIT_R_WMAC_MASK_LA_MAC_8822B(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8822B)                             \\\n\t << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B)\n#define BITS_R_WMAC_MASK_LA_MAC_8822B                                          \\\n\t(BIT_MASK_R_WMAC_MASK_LA_MAC_8822B                                     \\\n\t << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B)\n#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_8822B(x)                                  \\\n\t((x) & (~BITS_R_WMAC_MASK_LA_MAC_8822B))\n#define BIT_GET_R_WMAC_MASK_LA_MAC_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B) &                         \\\n\t BIT_MASK_R_WMAC_MASK_LA_MAC_8822B)\n#define BIT_SET_R_WMAC_MASK_LA_MAC_8822B(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_MASK_LA_MAC_8822B(x) |                               \\\n\t BIT_R_WMAC_MASK_LA_MAC_8822B(v))\n\n#define BIT_SHIFT_DUMP_OK_ADDR_8822B 16\n#define BIT_MASK_DUMP_OK_ADDR_8822B 0xffff\n#define BIT_DUMP_OK_ADDR_8822B(x)                                              \\\n\t(((x) & BIT_MASK_DUMP_OK_ADDR_8822B) << BIT_SHIFT_DUMP_OK_ADDR_8822B)\n#define BITS_DUMP_OK_ADDR_8822B                                                \\\n\t(BIT_MASK_DUMP_OK_ADDR_8822B << BIT_SHIFT_DUMP_OK_ADDR_8822B)\n#define BIT_CLEAR_DUMP_OK_ADDR_8822B(x) ((x) & (~BITS_DUMP_OK_ADDR_8822B))\n#define BIT_GET_DUMP_OK_ADDR_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_DUMP_OK_ADDR_8822B) & BIT_MASK_DUMP_OK_ADDR_8822B)\n#define BIT_SET_DUMP_OK_ADDR_8822B(x, v)                                       \\\n\t(BIT_CLEAR_DUMP_OK_ADDR_8822B(x) | BIT_DUMP_OK_ADDR_8822B(v))\n\n#define BIT_SHIFT_R_TRIG_TIME_SEL_8822B 8\n#define BIT_MASK_R_TRIG_TIME_SEL_8822B 0x7f\n#define BIT_R_TRIG_TIME_SEL_8822B(x)                                           \\\n\t(((x) & BIT_MASK_R_TRIG_TIME_SEL_8822B)                                \\\n\t << BIT_SHIFT_R_TRIG_TIME_SEL_8822B)\n#define BITS_R_TRIG_TIME_SEL_8822B                                             \\\n\t(BIT_MASK_R_TRIG_TIME_SEL_8822B << BIT_SHIFT_R_TRIG_TIME_SEL_8822B)\n#define BIT_CLEAR_R_TRIG_TIME_SEL_8822B(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8822B))\n#define BIT_GET_R_TRIG_TIME_SEL_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8822B) &                            \\\n\t BIT_MASK_R_TRIG_TIME_SEL_8822B)\n#define BIT_SET_R_TRIG_TIME_SEL_8822B(x, v)                                    \\\n\t(BIT_CLEAR_R_TRIG_TIME_SEL_8822B(x) | BIT_R_TRIG_TIME_SEL_8822B(v))\n\n#define BIT_SHIFT_R_MAC_TRIG_SEL_8822B 6\n#define BIT_MASK_R_MAC_TRIG_SEL_8822B 0x3\n#define BIT_R_MAC_TRIG_SEL_8822B(x)                                            \\\n\t(((x) & BIT_MASK_R_MAC_TRIG_SEL_8822B)                                 \\\n\t << BIT_SHIFT_R_MAC_TRIG_SEL_8822B)\n#define BITS_R_MAC_TRIG_SEL_8822B                                              \\\n\t(BIT_MASK_R_MAC_TRIG_SEL_8822B << BIT_SHIFT_R_MAC_TRIG_SEL_8822B)\n#define BIT_CLEAR_R_MAC_TRIG_SEL_8822B(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8822B))\n#define BIT_GET_R_MAC_TRIG_SEL_8822B(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8822B) &                             \\\n\t BIT_MASK_R_MAC_TRIG_SEL_8822B)\n#define BIT_SET_R_MAC_TRIG_SEL_8822B(x, v)                                     \\\n\t(BIT_CLEAR_R_MAC_TRIG_SEL_8822B(x) | BIT_R_MAC_TRIG_SEL_8822B(v))\n\n#define BIT_MAC_TRIG_REG_8822B BIT(5)\n\n#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B 3\n#define BIT_MASK_R_LEVEL_PULSE_SEL_8822B 0x3\n#define BIT_R_LEVEL_PULSE_SEL_8822B(x)                                         \\\n\t(((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8822B)                              \\\n\t << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B)\n#define BITS_R_LEVEL_PULSE_SEL_8822B                                           \\\n\t(BIT_MASK_R_LEVEL_PULSE_SEL_8822B << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B)\n#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8822B(x)                                   \\\n\t((x) & (~BITS_R_LEVEL_PULSE_SEL_8822B))\n#define BIT_GET_R_LEVEL_PULSE_SEL_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B) &                          \\\n\t BIT_MASK_R_LEVEL_PULSE_SEL_8822B)\n#define BIT_SET_R_LEVEL_PULSE_SEL_8822B(x, v)                                  \\\n\t(BIT_CLEAR_R_LEVEL_PULSE_SEL_8822B(x) | BIT_R_LEVEL_PULSE_SEL_8822B(v))\n\n#define BIT_EN_LA_MAC_8822B BIT(2)\n#define BIT_R_EN_IQDUMP_8822B BIT(1)\n#define BIT_R_IQDATA_DUMP_8822B BIT(0)\n\n/* 2 REG_WMAC_FTM_CTL_8822B */\n#define BIT_RXFTM_TXACK_SC_8822B BIT(6)\n#define BIT_RXFTM_TXACK_BW_8822B BIT(5)\n#define BIT_RXFTM_EN_8822B BIT(3)\n#define BIT_RXFTMREQ_BYDRV_8822B BIT(2)\n#define BIT_RXFTMREQ_EN_8822B BIT(1)\n#define BIT_FTM_EN_8822B BIT(0)\n\n/* 2 REG_WMAC_IQ_MDPK_FUNC_8822B */\n\n/* 2 REG_WMAC_OPTION_FUNCTION_8822B */\n\n#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B (64 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_WMAC_RX_FIL_LEN_8822B 0xffff\n#define BIT_R_WMAC_RX_FIL_LEN_8822B(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8822B)                              \\\n\t << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B)\n#define BITS_R_WMAC_RX_FIL_LEN_8822B                                           \\\n\t(BIT_MASK_R_WMAC_RX_FIL_LEN_8822B << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B)\n#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_8822B(x)                                   \\\n\t((x) & (~BITS_R_WMAC_RX_FIL_LEN_8822B))\n#define BIT_GET_R_WMAC_RX_FIL_LEN_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B) &                          \\\n\t BIT_MASK_R_WMAC_RX_FIL_LEN_8822B)\n#define BIT_SET_R_WMAC_RX_FIL_LEN_8822B(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_RX_FIL_LEN_8822B(x) | BIT_R_WMAC_RX_FIL_LEN_8822B(v))\n\n#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B (56 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B 0xff\n#define BIT_R_WMAC_RXFIFO_FULL_TH_8822B(x)                                     \\\n\t(((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B)                          \\\n\t << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B)\n#define BITS_R_WMAC_RXFIFO_FULL_TH_8822B                                       \\\n\t(BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B                                  \\\n\t << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B)\n#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8822B(x)                               \\\n\t((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_8822B))\n#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8822B(x)                                 \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B) &                      \\\n\t BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B)\n#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_8822B(x, v)                              \\\n\t(BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8822B(x) |                            \\\n\t BIT_R_WMAC_RXFIFO_FULL_TH_8822B(v))\n\n#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_8822B BIT(55)\n#define BIT_R_WMAC_RXRST_DLY_8822B BIT(54)\n#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_8822B BIT(53)\n#define BIT_R_WMAC_SRCH_TXRPT_UA1_8822B BIT(52)\n#define BIT_R_WMAC_SRCH_TXRPT_TYPE_8822B BIT(51)\n#define BIT_R_WMAC_NDP_RST_8822B BIT(50)\n#define BIT_R_WMAC_POWINT_EN_8822B BIT(49)\n#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_8822B BIT(48)\n#define BIT_R_WMAC_SRCH_TXRPT_MID_8822B BIT(47)\n#define BIT_R_WMAC_PFIN_TOEN_8822B BIT(46)\n#define BIT_R_WMAC_FIL_SECERR_8822B BIT(45)\n#define BIT_R_WMAC_FIL_CTLPKTLEN_8822B BIT(44)\n#define BIT_R_WMAC_FIL_FCTYPE_8822B BIT(43)\n#define BIT_R_WMAC_FIL_FCPROVER_8822B BIT(42)\n#define BIT_R_WMAC_PHYSTS_SNIF_8822B BIT(41)\n#define BIT_R_WMAC_PHYSTS_PLCP_8822B BIT(40)\n#define BIT_R_MAC_TCR_VBONF_RD_8822B BIT(39)\n#define BIT_R_WMAC_TCR_MPAR_NDP_8822B BIT(38)\n#define BIT_R_WMAC_NDP_FILTER_8822B BIT(37)\n#define BIT_R_WMAC_RXLEN_SEL_8822B BIT(36)\n#define BIT_R_WMAC_RXLEN_SEL1_8822B BIT(35)\n#define BIT_R_OFDM_FILTER_8822B BIT(34)\n#define BIT_R_WMAC_CHK_OFDM_LEN_8822B BIT(33)\n#define BIT_R_WMAC_CHK_CCK_LEN_8822B BIT(32)\n\n#define BIT_SHIFT_R_OFDM_LEN_8822B 26\n#define BIT_MASK_R_OFDM_LEN_8822B 0x3f\n#define BIT_R_OFDM_LEN_8822B(x)                                                \\\n\t(((x) & BIT_MASK_R_OFDM_LEN_8822B) << BIT_SHIFT_R_OFDM_LEN_8822B)\n#define BITS_R_OFDM_LEN_8822B                                                  \\\n\t(BIT_MASK_R_OFDM_LEN_8822B << BIT_SHIFT_R_OFDM_LEN_8822B)\n#define BIT_CLEAR_R_OFDM_LEN_8822B(x) ((x) & (~BITS_R_OFDM_LEN_8822B))\n#define BIT_GET_R_OFDM_LEN_8822B(x)                                            \\\n\t(((x) >> BIT_SHIFT_R_OFDM_LEN_8822B) & BIT_MASK_R_OFDM_LEN_8822B)\n#define BIT_SET_R_OFDM_LEN_8822B(x, v)                                         \\\n\t(BIT_CLEAR_R_OFDM_LEN_8822B(x) | BIT_R_OFDM_LEN_8822B(v))\n\n#define BIT_SHIFT_R_CCK_LEN_8822B 0\n#define BIT_MASK_R_CCK_LEN_8822B 0xffff\n#define BIT_R_CCK_LEN_8822B(x)                                                 \\\n\t(((x) & BIT_MASK_R_CCK_LEN_8822B) << BIT_SHIFT_R_CCK_LEN_8822B)\n#define BITS_R_CCK_LEN_8822B                                                   \\\n\t(BIT_MASK_R_CCK_LEN_8822B << BIT_SHIFT_R_CCK_LEN_8822B)\n#define BIT_CLEAR_R_CCK_LEN_8822B(x) ((x) & (~BITS_R_CCK_LEN_8822B))\n#define BIT_GET_R_CCK_LEN_8822B(x)                                             \\\n\t(((x) >> BIT_SHIFT_R_CCK_LEN_8822B) & BIT_MASK_R_CCK_LEN_8822B)\n#define BIT_SET_R_CCK_LEN_8822B(x, v)                                          \\\n\t(BIT_CLEAR_R_CCK_LEN_8822B(x) | BIT_R_CCK_LEN_8822B(v))\n\n/* 2 REG_RX_FILTER_FUNCTION_8822B */\n#define BIT_R_WMAC_MHRDDY_LATCH_8822B BIT(14)\n#define BIT_R_WMAC_MHRDDY_CLR_8822B BIT(13)\n#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8822B BIT(12)\n#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU_8822B BIT(11)\n#define BIT_R_CHK_DELIMIT_LEN_8822B BIT(10)\n#define BIT_R_REAPTER_ADDR_MATCH_8822B BIT(9)\n#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8822B BIT(8)\n#define BIT_R_LATCH_MACHRDY_8822B BIT(7)\n#define BIT_R_WMAC_RXFIL_REND_8822B BIT(6)\n#define BIT_R_WMAC_MPDURDY_CLR_8822B BIT(5)\n#define BIT_R_WMAC_CLRRXSEC_8822B BIT(4)\n#define BIT_R_WMAC_RXFIL_RDEL_8822B BIT(3)\n#define BIT_R_WMAC_RXFIL_FCSE_8822B BIT(2)\n#define BIT_R_WMAC_RXFIL_MESH_DEL_8822B BIT(1)\n#define BIT_R_WMAC_RXFIL_MASKM_8822B BIT(0)\n\n/* 2 REG_NDP_SIG_8822B */\n\n#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B 0\n#define BIT_MASK_R_WMAC_TXNDP_SIGB_8822B 0x1fffff\n#define BIT_R_WMAC_TXNDP_SIGB_8822B(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822B)                              \\\n\t << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B)\n#define BITS_R_WMAC_TXNDP_SIGB_8822B                                           \\\n\t(BIT_MASK_R_WMAC_TXNDP_SIGB_8822B << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B)\n#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822B(x)                                   \\\n\t((x) & (~BITS_R_WMAC_TXNDP_SIGB_8822B))\n#define BIT_GET_R_WMAC_TXNDP_SIGB_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B) &                          \\\n\t BIT_MASK_R_WMAC_TXNDP_SIGB_8822B)\n#define BIT_SET_R_WMAC_TXNDP_SIGB_8822B(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822B(x) | BIT_R_WMAC_TXNDP_SIGB_8822B(v))\n\n/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8822B */\n\n#define BIT_SHIFT_R_MAC_DEBUG_8822B (32 & CPU_OPT_WIDTH)\n#define BIT_MASK_R_MAC_DEBUG_8822B 0xffffffffL\n#define BIT_R_MAC_DEBUG_8822B(x)                                               \\\n\t(((x) & BIT_MASK_R_MAC_DEBUG_8822B) << BIT_SHIFT_R_MAC_DEBUG_8822B)\n#define BITS_R_MAC_DEBUG_8822B                                                 \\\n\t(BIT_MASK_R_MAC_DEBUG_8822B << BIT_SHIFT_R_MAC_DEBUG_8822B)\n#define BIT_CLEAR_R_MAC_DEBUG_8822B(x) ((x) & (~BITS_R_MAC_DEBUG_8822B))\n#define BIT_GET_R_MAC_DEBUG_8822B(x)                                           \\\n\t(((x) >> BIT_SHIFT_R_MAC_DEBUG_8822B) & BIT_MASK_R_MAC_DEBUG_8822B)\n#define BIT_SET_R_MAC_DEBUG_8822B(x, v)                                        \\\n\t(BIT_CLEAR_R_MAC_DEBUG_8822B(x) | BIT_R_MAC_DEBUG_8822B(v))\n\n#define BIT_SHIFT_R_MAC_DBG_SHIFT_8822B 8\n#define BIT_MASK_R_MAC_DBG_SHIFT_8822B 0x7\n#define BIT_R_MAC_DBG_SHIFT_8822B(x)                                           \\\n\t(((x) & BIT_MASK_R_MAC_DBG_SHIFT_8822B)                                \\\n\t << BIT_SHIFT_R_MAC_DBG_SHIFT_8822B)\n#define BITS_R_MAC_DBG_SHIFT_8822B                                             \\\n\t(BIT_MASK_R_MAC_DBG_SHIFT_8822B << BIT_SHIFT_R_MAC_DBG_SHIFT_8822B)\n#define BIT_CLEAR_R_MAC_DBG_SHIFT_8822B(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8822B))\n#define BIT_GET_R_MAC_DBG_SHIFT_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8822B) &                            \\\n\t BIT_MASK_R_MAC_DBG_SHIFT_8822B)\n#define BIT_SET_R_MAC_DBG_SHIFT_8822B(x, v)                                    \\\n\t(BIT_CLEAR_R_MAC_DBG_SHIFT_8822B(x) | BIT_R_MAC_DBG_SHIFT_8822B(v))\n\n#define BIT_SHIFT_R_MAC_DBG_SEL_8822B 0\n#define BIT_MASK_R_MAC_DBG_SEL_8822B 0x3\n#define BIT_R_MAC_DBG_SEL_8822B(x)                                             \\\n\t(((x) & BIT_MASK_R_MAC_DBG_SEL_8822B) << BIT_SHIFT_R_MAC_DBG_SEL_8822B)\n#define BITS_R_MAC_DBG_SEL_8822B                                               \\\n\t(BIT_MASK_R_MAC_DBG_SEL_8822B << BIT_SHIFT_R_MAC_DBG_SEL_8822B)\n#define BIT_CLEAR_R_MAC_DBG_SEL_8822B(x) ((x) & (~BITS_R_MAC_DBG_SEL_8822B))\n#define BIT_GET_R_MAC_DBG_SEL_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8822B) & BIT_MASK_R_MAC_DBG_SEL_8822B)\n#define BIT_SET_R_MAC_DBG_SEL_8822B(x, v)                                      \\\n\t(BIT_CLEAR_R_MAC_DBG_SEL_8822B(x) | BIT_R_MAC_DBG_SEL_8822B(v))\n\n/* 2 REG_RTS_ADDRESS_0_8822B */\n\n/* 2 REG_RTS_ADDRESS_1_8822B */\n\n/* 2 REG_RPFM_MAP1_8822B */\n#define BIT_DATA_RPFM15EN_8822B BIT(15)\n#define BIT_DATA_RPFM14EN_8822B BIT(14)\n#define BIT_DATA_RPFM13EN_8822B BIT(13)\n#define BIT_DATA_RPFM12EN_8822B BIT(12)\n#define BIT_DATA_RPFM11EN_8822B BIT(11)\n#define BIT_DATA_RPFM10EN_8822B BIT(10)\n#define BIT_DATA_RPFM9EN_8822B BIT(9)\n#define BIT_DATA_RPFM8EN_8822B BIT(8)\n#define BIT_DATA_RPFM7EN_8822B BIT(7)\n#define BIT_DATA_RPFM6EN_8822B BIT(6)\n#define BIT_DATA_RPFM5EN_8822B BIT(5)\n#define BIT_DATA_RPFM4EN_8822B BIT(4)\n#define BIT_DATA_RPFM3EN_8822B BIT(3)\n#define BIT_DATA_RPFM2EN_8822B BIT(2)\n#define BIT_DATA_RPFM1EN_8822B BIT(1)\n#define BIT_DATA_RPFM0EN_8822B BIT(0)\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822B */\n#define BIT_LTECOEX_ACCESS_START_V1_8822B BIT(31)\n#define BIT_LTECOEX_WRITE_MODE_V1_8822B BIT(30)\n#define BIT_LTECOEX_READY_BIT_V1_8822B BIT(29)\n\n#define BIT_SHIFT_WRITE_BYTE_EN_V1_8822B 16\n#define BIT_MASK_WRITE_BYTE_EN_V1_8822B 0xf\n#define BIT_WRITE_BYTE_EN_V1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_WRITE_BYTE_EN_V1_8822B)                               \\\n\t << BIT_SHIFT_WRITE_BYTE_EN_V1_8822B)\n#define BITS_WRITE_BYTE_EN_V1_8822B                                            \\\n\t(BIT_MASK_WRITE_BYTE_EN_V1_8822B << BIT_SHIFT_WRITE_BYTE_EN_V1_8822B)\n#define BIT_CLEAR_WRITE_BYTE_EN_V1_8822B(x)                                    \\\n\t((x) & (~BITS_WRITE_BYTE_EN_V1_8822B))\n#define BIT_GET_WRITE_BYTE_EN_V1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8822B) &                           \\\n\t BIT_MASK_WRITE_BYTE_EN_V1_8822B)\n#define BIT_SET_WRITE_BYTE_EN_V1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_WRITE_BYTE_EN_V1_8822B(x) | BIT_WRITE_BYTE_EN_V1_8822B(v))\n\n#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B 0\n#define BIT_MASK_LTECOEX_REG_ADDR_V1_8822B 0xffff\n#define BIT_LTECOEX_REG_ADDR_V1_8822B(x)                                       \\\n\t(((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822B)                            \\\n\t << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B)\n#define BITS_LTECOEX_REG_ADDR_V1_8822B                                         \\\n\t(BIT_MASK_LTECOEX_REG_ADDR_V1_8822B                                    \\\n\t << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B)\n#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822B(x)                                 \\\n\t((x) & (~BITS_LTECOEX_REG_ADDR_V1_8822B))\n#define BIT_GET_LTECOEX_REG_ADDR_V1_8822B(x)                                   \\\n\t(((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B) &                        \\\n\t BIT_MASK_LTECOEX_REG_ADDR_V1_8822B)\n#define BIT_SET_LTECOEX_REG_ADDR_V1_8822B(x, v)                                \\\n\t(BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822B(x) |                              \\\n\t BIT_LTECOEX_REG_ADDR_V1_8822B(v))\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822B */\n\n#define BIT_SHIFT_LTECOEX_W_DATA_V1_8822B 0\n#define BIT_MASK_LTECOEX_W_DATA_V1_8822B 0xffffffffL\n#define BIT_LTECOEX_W_DATA_V1_8822B(x)                                         \\\n\t(((x) & BIT_MASK_LTECOEX_W_DATA_V1_8822B)                              \\\n\t << BIT_SHIFT_LTECOEX_W_DATA_V1_8822B)\n#define BITS_LTECOEX_W_DATA_V1_8822B                                           \\\n\t(BIT_MASK_LTECOEX_W_DATA_V1_8822B << BIT_SHIFT_LTECOEX_W_DATA_V1_8822B)\n#define BIT_CLEAR_LTECOEX_W_DATA_V1_8822B(x)                                   \\\n\t((x) & (~BITS_LTECOEX_W_DATA_V1_8822B))\n#define BIT_GET_LTECOEX_W_DATA_V1_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8822B) &                          \\\n\t BIT_MASK_LTECOEX_W_DATA_V1_8822B)\n#define BIT_SET_LTECOEX_W_DATA_V1_8822B(x, v)                                  \\\n\t(BIT_CLEAR_LTECOEX_W_DATA_V1_8822B(x) | BIT_LTECOEX_W_DATA_V1_8822B(v))\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822B */\n\n#define BIT_SHIFT_LTECOEX_R_DATA_V1_8822B 0\n#define BIT_MASK_LTECOEX_R_DATA_V1_8822B 0xffffffffL\n#define BIT_LTECOEX_R_DATA_V1_8822B(x)                                         \\\n\t(((x) & BIT_MASK_LTECOEX_R_DATA_V1_8822B)                              \\\n\t << BIT_SHIFT_LTECOEX_R_DATA_V1_8822B)\n#define BITS_LTECOEX_R_DATA_V1_8822B                                           \\\n\t(BIT_MASK_LTECOEX_R_DATA_V1_8822B << BIT_SHIFT_LTECOEX_R_DATA_V1_8822B)\n#define BIT_CLEAR_LTECOEX_R_DATA_V1_8822B(x)                                   \\\n\t((x) & (~BITS_LTECOEX_R_DATA_V1_8822B))\n#define BIT_GET_LTECOEX_R_DATA_V1_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8822B) &                          \\\n\t BIT_MASK_LTECOEX_R_DATA_V1_8822B)\n#define BIT_SET_LTECOEX_R_DATA_V1_8822B(x, v)                                  \\\n\t(BIT_CLEAR_LTECOEX_R_DATA_V1_8822B(x) | BIT_LTECOEX_R_DATA_V1_8822B(v))\n\n/* 2 REG_NOT_VALID_8822B */\n\n/* 2 REG_SDIO_TX_CTRL_8822B */\n\n#define BIT_SHIFT_SDIO_INT_TIMEOUT_8822B 16\n#define BIT_MASK_SDIO_INT_TIMEOUT_8822B 0xffff\n#define BIT_SDIO_INT_TIMEOUT_8822B(x)                                          \\\n\t(((x) & BIT_MASK_SDIO_INT_TIMEOUT_8822B)                               \\\n\t << BIT_SHIFT_SDIO_INT_TIMEOUT_8822B)\n#define BITS_SDIO_INT_TIMEOUT_8822B                                            \\\n\t(BIT_MASK_SDIO_INT_TIMEOUT_8822B << BIT_SHIFT_SDIO_INT_TIMEOUT_8822B)\n#define BIT_CLEAR_SDIO_INT_TIMEOUT_8822B(x)                                    \\\n\t((x) & (~BITS_SDIO_INT_TIMEOUT_8822B))\n#define BIT_GET_SDIO_INT_TIMEOUT_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8822B) &                           \\\n\t BIT_MASK_SDIO_INT_TIMEOUT_8822B)\n#define BIT_SET_SDIO_INT_TIMEOUT_8822B(x, v)                                   \\\n\t(BIT_CLEAR_SDIO_INT_TIMEOUT_8822B(x) | BIT_SDIO_INT_TIMEOUT_8822B(v))\n\n#define BIT_IO_ERR_STATUS_8822B BIT(15)\n#define BIT_REPLY_ERRCRC_IN_DATA_8822B BIT(9)\n#define BIT_EN_CMD53_OVERLAP_8822B BIT(8)\n#define BIT_REPLY_ERR_IN_R5_8822B BIT(7)\n#define BIT_R18A_EN_8822B BIT(6)\n#define BIT_SDIO_CMD_FORCE_VLD_8822B BIT(5)\n#define BIT_INIT_CMD_EN_8822B BIT(4)\n#define BIT_EN_RXDMA_MASK_INT_8822B BIT(2)\n#define BIT_EN_MASK_TIMER_8822B BIT(1)\n#define BIT_CMD_ERR_STOP_INT_EN_8822B BIT(0)\n\n/* 2 REG_SDIO_HIMR_8822B */\n#define BIT_SDIO_CRCERR_MSK_8822B BIT(31)\n#define BIT_SDIO_HSISR3_IND_MSK_8822B BIT(30)\n#define BIT_SDIO_HSISR2_IND_MSK_8822B BIT(29)\n#define BIT_SDIO_HEISR_IND_MSK_8822B BIT(28)\n#define BIT_SDIO_CTWEND_MSK_8822B BIT(27)\n#define BIT_SDIO_ATIMEND_E_MSK_8822B BIT(26)\n#define BIT_SDIIO_ATIMEND_MSK_8822B BIT(25)\n#define BIT_SDIO_OCPINT_MSK_8822B BIT(24)\n#define BIT_SDIO_PSTIMEOUT_MSK_8822B BIT(23)\n#define BIT_SDIO_GTINT4_MSK_8822B BIT(22)\n#define BIT_SDIO_GTINT3_MSK_8822B BIT(21)\n#define BIT_SDIO_HSISR_IND_MSK_8822B BIT(20)\n#define BIT_SDIO_CPWM2_MSK_8822B BIT(19)\n#define BIT_SDIO_CPWM1_MSK_8822B BIT(18)\n#define BIT_SDIO_C2HCMD_INT_MSK_8822B BIT(17)\n#define BIT_SDIO_BCNERLY_INT_MSK_8822B BIT(16)\n#define BIT_SDIO_TXBCNERR_MSK_8822B BIT(7)\n#define BIT_SDIO_TXBCNOK_MSK_8822B BIT(6)\n#define BIT_SDIO_RXFOVW_MSK_8822B BIT(5)\n#define BIT_SDIO_TXFOVW_MSK_8822B BIT(4)\n#define BIT_SDIO_RXERR_MSK_8822B BIT(3)\n#define BIT_SDIO_TXERR_MSK_8822B BIT(2)\n#define BIT_SDIO_AVAL_MSK_8822B BIT(1)\n#define BIT_RX_REQUEST_MSK_8822B BIT(0)\n\n/* 2 REG_SDIO_HISR_8822B */\n#define BIT_SDIO_CRCERR_8822B BIT(31)\n#define BIT_SDIO_HSISR3_IND_8822B BIT(30)\n#define BIT_SDIO_HSISR2_IND_8822B BIT(29)\n#define BIT_SDIO_HEISR_IND_8822B BIT(28)\n#define BIT_SDIO_CTWEND_8822B BIT(27)\n#define BIT_SDIO_ATIMEND_E_8822B BIT(26)\n#define BIT_SDIO_ATIMEND_8822B BIT(25)\n#define BIT_SDIO_OCPINT_8822B BIT(24)\n#define BIT_SDIO_PSTIMEOUT_8822B BIT(23)\n#define BIT_SDIO_GTINT4_8822B BIT(22)\n#define BIT_SDIO_GTINT3_8822B BIT(21)\n#define BIT_SDIO_HSISR_IND_8822B BIT(20)\n#define BIT_SDIO_CPWM2_8822B BIT(19)\n#define BIT_SDIO_CPWM1_8822B BIT(18)\n#define BIT_SDIO_C2HCMD_INT_8822B BIT(17)\n#define BIT_SDIO_BCNERLY_INT_8822B BIT(16)\n#define BIT_SDIO_TXBCNERR_8822B BIT(7)\n#define BIT_SDIO_TXBCNOK_8822B BIT(6)\n#define BIT_SDIO_RXFOVW_8822B BIT(5)\n#define BIT_SDIO_TXFOVW_8822B BIT(4)\n#define BIT_SDIO_RXERR_8822B BIT(3)\n#define BIT_SDIO_TXERR_8822B BIT(2)\n#define BIT_SDIO_AVAL_8822B BIT(1)\n#define BIT_RX_REQUEST_8822B BIT(0)\n\n/* 2 REG_SDIO_RX_REQ_LEN_8822B */\n\n#define BIT_SHIFT_RX_REQ_LEN_V1_8822B 0\n#define BIT_MASK_RX_REQ_LEN_V1_8822B 0x3ffff\n#define BIT_RX_REQ_LEN_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_RX_REQ_LEN_V1_8822B) << BIT_SHIFT_RX_REQ_LEN_V1_8822B)\n#define BITS_RX_REQ_LEN_V1_8822B                                               \\\n\t(BIT_MASK_RX_REQ_LEN_V1_8822B << BIT_SHIFT_RX_REQ_LEN_V1_8822B)\n#define BIT_CLEAR_RX_REQ_LEN_V1_8822B(x) ((x) & (~BITS_RX_REQ_LEN_V1_8822B))\n#define BIT_GET_RX_REQ_LEN_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8822B) & BIT_MASK_RX_REQ_LEN_V1_8822B)\n#define BIT_SET_RX_REQ_LEN_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_RX_REQ_LEN_V1_8822B(x) | BIT_RX_REQ_LEN_V1_8822B(v))\n\n/* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8822B */\n\n#define BIT_SHIFT_FREE_TXPG_SEQ_8822B 0\n#define BIT_MASK_FREE_TXPG_SEQ_8822B 0xff\n#define BIT_FREE_TXPG_SEQ_8822B(x)                                             \\\n\t(((x) & BIT_MASK_FREE_TXPG_SEQ_8822B) << BIT_SHIFT_FREE_TXPG_SEQ_8822B)\n#define BITS_FREE_TXPG_SEQ_8822B                                               \\\n\t(BIT_MASK_FREE_TXPG_SEQ_8822B << BIT_SHIFT_FREE_TXPG_SEQ_8822B)\n#define BIT_CLEAR_FREE_TXPG_SEQ_8822B(x) ((x) & (~BITS_FREE_TXPG_SEQ_8822B))\n#define BIT_GET_FREE_TXPG_SEQ_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8822B) & BIT_MASK_FREE_TXPG_SEQ_8822B)\n#define BIT_SET_FREE_TXPG_SEQ_8822B(x, v)                                      \\\n\t(BIT_CLEAR_FREE_TXPG_SEQ_8822B(x) | BIT_FREE_TXPG_SEQ_8822B(v))\n\n/* 2 REG_SDIO_FREE_TXPG_8822B */\n\n#define BIT_SHIFT_MID_FREEPG_V1_8822B 16\n#define BIT_MASK_MID_FREEPG_V1_8822B 0xfff\n#define BIT_MID_FREEPG_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_MID_FREEPG_V1_8822B) << BIT_SHIFT_MID_FREEPG_V1_8822B)\n#define BITS_MID_FREEPG_V1_8822B                                               \\\n\t(BIT_MASK_MID_FREEPG_V1_8822B << BIT_SHIFT_MID_FREEPG_V1_8822B)\n#define BIT_CLEAR_MID_FREEPG_V1_8822B(x) ((x) & (~BITS_MID_FREEPG_V1_8822B))\n#define BIT_GET_MID_FREEPG_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_MID_FREEPG_V1_8822B) & BIT_MASK_MID_FREEPG_V1_8822B)\n#define BIT_SET_MID_FREEPG_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_MID_FREEPG_V1_8822B(x) | BIT_MID_FREEPG_V1_8822B(v))\n\n#define BIT_SHIFT_HIQ_FREEPG_V1_8822B 0\n#define BIT_MASK_HIQ_FREEPG_V1_8822B 0xfff\n#define BIT_HIQ_FREEPG_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_HIQ_FREEPG_V1_8822B) << BIT_SHIFT_HIQ_FREEPG_V1_8822B)\n#define BITS_HIQ_FREEPG_V1_8822B                                               \\\n\t(BIT_MASK_HIQ_FREEPG_V1_8822B << BIT_SHIFT_HIQ_FREEPG_V1_8822B)\n#define BIT_CLEAR_HIQ_FREEPG_V1_8822B(x) ((x) & (~BITS_HIQ_FREEPG_V1_8822B))\n#define BIT_GET_HIQ_FREEPG_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8822B) & BIT_MASK_HIQ_FREEPG_V1_8822B)\n#define BIT_SET_HIQ_FREEPG_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_HIQ_FREEPG_V1_8822B(x) | BIT_HIQ_FREEPG_V1_8822B(v))\n\n/* 2 REG_SDIO_FREE_TXPG2_8822B */\n\n#define BIT_SHIFT_PUB_FREEPG_V1_8822B 16\n#define BIT_MASK_PUB_FREEPG_V1_8822B 0xfff\n#define BIT_PUB_FREEPG_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_PUB_FREEPG_V1_8822B) << BIT_SHIFT_PUB_FREEPG_V1_8822B)\n#define BITS_PUB_FREEPG_V1_8822B                                               \\\n\t(BIT_MASK_PUB_FREEPG_V1_8822B << BIT_SHIFT_PUB_FREEPG_V1_8822B)\n#define BIT_CLEAR_PUB_FREEPG_V1_8822B(x) ((x) & (~BITS_PUB_FREEPG_V1_8822B))\n#define BIT_GET_PUB_FREEPG_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_PUB_FREEPG_V1_8822B) & BIT_MASK_PUB_FREEPG_V1_8822B)\n#define BIT_SET_PUB_FREEPG_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_PUB_FREEPG_V1_8822B(x) | BIT_PUB_FREEPG_V1_8822B(v))\n\n#define BIT_SHIFT_LOW_FREEPG_V1_8822B 0\n#define BIT_MASK_LOW_FREEPG_V1_8822B 0xfff\n#define BIT_LOW_FREEPG_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_LOW_FREEPG_V1_8822B) << BIT_SHIFT_LOW_FREEPG_V1_8822B)\n#define BITS_LOW_FREEPG_V1_8822B                                               \\\n\t(BIT_MASK_LOW_FREEPG_V1_8822B << BIT_SHIFT_LOW_FREEPG_V1_8822B)\n#define BIT_CLEAR_LOW_FREEPG_V1_8822B(x) ((x) & (~BITS_LOW_FREEPG_V1_8822B))\n#define BIT_GET_LOW_FREEPG_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_LOW_FREEPG_V1_8822B) & BIT_MASK_LOW_FREEPG_V1_8822B)\n#define BIT_SET_LOW_FREEPG_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_LOW_FREEPG_V1_8822B(x) | BIT_LOW_FREEPG_V1_8822B(v))\n\n/* 2 REG_SDIO_OQT_FREE_TXPG_V1_8822B */\n\n#define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B 24\n#define BIT_MASK_NOAC_OQT_FREEPG_V1_8822B 0xff\n#define BIT_NOAC_OQT_FREEPG_V1_8822B(x)                                        \\\n\t(((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822B)                             \\\n\t << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B)\n#define BITS_NOAC_OQT_FREEPG_V1_8822B                                          \\\n\t(BIT_MASK_NOAC_OQT_FREEPG_V1_8822B                                     \\\n\t << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B)\n#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822B(x)                                  \\\n\t((x) & (~BITS_NOAC_OQT_FREEPG_V1_8822B))\n#define BIT_GET_NOAC_OQT_FREEPG_V1_8822B(x)                                    \\\n\t(((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B) &                         \\\n\t BIT_MASK_NOAC_OQT_FREEPG_V1_8822B)\n#define BIT_SET_NOAC_OQT_FREEPG_V1_8822B(x, v)                                 \\\n\t(BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822B(x) |                               \\\n\t BIT_NOAC_OQT_FREEPG_V1_8822B(v))\n\n#define BIT_SHIFT_AC_OQT_FREEPG_V1_8822B 16\n#define BIT_MASK_AC_OQT_FREEPG_V1_8822B 0xff\n#define BIT_AC_OQT_FREEPG_V1_8822B(x)                                          \\\n\t(((x) & BIT_MASK_AC_OQT_FREEPG_V1_8822B)                               \\\n\t << BIT_SHIFT_AC_OQT_FREEPG_V1_8822B)\n#define BITS_AC_OQT_FREEPG_V1_8822B                                            \\\n\t(BIT_MASK_AC_OQT_FREEPG_V1_8822B << BIT_SHIFT_AC_OQT_FREEPG_V1_8822B)\n#define BIT_CLEAR_AC_OQT_FREEPG_V1_8822B(x)                                    \\\n\t((x) & (~BITS_AC_OQT_FREEPG_V1_8822B))\n#define BIT_GET_AC_OQT_FREEPG_V1_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8822B) &                           \\\n\t BIT_MASK_AC_OQT_FREEPG_V1_8822B)\n#define BIT_SET_AC_OQT_FREEPG_V1_8822B(x, v)                                   \\\n\t(BIT_CLEAR_AC_OQT_FREEPG_V1_8822B(x) | BIT_AC_OQT_FREEPG_V1_8822B(v))\n\n#define BIT_SHIFT_EXQ_FREEPG_V1_8822B 0\n#define BIT_MASK_EXQ_FREEPG_V1_8822B 0xfff\n#define BIT_EXQ_FREEPG_V1_8822B(x)                                             \\\n\t(((x) & BIT_MASK_EXQ_FREEPG_V1_8822B) << BIT_SHIFT_EXQ_FREEPG_V1_8822B)\n#define BITS_EXQ_FREEPG_V1_8822B                                               \\\n\t(BIT_MASK_EXQ_FREEPG_V1_8822B << BIT_SHIFT_EXQ_FREEPG_V1_8822B)\n#define BIT_CLEAR_EXQ_FREEPG_V1_8822B(x) ((x) & (~BITS_EXQ_FREEPG_V1_8822B))\n#define BIT_GET_EXQ_FREEPG_V1_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8822B) & BIT_MASK_EXQ_FREEPG_V1_8822B)\n#define BIT_SET_EXQ_FREEPG_V1_8822B(x, v)                                      \\\n\t(BIT_CLEAR_EXQ_FREEPG_V1_8822B(x) | BIT_EXQ_FREEPG_V1_8822B(v))\n\n/* 2 REG_SDIO_HTSFR_INFO_8822B */\n\n#define BIT_SHIFT_HTSFR1_8822B 16\n#define BIT_MASK_HTSFR1_8822B 0xffff\n#define BIT_HTSFR1_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_HTSFR1_8822B) << BIT_SHIFT_HTSFR1_8822B)\n#define BITS_HTSFR1_8822B (BIT_MASK_HTSFR1_8822B << BIT_SHIFT_HTSFR1_8822B)\n#define BIT_CLEAR_HTSFR1_8822B(x) ((x) & (~BITS_HTSFR1_8822B))\n#define BIT_GET_HTSFR1_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_HTSFR1_8822B) & BIT_MASK_HTSFR1_8822B)\n#define BIT_SET_HTSFR1_8822B(x, v)                                             \\\n\t(BIT_CLEAR_HTSFR1_8822B(x) | BIT_HTSFR1_8822B(v))\n\n#define BIT_SHIFT_HTSFR0_8822B 0\n#define BIT_MASK_HTSFR0_8822B 0xffff\n#define BIT_HTSFR0_8822B(x)                                                    \\\n\t(((x) & BIT_MASK_HTSFR0_8822B) << BIT_SHIFT_HTSFR0_8822B)\n#define BITS_HTSFR0_8822B (BIT_MASK_HTSFR0_8822B << BIT_SHIFT_HTSFR0_8822B)\n#define BIT_CLEAR_HTSFR0_8822B(x) ((x) & (~BITS_HTSFR0_8822B))\n#define BIT_GET_HTSFR0_8822B(x)                                                \\\n\t(((x) >> BIT_SHIFT_HTSFR0_8822B) & BIT_MASK_HTSFR0_8822B)\n#define BIT_SET_HTSFR0_8822B(x, v)                                             \\\n\t(BIT_CLEAR_HTSFR0_8822B(x) | BIT_HTSFR0_8822B(v))\n\n/* 2 REG_SDIO_HCPWM1_V2_8822B */\n#define BIT_TOGGLE_8822B BIT(7)\n#define BIT_CUR_PS_8822B BIT(0)\n\n/* 2 REG_SDIO_HCPWM2_V2_8822B */\n\n/* 2 REG_SDIO_INDIRECT_REG_CFG_8822B */\n#define BIT_INDIRECT_REG_RDY_8822B BIT(20)\n#define BIT_INDIRECT_REG_R_8822B BIT(19)\n#define BIT_INDIRECT_REG_W_8822B BIT(18)\n\n#define BIT_SHIFT_INDIRECT_REG_SIZE_8822B 16\n#define BIT_MASK_INDIRECT_REG_SIZE_8822B 0x3\n#define BIT_INDIRECT_REG_SIZE_8822B(x)                                         \\\n\t(((x) & BIT_MASK_INDIRECT_REG_SIZE_8822B)                              \\\n\t << BIT_SHIFT_INDIRECT_REG_SIZE_8822B)\n#define BITS_INDIRECT_REG_SIZE_8822B                                           \\\n\t(BIT_MASK_INDIRECT_REG_SIZE_8822B << BIT_SHIFT_INDIRECT_REG_SIZE_8822B)\n#define BIT_CLEAR_INDIRECT_REG_SIZE_8822B(x)                                   \\\n\t((x) & (~BITS_INDIRECT_REG_SIZE_8822B))\n#define BIT_GET_INDIRECT_REG_SIZE_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8822B) &                          \\\n\t BIT_MASK_INDIRECT_REG_SIZE_8822B)\n#define BIT_SET_INDIRECT_REG_SIZE_8822B(x, v)                                  \\\n\t(BIT_CLEAR_INDIRECT_REG_SIZE_8822B(x) | BIT_INDIRECT_REG_SIZE_8822B(v))\n\n#define BIT_SHIFT_INDIRECT_REG_ADDR_8822B 0\n#define BIT_MASK_INDIRECT_REG_ADDR_8822B 0xffff\n#define BIT_INDIRECT_REG_ADDR_8822B(x)                                         \\\n\t(((x) & BIT_MASK_INDIRECT_REG_ADDR_8822B)                              \\\n\t << BIT_SHIFT_INDIRECT_REG_ADDR_8822B)\n#define BITS_INDIRECT_REG_ADDR_8822B                                           \\\n\t(BIT_MASK_INDIRECT_REG_ADDR_8822B << BIT_SHIFT_INDIRECT_REG_ADDR_8822B)\n#define BIT_CLEAR_INDIRECT_REG_ADDR_8822B(x)                                   \\\n\t((x) & (~BITS_INDIRECT_REG_ADDR_8822B))\n#define BIT_GET_INDIRECT_REG_ADDR_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8822B) &                          \\\n\t BIT_MASK_INDIRECT_REG_ADDR_8822B)\n#define BIT_SET_INDIRECT_REG_ADDR_8822B(x, v)                                  \\\n\t(BIT_CLEAR_INDIRECT_REG_ADDR_8822B(x) | BIT_INDIRECT_REG_ADDR_8822B(v))\n\n/* 2 REG_SDIO_INDIRECT_REG_DATA_8822B */\n\n#define BIT_SHIFT_INDIRECT_REG_DATA_8822B 0\n#define BIT_MASK_INDIRECT_REG_DATA_8822B 0xffffffffL\n#define BIT_INDIRECT_REG_DATA_8822B(x)                                         \\\n\t(((x) & BIT_MASK_INDIRECT_REG_DATA_8822B)                              \\\n\t << BIT_SHIFT_INDIRECT_REG_DATA_8822B)\n#define BITS_INDIRECT_REG_DATA_8822B                                           \\\n\t(BIT_MASK_INDIRECT_REG_DATA_8822B << BIT_SHIFT_INDIRECT_REG_DATA_8822B)\n#define BIT_CLEAR_INDIRECT_REG_DATA_8822B(x)                                   \\\n\t((x) & (~BITS_INDIRECT_REG_DATA_8822B))\n#define BIT_GET_INDIRECT_REG_DATA_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8822B) &                          \\\n\t BIT_MASK_INDIRECT_REG_DATA_8822B)\n#define BIT_SET_INDIRECT_REG_DATA_8822B(x, v)                                  \\\n\t(BIT_CLEAR_INDIRECT_REG_DATA_8822B(x) | BIT_INDIRECT_REG_DATA_8822B(v))\n\n/* 2 REG_SDIO_H2C_8822B */\n\n#define BIT_SHIFT_SDIO_H2C_MSG_8822B 0\n#define BIT_MASK_SDIO_H2C_MSG_8822B 0xffffffffL\n#define BIT_SDIO_H2C_MSG_8822B(x)                                              \\\n\t(((x) & BIT_MASK_SDIO_H2C_MSG_8822B) << BIT_SHIFT_SDIO_H2C_MSG_8822B)\n#define BITS_SDIO_H2C_MSG_8822B                                                \\\n\t(BIT_MASK_SDIO_H2C_MSG_8822B << BIT_SHIFT_SDIO_H2C_MSG_8822B)\n#define BIT_CLEAR_SDIO_H2C_MSG_8822B(x) ((x) & (~BITS_SDIO_H2C_MSG_8822B))\n#define BIT_GET_SDIO_H2C_MSG_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SDIO_H2C_MSG_8822B) & BIT_MASK_SDIO_H2C_MSG_8822B)\n#define BIT_SET_SDIO_H2C_MSG_8822B(x, v)                                       \\\n\t(BIT_CLEAR_SDIO_H2C_MSG_8822B(x) | BIT_SDIO_H2C_MSG_8822B(v))\n\n/* 2 REG_SDIO_C2H_8822B */\n\n#define BIT_SHIFT_SDIO_C2H_MSG_8822B 0\n#define BIT_MASK_SDIO_C2H_MSG_8822B 0xffffffffL\n#define BIT_SDIO_C2H_MSG_8822B(x)                                              \\\n\t(((x) & BIT_MASK_SDIO_C2H_MSG_8822B) << BIT_SHIFT_SDIO_C2H_MSG_8822B)\n#define BITS_SDIO_C2H_MSG_8822B                                                \\\n\t(BIT_MASK_SDIO_C2H_MSG_8822B << BIT_SHIFT_SDIO_C2H_MSG_8822B)\n#define BIT_CLEAR_SDIO_C2H_MSG_8822B(x) ((x) & (~BITS_SDIO_C2H_MSG_8822B))\n#define BIT_GET_SDIO_C2H_MSG_8822B(x)                                          \\\n\t(((x) >> BIT_SHIFT_SDIO_C2H_MSG_8822B) & BIT_MASK_SDIO_C2H_MSG_8822B)\n#define BIT_SET_SDIO_C2H_MSG_8822B(x, v)                                       \\\n\t(BIT_CLEAR_SDIO_C2H_MSG_8822B(x) | BIT_SDIO_C2H_MSG_8822B(v))\n\n/* 2 REG_SDIO_HRPWM1_8822B */\n#define BIT_TOGGLE_8822B BIT(7)\n#define BIT_ACK_8822B BIT(6)\n#define BIT_REQ_PS_8822B BIT(0)\n\n/* 2 REG_SDIO_HRPWM2_8822B */\n\n/* 2 REG_SDIO_HPS_CLKR_8822B */\n\n/* 2 REG_SDIO_BUS_CTRL_8822B */\n#define BIT_PAD_CLK_XHGE_EN_8822B BIT(3)\n#define BIT_INTER_CLK_EN_8822B BIT(2)\n#define BIT_EN_RPT_TXCRC_8822B BIT(1)\n#define BIT_DIS_RXDMA_STS_8822B BIT(0)\n\n/* 2 REG_SDIO_HSUS_CTRL_8822B */\n#define BIT_INTR_CTRL_8822B BIT(4)\n#define BIT_SDIO_VOLTAGE_8822B BIT(3)\n#define BIT_BYPASS_INIT_8822B BIT(2)\n#define BIT_HCI_RESUME_RDY_8822B BIT(1)\n#define BIT_HCI_SUS_REQ_8822B BIT(0)\n\n/* 2 REG_SDIO_RESPONSE_TIMER_8822B */\n\n#define BIT_SHIFT_CMDIN_2RESP_TIMER_8822B 0\n#define BIT_MASK_CMDIN_2RESP_TIMER_8822B 0xffff\n#define BIT_CMDIN_2RESP_TIMER_8822B(x)                                         \\\n\t(((x) & BIT_MASK_CMDIN_2RESP_TIMER_8822B)                              \\\n\t << BIT_SHIFT_CMDIN_2RESP_TIMER_8822B)\n#define BITS_CMDIN_2RESP_TIMER_8822B                                           \\\n\t(BIT_MASK_CMDIN_2RESP_TIMER_8822B << BIT_SHIFT_CMDIN_2RESP_TIMER_8822B)\n#define BIT_CLEAR_CMDIN_2RESP_TIMER_8822B(x)                                   \\\n\t((x) & (~BITS_CMDIN_2RESP_TIMER_8822B))\n#define BIT_GET_CMDIN_2RESP_TIMER_8822B(x)                                     \\\n\t(((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8822B) &                          \\\n\t BIT_MASK_CMDIN_2RESP_TIMER_8822B)\n#define BIT_SET_CMDIN_2RESP_TIMER_8822B(x, v)                                  \\\n\t(BIT_CLEAR_CMDIN_2RESP_TIMER_8822B(x) | BIT_CMDIN_2RESP_TIMER_8822B(v))\n\n/* 2 REG_SDIO_CMD_CRC_8822B */\n\n#define BIT_SHIFT_SDIO_CMD_CRC_V1_8822B 0\n#define BIT_MASK_SDIO_CMD_CRC_V1_8822B 0xff\n#define BIT_SDIO_CMD_CRC_V1_8822B(x)                                           \\\n\t(((x) & BIT_MASK_SDIO_CMD_CRC_V1_8822B)                                \\\n\t << BIT_SHIFT_SDIO_CMD_CRC_V1_8822B)\n#define BITS_SDIO_CMD_CRC_V1_8822B                                             \\\n\t(BIT_MASK_SDIO_CMD_CRC_V1_8822B << BIT_SHIFT_SDIO_CMD_CRC_V1_8822B)\n#define BIT_CLEAR_SDIO_CMD_CRC_V1_8822B(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8822B))\n#define BIT_GET_SDIO_CMD_CRC_V1_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8822B) &                            \\\n\t BIT_MASK_SDIO_CMD_CRC_V1_8822B)\n#define BIT_SET_SDIO_CMD_CRC_V1_8822B(x, v)                                    \\\n\t(BIT_CLEAR_SDIO_CMD_CRC_V1_8822B(x) | BIT_SDIO_CMD_CRC_V1_8822B(v))\n\n/* 2 REG_SDIO_HSISR_8822B */\n#define BIT_DRV_WLAN_INT_CLR_8822B BIT(1)\n#define BIT_DRV_WLAN_INT_8822B BIT(0)\n\n/* 2 REG_SDIO_ERR_RPT_8822B */\n#define BIT_HR_FF_OVF_8822B BIT(6)\n#define BIT_HR_FF_UDN_8822B BIT(5)\n#define BIT_TXDMA_BUSY_ERR_8822B BIT(4)\n#define BIT_TXDMA_VLD_ERR_8822B BIT(3)\n#define BIT_QSEL_UNKNOWN_ERR_8822B BIT(2)\n#define BIT_QSEL_MIS_ERR_8822B BIT(1)\n#define BIT_SDIO_OVERRD_ERR_8822B BIT(0)\n\n/* 2 REG_SDIO_CMD_ERRCNT_8822B */\n\n#define BIT_SHIFT_CMD_CRC_ERR_CNT_8822B 0\n#define BIT_MASK_CMD_CRC_ERR_CNT_8822B 0xff\n#define BIT_CMD_CRC_ERR_CNT_8822B(x)                                           \\\n\t(((x) & BIT_MASK_CMD_CRC_ERR_CNT_8822B)                                \\\n\t << BIT_SHIFT_CMD_CRC_ERR_CNT_8822B)\n#define BITS_CMD_CRC_ERR_CNT_8822B                                             \\\n\t(BIT_MASK_CMD_CRC_ERR_CNT_8822B << BIT_SHIFT_CMD_CRC_ERR_CNT_8822B)\n#define BIT_CLEAR_CMD_CRC_ERR_CNT_8822B(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8822B))\n#define BIT_GET_CMD_CRC_ERR_CNT_8822B(x)                                       \\\n\t(((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8822B) &                            \\\n\t BIT_MASK_CMD_CRC_ERR_CNT_8822B)\n#define BIT_SET_CMD_CRC_ERR_CNT_8822B(x, v)                                    \\\n\t(BIT_CLEAR_CMD_CRC_ERR_CNT_8822B(x) | BIT_CMD_CRC_ERR_CNT_8822B(v))\n\n/* 2 REG_SDIO_DATA_ERRCNT_8822B */\n\n#define BIT_SHIFT_DATA_CRC_ERR_CNT_8822B 0\n#define BIT_MASK_DATA_CRC_ERR_CNT_8822B 0xff\n#define BIT_DATA_CRC_ERR_CNT_8822B(x)                                          \\\n\t(((x) & BIT_MASK_DATA_CRC_ERR_CNT_8822B)                               \\\n\t << BIT_SHIFT_DATA_CRC_ERR_CNT_8822B)\n#define BITS_DATA_CRC_ERR_CNT_8822B                                            \\\n\t(BIT_MASK_DATA_CRC_ERR_CNT_8822B << BIT_SHIFT_DATA_CRC_ERR_CNT_8822B)\n#define BIT_CLEAR_DATA_CRC_ERR_CNT_8822B(x)                                    \\\n\t((x) & (~BITS_DATA_CRC_ERR_CNT_8822B))\n#define BIT_GET_DATA_CRC_ERR_CNT_8822B(x)                                      \\\n\t(((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8822B) &                           \\\n\t BIT_MASK_DATA_CRC_ERR_CNT_8822B)\n#define BIT_SET_DATA_CRC_ERR_CNT_8822B(x, v)                                   \\\n\t(BIT_CLEAR_DATA_CRC_ERR_CNT_8822B(x) | BIT_DATA_CRC_ERR_CNT_8822B(v))\n\n/* 2 REG_SDIO_CMD_ERR_CONTENT_8822B */\n\n#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B 0\n#define BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B 0xffffffffffL\n#define BIT_SDIO_CMD_ERR_CONTENT_8822B(x)                                      \\\n\t(((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B)                           \\\n\t << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B)\n#define BITS_SDIO_CMD_ERR_CONTENT_8822B                                        \\\n\t(BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B                                   \\\n\t << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B)\n#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822B(x)                                \\\n\t((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8822B))\n#define BIT_GET_SDIO_CMD_ERR_CONTENT_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B) &                       \\\n\t BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B)\n#define BIT_SET_SDIO_CMD_ERR_CONTENT_8822B(x, v)                               \\\n\t(BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822B(x) |                             \\\n\t BIT_SDIO_CMD_ERR_CONTENT_8822B(v))\n\n/* 2 REG_SDIO_CRC_ERR_IDX_8822B */\n#define BIT_D3_CRC_ERR_8822B BIT(4)\n#define BIT_D2_CRC_ERR_8822B BIT(3)\n#define BIT_D1_CRC_ERR_8822B BIT(2)\n#define BIT_D0_CRC_ERR_8822B BIT(1)\n#define BIT_CMD_CRC_ERR_8822B BIT(0)\n\n/* 2 REG_SDIO_DATA_CRC_8822B */\n\n#define BIT_SHIFT_SDIO_DATA_CRC_8822B 0\n#define BIT_MASK_SDIO_DATA_CRC_8822B 0xffff\n#define BIT_SDIO_DATA_CRC_8822B(x)                                             \\\n\t(((x) & BIT_MASK_SDIO_DATA_CRC_8822B) << BIT_SHIFT_SDIO_DATA_CRC_8822B)\n#define BITS_SDIO_DATA_CRC_8822B                                               \\\n\t(BIT_MASK_SDIO_DATA_CRC_8822B << BIT_SHIFT_SDIO_DATA_CRC_8822B)\n#define BIT_CLEAR_SDIO_DATA_CRC_8822B(x) ((x) & (~BITS_SDIO_DATA_CRC_8822B))\n#define BIT_GET_SDIO_DATA_CRC_8822B(x)                                         \\\n\t(((x) >> BIT_SHIFT_SDIO_DATA_CRC_8822B) & BIT_MASK_SDIO_DATA_CRC_8822B)\n#define BIT_SET_SDIO_DATA_CRC_8822B(x, v)                                      \\\n\t(BIT_CLEAR_SDIO_DATA_CRC_8822B(x) | BIT_SDIO_DATA_CRC_8822B(v))\n\n/* 2 REG_SDIO_DATA_REPLY_TIME_8822B */\n\n#define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B 0\n#define BIT_MASK_SDIO_DATA_REPLY_TIME_8822B 0x7\n#define BIT_SDIO_DATA_REPLY_TIME_8822B(x)                                      \\\n\t(((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8822B)                           \\\n\t << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B)\n#define BITS_SDIO_DATA_REPLY_TIME_8822B                                        \\\n\t(BIT_MASK_SDIO_DATA_REPLY_TIME_8822B                                   \\\n\t << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B)\n#define BIT_CLEAR_SDIO_DATA_REPLY_TIME_8822B(x)                                \\\n\t((x) & (~BITS_SDIO_DATA_REPLY_TIME_8822B))\n#define BIT_GET_SDIO_DATA_REPLY_TIME_8822B(x)                                  \\\n\t(((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B) &                       \\\n\t BIT_MASK_SDIO_DATA_REPLY_TIME_8822B)\n#define BIT_SET_SDIO_DATA_REPLY_TIME_8822B(x, v)                               \\\n\t(BIT_CLEAR_SDIO_DATA_REPLY_TIME_8822B(x) |                             \\\n\t BIT_SDIO_DATA_REPLY_TIME_8822B(v))\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_bit_8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef __INC_HALMAC_BIT_8822C_H\n#define __INC_HALMAC_BIT_8822C_H\n\n#define CPU_OPT_WIDTH 0x1F\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_SYS_ISO_CTRL_8822C */\n#define BIT_PWC_EV12V_8822C BIT(15)\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_PA33V_EN_8822C BIT(13)\n#define BIT_PA12V_EN_8822C BIT(12)\n#define BIT_UA33V_EN_8822C BIT(11)\n#define BIT_UA12V_EN_8822C BIT(10)\n#define BIT_ISO_RFDIO_8822C BIT(9)\n#define BIT_ISO_EB2CORE_8822C BIT(8)\n#define BIT_ISO_DIOE_8822C BIT(7)\n#define BIT_ISO_WLPON2PP_8822C BIT(6)\n#define BIT_ISO_IP2MAC_WA2PP_8822C BIT(5)\n#define BIT_ISO_PD2CORE_8822C BIT(4)\n#define BIT_ISO_PA2PCIE_8822C BIT(3)\n#define BIT_ISO_UD2CORE_8822C BIT(2)\n#define BIT_ISO_UA2USB_8822C BIT(1)\n#define BIT_ISO_WD2PP_8822C BIT(0)\n\n/* 2 REG_SYS_FUNC_EN_8822C */\n#define BIT_FEN_MREGEN_8822C BIT(15)\n#define BIT_FEN_HWPDN_8822C BIT(14)\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_FEN_ELDR_8822C BIT(12)\n#define BIT_FEN_DCORE_8822C BIT(11)\n#define BIT_FEN_CPUEN_8822C BIT(10)\n#define BIT_FEN_DIOE_8822C BIT(9)\n#define BIT_FEN_PCIED_8822C BIT(8)\n#define BIT_FEN_PPLL_8822C BIT(7)\n#define BIT_FEN_PCIEA_8822C BIT(6)\n#define BIT_FEN_DIO_PCIE_8822C BIT(5)\n#define BIT_FEN_USBD_8822C BIT(4)\n#define BIT_FEN_UPLL_8822C BIT(3)\n#define BIT_FEN_USBA_8822C BIT(2)\n#define BIT_FEN_BB_GLB_RSTN_8822C BIT(1)\n#define BIT_FEN_BBRSTB_8822C BIT(0)\n\n/* 2 REG_SYS_PW_CTRL_8822C */\n#define BIT_SOP_EABM_8822C BIT(31)\n#define BIT_SOP_ACKF_8822C BIT(30)\n#define BIT_SOP_ERCK_8822C BIT(29)\n#define BIT_SOP_ESWR_8822C BIT(28)\n#define BIT_SOP_PWMM_8822C BIT(27)\n#define BIT_SOP_EECK_8822C BIT(26)\n#define BIT_SOP_ANA_CLK_DIVISION_2_8822C BIT(25)\n#define BIT_SOP_EXTL_8822C BIT(24)\n#define BIT_SYM_OP_RING_12M_8822C BIT(22)\n#define BIT_ROP_SWPR_8822C BIT(21)\n#define BIT_DIS_HW_LPLDM_8822C BIT(20)\n#define BIT_OPT_SWRST_WLMCU_8822C BIT(19)\n#define BIT_RDY_SYSPWR_8822C BIT(17)\n#define BIT_EN_WLON_8822C BIT(16)\n#define BIT_APDM_HPDN_8822C BIT(15)\n#define BIT_AFSM_PCIE_SUS_EN_8822C BIT(12)\n#define BIT_AFSM_WLSUS_EN_8822C BIT(11)\n#define BIT_APFM_SWLPS_8822C BIT(10)\n#define BIT_APFM_OFFMAC_8822C BIT(9)\n#define BIT_APFN_ONMAC_8822C BIT(8)\n#define BIT_CHIP_PDN_EN_8822C BIT(7)\n#define BIT_RDY_MACDIS_8822C BIT(6)\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_PFM_WOWL_8822C BIT(3)\n#define BIT_PFM_LDKP_8822C BIT(2)\n#define BIT_WL_HCI_ALD_8822C BIT(1)\n#define BIT_PFM_LDALL_8822C BIT(0)\n\n/* 2 REG_SYS_CLK_CTRL_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_CPU_CLK_EN_8822C BIT(14)\n#define BIT_SYMREG_CLK_EN_8822C BIT(13)\n#define BIT_HCI_CLK_EN_8822C BIT(12)\n#define BIT_MAC_CLK_EN_8822C BIT(11)\n#define BIT_SEC_CLK_EN_8822C BIT(10)\n#define BIT_PHY_SSC_RSTB_8822C BIT(9)\n#define BIT_EXT_32K_EN_8822C BIT(8)\n#define BIT_WL_CLK_TEST_8822C BIT(7)\n#define BIT_OP_SPS_PWM_EN_8822C BIT(6)\n#define BIT_LOADER_CLK_EN_8822C BIT(5)\n#define BIT_MACSLP_8822C BIT(4)\n#define BIT_WAKEPAD_EN_8822C BIT(3)\n#define BIT_ROMD16V_EN_8822C BIT(2)\n#define BIT_ANA_CLK_DIVISION_2_8822C BIT(1)\n#define BIT_CNTD16V_EN_8822C BIT(0)\n\n/* 2 REG_SYS_EEPROM_CTRL_8822C */\n\n#define BIT_SHIFT_VPDIDX_8822C 8\n#define BIT_MASK_VPDIDX_8822C 0xff\n#define BIT_VPDIDX_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_VPDIDX_8822C) << BIT_SHIFT_VPDIDX_8822C)\n#define BITS_VPDIDX_8822C (BIT_MASK_VPDIDX_8822C << BIT_SHIFT_VPDIDX_8822C)\n#define BIT_CLEAR_VPDIDX_8822C(x) ((x) & (~BITS_VPDIDX_8822C))\n#define BIT_GET_VPDIDX_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_VPDIDX_8822C) & BIT_MASK_VPDIDX_8822C)\n#define BIT_SET_VPDIDX_8822C(x, v)                                             \\\n\t(BIT_CLEAR_VPDIDX_8822C(x) | BIT_VPDIDX_8822C(v))\n\n#define BIT_SHIFT_EEM1_0_8822C 6\n#define BIT_MASK_EEM1_0_8822C 0x3\n#define BIT_EEM1_0_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_EEM1_0_8822C) << BIT_SHIFT_EEM1_0_8822C)\n#define BITS_EEM1_0_8822C (BIT_MASK_EEM1_0_8822C << BIT_SHIFT_EEM1_0_8822C)\n#define BIT_CLEAR_EEM1_0_8822C(x) ((x) & (~BITS_EEM1_0_8822C))\n#define BIT_GET_EEM1_0_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_EEM1_0_8822C) & BIT_MASK_EEM1_0_8822C)\n#define BIT_SET_EEM1_0_8822C(x, v)                                             \\\n\t(BIT_CLEAR_EEM1_0_8822C(x) | BIT_EEM1_0_8822C(v))\n\n#define BIT_AUTOLOAD_SUS_8822C BIT(5)\n#define BIT_EERPOMSEL_8822C BIT(4)\n#define BIT_EECS_V1_8822C BIT(3)\n#define BIT_EESK_V1_8822C BIT(2)\n#define BIT_EEDI_V1_8822C BIT(1)\n#define BIT_EEDO_V1_8822C BIT(0)\n\n/* 2 REG_EE_VPD_8822C */\n\n#define BIT_SHIFT_VPD_DATA_8822C 0\n#define BIT_MASK_VPD_DATA_8822C 0xffffffffL\n#define BIT_VPD_DATA_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_VPD_DATA_8822C) << BIT_SHIFT_VPD_DATA_8822C)\n#define BITS_VPD_DATA_8822C                                                    \\\n\t(BIT_MASK_VPD_DATA_8822C << BIT_SHIFT_VPD_DATA_8822C)\n#define BIT_CLEAR_VPD_DATA_8822C(x) ((x) & (~BITS_VPD_DATA_8822C))\n#define BIT_GET_VPD_DATA_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_VPD_DATA_8822C) & BIT_MASK_VPD_DATA_8822C)\n#define BIT_SET_VPD_DATA_8822C(x, v)                                           \\\n\t(BIT_CLEAR_VPD_DATA_8822C(x) | BIT_VPD_DATA_8822C(v))\n\n/* 2 REG_SYS_SWR_CTRL1_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_HW_AUTO_CTRL_EXT_SWR_8822C BIT(9)\n#define BIT_USE_INTERNAL_SWR_AND_LDO_8822C BIT(8)\n#define BIT_MAC_ID_EN_8822C BIT(7)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_SYS_SWR_CTRL2_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_SW18_SEL_8822C BIT(13)\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_SW18_SD_8822C BIT(10)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_SYS_SWR_CTRL3_8822C */\n#define BIT_SPS18_OCP_DIS_8822C BIT(31)\n\n#define BIT_SHIFT_SPS18_OCP_TH_8822C 16\n#define BIT_MASK_SPS18_OCP_TH_8822C 0x7fff\n#define BIT_SPS18_OCP_TH_8822C(x)                                              \\\n\t(((x) & BIT_MASK_SPS18_OCP_TH_8822C) << BIT_SHIFT_SPS18_OCP_TH_8822C)\n#define BITS_SPS18_OCP_TH_8822C                                                \\\n\t(BIT_MASK_SPS18_OCP_TH_8822C << BIT_SHIFT_SPS18_OCP_TH_8822C)\n#define BIT_CLEAR_SPS18_OCP_TH_8822C(x) ((x) & (~BITS_SPS18_OCP_TH_8822C))\n#define BIT_GET_SPS18_OCP_TH_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_SPS18_OCP_TH_8822C) & BIT_MASK_SPS18_OCP_TH_8822C)\n#define BIT_SET_SPS18_OCP_TH_8822C(x, v)                                       \\\n\t(BIT_CLEAR_SPS18_OCP_TH_8822C(x) | BIT_SPS18_OCP_TH_8822C(v))\n\n#define BIT_SHIFT_OCP_WINDOW_8822C 0\n#define BIT_MASK_OCP_WINDOW_8822C 0xffff\n#define BIT_OCP_WINDOW_8822C(x)                                                \\\n\t(((x) & BIT_MASK_OCP_WINDOW_8822C) << BIT_SHIFT_OCP_WINDOW_8822C)\n#define BITS_OCP_WINDOW_8822C                                                  \\\n\t(BIT_MASK_OCP_WINDOW_8822C << BIT_SHIFT_OCP_WINDOW_8822C)\n#define BIT_CLEAR_OCP_WINDOW_8822C(x) ((x) & (~BITS_OCP_WINDOW_8822C))\n#define BIT_GET_OCP_WINDOW_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_OCP_WINDOW_8822C) & BIT_MASK_OCP_WINDOW_8822C)\n#define BIT_SET_OCP_WINDOW_8822C(x, v)                                         \\\n\t(BIT_CLEAR_OCP_WINDOW_8822C(x) | BIT_OCP_WINDOW_8822C(v))\n\n/* 2 REG_RSV_CTRL_8822C */\n#define BIT_HREG_DBG_8822C BIT(23)\n#define BIT_WLMCUIOIF_8822C BIT(8)\n#define BIT_LOCK_ALL_EN_8822C BIT(7)\n#define BIT_R_DIS_PRST_8822C BIT(6)\n#define BIT_WLOCK_1C_B6_8822C BIT(5)\n#define BIT_WLOCK_40_8822C BIT(4)\n#define BIT_WLOCK_08_8822C BIT(3)\n#define BIT_WLOCK_04_8822C BIT(2)\n#define BIT_WLOCK_00_8822C BIT(1)\n#define BIT_WLOCK_ALL_8822C BIT(0)\n\n/* 2 REG_RF_CTRL_8822C */\n#define BIT_RF_SDMRSTB_8822C BIT(2)\n#define BIT_RF_RSTB_8822C BIT(1)\n#define BIT_RF_EN_8822C BIT(0)\n\n/* 2 REG_AFE_LDO_CTRL_8822C */\n#define BIT_R_SYM_WLPON_EMEM1_EN_8822C BIT(31)\n#define BIT_R_SYM_WLPON_EMEM0_EN_8822C BIT(30)\n#define BIT_R_SYM_WLPOFF_P4EN_8822C BIT(28)\n#define BIT_R_SYM_WLPOFF_P3EN_8822C BIT(27)\n#define BIT_R_SYM_WLPOFF_P2EN_8822C BIT(26)\n#define BIT_R_SYM_WLPOFF_P1EN_8822C BIT(25)\n#define BIT_R_SYM_WLPOFF_EN_8822C BIT(24)\n#define BIT_R_SYM_WLPON_P3EN_8822C BIT(21)\n#define BIT_R_SYM_WLPON_P2EN_8822C BIT(20)\n#define BIT_R_SYM_WLPON_P1EN_8822C BIT(19)\n#define BIT_R_SYM_WLPON_EN_8822C BIT(18)\n#define BIT_R_SYM_LDOV12D_STBY_8822C BIT(16)\n#define BIT_R_SYM_WLBBOFF1_P4_EN_8822C BIT(9)\n#define BIT_R_SYM_WLBBOFF1_P3_EN_8822C BIT(8)\n#define BIT_R_SYM_WLBBOFF1_P2_EN_8822C BIT(7)\n#define BIT_R_SYM_WLBBOFF1_P1_EN_8822C BIT(6)\n#define BIT_R_SYM_WLBBOFF_P4_EN_8822C BIT(4)\n#define BIT_R_SYM_WLBBOFF_P3_EN_8822C BIT(3)\n#define BIT_R_SYM_WLBBOFF_P2_EN_8822C BIT(2)\n#define BIT_R_SYM_WLBBOFF_P1_EN_8822C BIT(1)\n#define BIT_R_SYM_WLBBOFF_EN_8822C BIT(0)\n\n/* 2 REG_AFE_CTRL1_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_MAC_CLK_SEL_8822C 20\n#define BIT_MASK_MAC_CLK_SEL_8822C 0x3\n#define BIT_MAC_CLK_SEL_8822C(x)                                               \\\n\t(((x) & BIT_MASK_MAC_CLK_SEL_8822C) << BIT_SHIFT_MAC_CLK_SEL_8822C)\n#define BITS_MAC_CLK_SEL_8822C                                                 \\\n\t(BIT_MASK_MAC_CLK_SEL_8822C << BIT_SHIFT_MAC_CLK_SEL_8822C)\n#define BIT_CLEAR_MAC_CLK_SEL_8822C(x) ((x) & (~BITS_MAC_CLK_SEL_8822C))\n#define BIT_GET_MAC_CLK_SEL_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_MAC_CLK_SEL_8822C) & BIT_MASK_MAC_CLK_SEL_8822C)\n#define BIT_SET_MAC_CLK_SEL_8822C(x, v)                                        \\\n\t(BIT_CLEAR_MAC_CLK_SEL_8822C(x) | BIT_MAC_CLK_SEL_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_ANAPARSW_POW_MAC_8822C */\n#define BIT_POW_LDO15_8822C BIT(2)\n#define BIT_POW_SW_8822C BIT(1)\n#define BIT_POW_LDO14_8822C BIT(0)\n\n/* 2 REG_ANAPARLDO_POW_MAC_8822C */\n#define BIT_LDOE25_POW_L_8822C BIT(0)\n\n/* 2 REG_ANAPAR_POW_MAC_8822C */\n#define BIT_DUMMY_V4_8822C BIT(7)\n#define BIT_DUMMY_V3_8822C BIT(6)\n#define BIT_DUMMY_V2_8822C BIT(5)\n#define BIT_DUMMY_V1_8822C BIT(4)\n#define BIT_POW_PC_LDO_PORT1_8822C BIT(3)\n#define BIT_POW_PC_LDO_PORT0_8822C BIT(2)\n#define BIT_POW_PLL_V1_8822C BIT(1)\n#define BIT_POW_POWER_CUT_POW_LDO_8822C BIT(0)\n\n/* 2 REG_ANAPAR_POW_XTAL_8822C */\n#define BIT_POW_XTAL_8822C BIT(1)\n#define BIT_POW_BG_8822C BIT(0)\n\n/* 2 REG_ANAPARLDO_MAC_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_REG_STANDBY_L_8822C BIT(19)\n#define BIT_PD_REGU_L_8822C BIT(18)\n#define BIT_EN_PC_BT_L_8822C BIT(17)\n\n#define BIT_SHIFT_REG_LDOADJ_L_8822C 13\n#define BIT_MASK_REG_LDOADJ_L_8822C 0xf\n#define BIT_REG_LDOADJ_L_8822C(x)                                              \\\n\t(((x) & BIT_MASK_REG_LDOADJ_L_8822C) << BIT_SHIFT_REG_LDOADJ_L_8822C)\n#define BITS_REG_LDOADJ_L_8822C                                                \\\n\t(BIT_MASK_REG_LDOADJ_L_8822C << BIT_SHIFT_REG_LDOADJ_L_8822C)\n#define BIT_CLEAR_REG_LDOADJ_L_8822C(x) ((x) & (~BITS_REG_LDOADJ_L_8822C))\n#define BIT_GET_REG_LDOADJ_L_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_REG_LDOADJ_L_8822C) & BIT_MASK_REG_LDOADJ_L_8822C)\n#define BIT_SET_REG_LDOADJ_L_8822C(x, v)                                       \\\n\t(BIT_CLEAR_REG_LDOADJ_L_8822C(x) | BIT_REG_LDOADJ_L_8822C(v))\n\n#define BIT_CK12M_EN_8822C BIT(11)\n#define BIT_CK12M_SEL_8822C BIT(10)\n#define BIT_EN_25_L_8822C BIT(9)\n#define BIT_EN_SLEEP_8822C BIT(8)\n\n#define BIT_SHIFT_LDOH12_V12ADJ_L_8822C 4\n#define BIT_MASK_LDOH12_V12ADJ_L_8822C 0xf\n#define BIT_LDOH12_V12ADJ_L_8822C(x)                                           \\\n\t(((x) & BIT_MASK_LDOH12_V12ADJ_L_8822C)                                \\\n\t << BIT_SHIFT_LDOH12_V12ADJ_L_8822C)\n#define BITS_LDOH12_V12ADJ_L_8822C                                             \\\n\t(BIT_MASK_LDOH12_V12ADJ_L_8822C << BIT_SHIFT_LDOH12_V12ADJ_L_8822C)\n#define BIT_CLEAR_LDOH12_V12ADJ_L_8822C(x) ((x) & (~BITS_LDOH12_V12ADJ_L_8822C))\n#define BIT_GET_LDOH12_V12ADJ_L_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_LDOH12_V12ADJ_L_8822C) &                            \\\n\t BIT_MASK_LDOH12_V12ADJ_L_8822C)\n#define BIT_SET_LDOH12_V12ADJ_L_8822C(x, v)                                    \\\n\t(BIT_CLEAR_LDOH12_V12ADJ_L_8822C(x) | BIT_LDOH12_V12ADJ_L_8822C(v))\n\n#define BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C 0\n#define BIT_MASK_LDOE25_V12ADJ_L_V1_8822C 0xf\n#define BIT_LDOE25_V12ADJ_L_V1_8822C(x)                                        \\\n\t(((x) & BIT_MASK_LDOE25_V12ADJ_L_V1_8822C)                             \\\n\t << BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C)\n#define BITS_LDOE25_V12ADJ_L_V1_8822C                                          \\\n\t(BIT_MASK_LDOE25_V12ADJ_L_V1_8822C                                     \\\n\t << BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C)\n#define BIT_CLEAR_LDOE25_V12ADJ_L_V1_8822C(x)                                  \\\n\t((x) & (~BITS_LDOE25_V12ADJ_L_V1_8822C))\n#define BIT_GET_LDOE25_V12ADJ_L_V1_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C) &                         \\\n\t BIT_MASK_LDOE25_V12ADJ_L_V1_8822C)\n#define BIT_SET_LDOE25_V12ADJ_L_V1_8822C(x, v)                                 \\\n\t(BIT_CLEAR_LDOE25_V12ADJ_L_V1_8822C(x) |                               \\\n\t BIT_LDOE25_V12ADJ_L_V1_8822C(v))\n\n/* 2 REG_EFUSE_CTRL_8822C */\n#define BIT_EF_FLAG_8822C BIT(31)\n\n#define BIT_SHIFT_EF_PGPD_8822C 28\n#define BIT_MASK_EF_PGPD_8822C 0x7\n#define BIT_EF_PGPD_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_EF_PGPD_8822C) << BIT_SHIFT_EF_PGPD_8822C)\n#define BITS_EF_PGPD_8822C (BIT_MASK_EF_PGPD_8822C << BIT_SHIFT_EF_PGPD_8822C)\n#define BIT_CLEAR_EF_PGPD_8822C(x) ((x) & (~BITS_EF_PGPD_8822C))\n#define BIT_GET_EF_PGPD_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_PGPD_8822C) & BIT_MASK_EF_PGPD_8822C)\n#define BIT_SET_EF_PGPD_8822C(x, v)                                            \\\n\t(BIT_CLEAR_EF_PGPD_8822C(x) | BIT_EF_PGPD_8822C(v))\n\n#define BIT_SHIFT_EF_RDT_8822C 24\n#define BIT_MASK_EF_RDT_8822C 0xf\n#define BIT_EF_RDT_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_EF_RDT_8822C) << BIT_SHIFT_EF_RDT_8822C)\n#define BITS_EF_RDT_8822C (BIT_MASK_EF_RDT_8822C << BIT_SHIFT_EF_RDT_8822C)\n#define BIT_CLEAR_EF_RDT_8822C(x) ((x) & (~BITS_EF_RDT_8822C))\n#define BIT_GET_EF_RDT_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_EF_RDT_8822C) & BIT_MASK_EF_RDT_8822C)\n#define BIT_SET_EF_RDT_8822C(x, v)                                             \\\n\t(BIT_CLEAR_EF_RDT_8822C(x) | BIT_EF_RDT_8822C(v))\n\n#define BIT_SHIFT_EF_PGTS_8822C 20\n#define BIT_MASK_EF_PGTS_8822C 0xf\n#define BIT_EF_PGTS_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_EF_PGTS_8822C) << BIT_SHIFT_EF_PGTS_8822C)\n#define BITS_EF_PGTS_8822C (BIT_MASK_EF_PGTS_8822C << BIT_SHIFT_EF_PGTS_8822C)\n#define BIT_CLEAR_EF_PGTS_8822C(x) ((x) & (~BITS_EF_PGTS_8822C))\n#define BIT_GET_EF_PGTS_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_PGTS_8822C) & BIT_MASK_EF_PGTS_8822C)\n#define BIT_SET_EF_PGTS_8822C(x, v)                                            \\\n\t(BIT_CLEAR_EF_PGTS_8822C(x) | BIT_EF_PGTS_8822C(v))\n\n#define BIT_EF_PDWN_8822C BIT(19)\n#define BIT_EF_ALDEN_8822C BIT(18)\n\n#define BIT_SHIFT_EF_ADDR_8822C 8\n#define BIT_MASK_EF_ADDR_8822C 0x3ff\n#define BIT_EF_ADDR_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_EF_ADDR_8822C) << BIT_SHIFT_EF_ADDR_8822C)\n#define BITS_EF_ADDR_8822C (BIT_MASK_EF_ADDR_8822C << BIT_SHIFT_EF_ADDR_8822C)\n#define BIT_CLEAR_EF_ADDR_8822C(x) ((x) & (~BITS_EF_ADDR_8822C))\n#define BIT_GET_EF_ADDR_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_ADDR_8822C) & BIT_MASK_EF_ADDR_8822C)\n#define BIT_SET_EF_ADDR_8822C(x, v)                                            \\\n\t(BIT_CLEAR_EF_ADDR_8822C(x) | BIT_EF_ADDR_8822C(v))\n\n#define BIT_SHIFT_EF_DATA_8822C 0\n#define BIT_MASK_EF_DATA_8822C 0xff\n#define BIT_EF_DATA_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_EF_DATA_8822C) << BIT_SHIFT_EF_DATA_8822C)\n#define BITS_EF_DATA_8822C (BIT_MASK_EF_DATA_8822C << BIT_SHIFT_EF_DATA_8822C)\n#define BIT_CLEAR_EF_DATA_8822C(x) ((x) & (~BITS_EF_DATA_8822C))\n#define BIT_GET_EF_DATA_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_DATA_8822C) & BIT_MASK_EF_DATA_8822C)\n#define BIT_SET_EF_DATA_8822C(x, v)                                            \\\n\t(BIT_CLEAR_EF_DATA_8822C(x) | BIT_EF_DATA_8822C(v))\n\n/* 2 REG_LDO_EFUSE_CTRL_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_EF_CRES_SEL_8822C BIT(26)\n\n#define BIT_SHIFT_EF_SCAN_START_V1_8822C 16\n#define BIT_MASK_EF_SCAN_START_V1_8822C 0x3ff\n#define BIT_EF_SCAN_START_V1_8822C(x)                                          \\\n\t(((x) & BIT_MASK_EF_SCAN_START_V1_8822C)                               \\\n\t << BIT_SHIFT_EF_SCAN_START_V1_8822C)\n#define BITS_EF_SCAN_START_V1_8822C                                            \\\n\t(BIT_MASK_EF_SCAN_START_V1_8822C << BIT_SHIFT_EF_SCAN_START_V1_8822C)\n#define BIT_CLEAR_EF_SCAN_START_V1_8822C(x)                                    \\\n\t((x) & (~BITS_EF_SCAN_START_V1_8822C))\n#define BIT_GET_EF_SCAN_START_V1_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_EF_SCAN_START_V1_8822C) &                           \\\n\t BIT_MASK_EF_SCAN_START_V1_8822C)\n#define BIT_SET_EF_SCAN_START_V1_8822C(x, v)                                   \\\n\t(BIT_CLEAR_EF_SCAN_START_V1_8822C(x) | BIT_EF_SCAN_START_V1_8822C(v))\n\n#define BIT_SHIFT_EF_SCAN_END_8822C 12\n#define BIT_MASK_EF_SCAN_END_8822C 0xf\n#define BIT_EF_SCAN_END_8822C(x)                                               \\\n\t(((x) & BIT_MASK_EF_SCAN_END_8822C) << BIT_SHIFT_EF_SCAN_END_8822C)\n#define BITS_EF_SCAN_END_8822C                                                 \\\n\t(BIT_MASK_EF_SCAN_END_8822C << BIT_SHIFT_EF_SCAN_END_8822C)\n#define BIT_CLEAR_EF_SCAN_END_8822C(x) ((x) & (~BITS_EF_SCAN_END_8822C))\n#define BIT_GET_EF_SCAN_END_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_EF_SCAN_END_8822C) & BIT_MASK_EF_SCAN_END_8822C)\n#define BIT_SET_EF_SCAN_END_8822C(x, v)                                        \\\n\t(BIT_CLEAR_EF_SCAN_END_8822C(x) | BIT_EF_SCAN_END_8822C(v))\n\n#define BIT_EF_PD_DIS_8822C BIT(11)\n\n#define BIT_SHIFT_EF_CELL_SEL_8822C 8\n#define BIT_MASK_EF_CELL_SEL_8822C 0x3\n#define BIT_EF_CELL_SEL_8822C(x)                                               \\\n\t(((x) & BIT_MASK_EF_CELL_SEL_8822C) << BIT_SHIFT_EF_CELL_SEL_8822C)\n#define BITS_EF_CELL_SEL_8822C                                                 \\\n\t(BIT_MASK_EF_CELL_SEL_8822C << BIT_SHIFT_EF_CELL_SEL_8822C)\n#define BIT_CLEAR_EF_CELL_SEL_8822C(x) ((x) & (~BITS_EF_CELL_SEL_8822C))\n#define BIT_GET_EF_CELL_SEL_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_EF_CELL_SEL_8822C) & BIT_MASK_EF_CELL_SEL_8822C)\n#define BIT_SET_EF_CELL_SEL_8822C(x, v)                                        \\\n\t(BIT_CLEAR_EF_CELL_SEL_8822C(x) | BIT_EF_CELL_SEL_8822C(v))\n\n#define BIT_EF_TRPT_8822C BIT(7)\n\n#define BIT_SHIFT_EF_TTHD_8822C 0\n#define BIT_MASK_EF_TTHD_8822C 0x7f\n#define BIT_EF_TTHD_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_EF_TTHD_8822C) << BIT_SHIFT_EF_TTHD_8822C)\n#define BITS_EF_TTHD_8822C (BIT_MASK_EF_TTHD_8822C << BIT_SHIFT_EF_TTHD_8822C)\n#define BIT_CLEAR_EF_TTHD_8822C(x) ((x) & (~BITS_EF_TTHD_8822C))\n#define BIT_GET_EF_TTHD_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_EF_TTHD_8822C) & BIT_MASK_EF_TTHD_8822C)\n#define BIT_SET_EF_TTHD_8822C(x, v)                                            \\\n\t(BIT_CLEAR_EF_TTHD_8822C(x) | BIT_EF_TTHD_8822C(v))\n\n/* 2 REG_PWR_OPTION_CTRL_8822C */\n\n#define BIT_SHIFT_DBG_SEL_V1_8822C 16\n#define BIT_MASK_DBG_SEL_V1_8822C 0xff\n#define BIT_DBG_SEL_V1_8822C(x)                                                \\\n\t(((x) & BIT_MASK_DBG_SEL_V1_8822C) << BIT_SHIFT_DBG_SEL_V1_8822C)\n#define BITS_DBG_SEL_V1_8822C                                                  \\\n\t(BIT_MASK_DBG_SEL_V1_8822C << BIT_SHIFT_DBG_SEL_V1_8822C)\n#define BIT_CLEAR_DBG_SEL_V1_8822C(x) ((x) & (~BITS_DBG_SEL_V1_8822C))\n#define BIT_GET_DBG_SEL_V1_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DBG_SEL_V1_8822C) & BIT_MASK_DBG_SEL_V1_8822C)\n#define BIT_SET_DBG_SEL_V1_8822C(x, v)                                         \\\n\t(BIT_CLEAR_DBG_SEL_V1_8822C(x) | BIT_DBG_SEL_V1_8822C(v))\n\n#define BIT_SHIFT_DBG_SEL_BYTE_8822C 14\n#define BIT_MASK_DBG_SEL_BYTE_8822C 0x3\n#define BIT_DBG_SEL_BYTE_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DBG_SEL_BYTE_8822C) << BIT_SHIFT_DBG_SEL_BYTE_8822C)\n#define BITS_DBG_SEL_BYTE_8822C                                                \\\n\t(BIT_MASK_DBG_SEL_BYTE_8822C << BIT_SHIFT_DBG_SEL_BYTE_8822C)\n#define BIT_CLEAR_DBG_SEL_BYTE_8822C(x) ((x) & (~BITS_DBG_SEL_BYTE_8822C))\n#define BIT_GET_DBG_SEL_BYTE_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DBG_SEL_BYTE_8822C) & BIT_MASK_DBG_SEL_BYTE_8822C)\n#define BIT_SET_DBG_SEL_BYTE_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DBG_SEL_BYTE_8822C(x) | BIT_DBG_SEL_BYTE_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_SYSON_DBG_PAD_E2_8822C BIT(11)\n#define BIT_SYSON_LED_PAD_E2_8822C BIT(10)\n#define BIT_SYSON_GPEE_PAD_E2_8822C BIT(9)\n#define BIT_SYSON_PCI_PAD_E2_8822C BIT(8)\n#define BIT_AUTO_SW_LDO_VOL_EN_8822C BIT(7)\n\n#define BIT_SHIFT_SYSON_SPS0WWV_WT_8822C 4\n#define BIT_MASK_SYSON_SPS0WWV_WT_8822C 0x3\n#define BIT_SYSON_SPS0WWV_WT_8822C(x)                                          \\\n\t(((x) & BIT_MASK_SYSON_SPS0WWV_WT_8822C)                               \\\n\t << BIT_SHIFT_SYSON_SPS0WWV_WT_8822C)\n#define BITS_SYSON_SPS0WWV_WT_8822C                                            \\\n\t(BIT_MASK_SYSON_SPS0WWV_WT_8822C << BIT_SHIFT_SYSON_SPS0WWV_WT_8822C)\n#define BIT_CLEAR_SYSON_SPS0WWV_WT_8822C(x)                                    \\\n\t((x) & (~BITS_SYSON_SPS0WWV_WT_8822C))\n#define BIT_GET_SYSON_SPS0WWV_WT_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8822C) &                           \\\n\t BIT_MASK_SYSON_SPS0WWV_WT_8822C)\n#define BIT_SET_SYSON_SPS0WWV_WT_8822C(x, v)                                   \\\n\t(BIT_CLEAR_SYSON_SPS0WWV_WT_8822C(x) | BIT_SYSON_SPS0WWV_WT_8822C(v))\n\n#define BIT_SHIFT_SYSON_SPS0LDO_WT_8822C 2\n#define BIT_MASK_SYSON_SPS0LDO_WT_8822C 0x3\n#define BIT_SYSON_SPS0LDO_WT_8822C(x)                                          \\\n\t(((x) & BIT_MASK_SYSON_SPS0LDO_WT_8822C)                               \\\n\t << BIT_SHIFT_SYSON_SPS0LDO_WT_8822C)\n#define BITS_SYSON_SPS0LDO_WT_8822C                                            \\\n\t(BIT_MASK_SYSON_SPS0LDO_WT_8822C << BIT_SHIFT_SYSON_SPS0LDO_WT_8822C)\n#define BIT_CLEAR_SYSON_SPS0LDO_WT_8822C(x)                                    \\\n\t((x) & (~BITS_SYSON_SPS0LDO_WT_8822C))\n#define BIT_GET_SYSON_SPS0LDO_WT_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8822C) &                           \\\n\t BIT_MASK_SYSON_SPS0LDO_WT_8822C)\n#define BIT_SET_SYSON_SPS0LDO_WT_8822C(x, v)                                   \\\n\t(BIT_CLEAR_SYSON_SPS0LDO_WT_8822C(x) | BIT_SYSON_SPS0LDO_WT_8822C(v))\n\n#define BIT_SHIFT_SYSON_RCLK_SCALE_8822C 0\n#define BIT_MASK_SYSON_RCLK_SCALE_8822C 0x3\n#define BIT_SYSON_RCLK_SCALE_8822C(x)                                          \\\n\t(((x) & BIT_MASK_SYSON_RCLK_SCALE_8822C)                               \\\n\t << BIT_SHIFT_SYSON_RCLK_SCALE_8822C)\n#define BITS_SYSON_RCLK_SCALE_8822C                                            \\\n\t(BIT_MASK_SYSON_RCLK_SCALE_8822C << BIT_SHIFT_SYSON_RCLK_SCALE_8822C)\n#define BIT_CLEAR_SYSON_RCLK_SCALE_8822C(x)                                    \\\n\t((x) & (~BITS_SYSON_RCLK_SCALE_8822C))\n#define BIT_GET_SYSON_RCLK_SCALE_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8822C) &                           \\\n\t BIT_MASK_SYSON_RCLK_SCALE_8822C)\n#define BIT_SET_SYSON_RCLK_SCALE_8822C(x, v)                                   \\\n\t(BIT_CLEAR_SYSON_RCLK_SCALE_8822C(x) | BIT_SYSON_RCLK_SCALE_8822C(v))\n\n/* 2 REG_CAL_TIMER_8822C */\n\n#define BIT_SHIFT_MATCH_CNT_8822C 8\n#define BIT_MASK_MATCH_CNT_8822C 0xff\n#define BIT_MATCH_CNT_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_MATCH_CNT_8822C) << BIT_SHIFT_MATCH_CNT_8822C)\n#define BITS_MATCH_CNT_8822C                                                   \\\n\t(BIT_MASK_MATCH_CNT_8822C << BIT_SHIFT_MATCH_CNT_8822C)\n#define BIT_CLEAR_MATCH_CNT_8822C(x) ((x) & (~BITS_MATCH_CNT_8822C))\n#define BIT_GET_MATCH_CNT_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MATCH_CNT_8822C) & BIT_MASK_MATCH_CNT_8822C)\n#define BIT_SET_MATCH_CNT_8822C(x, v)                                          \\\n\t(BIT_CLEAR_MATCH_CNT_8822C(x) | BIT_MATCH_CNT_8822C(v))\n\n#define BIT_SHIFT_CAL_SCAL_8822C 0\n#define BIT_MASK_CAL_SCAL_8822C 0xff\n#define BIT_CAL_SCAL_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_CAL_SCAL_8822C) << BIT_SHIFT_CAL_SCAL_8822C)\n#define BITS_CAL_SCAL_8822C                                                    \\\n\t(BIT_MASK_CAL_SCAL_8822C << BIT_SHIFT_CAL_SCAL_8822C)\n#define BIT_CLEAR_CAL_SCAL_8822C(x) ((x) & (~BITS_CAL_SCAL_8822C))\n#define BIT_GET_CAL_SCAL_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_CAL_SCAL_8822C) & BIT_MASK_CAL_SCAL_8822C)\n#define BIT_SET_CAL_SCAL_8822C(x, v)                                           \\\n\t(BIT_CLEAR_CAL_SCAL_8822C(x) | BIT_CAL_SCAL_8822C(v))\n\n/* 2 REG_ACLK_MON_8822C */\n\n#define BIT_SHIFT_RCLK_MON_8822C 5\n#define BIT_MASK_RCLK_MON_8822C 0x7ff\n#define BIT_RCLK_MON_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_RCLK_MON_8822C) << BIT_SHIFT_RCLK_MON_8822C)\n#define BITS_RCLK_MON_8822C                                                    \\\n\t(BIT_MASK_RCLK_MON_8822C << BIT_SHIFT_RCLK_MON_8822C)\n#define BIT_CLEAR_RCLK_MON_8822C(x) ((x) & (~BITS_RCLK_MON_8822C))\n#define BIT_GET_RCLK_MON_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RCLK_MON_8822C) & BIT_MASK_RCLK_MON_8822C)\n#define BIT_SET_RCLK_MON_8822C(x, v)                                           \\\n\t(BIT_CLEAR_RCLK_MON_8822C(x) | BIT_RCLK_MON_8822C(v))\n\n#define BIT_CAL_EN_8822C BIT(4)\n\n#define BIT_SHIFT_DPSTU_8822C 2\n#define BIT_MASK_DPSTU_8822C 0x3\n#define BIT_DPSTU_8822C(x)                                                     \\\n\t(((x) & BIT_MASK_DPSTU_8822C) << BIT_SHIFT_DPSTU_8822C)\n#define BITS_DPSTU_8822C (BIT_MASK_DPSTU_8822C << BIT_SHIFT_DPSTU_8822C)\n#define BIT_CLEAR_DPSTU_8822C(x) ((x) & (~BITS_DPSTU_8822C))\n#define BIT_GET_DPSTU_8822C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_DPSTU_8822C) & BIT_MASK_DPSTU_8822C)\n#define BIT_SET_DPSTU_8822C(x, v)                                              \\\n\t(BIT_CLEAR_DPSTU_8822C(x) | BIT_DPSTU_8822C(v))\n\n#define BIT_SUS_16X_8822C BIT(1)\n\n/* 2 REG_GPIO_MUXCFG_2_8822C */\n#define BIT_SOUT_GPIO8_8822C BIT(7)\n#define BIT_SOUT_GPIO5_8822C BIT(6)\n#define BIT_RFE_CTRL_5_GPIO14_V1_8822C BIT(5)\n#define BIT_RFE_CTRL_10_GPIO13_V1_8822C BIT(4)\n#define BIT_RFE_CTRL_11_GPIO4_V1_8822C BIT(3)\n#define BIT_RFE_CTRL_5_GPIO14_8822C BIT(2)\n#define BIT_RFE_CTRL_10_GPIO13_8822C BIT(1)\n#define BIT_RFE_CTRL_11_GPIO4_8822C BIT(0)\n\n/* 2 REG_GPIO_MUXCFG_8822C */\n#define BIT_RFE_CTRL_3_GPIO12_8822C BIT(31)\n#define BIT_BT_RFE_CTRL_5_GPIO12_8822C BIT(30)\n#define BIT_S0_TRSW_GPIO12_8822C BIT(29)\n#define BIT_RFE_CTRL_9_GPIO13_8822C BIT(28)\n#define BIT_RFE_CTRL_9_GPIO12_8822C BIT(27)\n#define BIT_RFE_CTRL_8_GPIO4_8822C BIT(26)\n#define BIT_BT_RFE_CTRL_1_GPIO13_8822C BIT(25)\n#define BIT_BT_RFE_CTRL_1_GPIO12_8822C BIT(24)\n#define BIT_BT_RFE_CTRL_0_GPIO4_8822C BIT(23)\n#define BIT_ANTSW_GPIO13_8822C BIT(22)\n#define BIT_ANTSW_GPIO12_8822C BIT(21)\n#define BIT_ANTSWB_GPIO4_8822C BIT(20)\n#define BIT_FSPI_EN_8822C BIT(19)\n#define BIT_WL_RTS_EXT_32K_SEL_8822C BIT(18)\n#define BIT_WLBT_DPDT_SEL_EN_8822C BIT(17)\n#define BIT_WLBT_LNAON_SEL_EN_8822C BIT(16)\n#define BIT_SIC_LBK_8822C BIT(15)\n#define BIT_ENHTP_8822C BIT(14)\n#define BIT_BT_AOD_GPIO3_8822C BIT(13)\n#define BIT_ENSIC_8822C BIT(12)\n#define BIT_SIC_SWRST_8822C BIT(11)\n#define BIT_PO_WIFI_PTA_PINS_8822C BIT(10)\n#define BIT_PO_BT_PTA_PINS_8822C BIT(9)\n#define BIT_ENUART_8822C BIT(8)\n\n#define BIT_SHIFT_BTMODE_8822C 6\n#define BIT_MASK_BTMODE_8822C 0x3\n#define BIT_BTMODE_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_BTMODE_8822C) << BIT_SHIFT_BTMODE_8822C)\n#define BITS_BTMODE_8822C (BIT_MASK_BTMODE_8822C << BIT_SHIFT_BTMODE_8822C)\n#define BIT_CLEAR_BTMODE_8822C(x) ((x) & (~BITS_BTMODE_8822C))\n#define BIT_GET_BTMODE_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_BTMODE_8822C) & BIT_MASK_BTMODE_8822C)\n#define BIT_SET_BTMODE_8822C(x, v)                                             \\\n\t(BIT_CLEAR_BTMODE_8822C(x) | BIT_BTMODE_8822C(v))\n\n#define BIT_ENBT_8822C BIT(5)\n#define BIT_EROM_EN_8822C BIT(4)\n#define BIT_WLRFE_6_7_EN_8822C BIT(3)\n#define BIT_WLRFE_4_5_EN_8822C BIT(2)\n\n#define BIT_SHIFT_GPIOSEL_8822C 0\n#define BIT_MASK_GPIOSEL_8822C 0x3\n#define BIT_GPIOSEL_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_GPIOSEL_8822C) << BIT_SHIFT_GPIOSEL_8822C)\n#define BITS_GPIOSEL_8822C (BIT_MASK_GPIOSEL_8822C << BIT_SHIFT_GPIOSEL_8822C)\n#define BIT_CLEAR_GPIOSEL_8822C(x) ((x) & (~BITS_GPIOSEL_8822C))\n#define BIT_GET_GPIOSEL_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_GPIOSEL_8822C) & BIT_MASK_GPIOSEL_8822C)\n#define BIT_SET_GPIOSEL_8822C(x, v)                                            \\\n\t(BIT_CLEAR_GPIOSEL_8822C(x) | BIT_GPIOSEL_8822C(v))\n\n/* 2 REG_GPIO_PIN_CTRL_8822C */\n\n#define BIT_SHIFT_GPIO_MOD_7_TO_0_8822C 24\n#define BIT_MASK_GPIO_MOD_7_TO_0_8822C 0xff\n#define BIT_GPIO_MOD_7_TO_0_8822C(x)                                           \\\n\t(((x) & BIT_MASK_GPIO_MOD_7_TO_0_8822C)                                \\\n\t << BIT_SHIFT_GPIO_MOD_7_TO_0_8822C)\n#define BITS_GPIO_MOD_7_TO_0_8822C                                             \\\n\t(BIT_MASK_GPIO_MOD_7_TO_0_8822C << BIT_SHIFT_GPIO_MOD_7_TO_0_8822C)\n#define BIT_CLEAR_GPIO_MOD_7_TO_0_8822C(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8822C))\n#define BIT_GET_GPIO_MOD_7_TO_0_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8822C) &                            \\\n\t BIT_MASK_GPIO_MOD_7_TO_0_8822C)\n#define BIT_SET_GPIO_MOD_7_TO_0_8822C(x, v)                                    \\\n\t(BIT_CLEAR_GPIO_MOD_7_TO_0_8822C(x) | BIT_GPIO_MOD_7_TO_0_8822C(v))\n\n#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C 16\n#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C 0xff\n#define BIT_GPIO_IO_SEL_7_TO_0_8822C(x)                                        \\\n\t(((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C)                             \\\n\t << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C)\n#define BITS_GPIO_IO_SEL_7_TO_0_8822C                                          \\\n\t(BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C                                     \\\n\t << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C)\n#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822C(x)                                  \\\n\t((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8822C))\n#define BIT_GET_GPIO_IO_SEL_7_TO_0_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C) &                         \\\n\t BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C)\n#define BIT_SET_GPIO_IO_SEL_7_TO_0_8822C(x, v)                                 \\\n\t(BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822C(x) |                               \\\n\t BIT_GPIO_IO_SEL_7_TO_0_8822C(v))\n\n#define BIT_SHIFT_GPIO_OUT_7_TO_0_8822C 8\n#define BIT_MASK_GPIO_OUT_7_TO_0_8822C 0xff\n#define BIT_GPIO_OUT_7_TO_0_8822C(x)                                           \\\n\t(((x) & BIT_MASK_GPIO_OUT_7_TO_0_8822C)                                \\\n\t << BIT_SHIFT_GPIO_OUT_7_TO_0_8822C)\n#define BITS_GPIO_OUT_7_TO_0_8822C                                             \\\n\t(BIT_MASK_GPIO_OUT_7_TO_0_8822C << BIT_SHIFT_GPIO_OUT_7_TO_0_8822C)\n#define BIT_CLEAR_GPIO_OUT_7_TO_0_8822C(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8822C))\n#define BIT_GET_GPIO_OUT_7_TO_0_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8822C) &                            \\\n\t BIT_MASK_GPIO_OUT_7_TO_0_8822C)\n#define BIT_SET_GPIO_OUT_7_TO_0_8822C(x, v)                                    \\\n\t(BIT_CLEAR_GPIO_OUT_7_TO_0_8822C(x) | BIT_GPIO_OUT_7_TO_0_8822C(v))\n\n#define BIT_SHIFT_GPIO_IN_7_TO_0_8822C 0\n#define BIT_MASK_GPIO_IN_7_TO_0_8822C 0xff\n#define BIT_GPIO_IN_7_TO_0_8822C(x)                                            \\\n\t(((x) & BIT_MASK_GPIO_IN_7_TO_0_8822C)                                 \\\n\t << BIT_SHIFT_GPIO_IN_7_TO_0_8822C)\n#define BITS_GPIO_IN_7_TO_0_8822C                                              \\\n\t(BIT_MASK_GPIO_IN_7_TO_0_8822C << BIT_SHIFT_GPIO_IN_7_TO_0_8822C)\n#define BIT_CLEAR_GPIO_IN_7_TO_0_8822C(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8822C))\n#define BIT_GET_GPIO_IN_7_TO_0_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8822C) &                             \\\n\t BIT_MASK_GPIO_IN_7_TO_0_8822C)\n#define BIT_SET_GPIO_IN_7_TO_0_8822C(x, v)                                     \\\n\t(BIT_CLEAR_GPIO_IN_7_TO_0_8822C(x) | BIT_GPIO_IN_7_TO_0_8822C(v))\n\n/* 2 REG_GPIO_INTM_8822C */\n\n#define BIT_SHIFT_MUXDBG_SEL_8822C 30\n#define BIT_MASK_MUXDBG_SEL_8822C 0x3\n#define BIT_MUXDBG_SEL_8822C(x)                                                \\\n\t(((x) & BIT_MASK_MUXDBG_SEL_8822C) << BIT_SHIFT_MUXDBG_SEL_8822C)\n#define BITS_MUXDBG_SEL_8822C                                                  \\\n\t(BIT_MASK_MUXDBG_SEL_8822C << BIT_SHIFT_MUXDBG_SEL_8822C)\n#define BIT_CLEAR_MUXDBG_SEL_8822C(x) ((x) & (~BITS_MUXDBG_SEL_8822C))\n#define BIT_GET_MUXDBG_SEL_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_MUXDBG_SEL_8822C) & BIT_MASK_MUXDBG_SEL_8822C)\n#define BIT_SET_MUXDBG_SEL_8822C(x, v)                                         \\\n\t(BIT_CLEAR_MUXDBG_SEL_8822C(x) | BIT_MUXDBG_SEL_8822C(v))\n\n#define BIT_EXTWOL_SEL_8822C BIT(17)\n#define BIT_EXTWOL_EN_8822C BIT(16)\n#define BIT_GPIOF_INT_MD_8822C BIT(15)\n#define BIT_GPIOE_INT_MD_8822C BIT(14)\n#define BIT_GPIOD_INT_MD_8822C BIT(13)\n#define BIT_GPIOF_INT_MD_8822C BIT(15)\n#define BIT_GPIOE_INT_MD_8822C BIT(14)\n#define BIT_GPIOD_INT_MD_8822C BIT(13)\n#define BIT_GPIOC_INT_MD_8822C BIT(12)\n#define BIT_GPIOB_INT_MD_8822C BIT(11)\n#define BIT_GPIOA_INT_MD_8822C BIT(10)\n#define BIT_GPIO9_INT_MD_8822C BIT(9)\n#define BIT_GPIO8_INT_MD_8822C BIT(8)\n#define BIT_GPIO7_INT_MD_8822C BIT(7)\n#define BIT_GPIO6_INT_MD_8822C BIT(6)\n#define BIT_GPIO5_INT_MD_8822C BIT(5)\n#define BIT_GPIO4_INT_MD_8822C BIT(4)\n#define BIT_GPIO3_INT_MD_8822C BIT(3)\n#define BIT_GPIO2_INT_MD_8822C BIT(2)\n#define BIT_GPIO1_INT_MD_8822C BIT(1)\n#define BIT_GPIO0_INT_MD_8822C BIT(0)\n\n/* 2 REG_LED_CFG_8822C */\n#define BIT_MAILBOX_1WIRE_GPIO_CFG_8822C BIT(31)\n#define BIT_BT_RF_GPIO_CFG_8822C BIT(30)\n#define BIT_BT_SDIO_INT_GPIO_CFG_8822C BIT(29)\n#define BIT_MAILBOX_3WIRE_GPIO_CFG_8822C BIT(28)\n#define BIT_WLBT_PAPE_SEL_EN_8822C BIT(27)\n#define BIT_LNAON_SEL_EN_8822C BIT(26)\n#define BIT_PAPE_SEL_EN_8822C BIT(25)\n#define BIT_DPDT_WLBT_SEL_8822C BIT(24)\n#define BIT_DPDT_SEL_EN_8822C BIT(23)\n#define BIT_GPIO13_14_WL_CTRL_EN_8822C BIT(22)\n#define BIT_LED2DIS_8822C BIT(21)\n#define BIT_LED2PL_8822C BIT(20)\n#define BIT_LED2SV_8822C BIT(19)\n\n#define BIT_SHIFT_LED2CM_8822C 16\n#define BIT_MASK_LED2CM_8822C 0x7\n#define BIT_LED2CM_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_LED2CM_8822C) << BIT_SHIFT_LED2CM_8822C)\n#define BITS_LED2CM_8822C (BIT_MASK_LED2CM_8822C << BIT_SHIFT_LED2CM_8822C)\n#define BIT_CLEAR_LED2CM_8822C(x) ((x) & (~BITS_LED2CM_8822C))\n#define BIT_GET_LED2CM_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_LED2CM_8822C) & BIT_MASK_LED2CM_8822C)\n#define BIT_SET_LED2CM_8822C(x, v)                                             \\\n\t(BIT_CLEAR_LED2CM_8822C(x) | BIT_LED2CM_8822C(v))\n\n#define BIT_LED1DIS_8822C BIT(15)\n#define BIT_LED1PL_8822C BIT(12)\n#define BIT_LED1SV_8822C BIT(11)\n\n#define BIT_SHIFT_LED1CM_8822C 8\n#define BIT_MASK_LED1CM_8822C 0x7\n#define BIT_LED1CM_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_LED1CM_8822C) << BIT_SHIFT_LED1CM_8822C)\n#define BITS_LED1CM_8822C (BIT_MASK_LED1CM_8822C << BIT_SHIFT_LED1CM_8822C)\n#define BIT_CLEAR_LED1CM_8822C(x) ((x) & (~BITS_LED1CM_8822C))\n#define BIT_GET_LED1CM_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_LED1CM_8822C) & BIT_MASK_LED1CM_8822C)\n#define BIT_SET_LED1CM_8822C(x, v)                                             \\\n\t(BIT_CLEAR_LED1CM_8822C(x) | BIT_LED1CM_8822C(v))\n\n#define BIT_LED0DIS_8822C BIT(7)\n\n#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C 5\n#define BIT_MASK_AFE_LDO_SWR_CHECK_8822C 0x3\n#define BIT_AFE_LDO_SWR_CHECK_8822C(x)                                         \\\n\t(((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8822C)                              \\\n\t << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C)\n#define BITS_AFE_LDO_SWR_CHECK_8822C                                           \\\n\t(BIT_MASK_AFE_LDO_SWR_CHECK_8822C << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C)\n#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8822C(x)                                   \\\n\t((x) & (~BITS_AFE_LDO_SWR_CHECK_8822C))\n#define BIT_GET_AFE_LDO_SWR_CHECK_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C) &                          \\\n\t BIT_MASK_AFE_LDO_SWR_CHECK_8822C)\n#define BIT_SET_AFE_LDO_SWR_CHECK_8822C(x, v)                                  \\\n\t(BIT_CLEAR_AFE_LDO_SWR_CHECK_8822C(x) | BIT_AFE_LDO_SWR_CHECK_8822C(v))\n\n#define BIT_LED0PL_8822C BIT(4)\n#define BIT_LED0SV_8822C BIT(3)\n\n#define BIT_SHIFT_LED0CM_8822C 0\n#define BIT_MASK_LED0CM_8822C 0x7\n#define BIT_LED0CM_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_LED0CM_8822C) << BIT_SHIFT_LED0CM_8822C)\n#define BITS_LED0CM_8822C (BIT_MASK_LED0CM_8822C << BIT_SHIFT_LED0CM_8822C)\n#define BIT_CLEAR_LED0CM_8822C(x) ((x) & (~BITS_LED0CM_8822C))\n#define BIT_GET_LED0CM_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_LED0CM_8822C) & BIT_MASK_LED0CM_8822C)\n#define BIT_SET_LED0CM_8822C(x, v)                                             \\\n\t(BIT_CLEAR_LED0CM_8822C(x) | BIT_LED0CM_8822C(v))\n\n/* 2 REG_FSIMR_8822C */\n#define BIT_FS_PDNINT_EN_8822C BIT(31)\n#define BIT_FS_SPS_OCP_INT_EN_8822C BIT(29)\n#define BIT_FS_PWMERR_INT_EN_8822C BIT(28)\n#define BIT_FS_GPIOF_INT_EN_8822C BIT(27)\n#define BIT_FS_GPIOE_INT_EN_8822C BIT(26)\n#define BIT_FS_GPIOD_INT_EN_8822C BIT(25)\n#define BIT_FS_GPIOC_INT_EN_8822C BIT(24)\n#define BIT_FS_GPIOB_INT_EN_8822C BIT(23)\n#define BIT_FS_GPIOA_INT_EN_8822C BIT(22)\n#define BIT_FS_GPIO9_INT_EN_8822C BIT(21)\n#define BIT_FS_GPIO8_INT_EN_8822C BIT(20)\n#define BIT_FS_GPIO7_INT_EN_8822C BIT(19)\n#define BIT_FS_GPIO6_INT_EN_8822C BIT(18)\n#define BIT_FS_GPIO5_INT_EN_8822C BIT(17)\n#define BIT_FS_GPIO4_INT_EN_8822C BIT(16)\n#define BIT_FS_GPIO3_INT_EN_8822C BIT(15)\n#define BIT_FS_GPIO2_INT_EN_8822C BIT(14)\n#define BIT_FS_GPIO1_INT_EN_8822C BIT(13)\n#define BIT_FS_GPIO0_INT_EN_8822C BIT(12)\n#define BIT_FS_HCI_SUS_EN_8822C BIT(11)\n#define BIT_FS_HCI_RES_EN_8822C BIT(10)\n#define BIT_FS_HCI_RESET_EN_8822C BIT(9)\n#define BIT_USB_SCSI_CMD_EN_8822C BIT(8)\n#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8822C BIT(7)\n#define BIT_ACT2RECOVERY_INT_EN_V1_8822C BIT(6)\n#define BIT_GEN1GEN2_SWITCH_8822C BIT(5)\n#define BIT_HCI_TXDMA_REQ_HIMR_8822C BIT(4)\n#define BIT_FS_32K_LEAVE_SETTING_MAK_8822C BIT(3)\n#define BIT_FS_32K_ENTER_SETTING_MAK_8822C BIT(2)\n#define BIT_FS_USB_LPMRSM_MSK_8822C BIT(1)\n#define BIT_FS_USB_LPMINT_MSK_8822C BIT(0)\n\n/* 2 REG_FSISR_8822C */\n#define BIT_FS_PDNINT_8822C BIT(31)\n#define BIT_FS_SPS_OCP_INT_8822C BIT(29)\n#define BIT_FS_PWMERR_INT_8822C BIT(28)\n#define BIT_FS_GPIOF_INT_8822C BIT(27)\n#define BIT_FS_GPIOE_INT_8822C BIT(26)\n#define BIT_FS_GPIOD_INT_8822C BIT(25)\n#define BIT_FS_GPIOC_INT_8822C BIT(24)\n#define BIT_FS_GPIOB_INT_8822C BIT(23)\n#define BIT_FS_GPIOA_INT_8822C BIT(22)\n#define BIT_FS_GPIO9_INT_8822C BIT(21)\n#define BIT_FS_GPIO8_INT_8822C BIT(20)\n#define BIT_FS_GPIO7_INT_8822C BIT(19)\n#define BIT_FS_GPIO6_INT_8822C BIT(18)\n#define BIT_FS_GPIO5_INT_8822C BIT(17)\n#define BIT_FS_GPIO4_INT_8822C BIT(16)\n#define BIT_FS_GPIO3_INT_8822C BIT(15)\n#define BIT_FS_GPIO2_INT_8822C BIT(14)\n#define BIT_FS_GPIO1_INT_8822C BIT(13)\n#define BIT_FS_GPIO0_INT_8822C BIT(12)\n#define BIT_FS_HCI_SUS_INT_8822C BIT(11)\n#define BIT_FS_HCI_RES_INT_8822C BIT(10)\n#define BIT_FS_HCI_RESET_INT_8822C BIT(9)\n#define BIT_USB_SCSI_CMD_INT_8822C BIT(8)\n#define BIT_ACT2RECOVERY_8822C BIT(6)\n#define BIT_GEN1GEN2_SWITCH_8822C BIT(5)\n#define BIT_HCI_TXDMA_REQ_HISR_8822C BIT(4)\n#define BIT_FS_32K_LEAVE_SETTING_INT_8822C BIT(3)\n#define BIT_FS_32K_ENTER_SETTING_INT_8822C BIT(2)\n#define BIT_FS_USB_LPMRSM_INT_8822C BIT(1)\n#define BIT_FS_USB_LPMINT_INT_8822C BIT(0)\n\n/* 2 REG_HSIMR_8822C */\n#define BIT_GPIOF_INT_EN_8822C BIT(31)\n#define BIT_GPIOE_INT_EN_8822C BIT(30)\n#define BIT_GPIOD_INT_EN_8822C BIT(29)\n#define BIT_GPIOC_INT_EN_8822C BIT(28)\n#define BIT_GPIOB_INT_EN_8822C BIT(27)\n#define BIT_GPIOA_INT_EN_8822C BIT(26)\n#define BIT_GPIO9_INT_EN_8822C BIT(25)\n#define BIT_GPIO8_INT_EN_8822C BIT(24)\n#define BIT_GPIO7_INT_EN_8822C BIT(23)\n#define BIT_GPIO6_INT_EN_8822C BIT(22)\n#define BIT_GPIO5_INT_EN_8822C BIT(21)\n#define BIT_GPIO4_INT_EN_8822C BIT(20)\n#define BIT_GPIO3_INT_EN_8822C BIT(19)\n#define BIT_GPIO2_INT_EN_V1_8822C BIT(18)\n#define BIT_GPIO1_INT_EN_8822C BIT(17)\n#define BIT_GPIO0_INT_EN_8822C BIT(16)\n#define BIT_PDNINT_EN_8822C BIT(7)\n#define BIT_RON_INT_EN_8822C BIT(6)\n#define BIT_SPS_OCP_INT_EN_8822C BIT(5)\n#define BIT_GPIO15_0_INT_EN_8822C BIT(0)\n\n/* 2 REG_HSISR_8822C */\n#define BIT_GPIOF_INT_8822C BIT(31)\n#define BIT_GPIOE_INT_8822C BIT(30)\n#define BIT_GPIOD_INT_8822C BIT(29)\n#define BIT_GPIOC_INT_8822C BIT(28)\n#define BIT_GPIOB_INT_8822C BIT(27)\n#define BIT_GPIOA_INT_8822C BIT(26)\n#define BIT_GPIO9_INT_8822C BIT(25)\n#define BIT_GPIO8_INT_8822C BIT(24)\n#define BIT_GPIO7_INT_8822C BIT(23)\n#define BIT_GPIO6_INT_8822C BIT(22)\n#define BIT_GPIO5_INT_8822C BIT(21)\n#define BIT_GPIO4_INT_8822C BIT(20)\n#define BIT_GPIO3_INT_8822C BIT(19)\n#define BIT_GPIO2_INT_V1_8822C BIT(18)\n#define BIT_GPIO1_INT_8822C BIT(17)\n#define BIT_GPIO0_INT_8822C BIT(16)\n#define BIT_PDNINT_8822C BIT(7)\n#define BIT_RON_INT_8822C BIT(6)\n#define BIT_SPS_OCP_INT_8822C BIT(5)\n#define BIT_GPIO15_0_INT_8822C BIT(0)\n\n/* 2 REG_GPIO_EXT_CTRL_8822C */\n\n#define BIT_SHIFT_GPIO_MOD_15_TO_8_8822C 24\n#define BIT_MASK_GPIO_MOD_15_TO_8_8822C 0xff\n#define BIT_GPIO_MOD_15_TO_8_8822C(x)                                          \\\n\t(((x) & BIT_MASK_GPIO_MOD_15_TO_8_8822C)                               \\\n\t << BIT_SHIFT_GPIO_MOD_15_TO_8_8822C)\n#define BITS_GPIO_MOD_15_TO_8_8822C                                            \\\n\t(BIT_MASK_GPIO_MOD_15_TO_8_8822C << BIT_SHIFT_GPIO_MOD_15_TO_8_8822C)\n#define BIT_CLEAR_GPIO_MOD_15_TO_8_8822C(x)                                    \\\n\t((x) & (~BITS_GPIO_MOD_15_TO_8_8822C))\n#define BIT_GET_GPIO_MOD_15_TO_8_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8822C) &                           \\\n\t BIT_MASK_GPIO_MOD_15_TO_8_8822C)\n#define BIT_SET_GPIO_MOD_15_TO_8_8822C(x, v)                                   \\\n\t(BIT_CLEAR_GPIO_MOD_15_TO_8_8822C(x) | BIT_GPIO_MOD_15_TO_8_8822C(v))\n\n#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C 16\n#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C 0xff\n#define BIT_GPIO_IO_SEL_15_TO_8_8822C(x)                                       \\\n\t(((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C)                            \\\n\t << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C)\n#define BITS_GPIO_IO_SEL_15_TO_8_8822C                                         \\\n\t(BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C                                    \\\n\t << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C)\n#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822C(x)                                 \\\n\t((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8822C))\n#define BIT_GET_GPIO_IO_SEL_15_TO_8_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C) &                        \\\n\t BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C)\n#define BIT_SET_GPIO_IO_SEL_15_TO_8_8822C(x, v)                                \\\n\t(BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822C(x) |                              \\\n\t BIT_GPIO_IO_SEL_15_TO_8_8822C(v))\n\n#define BIT_SHIFT_GPIO_OUT_15_TO_8_8822C 8\n#define BIT_MASK_GPIO_OUT_15_TO_8_8822C 0xff\n#define BIT_GPIO_OUT_15_TO_8_8822C(x)                                          \\\n\t(((x) & BIT_MASK_GPIO_OUT_15_TO_8_8822C)                               \\\n\t << BIT_SHIFT_GPIO_OUT_15_TO_8_8822C)\n#define BITS_GPIO_OUT_15_TO_8_8822C                                            \\\n\t(BIT_MASK_GPIO_OUT_15_TO_8_8822C << BIT_SHIFT_GPIO_OUT_15_TO_8_8822C)\n#define BIT_CLEAR_GPIO_OUT_15_TO_8_8822C(x)                                    \\\n\t((x) & (~BITS_GPIO_OUT_15_TO_8_8822C))\n#define BIT_GET_GPIO_OUT_15_TO_8_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8822C) &                           \\\n\t BIT_MASK_GPIO_OUT_15_TO_8_8822C)\n#define BIT_SET_GPIO_OUT_15_TO_8_8822C(x, v)                                   \\\n\t(BIT_CLEAR_GPIO_OUT_15_TO_8_8822C(x) | BIT_GPIO_OUT_15_TO_8_8822C(v))\n\n#define BIT_SHIFT_GPIO_IN_15_TO_8_8822C 0\n#define BIT_MASK_GPIO_IN_15_TO_8_8822C 0xff\n#define BIT_GPIO_IN_15_TO_8_8822C(x)                                           \\\n\t(((x) & BIT_MASK_GPIO_IN_15_TO_8_8822C)                                \\\n\t << BIT_SHIFT_GPIO_IN_15_TO_8_8822C)\n#define BITS_GPIO_IN_15_TO_8_8822C                                             \\\n\t(BIT_MASK_GPIO_IN_15_TO_8_8822C << BIT_SHIFT_GPIO_IN_15_TO_8_8822C)\n#define BIT_CLEAR_GPIO_IN_15_TO_8_8822C(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8822C))\n#define BIT_GET_GPIO_IN_15_TO_8_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8822C) &                            \\\n\t BIT_MASK_GPIO_IN_15_TO_8_8822C)\n#define BIT_SET_GPIO_IN_15_TO_8_8822C(x, v)                                    \\\n\t(BIT_CLEAR_GPIO_IN_15_TO_8_8822C(x) | BIT_GPIO_IN_15_TO_8_8822C(v))\n\n/* 2 REG_PAD_CTRL1_8822C */\n#define BIT_PAPE_WLBT_SEL_8822C BIT(29)\n#define BIT_LNAON_WLBT_SEL_8822C BIT(28)\n#define BIT_BT_BQB_GPIO_SEL_8822C BIT(27)\n#define BIT_BTGP_GPG3_FEN_8822C BIT(26)\n#define BIT_BTGP_GPG2_FEN_8822C BIT(25)\n#define BIT_BTGP_JTAG_EN_8822C BIT(24)\n#define BIT_XTAL_CLK_EXTARNAL_EN_8822C BIT(23)\n#define BIT_BTGP_UART0_EN_8822C BIT(22)\n#define BIT_BTGP_UART1_EN_8822C BIT(21)\n#define BIT_BTGP_SPI_EN_8822C BIT(20)\n#define BIT_BTGP_GPIO_E2_8822C BIT(19)\n#define BIT_BTGP_GPIO_EN_8822C BIT(18)\n\n#define BIT_SHIFT_BTGP_GPIO_SL_8822C 16\n#define BIT_MASK_BTGP_GPIO_SL_8822C 0x3\n#define BIT_BTGP_GPIO_SL_8822C(x)                                              \\\n\t(((x) & BIT_MASK_BTGP_GPIO_SL_8822C) << BIT_SHIFT_BTGP_GPIO_SL_8822C)\n#define BITS_BTGP_GPIO_SL_8822C                                                \\\n\t(BIT_MASK_BTGP_GPIO_SL_8822C << BIT_SHIFT_BTGP_GPIO_SL_8822C)\n#define BIT_CLEAR_BTGP_GPIO_SL_8822C(x) ((x) & (~BITS_BTGP_GPIO_SL_8822C))\n#define BIT_GET_BTGP_GPIO_SL_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BTGP_GPIO_SL_8822C) & BIT_MASK_BTGP_GPIO_SL_8822C)\n#define BIT_SET_BTGP_GPIO_SL_8822C(x, v)                                       \\\n\t(BIT_CLEAR_BTGP_GPIO_SL_8822C(x) | BIT_BTGP_GPIO_SL_8822C(v))\n\n#define BIT_PAD_SDIO_SR_8822C BIT(14)\n#define BIT_GPIO14_OUTPUT_PL_8822C BIT(13)\n#define BIT_HOST_WAKE_PAD_PULL_EN_8822C BIT(12)\n#define BIT_HOST_WAKE_PAD_SL_8822C BIT(11)\n#define BIT_PAD_LNAON_SR_8822C BIT(10)\n#define BIT_PAD_LNAON_E2_8822C BIT(9)\n#define BIT_SW_LNAON_G_SEL_DATA_8822C BIT(8)\n#define BIT_SW_LNAON_A_SEL_DATA_8822C BIT(7)\n#define BIT_PAD_PAPE_SR_8822C BIT(6)\n#define BIT_PAD_PAPE_E2_8822C BIT(5)\n#define BIT_SW_PAPE_G_SEL_DATA_8822C BIT(4)\n#define BIT_SW_PAPE_A_SEL_DATA_8822C BIT(3)\n#define BIT_PAD_DPDT_SR_8822C BIT(2)\n#define BIT_PAD_DPDT_PAD_E2_8822C BIT(1)\n#define BIT_SW_DPDT_SEL_DATA_8822C BIT(0)\n\n/* 2 REG_WL_BT_PWR_CTRL_8822C */\n#define BIT_ISO_BD2PP_8822C BIT(31)\n#define BIT_LDOV12B_EN_8822C BIT(30)\n#define BIT_CKEN_BTGPS_8822C BIT(29)\n#define BIT_FEN_BTGPS_8822C BIT(28)\n#define BIT_BTCPU_BOOTSEL_8822C BIT(27)\n#define BIT_SPI_SPEEDUP_8822C BIT(26)\n#define BIT_BT_LDO_MODE_8822C BIT(25)\n#define BIT_DEVWAKE_PAD_TYPE_SEL_8822C BIT(24)\n#define BIT_CLKREQ_PAD_TYPE_SEL_8822C BIT(23)\n#define BIT_ISO_BTPON2PP_8822C BIT(22)\n#define BIT_BT_HWROF_EN_8822C BIT(19)\n#define BIT_BT_FUNC_EN_8822C BIT(18)\n#define BIT_BT_HWPDN_SL_8822C BIT(17)\n#define BIT_BT_DISN_EN_8822C BIT(16)\n#define BIT_BT_PDN_PULL_EN_8822C BIT(15)\n#define BIT_WL_PDN_PULL_EN_8822C BIT(14)\n#define BIT_EXTERNAL_REQUEST_PL_8822C BIT(13)\n#define BIT_GPIO0_2_3_PULL_LOW_EN_8822C BIT(12)\n#define BIT_ISO_BA2PP_8822C BIT(11)\n#define BIT_BT_AFE_LDO_EN_8822C BIT(10)\n#define BIT_BT_AFE_PLL_EN_8822C BIT(9)\n#define BIT_BT_DIG_CLK_EN_8822C BIT(8)\n#define BIT_WLAN_32K_SEL_8822C BIT(6)\n#define BIT_WL_DRV_EXIST_IDX_8822C BIT(5)\n#define BIT_DOP_EHPAD_8822C BIT(4)\n#define BIT_WL_HWROF_EN_8822C BIT(3)\n#define BIT_WL_FUNC_EN_8822C BIT(2)\n#define BIT_WL_HWPDN_SL_8822C BIT(1)\n#define BIT_WL_HWPDN_EN_8822C BIT(0)\n\n/* 2 REG_SDM_DEBUG_8822C */\n#define BIT_GPIO_IE_V18_8822C BIT(10)\n#define BIT_PCIE_IE_V18_8822C BIT(9)\n#define BIT_UART_IE_V18_8822C BIT(8)\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_WLCLK_PHASE_8822C 0\n#define BIT_MASK_WLCLK_PHASE_8822C 0x1f\n#define BIT_WLCLK_PHASE_8822C(x)                                               \\\n\t(((x) & BIT_MASK_WLCLK_PHASE_8822C) << BIT_SHIFT_WLCLK_PHASE_8822C)\n#define BITS_WLCLK_PHASE_8822C                                                 \\\n\t(BIT_MASK_WLCLK_PHASE_8822C << BIT_SHIFT_WLCLK_PHASE_8822C)\n#define BIT_CLEAR_WLCLK_PHASE_8822C(x) ((x) & (~BITS_WLCLK_PHASE_8822C))\n#define BIT_GET_WLCLK_PHASE_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_WLCLK_PHASE_8822C) & BIT_MASK_WLCLK_PHASE_8822C)\n#define BIT_SET_WLCLK_PHASE_8822C(x, v)                                        \\\n\t(BIT_CLEAR_WLCLK_PHASE_8822C(x) | BIT_WLCLK_PHASE_8822C(v))\n\n/* 2 REG_SYS_SDIO_CTRL_8822C */\n#define BIT_DBG_GNT_WL_BT_8822C BIT(27)\n#define BIT_LTE_MUX_CTRL_PATH_8822C BIT(26)\n#define BIT_LTE_COEX_UART_8822C BIT(25)\n#define BIT_3W_LTE_WL_GPIO_8822C BIT(24)\n#define BIT_SDIO_INT_POLARITY_8822C BIT(19)\n#define BIT_SDIO_INT_8822C BIT(18)\n#define BIT_SDIO_OFF_EN_8822C BIT(17)\n#define BIT_SDIO_ON_EN_8822C BIT(16)\n#define BIT_PCIE_FORCE_PWR_NGAT_8822C BIT(13)\n#define BIT_PCIE_CALIB_EN_V1_8822C BIT(12)\n#define BIT_PAGE3_AUXCLK_GATE_8822C BIT(11)\n#define BIT_PCIE_WAIT_TIMEOUT_EVENT_8822C BIT(10)\n#define BIT_PCIE_WAIT_TIME_8822C BIT(9)\n#define BIT_MPCIE_REFCLK_XTAL_SEL_8822C BIT(8)\n#define BIT_BT_CTRL_USB_PWR_BACKDOOR_8822C BIT(5)\n#define BIT_USB_D_STATE_HOLD_8822C BIT(4)\n#define BIT_REG_FORCE_DP_8822C BIT(3)\n#define BIT_REG_DP_MODE_8822C BIT(2)\n#define BIT_RES_USB_MASS_STORAGE_DESC_8822C BIT(1)\n#define BIT_USB_WAIT_TIME_8822C BIT(0)\n\n/* 2 REG_HCI_OPT_CTRL_8822C */\n\n#define BIT_SHIFT_TSFT_SEL_8822C 29\n#define BIT_MASK_TSFT_SEL_8822C 0x7\n#define BIT_TSFT_SEL_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_TSFT_SEL_8822C) << BIT_SHIFT_TSFT_SEL_8822C)\n#define BITS_TSFT_SEL_8822C                                                    \\\n\t(BIT_MASK_TSFT_SEL_8822C << BIT_SHIFT_TSFT_SEL_8822C)\n#define BIT_CLEAR_TSFT_SEL_8822C(x) ((x) & (~BITS_TSFT_SEL_8822C))\n#define BIT_GET_TSFT_SEL_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TSFT_SEL_8822C) & BIT_MASK_TSFT_SEL_8822C)\n#define BIT_SET_TSFT_SEL_8822C(x, v)                                           \\\n\t(BIT_CLEAR_TSFT_SEL_8822C(x) | BIT_TSFT_SEL_8822C(v))\n\n#define BIT_SDIO_PAD_E5_8822C BIT(18)\n#define BIT_USB_HOST_PWR_OFF_EN_8822C BIT(12)\n#define BIT_SYM_LPS_BLOCK_EN_8822C BIT(11)\n#define BIT_USB_LPM_ACT_EN_8822C BIT(10)\n#define BIT_USB_LPM_NY_8822C BIT(9)\n#define BIT_USB_SUS_DIS_8822C BIT(8)\n\n#define BIT_SHIFT_SDIO_PAD_E_8822C 5\n#define BIT_MASK_SDIO_PAD_E_8822C 0x7\n#define BIT_SDIO_PAD_E_8822C(x)                                                \\\n\t(((x) & BIT_MASK_SDIO_PAD_E_8822C) << BIT_SHIFT_SDIO_PAD_E_8822C)\n#define BITS_SDIO_PAD_E_8822C                                                  \\\n\t(BIT_MASK_SDIO_PAD_E_8822C << BIT_SHIFT_SDIO_PAD_E_8822C)\n#define BIT_CLEAR_SDIO_PAD_E_8822C(x) ((x) & (~BITS_SDIO_PAD_E_8822C))\n#define BIT_GET_SDIO_PAD_E_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_SDIO_PAD_E_8822C) & BIT_MASK_SDIO_PAD_E_8822C)\n#define BIT_SET_SDIO_PAD_E_8822C(x, v)                                         \\\n\t(BIT_CLEAR_SDIO_PAD_E_8822C(x) | BIT_SDIO_PAD_E_8822C(v))\n\n#define BIT_USB_LPPLL_EN_8822C BIT(4)\n#define BIT_USB1_1_USB2_0_DECISION_8822C BIT(3)\n#define BIT_ROP_SW15_8822C BIT(2)\n#define BIT_PCI_CKRDY_OPT_8822C BIT(1)\n#define BIT_PCI_VAUX_EN_8822C BIT(0)\n\n/* 2 REG_HCI_BG_CTRL_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_IBX_EN_VALUE_8822C BIT(9)\n#define BIT_IB_EN_VALUE_8822C BIT(8)\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_FORCED_IB_EN_8822C BIT(4)\n#define BIT_EN_REGBG_8822C BIT(3)\n#define BIT_REG_BG_LPF_8822C BIT(2)\n\n#define BIT_SHIFT_REG_BG_8822C 0\n#define BIT_MASK_REG_BG_8822C 0x3\n#define BIT_REG_BG_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_REG_BG_8822C) << BIT_SHIFT_REG_BG_8822C)\n#define BITS_REG_BG_8822C (BIT_MASK_REG_BG_8822C << BIT_SHIFT_REG_BG_8822C)\n#define BIT_CLEAR_REG_BG_8822C(x) ((x) & (~BITS_REG_BG_8822C))\n#define BIT_GET_REG_BG_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_REG_BG_8822C) & BIT_MASK_REG_BG_8822C)\n#define BIT_SET_REG_BG_8822C(x, v)                                             \\\n\t(BIT_CLEAR_REG_BG_8822C(x) | BIT_REG_BG_8822C(v))\n\n/* 2 REG_HCI_LDO_CTRL_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_EN_LW_PWR_8822C BIT(6)\n#define BIT_EN_REGU_8822C BIT(5)\n#define BIT_EN_PC_8822C BIT(4)\n\n#define BIT_SHIFT_REG_VADJ_8822C 0\n#define BIT_MASK_REG_VADJ_8822C 0xf\n#define BIT_REG_VADJ_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_REG_VADJ_8822C) << BIT_SHIFT_REG_VADJ_8822C)\n#define BITS_REG_VADJ_8822C                                                    \\\n\t(BIT_MASK_REG_VADJ_8822C << BIT_SHIFT_REG_VADJ_8822C)\n#define BIT_CLEAR_REG_VADJ_8822C(x) ((x) & (~BITS_REG_VADJ_8822C))\n#define BIT_GET_REG_VADJ_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_REG_VADJ_8822C) & BIT_MASK_REG_VADJ_8822C)\n#define BIT_SET_REG_VADJ_8822C(x, v)                                           \\\n\t(BIT_CLEAR_REG_VADJ_8822C(x) | BIT_REG_VADJ_8822C(v))\n\n/* 2 REG_LDO_SWR_CTRL_8822C */\n#define BIT_EXT_SWR_CTRL_EN_8822C BIT(31)\n#define BIT_ZCD_HW_AUTO_EN_8822C BIT(27)\n#define BIT_ZCD_REGSEL_8822C BIT(26)\n\n#define BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C 21\n#define BIT_MASK_AUTO_ZCD_IN_CODE_8822C 0x1f\n#define BIT_AUTO_ZCD_IN_CODE_8822C(x)                                          \\\n\t(((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8822C)                               \\\n\t << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C)\n#define BITS_AUTO_ZCD_IN_CODE_8822C                                            \\\n\t(BIT_MASK_AUTO_ZCD_IN_CODE_8822C << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C)\n#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8822C(x)                                    \\\n\t((x) & (~BITS_AUTO_ZCD_IN_CODE_8822C))\n#define BIT_GET_AUTO_ZCD_IN_CODE_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C) &                           \\\n\t BIT_MASK_AUTO_ZCD_IN_CODE_8822C)\n#define BIT_SET_AUTO_ZCD_IN_CODE_8822C(x, v)                                   \\\n\t(BIT_CLEAR_AUTO_ZCD_IN_CODE_8822C(x) | BIT_AUTO_ZCD_IN_CODE_8822C(v))\n\n#define BIT_SHIFT_ZCD_CODE_IN_L_8822C 16\n#define BIT_MASK_ZCD_CODE_IN_L_8822C 0x1f\n#define BIT_ZCD_CODE_IN_L_8822C(x)                                             \\\n\t(((x) & BIT_MASK_ZCD_CODE_IN_L_8822C) << BIT_SHIFT_ZCD_CODE_IN_L_8822C)\n#define BITS_ZCD_CODE_IN_L_8822C                                               \\\n\t(BIT_MASK_ZCD_CODE_IN_L_8822C << BIT_SHIFT_ZCD_CODE_IN_L_8822C)\n#define BIT_CLEAR_ZCD_CODE_IN_L_8822C(x) ((x) & (~BITS_ZCD_CODE_IN_L_8822C))\n#define BIT_GET_ZCD_CODE_IN_L_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8822C) & BIT_MASK_ZCD_CODE_IN_L_8822C)\n#define BIT_SET_ZCD_CODE_IN_L_8822C(x, v)                                      \\\n\t(BIT_CLEAR_ZCD_CODE_IN_L_8822C(x) | BIT_ZCD_CODE_IN_L_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_MCUFW_CTRL_8822C */\n\n#define BIT_SHIFT_RPWM_8822C 24\n#define BIT_MASK_RPWM_8822C 0xff\n#define BIT_RPWM_8822C(x) (((x) & BIT_MASK_RPWM_8822C) << BIT_SHIFT_RPWM_8822C)\n#define BITS_RPWM_8822C (BIT_MASK_RPWM_8822C << BIT_SHIFT_RPWM_8822C)\n#define BIT_CLEAR_RPWM_8822C(x) ((x) & (~BITS_RPWM_8822C))\n#define BIT_GET_RPWM_8822C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_RPWM_8822C) & BIT_MASK_RPWM_8822C)\n#define BIT_SET_RPWM_8822C(x, v) (BIT_CLEAR_RPWM_8822C(x) | BIT_RPWM_8822C(v))\n\n#define BIT_ANA_PORT_EN_8822C BIT(22)\n#define BIT_MAC_PORT_EN_8822C BIT(21)\n#define BIT_BOOT_FSPI_EN_8822C BIT(20)\n#define BIT_ROM_DLEN_8822C BIT(19)\n\n#define BIT_SHIFT_ROM_PGE_8822C 16\n#define BIT_MASK_ROM_PGE_8822C 0x7\n#define BIT_ROM_PGE_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_ROM_PGE_8822C) << BIT_SHIFT_ROM_PGE_8822C)\n#define BITS_ROM_PGE_8822C (BIT_MASK_ROM_PGE_8822C << BIT_SHIFT_ROM_PGE_8822C)\n#define BIT_CLEAR_ROM_PGE_8822C(x) ((x) & (~BITS_ROM_PGE_8822C))\n#define BIT_GET_ROM_PGE_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_ROM_PGE_8822C) & BIT_MASK_ROM_PGE_8822C)\n#define BIT_SET_ROM_PGE_8822C(x, v)                                            \\\n\t(BIT_CLEAR_ROM_PGE_8822C(x) | BIT_ROM_PGE_8822C(v))\n\n#define BIT_FW_INIT_RDY_8822C BIT(15)\n#define BIT_FW_DW_RDY_8822C BIT(14)\n\n#define BIT_SHIFT_CPU_CLK_SEL_8822C 12\n#define BIT_MASK_CPU_CLK_SEL_8822C 0x3\n#define BIT_CPU_CLK_SEL_8822C(x)                                               \\\n\t(((x) & BIT_MASK_CPU_CLK_SEL_8822C) << BIT_SHIFT_CPU_CLK_SEL_8822C)\n#define BITS_CPU_CLK_SEL_8822C                                                 \\\n\t(BIT_MASK_CPU_CLK_SEL_8822C << BIT_SHIFT_CPU_CLK_SEL_8822C)\n#define BIT_CLEAR_CPU_CLK_SEL_8822C(x) ((x) & (~BITS_CPU_CLK_SEL_8822C))\n#define BIT_GET_CPU_CLK_SEL_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_CPU_CLK_SEL_8822C) & BIT_MASK_CPU_CLK_SEL_8822C)\n#define BIT_SET_CPU_CLK_SEL_8822C(x, v)                                        \\\n\t(BIT_CLEAR_CPU_CLK_SEL_8822C(x) | BIT_CPU_CLK_SEL_8822C(v))\n\n#define BIT_CCLK_CHG_MASK_8822C BIT(11)\n#define BIT_EMEM__TXBUF_CHKSUM_OK_8822C BIT(10)\n#define BIT_EMEM_TXBUF_DW_RDY_8822C BIT(9)\n#define BIT_EMEM_CHKSUM_OK_8822C BIT(8)\n#define BIT_EMEM_DW_OK_8822C BIT(7)\n#define BIT_DMEM_CHKSUM_OK_8822C BIT(6)\n#define BIT_DMEM_DW_OK_8822C BIT(5)\n#define BIT_IMEM_CHKSUM_OK_8822C BIT(4)\n#define BIT_IMEM_DW_OK_8822C BIT(3)\n#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK_8822C BIT(2)\n#define BIT_IMEM_BOOT_LOAD_DW_OK_8822C BIT(1)\n#define BIT_MCUFWDL_EN_8822C BIT(0)\n\n/* 2 REG_MCU_TST_CFG_8822C */\n\n#define BIT_SHIFT_LBKTST_8822C 0\n#define BIT_MASK_LBKTST_8822C 0xffff\n#define BIT_LBKTST_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_LBKTST_8822C) << BIT_SHIFT_LBKTST_8822C)\n#define BITS_LBKTST_8822C (BIT_MASK_LBKTST_8822C << BIT_SHIFT_LBKTST_8822C)\n#define BIT_CLEAR_LBKTST_8822C(x) ((x) & (~BITS_LBKTST_8822C))\n#define BIT_GET_LBKTST_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_LBKTST_8822C) & BIT_MASK_LBKTST_8822C)\n#define BIT_SET_LBKTST_8822C(x, v)                                             \\\n\t(BIT_CLEAR_LBKTST_8822C(x) | BIT_LBKTST_8822C(v))\n\n/* 2 REG_HMEBOX_E0_E1_8822C */\n\n#define BIT_SHIFT_HOST_MSG_E1_8822C 16\n#define BIT_MASK_HOST_MSG_E1_8822C 0xffff\n#define BIT_HOST_MSG_E1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E1_8822C) << BIT_SHIFT_HOST_MSG_E1_8822C)\n#define BITS_HOST_MSG_E1_8822C                                                 \\\n\t(BIT_MASK_HOST_MSG_E1_8822C << BIT_SHIFT_HOST_MSG_E1_8822C)\n#define BIT_CLEAR_HOST_MSG_E1_8822C(x) ((x) & (~BITS_HOST_MSG_E1_8822C))\n#define BIT_GET_HOST_MSG_E1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E1_8822C) & BIT_MASK_HOST_MSG_E1_8822C)\n#define BIT_SET_HOST_MSG_E1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E1_8822C(x) | BIT_HOST_MSG_E1_8822C(v))\n\n#define BIT_SHIFT_HOST_MSG_E0_8822C 0\n#define BIT_MASK_HOST_MSG_E0_8822C 0xffff\n#define BIT_HOST_MSG_E0_8822C(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E0_8822C) << BIT_SHIFT_HOST_MSG_E0_8822C)\n#define BITS_HOST_MSG_E0_8822C                                                 \\\n\t(BIT_MASK_HOST_MSG_E0_8822C << BIT_SHIFT_HOST_MSG_E0_8822C)\n#define BIT_CLEAR_HOST_MSG_E0_8822C(x) ((x) & (~BITS_HOST_MSG_E0_8822C))\n#define BIT_GET_HOST_MSG_E0_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E0_8822C) & BIT_MASK_HOST_MSG_E0_8822C)\n#define BIT_SET_HOST_MSG_E0_8822C(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E0_8822C(x) | BIT_HOST_MSG_E0_8822C(v))\n\n/* 2 REG_HMEBOX_E2_E3_8822C */\n\n#define BIT_SHIFT_HOST_MSG_E3_8822C 16\n#define BIT_MASK_HOST_MSG_E3_8822C 0xffff\n#define BIT_HOST_MSG_E3_8822C(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E3_8822C) << BIT_SHIFT_HOST_MSG_E3_8822C)\n#define BITS_HOST_MSG_E3_8822C                                                 \\\n\t(BIT_MASK_HOST_MSG_E3_8822C << BIT_SHIFT_HOST_MSG_E3_8822C)\n#define BIT_CLEAR_HOST_MSG_E3_8822C(x) ((x) & (~BITS_HOST_MSG_E3_8822C))\n#define BIT_GET_HOST_MSG_E3_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E3_8822C) & BIT_MASK_HOST_MSG_E3_8822C)\n#define BIT_SET_HOST_MSG_E3_8822C(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E3_8822C(x) | BIT_HOST_MSG_E3_8822C(v))\n\n#define BIT_SHIFT_HOST_MSG_E2_8822C 0\n#define BIT_MASK_HOST_MSG_E2_8822C 0xffff\n#define BIT_HOST_MSG_E2_8822C(x)                                               \\\n\t(((x) & BIT_MASK_HOST_MSG_E2_8822C) << BIT_SHIFT_HOST_MSG_E2_8822C)\n#define BITS_HOST_MSG_E2_8822C                                                 \\\n\t(BIT_MASK_HOST_MSG_E2_8822C << BIT_SHIFT_HOST_MSG_E2_8822C)\n#define BIT_CLEAR_HOST_MSG_E2_8822C(x) ((x) & (~BITS_HOST_MSG_E2_8822C))\n#define BIT_GET_HOST_MSG_E2_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_E2_8822C) & BIT_MASK_HOST_MSG_E2_8822C)\n#define BIT_SET_HOST_MSG_E2_8822C(x, v)                                        \\\n\t(BIT_CLEAR_HOST_MSG_E2_8822C(x) | BIT_HOST_MSG_E2_8822C(v))\n\n/* 2 REG_WLLPS_CTRL_8822C */\n#define BIT_WLLPSOP_EABM_8822C BIT(31)\n#define BIT_WLLPSOP_ACKF_8822C BIT(30)\n#define BIT_WLLPSOP_DLDM_8822C BIT(29)\n#define BIT_WLLPSOP_ESWR_8822C BIT(28)\n#define BIT_WLLPSOP_PWMM_8822C BIT(27)\n#define BIT_WLLPSOP_EECK_8822C BIT(26)\n#define BIT_WLLPSOP_WLMACOFF_8822C BIT(25)\n#define BIT_WLLPSOP_EXTAL_8822C BIT(24)\n#define BIT_WL_SYNPON_VOLTSPDN_8822C BIT(23)\n#define BIT_WLLPSOP_WLBBOFF_8822C BIT(22)\n#define BIT_WLLPSOP_WLMEM_DS_8822C BIT(21)\n#define BIT_WLLPSOP_LDO_WAIT_TIME_8822C BIT(20)\n#define BIT_WLLPSOP_ANA_CLK_DIVISION_2_8822C BIT(19)\n#define BIT_AFE_BCN_8822C BIT(18)\n\n#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C 12\n#define BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C 0xf\n#define BIT_LPLDH12_VADJ_STEP_DN_8822C(x)                                      \\\n\t(((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C)                           \\\n\t << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C)\n#define BITS_LPLDH12_VADJ_STEP_DN_8822C                                        \\\n\t(BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C                                   \\\n\t << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C)\n#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822C(x)                                \\\n\t((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8822C))\n#define BIT_GET_LPLDH12_VADJ_STEP_DN_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C) &                       \\\n\t BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C)\n#define BIT_SET_LPLDH12_VADJ_STEP_DN_8822C(x, v)                               \\\n\t(BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822C(x) |                             \\\n\t BIT_LPLDH12_VADJ_STEP_DN_8822C(v))\n\n#define BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C 8\n#define BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C 0xf\n#define BIT_V15ADJ_L1_STEP_DN_V1_8822C(x)                                      \\\n\t(((x) & BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C)                           \\\n\t << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C)\n#define BITS_V15ADJ_L1_STEP_DN_V1_8822C                                        \\\n\t(BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C                                   \\\n\t << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C)\n#define BIT_CLEAR_V15ADJ_L1_STEP_DN_V1_8822C(x)                                \\\n\t((x) & (~BITS_V15ADJ_L1_STEP_DN_V1_8822C))\n#define BIT_GET_V15ADJ_L1_STEP_DN_V1_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C) &                       \\\n\t BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C)\n#define BIT_SET_V15ADJ_L1_STEP_DN_V1_8822C(x, v)                               \\\n\t(BIT_CLEAR_V15ADJ_L1_STEP_DN_V1_8822C(x) |                             \\\n\t BIT_V15ADJ_L1_STEP_DN_V1_8822C(v))\n\n#define BIT_FORCE_LEAVE_LPS_8822C BIT(3)\n#define BIT_SW_AFE_MODE_8822C BIT(2)\n#define BIT_REGU_32K_CLK_EN_8822C BIT(1)\n#define BIT_WL_LPS_EN_8822C BIT(0)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_GPIO_DEBOUNCE_CTRL_8822C */\n#define BIT_WLGP_DBC1EN_8822C BIT(15)\n\n#define BIT_SHIFT_WLGP_DBC1_8822C 8\n#define BIT_MASK_WLGP_DBC1_8822C 0xf\n#define BIT_WLGP_DBC1_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_WLGP_DBC1_8822C) << BIT_SHIFT_WLGP_DBC1_8822C)\n#define BITS_WLGP_DBC1_8822C                                                   \\\n\t(BIT_MASK_WLGP_DBC1_8822C << BIT_SHIFT_WLGP_DBC1_8822C)\n#define BIT_CLEAR_WLGP_DBC1_8822C(x) ((x) & (~BITS_WLGP_DBC1_8822C))\n#define BIT_GET_WLGP_DBC1_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_WLGP_DBC1_8822C) & BIT_MASK_WLGP_DBC1_8822C)\n#define BIT_SET_WLGP_DBC1_8822C(x, v)                                          \\\n\t(BIT_CLEAR_WLGP_DBC1_8822C(x) | BIT_WLGP_DBC1_8822C(v))\n\n#define BIT_WLGP_DBC0EN_8822C BIT(7)\n\n#define BIT_SHIFT_WLGP_DBC0_8822C 0\n#define BIT_MASK_WLGP_DBC0_8822C 0xf\n#define BIT_WLGP_DBC0_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_WLGP_DBC0_8822C) << BIT_SHIFT_WLGP_DBC0_8822C)\n#define BITS_WLGP_DBC0_8822C                                                   \\\n\t(BIT_MASK_WLGP_DBC0_8822C << BIT_SHIFT_WLGP_DBC0_8822C)\n#define BIT_CLEAR_WLGP_DBC0_8822C(x) ((x) & (~BITS_WLGP_DBC0_8822C))\n#define BIT_GET_WLGP_DBC0_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_WLGP_DBC0_8822C) & BIT_MASK_WLGP_DBC0_8822C)\n#define BIT_SET_WLGP_DBC0_8822C(x, v)                                          \\\n\t(BIT_CLEAR_WLGP_DBC0_8822C(x) | BIT_WLGP_DBC0_8822C(v))\n\n/* 2 REG_RPWM2_8822C */\n\n#define BIT_SHIFT_RPWM2_8822C 16\n#define BIT_MASK_RPWM2_8822C 0xffff\n#define BIT_RPWM2_8822C(x)                                                     \\\n\t(((x) & BIT_MASK_RPWM2_8822C) << BIT_SHIFT_RPWM2_8822C)\n#define BITS_RPWM2_8822C (BIT_MASK_RPWM2_8822C << BIT_SHIFT_RPWM2_8822C)\n#define BIT_CLEAR_RPWM2_8822C(x) ((x) & (~BITS_RPWM2_8822C))\n#define BIT_GET_RPWM2_8822C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RPWM2_8822C) & BIT_MASK_RPWM2_8822C)\n#define BIT_SET_RPWM2_8822C(x, v)                                              \\\n\t(BIT_CLEAR_RPWM2_8822C(x) | BIT_RPWM2_8822C(v))\n\n/* 2 REG_SYSON_FSM_MON_8822C */\n\n#define BIT_SHIFT_FSM_MON_SEL_8822C 24\n#define BIT_MASK_FSM_MON_SEL_8822C 0x7\n#define BIT_FSM_MON_SEL_8822C(x)                                               \\\n\t(((x) & BIT_MASK_FSM_MON_SEL_8822C) << BIT_SHIFT_FSM_MON_SEL_8822C)\n#define BITS_FSM_MON_SEL_8822C                                                 \\\n\t(BIT_MASK_FSM_MON_SEL_8822C << BIT_SHIFT_FSM_MON_SEL_8822C)\n#define BIT_CLEAR_FSM_MON_SEL_8822C(x) ((x) & (~BITS_FSM_MON_SEL_8822C))\n#define BIT_GET_FSM_MON_SEL_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_FSM_MON_SEL_8822C) & BIT_MASK_FSM_MON_SEL_8822C)\n#define BIT_SET_FSM_MON_SEL_8822C(x, v)                                        \\\n\t(BIT_CLEAR_FSM_MON_SEL_8822C(x) | BIT_FSM_MON_SEL_8822C(v))\n\n#define BIT_DOP_ELDO_8822C BIT(23)\n#define BIT_FSM_MON_UPD_8822C BIT(15)\n\n#define BIT_SHIFT_FSM_PAR_8822C 0\n#define BIT_MASK_FSM_PAR_8822C 0x7fff\n#define BIT_FSM_PAR_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_FSM_PAR_8822C) << BIT_SHIFT_FSM_PAR_8822C)\n#define BITS_FSM_PAR_8822C (BIT_MASK_FSM_PAR_8822C << BIT_SHIFT_FSM_PAR_8822C)\n#define BIT_CLEAR_FSM_PAR_8822C(x) ((x) & (~BITS_FSM_PAR_8822C))\n#define BIT_GET_FSM_PAR_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_FSM_PAR_8822C) & BIT_MASK_FSM_PAR_8822C)\n#define BIT_SET_FSM_PAR_8822C(x, v)                                            \\\n\t(BIT_CLEAR_FSM_PAR_8822C(x) | BIT_FSM_PAR_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_PMC_DBG_CTRL1_8822C */\n#define BIT_BT_INT_EN_8822C BIT(31)\n\n#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C 16\n#define BIT_MASK_RD_WR_WIFI_BT_INFO_8822C 0x7fff\n#define BIT_RD_WR_WIFI_BT_INFO_8822C(x)                                        \\\n\t(((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822C)                             \\\n\t << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C)\n#define BITS_RD_WR_WIFI_BT_INFO_8822C                                          \\\n\t(BIT_MASK_RD_WR_WIFI_BT_INFO_8822C                                     \\\n\t << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C)\n#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822C(x)                                  \\\n\t((x) & (~BITS_RD_WR_WIFI_BT_INFO_8822C))\n#define BIT_GET_RD_WR_WIFI_BT_INFO_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C) &                         \\\n\t BIT_MASK_RD_WR_WIFI_BT_INFO_8822C)\n#define BIT_SET_RD_WR_WIFI_BT_INFO_8822C(x, v)                                 \\\n\t(BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822C(x) |                               \\\n\t BIT_RD_WR_WIFI_BT_INFO_8822C(v))\n\n#define BIT_PMC_WR_OVF_8822C BIT(8)\n\n#define BIT_SHIFT_WLPMC_ERRINT_8822C 0\n#define BIT_MASK_WLPMC_ERRINT_8822C 0xff\n#define BIT_WLPMC_ERRINT_8822C(x)                                              \\\n\t(((x) & BIT_MASK_WLPMC_ERRINT_8822C) << BIT_SHIFT_WLPMC_ERRINT_8822C)\n#define BITS_WLPMC_ERRINT_8822C                                                \\\n\t(BIT_MASK_WLPMC_ERRINT_8822C << BIT_SHIFT_WLPMC_ERRINT_8822C)\n#define BIT_CLEAR_WLPMC_ERRINT_8822C(x) ((x) & (~BITS_WLPMC_ERRINT_8822C))\n#define BIT_GET_WLPMC_ERRINT_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_WLPMC_ERRINT_8822C) & BIT_MASK_WLPMC_ERRINT_8822C)\n#define BIT_SET_WLPMC_ERRINT_8822C(x, v)                                       \\\n\t(BIT_CLEAR_WLPMC_ERRINT_8822C(x) | BIT_WLPMC_ERRINT_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_HIMR0_8822C */\n#define BIT_TIMEOUT_INTERRUPT2_MASK_8822C BIT(31)\n#define BIT_TIMEOUT_INTERRUTP1_MASK_8822C BIT(30)\n#define BIT_PSTIMEOUT_MSK_8822C BIT(29)\n#define BIT_GTINT4_MSK_8822C BIT(28)\n#define BIT_GTINT3_MSK_8822C BIT(27)\n#define BIT_TXBCN0ERR_MSK_8822C BIT(26)\n#define BIT_TXBCN0OK_MSK_8822C BIT(25)\n#define BIT_TSF_BIT32_TOGGLE_MSK_8822C BIT(24)\n#define BIT_BCNDMAINT0_MSK_8822C BIT(20)\n#define BIT_BCNDERR0_MSK_8822C BIT(16)\n#define BIT_HSISR_IND_ON_INT_MSK_8822C BIT(15)\n#define BIT_BCNDMAINT_E_MSK_8822C BIT(14)\n#define BIT_CTWEND_MSK_8822C BIT(12)\n#define BIT_HISR1_IND_MSK_8822C BIT(11)\n#define BIT_C2HCMD_MSK_8822C BIT(10)\n#define BIT_CPWM2_MSK_8822C BIT(9)\n#define BIT_CPWM_MSK_8822C BIT(8)\n#define BIT_HIGHDOK_MSK_8822C BIT(7)\n#define BIT_MGTDOK_MSK_8822C BIT(6)\n#define BIT_BKDOK_MSK_8822C BIT(5)\n#define BIT_BEDOK_MSK_8822C BIT(4)\n#define BIT_VIDOK_MSK_8822C BIT(3)\n#define BIT_VODOK_MSK_8822C BIT(2)\n#define BIT_RDU_MSK_8822C BIT(1)\n#define BIT_RXOK_MSK_8822C BIT(0)\n\n/* 2 REG_HISR0_8822C */\n#define BIT_PSTIMEOUT2_8822C BIT(31)\n#define BIT_PSTIMEOUT1_8822C BIT(30)\n#define BIT_PSTIMEOUT_8822C BIT(29)\n#define BIT_GTINT4_8822C BIT(28)\n#define BIT_GTINT3_8822C BIT(27)\n#define BIT_TXBCN0ERR_8822C BIT(26)\n#define BIT_TXBCN0OK_8822C BIT(25)\n#define BIT_TSF_BIT32_TOGGLE_8822C BIT(24)\n#define BIT_BCNDMAINT0_8822C BIT(20)\n#define BIT_BCNDERR0_8822C BIT(16)\n#define BIT_HSISR_IND_ON_INT_8822C BIT(15)\n#define BIT_BCNDMAINT_E_8822C BIT(14)\n#define BIT_CTWEND_8822C BIT(12)\n#define BIT_HISR1_IND_INT_8822C BIT(11)\n#define BIT_C2HCMD_8822C BIT(10)\n#define BIT_CPWM2_8822C BIT(9)\n#define BIT_CPWM_8822C BIT(8)\n#define BIT_HIGHDOK_8822C BIT(7)\n#define BIT_MGTDOK_8822C BIT(6)\n#define BIT_BKDOK_8822C BIT(5)\n#define BIT_BEDOK_8822C BIT(4)\n#define BIT_VIDOK_8822C BIT(3)\n#define BIT_VODOK_8822C BIT(2)\n#define BIT_RDU_8822C BIT(1)\n#define BIT_RXOK_8822C BIT(0)\n\n/* 2 REG_HIMR1_8822C */\n#define BIT_TXFIFO_TH_INT_8822C BIT(30)\n#define BIT_BTON_STS_UPDATE_MASK_8822C BIT(29)\n#define BIT_MCU_ERR_MASK_8822C BIT(28)\n#define BIT_BCNDMAINT7__MSK_8822C BIT(27)\n#define BIT_BCNDMAINT6__MSK_8822C BIT(26)\n#define BIT_BCNDMAINT5__MSK_8822C BIT(25)\n#define BIT_BCNDMAINT4__MSK_8822C BIT(24)\n#define BIT_BCNDMAINT3_MSK_8822C BIT(23)\n#define BIT_BCNDMAINT2_MSK_8822C BIT(22)\n#define BIT_BCNDMAINT1_MSK_8822C BIT(21)\n#define BIT_BCNDERR7_MSK_8822C BIT(20)\n#define BIT_BCNDERR6_MSK_8822C BIT(19)\n#define BIT_BCNDERR5_MSK_8822C BIT(18)\n#define BIT_BCNDERR4_MSK_8822C BIT(17)\n#define BIT_BCNDERR3_MSK_8822C BIT(16)\n#define BIT_BCNDERR2_MSK_8822C BIT(15)\n#define BIT_BCNDERR1_MSK_8822C BIT(14)\n#define BIT_ATIMEND_E_MSK_8822C BIT(13)\n#define BIT_ATIMEND__MSK_8822C BIT(12)\n#define BIT_TXERR_MSK_8822C BIT(11)\n#define BIT_RXERR_MSK_8822C BIT(10)\n#define BIT_TXFOVW_MSK_8822C BIT(9)\n#define BIT_FOVW_MSK_8822C BIT(8)\n#define BIT_CPU_MGQ_TXDONE_MSK_8822C BIT(5)\n#define BIT_PS_TIMER_C_MSK_8822C BIT(4)\n#define BIT_PS_TIMER_B_MSK_8822C BIT(3)\n#define BIT_PS_TIMER_A_MSK_8822C BIT(2)\n#define BIT_CPUMGQ_TX_TIMER_MSK_8822C BIT(1)\n\n/* 2 REG_HISR1_8822C */\n#define BIT_TXFIFO_TH_INT_8822C BIT(30)\n#define BIT_BTON_STS_UPDATE_INT_8822C BIT(29)\n#define BIT_MCU_ERR_8822C BIT(28)\n#define BIT_BCNDMAINT7_8822C BIT(27)\n#define BIT_BCNDMAINT6_8822C BIT(26)\n#define BIT_BCNDMAINT5_8822C BIT(25)\n#define BIT_BCNDMAINT4_8822C BIT(24)\n#define BIT_BCNDMAINT3_8822C BIT(23)\n#define BIT_BCNDMAINT2_8822C BIT(22)\n#define BIT_BCNDMAINT1_8822C BIT(21)\n#define BIT_BCNDERR7_8822C BIT(20)\n#define BIT_BCNDERR6_8822C BIT(19)\n#define BIT_BCNDERR5_8822C BIT(18)\n#define BIT_BCNDERR4_8822C BIT(17)\n#define BIT_BCNDERR3_8822C BIT(16)\n#define BIT_BCNDERR2_8822C BIT(15)\n#define BIT_BCNDERR1_8822C BIT(14)\n#define BIT_ATIMEND_E_8822C BIT(13)\n#define BIT_ATIMEND_8822C BIT(12)\n#define BIT_TXERR_INT_8822C BIT(11)\n#define BIT_RXERR_INT_8822C BIT(10)\n#define BIT_TXFOVW_8822C BIT(9)\n#define BIT_FOVW_8822C BIT(8)\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_CPU_MGQ_TXDONE_8822C BIT(5)\n#define BIT_PS_TIMER_C_8822C BIT(4)\n#define BIT_PS_TIMER_B_8822C BIT(3)\n#define BIT_PS_TIMER_A_8822C BIT(2)\n#define BIT_CPUMGQ_TX_TIMER_8822C BIT(1)\n\n/* 2 REG_DBG_PORT_SEL_8822C */\n\n#define BIT_SHIFT_DEBUG_ST_8822C 0\n#define BIT_MASK_DEBUG_ST_8822C 0xffffffffL\n#define BIT_DEBUG_ST_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_DEBUG_ST_8822C) << BIT_SHIFT_DEBUG_ST_8822C)\n#define BITS_DEBUG_ST_8822C                                                    \\\n\t(BIT_MASK_DEBUG_ST_8822C << BIT_SHIFT_DEBUG_ST_8822C)\n#define BIT_CLEAR_DEBUG_ST_8822C(x) ((x) & (~BITS_DEBUG_ST_8822C))\n#define BIT_GET_DEBUG_ST_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_DEBUG_ST_8822C) & BIT_MASK_DEBUG_ST_8822C)\n#define BIT_SET_DEBUG_ST_8822C(x, v)                                           \\\n\t(BIT_CLEAR_DEBUG_ST_8822C(x) | BIT_DEBUG_ST_8822C(v))\n\n/* 2 REG_PAD_CTRL2_8822C */\n#define BIT_USB3_USB2_TRANSITION_8822C BIT(20)\n\n#define BIT_SHIFT_USB23_SW_MODE_V1_8822C 18\n#define BIT_MASK_USB23_SW_MODE_V1_8822C 0x3\n#define BIT_USB23_SW_MODE_V1_8822C(x)                                          \\\n\t(((x) & BIT_MASK_USB23_SW_MODE_V1_8822C)                               \\\n\t << BIT_SHIFT_USB23_SW_MODE_V1_8822C)\n#define BITS_USB23_SW_MODE_V1_8822C                                            \\\n\t(BIT_MASK_USB23_SW_MODE_V1_8822C << BIT_SHIFT_USB23_SW_MODE_V1_8822C)\n#define BIT_CLEAR_USB23_SW_MODE_V1_8822C(x)                                    \\\n\t((x) & (~BITS_USB23_SW_MODE_V1_8822C))\n#define BIT_GET_USB23_SW_MODE_V1_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8822C) &                           \\\n\t BIT_MASK_USB23_SW_MODE_V1_8822C)\n#define BIT_SET_USB23_SW_MODE_V1_8822C(x, v)                                   \\\n\t(BIT_CLEAR_USB23_SW_MODE_V1_8822C(x) | BIT_USB23_SW_MODE_V1_8822C(v))\n\n#define BIT_NO_PDN_CHIPOFF_V1_8822C BIT(17)\n#define BIT_RSM_EN_V1_8822C BIT(16)\n\n#define BIT_SHIFT_MATCH_CNT_8822C 8\n#define BIT_MASK_MATCH_CNT_8822C 0xff\n#define BIT_MATCH_CNT_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_MATCH_CNT_8822C) << BIT_SHIFT_MATCH_CNT_8822C)\n#define BITS_MATCH_CNT_8822C                                                   \\\n\t(BIT_MASK_MATCH_CNT_8822C << BIT_SHIFT_MATCH_CNT_8822C)\n#define BIT_CLEAR_MATCH_CNT_8822C(x) ((x) & (~BITS_MATCH_CNT_8822C))\n#define BIT_GET_MATCH_CNT_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MATCH_CNT_8822C) & BIT_MASK_MATCH_CNT_8822C)\n#define BIT_SET_MATCH_CNT_8822C(x, v)                                          \\\n\t(BIT_CLEAR_MATCH_CNT_8822C(x) | BIT_MATCH_CNT_8822C(v))\n\n#define BIT_LD_B12V_EN_8822C BIT(7)\n#define BIT_EECS_IOSEL_V1_8822C BIT(6)\n#define BIT_EECS_DATA_O_V1_8822C BIT(5)\n#define BIT_EECS_DATA_I_V1_8822C BIT(4)\n#define BIT_EESK_IOSEL_V1_8822C BIT(2)\n#define BIT_EESK_DATA_O_V1_8822C BIT(1)\n#define BIT_EESK_DATA_I_V1_8822C BIT(0)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_PMC_DBG_CTRL2_8822C */\n\n#define BIT_SHIFT_EFUSE_BURN_GNT_8822C 24\n#define BIT_MASK_EFUSE_BURN_GNT_8822C 0xff\n#define BIT_EFUSE_BURN_GNT_8822C(x)                                            \\\n\t(((x) & BIT_MASK_EFUSE_BURN_GNT_8822C)                                 \\\n\t << BIT_SHIFT_EFUSE_BURN_GNT_8822C)\n#define BITS_EFUSE_BURN_GNT_8822C                                              \\\n\t(BIT_MASK_EFUSE_BURN_GNT_8822C << BIT_SHIFT_EFUSE_BURN_GNT_8822C)\n#define BIT_CLEAR_EFUSE_BURN_GNT_8822C(x) ((x) & (~BITS_EFUSE_BURN_GNT_8822C))\n#define BIT_GET_EFUSE_BURN_GNT_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8822C) &                             \\\n\t BIT_MASK_EFUSE_BURN_GNT_8822C)\n#define BIT_SET_EFUSE_BURN_GNT_8822C(x, v)                                     \\\n\t(BIT_CLEAR_EFUSE_BURN_GNT_8822C(x) | BIT_EFUSE_BURN_GNT_8822C(v))\n\n#define BIT_STOP_WL_PMC_8822C BIT(9)\n#define BIT_STOP_SYM_PMC_8822C BIT(8)\n#define BIT_BT_ACCESS_WL_PAGE0_8822C BIT(6)\n#define BIT_REG_RST_WLPMC_8822C BIT(5)\n#define BIT_REG_RST_PD12N_8822C BIT(4)\n#define BIT_SYSON_DIS_WLREG_WRMSK_8822C BIT(3)\n#define BIT_SYSON_DIS_PMCREG_WRMSK_8822C BIT(2)\n\n#define BIT_SHIFT_SYSON_REG_ARB_8822C 0\n#define BIT_MASK_SYSON_REG_ARB_8822C 0x3\n#define BIT_SYSON_REG_ARB_8822C(x)                                             \\\n\t(((x) & BIT_MASK_SYSON_REG_ARB_8822C) << BIT_SHIFT_SYSON_REG_ARB_8822C)\n#define BITS_SYSON_REG_ARB_8822C                                               \\\n\t(BIT_MASK_SYSON_REG_ARB_8822C << BIT_SHIFT_SYSON_REG_ARB_8822C)\n#define BIT_CLEAR_SYSON_REG_ARB_8822C(x) ((x) & (~BITS_SYSON_REG_ARB_8822C))\n#define BIT_GET_SYSON_REG_ARB_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SYSON_REG_ARB_8822C) & BIT_MASK_SYSON_REG_ARB_8822C)\n#define BIT_SET_SYSON_REG_ARB_8822C(x, v)                                      \\\n\t(BIT_CLEAR_SYSON_REG_ARB_8822C(x) | BIT_SYSON_REG_ARB_8822C(v))\n\n/* 2 REG_BIST_CTRL_8822C */\n#define BIT_BIST_USB_DIS_8822C BIT(27)\n#define BIT_BIST_PCI_DIS_8822C BIT(26)\n#define BIT_BIST_BT_DIS_8822C BIT(25)\n#define BIT_BIST_WL_DIS_8822C BIT(24)\n\n#define BIT_SHIFT_BIST_RPT_SEL_8822C 16\n#define BIT_MASK_BIST_RPT_SEL_8822C 0xf\n#define BIT_BIST_RPT_SEL_8822C(x)                                              \\\n\t(((x) & BIT_MASK_BIST_RPT_SEL_8822C) << BIT_SHIFT_BIST_RPT_SEL_8822C)\n#define BITS_BIST_RPT_SEL_8822C                                                \\\n\t(BIT_MASK_BIST_RPT_SEL_8822C << BIT_SHIFT_BIST_RPT_SEL_8822C)\n#define BIT_CLEAR_BIST_RPT_SEL_8822C(x) ((x) & (~BITS_BIST_RPT_SEL_8822C))\n#define BIT_GET_BIST_RPT_SEL_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BIST_RPT_SEL_8822C) & BIT_MASK_BIST_RPT_SEL_8822C)\n#define BIT_SET_BIST_RPT_SEL_8822C(x, v)                                       \\\n\t(BIT_CLEAR_BIST_RPT_SEL_8822C(x) | BIT_BIST_RPT_SEL_8822C(v))\n\n#define BIT_BIST_RESUME_PS_8822C BIT(4)\n#define BIT_BIST_RESUME_8822C BIT(3)\n#define BIT_BIST_NORMAL_8822C BIT(2)\n#define BIT_BIST_RSTN_8822C BIT(1)\n#define BIT_BIST_CLK_EN_8822C BIT(0)\n\n/* 2 REG_BIST_RPT_8822C */\n\n#define BIT_SHIFT_MBIST_REPORT_8822C 0\n#define BIT_MASK_MBIST_REPORT_8822C 0xffffffffL\n#define BIT_MBIST_REPORT_8822C(x)                                              \\\n\t(((x) & BIT_MASK_MBIST_REPORT_8822C) << BIT_SHIFT_MBIST_REPORT_8822C)\n#define BITS_MBIST_REPORT_8822C                                                \\\n\t(BIT_MASK_MBIST_REPORT_8822C << BIT_SHIFT_MBIST_REPORT_8822C)\n#define BIT_CLEAR_MBIST_REPORT_8822C(x) ((x) & (~BITS_MBIST_REPORT_8822C))\n#define BIT_GET_MBIST_REPORT_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_MBIST_REPORT_8822C) & BIT_MASK_MBIST_REPORT_8822C)\n#define BIT_SET_MBIST_REPORT_8822C(x, v)                                       \\\n\t(BIT_CLEAR_MBIST_REPORT_8822C(x) | BIT_MBIST_REPORT_8822C(v))\n\n/* 2 REG_MEM_CTRL_8822C */\n#define BIT_UMEM_RME_8822C BIT(31)\n\n#define BIT_SHIFT_BT_SPRAM_8822C 28\n#define BIT_MASK_BT_SPRAM_8822C 0x3\n#define BIT_BT_SPRAM_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_BT_SPRAM_8822C) << BIT_SHIFT_BT_SPRAM_8822C)\n#define BITS_BT_SPRAM_8822C                                                    \\\n\t(BIT_MASK_BT_SPRAM_8822C << BIT_SHIFT_BT_SPRAM_8822C)\n#define BIT_CLEAR_BT_SPRAM_8822C(x) ((x) & (~BITS_BT_SPRAM_8822C))\n#define BIT_GET_BT_SPRAM_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_BT_SPRAM_8822C) & BIT_MASK_BT_SPRAM_8822C)\n#define BIT_SET_BT_SPRAM_8822C(x, v)                                           \\\n\t(BIT_CLEAR_BT_SPRAM_8822C(x) | BIT_BT_SPRAM_8822C(v))\n\n#define BIT_SHIFT_BT_ROM_8822C 24\n#define BIT_MASK_BT_ROM_8822C 0xf\n#define BIT_BT_ROM_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_BT_ROM_8822C) << BIT_SHIFT_BT_ROM_8822C)\n#define BITS_BT_ROM_8822C (BIT_MASK_BT_ROM_8822C << BIT_SHIFT_BT_ROM_8822C)\n#define BIT_CLEAR_BT_ROM_8822C(x) ((x) & (~BITS_BT_ROM_8822C))\n#define BIT_GET_BT_ROM_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_BT_ROM_8822C) & BIT_MASK_BT_ROM_8822C)\n#define BIT_SET_BT_ROM_8822C(x, v)                                             \\\n\t(BIT_CLEAR_BT_ROM_8822C(x) | BIT_BT_ROM_8822C(v))\n\n#define BIT_SHIFT_PCI_DPRAM_8822C 10\n#define BIT_MASK_PCI_DPRAM_8822C 0x3\n#define BIT_PCI_DPRAM_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_PCI_DPRAM_8822C) << BIT_SHIFT_PCI_DPRAM_8822C)\n#define BITS_PCI_DPRAM_8822C                                                   \\\n\t(BIT_MASK_PCI_DPRAM_8822C << BIT_SHIFT_PCI_DPRAM_8822C)\n#define BIT_CLEAR_PCI_DPRAM_8822C(x) ((x) & (~BITS_PCI_DPRAM_8822C))\n#define BIT_GET_PCI_DPRAM_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_PCI_DPRAM_8822C) & BIT_MASK_PCI_DPRAM_8822C)\n#define BIT_SET_PCI_DPRAM_8822C(x, v)                                          \\\n\t(BIT_CLEAR_PCI_DPRAM_8822C(x) | BIT_PCI_DPRAM_8822C(v))\n\n#define BIT_SHIFT_PCI_SPRAM_8822C 8\n#define BIT_MASK_PCI_SPRAM_8822C 0x3\n#define BIT_PCI_SPRAM_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_PCI_SPRAM_8822C) << BIT_SHIFT_PCI_SPRAM_8822C)\n#define BITS_PCI_SPRAM_8822C                                                   \\\n\t(BIT_MASK_PCI_SPRAM_8822C << BIT_SHIFT_PCI_SPRAM_8822C)\n#define BIT_CLEAR_PCI_SPRAM_8822C(x) ((x) & (~BITS_PCI_SPRAM_8822C))\n#define BIT_GET_PCI_SPRAM_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_PCI_SPRAM_8822C) & BIT_MASK_PCI_SPRAM_8822C)\n#define BIT_SET_PCI_SPRAM_8822C(x, v)                                          \\\n\t(BIT_CLEAR_PCI_SPRAM_8822C(x) | BIT_PCI_SPRAM_8822C(v))\n\n#define BIT_SHIFT_USB_SPRAM_8822C 6\n#define BIT_MASK_USB_SPRAM_8822C 0x3\n#define BIT_USB_SPRAM_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_USB_SPRAM_8822C) << BIT_SHIFT_USB_SPRAM_8822C)\n#define BITS_USB_SPRAM_8822C                                                   \\\n\t(BIT_MASK_USB_SPRAM_8822C << BIT_SHIFT_USB_SPRAM_8822C)\n#define BIT_CLEAR_USB_SPRAM_8822C(x) ((x) & (~BITS_USB_SPRAM_8822C))\n#define BIT_GET_USB_SPRAM_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_USB_SPRAM_8822C) & BIT_MASK_USB_SPRAM_8822C)\n#define BIT_SET_USB_SPRAM_8822C(x, v)                                          \\\n\t(BIT_CLEAR_USB_SPRAM_8822C(x) | BIT_USB_SPRAM_8822C(v))\n\n#define BIT_SHIFT_USB_SPRF_8822C 4\n#define BIT_MASK_USB_SPRF_8822C 0x3\n#define BIT_USB_SPRF_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_USB_SPRF_8822C) << BIT_SHIFT_USB_SPRF_8822C)\n#define BITS_USB_SPRF_8822C                                                    \\\n\t(BIT_MASK_USB_SPRF_8822C << BIT_SHIFT_USB_SPRF_8822C)\n#define BIT_CLEAR_USB_SPRF_8822C(x) ((x) & (~BITS_USB_SPRF_8822C))\n#define BIT_GET_USB_SPRF_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_USB_SPRF_8822C) & BIT_MASK_USB_SPRF_8822C)\n#define BIT_SET_USB_SPRF_8822C(x, v)                                           \\\n\t(BIT_CLEAR_USB_SPRF_8822C(x) | BIT_USB_SPRF_8822C(v))\n\n#define BIT_SHIFT_MCU_ROM_8822C 0\n#define BIT_MASK_MCU_ROM_8822C 0xf\n#define BIT_MCU_ROM_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_MCU_ROM_8822C) << BIT_SHIFT_MCU_ROM_8822C)\n#define BITS_MCU_ROM_8822C (BIT_MASK_MCU_ROM_8822C << BIT_SHIFT_MCU_ROM_8822C)\n#define BIT_CLEAR_MCU_ROM_8822C(x) ((x) & (~BITS_MCU_ROM_8822C))\n#define BIT_GET_MCU_ROM_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_MCU_ROM_8822C) & BIT_MASK_MCU_ROM_8822C)\n#define BIT_SET_MCU_ROM_8822C(x, v)                                            \\\n\t(BIT_CLEAR_MCU_ROM_8822C(x) | BIT_MCU_ROM_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_USB_SIE_INTF_8822C */\n#define BIT_RD_SEL_8822C BIT(31)\n#define BIT_USB_SIE_INTF_WE_V1_8822C BIT(30)\n#define BIT_USB_SIE_INTF_BYIOREG_V1_8822C BIT(29)\n#define BIT_USB_SIE_SELECT_8822C BIT(28)\n\n#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C 16\n#define BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C 0x1ff\n#define BIT_USB_SIE_INTF_ADDR_V1_8822C(x)                                      \\\n\t(((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C)                           \\\n\t << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C)\n#define BITS_USB_SIE_INTF_ADDR_V1_8822C                                        \\\n\t(BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C                                   \\\n\t << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C)\n#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822C(x)                                \\\n\t((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8822C))\n#define BIT_GET_USB_SIE_INTF_ADDR_V1_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C) &                       \\\n\t BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C)\n#define BIT_SET_USB_SIE_INTF_ADDR_V1_8822C(x, v)                               \\\n\t(BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822C(x) |                             \\\n\t BIT_USB_SIE_INTF_ADDR_V1_8822C(v))\n\n#define BIT_SHIFT_USB_SIE_INTF_RD_8822C 8\n#define BIT_MASK_USB_SIE_INTF_RD_8822C 0xff\n#define BIT_USB_SIE_INTF_RD_8822C(x)                                           \\\n\t(((x) & BIT_MASK_USB_SIE_INTF_RD_8822C)                                \\\n\t << BIT_SHIFT_USB_SIE_INTF_RD_8822C)\n#define BITS_USB_SIE_INTF_RD_8822C                                             \\\n\t(BIT_MASK_USB_SIE_INTF_RD_8822C << BIT_SHIFT_USB_SIE_INTF_RD_8822C)\n#define BIT_CLEAR_USB_SIE_INTF_RD_8822C(x) ((x) & (~BITS_USB_SIE_INTF_RD_8822C))\n#define BIT_GET_USB_SIE_INTF_RD_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8822C) &                            \\\n\t BIT_MASK_USB_SIE_INTF_RD_8822C)\n#define BIT_SET_USB_SIE_INTF_RD_8822C(x, v)                                    \\\n\t(BIT_CLEAR_USB_SIE_INTF_RD_8822C(x) | BIT_USB_SIE_INTF_RD_8822C(v))\n\n#define BIT_SHIFT_USB_SIE_INTF_WD_8822C 0\n#define BIT_MASK_USB_SIE_INTF_WD_8822C 0xff\n#define BIT_USB_SIE_INTF_WD_8822C(x)                                           \\\n\t(((x) & BIT_MASK_USB_SIE_INTF_WD_8822C)                                \\\n\t << BIT_SHIFT_USB_SIE_INTF_WD_8822C)\n#define BITS_USB_SIE_INTF_WD_8822C                                             \\\n\t(BIT_MASK_USB_SIE_INTF_WD_8822C << BIT_SHIFT_USB_SIE_INTF_WD_8822C)\n#define BIT_CLEAR_USB_SIE_INTF_WD_8822C(x) ((x) & (~BITS_USB_SIE_INTF_WD_8822C))\n#define BIT_GET_USB_SIE_INTF_WD_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8822C) &                            \\\n\t BIT_MASK_USB_SIE_INTF_WD_8822C)\n#define BIT_SET_USB_SIE_INTF_WD_8822C(x, v)                                    \\\n\t(BIT_CLEAR_USB_SIE_INTF_WD_8822C(x) | BIT_USB_SIE_INTF_WD_8822C(v))\n\n/* 2 REG_PCIE_MIO_INTF_8822C */\n\n#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C 16\n#define BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C 0x3\n#define BIT_PCIE_MIO_ADDR_PAGE_8822C(x)                                        \\\n\t(((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C)                             \\\n\t << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C)\n#define BITS_PCIE_MIO_ADDR_PAGE_8822C                                          \\\n\t(BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C                                     \\\n\t << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C)\n#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8822C(x)                                  \\\n\t((x) & (~BITS_PCIE_MIO_ADDR_PAGE_8822C))\n#define BIT_GET_PCIE_MIO_ADDR_PAGE_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C) &                         \\\n\t BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C)\n#define BIT_SET_PCIE_MIO_ADDR_PAGE_8822C(x, v)                                 \\\n\t(BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8822C(x) |                               \\\n\t BIT_PCIE_MIO_ADDR_PAGE_8822C(v))\n\n#define BIT_PCIE_MIO_BYIOREG_8822C BIT(13)\n#define BIT_PCIE_MIO_RE_8822C BIT(12)\n\n#define BIT_SHIFT_PCIE_MIO_WE_8822C 8\n#define BIT_MASK_PCIE_MIO_WE_8822C 0xf\n#define BIT_PCIE_MIO_WE_8822C(x)                                               \\\n\t(((x) & BIT_MASK_PCIE_MIO_WE_8822C) << BIT_SHIFT_PCIE_MIO_WE_8822C)\n#define BITS_PCIE_MIO_WE_8822C                                                 \\\n\t(BIT_MASK_PCIE_MIO_WE_8822C << BIT_SHIFT_PCIE_MIO_WE_8822C)\n#define BIT_CLEAR_PCIE_MIO_WE_8822C(x) ((x) & (~BITS_PCIE_MIO_WE_8822C))\n#define BIT_GET_PCIE_MIO_WE_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_WE_8822C) & BIT_MASK_PCIE_MIO_WE_8822C)\n#define BIT_SET_PCIE_MIO_WE_8822C(x, v)                                        \\\n\t(BIT_CLEAR_PCIE_MIO_WE_8822C(x) | BIT_PCIE_MIO_WE_8822C(v))\n\n#define BIT_SHIFT_PCIE_MIO_ADDR_8822C 0\n#define BIT_MASK_PCIE_MIO_ADDR_8822C 0xff\n#define BIT_PCIE_MIO_ADDR_8822C(x)                                             \\\n\t(((x) & BIT_MASK_PCIE_MIO_ADDR_8822C) << BIT_SHIFT_PCIE_MIO_ADDR_8822C)\n#define BITS_PCIE_MIO_ADDR_8822C                                               \\\n\t(BIT_MASK_PCIE_MIO_ADDR_8822C << BIT_SHIFT_PCIE_MIO_ADDR_8822C)\n#define BIT_CLEAR_PCIE_MIO_ADDR_8822C(x) ((x) & (~BITS_PCIE_MIO_ADDR_8822C))\n#define BIT_GET_PCIE_MIO_ADDR_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8822C) & BIT_MASK_PCIE_MIO_ADDR_8822C)\n#define BIT_SET_PCIE_MIO_ADDR_8822C(x, v)                                      \\\n\t(BIT_CLEAR_PCIE_MIO_ADDR_8822C(x) | BIT_PCIE_MIO_ADDR_8822C(v))\n\n/* 2 REG_PCIE_MIO_INTD_8822C */\n\n#define BIT_SHIFT_PCIE_MIO_DATA_8822C 0\n#define BIT_MASK_PCIE_MIO_DATA_8822C 0xffffffffL\n#define BIT_PCIE_MIO_DATA_8822C(x)                                             \\\n\t(((x) & BIT_MASK_PCIE_MIO_DATA_8822C) << BIT_SHIFT_PCIE_MIO_DATA_8822C)\n#define BITS_PCIE_MIO_DATA_8822C                                               \\\n\t(BIT_MASK_PCIE_MIO_DATA_8822C << BIT_SHIFT_PCIE_MIO_DATA_8822C)\n#define BIT_CLEAR_PCIE_MIO_DATA_8822C(x) ((x) & (~BITS_PCIE_MIO_DATA_8822C))\n#define BIT_GET_PCIE_MIO_DATA_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PCIE_MIO_DATA_8822C) & BIT_MASK_PCIE_MIO_DATA_8822C)\n#define BIT_SET_PCIE_MIO_DATA_8822C(x, v)                                      \\\n\t(BIT_CLEAR_PCIE_MIO_DATA_8822C(x) | BIT_PCIE_MIO_DATA_8822C(v))\n\n/* 2 REG_WLRF1_8822C */\n\n#define BIT_SHIFT_WLRF1_CTRL_8822C 24\n#define BIT_MASK_WLRF1_CTRL_8822C 0xff\n#define BIT_WLRF1_CTRL_8822C(x)                                                \\\n\t(((x) & BIT_MASK_WLRF1_CTRL_8822C) << BIT_SHIFT_WLRF1_CTRL_8822C)\n#define BITS_WLRF1_CTRL_8822C                                                  \\\n\t(BIT_MASK_WLRF1_CTRL_8822C << BIT_SHIFT_WLRF1_CTRL_8822C)\n#define BIT_CLEAR_WLRF1_CTRL_8822C(x) ((x) & (~BITS_WLRF1_CTRL_8822C))\n#define BIT_GET_WLRF1_CTRL_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_WLRF1_CTRL_8822C) & BIT_MASK_WLRF1_CTRL_8822C)\n#define BIT_SET_WLRF1_CTRL_8822C(x, v)                                         \\\n\t(BIT_CLEAR_WLRF1_CTRL_8822C(x) | BIT_WLRF1_CTRL_8822C(v))\n\n/* 2 REG_SYS_CFG1_8822C */\n\n#define BIT_SHIFT_TRP_ICFG_8822C 28\n#define BIT_MASK_TRP_ICFG_8822C 0xf\n#define BIT_TRP_ICFG_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_TRP_ICFG_8822C) << BIT_SHIFT_TRP_ICFG_8822C)\n#define BITS_TRP_ICFG_8822C                                                    \\\n\t(BIT_MASK_TRP_ICFG_8822C << BIT_SHIFT_TRP_ICFG_8822C)\n#define BIT_CLEAR_TRP_ICFG_8822C(x) ((x) & (~BITS_TRP_ICFG_8822C))\n#define BIT_GET_TRP_ICFG_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TRP_ICFG_8822C) & BIT_MASK_TRP_ICFG_8822C)\n#define BIT_SET_TRP_ICFG_8822C(x, v)                                           \\\n\t(BIT_CLEAR_TRP_ICFG_8822C(x) | BIT_TRP_ICFG_8822C(v))\n\n#define BIT_RF_TYPE_ID_8822C BIT(27)\n#define BIT_BD_HCI_SEL_8822C BIT(26)\n#define BIT_BD_PKG_SEL_8822C BIT(25)\n#define BIT_INTERNAL_EXTERNAL_SWR_8822C BIT(24)\n#define BIT_RTL_ID_8822C BIT(23)\n#define BIT_PAD_HWPD_IDN_8822C BIT(22)\n#define BIT_TESTMODE_8822C BIT(20)\n\n#define BIT_SHIFT_VENDOR_ID_8822C 16\n#define BIT_MASK_VENDOR_ID_8822C 0xf\n#define BIT_VENDOR_ID_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_VENDOR_ID_8822C) << BIT_SHIFT_VENDOR_ID_8822C)\n#define BITS_VENDOR_ID_8822C                                                   \\\n\t(BIT_MASK_VENDOR_ID_8822C << BIT_SHIFT_VENDOR_ID_8822C)\n#define BIT_CLEAR_VENDOR_ID_8822C(x) ((x) & (~BITS_VENDOR_ID_8822C))\n#define BIT_GET_VENDOR_ID_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_VENDOR_ID_8822C) & BIT_MASK_VENDOR_ID_8822C)\n#define BIT_SET_VENDOR_ID_8822C(x, v)                                          \\\n\t(BIT_CLEAR_VENDOR_ID_8822C(x) | BIT_VENDOR_ID_8822C(v))\n\n#define BIT_SHIFT_CHIP_VER_8822C 12\n#define BIT_MASK_CHIP_VER_8822C 0xf\n#define BIT_CHIP_VER_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_CHIP_VER_8822C) << BIT_SHIFT_CHIP_VER_8822C)\n#define BITS_CHIP_VER_8822C                                                    \\\n\t(BIT_MASK_CHIP_VER_8822C << BIT_SHIFT_CHIP_VER_8822C)\n#define BIT_CLEAR_CHIP_VER_8822C(x) ((x) & (~BITS_CHIP_VER_8822C))\n#define BIT_GET_CHIP_VER_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_CHIP_VER_8822C) & BIT_MASK_CHIP_VER_8822C)\n#define BIT_SET_CHIP_VER_8822C(x, v)                                           \\\n\t(BIT_CLEAR_CHIP_VER_8822C(x) | BIT_CHIP_VER_8822C(v))\n\n#define BIT_BD_MAC3_8822C BIT(11)\n#define BIT_BD_MAC1_8822C BIT(10)\n#define BIT_BD_MAC2_8822C BIT(9)\n#define BIT_SIC_IDLE_8822C BIT(8)\n#define BIT_SW_OFFLOAD_EN_8822C BIT(7)\n#define BIT_OCP_SHUTDN_8822C BIT(6)\n#define BIT_V15_VLD_8822C BIT(5)\n#define BIT_PCIRSTB_8822C BIT(4)\n#define BIT_PCLK_VLD_8822C BIT(3)\n#define BIT_UCLK_VLD_8822C BIT(2)\n#define BIT_ACLK_VLD_8822C BIT(1)\n#define BIT_XCLK_VLD_8822C BIT(0)\n\n/* 2 REG_SYS_STATUS1_8822C */\n\n#define BIT_SHIFT_RF_RL_ID_8822C 28\n#define BIT_MASK_RF_RL_ID_8822C 0xf\n#define BIT_RF_RL_ID_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_RF_RL_ID_8822C) << BIT_SHIFT_RF_RL_ID_8822C)\n#define BITS_RF_RL_ID_8822C                                                    \\\n\t(BIT_MASK_RF_RL_ID_8822C << BIT_SHIFT_RF_RL_ID_8822C)\n#define BIT_CLEAR_RF_RL_ID_8822C(x) ((x) & (~BITS_RF_RL_ID_8822C))\n#define BIT_GET_RF_RL_ID_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RF_RL_ID_8822C) & BIT_MASK_RF_RL_ID_8822C)\n#define BIT_SET_RF_RL_ID_8822C(x, v)                                           \\\n\t(BIT_CLEAR_RF_RL_ID_8822C(x) | BIT_RF_RL_ID_8822C(v))\n\n#define BIT_HPHY_ICFG_8822C BIT(19)\n\n#define BIT_SHIFT_SEL_0XC0_8822C 16\n#define BIT_MASK_SEL_0XC0_8822C 0x3\n#define BIT_SEL_0XC0_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_SEL_0XC0_8822C) << BIT_SHIFT_SEL_0XC0_8822C)\n#define BITS_SEL_0XC0_8822C                                                    \\\n\t(BIT_MASK_SEL_0XC0_8822C << BIT_SHIFT_SEL_0XC0_8822C)\n#define BIT_CLEAR_SEL_0XC0_8822C(x) ((x) & (~BITS_SEL_0XC0_8822C))\n#define BIT_GET_SEL_0XC0_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_SEL_0XC0_8822C) & BIT_MASK_SEL_0XC0_8822C)\n#define BIT_SET_SEL_0XC0_8822C(x, v)                                           \\\n\t(BIT_CLEAR_SEL_0XC0_8822C(x) | BIT_SEL_0XC0_8822C(v))\n\n#define BIT_SHIFT_HCI_SEL_V4_8822C 12\n#define BIT_MASK_HCI_SEL_V4_8822C 0x3\n#define BIT_HCI_SEL_V4_8822C(x)                                                \\\n\t(((x) & BIT_MASK_HCI_SEL_V4_8822C) << BIT_SHIFT_HCI_SEL_V4_8822C)\n#define BITS_HCI_SEL_V4_8822C                                                  \\\n\t(BIT_MASK_HCI_SEL_V4_8822C << BIT_SHIFT_HCI_SEL_V4_8822C)\n#define BIT_CLEAR_HCI_SEL_V4_8822C(x) ((x) & (~BITS_HCI_SEL_V4_8822C))\n#define BIT_GET_HCI_SEL_V4_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_HCI_SEL_V4_8822C) & BIT_MASK_HCI_SEL_V4_8822C)\n#define BIT_SET_HCI_SEL_V4_8822C(x, v)                                         \\\n\t(BIT_CLEAR_HCI_SEL_V4_8822C(x) | BIT_HCI_SEL_V4_8822C(v))\n\n#define BIT_USB_OPERATION_MODE_8822C BIT(10)\n#define BIT_BT_PDN_8822C BIT(9)\n#define BIT_AUTO_WLPON_8822C BIT(8)\n#define BIT_WL_MODE_8822C BIT(7)\n#define BIT_PKG_SEL_HCI_8822C BIT(6)\n\n#define BIT_SHIFT_PAD_HCI_SEL_V2_8822C 3\n#define BIT_MASK_PAD_HCI_SEL_V2_8822C 0x3\n#define BIT_PAD_HCI_SEL_V2_8822C(x)                                            \\\n\t(((x) & BIT_MASK_PAD_HCI_SEL_V2_8822C)                                 \\\n\t << BIT_SHIFT_PAD_HCI_SEL_V2_8822C)\n#define BITS_PAD_HCI_SEL_V2_8822C                                              \\\n\t(BIT_MASK_PAD_HCI_SEL_V2_8822C << BIT_SHIFT_PAD_HCI_SEL_V2_8822C)\n#define BIT_CLEAR_PAD_HCI_SEL_V2_8822C(x) ((x) & (~BITS_PAD_HCI_SEL_V2_8822C))\n#define BIT_GET_PAD_HCI_SEL_V2_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_PAD_HCI_SEL_V2_8822C) &                             \\\n\t BIT_MASK_PAD_HCI_SEL_V2_8822C)\n#define BIT_SET_PAD_HCI_SEL_V2_8822C(x, v)                                     \\\n\t(BIT_CLEAR_PAD_HCI_SEL_V2_8822C(x) | BIT_PAD_HCI_SEL_V2_8822C(v))\n\n#define BIT_SHIFT_EFS_HCI_SEL_V1_8822C 0\n#define BIT_MASK_EFS_HCI_SEL_V1_8822C 0x7\n#define BIT_EFS_HCI_SEL_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_EFS_HCI_SEL_V1_8822C)                                 \\\n\t << BIT_SHIFT_EFS_HCI_SEL_V1_8822C)\n#define BITS_EFS_HCI_SEL_V1_8822C                                              \\\n\t(BIT_MASK_EFS_HCI_SEL_V1_8822C << BIT_SHIFT_EFS_HCI_SEL_V1_8822C)\n#define BIT_CLEAR_EFS_HCI_SEL_V1_8822C(x) ((x) & (~BITS_EFS_HCI_SEL_V1_8822C))\n#define BIT_GET_EFS_HCI_SEL_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_EFS_HCI_SEL_V1_8822C) &                             \\\n\t BIT_MASK_EFS_HCI_SEL_V1_8822C)\n#define BIT_SET_EFS_HCI_SEL_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_EFS_HCI_SEL_V1_8822C(x) | BIT_EFS_HCI_SEL_V1_8822C(v))\n\n/* 2 REG_SYS_STATUS2_8822C */\n#define BIT_HIOE_ON_TIMEOUT_8822C BIT(23)\n#define BIT_SIC_ON_TIMEOUT_8822C BIT(22)\n#define BIT_CPU_ON_TIMEOUT_8822C BIT(21)\n#define BIT_HCI_ON_TIMEOUT_8822C BIT(20)\n#define BIT_SIO_ALDN_8822C BIT(19)\n#define BIT_USB_ALDN_8822C BIT(18)\n#define BIT_PCI_ALDN_8822C BIT(17)\n#define BIT_SYS_ALDN_8822C BIT(16)\n\n#define BIT_SHIFT_EPVID1_8822C 8\n#define BIT_MASK_EPVID1_8822C 0xff\n#define BIT_EPVID1_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_EPVID1_8822C) << BIT_SHIFT_EPVID1_8822C)\n#define BITS_EPVID1_8822C (BIT_MASK_EPVID1_8822C << BIT_SHIFT_EPVID1_8822C)\n#define BIT_CLEAR_EPVID1_8822C(x) ((x) & (~BITS_EPVID1_8822C))\n#define BIT_GET_EPVID1_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_EPVID1_8822C) & BIT_MASK_EPVID1_8822C)\n#define BIT_SET_EPVID1_8822C(x, v)                                             \\\n\t(BIT_CLEAR_EPVID1_8822C(x) | BIT_EPVID1_8822C(v))\n\n#define BIT_SHIFT_EPVID0_8822C 0\n#define BIT_MASK_EPVID0_8822C 0xff\n#define BIT_EPVID0_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_EPVID0_8822C) << BIT_SHIFT_EPVID0_8822C)\n#define BITS_EPVID0_8822C (BIT_MASK_EPVID0_8822C << BIT_SHIFT_EPVID0_8822C)\n#define BIT_CLEAR_EPVID0_8822C(x) ((x) & (~BITS_EPVID0_8822C))\n#define BIT_GET_EPVID0_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_EPVID0_8822C) & BIT_MASK_EPVID0_8822C)\n#define BIT_SET_EPVID0_8822C(x, v)                                             \\\n\t(BIT_CLEAR_EPVID0_8822C(x) | BIT_EPVID0_8822C(v))\n\n/* 2 REG_SYS_CFG2_8822C */\n#define BIT_HCI_SEL_EMBEDDED_8822C BIT(8)\n\n#define BIT_SHIFT_HW_ID_8822C 0\n#define BIT_MASK_HW_ID_8822C 0xff\n#define BIT_HW_ID_8822C(x)                                                     \\\n\t(((x) & BIT_MASK_HW_ID_8822C) << BIT_SHIFT_HW_ID_8822C)\n#define BITS_HW_ID_8822C (BIT_MASK_HW_ID_8822C << BIT_SHIFT_HW_ID_8822C)\n#define BIT_CLEAR_HW_ID_8822C(x) ((x) & (~BITS_HW_ID_8822C))\n#define BIT_GET_HW_ID_8822C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_HW_ID_8822C) & BIT_MASK_HW_ID_8822C)\n#define BIT_SET_HW_ID_8822C(x, v)                                              \\\n\t(BIT_CLEAR_HW_ID_8822C(x) | BIT_HW_ID_8822C(v))\n\n/* 2 REG_SYS_CFG3_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_ANAPARSW_MAC_0_8822C */\n#define BIT_OCP_L_8822C BIT(31)\n#define BIT_POWOCP_L_8822C BIT(30)\n\n#define BIT_SHIFT_CF_L_V2_8822C 28\n#define BIT_MASK_CF_L_V2_8822C 0x3\n#define BIT_CF_L_V2_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_CF_L_V2_8822C) << BIT_SHIFT_CF_L_V2_8822C)\n#define BITS_CF_L_V2_8822C (BIT_MASK_CF_L_V2_8822C << BIT_SHIFT_CF_L_V2_8822C)\n#define BIT_CLEAR_CF_L_V2_8822C(x) ((x) & (~BITS_CF_L_V2_8822C))\n#define BIT_GET_CF_L_V2_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_CF_L_V2_8822C) & BIT_MASK_CF_L_V2_8822C)\n#define BIT_SET_CF_L_V2_8822C(x, v)                                            \\\n\t(BIT_CLEAR_CF_L_V2_8822C(x) | BIT_CF_L_V2_8822C(v))\n\n#define BIT_SHIFT_CFC_L_V2_8822C 26\n#define BIT_MASK_CFC_L_V2_8822C 0x3\n#define BIT_CFC_L_V2_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_CFC_L_V2_8822C) << BIT_SHIFT_CFC_L_V2_8822C)\n#define BITS_CFC_L_V2_8822C                                                    \\\n\t(BIT_MASK_CFC_L_V2_8822C << BIT_SHIFT_CFC_L_V2_8822C)\n#define BIT_CLEAR_CFC_L_V2_8822C(x) ((x) & (~BITS_CFC_L_V2_8822C))\n#define BIT_GET_CFC_L_V2_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_CFC_L_V2_8822C) & BIT_MASK_CFC_L_V2_8822C)\n#define BIT_SET_CFC_L_V2_8822C(x, v)                                           \\\n\t(BIT_CLEAR_CFC_L_V2_8822C(x) | BIT_CFC_L_V2_8822C(v))\n\n#define BIT_SHIFT_R3_L_V2_8822C 24\n#define BIT_MASK_R3_L_V2_8822C 0x3\n#define BIT_R3_L_V2_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_R3_L_V2_8822C) << BIT_SHIFT_R3_L_V2_8822C)\n#define BITS_R3_L_V2_8822C (BIT_MASK_R3_L_V2_8822C << BIT_SHIFT_R3_L_V2_8822C)\n#define BIT_CLEAR_R3_L_V2_8822C(x) ((x) & (~BITS_R3_L_V2_8822C))\n#define BIT_GET_R3_L_V2_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_R3_L_V2_8822C) & BIT_MASK_R3_L_V2_8822C)\n#define BIT_SET_R3_L_V2_8822C(x, v)                                            \\\n\t(BIT_CLEAR_R3_L_V2_8822C(x) | BIT_R3_L_V2_8822C(v))\n\n#define BIT_SHIFT_R2_L_8822C 22\n#define BIT_MASK_R2_L_8822C 0x3\n#define BIT_R2_L_8822C(x) (((x) & BIT_MASK_R2_L_8822C) << BIT_SHIFT_R2_L_8822C)\n#define BITS_R2_L_8822C (BIT_MASK_R2_L_8822C << BIT_SHIFT_R2_L_8822C)\n#define BIT_CLEAR_R2_L_8822C(x) ((x) & (~BITS_R2_L_8822C))\n#define BIT_GET_R2_L_8822C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_R2_L_8822C) & BIT_MASK_R2_L_8822C)\n#define BIT_SET_R2_L_8822C(x, v) (BIT_CLEAR_R2_L_8822C(x) | BIT_R2_L_8822C(v))\n\n#define BIT_SHIFT_R1_L_8822C 20\n#define BIT_MASK_R1_L_8822C 0x3\n#define BIT_R1_L_8822C(x) (((x) & BIT_MASK_R1_L_8822C) << BIT_SHIFT_R1_L_8822C)\n#define BITS_R1_L_8822C (BIT_MASK_R1_L_8822C << BIT_SHIFT_R1_L_8822C)\n#define BIT_CLEAR_R1_L_8822C(x) ((x) & (~BITS_R1_L_8822C))\n#define BIT_GET_R1_L_8822C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_R1_L_8822C) & BIT_MASK_R1_L_8822C)\n#define BIT_SET_R1_L_8822C(x, v) (BIT_CLEAR_R1_L_8822C(x) | BIT_R1_L_8822C(v))\n\n#define BIT_SHIFT_C3_L_8822C 18\n#define BIT_MASK_C3_L_8822C 0x3\n#define BIT_C3_L_8822C(x) (((x) & BIT_MASK_C3_L_8822C) << BIT_SHIFT_C3_L_8822C)\n#define BITS_C3_L_8822C (BIT_MASK_C3_L_8822C << BIT_SHIFT_C3_L_8822C)\n#define BIT_CLEAR_C3_L_8822C(x) ((x) & (~BITS_C3_L_8822C))\n#define BIT_GET_C3_L_8822C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_C3_L_8822C) & BIT_MASK_C3_L_8822C)\n#define BIT_SET_C3_L_8822C(x, v) (BIT_CLEAR_C3_L_8822C(x) | BIT_C3_L_8822C(v))\n\n#define BIT_SHIFT_C2_L_8822C 16\n#define BIT_MASK_C2_L_8822C 0x3\n#define BIT_C2_L_8822C(x) (((x) & BIT_MASK_C2_L_8822C) << BIT_SHIFT_C2_L_8822C)\n#define BITS_C2_L_8822C (BIT_MASK_C2_L_8822C << BIT_SHIFT_C2_L_8822C)\n#define BIT_CLEAR_C2_L_8822C(x) ((x) & (~BITS_C2_L_8822C))\n#define BIT_GET_C2_L_8822C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_C2_L_8822C) & BIT_MASK_C2_L_8822C)\n#define BIT_SET_C2_L_8822C(x, v) (BIT_CLEAR_C2_L_8822C(x) | BIT_C2_L_8822C(v))\n\n#define BIT_SHIFT_C1_L_V2_8822C 14\n#define BIT_MASK_C1_L_V2_8822C 0x3\n#define BIT_C1_L_V2_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_C1_L_V2_8822C) << BIT_SHIFT_C1_L_V2_8822C)\n#define BITS_C1_L_V2_8822C (BIT_MASK_C1_L_V2_8822C << BIT_SHIFT_C1_L_V2_8822C)\n#define BIT_CLEAR_C1_L_V2_8822C(x) ((x) & (~BITS_C1_L_V2_8822C))\n#define BIT_GET_C1_L_V2_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_C1_L_V2_8822C) & BIT_MASK_C1_L_V2_8822C)\n#define BIT_SET_C1_L_V2_8822C(x, v)                                            \\\n\t(BIT_CLEAR_C1_L_V2_8822C(x) | BIT_C1_L_V2_8822C(v))\n\n#define BIT_REG_OCPS_L_V2_8822C BIT(13)\n#define BIT_REG_PWM_L_8822C BIT(12)\n\n#define BIT_SHIFT_V15ADJ_L_8822C 9\n#define BIT_MASK_V15ADJ_L_8822C 0x7\n#define BIT_V15ADJ_L_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_V15ADJ_L_8822C) << BIT_SHIFT_V15ADJ_L_8822C)\n#define BITS_V15ADJ_L_8822C                                                    \\\n\t(BIT_MASK_V15ADJ_L_8822C << BIT_SHIFT_V15ADJ_L_8822C)\n#define BIT_CLEAR_V15ADJ_L_8822C(x) ((x) & (~BITS_V15ADJ_L_8822C))\n#define BIT_GET_V15ADJ_L_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_V15ADJ_L_8822C) & BIT_MASK_V15ADJ_L_8822C)\n#define BIT_SET_V15ADJ_L_8822C(x, v)                                           \\\n\t(BIT_CLEAR_V15ADJ_L_8822C(x) | BIT_V15ADJ_L_8822C(v))\n\n#define BIT_SHIFT_IN_L_8822C 6\n#define BIT_MASK_IN_L_8822C 0x7\n#define BIT_IN_L_8822C(x) (((x) & BIT_MASK_IN_L_8822C) << BIT_SHIFT_IN_L_8822C)\n#define BITS_IN_L_8822C (BIT_MASK_IN_L_8822C << BIT_SHIFT_IN_L_8822C)\n#define BIT_CLEAR_IN_L_8822C(x) ((x) & (~BITS_IN_L_8822C))\n#define BIT_GET_IN_L_8822C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_IN_L_8822C) & BIT_MASK_IN_L_8822C)\n#define BIT_SET_IN_L_8822C(x, v) (BIT_CLEAR_IN_L_8822C(x) | BIT_IN_L_8822C(v))\n\n#define BIT_SHIFT_STD_L_8822C 4\n#define BIT_MASK_STD_L_8822C 0x3\n#define BIT_STD_L_8822C(x)                                                     \\\n\t(((x) & BIT_MASK_STD_L_8822C) << BIT_SHIFT_STD_L_8822C)\n#define BITS_STD_L_8822C (BIT_MASK_STD_L_8822C << BIT_SHIFT_STD_L_8822C)\n#define BIT_CLEAR_STD_L_8822C(x) ((x) & (~BITS_STD_L_8822C))\n#define BIT_GET_STD_L_8822C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_STD_L_8822C) & BIT_MASK_STD_L_8822C)\n#define BIT_SET_STD_L_8822C(x, v)                                              \\\n\t(BIT_CLEAR_STD_L_8822C(x) | BIT_STD_L_8822C(v))\n\n#define BIT_SHIFT_VOL_L_8822C 0\n#define BIT_MASK_VOL_L_8822C 0xf\n#define BIT_VOL_L_8822C(x)                                                     \\\n\t(((x) & BIT_MASK_VOL_L_8822C) << BIT_SHIFT_VOL_L_8822C)\n#define BITS_VOL_L_8822C (BIT_MASK_VOL_L_8822C << BIT_SHIFT_VOL_L_8822C)\n#define BIT_CLEAR_VOL_L_8822C(x) ((x) & (~BITS_VOL_L_8822C))\n#define BIT_GET_VOL_L_8822C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_VOL_L_8822C) & BIT_MASK_VOL_L_8822C)\n#define BIT_SET_VOL_L_8822C(x, v)                                              \\\n\t(BIT_CLEAR_VOL_L_8822C(x) | BIT_VOL_L_8822C(v))\n\n/* 2 REG_ANAPARSW_MAC_1_8822C */\n\n#define BIT_SHIFT_OCP_L_PFM_8822C 29\n#define BIT_MASK_OCP_L_PFM_8822C 0x7\n#define BIT_OCP_L_PFM_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_OCP_L_PFM_8822C) << BIT_SHIFT_OCP_L_PFM_8822C)\n#define BITS_OCP_L_PFM_8822C                                                   \\\n\t(BIT_MASK_OCP_L_PFM_8822C << BIT_SHIFT_OCP_L_PFM_8822C)\n#define BIT_CLEAR_OCP_L_PFM_8822C(x) ((x) & (~BITS_OCP_L_PFM_8822C))\n#define BIT_GET_OCP_L_PFM_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_OCP_L_PFM_8822C) & BIT_MASK_OCP_L_PFM_8822C)\n#define BIT_SET_OCP_L_PFM_8822C(x, v)                                          \\\n\t(BIT_CLEAR_OCP_L_PFM_8822C(x) | BIT_OCP_L_PFM_8822C(v))\n\n#define BIT_SHIFT_CFC_L_PFM_8822C 27\n#define BIT_MASK_CFC_L_PFM_8822C 0x3\n#define BIT_CFC_L_PFM_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_CFC_L_PFM_8822C) << BIT_SHIFT_CFC_L_PFM_8822C)\n#define BITS_CFC_L_PFM_8822C                                                   \\\n\t(BIT_MASK_CFC_L_PFM_8822C << BIT_SHIFT_CFC_L_PFM_8822C)\n#define BIT_CLEAR_CFC_L_PFM_8822C(x) ((x) & (~BITS_CFC_L_PFM_8822C))\n#define BIT_GET_CFC_L_PFM_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_CFC_L_PFM_8822C) & BIT_MASK_CFC_L_PFM_8822C)\n#define BIT_SET_CFC_L_PFM_8822C(x, v)                                          \\\n\t(BIT_CLEAR_CFC_L_PFM_8822C(x) | BIT_CFC_L_PFM_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_REG_FREQ_L_V1_8822C 20\n#define BIT_MASK_REG_FREQ_L_V1_8822C 0x7\n#define BIT_REG_FREQ_L_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_REG_FREQ_L_V1_8822C) << BIT_SHIFT_REG_FREQ_L_V1_8822C)\n#define BITS_REG_FREQ_L_V1_8822C                                               \\\n\t(BIT_MASK_REG_FREQ_L_V1_8822C << BIT_SHIFT_REG_FREQ_L_V1_8822C)\n#define BIT_CLEAR_REG_FREQ_L_V1_8822C(x) ((x) & (~BITS_REG_FREQ_L_V1_8822C))\n#define BIT_GET_REG_FREQ_L_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_REG_FREQ_L_V1_8822C) & BIT_MASK_REG_FREQ_L_V1_8822C)\n#define BIT_SET_REG_FREQ_L_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_REG_FREQ_L_V1_8822C(x) | BIT_REG_FREQ_L_V1_8822C(v))\n\n#define BIT_EN_DUTY_8822C BIT(19)\n\n#define BIT_SHIFT_REG_MODE_V2_8822C 17\n#define BIT_MASK_REG_MODE_V2_8822C 0x3\n#define BIT_REG_MODE_V2_8822C(x)                                               \\\n\t(((x) & BIT_MASK_REG_MODE_V2_8822C) << BIT_SHIFT_REG_MODE_V2_8822C)\n#define BITS_REG_MODE_V2_8822C                                                 \\\n\t(BIT_MASK_REG_MODE_V2_8822C << BIT_SHIFT_REG_MODE_V2_8822C)\n#define BIT_CLEAR_REG_MODE_V2_8822C(x) ((x) & (~BITS_REG_MODE_V2_8822C))\n#define BIT_GET_REG_MODE_V2_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_REG_MODE_V2_8822C) & BIT_MASK_REG_MODE_V2_8822C)\n#define BIT_SET_REG_MODE_V2_8822C(x, v)                                        \\\n\t(BIT_CLEAR_REG_MODE_V2_8822C(x) | BIT_REG_MODE_V2_8822C(v))\n\n#define BIT_EN_SP_8822C BIT(16)\n#define BIT_REG_AUTO_L_V2_8822C BIT(15)\n#define BIT_REG_LDOF_L_V2_8822C BIT(14)\n#define BIT_REG_TYPE_L_V2_8822C BIT(13)\n#define BIT_VO15_V1P05_H_8822C BIT(12)\n#define BIT_ARENB_L_V2_8822C BIT(11)\n\n#define BIT_SHIFT_TBOX_L1_V2_8822C 9\n#define BIT_MASK_TBOX_L1_V2_8822C 0x3\n#define BIT_TBOX_L1_V2_8822C(x)                                                \\\n\t(((x) & BIT_MASK_TBOX_L1_V2_8822C) << BIT_SHIFT_TBOX_L1_V2_8822C)\n#define BITS_TBOX_L1_V2_8822C                                                  \\\n\t(BIT_MASK_TBOX_L1_V2_8822C << BIT_SHIFT_TBOX_L1_V2_8822C)\n#define BIT_CLEAR_TBOX_L1_V2_8822C(x) ((x) & (~BITS_TBOX_L1_V2_8822C))\n#define BIT_GET_TBOX_L1_V2_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_TBOX_L1_V2_8822C) & BIT_MASK_TBOX_L1_V2_8822C)\n#define BIT_SET_TBOX_L1_V2_8822C(x, v)                                         \\\n\t(BIT_CLEAR_TBOX_L1_V2_8822C(x) | BIT_TBOX_L1_V2_8822C(v))\n\n#define BIT_SHIFT_REG_DELAY_L_8822C 7\n#define BIT_MASK_REG_DELAY_L_8822C 0x3\n#define BIT_REG_DELAY_L_8822C(x)                                               \\\n\t(((x) & BIT_MASK_REG_DELAY_L_8822C) << BIT_SHIFT_REG_DELAY_L_8822C)\n#define BITS_REG_DELAY_L_8822C                                                 \\\n\t(BIT_MASK_REG_DELAY_L_8822C << BIT_SHIFT_REG_DELAY_L_8822C)\n#define BIT_CLEAR_REG_DELAY_L_8822C(x) ((x) & (~BITS_REG_DELAY_L_8822C))\n#define BIT_GET_REG_DELAY_L_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_REG_DELAY_L_8822C) & BIT_MASK_REG_DELAY_L_8822C)\n#define BIT_SET_REG_DELAY_L_8822C(x, v)                                        \\\n\t(BIT_CLEAR_REG_DELAY_L_8822C(x) | BIT_REG_DELAY_L_8822C(v))\n\n#define BIT_REG_CLAMP_D_L_8822C BIT(6)\n#define BIT_REG_BYPASS_L_V2_8822C BIT(5)\n#define BIT_REG_AUTOZCD_L_8822C BIT(4)\n#define BIT_POW_ZCD_L_V2_8822C BIT(3)\n#define BIT_REG_HALF_L_8822C BIT(2)\n\n#define BIT_SHIFT_OCP_L_V2_8822C 0\n#define BIT_MASK_OCP_L_V2_8822C 0x3\n#define BIT_OCP_L_V2_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_OCP_L_V2_8822C) << BIT_SHIFT_OCP_L_V2_8822C)\n#define BITS_OCP_L_V2_8822C                                                    \\\n\t(BIT_MASK_OCP_L_V2_8822C << BIT_SHIFT_OCP_L_V2_8822C)\n#define BIT_CLEAR_OCP_L_V2_8822C(x) ((x) & (~BITS_OCP_L_V2_8822C))\n#define BIT_GET_OCP_L_V2_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_OCP_L_V2_8822C) & BIT_MASK_OCP_L_V2_8822C)\n#define BIT_SET_OCP_L_V2_8822C(x, v)                                           \\\n\t(BIT_CLEAR_OCP_L_V2_8822C(x) | BIT_OCP_L_V2_8822C(v))\n\n/* 2 REG_ANAPAR_MAC_0_8822C */\n\n#define BIT_SHIFT_REG_LPF_R3_8822C 29\n#define BIT_MASK_REG_LPF_R3_8822C 0x7\n#define BIT_REG_LPF_R3_8822C(x)                                                \\\n\t(((x) & BIT_MASK_REG_LPF_R3_8822C) << BIT_SHIFT_REG_LPF_R3_8822C)\n#define BITS_REG_LPF_R3_8822C                                                  \\\n\t(BIT_MASK_REG_LPF_R3_8822C << BIT_SHIFT_REG_LPF_R3_8822C)\n#define BIT_CLEAR_REG_LPF_R3_8822C(x) ((x) & (~BITS_REG_LPF_R3_8822C))\n#define BIT_GET_REG_LPF_R3_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_REG_LPF_R3_8822C) & BIT_MASK_REG_LPF_R3_8822C)\n#define BIT_SET_REG_LPF_R3_8822C(x, v)                                         \\\n\t(BIT_CLEAR_REG_LPF_R3_8822C(x) | BIT_REG_LPF_R3_8822C(v))\n\n#define BIT_SHIFT_REG_LPF_R2_8822C 24\n#define BIT_MASK_REG_LPF_R2_8822C 0x1f\n#define BIT_REG_LPF_R2_8822C(x)                                                \\\n\t(((x) & BIT_MASK_REG_LPF_R2_8822C) << BIT_SHIFT_REG_LPF_R2_8822C)\n#define BITS_REG_LPF_R2_8822C                                                  \\\n\t(BIT_MASK_REG_LPF_R2_8822C << BIT_SHIFT_REG_LPF_R2_8822C)\n#define BIT_CLEAR_REG_LPF_R2_8822C(x) ((x) & (~BITS_REG_LPF_R2_8822C))\n#define BIT_GET_REG_LPF_R2_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_REG_LPF_R2_8822C) & BIT_MASK_REG_LPF_R2_8822C)\n#define BIT_SET_REG_LPF_R2_8822C(x, v)                                         \\\n\t(BIT_CLEAR_REG_LPF_R2_8822C(x) | BIT_REG_LPF_R2_8822C(v))\n\n#define BIT_SHIFT_REG_LPF_C3_8822C 21\n#define BIT_MASK_REG_LPF_C3_8822C 0x7\n#define BIT_REG_LPF_C3_8822C(x)                                                \\\n\t(((x) & BIT_MASK_REG_LPF_C3_8822C) << BIT_SHIFT_REG_LPF_C3_8822C)\n#define BITS_REG_LPF_C3_8822C                                                  \\\n\t(BIT_MASK_REG_LPF_C3_8822C << BIT_SHIFT_REG_LPF_C3_8822C)\n#define BIT_CLEAR_REG_LPF_C3_8822C(x) ((x) & (~BITS_REG_LPF_C3_8822C))\n#define BIT_GET_REG_LPF_C3_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_REG_LPF_C3_8822C) & BIT_MASK_REG_LPF_C3_8822C)\n#define BIT_SET_REG_LPF_C3_8822C(x, v)                                         \\\n\t(BIT_CLEAR_REG_LPF_C3_8822C(x) | BIT_REG_LPF_C3_8822C(v))\n\n#define BIT_SHIFT_REG_LPF_C2_8822C 18\n#define BIT_MASK_REG_LPF_C2_8822C 0x7\n#define BIT_REG_LPF_C2_8822C(x)                                                \\\n\t(((x) & BIT_MASK_REG_LPF_C2_8822C) << BIT_SHIFT_REG_LPF_C2_8822C)\n#define BITS_REG_LPF_C2_8822C                                                  \\\n\t(BIT_MASK_REG_LPF_C2_8822C << BIT_SHIFT_REG_LPF_C2_8822C)\n#define BIT_CLEAR_REG_LPF_C2_8822C(x) ((x) & (~BITS_REG_LPF_C2_8822C))\n#define BIT_GET_REG_LPF_C2_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_REG_LPF_C2_8822C) & BIT_MASK_REG_LPF_C2_8822C)\n#define BIT_SET_REG_LPF_C2_8822C(x, v)                                         \\\n\t(BIT_CLEAR_REG_LPF_C2_8822C(x) | BIT_REG_LPF_C2_8822C(v))\n\n#define BIT_SHIFT_REG_LPF_C1_8822C 15\n#define BIT_MASK_REG_LPF_C1_8822C 0x7\n#define BIT_REG_LPF_C1_8822C(x)                                                \\\n\t(((x) & BIT_MASK_REG_LPF_C1_8822C) << BIT_SHIFT_REG_LPF_C1_8822C)\n#define BITS_REG_LPF_C1_8822C                                                  \\\n\t(BIT_MASK_REG_LPF_C1_8822C << BIT_SHIFT_REG_LPF_C1_8822C)\n#define BIT_CLEAR_REG_LPF_C1_8822C(x) ((x) & (~BITS_REG_LPF_C1_8822C))\n#define BIT_GET_REG_LPF_C1_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_REG_LPF_C1_8822C) & BIT_MASK_REG_LPF_C1_8822C)\n#define BIT_SET_REG_LPF_C1_8822C(x, v)                                         \\\n\t(BIT_CLEAR_REG_LPF_C1_8822C(x) | BIT_REG_LPF_C1_8822C(v))\n\n#define BIT_SHIFT_REG_LDO_SEL_V1_8822C 13\n#define BIT_MASK_REG_LDO_SEL_V1_8822C 0x3\n#define BIT_REG_LDO_SEL_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_REG_LDO_SEL_V1_8822C)                                 \\\n\t << BIT_SHIFT_REG_LDO_SEL_V1_8822C)\n#define BITS_REG_LDO_SEL_V1_8822C                                              \\\n\t(BIT_MASK_REG_LDO_SEL_V1_8822C << BIT_SHIFT_REG_LDO_SEL_V1_8822C)\n#define BIT_CLEAR_REG_LDO_SEL_V1_8822C(x) ((x) & (~BITS_REG_LDO_SEL_V1_8822C))\n#define BIT_GET_REG_LDO_SEL_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_REG_LDO_SEL_V1_8822C) &                             \\\n\t BIT_MASK_REG_LDO_SEL_V1_8822C)\n#define BIT_SET_REG_LDO_SEL_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_REG_LDO_SEL_V1_8822C(x) | BIT_REG_LDO_SEL_V1_8822C(v))\n\n#define BIT_REG_CP_ICPX2_8822C BIT(12)\n\n#define BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C 9\n#define BIT_MASK_REG_CP_ICP_SEL_FAST_8822C 0x7\n#define BIT_REG_CP_ICP_SEL_FAST_8822C(x)                                       \\\n\t(((x) & BIT_MASK_REG_CP_ICP_SEL_FAST_8822C)                            \\\n\t << BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C)\n#define BITS_REG_CP_ICP_SEL_FAST_8822C                                         \\\n\t(BIT_MASK_REG_CP_ICP_SEL_FAST_8822C                                    \\\n\t << BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C)\n#define BIT_CLEAR_REG_CP_ICP_SEL_FAST_8822C(x)                                 \\\n\t((x) & (~BITS_REG_CP_ICP_SEL_FAST_8822C))\n#define BIT_GET_REG_CP_ICP_SEL_FAST_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C) &                        \\\n\t BIT_MASK_REG_CP_ICP_SEL_FAST_8822C)\n#define BIT_SET_REG_CP_ICP_SEL_FAST_8822C(x, v)                                \\\n\t(BIT_CLEAR_REG_CP_ICP_SEL_FAST_8822C(x) |                              \\\n\t BIT_REG_CP_ICP_SEL_FAST_8822C(v))\n\n#define BIT_SHIFT_REG_CP_ICP_SEL_8822C 6\n#define BIT_MASK_REG_CP_ICP_SEL_8822C 0x7\n#define BIT_REG_CP_ICP_SEL_8822C(x)                                            \\\n\t(((x) & BIT_MASK_REG_CP_ICP_SEL_8822C)                                 \\\n\t << BIT_SHIFT_REG_CP_ICP_SEL_8822C)\n#define BITS_REG_CP_ICP_SEL_8822C                                              \\\n\t(BIT_MASK_REG_CP_ICP_SEL_8822C << BIT_SHIFT_REG_CP_ICP_SEL_8822C)\n#define BIT_CLEAR_REG_CP_ICP_SEL_8822C(x) ((x) & (~BITS_REG_CP_ICP_SEL_8822C))\n#define BIT_GET_REG_CP_ICP_SEL_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_REG_CP_ICP_SEL_8822C) &                             \\\n\t BIT_MASK_REG_CP_ICP_SEL_8822C)\n#define BIT_SET_REG_CP_ICP_SEL_8822C(x, v)                                     \\\n\t(BIT_CLEAR_REG_CP_ICP_SEL_8822C(x) | BIT_REG_CP_ICP_SEL_8822C(v))\n\n#define BIT_SHIFT_REG_IB_PI_8822C 4\n#define BIT_MASK_REG_IB_PI_8822C 0x3\n#define BIT_REG_IB_PI_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_REG_IB_PI_8822C) << BIT_SHIFT_REG_IB_PI_8822C)\n#define BITS_REG_IB_PI_8822C                                                   \\\n\t(BIT_MASK_REG_IB_PI_8822C << BIT_SHIFT_REG_IB_PI_8822C)\n#define BIT_CLEAR_REG_IB_PI_8822C(x) ((x) & (~BITS_REG_IB_PI_8822C))\n#define BIT_GET_REG_IB_PI_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_REG_IB_PI_8822C) & BIT_MASK_REG_IB_PI_8822C)\n#define BIT_SET_REG_IB_PI_8822C(x, v)                                          \\\n\t(BIT_CLEAR_REG_IB_PI_8822C(x) | BIT_REG_IB_PI_8822C(v))\n\n#define BIT_LDO2PWRCUT_8822C BIT(3)\n#define BIT_VPULSE_LDO_8822C BIT(2)\n\n#define BIT_SHIFT_LDO_VSEL_8822C 0\n#define BIT_MASK_LDO_VSEL_8822C 0x3\n#define BIT_LDO_VSEL_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_LDO_VSEL_8822C) << BIT_SHIFT_LDO_VSEL_8822C)\n#define BITS_LDO_VSEL_8822C                                                    \\\n\t(BIT_MASK_LDO_VSEL_8822C << BIT_SHIFT_LDO_VSEL_8822C)\n#define BIT_CLEAR_LDO_VSEL_8822C(x) ((x) & (~BITS_LDO_VSEL_8822C))\n#define BIT_GET_LDO_VSEL_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_LDO_VSEL_8822C) & BIT_MASK_LDO_VSEL_8822C)\n#define BIT_SET_LDO_VSEL_8822C(x, v)                                           \\\n\t(BIT_CLEAR_LDO_VSEL_8822C(x) | BIT_LDO_VSEL_8822C(v))\n\n/* 2 REG_ANAPAR_MAC_1_8822C */\n\n#define BIT_SHIFT_REG_CK_MON_SEL_8822C 29\n#define BIT_MASK_REG_CK_MON_SEL_8822C 0x7\n#define BIT_REG_CK_MON_SEL_8822C(x)                                            \\\n\t(((x) & BIT_MASK_REG_CK_MON_SEL_8822C)                                 \\\n\t << BIT_SHIFT_REG_CK_MON_SEL_8822C)\n#define BITS_REG_CK_MON_SEL_8822C                                              \\\n\t(BIT_MASK_REG_CK_MON_SEL_8822C << BIT_SHIFT_REG_CK_MON_SEL_8822C)\n#define BIT_CLEAR_REG_CK_MON_SEL_8822C(x) ((x) & (~BITS_REG_CK_MON_SEL_8822C))\n#define BIT_GET_REG_CK_MON_SEL_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_REG_CK_MON_SEL_8822C) &                             \\\n\t BIT_MASK_REG_CK_MON_SEL_8822C)\n#define BIT_SET_REG_CK_MON_SEL_8822C(x, v)                                     \\\n\t(BIT_CLEAR_REG_CK_MON_SEL_8822C(x) | BIT_REG_CK_MON_SEL_8822C(v))\n\n#define BIT_REG_CK_MON_EN_8822C BIT(28)\n#define BIT_REG_XTAL_FREQ_SEL_8822C BIT(27)\n#define BIT_REG_XTAL_EDGE_SEL_8822C BIT(26)\n#define BIT_REG_VCO_KVCO_8822C BIT(25)\n#define BIT_REG_SDM_EDGE_SEL_8822C BIT(24)\n#define BIT_REG_SDM_CK_SEL_8822C BIT(23)\n#define BIT_REG_SDM_CK_GATED_8822C BIT(22)\n#define BIT_REG_PFD_RESET_GATED_8822C BIT(21)\n\n#define BIT_SHIFT_REG_LPF_R3_FAST_8822C 16\n#define BIT_MASK_REG_LPF_R3_FAST_8822C 0x1f\n#define BIT_REG_LPF_R3_FAST_8822C(x)                                           \\\n\t(((x) & BIT_MASK_REG_LPF_R3_FAST_8822C)                                \\\n\t << BIT_SHIFT_REG_LPF_R3_FAST_8822C)\n#define BITS_REG_LPF_R3_FAST_8822C                                             \\\n\t(BIT_MASK_REG_LPF_R3_FAST_8822C << BIT_SHIFT_REG_LPF_R3_FAST_8822C)\n#define BIT_CLEAR_REG_LPF_R3_FAST_8822C(x) ((x) & (~BITS_REG_LPF_R3_FAST_8822C))\n#define BIT_GET_REG_LPF_R3_FAST_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_REG_LPF_R3_FAST_8822C) &                            \\\n\t BIT_MASK_REG_LPF_R3_FAST_8822C)\n#define BIT_SET_REG_LPF_R3_FAST_8822C(x, v)                                    \\\n\t(BIT_CLEAR_REG_LPF_R3_FAST_8822C(x) | BIT_REG_LPF_R3_FAST_8822C(v))\n\n#define BIT_SHIFT_REG_LPF_R2_FAST_8822C 11\n#define BIT_MASK_REG_LPF_R2_FAST_8822C 0x1f\n#define BIT_REG_LPF_R2_FAST_8822C(x)                                           \\\n\t(((x) & BIT_MASK_REG_LPF_R2_FAST_8822C)                                \\\n\t << BIT_SHIFT_REG_LPF_R2_FAST_8822C)\n#define BITS_REG_LPF_R2_FAST_8822C                                             \\\n\t(BIT_MASK_REG_LPF_R2_FAST_8822C << BIT_SHIFT_REG_LPF_R2_FAST_8822C)\n#define BIT_CLEAR_REG_LPF_R2_FAST_8822C(x) ((x) & (~BITS_REG_LPF_R2_FAST_8822C))\n#define BIT_GET_REG_LPF_R2_FAST_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_REG_LPF_R2_FAST_8822C) &                            \\\n\t BIT_MASK_REG_LPF_R2_FAST_8822C)\n#define BIT_SET_REG_LPF_R2_FAST_8822C(x, v)                                    \\\n\t(BIT_CLEAR_REG_LPF_R2_FAST_8822C(x) | BIT_REG_LPF_R2_FAST_8822C(v))\n\n#define BIT_SHIFT_REG_LPF_C3_FAST_8822C 8\n#define BIT_MASK_REG_LPF_C3_FAST_8822C 0x7\n#define BIT_REG_LPF_C3_FAST_8822C(x)                                           \\\n\t(((x) & BIT_MASK_REG_LPF_C3_FAST_8822C)                                \\\n\t << BIT_SHIFT_REG_LPF_C3_FAST_8822C)\n#define BITS_REG_LPF_C3_FAST_8822C                                             \\\n\t(BIT_MASK_REG_LPF_C3_FAST_8822C << BIT_SHIFT_REG_LPF_C3_FAST_8822C)\n#define BIT_CLEAR_REG_LPF_C3_FAST_8822C(x) ((x) & (~BITS_REG_LPF_C3_FAST_8822C))\n#define BIT_GET_REG_LPF_C3_FAST_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_REG_LPF_C3_FAST_8822C) &                            \\\n\t BIT_MASK_REG_LPF_C3_FAST_8822C)\n#define BIT_SET_REG_LPF_C3_FAST_8822C(x, v)                                    \\\n\t(BIT_CLEAR_REG_LPF_C3_FAST_8822C(x) | BIT_REG_LPF_C3_FAST_8822C(v))\n\n#define BIT_SHIFT_REG_LPF_C2_FAST_8822C 5\n#define BIT_MASK_REG_LPF_C2_FAST_8822C 0x7\n#define BIT_REG_LPF_C2_FAST_8822C(x)                                           \\\n\t(((x) & BIT_MASK_REG_LPF_C2_FAST_8822C)                                \\\n\t << BIT_SHIFT_REG_LPF_C2_FAST_8822C)\n#define BITS_REG_LPF_C2_FAST_8822C                                             \\\n\t(BIT_MASK_REG_LPF_C2_FAST_8822C << BIT_SHIFT_REG_LPF_C2_FAST_8822C)\n#define BIT_CLEAR_REG_LPF_C2_FAST_8822C(x) ((x) & (~BITS_REG_LPF_C2_FAST_8822C))\n#define BIT_GET_REG_LPF_C2_FAST_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_REG_LPF_C2_FAST_8822C) &                            \\\n\t BIT_MASK_REG_LPF_C2_FAST_8822C)\n#define BIT_SET_REG_LPF_C2_FAST_8822C(x, v)                                    \\\n\t(BIT_CLEAR_REG_LPF_C2_FAST_8822C(x) | BIT_REG_LPF_C2_FAST_8822C(v))\n\n#define BIT_SHIFT_REG_LPF_C1_FAST_8822C 2\n#define BIT_MASK_REG_LPF_C1_FAST_8822C 0x7\n#define BIT_REG_LPF_C1_FAST_8822C(x)                                           \\\n\t(((x) & BIT_MASK_REG_LPF_C1_FAST_8822C)                                \\\n\t << BIT_SHIFT_REG_LPF_C1_FAST_8822C)\n#define BITS_REG_LPF_C1_FAST_8822C                                             \\\n\t(BIT_MASK_REG_LPF_C1_FAST_8822C << BIT_SHIFT_REG_LPF_C1_FAST_8822C)\n#define BIT_CLEAR_REG_LPF_C1_FAST_8822C(x) ((x) & (~BITS_REG_LPF_C1_FAST_8822C))\n#define BIT_GET_REG_LPF_C1_FAST_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_REG_LPF_C1_FAST_8822C) &                            \\\n\t BIT_MASK_REG_LPF_C1_FAST_8822C)\n#define BIT_SET_REG_LPF_C1_FAST_8822C(x, v)                                    \\\n\t(BIT_CLEAR_REG_LPF_C1_FAST_8822C(x) | BIT_REG_LPF_C1_FAST_8822C(v))\n\n#define BIT_SHIFT_REG_LPF_R3_V1_8822C 0\n#define BIT_MASK_REG_LPF_R3_V1_8822C 0x3\n#define BIT_REG_LPF_R3_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_REG_LPF_R3_V1_8822C) << BIT_SHIFT_REG_LPF_R3_V1_8822C)\n#define BITS_REG_LPF_R3_V1_8822C                                               \\\n\t(BIT_MASK_REG_LPF_R3_V1_8822C << BIT_SHIFT_REG_LPF_R3_V1_8822C)\n#define BIT_CLEAR_REG_LPF_R3_V1_8822C(x) ((x) & (~BITS_REG_LPF_R3_V1_8822C))\n#define BIT_GET_REG_LPF_R3_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_REG_LPF_R3_V1_8822C) & BIT_MASK_REG_LPF_R3_V1_8822C)\n#define BIT_SET_REG_LPF_R3_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_REG_LPF_R3_V1_8822C(x) | BIT_REG_LPF_R3_V1_8822C(v))\n\n/* 2 REG_ANAPAR_MAC_2_8822C */\n\n#define BIT_SHIFT_AGPIO_DRV_V1_8822C 30\n#define BIT_MASK_AGPIO_DRV_V1_8822C 0x3\n#define BIT_AGPIO_DRV_V1_8822C(x)                                              \\\n\t(((x) & BIT_MASK_AGPIO_DRV_V1_8822C) << BIT_SHIFT_AGPIO_DRV_V1_8822C)\n#define BITS_AGPIO_DRV_V1_8822C                                                \\\n\t(BIT_MASK_AGPIO_DRV_V1_8822C << BIT_SHIFT_AGPIO_DRV_V1_8822C)\n#define BIT_CLEAR_AGPIO_DRV_V1_8822C(x) ((x) & (~BITS_AGPIO_DRV_V1_8822C))\n#define BIT_GET_AGPIO_DRV_V1_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AGPIO_DRV_V1_8822C) & BIT_MASK_AGPIO_DRV_V1_8822C)\n#define BIT_SET_AGPIO_DRV_V1_8822C(x, v)                                       \\\n\t(BIT_CLEAR_AGPIO_DRV_V1_8822C(x) | BIT_AGPIO_DRV_V1_8822C(v))\n\n#define BIT_AGPIO_GPO_V1_8822C BIT(29)\n#define BIT_AGPIO_GPE_V1_8822C BIT(28)\n#define BIT_SEL_CLK_8822C BIT(27)\n\n#define BIT_SHIFT_LS_XTAL_SEL_8822C 23\n#define BIT_MASK_LS_XTAL_SEL_8822C 0xf\n#define BIT_LS_XTAL_SEL_8822C(x)                                               \\\n\t(((x) & BIT_MASK_LS_XTAL_SEL_8822C) << BIT_SHIFT_LS_XTAL_SEL_8822C)\n#define BITS_LS_XTAL_SEL_8822C                                                 \\\n\t(BIT_MASK_LS_XTAL_SEL_8822C << BIT_SHIFT_LS_XTAL_SEL_8822C)\n#define BIT_CLEAR_LS_XTAL_SEL_8822C(x) ((x) & (~BITS_LS_XTAL_SEL_8822C))\n#define BIT_GET_LS_XTAL_SEL_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_LS_XTAL_SEL_8822C) & BIT_MASK_LS_XTAL_SEL_8822C)\n#define BIT_SET_LS_XTAL_SEL_8822C(x, v)                                        \\\n\t(BIT_CLEAR_LS_XTAL_SEL_8822C(x) | BIT_LS_XTAL_SEL_8822C(v))\n\n#define BIT_LS_SDM_ORDER_V1_8822C BIT(22)\n#define BIT_LS_DELAY_PH_8822C BIT(21)\n#define BIT_DIVIDER_SEL_8822C BIT(20)\n\n#define BIT_SHIFT_PCODE_8822C 15\n#define BIT_MASK_PCODE_8822C 0x1f\n#define BIT_PCODE_8822C(x)                                                     \\\n\t(((x) & BIT_MASK_PCODE_8822C) << BIT_SHIFT_PCODE_8822C)\n#define BITS_PCODE_8822C (BIT_MASK_PCODE_8822C << BIT_SHIFT_PCODE_8822C)\n#define BIT_CLEAR_PCODE_8822C(x) ((x) & (~BITS_PCODE_8822C))\n#define BIT_GET_PCODE_8822C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_PCODE_8822C) & BIT_MASK_PCODE_8822C)\n#define BIT_SET_PCODE_8822C(x, v)                                              \\\n\t(BIT_CLEAR_PCODE_8822C(x) | BIT_PCODE_8822C(v))\n\n#define BIT_SHIFT_NCODE_8822C 7\n#define BIT_MASK_NCODE_8822C 0xff\n#define BIT_NCODE_8822C(x)                                                     \\\n\t(((x) & BIT_MASK_NCODE_8822C) << BIT_SHIFT_NCODE_8822C)\n#define BITS_NCODE_8822C (BIT_MASK_NCODE_8822C << BIT_SHIFT_NCODE_8822C)\n#define BIT_CLEAR_NCODE_8822C(x) ((x) & (~BITS_NCODE_8822C))\n#define BIT_GET_NCODE_8822C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_NCODE_8822C) & BIT_MASK_NCODE_8822C)\n#define BIT_SET_NCODE_8822C(x, v)                                              \\\n\t(BIT_CLEAR_NCODE_8822C(x) | BIT_NCODE_8822C(v))\n\n#define BIT_REG_BEACON_8822C BIT(6)\n#define BIT_REG_MBIASE_8822C BIT(5)\n\n#define BIT_SHIFT_REG_FAST_SEL_8822C 3\n#define BIT_MASK_REG_FAST_SEL_8822C 0x3\n#define BIT_REG_FAST_SEL_8822C(x)                                              \\\n\t(((x) & BIT_MASK_REG_FAST_SEL_8822C) << BIT_SHIFT_REG_FAST_SEL_8822C)\n#define BITS_REG_FAST_SEL_8822C                                                \\\n\t(BIT_MASK_REG_FAST_SEL_8822C << BIT_SHIFT_REG_FAST_SEL_8822C)\n#define BIT_CLEAR_REG_FAST_SEL_8822C(x) ((x) & (~BITS_REG_FAST_SEL_8822C))\n#define BIT_GET_REG_FAST_SEL_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_REG_FAST_SEL_8822C) & BIT_MASK_REG_FAST_SEL_8822C)\n#define BIT_SET_REG_FAST_SEL_8822C(x, v)                                       \\\n\t(BIT_CLEAR_REG_FAST_SEL_8822C(x) | BIT_REG_FAST_SEL_8822C(v))\n\n#define BIT_REG_CK960M_EN_8822C BIT(2)\n#define BIT_REG_CK320M_EN_8822C BIT(1)\n#define BIT_REG_CK_5M_EN_8822C BIT(0)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_ANAPAR_XTAL_0_8822C */\n#define BIT_XTAL_SC_LPS_8822C BIT(31)\n\n#define BIT_SHIFT_XTAL_SC_INIT_8822C 24\n#define BIT_MASK_XTAL_SC_INIT_8822C 0x7f\n#define BIT_XTAL_SC_INIT_8822C(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_SC_INIT_8822C) << BIT_SHIFT_XTAL_SC_INIT_8822C)\n#define BITS_XTAL_SC_INIT_8822C                                                \\\n\t(BIT_MASK_XTAL_SC_INIT_8822C << BIT_SHIFT_XTAL_SC_INIT_8822C)\n#define BIT_CLEAR_XTAL_SC_INIT_8822C(x) ((x) & (~BITS_XTAL_SC_INIT_8822C))\n#define BIT_GET_XTAL_SC_INIT_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_SC_INIT_8822C) & BIT_MASK_XTAL_SC_INIT_8822C)\n#define BIT_SET_XTAL_SC_INIT_8822C(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_SC_INIT_8822C(x) | BIT_XTAL_SC_INIT_8822C(v))\n\n#define BIT_SHIFT_XTAL_SC_XO_8822C 17\n#define BIT_MASK_XTAL_SC_XO_8822C 0x7f\n#define BIT_XTAL_SC_XO_8822C(x)                                                \\\n\t(((x) & BIT_MASK_XTAL_SC_XO_8822C) << BIT_SHIFT_XTAL_SC_XO_8822C)\n#define BITS_XTAL_SC_XO_8822C                                                  \\\n\t(BIT_MASK_XTAL_SC_XO_8822C << BIT_SHIFT_XTAL_SC_XO_8822C)\n#define BIT_CLEAR_XTAL_SC_XO_8822C(x) ((x) & (~BITS_XTAL_SC_XO_8822C))\n#define BIT_GET_XTAL_SC_XO_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_XTAL_SC_XO_8822C) & BIT_MASK_XTAL_SC_XO_8822C)\n#define BIT_SET_XTAL_SC_XO_8822C(x, v)                                         \\\n\t(BIT_CLEAR_XTAL_SC_XO_8822C(x) | BIT_XTAL_SC_XO_8822C(v))\n\n#define BIT_SHIFT_XTAL_SC_XI_8822C 10\n#define BIT_MASK_XTAL_SC_XI_8822C 0x7f\n#define BIT_XTAL_SC_XI_8822C(x)                                                \\\n\t(((x) & BIT_MASK_XTAL_SC_XI_8822C) << BIT_SHIFT_XTAL_SC_XI_8822C)\n#define BITS_XTAL_SC_XI_8822C                                                  \\\n\t(BIT_MASK_XTAL_SC_XI_8822C << BIT_SHIFT_XTAL_SC_XI_8822C)\n#define BIT_CLEAR_XTAL_SC_XI_8822C(x) ((x) & (~BITS_XTAL_SC_XI_8822C))\n#define BIT_GET_XTAL_SC_XI_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_XTAL_SC_XI_8822C) & BIT_MASK_XTAL_SC_XI_8822C)\n#define BIT_SET_XTAL_SC_XI_8822C(x, v)                                         \\\n\t(BIT_CLEAR_XTAL_SC_XI_8822C(x) | BIT_XTAL_SC_XI_8822C(v))\n\n#define BIT_SHIFT_XTAL_GMN_V3_8822C 5\n#define BIT_MASK_XTAL_GMN_V3_8822C 0x1f\n#define BIT_XTAL_GMN_V3_8822C(x)                                               \\\n\t(((x) & BIT_MASK_XTAL_GMN_V3_8822C) << BIT_SHIFT_XTAL_GMN_V3_8822C)\n#define BITS_XTAL_GMN_V3_8822C                                                 \\\n\t(BIT_MASK_XTAL_GMN_V3_8822C << BIT_SHIFT_XTAL_GMN_V3_8822C)\n#define BIT_CLEAR_XTAL_GMN_V3_8822C(x) ((x) & (~BITS_XTAL_GMN_V3_8822C))\n#define BIT_GET_XTAL_GMN_V3_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_XTAL_GMN_V3_8822C) & BIT_MASK_XTAL_GMN_V3_8822C)\n#define BIT_SET_XTAL_GMN_V3_8822C(x, v)                                        \\\n\t(BIT_CLEAR_XTAL_GMN_V3_8822C(x) | BIT_XTAL_GMN_V3_8822C(v))\n\n#define BIT_SHIFT_XTAL_GMP_V3_8822C 0\n#define BIT_MASK_XTAL_GMP_V3_8822C 0x1f\n#define BIT_XTAL_GMP_V3_8822C(x)                                               \\\n\t(((x) & BIT_MASK_XTAL_GMP_V3_8822C) << BIT_SHIFT_XTAL_GMP_V3_8822C)\n#define BITS_XTAL_GMP_V3_8822C                                                 \\\n\t(BIT_MASK_XTAL_GMP_V3_8822C << BIT_SHIFT_XTAL_GMP_V3_8822C)\n#define BIT_CLEAR_XTAL_GMP_V3_8822C(x) ((x) & (~BITS_XTAL_GMP_V3_8822C))\n#define BIT_GET_XTAL_GMP_V3_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_XTAL_GMP_V3_8822C) & BIT_MASK_XTAL_GMP_V3_8822C)\n#define BIT_SET_XTAL_GMP_V3_8822C(x, v)                                        \\\n\t(BIT_CLEAR_XTAL_GMP_V3_8822C(x) | BIT_XTAL_GMP_V3_8822C(v))\n\n/* 2 REG_ANAPAR_XTAL_1_8822C */\n#define BIT_XTAL_SEL_TOK_V1_8822C BIT(31)\n#define BIT_XTAL_DELAY_DIGI_V2_8822C BIT(30)\n#define BIT_XTAL_DELAY_USB_V2_8822C BIT(29)\n#define BIT_XTAL_DELAY_AFE_V2_8822C BIT(28)\n\n#define BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C 26\n#define BIT_MASK_XTAL_DRV_DIGI_V2_8822C 0x3\n#define BIT_XTAL_DRV_DIGI_V2_8822C(x)                                          \\\n\t(((x) & BIT_MASK_XTAL_DRV_DIGI_V2_8822C)                               \\\n\t << BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C)\n#define BITS_XTAL_DRV_DIGI_V2_8822C                                            \\\n\t(BIT_MASK_XTAL_DRV_DIGI_V2_8822C << BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C)\n#define BIT_CLEAR_XTAL_DRV_DIGI_V2_8822C(x)                                    \\\n\t((x) & (~BITS_XTAL_DRV_DIGI_V2_8822C))\n#define BIT_GET_XTAL_DRV_DIGI_V2_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C) &                           \\\n\t BIT_MASK_XTAL_DRV_DIGI_V2_8822C)\n#define BIT_SET_XTAL_DRV_DIGI_V2_8822C(x, v)                                   \\\n\t(BIT_CLEAR_XTAL_DRV_DIGI_V2_8822C(x) | BIT_XTAL_DRV_DIGI_V2_8822C(v))\n\n#define BIT_EN_XTAL_DRV_LPS_8822C BIT(25)\n#define BIT_EN_XTAL_DRV_DIGI_V2_8822C BIT(24)\n\n#define BIT_SHIFT_XTAL_DRV_USB_8822C 22\n#define BIT_MASK_XTAL_DRV_USB_8822C 0x3\n#define BIT_XTAL_DRV_USB_8822C(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_DRV_USB_8822C) << BIT_SHIFT_XTAL_DRV_USB_8822C)\n#define BITS_XTAL_DRV_USB_8822C                                                \\\n\t(BIT_MASK_XTAL_DRV_USB_8822C << BIT_SHIFT_XTAL_DRV_USB_8822C)\n#define BIT_CLEAR_XTAL_DRV_USB_8822C(x) ((x) & (~BITS_XTAL_DRV_USB_8822C))\n#define BIT_GET_XTAL_DRV_USB_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_USB_8822C) & BIT_MASK_XTAL_DRV_USB_8822C)\n#define BIT_SET_XTAL_DRV_USB_8822C(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_DRV_USB_8822C(x) | BIT_XTAL_DRV_USB_8822C(v))\n\n#define BIT_EN_XTAL_DRV_USB_8822C BIT(21)\n\n#define BIT_SHIFT_XTAL_DRV_AFE_V2_8822C 19\n#define BIT_MASK_XTAL_DRV_AFE_V2_8822C 0x3\n#define BIT_XTAL_DRV_AFE_V2_8822C(x)                                           \\\n\t(((x) & BIT_MASK_XTAL_DRV_AFE_V2_8822C)                                \\\n\t << BIT_SHIFT_XTAL_DRV_AFE_V2_8822C)\n#define BITS_XTAL_DRV_AFE_V2_8822C                                             \\\n\t(BIT_MASK_XTAL_DRV_AFE_V2_8822C << BIT_SHIFT_XTAL_DRV_AFE_V2_8822C)\n#define BIT_CLEAR_XTAL_DRV_AFE_V2_8822C(x) ((x) & (~BITS_XTAL_DRV_AFE_V2_8822C))\n#define BIT_GET_XTAL_DRV_AFE_V2_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_AFE_V2_8822C) &                            \\\n\t BIT_MASK_XTAL_DRV_AFE_V2_8822C)\n#define BIT_SET_XTAL_DRV_AFE_V2_8822C(x, v)                                    \\\n\t(BIT_CLEAR_XTAL_DRV_AFE_V2_8822C(x) | BIT_XTAL_DRV_AFE_V2_8822C(v))\n\n#define BIT_EN_XTAL_DRV_AFE_8822C BIT(18)\n\n#define BIT_SHIFT_XTAL_DRV_RF2_V2_8822C 16\n#define BIT_MASK_XTAL_DRV_RF2_V2_8822C 0x3\n#define BIT_XTAL_DRV_RF2_V2_8822C(x)                                           \\\n\t(((x) & BIT_MASK_XTAL_DRV_RF2_V2_8822C)                                \\\n\t << BIT_SHIFT_XTAL_DRV_RF2_V2_8822C)\n#define BITS_XTAL_DRV_RF2_V2_8822C                                             \\\n\t(BIT_MASK_XTAL_DRV_RF2_V2_8822C << BIT_SHIFT_XTAL_DRV_RF2_V2_8822C)\n#define BIT_CLEAR_XTAL_DRV_RF2_V2_8822C(x) ((x) & (~BITS_XTAL_DRV_RF2_V2_8822C))\n#define BIT_GET_XTAL_DRV_RF2_V2_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_RF2_V2_8822C) &                            \\\n\t BIT_MASK_XTAL_DRV_RF2_V2_8822C)\n#define BIT_SET_XTAL_DRV_RF2_V2_8822C(x, v)                                    \\\n\t(BIT_CLEAR_XTAL_DRV_RF2_V2_8822C(x) | BIT_XTAL_DRV_RF2_V2_8822C(v))\n\n#define BIT_EN_XTAL_DRV_RF2_8822C BIT(15)\n\n#define BIT_SHIFT_XTAL_DRV_RF1_8822C 13\n#define BIT_MASK_XTAL_DRV_RF1_8822C 0x3\n#define BIT_XTAL_DRV_RF1_8822C(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_DRV_RF1_8822C) << BIT_SHIFT_XTAL_DRV_RF1_8822C)\n#define BITS_XTAL_DRV_RF1_8822C                                                \\\n\t(BIT_MASK_XTAL_DRV_RF1_8822C << BIT_SHIFT_XTAL_DRV_RF1_8822C)\n#define BIT_CLEAR_XTAL_DRV_RF1_8822C(x) ((x) & (~BITS_XTAL_DRV_RF1_8822C))\n#define BIT_GET_XTAL_DRV_RF1_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_DRV_RF1_8822C) & BIT_MASK_XTAL_DRV_RF1_8822C)\n#define BIT_SET_XTAL_DRV_RF1_8822C(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_DRV_RF1_8822C(x) | BIT_XTAL_DRV_RF1_8822C(v))\n\n#define BIT_EN_XTAL_DRV_RF1_8822C BIT(12)\n#define BIT_XTAL_DRV_RF_LATCH_V4_8822C BIT(11)\n#define BIT_XTAL_GM_SEP_V3_8822C BIT(10)\n#define BIT_XQSEL_RF_AWAKE_V3_8822C BIT(9)\n#define BIT_XQSEL_RF_INITIAL_V3_8822C BIT(8)\n#define BIT_XQSEL_V2_8822C BIT(7)\n#define BIT_GATED_XTAL_OK0_V2_8822C BIT(6)\n\n#define BIT_SHIFT_XTAL_SC_LPS_V2_8822C 0\n#define BIT_MASK_XTAL_SC_LPS_V2_8822C 0x3f\n#define BIT_XTAL_SC_LPS_V2_8822C(x)                                            \\\n\t(((x) & BIT_MASK_XTAL_SC_LPS_V2_8822C)                                 \\\n\t << BIT_SHIFT_XTAL_SC_LPS_V2_8822C)\n#define BITS_XTAL_SC_LPS_V2_8822C                                              \\\n\t(BIT_MASK_XTAL_SC_LPS_V2_8822C << BIT_SHIFT_XTAL_SC_LPS_V2_8822C)\n#define BIT_CLEAR_XTAL_SC_LPS_V2_8822C(x) ((x) & (~BITS_XTAL_SC_LPS_V2_8822C))\n#define BIT_GET_XTAL_SC_LPS_V2_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_XTAL_SC_LPS_V2_8822C) &                             \\\n\t BIT_MASK_XTAL_SC_LPS_V2_8822C)\n#define BIT_SET_XTAL_SC_LPS_V2_8822C(x, v)                                     \\\n\t(BIT_CLEAR_XTAL_SC_LPS_V2_8822C(x) | BIT_XTAL_SC_LPS_V2_8822C(v))\n\n/* 2 REG_ANAPAR_XTAL_2_8822C */\n#define BIT_XTAL_AAC_CAP_8822C BIT(31)\n\n#define BIT_SHIFT_XTAL_PDSW_8822C 29\n#define BIT_MASK_XTAL_PDSW_8822C 0x3\n#define BIT_XTAL_PDSW_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_XTAL_PDSW_8822C) << BIT_SHIFT_XTAL_PDSW_8822C)\n#define BITS_XTAL_PDSW_8822C                                                   \\\n\t(BIT_MASK_XTAL_PDSW_8822C << BIT_SHIFT_XTAL_PDSW_8822C)\n#define BIT_CLEAR_XTAL_PDSW_8822C(x) ((x) & (~BITS_XTAL_PDSW_8822C))\n#define BIT_GET_XTAL_PDSW_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_XTAL_PDSW_8822C) & BIT_MASK_XTAL_PDSW_8822C)\n#define BIT_SET_XTAL_PDSW_8822C(x, v)                                          \\\n\t(BIT_CLEAR_XTAL_PDSW_8822C(x) | BIT_XTAL_PDSW_8822C(v))\n\n#define BIT_SHIFT_XTAL_LPS_BUF_VB_8822C 27\n#define BIT_MASK_XTAL_LPS_BUF_VB_8822C 0x3\n#define BIT_XTAL_LPS_BUF_VB_8822C(x)                                           \\\n\t(((x) & BIT_MASK_XTAL_LPS_BUF_VB_8822C)                                \\\n\t << BIT_SHIFT_XTAL_LPS_BUF_VB_8822C)\n#define BITS_XTAL_LPS_BUF_VB_8822C                                             \\\n\t(BIT_MASK_XTAL_LPS_BUF_VB_8822C << BIT_SHIFT_XTAL_LPS_BUF_VB_8822C)\n#define BIT_CLEAR_XTAL_LPS_BUF_VB_8822C(x) ((x) & (~BITS_XTAL_LPS_BUF_VB_8822C))\n#define BIT_GET_XTAL_LPS_BUF_VB_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_XTAL_LPS_BUF_VB_8822C) &                            \\\n\t BIT_MASK_XTAL_LPS_BUF_VB_8822C)\n#define BIT_SET_XTAL_LPS_BUF_VB_8822C(x, v)                                    \\\n\t(BIT_CLEAR_XTAL_LPS_BUF_VB_8822C(x) | BIT_XTAL_LPS_BUF_VB_8822C(v))\n\n#define BIT_XTAL_PDCK_MANU_8822C BIT(26)\n#define BIT_XTAL_PDCK_OK_MANU_8822C BIT(25)\n\n#define BIT_SHIFT_XTAL_VREF_SEL_8822C 20\n#define BIT_MASK_XTAL_VREF_SEL_8822C 0x1f\n#define BIT_XTAL_VREF_SEL_8822C(x)                                             \\\n\t(((x) & BIT_MASK_XTAL_VREF_SEL_8822C) << BIT_SHIFT_XTAL_VREF_SEL_8822C)\n#define BITS_XTAL_VREF_SEL_8822C                                               \\\n\t(BIT_MASK_XTAL_VREF_SEL_8822C << BIT_SHIFT_XTAL_VREF_SEL_8822C)\n#define BIT_CLEAR_XTAL_VREF_SEL_8822C(x) ((x) & (~BITS_XTAL_VREF_SEL_8822C))\n#define BIT_GET_XTAL_VREF_SEL_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_XTAL_VREF_SEL_8822C) & BIT_MASK_XTAL_VREF_SEL_8822C)\n#define BIT_SET_XTAL_VREF_SEL_8822C(x, v)                                      \\\n\t(BIT_CLEAR_XTAL_VREF_SEL_8822C(x) | BIT_XTAL_VREF_SEL_8822C(v))\n\n#define BIT_EN_XTAL_PDCK_VREF_8822C BIT(19)\n#define BIT_XTAL_SEL_PWR_V1_8822C BIT(18)\n#define BIT_XTAL_LPS_DIVISOR_8822C BIT(17)\n#define BIT_XTAL_CKDIGI_SEL_8822C BIT(16)\n#define BIT_EN_XTAL_LPS_CLK_8822C BIT(15)\n#define BIT_EN_XTAL_SCHMITT_8822C BIT(14)\n#define BIT_XTAL_PK_SEL_OFFSET_8822C BIT(13)\n\n#define BIT_SHIFT_XTAL_MANU_PK_SEL_8822C 11\n#define BIT_MASK_XTAL_MANU_PK_SEL_8822C 0x3\n#define BIT_XTAL_MANU_PK_SEL_8822C(x)                                          \\\n\t(((x) & BIT_MASK_XTAL_MANU_PK_SEL_8822C)                               \\\n\t << BIT_SHIFT_XTAL_MANU_PK_SEL_8822C)\n#define BITS_XTAL_MANU_PK_SEL_8822C                                            \\\n\t(BIT_MASK_XTAL_MANU_PK_SEL_8822C << BIT_SHIFT_XTAL_MANU_PK_SEL_8822C)\n#define BIT_CLEAR_XTAL_MANU_PK_SEL_8822C(x)                                    \\\n\t((x) & (~BITS_XTAL_MANU_PK_SEL_8822C))\n#define BIT_GET_XTAL_MANU_PK_SEL_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_XTAL_MANU_PK_SEL_8822C) &                           \\\n\t BIT_MASK_XTAL_MANU_PK_SEL_8822C)\n#define BIT_SET_XTAL_MANU_PK_SEL_8822C(x, v)                                   \\\n\t(BIT_CLEAR_XTAL_MANU_PK_SEL_8822C(x) | BIT_XTAL_MANU_PK_SEL_8822C(v))\n\n#define BIT_XTAL_AACK_PK_MANU_8822C BIT(10)\n#define BIT_EN_XTAL_AAC_PKDET_V1_8822C BIT(9)\n#define BIT_EN_XTAL_AAC_GM_V1_8822C BIT(8)\n#define BIT_XTAL_LDO_OPVB_SEL_8822C BIT(7)\n#define BIT_XTAL_LDO_NC_8822C BIT(6)\n\n#define BIT_SHIFT_XTAL_LDO_VREF_V2_8822C 3\n#define BIT_MASK_XTAL_LDO_VREF_V2_8822C 0x7\n#define BIT_XTAL_LDO_VREF_V2_8822C(x)                                          \\\n\t(((x) & BIT_MASK_XTAL_LDO_VREF_V2_8822C)                               \\\n\t << BIT_SHIFT_XTAL_LDO_VREF_V2_8822C)\n#define BITS_XTAL_LDO_VREF_V2_8822C                                            \\\n\t(BIT_MASK_XTAL_LDO_VREF_V2_8822C << BIT_SHIFT_XTAL_LDO_VREF_V2_8822C)\n#define BIT_CLEAR_XTAL_LDO_VREF_V2_8822C(x)                                    \\\n\t((x) & (~BITS_XTAL_LDO_VREF_V2_8822C))\n#define BIT_GET_XTAL_LDO_VREF_V2_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_XTAL_LDO_VREF_V2_8822C) &                           \\\n\t BIT_MASK_XTAL_LDO_VREF_V2_8822C)\n#define BIT_SET_XTAL_LDO_VREF_V2_8822C(x, v)                                   \\\n\t(BIT_CLEAR_XTAL_LDO_VREF_V2_8822C(x) | BIT_XTAL_LDO_VREF_V2_8822C(v))\n\n#define BIT_XTAL_LPMODE_V1_8822C BIT(2)\n\n#define BIT_SHIFT_XTAL_SEL_TOK_V3_8822C 0\n#define BIT_MASK_XTAL_SEL_TOK_V3_8822C 0x3\n#define BIT_XTAL_SEL_TOK_V3_8822C(x)                                           \\\n\t(((x) & BIT_MASK_XTAL_SEL_TOK_V3_8822C)                                \\\n\t << BIT_SHIFT_XTAL_SEL_TOK_V3_8822C)\n#define BITS_XTAL_SEL_TOK_V3_8822C                                             \\\n\t(BIT_MASK_XTAL_SEL_TOK_V3_8822C << BIT_SHIFT_XTAL_SEL_TOK_V3_8822C)\n#define BIT_CLEAR_XTAL_SEL_TOK_V3_8822C(x) ((x) & (~BITS_XTAL_SEL_TOK_V3_8822C))\n#define BIT_GET_XTAL_SEL_TOK_V3_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_XTAL_SEL_TOK_V3_8822C) &                            \\\n\t BIT_MASK_XTAL_SEL_TOK_V3_8822C)\n#define BIT_SET_XTAL_SEL_TOK_V3_8822C(x, v)                                    \\\n\t(BIT_CLEAR_XTAL_SEL_TOK_V3_8822C(x) | BIT_XTAL_SEL_TOK_V3_8822C(v))\n\n/* 2 REG_ANAPAR_XTAL_3_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_XTAL_DUMMY_V1_8822C 7\n#define BIT_MASK_XTAL_DUMMY_V1_8822C 0x3f\n#define BIT_XTAL_DUMMY_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_XTAL_DUMMY_V1_8822C) << BIT_SHIFT_XTAL_DUMMY_V1_8822C)\n#define BITS_XTAL_DUMMY_V1_8822C                                               \\\n\t(BIT_MASK_XTAL_DUMMY_V1_8822C << BIT_SHIFT_XTAL_DUMMY_V1_8822C)\n#define BIT_CLEAR_XTAL_DUMMY_V1_8822C(x) ((x) & (~BITS_XTAL_DUMMY_V1_8822C))\n#define BIT_GET_XTAL_DUMMY_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_XTAL_DUMMY_V1_8822C) & BIT_MASK_XTAL_DUMMY_V1_8822C)\n#define BIT_SET_XTAL_DUMMY_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_XTAL_DUMMY_V1_8822C(x) | BIT_XTAL_DUMMY_V1_8822C(v))\n\n#define BIT_XTAL_EN_LNBUF_8822C BIT(6)\n#define BIT_XTAL__AAC_TIE_MID_8822C BIT(5)\n\n#define BIT_SHIFT_XTAL_AAC_OPCUR_8822C 3\n#define BIT_MASK_XTAL_AAC_OPCUR_8822C 0x3\n#define BIT_XTAL_AAC_OPCUR_8822C(x)                                            \\\n\t(((x) & BIT_MASK_XTAL_AAC_OPCUR_8822C)                                 \\\n\t << BIT_SHIFT_XTAL_AAC_OPCUR_8822C)\n#define BITS_XTAL_AAC_OPCUR_8822C                                              \\\n\t(BIT_MASK_XTAL_AAC_OPCUR_8822C << BIT_SHIFT_XTAL_AAC_OPCUR_8822C)\n#define BIT_CLEAR_XTAL_AAC_OPCUR_8822C(x) ((x) & (~BITS_XTAL_AAC_OPCUR_8822C))\n#define BIT_GET_XTAL_AAC_OPCUR_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_XTAL_AAC_OPCUR_8822C) &                             \\\n\t BIT_MASK_XTAL_AAC_OPCUR_8822C)\n#define BIT_SET_XTAL_AAC_OPCUR_8822C(x, v)                                     \\\n\t(BIT_CLEAR_XTAL_AAC_OPCUR_8822C(x) | BIT_XTAL_AAC_OPCUR_8822C(v))\n\n#define BIT_SHIFT_XTAL_AAC_IOFFSET_8822C 1\n#define BIT_MASK_XTAL_AAC_IOFFSET_8822C 0x3\n#define BIT_XTAL_AAC_IOFFSET_8822C(x)                                          \\\n\t(((x) & BIT_MASK_XTAL_AAC_IOFFSET_8822C)                               \\\n\t << BIT_SHIFT_XTAL_AAC_IOFFSET_8822C)\n#define BITS_XTAL_AAC_IOFFSET_8822C                                            \\\n\t(BIT_MASK_XTAL_AAC_IOFFSET_8822C << BIT_SHIFT_XTAL_AAC_IOFFSET_8822C)\n#define BIT_CLEAR_XTAL_AAC_IOFFSET_8822C(x)                                    \\\n\t((x) & (~BITS_XTAL_AAC_IOFFSET_8822C))\n#define BIT_GET_XTAL_AAC_IOFFSET_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_XTAL_AAC_IOFFSET_8822C) &                           \\\n\t BIT_MASK_XTAL_AAC_IOFFSET_8822C)\n#define BIT_SET_XTAL_AAC_IOFFSET_8822C(x, v)                                   \\\n\t(BIT_CLEAR_XTAL_AAC_IOFFSET_8822C(x) | BIT_XTAL_AAC_IOFFSET_8822C(v))\n\n#define BIT_XTAL_AAC_CAP_V1_8822C BIT(0)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_ANAPAR_XTAL_AACK_0_8822C */\n#define BIT_XAAC_LPOW_8822C BIT(31)\n\n#define BIT_SHIFT_AAC_MODE_8822C 29\n#define BIT_MASK_AAC_MODE_8822C 0x3\n#define BIT_AAC_MODE_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_AAC_MODE_8822C) << BIT_SHIFT_AAC_MODE_8822C)\n#define BITS_AAC_MODE_8822C                                                    \\\n\t(BIT_MASK_AAC_MODE_8822C << BIT_SHIFT_AAC_MODE_8822C)\n#define BIT_CLEAR_AAC_MODE_8822C(x) ((x) & (~BITS_AAC_MODE_8822C))\n#define BIT_GET_AAC_MODE_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_AAC_MODE_8822C) & BIT_MASK_AAC_MODE_8822C)\n#define BIT_SET_AAC_MODE_8822C(x, v)                                           \\\n\t(BIT_CLEAR_AAC_MODE_8822C(x) | BIT_AAC_MODE_8822C(v))\n\n#define BIT_EN_XTAL_AAC_TRIG_8822C BIT(28)\n#define BIT_EN_XTAL_AAC_8822C BIT(27)\n#define BIT_EN_XTAL_AAC_DIGI_8822C BIT(26)\n\n#define BIT_SHIFT_GM_MANUAL_8822C 21\n#define BIT_MASK_GM_MANUAL_8822C 0x1f\n#define BIT_GM_MANUAL_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_GM_MANUAL_8822C) << BIT_SHIFT_GM_MANUAL_8822C)\n#define BITS_GM_MANUAL_8822C                                                   \\\n\t(BIT_MASK_GM_MANUAL_8822C << BIT_SHIFT_GM_MANUAL_8822C)\n#define BIT_CLEAR_GM_MANUAL_8822C(x) ((x) & (~BITS_GM_MANUAL_8822C))\n#define BIT_GET_GM_MANUAL_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_GM_MANUAL_8822C) & BIT_MASK_GM_MANUAL_8822C)\n#define BIT_SET_GM_MANUAL_8822C(x, v)                                          \\\n\t(BIT_CLEAR_GM_MANUAL_8822C(x) | BIT_GM_MANUAL_8822C(v))\n\n#define BIT_SHIFT_GM_STUP_8822C 16\n#define BIT_MASK_GM_STUP_8822C 0x1f\n#define BIT_GM_STUP_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_GM_STUP_8822C) << BIT_SHIFT_GM_STUP_8822C)\n#define BITS_GM_STUP_8822C (BIT_MASK_GM_STUP_8822C << BIT_SHIFT_GM_STUP_8822C)\n#define BIT_CLEAR_GM_STUP_8822C(x) ((x) & (~BITS_GM_STUP_8822C))\n#define BIT_GET_GM_STUP_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_GM_STUP_8822C) & BIT_MASK_GM_STUP_8822C)\n#define BIT_SET_GM_STUP_8822C(x, v)                                            \\\n\t(BIT_CLEAR_GM_STUP_8822C(x) | BIT_GM_STUP_8822C(v))\n\n#define BIT_SHIFT_XTAL_CK_SET_8822C 13\n#define BIT_MASK_XTAL_CK_SET_8822C 0x7\n#define BIT_XTAL_CK_SET_8822C(x)                                               \\\n\t(((x) & BIT_MASK_XTAL_CK_SET_8822C) << BIT_SHIFT_XTAL_CK_SET_8822C)\n#define BITS_XTAL_CK_SET_8822C                                                 \\\n\t(BIT_MASK_XTAL_CK_SET_8822C << BIT_SHIFT_XTAL_CK_SET_8822C)\n#define BIT_CLEAR_XTAL_CK_SET_8822C(x) ((x) & (~BITS_XTAL_CK_SET_8822C))\n#define BIT_GET_XTAL_CK_SET_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_XTAL_CK_SET_8822C) & BIT_MASK_XTAL_CK_SET_8822C)\n#define BIT_SET_XTAL_CK_SET_8822C(x, v)                                        \\\n\t(BIT_CLEAR_XTAL_CK_SET_8822C(x) | BIT_XTAL_CK_SET_8822C(v))\n\n#define BIT_SHIFT_GM_INIT_8822C 8\n#define BIT_MASK_GM_INIT_8822C 0x1f\n#define BIT_GM_INIT_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_GM_INIT_8822C) << BIT_SHIFT_GM_INIT_8822C)\n#define BITS_GM_INIT_8822C (BIT_MASK_GM_INIT_8822C << BIT_SHIFT_GM_INIT_8822C)\n#define BIT_CLEAR_GM_INIT_8822C(x) ((x) & (~BITS_GM_INIT_8822C))\n#define BIT_GET_GM_INIT_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_GM_INIT_8822C) & BIT_MASK_GM_INIT_8822C)\n#define BIT_SET_GM_INIT_8822C(x, v)                                            \\\n\t(BIT_CLEAR_GM_INIT_8822C(x) | BIT_GM_INIT_8822C(v))\n\n#define BIT_GM_STEP_8822C BIT(7)\n\n#define BIT_SHIFT_XAAC_GM_OFFSET_8822C 2\n#define BIT_MASK_XAAC_GM_OFFSET_8822C 0x1f\n#define BIT_XAAC_GM_OFFSET_8822C(x)                                            \\\n\t(((x) & BIT_MASK_XAAC_GM_OFFSET_8822C)                                 \\\n\t << BIT_SHIFT_XAAC_GM_OFFSET_8822C)\n#define BITS_XAAC_GM_OFFSET_8822C                                              \\\n\t(BIT_MASK_XAAC_GM_OFFSET_8822C << BIT_SHIFT_XAAC_GM_OFFSET_8822C)\n#define BIT_CLEAR_XAAC_GM_OFFSET_8822C(x) ((x) & (~BITS_XAAC_GM_OFFSET_8822C))\n#define BIT_GET_XAAC_GM_OFFSET_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_XAAC_GM_OFFSET_8822C) &                             \\\n\t BIT_MASK_XAAC_GM_OFFSET_8822C)\n#define BIT_SET_XAAC_GM_OFFSET_8822C(x, v)                                     \\\n\t(BIT_CLEAR_XAAC_GM_OFFSET_8822C(x) | BIT_XAAC_GM_OFFSET_8822C(v))\n\n#define BIT_OFFSET_PLUS_8822C BIT(1)\n#define BIT_RESET_N_8822C BIT(0)\n\n/* 2 REG_ANAPAR_XTAL_AACK_1_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_PK_END_AR_8822C 3\n#define BIT_MASK_PK_END_AR_8822C 0x3\n#define BIT_PK_END_AR_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_PK_END_AR_8822C) << BIT_SHIFT_PK_END_AR_8822C)\n#define BITS_PK_END_AR_8822C                                                   \\\n\t(BIT_MASK_PK_END_AR_8822C << BIT_SHIFT_PK_END_AR_8822C)\n#define BIT_CLEAR_PK_END_AR_8822C(x) ((x) & (~BITS_PK_END_AR_8822C))\n#define BIT_GET_PK_END_AR_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_PK_END_AR_8822C) & BIT_MASK_PK_END_AR_8822C)\n#define BIT_SET_PK_END_AR_8822C(x, v)                                          \\\n\t(BIT_CLEAR_PK_END_AR_8822C(x) | BIT_PK_END_AR_8822C(v))\n\n#define BIT_SHIFT_PK_START_AR_8822C 1\n#define BIT_MASK_PK_START_AR_8822C 0x3\n#define BIT_PK_START_AR_8822C(x)                                               \\\n\t(((x) & BIT_MASK_PK_START_AR_8822C) << BIT_SHIFT_PK_START_AR_8822C)\n#define BITS_PK_START_AR_8822C                                                 \\\n\t(BIT_MASK_PK_START_AR_8822C << BIT_SHIFT_PK_START_AR_8822C)\n#define BIT_CLEAR_PK_START_AR_8822C(x) ((x) & (~BITS_PK_START_AR_8822C))\n#define BIT_GET_PK_START_AR_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_PK_START_AR_8822C) & BIT_MASK_PK_START_AR_8822C)\n#define BIT_SET_PK_START_AR_8822C(x, v)                                        \\\n\t(BIT_CLEAR_PK_START_AR_8822C(x) | BIT_PK_START_AR_8822C(v))\n\n#define BIT_XAAC_LUT_MANUAL_EN_8822C BIT(0)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_ANAPAR_XTAL_MODE_DECODER_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_XTAL_LDO_LPS_8822C 21\n#define BIT_MASK_XTAL_LDO_LPS_8822C 0x7\n#define BIT_XTAL_LDO_LPS_8822C(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_LDO_LPS_8822C) << BIT_SHIFT_XTAL_LDO_LPS_8822C)\n#define BITS_XTAL_LDO_LPS_8822C                                                \\\n\t(BIT_MASK_XTAL_LDO_LPS_8822C << BIT_SHIFT_XTAL_LDO_LPS_8822C)\n#define BIT_CLEAR_XTAL_LDO_LPS_8822C(x) ((x) & (~BITS_XTAL_LDO_LPS_8822C))\n#define BIT_GET_XTAL_LDO_LPS_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_LDO_LPS_8822C) & BIT_MASK_XTAL_LDO_LPS_8822C)\n#define BIT_SET_XTAL_LDO_LPS_8822C(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_LDO_LPS_8822C(x) | BIT_XTAL_LDO_LPS_8822C(v))\n\n#define BIT_SHIFT_XTAL_WAIT_CYC_8822C 15\n#define BIT_MASK_XTAL_WAIT_CYC_8822C 0x3f\n#define BIT_XTAL_WAIT_CYC_8822C(x)                                             \\\n\t(((x) & BIT_MASK_XTAL_WAIT_CYC_8822C) << BIT_SHIFT_XTAL_WAIT_CYC_8822C)\n#define BITS_XTAL_WAIT_CYC_8822C                                               \\\n\t(BIT_MASK_XTAL_WAIT_CYC_8822C << BIT_SHIFT_XTAL_WAIT_CYC_8822C)\n#define BIT_CLEAR_XTAL_WAIT_CYC_8822C(x) ((x) & (~BITS_XTAL_WAIT_CYC_8822C))\n#define BIT_GET_XTAL_WAIT_CYC_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_XTAL_WAIT_CYC_8822C) & BIT_MASK_XTAL_WAIT_CYC_8822C)\n#define BIT_SET_XTAL_WAIT_CYC_8822C(x, v)                                      \\\n\t(BIT_CLEAR_XTAL_WAIT_CYC_8822C(x) | BIT_XTAL_WAIT_CYC_8822C(v))\n\n#define BIT_SHIFT_XTAL_LDO_OK_8822C 12\n#define BIT_MASK_XTAL_LDO_OK_8822C 0x7\n#define BIT_XTAL_LDO_OK_8822C(x)                                               \\\n\t(((x) & BIT_MASK_XTAL_LDO_OK_8822C) << BIT_SHIFT_XTAL_LDO_OK_8822C)\n#define BITS_XTAL_LDO_OK_8822C                                                 \\\n\t(BIT_MASK_XTAL_LDO_OK_8822C << BIT_SHIFT_XTAL_LDO_OK_8822C)\n#define BIT_CLEAR_XTAL_LDO_OK_8822C(x) ((x) & (~BITS_XTAL_LDO_OK_8822C))\n#define BIT_GET_XTAL_LDO_OK_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_XTAL_LDO_OK_8822C) & BIT_MASK_XTAL_LDO_OK_8822C)\n#define BIT_SET_XTAL_LDO_OK_8822C(x, v)                                        \\\n\t(BIT_CLEAR_XTAL_LDO_OK_8822C(x) | BIT_XTAL_LDO_OK_8822C(v))\n\n#define BIT_XTAL_MD_LPOW_8822C BIT(11)\n\n#define BIT_SHIFT_XTAL_OV_RATIO_8822C 9\n#define BIT_MASK_XTAL_OV_RATIO_8822C 0x3\n#define BIT_XTAL_OV_RATIO_8822C(x)                                             \\\n\t(((x) & BIT_MASK_XTAL_OV_RATIO_8822C) << BIT_SHIFT_XTAL_OV_RATIO_8822C)\n#define BITS_XTAL_OV_RATIO_8822C                                               \\\n\t(BIT_MASK_XTAL_OV_RATIO_8822C << BIT_SHIFT_XTAL_OV_RATIO_8822C)\n#define BIT_CLEAR_XTAL_OV_RATIO_8822C(x) ((x) & (~BITS_XTAL_OV_RATIO_8822C))\n#define BIT_GET_XTAL_OV_RATIO_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_XTAL_OV_RATIO_8822C) & BIT_MASK_XTAL_OV_RATIO_8822C)\n#define BIT_SET_XTAL_OV_RATIO_8822C(x, v)                                      \\\n\t(BIT_CLEAR_XTAL_OV_RATIO_8822C(x) | BIT_XTAL_OV_RATIO_8822C(v))\n\n#define BIT_SHIFT_XTAL_OV_UNIT_8822C 6\n#define BIT_MASK_XTAL_OV_UNIT_8822C 0x7\n#define BIT_XTAL_OV_UNIT_8822C(x)                                              \\\n\t(((x) & BIT_MASK_XTAL_OV_UNIT_8822C) << BIT_SHIFT_XTAL_OV_UNIT_8822C)\n#define BITS_XTAL_OV_UNIT_8822C                                                \\\n\t(BIT_MASK_XTAL_OV_UNIT_8822C << BIT_SHIFT_XTAL_OV_UNIT_8822C)\n#define BIT_CLEAR_XTAL_OV_UNIT_8822C(x) ((x) & (~BITS_XTAL_OV_UNIT_8822C))\n#define BIT_GET_XTAL_OV_UNIT_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_XTAL_OV_UNIT_8822C) & BIT_MASK_XTAL_OV_UNIT_8822C)\n#define BIT_SET_XTAL_OV_UNIT_8822C(x, v)                                       \\\n\t(BIT_CLEAR_XTAL_OV_UNIT_8822C(x) | BIT_XTAL_OV_UNIT_8822C(v))\n\n#define BIT_SHIFT_XTAL_MODE_MANUAL_8822C 4\n#define BIT_MASK_XTAL_MODE_MANUAL_8822C 0x3\n#define BIT_XTAL_MODE_MANUAL_8822C(x)                                          \\\n\t(((x) & BIT_MASK_XTAL_MODE_MANUAL_8822C)                               \\\n\t << BIT_SHIFT_XTAL_MODE_MANUAL_8822C)\n#define BITS_XTAL_MODE_MANUAL_8822C                                            \\\n\t(BIT_MASK_XTAL_MODE_MANUAL_8822C << BIT_SHIFT_XTAL_MODE_MANUAL_8822C)\n#define BIT_CLEAR_XTAL_MODE_MANUAL_8822C(x)                                    \\\n\t((x) & (~BITS_XTAL_MODE_MANUAL_8822C))\n#define BIT_GET_XTAL_MODE_MANUAL_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_XTAL_MODE_MANUAL_8822C) &                           \\\n\t BIT_MASK_XTAL_MODE_MANUAL_8822C)\n#define BIT_SET_XTAL_MODE_MANUAL_8822C(x, v)                                   \\\n\t(BIT_CLEAR_XTAL_MODE_MANUAL_8822C(x) | BIT_XTAL_MODE_MANUAL_8822C(v))\n\n#define BIT_XTAL_MANU_SEL_8822C BIT(3)\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_XTAL_MODE_8822C BIT(1)\n#define BIT_RESET_N_DECODER_8822C BIT(0)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_SYS_CFG5_8822C */\n#define BIT_LPS_STATUS_8822C BIT(3)\n#define BIT_HCI_TXDMA_BUSY_8822C BIT(2)\n#define BIT_HCI_TXDMA_ALLOW_8822C BIT(1)\n#define BIT_FW_CTRL_HCI_TXDMA_EN_8822C BIT(0)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_CPU_DMEM_CON_8822C */\n#define BIT_WDT_AUTO_MODE_8822C BIT(22)\n#define BIT_WDT_PLATFORM_EN_8822C BIT(21)\n#define BIT_WDT_CPU_EN_8822C BIT(20)\n#define BIT_WDT_OPT_IOWRAPPER_8822C BIT(19)\n#define BIT_ANA_PORT_IDLE_8822C BIT(18)\n#define BIT_MAC_PORT_IDLE_8822C BIT(17)\n#define BIT_WL_PLATFORM_RST_8822C BIT(16)\n#define BIT_WL_SECURITY_CLK_8822C BIT(15)\n#define BIT_DDMA_EN_8822C BIT(8)\n\n#define BIT_SHIFT_CPU_DMEM_CON_8822C 0\n#define BIT_MASK_CPU_DMEM_CON_8822C 0xff\n#define BIT_CPU_DMEM_CON_8822C(x)                                              \\\n\t(((x) & BIT_MASK_CPU_DMEM_CON_8822C) << BIT_SHIFT_CPU_DMEM_CON_8822C)\n#define BITS_CPU_DMEM_CON_8822C                                                \\\n\t(BIT_MASK_CPU_DMEM_CON_8822C << BIT_SHIFT_CPU_DMEM_CON_8822C)\n#define BIT_CLEAR_CPU_DMEM_CON_8822C(x) ((x) & (~BITS_CPU_DMEM_CON_8822C))\n#define BIT_GET_CPU_DMEM_CON_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_CPU_DMEM_CON_8822C) & BIT_MASK_CPU_DMEM_CON_8822C)\n#define BIT_SET_CPU_DMEM_CON_8822C(x, v)                                       \\\n\t(BIT_CLEAR_CPU_DMEM_CON_8822C(x) | BIT_CPU_DMEM_CON_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_BOOT_REASON_8822C */\n\n#define BIT_SHIFT_BOOT_REASON_V1_8822C 0\n#define BIT_MASK_BOOT_REASON_V1_8822C 0x7\n#define BIT_BOOT_REASON_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_BOOT_REASON_V1_8822C)                                 \\\n\t << BIT_SHIFT_BOOT_REASON_V1_8822C)\n#define BITS_BOOT_REASON_V1_8822C                                              \\\n\t(BIT_MASK_BOOT_REASON_V1_8822C << BIT_SHIFT_BOOT_REASON_V1_8822C)\n#define BIT_CLEAR_BOOT_REASON_V1_8822C(x) ((x) & (~BITS_BOOT_REASON_V1_8822C))\n#define BIT_GET_BOOT_REASON_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_BOOT_REASON_V1_8822C) &                             \\\n\t BIT_MASK_BOOT_REASON_V1_8822C)\n#define BIT_SET_BOOT_REASON_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_BOOT_REASON_V1_8822C(x) | BIT_BOOT_REASON_V1_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_HIMR2_8822C */\n#define BIT_BCNDMAINT_P4_MSK_8822C BIT(31)\n#define BIT_BCNDMAINT_P3_MSK_8822C BIT(30)\n#define BIT_BCNDMAINT_P2_MSK_8822C BIT(29)\n#define BIT_BCNDMAINT_P1_MSK_8822C BIT(28)\n#define BIT_ATIMEND7_MSK_8822C BIT(22)\n#define BIT_ATIMEND6_MSK_8822C BIT(21)\n#define BIT_ATIMEND5_MSK_8822C BIT(20)\n#define BIT_ATIMEND4_MSK_8822C BIT(19)\n#define BIT_ATIMEND3_MSK_8822C BIT(18)\n#define BIT_ATIMEND2_MSK_8822C BIT(17)\n#define BIT_ATIMEND1_MSK_8822C BIT(16)\n#define BIT_TXBCN7OK_MSK_8822C BIT(14)\n#define BIT_TXBCN6OK_MSK_8822C BIT(13)\n#define BIT_TXBCN5OK_MSK_8822C BIT(12)\n#define BIT_TXBCN4OK_MSK_8822C BIT(11)\n#define BIT_TXBCN3OK_MSK_8822C BIT(10)\n#define BIT_TXBCN2OK_MSK_8822C BIT(9)\n#define BIT_TXBCN1OK_MSK_V1_8822C BIT(8)\n#define BIT_TXBCN7ERR_MSK_8822C BIT(6)\n#define BIT_TXBCN6ERR_MSK_8822C BIT(5)\n#define BIT_TXBCN5ERR_MSK_8822C BIT(4)\n#define BIT_TXBCN4ERR_MSK_8822C BIT(3)\n#define BIT_TXBCN3ERR_MSK_8822C BIT(2)\n#define BIT_TXBCN2ERR_MSK_8822C BIT(1)\n#define BIT_TXBCN1ERR_MSK_V1_8822C BIT(0)\n\n/* 2 REG_HISR2_8822C */\n#define BIT_BCNDMAINT_P4_8822C BIT(31)\n#define BIT_BCNDMAINT_P3_8822C BIT(30)\n#define BIT_BCNDMAINT_P2_8822C BIT(29)\n#define BIT_BCNDMAINT_P1_8822C BIT(28)\n#define BIT_ATIMEND7_8822C BIT(22)\n#define BIT_ATIMEND6_8822C BIT(21)\n#define BIT_ATIMEND5_8822C BIT(20)\n#define BIT_ATIMEND4_8822C BIT(19)\n#define BIT_ATIMEND3_8822C BIT(18)\n#define BIT_ATIMEND2_8822C BIT(17)\n#define BIT_ATIMEND1_8822C BIT(16)\n#define BIT_TXBCN7OK_8822C BIT(14)\n#define BIT_TXBCN6OK_8822C BIT(13)\n#define BIT_TXBCN5OK_8822C BIT(12)\n#define BIT_TXBCN4OK_8822C BIT(11)\n#define BIT_TXBCN3OK_8822C BIT(10)\n#define BIT_TXBCN2OK_8822C BIT(9)\n#define BIT_TXBCN1OK_8822C BIT(8)\n#define BIT_TXBCN7ERR_8822C BIT(6)\n#define BIT_TXBCN6ERR_8822C BIT(5)\n#define BIT_TXBCN5ERR_8822C BIT(4)\n#define BIT_TXBCN4ERR_8822C BIT(3)\n#define BIT_TXBCN3ERR_8822C BIT(2)\n#define BIT_TXBCN2ERR_8822C BIT(1)\n#define BIT_TXBCN1ERR_8822C BIT(0)\n\n/* 2 REG_HIMR3_8822C */\n#define BIT_WDT_PLATFORM_INT_MSK_8822C BIT(18)\n#define BIT_WDT_CPU_INT_MSK_8822C BIT(17)\n#define BIT_SETH2CDOK_MASK_8822C BIT(16)\n#define BIT_H2C_CMD_FULL_MASK_8822C BIT(15)\n#define BIT_PWR_INT_127_MASK_8822C BIT(14)\n#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8822C BIT(13)\n#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8822C BIT(12)\n#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8822C BIT(11)\n#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8822C BIT(10)\n#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8822C BIT(9)\n#define BIT_PWR_INT_127_MASK_V1_8822C BIT(8)\n#define BIT_PWR_INT_126TO96_MASK_8822C BIT(7)\n#define BIT_PWR_INT_95TO64_MASK_8822C BIT(6)\n#define BIT_PWR_INT_63TO32_MASK_8822C BIT(5)\n#define BIT_PWR_INT_31TO0_MASK_8822C BIT(4)\n#define BIT_RX_DMA_STUCK_MSK_8822C BIT(3)\n#define BIT_TX_DMA_STUCK_MSK_8822C BIT(2)\n#define BIT_DDMA0_LP_INT_MSK_8822C BIT(1)\n#define BIT_DDMA0_HP_INT_MSK_8822C BIT(0)\n\n/* 2 REG_HISR3_8822C */\n#define BIT_WDT_PLATFORM_INT_8822C BIT(18)\n#define BIT_WDT_CPU_INT_8822C BIT(17)\n#define BIT_SETH2CDOK_8822C BIT(16)\n#define BIT_H2C_CMD_FULL_8822C BIT(15)\n#define BIT_PWR_INT_127_8822C BIT(14)\n#define BIT_TXSHORTCUT_TXDESUPDATEOK_8822C BIT(13)\n#define BIT_TXSHORTCUT_BKUPDATEOK_8822C BIT(12)\n#define BIT_TXSHORTCUT_BEUPDATEOK_8822C BIT(11)\n#define BIT_TXSHORTCUT_VIUPDATEOK_8822C BIT(10)\n#define BIT_TXSHORTCUT_VOUPDATEOK_8822C BIT(9)\n#define BIT_PWR_INT_127_V1_8822C BIT(8)\n#define BIT_PWR_INT_126TO96_8822C BIT(7)\n#define BIT_PWR_INT_95TO64_8822C BIT(6)\n#define BIT_PWR_INT_63TO32_8822C BIT(5)\n#define BIT_PWR_INT_31TO0_8822C BIT(4)\n#define BIT_RX_DMA_STUCK_8822C BIT(3)\n#define BIT_TX_DMA_STUCK_8822C BIT(2)\n#define BIT_DDMA0_LP_INT_8822C BIT(1)\n#define BIT_DDMA0_HP_INT_8822C BIT(0)\n\n/* 2 REG_SW_MDIO_8822C */\n#define BIT_DIS_TIMEOUT_IO_8822C BIT(24)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_H2C_PKT_READADDR_8822C */\n\n#define BIT_SHIFT_H2C_PKT_READADDR_8822C 0\n#define BIT_MASK_H2C_PKT_READADDR_8822C 0x3ffff\n#define BIT_H2C_PKT_READADDR_8822C(x)                                          \\\n\t(((x) & BIT_MASK_H2C_PKT_READADDR_8822C)                               \\\n\t << BIT_SHIFT_H2C_PKT_READADDR_8822C)\n#define BITS_H2C_PKT_READADDR_8822C                                            \\\n\t(BIT_MASK_H2C_PKT_READADDR_8822C << BIT_SHIFT_H2C_PKT_READADDR_8822C)\n#define BIT_CLEAR_H2C_PKT_READADDR_8822C(x)                                    \\\n\t((x) & (~BITS_H2C_PKT_READADDR_8822C))\n#define BIT_GET_H2C_PKT_READADDR_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_H2C_PKT_READADDR_8822C) &                           \\\n\t BIT_MASK_H2C_PKT_READADDR_8822C)\n#define BIT_SET_H2C_PKT_READADDR_8822C(x, v)                                   \\\n\t(BIT_CLEAR_H2C_PKT_READADDR_8822C(x) | BIT_H2C_PKT_READADDR_8822C(v))\n\n/* 2 REG_H2C_PKT_WRITEADDR_8822C */\n\n#define BIT_SHIFT_H2C_PKT_WRITEADDR_8822C 0\n#define BIT_MASK_H2C_PKT_WRITEADDR_8822C 0x3ffff\n#define BIT_H2C_PKT_WRITEADDR_8822C(x)                                         \\\n\t(((x) & BIT_MASK_H2C_PKT_WRITEADDR_8822C)                              \\\n\t << BIT_SHIFT_H2C_PKT_WRITEADDR_8822C)\n#define BITS_H2C_PKT_WRITEADDR_8822C                                           \\\n\t(BIT_MASK_H2C_PKT_WRITEADDR_8822C << BIT_SHIFT_H2C_PKT_WRITEADDR_8822C)\n#define BIT_CLEAR_H2C_PKT_WRITEADDR_8822C(x)                                   \\\n\t((x) & (~BITS_H2C_PKT_WRITEADDR_8822C))\n#define BIT_GET_H2C_PKT_WRITEADDR_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8822C) &                          \\\n\t BIT_MASK_H2C_PKT_WRITEADDR_8822C)\n#define BIT_SET_H2C_PKT_WRITEADDR_8822C(x, v)                                  \\\n\t(BIT_CLEAR_H2C_PKT_WRITEADDR_8822C(x) | BIT_H2C_PKT_WRITEADDR_8822C(v))\n\n/* 2 REG_MEM_PWR_CRTL_8822C */\n#define BIT_MEM_BB_SD_8822C BIT(17)\n#define BIT_MEM_BB_DS_8822C BIT(16)\n#define BIT_MEM_BT_DS_8822C BIT(10)\n#define BIT_MEM_SDIO_LS_8822C BIT(9)\n#define BIT_MEM_SDIO_DS_8822C BIT(8)\n#define BIT_MEM_USB_LS_8822C BIT(7)\n#define BIT_MEM_USB_DS_8822C BIT(6)\n#define BIT_MEM_PCI_LS_8822C BIT(5)\n#define BIT_MEM_PCI_DS_8822C BIT(4)\n#define BIT_MEM_WLMAC_LS_8822C BIT(3)\n#define BIT_MEM_WLMAC_DS_8822C BIT(2)\n#define BIT_MEM_WLMCU_LS_8822C BIT(1)\n#define BIT_MEM_WLMCU_DS_8822C BIT(0)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_FW_DBG6_8822C */\n\n#define BIT_SHIFT_FW_DBG6_8822C 0\n#define BIT_MASK_FW_DBG6_8822C 0xffffffffL\n#define BIT_FW_DBG6_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG6_8822C) << BIT_SHIFT_FW_DBG6_8822C)\n#define BITS_FW_DBG6_8822C (BIT_MASK_FW_DBG6_8822C << BIT_SHIFT_FW_DBG6_8822C)\n#define BIT_CLEAR_FW_DBG6_8822C(x) ((x) & (~BITS_FW_DBG6_8822C))\n#define BIT_GET_FW_DBG6_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG6_8822C) & BIT_MASK_FW_DBG6_8822C)\n#define BIT_SET_FW_DBG6_8822C(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG6_8822C(x) | BIT_FW_DBG6_8822C(v))\n\n/* 2 REG_FW_DBG7_8822C */\n\n#define BIT_SHIFT_FW_DBG7_8822C 0\n#define BIT_MASK_FW_DBG7_8822C 0xffffffffL\n#define BIT_FW_DBG7_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_FW_DBG7_8822C) << BIT_SHIFT_FW_DBG7_8822C)\n#define BITS_FW_DBG7_8822C (BIT_MASK_FW_DBG7_8822C << BIT_SHIFT_FW_DBG7_8822C)\n#define BIT_CLEAR_FW_DBG7_8822C(x) ((x) & (~BITS_FW_DBG7_8822C))\n#define BIT_GET_FW_DBG7_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_DBG7_8822C) & BIT_MASK_FW_DBG7_8822C)\n#define BIT_SET_FW_DBG7_8822C(x, v)                                            \\\n\t(BIT_CLEAR_FW_DBG7_8822C(x) | BIT_FW_DBG7_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_CR_8822C */\n\n#define BIT_SHIFT_LBMODE_8822C 24\n#define BIT_MASK_LBMODE_8822C 0x1f\n#define BIT_LBMODE_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_LBMODE_8822C) << BIT_SHIFT_LBMODE_8822C)\n#define BITS_LBMODE_8822C (BIT_MASK_LBMODE_8822C << BIT_SHIFT_LBMODE_8822C)\n#define BIT_CLEAR_LBMODE_8822C(x) ((x) & (~BITS_LBMODE_8822C))\n#define BIT_GET_LBMODE_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_LBMODE_8822C) & BIT_MASK_LBMODE_8822C)\n#define BIT_SET_LBMODE_8822C(x, v)                                             \\\n\t(BIT_CLEAR_LBMODE_8822C(x) | BIT_LBMODE_8822C(v))\n\n#define BIT_SHIFT_NETYPE1_8822C 18\n#define BIT_MASK_NETYPE1_8822C 0x3\n#define BIT_NETYPE1_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE1_8822C) << BIT_SHIFT_NETYPE1_8822C)\n#define BITS_NETYPE1_8822C (BIT_MASK_NETYPE1_8822C << BIT_SHIFT_NETYPE1_8822C)\n#define BIT_CLEAR_NETYPE1_8822C(x) ((x) & (~BITS_NETYPE1_8822C))\n#define BIT_GET_NETYPE1_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE1_8822C) & BIT_MASK_NETYPE1_8822C)\n#define BIT_SET_NETYPE1_8822C(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE1_8822C(x) | BIT_NETYPE1_8822C(v))\n\n#define BIT_SHIFT_NETYPE0_8822C 16\n#define BIT_MASK_NETYPE0_8822C 0x3\n#define BIT_NETYPE0_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE0_8822C) << BIT_SHIFT_NETYPE0_8822C)\n#define BITS_NETYPE0_8822C (BIT_MASK_NETYPE0_8822C << BIT_SHIFT_NETYPE0_8822C)\n#define BIT_CLEAR_NETYPE0_8822C(x) ((x) & (~BITS_NETYPE0_8822C))\n#define BIT_GET_NETYPE0_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE0_8822C) & BIT_MASK_NETYPE0_8822C)\n#define BIT_SET_NETYPE0_8822C(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE0_8822C(x) | BIT_NETYPE0_8822C(v))\n\n#define BIT_COUNTER_STS_EN_8822C BIT(13)\n#define BIT_I2C_MAILBOX_EN_8822C BIT(12)\n#define BIT_SHCUT_EN_8822C BIT(11)\n#define BIT_32K_CAL_TMR_EN_8822C BIT(10)\n#define BIT_MAC_SEC_EN_8822C BIT(9)\n#define BIT_ENSWBCN_8822C BIT(8)\n#define BIT_MACRXEN_8822C BIT(7)\n#define BIT_MACTXEN_8822C BIT(6)\n#define BIT_SCHEDULE_EN_8822C BIT(5)\n#define BIT_PROTOCOL_EN_8822C BIT(4)\n#define BIT_RXDMA_EN_8822C BIT(3)\n#define BIT_TXDMA_EN_8822C BIT(2)\n#define BIT_HCI_RXDMA_EN_8822C BIT(1)\n#define BIT_HCI_TXDMA_EN_8822C BIT(0)\n\n/* 2 REG_PG_SIZE_8822C */\n\n#define BIT_SHIFT_DBG_FIFO_SEL_8822C 16\n#define BIT_MASK_DBG_FIFO_SEL_8822C 0xff\n#define BIT_DBG_FIFO_SEL_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DBG_FIFO_SEL_8822C) << BIT_SHIFT_DBG_FIFO_SEL_8822C)\n#define BITS_DBG_FIFO_SEL_8822C                                                \\\n\t(BIT_MASK_DBG_FIFO_SEL_8822C << BIT_SHIFT_DBG_FIFO_SEL_8822C)\n#define BIT_CLEAR_DBG_FIFO_SEL_8822C(x) ((x) & (~BITS_DBG_FIFO_SEL_8822C))\n#define BIT_GET_DBG_FIFO_SEL_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DBG_FIFO_SEL_8822C) & BIT_MASK_DBG_FIFO_SEL_8822C)\n#define BIT_SET_DBG_FIFO_SEL_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DBG_FIFO_SEL_8822C(x) | BIT_DBG_FIFO_SEL_8822C(v))\n\n/* 2 REG_PKT_BUFF_ACCESS_CTRL_8822C */\n\n#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C 0\n#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C 0xff\n#define BIT_PKT_BUFF_ACCESS_CTRL_8822C(x)                                      \\\n\t(((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C)                           \\\n\t << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C)\n#define BITS_PKT_BUFF_ACCESS_CTRL_8822C                                        \\\n\t(BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C                                   \\\n\t << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C)\n#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8822C(x)                                \\\n\t((x) & (~BITS_PKT_BUFF_ACCESS_CTRL_8822C))\n#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C) &                       \\\n\t BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C)\n#define BIT_SET_PKT_BUFF_ACCESS_CTRL_8822C(x, v)                               \\\n\t(BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8822C(x) |                             \\\n\t BIT_PKT_BUFF_ACCESS_CTRL_8822C(v))\n\n/* 2 REG_TSF_CLK_STATE_8822C */\n#define BIT_TSF_CLK_STABLE_8822C BIT(15)\n\n/* 2 REG_TXDMA_PQ_MAP_8822C */\n#define BIT_CSI_BW_EN_8822C BIT(31)\n\n#define BIT_SHIFT_TXDMA_H2C_MAP_8822C 16\n#define BIT_MASK_TXDMA_H2C_MAP_8822C 0x3\n#define BIT_TXDMA_H2C_MAP_8822C(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_H2C_MAP_8822C) << BIT_SHIFT_TXDMA_H2C_MAP_8822C)\n#define BITS_TXDMA_H2C_MAP_8822C                                               \\\n\t(BIT_MASK_TXDMA_H2C_MAP_8822C << BIT_SHIFT_TXDMA_H2C_MAP_8822C)\n#define BIT_CLEAR_TXDMA_H2C_MAP_8822C(x) ((x) & (~BITS_TXDMA_H2C_MAP_8822C))\n#define BIT_GET_TXDMA_H2C_MAP_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_H2C_MAP_8822C) & BIT_MASK_TXDMA_H2C_MAP_8822C)\n#define BIT_SET_TXDMA_H2C_MAP_8822C(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_H2C_MAP_8822C(x) | BIT_TXDMA_H2C_MAP_8822C(v))\n\n#define BIT_SHIFT_TXDMA_HIQ_MAP_8822C 14\n#define BIT_MASK_TXDMA_HIQ_MAP_8822C 0x3\n#define BIT_TXDMA_HIQ_MAP_8822C(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_HIQ_MAP_8822C) << BIT_SHIFT_TXDMA_HIQ_MAP_8822C)\n#define BITS_TXDMA_HIQ_MAP_8822C                                               \\\n\t(BIT_MASK_TXDMA_HIQ_MAP_8822C << BIT_SHIFT_TXDMA_HIQ_MAP_8822C)\n#define BIT_CLEAR_TXDMA_HIQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8822C))\n#define BIT_GET_TXDMA_HIQ_MAP_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8822C) & BIT_MASK_TXDMA_HIQ_MAP_8822C)\n#define BIT_SET_TXDMA_HIQ_MAP_8822C(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_HIQ_MAP_8822C(x) | BIT_TXDMA_HIQ_MAP_8822C(v))\n\n#define BIT_SHIFT_TXDMA_MGQ_MAP_8822C 12\n#define BIT_MASK_TXDMA_MGQ_MAP_8822C 0x3\n#define BIT_TXDMA_MGQ_MAP_8822C(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_MGQ_MAP_8822C) << BIT_SHIFT_TXDMA_MGQ_MAP_8822C)\n#define BITS_TXDMA_MGQ_MAP_8822C                                               \\\n\t(BIT_MASK_TXDMA_MGQ_MAP_8822C << BIT_SHIFT_TXDMA_MGQ_MAP_8822C)\n#define BIT_CLEAR_TXDMA_MGQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8822C))\n#define BIT_GET_TXDMA_MGQ_MAP_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8822C) & BIT_MASK_TXDMA_MGQ_MAP_8822C)\n#define BIT_SET_TXDMA_MGQ_MAP_8822C(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_MGQ_MAP_8822C(x) | BIT_TXDMA_MGQ_MAP_8822C(v))\n\n#define BIT_SHIFT_TXDMA_BKQ_MAP_8822C 10\n#define BIT_MASK_TXDMA_BKQ_MAP_8822C 0x3\n#define BIT_TXDMA_BKQ_MAP_8822C(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_BKQ_MAP_8822C) << BIT_SHIFT_TXDMA_BKQ_MAP_8822C)\n#define BITS_TXDMA_BKQ_MAP_8822C                                               \\\n\t(BIT_MASK_TXDMA_BKQ_MAP_8822C << BIT_SHIFT_TXDMA_BKQ_MAP_8822C)\n#define BIT_CLEAR_TXDMA_BKQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8822C))\n#define BIT_GET_TXDMA_BKQ_MAP_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8822C) & BIT_MASK_TXDMA_BKQ_MAP_8822C)\n#define BIT_SET_TXDMA_BKQ_MAP_8822C(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_BKQ_MAP_8822C(x) | BIT_TXDMA_BKQ_MAP_8822C(v))\n\n#define BIT_SHIFT_TXDMA_BEQ_MAP_8822C 8\n#define BIT_MASK_TXDMA_BEQ_MAP_8822C 0x3\n#define BIT_TXDMA_BEQ_MAP_8822C(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_BEQ_MAP_8822C) << BIT_SHIFT_TXDMA_BEQ_MAP_8822C)\n#define BITS_TXDMA_BEQ_MAP_8822C                                               \\\n\t(BIT_MASK_TXDMA_BEQ_MAP_8822C << BIT_SHIFT_TXDMA_BEQ_MAP_8822C)\n#define BIT_CLEAR_TXDMA_BEQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8822C))\n#define BIT_GET_TXDMA_BEQ_MAP_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8822C) & BIT_MASK_TXDMA_BEQ_MAP_8822C)\n#define BIT_SET_TXDMA_BEQ_MAP_8822C(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_BEQ_MAP_8822C(x) | BIT_TXDMA_BEQ_MAP_8822C(v))\n\n#define BIT_SHIFT_TXDMA_VIQ_MAP_8822C 6\n#define BIT_MASK_TXDMA_VIQ_MAP_8822C 0x3\n#define BIT_TXDMA_VIQ_MAP_8822C(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_VIQ_MAP_8822C) << BIT_SHIFT_TXDMA_VIQ_MAP_8822C)\n#define BITS_TXDMA_VIQ_MAP_8822C                                               \\\n\t(BIT_MASK_TXDMA_VIQ_MAP_8822C << BIT_SHIFT_TXDMA_VIQ_MAP_8822C)\n#define BIT_CLEAR_TXDMA_VIQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8822C))\n#define BIT_GET_TXDMA_VIQ_MAP_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8822C) & BIT_MASK_TXDMA_VIQ_MAP_8822C)\n#define BIT_SET_TXDMA_VIQ_MAP_8822C(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_VIQ_MAP_8822C(x) | BIT_TXDMA_VIQ_MAP_8822C(v))\n\n#define BIT_SHIFT_TXDMA_VOQ_MAP_8822C 4\n#define BIT_MASK_TXDMA_VOQ_MAP_8822C 0x3\n#define BIT_TXDMA_VOQ_MAP_8822C(x)                                             \\\n\t(((x) & BIT_MASK_TXDMA_VOQ_MAP_8822C) << BIT_SHIFT_TXDMA_VOQ_MAP_8822C)\n#define BITS_TXDMA_VOQ_MAP_8822C                                               \\\n\t(BIT_MASK_TXDMA_VOQ_MAP_8822C << BIT_SHIFT_TXDMA_VOQ_MAP_8822C)\n#define BIT_CLEAR_TXDMA_VOQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8822C))\n#define BIT_GET_TXDMA_VOQ_MAP_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8822C) & BIT_MASK_TXDMA_VOQ_MAP_8822C)\n#define BIT_SET_TXDMA_VOQ_MAP_8822C(x, v)                                      \\\n\t(BIT_CLEAR_TXDMA_VOQ_MAP_8822C(x) | BIT_TXDMA_VOQ_MAP_8822C(v))\n\n#define BIT_TXDMA_BW_EN_8822C BIT(3)\n#define BIT_RXDMA_AGG_EN_8822C BIT(2)\n#define BIT_RXSHFT_EN_8822C BIT(1)\n#define BIT_RXDMA_ARBBW_EN_8822C BIT(0)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_TRXFF_BNDY_8822C */\n\n#define BIT_SHIFT_FWFFOVFL_RSV_8822C 16\n#define BIT_MASK_FWFFOVFL_RSV_8822C 0xf\n#define BIT_FWFFOVFL_RSV_8822C(x)                                              \\\n\t(((x) & BIT_MASK_FWFFOVFL_RSV_8822C) << BIT_SHIFT_FWFFOVFL_RSV_8822C)\n#define BITS_FWFFOVFL_RSV_8822C                                                \\\n\t(BIT_MASK_FWFFOVFL_RSV_8822C << BIT_SHIFT_FWFFOVFL_RSV_8822C)\n#define BIT_CLEAR_FWFFOVFL_RSV_8822C(x) ((x) & (~BITS_FWFFOVFL_RSV_8822C))\n#define BIT_GET_FWFFOVFL_RSV_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_FWFFOVFL_RSV_8822C) & BIT_MASK_FWFFOVFL_RSV_8822C)\n#define BIT_SET_FWFFOVFL_RSV_8822C(x, v)                                       \\\n\t(BIT_CLEAR_FWFFOVFL_RSV_8822C(x) | BIT_FWFFOVFL_RSV_8822C(v))\n\n#define BIT_SHIFT_RXFFOVFL_RSV_V2_8822C 8\n#define BIT_MASK_RXFFOVFL_RSV_V2_8822C 0xf\n#define BIT_RXFFOVFL_RSV_V2_8822C(x)                                           \\\n\t(((x) & BIT_MASK_RXFFOVFL_RSV_V2_8822C)                                \\\n\t << BIT_SHIFT_RXFFOVFL_RSV_V2_8822C)\n#define BITS_RXFFOVFL_RSV_V2_8822C                                             \\\n\t(BIT_MASK_RXFFOVFL_RSV_V2_8822C << BIT_SHIFT_RXFFOVFL_RSV_V2_8822C)\n#define BIT_CLEAR_RXFFOVFL_RSV_V2_8822C(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8822C))\n#define BIT_GET_RXFFOVFL_RSV_V2_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8822C) &                            \\\n\t BIT_MASK_RXFFOVFL_RSV_V2_8822C)\n#define BIT_SET_RXFFOVFL_RSV_V2_8822C(x, v)                                    \\\n\t(BIT_CLEAR_RXFFOVFL_RSV_V2_8822C(x) | BIT_RXFFOVFL_RSV_V2_8822C(v))\n\n/* 2 REG_PTA_I2C_MBOX_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_I2C_M_STATUS_8822C 8\n#define BIT_MASK_I2C_M_STATUS_8822C 0xf\n#define BIT_I2C_M_STATUS_8822C(x)                                              \\\n\t(((x) & BIT_MASK_I2C_M_STATUS_8822C) << BIT_SHIFT_I2C_M_STATUS_8822C)\n#define BITS_I2C_M_STATUS_8822C                                                \\\n\t(BIT_MASK_I2C_M_STATUS_8822C << BIT_SHIFT_I2C_M_STATUS_8822C)\n#define BIT_CLEAR_I2C_M_STATUS_8822C(x) ((x) & (~BITS_I2C_M_STATUS_8822C))\n#define BIT_GET_I2C_M_STATUS_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_I2C_M_STATUS_8822C) & BIT_MASK_I2C_M_STATUS_8822C)\n#define BIT_SET_I2C_M_STATUS_8822C(x, v)                                       \\\n\t(BIT_CLEAR_I2C_M_STATUS_8822C(x) | BIT_I2C_M_STATUS_8822C(v))\n\n#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C 4\n#define BIT_MASK_I2C_M_BUS_GNT_FW_8822C 0x7\n#define BIT_I2C_M_BUS_GNT_FW_8822C(x)                                          \\\n\t(((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8822C)                               \\\n\t << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C)\n#define BITS_I2C_M_BUS_GNT_FW_8822C                                            \\\n\t(BIT_MASK_I2C_M_BUS_GNT_FW_8822C << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C)\n#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8822C(x)                                    \\\n\t((x) & (~BITS_I2C_M_BUS_GNT_FW_8822C))\n#define BIT_GET_I2C_M_BUS_GNT_FW_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C) &                           \\\n\t BIT_MASK_I2C_M_BUS_GNT_FW_8822C)\n#define BIT_SET_I2C_M_BUS_GNT_FW_8822C(x, v)                                   \\\n\t(BIT_CLEAR_I2C_M_BUS_GNT_FW_8822C(x) | BIT_I2C_M_BUS_GNT_FW_8822C(v))\n\n#define BIT_I2C_M_GNT_FW_8822C BIT(3)\n\n#define BIT_SHIFT_I2C_M_SPEED_8822C 1\n#define BIT_MASK_I2C_M_SPEED_8822C 0x3\n#define BIT_I2C_M_SPEED_8822C(x)                                               \\\n\t(((x) & BIT_MASK_I2C_M_SPEED_8822C) << BIT_SHIFT_I2C_M_SPEED_8822C)\n#define BITS_I2C_M_SPEED_8822C                                                 \\\n\t(BIT_MASK_I2C_M_SPEED_8822C << BIT_SHIFT_I2C_M_SPEED_8822C)\n#define BIT_CLEAR_I2C_M_SPEED_8822C(x) ((x) & (~BITS_I2C_M_SPEED_8822C))\n#define BIT_GET_I2C_M_SPEED_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_I2C_M_SPEED_8822C) & BIT_MASK_I2C_M_SPEED_8822C)\n#define BIT_SET_I2C_M_SPEED_8822C(x, v)                                        \\\n\t(BIT_CLEAR_I2C_M_SPEED_8822C(x) | BIT_I2C_M_SPEED_8822C(v))\n\n#define BIT_I2C_M_UNLOCK_8822C BIT(0)\n\n/* 2 REG_RXFF_BNDY_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_RXFF0_BNDY_V2_8822C 0\n#define BIT_MASK_RXFF0_BNDY_V2_8822C 0x3ffff\n#define BIT_RXFF0_BNDY_V2_8822C(x)                                             \\\n\t(((x) & BIT_MASK_RXFF0_BNDY_V2_8822C) << BIT_SHIFT_RXFF0_BNDY_V2_8822C)\n#define BITS_RXFF0_BNDY_V2_8822C                                               \\\n\t(BIT_MASK_RXFF0_BNDY_V2_8822C << BIT_SHIFT_RXFF0_BNDY_V2_8822C)\n#define BIT_CLEAR_RXFF0_BNDY_V2_8822C(x) ((x) & (~BITS_RXFF0_BNDY_V2_8822C))\n#define BIT_GET_RXFF0_BNDY_V2_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8822C) & BIT_MASK_RXFF0_BNDY_V2_8822C)\n#define BIT_SET_RXFF0_BNDY_V2_8822C(x, v)                                      \\\n\t(BIT_CLEAR_RXFF0_BNDY_V2_8822C(x) | BIT_RXFF0_BNDY_V2_8822C(v))\n\n/* 2 REG_FE1IMR_8822C */\n#define BIT_FS_SW_PLL_LEAVE_32K_INT_EN_8822C BIT(31)\n#define BIT_FS_FWFF_FULL_INT_EN_8822C BIT(30)\n#define BIT_FS_BB_STOP_RX_INT_EN_8822C BIT(29)\n#define BIT_FS_RXDMA2_DONE_INT_EN_8822C BIT(28)\n#define BIT_FS_RXDONE2_INT_EN_8822C BIT(26)\n#define BIT_FS_RX_BCN_P4_INT_EN_8822C BIT(25)\n#define BIT_FS_RX_BCN_P3_INT_EN_8822C BIT(24)\n#define BIT_FS_RX_BCN_P2_INT_EN_8822C BIT(23)\n#define BIT_FS_RX_BCN_P1_INT_EN_8822C BIT(22)\n#define BIT_FS_RX_BCN_P0_INT_EN_8822C BIT(21)\n#define BIT_FS_RX_UMD0_INT_EN_8822C BIT(20)\n#define BIT_FS_RX_UMD1_INT_EN_8822C BIT(19)\n#define BIT_FS_RX_BMD0_INT_EN_8822C BIT(18)\n#define BIT_FS_RX_BMD1_INT_EN_8822C BIT(17)\n#define BIT_FS_RXDONE_INT_EN_8822C BIT(16)\n#define BIT_FS_WWLAN_INT_EN_8822C BIT(15)\n#define BIT_FS_SOUND_DONE_INT_EN_8822C BIT(14)\n#define BIT_FS_BF1_PRETO_INT_EN_8822C BIT(11)\n#define BIT_FS_BF0_PRETO_INT_EN_8822C BIT(10)\n#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8822C BIT(9)\n#define BIT_FS_PRETX_ERRHLD_INT_EN_8822C BIT(8)\n#define BIT_FS_LTE_COEX_EN_8822C BIT(6)\n#define BIT_FS_WLACTOFF_INT_EN_8822C BIT(5)\n#define BIT_FS_WLACTON_INT_EN_8822C BIT(4)\n#define BIT_FS_BTCMD_INT_EN_8822C BIT(3)\n#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8822C BIT(2)\n#define BIT_FS_TRPC_TO_INT_EN_V1_8822C BIT(1)\n#define BIT_FS_RPC_O_T_INT_EN_V1_8822C BIT(0)\n\n/* 2 REG_FE1ISR_8822C */\n#define BIT_FS_SW_PLL_LEAVE_32K_INT_8822C BIT(31)\n#define BIT_FS_FS_FWFF_FULL_INT_8822C BIT(30)\n#define BIT_FS_BB_STOP_RX_INT_8822C BIT(29)\n#define BIT_FS_RXDMA2_DONE_INT_8822C BIT(28)\n#define BIT_FS_RXDONE2_INT_8822C BIT(26)\n#define BIT_FS_RX_BCN_P4_INT_8822C BIT(25)\n#define BIT_FS_RX_BCN_P3_INT_8822C BIT(24)\n#define BIT_FS_RX_BCN_P2_INT_8822C BIT(23)\n#define BIT_FS_RX_BCN_P1_INT_8822C BIT(22)\n#define BIT_FS_RX_BCN_P0_INT_8822C BIT(21)\n#define BIT_FS_RX_UMD0_INT_8822C BIT(20)\n#define BIT_FS_RX_UMD1_INT_8822C BIT(19)\n#define BIT_FS_RX_BMD0_INT_8822C BIT(18)\n#define BIT_FS_RX_BMD1_INT_8822C BIT(17)\n#define BIT_FS_RXDONE_INT_8822C BIT(16)\n#define BIT_FS_WWLAN_INT_8822C BIT(15)\n#define BIT_FS_SOUND_DONE_INT_8822C BIT(14)\n#define BIT_FS_BF1_PRETO_INT_8822C BIT(11)\n#define BIT_FS_BF0_PRETO_INT_8822C BIT(10)\n#define BIT_FS_PTCL_RELEASE_MACID_INT_8822C BIT(9)\n#define BIT_FS_PRETX_ERRHLD_INT_8822C BIT(8)\n#define BIT_FS_LTE_COEX_INT_8822C BIT(6)\n#define BIT_FS_WLACTOFF_INT_8822C BIT(5)\n#define BIT_FS_WLACTON_INT_8822C BIT(4)\n#define BIT_FS_BCN_RX_INT_INT_8822C BIT(3)\n#define BIT_FS_MAILBOX_TO_I2C_INT_8822C BIT(2)\n#define BIT_FS_TRPC_TO_INT_8822C BIT(1)\n#define BIT_FS_RPC_O_T_INT_8822C BIT(0)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_CPWM_8822C */\n#define BIT_CPWM_TOGGLING_8822C BIT(31)\n\n#define BIT_SHIFT_CPWM_MOD_8822C 24\n#define BIT_MASK_CPWM_MOD_8822C 0x7f\n#define BIT_CPWM_MOD_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_CPWM_MOD_8822C) << BIT_SHIFT_CPWM_MOD_8822C)\n#define BITS_CPWM_MOD_8822C                                                    \\\n\t(BIT_MASK_CPWM_MOD_8822C << BIT_SHIFT_CPWM_MOD_8822C)\n#define BIT_CLEAR_CPWM_MOD_8822C(x) ((x) & (~BITS_CPWM_MOD_8822C))\n#define BIT_GET_CPWM_MOD_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_CPWM_MOD_8822C) & BIT_MASK_CPWM_MOD_8822C)\n#define BIT_SET_CPWM_MOD_8822C(x, v)                                           \\\n\t(BIT_CLEAR_CPWM_MOD_8822C(x) | BIT_CPWM_MOD_8822C(v))\n\n/* 2 REG_FWIMR_8822C */\n#define BIT_FS_TXBCNOK_MB7_INT_EN_8822C BIT(31)\n#define BIT_FS_TXBCNOK_MB6_INT_EN_8822C BIT(30)\n#define BIT_FS_TXBCNOK_MB5_INT_EN_8822C BIT(29)\n#define BIT_FS_TXBCNOK_MB4_INT_EN_8822C BIT(28)\n#define BIT_FS_TXBCNOK_MB3_INT_EN_8822C BIT(27)\n#define BIT_FS_TXBCNOK_MB2_INT_EN_8822C BIT(26)\n#define BIT_FS_TXBCNOK_MB1_INT_EN_8822C BIT(25)\n#define BIT_FS_TXBCNOK_MB0_INT_EN_8822C BIT(24)\n#define BIT_FS_TXBCNERR_MB7_INT_EN_8822C BIT(23)\n#define BIT_FS_TXBCNERR_MB6_INT_EN_8822C BIT(22)\n#define BIT_FS_TXBCNERR_MB5_INT_EN_8822C BIT(21)\n#define BIT_FS_TXBCNERR_MB4_INT_EN_8822C BIT(20)\n#define BIT_FS_TXBCNERR_MB3_INT_EN_8822C BIT(19)\n#define BIT_FS_TXBCNERR_MB2_INT_EN_8822C BIT(18)\n#define BIT_FS_TXBCNERR_MB1_INT_EN_8822C BIT(17)\n#define BIT_FS_TXBCNERR_MB0_INT_EN_8822C BIT(16)\n#define BIT_CPU_MGQ_TXDONE_INT_EN_8822C BIT(15)\n#define BIT_SIFS_OVERSPEC_INT_EN_8822C BIT(14)\n#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8822C BIT(13)\n#define BIT_FS_MGNTQFF_TO_INT_EN_8822C BIT(12)\n#define BIT_FS_CPUMGQ_ERR_INT_EN_8822C BIT(11)\n#define BIT_FS_DDMA0_LP_INT_EN_8822C BIT(9)\n#define BIT_FS_DDMA0_HP_INT_EN_8822C BIT(8)\n#define BIT_FS_TRXRPT_INT_EN_8822C BIT(7)\n#define BIT_FS_C2H_W_READY_INT_EN_8822C BIT(6)\n#define BIT_FS_HRCV_INT_EN_8822C BIT(5)\n#define BIT_FS_H2CCMD_INT_EN_8822C BIT(4)\n#define BIT_FS_TXPKTIN_INT_EN_8822C BIT(3)\n#define BIT_FS_ERRORHDL_INT_EN_8822C BIT(2)\n#define BIT_FS_TXCCX_INT_EN_8822C BIT(1)\n#define BIT_FS_TXCLOSE_INT_EN_8822C BIT(0)\n\n/* 2 REG_FWISR_8822C */\n#define BIT_FS_TXBCNOK_MB7_INT_8822C BIT(31)\n#define BIT_FS_TXBCNOK_MB6_INT_8822C BIT(30)\n#define BIT_FS_TXBCNOK_MB5_INT_8822C BIT(29)\n#define BIT_FS_TXBCNOK_MB4_INT_8822C BIT(28)\n#define BIT_FS_TXBCNOK_MB3_INT_8822C BIT(27)\n#define BIT_FS_TXBCNOK_MB2_INT_8822C BIT(26)\n#define BIT_FS_TXBCNOK_MB1_INT_8822C BIT(25)\n#define BIT_FS_TXBCNOK_MB0_INT_8822C BIT(24)\n#define BIT_FS_TXBCNERR_MB7_INT_8822C BIT(23)\n#define BIT_FS_TXBCNERR_MB6_INT_8822C BIT(22)\n#define BIT_FS_TXBCNERR_MB5_INT_8822C BIT(21)\n#define BIT_FS_TXBCNERR_MB4_INT_8822C BIT(20)\n#define BIT_FS_TXBCNERR_MB3_INT_8822C BIT(19)\n#define BIT_FS_TXBCNERR_MB2_INT_8822C BIT(18)\n#define BIT_FS_TXBCNERR_MB1_INT_8822C BIT(17)\n#define BIT_FS_TXBCNERR_MB0_INT_8822C BIT(16)\n#define BIT_CPU_MGQ_TXDONE_INT_8822C BIT(15)\n#define BIT_SIFS_OVERSPEC_INT_8822C BIT(14)\n#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8822C BIT(13)\n#define BIT_FS_MGNTQFF_TO_INT_8822C BIT(12)\n#define BIT_FS_CPUMGQ_ERR_INT_8822C BIT(11)\n#define BIT_FS_DDMA0_LP_INT_8822C BIT(9)\n#define BIT_FS_DDMA0_HP_INT_8822C BIT(8)\n#define BIT_FS_TRXRPT_INT_8822C BIT(7)\n#define BIT_FS_C2H_W_READY_INT_8822C BIT(6)\n#define BIT_FS_HRCV_INT_8822C BIT(5)\n#define BIT_FS_H2CCMD_INT_8822C BIT(4)\n#define BIT_FS_TXPKTIN_INT_8822C BIT(3)\n#define BIT_FS_ERRORHDL_INT_8822C BIT(2)\n#define BIT_FS_TXCCX_INT_8822C BIT(1)\n#define BIT_FS_TXCLOSE_INT_8822C BIT(0)\n\n/* 2 REG_FTIMR_8822C */\n#define BIT_PS_TIMER_C_EARLY_INT_EN_8822C BIT(23)\n#define BIT_PS_TIMER_B_EARLY_INT_EN_8822C BIT(22)\n#define BIT_PS_TIMER_A_EARLY_INT_EN_8822C BIT(21)\n#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8822C BIT(20)\n#define BIT_PS_TIMER_C_INT_EN_8822C BIT(19)\n#define BIT_PS_TIMER_B_INT_EN_8822C BIT(18)\n#define BIT_PS_TIMER_A_INT_EN_8822C BIT(17)\n#define BIT_CPUMGQ_TX_TIMER_INT_EN_8822C BIT(16)\n#define BIT_FS_PS_TIMEOUT2_EN_8822C BIT(15)\n#define BIT_FS_PS_TIMEOUT1_EN_8822C BIT(14)\n#define BIT_FS_PS_TIMEOUT0_EN_8822C BIT(13)\n#define BIT_FS_GTINT8_EN_8822C BIT(8)\n#define BIT_FS_GTINT7_EN_8822C BIT(7)\n#define BIT_FS_GTINT6_EN_8822C BIT(6)\n#define BIT_FS_GTINT5_EN_8822C BIT(5)\n#define BIT_FS_GTINT4_EN_8822C BIT(4)\n#define BIT_FS_GTINT3_EN_8822C BIT(3)\n#define BIT_FS_GTINT2_EN_8822C BIT(2)\n#define BIT_FS_GTINT1_EN_8822C BIT(1)\n#define BIT_FS_GTINT0_EN_8822C BIT(0)\n\n/* 2 REG_FTISR_8822C */\n#define BIT_PS_TIMER_C_EARLY__INT_8822C BIT(23)\n#define BIT_PS_TIMER_B_EARLY__INT_8822C BIT(22)\n#define BIT_PS_TIMER_A_EARLY__INT_8822C BIT(21)\n#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8822C BIT(20)\n#define BIT_PS_TIMER_C_INT_8822C BIT(19)\n#define BIT_PS_TIMER_B_INT_8822C BIT(18)\n#define BIT_PS_TIMER_A_INT_8822C BIT(17)\n#define BIT_CPUMGQ_TX_TIMER_INT_8822C BIT(16)\n#define BIT_FS_PS_TIMEOUT2_INT_8822C BIT(15)\n#define BIT_FS_PS_TIMEOUT1_INT_8822C BIT(14)\n#define BIT_FS_PS_TIMEOUT0_INT_8822C BIT(13)\n#define BIT_FS_GTINT8_INT_8822C BIT(8)\n#define BIT_FS_GTINT7_INT_8822C BIT(7)\n#define BIT_FS_GTINT6_INT_8822C BIT(6)\n#define BIT_FS_GTINT5_INT_8822C BIT(5)\n#define BIT_FS_GTINT4_INT_8822C BIT(4)\n#define BIT_FS_GTINT3_INT_8822C BIT(3)\n#define BIT_FS_GTINT2_INT_8822C BIT(2)\n#define BIT_FS_GTINT1_INT_8822C BIT(1)\n#define BIT_FS_GTINT0_INT_8822C BIT(0)\n\n/* 2 REG_PKTBUF_DBG_CTRL_8822C */\n\n#define BIT_SHIFT_PKTBUF_WRITE_EN_8822C 24\n#define BIT_MASK_PKTBUF_WRITE_EN_8822C 0xff\n#define BIT_PKTBUF_WRITE_EN_8822C(x)                                           \\\n\t(((x) & BIT_MASK_PKTBUF_WRITE_EN_8822C)                                \\\n\t << BIT_SHIFT_PKTBUF_WRITE_EN_8822C)\n#define BITS_PKTBUF_WRITE_EN_8822C                                             \\\n\t(BIT_MASK_PKTBUF_WRITE_EN_8822C << BIT_SHIFT_PKTBUF_WRITE_EN_8822C)\n#define BIT_CLEAR_PKTBUF_WRITE_EN_8822C(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8822C))\n#define BIT_GET_PKTBUF_WRITE_EN_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8822C) &                            \\\n\t BIT_MASK_PKTBUF_WRITE_EN_8822C)\n#define BIT_SET_PKTBUF_WRITE_EN_8822C(x, v)                                    \\\n\t(BIT_CLEAR_PKTBUF_WRITE_EN_8822C(x) | BIT_PKTBUF_WRITE_EN_8822C(v))\n\n#define BIT_TXRPTBUF_DBG_8822C BIT(23)\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_TXPKTBUF_DBG_V2_8822C BIT(20)\n#define BIT_RXPKTBUF_DBG_8822C BIT(16)\n\n#define BIT_SHIFT_PKTBUF_DBG_ADDR_8822C 0\n#define BIT_MASK_PKTBUF_DBG_ADDR_8822C 0x1fff\n#define BIT_PKTBUF_DBG_ADDR_8822C(x)                                           \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_ADDR_8822C)                                \\\n\t << BIT_SHIFT_PKTBUF_DBG_ADDR_8822C)\n#define BITS_PKTBUF_DBG_ADDR_8822C                                             \\\n\t(BIT_MASK_PKTBUF_DBG_ADDR_8822C << BIT_SHIFT_PKTBUF_DBG_ADDR_8822C)\n#define BIT_CLEAR_PKTBUF_DBG_ADDR_8822C(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8822C))\n#define BIT_GET_PKTBUF_DBG_ADDR_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8822C) &                            \\\n\t BIT_MASK_PKTBUF_DBG_ADDR_8822C)\n#define BIT_SET_PKTBUF_DBG_ADDR_8822C(x, v)                                    \\\n\t(BIT_CLEAR_PKTBUF_DBG_ADDR_8822C(x) | BIT_PKTBUF_DBG_ADDR_8822C(v))\n\n/* 2 REG_PKTBUF_DBG_DATA_L_8822C */\n\n#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C 0\n#define BIT_MASK_PKTBUF_DBG_DATA_L_8822C 0xffffffffL\n#define BIT_PKTBUF_DBG_DATA_L_8822C(x)                                         \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8822C)                              \\\n\t << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C)\n#define BITS_PKTBUF_DBG_DATA_L_8822C                                           \\\n\t(BIT_MASK_PKTBUF_DBG_DATA_L_8822C << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C)\n#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8822C(x)                                   \\\n\t((x) & (~BITS_PKTBUF_DBG_DATA_L_8822C))\n#define BIT_GET_PKTBUF_DBG_DATA_L_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C) &                          \\\n\t BIT_MASK_PKTBUF_DBG_DATA_L_8822C)\n#define BIT_SET_PKTBUF_DBG_DATA_L_8822C(x, v)                                  \\\n\t(BIT_CLEAR_PKTBUF_DBG_DATA_L_8822C(x) | BIT_PKTBUF_DBG_DATA_L_8822C(v))\n\n/* 2 REG_PKTBUF_DBG_DATA_H_8822C */\n\n#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C 0\n#define BIT_MASK_PKTBUF_DBG_DATA_H_8822C 0xffffffffL\n#define BIT_PKTBUF_DBG_DATA_H_8822C(x)                                         \\\n\t(((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8822C)                              \\\n\t << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C)\n#define BITS_PKTBUF_DBG_DATA_H_8822C                                           \\\n\t(BIT_MASK_PKTBUF_DBG_DATA_H_8822C << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C)\n#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8822C(x)                                   \\\n\t((x) & (~BITS_PKTBUF_DBG_DATA_H_8822C))\n#define BIT_GET_PKTBUF_DBG_DATA_H_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C) &                          \\\n\t BIT_MASK_PKTBUF_DBG_DATA_H_8822C)\n#define BIT_SET_PKTBUF_DBG_DATA_H_8822C(x, v)                                  \\\n\t(BIT_CLEAR_PKTBUF_DBG_DATA_H_8822C(x) | BIT_PKTBUF_DBG_DATA_H_8822C(v))\n\n/* 2 REG_CPWM2_8822C */\n\n#define BIT_SHIFT_L0S_TO_RCVY_NUM_8822C 16\n#define BIT_MASK_L0S_TO_RCVY_NUM_8822C 0xff\n#define BIT_L0S_TO_RCVY_NUM_8822C(x)                                           \\\n\t(((x) & BIT_MASK_L0S_TO_RCVY_NUM_8822C)                                \\\n\t << BIT_SHIFT_L0S_TO_RCVY_NUM_8822C)\n#define BITS_L0S_TO_RCVY_NUM_8822C                                             \\\n\t(BIT_MASK_L0S_TO_RCVY_NUM_8822C << BIT_SHIFT_L0S_TO_RCVY_NUM_8822C)\n#define BIT_CLEAR_L0S_TO_RCVY_NUM_8822C(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8822C))\n#define BIT_GET_L0S_TO_RCVY_NUM_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8822C) &                            \\\n\t BIT_MASK_L0S_TO_RCVY_NUM_8822C)\n#define BIT_SET_L0S_TO_RCVY_NUM_8822C(x, v)                                    \\\n\t(BIT_CLEAR_L0S_TO_RCVY_NUM_8822C(x) | BIT_L0S_TO_RCVY_NUM_8822C(v))\n\n#define BIT_CPWM2_TOGGLING_8822C BIT(15)\n\n#define BIT_SHIFT_CPWM2_MOD_8822C 0\n#define BIT_MASK_CPWM2_MOD_8822C 0x7fff\n#define BIT_CPWM2_MOD_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_CPWM2_MOD_8822C) << BIT_SHIFT_CPWM2_MOD_8822C)\n#define BITS_CPWM2_MOD_8822C                                                   \\\n\t(BIT_MASK_CPWM2_MOD_8822C << BIT_SHIFT_CPWM2_MOD_8822C)\n#define BIT_CLEAR_CPWM2_MOD_8822C(x) ((x) & (~BITS_CPWM2_MOD_8822C))\n#define BIT_GET_CPWM2_MOD_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_CPWM2_MOD_8822C) & BIT_MASK_CPWM2_MOD_8822C)\n#define BIT_SET_CPWM2_MOD_8822C(x, v)                                          \\\n\t(BIT_CLEAR_CPWM2_MOD_8822C(x) | BIT_CPWM2_MOD_8822C(v))\n\n/* 2 REG_TC0_CTRL_8822C */\n#define BIT_TC0INT_EN_8822C BIT(26)\n#define BIT_TC0MODE_8822C BIT(25)\n#define BIT_TC0EN_8822C BIT(24)\n\n#define BIT_SHIFT_TC0DATA_8822C 0\n#define BIT_MASK_TC0DATA_8822C 0xffffff\n#define BIT_TC0DATA_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_TC0DATA_8822C) << BIT_SHIFT_TC0DATA_8822C)\n#define BITS_TC0DATA_8822C (BIT_MASK_TC0DATA_8822C << BIT_SHIFT_TC0DATA_8822C)\n#define BIT_CLEAR_TC0DATA_8822C(x) ((x) & (~BITS_TC0DATA_8822C))\n#define BIT_GET_TC0DATA_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC0DATA_8822C) & BIT_MASK_TC0DATA_8822C)\n#define BIT_SET_TC0DATA_8822C(x, v)                                            \\\n\t(BIT_CLEAR_TC0DATA_8822C(x) | BIT_TC0DATA_8822C(v))\n\n/* 2 REG_TC1_CTRL_8822C */\n#define BIT_TC1INT_EN_8822C BIT(26)\n#define BIT_TC1MODE_8822C BIT(25)\n#define BIT_TC1EN_8822C BIT(24)\n\n#define BIT_SHIFT_TC1DATA_8822C 0\n#define BIT_MASK_TC1DATA_8822C 0xffffff\n#define BIT_TC1DATA_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_TC1DATA_8822C) << BIT_SHIFT_TC1DATA_8822C)\n#define BITS_TC1DATA_8822C (BIT_MASK_TC1DATA_8822C << BIT_SHIFT_TC1DATA_8822C)\n#define BIT_CLEAR_TC1DATA_8822C(x) ((x) & (~BITS_TC1DATA_8822C))\n#define BIT_GET_TC1DATA_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC1DATA_8822C) & BIT_MASK_TC1DATA_8822C)\n#define BIT_SET_TC1DATA_8822C(x, v)                                            \\\n\t(BIT_CLEAR_TC1DATA_8822C(x) | BIT_TC1DATA_8822C(v))\n\n/* 2 REG_TC2_CTRL_8822C */\n#define BIT_TC2INT_EN_8822C BIT(26)\n#define BIT_TC2MODE_8822C BIT(25)\n#define BIT_TC2EN_8822C BIT(24)\n\n#define BIT_SHIFT_TC2DATA_8822C 0\n#define BIT_MASK_TC2DATA_8822C 0xffffff\n#define BIT_TC2DATA_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_TC2DATA_8822C) << BIT_SHIFT_TC2DATA_8822C)\n#define BITS_TC2DATA_8822C (BIT_MASK_TC2DATA_8822C << BIT_SHIFT_TC2DATA_8822C)\n#define BIT_CLEAR_TC2DATA_8822C(x) ((x) & (~BITS_TC2DATA_8822C))\n#define BIT_GET_TC2DATA_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC2DATA_8822C) & BIT_MASK_TC2DATA_8822C)\n#define BIT_SET_TC2DATA_8822C(x, v)                                            \\\n\t(BIT_CLEAR_TC2DATA_8822C(x) | BIT_TC2DATA_8822C(v))\n\n/* 2 REG_TC3_CTRL_8822C */\n#define BIT_TC3INT_EN_8822C BIT(26)\n#define BIT_TC3MODE_8822C BIT(25)\n#define BIT_TC3EN_8822C BIT(24)\n\n#define BIT_SHIFT_TC3DATA_8822C 0\n#define BIT_MASK_TC3DATA_8822C 0xffffff\n#define BIT_TC3DATA_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_TC3DATA_8822C) << BIT_SHIFT_TC3DATA_8822C)\n#define BITS_TC3DATA_8822C (BIT_MASK_TC3DATA_8822C << BIT_SHIFT_TC3DATA_8822C)\n#define BIT_CLEAR_TC3DATA_8822C(x) ((x) & (~BITS_TC3DATA_8822C))\n#define BIT_GET_TC3DATA_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC3DATA_8822C) & BIT_MASK_TC3DATA_8822C)\n#define BIT_SET_TC3DATA_8822C(x, v)                                            \\\n\t(BIT_CLEAR_TC3DATA_8822C(x) | BIT_TC3DATA_8822C(v))\n\n/* 2 REG_TC4_CTRL_8822C */\n#define BIT_TC4INT_EN_8822C BIT(26)\n#define BIT_TC4MODE_8822C BIT(25)\n#define BIT_TC4EN_8822C BIT(24)\n\n#define BIT_SHIFT_TC4DATA_8822C 0\n#define BIT_MASK_TC4DATA_8822C 0xffffff\n#define BIT_TC4DATA_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_TC4DATA_8822C) << BIT_SHIFT_TC4DATA_8822C)\n#define BITS_TC4DATA_8822C (BIT_MASK_TC4DATA_8822C << BIT_SHIFT_TC4DATA_8822C)\n#define BIT_CLEAR_TC4DATA_8822C(x) ((x) & (~BITS_TC4DATA_8822C))\n#define BIT_GET_TC4DATA_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC4DATA_8822C) & BIT_MASK_TC4DATA_8822C)\n#define BIT_SET_TC4DATA_8822C(x, v)                                            \\\n\t(BIT_CLEAR_TC4DATA_8822C(x) | BIT_TC4DATA_8822C(v))\n\n/* 2 REG_TCUNIT_BASE_8822C */\n\n#define BIT_SHIFT_TCUNIT_BASE_8822C 0\n#define BIT_MASK_TCUNIT_BASE_8822C 0x3fff\n#define BIT_TCUNIT_BASE_8822C(x)                                               \\\n\t(((x) & BIT_MASK_TCUNIT_BASE_8822C) << BIT_SHIFT_TCUNIT_BASE_8822C)\n#define BITS_TCUNIT_BASE_8822C                                                 \\\n\t(BIT_MASK_TCUNIT_BASE_8822C << BIT_SHIFT_TCUNIT_BASE_8822C)\n#define BIT_CLEAR_TCUNIT_BASE_8822C(x) ((x) & (~BITS_TCUNIT_BASE_8822C))\n#define BIT_GET_TCUNIT_BASE_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_TCUNIT_BASE_8822C) & BIT_MASK_TCUNIT_BASE_8822C)\n#define BIT_SET_TCUNIT_BASE_8822C(x, v)                                        \\\n\t(BIT_CLEAR_TCUNIT_BASE_8822C(x) | BIT_TCUNIT_BASE_8822C(v))\n\n/* 2 REG_TC5_CTRL_8822C */\n#define BIT_TC5INT_EN_8822C BIT(26)\n#define BIT_TC5MODE_8822C BIT(25)\n#define BIT_TC5EN_8822C BIT(24)\n\n#define BIT_SHIFT_TC5DATA_8822C 0\n#define BIT_MASK_TC5DATA_8822C 0xffffff\n#define BIT_TC5DATA_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_TC5DATA_8822C) << BIT_SHIFT_TC5DATA_8822C)\n#define BITS_TC5DATA_8822C (BIT_MASK_TC5DATA_8822C << BIT_SHIFT_TC5DATA_8822C)\n#define BIT_CLEAR_TC5DATA_8822C(x) ((x) & (~BITS_TC5DATA_8822C))\n#define BIT_GET_TC5DATA_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC5DATA_8822C) & BIT_MASK_TC5DATA_8822C)\n#define BIT_SET_TC5DATA_8822C(x, v)                                            \\\n\t(BIT_CLEAR_TC5DATA_8822C(x) | BIT_TC5DATA_8822C(v))\n\n/* 2 REG_TC6_CTRL_8822C */\n#define BIT_TC6INT_EN_8822C BIT(26)\n#define BIT_TC6MODE_8822C BIT(25)\n#define BIT_TC6EN_8822C BIT(24)\n\n#define BIT_SHIFT_TC6DATA_8822C 0\n#define BIT_MASK_TC6DATA_8822C 0xffffff\n#define BIT_TC6DATA_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_TC6DATA_8822C) << BIT_SHIFT_TC6DATA_8822C)\n#define BITS_TC6DATA_8822C (BIT_MASK_TC6DATA_8822C << BIT_SHIFT_TC6DATA_8822C)\n#define BIT_CLEAR_TC6DATA_8822C(x) ((x) & (~BITS_TC6DATA_8822C))\n#define BIT_GET_TC6DATA_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC6DATA_8822C) & BIT_MASK_TC6DATA_8822C)\n#define BIT_SET_TC6DATA_8822C(x, v)                                            \\\n\t(BIT_CLEAR_TC6DATA_8822C(x) | BIT_TC6DATA_8822C(v))\n\n/* 2 REG_MBIST_DRF_FAIL_8822C */\n\n#define BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C 26\n#define BIT_MASK_8051_MBIST_DRF_FAIL_8822C 0x3f\n#define BIT_8051_MBIST_DRF_FAIL_8822C(x)                                       \\\n\t(((x) & BIT_MASK_8051_MBIST_DRF_FAIL_8822C)                            \\\n\t << BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C)\n#define BITS_8051_MBIST_DRF_FAIL_8822C                                         \\\n\t(BIT_MASK_8051_MBIST_DRF_FAIL_8822C                                    \\\n\t << BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C)\n#define BIT_CLEAR_8051_MBIST_DRF_FAIL_8822C(x)                                 \\\n\t((x) & (~BITS_8051_MBIST_DRF_FAIL_8822C))\n#define BIT_GET_8051_MBIST_DRF_FAIL_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C) &                        \\\n\t BIT_MASK_8051_MBIST_DRF_FAIL_8822C)\n#define BIT_SET_8051_MBIST_DRF_FAIL_8822C(x, v)                                \\\n\t(BIT_CLEAR_8051_MBIST_DRF_FAIL_8822C(x) |                              \\\n\t BIT_8051_MBIST_DRF_FAIL_8822C(v))\n\n#define BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C 24\n#define BIT_MASK_USB_MBIST_DRF_FAIL_8822C 0x3\n#define BIT_USB_MBIST_DRF_FAIL_8822C(x)                                        \\\n\t(((x) & BIT_MASK_USB_MBIST_DRF_FAIL_8822C)                             \\\n\t << BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C)\n#define BITS_USB_MBIST_DRF_FAIL_8822C                                          \\\n\t(BIT_MASK_USB_MBIST_DRF_FAIL_8822C                                     \\\n\t << BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C)\n#define BIT_CLEAR_USB_MBIST_DRF_FAIL_8822C(x)                                  \\\n\t((x) & (~BITS_USB_MBIST_DRF_FAIL_8822C))\n#define BIT_GET_USB_MBIST_DRF_FAIL_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C) &                         \\\n\t BIT_MASK_USB_MBIST_DRF_FAIL_8822C)\n#define BIT_SET_USB_MBIST_DRF_FAIL_8822C(x, v)                                 \\\n\t(BIT_CLEAR_USB_MBIST_DRF_FAIL_8822C(x) |                               \\\n\t BIT_USB_MBIST_DRF_FAIL_8822C(v))\n\n#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C 18\n#define BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C 0x3f\n#define BIT_PCIE_MBIST_DRF_FAIL_8822C(x)                                       \\\n\t(((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C)                            \\\n\t << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C)\n#define BITS_PCIE_MBIST_DRF_FAIL_8822C                                         \\\n\t(BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C                                    \\\n\t << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C)\n#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8822C(x)                                 \\\n\t((x) & (~BITS_PCIE_MBIST_DRF_FAIL_8822C))\n#define BIT_GET_PCIE_MBIST_DRF_FAIL_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C) &                        \\\n\t BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C)\n#define BIT_SET_PCIE_MBIST_DRF_FAIL_8822C(x, v)                                \\\n\t(BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8822C(x) |                              \\\n\t BIT_PCIE_MBIST_DRF_FAIL_8822C(v))\n\n#define BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C 0\n#define BIT_MASK_MAC_MBIST_DRF_FAIL_8822C 0x3ffff\n#define BIT_MAC_MBIST_DRF_FAIL_8822C(x)                                        \\\n\t(((x) & BIT_MASK_MAC_MBIST_DRF_FAIL_8822C)                             \\\n\t << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C)\n#define BITS_MAC_MBIST_DRF_FAIL_8822C                                          \\\n\t(BIT_MASK_MAC_MBIST_DRF_FAIL_8822C                                     \\\n\t << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C)\n#define BIT_CLEAR_MAC_MBIST_DRF_FAIL_8822C(x)                                  \\\n\t((x) & (~BITS_MAC_MBIST_DRF_FAIL_8822C))\n#define BIT_GET_MAC_MBIST_DRF_FAIL_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C) &                         \\\n\t BIT_MASK_MAC_MBIST_DRF_FAIL_8822C)\n#define BIT_SET_MAC_MBIST_DRF_FAIL_8822C(x, v)                                 \\\n\t(BIT_CLEAR_MAC_MBIST_DRF_FAIL_8822C(x) |                               \\\n\t BIT_MAC_MBIST_DRF_FAIL_8822C(v))\n\n/* 2 REG_MBIST_START_PAUSE_8822C */\n\n#define BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C 26\n#define BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C 0x3f\n#define BIT_8051_MBIST_START_PAUSE_V1_8822C(x)                                 \\\n\t(((x) & BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C)                      \\\n\t << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C)\n#define BITS_8051_MBIST_START_PAUSE_V1_8822C                                   \\\n\t(BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C                              \\\n\t << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C)\n#define BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8822C(x)                           \\\n\t((x) & (~BITS_8051_MBIST_START_PAUSE_V1_8822C))\n#define BIT_GET_8051_MBIST_START_PAUSE_V1_8822C(x)                             \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C) &                  \\\n\t BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C)\n#define BIT_SET_8051_MBIST_START_PAUSE_V1_8822C(x, v)                          \\\n\t(BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8822C(x) |                        \\\n\t BIT_8051_MBIST_START_PAUSE_V1_8822C(v))\n\n#define BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C 24\n#define BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C 0x3\n#define BIT_USB_MBIST_START_PAUSE_V1_8822C(x)                                  \\\n\t(((x) & BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C)                       \\\n\t << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C)\n#define BITS_USB_MBIST_START_PAUSE_V1_8822C                                    \\\n\t(BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C                               \\\n\t << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C)\n#define BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8822C(x)                            \\\n\t((x) & (~BITS_USB_MBIST_START_PAUSE_V1_8822C))\n#define BIT_GET_USB_MBIST_START_PAUSE_V1_8822C(x)                              \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C) &                   \\\n\t BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C)\n#define BIT_SET_USB_MBIST_START_PAUSE_V1_8822C(x, v)                           \\\n\t(BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8822C(x) |                         \\\n\t BIT_USB_MBIST_START_PAUSE_V1_8822C(v))\n\n#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C 18\n#define BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C 0x3f\n#define BIT_PCIE_MBIST_START_PAUSE_V1_8822C(x)                                 \\\n\t(((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C)                      \\\n\t << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C)\n#define BITS_PCIE_MBIST_START_PAUSE_V1_8822C                                   \\\n\t(BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C                              \\\n\t << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C)\n#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8822C(x)                           \\\n\t((x) & (~BITS_PCIE_MBIST_START_PAUSE_V1_8822C))\n#define BIT_GET_PCIE_MBIST_START_PAUSE_V1_8822C(x)                             \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C) &                  \\\n\t BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C)\n#define BIT_SET_PCIE_MBIST_START_PAUSE_V1_8822C(x, v)                          \\\n\t(BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8822C(x) |                        \\\n\t BIT_PCIE_MBIST_START_PAUSE_V1_8822C(v))\n\n#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C 0\n#define BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C 0x3ffff\n#define BIT_MAC_MBIST_START_PAUSE_V1_8822C(x)                                  \\\n\t(((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C)                       \\\n\t << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C)\n#define BITS_MAC_MBIST_START_PAUSE_V1_8822C                                    \\\n\t(BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C                               \\\n\t << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C)\n#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8822C(x)                            \\\n\t((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8822C))\n#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8822C(x)                              \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C) &                   \\\n\t BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C)\n#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8822C(x, v)                           \\\n\t(BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8822C(x) |                         \\\n\t BIT_MAC_MBIST_START_PAUSE_V1_8822C(v))\n\n/* 2 REG_MBIST_DONE_8822C */\n\n#define BIT_SHIFT_8051_MBIST_DONE_V1_8822C 26\n#define BIT_MASK_8051_MBIST_DONE_V1_8822C 0x3f\n#define BIT_8051_MBIST_DONE_V1_8822C(x)                                        \\\n\t(((x) & BIT_MASK_8051_MBIST_DONE_V1_8822C)                             \\\n\t << BIT_SHIFT_8051_MBIST_DONE_V1_8822C)\n#define BITS_8051_MBIST_DONE_V1_8822C                                          \\\n\t(BIT_MASK_8051_MBIST_DONE_V1_8822C                                     \\\n\t << BIT_SHIFT_8051_MBIST_DONE_V1_8822C)\n#define BIT_CLEAR_8051_MBIST_DONE_V1_8822C(x)                                  \\\n\t((x) & (~BITS_8051_MBIST_DONE_V1_8822C))\n#define BIT_GET_8051_MBIST_DONE_V1_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_8051_MBIST_DONE_V1_8822C) &                         \\\n\t BIT_MASK_8051_MBIST_DONE_V1_8822C)\n#define BIT_SET_8051_MBIST_DONE_V1_8822C(x, v)                                 \\\n\t(BIT_CLEAR_8051_MBIST_DONE_V1_8822C(x) |                               \\\n\t BIT_8051_MBIST_DONE_V1_8822C(v))\n\n#define BIT_SHIFT_USB_MBIST_DONE_V1_8822C 24\n#define BIT_MASK_USB_MBIST_DONE_V1_8822C 0x3\n#define BIT_USB_MBIST_DONE_V1_8822C(x)                                         \\\n\t(((x) & BIT_MASK_USB_MBIST_DONE_V1_8822C)                              \\\n\t << BIT_SHIFT_USB_MBIST_DONE_V1_8822C)\n#define BITS_USB_MBIST_DONE_V1_8822C                                           \\\n\t(BIT_MASK_USB_MBIST_DONE_V1_8822C << BIT_SHIFT_USB_MBIST_DONE_V1_8822C)\n#define BIT_CLEAR_USB_MBIST_DONE_V1_8822C(x)                                   \\\n\t((x) & (~BITS_USB_MBIST_DONE_V1_8822C))\n#define BIT_GET_USB_MBIST_DONE_V1_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_USB_MBIST_DONE_V1_8822C) &                          \\\n\t BIT_MASK_USB_MBIST_DONE_V1_8822C)\n#define BIT_SET_USB_MBIST_DONE_V1_8822C(x, v)                                  \\\n\t(BIT_CLEAR_USB_MBIST_DONE_V1_8822C(x) | BIT_USB_MBIST_DONE_V1_8822C(v))\n\n#define BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C 18\n#define BIT_MASK_PCIE_MBIST_DONE_V1_8822C 0x3f\n#define BIT_PCIE_MBIST_DONE_V1_8822C(x)                                        \\\n\t(((x) & BIT_MASK_PCIE_MBIST_DONE_V1_8822C)                             \\\n\t << BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C)\n#define BITS_PCIE_MBIST_DONE_V1_8822C                                          \\\n\t(BIT_MASK_PCIE_MBIST_DONE_V1_8822C                                     \\\n\t << BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C)\n#define BIT_CLEAR_PCIE_MBIST_DONE_V1_8822C(x)                                  \\\n\t((x) & (~BITS_PCIE_MBIST_DONE_V1_8822C))\n#define BIT_GET_PCIE_MBIST_DONE_V1_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C) &                         \\\n\t BIT_MASK_PCIE_MBIST_DONE_V1_8822C)\n#define BIT_SET_PCIE_MBIST_DONE_V1_8822C(x, v)                                 \\\n\t(BIT_CLEAR_PCIE_MBIST_DONE_V1_8822C(x) |                               \\\n\t BIT_PCIE_MBIST_DONE_V1_8822C(v))\n\n#define BIT_SHIFT_MAC_MBIST_DONE_V1_8822C 0\n#define BIT_MASK_MAC_MBIST_DONE_V1_8822C 0x3ffff\n#define BIT_MAC_MBIST_DONE_V1_8822C(x)                                         \\\n\t(((x) & BIT_MASK_MAC_MBIST_DONE_V1_8822C)                              \\\n\t << BIT_SHIFT_MAC_MBIST_DONE_V1_8822C)\n#define BITS_MAC_MBIST_DONE_V1_8822C                                           \\\n\t(BIT_MASK_MAC_MBIST_DONE_V1_8822C << BIT_SHIFT_MAC_MBIST_DONE_V1_8822C)\n#define BIT_CLEAR_MAC_MBIST_DONE_V1_8822C(x)                                   \\\n\t((x) & (~BITS_MAC_MBIST_DONE_V1_8822C))\n#define BIT_GET_MAC_MBIST_DONE_V1_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8822C) &                          \\\n\t BIT_MASK_MAC_MBIST_DONE_V1_8822C)\n#define BIT_SET_MAC_MBIST_DONE_V1_8822C(x, v)                                  \\\n\t(BIT_CLEAR_MAC_MBIST_DONE_V1_8822C(x) | BIT_MAC_MBIST_DONE_V1_8822C(v))\n\n/* 2 REG_MBIST_READ_BIST_RPT_8822C */\n\n#define BIT_SHIFT_MBIST_READ_BIST_RPT_8822C 0\n#define BIT_MASK_MBIST_READ_BIST_RPT_8822C 0xffffffffL\n#define BIT_MBIST_READ_BIST_RPT_8822C(x)                                       \\\n\t(((x) & BIT_MASK_MBIST_READ_BIST_RPT_8822C)                            \\\n\t << BIT_SHIFT_MBIST_READ_BIST_RPT_8822C)\n#define BITS_MBIST_READ_BIST_RPT_8822C                                         \\\n\t(BIT_MASK_MBIST_READ_BIST_RPT_8822C                                    \\\n\t << BIT_SHIFT_MBIST_READ_BIST_RPT_8822C)\n#define BIT_CLEAR_MBIST_READ_BIST_RPT_8822C(x)                                 \\\n\t((x) & (~BITS_MBIST_READ_BIST_RPT_8822C))\n#define BIT_GET_MBIST_READ_BIST_RPT_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_MBIST_READ_BIST_RPT_8822C) &                        \\\n\t BIT_MASK_MBIST_READ_BIST_RPT_8822C)\n#define BIT_SET_MBIST_READ_BIST_RPT_8822C(x, v)                                \\\n\t(BIT_CLEAR_MBIST_READ_BIST_RPT_8822C(x) |                              \\\n\t BIT_MBIST_READ_BIST_RPT_8822C(v))\n\n/* 2 REG_AES_DECRPT_DATA_8822C */\n\n#define BIT_SHIFT_IPS_CFG_ADDR_8822C 0\n#define BIT_MASK_IPS_CFG_ADDR_8822C 0xff\n#define BIT_IPS_CFG_ADDR_8822C(x)                                              \\\n\t(((x) & BIT_MASK_IPS_CFG_ADDR_8822C) << BIT_SHIFT_IPS_CFG_ADDR_8822C)\n#define BITS_IPS_CFG_ADDR_8822C                                                \\\n\t(BIT_MASK_IPS_CFG_ADDR_8822C << BIT_SHIFT_IPS_CFG_ADDR_8822C)\n#define BIT_CLEAR_IPS_CFG_ADDR_8822C(x) ((x) & (~BITS_IPS_CFG_ADDR_8822C))\n#define BIT_GET_IPS_CFG_ADDR_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_IPS_CFG_ADDR_8822C) & BIT_MASK_IPS_CFG_ADDR_8822C)\n#define BIT_SET_IPS_CFG_ADDR_8822C(x, v)                                       \\\n\t(BIT_CLEAR_IPS_CFG_ADDR_8822C(x) | BIT_IPS_CFG_ADDR_8822C(v))\n\n/* 2 REG_AES_DECRPT_CFG_8822C */\n\n#define BIT_SHIFT_IPS_CFG_DATA_8822C 0\n#define BIT_MASK_IPS_CFG_DATA_8822C 0xffffffffL\n#define BIT_IPS_CFG_DATA_8822C(x)                                              \\\n\t(((x) & BIT_MASK_IPS_CFG_DATA_8822C) << BIT_SHIFT_IPS_CFG_DATA_8822C)\n#define BITS_IPS_CFG_DATA_8822C                                                \\\n\t(BIT_MASK_IPS_CFG_DATA_8822C << BIT_SHIFT_IPS_CFG_DATA_8822C)\n#define BIT_CLEAR_IPS_CFG_DATA_8822C(x) ((x) & (~BITS_IPS_CFG_DATA_8822C))\n#define BIT_GET_IPS_CFG_DATA_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_IPS_CFG_DATA_8822C) & BIT_MASK_IPS_CFG_DATA_8822C)\n#define BIT_SET_IPS_CFG_DATA_8822C(x, v)                                       \\\n\t(BIT_CLEAR_IPS_CFG_DATA_8822C(x) | BIT_IPS_CFG_DATA_8822C(v))\n\n/* 2 REG_HIOE_CTRL_8822C */\n#define BIT_HIOE_CFG_FILE_LOC_SEL_8822C BIT(31)\n#define BIT_HIOE_WRITE_REQ_8822C BIT(30)\n#define BIT_HIOE_READ_REQ_8822C BIT(29)\n#define BIT_INST_FORMAT_ERR_8822C BIT(25)\n#define BIT_OP_TIMEOUT_ERR_8822C BIT(24)\n\n#define BIT_SHIFT_HIOE_OP_TIMEOUT_8822C 16\n#define BIT_MASK_HIOE_OP_TIMEOUT_8822C 0xff\n#define BIT_HIOE_OP_TIMEOUT_8822C(x)                                           \\\n\t(((x) & BIT_MASK_HIOE_OP_TIMEOUT_8822C)                                \\\n\t << BIT_SHIFT_HIOE_OP_TIMEOUT_8822C)\n#define BITS_HIOE_OP_TIMEOUT_8822C                                             \\\n\t(BIT_MASK_HIOE_OP_TIMEOUT_8822C << BIT_SHIFT_HIOE_OP_TIMEOUT_8822C)\n#define BIT_CLEAR_HIOE_OP_TIMEOUT_8822C(x) ((x) & (~BITS_HIOE_OP_TIMEOUT_8822C))\n#define BIT_GET_HIOE_OP_TIMEOUT_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_HIOE_OP_TIMEOUT_8822C) &                            \\\n\t BIT_MASK_HIOE_OP_TIMEOUT_8822C)\n#define BIT_SET_HIOE_OP_TIMEOUT_8822C(x, v)                                    \\\n\t(BIT_CLEAR_HIOE_OP_TIMEOUT_8822C(x) | BIT_HIOE_OP_TIMEOUT_8822C(v))\n\n#define BIT_SHIFT_BITDATA_CHECKSUM_8822C 0\n#define BIT_MASK_BITDATA_CHECKSUM_8822C 0xffff\n#define BIT_BITDATA_CHECKSUM_8822C(x)                                          \\\n\t(((x) & BIT_MASK_BITDATA_CHECKSUM_8822C)                               \\\n\t << BIT_SHIFT_BITDATA_CHECKSUM_8822C)\n#define BITS_BITDATA_CHECKSUM_8822C                                            \\\n\t(BIT_MASK_BITDATA_CHECKSUM_8822C << BIT_SHIFT_BITDATA_CHECKSUM_8822C)\n#define BIT_CLEAR_BITDATA_CHECKSUM_8822C(x)                                    \\\n\t((x) & (~BITS_BITDATA_CHECKSUM_8822C))\n#define BIT_GET_BITDATA_CHECKSUM_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BITDATA_CHECKSUM_8822C) &                           \\\n\t BIT_MASK_BITDATA_CHECKSUM_8822C)\n#define BIT_SET_BITDATA_CHECKSUM_8822C(x, v)                                   \\\n\t(BIT_CLEAR_BITDATA_CHECKSUM_8822C(x) | BIT_BITDATA_CHECKSUM_8822C(v))\n\n/* 2 REG_HIOE_CFG_FILE_8822C */\n\n#define BIT_SHIFT_TXBF_END_ADDR_8822C 16\n#define BIT_MASK_TXBF_END_ADDR_8822C 0xffff\n#define BIT_TXBF_END_ADDR_8822C(x)                                             \\\n\t(((x) & BIT_MASK_TXBF_END_ADDR_8822C) << BIT_SHIFT_TXBF_END_ADDR_8822C)\n#define BITS_TXBF_END_ADDR_8822C                                               \\\n\t(BIT_MASK_TXBF_END_ADDR_8822C << BIT_SHIFT_TXBF_END_ADDR_8822C)\n#define BIT_CLEAR_TXBF_END_ADDR_8822C(x) ((x) & (~BITS_TXBF_END_ADDR_8822C))\n#define BIT_GET_TXBF_END_ADDR_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXBF_END_ADDR_8822C) & BIT_MASK_TXBF_END_ADDR_8822C)\n#define BIT_SET_TXBF_END_ADDR_8822C(x, v)                                      \\\n\t(BIT_CLEAR_TXBF_END_ADDR_8822C(x) | BIT_TXBF_END_ADDR_8822C(v))\n\n#define BIT_SHIFT_TXBF_STR_ADDR_8822C 0\n#define BIT_MASK_TXBF_STR_ADDR_8822C 0xffff\n#define BIT_TXBF_STR_ADDR_8822C(x)                                             \\\n\t(((x) & BIT_MASK_TXBF_STR_ADDR_8822C) << BIT_SHIFT_TXBF_STR_ADDR_8822C)\n#define BITS_TXBF_STR_ADDR_8822C                                               \\\n\t(BIT_MASK_TXBF_STR_ADDR_8822C << BIT_SHIFT_TXBF_STR_ADDR_8822C)\n#define BIT_CLEAR_TXBF_STR_ADDR_8822C(x) ((x) & (~BITS_TXBF_STR_ADDR_8822C))\n#define BIT_GET_TXBF_STR_ADDR_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXBF_STR_ADDR_8822C) & BIT_MASK_TXBF_STR_ADDR_8822C)\n#define BIT_SET_TXBF_STR_ADDR_8822C(x, v)                                      \\\n\t(BIT_CLEAR_TXBF_STR_ADDR_8822C(x) | BIT_TXBF_STR_ADDR_8822C(v))\n\n/* 2 REG_TMETER_8822C */\n#define BIT_TEMP_VALID_8822C BIT(31)\n\n#define BIT_SHIFT_TEMP_VALUE_8822C 24\n#define BIT_MASK_TEMP_VALUE_8822C 0x3f\n#define BIT_TEMP_VALUE_8822C(x)                                                \\\n\t(((x) & BIT_MASK_TEMP_VALUE_8822C) << BIT_SHIFT_TEMP_VALUE_8822C)\n#define BITS_TEMP_VALUE_8822C                                                  \\\n\t(BIT_MASK_TEMP_VALUE_8822C << BIT_SHIFT_TEMP_VALUE_8822C)\n#define BIT_CLEAR_TEMP_VALUE_8822C(x) ((x) & (~BITS_TEMP_VALUE_8822C))\n#define BIT_GET_TEMP_VALUE_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_TEMP_VALUE_8822C) & BIT_MASK_TEMP_VALUE_8822C)\n#define BIT_SET_TEMP_VALUE_8822C(x, v)                                         \\\n\t(BIT_CLEAR_TEMP_VALUE_8822C(x) | BIT_TEMP_VALUE_8822C(v))\n\n#define BIT_SHIFT_REG_TMETER_TIMER_8822C 8\n#define BIT_MASK_REG_TMETER_TIMER_8822C 0xfff\n#define BIT_REG_TMETER_TIMER_8822C(x)                                          \\\n\t(((x) & BIT_MASK_REG_TMETER_TIMER_8822C)                               \\\n\t << BIT_SHIFT_REG_TMETER_TIMER_8822C)\n#define BITS_REG_TMETER_TIMER_8822C                                            \\\n\t(BIT_MASK_REG_TMETER_TIMER_8822C << BIT_SHIFT_REG_TMETER_TIMER_8822C)\n#define BIT_CLEAR_REG_TMETER_TIMER_8822C(x)                                    \\\n\t((x) & (~BITS_REG_TMETER_TIMER_8822C))\n#define BIT_GET_REG_TMETER_TIMER_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_REG_TMETER_TIMER_8822C) &                           \\\n\t BIT_MASK_REG_TMETER_TIMER_8822C)\n#define BIT_SET_REG_TMETER_TIMER_8822C(x, v)                                   \\\n\t(BIT_CLEAR_REG_TMETER_TIMER_8822C(x) | BIT_REG_TMETER_TIMER_8822C(v))\n\n#define BIT_SHIFT_REG_TEMP_DELTA_8822C 2\n#define BIT_MASK_REG_TEMP_DELTA_8822C 0x3f\n#define BIT_REG_TEMP_DELTA_8822C(x)                                            \\\n\t(((x) & BIT_MASK_REG_TEMP_DELTA_8822C)                                 \\\n\t << BIT_SHIFT_REG_TEMP_DELTA_8822C)\n#define BITS_REG_TEMP_DELTA_8822C                                              \\\n\t(BIT_MASK_REG_TEMP_DELTA_8822C << BIT_SHIFT_REG_TEMP_DELTA_8822C)\n#define BIT_CLEAR_REG_TEMP_DELTA_8822C(x) ((x) & (~BITS_REG_TEMP_DELTA_8822C))\n#define BIT_GET_REG_TEMP_DELTA_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_REG_TEMP_DELTA_8822C) &                             \\\n\t BIT_MASK_REG_TEMP_DELTA_8822C)\n#define BIT_SET_REG_TEMP_DELTA_8822C(x, v)                                     \\\n\t(BIT_CLEAR_REG_TEMP_DELTA_8822C(x) | BIT_REG_TEMP_DELTA_8822C(v))\n\n#define BIT_REG_TMETER_EN_8822C BIT(0)\n\n/* 2 REG_OSC_32K_CTRL_8822C */\n\n#define BIT_SHIFT_OSC_32K_CLKGEN_0_8822C 16\n#define BIT_MASK_OSC_32K_CLKGEN_0_8822C 0xffff\n#define BIT_OSC_32K_CLKGEN_0_8822C(x)                                          \\\n\t(((x) & BIT_MASK_OSC_32K_CLKGEN_0_8822C)                               \\\n\t << BIT_SHIFT_OSC_32K_CLKGEN_0_8822C)\n#define BITS_OSC_32K_CLKGEN_0_8822C                                            \\\n\t(BIT_MASK_OSC_32K_CLKGEN_0_8822C << BIT_SHIFT_OSC_32K_CLKGEN_0_8822C)\n#define BIT_CLEAR_OSC_32K_CLKGEN_0_8822C(x)                                    \\\n\t((x) & (~BITS_OSC_32K_CLKGEN_0_8822C))\n#define BIT_GET_OSC_32K_CLKGEN_0_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8822C) &                           \\\n\t BIT_MASK_OSC_32K_CLKGEN_0_8822C)\n#define BIT_SET_OSC_32K_CLKGEN_0_8822C(x, v)                                   \\\n\t(BIT_CLEAR_OSC_32K_CLKGEN_0_8822C(x) | BIT_OSC_32K_CLKGEN_0_8822C(v))\n\n#define BIT_SHIFT_OSC_32K_RES_COMP_8822C 4\n#define BIT_MASK_OSC_32K_RES_COMP_8822C 0x3\n#define BIT_OSC_32K_RES_COMP_8822C(x)                                          \\\n\t(((x) & BIT_MASK_OSC_32K_RES_COMP_8822C)                               \\\n\t << BIT_SHIFT_OSC_32K_RES_COMP_8822C)\n#define BITS_OSC_32K_RES_COMP_8822C                                            \\\n\t(BIT_MASK_OSC_32K_RES_COMP_8822C << BIT_SHIFT_OSC_32K_RES_COMP_8822C)\n#define BIT_CLEAR_OSC_32K_RES_COMP_8822C(x)                                    \\\n\t((x) & (~BITS_OSC_32K_RES_COMP_8822C))\n#define BIT_GET_OSC_32K_RES_COMP_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8822C) &                           \\\n\t BIT_MASK_OSC_32K_RES_COMP_8822C)\n#define BIT_SET_OSC_32K_RES_COMP_8822C(x, v)                                   \\\n\t(BIT_CLEAR_OSC_32K_RES_COMP_8822C(x) | BIT_OSC_32K_RES_COMP_8822C(v))\n\n#define BIT_OSC_32K_OUT_SEL_8822C BIT(3)\n#define BIT_ISO_WL_2_OSC_32K_8822C BIT(1)\n#define BIT_POW_CKGEN_8822C BIT(0)\n\n/* 2 REG_32K_CAL_REG1_8822C */\n#define BIT_CAL_32K_REG_WR_8822C BIT(31)\n#define BIT_CAL_32K_DBG_SEL_8822C BIT(22)\n\n#define BIT_SHIFT_CAL_32K_REG_ADDR_8822C 16\n#define BIT_MASK_CAL_32K_REG_ADDR_8822C 0x3f\n#define BIT_CAL_32K_REG_ADDR_8822C(x)                                          \\\n\t(((x) & BIT_MASK_CAL_32K_REG_ADDR_8822C)                               \\\n\t << BIT_SHIFT_CAL_32K_REG_ADDR_8822C)\n#define BITS_CAL_32K_REG_ADDR_8822C                                            \\\n\t(BIT_MASK_CAL_32K_REG_ADDR_8822C << BIT_SHIFT_CAL_32K_REG_ADDR_8822C)\n#define BIT_CLEAR_CAL_32K_REG_ADDR_8822C(x)                                    \\\n\t((x) & (~BITS_CAL_32K_REG_ADDR_8822C))\n#define BIT_GET_CAL_32K_REG_ADDR_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8822C) &                           \\\n\t BIT_MASK_CAL_32K_REG_ADDR_8822C)\n#define BIT_SET_CAL_32K_REG_ADDR_8822C(x, v)                                   \\\n\t(BIT_CLEAR_CAL_32K_REG_ADDR_8822C(x) | BIT_CAL_32K_REG_ADDR_8822C(v))\n\n#define BIT_SHIFT_CAL_32K_REG_DATA_8822C 0\n#define BIT_MASK_CAL_32K_REG_DATA_8822C 0xffff\n#define BIT_CAL_32K_REG_DATA_8822C(x)                                          \\\n\t(((x) & BIT_MASK_CAL_32K_REG_DATA_8822C)                               \\\n\t << BIT_SHIFT_CAL_32K_REG_DATA_8822C)\n#define BITS_CAL_32K_REG_DATA_8822C                                            \\\n\t(BIT_MASK_CAL_32K_REG_DATA_8822C << BIT_SHIFT_CAL_32K_REG_DATA_8822C)\n#define BIT_CLEAR_CAL_32K_REG_DATA_8822C(x)                                    \\\n\t((x) & (~BITS_CAL_32K_REG_DATA_8822C))\n#define BIT_GET_CAL_32K_REG_DATA_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8822C) &                           \\\n\t BIT_MASK_CAL_32K_REG_DATA_8822C)\n#define BIT_SET_CAL_32K_REG_DATA_8822C(x, v)                                   \\\n\t(BIT_CLEAR_CAL_32K_REG_DATA_8822C(x) | BIT_CAL_32K_REG_DATA_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_C2HEVT_8822C */\n\n#define BIT_SHIFT_C2HEVT_MSG_V1_8822C 0\n#define BIT_MASK_C2HEVT_MSG_V1_8822C 0xffffffffL\n#define BIT_C2HEVT_MSG_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_V1_8822C) << BIT_SHIFT_C2HEVT_MSG_V1_8822C)\n#define BITS_C2HEVT_MSG_V1_8822C                                               \\\n\t(BIT_MASK_C2HEVT_MSG_V1_8822C << BIT_SHIFT_C2HEVT_MSG_V1_8822C)\n#define BIT_CLEAR_C2HEVT_MSG_V1_8822C(x) ((x) & (~BITS_C2HEVT_MSG_V1_8822C))\n#define BIT_GET_C2HEVT_MSG_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8822C) & BIT_MASK_C2HEVT_MSG_V1_8822C)\n#define BIT_SET_C2HEVT_MSG_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_C2HEVT_MSG_V1_8822C(x) | BIT_C2HEVT_MSG_V1_8822C(v))\n\n/* 2 REG_C2HEVT_1_8822C */\n\n#define BIT_SHIFT_C2HEVT_MSG_1_8822C 0\n#define BIT_MASK_C2HEVT_MSG_1_8822C 0xffffffffL\n#define BIT_C2HEVT_MSG_1_8822C(x)                                              \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_1_8822C) << BIT_SHIFT_C2HEVT_MSG_1_8822C)\n#define BITS_C2HEVT_MSG_1_8822C                                                \\\n\t(BIT_MASK_C2HEVT_MSG_1_8822C << BIT_SHIFT_C2HEVT_MSG_1_8822C)\n#define BIT_CLEAR_C2HEVT_MSG_1_8822C(x) ((x) & (~BITS_C2HEVT_MSG_1_8822C))\n#define BIT_GET_C2HEVT_MSG_1_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_1_8822C) & BIT_MASK_C2HEVT_MSG_1_8822C)\n#define BIT_SET_C2HEVT_MSG_1_8822C(x, v)                                       \\\n\t(BIT_CLEAR_C2HEVT_MSG_1_8822C(x) | BIT_C2HEVT_MSG_1_8822C(v))\n\n/* 2 REG_C2HEVT_2_8822C */\n\n#define BIT_SHIFT_C2HEVT_MSG_2_8822C 0\n#define BIT_MASK_C2HEVT_MSG_2_8822C 0xffffffffL\n#define BIT_C2HEVT_MSG_2_8822C(x)                                              \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_2_8822C) << BIT_SHIFT_C2HEVT_MSG_2_8822C)\n#define BITS_C2HEVT_MSG_2_8822C                                                \\\n\t(BIT_MASK_C2HEVT_MSG_2_8822C << BIT_SHIFT_C2HEVT_MSG_2_8822C)\n#define BIT_CLEAR_C2HEVT_MSG_2_8822C(x) ((x) & (~BITS_C2HEVT_MSG_2_8822C))\n#define BIT_GET_C2HEVT_MSG_2_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_2_8822C) & BIT_MASK_C2HEVT_MSG_2_8822C)\n#define BIT_SET_C2HEVT_MSG_2_8822C(x, v)                                       \\\n\t(BIT_CLEAR_C2HEVT_MSG_2_8822C(x) | BIT_C2HEVT_MSG_2_8822C(v))\n\n/* 2 REG_C2HEVT_3_8822C */\n\n#define BIT_SHIFT_C2HEVT_MSG_3_8822C 0\n#define BIT_MASK_C2HEVT_MSG_3_8822C 0xffffffffL\n#define BIT_C2HEVT_MSG_3_8822C(x)                                              \\\n\t(((x) & BIT_MASK_C2HEVT_MSG_3_8822C) << BIT_SHIFT_C2HEVT_MSG_3_8822C)\n#define BITS_C2HEVT_MSG_3_8822C                                                \\\n\t(BIT_MASK_C2HEVT_MSG_3_8822C << BIT_SHIFT_C2HEVT_MSG_3_8822C)\n#define BIT_CLEAR_C2HEVT_MSG_3_8822C(x) ((x) & (~BITS_C2HEVT_MSG_3_8822C))\n#define BIT_GET_C2HEVT_MSG_3_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_C2HEVT_MSG_3_8822C) & BIT_MASK_C2HEVT_MSG_3_8822C)\n#define BIT_SET_C2HEVT_MSG_3_8822C(x, v)                                       \\\n\t(BIT_CLEAR_C2HEVT_MSG_3_8822C(x) | BIT_C2HEVT_MSG_3_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_SW_DEFINED_PAGE1_8822C */\n\n#define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C 0\n#define BIT_MASK_SW_DEFINED_PAGE1_V1_8822C 0xffffffffL\n#define BIT_SW_DEFINED_PAGE1_V1_8822C(x)                                       \\\n\t(((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8822C)                            \\\n\t << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C)\n#define BITS_SW_DEFINED_PAGE1_V1_8822C                                         \\\n\t(BIT_MASK_SW_DEFINED_PAGE1_V1_8822C                                    \\\n\t << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C)\n#define BIT_CLEAR_SW_DEFINED_PAGE1_V1_8822C(x)                                 \\\n\t((x) & (~BITS_SW_DEFINED_PAGE1_V1_8822C))\n#define BIT_GET_SW_DEFINED_PAGE1_V1_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C) &                        \\\n\t BIT_MASK_SW_DEFINED_PAGE1_V1_8822C)\n#define BIT_SET_SW_DEFINED_PAGE1_V1_8822C(x, v)                                \\\n\t(BIT_CLEAR_SW_DEFINED_PAGE1_V1_8822C(x) |                              \\\n\t BIT_SW_DEFINED_PAGE1_V1_8822C(v))\n\n/* 2 REG_SW_DEFINED_PAGE2_8822C */\n\n#define BIT_SHIFT_SW_DEFINED_PAGE2_8822C 0\n#define BIT_MASK_SW_DEFINED_PAGE2_8822C 0xffffffffL\n#define BIT_SW_DEFINED_PAGE2_8822C(x)                                          \\\n\t(((x) & BIT_MASK_SW_DEFINED_PAGE2_8822C)                               \\\n\t << BIT_SHIFT_SW_DEFINED_PAGE2_8822C)\n#define BITS_SW_DEFINED_PAGE2_8822C                                            \\\n\t(BIT_MASK_SW_DEFINED_PAGE2_8822C << BIT_SHIFT_SW_DEFINED_PAGE2_8822C)\n#define BIT_CLEAR_SW_DEFINED_PAGE2_8822C(x)                                    \\\n\t((x) & (~BITS_SW_DEFINED_PAGE2_8822C))\n#define BIT_GET_SW_DEFINED_PAGE2_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8822C) &                           \\\n\t BIT_MASK_SW_DEFINED_PAGE2_8822C)\n#define BIT_SET_SW_DEFINED_PAGE2_8822C(x, v)                                   \\\n\t(BIT_CLEAR_SW_DEFINED_PAGE2_8822C(x) | BIT_SW_DEFINED_PAGE2_8822C(v))\n\n/* 2 REG_MCUTST_I_8822C */\n\n#define BIT_SHIFT_MCUDMSG_I_8822C 0\n#define BIT_MASK_MCUDMSG_I_8822C 0xffffffffL\n#define BIT_MCUDMSG_I_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_MCUDMSG_I_8822C) << BIT_SHIFT_MCUDMSG_I_8822C)\n#define BITS_MCUDMSG_I_8822C                                                   \\\n\t(BIT_MASK_MCUDMSG_I_8822C << BIT_SHIFT_MCUDMSG_I_8822C)\n#define BIT_CLEAR_MCUDMSG_I_8822C(x) ((x) & (~BITS_MCUDMSG_I_8822C))\n#define BIT_GET_MCUDMSG_I_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MCUDMSG_I_8822C) & BIT_MASK_MCUDMSG_I_8822C)\n#define BIT_SET_MCUDMSG_I_8822C(x, v)                                          \\\n\t(BIT_CLEAR_MCUDMSG_I_8822C(x) | BIT_MCUDMSG_I_8822C(v))\n\n/* 2 REG_MCUTST_II_8822C */\n\n#define BIT_SHIFT_MCUDMSG_II_8822C 0\n#define BIT_MASK_MCUDMSG_II_8822C 0xffffffffL\n#define BIT_MCUDMSG_II_8822C(x)                                                \\\n\t(((x) & BIT_MASK_MCUDMSG_II_8822C) << BIT_SHIFT_MCUDMSG_II_8822C)\n#define BITS_MCUDMSG_II_8822C                                                  \\\n\t(BIT_MASK_MCUDMSG_II_8822C << BIT_SHIFT_MCUDMSG_II_8822C)\n#define BIT_CLEAR_MCUDMSG_II_8822C(x) ((x) & (~BITS_MCUDMSG_II_8822C))\n#define BIT_GET_MCUDMSG_II_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_MCUDMSG_II_8822C) & BIT_MASK_MCUDMSG_II_8822C)\n#define BIT_SET_MCUDMSG_II_8822C(x, v)                                         \\\n\t(BIT_CLEAR_MCUDMSG_II_8822C(x) | BIT_MCUDMSG_II_8822C(v))\n\n/* 2 REG_FMETHR_8822C */\n#define BIT_FMSG_INT_8822C BIT(31)\n\n#define BIT_SHIFT_FW_MSG_8822C 0\n#define BIT_MASK_FW_MSG_8822C 0xffffffffL\n#define BIT_FW_MSG_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_FW_MSG_8822C) << BIT_SHIFT_FW_MSG_8822C)\n#define BITS_FW_MSG_8822C (BIT_MASK_FW_MSG_8822C << BIT_SHIFT_FW_MSG_8822C)\n#define BIT_CLEAR_FW_MSG_8822C(x) ((x) & (~BITS_FW_MSG_8822C))\n#define BIT_GET_FW_MSG_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_FW_MSG_8822C) & BIT_MASK_FW_MSG_8822C)\n#define BIT_SET_FW_MSG_8822C(x, v)                                             \\\n\t(BIT_CLEAR_FW_MSG_8822C(x) | BIT_FW_MSG_8822C(v))\n\n/* 2 REG_HMETFR_8822C */\n\n#define BIT_SHIFT_HRCV_MSG_8822C 24\n#define BIT_MASK_HRCV_MSG_8822C 0xff\n#define BIT_HRCV_MSG_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_HRCV_MSG_8822C) << BIT_SHIFT_HRCV_MSG_8822C)\n#define BITS_HRCV_MSG_8822C                                                    \\\n\t(BIT_MASK_HRCV_MSG_8822C << BIT_SHIFT_HRCV_MSG_8822C)\n#define BIT_CLEAR_HRCV_MSG_8822C(x) ((x) & (~BITS_HRCV_MSG_8822C))\n#define BIT_GET_HRCV_MSG_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_HRCV_MSG_8822C) & BIT_MASK_HRCV_MSG_8822C)\n#define BIT_SET_HRCV_MSG_8822C(x, v)                                           \\\n\t(BIT_CLEAR_HRCV_MSG_8822C(x) | BIT_HRCV_MSG_8822C(v))\n\n#define BIT_INT_BOX3_8822C BIT(3)\n#define BIT_INT_BOX2_8822C BIT(2)\n#define BIT_INT_BOX1_8822C BIT(1)\n#define BIT_INT_BOX0_8822C BIT(0)\n\n/* 2 REG_HMEBOX0_8822C */\n\n#define BIT_SHIFT_HOST_MSG_0_8822C 0\n#define BIT_MASK_HOST_MSG_0_8822C 0xffffffffL\n#define BIT_HOST_MSG_0_8822C(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_0_8822C) << BIT_SHIFT_HOST_MSG_0_8822C)\n#define BITS_HOST_MSG_0_8822C                                                  \\\n\t(BIT_MASK_HOST_MSG_0_8822C << BIT_SHIFT_HOST_MSG_0_8822C)\n#define BIT_CLEAR_HOST_MSG_0_8822C(x) ((x) & (~BITS_HOST_MSG_0_8822C))\n#define BIT_GET_HOST_MSG_0_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_0_8822C) & BIT_MASK_HOST_MSG_0_8822C)\n#define BIT_SET_HOST_MSG_0_8822C(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_0_8822C(x) | BIT_HOST_MSG_0_8822C(v))\n\n/* 2 REG_HMEBOX1_8822C */\n\n#define BIT_SHIFT_HOST_MSG_1_8822C 0\n#define BIT_MASK_HOST_MSG_1_8822C 0xffffffffL\n#define BIT_HOST_MSG_1_8822C(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_1_8822C) << BIT_SHIFT_HOST_MSG_1_8822C)\n#define BITS_HOST_MSG_1_8822C                                                  \\\n\t(BIT_MASK_HOST_MSG_1_8822C << BIT_SHIFT_HOST_MSG_1_8822C)\n#define BIT_CLEAR_HOST_MSG_1_8822C(x) ((x) & (~BITS_HOST_MSG_1_8822C))\n#define BIT_GET_HOST_MSG_1_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_1_8822C) & BIT_MASK_HOST_MSG_1_8822C)\n#define BIT_SET_HOST_MSG_1_8822C(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_1_8822C(x) | BIT_HOST_MSG_1_8822C(v))\n\n/* 2 REG_HMEBOX2_8822C */\n\n#define BIT_SHIFT_HOST_MSG_2_8822C 0\n#define BIT_MASK_HOST_MSG_2_8822C 0xffffffffL\n#define BIT_HOST_MSG_2_8822C(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_2_8822C) << BIT_SHIFT_HOST_MSG_2_8822C)\n#define BITS_HOST_MSG_2_8822C                                                  \\\n\t(BIT_MASK_HOST_MSG_2_8822C << BIT_SHIFT_HOST_MSG_2_8822C)\n#define BIT_CLEAR_HOST_MSG_2_8822C(x) ((x) & (~BITS_HOST_MSG_2_8822C))\n#define BIT_GET_HOST_MSG_2_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_2_8822C) & BIT_MASK_HOST_MSG_2_8822C)\n#define BIT_SET_HOST_MSG_2_8822C(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_2_8822C(x) | BIT_HOST_MSG_2_8822C(v))\n\n/* 2 REG_HMEBOX3_8822C */\n\n#define BIT_SHIFT_HOST_MSG_3_8822C 0\n#define BIT_MASK_HOST_MSG_3_8822C 0xffffffffL\n#define BIT_HOST_MSG_3_8822C(x)                                                \\\n\t(((x) & BIT_MASK_HOST_MSG_3_8822C) << BIT_SHIFT_HOST_MSG_3_8822C)\n#define BITS_HOST_MSG_3_8822C                                                  \\\n\t(BIT_MASK_HOST_MSG_3_8822C << BIT_SHIFT_HOST_MSG_3_8822C)\n#define BIT_CLEAR_HOST_MSG_3_8822C(x) ((x) & (~BITS_HOST_MSG_3_8822C))\n#define BIT_GET_HOST_MSG_3_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_HOST_MSG_3_8822C) & BIT_MASK_HOST_MSG_3_8822C)\n#define BIT_SET_HOST_MSG_3_8822C(x, v)                                         \\\n\t(BIT_CLEAR_HOST_MSG_3_8822C(x) | BIT_HOST_MSG_3_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_BB_ACCESS_CTRL_8822C */\n\n#define BIT_SHIFT_BB_WRITE_READ_8822C 30\n#define BIT_MASK_BB_WRITE_READ_8822C 0x3\n#define BIT_BB_WRITE_READ_8822C(x)                                             \\\n\t(((x) & BIT_MASK_BB_WRITE_READ_8822C) << BIT_SHIFT_BB_WRITE_READ_8822C)\n#define BITS_BB_WRITE_READ_8822C                                               \\\n\t(BIT_MASK_BB_WRITE_READ_8822C << BIT_SHIFT_BB_WRITE_READ_8822C)\n#define BIT_CLEAR_BB_WRITE_READ_8822C(x) ((x) & (~BITS_BB_WRITE_READ_8822C))\n#define BIT_GET_BB_WRITE_READ_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BB_WRITE_READ_8822C) & BIT_MASK_BB_WRITE_READ_8822C)\n#define BIT_SET_BB_WRITE_READ_8822C(x, v)                                      \\\n\t(BIT_CLEAR_BB_WRITE_READ_8822C(x) | BIT_BB_WRITE_READ_8822C(v))\n\n#define BIT_SHIFT_BB_WRITE_EN_8822C 12\n#define BIT_MASK_BB_WRITE_EN_8822C 0xf\n#define BIT_BB_WRITE_EN_8822C(x)                                               \\\n\t(((x) & BIT_MASK_BB_WRITE_EN_8822C) << BIT_SHIFT_BB_WRITE_EN_8822C)\n#define BITS_BB_WRITE_EN_8822C                                                 \\\n\t(BIT_MASK_BB_WRITE_EN_8822C << BIT_SHIFT_BB_WRITE_EN_8822C)\n#define BIT_CLEAR_BB_WRITE_EN_8822C(x) ((x) & (~BITS_BB_WRITE_EN_8822C))\n#define BIT_GET_BB_WRITE_EN_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_BB_WRITE_EN_8822C) & BIT_MASK_BB_WRITE_EN_8822C)\n#define BIT_SET_BB_WRITE_EN_8822C(x, v)                                        \\\n\t(BIT_CLEAR_BB_WRITE_EN_8822C(x) | BIT_BB_WRITE_EN_8822C(v))\n\n#define BIT_SHIFT_BB_ADDR_8822C 2\n#define BIT_MASK_BB_ADDR_8822C 0x1ff\n#define BIT_BB_ADDR_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_BB_ADDR_8822C) << BIT_SHIFT_BB_ADDR_8822C)\n#define BITS_BB_ADDR_8822C (BIT_MASK_BB_ADDR_8822C << BIT_SHIFT_BB_ADDR_8822C)\n#define BIT_CLEAR_BB_ADDR_8822C(x) ((x) & (~BITS_BB_ADDR_8822C))\n#define BIT_GET_BB_ADDR_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_BB_ADDR_8822C) & BIT_MASK_BB_ADDR_8822C)\n#define BIT_SET_BB_ADDR_8822C(x, v)                                            \\\n\t(BIT_CLEAR_BB_ADDR_8822C(x) | BIT_BB_ADDR_8822C(v))\n\n#define BIT_BB_ERRACC_8822C BIT(0)\n\n/* 2 REG_BB_ACCESS_DATA_8822C */\n\n#define BIT_SHIFT_BB_DATA_8822C 0\n#define BIT_MASK_BB_DATA_8822C 0xffffffffL\n#define BIT_BB_DATA_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_BB_DATA_8822C) << BIT_SHIFT_BB_DATA_8822C)\n#define BITS_BB_DATA_8822C (BIT_MASK_BB_DATA_8822C << BIT_SHIFT_BB_DATA_8822C)\n#define BIT_CLEAR_BB_DATA_8822C(x) ((x) & (~BITS_BB_DATA_8822C))\n#define BIT_GET_BB_DATA_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_BB_DATA_8822C) & BIT_MASK_BB_DATA_8822C)\n#define BIT_SET_BB_DATA_8822C(x, v)                                            \\\n\t(BIT_CLEAR_BB_DATA_8822C(x) | BIT_BB_DATA_8822C(v))\n\n/* 2 REG_HMEBOX_E0_8822C */\n\n#define BIT_SHIFT_HMEBOX_E0_8822C 0\n#define BIT_MASK_HMEBOX_E0_8822C 0xffffffffL\n#define BIT_HMEBOX_E0_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E0_8822C) << BIT_SHIFT_HMEBOX_E0_8822C)\n#define BITS_HMEBOX_E0_8822C                                                   \\\n\t(BIT_MASK_HMEBOX_E0_8822C << BIT_SHIFT_HMEBOX_E0_8822C)\n#define BIT_CLEAR_HMEBOX_E0_8822C(x) ((x) & (~BITS_HMEBOX_E0_8822C))\n#define BIT_GET_HMEBOX_E0_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E0_8822C) & BIT_MASK_HMEBOX_E0_8822C)\n#define BIT_SET_HMEBOX_E0_8822C(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E0_8822C(x) | BIT_HMEBOX_E0_8822C(v))\n\n/* 2 REG_HMEBOX_E1_8822C */\n\n#define BIT_SHIFT_HMEBOX_E1_8822C 0\n#define BIT_MASK_HMEBOX_E1_8822C 0xffffffffL\n#define BIT_HMEBOX_E1_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E1_8822C) << BIT_SHIFT_HMEBOX_E1_8822C)\n#define BITS_HMEBOX_E1_8822C                                                   \\\n\t(BIT_MASK_HMEBOX_E1_8822C << BIT_SHIFT_HMEBOX_E1_8822C)\n#define BIT_CLEAR_HMEBOX_E1_8822C(x) ((x) & (~BITS_HMEBOX_E1_8822C))\n#define BIT_GET_HMEBOX_E1_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E1_8822C) & BIT_MASK_HMEBOX_E1_8822C)\n#define BIT_SET_HMEBOX_E1_8822C(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E1_8822C(x) | BIT_HMEBOX_E1_8822C(v))\n\n/* 2 REG_HMEBOX_E2_8822C */\n\n#define BIT_SHIFT_HMEBOX_E2_8822C 0\n#define BIT_MASK_HMEBOX_E2_8822C 0xffffffffL\n#define BIT_HMEBOX_E2_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E2_8822C) << BIT_SHIFT_HMEBOX_E2_8822C)\n#define BITS_HMEBOX_E2_8822C                                                   \\\n\t(BIT_MASK_HMEBOX_E2_8822C << BIT_SHIFT_HMEBOX_E2_8822C)\n#define BIT_CLEAR_HMEBOX_E2_8822C(x) ((x) & (~BITS_HMEBOX_E2_8822C))\n#define BIT_GET_HMEBOX_E2_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E2_8822C) & BIT_MASK_HMEBOX_E2_8822C)\n#define BIT_SET_HMEBOX_E2_8822C(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E2_8822C(x) | BIT_HMEBOX_E2_8822C(v))\n\n/* 2 REG_HMEBOX_E3_8822C */\n\n#define BIT_SHIFT_HMEBOX_E3_8822C 0\n#define BIT_MASK_HMEBOX_E3_8822C 0xffffffffL\n#define BIT_HMEBOX_E3_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_HMEBOX_E3_8822C) << BIT_SHIFT_HMEBOX_E3_8822C)\n#define BITS_HMEBOX_E3_8822C                                                   \\\n\t(BIT_MASK_HMEBOX_E3_8822C << BIT_SHIFT_HMEBOX_E3_8822C)\n#define BIT_CLEAR_HMEBOX_E3_8822C(x) ((x) & (~BITS_HMEBOX_E3_8822C))\n#define BIT_GET_HMEBOX_E3_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_HMEBOX_E3_8822C) & BIT_MASK_HMEBOX_E3_8822C)\n#define BIT_SET_HMEBOX_E3_8822C(x, v)                                          \\\n\t(BIT_CLEAR_HMEBOX_E3_8822C(x) | BIT_HMEBOX_E3_8822C(v))\n\n/* 2 REG_CR_EXT_8822C */\n\n#define BIT_SHIFT_PHY_REQ_DELAY_8822C 24\n#define BIT_MASK_PHY_REQ_DELAY_8822C 0xf\n#define BIT_PHY_REQ_DELAY_8822C(x)                                             \\\n\t(((x) & BIT_MASK_PHY_REQ_DELAY_8822C) << BIT_SHIFT_PHY_REQ_DELAY_8822C)\n#define BITS_PHY_REQ_DELAY_8822C                                               \\\n\t(BIT_MASK_PHY_REQ_DELAY_8822C << BIT_SHIFT_PHY_REQ_DELAY_8822C)\n#define BIT_CLEAR_PHY_REQ_DELAY_8822C(x) ((x) & (~BITS_PHY_REQ_DELAY_8822C))\n#define BIT_GET_PHY_REQ_DELAY_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PHY_REQ_DELAY_8822C) & BIT_MASK_PHY_REQ_DELAY_8822C)\n#define BIT_SET_PHY_REQ_DELAY_8822C(x, v)                                      \\\n\t(BIT_CLEAR_PHY_REQ_DELAY_8822C(x) | BIT_PHY_REQ_DELAY_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_SPD_DOWN_8822C BIT(16)\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_NETYPE4_8822C 4\n#define BIT_MASK_NETYPE4_8822C 0x3\n#define BIT_NETYPE4_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE4_8822C) << BIT_SHIFT_NETYPE4_8822C)\n#define BITS_NETYPE4_8822C (BIT_MASK_NETYPE4_8822C << BIT_SHIFT_NETYPE4_8822C)\n#define BIT_CLEAR_NETYPE4_8822C(x) ((x) & (~BITS_NETYPE4_8822C))\n#define BIT_GET_NETYPE4_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE4_8822C) & BIT_MASK_NETYPE4_8822C)\n#define BIT_SET_NETYPE4_8822C(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE4_8822C(x) | BIT_NETYPE4_8822C(v))\n\n#define BIT_SHIFT_NETYPE3_8822C 2\n#define BIT_MASK_NETYPE3_8822C 0x3\n#define BIT_NETYPE3_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE3_8822C) << BIT_SHIFT_NETYPE3_8822C)\n#define BITS_NETYPE3_8822C (BIT_MASK_NETYPE3_8822C << BIT_SHIFT_NETYPE3_8822C)\n#define BIT_CLEAR_NETYPE3_8822C(x) ((x) & (~BITS_NETYPE3_8822C))\n#define BIT_GET_NETYPE3_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE3_8822C) & BIT_MASK_NETYPE3_8822C)\n#define BIT_SET_NETYPE3_8822C(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE3_8822C(x) | BIT_NETYPE3_8822C(v))\n\n#define BIT_SHIFT_NETYPE2_8822C 0\n#define BIT_MASK_NETYPE2_8822C 0x3\n#define BIT_NETYPE2_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_NETYPE2_8822C) << BIT_SHIFT_NETYPE2_8822C)\n#define BITS_NETYPE2_8822C (BIT_MASK_NETYPE2_8822C << BIT_SHIFT_NETYPE2_8822C)\n#define BIT_CLEAR_NETYPE2_8822C(x) ((x) & (~BITS_NETYPE2_8822C))\n#define BIT_GET_NETYPE2_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_NETYPE2_8822C) & BIT_MASK_NETYPE2_8822C)\n#define BIT_SET_NETYPE2_8822C(x, v)                                            \\\n\t(BIT_CLEAR_NETYPE2_8822C(x) | BIT_NETYPE2_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_FWFF_8822C */\n\n#define BIT_SHIFT_PKTNUM_TH_V1_8822C 24\n#define BIT_MASK_PKTNUM_TH_V1_8822C 0xff\n#define BIT_PKTNUM_TH_V1_8822C(x)                                              \\\n\t(((x) & BIT_MASK_PKTNUM_TH_V1_8822C) << BIT_SHIFT_PKTNUM_TH_V1_8822C)\n#define BITS_PKTNUM_TH_V1_8822C                                                \\\n\t(BIT_MASK_PKTNUM_TH_V1_8822C << BIT_SHIFT_PKTNUM_TH_V1_8822C)\n#define BIT_CLEAR_PKTNUM_TH_V1_8822C(x) ((x) & (~BITS_PKTNUM_TH_V1_8822C))\n#define BIT_GET_PKTNUM_TH_V1_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_PKTNUM_TH_V1_8822C) & BIT_MASK_PKTNUM_TH_V1_8822C)\n#define BIT_SET_PKTNUM_TH_V1_8822C(x, v)                                       \\\n\t(BIT_CLEAR_PKTNUM_TH_V1_8822C(x) | BIT_PKTNUM_TH_V1_8822C(v))\n\n#define BIT_SHIFT_TIMER_TH_8822C 16\n#define BIT_MASK_TIMER_TH_8822C 0xff\n#define BIT_TIMER_TH_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_TIMER_TH_8822C) << BIT_SHIFT_TIMER_TH_8822C)\n#define BITS_TIMER_TH_8822C                                                    \\\n\t(BIT_MASK_TIMER_TH_8822C << BIT_SHIFT_TIMER_TH_8822C)\n#define BIT_CLEAR_TIMER_TH_8822C(x) ((x) & (~BITS_TIMER_TH_8822C))\n#define BIT_GET_TIMER_TH_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TIMER_TH_8822C) & BIT_MASK_TIMER_TH_8822C)\n#define BIT_SET_TIMER_TH_8822C(x, v)                                           \\\n\t(BIT_CLEAR_TIMER_TH_8822C(x) | BIT_TIMER_TH_8822C(v))\n\n#define BIT_SHIFT_RXPKT1ENADDR_8822C 0\n#define BIT_MASK_RXPKT1ENADDR_8822C 0xffff\n#define BIT_RXPKT1ENADDR_8822C(x)                                              \\\n\t(((x) & BIT_MASK_RXPKT1ENADDR_8822C) << BIT_SHIFT_RXPKT1ENADDR_8822C)\n#define BITS_RXPKT1ENADDR_8822C                                                \\\n\t(BIT_MASK_RXPKT1ENADDR_8822C << BIT_SHIFT_RXPKT1ENADDR_8822C)\n#define BIT_CLEAR_RXPKT1ENADDR_8822C(x) ((x) & (~BITS_RXPKT1ENADDR_8822C))\n#define BIT_GET_RXPKT1ENADDR_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXPKT1ENADDR_8822C) & BIT_MASK_RXPKT1ENADDR_8822C)\n#define BIT_SET_RXPKT1ENADDR_8822C(x, v)                                       \\\n\t(BIT_CLEAR_RXPKT1ENADDR_8822C(x) | BIT_RXPKT1ENADDR_8822C(v))\n\n/* 2 REG_RXFF_PTR_V1_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_RXFF0_RDPTR_V2_8822C 0\n#define BIT_MASK_RXFF0_RDPTR_V2_8822C 0x3ffff\n#define BIT_RXFF0_RDPTR_V2_8822C(x)                                            \\\n\t(((x) & BIT_MASK_RXFF0_RDPTR_V2_8822C)                                 \\\n\t << BIT_SHIFT_RXFF0_RDPTR_V2_8822C)\n#define BITS_RXFF0_RDPTR_V2_8822C                                              \\\n\t(BIT_MASK_RXFF0_RDPTR_V2_8822C << BIT_SHIFT_RXFF0_RDPTR_V2_8822C)\n#define BIT_CLEAR_RXFF0_RDPTR_V2_8822C(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8822C))\n#define BIT_GET_RXFF0_RDPTR_V2_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8822C) &                             \\\n\t BIT_MASK_RXFF0_RDPTR_V2_8822C)\n#define BIT_SET_RXFF0_RDPTR_V2_8822C(x, v)                                     \\\n\t(BIT_CLEAR_RXFF0_RDPTR_V2_8822C(x) | BIT_RXFF0_RDPTR_V2_8822C(v))\n\n/* 2 REG_RXFF_WTR_V1_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_RXFF0_WTPTR_V2_8822C 0\n#define BIT_MASK_RXFF0_WTPTR_V2_8822C 0x3ffff\n#define BIT_RXFF0_WTPTR_V2_8822C(x)                                            \\\n\t(((x) & BIT_MASK_RXFF0_WTPTR_V2_8822C)                                 \\\n\t << BIT_SHIFT_RXFF0_WTPTR_V2_8822C)\n#define BITS_RXFF0_WTPTR_V2_8822C                                              \\\n\t(BIT_MASK_RXFF0_WTPTR_V2_8822C << BIT_SHIFT_RXFF0_WTPTR_V2_8822C)\n#define BIT_CLEAR_RXFF0_WTPTR_V2_8822C(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8822C))\n#define BIT_GET_RXFF0_WTPTR_V2_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8822C) &                             \\\n\t BIT_MASK_RXFF0_WTPTR_V2_8822C)\n#define BIT_SET_RXFF0_WTPTR_V2_8822C(x, v)                                     \\\n\t(BIT_CLEAR_RXFF0_WTPTR_V2_8822C(x) | BIT_RXFF0_WTPTR_V2_8822C(v))\n\n/* 2 REG_FE2IMR_8822C */\n#define BIT__FE4ISR__IND_MSK_8822C BIT(29)\n#define BIT_FS_TXSC_DESC_DONE_INT_EN_8822C BIT(28)\n#define BIT_FS_TXSC_BKDONE_INT_EN_8822C BIT(27)\n#define BIT_FS_TXSC_BEDONE_INT_EN_8822C BIT(26)\n#define BIT_FS_TXSC_VIDONE_INT_EN_8822C BIT(25)\n#define BIT_FS_TXSC_VODONE_INT_EN_8822C BIT(24)\n#define BIT_FS_ATIM_MB7_INT_EN_8822C BIT(23)\n#define BIT_FS_ATIM_MB6_INT_EN_8822C BIT(22)\n#define BIT_FS_ATIM_MB5_INT_EN_8822C BIT(21)\n#define BIT_FS_ATIM_MB4_INT_EN_8822C BIT(20)\n#define BIT_FS_ATIM_MB3_INT_EN_8822C BIT(19)\n#define BIT_FS_ATIM_MB2_INT_EN_8822C BIT(18)\n#define BIT_FS_ATIM_MB1_INT_EN_8822C BIT(17)\n#define BIT_FS_ATIM_MB0_INT_EN_8822C BIT(16)\n#define BIT_FS_TBTT4INT_EN_8822C BIT(11)\n#define BIT_FS_TBTT3INT_EN_8822C BIT(10)\n#define BIT_FS_TBTT2INT_EN_8822C BIT(9)\n#define BIT_FS_TBTT1INT_EN_8822C BIT(8)\n#define BIT_FS_TBTT0_MB7INT_EN_8822C BIT(7)\n#define BIT_FS_TBTT0_MB6INT_EN_8822C BIT(6)\n#define BIT_FS_TBTT0_MB5INT_EN_8822C BIT(5)\n#define BIT_FS_TBTT0_MB4INT_EN_8822C BIT(4)\n#define BIT_FS_TBTT0_MB3INT_EN_8822C BIT(3)\n#define BIT_FS_TBTT0_MB2INT_EN_8822C BIT(2)\n#define BIT_FS_TBTT0_MB1INT_EN_8822C BIT(1)\n#define BIT_FS_TBTT0_INT_EN_8822C BIT(0)\n\n/* 2 REG_FE2ISR_8822C */\n#define BIT__FE4ISR__IND_INT_8822C BIT(29)\n#define BIT_FS_TXSC_DESC_DONE_INT_8822C BIT(28)\n#define BIT_FS_TXSC_BKDONE_INT_8822C BIT(27)\n#define BIT_FS_TXSC_BEDONE_INT_8822C BIT(26)\n#define BIT_FS_TXSC_VIDONE_INT_8822C BIT(25)\n#define BIT_FS_TXSC_VODONE_INT_8822C BIT(24)\n#define BIT_FS_ATIM_MB7_INT_8822C BIT(23)\n#define BIT_FS_ATIM_MB6_INT_8822C BIT(22)\n#define BIT_FS_ATIM_MB5_INT_8822C BIT(21)\n#define BIT_FS_ATIM_MB4_INT_8822C BIT(20)\n#define BIT_FS_ATIM_MB3_INT_8822C BIT(19)\n#define BIT_FS_ATIM_MB2_INT_8822C BIT(18)\n#define BIT_FS_ATIM_MB1_INT_8822C BIT(17)\n#define BIT_FS_ATIM_MB0_INT_8822C BIT(16)\n#define BIT_FS_TBTT4INT_8822C BIT(11)\n#define BIT_FS_TBTT3INT_8822C BIT(10)\n#define BIT_FS_TBTT2INT_8822C BIT(9)\n#define BIT_FS_TBTT1INT_8822C BIT(8)\n#define BIT_FS_TBTT0_MB7INT_8822C BIT(7)\n#define BIT_FS_TBTT0_MB6INT_8822C BIT(6)\n#define BIT_FS_TBTT0_MB5INT_8822C BIT(5)\n#define BIT_FS_TBTT0_MB4INT_8822C BIT(4)\n#define BIT_FS_TBTT0_MB3INT_8822C BIT(3)\n#define BIT_FS_TBTT0_MB2INT_8822C BIT(2)\n#define BIT_FS_TBTT0_MB1INT_8822C BIT(1)\n#define BIT_FS_TBTT0_INT_8822C BIT(0)\n\n/* 2 REG_FE3IMR_8822C */\n#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN_8822C BIT(31)\n#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN_8822C BIT(30)\n#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN_8822C BIT(29)\n#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN_8822C BIT(28)\n#define BIT_FS_BCNDMA4_INT_EN_8822C BIT(27)\n#define BIT_FS_BCNDMA3_INT_EN_8822C BIT(26)\n#define BIT_FS_BCNDMA2_INT_EN_8822C BIT(25)\n#define BIT_FS_BCNDMA1_INT_EN_8822C BIT(24)\n#define BIT_FS_BCNDMA0_MB7_INT_EN_8822C BIT(23)\n#define BIT_FS_BCNDMA0_MB6_INT_EN_8822C BIT(22)\n#define BIT_FS_BCNDMA0_MB5_INT_EN_8822C BIT(21)\n#define BIT_FS_BCNDMA0_MB4_INT_EN_8822C BIT(20)\n#define BIT_FS_BCNDMA0_MB3_INT_EN_8822C BIT(19)\n#define BIT_FS_BCNDMA0_MB2_INT_EN_8822C BIT(18)\n#define BIT_FS_BCNDMA0_MB1_INT_EN_8822C BIT(17)\n#define BIT_FS_BCNDMA0_INT_EN_8822C BIT(16)\n#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8822C BIT(15)\n#define BIT_FS_BCNERLY4_INT_EN_8822C BIT(11)\n#define BIT_FS_BCNERLY3_INT_EN_8822C BIT(10)\n#define BIT_FS_BCNERLY2_INT_EN_8822C BIT(9)\n#define BIT_FS_BCNERLY1_INT_EN_8822C BIT(8)\n#define BIT_FS_BCNERLY0_MB7INT_EN_8822C BIT(7)\n#define BIT_FS_BCNERLY0_MB6INT_EN_8822C BIT(6)\n#define BIT_FS_BCNERLY0_MB5INT_EN_8822C BIT(5)\n#define BIT_FS_BCNERLY0_MB4INT_EN_8822C BIT(4)\n#define BIT_FS_BCNERLY0_MB3INT_EN_8822C BIT(3)\n#define BIT_FS_BCNERLY0_MB2INT_EN_8822C BIT(2)\n#define BIT_FS_BCNERLY0_MB1INT_EN_8822C BIT(1)\n#define BIT_FS_BCNERLY0_INT_EN_8822C BIT(0)\n\n/* 2 REG_FE3ISR_8822C */\n#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT_8822C BIT(31)\n#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT_8822C BIT(30)\n#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT_8822C BIT(29)\n#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT_8822C BIT(28)\n#define BIT_FS_BCNDMA4_INT_8822C BIT(27)\n#define BIT_FS_BCNDMA3_INT_8822C BIT(26)\n#define BIT_FS_BCNDMA2_INT_8822C BIT(25)\n#define BIT_FS_BCNDMA1_INT_8822C BIT(24)\n#define BIT_FS_BCNDMA0_MB7_INT_8822C BIT(23)\n#define BIT_FS_BCNDMA0_MB6_INT_8822C BIT(22)\n#define BIT_FS_BCNDMA0_MB5_INT_8822C BIT(21)\n#define BIT_FS_BCNDMA0_MB4_INT_8822C BIT(20)\n#define BIT_FS_BCNDMA0_MB3_INT_8822C BIT(19)\n#define BIT_FS_BCNDMA0_MB2_INT_8822C BIT(18)\n#define BIT_FS_BCNDMA0_MB1_INT_8822C BIT(17)\n#define BIT_FS_BCNDMA0_INT_8822C BIT(16)\n#define BIT_FS_MTI_BCNIVLEAR_INT_8822C BIT(15)\n#define BIT_FS_BCNERLY4_INT_8822C BIT(11)\n#define BIT_FS_BCNERLY3_INT_8822C BIT(10)\n#define BIT_FS_BCNERLY2_INT_8822C BIT(9)\n#define BIT_FS_BCNERLY1_INT_8822C BIT(8)\n#define BIT_FS_BCNERLY0_MB7INT_8822C BIT(7)\n#define BIT_FS_BCNERLY0_MB6INT_8822C BIT(6)\n#define BIT_FS_BCNERLY0_MB5INT_8822C BIT(5)\n#define BIT_FS_BCNERLY0_MB4INT_8822C BIT(4)\n#define BIT_FS_BCNERLY0_MB3INT_8822C BIT(3)\n#define BIT_FS_BCNERLY0_MB2INT_8822C BIT(2)\n#define BIT_FS_BCNERLY0_MB1INT_8822C BIT(1)\n#define BIT_FS_BCNERLY0_INT_8822C BIT(0)\n\n/* 2 REG_FE4IMR_8822C */\n#define BIT_FS_CLI3_TXPKTIN_INT_EN_8822C BIT(19)\n#define BIT_FS_CLI2_TXPKTIN_INT_EN_8822C BIT(18)\n#define BIT_FS_CLI1_TXPKTIN_INT_EN_8822C BIT(17)\n#define BIT_FS_CLI0_TXPKTIN_INT_EN_8822C BIT(16)\n#define BIT_FS_CLI3_RX_UMD0_INT_EN_8822C BIT(15)\n#define BIT_FS_CLI3_RX_UMD1_INT_EN_8822C BIT(14)\n#define BIT_FS_CLI3_RX_BMD0_INT_EN_8822C BIT(13)\n#define BIT_FS_CLI3_RX_BMD1_INT_EN_8822C BIT(12)\n#define BIT_FS_CLI2_RX_UMD0_INT_EN_8822C BIT(11)\n#define BIT_FS_CLI2_RX_UMD1_INT_EN_8822C BIT(10)\n#define BIT_FS_CLI2_RX_BMD0_INT_EN_8822C BIT(9)\n#define BIT_FS_CLI2_RX_BMD1_INT_EN_8822C BIT(8)\n#define BIT_FS_CLI1_RX_UMD0_INT_EN_8822C BIT(7)\n#define BIT_FS_CLI1_RX_UMD1_INT_EN_8822C BIT(6)\n#define BIT_FS_CLI1_RX_BMD0_INT_EN_8822C BIT(5)\n#define BIT_FS_CLI1_RX_BMD1_INT_EN_8822C BIT(4)\n#define BIT_FS_CLI0_RX_UMD0_INT_EN_8822C BIT(3)\n#define BIT_FS_CLI0_RX_UMD1_INT_EN_8822C BIT(2)\n#define BIT_FS_CLI0_RX_BMD0_INT_EN_8822C BIT(1)\n#define BIT_FS_CLI0_RX_BMD1_INT_EN_8822C BIT(0)\n\n/* 2 REG_FE4ISR_8822C */\n#define BIT_FS_CLI3_TXPKTIN_INT_8822C BIT(19)\n#define BIT_FS_CLI2_TXPKTIN_INT_8822C BIT(18)\n#define BIT_FS_CLI1_TXPKTIN_INT_8822C BIT(17)\n#define BIT_FS_CLI0_TXPKTIN_INT_8822C BIT(16)\n#define BIT_FS_CLI3_RX_UMD0_INT_8822C BIT(15)\n#define BIT_FS_CLI3_RX_UMD1_INT_8822C BIT(14)\n#define BIT_FS_CLI3_RX_BMD0_INT_8822C BIT(13)\n#define BIT_FS_CLI3_RX_BMD1_INT_8822C BIT(12)\n#define BIT_FS_CLI2_RX_UMD0_INT_8822C BIT(11)\n#define BIT_FS_CLI2_RX_UMD1_INT_8822C BIT(10)\n#define BIT_FS_CLI2_RX_BMD0_INT_8822C BIT(9)\n#define BIT_FS_CLI2_RX_BMD1_INT_8822C BIT(8)\n#define BIT_FS_CLI1_RX_UMD0_INT_8822C BIT(7)\n#define BIT_FS_CLI1_RX_UMD1_INT_8822C BIT(6)\n#define BIT_FS_CLI1_RX_BMD0_INT_8822C BIT(5)\n#define BIT_FS_CLI1_RX_BMD1_INT_8822C BIT(4)\n#define BIT_FS_CLI0_RX_UMD0_INT_8822C BIT(3)\n#define BIT_FS_CLI0_RX_UMD1_INT_8822C BIT(2)\n#define BIT_FS_CLI0_RX_BMD0_INT_8822C BIT(1)\n#define BIT_FS_CLI0_RX_BMD1_INT_8822C BIT(0)\n\n/* 2 REG_FT1IMR_8822C */\n#define BIT__FT2ISR__IND_MSK_8822C BIT(30)\n#define BIT_FTM_PTT_INT_EN_8822C BIT(29)\n#define BIT_RXFTMREQ_INT_EN_8822C BIT(28)\n#define BIT_RXFTM_INT_EN_8822C BIT(27)\n#define BIT_TXFTM_INT_EN_8822C BIT(26)\n#define BIT_FS_H2C_CMD_OK_INT_EN_8822C BIT(25)\n#define BIT_FS_H2C_CMD_FULL_INT_EN_8822C BIT(24)\n#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8822C BIT(23)\n#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8822C BIT(22)\n#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8822C BIT(21)\n#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8822C BIT(20)\n#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8822C BIT(19)\n#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8822C BIT(18)\n#define BIT_FS_CTWEND2_INT_EN_8822C BIT(17)\n#define BIT_FS_CTWEND1_INT_EN_8822C BIT(16)\n#define BIT_FS_CTWEND0_INT_EN_8822C BIT(15)\n#define BIT_FS_TX_NULL1_INT_EN_8822C BIT(14)\n#define BIT_FS_TX_NULL0_INT_EN_8822C BIT(13)\n#define BIT_FS_TSF_BIT32_TOGGLE_EN_8822C BIT(12)\n#define BIT_FS_P2P_RFON2_INT_EN_8822C BIT(11)\n#define BIT_FS_P2P_RFOFF2_INT_EN_8822C BIT(10)\n#define BIT_FS_P2P_RFON1_INT_EN_8822C BIT(9)\n#define BIT_FS_P2P_RFOFF1_INT_EN_8822C BIT(8)\n#define BIT_FS_P2P_RFON0_INT_EN_8822C BIT(7)\n#define BIT_FS_P2P_RFOFF0_INT_EN_8822C BIT(6)\n#define BIT_FS_RX_UAPSDMD1_EN_8822C BIT(5)\n#define BIT_FS_RX_UAPSDMD0_EN_8822C BIT(4)\n#define BIT_FS_TRIGGER_PKT_EN_8822C BIT(3)\n#define BIT_FS_EOSP_INT_EN_8822C BIT(2)\n#define BIT_FS_RPWM2_INT_EN_8822C BIT(1)\n#define BIT_FS_RPWM_INT_EN_8822C BIT(0)\n\n/* 2 REG_FT1ISR_8822C */\n#define BIT__FT2ISR__IND_INT_8822C BIT(30)\n#define BIT_FTM_PTT_INT_8822C BIT(29)\n#define BIT_RXFTMREQ_INT_8822C BIT(28)\n#define BIT_RXFTM_INT_8822C BIT(27)\n#define BIT_TXFTM_INT_8822C BIT(26)\n#define BIT_FS_H2C_CMD_OK_INT_8822C BIT(25)\n#define BIT_FS_H2C_CMD_FULL_INT_8822C BIT(24)\n#define BIT_FS_MACID_PWRCHANGE5_INT_8822C BIT(23)\n#define BIT_FS_MACID_PWRCHANGE4_INT_8822C BIT(22)\n#define BIT_FS_MACID_PWRCHANGE3_INT_8822C BIT(21)\n#define BIT_FS_MACID_PWRCHANGE2_INT_8822C BIT(20)\n#define BIT_FS_MACID_PWRCHANGE1_INT_8822C BIT(19)\n#define BIT_FS_MACID_PWRCHANGE0_INT_8822C BIT(18)\n#define BIT_FS_CTWEND2_INT_8822C BIT(17)\n#define BIT_FS_CTWEND1_INT_8822C BIT(16)\n#define BIT_FS_CTWEND0_INT_8822C BIT(15)\n#define BIT_FS_TX_NULL1_INT_8822C BIT(14)\n#define BIT_FS_TX_NULL0_INT_8822C BIT(13)\n#define BIT_FS_TSF_BIT32_TOGGLE_INT_8822C BIT(12)\n#define BIT_FS_P2P_RFON2_INT_8822C BIT(11)\n#define BIT_FS_P2P_RFOFF2_INT_8822C BIT(10)\n#define BIT_FS_P2P_RFON1_INT_8822C BIT(9)\n#define BIT_FS_P2P_RFOFF1_INT_8822C BIT(8)\n#define BIT_FS_P2P_RFON0_INT_8822C BIT(7)\n#define BIT_FS_P2P_RFOFF0_INT_8822C BIT(6)\n#define BIT_FS_RX_UAPSDMD1_INT_8822C BIT(5)\n#define BIT_FS_RX_UAPSDMD0_INT_8822C BIT(4)\n#define BIT_FS_TRIGGER_PKT_INT_8822C BIT(3)\n#define BIT_FS_EOSP_INT_8822C BIT(2)\n#define BIT_FS_RPWM2_INT_8822C BIT(1)\n#define BIT_FS_RPWM_INT_8822C BIT(0)\n\n/* 2 REG_SPWR0_8822C */\n\n#define BIT_SHIFT_MID_31TO0_8822C 0\n#define BIT_MASK_MID_31TO0_8822C 0xffffffffL\n#define BIT_MID_31TO0_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_MID_31TO0_8822C) << BIT_SHIFT_MID_31TO0_8822C)\n#define BITS_MID_31TO0_8822C                                                   \\\n\t(BIT_MASK_MID_31TO0_8822C << BIT_SHIFT_MID_31TO0_8822C)\n#define BIT_CLEAR_MID_31TO0_8822C(x) ((x) & (~BITS_MID_31TO0_8822C))\n#define BIT_GET_MID_31TO0_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MID_31TO0_8822C) & BIT_MASK_MID_31TO0_8822C)\n#define BIT_SET_MID_31TO0_8822C(x, v)                                          \\\n\t(BIT_CLEAR_MID_31TO0_8822C(x) | BIT_MID_31TO0_8822C(v))\n\n/* 2 REG_SPWR1_8822C */\n\n#define BIT_SHIFT_MID_63TO32_8822C 0\n#define BIT_MASK_MID_63TO32_8822C 0xffffffffL\n#define BIT_MID_63TO32_8822C(x)                                                \\\n\t(((x) & BIT_MASK_MID_63TO32_8822C) << BIT_SHIFT_MID_63TO32_8822C)\n#define BITS_MID_63TO32_8822C                                                  \\\n\t(BIT_MASK_MID_63TO32_8822C << BIT_SHIFT_MID_63TO32_8822C)\n#define BIT_CLEAR_MID_63TO32_8822C(x) ((x) & (~BITS_MID_63TO32_8822C))\n#define BIT_GET_MID_63TO32_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_MID_63TO32_8822C) & BIT_MASK_MID_63TO32_8822C)\n#define BIT_SET_MID_63TO32_8822C(x, v)                                         \\\n\t(BIT_CLEAR_MID_63TO32_8822C(x) | BIT_MID_63TO32_8822C(v))\n\n/* 2 REG_SPWR2_8822C */\n\n#define BIT_SHIFT_MID_95O64_8822C 0\n#define BIT_MASK_MID_95O64_8822C 0xffffffffL\n#define BIT_MID_95O64_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_MID_95O64_8822C) << BIT_SHIFT_MID_95O64_8822C)\n#define BITS_MID_95O64_8822C                                                   \\\n\t(BIT_MASK_MID_95O64_8822C << BIT_SHIFT_MID_95O64_8822C)\n#define BIT_CLEAR_MID_95O64_8822C(x) ((x) & (~BITS_MID_95O64_8822C))\n#define BIT_GET_MID_95O64_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MID_95O64_8822C) & BIT_MASK_MID_95O64_8822C)\n#define BIT_SET_MID_95O64_8822C(x, v)                                          \\\n\t(BIT_CLEAR_MID_95O64_8822C(x) | BIT_MID_95O64_8822C(v))\n\n/* 2 REG_SPWR3_8822C */\n\n#define BIT_SHIFT_MID_127TO96_8822C 0\n#define BIT_MASK_MID_127TO96_8822C 0xffffffffL\n#define BIT_MID_127TO96_8822C(x)                                               \\\n\t(((x) & BIT_MASK_MID_127TO96_8822C) << BIT_SHIFT_MID_127TO96_8822C)\n#define BITS_MID_127TO96_8822C                                                 \\\n\t(BIT_MASK_MID_127TO96_8822C << BIT_SHIFT_MID_127TO96_8822C)\n#define BIT_CLEAR_MID_127TO96_8822C(x) ((x) & (~BITS_MID_127TO96_8822C))\n#define BIT_GET_MID_127TO96_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_MID_127TO96_8822C) & BIT_MASK_MID_127TO96_8822C)\n#define BIT_SET_MID_127TO96_8822C(x, v)                                        \\\n\t(BIT_CLEAR_MID_127TO96_8822C(x) | BIT_MID_127TO96_8822C(v))\n\n/* 2 REG_POWSEQ_8822C */\n\n#define BIT_SHIFT_SEQNUM_MID_8822C 16\n#define BIT_MASK_SEQNUM_MID_8822C 0xffff\n#define BIT_SEQNUM_MID_8822C(x)                                                \\\n\t(((x) & BIT_MASK_SEQNUM_MID_8822C) << BIT_SHIFT_SEQNUM_MID_8822C)\n#define BITS_SEQNUM_MID_8822C                                                  \\\n\t(BIT_MASK_SEQNUM_MID_8822C << BIT_SHIFT_SEQNUM_MID_8822C)\n#define BIT_CLEAR_SEQNUM_MID_8822C(x) ((x) & (~BITS_SEQNUM_MID_8822C))\n#define BIT_GET_SEQNUM_MID_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_SEQNUM_MID_8822C) & BIT_MASK_SEQNUM_MID_8822C)\n#define BIT_SET_SEQNUM_MID_8822C(x, v)                                         \\\n\t(BIT_CLEAR_SEQNUM_MID_8822C(x) | BIT_SEQNUM_MID_8822C(v))\n\n#define BIT_SHIFT_REF_MID_8822C 0\n#define BIT_MASK_REF_MID_8822C 0x7f\n#define BIT_REF_MID_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_REF_MID_8822C) << BIT_SHIFT_REF_MID_8822C)\n#define BITS_REF_MID_8822C (BIT_MASK_REF_MID_8822C << BIT_SHIFT_REF_MID_8822C)\n#define BIT_CLEAR_REF_MID_8822C(x) ((x) & (~BITS_REF_MID_8822C))\n#define BIT_GET_REF_MID_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_REF_MID_8822C) & BIT_MASK_REF_MID_8822C)\n#define BIT_SET_REF_MID_8822C(x, v)                                            \\\n\t(BIT_CLEAR_REF_MID_8822C(x) | BIT_REF_MID_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_TC7_CTRL_V1_8822C */\n#define BIT_TC7INT_EN_8822C BIT(26)\n#define BIT_TC7MODE_8822C BIT(25)\n#define BIT_TC7EN_8822C BIT(24)\n\n#define BIT_SHIFT_TC7DATA_8822C 0\n#define BIT_MASK_TC7DATA_8822C 0xffffff\n#define BIT_TC7DATA_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_TC7DATA_8822C) << BIT_SHIFT_TC7DATA_8822C)\n#define BITS_TC7DATA_8822C (BIT_MASK_TC7DATA_8822C << BIT_SHIFT_TC7DATA_8822C)\n#define BIT_CLEAR_TC7DATA_8822C(x) ((x) & (~BITS_TC7DATA_8822C))\n#define BIT_GET_TC7DATA_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC7DATA_8822C) & BIT_MASK_TC7DATA_8822C)\n#define BIT_SET_TC7DATA_8822C(x, v)                                            \\\n\t(BIT_CLEAR_TC7DATA_8822C(x) | BIT_TC7DATA_8822C(v))\n\n/* 2 REG_TC8_CTRL_V1_8822C */\n#define BIT_TC8INT_EN_8822C BIT(26)\n#define BIT_TC8MODE_8822C BIT(25)\n#define BIT_TC8EN_8822C BIT(24)\n\n#define BIT_SHIFT_TC8DATA_8822C 0\n#define BIT_MASK_TC8DATA_8822C 0xffffff\n#define BIT_TC8DATA_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_TC8DATA_8822C) << BIT_SHIFT_TC8DATA_8822C)\n#define BITS_TC8DATA_8822C (BIT_MASK_TC8DATA_8822C << BIT_SHIFT_TC8DATA_8822C)\n#define BIT_CLEAR_TC8DATA_8822C(x) ((x) & (~BITS_TC8DATA_8822C))\n#define BIT_GET_TC8DATA_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_TC8DATA_8822C) & BIT_MASK_TC8DATA_8822C)\n#define BIT_SET_TC8DATA_8822C(x, v)                                            \\\n\t(BIT_CLEAR_TC8DATA_8822C(x) | BIT_TC8DATA_8822C(v))\n\n/* 2 REG_RX_BCN_TBTT_ITVL0_8822C */\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C 24\n#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C 0xff\n#define BIT_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x)                                  \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C)                       \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C)\n#define BITS_RX_BCN_TBTT_ITVL_CLIENT2_8822C                                    \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C                               \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x)                            \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2_8822C))\n#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x)                              \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C) &                   \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C)\n#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x, v)                           \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x) |                         \\\n\t BIT_RX_BCN_TBTT_ITVL_CLIENT2_8822C(v))\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C 16\n#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C 0xff\n#define BIT_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x)                                  \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C)                       \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C)\n#define BITS_RX_BCN_TBTT_ITVL_CLIENT1_8822C                                    \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C                               \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x)                            \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1_8822C))\n#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x)                              \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C) &                   \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C)\n#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x, v)                           \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x) |                         \\\n\t BIT_RX_BCN_TBTT_ITVL_CLIENT1_8822C(v))\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C 8\n#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C 0xff\n#define BIT_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x)                                  \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C)                       \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C)\n#define BITS_RX_BCN_TBTT_ITVL_CLIENT0_8822C                                    \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C                               \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x)                            \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0_8822C))\n#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x)                              \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C) &                   \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C)\n#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x, v)                           \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x) |                         \\\n\t BIT_RX_BCN_TBTT_ITVL_CLIENT0_8822C(v))\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C 0\n#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C 0xff\n#define BIT_RX_BCN_TBTT_ITVL_PORT0_8822C(x)                                    \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C)                         \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C)\n#define BITS_RX_BCN_TBTT_ITVL_PORT0_8822C                                      \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C                                 \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8822C(x)                              \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0_8822C))\n#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0_8822C(x)                                \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C) &                     \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C)\n#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0_8822C(x, v)                             \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8822C(x) |                           \\\n\t BIT_RX_BCN_TBTT_ITVL_PORT0_8822C(v))\n\n/* 2 REG_RX_BCN_TBTT_ITVL1_8822C */\n\n#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C 0\n#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C 0xff\n#define BIT_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x)                                  \\\n\t(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C)                       \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C)\n#define BITS_RX_BCN_TBTT_ITVL_CLIENT3_8822C                                    \\\n\t(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C                               \\\n\t << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C)\n#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x)                            \\\n\t((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3_8822C))\n#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x)                              \\\n\t(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C) &                   \\\n\t BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C)\n#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x, v)                           \\\n\t(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x) |                         \\\n\t BIT_RX_BCN_TBTT_ITVL_CLIENT3_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_IO_WRAP_ERR_FLAG_8822C */\n#define BIT_IO_WRAP_ERR_8822C BIT(0)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_SPEED_SENSOR_8822C */\n#define BIT_DSS_1_RST_N_8822C BIT(31)\n#define BIT_DSS_1_SPEED_EN_8822C BIT(30)\n#define BIT_DSS_1_WIRE_SEL_8822C BIT(29)\n#define BIT_DSS_ENCLK_8822C BIT(28)\n\n#define BIT_SHIFT_DSS_1_RO_SEL_8822C 24\n#define BIT_MASK_DSS_1_RO_SEL_8822C 0x7\n#define BIT_DSS_1_RO_SEL_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DSS_1_RO_SEL_8822C) << BIT_SHIFT_DSS_1_RO_SEL_8822C)\n#define BITS_DSS_1_RO_SEL_8822C                                                \\\n\t(BIT_MASK_DSS_1_RO_SEL_8822C << BIT_SHIFT_DSS_1_RO_SEL_8822C)\n#define BIT_CLEAR_DSS_1_RO_SEL_8822C(x) ((x) & (~BITS_DSS_1_RO_SEL_8822C))\n#define BIT_GET_DSS_1_RO_SEL_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DSS_1_RO_SEL_8822C) & BIT_MASK_DSS_1_RO_SEL_8822C)\n#define BIT_SET_DSS_1_RO_SEL_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DSS_1_RO_SEL_8822C(x) | BIT_DSS_1_RO_SEL_8822C(v))\n\n#define BIT_SHIFT_DSS_1_DATA_IN_8822C 0\n#define BIT_MASK_DSS_1_DATA_IN_8822C 0xfffff\n#define BIT_DSS_1_DATA_IN_8822C(x)                                             \\\n\t(((x) & BIT_MASK_DSS_1_DATA_IN_8822C) << BIT_SHIFT_DSS_1_DATA_IN_8822C)\n#define BITS_DSS_1_DATA_IN_8822C                                               \\\n\t(BIT_MASK_DSS_1_DATA_IN_8822C << BIT_SHIFT_DSS_1_DATA_IN_8822C)\n#define BIT_CLEAR_DSS_1_DATA_IN_8822C(x) ((x) & (~BITS_DSS_1_DATA_IN_8822C))\n#define BIT_GET_DSS_1_DATA_IN_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_DSS_1_DATA_IN_8822C) & BIT_MASK_DSS_1_DATA_IN_8822C)\n#define BIT_SET_DSS_1_DATA_IN_8822C(x, v)                                      \\\n\t(BIT_CLEAR_DSS_1_DATA_IN_8822C(x) | BIT_DSS_1_DATA_IN_8822C(v))\n\n/* 2 REG_SPEED_SENSOR1_8822C */\n#define BIT_DSS_1_READY_8822C BIT(31)\n#define BIT_DSS_1_WSORT_GO_8822C BIT(30)\n\n#define BIT_SHIFT_DSS_1_COUNT_OUT_8822C 0\n#define BIT_MASK_DSS_1_COUNT_OUT_8822C 0xfffff\n#define BIT_DSS_1_COUNT_OUT_8822C(x)                                           \\\n\t(((x) & BIT_MASK_DSS_1_COUNT_OUT_8822C)                                \\\n\t << BIT_SHIFT_DSS_1_COUNT_OUT_8822C)\n#define BITS_DSS_1_COUNT_OUT_8822C                                             \\\n\t(BIT_MASK_DSS_1_COUNT_OUT_8822C << BIT_SHIFT_DSS_1_COUNT_OUT_8822C)\n#define BIT_CLEAR_DSS_1_COUNT_OUT_8822C(x) ((x) & (~BITS_DSS_1_COUNT_OUT_8822C))\n#define BIT_GET_DSS_1_COUNT_OUT_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DSS_1_COUNT_OUT_8822C) &                            \\\n\t BIT_MASK_DSS_1_COUNT_OUT_8822C)\n#define BIT_SET_DSS_1_COUNT_OUT_8822C(x, v)                                    \\\n\t(BIT_CLEAR_DSS_1_COUNT_OUT_8822C(x) | BIT_DSS_1_COUNT_OUT_8822C(v))\n\n/* 2 REG_SPEED_SENSOR2_8822C */\n#define BIT_DSS_2_RST_N_8822C BIT(31)\n#define BIT_DSS_2_SPEED_EN_8822C BIT(30)\n#define BIT_DSS_2_WIRE_SEL_8822C BIT(29)\n#define BIT_DSS_ENCLK_8822C BIT(28)\n\n#define BIT_SHIFT_DSS_2_RO_SEL_8822C 24\n#define BIT_MASK_DSS_2_RO_SEL_8822C 0x7\n#define BIT_DSS_2_RO_SEL_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DSS_2_RO_SEL_8822C) << BIT_SHIFT_DSS_2_RO_SEL_8822C)\n#define BITS_DSS_2_RO_SEL_8822C                                                \\\n\t(BIT_MASK_DSS_2_RO_SEL_8822C << BIT_SHIFT_DSS_2_RO_SEL_8822C)\n#define BIT_CLEAR_DSS_2_RO_SEL_8822C(x) ((x) & (~BITS_DSS_2_RO_SEL_8822C))\n#define BIT_GET_DSS_2_RO_SEL_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DSS_2_RO_SEL_8822C) & BIT_MASK_DSS_2_RO_SEL_8822C)\n#define BIT_SET_DSS_2_RO_SEL_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DSS_2_RO_SEL_8822C(x) | BIT_DSS_2_RO_SEL_8822C(v))\n\n#define BIT_SHIFT_DSS_2_DATA_IN_8822C 0\n#define BIT_MASK_DSS_2_DATA_IN_8822C 0xfffff\n#define BIT_DSS_2_DATA_IN_8822C(x)                                             \\\n\t(((x) & BIT_MASK_DSS_2_DATA_IN_8822C) << BIT_SHIFT_DSS_2_DATA_IN_8822C)\n#define BITS_DSS_2_DATA_IN_8822C                                               \\\n\t(BIT_MASK_DSS_2_DATA_IN_8822C << BIT_SHIFT_DSS_2_DATA_IN_8822C)\n#define BIT_CLEAR_DSS_2_DATA_IN_8822C(x) ((x) & (~BITS_DSS_2_DATA_IN_8822C))\n#define BIT_GET_DSS_2_DATA_IN_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_DSS_2_DATA_IN_8822C) & BIT_MASK_DSS_2_DATA_IN_8822C)\n#define BIT_SET_DSS_2_DATA_IN_8822C(x, v)                                      \\\n\t(BIT_CLEAR_DSS_2_DATA_IN_8822C(x) | BIT_DSS_2_DATA_IN_8822C(v))\n\n/* 2 REG_SPEED_SENSOR3_8822C */\n#define BIT_DSS_2_READY_8822C BIT(31)\n#define BIT_DSS_2_WSORT_GO_8822C BIT(30)\n\n#define BIT_SHIFT_DSS_2_COUNT_OUT_8822C 0\n#define BIT_MASK_DSS_2_COUNT_OUT_8822C 0xfffff\n#define BIT_DSS_2_COUNT_OUT_8822C(x)                                           \\\n\t(((x) & BIT_MASK_DSS_2_COUNT_OUT_8822C)                                \\\n\t << BIT_SHIFT_DSS_2_COUNT_OUT_8822C)\n#define BITS_DSS_2_COUNT_OUT_8822C                                             \\\n\t(BIT_MASK_DSS_2_COUNT_OUT_8822C << BIT_SHIFT_DSS_2_COUNT_OUT_8822C)\n#define BIT_CLEAR_DSS_2_COUNT_OUT_8822C(x) ((x) & (~BITS_DSS_2_COUNT_OUT_8822C))\n#define BIT_GET_DSS_2_COUNT_OUT_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DSS_2_COUNT_OUT_8822C) &                            \\\n\t BIT_MASK_DSS_2_COUNT_OUT_8822C)\n#define BIT_SET_DSS_2_COUNT_OUT_8822C(x, v)                                    \\\n\t(BIT_CLEAR_DSS_2_COUNT_OUT_8822C(x) | BIT_DSS_2_COUNT_OUT_8822C(v))\n\n/* 2 REG_SPEED_SENSOR4_8822C */\n#define BIT_DSS_3_RST_N_8822C BIT(31)\n#define BIT_DSS_3_SPEED_EN_8822C BIT(30)\n#define BIT_DSS_3_WIRE_SEL_8822C BIT(29)\n#define BIT_DSS_ENCLK_8822C BIT(28)\n\n#define BIT_SHIFT_DSS_3_RO_SEL_8822C 24\n#define BIT_MASK_DSS_3_RO_SEL_8822C 0x7\n#define BIT_DSS_3_RO_SEL_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DSS_3_RO_SEL_8822C) << BIT_SHIFT_DSS_3_RO_SEL_8822C)\n#define BITS_DSS_3_RO_SEL_8822C                                                \\\n\t(BIT_MASK_DSS_3_RO_SEL_8822C << BIT_SHIFT_DSS_3_RO_SEL_8822C)\n#define BIT_CLEAR_DSS_3_RO_SEL_8822C(x) ((x) & (~BITS_DSS_3_RO_SEL_8822C))\n#define BIT_GET_DSS_3_RO_SEL_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DSS_3_RO_SEL_8822C) & BIT_MASK_DSS_3_RO_SEL_8822C)\n#define BIT_SET_DSS_3_RO_SEL_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DSS_3_RO_SEL_8822C(x) | BIT_DSS_3_RO_SEL_8822C(v))\n\n#define BIT_SHIFT_DSS_3_DATA_IN_8822C 0\n#define BIT_MASK_DSS_3_DATA_IN_8822C 0xfffff\n#define BIT_DSS_3_DATA_IN_8822C(x)                                             \\\n\t(((x) & BIT_MASK_DSS_3_DATA_IN_8822C) << BIT_SHIFT_DSS_3_DATA_IN_8822C)\n#define BITS_DSS_3_DATA_IN_8822C                                               \\\n\t(BIT_MASK_DSS_3_DATA_IN_8822C << BIT_SHIFT_DSS_3_DATA_IN_8822C)\n#define BIT_CLEAR_DSS_3_DATA_IN_8822C(x) ((x) & (~BITS_DSS_3_DATA_IN_8822C))\n#define BIT_GET_DSS_3_DATA_IN_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_DSS_3_DATA_IN_8822C) & BIT_MASK_DSS_3_DATA_IN_8822C)\n#define BIT_SET_DSS_3_DATA_IN_8822C(x, v)                                      \\\n\t(BIT_CLEAR_DSS_3_DATA_IN_8822C(x) | BIT_DSS_3_DATA_IN_8822C(v))\n\n/* 2 REG_SPEED_SENSOR5_8822C */\n#define BIT_DSS_3_READY_8822C BIT(31)\n#define BIT_DSS_3_WSORT_GO_8822C BIT(30)\n\n#define BIT_SHIFT_DSS_3_COUNT_OUT_8822C 0\n#define BIT_MASK_DSS_3_COUNT_OUT_8822C 0xfffff\n#define BIT_DSS_3_COUNT_OUT_8822C(x)                                           \\\n\t(((x) & BIT_MASK_DSS_3_COUNT_OUT_8822C)                                \\\n\t << BIT_SHIFT_DSS_3_COUNT_OUT_8822C)\n#define BITS_DSS_3_COUNT_OUT_8822C                                             \\\n\t(BIT_MASK_DSS_3_COUNT_OUT_8822C << BIT_SHIFT_DSS_3_COUNT_OUT_8822C)\n#define BIT_CLEAR_DSS_3_COUNT_OUT_8822C(x) ((x) & (~BITS_DSS_3_COUNT_OUT_8822C))\n#define BIT_GET_DSS_3_COUNT_OUT_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DSS_3_COUNT_OUT_8822C) &                            \\\n\t BIT_MASK_DSS_3_COUNT_OUT_8822C)\n#define BIT_SET_DSS_3_COUNT_OUT_8822C(x, v)                                    \\\n\t(BIT_CLEAR_DSS_3_COUNT_OUT_8822C(x) | BIT_DSS_3_COUNT_OUT_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_COUNTER_CTRL_8822C */\n\n#define BIT_SHIFT_COUNTER_BASE_8822C 16\n#define BIT_MASK_COUNTER_BASE_8822C 0x1fff\n#define BIT_COUNTER_BASE_8822C(x)                                              \\\n\t(((x) & BIT_MASK_COUNTER_BASE_8822C) << BIT_SHIFT_COUNTER_BASE_8822C)\n#define BITS_COUNTER_BASE_8822C                                                \\\n\t(BIT_MASK_COUNTER_BASE_8822C << BIT_SHIFT_COUNTER_BASE_8822C)\n#define BIT_CLEAR_COUNTER_BASE_8822C(x) ((x) & (~BITS_COUNTER_BASE_8822C))\n#define BIT_GET_COUNTER_BASE_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_COUNTER_BASE_8822C) & BIT_MASK_COUNTER_BASE_8822C)\n#define BIT_SET_COUNTER_BASE_8822C(x, v)                                       \\\n\t(BIT_CLEAR_COUNTER_BASE_8822C(x) | BIT_COUNTER_BASE_8822C(v))\n\n#define BIT_EN_RTS_REQ_8822C BIT(9)\n#define BIT_EN_EDCA_REQ_8822C BIT(8)\n#define BIT_EN_PTCL_REQ_8822C BIT(7)\n#define BIT_EN_SCH_REQ_8822C BIT(6)\n#define BIT_USB_COUNT_EN_8822C BIT(5)\n#define BIT_PCIE_COUNT_EN_8822C BIT(4)\n#define BIT_RQPN_COUNT_EN_8822C BIT(3)\n#define BIT_RDE_COUNT_EN_8822C BIT(2)\n#define BIT_TDE_COUNT_EN_8822C BIT(1)\n#define BIT_DISABLE_COUNTER_8822C BIT(0)\n\n/* 2 REG_COUNTER_THRESHOLD_8822C */\n#define BIT_SEL_ALL_MACID_8822C BIT(31)\n\n#define BIT_SHIFT_COUNTER_MACID_8822C 24\n#define BIT_MASK_COUNTER_MACID_8822C 0x7f\n#define BIT_COUNTER_MACID_8822C(x)                                             \\\n\t(((x) & BIT_MASK_COUNTER_MACID_8822C) << BIT_SHIFT_COUNTER_MACID_8822C)\n#define BITS_COUNTER_MACID_8822C                                               \\\n\t(BIT_MASK_COUNTER_MACID_8822C << BIT_SHIFT_COUNTER_MACID_8822C)\n#define BIT_CLEAR_COUNTER_MACID_8822C(x) ((x) & (~BITS_COUNTER_MACID_8822C))\n#define BIT_GET_COUNTER_MACID_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_COUNTER_MACID_8822C) & BIT_MASK_COUNTER_MACID_8822C)\n#define BIT_SET_COUNTER_MACID_8822C(x, v)                                      \\\n\t(BIT_CLEAR_COUNTER_MACID_8822C(x) | BIT_COUNTER_MACID_8822C(v))\n\n#define BIT_SHIFT_AGG_VALUE2_8822C 16\n#define BIT_MASK_AGG_VALUE2_8822C 0x7f\n#define BIT_AGG_VALUE2_8822C(x)                                                \\\n\t(((x) & BIT_MASK_AGG_VALUE2_8822C) << BIT_SHIFT_AGG_VALUE2_8822C)\n#define BITS_AGG_VALUE2_8822C                                                  \\\n\t(BIT_MASK_AGG_VALUE2_8822C << BIT_SHIFT_AGG_VALUE2_8822C)\n#define BIT_CLEAR_AGG_VALUE2_8822C(x) ((x) & (~BITS_AGG_VALUE2_8822C))\n#define BIT_GET_AGG_VALUE2_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_AGG_VALUE2_8822C) & BIT_MASK_AGG_VALUE2_8822C)\n#define BIT_SET_AGG_VALUE2_8822C(x, v)                                         \\\n\t(BIT_CLEAR_AGG_VALUE2_8822C(x) | BIT_AGG_VALUE2_8822C(v))\n\n#define BIT_SHIFT_AGG_VALUE1_8822C 8\n#define BIT_MASK_AGG_VALUE1_8822C 0x7f\n#define BIT_AGG_VALUE1_8822C(x)                                                \\\n\t(((x) & BIT_MASK_AGG_VALUE1_8822C) << BIT_SHIFT_AGG_VALUE1_8822C)\n#define BITS_AGG_VALUE1_8822C                                                  \\\n\t(BIT_MASK_AGG_VALUE1_8822C << BIT_SHIFT_AGG_VALUE1_8822C)\n#define BIT_CLEAR_AGG_VALUE1_8822C(x) ((x) & (~BITS_AGG_VALUE1_8822C))\n#define BIT_GET_AGG_VALUE1_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_AGG_VALUE1_8822C) & BIT_MASK_AGG_VALUE1_8822C)\n#define BIT_SET_AGG_VALUE1_8822C(x, v)                                         \\\n\t(BIT_CLEAR_AGG_VALUE1_8822C(x) | BIT_AGG_VALUE1_8822C(v))\n\n#define BIT_SHIFT_AGG_VALUE0_8822C 0\n#define BIT_MASK_AGG_VALUE0_8822C 0x7f\n#define BIT_AGG_VALUE0_8822C(x)                                                \\\n\t(((x) & BIT_MASK_AGG_VALUE0_8822C) << BIT_SHIFT_AGG_VALUE0_8822C)\n#define BITS_AGG_VALUE0_8822C                                                  \\\n\t(BIT_MASK_AGG_VALUE0_8822C << BIT_SHIFT_AGG_VALUE0_8822C)\n#define BIT_CLEAR_AGG_VALUE0_8822C(x) ((x) & (~BITS_AGG_VALUE0_8822C))\n#define BIT_GET_AGG_VALUE0_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_AGG_VALUE0_8822C) & BIT_MASK_AGG_VALUE0_8822C)\n#define BIT_SET_AGG_VALUE0_8822C(x, v)                                         \\\n\t(BIT_CLEAR_AGG_VALUE0_8822C(x) | BIT_AGG_VALUE0_8822C(v))\n\n/* 2 REG_COUNTER_SET_8822C */\n\n#define BIT_SHIFT_REQUEST_RESET_8822C 16\n#define BIT_MASK_REQUEST_RESET_8822C 0xffff\n#define BIT_REQUEST_RESET_8822C(x)                                             \\\n\t(((x) & BIT_MASK_REQUEST_RESET_8822C) << BIT_SHIFT_REQUEST_RESET_8822C)\n#define BITS_REQUEST_RESET_8822C                                               \\\n\t(BIT_MASK_REQUEST_RESET_8822C << BIT_SHIFT_REQUEST_RESET_8822C)\n#define BIT_CLEAR_REQUEST_RESET_8822C(x) ((x) & (~BITS_REQUEST_RESET_8822C))\n#define BIT_GET_REQUEST_RESET_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_REQUEST_RESET_8822C) & BIT_MASK_REQUEST_RESET_8822C)\n#define BIT_SET_REQUEST_RESET_8822C(x, v)                                      \\\n\t(BIT_CLEAR_REQUEST_RESET_8822C(x) | BIT_REQUEST_RESET_8822C(v))\n\n#define BIT_SHIFT_REQUEST_START_8822C 0\n#define BIT_MASK_REQUEST_START_8822C 0xffff\n#define BIT_REQUEST_START_8822C(x)                                             \\\n\t(((x) & BIT_MASK_REQUEST_START_8822C) << BIT_SHIFT_REQUEST_START_8822C)\n#define BITS_REQUEST_START_8822C                                               \\\n\t(BIT_MASK_REQUEST_START_8822C << BIT_SHIFT_REQUEST_START_8822C)\n#define BIT_CLEAR_REQUEST_START_8822C(x) ((x) & (~BITS_REQUEST_START_8822C))\n#define BIT_GET_REQUEST_START_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_REQUEST_START_8822C) & BIT_MASK_REQUEST_START_8822C)\n#define BIT_SET_REQUEST_START_8822C(x, v)                                      \\\n\t(BIT_CLEAR_REQUEST_START_8822C(x) | BIT_REQUEST_START_8822C(v))\n\n/* 2 REG_COUNTER_OVERFLOW_8822C */\n\n#define BIT_SHIFT_CNT_OVF_REG_8822C 0\n#define BIT_MASK_CNT_OVF_REG_8822C 0xffff\n#define BIT_CNT_OVF_REG_8822C(x)                                               \\\n\t(((x) & BIT_MASK_CNT_OVF_REG_8822C) << BIT_SHIFT_CNT_OVF_REG_8822C)\n#define BITS_CNT_OVF_REG_8822C                                                 \\\n\t(BIT_MASK_CNT_OVF_REG_8822C << BIT_SHIFT_CNT_OVF_REG_8822C)\n#define BIT_CLEAR_CNT_OVF_REG_8822C(x) ((x) & (~BITS_CNT_OVF_REG_8822C))\n#define BIT_GET_CNT_OVF_REG_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_CNT_OVF_REG_8822C) & BIT_MASK_CNT_OVF_REG_8822C)\n#define BIT_SET_CNT_OVF_REG_8822C(x, v)                                        \\\n\t(BIT_CLEAR_CNT_OVF_REG_8822C(x) | BIT_CNT_OVF_REG_8822C(v))\n\n/* 2 REG_TXDMA_LEN_THRESHOLD_8822C */\n\n#define BIT_SHIFT_TDE_LEN_TH1_8822C 16\n#define BIT_MASK_TDE_LEN_TH1_8822C 0xffff\n#define BIT_TDE_LEN_TH1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_TDE_LEN_TH1_8822C) << BIT_SHIFT_TDE_LEN_TH1_8822C)\n#define BITS_TDE_LEN_TH1_8822C                                                 \\\n\t(BIT_MASK_TDE_LEN_TH1_8822C << BIT_SHIFT_TDE_LEN_TH1_8822C)\n#define BIT_CLEAR_TDE_LEN_TH1_8822C(x) ((x) & (~BITS_TDE_LEN_TH1_8822C))\n#define BIT_GET_TDE_LEN_TH1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_TDE_LEN_TH1_8822C) & BIT_MASK_TDE_LEN_TH1_8822C)\n#define BIT_SET_TDE_LEN_TH1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_TDE_LEN_TH1_8822C(x) | BIT_TDE_LEN_TH1_8822C(v))\n\n#define BIT_SHIFT_TDE_LEN_TH0_8822C 0\n#define BIT_MASK_TDE_LEN_TH0_8822C 0xffff\n#define BIT_TDE_LEN_TH0_8822C(x)                                               \\\n\t(((x) & BIT_MASK_TDE_LEN_TH0_8822C) << BIT_SHIFT_TDE_LEN_TH0_8822C)\n#define BITS_TDE_LEN_TH0_8822C                                                 \\\n\t(BIT_MASK_TDE_LEN_TH0_8822C << BIT_SHIFT_TDE_LEN_TH0_8822C)\n#define BIT_CLEAR_TDE_LEN_TH0_8822C(x) ((x) & (~BITS_TDE_LEN_TH0_8822C))\n#define BIT_GET_TDE_LEN_TH0_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_TDE_LEN_TH0_8822C) & BIT_MASK_TDE_LEN_TH0_8822C)\n#define BIT_SET_TDE_LEN_TH0_8822C(x, v)                                        \\\n\t(BIT_CLEAR_TDE_LEN_TH0_8822C(x) | BIT_TDE_LEN_TH0_8822C(v))\n\n/* 2 REG_RXDMA_LEN_THRESHOLD_8822C */\n\n#define BIT_SHIFT_RDE_LEN_TH1_8822C 16\n#define BIT_MASK_RDE_LEN_TH1_8822C 0xffff\n#define BIT_RDE_LEN_TH1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_RDE_LEN_TH1_8822C) << BIT_SHIFT_RDE_LEN_TH1_8822C)\n#define BITS_RDE_LEN_TH1_8822C                                                 \\\n\t(BIT_MASK_RDE_LEN_TH1_8822C << BIT_SHIFT_RDE_LEN_TH1_8822C)\n#define BIT_CLEAR_RDE_LEN_TH1_8822C(x) ((x) & (~BITS_RDE_LEN_TH1_8822C))\n#define BIT_GET_RDE_LEN_TH1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RDE_LEN_TH1_8822C) & BIT_MASK_RDE_LEN_TH1_8822C)\n#define BIT_SET_RDE_LEN_TH1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_RDE_LEN_TH1_8822C(x) | BIT_RDE_LEN_TH1_8822C(v))\n\n#define BIT_SHIFT_RDE_LEN_TH0_8822C 0\n#define BIT_MASK_RDE_LEN_TH0_8822C 0xffff\n#define BIT_RDE_LEN_TH0_8822C(x)                                               \\\n\t(((x) & BIT_MASK_RDE_LEN_TH0_8822C) << BIT_SHIFT_RDE_LEN_TH0_8822C)\n#define BITS_RDE_LEN_TH0_8822C                                                 \\\n\t(BIT_MASK_RDE_LEN_TH0_8822C << BIT_SHIFT_RDE_LEN_TH0_8822C)\n#define BIT_CLEAR_RDE_LEN_TH0_8822C(x) ((x) & (~BITS_RDE_LEN_TH0_8822C))\n#define BIT_GET_RDE_LEN_TH0_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RDE_LEN_TH0_8822C) & BIT_MASK_RDE_LEN_TH0_8822C)\n#define BIT_SET_RDE_LEN_TH0_8822C(x, v)                                        \\\n\t(BIT_CLEAR_RDE_LEN_TH0_8822C(x) | BIT_RDE_LEN_TH0_8822C(v))\n\n/* 2 REG_PCIE_EXEC_TIME_THRESHOLD_8822C */\n\n#define BIT_SHIFT_COUNT_INT_SEL_8822C 16\n#define BIT_MASK_COUNT_INT_SEL_8822C 0x3\n#define BIT_COUNT_INT_SEL_8822C(x)                                             \\\n\t(((x) & BIT_MASK_COUNT_INT_SEL_8822C) << BIT_SHIFT_COUNT_INT_SEL_8822C)\n#define BITS_COUNT_INT_SEL_8822C                                               \\\n\t(BIT_MASK_COUNT_INT_SEL_8822C << BIT_SHIFT_COUNT_INT_SEL_8822C)\n#define BIT_CLEAR_COUNT_INT_SEL_8822C(x) ((x) & (~BITS_COUNT_INT_SEL_8822C))\n#define BIT_GET_COUNT_INT_SEL_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_COUNT_INT_SEL_8822C) & BIT_MASK_COUNT_INT_SEL_8822C)\n#define BIT_SET_COUNT_INT_SEL_8822C(x, v)                                      \\\n\t(BIT_CLEAR_COUNT_INT_SEL_8822C(x) | BIT_COUNT_INT_SEL_8822C(v))\n\n#define BIT_SHIFT_EXEC_TIME_TH_8822C 0\n#define BIT_MASK_EXEC_TIME_TH_8822C 0xffff\n#define BIT_EXEC_TIME_TH_8822C(x)                                              \\\n\t(((x) & BIT_MASK_EXEC_TIME_TH_8822C) << BIT_SHIFT_EXEC_TIME_TH_8822C)\n#define BITS_EXEC_TIME_TH_8822C                                                \\\n\t(BIT_MASK_EXEC_TIME_TH_8822C << BIT_SHIFT_EXEC_TIME_TH_8822C)\n#define BIT_CLEAR_EXEC_TIME_TH_8822C(x) ((x) & (~BITS_EXEC_TIME_TH_8822C))\n#define BIT_GET_EXEC_TIME_TH_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_EXEC_TIME_TH_8822C) & BIT_MASK_EXEC_TIME_TH_8822C)\n#define BIT_SET_EXEC_TIME_TH_8822C(x, v)                                       \\\n\t(BIT_CLEAR_EXEC_TIME_TH_8822C(x) | BIT_EXEC_TIME_TH_8822C(v))\n\n/* 2 REG_FT2IMR_8822C */\n#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8822C BIT(31)\n#define BIT_FS_CLI3_RX_UAPSDMD0_EN_8822C BIT(30)\n#define BIT_FS_CLI3_TRIGGER_PKT_EN_8822C BIT(29)\n#define BIT_FS_CLI3_EOSP_INT_EN_8822C BIT(28)\n#define BIT_FS_CLI2_RX_UAPSDMD1_EN_8822C BIT(27)\n#define BIT_FS_CLI2_RX_UAPSDMD0_EN_8822C BIT(26)\n#define BIT_FS_CLI2_TRIGGER_PKT_EN_8822C BIT(25)\n#define BIT_FS_CLI2_EOSP_INT_EN_8822C BIT(24)\n#define BIT_FS_CLI1_RX_UAPSDMD1_EN_8822C BIT(23)\n#define BIT_FS_CLI1_RX_UAPSDMD0_EN_8822C BIT(22)\n#define BIT_FS_CLI1_TRIGGER_PKT_EN_8822C BIT(21)\n#define BIT_FS_CLI1_EOSP_INT_EN_8822C BIT(20)\n#define BIT_FS_CLI0_RX_UAPSDMD1_EN_8822C BIT(19)\n#define BIT_FS_CLI0_RX_UAPSDMD0_EN_8822C BIT(18)\n#define BIT_FS_CLI0_TRIGGER_PKT_EN_8822C BIT(17)\n#define BIT_FS_CLI0_EOSP_INT_EN_8822C BIT(16)\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN_8822C BIT(9)\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN_8822C BIT(8)\n#define BIT_FS_CLI3_TX_NULL1_INT_EN_8822C BIT(7)\n#define BIT_FS_CLI3_TX_NULL0_INT_EN_8822C BIT(6)\n#define BIT_FS_CLI2_TX_NULL1_INT_EN_8822C BIT(5)\n#define BIT_FS_CLI2_TX_NULL0_INT_EN_8822C BIT(4)\n#define BIT_FS_CLI1_TX_NULL1_INT_EN_8822C BIT(3)\n#define BIT_FS_CLI1_TX_NULL0_INT_EN_8822C BIT(2)\n#define BIT_FS_CLI0_TX_NULL1_INT_EN_8822C BIT(1)\n#define BIT_FS_CLI0_TX_NULL0_INT_EN_8822C BIT(0)\n\n/* 2 REG_FT2ISR_8822C */\n#define BIT_FS_CLI3_RX_UAPSDMD1_INT_8822C BIT(31)\n#define BIT_FS_CLI3_RX_UAPSDMD0_INT_8822C BIT(30)\n#define BIT_FS_CLI3_TRIGGER_PKT_INT_8822C BIT(29)\n#define BIT_FS_CLI3_EOSP_INT_8822C BIT(28)\n#define BIT_FS_CLI2_RX_UAPSDMD1_INT_8822C BIT(27)\n#define BIT_FS_CLI2_RX_UAPSDMD0_INT_8822C BIT(26)\n#define BIT_FS_CLI2_TRIGGER_PKT_INT_8822C BIT(25)\n#define BIT_FS_CLI2_EOSP_INT_8822C BIT(24)\n#define BIT_FS_CLI1_RX_UAPSDMD1_INT_8822C BIT(23)\n#define BIT_FS_CLI1_RX_UAPSDMD0_INT_8822C BIT(22)\n#define BIT_FS_CLI1_TRIGGER_PKT_INT_8822C BIT(21)\n#define BIT_FS_CLI1_EOSP_INT_8822C BIT(20)\n#define BIT_FS_CLI0_RX_UAPSDMD1_INT_8822C BIT(19)\n#define BIT_FS_CLI0_RX_UAPSDMD0_INT_8822C BIT(18)\n#define BIT_FS_CLI0_TRIGGER_PKT_INT_8822C BIT(17)\n#define BIT_FS_CLI0_EOSP_INT_8822C BIT(16)\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT_8822C BIT(9)\n#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT_8822C BIT(8)\n#define BIT_FS_CLI3_TX_NULL1_INT_8822C BIT(7)\n#define BIT_FS_CLI3_TX_NULL0_INT_8822C BIT(6)\n#define BIT_FS_CLI2_TX_NULL1_INT_8822C BIT(5)\n#define BIT_FS_CLI2_TX_NULL0_INT_8822C BIT(4)\n#define BIT_FS_CLI1_TX_NULL1_INT_8822C BIT(3)\n#define BIT_FS_CLI1_TX_NULL0_INT_8822C BIT(2)\n#define BIT_FS_CLI0_TX_NULL1_INT_8822C BIT(1)\n#define BIT_FS_CLI0_TX_NULL0_INT_8822C BIT(0)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_MSG2_8822C */\n\n#define BIT_SHIFT_FW_MSG2_8822C 0\n#define BIT_MASK_FW_MSG2_8822C 0xffffffffL\n#define BIT_FW_MSG2_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG2_8822C) << BIT_SHIFT_FW_MSG2_8822C)\n#define BITS_FW_MSG2_8822C (BIT_MASK_FW_MSG2_8822C << BIT_SHIFT_FW_MSG2_8822C)\n#define BIT_CLEAR_FW_MSG2_8822C(x) ((x) & (~BITS_FW_MSG2_8822C))\n#define BIT_GET_FW_MSG2_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG2_8822C) & BIT_MASK_FW_MSG2_8822C)\n#define BIT_SET_FW_MSG2_8822C(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG2_8822C(x) | BIT_FW_MSG2_8822C(v))\n\n/* 2 REG_MSG3_8822C */\n\n#define BIT_SHIFT_FW_MSG3_8822C 0\n#define BIT_MASK_FW_MSG3_8822C 0xffffffffL\n#define BIT_FW_MSG3_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG3_8822C) << BIT_SHIFT_FW_MSG3_8822C)\n#define BITS_FW_MSG3_8822C (BIT_MASK_FW_MSG3_8822C << BIT_SHIFT_FW_MSG3_8822C)\n#define BIT_CLEAR_FW_MSG3_8822C(x) ((x) & (~BITS_FW_MSG3_8822C))\n#define BIT_GET_FW_MSG3_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG3_8822C) & BIT_MASK_FW_MSG3_8822C)\n#define BIT_SET_FW_MSG3_8822C(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG3_8822C(x) | BIT_FW_MSG3_8822C(v))\n\n/* 2 REG_MSG4_8822C */\n\n#define BIT_SHIFT_FW_MSG4_8822C 0\n#define BIT_MASK_FW_MSG4_8822C 0xffffffffL\n#define BIT_FW_MSG4_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG4_8822C) << BIT_SHIFT_FW_MSG4_8822C)\n#define BITS_FW_MSG4_8822C (BIT_MASK_FW_MSG4_8822C << BIT_SHIFT_FW_MSG4_8822C)\n#define BIT_CLEAR_FW_MSG4_8822C(x) ((x) & (~BITS_FW_MSG4_8822C))\n#define BIT_GET_FW_MSG4_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG4_8822C) & BIT_MASK_FW_MSG4_8822C)\n#define BIT_SET_FW_MSG4_8822C(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG4_8822C(x) | BIT_FW_MSG4_8822C(v))\n\n/* 2 REG_MSG5_8822C */\n\n#define BIT_SHIFT_FW_MSG5_8822C 0\n#define BIT_MASK_FW_MSG5_8822C 0xffffffffL\n#define BIT_FW_MSG5_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_FW_MSG5_8822C) << BIT_SHIFT_FW_MSG5_8822C)\n#define BITS_FW_MSG5_8822C (BIT_MASK_FW_MSG5_8822C << BIT_SHIFT_FW_MSG5_8822C)\n#define BIT_CLEAR_FW_MSG5_8822C(x) ((x) & (~BITS_FW_MSG5_8822C))\n#define BIT_GET_FW_MSG5_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_FW_MSG5_8822C) & BIT_MASK_FW_MSG5_8822C)\n#define BIT_SET_FW_MSG5_8822C(x, v)                                            \\\n\t(BIT_CLEAR_FW_MSG5_8822C(x) | BIT_FW_MSG5_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_FIFOPAGE_CTRL_1_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C 16\n#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C 0xff\n#define BIT_TX_OQT_HE_FREE_SPACE_V1_8822C(x)                                   \\\n\t(((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C)                        \\\n\t << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C)\n#define BITS_TX_OQT_HE_FREE_SPACE_V1_8822C                                     \\\n\t(BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C                                \\\n\t << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C)\n#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822C(x)                             \\\n\t((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8822C))\n#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8822C(x)                               \\\n\t(((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C) &                    \\\n\t BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C)\n#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8822C(x, v)                            \\\n\t(BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822C(x) |                          \\\n\t BIT_TX_OQT_HE_FREE_SPACE_V1_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C 0\n#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C 0xff\n#define BIT_TX_OQT_NL_FREE_SPACE_V1_8822C(x)                                   \\\n\t(((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C)                        \\\n\t << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C)\n#define BITS_TX_OQT_NL_FREE_SPACE_V1_8822C                                     \\\n\t(BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C                                \\\n\t << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C)\n#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822C(x)                             \\\n\t((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8822C))\n#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8822C(x)                               \\\n\t(((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C) &                    \\\n\t BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C)\n#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8822C(x, v)                            \\\n\t(BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822C(x) |                          \\\n\t BIT_TX_OQT_NL_FREE_SPACE_V1_8822C(v))\n\n/* 2 REG_FIFOPAGE_CTRL_2_8822C */\n#define BIT_BCN_VALID_1_V1_8822C BIT(31)\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_BCN_HEAD_1_V1_8822C 16\n#define BIT_MASK_BCN_HEAD_1_V1_8822C 0xfff\n#define BIT_BCN_HEAD_1_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_BCN_HEAD_1_V1_8822C) << BIT_SHIFT_BCN_HEAD_1_V1_8822C)\n#define BITS_BCN_HEAD_1_V1_8822C                                               \\\n\t(BIT_MASK_BCN_HEAD_1_V1_8822C << BIT_SHIFT_BCN_HEAD_1_V1_8822C)\n#define BIT_CLEAR_BCN_HEAD_1_V1_8822C(x) ((x) & (~BITS_BCN_HEAD_1_V1_8822C))\n#define BIT_GET_BCN_HEAD_1_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8822C) & BIT_MASK_BCN_HEAD_1_V1_8822C)\n#define BIT_SET_BCN_HEAD_1_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_BCN_HEAD_1_V1_8822C(x) | BIT_BCN_HEAD_1_V1_8822C(v))\n\n#define BIT_BCN_VALID_V1_8822C BIT(15)\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_BCN_HEAD_V1_8822C 0\n#define BIT_MASK_BCN_HEAD_V1_8822C 0xfff\n#define BIT_BCN_HEAD_V1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_BCN_HEAD_V1_8822C) << BIT_SHIFT_BCN_HEAD_V1_8822C)\n#define BITS_BCN_HEAD_V1_8822C                                                 \\\n\t(BIT_MASK_BCN_HEAD_V1_8822C << BIT_SHIFT_BCN_HEAD_V1_8822C)\n#define BIT_CLEAR_BCN_HEAD_V1_8822C(x) ((x) & (~BITS_BCN_HEAD_V1_8822C))\n#define BIT_GET_BCN_HEAD_V1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_BCN_HEAD_V1_8822C) & BIT_MASK_BCN_HEAD_V1_8822C)\n#define BIT_SET_BCN_HEAD_V1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_BCN_HEAD_V1_8822C(x) | BIT_BCN_HEAD_V1_8822C(v))\n\n/* 2 REG_AUTO_LLT_V1_8822C */\n\n#define BIT_SHIFT_MAX_TX_PKT_V1_8822C 24\n#define BIT_MASK_MAX_TX_PKT_V1_8822C 0xff\n#define BIT_MAX_TX_PKT_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_MAX_TX_PKT_V1_8822C) << BIT_SHIFT_MAX_TX_PKT_V1_8822C)\n#define BITS_MAX_TX_PKT_V1_8822C                                               \\\n\t(BIT_MASK_MAX_TX_PKT_V1_8822C << BIT_SHIFT_MAX_TX_PKT_V1_8822C)\n#define BIT_CLEAR_MAX_TX_PKT_V1_8822C(x) ((x) & (~BITS_MAX_TX_PKT_V1_8822C))\n#define BIT_GET_MAX_TX_PKT_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MAX_TX_PKT_V1_8822C) & BIT_MASK_MAX_TX_PKT_V1_8822C)\n#define BIT_SET_MAX_TX_PKT_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_MAX_TX_PKT_V1_8822C(x) | BIT_MAX_TX_PKT_V1_8822C(v))\n\n#define BIT_TDE_ERROR_STOP_V1_8822C BIT(23)\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_LLT_FREE_PAGE_V2_8822C 8\n#define BIT_MASK_LLT_FREE_PAGE_V2_8822C 0xfff\n#define BIT_LLT_FREE_PAGE_V2_8822C(x)                                          \\\n\t(((x) & BIT_MASK_LLT_FREE_PAGE_V2_8822C)                               \\\n\t << BIT_SHIFT_LLT_FREE_PAGE_V2_8822C)\n#define BITS_LLT_FREE_PAGE_V2_8822C                                            \\\n\t(BIT_MASK_LLT_FREE_PAGE_V2_8822C << BIT_SHIFT_LLT_FREE_PAGE_V2_8822C)\n#define BIT_CLEAR_LLT_FREE_PAGE_V2_8822C(x)                                    \\\n\t((x) & (~BITS_LLT_FREE_PAGE_V2_8822C))\n#define BIT_GET_LLT_FREE_PAGE_V2_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2_8822C) &                           \\\n\t BIT_MASK_LLT_FREE_PAGE_V2_8822C)\n#define BIT_SET_LLT_FREE_PAGE_V2_8822C(x, v)                                   \\\n\t(BIT_CLEAR_LLT_FREE_PAGE_V2_8822C(x) | BIT_LLT_FREE_PAGE_V2_8822C(v))\n\n#define BIT_SHIFT_BLK_DESC_NUM_8822C 4\n#define BIT_MASK_BLK_DESC_NUM_8822C 0xf\n#define BIT_BLK_DESC_NUM_8822C(x)                                              \\\n\t(((x) & BIT_MASK_BLK_DESC_NUM_8822C) << BIT_SHIFT_BLK_DESC_NUM_8822C)\n#define BITS_BLK_DESC_NUM_8822C                                                \\\n\t(BIT_MASK_BLK_DESC_NUM_8822C << BIT_SHIFT_BLK_DESC_NUM_8822C)\n#define BIT_CLEAR_BLK_DESC_NUM_8822C(x) ((x) & (~BITS_BLK_DESC_NUM_8822C))\n#define BIT_GET_BLK_DESC_NUM_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BLK_DESC_NUM_8822C) & BIT_MASK_BLK_DESC_NUM_8822C)\n#define BIT_SET_BLK_DESC_NUM_8822C(x, v)                                       \\\n\t(BIT_CLEAR_BLK_DESC_NUM_8822C(x) | BIT_BLK_DESC_NUM_8822C(v))\n\n#define BIT_R_BCN_HEAD_SEL_8822C BIT(3)\n#define BIT_R_EN_BCN_SW_HEAD_SEL_8822C BIT(2)\n#define BIT_LLT_DBG_SEL_8822C BIT(1)\n#define BIT_AUTO_INIT_LLT_V1_8822C BIT(0)\n\n/* 2 REG_TXDMA_OFFSET_CHK_8822C */\n#define BIT_EM_CHKSUM_FIN_8822C BIT(31)\n#define BIT_EMN_PCIE_DMA_MOD_8822C BIT(30)\n#define BIT_EN_TXQUE_CLR_8822C BIT(29)\n#define BIT_EN_PCIE_FIFO_MODE_8822C BIT(28)\n\n#define BIT_SHIFT_PG_UNDER_TH_V1_8822C 16\n#define BIT_MASK_PG_UNDER_TH_V1_8822C 0xfff\n#define BIT_PG_UNDER_TH_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_PG_UNDER_TH_V1_8822C)                                 \\\n\t << BIT_SHIFT_PG_UNDER_TH_V1_8822C)\n#define BITS_PG_UNDER_TH_V1_8822C                                              \\\n\t(BIT_MASK_PG_UNDER_TH_V1_8822C << BIT_SHIFT_PG_UNDER_TH_V1_8822C)\n#define BIT_CLEAR_PG_UNDER_TH_V1_8822C(x) ((x) & (~BITS_PG_UNDER_TH_V1_8822C))\n#define BIT_GET_PG_UNDER_TH_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8822C) &                             \\\n\t BIT_MASK_PG_UNDER_TH_V1_8822C)\n#define BIT_SET_PG_UNDER_TH_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_PG_UNDER_TH_V1_8822C(x) | BIT_PG_UNDER_TH_V1_8822C(v))\n\n#define BIT_R_EN_RESET_RESTORE_H2C_8822C BIT(15)\n#define BIT_SDIO_TDE_FINISH_8822C BIT(14)\n#define BIT_SDIO_TXDESC_CHKSUM_EN_8822C BIT(13)\n#define BIT_RST_RDPTR_8822C BIT(12)\n#define BIT_RST_WRPTR_8822C BIT(11)\n#define BIT_CHK_PG_TH_EN_8822C BIT(10)\n#define BIT_DROP_DATA_EN_8822C BIT(9)\n#define BIT_CHECK_OFFSET_EN_8822C BIT(8)\n\n#define BIT_SHIFT_CHECK_OFFSET_8822C 0\n#define BIT_MASK_CHECK_OFFSET_8822C 0xff\n#define BIT_CHECK_OFFSET_8822C(x)                                              \\\n\t(((x) & BIT_MASK_CHECK_OFFSET_8822C) << BIT_SHIFT_CHECK_OFFSET_8822C)\n#define BITS_CHECK_OFFSET_8822C                                                \\\n\t(BIT_MASK_CHECK_OFFSET_8822C << BIT_SHIFT_CHECK_OFFSET_8822C)\n#define BIT_CLEAR_CHECK_OFFSET_8822C(x) ((x) & (~BITS_CHECK_OFFSET_8822C))\n#define BIT_GET_CHECK_OFFSET_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_CHECK_OFFSET_8822C) & BIT_MASK_CHECK_OFFSET_8822C)\n#define BIT_SET_CHECK_OFFSET_8822C(x, v)                                       \\\n\t(BIT_CLEAR_CHECK_OFFSET_8822C(x) | BIT_CHECK_OFFSET_8822C(v))\n\n/* 2 REG_TXDMA_STATUS_8822C */\n#define BIT_TXPKTBUF_REQ_ERR_8822C BIT(18)\n#define BIT_HI_OQT_UDN_8822C BIT(17)\n#define BIT_HI_OQT_OVF_8822C BIT(16)\n#define BIT_PAYLOAD_CHKSUM_ERR_8822C BIT(15)\n#define BIT_PAYLOAD_UDN_8822C BIT(14)\n#define BIT_PAYLOAD_OVF_8822C BIT(13)\n#define BIT_DSC_CHKSUM_FAIL_8822C BIT(12)\n#define BIT_UNKNOWN_QSEL_8822C BIT(11)\n#define BIT_EP_QSEL_DIFF_8822C BIT(10)\n#define BIT_TX_OFFS_UNMATCH_8822C BIT(9)\n#define BIT_TXOQT_UDN_8822C BIT(8)\n#define BIT_TXOQT_OVF_8822C BIT(7)\n#define BIT_TXDMA_SFF_UDN_8822C BIT(6)\n#define BIT_TXDMA_SFF_OVF_8822C BIT(5)\n#define BIT_LLT_NULL_PG_8822C BIT(4)\n#define BIT_PAGE_UDN_8822C BIT(3)\n#define BIT_PAGE_OVF_8822C BIT(2)\n#define BIT_TXFF_PG_UDN_8822C BIT(1)\n#define BIT_TXFF_PG_OVF_8822C BIT(0)\n\n/* 2 REG_TX_DMA_DBG_8822C */\n\n/* 2 REG_TQPNT1_8822C */\n#define BIT_HPQ_INT_EN_8822C BIT(31)\n\n#define BIT_SHIFT_HPQ_HIGH_TH_V1_8822C 16\n#define BIT_MASK_HPQ_HIGH_TH_V1_8822C 0xfff\n#define BIT_HPQ_HIGH_TH_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HPQ_HIGH_TH_V1_8822C)                                 \\\n\t << BIT_SHIFT_HPQ_HIGH_TH_V1_8822C)\n#define BITS_HPQ_HIGH_TH_V1_8822C                                              \\\n\t(BIT_MASK_HPQ_HIGH_TH_V1_8822C << BIT_SHIFT_HPQ_HIGH_TH_V1_8822C)\n#define BIT_CLEAR_HPQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8822C))\n#define BIT_GET_HPQ_HIGH_TH_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8822C) &                             \\\n\t BIT_MASK_HPQ_HIGH_TH_V1_8822C)\n#define BIT_SET_HPQ_HIGH_TH_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HPQ_HIGH_TH_V1_8822C(x) | BIT_HPQ_HIGH_TH_V1_8822C(v))\n\n#define BIT_SHIFT_HPQ_LOW_TH_V1_8822C 0\n#define BIT_MASK_HPQ_LOW_TH_V1_8822C 0xfff\n#define BIT_HPQ_LOW_TH_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HPQ_LOW_TH_V1_8822C) << BIT_SHIFT_HPQ_LOW_TH_V1_8822C)\n#define BITS_HPQ_LOW_TH_V1_8822C                                               \\\n\t(BIT_MASK_HPQ_LOW_TH_V1_8822C << BIT_SHIFT_HPQ_LOW_TH_V1_8822C)\n#define BIT_CLEAR_HPQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8822C))\n#define BIT_GET_HPQ_LOW_TH_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8822C) & BIT_MASK_HPQ_LOW_TH_V1_8822C)\n#define BIT_SET_HPQ_LOW_TH_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HPQ_LOW_TH_V1_8822C(x) | BIT_HPQ_LOW_TH_V1_8822C(v))\n\n/* 2 REG_TQPNT2_8822C */\n#define BIT_NPQ_INT_EN_8822C BIT(31)\n\n#define BIT_SHIFT_NPQ_HIGH_TH_V1_8822C 16\n#define BIT_MASK_NPQ_HIGH_TH_V1_8822C 0xfff\n#define BIT_NPQ_HIGH_TH_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_NPQ_HIGH_TH_V1_8822C)                                 \\\n\t << BIT_SHIFT_NPQ_HIGH_TH_V1_8822C)\n#define BITS_NPQ_HIGH_TH_V1_8822C                                              \\\n\t(BIT_MASK_NPQ_HIGH_TH_V1_8822C << BIT_SHIFT_NPQ_HIGH_TH_V1_8822C)\n#define BIT_CLEAR_NPQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8822C))\n#define BIT_GET_NPQ_HIGH_TH_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8822C) &                             \\\n\t BIT_MASK_NPQ_HIGH_TH_V1_8822C)\n#define BIT_SET_NPQ_HIGH_TH_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_NPQ_HIGH_TH_V1_8822C(x) | BIT_NPQ_HIGH_TH_V1_8822C(v))\n\n#define BIT_SHIFT_NPQ_LOW_TH_V1_8822C 0\n#define BIT_MASK_NPQ_LOW_TH_V1_8822C 0xfff\n#define BIT_NPQ_LOW_TH_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_NPQ_LOW_TH_V1_8822C) << BIT_SHIFT_NPQ_LOW_TH_V1_8822C)\n#define BITS_NPQ_LOW_TH_V1_8822C                                               \\\n\t(BIT_MASK_NPQ_LOW_TH_V1_8822C << BIT_SHIFT_NPQ_LOW_TH_V1_8822C)\n#define BIT_CLEAR_NPQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8822C))\n#define BIT_GET_NPQ_LOW_TH_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8822C) & BIT_MASK_NPQ_LOW_TH_V1_8822C)\n#define BIT_SET_NPQ_LOW_TH_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_NPQ_LOW_TH_V1_8822C(x) | BIT_NPQ_LOW_TH_V1_8822C(v))\n\n/* 2 REG_TQPNT3_8822C */\n#define BIT_LPQ_INT_EN_8822C BIT(31)\n\n#define BIT_SHIFT_LPQ_HIGH_TH_V1_8822C 16\n#define BIT_MASK_LPQ_HIGH_TH_V1_8822C 0xfff\n#define BIT_LPQ_HIGH_TH_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_LPQ_HIGH_TH_V1_8822C)                                 \\\n\t << BIT_SHIFT_LPQ_HIGH_TH_V1_8822C)\n#define BITS_LPQ_HIGH_TH_V1_8822C                                              \\\n\t(BIT_MASK_LPQ_HIGH_TH_V1_8822C << BIT_SHIFT_LPQ_HIGH_TH_V1_8822C)\n#define BIT_CLEAR_LPQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8822C))\n#define BIT_GET_LPQ_HIGH_TH_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8822C) &                             \\\n\t BIT_MASK_LPQ_HIGH_TH_V1_8822C)\n#define BIT_SET_LPQ_HIGH_TH_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_LPQ_HIGH_TH_V1_8822C(x) | BIT_LPQ_HIGH_TH_V1_8822C(v))\n\n#define BIT_SHIFT_LPQ_LOW_TH_V1_8822C 0\n#define BIT_MASK_LPQ_LOW_TH_V1_8822C 0xfff\n#define BIT_LPQ_LOW_TH_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_LPQ_LOW_TH_V1_8822C) << BIT_SHIFT_LPQ_LOW_TH_V1_8822C)\n#define BITS_LPQ_LOW_TH_V1_8822C                                               \\\n\t(BIT_MASK_LPQ_LOW_TH_V1_8822C << BIT_SHIFT_LPQ_LOW_TH_V1_8822C)\n#define BIT_CLEAR_LPQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8822C))\n#define BIT_GET_LPQ_LOW_TH_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8822C) & BIT_MASK_LPQ_LOW_TH_V1_8822C)\n#define BIT_SET_LPQ_LOW_TH_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_LPQ_LOW_TH_V1_8822C(x) | BIT_LPQ_LOW_TH_V1_8822C(v))\n\n/* 2 REG_TQPNT4_8822C */\n#define BIT_EXQ_INT_EN_8822C BIT(31)\n\n#define BIT_SHIFT_EXQ_HIGH_TH_V1_8822C 16\n#define BIT_MASK_EXQ_HIGH_TH_V1_8822C 0xfff\n#define BIT_EXQ_HIGH_TH_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_EXQ_HIGH_TH_V1_8822C)                                 \\\n\t << BIT_SHIFT_EXQ_HIGH_TH_V1_8822C)\n#define BITS_EXQ_HIGH_TH_V1_8822C                                              \\\n\t(BIT_MASK_EXQ_HIGH_TH_V1_8822C << BIT_SHIFT_EXQ_HIGH_TH_V1_8822C)\n#define BIT_CLEAR_EXQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8822C))\n#define BIT_GET_EXQ_HIGH_TH_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8822C) &                             \\\n\t BIT_MASK_EXQ_HIGH_TH_V1_8822C)\n#define BIT_SET_EXQ_HIGH_TH_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_EXQ_HIGH_TH_V1_8822C(x) | BIT_EXQ_HIGH_TH_V1_8822C(v))\n\n#define BIT_SHIFT_EXQ_LOW_TH_V1_8822C 0\n#define BIT_MASK_EXQ_LOW_TH_V1_8822C 0xfff\n#define BIT_EXQ_LOW_TH_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_EXQ_LOW_TH_V1_8822C) << BIT_SHIFT_EXQ_LOW_TH_V1_8822C)\n#define BITS_EXQ_LOW_TH_V1_8822C                                               \\\n\t(BIT_MASK_EXQ_LOW_TH_V1_8822C << BIT_SHIFT_EXQ_LOW_TH_V1_8822C)\n#define BIT_CLEAR_EXQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8822C))\n#define BIT_GET_EXQ_LOW_TH_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8822C) & BIT_MASK_EXQ_LOW_TH_V1_8822C)\n#define BIT_SET_EXQ_LOW_TH_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_EXQ_LOW_TH_V1_8822C(x) | BIT_EXQ_LOW_TH_V1_8822C(v))\n\n/* 2 REG_RQPN_CTRL_1_8822C */\n\n#define BIT_SHIFT_TXPKTNUM_H_V2_8822C 16\n#define BIT_MASK_TXPKTNUM_H_V2_8822C 0xfff\n#define BIT_TXPKTNUM_H_V2_8822C(x)                                             \\\n\t(((x) & BIT_MASK_TXPKTNUM_H_V2_8822C) << BIT_SHIFT_TXPKTNUM_H_V2_8822C)\n#define BITS_TXPKTNUM_H_V2_8822C                                               \\\n\t(BIT_MASK_TXPKTNUM_H_V2_8822C << BIT_SHIFT_TXPKTNUM_H_V2_8822C)\n#define BIT_CLEAR_TXPKTNUM_H_V2_8822C(x) ((x) & (~BITS_TXPKTNUM_H_V2_8822C))\n#define BIT_GET_TXPKTNUM_H_V2_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_H_V2_8822C) & BIT_MASK_TXPKTNUM_H_V2_8822C)\n#define BIT_SET_TXPKTNUM_H_V2_8822C(x, v)                                      \\\n\t(BIT_CLEAR_TXPKTNUM_H_V2_8822C(x) | BIT_TXPKTNUM_H_V2_8822C(v))\n\n#define BIT_SHIFT_TXPKTNUM_V3_8822C 0\n#define BIT_MASK_TXPKTNUM_V3_8822C 0xfff\n#define BIT_TXPKTNUM_V3_8822C(x)                                               \\\n\t(((x) & BIT_MASK_TXPKTNUM_V3_8822C) << BIT_SHIFT_TXPKTNUM_V3_8822C)\n#define BITS_TXPKTNUM_V3_8822C                                                 \\\n\t(BIT_MASK_TXPKTNUM_V3_8822C << BIT_SHIFT_TXPKTNUM_V3_8822C)\n#define BIT_CLEAR_TXPKTNUM_V3_8822C(x) ((x) & (~BITS_TXPKTNUM_V3_8822C))\n#define BIT_GET_TXPKTNUM_V3_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_TXPKTNUM_V3_8822C) & BIT_MASK_TXPKTNUM_V3_8822C)\n#define BIT_SET_TXPKTNUM_V3_8822C(x, v)                                        \\\n\t(BIT_CLEAR_TXPKTNUM_V3_8822C(x) | BIT_TXPKTNUM_V3_8822C(v))\n\n/* 2 REG_RQPN_CTRL_2_8822C */\n#define BIT_LD_RQPN_8822C BIT(31)\n#define BIT_EXQ_PUBLIC_DIS_V1_8822C BIT(19)\n#define BIT_NPQ_PUBLIC_DIS_V1_8822C BIT(18)\n#define BIT_LPQ_PUBLIC_DIS_V1_8822C BIT(17)\n#define BIT_HPQ_PUBLIC_DIS_V1_8822C BIT(16)\n#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_8822C BIT(15)\n\n#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C 0\n#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C 0xfff\n#define BIT_SDIO_TXAGG_ALIGN_SIZE_8822C(x)                                     \\\n\t(((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C)                          \\\n\t << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C)\n#define BITS_SDIO_TXAGG_ALIGN_SIZE_8822C                                       \\\n\t(BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C                                  \\\n\t << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C)\n#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8822C(x)                               \\\n\t((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_8822C))\n#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8822C(x)                                 \\\n\t(((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C) &                      \\\n\t BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C)\n#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_8822C(x, v)                              \\\n\t(BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8822C(x) |                            \\\n\t BIT_SDIO_TXAGG_ALIGN_SIZE_8822C(v))\n\n/* 2 REG_FIFOPAGE_INFO_1_8822C */\n\n#define BIT_SHIFT_HPQ_AVAL_PG_V1_8822C 16\n#define BIT_MASK_HPQ_AVAL_PG_V1_8822C 0xfff\n#define BIT_HPQ_AVAL_PG_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HPQ_AVAL_PG_V1_8822C)                                 \\\n\t << BIT_SHIFT_HPQ_AVAL_PG_V1_8822C)\n#define BITS_HPQ_AVAL_PG_V1_8822C                                              \\\n\t(BIT_MASK_HPQ_AVAL_PG_V1_8822C << BIT_SHIFT_HPQ_AVAL_PG_V1_8822C)\n#define BIT_CLEAR_HPQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8822C))\n#define BIT_GET_HPQ_AVAL_PG_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8822C) &                             \\\n\t BIT_MASK_HPQ_AVAL_PG_V1_8822C)\n#define BIT_SET_HPQ_AVAL_PG_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HPQ_AVAL_PG_V1_8822C(x) | BIT_HPQ_AVAL_PG_V1_8822C(v))\n\n#define BIT_SHIFT_HPQ_V1_8822C 0\n#define BIT_MASK_HPQ_V1_8822C 0xfff\n#define BIT_HPQ_V1_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_HPQ_V1_8822C) << BIT_SHIFT_HPQ_V1_8822C)\n#define BITS_HPQ_V1_8822C (BIT_MASK_HPQ_V1_8822C << BIT_SHIFT_HPQ_V1_8822C)\n#define BIT_CLEAR_HPQ_V1_8822C(x) ((x) & (~BITS_HPQ_V1_8822C))\n#define BIT_GET_HPQ_V1_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_HPQ_V1_8822C) & BIT_MASK_HPQ_V1_8822C)\n#define BIT_SET_HPQ_V1_8822C(x, v)                                             \\\n\t(BIT_CLEAR_HPQ_V1_8822C(x) | BIT_HPQ_V1_8822C(v))\n\n/* 2 REG_FIFOPAGE_INFO_2_8822C */\n\n#define BIT_SHIFT_LPQ_AVAL_PG_V1_8822C 16\n#define BIT_MASK_LPQ_AVAL_PG_V1_8822C 0xfff\n#define BIT_LPQ_AVAL_PG_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_LPQ_AVAL_PG_V1_8822C)                                 \\\n\t << BIT_SHIFT_LPQ_AVAL_PG_V1_8822C)\n#define BITS_LPQ_AVAL_PG_V1_8822C                                              \\\n\t(BIT_MASK_LPQ_AVAL_PG_V1_8822C << BIT_SHIFT_LPQ_AVAL_PG_V1_8822C)\n#define BIT_CLEAR_LPQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8822C))\n#define BIT_GET_LPQ_AVAL_PG_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8822C) &                             \\\n\t BIT_MASK_LPQ_AVAL_PG_V1_8822C)\n#define BIT_SET_LPQ_AVAL_PG_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_LPQ_AVAL_PG_V1_8822C(x) | BIT_LPQ_AVAL_PG_V1_8822C(v))\n\n#define BIT_SHIFT_LPQ_V1_8822C 0\n#define BIT_MASK_LPQ_V1_8822C 0xfff\n#define BIT_LPQ_V1_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_LPQ_V1_8822C) << BIT_SHIFT_LPQ_V1_8822C)\n#define BITS_LPQ_V1_8822C (BIT_MASK_LPQ_V1_8822C << BIT_SHIFT_LPQ_V1_8822C)\n#define BIT_CLEAR_LPQ_V1_8822C(x) ((x) & (~BITS_LPQ_V1_8822C))\n#define BIT_GET_LPQ_V1_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_LPQ_V1_8822C) & BIT_MASK_LPQ_V1_8822C)\n#define BIT_SET_LPQ_V1_8822C(x, v)                                             \\\n\t(BIT_CLEAR_LPQ_V1_8822C(x) | BIT_LPQ_V1_8822C(v))\n\n/* 2 REG_FIFOPAGE_INFO_3_8822C */\n\n#define BIT_SHIFT_NPQ_AVAL_PG_V1_8822C 16\n#define BIT_MASK_NPQ_AVAL_PG_V1_8822C 0xfff\n#define BIT_NPQ_AVAL_PG_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_NPQ_AVAL_PG_V1_8822C)                                 \\\n\t << BIT_SHIFT_NPQ_AVAL_PG_V1_8822C)\n#define BITS_NPQ_AVAL_PG_V1_8822C                                              \\\n\t(BIT_MASK_NPQ_AVAL_PG_V1_8822C << BIT_SHIFT_NPQ_AVAL_PG_V1_8822C)\n#define BIT_CLEAR_NPQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8822C))\n#define BIT_GET_NPQ_AVAL_PG_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8822C) &                             \\\n\t BIT_MASK_NPQ_AVAL_PG_V1_8822C)\n#define BIT_SET_NPQ_AVAL_PG_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_NPQ_AVAL_PG_V1_8822C(x) | BIT_NPQ_AVAL_PG_V1_8822C(v))\n\n#define BIT_SHIFT_NPQ_V1_8822C 0\n#define BIT_MASK_NPQ_V1_8822C 0xfff\n#define BIT_NPQ_V1_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_NPQ_V1_8822C) << BIT_SHIFT_NPQ_V1_8822C)\n#define BITS_NPQ_V1_8822C (BIT_MASK_NPQ_V1_8822C << BIT_SHIFT_NPQ_V1_8822C)\n#define BIT_CLEAR_NPQ_V1_8822C(x) ((x) & (~BITS_NPQ_V1_8822C))\n#define BIT_GET_NPQ_V1_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_NPQ_V1_8822C) & BIT_MASK_NPQ_V1_8822C)\n#define BIT_SET_NPQ_V1_8822C(x, v)                                             \\\n\t(BIT_CLEAR_NPQ_V1_8822C(x) | BIT_NPQ_V1_8822C(v))\n\n/* 2 REG_FIFOPAGE_INFO_4_8822C */\n\n#define BIT_SHIFT_EXQ_AVAL_PG_V1_8822C 16\n#define BIT_MASK_EXQ_AVAL_PG_V1_8822C 0xfff\n#define BIT_EXQ_AVAL_PG_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_EXQ_AVAL_PG_V1_8822C)                                 \\\n\t << BIT_SHIFT_EXQ_AVAL_PG_V1_8822C)\n#define BITS_EXQ_AVAL_PG_V1_8822C                                              \\\n\t(BIT_MASK_EXQ_AVAL_PG_V1_8822C << BIT_SHIFT_EXQ_AVAL_PG_V1_8822C)\n#define BIT_CLEAR_EXQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8822C))\n#define BIT_GET_EXQ_AVAL_PG_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8822C) &                             \\\n\t BIT_MASK_EXQ_AVAL_PG_V1_8822C)\n#define BIT_SET_EXQ_AVAL_PG_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_EXQ_AVAL_PG_V1_8822C(x) | BIT_EXQ_AVAL_PG_V1_8822C(v))\n\n#define BIT_SHIFT_EXQ_V1_8822C 0\n#define BIT_MASK_EXQ_V1_8822C 0xfff\n#define BIT_EXQ_V1_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_EXQ_V1_8822C) << BIT_SHIFT_EXQ_V1_8822C)\n#define BITS_EXQ_V1_8822C (BIT_MASK_EXQ_V1_8822C << BIT_SHIFT_EXQ_V1_8822C)\n#define BIT_CLEAR_EXQ_V1_8822C(x) ((x) & (~BITS_EXQ_V1_8822C))\n#define BIT_GET_EXQ_V1_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_EXQ_V1_8822C) & BIT_MASK_EXQ_V1_8822C)\n#define BIT_SET_EXQ_V1_8822C(x, v)                                             \\\n\t(BIT_CLEAR_EXQ_V1_8822C(x) | BIT_EXQ_V1_8822C(v))\n\n/* 2 REG_FIFOPAGE_INFO_5_8822C */\n\n#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C 16\n#define BIT_MASK_PUBQ_AVAL_PG_V1_8822C 0xfff\n#define BIT_PUBQ_AVAL_PG_V1_8822C(x)                                           \\\n\t(((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8822C)                                \\\n\t << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C)\n#define BITS_PUBQ_AVAL_PG_V1_8822C                                             \\\n\t(BIT_MASK_PUBQ_AVAL_PG_V1_8822C << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C)\n#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8822C))\n#define BIT_GET_PUBQ_AVAL_PG_V1_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C) &                            \\\n\t BIT_MASK_PUBQ_AVAL_PG_V1_8822C)\n#define BIT_SET_PUBQ_AVAL_PG_V1_8822C(x, v)                                    \\\n\t(BIT_CLEAR_PUBQ_AVAL_PG_V1_8822C(x) | BIT_PUBQ_AVAL_PG_V1_8822C(v))\n\n#define BIT_SHIFT_PUBQ_V1_8822C 0\n#define BIT_MASK_PUBQ_V1_8822C 0xfff\n#define BIT_PUBQ_V1_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_PUBQ_V1_8822C) << BIT_SHIFT_PUBQ_V1_8822C)\n#define BITS_PUBQ_V1_8822C (BIT_MASK_PUBQ_V1_8822C << BIT_SHIFT_PUBQ_V1_8822C)\n#define BIT_CLEAR_PUBQ_V1_8822C(x) ((x) & (~BITS_PUBQ_V1_8822C))\n#define BIT_GET_PUBQ_V1_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_PUBQ_V1_8822C) & BIT_MASK_PUBQ_V1_8822C)\n#define BIT_SET_PUBQ_V1_8822C(x, v)                                            \\\n\t(BIT_CLEAR_PUBQ_V1_8822C(x) | BIT_PUBQ_V1_8822C(v))\n\n/* 2 REG_H2C_HEAD_8822C */\n\n#define BIT_SHIFT_H2C_HEAD_8822C 0\n#define BIT_MASK_H2C_HEAD_8822C 0x3ffff\n#define BIT_H2C_HEAD_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_H2C_HEAD_8822C) << BIT_SHIFT_H2C_HEAD_8822C)\n#define BITS_H2C_HEAD_8822C                                                    \\\n\t(BIT_MASK_H2C_HEAD_8822C << BIT_SHIFT_H2C_HEAD_8822C)\n#define BIT_CLEAR_H2C_HEAD_8822C(x) ((x) & (~BITS_H2C_HEAD_8822C))\n#define BIT_GET_H2C_HEAD_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_H2C_HEAD_8822C) & BIT_MASK_H2C_HEAD_8822C)\n#define BIT_SET_H2C_HEAD_8822C(x, v)                                           \\\n\t(BIT_CLEAR_H2C_HEAD_8822C(x) | BIT_H2C_HEAD_8822C(v))\n\n/* 2 REG_H2C_TAIL_8822C */\n\n#define BIT_SHIFT_H2C_TAIL_8822C 0\n#define BIT_MASK_H2C_TAIL_8822C 0x3ffff\n#define BIT_H2C_TAIL_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_H2C_TAIL_8822C) << BIT_SHIFT_H2C_TAIL_8822C)\n#define BITS_H2C_TAIL_8822C                                                    \\\n\t(BIT_MASK_H2C_TAIL_8822C << BIT_SHIFT_H2C_TAIL_8822C)\n#define BIT_CLEAR_H2C_TAIL_8822C(x) ((x) & (~BITS_H2C_TAIL_8822C))\n#define BIT_GET_H2C_TAIL_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_H2C_TAIL_8822C) & BIT_MASK_H2C_TAIL_8822C)\n#define BIT_SET_H2C_TAIL_8822C(x, v)                                           \\\n\t(BIT_CLEAR_H2C_TAIL_8822C(x) | BIT_H2C_TAIL_8822C(v))\n\n/* 2 REG_H2C_READ_ADDR_8822C */\n\n#define BIT_SHIFT_H2C_READ_ADDR_8822C 0\n#define BIT_MASK_H2C_READ_ADDR_8822C 0x3ffff\n#define BIT_H2C_READ_ADDR_8822C(x)                                             \\\n\t(((x) & BIT_MASK_H2C_READ_ADDR_8822C) << BIT_SHIFT_H2C_READ_ADDR_8822C)\n#define BITS_H2C_READ_ADDR_8822C                                               \\\n\t(BIT_MASK_H2C_READ_ADDR_8822C << BIT_SHIFT_H2C_READ_ADDR_8822C)\n#define BIT_CLEAR_H2C_READ_ADDR_8822C(x) ((x) & (~BITS_H2C_READ_ADDR_8822C))\n#define BIT_GET_H2C_READ_ADDR_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_H2C_READ_ADDR_8822C) & BIT_MASK_H2C_READ_ADDR_8822C)\n#define BIT_SET_H2C_READ_ADDR_8822C(x, v)                                      \\\n\t(BIT_CLEAR_H2C_READ_ADDR_8822C(x) | BIT_H2C_READ_ADDR_8822C(v))\n\n/* 2 REG_H2C_WR_ADDR_8822C */\n\n#define BIT_SHIFT_H2C_WR_ADDR_8822C 0\n#define BIT_MASK_H2C_WR_ADDR_8822C 0x3ffff\n#define BIT_H2C_WR_ADDR_8822C(x)                                               \\\n\t(((x) & BIT_MASK_H2C_WR_ADDR_8822C) << BIT_SHIFT_H2C_WR_ADDR_8822C)\n#define BITS_H2C_WR_ADDR_8822C                                                 \\\n\t(BIT_MASK_H2C_WR_ADDR_8822C << BIT_SHIFT_H2C_WR_ADDR_8822C)\n#define BIT_CLEAR_H2C_WR_ADDR_8822C(x) ((x) & (~BITS_H2C_WR_ADDR_8822C))\n#define BIT_GET_H2C_WR_ADDR_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_H2C_WR_ADDR_8822C) & BIT_MASK_H2C_WR_ADDR_8822C)\n#define BIT_SET_H2C_WR_ADDR_8822C(x, v)                                        \\\n\t(BIT_CLEAR_H2C_WR_ADDR_8822C(x) | BIT_H2C_WR_ADDR_8822C(v))\n\n/* 2 REG_H2C_INFO_8822C */\n#define BIT_H2C_SPACE_VLD_8822C BIT(3)\n#define BIT_H2C_WR_ADDR_RST_8822C BIT(2)\n\n#define BIT_SHIFT_H2C_LEN_SEL_8822C 0\n#define BIT_MASK_H2C_LEN_SEL_8822C 0x3\n#define BIT_H2C_LEN_SEL_8822C(x)                                               \\\n\t(((x) & BIT_MASK_H2C_LEN_SEL_8822C) << BIT_SHIFT_H2C_LEN_SEL_8822C)\n#define BITS_H2C_LEN_SEL_8822C                                                 \\\n\t(BIT_MASK_H2C_LEN_SEL_8822C << BIT_SHIFT_H2C_LEN_SEL_8822C)\n#define BIT_CLEAR_H2C_LEN_SEL_8822C(x) ((x) & (~BITS_H2C_LEN_SEL_8822C))\n#define BIT_GET_H2C_LEN_SEL_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_H2C_LEN_SEL_8822C) & BIT_MASK_H2C_LEN_SEL_8822C)\n#define BIT_SET_H2C_LEN_SEL_8822C(x, v)                                        \\\n\t(BIT_CLEAR_H2C_LEN_SEL_8822C(x) | BIT_H2C_LEN_SEL_8822C(v))\n\n/* 2 REG_PGSUB_CNT_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_RST_PGSUB_CNT_8822C BIT(1)\n#define BIT_PGSUB_CNT_EN_8822C BIT(0)\n\n/* 2 REG_PGSUB_H_8822C */\n\n#define BIT_SHIFT_HPQ_PGSUB_CNT_8822C 0\n#define BIT_MASK_HPQ_PGSUB_CNT_8822C 0xffffffffL\n#define BIT_HPQ_PGSUB_CNT_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HPQ_PGSUB_CNT_8822C) << BIT_SHIFT_HPQ_PGSUB_CNT_8822C)\n#define BITS_HPQ_PGSUB_CNT_8822C                                               \\\n\t(BIT_MASK_HPQ_PGSUB_CNT_8822C << BIT_SHIFT_HPQ_PGSUB_CNT_8822C)\n#define BIT_CLEAR_HPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_HPQ_PGSUB_CNT_8822C))\n#define BIT_GET_HPQ_PGSUB_CNT_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HPQ_PGSUB_CNT_8822C) & BIT_MASK_HPQ_PGSUB_CNT_8822C)\n#define BIT_SET_HPQ_PGSUB_CNT_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HPQ_PGSUB_CNT_8822C(x) | BIT_HPQ_PGSUB_CNT_8822C(v))\n\n/* 2 REG_PGSUB_N_8822C */\n\n#define BIT_SHIFT_NPQ_PGSUB_CNT_8822C 0\n#define BIT_MASK_NPQ_PGSUB_CNT_8822C 0xffffffffL\n#define BIT_NPQ_PGSUB_CNT_8822C(x)                                             \\\n\t(((x) & BIT_MASK_NPQ_PGSUB_CNT_8822C) << BIT_SHIFT_NPQ_PGSUB_CNT_8822C)\n#define BITS_NPQ_PGSUB_CNT_8822C                                               \\\n\t(BIT_MASK_NPQ_PGSUB_CNT_8822C << BIT_SHIFT_NPQ_PGSUB_CNT_8822C)\n#define BIT_CLEAR_NPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_NPQ_PGSUB_CNT_8822C))\n#define BIT_GET_NPQ_PGSUB_CNT_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_NPQ_PGSUB_CNT_8822C) & BIT_MASK_NPQ_PGSUB_CNT_8822C)\n#define BIT_SET_NPQ_PGSUB_CNT_8822C(x, v)                                      \\\n\t(BIT_CLEAR_NPQ_PGSUB_CNT_8822C(x) | BIT_NPQ_PGSUB_CNT_8822C(v))\n\n/* 2 REG_PGSUB_L_8822C */\n\n#define BIT_SHIFT_LPQ_PGSUB_CNT_8822C 0\n#define BIT_MASK_LPQ_PGSUB_CNT_8822C 0xffffffffL\n#define BIT_LPQ_PGSUB_CNT_8822C(x)                                             \\\n\t(((x) & BIT_MASK_LPQ_PGSUB_CNT_8822C) << BIT_SHIFT_LPQ_PGSUB_CNT_8822C)\n#define BITS_LPQ_PGSUB_CNT_8822C                                               \\\n\t(BIT_MASK_LPQ_PGSUB_CNT_8822C << BIT_SHIFT_LPQ_PGSUB_CNT_8822C)\n#define BIT_CLEAR_LPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_LPQ_PGSUB_CNT_8822C))\n#define BIT_GET_LPQ_PGSUB_CNT_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_LPQ_PGSUB_CNT_8822C) & BIT_MASK_LPQ_PGSUB_CNT_8822C)\n#define BIT_SET_LPQ_PGSUB_CNT_8822C(x, v)                                      \\\n\t(BIT_CLEAR_LPQ_PGSUB_CNT_8822C(x) | BIT_LPQ_PGSUB_CNT_8822C(v))\n\n/* 2 REG_PGSUB_E_8822C */\n\n#define BIT_SHIFT_EPQ_PGSUB_CNT_8822C 0\n#define BIT_MASK_EPQ_PGSUB_CNT_8822C 0xffffffffL\n#define BIT_EPQ_PGSUB_CNT_8822C(x)                                             \\\n\t(((x) & BIT_MASK_EPQ_PGSUB_CNT_8822C) << BIT_SHIFT_EPQ_PGSUB_CNT_8822C)\n#define BITS_EPQ_PGSUB_CNT_8822C                                               \\\n\t(BIT_MASK_EPQ_PGSUB_CNT_8822C << BIT_SHIFT_EPQ_PGSUB_CNT_8822C)\n#define BIT_CLEAR_EPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_EPQ_PGSUB_CNT_8822C))\n#define BIT_GET_EPQ_PGSUB_CNT_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_EPQ_PGSUB_CNT_8822C) & BIT_MASK_EPQ_PGSUB_CNT_8822C)\n#define BIT_SET_EPQ_PGSUB_CNT_8822C(x, v)                                      \\\n\t(BIT_CLEAR_EPQ_PGSUB_CNT_8822C(x) | BIT_EPQ_PGSUB_CNT_8822C(v))\n\n/* 2 REG_RXDMA_AGG_PG_TH_8822C */\n#define BIT_USB_RXDMA_AGG_EN_8822C BIT(31)\n#define BIT_EN_FW_ADD_8822C BIT(30)\n#define BIT_EN_PRE_CALC_8822C BIT(29)\n#define BIT_RXAGG_SW_EN_8822C BIT(28)\n#define BIT_RXAGG_SW_TRIG_8822C BIT(27)\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_DMA_AGG_TO_V1_8822C 8\n#define BIT_MASK_DMA_AGG_TO_V1_8822C 0xff\n#define BIT_DMA_AGG_TO_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_DMA_AGG_TO_V1_8822C) << BIT_SHIFT_DMA_AGG_TO_V1_8822C)\n#define BITS_DMA_AGG_TO_V1_8822C                                               \\\n\t(BIT_MASK_DMA_AGG_TO_V1_8822C << BIT_SHIFT_DMA_AGG_TO_V1_8822C)\n#define BIT_CLEAR_DMA_AGG_TO_V1_8822C(x) ((x) & (~BITS_DMA_AGG_TO_V1_8822C))\n#define BIT_GET_DMA_AGG_TO_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8822C) & BIT_MASK_DMA_AGG_TO_V1_8822C)\n#define BIT_SET_DMA_AGG_TO_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_DMA_AGG_TO_V1_8822C(x) | BIT_DMA_AGG_TO_V1_8822C(v))\n\n#define BIT_SHIFT_RXDMA_AGG_PG_TH_8822C 0\n#define BIT_MASK_RXDMA_AGG_PG_TH_8822C 0xff\n#define BIT_RXDMA_AGG_PG_TH_8822C(x)                                           \\\n\t(((x) & BIT_MASK_RXDMA_AGG_PG_TH_8822C)                                \\\n\t << BIT_SHIFT_RXDMA_AGG_PG_TH_8822C)\n#define BITS_RXDMA_AGG_PG_TH_8822C                                             \\\n\t(BIT_MASK_RXDMA_AGG_PG_TH_8822C << BIT_SHIFT_RXDMA_AGG_PG_TH_8822C)\n#define BIT_CLEAR_RXDMA_AGG_PG_TH_8822C(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8822C))\n#define BIT_GET_RXDMA_AGG_PG_TH_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8822C) &                            \\\n\t BIT_MASK_RXDMA_AGG_PG_TH_8822C)\n#define BIT_SET_RXDMA_AGG_PG_TH_8822C(x, v)                                    \\\n\t(BIT_CLEAR_RXDMA_AGG_PG_TH_8822C(x) | BIT_RXDMA_AGG_PG_TH_8822C(v))\n\n/* 2 REG_RXPKT_NUM_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C 20\n#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C 0xf\n#define BIT_FW_UPD_RDPTR19_TO_16_8822C(x)                                      \\\n\t(((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C)                           \\\n\t << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C)\n#define BITS_FW_UPD_RDPTR19_TO_16_8822C                                        \\\n\t(BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C                                   \\\n\t << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C)\n#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822C(x)                                \\\n\t((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8822C))\n#define BIT_GET_FW_UPD_RDPTR19_TO_16_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C) &                       \\\n\t BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C)\n#define BIT_SET_FW_UPD_RDPTR19_TO_16_8822C(x, v)                               \\\n\t(BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822C(x) |                             \\\n\t BIT_FW_UPD_RDPTR19_TO_16_8822C(v))\n\n#define BIT_RXDMA_REQ_8822C BIT(19)\n#define BIT_RW_RELEASE_EN_8822C BIT(18)\n#define BIT_RXDMA_IDLE_8822C BIT(17)\n#define BIT_RXPKT_RELEASE_POLL_8822C BIT(16)\n\n#define BIT_SHIFT_FW_UPD_RDPTR_8822C 0\n#define BIT_MASK_FW_UPD_RDPTR_8822C 0xffff\n#define BIT_FW_UPD_RDPTR_8822C(x)                                              \\\n\t(((x) & BIT_MASK_FW_UPD_RDPTR_8822C) << BIT_SHIFT_FW_UPD_RDPTR_8822C)\n#define BITS_FW_UPD_RDPTR_8822C                                                \\\n\t(BIT_MASK_FW_UPD_RDPTR_8822C << BIT_SHIFT_FW_UPD_RDPTR_8822C)\n#define BIT_CLEAR_FW_UPD_RDPTR_8822C(x) ((x) & (~BITS_FW_UPD_RDPTR_8822C))\n#define BIT_GET_FW_UPD_RDPTR_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_FW_UPD_RDPTR_8822C) & BIT_MASK_FW_UPD_RDPTR_8822C)\n#define BIT_SET_FW_UPD_RDPTR_8822C(x, v)                                       \\\n\t(BIT_CLEAR_FW_UPD_RDPTR_8822C(x) | BIT_FW_UPD_RDPTR_8822C(v))\n\n/* 2 REG_RXDMA_STATUS_8822C */\n#define BIT_C2H_PKT_OVF_8822C BIT(7)\n#define BIT_AGG_CONFGI_ISSUE_8822C BIT(6)\n#define BIT_FW_POLL_ISSUE_8822C BIT(5)\n#define BIT_RX_DATA_UDN_8822C BIT(4)\n#define BIT_RX_SFF_UDN_8822C BIT(3)\n#define BIT_RX_SFF_OVF_8822C BIT(2)\n#define BIT_RXPKT_OVF_8822C BIT(0)\n\n/* 2 REG_RXDMA_DPR_8822C */\n\n#define BIT_SHIFT_RDE_DEBUG_8822C 0\n#define BIT_MASK_RDE_DEBUG_8822C 0xffffffffL\n#define BIT_RDE_DEBUG_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_RDE_DEBUG_8822C) << BIT_SHIFT_RDE_DEBUG_8822C)\n#define BITS_RDE_DEBUG_8822C                                                   \\\n\t(BIT_MASK_RDE_DEBUG_8822C << BIT_SHIFT_RDE_DEBUG_8822C)\n#define BIT_CLEAR_RDE_DEBUG_8822C(x) ((x) & (~BITS_RDE_DEBUG_8822C))\n#define BIT_GET_RDE_DEBUG_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_RDE_DEBUG_8822C) & BIT_MASK_RDE_DEBUG_8822C)\n#define BIT_SET_RDE_DEBUG_8822C(x, v)                                          \\\n\t(BIT_CLEAR_RDE_DEBUG_8822C(x) | BIT_RDE_DEBUG_8822C(v))\n\n/* 2 REG_RXDMA_MODE_8822C */\n\n#define BIT_SHIFT_PKTNUM_TH_V2_8822C 24\n#define BIT_MASK_PKTNUM_TH_V2_8822C 0x1f\n#define BIT_PKTNUM_TH_V2_8822C(x)                                              \\\n\t(((x) & BIT_MASK_PKTNUM_TH_V2_8822C) << BIT_SHIFT_PKTNUM_TH_V2_8822C)\n#define BITS_PKTNUM_TH_V2_8822C                                                \\\n\t(BIT_MASK_PKTNUM_TH_V2_8822C << BIT_SHIFT_PKTNUM_TH_V2_8822C)\n#define BIT_CLEAR_PKTNUM_TH_V2_8822C(x) ((x) & (~BITS_PKTNUM_TH_V2_8822C))\n#define BIT_GET_PKTNUM_TH_V2_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_PKTNUM_TH_V2_8822C) & BIT_MASK_PKTNUM_TH_V2_8822C)\n#define BIT_SET_PKTNUM_TH_V2_8822C(x, v)                                       \\\n\t(BIT_CLEAR_PKTNUM_TH_V2_8822C(x) | BIT_PKTNUM_TH_V2_8822C(v))\n\n#define BIT_TXBA_BREAK_USBAGG_8822C BIT(23)\n\n#define BIT_SHIFT_PKTLEN_PARA_8822C 16\n#define BIT_MASK_PKTLEN_PARA_8822C 0x7\n#define BIT_PKTLEN_PARA_8822C(x)                                               \\\n\t(((x) & BIT_MASK_PKTLEN_PARA_8822C) << BIT_SHIFT_PKTLEN_PARA_8822C)\n#define BITS_PKTLEN_PARA_8822C                                                 \\\n\t(BIT_MASK_PKTLEN_PARA_8822C << BIT_SHIFT_PKTLEN_PARA_8822C)\n#define BIT_CLEAR_PKTLEN_PARA_8822C(x) ((x) & (~BITS_PKTLEN_PARA_8822C))\n#define BIT_GET_PKTLEN_PARA_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_PKTLEN_PARA_8822C) & BIT_MASK_PKTLEN_PARA_8822C)\n#define BIT_SET_PKTLEN_PARA_8822C(x, v)                                        \\\n\t(BIT_CLEAR_PKTLEN_PARA_8822C(x) | BIT_PKTLEN_PARA_8822C(v))\n\n#define BIT_RX_DBG_SEL_8822C BIT(7)\n#define BIT_EN_SPD_8822C BIT(6)\n\n#define BIT_SHIFT_BURST_SIZE_8822C 4\n#define BIT_MASK_BURST_SIZE_8822C 0x3\n#define BIT_BURST_SIZE_8822C(x)                                                \\\n\t(((x) & BIT_MASK_BURST_SIZE_8822C) << BIT_SHIFT_BURST_SIZE_8822C)\n#define BITS_BURST_SIZE_8822C                                                  \\\n\t(BIT_MASK_BURST_SIZE_8822C << BIT_SHIFT_BURST_SIZE_8822C)\n#define BIT_CLEAR_BURST_SIZE_8822C(x) ((x) & (~BITS_BURST_SIZE_8822C))\n#define BIT_GET_BURST_SIZE_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BURST_SIZE_8822C) & BIT_MASK_BURST_SIZE_8822C)\n#define BIT_SET_BURST_SIZE_8822C(x, v)                                         \\\n\t(BIT_CLEAR_BURST_SIZE_8822C(x) | BIT_BURST_SIZE_8822C(v))\n\n#define BIT_SHIFT_BURST_CNT_8822C 2\n#define BIT_MASK_BURST_CNT_8822C 0x3\n#define BIT_BURST_CNT_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_BURST_CNT_8822C) << BIT_SHIFT_BURST_CNT_8822C)\n#define BITS_BURST_CNT_8822C                                                   \\\n\t(BIT_MASK_BURST_CNT_8822C << BIT_SHIFT_BURST_CNT_8822C)\n#define BIT_CLEAR_BURST_CNT_8822C(x) ((x) & (~BITS_BURST_CNT_8822C))\n#define BIT_GET_BURST_CNT_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_BURST_CNT_8822C) & BIT_MASK_BURST_CNT_8822C)\n#define BIT_SET_BURST_CNT_8822C(x, v)                                          \\\n\t(BIT_CLEAR_BURST_CNT_8822C(x) | BIT_BURST_CNT_8822C(v))\n\n#define BIT_DMA_MODE_8822C BIT(1)\n\n/* 2 REG_C2H_PKT_8822C */\n\n#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C 24\n#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C 0xf\n#define BIT_R_C2H_STR_ADDR_16_TO_19_8822C(x)                                   \\\n\t(((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C)                        \\\n\t << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C)\n#define BITS_R_C2H_STR_ADDR_16_TO_19_8822C                                     \\\n\t(BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C                                \\\n\t << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C)\n#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822C(x)                             \\\n\t((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8822C))\n#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8822C(x)                               \\\n\t(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C) &                    \\\n\t BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C)\n#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8822C(x, v)                            \\\n\t(BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822C(x) |                          \\\n\t BIT_R_C2H_STR_ADDR_16_TO_19_8822C(v))\n\n#define BIT_R_C2H_PKT_REQ_8822C BIT(16)\n\n#define BIT_SHIFT_R_C2H_STR_ADDR_8822C 0\n#define BIT_MASK_R_C2H_STR_ADDR_8822C 0xffff\n#define BIT_R_C2H_STR_ADDR_8822C(x)                                            \\\n\t(((x) & BIT_MASK_R_C2H_STR_ADDR_8822C)                                 \\\n\t << BIT_SHIFT_R_C2H_STR_ADDR_8822C)\n#define BITS_R_C2H_STR_ADDR_8822C                                              \\\n\t(BIT_MASK_R_C2H_STR_ADDR_8822C << BIT_SHIFT_R_C2H_STR_ADDR_8822C)\n#define BIT_CLEAR_R_C2H_STR_ADDR_8822C(x) ((x) & (~BITS_R_C2H_STR_ADDR_8822C))\n#define BIT_GET_R_C2H_STR_ADDR_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8822C) &                             \\\n\t BIT_MASK_R_C2H_STR_ADDR_8822C)\n#define BIT_SET_R_C2H_STR_ADDR_8822C(x, v)                                     \\\n\t(BIT_CLEAR_R_C2H_STR_ADDR_8822C(x) | BIT_R_C2H_STR_ADDR_8822C(v))\n\n/* 2 REG_FWFF_C2H_8822C */\n\n#define BIT_SHIFT_C2H_DMA_ADDR_8822C 0\n#define BIT_MASK_C2H_DMA_ADDR_8822C 0x3ffff\n#define BIT_C2H_DMA_ADDR_8822C(x)                                              \\\n\t(((x) & BIT_MASK_C2H_DMA_ADDR_8822C) << BIT_SHIFT_C2H_DMA_ADDR_8822C)\n#define BITS_C2H_DMA_ADDR_8822C                                                \\\n\t(BIT_MASK_C2H_DMA_ADDR_8822C << BIT_SHIFT_C2H_DMA_ADDR_8822C)\n#define BIT_CLEAR_C2H_DMA_ADDR_8822C(x) ((x) & (~BITS_C2H_DMA_ADDR_8822C))\n#define BIT_GET_C2H_DMA_ADDR_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_C2H_DMA_ADDR_8822C) & BIT_MASK_C2H_DMA_ADDR_8822C)\n#define BIT_SET_C2H_DMA_ADDR_8822C(x, v)                                       \\\n\t(BIT_CLEAR_C2H_DMA_ADDR_8822C(x) | BIT_C2H_DMA_ADDR_8822C(v))\n\n/* 2 REG_FWFF_CTRL_8822C */\n#define BIT_FWFF_DMAPKT_REQ_8822C BIT(31)\n\n#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C 16\n#define BIT_MASK_FWFF_DMA_PKT_NUM_8822C 0xff\n#define BIT_FWFF_DMA_PKT_NUM_8822C(x)                                          \\\n\t(((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8822C)                               \\\n\t << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C)\n#define BITS_FWFF_DMA_PKT_NUM_8822C                                            \\\n\t(BIT_MASK_FWFF_DMA_PKT_NUM_8822C << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C)\n#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8822C(x)                                    \\\n\t((x) & (~BITS_FWFF_DMA_PKT_NUM_8822C))\n#define BIT_GET_FWFF_DMA_PKT_NUM_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C) &                           \\\n\t BIT_MASK_FWFF_DMA_PKT_NUM_8822C)\n#define BIT_SET_FWFF_DMA_PKT_NUM_8822C(x, v)                                   \\\n\t(BIT_CLEAR_FWFF_DMA_PKT_NUM_8822C(x) | BIT_FWFF_DMA_PKT_NUM_8822C(v))\n\n#define BIT_SHIFT_FWFF_STR_ADDR_8822C 0\n#define BIT_MASK_FWFF_STR_ADDR_8822C 0xffff\n#define BIT_FWFF_STR_ADDR_8822C(x)                                             \\\n\t(((x) & BIT_MASK_FWFF_STR_ADDR_8822C) << BIT_SHIFT_FWFF_STR_ADDR_8822C)\n#define BITS_FWFF_STR_ADDR_8822C                                               \\\n\t(BIT_MASK_FWFF_STR_ADDR_8822C << BIT_SHIFT_FWFF_STR_ADDR_8822C)\n#define BIT_CLEAR_FWFF_STR_ADDR_8822C(x) ((x) & (~BITS_FWFF_STR_ADDR_8822C))\n#define BIT_GET_FWFF_STR_ADDR_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_FWFF_STR_ADDR_8822C) & BIT_MASK_FWFF_STR_ADDR_8822C)\n#define BIT_SET_FWFF_STR_ADDR_8822C(x, v)                                      \\\n\t(BIT_CLEAR_FWFF_STR_ADDR_8822C(x) | BIT_FWFF_STR_ADDR_8822C(v))\n\n/* 2 REG_FWFF_PKT_INFO_8822C */\n\n#define BIT_SHIFT_FWFF_PKT_QUEUED_8822C 16\n#define BIT_MASK_FWFF_PKT_QUEUED_8822C 0xff\n#define BIT_FWFF_PKT_QUEUED_8822C(x)                                           \\\n\t(((x) & BIT_MASK_FWFF_PKT_QUEUED_8822C)                                \\\n\t << BIT_SHIFT_FWFF_PKT_QUEUED_8822C)\n#define BITS_FWFF_PKT_QUEUED_8822C                                             \\\n\t(BIT_MASK_FWFF_PKT_QUEUED_8822C << BIT_SHIFT_FWFF_PKT_QUEUED_8822C)\n#define BIT_CLEAR_FWFF_PKT_QUEUED_8822C(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8822C))\n#define BIT_GET_FWFF_PKT_QUEUED_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8822C) &                            \\\n\t BIT_MASK_FWFF_PKT_QUEUED_8822C)\n#define BIT_SET_FWFF_PKT_QUEUED_8822C(x, v)                                    \\\n\t(BIT_CLEAR_FWFF_PKT_QUEUED_8822C(x) | BIT_FWFF_PKT_QUEUED_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C 0\n#define BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C 0x3fff\n#define BIT_FWFF_PKT_STR_ADDR_V2_8822C(x)                                      \\\n\t(((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C)                           \\\n\t << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C)\n#define BITS_FWFF_PKT_STR_ADDR_V2_8822C                                        \\\n\t(BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C                                   \\\n\t << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C)\n#define BIT_CLEAR_FWFF_PKT_STR_ADDR_V2_8822C(x)                                \\\n\t((x) & (~BITS_FWFF_PKT_STR_ADDR_V2_8822C))\n#define BIT_GET_FWFF_PKT_STR_ADDR_V2_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C) &                       \\\n\t BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C)\n#define BIT_SET_FWFF_PKT_STR_ADDR_V2_8822C(x, v)                               \\\n\t(BIT_CLEAR_FWFF_PKT_STR_ADDR_V2_8822C(x) |                             \\\n\t BIT_FWFF_PKT_STR_ADDR_V2_8822C(v))\n\n/* 2 REG_RXPKTNUM_8822C */\n\n#define BIT_SHIFT_PKT_NUM_WOL_V1_8822C 16\n#define BIT_MASK_PKT_NUM_WOL_V1_8822C 0xffff\n#define BIT_PKT_NUM_WOL_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_PKT_NUM_WOL_V1_8822C)                                 \\\n\t << BIT_SHIFT_PKT_NUM_WOL_V1_8822C)\n#define BITS_PKT_NUM_WOL_V1_8822C                                              \\\n\t(BIT_MASK_PKT_NUM_WOL_V1_8822C << BIT_SHIFT_PKT_NUM_WOL_V1_8822C)\n#define BIT_CLEAR_PKT_NUM_WOL_V1_8822C(x) ((x) & (~BITS_PKT_NUM_WOL_V1_8822C))\n#define BIT_GET_PKT_NUM_WOL_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_PKT_NUM_WOL_V1_8822C) &                             \\\n\t BIT_MASK_PKT_NUM_WOL_V1_8822C)\n#define BIT_SET_PKT_NUM_WOL_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_PKT_NUM_WOL_V1_8822C(x) | BIT_PKT_NUM_WOL_V1_8822C(v))\n\n#define BIT_SHIFT_RXPKT_NUM_V1_8822C 0\n#define BIT_MASK_RXPKT_NUM_V1_8822C 0xffff\n#define BIT_RXPKT_NUM_V1_8822C(x)                                              \\\n\t(((x) & BIT_MASK_RXPKT_NUM_V1_8822C) << BIT_SHIFT_RXPKT_NUM_V1_8822C)\n#define BITS_RXPKT_NUM_V1_8822C                                                \\\n\t(BIT_MASK_RXPKT_NUM_V1_8822C << BIT_SHIFT_RXPKT_NUM_V1_8822C)\n#define BIT_CLEAR_RXPKT_NUM_V1_8822C(x) ((x) & (~BITS_RXPKT_NUM_V1_8822C))\n#define BIT_GET_RXPKT_NUM_V1_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXPKT_NUM_V1_8822C) & BIT_MASK_RXPKT_NUM_V1_8822C)\n#define BIT_SET_RXPKT_NUM_V1_8822C(x, v)                                       \\\n\t(BIT_CLEAR_RXPKT_NUM_V1_8822C(x) | BIT_RXPKT_NUM_V1_8822C(v))\n\n/* 2 REG_RXPKTNUM_TH_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_RXPKT_NUM_TH_8822C 0\n#define BIT_MASK_RXPKT_NUM_TH_8822C 0xff\n#define BIT_RXPKT_NUM_TH_8822C(x)                                              \\\n\t(((x) & BIT_MASK_RXPKT_NUM_TH_8822C) << BIT_SHIFT_RXPKT_NUM_TH_8822C)\n#define BITS_RXPKT_NUM_TH_8822C                                                \\\n\t(BIT_MASK_RXPKT_NUM_TH_8822C << BIT_SHIFT_RXPKT_NUM_TH_8822C)\n#define BIT_CLEAR_RXPKT_NUM_TH_8822C(x) ((x) & (~BITS_RXPKT_NUM_TH_8822C))\n#define BIT_GET_RXPKT_NUM_TH_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXPKT_NUM_TH_8822C) & BIT_MASK_RXPKT_NUM_TH_8822C)\n#define BIT_SET_RXPKT_NUM_TH_8822C(x, v)                                       \\\n\t(BIT_CLEAR_RXPKT_NUM_TH_8822C(x) | BIT_RXPKT_NUM_TH_8822C(v))\n\n/* 2 REG_FW_MSG1_8822C */\n\n#define BIT_SHIFT_FW_MSG_REG1_8822C 0\n#define BIT_MASK_FW_MSG_REG1_8822C 0xffffffffL\n#define BIT_FW_MSG_REG1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_FW_MSG_REG1_8822C) << BIT_SHIFT_FW_MSG_REG1_8822C)\n#define BITS_FW_MSG_REG1_8822C                                                 \\\n\t(BIT_MASK_FW_MSG_REG1_8822C << BIT_SHIFT_FW_MSG_REG1_8822C)\n#define BIT_CLEAR_FW_MSG_REG1_8822C(x) ((x) & (~BITS_FW_MSG_REG1_8822C))\n#define BIT_GET_FW_MSG_REG1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_FW_MSG_REG1_8822C) & BIT_MASK_FW_MSG_REG1_8822C)\n#define BIT_SET_FW_MSG_REG1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_FW_MSG_REG1_8822C(x) | BIT_FW_MSG_REG1_8822C(v))\n\n/* 2 REG_FW_MSG2_8822C */\n\n#define BIT_SHIFT_FW_MSG_REG2_8822C 0\n#define BIT_MASK_FW_MSG_REG2_8822C 0xffffffffL\n#define BIT_FW_MSG_REG2_8822C(x)                                               \\\n\t(((x) & BIT_MASK_FW_MSG_REG2_8822C) << BIT_SHIFT_FW_MSG_REG2_8822C)\n#define BITS_FW_MSG_REG2_8822C                                                 \\\n\t(BIT_MASK_FW_MSG_REG2_8822C << BIT_SHIFT_FW_MSG_REG2_8822C)\n#define BIT_CLEAR_FW_MSG_REG2_8822C(x) ((x) & (~BITS_FW_MSG_REG2_8822C))\n#define BIT_GET_FW_MSG_REG2_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_FW_MSG_REG2_8822C) & BIT_MASK_FW_MSG_REG2_8822C)\n#define BIT_SET_FW_MSG_REG2_8822C(x, v)                                        \\\n\t(BIT_CLEAR_FW_MSG_REG2_8822C(x) | BIT_FW_MSG_REG2_8822C(v))\n\n/* 2 REG_FW_MSG3_8822C */\n\n#define BIT_SHIFT_FW_MSG_REG3_8822C 0\n#define BIT_MASK_FW_MSG_REG3_8822C 0xffffffffL\n#define BIT_FW_MSG_REG3_8822C(x)                                               \\\n\t(((x) & BIT_MASK_FW_MSG_REG3_8822C) << BIT_SHIFT_FW_MSG_REG3_8822C)\n#define BITS_FW_MSG_REG3_8822C                                                 \\\n\t(BIT_MASK_FW_MSG_REG3_8822C << BIT_SHIFT_FW_MSG_REG3_8822C)\n#define BIT_CLEAR_FW_MSG_REG3_8822C(x) ((x) & (~BITS_FW_MSG_REG3_8822C))\n#define BIT_GET_FW_MSG_REG3_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_FW_MSG_REG3_8822C) & BIT_MASK_FW_MSG_REG3_8822C)\n#define BIT_SET_FW_MSG_REG3_8822C(x, v)                                        \\\n\t(BIT_CLEAR_FW_MSG_REG3_8822C(x) | BIT_FW_MSG_REG3_8822C(v))\n\n/* 2 REG_FW_MSG4_8822C */\n\n#define BIT_SHIFT_FW_MSG_REG4_8822C 0\n#define BIT_MASK_FW_MSG_REG4_8822C 0xffffffffL\n#define BIT_FW_MSG_REG4_8822C(x)                                               \\\n\t(((x) & BIT_MASK_FW_MSG_REG4_8822C) << BIT_SHIFT_FW_MSG_REG4_8822C)\n#define BITS_FW_MSG_REG4_8822C                                                 \\\n\t(BIT_MASK_FW_MSG_REG4_8822C << BIT_SHIFT_FW_MSG_REG4_8822C)\n#define BIT_CLEAR_FW_MSG_REG4_8822C(x) ((x) & (~BITS_FW_MSG_REG4_8822C))\n#define BIT_GET_FW_MSG_REG4_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_FW_MSG_REG4_8822C) & BIT_MASK_FW_MSG_REG4_8822C)\n#define BIT_SET_FW_MSG_REG4_8822C(x, v)                                        \\\n\t(BIT_CLEAR_FW_MSG_REG4_8822C(x) | BIT_FW_MSG_REG4_8822C(v))\n\n/* 2 REG_DDMA_CH0SA_8822C */\n\n#define BIT_SHIFT_DDMACH0_SA_8822C 0\n#define BIT_MASK_DDMACH0_SA_8822C 0xffffffffL\n#define BIT_DDMACH0_SA_8822C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH0_SA_8822C) << BIT_SHIFT_DDMACH0_SA_8822C)\n#define BITS_DDMACH0_SA_8822C                                                  \\\n\t(BIT_MASK_DDMACH0_SA_8822C << BIT_SHIFT_DDMACH0_SA_8822C)\n#define BIT_CLEAR_DDMACH0_SA_8822C(x) ((x) & (~BITS_DDMACH0_SA_8822C))\n#define BIT_GET_DDMACH0_SA_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH0_SA_8822C) & BIT_MASK_DDMACH0_SA_8822C)\n#define BIT_SET_DDMACH0_SA_8822C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH0_SA_8822C(x) | BIT_DDMACH0_SA_8822C(v))\n\n/* 2 REG_DDMA_CH0DA_8822C */\n\n#define BIT_SHIFT_DDMACH0_DA_8822C 0\n#define BIT_MASK_DDMACH0_DA_8822C 0xffffffffL\n#define BIT_DDMACH0_DA_8822C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH0_DA_8822C) << BIT_SHIFT_DDMACH0_DA_8822C)\n#define BITS_DDMACH0_DA_8822C                                                  \\\n\t(BIT_MASK_DDMACH0_DA_8822C << BIT_SHIFT_DDMACH0_DA_8822C)\n#define BIT_CLEAR_DDMACH0_DA_8822C(x) ((x) & (~BITS_DDMACH0_DA_8822C))\n#define BIT_GET_DDMACH0_DA_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH0_DA_8822C) & BIT_MASK_DDMACH0_DA_8822C)\n#define BIT_SET_DDMACH0_DA_8822C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH0_DA_8822C(x) | BIT_DDMACH0_DA_8822C(v))\n\n/* 2 REG_DDMA_CH0CTRL_8822C */\n#define BIT_DDMACH0_OWN_8822C BIT(31)\n#define BIT_DDMACH0_IDMEM_ERR_8822C BIT(30)\n#define BIT_DDMACH0_CHKSUM_EN_8822C BIT(29)\n#define BIT_DDMACH0_DA_W_DISABLE_8822C BIT(28)\n#define BIT_DDMACH0_CHKSUM_STS_8822C BIT(27)\n#define BIT_DDMACH0_DDMA_MODE_8822C BIT(26)\n#define BIT_DDMACH0_RESET_CHKSUM_STS_8822C BIT(25)\n#define BIT_DDMACH0_CHKSUM_CONT_8822C BIT(24)\n\n#define BIT_SHIFT_DDMACH0_DLEN_8822C 0\n#define BIT_MASK_DDMACH0_DLEN_8822C 0x3ffff\n#define BIT_DDMACH0_DLEN_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH0_DLEN_8822C) << BIT_SHIFT_DDMACH0_DLEN_8822C)\n#define BITS_DDMACH0_DLEN_8822C                                                \\\n\t(BIT_MASK_DDMACH0_DLEN_8822C << BIT_SHIFT_DDMACH0_DLEN_8822C)\n#define BIT_CLEAR_DDMACH0_DLEN_8822C(x) ((x) & (~BITS_DDMACH0_DLEN_8822C))\n#define BIT_GET_DDMACH0_DLEN_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH0_DLEN_8822C) & BIT_MASK_DDMACH0_DLEN_8822C)\n#define BIT_SET_DDMACH0_DLEN_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH0_DLEN_8822C(x) | BIT_DDMACH0_DLEN_8822C(v))\n\n/* 2 REG_DDMA_CH1SA_8822C */\n\n#define BIT_SHIFT_DDMACH1_SA_8822C 0\n#define BIT_MASK_DDMACH1_SA_8822C 0xffffffffL\n#define BIT_DDMACH1_SA_8822C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH1_SA_8822C) << BIT_SHIFT_DDMACH1_SA_8822C)\n#define BITS_DDMACH1_SA_8822C                                                  \\\n\t(BIT_MASK_DDMACH1_SA_8822C << BIT_SHIFT_DDMACH1_SA_8822C)\n#define BIT_CLEAR_DDMACH1_SA_8822C(x) ((x) & (~BITS_DDMACH1_SA_8822C))\n#define BIT_GET_DDMACH1_SA_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH1_SA_8822C) & BIT_MASK_DDMACH1_SA_8822C)\n#define BIT_SET_DDMACH1_SA_8822C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH1_SA_8822C(x) | BIT_DDMACH1_SA_8822C(v))\n\n/* 2 REG_DDMA_CH1DA_8822C */\n\n#define BIT_SHIFT_DDMACH1_DA_8822C 0\n#define BIT_MASK_DDMACH1_DA_8822C 0xffffffffL\n#define BIT_DDMACH1_DA_8822C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH1_DA_8822C) << BIT_SHIFT_DDMACH1_DA_8822C)\n#define BITS_DDMACH1_DA_8822C                                                  \\\n\t(BIT_MASK_DDMACH1_DA_8822C << BIT_SHIFT_DDMACH1_DA_8822C)\n#define BIT_CLEAR_DDMACH1_DA_8822C(x) ((x) & (~BITS_DDMACH1_DA_8822C))\n#define BIT_GET_DDMACH1_DA_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH1_DA_8822C) & BIT_MASK_DDMACH1_DA_8822C)\n#define BIT_SET_DDMACH1_DA_8822C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH1_DA_8822C(x) | BIT_DDMACH1_DA_8822C(v))\n\n/* 2 REG_DDMA_CH1CTRL_8822C */\n#define BIT_DDMACH1_OWN_8822C BIT(31)\n#define BIT_DDMACH1_IDMEM_ERR_8822C BIT(30)\n#define BIT_DDMACH1_CHKSUM_EN_8822C BIT(29)\n#define BIT_DDMACH1_DA_W_DISABLE_8822C BIT(28)\n#define BIT_DDMACH1_CHKSUM_STS_8822C BIT(27)\n#define BIT_DDMACH1_DDMA_MODE_8822C BIT(26)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_DDMACH1_DLEN_8822C 0\n#define BIT_MASK_DDMACH1_DLEN_8822C 0x3ffff\n#define BIT_DDMACH1_DLEN_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH1_DLEN_8822C) << BIT_SHIFT_DDMACH1_DLEN_8822C)\n#define BITS_DDMACH1_DLEN_8822C                                                \\\n\t(BIT_MASK_DDMACH1_DLEN_8822C << BIT_SHIFT_DDMACH1_DLEN_8822C)\n#define BIT_CLEAR_DDMACH1_DLEN_8822C(x) ((x) & (~BITS_DDMACH1_DLEN_8822C))\n#define BIT_GET_DDMACH1_DLEN_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH1_DLEN_8822C) & BIT_MASK_DDMACH1_DLEN_8822C)\n#define BIT_SET_DDMACH1_DLEN_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH1_DLEN_8822C(x) | BIT_DDMACH1_DLEN_8822C(v))\n\n/* 2 REG_DDMA_CH2SA_8822C */\n\n#define BIT_SHIFT_DDMACH2_SA_8822C 0\n#define BIT_MASK_DDMACH2_SA_8822C 0xffffffffL\n#define BIT_DDMACH2_SA_8822C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH2_SA_8822C) << BIT_SHIFT_DDMACH2_SA_8822C)\n#define BITS_DDMACH2_SA_8822C                                                  \\\n\t(BIT_MASK_DDMACH2_SA_8822C << BIT_SHIFT_DDMACH2_SA_8822C)\n#define BIT_CLEAR_DDMACH2_SA_8822C(x) ((x) & (~BITS_DDMACH2_SA_8822C))\n#define BIT_GET_DDMACH2_SA_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH2_SA_8822C) & BIT_MASK_DDMACH2_SA_8822C)\n#define BIT_SET_DDMACH2_SA_8822C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH2_SA_8822C(x) | BIT_DDMACH2_SA_8822C(v))\n\n/* 2 REG_DDMA_CH2DA_8822C */\n\n#define BIT_SHIFT_DDMACH2_DA_8822C 0\n#define BIT_MASK_DDMACH2_DA_8822C 0xffffffffL\n#define BIT_DDMACH2_DA_8822C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH2_DA_8822C) << BIT_SHIFT_DDMACH2_DA_8822C)\n#define BITS_DDMACH2_DA_8822C                                                  \\\n\t(BIT_MASK_DDMACH2_DA_8822C << BIT_SHIFT_DDMACH2_DA_8822C)\n#define BIT_CLEAR_DDMACH2_DA_8822C(x) ((x) & (~BITS_DDMACH2_DA_8822C))\n#define BIT_GET_DDMACH2_DA_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH2_DA_8822C) & BIT_MASK_DDMACH2_DA_8822C)\n#define BIT_SET_DDMACH2_DA_8822C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH2_DA_8822C(x) | BIT_DDMACH2_DA_8822C(v))\n\n/* 2 REG_DDMA_CH2CTRL_8822C */\n#define BIT_DDMACH2_OWN_8822C BIT(31)\n#define BIT_DDMACH2_IDMEM_ERR_8822C BIT(30)\n#define BIT_DDMACH2_CHKSUM_EN_8822C BIT(29)\n#define BIT_DDMACH2_DA_W_DISABLE_8822C BIT(28)\n#define BIT_DDMACH2_CHKSUM_STS_8822C BIT(27)\n#define BIT_DDMACH2_DDMA_MODE_8822C BIT(26)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_DDMACH2_DLEN_8822C 0\n#define BIT_MASK_DDMACH2_DLEN_8822C 0x3ffff\n#define BIT_DDMACH2_DLEN_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH2_DLEN_8822C) << BIT_SHIFT_DDMACH2_DLEN_8822C)\n#define BITS_DDMACH2_DLEN_8822C                                                \\\n\t(BIT_MASK_DDMACH2_DLEN_8822C << BIT_SHIFT_DDMACH2_DLEN_8822C)\n#define BIT_CLEAR_DDMACH2_DLEN_8822C(x) ((x) & (~BITS_DDMACH2_DLEN_8822C))\n#define BIT_GET_DDMACH2_DLEN_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH2_DLEN_8822C) & BIT_MASK_DDMACH2_DLEN_8822C)\n#define BIT_SET_DDMACH2_DLEN_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH2_DLEN_8822C(x) | BIT_DDMACH2_DLEN_8822C(v))\n\n/* 2 REG_DDMA_CH3SA_8822C */\n\n#define BIT_SHIFT_DDMACH3_SA_8822C 0\n#define BIT_MASK_DDMACH3_SA_8822C 0xffffffffL\n#define BIT_DDMACH3_SA_8822C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH3_SA_8822C) << BIT_SHIFT_DDMACH3_SA_8822C)\n#define BITS_DDMACH3_SA_8822C                                                  \\\n\t(BIT_MASK_DDMACH3_SA_8822C << BIT_SHIFT_DDMACH3_SA_8822C)\n#define BIT_CLEAR_DDMACH3_SA_8822C(x) ((x) & (~BITS_DDMACH3_SA_8822C))\n#define BIT_GET_DDMACH3_SA_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH3_SA_8822C) & BIT_MASK_DDMACH3_SA_8822C)\n#define BIT_SET_DDMACH3_SA_8822C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH3_SA_8822C(x) | BIT_DDMACH3_SA_8822C(v))\n\n/* 2 REG_DDMA_CH3DA_8822C */\n\n#define BIT_SHIFT_DDMACH3_DA_8822C 0\n#define BIT_MASK_DDMACH3_DA_8822C 0xffffffffL\n#define BIT_DDMACH3_DA_8822C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH3_DA_8822C) << BIT_SHIFT_DDMACH3_DA_8822C)\n#define BITS_DDMACH3_DA_8822C                                                  \\\n\t(BIT_MASK_DDMACH3_DA_8822C << BIT_SHIFT_DDMACH3_DA_8822C)\n#define BIT_CLEAR_DDMACH3_DA_8822C(x) ((x) & (~BITS_DDMACH3_DA_8822C))\n#define BIT_GET_DDMACH3_DA_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH3_DA_8822C) & BIT_MASK_DDMACH3_DA_8822C)\n#define BIT_SET_DDMACH3_DA_8822C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH3_DA_8822C(x) | BIT_DDMACH3_DA_8822C(v))\n\n/* 2 REG_DDMA_CH3CTRL_8822C */\n#define BIT_DDMACH3_OWN_8822C BIT(31)\n#define BIT_DDMACH3_IDMEM_ERR_8822C BIT(30)\n#define BIT_DDMACH3_CHKSUM_EN_8822C BIT(29)\n#define BIT_DDMACH3_DA_W_DISABLE_8822C BIT(28)\n#define BIT_DDMACH3_CHKSUM_STS_8822C BIT(27)\n#define BIT_DDMACH3_DDMA_MODE_8822C BIT(26)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_DDMACH3_DLEN_8822C 0\n#define BIT_MASK_DDMACH3_DLEN_8822C 0x3ffff\n#define BIT_DDMACH3_DLEN_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH3_DLEN_8822C) << BIT_SHIFT_DDMACH3_DLEN_8822C)\n#define BITS_DDMACH3_DLEN_8822C                                                \\\n\t(BIT_MASK_DDMACH3_DLEN_8822C << BIT_SHIFT_DDMACH3_DLEN_8822C)\n#define BIT_CLEAR_DDMACH3_DLEN_8822C(x) ((x) & (~BITS_DDMACH3_DLEN_8822C))\n#define BIT_GET_DDMACH3_DLEN_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH3_DLEN_8822C) & BIT_MASK_DDMACH3_DLEN_8822C)\n#define BIT_SET_DDMACH3_DLEN_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH3_DLEN_8822C(x) | BIT_DDMACH3_DLEN_8822C(v))\n\n/* 2 REG_DDMA_CH4SA_8822C */\n\n#define BIT_SHIFT_DDMACH4_SA_8822C 0\n#define BIT_MASK_DDMACH4_SA_8822C 0xffffffffL\n#define BIT_DDMACH4_SA_8822C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH4_SA_8822C) << BIT_SHIFT_DDMACH4_SA_8822C)\n#define BITS_DDMACH4_SA_8822C                                                  \\\n\t(BIT_MASK_DDMACH4_SA_8822C << BIT_SHIFT_DDMACH4_SA_8822C)\n#define BIT_CLEAR_DDMACH4_SA_8822C(x) ((x) & (~BITS_DDMACH4_SA_8822C))\n#define BIT_GET_DDMACH4_SA_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH4_SA_8822C) & BIT_MASK_DDMACH4_SA_8822C)\n#define BIT_SET_DDMACH4_SA_8822C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH4_SA_8822C(x) | BIT_DDMACH4_SA_8822C(v))\n\n/* 2 REG_DDMA_CH4DA_8822C */\n\n#define BIT_SHIFT_DDMACH4_DA_8822C 0\n#define BIT_MASK_DDMACH4_DA_8822C 0xffffffffL\n#define BIT_DDMACH4_DA_8822C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH4_DA_8822C) << BIT_SHIFT_DDMACH4_DA_8822C)\n#define BITS_DDMACH4_DA_8822C                                                  \\\n\t(BIT_MASK_DDMACH4_DA_8822C << BIT_SHIFT_DDMACH4_DA_8822C)\n#define BIT_CLEAR_DDMACH4_DA_8822C(x) ((x) & (~BITS_DDMACH4_DA_8822C))\n#define BIT_GET_DDMACH4_DA_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH4_DA_8822C) & BIT_MASK_DDMACH4_DA_8822C)\n#define BIT_SET_DDMACH4_DA_8822C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH4_DA_8822C(x) | BIT_DDMACH4_DA_8822C(v))\n\n/* 2 REG_DDMA_CH4CTRL_8822C */\n#define BIT_DDMACH4_OWN_8822C BIT(31)\n#define BIT_DDMACH4_IDMEM_ERR_8822C BIT(30)\n#define BIT_DDMACH4_CHKSUM_EN_8822C BIT(29)\n#define BIT_DDMACH4_DA_W_DISABLE_8822C BIT(28)\n#define BIT_DDMACH4_CHKSUM_STS_8822C BIT(27)\n#define BIT_DDMACH4_DDMA_MODE_8822C BIT(26)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_DDMACH4_DLEN_8822C 0\n#define BIT_MASK_DDMACH4_DLEN_8822C 0x3ffff\n#define BIT_DDMACH4_DLEN_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH4_DLEN_8822C) << BIT_SHIFT_DDMACH4_DLEN_8822C)\n#define BITS_DDMACH4_DLEN_8822C                                                \\\n\t(BIT_MASK_DDMACH4_DLEN_8822C << BIT_SHIFT_DDMACH4_DLEN_8822C)\n#define BIT_CLEAR_DDMACH4_DLEN_8822C(x) ((x) & (~BITS_DDMACH4_DLEN_8822C))\n#define BIT_GET_DDMACH4_DLEN_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH4_DLEN_8822C) & BIT_MASK_DDMACH4_DLEN_8822C)\n#define BIT_SET_DDMACH4_DLEN_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH4_DLEN_8822C(x) | BIT_DDMACH4_DLEN_8822C(v))\n\n/* 2 REG_DDMA_CH5SA_8822C */\n\n#define BIT_SHIFT_DDMACH5_SA_8822C 0\n#define BIT_MASK_DDMACH5_SA_8822C 0xffffffffL\n#define BIT_DDMACH5_SA_8822C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH5_SA_8822C) << BIT_SHIFT_DDMACH5_SA_8822C)\n#define BITS_DDMACH5_SA_8822C                                                  \\\n\t(BIT_MASK_DDMACH5_SA_8822C << BIT_SHIFT_DDMACH5_SA_8822C)\n#define BIT_CLEAR_DDMACH5_SA_8822C(x) ((x) & (~BITS_DDMACH5_SA_8822C))\n#define BIT_GET_DDMACH5_SA_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH5_SA_8822C) & BIT_MASK_DDMACH5_SA_8822C)\n#define BIT_SET_DDMACH5_SA_8822C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH5_SA_8822C(x) | BIT_DDMACH5_SA_8822C(v))\n\n/* 2 REG_DDMA_CH5DA_8822C */\n\n#define BIT_SHIFT_DDMACH5_DA_8822C 0\n#define BIT_MASK_DDMACH5_DA_8822C 0xffffffffL\n#define BIT_DDMACH5_DA_8822C(x)                                                \\\n\t(((x) & BIT_MASK_DDMACH5_DA_8822C) << BIT_SHIFT_DDMACH5_DA_8822C)\n#define BITS_DDMACH5_DA_8822C                                                  \\\n\t(BIT_MASK_DDMACH5_DA_8822C << BIT_SHIFT_DDMACH5_DA_8822C)\n#define BIT_CLEAR_DDMACH5_DA_8822C(x) ((x) & (~BITS_DDMACH5_DA_8822C))\n#define BIT_GET_DDMACH5_DA_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DDMACH5_DA_8822C) & BIT_MASK_DDMACH5_DA_8822C)\n#define BIT_SET_DDMACH5_DA_8822C(x, v)                                         \\\n\t(BIT_CLEAR_DDMACH5_DA_8822C(x) | BIT_DDMACH5_DA_8822C(v))\n\n/* 2 REG_DDMA_CH5CTRL_8822C */\n#define BIT_DDMACH5_OWN_8822C BIT(31)\n#define BIT_DDMACH5_IDMEM_ERR_8822C BIT(30)\n#define BIT_DDMACH5_CHKSUM_EN_8822C BIT(29)\n#define BIT_DDMACH5_DA_W_DISABLE_8822C BIT(28)\n#define BIT_DDMACH5_CHKSUM_STS_8822C BIT(27)\n#define BIT_DDMACH5_DDMA_MODE_8822C BIT(26)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_DDMACH5_DLEN_8822C 0\n#define BIT_MASK_DDMACH5_DLEN_8822C 0x3ffff\n#define BIT_DDMACH5_DLEN_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DDMACH5_DLEN_8822C) << BIT_SHIFT_DDMACH5_DLEN_8822C)\n#define BITS_DDMACH5_DLEN_8822C                                                \\\n\t(BIT_MASK_DDMACH5_DLEN_8822C << BIT_SHIFT_DDMACH5_DLEN_8822C)\n#define BIT_CLEAR_DDMACH5_DLEN_8822C(x) ((x) & (~BITS_DDMACH5_DLEN_8822C))\n#define BIT_GET_DDMACH5_DLEN_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DDMACH5_DLEN_8822C) & BIT_MASK_DDMACH5_DLEN_8822C)\n#define BIT_SET_DDMACH5_DLEN_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DDMACH5_DLEN_8822C(x) | BIT_DDMACH5_DLEN_8822C(v))\n\n/* 2 REG_DDMA_INT_MSK_8822C */\n#define BIT_DDMACH5_MSK_8822C BIT(5)\n#define BIT_DDMACH4_MSK_8822C BIT(4)\n#define BIT_DDMACH3_MSK_8822C BIT(3)\n#define BIT_DDMACH2_MSK_8822C BIT(2)\n#define BIT_DDMACH1_MSK_8822C BIT(1)\n#define BIT_DDMACH0_MSK_8822C BIT(0)\n\n/* 2 REG_DDMA_CHSTATUS_8822C */\n#define BIT_DDMACH5_BUSY_8822C BIT(5)\n#define BIT_DDMACH4_BUSY_8822C BIT(4)\n#define BIT_DDMACH3_BUSY_8822C BIT(3)\n#define BIT_DDMACH2_BUSY_8822C BIT(2)\n#define BIT_DDMACH1_BUSY_8822C BIT(1)\n#define BIT_DDMACH0_BUSY_8822C BIT(0)\n\n/* 2 REG_DDMA_CHKSUM_8822C */\n\n#define BIT_SHIFT_IDDMA0_CHKSUM_8822C 0\n#define BIT_MASK_IDDMA0_CHKSUM_8822C 0xffff\n#define BIT_IDDMA0_CHKSUM_8822C(x)                                             \\\n\t(((x) & BIT_MASK_IDDMA0_CHKSUM_8822C) << BIT_SHIFT_IDDMA0_CHKSUM_8822C)\n#define BITS_IDDMA0_CHKSUM_8822C                                               \\\n\t(BIT_MASK_IDDMA0_CHKSUM_8822C << BIT_SHIFT_IDDMA0_CHKSUM_8822C)\n#define BIT_CLEAR_IDDMA0_CHKSUM_8822C(x) ((x) & (~BITS_IDDMA0_CHKSUM_8822C))\n#define BIT_GET_IDDMA0_CHKSUM_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8822C) & BIT_MASK_IDDMA0_CHKSUM_8822C)\n#define BIT_SET_IDDMA0_CHKSUM_8822C(x, v)                                      \\\n\t(BIT_CLEAR_IDDMA0_CHKSUM_8822C(x) | BIT_IDDMA0_CHKSUM_8822C(v))\n\n/* 2 REG_DDMA_MONITOR_8822C */\n#define BIT_IDDMA0_PERMU_UNDERFLOW_8822C BIT(14)\n#define BIT_IDDMA0_FIFO_UNDERFLOW_8822C BIT(13)\n#define BIT_IDDMA0_FIFO_OVERFLOW_8822C BIT(12)\n#define BIT_CH5_ERR_8822C BIT(5)\n#define BIT_CH4_ERR_8822C BIT(4)\n#define BIT_CH3_ERR_8822C BIT(3)\n#define BIT_CH2_ERR_8822C BIT(2)\n#define BIT_CH1_ERR_8822C BIT(1)\n#define BIT_CH0_ERR_8822C BIT(0)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_PCIE_CTRL_8822C */\n#define BIT_PCIEIO_PERSTB_SEL_8822C BIT(31)\n\n#define BIT_SHIFT_PCIE_MAX_RXDMA_8822C 28\n#define BIT_MASK_PCIE_MAX_RXDMA_8822C 0x7\n#define BIT_PCIE_MAX_RXDMA_8822C(x)                                            \\\n\t(((x) & BIT_MASK_PCIE_MAX_RXDMA_8822C)                                 \\\n\t << BIT_SHIFT_PCIE_MAX_RXDMA_8822C)\n#define BITS_PCIE_MAX_RXDMA_8822C                                              \\\n\t(BIT_MASK_PCIE_MAX_RXDMA_8822C << BIT_SHIFT_PCIE_MAX_RXDMA_8822C)\n#define BIT_CLEAR_PCIE_MAX_RXDMA_8822C(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8822C))\n#define BIT_GET_PCIE_MAX_RXDMA_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8822C) &                             \\\n\t BIT_MASK_PCIE_MAX_RXDMA_8822C)\n#define BIT_SET_PCIE_MAX_RXDMA_8822C(x, v)                                     \\\n\t(BIT_CLEAR_PCIE_MAX_RXDMA_8822C(x) | BIT_PCIE_MAX_RXDMA_8822C(v))\n\n#define BIT_SHIFT_PCIE_MAX_TXDMA_8822C 24\n#define BIT_MASK_PCIE_MAX_TXDMA_8822C 0x7\n#define BIT_PCIE_MAX_TXDMA_8822C(x)                                            \\\n\t(((x) & BIT_MASK_PCIE_MAX_TXDMA_8822C)                                 \\\n\t << BIT_SHIFT_PCIE_MAX_TXDMA_8822C)\n#define BITS_PCIE_MAX_TXDMA_8822C                                              \\\n\t(BIT_MASK_PCIE_MAX_TXDMA_8822C << BIT_SHIFT_PCIE_MAX_TXDMA_8822C)\n#define BIT_CLEAR_PCIE_MAX_TXDMA_8822C(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8822C))\n#define BIT_GET_PCIE_MAX_TXDMA_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8822C) &                             \\\n\t BIT_MASK_PCIE_MAX_TXDMA_8822C)\n#define BIT_SET_PCIE_MAX_TXDMA_8822C(x, v)                                     \\\n\t(BIT_CLEAR_PCIE_MAX_TXDMA_8822C(x) | BIT_PCIE_MAX_TXDMA_8822C(v))\n\n#define BIT_EN_CPL_TIMEOUT_PS_8822C BIT(22)\n#define BIT_REG_TXDMA_FAIL_PS_8822C BIT(21)\n#define BIT_PCIE_RST_TRXDMA_INTF_8822C BIT(20)\n#define BIT_EN_HWENTR_L1_8822C BIT(19)\n#define BIT_EN_ADV_CLKGATE_8822C BIT(18)\n#define BIT_PCIE_EN_SWENT_L23_8822C BIT(17)\n#define BIT_PCIE_EN_HWEXT_L1_8822C BIT(16)\n#define BIT_RX_CLOSE_EN_8822C BIT(15)\n#define BIT_STOP_BCNQ_8822C BIT(14)\n#define BIT_STOP_MGQ_8822C BIT(13)\n#define BIT_STOP_VOQ_8822C BIT(12)\n#define BIT_STOP_VIQ_8822C BIT(11)\n#define BIT_STOP_BEQ_8822C BIT(10)\n#define BIT_STOP_BKQ_8822C BIT(9)\n#define BIT_STOP_RXQ_8822C BIT(8)\n#define BIT_STOP_HI7Q_8822C BIT(7)\n#define BIT_STOP_HI6Q_8822C BIT(6)\n#define BIT_STOP_HI5Q_8822C BIT(5)\n#define BIT_STOP_HI4Q_8822C BIT(4)\n#define BIT_STOP_HI3Q_8822C BIT(3)\n#define BIT_STOP_HI2Q_8822C BIT(2)\n#define BIT_STOP_HI1Q_8822C BIT(1)\n#define BIT_STOP_HI0Q_8822C BIT(0)\n\n/* 2 REG_INT_MIG_8822C */\n\n#define BIT_SHIFT_TRXCOUNTER_MATCH_8822C 24\n#define BIT_MASK_TRXCOUNTER_MATCH_8822C 0xff\n#define BIT_TRXCOUNTER_MATCH_8822C(x)                                          \\\n\t(((x) & BIT_MASK_TRXCOUNTER_MATCH_8822C)                               \\\n\t << BIT_SHIFT_TRXCOUNTER_MATCH_8822C)\n#define BITS_TRXCOUNTER_MATCH_8822C                                            \\\n\t(BIT_MASK_TRXCOUNTER_MATCH_8822C << BIT_SHIFT_TRXCOUNTER_MATCH_8822C)\n#define BIT_CLEAR_TRXCOUNTER_MATCH_8822C(x)                                    \\\n\t((x) & (~BITS_TRXCOUNTER_MATCH_8822C))\n#define BIT_GET_TRXCOUNTER_MATCH_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_TRXCOUNTER_MATCH_8822C) &                           \\\n\t BIT_MASK_TRXCOUNTER_MATCH_8822C)\n#define BIT_SET_TRXCOUNTER_MATCH_8822C(x, v)                                   \\\n\t(BIT_CLEAR_TRXCOUNTER_MATCH_8822C(x) | BIT_TRXCOUNTER_MATCH_8822C(v))\n\n#define BIT_SHIFT_TRXTIMER_MATCH_8822C 16\n#define BIT_MASK_TRXTIMER_MATCH_8822C 0xff\n#define BIT_TRXTIMER_MATCH_8822C(x)                                            \\\n\t(((x) & BIT_MASK_TRXTIMER_MATCH_8822C)                                 \\\n\t << BIT_SHIFT_TRXTIMER_MATCH_8822C)\n#define BITS_TRXTIMER_MATCH_8822C                                              \\\n\t(BIT_MASK_TRXTIMER_MATCH_8822C << BIT_SHIFT_TRXTIMER_MATCH_8822C)\n#define BIT_CLEAR_TRXTIMER_MATCH_8822C(x) ((x) & (~BITS_TRXTIMER_MATCH_8822C))\n#define BIT_GET_TRXTIMER_MATCH_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TRXTIMER_MATCH_8822C) &                             \\\n\t BIT_MASK_TRXTIMER_MATCH_8822C)\n#define BIT_SET_TRXTIMER_MATCH_8822C(x, v)                                     \\\n\t(BIT_CLEAR_TRXTIMER_MATCH_8822C(x) | BIT_TRXTIMER_MATCH_8822C(v))\n\n#define BIT_SHIFT_TRXTIMER_UNIT_8822C 0\n#define BIT_MASK_TRXTIMER_UNIT_8822C 0x3\n#define BIT_TRXTIMER_UNIT_8822C(x)                                             \\\n\t(((x) & BIT_MASK_TRXTIMER_UNIT_8822C) << BIT_SHIFT_TRXTIMER_UNIT_8822C)\n#define BITS_TRXTIMER_UNIT_8822C                                               \\\n\t(BIT_MASK_TRXTIMER_UNIT_8822C << BIT_SHIFT_TRXTIMER_UNIT_8822C)\n#define BIT_CLEAR_TRXTIMER_UNIT_8822C(x) ((x) & (~BITS_TRXTIMER_UNIT_8822C))\n#define BIT_GET_TRXTIMER_UNIT_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TRXTIMER_UNIT_8822C) & BIT_MASK_TRXTIMER_UNIT_8822C)\n#define BIT_SET_TRXTIMER_UNIT_8822C(x, v)                                      \\\n\t(BIT_CLEAR_TRXTIMER_UNIT_8822C(x) | BIT_TRXTIMER_UNIT_8822C(v))\n\n/* 2 REG_BCNQ_TXBD_DESA_8822C */\n\n#define BIT_SHIFT_BCNQ_TXBD_DESA_8822C 0\n#define BIT_MASK_BCNQ_TXBD_DESA_8822C 0xffffffffffffffffL\n#define BIT_BCNQ_TXBD_DESA_8822C(x)                                            \\\n\t(((x) & BIT_MASK_BCNQ_TXBD_DESA_8822C)                                 \\\n\t << BIT_SHIFT_BCNQ_TXBD_DESA_8822C)\n#define BITS_BCNQ_TXBD_DESA_8822C                                              \\\n\t(BIT_MASK_BCNQ_TXBD_DESA_8822C << BIT_SHIFT_BCNQ_TXBD_DESA_8822C)\n#define BIT_CLEAR_BCNQ_TXBD_DESA_8822C(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8822C))\n#define BIT_GET_BCNQ_TXBD_DESA_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8822C) &                             \\\n\t BIT_MASK_BCNQ_TXBD_DESA_8822C)\n#define BIT_SET_BCNQ_TXBD_DESA_8822C(x, v)                                     \\\n\t(BIT_CLEAR_BCNQ_TXBD_DESA_8822C(x) | BIT_BCNQ_TXBD_DESA_8822C(v))\n\n/* 2 REG_MGQ_TXBD_DESA_8822C */\n\n#define BIT_SHIFT_MGQ_TXBD_DESA_8822C 0\n#define BIT_MASK_MGQ_TXBD_DESA_8822C 0xffffffffffffffffL\n#define BIT_MGQ_TXBD_DESA_8822C(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_TXBD_DESA_8822C) << BIT_SHIFT_MGQ_TXBD_DESA_8822C)\n#define BITS_MGQ_TXBD_DESA_8822C                                               \\\n\t(BIT_MASK_MGQ_TXBD_DESA_8822C << BIT_SHIFT_MGQ_TXBD_DESA_8822C)\n#define BIT_CLEAR_MGQ_TXBD_DESA_8822C(x) ((x) & (~BITS_MGQ_TXBD_DESA_8822C))\n#define BIT_GET_MGQ_TXBD_DESA_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8822C) & BIT_MASK_MGQ_TXBD_DESA_8822C)\n#define BIT_SET_MGQ_TXBD_DESA_8822C(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_TXBD_DESA_8822C(x) | BIT_MGQ_TXBD_DESA_8822C(v))\n\n/* 2 REG_VOQ_TXBD_DESA_8822C */\n\n#define BIT_SHIFT_VOQ_TXBD_DESA_8822C 0\n#define BIT_MASK_VOQ_TXBD_DESA_8822C 0xffffffffffffffffL\n#define BIT_VOQ_TXBD_DESA_8822C(x)                                             \\\n\t(((x) & BIT_MASK_VOQ_TXBD_DESA_8822C) << BIT_SHIFT_VOQ_TXBD_DESA_8822C)\n#define BITS_VOQ_TXBD_DESA_8822C                                               \\\n\t(BIT_MASK_VOQ_TXBD_DESA_8822C << BIT_SHIFT_VOQ_TXBD_DESA_8822C)\n#define BIT_CLEAR_VOQ_TXBD_DESA_8822C(x) ((x) & (~BITS_VOQ_TXBD_DESA_8822C))\n#define BIT_GET_VOQ_TXBD_DESA_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8822C) & BIT_MASK_VOQ_TXBD_DESA_8822C)\n#define BIT_SET_VOQ_TXBD_DESA_8822C(x, v)                                      \\\n\t(BIT_CLEAR_VOQ_TXBD_DESA_8822C(x) | BIT_VOQ_TXBD_DESA_8822C(v))\n\n/* 2 REG_VIQ_TXBD_DESA_8822C */\n\n#define BIT_SHIFT_VIQ_TXBD_DESA_8822C 0\n#define BIT_MASK_VIQ_TXBD_DESA_8822C 0xffffffffffffffffL\n#define BIT_VIQ_TXBD_DESA_8822C(x)                                             \\\n\t(((x) & BIT_MASK_VIQ_TXBD_DESA_8822C) << BIT_SHIFT_VIQ_TXBD_DESA_8822C)\n#define BITS_VIQ_TXBD_DESA_8822C                                               \\\n\t(BIT_MASK_VIQ_TXBD_DESA_8822C << BIT_SHIFT_VIQ_TXBD_DESA_8822C)\n#define BIT_CLEAR_VIQ_TXBD_DESA_8822C(x) ((x) & (~BITS_VIQ_TXBD_DESA_8822C))\n#define BIT_GET_VIQ_TXBD_DESA_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8822C) & BIT_MASK_VIQ_TXBD_DESA_8822C)\n#define BIT_SET_VIQ_TXBD_DESA_8822C(x, v)                                      \\\n\t(BIT_CLEAR_VIQ_TXBD_DESA_8822C(x) | BIT_VIQ_TXBD_DESA_8822C(v))\n\n/* 2 REG_BEQ_TXBD_DESA_8822C */\n\n#define BIT_SHIFT_BEQ_TXBD_DESA_8822C 0\n#define BIT_MASK_BEQ_TXBD_DESA_8822C 0xffffffffffffffffL\n#define BIT_BEQ_TXBD_DESA_8822C(x)                                             \\\n\t(((x) & BIT_MASK_BEQ_TXBD_DESA_8822C) << BIT_SHIFT_BEQ_TXBD_DESA_8822C)\n#define BITS_BEQ_TXBD_DESA_8822C                                               \\\n\t(BIT_MASK_BEQ_TXBD_DESA_8822C << BIT_SHIFT_BEQ_TXBD_DESA_8822C)\n#define BIT_CLEAR_BEQ_TXBD_DESA_8822C(x) ((x) & (~BITS_BEQ_TXBD_DESA_8822C))\n#define BIT_GET_BEQ_TXBD_DESA_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8822C) & BIT_MASK_BEQ_TXBD_DESA_8822C)\n#define BIT_SET_BEQ_TXBD_DESA_8822C(x, v)                                      \\\n\t(BIT_CLEAR_BEQ_TXBD_DESA_8822C(x) | BIT_BEQ_TXBD_DESA_8822C(v))\n\n/* 2 REG_BKQ_TXBD_DESA_8822C */\n\n#define BIT_SHIFT_BKQ_TXBD_DESA_8822C 0\n#define BIT_MASK_BKQ_TXBD_DESA_8822C 0xffffffffffffffffL\n#define BIT_BKQ_TXBD_DESA_8822C(x)                                             \\\n\t(((x) & BIT_MASK_BKQ_TXBD_DESA_8822C) << BIT_SHIFT_BKQ_TXBD_DESA_8822C)\n#define BITS_BKQ_TXBD_DESA_8822C                                               \\\n\t(BIT_MASK_BKQ_TXBD_DESA_8822C << BIT_SHIFT_BKQ_TXBD_DESA_8822C)\n#define BIT_CLEAR_BKQ_TXBD_DESA_8822C(x) ((x) & (~BITS_BKQ_TXBD_DESA_8822C))\n#define BIT_GET_BKQ_TXBD_DESA_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8822C) & BIT_MASK_BKQ_TXBD_DESA_8822C)\n#define BIT_SET_BKQ_TXBD_DESA_8822C(x, v)                                      \\\n\t(BIT_CLEAR_BKQ_TXBD_DESA_8822C(x) | BIT_BKQ_TXBD_DESA_8822C(v))\n\n/* 2 REG_RXQ_RXBD_DESA_8822C */\n\n#define BIT_SHIFT_RXQ_RXBD_DESA_8822C 0\n#define BIT_MASK_RXQ_RXBD_DESA_8822C 0xffffffffffffffffL\n#define BIT_RXQ_RXBD_DESA_8822C(x)                                             \\\n\t(((x) & BIT_MASK_RXQ_RXBD_DESA_8822C) << BIT_SHIFT_RXQ_RXBD_DESA_8822C)\n#define BITS_RXQ_RXBD_DESA_8822C                                               \\\n\t(BIT_MASK_RXQ_RXBD_DESA_8822C << BIT_SHIFT_RXQ_RXBD_DESA_8822C)\n#define BIT_CLEAR_RXQ_RXBD_DESA_8822C(x) ((x) & (~BITS_RXQ_RXBD_DESA_8822C))\n#define BIT_GET_RXQ_RXBD_DESA_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8822C) & BIT_MASK_RXQ_RXBD_DESA_8822C)\n#define BIT_SET_RXQ_RXBD_DESA_8822C(x, v)                                      \\\n\t(BIT_CLEAR_RXQ_RXBD_DESA_8822C(x) | BIT_RXQ_RXBD_DESA_8822C(v))\n\n/* 2 REG_HI0Q_TXBD_DESA_8822C */\n\n#define BIT_SHIFT_HI0Q_TXBD_DESA_8822C 0\n#define BIT_MASK_HI0Q_TXBD_DESA_8822C 0xffffffffffffffffL\n#define BIT_HI0Q_TXBD_DESA_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HI0Q_TXBD_DESA_8822C)                                 \\\n\t << BIT_SHIFT_HI0Q_TXBD_DESA_8822C)\n#define BITS_HI0Q_TXBD_DESA_8822C                                              \\\n\t(BIT_MASK_HI0Q_TXBD_DESA_8822C << BIT_SHIFT_HI0Q_TXBD_DESA_8822C)\n#define BIT_CLEAR_HI0Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8822C))\n#define BIT_GET_HI0Q_TXBD_DESA_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8822C) &                             \\\n\t BIT_MASK_HI0Q_TXBD_DESA_8822C)\n#define BIT_SET_HI0Q_TXBD_DESA_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HI0Q_TXBD_DESA_8822C(x) | BIT_HI0Q_TXBD_DESA_8822C(v))\n\n/* 2 REG_HI1Q_TXBD_DESA_8822C */\n\n#define BIT_SHIFT_HI1Q_TXBD_DESA_8822C 0\n#define BIT_MASK_HI1Q_TXBD_DESA_8822C 0xffffffffffffffffL\n#define BIT_HI1Q_TXBD_DESA_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HI1Q_TXBD_DESA_8822C)                                 \\\n\t << BIT_SHIFT_HI1Q_TXBD_DESA_8822C)\n#define BITS_HI1Q_TXBD_DESA_8822C                                              \\\n\t(BIT_MASK_HI1Q_TXBD_DESA_8822C << BIT_SHIFT_HI1Q_TXBD_DESA_8822C)\n#define BIT_CLEAR_HI1Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8822C))\n#define BIT_GET_HI1Q_TXBD_DESA_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8822C) &                             \\\n\t BIT_MASK_HI1Q_TXBD_DESA_8822C)\n#define BIT_SET_HI1Q_TXBD_DESA_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HI1Q_TXBD_DESA_8822C(x) | BIT_HI1Q_TXBD_DESA_8822C(v))\n\n/* 2 REG_HI2Q_TXBD_DESA_8822C */\n\n#define BIT_SHIFT_HI2Q_TXBD_DESA_8822C 0\n#define BIT_MASK_HI2Q_TXBD_DESA_8822C 0xffffffffffffffffL\n#define BIT_HI2Q_TXBD_DESA_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HI2Q_TXBD_DESA_8822C)                                 \\\n\t << BIT_SHIFT_HI2Q_TXBD_DESA_8822C)\n#define BITS_HI2Q_TXBD_DESA_8822C                                              \\\n\t(BIT_MASK_HI2Q_TXBD_DESA_8822C << BIT_SHIFT_HI2Q_TXBD_DESA_8822C)\n#define BIT_CLEAR_HI2Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8822C))\n#define BIT_GET_HI2Q_TXBD_DESA_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8822C) &                             \\\n\t BIT_MASK_HI2Q_TXBD_DESA_8822C)\n#define BIT_SET_HI2Q_TXBD_DESA_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HI2Q_TXBD_DESA_8822C(x) | BIT_HI2Q_TXBD_DESA_8822C(v))\n\n/* 2 REG_HI3Q_TXBD_DESA_8822C */\n\n#define BIT_SHIFT_HI3Q_TXBD_DESA_8822C 0\n#define BIT_MASK_HI3Q_TXBD_DESA_8822C 0xffffffffffffffffL\n#define BIT_HI3Q_TXBD_DESA_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HI3Q_TXBD_DESA_8822C)                                 \\\n\t << BIT_SHIFT_HI3Q_TXBD_DESA_8822C)\n#define BITS_HI3Q_TXBD_DESA_8822C                                              \\\n\t(BIT_MASK_HI3Q_TXBD_DESA_8822C << BIT_SHIFT_HI3Q_TXBD_DESA_8822C)\n#define BIT_CLEAR_HI3Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8822C))\n#define BIT_GET_HI3Q_TXBD_DESA_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8822C) &                             \\\n\t BIT_MASK_HI3Q_TXBD_DESA_8822C)\n#define BIT_SET_HI3Q_TXBD_DESA_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HI3Q_TXBD_DESA_8822C(x) | BIT_HI3Q_TXBD_DESA_8822C(v))\n\n/* 2 REG_HI4Q_TXBD_DESA_8822C */\n\n#define BIT_SHIFT_HI4Q_TXBD_DESA_8822C 0\n#define BIT_MASK_HI4Q_TXBD_DESA_8822C 0xffffffffffffffffL\n#define BIT_HI4Q_TXBD_DESA_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HI4Q_TXBD_DESA_8822C)                                 \\\n\t << BIT_SHIFT_HI4Q_TXBD_DESA_8822C)\n#define BITS_HI4Q_TXBD_DESA_8822C                                              \\\n\t(BIT_MASK_HI4Q_TXBD_DESA_8822C << BIT_SHIFT_HI4Q_TXBD_DESA_8822C)\n#define BIT_CLEAR_HI4Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8822C))\n#define BIT_GET_HI4Q_TXBD_DESA_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8822C) &                             \\\n\t BIT_MASK_HI4Q_TXBD_DESA_8822C)\n#define BIT_SET_HI4Q_TXBD_DESA_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HI4Q_TXBD_DESA_8822C(x) | BIT_HI4Q_TXBD_DESA_8822C(v))\n\n/* 2 REG_HI5Q_TXBD_DESA_8822C */\n\n#define BIT_SHIFT_HI5Q_TXBD_DESA_8822C 0\n#define BIT_MASK_HI5Q_TXBD_DESA_8822C 0xffffffffffffffffL\n#define BIT_HI5Q_TXBD_DESA_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HI5Q_TXBD_DESA_8822C)                                 \\\n\t << BIT_SHIFT_HI5Q_TXBD_DESA_8822C)\n#define BITS_HI5Q_TXBD_DESA_8822C                                              \\\n\t(BIT_MASK_HI5Q_TXBD_DESA_8822C << BIT_SHIFT_HI5Q_TXBD_DESA_8822C)\n#define BIT_CLEAR_HI5Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8822C))\n#define BIT_GET_HI5Q_TXBD_DESA_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8822C) &                             \\\n\t BIT_MASK_HI5Q_TXBD_DESA_8822C)\n#define BIT_SET_HI5Q_TXBD_DESA_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HI5Q_TXBD_DESA_8822C(x) | BIT_HI5Q_TXBD_DESA_8822C(v))\n\n/* 2 REG_HI6Q_TXBD_DESA_8822C */\n\n#define BIT_SHIFT_HI6Q_TXBD_DESA_8822C 0\n#define BIT_MASK_HI6Q_TXBD_DESA_8822C 0xffffffffffffffffL\n#define BIT_HI6Q_TXBD_DESA_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HI6Q_TXBD_DESA_8822C)                                 \\\n\t << BIT_SHIFT_HI6Q_TXBD_DESA_8822C)\n#define BITS_HI6Q_TXBD_DESA_8822C                                              \\\n\t(BIT_MASK_HI6Q_TXBD_DESA_8822C << BIT_SHIFT_HI6Q_TXBD_DESA_8822C)\n#define BIT_CLEAR_HI6Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8822C))\n#define BIT_GET_HI6Q_TXBD_DESA_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8822C) &                             \\\n\t BIT_MASK_HI6Q_TXBD_DESA_8822C)\n#define BIT_SET_HI6Q_TXBD_DESA_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HI6Q_TXBD_DESA_8822C(x) | BIT_HI6Q_TXBD_DESA_8822C(v))\n\n/* 2 REG_HI7Q_TXBD_DESA_8822C */\n\n#define BIT_SHIFT_HI7Q_TXBD_DESA_8822C 0\n#define BIT_MASK_HI7Q_TXBD_DESA_8822C 0xffffffffffffffffL\n#define BIT_HI7Q_TXBD_DESA_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HI7Q_TXBD_DESA_8822C)                                 \\\n\t << BIT_SHIFT_HI7Q_TXBD_DESA_8822C)\n#define BITS_HI7Q_TXBD_DESA_8822C                                              \\\n\t(BIT_MASK_HI7Q_TXBD_DESA_8822C << BIT_SHIFT_HI7Q_TXBD_DESA_8822C)\n#define BIT_CLEAR_HI7Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8822C))\n#define BIT_GET_HI7Q_TXBD_DESA_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8822C) &                             \\\n\t BIT_MASK_HI7Q_TXBD_DESA_8822C)\n#define BIT_SET_HI7Q_TXBD_DESA_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HI7Q_TXBD_DESA_8822C(x) | BIT_HI7Q_TXBD_DESA_8822C(v))\n\n/* 2 REG_MGQ_TXBD_NUM_8822C */\n#define BIT_PCIE_MGQ_FLAG_8822C BIT(14)\n\n#define BIT_SHIFT_MGQ_DESC_MODE_8822C 12\n#define BIT_MASK_MGQ_DESC_MODE_8822C 0x3\n#define BIT_MGQ_DESC_MODE_8822C(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_DESC_MODE_8822C) << BIT_SHIFT_MGQ_DESC_MODE_8822C)\n#define BITS_MGQ_DESC_MODE_8822C                                               \\\n\t(BIT_MASK_MGQ_DESC_MODE_8822C << BIT_SHIFT_MGQ_DESC_MODE_8822C)\n#define BIT_CLEAR_MGQ_DESC_MODE_8822C(x) ((x) & (~BITS_MGQ_DESC_MODE_8822C))\n#define BIT_GET_MGQ_DESC_MODE_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_DESC_MODE_8822C) & BIT_MASK_MGQ_DESC_MODE_8822C)\n#define BIT_SET_MGQ_DESC_MODE_8822C(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_DESC_MODE_8822C(x) | BIT_MGQ_DESC_MODE_8822C(v))\n\n#define BIT_SHIFT_MGQ_DESC_NUM_8822C 0\n#define BIT_MASK_MGQ_DESC_NUM_8822C 0xfff\n#define BIT_MGQ_DESC_NUM_8822C(x)                                              \\\n\t(((x) & BIT_MASK_MGQ_DESC_NUM_8822C) << BIT_SHIFT_MGQ_DESC_NUM_8822C)\n#define BITS_MGQ_DESC_NUM_8822C                                                \\\n\t(BIT_MASK_MGQ_DESC_NUM_8822C << BIT_SHIFT_MGQ_DESC_NUM_8822C)\n#define BIT_CLEAR_MGQ_DESC_NUM_8822C(x) ((x) & (~BITS_MGQ_DESC_NUM_8822C))\n#define BIT_GET_MGQ_DESC_NUM_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_MGQ_DESC_NUM_8822C) & BIT_MASK_MGQ_DESC_NUM_8822C)\n#define BIT_SET_MGQ_DESC_NUM_8822C(x, v)                                       \\\n\t(BIT_CLEAR_MGQ_DESC_NUM_8822C(x) | BIT_MGQ_DESC_NUM_8822C(v))\n\n/* 2 REG_RX_RXBD_NUM_8822C */\n#define BIT_SYS_32_64_8822C BIT(15)\n\n#define BIT_SHIFT_BCNQ_DESC_MODE_8822C 13\n#define BIT_MASK_BCNQ_DESC_MODE_8822C 0x3\n#define BIT_BCNQ_DESC_MODE_8822C(x)                                            \\\n\t(((x) & BIT_MASK_BCNQ_DESC_MODE_8822C)                                 \\\n\t << BIT_SHIFT_BCNQ_DESC_MODE_8822C)\n#define BITS_BCNQ_DESC_MODE_8822C                                              \\\n\t(BIT_MASK_BCNQ_DESC_MODE_8822C << BIT_SHIFT_BCNQ_DESC_MODE_8822C)\n#define BIT_CLEAR_BCNQ_DESC_MODE_8822C(x) ((x) & (~BITS_BCNQ_DESC_MODE_8822C))\n#define BIT_GET_BCNQ_DESC_MODE_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8822C) &                             \\\n\t BIT_MASK_BCNQ_DESC_MODE_8822C)\n#define BIT_SET_BCNQ_DESC_MODE_8822C(x, v)                                     \\\n\t(BIT_CLEAR_BCNQ_DESC_MODE_8822C(x) | BIT_BCNQ_DESC_MODE_8822C(v))\n\n#define BIT_PCIE_BCNQ_FLAG_8822C BIT(12)\n\n#define BIT_SHIFT_RXQ_DESC_NUM_8822C 0\n#define BIT_MASK_RXQ_DESC_NUM_8822C 0xfff\n#define BIT_RXQ_DESC_NUM_8822C(x)                                              \\\n\t(((x) & BIT_MASK_RXQ_DESC_NUM_8822C) << BIT_SHIFT_RXQ_DESC_NUM_8822C)\n#define BITS_RXQ_DESC_NUM_8822C                                                \\\n\t(BIT_MASK_RXQ_DESC_NUM_8822C << BIT_SHIFT_RXQ_DESC_NUM_8822C)\n#define BIT_CLEAR_RXQ_DESC_NUM_8822C(x) ((x) & (~BITS_RXQ_DESC_NUM_8822C))\n#define BIT_GET_RXQ_DESC_NUM_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXQ_DESC_NUM_8822C) & BIT_MASK_RXQ_DESC_NUM_8822C)\n#define BIT_SET_RXQ_DESC_NUM_8822C(x, v)                                       \\\n\t(BIT_CLEAR_RXQ_DESC_NUM_8822C(x) | BIT_RXQ_DESC_NUM_8822C(v))\n\n/* 2 REG_VOQ_TXBD_NUM_8822C */\n#define BIT_PCIE_VOQ_FLAG_8822C BIT(14)\n\n#define BIT_SHIFT_VOQ_DESC_MODE_8822C 12\n#define BIT_MASK_VOQ_DESC_MODE_8822C 0x3\n#define BIT_VOQ_DESC_MODE_8822C(x)                                             \\\n\t(((x) & BIT_MASK_VOQ_DESC_MODE_8822C) << BIT_SHIFT_VOQ_DESC_MODE_8822C)\n#define BITS_VOQ_DESC_MODE_8822C                                               \\\n\t(BIT_MASK_VOQ_DESC_MODE_8822C << BIT_SHIFT_VOQ_DESC_MODE_8822C)\n#define BIT_CLEAR_VOQ_DESC_MODE_8822C(x) ((x) & (~BITS_VOQ_DESC_MODE_8822C))\n#define BIT_GET_VOQ_DESC_MODE_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_VOQ_DESC_MODE_8822C) & BIT_MASK_VOQ_DESC_MODE_8822C)\n#define BIT_SET_VOQ_DESC_MODE_8822C(x, v)                                      \\\n\t(BIT_CLEAR_VOQ_DESC_MODE_8822C(x) | BIT_VOQ_DESC_MODE_8822C(v))\n\n#define BIT_SHIFT_VOQ_DESC_NUM_8822C 0\n#define BIT_MASK_VOQ_DESC_NUM_8822C 0xfff\n#define BIT_VOQ_DESC_NUM_8822C(x)                                              \\\n\t(((x) & BIT_MASK_VOQ_DESC_NUM_8822C) << BIT_SHIFT_VOQ_DESC_NUM_8822C)\n#define BITS_VOQ_DESC_NUM_8822C                                                \\\n\t(BIT_MASK_VOQ_DESC_NUM_8822C << BIT_SHIFT_VOQ_DESC_NUM_8822C)\n#define BIT_CLEAR_VOQ_DESC_NUM_8822C(x) ((x) & (~BITS_VOQ_DESC_NUM_8822C))\n#define BIT_GET_VOQ_DESC_NUM_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_VOQ_DESC_NUM_8822C) & BIT_MASK_VOQ_DESC_NUM_8822C)\n#define BIT_SET_VOQ_DESC_NUM_8822C(x, v)                                       \\\n\t(BIT_CLEAR_VOQ_DESC_NUM_8822C(x) | BIT_VOQ_DESC_NUM_8822C(v))\n\n/* 2 REG_VIQ_TXBD_NUM_8822C */\n#define BIT_PCIE_VIQ_FLAG_8822C BIT(14)\n\n#define BIT_SHIFT_VIQ_DESC_MODE_8822C 12\n#define BIT_MASK_VIQ_DESC_MODE_8822C 0x3\n#define BIT_VIQ_DESC_MODE_8822C(x)                                             \\\n\t(((x) & BIT_MASK_VIQ_DESC_MODE_8822C) << BIT_SHIFT_VIQ_DESC_MODE_8822C)\n#define BITS_VIQ_DESC_MODE_8822C                                               \\\n\t(BIT_MASK_VIQ_DESC_MODE_8822C << BIT_SHIFT_VIQ_DESC_MODE_8822C)\n#define BIT_CLEAR_VIQ_DESC_MODE_8822C(x) ((x) & (~BITS_VIQ_DESC_MODE_8822C))\n#define BIT_GET_VIQ_DESC_MODE_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_VIQ_DESC_MODE_8822C) & BIT_MASK_VIQ_DESC_MODE_8822C)\n#define BIT_SET_VIQ_DESC_MODE_8822C(x, v)                                      \\\n\t(BIT_CLEAR_VIQ_DESC_MODE_8822C(x) | BIT_VIQ_DESC_MODE_8822C(v))\n\n#define BIT_SHIFT_VIQ_DESC_NUM_8822C 0\n#define BIT_MASK_VIQ_DESC_NUM_8822C 0xfff\n#define BIT_VIQ_DESC_NUM_8822C(x)                                              \\\n\t(((x) & BIT_MASK_VIQ_DESC_NUM_8822C) << BIT_SHIFT_VIQ_DESC_NUM_8822C)\n#define BITS_VIQ_DESC_NUM_8822C                                                \\\n\t(BIT_MASK_VIQ_DESC_NUM_8822C << BIT_SHIFT_VIQ_DESC_NUM_8822C)\n#define BIT_CLEAR_VIQ_DESC_NUM_8822C(x) ((x) & (~BITS_VIQ_DESC_NUM_8822C))\n#define BIT_GET_VIQ_DESC_NUM_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_VIQ_DESC_NUM_8822C) & BIT_MASK_VIQ_DESC_NUM_8822C)\n#define BIT_SET_VIQ_DESC_NUM_8822C(x, v)                                       \\\n\t(BIT_CLEAR_VIQ_DESC_NUM_8822C(x) | BIT_VIQ_DESC_NUM_8822C(v))\n\n/* 2 REG_BEQ_TXBD_NUM_8822C */\n#define BIT_PCIE_BEQ_FLAG_8822C BIT(14)\n\n#define BIT_SHIFT_BEQ_DESC_MODE_8822C 12\n#define BIT_MASK_BEQ_DESC_MODE_8822C 0x3\n#define BIT_BEQ_DESC_MODE_8822C(x)                                             \\\n\t(((x) & BIT_MASK_BEQ_DESC_MODE_8822C) << BIT_SHIFT_BEQ_DESC_MODE_8822C)\n#define BITS_BEQ_DESC_MODE_8822C                                               \\\n\t(BIT_MASK_BEQ_DESC_MODE_8822C << BIT_SHIFT_BEQ_DESC_MODE_8822C)\n#define BIT_CLEAR_BEQ_DESC_MODE_8822C(x) ((x) & (~BITS_BEQ_DESC_MODE_8822C))\n#define BIT_GET_BEQ_DESC_MODE_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BEQ_DESC_MODE_8822C) & BIT_MASK_BEQ_DESC_MODE_8822C)\n#define BIT_SET_BEQ_DESC_MODE_8822C(x, v)                                      \\\n\t(BIT_CLEAR_BEQ_DESC_MODE_8822C(x) | BIT_BEQ_DESC_MODE_8822C(v))\n\n#define BIT_SHIFT_BEQ_DESC_NUM_8822C 0\n#define BIT_MASK_BEQ_DESC_NUM_8822C 0xfff\n#define BIT_BEQ_DESC_NUM_8822C(x)                                              \\\n\t(((x) & BIT_MASK_BEQ_DESC_NUM_8822C) << BIT_SHIFT_BEQ_DESC_NUM_8822C)\n#define BITS_BEQ_DESC_NUM_8822C                                                \\\n\t(BIT_MASK_BEQ_DESC_NUM_8822C << BIT_SHIFT_BEQ_DESC_NUM_8822C)\n#define BIT_CLEAR_BEQ_DESC_NUM_8822C(x) ((x) & (~BITS_BEQ_DESC_NUM_8822C))\n#define BIT_GET_BEQ_DESC_NUM_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BEQ_DESC_NUM_8822C) & BIT_MASK_BEQ_DESC_NUM_8822C)\n#define BIT_SET_BEQ_DESC_NUM_8822C(x, v)                                       \\\n\t(BIT_CLEAR_BEQ_DESC_NUM_8822C(x) | BIT_BEQ_DESC_NUM_8822C(v))\n\n/* 2 REG_BKQ_TXBD_NUM_8822C */\n#define BIT_PCIE_BKQ_FLAG_8822C BIT(14)\n\n#define BIT_SHIFT_BKQ_DESC_MODE_8822C 12\n#define BIT_MASK_BKQ_DESC_MODE_8822C 0x3\n#define BIT_BKQ_DESC_MODE_8822C(x)                                             \\\n\t(((x) & BIT_MASK_BKQ_DESC_MODE_8822C) << BIT_SHIFT_BKQ_DESC_MODE_8822C)\n#define BITS_BKQ_DESC_MODE_8822C                                               \\\n\t(BIT_MASK_BKQ_DESC_MODE_8822C << BIT_SHIFT_BKQ_DESC_MODE_8822C)\n#define BIT_CLEAR_BKQ_DESC_MODE_8822C(x) ((x) & (~BITS_BKQ_DESC_MODE_8822C))\n#define BIT_GET_BKQ_DESC_MODE_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BKQ_DESC_MODE_8822C) & BIT_MASK_BKQ_DESC_MODE_8822C)\n#define BIT_SET_BKQ_DESC_MODE_8822C(x, v)                                      \\\n\t(BIT_CLEAR_BKQ_DESC_MODE_8822C(x) | BIT_BKQ_DESC_MODE_8822C(v))\n\n#define BIT_SHIFT_BKQ_DESC_NUM_8822C 0\n#define BIT_MASK_BKQ_DESC_NUM_8822C 0xfff\n#define BIT_BKQ_DESC_NUM_8822C(x)                                              \\\n\t(((x) & BIT_MASK_BKQ_DESC_NUM_8822C) << BIT_SHIFT_BKQ_DESC_NUM_8822C)\n#define BITS_BKQ_DESC_NUM_8822C                                                \\\n\t(BIT_MASK_BKQ_DESC_NUM_8822C << BIT_SHIFT_BKQ_DESC_NUM_8822C)\n#define BIT_CLEAR_BKQ_DESC_NUM_8822C(x) ((x) & (~BITS_BKQ_DESC_NUM_8822C))\n#define BIT_GET_BKQ_DESC_NUM_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BKQ_DESC_NUM_8822C) & BIT_MASK_BKQ_DESC_NUM_8822C)\n#define BIT_SET_BKQ_DESC_NUM_8822C(x, v)                                       \\\n\t(BIT_CLEAR_BKQ_DESC_NUM_8822C(x) | BIT_BKQ_DESC_NUM_8822C(v))\n\n/* 2 REG_HI0Q_TXBD_NUM_8822C */\n#define BIT_HI0Q_FLAG_8822C BIT(14)\n\n#define BIT_SHIFT_HI0Q_DESC_MODE_8822C 12\n#define BIT_MASK_HI0Q_DESC_MODE_8822C 0x3\n#define BIT_HI0Q_DESC_MODE_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HI0Q_DESC_MODE_8822C)                                 \\\n\t << BIT_SHIFT_HI0Q_DESC_MODE_8822C)\n#define BITS_HI0Q_DESC_MODE_8822C                                              \\\n\t(BIT_MASK_HI0Q_DESC_MODE_8822C << BIT_SHIFT_HI0Q_DESC_MODE_8822C)\n#define BIT_CLEAR_HI0Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI0Q_DESC_MODE_8822C))\n#define BIT_GET_HI0Q_DESC_MODE_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8822C) &                             \\\n\t BIT_MASK_HI0Q_DESC_MODE_8822C)\n#define BIT_SET_HI0Q_DESC_MODE_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HI0Q_DESC_MODE_8822C(x) | BIT_HI0Q_DESC_MODE_8822C(v))\n\n#define BIT_SHIFT_HI0Q_DESC_NUM_8822C 0\n#define BIT_MASK_HI0Q_DESC_NUM_8822C 0xfff\n#define BIT_HI0Q_DESC_NUM_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HI0Q_DESC_NUM_8822C) << BIT_SHIFT_HI0Q_DESC_NUM_8822C)\n#define BITS_HI0Q_DESC_NUM_8822C                                               \\\n\t(BIT_MASK_HI0Q_DESC_NUM_8822C << BIT_SHIFT_HI0Q_DESC_NUM_8822C)\n#define BIT_CLEAR_HI0Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI0Q_DESC_NUM_8822C))\n#define BIT_GET_HI0Q_DESC_NUM_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8822C) & BIT_MASK_HI0Q_DESC_NUM_8822C)\n#define BIT_SET_HI0Q_DESC_NUM_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HI0Q_DESC_NUM_8822C(x) | BIT_HI0Q_DESC_NUM_8822C(v))\n\n/* 2 REG_HI1Q_TXBD_NUM_8822C */\n#define BIT_HI1Q_FLAG_8822C BIT(14)\n\n#define BIT_SHIFT_HI1Q_DESC_MODE_8822C 12\n#define BIT_MASK_HI1Q_DESC_MODE_8822C 0x3\n#define BIT_HI1Q_DESC_MODE_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HI1Q_DESC_MODE_8822C)                                 \\\n\t << BIT_SHIFT_HI1Q_DESC_MODE_8822C)\n#define BITS_HI1Q_DESC_MODE_8822C                                              \\\n\t(BIT_MASK_HI1Q_DESC_MODE_8822C << BIT_SHIFT_HI1Q_DESC_MODE_8822C)\n#define BIT_CLEAR_HI1Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI1Q_DESC_MODE_8822C))\n#define BIT_GET_HI1Q_DESC_MODE_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8822C) &                             \\\n\t BIT_MASK_HI1Q_DESC_MODE_8822C)\n#define BIT_SET_HI1Q_DESC_MODE_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HI1Q_DESC_MODE_8822C(x) | BIT_HI1Q_DESC_MODE_8822C(v))\n\n#define BIT_SHIFT_HI1Q_DESC_NUM_8822C 0\n#define BIT_MASK_HI1Q_DESC_NUM_8822C 0xfff\n#define BIT_HI1Q_DESC_NUM_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HI1Q_DESC_NUM_8822C) << BIT_SHIFT_HI1Q_DESC_NUM_8822C)\n#define BITS_HI1Q_DESC_NUM_8822C                                               \\\n\t(BIT_MASK_HI1Q_DESC_NUM_8822C << BIT_SHIFT_HI1Q_DESC_NUM_8822C)\n#define BIT_CLEAR_HI1Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI1Q_DESC_NUM_8822C))\n#define BIT_GET_HI1Q_DESC_NUM_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8822C) & BIT_MASK_HI1Q_DESC_NUM_8822C)\n#define BIT_SET_HI1Q_DESC_NUM_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HI1Q_DESC_NUM_8822C(x) | BIT_HI1Q_DESC_NUM_8822C(v))\n\n/* 2 REG_HI2Q_TXBD_NUM_8822C */\n#define BIT_HI2Q_FLAG_8822C BIT(14)\n\n#define BIT_SHIFT_HI2Q_DESC_MODE_8822C 12\n#define BIT_MASK_HI2Q_DESC_MODE_8822C 0x3\n#define BIT_HI2Q_DESC_MODE_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HI2Q_DESC_MODE_8822C)                                 \\\n\t << BIT_SHIFT_HI2Q_DESC_MODE_8822C)\n#define BITS_HI2Q_DESC_MODE_8822C                                              \\\n\t(BIT_MASK_HI2Q_DESC_MODE_8822C << BIT_SHIFT_HI2Q_DESC_MODE_8822C)\n#define BIT_CLEAR_HI2Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI2Q_DESC_MODE_8822C))\n#define BIT_GET_HI2Q_DESC_MODE_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8822C) &                             \\\n\t BIT_MASK_HI2Q_DESC_MODE_8822C)\n#define BIT_SET_HI2Q_DESC_MODE_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HI2Q_DESC_MODE_8822C(x) | BIT_HI2Q_DESC_MODE_8822C(v))\n\n#define BIT_SHIFT_HI2Q_DESC_NUM_8822C 0\n#define BIT_MASK_HI2Q_DESC_NUM_8822C 0xfff\n#define BIT_HI2Q_DESC_NUM_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HI2Q_DESC_NUM_8822C) << BIT_SHIFT_HI2Q_DESC_NUM_8822C)\n#define BITS_HI2Q_DESC_NUM_8822C                                               \\\n\t(BIT_MASK_HI2Q_DESC_NUM_8822C << BIT_SHIFT_HI2Q_DESC_NUM_8822C)\n#define BIT_CLEAR_HI2Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI2Q_DESC_NUM_8822C))\n#define BIT_GET_HI2Q_DESC_NUM_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8822C) & BIT_MASK_HI2Q_DESC_NUM_8822C)\n#define BIT_SET_HI2Q_DESC_NUM_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HI2Q_DESC_NUM_8822C(x) | BIT_HI2Q_DESC_NUM_8822C(v))\n\n/* 2 REG_HI3Q_TXBD_NUM_8822C */\n#define BIT_HI3Q_FLAG_8822C BIT(14)\n\n#define BIT_SHIFT_HI3Q_DESC_MODE_8822C 12\n#define BIT_MASK_HI3Q_DESC_MODE_8822C 0x3\n#define BIT_HI3Q_DESC_MODE_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HI3Q_DESC_MODE_8822C)                                 \\\n\t << BIT_SHIFT_HI3Q_DESC_MODE_8822C)\n#define BITS_HI3Q_DESC_MODE_8822C                                              \\\n\t(BIT_MASK_HI3Q_DESC_MODE_8822C << BIT_SHIFT_HI3Q_DESC_MODE_8822C)\n#define BIT_CLEAR_HI3Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI3Q_DESC_MODE_8822C))\n#define BIT_GET_HI3Q_DESC_MODE_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8822C) &                             \\\n\t BIT_MASK_HI3Q_DESC_MODE_8822C)\n#define BIT_SET_HI3Q_DESC_MODE_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HI3Q_DESC_MODE_8822C(x) | BIT_HI3Q_DESC_MODE_8822C(v))\n\n#define BIT_SHIFT_HI3Q_DESC_NUM_8822C 0\n#define BIT_MASK_HI3Q_DESC_NUM_8822C 0xfff\n#define BIT_HI3Q_DESC_NUM_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HI3Q_DESC_NUM_8822C) << BIT_SHIFT_HI3Q_DESC_NUM_8822C)\n#define BITS_HI3Q_DESC_NUM_8822C                                               \\\n\t(BIT_MASK_HI3Q_DESC_NUM_8822C << BIT_SHIFT_HI3Q_DESC_NUM_8822C)\n#define BIT_CLEAR_HI3Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI3Q_DESC_NUM_8822C))\n#define BIT_GET_HI3Q_DESC_NUM_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8822C) & BIT_MASK_HI3Q_DESC_NUM_8822C)\n#define BIT_SET_HI3Q_DESC_NUM_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HI3Q_DESC_NUM_8822C(x) | BIT_HI3Q_DESC_NUM_8822C(v))\n\n/* 2 REG_HI4Q_TXBD_NUM_8822C */\n#define BIT_HI4Q_FLAG_8822C BIT(14)\n\n#define BIT_SHIFT_HI4Q_DESC_MODE_8822C 12\n#define BIT_MASK_HI4Q_DESC_MODE_8822C 0x3\n#define BIT_HI4Q_DESC_MODE_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HI4Q_DESC_MODE_8822C)                                 \\\n\t << BIT_SHIFT_HI4Q_DESC_MODE_8822C)\n#define BITS_HI4Q_DESC_MODE_8822C                                              \\\n\t(BIT_MASK_HI4Q_DESC_MODE_8822C << BIT_SHIFT_HI4Q_DESC_MODE_8822C)\n#define BIT_CLEAR_HI4Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI4Q_DESC_MODE_8822C))\n#define BIT_GET_HI4Q_DESC_MODE_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8822C) &                             \\\n\t BIT_MASK_HI4Q_DESC_MODE_8822C)\n#define BIT_SET_HI4Q_DESC_MODE_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HI4Q_DESC_MODE_8822C(x) | BIT_HI4Q_DESC_MODE_8822C(v))\n\n#define BIT_SHIFT_HI4Q_DESC_NUM_8822C 0\n#define BIT_MASK_HI4Q_DESC_NUM_8822C 0xfff\n#define BIT_HI4Q_DESC_NUM_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HI4Q_DESC_NUM_8822C) << BIT_SHIFT_HI4Q_DESC_NUM_8822C)\n#define BITS_HI4Q_DESC_NUM_8822C                                               \\\n\t(BIT_MASK_HI4Q_DESC_NUM_8822C << BIT_SHIFT_HI4Q_DESC_NUM_8822C)\n#define BIT_CLEAR_HI4Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI4Q_DESC_NUM_8822C))\n#define BIT_GET_HI4Q_DESC_NUM_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8822C) & BIT_MASK_HI4Q_DESC_NUM_8822C)\n#define BIT_SET_HI4Q_DESC_NUM_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HI4Q_DESC_NUM_8822C(x) | BIT_HI4Q_DESC_NUM_8822C(v))\n\n/* 2 REG_HI5Q_TXBD_NUM_8822C */\n#define BIT_HI5Q_FLAG_8822C BIT(14)\n\n#define BIT_SHIFT_HI5Q_DESC_MODE_8822C 12\n#define BIT_MASK_HI5Q_DESC_MODE_8822C 0x3\n#define BIT_HI5Q_DESC_MODE_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HI5Q_DESC_MODE_8822C)                                 \\\n\t << BIT_SHIFT_HI5Q_DESC_MODE_8822C)\n#define BITS_HI5Q_DESC_MODE_8822C                                              \\\n\t(BIT_MASK_HI5Q_DESC_MODE_8822C << BIT_SHIFT_HI5Q_DESC_MODE_8822C)\n#define BIT_CLEAR_HI5Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI5Q_DESC_MODE_8822C))\n#define BIT_GET_HI5Q_DESC_MODE_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8822C) &                             \\\n\t BIT_MASK_HI5Q_DESC_MODE_8822C)\n#define BIT_SET_HI5Q_DESC_MODE_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HI5Q_DESC_MODE_8822C(x) | BIT_HI5Q_DESC_MODE_8822C(v))\n\n#define BIT_SHIFT_HI5Q_DESC_NUM_8822C 0\n#define BIT_MASK_HI5Q_DESC_NUM_8822C 0xfff\n#define BIT_HI5Q_DESC_NUM_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HI5Q_DESC_NUM_8822C) << BIT_SHIFT_HI5Q_DESC_NUM_8822C)\n#define BITS_HI5Q_DESC_NUM_8822C                                               \\\n\t(BIT_MASK_HI5Q_DESC_NUM_8822C << BIT_SHIFT_HI5Q_DESC_NUM_8822C)\n#define BIT_CLEAR_HI5Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI5Q_DESC_NUM_8822C))\n#define BIT_GET_HI5Q_DESC_NUM_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8822C) & BIT_MASK_HI5Q_DESC_NUM_8822C)\n#define BIT_SET_HI5Q_DESC_NUM_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HI5Q_DESC_NUM_8822C(x) | BIT_HI5Q_DESC_NUM_8822C(v))\n\n/* 2 REG_HI6Q_TXBD_NUM_8822C */\n#define BIT_HI6Q_FLAG_8822C BIT(14)\n\n#define BIT_SHIFT_HI6Q_DESC_MODE_8822C 12\n#define BIT_MASK_HI6Q_DESC_MODE_8822C 0x3\n#define BIT_HI6Q_DESC_MODE_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HI6Q_DESC_MODE_8822C)                                 \\\n\t << BIT_SHIFT_HI6Q_DESC_MODE_8822C)\n#define BITS_HI6Q_DESC_MODE_8822C                                              \\\n\t(BIT_MASK_HI6Q_DESC_MODE_8822C << BIT_SHIFT_HI6Q_DESC_MODE_8822C)\n#define BIT_CLEAR_HI6Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI6Q_DESC_MODE_8822C))\n#define BIT_GET_HI6Q_DESC_MODE_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8822C) &                             \\\n\t BIT_MASK_HI6Q_DESC_MODE_8822C)\n#define BIT_SET_HI6Q_DESC_MODE_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HI6Q_DESC_MODE_8822C(x) | BIT_HI6Q_DESC_MODE_8822C(v))\n\n#define BIT_SHIFT_HI6Q_DESC_NUM_8822C 0\n#define BIT_MASK_HI6Q_DESC_NUM_8822C 0xfff\n#define BIT_HI6Q_DESC_NUM_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HI6Q_DESC_NUM_8822C) << BIT_SHIFT_HI6Q_DESC_NUM_8822C)\n#define BITS_HI6Q_DESC_NUM_8822C                                               \\\n\t(BIT_MASK_HI6Q_DESC_NUM_8822C << BIT_SHIFT_HI6Q_DESC_NUM_8822C)\n#define BIT_CLEAR_HI6Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI6Q_DESC_NUM_8822C))\n#define BIT_GET_HI6Q_DESC_NUM_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8822C) & BIT_MASK_HI6Q_DESC_NUM_8822C)\n#define BIT_SET_HI6Q_DESC_NUM_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HI6Q_DESC_NUM_8822C(x) | BIT_HI6Q_DESC_NUM_8822C(v))\n\n/* 2 REG_HI7Q_TXBD_NUM_8822C */\n#define BIT_HI7Q_FLAG_8822C BIT(14)\n\n#define BIT_SHIFT_HI7Q_DESC_MODE_8822C 12\n#define BIT_MASK_HI7Q_DESC_MODE_8822C 0x3\n#define BIT_HI7Q_DESC_MODE_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HI7Q_DESC_MODE_8822C)                                 \\\n\t << BIT_SHIFT_HI7Q_DESC_MODE_8822C)\n#define BITS_HI7Q_DESC_MODE_8822C                                              \\\n\t(BIT_MASK_HI7Q_DESC_MODE_8822C << BIT_SHIFT_HI7Q_DESC_MODE_8822C)\n#define BIT_CLEAR_HI7Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI7Q_DESC_MODE_8822C))\n#define BIT_GET_HI7Q_DESC_MODE_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8822C) &                             \\\n\t BIT_MASK_HI7Q_DESC_MODE_8822C)\n#define BIT_SET_HI7Q_DESC_MODE_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HI7Q_DESC_MODE_8822C(x) | BIT_HI7Q_DESC_MODE_8822C(v))\n\n#define BIT_SHIFT_HI7Q_DESC_NUM_8822C 0\n#define BIT_MASK_HI7Q_DESC_NUM_8822C 0xfff\n#define BIT_HI7Q_DESC_NUM_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HI7Q_DESC_NUM_8822C) << BIT_SHIFT_HI7Q_DESC_NUM_8822C)\n#define BITS_HI7Q_DESC_NUM_8822C                                               \\\n\t(BIT_MASK_HI7Q_DESC_NUM_8822C << BIT_SHIFT_HI7Q_DESC_NUM_8822C)\n#define BIT_CLEAR_HI7Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI7Q_DESC_NUM_8822C))\n#define BIT_GET_HI7Q_DESC_NUM_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8822C) & BIT_MASK_HI7Q_DESC_NUM_8822C)\n#define BIT_SET_HI7Q_DESC_NUM_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HI7Q_DESC_NUM_8822C(x) | BIT_HI7Q_DESC_NUM_8822C(v))\n\n/* 2 REG_TSFTIMER_HCI_8822C */\n\n#define BIT_SHIFT_TSFT2_HCI_8822C 16\n#define BIT_MASK_TSFT2_HCI_8822C 0xffff\n#define BIT_TSFT2_HCI_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_TSFT2_HCI_8822C) << BIT_SHIFT_TSFT2_HCI_8822C)\n#define BITS_TSFT2_HCI_8822C                                                   \\\n\t(BIT_MASK_TSFT2_HCI_8822C << BIT_SHIFT_TSFT2_HCI_8822C)\n#define BIT_CLEAR_TSFT2_HCI_8822C(x) ((x) & (~BITS_TSFT2_HCI_8822C))\n#define BIT_GET_TSFT2_HCI_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_TSFT2_HCI_8822C) & BIT_MASK_TSFT2_HCI_8822C)\n#define BIT_SET_TSFT2_HCI_8822C(x, v)                                          \\\n\t(BIT_CLEAR_TSFT2_HCI_8822C(x) | BIT_TSFT2_HCI_8822C(v))\n\n#define BIT_SHIFT_TSFT1_HCI_8822C 0\n#define BIT_MASK_TSFT1_HCI_8822C 0xffff\n#define BIT_TSFT1_HCI_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_TSFT1_HCI_8822C) << BIT_SHIFT_TSFT1_HCI_8822C)\n#define BITS_TSFT1_HCI_8822C                                                   \\\n\t(BIT_MASK_TSFT1_HCI_8822C << BIT_SHIFT_TSFT1_HCI_8822C)\n#define BIT_CLEAR_TSFT1_HCI_8822C(x) ((x) & (~BITS_TSFT1_HCI_8822C))\n#define BIT_GET_TSFT1_HCI_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_TSFT1_HCI_8822C) & BIT_MASK_TSFT1_HCI_8822C)\n#define BIT_SET_TSFT1_HCI_8822C(x, v)                                          \\\n\t(BIT_CLEAR_TSFT1_HCI_8822C(x) | BIT_TSFT1_HCI_8822C(v))\n\n/* 2 REG_BD_RWPTR_CLR_8822C */\n#define BIT_CLR_HI7Q_HW_IDX_8822C BIT(29)\n#define BIT_CLR_HI6Q_HW_IDX_8822C BIT(28)\n#define BIT_CLR_HI5Q_HW_IDX_8822C BIT(27)\n#define BIT_CLR_HI4Q_HW_IDX_8822C BIT(26)\n#define BIT_CLR_HI3Q_HW_IDX_8822C BIT(25)\n#define BIT_CLR_HI2Q_HW_IDX_8822C BIT(24)\n#define BIT_CLR_HI1Q_HW_IDX_8822C BIT(23)\n#define BIT_CLR_HI0Q_HW_IDX_8822C BIT(22)\n#define BIT_CLR_BKQ_HW_IDX_8822C BIT(21)\n#define BIT_CLR_BEQ_HW_IDX_8822C BIT(20)\n#define BIT_CLR_VIQ_HW_IDX_8822C BIT(19)\n#define BIT_CLR_VOQ_HW_IDX_8822C BIT(18)\n#define BIT_CLR_MGQ_HW_IDX_8822C BIT(17)\n#define BIT_CLR_RXQ_HW_IDX_8822C BIT(16)\n#define BIT_CLR_HI7Q_HOST_IDX_8822C BIT(13)\n#define BIT_CLR_HI6Q_HOST_IDX_8822C BIT(12)\n#define BIT_CLR_HI5Q_HOST_IDX_8822C BIT(11)\n#define BIT_CLR_HI4Q_HOST_IDX_8822C BIT(10)\n#define BIT_CLR_HI3Q_HOST_IDX_8822C BIT(9)\n#define BIT_CLR_HI2Q_HOST_IDX_8822C BIT(8)\n#define BIT_CLR_HI1Q_HOST_IDX_8822C BIT(7)\n#define BIT_CLR_HI0Q_HOST_IDX_8822C BIT(6)\n#define BIT_CLR_BKQ_HOST_IDX_8822C BIT(5)\n#define BIT_CLR_BEQ_HOST_IDX_8822C BIT(4)\n#define BIT_CLR_VIQ_HOST_IDX_8822C BIT(3)\n#define BIT_CLR_VOQ_HOST_IDX_8822C BIT(2)\n#define BIT_CLR_MGQ_HOST_IDX_8822C BIT(1)\n#define BIT_CLR_RXQ_HOST_IDX_8822C BIT(0)\n\n/* 2 REG_VOQ_TXBD_IDX_8822C */\n\n#define BIT_SHIFT_VOQ_HW_IDX_8822C 16\n#define BIT_MASK_VOQ_HW_IDX_8822C 0xfff\n#define BIT_VOQ_HW_IDX_8822C(x)                                                \\\n\t(((x) & BIT_MASK_VOQ_HW_IDX_8822C) << BIT_SHIFT_VOQ_HW_IDX_8822C)\n#define BITS_VOQ_HW_IDX_8822C                                                  \\\n\t(BIT_MASK_VOQ_HW_IDX_8822C << BIT_SHIFT_VOQ_HW_IDX_8822C)\n#define BIT_CLEAR_VOQ_HW_IDX_8822C(x) ((x) & (~BITS_VOQ_HW_IDX_8822C))\n#define BIT_GET_VOQ_HW_IDX_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_VOQ_HW_IDX_8822C) & BIT_MASK_VOQ_HW_IDX_8822C)\n#define BIT_SET_VOQ_HW_IDX_8822C(x, v)                                         \\\n\t(BIT_CLEAR_VOQ_HW_IDX_8822C(x) | BIT_VOQ_HW_IDX_8822C(v))\n\n#define BIT_SHIFT_VOQ_HOST_IDX_8822C 0\n#define BIT_MASK_VOQ_HOST_IDX_8822C 0xfff\n#define BIT_VOQ_HOST_IDX_8822C(x)                                              \\\n\t(((x) & BIT_MASK_VOQ_HOST_IDX_8822C) << BIT_SHIFT_VOQ_HOST_IDX_8822C)\n#define BITS_VOQ_HOST_IDX_8822C                                                \\\n\t(BIT_MASK_VOQ_HOST_IDX_8822C << BIT_SHIFT_VOQ_HOST_IDX_8822C)\n#define BIT_CLEAR_VOQ_HOST_IDX_8822C(x) ((x) & (~BITS_VOQ_HOST_IDX_8822C))\n#define BIT_GET_VOQ_HOST_IDX_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_VOQ_HOST_IDX_8822C) & BIT_MASK_VOQ_HOST_IDX_8822C)\n#define BIT_SET_VOQ_HOST_IDX_8822C(x, v)                                       \\\n\t(BIT_CLEAR_VOQ_HOST_IDX_8822C(x) | BIT_VOQ_HOST_IDX_8822C(v))\n\n/* 2 REG_VIQ_TXBD_IDX_8822C */\n\n#define BIT_SHIFT_VIQ_HW_IDX_8822C 16\n#define BIT_MASK_VIQ_HW_IDX_8822C 0xfff\n#define BIT_VIQ_HW_IDX_8822C(x)                                                \\\n\t(((x) & BIT_MASK_VIQ_HW_IDX_8822C) << BIT_SHIFT_VIQ_HW_IDX_8822C)\n#define BITS_VIQ_HW_IDX_8822C                                                  \\\n\t(BIT_MASK_VIQ_HW_IDX_8822C << BIT_SHIFT_VIQ_HW_IDX_8822C)\n#define BIT_CLEAR_VIQ_HW_IDX_8822C(x) ((x) & (~BITS_VIQ_HW_IDX_8822C))\n#define BIT_GET_VIQ_HW_IDX_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_VIQ_HW_IDX_8822C) & BIT_MASK_VIQ_HW_IDX_8822C)\n#define BIT_SET_VIQ_HW_IDX_8822C(x, v)                                         \\\n\t(BIT_CLEAR_VIQ_HW_IDX_8822C(x) | BIT_VIQ_HW_IDX_8822C(v))\n\n#define BIT_SHIFT_VIQ_HOST_IDX_8822C 0\n#define BIT_MASK_VIQ_HOST_IDX_8822C 0xfff\n#define BIT_VIQ_HOST_IDX_8822C(x)                                              \\\n\t(((x) & BIT_MASK_VIQ_HOST_IDX_8822C) << BIT_SHIFT_VIQ_HOST_IDX_8822C)\n#define BITS_VIQ_HOST_IDX_8822C                                                \\\n\t(BIT_MASK_VIQ_HOST_IDX_8822C << BIT_SHIFT_VIQ_HOST_IDX_8822C)\n#define BIT_CLEAR_VIQ_HOST_IDX_8822C(x) ((x) & (~BITS_VIQ_HOST_IDX_8822C))\n#define BIT_GET_VIQ_HOST_IDX_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_VIQ_HOST_IDX_8822C) & BIT_MASK_VIQ_HOST_IDX_8822C)\n#define BIT_SET_VIQ_HOST_IDX_8822C(x, v)                                       \\\n\t(BIT_CLEAR_VIQ_HOST_IDX_8822C(x) | BIT_VIQ_HOST_IDX_8822C(v))\n\n/* 2 REG_BEQ_TXBD_IDX_8822C */\n\n#define BIT_SHIFT_BEQ_HW_IDX_8822C 16\n#define BIT_MASK_BEQ_HW_IDX_8822C 0xfff\n#define BIT_BEQ_HW_IDX_8822C(x)                                                \\\n\t(((x) & BIT_MASK_BEQ_HW_IDX_8822C) << BIT_SHIFT_BEQ_HW_IDX_8822C)\n#define BITS_BEQ_HW_IDX_8822C                                                  \\\n\t(BIT_MASK_BEQ_HW_IDX_8822C << BIT_SHIFT_BEQ_HW_IDX_8822C)\n#define BIT_CLEAR_BEQ_HW_IDX_8822C(x) ((x) & (~BITS_BEQ_HW_IDX_8822C))\n#define BIT_GET_BEQ_HW_IDX_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BEQ_HW_IDX_8822C) & BIT_MASK_BEQ_HW_IDX_8822C)\n#define BIT_SET_BEQ_HW_IDX_8822C(x, v)                                         \\\n\t(BIT_CLEAR_BEQ_HW_IDX_8822C(x) | BIT_BEQ_HW_IDX_8822C(v))\n\n#define BIT_SHIFT_BEQ_HOST_IDX_8822C 0\n#define BIT_MASK_BEQ_HOST_IDX_8822C 0xfff\n#define BIT_BEQ_HOST_IDX_8822C(x)                                              \\\n\t(((x) & BIT_MASK_BEQ_HOST_IDX_8822C) << BIT_SHIFT_BEQ_HOST_IDX_8822C)\n#define BITS_BEQ_HOST_IDX_8822C                                                \\\n\t(BIT_MASK_BEQ_HOST_IDX_8822C << BIT_SHIFT_BEQ_HOST_IDX_8822C)\n#define BIT_CLEAR_BEQ_HOST_IDX_8822C(x) ((x) & (~BITS_BEQ_HOST_IDX_8822C))\n#define BIT_GET_BEQ_HOST_IDX_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BEQ_HOST_IDX_8822C) & BIT_MASK_BEQ_HOST_IDX_8822C)\n#define BIT_SET_BEQ_HOST_IDX_8822C(x, v)                                       \\\n\t(BIT_CLEAR_BEQ_HOST_IDX_8822C(x) | BIT_BEQ_HOST_IDX_8822C(v))\n\n/* 2 REG_BKQ_TXBD_IDX_8822C */\n\n#define BIT_SHIFT_BKQ_HW_IDX_8822C 16\n#define BIT_MASK_BKQ_HW_IDX_8822C 0xfff\n#define BIT_BKQ_HW_IDX_8822C(x)                                                \\\n\t(((x) & BIT_MASK_BKQ_HW_IDX_8822C) << BIT_SHIFT_BKQ_HW_IDX_8822C)\n#define BITS_BKQ_HW_IDX_8822C                                                  \\\n\t(BIT_MASK_BKQ_HW_IDX_8822C << BIT_SHIFT_BKQ_HW_IDX_8822C)\n#define BIT_CLEAR_BKQ_HW_IDX_8822C(x) ((x) & (~BITS_BKQ_HW_IDX_8822C))\n#define BIT_GET_BKQ_HW_IDX_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BKQ_HW_IDX_8822C) & BIT_MASK_BKQ_HW_IDX_8822C)\n#define BIT_SET_BKQ_HW_IDX_8822C(x, v)                                         \\\n\t(BIT_CLEAR_BKQ_HW_IDX_8822C(x) | BIT_BKQ_HW_IDX_8822C(v))\n\n#define BIT_SHIFT_BKQ_HOST_IDX_8822C 0\n#define BIT_MASK_BKQ_HOST_IDX_8822C 0xfff\n#define BIT_BKQ_HOST_IDX_8822C(x)                                              \\\n\t(((x) & BIT_MASK_BKQ_HOST_IDX_8822C) << BIT_SHIFT_BKQ_HOST_IDX_8822C)\n#define BITS_BKQ_HOST_IDX_8822C                                                \\\n\t(BIT_MASK_BKQ_HOST_IDX_8822C << BIT_SHIFT_BKQ_HOST_IDX_8822C)\n#define BIT_CLEAR_BKQ_HOST_IDX_8822C(x) ((x) & (~BITS_BKQ_HOST_IDX_8822C))\n#define BIT_GET_BKQ_HOST_IDX_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BKQ_HOST_IDX_8822C) & BIT_MASK_BKQ_HOST_IDX_8822C)\n#define BIT_SET_BKQ_HOST_IDX_8822C(x, v)                                       \\\n\t(BIT_CLEAR_BKQ_HOST_IDX_8822C(x) | BIT_BKQ_HOST_IDX_8822C(v))\n\n/* 2 REG_MGQ_TXBD_IDX_8822C */\n\n#define BIT_SHIFT_MGQ_HW_IDX_8822C 16\n#define BIT_MASK_MGQ_HW_IDX_8822C 0xfff\n#define BIT_MGQ_HW_IDX_8822C(x)                                                \\\n\t(((x) & BIT_MASK_MGQ_HW_IDX_8822C) << BIT_SHIFT_MGQ_HW_IDX_8822C)\n#define BITS_MGQ_HW_IDX_8822C                                                  \\\n\t(BIT_MASK_MGQ_HW_IDX_8822C << BIT_SHIFT_MGQ_HW_IDX_8822C)\n#define BIT_CLEAR_MGQ_HW_IDX_8822C(x) ((x) & (~BITS_MGQ_HW_IDX_8822C))\n#define BIT_GET_MGQ_HW_IDX_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_MGQ_HW_IDX_8822C) & BIT_MASK_MGQ_HW_IDX_8822C)\n#define BIT_SET_MGQ_HW_IDX_8822C(x, v)                                         \\\n\t(BIT_CLEAR_MGQ_HW_IDX_8822C(x) | BIT_MGQ_HW_IDX_8822C(v))\n\n#define BIT_SHIFT_MGQ_HOST_IDX_8822C 0\n#define BIT_MASK_MGQ_HOST_IDX_8822C 0xfff\n#define BIT_MGQ_HOST_IDX_8822C(x)                                              \\\n\t(((x) & BIT_MASK_MGQ_HOST_IDX_8822C) << BIT_SHIFT_MGQ_HOST_IDX_8822C)\n#define BITS_MGQ_HOST_IDX_8822C                                                \\\n\t(BIT_MASK_MGQ_HOST_IDX_8822C << BIT_SHIFT_MGQ_HOST_IDX_8822C)\n#define BIT_CLEAR_MGQ_HOST_IDX_8822C(x) ((x) & (~BITS_MGQ_HOST_IDX_8822C))\n#define BIT_GET_MGQ_HOST_IDX_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_MGQ_HOST_IDX_8822C) & BIT_MASK_MGQ_HOST_IDX_8822C)\n#define BIT_SET_MGQ_HOST_IDX_8822C(x, v)                                       \\\n\t(BIT_CLEAR_MGQ_HOST_IDX_8822C(x) | BIT_MGQ_HOST_IDX_8822C(v))\n\n/* 2 REG_RXQ_RXBD_IDX_8822C */\n\n#define BIT_SHIFT_RXQ_HW_IDX_8822C 16\n#define BIT_MASK_RXQ_HW_IDX_8822C 0xfff\n#define BIT_RXQ_HW_IDX_8822C(x)                                                \\\n\t(((x) & BIT_MASK_RXQ_HW_IDX_8822C) << BIT_SHIFT_RXQ_HW_IDX_8822C)\n#define BITS_RXQ_HW_IDX_8822C                                                  \\\n\t(BIT_MASK_RXQ_HW_IDX_8822C << BIT_SHIFT_RXQ_HW_IDX_8822C)\n#define BIT_CLEAR_RXQ_HW_IDX_8822C(x) ((x) & (~BITS_RXQ_HW_IDX_8822C))\n#define BIT_GET_RXQ_HW_IDX_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXQ_HW_IDX_8822C) & BIT_MASK_RXQ_HW_IDX_8822C)\n#define BIT_SET_RXQ_HW_IDX_8822C(x, v)                                         \\\n\t(BIT_CLEAR_RXQ_HW_IDX_8822C(x) | BIT_RXQ_HW_IDX_8822C(v))\n\n#define BIT_SHIFT_RXQ_HOST_IDX_8822C 0\n#define BIT_MASK_RXQ_HOST_IDX_8822C 0xfff\n#define BIT_RXQ_HOST_IDX_8822C(x)                                              \\\n\t(((x) & BIT_MASK_RXQ_HOST_IDX_8822C) << BIT_SHIFT_RXQ_HOST_IDX_8822C)\n#define BITS_RXQ_HOST_IDX_8822C                                                \\\n\t(BIT_MASK_RXQ_HOST_IDX_8822C << BIT_SHIFT_RXQ_HOST_IDX_8822C)\n#define BIT_CLEAR_RXQ_HOST_IDX_8822C(x) ((x) & (~BITS_RXQ_HOST_IDX_8822C))\n#define BIT_GET_RXQ_HOST_IDX_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXQ_HOST_IDX_8822C) & BIT_MASK_RXQ_HOST_IDX_8822C)\n#define BIT_SET_RXQ_HOST_IDX_8822C(x, v)                                       \\\n\t(BIT_CLEAR_RXQ_HOST_IDX_8822C(x) | BIT_RXQ_HOST_IDX_8822C(v))\n\n/* 2 REG_HI0Q_TXBD_IDX_8822C */\n\n#define BIT_SHIFT_HI0Q_HW_IDX_8822C 16\n#define BIT_MASK_HI0Q_HW_IDX_8822C 0xfff\n#define BIT_HI0Q_HW_IDX_8822C(x)                                               \\\n\t(((x) & BIT_MASK_HI0Q_HW_IDX_8822C) << BIT_SHIFT_HI0Q_HW_IDX_8822C)\n#define BITS_HI0Q_HW_IDX_8822C                                                 \\\n\t(BIT_MASK_HI0Q_HW_IDX_8822C << BIT_SHIFT_HI0Q_HW_IDX_8822C)\n#define BIT_CLEAR_HI0Q_HW_IDX_8822C(x) ((x) & (~BITS_HI0Q_HW_IDX_8822C))\n#define BIT_GET_HI0Q_HW_IDX_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI0Q_HW_IDX_8822C) & BIT_MASK_HI0Q_HW_IDX_8822C)\n#define BIT_SET_HI0Q_HW_IDX_8822C(x, v)                                        \\\n\t(BIT_CLEAR_HI0Q_HW_IDX_8822C(x) | BIT_HI0Q_HW_IDX_8822C(v))\n\n#define BIT_SHIFT_HI0Q_HOST_IDX_8822C 0\n#define BIT_MASK_HI0Q_HOST_IDX_8822C 0xfff\n#define BIT_HI0Q_HOST_IDX_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HI0Q_HOST_IDX_8822C) << BIT_SHIFT_HI0Q_HOST_IDX_8822C)\n#define BITS_HI0Q_HOST_IDX_8822C                                               \\\n\t(BIT_MASK_HI0Q_HOST_IDX_8822C << BIT_SHIFT_HI0Q_HOST_IDX_8822C)\n#define BIT_CLEAR_HI0Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI0Q_HOST_IDX_8822C))\n#define BIT_GET_HI0Q_HOST_IDX_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8822C) & BIT_MASK_HI0Q_HOST_IDX_8822C)\n#define BIT_SET_HI0Q_HOST_IDX_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HI0Q_HOST_IDX_8822C(x) | BIT_HI0Q_HOST_IDX_8822C(v))\n\n/* 2 REG_HI1Q_TXBD_IDX_8822C */\n\n#define BIT_SHIFT_HI1Q_HW_IDX_8822C 16\n#define BIT_MASK_HI1Q_HW_IDX_8822C 0xfff\n#define BIT_HI1Q_HW_IDX_8822C(x)                                               \\\n\t(((x) & BIT_MASK_HI1Q_HW_IDX_8822C) << BIT_SHIFT_HI1Q_HW_IDX_8822C)\n#define BITS_HI1Q_HW_IDX_8822C                                                 \\\n\t(BIT_MASK_HI1Q_HW_IDX_8822C << BIT_SHIFT_HI1Q_HW_IDX_8822C)\n#define BIT_CLEAR_HI1Q_HW_IDX_8822C(x) ((x) & (~BITS_HI1Q_HW_IDX_8822C))\n#define BIT_GET_HI1Q_HW_IDX_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI1Q_HW_IDX_8822C) & BIT_MASK_HI1Q_HW_IDX_8822C)\n#define BIT_SET_HI1Q_HW_IDX_8822C(x, v)                                        \\\n\t(BIT_CLEAR_HI1Q_HW_IDX_8822C(x) | BIT_HI1Q_HW_IDX_8822C(v))\n\n#define BIT_SHIFT_HI1Q_HOST_IDX_8822C 0\n#define BIT_MASK_HI1Q_HOST_IDX_8822C 0xfff\n#define BIT_HI1Q_HOST_IDX_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HI1Q_HOST_IDX_8822C) << BIT_SHIFT_HI1Q_HOST_IDX_8822C)\n#define BITS_HI1Q_HOST_IDX_8822C                                               \\\n\t(BIT_MASK_HI1Q_HOST_IDX_8822C << BIT_SHIFT_HI1Q_HOST_IDX_8822C)\n#define BIT_CLEAR_HI1Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI1Q_HOST_IDX_8822C))\n#define BIT_GET_HI1Q_HOST_IDX_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8822C) & BIT_MASK_HI1Q_HOST_IDX_8822C)\n#define BIT_SET_HI1Q_HOST_IDX_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HI1Q_HOST_IDX_8822C(x) | BIT_HI1Q_HOST_IDX_8822C(v))\n\n/* 2 REG_HI2Q_TXBD_IDX_8822C */\n\n#define BIT_SHIFT_HI2Q_HW_IDX_8822C 16\n#define BIT_MASK_HI2Q_HW_IDX_8822C 0xfff\n#define BIT_HI2Q_HW_IDX_8822C(x)                                               \\\n\t(((x) & BIT_MASK_HI2Q_HW_IDX_8822C) << BIT_SHIFT_HI2Q_HW_IDX_8822C)\n#define BITS_HI2Q_HW_IDX_8822C                                                 \\\n\t(BIT_MASK_HI2Q_HW_IDX_8822C << BIT_SHIFT_HI2Q_HW_IDX_8822C)\n#define BIT_CLEAR_HI2Q_HW_IDX_8822C(x) ((x) & (~BITS_HI2Q_HW_IDX_8822C))\n#define BIT_GET_HI2Q_HW_IDX_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI2Q_HW_IDX_8822C) & BIT_MASK_HI2Q_HW_IDX_8822C)\n#define BIT_SET_HI2Q_HW_IDX_8822C(x, v)                                        \\\n\t(BIT_CLEAR_HI2Q_HW_IDX_8822C(x) | BIT_HI2Q_HW_IDX_8822C(v))\n\n#define BIT_SHIFT_HI2Q_HOST_IDX_8822C 0\n#define BIT_MASK_HI2Q_HOST_IDX_8822C 0xfff\n#define BIT_HI2Q_HOST_IDX_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HI2Q_HOST_IDX_8822C) << BIT_SHIFT_HI2Q_HOST_IDX_8822C)\n#define BITS_HI2Q_HOST_IDX_8822C                                               \\\n\t(BIT_MASK_HI2Q_HOST_IDX_8822C << BIT_SHIFT_HI2Q_HOST_IDX_8822C)\n#define BIT_CLEAR_HI2Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI2Q_HOST_IDX_8822C))\n#define BIT_GET_HI2Q_HOST_IDX_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8822C) & BIT_MASK_HI2Q_HOST_IDX_8822C)\n#define BIT_SET_HI2Q_HOST_IDX_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HI2Q_HOST_IDX_8822C(x) | BIT_HI2Q_HOST_IDX_8822C(v))\n\n/* 2 REG_HI3Q_TXBD_IDX_8822C */\n\n#define BIT_SHIFT_HI3Q_HW_IDX_8822C 16\n#define BIT_MASK_HI3Q_HW_IDX_8822C 0xfff\n#define BIT_HI3Q_HW_IDX_8822C(x)                                               \\\n\t(((x) & BIT_MASK_HI3Q_HW_IDX_8822C) << BIT_SHIFT_HI3Q_HW_IDX_8822C)\n#define BITS_HI3Q_HW_IDX_8822C                                                 \\\n\t(BIT_MASK_HI3Q_HW_IDX_8822C << BIT_SHIFT_HI3Q_HW_IDX_8822C)\n#define BIT_CLEAR_HI3Q_HW_IDX_8822C(x) ((x) & (~BITS_HI3Q_HW_IDX_8822C))\n#define BIT_GET_HI3Q_HW_IDX_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI3Q_HW_IDX_8822C) & BIT_MASK_HI3Q_HW_IDX_8822C)\n#define BIT_SET_HI3Q_HW_IDX_8822C(x, v)                                        \\\n\t(BIT_CLEAR_HI3Q_HW_IDX_8822C(x) | BIT_HI3Q_HW_IDX_8822C(v))\n\n#define BIT_SHIFT_HI3Q_HOST_IDX_8822C 0\n#define BIT_MASK_HI3Q_HOST_IDX_8822C 0xfff\n#define BIT_HI3Q_HOST_IDX_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HI3Q_HOST_IDX_8822C) << BIT_SHIFT_HI3Q_HOST_IDX_8822C)\n#define BITS_HI3Q_HOST_IDX_8822C                                               \\\n\t(BIT_MASK_HI3Q_HOST_IDX_8822C << BIT_SHIFT_HI3Q_HOST_IDX_8822C)\n#define BIT_CLEAR_HI3Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI3Q_HOST_IDX_8822C))\n#define BIT_GET_HI3Q_HOST_IDX_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8822C) & BIT_MASK_HI3Q_HOST_IDX_8822C)\n#define BIT_SET_HI3Q_HOST_IDX_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HI3Q_HOST_IDX_8822C(x) | BIT_HI3Q_HOST_IDX_8822C(v))\n\n/* 2 REG_HI4Q_TXBD_IDX_8822C */\n\n#define BIT_SHIFT_HI4Q_HW_IDX_8822C 16\n#define BIT_MASK_HI4Q_HW_IDX_8822C 0xfff\n#define BIT_HI4Q_HW_IDX_8822C(x)                                               \\\n\t(((x) & BIT_MASK_HI4Q_HW_IDX_8822C) << BIT_SHIFT_HI4Q_HW_IDX_8822C)\n#define BITS_HI4Q_HW_IDX_8822C                                                 \\\n\t(BIT_MASK_HI4Q_HW_IDX_8822C << BIT_SHIFT_HI4Q_HW_IDX_8822C)\n#define BIT_CLEAR_HI4Q_HW_IDX_8822C(x) ((x) & (~BITS_HI4Q_HW_IDX_8822C))\n#define BIT_GET_HI4Q_HW_IDX_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI4Q_HW_IDX_8822C) & BIT_MASK_HI4Q_HW_IDX_8822C)\n#define BIT_SET_HI4Q_HW_IDX_8822C(x, v)                                        \\\n\t(BIT_CLEAR_HI4Q_HW_IDX_8822C(x) | BIT_HI4Q_HW_IDX_8822C(v))\n\n#define BIT_SHIFT_HI4Q_HOST_IDX_8822C 0\n#define BIT_MASK_HI4Q_HOST_IDX_8822C 0xfff\n#define BIT_HI4Q_HOST_IDX_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HI4Q_HOST_IDX_8822C) << BIT_SHIFT_HI4Q_HOST_IDX_8822C)\n#define BITS_HI4Q_HOST_IDX_8822C                                               \\\n\t(BIT_MASK_HI4Q_HOST_IDX_8822C << BIT_SHIFT_HI4Q_HOST_IDX_8822C)\n#define BIT_CLEAR_HI4Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI4Q_HOST_IDX_8822C))\n#define BIT_GET_HI4Q_HOST_IDX_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8822C) & BIT_MASK_HI4Q_HOST_IDX_8822C)\n#define BIT_SET_HI4Q_HOST_IDX_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HI4Q_HOST_IDX_8822C(x) | BIT_HI4Q_HOST_IDX_8822C(v))\n\n/* 2 REG_HI5Q_TXBD_IDX_8822C */\n\n#define BIT_SHIFT_HI5Q_HW_IDX_8822C 16\n#define BIT_MASK_HI5Q_HW_IDX_8822C 0xfff\n#define BIT_HI5Q_HW_IDX_8822C(x)                                               \\\n\t(((x) & BIT_MASK_HI5Q_HW_IDX_8822C) << BIT_SHIFT_HI5Q_HW_IDX_8822C)\n#define BITS_HI5Q_HW_IDX_8822C                                                 \\\n\t(BIT_MASK_HI5Q_HW_IDX_8822C << BIT_SHIFT_HI5Q_HW_IDX_8822C)\n#define BIT_CLEAR_HI5Q_HW_IDX_8822C(x) ((x) & (~BITS_HI5Q_HW_IDX_8822C))\n#define BIT_GET_HI5Q_HW_IDX_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI5Q_HW_IDX_8822C) & BIT_MASK_HI5Q_HW_IDX_8822C)\n#define BIT_SET_HI5Q_HW_IDX_8822C(x, v)                                        \\\n\t(BIT_CLEAR_HI5Q_HW_IDX_8822C(x) | BIT_HI5Q_HW_IDX_8822C(v))\n\n#define BIT_SHIFT_HI5Q_HOST_IDX_8822C 0\n#define BIT_MASK_HI5Q_HOST_IDX_8822C 0xfff\n#define BIT_HI5Q_HOST_IDX_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HI5Q_HOST_IDX_8822C) << BIT_SHIFT_HI5Q_HOST_IDX_8822C)\n#define BITS_HI5Q_HOST_IDX_8822C                                               \\\n\t(BIT_MASK_HI5Q_HOST_IDX_8822C << BIT_SHIFT_HI5Q_HOST_IDX_8822C)\n#define BIT_CLEAR_HI5Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI5Q_HOST_IDX_8822C))\n#define BIT_GET_HI5Q_HOST_IDX_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8822C) & BIT_MASK_HI5Q_HOST_IDX_8822C)\n#define BIT_SET_HI5Q_HOST_IDX_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HI5Q_HOST_IDX_8822C(x) | BIT_HI5Q_HOST_IDX_8822C(v))\n\n/* 2 REG_HI6Q_TXBD_IDX_8822C */\n\n#define BIT_SHIFT_HI6Q_HW_IDX_8822C 16\n#define BIT_MASK_HI6Q_HW_IDX_8822C 0xfff\n#define BIT_HI6Q_HW_IDX_8822C(x)                                               \\\n\t(((x) & BIT_MASK_HI6Q_HW_IDX_8822C) << BIT_SHIFT_HI6Q_HW_IDX_8822C)\n#define BITS_HI6Q_HW_IDX_8822C                                                 \\\n\t(BIT_MASK_HI6Q_HW_IDX_8822C << BIT_SHIFT_HI6Q_HW_IDX_8822C)\n#define BIT_CLEAR_HI6Q_HW_IDX_8822C(x) ((x) & (~BITS_HI6Q_HW_IDX_8822C))\n#define BIT_GET_HI6Q_HW_IDX_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI6Q_HW_IDX_8822C) & BIT_MASK_HI6Q_HW_IDX_8822C)\n#define BIT_SET_HI6Q_HW_IDX_8822C(x, v)                                        \\\n\t(BIT_CLEAR_HI6Q_HW_IDX_8822C(x) | BIT_HI6Q_HW_IDX_8822C(v))\n\n#define BIT_SHIFT_HI6Q_HOST_IDX_8822C 0\n#define BIT_MASK_HI6Q_HOST_IDX_8822C 0xfff\n#define BIT_HI6Q_HOST_IDX_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HI6Q_HOST_IDX_8822C) << BIT_SHIFT_HI6Q_HOST_IDX_8822C)\n#define BITS_HI6Q_HOST_IDX_8822C                                               \\\n\t(BIT_MASK_HI6Q_HOST_IDX_8822C << BIT_SHIFT_HI6Q_HOST_IDX_8822C)\n#define BIT_CLEAR_HI6Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI6Q_HOST_IDX_8822C))\n#define BIT_GET_HI6Q_HOST_IDX_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8822C) & BIT_MASK_HI6Q_HOST_IDX_8822C)\n#define BIT_SET_HI6Q_HOST_IDX_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HI6Q_HOST_IDX_8822C(x) | BIT_HI6Q_HOST_IDX_8822C(v))\n\n/* 2 REG_HI7Q_TXBD_IDX_8822C */\n\n#define BIT_SHIFT_HI7Q_HW_IDX_8822C 16\n#define BIT_MASK_HI7Q_HW_IDX_8822C 0xfff\n#define BIT_HI7Q_HW_IDX_8822C(x)                                               \\\n\t(((x) & BIT_MASK_HI7Q_HW_IDX_8822C) << BIT_SHIFT_HI7Q_HW_IDX_8822C)\n#define BITS_HI7Q_HW_IDX_8822C                                                 \\\n\t(BIT_MASK_HI7Q_HW_IDX_8822C << BIT_SHIFT_HI7Q_HW_IDX_8822C)\n#define BIT_CLEAR_HI7Q_HW_IDX_8822C(x) ((x) & (~BITS_HI7Q_HW_IDX_8822C))\n#define BIT_GET_HI7Q_HW_IDX_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HI7Q_HW_IDX_8822C) & BIT_MASK_HI7Q_HW_IDX_8822C)\n#define BIT_SET_HI7Q_HW_IDX_8822C(x, v)                                        \\\n\t(BIT_CLEAR_HI7Q_HW_IDX_8822C(x) | BIT_HI7Q_HW_IDX_8822C(v))\n\n#define BIT_SHIFT_HI7Q_HOST_IDX_8822C 0\n#define BIT_MASK_HI7Q_HOST_IDX_8822C 0xfff\n#define BIT_HI7Q_HOST_IDX_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HI7Q_HOST_IDX_8822C) << BIT_SHIFT_HI7Q_HOST_IDX_8822C)\n#define BITS_HI7Q_HOST_IDX_8822C                                               \\\n\t(BIT_MASK_HI7Q_HOST_IDX_8822C << BIT_SHIFT_HI7Q_HOST_IDX_8822C)\n#define BIT_CLEAR_HI7Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI7Q_HOST_IDX_8822C))\n#define BIT_GET_HI7Q_HOST_IDX_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8822C) & BIT_MASK_HI7Q_HOST_IDX_8822C)\n#define BIT_SET_HI7Q_HOST_IDX_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HI7Q_HOST_IDX_8822C(x) | BIT_HI7Q_HOST_IDX_8822C(v))\n\n/* 2 REG_DBG_SEL_V1_8822C */\n\n#define BIT_SHIFT_DBG_SEL_8822C 0\n#define BIT_MASK_DBG_SEL_8822C 0xff\n#define BIT_DBG_SEL_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_DBG_SEL_8822C) << BIT_SHIFT_DBG_SEL_8822C)\n#define BITS_DBG_SEL_8822C (BIT_MASK_DBG_SEL_8822C << BIT_SHIFT_DBG_SEL_8822C)\n#define BIT_CLEAR_DBG_SEL_8822C(x) ((x) & (~BITS_DBG_SEL_8822C))\n#define BIT_GET_DBG_SEL_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_DBG_SEL_8822C) & BIT_MASK_DBG_SEL_8822C)\n#define BIT_SET_DBG_SEL_8822C(x, v)                                            \\\n\t(BIT_CLEAR_DBG_SEL_8822C(x) | BIT_DBG_SEL_8822C(v))\n\n/* 2 REG_PCIE_HRPWM1_V1_8822C */\n\n#define BIT_SHIFT_PCIE_HRPWM_8822C 0\n#define BIT_MASK_PCIE_HRPWM_8822C 0xff\n#define BIT_PCIE_HRPWM_8822C(x)                                                \\\n\t(((x) & BIT_MASK_PCIE_HRPWM_8822C) << BIT_SHIFT_PCIE_HRPWM_8822C)\n#define BITS_PCIE_HRPWM_8822C                                                  \\\n\t(BIT_MASK_PCIE_HRPWM_8822C << BIT_SHIFT_PCIE_HRPWM_8822C)\n#define BIT_CLEAR_PCIE_HRPWM_8822C(x) ((x) & (~BITS_PCIE_HRPWM_8822C))\n#define BIT_GET_PCIE_HRPWM_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_PCIE_HRPWM_8822C) & BIT_MASK_PCIE_HRPWM_8822C)\n#define BIT_SET_PCIE_HRPWM_8822C(x, v)                                         \\\n\t(BIT_CLEAR_PCIE_HRPWM_8822C(x) | BIT_PCIE_HRPWM_8822C(v))\n\n/* 2 REG_PCIE_HCPWM1_V1_8822C */\n\n#define BIT_SHIFT_PCIE_HCPWM_8822C 0\n#define BIT_MASK_PCIE_HCPWM_8822C 0xff\n#define BIT_PCIE_HCPWM_8822C(x)                                                \\\n\t(((x) & BIT_MASK_PCIE_HCPWM_8822C) << BIT_SHIFT_PCIE_HCPWM_8822C)\n#define BITS_PCIE_HCPWM_8822C                                                  \\\n\t(BIT_MASK_PCIE_HCPWM_8822C << BIT_SHIFT_PCIE_HCPWM_8822C)\n#define BIT_CLEAR_PCIE_HCPWM_8822C(x) ((x) & (~BITS_PCIE_HCPWM_8822C))\n#define BIT_GET_PCIE_HCPWM_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_PCIE_HCPWM_8822C) & BIT_MASK_PCIE_HCPWM_8822C)\n#define BIT_SET_PCIE_HCPWM_8822C(x, v)                                         \\\n\t(BIT_CLEAR_PCIE_HCPWM_8822C(x) | BIT_PCIE_HCPWM_8822C(v))\n\n/* 2 REG_PCIE_CTRL2_8822C */\n#define BIT_DIS_TXDMA_PRE_8822C BIT(7)\n#define BIT_DIS_RXDMA_PRE_8822C BIT(6)\n\n#define BIT_SHIFT_HPS_CLKR_PCIE_8822C 4\n#define BIT_MASK_HPS_CLKR_PCIE_8822C 0x3\n#define BIT_HPS_CLKR_PCIE_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HPS_CLKR_PCIE_8822C) << BIT_SHIFT_HPS_CLKR_PCIE_8822C)\n#define BITS_HPS_CLKR_PCIE_8822C                                               \\\n\t(BIT_MASK_HPS_CLKR_PCIE_8822C << BIT_SHIFT_HPS_CLKR_PCIE_8822C)\n#define BIT_CLEAR_HPS_CLKR_PCIE_8822C(x) ((x) & (~BITS_HPS_CLKR_PCIE_8822C))\n#define BIT_GET_HPS_CLKR_PCIE_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8822C) & BIT_MASK_HPS_CLKR_PCIE_8822C)\n#define BIT_SET_HPS_CLKR_PCIE_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HPS_CLKR_PCIE_8822C(x) | BIT_HPS_CLKR_PCIE_8822C(v))\n\n#define BIT_PCIE_INT_8822C BIT(3)\n#define BIT_TXFLAG_EXIT_L1_EN_8822C BIT(2)\n#define BIT_EN_RXDMA_ALIGN_8822C BIT(1)\n#define BIT_EN_TXDMA_ALIGN_8822C BIT(0)\n\n/* 2 REG_PCIE_HRPWM2_V1_8822C */\n\n#define BIT_SHIFT_PCIE_HRPWM2_8822C 0\n#define BIT_MASK_PCIE_HRPWM2_8822C 0xffff\n#define BIT_PCIE_HRPWM2_8822C(x)                                               \\\n\t(((x) & BIT_MASK_PCIE_HRPWM2_8822C) << BIT_SHIFT_PCIE_HRPWM2_8822C)\n#define BITS_PCIE_HRPWM2_8822C                                                 \\\n\t(BIT_MASK_PCIE_HRPWM2_8822C << BIT_SHIFT_PCIE_HRPWM2_8822C)\n#define BIT_CLEAR_PCIE_HRPWM2_8822C(x) ((x) & (~BITS_PCIE_HRPWM2_8822C))\n#define BIT_GET_PCIE_HRPWM2_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_PCIE_HRPWM2_8822C) & BIT_MASK_PCIE_HRPWM2_8822C)\n#define BIT_SET_PCIE_HRPWM2_8822C(x, v)                                        \\\n\t(BIT_CLEAR_PCIE_HRPWM2_8822C(x) | BIT_PCIE_HRPWM2_8822C(v))\n\n/* 2 REG_PCIE_HCPWM2_V1_8822C */\n\n#define BIT_SHIFT_PCIE_HCPWM2_8822C 0\n#define BIT_MASK_PCIE_HCPWM2_8822C 0xffff\n#define BIT_PCIE_HCPWM2_8822C(x)                                               \\\n\t(((x) & BIT_MASK_PCIE_HCPWM2_8822C) << BIT_SHIFT_PCIE_HCPWM2_8822C)\n#define BITS_PCIE_HCPWM2_8822C                                                 \\\n\t(BIT_MASK_PCIE_HCPWM2_8822C << BIT_SHIFT_PCIE_HCPWM2_8822C)\n#define BIT_CLEAR_PCIE_HCPWM2_8822C(x) ((x) & (~BITS_PCIE_HCPWM2_8822C))\n#define BIT_GET_PCIE_HCPWM2_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_PCIE_HCPWM2_8822C) & BIT_MASK_PCIE_HCPWM2_8822C)\n#define BIT_SET_PCIE_HCPWM2_8822C(x, v)                                        \\\n\t(BIT_CLEAR_PCIE_HCPWM2_8822C(x) | BIT_PCIE_HCPWM2_8822C(v))\n\n/* 2 REG_PCIE_H2C_MSG_V1_8822C */\n\n#define BIT_SHIFT_DRV2FW_INFO_8822C 0\n#define BIT_MASK_DRV2FW_INFO_8822C 0xffffffffL\n#define BIT_DRV2FW_INFO_8822C(x)                                               \\\n\t(((x) & BIT_MASK_DRV2FW_INFO_8822C) << BIT_SHIFT_DRV2FW_INFO_8822C)\n#define BITS_DRV2FW_INFO_8822C                                                 \\\n\t(BIT_MASK_DRV2FW_INFO_8822C << BIT_SHIFT_DRV2FW_INFO_8822C)\n#define BIT_CLEAR_DRV2FW_INFO_8822C(x) ((x) & (~BITS_DRV2FW_INFO_8822C))\n#define BIT_GET_DRV2FW_INFO_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_DRV2FW_INFO_8822C) & BIT_MASK_DRV2FW_INFO_8822C)\n#define BIT_SET_DRV2FW_INFO_8822C(x, v)                                        \\\n\t(BIT_CLEAR_DRV2FW_INFO_8822C(x) | BIT_DRV2FW_INFO_8822C(v))\n\n/* 2 REG_PCIE_C2H_MSG_V1_8822C */\n\n#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C 0\n#define BIT_MASK_HCI_PCIE_C2H_MSG_8822C 0xffffffffL\n#define BIT_HCI_PCIE_C2H_MSG_8822C(x)                                          \\\n\t(((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8822C)                               \\\n\t << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C)\n#define BITS_HCI_PCIE_C2H_MSG_8822C                                            \\\n\t(BIT_MASK_HCI_PCIE_C2H_MSG_8822C << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C)\n#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8822C(x)                                    \\\n\t((x) & (~BITS_HCI_PCIE_C2H_MSG_8822C))\n#define BIT_GET_HCI_PCIE_C2H_MSG_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C) &                           \\\n\t BIT_MASK_HCI_PCIE_C2H_MSG_8822C)\n#define BIT_SET_HCI_PCIE_C2H_MSG_8822C(x, v)                                   \\\n\t(BIT_CLEAR_HCI_PCIE_C2H_MSG_8822C(x) | BIT_HCI_PCIE_C2H_MSG_8822C(v))\n\n/* 2 REG_DBI_WDATA_V1_8822C */\n\n#define BIT_SHIFT_DBI_WDATA_8822C 0\n#define BIT_MASK_DBI_WDATA_8822C 0xffffffffL\n#define BIT_DBI_WDATA_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_DBI_WDATA_8822C) << BIT_SHIFT_DBI_WDATA_8822C)\n#define BITS_DBI_WDATA_8822C                                                   \\\n\t(BIT_MASK_DBI_WDATA_8822C << BIT_SHIFT_DBI_WDATA_8822C)\n#define BIT_CLEAR_DBI_WDATA_8822C(x) ((x) & (~BITS_DBI_WDATA_8822C))\n#define BIT_GET_DBI_WDATA_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBI_WDATA_8822C) & BIT_MASK_DBI_WDATA_8822C)\n#define BIT_SET_DBI_WDATA_8822C(x, v)                                          \\\n\t(BIT_CLEAR_DBI_WDATA_8822C(x) | BIT_DBI_WDATA_8822C(v))\n\n/* 2 REG_DBI_RDATA_V1_8822C */\n\n#define BIT_SHIFT_DBI_RDATA_8822C 0\n#define BIT_MASK_DBI_RDATA_8822C 0xffffffffL\n#define BIT_DBI_RDATA_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_DBI_RDATA_8822C) << BIT_SHIFT_DBI_RDATA_8822C)\n#define BITS_DBI_RDATA_8822C                                                   \\\n\t(BIT_MASK_DBI_RDATA_8822C << BIT_SHIFT_DBI_RDATA_8822C)\n#define BIT_CLEAR_DBI_RDATA_8822C(x) ((x) & (~BITS_DBI_RDATA_8822C))\n#define BIT_GET_DBI_RDATA_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_DBI_RDATA_8822C) & BIT_MASK_DBI_RDATA_8822C)\n#define BIT_SET_DBI_RDATA_8822C(x, v)                                          \\\n\t(BIT_CLEAR_DBI_RDATA_8822C(x) | BIT_DBI_RDATA_8822C(v))\n\n/* 2 REG_DBI_FLAG_V1_8822C */\n#define BIT_EN_STUCK_DBG_8822C BIT(26)\n#define BIT_RX_STUCK_8822C BIT(25)\n#define BIT_TX_STUCK_8822C BIT(24)\n#define BIT_DBI_RFLAG_8822C BIT(17)\n#define BIT_DBI_WFLAG_8822C BIT(16)\n\n#define BIT_SHIFT_DBI_WREN_8822C 12\n#define BIT_MASK_DBI_WREN_8822C 0xf\n#define BIT_DBI_WREN_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_DBI_WREN_8822C) << BIT_SHIFT_DBI_WREN_8822C)\n#define BITS_DBI_WREN_8822C                                                    \\\n\t(BIT_MASK_DBI_WREN_8822C << BIT_SHIFT_DBI_WREN_8822C)\n#define BIT_CLEAR_DBI_WREN_8822C(x) ((x) & (~BITS_DBI_WREN_8822C))\n#define BIT_GET_DBI_WREN_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_DBI_WREN_8822C) & BIT_MASK_DBI_WREN_8822C)\n#define BIT_SET_DBI_WREN_8822C(x, v)                                           \\\n\t(BIT_CLEAR_DBI_WREN_8822C(x) | BIT_DBI_WREN_8822C(v))\n\n#define BIT_SHIFT_DBI_ADDR_8822C 0\n#define BIT_MASK_DBI_ADDR_8822C 0xfff\n#define BIT_DBI_ADDR_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_DBI_ADDR_8822C) << BIT_SHIFT_DBI_ADDR_8822C)\n#define BITS_DBI_ADDR_8822C                                                    \\\n\t(BIT_MASK_DBI_ADDR_8822C << BIT_SHIFT_DBI_ADDR_8822C)\n#define BIT_CLEAR_DBI_ADDR_8822C(x) ((x) & (~BITS_DBI_ADDR_8822C))\n#define BIT_GET_DBI_ADDR_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_DBI_ADDR_8822C) & BIT_MASK_DBI_ADDR_8822C)\n#define BIT_SET_DBI_ADDR_8822C(x, v)                                           \\\n\t(BIT_CLEAR_DBI_ADDR_8822C(x) | BIT_DBI_ADDR_8822C(v))\n\n/* 2 REG_MDIO_V1_8822C */\n\n#define BIT_SHIFT_MDIO_RDATA_8822C 16\n#define BIT_MASK_MDIO_RDATA_8822C 0xffff\n#define BIT_MDIO_RDATA_8822C(x)                                                \\\n\t(((x) & BIT_MASK_MDIO_RDATA_8822C) << BIT_SHIFT_MDIO_RDATA_8822C)\n#define BITS_MDIO_RDATA_8822C                                                  \\\n\t(BIT_MASK_MDIO_RDATA_8822C << BIT_SHIFT_MDIO_RDATA_8822C)\n#define BIT_CLEAR_MDIO_RDATA_8822C(x) ((x) & (~BITS_MDIO_RDATA_8822C))\n#define BIT_GET_MDIO_RDATA_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_MDIO_RDATA_8822C) & BIT_MASK_MDIO_RDATA_8822C)\n#define BIT_SET_MDIO_RDATA_8822C(x, v)                                         \\\n\t(BIT_CLEAR_MDIO_RDATA_8822C(x) | BIT_MDIO_RDATA_8822C(v))\n\n#define BIT_SHIFT_MDIO_WDATA_8822C 0\n#define BIT_MASK_MDIO_WDATA_8822C 0xffff\n#define BIT_MDIO_WDATA_8822C(x)                                                \\\n\t(((x) & BIT_MASK_MDIO_WDATA_8822C) << BIT_SHIFT_MDIO_WDATA_8822C)\n#define BITS_MDIO_WDATA_8822C                                                  \\\n\t(BIT_MASK_MDIO_WDATA_8822C << BIT_SHIFT_MDIO_WDATA_8822C)\n#define BIT_CLEAR_MDIO_WDATA_8822C(x) ((x) & (~BITS_MDIO_WDATA_8822C))\n#define BIT_GET_MDIO_WDATA_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_MDIO_WDATA_8822C) & BIT_MASK_MDIO_WDATA_8822C)\n#define BIT_SET_MDIO_WDATA_8822C(x, v)                                         \\\n\t(BIT_CLEAR_MDIO_WDATA_8822C(x) | BIT_MDIO_WDATA_8822C(v))\n\n/* 2 REG_PCIE_MIX_CFG_8822C */\n\n#define BIT_SHIFT_MDIO_PHY_ADDR_8822C 24\n#define BIT_MASK_MDIO_PHY_ADDR_8822C 0x1f\n#define BIT_MDIO_PHY_ADDR_8822C(x)                                             \\\n\t(((x) & BIT_MASK_MDIO_PHY_ADDR_8822C) << BIT_SHIFT_MDIO_PHY_ADDR_8822C)\n#define BITS_MDIO_PHY_ADDR_8822C                                               \\\n\t(BIT_MASK_MDIO_PHY_ADDR_8822C << BIT_SHIFT_MDIO_PHY_ADDR_8822C)\n#define BIT_CLEAR_MDIO_PHY_ADDR_8822C(x) ((x) & (~BITS_MDIO_PHY_ADDR_8822C))\n#define BIT_GET_MDIO_PHY_ADDR_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8822C) & BIT_MASK_MDIO_PHY_ADDR_8822C)\n#define BIT_SET_MDIO_PHY_ADDR_8822C(x, v)                                      \\\n\t(BIT_CLEAR_MDIO_PHY_ADDR_8822C(x) | BIT_MDIO_PHY_ADDR_8822C(v))\n\n#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C 10\n#define BIT_MASK_WATCH_DOG_RECORD_V1_8822C 0x3fff\n#define BIT_WATCH_DOG_RECORD_V1_8822C(x)                                       \\\n\t(((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8822C)                            \\\n\t << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C)\n#define BITS_WATCH_DOG_RECORD_V1_8822C                                         \\\n\t(BIT_MASK_WATCH_DOG_RECORD_V1_8822C                                    \\\n\t << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C)\n#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8822C(x)                                 \\\n\t((x) & (~BITS_WATCH_DOG_RECORD_V1_8822C))\n#define BIT_GET_WATCH_DOG_RECORD_V1_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C) &                        \\\n\t BIT_MASK_WATCH_DOG_RECORD_V1_8822C)\n#define BIT_SET_WATCH_DOG_RECORD_V1_8822C(x, v)                                \\\n\t(BIT_CLEAR_WATCH_DOG_RECORD_V1_8822C(x) |                              \\\n\t BIT_WATCH_DOG_RECORD_V1_8822C(v))\n\n#define BIT_R_IO_TIMEOUT_FLAG_V1_8822C BIT(9)\n#define BIT_EN_WATCH_DOG_8822C BIT(8)\n#define BIT_ECRC_EN_V1_8822C BIT(7)\n#define BIT_MDIO_RFLAG_V1_8822C BIT(6)\n#define BIT_MDIO_WFLAG_V1_8822C BIT(5)\n\n#define BIT_SHIFT_MDIO_REG_ADDR_V1_8822C 0\n#define BIT_MASK_MDIO_REG_ADDR_V1_8822C 0x1f\n#define BIT_MDIO_REG_ADDR_V1_8822C(x)                                          \\\n\t(((x) & BIT_MASK_MDIO_REG_ADDR_V1_8822C)                               \\\n\t << BIT_SHIFT_MDIO_REG_ADDR_V1_8822C)\n#define BITS_MDIO_REG_ADDR_V1_8822C                                            \\\n\t(BIT_MASK_MDIO_REG_ADDR_V1_8822C << BIT_SHIFT_MDIO_REG_ADDR_V1_8822C)\n#define BIT_CLEAR_MDIO_REG_ADDR_V1_8822C(x)                                    \\\n\t((x) & (~BITS_MDIO_REG_ADDR_V1_8822C))\n#define BIT_GET_MDIO_REG_ADDR_V1_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8822C) &                           \\\n\t BIT_MASK_MDIO_REG_ADDR_V1_8822C)\n#define BIT_SET_MDIO_REG_ADDR_V1_8822C(x, v)                                   \\\n\t(BIT_CLEAR_MDIO_REG_ADDR_V1_8822C(x) | BIT_MDIO_REG_ADDR_V1_8822C(v))\n\n/* 2 REG_HCI_MIX_CFG_8822C */\n\n#define BIT_SHIFT_WATCH_DOG_TIMER_8822C 28\n#define BIT_MASK_WATCH_DOG_TIMER_8822C 0xf\n#define BIT_WATCH_DOG_TIMER_8822C(x)                                           \\\n\t(((x) & BIT_MASK_WATCH_DOG_TIMER_8822C)                                \\\n\t << BIT_SHIFT_WATCH_DOG_TIMER_8822C)\n#define BITS_WATCH_DOG_TIMER_8822C                                             \\\n\t(BIT_MASK_WATCH_DOG_TIMER_8822C << BIT_SHIFT_WATCH_DOG_TIMER_8822C)\n#define BIT_CLEAR_WATCH_DOG_TIMER_8822C(x) ((x) & (~BITS_WATCH_DOG_TIMER_8822C))\n#define BIT_GET_WATCH_DOG_TIMER_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_WATCH_DOG_TIMER_8822C) &                            \\\n\t BIT_MASK_WATCH_DOG_TIMER_8822C)\n#define BIT_SET_WATCH_DOG_TIMER_8822C(x, v)                                    \\\n\t(BIT_CLEAR_WATCH_DOG_TIMER_8822C(x) | BIT_WATCH_DOG_TIMER_8822C(v))\n\n#define BIT_EN_ALIGN_MTU_8822C BIT(23)\n\n#define BIT_SHIFT_LATENCY_CONTROL_8822C 21\n#define BIT_MASK_LATENCY_CONTROL_8822C 0x3\n#define BIT_LATENCY_CONTROL_8822C(x)                                           \\\n\t(((x) & BIT_MASK_LATENCY_CONTROL_8822C)                                \\\n\t << BIT_SHIFT_LATENCY_CONTROL_8822C)\n#define BITS_LATENCY_CONTROL_8822C                                             \\\n\t(BIT_MASK_LATENCY_CONTROL_8822C << BIT_SHIFT_LATENCY_CONTROL_8822C)\n#define BIT_CLEAR_LATENCY_CONTROL_8822C(x) ((x) & (~BITS_LATENCY_CONTROL_8822C))\n#define BIT_GET_LATENCY_CONTROL_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_LATENCY_CONTROL_8822C) &                            \\\n\t BIT_MASK_LATENCY_CONTROL_8822C)\n#define BIT_SET_LATENCY_CONTROL_8822C(x, v)                                    \\\n\t(BIT_CLEAR_LATENCY_CONTROL_8822C(x) | BIT_LATENCY_CONTROL_8822C(v))\n\n#define BIT_HOST_GEN2_SUPPORT_8822C BIT(20)\n\n#define BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C 15\n#define BIT_MASK_TXDMA_ERR_FLAG_V1_8822C 0x1f\n#define BIT_TXDMA_ERR_FLAG_V1_8822C(x)                                         \\\n\t(((x) & BIT_MASK_TXDMA_ERR_FLAG_V1_8822C)                              \\\n\t << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C)\n#define BITS_TXDMA_ERR_FLAG_V1_8822C                                           \\\n\t(BIT_MASK_TXDMA_ERR_FLAG_V1_8822C << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C)\n#define BIT_CLEAR_TXDMA_ERR_FLAG_V1_8822C(x)                                   \\\n\t((x) & (~BITS_TXDMA_ERR_FLAG_V1_8822C))\n#define BIT_GET_TXDMA_ERR_FLAG_V1_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C) &                          \\\n\t BIT_MASK_TXDMA_ERR_FLAG_V1_8822C)\n#define BIT_SET_TXDMA_ERR_FLAG_V1_8822C(x, v)                                  \\\n\t(BIT_CLEAR_TXDMA_ERR_FLAG_V1_8822C(x) | BIT_TXDMA_ERR_FLAG_V1_8822C(v))\n\n#define BIT_EPHY_RX50_EN_8822C BIT(11)\n\n#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C 8\n#define BIT_MASK_MSI_TIMEOUT_ID_V1_8822C 0x7\n#define BIT_MSI_TIMEOUT_ID_V1_8822C(x)                                         \\\n\t(((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822C)                              \\\n\t << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C)\n#define BITS_MSI_TIMEOUT_ID_V1_8822C                                           \\\n\t(BIT_MASK_MSI_TIMEOUT_ID_V1_8822C << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C)\n#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822C(x)                                   \\\n\t((x) & (~BITS_MSI_TIMEOUT_ID_V1_8822C))\n#define BIT_GET_MSI_TIMEOUT_ID_V1_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C) &                          \\\n\t BIT_MASK_MSI_TIMEOUT_ID_V1_8822C)\n#define BIT_SET_MSI_TIMEOUT_ID_V1_8822C(x, v)                                  \\\n\t(BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822C(x) | BIT_MSI_TIMEOUT_ID_V1_8822C(v))\n\n#define BIT_RADDR_RD_8822C BIT(7)\n#define BIT_L1OFF_PWR_OFF_EN_8822C BIT(6)\n#define BIT_L0S_LINK_OFF_8822C BIT(4)\n#define BIT_ACT_LINK_OFF_8822C BIT(3)\n#define BIT_EN_SLOW_MAC_TX_8822C BIT(2)\n#define BIT_EN_SLOW_MAC_RX_8822C BIT(1)\n#define BIT_EN_SLOW_MAC_HW_8822C BIT(0)\n\n/* 2 REG_STC_INT_CS_8822C(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */\n#define BIT_STC_INT_EN_8822C BIT(31)\n\n#define BIT_SHIFT_STC_INT_FLAG_8822C 16\n#define BIT_MASK_STC_INT_FLAG_8822C 0xff\n#define BIT_STC_INT_FLAG_8822C(x)                                              \\\n\t(((x) & BIT_MASK_STC_INT_FLAG_8822C) << BIT_SHIFT_STC_INT_FLAG_8822C)\n#define BITS_STC_INT_FLAG_8822C                                                \\\n\t(BIT_MASK_STC_INT_FLAG_8822C << BIT_SHIFT_STC_INT_FLAG_8822C)\n#define BIT_CLEAR_STC_INT_FLAG_8822C(x) ((x) & (~BITS_STC_INT_FLAG_8822C))\n#define BIT_GET_STC_INT_FLAG_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_STC_INT_FLAG_8822C) & BIT_MASK_STC_INT_FLAG_8822C)\n#define BIT_SET_STC_INT_FLAG_8822C(x, v)                                       \\\n\t(BIT_CLEAR_STC_INT_FLAG_8822C(x) | BIT_STC_INT_FLAG_8822C(v))\n\n#define BIT_SHIFT_STC_INT_IDX_8822C 8\n#define BIT_MASK_STC_INT_IDX_8822C 0x7\n#define BIT_STC_INT_IDX_8822C(x)                                               \\\n\t(((x) & BIT_MASK_STC_INT_IDX_8822C) << BIT_SHIFT_STC_INT_IDX_8822C)\n#define BITS_STC_INT_IDX_8822C                                                 \\\n\t(BIT_MASK_STC_INT_IDX_8822C << BIT_SHIFT_STC_INT_IDX_8822C)\n#define BIT_CLEAR_STC_INT_IDX_8822C(x) ((x) & (~BITS_STC_INT_IDX_8822C))\n#define BIT_GET_STC_INT_IDX_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_STC_INT_IDX_8822C) & BIT_MASK_STC_INT_IDX_8822C)\n#define BIT_SET_STC_INT_IDX_8822C(x, v)                                        \\\n\t(BIT_CLEAR_STC_INT_IDX_8822C(x) | BIT_STC_INT_IDX_8822C(v))\n\n#define BIT_SHIFT_STC_INT_REALTIME_CS_8822C 0\n#define BIT_MASK_STC_INT_REALTIME_CS_8822C 0x3f\n#define BIT_STC_INT_REALTIME_CS_8822C(x)                                       \\\n\t(((x) & BIT_MASK_STC_INT_REALTIME_CS_8822C)                            \\\n\t << BIT_SHIFT_STC_INT_REALTIME_CS_8822C)\n#define BITS_STC_INT_REALTIME_CS_8822C                                         \\\n\t(BIT_MASK_STC_INT_REALTIME_CS_8822C                                    \\\n\t << BIT_SHIFT_STC_INT_REALTIME_CS_8822C)\n#define BIT_CLEAR_STC_INT_REALTIME_CS_8822C(x)                                 \\\n\t((x) & (~BITS_STC_INT_REALTIME_CS_8822C))\n#define BIT_GET_STC_INT_REALTIME_CS_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8822C) &                        \\\n\t BIT_MASK_STC_INT_REALTIME_CS_8822C)\n#define BIT_SET_STC_INT_REALTIME_CS_8822C(x, v)                                \\\n\t(BIT_CLEAR_STC_INT_REALTIME_CS_8822C(x) |                              \\\n\t BIT_STC_INT_REALTIME_CS_8822C(v))\n\n#define BIT_STC_INT_GRP_EN_8822C BIT(31)\n\n#define BIT_SHIFT_STC_INT_EXPECT_LS_8822C 8\n#define BIT_MASK_STC_INT_EXPECT_LS_8822C 0x3f\n#define BIT_STC_INT_EXPECT_LS_8822C(x)                                         \\\n\t(((x) & BIT_MASK_STC_INT_EXPECT_LS_8822C)                              \\\n\t << BIT_SHIFT_STC_INT_EXPECT_LS_8822C)\n#define BITS_STC_INT_EXPECT_LS_8822C                                           \\\n\t(BIT_MASK_STC_INT_EXPECT_LS_8822C << BIT_SHIFT_STC_INT_EXPECT_LS_8822C)\n#define BIT_CLEAR_STC_INT_EXPECT_LS_8822C(x)                                   \\\n\t((x) & (~BITS_STC_INT_EXPECT_LS_8822C))\n#define BIT_GET_STC_INT_EXPECT_LS_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8822C) &                          \\\n\t BIT_MASK_STC_INT_EXPECT_LS_8822C)\n#define BIT_SET_STC_INT_EXPECT_LS_8822C(x, v)                                  \\\n\t(BIT_CLEAR_STC_INT_EXPECT_LS_8822C(x) | BIT_STC_INT_EXPECT_LS_8822C(v))\n\n#define BIT_SHIFT_STC_INT_EXPECT_CS_8822C 0\n#define BIT_MASK_STC_INT_EXPECT_CS_8822C 0x3f\n#define BIT_STC_INT_EXPECT_CS_8822C(x)                                         \\\n\t(((x) & BIT_MASK_STC_INT_EXPECT_CS_8822C)                              \\\n\t << BIT_SHIFT_STC_INT_EXPECT_CS_8822C)\n#define BITS_STC_INT_EXPECT_CS_8822C                                           \\\n\t(BIT_MASK_STC_INT_EXPECT_CS_8822C << BIT_SHIFT_STC_INT_EXPECT_CS_8822C)\n#define BIT_CLEAR_STC_INT_EXPECT_CS_8822C(x)                                   \\\n\t((x) & (~BITS_STC_INT_EXPECT_CS_8822C))\n#define BIT_GET_STC_INT_EXPECT_CS_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8822C) &                          \\\n\t BIT_MASK_STC_INT_EXPECT_CS_8822C)\n#define BIT_SET_STC_INT_EXPECT_CS_8822C(x, v)                                  \\\n\t(BIT_CLEAR_STC_INT_EXPECT_CS_8822C(x) | BIT_STC_INT_EXPECT_CS_8822C(v))\n\n/* 2 REG_H2CQ_TXBD_DESA_8822C */\n\n#define BIT_SHIFT_H2CQ_TXBD_DESA_8822C 0\n#define BIT_MASK_H2CQ_TXBD_DESA_8822C 0xffffffffffffffffL\n#define BIT_H2CQ_TXBD_DESA_8822C(x)                                            \\\n\t(((x) & BIT_MASK_H2CQ_TXBD_DESA_8822C)                                 \\\n\t << BIT_SHIFT_H2CQ_TXBD_DESA_8822C)\n#define BITS_H2CQ_TXBD_DESA_8822C                                              \\\n\t(BIT_MASK_H2CQ_TXBD_DESA_8822C << BIT_SHIFT_H2CQ_TXBD_DESA_8822C)\n#define BIT_CLEAR_H2CQ_TXBD_DESA_8822C(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8822C))\n#define BIT_GET_H2CQ_TXBD_DESA_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8822C) &                             \\\n\t BIT_MASK_H2CQ_TXBD_DESA_8822C)\n#define BIT_SET_H2CQ_TXBD_DESA_8822C(x, v)                                     \\\n\t(BIT_CLEAR_H2CQ_TXBD_DESA_8822C(x) | BIT_H2CQ_TXBD_DESA_8822C(v))\n\n/* 2 REG_H2CQ_TXBD_NUM_8822C */\n#define BIT_PCIE_H2CQ_FLAG_8822C BIT(14)\n\n#define BIT_SHIFT_H2CQ_DESC_MODE_8822C 12\n#define BIT_MASK_H2CQ_DESC_MODE_8822C 0x3\n#define BIT_H2CQ_DESC_MODE_8822C(x)                                            \\\n\t(((x) & BIT_MASK_H2CQ_DESC_MODE_8822C)                                 \\\n\t << BIT_SHIFT_H2CQ_DESC_MODE_8822C)\n#define BITS_H2CQ_DESC_MODE_8822C                                              \\\n\t(BIT_MASK_H2CQ_DESC_MODE_8822C << BIT_SHIFT_H2CQ_DESC_MODE_8822C)\n#define BIT_CLEAR_H2CQ_DESC_MODE_8822C(x) ((x) & (~BITS_H2CQ_DESC_MODE_8822C))\n#define BIT_GET_H2CQ_DESC_MODE_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8822C) &                             \\\n\t BIT_MASK_H2CQ_DESC_MODE_8822C)\n#define BIT_SET_H2CQ_DESC_MODE_8822C(x, v)                                     \\\n\t(BIT_CLEAR_H2CQ_DESC_MODE_8822C(x) | BIT_H2CQ_DESC_MODE_8822C(v))\n\n#define BIT_SHIFT_H2CQ_DESC_NUM_8822C 0\n#define BIT_MASK_H2CQ_DESC_NUM_8822C 0xfff\n#define BIT_H2CQ_DESC_NUM_8822C(x)                                             \\\n\t(((x) & BIT_MASK_H2CQ_DESC_NUM_8822C) << BIT_SHIFT_H2CQ_DESC_NUM_8822C)\n#define BITS_H2CQ_DESC_NUM_8822C                                               \\\n\t(BIT_MASK_H2CQ_DESC_NUM_8822C << BIT_SHIFT_H2CQ_DESC_NUM_8822C)\n#define BIT_CLEAR_H2CQ_DESC_NUM_8822C(x) ((x) & (~BITS_H2CQ_DESC_NUM_8822C))\n#define BIT_GET_H2CQ_DESC_NUM_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8822C) & BIT_MASK_H2CQ_DESC_NUM_8822C)\n#define BIT_SET_H2CQ_DESC_NUM_8822C(x, v)                                      \\\n\t(BIT_CLEAR_H2CQ_DESC_NUM_8822C(x) | BIT_H2CQ_DESC_NUM_8822C(v))\n\n/* 2 REG_H2CQ_TXBD_IDX_8822C */\n\n#define BIT_SHIFT_H2CQ_HW_IDX_8822C 16\n#define BIT_MASK_H2CQ_HW_IDX_8822C 0xfff\n#define BIT_H2CQ_HW_IDX_8822C(x)                                               \\\n\t(((x) & BIT_MASK_H2CQ_HW_IDX_8822C) << BIT_SHIFT_H2CQ_HW_IDX_8822C)\n#define BITS_H2CQ_HW_IDX_8822C                                                 \\\n\t(BIT_MASK_H2CQ_HW_IDX_8822C << BIT_SHIFT_H2CQ_HW_IDX_8822C)\n#define BIT_CLEAR_H2CQ_HW_IDX_8822C(x) ((x) & (~BITS_H2CQ_HW_IDX_8822C))\n#define BIT_GET_H2CQ_HW_IDX_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_H2CQ_HW_IDX_8822C) & BIT_MASK_H2CQ_HW_IDX_8822C)\n#define BIT_SET_H2CQ_HW_IDX_8822C(x, v)                                        \\\n\t(BIT_CLEAR_H2CQ_HW_IDX_8822C(x) | BIT_H2CQ_HW_IDX_8822C(v))\n\n#define BIT_SHIFT_H2CQ_HOST_IDX_8822C 0\n#define BIT_MASK_H2CQ_HOST_IDX_8822C 0xfff\n#define BIT_H2CQ_HOST_IDX_8822C(x)                                             \\\n\t(((x) & BIT_MASK_H2CQ_HOST_IDX_8822C) << BIT_SHIFT_H2CQ_HOST_IDX_8822C)\n#define BITS_H2CQ_HOST_IDX_8822C                                               \\\n\t(BIT_MASK_H2CQ_HOST_IDX_8822C << BIT_SHIFT_H2CQ_HOST_IDX_8822C)\n#define BIT_CLEAR_H2CQ_HOST_IDX_8822C(x) ((x) & (~BITS_H2CQ_HOST_IDX_8822C))\n#define BIT_GET_H2CQ_HOST_IDX_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8822C) & BIT_MASK_H2CQ_HOST_IDX_8822C)\n#define BIT_SET_H2CQ_HOST_IDX_8822C(x, v)                                      \\\n\t(BIT_CLEAR_H2CQ_HOST_IDX_8822C(x) | BIT_H2CQ_HOST_IDX_8822C(v))\n\n/* 2 REG_H2CQ_CSR_8822C[31:0] (H2CQ CONTROL AND STATUS) */\n#define BIT_H2CQ_FULL_8822C BIT(31)\n#define BIT_CLR_H2CQ_HOST_IDX_8822C BIT(16)\n#define BIT_CLR_H2CQ_HW_IDX_8822C BIT(8)\n#define BIT_STOP_H2CQ_8822C BIT(0)\n\n/* 2 REG_CHANGE_PCIE_SPEED_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_RXDMA_ERR_CNT_8822C 8\n#define BIT_MASK_RXDMA_ERR_CNT_8822C 0xff\n#define BIT_RXDMA_ERR_CNT_8822C(x)                                             \\\n\t(((x) & BIT_MASK_RXDMA_ERR_CNT_8822C) << BIT_SHIFT_RXDMA_ERR_CNT_8822C)\n#define BITS_RXDMA_ERR_CNT_8822C                                               \\\n\t(BIT_MASK_RXDMA_ERR_CNT_8822C << BIT_SHIFT_RXDMA_ERR_CNT_8822C)\n#define BIT_CLEAR_RXDMA_ERR_CNT_8822C(x) ((x) & (~BITS_RXDMA_ERR_CNT_8822C))\n#define BIT_GET_RXDMA_ERR_CNT_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_RXDMA_ERR_CNT_8822C) & BIT_MASK_RXDMA_ERR_CNT_8822C)\n#define BIT_SET_RXDMA_ERR_CNT_8822C(x, v)                                      \\\n\t(BIT_CLEAR_RXDMA_ERR_CNT_8822C(x) | BIT_RXDMA_ERR_CNT_8822C(v))\n\n#define BIT_TXDMA_ERR_HANDLE_REQ_8822C BIT(7)\n#define BIT_TXDMA_ERROR_PS_8822C BIT(6)\n#define BIT_EN_TXDMA_STUCK_ERR_HANDLE_8822C BIT(5)\n#define BIT_EN_TXDMA_RTN_ERR_HANDLE_8822C BIT(4)\n#define BIT_RXDMA_ERR_HANDLE_REQ_8822C BIT(3)\n#define BIT_RXDMA_ERROR_PS_8822C BIT(2)\n#define BIT_EN_RXDMA_STUCK_ERR_HANDLE_8822C BIT(1)\n#define BIT_EN_RXDMA_RTN_ERR_HANDLE_8822C BIT(0)\n\n/* 2 REG_DEBUG_STATE1_8822C */\n\n#define BIT_SHIFT_DEBUG_STATE1_8822C 0\n#define BIT_MASK_DEBUG_STATE1_8822C 0xffffffffL\n#define BIT_DEBUG_STATE1_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DEBUG_STATE1_8822C) << BIT_SHIFT_DEBUG_STATE1_8822C)\n#define BITS_DEBUG_STATE1_8822C                                                \\\n\t(BIT_MASK_DEBUG_STATE1_8822C << BIT_SHIFT_DEBUG_STATE1_8822C)\n#define BIT_CLEAR_DEBUG_STATE1_8822C(x) ((x) & (~BITS_DEBUG_STATE1_8822C))\n#define BIT_GET_DEBUG_STATE1_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DEBUG_STATE1_8822C) & BIT_MASK_DEBUG_STATE1_8822C)\n#define BIT_SET_DEBUG_STATE1_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DEBUG_STATE1_8822C(x) | BIT_DEBUG_STATE1_8822C(v))\n\n/* 2 REG_DEBUG_STATE2_8822C */\n\n#define BIT_SHIFT_DEBUG_STATE2_8822C 0\n#define BIT_MASK_DEBUG_STATE2_8822C 0xffffffffL\n#define BIT_DEBUG_STATE2_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DEBUG_STATE2_8822C) << BIT_SHIFT_DEBUG_STATE2_8822C)\n#define BITS_DEBUG_STATE2_8822C                                                \\\n\t(BIT_MASK_DEBUG_STATE2_8822C << BIT_SHIFT_DEBUG_STATE2_8822C)\n#define BIT_CLEAR_DEBUG_STATE2_8822C(x) ((x) & (~BITS_DEBUG_STATE2_8822C))\n#define BIT_GET_DEBUG_STATE2_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DEBUG_STATE2_8822C) & BIT_MASK_DEBUG_STATE2_8822C)\n#define BIT_SET_DEBUG_STATE2_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DEBUG_STATE2_8822C(x) | BIT_DEBUG_STATE2_8822C(v))\n\n/* 2 REG_DEBUG_STATE3_8822C */\n\n#define BIT_SHIFT_DEBUG_STATE3_8822C 0\n#define BIT_MASK_DEBUG_STATE3_8822C 0xffffffffL\n#define BIT_DEBUG_STATE3_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DEBUG_STATE3_8822C) << BIT_SHIFT_DEBUG_STATE3_8822C)\n#define BITS_DEBUG_STATE3_8822C                                                \\\n\t(BIT_MASK_DEBUG_STATE3_8822C << BIT_SHIFT_DEBUG_STATE3_8822C)\n#define BIT_CLEAR_DEBUG_STATE3_8822C(x) ((x) & (~BITS_DEBUG_STATE3_8822C))\n#define BIT_GET_DEBUG_STATE3_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DEBUG_STATE3_8822C) & BIT_MASK_DEBUG_STATE3_8822C)\n#define BIT_SET_DEBUG_STATE3_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DEBUG_STATE3_8822C(x) | BIT_DEBUG_STATE3_8822C(v))\n\n/* 2 REG_CHNL_DMA_CFG_V1_8822C */\n#define BIT_TXHCI_EN_V1_8822C BIT(26)\n#define BIT_TXHCI_IDLE_V1_8822C BIT(25)\n#define BIT_DMA_PRI_EN_V1_8822C BIT(24)\n\n/* 2 REG_PCIE_HISR0_V1_8822C */\n#define BIT_PSTIMER_2_8822C BIT(31)\n#define BIT_PSTIMER_1_8822C BIT(30)\n#define BIT_PSTIMER_0_8822C BIT(29)\n#define BIT_GTINT4_8822C BIT(28)\n#define BIT_GTINT3_8822C BIT(27)\n#define BIT_TXBCN0ERR_8822C BIT(26)\n#define BIT_TXBCN0OK_8822C BIT(25)\n#define BIT_TSF_BIT32_TOGGLE_8822C BIT(24)\n#define BIT_TXDMA_START_INT_8822C BIT(23)\n#define BIT_TXDMA_STOP_INT_8822C BIT(22)\n#define BIT_HISR7_IND_8822C BIT(21)\n#define BIT_BCNDMAINT0_8822C BIT(20)\n#define BIT_HISR6_IND_8822C BIT(19)\n#define BIT_HISR5_IND_8822C BIT(18)\n#define BIT_HISR4_IND_8822C BIT(17)\n#define BIT_BCNDERR0_8822C BIT(16)\n#define BIT_HSISR_IND_ON_INT_8822C BIT(15)\n#define BIT_HISR3_IND_8822C BIT(14)\n#define BIT_HISR2_IND_8822C BIT(13)\n#define BIT_HISR1_IND_8822C BIT(11)\n#define BIT_C2HCMD_8822C BIT(10)\n#define BIT_CPWM2_8822C BIT(9)\n#define BIT_CPWM_8822C BIT(8)\n#define BIT_TXDMAOK_CHANNEL15_8822C BIT(7)\n#define BIT_TXDMAOK_CHANNEL14_8822C BIT(6)\n#define BIT_TXDMAOK_CHANNEL3_8822C BIT(5)\n#define BIT_TXDMAOK_CHANNEL2_8822C BIT(4)\n#define BIT_TXDMAOK_CHANNEL1_8822C BIT(3)\n#define BIT_TXDMAOK_CHANNEL0_8822C BIT(2)\n#define BIT_RDU_8822C BIT(1)\n#define BIT_RXOK_8822C BIT(0)\n\n/* 2 REG_PCIE_HISR1_V1_8822C */\n#define BIT_PRE_TX_ERR_INT_8822C BIT(31)\n#define BIT_TXFIFO_TH_INT_8822C BIT(30)\n#define BIT_BTON_STS_UPDATE_INT_8822C BIT(29)\n#define BIT_BCNDMAINT7_8822C BIT(27)\n#define BIT_BCNDMAINT6_8822C BIT(26)\n#define BIT_BCNDMAINT5_8822C BIT(25)\n#define BIT_BCNDMAINT4_8822C BIT(24)\n#define BIT_BCNDMAINT3_8822C BIT(23)\n#define BIT_BCNDMAINT2_8822C BIT(22)\n#define BIT_BCNDMAINT1_8822C BIT(21)\n#define BIT_BCNDERR7_8822C BIT(20)\n#define BIT_BCNDERR6_8822C BIT(19)\n#define BIT_BCNDERR5_8822C BIT(18)\n#define BIT_BCNDERR4_8822C BIT(17)\n#define BIT_BCNDERR3_8822C BIT(16)\n#define BIT_BCNDERR2_8822C BIT(15)\n#define BIT_BCNDERR1_8822C BIT(14)\n#define BIT_ATIMEND_8822C BIT(12)\n#define BIT_TXERR_INT_8822C BIT(11)\n#define BIT_RXERR_INT_8822C BIT(10)\n#define BIT_TXFOVW_8822C BIT(9)\n#define BIT_FOVW_8822C BIT(8)\n#define BIT_CPU_MGQ_EARLY_INT_8822C BIT(6)\n#define BIT_CPU_MGQ_TXDONE_8822C BIT(5)\n#define BIT_PSTIMER_5_8822C BIT(4)\n#define BIT_PSTIMER_4_8822C BIT(3)\n#define BIT_PSTIMER_3_8822C BIT(2)\n#define BIT_CPUMGQ_TX_TIMER_8822C BIT(1)\n#define BIT_BB_STOPRX_INT_8822C BIT(0)\n\n/* 2 REG_PCIE_HISR2_V1_8822C */\n#define BIT_BCNDMAINT_P4_8822C BIT(31)\n#define BIT_BCNDMAINT_P3_8822C BIT(30)\n#define BIT_BCNDMAINT_P2_8822C BIT(29)\n#define BIT_BCNDMAINT_P1_8822C BIT(28)\n#define BIT_SCH_PHY_TXOP_SIFS_INT_8822C BIT(23)\n#define BIT_ATIMEND7_8822C BIT(22)\n#define BIT_ATIMEND6_8822C BIT(21)\n#define BIT_ATIMEND5_8822C BIT(20)\n#define BIT_ATIMEND4_8822C BIT(19)\n#define BIT_ATIMEND3_8822C BIT(18)\n#define BIT_ATIMEND2_8822C BIT(17)\n#define BIT_ATIMEND1_8822C BIT(16)\n#define BIT_TXBCN7OK_8822C BIT(14)\n#define BIT_TXBCN6OK_8822C BIT(13)\n#define BIT_TXBCN5OK_8822C BIT(12)\n#define BIT_TXBCN4OK_8822C BIT(11)\n#define BIT_TXBCN3OK_8822C BIT(10)\n#define BIT_TXBCN2OK_8822C BIT(9)\n#define BIT_TXBCN1OK_8822C BIT(8)\n#define BIT_TXBCN7ERR_8822C BIT(6)\n#define BIT_TXBCN6ERR_8822C BIT(5)\n#define BIT_TXBCN5ERR_8822C BIT(4)\n#define BIT_TXBCN4ERR_8822C BIT(3)\n#define BIT_TXBCN3ERR_8822C BIT(2)\n#define BIT_TXBCN2ERR_8822C BIT(1)\n#define BIT_TXBCN1ERR_8822C BIT(0)\n\n/* 2 REG_PCIE_HISR3_V1_8822C */\n#define BIT_GTINT12_8822C BIT(24)\n#define BIT_GTINT11_8822C BIT(23)\n#define BIT_GTINT10_8822C BIT(22)\n#define BIT_GTINT9_8822C BIT(21)\n#define BIT_RX_DESC_BUF_FULL_8822C BIT(20)\n#define BIT_CPHY_LDO_OCP_DET_INT_8822C BIT(19)\n#define BIT_WDT_PLATFORM_INT_8822C BIT(18)\n#define BIT_WDT_CPU_INT_8822C BIT(17)\n#define BIT_SETH2CDOK_8822C BIT(16)\n#define BIT_H2C_CMD_FULL_8822C BIT(15)\n#define BIT_PKT_TRANS_ERR_8822C BIT(14)\n#define BIT_TXSHORTCUT_TXDESUPDATEOK_8822C BIT(13)\n#define BIT_TXSHORTCUT_BKUPDATEOK_8822C BIT(12)\n#define BIT_TXSHORTCUT_BEUPDATEOK_8822C BIT(11)\n#define BIT_TXSHORTCUT_VIUPDATEOK_8822C BIT(10)\n#define BIT_TXSHORTCUT_VOUPDATEOK_8822C BIT(9)\n#define BIT_SEARCH_FAIL_8822C BIT(8)\n#define BIT_PWR_INT_127TO96_8822C BIT(7)\n#define BIT_PWR_INT_95TO64_8822C BIT(6)\n#define BIT_PWR_INT_63TO32_8822C BIT(5)\n#define BIT_PWR_INT_31TO0_8822C BIT(4)\n#define BIT_RX_DMA_STUCK_8822C BIT(3)\n#define BIT_TX_DMA_STUCK_8822C BIT(2)\n#define BIT_DDMA0_LP_INT_8822C BIT(1)\n#define BIT_DDMA0_HP_INT_8822C BIT(0)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_Q0_INFO_8822C */\n\n#define BIT_SHIFT_QUEUEMACID_Q0_V1_8822C 25\n#define BIT_MASK_QUEUEMACID_Q0_V1_8822C 0x7f\n#define BIT_QUEUEMACID_Q0_V1_8822C(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q0_V1_8822C)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q0_V1_8822C)\n#define BITS_QUEUEMACID_Q0_V1_8822C                                            \\\n\t(BIT_MASK_QUEUEMACID_Q0_V1_8822C << BIT_SHIFT_QUEUEMACID_Q0_V1_8822C)\n#define BIT_CLEAR_QUEUEMACID_Q0_V1_8822C(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q0_V1_8822C))\n#define BIT_GET_QUEUEMACID_Q0_V1_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8822C) &                           \\\n\t BIT_MASK_QUEUEMACID_Q0_V1_8822C)\n#define BIT_SET_QUEUEMACID_Q0_V1_8822C(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q0_V1_8822C(x) | BIT_QUEUEMACID_Q0_V1_8822C(v))\n\n#define BIT_SHIFT_QUEUEAC_Q0_V1_8822C 23\n#define BIT_MASK_QUEUEAC_Q0_V1_8822C 0x3\n#define BIT_QUEUEAC_Q0_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q0_V1_8822C) << BIT_SHIFT_QUEUEAC_Q0_V1_8822C)\n#define BITS_QUEUEAC_Q0_V1_8822C                                               \\\n\t(BIT_MASK_QUEUEAC_Q0_V1_8822C << BIT_SHIFT_QUEUEAC_Q0_V1_8822C)\n#define BIT_CLEAR_QUEUEAC_Q0_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8822C))\n#define BIT_GET_QUEUEAC_Q0_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8822C) & BIT_MASK_QUEUEAC_Q0_V1_8822C)\n#define BIT_SET_QUEUEAC_Q0_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q0_V1_8822C(x) | BIT_QUEUEAC_Q0_V1_8822C(v))\n\n#define BIT_TIDEMPTY_Q0_V1_8822C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q0_V2_8822C 11\n#define BIT_MASK_TAIL_PKT_Q0_V2_8822C 0x7ff\n#define BIT_TAIL_PKT_Q0_V2_8822C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q0_V2_8822C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q0_V2_8822C)\n#define BITS_TAIL_PKT_Q0_V2_8822C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q0_V2_8822C << BIT_SHIFT_TAIL_PKT_Q0_V2_8822C)\n#define BIT_CLEAR_TAIL_PKT_Q0_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8822C))\n#define BIT_GET_TAIL_PKT_Q0_V2_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8822C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q0_V2_8822C)\n#define BIT_SET_TAIL_PKT_Q0_V2_8822C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q0_V2_8822C(x) | BIT_TAIL_PKT_Q0_V2_8822C(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q0_V1_8822C 0\n#define BIT_MASK_HEAD_PKT_Q0_V1_8822C 0x7ff\n#define BIT_HEAD_PKT_Q0_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q0_V1_8822C)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q0_V1_8822C)\n#define BITS_HEAD_PKT_Q0_V1_8822C                                              \\\n\t(BIT_MASK_HEAD_PKT_Q0_V1_8822C << BIT_SHIFT_HEAD_PKT_Q0_V1_8822C)\n#define BIT_CLEAR_HEAD_PKT_Q0_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8822C))\n#define BIT_GET_HEAD_PKT_Q0_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8822C) &                             \\\n\t BIT_MASK_HEAD_PKT_Q0_V1_8822C)\n#define BIT_SET_HEAD_PKT_Q0_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q0_V1_8822C(x) | BIT_HEAD_PKT_Q0_V1_8822C(v))\n\n/* 2 REG_Q1_INFO_8822C */\n\n#define BIT_SHIFT_QUEUEMACID_Q1_V1_8822C 25\n#define BIT_MASK_QUEUEMACID_Q1_V1_8822C 0x7f\n#define BIT_QUEUEMACID_Q1_V1_8822C(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q1_V1_8822C)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q1_V1_8822C)\n#define BITS_QUEUEMACID_Q1_V1_8822C                                            \\\n\t(BIT_MASK_QUEUEMACID_Q1_V1_8822C << BIT_SHIFT_QUEUEMACID_Q1_V1_8822C)\n#define BIT_CLEAR_QUEUEMACID_Q1_V1_8822C(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q1_V1_8822C))\n#define BIT_GET_QUEUEMACID_Q1_V1_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8822C) &                           \\\n\t BIT_MASK_QUEUEMACID_Q1_V1_8822C)\n#define BIT_SET_QUEUEMACID_Q1_V1_8822C(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q1_V1_8822C(x) | BIT_QUEUEMACID_Q1_V1_8822C(v))\n\n#define BIT_SHIFT_QUEUEAC_Q1_V1_8822C 23\n#define BIT_MASK_QUEUEAC_Q1_V1_8822C 0x3\n#define BIT_QUEUEAC_Q1_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q1_V1_8822C) << BIT_SHIFT_QUEUEAC_Q1_V1_8822C)\n#define BITS_QUEUEAC_Q1_V1_8822C                                               \\\n\t(BIT_MASK_QUEUEAC_Q1_V1_8822C << BIT_SHIFT_QUEUEAC_Q1_V1_8822C)\n#define BIT_CLEAR_QUEUEAC_Q1_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8822C))\n#define BIT_GET_QUEUEAC_Q1_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8822C) & BIT_MASK_QUEUEAC_Q1_V1_8822C)\n#define BIT_SET_QUEUEAC_Q1_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q1_V1_8822C(x) | BIT_QUEUEAC_Q1_V1_8822C(v))\n\n#define BIT_TIDEMPTY_Q1_V1_8822C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q1_V2_8822C 11\n#define BIT_MASK_TAIL_PKT_Q1_V2_8822C 0x7ff\n#define BIT_TAIL_PKT_Q1_V2_8822C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q1_V2_8822C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q1_V2_8822C)\n#define BITS_TAIL_PKT_Q1_V2_8822C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q1_V2_8822C << BIT_SHIFT_TAIL_PKT_Q1_V2_8822C)\n#define BIT_CLEAR_TAIL_PKT_Q1_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8822C))\n#define BIT_GET_TAIL_PKT_Q1_V2_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8822C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q1_V2_8822C)\n#define BIT_SET_TAIL_PKT_Q1_V2_8822C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q1_V2_8822C(x) | BIT_TAIL_PKT_Q1_V2_8822C(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q1_V1_8822C 0\n#define BIT_MASK_HEAD_PKT_Q1_V1_8822C 0x7ff\n#define BIT_HEAD_PKT_Q1_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q1_V1_8822C)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q1_V1_8822C)\n#define BITS_HEAD_PKT_Q1_V1_8822C                                              \\\n\t(BIT_MASK_HEAD_PKT_Q1_V1_8822C << BIT_SHIFT_HEAD_PKT_Q1_V1_8822C)\n#define BIT_CLEAR_HEAD_PKT_Q1_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8822C))\n#define BIT_GET_HEAD_PKT_Q1_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8822C) &                             \\\n\t BIT_MASK_HEAD_PKT_Q1_V1_8822C)\n#define BIT_SET_HEAD_PKT_Q1_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q1_V1_8822C(x) | BIT_HEAD_PKT_Q1_V1_8822C(v))\n\n/* 2 REG_Q2_INFO_8822C */\n\n#define BIT_SHIFT_QUEUEMACID_Q2_V1_8822C 25\n#define BIT_MASK_QUEUEMACID_Q2_V1_8822C 0x7f\n#define BIT_QUEUEMACID_Q2_V1_8822C(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q2_V1_8822C)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q2_V1_8822C)\n#define BITS_QUEUEMACID_Q2_V1_8822C                                            \\\n\t(BIT_MASK_QUEUEMACID_Q2_V1_8822C << BIT_SHIFT_QUEUEMACID_Q2_V1_8822C)\n#define BIT_CLEAR_QUEUEMACID_Q2_V1_8822C(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q2_V1_8822C))\n#define BIT_GET_QUEUEMACID_Q2_V1_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8822C) &                           \\\n\t BIT_MASK_QUEUEMACID_Q2_V1_8822C)\n#define BIT_SET_QUEUEMACID_Q2_V1_8822C(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q2_V1_8822C(x) | BIT_QUEUEMACID_Q2_V1_8822C(v))\n\n#define BIT_SHIFT_QUEUEAC_Q2_V1_8822C 23\n#define BIT_MASK_QUEUEAC_Q2_V1_8822C 0x3\n#define BIT_QUEUEAC_Q2_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q2_V1_8822C) << BIT_SHIFT_QUEUEAC_Q2_V1_8822C)\n#define BITS_QUEUEAC_Q2_V1_8822C                                               \\\n\t(BIT_MASK_QUEUEAC_Q2_V1_8822C << BIT_SHIFT_QUEUEAC_Q2_V1_8822C)\n#define BIT_CLEAR_QUEUEAC_Q2_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8822C))\n#define BIT_GET_QUEUEAC_Q2_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8822C) & BIT_MASK_QUEUEAC_Q2_V1_8822C)\n#define BIT_SET_QUEUEAC_Q2_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q2_V1_8822C(x) | BIT_QUEUEAC_Q2_V1_8822C(v))\n\n#define BIT_TIDEMPTY_Q2_V1_8822C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q2_V2_8822C 11\n#define BIT_MASK_TAIL_PKT_Q2_V2_8822C 0x7ff\n#define BIT_TAIL_PKT_Q2_V2_8822C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q2_V2_8822C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q2_V2_8822C)\n#define BITS_TAIL_PKT_Q2_V2_8822C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q2_V2_8822C << BIT_SHIFT_TAIL_PKT_Q2_V2_8822C)\n#define BIT_CLEAR_TAIL_PKT_Q2_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8822C))\n#define BIT_GET_TAIL_PKT_Q2_V2_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8822C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q2_V2_8822C)\n#define BIT_SET_TAIL_PKT_Q2_V2_8822C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q2_V2_8822C(x) | BIT_TAIL_PKT_Q2_V2_8822C(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q2_V1_8822C 0\n#define BIT_MASK_HEAD_PKT_Q2_V1_8822C 0x7ff\n#define BIT_HEAD_PKT_Q2_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q2_V1_8822C)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q2_V1_8822C)\n#define BITS_HEAD_PKT_Q2_V1_8822C                                              \\\n\t(BIT_MASK_HEAD_PKT_Q2_V1_8822C << BIT_SHIFT_HEAD_PKT_Q2_V1_8822C)\n#define BIT_CLEAR_HEAD_PKT_Q2_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8822C))\n#define BIT_GET_HEAD_PKT_Q2_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8822C) &                             \\\n\t BIT_MASK_HEAD_PKT_Q2_V1_8822C)\n#define BIT_SET_HEAD_PKT_Q2_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q2_V1_8822C(x) | BIT_HEAD_PKT_Q2_V1_8822C(v))\n\n/* 2 REG_Q3_INFO_8822C */\n\n#define BIT_SHIFT_QUEUEMACID_Q3_V1_8822C 25\n#define BIT_MASK_QUEUEMACID_Q3_V1_8822C 0x7f\n#define BIT_QUEUEMACID_Q3_V1_8822C(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q3_V1_8822C)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q3_V1_8822C)\n#define BITS_QUEUEMACID_Q3_V1_8822C                                            \\\n\t(BIT_MASK_QUEUEMACID_Q3_V1_8822C << BIT_SHIFT_QUEUEMACID_Q3_V1_8822C)\n#define BIT_CLEAR_QUEUEMACID_Q3_V1_8822C(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q3_V1_8822C))\n#define BIT_GET_QUEUEMACID_Q3_V1_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8822C) &                           \\\n\t BIT_MASK_QUEUEMACID_Q3_V1_8822C)\n#define BIT_SET_QUEUEMACID_Q3_V1_8822C(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q3_V1_8822C(x) | BIT_QUEUEMACID_Q3_V1_8822C(v))\n\n#define BIT_SHIFT_QUEUEAC_Q3_V1_8822C 23\n#define BIT_MASK_QUEUEAC_Q3_V1_8822C 0x3\n#define BIT_QUEUEAC_Q3_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q3_V1_8822C) << BIT_SHIFT_QUEUEAC_Q3_V1_8822C)\n#define BITS_QUEUEAC_Q3_V1_8822C                                               \\\n\t(BIT_MASK_QUEUEAC_Q3_V1_8822C << BIT_SHIFT_QUEUEAC_Q3_V1_8822C)\n#define BIT_CLEAR_QUEUEAC_Q3_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8822C))\n#define BIT_GET_QUEUEAC_Q3_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8822C) & BIT_MASK_QUEUEAC_Q3_V1_8822C)\n#define BIT_SET_QUEUEAC_Q3_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q3_V1_8822C(x) | BIT_QUEUEAC_Q3_V1_8822C(v))\n\n#define BIT_TIDEMPTY_Q3_V1_8822C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q3_V2_8822C 11\n#define BIT_MASK_TAIL_PKT_Q3_V2_8822C 0x7ff\n#define BIT_TAIL_PKT_Q3_V2_8822C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q3_V2_8822C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q3_V2_8822C)\n#define BITS_TAIL_PKT_Q3_V2_8822C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q3_V2_8822C << BIT_SHIFT_TAIL_PKT_Q3_V2_8822C)\n#define BIT_CLEAR_TAIL_PKT_Q3_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8822C))\n#define BIT_GET_TAIL_PKT_Q3_V2_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8822C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q3_V2_8822C)\n#define BIT_SET_TAIL_PKT_Q3_V2_8822C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q3_V2_8822C(x) | BIT_TAIL_PKT_Q3_V2_8822C(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q3_V1_8822C 0\n#define BIT_MASK_HEAD_PKT_Q3_V1_8822C 0x7ff\n#define BIT_HEAD_PKT_Q3_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q3_V1_8822C)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q3_V1_8822C)\n#define BITS_HEAD_PKT_Q3_V1_8822C                                              \\\n\t(BIT_MASK_HEAD_PKT_Q3_V1_8822C << BIT_SHIFT_HEAD_PKT_Q3_V1_8822C)\n#define BIT_CLEAR_HEAD_PKT_Q3_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8822C))\n#define BIT_GET_HEAD_PKT_Q3_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8822C) &                             \\\n\t BIT_MASK_HEAD_PKT_Q3_V1_8822C)\n#define BIT_SET_HEAD_PKT_Q3_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q3_V1_8822C(x) | BIT_HEAD_PKT_Q3_V1_8822C(v))\n\n/* 2 REG_MGQ_INFO_8822C */\n\n#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C 25\n#define BIT_MASK_QUEUEMACID_MGQ_V1_8822C 0x7f\n#define BIT_QUEUEMACID_MGQ_V1_8822C(x)                                         \\\n\t(((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8822C)                              \\\n\t << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C)\n#define BITS_QUEUEMACID_MGQ_V1_8822C                                           \\\n\t(BIT_MASK_QUEUEMACID_MGQ_V1_8822C << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C)\n#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8822C(x)                                   \\\n\t((x) & (~BITS_QUEUEMACID_MGQ_V1_8822C))\n#define BIT_GET_QUEUEMACID_MGQ_V1_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C) &                          \\\n\t BIT_MASK_QUEUEMACID_MGQ_V1_8822C)\n#define BIT_SET_QUEUEMACID_MGQ_V1_8822C(x, v)                                  \\\n\t(BIT_CLEAR_QUEUEMACID_MGQ_V1_8822C(x) | BIT_QUEUEMACID_MGQ_V1_8822C(v))\n\n#define BIT_SHIFT_QUEUEAC_MGQ_V1_8822C 23\n#define BIT_MASK_QUEUEAC_MGQ_V1_8822C 0x3\n#define BIT_QUEUEAC_MGQ_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_QUEUEAC_MGQ_V1_8822C)                                 \\\n\t << BIT_SHIFT_QUEUEAC_MGQ_V1_8822C)\n#define BITS_QUEUEAC_MGQ_V1_8822C                                              \\\n\t(BIT_MASK_QUEUEAC_MGQ_V1_8822C << BIT_SHIFT_QUEUEAC_MGQ_V1_8822C)\n#define BIT_CLEAR_QUEUEAC_MGQ_V1_8822C(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8822C))\n#define BIT_GET_QUEUEAC_MGQ_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8822C) &                             \\\n\t BIT_MASK_QUEUEAC_MGQ_V1_8822C)\n#define BIT_SET_QUEUEAC_MGQ_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_QUEUEAC_MGQ_V1_8822C(x) | BIT_QUEUEAC_MGQ_V1_8822C(v))\n\n#define BIT_TIDEMPTY_MGQ_V1_8822C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C 11\n#define BIT_MASK_TAIL_PKT_MGQ_V2_8822C 0x7ff\n#define BIT_TAIL_PKT_MGQ_V2_8822C(x)                                           \\\n\t(((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8822C)                                \\\n\t << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C)\n#define BITS_TAIL_PKT_MGQ_V2_8822C                                             \\\n\t(BIT_MASK_TAIL_PKT_MGQ_V2_8822C << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C)\n#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8822C))\n#define BIT_GET_TAIL_PKT_MGQ_V2_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C) &                            \\\n\t BIT_MASK_TAIL_PKT_MGQ_V2_8822C)\n#define BIT_SET_TAIL_PKT_MGQ_V2_8822C(x, v)                                    \\\n\t(BIT_CLEAR_TAIL_PKT_MGQ_V2_8822C(x) | BIT_TAIL_PKT_MGQ_V2_8822C(v))\n\n#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C 0\n#define BIT_MASK_HEAD_PKT_MGQ_V1_8822C 0x7ff\n#define BIT_HEAD_PKT_MGQ_V1_8822C(x)                                           \\\n\t(((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8822C)                                \\\n\t << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C)\n#define BITS_HEAD_PKT_MGQ_V1_8822C                                             \\\n\t(BIT_MASK_HEAD_PKT_MGQ_V1_8822C << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C)\n#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8822C))\n#define BIT_GET_HEAD_PKT_MGQ_V1_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C) &                            \\\n\t BIT_MASK_HEAD_PKT_MGQ_V1_8822C)\n#define BIT_SET_HEAD_PKT_MGQ_V1_8822C(x, v)                                    \\\n\t(BIT_CLEAR_HEAD_PKT_MGQ_V1_8822C(x) | BIT_HEAD_PKT_MGQ_V1_8822C(v))\n\n/* 2 REG_HIQ_INFO_8822C */\n\n#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C 25\n#define BIT_MASK_QUEUEMACID_HIQ_V1_8822C 0x7f\n#define BIT_QUEUEMACID_HIQ_V1_8822C(x)                                         \\\n\t(((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8822C)                              \\\n\t << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C)\n#define BITS_QUEUEMACID_HIQ_V1_8822C                                           \\\n\t(BIT_MASK_QUEUEMACID_HIQ_V1_8822C << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C)\n#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8822C(x)                                   \\\n\t((x) & (~BITS_QUEUEMACID_HIQ_V1_8822C))\n#define BIT_GET_QUEUEMACID_HIQ_V1_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C) &                          \\\n\t BIT_MASK_QUEUEMACID_HIQ_V1_8822C)\n#define BIT_SET_QUEUEMACID_HIQ_V1_8822C(x, v)                                  \\\n\t(BIT_CLEAR_QUEUEMACID_HIQ_V1_8822C(x) | BIT_QUEUEMACID_HIQ_V1_8822C(v))\n\n#define BIT_SHIFT_QUEUEAC_HIQ_V1_8822C 23\n#define BIT_MASK_QUEUEAC_HIQ_V1_8822C 0x3\n#define BIT_QUEUEAC_HIQ_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_QUEUEAC_HIQ_V1_8822C)                                 \\\n\t << BIT_SHIFT_QUEUEAC_HIQ_V1_8822C)\n#define BITS_QUEUEAC_HIQ_V1_8822C                                              \\\n\t(BIT_MASK_QUEUEAC_HIQ_V1_8822C << BIT_SHIFT_QUEUEAC_HIQ_V1_8822C)\n#define BIT_CLEAR_QUEUEAC_HIQ_V1_8822C(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8822C))\n#define BIT_GET_QUEUEAC_HIQ_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8822C) &                             \\\n\t BIT_MASK_QUEUEAC_HIQ_V1_8822C)\n#define BIT_SET_QUEUEAC_HIQ_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_QUEUEAC_HIQ_V1_8822C(x) | BIT_QUEUEAC_HIQ_V1_8822C(v))\n\n#define BIT_TIDEMPTY_HIQ_V1_8822C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C 11\n#define BIT_MASK_TAIL_PKT_HIQ_V2_8822C 0x7ff\n#define BIT_TAIL_PKT_HIQ_V2_8822C(x)                                           \\\n\t(((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8822C)                                \\\n\t << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C)\n#define BITS_TAIL_PKT_HIQ_V2_8822C                                             \\\n\t(BIT_MASK_TAIL_PKT_HIQ_V2_8822C << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C)\n#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8822C))\n#define BIT_GET_TAIL_PKT_HIQ_V2_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C) &                            \\\n\t BIT_MASK_TAIL_PKT_HIQ_V2_8822C)\n#define BIT_SET_TAIL_PKT_HIQ_V2_8822C(x, v)                                    \\\n\t(BIT_CLEAR_TAIL_PKT_HIQ_V2_8822C(x) | BIT_TAIL_PKT_HIQ_V2_8822C(v))\n\n#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C 0\n#define BIT_MASK_HEAD_PKT_HIQ_V1_8822C 0x7ff\n#define BIT_HEAD_PKT_HIQ_V1_8822C(x)                                           \\\n\t(((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8822C)                                \\\n\t << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C)\n#define BITS_HEAD_PKT_HIQ_V1_8822C                                             \\\n\t(BIT_MASK_HEAD_PKT_HIQ_V1_8822C << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C)\n#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8822C))\n#define BIT_GET_HEAD_PKT_HIQ_V1_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C) &                            \\\n\t BIT_MASK_HEAD_PKT_HIQ_V1_8822C)\n#define BIT_SET_HEAD_PKT_HIQ_V1_8822C(x, v)                                    \\\n\t(BIT_CLEAR_HEAD_PKT_HIQ_V1_8822C(x) | BIT_HEAD_PKT_HIQ_V1_8822C(v))\n\n/* 2 REG_BCNQ_INFO_8822C */\n\n#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C 0\n#define BIT_MASK_BCNQ_HEAD_PG_V1_8822C 0xfff\n#define BIT_BCNQ_HEAD_PG_V1_8822C(x)                                           \\\n\t(((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8822C)                                \\\n\t << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C)\n#define BITS_BCNQ_HEAD_PG_V1_8822C                                             \\\n\t(BIT_MASK_BCNQ_HEAD_PG_V1_8822C << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C)\n#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8822C(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8822C))\n#define BIT_GET_BCNQ_HEAD_PG_V1_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C) &                            \\\n\t BIT_MASK_BCNQ_HEAD_PG_V1_8822C)\n#define BIT_SET_BCNQ_HEAD_PG_V1_8822C(x, v)                                    \\\n\t(BIT_CLEAR_BCNQ_HEAD_PG_V1_8822C(x) | BIT_BCNQ_HEAD_PG_V1_8822C(v))\n\n/* 2 REG_TXPKT_EMPTY_8822C */\n#define BIT_BCNQ_EMPTY_8822C BIT(11)\n#define BIT_HQQ_EMPTY_8822C BIT(10)\n#define BIT_MQQ_EMPTY_8822C BIT(9)\n#define BIT_MGQ_CPU_EMPTY_8822C BIT(8)\n#define BIT_AC7Q_EMPTY_8822C BIT(7)\n#define BIT_AC6Q_EMPTY_8822C BIT(6)\n#define BIT_AC5Q_EMPTY_8822C BIT(5)\n#define BIT_AC4Q_EMPTY_8822C BIT(4)\n#define BIT_AC3Q_EMPTY_8822C BIT(3)\n#define BIT_AC2Q_EMPTY_8822C BIT(2)\n#define BIT_AC1Q_EMPTY_8822C BIT(1)\n#define BIT_AC0Q_EMPTY_8822C BIT(0)\n\n/* 2 REG_CPU_MGQ_INFO_8822C */\n#define BIT_BCN1_POLL_8822C BIT(30)\n#define BIT_CPUMGT_POLL_8822C BIT(29)\n#define BIT_BCN_POLL_8822C BIT(28)\n#define BIT_CPUMGQ_FW_NUM_V1_8822C BIT(12)\n\n#define BIT_SHIFT_FW_FREE_TAIL_V1_8822C 0\n#define BIT_MASK_FW_FREE_TAIL_V1_8822C 0xfff\n#define BIT_FW_FREE_TAIL_V1_8822C(x)                                           \\\n\t(((x) & BIT_MASK_FW_FREE_TAIL_V1_8822C)                                \\\n\t << BIT_SHIFT_FW_FREE_TAIL_V1_8822C)\n#define BITS_FW_FREE_TAIL_V1_8822C                                             \\\n\t(BIT_MASK_FW_FREE_TAIL_V1_8822C << BIT_SHIFT_FW_FREE_TAIL_V1_8822C)\n#define BIT_CLEAR_FW_FREE_TAIL_V1_8822C(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8822C))\n#define BIT_GET_FW_FREE_TAIL_V1_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8822C) &                            \\\n\t BIT_MASK_FW_FREE_TAIL_V1_8822C)\n#define BIT_SET_FW_FREE_TAIL_V1_8822C(x, v)                                    \\\n\t(BIT_CLEAR_FW_FREE_TAIL_V1_8822C(x) | BIT_FW_FREE_TAIL_V1_8822C(v))\n\n/* 2 REG_FWHW_TXQ_CTRL_8822C */\n#define BIT_RTS_LIMIT_IN_OFDM_8822C BIT(23)\n#define BIT_EN_BCNQ_DL_8822C BIT(22)\n#define BIT_EN_RD_RESP_NAV_BK_8822C BIT(21)\n#define BIT_EN_WR_FREE_TAIL_8822C BIT(20)\n#define BIT_NOTXRPT_USERATE_EN_8822C BIT(19)\n#define BIT_DIS_TXFAIL_RPT_8822C BIT(18)\n#define BIT_FTM_TIMEOUT_BYPASS_8822C BIT(16)\n\n#define BIT_SHIFT_EN_QUEUE_RPT_8822C 8\n#define BIT_MASK_EN_QUEUE_RPT_8822C 0xff\n#define BIT_EN_QUEUE_RPT_8822C(x)                                              \\\n\t(((x) & BIT_MASK_EN_QUEUE_RPT_8822C) << BIT_SHIFT_EN_QUEUE_RPT_8822C)\n#define BITS_EN_QUEUE_RPT_8822C                                                \\\n\t(BIT_MASK_EN_QUEUE_RPT_8822C << BIT_SHIFT_EN_QUEUE_RPT_8822C)\n#define BIT_CLEAR_EN_QUEUE_RPT_8822C(x) ((x) & (~BITS_EN_QUEUE_RPT_8822C))\n#define BIT_GET_EN_QUEUE_RPT_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_EN_QUEUE_RPT_8822C) & BIT_MASK_EN_QUEUE_RPT_8822C)\n#define BIT_SET_EN_QUEUE_RPT_8822C(x, v)                                       \\\n\t(BIT_CLEAR_EN_QUEUE_RPT_8822C(x) | BIT_EN_QUEUE_RPT_8822C(v))\n\n#define BIT_EN_RTY_BK_8822C BIT(7)\n#define BIT_EN_USE_INI_RAT_8822C BIT(6)\n#define BIT_EN_RTS_NAV_BK_8822C BIT(5)\n#define BIT_DIS_SSN_CHECK_8822C BIT(4)\n#define BIT_MACID_MATCH_RTS_8822C BIT(3)\n#define BIT_EN_BCN_TRXRPT_V1_8822C BIT(2)\n#define BIT_R_EN_FTMRPT_V1_8822C BIT(1)\n#define BIT_R_BMC_NAV_PROTECT_8822C BIT(0)\n\n/* 2 REG_DATAFB_SEL_8822C */\n#define BIT_BROADCAST_RTY_EN_8822C BIT(3)\n#define BIT_EN_RTY_BK_COD_8822C BIT(2)\n\n#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C 0\n#define BIT_MASK__R_DATA_FALLBACK_SEL_8822C 0x3\n#define BIT__R_DATA_FALLBACK_SEL_8822C(x)                                      \\\n\t(((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8822C)                           \\\n\t << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C)\n#define BITS__R_DATA_FALLBACK_SEL_8822C                                        \\\n\t(BIT_MASK__R_DATA_FALLBACK_SEL_8822C                                   \\\n\t << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C)\n#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8822C(x)                                \\\n\t((x) & (~BITS__R_DATA_FALLBACK_SEL_8822C))\n#define BIT_GET__R_DATA_FALLBACK_SEL_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C) &                       \\\n\t BIT_MASK__R_DATA_FALLBACK_SEL_8822C)\n#define BIT_SET__R_DATA_FALLBACK_SEL_8822C(x, v)                               \\\n\t(BIT_CLEAR__R_DATA_FALLBACK_SEL_8822C(x) |                             \\\n\t BIT__R_DATA_FALLBACK_SEL_8822C(v))\n\n/* 2 REG_BCNQ_BDNY_V1_8822C */\n\n#define BIT_SHIFT_BCNQ_PGBNDY_V1_8822C 0\n#define BIT_MASK_BCNQ_PGBNDY_V1_8822C 0xfff\n#define BIT_BCNQ_PGBNDY_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_BCNQ_PGBNDY_V1_8822C)                                 \\\n\t << BIT_SHIFT_BCNQ_PGBNDY_V1_8822C)\n#define BITS_BCNQ_PGBNDY_V1_8822C                                              \\\n\t(BIT_MASK_BCNQ_PGBNDY_V1_8822C << BIT_SHIFT_BCNQ_PGBNDY_V1_8822C)\n#define BIT_CLEAR_BCNQ_PGBNDY_V1_8822C(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8822C))\n#define BIT_GET_BCNQ_PGBNDY_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8822C) &                             \\\n\t BIT_MASK_BCNQ_PGBNDY_V1_8822C)\n#define BIT_SET_BCNQ_PGBNDY_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_BCNQ_PGBNDY_V1_8822C(x) | BIT_BCNQ_PGBNDY_V1_8822C(v))\n\n/* 2 REG_LIFETIME_EN_8822C */\n#define BIT_BT_INT_CPU_8822C BIT(7)\n#define BIT_BT_INT_PTA_8822C BIT(6)\n#define BIT_EN_CTRL_RTYBIT_8822C BIT(4)\n#define BIT_LIFETIME_BK_EN_8822C BIT(3)\n#define BIT_LIFETIME_BE_EN_8822C BIT(2)\n#define BIT_LIFETIME_VI_EN_8822C BIT(1)\n#define BIT_LIFETIME_VO_EN_8822C BIT(0)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_SPEC_SIFS_8822C */\n\n#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C 8\n#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C 0xff\n#define BIT_SPEC_SIFS_OFDM_PTCL_8822C(x)                                       \\\n\t(((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C)                            \\\n\t << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C)\n#define BITS_SPEC_SIFS_OFDM_PTCL_8822C                                         \\\n\t(BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C                                    \\\n\t << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C)\n#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822C(x)                                 \\\n\t((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8822C))\n#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C) &                        \\\n\t BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C)\n#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8822C(x, v)                                \\\n\t(BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822C(x) |                              \\\n\t BIT_SPEC_SIFS_OFDM_PTCL_8822C(v))\n\n#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C 0\n#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C 0xff\n#define BIT_SPEC_SIFS_CCK_PTCL_8822C(x)                                        \\\n\t(((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C)                             \\\n\t << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C)\n#define BITS_SPEC_SIFS_CCK_PTCL_8822C                                          \\\n\t(BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C                                     \\\n\t << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C)\n#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822C(x)                                  \\\n\t((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8822C))\n#define BIT_GET_SPEC_SIFS_CCK_PTCL_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C) &                         \\\n\t BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C)\n#define BIT_SET_SPEC_SIFS_CCK_PTCL_8822C(x, v)                                 \\\n\t(BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822C(x) |                               \\\n\t BIT_SPEC_SIFS_CCK_PTCL_8822C(v))\n\n/* 2 REG_RETRY_LIMIT_8822C */\n\n#define BIT_SHIFT_SRL_8822C 8\n#define BIT_MASK_SRL_8822C 0x3f\n#define BIT_SRL_8822C(x) (((x) & BIT_MASK_SRL_8822C) << BIT_SHIFT_SRL_8822C)\n#define BITS_SRL_8822C (BIT_MASK_SRL_8822C << BIT_SHIFT_SRL_8822C)\n#define BIT_CLEAR_SRL_8822C(x) ((x) & (~BITS_SRL_8822C))\n#define BIT_GET_SRL_8822C(x) (((x) >> BIT_SHIFT_SRL_8822C) & BIT_MASK_SRL_8822C)\n#define BIT_SET_SRL_8822C(x, v) (BIT_CLEAR_SRL_8822C(x) | BIT_SRL_8822C(v))\n\n#define BIT_SHIFT_LRL_8822C 0\n#define BIT_MASK_LRL_8822C 0x3f\n#define BIT_LRL_8822C(x) (((x) & BIT_MASK_LRL_8822C) << BIT_SHIFT_LRL_8822C)\n#define BITS_LRL_8822C (BIT_MASK_LRL_8822C << BIT_SHIFT_LRL_8822C)\n#define BIT_CLEAR_LRL_8822C(x) ((x) & (~BITS_LRL_8822C))\n#define BIT_GET_LRL_8822C(x) (((x) >> BIT_SHIFT_LRL_8822C) & BIT_MASK_LRL_8822C)\n#define BIT_SET_LRL_8822C(x, v) (BIT_CLEAR_LRL_8822C(x) | BIT_LRL_8822C(v))\n\n/* 2 REG_TXBF_CTRL_8822C */\n#define BIT_R_ENABLE_NDPA_8822C BIT(31)\n#define BIT_USE_NDPA_PARAMETER_8822C BIT(30)\n#define BIT_R_PROP_TXBF_8822C BIT(29)\n#define BIT_R_EN_NDPA_INT_8822C BIT(28)\n#define BIT_R_TXBF1_80M_8822C BIT(27)\n#define BIT_R_TXBF1_40M_8822C BIT(26)\n#define BIT_R_TXBF1_20M_8822C BIT(25)\n\n#define BIT_SHIFT_R_TXBF1_AID_8822C 16\n#define BIT_MASK_R_TXBF1_AID_8822C 0x1ff\n#define BIT_R_TXBF1_AID_8822C(x)                                               \\\n\t(((x) & BIT_MASK_R_TXBF1_AID_8822C) << BIT_SHIFT_R_TXBF1_AID_8822C)\n#define BITS_R_TXBF1_AID_8822C                                                 \\\n\t(BIT_MASK_R_TXBF1_AID_8822C << BIT_SHIFT_R_TXBF1_AID_8822C)\n#define BIT_CLEAR_R_TXBF1_AID_8822C(x) ((x) & (~BITS_R_TXBF1_AID_8822C))\n#define BIT_GET_R_TXBF1_AID_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_R_TXBF1_AID_8822C) & BIT_MASK_R_TXBF1_AID_8822C)\n#define BIT_SET_R_TXBF1_AID_8822C(x, v)                                        \\\n\t(BIT_CLEAR_R_TXBF1_AID_8822C(x) | BIT_R_TXBF1_AID_8822C(v))\n\n#define BIT_DIS_NDP_BFEN_8822C BIT(15)\n#define BIT_R_TXBCN_NOBLOCK_NDP_8822C BIT(14)\n#define BIT_R_TXBF0_80M_8822C BIT(11)\n#define BIT_R_TXBF0_40M_8822C BIT(10)\n#define BIT_R_TXBF0_20M_8822C BIT(9)\n\n#define BIT_SHIFT_R_TXBF0_AID_8822C 0\n#define BIT_MASK_R_TXBF0_AID_8822C 0x1ff\n#define BIT_R_TXBF0_AID_8822C(x)                                               \\\n\t(((x) & BIT_MASK_R_TXBF0_AID_8822C) << BIT_SHIFT_R_TXBF0_AID_8822C)\n#define BITS_R_TXBF0_AID_8822C                                                 \\\n\t(BIT_MASK_R_TXBF0_AID_8822C << BIT_SHIFT_R_TXBF0_AID_8822C)\n#define BIT_CLEAR_R_TXBF0_AID_8822C(x) ((x) & (~BITS_R_TXBF0_AID_8822C))\n#define BIT_GET_R_TXBF0_AID_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_R_TXBF0_AID_8822C) & BIT_MASK_R_TXBF0_AID_8822C)\n#define BIT_SET_R_TXBF0_AID_8822C(x, v)                                        \\\n\t(BIT_CLEAR_R_TXBF0_AID_8822C(x) | BIT_R_TXBF0_AID_8822C(v))\n\n/* 2 REG_DARFRC_8822C */\n\n#define BIT_SHIFT_DARF_RC4_8822C 24\n#define BIT_MASK_DARF_RC4_8822C 0x1f\n#define BIT_DARF_RC4_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_DARF_RC4_8822C) << BIT_SHIFT_DARF_RC4_8822C)\n#define BITS_DARF_RC4_8822C                                                    \\\n\t(BIT_MASK_DARF_RC4_8822C << BIT_SHIFT_DARF_RC4_8822C)\n#define BIT_CLEAR_DARF_RC4_8822C(x) ((x) & (~BITS_DARF_RC4_8822C))\n#define BIT_GET_DARF_RC4_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_DARF_RC4_8822C) & BIT_MASK_DARF_RC4_8822C)\n#define BIT_SET_DARF_RC4_8822C(x, v)                                           \\\n\t(BIT_CLEAR_DARF_RC4_8822C(x) | BIT_DARF_RC4_8822C(v))\n\n#define BIT_SHIFT_DARF_RC3_8822C 16\n#define BIT_MASK_DARF_RC3_8822C 0x1f\n#define BIT_DARF_RC3_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_DARF_RC3_8822C) << BIT_SHIFT_DARF_RC3_8822C)\n#define BITS_DARF_RC3_8822C                                                    \\\n\t(BIT_MASK_DARF_RC3_8822C << BIT_SHIFT_DARF_RC3_8822C)\n#define BIT_CLEAR_DARF_RC3_8822C(x) ((x) & (~BITS_DARF_RC3_8822C))\n#define BIT_GET_DARF_RC3_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_DARF_RC3_8822C) & BIT_MASK_DARF_RC3_8822C)\n#define BIT_SET_DARF_RC3_8822C(x, v)                                           \\\n\t(BIT_CLEAR_DARF_RC3_8822C(x) | BIT_DARF_RC3_8822C(v))\n\n#define BIT_SHIFT_DARF_RC2_8822C 8\n#define BIT_MASK_DARF_RC2_8822C 0x1f\n#define BIT_DARF_RC2_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_DARF_RC2_8822C) << BIT_SHIFT_DARF_RC2_8822C)\n#define BITS_DARF_RC2_8822C                                                    \\\n\t(BIT_MASK_DARF_RC2_8822C << BIT_SHIFT_DARF_RC2_8822C)\n#define BIT_CLEAR_DARF_RC2_8822C(x) ((x) & (~BITS_DARF_RC2_8822C))\n#define BIT_GET_DARF_RC2_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_DARF_RC2_8822C) & BIT_MASK_DARF_RC2_8822C)\n#define BIT_SET_DARF_RC2_8822C(x, v)                                           \\\n\t(BIT_CLEAR_DARF_RC2_8822C(x) | BIT_DARF_RC2_8822C(v))\n\n#define BIT_SHIFT_DARF_RC1_8822C 0\n#define BIT_MASK_DARF_RC1_8822C 0x1f\n#define BIT_DARF_RC1_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_DARF_RC1_8822C) << BIT_SHIFT_DARF_RC1_8822C)\n#define BITS_DARF_RC1_8822C                                                    \\\n\t(BIT_MASK_DARF_RC1_8822C << BIT_SHIFT_DARF_RC1_8822C)\n#define BIT_CLEAR_DARF_RC1_8822C(x) ((x) & (~BITS_DARF_RC1_8822C))\n#define BIT_GET_DARF_RC1_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_DARF_RC1_8822C) & BIT_MASK_DARF_RC1_8822C)\n#define BIT_SET_DARF_RC1_8822C(x, v)                                           \\\n\t(BIT_CLEAR_DARF_RC1_8822C(x) | BIT_DARF_RC1_8822C(v))\n\n/* 2 REG_DARFRCH_8822C */\n\n#define BIT_SHIFT_DARF_RC8_V1_8822C 24\n#define BIT_MASK_DARF_RC8_V1_8822C 0x1f\n#define BIT_DARF_RC8_V1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC8_V1_8822C) << BIT_SHIFT_DARF_RC8_V1_8822C)\n#define BITS_DARF_RC8_V1_8822C                                                 \\\n\t(BIT_MASK_DARF_RC8_V1_8822C << BIT_SHIFT_DARF_RC8_V1_8822C)\n#define BIT_CLEAR_DARF_RC8_V1_8822C(x) ((x) & (~BITS_DARF_RC8_V1_8822C))\n#define BIT_GET_DARF_RC8_V1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC8_V1_8822C) & BIT_MASK_DARF_RC8_V1_8822C)\n#define BIT_SET_DARF_RC8_V1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC8_V1_8822C(x) | BIT_DARF_RC8_V1_8822C(v))\n\n#define BIT_SHIFT_DARF_RC7_V1_8822C 16\n#define BIT_MASK_DARF_RC7_V1_8822C 0x1f\n#define BIT_DARF_RC7_V1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC7_V1_8822C) << BIT_SHIFT_DARF_RC7_V1_8822C)\n#define BITS_DARF_RC7_V1_8822C                                                 \\\n\t(BIT_MASK_DARF_RC7_V1_8822C << BIT_SHIFT_DARF_RC7_V1_8822C)\n#define BIT_CLEAR_DARF_RC7_V1_8822C(x) ((x) & (~BITS_DARF_RC7_V1_8822C))\n#define BIT_GET_DARF_RC7_V1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC7_V1_8822C) & BIT_MASK_DARF_RC7_V1_8822C)\n#define BIT_SET_DARF_RC7_V1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC7_V1_8822C(x) | BIT_DARF_RC7_V1_8822C(v))\n\n#define BIT_SHIFT_DARF_RC6_V1_8822C 8\n#define BIT_MASK_DARF_RC6_V1_8822C 0x1f\n#define BIT_DARF_RC6_V1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC6_V1_8822C) << BIT_SHIFT_DARF_RC6_V1_8822C)\n#define BITS_DARF_RC6_V1_8822C                                                 \\\n\t(BIT_MASK_DARF_RC6_V1_8822C << BIT_SHIFT_DARF_RC6_V1_8822C)\n#define BIT_CLEAR_DARF_RC6_V1_8822C(x) ((x) & (~BITS_DARF_RC6_V1_8822C))\n#define BIT_GET_DARF_RC6_V1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC6_V1_8822C) & BIT_MASK_DARF_RC6_V1_8822C)\n#define BIT_SET_DARF_RC6_V1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC6_V1_8822C(x) | BIT_DARF_RC6_V1_8822C(v))\n\n#define BIT_SHIFT_DARF_RC5_V1_8822C 0\n#define BIT_MASK_DARF_RC5_V1_8822C 0x1f\n#define BIT_DARF_RC5_V1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_DARF_RC5_V1_8822C) << BIT_SHIFT_DARF_RC5_V1_8822C)\n#define BITS_DARF_RC5_V1_8822C                                                 \\\n\t(BIT_MASK_DARF_RC5_V1_8822C << BIT_SHIFT_DARF_RC5_V1_8822C)\n#define BIT_CLEAR_DARF_RC5_V1_8822C(x) ((x) & (~BITS_DARF_RC5_V1_8822C))\n#define BIT_GET_DARF_RC5_V1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_DARF_RC5_V1_8822C) & BIT_MASK_DARF_RC5_V1_8822C)\n#define BIT_SET_DARF_RC5_V1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_DARF_RC5_V1_8822C(x) | BIT_DARF_RC5_V1_8822C(v))\n\n/* 2 REG_RARFRC_8822C */\n\n#define BIT_SHIFT_RARF_RC4_8822C 24\n#define BIT_MASK_RARF_RC4_8822C 0x1f\n#define BIT_RARF_RC4_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC4_8822C) << BIT_SHIFT_RARF_RC4_8822C)\n#define BITS_RARF_RC4_8822C                                                    \\\n\t(BIT_MASK_RARF_RC4_8822C << BIT_SHIFT_RARF_RC4_8822C)\n#define BIT_CLEAR_RARF_RC4_8822C(x) ((x) & (~BITS_RARF_RC4_8822C))\n#define BIT_GET_RARF_RC4_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC4_8822C) & BIT_MASK_RARF_RC4_8822C)\n#define BIT_SET_RARF_RC4_8822C(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC4_8822C(x) | BIT_RARF_RC4_8822C(v))\n\n#define BIT_SHIFT_RARF_RC3_8822C 16\n#define BIT_MASK_RARF_RC3_8822C 0x1f\n#define BIT_RARF_RC3_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC3_8822C) << BIT_SHIFT_RARF_RC3_8822C)\n#define BITS_RARF_RC3_8822C                                                    \\\n\t(BIT_MASK_RARF_RC3_8822C << BIT_SHIFT_RARF_RC3_8822C)\n#define BIT_CLEAR_RARF_RC3_8822C(x) ((x) & (~BITS_RARF_RC3_8822C))\n#define BIT_GET_RARF_RC3_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC3_8822C) & BIT_MASK_RARF_RC3_8822C)\n#define BIT_SET_RARF_RC3_8822C(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC3_8822C(x) | BIT_RARF_RC3_8822C(v))\n\n#define BIT_SHIFT_RARF_RC2_8822C 8\n#define BIT_MASK_RARF_RC2_8822C 0x1f\n#define BIT_RARF_RC2_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC2_8822C) << BIT_SHIFT_RARF_RC2_8822C)\n#define BITS_RARF_RC2_8822C                                                    \\\n\t(BIT_MASK_RARF_RC2_8822C << BIT_SHIFT_RARF_RC2_8822C)\n#define BIT_CLEAR_RARF_RC2_8822C(x) ((x) & (~BITS_RARF_RC2_8822C))\n#define BIT_GET_RARF_RC2_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC2_8822C) & BIT_MASK_RARF_RC2_8822C)\n#define BIT_SET_RARF_RC2_8822C(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC2_8822C(x) | BIT_RARF_RC2_8822C(v))\n\n#define BIT_SHIFT_RARF_RC1_8822C 0\n#define BIT_MASK_RARF_RC1_8822C 0x1f\n#define BIT_RARF_RC1_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_RARF_RC1_8822C) << BIT_SHIFT_RARF_RC1_8822C)\n#define BITS_RARF_RC1_8822C                                                    \\\n\t(BIT_MASK_RARF_RC1_8822C << BIT_SHIFT_RARF_RC1_8822C)\n#define BIT_CLEAR_RARF_RC1_8822C(x) ((x) & (~BITS_RARF_RC1_8822C))\n#define BIT_GET_RARF_RC1_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RARF_RC1_8822C) & BIT_MASK_RARF_RC1_8822C)\n#define BIT_SET_RARF_RC1_8822C(x, v)                                           \\\n\t(BIT_CLEAR_RARF_RC1_8822C(x) | BIT_RARF_RC1_8822C(v))\n\n/* 2 REG_RARFRCH_8822C */\n\n#define BIT_SHIFT_RARF_RC8_V1_8822C 24\n#define BIT_MASK_RARF_RC8_V1_8822C 0x1f\n#define BIT_RARF_RC8_V1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_RARF_RC8_V1_8822C) << BIT_SHIFT_RARF_RC8_V1_8822C)\n#define BITS_RARF_RC8_V1_8822C                                                 \\\n\t(BIT_MASK_RARF_RC8_V1_8822C << BIT_SHIFT_RARF_RC8_V1_8822C)\n#define BIT_CLEAR_RARF_RC8_V1_8822C(x) ((x) & (~BITS_RARF_RC8_V1_8822C))\n#define BIT_GET_RARF_RC8_V1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RARF_RC8_V1_8822C) & BIT_MASK_RARF_RC8_V1_8822C)\n#define BIT_SET_RARF_RC8_V1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_RARF_RC8_V1_8822C(x) | BIT_RARF_RC8_V1_8822C(v))\n\n#define BIT_SHIFT_RARF_RC7_V1_8822C 16\n#define BIT_MASK_RARF_RC7_V1_8822C 0x1f\n#define BIT_RARF_RC7_V1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_RARF_RC7_V1_8822C) << BIT_SHIFT_RARF_RC7_V1_8822C)\n#define BITS_RARF_RC7_V1_8822C                                                 \\\n\t(BIT_MASK_RARF_RC7_V1_8822C << BIT_SHIFT_RARF_RC7_V1_8822C)\n#define BIT_CLEAR_RARF_RC7_V1_8822C(x) ((x) & (~BITS_RARF_RC7_V1_8822C))\n#define BIT_GET_RARF_RC7_V1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RARF_RC7_V1_8822C) & BIT_MASK_RARF_RC7_V1_8822C)\n#define BIT_SET_RARF_RC7_V1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_RARF_RC7_V1_8822C(x) | BIT_RARF_RC7_V1_8822C(v))\n\n#define BIT_SHIFT_RARF_RC6_V1_8822C 8\n#define BIT_MASK_RARF_RC6_V1_8822C 0x1f\n#define BIT_RARF_RC6_V1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_RARF_RC6_V1_8822C) << BIT_SHIFT_RARF_RC6_V1_8822C)\n#define BITS_RARF_RC6_V1_8822C                                                 \\\n\t(BIT_MASK_RARF_RC6_V1_8822C << BIT_SHIFT_RARF_RC6_V1_8822C)\n#define BIT_CLEAR_RARF_RC6_V1_8822C(x) ((x) & (~BITS_RARF_RC6_V1_8822C))\n#define BIT_GET_RARF_RC6_V1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RARF_RC6_V1_8822C) & BIT_MASK_RARF_RC6_V1_8822C)\n#define BIT_SET_RARF_RC6_V1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_RARF_RC6_V1_8822C(x) | BIT_RARF_RC6_V1_8822C(v))\n\n#define BIT_SHIFT_RARF_RC5_V1_8822C 0\n#define BIT_MASK_RARF_RC5_V1_8822C 0x1f\n#define BIT_RARF_RC5_V1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_RARF_RC5_V1_8822C) << BIT_SHIFT_RARF_RC5_V1_8822C)\n#define BITS_RARF_RC5_V1_8822C                                                 \\\n\t(BIT_MASK_RARF_RC5_V1_8822C << BIT_SHIFT_RARF_RC5_V1_8822C)\n#define BIT_CLEAR_RARF_RC5_V1_8822C(x) ((x) & (~BITS_RARF_RC5_V1_8822C))\n#define BIT_GET_RARF_RC5_V1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RARF_RC5_V1_8822C) & BIT_MASK_RARF_RC5_V1_8822C)\n#define BIT_SET_RARF_RC5_V1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_RARF_RC5_V1_8822C(x) | BIT_RARF_RC5_V1_8822C(v))\n\n/* 2 REG_RRSR_8822C */\n\n#define BIT_SHIFT_RRSR_RSC_8822C 21\n#define BIT_MASK_RRSR_RSC_8822C 0x3\n#define BIT_RRSR_RSC_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_RRSR_RSC_8822C) << BIT_SHIFT_RRSR_RSC_8822C)\n#define BITS_RRSR_RSC_8822C                                                    \\\n\t(BIT_MASK_RRSR_RSC_8822C << BIT_SHIFT_RRSR_RSC_8822C)\n#define BIT_CLEAR_RRSR_RSC_8822C(x) ((x) & (~BITS_RRSR_RSC_8822C))\n#define BIT_GET_RRSR_RSC_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RRSR_RSC_8822C) & BIT_MASK_RRSR_RSC_8822C)\n#define BIT_SET_RRSR_RSC_8822C(x, v)                                           \\\n\t(BIT_CLEAR_RRSR_RSC_8822C(x) | BIT_RRSR_RSC_8822C(v))\n\n#define BIT_SHIFT_RRSC_BITMAP_8822C 0\n#define BIT_MASK_RRSC_BITMAP_8822C 0xfffff\n#define BIT_RRSC_BITMAP_8822C(x)                                               \\\n\t(((x) & BIT_MASK_RRSC_BITMAP_8822C) << BIT_SHIFT_RRSC_BITMAP_8822C)\n#define BITS_RRSC_BITMAP_8822C                                                 \\\n\t(BIT_MASK_RRSC_BITMAP_8822C << BIT_SHIFT_RRSC_BITMAP_8822C)\n#define BIT_CLEAR_RRSC_BITMAP_8822C(x) ((x) & (~BITS_RRSC_BITMAP_8822C))\n#define BIT_GET_RRSC_BITMAP_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RRSC_BITMAP_8822C) & BIT_MASK_RRSC_BITMAP_8822C)\n#define BIT_SET_RRSC_BITMAP_8822C(x, v)                                        \\\n\t(BIT_CLEAR_RRSC_BITMAP_8822C(x) | BIT_RRSC_BITMAP_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_ARFR0_8822C */\n\n#define BIT_SHIFT_ARFRL0_8822C 0\n#define BIT_MASK_ARFRL0_8822C 0xffffffffL\n#define BIT_ARFRL0_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRL0_8822C) << BIT_SHIFT_ARFRL0_8822C)\n#define BITS_ARFRL0_8822C (BIT_MASK_ARFRL0_8822C << BIT_SHIFT_ARFRL0_8822C)\n#define BIT_CLEAR_ARFRL0_8822C(x) ((x) & (~BITS_ARFRL0_8822C))\n#define BIT_GET_ARFRL0_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRL0_8822C) & BIT_MASK_ARFRL0_8822C)\n#define BIT_SET_ARFRL0_8822C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRL0_8822C(x) | BIT_ARFRL0_8822C(v))\n\n/* 2 REG_ARFRH0_8822C */\n\n#define BIT_SHIFT_ARFRH0_8822C 0\n#define BIT_MASK_ARFRH0_8822C 0xffffffffL\n#define BIT_ARFRH0_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRH0_8822C) << BIT_SHIFT_ARFRH0_8822C)\n#define BITS_ARFRH0_8822C (BIT_MASK_ARFRH0_8822C << BIT_SHIFT_ARFRH0_8822C)\n#define BIT_CLEAR_ARFRH0_8822C(x) ((x) & (~BITS_ARFRH0_8822C))\n#define BIT_GET_ARFRH0_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRH0_8822C) & BIT_MASK_ARFRH0_8822C)\n#define BIT_SET_ARFRH0_8822C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRH0_8822C(x) | BIT_ARFRH0_8822C(v))\n\n/* 2 REG_ARFR1_V1_8822C */\n\n#define BIT_SHIFT_ARFRL1_8822C 0\n#define BIT_MASK_ARFRL1_8822C 0xffffffffL\n#define BIT_ARFRL1_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRL1_8822C) << BIT_SHIFT_ARFRL1_8822C)\n#define BITS_ARFRL1_8822C (BIT_MASK_ARFRL1_8822C << BIT_SHIFT_ARFRL1_8822C)\n#define BIT_CLEAR_ARFRL1_8822C(x) ((x) & (~BITS_ARFRL1_8822C))\n#define BIT_GET_ARFRL1_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRL1_8822C) & BIT_MASK_ARFRL1_8822C)\n#define BIT_SET_ARFRL1_8822C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRL1_8822C(x) | BIT_ARFRL1_8822C(v))\n\n/* 2 REG_ARFRH1_V1_8822C */\n\n#define BIT_SHIFT_ARFRH1_8822C 0\n#define BIT_MASK_ARFRH1_8822C 0xffffffffL\n#define BIT_ARFRH1_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRH1_8822C) << BIT_SHIFT_ARFRH1_8822C)\n#define BITS_ARFRH1_8822C (BIT_MASK_ARFRH1_8822C << BIT_SHIFT_ARFRH1_8822C)\n#define BIT_CLEAR_ARFRH1_8822C(x) ((x) & (~BITS_ARFRH1_8822C))\n#define BIT_GET_ARFRH1_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRH1_8822C) & BIT_MASK_ARFRH1_8822C)\n#define BIT_SET_ARFRH1_8822C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRH1_8822C(x) | BIT_ARFRH1_8822C(v))\n\n/* 2 REG_CCK_CHECK_8822C */\n#define BIT_CHECK_CCK_EN_8822C BIT(7)\n#define BIT_EN_BCN_PKT_REL_8822C BIT(6)\n#define BIT_BCN_PORT_SEL_8822C BIT(5)\n#define BIT_MOREDATA_BYPASS_8822C BIT(4)\n#define BIT_EN_CLR_CMD_REL_BCN_PKT_8822C BIT(3)\n#define BIT_R_EN_SET_MOREDATA_8822C BIT(2)\n#define BIT__R_DIS_CLEAR_MACID_RELEASE_8822C BIT(1)\n#define BIT__R_MACID_RELEASE_EN_8822C BIT(0)\n\n/* 2 REG_AMPDU_MAX_TIME_V1_8822C */\n\n#define BIT_SHIFT_AMPDU_MAX_TIME_8822C 0\n#define BIT_MASK_AMPDU_MAX_TIME_8822C 0xff\n#define BIT_AMPDU_MAX_TIME_8822C(x)                                            \\\n\t(((x) & BIT_MASK_AMPDU_MAX_TIME_8822C)                                 \\\n\t << BIT_SHIFT_AMPDU_MAX_TIME_8822C)\n#define BITS_AMPDU_MAX_TIME_8822C                                              \\\n\t(BIT_MASK_AMPDU_MAX_TIME_8822C << BIT_SHIFT_AMPDU_MAX_TIME_8822C)\n#define BIT_CLEAR_AMPDU_MAX_TIME_8822C(x) ((x) & (~BITS_AMPDU_MAX_TIME_8822C))\n#define BIT_GET_AMPDU_MAX_TIME_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8822C) &                             \\\n\t BIT_MASK_AMPDU_MAX_TIME_8822C)\n#define BIT_SET_AMPDU_MAX_TIME_8822C(x, v)                                     \\\n\t(BIT_CLEAR_AMPDU_MAX_TIME_8822C(x) | BIT_AMPDU_MAX_TIME_8822C(v))\n\n/* 2 REG_BCNQ1_BDNY_V1_8822C */\n\n#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C 0\n#define BIT_MASK_BCNQ1_PGBNDY_V1_8822C 0xfff\n#define BIT_BCNQ1_PGBNDY_V1_8822C(x)                                           \\\n\t(((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8822C)                                \\\n\t << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C)\n#define BITS_BCNQ1_PGBNDY_V1_8822C                                             \\\n\t(BIT_MASK_BCNQ1_PGBNDY_V1_8822C << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C)\n#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8822C(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8822C))\n#define BIT_GET_BCNQ1_PGBNDY_V1_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C) &                            \\\n\t BIT_MASK_BCNQ1_PGBNDY_V1_8822C)\n#define BIT_SET_BCNQ1_PGBNDY_V1_8822C(x, v)                                    \\\n\t(BIT_CLEAR_BCNQ1_PGBNDY_V1_8822C(x) | BIT_BCNQ1_PGBNDY_V1_8822C(v))\n\n/* 2 REG_AMPDU_MAX_LENGTH_HT_8822C */\n\n#define BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C 0\n#define BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C 0xffff\n#define BIT_AMPDU_MAX_LENGTH_HT_8822C(x)                                       \\\n\t(((x) & BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C)                            \\\n\t << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C)\n#define BITS_AMPDU_MAX_LENGTH_HT_8822C                                         \\\n\t(BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C                                    \\\n\t << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C)\n#define BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8822C(x)                                 \\\n\t((x) & (~BITS_AMPDU_MAX_LENGTH_HT_8822C))\n#define BIT_GET_AMPDU_MAX_LENGTH_HT_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C) &                        \\\n\t BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C)\n#define BIT_SET_AMPDU_MAX_LENGTH_HT_8822C(x, v)                                \\\n\t(BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8822C(x) |                              \\\n\t BIT_AMPDU_MAX_LENGTH_HT_8822C(v))\n\n/* 2 REG_ACQ_STOP_8822C */\n#define BIT_AC7Q_STOP_8822C BIT(7)\n#define BIT_AC6Q_STOP_8822C BIT(6)\n#define BIT_AC5Q_STOP_8822C BIT(5)\n#define BIT_AC4Q_STOP_8822C BIT(4)\n#define BIT_AC3Q_STOP_8822C BIT(3)\n#define BIT_AC2Q_STOP_8822C BIT(2)\n#define BIT_AC1Q_STOP_8822C BIT(1)\n#define BIT_AC0Q_STOP_8822C BIT(0)\n\n/* 2 REG_NDPA_RATE_8822C */\n\n#define BIT_SHIFT_R_NDPA_RATE_V1_8822C 0\n#define BIT_MASK_R_NDPA_RATE_V1_8822C 0xff\n#define BIT_R_NDPA_RATE_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_R_NDPA_RATE_V1_8822C)                                 \\\n\t << BIT_SHIFT_R_NDPA_RATE_V1_8822C)\n#define BITS_R_NDPA_RATE_V1_8822C                                              \\\n\t(BIT_MASK_R_NDPA_RATE_V1_8822C << BIT_SHIFT_R_NDPA_RATE_V1_8822C)\n#define BIT_CLEAR_R_NDPA_RATE_V1_8822C(x) ((x) & (~BITS_R_NDPA_RATE_V1_8822C))\n#define BIT_GET_R_NDPA_RATE_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8822C) &                             \\\n\t BIT_MASK_R_NDPA_RATE_V1_8822C)\n#define BIT_SET_R_NDPA_RATE_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_R_NDPA_RATE_V1_8822C(x) | BIT_R_NDPA_RATE_V1_8822C(v))\n\n/* 2 REG_TX_HANG_CTRL_8822C */\n#define BIT_R_EN_GNT_BT_AWAKE_8822C BIT(3)\n#define BIT_EN_EOF_V1_8822C BIT(2)\n#define BIT_DIS_OQT_BLOCK_8822C BIT(1)\n#define BIT_SEARCH_QUEUE_EN_8822C BIT(0)\n\n/* 2 REG_NDPA_OPT_CTRL_8822C */\n#define BIT_R_DIS_MACID_RELEASE_RTY_8822C BIT(5)\n\n#define BIT_SHIFT_BW_SIGTA_8822C 3\n#define BIT_MASK_BW_SIGTA_8822C 0x3\n#define BIT_BW_SIGTA_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_BW_SIGTA_8822C) << BIT_SHIFT_BW_SIGTA_8822C)\n#define BITS_BW_SIGTA_8822C                                                    \\\n\t(BIT_MASK_BW_SIGTA_8822C << BIT_SHIFT_BW_SIGTA_8822C)\n#define BIT_CLEAR_BW_SIGTA_8822C(x) ((x) & (~BITS_BW_SIGTA_8822C))\n#define BIT_GET_BW_SIGTA_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_BW_SIGTA_8822C) & BIT_MASK_BW_SIGTA_8822C)\n#define BIT_SET_BW_SIGTA_8822C(x, v)                                           \\\n\t(BIT_CLEAR_BW_SIGTA_8822C(x) | BIT_BW_SIGTA_8822C(v))\n\n#define BIT_EN_BAR_SIGTA_8822C BIT(2)\n\n#define BIT_SHIFT_R_NDPA_BW_8822C 0\n#define BIT_MASK_R_NDPA_BW_8822C 0x3\n#define BIT_R_NDPA_BW_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_R_NDPA_BW_8822C) << BIT_SHIFT_R_NDPA_BW_8822C)\n#define BITS_R_NDPA_BW_8822C                                                   \\\n\t(BIT_MASK_R_NDPA_BW_8822C << BIT_SHIFT_R_NDPA_BW_8822C)\n#define BIT_CLEAR_R_NDPA_BW_8822C(x) ((x) & (~BITS_R_NDPA_BW_8822C))\n#define BIT_GET_R_NDPA_BW_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_R_NDPA_BW_8822C) & BIT_MASK_R_NDPA_BW_8822C)\n#define BIT_SET_R_NDPA_BW_8822C(x, v)                                          \\\n\t(BIT_CLEAR_R_NDPA_BW_8822C(x) | BIT_R_NDPA_BW_8822C(v))\n\n/* 2 REG_AMPDU_MAX_LENGTH_VHT_8822C */\n\n#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C 0\n#define BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C 0xfffff\n#define BIT_AMPDU_MAX_LENGTH_VHT_V1_8822C(x)                                   \\\n\t(((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C)                        \\\n\t << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C)\n#define BITS_AMPDU_MAX_LENGTH_VHT_V1_8822C                                     \\\n\t(BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C                                \\\n\t << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C)\n#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1_8822C(x)                             \\\n\t((x) & (~BITS_AMPDU_MAX_LENGTH_VHT_V1_8822C))\n#define BIT_GET_AMPDU_MAX_LENGTH_VHT_V1_8822C(x)                               \\\n\t(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C) &                    \\\n\t BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C)\n#define BIT_SET_AMPDU_MAX_LENGTH_VHT_V1_8822C(x, v)                            \\\n\t(BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1_8822C(x) |                          \\\n\t BIT_AMPDU_MAX_LENGTH_VHT_V1_8822C(v))\n\n/* 2 REG_RD_RESP_PKT_TH_8822C */\n\n#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C 0\n#define BIT_MASK_RD_RESP_PKT_TH_V1_8822C 0x3f\n#define BIT_RD_RESP_PKT_TH_V1_8822C(x)                                         \\\n\t(((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8822C)                              \\\n\t << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C)\n#define BITS_RD_RESP_PKT_TH_V1_8822C                                           \\\n\t(BIT_MASK_RD_RESP_PKT_TH_V1_8822C << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C)\n#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8822C(x)                                   \\\n\t((x) & (~BITS_RD_RESP_PKT_TH_V1_8822C))\n#define BIT_GET_RD_RESP_PKT_TH_V1_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C) &                          \\\n\t BIT_MASK_RD_RESP_PKT_TH_V1_8822C)\n#define BIT_SET_RD_RESP_PKT_TH_V1_8822C(x, v)                                  \\\n\t(BIT_CLEAR_RD_RESP_PKT_TH_V1_8822C(x) | BIT_RD_RESP_PKT_TH_V1_8822C(v))\n\n/* 2 REG_CMDQ_INFO_8822C */\n\n#define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C 25\n#define BIT_MASK_QUEUEMACID_CMDQ_V1_8822C 0x7f\n#define BIT_QUEUEMACID_CMDQ_V1_8822C(x)                                        \\\n\t(((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822C)                             \\\n\t << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C)\n#define BITS_QUEUEMACID_CMDQ_V1_8822C                                          \\\n\t(BIT_MASK_QUEUEMACID_CMDQ_V1_8822C                                     \\\n\t << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C)\n#define BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822C(x)                                  \\\n\t((x) & (~BITS_QUEUEMACID_CMDQ_V1_8822C))\n#define BIT_GET_QUEUEMACID_CMDQ_V1_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C) &                         \\\n\t BIT_MASK_QUEUEMACID_CMDQ_V1_8822C)\n#define BIT_SET_QUEUEMACID_CMDQ_V1_8822C(x, v)                                 \\\n\t(BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822C(x) |                               \\\n\t BIT_QUEUEMACID_CMDQ_V1_8822C(v))\n\n#define BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C 23\n#define BIT_MASK_QUEUEAC_CMDQ_V1_8822C 0x3\n#define BIT_QUEUEAC_CMDQ_V1_8822C(x)                                           \\\n\t(((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8822C)                                \\\n\t << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C)\n#define BITS_QUEUEAC_CMDQ_V1_8822C                                             \\\n\t(BIT_MASK_QUEUEAC_CMDQ_V1_8822C << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C)\n#define BIT_CLEAR_QUEUEAC_CMDQ_V1_8822C(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1_8822C))\n#define BIT_GET_QUEUEAC_CMDQ_V1_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C) &                            \\\n\t BIT_MASK_QUEUEAC_CMDQ_V1_8822C)\n#define BIT_SET_QUEUEAC_CMDQ_V1_8822C(x, v)                                    \\\n\t(BIT_CLEAR_QUEUEAC_CMDQ_V1_8822C(x) | BIT_QUEUEAC_CMDQ_V1_8822C(v))\n\n#define BIT_TIDEMPTY_CMDQ_V1_8822C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q4_V2_8822C 11\n#define BIT_MASK_TAIL_PKT_Q4_V2_8822C 0x7ff\n#define BIT_TAIL_PKT_Q4_V2_8822C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C)\n#define BITS_TAIL_PKT_Q4_V2_8822C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q4_V2_8822C << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C)\n#define BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8822C))\n#define BIT_GET_TAIL_PKT_Q4_V2_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q4_V2_8822C)\n#define BIT_SET_TAIL_PKT_Q4_V2_8822C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) | BIT_TAIL_PKT_Q4_V2_8822C(v))\n\n#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C 0\n#define BIT_MASK_HEAD_PKT_CMDQ_V1_8822C 0x7ff\n#define BIT_HEAD_PKT_CMDQ_V1_8822C(x)                                          \\\n\t(((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822C)                               \\\n\t << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C)\n#define BITS_HEAD_PKT_CMDQ_V1_8822C                                            \\\n\t(BIT_MASK_HEAD_PKT_CMDQ_V1_8822C << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C)\n#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822C(x)                                    \\\n\t((x) & (~BITS_HEAD_PKT_CMDQ_V1_8822C))\n#define BIT_GET_HEAD_PKT_CMDQ_V1_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C) &                           \\\n\t BIT_MASK_HEAD_PKT_CMDQ_V1_8822C)\n#define BIT_SET_HEAD_PKT_CMDQ_V1_8822C(x, v)                                   \\\n\t(BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822C(x) | BIT_HEAD_PKT_CMDQ_V1_8822C(v))\n\n/* 2 REG_Q4_INFO_8822C */\n\n#define BIT_SHIFT_QUEUEMACID_Q4_V1_8822C 25\n#define BIT_MASK_QUEUEMACID_Q4_V1_8822C 0x7f\n#define BIT_QUEUEMACID_Q4_V1_8822C(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q4_V1_8822C)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q4_V1_8822C)\n#define BITS_QUEUEMACID_Q4_V1_8822C                                            \\\n\t(BIT_MASK_QUEUEMACID_Q4_V1_8822C << BIT_SHIFT_QUEUEMACID_Q4_V1_8822C)\n#define BIT_CLEAR_QUEUEMACID_Q4_V1_8822C(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q4_V1_8822C))\n#define BIT_GET_QUEUEMACID_Q4_V1_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8822C) &                           \\\n\t BIT_MASK_QUEUEMACID_Q4_V1_8822C)\n#define BIT_SET_QUEUEMACID_Q4_V1_8822C(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q4_V1_8822C(x) | BIT_QUEUEMACID_Q4_V1_8822C(v))\n\n#define BIT_SHIFT_QUEUEAC_Q4_V1_8822C 23\n#define BIT_MASK_QUEUEAC_Q4_V1_8822C 0x3\n#define BIT_QUEUEAC_Q4_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q4_V1_8822C) << BIT_SHIFT_QUEUEAC_Q4_V1_8822C)\n#define BITS_QUEUEAC_Q4_V1_8822C                                               \\\n\t(BIT_MASK_QUEUEAC_Q4_V1_8822C << BIT_SHIFT_QUEUEAC_Q4_V1_8822C)\n#define BIT_CLEAR_QUEUEAC_Q4_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8822C))\n#define BIT_GET_QUEUEAC_Q4_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8822C) & BIT_MASK_QUEUEAC_Q4_V1_8822C)\n#define BIT_SET_QUEUEAC_Q4_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q4_V1_8822C(x) | BIT_QUEUEAC_Q4_V1_8822C(v))\n\n#define BIT_TIDEMPTY_Q4_V1_8822C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q4_V2_8822C 11\n#define BIT_MASK_TAIL_PKT_Q4_V2_8822C 0x7ff\n#define BIT_TAIL_PKT_Q4_V2_8822C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C)\n#define BITS_TAIL_PKT_Q4_V2_8822C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q4_V2_8822C << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C)\n#define BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8822C))\n#define BIT_GET_TAIL_PKT_Q4_V2_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q4_V2_8822C)\n#define BIT_SET_TAIL_PKT_Q4_V2_8822C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) | BIT_TAIL_PKT_Q4_V2_8822C(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q4_V1_8822C 0\n#define BIT_MASK_HEAD_PKT_Q4_V1_8822C 0x7ff\n#define BIT_HEAD_PKT_Q4_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q4_V1_8822C)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q4_V1_8822C)\n#define BITS_HEAD_PKT_Q4_V1_8822C                                              \\\n\t(BIT_MASK_HEAD_PKT_Q4_V1_8822C << BIT_SHIFT_HEAD_PKT_Q4_V1_8822C)\n#define BIT_CLEAR_HEAD_PKT_Q4_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8822C))\n#define BIT_GET_HEAD_PKT_Q4_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8822C) &                             \\\n\t BIT_MASK_HEAD_PKT_Q4_V1_8822C)\n#define BIT_SET_HEAD_PKT_Q4_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q4_V1_8822C(x) | BIT_HEAD_PKT_Q4_V1_8822C(v))\n\n/* 2 REG_Q5_INFO_8822C */\n\n#define BIT_SHIFT_QUEUEMACID_Q5_V1_8822C 25\n#define BIT_MASK_QUEUEMACID_Q5_V1_8822C 0x7f\n#define BIT_QUEUEMACID_Q5_V1_8822C(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q5_V1_8822C)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q5_V1_8822C)\n#define BITS_QUEUEMACID_Q5_V1_8822C                                            \\\n\t(BIT_MASK_QUEUEMACID_Q5_V1_8822C << BIT_SHIFT_QUEUEMACID_Q5_V1_8822C)\n#define BIT_CLEAR_QUEUEMACID_Q5_V1_8822C(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q5_V1_8822C))\n#define BIT_GET_QUEUEMACID_Q5_V1_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8822C) &                           \\\n\t BIT_MASK_QUEUEMACID_Q5_V1_8822C)\n#define BIT_SET_QUEUEMACID_Q5_V1_8822C(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q5_V1_8822C(x) | BIT_QUEUEMACID_Q5_V1_8822C(v))\n\n#define BIT_SHIFT_QUEUEAC_Q5_V1_8822C 23\n#define BIT_MASK_QUEUEAC_Q5_V1_8822C 0x3\n#define BIT_QUEUEAC_Q5_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q5_V1_8822C) << BIT_SHIFT_QUEUEAC_Q5_V1_8822C)\n#define BITS_QUEUEAC_Q5_V1_8822C                                               \\\n\t(BIT_MASK_QUEUEAC_Q5_V1_8822C << BIT_SHIFT_QUEUEAC_Q5_V1_8822C)\n#define BIT_CLEAR_QUEUEAC_Q5_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8822C))\n#define BIT_GET_QUEUEAC_Q5_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8822C) & BIT_MASK_QUEUEAC_Q5_V1_8822C)\n#define BIT_SET_QUEUEAC_Q5_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q5_V1_8822C(x) | BIT_QUEUEAC_Q5_V1_8822C(v))\n\n#define BIT_TIDEMPTY_Q5_V1_8822C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q5_V2_8822C 11\n#define BIT_MASK_TAIL_PKT_Q5_V2_8822C 0x7ff\n#define BIT_TAIL_PKT_Q5_V2_8822C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q5_V2_8822C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q5_V2_8822C)\n#define BITS_TAIL_PKT_Q5_V2_8822C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q5_V2_8822C << BIT_SHIFT_TAIL_PKT_Q5_V2_8822C)\n#define BIT_CLEAR_TAIL_PKT_Q5_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8822C))\n#define BIT_GET_TAIL_PKT_Q5_V2_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8822C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q5_V2_8822C)\n#define BIT_SET_TAIL_PKT_Q5_V2_8822C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q5_V2_8822C(x) | BIT_TAIL_PKT_Q5_V2_8822C(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q5_V1_8822C 0\n#define BIT_MASK_HEAD_PKT_Q5_V1_8822C 0x7ff\n#define BIT_HEAD_PKT_Q5_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q5_V1_8822C)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q5_V1_8822C)\n#define BITS_HEAD_PKT_Q5_V1_8822C                                              \\\n\t(BIT_MASK_HEAD_PKT_Q5_V1_8822C << BIT_SHIFT_HEAD_PKT_Q5_V1_8822C)\n#define BIT_CLEAR_HEAD_PKT_Q5_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8822C))\n#define BIT_GET_HEAD_PKT_Q5_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8822C) &                             \\\n\t BIT_MASK_HEAD_PKT_Q5_V1_8822C)\n#define BIT_SET_HEAD_PKT_Q5_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q5_V1_8822C(x) | BIT_HEAD_PKT_Q5_V1_8822C(v))\n\n/* 2 REG_Q6_INFO_8822C */\n\n#define BIT_SHIFT_QUEUEMACID_Q6_V1_8822C 25\n#define BIT_MASK_QUEUEMACID_Q6_V1_8822C 0x7f\n#define BIT_QUEUEMACID_Q6_V1_8822C(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q6_V1_8822C)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q6_V1_8822C)\n#define BITS_QUEUEMACID_Q6_V1_8822C                                            \\\n\t(BIT_MASK_QUEUEMACID_Q6_V1_8822C << BIT_SHIFT_QUEUEMACID_Q6_V1_8822C)\n#define BIT_CLEAR_QUEUEMACID_Q6_V1_8822C(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q6_V1_8822C))\n#define BIT_GET_QUEUEMACID_Q6_V1_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8822C) &                           \\\n\t BIT_MASK_QUEUEMACID_Q6_V1_8822C)\n#define BIT_SET_QUEUEMACID_Q6_V1_8822C(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q6_V1_8822C(x) | BIT_QUEUEMACID_Q6_V1_8822C(v))\n\n#define BIT_SHIFT_QUEUEAC_Q6_V1_8822C 23\n#define BIT_MASK_QUEUEAC_Q6_V1_8822C 0x3\n#define BIT_QUEUEAC_Q6_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q6_V1_8822C) << BIT_SHIFT_QUEUEAC_Q6_V1_8822C)\n#define BITS_QUEUEAC_Q6_V1_8822C                                               \\\n\t(BIT_MASK_QUEUEAC_Q6_V1_8822C << BIT_SHIFT_QUEUEAC_Q6_V1_8822C)\n#define BIT_CLEAR_QUEUEAC_Q6_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8822C))\n#define BIT_GET_QUEUEAC_Q6_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8822C) & BIT_MASK_QUEUEAC_Q6_V1_8822C)\n#define BIT_SET_QUEUEAC_Q6_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q6_V1_8822C(x) | BIT_QUEUEAC_Q6_V1_8822C(v))\n\n#define BIT_TIDEMPTY_Q6_V1_8822C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q6_V2_8822C 11\n#define BIT_MASK_TAIL_PKT_Q6_V2_8822C 0x7ff\n#define BIT_TAIL_PKT_Q6_V2_8822C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q6_V2_8822C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q6_V2_8822C)\n#define BITS_TAIL_PKT_Q6_V2_8822C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q6_V2_8822C << BIT_SHIFT_TAIL_PKT_Q6_V2_8822C)\n#define BIT_CLEAR_TAIL_PKT_Q6_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8822C))\n#define BIT_GET_TAIL_PKT_Q6_V2_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8822C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q6_V2_8822C)\n#define BIT_SET_TAIL_PKT_Q6_V2_8822C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q6_V2_8822C(x) | BIT_TAIL_PKT_Q6_V2_8822C(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q6_V1_8822C 0\n#define BIT_MASK_HEAD_PKT_Q6_V1_8822C 0x7ff\n#define BIT_HEAD_PKT_Q6_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q6_V1_8822C)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q6_V1_8822C)\n#define BITS_HEAD_PKT_Q6_V1_8822C                                              \\\n\t(BIT_MASK_HEAD_PKT_Q6_V1_8822C << BIT_SHIFT_HEAD_PKT_Q6_V1_8822C)\n#define BIT_CLEAR_HEAD_PKT_Q6_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8822C))\n#define BIT_GET_HEAD_PKT_Q6_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8822C) &                             \\\n\t BIT_MASK_HEAD_PKT_Q6_V1_8822C)\n#define BIT_SET_HEAD_PKT_Q6_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q6_V1_8822C(x) | BIT_HEAD_PKT_Q6_V1_8822C(v))\n\n/* 2 REG_Q7_INFO_8822C */\n\n#define BIT_SHIFT_QUEUEMACID_Q7_V1_8822C 25\n#define BIT_MASK_QUEUEMACID_Q7_V1_8822C 0x7f\n#define BIT_QUEUEMACID_Q7_V1_8822C(x)                                          \\\n\t(((x) & BIT_MASK_QUEUEMACID_Q7_V1_8822C)                               \\\n\t << BIT_SHIFT_QUEUEMACID_Q7_V1_8822C)\n#define BITS_QUEUEMACID_Q7_V1_8822C                                            \\\n\t(BIT_MASK_QUEUEMACID_Q7_V1_8822C << BIT_SHIFT_QUEUEMACID_Q7_V1_8822C)\n#define BIT_CLEAR_QUEUEMACID_Q7_V1_8822C(x)                                    \\\n\t((x) & (~BITS_QUEUEMACID_Q7_V1_8822C))\n#define BIT_GET_QUEUEMACID_Q7_V1_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8822C) &                           \\\n\t BIT_MASK_QUEUEMACID_Q7_V1_8822C)\n#define BIT_SET_QUEUEMACID_Q7_V1_8822C(x, v)                                   \\\n\t(BIT_CLEAR_QUEUEMACID_Q7_V1_8822C(x) | BIT_QUEUEMACID_Q7_V1_8822C(v))\n\n#define BIT_SHIFT_QUEUEAC_Q7_V1_8822C 23\n#define BIT_MASK_QUEUEAC_Q7_V1_8822C 0x3\n#define BIT_QUEUEAC_Q7_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_QUEUEAC_Q7_V1_8822C) << BIT_SHIFT_QUEUEAC_Q7_V1_8822C)\n#define BITS_QUEUEAC_Q7_V1_8822C                                               \\\n\t(BIT_MASK_QUEUEAC_Q7_V1_8822C << BIT_SHIFT_QUEUEAC_Q7_V1_8822C)\n#define BIT_CLEAR_QUEUEAC_Q7_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8822C))\n#define BIT_GET_QUEUEAC_Q7_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8822C) & BIT_MASK_QUEUEAC_Q7_V1_8822C)\n#define BIT_SET_QUEUEAC_Q7_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_QUEUEAC_Q7_V1_8822C(x) | BIT_QUEUEAC_Q7_V1_8822C(v))\n\n#define BIT_TIDEMPTY_Q7_V1_8822C BIT(22)\n\n#define BIT_SHIFT_TAIL_PKT_Q7_V2_8822C 11\n#define BIT_MASK_TAIL_PKT_Q7_V2_8822C 0x7ff\n#define BIT_TAIL_PKT_Q7_V2_8822C(x)                                            \\\n\t(((x) & BIT_MASK_TAIL_PKT_Q7_V2_8822C)                                 \\\n\t << BIT_SHIFT_TAIL_PKT_Q7_V2_8822C)\n#define BITS_TAIL_PKT_Q7_V2_8822C                                              \\\n\t(BIT_MASK_TAIL_PKT_Q7_V2_8822C << BIT_SHIFT_TAIL_PKT_Q7_V2_8822C)\n#define BIT_CLEAR_TAIL_PKT_Q7_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8822C))\n#define BIT_GET_TAIL_PKT_Q7_V2_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8822C) &                             \\\n\t BIT_MASK_TAIL_PKT_Q7_V2_8822C)\n#define BIT_SET_TAIL_PKT_Q7_V2_8822C(x, v)                                     \\\n\t(BIT_CLEAR_TAIL_PKT_Q7_V2_8822C(x) | BIT_TAIL_PKT_Q7_V2_8822C(v))\n\n#define BIT_SHIFT_HEAD_PKT_Q7_V1_8822C 0\n#define BIT_MASK_HEAD_PKT_Q7_V1_8822C 0x7ff\n#define BIT_HEAD_PKT_Q7_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_HEAD_PKT_Q7_V1_8822C)                                 \\\n\t << BIT_SHIFT_HEAD_PKT_Q7_V1_8822C)\n#define BITS_HEAD_PKT_Q7_V1_8822C                                              \\\n\t(BIT_MASK_HEAD_PKT_Q7_V1_8822C << BIT_SHIFT_HEAD_PKT_Q7_V1_8822C)\n#define BIT_CLEAR_HEAD_PKT_Q7_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8822C))\n#define BIT_GET_HEAD_PKT_Q7_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8822C) &                             \\\n\t BIT_MASK_HEAD_PKT_Q7_V1_8822C)\n#define BIT_SET_HEAD_PKT_Q7_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_HEAD_PKT_Q7_V1_8822C(x) | BIT_HEAD_PKT_Q7_V1_8822C(v))\n\n/* 2 REG_WMAC_LBK_BUF_HD_V1_8822C */\n\n#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C 0\n#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C 0xfff\n#define BIT_WMAC_LBK_BUF_HEAD_V1_8822C(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C)                           \\\n\t << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C)\n#define BITS_WMAC_LBK_BUF_HEAD_V1_8822C                                        \\\n\t(BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C                                   \\\n\t << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C)\n#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822C(x)                                \\\n\t((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8822C))\n#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C) &                       \\\n\t BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C)\n#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8822C(x, v)                               \\\n\t(BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822C(x) |                             \\\n\t BIT_WMAC_LBK_BUF_HEAD_V1_8822C(v))\n\n/* 2 REG_MGQ_BDNY_V1_8822C */\n\n#define BIT_SHIFT_MGQ_PGBNDY_V1_8822C 0\n#define BIT_MASK_MGQ_PGBNDY_V1_8822C 0xfff\n#define BIT_MGQ_PGBNDY_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_PGBNDY_V1_8822C) << BIT_SHIFT_MGQ_PGBNDY_V1_8822C)\n#define BITS_MGQ_PGBNDY_V1_8822C                                               \\\n\t(BIT_MASK_MGQ_PGBNDY_V1_8822C << BIT_SHIFT_MGQ_PGBNDY_V1_8822C)\n#define BIT_CLEAR_MGQ_PGBNDY_V1_8822C(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8822C))\n#define BIT_GET_MGQ_PGBNDY_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8822C) & BIT_MASK_MGQ_PGBNDY_V1_8822C)\n#define BIT_SET_MGQ_PGBNDY_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_PGBNDY_V1_8822C(x) | BIT_MGQ_PGBNDY_V1_8822C(v))\n\n/* 2 REG_TXRPT_CTRL_8822C */\n\n#define BIT_SHIFT_TRXRPT_TIMER_TH_8822C 24\n#define BIT_MASK_TRXRPT_TIMER_TH_8822C 0xff\n#define BIT_TRXRPT_TIMER_TH_8822C(x)                                           \\\n\t(((x) & BIT_MASK_TRXRPT_TIMER_TH_8822C)                                \\\n\t << BIT_SHIFT_TRXRPT_TIMER_TH_8822C)\n#define BITS_TRXRPT_TIMER_TH_8822C                                             \\\n\t(BIT_MASK_TRXRPT_TIMER_TH_8822C << BIT_SHIFT_TRXRPT_TIMER_TH_8822C)\n#define BIT_CLEAR_TRXRPT_TIMER_TH_8822C(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8822C))\n#define BIT_GET_TRXRPT_TIMER_TH_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8822C) &                            \\\n\t BIT_MASK_TRXRPT_TIMER_TH_8822C)\n#define BIT_SET_TRXRPT_TIMER_TH_8822C(x, v)                                    \\\n\t(BIT_CLEAR_TRXRPT_TIMER_TH_8822C(x) | BIT_TRXRPT_TIMER_TH_8822C(v))\n\n#define BIT_SHIFT_TRXRPT_LEN_TH_8822C 16\n#define BIT_MASK_TRXRPT_LEN_TH_8822C 0xff\n#define BIT_TRXRPT_LEN_TH_8822C(x)                                             \\\n\t(((x) & BIT_MASK_TRXRPT_LEN_TH_8822C) << BIT_SHIFT_TRXRPT_LEN_TH_8822C)\n#define BITS_TRXRPT_LEN_TH_8822C                                               \\\n\t(BIT_MASK_TRXRPT_LEN_TH_8822C << BIT_SHIFT_TRXRPT_LEN_TH_8822C)\n#define BIT_CLEAR_TRXRPT_LEN_TH_8822C(x) ((x) & (~BITS_TRXRPT_LEN_TH_8822C))\n#define BIT_GET_TRXRPT_LEN_TH_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8822C) & BIT_MASK_TRXRPT_LEN_TH_8822C)\n#define BIT_SET_TRXRPT_LEN_TH_8822C(x, v)                                      \\\n\t(BIT_CLEAR_TRXRPT_LEN_TH_8822C(x) | BIT_TRXRPT_LEN_TH_8822C(v))\n\n#define BIT_SHIFT_TRXRPT_READ_PTR_8822C 8\n#define BIT_MASK_TRXRPT_READ_PTR_8822C 0xff\n#define BIT_TRXRPT_READ_PTR_8822C(x)                                           \\\n\t(((x) & BIT_MASK_TRXRPT_READ_PTR_8822C)                                \\\n\t << BIT_SHIFT_TRXRPT_READ_PTR_8822C)\n#define BITS_TRXRPT_READ_PTR_8822C                                             \\\n\t(BIT_MASK_TRXRPT_READ_PTR_8822C << BIT_SHIFT_TRXRPT_READ_PTR_8822C)\n#define BIT_CLEAR_TRXRPT_READ_PTR_8822C(x) ((x) & (~BITS_TRXRPT_READ_PTR_8822C))\n#define BIT_GET_TRXRPT_READ_PTR_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8822C) &                            \\\n\t BIT_MASK_TRXRPT_READ_PTR_8822C)\n#define BIT_SET_TRXRPT_READ_PTR_8822C(x, v)                                    \\\n\t(BIT_CLEAR_TRXRPT_READ_PTR_8822C(x) | BIT_TRXRPT_READ_PTR_8822C(v))\n\n#define BIT_SHIFT_TRXRPT_WRITE_PTR_8822C 0\n#define BIT_MASK_TRXRPT_WRITE_PTR_8822C 0xff\n#define BIT_TRXRPT_WRITE_PTR_8822C(x)                                          \\\n\t(((x) & BIT_MASK_TRXRPT_WRITE_PTR_8822C)                               \\\n\t << BIT_SHIFT_TRXRPT_WRITE_PTR_8822C)\n#define BITS_TRXRPT_WRITE_PTR_8822C                                            \\\n\t(BIT_MASK_TRXRPT_WRITE_PTR_8822C << BIT_SHIFT_TRXRPT_WRITE_PTR_8822C)\n#define BIT_CLEAR_TRXRPT_WRITE_PTR_8822C(x)                                    \\\n\t((x) & (~BITS_TRXRPT_WRITE_PTR_8822C))\n#define BIT_GET_TRXRPT_WRITE_PTR_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8822C) &                           \\\n\t BIT_MASK_TRXRPT_WRITE_PTR_8822C)\n#define BIT_SET_TRXRPT_WRITE_PTR_8822C(x, v)                                   \\\n\t(BIT_CLEAR_TRXRPT_WRITE_PTR_8822C(x) | BIT_TRXRPT_WRITE_PTR_8822C(v))\n\n/* 2 REG_INIRTS_RATE_SEL_8822C */\n#define BIT_LEAG_RTS_BW_DUP_8822C BIT(5)\n\n/* 2 REG_BASIC_CFEND_RATE_8822C */\n\n#define BIT_SHIFT_BASIC_CFEND_RATE_8822C 0\n#define BIT_MASK_BASIC_CFEND_RATE_8822C 0x1f\n#define BIT_BASIC_CFEND_RATE_8822C(x)                                          \\\n\t(((x) & BIT_MASK_BASIC_CFEND_RATE_8822C)                               \\\n\t << BIT_SHIFT_BASIC_CFEND_RATE_8822C)\n#define BITS_BASIC_CFEND_RATE_8822C                                            \\\n\t(BIT_MASK_BASIC_CFEND_RATE_8822C << BIT_SHIFT_BASIC_CFEND_RATE_8822C)\n#define BIT_CLEAR_BASIC_CFEND_RATE_8822C(x)                                    \\\n\t((x) & (~BITS_BASIC_CFEND_RATE_8822C))\n#define BIT_GET_BASIC_CFEND_RATE_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8822C) &                           \\\n\t BIT_MASK_BASIC_CFEND_RATE_8822C)\n#define BIT_SET_BASIC_CFEND_RATE_8822C(x, v)                                   \\\n\t(BIT_CLEAR_BASIC_CFEND_RATE_8822C(x) | BIT_BASIC_CFEND_RATE_8822C(v))\n\n/* 2 REG_STBC_CFEND_RATE_8822C */\n\n#define BIT_SHIFT_STBC_CFEND_RATE_8822C 0\n#define BIT_MASK_STBC_CFEND_RATE_8822C 0x1f\n#define BIT_STBC_CFEND_RATE_8822C(x)                                           \\\n\t(((x) & BIT_MASK_STBC_CFEND_RATE_8822C)                                \\\n\t << BIT_SHIFT_STBC_CFEND_RATE_8822C)\n#define BITS_STBC_CFEND_RATE_8822C                                             \\\n\t(BIT_MASK_STBC_CFEND_RATE_8822C << BIT_SHIFT_STBC_CFEND_RATE_8822C)\n#define BIT_CLEAR_STBC_CFEND_RATE_8822C(x) ((x) & (~BITS_STBC_CFEND_RATE_8822C))\n#define BIT_GET_STBC_CFEND_RATE_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_STBC_CFEND_RATE_8822C) &                            \\\n\t BIT_MASK_STBC_CFEND_RATE_8822C)\n#define BIT_SET_STBC_CFEND_RATE_8822C(x, v)                                    \\\n\t(BIT_CLEAR_STBC_CFEND_RATE_8822C(x) | BIT_STBC_CFEND_RATE_8822C(v))\n\n/* 2 REG_DATA_SC_8822C */\n\n#define BIT_SHIFT_TXSC_40M_8822C 4\n#define BIT_MASK_TXSC_40M_8822C 0xf\n#define BIT_TXSC_40M_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_TXSC_40M_8822C) << BIT_SHIFT_TXSC_40M_8822C)\n#define BITS_TXSC_40M_8822C                                                    \\\n\t(BIT_MASK_TXSC_40M_8822C << BIT_SHIFT_TXSC_40M_8822C)\n#define BIT_CLEAR_TXSC_40M_8822C(x) ((x) & (~BITS_TXSC_40M_8822C))\n#define BIT_GET_TXSC_40M_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXSC_40M_8822C) & BIT_MASK_TXSC_40M_8822C)\n#define BIT_SET_TXSC_40M_8822C(x, v)                                           \\\n\t(BIT_CLEAR_TXSC_40M_8822C(x) | BIT_TXSC_40M_8822C(v))\n\n#define BIT_SHIFT_TXSC_20M_8822C 0\n#define BIT_MASK_TXSC_20M_8822C 0xf\n#define BIT_TXSC_20M_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_TXSC_20M_8822C) << BIT_SHIFT_TXSC_20M_8822C)\n#define BITS_TXSC_20M_8822C                                                    \\\n\t(BIT_MASK_TXSC_20M_8822C << BIT_SHIFT_TXSC_20M_8822C)\n#define BIT_CLEAR_TXSC_20M_8822C(x) ((x) & (~BITS_TXSC_20M_8822C))\n#define BIT_GET_TXSC_20M_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXSC_20M_8822C) & BIT_MASK_TXSC_20M_8822C)\n#define BIT_SET_TXSC_20M_8822C(x, v)                                           \\\n\t(BIT_CLEAR_TXSC_20M_8822C(x) | BIT_TXSC_20M_8822C(v))\n\n/* 2 REG_MACID_SLEEP3_8822C */\n\n#define BIT_SHIFT_MACID127_96_PKTSLEEP_8822C 0\n#define BIT_MASK_MACID127_96_PKTSLEEP_8822C 0xffffffffL\n#define BIT_MACID127_96_PKTSLEEP_8822C(x)                                      \\\n\t(((x) & BIT_MASK_MACID127_96_PKTSLEEP_8822C)                           \\\n\t << BIT_SHIFT_MACID127_96_PKTSLEEP_8822C)\n#define BITS_MACID127_96_PKTSLEEP_8822C                                        \\\n\t(BIT_MASK_MACID127_96_PKTSLEEP_8822C                                   \\\n\t << BIT_SHIFT_MACID127_96_PKTSLEEP_8822C)\n#define BIT_CLEAR_MACID127_96_PKTSLEEP_8822C(x)                                \\\n\t((x) & (~BITS_MACID127_96_PKTSLEEP_8822C))\n#define BIT_GET_MACID127_96_PKTSLEEP_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8822C) &                       \\\n\t BIT_MASK_MACID127_96_PKTSLEEP_8822C)\n#define BIT_SET_MACID127_96_PKTSLEEP_8822C(x, v)                               \\\n\t(BIT_CLEAR_MACID127_96_PKTSLEEP_8822C(x) |                             \\\n\t BIT_MACID127_96_PKTSLEEP_8822C(v))\n\n/* 2 REG_MACID_SLEEP1_8822C */\n\n#define BIT_SHIFT_MACID63_32_PKTSLEEP_8822C 0\n#define BIT_MASK_MACID63_32_PKTSLEEP_8822C 0xffffffffL\n#define BIT_MACID63_32_PKTSLEEP_8822C(x)                                       \\\n\t(((x) & BIT_MASK_MACID63_32_PKTSLEEP_8822C)                            \\\n\t << BIT_SHIFT_MACID63_32_PKTSLEEP_8822C)\n#define BITS_MACID63_32_PKTSLEEP_8822C                                         \\\n\t(BIT_MASK_MACID63_32_PKTSLEEP_8822C                                    \\\n\t << BIT_SHIFT_MACID63_32_PKTSLEEP_8822C)\n#define BIT_CLEAR_MACID63_32_PKTSLEEP_8822C(x)                                 \\\n\t((x) & (~BITS_MACID63_32_PKTSLEEP_8822C))\n#define BIT_GET_MACID63_32_PKTSLEEP_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8822C) &                        \\\n\t BIT_MASK_MACID63_32_PKTSLEEP_8822C)\n#define BIT_SET_MACID63_32_PKTSLEEP_8822C(x, v)                                \\\n\t(BIT_CLEAR_MACID63_32_PKTSLEEP_8822C(x) |                              \\\n\t BIT_MACID63_32_PKTSLEEP_8822C(v))\n\n/* 2 REG_ARFR2_V1_8822C */\n\n#define BIT_SHIFT_ARFRL2_8822C 0\n#define BIT_MASK_ARFRL2_8822C 0xffffffffL\n#define BIT_ARFRL2_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRL2_8822C) << BIT_SHIFT_ARFRL2_8822C)\n#define BITS_ARFRL2_8822C (BIT_MASK_ARFRL2_8822C << BIT_SHIFT_ARFRL2_8822C)\n#define BIT_CLEAR_ARFRL2_8822C(x) ((x) & (~BITS_ARFRL2_8822C))\n#define BIT_GET_ARFRL2_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRL2_8822C) & BIT_MASK_ARFRL2_8822C)\n#define BIT_SET_ARFRL2_8822C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRL2_8822C(x) | BIT_ARFRL2_8822C(v))\n\n/* 2 REG_ARFRH2_V1_8822C */\n\n#define BIT_SHIFT_ARFRH2_8822C 0\n#define BIT_MASK_ARFRH2_8822C 0xffffffffL\n#define BIT_ARFRH2_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRH2_8822C) << BIT_SHIFT_ARFRH2_8822C)\n#define BITS_ARFRH2_8822C (BIT_MASK_ARFRH2_8822C << BIT_SHIFT_ARFRH2_8822C)\n#define BIT_CLEAR_ARFRH2_8822C(x) ((x) & (~BITS_ARFRH2_8822C))\n#define BIT_GET_ARFRH2_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRH2_8822C) & BIT_MASK_ARFRH2_8822C)\n#define BIT_SET_ARFRH2_8822C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRH2_8822C(x) | BIT_ARFRH2_8822C(v))\n\n/* 2 REG_ARFR3_V1_8822C */\n\n#define BIT_SHIFT_ARFRL3_8822C 0\n#define BIT_MASK_ARFRL3_8822C 0xffffffffL\n#define BIT_ARFRL3_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRL3_8822C) << BIT_SHIFT_ARFRL3_8822C)\n#define BITS_ARFRL3_8822C (BIT_MASK_ARFRL3_8822C << BIT_SHIFT_ARFRL3_8822C)\n#define BIT_CLEAR_ARFRL3_8822C(x) ((x) & (~BITS_ARFRL3_8822C))\n#define BIT_GET_ARFRL3_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRL3_8822C) & BIT_MASK_ARFRL3_8822C)\n#define BIT_SET_ARFRL3_8822C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRL3_8822C(x) | BIT_ARFRL3_8822C(v))\n\n/* 2 REG_ARFRH3_V1_8822C */\n\n#define BIT_SHIFT_ARFRH3_8822C 0\n#define BIT_MASK_ARFRH3_8822C 0xffffffffL\n#define BIT_ARFRH3_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRH3_8822C) << BIT_SHIFT_ARFRH3_8822C)\n#define BITS_ARFRH3_8822C (BIT_MASK_ARFRH3_8822C << BIT_SHIFT_ARFRH3_8822C)\n#define BIT_CLEAR_ARFRH3_8822C(x) ((x) & (~BITS_ARFRH3_8822C))\n#define BIT_GET_ARFRH3_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRH3_8822C) & BIT_MASK_ARFRH3_8822C)\n#define BIT_SET_ARFRH3_8822C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRH3_8822C(x) | BIT_ARFRH3_8822C(v))\n\n/* 2 REG_ARFR4_8822C */\n\n#define BIT_SHIFT_ARFRL4_8822C 0\n#define BIT_MASK_ARFRL4_8822C 0xffffffffL\n#define BIT_ARFRL4_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRL4_8822C) << BIT_SHIFT_ARFRL4_8822C)\n#define BITS_ARFRL4_8822C (BIT_MASK_ARFRL4_8822C << BIT_SHIFT_ARFRL4_8822C)\n#define BIT_CLEAR_ARFRL4_8822C(x) ((x) & (~BITS_ARFRL4_8822C))\n#define BIT_GET_ARFRL4_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRL4_8822C) & BIT_MASK_ARFRL4_8822C)\n#define BIT_SET_ARFRL4_8822C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRL4_8822C(x) | BIT_ARFRL4_8822C(v))\n\n/* 2 REG_ARFRH4_8822C */\n\n#define BIT_SHIFT_ARFRH4_8822C 0\n#define BIT_MASK_ARFRH4_8822C 0xffffffffL\n#define BIT_ARFRH4_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRH4_8822C) << BIT_SHIFT_ARFRH4_8822C)\n#define BITS_ARFRH4_8822C (BIT_MASK_ARFRH4_8822C << BIT_SHIFT_ARFRH4_8822C)\n#define BIT_CLEAR_ARFRH4_8822C(x) ((x) & (~BITS_ARFRH4_8822C))\n#define BIT_GET_ARFRH4_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRH4_8822C) & BIT_MASK_ARFRH4_8822C)\n#define BIT_SET_ARFRH4_8822C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRH4_8822C(x) | BIT_ARFRH4_8822C(v))\n\n/* 2 REG_ARFR5_8822C */\n\n#define BIT_SHIFT_ARFRL5_8822C 0\n#define BIT_MASK_ARFRL5_8822C 0xffffffffL\n#define BIT_ARFRL5_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRL5_8822C) << BIT_SHIFT_ARFRL5_8822C)\n#define BITS_ARFRL5_8822C (BIT_MASK_ARFRL5_8822C << BIT_SHIFT_ARFRL5_8822C)\n#define BIT_CLEAR_ARFRL5_8822C(x) ((x) & (~BITS_ARFRL5_8822C))\n#define BIT_GET_ARFRL5_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRL5_8822C) & BIT_MASK_ARFRL5_8822C)\n#define BIT_SET_ARFRL5_8822C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRL5_8822C(x) | BIT_ARFRL5_8822C(v))\n\n/* 2 REG_ARFRH5_8822C */\n\n#define BIT_SHIFT_ARFRH5_8822C 0\n#define BIT_MASK_ARFRH5_8822C 0xffffffffL\n#define BIT_ARFRH5_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_ARFRH5_8822C) << BIT_SHIFT_ARFRH5_8822C)\n#define BITS_ARFRH5_8822C (BIT_MASK_ARFRH5_8822C << BIT_SHIFT_ARFRH5_8822C)\n#define BIT_CLEAR_ARFRH5_8822C(x) ((x) & (~BITS_ARFRH5_8822C))\n#define BIT_GET_ARFRH5_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_ARFRH5_8822C) & BIT_MASK_ARFRH5_8822C)\n#define BIT_SET_ARFRH5_8822C(x, v)                                             \\\n\t(BIT_CLEAR_ARFRH5_8822C(x) | BIT_ARFRH5_8822C(v))\n\n/* 2 REG_TXRPT_START_OFFSET_8822C */\n\n#define BIT_SHIFT_MACID_MURATE_OFFSET_8822C 24\n#define BIT_MASK_MACID_MURATE_OFFSET_8822C 0xff\n#define BIT_MACID_MURATE_OFFSET_8822C(x)                                       \\\n\t(((x) & BIT_MASK_MACID_MURATE_OFFSET_8822C)                            \\\n\t << BIT_SHIFT_MACID_MURATE_OFFSET_8822C)\n#define BITS_MACID_MURATE_OFFSET_8822C                                         \\\n\t(BIT_MASK_MACID_MURATE_OFFSET_8822C                                    \\\n\t << BIT_SHIFT_MACID_MURATE_OFFSET_8822C)\n#define BIT_CLEAR_MACID_MURATE_OFFSET_8822C(x)                                 \\\n\t((x) & (~BITS_MACID_MURATE_OFFSET_8822C))\n#define BIT_GET_MACID_MURATE_OFFSET_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_MACID_MURATE_OFFSET_8822C) &                        \\\n\t BIT_MASK_MACID_MURATE_OFFSET_8822C)\n#define BIT_SET_MACID_MURATE_OFFSET_8822C(x, v)                                \\\n\t(BIT_CLEAR_MACID_MURATE_OFFSET_8822C(x) |                              \\\n\t BIT_MACID_MURATE_OFFSET_8822C(v))\n\n#define BIT_SHIFT_TXRPT_MISS_COUNT_8822C 17\n#define BIT_MASK_TXRPT_MISS_COUNT_8822C 0x7\n#define BIT_TXRPT_MISS_COUNT_8822C(x)                                          \\\n\t(((x) & BIT_MASK_TXRPT_MISS_COUNT_8822C)                               \\\n\t << BIT_SHIFT_TXRPT_MISS_COUNT_8822C)\n#define BITS_TXRPT_MISS_COUNT_8822C                                            \\\n\t(BIT_MASK_TXRPT_MISS_COUNT_8822C << BIT_SHIFT_TXRPT_MISS_COUNT_8822C)\n#define BIT_CLEAR_TXRPT_MISS_COUNT_8822C(x)                                    \\\n\t((x) & (~BITS_TXRPT_MISS_COUNT_8822C))\n#define BIT_GET_TXRPT_MISS_COUNT_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_TXRPT_MISS_COUNT_8822C) &                           \\\n\t BIT_MASK_TXRPT_MISS_COUNT_8822C)\n#define BIT_SET_TXRPT_MISS_COUNT_8822C(x, v)                                   \\\n\t(BIT_CLEAR_TXRPT_MISS_COUNT_8822C(x) | BIT_TXRPT_MISS_COUNT_8822C(v))\n\n#define BIT_RPTFIFO_SIZE_OPT_8822C BIT(16)\n\n#define BIT_SHIFT_MACID_CTRL_OFFSET_8822C 8\n#define BIT_MASK_MACID_CTRL_OFFSET_8822C 0xff\n#define BIT_MACID_CTRL_OFFSET_8822C(x)                                         \\\n\t(((x) & BIT_MASK_MACID_CTRL_OFFSET_8822C)                              \\\n\t << BIT_SHIFT_MACID_CTRL_OFFSET_8822C)\n#define BITS_MACID_CTRL_OFFSET_8822C                                           \\\n\t(BIT_MASK_MACID_CTRL_OFFSET_8822C << BIT_SHIFT_MACID_CTRL_OFFSET_8822C)\n#define BIT_CLEAR_MACID_CTRL_OFFSET_8822C(x)                                   \\\n\t((x) & (~BITS_MACID_CTRL_OFFSET_8822C))\n#define BIT_GET_MACID_CTRL_OFFSET_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8822C) &                          \\\n\t BIT_MASK_MACID_CTRL_OFFSET_8822C)\n#define BIT_SET_MACID_CTRL_OFFSET_8822C(x, v)                                  \\\n\t(BIT_CLEAR_MACID_CTRL_OFFSET_8822C(x) | BIT_MACID_CTRL_OFFSET_8822C(v))\n\n#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C 0\n#define BIT_MASK_AMPDU_TXRPT_OFFSET_8822C 0xff\n#define BIT_AMPDU_TXRPT_OFFSET_8822C(x)                                        \\\n\t(((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822C)                             \\\n\t << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C)\n#define BITS_AMPDU_TXRPT_OFFSET_8822C                                          \\\n\t(BIT_MASK_AMPDU_TXRPT_OFFSET_8822C                                     \\\n\t << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C)\n#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822C(x)                                  \\\n\t((x) & (~BITS_AMPDU_TXRPT_OFFSET_8822C))\n#define BIT_GET_AMPDU_TXRPT_OFFSET_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C) &                         \\\n\t BIT_MASK_AMPDU_TXRPT_OFFSET_8822C)\n#define BIT_SET_AMPDU_TXRPT_OFFSET_8822C(x, v)                                 \\\n\t(BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822C(x) |                               \\\n\t BIT_AMPDU_TXRPT_OFFSET_8822C(v))\n\n/* 2 REG_POWER_STAGE1_8822C */\n#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8822C BIT(31)\n#define BIT_PTA_WL_PRI_MASK_BCNQ_8822C BIT(30)\n#define BIT_PTA_WL_PRI_MASK_HIQ_8822C BIT(29)\n#define BIT_PTA_WL_PRI_MASK_MGQ_8822C BIT(28)\n#define BIT_PTA_WL_PRI_MASK_BK_8822C BIT(27)\n#define BIT_PTA_WL_PRI_MASK_BE_8822C BIT(26)\n#define BIT_PTA_WL_PRI_MASK_VI_8822C BIT(25)\n#define BIT_PTA_WL_PRI_MASK_VO_8822C BIT(24)\n\n#define BIT_SHIFT_POWER_STAGE1_8822C 0\n#define BIT_MASK_POWER_STAGE1_8822C 0xffffff\n#define BIT_POWER_STAGE1_8822C(x)                                              \\\n\t(((x) & BIT_MASK_POWER_STAGE1_8822C) << BIT_SHIFT_POWER_STAGE1_8822C)\n#define BITS_POWER_STAGE1_8822C                                                \\\n\t(BIT_MASK_POWER_STAGE1_8822C << BIT_SHIFT_POWER_STAGE1_8822C)\n#define BIT_CLEAR_POWER_STAGE1_8822C(x) ((x) & (~BITS_POWER_STAGE1_8822C))\n#define BIT_GET_POWER_STAGE1_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_POWER_STAGE1_8822C) & BIT_MASK_POWER_STAGE1_8822C)\n#define BIT_SET_POWER_STAGE1_8822C(x, v)                                       \\\n\t(BIT_CLEAR_POWER_STAGE1_8822C(x) | BIT_POWER_STAGE1_8822C(v))\n\n/* 2 REG_POWER_STAGE2_8822C */\n#define BIT__R_CTRL_PKT_POW_ADJ_8822C BIT(24)\n\n#define BIT_SHIFT_POWER_STAGE2_8822C 0\n#define BIT_MASK_POWER_STAGE2_8822C 0xffffff\n#define BIT_POWER_STAGE2_8822C(x)                                              \\\n\t(((x) & BIT_MASK_POWER_STAGE2_8822C) << BIT_SHIFT_POWER_STAGE2_8822C)\n#define BITS_POWER_STAGE2_8822C                                                \\\n\t(BIT_MASK_POWER_STAGE2_8822C << BIT_SHIFT_POWER_STAGE2_8822C)\n#define BIT_CLEAR_POWER_STAGE2_8822C(x) ((x) & (~BITS_POWER_STAGE2_8822C))\n#define BIT_GET_POWER_STAGE2_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_POWER_STAGE2_8822C) & BIT_MASK_POWER_STAGE2_8822C)\n#define BIT_SET_POWER_STAGE2_8822C(x, v)                                       \\\n\t(BIT_CLEAR_POWER_STAGE2_8822C(x) | BIT_POWER_STAGE2_8822C(v))\n\n/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8822C */\n\n#define BIT_SHIFT_PAD_NUM_THRES_8822C 24\n#define BIT_MASK_PAD_NUM_THRES_8822C 0x3f\n#define BIT_PAD_NUM_THRES_8822C(x)                                             \\\n\t(((x) & BIT_MASK_PAD_NUM_THRES_8822C) << BIT_SHIFT_PAD_NUM_THRES_8822C)\n#define BITS_PAD_NUM_THRES_8822C                                               \\\n\t(BIT_MASK_PAD_NUM_THRES_8822C << BIT_SHIFT_PAD_NUM_THRES_8822C)\n#define BIT_CLEAR_PAD_NUM_THRES_8822C(x) ((x) & (~BITS_PAD_NUM_THRES_8822C))\n#define BIT_GET_PAD_NUM_THRES_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PAD_NUM_THRES_8822C) & BIT_MASK_PAD_NUM_THRES_8822C)\n#define BIT_SET_PAD_NUM_THRES_8822C(x, v)                                      \\\n\t(BIT_CLEAR_PAD_NUM_THRES_8822C(x) | BIT_PAD_NUM_THRES_8822C(v))\n\n#define BIT_R_DMA_THIS_QUEUE_BK_8822C BIT(23)\n#define BIT_R_DMA_THIS_QUEUE_BE_8822C BIT(22)\n#define BIT_R_DMA_THIS_QUEUE_VI_8822C BIT(21)\n#define BIT_R_DMA_THIS_QUEUE_VO_8822C BIT(20)\n\n#define BIT_SHIFT_R_TOTAL_LEN_TH_8822C 8\n#define BIT_MASK_R_TOTAL_LEN_TH_8822C 0xfff\n#define BIT_R_TOTAL_LEN_TH_8822C(x)                                            \\\n\t(((x) & BIT_MASK_R_TOTAL_LEN_TH_8822C)                                 \\\n\t << BIT_SHIFT_R_TOTAL_LEN_TH_8822C)\n#define BITS_R_TOTAL_LEN_TH_8822C                                              \\\n\t(BIT_MASK_R_TOTAL_LEN_TH_8822C << BIT_SHIFT_R_TOTAL_LEN_TH_8822C)\n#define BIT_CLEAR_R_TOTAL_LEN_TH_8822C(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8822C))\n#define BIT_GET_R_TOTAL_LEN_TH_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8822C) &                             \\\n\t BIT_MASK_R_TOTAL_LEN_TH_8822C)\n#define BIT_SET_R_TOTAL_LEN_TH_8822C(x, v)                                     \\\n\t(BIT_CLEAR_R_TOTAL_LEN_TH_8822C(x) | BIT_R_TOTAL_LEN_TH_8822C(v))\n\n#define BIT_EN_NEW_EARLY_8822C BIT(7)\n#define BIT_PRE_TX_CMD_8822C BIT(6)\n\n#define BIT_SHIFT_NUM_SCL_EN_8822C 4\n#define BIT_MASK_NUM_SCL_EN_8822C 0x3\n#define BIT_NUM_SCL_EN_8822C(x)                                                \\\n\t(((x) & BIT_MASK_NUM_SCL_EN_8822C) << BIT_SHIFT_NUM_SCL_EN_8822C)\n#define BITS_NUM_SCL_EN_8822C                                                  \\\n\t(BIT_MASK_NUM_SCL_EN_8822C << BIT_SHIFT_NUM_SCL_EN_8822C)\n#define BIT_CLEAR_NUM_SCL_EN_8822C(x) ((x) & (~BITS_NUM_SCL_EN_8822C))\n#define BIT_GET_NUM_SCL_EN_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_NUM_SCL_EN_8822C) & BIT_MASK_NUM_SCL_EN_8822C)\n#define BIT_SET_NUM_SCL_EN_8822C(x, v)                                         \\\n\t(BIT_CLEAR_NUM_SCL_EN_8822C(x) | BIT_NUM_SCL_EN_8822C(v))\n\n#define BIT_BK_EN_8822C BIT(3)\n#define BIT_BE_EN_8822C BIT(2)\n#define BIT_VI_EN_8822C BIT(1)\n#define BIT_VO_EN_8822C BIT(0)\n\n/* 2 REG_PKT_LIFE_TIME_8822C */\n\n#define BIT_SHIFT_PKT_LIFTIME_BEBK_8822C 16\n#define BIT_MASK_PKT_LIFTIME_BEBK_8822C 0xffff\n#define BIT_PKT_LIFTIME_BEBK_8822C(x)                                          \\\n\t(((x) & BIT_MASK_PKT_LIFTIME_BEBK_8822C)                               \\\n\t << BIT_SHIFT_PKT_LIFTIME_BEBK_8822C)\n#define BITS_PKT_LIFTIME_BEBK_8822C                                            \\\n\t(BIT_MASK_PKT_LIFTIME_BEBK_8822C << BIT_SHIFT_PKT_LIFTIME_BEBK_8822C)\n#define BIT_CLEAR_PKT_LIFTIME_BEBK_8822C(x)                                    \\\n\t((x) & (~BITS_PKT_LIFTIME_BEBK_8822C))\n#define BIT_GET_PKT_LIFTIME_BEBK_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8822C) &                           \\\n\t BIT_MASK_PKT_LIFTIME_BEBK_8822C)\n#define BIT_SET_PKT_LIFTIME_BEBK_8822C(x, v)                                   \\\n\t(BIT_CLEAR_PKT_LIFTIME_BEBK_8822C(x) | BIT_PKT_LIFTIME_BEBK_8822C(v))\n\n#define BIT_SHIFT_PKT_LIFTIME_VOVI_8822C 0\n#define BIT_MASK_PKT_LIFTIME_VOVI_8822C 0xffff\n#define BIT_PKT_LIFTIME_VOVI_8822C(x)                                          \\\n\t(((x) & BIT_MASK_PKT_LIFTIME_VOVI_8822C)                               \\\n\t << BIT_SHIFT_PKT_LIFTIME_VOVI_8822C)\n#define BITS_PKT_LIFTIME_VOVI_8822C                                            \\\n\t(BIT_MASK_PKT_LIFTIME_VOVI_8822C << BIT_SHIFT_PKT_LIFTIME_VOVI_8822C)\n#define BIT_CLEAR_PKT_LIFTIME_VOVI_8822C(x)                                    \\\n\t((x) & (~BITS_PKT_LIFTIME_VOVI_8822C))\n#define BIT_GET_PKT_LIFTIME_VOVI_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8822C) &                           \\\n\t BIT_MASK_PKT_LIFTIME_VOVI_8822C)\n#define BIT_SET_PKT_LIFTIME_VOVI_8822C(x, v)                                   \\\n\t(BIT_CLEAR_PKT_LIFTIME_VOVI_8822C(x) | BIT_PKT_LIFTIME_VOVI_8822C(v))\n\n/* 2 REG_STBC_SETTING_8822C */\n\n#define BIT_SHIFT_CDEND_TXTIME_L_8822C 4\n#define BIT_MASK_CDEND_TXTIME_L_8822C 0xf\n#define BIT_CDEND_TXTIME_L_8822C(x)                                            \\\n\t(((x) & BIT_MASK_CDEND_TXTIME_L_8822C)                                 \\\n\t << BIT_SHIFT_CDEND_TXTIME_L_8822C)\n#define BITS_CDEND_TXTIME_L_8822C                                              \\\n\t(BIT_MASK_CDEND_TXTIME_L_8822C << BIT_SHIFT_CDEND_TXTIME_L_8822C)\n#define BIT_CLEAR_CDEND_TXTIME_L_8822C(x) ((x) & (~BITS_CDEND_TXTIME_L_8822C))\n#define BIT_GET_CDEND_TXTIME_L_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_CDEND_TXTIME_L_8822C) &                             \\\n\t BIT_MASK_CDEND_TXTIME_L_8822C)\n#define BIT_SET_CDEND_TXTIME_L_8822C(x, v)                                     \\\n\t(BIT_CLEAR_CDEND_TXTIME_L_8822C(x) | BIT_CDEND_TXTIME_L_8822C(v))\n\n#define BIT_SHIFT_NESS_8822C 2\n#define BIT_MASK_NESS_8822C 0x3\n#define BIT_NESS_8822C(x) (((x) & BIT_MASK_NESS_8822C) << BIT_SHIFT_NESS_8822C)\n#define BITS_NESS_8822C (BIT_MASK_NESS_8822C << BIT_SHIFT_NESS_8822C)\n#define BIT_CLEAR_NESS_8822C(x) ((x) & (~BITS_NESS_8822C))\n#define BIT_GET_NESS_8822C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_NESS_8822C) & BIT_MASK_NESS_8822C)\n#define BIT_SET_NESS_8822C(x, v) (BIT_CLEAR_NESS_8822C(x) | BIT_NESS_8822C(v))\n\n#define BIT_SHIFT_STBC_CFEND_8822C 0\n#define BIT_MASK_STBC_CFEND_8822C 0x3\n#define BIT_STBC_CFEND_8822C(x)                                                \\\n\t(((x) & BIT_MASK_STBC_CFEND_8822C) << BIT_SHIFT_STBC_CFEND_8822C)\n#define BITS_STBC_CFEND_8822C                                                  \\\n\t(BIT_MASK_STBC_CFEND_8822C << BIT_SHIFT_STBC_CFEND_8822C)\n#define BIT_CLEAR_STBC_CFEND_8822C(x) ((x) & (~BITS_STBC_CFEND_8822C))\n#define BIT_GET_STBC_CFEND_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_STBC_CFEND_8822C) & BIT_MASK_STBC_CFEND_8822C)\n#define BIT_SET_STBC_CFEND_8822C(x, v)                                         \\\n\t(BIT_CLEAR_STBC_CFEND_8822C(x) | BIT_STBC_CFEND_8822C(v))\n\n/* 2 REG_STBC_SETTING2_8822C */\n\n#define BIT_SHIFT_CDEND_TXTIME_H_8822C 0\n#define BIT_MASK_CDEND_TXTIME_H_8822C 0x1f\n#define BIT_CDEND_TXTIME_H_8822C(x)                                            \\\n\t(((x) & BIT_MASK_CDEND_TXTIME_H_8822C)                                 \\\n\t << BIT_SHIFT_CDEND_TXTIME_H_8822C)\n#define BITS_CDEND_TXTIME_H_8822C                                              \\\n\t(BIT_MASK_CDEND_TXTIME_H_8822C << BIT_SHIFT_CDEND_TXTIME_H_8822C)\n#define BIT_CLEAR_CDEND_TXTIME_H_8822C(x) ((x) & (~BITS_CDEND_TXTIME_H_8822C))\n#define BIT_GET_CDEND_TXTIME_H_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_CDEND_TXTIME_H_8822C) &                             \\\n\t BIT_MASK_CDEND_TXTIME_H_8822C)\n#define BIT_SET_CDEND_TXTIME_H_8822C(x, v)                                     \\\n\t(BIT_CLEAR_CDEND_TXTIME_H_8822C(x) | BIT_CDEND_TXTIME_H_8822C(v))\n\n/* 2 REG_QUEUE_CTRL_8822C */\n#define BIT_FORCE_RND_PRI_8822C BIT(6)\n#define BIT_PTA_EDCCA_EN_8822C BIT(5)\n#define BIT_PTA_WL_TX_EN_8822C BIT(4)\n#define BIT_R_USE_DATA_BW_8822C BIT(3)\n#define BIT_TRI_PKT_INT_MODE1_8822C BIT(2)\n#define BIT_TRI_PKT_INT_MODE0_8822C BIT(1)\n#define BIT_ACQ_MODE_SEL_8822C BIT(0)\n\n/* 2 REG_SINGLE_AMPDU_CTRL_8822C */\n#define BIT_EN_SINGLE_APMDU_8822C BIT(7)\n\n#define BIT_SHIFT_SNDTX_MAXTIME_8822C 0\n#define BIT_MASK_SNDTX_MAXTIME_8822C 0x7f\n#define BIT_SNDTX_MAXTIME_8822C(x)                                             \\\n\t(((x) & BIT_MASK_SNDTX_MAXTIME_8822C) << BIT_SHIFT_SNDTX_MAXTIME_8822C)\n#define BITS_SNDTX_MAXTIME_8822C                                               \\\n\t(BIT_MASK_SNDTX_MAXTIME_8822C << BIT_SHIFT_SNDTX_MAXTIME_8822C)\n#define BIT_CLEAR_SNDTX_MAXTIME_8822C(x) ((x) & (~BITS_SNDTX_MAXTIME_8822C))\n#define BIT_GET_SNDTX_MAXTIME_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SNDTX_MAXTIME_8822C) & BIT_MASK_SNDTX_MAXTIME_8822C)\n#define BIT_SET_SNDTX_MAXTIME_8822C(x, v)                                      \\\n\t(BIT_CLEAR_SNDTX_MAXTIME_8822C(x) | BIT_SNDTX_MAXTIME_8822C(v))\n\n/* 2 REG_PROT_MODE_CTRL_8822C */\n#define BIT_SND_SIFS_TXDATA_8822C BIT(31)\n#define BIT_TX_SND_MATCH_MACID_8822C BIT(30)\n\n#define BIT_SHIFT_RTS_MAX_AGG_NUM_8822C 24\n#define BIT_MASK_RTS_MAX_AGG_NUM_8822C 0x3f\n#define BIT_RTS_MAX_AGG_NUM_8822C(x)                                           \\\n\t(((x) & BIT_MASK_RTS_MAX_AGG_NUM_8822C)                                \\\n\t << BIT_SHIFT_RTS_MAX_AGG_NUM_8822C)\n#define BITS_RTS_MAX_AGG_NUM_8822C                                             \\\n\t(BIT_MASK_RTS_MAX_AGG_NUM_8822C << BIT_SHIFT_RTS_MAX_AGG_NUM_8822C)\n#define BIT_CLEAR_RTS_MAX_AGG_NUM_8822C(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8822C))\n#define BIT_GET_RTS_MAX_AGG_NUM_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8822C) &                            \\\n\t BIT_MASK_RTS_MAX_AGG_NUM_8822C)\n#define BIT_SET_RTS_MAX_AGG_NUM_8822C(x, v)                                    \\\n\t(BIT_CLEAR_RTS_MAX_AGG_NUM_8822C(x) | BIT_RTS_MAX_AGG_NUM_8822C(v))\n\n#define BIT_SHIFT_MAX_AGG_NUM_8822C 16\n#define BIT_MASK_MAX_AGG_NUM_8822C 0x3f\n#define BIT_MAX_AGG_NUM_8822C(x)                                               \\\n\t(((x) & BIT_MASK_MAX_AGG_NUM_8822C) << BIT_SHIFT_MAX_AGG_NUM_8822C)\n#define BITS_MAX_AGG_NUM_8822C                                                 \\\n\t(BIT_MASK_MAX_AGG_NUM_8822C << BIT_SHIFT_MAX_AGG_NUM_8822C)\n#define BIT_CLEAR_MAX_AGG_NUM_8822C(x) ((x) & (~BITS_MAX_AGG_NUM_8822C))\n#define BIT_GET_MAX_AGG_NUM_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_MAX_AGG_NUM_8822C) & BIT_MASK_MAX_AGG_NUM_8822C)\n#define BIT_SET_MAX_AGG_NUM_8822C(x, v)                                        \\\n\t(BIT_CLEAR_MAX_AGG_NUM_8822C(x) | BIT_MAX_AGG_NUM_8822C(v))\n\n#define BIT_SHIFT_RTS_TXTIME_TH_8822C 8\n#define BIT_MASK_RTS_TXTIME_TH_8822C 0xff\n#define BIT_RTS_TXTIME_TH_8822C(x)                                             \\\n\t(((x) & BIT_MASK_RTS_TXTIME_TH_8822C) << BIT_SHIFT_RTS_TXTIME_TH_8822C)\n#define BITS_RTS_TXTIME_TH_8822C                                               \\\n\t(BIT_MASK_RTS_TXTIME_TH_8822C << BIT_SHIFT_RTS_TXTIME_TH_8822C)\n#define BIT_CLEAR_RTS_TXTIME_TH_8822C(x) ((x) & (~BITS_RTS_TXTIME_TH_8822C))\n#define BIT_GET_RTS_TXTIME_TH_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_RTS_TXTIME_TH_8822C) & BIT_MASK_RTS_TXTIME_TH_8822C)\n#define BIT_SET_RTS_TXTIME_TH_8822C(x, v)                                      \\\n\t(BIT_CLEAR_RTS_TXTIME_TH_8822C(x) | BIT_RTS_TXTIME_TH_8822C(v))\n\n#define BIT_SHIFT_RTS_LEN_TH_8822C 0\n#define BIT_MASK_RTS_LEN_TH_8822C 0xff\n#define BIT_RTS_LEN_TH_8822C(x)                                                \\\n\t(((x) & BIT_MASK_RTS_LEN_TH_8822C) << BIT_SHIFT_RTS_LEN_TH_8822C)\n#define BITS_RTS_LEN_TH_8822C                                                  \\\n\t(BIT_MASK_RTS_LEN_TH_8822C << BIT_SHIFT_RTS_LEN_TH_8822C)\n#define BIT_CLEAR_RTS_LEN_TH_8822C(x) ((x) & (~BITS_RTS_LEN_TH_8822C))\n#define BIT_GET_RTS_LEN_TH_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_RTS_LEN_TH_8822C) & BIT_MASK_RTS_LEN_TH_8822C)\n#define BIT_SET_RTS_LEN_TH_8822C(x, v)                                         \\\n\t(BIT_CLEAR_RTS_LEN_TH_8822C(x) | BIT_RTS_LEN_TH_8822C(v))\n\n/* 2 REG_BAR_MODE_CTRL_8822C */\n\n#define BIT_SHIFT_BAR_RTY_LMT_8822C 16\n#define BIT_MASK_BAR_RTY_LMT_8822C 0x3\n#define BIT_BAR_RTY_LMT_8822C(x)                                               \\\n\t(((x) & BIT_MASK_BAR_RTY_LMT_8822C) << BIT_SHIFT_BAR_RTY_LMT_8822C)\n#define BITS_BAR_RTY_LMT_8822C                                                 \\\n\t(BIT_MASK_BAR_RTY_LMT_8822C << BIT_SHIFT_BAR_RTY_LMT_8822C)\n#define BIT_CLEAR_BAR_RTY_LMT_8822C(x) ((x) & (~BITS_BAR_RTY_LMT_8822C))\n#define BIT_GET_BAR_RTY_LMT_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_BAR_RTY_LMT_8822C) & BIT_MASK_BAR_RTY_LMT_8822C)\n#define BIT_SET_BAR_RTY_LMT_8822C(x, v)                                        \\\n\t(BIT_CLEAR_BAR_RTY_LMT_8822C(x) | BIT_BAR_RTY_LMT_8822C(v))\n\n#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C 8\n#define BIT_MASK_BAR_PKT_TXTIME_TH_8822C 0xff\n#define BIT_BAR_PKT_TXTIME_TH_8822C(x)                                         \\\n\t(((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8822C)                              \\\n\t << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C)\n#define BITS_BAR_PKT_TXTIME_TH_8822C                                           \\\n\t(BIT_MASK_BAR_PKT_TXTIME_TH_8822C << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C)\n#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8822C(x)                                   \\\n\t((x) & (~BITS_BAR_PKT_TXTIME_TH_8822C))\n#define BIT_GET_BAR_PKT_TXTIME_TH_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C) &                          \\\n\t BIT_MASK_BAR_PKT_TXTIME_TH_8822C)\n#define BIT_SET_BAR_PKT_TXTIME_TH_8822C(x, v)                                  \\\n\t(BIT_CLEAR_BAR_PKT_TXTIME_TH_8822C(x) | BIT_BAR_PKT_TXTIME_TH_8822C(v))\n\n#define BIT_BAR_EN_V1_8822C BIT(6)\n\n#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C 0\n#define BIT_MASK_BAR_PKTNUM_TH_V1_8822C 0x3f\n#define BIT_BAR_PKTNUM_TH_V1_8822C(x)                                          \\\n\t(((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8822C)                               \\\n\t << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C)\n#define BITS_BAR_PKTNUM_TH_V1_8822C                                            \\\n\t(BIT_MASK_BAR_PKTNUM_TH_V1_8822C << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C)\n#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8822C(x)                                    \\\n\t((x) & (~BITS_BAR_PKTNUM_TH_V1_8822C))\n#define BIT_GET_BAR_PKTNUM_TH_V1_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C) &                           \\\n\t BIT_MASK_BAR_PKTNUM_TH_V1_8822C)\n#define BIT_SET_BAR_PKTNUM_TH_V1_8822C(x, v)                                   \\\n\t(BIT_CLEAR_BAR_PKTNUM_TH_V1_8822C(x) | BIT_BAR_PKTNUM_TH_V1_8822C(v))\n\n/* 2 REG_RA_TRY_RATE_AGG_LMT_8822C */\n\n#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C 0\n#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C 0x3f\n#define BIT_RA_TRY_RATE_AGG_LMT_V1_8822C(x)                                    \\\n\t(((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C)                         \\\n\t << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C)\n#define BITS_RA_TRY_RATE_AGG_LMT_V1_8822C                                      \\\n\t(BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C                                 \\\n\t << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C)\n#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822C(x)                              \\\n\t((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8822C))\n#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8822C(x)                                \\\n\t(((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C) &                     \\\n\t BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C)\n#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8822C(x, v)                             \\\n\t(BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822C(x) |                           \\\n\t BIT_RA_TRY_RATE_AGG_LMT_V1_8822C(v))\n\n/* 2 REG_MACID_SLEEP2_8822C */\n\n#define BIT_SHIFT_MACID95_64PKTSLEEP_8822C 0\n#define BIT_MASK_MACID95_64PKTSLEEP_8822C 0xffffffffL\n#define BIT_MACID95_64PKTSLEEP_8822C(x)                                        \\\n\t(((x) & BIT_MASK_MACID95_64PKTSLEEP_8822C)                             \\\n\t << BIT_SHIFT_MACID95_64PKTSLEEP_8822C)\n#define BITS_MACID95_64PKTSLEEP_8822C                                          \\\n\t(BIT_MASK_MACID95_64PKTSLEEP_8822C                                     \\\n\t << BIT_SHIFT_MACID95_64PKTSLEEP_8822C)\n#define BIT_CLEAR_MACID95_64PKTSLEEP_8822C(x)                                  \\\n\t((x) & (~BITS_MACID95_64PKTSLEEP_8822C))\n#define BIT_GET_MACID95_64PKTSLEEP_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8822C) &                         \\\n\t BIT_MASK_MACID95_64PKTSLEEP_8822C)\n#define BIT_SET_MACID95_64PKTSLEEP_8822C(x, v)                                 \\\n\t(BIT_CLEAR_MACID95_64PKTSLEEP_8822C(x) |                               \\\n\t BIT_MACID95_64PKTSLEEP_8822C(v))\n\n/* 2 REG_MACID_SLEEP_8822C */\n\n#define BIT_SHIFT_MACID31_0_PKTSLEEP_8822C 0\n#define BIT_MASK_MACID31_0_PKTSLEEP_8822C 0xffffffffL\n#define BIT_MACID31_0_PKTSLEEP_8822C(x)                                        \\\n\t(((x) & BIT_MASK_MACID31_0_PKTSLEEP_8822C)                             \\\n\t << BIT_SHIFT_MACID31_0_PKTSLEEP_8822C)\n#define BITS_MACID31_0_PKTSLEEP_8822C                                          \\\n\t(BIT_MASK_MACID31_0_PKTSLEEP_8822C                                     \\\n\t << BIT_SHIFT_MACID31_0_PKTSLEEP_8822C)\n#define BIT_CLEAR_MACID31_0_PKTSLEEP_8822C(x)                                  \\\n\t((x) & (~BITS_MACID31_0_PKTSLEEP_8822C))\n#define BIT_GET_MACID31_0_PKTSLEEP_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8822C) &                         \\\n\t BIT_MASK_MACID31_0_PKTSLEEP_8822C)\n#define BIT_SET_MACID31_0_PKTSLEEP_8822C(x, v)                                 \\\n\t(BIT_CLEAR_MACID31_0_PKTSLEEP_8822C(x) |                               \\\n\t BIT_MACID31_0_PKTSLEEP_8822C(v))\n\n/* 2 REG_HW_SEQ0_8822C */\n\n#define BIT_SHIFT_HW_SSN_SEQ0_8822C 0\n#define BIT_MASK_HW_SSN_SEQ0_8822C 0xfff\n#define BIT_HW_SSN_SEQ0_8822C(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ0_8822C) << BIT_SHIFT_HW_SSN_SEQ0_8822C)\n#define BITS_HW_SSN_SEQ0_8822C                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ0_8822C << BIT_SHIFT_HW_SSN_SEQ0_8822C)\n#define BIT_CLEAR_HW_SSN_SEQ0_8822C(x) ((x) & (~BITS_HW_SSN_SEQ0_8822C))\n#define BIT_GET_HW_SSN_SEQ0_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ0_8822C) & BIT_MASK_HW_SSN_SEQ0_8822C)\n#define BIT_SET_HW_SSN_SEQ0_8822C(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ0_8822C(x) | BIT_HW_SSN_SEQ0_8822C(v))\n\n/* 2 REG_HW_SEQ1_8822C */\n\n#define BIT_SHIFT_HW_SSN_SEQ1_8822C 0\n#define BIT_MASK_HW_SSN_SEQ1_8822C 0xfff\n#define BIT_HW_SSN_SEQ1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ1_8822C) << BIT_SHIFT_HW_SSN_SEQ1_8822C)\n#define BITS_HW_SSN_SEQ1_8822C                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ1_8822C << BIT_SHIFT_HW_SSN_SEQ1_8822C)\n#define BIT_CLEAR_HW_SSN_SEQ1_8822C(x) ((x) & (~BITS_HW_SSN_SEQ1_8822C))\n#define BIT_GET_HW_SSN_SEQ1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ1_8822C) & BIT_MASK_HW_SSN_SEQ1_8822C)\n#define BIT_SET_HW_SSN_SEQ1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ1_8822C(x) | BIT_HW_SSN_SEQ1_8822C(v))\n\n/* 2 REG_HW_SEQ2_8822C */\n\n#define BIT_SHIFT_HW_SSN_SEQ2_8822C 0\n#define BIT_MASK_HW_SSN_SEQ2_8822C 0xfff\n#define BIT_HW_SSN_SEQ2_8822C(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ2_8822C) << BIT_SHIFT_HW_SSN_SEQ2_8822C)\n#define BITS_HW_SSN_SEQ2_8822C                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ2_8822C << BIT_SHIFT_HW_SSN_SEQ2_8822C)\n#define BIT_CLEAR_HW_SSN_SEQ2_8822C(x) ((x) & (~BITS_HW_SSN_SEQ2_8822C))\n#define BIT_GET_HW_SSN_SEQ2_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ2_8822C) & BIT_MASK_HW_SSN_SEQ2_8822C)\n#define BIT_SET_HW_SSN_SEQ2_8822C(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ2_8822C(x) | BIT_HW_SSN_SEQ2_8822C(v))\n\n/* 2 REG_HW_SEQ3_8822C */\n\n#define BIT_SHIFT_CSI_HWSEQ_SEL_8822C 12\n#define BIT_MASK_CSI_HWSEQ_SEL_8822C 0x3\n#define BIT_CSI_HWSEQ_SEL_8822C(x)                                             \\\n\t(((x) & BIT_MASK_CSI_HWSEQ_SEL_8822C) << BIT_SHIFT_CSI_HWSEQ_SEL_8822C)\n#define BITS_CSI_HWSEQ_SEL_8822C                                               \\\n\t(BIT_MASK_CSI_HWSEQ_SEL_8822C << BIT_SHIFT_CSI_HWSEQ_SEL_8822C)\n#define BIT_CLEAR_CSI_HWSEQ_SEL_8822C(x) ((x) & (~BITS_CSI_HWSEQ_SEL_8822C))\n#define BIT_GET_CSI_HWSEQ_SEL_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_CSI_HWSEQ_SEL_8822C) & BIT_MASK_CSI_HWSEQ_SEL_8822C)\n#define BIT_SET_CSI_HWSEQ_SEL_8822C(x, v)                                      \\\n\t(BIT_CLEAR_CSI_HWSEQ_SEL_8822C(x) | BIT_CSI_HWSEQ_SEL_8822C(v))\n\n#define BIT_SHIFT_HW_SSN_SEQ3_8822C 0\n#define BIT_MASK_HW_SSN_SEQ3_8822C 0xfff\n#define BIT_HW_SSN_SEQ3_8822C(x)                                               \\\n\t(((x) & BIT_MASK_HW_SSN_SEQ3_8822C) << BIT_SHIFT_HW_SSN_SEQ3_8822C)\n#define BITS_HW_SSN_SEQ3_8822C                                                 \\\n\t(BIT_MASK_HW_SSN_SEQ3_8822C << BIT_SHIFT_HW_SSN_SEQ3_8822C)\n#define BIT_CLEAR_HW_SSN_SEQ3_8822C(x) ((x) & (~BITS_HW_SSN_SEQ3_8822C))\n#define BIT_GET_HW_SSN_SEQ3_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_HW_SSN_SEQ3_8822C) & BIT_MASK_HW_SSN_SEQ3_8822C)\n#define BIT_SET_HW_SSN_SEQ3_8822C(x, v)                                        \\\n\t(BIT_CLEAR_HW_SSN_SEQ3_8822C(x) | BIT_HW_SSN_SEQ3_8822C(v))\n\n/* 2 REG_NULL_PKT_STATUS_V1_8822C */\n\n#define BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C 2\n#define BIT_MASK_PTCL_TOTAL_PG_V2_8822C 0x3fff\n#define BIT_PTCL_TOTAL_PG_V2_8822C(x)                                          \\\n\t(((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8822C)                               \\\n\t << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C)\n#define BITS_PTCL_TOTAL_PG_V2_8822C                                            \\\n\t(BIT_MASK_PTCL_TOTAL_PG_V2_8822C << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C)\n#define BIT_CLEAR_PTCL_TOTAL_PG_V2_8822C(x)                                    \\\n\t((x) & (~BITS_PTCL_TOTAL_PG_V2_8822C))\n#define BIT_GET_PTCL_TOTAL_PG_V2_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C) &                           \\\n\t BIT_MASK_PTCL_TOTAL_PG_V2_8822C)\n#define BIT_SET_PTCL_TOTAL_PG_V2_8822C(x, v)                                   \\\n\t(BIT_CLEAR_PTCL_TOTAL_PG_V2_8822C(x) | BIT_PTCL_TOTAL_PG_V2_8822C(v))\n\n#define BIT_TX_NULL_1_8822C BIT(1)\n#define BIT_TX_NULL_0_8822C BIT(0)\n\n/* 2 REG_PTCL_ERR_STATUS_8822C */\n#define BIT_PTCL_RATE_TABLE_INVALID_8822C BIT(7)\n#define BIT_FTM_T2R_ERROR_8822C BIT(6)\n#define BIT_PTCL_ERR0_8822C BIT(5)\n#define BIT_PTCL_ERR1_8822C BIT(4)\n#define BIT_PTCL_ERR2_8822C BIT(3)\n#define BIT_PTCL_ERR3_8822C BIT(2)\n#define BIT_PTCL_ERR4_8822C BIT(1)\n#define BIT_PTCL_ERR5_8822C BIT(0)\n\n/* 2 REG_NULL_PKT_STATUS_EXTEND_8822C */\n#define BIT_CLI3_TX_NULL_1_8822C BIT(7)\n#define BIT_CLI3_TX_NULL_0_8822C BIT(6)\n#define BIT_CLI2_TX_NULL_1_8822C BIT(5)\n#define BIT_CLI2_TX_NULL_0_8822C BIT(4)\n#define BIT_CLI1_TX_NULL_1_8822C BIT(3)\n#define BIT_CLI1_TX_NULL_0_8822C BIT(2)\n#define BIT_CLI0_TX_NULL_1_8822C BIT(1)\n#define BIT_CLI0_TX_NULL_0_8822C BIT(0)\n\n/* 2 REG_HQMGQ_DROP_8822C */\n#define BIT_HIQ_DROP_8822C BIT(7)\n#define BIT_MGQ_DROP_8822C BIT(6)\n#define BIT_CLR_HGQ_REQ_BLOCK_8822C BIT(5)\n\n/* 2 REG_PRECNT_CTRL_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_EN_PRECNT_8822C BIT(11)\n\n#define BIT_SHIFT_PRECNT_TH_8822C 0\n#define BIT_MASK_PRECNT_TH_8822C 0x7ff\n#define BIT_PRECNT_TH_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_PRECNT_TH_8822C) << BIT_SHIFT_PRECNT_TH_8822C)\n#define BITS_PRECNT_TH_8822C                                                   \\\n\t(BIT_MASK_PRECNT_TH_8822C << BIT_SHIFT_PRECNT_TH_8822C)\n#define BIT_CLEAR_PRECNT_TH_8822C(x) ((x) & (~BITS_PRECNT_TH_8822C))\n#define BIT_GET_PRECNT_TH_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_PRECNT_TH_8822C) & BIT_MASK_PRECNT_TH_8822C)\n#define BIT_SET_PRECNT_TH_8822C(x, v)                                          \\\n\t(BIT_CLEAR_PRECNT_TH_8822C(x) | BIT_PRECNT_TH_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_BT_POLLUTE_PKT_CNT_8822C */\n\n#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C 0\n#define BIT_MASK_BT_POLLUTE_PKT_CNT_8822C 0xffff\n#define BIT_BT_POLLUTE_PKT_CNT_8822C(x)                                        \\\n\t(((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822C)                             \\\n\t << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C)\n#define BITS_BT_POLLUTE_PKT_CNT_8822C                                          \\\n\t(BIT_MASK_BT_POLLUTE_PKT_CNT_8822C                                     \\\n\t << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C)\n#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822C(x)                                  \\\n\t((x) & (~BITS_BT_POLLUTE_PKT_CNT_8822C))\n#define BIT_GET_BT_POLLUTE_PKT_CNT_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C) &                         \\\n\t BIT_MASK_BT_POLLUTE_PKT_CNT_8822C)\n#define BIT_SET_BT_POLLUTE_PKT_CNT_8822C(x, v)                                 \\\n\t(BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822C(x) |                               \\\n\t BIT_BT_POLLUTE_PKT_CNT_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_PTCL_DBG_8822C */\n\n#define BIT_SHIFT_PTCL_DBG_8822C 0\n#define BIT_MASK_PTCL_DBG_8822C 0xffffffffL\n#define BIT_PTCL_DBG_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_PTCL_DBG_8822C) << BIT_SHIFT_PTCL_DBG_8822C)\n#define BITS_PTCL_DBG_8822C                                                    \\\n\t(BIT_MASK_PTCL_DBG_8822C << BIT_SHIFT_PTCL_DBG_8822C)\n#define BIT_CLEAR_PTCL_DBG_8822C(x) ((x) & (~BITS_PTCL_DBG_8822C))\n#define BIT_GET_PTCL_DBG_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_PTCL_DBG_8822C) & BIT_MASK_PTCL_DBG_8822C)\n#define BIT_SET_PTCL_DBG_8822C(x, v)                                           \\\n\t(BIT_CLEAR_PTCL_DBG_8822C(x) | BIT_PTCL_DBG_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_CPUMGQ_TIMER_CTRL2_8822C */\n\n#define BIT_SHIFT_TRI_HEAD_ADDR_8822C 16\n#define BIT_MASK_TRI_HEAD_ADDR_8822C 0xfff\n#define BIT_TRI_HEAD_ADDR_8822C(x)                                             \\\n\t(((x) & BIT_MASK_TRI_HEAD_ADDR_8822C) << BIT_SHIFT_TRI_HEAD_ADDR_8822C)\n#define BITS_TRI_HEAD_ADDR_8822C                                               \\\n\t(BIT_MASK_TRI_HEAD_ADDR_8822C << BIT_SHIFT_TRI_HEAD_ADDR_8822C)\n#define BIT_CLEAR_TRI_HEAD_ADDR_8822C(x) ((x) & (~BITS_TRI_HEAD_ADDR_8822C))\n#define BIT_GET_TRI_HEAD_ADDR_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8822C) & BIT_MASK_TRI_HEAD_ADDR_8822C)\n#define BIT_SET_TRI_HEAD_ADDR_8822C(x, v)                                      \\\n\t(BIT_CLEAR_TRI_HEAD_ADDR_8822C(x) | BIT_TRI_HEAD_ADDR_8822C(v))\n\n#define BIT_DROP_TH_EN_8822C BIT(8)\n\n#define BIT_SHIFT_DROP_TH_8822C 0\n#define BIT_MASK_DROP_TH_8822C 0xff\n#define BIT_DROP_TH_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_DROP_TH_8822C) << BIT_SHIFT_DROP_TH_8822C)\n#define BITS_DROP_TH_8822C (BIT_MASK_DROP_TH_8822C << BIT_SHIFT_DROP_TH_8822C)\n#define BIT_CLEAR_DROP_TH_8822C(x) ((x) & (~BITS_DROP_TH_8822C))\n#define BIT_GET_DROP_TH_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_DROP_TH_8822C) & BIT_MASK_DROP_TH_8822C)\n#define BIT_SET_DROP_TH_8822C(x, v)                                            \\\n\t(BIT_CLEAR_DROP_TH_8822C(x) | BIT_DROP_TH_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_DUMMY_PAGE4_V1_8822C */\n\n/* 2 REG_MOREDATA_8822C */\n#define BIT_MOREDATA_CTRL2_EN_V1_8822C BIT(3)\n#define BIT_MOREDATA_CTRL1_EN_V1_8822C BIT(2)\n#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8822C BIT(0)\n\n/* 2 REG_Q0_Q1_INFO_8822C */\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31)\n\n#define BIT_SHIFT_GTAB_ID_8822C 28\n#define BIT_MASK_GTAB_ID_8822C 0x7\n#define BIT_GTAB_ID_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C)\n#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C)\n#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C))\n#define BIT_GET_GTAB_ID_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C)\n#define BIT_SET_GTAB_ID_8822C(x, v)                                            \\\n\t(BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v))\n\n#define BIT_SHIFT_AC1_PKT_INFO_8822C 16\n#define BIT_MASK_AC1_PKT_INFO_8822C 0xfff\n#define BIT_AC1_PKT_INFO_8822C(x)                                              \\\n\t(((x) & BIT_MASK_AC1_PKT_INFO_8822C) << BIT_SHIFT_AC1_PKT_INFO_8822C)\n#define BITS_AC1_PKT_INFO_8822C                                                \\\n\t(BIT_MASK_AC1_PKT_INFO_8822C << BIT_SHIFT_AC1_PKT_INFO_8822C)\n#define BIT_CLEAR_AC1_PKT_INFO_8822C(x) ((x) & (~BITS_AC1_PKT_INFO_8822C))\n#define BIT_GET_AC1_PKT_INFO_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC1_PKT_INFO_8822C) & BIT_MASK_AC1_PKT_INFO_8822C)\n#define BIT_SET_AC1_PKT_INFO_8822C(x, v)                                       \\\n\t(BIT_CLEAR_AC1_PKT_INFO_8822C(x) | BIT_AC1_PKT_INFO_8822C(v))\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15)\n\n#define BIT_SHIFT_GTAB_ID_V1_8822C 12\n#define BIT_MASK_GTAB_ID_V1_8822C 0x7\n#define BIT_GTAB_ID_V1_8822C(x)                                                \\\n\t(((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C)\n#define BITS_GTAB_ID_V1_8822C                                                  \\\n\t(BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C)\n#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C))\n#define BIT_GET_GTAB_ID_V1_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C)\n#define BIT_SET_GTAB_ID_V1_8822C(x, v)                                         \\\n\t(BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v))\n\n#define BIT_SHIFT_AC0_PKT_INFO_8822C 0\n#define BIT_MASK_AC0_PKT_INFO_8822C 0xfff\n#define BIT_AC0_PKT_INFO_8822C(x)                                              \\\n\t(((x) & BIT_MASK_AC0_PKT_INFO_8822C) << BIT_SHIFT_AC0_PKT_INFO_8822C)\n#define BITS_AC0_PKT_INFO_8822C                                                \\\n\t(BIT_MASK_AC0_PKT_INFO_8822C << BIT_SHIFT_AC0_PKT_INFO_8822C)\n#define BIT_CLEAR_AC0_PKT_INFO_8822C(x) ((x) & (~BITS_AC0_PKT_INFO_8822C))\n#define BIT_GET_AC0_PKT_INFO_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC0_PKT_INFO_8822C) & BIT_MASK_AC0_PKT_INFO_8822C)\n#define BIT_SET_AC0_PKT_INFO_8822C(x, v)                                       \\\n\t(BIT_CLEAR_AC0_PKT_INFO_8822C(x) | BIT_AC0_PKT_INFO_8822C(v))\n\n/* 2 REG_Q2_Q3_INFO_8822C */\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31)\n\n#define BIT_SHIFT_GTAB_ID_8822C 28\n#define BIT_MASK_GTAB_ID_8822C 0x7\n#define BIT_GTAB_ID_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C)\n#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C)\n#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C))\n#define BIT_GET_GTAB_ID_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C)\n#define BIT_SET_GTAB_ID_8822C(x, v)                                            \\\n\t(BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v))\n\n#define BIT_SHIFT_AC3_PKT_INFO_8822C 16\n#define BIT_MASK_AC3_PKT_INFO_8822C 0xfff\n#define BIT_AC3_PKT_INFO_8822C(x)                                              \\\n\t(((x) & BIT_MASK_AC3_PKT_INFO_8822C) << BIT_SHIFT_AC3_PKT_INFO_8822C)\n#define BITS_AC3_PKT_INFO_8822C                                                \\\n\t(BIT_MASK_AC3_PKT_INFO_8822C << BIT_SHIFT_AC3_PKT_INFO_8822C)\n#define BIT_CLEAR_AC3_PKT_INFO_8822C(x) ((x) & (~BITS_AC3_PKT_INFO_8822C))\n#define BIT_GET_AC3_PKT_INFO_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC3_PKT_INFO_8822C) & BIT_MASK_AC3_PKT_INFO_8822C)\n#define BIT_SET_AC3_PKT_INFO_8822C(x, v)                                       \\\n\t(BIT_CLEAR_AC3_PKT_INFO_8822C(x) | BIT_AC3_PKT_INFO_8822C(v))\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15)\n\n#define BIT_SHIFT_GTAB_ID_V1_8822C 12\n#define BIT_MASK_GTAB_ID_V1_8822C 0x7\n#define BIT_GTAB_ID_V1_8822C(x)                                                \\\n\t(((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C)\n#define BITS_GTAB_ID_V1_8822C                                                  \\\n\t(BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C)\n#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C))\n#define BIT_GET_GTAB_ID_V1_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C)\n#define BIT_SET_GTAB_ID_V1_8822C(x, v)                                         \\\n\t(BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v))\n\n#define BIT_SHIFT_AC2_PKT_INFO_8822C 0\n#define BIT_MASK_AC2_PKT_INFO_8822C 0xfff\n#define BIT_AC2_PKT_INFO_8822C(x)                                              \\\n\t(((x) & BIT_MASK_AC2_PKT_INFO_8822C) << BIT_SHIFT_AC2_PKT_INFO_8822C)\n#define BITS_AC2_PKT_INFO_8822C                                                \\\n\t(BIT_MASK_AC2_PKT_INFO_8822C << BIT_SHIFT_AC2_PKT_INFO_8822C)\n#define BIT_CLEAR_AC2_PKT_INFO_8822C(x) ((x) & (~BITS_AC2_PKT_INFO_8822C))\n#define BIT_GET_AC2_PKT_INFO_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC2_PKT_INFO_8822C) & BIT_MASK_AC2_PKT_INFO_8822C)\n#define BIT_SET_AC2_PKT_INFO_8822C(x, v)                                       \\\n\t(BIT_CLEAR_AC2_PKT_INFO_8822C(x) | BIT_AC2_PKT_INFO_8822C(v))\n\n/* 2 REG_Q4_Q5_INFO_8822C */\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31)\n\n#define BIT_SHIFT_GTAB_ID_8822C 28\n#define BIT_MASK_GTAB_ID_8822C 0x7\n#define BIT_GTAB_ID_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C)\n#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C)\n#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C))\n#define BIT_GET_GTAB_ID_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C)\n#define BIT_SET_GTAB_ID_8822C(x, v)                                            \\\n\t(BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v))\n\n#define BIT_SHIFT_AC5_PKT_INFO_8822C 16\n#define BIT_MASK_AC5_PKT_INFO_8822C 0xfff\n#define BIT_AC5_PKT_INFO_8822C(x)                                              \\\n\t(((x) & BIT_MASK_AC5_PKT_INFO_8822C) << BIT_SHIFT_AC5_PKT_INFO_8822C)\n#define BITS_AC5_PKT_INFO_8822C                                                \\\n\t(BIT_MASK_AC5_PKT_INFO_8822C << BIT_SHIFT_AC5_PKT_INFO_8822C)\n#define BIT_CLEAR_AC5_PKT_INFO_8822C(x) ((x) & (~BITS_AC5_PKT_INFO_8822C))\n#define BIT_GET_AC5_PKT_INFO_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC5_PKT_INFO_8822C) & BIT_MASK_AC5_PKT_INFO_8822C)\n#define BIT_SET_AC5_PKT_INFO_8822C(x, v)                                       \\\n\t(BIT_CLEAR_AC5_PKT_INFO_8822C(x) | BIT_AC5_PKT_INFO_8822C(v))\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15)\n\n#define BIT_SHIFT_GTAB_ID_V1_8822C 12\n#define BIT_MASK_GTAB_ID_V1_8822C 0x7\n#define BIT_GTAB_ID_V1_8822C(x)                                                \\\n\t(((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C)\n#define BITS_GTAB_ID_V1_8822C                                                  \\\n\t(BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C)\n#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C))\n#define BIT_GET_GTAB_ID_V1_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C)\n#define BIT_SET_GTAB_ID_V1_8822C(x, v)                                         \\\n\t(BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v))\n\n#define BIT_SHIFT_AC4_PKT_INFO_8822C 0\n#define BIT_MASK_AC4_PKT_INFO_8822C 0xfff\n#define BIT_AC4_PKT_INFO_8822C(x)                                              \\\n\t(((x) & BIT_MASK_AC4_PKT_INFO_8822C) << BIT_SHIFT_AC4_PKT_INFO_8822C)\n#define BITS_AC4_PKT_INFO_8822C                                                \\\n\t(BIT_MASK_AC4_PKT_INFO_8822C << BIT_SHIFT_AC4_PKT_INFO_8822C)\n#define BIT_CLEAR_AC4_PKT_INFO_8822C(x) ((x) & (~BITS_AC4_PKT_INFO_8822C))\n#define BIT_GET_AC4_PKT_INFO_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC4_PKT_INFO_8822C) & BIT_MASK_AC4_PKT_INFO_8822C)\n#define BIT_SET_AC4_PKT_INFO_8822C(x, v)                                       \\\n\t(BIT_CLEAR_AC4_PKT_INFO_8822C(x) | BIT_AC4_PKT_INFO_8822C(v))\n\n/* 2 REG_Q6_Q7_INFO_8822C */\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31)\n\n#define BIT_SHIFT_GTAB_ID_8822C 28\n#define BIT_MASK_GTAB_ID_8822C 0x7\n#define BIT_GTAB_ID_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C)\n#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C)\n#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C))\n#define BIT_GET_GTAB_ID_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C)\n#define BIT_SET_GTAB_ID_8822C(x, v)                                            \\\n\t(BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v))\n\n#define BIT_SHIFT_AC7_PKT_INFO_8822C 16\n#define BIT_MASK_AC7_PKT_INFO_8822C 0xfff\n#define BIT_AC7_PKT_INFO_8822C(x)                                              \\\n\t(((x) & BIT_MASK_AC7_PKT_INFO_8822C) << BIT_SHIFT_AC7_PKT_INFO_8822C)\n#define BITS_AC7_PKT_INFO_8822C                                                \\\n\t(BIT_MASK_AC7_PKT_INFO_8822C << BIT_SHIFT_AC7_PKT_INFO_8822C)\n#define BIT_CLEAR_AC7_PKT_INFO_8822C(x) ((x) & (~BITS_AC7_PKT_INFO_8822C))\n#define BIT_GET_AC7_PKT_INFO_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC7_PKT_INFO_8822C) & BIT_MASK_AC7_PKT_INFO_8822C)\n#define BIT_SET_AC7_PKT_INFO_8822C(x, v)                                       \\\n\t(BIT_CLEAR_AC7_PKT_INFO_8822C(x) | BIT_AC7_PKT_INFO_8822C(v))\n\n#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15)\n\n#define BIT_SHIFT_GTAB_ID_V1_8822C 12\n#define BIT_MASK_GTAB_ID_V1_8822C 0x7\n#define BIT_GTAB_ID_V1_8822C(x)                                                \\\n\t(((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C)\n#define BITS_GTAB_ID_V1_8822C                                                  \\\n\t(BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C)\n#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C))\n#define BIT_GET_GTAB_ID_V1_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C)\n#define BIT_SET_GTAB_ID_V1_8822C(x, v)                                         \\\n\t(BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v))\n\n#define BIT_SHIFT_AC6_PKT_INFO_8822C 0\n#define BIT_MASK_AC6_PKT_INFO_8822C 0xfff\n#define BIT_AC6_PKT_INFO_8822C(x)                                              \\\n\t(((x) & BIT_MASK_AC6_PKT_INFO_8822C) << BIT_SHIFT_AC6_PKT_INFO_8822C)\n#define BITS_AC6_PKT_INFO_8822C                                                \\\n\t(BIT_MASK_AC6_PKT_INFO_8822C << BIT_SHIFT_AC6_PKT_INFO_8822C)\n#define BIT_CLEAR_AC6_PKT_INFO_8822C(x) ((x) & (~BITS_AC6_PKT_INFO_8822C))\n#define BIT_GET_AC6_PKT_INFO_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AC6_PKT_INFO_8822C) & BIT_MASK_AC6_PKT_INFO_8822C)\n#define BIT_SET_AC6_PKT_INFO_8822C(x, v)                                       \\\n\t(BIT_CLEAR_AC6_PKT_INFO_8822C(x) | BIT_AC6_PKT_INFO_8822C(v))\n\n/* 2 REG_MGQ_HIQ_INFO_8822C */\n\n#define BIT_SHIFT_HIQ_PKT_INFO_8822C 16\n#define BIT_MASK_HIQ_PKT_INFO_8822C 0xfff\n#define BIT_HIQ_PKT_INFO_8822C(x)                                              \\\n\t(((x) & BIT_MASK_HIQ_PKT_INFO_8822C) << BIT_SHIFT_HIQ_PKT_INFO_8822C)\n#define BITS_HIQ_PKT_INFO_8822C                                                \\\n\t(BIT_MASK_HIQ_PKT_INFO_8822C << BIT_SHIFT_HIQ_PKT_INFO_8822C)\n#define BIT_CLEAR_HIQ_PKT_INFO_8822C(x) ((x) & (~BITS_HIQ_PKT_INFO_8822C))\n#define BIT_GET_HIQ_PKT_INFO_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_HIQ_PKT_INFO_8822C) & BIT_MASK_HIQ_PKT_INFO_8822C)\n#define BIT_SET_HIQ_PKT_INFO_8822C(x, v)                                       \\\n\t(BIT_CLEAR_HIQ_PKT_INFO_8822C(x) | BIT_HIQ_PKT_INFO_8822C(v))\n\n#define BIT_SHIFT_MGQ_PKT_INFO_8822C 0\n#define BIT_MASK_MGQ_PKT_INFO_8822C 0xfff\n#define BIT_MGQ_PKT_INFO_8822C(x)                                              \\\n\t(((x) & BIT_MASK_MGQ_PKT_INFO_8822C) << BIT_SHIFT_MGQ_PKT_INFO_8822C)\n#define BITS_MGQ_PKT_INFO_8822C                                                \\\n\t(BIT_MASK_MGQ_PKT_INFO_8822C << BIT_SHIFT_MGQ_PKT_INFO_8822C)\n#define BIT_CLEAR_MGQ_PKT_INFO_8822C(x) ((x) & (~BITS_MGQ_PKT_INFO_8822C))\n#define BIT_GET_MGQ_PKT_INFO_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_MGQ_PKT_INFO_8822C) & BIT_MASK_MGQ_PKT_INFO_8822C)\n#define BIT_SET_MGQ_PKT_INFO_8822C(x, v)                                       \\\n\t(BIT_CLEAR_MGQ_PKT_INFO_8822C(x) | BIT_MGQ_PKT_INFO_8822C(v))\n\n/* 2 REG_CMDQ_BCNQ_INFO_8822C */\n\n#define BIT_SHIFT_CMDQ_PKT_INFO_8822C 16\n#define BIT_MASK_CMDQ_PKT_INFO_8822C 0xfff\n#define BIT_CMDQ_PKT_INFO_8822C(x)                                             \\\n\t(((x) & BIT_MASK_CMDQ_PKT_INFO_8822C) << BIT_SHIFT_CMDQ_PKT_INFO_8822C)\n#define BITS_CMDQ_PKT_INFO_8822C                                               \\\n\t(BIT_MASK_CMDQ_PKT_INFO_8822C << BIT_SHIFT_CMDQ_PKT_INFO_8822C)\n#define BIT_CLEAR_CMDQ_PKT_INFO_8822C(x) ((x) & (~BITS_CMDQ_PKT_INFO_8822C))\n#define BIT_GET_CMDQ_PKT_INFO_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8822C) & BIT_MASK_CMDQ_PKT_INFO_8822C)\n#define BIT_SET_CMDQ_PKT_INFO_8822C(x, v)                                      \\\n\t(BIT_CLEAR_CMDQ_PKT_INFO_8822C(x) | BIT_CMDQ_PKT_INFO_8822C(v))\n\n#define BIT_SHIFT_BCNQ_PKT_INFO_8822C 0\n#define BIT_MASK_BCNQ_PKT_INFO_8822C 0xfff\n#define BIT_BCNQ_PKT_INFO_8822C(x)                                             \\\n\t(((x) & BIT_MASK_BCNQ_PKT_INFO_8822C) << BIT_SHIFT_BCNQ_PKT_INFO_8822C)\n#define BITS_BCNQ_PKT_INFO_8822C                                               \\\n\t(BIT_MASK_BCNQ_PKT_INFO_8822C << BIT_SHIFT_BCNQ_PKT_INFO_8822C)\n#define BIT_CLEAR_BCNQ_PKT_INFO_8822C(x) ((x) & (~BITS_BCNQ_PKT_INFO_8822C))\n#define BIT_GET_BCNQ_PKT_INFO_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8822C) & BIT_MASK_BCNQ_PKT_INFO_8822C)\n#define BIT_SET_BCNQ_PKT_INFO_8822C(x, v)                                      \\\n\t(BIT_CLEAR_BCNQ_PKT_INFO_8822C(x) | BIT_BCNQ_PKT_INFO_8822C(v))\n\n/* 2 REG_LOOPBACK_OPTION_8822C */\n#define BIT_LOOPACK_FAST_EDCA_EN_8822C BIT(24)\n\n/* 2 REG_AESIV_SETTING_8822C */\n\n#define BIT_SHIFT_AESIV_OFFSET_8822C 0\n#define BIT_MASK_AESIV_OFFSET_8822C 0xfff\n#define BIT_AESIV_OFFSET_8822C(x)                                              \\\n\t(((x) & BIT_MASK_AESIV_OFFSET_8822C) << BIT_SHIFT_AESIV_OFFSET_8822C)\n#define BITS_AESIV_OFFSET_8822C                                                \\\n\t(BIT_MASK_AESIV_OFFSET_8822C << BIT_SHIFT_AESIV_OFFSET_8822C)\n#define BIT_CLEAR_AESIV_OFFSET_8822C(x) ((x) & (~BITS_AESIV_OFFSET_8822C))\n#define BIT_GET_AESIV_OFFSET_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AESIV_OFFSET_8822C) & BIT_MASK_AESIV_OFFSET_8822C)\n#define BIT_SET_AESIV_OFFSET_8822C(x, v)                                       \\\n\t(BIT_CLEAR_AESIV_OFFSET_8822C(x) | BIT_AESIV_OFFSET_8822C(v))\n\n/* 2 REG_BF0_TIME_SETTING_8822C */\n#define BIT_BF0_TIMER_SET_8822C BIT(31)\n#define BIT_BF0_TIMER_CLR_8822C BIT(30)\n#define BIT_BF0_UPDATE_EN_8822C BIT(29)\n#define BIT_BF0_TIMER_EN_8822C BIT(28)\n\n#define BIT_SHIFT_BF0_PRETIME_OVER_8822C 16\n#define BIT_MASK_BF0_PRETIME_OVER_8822C 0xfff\n#define BIT_BF0_PRETIME_OVER_8822C(x)                                          \\\n\t(((x) & BIT_MASK_BF0_PRETIME_OVER_8822C)                               \\\n\t << BIT_SHIFT_BF0_PRETIME_OVER_8822C)\n#define BITS_BF0_PRETIME_OVER_8822C                                            \\\n\t(BIT_MASK_BF0_PRETIME_OVER_8822C << BIT_SHIFT_BF0_PRETIME_OVER_8822C)\n#define BIT_CLEAR_BF0_PRETIME_OVER_8822C(x)                                    \\\n\t((x) & (~BITS_BF0_PRETIME_OVER_8822C))\n#define BIT_GET_BF0_PRETIME_OVER_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8822C) &                           \\\n\t BIT_MASK_BF0_PRETIME_OVER_8822C)\n#define BIT_SET_BF0_PRETIME_OVER_8822C(x, v)                                   \\\n\t(BIT_CLEAR_BF0_PRETIME_OVER_8822C(x) | BIT_BF0_PRETIME_OVER_8822C(v))\n\n#define BIT_SHIFT_BF0_LIFETIME_8822C 0\n#define BIT_MASK_BF0_LIFETIME_8822C 0xffff\n#define BIT_BF0_LIFETIME_8822C(x)                                              \\\n\t(((x) & BIT_MASK_BF0_LIFETIME_8822C) << BIT_SHIFT_BF0_LIFETIME_8822C)\n#define BITS_BF0_LIFETIME_8822C                                                \\\n\t(BIT_MASK_BF0_LIFETIME_8822C << BIT_SHIFT_BF0_LIFETIME_8822C)\n#define BIT_CLEAR_BF0_LIFETIME_8822C(x) ((x) & (~BITS_BF0_LIFETIME_8822C))\n#define BIT_GET_BF0_LIFETIME_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BF0_LIFETIME_8822C) & BIT_MASK_BF0_LIFETIME_8822C)\n#define BIT_SET_BF0_LIFETIME_8822C(x, v)                                       \\\n\t(BIT_CLEAR_BF0_LIFETIME_8822C(x) | BIT_BF0_LIFETIME_8822C(v))\n\n/* 2 REG_BF1_TIME_SETTING_8822C */\n#define BIT_BF1_TIMER_SET_8822C BIT(31)\n#define BIT_BF1_TIMER_CLR_8822C BIT(30)\n#define BIT_BF1_UPDATE_EN_8822C BIT(29)\n#define BIT_BF1_TIMER_EN_8822C BIT(28)\n\n#define BIT_SHIFT_BF1_PRETIME_OVER_8822C 16\n#define BIT_MASK_BF1_PRETIME_OVER_8822C 0xfff\n#define BIT_BF1_PRETIME_OVER_8822C(x)                                          \\\n\t(((x) & BIT_MASK_BF1_PRETIME_OVER_8822C)                               \\\n\t << BIT_SHIFT_BF1_PRETIME_OVER_8822C)\n#define BITS_BF1_PRETIME_OVER_8822C                                            \\\n\t(BIT_MASK_BF1_PRETIME_OVER_8822C << BIT_SHIFT_BF1_PRETIME_OVER_8822C)\n#define BIT_CLEAR_BF1_PRETIME_OVER_8822C(x)                                    \\\n\t((x) & (~BITS_BF1_PRETIME_OVER_8822C))\n#define BIT_GET_BF1_PRETIME_OVER_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8822C) &                           \\\n\t BIT_MASK_BF1_PRETIME_OVER_8822C)\n#define BIT_SET_BF1_PRETIME_OVER_8822C(x, v)                                   \\\n\t(BIT_CLEAR_BF1_PRETIME_OVER_8822C(x) | BIT_BF1_PRETIME_OVER_8822C(v))\n\n#define BIT_SHIFT_BF1_LIFETIME_8822C 0\n#define BIT_MASK_BF1_LIFETIME_8822C 0xffff\n#define BIT_BF1_LIFETIME_8822C(x)                                              \\\n\t(((x) & BIT_MASK_BF1_LIFETIME_8822C) << BIT_SHIFT_BF1_LIFETIME_8822C)\n#define BITS_BF1_LIFETIME_8822C                                                \\\n\t(BIT_MASK_BF1_LIFETIME_8822C << BIT_SHIFT_BF1_LIFETIME_8822C)\n#define BIT_CLEAR_BF1_LIFETIME_8822C(x) ((x) & (~BITS_BF1_LIFETIME_8822C))\n#define BIT_GET_BF1_LIFETIME_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BF1_LIFETIME_8822C) & BIT_MASK_BF1_LIFETIME_8822C)\n#define BIT_SET_BF1_LIFETIME_8822C(x, v)                                       \\\n\t(BIT_CLEAR_BF1_LIFETIME_8822C(x) | BIT_BF1_LIFETIME_8822C(v))\n\n/* 2 REG_BF_TIMEOUT_EN_8822C */\n#define BIT_EN_VHT_LDPC_8822C BIT(9)\n#define BIT_EN_HT_LDPC_8822C BIT(8)\n#define BIT_BF1_TIMEOUT_EN_8822C BIT(1)\n#define BIT_BF0_TIMEOUT_EN_8822C BIT(0)\n\n/* 2 REG_MACID_RELEASE0_8822C */\n\n#define BIT_SHIFT_MACID31_0_RELEASE_8822C 0\n#define BIT_MASK_MACID31_0_RELEASE_8822C 0xffffffffL\n#define BIT_MACID31_0_RELEASE_8822C(x)                                         \\\n\t(((x) & BIT_MASK_MACID31_0_RELEASE_8822C)                              \\\n\t << BIT_SHIFT_MACID31_0_RELEASE_8822C)\n#define BITS_MACID31_0_RELEASE_8822C                                           \\\n\t(BIT_MASK_MACID31_0_RELEASE_8822C << BIT_SHIFT_MACID31_0_RELEASE_8822C)\n#define BIT_CLEAR_MACID31_0_RELEASE_8822C(x)                                   \\\n\t((x) & (~BITS_MACID31_0_RELEASE_8822C))\n#define BIT_GET_MACID31_0_RELEASE_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_MACID31_0_RELEASE_8822C) &                          \\\n\t BIT_MASK_MACID31_0_RELEASE_8822C)\n#define BIT_SET_MACID31_0_RELEASE_8822C(x, v)                                  \\\n\t(BIT_CLEAR_MACID31_0_RELEASE_8822C(x) | BIT_MACID31_0_RELEASE_8822C(v))\n\n/* 2 REG_MACID_RELEASE1_8822C */\n\n#define BIT_SHIFT_MACID63_32_RELEASE_8822C 0\n#define BIT_MASK_MACID63_32_RELEASE_8822C 0xffffffffL\n#define BIT_MACID63_32_RELEASE_8822C(x)                                        \\\n\t(((x) & BIT_MASK_MACID63_32_RELEASE_8822C)                             \\\n\t << BIT_SHIFT_MACID63_32_RELEASE_8822C)\n#define BITS_MACID63_32_RELEASE_8822C                                          \\\n\t(BIT_MASK_MACID63_32_RELEASE_8822C                                     \\\n\t << BIT_SHIFT_MACID63_32_RELEASE_8822C)\n#define BIT_CLEAR_MACID63_32_RELEASE_8822C(x)                                  \\\n\t((x) & (~BITS_MACID63_32_RELEASE_8822C))\n#define BIT_GET_MACID63_32_RELEASE_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACID63_32_RELEASE_8822C) &                         \\\n\t BIT_MASK_MACID63_32_RELEASE_8822C)\n#define BIT_SET_MACID63_32_RELEASE_8822C(x, v)                                 \\\n\t(BIT_CLEAR_MACID63_32_RELEASE_8822C(x) |                               \\\n\t BIT_MACID63_32_RELEASE_8822C(v))\n\n/* 2 REG_MACID_RELEASE2_8822C */\n\n#define BIT_SHIFT_MACID95_64_RELEASE_8822C 0\n#define BIT_MASK_MACID95_64_RELEASE_8822C 0xffffffffL\n#define BIT_MACID95_64_RELEASE_8822C(x)                                        \\\n\t(((x) & BIT_MASK_MACID95_64_RELEASE_8822C)                             \\\n\t << BIT_SHIFT_MACID95_64_RELEASE_8822C)\n#define BITS_MACID95_64_RELEASE_8822C                                          \\\n\t(BIT_MASK_MACID95_64_RELEASE_8822C                                     \\\n\t << BIT_SHIFT_MACID95_64_RELEASE_8822C)\n#define BIT_CLEAR_MACID95_64_RELEASE_8822C(x)                                  \\\n\t((x) & (~BITS_MACID95_64_RELEASE_8822C))\n#define BIT_GET_MACID95_64_RELEASE_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_MACID95_64_RELEASE_8822C) &                         \\\n\t BIT_MASK_MACID95_64_RELEASE_8822C)\n#define BIT_SET_MACID95_64_RELEASE_8822C(x, v)                                 \\\n\t(BIT_CLEAR_MACID95_64_RELEASE_8822C(x) |                               \\\n\t BIT_MACID95_64_RELEASE_8822C(v))\n\n/* 2 REG_MACID_RELEASE3_8822C */\n\n#define BIT_SHIFT_MACID127_96_RELEASE_8822C 0\n#define BIT_MASK_MACID127_96_RELEASE_8822C 0xffffffffL\n#define BIT_MACID127_96_RELEASE_8822C(x)                                       \\\n\t(((x) & BIT_MASK_MACID127_96_RELEASE_8822C)                            \\\n\t << BIT_SHIFT_MACID127_96_RELEASE_8822C)\n#define BITS_MACID127_96_RELEASE_8822C                                         \\\n\t(BIT_MASK_MACID127_96_RELEASE_8822C                                    \\\n\t << BIT_SHIFT_MACID127_96_RELEASE_8822C)\n#define BIT_CLEAR_MACID127_96_RELEASE_8822C(x)                                 \\\n\t((x) & (~BITS_MACID127_96_RELEASE_8822C))\n#define BIT_GET_MACID127_96_RELEASE_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_MACID127_96_RELEASE_8822C) &                        \\\n\t BIT_MASK_MACID127_96_RELEASE_8822C)\n#define BIT_SET_MACID127_96_RELEASE_8822C(x, v)                                \\\n\t(BIT_CLEAR_MACID127_96_RELEASE_8822C(x) |                              \\\n\t BIT_MACID127_96_RELEASE_8822C(v))\n\n/* 2 REG_MACID_RELEASE_SETTING_8822C */\n#define BIT_MACID_VALUE_8822C BIT(7)\n\n#define BIT_SHIFT_MACID_OFFSET_8822C 0\n#define BIT_MASK_MACID_OFFSET_8822C 0x7f\n#define BIT_MACID_OFFSET_8822C(x)                                              \\\n\t(((x) & BIT_MASK_MACID_OFFSET_8822C) << BIT_SHIFT_MACID_OFFSET_8822C)\n#define BITS_MACID_OFFSET_8822C                                                \\\n\t(BIT_MASK_MACID_OFFSET_8822C << BIT_SHIFT_MACID_OFFSET_8822C)\n#define BIT_CLEAR_MACID_OFFSET_8822C(x) ((x) & (~BITS_MACID_OFFSET_8822C))\n#define BIT_GET_MACID_OFFSET_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_MACID_OFFSET_8822C) & BIT_MASK_MACID_OFFSET_8822C)\n#define BIT_SET_MACID_OFFSET_8822C(x, v)                                       \\\n\t(BIT_CLEAR_MACID_OFFSET_8822C(x) | BIT_MACID_OFFSET_8822C(v))\n\n/* 2 REG_FAST_EDCA_VOVI_SETTING_8822C */\n\n#define BIT_SHIFT_VI_FAST_EDCA_TO_8822C 24\n#define BIT_MASK_VI_FAST_EDCA_TO_8822C 0xff\n#define BIT_VI_FAST_EDCA_TO_8822C(x)                                           \\\n\t(((x) & BIT_MASK_VI_FAST_EDCA_TO_8822C)                                \\\n\t << BIT_SHIFT_VI_FAST_EDCA_TO_8822C)\n#define BITS_VI_FAST_EDCA_TO_8822C                                             \\\n\t(BIT_MASK_VI_FAST_EDCA_TO_8822C << BIT_SHIFT_VI_FAST_EDCA_TO_8822C)\n#define BIT_CLEAR_VI_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8822C))\n#define BIT_GET_VI_FAST_EDCA_TO_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8822C) &                            \\\n\t BIT_MASK_VI_FAST_EDCA_TO_8822C)\n#define BIT_SET_VI_FAST_EDCA_TO_8822C(x, v)                                    \\\n\t(BIT_CLEAR_VI_FAST_EDCA_TO_8822C(x) | BIT_VI_FAST_EDCA_TO_8822C(v))\n\n#define BIT_VI_THRESHOLD_SEL_8822C BIT(23)\n\n#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C 16\n#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C 0x7f\n#define BIT_VI_FAST_EDCA_PKT_TH_8822C(x)                                       \\\n\t(((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C)                            \\\n\t << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C)\n#define BITS_VI_FAST_EDCA_PKT_TH_8822C                                         \\\n\t(BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C                                    \\\n\t << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C)\n#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822C(x)                                 \\\n\t((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8822C))\n#define BIT_GET_VI_FAST_EDCA_PKT_TH_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C) &                        \\\n\t BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C)\n#define BIT_SET_VI_FAST_EDCA_PKT_TH_8822C(x, v)                                \\\n\t(BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822C(x) |                              \\\n\t BIT_VI_FAST_EDCA_PKT_TH_8822C(v))\n\n#define BIT_SHIFT_VO_FAST_EDCA_TO_8822C 8\n#define BIT_MASK_VO_FAST_EDCA_TO_8822C 0xff\n#define BIT_VO_FAST_EDCA_TO_8822C(x)                                           \\\n\t(((x) & BIT_MASK_VO_FAST_EDCA_TO_8822C)                                \\\n\t << BIT_SHIFT_VO_FAST_EDCA_TO_8822C)\n#define BITS_VO_FAST_EDCA_TO_8822C                                             \\\n\t(BIT_MASK_VO_FAST_EDCA_TO_8822C << BIT_SHIFT_VO_FAST_EDCA_TO_8822C)\n#define BIT_CLEAR_VO_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8822C))\n#define BIT_GET_VO_FAST_EDCA_TO_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8822C) &                            \\\n\t BIT_MASK_VO_FAST_EDCA_TO_8822C)\n#define BIT_SET_VO_FAST_EDCA_TO_8822C(x, v)                                    \\\n\t(BIT_CLEAR_VO_FAST_EDCA_TO_8822C(x) | BIT_VO_FAST_EDCA_TO_8822C(v))\n\n#define BIT_VO_THRESHOLD_SEL_8822C BIT(7)\n\n#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C 0\n#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C 0x7f\n#define BIT_VO_FAST_EDCA_PKT_TH_8822C(x)                                       \\\n\t(((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C)                            \\\n\t << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C)\n#define BITS_VO_FAST_EDCA_PKT_TH_8822C                                         \\\n\t(BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C                                    \\\n\t << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C)\n#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822C(x)                                 \\\n\t((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8822C))\n#define BIT_GET_VO_FAST_EDCA_PKT_TH_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C) &                        \\\n\t BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C)\n#define BIT_SET_VO_FAST_EDCA_PKT_TH_8822C(x, v)                                \\\n\t(BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822C(x) |                              \\\n\t BIT_VO_FAST_EDCA_PKT_TH_8822C(v))\n\n/* 2 REG_FAST_EDCA_BEBK_SETTING_8822C */\n\n#define BIT_SHIFT_BK_FAST_EDCA_TO_8822C 24\n#define BIT_MASK_BK_FAST_EDCA_TO_8822C 0xff\n#define BIT_BK_FAST_EDCA_TO_8822C(x)                                           \\\n\t(((x) & BIT_MASK_BK_FAST_EDCA_TO_8822C)                                \\\n\t << BIT_SHIFT_BK_FAST_EDCA_TO_8822C)\n#define BITS_BK_FAST_EDCA_TO_8822C                                             \\\n\t(BIT_MASK_BK_FAST_EDCA_TO_8822C << BIT_SHIFT_BK_FAST_EDCA_TO_8822C)\n#define BIT_CLEAR_BK_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8822C))\n#define BIT_GET_BK_FAST_EDCA_TO_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8822C) &                            \\\n\t BIT_MASK_BK_FAST_EDCA_TO_8822C)\n#define BIT_SET_BK_FAST_EDCA_TO_8822C(x, v)                                    \\\n\t(BIT_CLEAR_BK_FAST_EDCA_TO_8822C(x) | BIT_BK_FAST_EDCA_TO_8822C(v))\n\n#define BIT_BK_THRESHOLD_SEL_8822C BIT(23)\n\n#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C 16\n#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C 0x7f\n#define BIT_BK_FAST_EDCA_PKT_TH_8822C(x)                                       \\\n\t(((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C)                            \\\n\t << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C)\n#define BITS_BK_FAST_EDCA_PKT_TH_8822C                                         \\\n\t(BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C                                    \\\n\t << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C)\n#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822C(x)                                 \\\n\t((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8822C))\n#define BIT_GET_BK_FAST_EDCA_PKT_TH_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C) &                        \\\n\t BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C)\n#define BIT_SET_BK_FAST_EDCA_PKT_TH_8822C(x, v)                                \\\n\t(BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822C(x) |                              \\\n\t BIT_BK_FAST_EDCA_PKT_TH_8822C(v))\n\n#define BIT_SHIFT_BE_FAST_EDCA_TO_8822C 8\n#define BIT_MASK_BE_FAST_EDCA_TO_8822C 0xff\n#define BIT_BE_FAST_EDCA_TO_8822C(x)                                           \\\n\t(((x) & BIT_MASK_BE_FAST_EDCA_TO_8822C)                                \\\n\t << BIT_SHIFT_BE_FAST_EDCA_TO_8822C)\n#define BITS_BE_FAST_EDCA_TO_8822C                                             \\\n\t(BIT_MASK_BE_FAST_EDCA_TO_8822C << BIT_SHIFT_BE_FAST_EDCA_TO_8822C)\n#define BIT_CLEAR_BE_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8822C))\n#define BIT_GET_BE_FAST_EDCA_TO_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8822C) &                            \\\n\t BIT_MASK_BE_FAST_EDCA_TO_8822C)\n#define BIT_SET_BE_FAST_EDCA_TO_8822C(x, v)                                    \\\n\t(BIT_CLEAR_BE_FAST_EDCA_TO_8822C(x) | BIT_BE_FAST_EDCA_TO_8822C(v))\n\n#define BIT_BE_THRESHOLD_SEL_8822C BIT(7)\n\n#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C 0\n#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C 0x7f\n#define BIT_BE_FAST_EDCA_PKT_TH_8822C(x)                                       \\\n\t(((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C)                            \\\n\t << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C)\n#define BITS_BE_FAST_EDCA_PKT_TH_8822C                                         \\\n\t(BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C                                    \\\n\t << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C)\n#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822C(x)                                 \\\n\t((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8822C))\n#define BIT_GET_BE_FAST_EDCA_PKT_TH_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C) &                        \\\n\t BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C)\n#define BIT_SET_BE_FAST_EDCA_PKT_TH_8822C(x, v)                                \\\n\t(BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822C(x) |                              \\\n\t BIT_BE_FAST_EDCA_PKT_TH_8822C(v))\n\n/* 2 REG_MACID_DROP0_8822C */\n\n#define BIT_SHIFT_MACID31_0_DROP_8822C 0\n#define BIT_MASK_MACID31_0_DROP_8822C 0xffffffffL\n#define BIT_MACID31_0_DROP_8822C(x)                                            \\\n\t(((x) & BIT_MASK_MACID31_0_DROP_8822C)                                 \\\n\t << BIT_SHIFT_MACID31_0_DROP_8822C)\n#define BITS_MACID31_0_DROP_8822C                                              \\\n\t(BIT_MASK_MACID31_0_DROP_8822C << BIT_SHIFT_MACID31_0_DROP_8822C)\n#define BIT_CLEAR_MACID31_0_DROP_8822C(x) ((x) & (~BITS_MACID31_0_DROP_8822C))\n#define BIT_GET_MACID31_0_DROP_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_MACID31_0_DROP_8822C) &                             \\\n\t BIT_MASK_MACID31_0_DROP_8822C)\n#define BIT_SET_MACID31_0_DROP_8822C(x, v)                                     \\\n\t(BIT_CLEAR_MACID31_0_DROP_8822C(x) | BIT_MACID31_0_DROP_8822C(v))\n\n/* 2 REG_MACID_DROP1_8822C */\n\n#define BIT_SHIFT_MACID63_32_DROP_8822C 0\n#define BIT_MASK_MACID63_32_DROP_8822C 0xffffffffL\n#define BIT_MACID63_32_DROP_8822C(x)                                           \\\n\t(((x) & BIT_MASK_MACID63_32_DROP_8822C)                                \\\n\t << BIT_SHIFT_MACID63_32_DROP_8822C)\n#define BITS_MACID63_32_DROP_8822C                                             \\\n\t(BIT_MASK_MACID63_32_DROP_8822C << BIT_SHIFT_MACID63_32_DROP_8822C)\n#define BIT_CLEAR_MACID63_32_DROP_8822C(x) ((x) & (~BITS_MACID63_32_DROP_8822C))\n#define BIT_GET_MACID63_32_DROP_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_MACID63_32_DROP_8822C) &                            \\\n\t BIT_MASK_MACID63_32_DROP_8822C)\n#define BIT_SET_MACID63_32_DROP_8822C(x, v)                                    \\\n\t(BIT_CLEAR_MACID63_32_DROP_8822C(x) | BIT_MACID63_32_DROP_8822C(v))\n\n/* 2 REG_MACID_DROP2_8822C */\n\n#define BIT_SHIFT_MACID95_64_DROP_8822C 0\n#define BIT_MASK_MACID95_64_DROP_8822C 0xffffffffL\n#define BIT_MACID95_64_DROP_8822C(x)                                           \\\n\t(((x) & BIT_MASK_MACID95_64_DROP_8822C)                                \\\n\t << BIT_SHIFT_MACID95_64_DROP_8822C)\n#define BITS_MACID95_64_DROP_8822C                                             \\\n\t(BIT_MASK_MACID95_64_DROP_8822C << BIT_SHIFT_MACID95_64_DROP_8822C)\n#define BIT_CLEAR_MACID95_64_DROP_8822C(x) ((x) & (~BITS_MACID95_64_DROP_8822C))\n#define BIT_GET_MACID95_64_DROP_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_MACID95_64_DROP_8822C) &                            \\\n\t BIT_MASK_MACID95_64_DROP_8822C)\n#define BIT_SET_MACID95_64_DROP_8822C(x, v)                                    \\\n\t(BIT_CLEAR_MACID95_64_DROP_8822C(x) | BIT_MACID95_64_DROP_8822C(v))\n\n/* 2 REG_MACID_DROP3_8822C */\n\n#define BIT_SHIFT_MACID127_96_DROP_8822C 0\n#define BIT_MASK_MACID127_96_DROP_8822C 0xffffffffL\n#define BIT_MACID127_96_DROP_8822C(x)                                          \\\n\t(((x) & BIT_MASK_MACID127_96_DROP_8822C)                               \\\n\t << BIT_SHIFT_MACID127_96_DROP_8822C)\n#define BITS_MACID127_96_DROP_8822C                                            \\\n\t(BIT_MASK_MACID127_96_DROP_8822C << BIT_SHIFT_MACID127_96_DROP_8822C)\n#define BIT_CLEAR_MACID127_96_DROP_8822C(x)                                    \\\n\t((x) & (~BITS_MACID127_96_DROP_8822C))\n#define BIT_GET_MACID127_96_DROP_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_MACID127_96_DROP_8822C) &                           \\\n\t BIT_MASK_MACID127_96_DROP_8822C)\n#define BIT_SET_MACID127_96_DROP_8822C(x, v)                                   \\\n\t(BIT_CLEAR_MACID127_96_DROP_8822C(x) | BIT_MACID127_96_DROP_8822C(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8822C */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_0_8822C(x)                                 \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C)                      \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C)\n#define BITS_R_MACID_RELEASE_SUCCESS_0_8822C                                   \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C                              \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822C(x)                           \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8822C))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8822C(x)                             \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C) &                  \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8822C(x, v)                          \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822C(x) |                        \\\n\t BIT_R_MACID_RELEASE_SUCCESS_0_8822C(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8822C */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_1_8822C(x)                                 \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C)                      \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C)\n#define BITS_R_MACID_RELEASE_SUCCESS_1_8822C                                   \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C                              \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822C(x)                           \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8822C))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8822C(x)                             \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C) &                  \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8822C(x, v)                          \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822C(x) |                        \\\n\t BIT_R_MACID_RELEASE_SUCCESS_1_8822C(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8822C */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_2_8822C(x)                                 \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C)                      \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C)\n#define BITS_R_MACID_RELEASE_SUCCESS_2_8822C                                   \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C                              \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822C(x)                           \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8822C))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8822C(x)                             \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C) &                  \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8822C(x, v)                          \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822C(x) |                        \\\n\t BIT_R_MACID_RELEASE_SUCCESS_2_8822C(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8822C */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C 0xffffffffL\n#define BIT_R_MACID_RELEASE_SUCCESS_3_8822C(x)                                 \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C)                      \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C)\n#define BITS_R_MACID_RELEASE_SUCCESS_3_8822C                                   \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C                              \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822C(x)                           \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8822C))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8822C(x)                             \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C) &                  \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8822C(x, v)                          \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822C(x) |                        \\\n\t BIT_R_MACID_RELEASE_SUCCESS_3_8822C(v))\n\n/* 2 REG_MGQ_FIFO_WRITE_POINTER_8822C */\n#define BIT_MGQ_FIFO_OV_8822C BIT(7)\n#define BIT_MGQ_FIFO_WPTR_ERROR_8822C BIT(6)\n#define BIT_EN_MGQ_FIFO_LIFETIME_8822C BIT(5)\n\n#define BIT_SHIFT_MGQ_FIFO_WPTR_8822C 0\n#define BIT_MASK_MGQ_FIFO_WPTR_8822C 0x1f\n#define BIT_MGQ_FIFO_WPTR_8822C(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_FIFO_WPTR_8822C) << BIT_SHIFT_MGQ_FIFO_WPTR_8822C)\n#define BITS_MGQ_FIFO_WPTR_8822C                                               \\\n\t(BIT_MASK_MGQ_FIFO_WPTR_8822C << BIT_SHIFT_MGQ_FIFO_WPTR_8822C)\n#define BIT_CLEAR_MGQ_FIFO_WPTR_8822C(x) ((x) & (~BITS_MGQ_FIFO_WPTR_8822C))\n#define BIT_GET_MGQ_FIFO_WPTR_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_WPTR_8822C) & BIT_MASK_MGQ_FIFO_WPTR_8822C)\n#define BIT_SET_MGQ_FIFO_WPTR_8822C(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_FIFO_WPTR_8822C(x) | BIT_MGQ_FIFO_WPTR_8822C(v))\n\n/* 2 REG_MGQ_FIFO_READ_POINTER_8822C */\n\n#define BIT_SHIFT_MGQ_FIFO_SIZE_8822C 14\n#define BIT_MASK_MGQ_FIFO_SIZE_8822C 0x3\n#define BIT_MGQ_FIFO_SIZE_8822C(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_FIFO_SIZE_8822C) << BIT_SHIFT_MGQ_FIFO_SIZE_8822C)\n#define BITS_MGQ_FIFO_SIZE_8822C                                               \\\n\t(BIT_MASK_MGQ_FIFO_SIZE_8822C << BIT_SHIFT_MGQ_FIFO_SIZE_8822C)\n#define BIT_CLEAR_MGQ_FIFO_SIZE_8822C(x) ((x) & (~BITS_MGQ_FIFO_SIZE_8822C))\n#define BIT_GET_MGQ_FIFO_SIZE_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_SIZE_8822C) & BIT_MASK_MGQ_FIFO_SIZE_8822C)\n#define BIT_SET_MGQ_FIFO_SIZE_8822C(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_FIFO_SIZE_8822C(x) | BIT_MGQ_FIFO_SIZE_8822C(v))\n\n#define BIT_MGQ_FIFO_PAUSE_8822C BIT(13)\n\n#define BIT_SHIFT_MGQ_FIFO_RPTR_8822C 8\n#define BIT_MASK_MGQ_FIFO_RPTR_8822C 0x1f\n#define BIT_MGQ_FIFO_RPTR_8822C(x)                                             \\\n\t(((x) & BIT_MASK_MGQ_FIFO_RPTR_8822C) << BIT_SHIFT_MGQ_FIFO_RPTR_8822C)\n#define BITS_MGQ_FIFO_RPTR_8822C                                               \\\n\t(BIT_MASK_MGQ_FIFO_RPTR_8822C << BIT_SHIFT_MGQ_FIFO_RPTR_8822C)\n#define BIT_CLEAR_MGQ_FIFO_RPTR_8822C(x) ((x) & (~BITS_MGQ_FIFO_RPTR_8822C))\n#define BIT_GET_MGQ_FIFO_RPTR_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_RPTR_8822C) & BIT_MASK_MGQ_FIFO_RPTR_8822C)\n#define BIT_SET_MGQ_FIFO_RPTR_8822C(x, v)                                      \\\n\t(BIT_CLEAR_MGQ_FIFO_RPTR_8822C(x) | BIT_MGQ_FIFO_RPTR_8822C(v))\n\n/* 2 REG_MGQ_FIFO_ENABLE_8822C */\n#define BIT_MGQ_FIFO_EN_8822C BIT(15)\n\n#define BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C 12\n#define BIT_MASK_MGQ_FIFO_PG_SIZE_8822C 0x7\n#define BIT_MGQ_FIFO_PG_SIZE_8822C(x)                                          \\\n\t(((x) & BIT_MASK_MGQ_FIFO_PG_SIZE_8822C)                               \\\n\t << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C)\n#define BITS_MGQ_FIFO_PG_SIZE_8822C                                            \\\n\t(BIT_MASK_MGQ_FIFO_PG_SIZE_8822C << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C)\n#define BIT_CLEAR_MGQ_FIFO_PG_SIZE_8822C(x)                                    \\\n\t((x) & (~BITS_MGQ_FIFO_PG_SIZE_8822C))\n#define BIT_GET_MGQ_FIFO_PG_SIZE_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C) &                           \\\n\t BIT_MASK_MGQ_FIFO_PG_SIZE_8822C)\n#define BIT_SET_MGQ_FIFO_PG_SIZE_8822C(x, v)                                   \\\n\t(BIT_CLEAR_MGQ_FIFO_PG_SIZE_8822C(x) | BIT_MGQ_FIFO_PG_SIZE_8822C(v))\n\n#define BIT_SHIFT_MGQ_FIFO_START_PG_8822C 0\n#define BIT_MASK_MGQ_FIFO_START_PG_8822C 0xfff\n#define BIT_MGQ_FIFO_START_PG_8822C(x)                                         \\\n\t(((x) & BIT_MASK_MGQ_FIFO_START_PG_8822C)                              \\\n\t << BIT_SHIFT_MGQ_FIFO_START_PG_8822C)\n#define BITS_MGQ_FIFO_START_PG_8822C                                           \\\n\t(BIT_MASK_MGQ_FIFO_START_PG_8822C << BIT_SHIFT_MGQ_FIFO_START_PG_8822C)\n#define BIT_CLEAR_MGQ_FIFO_START_PG_8822C(x)                                   \\\n\t((x) & (~BITS_MGQ_FIFO_START_PG_8822C))\n#define BIT_GET_MGQ_FIFO_START_PG_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_START_PG_8822C) &                          \\\n\t BIT_MASK_MGQ_FIFO_START_PG_8822C)\n#define BIT_SET_MGQ_FIFO_START_PG_8822C(x, v)                                  \\\n\t(BIT_CLEAR_MGQ_FIFO_START_PG_8822C(x) | BIT_MGQ_FIFO_START_PG_8822C(v))\n\n/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK_8822C */\n\n#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C 0\n#define BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C 0xffff\n#define BIT_MGQ_FIFO_REL_INT_MASK_8822C(x)                                     \\\n\t(((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C)                          \\\n\t << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C)\n#define BITS_MGQ_FIFO_REL_INT_MASK_8822C                                       \\\n\t(BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C                                  \\\n\t << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C)\n#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8822C(x)                               \\\n\t((x) & (~BITS_MGQ_FIFO_REL_INT_MASK_8822C))\n#define BIT_GET_MGQ_FIFO_REL_INT_MASK_8822C(x)                                 \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C) &                      \\\n\t BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C)\n#define BIT_SET_MGQ_FIFO_REL_INT_MASK_8822C(x, v)                              \\\n\t(BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8822C(x) |                            \\\n\t BIT_MGQ_FIFO_REL_INT_MASK_8822C(v))\n\n/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG_8822C */\n\n#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C 0\n#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C 0xffff\n#define BIT_MGQ_FIFO_REL_INT_FLAG_8822C(x)                                     \\\n\t(((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C)                          \\\n\t << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C)\n#define BITS_MGQ_FIFO_REL_INT_FLAG_8822C                                       \\\n\t(BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C                                  \\\n\t << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C)\n#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8822C(x)                               \\\n\t((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG_8822C))\n#define BIT_GET_MGQ_FIFO_REL_INT_FLAG_8822C(x)                                 \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C) &                      \\\n\t BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C)\n#define BIT_SET_MGQ_FIFO_REL_INT_FLAG_8822C(x, v)                              \\\n\t(BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8822C(x) |                            \\\n\t BIT_MGQ_FIFO_REL_INT_FLAG_8822C(v))\n\n/* 2 REG_MGQ_FIFO_VALID_MAP_8822C */\n\n#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C 0\n#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C 0xffff\n#define BIT_MGQ_FIFO_PKT_VALID_MAP_8822C(x)                                    \\\n\t(((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C)                         \\\n\t << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C)\n#define BITS_MGQ_FIFO_PKT_VALID_MAP_8822C                                      \\\n\t(BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C                                 \\\n\t << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C)\n#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8822C(x)                              \\\n\t((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP_8822C))\n#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP_8822C(x)                                \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C) &                     \\\n\t BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C)\n#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP_8822C(x, v)                             \\\n\t(BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8822C(x) |                           \\\n\t BIT_MGQ_FIFO_PKT_VALID_MAP_8822C(v))\n\n/* 2 REG_MGQ_FIFO_LIFETIME_8822C */\n\n#define BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C 0\n#define BIT_MASK_MGQ_FIFO_LIFETIME_8822C 0xffff\n#define BIT_MGQ_FIFO_LIFETIME_8822C(x)                                         \\\n\t(((x) & BIT_MASK_MGQ_FIFO_LIFETIME_8822C)                              \\\n\t << BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C)\n#define BITS_MGQ_FIFO_LIFETIME_8822C                                           \\\n\t(BIT_MASK_MGQ_FIFO_LIFETIME_8822C << BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C)\n#define BIT_CLEAR_MGQ_FIFO_LIFETIME_8822C(x)                                   \\\n\t((x) & (~BITS_MGQ_FIFO_LIFETIME_8822C))\n#define BIT_GET_MGQ_FIFO_LIFETIME_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C) &                          \\\n\t BIT_MASK_MGQ_FIFO_LIFETIME_8822C)\n#define BIT_SET_MGQ_FIFO_LIFETIME_8822C(x, v)                                  \\\n\t(BIT_CLEAR_MGQ_FIFO_LIFETIME_8822C(x) | BIT_MGQ_FIFO_LIFETIME_8822C(v))\n\n/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C */\n\n#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C 0\n#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C 0x7f\n#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x)                      \\\n\t(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C)           \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C)\n#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C                        \\\n\t(BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C                   \\\n\t << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C)\n#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x)                \\\n\t((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C))\n#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x)                  \\\n\t(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C) &       \\\n\t BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C)\n#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x, v)               \\\n\t(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x) |             \\\n\t BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(v))\n\n/* 2 REG_SHCUT_SETTING_8822C */\n\n/* 2 REG_SHCUT_LLC_ETH_TYPE0_8822C */\n\n/* 2 REG_SHCUT_LLC_ETH_TYPE1_8822C */\n\n/* 2 REG_SHCUT_LLC_OUI0_8822C */\n\n/* 2 REG_SHCUT_LLC_OUI1_8822C */\n\n/* 2 REG_SHCUT_LLC_OUI2_8822C */\n\n/* 2 REG_MU_TX_CTL_8822C */\n#define BIT_R_MU_P1_WAIT_STATE_EN_8822C BIT(16)\n\n#define BIT_SHIFT_R_MU_RL_8822C 12\n#define BIT_MASK_R_MU_RL_8822C 0xf\n#define BIT_R_MU_RL_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_R_MU_RL_8822C) << BIT_SHIFT_R_MU_RL_8822C)\n#define BITS_R_MU_RL_8822C (BIT_MASK_R_MU_RL_8822C << BIT_SHIFT_R_MU_RL_8822C)\n#define BIT_CLEAR_R_MU_RL_8822C(x) ((x) & (~BITS_R_MU_RL_8822C))\n#define BIT_GET_R_MU_RL_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_R_MU_RL_8822C) & BIT_MASK_R_MU_RL_8822C)\n#define BIT_SET_R_MU_RL_8822C(x, v)                                            \\\n\t(BIT_CLEAR_R_MU_RL_8822C(x) | BIT_R_MU_RL_8822C(v))\n\n#define BIT_R_FORCE_P1_RATEDOWN_8822C BIT(11)\n\n#define BIT_SHIFT_R_MU_TAB_SEL_8822C 8\n#define BIT_MASK_R_MU_TAB_SEL_8822C 0x7\n#define BIT_R_MU_TAB_SEL_8822C(x)                                              \\\n\t(((x) & BIT_MASK_R_MU_TAB_SEL_8822C) << BIT_SHIFT_R_MU_TAB_SEL_8822C)\n#define BITS_R_MU_TAB_SEL_8822C                                                \\\n\t(BIT_MASK_R_MU_TAB_SEL_8822C << BIT_SHIFT_R_MU_TAB_SEL_8822C)\n#define BIT_CLEAR_R_MU_TAB_SEL_8822C(x) ((x) & (~BITS_R_MU_TAB_SEL_8822C))\n#define BIT_GET_R_MU_TAB_SEL_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_MU_TAB_SEL_8822C) & BIT_MASK_R_MU_TAB_SEL_8822C)\n#define BIT_SET_R_MU_TAB_SEL_8822C(x, v)                                       \\\n\t(BIT_CLEAR_R_MU_TAB_SEL_8822C(x) | BIT_R_MU_TAB_SEL_8822C(v))\n\n#define BIT_R_EN_MU_MIMO_8822C BIT(7)\n#define BIT_R_EN_REVERS_GTAB_8822C BIT(6)\n\n#define BIT_SHIFT_R_MU_TABLE_VALID_8822C 0\n#define BIT_MASK_R_MU_TABLE_VALID_8822C 0x3f\n#define BIT_R_MU_TABLE_VALID_8822C(x)                                          \\\n\t(((x) & BIT_MASK_R_MU_TABLE_VALID_8822C)                               \\\n\t << BIT_SHIFT_R_MU_TABLE_VALID_8822C)\n#define BITS_R_MU_TABLE_VALID_8822C                                            \\\n\t(BIT_MASK_R_MU_TABLE_VALID_8822C << BIT_SHIFT_R_MU_TABLE_VALID_8822C)\n#define BIT_CLEAR_R_MU_TABLE_VALID_8822C(x)                                    \\\n\t((x) & (~BITS_R_MU_TABLE_VALID_8822C))\n#define BIT_GET_R_MU_TABLE_VALID_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822C) &                           \\\n\t BIT_MASK_R_MU_TABLE_VALID_8822C)\n#define BIT_SET_R_MU_TABLE_VALID_8822C(x, v)                                   \\\n\t(BIT_CLEAR_R_MU_TABLE_VALID_8822C(x) | BIT_R_MU_TABLE_VALID_8822C(v))\n\n/* 2 REG_MU_STA_GID_VLD_8822C */\n\n#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C 0\n#define BIT_MASK_R_MU_STA_GTAB_VALID_8822C 0xffffffffL\n#define BIT_R_MU_STA_GTAB_VALID_8822C(x)                                       \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822C)                            \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C)\n#define BITS_R_MU_STA_GTAB_VALID_8822C                                         \\\n\t(BIT_MASK_R_MU_STA_GTAB_VALID_8822C                                    \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C)\n#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822C(x)                                 \\\n\t((x) & (~BITS_R_MU_STA_GTAB_VALID_8822C))\n#define BIT_GET_R_MU_STA_GTAB_VALID_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C) &                        \\\n\t BIT_MASK_R_MU_STA_GTAB_VALID_8822C)\n#define BIT_SET_R_MU_STA_GTAB_VALID_8822C(x, v)                                \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_VALID_8822C(x) |                              \\\n\t BIT_R_MU_STA_GTAB_VALID_8822C(v))\n\n/* 2 REG_MU_STA_USER_POS_INFO_8822C */\n\n#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C 0\n#define BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C 0xffffffffL\n#define BIT_R_MU_STA_GTAB_POSITION_L_8822C(x)                                  \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C)                       \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C)\n#define BITS_R_MU_STA_GTAB_POSITION_L_8822C                                    \\\n\t(BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C                               \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C)\n#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8822C(x)                            \\\n\t((x) & (~BITS_R_MU_STA_GTAB_POSITION_L_8822C))\n#define BIT_GET_R_MU_STA_GTAB_POSITION_L_8822C(x)                              \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C) &                   \\\n\t BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C)\n#define BIT_SET_R_MU_STA_GTAB_POSITION_L_8822C(x, v)                           \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8822C(x) |                         \\\n\t BIT_R_MU_STA_GTAB_POSITION_L_8822C(v))\n\n/* 2 REG_MU_STA_USER_POS_INFO_H_8822C */\n\n#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C 0\n#define BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C 0xffffffffL\n#define BIT_R_MU_STA_GTAB_POSITION_H_8822C(x)                                  \\\n\t(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C)                       \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C)\n#define BITS_R_MU_STA_GTAB_POSITION_H_8822C                                    \\\n\t(BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C                               \\\n\t << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C)\n#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8822C(x)                            \\\n\t((x) & (~BITS_R_MU_STA_GTAB_POSITION_H_8822C))\n#define BIT_GET_R_MU_STA_GTAB_POSITION_H_8822C(x)                              \\\n\t(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C) &                   \\\n\t BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C)\n#define BIT_SET_R_MU_STA_GTAB_POSITION_H_8822C(x, v)                           \\\n\t(BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8822C(x) |                         \\\n\t BIT_R_MU_STA_GTAB_POSITION_H_8822C(v))\n\n/* 2 REG_CHNL_INFO_CTRL_8822C */\n#define BIT_CHNL_REF_RXNAV_8822C BIT(7)\n#define BIT_CHNL_REF_VBON_8822C BIT(6)\n#define BIT_CHNL_REF_EDCA_8822C BIT(5)\n#define BIT_CHNL_REF_CCA_8822C BIT(4)\n#define BIT_RST_CHNL_BUSY_8822C BIT(3)\n#define BIT_RST_CHNL_IDLE_8822C BIT(2)\n#define BIT_CHNL_INFO_RST_8822C BIT(1)\n#define BIT_ATM_AIRTIME_EN_8822C BIT(0)\n\n/* 2 REG_CHNL_IDLE_TIME_8822C */\n\n#define BIT_SHIFT_CHNL_IDLE_TIME_8822C 0\n#define BIT_MASK_CHNL_IDLE_TIME_8822C 0xffffffffL\n#define BIT_CHNL_IDLE_TIME_8822C(x)                                            \\\n\t(((x) & BIT_MASK_CHNL_IDLE_TIME_8822C)                                 \\\n\t << BIT_SHIFT_CHNL_IDLE_TIME_8822C)\n#define BITS_CHNL_IDLE_TIME_8822C                                              \\\n\t(BIT_MASK_CHNL_IDLE_TIME_8822C << BIT_SHIFT_CHNL_IDLE_TIME_8822C)\n#define BIT_CLEAR_CHNL_IDLE_TIME_8822C(x) ((x) & (~BITS_CHNL_IDLE_TIME_8822C))\n#define BIT_GET_CHNL_IDLE_TIME_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8822C) &                             \\\n\t BIT_MASK_CHNL_IDLE_TIME_8822C)\n#define BIT_SET_CHNL_IDLE_TIME_8822C(x, v)                                     \\\n\t(BIT_CLEAR_CHNL_IDLE_TIME_8822C(x) | BIT_CHNL_IDLE_TIME_8822C(v))\n\n/* 2 REG_CHNL_BUSY_TIME_8822C */\n\n#define BIT_SHIFT_CHNL_BUSY_TIME_8822C 0\n#define BIT_MASK_CHNL_BUSY_TIME_8822C 0xffffffffL\n#define BIT_CHNL_BUSY_TIME_8822C(x)                                            \\\n\t(((x) & BIT_MASK_CHNL_BUSY_TIME_8822C)                                 \\\n\t << BIT_SHIFT_CHNL_BUSY_TIME_8822C)\n#define BITS_CHNL_BUSY_TIME_8822C                                              \\\n\t(BIT_MASK_CHNL_BUSY_TIME_8822C << BIT_SHIFT_CHNL_BUSY_TIME_8822C)\n#define BIT_CLEAR_CHNL_BUSY_TIME_8822C(x) ((x) & (~BITS_CHNL_BUSY_TIME_8822C))\n#define BIT_GET_CHNL_BUSY_TIME_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8822C) &                             \\\n\t BIT_MASK_CHNL_BUSY_TIME_8822C)\n#define BIT_SET_CHNL_BUSY_TIME_8822C(x, v)                                     \\\n\t(BIT_CLEAR_CHNL_BUSY_TIME_8822C(x) | BIT_CHNL_BUSY_TIME_8822C(v))\n\n/* 2 REG_MU_TRX_DBG_CNT_V1_8822C */\n#define BIT_MU_DNGCNT_RST_8822C BIT(20)\n\n#define BIT_SHIFT_MU_DNGCNT_SEL_8822C 16\n#define BIT_MASK_MU_DNGCNT_SEL_8822C 0xf\n#define BIT_MU_DNGCNT_SEL_8822C(x)                                             \\\n\t(((x) & BIT_MASK_MU_DNGCNT_SEL_8822C) << BIT_SHIFT_MU_DNGCNT_SEL_8822C)\n#define BITS_MU_DNGCNT_SEL_8822C                                               \\\n\t(BIT_MASK_MU_DNGCNT_SEL_8822C << BIT_SHIFT_MU_DNGCNT_SEL_8822C)\n#define BIT_CLEAR_MU_DNGCNT_SEL_8822C(x) ((x) & (~BITS_MU_DNGCNT_SEL_8822C))\n#define BIT_GET_MU_DNGCNT_SEL_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MU_DNGCNT_SEL_8822C) & BIT_MASK_MU_DNGCNT_SEL_8822C)\n#define BIT_SET_MU_DNGCNT_SEL_8822C(x, v)                                      \\\n\t(BIT_CLEAR_MU_DNGCNT_SEL_8822C(x) | BIT_MU_DNGCNT_SEL_8822C(v))\n\n#define BIT_SHIFT_MU_DNGCNT_8822C 0\n#define BIT_MASK_MU_DNGCNT_8822C 0xffff\n#define BIT_MU_DNGCNT_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_MU_DNGCNT_8822C) << BIT_SHIFT_MU_DNGCNT_8822C)\n#define BITS_MU_DNGCNT_8822C                                                   \\\n\t(BIT_MASK_MU_DNGCNT_8822C << BIT_SHIFT_MU_DNGCNT_8822C)\n#define BIT_CLEAR_MU_DNGCNT_8822C(x) ((x) & (~BITS_MU_DNGCNT_8822C))\n#define BIT_GET_MU_DNGCNT_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MU_DNGCNT_8822C) & BIT_MASK_MU_DNGCNT_8822C)\n#define BIT_SET_MU_DNGCNT_8822C(x, v)                                          \\\n\t(BIT_CLEAR_MU_DNGCNT_8822C(x) | BIT_MU_DNGCNT_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_EDCA_VO_PARAM_8822C */\n\n#define BIT_SHIFT_TXOPLIMIT_8822C 16\n#define BIT_MASK_TXOPLIMIT_8822C 0x7ff\n#define BIT_TXOPLIMIT_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C)\n#define BITS_TXOPLIMIT_8822C                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C)\n#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C))\n#define BIT_GET_TXOPLIMIT_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C)\n#define BIT_SET_TXOPLIMIT_8822C(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v))\n\n#define BIT_SHIFT_CW_8822C 8\n#define BIT_MASK_CW_8822C 0xff\n#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C)\n#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C)\n#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C))\n#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C)\n#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v))\n\n#define BIT_SHIFT_AIFS_8822C 0\n#define BIT_MASK_AIFS_8822C 0xff\n#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C)\n#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C)\n#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C))\n#define BIT_GET_AIFS_8822C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C)\n#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v))\n\n/* 2 REG_EDCA_VI_PARAM_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_TXOPLIMIT_8822C 16\n#define BIT_MASK_TXOPLIMIT_8822C 0x7ff\n#define BIT_TXOPLIMIT_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C)\n#define BITS_TXOPLIMIT_8822C                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C)\n#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C))\n#define BIT_GET_TXOPLIMIT_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C)\n#define BIT_SET_TXOPLIMIT_8822C(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v))\n\n#define BIT_SHIFT_CW_8822C 8\n#define BIT_MASK_CW_8822C 0xff\n#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C)\n#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C)\n#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C))\n#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C)\n#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v))\n\n#define BIT_SHIFT_AIFS_8822C 0\n#define BIT_MASK_AIFS_8822C 0xff\n#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C)\n#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C)\n#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C))\n#define BIT_GET_AIFS_8822C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C)\n#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v))\n\n/* 2 REG_EDCA_BE_PARAM_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_TXOPLIMIT_8822C 16\n#define BIT_MASK_TXOPLIMIT_8822C 0x7ff\n#define BIT_TXOPLIMIT_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C)\n#define BITS_TXOPLIMIT_8822C                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C)\n#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C))\n#define BIT_GET_TXOPLIMIT_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C)\n#define BIT_SET_TXOPLIMIT_8822C(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v))\n\n#define BIT_SHIFT_CW_8822C 8\n#define BIT_MASK_CW_8822C 0xff\n#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C)\n#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C)\n#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C))\n#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C)\n#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v))\n\n#define BIT_SHIFT_AIFS_8822C 0\n#define BIT_MASK_AIFS_8822C 0xff\n#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C)\n#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C)\n#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C))\n#define BIT_GET_AIFS_8822C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C)\n#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v))\n\n/* 2 REG_EDCA_BK_PARAM_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_TXOPLIMIT_8822C 16\n#define BIT_MASK_TXOPLIMIT_8822C 0x7ff\n#define BIT_TXOPLIMIT_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C)\n#define BITS_TXOPLIMIT_8822C                                                   \\\n\t(BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C)\n#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C))\n#define BIT_GET_TXOPLIMIT_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C)\n#define BIT_SET_TXOPLIMIT_8822C(x, v)                                          \\\n\t(BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v))\n\n#define BIT_SHIFT_CW_8822C 8\n#define BIT_MASK_CW_8822C 0xff\n#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C)\n#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C)\n#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C))\n#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C)\n#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v))\n\n#define BIT_SHIFT_AIFS_8822C 0\n#define BIT_MASK_AIFS_8822C 0xff\n#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C)\n#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C)\n#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C))\n#define BIT_GET_AIFS_8822C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C)\n#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v))\n\n/* 2 REG_BCNTCFG_8822C */\n\n#define BIT_SHIFT_BCNCW_MAX_8822C 12\n#define BIT_MASK_BCNCW_MAX_8822C 0xf\n#define BIT_BCNCW_MAX_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_BCNCW_MAX_8822C) << BIT_SHIFT_BCNCW_MAX_8822C)\n#define BITS_BCNCW_MAX_8822C                                                   \\\n\t(BIT_MASK_BCNCW_MAX_8822C << BIT_SHIFT_BCNCW_MAX_8822C)\n#define BIT_CLEAR_BCNCW_MAX_8822C(x) ((x) & (~BITS_BCNCW_MAX_8822C))\n#define BIT_GET_BCNCW_MAX_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNCW_MAX_8822C) & BIT_MASK_BCNCW_MAX_8822C)\n#define BIT_SET_BCNCW_MAX_8822C(x, v)                                          \\\n\t(BIT_CLEAR_BCNCW_MAX_8822C(x) | BIT_BCNCW_MAX_8822C(v))\n\n#define BIT_SHIFT_BCNCW_MIN_8822C 8\n#define BIT_MASK_BCNCW_MIN_8822C 0xf\n#define BIT_BCNCW_MIN_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_BCNCW_MIN_8822C) << BIT_SHIFT_BCNCW_MIN_8822C)\n#define BITS_BCNCW_MIN_8822C                                                   \\\n\t(BIT_MASK_BCNCW_MIN_8822C << BIT_SHIFT_BCNCW_MIN_8822C)\n#define BIT_CLEAR_BCNCW_MIN_8822C(x) ((x) & (~BITS_BCNCW_MIN_8822C))\n#define BIT_GET_BCNCW_MIN_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNCW_MIN_8822C) & BIT_MASK_BCNCW_MIN_8822C)\n#define BIT_SET_BCNCW_MIN_8822C(x, v)                                          \\\n\t(BIT_CLEAR_BCNCW_MIN_8822C(x) | BIT_BCNCW_MIN_8822C(v))\n\n#define BIT_SHIFT_BCNIFS_8822C 0\n#define BIT_MASK_BCNIFS_8822C 0xff\n#define BIT_BCNIFS_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_BCNIFS_8822C) << BIT_SHIFT_BCNIFS_8822C)\n#define BITS_BCNIFS_8822C (BIT_MASK_BCNIFS_8822C << BIT_SHIFT_BCNIFS_8822C)\n#define BIT_CLEAR_BCNIFS_8822C(x) ((x) & (~BITS_BCNIFS_8822C))\n#define BIT_GET_BCNIFS_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_BCNIFS_8822C) & BIT_MASK_BCNIFS_8822C)\n#define BIT_SET_BCNIFS_8822C(x, v)                                             \\\n\t(BIT_CLEAR_BCNIFS_8822C(x) | BIT_BCNIFS_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_PIFS_8822C */\n\n#define BIT_SHIFT_PIFS_8822C 0\n#define BIT_MASK_PIFS_8822C 0xff\n#define BIT_PIFS_8822C(x) (((x) & BIT_MASK_PIFS_8822C) << BIT_SHIFT_PIFS_8822C)\n#define BITS_PIFS_8822C (BIT_MASK_PIFS_8822C << BIT_SHIFT_PIFS_8822C)\n#define BIT_CLEAR_PIFS_8822C(x) ((x) & (~BITS_PIFS_8822C))\n#define BIT_GET_PIFS_8822C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_PIFS_8822C) & BIT_MASK_PIFS_8822C)\n#define BIT_SET_PIFS_8822C(x, v) (BIT_CLEAR_PIFS_8822C(x) | BIT_PIFS_8822C(v))\n\n/* 2 REG_RDG_PIFS_8822C */\n\n#define BIT_SHIFT_RDG_PIFS_8822C 0\n#define BIT_MASK_RDG_PIFS_8822C 0xff\n#define BIT_RDG_PIFS_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_RDG_PIFS_8822C) << BIT_SHIFT_RDG_PIFS_8822C)\n#define BITS_RDG_PIFS_8822C                                                    \\\n\t(BIT_MASK_RDG_PIFS_8822C << BIT_SHIFT_RDG_PIFS_8822C)\n#define BIT_CLEAR_RDG_PIFS_8822C(x) ((x) & (~BITS_RDG_PIFS_8822C))\n#define BIT_GET_RDG_PIFS_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RDG_PIFS_8822C) & BIT_MASK_RDG_PIFS_8822C)\n#define BIT_SET_RDG_PIFS_8822C(x, v)                                           \\\n\t(BIT_CLEAR_RDG_PIFS_8822C(x) | BIT_RDG_PIFS_8822C(v))\n\n/* 2 REG_SIFS_8822C */\n\n#define BIT_SHIFT_SIFS_OFDM_TRX_8822C 24\n#define BIT_MASK_SIFS_OFDM_TRX_8822C 0xff\n#define BIT_SIFS_OFDM_TRX_8822C(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_OFDM_TRX_8822C) << BIT_SHIFT_SIFS_OFDM_TRX_8822C)\n#define BITS_SIFS_OFDM_TRX_8822C                                               \\\n\t(BIT_MASK_SIFS_OFDM_TRX_8822C << BIT_SHIFT_SIFS_OFDM_TRX_8822C)\n#define BIT_CLEAR_SIFS_OFDM_TRX_8822C(x) ((x) & (~BITS_SIFS_OFDM_TRX_8822C))\n#define BIT_GET_SIFS_OFDM_TRX_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8822C) & BIT_MASK_SIFS_OFDM_TRX_8822C)\n#define BIT_SET_SIFS_OFDM_TRX_8822C(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_OFDM_TRX_8822C(x) | BIT_SIFS_OFDM_TRX_8822C(v))\n\n#define BIT_SHIFT_SIFS_CCK_TRX_8822C 16\n#define BIT_MASK_SIFS_CCK_TRX_8822C 0xff\n#define BIT_SIFS_CCK_TRX_8822C(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_CCK_TRX_8822C) << BIT_SHIFT_SIFS_CCK_TRX_8822C)\n#define BITS_SIFS_CCK_TRX_8822C                                                \\\n\t(BIT_MASK_SIFS_CCK_TRX_8822C << BIT_SHIFT_SIFS_CCK_TRX_8822C)\n#define BIT_CLEAR_SIFS_CCK_TRX_8822C(x) ((x) & (~BITS_SIFS_CCK_TRX_8822C))\n#define BIT_GET_SIFS_CCK_TRX_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_CCK_TRX_8822C) & BIT_MASK_SIFS_CCK_TRX_8822C)\n#define BIT_SET_SIFS_CCK_TRX_8822C(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_CCK_TRX_8822C(x) | BIT_SIFS_CCK_TRX_8822C(v))\n\n#define BIT_SHIFT_SIFS_OFDM_CTX_8822C 8\n#define BIT_MASK_SIFS_OFDM_CTX_8822C 0xff\n#define BIT_SIFS_OFDM_CTX_8822C(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_OFDM_CTX_8822C) << BIT_SHIFT_SIFS_OFDM_CTX_8822C)\n#define BITS_SIFS_OFDM_CTX_8822C                                               \\\n\t(BIT_MASK_SIFS_OFDM_CTX_8822C << BIT_SHIFT_SIFS_OFDM_CTX_8822C)\n#define BIT_CLEAR_SIFS_OFDM_CTX_8822C(x) ((x) & (~BITS_SIFS_OFDM_CTX_8822C))\n#define BIT_GET_SIFS_OFDM_CTX_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8822C) & BIT_MASK_SIFS_OFDM_CTX_8822C)\n#define BIT_SET_SIFS_OFDM_CTX_8822C(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_OFDM_CTX_8822C(x) | BIT_SIFS_OFDM_CTX_8822C(v))\n\n#define BIT_SHIFT_SIFS_CCK_CTX_8822C 0\n#define BIT_MASK_SIFS_CCK_CTX_8822C 0xff\n#define BIT_SIFS_CCK_CTX_8822C(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_CCK_CTX_8822C) << BIT_SHIFT_SIFS_CCK_CTX_8822C)\n#define BITS_SIFS_CCK_CTX_8822C                                                \\\n\t(BIT_MASK_SIFS_CCK_CTX_8822C << BIT_SHIFT_SIFS_CCK_CTX_8822C)\n#define BIT_CLEAR_SIFS_CCK_CTX_8822C(x) ((x) & (~BITS_SIFS_CCK_CTX_8822C))\n#define BIT_GET_SIFS_CCK_CTX_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_CCK_CTX_8822C) & BIT_MASK_SIFS_CCK_CTX_8822C)\n#define BIT_SET_SIFS_CCK_CTX_8822C(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_CCK_CTX_8822C(x) | BIT_SIFS_CCK_CTX_8822C(v))\n\n/* 2 REG_TSFTR_SYN_OFFSET_8822C */\n\n#define BIT_SHIFT_TSFTR_SNC_OFFSET_8822C 0\n#define BIT_MASK_TSFTR_SNC_OFFSET_8822C 0xffff\n#define BIT_TSFTR_SNC_OFFSET_8822C(x)                                          \\\n\t(((x) & BIT_MASK_TSFTR_SNC_OFFSET_8822C)                               \\\n\t << BIT_SHIFT_TSFTR_SNC_OFFSET_8822C)\n#define BITS_TSFTR_SNC_OFFSET_8822C                                            \\\n\t(BIT_MASK_TSFTR_SNC_OFFSET_8822C << BIT_SHIFT_TSFTR_SNC_OFFSET_8822C)\n#define BIT_CLEAR_TSFTR_SNC_OFFSET_8822C(x)                                    \\\n\t((x) & (~BITS_TSFTR_SNC_OFFSET_8822C))\n#define BIT_GET_TSFTR_SNC_OFFSET_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8822C) &                           \\\n\t BIT_MASK_TSFTR_SNC_OFFSET_8822C)\n#define BIT_SET_TSFTR_SNC_OFFSET_8822C(x, v)                                   \\\n\t(BIT_CLEAR_TSFTR_SNC_OFFSET_8822C(x) | BIT_TSFTR_SNC_OFFSET_8822C(v))\n\n/* 2 REG_AGGR_BREAK_TIME_8822C */\n\n#define BIT_SHIFT_AGGR_BK_TIME_8822C 0\n#define BIT_MASK_AGGR_BK_TIME_8822C 0xff\n#define BIT_AGGR_BK_TIME_8822C(x)                                              \\\n\t(((x) & BIT_MASK_AGGR_BK_TIME_8822C) << BIT_SHIFT_AGGR_BK_TIME_8822C)\n#define BITS_AGGR_BK_TIME_8822C                                                \\\n\t(BIT_MASK_AGGR_BK_TIME_8822C << BIT_SHIFT_AGGR_BK_TIME_8822C)\n#define BIT_CLEAR_AGGR_BK_TIME_8822C(x) ((x) & (~BITS_AGGR_BK_TIME_8822C))\n#define BIT_GET_AGGR_BK_TIME_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_AGGR_BK_TIME_8822C) & BIT_MASK_AGGR_BK_TIME_8822C)\n#define BIT_SET_AGGR_BK_TIME_8822C(x, v)                                       \\\n\t(BIT_CLEAR_AGGR_BK_TIME_8822C(x) | BIT_AGGR_BK_TIME_8822C(v))\n\n/* 2 REG_SLOT_8822C */\n\n#define BIT_SHIFT_SLOT_8822C 0\n#define BIT_MASK_SLOT_8822C 0xff\n#define BIT_SLOT_8822C(x) (((x) & BIT_MASK_SLOT_8822C) << BIT_SHIFT_SLOT_8822C)\n#define BITS_SLOT_8822C (BIT_MASK_SLOT_8822C << BIT_SHIFT_SLOT_8822C)\n#define BIT_CLEAR_SLOT_8822C(x) ((x) & (~BITS_SLOT_8822C))\n#define BIT_GET_SLOT_8822C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_SLOT_8822C) & BIT_MASK_SLOT_8822C)\n#define BIT_SET_SLOT_8822C(x, v) (BIT_CLEAR_SLOT_8822C(x) | BIT_SLOT_8822C(v))\n\n/* 2 REG_NOA_ON_ERLY_TIME_8822C */\n\n#define BIT_SHIFT__NOA_ON_ERLY_TIME_8822C 0\n#define BIT_MASK__NOA_ON_ERLY_TIME_8822C 0xff\n#define BIT__NOA_ON_ERLY_TIME_8822C(x)                                         \\\n\t(((x) & BIT_MASK__NOA_ON_ERLY_TIME_8822C)                              \\\n\t << BIT_SHIFT__NOA_ON_ERLY_TIME_8822C)\n#define BITS__NOA_ON_ERLY_TIME_8822C                                           \\\n\t(BIT_MASK__NOA_ON_ERLY_TIME_8822C << BIT_SHIFT__NOA_ON_ERLY_TIME_8822C)\n#define BIT_CLEAR__NOA_ON_ERLY_TIME_8822C(x)                                   \\\n\t((x) & (~BITS__NOA_ON_ERLY_TIME_8822C))\n#define BIT_GET__NOA_ON_ERLY_TIME_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME_8822C) &                          \\\n\t BIT_MASK__NOA_ON_ERLY_TIME_8822C)\n#define BIT_SET__NOA_ON_ERLY_TIME_8822C(x, v)                                  \\\n\t(BIT_CLEAR__NOA_ON_ERLY_TIME_8822C(x) | BIT__NOA_ON_ERLY_TIME_8822C(v))\n\n/* 2 REG_NOA_OFF_ERLY_TIME_8822C */\n\n#define BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C 0\n#define BIT_MASK__NOA_OFF_ERLY_TIME_8822C 0xff\n#define BIT__NOA_OFF_ERLY_TIME_8822C(x)                                        \\\n\t(((x) & BIT_MASK__NOA_OFF_ERLY_TIME_8822C)                             \\\n\t << BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C)\n#define BITS__NOA_OFF_ERLY_TIME_8822C                                          \\\n\t(BIT_MASK__NOA_OFF_ERLY_TIME_8822C                                     \\\n\t << BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C)\n#define BIT_CLEAR__NOA_OFF_ERLY_TIME_8822C(x)                                  \\\n\t((x) & (~BITS__NOA_OFF_ERLY_TIME_8822C))\n#define BIT_GET__NOA_OFF_ERLY_TIME_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C) &                         \\\n\t BIT_MASK__NOA_OFF_ERLY_TIME_8822C)\n#define BIT_SET__NOA_OFF_ERLY_TIME_8822C(x, v)                                 \\\n\t(BIT_CLEAR__NOA_OFF_ERLY_TIME_8822C(x) |                               \\\n\t BIT__NOA_OFF_ERLY_TIME_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_TX_PTCL_CTRL_8822C */\n#define BIT_DIS_EDCCA_8822C BIT(15)\n#define BIT_DIS_CCA_8822C BIT(14)\n#define BIT_LSIG_TXOP_TXCMD_NAV_8822C BIT(13)\n#define BIT_SIFS_BK_EN_8822C BIT(12)\n\n#define BIT_SHIFT_TXQ_NAV_MSK_8822C 8\n#define BIT_MASK_TXQ_NAV_MSK_8822C 0xf\n#define BIT_TXQ_NAV_MSK_8822C(x)                                               \\\n\t(((x) & BIT_MASK_TXQ_NAV_MSK_8822C) << BIT_SHIFT_TXQ_NAV_MSK_8822C)\n#define BITS_TXQ_NAV_MSK_8822C                                                 \\\n\t(BIT_MASK_TXQ_NAV_MSK_8822C << BIT_SHIFT_TXQ_NAV_MSK_8822C)\n#define BIT_CLEAR_TXQ_NAV_MSK_8822C(x) ((x) & (~BITS_TXQ_NAV_MSK_8822C))\n#define BIT_GET_TXQ_NAV_MSK_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_TXQ_NAV_MSK_8822C) & BIT_MASK_TXQ_NAV_MSK_8822C)\n#define BIT_SET_TXQ_NAV_MSK_8822C(x, v)                                        \\\n\t(BIT_CLEAR_TXQ_NAV_MSK_8822C(x) | BIT_TXQ_NAV_MSK_8822C(v))\n\n#define BIT_DIS_CW_8822C BIT(7)\n#define BIT_NAV_END_TXOP_8822C BIT(6)\n#define BIT_RDG_END_TXOP_8822C BIT(5)\n#define BIT_AC_INBCN_HOLD_8822C BIT(4)\n#define BIT_MGTQ_TXOP_EN_8822C BIT(3)\n#define BIT_MGTQ_RTSMF_EN_8822C BIT(2)\n#define BIT_HIQ_RTSMF_EN_8822C BIT(1)\n#define BIT_BCN_RTSMF_EN_8822C BIT(0)\n\n/* 2 REG_TXPAUSE_8822C */\n#define BIT_STOP_BCN_HI_MGT_8822C BIT(7)\n#define BIT_MAC_STOPBCNQ_8822C BIT(6)\n#define BIT_MAC_STOPHIQ_8822C BIT(5)\n#define BIT_MAC_STOPMGQ_8822C BIT(4)\n#define BIT_MAC_STOPBK_8822C BIT(3)\n#define BIT_MAC_STOPBE_8822C BIT(2)\n#define BIT_MAC_STOPVI_8822C BIT(1)\n#define BIT_MAC_STOPVO_8822C BIT(0)\n\n/* 2 REG_DIS_TXREQ_CLR_8822C */\n#define BIT_DIS_BT_CCA_8822C BIT(7)\n#define BIT_DIS_TXREQ_CLR_HI_8822C BIT(5)\n#define BIT_DIS_TXREQ_CLR_MGQ_8822C BIT(4)\n#define BIT_DIS_TXREQ_CLR_VO_8822C BIT(3)\n#define BIT_DIS_TXREQ_CLR_VI_8822C BIT(2)\n#define BIT_DIS_TXREQ_CLR_BE_8822C BIT(1)\n#define BIT_DIS_TXREQ_CLR_BK_8822C BIT(0)\n\n/* 2 REG_RD_CTRL_8822C */\n#define BIT_EN_CLR_TXREQ_INCCA_8822C BIT(15)\n#define BIT_DIS_TX_OVER_BCNQ_8822C BIT(14)\n#define BIT_EN_BCNERR_INCCCA_8822C BIT(13)\n#define BIT_EDCCA_MSK_CNTDOWN_EN_8822C BIT(11)\n#define BIT_DIS_TXOP_CFE_8822C BIT(10)\n#define BIT_DIS_LSIG_CFE_8822C BIT(9)\n#define BIT_DIS_STBC_CFE_8822C BIT(8)\n#define BIT_BKQ_RD_INIT_EN_8822C BIT(7)\n#define BIT_BEQ_RD_INIT_EN_8822C BIT(6)\n#define BIT_VIQ_RD_INIT_EN_8822C BIT(5)\n#define BIT_VOQ_RD_INIT_EN_8822C BIT(4)\n#define BIT_BKQ_RD_RESP_EN_8822C BIT(3)\n#define BIT_BEQ_RD_RESP_EN_8822C BIT(2)\n#define BIT_VIQ_RD_RESP_EN_8822C BIT(1)\n#define BIT_VOQ_RD_RESP_EN_8822C BIT(0)\n\n/* 2 REG_MBSSID_CTRL_8822C */\n#define BIT_MBID_BCNQ7_EN_8822C BIT(7)\n#define BIT_MBID_BCNQ6_EN_8822C BIT(6)\n#define BIT_MBID_BCNQ5_EN_8822C BIT(5)\n#define BIT_MBID_BCNQ4_EN_8822C BIT(4)\n#define BIT_MBID_BCNQ3_EN_8822C BIT(3)\n#define BIT_MBID_BCNQ2_EN_8822C BIT(2)\n#define BIT_MBID_BCNQ1_EN_8822C BIT(1)\n#define BIT_MBID_BCNQ0_EN_8822C BIT(0)\n\n/* 2 REG_P2PPS_CTRL_8822C */\n#define BIT_P2P_CTW_ALLSTASLEEP_8822C BIT(7)\n#define BIT_P2P_OFF_DISTX_EN_8822C BIT(6)\n#define BIT_PWR_MGT_EN_8822C BIT(5)\n#define BIT_P2P_NOA1_EN_8822C BIT(2)\n#define BIT_P2P_NOA0_EN_8822C BIT(1)\n\n/* 2 REG_PKT_LIFETIME_CTRL_8822C */\n#define BIT_EN_P2P_CTWND1_8822C BIT(23)\n#define BIT_EN_BKF_CLR_TXREQ_8822C BIT(22)\n#define BIT_EN_TSFBIT32_RST_P2P_8822C BIT(21)\n#define BIT_EN_BCN_TX_BTCCA_8822C BIT(20)\n#define BIT_DIS_PKT_TX_ATIM_8822C BIT(19)\n#define BIT_DIS_BCN_DIS_CTN_8822C BIT(18)\n#define BIT_EN_NAVEND_RST_TXOP_8822C BIT(17)\n#define BIT_EN_FILTER_CCA_8822C BIT(16)\n\n#define BIT_SHIFT_CCA_FILTER_THRS_8822C 8\n#define BIT_MASK_CCA_FILTER_THRS_8822C 0xff\n#define BIT_CCA_FILTER_THRS_8822C(x)                                           \\\n\t(((x) & BIT_MASK_CCA_FILTER_THRS_8822C)                                \\\n\t << BIT_SHIFT_CCA_FILTER_THRS_8822C)\n#define BITS_CCA_FILTER_THRS_8822C                                             \\\n\t(BIT_MASK_CCA_FILTER_THRS_8822C << BIT_SHIFT_CCA_FILTER_THRS_8822C)\n#define BIT_CLEAR_CCA_FILTER_THRS_8822C(x) ((x) & (~BITS_CCA_FILTER_THRS_8822C))\n#define BIT_GET_CCA_FILTER_THRS_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_CCA_FILTER_THRS_8822C) &                            \\\n\t BIT_MASK_CCA_FILTER_THRS_8822C)\n#define BIT_SET_CCA_FILTER_THRS_8822C(x, v)                                    \\\n\t(BIT_CLEAR_CCA_FILTER_THRS_8822C(x) | BIT_CCA_FILTER_THRS_8822C(v))\n\n#define BIT_SHIFT_EDCCA_THRS_8822C 0\n#define BIT_MASK_EDCCA_THRS_8822C 0xff\n#define BIT_EDCCA_THRS_8822C(x)                                                \\\n\t(((x) & BIT_MASK_EDCCA_THRS_8822C) << BIT_SHIFT_EDCCA_THRS_8822C)\n#define BITS_EDCCA_THRS_8822C                                                  \\\n\t(BIT_MASK_EDCCA_THRS_8822C << BIT_SHIFT_EDCCA_THRS_8822C)\n#define BIT_CLEAR_EDCCA_THRS_8822C(x) ((x) & (~BITS_EDCCA_THRS_8822C))\n#define BIT_GET_EDCCA_THRS_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_EDCCA_THRS_8822C) & BIT_MASK_EDCCA_THRS_8822C)\n#define BIT_SET_EDCCA_THRS_8822C(x, v)                                         \\\n\t(BIT_CLEAR_EDCCA_THRS_8822C(x) | BIT_EDCCA_THRS_8822C(v))\n\n/* 2 REG_P2PPS_SPEC_STATE_8822C */\n#define BIT_SPEC_POWER_STATE_8822C BIT(7)\n#define BIT_SPEC_CTWINDOW_ON_8822C BIT(6)\n#define BIT_SPEC_BEACON_AREA_ON_8822C BIT(5)\n#define BIT_SPEC_CTWIN_EARLY_DISTX_8822C BIT(4)\n#define BIT_SPEC_NOA1_OFF_PERIOD_8822C BIT(3)\n#define BIT_SPEC_FORCE_DOZE1_8822C BIT(2)\n#define BIT_SPEC_NOA0_OFF_PERIOD_8822C BIT(1)\n#define BIT_SPEC_FORCE_DOZE0_8822C BIT(0)\n\n/* 2 REG_TXOP_LIMIT_CTRL_8822C */\n\n#define BIT_SHIFT_TXOP_TBTT_CNT_8822C 24\n#define BIT_MASK_TXOP_TBTT_CNT_8822C 0xff\n#define BIT_TXOP_TBTT_CNT_8822C(x)                                             \\\n\t(((x) & BIT_MASK_TXOP_TBTT_CNT_8822C) << BIT_SHIFT_TXOP_TBTT_CNT_8822C)\n#define BITS_TXOP_TBTT_CNT_8822C                                               \\\n\t(BIT_MASK_TXOP_TBTT_CNT_8822C << BIT_SHIFT_TXOP_TBTT_CNT_8822C)\n#define BIT_CLEAR_TXOP_TBTT_CNT_8822C(x) ((x) & (~BITS_TXOP_TBTT_CNT_8822C))\n#define BIT_GET_TXOP_TBTT_CNT_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXOP_TBTT_CNT_8822C) & BIT_MASK_TXOP_TBTT_CNT_8822C)\n#define BIT_SET_TXOP_TBTT_CNT_8822C(x, v)                                      \\\n\t(BIT_CLEAR_TXOP_TBTT_CNT_8822C(x) | BIT_TXOP_TBTT_CNT_8822C(v))\n\n#define BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C 20\n#define BIT_MASK_TXOP_TBTT_CNT_SEL_8822C 0xf\n#define BIT_TXOP_TBTT_CNT_SEL_8822C(x)                                         \\\n\t(((x) & BIT_MASK_TXOP_TBTT_CNT_SEL_8822C)                              \\\n\t << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C)\n#define BITS_TXOP_TBTT_CNT_SEL_8822C                                           \\\n\t(BIT_MASK_TXOP_TBTT_CNT_SEL_8822C << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C)\n#define BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822C(x)                                   \\\n\t((x) & (~BITS_TXOP_TBTT_CNT_SEL_8822C))\n#define BIT_GET_TXOP_TBTT_CNT_SEL_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C) &                          \\\n\t BIT_MASK_TXOP_TBTT_CNT_SEL_8822C)\n#define BIT_SET_TXOP_TBTT_CNT_SEL_8822C(x, v)                                  \\\n\t(BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822C(x) | BIT_TXOP_TBTT_CNT_SEL_8822C(v))\n\n#define BIT_SHIFT_TXOP_LMT_EN_8822C 16\n#define BIT_MASK_TXOP_LMT_EN_8822C 0xf\n#define BIT_TXOP_LMT_EN_8822C(x)                                               \\\n\t(((x) & BIT_MASK_TXOP_LMT_EN_8822C) << BIT_SHIFT_TXOP_LMT_EN_8822C)\n#define BITS_TXOP_LMT_EN_8822C                                                 \\\n\t(BIT_MASK_TXOP_LMT_EN_8822C << BIT_SHIFT_TXOP_LMT_EN_8822C)\n#define BIT_CLEAR_TXOP_LMT_EN_8822C(x) ((x) & (~BITS_TXOP_LMT_EN_8822C))\n#define BIT_GET_TXOP_LMT_EN_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_TXOP_LMT_EN_8822C) & BIT_MASK_TXOP_LMT_EN_8822C)\n#define BIT_SET_TXOP_LMT_EN_8822C(x, v)                                        \\\n\t(BIT_CLEAR_TXOP_LMT_EN_8822C(x) | BIT_TXOP_LMT_EN_8822C(v))\n\n#define BIT_SHIFT_TXOP_LMT_TX_TIME_8822C 8\n#define BIT_MASK_TXOP_LMT_TX_TIME_8822C 0xff\n#define BIT_TXOP_LMT_TX_TIME_8822C(x)                                          \\\n\t(((x) & BIT_MASK_TXOP_LMT_TX_TIME_8822C)                               \\\n\t << BIT_SHIFT_TXOP_LMT_TX_TIME_8822C)\n#define BITS_TXOP_LMT_TX_TIME_8822C                                            \\\n\t(BIT_MASK_TXOP_LMT_TX_TIME_8822C << BIT_SHIFT_TXOP_LMT_TX_TIME_8822C)\n#define BIT_CLEAR_TXOP_LMT_TX_TIME_8822C(x)                                    \\\n\t((x) & (~BITS_TXOP_LMT_TX_TIME_8822C))\n#define BIT_GET_TXOP_LMT_TX_TIME_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME_8822C) &                           \\\n\t BIT_MASK_TXOP_LMT_TX_TIME_8822C)\n#define BIT_SET_TXOP_LMT_TX_TIME_8822C(x, v)                                   \\\n\t(BIT_CLEAR_TXOP_LMT_TX_TIME_8822C(x) | BIT_TXOP_LMT_TX_TIME_8822C(v))\n\n#define BIT_TXOP_CNT_TRIGGER_RESET_8822C BIT(7)\n\n#define BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C 0\n#define BIT_MASK_TXOP_LMT_PKT_NUM_8822C 0x3f\n#define BIT_TXOP_LMT_PKT_NUM_8822C(x)                                          \\\n\t(((x) & BIT_MASK_TXOP_LMT_PKT_NUM_8822C)                               \\\n\t << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C)\n#define BITS_TXOP_LMT_PKT_NUM_8822C                                            \\\n\t(BIT_MASK_TXOP_LMT_PKT_NUM_8822C << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C)\n#define BIT_CLEAR_TXOP_LMT_PKT_NUM_8822C(x)                                    \\\n\t((x) & (~BITS_TXOP_LMT_PKT_NUM_8822C))\n#define BIT_GET_TXOP_LMT_PKT_NUM_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C) &                           \\\n\t BIT_MASK_TXOP_LMT_PKT_NUM_8822C)\n#define BIT_SET_TXOP_LMT_PKT_NUM_8822C(x, v)                                   \\\n\t(BIT_CLEAR_TXOP_LMT_PKT_NUM_8822C(x) | BIT_TXOP_LMT_PKT_NUM_8822C(v))\n\n/* 2 REG_BAR_TX_CTRL_8822C */\n\n/* 2 REG_P2PON_DIS_TXTIME_8822C */\n\n#define BIT_SHIFT_P2PON_DIS_TXTIME_8822C 0\n#define BIT_MASK_P2PON_DIS_TXTIME_8822C 0xff\n#define BIT_P2PON_DIS_TXTIME_8822C(x)                                          \\\n\t(((x) & BIT_MASK_P2PON_DIS_TXTIME_8822C)                               \\\n\t << BIT_SHIFT_P2PON_DIS_TXTIME_8822C)\n#define BITS_P2PON_DIS_TXTIME_8822C                                            \\\n\t(BIT_MASK_P2PON_DIS_TXTIME_8822C << BIT_SHIFT_P2PON_DIS_TXTIME_8822C)\n#define BIT_CLEAR_P2PON_DIS_TXTIME_8822C(x)                                    \\\n\t((x) & (~BITS_P2PON_DIS_TXTIME_8822C))\n#define BIT_GET_P2PON_DIS_TXTIME_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8822C) &                           \\\n\t BIT_MASK_P2PON_DIS_TXTIME_8822C)\n#define BIT_SET_P2PON_DIS_TXTIME_8822C(x, v)                                   \\\n\t(BIT_CLEAR_P2PON_DIS_TXTIME_8822C(x) | BIT_P2PON_DIS_TXTIME_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_CCA_TXEN_CNT_8822C */\n#define BIT_ENABLE_STOP_UPDATE_NAV_8822C BIT(21)\n#define BIT_ENABLE_GEN_RANDON_SLOT_TX_8822C BIT(20)\n#define BIT_ENABLE_RANDOM_SHIFT_TX_8822C BIT(19)\n#define BIT_ENABLE_EDCA_REF_FUNCTION_8822C BIT(18)\n#define BIT_CCA_TXEN_CNT_SWITCH_8822C BIT(17)\n#define BIT_CCA_TXEN_CNT_EN_8822C BIT(16)\n\n#define BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C 8\n#define BIT_MASK_CCA_TXEN_BIG_CNT_8822C 0xff\n#define BIT_CCA_TXEN_BIG_CNT_8822C(x)                                          \\\n\t(((x) & BIT_MASK_CCA_TXEN_BIG_CNT_8822C)                               \\\n\t << BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C)\n#define BITS_CCA_TXEN_BIG_CNT_8822C                                            \\\n\t(BIT_MASK_CCA_TXEN_BIG_CNT_8822C << BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C)\n#define BIT_CLEAR_CCA_TXEN_BIG_CNT_8822C(x)                                    \\\n\t((x) & (~BITS_CCA_TXEN_BIG_CNT_8822C))\n#define BIT_GET_CCA_TXEN_BIG_CNT_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C) &                           \\\n\t BIT_MASK_CCA_TXEN_BIG_CNT_8822C)\n#define BIT_SET_CCA_TXEN_BIG_CNT_8822C(x, v)                                   \\\n\t(BIT_CLEAR_CCA_TXEN_BIG_CNT_8822C(x) | BIT_CCA_TXEN_BIG_CNT_8822C(v))\n\n#define BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C 0\n#define BIT_MASK_CCA_TXEN_SMALL_CNT_8822C 0xff\n#define BIT_CCA_TXEN_SMALL_CNT_8822C(x)                                        \\\n\t(((x) & BIT_MASK_CCA_TXEN_SMALL_CNT_8822C)                             \\\n\t << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C)\n#define BITS_CCA_TXEN_SMALL_CNT_8822C                                          \\\n\t(BIT_MASK_CCA_TXEN_SMALL_CNT_8822C                                     \\\n\t << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C)\n#define BIT_CLEAR_CCA_TXEN_SMALL_CNT_8822C(x)                                  \\\n\t((x) & (~BITS_CCA_TXEN_SMALL_CNT_8822C))\n#define BIT_GET_CCA_TXEN_SMALL_CNT_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C) &                         \\\n\t BIT_MASK_CCA_TXEN_SMALL_CNT_8822C)\n#define BIT_SET_CCA_TXEN_SMALL_CNT_8822C(x, v)                                 \\\n\t(BIT_CLEAR_CCA_TXEN_SMALL_CNT_8822C(x) |                               \\\n\t BIT_CCA_TXEN_SMALL_CNT_8822C(v))\n\n/* 2 REG_MAX_INTER_COLLISION_8822C */\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C 24\n#define BIT_MASK_MAX_INTER_COLLISION_BK_8822C 0xff\n#define BIT_MAX_INTER_COLLISION_BK_8822C(x)                                    \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_BK_8822C)                         \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C)\n#define BITS_MAX_INTER_COLLISION_BK_8822C                                      \\\n\t(BIT_MASK_MAX_INTER_COLLISION_BK_8822C                                 \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C)\n#define BIT_CLEAR_MAX_INTER_COLLISION_BK_8822C(x)                              \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_BK_8822C))\n#define BIT_GET_MAX_INTER_COLLISION_BK_8822C(x)                                \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C) &                     \\\n\t BIT_MASK_MAX_INTER_COLLISION_BK_8822C)\n#define BIT_SET_MAX_INTER_COLLISION_BK_8822C(x, v)                             \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_BK_8822C(x) |                           \\\n\t BIT_MAX_INTER_COLLISION_BK_8822C(v))\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C 16\n#define BIT_MASK_MAX_INTER_COLLISION_BE_8822C 0xff\n#define BIT_MAX_INTER_COLLISION_BE_8822C(x)                                    \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_BE_8822C)                         \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C)\n#define BITS_MAX_INTER_COLLISION_BE_8822C                                      \\\n\t(BIT_MASK_MAX_INTER_COLLISION_BE_8822C                                 \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C)\n#define BIT_CLEAR_MAX_INTER_COLLISION_BE_8822C(x)                              \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_BE_8822C))\n#define BIT_GET_MAX_INTER_COLLISION_BE_8822C(x)                                \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C) &                     \\\n\t BIT_MASK_MAX_INTER_COLLISION_BE_8822C)\n#define BIT_SET_MAX_INTER_COLLISION_BE_8822C(x, v)                             \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_BE_8822C(x) |                           \\\n\t BIT_MAX_INTER_COLLISION_BE_8822C(v))\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C 8\n#define BIT_MASK_MAX_INTER_COLLISION_VI_8822C 0xff\n#define BIT_MAX_INTER_COLLISION_VI_8822C(x)                                    \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_VI_8822C)                         \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C)\n#define BITS_MAX_INTER_COLLISION_VI_8822C                                      \\\n\t(BIT_MASK_MAX_INTER_COLLISION_VI_8822C                                 \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C)\n#define BIT_CLEAR_MAX_INTER_COLLISION_VI_8822C(x)                              \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_VI_8822C))\n#define BIT_GET_MAX_INTER_COLLISION_VI_8822C(x)                                \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C) &                     \\\n\t BIT_MASK_MAX_INTER_COLLISION_VI_8822C)\n#define BIT_SET_MAX_INTER_COLLISION_VI_8822C(x, v)                             \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_VI_8822C(x) |                           \\\n\t BIT_MAX_INTER_COLLISION_VI_8822C(v))\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C 0\n#define BIT_MASK_MAX_INTER_COLLISION_VO_8822C 0xff\n#define BIT_MAX_INTER_COLLISION_VO_8822C(x)                                    \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_VO_8822C)                         \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C)\n#define BITS_MAX_INTER_COLLISION_VO_8822C                                      \\\n\t(BIT_MASK_MAX_INTER_COLLISION_VO_8822C                                 \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C)\n#define BIT_CLEAR_MAX_INTER_COLLISION_VO_8822C(x)                              \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_VO_8822C))\n#define BIT_GET_MAX_INTER_COLLISION_VO_8822C(x)                                \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C) &                     \\\n\t BIT_MASK_MAX_INTER_COLLISION_VO_8822C)\n#define BIT_SET_MAX_INTER_COLLISION_VO_8822C(x, v)                             \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_VO_8822C(x) |                           \\\n\t BIT_MAX_INTER_COLLISION_VO_8822C(v))\n\n/* 2 REG_MAX_INTER_COLLISION_CNT_8822C */\n#define BIT_MAX_INTER_COLLISION_EN_8822C BIT(16)\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C 12\n#define BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C 0xf\n#define BIT_MAX_INTER_COLLISION_CNT_BK_8822C(x)                                \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C)                     \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C)\n#define BITS_MAX_INTER_COLLISION_CNT_BK_8822C                                  \\\n\t(BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C                             \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C)\n#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8822C(x)                          \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_CNT_BK_8822C))\n#define BIT_GET_MAX_INTER_COLLISION_CNT_BK_8822C(x)                            \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C) &                 \\\n\t BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C)\n#define BIT_SET_MAX_INTER_COLLISION_CNT_BK_8822C(x, v)                         \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8822C(x) |                       \\\n\t BIT_MAX_INTER_COLLISION_CNT_BK_8822C(v))\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C 8\n#define BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C 0xf\n#define BIT_MAX_INTER_COLLISION_CNT_BE_8822C(x)                                \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C)                     \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C)\n#define BITS_MAX_INTER_COLLISION_CNT_BE_8822C                                  \\\n\t(BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C                             \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C)\n#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8822C(x)                          \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_CNT_BE_8822C))\n#define BIT_GET_MAX_INTER_COLLISION_CNT_BE_8822C(x)                            \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C) &                 \\\n\t BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C)\n#define BIT_SET_MAX_INTER_COLLISION_CNT_BE_8822C(x, v)                         \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8822C(x) |                       \\\n\t BIT_MAX_INTER_COLLISION_CNT_BE_8822C(v))\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C 4\n#define BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C 0xf\n#define BIT_MAX_INTER_COLLISION_CNT_VI_8822C(x)                                \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C)                     \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C)\n#define BITS_MAX_INTER_COLLISION_CNT_VI_8822C                                  \\\n\t(BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C                             \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C)\n#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8822C(x)                          \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_CNT_VI_8822C))\n#define BIT_GET_MAX_INTER_COLLISION_CNT_VI_8822C(x)                            \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C) &                 \\\n\t BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C)\n#define BIT_SET_MAX_INTER_COLLISION_CNT_VI_8822C(x, v)                         \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8822C(x) |                       \\\n\t BIT_MAX_INTER_COLLISION_CNT_VI_8822C(v))\n\n#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C 0\n#define BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C 0xf\n#define BIT_MAX_INTER_COLLISION_CNT_VO_8822C(x)                                \\\n\t(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C)                     \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C)\n#define BITS_MAX_INTER_COLLISION_CNT_VO_8822C                                  \\\n\t(BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C                             \\\n\t << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C)\n#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8822C(x)                          \\\n\t((x) & (~BITS_MAX_INTER_COLLISION_CNT_VO_8822C))\n#define BIT_GET_MAX_INTER_COLLISION_CNT_VO_8822C(x)                            \\\n\t(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C) &                 \\\n\t BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C)\n#define BIT_SET_MAX_INTER_COLLISION_CNT_VO_8822C(x, v)                         \\\n\t(BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8822C(x) |                       \\\n\t BIT_MAX_INTER_COLLISION_CNT_VO_8822C(v))\n\n/* 2 REG_TBTT_PROHIBIT_8822C */\n\n#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C 8\n#define BIT_MASK_TBTT_HOLD_TIME_AP_8822C 0xfff\n#define BIT_TBTT_HOLD_TIME_AP_8822C(x)                                         \\\n\t(((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8822C)                              \\\n\t << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C)\n#define BITS_TBTT_HOLD_TIME_AP_8822C                                           \\\n\t(BIT_MASK_TBTT_HOLD_TIME_AP_8822C << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C)\n#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8822C(x)                                   \\\n\t((x) & (~BITS_TBTT_HOLD_TIME_AP_8822C))\n#define BIT_GET_TBTT_HOLD_TIME_AP_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C) &                          \\\n\t BIT_MASK_TBTT_HOLD_TIME_AP_8822C)\n#define BIT_SET_TBTT_HOLD_TIME_AP_8822C(x, v)                                  \\\n\t(BIT_CLEAR_TBTT_HOLD_TIME_AP_8822C(x) | BIT_TBTT_HOLD_TIME_AP_8822C(v))\n\n#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C 0\n#define BIT_MASK_TBTT_PROHIBIT_SETUP_8822C 0xf\n#define BIT_TBTT_PROHIBIT_SETUP_8822C(x)                                       \\\n\t(((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822C)                            \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C)\n#define BITS_TBTT_PROHIBIT_SETUP_8822C                                         \\\n\t(BIT_MASK_TBTT_PROHIBIT_SETUP_8822C                                    \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C)\n#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822C(x)                                 \\\n\t((x) & (~BITS_TBTT_PROHIBIT_SETUP_8822C))\n#define BIT_GET_TBTT_PROHIBIT_SETUP_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C) &                        \\\n\t BIT_MASK_TBTT_PROHIBIT_SETUP_8822C)\n#define BIT_SET_TBTT_PROHIBIT_SETUP_8822C(x, v)                                \\\n\t(BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822C(x) |                              \\\n\t BIT_TBTT_PROHIBIT_SETUP_8822C(v))\n\n/* 2 REG_P2PPS_STATE_8822C */\n#define BIT_POWER_STATE_8822C BIT(7)\n#define BIT_CTWINDOW_ON_8822C BIT(6)\n#define BIT_BEACON_AREA_ON_8822C BIT(5)\n#define BIT_CTWIN_EARLY_DISTX_8822C BIT(4)\n#define BIT_NOA1_OFF_PERIOD_8822C BIT(3)\n#define BIT_FORCE_DOZE1_8822C BIT(2)\n#define BIT_NOA0_OFF_PERIOD_8822C BIT(1)\n#define BIT_FORCE_DOZE0_8822C BIT(0)\n\n/* 2 REG_RD_NAV_NXT_8822C */\n\n#define BIT_SHIFT_RD_NAV_PROT_NXT_8822C 0\n#define BIT_MASK_RD_NAV_PROT_NXT_8822C 0xffff\n#define BIT_RD_NAV_PROT_NXT_8822C(x)                                           \\\n\t(((x) & BIT_MASK_RD_NAV_PROT_NXT_8822C)                                \\\n\t << BIT_SHIFT_RD_NAV_PROT_NXT_8822C)\n#define BITS_RD_NAV_PROT_NXT_8822C                                             \\\n\t(BIT_MASK_RD_NAV_PROT_NXT_8822C << BIT_SHIFT_RD_NAV_PROT_NXT_8822C)\n#define BIT_CLEAR_RD_NAV_PROT_NXT_8822C(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8822C))\n#define BIT_GET_RD_NAV_PROT_NXT_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8822C) &                            \\\n\t BIT_MASK_RD_NAV_PROT_NXT_8822C)\n#define BIT_SET_RD_NAV_PROT_NXT_8822C(x, v)                                    \\\n\t(BIT_CLEAR_RD_NAV_PROT_NXT_8822C(x) | BIT_RD_NAV_PROT_NXT_8822C(v))\n\n/* 2 REG_NAV_PROT_LEN_8822C */\n\n#define BIT_SHIFT_NAV_PROT_LEN_8822C 0\n#define BIT_MASK_NAV_PROT_LEN_8822C 0xffff\n#define BIT_NAV_PROT_LEN_8822C(x)                                              \\\n\t(((x) & BIT_MASK_NAV_PROT_LEN_8822C) << BIT_SHIFT_NAV_PROT_LEN_8822C)\n#define BITS_NAV_PROT_LEN_8822C                                                \\\n\t(BIT_MASK_NAV_PROT_LEN_8822C << BIT_SHIFT_NAV_PROT_LEN_8822C)\n#define BIT_CLEAR_NAV_PROT_LEN_8822C(x) ((x) & (~BITS_NAV_PROT_LEN_8822C))\n#define BIT_GET_NAV_PROT_LEN_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_NAV_PROT_LEN_8822C) & BIT_MASK_NAV_PROT_LEN_8822C)\n#define BIT_SET_NAV_PROT_LEN_8822C(x, v)                                       \\\n\t(BIT_CLEAR_NAV_PROT_LEN_8822C(x) | BIT_NAV_PROT_LEN_8822C(v))\n\n/* 2 REG_FTM_PTT_8822C */\n\n#define BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C 22\n#define BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C 0x7\n#define BIT_FTM_PTT_TSF_R2T_SEL_8822C(x)                                       \\\n\t(((x) & BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C)                            \\\n\t << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C)\n#define BITS_FTM_PTT_TSF_R2T_SEL_8822C                                         \\\n\t(BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C                                    \\\n\t << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C)\n#define BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8822C(x)                                 \\\n\t((x) & (~BITS_FTM_PTT_TSF_R2T_SEL_8822C))\n#define BIT_GET_FTM_PTT_TSF_R2T_SEL_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C) &                        \\\n\t BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C)\n#define BIT_SET_FTM_PTT_TSF_R2T_SEL_8822C(x, v)                                \\\n\t(BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8822C(x) |                              \\\n\t BIT_FTM_PTT_TSF_R2T_SEL_8822C(v))\n\n#define BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C 19\n#define BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C 0x7\n#define BIT_FTM_PTT_TSF_T2R_SEL_8822C(x)                                       \\\n\t(((x) & BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C)                            \\\n\t << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C)\n#define BITS_FTM_PTT_TSF_T2R_SEL_8822C                                         \\\n\t(BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C                                    \\\n\t << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C)\n#define BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8822C(x)                                 \\\n\t((x) & (~BITS_FTM_PTT_TSF_T2R_SEL_8822C))\n#define BIT_GET_FTM_PTT_TSF_T2R_SEL_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C) &                        \\\n\t BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C)\n#define BIT_SET_FTM_PTT_TSF_T2R_SEL_8822C(x, v)                                \\\n\t(BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8822C(x) |                              \\\n\t BIT_FTM_PTT_TSF_T2R_SEL_8822C(v))\n\n#define BIT_SHIFT_FTM_PTT_TSF_SEL_8822C 16\n#define BIT_MASK_FTM_PTT_TSF_SEL_8822C 0x7\n#define BIT_FTM_PTT_TSF_SEL_8822C(x)                                           \\\n\t(((x) & BIT_MASK_FTM_PTT_TSF_SEL_8822C)                                \\\n\t << BIT_SHIFT_FTM_PTT_TSF_SEL_8822C)\n#define BITS_FTM_PTT_TSF_SEL_8822C                                             \\\n\t(BIT_MASK_FTM_PTT_TSF_SEL_8822C << BIT_SHIFT_FTM_PTT_TSF_SEL_8822C)\n#define BIT_CLEAR_FTM_PTT_TSF_SEL_8822C(x) ((x) & (~BITS_FTM_PTT_TSF_SEL_8822C))\n#define BIT_GET_FTM_PTT_TSF_SEL_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_FTM_PTT_TSF_SEL_8822C) &                            \\\n\t BIT_MASK_FTM_PTT_TSF_SEL_8822C)\n#define BIT_SET_FTM_PTT_TSF_SEL_8822C(x, v)                                    \\\n\t(BIT_CLEAR_FTM_PTT_TSF_SEL_8822C(x) | BIT_FTM_PTT_TSF_SEL_8822C(v))\n\n#define BIT_SHIFT_FTM_PTT_VALUE_8822C 0\n#define BIT_MASK_FTM_PTT_VALUE_8822C 0xffff\n#define BIT_FTM_PTT_VALUE_8822C(x)                                             \\\n\t(((x) & BIT_MASK_FTM_PTT_VALUE_8822C) << BIT_SHIFT_FTM_PTT_VALUE_8822C)\n#define BITS_FTM_PTT_VALUE_8822C                                               \\\n\t(BIT_MASK_FTM_PTT_VALUE_8822C << BIT_SHIFT_FTM_PTT_VALUE_8822C)\n#define BIT_CLEAR_FTM_PTT_VALUE_8822C(x) ((x) & (~BITS_FTM_PTT_VALUE_8822C))\n#define BIT_GET_FTM_PTT_VALUE_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_FTM_PTT_VALUE_8822C) & BIT_MASK_FTM_PTT_VALUE_8822C)\n#define BIT_SET_FTM_PTT_VALUE_8822C(x, v)                                      \\\n\t(BIT_CLEAR_FTM_PTT_VALUE_8822C(x) | BIT_FTM_PTT_VALUE_8822C(v))\n\n/* 2 REG_FTM_TSF_8822C */\n\n#define BIT_SHIFT_FTM_T2_TSF_8822C 16\n#define BIT_MASK_FTM_T2_TSF_8822C 0xffff\n#define BIT_FTM_T2_TSF_8822C(x)                                                \\\n\t(((x) & BIT_MASK_FTM_T2_TSF_8822C) << BIT_SHIFT_FTM_T2_TSF_8822C)\n#define BITS_FTM_T2_TSF_8822C                                                  \\\n\t(BIT_MASK_FTM_T2_TSF_8822C << BIT_SHIFT_FTM_T2_TSF_8822C)\n#define BIT_CLEAR_FTM_T2_TSF_8822C(x) ((x) & (~BITS_FTM_T2_TSF_8822C))\n#define BIT_GET_FTM_T2_TSF_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_FTM_T2_TSF_8822C) & BIT_MASK_FTM_T2_TSF_8822C)\n#define BIT_SET_FTM_T2_TSF_8822C(x, v)                                         \\\n\t(BIT_CLEAR_FTM_T2_TSF_8822C(x) | BIT_FTM_T2_TSF_8822C(v))\n\n#define BIT_SHIFT_FTM_T1_TSF_8822C 0\n#define BIT_MASK_FTM_T1_TSF_8822C 0xffff\n#define BIT_FTM_T1_TSF_8822C(x)                                                \\\n\t(((x) & BIT_MASK_FTM_T1_TSF_8822C) << BIT_SHIFT_FTM_T1_TSF_8822C)\n#define BITS_FTM_T1_TSF_8822C                                                  \\\n\t(BIT_MASK_FTM_T1_TSF_8822C << BIT_SHIFT_FTM_T1_TSF_8822C)\n#define BIT_CLEAR_FTM_T1_TSF_8822C(x) ((x) & (~BITS_FTM_T1_TSF_8822C))\n#define BIT_GET_FTM_T1_TSF_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_FTM_T1_TSF_8822C) & BIT_MASK_FTM_T1_TSF_8822C)\n#define BIT_SET_FTM_T1_TSF_8822C(x, v)                                         \\\n\t(BIT_CLEAR_FTM_T1_TSF_8822C(x) | BIT_FTM_T1_TSF_8822C(v))\n\n/* 2 REG_BCN_CTRL_8822C */\n#define BIT_DIS_RX_BSSID_FIT_8822C BIT(6)\n#define BIT_P0_EN_TXBCN_RPT_8822C BIT(5)\n#define BIT_DIS_TSF_UDT_8822C BIT(4)\n#define BIT_EN_BCN_FUNCTION_8822C BIT(3)\n#define BIT_P0_EN_RXBCN_RPT_8822C BIT(2)\n#define BIT_EN_P2P_CTWINDOW_8822C BIT(1)\n#define BIT_EN_P2P_BCNQ_AREA_8822C BIT(0)\n\n/* 2 REG_BCN_CTRL_CLINT0_8822C */\n#define BIT_CLI0_DIS_RX_BSSID_FIT_8822C BIT(6)\n#define BIT_CLI0_DIS_TSF_UDT_8822C BIT(4)\n#define BIT_CLI0_EN_BCN_FUNCTION_8822C BIT(3)\n#define BIT_CLI0_EN_RXBCN_RPT_8822C BIT(2)\n#define BIT_CLI0_ENP2P_CTWINDOW_8822C BIT(1)\n#define BIT_CLI0_ENP2P_BCNQ_AREA_8822C BIT(0)\n\n/* 2 REG_MBID_NUM_8822C */\n#define BIT_EN_PRE_DL_BEACON_8822C BIT(3)\n\n#define BIT_SHIFT_MBID_BCN_NUM_8822C 0\n#define BIT_MASK_MBID_BCN_NUM_8822C 0x7\n#define BIT_MBID_BCN_NUM_8822C(x)                                              \\\n\t(((x) & BIT_MASK_MBID_BCN_NUM_8822C) << BIT_SHIFT_MBID_BCN_NUM_8822C)\n#define BITS_MBID_BCN_NUM_8822C                                                \\\n\t(BIT_MASK_MBID_BCN_NUM_8822C << BIT_SHIFT_MBID_BCN_NUM_8822C)\n#define BIT_CLEAR_MBID_BCN_NUM_8822C(x) ((x) & (~BITS_MBID_BCN_NUM_8822C))\n#define BIT_GET_MBID_BCN_NUM_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_MBID_BCN_NUM_8822C) & BIT_MASK_MBID_BCN_NUM_8822C)\n#define BIT_SET_MBID_BCN_NUM_8822C(x, v)                                       \\\n\t(BIT_CLEAR_MBID_BCN_NUM_8822C(x) | BIT_MBID_BCN_NUM_8822C(v))\n\n/* 2 REG_DUAL_TSF_RST_8822C */\n#define BIT_FREECNT_RST_8822C BIT(5)\n#define BIT_TSFTR_CLI3_RST_8822C BIT(4)\n#define BIT_TSFTR_CLI2_RST_8822C BIT(3)\n#define BIT_TSFTR_CLI1_RST_8822C BIT(2)\n#define BIT_TSFTR_CLI0_RST_8822C BIT(1)\n#define BIT_TSFTR_RST_8822C BIT(0)\n\n/* 2 REG_MBSSID_BCN_SPACE_8822C */\n\n#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C 28\n#define BIT_MASK_BCN_TIMER_SEL_FWRD_8822C 0x7\n#define BIT_BCN_TIMER_SEL_FWRD_8822C(x)                                        \\\n\t(((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822C)                             \\\n\t << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C)\n#define BITS_BCN_TIMER_SEL_FWRD_8822C                                          \\\n\t(BIT_MASK_BCN_TIMER_SEL_FWRD_8822C                                     \\\n\t << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C)\n#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822C(x)                                  \\\n\t((x) & (~BITS_BCN_TIMER_SEL_FWRD_8822C))\n#define BIT_GET_BCN_TIMER_SEL_FWRD_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C) &                         \\\n\t BIT_MASK_BCN_TIMER_SEL_FWRD_8822C)\n#define BIT_SET_BCN_TIMER_SEL_FWRD_8822C(x, v)                                 \\\n\t(BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822C(x) |                               \\\n\t BIT_BCN_TIMER_SEL_FWRD_8822C(v))\n\n#define BIT_SHIFT_BCN_SPACE_CLINT0_8822C 16\n#define BIT_MASK_BCN_SPACE_CLINT0_8822C 0xfff\n#define BIT_BCN_SPACE_CLINT0_8822C(x)                                          \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT0_8822C)                               \\\n\t << BIT_SHIFT_BCN_SPACE_CLINT0_8822C)\n#define BITS_BCN_SPACE_CLINT0_8822C                                            \\\n\t(BIT_MASK_BCN_SPACE_CLINT0_8822C << BIT_SHIFT_BCN_SPACE_CLINT0_8822C)\n#define BIT_CLEAR_BCN_SPACE_CLINT0_8822C(x)                                    \\\n\t((x) & (~BITS_BCN_SPACE_CLINT0_8822C))\n#define BIT_GET_BCN_SPACE_CLINT0_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8822C) &                           \\\n\t BIT_MASK_BCN_SPACE_CLINT0_8822C)\n#define BIT_SET_BCN_SPACE_CLINT0_8822C(x, v)                                   \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT0_8822C(x) | BIT_BCN_SPACE_CLINT0_8822C(v))\n\n#define BIT_SHIFT_BCN_SPACE0_8822C 0\n#define BIT_MASK_BCN_SPACE0_8822C 0xffff\n#define BIT_BCN_SPACE0_8822C(x)                                                \\\n\t(((x) & BIT_MASK_BCN_SPACE0_8822C) << BIT_SHIFT_BCN_SPACE0_8822C)\n#define BITS_BCN_SPACE0_8822C                                                  \\\n\t(BIT_MASK_BCN_SPACE0_8822C << BIT_SHIFT_BCN_SPACE0_8822C)\n#define BIT_CLEAR_BCN_SPACE0_8822C(x) ((x) & (~BITS_BCN_SPACE0_8822C))\n#define BIT_GET_BCN_SPACE0_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE0_8822C) & BIT_MASK_BCN_SPACE0_8822C)\n#define BIT_SET_BCN_SPACE0_8822C(x, v)                                         \\\n\t(BIT_CLEAR_BCN_SPACE0_8822C(x) | BIT_BCN_SPACE0_8822C(v))\n\n/* 2 REG_DRVERLYINT_8822C */\n\n#define BIT_SHIFT_DRVERLYITV_8822C 0\n#define BIT_MASK_DRVERLYITV_8822C 0xff\n#define BIT_DRVERLYITV_8822C(x)                                                \\\n\t(((x) & BIT_MASK_DRVERLYITV_8822C) << BIT_SHIFT_DRVERLYITV_8822C)\n#define BITS_DRVERLYITV_8822C                                                  \\\n\t(BIT_MASK_DRVERLYITV_8822C << BIT_SHIFT_DRVERLYITV_8822C)\n#define BIT_CLEAR_DRVERLYITV_8822C(x) ((x) & (~BITS_DRVERLYITV_8822C))\n#define BIT_GET_DRVERLYITV_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_DRVERLYITV_8822C) & BIT_MASK_DRVERLYITV_8822C)\n#define BIT_SET_DRVERLYITV_8822C(x, v)                                         \\\n\t(BIT_CLEAR_DRVERLYITV_8822C(x) | BIT_DRVERLYITV_8822C(v))\n\n/* 2 REG_BCNDMATIM_8822C */\n\n#define BIT_SHIFT_BCNDMATIM_8822C 0\n#define BIT_MASK_BCNDMATIM_8822C 0xff\n#define BIT_BCNDMATIM_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_BCNDMATIM_8822C) << BIT_SHIFT_BCNDMATIM_8822C)\n#define BITS_BCNDMATIM_8822C                                                   \\\n\t(BIT_MASK_BCNDMATIM_8822C << BIT_SHIFT_BCNDMATIM_8822C)\n#define BIT_CLEAR_BCNDMATIM_8822C(x) ((x) & (~BITS_BCNDMATIM_8822C))\n#define BIT_GET_BCNDMATIM_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_BCNDMATIM_8822C) & BIT_MASK_BCNDMATIM_8822C)\n#define BIT_SET_BCNDMATIM_8822C(x, v)                                          \\\n\t(BIT_CLEAR_BCNDMATIM_8822C(x) | BIT_BCNDMATIM_8822C(v))\n\n/* 2 REG_ATIMWND_8822C */\n\n#define BIT_SHIFT_ATIMWND0_8822C 0\n#define BIT_MASK_ATIMWND0_8822C 0xffff\n#define BIT_ATIMWND0_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND0_8822C) << BIT_SHIFT_ATIMWND0_8822C)\n#define BITS_ATIMWND0_8822C                                                    \\\n\t(BIT_MASK_ATIMWND0_8822C << BIT_SHIFT_ATIMWND0_8822C)\n#define BIT_CLEAR_ATIMWND0_8822C(x) ((x) & (~BITS_ATIMWND0_8822C))\n#define BIT_GET_ATIMWND0_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND0_8822C) & BIT_MASK_ATIMWND0_8822C)\n#define BIT_SET_ATIMWND0_8822C(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND0_8822C(x) | BIT_ATIMWND0_8822C(v))\n\n/* 2 REG_USTIME_TSF_8822C */\n\n#define BIT_SHIFT_USTIME_TSF_V1_8822C 0\n#define BIT_MASK_USTIME_TSF_V1_8822C 0xff\n#define BIT_USTIME_TSF_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_USTIME_TSF_V1_8822C) << BIT_SHIFT_USTIME_TSF_V1_8822C)\n#define BITS_USTIME_TSF_V1_8822C                                               \\\n\t(BIT_MASK_USTIME_TSF_V1_8822C << BIT_SHIFT_USTIME_TSF_V1_8822C)\n#define BIT_CLEAR_USTIME_TSF_V1_8822C(x) ((x) & (~BITS_USTIME_TSF_V1_8822C))\n#define BIT_GET_USTIME_TSF_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_USTIME_TSF_V1_8822C) & BIT_MASK_USTIME_TSF_V1_8822C)\n#define BIT_SET_USTIME_TSF_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_USTIME_TSF_V1_8822C(x) | BIT_USTIME_TSF_V1_8822C(v))\n\n/* 2 REG_BCN_MAX_ERR_8822C */\n\n#define BIT_SHIFT_BCN_MAX_ERR_8822C 0\n#define BIT_MASK_BCN_MAX_ERR_8822C 0xff\n#define BIT_BCN_MAX_ERR_8822C(x)                                               \\\n\t(((x) & BIT_MASK_BCN_MAX_ERR_8822C) << BIT_SHIFT_BCN_MAX_ERR_8822C)\n#define BITS_BCN_MAX_ERR_8822C                                                 \\\n\t(BIT_MASK_BCN_MAX_ERR_8822C << BIT_SHIFT_BCN_MAX_ERR_8822C)\n#define BIT_CLEAR_BCN_MAX_ERR_8822C(x) ((x) & (~BITS_BCN_MAX_ERR_8822C))\n#define BIT_GET_BCN_MAX_ERR_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_BCN_MAX_ERR_8822C) & BIT_MASK_BCN_MAX_ERR_8822C)\n#define BIT_SET_BCN_MAX_ERR_8822C(x, v)                                        \\\n\t(BIT_CLEAR_BCN_MAX_ERR_8822C(x) | BIT_BCN_MAX_ERR_8822C(v))\n\n/* 2 REG_RXTSF_OFFSET_CCK_8822C */\n\n#define BIT_SHIFT_CCK_RXTSF_OFFSET_8822C 0\n#define BIT_MASK_CCK_RXTSF_OFFSET_8822C 0xff\n#define BIT_CCK_RXTSF_OFFSET_8822C(x)                                          \\\n\t(((x) & BIT_MASK_CCK_RXTSF_OFFSET_8822C)                               \\\n\t << BIT_SHIFT_CCK_RXTSF_OFFSET_8822C)\n#define BITS_CCK_RXTSF_OFFSET_8822C                                            \\\n\t(BIT_MASK_CCK_RXTSF_OFFSET_8822C << BIT_SHIFT_CCK_RXTSF_OFFSET_8822C)\n#define BIT_CLEAR_CCK_RXTSF_OFFSET_8822C(x)                                    \\\n\t((x) & (~BITS_CCK_RXTSF_OFFSET_8822C))\n#define BIT_GET_CCK_RXTSF_OFFSET_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8822C) &                           \\\n\t BIT_MASK_CCK_RXTSF_OFFSET_8822C)\n#define BIT_SET_CCK_RXTSF_OFFSET_8822C(x, v)                                   \\\n\t(BIT_CLEAR_CCK_RXTSF_OFFSET_8822C(x) | BIT_CCK_RXTSF_OFFSET_8822C(v))\n\n/* 2 REG_RXTSF_OFFSET_OFDM_8822C */\n\n#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C 0\n#define BIT_MASK_OFDM_RXTSF_OFFSET_8822C 0xff\n#define BIT_OFDM_RXTSF_OFFSET_8822C(x)                                         \\\n\t(((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8822C)                              \\\n\t << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C)\n#define BITS_OFDM_RXTSF_OFFSET_8822C                                           \\\n\t(BIT_MASK_OFDM_RXTSF_OFFSET_8822C << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C)\n#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8822C(x)                                   \\\n\t((x) & (~BITS_OFDM_RXTSF_OFFSET_8822C))\n#define BIT_GET_OFDM_RXTSF_OFFSET_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C) &                          \\\n\t BIT_MASK_OFDM_RXTSF_OFFSET_8822C)\n#define BIT_SET_OFDM_RXTSF_OFFSET_8822C(x, v)                                  \\\n\t(BIT_CLEAR_OFDM_RXTSF_OFFSET_8822C(x) | BIT_OFDM_RXTSF_OFFSET_8822C(v))\n\n/* 2 REG_TSFTR_8822C */\n\n#define BIT_SHIFT_TSF_TIMER_V1_8822C 0\n#define BIT_MASK_TSF_TIMER_V1_8822C 0xffffffffL\n#define BIT_TSF_TIMER_V1_8822C(x)                                              \\\n\t(((x) & BIT_MASK_TSF_TIMER_V1_8822C) << BIT_SHIFT_TSF_TIMER_V1_8822C)\n#define BITS_TSF_TIMER_V1_8822C                                                \\\n\t(BIT_MASK_TSF_TIMER_V1_8822C << BIT_SHIFT_TSF_TIMER_V1_8822C)\n#define BIT_CLEAR_TSF_TIMER_V1_8822C(x) ((x) & (~BITS_TSF_TIMER_V1_8822C))\n#define BIT_GET_TSF_TIMER_V1_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_TSF_TIMER_V1_8822C) & BIT_MASK_TSF_TIMER_V1_8822C)\n#define BIT_SET_TSF_TIMER_V1_8822C(x, v)                                       \\\n\t(BIT_CLEAR_TSF_TIMER_V1_8822C(x) | BIT_TSF_TIMER_V1_8822C(v))\n\n/* 2 REG_TSFTR_1_8822C */\n\n#define BIT_SHIFT_TSF_TIMER_V2_8822C 0\n#define BIT_MASK_TSF_TIMER_V2_8822C 0xffffffffL\n#define BIT_TSF_TIMER_V2_8822C(x)                                              \\\n\t(((x) & BIT_MASK_TSF_TIMER_V2_8822C) << BIT_SHIFT_TSF_TIMER_V2_8822C)\n#define BITS_TSF_TIMER_V2_8822C                                                \\\n\t(BIT_MASK_TSF_TIMER_V2_8822C << BIT_SHIFT_TSF_TIMER_V2_8822C)\n#define BIT_CLEAR_TSF_TIMER_V2_8822C(x) ((x) & (~BITS_TSF_TIMER_V2_8822C))\n#define BIT_GET_TSF_TIMER_V2_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_TSF_TIMER_V2_8822C) & BIT_MASK_TSF_TIMER_V2_8822C)\n#define BIT_SET_TSF_TIMER_V2_8822C(x, v)                                       \\\n\t(BIT_CLEAR_TSF_TIMER_V2_8822C(x) | BIT_TSF_TIMER_V2_8822C(v))\n\n/* 2 REG_FREERUN_CNT_8822C */\n\n#define BIT_SHIFT_FREERUN_CNT_V1_8822C 0\n#define BIT_MASK_FREERUN_CNT_V1_8822C 0xffffffffL\n#define BIT_FREERUN_CNT_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_FREERUN_CNT_V1_8822C)                                 \\\n\t << BIT_SHIFT_FREERUN_CNT_V1_8822C)\n#define BITS_FREERUN_CNT_V1_8822C                                              \\\n\t(BIT_MASK_FREERUN_CNT_V1_8822C << BIT_SHIFT_FREERUN_CNT_V1_8822C)\n#define BIT_CLEAR_FREERUN_CNT_V1_8822C(x) ((x) & (~BITS_FREERUN_CNT_V1_8822C))\n#define BIT_GET_FREERUN_CNT_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_FREERUN_CNT_V1_8822C) &                             \\\n\t BIT_MASK_FREERUN_CNT_V1_8822C)\n#define BIT_SET_FREERUN_CNT_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_FREERUN_CNT_V1_8822C(x) | BIT_FREERUN_CNT_V1_8822C(v))\n\n/* 2 REG_FREERUN_CNT_1_8822C */\n\n#define BIT_SHIFT_FREERUN_CNT_V2_8822C 0\n#define BIT_MASK_FREERUN_CNT_V2_8822C 0xffffffffL\n#define BIT_FREERUN_CNT_V2_8822C(x)                                            \\\n\t(((x) & BIT_MASK_FREERUN_CNT_V2_8822C)                                 \\\n\t << BIT_SHIFT_FREERUN_CNT_V2_8822C)\n#define BITS_FREERUN_CNT_V2_8822C                                              \\\n\t(BIT_MASK_FREERUN_CNT_V2_8822C << BIT_SHIFT_FREERUN_CNT_V2_8822C)\n#define BIT_CLEAR_FREERUN_CNT_V2_8822C(x) ((x) & (~BITS_FREERUN_CNT_V2_8822C))\n#define BIT_GET_FREERUN_CNT_V2_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_FREERUN_CNT_V2_8822C) &                             \\\n\t BIT_MASK_FREERUN_CNT_V2_8822C)\n#define BIT_SET_FREERUN_CNT_V2_8822C(x, v)                                     \\\n\t(BIT_CLEAR_FREERUN_CNT_V2_8822C(x) | BIT_FREERUN_CNT_V2_8822C(v))\n\n/* 2 REG_ATIMWND1_V1_8822C */\n\n#define BIT_SHIFT_ATIMWND1_V1_8822C 0\n#define BIT_MASK_ATIMWND1_V1_8822C 0xff\n#define BIT_ATIMWND1_V1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_ATIMWND1_V1_8822C) << BIT_SHIFT_ATIMWND1_V1_8822C)\n#define BITS_ATIMWND1_V1_8822C                                                 \\\n\t(BIT_MASK_ATIMWND1_V1_8822C << BIT_SHIFT_ATIMWND1_V1_8822C)\n#define BIT_CLEAR_ATIMWND1_V1_8822C(x) ((x) & (~BITS_ATIMWND1_V1_8822C))\n#define BIT_GET_ATIMWND1_V1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_ATIMWND1_V1_8822C) & BIT_MASK_ATIMWND1_V1_8822C)\n#define BIT_SET_ATIMWND1_V1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_ATIMWND1_V1_8822C(x) | BIT_ATIMWND1_V1_8822C(v))\n\n/* 2 REG_TBTT_PROHIBIT_INFRA_8822C */\n\n#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C 0\n#define BIT_MASK_TBTT_PROHIBIT_INFRA_8822C 0xff\n#define BIT_TBTT_PROHIBIT_INFRA_8822C(x)                                       \\\n\t(((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822C)                            \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C)\n#define BITS_TBTT_PROHIBIT_INFRA_8822C                                         \\\n\t(BIT_MASK_TBTT_PROHIBIT_INFRA_8822C                                    \\\n\t << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C)\n#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822C(x)                                 \\\n\t((x) & (~BITS_TBTT_PROHIBIT_INFRA_8822C))\n#define BIT_GET_TBTT_PROHIBIT_INFRA_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C) &                        \\\n\t BIT_MASK_TBTT_PROHIBIT_INFRA_8822C)\n#define BIT_SET_TBTT_PROHIBIT_INFRA_8822C(x, v)                                \\\n\t(BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822C(x) |                              \\\n\t BIT_TBTT_PROHIBIT_INFRA_8822C(v))\n\n/* 2 REG_CTWND_8822C */\n\n#define BIT_SHIFT_CTWND_8822C 0\n#define BIT_MASK_CTWND_8822C 0xff\n#define BIT_CTWND_8822C(x)                                                     \\\n\t(((x) & BIT_MASK_CTWND_8822C) << BIT_SHIFT_CTWND_8822C)\n#define BITS_CTWND_8822C (BIT_MASK_CTWND_8822C << BIT_SHIFT_CTWND_8822C)\n#define BIT_CLEAR_CTWND_8822C(x) ((x) & (~BITS_CTWND_8822C))\n#define BIT_GET_CTWND_8822C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_CTWND_8822C) & BIT_MASK_CTWND_8822C)\n#define BIT_SET_CTWND_8822C(x, v)                                              \\\n\t(BIT_CLEAR_CTWND_8822C(x) | BIT_CTWND_8822C(v))\n\n/* 2 REG_BCNIVLCUNT_8822C */\n\n#define BIT_SHIFT_BCNIVLCUNT_8822C 0\n#define BIT_MASK_BCNIVLCUNT_8822C 0x7f\n#define BIT_BCNIVLCUNT_8822C(x)                                                \\\n\t(((x) & BIT_MASK_BCNIVLCUNT_8822C) << BIT_SHIFT_BCNIVLCUNT_8822C)\n#define BITS_BCNIVLCUNT_8822C                                                  \\\n\t(BIT_MASK_BCNIVLCUNT_8822C << BIT_SHIFT_BCNIVLCUNT_8822C)\n#define BIT_CLEAR_BCNIVLCUNT_8822C(x) ((x) & (~BITS_BCNIVLCUNT_8822C))\n#define BIT_GET_BCNIVLCUNT_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BCNIVLCUNT_8822C) & BIT_MASK_BCNIVLCUNT_8822C)\n#define BIT_SET_BCNIVLCUNT_8822C(x, v)                                         \\\n\t(BIT_CLEAR_BCNIVLCUNT_8822C(x) | BIT_BCNIVLCUNT_8822C(v))\n\n/* 2 REG_BCNDROPCTRL_8822C */\n#define BIT_BEACON_DROP_EN_8822C BIT(7)\n\n#define BIT_SHIFT_BEACON_DROP_IVL_8822C 0\n#define BIT_MASK_BEACON_DROP_IVL_8822C 0x7f\n#define BIT_BEACON_DROP_IVL_8822C(x)                                           \\\n\t(((x) & BIT_MASK_BEACON_DROP_IVL_8822C)                                \\\n\t << BIT_SHIFT_BEACON_DROP_IVL_8822C)\n#define BITS_BEACON_DROP_IVL_8822C                                             \\\n\t(BIT_MASK_BEACON_DROP_IVL_8822C << BIT_SHIFT_BEACON_DROP_IVL_8822C)\n#define BIT_CLEAR_BEACON_DROP_IVL_8822C(x) ((x) & (~BITS_BEACON_DROP_IVL_8822C))\n#define BIT_GET_BEACON_DROP_IVL_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_BEACON_DROP_IVL_8822C) &                            \\\n\t BIT_MASK_BEACON_DROP_IVL_8822C)\n#define BIT_SET_BEACON_DROP_IVL_8822C(x, v)                                    \\\n\t(BIT_CLEAR_BEACON_DROP_IVL_8822C(x) | BIT_BEACON_DROP_IVL_8822C(v))\n\n/* 2 REG_HGQ_TIMEOUT_PERIOD_8822C */\n\n#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C 0\n#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C 0xff\n#define BIT_HGQ_TIMEOUT_PERIOD_8822C(x)                                        \\\n\t(((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C)                             \\\n\t << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C)\n#define BITS_HGQ_TIMEOUT_PERIOD_8822C                                          \\\n\t(BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C                                     \\\n\t << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C)\n#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822C(x)                                  \\\n\t((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8822C))\n#define BIT_GET_HGQ_TIMEOUT_PERIOD_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C) &                         \\\n\t BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C)\n#define BIT_SET_HGQ_TIMEOUT_PERIOD_8822C(x, v)                                 \\\n\t(BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822C(x) |                               \\\n\t BIT_HGQ_TIMEOUT_PERIOD_8822C(v))\n\n/* 2 REG_TXCMD_TIMEOUT_PERIOD_8822C */\n\n#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C 0\n#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C 0xff\n#define BIT_TXCMD_TIMEOUT_PERIOD_8822C(x)                                      \\\n\t(((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C)                           \\\n\t << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C)\n#define BITS_TXCMD_TIMEOUT_PERIOD_8822C                                        \\\n\t(BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C                                   \\\n\t << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C)\n#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822C(x)                                \\\n\t((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8822C))\n#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C) &                       \\\n\t BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C)\n#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8822C(x, v)                               \\\n\t(BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822C(x) |                             \\\n\t BIT_TXCMD_TIMEOUT_PERIOD_8822C(v))\n\n/* 2 REG_MISC_CTRL_8822C */\n#define BIT_DIS_MARK_TSF_US_V2_8822C BIT(7)\n#define BIT_AUTO_SYNC_BY_TBTT_8822C BIT(6)\n#define BIT_DIS_TRX_CAL_BCN_8822C BIT(5)\n#define BIT_DIS_TX_CAL_TBTT_8822C BIT(4)\n#define BIT_EN_FREECNT_8822C BIT(3)\n#define BIT_BCN_AGGRESSION_8822C BIT(2)\n\n#define BIT_SHIFT_DIS_SECONDARY_CCA_8822C 0\n#define BIT_MASK_DIS_SECONDARY_CCA_8822C 0x3\n#define BIT_DIS_SECONDARY_CCA_8822C(x)                                         \\\n\t(((x) & BIT_MASK_DIS_SECONDARY_CCA_8822C)                              \\\n\t << BIT_SHIFT_DIS_SECONDARY_CCA_8822C)\n#define BITS_DIS_SECONDARY_CCA_8822C                                           \\\n\t(BIT_MASK_DIS_SECONDARY_CCA_8822C << BIT_SHIFT_DIS_SECONDARY_CCA_8822C)\n#define BIT_CLEAR_DIS_SECONDARY_CCA_8822C(x)                                   \\\n\t((x) & (~BITS_DIS_SECONDARY_CCA_8822C))\n#define BIT_GET_DIS_SECONDARY_CCA_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8822C) &                          \\\n\t BIT_MASK_DIS_SECONDARY_CCA_8822C)\n#define BIT_SET_DIS_SECONDARY_CCA_8822C(x, v)                                  \\\n\t(BIT_CLEAR_DIS_SECONDARY_CCA_8822C(x) | BIT_DIS_SECONDARY_CCA_8822C(v))\n\n/* 2 REG_BCN_CTRL_CLINT1_8822C */\n#define BIT_CLI1_DIS_RX_BSSID_FIT_8822C BIT(6)\n#define BIT_CLI1_DIS_TSF_UDT_8822C BIT(4)\n#define BIT_CLI1_EN_BCN_FUNCTION_8822C BIT(3)\n#define BIT_CLI1_EN_RXBCN_RPT_8822C BIT(2)\n#define BIT_CLI1_ENP2P_CTWINDOW_8822C BIT(1)\n#define BIT_CLI1_ENP2P_BCNQ_AREA_8822C BIT(0)\n\n/* 2 REG_BCN_CTRL_CLINT2_8822C */\n#define BIT_CLI2_DIS_RX_BSSID_FIT_8822C BIT(6)\n#define BIT_CLI2_DIS_TSF_UDT_8822C BIT(4)\n#define BIT_CLI2_EN_BCN_FUNCTION_8822C BIT(3)\n#define BIT_CLI2_EN_RXBCN_RPT_8822C BIT(2)\n#define BIT_CLI2_ENP2P_CTWINDOW_8822C BIT(1)\n#define BIT_CLI2_ENP2P_BCNQ_AREA_8822C BIT(0)\n\n/* 2 REG_BCN_CTRL_CLINT3_8822C */\n#define BIT_CLI3_DIS_RX_BSSID_FIT_8822C BIT(6)\n#define BIT_CLI3_DIS_TSF_UDT_8822C BIT(4)\n#define BIT_CLI3_EN_BCN_FUNCTION_8822C BIT(3)\n#define BIT_CLI3_EN_RXBCN_RPT_8822C BIT(2)\n#define BIT_CLI3_ENP2P_CTWINDOW_8822C BIT(1)\n#define BIT_CLI3_ENP2P_BCNQ_AREA_8822C BIT(0)\n\n/* 2 REG_EXTEND_CTRL_8822C */\n#define BIT_EN_TSFBIT32_RST_P2P2_8822C BIT(5)\n#define BIT_EN_TSFBIT32_RST_P2P1_8822C BIT(4)\n\n#define BIT_SHIFT_PORT_SEL_8822C 0\n#define BIT_MASK_PORT_SEL_8822C 0x7\n#define BIT_PORT_SEL_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_PORT_SEL_8822C) << BIT_SHIFT_PORT_SEL_8822C)\n#define BITS_PORT_SEL_8822C                                                    \\\n\t(BIT_MASK_PORT_SEL_8822C << BIT_SHIFT_PORT_SEL_8822C)\n#define BIT_CLEAR_PORT_SEL_8822C(x) ((x) & (~BITS_PORT_SEL_8822C))\n#define BIT_GET_PORT_SEL_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_PORT_SEL_8822C) & BIT_MASK_PORT_SEL_8822C)\n#define BIT_SET_PORT_SEL_8822C(x, v)                                           \\\n\t(BIT_CLEAR_PORT_SEL_8822C(x) | BIT_PORT_SEL_8822C(v))\n\n/* 2 REG_P2PPS1_SPEC_STATE_8822C */\n#define BIT_P2P1_SPEC_POWER_STATE_8822C BIT(7)\n#define BIT_P2P1_SPEC_CTWINDOW_ON_8822C BIT(6)\n#define BIT_P2P1_SPEC_BCN_AREA_ON_8822C BIT(5)\n#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8822C BIT(4)\n#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8822C BIT(3)\n#define BIT_P2P1_SPEC_FORCE_DOZE1_8822C BIT(2)\n#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8822C BIT(1)\n#define BIT_P2P1_SPEC_FORCE_DOZE0_8822C BIT(0)\n\n/* 2 REG_P2PPS1_STATE_8822C */\n#define BIT_P2P1_POWER_STATE_8822C BIT(7)\n#define BIT_P2P1_CTWINDOW_ON_8822C BIT(6)\n#define BIT_P2P1_BEACON_AREA_ON_8822C BIT(5)\n#define BIT_P2P1_CTWIN_EARLY_DISTX_8822C BIT(4)\n#define BIT_P2P1_NOA1_OFF_PERIOD_8822C BIT(3)\n#define BIT_P2P1_FORCE_DOZE1_8822C BIT(2)\n#define BIT_P2P1_NOA0_OFF_PERIOD_8822C BIT(1)\n#define BIT_P2P1_FORCE_DOZE0_8822C BIT(0)\n\n/* 2 REG_P2PPS2_SPEC_STATE_8822C */\n#define BIT_P2P2_SPEC_POWER_STATE_8822C BIT(7)\n#define BIT_P2P2_SPEC_CTWINDOW_ON_8822C BIT(6)\n#define BIT_P2P2_SPEC_BCN_AREA_ON_8822C BIT(5)\n#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8822C BIT(4)\n#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8822C BIT(3)\n#define BIT_P2P2_SPEC_FORCE_DOZE1_8822C BIT(2)\n#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8822C BIT(1)\n#define BIT_P2P2_SPEC_FORCE_DOZE0_8822C BIT(0)\n\n/* 2 REG_P2PPS2_STATE_8822C */\n#define BIT_P2P2_POWER_STATE_8822C BIT(7)\n#define BIT_P2P2_CTWINDOW_ON_8822C BIT(6)\n#define BIT_P2P2_BEACON_AREA_ON_8822C BIT(5)\n#define BIT_P2P2_CTWIN_EARLY_DISTX_8822C BIT(4)\n#define BIT_P2P2_NOA1_OFF_PERIOD_8822C BIT(3)\n#define BIT_P2P2_FORCE_DOZE1_8822C BIT(2)\n#define BIT_P2P2_NOA0_OFF_PERIOD_8822C BIT(1)\n#define BIT_P2P2_FORCE_DOZE0_8822C BIT(0)\n\n/* 2 REG_PS_TIMER0_8822C */\n\n#define BIT_SHIFT_PSTIMER0_INT_8822C 5\n#define BIT_MASK_PSTIMER0_INT_8822C 0x7ffffff\n#define BIT_PSTIMER0_INT_8822C(x)                                              \\\n\t(((x) & BIT_MASK_PSTIMER0_INT_8822C) << BIT_SHIFT_PSTIMER0_INT_8822C)\n#define BITS_PSTIMER0_INT_8822C                                                \\\n\t(BIT_MASK_PSTIMER0_INT_8822C << BIT_SHIFT_PSTIMER0_INT_8822C)\n#define BIT_CLEAR_PSTIMER0_INT_8822C(x) ((x) & (~BITS_PSTIMER0_INT_8822C))\n#define BIT_GET_PSTIMER0_INT_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_PSTIMER0_INT_8822C) & BIT_MASK_PSTIMER0_INT_8822C)\n#define BIT_SET_PSTIMER0_INT_8822C(x, v)                                       \\\n\t(BIT_CLEAR_PSTIMER0_INT_8822C(x) | BIT_PSTIMER0_INT_8822C(v))\n\n/* 2 REG_PS_TIMER1_8822C */\n\n#define BIT_SHIFT_PSTIMER1_INT_8822C 5\n#define BIT_MASK_PSTIMER1_INT_8822C 0x7ffffff\n#define BIT_PSTIMER1_INT_8822C(x)                                              \\\n\t(((x) & BIT_MASK_PSTIMER1_INT_8822C) << BIT_SHIFT_PSTIMER1_INT_8822C)\n#define BITS_PSTIMER1_INT_8822C                                                \\\n\t(BIT_MASK_PSTIMER1_INT_8822C << BIT_SHIFT_PSTIMER1_INT_8822C)\n#define BIT_CLEAR_PSTIMER1_INT_8822C(x) ((x) & (~BITS_PSTIMER1_INT_8822C))\n#define BIT_GET_PSTIMER1_INT_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_PSTIMER1_INT_8822C) & BIT_MASK_PSTIMER1_INT_8822C)\n#define BIT_SET_PSTIMER1_INT_8822C(x, v)                                       \\\n\t(BIT_CLEAR_PSTIMER1_INT_8822C(x) | BIT_PSTIMER1_INT_8822C(v))\n\n/* 2 REG_PS_TIMER2_8822C */\n\n#define BIT_SHIFT_PSTIMER2_INT_8822C 5\n#define BIT_MASK_PSTIMER2_INT_8822C 0x7ffffff\n#define BIT_PSTIMER2_INT_8822C(x)                                              \\\n\t(((x) & BIT_MASK_PSTIMER2_INT_8822C) << BIT_SHIFT_PSTIMER2_INT_8822C)\n#define BITS_PSTIMER2_INT_8822C                                                \\\n\t(BIT_MASK_PSTIMER2_INT_8822C << BIT_SHIFT_PSTIMER2_INT_8822C)\n#define BIT_CLEAR_PSTIMER2_INT_8822C(x) ((x) & (~BITS_PSTIMER2_INT_8822C))\n#define BIT_GET_PSTIMER2_INT_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_PSTIMER2_INT_8822C) & BIT_MASK_PSTIMER2_INT_8822C)\n#define BIT_SET_PSTIMER2_INT_8822C(x, v)                                       \\\n\t(BIT_CLEAR_PSTIMER2_INT_8822C(x) | BIT_PSTIMER2_INT_8822C(v))\n\n/* 2 REG_TBTT_CTN_AREA_8822C */\n\n#define BIT_SHIFT_TBTT_CTN_AREA_8822C 0\n#define BIT_MASK_TBTT_CTN_AREA_8822C 0xff\n#define BIT_TBTT_CTN_AREA_8822C(x)                                             \\\n\t(((x) & BIT_MASK_TBTT_CTN_AREA_8822C) << BIT_SHIFT_TBTT_CTN_AREA_8822C)\n#define BITS_TBTT_CTN_AREA_8822C                                               \\\n\t(BIT_MASK_TBTT_CTN_AREA_8822C << BIT_SHIFT_TBTT_CTN_AREA_8822C)\n#define BIT_CLEAR_TBTT_CTN_AREA_8822C(x) ((x) & (~BITS_TBTT_CTN_AREA_8822C))\n#define BIT_GET_TBTT_CTN_AREA_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TBTT_CTN_AREA_8822C) & BIT_MASK_TBTT_CTN_AREA_8822C)\n#define BIT_SET_TBTT_CTN_AREA_8822C(x, v)                                      \\\n\t(BIT_CLEAR_TBTT_CTN_AREA_8822C(x) | BIT_TBTT_CTN_AREA_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_FORCE_BCN_IFS_8822C */\n\n#define BIT_SHIFT_FORCE_BCN_IFS_8822C 0\n#define BIT_MASK_FORCE_BCN_IFS_8822C 0xff\n#define BIT_FORCE_BCN_IFS_8822C(x)                                             \\\n\t(((x) & BIT_MASK_FORCE_BCN_IFS_8822C) << BIT_SHIFT_FORCE_BCN_IFS_8822C)\n#define BITS_FORCE_BCN_IFS_8822C                                               \\\n\t(BIT_MASK_FORCE_BCN_IFS_8822C << BIT_SHIFT_FORCE_BCN_IFS_8822C)\n#define BIT_CLEAR_FORCE_BCN_IFS_8822C(x) ((x) & (~BITS_FORCE_BCN_IFS_8822C))\n#define BIT_GET_FORCE_BCN_IFS_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_FORCE_BCN_IFS_8822C) & BIT_MASK_FORCE_BCN_IFS_8822C)\n#define BIT_SET_FORCE_BCN_IFS_8822C(x, v)                                      \\\n\t(BIT_CLEAR_FORCE_BCN_IFS_8822C(x) | BIT_FORCE_BCN_IFS_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_TXOP_MIN_8822C */\n#define BIT_HIQ_NAV_BREAK_EN_8822C BIT(15)\n#define BIT_MGQ_NAV_BREAK_EN_8822C BIT(14)\n\n#define BIT_SHIFT_TXOP_MIN_8822C 0\n#define BIT_MASK_TXOP_MIN_8822C 0x3fff\n#define BIT_TXOP_MIN_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_TXOP_MIN_8822C) << BIT_SHIFT_TXOP_MIN_8822C)\n#define BITS_TXOP_MIN_8822C                                                    \\\n\t(BIT_MASK_TXOP_MIN_8822C << BIT_SHIFT_TXOP_MIN_8822C)\n#define BIT_CLEAR_TXOP_MIN_8822C(x) ((x) & (~BITS_TXOP_MIN_8822C))\n#define BIT_GET_TXOP_MIN_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TXOP_MIN_8822C) & BIT_MASK_TXOP_MIN_8822C)\n#define BIT_SET_TXOP_MIN_8822C(x, v)                                           \\\n\t(BIT_CLEAR_TXOP_MIN_8822C(x) | BIT_TXOP_MIN_8822C(v))\n\n/* 2 REG_PRE_BKF_TIME_8822C */\n\n#define BIT_SHIFT_PRE_BKF_TIME_8822C 0\n#define BIT_MASK_PRE_BKF_TIME_8822C 0xff\n#define BIT_PRE_BKF_TIME_8822C(x)                                              \\\n\t(((x) & BIT_MASK_PRE_BKF_TIME_8822C) << BIT_SHIFT_PRE_BKF_TIME_8822C)\n#define BITS_PRE_BKF_TIME_8822C                                                \\\n\t(BIT_MASK_PRE_BKF_TIME_8822C << BIT_SHIFT_PRE_BKF_TIME_8822C)\n#define BIT_CLEAR_PRE_BKF_TIME_8822C(x) ((x) & (~BITS_PRE_BKF_TIME_8822C))\n#define BIT_GET_PRE_BKF_TIME_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_PRE_BKF_TIME_8822C) & BIT_MASK_PRE_BKF_TIME_8822C)\n#define BIT_SET_PRE_BKF_TIME_8822C(x, v)                                       \\\n\t(BIT_CLEAR_PRE_BKF_TIME_8822C(x) | BIT_PRE_BKF_TIME_8822C(v))\n\n/* 2 REG_CROSS_TXOP_CTRL_8822C */\n#define BIT_TXFAIL_BREACK_TXOP_EN_8822C BIT(3)\n#define BIT_DTIM_BYPASS_8822C BIT(2)\n#define BIT_RTS_NAV_TXOP_8822C BIT(1)\n#define BIT_NOT_CROSS_TXOP_8822C BIT(0)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_RX_TBTT_SHIFT_V1_8822C */\n#define BIT_RX_TBTT_SHIFT_RW_FLAG_V1_8822C BIT(31)\n\n#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C 16\n#define BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C 0xfff\n#define BIT_RX_TBTT_SHIFT_OFFSET_V1_8822C(x)                                   \\\n\t(((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C)                        \\\n\t << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C)\n#define BITS_RX_TBTT_SHIFT_OFFSET_V1_8822C                                     \\\n\t(BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C                                \\\n\t << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C)\n#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1_8822C(x)                             \\\n\t((x) & (~BITS_RX_TBTT_SHIFT_OFFSET_V1_8822C))\n#define BIT_GET_RX_TBTT_SHIFT_OFFSET_V1_8822C(x)                               \\\n\t(((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C) &                    \\\n\t BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C)\n#define BIT_SET_RX_TBTT_SHIFT_OFFSET_V1_8822C(x, v)                            \\\n\t(BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1_8822C(x) |                          \\\n\t BIT_RX_TBTT_SHIFT_OFFSET_V1_8822C(v))\n\n#define BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C 8\n#define BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C 0x7\n#define BIT_RX_TBTT_SHIFT_SEL_V1_8822C(x)                                      \\\n\t(((x) & BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C)                           \\\n\t << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C)\n#define BITS_RX_TBTT_SHIFT_SEL_V1_8822C                                        \\\n\t(BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C                                   \\\n\t << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C)\n#define BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1_8822C(x)                                \\\n\t((x) & (~BITS_RX_TBTT_SHIFT_SEL_V1_8822C))\n#define BIT_GET_RX_TBTT_SHIFT_SEL_V1_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C) &                       \\\n\t BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C)\n#define BIT_SET_RX_TBTT_SHIFT_SEL_V1_8822C(x, v)                               \\\n\t(BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1_8822C(x) |                             \\\n\t BIT_RX_TBTT_SHIFT_SEL_V1_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_ATIMWND2_8822C */\n\n#define BIT_SHIFT_ATIMWND2_8822C 0\n#define BIT_MASK_ATIMWND2_8822C 0xff\n#define BIT_ATIMWND2_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND2_8822C) << BIT_SHIFT_ATIMWND2_8822C)\n#define BITS_ATIMWND2_8822C                                                    \\\n\t(BIT_MASK_ATIMWND2_8822C << BIT_SHIFT_ATIMWND2_8822C)\n#define BIT_CLEAR_ATIMWND2_8822C(x) ((x) & (~BITS_ATIMWND2_8822C))\n#define BIT_GET_ATIMWND2_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND2_8822C) & BIT_MASK_ATIMWND2_8822C)\n#define BIT_SET_ATIMWND2_8822C(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND2_8822C(x) | BIT_ATIMWND2_8822C(v))\n\n/* 2 REG_ATIMWND3_8822C */\n\n#define BIT_SHIFT_ATIMWND3_8822C 0\n#define BIT_MASK_ATIMWND3_8822C 0xff\n#define BIT_ATIMWND3_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND3_8822C) << BIT_SHIFT_ATIMWND3_8822C)\n#define BITS_ATIMWND3_8822C                                                    \\\n\t(BIT_MASK_ATIMWND3_8822C << BIT_SHIFT_ATIMWND3_8822C)\n#define BIT_CLEAR_ATIMWND3_8822C(x) ((x) & (~BITS_ATIMWND3_8822C))\n#define BIT_GET_ATIMWND3_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND3_8822C) & BIT_MASK_ATIMWND3_8822C)\n#define BIT_SET_ATIMWND3_8822C(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND3_8822C(x) | BIT_ATIMWND3_8822C(v))\n\n/* 2 REG_ATIMWND4_8822C */\n\n#define BIT_SHIFT_ATIMWND4_8822C 0\n#define BIT_MASK_ATIMWND4_8822C 0xff\n#define BIT_ATIMWND4_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND4_8822C) << BIT_SHIFT_ATIMWND4_8822C)\n#define BITS_ATIMWND4_8822C                                                    \\\n\t(BIT_MASK_ATIMWND4_8822C << BIT_SHIFT_ATIMWND4_8822C)\n#define BIT_CLEAR_ATIMWND4_8822C(x) ((x) & (~BITS_ATIMWND4_8822C))\n#define BIT_GET_ATIMWND4_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND4_8822C) & BIT_MASK_ATIMWND4_8822C)\n#define BIT_SET_ATIMWND4_8822C(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND4_8822C(x) | BIT_ATIMWND4_8822C(v))\n\n/* 2 REG_ATIMWND5_8822C */\n\n#define BIT_SHIFT_ATIMWND5_8822C 0\n#define BIT_MASK_ATIMWND5_8822C 0xff\n#define BIT_ATIMWND5_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND5_8822C) << BIT_SHIFT_ATIMWND5_8822C)\n#define BITS_ATIMWND5_8822C                                                    \\\n\t(BIT_MASK_ATIMWND5_8822C << BIT_SHIFT_ATIMWND5_8822C)\n#define BIT_CLEAR_ATIMWND5_8822C(x) ((x) & (~BITS_ATIMWND5_8822C))\n#define BIT_GET_ATIMWND5_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND5_8822C) & BIT_MASK_ATIMWND5_8822C)\n#define BIT_SET_ATIMWND5_8822C(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND5_8822C(x) | BIT_ATIMWND5_8822C(v))\n\n/* 2 REG_ATIMWND6_8822C */\n\n#define BIT_SHIFT_ATIMWND6_8822C 0\n#define BIT_MASK_ATIMWND6_8822C 0xff\n#define BIT_ATIMWND6_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND6_8822C) << BIT_SHIFT_ATIMWND6_8822C)\n#define BITS_ATIMWND6_8822C                                                    \\\n\t(BIT_MASK_ATIMWND6_8822C << BIT_SHIFT_ATIMWND6_8822C)\n#define BIT_CLEAR_ATIMWND6_8822C(x) ((x) & (~BITS_ATIMWND6_8822C))\n#define BIT_GET_ATIMWND6_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND6_8822C) & BIT_MASK_ATIMWND6_8822C)\n#define BIT_SET_ATIMWND6_8822C(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND6_8822C(x) | BIT_ATIMWND6_8822C(v))\n\n/* 2 REG_ATIMWND7_8822C */\n\n#define BIT_SHIFT_ATIMWND7_8822C 0\n#define BIT_MASK_ATIMWND7_8822C 0xff\n#define BIT_ATIMWND7_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_ATIMWND7_8822C) << BIT_SHIFT_ATIMWND7_8822C)\n#define BITS_ATIMWND7_8822C                                                    \\\n\t(BIT_MASK_ATIMWND7_8822C << BIT_SHIFT_ATIMWND7_8822C)\n#define BIT_CLEAR_ATIMWND7_8822C(x) ((x) & (~BITS_ATIMWND7_8822C))\n#define BIT_GET_ATIMWND7_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_ATIMWND7_8822C) & BIT_MASK_ATIMWND7_8822C)\n#define BIT_SET_ATIMWND7_8822C(x, v)                                           \\\n\t(BIT_CLEAR_ATIMWND7_8822C(x) | BIT_ATIMWND7_8822C(v))\n\n/* 2 REG_ATIMUGT_8822C */\n\n#define BIT_SHIFT_ATIM_URGENT_8822C 0\n#define BIT_MASK_ATIM_URGENT_8822C 0xff\n#define BIT_ATIM_URGENT_8822C(x)                                               \\\n\t(((x) & BIT_MASK_ATIM_URGENT_8822C) << BIT_SHIFT_ATIM_URGENT_8822C)\n#define BITS_ATIM_URGENT_8822C                                                 \\\n\t(BIT_MASK_ATIM_URGENT_8822C << BIT_SHIFT_ATIM_URGENT_8822C)\n#define BIT_CLEAR_ATIM_URGENT_8822C(x) ((x) & (~BITS_ATIM_URGENT_8822C))\n#define BIT_GET_ATIM_URGENT_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_ATIM_URGENT_8822C) & BIT_MASK_ATIM_URGENT_8822C)\n#define BIT_SET_ATIM_URGENT_8822C(x, v)                                        \\\n\t(BIT_CLEAR_ATIM_URGENT_8822C(x) | BIT_ATIM_URGENT_8822C(v))\n\n/* 2 REG_HIQ_NO_LMT_EN_8822C */\n#define BIT_HIQ_NO_LMT_EN_VAP7_8822C BIT(7)\n#define BIT_HIQ_NO_LMT_EN_VAP6_8822C BIT(6)\n#define BIT_HIQ_NO_LMT_EN_VAP5_8822C BIT(5)\n#define BIT_HIQ_NO_LMT_EN_VAP4_8822C BIT(4)\n#define BIT_HIQ_NO_LMT_EN_VAP3_8822C BIT(3)\n#define BIT_HIQ_NO_LMT_EN_VAP2_8822C BIT(2)\n#define BIT_HIQ_NO_LMT_EN_VAP1_8822C BIT(1)\n#define BIT_HIQ_NO_LMT_EN_ROOT_8822C BIT(0)\n\n/* 2 REG_DTIM_COUNTER_ROOT_8822C */\n\n#define BIT_SHIFT_DTIM_COUNT_ROOT_8822C 0\n#define BIT_MASK_DTIM_COUNT_ROOT_8822C 0xff\n#define BIT_DTIM_COUNT_ROOT_8822C(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_ROOT_8822C)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_ROOT_8822C)\n#define BITS_DTIM_COUNT_ROOT_8822C                                             \\\n\t(BIT_MASK_DTIM_COUNT_ROOT_8822C << BIT_SHIFT_DTIM_COUNT_ROOT_8822C)\n#define BIT_CLEAR_DTIM_COUNT_ROOT_8822C(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8822C))\n#define BIT_GET_DTIM_COUNT_ROOT_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8822C) &                            \\\n\t BIT_MASK_DTIM_COUNT_ROOT_8822C)\n#define BIT_SET_DTIM_COUNT_ROOT_8822C(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_ROOT_8822C(x) | BIT_DTIM_COUNT_ROOT_8822C(v))\n\n/* 2 REG_DTIM_COUNTER_VAP1_8822C */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP1_8822C 0\n#define BIT_MASK_DTIM_COUNT_VAP1_8822C 0xff\n#define BIT_DTIM_COUNT_VAP1_8822C(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP1_8822C)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP1_8822C)\n#define BITS_DTIM_COUNT_VAP1_8822C                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP1_8822C << BIT_SHIFT_DTIM_COUNT_VAP1_8822C)\n#define BIT_CLEAR_DTIM_COUNT_VAP1_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8822C))\n#define BIT_GET_DTIM_COUNT_VAP1_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8822C) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP1_8822C)\n#define BIT_SET_DTIM_COUNT_VAP1_8822C(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP1_8822C(x) | BIT_DTIM_COUNT_VAP1_8822C(v))\n\n/* 2 REG_DTIM_COUNTER_VAP2_8822C */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP2_8822C 0\n#define BIT_MASK_DTIM_COUNT_VAP2_8822C 0xff\n#define BIT_DTIM_COUNT_VAP2_8822C(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP2_8822C)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP2_8822C)\n#define BITS_DTIM_COUNT_VAP2_8822C                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP2_8822C << BIT_SHIFT_DTIM_COUNT_VAP2_8822C)\n#define BIT_CLEAR_DTIM_COUNT_VAP2_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8822C))\n#define BIT_GET_DTIM_COUNT_VAP2_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8822C) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP2_8822C)\n#define BIT_SET_DTIM_COUNT_VAP2_8822C(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP2_8822C(x) | BIT_DTIM_COUNT_VAP2_8822C(v))\n\n/* 2 REG_DTIM_COUNTER_VAP3_8822C */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP3_8822C 0\n#define BIT_MASK_DTIM_COUNT_VAP3_8822C 0xff\n#define BIT_DTIM_COUNT_VAP3_8822C(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP3_8822C)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP3_8822C)\n#define BITS_DTIM_COUNT_VAP3_8822C                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP3_8822C << BIT_SHIFT_DTIM_COUNT_VAP3_8822C)\n#define BIT_CLEAR_DTIM_COUNT_VAP3_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8822C))\n#define BIT_GET_DTIM_COUNT_VAP3_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8822C) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP3_8822C)\n#define BIT_SET_DTIM_COUNT_VAP3_8822C(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP3_8822C(x) | BIT_DTIM_COUNT_VAP3_8822C(v))\n\n/* 2 REG_DTIM_COUNTER_VAP4_8822C */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP4_8822C 0\n#define BIT_MASK_DTIM_COUNT_VAP4_8822C 0xff\n#define BIT_DTIM_COUNT_VAP4_8822C(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP4_8822C)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP4_8822C)\n#define BITS_DTIM_COUNT_VAP4_8822C                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP4_8822C << BIT_SHIFT_DTIM_COUNT_VAP4_8822C)\n#define BIT_CLEAR_DTIM_COUNT_VAP4_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8822C))\n#define BIT_GET_DTIM_COUNT_VAP4_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8822C) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP4_8822C)\n#define BIT_SET_DTIM_COUNT_VAP4_8822C(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP4_8822C(x) | BIT_DTIM_COUNT_VAP4_8822C(v))\n\n/* 2 REG_DTIM_COUNTER_VAP5_8822C */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP5_8822C 0\n#define BIT_MASK_DTIM_COUNT_VAP5_8822C 0xff\n#define BIT_DTIM_COUNT_VAP5_8822C(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP5_8822C)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP5_8822C)\n#define BITS_DTIM_COUNT_VAP5_8822C                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP5_8822C << BIT_SHIFT_DTIM_COUNT_VAP5_8822C)\n#define BIT_CLEAR_DTIM_COUNT_VAP5_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8822C))\n#define BIT_GET_DTIM_COUNT_VAP5_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8822C) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP5_8822C)\n#define BIT_SET_DTIM_COUNT_VAP5_8822C(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP5_8822C(x) | BIT_DTIM_COUNT_VAP5_8822C(v))\n\n/* 2 REG_DTIM_COUNTER_VAP6_8822C */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP6_8822C 0\n#define BIT_MASK_DTIM_COUNT_VAP6_8822C 0xff\n#define BIT_DTIM_COUNT_VAP6_8822C(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP6_8822C)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP6_8822C)\n#define BITS_DTIM_COUNT_VAP6_8822C                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP6_8822C << BIT_SHIFT_DTIM_COUNT_VAP6_8822C)\n#define BIT_CLEAR_DTIM_COUNT_VAP6_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8822C))\n#define BIT_GET_DTIM_COUNT_VAP6_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8822C) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP6_8822C)\n#define BIT_SET_DTIM_COUNT_VAP6_8822C(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP6_8822C(x) | BIT_DTIM_COUNT_VAP6_8822C(v))\n\n/* 2 REG_DTIM_COUNTER_VAP7_8822C */\n\n#define BIT_SHIFT_DTIM_COUNT_VAP7_8822C 0\n#define BIT_MASK_DTIM_COUNT_VAP7_8822C 0xff\n#define BIT_DTIM_COUNT_VAP7_8822C(x)                                           \\\n\t(((x) & BIT_MASK_DTIM_COUNT_VAP7_8822C)                                \\\n\t << BIT_SHIFT_DTIM_COUNT_VAP7_8822C)\n#define BITS_DTIM_COUNT_VAP7_8822C                                             \\\n\t(BIT_MASK_DTIM_COUNT_VAP7_8822C << BIT_SHIFT_DTIM_COUNT_VAP7_8822C)\n#define BIT_CLEAR_DTIM_COUNT_VAP7_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8822C))\n#define BIT_GET_DTIM_COUNT_VAP7_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8822C) &                            \\\n\t BIT_MASK_DTIM_COUNT_VAP7_8822C)\n#define BIT_SET_DTIM_COUNT_VAP7_8822C(x, v)                                    \\\n\t(BIT_CLEAR_DTIM_COUNT_VAP7_8822C(x) | BIT_DTIM_COUNT_VAP7_8822C(v))\n\n/* 2 REG_DIS_ATIM_8822C */\n#define BIT_DIS_ATIM_VAP7_8822C BIT(7)\n#define BIT_DIS_ATIM_VAP6_8822C BIT(6)\n#define BIT_DIS_ATIM_VAP5_8822C BIT(5)\n#define BIT_DIS_ATIM_VAP4_8822C BIT(4)\n#define BIT_DIS_ATIM_VAP3_8822C BIT(3)\n#define BIT_DIS_ATIM_VAP2_8822C BIT(2)\n#define BIT_DIS_ATIM_VAP1_8822C BIT(1)\n#define BIT_DIS_ATIM_ROOT_8822C BIT(0)\n\n/* 2 REG_EARLY_128US_8822C */\n\n#define BIT_SHIFT_TSFT_SEL_TIMER1_8822C 3\n#define BIT_MASK_TSFT_SEL_TIMER1_8822C 0x7\n#define BIT_TSFT_SEL_TIMER1_8822C(x)                                           \\\n\t(((x) & BIT_MASK_TSFT_SEL_TIMER1_8822C)                                \\\n\t << BIT_SHIFT_TSFT_SEL_TIMER1_8822C)\n#define BITS_TSFT_SEL_TIMER1_8822C                                             \\\n\t(BIT_MASK_TSFT_SEL_TIMER1_8822C << BIT_SHIFT_TSFT_SEL_TIMER1_8822C)\n#define BIT_CLEAR_TSFT_SEL_TIMER1_8822C(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8822C))\n#define BIT_GET_TSFT_SEL_TIMER1_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8822C) &                            \\\n\t BIT_MASK_TSFT_SEL_TIMER1_8822C)\n#define BIT_SET_TSFT_SEL_TIMER1_8822C(x, v)                                    \\\n\t(BIT_CLEAR_TSFT_SEL_TIMER1_8822C(x) | BIT_TSFT_SEL_TIMER1_8822C(v))\n\n#define BIT_SHIFT_EARLY_128US_8822C 0\n#define BIT_MASK_EARLY_128US_8822C 0x7\n#define BIT_EARLY_128US_8822C(x)                                               \\\n\t(((x) & BIT_MASK_EARLY_128US_8822C) << BIT_SHIFT_EARLY_128US_8822C)\n#define BITS_EARLY_128US_8822C                                                 \\\n\t(BIT_MASK_EARLY_128US_8822C << BIT_SHIFT_EARLY_128US_8822C)\n#define BIT_CLEAR_EARLY_128US_8822C(x) ((x) & (~BITS_EARLY_128US_8822C))\n#define BIT_GET_EARLY_128US_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_EARLY_128US_8822C) & BIT_MASK_EARLY_128US_8822C)\n#define BIT_SET_EARLY_128US_8822C(x, v)                                        \\\n\t(BIT_CLEAR_EARLY_128US_8822C(x) | BIT_EARLY_128US_8822C(v))\n\n/* 2 REG_P2PPS1_CTRL_8822C */\n#define BIT_P2P1_CTW_ALLSTASLEEP_8822C BIT(7)\n#define BIT_P2P1_OFF_DISTX_EN_8822C BIT(6)\n#define BIT_P2P1_PWR_MGT_EN_8822C BIT(5)\n#define BIT_P2P1_NOA1_EN_8822C BIT(2)\n#define BIT_P2P1_NOA0_EN_8822C BIT(1)\n\n/* 2 REG_P2PPS2_CTRL_8822C */\n#define BIT_P2P2_CTW_ALLSTASLEEP_8822C BIT(7)\n#define BIT_P2P2_OFF_DISTX_EN_8822C BIT(6)\n#define BIT_P2P2_PWR_MGT_EN_8822C BIT(5)\n#define BIT_P2P2_NOA1_EN_8822C BIT(2)\n#define BIT_P2P2_NOA0_EN_8822C BIT(1)\n\n/* 2 REG_TIMER0_SRC_SEL_8822C */\n\n#define BIT_SHIFT_SYNC_CLI_SEL_8822C 4\n#define BIT_MASK_SYNC_CLI_SEL_8822C 0x7\n#define BIT_SYNC_CLI_SEL_8822C(x)                                              \\\n\t(((x) & BIT_MASK_SYNC_CLI_SEL_8822C) << BIT_SHIFT_SYNC_CLI_SEL_8822C)\n#define BITS_SYNC_CLI_SEL_8822C                                                \\\n\t(BIT_MASK_SYNC_CLI_SEL_8822C << BIT_SHIFT_SYNC_CLI_SEL_8822C)\n#define BIT_CLEAR_SYNC_CLI_SEL_8822C(x) ((x) & (~BITS_SYNC_CLI_SEL_8822C))\n#define BIT_GET_SYNC_CLI_SEL_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_SYNC_CLI_SEL_8822C) & BIT_MASK_SYNC_CLI_SEL_8822C)\n#define BIT_SET_SYNC_CLI_SEL_8822C(x, v)                                       \\\n\t(BIT_CLEAR_SYNC_CLI_SEL_8822C(x) | BIT_SYNC_CLI_SEL_8822C(v))\n\n#define BIT_SHIFT_TSFT_SEL_TIMER0_8822C 0\n#define BIT_MASK_TSFT_SEL_TIMER0_8822C 0x7\n#define BIT_TSFT_SEL_TIMER0_8822C(x)                                           \\\n\t(((x) & BIT_MASK_TSFT_SEL_TIMER0_8822C)                                \\\n\t << BIT_SHIFT_TSFT_SEL_TIMER0_8822C)\n#define BITS_TSFT_SEL_TIMER0_8822C                                             \\\n\t(BIT_MASK_TSFT_SEL_TIMER0_8822C << BIT_SHIFT_TSFT_SEL_TIMER0_8822C)\n#define BIT_CLEAR_TSFT_SEL_TIMER0_8822C(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8822C))\n#define BIT_GET_TSFT_SEL_TIMER0_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8822C) &                            \\\n\t BIT_MASK_TSFT_SEL_TIMER0_8822C)\n#define BIT_SET_TSFT_SEL_TIMER0_8822C(x, v)                                    \\\n\t(BIT_CLEAR_TSFT_SEL_TIMER0_8822C(x) | BIT_TSFT_SEL_TIMER0_8822C(v))\n\n/* 2 REG_NOA_UNIT_SEL_8822C */\n\n#define BIT_SHIFT_NOA_UNIT2_SEL_8822C 8\n#define BIT_MASK_NOA_UNIT2_SEL_8822C 0x7\n#define BIT_NOA_UNIT2_SEL_8822C(x)                                             \\\n\t(((x) & BIT_MASK_NOA_UNIT2_SEL_8822C) << BIT_SHIFT_NOA_UNIT2_SEL_8822C)\n#define BITS_NOA_UNIT2_SEL_8822C                                               \\\n\t(BIT_MASK_NOA_UNIT2_SEL_8822C << BIT_SHIFT_NOA_UNIT2_SEL_8822C)\n#define BIT_CLEAR_NOA_UNIT2_SEL_8822C(x) ((x) & (~BITS_NOA_UNIT2_SEL_8822C))\n#define BIT_GET_NOA_UNIT2_SEL_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8822C) & BIT_MASK_NOA_UNIT2_SEL_8822C)\n#define BIT_SET_NOA_UNIT2_SEL_8822C(x, v)                                      \\\n\t(BIT_CLEAR_NOA_UNIT2_SEL_8822C(x) | BIT_NOA_UNIT2_SEL_8822C(v))\n\n#define BIT_SHIFT_NOA_UNIT1_SEL_8822C 4\n#define BIT_MASK_NOA_UNIT1_SEL_8822C 0x7\n#define BIT_NOA_UNIT1_SEL_8822C(x)                                             \\\n\t(((x) & BIT_MASK_NOA_UNIT1_SEL_8822C) << BIT_SHIFT_NOA_UNIT1_SEL_8822C)\n#define BITS_NOA_UNIT1_SEL_8822C                                               \\\n\t(BIT_MASK_NOA_UNIT1_SEL_8822C << BIT_SHIFT_NOA_UNIT1_SEL_8822C)\n#define BIT_CLEAR_NOA_UNIT1_SEL_8822C(x) ((x) & (~BITS_NOA_UNIT1_SEL_8822C))\n#define BIT_GET_NOA_UNIT1_SEL_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8822C) & BIT_MASK_NOA_UNIT1_SEL_8822C)\n#define BIT_SET_NOA_UNIT1_SEL_8822C(x, v)                                      \\\n\t(BIT_CLEAR_NOA_UNIT1_SEL_8822C(x) | BIT_NOA_UNIT1_SEL_8822C(v))\n\n#define BIT_SHIFT_NOA_UNIT0_SEL_8822C 0\n#define BIT_MASK_NOA_UNIT0_SEL_8822C 0x7\n#define BIT_NOA_UNIT0_SEL_8822C(x)                                             \\\n\t(((x) & BIT_MASK_NOA_UNIT0_SEL_8822C) << BIT_SHIFT_NOA_UNIT0_SEL_8822C)\n#define BITS_NOA_UNIT0_SEL_8822C                                               \\\n\t(BIT_MASK_NOA_UNIT0_SEL_8822C << BIT_SHIFT_NOA_UNIT0_SEL_8822C)\n#define BIT_CLEAR_NOA_UNIT0_SEL_8822C(x) ((x) & (~BITS_NOA_UNIT0_SEL_8822C))\n#define BIT_GET_NOA_UNIT0_SEL_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8822C) & BIT_MASK_NOA_UNIT0_SEL_8822C)\n#define BIT_SET_NOA_UNIT0_SEL_8822C(x, v)                                      \\\n\t(BIT_CLEAR_NOA_UNIT0_SEL_8822C(x) | BIT_NOA_UNIT0_SEL_8822C(v))\n\n/* 2 REG_P2POFF_DIS_TXTIME_8822C */\n\n#define BIT_SHIFT_P2POFF_DIS_TXTIME_8822C 0\n#define BIT_MASK_P2POFF_DIS_TXTIME_8822C 0xff\n#define BIT_P2POFF_DIS_TXTIME_8822C(x)                                         \\\n\t(((x) & BIT_MASK_P2POFF_DIS_TXTIME_8822C)                              \\\n\t << BIT_SHIFT_P2POFF_DIS_TXTIME_8822C)\n#define BITS_P2POFF_DIS_TXTIME_8822C                                           \\\n\t(BIT_MASK_P2POFF_DIS_TXTIME_8822C << BIT_SHIFT_P2POFF_DIS_TXTIME_8822C)\n#define BIT_CLEAR_P2POFF_DIS_TXTIME_8822C(x)                                   \\\n\t((x) & (~BITS_P2POFF_DIS_TXTIME_8822C))\n#define BIT_GET_P2POFF_DIS_TXTIME_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8822C) &                          \\\n\t BIT_MASK_P2POFF_DIS_TXTIME_8822C)\n#define BIT_SET_P2POFF_DIS_TXTIME_8822C(x, v)                                  \\\n\t(BIT_CLEAR_P2POFF_DIS_TXTIME_8822C(x) | BIT_P2POFF_DIS_TXTIME_8822C(v))\n\n/* 2 REG_MBSSID_BCN_SPACE2_8822C */\n\n#define BIT_SHIFT_BCN_SPACE_CLINT2_8822C 16\n#define BIT_MASK_BCN_SPACE_CLINT2_8822C 0xfff\n#define BIT_BCN_SPACE_CLINT2_8822C(x)                                          \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT2_8822C)                               \\\n\t << BIT_SHIFT_BCN_SPACE_CLINT2_8822C)\n#define BITS_BCN_SPACE_CLINT2_8822C                                            \\\n\t(BIT_MASK_BCN_SPACE_CLINT2_8822C << BIT_SHIFT_BCN_SPACE_CLINT2_8822C)\n#define BIT_CLEAR_BCN_SPACE_CLINT2_8822C(x)                                    \\\n\t((x) & (~BITS_BCN_SPACE_CLINT2_8822C))\n#define BIT_GET_BCN_SPACE_CLINT2_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8822C) &                           \\\n\t BIT_MASK_BCN_SPACE_CLINT2_8822C)\n#define BIT_SET_BCN_SPACE_CLINT2_8822C(x, v)                                   \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT2_8822C(x) | BIT_BCN_SPACE_CLINT2_8822C(v))\n\n#define BIT_SHIFT_BCN_SPACE_CLINT1_8822C 0\n#define BIT_MASK_BCN_SPACE_CLINT1_8822C 0xfff\n#define BIT_BCN_SPACE_CLINT1_8822C(x)                                          \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT1_8822C)                               \\\n\t << BIT_SHIFT_BCN_SPACE_CLINT1_8822C)\n#define BITS_BCN_SPACE_CLINT1_8822C                                            \\\n\t(BIT_MASK_BCN_SPACE_CLINT1_8822C << BIT_SHIFT_BCN_SPACE_CLINT1_8822C)\n#define BIT_CLEAR_BCN_SPACE_CLINT1_8822C(x)                                    \\\n\t((x) & (~BITS_BCN_SPACE_CLINT1_8822C))\n#define BIT_GET_BCN_SPACE_CLINT1_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8822C) &                           \\\n\t BIT_MASK_BCN_SPACE_CLINT1_8822C)\n#define BIT_SET_BCN_SPACE_CLINT1_8822C(x, v)                                   \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT1_8822C(x) | BIT_BCN_SPACE_CLINT1_8822C(v))\n\n/* 2 REG_MBSSID_BCN_SPACE3_8822C */\n\n#define BIT_SHIFT_SUB_BCN_SPACE_8822C 16\n#define BIT_MASK_SUB_BCN_SPACE_8822C 0xff\n#define BIT_SUB_BCN_SPACE_8822C(x)                                             \\\n\t(((x) & BIT_MASK_SUB_BCN_SPACE_8822C) << BIT_SHIFT_SUB_BCN_SPACE_8822C)\n#define BITS_SUB_BCN_SPACE_8822C                                               \\\n\t(BIT_MASK_SUB_BCN_SPACE_8822C << BIT_SHIFT_SUB_BCN_SPACE_8822C)\n#define BIT_CLEAR_SUB_BCN_SPACE_8822C(x) ((x) & (~BITS_SUB_BCN_SPACE_8822C))\n#define BIT_GET_SUB_BCN_SPACE_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SUB_BCN_SPACE_8822C) & BIT_MASK_SUB_BCN_SPACE_8822C)\n#define BIT_SET_SUB_BCN_SPACE_8822C(x, v)                                      \\\n\t(BIT_CLEAR_SUB_BCN_SPACE_8822C(x) | BIT_SUB_BCN_SPACE_8822C(v))\n\n#define BIT_SHIFT_BCN_SPACE_CLINT3_8822C 0\n#define BIT_MASK_BCN_SPACE_CLINT3_8822C 0xfff\n#define BIT_BCN_SPACE_CLINT3_8822C(x)                                          \\\n\t(((x) & BIT_MASK_BCN_SPACE_CLINT3_8822C)                               \\\n\t << BIT_SHIFT_BCN_SPACE_CLINT3_8822C)\n#define BITS_BCN_SPACE_CLINT3_8822C                                            \\\n\t(BIT_MASK_BCN_SPACE_CLINT3_8822C << BIT_SHIFT_BCN_SPACE_CLINT3_8822C)\n#define BIT_CLEAR_BCN_SPACE_CLINT3_8822C(x)                                    \\\n\t((x) & (~BITS_BCN_SPACE_CLINT3_8822C))\n#define BIT_GET_BCN_SPACE_CLINT3_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8822C) &                           \\\n\t BIT_MASK_BCN_SPACE_CLINT3_8822C)\n#define BIT_SET_BCN_SPACE_CLINT3_8822C(x, v)                                   \\\n\t(BIT_CLEAR_BCN_SPACE_CLINT3_8822C(x) | BIT_BCN_SPACE_CLINT3_8822C(v))\n\n/* 2 REG_ACMHWCTRL_8822C */\n#define BIT_BEQ_ACM_STATUS_8822C BIT(7)\n#define BIT_VIQ_ACM_STATUS_8822C BIT(6)\n#define BIT_VOQ_ACM_STATUS_8822C BIT(5)\n#define BIT_BEQ_ACM_EN_8822C BIT(3)\n#define BIT_VIQ_ACM_EN_8822C BIT(2)\n#define BIT_VOQ_ACM_EN_8822C BIT(1)\n#define BIT_ACMHWEN_8822C BIT(0)\n\n/* 2 REG_ACMRSTCTRL_8822C */\n#define BIT_BE_ACM_RESET_USED_TIME_8822C BIT(2)\n#define BIT_VI_ACM_RESET_USED_TIME_8822C BIT(1)\n#define BIT_VO_ACM_RESET_USED_TIME_8822C BIT(0)\n\n/* 2 REG_ACMAVG_8822C */\n\n#define BIT_SHIFT_AVGPERIOD_8822C 0\n#define BIT_MASK_AVGPERIOD_8822C 0xffff\n#define BIT_AVGPERIOD_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_AVGPERIOD_8822C) << BIT_SHIFT_AVGPERIOD_8822C)\n#define BITS_AVGPERIOD_8822C                                                   \\\n\t(BIT_MASK_AVGPERIOD_8822C << BIT_SHIFT_AVGPERIOD_8822C)\n#define BIT_CLEAR_AVGPERIOD_8822C(x) ((x) & (~BITS_AVGPERIOD_8822C))\n#define BIT_GET_AVGPERIOD_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_AVGPERIOD_8822C) & BIT_MASK_AVGPERIOD_8822C)\n#define BIT_SET_AVGPERIOD_8822C(x, v)                                          \\\n\t(BIT_CLEAR_AVGPERIOD_8822C(x) | BIT_AVGPERIOD_8822C(v))\n\n/* 2 REG_VO_ADMTIME_8822C */\n\n#define BIT_SHIFT_VO_ADMITTED_TIME_8822C 0\n#define BIT_MASK_VO_ADMITTED_TIME_8822C 0xffff\n#define BIT_VO_ADMITTED_TIME_8822C(x)                                          \\\n\t(((x) & BIT_MASK_VO_ADMITTED_TIME_8822C)                               \\\n\t << BIT_SHIFT_VO_ADMITTED_TIME_8822C)\n#define BITS_VO_ADMITTED_TIME_8822C                                            \\\n\t(BIT_MASK_VO_ADMITTED_TIME_8822C << BIT_SHIFT_VO_ADMITTED_TIME_8822C)\n#define BIT_CLEAR_VO_ADMITTED_TIME_8822C(x)                                    \\\n\t((x) & (~BITS_VO_ADMITTED_TIME_8822C))\n#define BIT_GET_VO_ADMITTED_TIME_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8822C) &                           \\\n\t BIT_MASK_VO_ADMITTED_TIME_8822C)\n#define BIT_SET_VO_ADMITTED_TIME_8822C(x, v)                                   \\\n\t(BIT_CLEAR_VO_ADMITTED_TIME_8822C(x) | BIT_VO_ADMITTED_TIME_8822C(v))\n\n/* 2 REG_VI_ADMTIME_8822C */\n\n#define BIT_SHIFT_VI_ADMITTED_TIME_8822C 0\n#define BIT_MASK_VI_ADMITTED_TIME_8822C 0xffff\n#define BIT_VI_ADMITTED_TIME_8822C(x)                                          \\\n\t(((x) & BIT_MASK_VI_ADMITTED_TIME_8822C)                               \\\n\t << BIT_SHIFT_VI_ADMITTED_TIME_8822C)\n#define BITS_VI_ADMITTED_TIME_8822C                                            \\\n\t(BIT_MASK_VI_ADMITTED_TIME_8822C << BIT_SHIFT_VI_ADMITTED_TIME_8822C)\n#define BIT_CLEAR_VI_ADMITTED_TIME_8822C(x)                                    \\\n\t((x) & (~BITS_VI_ADMITTED_TIME_8822C))\n#define BIT_GET_VI_ADMITTED_TIME_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8822C) &                           \\\n\t BIT_MASK_VI_ADMITTED_TIME_8822C)\n#define BIT_SET_VI_ADMITTED_TIME_8822C(x, v)                                   \\\n\t(BIT_CLEAR_VI_ADMITTED_TIME_8822C(x) | BIT_VI_ADMITTED_TIME_8822C(v))\n\n/* 2 REG_BE_ADMTIME_8822C */\n\n#define BIT_SHIFT_BE_ADMITTED_TIME_8822C 0\n#define BIT_MASK_BE_ADMITTED_TIME_8822C 0xffff\n#define BIT_BE_ADMITTED_TIME_8822C(x)                                          \\\n\t(((x) & BIT_MASK_BE_ADMITTED_TIME_8822C)                               \\\n\t << BIT_SHIFT_BE_ADMITTED_TIME_8822C)\n#define BITS_BE_ADMITTED_TIME_8822C                                            \\\n\t(BIT_MASK_BE_ADMITTED_TIME_8822C << BIT_SHIFT_BE_ADMITTED_TIME_8822C)\n#define BIT_CLEAR_BE_ADMITTED_TIME_8822C(x)                                    \\\n\t((x) & (~BITS_BE_ADMITTED_TIME_8822C))\n#define BIT_GET_BE_ADMITTED_TIME_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8822C) &                           \\\n\t BIT_MASK_BE_ADMITTED_TIME_8822C)\n#define BIT_SET_BE_ADMITTED_TIME_8822C(x, v)                                   \\\n\t(BIT_CLEAR_BE_ADMITTED_TIME_8822C(x) | BIT_BE_ADMITTED_TIME_8822C(v))\n\n/* 2 REG_MAC_HEADER_NAV_OFFSET_8822C */\n\n#define BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C 0\n#define BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C 0xff\n#define BIT_MAC_HEADER_NAV_OFFSET_8822C(x)                                     \\\n\t(((x) & BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C)                          \\\n\t << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C)\n#define BITS_MAC_HEADER_NAV_OFFSET_8822C                                       \\\n\t(BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C                                  \\\n\t << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C)\n#define BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8822C(x)                               \\\n\t((x) & (~BITS_MAC_HEADER_NAV_OFFSET_8822C))\n#define BIT_GET_MAC_HEADER_NAV_OFFSET_8822C(x)                                 \\\n\t(((x) >> BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C) &                      \\\n\t BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C)\n#define BIT_SET_MAC_HEADER_NAV_OFFSET_8822C(x, v)                              \\\n\t(BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8822C(x) |                            \\\n\t BIT_MAC_HEADER_NAV_OFFSET_8822C(v))\n\n/* 2 REG_DIS_NDPA_NAV_CHECK_8822C */\n#define BIT_CHG_POWER_BCN_AREA_V1_8822C BIT(1)\n#define BIT_DIS_NDPA_NAV_CHECK_8822C BIT(0)\n\n/* 2 REG_EDCA_RANDOM_GEN_8822C */\n\n#define BIT_SHIFT_RANDOM_GEN_8822C 0\n#define BIT_MASK_RANDOM_GEN_8822C 0xffffff\n#define BIT_RANDOM_GEN_8822C(x)                                                \\\n\t(((x) & BIT_MASK_RANDOM_GEN_8822C) << BIT_SHIFT_RANDOM_GEN_8822C)\n#define BITS_RANDOM_GEN_8822C                                                  \\\n\t(BIT_MASK_RANDOM_GEN_8822C << BIT_SHIFT_RANDOM_GEN_8822C)\n#define BIT_CLEAR_RANDOM_GEN_8822C(x) ((x) & (~BITS_RANDOM_GEN_8822C))\n#define BIT_GET_RANDOM_GEN_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_RANDOM_GEN_8822C) & BIT_MASK_RANDOM_GEN_8822C)\n#define BIT_SET_RANDOM_GEN_8822C(x, v)                                         \\\n\t(BIT_CLEAR_RANDOM_GEN_8822C(x) | BIT_RANDOM_GEN_8822C(v))\n\n/* 2 REG_TXCMD_NOA_SEL_8822C */\n\n#define BIT_SHIFT_NOA_SEL_V2_8822C 4\n#define BIT_MASK_NOA_SEL_V2_8822C 0x7\n#define BIT_NOA_SEL_V2_8822C(x)                                                \\\n\t(((x) & BIT_MASK_NOA_SEL_V2_8822C) << BIT_SHIFT_NOA_SEL_V2_8822C)\n#define BITS_NOA_SEL_V2_8822C                                                  \\\n\t(BIT_MASK_NOA_SEL_V2_8822C << BIT_SHIFT_NOA_SEL_V2_8822C)\n#define BIT_CLEAR_NOA_SEL_V2_8822C(x) ((x) & (~BITS_NOA_SEL_V2_8822C))\n#define BIT_GET_NOA_SEL_V2_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_NOA_SEL_V2_8822C) & BIT_MASK_NOA_SEL_V2_8822C)\n#define BIT_SET_NOA_SEL_V2_8822C(x, v)                                         \\\n\t(BIT_CLEAR_NOA_SEL_V2_8822C(x) | BIT_NOA_SEL_V2_8822C(v))\n\n#define BIT_SHIFT_TXCMD_SEG_SEL_8822C 0\n#define BIT_MASK_TXCMD_SEG_SEL_8822C 0xf\n#define BIT_TXCMD_SEG_SEL_8822C(x)                                             \\\n\t(((x) & BIT_MASK_TXCMD_SEG_SEL_8822C) << BIT_SHIFT_TXCMD_SEG_SEL_8822C)\n#define BITS_TXCMD_SEG_SEL_8822C                                               \\\n\t(BIT_MASK_TXCMD_SEG_SEL_8822C << BIT_SHIFT_TXCMD_SEG_SEL_8822C)\n#define BIT_CLEAR_TXCMD_SEG_SEL_8822C(x) ((x) & (~BITS_TXCMD_SEG_SEL_8822C))\n#define BIT_GET_TXCMD_SEG_SEL_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8822C) & BIT_MASK_TXCMD_SEG_SEL_8822C)\n#define BIT_SET_TXCMD_SEG_SEL_8822C(x, v)                                      \\\n\t(BIT_CLEAR_TXCMD_SEG_SEL_8822C(x) | BIT_TXCMD_SEG_SEL_8822C(v))\n\n/* 2 REG_32K_CLK_SEL_8822C */\n#define BIT_R_BCNERR_CNT_EN_8822C BIT(20)\n\n#define BIT_SHIFT_R_BCNERR_PORT_SEL_8822C 16\n#define BIT_MASK_R_BCNERR_PORT_SEL_8822C 0x7\n#define BIT_R_BCNERR_PORT_SEL_8822C(x)                                         \\\n\t(((x) & BIT_MASK_R_BCNERR_PORT_SEL_8822C)                              \\\n\t << BIT_SHIFT_R_BCNERR_PORT_SEL_8822C)\n#define BITS_R_BCNERR_PORT_SEL_8822C                                           \\\n\t(BIT_MASK_R_BCNERR_PORT_SEL_8822C << BIT_SHIFT_R_BCNERR_PORT_SEL_8822C)\n#define BIT_CLEAR_R_BCNERR_PORT_SEL_8822C(x)                                   \\\n\t((x) & (~BITS_R_BCNERR_PORT_SEL_8822C))\n#define BIT_GET_R_BCNERR_PORT_SEL_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_BCNERR_PORT_SEL_8822C) &                          \\\n\t BIT_MASK_R_BCNERR_PORT_SEL_8822C)\n#define BIT_SET_R_BCNERR_PORT_SEL_8822C(x, v)                                  \\\n\t(BIT_CLEAR_R_BCNERR_PORT_SEL_8822C(x) | BIT_R_BCNERR_PORT_SEL_8822C(v))\n\n#define BIT_SHIFT_R_TXPAUSE1_8822C 8\n#define BIT_MASK_R_TXPAUSE1_8822C 0xff\n#define BIT_R_TXPAUSE1_8822C(x)                                                \\\n\t(((x) & BIT_MASK_R_TXPAUSE1_8822C) << BIT_SHIFT_R_TXPAUSE1_8822C)\n#define BITS_R_TXPAUSE1_8822C                                                  \\\n\t(BIT_MASK_R_TXPAUSE1_8822C << BIT_SHIFT_R_TXPAUSE1_8822C)\n#define BIT_CLEAR_R_TXPAUSE1_8822C(x) ((x) & (~BITS_R_TXPAUSE1_8822C))\n#define BIT_GET_R_TXPAUSE1_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_R_TXPAUSE1_8822C) & BIT_MASK_R_TXPAUSE1_8822C)\n#define BIT_SET_R_TXPAUSE1_8822C(x, v)                                         \\\n\t(BIT_CLEAR_R_TXPAUSE1_8822C(x) | BIT_R_TXPAUSE1_8822C(v))\n\n#define BIT_SLEEP_32K_EN_V1_8822C BIT(2)\n\n#define BIT_SHIFT_BW_CFG_8822C 0\n#define BIT_MASK_BW_CFG_8822C 0x3\n#define BIT_BW_CFG_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_BW_CFG_8822C) << BIT_SHIFT_BW_CFG_8822C)\n#define BITS_BW_CFG_8822C (BIT_MASK_BW_CFG_8822C << BIT_SHIFT_BW_CFG_8822C)\n#define BIT_CLEAR_BW_CFG_8822C(x) ((x) & (~BITS_BW_CFG_8822C))\n#define BIT_GET_BW_CFG_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_BW_CFG_8822C) & BIT_MASK_BW_CFG_8822C)\n#define BIT_SET_BW_CFG_8822C(x, v)                                             \\\n\t(BIT_CLEAR_BW_CFG_8822C(x) | BIT_BW_CFG_8822C(v))\n\n/* 2 REG_EARLYINT_ADJUST_8822C */\n\n#define BIT_SHIFT_RXBCN_TIMER_8822C 16\n#define BIT_MASK_RXBCN_TIMER_8822C 0xffff\n#define BIT_RXBCN_TIMER_8822C(x)                                               \\\n\t(((x) & BIT_MASK_RXBCN_TIMER_8822C) << BIT_SHIFT_RXBCN_TIMER_8822C)\n#define BITS_RXBCN_TIMER_8822C                                                 \\\n\t(BIT_MASK_RXBCN_TIMER_8822C << BIT_SHIFT_RXBCN_TIMER_8822C)\n#define BIT_CLEAR_RXBCN_TIMER_8822C(x) ((x) & (~BITS_RXBCN_TIMER_8822C))\n#define BIT_GET_RXBCN_TIMER_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RXBCN_TIMER_8822C) & BIT_MASK_RXBCN_TIMER_8822C)\n#define BIT_SET_RXBCN_TIMER_8822C(x, v)                                        \\\n\t(BIT_CLEAR_RXBCN_TIMER_8822C(x) | BIT_RXBCN_TIMER_8822C(v))\n\n#define BIT_SHIFT_R_ERLYINTADJ_8822C 0\n#define BIT_MASK_R_ERLYINTADJ_8822C 0xffff\n#define BIT_R_ERLYINTADJ_8822C(x)                                              \\\n\t(((x) & BIT_MASK_R_ERLYINTADJ_8822C) << BIT_SHIFT_R_ERLYINTADJ_8822C)\n#define BITS_R_ERLYINTADJ_8822C                                                \\\n\t(BIT_MASK_R_ERLYINTADJ_8822C << BIT_SHIFT_R_ERLYINTADJ_8822C)\n#define BIT_CLEAR_R_ERLYINTADJ_8822C(x) ((x) & (~BITS_R_ERLYINTADJ_8822C))\n#define BIT_GET_R_ERLYINTADJ_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_ERLYINTADJ_8822C) & BIT_MASK_R_ERLYINTADJ_8822C)\n#define BIT_SET_R_ERLYINTADJ_8822C(x, v)                                       \\\n\t(BIT_CLEAR_R_ERLYINTADJ_8822C(x) | BIT_R_ERLYINTADJ_8822C(v))\n\n/* 2 REG_BCNERR_CNT_8822C */\n\n#define BIT_SHIFT_BCNERR_CNT_OTHERS_8822C 24\n#define BIT_MASK_BCNERR_CNT_OTHERS_8822C 0xff\n#define BIT_BCNERR_CNT_OTHERS_8822C(x)                                         \\\n\t(((x) & BIT_MASK_BCNERR_CNT_OTHERS_8822C)                              \\\n\t << BIT_SHIFT_BCNERR_CNT_OTHERS_8822C)\n#define BITS_BCNERR_CNT_OTHERS_8822C                                           \\\n\t(BIT_MASK_BCNERR_CNT_OTHERS_8822C << BIT_SHIFT_BCNERR_CNT_OTHERS_8822C)\n#define BIT_CLEAR_BCNERR_CNT_OTHERS_8822C(x)                                   \\\n\t((x) & (~BITS_BCNERR_CNT_OTHERS_8822C))\n#define BIT_GET_BCNERR_CNT_OTHERS_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS_8822C) &                          \\\n\t BIT_MASK_BCNERR_CNT_OTHERS_8822C)\n#define BIT_SET_BCNERR_CNT_OTHERS_8822C(x, v)                                  \\\n\t(BIT_CLEAR_BCNERR_CNT_OTHERS_8822C(x) | BIT_BCNERR_CNT_OTHERS_8822C(v))\n\n#define BIT_SHIFT_BCNERR_CNT_INVALID_8822C 16\n#define BIT_MASK_BCNERR_CNT_INVALID_8822C 0xff\n#define BIT_BCNERR_CNT_INVALID_8822C(x)                                        \\\n\t(((x) & BIT_MASK_BCNERR_CNT_INVALID_8822C)                             \\\n\t << BIT_SHIFT_BCNERR_CNT_INVALID_8822C)\n#define BITS_BCNERR_CNT_INVALID_8822C                                          \\\n\t(BIT_MASK_BCNERR_CNT_INVALID_8822C                                     \\\n\t << BIT_SHIFT_BCNERR_CNT_INVALID_8822C)\n#define BIT_CLEAR_BCNERR_CNT_INVALID_8822C(x)                                  \\\n\t((x) & (~BITS_BCNERR_CNT_INVALID_8822C))\n#define BIT_GET_BCNERR_CNT_INVALID_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_BCNERR_CNT_INVALID_8822C) &                         \\\n\t BIT_MASK_BCNERR_CNT_INVALID_8822C)\n#define BIT_SET_BCNERR_CNT_INVALID_8822C(x, v)                                 \\\n\t(BIT_CLEAR_BCNERR_CNT_INVALID_8822C(x) |                               \\\n\t BIT_BCNERR_CNT_INVALID_8822C(v))\n\n#define BIT_SHIFT_BCNERR_CNT_MAC_8822C 8\n#define BIT_MASK_BCNERR_CNT_MAC_8822C 0xff\n#define BIT_BCNERR_CNT_MAC_8822C(x)                                            \\\n\t(((x) & BIT_MASK_BCNERR_CNT_MAC_8822C)                                 \\\n\t << BIT_SHIFT_BCNERR_CNT_MAC_8822C)\n#define BITS_BCNERR_CNT_MAC_8822C                                              \\\n\t(BIT_MASK_BCNERR_CNT_MAC_8822C << BIT_SHIFT_BCNERR_CNT_MAC_8822C)\n#define BIT_CLEAR_BCNERR_CNT_MAC_8822C(x) ((x) & (~BITS_BCNERR_CNT_MAC_8822C))\n#define BIT_GET_BCNERR_CNT_MAC_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNERR_CNT_MAC_8822C) &                             \\\n\t BIT_MASK_BCNERR_CNT_MAC_8822C)\n#define BIT_SET_BCNERR_CNT_MAC_8822C(x, v)                                     \\\n\t(BIT_CLEAR_BCNERR_CNT_MAC_8822C(x) | BIT_BCNERR_CNT_MAC_8822C(v))\n\n#define BIT_SHIFT_BCNERR_CNT_CCA_8822C 0\n#define BIT_MASK_BCNERR_CNT_CCA_8822C 0xff\n#define BIT_BCNERR_CNT_CCA_8822C(x)                                            \\\n\t(((x) & BIT_MASK_BCNERR_CNT_CCA_8822C)                                 \\\n\t << BIT_SHIFT_BCNERR_CNT_CCA_8822C)\n#define BITS_BCNERR_CNT_CCA_8822C                                              \\\n\t(BIT_MASK_BCNERR_CNT_CCA_8822C << BIT_SHIFT_BCNERR_CNT_CCA_8822C)\n#define BIT_CLEAR_BCNERR_CNT_CCA_8822C(x) ((x) & (~BITS_BCNERR_CNT_CCA_8822C))\n#define BIT_GET_BCNERR_CNT_CCA_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_BCNERR_CNT_CCA_8822C) &                             \\\n\t BIT_MASK_BCNERR_CNT_CCA_8822C)\n#define BIT_SET_BCNERR_CNT_CCA_8822C(x, v)                                     \\\n\t(BIT_CLEAR_BCNERR_CNT_CCA_8822C(x) | BIT_BCNERR_CNT_CCA_8822C(v))\n\n/* 2 REG_BCNERR_CNT_2_8822C */\n\n#define BIT_SHIFT_BCNERR_CNT_EDCCA_8822C 0\n#define BIT_MASK_BCNERR_CNT_EDCCA_8822C 0xff\n#define BIT_BCNERR_CNT_EDCCA_8822C(x)                                          \\\n\t(((x) & BIT_MASK_BCNERR_CNT_EDCCA_8822C)                               \\\n\t << BIT_SHIFT_BCNERR_CNT_EDCCA_8822C)\n#define BITS_BCNERR_CNT_EDCCA_8822C                                            \\\n\t(BIT_MASK_BCNERR_CNT_EDCCA_8822C << BIT_SHIFT_BCNERR_CNT_EDCCA_8822C)\n#define BIT_CLEAR_BCNERR_CNT_EDCCA_8822C(x)                                    \\\n\t((x) & (~BITS_BCNERR_CNT_EDCCA_8822C))\n#define BIT_GET_BCNERR_CNT_EDCCA_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BCNERR_CNT_EDCCA_8822C) &                           \\\n\t BIT_MASK_BCNERR_CNT_EDCCA_8822C)\n#define BIT_SET_BCNERR_CNT_EDCCA_8822C(x, v)                                   \\\n\t(BIT_CLEAR_BCNERR_CNT_EDCCA_8822C(x) | BIT_BCNERR_CNT_EDCCA_8822C(v))\n\n/* 2 REG_NOA_PARAM_8822C */\n\n#define BIT_SHIFT_NOA_DURATION_V1_8822C 0\n#define BIT_MASK_NOA_DURATION_V1_8822C 0xffffffffL\n#define BIT_NOA_DURATION_V1_8822C(x)                                           \\\n\t(((x) & BIT_MASK_NOA_DURATION_V1_8822C)                                \\\n\t << BIT_SHIFT_NOA_DURATION_V1_8822C)\n#define BITS_NOA_DURATION_V1_8822C                                             \\\n\t(BIT_MASK_NOA_DURATION_V1_8822C << BIT_SHIFT_NOA_DURATION_V1_8822C)\n#define BIT_CLEAR_NOA_DURATION_V1_8822C(x) ((x) & (~BITS_NOA_DURATION_V1_8822C))\n#define BIT_GET_NOA_DURATION_V1_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_NOA_DURATION_V1_8822C) &                            \\\n\t BIT_MASK_NOA_DURATION_V1_8822C)\n#define BIT_SET_NOA_DURATION_V1_8822C(x, v)                                    \\\n\t(BIT_CLEAR_NOA_DURATION_V1_8822C(x) | BIT_NOA_DURATION_V1_8822C(v))\n\n/* 2 REG_NOA_PARAM_1_8822C */\n\n#define BIT_SHIFT_NOA_INTERVAL_V1_8822C 0\n#define BIT_MASK_NOA_INTERVAL_V1_8822C 0xffffffffL\n#define BIT_NOA_INTERVAL_V1_8822C(x)                                           \\\n\t(((x) & BIT_MASK_NOA_INTERVAL_V1_8822C)                                \\\n\t << BIT_SHIFT_NOA_INTERVAL_V1_8822C)\n#define BITS_NOA_INTERVAL_V1_8822C                                             \\\n\t(BIT_MASK_NOA_INTERVAL_V1_8822C << BIT_SHIFT_NOA_INTERVAL_V1_8822C)\n#define BIT_CLEAR_NOA_INTERVAL_V1_8822C(x) ((x) & (~BITS_NOA_INTERVAL_V1_8822C))\n#define BIT_GET_NOA_INTERVAL_V1_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_NOA_INTERVAL_V1_8822C) &                            \\\n\t BIT_MASK_NOA_INTERVAL_V1_8822C)\n#define BIT_SET_NOA_INTERVAL_V1_8822C(x, v)                                    \\\n\t(BIT_CLEAR_NOA_INTERVAL_V1_8822C(x) | BIT_NOA_INTERVAL_V1_8822C(v))\n\n/* 2 REG_NOA_PARAM_2_8822C */\n\n#define BIT_SHIFT_NOA_START_TIME_V1_8822C 0\n#define BIT_MASK_NOA_START_TIME_V1_8822C 0xffffffffL\n#define BIT_NOA_START_TIME_V1_8822C(x)                                         \\\n\t(((x) & BIT_MASK_NOA_START_TIME_V1_8822C)                              \\\n\t << BIT_SHIFT_NOA_START_TIME_V1_8822C)\n#define BITS_NOA_START_TIME_V1_8822C                                           \\\n\t(BIT_MASK_NOA_START_TIME_V1_8822C << BIT_SHIFT_NOA_START_TIME_V1_8822C)\n#define BIT_CLEAR_NOA_START_TIME_V1_8822C(x)                                   \\\n\t((x) & (~BITS_NOA_START_TIME_V1_8822C))\n#define BIT_GET_NOA_START_TIME_V1_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_NOA_START_TIME_V1_8822C) &                          \\\n\t BIT_MASK_NOA_START_TIME_V1_8822C)\n#define BIT_SET_NOA_START_TIME_V1_8822C(x, v)                                  \\\n\t(BIT_CLEAR_NOA_START_TIME_V1_8822C(x) | BIT_NOA_START_TIME_V1_8822C(v))\n\n/* 2 REG_NOA_PARAM_3_8822C */\n\n#define BIT_SHIFT_NOA_COUNT_V1_8822C 0\n#define BIT_MASK_NOA_COUNT_V1_8822C 0xffffffffL\n#define BIT_NOA_COUNT_V1_8822C(x)                                              \\\n\t(((x) & BIT_MASK_NOA_COUNT_V1_8822C) << BIT_SHIFT_NOA_COUNT_V1_8822C)\n#define BITS_NOA_COUNT_V1_8822C                                                \\\n\t(BIT_MASK_NOA_COUNT_V1_8822C << BIT_SHIFT_NOA_COUNT_V1_8822C)\n#define BIT_CLEAR_NOA_COUNT_V1_8822C(x) ((x) & (~BITS_NOA_COUNT_V1_8822C))\n#define BIT_GET_NOA_COUNT_V1_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_NOA_COUNT_V1_8822C) & BIT_MASK_NOA_COUNT_V1_8822C)\n#define BIT_SET_NOA_COUNT_V1_8822C(x, v)                                       \\\n\t(BIT_CLEAR_NOA_COUNT_V1_8822C(x) | BIT_NOA_COUNT_V1_8822C(v))\n\n/* 2 REG_P2P_RST_8822C */\n#define BIT_P2P2_PWR_RST1_8822C BIT(5)\n#define BIT_P2P2_PWR_RST0_8822C BIT(4)\n#define BIT_P2P1_PWR_RST1_8822C BIT(3)\n#define BIT_P2P1_PWR_RST0_8822C BIT(2)\n#define BIT_P2P_PWR_RST1_V1_8822C BIT(1)\n#define BIT_P2P_PWR_RST0_V1_8822C BIT(0)\n\n/* 2 REG_SCHEDULER_RST_8822C */\n#define BIT_SYNC_CLI_ONCE_RIGHT_NOW_8822C BIT(2)\n#define BIT_SYNC_CLI_ONCE_BY_TBTT_8822C BIT(1)\n#define BIT_SCHEDULER_RST_V1_8822C BIT(0)\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_SCH_DBG_VALUE_8822C */\n\n#define BIT_SHIFT_SCH_DBG_VALUE_8822C 0\n#define BIT_MASK_SCH_DBG_VALUE_8822C 0xffffffffL\n#define BIT_SCH_DBG_VALUE_8822C(x)                                             \\\n\t(((x) & BIT_MASK_SCH_DBG_VALUE_8822C) << BIT_SHIFT_SCH_DBG_VALUE_8822C)\n#define BITS_SCH_DBG_VALUE_8822C                                               \\\n\t(BIT_MASK_SCH_DBG_VALUE_8822C << BIT_SHIFT_SCH_DBG_VALUE_8822C)\n#define BIT_CLEAR_SCH_DBG_VALUE_8822C(x) ((x) & (~BITS_SCH_DBG_VALUE_8822C))\n#define BIT_GET_SCH_DBG_VALUE_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SCH_DBG_VALUE_8822C) & BIT_MASK_SCH_DBG_VALUE_8822C)\n#define BIT_SET_SCH_DBG_VALUE_8822C(x, v)                                      \\\n\t(BIT_CLEAR_SCH_DBG_VALUE_8822C(x) | BIT_SCH_DBG_VALUE_8822C(v))\n\n/* 2 REG_SCH_TXCMD_8822C */\n\n#define BIT_SHIFT_SCH_TXCMD_8822C 0\n#define BIT_MASK_SCH_TXCMD_8822C 0xffffffffL\n#define BIT_SCH_TXCMD_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_SCH_TXCMD_8822C) << BIT_SHIFT_SCH_TXCMD_8822C)\n#define BITS_SCH_TXCMD_8822C                                                   \\\n\t(BIT_MASK_SCH_TXCMD_8822C << BIT_SHIFT_SCH_TXCMD_8822C)\n#define BIT_CLEAR_SCH_TXCMD_8822C(x) ((x) & (~BITS_SCH_TXCMD_8822C))\n#define BIT_GET_SCH_TXCMD_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_SCH_TXCMD_8822C) & BIT_MASK_SCH_TXCMD_8822C)\n#define BIT_SET_SCH_TXCMD_8822C(x, v)                                          \\\n\t(BIT_CLEAR_SCH_TXCMD_8822C(x) | BIT_SCH_TXCMD_8822C(v))\n\n/* 2 REG_PAGE5_DUMMY_8822C */\n\n/* 2 REG_CPUMGQ_TX_TIMER_8822C */\n\n#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C 0\n#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C 0xffffffffL\n#define BIT_CPUMGQ_TX_TIMER_V1_8822C(x)                                        \\\n\t(((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C)                             \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C)\n#define BITS_CPUMGQ_TX_TIMER_V1_8822C                                          \\\n\t(BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C                                     \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C)\n#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822C(x)                                  \\\n\t((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8822C))\n#define BIT_GET_CPUMGQ_TX_TIMER_V1_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C) &                         \\\n\t BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C)\n#define BIT_SET_CPUMGQ_TX_TIMER_V1_8822C(x, v)                                 \\\n\t(BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822C(x) |                               \\\n\t BIT_CPUMGQ_TX_TIMER_V1_8822C(v))\n\n/* 2 REG_PS_TIMER_A_8822C */\n\n#define BIT_SHIFT_PS_TIMER_A_V1_8822C 0\n#define BIT_MASK_PS_TIMER_A_V1_8822C 0xffffffffL\n#define BIT_PS_TIMER_A_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_PS_TIMER_A_V1_8822C) << BIT_SHIFT_PS_TIMER_A_V1_8822C)\n#define BITS_PS_TIMER_A_V1_8822C                                               \\\n\t(BIT_MASK_PS_TIMER_A_V1_8822C << BIT_SHIFT_PS_TIMER_A_V1_8822C)\n#define BIT_CLEAR_PS_TIMER_A_V1_8822C(x) ((x) & (~BITS_PS_TIMER_A_V1_8822C))\n#define BIT_GET_PS_TIMER_A_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_A_V1_8822C) & BIT_MASK_PS_TIMER_A_V1_8822C)\n#define BIT_SET_PS_TIMER_A_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_PS_TIMER_A_V1_8822C(x) | BIT_PS_TIMER_A_V1_8822C(v))\n\n/* 2 REG_PS_TIMER_B_8822C */\n\n#define BIT_SHIFT_PS_TIMER_B_V1_8822C 0\n#define BIT_MASK_PS_TIMER_B_V1_8822C 0xffffffffL\n#define BIT_PS_TIMER_B_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_PS_TIMER_B_V1_8822C) << BIT_SHIFT_PS_TIMER_B_V1_8822C)\n#define BITS_PS_TIMER_B_V1_8822C                                               \\\n\t(BIT_MASK_PS_TIMER_B_V1_8822C << BIT_SHIFT_PS_TIMER_B_V1_8822C)\n#define BIT_CLEAR_PS_TIMER_B_V1_8822C(x) ((x) & (~BITS_PS_TIMER_B_V1_8822C))\n#define BIT_GET_PS_TIMER_B_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_B_V1_8822C) & BIT_MASK_PS_TIMER_B_V1_8822C)\n#define BIT_SET_PS_TIMER_B_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_PS_TIMER_B_V1_8822C(x) | BIT_PS_TIMER_B_V1_8822C(v))\n\n/* 2 REG_PS_TIMER_C_8822C */\n\n#define BIT_SHIFT_PS_TIMER_C_V1_8822C 0\n#define BIT_MASK_PS_TIMER_C_V1_8822C 0xffffffffL\n#define BIT_PS_TIMER_C_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_PS_TIMER_C_V1_8822C) << BIT_SHIFT_PS_TIMER_C_V1_8822C)\n#define BITS_PS_TIMER_C_V1_8822C                                               \\\n\t(BIT_MASK_PS_TIMER_C_V1_8822C << BIT_SHIFT_PS_TIMER_C_V1_8822C)\n#define BIT_CLEAR_PS_TIMER_C_V1_8822C(x) ((x) & (~BITS_PS_TIMER_C_V1_8822C))\n#define BIT_GET_PS_TIMER_C_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_C_V1_8822C) & BIT_MASK_PS_TIMER_C_V1_8822C)\n#define BIT_SET_PS_TIMER_C_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_PS_TIMER_C_V1_8822C(x) | BIT_PS_TIMER_C_V1_8822C(v))\n\n/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822C */\n#define BIT_CPUMGQ_TIMER_EN_8822C BIT(31)\n#define BIT_CPUMGQ_TX_EN_8822C BIT(28)\n\n#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C 24\n#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C 0x7\n#define BIT_CPUMGQ_TIMER_TSF_SEL_8822C(x)                                      \\\n\t(((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C)                           \\\n\t << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C)\n#define BITS_CPUMGQ_TIMER_TSF_SEL_8822C                                        \\\n\t(BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C                                   \\\n\t << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C)\n#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822C(x)                                \\\n\t((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8822C))\n#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C) &                       \\\n\t BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C)\n#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8822C(x, v)                               \\\n\t(BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822C(x) |                             \\\n\t BIT_CPUMGQ_TIMER_TSF_SEL_8822C(v))\n\n#define BIT_PS_TIMER_C_EN_8822C BIT(23)\n\n#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C 16\n#define BIT_MASK_PS_TIMER_C_TSF_SEL_8822C 0x7\n#define BIT_PS_TIMER_C_TSF_SEL_8822C(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822C)                             \\\n\t << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C)\n#define BITS_PS_TIMER_C_TSF_SEL_8822C                                          \\\n\t(BIT_MASK_PS_TIMER_C_TSF_SEL_8822C                                     \\\n\t << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C)\n#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822C(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_C_TSF_SEL_8822C))\n#define BIT_GET_PS_TIMER_C_TSF_SEL_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C) &                         \\\n\t BIT_MASK_PS_TIMER_C_TSF_SEL_8822C)\n#define BIT_SET_PS_TIMER_C_TSF_SEL_8822C(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822C(x) |                               \\\n\t BIT_PS_TIMER_C_TSF_SEL_8822C(v))\n\n#define BIT_PS_TIMER_B_EN_8822C BIT(15)\n\n#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C 8\n#define BIT_MASK_PS_TIMER_B_TSF_SEL_8822C 0x7\n#define BIT_PS_TIMER_B_TSF_SEL_8822C(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822C)                             \\\n\t << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C)\n#define BITS_PS_TIMER_B_TSF_SEL_8822C                                          \\\n\t(BIT_MASK_PS_TIMER_B_TSF_SEL_8822C                                     \\\n\t << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C)\n#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822C(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_B_TSF_SEL_8822C))\n#define BIT_GET_PS_TIMER_B_TSF_SEL_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C) &                         \\\n\t BIT_MASK_PS_TIMER_B_TSF_SEL_8822C)\n#define BIT_SET_PS_TIMER_B_TSF_SEL_8822C(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822C(x) |                               \\\n\t BIT_PS_TIMER_B_TSF_SEL_8822C(v))\n\n#define BIT_PS_TIMER_A_EN_8822C BIT(7)\n\n#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C 0\n#define BIT_MASK_PS_TIMER_A_TSF_SEL_8822C 0x7\n#define BIT_PS_TIMER_A_TSF_SEL_8822C(x)                                        \\\n\t(((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822C)                             \\\n\t << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C)\n#define BITS_PS_TIMER_A_TSF_SEL_8822C                                          \\\n\t(BIT_MASK_PS_TIMER_A_TSF_SEL_8822C                                     \\\n\t << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C)\n#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822C(x)                                  \\\n\t((x) & (~BITS_PS_TIMER_A_TSF_SEL_8822C))\n#define BIT_GET_PS_TIMER_A_TSF_SEL_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C) &                         \\\n\t BIT_MASK_PS_TIMER_A_TSF_SEL_8822C)\n#define BIT_SET_PS_TIMER_A_TSF_SEL_8822C(x, v)                                 \\\n\t(BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822C(x) |                               \\\n\t BIT_PS_TIMER_A_TSF_SEL_8822C(v))\n\n/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8822C */\n\n#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C 0\n#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C 0xff\n#define BIT_CPUMGQ_TX_TIMER_EARLY_8822C(x)                                     \\\n\t(((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C)                          \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C)\n#define BITS_CPUMGQ_TX_TIMER_EARLY_8822C                                       \\\n\t(BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C                                  \\\n\t << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C)\n#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822C(x)                               \\\n\t((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8822C))\n#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8822C(x)                                 \\\n\t(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C) &                      \\\n\t BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C)\n#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8822C(x, v)                              \\\n\t(BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822C(x) |                            \\\n\t BIT_CPUMGQ_TX_TIMER_EARLY_8822C(v))\n\n/* 2 REG_PS_TIMER_A_EARLY_8822C */\n\n#define BIT_SHIFT_PS_TIMER_A_EARLY_8822C 0\n#define BIT_MASK_PS_TIMER_A_EARLY_8822C 0xff\n#define BIT_PS_TIMER_A_EARLY_8822C(x)                                          \\\n\t(((x) & BIT_MASK_PS_TIMER_A_EARLY_8822C)                               \\\n\t << BIT_SHIFT_PS_TIMER_A_EARLY_8822C)\n#define BITS_PS_TIMER_A_EARLY_8822C                                            \\\n\t(BIT_MASK_PS_TIMER_A_EARLY_8822C << BIT_SHIFT_PS_TIMER_A_EARLY_8822C)\n#define BIT_CLEAR_PS_TIMER_A_EARLY_8822C(x)                                    \\\n\t((x) & (~BITS_PS_TIMER_A_EARLY_8822C))\n#define BIT_GET_PS_TIMER_A_EARLY_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8822C) &                           \\\n\t BIT_MASK_PS_TIMER_A_EARLY_8822C)\n#define BIT_SET_PS_TIMER_A_EARLY_8822C(x, v)                                   \\\n\t(BIT_CLEAR_PS_TIMER_A_EARLY_8822C(x) | BIT_PS_TIMER_A_EARLY_8822C(v))\n\n/* 2 REG_PS_TIMER_B_EARLY_8822C */\n\n#define BIT_SHIFT_PS_TIMER_B_EARLY_8822C 0\n#define BIT_MASK_PS_TIMER_B_EARLY_8822C 0xff\n#define BIT_PS_TIMER_B_EARLY_8822C(x)                                          \\\n\t(((x) & BIT_MASK_PS_TIMER_B_EARLY_8822C)                               \\\n\t << BIT_SHIFT_PS_TIMER_B_EARLY_8822C)\n#define BITS_PS_TIMER_B_EARLY_8822C                                            \\\n\t(BIT_MASK_PS_TIMER_B_EARLY_8822C << BIT_SHIFT_PS_TIMER_B_EARLY_8822C)\n#define BIT_CLEAR_PS_TIMER_B_EARLY_8822C(x)                                    \\\n\t((x) & (~BITS_PS_TIMER_B_EARLY_8822C))\n#define BIT_GET_PS_TIMER_B_EARLY_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8822C) &                           \\\n\t BIT_MASK_PS_TIMER_B_EARLY_8822C)\n#define BIT_SET_PS_TIMER_B_EARLY_8822C(x, v)                                   \\\n\t(BIT_CLEAR_PS_TIMER_B_EARLY_8822C(x) | BIT_PS_TIMER_B_EARLY_8822C(v))\n\n/* 2 REG_PS_TIMER_C_EARLY_8822C */\n\n#define BIT_SHIFT_PS_TIMER_C_EARLY_8822C 0\n#define BIT_MASK_PS_TIMER_C_EARLY_8822C 0xff\n#define BIT_PS_TIMER_C_EARLY_8822C(x)                                          \\\n\t(((x) & BIT_MASK_PS_TIMER_C_EARLY_8822C)                               \\\n\t << BIT_SHIFT_PS_TIMER_C_EARLY_8822C)\n#define BITS_PS_TIMER_C_EARLY_8822C                                            \\\n\t(BIT_MASK_PS_TIMER_C_EARLY_8822C << BIT_SHIFT_PS_TIMER_C_EARLY_8822C)\n#define BIT_CLEAR_PS_TIMER_C_EARLY_8822C(x)                                    \\\n\t((x) & (~BITS_PS_TIMER_C_EARLY_8822C))\n#define BIT_GET_PS_TIMER_C_EARLY_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8822C) &                           \\\n\t BIT_MASK_PS_TIMER_C_EARLY_8822C)\n#define BIT_SET_PS_TIMER_C_EARLY_8822C(x, v)                                   \\\n\t(BIT_CLEAR_PS_TIMER_C_EARLY_8822C(x) | BIT_PS_TIMER_C_EARLY_8822C(v))\n\n/* 2 REG_CPUMGQ_PARAMETER_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n#define BIT_MAC_STOP_CPUMGQ_8822C BIT(16)\n\n#define BIT_SHIFT_CW_8822C 8\n#define BIT_MASK_CW_8822C 0xff\n#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C)\n#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C)\n#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C))\n#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C)\n#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v))\n\n#define BIT_SHIFT_AIFS_8822C 0\n#define BIT_MASK_AIFS_8822C 0xff\n#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C)\n#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C)\n#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C))\n#define BIT_GET_AIFS_8822C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C)\n#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_TSF_SYNC_ADJ_8822C */\n\n#define BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C 16\n#define BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C 0xffff\n#define BIT_R_P0_TSFT_ADJ_VAL_8822C(x)                                         \\\n\t(((x) & BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C)                              \\\n\t << BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C)\n#define BITS_R_P0_TSFT_ADJ_VAL_8822C                                           \\\n\t(BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C << BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C)\n#define BIT_CLEAR_R_P0_TSFT_ADJ_VAL_8822C(x)                                   \\\n\t((x) & (~BITS_R_P0_TSFT_ADJ_VAL_8822C))\n#define BIT_GET_R_P0_TSFT_ADJ_VAL_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C) &                          \\\n\t BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C)\n#define BIT_SET_R_P0_TSFT_ADJ_VAL_8822C(x, v)                                  \\\n\t(BIT_CLEAR_R_P0_TSFT_ADJ_VAL_8822C(x) | BIT_R_P0_TSFT_ADJ_VAL_8822C(v))\n\n#define BIT_R_X_COMP_Y_OVER_8822C BIT(8)\n\n#define BIT_SHIFT_R_X_SYNC_SEL_8822C 3\n#define BIT_MASK_R_X_SYNC_SEL_8822C 0x7\n#define BIT_R_X_SYNC_SEL_8822C(x)                                              \\\n\t(((x) & BIT_MASK_R_X_SYNC_SEL_8822C) << BIT_SHIFT_R_X_SYNC_SEL_8822C)\n#define BITS_R_X_SYNC_SEL_8822C                                                \\\n\t(BIT_MASK_R_X_SYNC_SEL_8822C << BIT_SHIFT_R_X_SYNC_SEL_8822C)\n#define BIT_CLEAR_R_X_SYNC_SEL_8822C(x) ((x) & (~BITS_R_X_SYNC_SEL_8822C))\n#define BIT_GET_R_X_SYNC_SEL_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_X_SYNC_SEL_8822C) & BIT_MASK_R_X_SYNC_SEL_8822C)\n#define BIT_SET_R_X_SYNC_SEL_8822C(x, v)                                       \\\n\t(BIT_CLEAR_R_X_SYNC_SEL_8822C(x) | BIT_R_X_SYNC_SEL_8822C(v))\n\n#define BIT_SHIFT_R_SYNC_Y_SEL_8822C 0\n#define BIT_MASK_R_SYNC_Y_SEL_8822C 0x7\n#define BIT_R_SYNC_Y_SEL_8822C(x)                                              \\\n\t(((x) & BIT_MASK_R_SYNC_Y_SEL_8822C) << BIT_SHIFT_R_SYNC_Y_SEL_8822C)\n#define BITS_R_SYNC_Y_SEL_8822C                                                \\\n\t(BIT_MASK_R_SYNC_Y_SEL_8822C << BIT_SHIFT_R_SYNC_Y_SEL_8822C)\n#define BIT_CLEAR_R_SYNC_Y_SEL_8822C(x) ((x) & (~BITS_R_SYNC_Y_SEL_8822C))\n#define BIT_GET_R_SYNC_Y_SEL_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_SYNC_Y_SEL_8822C) & BIT_MASK_R_SYNC_Y_SEL_8822C)\n#define BIT_SET_R_SYNC_Y_SEL_8822C(x, v)                                       \\\n\t(BIT_CLEAR_R_SYNC_Y_SEL_8822C(x) | BIT_R_SYNC_Y_SEL_8822C(v))\n\n/* 2 REG_TSF_ADJ_VLAUE_8822C */\n\n#define BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C 16\n#define BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C 0xffff\n#define BIT_R_CLI1_TSFT_ADJ_VAL_8822C(x)                                       \\\n\t(((x) & BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C)                            \\\n\t << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C)\n#define BITS_R_CLI1_TSFT_ADJ_VAL_8822C                                         \\\n\t(BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C                                    \\\n\t << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C)\n#define BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL_8822C(x)                                 \\\n\t((x) & (~BITS_R_CLI1_TSFT_ADJ_VAL_8822C))\n#define BIT_GET_R_CLI1_TSFT_ADJ_VAL_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C) &                        \\\n\t BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C)\n#define BIT_SET_R_CLI1_TSFT_ADJ_VAL_8822C(x, v)                                \\\n\t(BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL_8822C(x) |                              \\\n\t BIT_R_CLI1_TSFT_ADJ_VAL_8822C(v))\n\n#define BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C 0\n#define BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C 0xffff\n#define BIT_R_CLI0_TSFT_ADJ_VAL_8822C(x)                                       \\\n\t(((x) & BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C)                            \\\n\t << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C)\n#define BITS_R_CLI0_TSFT_ADJ_VAL_8822C                                         \\\n\t(BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C                                    \\\n\t << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C)\n#define BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL_8822C(x)                                 \\\n\t((x) & (~BITS_R_CLI0_TSFT_ADJ_VAL_8822C))\n#define BIT_GET_R_CLI0_TSFT_ADJ_VAL_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C) &                        \\\n\t BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C)\n#define BIT_SET_R_CLI0_TSFT_ADJ_VAL_8822C(x, v)                                \\\n\t(BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL_8822C(x) |                              \\\n\t BIT_R_CLI0_TSFT_ADJ_VAL_8822C(v))\n\n/* 2 REG_TSF_ADJ_VLAUE_2_8822C */\n\n#define BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C 16\n#define BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C 0xffff\n#define BIT_R_CLI3_TSFT_ADJ_VAL_8822C(x)                                       \\\n\t(((x) & BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C)                            \\\n\t << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C)\n#define BITS_R_CLI3_TSFT_ADJ_VAL_8822C                                         \\\n\t(BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C                                    \\\n\t << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C)\n#define BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL_8822C(x)                                 \\\n\t((x) & (~BITS_R_CLI3_TSFT_ADJ_VAL_8822C))\n#define BIT_GET_R_CLI3_TSFT_ADJ_VAL_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C) &                        \\\n\t BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C)\n#define BIT_SET_R_CLI3_TSFT_ADJ_VAL_8822C(x, v)                                \\\n\t(BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL_8822C(x) |                              \\\n\t BIT_R_CLI3_TSFT_ADJ_VAL_8822C(v))\n\n#define BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C 0\n#define BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C 0xffff\n#define BIT_R_CLI2_TSFT_ADJ_VAL_8822C(x)                                       \\\n\t(((x) & BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C)                            \\\n\t << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C)\n#define BITS_R_CLI2_TSFT_ADJ_VAL_8822C                                         \\\n\t(BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C                                    \\\n\t << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C)\n#define BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL_8822C(x)                                 \\\n\t((x) & (~BITS_R_CLI2_TSFT_ADJ_VAL_8822C))\n#define BIT_GET_R_CLI2_TSFT_ADJ_VAL_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C) &                        \\\n\t BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C)\n#define BIT_SET_R_CLI2_TSFT_ADJ_VAL_8822C(x, v)                                \\\n\t(BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL_8822C(x) |                              \\\n\t BIT_R_CLI2_TSFT_ADJ_VAL_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_P2PPS_HW_AUTO_PAUSE_CTRL_8822C */\n#define BIT_P2PPS_NOA_STOP_TX_HANG_8822C BIT(31)\n#define BIT_P2PPS_MACID_PAUSE_EN_8822C BIT(11)\n#define BIT_P2PPS__MGQ_PAUSE_8822C BIT(10)\n#define BIT_P2PPS__HIQ_PAUSE_8822C BIT(9)\n#define BIT_P2PPS__BCNQ_PAUSE_8822C BIT(8)\n\n#define BIT_SHIFT_P2PPS_MACID_PAUSE_8822C 0\n#define BIT_MASK_P2PPS_MACID_PAUSE_8822C 0xff\n#define BIT_P2PPS_MACID_PAUSE_8822C(x)                                         \\\n\t(((x) & BIT_MASK_P2PPS_MACID_PAUSE_8822C)                              \\\n\t << BIT_SHIFT_P2PPS_MACID_PAUSE_8822C)\n#define BITS_P2PPS_MACID_PAUSE_8822C                                           \\\n\t(BIT_MASK_P2PPS_MACID_PAUSE_8822C << BIT_SHIFT_P2PPS_MACID_PAUSE_8822C)\n#define BIT_CLEAR_P2PPS_MACID_PAUSE_8822C(x)                                   \\\n\t((x) & (~BITS_P2PPS_MACID_PAUSE_8822C))\n#define BIT_GET_P2PPS_MACID_PAUSE_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_P2PPS_MACID_PAUSE_8822C) &                          \\\n\t BIT_MASK_P2PPS_MACID_PAUSE_8822C)\n#define BIT_SET_P2PPS_MACID_PAUSE_8822C(x, v)                                  \\\n\t(BIT_CLEAR_P2PPS_MACID_PAUSE_8822C(x) | BIT_P2PPS_MACID_PAUSE_8822C(v))\n\n/* 2 REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8822C */\n#define BIT_P2PPS1_NOA_STOP_TX_HANG_8822C BIT(31)\n#define BIT_P2PPS1_MACID_PAUSE_EN_8822C BIT(11)\n#define BIT_P2PPS1__MGQ_PAUSE_8822C BIT(10)\n#define BIT_P2PPS1__HIQ_PAUSE_8822C BIT(9)\n#define BIT_P2PPS1__BCNQ_PAUSE_8822C BIT(8)\n\n#define BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C 0\n#define BIT_MASK_P2PPS1_MACID_PAUSE_8822C 0xff\n#define BIT_P2PPS1_MACID_PAUSE_8822C(x)                                        \\\n\t(((x) & BIT_MASK_P2PPS1_MACID_PAUSE_8822C)                             \\\n\t << BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C)\n#define BITS_P2PPS1_MACID_PAUSE_8822C                                          \\\n\t(BIT_MASK_P2PPS1_MACID_PAUSE_8822C                                     \\\n\t << BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C)\n#define BIT_CLEAR_P2PPS1_MACID_PAUSE_8822C(x)                                  \\\n\t((x) & (~BITS_P2PPS1_MACID_PAUSE_8822C))\n#define BIT_GET_P2PPS1_MACID_PAUSE_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C) &                         \\\n\t BIT_MASK_P2PPS1_MACID_PAUSE_8822C)\n#define BIT_SET_P2PPS1_MACID_PAUSE_8822C(x, v)                                 \\\n\t(BIT_CLEAR_P2PPS1_MACID_PAUSE_8822C(x) |                               \\\n\t BIT_P2PPS1_MACID_PAUSE_8822C(v))\n\n/* 2 REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8822C */\n#define BIT_P2PPS2_NOA_STOP_TX_HANG_8822C BIT(31)\n#define BIT_P2PPS2_MACID_PAUSE_EN_8822C BIT(11)\n#define BIT_P2PPS2__MGQ_PAUSE_8822C BIT(10)\n#define BIT_P2PPS2__HIQ_PAUSE_8822C BIT(9)\n#define BIT_P2PPS2__BCNQ_PAUSE_8822C BIT(8)\n\n#define BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C 0\n#define BIT_MASK_P2PPS2_MACID_PAUSE_8822C 0xff\n#define BIT_P2PPS2_MACID_PAUSE_8822C(x)                                        \\\n\t(((x) & BIT_MASK_P2PPS2_MACID_PAUSE_8822C)                             \\\n\t << BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C)\n#define BITS_P2PPS2_MACID_PAUSE_8822C                                          \\\n\t(BIT_MASK_P2PPS2_MACID_PAUSE_8822C                                     \\\n\t << BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C)\n#define BIT_CLEAR_P2PPS2_MACID_PAUSE_8822C(x)                                  \\\n\t((x) & (~BITS_P2PPS2_MACID_PAUSE_8822C))\n#define BIT_GET_P2PPS2_MACID_PAUSE_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C) &                         \\\n\t BIT_MASK_P2PPS2_MACID_PAUSE_8822C)\n#define BIT_SET_P2PPS2_MACID_PAUSE_8822C(x, v)                                 \\\n\t(BIT_CLEAR_P2PPS2_MACID_PAUSE_8822C(x) |                               \\\n\t BIT_P2PPS2_MACID_PAUSE_8822C(v))\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_SCHEDULER_COUNTER_8822C */\n\n#define BIT_SHIFT__SCHEDULER_COUNTER_8822C 16\n#define BIT_MASK__SCHEDULER_COUNTER_8822C 0xffff\n#define BIT__SCHEDULER_COUNTER_8822C(x)                                        \\\n\t(((x) & BIT_MASK__SCHEDULER_COUNTER_8822C)                             \\\n\t << BIT_SHIFT__SCHEDULER_COUNTER_8822C)\n#define BITS__SCHEDULER_COUNTER_8822C                                          \\\n\t(BIT_MASK__SCHEDULER_COUNTER_8822C                                     \\\n\t << BIT_SHIFT__SCHEDULER_COUNTER_8822C)\n#define BIT_CLEAR__SCHEDULER_COUNTER_8822C(x)                                  \\\n\t((x) & (~BITS__SCHEDULER_COUNTER_8822C))\n#define BIT_GET__SCHEDULER_COUNTER_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT__SCHEDULER_COUNTER_8822C) &                         \\\n\t BIT_MASK__SCHEDULER_COUNTER_8822C)\n#define BIT_SET__SCHEDULER_COUNTER_8822C(x, v)                                 \\\n\t(BIT_CLEAR__SCHEDULER_COUNTER_8822C(x) |                               \\\n\t BIT__SCHEDULER_COUNTER_8822C(v))\n\n#define BIT__SCHEDULER_COUNTER_RST_8822C BIT(8)\n\n#define BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C 0\n#define BIT_MASK_SCHEDULER_COUNTER_SEL_8822C 0xff\n#define BIT_SCHEDULER_COUNTER_SEL_8822C(x)                                     \\\n\t(((x) & BIT_MASK_SCHEDULER_COUNTER_SEL_8822C)                          \\\n\t << BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C)\n#define BITS_SCHEDULER_COUNTER_SEL_8822C                                       \\\n\t(BIT_MASK_SCHEDULER_COUNTER_SEL_8822C                                  \\\n\t << BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C)\n#define BIT_CLEAR_SCHEDULER_COUNTER_SEL_8822C(x)                               \\\n\t((x) & (~BITS_SCHEDULER_COUNTER_SEL_8822C))\n#define BIT_GET_SCHEDULER_COUNTER_SEL_8822C(x)                                 \\\n\t(((x) >> BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C) &                      \\\n\t BIT_MASK_SCHEDULER_COUNTER_SEL_8822C)\n#define BIT_SET_SCHEDULER_COUNTER_SEL_8822C(x, v)                              \\\n\t(BIT_CLEAR_SCHEDULER_COUNTER_SEL_8822C(x) |                            \\\n\t BIT_SCHEDULER_COUNTER_SEL_8822C(v))\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_WMAC_CR_8822C (WMAC CR AND APSD CONTROL REGISTER) */\n#define BIT_IC_MACPHY_M_8822C BIT(0)\n\n/* 2 REG_WMAC_FWPKT_CR_8822C */\n#define BIT_FWEN_8822C BIT(7)\n#define BIT_PHYSTS_PKT_CTRL_8822C BIT(6)\n#define BIT_APPHDR_MIDSRCH_FAIL_8822C BIT(4)\n#define BIT_FWPARSING_EN_8822C BIT(3)\n\n#define BIT_SHIFT_APPEND_MHDR_LEN_8822C 0\n#define BIT_MASK_APPEND_MHDR_LEN_8822C 0x7\n#define BIT_APPEND_MHDR_LEN_8822C(x)                                           \\\n\t(((x) & BIT_MASK_APPEND_MHDR_LEN_8822C)                                \\\n\t << BIT_SHIFT_APPEND_MHDR_LEN_8822C)\n#define BITS_APPEND_MHDR_LEN_8822C                                             \\\n\t(BIT_MASK_APPEND_MHDR_LEN_8822C << BIT_SHIFT_APPEND_MHDR_LEN_8822C)\n#define BIT_CLEAR_APPEND_MHDR_LEN_8822C(x) ((x) & (~BITS_APPEND_MHDR_LEN_8822C))\n#define BIT_GET_APPEND_MHDR_LEN_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8822C) &                            \\\n\t BIT_MASK_APPEND_MHDR_LEN_8822C)\n#define BIT_SET_APPEND_MHDR_LEN_8822C(x, v)                                    \\\n\t(BIT_CLEAR_APPEND_MHDR_LEN_8822C(x) | BIT_APPEND_MHDR_LEN_8822C(v))\n\n/* 2 REG_FW_STS_FILTER_8822C */\n#define BIT_DATA_FW_STS_FILTER_8822C BIT(2)\n#define BIT_CTRL_FW_STS_FILTER_8822C BIT(1)\n#define BIT_MGNT_FW_STS_FILTER_8822C BIT(0)\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_TCR_8822C (TRANSMISSION CONFIGURATION REGISTER) */\n#define BIT_WMAC_EN_RTS_ADDR_8822C BIT(31)\n#define BIT_WMAC_DISABLE_CCK_8822C BIT(30)\n#define BIT_WMAC_RAW_LEN_8822C BIT(29)\n#define BIT_WMAC_NOTX_IN_RXNDP_8822C BIT(28)\n#define BIT_WMAC_EN_EOF_8822C BIT(27)\n#define BIT_WMAC_BF_SEL_8822C BIT(26)\n#define BIT_WMAC_ANTMODE_SEL_8822C BIT(25)\n#define BIT_WMAC_TCRPWRMGT_HWCTL_8822C BIT(24)\n#define BIT_WMAC_SMOOTH_VAL_8822C BIT(23)\n#define BIT_WMAC_EN_SCRAM_INC_8822C BIT(22)\n#define BIT_UNDERFLOWEN_CMPLEN_SEL_8822C BIT(21)\n#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8822C BIT(20)\n#define BIT_WMAC_TCR_EN_20MST_8822C BIT(19)\n#define BIT_WMAC_DIS_SIGTA_8822C BIT(18)\n#define BIT_WMAC_DIS_A2B0_8822C BIT(17)\n#define BIT_WMAC_MSK_SIGBCRC_8822C BIT(16)\n#define BIT_WMAC_TCR_ERRSTEN_3_8822C BIT(15)\n#define BIT_WMAC_TCR_ERRSTEN_2_8822C BIT(14)\n#define BIT_WMAC_TCR_ERRSTEN_1_8822C BIT(13)\n#define BIT_WMAC_TCR_ERRSTEN_0_8822C BIT(12)\n#define BIT_WMAC_TCR_TXSK_PERPKT_8822C BIT(11)\n#define BIT_ICV_8822C BIT(10)\n#define BIT_CFEND_FORMAT_8822C BIT(9)\n#define BIT_CRC_8822C BIT(8)\n#define BIT_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(7)\n#define BIT_PWR_ST_8822C BIT(6)\n#define BIT_WMAC_TCR_UPD_TIMIE_8822C BIT(5)\n#define BIT_WMAC_TCR_UPD_HGQMD_8822C BIT(4)\n#define BIT_VHTSIGA1_TXPS_8822C BIT(3)\n#define BIT_PAD_SEL_8822C BIT(2)\n#define BIT_DIS_GCLK_8822C BIT(1)\n#define BIT_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(0)\n\n/* 2 REG_RCR_8822C (RECEIVE CONFIGURATION REGISTER) */\n#define BIT_APP_FCS_8822C BIT(31)\n#define BIT_APP_MIC_8822C BIT(30)\n#define BIT_APP_ICV_8822C BIT(29)\n#define BIT_APP_PHYSTS_8822C BIT(28)\n#define BIT_APP_BASSN_8822C BIT(27)\n#define BIT_VHT_DACK_8822C BIT(26)\n#define BIT_TCPOFLD_EN_8822C BIT(25)\n#define BIT_ENMBID_8822C BIT(24)\n#define BIT_LSIGEN_8822C BIT(23)\n#define BIT_MFBEN_8822C BIT(22)\n#define BIT_DISCHKPPDLLEN_8822C BIT(21)\n#define BIT_PKTCTL_DLEN_8822C BIT(20)\n#define BIT_DISGCLK_8822C BIT(19)\n#define BIT_TIM_PARSER_EN_8822C BIT(18)\n#define BIT_BC_MD_EN_8822C BIT(17)\n#define BIT_UC_MD_EN_8822C BIT(16)\n#define BIT_RXSK_PERPKT_8822C BIT(15)\n#define BIT_HTC_LOC_CTRL_8822C BIT(14)\n#define BIT_ACK_WITH_CBSSID_DATA_OPTION_8822C BIT(13)\n#define BIT_RPFM_CAM_ENABLE_8822C BIT(12)\n#define BIT_TA_BCN_8822C BIT(11)\n#define BIT_DISDECMYPKT_8822C BIT(10)\n#define BIT_AICV_8822C BIT(9)\n#define BIT_ACRC32_8822C BIT(8)\n#define BIT_CBSSID_BCN_8822C BIT(7)\n#define BIT_CBSSID_DATA_8822C BIT(6)\n#define BIT_APWRMGT_8822C BIT(5)\n#define BIT_ADD3_8822C BIT(4)\n#define BIT_AB_8822C BIT(3)\n#define BIT_AM_8822C BIT(2)\n#define BIT_APM_8822C BIT(1)\n#define BIT_AAP_8822C BIT(0)\n\n/* 2 REG_RX_PKT_LIMIT_8822C (RX PACKET LENGTH LIMIT REGISTER) */\n\n#define BIT_SHIFT_RXPKTLMT_8822C 0\n#define BIT_MASK_RXPKTLMT_8822C 0x3f\n#define BIT_RXPKTLMT_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_RXPKTLMT_8822C) << BIT_SHIFT_RXPKTLMT_8822C)\n#define BITS_RXPKTLMT_8822C                                                    \\\n\t(BIT_MASK_RXPKTLMT_8822C << BIT_SHIFT_RXPKTLMT_8822C)\n#define BIT_CLEAR_RXPKTLMT_8822C(x) ((x) & (~BITS_RXPKTLMT_8822C))\n#define BIT_GET_RXPKTLMT_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_RXPKTLMT_8822C) & BIT_MASK_RXPKTLMT_8822C)\n#define BIT_SET_RXPKTLMT_8822C(x, v)                                           \\\n\t(BIT_CLEAR_RXPKTLMT_8822C(x) | BIT_RXPKTLMT_8822C(v))\n\n/* 2 REG_RX_DLK_TIME_8822C (RX DEADLOCK TIME REGISTER) */\n\n#define BIT_SHIFT_RX_DLK_TIME_8822C 0\n#define BIT_MASK_RX_DLK_TIME_8822C 0xff\n#define BIT_RX_DLK_TIME_8822C(x)                                               \\\n\t(((x) & BIT_MASK_RX_DLK_TIME_8822C) << BIT_SHIFT_RX_DLK_TIME_8822C)\n#define BITS_RX_DLK_TIME_8822C                                                 \\\n\t(BIT_MASK_RX_DLK_TIME_8822C << BIT_SHIFT_RX_DLK_TIME_8822C)\n#define BIT_CLEAR_RX_DLK_TIME_8822C(x) ((x) & (~BITS_RX_DLK_TIME_8822C))\n#define BIT_GET_RX_DLK_TIME_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RX_DLK_TIME_8822C) & BIT_MASK_RX_DLK_TIME_8822C)\n#define BIT_SET_RX_DLK_TIME_8822C(x, v)                                        \\\n\t(BIT_CLEAR_RX_DLK_TIME_8822C(x) | BIT_RX_DLK_TIME_8822C(v))\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RX_DRVINFO_SZ_8822C (RX DRIVER INFO SIZE REGISTER) */\n#define BIT_PHYSTS_PER_PKT_MODE_8822C BIT(7)\n\n#define BIT_SHIFT_DRVINFO_SZ_V1_8822C 0\n#define BIT_MASK_DRVINFO_SZ_V1_8822C 0xf\n#define BIT_DRVINFO_SZ_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_DRVINFO_SZ_V1_8822C) << BIT_SHIFT_DRVINFO_SZ_V1_8822C)\n#define BITS_DRVINFO_SZ_V1_8822C                                               \\\n\t(BIT_MASK_DRVINFO_SZ_V1_8822C << BIT_SHIFT_DRVINFO_SZ_V1_8822C)\n#define BIT_CLEAR_DRVINFO_SZ_V1_8822C(x) ((x) & (~BITS_DRVINFO_SZ_V1_8822C))\n#define BIT_GET_DRVINFO_SZ_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8822C) & BIT_MASK_DRVINFO_SZ_V1_8822C)\n#define BIT_SET_DRVINFO_SZ_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_DRVINFO_SZ_V1_8822C(x) | BIT_DRVINFO_SZ_V1_8822C(v))\n\n/* 2 REG_MACID_8822C\t(MAC ID REGISTER) */\n\n#define BIT_SHIFT_MACID_V1_8822C 0\n#define BIT_MASK_MACID_V1_8822C 0xffffffffL\n#define BIT_MACID_V1_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_MACID_V1_8822C) << BIT_SHIFT_MACID_V1_8822C)\n#define BITS_MACID_V1_8822C                                                    \\\n\t(BIT_MASK_MACID_V1_8822C << BIT_SHIFT_MACID_V1_8822C)\n#define BIT_CLEAR_MACID_V1_8822C(x) ((x) & (~BITS_MACID_V1_8822C))\n#define BIT_GET_MACID_V1_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_MACID_V1_8822C) & BIT_MASK_MACID_V1_8822C)\n#define BIT_SET_MACID_V1_8822C(x, v)                                           \\\n\t(BIT_CLEAR_MACID_V1_8822C(x) | BIT_MACID_V1_8822C(v))\n\n/* 2 REG_MACID_H_8822C\t(MAC ID REGISTER) */\n\n#define BIT_SHIFT_MACID_H_V1_8822C 0\n#define BIT_MASK_MACID_H_V1_8822C 0xffff\n#define BIT_MACID_H_V1_8822C(x)                                                \\\n\t(((x) & BIT_MASK_MACID_H_V1_8822C) << BIT_SHIFT_MACID_H_V1_8822C)\n#define BITS_MACID_H_V1_8822C                                                  \\\n\t(BIT_MASK_MACID_H_V1_8822C << BIT_SHIFT_MACID_H_V1_8822C)\n#define BIT_CLEAR_MACID_H_V1_8822C(x) ((x) & (~BITS_MACID_H_V1_8822C))\n#define BIT_GET_MACID_H_V1_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_MACID_H_V1_8822C) & BIT_MASK_MACID_H_V1_8822C)\n#define BIT_SET_MACID_H_V1_8822C(x, v)                                         \\\n\t(BIT_CLEAR_MACID_H_V1_8822C(x) | BIT_MACID_H_V1_8822C(v))\n\n/* 2 REG_BSSID_8822C (BSSID REGISTER) */\n\n#define BIT_SHIFT_BSSID_V1_8822C 0\n#define BIT_MASK_BSSID_V1_8822C 0xffffffffL\n#define BIT_BSSID_V1_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_BSSID_V1_8822C) << BIT_SHIFT_BSSID_V1_8822C)\n#define BITS_BSSID_V1_8822C                                                    \\\n\t(BIT_MASK_BSSID_V1_8822C << BIT_SHIFT_BSSID_V1_8822C)\n#define BIT_CLEAR_BSSID_V1_8822C(x) ((x) & (~BITS_BSSID_V1_8822C))\n#define BIT_GET_BSSID_V1_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_BSSID_V1_8822C) & BIT_MASK_BSSID_V1_8822C)\n#define BIT_SET_BSSID_V1_8822C(x, v)                                           \\\n\t(BIT_CLEAR_BSSID_V1_8822C(x) | BIT_BSSID_V1_8822C(v))\n\n/* 2 REG_BSSID_H_8822C\t(BSSID REGISTER) */\n\n/* 2 REG_NOT_VALID_8822C */\n\n#define BIT_SHIFT_BSSID_H_V1_8822C 0\n#define BIT_MASK_BSSID_H_V1_8822C 0xffff\n#define BIT_BSSID_H_V1_8822C(x)                                                \\\n\t(((x) & BIT_MASK_BSSID_H_V1_8822C) << BIT_SHIFT_BSSID_H_V1_8822C)\n#define BITS_BSSID_H_V1_8822C                                                  \\\n\t(BIT_MASK_BSSID_H_V1_8822C << BIT_SHIFT_BSSID_H_V1_8822C)\n#define BIT_CLEAR_BSSID_H_V1_8822C(x) ((x) & (~BITS_BSSID_H_V1_8822C))\n#define BIT_GET_BSSID_H_V1_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BSSID_H_V1_8822C) & BIT_MASK_BSSID_H_V1_8822C)\n#define BIT_SET_BSSID_H_V1_8822C(x, v)                                         \\\n\t(BIT_CLEAR_BSSID_H_V1_8822C(x) | BIT_BSSID_H_V1_8822C(v))\n\n/* 2 REG_MAR_8822C (MULTICAST ADDRESS REGISTER) */\n\n#define BIT_SHIFT_MAR_V1_8822C 0\n#define BIT_MASK_MAR_V1_8822C 0xffffffffL\n#define BIT_MAR_V1_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_MAR_V1_8822C) << BIT_SHIFT_MAR_V1_8822C)\n#define BITS_MAR_V1_8822C (BIT_MASK_MAR_V1_8822C << BIT_SHIFT_MAR_V1_8822C)\n#define BIT_CLEAR_MAR_V1_8822C(x) ((x) & (~BITS_MAR_V1_8822C))\n#define BIT_GET_MAR_V1_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_MAR_V1_8822C) & BIT_MASK_MAR_V1_8822C)\n#define BIT_SET_MAR_V1_8822C(x, v)                                             \\\n\t(BIT_CLEAR_MAR_V1_8822C(x) | BIT_MAR_V1_8822C(v))\n\n/* 2 REG_MAR_H_8822C (MULTICAST ADDRESS REGISTER) */\n\n#define BIT_SHIFT_MAR_H_V1_8822C 0\n#define BIT_MASK_MAR_H_V1_8822C 0xffffffffL\n#define BIT_MAR_H_V1_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_MAR_H_V1_8822C) << BIT_SHIFT_MAR_H_V1_8822C)\n#define BITS_MAR_H_V1_8822C                                                    \\\n\t(BIT_MASK_MAR_H_V1_8822C << BIT_SHIFT_MAR_H_V1_8822C)\n#define BIT_CLEAR_MAR_H_V1_8822C(x) ((x) & (~BITS_MAR_H_V1_8822C))\n#define BIT_GET_MAR_H_V1_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_MAR_H_V1_8822C) & BIT_MASK_MAR_H_V1_8822C)\n#define BIT_SET_MAR_H_V1_8822C(x, v)                                           \\\n\t(BIT_CLEAR_MAR_H_V1_8822C(x) | BIT_MAR_H_V1_8822C(v))\n\n/* 2 REG_MBIDCAMCFG_1_8822C (MBSSID CAM CONFIGURATION REGISTER) */\n\n#define BIT_SHIFT_MBIDCAM_RWDATA_L_8822C 0\n#define BIT_MASK_MBIDCAM_RWDATA_L_8822C 0xffffffffL\n#define BIT_MBIDCAM_RWDATA_L_8822C(x)                                          \\\n\t(((x) & BIT_MASK_MBIDCAM_RWDATA_L_8822C)                               \\\n\t << BIT_SHIFT_MBIDCAM_RWDATA_L_8822C)\n#define BITS_MBIDCAM_RWDATA_L_8822C                                            \\\n\t(BIT_MASK_MBIDCAM_RWDATA_L_8822C << BIT_SHIFT_MBIDCAM_RWDATA_L_8822C)\n#define BIT_CLEAR_MBIDCAM_RWDATA_L_8822C(x)                                    \\\n\t((x) & (~BITS_MBIDCAM_RWDATA_L_8822C))\n#define BIT_GET_MBIDCAM_RWDATA_L_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8822C) &                           \\\n\t BIT_MASK_MBIDCAM_RWDATA_L_8822C)\n#define BIT_SET_MBIDCAM_RWDATA_L_8822C(x, v)                                   \\\n\t(BIT_CLEAR_MBIDCAM_RWDATA_L_8822C(x) | BIT_MBIDCAM_RWDATA_L_8822C(v))\n\n/* 2 REG_MBIDCAMCFG_2_8822C (MBSSID CAM CONFIGURATION REGISTER) */\n#define BIT_MBIDCAM_POLL_8822C BIT(31)\n#define BIT_MBIDCAM_WT_EN_8822C BIT(30)\n\n#define BIT_SHIFT_MBIDCAM_ADDR_V1_8822C 24\n#define BIT_MASK_MBIDCAM_ADDR_V1_8822C 0x3f\n#define BIT_MBIDCAM_ADDR_V1_8822C(x)                                           \\\n\t(((x) & BIT_MASK_MBIDCAM_ADDR_V1_8822C)                                \\\n\t << BIT_SHIFT_MBIDCAM_ADDR_V1_8822C)\n#define BITS_MBIDCAM_ADDR_V1_8822C                                             \\\n\t(BIT_MASK_MBIDCAM_ADDR_V1_8822C << BIT_SHIFT_MBIDCAM_ADDR_V1_8822C)\n#define BIT_CLEAR_MBIDCAM_ADDR_V1_8822C(x) ((x) & (~BITS_MBIDCAM_ADDR_V1_8822C))\n#define BIT_GET_MBIDCAM_ADDR_V1_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_MBIDCAM_ADDR_V1_8822C) &                            \\\n\t BIT_MASK_MBIDCAM_ADDR_V1_8822C)\n#define BIT_SET_MBIDCAM_ADDR_V1_8822C(x, v)                                    \\\n\t(BIT_CLEAR_MBIDCAM_ADDR_V1_8822C(x) | BIT_MBIDCAM_ADDR_V1_8822C(v))\n\n#define BIT_MBIDCAM_VALID_8822C BIT(23)\n#define BIT_LSIC_TXOP_EN_8822C BIT(17)\n#define BIT_CTS_EN_8822C BIT(16)\n\n#define BIT_SHIFT_MBIDCAM_RWDATA_H_8822C 0\n#define BIT_MASK_MBIDCAM_RWDATA_H_8822C 0xffff\n#define BIT_MBIDCAM_RWDATA_H_8822C(x)                                          \\\n\t(((x) & BIT_MASK_MBIDCAM_RWDATA_H_8822C)                               \\\n\t << BIT_SHIFT_MBIDCAM_RWDATA_H_8822C)\n#define BITS_MBIDCAM_RWDATA_H_8822C                                            \\\n\t(BIT_MASK_MBIDCAM_RWDATA_H_8822C << BIT_SHIFT_MBIDCAM_RWDATA_H_8822C)\n#define BIT_CLEAR_MBIDCAM_RWDATA_H_8822C(x)                                    \\\n\t((x) & (~BITS_MBIDCAM_RWDATA_H_8822C))\n#define BIT_GET_MBIDCAM_RWDATA_H_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8822C) &                           \\\n\t BIT_MASK_MBIDCAM_RWDATA_H_8822C)\n#define BIT_SET_MBIDCAM_RWDATA_H_8822C(x, v)                                   \\\n\t(BIT_CLEAR_MBIDCAM_RWDATA_H_8822C(x) | BIT_MBIDCAM_RWDATA_H_8822C(v))\n\n/* 2 REG_WMAC_TCR_TSFT_OFS_8822C */\n\n#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C 0\n#define BIT_MASK_WMAC_TCR_TSFT_OFS_8822C 0xffff\n#define BIT_WMAC_TCR_TSFT_OFS_8822C(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822C)                              \\\n\t << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C)\n#define BITS_WMAC_TCR_TSFT_OFS_8822C                                           \\\n\t(BIT_MASK_WMAC_TCR_TSFT_OFS_8822C << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C)\n#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822C(x)                                   \\\n\t((x) & (~BITS_WMAC_TCR_TSFT_OFS_8822C))\n#define BIT_GET_WMAC_TCR_TSFT_OFS_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C) &                          \\\n\t BIT_MASK_WMAC_TCR_TSFT_OFS_8822C)\n#define BIT_SET_WMAC_TCR_TSFT_OFS_8822C(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822C(x) | BIT_WMAC_TCR_TSFT_OFS_8822C(v))\n\n/* 2 REG_UDF_THSD_8822C */\n#define BIT_UDF_THSD_V1_8822C BIT(7)\n\n#define BIT_SHIFT_UDF_THSD_VALUE_8822C 0\n#define BIT_MASK_UDF_THSD_VALUE_8822C 0x7f\n#define BIT_UDF_THSD_VALUE_8822C(x)                                            \\\n\t(((x) & BIT_MASK_UDF_THSD_VALUE_8822C)                                 \\\n\t << BIT_SHIFT_UDF_THSD_VALUE_8822C)\n#define BITS_UDF_THSD_VALUE_8822C                                              \\\n\t(BIT_MASK_UDF_THSD_VALUE_8822C << BIT_SHIFT_UDF_THSD_VALUE_8822C)\n#define BIT_CLEAR_UDF_THSD_VALUE_8822C(x) ((x) & (~BITS_UDF_THSD_VALUE_8822C))\n#define BIT_GET_UDF_THSD_VALUE_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_UDF_THSD_VALUE_8822C) &                             \\\n\t BIT_MASK_UDF_THSD_VALUE_8822C)\n#define BIT_SET_UDF_THSD_VALUE_8822C(x, v)                                     \\\n\t(BIT_CLEAR_UDF_THSD_VALUE_8822C(x) | BIT_UDF_THSD_VALUE_8822C(v))\n\n/* 2 REG_ZLD_NUM_8822C */\n\n#define BIT_SHIFT_ZLD_NUM_8822C 0\n#define BIT_MASK_ZLD_NUM_8822C 0xff\n#define BIT_ZLD_NUM_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_ZLD_NUM_8822C) << BIT_SHIFT_ZLD_NUM_8822C)\n#define BITS_ZLD_NUM_8822C (BIT_MASK_ZLD_NUM_8822C << BIT_SHIFT_ZLD_NUM_8822C)\n#define BIT_CLEAR_ZLD_NUM_8822C(x) ((x) & (~BITS_ZLD_NUM_8822C))\n#define BIT_GET_ZLD_NUM_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_ZLD_NUM_8822C) & BIT_MASK_ZLD_NUM_8822C)\n#define BIT_SET_ZLD_NUM_8822C(x, v)                                            \\\n\t(BIT_CLEAR_ZLD_NUM_8822C(x) | BIT_ZLD_NUM_8822C(v))\n\n/* 2 REG_STMP_THSD_8822C */\n\n#define BIT_SHIFT_STMP_THSD_8822C 0\n#define BIT_MASK_STMP_THSD_8822C 0xff\n#define BIT_STMP_THSD_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_STMP_THSD_8822C) << BIT_SHIFT_STMP_THSD_8822C)\n#define BITS_STMP_THSD_8822C                                                   \\\n\t(BIT_MASK_STMP_THSD_8822C << BIT_SHIFT_STMP_THSD_8822C)\n#define BIT_CLEAR_STMP_THSD_8822C(x) ((x) & (~BITS_STMP_THSD_8822C))\n#define BIT_GET_STMP_THSD_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_STMP_THSD_8822C) & BIT_MASK_STMP_THSD_8822C)\n#define BIT_SET_STMP_THSD_8822C(x, v)                                          \\\n\t(BIT_CLEAR_STMP_THSD_8822C(x) | BIT_STMP_THSD_8822C(v))\n\n/* 2 REG_WMAC_TXTIMEOUT_8822C */\n\n#define BIT_SHIFT_WMAC_TXTIMEOUT_8822C 0\n#define BIT_MASK_WMAC_TXTIMEOUT_8822C 0xff\n#define BIT_WMAC_TXTIMEOUT_8822C(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_TXTIMEOUT_8822C)                                 \\\n\t << BIT_SHIFT_WMAC_TXTIMEOUT_8822C)\n#define BITS_WMAC_TXTIMEOUT_8822C                                              \\\n\t(BIT_MASK_WMAC_TXTIMEOUT_8822C << BIT_SHIFT_WMAC_TXTIMEOUT_8822C)\n#define BIT_CLEAR_WMAC_TXTIMEOUT_8822C(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8822C))\n#define BIT_GET_WMAC_TXTIMEOUT_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8822C) &                             \\\n\t BIT_MASK_WMAC_TXTIMEOUT_8822C)\n#define BIT_SET_WMAC_TXTIMEOUT_8822C(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_TXTIMEOUT_8822C(x) | BIT_WMAC_TXTIMEOUT_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_USTIME_EDCA_8822C (US TIME TUNING FOR EDCA REGISTER) */\n\n#define BIT_SHIFT_USTIME_EDCA_8822C 0\n#define BIT_MASK_USTIME_EDCA_8822C 0xff\n#define BIT_USTIME_EDCA_8822C(x)                                               \\\n\t(((x) & BIT_MASK_USTIME_EDCA_8822C) << BIT_SHIFT_USTIME_EDCA_8822C)\n#define BITS_USTIME_EDCA_8822C                                                 \\\n\t(BIT_MASK_USTIME_EDCA_8822C << BIT_SHIFT_USTIME_EDCA_8822C)\n#define BIT_CLEAR_USTIME_EDCA_8822C(x) ((x) & (~BITS_USTIME_EDCA_8822C))\n#define BIT_GET_USTIME_EDCA_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_USTIME_EDCA_8822C) & BIT_MASK_USTIME_EDCA_8822C)\n#define BIT_SET_USTIME_EDCA_8822C(x, v)                                        \\\n\t(BIT_CLEAR_USTIME_EDCA_8822C(x) | BIT_USTIME_EDCA_8822C(v))\n\n/* 2 REG_ACKTO_CCK_8822C (ACK TIMEOUT REGISTER FOR CCK RATE) */\n\n#define BIT_SHIFT_ACKTO_CCK_8822C 0\n#define BIT_MASK_ACKTO_CCK_8822C 0xff\n#define BIT_ACKTO_CCK_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_ACKTO_CCK_8822C) << BIT_SHIFT_ACKTO_CCK_8822C)\n#define BITS_ACKTO_CCK_8822C                                                   \\\n\t(BIT_MASK_ACKTO_CCK_8822C << BIT_SHIFT_ACKTO_CCK_8822C)\n#define BIT_CLEAR_ACKTO_CCK_8822C(x) ((x) & (~BITS_ACKTO_CCK_8822C))\n#define BIT_GET_ACKTO_CCK_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_ACKTO_CCK_8822C) & BIT_MASK_ACKTO_CCK_8822C)\n#define BIT_SET_ACKTO_CCK_8822C(x, v)                                          \\\n\t(BIT_CLEAR_ACKTO_CCK_8822C(x) | BIT_ACKTO_CCK_8822C(v))\n\n/* 2 REG_MAC_SPEC_SIFS_8822C (SPECIFICATION SIFS REGISTER) */\n\n#define BIT_SHIFT_SPEC_SIFS_OFDM_8822C 8\n#define BIT_MASK_SPEC_SIFS_OFDM_8822C 0xff\n#define BIT_SPEC_SIFS_OFDM_8822C(x)                                            \\\n\t(((x) & BIT_MASK_SPEC_SIFS_OFDM_8822C)                                 \\\n\t << BIT_SHIFT_SPEC_SIFS_OFDM_8822C)\n#define BITS_SPEC_SIFS_OFDM_8822C                                              \\\n\t(BIT_MASK_SPEC_SIFS_OFDM_8822C << BIT_SHIFT_SPEC_SIFS_OFDM_8822C)\n#define BIT_CLEAR_SPEC_SIFS_OFDM_8822C(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8822C))\n#define BIT_GET_SPEC_SIFS_OFDM_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8822C) &                             \\\n\t BIT_MASK_SPEC_SIFS_OFDM_8822C)\n#define BIT_SET_SPEC_SIFS_OFDM_8822C(x, v)                                     \\\n\t(BIT_CLEAR_SPEC_SIFS_OFDM_8822C(x) | BIT_SPEC_SIFS_OFDM_8822C(v))\n\n#define BIT_SHIFT_SPEC_SIFS_CCK_8822C 0\n#define BIT_MASK_SPEC_SIFS_CCK_8822C 0xff\n#define BIT_SPEC_SIFS_CCK_8822C(x)                                             \\\n\t(((x) & BIT_MASK_SPEC_SIFS_CCK_8822C) << BIT_SHIFT_SPEC_SIFS_CCK_8822C)\n#define BITS_SPEC_SIFS_CCK_8822C                                               \\\n\t(BIT_MASK_SPEC_SIFS_CCK_8822C << BIT_SHIFT_SPEC_SIFS_CCK_8822C)\n#define BIT_CLEAR_SPEC_SIFS_CCK_8822C(x) ((x) & (~BITS_SPEC_SIFS_CCK_8822C))\n#define BIT_GET_SPEC_SIFS_CCK_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8822C) & BIT_MASK_SPEC_SIFS_CCK_8822C)\n#define BIT_SET_SPEC_SIFS_CCK_8822C(x, v)                                      \\\n\t(BIT_CLEAR_SPEC_SIFS_CCK_8822C(x) | BIT_SPEC_SIFS_CCK_8822C(v))\n\n/* 2 REG_RESP_SIFS_CCK_8822C (RESPONSE SIFS FOR CCK REGISTER) */\n\n#define BIT_SHIFT_SIFS_R2T_CCK_8822C 8\n#define BIT_MASK_SIFS_R2T_CCK_8822C 0xff\n#define BIT_SIFS_R2T_CCK_8822C(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_R2T_CCK_8822C) << BIT_SHIFT_SIFS_R2T_CCK_8822C)\n#define BITS_SIFS_R2T_CCK_8822C                                                \\\n\t(BIT_MASK_SIFS_R2T_CCK_8822C << BIT_SHIFT_SIFS_R2T_CCK_8822C)\n#define BIT_CLEAR_SIFS_R2T_CCK_8822C(x) ((x) & (~BITS_SIFS_R2T_CCK_8822C))\n#define BIT_GET_SIFS_R2T_CCK_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_R2T_CCK_8822C) & BIT_MASK_SIFS_R2T_CCK_8822C)\n#define BIT_SET_SIFS_R2T_CCK_8822C(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_R2T_CCK_8822C(x) | BIT_SIFS_R2T_CCK_8822C(v))\n\n#define BIT_SHIFT_SIFS_T2T_CCK_8822C 0\n#define BIT_MASK_SIFS_T2T_CCK_8822C 0xff\n#define BIT_SIFS_T2T_CCK_8822C(x)                                              \\\n\t(((x) & BIT_MASK_SIFS_T2T_CCK_8822C) << BIT_SHIFT_SIFS_T2T_CCK_8822C)\n#define BITS_SIFS_T2T_CCK_8822C                                                \\\n\t(BIT_MASK_SIFS_T2T_CCK_8822C << BIT_SHIFT_SIFS_T2T_CCK_8822C)\n#define BIT_CLEAR_SIFS_T2T_CCK_8822C(x) ((x) & (~BITS_SIFS_T2T_CCK_8822C))\n#define BIT_GET_SIFS_T2T_CCK_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_SIFS_T2T_CCK_8822C) & BIT_MASK_SIFS_T2T_CCK_8822C)\n#define BIT_SET_SIFS_T2T_CCK_8822C(x, v)                                       \\\n\t(BIT_CLEAR_SIFS_T2T_CCK_8822C(x) | BIT_SIFS_T2T_CCK_8822C(v))\n\n/* 2 REG_RESP_SIFS_OFDM_8822C (RESPONSE SIFS FOR OFDM REGISTER) */\n\n#define BIT_SHIFT_SIFS_R2T_OFDM_8822C 8\n#define BIT_MASK_SIFS_R2T_OFDM_8822C 0xff\n#define BIT_SIFS_R2T_OFDM_8822C(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_R2T_OFDM_8822C) << BIT_SHIFT_SIFS_R2T_OFDM_8822C)\n#define BITS_SIFS_R2T_OFDM_8822C                                               \\\n\t(BIT_MASK_SIFS_R2T_OFDM_8822C << BIT_SHIFT_SIFS_R2T_OFDM_8822C)\n#define BIT_CLEAR_SIFS_R2T_OFDM_8822C(x) ((x) & (~BITS_SIFS_R2T_OFDM_8822C))\n#define BIT_GET_SIFS_R2T_OFDM_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8822C) & BIT_MASK_SIFS_R2T_OFDM_8822C)\n#define BIT_SET_SIFS_R2T_OFDM_8822C(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_R2T_OFDM_8822C(x) | BIT_SIFS_R2T_OFDM_8822C(v))\n\n#define BIT_SHIFT_SIFS_T2T_OFDM_8822C 0\n#define BIT_MASK_SIFS_T2T_OFDM_8822C 0xff\n#define BIT_SIFS_T2T_OFDM_8822C(x)                                             \\\n\t(((x) & BIT_MASK_SIFS_T2T_OFDM_8822C) << BIT_SHIFT_SIFS_T2T_OFDM_8822C)\n#define BITS_SIFS_T2T_OFDM_8822C                                               \\\n\t(BIT_MASK_SIFS_T2T_OFDM_8822C << BIT_SHIFT_SIFS_T2T_OFDM_8822C)\n#define BIT_CLEAR_SIFS_T2T_OFDM_8822C(x) ((x) & (~BITS_SIFS_T2T_OFDM_8822C))\n#define BIT_GET_SIFS_T2T_OFDM_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8822C) & BIT_MASK_SIFS_T2T_OFDM_8822C)\n#define BIT_SET_SIFS_T2T_OFDM_8822C(x, v)                                      \\\n\t(BIT_CLEAR_SIFS_T2T_OFDM_8822C(x) | BIT_SIFS_T2T_OFDM_8822C(v))\n\n/* 2 REG_ACKTO_8822C (ACK TIMEOUT REGISTER) */\n\n#define BIT_SHIFT_ACKTO_8822C 0\n#define BIT_MASK_ACKTO_8822C 0xff\n#define BIT_ACKTO_8822C(x)                                                     \\\n\t(((x) & BIT_MASK_ACKTO_8822C) << BIT_SHIFT_ACKTO_8822C)\n#define BITS_ACKTO_8822C (BIT_MASK_ACKTO_8822C << BIT_SHIFT_ACKTO_8822C)\n#define BIT_CLEAR_ACKTO_8822C(x) ((x) & (~BITS_ACKTO_8822C))\n#define BIT_GET_ACKTO_8822C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_ACKTO_8822C) & BIT_MASK_ACKTO_8822C)\n#define BIT_SET_ACKTO_8822C(x, v)                                              \\\n\t(BIT_CLEAR_ACKTO_8822C(x) | BIT_ACKTO_8822C(v))\n\n/* 2 REG_CTS2TO_8822C (CTS2 TIMEOUT REGISTER) */\n\n#define BIT_SHIFT_CTS2TO_8822C 0\n#define BIT_MASK_CTS2TO_8822C 0xff\n#define BIT_CTS2TO_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_CTS2TO_8822C) << BIT_SHIFT_CTS2TO_8822C)\n#define BITS_CTS2TO_8822C (BIT_MASK_CTS2TO_8822C << BIT_SHIFT_CTS2TO_8822C)\n#define BIT_CLEAR_CTS2TO_8822C(x) ((x) & (~BITS_CTS2TO_8822C))\n#define BIT_GET_CTS2TO_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_CTS2TO_8822C) & BIT_MASK_CTS2TO_8822C)\n#define BIT_SET_CTS2TO_8822C(x, v)                                             \\\n\t(BIT_CLEAR_CTS2TO_8822C(x) | BIT_CTS2TO_8822C(v))\n\n/* 2 REG_EIFS_8822C (EIFS REGISTER) */\n\n#define BIT_SHIFT_EIFS_8822C 0\n#define BIT_MASK_EIFS_8822C 0xffff\n#define BIT_EIFS_8822C(x) (((x) & BIT_MASK_EIFS_8822C) << BIT_SHIFT_EIFS_8822C)\n#define BITS_EIFS_8822C (BIT_MASK_EIFS_8822C << BIT_SHIFT_EIFS_8822C)\n#define BIT_CLEAR_EIFS_8822C(x) ((x) & (~BITS_EIFS_8822C))\n#define BIT_GET_EIFS_8822C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_EIFS_8822C) & BIT_MASK_EIFS_8822C)\n#define BIT_SET_EIFS_8822C(x, v) (BIT_CLEAR_EIFS_8822C(x) | BIT_EIFS_8822C(v))\n\n/* 2 REG_RPFM_MAP0_8822C */\n#define BIT_MGT_RPFM15EN_8822C BIT(15)\n#define BIT_MGT_RPFM14EN_8822C BIT(14)\n#define BIT_MGT_RPFM13EN_8822C BIT(13)\n#define BIT_MGT_RPFM12EN_8822C BIT(12)\n#define BIT_MGT_RPFM11EN_8822C BIT(11)\n#define BIT_MGT_RPFM10EN_8822C BIT(10)\n#define BIT_MGT_RPFM9EN_8822C BIT(9)\n#define BIT_MGT_RPFM8EN_8822C BIT(8)\n#define BIT_MGT_RPFM7EN_8822C BIT(7)\n#define BIT_MGT_RPFM6EN_8822C BIT(6)\n#define BIT_MGT_RPFM5EN_8822C BIT(5)\n#define BIT_MGT_RPFM4EN_8822C BIT(4)\n#define BIT_MGT_RPFM3EN_8822C BIT(3)\n#define BIT_MGT_RPFM2EN_8822C BIT(2)\n#define BIT_MGT_RPFM1EN_8822C BIT(1)\n#define BIT_MGT_RPFM0EN_8822C BIT(0)\n\n/* 2 REG_RPFM_MAP1_V1_8822C */\n#define BIT_DATA_RPFM15EN_8822C BIT(15)\n#define BIT_DATA_RPFM14EN_8822C BIT(14)\n#define BIT_DATA_RPFM13EN_8822C BIT(13)\n#define BIT_DATA_RPFM12EN_8822C BIT(12)\n#define BIT_DATA_RPFM11EN_8822C BIT(11)\n#define BIT_DATA_RPFM10EN_8822C BIT(10)\n#define BIT_DATA_RPFM9EN_8822C BIT(9)\n#define BIT_DATA_RPFM8EN_8822C BIT(8)\n#define BIT_DATA_RPFM7EN_8822C BIT(7)\n#define BIT_DATA_RPFM6EN_8822C BIT(6)\n#define BIT_DATA_RPFM5EN_8822C BIT(5)\n#define BIT_DATA_RPFM4EN_8822C BIT(4)\n#define BIT_DATA_RPFM3EN_8822C BIT(3)\n#define BIT_DATA_RPFM2EN_8822C BIT(2)\n#define BIT_DATA_RPFM1EN_8822C BIT(1)\n#define BIT_DATA_RPFM0EN_8822C BIT(0)\n\n/* 2 REG_RPFM_CAM_CMD_8822C (RX PAYLOAD FRAME MASK CAM COMMAND REGISTER) */\n#define BIT_RPFM_CAM_POLLING_8822C BIT(31)\n#define BIT_RPFM_CAM_CLR_8822C BIT(30)\n#define BIT_RPFM_CAM_WE_8822C BIT(16)\n\n#define BIT_SHIFT_RPFM_CAM_ADDR_8822C 0\n#define BIT_MASK_RPFM_CAM_ADDR_8822C 0x7f\n#define BIT_RPFM_CAM_ADDR_8822C(x)                                             \\\n\t(((x) & BIT_MASK_RPFM_CAM_ADDR_8822C) << BIT_SHIFT_RPFM_CAM_ADDR_8822C)\n#define BITS_RPFM_CAM_ADDR_8822C                                               \\\n\t(BIT_MASK_RPFM_CAM_ADDR_8822C << BIT_SHIFT_RPFM_CAM_ADDR_8822C)\n#define BIT_CLEAR_RPFM_CAM_ADDR_8822C(x) ((x) & (~BITS_RPFM_CAM_ADDR_8822C))\n#define BIT_GET_RPFM_CAM_ADDR_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8822C) & BIT_MASK_RPFM_CAM_ADDR_8822C)\n#define BIT_SET_RPFM_CAM_ADDR_8822C(x, v)                                      \\\n\t(BIT_CLEAR_RPFM_CAM_ADDR_8822C(x) | BIT_RPFM_CAM_ADDR_8822C(v))\n\n/* 2 REG_RPFM_CAM_RWD_8822C (ACK TIMEOUT REGISTER) */\n\n#define BIT_SHIFT_RPFM_CAM_RWD_8822C 0\n#define BIT_MASK_RPFM_CAM_RWD_8822C 0xffffffffL\n#define BIT_RPFM_CAM_RWD_8822C(x)                                              \\\n\t(((x) & BIT_MASK_RPFM_CAM_RWD_8822C) << BIT_SHIFT_RPFM_CAM_RWD_8822C)\n#define BITS_RPFM_CAM_RWD_8822C                                                \\\n\t(BIT_MASK_RPFM_CAM_RWD_8822C << BIT_SHIFT_RPFM_CAM_RWD_8822C)\n#define BIT_CLEAR_RPFM_CAM_RWD_8822C(x) ((x) & (~BITS_RPFM_CAM_RWD_8822C))\n#define BIT_GET_RPFM_CAM_RWD_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RPFM_CAM_RWD_8822C) & BIT_MASK_RPFM_CAM_RWD_8822C)\n#define BIT_SET_RPFM_CAM_RWD_8822C(x, v)                                       \\\n\t(BIT_CLEAR_RPFM_CAM_RWD_8822C(x) | BIT_RPFM_CAM_RWD_8822C(v))\n\n/* 2 REG_NAV_CTRL_8822C (NAV CONTROL REGISTER) */\n\n#define BIT_SHIFT_NAV_UPPER_8822C 16\n#define BIT_MASK_NAV_UPPER_8822C 0xff\n#define BIT_NAV_UPPER_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_NAV_UPPER_8822C) << BIT_SHIFT_NAV_UPPER_8822C)\n#define BITS_NAV_UPPER_8822C                                                   \\\n\t(BIT_MASK_NAV_UPPER_8822C << BIT_SHIFT_NAV_UPPER_8822C)\n#define BIT_CLEAR_NAV_UPPER_8822C(x) ((x) & (~BITS_NAV_UPPER_8822C))\n#define BIT_GET_NAV_UPPER_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_NAV_UPPER_8822C) & BIT_MASK_NAV_UPPER_8822C)\n#define BIT_SET_NAV_UPPER_8822C(x, v)                                          \\\n\t(BIT_CLEAR_NAV_UPPER_8822C(x) | BIT_NAV_UPPER_8822C(v))\n\n#define BIT_SHIFT_RXMYRTS_NAV_8822C 8\n#define BIT_MASK_RXMYRTS_NAV_8822C 0xf\n#define BIT_RXMYRTS_NAV_8822C(x)                                               \\\n\t(((x) & BIT_MASK_RXMYRTS_NAV_8822C) << BIT_SHIFT_RXMYRTS_NAV_8822C)\n#define BITS_RXMYRTS_NAV_8822C                                                 \\\n\t(BIT_MASK_RXMYRTS_NAV_8822C << BIT_SHIFT_RXMYRTS_NAV_8822C)\n#define BIT_CLEAR_RXMYRTS_NAV_8822C(x) ((x) & (~BITS_RXMYRTS_NAV_8822C))\n#define BIT_GET_RXMYRTS_NAV_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RXMYRTS_NAV_8822C) & BIT_MASK_RXMYRTS_NAV_8822C)\n#define BIT_SET_RXMYRTS_NAV_8822C(x, v)                                        \\\n\t(BIT_CLEAR_RXMYRTS_NAV_8822C(x) | BIT_RXMYRTS_NAV_8822C(v))\n\n#define BIT_SHIFT_RTSRST_8822C 0\n#define BIT_MASK_RTSRST_8822C 0xff\n#define BIT_RTSRST_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_RTSRST_8822C) << BIT_SHIFT_RTSRST_8822C)\n#define BITS_RTSRST_8822C (BIT_MASK_RTSRST_8822C << BIT_SHIFT_RTSRST_8822C)\n#define BIT_CLEAR_RTSRST_8822C(x) ((x) & (~BITS_RTSRST_8822C))\n#define BIT_GET_RTSRST_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_RTSRST_8822C) & BIT_MASK_RTSRST_8822C)\n#define BIT_SET_RTSRST_8822C(x, v)                                             \\\n\t(BIT_CLEAR_RTSRST_8822C(x) | BIT_RTSRST_8822C(v))\n\n/* 2 REG_BACAMCMD_8822C (BLOCK ACK CAM COMMAND REGISTER) */\n#define BIT_BACAM_POLL_8822C BIT(31)\n#define BIT_BACAM_RST_8822C BIT(17)\n#define BIT_BACAM_RW_8822C BIT(16)\n\n#define BIT_SHIFT_TXSBM_8822C 14\n#define BIT_MASK_TXSBM_8822C 0x3\n#define BIT_TXSBM_8822C(x)                                                     \\\n\t(((x) & BIT_MASK_TXSBM_8822C) << BIT_SHIFT_TXSBM_8822C)\n#define BITS_TXSBM_8822C (BIT_MASK_TXSBM_8822C << BIT_SHIFT_TXSBM_8822C)\n#define BIT_CLEAR_TXSBM_8822C(x) ((x) & (~BITS_TXSBM_8822C))\n#define BIT_GET_TXSBM_8822C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TXSBM_8822C) & BIT_MASK_TXSBM_8822C)\n#define BIT_SET_TXSBM_8822C(x, v)                                              \\\n\t(BIT_CLEAR_TXSBM_8822C(x) | BIT_TXSBM_8822C(v))\n\n#define BIT_SHIFT_BACAM_ADDR_8822C 0\n#define BIT_MASK_BACAM_ADDR_8822C 0x3f\n#define BIT_BACAM_ADDR_8822C(x)                                                \\\n\t(((x) & BIT_MASK_BACAM_ADDR_8822C) << BIT_SHIFT_BACAM_ADDR_8822C)\n#define BITS_BACAM_ADDR_8822C                                                  \\\n\t(BIT_MASK_BACAM_ADDR_8822C << BIT_SHIFT_BACAM_ADDR_8822C)\n#define BIT_CLEAR_BACAM_ADDR_8822C(x) ((x) & (~BITS_BACAM_ADDR_8822C))\n#define BIT_GET_BACAM_ADDR_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BACAM_ADDR_8822C) & BIT_MASK_BACAM_ADDR_8822C)\n#define BIT_SET_BACAM_ADDR_8822C(x, v)                                         \\\n\t(BIT_CLEAR_BACAM_ADDR_8822C(x) | BIT_BACAM_ADDR_8822C(v))\n\n/* 2 REG_BACAMCONTENT_8822C (BLOCK ACK CAM CONTENT REGISTER) */\n\n#define BIT_SHIFT_BA_CONTENT_L_8822C 0\n#define BIT_MASK_BA_CONTENT_L_8822C 0xffffffffL\n#define BIT_BA_CONTENT_L_8822C(x)                                              \\\n\t(((x) & BIT_MASK_BA_CONTENT_L_8822C) << BIT_SHIFT_BA_CONTENT_L_8822C)\n#define BITS_BA_CONTENT_L_8822C                                                \\\n\t(BIT_MASK_BA_CONTENT_L_8822C << BIT_SHIFT_BA_CONTENT_L_8822C)\n#define BIT_CLEAR_BA_CONTENT_L_8822C(x) ((x) & (~BITS_BA_CONTENT_L_8822C))\n#define BIT_GET_BA_CONTENT_L_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BA_CONTENT_L_8822C) & BIT_MASK_BA_CONTENT_L_8822C)\n#define BIT_SET_BA_CONTENT_L_8822C(x, v)                                       \\\n\t(BIT_CLEAR_BA_CONTENT_L_8822C(x) | BIT_BA_CONTENT_L_8822C(v))\n\n/* 2 REG_BACAMCONTENT_H_8822C (BLOCK ACK CAM CONTENT REGISTER) */\n\n#define BIT_SHIFT_BA_CONTENT_H_8822C 0\n#define BIT_MASK_BA_CONTENT_H_8822C 0xffffffffL\n#define BIT_BA_CONTENT_H_8822C(x)                                              \\\n\t(((x) & BIT_MASK_BA_CONTENT_H_8822C) << BIT_SHIFT_BA_CONTENT_H_8822C)\n#define BITS_BA_CONTENT_H_8822C                                                \\\n\t(BIT_MASK_BA_CONTENT_H_8822C << BIT_SHIFT_BA_CONTENT_H_8822C)\n#define BIT_CLEAR_BA_CONTENT_H_8822C(x) ((x) & (~BITS_BA_CONTENT_H_8822C))\n#define BIT_GET_BA_CONTENT_H_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BA_CONTENT_H_8822C) & BIT_MASK_BA_CONTENT_H_8822C)\n#define BIT_SET_BA_CONTENT_H_8822C(x, v)                                       \\\n\t(BIT_CLEAR_BA_CONTENT_H_8822C(x) | BIT_BA_CONTENT_H_8822C(v))\n\n/* 2 REG_LBDLY_8822C (LOOPBACK DELAY REGISTER) */\n\n#define BIT_SHIFT_LBDLY_8822C 0\n#define BIT_MASK_LBDLY_8822C 0x1f\n#define BIT_LBDLY_8822C(x)                                                     \\\n\t(((x) & BIT_MASK_LBDLY_8822C) << BIT_SHIFT_LBDLY_8822C)\n#define BITS_LBDLY_8822C (BIT_MASK_LBDLY_8822C << BIT_SHIFT_LBDLY_8822C)\n#define BIT_CLEAR_LBDLY_8822C(x) ((x) & (~BITS_LBDLY_8822C))\n#define BIT_GET_LBDLY_8822C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_LBDLY_8822C) & BIT_MASK_LBDLY_8822C)\n#define BIT_SET_LBDLY_8822C(x, v)                                              \\\n\t(BIT_CLEAR_LBDLY_8822C(x) | BIT_LBDLY_8822C(v))\n\n/* 2 REG_WMAC_BACAM_RPMEN_8822C */\n\n#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C 2\n#define BIT_MASK_BITMAP_SSNBK_COUNTER_8822C 0x3f\n#define BIT_BITMAP_SSNBK_COUNTER_8822C(x)                                      \\\n\t(((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822C)                           \\\n\t << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C)\n#define BITS_BITMAP_SSNBK_COUNTER_8822C                                        \\\n\t(BIT_MASK_BITMAP_SSNBK_COUNTER_8822C                                   \\\n\t << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C)\n#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822C(x)                                \\\n\t((x) & (~BITS_BITMAP_SSNBK_COUNTER_8822C))\n#define BIT_GET_BITMAP_SSNBK_COUNTER_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C) &                       \\\n\t BIT_MASK_BITMAP_SSNBK_COUNTER_8822C)\n#define BIT_SET_BITMAP_SSNBK_COUNTER_8822C(x, v)                               \\\n\t(BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822C(x) |                             \\\n\t BIT_BITMAP_SSNBK_COUNTER_8822C(v))\n\n#define BIT_BITMAP_EN_8822C BIT(1)\n#define BIT_WMAC_BACAM_RPMEN_8822C BIT(0)\n\n/* 2 REG_TX_RX_8822C STATUS */\n\n#define BIT_SHIFT_RXPKT_TYPE_8822C 2\n#define BIT_MASK_RXPKT_TYPE_8822C 0x3f\n#define BIT_RXPKT_TYPE_8822C(x)                                                \\\n\t(((x) & BIT_MASK_RXPKT_TYPE_8822C) << BIT_SHIFT_RXPKT_TYPE_8822C)\n#define BITS_RXPKT_TYPE_8822C                                                  \\\n\t(BIT_MASK_RXPKT_TYPE_8822C << BIT_SHIFT_RXPKT_TYPE_8822C)\n#define BIT_CLEAR_RXPKT_TYPE_8822C(x) ((x) & (~BITS_RXPKT_TYPE_8822C))\n#define BIT_GET_RXPKT_TYPE_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXPKT_TYPE_8822C) & BIT_MASK_RXPKT_TYPE_8822C)\n#define BIT_SET_RXPKT_TYPE_8822C(x, v)                                         \\\n\t(BIT_CLEAR_RXPKT_TYPE_8822C(x) | BIT_RXPKT_TYPE_8822C(v))\n\n#define BIT_TXACT_IND_8822C BIT(1)\n#define BIT_RXACT_IND_8822C BIT(0)\n\n/* 2 REG_WMAC_BITMAP_CTL_8822C */\n#define BIT_BITMAP_VO_8822C BIT(7)\n#define BIT_BITMAP_VI_8822C BIT(6)\n#define BIT_BITMAP_BE_8822C BIT(5)\n#define BIT_BITMAP_BK_8822C BIT(4)\n\n#define BIT_SHIFT_BITMAP_CONDITION_8822C 2\n#define BIT_MASK_BITMAP_CONDITION_8822C 0x3\n#define BIT_BITMAP_CONDITION_8822C(x)                                          \\\n\t(((x) & BIT_MASK_BITMAP_CONDITION_8822C)                               \\\n\t << BIT_SHIFT_BITMAP_CONDITION_8822C)\n#define BITS_BITMAP_CONDITION_8822C                                            \\\n\t(BIT_MASK_BITMAP_CONDITION_8822C << BIT_SHIFT_BITMAP_CONDITION_8822C)\n#define BIT_CLEAR_BITMAP_CONDITION_8822C(x)                                    \\\n\t((x) & (~BITS_BITMAP_CONDITION_8822C))\n#define BIT_GET_BITMAP_CONDITION_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BITMAP_CONDITION_8822C) &                           \\\n\t BIT_MASK_BITMAP_CONDITION_8822C)\n#define BIT_SET_BITMAP_CONDITION_8822C(x, v)                                   \\\n\t(BIT_CLEAR_BITMAP_CONDITION_8822C(x) | BIT_BITMAP_CONDITION_8822C(v))\n\n#define BIT_BITMAP_SSNBK_COUNTER_CLR_8822C BIT(1)\n#define BIT_BITMAP_FORCE_8822C BIT(0)\n\n/* 2 REG_RXERR_RPT_8822C (RX ERROR REPORT REGISTER) */\n\n#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C 28\n#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C 0xf\n#define BIT_RXERR_RPT_SEL_V1_3_0_8822C(x)                                      \\\n\t(((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C)                           \\\n\t << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C)\n#define BITS_RXERR_RPT_SEL_V1_3_0_8822C                                        \\\n\t(BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C                                   \\\n\t << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C)\n#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822C(x)                                \\\n\t((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8822C))\n#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C) &                       \\\n\t BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C)\n#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8822C(x, v)                               \\\n\t(BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822C(x) |                             \\\n\t BIT_RXERR_RPT_SEL_V1_3_0_8822C(v))\n\n#define BIT_RXERR_RPT_RST_8822C BIT(27)\n#define BIT_RXERR_RPT_SEL_V1_4_8822C BIT(26)\n\n#define BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C 24\n#define BIT_MASK_UD_SELECT_BSSID_2_1_8822C 0x3\n#define BIT_UD_SELECT_BSSID_2_1_8822C(x)                                       \\\n\t(((x) & BIT_MASK_UD_SELECT_BSSID_2_1_8822C)                            \\\n\t << BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C)\n#define BITS_UD_SELECT_BSSID_2_1_8822C                                         \\\n\t(BIT_MASK_UD_SELECT_BSSID_2_1_8822C                                    \\\n\t << BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C)\n#define BIT_CLEAR_UD_SELECT_BSSID_2_1_8822C(x)                                 \\\n\t((x) & (~BITS_UD_SELECT_BSSID_2_1_8822C))\n#define BIT_GET_UD_SELECT_BSSID_2_1_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C) &                        \\\n\t BIT_MASK_UD_SELECT_BSSID_2_1_8822C)\n#define BIT_SET_UD_SELECT_BSSID_2_1_8822C(x, v)                                \\\n\t(BIT_CLEAR_UD_SELECT_BSSID_2_1_8822C(x) |                              \\\n\t BIT_UD_SELECT_BSSID_2_1_8822C(v))\n\n#define BIT_W1S_8822C BIT(23)\n#define BIT_UD_SELECT_BSSID_0_8822C BIT(22)\n\n#define BIT_SHIFT_UD_SUB_TYPE_8822C 18\n#define BIT_MASK_UD_SUB_TYPE_8822C 0xf\n#define BIT_UD_SUB_TYPE_8822C(x)                                               \\\n\t(((x) & BIT_MASK_UD_SUB_TYPE_8822C) << BIT_SHIFT_UD_SUB_TYPE_8822C)\n#define BITS_UD_SUB_TYPE_8822C                                                 \\\n\t(BIT_MASK_UD_SUB_TYPE_8822C << BIT_SHIFT_UD_SUB_TYPE_8822C)\n#define BIT_CLEAR_UD_SUB_TYPE_8822C(x) ((x) & (~BITS_UD_SUB_TYPE_8822C))\n#define BIT_GET_UD_SUB_TYPE_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_UD_SUB_TYPE_8822C) & BIT_MASK_UD_SUB_TYPE_8822C)\n#define BIT_SET_UD_SUB_TYPE_8822C(x, v)                                        \\\n\t(BIT_CLEAR_UD_SUB_TYPE_8822C(x) | BIT_UD_SUB_TYPE_8822C(v))\n\n#define BIT_SHIFT_UD_TYPE_8822C 16\n#define BIT_MASK_UD_TYPE_8822C 0x3\n#define BIT_UD_TYPE_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_UD_TYPE_8822C) << BIT_SHIFT_UD_TYPE_8822C)\n#define BITS_UD_TYPE_8822C (BIT_MASK_UD_TYPE_8822C << BIT_SHIFT_UD_TYPE_8822C)\n#define BIT_CLEAR_UD_TYPE_8822C(x) ((x) & (~BITS_UD_TYPE_8822C))\n#define BIT_GET_UD_TYPE_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_UD_TYPE_8822C) & BIT_MASK_UD_TYPE_8822C)\n#define BIT_SET_UD_TYPE_8822C(x, v)                                            \\\n\t(BIT_CLEAR_UD_TYPE_8822C(x) | BIT_UD_TYPE_8822C(v))\n\n#define BIT_SHIFT_RPT_COUNTER_8822C 0\n#define BIT_MASK_RPT_COUNTER_8822C 0xffff\n#define BIT_RPT_COUNTER_8822C(x)                                               \\\n\t(((x) & BIT_MASK_RPT_COUNTER_8822C) << BIT_SHIFT_RPT_COUNTER_8822C)\n#define BITS_RPT_COUNTER_8822C                                                 \\\n\t(BIT_MASK_RPT_COUNTER_8822C << BIT_SHIFT_RPT_COUNTER_8822C)\n#define BIT_CLEAR_RPT_COUNTER_8822C(x) ((x) & (~BITS_RPT_COUNTER_8822C))\n#define BIT_GET_RPT_COUNTER_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_RPT_COUNTER_8822C) & BIT_MASK_RPT_COUNTER_8822C)\n#define BIT_SET_RPT_COUNTER_8822C(x, v)                                        \\\n\t(BIT_CLEAR_RPT_COUNTER_8822C(x) | BIT_RPT_COUNTER_8822C(v))\n\n/* 2 REG_WMAC_TRXPTCL_CTL_8822C\t(WMAC TX/RX PROTOCOL CONTROL REGISTER) */\n#define BIT_ACKTO_BLOCK_SCH_EN_8822C BIT(27)\n#define BIT_EIFS_BLOCK_SCH_EN_8822C BIT(26)\n#define BIT_PLCPCHK_RST_EIFS_8822C BIT(25)\n#define BIT_CCA_RST_EIFS_8822C BIT(24)\n#define BIT_DIS_UPD_MYRXPKTNAV_8822C BIT(23)\n#define BIT_EARLY_TXBA_8822C BIT(22)\n\n#define BIT_SHIFT_RESP_CHNBUSY_8822C 20\n#define BIT_MASK_RESP_CHNBUSY_8822C 0x3\n#define BIT_RESP_CHNBUSY_8822C(x)                                              \\\n\t(((x) & BIT_MASK_RESP_CHNBUSY_8822C) << BIT_SHIFT_RESP_CHNBUSY_8822C)\n#define BITS_RESP_CHNBUSY_8822C                                                \\\n\t(BIT_MASK_RESP_CHNBUSY_8822C << BIT_SHIFT_RESP_CHNBUSY_8822C)\n#define BIT_CLEAR_RESP_CHNBUSY_8822C(x) ((x) & (~BITS_RESP_CHNBUSY_8822C))\n#define BIT_GET_RESP_CHNBUSY_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RESP_CHNBUSY_8822C) & BIT_MASK_RESP_CHNBUSY_8822C)\n#define BIT_SET_RESP_CHNBUSY_8822C(x, v)                                       \\\n\t(BIT_CLEAR_RESP_CHNBUSY_8822C(x) | BIT_RESP_CHNBUSY_8822C(v))\n\n#define BIT_RESP_DCTS_EN_8822C BIT(19)\n#define BIT_RESP_DCFE_EN_8822C BIT(18)\n#define BIT_RESP_SPLCPEN_8822C BIT(17)\n#define BIT_RESP_SGIEN_8822C BIT(16)\n#define BIT_RESP_LDPC_EN_8822C BIT(15)\n#define BIT_DIS_RESP_ACKINCCA_8822C BIT(14)\n#define BIT_DIS_RESP_CTSINCCA_8822C BIT(13)\n\n#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C 10\n#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C 0x7\n#define BIT_R_WMAC_SECOND_CCA_TIMER_8822C(x)                                   \\\n\t(((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C)                        \\\n\t << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C)\n#define BITS_R_WMAC_SECOND_CCA_TIMER_8822C                                     \\\n\t(BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C                                \\\n\t << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C)\n#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822C(x)                             \\\n\t((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8822C))\n#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8822C(x)                               \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C) &                    \\\n\t BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C)\n#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8822C(x, v)                            \\\n\t(BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822C(x) |                          \\\n\t BIT_R_WMAC_SECOND_CCA_TIMER_8822C(v))\n\n#define BIT_SHIFT_RFMOD_8822C 7\n#define BIT_MASK_RFMOD_8822C 0x3\n#define BIT_RFMOD_8822C(x)                                                     \\\n\t(((x) & BIT_MASK_RFMOD_8822C) << BIT_SHIFT_RFMOD_8822C)\n#define BITS_RFMOD_8822C (BIT_MASK_RFMOD_8822C << BIT_SHIFT_RFMOD_8822C)\n#define BIT_CLEAR_RFMOD_8822C(x) ((x) & (~BITS_RFMOD_8822C))\n#define BIT_GET_RFMOD_8822C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_RFMOD_8822C) & BIT_MASK_RFMOD_8822C)\n#define BIT_SET_RFMOD_8822C(x, v)                                              \\\n\t(BIT_CLEAR_RFMOD_8822C(x) | BIT_RFMOD_8822C(v))\n\n#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C 5\n#define BIT_MASK_RESP_CTS_DYNBW_SEL_8822C 0x3\n#define BIT_RESP_CTS_DYNBW_SEL_8822C(x)                                        \\\n\t(((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822C)                             \\\n\t << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C)\n#define BITS_RESP_CTS_DYNBW_SEL_8822C                                          \\\n\t(BIT_MASK_RESP_CTS_DYNBW_SEL_8822C                                     \\\n\t << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C)\n#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822C(x)                                  \\\n\t((x) & (~BITS_RESP_CTS_DYNBW_SEL_8822C))\n#define BIT_GET_RESP_CTS_DYNBW_SEL_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C) &                         \\\n\t BIT_MASK_RESP_CTS_DYNBW_SEL_8822C)\n#define BIT_SET_RESP_CTS_DYNBW_SEL_8822C(x, v)                                 \\\n\t(BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822C(x) |                               \\\n\t BIT_RESP_CTS_DYNBW_SEL_8822C(v))\n\n#define BIT_DLY_TX_WAIT_RXANTSEL_8822C BIT(4)\n#define BIT_TXRESP_BY_RXANTSEL_8822C BIT(3)\n\n#define BIT_SHIFT_ORIG_DCTS_CHK_8822C 0\n#define BIT_MASK_ORIG_DCTS_CHK_8822C 0x3\n#define BIT_ORIG_DCTS_CHK_8822C(x)                                             \\\n\t(((x) & BIT_MASK_ORIG_DCTS_CHK_8822C) << BIT_SHIFT_ORIG_DCTS_CHK_8822C)\n#define BITS_ORIG_DCTS_CHK_8822C                                               \\\n\t(BIT_MASK_ORIG_DCTS_CHK_8822C << BIT_SHIFT_ORIG_DCTS_CHK_8822C)\n#define BIT_CLEAR_ORIG_DCTS_CHK_8822C(x) ((x) & (~BITS_ORIG_DCTS_CHK_8822C))\n#define BIT_GET_ORIG_DCTS_CHK_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8822C) & BIT_MASK_ORIG_DCTS_CHK_8822C)\n#define BIT_SET_ORIG_DCTS_CHK_8822C(x, v)                                      \\\n\t(BIT_CLEAR_ORIG_DCTS_CHK_8822C(x) | BIT_ORIG_DCTS_CHK_8822C(v))\n\n/* 2 REG_WMAC_TRXPTCL_CTL_H_8822C */\n\n#define BIT_SHIFT_ACKBA_TYPSEL_8822C 28\n#define BIT_MASK_ACKBA_TYPSEL_8822C 0xf\n#define BIT_ACKBA_TYPSEL_8822C(x)                                              \\\n\t(((x) & BIT_MASK_ACKBA_TYPSEL_8822C) << BIT_SHIFT_ACKBA_TYPSEL_8822C)\n#define BITS_ACKBA_TYPSEL_8822C                                                \\\n\t(BIT_MASK_ACKBA_TYPSEL_8822C << BIT_SHIFT_ACKBA_TYPSEL_8822C)\n#define BIT_CLEAR_ACKBA_TYPSEL_8822C(x) ((x) & (~BITS_ACKBA_TYPSEL_8822C))\n#define BIT_GET_ACKBA_TYPSEL_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_ACKBA_TYPSEL_8822C) & BIT_MASK_ACKBA_TYPSEL_8822C)\n#define BIT_SET_ACKBA_TYPSEL_8822C(x, v)                                       \\\n\t(BIT_CLEAR_ACKBA_TYPSEL_8822C(x) | BIT_ACKBA_TYPSEL_8822C(v))\n\n#define BIT_SHIFT_ACKBA_ACKPCHK_8822C 24\n#define BIT_MASK_ACKBA_ACKPCHK_8822C 0xf\n#define BIT_ACKBA_ACKPCHK_8822C(x)                                             \\\n\t(((x) & BIT_MASK_ACKBA_ACKPCHK_8822C) << BIT_SHIFT_ACKBA_ACKPCHK_8822C)\n#define BITS_ACKBA_ACKPCHK_8822C                                               \\\n\t(BIT_MASK_ACKBA_ACKPCHK_8822C << BIT_SHIFT_ACKBA_ACKPCHK_8822C)\n#define BIT_CLEAR_ACKBA_ACKPCHK_8822C(x) ((x) & (~BITS_ACKBA_ACKPCHK_8822C))\n#define BIT_GET_ACKBA_ACKPCHK_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8822C) & BIT_MASK_ACKBA_ACKPCHK_8822C)\n#define BIT_SET_ACKBA_ACKPCHK_8822C(x, v)                                      \\\n\t(BIT_CLEAR_ACKBA_ACKPCHK_8822C(x) | BIT_ACKBA_ACKPCHK_8822C(v))\n\n#define BIT_SHIFT_ACKBAR_TYPESEL_8822C 16\n#define BIT_MASK_ACKBAR_TYPESEL_8822C 0xff\n#define BIT_ACKBAR_TYPESEL_8822C(x)                                            \\\n\t(((x) & BIT_MASK_ACKBAR_TYPESEL_8822C)                                 \\\n\t << BIT_SHIFT_ACKBAR_TYPESEL_8822C)\n#define BITS_ACKBAR_TYPESEL_8822C                                              \\\n\t(BIT_MASK_ACKBAR_TYPESEL_8822C << BIT_SHIFT_ACKBAR_TYPESEL_8822C)\n#define BIT_CLEAR_ACKBAR_TYPESEL_8822C(x) ((x) & (~BITS_ACKBAR_TYPESEL_8822C))\n#define BIT_GET_ACKBAR_TYPESEL_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8822C) &                             \\\n\t BIT_MASK_ACKBAR_TYPESEL_8822C)\n#define BIT_SET_ACKBAR_TYPESEL_8822C(x, v)                                     \\\n\t(BIT_CLEAR_ACKBAR_TYPESEL_8822C(x) | BIT_ACKBAR_TYPESEL_8822C(v))\n\n#define BIT_SHIFT_ACKBAR_ACKPCHK_8822C 12\n#define BIT_MASK_ACKBAR_ACKPCHK_8822C 0xf\n#define BIT_ACKBAR_ACKPCHK_8822C(x)                                            \\\n\t(((x) & BIT_MASK_ACKBAR_ACKPCHK_8822C)                                 \\\n\t << BIT_SHIFT_ACKBAR_ACKPCHK_8822C)\n#define BITS_ACKBAR_ACKPCHK_8822C                                              \\\n\t(BIT_MASK_ACKBAR_ACKPCHK_8822C << BIT_SHIFT_ACKBAR_ACKPCHK_8822C)\n#define BIT_CLEAR_ACKBAR_ACKPCHK_8822C(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8822C))\n#define BIT_GET_ACKBAR_ACKPCHK_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8822C) &                             \\\n\t BIT_MASK_ACKBAR_ACKPCHK_8822C)\n#define BIT_SET_ACKBAR_ACKPCHK_8822C(x, v)                                     \\\n\t(BIT_CLEAR_ACKBAR_ACKPCHK_8822C(x) | BIT_ACKBAR_ACKPCHK_8822C(v))\n\n#define BIT_RXBA_IGNOREA2_V1_8822C BIT(10)\n#define BIT_EN_SAVE_ALL_TXOPADDR_V1_8822C BIT(9)\n#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1_8822C BIT(8)\n#define BIT_DIS_TXBA_AMPDUFCSERR_V1_8822C BIT(7)\n#define BIT_DIS_TXBA_RXBARINFULL_V1_8822C BIT(6)\n#define BIT_DIS_TXCFE_INFULL_V1_8822C BIT(5)\n#define BIT_DIS_TXCTS_INFULL_V1_8822C BIT(4)\n#define BIT_EN_TXACKBA_IN_TX_RDG_V1_8822C BIT(3)\n#define BIT_EN_TXACKBA_IN_TXOP_V1_8822C BIT(2)\n#define BIT_EN_TXCTS_IN_RXNAV_V1_8822C BIT(1)\n#define BIT_EN_TXCTS_INTXOP_V1_8822C BIT(0)\n\n/* 2 REG_CAMCMD_8822C (CAM COMMAND REGISTER) */\n#define BIT_SECCAM_POLLING_8822C BIT(31)\n#define BIT_SECCAM_CLR_8822C BIT(30)\n#define BIT_SECCAM_WE_8822C BIT(16)\n\n#define BIT_SHIFT_SECCAM_ADDR_V2_8822C 0\n#define BIT_MASK_SECCAM_ADDR_V2_8822C 0x3ff\n#define BIT_SECCAM_ADDR_V2_8822C(x)                                            \\\n\t(((x) & BIT_MASK_SECCAM_ADDR_V2_8822C)                                 \\\n\t << BIT_SHIFT_SECCAM_ADDR_V2_8822C)\n#define BITS_SECCAM_ADDR_V2_8822C                                              \\\n\t(BIT_MASK_SECCAM_ADDR_V2_8822C << BIT_SHIFT_SECCAM_ADDR_V2_8822C)\n#define BIT_CLEAR_SECCAM_ADDR_V2_8822C(x) ((x) & (~BITS_SECCAM_ADDR_V2_8822C))\n#define BIT_GET_SECCAM_ADDR_V2_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8822C) &                             \\\n\t BIT_MASK_SECCAM_ADDR_V2_8822C)\n#define BIT_SET_SECCAM_ADDR_V2_8822C(x, v)                                     \\\n\t(BIT_CLEAR_SECCAM_ADDR_V2_8822C(x) | BIT_SECCAM_ADDR_V2_8822C(v))\n\n/* 2 REG_CAMWRITE_8822C (CAM WRITE REGISTER) */\n\n#define BIT_SHIFT_CAMW_DATA_8822C 0\n#define BIT_MASK_CAMW_DATA_8822C 0xffffffffL\n#define BIT_CAMW_DATA_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_CAMW_DATA_8822C) << BIT_SHIFT_CAMW_DATA_8822C)\n#define BITS_CAMW_DATA_8822C                                                   \\\n\t(BIT_MASK_CAMW_DATA_8822C << BIT_SHIFT_CAMW_DATA_8822C)\n#define BIT_CLEAR_CAMW_DATA_8822C(x) ((x) & (~BITS_CAMW_DATA_8822C))\n#define BIT_GET_CAMW_DATA_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_CAMW_DATA_8822C) & BIT_MASK_CAMW_DATA_8822C)\n#define BIT_SET_CAMW_DATA_8822C(x, v)                                          \\\n\t(BIT_CLEAR_CAMW_DATA_8822C(x) | BIT_CAMW_DATA_8822C(v))\n\n/* 2 REG_CAMREAD_8822C (CAM READ REGISTER) */\n\n#define BIT_SHIFT_CAMR_DATA_8822C 0\n#define BIT_MASK_CAMR_DATA_8822C 0xffffffffL\n#define BIT_CAMR_DATA_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_CAMR_DATA_8822C) << BIT_SHIFT_CAMR_DATA_8822C)\n#define BITS_CAMR_DATA_8822C                                                   \\\n\t(BIT_MASK_CAMR_DATA_8822C << BIT_SHIFT_CAMR_DATA_8822C)\n#define BIT_CLEAR_CAMR_DATA_8822C(x) ((x) & (~BITS_CAMR_DATA_8822C))\n#define BIT_GET_CAMR_DATA_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_CAMR_DATA_8822C) & BIT_MASK_CAMR_DATA_8822C)\n#define BIT_SET_CAMR_DATA_8822C(x, v)                                          \\\n\t(BIT_CLEAR_CAMR_DATA_8822C(x) | BIT_CAMR_DATA_8822C(v))\n\n/* 2 REG_CAMDBG_8822C (CAM DEBUG REGISTER) */\n#define BIT_SECCAM_INFO_8822C BIT(31)\n#define BIT_SEC_KEYFOUND_8822C BIT(15)\n\n#define BIT_SHIFT_CAMDBG_SEC_TYPE_8822C 12\n#define BIT_MASK_CAMDBG_SEC_TYPE_8822C 0x7\n#define BIT_CAMDBG_SEC_TYPE_8822C(x)                                           \\\n\t(((x) & BIT_MASK_CAMDBG_SEC_TYPE_8822C)                                \\\n\t << BIT_SHIFT_CAMDBG_SEC_TYPE_8822C)\n#define BITS_CAMDBG_SEC_TYPE_8822C                                             \\\n\t(BIT_MASK_CAMDBG_SEC_TYPE_8822C << BIT_SHIFT_CAMDBG_SEC_TYPE_8822C)\n#define BIT_CLEAR_CAMDBG_SEC_TYPE_8822C(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8822C))\n#define BIT_GET_CAMDBG_SEC_TYPE_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8822C) &                            \\\n\t BIT_MASK_CAMDBG_SEC_TYPE_8822C)\n#define BIT_SET_CAMDBG_SEC_TYPE_8822C(x, v)                                    \\\n\t(BIT_CLEAR_CAMDBG_SEC_TYPE_8822C(x) | BIT_CAMDBG_SEC_TYPE_8822C(v))\n\n#define BIT_CAMDBG_EXT_SECTYPE_8822C BIT(11)\n\n#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C 5\n#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C 0x1f\n#define BIT_CAMDBG_MIC_KEY_IDX_8822C(x)                                        \\\n\t(((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C)                             \\\n\t << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C)\n#define BITS_CAMDBG_MIC_KEY_IDX_8822C                                          \\\n\t(BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C                                     \\\n\t << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C)\n#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822C(x)                                  \\\n\t((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8822C))\n#define BIT_GET_CAMDBG_MIC_KEY_IDX_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C) &                         \\\n\t BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C)\n#define BIT_SET_CAMDBG_MIC_KEY_IDX_8822C(x, v)                                 \\\n\t(BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822C(x) |                               \\\n\t BIT_CAMDBG_MIC_KEY_IDX_8822C(v))\n\n#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C 0\n#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C 0x1f\n#define BIT_CAMDBG_SEC_KEY_IDX_8822C(x)                                        \\\n\t(((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C)                             \\\n\t << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C)\n#define BITS_CAMDBG_SEC_KEY_IDX_8822C                                          \\\n\t(BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C                                     \\\n\t << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C)\n#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822C(x)                                  \\\n\t((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8822C))\n#define BIT_GET_CAMDBG_SEC_KEY_IDX_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C) &                         \\\n\t BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C)\n#define BIT_SET_CAMDBG_SEC_KEY_IDX_8822C(x, v)                                 \\\n\t(BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822C(x) |                               \\\n\t BIT_CAMDBG_SEC_KEY_IDX_8822C(v))\n\n/* 2 REG_SECCFG_8822C (SECURITY CONFIGURATION REGISTER) */\n#define BIT_DIS_GCLK_WAPI_8822C BIT(15)\n#define BIT_DIS_GCLK_AES_8822C BIT(14)\n#define BIT_DIS_GCLK_TKIP_8822C BIT(13)\n#define BIT_AES_SEL_QC_1_8822C BIT(12)\n#define BIT_AES_SEL_QC_0_8822C BIT(11)\n#define BIT_CHK_BMC_8822C BIT(9)\n#define BIT_CHK_KEYID_8822C BIT(8)\n#define BIT_RXBCUSEDK_8822C BIT(7)\n#define BIT_TXBCUSEDK_8822C BIT(6)\n#define BIT_NOSKMC_8822C BIT(5)\n#define BIT_SKBYA2_8822C BIT(4)\n#define BIT_RXDEC_8822C BIT(3)\n#define BIT_TXENC_8822C BIT(2)\n#define BIT_RXUHUSEDK_8822C BIT(1)\n#define BIT_TXUHUSEDK_8822C BIT(0)\n\n/* 2 REG_RXFILTER_CATEGORY_1_8822C */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_1_8822C 0\n#define BIT_MASK_RXFILTER_CATEGORY_1_8822C 0xff\n#define BIT_RXFILTER_CATEGORY_1_8822C(x)                                       \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_1_8822C)                            \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_1_8822C)\n#define BITS_RXFILTER_CATEGORY_1_8822C                                         \\\n\t(BIT_MASK_RXFILTER_CATEGORY_1_8822C                                    \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_1_8822C)\n#define BIT_CLEAR_RXFILTER_CATEGORY_1_8822C(x)                                 \\\n\t((x) & (~BITS_RXFILTER_CATEGORY_1_8822C))\n#define BIT_GET_RXFILTER_CATEGORY_1_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8822C) &                        \\\n\t BIT_MASK_RXFILTER_CATEGORY_1_8822C)\n#define BIT_SET_RXFILTER_CATEGORY_1_8822C(x, v)                                \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_1_8822C(x) |                              \\\n\t BIT_RXFILTER_CATEGORY_1_8822C(v))\n\n/* 2 REG_RXFILTER_ACTION_1_8822C */\n\n#define BIT_SHIFT_RXFILTER_ACTION_1_8822C 0\n#define BIT_MASK_RXFILTER_ACTION_1_8822C 0xff\n#define BIT_RXFILTER_ACTION_1_8822C(x)                                         \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_1_8822C)                              \\\n\t << BIT_SHIFT_RXFILTER_ACTION_1_8822C)\n#define BITS_RXFILTER_ACTION_1_8822C                                           \\\n\t(BIT_MASK_RXFILTER_ACTION_1_8822C << BIT_SHIFT_RXFILTER_ACTION_1_8822C)\n#define BIT_CLEAR_RXFILTER_ACTION_1_8822C(x)                                   \\\n\t((x) & (~BITS_RXFILTER_ACTION_1_8822C))\n#define BIT_GET_RXFILTER_ACTION_1_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8822C) &                          \\\n\t BIT_MASK_RXFILTER_ACTION_1_8822C)\n#define BIT_SET_RXFILTER_ACTION_1_8822C(x, v)                                  \\\n\t(BIT_CLEAR_RXFILTER_ACTION_1_8822C(x) | BIT_RXFILTER_ACTION_1_8822C(v))\n\n/* 2 REG_RXFILTER_CATEGORY_2_8822C */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_2_8822C 0\n#define BIT_MASK_RXFILTER_CATEGORY_2_8822C 0xff\n#define BIT_RXFILTER_CATEGORY_2_8822C(x)                                       \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_2_8822C)                            \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_2_8822C)\n#define BITS_RXFILTER_CATEGORY_2_8822C                                         \\\n\t(BIT_MASK_RXFILTER_CATEGORY_2_8822C                                    \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_2_8822C)\n#define BIT_CLEAR_RXFILTER_CATEGORY_2_8822C(x)                                 \\\n\t((x) & (~BITS_RXFILTER_CATEGORY_2_8822C))\n#define BIT_GET_RXFILTER_CATEGORY_2_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8822C) &                        \\\n\t BIT_MASK_RXFILTER_CATEGORY_2_8822C)\n#define BIT_SET_RXFILTER_CATEGORY_2_8822C(x, v)                                \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_2_8822C(x) |                              \\\n\t BIT_RXFILTER_CATEGORY_2_8822C(v))\n\n/* 2 REG_RXFILTER_ACTION_2_8822C */\n\n#define BIT_SHIFT_RXFILTER_ACTION_2_8822C 0\n#define BIT_MASK_RXFILTER_ACTION_2_8822C 0xff\n#define BIT_RXFILTER_ACTION_2_8822C(x)                                         \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_2_8822C)                              \\\n\t << BIT_SHIFT_RXFILTER_ACTION_2_8822C)\n#define BITS_RXFILTER_ACTION_2_8822C                                           \\\n\t(BIT_MASK_RXFILTER_ACTION_2_8822C << BIT_SHIFT_RXFILTER_ACTION_2_8822C)\n#define BIT_CLEAR_RXFILTER_ACTION_2_8822C(x)                                   \\\n\t((x) & (~BITS_RXFILTER_ACTION_2_8822C))\n#define BIT_GET_RXFILTER_ACTION_2_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8822C) &                          \\\n\t BIT_MASK_RXFILTER_ACTION_2_8822C)\n#define BIT_SET_RXFILTER_ACTION_2_8822C(x, v)                                  \\\n\t(BIT_CLEAR_RXFILTER_ACTION_2_8822C(x) | BIT_RXFILTER_ACTION_2_8822C(v))\n\n/* 2 REG_RXFILTER_CATEGORY_3_8822C */\n\n#define BIT_SHIFT_RXFILTER_CATEGORY_3_8822C 0\n#define BIT_MASK_RXFILTER_CATEGORY_3_8822C 0xff\n#define BIT_RXFILTER_CATEGORY_3_8822C(x)                                       \\\n\t(((x) & BIT_MASK_RXFILTER_CATEGORY_3_8822C)                            \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_3_8822C)\n#define BITS_RXFILTER_CATEGORY_3_8822C                                         \\\n\t(BIT_MASK_RXFILTER_CATEGORY_3_8822C                                    \\\n\t << BIT_SHIFT_RXFILTER_CATEGORY_3_8822C)\n#define BIT_CLEAR_RXFILTER_CATEGORY_3_8822C(x)                                 \\\n\t((x) & (~BITS_RXFILTER_CATEGORY_3_8822C))\n#define BIT_GET_RXFILTER_CATEGORY_3_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8822C) &                        \\\n\t BIT_MASK_RXFILTER_CATEGORY_3_8822C)\n#define BIT_SET_RXFILTER_CATEGORY_3_8822C(x, v)                                \\\n\t(BIT_CLEAR_RXFILTER_CATEGORY_3_8822C(x) |                              \\\n\t BIT_RXFILTER_CATEGORY_3_8822C(v))\n\n/* 2 REG_RXFILTER_ACTION_3_8822C */\n\n#define BIT_SHIFT_RXFILTER_ACTION_3_8822C 0\n#define BIT_MASK_RXFILTER_ACTION_3_8822C 0xff\n#define BIT_RXFILTER_ACTION_3_8822C(x)                                         \\\n\t(((x) & BIT_MASK_RXFILTER_ACTION_3_8822C)                              \\\n\t << BIT_SHIFT_RXFILTER_ACTION_3_8822C)\n#define BITS_RXFILTER_ACTION_3_8822C                                           \\\n\t(BIT_MASK_RXFILTER_ACTION_3_8822C << BIT_SHIFT_RXFILTER_ACTION_3_8822C)\n#define BIT_CLEAR_RXFILTER_ACTION_3_8822C(x)                                   \\\n\t((x) & (~BITS_RXFILTER_ACTION_3_8822C))\n#define BIT_GET_RXFILTER_ACTION_3_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8822C) &                          \\\n\t BIT_MASK_RXFILTER_ACTION_3_8822C)\n#define BIT_SET_RXFILTER_ACTION_3_8822C(x, v)                                  \\\n\t(BIT_CLEAR_RXFILTER_ACTION_3_8822C(x) | BIT_RXFILTER_ACTION_3_8822C(v))\n\n/* 2 REG_RXFLTMAP3_8822C (RX FILTER MAP GROUP 3) */\n#define BIT_MGTFLT15EN_FW_8822C BIT(15)\n#define BIT_MGTFLT14EN_FW_8822C BIT(14)\n#define BIT_MGTFLT13EN_FW_8822C BIT(13)\n#define BIT_MGTFLT12EN_FW_8822C BIT(12)\n#define BIT_MGTFLT11EN_FW_8822C BIT(11)\n#define BIT_MGTFLT10EN_FW_8822C BIT(10)\n#define BIT_MGTFLT9EN_FW_8822C BIT(9)\n#define BIT_MGTFLT8EN_FW_8822C BIT(8)\n#define BIT_MGTFLT7EN_FW_8822C BIT(7)\n#define BIT_MGTFLT6EN_FW_8822C BIT(6)\n#define BIT_MGTFLT5EN_FW_8822C BIT(5)\n#define BIT_MGTFLT4EN_FW_8822C BIT(4)\n#define BIT_MGTFLT3EN_FW_8822C BIT(3)\n#define BIT_MGTFLT2EN_FW_8822C BIT(2)\n#define BIT_MGTFLT1EN_FW_8822C BIT(1)\n#define BIT_MGTFLT0EN_FW_8822C BIT(0)\n\n/* 2 REG_RXFLTMAP4_8822C (RX FILTER MAP GROUP 4) */\n#define BIT_CTRLFLT15EN_FW_8822C BIT(15)\n#define BIT_CTRLFLT14EN_FW_8822C BIT(14)\n#define BIT_CTRLFLT13EN_FW_8822C BIT(13)\n#define BIT_CTRLFLT12EN_FW_8822C BIT(12)\n#define BIT_CTRLFLT11EN_FW_8822C BIT(11)\n#define BIT_CTRLFLT10EN_FW_8822C BIT(10)\n#define BIT_CTRLFLT9EN_FW_8822C BIT(9)\n#define BIT_CTRLFLT8EN_FW_8822C BIT(8)\n#define BIT_CTRLFLT7EN_FW_8822C BIT(7)\n#define BIT_CTRLFLT6EN_FW_8822C BIT(6)\n#define BIT_CTRLFLT5EN_FW_8822C BIT(5)\n#define BIT_CTRLFLT4EN_FW_8822C BIT(4)\n#define BIT_CTRLFLT3EN_FW_8822C BIT(3)\n#define BIT_CTRLFLT2EN_FW_8822C BIT(2)\n#define BIT_CTRLFLT1EN_FW_8822C BIT(1)\n#define BIT_CTRLFLT0EN_FW_8822C BIT(0)\n\n/* 2 REG_RXFLTMAP5_8822C (RX FILTER MAP GROUP 5) */\n#define BIT_DATAFLT15EN_FW_8822C BIT(15)\n#define BIT_DATAFLT14EN_FW_8822C BIT(14)\n#define BIT_DATAFLT13EN_FW_8822C BIT(13)\n#define BIT_DATAFLT12EN_FW_8822C BIT(12)\n#define BIT_DATAFLT11EN_FW_8822C BIT(11)\n#define BIT_DATAFLT10EN_FW_8822C BIT(10)\n#define BIT_DATAFLT9EN_FW_8822C BIT(9)\n#define BIT_DATAFLT8EN_FW_8822C BIT(8)\n#define BIT_DATAFLT7EN_FW_8822C BIT(7)\n#define BIT_DATAFLT6EN_FW_8822C BIT(6)\n#define BIT_DATAFLT5EN_FW_8822C BIT(5)\n#define BIT_DATAFLT4EN_FW_8822C BIT(4)\n#define BIT_DATAFLT3EN_FW_8822C BIT(3)\n#define BIT_DATAFLT2EN_FW_8822C BIT(2)\n#define BIT_DATAFLT1EN_FW_8822C BIT(1)\n#define BIT_DATAFLT0EN_FW_8822C BIT(0)\n\n/* 2 REG_RXFLTMAP6_8822C (RX FILTER MAP GROUP 6) */\n#define BIT_ACTIONFLT15EN_FW_8822C BIT(15)\n#define BIT_ACTIONFLT14EN_FW_8822C BIT(14)\n#define BIT_ACTIONFLT13EN_FW_8822C BIT(13)\n#define BIT_ACTIONFLT12EN_FW_8822C BIT(12)\n#define BIT_ACTIONFLT11EN_FW_8822C BIT(11)\n#define BIT_ACTIONFLT10EN_FW_8822C BIT(10)\n#define BIT_ACTIONFLT9EN_FW_8822C BIT(9)\n#define BIT_ACTIONFLT8EN_FW_8822C BIT(8)\n#define BIT_ACTIONFLT7EN_FW_8822C BIT(7)\n#define BIT_ACTIONFLT6EN_FW_8822C BIT(6)\n#define BIT_ACTIONFLT5EN_FW_8822C BIT(5)\n#define BIT_ACTIONFLT4EN_FW_8822C BIT(4)\n#define BIT_ACTIONFLT3EN_FW_8822C BIT(3)\n#define BIT_ACTIONFLT2EN_FW_8822C BIT(2)\n#define BIT_ACTIONFLT1EN_FW_8822C BIT(1)\n#define BIT_ACTIONFLT0EN_FW_8822C BIT(0)\n\n/* 2 REG_WOW_CTRL_8822C (WAKE ON WLAN CONTROL REGISTER) */\n\n#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C 6\n#define BIT_MASK_PSF_BSSIDSEL_B2B1_8822C 0x3\n#define BIT_PSF_BSSIDSEL_B2B1_8822C(x)                                         \\\n\t(((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822C)                              \\\n\t << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C)\n#define BITS_PSF_BSSIDSEL_B2B1_8822C                                           \\\n\t(BIT_MASK_PSF_BSSIDSEL_B2B1_8822C << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C)\n#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822C(x)                                   \\\n\t((x) & (~BITS_PSF_BSSIDSEL_B2B1_8822C))\n#define BIT_GET_PSF_BSSIDSEL_B2B1_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C) &                          \\\n\t BIT_MASK_PSF_BSSIDSEL_B2B1_8822C)\n#define BIT_SET_PSF_BSSIDSEL_B2B1_8822C(x, v)                                  \\\n\t(BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822C(x) | BIT_PSF_BSSIDSEL_B2B1_8822C(v))\n\n#define BIT_WOWHCI_8822C BIT(5)\n#define BIT_PSF_BSSIDSEL_B0_8822C BIT(4)\n#define BIT_UWF_8822C BIT(3)\n#define BIT_MAGIC_8822C BIT(2)\n#define BIT_WOWEN_8822C BIT(1)\n#define BIT_FORCE_WAKEUP_8822C BIT(0)\n\n/* 2 REG_NAN_RX_TSF_FILTER_8822C(NAN_RX_TSF_ADDRESS_FILTER) */\n#define BIT_CHK_TSF_TA_8822C BIT(2)\n#define BIT_CHK_TSF_CBSSID_8822C BIT(1)\n#define BIT_CHK_TSF_EN_8822C BIT(0)\n\n/* 2 REG_PS_RX_INFO_8822C (POWER SAVE RX INFORMATION REGISTER) */\n\n#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C 5\n#define BIT_MASK_PORTSEL__PS_RX_INFO_8822C 0x7\n#define BIT_PORTSEL__PS_RX_INFO_8822C(x)                                       \\\n\t(((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8822C)                            \\\n\t << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C)\n#define BITS_PORTSEL__PS_RX_INFO_8822C                                         \\\n\t(BIT_MASK_PORTSEL__PS_RX_INFO_8822C                                    \\\n\t << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C)\n#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8822C(x)                                 \\\n\t((x) & (~BITS_PORTSEL__PS_RX_INFO_8822C))\n#define BIT_GET_PORTSEL__PS_RX_INFO_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C) &                        \\\n\t BIT_MASK_PORTSEL__PS_RX_INFO_8822C)\n#define BIT_SET_PORTSEL__PS_RX_INFO_8822C(x, v)                                \\\n\t(BIT_CLEAR_PORTSEL__PS_RX_INFO_8822C(x) |                              \\\n\t BIT_PORTSEL__PS_RX_INFO_8822C(v))\n\n#define BIT_RXCTRLIN0_8822C BIT(4)\n#define BIT_RXMGTIN0_8822C BIT(3)\n#define BIT_RXDATAIN2_8822C BIT(2)\n#define BIT_RXDATAIN1_8822C BIT(1)\n#define BIT_RXDATAIN0_8822C BIT(0)\n\n/* 2 REG_WMMPS_UAPSD_TID_8822C (WMM POWER SAVE UAPSD TID REGISTER) */\n#define BIT_WMMPS_UAPSD_TID7_8822C BIT(7)\n#define BIT_WMMPS_UAPSD_TID6_8822C BIT(6)\n#define BIT_WMMPS_UAPSD_TID5_8822C BIT(5)\n#define BIT_WMMPS_UAPSD_TID4_8822C BIT(4)\n#define BIT_WMMPS_UAPSD_TID3_8822C BIT(3)\n#define BIT_WMMPS_UAPSD_TID2_8822C BIT(2)\n#define BIT_WMMPS_UAPSD_TID1_8822C BIT(1)\n#define BIT_WMMPS_UAPSD_TID0_8822C BIT(0)\n\n/* 2 REG_LPNAV_CTRL_8822C (LOW POWER NAV CONTROL REGISTER) */\n\n/* 2 REG_WKFMCAM_CMD_8822C (WAKEUP FRAME CAM COMMAND REGISTER) */\n#define BIT_WKFCAM_POLLING_V1_8822C BIT(31)\n#define BIT_WKFCAM_CLR_V1_8822C BIT(30)\n#define BIT_WKFCAM_WE_8822C BIT(16)\n\n#define BIT_SHIFT_WKFCAM_ADDR_V2_8822C 8\n#define BIT_MASK_WKFCAM_ADDR_V2_8822C 0xff\n#define BIT_WKFCAM_ADDR_V2_8822C(x)                                            \\\n\t(((x) & BIT_MASK_WKFCAM_ADDR_V2_8822C)                                 \\\n\t << BIT_SHIFT_WKFCAM_ADDR_V2_8822C)\n#define BITS_WKFCAM_ADDR_V2_8822C                                              \\\n\t(BIT_MASK_WKFCAM_ADDR_V2_8822C << BIT_SHIFT_WKFCAM_ADDR_V2_8822C)\n#define BIT_CLEAR_WKFCAM_ADDR_V2_8822C(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8822C))\n#define BIT_GET_WKFCAM_ADDR_V2_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8822C) &                             \\\n\t BIT_MASK_WKFCAM_ADDR_V2_8822C)\n#define BIT_SET_WKFCAM_ADDR_V2_8822C(x, v)                                     \\\n\t(BIT_CLEAR_WKFCAM_ADDR_V2_8822C(x) | BIT_WKFCAM_ADDR_V2_8822C(v))\n\n#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C 0\n#define BIT_MASK_WKFCAM_CAM_NUM_V1_8822C 0xff\n#define BIT_WKFCAM_CAM_NUM_V1_8822C(x)                                         \\\n\t(((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822C)                              \\\n\t << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C)\n#define BITS_WKFCAM_CAM_NUM_V1_8822C                                           \\\n\t(BIT_MASK_WKFCAM_CAM_NUM_V1_8822C << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C)\n#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822C(x)                                   \\\n\t((x) & (~BITS_WKFCAM_CAM_NUM_V1_8822C))\n#define BIT_GET_WKFCAM_CAM_NUM_V1_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C) &                          \\\n\t BIT_MASK_WKFCAM_CAM_NUM_V1_8822C)\n#define BIT_SET_WKFCAM_CAM_NUM_V1_8822C(x, v)                                  \\\n\t(BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822C(x) | BIT_WKFCAM_CAM_NUM_V1_8822C(v))\n\n/* 2 REG_WKFMCAM_RWD_8822C (WAKEUP FRAME READ/WRITE DATA) */\n\n#define BIT_SHIFT_WKFMCAM_RWD_8822C 0\n#define BIT_MASK_WKFMCAM_RWD_8822C 0xffffffffL\n#define BIT_WKFMCAM_RWD_8822C(x)                                               \\\n\t(((x) & BIT_MASK_WKFMCAM_RWD_8822C) << BIT_SHIFT_WKFMCAM_RWD_8822C)\n#define BITS_WKFMCAM_RWD_8822C                                                 \\\n\t(BIT_MASK_WKFMCAM_RWD_8822C << BIT_SHIFT_WKFMCAM_RWD_8822C)\n#define BIT_CLEAR_WKFMCAM_RWD_8822C(x) ((x) & (~BITS_WKFMCAM_RWD_8822C))\n#define BIT_GET_WKFMCAM_RWD_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_WKFMCAM_RWD_8822C) & BIT_MASK_WKFMCAM_RWD_8822C)\n#define BIT_SET_WKFMCAM_RWD_8822C(x, v)                                        \\\n\t(BIT_CLEAR_WKFMCAM_RWD_8822C(x) | BIT_WKFMCAM_RWD_8822C(v))\n\n/* 2 REG_RXFLTMAP0_8822C (RX FILTER MAP GROUP 0) */\n#define BIT_MGTFLT15EN_8822C BIT(15)\n#define BIT_MGTFLT14EN_8822C BIT(14)\n#define BIT_MGTFLT13EN_8822C BIT(13)\n#define BIT_MGTFLT12EN_8822C BIT(12)\n#define BIT_MGTFLT11EN_8822C BIT(11)\n#define BIT_MGTFLT10EN_8822C BIT(10)\n#define BIT_MGTFLT9EN_8822C BIT(9)\n#define BIT_MGTFLT8EN_8822C BIT(8)\n#define BIT_MGTFLT7EN_8822C BIT(7)\n#define BIT_MGTFLT6EN_8822C BIT(6)\n#define BIT_MGTFLT5EN_8822C BIT(5)\n#define BIT_MGTFLT4EN_8822C BIT(4)\n#define BIT_MGTFLT3EN_8822C BIT(3)\n#define BIT_MGTFLT2EN_8822C BIT(2)\n#define BIT_MGTFLT1EN_8822C BIT(1)\n#define BIT_MGTFLT0EN_8822C BIT(0)\n\n/* 2 REG_RXFLTMAP1_8822C (RX FILTER MAP GROUP 1) */\n#define BIT_CTRLFLT15EN_8822C BIT(15)\n#define BIT_CTRLFLT14EN_8822C BIT(14)\n#define BIT_CTRLFLT13EN_8822C BIT(13)\n#define BIT_CTRLFLT12EN_8822C BIT(12)\n#define BIT_CTRLFLT11EN_8822C BIT(11)\n#define BIT_CTRLFLT10EN_8822C BIT(10)\n#define BIT_CTRLFLT9EN_8822C BIT(9)\n#define BIT_CTRLFLT8EN_8822C BIT(8)\n#define BIT_CTRLFLT7EN_8822C BIT(7)\n#define BIT_CTRLFLT6EN_8822C BIT(6)\n#define BIT_CTRLFLT5EN_8822C BIT(5)\n#define BIT_CTRLFLT4EN_8822C BIT(4)\n#define BIT_CTRLFLT3EN_8822C BIT(3)\n#define BIT_CTRLFLT2EN_8822C BIT(2)\n#define BIT_CTRLFLT1EN_8822C BIT(1)\n#define BIT_CTRLFLT0EN_8822C BIT(0)\n\n/* 2 REG_RXFLTMAP2_8822C (RX FILTER MAP GROUP 2) */\n#define BIT_DATAFLT15EN_8822C BIT(15)\n#define BIT_DATAFLT14EN_8822C BIT(14)\n#define BIT_DATAFLT13EN_8822C BIT(13)\n#define BIT_DATAFLT12EN_8822C BIT(12)\n#define BIT_DATAFLT11EN_8822C BIT(11)\n#define BIT_DATAFLT10EN_8822C BIT(10)\n#define BIT_DATAFLT9EN_8822C BIT(9)\n#define BIT_DATAFLT8EN_8822C BIT(8)\n#define BIT_DATAFLT7EN_8822C BIT(7)\n#define BIT_DATAFLT6EN_8822C BIT(6)\n#define BIT_DATAFLT5EN_8822C BIT(5)\n#define BIT_DATAFLT4EN_8822C BIT(4)\n#define BIT_DATAFLT3EN_8822C BIT(3)\n#define BIT_DATAFLT2EN_8822C BIT(2)\n#define BIT_DATAFLT1EN_8822C BIT(1)\n#define BIT_DATAFLT0EN_8822C BIT(0)\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_BCN_PSR_RPT_8822C (BEACON PARSER REPORT REGISTER) */\n\n#define BIT_SHIFT_DTIM_CNT_8822C 24\n#define BIT_MASK_DTIM_CNT_8822C 0xff\n#define BIT_DTIM_CNT_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_DTIM_CNT_8822C) << BIT_SHIFT_DTIM_CNT_8822C)\n#define BITS_DTIM_CNT_8822C                                                    \\\n\t(BIT_MASK_DTIM_CNT_8822C << BIT_SHIFT_DTIM_CNT_8822C)\n#define BIT_CLEAR_DTIM_CNT_8822C(x) ((x) & (~BITS_DTIM_CNT_8822C))\n#define BIT_GET_DTIM_CNT_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT_8822C) & BIT_MASK_DTIM_CNT_8822C)\n#define BIT_SET_DTIM_CNT_8822C(x, v)                                           \\\n\t(BIT_CLEAR_DTIM_CNT_8822C(x) | BIT_DTIM_CNT_8822C(v))\n\n#define BIT_SHIFT_DTIM_PERIOD_8822C 16\n#define BIT_MASK_DTIM_PERIOD_8822C 0xff\n#define BIT_DTIM_PERIOD_8822C(x)                                               \\\n\t(((x) & BIT_MASK_DTIM_PERIOD_8822C) << BIT_SHIFT_DTIM_PERIOD_8822C)\n#define BITS_DTIM_PERIOD_8822C                                                 \\\n\t(BIT_MASK_DTIM_PERIOD_8822C << BIT_SHIFT_DTIM_PERIOD_8822C)\n#define BIT_CLEAR_DTIM_PERIOD_8822C(x) ((x) & (~BITS_DTIM_PERIOD_8822C))\n#define BIT_GET_DTIM_PERIOD_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD_8822C) & BIT_MASK_DTIM_PERIOD_8822C)\n#define BIT_SET_DTIM_PERIOD_8822C(x, v)                                        \\\n\t(BIT_CLEAR_DTIM_PERIOD_8822C(x) | BIT_DTIM_PERIOD_8822C(v))\n\n#define BIT_DTIM_8822C BIT(15)\n#define BIT_TIM_8822C BIT(14)\n#define BIT_RPT_VALID_8822C BIT(13)\n\n#define BIT_SHIFT_PS_AID_0_8822C 0\n#define BIT_MASK_PS_AID_0_8822C 0x7ff\n#define BIT_PS_AID_0_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_0_8822C) << BIT_SHIFT_PS_AID_0_8822C)\n#define BITS_PS_AID_0_8822C                                                    \\\n\t(BIT_MASK_PS_AID_0_8822C << BIT_SHIFT_PS_AID_0_8822C)\n#define BIT_CLEAR_PS_AID_0_8822C(x) ((x) & (~BITS_PS_AID_0_8822C))\n#define BIT_GET_PS_AID_0_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_0_8822C) & BIT_MASK_PS_AID_0_8822C)\n#define BIT_SET_PS_AID_0_8822C(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_0_8822C(x) | BIT_PS_AID_0_8822C(v))\n\n/* 2 REG_FLC_RPC_8822C (FW LPS CONDITION -- RX PKT COUNTER) */\n\n#define BIT_SHIFT_FLC_RPC_8822C 0\n#define BIT_MASK_FLC_RPC_8822C 0xff\n#define BIT_FLC_RPC_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_FLC_RPC_8822C) << BIT_SHIFT_FLC_RPC_8822C)\n#define BITS_FLC_RPC_8822C (BIT_MASK_FLC_RPC_8822C << BIT_SHIFT_FLC_RPC_8822C)\n#define BIT_CLEAR_FLC_RPC_8822C(x) ((x) & (~BITS_FLC_RPC_8822C))\n#define BIT_GET_FLC_RPC_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_FLC_RPC_8822C) & BIT_MASK_FLC_RPC_8822C)\n#define BIT_SET_FLC_RPC_8822C(x, v)                                            \\\n\t(BIT_CLEAR_FLC_RPC_8822C(x) | BIT_FLC_RPC_8822C(v))\n\n/* 2 REG_FLC_RPCT_8822C (FLC_RPC THRESHOLD) */\n\n#define BIT_SHIFT_FLC_RPCT_8822C 0\n#define BIT_MASK_FLC_RPCT_8822C 0xff\n#define BIT_FLC_RPCT_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_FLC_RPCT_8822C) << BIT_SHIFT_FLC_RPCT_8822C)\n#define BITS_FLC_RPCT_8822C                                                    \\\n\t(BIT_MASK_FLC_RPCT_8822C << BIT_SHIFT_FLC_RPCT_8822C)\n#define BIT_CLEAR_FLC_RPCT_8822C(x) ((x) & (~BITS_FLC_RPCT_8822C))\n#define BIT_GET_FLC_RPCT_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_FLC_RPCT_8822C) & BIT_MASK_FLC_RPCT_8822C)\n#define BIT_SET_FLC_RPCT_8822C(x, v)                                           \\\n\t(BIT_CLEAR_FLC_RPCT_8822C(x) | BIT_FLC_RPCT_8822C(v))\n\n/* 2 REG_FLC_PTS_8822C (PKT TYPE SELECTION OF FLC_RPC T) */\n#define BIT_CMF_8822C BIT(2)\n#define BIT_CCF_8822C BIT(1)\n#define BIT_CDF_8822C BIT(0)\n\n/* 2 REG_FLC_TRPC_8822C (TIMER OF FLC_RPC) */\n#define BIT_FLC_RPCT_V1_8822C BIT(7)\n#define BIT_MODE_8822C BIT(6)\n\n#define BIT_SHIFT_TRPCD_8822C 0\n#define BIT_MASK_TRPCD_8822C 0x3f\n#define BIT_TRPCD_8822C(x)                                                     \\\n\t(((x) & BIT_MASK_TRPCD_8822C) << BIT_SHIFT_TRPCD_8822C)\n#define BITS_TRPCD_8822C (BIT_MASK_TRPCD_8822C << BIT_SHIFT_TRPCD_8822C)\n#define BIT_CLEAR_TRPCD_8822C(x) ((x) & (~BITS_TRPCD_8822C))\n#define BIT_GET_TRPCD_8822C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TRPCD_8822C) & BIT_MASK_TRPCD_8822C)\n#define BIT_SET_TRPCD_8822C(x, v)                                              \\\n\t(BIT_CLEAR_TRPCD_8822C(x) | BIT_TRPCD_8822C(v))\n\n/* 2 REG_RXPKTMON_CTRL_8822C */\n\n#define BIT_SHIFT_RXBKQPKT_SEQ_8822C 20\n#define BIT_MASK_RXBKQPKT_SEQ_8822C 0xf\n#define BIT_RXBKQPKT_SEQ_8822C(x)                                              \\\n\t(((x) & BIT_MASK_RXBKQPKT_SEQ_8822C) << BIT_SHIFT_RXBKQPKT_SEQ_8822C)\n#define BITS_RXBKQPKT_SEQ_8822C                                                \\\n\t(BIT_MASK_RXBKQPKT_SEQ_8822C << BIT_SHIFT_RXBKQPKT_SEQ_8822C)\n#define BIT_CLEAR_RXBKQPKT_SEQ_8822C(x) ((x) & (~BITS_RXBKQPKT_SEQ_8822C))\n#define BIT_GET_RXBKQPKT_SEQ_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8822C) & BIT_MASK_RXBKQPKT_SEQ_8822C)\n#define BIT_SET_RXBKQPKT_SEQ_8822C(x, v)                                       \\\n\t(BIT_CLEAR_RXBKQPKT_SEQ_8822C(x) | BIT_RXBKQPKT_SEQ_8822C(v))\n\n#define BIT_SHIFT_RXBEQPKT_SEQ_8822C 16\n#define BIT_MASK_RXBEQPKT_SEQ_8822C 0xf\n#define BIT_RXBEQPKT_SEQ_8822C(x)                                              \\\n\t(((x) & BIT_MASK_RXBEQPKT_SEQ_8822C) << BIT_SHIFT_RXBEQPKT_SEQ_8822C)\n#define BITS_RXBEQPKT_SEQ_8822C                                                \\\n\t(BIT_MASK_RXBEQPKT_SEQ_8822C << BIT_SHIFT_RXBEQPKT_SEQ_8822C)\n#define BIT_CLEAR_RXBEQPKT_SEQ_8822C(x) ((x) & (~BITS_RXBEQPKT_SEQ_8822C))\n#define BIT_GET_RXBEQPKT_SEQ_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8822C) & BIT_MASK_RXBEQPKT_SEQ_8822C)\n#define BIT_SET_RXBEQPKT_SEQ_8822C(x, v)                                       \\\n\t(BIT_CLEAR_RXBEQPKT_SEQ_8822C(x) | BIT_RXBEQPKT_SEQ_8822C(v))\n\n#define BIT_SHIFT_RXVIQPKT_SEQ_8822C 12\n#define BIT_MASK_RXVIQPKT_SEQ_8822C 0xf\n#define BIT_RXVIQPKT_SEQ_8822C(x)                                              \\\n\t(((x) & BIT_MASK_RXVIQPKT_SEQ_8822C) << BIT_SHIFT_RXVIQPKT_SEQ_8822C)\n#define BITS_RXVIQPKT_SEQ_8822C                                                \\\n\t(BIT_MASK_RXVIQPKT_SEQ_8822C << BIT_SHIFT_RXVIQPKT_SEQ_8822C)\n#define BIT_CLEAR_RXVIQPKT_SEQ_8822C(x) ((x) & (~BITS_RXVIQPKT_SEQ_8822C))\n#define BIT_GET_RXVIQPKT_SEQ_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8822C) & BIT_MASK_RXVIQPKT_SEQ_8822C)\n#define BIT_SET_RXVIQPKT_SEQ_8822C(x, v)                                       \\\n\t(BIT_CLEAR_RXVIQPKT_SEQ_8822C(x) | BIT_RXVIQPKT_SEQ_8822C(v))\n\n#define BIT_SHIFT_RXVOQPKT_SEQ_8822C 8\n#define BIT_MASK_RXVOQPKT_SEQ_8822C 0xf\n#define BIT_RXVOQPKT_SEQ_8822C(x)                                              \\\n\t(((x) & BIT_MASK_RXVOQPKT_SEQ_8822C) << BIT_SHIFT_RXVOQPKT_SEQ_8822C)\n#define BITS_RXVOQPKT_SEQ_8822C                                                \\\n\t(BIT_MASK_RXVOQPKT_SEQ_8822C << BIT_SHIFT_RXVOQPKT_SEQ_8822C)\n#define BIT_CLEAR_RXVOQPKT_SEQ_8822C(x) ((x) & (~BITS_RXVOQPKT_SEQ_8822C))\n#define BIT_GET_RXVOQPKT_SEQ_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8822C) & BIT_MASK_RXVOQPKT_SEQ_8822C)\n#define BIT_SET_RXVOQPKT_SEQ_8822C(x, v)                                       \\\n\t(BIT_CLEAR_RXVOQPKT_SEQ_8822C(x) | BIT_RXVOQPKT_SEQ_8822C(v))\n\n#define BIT_RXBKQPKT_ERR_8822C BIT(7)\n#define BIT_RXBEQPKT_ERR_8822C BIT(6)\n#define BIT_RXVIQPKT_ERR_8822C BIT(5)\n#define BIT_RXVOQPKT_ERR_8822C BIT(4)\n#define BIT_RXDMA_MON_EN_8822C BIT(2)\n#define BIT_RXPKT_MON_RST_8822C BIT(1)\n#define BIT_RXPKT_MON_EN_8822C BIT(0)\n\n/* 2 REG_STATE_MON_8822C */\n\n#define BIT_SHIFT_STATE_SEL_8822C 24\n#define BIT_MASK_STATE_SEL_8822C 0x1f\n#define BIT_STATE_SEL_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_STATE_SEL_8822C) << BIT_SHIFT_STATE_SEL_8822C)\n#define BITS_STATE_SEL_8822C                                                   \\\n\t(BIT_MASK_STATE_SEL_8822C << BIT_SHIFT_STATE_SEL_8822C)\n#define BIT_CLEAR_STATE_SEL_8822C(x) ((x) & (~BITS_STATE_SEL_8822C))\n#define BIT_GET_STATE_SEL_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_STATE_SEL_8822C) & BIT_MASK_STATE_SEL_8822C)\n#define BIT_SET_STATE_SEL_8822C(x, v)                                          \\\n\t(BIT_CLEAR_STATE_SEL_8822C(x) | BIT_STATE_SEL_8822C(v))\n\n#define BIT_SHIFT_STATE_INFO_8822C 8\n#define BIT_MASK_STATE_INFO_8822C 0xff\n#define BIT_STATE_INFO_8822C(x)                                                \\\n\t(((x) & BIT_MASK_STATE_INFO_8822C) << BIT_SHIFT_STATE_INFO_8822C)\n#define BITS_STATE_INFO_8822C                                                  \\\n\t(BIT_MASK_STATE_INFO_8822C << BIT_SHIFT_STATE_INFO_8822C)\n#define BIT_CLEAR_STATE_INFO_8822C(x) ((x) & (~BITS_STATE_INFO_8822C))\n#define BIT_GET_STATE_INFO_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_STATE_INFO_8822C) & BIT_MASK_STATE_INFO_8822C)\n#define BIT_SET_STATE_INFO_8822C(x, v)                                         \\\n\t(BIT_CLEAR_STATE_INFO_8822C(x) | BIT_STATE_INFO_8822C(v))\n\n#define BIT_UPD_NXT_STATE_8822C BIT(7)\n\n#define BIT_SHIFT_CUR_STATE_8822C 0\n#define BIT_MASK_CUR_STATE_8822C 0x7f\n#define BIT_CUR_STATE_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_CUR_STATE_8822C) << BIT_SHIFT_CUR_STATE_8822C)\n#define BITS_CUR_STATE_8822C                                                   \\\n\t(BIT_MASK_CUR_STATE_8822C << BIT_SHIFT_CUR_STATE_8822C)\n#define BIT_CLEAR_CUR_STATE_8822C(x) ((x) & (~BITS_CUR_STATE_8822C))\n#define BIT_GET_CUR_STATE_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_CUR_STATE_8822C) & BIT_MASK_CUR_STATE_8822C)\n#define BIT_SET_CUR_STATE_8822C(x, v)                                          \\\n\t(BIT_CLEAR_CUR_STATE_8822C(x) | BIT_CUR_STATE_8822C(v))\n\n/* 2 REG_ERROR_MON_8822C */\n#define BIT_CSIRPT_LEN_BB_MORE_THAN_MAC_8822C BIT(23)\n#define BIT_CSI_CHKSUM_ERROR_8822C BIT(22)\n#define BIT_MACRX_ERR_4_8822C BIT(20)\n#define BIT_MACRX_ERR_3_8822C BIT(19)\n#define BIT_MACRX_ERR_2_8822C BIT(18)\n#define BIT_MACRX_ERR_1_8822C BIT(17)\n#define BIT_MACRX_ERR_0_8822C BIT(16)\n#define BIT_WMAC_PRETX_ERRHDL_EN_8822C BIT(15)\n#define BIT_MACTX_ERR_5_8822C BIT(5)\n#define BIT_MACTX_ERR_4_8822C BIT(4)\n#define BIT_MACTX_ERR_3_8822C BIT(3)\n#define BIT_MACTX_ERR_2_8822C BIT(2)\n#define BIT_MACTX_ERR_1_8822C BIT(1)\n#define BIT_MACTX_ERR_0_8822C BIT(0)\n\n/* 2 REG_SEARCH_MACID_8822C */\n#define BIT_EN_TXRPTBUF_CLK_8822C BIT(31)\n\n#define BIT_SHIFT_INFO_INDEX_OFFSET_8822C 16\n#define BIT_MASK_INFO_INDEX_OFFSET_8822C 0x1fff\n#define BIT_INFO_INDEX_OFFSET_8822C(x)                                         \\\n\t(((x) & BIT_MASK_INFO_INDEX_OFFSET_8822C)                              \\\n\t << BIT_SHIFT_INFO_INDEX_OFFSET_8822C)\n#define BITS_INFO_INDEX_OFFSET_8822C                                           \\\n\t(BIT_MASK_INFO_INDEX_OFFSET_8822C << BIT_SHIFT_INFO_INDEX_OFFSET_8822C)\n#define BIT_CLEAR_INFO_INDEX_OFFSET_8822C(x)                                   \\\n\t((x) & (~BITS_INFO_INDEX_OFFSET_8822C))\n#define BIT_GET_INFO_INDEX_OFFSET_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8822C) &                          \\\n\t BIT_MASK_INFO_INDEX_OFFSET_8822C)\n#define BIT_SET_INFO_INDEX_OFFSET_8822C(x, v)                                  \\\n\t(BIT_CLEAR_INFO_INDEX_OFFSET_8822C(x) | BIT_INFO_INDEX_OFFSET_8822C(v))\n\n#define BIT_WMAC_SRCH_FIFOFULL_8822C BIT(15)\n#define BIT_DIS_INFOSRCH_8822C BIT(14)\n\n#define BIT_SHIFT_INFO_ADDR_OFFSET_8822C 0\n#define BIT_MASK_INFO_ADDR_OFFSET_8822C 0x1fff\n#define BIT_INFO_ADDR_OFFSET_8822C(x)                                          \\\n\t(((x) & BIT_MASK_INFO_ADDR_OFFSET_8822C)                               \\\n\t << BIT_SHIFT_INFO_ADDR_OFFSET_8822C)\n#define BITS_INFO_ADDR_OFFSET_8822C                                            \\\n\t(BIT_MASK_INFO_ADDR_OFFSET_8822C << BIT_SHIFT_INFO_ADDR_OFFSET_8822C)\n#define BIT_CLEAR_INFO_ADDR_OFFSET_8822C(x)                                    \\\n\t((x) & (~BITS_INFO_ADDR_OFFSET_8822C))\n#define BIT_GET_INFO_ADDR_OFFSET_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8822C) &                           \\\n\t BIT_MASK_INFO_ADDR_OFFSET_8822C)\n#define BIT_SET_INFO_ADDR_OFFSET_8822C(x, v)                                   \\\n\t(BIT_CLEAR_INFO_ADDR_OFFSET_8822C(x) | BIT_INFO_ADDR_OFFSET_8822C(v))\n\n/* 2 REG_BT_COEX_TABLE_8822C (BT-COEXISTENCE CONTROL REGISTER) */\n\n#define BIT_SHIFT_COEX_TABLE_1_8822C 0\n#define BIT_MASK_COEX_TABLE_1_8822C 0xffffffffL\n#define BIT_COEX_TABLE_1_8822C(x)                                              \\\n\t(((x) & BIT_MASK_COEX_TABLE_1_8822C) << BIT_SHIFT_COEX_TABLE_1_8822C)\n#define BITS_COEX_TABLE_1_8822C                                                \\\n\t(BIT_MASK_COEX_TABLE_1_8822C << BIT_SHIFT_COEX_TABLE_1_8822C)\n#define BIT_CLEAR_COEX_TABLE_1_8822C(x) ((x) & (~BITS_COEX_TABLE_1_8822C))\n#define BIT_GET_COEX_TABLE_1_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_COEX_TABLE_1_8822C) & BIT_MASK_COEX_TABLE_1_8822C)\n#define BIT_SET_COEX_TABLE_1_8822C(x, v)                                       \\\n\t(BIT_CLEAR_COEX_TABLE_1_8822C(x) | BIT_COEX_TABLE_1_8822C(v))\n\n/* 2 REG_BT_COEX_TABLE2_8822C (BT-COEXISTENCE CONTROL REGISTER) */\n\n#define BIT_SHIFT_COEX_TABLE_2_8822C 0\n#define BIT_MASK_COEX_TABLE_2_8822C 0xffffffffL\n#define BIT_COEX_TABLE_2_8822C(x)                                              \\\n\t(((x) & BIT_MASK_COEX_TABLE_2_8822C) << BIT_SHIFT_COEX_TABLE_2_8822C)\n#define BITS_COEX_TABLE_2_8822C                                                \\\n\t(BIT_MASK_COEX_TABLE_2_8822C << BIT_SHIFT_COEX_TABLE_2_8822C)\n#define BIT_CLEAR_COEX_TABLE_2_8822C(x) ((x) & (~BITS_COEX_TABLE_2_8822C))\n#define BIT_GET_COEX_TABLE_2_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_COEX_TABLE_2_8822C) & BIT_MASK_COEX_TABLE_2_8822C)\n#define BIT_SET_COEX_TABLE_2_8822C(x, v)                                       \\\n\t(BIT_CLEAR_COEX_TABLE_2_8822C(x) | BIT_COEX_TABLE_2_8822C(v))\n\n/* 2 REG_BT_COEX_BREAK_TABLE_8822C (BT-COEXISTENCE CONTROL REGISTER) */\n\n#define BIT_SHIFT_BREAK_TABLE_2_8822C 16\n#define BIT_MASK_BREAK_TABLE_2_8822C 0xffff\n#define BIT_BREAK_TABLE_2_8822C(x)                                             \\\n\t(((x) & BIT_MASK_BREAK_TABLE_2_8822C) << BIT_SHIFT_BREAK_TABLE_2_8822C)\n#define BITS_BREAK_TABLE_2_8822C                                               \\\n\t(BIT_MASK_BREAK_TABLE_2_8822C << BIT_SHIFT_BREAK_TABLE_2_8822C)\n#define BIT_CLEAR_BREAK_TABLE_2_8822C(x) ((x) & (~BITS_BREAK_TABLE_2_8822C))\n#define BIT_GET_BREAK_TABLE_2_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BREAK_TABLE_2_8822C) & BIT_MASK_BREAK_TABLE_2_8822C)\n#define BIT_SET_BREAK_TABLE_2_8822C(x, v)                                      \\\n\t(BIT_CLEAR_BREAK_TABLE_2_8822C(x) | BIT_BREAK_TABLE_2_8822C(v))\n\n#define BIT_SHIFT_BREAK_TABLE_1_8822C 0\n#define BIT_MASK_BREAK_TABLE_1_8822C 0xffff\n#define BIT_BREAK_TABLE_1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_BREAK_TABLE_1_8822C) << BIT_SHIFT_BREAK_TABLE_1_8822C)\n#define BITS_BREAK_TABLE_1_8822C                                               \\\n\t(BIT_MASK_BREAK_TABLE_1_8822C << BIT_SHIFT_BREAK_TABLE_1_8822C)\n#define BIT_CLEAR_BREAK_TABLE_1_8822C(x) ((x) & (~BITS_BREAK_TABLE_1_8822C))\n#define BIT_GET_BREAK_TABLE_1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BREAK_TABLE_1_8822C) & BIT_MASK_BREAK_TABLE_1_8822C)\n#define BIT_SET_BREAK_TABLE_1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_BREAK_TABLE_1_8822C(x) | BIT_BREAK_TABLE_1_8822C(v))\n\n/* 2 REG_BT_COEX_TABLE_H_8822C (BT-COEXISTENCE CONTROL REGISTER) */\n#define BIT_PRI_MASK_RX_RESP_V1_8822C BIT(30)\n#define BIT_PRI_MASK_RXOFDM_V1_8822C BIT(29)\n#define BIT_PRI_MASK_RXCCK_V1_8822C BIT(28)\n\n#define BIT_SHIFT_PRI_MASK_TXAC_8822C 21\n#define BIT_MASK_PRI_MASK_TXAC_8822C 0x7f\n#define BIT_PRI_MASK_TXAC_8822C(x)                                             \\\n\t(((x) & BIT_MASK_PRI_MASK_TXAC_8822C) << BIT_SHIFT_PRI_MASK_TXAC_8822C)\n#define BITS_PRI_MASK_TXAC_8822C                                               \\\n\t(BIT_MASK_PRI_MASK_TXAC_8822C << BIT_SHIFT_PRI_MASK_TXAC_8822C)\n#define BIT_CLEAR_PRI_MASK_TXAC_8822C(x) ((x) & (~BITS_PRI_MASK_TXAC_8822C))\n#define BIT_GET_PRI_MASK_TXAC_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_TXAC_8822C) & BIT_MASK_PRI_MASK_TXAC_8822C)\n#define BIT_SET_PRI_MASK_TXAC_8822C(x, v)                                      \\\n\t(BIT_CLEAR_PRI_MASK_TXAC_8822C(x) | BIT_PRI_MASK_TXAC_8822C(v))\n\n#define BIT_SHIFT_PRI_MASK_NAV_8822C 13\n#define BIT_MASK_PRI_MASK_NAV_8822C 0xff\n#define BIT_PRI_MASK_NAV_8822C(x)                                              \\\n\t(((x) & BIT_MASK_PRI_MASK_NAV_8822C) << BIT_SHIFT_PRI_MASK_NAV_8822C)\n#define BITS_PRI_MASK_NAV_8822C                                                \\\n\t(BIT_MASK_PRI_MASK_NAV_8822C << BIT_SHIFT_PRI_MASK_NAV_8822C)\n#define BIT_CLEAR_PRI_MASK_NAV_8822C(x) ((x) & (~BITS_PRI_MASK_NAV_8822C))\n#define BIT_GET_PRI_MASK_NAV_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_NAV_8822C) & BIT_MASK_PRI_MASK_NAV_8822C)\n#define BIT_SET_PRI_MASK_NAV_8822C(x, v)                                       \\\n\t(BIT_CLEAR_PRI_MASK_NAV_8822C(x) | BIT_PRI_MASK_NAV_8822C(v))\n\n#define BIT_PRI_MASK_CCK_V1_8822C BIT(12)\n#define BIT_PRI_MASK_OFDM_V1_8822C BIT(11)\n#define BIT_PRI_MASK_RTY_V1_8822C BIT(10)\n\n#define BIT_SHIFT_PRI_MASK_NUM_8822C 6\n#define BIT_MASK_PRI_MASK_NUM_8822C 0xf\n#define BIT_PRI_MASK_NUM_8822C(x)                                              \\\n\t(((x) & BIT_MASK_PRI_MASK_NUM_8822C) << BIT_SHIFT_PRI_MASK_NUM_8822C)\n#define BITS_PRI_MASK_NUM_8822C                                                \\\n\t(BIT_MASK_PRI_MASK_NUM_8822C << BIT_SHIFT_PRI_MASK_NUM_8822C)\n#define BIT_CLEAR_PRI_MASK_NUM_8822C(x) ((x) & (~BITS_PRI_MASK_NUM_8822C))\n#define BIT_GET_PRI_MASK_NUM_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_NUM_8822C) & BIT_MASK_PRI_MASK_NUM_8822C)\n#define BIT_SET_PRI_MASK_NUM_8822C(x, v)                                       \\\n\t(BIT_CLEAR_PRI_MASK_NUM_8822C(x) | BIT_PRI_MASK_NUM_8822C(v))\n\n#define BIT_SHIFT_PRI_MASK_TYPE_8822C 2\n#define BIT_MASK_PRI_MASK_TYPE_8822C 0xf\n#define BIT_PRI_MASK_TYPE_8822C(x)                                             \\\n\t(((x) & BIT_MASK_PRI_MASK_TYPE_8822C) << BIT_SHIFT_PRI_MASK_TYPE_8822C)\n#define BITS_PRI_MASK_TYPE_8822C                                               \\\n\t(BIT_MASK_PRI_MASK_TYPE_8822C << BIT_SHIFT_PRI_MASK_TYPE_8822C)\n#define BIT_CLEAR_PRI_MASK_TYPE_8822C(x) ((x) & (~BITS_PRI_MASK_TYPE_8822C))\n#define BIT_GET_PRI_MASK_TYPE_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PRI_MASK_TYPE_8822C) & BIT_MASK_PRI_MASK_TYPE_8822C)\n#define BIT_SET_PRI_MASK_TYPE_8822C(x, v)                                      \\\n\t(BIT_CLEAR_PRI_MASK_TYPE_8822C(x) | BIT_PRI_MASK_TYPE_8822C(v))\n\n#define BIT_OOB_V1_8822C BIT(1)\n#define BIT_ANT_SEL_V1_8822C BIT(0)\n\n/* 2 REG_RXCMD_0_8822C */\n#define BIT_RXCMD_EN_8822C BIT(31)\n\n#define BIT_SHIFT_RXCMD_INFO_8822C 0\n#define BIT_MASK_RXCMD_INFO_8822C 0x7fffffffL\n#define BIT_RXCMD_INFO_8822C(x)                                                \\\n\t(((x) & BIT_MASK_RXCMD_INFO_8822C) << BIT_SHIFT_RXCMD_INFO_8822C)\n#define BITS_RXCMD_INFO_8822C                                                  \\\n\t(BIT_MASK_RXCMD_INFO_8822C << BIT_SHIFT_RXCMD_INFO_8822C)\n#define BIT_CLEAR_RXCMD_INFO_8822C(x) ((x) & (~BITS_RXCMD_INFO_8822C))\n#define BIT_GET_RXCMD_INFO_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_RXCMD_INFO_8822C) & BIT_MASK_RXCMD_INFO_8822C)\n#define BIT_SET_RXCMD_INFO_8822C(x, v)                                         \\\n\t(BIT_CLEAR_RXCMD_INFO_8822C(x) | BIT_RXCMD_INFO_8822C(v))\n\n/* 2 REG_RXCMD_1_8822C */\n\n#define BIT_SHIFT_RXCMD_PRD_8822C 0\n#define BIT_MASK_RXCMD_PRD_8822C 0xffff\n#define BIT_RXCMD_PRD_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_RXCMD_PRD_8822C) << BIT_SHIFT_RXCMD_PRD_8822C)\n#define BITS_RXCMD_PRD_8822C                                                   \\\n\t(BIT_MASK_RXCMD_PRD_8822C << BIT_SHIFT_RXCMD_PRD_8822C)\n#define BIT_CLEAR_RXCMD_PRD_8822C(x) ((x) & (~BITS_RXCMD_PRD_8822C))\n#define BIT_GET_RXCMD_PRD_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_RXCMD_PRD_8822C) & BIT_MASK_RXCMD_PRD_8822C)\n#define BIT_SET_RXCMD_PRD_8822C(x, v)                                          \\\n\t(BIT_CLEAR_RXCMD_PRD_8822C(x) | BIT_RXCMD_PRD_8822C(v))\n\n/* 2 REG_WMAC_RESP_TXINFO_8822C (RESPONSE TXINFO REGISTER) */\n\n#define BIT_SHIFT_WMAC_RESP_MFB_8822C 25\n#define BIT_MASK_WMAC_RESP_MFB_8822C 0x7f\n#define BIT_WMAC_RESP_MFB_8822C(x)                                             \\\n\t(((x) & BIT_MASK_WMAC_RESP_MFB_8822C) << BIT_SHIFT_WMAC_RESP_MFB_8822C)\n#define BITS_WMAC_RESP_MFB_8822C                                               \\\n\t(BIT_MASK_WMAC_RESP_MFB_8822C << BIT_SHIFT_WMAC_RESP_MFB_8822C)\n#define BIT_CLEAR_WMAC_RESP_MFB_8822C(x) ((x) & (~BITS_WMAC_RESP_MFB_8822C))\n#define BIT_GET_WMAC_RESP_MFB_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_MFB_8822C) & BIT_MASK_WMAC_RESP_MFB_8822C)\n#define BIT_SET_WMAC_RESP_MFB_8822C(x, v)                                      \\\n\t(BIT_CLEAR_WMAC_RESP_MFB_8822C(x) | BIT_WMAC_RESP_MFB_8822C(v))\n\n#define BIT_SHIFT_WMAC_ANTINF_SEL_8822C 23\n#define BIT_MASK_WMAC_ANTINF_SEL_8822C 0x3\n#define BIT_WMAC_ANTINF_SEL_8822C(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_ANTINF_SEL_8822C)                                \\\n\t << BIT_SHIFT_WMAC_ANTINF_SEL_8822C)\n#define BITS_WMAC_ANTINF_SEL_8822C                                             \\\n\t(BIT_MASK_WMAC_ANTINF_SEL_8822C << BIT_SHIFT_WMAC_ANTINF_SEL_8822C)\n#define BIT_CLEAR_WMAC_ANTINF_SEL_8822C(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8822C))\n#define BIT_GET_WMAC_ANTINF_SEL_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8822C) &                            \\\n\t BIT_MASK_WMAC_ANTINF_SEL_8822C)\n#define BIT_SET_WMAC_ANTINF_SEL_8822C(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_ANTINF_SEL_8822C(x) | BIT_WMAC_ANTINF_SEL_8822C(v))\n\n#define BIT_SHIFT_WMAC_ANTSEL_SEL_8822C 21\n#define BIT_MASK_WMAC_ANTSEL_SEL_8822C 0x3\n#define BIT_WMAC_ANTSEL_SEL_8822C(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_ANTSEL_SEL_8822C)                                \\\n\t << BIT_SHIFT_WMAC_ANTSEL_SEL_8822C)\n#define BITS_WMAC_ANTSEL_SEL_8822C                                             \\\n\t(BIT_MASK_WMAC_ANTSEL_SEL_8822C << BIT_SHIFT_WMAC_ANTSEL_SEL_8822C)\n#define BIT_CLEAR_WMAC_ANTSEL_SEL_8822C(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8822C))\n#define BIT_GET_WMAC_ANTSEL_SEL_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8822C) &                            \\\n\t BIT_MASK_WMAC_ANTSEL_SEL_8822C)\n#define BIT_SET_WMAC_ANTSEL_SEL_8822C(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_ANTSEL_SEL_8822C(x) | BIT_WMAC_ANTSEL_SEL_8822C(v))\n\n#define BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C 18\n#define BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C 0x3\n#define BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x)                             \\\n\t(((x) & BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C)                  \\\n\t << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C)\n#define BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C                               \\\n\t(BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C                          \\\n\t << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C)\n#define BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x)                       \\\n\t((x) & (~BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C))\n#define BIT_GET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x)                         \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C) &              \\\n\t BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C)\n#define BIT_SET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x, v)                      \\\n\t(BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x) |                    \\\n\t BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(v))\n\n#define BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C 6\n#define BIT_MASK_WMAC_RESP_TXANT_V1_8822C 0xfff\n#define BIT_WMAC_RESP_TXANT_V1_8822C(x)                                        \\\n\t(((x) & BIT_MASK_WMAC_RESP_TXANT_V1_8822C)                             \\\n\t << BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C)\n#define BITS_WMAC_RESP_TXANT_V1_8822C                                          \\\n\t(BIT_MASK_WMAC_RESP_TXANT_V1_8822C                                     \\\n\t << BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C)\n#define BIT_CLEAR_WMAC_RESP_TXANT_V1_8822C(x)                                  \\\n\t((x) & (~BITS_WMAC_RESP_TXANT_V1_8822C))\n#define BIT_GET_WMAC_RESP_TXANT_V1_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C) &                         \\\n\t BIT_MASK_WMAC_RESP_TXANT_V1_8822C)\n#define BIT_SET_WMAC_RESP_TXANT_V1_8822C(x, v)                                 \\\n\t(BIT_CLEAR_WMAC_RESP_TXANT_V1_8822C(x) |                               \\\n\t BIT_WMAC_RESP_TXANT_V1_8822C(v))\n\n/* 2 REG_BBPSF_CTRL_8822C */\n#define BIT_CTL_IDLE_CLR_CSI_RPT_8822C BIT(31)\n#define BIT_WMAC_USE_NDPARATE_8822C BIT(30)\n\n#define BIT_SHIFT_WMAC_CSI_RATE_8822C 24\n#define BIT_MASK_WMAC_CSI_RATE_8822C 0x3f\n#define BIT_WMAC_CSI_RATE_8822C(x)                                             \\\n\t(((x) & BIT_MASK_WMAC_CSI_RATE_8822C) << BIT_SHIFT_WMAC_CSI_RATE_8822C)\n#define BITS_WMAC_CSI_RATE_8822C                                               \\\n\t(BIT_MASK_WMAC_CSI_RATE_8822C << BIT_SHIFT_WMAC_CSI_RATE_8822C)\n#define BIT_CLEAR_WMAC_CSI_RATE_8822C(x) ((x) & (~BITS_WMAC_CSI_RATE_8822C))\n#define BIT_GET_WMAC_CSI_RATE_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_WMAC_CSI_RATE_8822C) & BIT_MASK_WMAC_CSI_RATE_8822C)\n#define BIT_SET_WMAC_CSI_RATE_8822C(x, v)                                      \\\n\t(BIT_CLEAR_WMAC_CSI_RATE_8822C(x) | BIT_WMAC_CSI_RATE_8822C(v))\n\n#define BIT_SHIFT_WMAC_RESP_TXRATE_8822C 16\n#define BIT_MASK_WMAC_RESP_TXRATE_8822C 0xff\n#define BIT_WMAC_RESP_TXRATE_8822C(x)                                          \\\n\t(((x) & BIT_MASK_WMAC_RESP_TXRATE_8822C)                               \\\n\t << BIT_SHIFT_WMAC_RESP_TXRATE_8822C)\n#define BITS_WMAC_RESP_TXRATE_8822C                                            \\\n\t(BIT_MASK_WMAC_RESP_TXRATE_8822C << BIT_SHIFT_WMAC_RESP_TXRATE_8822C)\n#define BIT_CLEAR_WMAC_RESP_TXRATE_8822C(x)                                    \\\n\t((x) & (~BITS_WMAC_RESP_TXRATE_8822C))\n#define BIT_GET_WMAC_RESP_TXRATE_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8822C) &                           \\\n\t BIT_MASK_WMAC_RESP_TXRATE_8822C)\n#define BIT_SET_WMAC_RESP_TXRATE_8822C(x, v)                                   \\\n\t(BIT_CLEAR_WMAC_RESP_TXRATE_8822C(x) | BIT_WMAC_RESP_TXRATE_8822C(v))\n\n#define BIT_SHIFT_CSI_RSC_8822C 13\n#define BIT_MASK_CSI_RSC_8822C 0x3\n#define BIT_CSI_RSC_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_CSI_RSC_8822C) << BIT_SHIFT_CSI_RSC_8822C)\n#define BITS_CSI_RSC_8822C (BIT_MASK_CSI_RSC_8822C << BIT_SHIFT_CSI_RSC_8822C)\n#define BIT_CLEAR_CSI_RSC_8822C(x) ((x) & (~BITS_CSI_RSC_8822C))\n#define BIT_GET_CSI_RSC_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_CSI_RSC_8822C) & BIT_MASK_CSI_RSC_8822C)\n#define BIT_SET_CSI_RSC_8822C(x, v)                                            \\\n\t(BIT_CLEAR_CSI_RSC_8822C(x) | BIT_CSI_RSC_8822C(v))\n\n#define BIT_CSI_GID_SEL_8822C BIT(12)\n#define BIT_NDPVLD_PROTECT_RDRDY_DIS_8822C BIT(9)\n#define BIT_RDCSI_EMPTY_APPZERO_8822C BIT(8)\n#define BIT_CSI_RATE_FB_EN_8822C BIT(7)\n#define BIT_RXFIFO_WRPTR_WO_CHKSUM_8822C BIT(6)\n\n/* 2 REG_P2P_RX_BCN_NOA_8822C (P2P RX BEACON NOA REGISTER) */\n#define BIT_NOA_PARSER_EN_8822C BIT(15)\n\n#define BIT_SHIFT_BSSID_SEL_V1_8822C 12\n#define BIT_MASK_BSSID_SEL_V1_8822C 0x7\n#define BIT_BSSID_SEL_V1_8822C(x)                                              \\\n\t(((x) & BIT_MASK_BSSID_SEL_V1_8822C) << BIT_SHIFT_BSSID_SEL_V1_8822C)\n#define BITS_BSSID_SEL_V1_8822C                                                \\\n\t(BIT_MASK_BSSID_SEL_V1_8822C << BIT_SHIFT_BSSID_SEL_V1_8822C)\n#define BIT_CLEAR_BSSID_SEL_V1_8822C(x) ((x) & (~BITS_BSSID_SEL_V1_8822C))\n#define BIT_GET_BSSID_SEL_V1_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_BSSID_SEL_V1_8822C) & BIT_MASK_BSSID_SEL_V1_8822C)\n#define BIT_SET_BSSID_SEL_V1_8822C(x, v)                                       \\\n\t(BIT_CLEAR_BSSID_SEL_V1_8822C(x) | BIT_BSSID_SEL_V1_8822C(v))\n\n#define BIT_SHIFT_P2P_OUI_TYPE_8822C 0\n#define BIT_MASK_P2P_OUI_TYPE_8822C 0xff\n#define BIT_P2P_OUI_TYPE_8822C(x)                                              \\\n\t(((x) & BIT_MASK_P2P_OUI_TYPE_8822C) << BIT_SHIFT_P2P_OUI_TYPE_8822C)\n#define BITS_P2P_OUI_TYPE_8822C                                                \\\n\t(BIT_MASK_P2P_OUI_TYPE_8822C << BIT_SHIFT_P2P_OUI_TYPE_8822C)\n#define BIT_CLEAR_P2P_OUI_TYPE_8822C(x) ((x) & (~BITS_P2P_OUI_TYPE_8822C))\n#define BIT_GET_P2P_OUI_TYPE_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_P2P_OUI_TYPE_8822C) & BIT_MASK_P2P_OUI_TYPE_8822C)\n#define BIT_SET_P2P_OUI_TYPE_8822C(x, v)                                       \\\n\t(BIT_CLEAR_P2P_OUI_TYPE_8822C(x) | BIT_P2P_OUI_TYPE_8822C(v))\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_ASSOCIATED_BFMER0_INFO_8822C (ASSOCIATED BEAMFORMER0 INFO REGISTER) */\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C 0xffffffffL\n#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x)                               \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C)                    \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C)\n#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8822C                                 \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C                            \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x)                         \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8822C))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x)                           \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C) &                \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x, v)                        \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x) |                      \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(v))\n\n/* 2 REG_ASSOCIATED_BFMER0_INFO_H_8822C */\n\n#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C 16\n#define BIT_MASK_R_WMAC_TXCSI_AID0_8822C 0x1ff\n#define BIT_R_WMAC_TXCSI_AID0_8822C(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8822C)                              \\\n\t << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C)\n#define BITS_R_WMAC_TXCSI_AID0_8822C                                           \\\n\t(BIT_MASK_R_WMAC_TXCSI_AID0_8822C << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C)\n#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8822C(x)                                   \\\n\t((x) & (~BITS_R_WMAC_TXCSI_AID0_8822C))\n#define BIT_GET_R_WMAC_TXCSI_AID0_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C) &                          \\\n\t BIT_MASK_R_WMAC_TXCSI_AID0_8822C)\n#define BIT_SET_R_WMAC_TXCSI_AID0_8822C(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_TXCSI_AID0_8822C(x) | BIT_R_WMAC_TXCSI_AID0_8822C(v))\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C 0xffff\n#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x)                             \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C)                  \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C)\n#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C                               \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C                          \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x)                       \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x)                         \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C) &              \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x, v)                      \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x) |                    \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(v))\n\n/* 2 REG_ASSOCIATED_BFMER1_INFO_8822C (ASSOCIATED BEAMFORMER1 INFO REGISTER) */\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C 0xffffffffL\n#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x)                               \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C)                    \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C)\n#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8822C                                 \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C                            \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x)                         \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8822C))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x)                           \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C) &                \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x, v)                        \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x) |                      \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(v))\n\n/* 2 REG_ASSOCIATED_BFMER1_INFO_H_8822C */\n\n#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C 16\n#define BIT_MASK_R_WMAC_TXCSI_AID1_8822C 0x1ff\n#define BIT_R_WMAC_TXCSI_AID1_8822C(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8822C)                              \\\n\t << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C)\n#define BITS_R_WMAC_TXCSI_AID1_8822C                                           \\\n\t(BIT_MASK_R_WMAC_TXCSI_AID1_8822C << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C)\n#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8822C(x)                                   \\\n\t((x) & (~BITS_R_WMAC_TXCSI_AID1_8822C))\n#define BIT_GET_R_WMAC_TXCSI_AID1_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C) &                          \\\n\t BIT_MASK_R_WMAC_TXCSI_AID1_8822C)\n#define BIT_SET_R_WMAC_TXCSI_AID1_8822C(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_TXCSI_AID1_8822C(x) | BIT_R_WMAC_TXCSI_AID1_8822C(v))\n\n#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C 0\n#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C 0xffff\n#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x)                             \\\n\t(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C)                  \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C)\n#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C                               \\\n\t(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C                          \\\n\t << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C)\n#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x)                       \\\n\t((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C))\n#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x)                         \\\n\t(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C) &              \\\n\t BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C)\n#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x, v)                      \\\n\t(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x) |                    \\\n\t BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(v))\n\n/* 2 REG_TX_CSI_RPT_PARAM_BW20_8822C (TX CSI REPORT PARAMETER REGISTER) */\n\n#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C 16\n#define BIT_MASK_R_WMAC_BFINFO_20M_1_8822C 0xfff\n#define BIT_R_WMAC_BFINFO_20M_1_8822C(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822C)                            \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C)\n#define BITS_R_WMAC_BFINFO_20M_1_8822C                                         \\\n\t(BIT_MASK_R_WMAC_BFINFO_20M_1_8822C                                    \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C)\n#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822C(x)                                 \\\n\t((x) & (~BITS_R_WMAC_BFINFO_20M_1_8822C))\n#define BIT_GET_R_WMAC_BFINFO_20M_1_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C) &                        \\\n\t BIT_MASK_R_WMAC_BFINFO_20M_1_8822C)\n#define BIT_SET_R_WMAC_BFINFO_20M_1_8822C(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822C(x) |                              \\\n\t BIT_R_WMAC_BFINFO_20M_1_8822C(v))\n\n#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C 0\n#define BIT_MASK_R_WMAC_BFINFO_20M_0_8822C 0xfff\n#define BIT_R_WMAC_BFINFO_20M_0_8822C(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822C)                            \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C)\n#define BITS_R_WMAC_BFINFO_20M_0_8822C                                         \\\n\t(BIT_MASK_R_WMAC_BFINFO_20M_0_8822C                                    \\\n\t << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C)\n#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822C(x)                                 \\\n\t((x) & (~BITS_R_WMAC_BFINFO_20M_0_8822C))\n#define BIT_GET_R_WMAC_BFINFO_20M_0_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C) &                        \\\n\t BIT_MASK_R_WMAC_BFINFO_20M_0_8822C)\n#define BIT_SET_R_WMAC_BFINFO_20M_0_8822C(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822C(x) |                              \\\n\t BIT_R_WMAC_BFINFO_20M_0_8822C(v))\n\n/* 2 REG_TX_CSI_RPT_PARAM_BW40_8822C (TX CSI REPORT PARAMETER_BW40 REGISTER) */\n\n#define BIT_SHIFT_WMAC_RESP_ANTD_8822C 12\n#define BIT_MASK_WMAC_RESP_ANTD_8822C 0xf\n#define BIT_WMAC_RESP_ANTD_8822C(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_RESP_ANTD_8822C)                                 \\\n\t << BIT_SHIFT_WMAC_RESP_ANTD_8822C)\n#define BITS_WMAC_RESP_ANTD_8822C                                              \\\n\t(BIT_MASK_WMAC_RESP_ANTD_8822C << BIT_SHIFT_WMAC_RESP_ANTD_8822C)\n#define BIT_CLEAR_WMAC_RESP_ANTD_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTD_8822C))\n#define BIT_GET_WMAC_RESP_ANTD_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_ANTD_8822C) &                             \\\n\t BIT_MASK_WMAC_RESP_ANTD_8822C)\n#define BIT_SET_WMAC_RESP_ANTD_8822C(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_RESP_ANTD_8822C(x) | BIT_WMAC_RESP_ANTD_8822C(v))\n\n#define BIT_SHIFT_WMAC_RESP_ANTC_8822C 8\n#define BIT_MASK_WMAC_RESP_ANTC_8822C 0xf\n#define BIT_WMAC_RESP_ANTC_8822C(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_RESP_ANTC_8822C)                                 \\\n\t << BIT_SHIFT_WMAC_RESP_ANTC_8822C)\n#define BITS_WMAC_RESP_ANTC_8822C                                              \\\n\t(BIT_MASK_WMAC_RESP_ANTC_8822C << BIT_SHIFT_WMAC_RESP_ANTC_8822C)\n#define BIT_CLEAR_WMAC_RESP_ANTC_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTC_8822C))\n#define BIT_GET_WMAC_RESP_ANTC_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_ANTC_8822C) &                             \\\n\t BIT_MASK_WMAC_RESP_ANTC_8822C)\n#define BIT_SET_WMAC_RESP_ANTC_8822C(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_RESP_ANTC_8822C(x) | BIT_WMAC_RESP_ANTC_8822C(v))\n\n#define BIT_SHIFT_WMAC_RESP_ANTB_8822C 4\n#define BIT_MASK_WMAC_RESP_ANTB_8822C 0xf\n#define BIT_WMAC_RESP_ANTB_8822C(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_RESP_ANTB_8822C)                                 \\\n\t << BIT_SHIFT_WMAC_RESP_ANTB_8822C)\n#define BITS_WMAC_RESP_ANTB_8822C                                              \\\n\t(BIT_MASK_WMAC_RESP_ANTB_8822C << BIT_SHIFT_WMAC_RESP_ANTB_8822C)\n#define BIT_CLEAR_WMAC_RESP_ANTB_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTB_8822C))\n#define BIT_GET_WMAC_RESP_ANTB_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_ANTB_8822C) &                             \\\n\t BIT_MASK_WMAC_RESP_ANTB_8822C)\n#define BIT_SET_WMAC_RESP_ANTB_8822C(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_RESP_ANTB_8822C(x) | BIT_WMAC_RESP_ANTB_8822C(v))\n\n#define BIT_SHIFT_WMAC_RESP_ANTA_8822C 0\n#define BIT_MASK_WMAC_RESP_ANTA_8822C 0xf\n#define BIT_WMAC_RESP_ANTA_8822C(x)                                            \\\n\t(((x) & BIT_MASK_WMAC_RESP_ANTA_8822C)                                 \\\n\t << BIT_SHIFT_WMAC_RESP_ANTA_8822C)\n#define BITS_WMAC_RESP_ANTA_8822C                                              \\\n\t(BIT_MASK_WMAC_RESP_ANTA_8822C << BIT_SHIFT_WMAC_RESP_ANTA_8822C)\n#define BIT_CLEAR_WMAC_RESP_ANTA_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTA_8822C))\n#define BIT_GET_WMAC_RESP_ANTA_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_WMAC_RESP_ANTA_8822C) &                             \\\n\t BIT_MASK_WMAC_RESP_ANTA_8822C)\n#define BIT_SET_WMAC_RESP_ANTA_8822C(x, v)                                     \\\n\t(BIT_CLEAR_WMAC_RESP_ANTA_8822C(x) | BIT_WMAC_RESP_ANTA_8822C(v))\n\n/* 2 REG_CSI_PTR_8822C */\n\n#define BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C 16\n#define BIT_MASK_CSI_RADDR_LATCH_V2_8822C 0xffff\n#define BIT_CSI_RADDR_LATCH_V2_8822C(x)                                        \\\n\t(((x) & BIT_MASK_CSI_RADDR_LATCH_V2_8822C)                             \\\n\t << BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C)\n#define BITS_CSI_RADDR_LATCH_V2_8822C                                          \\\n\t(BIT_MASK_CSI_RADDR_LATCH_V2_8822C                                     \\\n\t << BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C)\n#define BIT_CLEAR_CSI_RADDR_LATCH_V2_8822C(x)                                  \\\n\t((x) & (~BITS_CSI_RADDR_LATCH_V2_8822C))\n#define BIT_GET_CSI_RADDR_LATCH_V2_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C) &                         \\\n\t BIT_MASK_CSI_RADDR_LATCH_V2_8822C)\n#define BIT_SET_CSI_RADDR_LATCH_V2_8822C(x, v)                                 \\\n\t(BIT_CLEAR_CSI_RADDR_LATCH_V2_8822C(x) |                               \\\n\t BIT_CSI_RADDR_LATCH_V2_8822C(v))\n\n#define BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C 0\n#define BIT_MASK_CSI_WADDR_LATCH_V2_8822C 0xffff\n#define BIT_CSI_WADDR_LATCH_V2_8822C(x)                                        \\\n\t(((x) & BIT_MASK_CSI_WADDR_LATCH_V2_8822C)                             \\\n\t << BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C)\n#define BITS_CSI_WADDR_LATCH_V2_8822C                                          \\\n\t(BIT_MASK_CSI_WADDR_LATCH_V2_8822C                                     \\\n\t << BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C)\n#define BIT_CLEAR_CSI_WADDR_LATCH_V2_8822C(x)                                  \\\n\t((x) & (~BITS_CSI_WADDR_LATCH_V2_8822C))\n#define BIT_GET_CSI_WADDR_LATCH_V2_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C) &                         \\\n\t BIT_MASK_CSI_WADDR_LATCH_V2_8822C)\n#define BIT_SET_CSI_WADDR_LATCH_V2_8822C(x, v)                                 \\\n\t(BIT_CLEAR_CSI_WADDR_LATCH_V2_8822C(x) |                               \\\n\t BIT_CSI_WADDR_LATCH_V2_8822C(v))\n\n/* 2 REG_BCN_PSR_RPT2_8822C (BEACON PARSER REPORT REGISTER2) */\n\n#define BIT_SHIFT_DTIM_CNT2_8822C 24\n#define BIT_MASK_DTIM_CNT2_8822C 0xff\n#define BIT_DTIM_CNT2_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT2_8822C) << BIT_SHIFT_DTIM_CNT2_8822C)\n#define BITS_DTIM_CNT2_8822C                                                   \\\n\t(BIT_MASK_DTIM_CNT2_8822C << BIT_SHIFT_DTIM_CNT2_8822C)\n#define BIT_CLEAR_DTIM_CNT2_8822C(x) ((x) & (~BITS_DTIM_CNT2_8822C))\n#define BIT_GET_DTIM_CNT2_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT2_8822C) & BIT_MASK_DTIM_CNT2_8822C)\n#define BIT_SET_DTIM_CNT2_8822C(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT2_8822C(x) | BIT_DTIM_CNT2_8822C(v))\n\n#define BIT_SHIFT_DTIM_PERIOD2_8822C 16\n#define BIT_MASK_DTIM_PERIOD2_8822C 0xff\n#define BIT_DTIM_PERIOD2_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD2_8822C) << BIT_SHIFT_DTIM_PERIOD2_8822C)\n#define BITS_DTIM_PERIOD2_8822C                                                \\\n\t(BIT_MASK_DTIM_PERIOD2_8822C << BIT_SHIFT_DTIM_PERIOD2_8822C)\n#define BIT_CLEAR_DTIM_PERIOD2_8822C(x) ((x) & (~BITS_DTIM_PERIOD2_8822C))\n#define BIT_GET_DTIM_PERIOD2_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD2_8822C) & BIT_MASK_DTIM_PERIOD2_8822C)\n#define BIT_SET_DTIM_PERIOD2_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD2_8822C(x) | BIT_DTIM_PERIOD2_8822C(v))\n\n#define BIT_DTIM2_8822C BIT(15)\n#define BIT_TIM2_8822C BIT(14)\n#define BIT_RPT_VALID_8822C BIT(13)\n\n#define BIT_SHIFT_PS_AID_2_8822C 0\n#define BIT_MASK_PS_AID_2_8822C 0x7ff\n#define BIT_PS_AID_2_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_2_8822C) << BIT_SHIFT_PS_AID_2_8822C)\n#define BITS_PS_AID_2_8822C                                                    \\\n\t(BIT_MASK_PS_AID_2_8822C << BIT_SHIFT_PS_AID_2_8822C)\n#define BIT_CLEAR_PS_AID_2_8822C(x) ((x) & (~BITS_PS_AID_2_8822C))\n#define BIT_GET_PS_AID_2_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_2_8822C) & BIT_MASK_PS_AID_2_8822C)\n#define BIT_SET_PS_AID_2_8822C(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_2_8822C(x) | BIT_PS_AID_2_8822C(v))\n\n/* 2 REG_BCN_PSR_RPT3_8822C (BEACON PARSER REPORT REGISTER3) */\n\n#define BIT_SHIFT_DTIM_CNT3_8822C 24\n#define BIT_MASK_DTIM_CNT3_8822C 0xff\n#define BIT_DTIM_CNT3_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT3_8822C) << BIT_SHIFT_DTIM_CNT3_8822C)\n#define BITS_DTIM_CNT3_8822C                                                   \\\n\t(BIT_MASK_DTIM_CNT3_8822C << BIT_SHIFT_DTIM_CNT3_8822C)\n#define BIT_CLEAR_DTIM_CNT3_8822C(x) ((x) & (~BITS_DTIM_CNT3_8822C))\n#define BIT_GET_DTIM_CNT3_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT3_8822C) & BIT_MASK_DTIM_CNT3_8822C)\n#define BIT_SET_DTIM_CNT3_8822C(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT3_8822C(x) | BIT_DTIM_CNT3_8822C(v))\n\n#define BIT_SHIFT_DTIM_PERIOD3_8822C 16\n#define BIT_MASK_DTIM_PERIOD3_8822C 0xff\n#define BIT_DTIM_PERIOD3_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD3_8822C) << BIT_SHIFT_DTIM_PERIOD3_8822C)\n#define BITS_DTIM_PERIOD3_8822C                                                \\\n\t(BIT_MASK_DTIM_PERIOD3_8822C << BIT_SHIFT_DTIM_PERIOD3_8822C)\n#define BIT_CLEAR_DTIM_PERIOD3_8822C(x) ((x) & (~BITS_DTIM_PERIOD3_8822C))\n#define BIT_GET_DTIM_PERIOD3_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD3_8822C) & BIT_MASK_DTIM_PERIOD3_8822C)\n#define BIT_SET_DTIM_PERIOD3_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD3_8822C(x) | BIT_DTIM_PERIOD3_8822C(v))\n\n#define BIT_DTIM3_8822C BIT(15)\n#define BIT_TIM3_8822C BIT(14)\n#define BIT_RPT_VALID_8822C BIT(13)\n\n#define BIT_SHIFT_PS_AID_3_8822C 0\n#define BIT_MASK_PS_AID_3_8822C 0x7ff\n#define BIT_PS_AID_3_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_3_8822C) << BIT_SHIFT_PS_AID_3_8822C)\n#define BITS_PS_AID_3_8822C                                                    \\\n\t(BIT_MASK_PS_AID_3_8822C << BIT_SHIFT_PS_AID_3_8822C)\n#define BIT_CLEAR_PS_AID_3_8822C(x) ((x) & (~BITS_PS_AID_3_8822C))\n#define BIT_GET_PS_AID_3_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_3_8822C) & BIT_MASK_PS_AID_3_8822C)\n#define BIT_SET_PS_AID_3_8822C(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_3_8822C(x) | BIT_PS_AID_3_8822C(v))\n\n/* 2 REG_BCN_PSR_RPT4_8822C (BEACON PARSER REPORT REGISTER4) */\n\n#define BIT_SHIFT_DTIM_CNT4_8822C 24\n#define BIT_MASK_DTIM_CNT4_8822C 0xff\n#define BIT_DTIM_CNT4_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT4_8822C) << BIT_SHIFT_DTIM_CNT4_8822C)\n#define BITS_DTIM_CNT4_8822C                                                   \\\n\t(BIT_MASK_DTIM_CNT4_8822C << BIT_SHIFT_DTIM_CNT4_8822C)\n#define BIT_CLEAR_DTIM_CNT4_8822C(x) ((x) & (~BITS_DTIM_CNT4_8822C))\n#define BIT_GET_DTIM_CNT4_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT4_8822C) & BIT_MASK_DTIM_CNT4_8822C)\n#define BIT_SET_DTIM_CNT4_8822C(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT4_8822C(x) | BIT_DTIM_CNT4_8822C(v))\n\n#define BIT_SHIFT_DTIM_PERIOD4_8822C 16\n#define BIT_MASK_DTIM_PERIOD4_8822C 0xff\n#define BIT_DTIM_PERIOD4_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD4_8822C) << BIT_SHIFT_DTIM_PERIOD4_8822C)\n#define BITS_DTIM_PERIOD4_8822C                                                \\\n\t(BIT_MASK_DTIM_PERIOD4_8822C << BIT_SHIFT_DTIM_PERIOD4_8822C)\n#define BIT_CLEAR_DTIM_PERIOD4_8822C(x) ((x) & (~BITS_DTIM_PERIOD4_8822C))\n#define BIT_GET_DTIM_PERIOD4_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD4_8822C) & BIT_MASK_DTIM_PERIOD4_8822C)\n#define BIT_SET_DTIM_PERIOD4_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD4_8822C(x) | BIT_DTIM_PERIOD4_8822C(v))\n\n#define BIT_DTIM4_8822C BIT(15)\n#define BIT_TIM4_8822C BIT(14)\n#define BIT_RPT_VALID_8822C BIT(13)\n\n#define BIT_SHIFT_PS_AID_4_8822C 0\n#define BIT_MASK_PS_AID_4_8822C 0x7ff\n#define BIT_PS_AID_4_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_4_8822C) << BIT_SHIFT_PS_AID_4_8822C)\n#define BITS_PS_AID_4_8822C                                                    \\\n\t(BIT_MASK_PS_AID_4_8822C << BIT_SHIFT_PS_AID_4_8822C)\n#define BIT_CLEAR_PS_AID_4_8822C(x) ((x) & (~BITS_PS_AID_4_8822C))\n#define BIT_GET_PS_AID_4_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_4_8822C) & BIT_MASK_PS_AID_4_8822C)\n#define BIT_SET_PS_AID_4_8822C(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_4_8822C(x) | BIT_PS_AID_4_8822C(v))\n\n/* 2 REG_A1_ADDR_MASK_8822C (A1 ADDR MASK REGISTER) */\n\n#define BIT_SHIFT_A1_ADDR_MASK_8822C 0\n#define BIT_MASK_A1_ADDR_MASK_8822C 0xffffffffL\n#define BIT_A1_ADDR_MASK_8822C(x)                                              \\\n\t(((x) & BIT_MASK_A1_ADDR_MASK_8822C) << BIT_SHIFT_A1_ADDR_MASK_8822C)\n#define BITS_A1_ADDR_MASK_8822C                                                \\\n\t(BIT_MASK_A1_ADDR_MASK_8822C << BIT_SHIFT_A1_ADDR_MASK_8822C)\n#define BIT_CLEAR_A1_ADDR_MASK_8822C(x) ((x) & (~BITS_A1_ADDR_MASK_8822C))\n#define BIT_GET_A1_ADDR_MASK_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_A1_ADDR_MASK_8822C) & BIT_MASK_A1_ADDR_MASK_8822C)\n#define BIT_SET_A1_ADDR_MASK_8822C(x, v)                                       \\\n\t(BIT_CLEAR_A1_ADDR_MASK_8822C(x) | BIT_A1_ADDR_MASK_8822C(v))\n\n/* 2 REG_RXPSF_CTRL_8822C */\n#define BIT_RXGCK_FIFOTHR_EN_8822C BIT(28)\n\n#define BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C 26\n#define BIT_MASK_RXGCK_VHT_FIFOTHR_8822C 0x3\n#define BIT_RXGCK_VHT_FIFOTHR_8822C(x)                                         \\\n\t(((x) & BIT_MASK_RXGCK_VHT_FIFOTHR_8822C)                              \\\n\t << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C)\n#define BITS_RXGCK_VHT_FIFOTHR_8822C                                           \\\n\t(BIT_MASK_RXGCK_VHT_FIFOTHR_8822C << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C)\n#define BIT_CLEAR_RXGCK_VHT_FIFOTHR_8822C(x)                                   \\\n\t((x) & (~BITS_RXGCK_VHT_FIFOTHR_8822C))\n#define BIT_GET_RXGCK_VHT_FIFOTHR_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C) &                          \\\n\t BIT_MASK_RXGCK_VHT_FIFOTHR_8822C)\n#define BIT_SET_RXGCK_VHT_FIFOTHR_8822C(x, v)                                  \\\n\t(BIT_CLEAR_RXGCK_VHT_FIFOTHR_8822C(x) | BIT_RXGCK_VHT_FIFOTHR_8822C(v))\n\n#define BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C 24\n#define BIT_MASK_RXGCK_HT_FIFOTHR_8822C 0x3\n#define BIT_RXGCK_HT_FIFOTHR_8822C(x)                                          \\\n\t(((x) & BIT_MASK_RXGCK_HT_FIFOTHR_8822C)                               \\\n\t << BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C)\n#define BITS_RXGCK_HT_FIFOTHR_8822C                                            \\\n\t(BIT_MASK_RXGCK_HT_FIFOTHR_8822C << BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C)\n#define BIT_CLEAR_RXGCK_HT_FIFOTHR_8822C(x)                                    \\\n\t((x) & (~BITS_RXGCK_HT_FIFOTHR_8822C))\n#define BIT_GET_RXGCK_HT_FIFOTHR_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C) &                           \\\n\t BIT_MASK_RXGCK_HT_FIFOTHR_8822C)\n#define BIT_SET_RXGCK_HT_FIFOTHR_8822C(x, v)                                   \\\n\t(BIT_CLEAR_RXGCK_HT_FIFOTHR_8822C(x) | BIT_RXGCK_HT_FIFOTHR_8822C(v))\n\n#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C 22\n#define BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C 0x3\n#define BIT_RXGCK_OFDM_FIFOTHR_8822C(x)                                        \\\n\t(((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C)                             \\\n\t << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C)\n#define BITS_RXGCK_OFDM_FIFOTHR_8822C                                          \\\n\t(BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C                                     \\\n\t << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C)\n#define BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8822C(x)                                  \\\n\t((x) & (~BITS_RXGCK_OFDM_FIFOTHR_8822C))\n#define BIT_GET_RXGCK_OFDM_FIFOTHR_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C) &                         \\\n\t BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C)\n#define BIT_SET_RXGCK_OFDM_FIFOTHR_8822C(x, v)                                 \\\n\t(BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8822C(x) |                               \\\n\t BIT_RXGCK_OFDM_FIFOTHR_8822C(v))\n\n#define BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C 20\n#define BIT_MASK_RXGCK_CCK_FIFOTHR_8822C 0x3\n#define BIT_RXGCK_CCK_FIFOTHR_8822C(x)                                         \\\n\t(((x) & BIT_MASK_RXGCK_CCK_FIFOTHR_8822C)                              \\\n\t << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C)\n#define BITS_RXGCK_CCK_FIFOTHR_8822C                                           \\\n\t(BIT_MASK_RXGCK_CCK_FIFOTHR_8822C << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C)\n#define BIT_CLEAR_RXGCK_CCK_FIFOTHR_8822C(x)                                   \\\n\t((x) & (~BITS_RXGCK_CCK_FIFOTHR_8822C))\n#define BIT_GET_RXGCK_CCK_FIFOTHR_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C) &                          \\\n\t BIT_MASK_RXGCK_CCK_FIFOTHR_8822C)\n#define BIT_SET_RXGCK_CCK_FIFOTHR_8822C(x, v)                                  \\\n\t(BIT_CLEAR_RXGCK_CCK_FIFOTHR_8822C(x) | BIT_RXGCK_CCK_FIFOTHR_8822C(v))\n\n#define BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C 17\n#define BIT_MASK_RXGCK_ENTRY_DELAY_8822C 0x7\n#define BIT_RXGCK_ENTRY_DELAY_8822C(x)                                         \\\n\t(((x) & BIT_MASK_RXGCK_ENTRY_DELAY_8822C)                              \\\n\t << BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C)\n#define BITS_RXGCK_ENTRY_DELAY_8822C                                           \\\n\t(BIT_MASK_RXGCK_ENTRY_DELAY_8822C << BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C)\n#define BIT_CLEAR_RXGCK_ENTRY_DELAY_8822C(x)                                   \\\n\t((x) & (~BITS_RXGCK_ENTRY_DELAY_8822C))\n#define BIT_GET_RXGCK_ENTRY_DELAY_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C) &                          \\\n\t BIT_MASK_RXGCK_ENTRY_DELAY_8822C)\n#define BIT_SET_RXGCK_ENTRY_DELAY_8822C(x, v)                                  \\\n\t(BIT_CLEAR_RXGCK_ENTRY_DELAY_8822C(x) | BIT_RXGCK_ENTRY_DELAY_8822C(v))\n\n#define BIT_RXGCK_OFDMCCA_EN_8822C BIT(16)\n\n#define BIT_SHIFT_RXPSF_PKTLENTHR_8822C 13\n#define BIT_MASK_RXPSF_PKTLENTHR_8822C 0x7\n#define BIT_RXPSF_PKTLENTHR_8822C(x)                                           \\\n\t(((x) & BIT_MASK_RXPSF_PKTLENTHR_8822C)                                \\\n\t << BIT_SHIFT_RXPSF_PKTLENTHR_8822C)\n#define BITS_RXPSF_PKTLENTHR_8822C                                             \\\n\t(BIT_MASK_RXPSF_PKTLENTHR_8822C << BIT_SHIFT_RXPSF_PKTLENTHR_8822C)\n#define BIT_CLEAR_RXPSF_PKTLENTHR_8822C(x) ((x) & (~BITS_RXPSF_PKTLENTHR_8822C))\n#define BIT_GET_RXPSF_PKTLENTHR_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_RXPSF_PKTLENTHR_8822C) &                            \\\n\t BIT_MASK_RXPSF_PKTLENTHR_8822C)\n#define BIT_SET_RXPSF_PKTLENTHR_8822C(x, v)                                    \\\n\t(BIT_CLEAR_RXPSF_PKTLENTHR_8822C(x) | BIT_RXPSF_PKTLENTHR_8822C(v))\n\n#define BIT_RXPSF_CTRLEN_8822C BIT(12)\n#define BIT_RXPSF_VHTCHKEN_8822C BIT(11)\n#define BIT_RXPSF_HTCHKEN_8822C BIT(10)\n#define BIT_RXPSF_OFDMCHKEN_8822C BIT(9)\n#define BIT_RXPSF_CCKCHKEN_8822C BIT(8)\n#define BIT_RXPSF_OFDMRST_8822C BIT(7)\n#define BIT_RXPSF_CCKRST_8822C BIT(6)\n#define BIT_RXPSF_MHCHKEN_8822C BIT(5)\n#define BIT_RXPSF_CONT_ERRCHKEN_8822C BIT(4)\n#define BIT_RXPSF_ALL_ERRCHKEN_8822C BIT(3)\n\n#define BIT_SHIFT_RXPSF_ERRTHR_8822C 0\n#define BIT_MASK_RXPSF_ERRTHR_8822C 0x7\n#define BIT_RXPSF_ERRTHR_8822C(x)                                              \\\n\t(((x) & BIT_MASK_RXPSF_ERRTHR_8822C) << BIT_SHIFT_RXPSF_ERRTHR_8822C)\n#define BITS_RXPSF_ERRTHR_8822C                                                \\\n\t(BIT_MASK_RXPSF_ERRTHR_8822C << BIT_SHIFT_RXPSF_ERRTHR_8822C)\n#define BIT_CLEAR_RXPSF_ERRTHR_8822C(x) ((x) & (~BITS_RXPSF_ERRTHR_8822C))\n#define BIT_GET_RXPSF_ERRTHR_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_RXPSF_ERRTHR_8822C) & BIT_MASK_RXPSF_ERRTHR_8822C)\n#define BIT_SET_RXPSF_ERRTHR_8822C(x, v)                                       \\\n\t(BIT_CLEAR_RXPSF_ERRTHR_8822C(x) | BIT_RXPSF_ERRTHR_8822C(v))\n\n/* 2 REG_RXPSF_TYPE_CTRL_8822C */\n#define BIT_RXPSF_DATA15EN_8822C BIT(31)\n#define BIT_RXPSF_DATA14EN_8822C BIT(30)\n#define BIT_RXPSF_DATA13EN_8822C BIT(29)\n#define BIT_RXPSF_DATA12EN_8822C BIT(28)\n#define BIT_RXPSF_DATA11EN_8822C BIT(27)\n#define BIT_RXPSF_DATA10EN_8822C BIT(26)\n#define BIT_RXPSF_DATA9EN_8822C BIT(25)\n#define BIT_RXPSF_DATA8EN_8822C BIT(24)\n#define BIT_RXPSF_DATA7EN_8822C BIT(23)\n#define BIT_RXPSF_DATA6EN_8822C BIT(22)\n#define BIT_RXPSF_DATA5EN_8822C BIT(21)\n#define BIT_RXPSF_DATA4EN_8822C BIT(20)\n#define BIT_RXPSF_DATA3EN_8822C BIT(19)\n#define BIT_RXPSF_DATA2EN_8822C BIT(18)\n#define BIT_RXPSF_DATA1EN_8822C BIT(17)\n#define BIT_RXPSF_DATA0EN_8822C BIT(16)\n#define BIT_RXPSF_MGT15EN_8822C BIT(15)\n#define BIT_RXPSF_MGT14EN_8822C BIT(14)\n#define BIT_RXPSF_MGT13EN_8822C BIT(13)\n#define BIT_RXPSF_MGT12EN_8822C BIT(12)\n#define BIT_RXPSF_MGT11EN_8822C BIT(11)\n#define BIT_RXPSF_MGT10EN_8822C BIT(10)\n#define BIT_RXPSF_MGT9EN_8822C BIT(9)\n#define BIT_RXPSF_MGT8EN_8822C BIT(8)\n#define BIT_RXPSF_MGT7EN_8822C BIT(7)\n#define BIT_RXPSF_MGT6EN_8822C BIT(6)\n#define BIT_RXPSF_MGT5EN_8822C BIT(5)\n#define BIT_RXPSF_MGT4EN_8822C BIT(4)\n#define BIT_RXPSF_MGT3EN_8822C BIT(3)\n#define BIT_RXPSF_MGT2EN_8822C BIT(2)\n#define BIT_RXPSF_MGT1EN_8822C BIT(1)\n#define BIT_RXPSF_MGT0EN_8822C BIT(0)\n\n/* 2 REG_CAM_ACCESS_CTRL_8822C */\n#define BIT_INDIRECT_ERR_8822C BIT(6)\n#define BIT_DIRECT_ERR_8822C BIT(5)\n#define BIT_DIR_ACCESS_EN_RX_BA_8822C BIT(4)\n#define BIT_DIR_ACCESS_EN_MBSSIDCAM_8822C BIT(3)\n#define BIT_DIR_ACCESS_EN_KEY_8822C BIT(2)\n#define BIT_DIR_ACCESS_EN_WOWLAN_8822C BIT(1)\n#define BIT_DIR_ACCESS_EN_FW_FILTER_8822C BIT(0)\n\n/* 2 REG_HT_SND_REF_RATE_8822C */\n\n#define BIT_SHIFT_WMAC_HT_CSI_RATE_8822C 0\n#define BIT_MASK_WMAC_HT_CSI_RATE_8822C 0x3f\n#define BIT_WMAC_HT_CSI_RATE_8822C(x)                                          \\\n\t(((x) & BIT_MASK_WMAC_HT_CSI_RATE_8822C)                               \\\n\t << BIT_SHIFT_WMAC_HT_CSI_RATE_8822C)\n#define BITS_WMAC_HT_CSI_RATE_8822C                                            \\\n\t(BIT_MASK_WMAC_HT_CSI_RATE_8822C << BIT_SHIFT_WMAC_HT_CSI_RATE_8822C)\n#define BIT_CLEAR_WMAC_HT_CSI_RATE_8822C(x)                                    \\\n\t((x) & (~BITS_WMAC_HT_CSI_RATE_8822C))\n#define BIT_GET_WMAC_HT_CSI_RATE_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_WMAC_HT_CSI_RATE_8822C) &                           \\\n\t BIT_MASK_WMAC_HT_CSI_RATE_8822C)\n#define BIT_SET_WMAC_HT_CSI_RATE_8822C(x, v)                                   \\\n\t(BIT_CLEAR_WMAC_HT_CSI_RATE_8822C(x) | BIT_WMAC_HT_CSI_RATE_8822C(v))\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_MACID2_8822C (MAC ID2 REGISTER) */\n\n#define BIT_SHIFT_MACID2_V1_8822C 0\n#define BIT_MASK_MACID2_V1_8822C 0xffffffffL\n#define BIT_MACID2_V1_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_MACID2_V1_8822C) << BIT_SHIFT_MACID2_V1_8822C)\n#define BITS_MACID2_V1_8822C                                                   \\\n\t(BIT_MASK_MACID2_V1_8822C << BIT_SHIFT_MACID2_V1_8822C)\n#define BIT_CLEAR_MACID2_V1_8822C(x) ((x) & (~BITS_MACID2_V1_8822C))\n#define BIT_GET_MACID2_V1_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MACID2_V1_8822C) & BIT_MASK_MACID2_V1_8822C)\n#define BIT_SET_MACID2_V1_8822C(x, v)                                          \\\n\t(BIT_CLEAR_MACID2_V1_8822C(x) | BIT_MACID2_V1_8822C(v))\n\n/* 2 REG_MACID2_H_8822C (MAC ID2 REGISTER) */\n\n#define BIT_SHIFT_MACID2_H_V1_8822C 0\n#define BIT_MASK_MACID2_H_V1_8822C 0xffff\n#define BIT_MACID2_H_V1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_MACID2_H_V1_8822C) << BIT_SHIFT_MACID2_H_V1_8822C)\n#define BITS_MACID2_H_V1_8822C                                                 \\\n\t(BIT_MASK_MACID2_H_V1_8822C << BIT_SHIFT_MACID2_H_V1_8822C)\n#define BIT_CLEAR_MACID2_H_V1_8822C(x) ((x) & (~BITS_MACID2_H_V1_8822C))\n#define BIT_GET_MACID2_H_V1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_MACID2_H_V1_8822C) & BIT_MASK_MACID2_H_V1_8822C)\n#define BIT_SET_MACID2_H_V1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_MACID2_H_V1_8822C(x) | BIT_MACID2_H_V1_8822C(v))\n\n/* 2 REG_BSSID2_8822C (BSSID2 REGISTER) */\n\n#define BIT_SHIFT_BSSID2_V1_8822C 0\n#define BIT_MASK_BSSID2_V1_8822C 0xffffffffL\n#define BIT_BSSID2_V1_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_BSSID2_V1_8822C) << BIT_SHIFT_BSSID2_V1_8822C)\n#define BITS_BSSID2_V1_8822C                                                   \\\n\t(BIT_MASK_BSSID2_V1_8822C << BIT_SHIFT_BSSID2_V1_8822C)\n#define BIT_CLEAR_BSSID2_V1_8822C(x) ((x) & (~BITS_BSSID2_V1_8822C))\n#define BIT_GET_BSSID2_V1_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_BSSID2_V1_8822C) & BIT_MASK_BSSID2_V1_8822C)\n#define BIT_SET_BSSID2_V1_8822C(x, v)                                          \\\n\t(BIT_CLEAR_BSSID2_V1_8822C(x) | BIT_BSSID2_V1_8822C(v))\n\n/* 2 REG_BSSID2_H_8822C (BSSID2 REGISTER) */\n\n#define BIT_SHIFT_BSSID2_H_V1_8822C 0\n#define BIT_MASK_BSSID2_H_V1_8822C 0xffff\n#define BIT_BSSID2_H_V1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_BSSID2_H_V1_8822C) << BIT_SHIFT_BSSID2_H_V1_8822C)\n#define BITS_BSSID2_H_V1_8822C                                                 \\\n\t(BIT_MASK_BSSID2_H_V1_8822C << BIT_SHIFT_BSSID2_H_V1_8822C)\n#define BIT_CLEAR_BSSID2_H_V1_8822C(x) ((x) & (~BITS_BSSID2_H_V1_8822C))\n#define BIT_GET_BSSID2_H_V1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_BSSID2_H_V1_8822C) & BIT_MASK_BSSID2_H_V1_8822C)\n#define BIT_SET_BSSID2_H_V1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_BSSID2_H_V1_8822C(x) | BIT_BSSID2_H_V1_8822C(v))\n\n/* 2 REG_MACID3_8822C (MAC ID3 REGISTER) */\n\n#define BIT_SHIFT_MACID3_V1_8822C 0\n#define BIT_MASK_MACID3_V1_8822C 0xffffffffL\n#define BIT_MACID3_V1_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_MACID3_V1_8822C) << BIT_SHIFT_MACID3_V1_8822C)\n#define BITS_MACID3_V1_8822C                                                   \\\n\t(BIT_MASK_MACID3_V1_8822C << BIT_SHIFT_MACID3_V1_8822C)\n#define BIT_CLEAR_MACID3_V1_8822C(x) ((x) & (~BITS_MACID3_V1_8822C))\n#define BIT_GET_MACID3_V1_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MACID3_V1_8822C) & BIT_MASK_MACID3_V1_8822C)\n#define BIT_SET_MACID3_V1_8822C(x, v)                                          \\\n\t(BIT_CLEAR_MACID3_V1_8822C(x) | BIT_MACID3_V1_8822C(v))\n\n/* 2 REG_MACID3_H_8822C (MAC ID3 REGISTER) */\n\n#define BIT_SHIFT_MACID3_H_V1_8822C 0\n#define BIT_MASK_MACID3_H_V1_8822C 0xffff\n#define BIT_MACID3_H_V1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_MACID3_H_V1_8822C) << BIT_SHIFT_MACID3_H_V1_8822C)\n#define BITS_MACID3_H_V1_8822C                                                 \\\n\t(BIT_MASK_MACID3_H_V1_8822C << BIT_SHIFT_MACID3_H_V1_8822C)\n#define BIT_CLEAR_MACID3_H_V1_8822C(x) ((x) & (~BITS_MACID3_H_V1_8822C))\n#define BIT_GET_MACID3_H_V1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_MACID3_H_V1_8822C) & BIT_MASK_MACID3_H_V1_8822C)\n#define BIT_SET_MACID3_H_V1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_MACID3_H_V1_8822C(x) | BIT_MACID3_H_V1_8822C(v))\n\n/* 2 REG_BSSID3_8822C (BSSID3 REGISTER) */\n\n#define BIT_SHIFT_BSSID3_V1_8822C 0\n#define BIT_MASK_BSSID3_V1_8822C 0xffffffffL\n#define BIT_BSSID3_V1_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_BSSID3_V1_8822C) << BIT_SHIFT_BSSID3_V1_8822C)\n#define BITS_BSSID3_V1_8822C                                                   \\\n\t(BIT_MASK_BSSID3_V1_8822C << BIT_SHIFT_BSSID3_V1_8822C)\n#define BIT_CLEAR_BSSID3_V1_8822C(x) ((x) & (~BITS_BSSID3_V1_8822C))\n#define BIT_GET_BSSID3_V1_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_BSSID3_V1_8822C) & BIT_MASK_BSSID3_V1_8822C)\n#define BIT_SET_BSSID3_V1_8822C(x, v)                                          \\\n\t(BIT_CLEAR_BSSID3_V1_8822C(x) | BIT_BSSID3_V1_8822C(v))\n\n/* 2 REG_BSSID3_H_8822C (BSSID3 REGISTER) */\n\n#define BIT_SHIFT_BSSID3_H_V1_8822C 0\n#define BIT_MASK_BSSID3_H_V1_8822C 0xffff\n#define BIT_BSSID3_H_V1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_BSSID3_H_V1_8822C) << BIT_SHIFT_BSSID3_H_V1_8822C)\n#define BITS_BSSID3_H_V1_8822C                                                 \\\n\t(BIT_MASK_BSSID3_H_V1_8822C << BIT_SHIFT_BSSID3_H_V1_8822C)\n#define BIT_CLEAR_BSSID3_H_V1_8822C(x) ((x) & (~BITS_BSSID3_H_V1_8822C))\n#define BIT_GET_BSSID3_H_V1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_BSSID3_H_V1_8822C) & BIT_MASK_BSSID3_H_V1_8822C)\n#define BIT_SET_BSSID3_H_V1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_BSSID3_H_V1_8822C(x) | BIT_BSSID3_H_V1_8822C(v))\n\n/* 2 REG_MACID4_8822C (MAC ID4 REGISTER) */\n\n#define BIT_SHIFT_MACID4_V1_8822C 0\n#define BIT_MASK_MACID4_V1_8822C 0xffffffffL\n#define BIT_MACID4_V1_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_MACID4_V1_8822C) << BIT_SHIFT_MACID4_V1_8822C)\n#define BITS_MACID4_V1_8822C                                                   \\\n\t(BIT_MASK_MACID4_V1_8822C << BIT_SHIFT_MACID4_V1_8822C)\n#define BIT_CLEAR_MACID4_V1_8822C(x) ((x) & (~BITS_MACID4_V1_8822C))\n#define BIT_GET_MACID4_V1_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_MACID4_V1_8822C) & BIT_MASK_MACID4_V1_8822C)\n#define BIT_SET_MACID4_V1_8822C(x, v)                                          \\\n\t(BIT_CLEAR_MACID4_V1_8822C(x) | BIT_MACID4_V1_8822C(v))\n\n/* 2 REG_MACID4_H_8822C (MAC ID4 REGISTER) */\n\n#define BIT_SHIFT_MACID4_H_V1_8822C 0\n#define BIT_MASK_MACID4_H_V1_8822C 0xffff\n#define BIT_MACID4_H_V1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_MACID4_H_V1_8822C) << BIT_SHIFT_MACID4_H_V1_8822C)\n#define BITS_MACID4_H_V1_8822C                                                 \\\n\t(BIT_MASK_MACID4_H_V1_8822C << BIT_SHIFT_MACID4_H_V1_8822C)\n#define BIT_CLEAR_MACID4_H_V1_8822C(x) ((x) & (~BITS_MACID4_H_V1_8822C))\n#define BIT_GET_MACID4_H_V1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_MACID4_H_V1_8822C) & BIT_MASK_MACID4_H_V1_8822C)\n#define BIT_SET_MACID4_H_V1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_MACID4_H_V1_8822C(x) | BIT_MACID4_H_V1_8822C(v))\n\n/* 2 REG_BSSID4_8822C (BSSID4 REGISTER) */\n\n#define BIT_SHIFT_BSSID4_V1_8822C 0\n#define BIT_MASK_BSSID4_V1_8822C 0xffffffffL\n#define BIT_BSSID4_V1_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_BSSID4_V1_8822C) << BIT_SHIFT_BSSID4_V1_8822C)\n#define BITS_BSSID4_V1_8822C                                                   \\\n\t(BIT_MASK_BSSID4_V1_8822C << BIT_SHIFT_BSSID4_V1_8822C)\n#define BIT_CLEAR_BSSID4_V1_8822C(x) ((x) & (~BITS_BSSID4_V1_8822C))\n#define BIT_GET_BSSID4_V1_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_BSSID4_V1_8822C) & BIT_MASK_BSSID4_V1_8822C)\n#define BIT_SET_BSSID4_V1_8822C(x, v)                                          \\\n\t(BIT_CLEAR_BSSID4_V1_8822C(x) | BIT_BSSID4_V1_8822C(v))\n\n/* 2 REG_BSSID4_H_8822C (BSSID4 REGISTER) */\n\n#define BIT_SHIFT_BSSID4_H_V1_8822C 0\n#define BIT_MASK_BSSID4_H_V1_8822C 0xffff\n#define BIT_BSSID4_H_V1_8822C(x)                                               \\\n\t(((x) & BIT_MASK_BSSID4_H_V1_8822C) << BIT_SHIFT_BSSID4_H_V1_8822C)\n#define BITS_BSSID4_H_V1_8822C                                                 \\\n\t(BIT_MASK_BSSID4_H_V1_8822C << BIT_SHIFT_BSSID4_H_V1_8822C)\n#define BIT_CLEAR_BSSID4_H_V1_8822C(x) ((x) & (~BITS_BSSID4_H_V1_8822C))\n#define BIT_GET_BSSID4_H_V1_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_BSSID4_H_V1_8822C) & BIT_MASK_BSSID4_H_V1_8822C)\n#define BIT_SET_BSSID4_H_V1_8822C(x, v)                                        \\\n\t(BIT_CLEAR_BSSID4_H_V1_8822C(x) | BIT_BSSID4_H_V1_8822C(v))\n\n/* 2 REG_NOA_REPORT_8822C */\n\n/* 2 REG_NOA_REPORT_1_8822C */\n\n/* 2 REG_NOA_REPORT_2_8822C */\n\n/* 2 REG_NOA_REPORT_3_8822C */\n\n/* 2 REG_PWRBIT_SETTING_8822C */\n#define BIT_CLI3_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(15)\n#define BIT_CLI3_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(14)\n#define BIT_CLI3_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(13)\n#define BIT_CLI3_PWR_ST_V1_8822C BIT(12)\n#define BIT_CLI2_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(11)\n#define BIT_CLI2_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(10)\n#define BIT_CLI2_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(9)\n#define BIT_CLI2_PWR_ST_V1_8822C BIT(8)\n#define BIT_CLI1_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(7)\n#define BIT_CLI1_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(6)\n#define BIT_CLI1_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(5)\n#define BIT_CLI1_PWR_ST_V1_8822C BIT(4)\n#define BIT_CLI0_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(3)\n#define BIT_CLI0_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(2)\n#define BIT_CLI0_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(1)\n#define BIT_CLI0_PWR_ST_V1_8822C BIT(0)\n\n/* 2 REG_GENERAL_OPTION_8822C */\n#define BIT_WMAC_RXRST_NDP_TIMEOUT_8822C BIT(11)\n#define BIT_WMAC_NDP_STANDBY_WAIT_RXEND_8822C BIT(10)\n#define BIT_DUMMY_FCS_READY_MASK_EN_8822C BIT(9)\n#define BIT_RXFIFO_GNT_CUT_8822C BIT(8)\n#define BIT_DUMMY_RXD_FCS_ERROR_MASK_EN_V1_8822C BIT(7)\n#define BIT_WMAC_EXT_DBG_SEL_V1_8822C BIT(6)\n#define BIT_WMAC_FIX_FIRST_MPDU_WITH_PHYSTS_8822C BIT(5)\n#define BIT_RX_DMA_BYPASS_CHECK_DATABYPASS_CHECK_DATA_8822C BIT(4)\n#define BIT_RX_DMA_BYPASS_CHECK_MGTBIT_RX_DMA_BYPASS_CHECK_MGT_8822C BIT(3)\n#define BIT_TXSERV_FIELD_SEL_8822C BIT(2)\n#define BIT_RXVHT_LEN_SEL_8822C BIT(1)\n#define BIT_RXMIC_PROTECT_EN_8822C BIT(0)\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_CSI_RRSR_8822C */\n#define BIT_CSI_LDPC_EN_8822C BIT(29)\n#define BIT_CSI_STBC_EN_8822C BIT(28)\n\n#define BIT_SHIFT_CSI_RRSC_BITMAP_8822C 4\n#define BIT_MASK_CSI_RRSC_BITMAP_8822C 0xffffff\n#define BIT_CSI_RRSC_BITMAP_8822C(x)                                           \\\n\t(((x) & BIT_MASK_CSI_RRSC_BITMAP_8822C)                                \\\n\t << BIT_SHIFT_CSI_RRSC_BITMAP_8822C)\n#define BITS_CSI_RRSC_BITMAP_8822C                                             \\\n\t(BIT_MASK_CSI_RRSC_BITMAP_8822C << BIT_SHIFT_CSI_RRSC_BITMAP_8822C)\n#define BIT_CLEAR_CSI_RRSC_BITMAP_8822C(x) ((x) & (~BITS_CSI_RRSC_BITMAP_8822C))\n#define BIT_GET_CSI_RRSC_BITMAP_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_CSI_RRSC_BITMAP_8822C) &                            \\\n\t BIT_MASK_CSI_RRSC_BITMAP_8822C)\n#define BIT_SET_CSI_RRSC_BITMAP_8822C(x, v)                                    \\\n\t(BIT_CLEAR_CSI_RRSC_BITMAP_8822C(x) | BIT_CSI_RRSC_BITMAP_8822C(v))\n\n#define BIT_SHIFT_OFDM_LEN_TH_8822C 0\n#define BIT_MASK_OFDM_LEN_TH_8822C 0xf\n#define BIT_OFDM_LEN_TH_8822C(x)                                               \\\n\t(((x) & BIT_MASK_OFDM_LEN_TH_8822C) << BIT_SHIFT_OFDM_LEN_TH_8822C)\n#define BITS_OFDM_LEN_TH_8822C                                                 \\\n\t(BIT_MASK_OFDM_LEN_TH_8822C << BIT_SHIFT_OFDM_LEN_TH_8822C)\n#define BIT_CLEAR_OFDM_LEN_TH_8822C(x) ((x) & (~BITS_OFDM_LEN_TH_8822C))\n#define BIT_GET_OFDM_LEN_TH_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_OFDM_LEN_TH_8822C) & BIT_MASK_OFDM_LEN_TH_8822C)\n#define BIT_SET_OFDM_LEN_TH_8822C(x, v)                                        \\\n\t(BIT_CLEAR_OFDM_LEN_TH_8822C(x) | BIT_OFDM_LEN_TH_8822C(v))\n\n/* 2 REG_MU_BF_OPTION_8822C */\n#define BIT_WMAC_RESP_NONSTA1_DIS_8822C BIT(7)\n#define BIT_WMAC_TXMU_ACKPOLICY_EN_8822C BIT(6)\n\n#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C 4\n#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C 0x3\n#define BIT_WMAC_TXMU_ACKPOLICY_8822C(x)                                       \\\n\t(((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C)                            \\\n\t << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C)\n#define BITS_WMAC_TXMU_ACKPOLICY_8822C                                         \\\n\t(BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C                                    \\\n\t << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C)\n#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822C(x)                                 \\\n\t((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8822C))\n#define BIT_GET_WMAC_TXMU_ACKPOLICY_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C) &                        \\\n\t BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C)\n#define BIT_SET_WMAC_TXMU_ACKPOLICY_8822C(x, v)                                \\\n\t(BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822C(x) |                              \\\n\t BIT_WMAC_TXMU_ACKPOLICY_8822C(v))\n\n#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C 1\n#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C 0x7\n#define BIT_WMAC_MU_BFEE_PORT_SEL_8822C(x)                                     \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C)                          \\\n\t << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C)\n#define BITS_WMAC_MU_BFEE_PORT_SEL_8822C                                       \\\n\t(BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C                                  \\\n\t << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C)\n#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822C(x)                               \\\n\t((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8822C))\n#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8822C(x)                                 \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C) &                      \\\n\t BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C)\n#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8822C(x, v)                              \\\n\t(BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822C(x) |                            \\\n\t BIT_WMAC_MU_BFEE_PORT_SEL_8822C(v))\n\n#define BIT_WMAC_MU_BFEE_DIS_8822C BIT(0)\n\n/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8822C */\n\n#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C 0\n#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C 0xff\n#define BIT_WMAC_PAUSE_BB_CLR_TH_8822C(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C)                           \\\n\t << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C)\n#define BITS_WMAC_PAUSE_BB_CLR_TH_8822C                                        \\\n\t(BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C                                   \\\n\t << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C)\n#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822C(x)                                \\\n\t((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8822C))\n#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C) &                       \\\n\t BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C)\n#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8822C(x, v)                               \\\n\t(BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822C(x) |                             \\\n\t BIT_WMAC_PAUSE_BB_CLR_TH_8822C(v))\n\n/* 2 REG__WMAC_MULBK_BUF_8822C */\n\n#define BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C 0\n#define BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C 0xff\n#define BIT_WMAC_MULBK_PAGE_SIZE_8822C(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C)                           \\\n\t << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C)\n#define BITS_WMAC_MULBK_PAGE_SIZE_8822C                                        \\\n\t(BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C                                   \\\n\t << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C)\n#define BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8822C(x)                                \\\n\t((x) & (~BITS_WMAC_MULBK_PAGE_SIZE_8822C))\n#define BIT_GET_WMAC_MULBK_PAGE_SIZE_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C) &                       \\\n\t BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C)\n#define BIT_SET_WMAC_MULBK_PAGE_SIZE_8822C(x, v)                               \\\n\t(BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8822C(x) |                             \\\n\t BIT_WMAC_MULBK_PAGE_SIZE_8822C(v))\n\n/* 2 REG_WMAC_MU_OPTION_8822C */\n\n/* 2 REG_WMAC_MU_BF_CTL_8822C */\n#define BIT_WMAC_INVLD_BFPRT_CHK_8822C BIT(15)\n#define BIT_WMAC_RETXBFRPTSEQ_UPD_8822C BIT(14)\n\n#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C 12\n#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C 0x3\n#define BIT_WMAC_MU_BFRPTSEG_SEL_8822C(x)                                      \\\n\t(((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C)                           \\\n\t << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C)\n#define BITS_WMAC_MU_BFRPTSEG_SEL_8822C                                        \\\n\t(BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C                                   \\\n\t << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C)\n#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822C(x)                                \\\n\t((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8822C))\n#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C) &                       \\\n\t BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C)\n#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8822C(x, v)                               \\\n\t(BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822C(x) |                             \\\n\t BIT_WMAC_MU_BFRPTSEG_SEL_8822C(v))\n\n#define BIT_SHIFT_WMAC_MU_BF_MYAID_8822C 0\n#define BIT_MASK_WMAC_MU_BF_MYAID_8822C 0xfff\n#define BIT_WMAC_MU_BF_MYAID_8822C(x)                                          \\\n\t(((x) & BIT_MASK_WMAC_MU_BF_MYAID_8822C)                               \\\n\t << BIT_SHIFT_WMAC_MU_BF_MYAID_8822C)\n#define BITS_WMAC_MU_BF_MYAID_8822C                                            \\\n\t(BIT_MASK_WMAC_MU_BF_MYAID_8822C << BIT_SHIFT_WMAC_MU_BF_MYAID_8822C)\n#define BIT_CLEAR_WMAC_MU_BF_MYAID_8822C(x)                                    \\\n\t((x) & (~BITS_WMAC_MU_BF_MYAID_8822C))\n#define BIT_GET_WMAC_MU_BF_MYAID_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8822C) &                           \\\n\t BIT_MASK_WMAC_MU_BF_MYAID_8822C)\n#define BIT_SET_WMAC_MU_BF_MYAID_8822C(x, v)                                   \\\n\t(BIT_CLEAR_WMAC_MU_BF_MYAID_8822C(x) | BIT_WMAC_MU_BF_MYAID_8822C(v))\n\n/* 2 REG_WMAC_MU_BFRPT_PARA_8822C */\n\n#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C 13\n#define BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C 0x7\n#define BIT_BFRPT_PARA_USERID_SEL_V1_8822C(x)                                  \\\n\t(((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C)                       \\\n\t << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C)\n#define BITS_BFRPT_PARA_USERID_SEL_V1_8822C                                    \\\n\t(BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C                               \\\n\t << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C)\n#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8822C(x)                            \\\n\t((x) & (~BITS_BFRPT_PARA_USERID_SEL_V1_8822C))\n#define BIT_GET_BFRPT_PARA_USERID_SEL_V1_8822C(x)                              \\\n\t(((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C) &                   \\\n\t BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C)\n#define BIT_SET_BFRPT_PARA_USERID_SEL_V1_8822C(x, v)                           \\\n\t(BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8822C(x) |                         \\\n\t BIT_BFRPT_PARA_USERID_SEL_V1_8822C(v))\n\n#define BIT_SHIFT_BFRPT_PARA_V1_8822C 0\n#define BIT_MASK_BFRPT_PARA_V1_8822C 0x1fff\n#define BIT_BFRPT_PARA_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_BFRPT_PARA_V1_8822C) << BIT_SHIFT_BFRPT_PARA_V1_8822C)\n#define BITS_BFRPT_PARA_V1_8822C                                               \\\n\t(BIT_MASK_BFRPT_PARA_V1_8822C << BIT_SHIFT_BFRPT_PARA_V1_8822C)\n#define BIT_CLEAR_BFRPT_PARA_V1_8822C(x) ((x) & (~BITS_BFRPT_PARA_V1_8822C))\n#define BIT_GET_BFRPT_PARA_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BFRPT_PARA_V1_8822C) & BIT_MASK_BFRPT_PARA_V1_8822C)\n#define BIT_SET_BFRPT_PARA_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_BFRPT_PARA_V1_8822C(x) | BIT_BFRPT_PARA_V1_8822C(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8822C */\n#define BIT_STATUS_BFEE2_8822C BIT(10)\n#define BIT_WMAC_MU_BFEE2_EN_8822C BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C 0\n#define BIT_MASK_WMAC_MU_BFEE2_AID_8822C 0x1ff\n#define BIT_WMAC_MU_BFEE2_AID_8822C(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8822C)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C)\n#define BITS_WMAC_MU_BFEE2_AID_8822C                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE2_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C)\n#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8822C(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE2_AID_8822C))\n#define BIT_GET_WMAC_MU_BFEE2_AID_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE2_AID_8822C)\n#define BIT_SET_WMAC_MU_BFEE2_AID_8822C(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE2_AID_8822C(x) | BIT_WMAC_MU_BFEE2_AID_8822C(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8822C */\n#define BIT_STATUS_BFEE3_8822C BIT(10)\n#define BIT_WMAC_MU_BFEE3_EN_8822C BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C 0\n#define BIT_MASK_WMAC_MU_BFEE3_AID_8822C 0x1ff\n#define BIT_WMAC_MU_BFEE3_AID_8822C(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8822C)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C)\n#define BITS_WMAC_MU_BFEE3_AID_8822C                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE3_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C)\n#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8822C(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE3_AID_8822C))\n#define BIT_GET_WMAC_MU_BFEE3_AID_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE3_AID_8822C)\n#define BIT_SET_WMAC_MU_BFEE3_AID_8822C(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE3_AID_8822C(x) | BIT_WMAC_MU_BFEE3_AID_8822C(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8822C */\n#define BIT_STATUS_BFEE4_8822C BIT(10)\n#define BIT_WMAC_MU_BFEE4_EN_8822C BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C 0\n#define BIT_MASK_WMAC_MU_BFEE4_AID_8822C 0x1ff\n#define BIT_WMAC_MU_BFEE4_AID_8822C(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8822C)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C)\n#define BITS_WMAC_MU_BFEE4_AID_8822C                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE4_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C)\n#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8822C(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE4_AID_8822C))\n#define BIT_GET_WMAC_MU_BFEE4_AID_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE4_AID_8822C)\n#define BIT_SET_WMAC_MU_BFEE4_AID_8822C(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE4_AID_8822C(x) | BIT_WMAC_MU_BFEE4_AID_8822C(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8822C */\n#define BIT_BIT_STATUS_BFEE5_8822C BIT(10)\n#define BIT_WMAC_MU_BFEE5_EN_8822C BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C 0\n#define BIT_MASK_WMAC_MU_BFEE5_AID_8822C 0x1ff\n#define BIT_WMAC_MU_BFEE5_AID_8822C(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8822C)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C)\n#define BITS_WMAC_MU_BFEE5_AID_8822C                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE5_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C)\n#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8822C(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE5_AID_8822C))\n#define BIT_GET_WMAC_MU_BFEE5_AID_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE5_AID_8822C)\n#define BIT_SET_WMAC_MU_BFEE5_AID_8822C(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE5_AID_8822C(x) | BIT_WMAC_MU_BFEE5_AID_8822C(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8822C */\n#define BIT_STATUS_BFEE6_8822C BIT(10)\n#define BIT_WMAC_MU_BFEE6_EN_8822C BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C 0\n#define BIT_MASK_WMAC_MU_BFEE6_AID_8822C 0x1ff\n#define BIT_WMAC_MU_BFEE6_AID_8822C(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8822C)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C)\n#define BITS_WMAC_MU_BFEE6_AID_8822C                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE6_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C)\n#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8822C(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE6_AID_8822C))\n#define BIT_GET_WMAC_MU_BFEE6_AID_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE6_AID_8822C)\n#define BIT_SET_WMAC_MU_BFEE6_AID_8822C(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE6_AID_8822C(x) | BIT_WMAC_MU_BFEE6_AID_8822C(v))\n\n/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8822C */\n#define BIT_STATUS_BFEE7_8822C BIT(10)\n#define BIT_WMAC_MU_BFEE7_EN_8822C BIT(9)\n\n#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C 0\n#define BIT_MASK_WMAC_MU_BFEE7_AID_8822C 0x1ff\n#define BIT_WMAC_MU_BFEE7_AID_8822C(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8822C)                              \\\n\t << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C)\n#define BITS_WMAC_MU_BFEE7_AID_8822C                                           \\\n\t(BIT_MASK_WMAC_MU_BFEE7_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C)\n#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8822C(x)                                   \\\n\t((x) & (~BITS_WMAC_MU_BFEE7_AID_8822C))\n#define BIT_GET_WMAC_MU_BFEE7_AID_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C) &                          \\\n\t BIT_MASK_WMAC_MU_BFEE7_AID_8822C)\n#define BIT_SET_WMAC_MU_BFEE7_AID_8822C(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_MU_BFEE7_AID_8822C(x) | BIT_WMAC_MU_BFEE7_AID_8822C(v))\n\n/* 2 REG_WMAC_BB_STOP_RX_COUNTER_8822C */\n#define BIT_RST_ALL_COUNTER_8822C BIT(31)\n\n#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C 16\n#define BIT_MASK_ABORT_RX_VBON_COUNTER_8822C 0xff\n#define BIT_ABORT_RX_VBON_COUNTER_8822C(x)                                     \\\n\t(((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8822C)                          \\\n\t << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C)\n#define BITS_ABORT_RX_VBON_COUNTER_8822C                                       \\\n\t(BIT_MASK_ABORT_RX_VBON_COUNTER_8822C                                  \\\n\t << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C)\n#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822C(x)                               \\\n\t((x) & (~BITS_ABORT_RX_VBON_COUNTER_8822C))\n#define BIT_GET_ABORT_RX_VBON_COUNTER_8822C(x)                                 \\\n\t(((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C) &                      \\\n\t BIT_MASK_ABORT_RX_VBON_COUNTER_8822C)\n#define BIT_SET_ABORT_RX_VBON_COUNTER_8822C(x, v)                              \\\n\t(BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822C(x) |                            \\\n\t BIT_ABORT_RX_VBON_COUNTER_8822C(v))\n\n#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C 8\n#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C 0xff\n#define BIT_ABORT_RX_RDRDY_COUNTER_8822C(x)                                    \\\n\t(((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C)                         \\\n\t << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C)\n#define BITS_ABORT_RX_RDRDY_COUNTER_8822C                                      \\\n\t(BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C                                 \\\n\t << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C)\n#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822C(x)                              \\\n\t((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8822C))\n#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8822C(x)                                \\\n\t(((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C) &                     \\\n\t BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C)\n#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8822C(x, v)                             \\\n\t(BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822C(x) |                           \\\n\t BIT_ABORT_RX_RDRDY_COUNTER_8822C(v))\n\n#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C 0\n#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C 0xff\n#define BIT_VBON_EARLY_FALLING_COUNTER_8822C(x)                                \\\n\t(((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C)                     \\\n\t << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C)\n#define BITS_VBON_EARLY_FALLING_COUNTER_8822C                                  \\\n\t(BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C                             \\\n\t << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C)\n#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822C(x)                          \\\n\t((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8822C))\n#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8822C(x)                            \\\n\t(((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C) &                 \\\n\t BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C)\n#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8822C(x, v)                         \\\n\t(BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822C(x) |                       \\\n\t BIT_VBON_EARLY_FALLING_COUNTER_8822C(v))\n\n/* 2 REG_WMAC_PLCP_MONITOR_8822C */\n#define BIT_WMAC_PLCP_TRX_SEL_8822C BIT(31)\n\n#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C 28\n#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C 0x7\n#define BIT_WMAC_PLCP_RDSIG_SEL_8822C(x)                                       \\\n\t(((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C)                            \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C)\n#define BITS_WMAC_PLCP_RDSIG_SEL_8822C                                         \\\n\t(BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C                                    \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C)\n#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822C(x)                                 \\\n\t((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8822C))\n#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C) &                        \\\n\t BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C)\n#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8822C(x, v)                                \\\n\t(BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822C(x) |                              \\\n\t BIT_WMAC_PLCP_RDSIG_SEL_8822C(v))\n\n#define BIT_SHIFT_WMAC_RATE_IDX_8822C 24\n#define BIT_MASK_WMAC_RATE_IDX_8822C 0xf\n#define BIT_WMAC_RATE_IDX_8822C(x)                                             \\\n\t(((x) & BIT_MASK_WMAC_RATE_IDX_8822C) << BIT_SHIFT_WMAC_RATE_IDX_8822C)\n#define BITS_WMAC_RATE_IDX_8822C                                               \\\n\t(BIT_MASK_WMAC_RATE_IDX_8822C << BIT_SHIFT_WMAC_RATE_IDX_8822C)\n#define BIT_CLEAR_WMAC_RATE_IDX_8822C(x) ((x) & (~BITS_WMAC_RATE_IDX_8822C))\n#define BIT_GET_WMAC_RATE_IDX_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_WMAC_RATE_IDX_8822C) & BIT_MASK_WMAC_RATE_IDX_8822C)\n#define BIT_SET_WMAC_RATE_IDX_8822C(x, v)                                      \\\n\t(BIT_CLEAR_WMAC_RATE_IDX_8822C(x) | BIT_WMAC_RATE_IDX_8822C(v))\n\n#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822C 0\n#define BIT_MASK_WMAC_PLCP_RDSIG_8822C 0xffffff\n#define BIT_WMAC_PLCP_RDSIG_8822C(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822C)                                \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C)\n#define BITS_WMAC_PLCP_RDSIG_8822C                                             \\\n\t(BIT_MASK_WMAC_PLCP_RDSIG_8822C << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C)\n#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822C))\n#define BIT_GET_WMAC_PLCP_RDSIG_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) &                            \\\n\t BIT_MASK_WMAC_PLCP_RDSIG_8822C)\n#define BIT_SET_WMAC_PLCP_RDSIG_8822C(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) | BIT_WMAC_PLCP_RDSIG_8822C(v))\n\n/* 2 REG_WMAC_PLCP_MONITOR_MUTX_8822C */\n#define BIT_WMAC_MUTX_IDX_8822C BIT(24)\n\n#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822C 0\n#define BIT_MASK_WMAC_PLCP_RDSIG_8822C 0xffffff\n#define BIT_WMAC_PLCP_RDSIG_8822C(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822C)                                \\\n\t << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C)\n#define BITS_WMAC_PLCP_RDSIG_8822C                                             \\\n\t(BIT_MASK_WMAC_PLCP_RDSIG_8822C << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C)\n#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822C))\n#define BIT_GET_WMAC_PLCP_RDSIG_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) &                            \\\n\t BIT_MASK_WMAC_PLCP_RDSIG_8822C)\n#define BIT_SET_WMAC_PLCP_RDSIG_8822C(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) | BIT_WMAC_PLCP_RDSIG_8822C(v))\n\n/* 2 REG_WMAC_CSIDMA_CFG_8822C */\n\n#define BIT_SHIFT_CSI_SEG_SIZE_8822C 16\n#define BIT_MASK_CSI_SEG_SIZE_8822C 0xfff\n#define BIT_CSI_SEG_SIZE_8822C(x)                                              \\\n\t(((x) & BIT_MASK_CSI_SEG_SIZE_8822C) << BIT_SHIFT_CSI_SEG_SIZE_8822C)\n#define BITS_CSI_SEG_SIZE_8822C                                                \\\n\t(BIT_MASK_CSI_SEG_SIZE_8822C << BIT_SHIFT_CSI_SEG_SIZE_8822C)\n#define BIT_CLEAR_CSI_SEG_SIZE_8822C(x) ((x) & (~BITS_CSI_SEG_SIZE_8822C))\n#define BIT_GET_CSI_SEG_SIZE_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_CSI_SEG_SIZE_8822C) & BIT_MASK_CSI_SEG_SIZE_8822C)\n#define BIT_SET_CSI_SEG_SIZE_8822C(x, v)                                       \\\n\t(BIT_CLEAR_CSI_SEG_SIZE_8822C(x) | BIT_CSI_SEG_SIZE_8822C(v))\n\n#define BIT_SHIFT_CSI_START_PAGE_8822C 0\n#define BIT_MASK_CSI_START_PAGE_8822C 0xfff\n#define BIT_CSI_START_PAGE_8822C(x)                                            \\\n\t(((x) & BIT_MASK_CSI_START_PAGE_8822C)                                 \\\n\t << BIT_SHIFT_CSI_START_PAGE_8822C)\n#define BITS_CSI_START_PAGE_8822C                                              \\\n\t(BIT_MASK_CSI_START_PAGE_8822C << BIT_SHIFT_CSI_START_PAGE_8822C)\n#define BIT_CLEAR_CSI_START_PAGE_8822C(x) ((x) & (~BITS_CSI_START_PAGE_8822C))\n#define BIT_GET_CSI_START_PAGE_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_CSI_START_PAGE_8822C) &                             \\\n\t BIT_MASK_CSI_START_PAGE_8822C)\n#define BIT_SET_CSI_START_PAGE_8822C(x, v)                                     \\\n\t(BIT_CLEAR_CSI_START_PAGE_8822C(x) | BIT_CSI_START_PAGE_8822C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_0_8822C (TA0 REGISTER) */\n\n#define BIT_SHIFT_TA0_V1_8822C 0\n#define BIT_MASK_TA0_V1_8822C 0xffffffffL\n#define BIT_TA0_V1_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_TA0_V1_8822C) << BIT_SHIFT_TA0_V1_8822C)\n#define BITS_TA0_V1_8822C (BIT_MASK_TA0_V1_8822C << BIT_SHIFT_TA0_V1_8822C)\n#define BIT_CLEAR_TA0_V1_8822C(x) ((x) & (~BITS_TA0_V1_8822C))\n#define BIT_GET_TA0_V1_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_TA0_V1_8822C) & BIT_MASK_TA0_V1_8822C)\n#define BIT_SET_TA0_V1_8822C(x, v)                                             \\\n\t(BIT_CLEAR_TA0_V1_8822C(x) | BIT_TA0_V1_8822C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_0_H_8822C (TA0 REGISTER) */\n\n#define BIT_SHIFT_TA0_H_V1_8822C 0\n#define BIT_MASK_TA0_H_V1_8822C 0xffff\n#define BIT_TA0_H_V1_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_TA0_H_V1_8822C) << BIT_SHIFT_TA0_H_V1_8822C)\n#define BITS_TA0_H_V1_8822C                                                    \\\n\t(BIT_MASK_TA0_H_V1_8822C << BIT_SHIFT_TA0_H_V1_8822C)\n#define BIT_CLEAR_TA0_H_V1_8822C(x) ((x) & (~BITS_TA0_H_V1_8822C))\n#define BIT_GET_TA0_H_V1_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TA0_H_V1_8822C) & BIT_MASK_TA0_H_V1_8822C)\n#define BIT_SET_TA0_H_V1_8822C(x, v)                                           \\\n\t(BIT_CLEAR_TA0_H_V1_8822C(x) | BIT_TA0_H_V1_8822C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_1_8822C (TA1 REGISTER) */\n\n#define BIT_SHIFT_TA1_V1_8822C 0\n#define BIT_MASK_TA1_V1_8822C 0xffffffffL\n#define BIT_TA1_V1_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_TA1_V1_8822C) << BIT_SHIFT_TA1_V1_8822C)\n#define BITS_TA1_V1_8822C (BIT_MASK_TA1_V1_8822C << BIT_SHIFT_TA1_V1_8822C)\n#define BIT_CLEAR_TA1_V1_8822C(x) ((x) & (~BITS_TA1_V1_8822C))\n#define BIT_GET_TA1_V1_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_TA1_V1_8822C) & BIT_MASK_TA1_V1_8822C)\n#define BIT_SET_TA1_V1_8822C(x, v)                                             \\\n\t(BIT_CLEAR_TA1_V1_8822C(x) | BIT_TA1_V1_8822C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_1_H_8822C (TA1 REGISTER) */\n\n#define BIT_SHIFT_TA1_H_V1_8822C 0\n#define BIT_MASK_TA1_H_V1_8822C 0xffff\n#define BIT_TA1_H_V1_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_TA1_H_V1_8822C) << BIT_SHIFT_TA1_H_V1_8822C)\n#define BITS_TA1_H_V1_8822C                                                    \\\n\t(BIT_MASK_TA1_H_V1_8822C << BIT_SHIFT_TA1_H_V1_8822C)\n#define BIT_CLEAR_TA1_H_V1_8822C(x) ((x) & (~BITS_TA1_H_V1_8822C))\n#define BIT_GET_TA1_H_V1_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TA1_H_V1_8822C) & BIT_MASK_TA1_H_V1_8822C)\n#define BIT_SET_TA1_H_V1_8822C(x, v)                                           \\\n\t(BIT_CLEAR_TA1_H_V1_8822C(x) | BIT_TA1_H_V1_8822C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_2_8822C (TA2 REGISTER) */\n\n#define BIT_SHIFT_TA2_V1_8822C 0\n#define BIT_MASK_TA2_V1_8822C 0xffffffffL\n#define BIT_TA2_V1_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_TA2_V1_8822C) << BIT_SHIFT_TA2_V1_8822C)\n#define BITS_TA2_V1_8822C (BIT_MASK_TA2_V1_8822C << BIT_SHIFT_TA2_V1_8822C)\n#define BIT_CLEAR_TA2_V1_8822C(x) ((x) & (~BITS_TA2_V1_8822C))\n#define BIT_GET_TA2_V1_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_TA2_V1_8822C) & BIT_MASK_TA2_V1_8822C)\n#define BIT_SET_TA2_V1_8822C(x, v)                                             \\\n\t(BIT_CLEAR_TA2_V1_8822C(x) | BIT_TA2_V1_8822C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_2_H_8822C (TA2 REGISTER) */\n\n#define BIT_SHIFT_TA2_H_V1_8822C 0\n#define BIT_MASK_TA2_H_V1_8822C 0xffff\n#define BIT_TA2_H_V1_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_TA2_H_V1_8822C) << BIT_SHIFT_TA2_H_V1_8822C)\n#define BITS_TA2_H_V1_8822C                                                    \\\n\t(BIT_MASK_TA2_H_V1_8822C << BIT_SHIFT_TA2_H_V1_8822C)\n#define BIT_CLEAR_TA2_H_V1_8822C(x) ((x) & (~BITS_TA2_H_V1_8822C))\n#define BIT_GET_TA2_H_V1_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TA2_H_V1_8822C) & BIT_MASK_TA2_H_V1_8822C)\n#define BIT_SET_TA2_H_V1_8822C(x, v)                                           \\\n\t(BIT_CLEAR_TA2_H_V1_8822C(x) | BIT_TA2_H_V1_8822C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_3_8822C (TA3 REGISTER) */\n\n#define BIT_SHIFT_TA2_V1_8822C 0\n#define BIT_MASK_TA2_V1_8822C 0xffffffffL\n#define BIT_TA2_V1_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_TA2_V1_8822C) << BIT_SHIFT_TA2_V1_8822C)\n#define BITS_TA2_V1_8822C (BIT_MASK_TA2_V1_8822C << BIT_SHIFT_TA2_V1_8822C)\n#define BIT_CLEAR_TA2_V1_8822C(x) ((x) & (~BITS_TA2_V1_8822C))\n#define BIT_GET_TA2_V1_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_TA2_V1_8822C) & BIT_MASK_TA2_V1_8822C)\n#define BIT_SET_TA2_V1_8822C(x, v)                                             \\\n\t(BIT_CLEAR_TA2_V1_8822C(x) | BIT_TA2_V1_8822C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_3_H_8822C (TA3 REGISTER) */\n\n#define BIT_SHIFT_TA3_H_V1_8822C 0\n#define BIT_MASK_TA3_H_V1_8822C 0xffff\n#define BIT_TA3_H_V1_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_TA3_H_V1_8822C) << BIT_SHIFT_TA3_H_V1_8822C)\n#define BITS_TA3_H_V1_8822C                                                    \\\n\t(BIT_MASK_TA3_H_V1_8822C << BIT_SHIFT_TA3_H_V1_8822C)\n#define BIT_CLEAR_TA3_H_V1_8822C(x) ((x) & (~BITS_TA3_H_V1_8822C))\n#define BIT_GET_TA3_H_V1_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TA3_H_V1_8822C) & BIT_MASK_TA3_H_V1_8822C)\n#define BIT_SET_TA3_H_V1_8822C(x, v)                                           \\\n\t(BIT_CLEAR_TA3_H_V1_8822C(x) | BIT_TA3_H_V1_8822C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_4_8822C (TA4 REGISTER) */\n\n#define BIT_SHIFT_TA4_V1_8822C 0\n#define BIT_MASK_TA4_V1_8822C 0xffffffffL\n#define BIT_TA4_V1_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_TA4_V1_8822C) << BIT_SHIFT_TA4_V1_8822C)\n#define BITS_TA4_V1_8822C (BIT_MASK_TA4_V1_8822C << BIT_SHIFT_TA4_V1_8822C)\n#define BIT_CLEAR_TA4_V1_8822C(x) ((x) & (~BITS_TA4_V1_8822C))\n#define BIT_GET_TA4_V1_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_TA4_V1_8822C) & BIT_MASK_TA4_V1_8822C)\n#define BIT_SET_TA4_V1_8822C(x, v)                                             \\\n\t(BIT_CLEAR_TA4_V1_8822C(x) | BIT_TA4_V1_8822C(v))\n\n/* 2 REG_TRANSMIT_ADDRSS_4_H_8822C (TA4 REGISTER) */\n\n#define BIT_SHIFT_TA4_H_V1_8822C 0\n#define BIT_MASK_TA4_H_V1_8822C 0xffff\n#define BIT_TA4_H_V1_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_TA4_H_V1_8822C) << BIT_SHIFT_TA4_H_V1_8822C)\n#define BITS_TA4_H_V1_8822C                                                    \\\n\t(BIT_MASK_TA4_H_V1_8822C << BIT_SHIFT_TA4_H_V1_8822C)\n#define BIT_CLEAR_TA4_H_V1_8822C(x) ((x) & (~BITS_TA4_H_V1_8822C))\n#define BIT_GET_TA4_H_V1_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_TA4_H_V1_8822C) & BIT_MASK_TA4_H_V1_8822C)\n#define BIT_SET_TA4_H_V1_8822C(x, v)                                           \\\n\t(BIT_CLEAR_TA4_H_V1_8822C(x) | BIT_TA4_H_V1_8822C(v))\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_RSVD_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_MACID1_8822C */\n\n#define BIT_SHIFT_MACID1_0_8822C 0\n#define BIT_MASK_MACID1_0_8822C 0xffffffffL\n#define BIT_MACID1_0_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_MACID1_0_8822C) << BIT_SHIFT_MACID1_0_8822C)\n#define BITS_MACID1_0_8822C                                                    \\\n\t(BIT_MASK_MACID1_0_8822C << BIT_SHIFT_MACID1_0_8822C)\n#define BIT_CLEAR_MACID1_0_8822C(x) ((x) & (~BITS_MACID1_0_8822C))\n#define BIT_GET_MACID1_0_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_MACID1_0_8822C) & BIT_MASK_MACID1_0_8822C)\n#define BIT_SET_MACID1_0_8822C(x, v)                                           \\\n\t(BIT_CLEAR_MACID1_0_8822C(x) | BIT_MACID1_0_8822C(v))\n\n/* 2 REG_MACID1_1_8822C */\n\n#define BIT_SHIFT_MACID1_1_8822C 0\n#define BIT_MASK_MACID1_1_8822C 0xffff\n#define BIT_MACID1_1_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_MACID1_1_8822C) << BIT_SHIFT_MACID1_1_8822C)\n#define BITS_MACID1_1_8822C                                                    \\\n\t(BIT_MASK_MACID1_1_8822C << BIT_SHIFT_MACID1_1_8822C)\n#define BIT_CLEAR_MACID1_1_8822C(x) ((x) & (~BITS_MACID1_1_8822C))\n#define BIT_GET_MACID1_1_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_MACID1_1_8822C) & BIT_MASK_MACID1_1_8822C)\n#define BIT_SET_MACID1_1_8822C(x, v)                                           \\\n\t(BIT_CLEAR_MACID1_1_8822C(x) | BIT_MACID1_1_8822C(v))\n\n/* 2 REG_BSSID1_8822C */\n\n#define BIT_SHIFT_BSSID1_0_8822C 0\n#define BIT_MASK_BSSID1_0_8822C 0xffffffffL\n#define BIT_BSSID1_0_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_BSSID1_0_8822C) << BIT_SHIFT_BSSID1_0_8822C)\n#define BITS_BSSID1_0_8822C                                                    \\\n\t(BIT_MASK_BSSID1_0_8822C << BIT_SHIFT_BSSID1_0_8822C)\n#define BIT_CLEAR_BSSID1_0_8822C(x) ((x) & (~BITS_BSSID1_0_8822C))\n#define BIT_GET_BSSID1_0_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_BSSID1_0_8822C) & BIT_MASK_BSSID1_0_8822C)\n#define BIT_SET_BSSID1_0_8822C(x, v)                                           \\\n\t(BIT_CLEAR_BSSID1_0_8822C(x) | BIT_BSSID1_0_8822C(v))\n\n/* 2 REG_BSSID1_1_8822C */\n\n#define BIT_SHIFT_BSSID1_1_8822C 0\n#define BIT_MASK_BSSID1_1_8822C 0xffff\n#define BIT_BSSID1_1_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_BSSID1_1_8822C) << BIT_SHIFT_BSSID1_1_8822C)\n#define BITS_BSSID1_1_8822C                                                    \\\n\t(BIT_MASK_BSSID1_1_8822C << BIT_SHIFT_BSSID1_1_8822C)\n#define BIT_CLEAR_BSSID1_1_8822C(x) ((x) & (~BITS_BSSID1_1_8822C))\n#define BIT_GET_BSSID1_1_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_BSSID1_1_8822C) & BIT_MASK_BSSID1_1_8822C)\n#define BIT_SET_BSSID1_1_8822C(x, v)                                           \\\n\t(BIT_CLEAR_BSSID1_1_8822C(x) | BIT_BSSID1_1_8822C(v))\n\n/* 2 REG_BCN_PSR_RPT1_8822C */\n\n#define BIT_SHIFT_DTIM_CNT1_8822C 24\n#define BIT_MASK_DTIM_CNT1_8822C 0xff\n#define BIT_DTIM_CNT1_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_DTIM_CNT1_8822C) << BIT_SHIFT_DTIM_CNT1_8822C)\n#define BITS_DTIM_CNT1_8822C                                                   \\\n\t(BIT_MASK_DTIM_CNT1_8822C << BIT_SHIFT_DTIM_CNT1_8822C)\n#define BIT_CLEAR_DTIM_CNT1_8822C(x) ((x) & (~BITS_DTIM_CNT1_8822C))\n#define BIT_GET_DTIM_CNT1_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_DTIM_CNT1_8822C) & BIT_MASK_DTIM_CNT1_8822C)\n#define BIT_SET_DTIM_CNT1_8822C(x, v)                                          \\\n\t(BIT_CLEAR_DTIM_CNT1_8822C(x) | BIT_DTIM_CNT1_8822C(v))\n\n#define BIT_SHIFT_DTIM_PERIOD1_8822C 16\n#define BIT_MASK_DTIM_PERIOD1_8822C 0xff\n#define BIT_DTIM_PERIOD1_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DTIM_PERIOD1_8822C) << BIT_SHIFT_DTIM_PERIOD1_8822C)\n#define BITS_DTIM_PERIOD1_8822C                                                \\\n\t(BIT_MASK_DTIM_PERIOD1_8822C << BIT_SHIFT_DTIM_PERIOD1_8822C)\n#define BIT_CLEAR_DTIM_PERIOD1_8822C(x) ((x) & (~BITS_DTIM_PERIOD1_8822C))\n#define BIT_GET_DTIM_PERIOD1_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DTIM_PERIOD1_8822C) & BIT_MASK_DTIM_PERIOD1_8822C)\n#define BIT_SET_DTIM_PERIOD1_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DTIM_PERIOD1_8822C(x) | BIT_DTIM_PERIOD1_8822C(v))\n\n#define BIT_DTIM1_8822C BIT(15)\n#define BIT_TIM1_8822C BIT(14)\n#define BIT_BCN_VALID_V2_8822C BIT(13)\n\n#define BIT_SHIFT_PS_AID_1_8822C 0\n#define BIT_MASK_PS_AID_1_8822C 0x7ff\n#define BIT_PS_AID_1_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_PS_AID_1_8822C) << BIT_SHIFT_PS_AID_1_8822C)\n#define BITS_PS_AID_1_8822C                                                    \\\n\t(BIT_MASK_PS_AID_1_8822C << BIT_SHIFT_PS_AID_1_8822C)\n#define BIT_CLEAR_PS_AID_1_8822C(x) ((x) & (~BITS_PS_AID_1_8822C))\n#define BIT_GET_PS_AID_1_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_PS_AID_1_8822C) & BIT_MASK_PS_AID_1_8822C)\n#define BIT_SET_PS_AID_1_8822C(x, v)                                           \\\n\t(BIT_CLEAR_PS_AID_1_8822C(x) | BIT_PS_AID_1_8822C(v))\n\n/* 2 REG_ASSOCIATED_BFMEE_SEL_8822C */\n#define BIT_TXUSER_ID1_8822C BIT(25)\n\n#define BIT_SHIFT_AID1_8822C 16\n#define BIT_MASK_AID1_8822C 0x1ff\n#define BIT_AID1_8822C(x) (((x) & BIT_MASK_AID1_8822C) << BIT_SHIFT_AID1_8822C)\n#define BITS_AID1_8822C (BIT_MASK_AID1_8822C << BIT_SHIFT_AID1_8822C)\n#define BIT_CLEAR_AID1_8822C(x) ((x) & (~BITS_AID1_8822C))\n#define BIT_GET_AID1_8822C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AID1_8822C) & BIT_MASK_AID1_8822C)\n#define BIT_SET_AID1_8822C(x, v) (BIT_CLEAR_AID1_8822C(x) | BIT_AID1_8822C(v))\n\n#define BIT_TXUSER_ID0_8822C BIT(9)\n\n#define BIT_SHIFT_AID0_8822C 0\n#define BIT_MASK_AID0_8822C 0x1ff\n#define BIT_AID0_8822C(x) (((x) & BIT_MASK_AID0_8822C) << BIT_SHIFT_AID0_8822C)\n#define BITS_AID0_8822C (BIT_MASK_AID0_8822C << BIT_SHIFT_AID0_8822C)\n#define BIT_CLEAR_AID0_8822C(x) ((x) & (~BITS_AID0_8822C))\n#define BIT_GET_AID0_8822C(x)                                                  \\\n\t(((x) >> BIT_SHIFT_AID0_8822C) & BIT_MASK_AID0_8822C)\n#define BIT_SET_AID0_8822C(x, v) (BIT_CLEAR_AID0_8822C(x) | BIT_AID0_8822C(v))\n\n/* 2 REG_SND_PTCL_CTRL_8822C */\n\n#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C 24\n#define BIT_MASK_NDP_RX_STANDBY_TIMER_8822C 0xff\n#define BIT_NDP_RX_STANDBY_TIMER_8822C(x)                                      \\\n\t(((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822C)                           \\\n\t << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C)\n#define BITS_NDP_RX_STANDBY_TIMER_8822C                                        \\\n\t(BIT_MASK_NDP_RX_STANDBY_TIMER_8822C                                   \\\n\t << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C)\n#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822C(x)                                \\\n\t((x) & (~BITS_NDP_RX_STANDBY_TIMER_8822C))\n#define BIT_GET_NDP_RX_STANDBY_TIMER_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C) &                       \\\n\t BIT_MASK_NDP_RX_STANDBY_TIMER_8822C)\n#define BIT_SET_NDP_RX_STANDBY_TIMER_8822C(x, v)                               \\\n\t(BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822C(x) |                             \\\n\t BIT_NDP_RX_STANDBY_TIMER_8822C(v))\n\n#define BIT_R_WMAC_CHK_RPTPOLL_A2_DIS_8822C BIT(23)\n#define BIT_R_WMAC_CHK_UCNDPA_A2_DIS_8822C BIT(22)\n\n#define BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C 16\n#define BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C 0x3f\n#define BIT_CSI_RPT_OFFSET_HT_V1_8822C(x)                                      \\\n\t(((x) & BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C)                           \\\n\t << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C)\n#define BITS_CSI_RPT_OFFSET_HT_V1_8822C                                        \\\n\t(BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C                                   \\\n\t << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C)\n#define BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822C(x)                                \\\n\t((x) & (~BITS_CSI_RPT_OFFSET_HT_V1_8822C))\n#define BIT_GET_CSI_RPT_OFFSET_HT_V1_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C) &                       \\\n\t BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C)\n#define BIT_SET_CSI_RPT_OFFSET_HT_V1_8822C(x, v)                               \\\n\t(BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822C(x) |                             \\\n\t BIT_CSI_RPT_OFFSET_HT_V1_8822C(v))\n\n#define BIT_R_WMAC_OFFSET_RPTPOLL_EN_8822C BIT(15)\n#define BIT_R_WMAC_CSI_CHKSUM_DIS_8822C BIT(14)\n\n#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C 8\n#define BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C 0x3f\n#define BIT_R_WMAC_VHT_CATEGORY_V1_8822C(x)                                    \\\n\t(((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C)                         \\\n\t << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C)\n#define BITS_R_WMAC_VHT_CATEGORY_V1_8822C                                      \\\n\t(BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C                                 \\\n\t << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C)\n#define BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1_8822C(x)                              \\\n\t((x) & (~BITS_R_WMAC_VHT_CATEGORY_V1_8822C))\n#define BIT_GET_R_WMAC_VHT_CATEGORY_V1_8822C(x)                                \\\n\t(((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C) &                     \\\n\t BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C)\n#define BIT_SET_R_WMAC_VHT_CATEGORY_V1_8822C(x, v)                             \\\n\t(BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1_8822C(x) |                           \\\n\t BIT_R_WMAC_VHT_CATEGORY_V1_8822C(v))\n\n#define BIT_R_WMAC_USE_NSTS_8822C BIT(7)\n#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8822C BIT(6)\n#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8822C BIT(5)\n#define BIT_R_WMAC_BFPARAM_SEL_8822C BIT(4)\n#define BIT_R_WMAC_CSISEQ_SEL_8822C BIT(3)\n#define BIT_R_WMAC_CSI_WITHHTC_EN_8822C BIT(2)\n#define BIT_R_WMAC_HT_NDPA_EN_8822C BIT(1)\n#define BIT_R_WMAC_VHT_NDPA_EN_8822C BIT(0)\n\n/* 2 REG_RX_CSI_RPT_INFO_8822C */\n#define BIT_WRITE_ENABLE_8822C BIT(31)\n#define BIT_WMAC_CHECK_SOUNDING_SEQ_8822C BIT(30)\n\n#define BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C 1\n#define BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C 0xffffff\n#define BIT_VHTHT_MIMO_CTRL_FIELD_8822C(x)                                     \\\n\t(((x) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C)                          \\\n\t << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C)\n#define BITS_VHTHT_MIMO_CTRL_FIELD_8822C                                       \\\n\t(BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C                                  \\\n\t << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C)\n#define BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8822C(x)                               \\\n\t((x) & (~BITS_VHTHT_MIMO_CTRL_FIELD_8822C))\n#define BIT_GET_VHTHT_MIMO_CTRL_FIELD_8822C(x)                                 \\\n\t(((x) >> BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C) &                      \\\n\t BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C)\n#define BIT_SET_VHTHT_MIMO_CTRL_FIELD_8822C(x, v)                              \\\n\t(BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8822C(x) |                            \\\n\t BIT_VHTHT_MIMO_CTRL_FIELD_8822C(v))\n\n#define BIT_CSI_INTERRUPT_STATUS_8822C BIT(0)\n\n/* 2 REG_NS_ARP_CTRL_8822C */\n#define BIT_R_WMAC_NSARP_RSPEN_8822C BIT(15)\n#define BIT_R_WMAC_NSARP_RARP_8822C BIT(9)\n#define BIT_R_WMAC_NSARP_RIPV6_8822C BIT(8)\n\n#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C 6\n#define BIT_MASK_R_WMAC_NSARP_MODEN_8822C 0x3\n#define BIT_R_WMAC_NSARP_MODEN_8822C(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8822C)                             \\\n\t << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C)\n#define BITS_R_WMAC_NSARP_MODEN_8822C                                          \\\n\t(BIT_MASK_R_WMAC_NSARP_MODEN_8822C                                     \\\n\t << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C)\n#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8822C(x)                                  \\\n\t((x) & (~BITS_R_WMAC_NSARP_MODEN_8822C))\n#define BIT_GET_R_WMAC_NSARP_MODEN_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C) &                         \\\n\t BIT_MASK_R_WMAC_NSARP_MODEN_8822C)\n#define BIT_SET_R_WMAC_NSARP_MODEN_8822C(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_NSARP_MODEN_8822C(x) |                               \\\n\t BIT_R_WMAC_NSARP_MODEN_8822C(v))\n\n#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C 4\n#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C 0x3\n#define BIT_R_WMAC_NSARP_RSPFTP_8822C(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C)                            \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C)\n#define BITS_R_WMAC_NSARP_RSPFTP_8822C                                         \\\n\t(BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C                                    \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C)\n#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822C(x)                                 \\\n\t((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8822C))\n#define BIT_GET_R_WMAC_NSARP_RSPFTP_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C) &                        \\\n\t BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C)\n#define BIT_SET_R_WMAC_NSARP_RSPFTP_8822C(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822C(x) |                              \\\n\t BIT_R_WMAC_NSARP_RSPFTP_8822C(v))\n\n#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C 0\n#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C 0xf\n#define BIT_R_WMAC_NSARP_RSPSEC_8822C(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C)                            \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C)\n#define BITS_R_WMAC_NSARP_RSPSEC_8822C                                         \\\n\t(BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C                                    \\\n\t << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C)\n#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822C(x)                                 \\\n\t((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8822C))\n#define BIT_GET_R_WMAC_NSARP_RSPSEC_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C) &                        \\\n\t BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C)\n#define BIT_SET_R_WMAC_NSARP_RSPSEC_8822C(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822C(x) |                              \\\n\t BIT_R_WMAC_NSARP_RSPSEC_8822C(v))\n\n/* 2 REG_NS_ARP_INFO_8822C */\n#define BIT_REQ_IS_MCNS_8822C BIT(23)\n#define BIT_REQ_IS_UCNS_8822C BIT(22)\n#define BIT_REQ_IS_USNS_8822C BIT(21)\n#define BIT_REQ_IS_ARP_8822C BIT(20)\n#define BIT_EXPRSP_MH_WITHQC_8822C BIT(19)\n\n#define BIT_SHIFT_EXPRSP_SECTYPE_8822C 16\n#define BIT_MASK_EXPRSP_SECTYPE_8822C 0x7\n#define BIT_EXPRSP_SECTYPE_8822C(x)                                            \\\n\t(((x) & BIT_MASK_EXPRSP_SECTYPE_8822C)                                 \\\n\t << BIT_SHIFT_EXPRSP_SECTYPE_8822C)\n#define BITS_EXPRSP_SECTYPE_8822C                                              \\\n\t(BIT_MASK_EXPRSP_SECTYPE_8822C << BIT_SHIFT_EXPRSP_SECTYPE_8822C)\n#define BIT_CLEAR_EXPRSP_SECTYPE_8822C(x) ((x) & (~BITS_EXPRSP_SECTYPE_8822C))\n#define BIT_GET_EXPRSP_SECTYPE_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8822C) &                             \\\n\t BIT_MASK_EXPRSP_SECTYPE_8822C)\n#define BIT_SET_EXPRSP_SECTYPE_8822C(x, v)                                     \\\n\t(BIT_CLEAR_EXPRSP_SECTYPE_8822C(x) | BIT_EXPRSP_SECTYPE_8822C(v))\n\n#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C 8\n#define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C 0xff\n#define BIT_EXPRSP_CHKSM_7_TO_0_8822C(x)                                       \\\n\t(((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C)                            \\\n\t << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C)\n#define BITS_EXPRSP_CHKSM_7_TO_0_8822C                                         \\\n\t(BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C                                    \\\n\t << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C)\n#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822C(x)                                 \\\n\t((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8822C))\n#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C) &                        \\\n\t BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C)\n#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8822C(x, v)                                \\\n\t(BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822C(x) |                              \\\n\t BIT_EXPRSP_CHKSM_7_TO_0_8822C(v))\n\n#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C 0\n#define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C 0xff\n#define BIT_EXPRSP_CHKSM_15_TO_8_8822C(x)                                      \\\n\t(((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C)                           \\\n\t << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C)\n#define BITS_EXPRSP_CHKSM_15_TO_8_8822C                                        \\\n\t(BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C                                   \\\n\t << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C)\n#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822C(x)                                \\\n\t((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8822C))\n#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C) &                       \\\n\t BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C)\n#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8822C(x, v)                               \\\n\t(BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822C(x) |                             \\\n\t BIT_EXPRSP_CHKSM_15_TO_8_8822C(v))\n\n/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8822C */\n\n#define BIT_SHIFT_WMAC_ARPIP_8822C 0\n#define BIT_MASK_WMAC_ARPIP_8822C 0xffffffffL\n#define BIT_WMAC_ARPIP_8822C(x)                                                \\\n\t(((x) & BIT_MASK_WMAC_ARPIP_8822C) << BIT_SHIFT_WMAC_ARPIP_8822C)\n#define BITS_WMAC_ARPIP_8822C                                                  \\\n\t(BIT_MASK_WMAC_ARPIP_8822C << BIT_SHIFT_WMAC_ARPIP_8822C)\n#define BIT_CLEAR_WMAC_ARPIP_8822C(x) ((x) & (~BITS_WMAC_ARPIP_8822C))\n#define BIT_GET_WMAC_ARPIP_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_WMAC_ARPIP_8822C) & BIT_MASK_WMAC_ARPIP_8822C)\n#define BIT_SET_WMAC_ARPIP_8822C(x, v)                                         \\\n\t(BIT_CLEAR_WMAC_ARPIP_8822C(x) | BIT_WMAC_ARPIP_8822C(v))\n\n/* 2 REG_BEAMFORMING_INFO_NSARP_8822C */\n\n#define BIT_SHIFT_UPD_BFMEE_USERID_8822C 13\n#define BIT_MASK_UPD_BFMEE_USERID_8822C 0x7\n#define BIT_UPD_BFMEE_USERID_8822C(x)                                          \\\n\t(((x) & BIT_MASK_UPD_BFMEE_USERID_8822C)                               \\\n\t << BIT_SHIFT_UPD_BFMEE_USERID_8822C)\n#define BITS_UPD_BFMEE_USERID_8822C                                            \\\n\t(BIT_MASK_UPD_BFMEE_USERID_8822C << BIT_SHIFT_UPD_BFMEE_USERID_8822C)\n#define BIT_CLEAR_UPD_BFMEE_USERID_8822C(x)                                    \\\n\t((x) & (~BITS_UPD_BFMEE_USERID_8822C))\n#define BIT_GET_UPD_BFMEE_USERID_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_UPD_BFMEE_USERID_8822C) &                           \\\n\t BIT_MASK_UPD_BFMEE_USERID_8822C)\n#define BIT_SET_UPD_BFMEE_USERID_8822C(x, v)                                   \\\n\t(BIT_CLEAR_UPD_BFMEE_USERID_8822C(x) | BIT_UPD_BFMEE_USERID_8822C(v))\n\n#define BIT_UPD_BFMEE_FBTP_8822C BIT(12)\n\n#define BIT_SHIFT_UPD_BFMEE_BW_8822C 0\n#define BIT_MASK_UPD_BFMEE_BW_8822C 0xfff\n#define BIT_UPD_BFMEE_BW_8822C(x)                                              \\\n\t(((x) & BIT_MASK_UPD_BFMEE_BW_8822C) << BIT_SHIFT_UPD_BFMEE_BW_8822C)\n#define BITS_UPD_BFMEE_BW_8822C                                                \\\n\t(BIT_MASK_UPD_BFMEE_BW_8822C << BIT_SHIFT_UPD_BFMEE_BW_8822C)\n#define BIT_CLEAR_UPD_BFMEE_BW_8822C(x) ((x) & (~BITS_UPD_BFMEE_BW_8822C))\n#define BIT_GET_UPD_BFMEE_BW_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_UPD_BFMEE_BW_8822C) & BIT_MASK_UPD_BFMEE_BW_8822C)\n#define BIT_SET_UPD_BFMEE_BW_8822C(x, v)                                       \\\n\t(BIT_CLEAR_UPD_BFMEE_BW_8822C(x) | BIT_UPD_BFMEE_BW_8822C(v))\n\n#define BIT_SHIFT_UPD_BFMEE_CB_8822C 8\n#define BIT_MASK_UPD_BFMEE_CB_8822C 0x3\n#define BIT_UPD_BFMEE_CB_8822C(x)                                              \\\n\t(((x) & BIT_MASK_UPD_BFMEE_CB_8822C) << BIT_SHIFT_UPD_BFMEE_CB_8822C)\n#define BITS_UPD_BFMEE_CB_8822C                                                \\\n\t(BIT_MASK_UPD_BFMEE_CB_8822C << BIT_SHIFT_UPD_BFMEE_CB_8822C)\n#define BIT_CLEAR_UPD_BFMEE_CB_8822C(x) ((x) & (~BITS_UPD_BFMEE_CB_8822C))\n#define BIT_GET_UPD_BFMEE_CB_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_UPD_BFMEE_CB_8822C) & BIT_MASK_UPD_BFMEE_CB_8822C)\n#define BIT_SET_UPD_BFMEE_CB_8822C(x, v)                                       \\\n\t(BIT_CLEAR_UPD_BFMEE_CB_8822C(x) | BIT_UPD_BFMEE_CB_8822C(v))\n\n#define BIT_SHIFT_UPD_BFMEE_NG_8822C 6\n#define BIT_MASK_UPD_BFMEE_NG_8822C 0x3\n#define BIT_UPD_BFMEE_NG_8822C(x)                                              \\\n\t(((x) & BIT_MASK_UPD_BFMEE_NG_8822C) << BIT_SHIFT_UPD_BFMEE_NG_8822C)\n#define BITS_UPD_BFMEE_NG_8822C                                                \\\n\t(BIT_MASK_UPD_BFMEE_NG_8822C << BIT_SHIFT_UPD_BFMEE_NG_8822C)\n#define BIT_CLEAR_UPD_BFMEE_NG_8822C(x) ((x) & (~BITS_UPD_BFMEE_NG_8822C))\n#define BIT_GET_UPD_BFMEE_NG_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_UPD_BFMEE_NG_8822C) & BIT_MASK_UPD_BFMEE_NG_8822C)\n#define BIT_SET_UPD_BFMEE_NG_8822C(x, v)                                       \\\n\t(BIT_CLEAR_UPD_BFMEE_NG_8822C(x) | BIT_UPD_BFMEE_NG_8822C(v))\n\n#define BIT_SHIFT_UPD_BFMEE_NR_8822C 3\n#define BIT_MASK_UPD_BFMEE_NR_8822C 0x7\n#define BIT_UPD_BFMEE_NR_8822C(x)                                              \\\n\t(((x) & BIT_MASK_UPD_BFMEE_NR_8822C) << BIT_SHIFT_UPD_BFMEE_NR_8822C)\n#define BITS_UPD_BFMEE_NR_8822C                                                \\\n\t(BIT_MASK_UPD_BFMEE_NR_8822C << BIT_SHIFT_UPD_BFMEE_NR_8822C)\n#define BIT_CLEAR_UPD_BFMEE_NR_8822C(x) ((x) & (~BITS_UPD_BFMEE_NR_8822C))\n#define BIT_GET_UPD_BFMEE_NR_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_UPD_BFMEE_NR_8822C) & BIT_MASK_UPD_BFMEE_NR_8822C)\n#define BIT_SET_UPD_BFMEE_NR_8822C(x, v)                                       \\\n\t(BIT_CLEAR_UPD_BFMEE_NR_8822C(x) | BIT_UPD_BFMEE_NR_8822C(v))\n\n#define BIT_SHIFT_UPD_BFMEE_NC_8822C 0\n#define BIT_MASK_UPD_BFMEE_NC_8822C 0x7\n#define BIT_UPD_BFMEE_NC_8822C(x)                                              \\\n\t(((x) & BIT_MASK_UPD_BFMEE_NC_8822C) << BIT_SHIFT_UPD_BFMEE_NC_8822C)\n#define BITS_UPD_BFMEE_NC_8822C                                                \\\n\t(BIT_MASK_UPD_BFMEE_NC_8822C << BIT_SHIFT_UPD_BFMEE_NC_8822C)\n#define BIT_CLEAR_UPD_BFMEE_NC_8822C(x) ((x) & (~BITS_UPD_BFMEE_NC_8822C))\n#define BIT_GET_UPD_BFMEE_NC_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_UPD_BFMEE_NC_8822C) & BIT_MASK_UPD_BFMEE_NC_8822C)\n#define BIT_SET_UPD_BFMEE_NC_8822C(x, v)                                       \\\n\t(BIT_CLEAR_UPD_BFMEE_NC_8822C(x) | BIT_UPD_BFMEE_NC_8822C(v))\n\n/* 2 REG_IPV6_8822C */\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C 0xffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD_0_8822C(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C)                           \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C)\n#define BITS_R_WMAC_IPV6_MYIPAD_0_8822C                                        \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C                                   \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8822C(x)                                \\\n\t((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0_8822C))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C) &                       \\\n\t BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD_0_8822C(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8822C(x) |                             \\\n\t BIT_R_WMAC_IPV6_MYIPAD_0_8822C(v))\n\n/* 2 REG_IPV6_1_8822C */\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C 0xffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD_1_8822C(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C)                           \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C)\n#define BITS_R_WMAC_IPV6_MYIPAD_1_8822C                                        \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C                                   \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8822C(x)                                \\\n\t((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1_8822C))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C) &                       \\\n\t BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD_1_8822C(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8822C(x) |                             \\\n\t BIT_R_WMAC_IPV6_MYIPAD_1_8822C(v))\n\n/* 2 REG_IPV6_2_8822C */\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C 0xffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD_2_8822C(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C)                           \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C)\n#define BITS_R_WMAC_IPV6_MYIPAD_2_8822C                                        \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C                                   \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8822C(x)                                \\\n\t((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2_8822C))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C) &                       \\\n\t BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD_2_8822C(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8822C(x) |                             \\\n\t BIT_R_WMAC_IPV6_MYIPAD_2_8822C(v))\n\n/* 2 REG_IPV6_3_8822C */\n\n#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C 0\n#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C 0xffffffffL\n#define BIT_R_WMAC_IPV6_MYIPAD_3_8822C(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C)                           \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C)\n#define BITS_R_WMAC_IPV6_MYIPAD_3_8822C                                        \\\n\t(BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C                                   \\\n\t << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C)\n#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8822C(x)                                \\\n\t((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3_8822C))\n#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C) &                       \\\n\t BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C)\n#define BIT_SET_R_WMAC_IPV6_MYIPAD_3_8822C(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8822C(x) |                             \\\n\t BIT_R_WMAC_IPV6_MYIPAD_3_8822C(v))\n\n/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822C */\n\n#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C 4\n#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C 0xf\n#define BIT_R_WMAC_CTX_SUBTYPE_8822C(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C)                             \\\n\t << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C)\n#define BITS_R_WMAC_CTX_SUBTYPE_8822C                                          \\\n\t(BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C                                     \\\n\t << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C)\n#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822C(x)                                  \\\n\t((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8822C))\n#define BIT_GET_R_WMAC_CTX_SUBTYPE_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C) &                         \\\n\t BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C)\n#define BIT_SET_R_WMAC_CTX_SUBTYPE_8822C(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822C(x) |                               \\\n\t BIT_R_WMAC_CTX_SUBTYPE_8822C(v))\n\n#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C 0\n#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C 0xf\n#define BIT_R_WMAC_RTX_SUBTYPE_8822C(x)                                        \\\n\t(((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C)                             \\\n\t << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C)\n#define BITS_R_WMAC_RTX_SUBTYPE_8822C                                          \\\n\t(BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C                                     \\\n\t << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C)\n#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822C(x)                                  \\\n\t((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8822C))\n#define BIT_GET_R_WMAC_RTX_SUBTYPE_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C) &                         \\\n\t BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C)\n#define BIT_SET_R_WMAC_RTX_SUBTYPE_8822C(x, v)                                 \\\n\t(BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822C(x) |                               \\\n\t BIT_R_WMAC_RTX_SUBTYPE_8822C(v))\n\n/* 2 REG_WMAC_SWAES_DIO_B63_B32_8822C */\n\n#define BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C 0\n#define BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C 0xffffffffL\n#define BIT_WMAC_SWAES_DIO_B63_B32_8822C(x)                                    \\\n\t(((x) & BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C)                         \\\n\t << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C)\n#define BITS_WMAC_SWAES_DIO_B63_B32_8822C                                      \\\n\t(BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C                                 \\\n\t << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C)\n#define BIT_CLEAR_WMAC_SWAES_DIO_B63_B32_8822C(x)                              \\\n\t((x) & (~BITS_WMAC_SWAES_DIO_B63_B32_8822C))\n#define BIT_GET_WMAC_SWAES_DIO_B63_B32_8822C(x)                                \\\n\t(((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C) &                     \\\n\t BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C)\n#define BIT_SET_WMAC_SWAES_DIO_B63_B32_8822C(x, v)                             \\\n\t(BIT_CLEAR_WMAC_SWAES_DIO_B63_B32_8822C(x) |                           \\\n\t BIT_WMAC_SWAES_DIO_B63_B32_8822C(v))\n\n/* 2 REG_WMAC_SWAES_DIO_B95_B64_8822C */\n\n#define BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C 0\n#define BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C 0xffffffffL\n#define BIT_WMAC_SWAES_DIO_B95_B64_8822C(x)                                    \\\n\t(((x) & BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C)                         \\\n\t << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C)\n#define BITS_WMAC_SWAES_DIO_B95_B64_8822C                                      \\\n\t(BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C                                 \\\n\t << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C)\n#define BIT_CLEAR_WMAC_SWAES_DIO_B95_B64_8822C(x)                              \\\n\t((x) & (~BITS_WMAC_SWAES_DIO_B95_B64_8822C))\n#define BIT_GET_WMAC_SWAES_DIO_B95_B64_8822C(x)                                \\\n\t(((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C) &                     \\\n\t BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C)\n#define BIT_SET_WMAC_SWAES_DIO_B95_B64_8822C(x, v)                             \\\n\t(BIT_CLEAR_WMAC_SWAES_DIO_B95_B64_8822C(x) |                           \\\n\t BIT_WMAC_SWAES_DIO_B95_B64_8822C(v))\n\n/* 2 REG_WMAC_SWAES_DIO_B127_B96_8822C */\n\n#define BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C 0\n#define BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C 0xffffffffL\n#define BIT_WMAC_SWAES_DIO_B127_B96_8822C(x)                                   \\\n\t(((x) & BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C)                        \\\n\t << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C)\n#define BITS_WMAC_SWAES_DIO_B127_B96_8822C                                     \\\n\t(BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C                                \\\n\t << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C)\n#define BIT_CLEAR_WMAC_SWAES_DIO_B127_B96_8822C(x)                             \\\n\t((x) & (~BITS_WMAC_SWAES_DIO_B127_B96_8822C))\n#define BIT_GET_WMAC_SWAES_DIO_B127_B96_8822C(x)                               \\\n\t(((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C) &                    \\\n\t BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C)\n#define BIT_SET_WMAC_SWAES_DIO_B127_B96_8822C(x, v)                            \\\n\t(BIT_CLEAR_WMAC_SWAES_DIO_B127_B96_8822C(x) |                          \\\n\t BIT_WMAC_SWAES_DIO_B127_B96_8822C(v))\n\n/* 2 REG_WMAC_SWAES_CFG_8822C */\n\n/* 2 REG_BT_COEX_V2_8822C */\n#define BIT_GNT_BT_POLARITY_8822C BIT(12)\n#define BIT_GNT_BT_BYPASS_PRIORITY_8822C BIT(8)\n\n#define BIT_SHIFT_TIMER_8822C 0\n#define BIT_MASK_TIMER_8822C 0xff\n#define BIT_TIMER_8822C(x)                                                     \\\n\t(((x) & BIT_MASK_TIMER_8822C) << BIT_SHIFT_TIMER_8822C)\n#define BITS_TIMER_8822C (BIT_MASK_TIMER_8822C << BIT_SHIFT_TIMER_8822C)\n#define BIT_CLEAR_TIMER_8822C(x) ((x) & (~BITS_TIMER_8822C))\n#define BIT_GET_TIMER_8822C(x)                                                 \\\n\t(((x) >> BIT_SHIFT_TIMER_8822C) & BIT_MASK_TIMER_8822C)\n#define BIT_SET_TIMER_8822C(x, v)                                              \\\n\t(BIT_CLEAR_TIMER_8822C(x) | BIT_TIMER_8822C(v))\n\n/* 2 REG_BT_COEX_8822C */\n#define BIT_R_GNT_BT_RFC_SW_8822C BIT(12)\n#define BIT_R_GNT_BT_RFC_SW_EN_8822C BIT(11)\n#define BIT_R_GNT_BT_BB_SW_8822C BIT(10)\n#define BIT_R_GNT_BT_BB_SW_EN_8822C BIT(9)\n#define BIT_R_BT_CNT_THREN_8822C BIT(8)\n\n#define BIT_SHIFT_R_BT_CNT_THR_8822C 0\n#define BIT_MASK_R_BT_CNT_THR_8822C 0xff\n#define BIT_R_BT_CNT_THR_8822C(x)                                              \\\n\t(((x) & BIT_MASK_R_BT_CNT_THR_8822C) << BIT_SHIFT_R_BT_CNT_THR_8822C)\n#define BITS_R_BT_CNT_THR_8822C                                                \\\n\t(BIT_MASK_R_BT_CNT_THR_8822C << BIT_SHIFT_R_BT_CNT_THR_8822C)\n#define BIT_CLEAR_R_BT_CNT_THR_8822C(x) ((x) & (~BITS_R_BT_CNT_THR_8822C))\n#define BIT_GET_R_BT_CNT_THR_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_BT_CNT_THR_8822C) & BIT_MASK_R_BT_CNT_THR_8822C)\n#define BIT_SET_R_BT_CNT_THR_8822C(x, v)                                       \\\n\t(BIT_CLEAR_R_BT_CNT_THR_8822C(x) | BIT_R_BT_CNT_THR_8822C(v))\n\n/* 2 REG_WLAN_ACT_MASK_CTRL_8822C */\n\n#define BIT_SHIFT_RXMYRTS_NAV_V1_8822C 8\n#define BIT_MASK_RXMYRTS_NAV_V1_8822C 0xff\n#define BIT_RXMYRTS_NAV_V1_8822C(x)                                            \\\n\t(((x) & BIT_MASK_RXMYRTS_NAV_V1_8822C)                                 \\\n\t << BIT_SHIFT_RXMYRTS_NAV_V1_8822C)\n#define BITS_RXMYRTS_NAV_V1_8822C                                              \\\n\t(BIT_MASK_RXMYRTS_NAV_V1_8822C << BIT_SHIFT_RXMYRTS_NAV_V1_8822C)\n#define BIT_CLEAR_RXMYRTS_NAV_V1_8822C(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8822C))\n#define BIT_GET_RXMYRTS_NAV_V1_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8822C) &                             \\\n\t BIT_MASK_RXMYRTS_NAV_V1_8822C)\n#define BIT_SET_RXMYRTS_NAV_V1_8822C(x, v)                                     \\\n\t(BIT_CLEAR_RXMYRTS_NAV_V1_8822C(x) | BIT_RXMYRTS_NAV_V1_8822C(v))\n\n#define BIT_SHIFT_RTSRST_V1_8822C 0\n#define BIT_MASK_RTSRST_V1_8822C 0xff\n#define BIT_RTSRST_V1_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_RTSRST_V1_8822C) << BIT_SHIFT_RTSRST_V1_8822C)\n#define BITS_RTSRST_V1_8822C                                                   \\\n\t(BIT_MASK_RTSRST_V1_8822C << BIT_SHIFT_RTSRST_V1_8822C)\n#define BIT_CLEAR_RTSRST_V1_8822C(x) ((x) & (~BITS_RTSRST_V1_8822C))\n#define BIT_GET_RTSRST_V1_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_RTSRST_V1_8822C) & BIT_MASK_RTSRST_V1_8822C)\n#define BIT_SET_RTSRST_V1_8822C(x, v)                                          \\\n\t(BIT_CLEAR_RTSRST_V1_8822C(x) | BIT_RTSRST_V1_8822C(v))\n\n/* 2 REG_WLAN_ACT_MASK_CTRL_1_8822C */\n#define BIT_WLRX_TER_BY_CTL_1_8822C BIT(11)\n#define BIT_WLRX_TER_BY_AD_1_8822C BIT(10)\n#define BIT_ANT_DIVERSITY_SEL_1_8822C BIT(9)\n#define BIT_ANTSEL_FOR_BT_CTRL_EN_1_8822C BIT(8)\n#define BIT_WLACT_LOW_GNTWL_EN_1_8822C BIT(2)\n#define BIT_WLACT_HIGH_GNTBT_EN_1_8822C BIT(1)\n#define BIT_NAV_UPPER_1_V1_8822C BIT(0)\n\n/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8822C */\n\n#define BIT_SHIFT_BT_STAT_DELAY_8822C 12\n#define BIT_MASK_BT_STAT_DELAY_8822C 0xf\n#define BIT_BT_STAT_DELAY_8822C(x)                                             \\\n\t(((x) & BIT_MASK_BT_STAT_DELAY_8822C) << BIT_SHIFT_BT_STAT_DELAY_8822C)\n#define BITS_BT_STAT_DELAY_8822C                                               \\\n\t(BIT_MASK_BT_STAT_DELAY_8822C << BIT_SHIFT_BT_STAT_DELAY_8822C)\n#define BIT_CLEAR_BT_STAT_DELAY_8822C(x) ((x) & (~BITS_BT_STAT_DELAY_8822C))\n#define BIT_GET_BT_STAT_DELAY_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_BT_STAT_DELAY_8822C) & BIT_MASK_BT_STAT_DELAY_8822C)\n#define BIT_SET_BT_STAT_DELAY_8822C(x, v)                                      \\\n\t(BIT_CLEAR_BT_STAT_DELAY_8822C(x) | BIT_BT_STAT_DELAY_8822C(v))\n\n#define BIT_SHIFT_BT_TRX_INIT_DETECT_8822C 8\n#define BIT_MASK_BT_TRX_INIT_DETECT_8822C 0xf\n#define BIT_BT_TRX_INIT_DETECT_8822C(x)                                        \\\n\t(((x) & BIT_MASK_BT_TRX_INIT_DETECT_8822C)                             \\\n\t << BIT_SHIFT_BT_TRX_INIT_DETECT_8822C)\n#define BITS_BT_TRX_INIT_DETECT_8822C                                          \\\n\t(BIT_MASK_BT_TRX_INIT_DETECT_8822C                                     \\\n\t << BIT_SHIFT_BT_TRX_INIT_DETECT_8822C)\n#define BIT_CLEAR_BT_TRX_INIT_DETECT_8822C(x)                                  \\\n\t((x) & (~BITS_BT_TRX_INIT_DETECT_8822C))\n#define BIT_GET_BT_TRX_INIT_DETECT_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8822C) &                         \\\n\t BIT_MASK_BT_TRX_INIT_DETECT_8822C)\n#define BIT_SET_BT_TRX_INIT_DETECT_8822C(x, v)                                 \\\n\t(BIT_CLEAR_BT_TRX_INIT_DETECT_8822C(x) |                               \\\n\t BIT_BT_TRX_INIT_DETECT_8822C(v))\n\n#define BIT_SHIFT_BT_PRI_DETECT_TO_8822C 4\n#define BIT_MASK_BT_PRI_DETECT_TO_8822C 0xf\n#define BIT_BT_PRI_DETECT_TO_8822C(x)                                          \\\n\t(((x) & BIT_MASK_BT_PRI_DETECT_TO_8822C)                               \\\n\t << BIT_SHIFT_BT_PRI_DETECT_TO_8822C)\n#define BITS_BT_PRI_DETECT_TO_8822C                                            \\\n\t(BIT_MASK_BT_PRI_DETECT_TO_8822C << BIT_SHIFT_BT_PRI_DETECT_TO_8822C)\n#define BIT_CLEAR_BT_PRI_DETECT_TO_8822C(x)                                    \\\n\t((x) & (~BITS_BT_PRI_DETECT_TO_8822C))\n#define BIT_GET_BT_PRI_DETECT_TO_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8822C) &                           \\\n\t BIT_MASK_BT_PRI_DETECT_TO_8822C)\n#define BIT_SET_BT_PRI_DETECT_TO_8822C(x, v)                                   \\\n\t(BIT_CLEAR_BT_PRI_DETECT_TO_8822C(x) | BIT_BT_PRI_DETECT_TO_8822C(v))\n\n#define BIT_R_GRANTALL_WLMASK_8822C BIT(3)\n#define BIT_STATIS_BT_EN_8822C BIT(2)\n#define BIT_WL_ACT_MASK_ENABLE_8822C BIT(1)\n#define BIT_ENHANCED_BT_8822C BIT(0)\n\n/* 2 REG_BT_ACT_STATISTICS_8822C */\n\n#define BIT_SHIFT_STATIS_BT_HI_RX_8822C 16\n#define BIT_MASK_STATIS_BT_HI_RX_8822C 0xffff\n#define BIT_STATIS_BT_HI_RX_8822C(x)                                           \\\n\t(((x) & BIT_MASK_STATIS_BT_HI_RX_8822C)                                \\\n\t << BIT_SHIFT_STATIS_BT_HI_RX_8822C)\n#define BITS_STATIS_BT_HI_RX_8822C                                             \\\n\t(BIT_MASK_STATIS_BT_HI_RX_8822C << BIT_SHIFT_STATIS_BT_HI_RX_8822C)\n#define BIT_CLEAR_STATIS_BT_HI_RX_8822C(x) ((x) & (~BITS_STATIS_BT_HI_RX_8822C))\n#define BIT_GET_STATIS_BT_HI_RX_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8822C) &                            \\\n\t BIT_MASK_STATIS_BT_HI_RX_8822C)\n#define BIT_SET_STATIS_BT_HI_RX_8822C(x, v)                                    \\\n\t(BIT_CLEAR_STATIS_BT_HI_RX_8822C(x) | BIT_STATIS_BT_HI_RX_8822C(v))\n\n#define BIT_SHIFT_STATIS_BT_HI_TX_8822C 0\n#define BIT_MASK_STATIS_BT_HI_TX_8822C 0xffff\n#define BIT_STATIS_BT_HI_TX_8822C(x)                                           \\\n\t(((x) & BIT_MASK_STATIS_BT_HI_TX_8822C)                                \\\n\t << BIT_SHIFT_STATIS_BT_HI_TX_8822C)\n#define BITS_STATIS_BT_HI_TX_8822C                                             \\\n\t(BIT_MASK_STATIS_BT_HI_TX_8822C << BIT_SHIFT_STATIS_BT_HI_TX_8822C)\n#define BIT_CLEAR_STATIS_BT_HI_TX_8822C(x) ((x) & (~BITS_STATIS_BT_HI_TX_8822C))\n#define BIT_GET_STATIS_BT_HI_TX_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8822C) &                            \\\n\t BIT_MASK_STATIS_BT_HI_TX_8822C)\n#define BIT_SET_STATIS_BT_HI_TX_8822C(x, v)                                    \\\n\t(BIT_CLEAR_STATIS_BT_HI_TX_8822C(x) | BIT_STATIS_BT_HI_TX_8822C(v))\n\n/* 2 REG_BT_ACT_STATISTICS_1_8822C */\n\n#define BIT_SHIFT_STATIS_BT_LO_RX_1_8822C 16\n#define BIT_MASK_STATIS_BT_LO_RX_1_8822C 0xffff\n#define BIT_STATIS_BT_LO_RX_1_8822C(x)                                         \\\n\t(((x) & BIT_MASK_STATIS_BT_LO_RX_1_8822C)                              \\\n\t << BIT_SHIFT_STATIS_BT_LO_RX_1_8822C)\n#define BITS_STATIS_BT_LO_RX_1_8822C                                           \\\n\t(BIT_MASK_STATIS_BT_LO_RX_1_8822C << BIT_SHIFT_STATIS_BT_LO_RX_1_8822C)\n#define BIT_CLEAR_STATIS_BT_LO_RX_1_8822C(x)                                   \\\n\t((x) & (~BITS_STATIS_BT_LO_RX_1_8822C))\n#define BIT_GET_STATIS_BT_LO_RX_1_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8822C) &                          \\\n\t BIT_MASK_STATIS_BT_LO_RX_1_8822C)\n#define BIT_SET_STATIS_BT_LO_RX_1_8822C(x, v)                                  \\\n\t(BIT_CLEAR_STATIS_BT_LO_RX_1_8822C(x) | BIT_STATIS_BT_LO_RX_1_8822C(v))\n\n#define BIT_SHIFT_STATIS_BT_LO_TX_1_8822C 0\n#define BIT_MASK_STATIS_BT_LO_TX_1_8822C 0xffff\n#define BIT_STATIS_BT_LO_TX_1_8822C(x)                                         \\\n\t(((x) & BIT_MASK_STATIS_BT_LO_TX_1_8822C)                              \\\n\t << BIT_SHIFT_STATIS_BT_LO_TX_1_8822C)\n#define BITS_STATIS_BT_LO_TX_1_8822C                                           \\\n\t(BIT_MASK_STATIS_BT_LO_TX_1_8822C << BIT_SHIFT_STATIS_BT_LO_TX_1_8822C)\n#define BIT_CLEAR_STATIS_BT_LO_TX_1_8822C(x)                                   \\\n\t((x) & (~BITS_STATIS_BT_LO_TX_1_8822C))\n#define BIT_GET_STATIS_BT_LO_TX_1_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8822C) &                          \\\n\t BIT_MASK_STATIS_BT_LO_TX_1_8822C)\n#define BIT_SET_STATIS_BT_LO_TX_1_8822C(x, v)                                  \\\n\t(BIT_CLEAR_STATIS_BT_LO_TX_1_8822C(x) | BIT_STATIS_BT_LO_TX_1_8822C(v))\n\n/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8822C */\n\n#define BIT_SHIFT_R_BT_CMD_RPT_8822C 16\n#define BIT_MASK_R_BT_CMD_RPT_8822C 0xffff\n#define BIT_R_BT_CMD_RPT_8822C(x)                                              \\\n\t(((x) & BIT_MASK_R_BT_CMD_RPT_8822C) << BIT_SHIFT_R_BT_CMD_RPT_8822C)\n#define BITS_R_BT_CMD_RPT_8822C                                                \\\n\t(BIT_MASK_R_BT_CMD_RPT_8822C << BIT_SHIFT_R_BT_CMD_RPT_8822C)\n#define BIT_CLEAR_R_BT_CMD_RPT_8822C(x) ((x) & (~BITS_R_BT_CMD_RPT_8822C))\n#define BIT_GET_R_BT_CMD_RPT_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_R_BT_CMD_RPT_8822C) & BIT_MASK_R_BT_CMD_RPT_8822C)\n#define BIT_SET_R_BT_CMD_RPT_8822C(x, v)                                       \\\n\t(BIT_CLEAR_R_BT_CMD_RPT_8822C(x) | BIT_R_BT_CMD_RPT_8822C(v))\n\n#define BIT_SHIFT_R_RPT_FROM_BT_8822C 8\n#define BIT_MASK_R_RPT_FROM_BT_8822C 0xff\n#define BIT_R_RPT_FROM_BT_8822C(x)                                             \\\n\t(((x) & BIT_MASK_R_RPT_FROM_BT_8822C) << BIT_SHIFT_R_RPT_FROM_BT_8822C)\n#define BITS_R_RPT_FROM_BT_8822C                                               \\\n\t(BIT_MASK_R_RPT_FROM_BT_8822C << BIT_SHIFT_R_RPT_FROM_BT_8822C)\n#define BIT_CLEAR_R_RPT_FROM_BT_8822C(x) ((x) & (~BITS_R_RPT_FROM_BT_8822C))\n#define BIT_GET_R_RPT_FROM_BT_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_RPT_FROM_BT_8822C) & BIT_MASK_R_RPT_FROM_BT_8822C)\n#define BIT_SET_R_RPT_FROM_BT_8822C(x, v)                                      \\\n\t(BIT_CLEAR_R_RPT_FROM_BT_8822C(x) | BIT_R_RPT_FROM_BT_8822C(v))\n\n#define BIT_SHIFT_BT_HID_ISR_SET_8822C 6\n#define BIT_MASK_BT_HID_ISR_SET_8822C 0x3\n#define BIT_BT_HID_ISR_SET_8822C(x)                                            \\\n\t(((x) & BIT_MASK_BT_HID_ISR_SET_8822C)                                 \\\n\t << BIT_SHIFT_BT_HID_ISR_SET_8822C)\n#define BITS_BT_HID_ISR_SET_8822C                                              \\\n\t(BIT_MASK_BT_HID_ISR_SET_8822C << BIT_SHIFT_BT_HID_ISR_SET_8822C)\n#define BIT_CLEAR_BT_HID_ISR_SET_8822C(x) ((x) & (~BITS_BT_HID_ISR_SET_8822C))\n#define BIT_GET_BT_HID_ISR_SET_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_BT_HID_ISR_SET_8822C) &                             \\\n\t BIT_MASK_BT_HID_ISR_SET_8822C)\n#define BIT_SET_BT_HID_ISR_SET_8822C(x, v)                                     \\\n\t(BIT_CLEAR_BT_HID_ISR_SET_8822C(x) | BIT_BT_HID_ISR_SET_8822C(v))\n\n#define BIT_TDMA_BT_START_NOTIFY_8822C BIT(5)\n#define BIT_ENABLE_TDMA_FW_MODE_8822C BIT(4)\n#define BIT_ENABLE_PTA_TDMA_MODE_8822C BIT(3)\n#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8822C BIT(2)\n#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8822C BIT(1)\n#define BIT_RTK_BT_ENABLE_8822C BIT(0)\n\n/* 2 REG_BT_STATUS_REPORT_REGISTER_8822C */\n\n#define BIT_SHIFT_BT_PROFILE_8822C 24\n#define BIT_MASK_BT_PROFILE_8822C 0xff\n#define BIT_BT_PROFILE_8822C(x)                                                \\\n\t(((x) & BIT_MASK_BT_PROFILE_8822C) << BIT_SHIFT_BT_PROFILE_8822C)\n#define BITS_BT_PROFILE_8822C                                                  \\\n\t(BIT_MASK_BT_PROFILE_8822C << BIT_SHIFT_BT_PROFILE_8822C)\n#define BIT_CLEAR_BT_PROFILE_8822C(x) ((x) & (~BITS_BT_PROFILE_8822C))\n#define BIT_GET_BT_PROFILE_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BT_PROFILE_8822C) & BIT_MASK_BT_PROFILE_8822C)\n#define BIT_SET_BT_PROFILE_8822C(x, v)                                         \\\n\t(BIT_CLEAR_BT_PROFILE_8822C(x) | BIT_BT_PROFILE_8822C(v))\n\n#define BIT_SHIFT_BT_POWER_8822C 16\n#define BIT_MASK_BT_POWER_8822C 0xff\n#define BIT_BT_POWER_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_BT_POWER_8822C) << BIT_SHIFT_BT_POWER_8822C)\n#define BITS_BT_POWER_8822C                                                    \\\n\t(BIT_MASK_BT_POWER_8822C << BIT_SHIFT_BT_POWER_8822C)\n#define BIT_CLEAR_BT_POWER_8822C(x) ((x) & (~BITS_BT_POWER_8822C))\n#define BIT_GET_BT_POWER_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_BT_POWER_8822C) & BIT_MASK_BT_POWER_8822C)\n#define BIT_SET_BT_POWER_8822C(x, v)                                           \\\n\t(BIT_CLEAR_BT_POWER_8822C(x) | BIT_BT_POWER_8822C(v))\n\n#define BIT_SHIFT_BT_PREDECT_STATUS_8822C 8\n#define BIT_MASK_BT_PREDECT_STATUS_8822C 0xff\n#define BIT_BT_PREDECT_STATUS_8822C(x)                                         \\\n\t(((x) & BIT_MASK_BT_PREDECT_STATUS_8822C)                              \\\n\t << BIT_SHIFT_BT_PREDECT_STATUS_8822C)\n#define BITS_BT_PREDECT_STATUS_8822C                                           \\\n\t(BIT_MASK_BT_PREDECT_STATUS_8822C << BIT_SHIFT_BT_PREDECT_STATUS_8822C)\n#define BIT_CLEAR_BT_PREDECT_STATUS_8822C(x)                                   \\\n\t((x) & (~BITS_BT_PREDECT_STATUS_8822C))\n#define BIT_GET_BT_PREDECT_STATUS_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8822C) &                          \\\n\t BIT_MASK_BT_PREDECT_STATUS_8822C)\n#define BIT_SET_BT_PREDECT_STATUS_8822C(x, v)                                  \\\n\t(BIT_CLEAR_BT_PREDECT_STATUS_8822C(x) | BIT_BT_PREDECT_STATUS_8822C(v))\n\n#define BIT_SHIFT_BT_CMD_INFO_8822C 0\n#define BIT_MASK_BT_CMD_INFO_8822C 0xff\n#define BIT_BT_CMD_INFO_8822C(x)                                               \\\n\t(((x) & BIT_MASK_BT_CMD_INFO_8822C) << BIT_SHIFT_BT_CMD_INFO_8822C)\n#define BITS_BT_CMD_INFO_8822C                                                 \\\n\t(BIT_MASK_BT_CMD_INFO_8822C << BIT_SHIFT_BT_CMD_INFO_8822C)\n#define BIT_CLEAR_BT_CMD_INFO_8822C(x) ((x) & (~BITS_BT_CMD_INFO_8822C))\n#define BIT_GET_BT_CMD_INFO_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_BT_CMD_INFO_8822C) & BIT_MASK_BT_CMD_INFO_8822C)\n#define BIT_SET_BT_CMD_INFO_8822C(x, v)                                        \\\n\t(BIT_CLEAR_BT_CMD_INFO_8822C(x) | BIT_BT_CMD_INFO_8822C(v))\n\n/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8822C */\n#define BIT_EN_MAC_NULL_PKT_NOTIFY_8822C BIT(31)\n#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8822C BIT(30)\n#define BIT_EN_BT_STSTUS_RPT_8822C BIT(29)\n#define BIT_EN_BT_POWER_8822C BIT(28)\n#define BIT_EN_BT_CHANNEL_8822C BIT(27)\n#define BIT_EN_BT_SLOT_CHANGE_8822C BIT(26)\n#define BIT_EN_BT_PROFILE_OR_HID_8822C BIT(25)\n#define BIT_WLAN_RPT_NOTIFY_8822C BIT(24)\n\n#define BIT_SHIFT_WLAN_RPT_DATA_8822C 16\n#define BIT_MASK_WLAN_RPT_DATA_8822C 0xff\n#define BIT_WLAN_RPT_DATA_8822C(x)                                             \\\n\t(((x) & BIT_MASK_WLAN_RPT_DATA_8822C) << BIT_SHIFT_WLAN_RPT_DATA_8822C)\n#define BITS_WLAN_RPT_DATA_8822C                                               \\\n\t(BIT_MASK_WLAN_RPT_DATA_8822C << BIT_SHIFT_WLAN_RPT_DATA_8822C)\n#define BIT_CLEAR_WLAN_RPT_DATA_8822C(x) ((x) & (~BITS_WLAN_RPT_DATA_8822C))\n#define BIT_GET_WLAN_RPT_DATA_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_WLAN_RPT_DATA_8822C) & BIT_MASK_WLAN_RPT_DATA_8822C)\n#define BIT_SET_WLAN_RPT_DATA_8822C(x, v)                                      \\\n\t(BIT_CLEAR_WLAN_RPT_DATA_8822C(x) | BIT_WLAN_RPT_DATA_8822C(v))\n\n#define BIT_SHIFT_CMD_ID_8822C 8\n#define BIT_MASK_CMD_ID_8822C 0xff\n#define BIT_CMD_ID_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_CMD_ID_8822C) << BIT_SHIFT_CMD_ID_8822C)\n#define BITS_CMD_ID_8822C (BIT_MASK_CMD_ID_8822C << BIT_SHIFT_CMD_ID_8822C)\n#define BIT_CLEAR_CMD_ID_8822C(x) ((x) & (~BITS_CMD_ID_8822C))\n#define BIT_GET_CMD_ID_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_CMD_ID_8822C) & BIT_MASK_CMD_ID_8822C)\n#define BIT_SET_CMD_ID_8822C(x, v)                                             \\\n\t(BIT_CLEAR_CMD_ID_8822C(x) | BIT_CMD_ID_8822C(v))\n\n#define BIT_SHIFT_BT_DATA_8822C 0\n#define BIT_MASK_BT_DATA_8822C 0xff\n#define BIT_BT_DATA_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_BT_DATA_8822C) << BIT_SHIFT_BT_DATA_8822C)\n#define BITS_BT_DATA_8822C (BIT_MASK_BT_DATA_8822C << BIT_SHIFT_BT_DATA_8822C)\n#define BIT_CLEAR_BT_DATA_8822C(x) ((x) & (~BITS_BT_DATA_8822C))\n#define BIT_GET_BT_DATA_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_BT_DATA_8822C) & BIT_MASK_BT_DATA_8822C)\n#define BIT_SET_BT_DATA_8822C(x, v)                                            \\\n\t(BIT_CLEAR_BT_DATA_8822C(x) | BIT_BT_DATA_8822C(v))\n\n/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822C */\n\n#define BIT_SHIFT_WLAN_RPT_TO_8822C 0\n#define BIT_MASK_WLAN_RPT_TO_8822C 0xff\n#define BIT_WLAN_RPT_TO_8822C(x)                                               \\\n\t(((x) & BIT_MASK_WLAN_RPT_TO_8822C) << BIT_SHIFT_WLAN_RPT_TO_8822C)\n#define BITS_WLAN_RPT_TO_8822C                                                 \\\n\t(BIT_MASK_WLAN_RPT_TO_8822C << BIT_SHIFT_WLAN_RPT_TO_8822C)\n#define BIT_CLEAR_WLAN_RPT_TO_8822C(x) ((x) & (~BITS_WLAN_RPT_TO_8822C))\n#define BIT_GET_WLAN_RPT_TO_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_WLAN_RPT_TO_8822C) & BIT_MASK_WLAN_RPT_TO_8822C)\n#define BIT_SET_WLAN_RPT_TO_8822C(x, v)                                        \\\n\t(BIT_CLEAR_WLAN_RPT_TO_8822C(x) | BIT_WLAN_RPT_TO_8822C(v))\n\n/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822C */\n\n#define BIT_SHIFT_ISOLATION_CHK_0_8822C 1\n#define BIT_MASK_ISOLATION_CHK_0_8822C 0x7fffff\n#define BIT_ISOLATION_CHK_0_8822C(x)                                           \\\n\t(((x) & BIT_MASK_ISOLATION_CHK_0_8822C)                                \\\n\t << BIT_SHIFT_ISOLATION_CHK_0_8822C)\n#define BITS_ISOLATION_CHK_0_8822C                                             \\\n\t(BIT_MASK_ISOLATION_CHK_0_8822C << BIT_SHIFT_ISOLATION_CHK_0_8822C)\n#define BIT_CLEAR_ISOLATION_CHK_0_8822C(x) ((x) & (~BITS_ISOLATION_CHK_0_8822C))\n#define BIT_GET_ISOLATION_CHK_0_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_ISOLATION_CHK_0_8822C) &                            \\\n\t BIT_MASK_ISOLATION_CHK_0_8822C)\n#define BIT_SET_ISOLATION_CHK_0_8822C(x, v)                                    \\\n\t(BIT_CLEAR_ISOLATION_CHK_0_8822C(x) | BIT_ISOLATION_CHK_0_8822C(v))\n\n#define BIT_ISOLATION_EN_8822C BIT(0)\n\n/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8822C */\n\n#define BIT_SHIFT_ISOLATION_CHK_1_8822C 0\n#define BIT_MASK_ISOLATION_CHK_1_8822C 0xffffffffL\n#define BIT_ISOLATION_CHK_1_8822C(x)                                           \\\n\t(((x) & BIT_MASK_ISOLATION_CHK_1_8822C)                                \\\n\t << BIT_SHIFT_ISOLATION_CHK_1_8822C)\n#define BITS_ISOLATION_CHK_1_8822C                                             \\\n\t(BIT_MASK_ISOLATION_CHK_1_8822C << BIT_SHIFT_ISOLATION_CHK_1_8822C)\n#define BIT_CLEAR_ISOLATION_CHK_1_8822C(x) ((x) & (~BITS_ISOLATION_CHK_1_8822C))\n#define BIT_GET_ISOLATION_CHK_1_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_ISOLATION_CHK_1_8822C) &                            \\\n\t BIT_MASK_ISOLATION_CHK_1_8822C)\n#define BIT_SET_ISOLATION_CHK_1_8822C(x, v)                                    \\\n\t(BIT_CLEAR_ISOLATION_CHK_1_8822C(x) | BIT_ISOLATION_CHK_1_8822C(v))\n\n/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8822C */\n\n#define BIT_SHIFT_ISOLATION_CHK_2_8822C 0\n#define BIT_MASK_ISOLATION_CHK_2_8822C 0xffffff\n#define BIT_ISOLATION_CHK_2_8822C(x)                                           \\\n\t(((x) & BIT_MASK_ISOLATION_CHK_2_8822C)                                \\\n\t << BIT_SHIFT_ISOLATION_CHK_2_8822C)\n#define BITS_ISOLATION_CHK_2_8822C                                             \\\n\t(BIT_MASK_ISOLATION_CHK_2_8822C << BIT_SHIFT_ISOLATION_CHK_2_8822C)\n#define BIT_CLEAR_ISOLATION_CHK_2_8822C(x) ((x) & (~BITS_ISOLATION_CHK_2_8822C))\n#define BIT_GET_ISOLATION_CHK_2_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_ISOLATION_CHK_2_8822C) &                            \\\n\t BIT_MASK_ISOLATION_CHK_2_8822C)\n#define BIT_SET_ISOLATION_CHK_2_8822C(x, v)                                    \\\n\t(BIT_CLEAR_ISOLATION_CHK_2_8822C(x) | BIT_ISOLATION_CHK_2_8822C(v))\n\n/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8822C */\n#define BIT_BT_HID_ISR_8822C BIT(7)\n#define BIT_BT_QUERY_ISR_8822C BIT(6)\n#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8822C BIT(5)\n#define BIT_WLAN_RPT_ISR_8822C BIT(4)\n#define BIT_BT_POWER_ISR_8822C BIT(3)\n#define BIT_BT_CHANNEL_ISR_8822C BIT(2)\n#define BIT_BT_SLOT_CHANGE_ISR_8822C BIT(1)\n#define BIT_BT_PROFILE_ISR_8822C BIT(0)\n\n/* 2 REG_BT_TDMA_TIME_REGISTER_8822C */\n\n#define BIT_SHIFT_BT_TIME_8822C 6\n#define BIT_MASK_BT_TIME_8822C 0x3ffffff\n#define BIT_BT_TIME_8822C(x)                                                   \\\n\t(((x) & BIT_MASK_BT_TIME_8822C) << BIT_SHIFT_BT_TIME_8822C)\n#define BITS_BT_TIME_8822C (BIT_MASK_BT_TIME_8822C << BIT_SHIFT_BT_TIME_8822C)\n#define BIT_CLEAR_BT_TIME_8822C(x) ((x) & (~BITS_BT_TIME_8822C))\n#define BIT_GET_BT_TIME_8822C(x)                                               \\\n\t(((x) >> BIT_SHIFT_BT_TIME_8822C) & BIT_MASK_BT_TIME_8822C)\n#define BIT_SET_BT_TIME_8822C(x, v)                                            \\\n\t(BIT_CLEAR_BT_TIME_8822C(x) | BIT_BT_TIME_8822C(v))\n\n#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C 0\n#define BIT_MASK_BT_RPT_SAMPLE_RATE_8822C 0x3f\n#define BIT_BT_RPT_SAMPLE_RATE_8822C(x)                                        \\\n\t(((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822C)                             \\\n\t << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C)\n#define BITS_BT_RPT_SAMPLE_RATE_8822C                                          \\\n\t(BIT_MASK_BT_RPT_SAMPLE_RATE_8822C                                     \\\n\t << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C)\n#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822C(x)                                  \\\n\t((x) & (~BITS_BT_RPT_SAMPLE_RATE_8822C))\n#define BIT_GET_BT_RPT_SAMPLE_RATE_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C) &                         \\\n\t BIT_MASK_BT_RPT_SAMPLE_RATE_8822C)\n#define BIT_SET_BT_RPT_SAMPLE_RATE_8822C(x, v)                                 \\\n\t(BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822C(x) |                               \\\n\t BIT_BT_RPT_SAMPLE_RATE_8822C(v))\n\n/* 2 REG_BT_ACT_REGISTER_8822C */\n\n#define BIT_SHIFT_BT_EISR_EN_8822C 16\n#define BIT_MASK_BT_EISR_EN_8822C 0xff\n#define BIT_BT_EISR_EN_8822C(x)                                                \\\n\t(((x) & BIT_MASK_BT_EISR_EN_8822C) << BIT_SHIFT_BT_EISR_EN_8822C)\n#define BITS_BT_EISR_EN_8822C                                                  \\\n\t(BIT_MASK_BT_EISR_EN_8822C << BIT_SHIFT_BT_EISR_EN_8822C)\n#define BIT_CLEAR_BT_EISR_EN_8822C(x) ((x) & (~BITS_BT_EISR_EN_8822C))\n#define BIT_GET_BT_EISR_EN_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_BT_EISR_EN_8822C) & BIT_MASK_BT_EISR_EN_8822C)\n#define BIT_SET_BT_EISR_EN_8822C(x, v)                                         \\\n\t(BIT_CLEAR_BT_EISR_EN_8822C(x) | BIT_BT_EISR_EN_8822C(v))\n\n#define BIT_BT_ACT_FALLING_ISR_8822C BIT(10)\n#define BIT_BT_ACT_RISING_ISR_8822C BIT(9)\n#define BIT_TDMA_TO_ISR_8822C BIT(8)\n\n#define BIT_SHIFT_BT_CH_V1_8822C 0\n#define BIT_MASK_BT_CH_V1_8822C 0x7f\n#define BIT_BT_CH_V1_8822C(x)                                                  \\\n\t(((x) & BIT_MASK_BT_CH_V1_8822C) << BIT_SHIFT_BT_CH_V1_8822C)\n#define BITS_BT_CH_V1_8822C                                                    \\\n\t(BIT_MASK_BT_CH_V1_8822C << BIT_SHIFT_BT_CH_V1_8822C)\n#define BIT_CLEAR_BT_CH_V1_8822C(x) ((x) & (~BITS_BT_CH_V1_8822C))\n#define BIT_GET_BT_CH_V1_8822C(x)                                              \\\n\t(((x) >> BIT_SHIFT_BT_CH_V1_8822C) & BIT_MASK_BT_CH_V1_8822C)\n#define BIT_SET_BT_CH_V1_8822C(x, v)                                           \\\n\t(BIT_CLEAR_BT_CH_V1_8822C(x) | BIT_BT_CH_V1_8822C(v))\n\n/* 2 REG_OBFF_CTRL_BASIC_8822C */\n#define BIT_OBFF_EN_V1_8822C BIT(31)\n\n#define BIT_SHIFT_OBFF_STATE_V1_8822C 28\n#define BIT_MASK_OBFF_STATE_V1_8822C 0x3\n#define BIT_OBFF_STATE_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_OBFF_STATE_V1_8822C) << BIT_SHIFT_OBFF_STATE_V1_8822C)\n#define BITS_OBFF_STATE_V1_8822C                                               \\\n\t(BIT_MASK_OBFF_STATE_V1_8822C << BIT_SHIFT_OBFF_STATE_V1_8822C)\n#define BIT_CLEAR_OBFF_STATE_V1_8822C(x) ((x) & (~BITS_OBFF_STATE_V1_8822C))\n#define BIT_GET_OBFF_STATE_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_OBFF_STATE_V1_8822C) & BIT_MASK_OBFF_STATE_V1_8822C)\n#define BIT_SET_OBFF_STATE_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_OBFF_STATE_V1_8822C(x) | BIT_OBFF_STATE_V1_8822C(v))\n\n#define BIT_OBFF_ACT_RXDMA_EN_8822C BIT(27)\n#define BIT_OBFF_BLOCK_INT_EN_8822C BIT(26)\n#define BIT_OBFF_AUTOACT_EN_8822C BIT(25)\n#define BIT_OBFF_AUTOIDLE_EN_8822C BIT(24)\n\n#define BIT_SHIFT_WAKE_MAX_PLS_8822C 20\n#define BIT_MASK_WAKE_MAX_PLS_8822C 0x7\n#define BIT_WAKE_MAX_PLS_8822C(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MAX_PLS_8822C) << BIT_SHIFT_WAKE_MAX_PLS_8822C)\n#define BITS_WAKE_MAX_PLS_8822C                                                \\\n\t(BIT_MASK_WAKE_MAX_PLS_8822C << BIT_SHIFT_WAKE_MAX_PLS_8822C)\n#define BIT_CLEAR_WAKE_MAX_PLS_8822C(x) ((x) & (~BITS_WAKE_MAX_PLS_8822C))\n#define BIT_GET_WAKE_MAX_PLS_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MAX_PLS_8822C) & BIT_MASK_WAKE_MAX_PLS_8822C)\n#define BIT_SET_WAKE_MAX_PLS_8822C(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MAX_PLS_8822C(x) | BIT_WAKE_MAX_PLS_8822C(v))\n\n#define BIT_SHIFT_WAKE_MIN_PLS_8822C 16\n#define BIT_MASK_WAKE_MIN_PLS_8822C 0x7\n#define BIT_WAKE_MIN_PLS_8822C(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MIN_PLS_8822C) << BIT_SHIFT_WAKE_MIN_PLS_8822C)\n#define BITS_WAKE_MIN_PLS_8822C                                                \\\n\t(BIT_MASK_WAKE_MIN_PLS_8822C << BIT_SHIFT_WAKE_MIN_PLS_8822C)\n#define BIT_CLEAR_WAKE_MIN_PLS_8822C(x) ((x) & (~BITS_WAKE_MIN_PLS_8822C))\n#define BIT_GET_WAKE_MIN_PLS_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MIN_PLS_8822C) & BIT_MASK_WAKE_MIN_PLS_8822C)\n#define BIT_SET_WAKE_MIN_PLS_8822C(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MIN_PLS_8822C(x) | BIT_WAKE_MIN_PLS_8822C(v))\n\n#define BIT_SHIFT_WAKE_MAX_F2F_8822C 12\n#define BIT_MASK_WAKE_MAX_F2F_8822C 0x7\n#define BIT_WAKE_MAX_F2F_8822C(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MAX_F2F_8822C) << BIT_SHIFT_WAKE_MAX_F2F_8822C)\n#define BITS_WAKE_MAX_F2F_8822C                                                \\\n\t(BIT_MASK_WAKE_MAX_F2F_8822C << BIT_SHIFT_WAKE_MAX_F2F_8822C)\n#define BIT_CLEAR_WAKE_MAX_F2F_8822C(x) ((x) & (~BITS_WAKE_MAX_F2F_8822C))\n#define BIT_GET_WAKE_MAX_F2F_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MAX_F2F_8822C) & BIT_MASK_WAKE_MAX_F2F_8822C)\n#define BIT_SET_WAKE_MAX_F2F_8822C(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MAX_F2F_8822C(x) | BIT_WAKE_MAX_F2F_8822C(v))\n\n#define BIT_SHIFT_WAKE_MIN_F2F_8822C 8\n#define BIT_MASK_WAKE_MIN_F2F_8822C 0x7\n#define BIT_WAKE_MIN_F2F_8822C(x)                                              \\\n\t(((x) & BIT_MASK_WAKE_MIN_F2F_8822C) << BIT_SHIFT_WAKE_MIN_F2F_8822C)\n#define BITS_WAKE_MIN_F2F_8822C                                                \\\n\t(BIT_MASK_WAKE_MIN_F2F_8822C << BIT_SHIFT_WAKE_MIN_F2F_8822C)\n#define BIT_CLEAR_WAKE_MIN_F2F_8822C(x) ((x) & (~BITS_WAKE_MIN_F2F_8822C))\n#define BIT_GET_WAKE_MIN_F2F_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_WAKE_MIN_F2F_8822C) & BIT_MASK_WAKE_MIN_F2F_8822C)\n#define BIT_SET_WAKE_MIN_F2F_8822C(x, v)                                       \\\n\t(BIT_CLEAR_WAKE_MIN_F2F_8822C(x) | BIT_WAKE_MIN_F2F_8822C(v))\n\n#define BIT_APP_CPU_ACT_V1_8822C BIT(3)\n#define BIT_APP_OBFF_V1_8822C BIT(2)\n#define BIT_APP_IDLE_V1_8822C BIT(1)\n#define BIT_APP_INIT_V1_8822C BIT(0)\n\n/* 2 REG_OBFF_CTRL2_TIMER_8822C */\n\n#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C 24\n#define BIT_MASK_RX_HIGH_TIMER_IDX_8822C 0x7\n#define BIT_RX_HIGH_TIMER_IDX_8822C(x)                                         \\\n\t(((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8822C)                              \\\n\t << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C)\n#define BITS_RX_HIGH_TIMER_IDX_8822C                                           \\\n\t(BIT_MASK_RX_HIGH_TIMER_IDX_8822C << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C)\n#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8822C(x)                                   \\\n\t((x) & (~BITS_RX_HIGH_TIMER_IDX_8822C))\n#define BIT_GET_RX_HIGH_TIMER_IDX_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C) &                          \\\n\t BIT_MASK_RX_HIGH_TIMER_IDX_8822C)\n#define BIT_SET_RX_HIGH_TIMER_IDX_8822C(x, v)                                  \\\n\t(BIT_CLEAR_RX_HIGH_TIMER_IDX_8822C(x) | BIT_RX_HIGH_TIMER_IDX_8822C(v))\n\n#define BIT_SHIFT_RX_MED_TIMER_IDX_8822C 16\n#define BIT_MASK_RX_MED_TIMER_IDX_8822C 0x7\n#define BIT_RX_MED_TIMER_IDX_8822C(x)                                          \\\n\t(((x) & BIT_MASK_RX_MED_TIMER_IDX_8822C)                               \\\n\t << BIT_SHIFT_RX_MED_TIMER_IDX_8822C)\n#define BITS_RX_MED_TIMER_IDX_8822C                                            \\\n\t(BIT_MASK_RX_MED_TIMER_IDX_8822C << BIT_SHIFT_RX_MED_TIMER_IDX_8822C)\n#define BIT_CLEAR_RX_MED_TIMER_IDX_8822C(x)                                    \\\n\t((x) & (~BITS_RX_MED_TIMER_IDX_8822C))\n#define BIT_GET_RX_MED_TIMER_IDX_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8822C) &                           \\\n\t BIT_MASK_RX_MED_TIMER_IDX_8822C)\n#define BIT_SET_RX_MED_TIMER_IDX_8822C(x, v)                                   \\\n\t(BIT_CLEAR_RX_MED_TIMER_IDX_8822C(x) | BIT_RX_MED_TIMER_IDX_8822C(v))\n\n#define BIT_SHIFT_RX_LOW_TIMER_IDX_8822C 8\n#define BIT_MASK_RX_LOW_TIMER_IDX_8822C 0x7\n#define BIT_RX_LOW_TIMER_IDX_8822C(x)                                          \\\n\t(((x) & BIT_MASK_RX_LOW_TIMER_IDX_8822C)                               \\\n\t << BIT_SHIFT_RX_LOW_TIMER_IDX_8822C)\n#define BITS_RX_LOW_TIMER_IDX_8822C                                            \\\n\t(BIT_MASK_RX_LOW_TIMER_IDX_8822C << BIT_SHIFT_RX_LOW_TIMER_IDX_8822C)\n#define BIT_CLEAR_RX_LOW_TIMER_IDX_8822C(x)                                    \\\n\t((x) & (~BITS_RX_LOW_TIMER_IDX_8822C))\n#define BIT_GET_RX_LOW_TIMER_IDX_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8822C) &                           \\\n\t BIT_MASK_RX_LOW_TIMER_IDX_8822C)\n#define BIT_SET_RX_LOW_TIMER_IDX_8822C(x, v)                                   \\\n\t(BIT_CLEAR_RX_LOW_TIMER_IDX_8822C(x) | BIT_RX_LOW_TIMER_IDX_8822C(v))\n\n#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C 0\n#define BIT_MASK_OBFF_INT_TIMER_IDX_8822C 0x7\n#define BIT_OBFF_INT_TIMER_IDX_8822C(x)                                        \\\n\t(((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8822C)                             \\\n\t << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C)\n#define BITS_OBFF_INT_TIMER_IDX_8822C                                          \\\n\t(BIT_MASK_OBFF_INT_TIMER_IDX_8822C                                     \\\n\t << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C)\n#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8822C(x)                                  \\\n\t((x) & (~BITS_OBFF_INT_TIMER_IDX_8822C))\n#define BIT_GET_OBFF_INT_TIMER_IDX_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C) &                         \\\n\t BIT_MASK_OBFF_INT_TIMER_IDX_8822C)\n#define BIT_SET_OBFF_INT_TIMER_IDX_8822C(x, v)                                 \\\n\t(BIT_CLEAR_OBFF_INT_TIMER_IDX_8822C(x) |                               \\\n\t BIT_OBFF_INT_TIMER_IDX_8822C(v))\n\n/* 2 REG_LTR_CTRL_BASIC_8822C */\n#define BIT_LTR_EN_V1_8822C BIT(31)\n#define BIT_LTR_HW_EN_V1_8822C BIT(30)\n#define BIT_LRT_ACT_CTS_EN_8822C BIT(29)\n#define BIT_LTR_ACT_RXPKT_EN_8822C BIT(28)\n#define BIT_LTR_ACT_RXDMA_EN_8822C BIT(27)\n#define BIT_LTR_IDLE_NO_SNOOP_8822C BIT(26)\n#define BIT_SPDUP_MGTPKT_8822C BIT(25)\n#define BIT_RX_AGG_EN_8822C BIT(24)\n#define BIT_APP_LTR_ACT_8822C BIT(23)\n#define BIT_APP_LTR_IDLE_8822C BIT(22)\n\n#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C 20\n#define BIT_MASK_HIGH_RATE_TRIG_SEL_8822C 0x3\n#define BIT_HIGH_RATE_TRIG_SEL_8822C(x)                                        \\\n\t(((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822C)                             \\\n\t << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C)\n#define BITS_HIGH_RATE_TRIG_SEL_8822C                                          \\\n\t(BIT_MASK_HIGH_RATE_TRIG_SEL_8822C                                     \\\n\t << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C)\n#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822C(x)                                  \\\n\t((x) & (~BITS_HIGH_RATE_TRIG_SEL_8822C))\n#define BIT_GET_HIGH_RATE_TRIG_SEL_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C) &                         \\\n\t BIT_MASK_HIGH_RATE_TRIG_SEL_8822C)\n#define BIT_SET_HIGH_RATE_TRIG_SEL_8822C(x, v)                                 \\\n\t(BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822C(x) |                               \\\n\t BIT_HIGH_RATE_TRIG_SEL_8822C(v))\n\n#define BIT_SHIFT_MED_RATE_TRIG_SEL_8822C 18\n#define BIT_MASK_MED_RATE_TRIG_SEL_8822C 0x3\n#define BIT_MED_RATE_TRIG_SEL_8822C(x)                                         \\\n\t(((x) & BIT_MASK_MED_RATE_TRIG_SEL_8822C)                              \\\n\t << BIT_SHIFT_MED_RATE_TRIG_SEL_8822C)\n#define BITS_MED_RATE_TRIG_SEL_8822C                                           \\\n\t(BIT_MASK_MED_RATE_TRIG_SEL_8822C << BIT_SHIFT_MED_RATE_TRIG_SEL_8822C)\n#define BIT_CLEAR_MED_RATE_TRIG_SEL_8822C(x)                                   \\\n\t((x) & (~BITS_MED_RATE_TRIG_SEL_8822C))\n#define BIT_GET_MED_RATE_TRIG_SEL_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8822C) &                          \\\n\t BIT_MASK_MED_RATE_TRIG_SEL_8822C)\n#define BIT_SET_MED_RATE_TRIG_SEL_8822C(x, v)                                  \\\n\t(BIT_CLEAR_MED_RATE_TRIG_SEL_8822C(x) | BIT_MED_RATE_TRIG_SEL_8822C(v))\n\n#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C 16\n#define BIT_MASK_LOW_RATE_TRIG_SEL_8822C 0x3\n#define BIT_LOW_RATE_TRIG_SEL_8822C(x)                                         \\\n\t(((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8822C)                              \\\n\t << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C)\n#define BITS_LOW_RATE_TRIG_SEL_8822C                                           \\\n\t(BIT_MASK_LOW_RATE_TRIG_SEL_8822C << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C)\n#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8822C(x)                                   \\\n\t((x) & (~BITS_LOW_RATE_TRIG_SEL_8822C))\n#define BIT_GET_LOW_RATE_TRIG_SEL_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C) &                          \\\n\t BIT_MASK_LOW_RATE_TRIG_SEL_8822C)\n#define BIT_SET_LOW_RATE_TRIG_SEL_8822C(x, v)                                  \\\n\t(BIT_CLEAR_LOW_RATE_TRIG_SEL_8822C(x) | BIT_LOW_RATE_TRIG_SEL_8822C(v))\n\n#define BIT_SHIFT_HIGH_RATE_BD_IDX_8822C 8\n#define BIT_MASK_HIGH_RATE_BD_IDX_8822C 0x7f\n#define BIT_HIGH_RATE_BD_IDX_8822C(x)                                          \\\n\t(((x) & BIT_MASK_HIGH_RATE_BD_IDX_8822C)                               \\\n\t << BIT_SHIFT_HIGH_RATE_BD_IDX_8822C)\n#define BITS_HIGH_RATE_BD_IDX_8822C                                            \\\n\t(BIT_MASK_HIGH_RATE_BD_IDX_8822C << BIT_SHIFT_HIGH_RATE_BD_IDX_8822C)\n#define BIT_CLEAR_HIGH_RATE_BD_IDX_8822C(x)                                    \\\n\t((x) & (~BITS_HIGH_RATE_BD_IDX_8822C))\n#define BIT_GET_HIGH_RATE_BD_IDX_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8822C) &                           \\\n\t BIT_MASK_HIGH_RATE_BD_IDX_8822C)\n#define BIT_SET_HIGH_RATE_BD_IDX_8822C(x, v)                                   \\\n\t(BIT_CLEAR_HIGH_RATE_BD_IDX_8822C(x) | BIT_HIGH_RATE_BD_IDX_8822C(v))\n\n#define BIT_SHIFT_LOW_RATE_BD_IDX_8822C 0\n#define BIT_MASK_LOW_RATE_BD_IDX_8822C 0x7f\n#define BIT_LOW_RATE_BD_IDX_8822C(x)                                           \\\n\t(((x) & BIT_MASK_LOW_RATE_BD_IDX_8822C)                                \\\n\t << BIT_SHIFT_LOW_RATE_BD_IDX_8822C)\n#define BITS_LOW_RATE_BD_IDX_8822C                                             \\\n\t(BIT_MASK_LOW_RATE_BD_IDX_8822C << BIT_SHIFT_LOW_RATE_BD_IDX_8822C)\n#define BIT_CLEAR_LOW_RATE_BD_IDX_8822C(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8822C))\n#define BIT_GET_LOW_RATE_BD_IDX_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8822C) &                            \\\n\t BIT_MASK_LOW_RATE_BD_IDX_8822C)\n#define BIT_SET_LOW_RATE_BD_IDX_8822C(x, v)                                    \\\n\t(BIT_CLEAR_LOW_RATE_BD_IDX_8822C(x) | BIT_LOW_RATE_BD_IDX_8822C(v))\n\n/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8822C */\n\n#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C 24\n#define BIT_MASK_RX_EMPTY_TIMER_IDX_8822C 0x7\n#define BIT_RX_EMPTY_TIMER_IDX_8822C(x)                                        \\\n\t(((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822C)                             \\\n\t << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C)\n#define BITS_RX_EMPTY_TIMER_IDX_8822C                                          \\\n\t(BIT_MASK_RX_EMPTY_TIMER_IDX_8822C                                     \\\n\t << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C)\n#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822C(x)                                  \\\n\t((x) & (~BITS_RX_EMPTY_TIMER_IDX_8822C))\n#define BIT_GET_RX_EMPTY_TIMER_IDX_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C) &                         \\\n\t BIT_MASK_RX_EMPTY_TIMER_IDX_8822C)\n#define BIT_SET_RX_EMPTY_TIMER_IDX_8822C(x, v)                                 \\\n\t(BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822C(x) |                               \\\n\t BIT_RX_EMPTY_TIMER_IDX_8822C(v))\n\n#define BIT_SHIFT_RX_AFULL_TH_IDX_8822C 20\n#define BIT_MASK_RX_AFULL_TH_IDX_8822C 0x7\n#define BIT_RX_AFULL_TH_IDX_8822C(x)                                           \\\n\t(((x) & BIT_MASK_RX_AFULL_TH_IDX_8822C)                                \\\n\t << BIT_SHIFT_RX_AFULL_TH_IDX_8822C)\n#define BITS_RX_AFULL_TH_IDX_8822C                                             \\\n\t(BIT_MASK_RX_AFULL_TH_IDX_8822C << BIT_SHIFT_RX_AFULL_TH_IDX_8822C)\n#define BIT_CLEAR_RX_AFULL_TH_IDX_8822C(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8822C))\n#define BIT_GET_RX_AFULL_TH_IDX_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8822C) &                            \\\n\t BIT_MASK_RX_AFULL_TH_IDX_8822C)\n#define BIT_SET_RX_AFULL_TH_IDX_8822C(x, v)                                    \\\n\t(BIT_CLEAR_RX_AFULL_TH_IDX_8822C(x) | BIT_RX_AFULL_TH_IDX_8822C(v))\n\n#define BIT_SHIFT_RX_HIGH_TH_IDX_8822C 16\n#define BIT_MASK_RX_HIGH_TH_IDX_8822C 0x7\n#define BIT_RX_HIGH_TH_IDX_8822C(x)                                            \\\n\t(((x) & BIT_MASK_RX_HIGH_TH_IDX_8822C)                                 \\\n\t << BIT_SHIFT_RX_HIGH_TH_IDX_8822C)\n#define BITS_RX_HIGH_TH_IDX_8822C                                              \\\n\t(BIT_MASK_RX_HIGH_TH_IDX_8822C << BIT_SHIFT_RX_HIGH_TH_IDX_8822C)\n#define BIT_CLEAR_RX_HIGH_TH_IDX_8822C(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8822C))\n#define BIT_GET_RX_HIGH_TH_IDX_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8822C) &                             \\\n\t BIT_MASK_RX_HIGH_TH_IDX_8822C)\n#define BIT_SET_RX_HIGH_TH_IDX_8822C(x, v)                                     \\\n\t(BIT_CLEAR_RX_HIGH_TH_IDX_8822C(x) | BIT_RX_HIGH_TH_IDX_8822C(v))\n\n#define BIT_SHIFT_RX_MED_TH_IDX_8822C 12\n#define BIT_MASK_RX_MED_TH_IDX_8822C 0x7\n#define BIT_RX_MED_TH_IDX_8822C(x)                                             \\\n\t(((x) & BIT_MASK_RX_MED_TH_IDX_8822C) << BIT_SHIFT_RX_MED_TH_IDX_8822C)\n#define BITS_RX_MED_TH_IDX_8822C                                               \\\n\t(BIT_MASK_RX_MED_TH_IDX_8822C << BIT_SHIFT_RX_MED_TH_IDX_8822C)\n#define BIT_CLEAR_RX_MED_TH_IDX_8822C(x) ((x) & (~BITS_RX_MED_TH_IDX_8822C))\n#define BIT_GET_RX_MED_TH_IDX_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_RX_MED_TH_IDX_8822C) & BIT_MASK_RX_MED_TH_IDX_8822C)\n#define BIT_SET_RX_MED_TH_IDX_8822C(x, v)                                      \\\n\t(BIT_CLEAR_RX_MED_TH_IDX_8822C(x) | BIT_RX_MED_TH_IDX_8822C(v))\n\n#define BIT_SHIFT_RX_LOW_TH_IDX_8822C 8\n#define BIT_MASK_RX_LOW_TH_IDX_8822C 0x7\n#define BIT_RX_LOW_TH_IDX_8822C(x)                                             \\\n\t(((x) & BIT_MASK_RX_LOW_TH_IDX_8822C) << BIT_SHIFT_RX_LOW_TH_IDX_8822C)\n#define BITS_RX_LOW_TH_IDX_8822C                                               \\\n\t(BIT_MASK_RX_LOW_TH_IDX_8822C << BIT_SHIFT_RX_LOW_TH_IDX_8822C)\n#define BIT_CLEAR_RX_LOW_TH_IDX_8822C(x) ((x) & (~BITS_RX_LOW_TH_IDX_8822C))\n#define BIT_GET_RX_LOW_TH_IDX_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8822C) & BIT_MASK_RX_LOW_TH_IDX_8822C)\n#define BIT_SET_RX_LOW_TH_IDX_8822C(x, v)                                      \\\n\t(BIT_CLEAR_RX_LOW_TH_IDX_8822C(x) | BIT_RX_LOW_TH_IDX_8822C(v))\n\n#define BIT_SHIFT_LTR_SPACE_IDX_8822C 4\n#define BIT_MASK_LTR_SPACE_IDX_8822C 0x3\n#define BIT_LTR_SPACE_IDX_8822C(x)                                             \\\n\t(((x) & BIT_MASK_LTR_SPACE_IDX_8822C) << BIT_SHIFT_LTR_SPACE_IDX_8822C)\n#define BITS_LTR_SPACE_IDX_8822C                                               \\\n\t(BIT_MASK_LTR_SPACE_IDX_8822C << BIT_SHIFT_LTR_SPACE_IDX_8822C)\n#define BIT_CLEAR_LTR_SPACE_IDX_8822C(x) ((x) & (~BITS_LTR_SPACE_IDX_8822C))\n#define BIT_GET_LTR_SPACE_IDX_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_LTR_SPACE_IDX_8822C) & BIT_MASK_LTR_SPACE_IDX_8822C)\n#define BIT_SET_LTR_SPACE_IDX_8822C(x, v)                                      \\\n\t(BIT_CLEAR_LTR_SPACE_IDX_8822C(x) | BIT_LTR_SPACE_IDX_8822C(v))\n\n#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C 0\n#define BIT_MASK_LTR_IDLE_TIMER_IDX_8822C 0x7\n#define BIT_LTR_IDLE_TIMER_IDX_8822C(x)                                        \\\n\t(((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822C)                             \\\n\t << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C)\n#define BITS_LTR_IDLE_TIMER_IDX_8822C                                          \\\n\t(BIT_MASK_LTR_IDLE_TIMER_IDX_8822C                                     \\\n\t << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C)\n#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822C(x)                                  \\\n\t((x) & (~BITS_LTR_IDLE_TIMER_IDX_8822C))\n#define BIT_GET_LTR_IDLE_TIMER_IDX_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C) &                         \\\n\t BIT_MASK_LTR_IDLE_TIMER_IDX_8822C)\n#define BIT_SET_LTR_IDLE_TIMER_IDX_8822C(x, v)                                 \\\n\t(BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822C(x) |                               \\\n\t BIT_LTR_IDLE_TIMER_IDX_8822C(v))\n\n/* 2 REG_LTR_IDLE_LATENCY_V1_8822C */\n\n#define BIT_SHIFT_LTR_IDLE_L_8822C 0\n#define BIT_MASK_LTR_IDLE_L_8822C 0xffffffffL\n#define BIT_LTR_IDLE_L_8822C(x)                                                \\\n\t(((x) & BIT_MASK_LTR_IDLE_L_8822C) << BIT_SHIFT_LTR_IDLE_L_8822C)\n#define BITS_LTR_IDLE_L_8822C                                                  \\\n\t(BIT_MASK_LTR_IDLE_L_8822C << BIT_SHIFT_LTR_IDLE_L_8822C)\n#define BIT_CLEAR_LTR_IDLE_L_8822C(x) ((x) & (~BITS_LTR_IDLE_L_8822C))\n#define BIT_GET_LTR_IDLE_L_8822C(x)                                            \\\n\t(((x) >> BIT_SHIFT_LTR_IDLE_L_8822C) & BIT_MASK_LTR_IDLE_L_8822C)\n#define BIT_SET_LTR_IDLE_L_8822C(x, v)                                         \\\n\t(BIT_CLEAR_LTR_IDLE_L_8822C(x) | BIT_LTR_IDLE_L_8822C(v))\n\n/* 2 REG_LTR_ACTIVE_LATENCY_V1_8822C */\n\n#define BIT_SHIFT_LTR_ACT_L_8822C 0\n#define BIT_MASK_LTR_ACT_L_8822C 0xffffffffL\n#define BIT_LTR_ACT_L_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_LTR_ACT_L_8822C) << BIT_SHIFT_LTR_ACT_L_8822C)\n#define BITS_LTR_ACT_L_8822C                                                   \\\n\t(BIT_MASK_LTR_ACT_L_8822C << BIT_SHIFT_LTR_ACT_L_8822C)\n#define BIT_CLEAR_LTR_ACT_L_8822C(x) ((x) & (~BITS_LTR_ACT_L_8822C))\n#define BIT_GET_LTR_ACT_L_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_LTR_ACT_L_8822C) & BIT_MASK_LTR_ACT_L_8822C)\n#define BIT_SET_LTR_ACT_L_8822C(x, v)                                          \\\n\t(BIT_CLEAR_LTR_ACT_L_8822C(x) | BIT_LTR_ACT_L_8822C(v))\n\n/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822C */\n\n#define BIT_SHIFT_TRAIN_STA_ADDR_0_8822C 0\n#define BIT_MASK_TRAIN_STA_ADDR_0_8822C 0xffffffffL\n#define BIT_TRAIN_STA_ADDR_0_8822C(x)                                          \\\n\t(((x) & BIT_MASK_TRAIN_STA_ADDR_0_8822C)                               \\\n\t << BIT_SHIFT_TRAIN_STA_ADDR_0_8822C)\n#define BITS_TRAIN_STA_ADDR_0_8822C                                            \\\n\t(BIT_MASK_TRAIN_STA_ADDR_0_8822C << BIT_SHIFT_TRAIN_STA_ADDR_0_8822C)\n#define BIT_CLEAR_TRAIN_STA_ADDR_0_8822C(x)                                    \\\n\t((x) & (~BITS_TRAIN_STA_ADDR_0_8822C))\n#define BIT_GET_TRAIN_STA_ADDR_0_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0_8822C) &                           \\\n\t BIT_MASK_TRAIN_STA_ADDR_0_8822C)\n#define BIT_SET_TRAIN_STA_ADDR_0_8822C(x, v)                                   \\\n\t(BIT_CLEAR_TRAIN_STA_ADDR_0_8822C(x) | BIT_TRAIN_STA_ADDR_0_8822C(v))\n\n/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8822C */\n#define BIT_ANTTRN_SWITCH_8822C BIT(19)\n#define BIT_APPEND_MACID_IN_RESP_EN_1_8822C BIT(18)\n#define BIT_ADDR2_MATCH_EN_1_8822C BIT(17)\n#define BIT_ANTTRN_EN_1_8822C BIT(16)\n\n#define BIT_SHIFT_TRAIN_STA_ADDR_1_8822C 0\n#define BIT_MASK_TRAIN_STA_ADDR_1_8822C 0xffff\n#define BIT_TRAIN_STA_ADDR_1_8822C(x)                                          \\\n\t(((x) & BIT_MASK_TRAIN_STA_ADDR_1_8822C)                               \\\n\t << BIT_SHIFT_TRAIN_STA_ADDR_1_8822C)\n#define BITS_TRAIN_STA_ADDR_1_8822C                                            \\\n\t(BIT_MASK_TRAIN_STA_ADDR_1_8822C << BIT_SHIFT_TRAIN_STA_ADDR_1_8822C)\n#define BIT_CLEAR_TRAIN_STA_ADDR_1_8822C(x)                                    \\\n\t((x) & (~BITS_TRAIN_STA_ADDR_1_8822C))\n#define BIT_GET_TRAIN_STA_ADDR_1_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1_8822C) &                           \\\n\t BIT_MASK_TRAIN_STA_ADDR_1_8822C)\n#define BIT_SET_TRAIN_STA_ADDR_1_8822C(x, v)                                   \\\n\t(BIT_CLEAR_TRAIN_STA_ADDR_1_8822C(x) | BIT_TRAIN_STA_ADDR_1_8822C(v))\n\n/* 2 REG_WMAC_PKTCNT_RWD_8822C */\n\n#define BIT_SHIFT_PKTCNT_BSSIDMAP_8822C 4\n#define BIT_MASK_PKTCNT_BSSIDMAP_8822C 0xf\n#define BIT_PKTCNT_BSSIDMAP_8822C(x)                                           \\\n\t(((x) & BIT_MASK_PKTCNT_BSSIDMAP_8822C)                                \\\n\t << BIT_SHIFT_PKTCNT_BSSIDMAP_8822C)\n#define BITS_PKTCNT_BSSIDMAP_8822C                                             \\\n\t(BIT_MASK_PKTCNT_BSSIDMAP_8822C << BIT_SHIFT_PKTCNT_BSSIDMAP_8822C)\n#define BIT_CLEAR_PKTCNT_BSSIDMAP_8822C(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8822C))\n#define BIT_GET_PKTCNT_BSSIDMAP_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8822C) &                            \\\n\t BIT_MASK_PKTCNT_BSSIDMAP_8822C)\n#define BIT_SET_PKTCNT_BSSIDMAP_8822C(x, v)                                    \\\n\t(BIT_CLEAR_PKTCNT_BSSIDMAP_8822C(x) | BIT_PKTCNT_BSSIDMAP_8822C(v))\n\n#define BIT_PKTCNT_CNTRST_8822C BIT(1)\n#define BIT_PKTCNT_CNTEN_8822C BIT(0)\n\n/* 2 REG_WMAC_PKTCNT_CTRL_8822C */\n#define BIT_WMAC_PKTCNT_TRST_8822C BIT(9)\n#define BIT_WMAC_PKTCNT_FEN_8822C BIT(8)\n\n#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C 0\n#define BIT_MASK_WMAC_PKTCNT_CFGAD_8822C 0xff\n#define BIT_WMAC_PKTCNT_CFGAD_8822C(x)                                         \\\n\t(((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822C)                              \\\n\t << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C)\n#define BITS_WMAC_PKTCNT_CFGAD_8822C                                           \\\n\t(BIT_MASK_WMAC_PKTCNT_CFGAD_8822C << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C)\n#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822C(x)                                   \\\n\t((x) & (~BITS_WMAC_PKTCNT_CFGAD_8822C))\n#define BIT_GET_WMAC_PKTCNT_CFGAD_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C) &                          \\\n\t BIT_MASK_WMAC_PKTCNT_CFGAD_8822C)\n#define BIT_SET_WMAC_PKTCNT_CFGAD_8822C(x, v)                                  \\\n\t(BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822C(x) | BIT_WMAC_PKTCNT_CFGAD_8822C(v))\n\n/* 2 REG_IQ_DUMP_8822C */\n\n#define BIT_SHIFT_DUMP_OK_ADDR_8822C 16\n#define BIT_MASK_DUMP_OK_ADDR_8822C 0xffff\n#define BIT_DUMP_OK_ADDR_8822C(x)                                              \\\n\t(((x) & BIT_MASK_DUMP_OK_ADDR_8822C) << BIT_SHIFT_DUMP_OK_ADDR_8822C)\n#define BITS_DUMP_OK_ADDR_8822C                                                \\\n\t(BIT_MASK_DUMP_OK_ADDR_8822C << BIT_SHIFT_DUMP_OK_ADDR_8822C)\n#define BIT_CLEAR_DUMP_OK_ADDR_8822C(x) ((x) & (~BITS_DUMP_OK_ADDR_8822C))\n#define BIT_GET_DUMP_OK_ADDR_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_DUMP_OK_ADDR_8822C) & BIT_MASK_DUMP_OK_ADDR_8822C)\n#define BIT_SET_DUMP_OK_ADDR_8822C(x, v)                                       \\\n\t(BIT_CLEAR_DUMP_OK_ADDR_8822C(x) | BIT_DUMP_OK_ADDR_8822C(v))\n\n#define BIT_MACDBG_TRIG_IQDUMP_8822C BIT(15)\n\n#define BIT_SHIFT_R_TRIG_TIME_SEL_8822C 8\n#define BIT_MASK_R_TRIG_TIME_SEL_8822C 0x7f\n#define BIT_R_TRIG_TIME_SEL_8822C(x)                                           \\\n\t(((x) & BIT_MASK_R_TRIG_TIME_SEL_8822C)                                \\\n\t << BIT_SHIFT_R_TRIG_TIME_SEL_8822C)\n#define BITS_R_TRIG_TIME_SEL_8822C                                             \\\n\t(BIT_MASK_R_TRIG_TIME_SEL_8822C << BIT_SHIFT_R_TRIG_TIME_SEL_8822C)\n#define BIT_CLEAR_R_TRIG_TIME_SEL_8822C(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8822C))\n#define BIT_GET_R_TRIG_TIME_SEL_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8822C) &                            \\\n\t BIT_MASK_R_TRIG_TIME_SEL_8822C)\n#define BIT_SET_R_TRIG_TIME_SEL_8822C(x, v)                                    \\\n\t(BIT_CLEAR_R_TRIG_TIME_SEL_8822C(x) | BIT_R_TRIG_TIME_SEL_8822C(v))\n\n#define BIT_SHIFT_R_MAC_TRIG_SEL_8822C 6\n#define BIT_MASK_R_MAC_TRIG_SEL_8822C 0x3\n#define BIT_R_MAC_TRIG_SEL_8822C(x)                                            \\\n\t(((x) & BIT_MASK_R_MAC_TRIG_SEL_8822C)                                 \\\n\t << BIT_SHIFT_R_MAC_TRIG_SEL_8822C)\n#define BITS_R_MAC_TRIG_SEL_8822C                                              \\\n\t(BIT_MASK_R_MAC_TRIG_SEL_8822C << BIT_SHIFT_R_MAC_TRIG_SEL_8822C)\n#define BIT_CLEAR_R_MAC_TRIG_SEL_8822C(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8822C))\n#define BIT_GET_R_MAC_TRIG_SEL_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8822C) &                             \\\n\t BIT_MASK_R_MAC_TRIG_SEL_8822C)\n#define BIT_SET_R_MAC_TRIG_SEL_8822C(x, v)                                     \\\n\t(BIT_CLEAR_R_MAC_TRIG_SEL_8822C(x) | BIT_R_MAC_TRIG_SEL_8822C(v))\n\n#define BIT_MAC_TRIG_REG_8822C BIT(5)\n\n#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C 3\n#define BIT_MASK_R_LEVEL_PULSE_SEL_8822C 0x3\n#define BIT_R_LEVEL_PULSE_SEL_8822C(x)                                         \\\n\t(((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8822C)                              \\\n\t << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C)\n#define BITS_R_LEVEL_PULSE_SEL_8822C                                           \\\n\t(BIT_MASK_R_LEVEL_PULSE_SEL_8822C << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C)\n#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8822C(x)                                   \\\n\t((x) & (~BITS_R_LEVEL_PULSE_SEL_8822C))\n#define BIT_GET_R_LEVEL_PULSE_SEL_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C) &                          \\\n\t BIT_MASK_R_LEVEL_PULSE_SEL_8822C)\n#define BIT_SET_R_LEVEL_PULSE_SEL_8822C(x, v)                                  \\\n\t(BIT_CLEAR_R_LEVEL_PULSE_SEL_8822C(x) | BIT_R_LEVEL_PULSE_SEL_8822C(v))\n\n#define BIT_EN_LA_MAC_8822C BIT(2)\n#define BIT_R_EN_IQDUMP_8822C BIT(1)\n#define BIT_R_IQDATA_DUMP_8822C BIT(0)\n\n/* 2 REG_IQ_DUMP_1_8822C */\n\n#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C 0\n#define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C 0xffffffffL\n#define BIT_R_WMAC_MASK_LA_MAC_1_8822C(x)                                      \\\n\t(((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C)                           \\\n\t << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C)\n#define BITS_R_WMAC_MASK_LA_MAC_1_8822C                                        \\\n\t(BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C                                   \\\n\t << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C)\n#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8822C(x)                                \\\n\t((x) & (~BITS_R_WMAC_MASK_LA_MAC_1_8822C))\n#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C) &                       \\\n\t BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C)\n#define BIT_SET_R_WMAC_MASK_LA_MAC_1_8822C(x, v)                               \\\n\t(BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8822C(x) |                             \\\n\t BIT_R_WMAC_MASK_LA_MAC_1_8822C(v))\n\n/* 2 REG_IQ_DUMP_2_8822C */\n\n#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C 0\n#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C 0xffffffffL\n#define BIT_R_WMAC_MATCH_REF_MAC_2_8822C(x)                                    \\\n\t(((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C)                         \\\n\t << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C)\n#define BITS_R_WMAC_MATCH_REF_MAC_2_8822C                                      \\\n\t(BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C                                 \\\n\t << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C)\n#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8822C(x)                              \\\n\t((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2_8822C))\n#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8822C(x)                                \\\n\t(((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C) &                     \\\n\t BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C)\n#define BIT_SET_R_WMAC_MATCH_REF_MAC_2_8822C(x, v)                             \\\n\t(BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8822C(x) |                           \\\n\t BIT_R_WMAC_MATCH_REF_MAC_2_8822C(v))\n\n/* 2 REG_WMAC_FTM_CTL_8822C */\n#define BIT_RXFTM_TXACK_SC_8822C BIT(6)\n#define BIT_RXFTM_TXACK_BW_8822C BIT(5)\n#define BIT_RXFTM_EN_8822C BIT(3)\n#define BIT_RXFTMREQ_BYDRV_8822C BIT(2)\n#define BIT_RXFTMREQ_EN_8822C BIT(1)\n#define BIT_FTM_EN_8822C BIT(0)\n\n/* 2 REG_WMAC_IQ_MDPK_FUNC_8822C */\n\n/* 2 REG_WMAC_OPTION_FUNCTION_8822C */\n\n#define BIT_SHIFT_R_OFDM_LEN_V1_8822C 16\n#define BIT_MASK_R_OFDM_LEN_V1_8822C 0xffff\n#define BIT_R_OFDM_LEN_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_R_OFDM_LEN_V1_8822C) << BIT_SHIFT_R_OFDM_LEN_V1_8822C)\n#define BITS_R_OFDM_LEN_V1_8822C                                               \\\n\t(BIT_MASK_R_OFDM_LEN_V1_8822C << BIT_SHIFT_R_OFDM_LEN_V1_8822C)\n#define BIT_CLEAR_R_OFDM_LEN_V1_8822C(x) ((x) & (~BITS_R_OFDM_LEN_V1_8822C))\n#define BIT_GET_R_OFDM_LEN_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_OFDM_LEN_V1_8822C) & BIT_MASK_R_OFDM_LEN_V1_8822C)\n#define BIT_SET_R_OFDM_LEN_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_R_OFDM_LEN_V1_8822C(x) | BIT_R_OFDM_LEN_V1_8822C(v))\n\n#define BIT_SHIFT_R_CCK_LEN_8822C 0\n#define BIT_MASK_R_CCK_LEN_8822C 0xffff\n#define BIT_R_CCK_LEN_8822C(x)                                                 \\\n\t(((x) & BIT_MASK_R_CCK_LEN_8822C) << BIT_SHIFT_R_CCK_LEN_8822C)\n#define BITS_R_CCK_LEN_8822C                                                   \\\n\t(BIT_MASK_R_CCK_LEN_8822C << BIT_SHIFT_R_CCK_LEN_8822C)\n#define BIT_CLEAR_R_CCK_LEN_8822C(x) ((x) & (~BITS_R_CCK_LEN_8822C))\n#define BIT_GET_R_CCK_LEN_8822C(x)                                             \\\n\t(((x) >> BIT_SHIFT_R_CCK_LEN_8822C) & BIT_MASK_R_CCK_LEN_8822C)\n#define BIT_SET_R_CCK_LEN_8822C(x, v)                                          \\\n\t(BIT_CLEAR_R_CCK_LEN_8822C(x) | BIT_R_CCK_LEN_8822C(v))\n\n/* 2 REG_WMAC_OPTION_FUNCTION_1_8822C */\n\n#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C 24\n#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C 0xff\n#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8822C(x)                                   \\\n\t(((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C)                        \\\n\t << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C)\n#define BITS_R_WMAC_RXFIFO_FULL_TH_1_8822C                                     \\\n\t(BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C                                \\\n\t << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C)\n#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8822C(x)                             \\\n\t((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1_8822C))\n#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8822C(x)                               \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C) &                    \\\n\t BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C)\n#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1_8822C(x, v)                            \\\n\t(BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8822C(x) |                          \\\n\t BIT_R_WMAC_RXFIFO_FULL_TH_1_8822C(v))\n\n#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8822C BIT(23)\n#define BIT_R_WMAC_RXRST_DLY_1_8822C BIT(22)\n#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1_8822C BIT(21)\n#define BIT_R_WMAC_SRCH_TXRPT_UA1_1_8822C BIT(20)\n#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1_8822C BIT(19)\n#define BIT_R_WMAC_NDP_RST_1_8822C BIT(18)\n#define BIT_R_WMAC_POWINT_EN_1_8822C BIT(17)\n#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1_8822C BIT(16)\n#define BIT_R_WMAC_SRCH_TXRPT_MID_1_8822C BIT(15)\n#define BIT_R_WMAC_PFIN_TOEN_1_8822C BIT(14)\n#define BIT_R_WMAC_FIL_SECERR_1_8822C BIT(13)\n#define BIT_R_WMAC_FIL_CTLPKTLEN_1_8822C BIT(12)\n#define BIT_R_WMAC_FIL_FCTYPE_1_8822C BIT(11)\n#define BIT_R_WMAC_FIL_FCPROVER_1_8822C BIT(10)\n#define BIT_R_WMAC_PHYSTS_SNIF_1_8822C BIT(9)\n#define BIT_R_WMAC_PHYSTS_PLCP_1_8822C BIT(8)\n#define BIT_R_MAC_TCR_VBONF_RD_1_8822C BIT(7)\n#define BIT_R_WMAC_TCR_MPAR_NDP_1_8822C BIT(6)\n#define BIT_R_WMAC_NDP_FILTER_1_8822C BIT(5)\n#define BIT_R_WMAC_RXLEN_SEL_1_8822C BIT(4)\n#define BIT_R_WMAC_RXLEN_SEL1_1_8822C BIT(3)\n#define BIT_R_OFDM_FILTER_1_8822C BIT(2)\n#define BIT_R_WMAC_CHK_OFDM_LEN_1_8822C BIT(1)\n#define BIT_R_WMAC_CHK_CCK_LEN_1_8822C BIT(0)\n\n/* 2 REG_WMAC_OPTION_FUNCTION_2_8822C */\n\n#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C 0\n#define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C 0xffff\n#define BIT_R_WMAC_RX_FIL_LEN_2_8822C(x)                                       \\\n\t(((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C)                            \\\n\t << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C)\n#define BITS_R_WMAC_RX_FIL_LEN_2_8822C                                         \\\n\t(BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C                                    \\\n\t << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C)\n#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8822C(x)                                 \\\n\t((x) & (~BITS_R_WMAC_RX_FIL_LEN_2_8822C))\n#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C) &                        \\\n\t BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C)\n#define BIT_SET_R_WMAC_RX_FIL_LEN_2_8822C(x, v)                                \\\n\t(BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8822C(x) |                              \\\n\t BIT_R_WMAC_RX_FIL_LEN_2_8822C(v))\n\n/* 2 REG_RX_FILTER_FUNCTION_8822C */\n#define BIT_RXHANG_EN_8822C BIT(15)\n#define BIT_R_WMAC_MHRDDY_LATCH_8822C BIT(14)\n#define BIT_R_WMAC_MHRDDY_CLR_8822C BIT(13)\n#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8822C BIT(12)\n#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU_8822C BIT(11)\n#define BIT_R_CHK_DELIMIT_LEN_8822C BIT(10)\n#define BIT_R_REAPTER_ADDR_MATCH_8822C BIT(9)\n#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8822C BIT(8)\n#define BIT_R_LATCH_MACHRDY_8822C BIT(7)\n#define BIT_R_WMAC_RXFIL_REND_8822C BIT(6)\n#define BIT_R_WMAC_MPDURDY_CLR_8822C BIT(5)\n#define BIT_R_WMAC_CLRRXSEC_8822C BIT(4)\n#define BIT_R_WMAC_RXFIL_RDEL_8822C BIT(3)\n#define BIT_R_WMAC_RXFIL_FCSE_8822C BIT(2)\n#define BIT_R_WMAC_RXFIL_MESH_DEL_8822C BIT(1)\n#define BIT_R_WMAC_RXFIL_MASKM_8822C BIT(0)\n\n/* 2 REG_NDP_SIG_8822C */\n\n#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C 0\n#define BIT_MASK_R_WMAC_TXNDP_SIGB_8822C 0x1fffff\n#define BIT_R_WMAC_TXNDP_SIGB_8822C(x)                                         \\\n\t(((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822C)                              \\\n\t << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C)\n#define BITS_R_WMAC_TXNDP_SIGB_8822C                                           \\\n\t(BIT_MASK_R_WMAC_TXNDP_SIGB_8822C << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C)\n#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822C(x)                                   \\\n\t((x) & (~BITS_R_WMAC_TXNDP_SIGB_8822C))\n#define BIT_GET_R_WMAC_TXNDP_SIGB_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C) &                          \\\n\t BIT_MASK_R_WMAC_TXNDP_SIGB_8822C)\n#define BIT_SET_R_WMAC_TXNDP_SIGB_8822C(x, v)                                  \\\n\t(BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822C(x) | BIT_R_WMAC_TXNDP_SIGB_8822C(v))\n\n/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8822C */\n\n#define BIT_SHIFT_R_MAC_DBG_SHIFT_8822C 8\n#define BIT_MASK_R_MAC_DBG_SHIFT_8822C 0x7\n#define BIT_R_MAC_DBG_SHIFT_8822C(x)                                           \\\n\t(((x) & BIT_MASK_R_MAC_DBG_SHIFT_8822C)                                \\\n\t << BIT_SHIFT_R_MAC_DBG_SHIFT_8822C)\n#define BITS_R_MAC_DBG_SHIFT_8822C                                             \\\n\t(BIT_MASK_R_MAC_DBG_SHIFT_8822C << BIT_SHIFT_R_MAC_DBG_SHIFT_8822C)\n#define BIT_CLEAR_R_MAC_DBG_SHIFT_8822C(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8822C))\n#define BIT_GET_R_MAC_DBG_SHIFT_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8822C) &                            \\\n\t BIT_MASK_R_MAC_DBG_SHIFT_8822C)\n#define BIT_SET_R_MAC_DBG_SHIFT_8822C(x, v)                                    \\\n\t(BIT_CLEAR_R_MAC_DBG_SHIFT_8822C(x) | BIT_R_MAC_DBG_SHIFT_8822C(v))\n\n#define BIT_SHIFT_R_MAC_DBG_SEL_8822C 0\n#define BIT_MASK_R_MAC_DBG_SEL_8822C 0x3\n#define BIT_R_MAC_DBG_SEL_8822C(x)                                             \\\n\t(((x) & BIT_MASK_R_MAC_DBG_SEL_8822C) << BIT_SHIFT_R_MAC_DBG_SEL_8822C)\n#define BITS_R_MAC_DBG_SEL_8822C                                               \\\n\t(BIT_MASK_R_MAC_DBG_SEL_8822C << BIT_SHIFT_R_MAC_DBG_SEL_8822C)\n#define BIT_CLEAR_R_MAC_DBG_SEL_8822C(x) ((x) & (~BITS_R_MAC_DBG_SEL_8822C))\n#define BIT_GET_R_MAC_DBG_SEL_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8822C) & BIT_MASK_R_MAC_DBG_SEL_8822C)\n#define BIT_SET_R_MAC_DBG_SEL_8822C(x, v)                                      \\\n\t(BIT_CLEAR_R_MAC_DBG_SEL_8822C(x) | BIT_R_MAC_DBG_SEL_8822C(v))\n\n/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8822C */\n\n#define BIT_SHIFT_R_MAC_DEBUG_1_8822C 0\n#define BIT_MASK_R_MAC_DEBUG_1_8822C 0xffffffffL\n#define BIT_R_MAC_DEBUG_1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_R_MAC_DEBUG_1_8822C) << BIT_SHIFT_R_MAC_DEBUG_1_8822C)\n#define BITS_R_MAC_DEBUG_1_8822C                                               \\\n\t(BIT_MASK_R_MAC_DEBUG_1_8822C << BIT_SHIFT_R_MAC_DEBUG_1_8822C)\n#define BIT_CLEAR_R_MAC_DEBUG_1_8822C(x) ((x) & (~BITS_R_MAC_DEBUG_1_8822C))\n#define BIT_GET_R_MAC_DEBUG_1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8822C) & BIT_MASK_R_MAC_DEBUG_1_8822C)\n#define BIT_SET_R_MAC_DEBUG_1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_R_MAC_DEBUG_1_8822C(x) | BIT_R_MAC_DEBUG_1_8822C(v))\n\n/* 2 REG_WSEC_OPTION_8822C */\n#define BIT_RXDEC_BM_MGNT_8822C BIT(22)\n#define BIT_TXENC_BM_MGNT_8822C BIT(21)\n#define BIT_RXDEC_UNI_MGNT_8822C BIT(20)\n#define BIT_TXENC_UNI_MGNT_8822C BIT(19)\n#define BIT_WMAC_SEC_MASKIV_8822C BIT(18)\n\n#define BIT_SHIFT_WMAC_SEC_PN_SEL_8822C 16\n#define BIT_MASK_WMAC_SEC_PN_SEL_8822C 0x3\n#define BIT_WMAC_SEC_PN_SEL_8822C(x)                                           \\\n\t(((x) & BIT_MASK_WMAC_SEC_PN_SEL_8822C)                                \\\n\t << BIT_SHIFT_WMAC_SEC_PN_SEL_8822C)\n#define BITS_WMAC_SEC_PN_SEL_8822C                                             \\\n\t(BIT_MASK_WMAC_SEC_PN_SEL_8822C << BIT_SHIFT_WMAC_SEC_PN_SEL_8822C)\n#define BIT_CLEAR_WMAC_SEC_PN_SEL_8822C(x) ((x) & (~BITS_WMAC_SEC_PN_SEL_8822C))\n#define BIT_GET_WMAC_SEC_PN_SEL_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_WMAC_SEC_PN_SEL_8822C) &                            \\\n\t BIT_MASK_WMAC_SEC_PN_SEL_8822C)\n#define BIT_SET_WMAC_SEC_PN_SEL_8822C(x, v)                                    \\\n\t(BIT_CLEAR_WMAC_SEC_PN_SEL_8822C(x) | BIT_WMAC_SEC_PN_SEL_8822C(v))\n\n#define BIT_SHIFT_BT_TIME_CNT_8822C 0\n#define BIT_MASK_BT_TIME_CNT_8822C 0xff\n#define BIT_BT_TIME_CNT_8822C(x)                                               \\\n\t(((x) & BIT_MASK_BT_TIME_CNT_8822C) << BIT_SHIFT_BT_TIME_CNT_8822C)\n#define BITS_BT_TIME_CNT_8822C                                                 \\\n\t(BIT_MASK_BT_TIME_CNT_8822C << BIT_SHIFT_BT_TIME_CNT_8822C)\n#define BIT_CLEAR_BT_TIME_CNT_8822C(x) ((x) & (~BITS_BT_TIME_CNT_8822C))\n#define BIT_GET_BT_TIME_CNT_8822C(x)                                           \\\n\t(((x) >> BIT_SHIFT_BT_TIME_CNT_8822C) & BIT_MASK_BT_TIME_CNT_8822C)\n#define BIT_SET_BT_TIME_CNT_8822C(x, v)                                        \\\n\t(BIT_CLEAR_BT_TIME_CNT_8822C(x) | BIT_BT_TIME_CNT_8822C(v))\n\n/* 2 REG_RTS_ADDRESS_0_8822C */\n\n/* 2 REG_RTS_ADDRESS_0_1_8822C */\n\n/* 2 REG_RTS_ADDRESS_1_8822C */\n\n/* 2 REG_RTS_ADDRESS_1_1_8822C */\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822C */\n#define BIT_LTECOEX_ACCESS_START_V1_8822C BIT(31)\n#define BIT_LTECOEX_WRITE_MODE_V1_8822C BIT(30)\n#define BIT_LTECOEX_READY_BIT_V1_8822C BIT(29)\n\n#define BIT_SHIFT_WRITE_BYTE_EN_V1_8822C 16\n#define BIT_MASK_WRITE_BYTE_EN_V1_8822C 0xf\n#define BIT_WRITE_BYTE_EN_V1_8822C(x)                                          \\\n\t(((x) & BIT_MASK_WRITE_BYTE_EN_V1_8822C)                               \\\n\t << BIT_SHIFT_WRITE_BYTE_EN_V1_8822C)\n#define BITS_WRITE_BYTE_EN_V1_8822C                                            \\\n\t(BIT_MASK_WRITE_BYTE_EN_V1_8822C << BIT_SHIFT_WRITE_BYTE_EN_V1_8822C)\n#define BIT_CLEAR_WRITE_BYTE_EN_V1_8822C(x)                                    \\\n\t((x) & (~BITS_WRITE_BYTE_EN_V1_8822C))\n#define BIT_GET_WRITE_BYTE_EN_V1_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8822C) &                           \\\n\t BIT_MASK_WRITE_BYTE_EN_V1_8822C)\n#define BIT_SET_WRITE_BYTE_EN_V1_8822C(x, v)                                   \\\n\t(BIT_CLEAR_WRITE_BYTE_EN_V1_8822C(x) | BIT_WRITE_BYTE_EN_V1_8822C(v))\n\n#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C 0\n#define BIT_MASK_LTECOEX_REG_ADDR_V1_8822C 0xffff\n#define BIT_LTECOEX_REG_ADDR_V1_8822C(x)                                       \\\n\t(((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822C)                            \\\n\t << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C)\n#define BITS_LTECOEX_REG_ADDR_V1_8822C                                         \\\n\t(BIT_MASK_LTECOEX_REG_ADDR_V1_8822C                                    \\\n\t << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C)\n#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822C(x)                                 \\\n\t((x) & (~BITS_LTECOEX_REG_ADDR_V1_8822C))\n#define BIT_GET_LTECOEX_REG_ADDR_V1_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C) &                        \\\n\t BIT_MASK_LTECOEX_REG_ADDR_V1_8822C)\n#define BIT_SET_LTECOEX_REG_ADDR_V1_8822C(x, v)                                \\\n\t(BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822C(x) |                              \\\n\t BIT_LTECOEX_REG_ADDR_V1_8822C(v))\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822C */\n\n#define BIT_SHIFT_LTECOEX_W_DATA_V1_8822C 0\n#define BIT_MASK_LTECOEX_W_DATA_V1_8822C 0xffffffffL\n#define BIT_LTECOEX_W_DATA_V1_8822C(x)                                         \\\n\t(((x) & BIT_MASK_LTECOEX_W_DATA_V1_8822C)                              \\\n\t << BIT_SHIFT_LTECOEX_W_DATA_V1_8822C)\n#define BITS_LTECOEX_W_DATA_V1_8822C                                           \\\n\t(BIT_MASK_LTECOEX_W_DATA_V1_8822C << BIT_SHIFT_LTECOEX_W_DATA_V1_8822C)\n#define BIT_CLEAR_LTECOEX_W_DATA_V1_8822C(x)                                   \\\n\t((x) & (~BITS_LTECOEX_W_DATA_V1_8822C))\n#define BIT_GET_LTECOEX_W_DATA_V1_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8822C) &                          \\\n\t BIT_MASK_LTECOEX_W_DATA_V1_8822C)\n#define BIT_SET_LTECOEX_W_DATA_V1_8822C(x, v)                                  \\\n\t(BIT_CLEAR_LTECOEX_W_DATA_V1_8822C(x) | BIT_LTECOEX_W_DATA_V1_8822C(v))\n\n/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822C */\n\n#define BIT_SHIFT_LTECOEX_R_DATA_V1_8822C 0\n#define BIT_MASK_LTECOEX_R_DATA_V1_8822C 0xffffffffL\n#define BIT_LTECOEX_R_DATA_V1_8822C(x)                                         \\\n\t(((x) & BIT_MASK_LTECOEX_R_DATA_V1_8822C)                              \\\n\t << BIT_SHIFT_LTECOEX_R_DATA_V1_8822C)\n#define BITS_LTECOEX_R_DATA_V1_8822C                                           \\\n\t(BIT_MASK_LTECOEX_R_DATA_V1_8822C << BIT_SHIFT_LTECOEX_R_DATA_V1_8822C)\n#define BIT_CLEAR_LTECOEX_R_DATA_V1_8822C(x)                                   \\\n\t((x) & (~BITS_LTECOEX_R_DATA_V1_8822C))\n#define BIT_GET_LTECOEX_R_DATA_V1_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8822C) &                          \\\n\t BIT_MASK_LTECOEX_R_DATA_V1_8822C)\n#define BIT_SET_LTECOEX_R_DATA_V1_8822C(x, v)                                  \\\n\t(BIT_CLEAR_LTECOEX_R_DATA_V1_8822C(x) | BIT_LTECOEX_R_DATA_V1_8822C(v))\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_NOT_VALID_8822C */\n\n/* 2 REG_SDIO_TX_CTRL_8822C */\n\n#define BIT_SHIFT_SDIO_INT_TIMEOUT_8822C 16\n#define BIT_MASK_SDIO_INT_TIMEOUT_8822C 0xffff\n#define BIT_SDIO_INT_TIMEOUT_8822C(x)                                          \\\n\t(((x) & BIT_MASK_SDIO_INT_TIMEOUT_8822C)                               \\\n\t << BIT_SHIFT_SDIO_INT_TIMEOUT_8822C)\n#define BITS_SDIO_INT_TIMEOUT_8822C                                            \\\n\t(BIT_MASK_SDIO_INT_TIMEOUT_8822C << BIT_SHIFT_SDIO_INT_TIMEOUT_8822C)\n#define BIT_CLEAR_SDIO_INT_TIMEOUT_8822C(x)                                    \\\n\t((x) & (~BITS_SDIO_INT_TIMEOUT_8822C))\n#define BIT_GET_SDIO_INT_TIMEOUT_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8822C) &                           \\\n\t BIT_MASK_SDIO_INT_TIMEOUT_8822C)\n#define BIT_SET_SDIO_INT_TIMEOUT_8822C(x, v)                                   \\\n\t(BIT_CLEAR_SDIO_INT_TIMEOUT_8822C(x) | BIT_SDIO_INT_TIMEOUT_8822C(v))\n\n#define BIT_IO_ERR_STATUS_8822C BIT(15)\n#define BIT_CMD53_W_MIX_8822C BIT(14)\n#define BIT_CMD53_TX_FORMAT_8822C BIT(13)\n#define BIT_CMD53_R_TIMEOUT_MASK_8822C BIT(12)\n\n#define BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C 10\n#define BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C 0x3\n#define BIT_CMD53_R_TIMEOUT_UNIT_8822C(x)                                      \\\n\t(((x) & BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C)                           \\\n\t << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C)\n#define BITS_CMD53_R_TIMEOUT_UNIT_8822C                                        \\\n\t(BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C                                   \\\n\t << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C)\n#define BIT_CLEAR_CMD53_R_TIMEOUT_UNIT_8822C(x)                                \\\n\t((x) & (~BITS_CMD53_R_TIMEOUT_UNIT_8822C))\n#define BIT_GET_CMD53_R_TIMEOUT_UNIT_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C) &                       \\\n\t BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C)\n#define BIT_SET_CMD53_R_TIMEOUT_UNIT_8822C(x, v)                               \\\n\t(BIT_CLEAR_CMD53_R_TIMEOUT_UNIT_8822C(x) |                             \\\n\t BIT_CMD53_R_TIMEOUT_UNIT_8822C(v))\n\n#define BIT_REPLY_ERRCRC_IN_DATA_8822C BIT(9)\n#define BIT_EN_CMD53_OVERLAP_8822C BIT(8)\n#define BIT_REPLY_ERR_IN_R5_8822C BIT(7)\n#define BIT_R18A_EN_8822C BIT(6)\n#define BIT_SDIO_CMD_FORCE_VLD_8822C BIT(5)\n#define BIT_INIT_CMD_EN_8822C BIT(4)\n#define BIT_RXINT_READ_MASK_DIS_8822C BIT(3)\n#define BIT_EN_RXDMA_MASK_INT_8822C BIT(2)\n#define BIT_EN_MASK_TIMER_8822C BIT(1)\n#define BIT_CMD_ERR_STOP_INT_EN_8822C BIT(0)\n\n/* 2 REG_SDIO_CMD11_VOL_SWITCH_8822C */\n\n#define BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C 4\n#define BIT_MASK_CMD11_SEQ_END_DELAY_8822C 0xf\n#define BIT_CMD11_SEQ_END_DELAY_8822C(x)                                       \\\n\t(((x) & BIT_MASK_CMD11_SEQ_END_DELAY_8822C)                            \\\n\t << BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C)\n#define BITS_CMD11_SEQ_END_DELAY_8822C                                         \\\n\t(BIT_MASK_CMD11_SEQ_END_DELAY_8822C                                    \\\n\t << BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C)\n#define BIT_CLEAR_CMD11_SEQ_END_DELAY_8822C(x)                                 \\\n\t((x) & (~BITS_CMD11_SEQ_END_DELAY_8822C))\n#define BIT_GET_CMD11_SEQ_END_DELAY_8822C(x)                                   \\\n\t(((x) >> BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C) &                        \\\n\t BIT_MASK_CMD11_SEQ_END_DELAY_8822C)\n#define BIT_SET_CMD11_SEQ_END_DELAY_8822C(x, v)                                \\\n\t(BIT_CLEAR_CMD11_SEQ_END_DELAY_8822C(x) |                              \\\n\t BIT_CMD11_SEQ_END_DELAY_8822C(v))\n\n#define BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C 1\n#define BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C 0x7\n#define BIT_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x)                                 \\\n\t(((x) & BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C)                      \\\n\t << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C)\n#define BITS_CMD11_SEQ_SAMPLE_INTERVAL_8822C                                   \\\n\t(BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C                              \\\n\t << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C)\n#define BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x)                           \\\n\t((x) & (~BITS_CMD11_SEQ_SAMPLE_INTERVAL_8822C))\n#define BIT_GET_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x)                             \\\n\t(((x) >> BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C) &                  \\\n\t BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C)\n#define BIT_SET_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x, v)                          \\\n\t(BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x) |                        \\\n\t BIT_CMD11_SEQ_SAMPLE_INTERVAL_8822C(v))\n\n#define BIT_CMD11_SEQ_EN_8822C BIT(0)\n\n/* 2 REG_SDIO_CTRL_8822C */\n#define BIT_SIG_OUT_PH_8822C BIT(0)\n\n/* 2 REG_SDIO_DRIVING_8822C */\n\n#define BIT_SHIFT_SDIO_DRV_TYPE_D_8822C 12\n#define BIT_MASK_SDIO_DRV_TYPE_D_8822C 0xf\n#define BIT_SDIO_DRV_TYPE_D_8822C(x)                                           \\\n\t(((x) & BIT_MASK_SDIO_DRV_TYPE_D_8822C)                                \\\n\t << BIT_SHIFT_SDIO_DRV_TYPE_D_8822C)\n#define BITS_SDIO_DRV_TYPE_D_8822C                                             \\\n\t(BIT_MASK_SDIO_DRV_TYPE_D_8822C << BIT_SHIFT_SDIO_DRV_TYPE_D_8822C)\n#define BIT_CLEAR_SDIO_DRV_TYPE_D_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_D_8822C))\n#define BIT_GET_SDIO_DRV_TYPE_D_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_D_8822C) &                            \\\n\t BIT_MASK_SDIO_DRV_TYPE_D_8822C)\n#define BIT_SET_SDIO_DRV_TYPE_D_8822C(x, v)                                    \\\n\t(BIT_CLEAR_SDIO_DRV_TYPE_D_8822C(x) | BIT_SDIO_DRV_TYPE_D_8822C(v))\n\n#define BIT_SHIFT_SDIO_DRV_TYPE_C_8822C 8\n#define BIT_MASK_SDIO_DRV_TYPE_C_8822C 0xf\n#define BIT_SDIO_DRV_TYPE_C_8822C(x)                                           \\\n\t(((x) & BIT_MASK_SDIO_DRV_TYPE_C_8822C)                                \\\n\t << BIT_SHIFT_SDIO_DRV_TYPE_C_8822C)\n#define BITS_SDIO_DRV_TYPE_C_8822C                                             \\\n\t(BIT_MASK_SDIO_DRV_TYPE_C_8822C << BIT_SHIFT_SDIO_DRV_TYPE_C_8822C)\n#define BIT_CLEAR_SDIO_DRV_TYPE_C_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_C_8822C))\n#define BIT_GET_SDIO_DRV_TYPE_C_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_C_8822C) &                            \\\n\t BIT_MASK_SDIO_DRV_TYPE_C_8822C)\n#define BIT_SET_SDIO_DRV_TYPE_C_8822C(x, v)                                    \\\n\t(BIT_CLEAR_SDIO_DRV_TYPE_C_8822C(x) | BIT_SDIO_DRV_TYPE_C_8822C(v))\n\n#define BIT_SHIFT_SDIO_DRV_TYPE_B_8822C 4\n#define BIT_MASK_SDIO_DRV_TYPE_B_8822C 0xf\n#define BIT_SDIO_DRV_TYPE_B_8822C(x)                                           \\\n\t(((x) & BIT_MASK_SDIO_DRV_TYPE_B_8822C)                                \\\n\t << BIT_SHIFT_SDIO_DRV_TYPE_B_8822C)\n#define BITS_SDIO_DRV_TYPE_B_8822C                                             \\\n\t(BIT_MASK_SDIO_DRV_TYPE_B_8822C << BIT_SHIFT_SDIO_DRV_TYPE_B_8822C)\n#define BIT_CLEAR_SDIO_DRV_TYPE_B_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_B_8822C))\n#define BIT_GET_SDIO_DRV_TYPE_B_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_B_8822C) &                            \\\n\t BIT_MASK_SDIO_DRV_TYPE_B_8822C)\n#define BIT_SET_SDIO_DRV_TYPE_B_8822C(x, v)                                    \\\n\t(BIT_CLEAR_SDIO_DRV_TYPE_B_8822C(x) | BIT_SDIO_DRV_TYPE_B_8822C(v))\n\n#define BIT_SHIFT_SDIO_DRV_TYPE_A_8822C 0\n#define BIT_MASK_SDIO_DRV_TYPE_A_8822C 0xf\n#define BIT_SDIO_DRV_TYPE_A_8822C(x)                                           \\\n\t(((x) & BIT_MASK_SDIO_DRV_TYPE_A_8822C)                                \\\n\t << BIT_SHIFT_SDIO_DRV_TYPE_A_8822C)\n#define BITS_SDIO_DRV_TYPE_A_8822C                                             \\\n\t(BIT_MASK_SDIO_DRV_TYPE_A_8822C << BIT_SHIFT_SDIO_DRV_TYPE_A_8822C)\n#define BIT_CLEAR_SDIO_DRV_TYPE_A_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_A_8822C))\n#define BIT_GET_SDIO_DRV_TYPE_A_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_A_8822C) &                            \\\n\t BIT_MASK_SDIO_DRV_TYPE_A_8822C)\n#define BIT_SET_SDIO_DRV_TYPE_A_8822C(x, v)                                    \\\n\t(BIT_CLEAR_SDIO_DRV_TYPE_A_8822C(x) | BIT_SDIO_DRV_TYPE_A_8822C(v))\n\n/* 2 REG_SDIO_MONITOR_8822C */\n\n#define BIT_SHIFT_SDIO_INT_START_8822C 0\n#define BIT_MASK_SDIO_INT_START_8822C 0xffffffffL\n#define BIT_SDIO_INT_START_8822C(x)                                            \\\n\t(((x) & BIT_MASK_SDIO_INT_START_8822C)                                 \\\n\t << BIT_SHIFT_SDIO_INT_START_8822C)\n#define BITS_SDIO_INT_START_8822C                                              \\\n\t(BIT_MASK_SDIO_INT_START_8822C << BIT_SHIFT_SDIO_INT_START_8822C)\n#define BIT_CLEAR_SDIO_INT_START_8822C(x) ((x) & (~BITS_SDIO_INT_START_8822C))\n#define BIT_GET_SDIO_INT_START_8822C(x)                                        \\\n\t(((x) >> BIT_SHIFT_SDIO_INT_START_8822C) &                             \\\n\t BIT_MASK_SDIO_INT_START_8822C)\n#define BIT_SET_SDIO_INT_START_8822C(x, v)                                     \\\n\t(BIT_CLEAR_SDIO_INT_START_8822C(x) | BIT_SDIO_INT_START_8822C(v))\n\n/* 2 REG_SDIO_MONITOR_2_8822C */\n#define BIT_CMD53_WT_EN_8822C BIT(23)\n\n#define BIT_SHIFT_SDIO_CLK_MONITOR_8822C 21\n#define BIT_MASK_SDIO_CLK_MONITOR_8822C 0x3\n#define BIT_SDIO_CLK_MONITOR_8822C(x)                                          \\\n\t(((x) & BIT_MASK_SDIO_CLK_MONITOR_8822C)                               \\\n\t << BIT_SHIFT_SDIO_CLK_MONITOR_8822C)\n#define BITS_SDIO_CLK_MONITOR_8822C                                            \\\n\t(BIT_MASK_SDIO_CLK_MONITOR_8822C << BIT_SHIFT_SDIO_CLK_MONITOR_8822C)\n#define BIT_CLEAR_SDIO_CLK_MONITOR_8822C(x)                                    \\\n\t((x) & (~BITS_SDIO_CLK_MONITOR_8822C))\n#define BIT_GET_SDIO_CLK_MONITOR_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_SDIO_CLK_MONITOR_8822C) &                           \\\n\t BIT_MASK_SDIO_CLK_MONITOR_8822C)\n#define BIT_SET_SDIO_CLK_MONITOR_8822C(x, v)                                   \\\n\t(BIT_CLEAR_SDIO_CLK_MONITOR_8822C(x) | BIT_SDIO_CLK_MONITOR_8822C(v))\n\n#define BIT_SHIFT_SDIO_CLK_CNT_8822C 0\n#define BIT_MASK_SDIO_CLK_CNT_8822C 0x1fffff\n#define BIT_SDIO_CLK_CNT_8822C(x)                                              \\\n\t(((x) & BIT_MASK_SDIO_CLK_CNT_8822C) << BIT_SHIFT_SDIO_CLK_CNT_8822C)\n#define BITS_SDIO_CLK_CNT_8822C                                                \\\n\t(BIT_MASK_SDIO_CLK_CNT_8822C << BIT_SHIFT_SDIO_CLK_CNT_8822C)\n#define BIT_CLEAR_SDIO_CLK_CNT_8822C(x) ((x) & (~BITS_SDIO_CLK_CNT_8822C))\n#define BIT_GET_SDIO_CLK_CNT_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_SDIO_CLK_CNT_8822C) & BIT_MASK_SDIO_CLK_CNT_8822C)\n#define BIT_SET_SDIO_CLK_CNT_8822C(x, v)                                       \\\n\t(BIT_CLEAR_SDIO_CLK_CNT_8822C(x) | BIT_SDIO_CLK_CNT_8822C(v))\n\n/* 2 REG_SDIO_HIMR_8822C */\n#define BIT_SDIO_CRCERR_MSK_8822C BIT(31)\n#define BIT_SDIO_HSISR3_IND_MSK_8822C BIT(30)\n#define BIT_SDIO_HSISR2_IND_MSK_8822C BIT(29)\n#define BIT_SDIO_HEISR_IND_MSK_8822C BIT(28)\n#define BIT_SDIO_CTWEND_MSK_8822C BIT(27)\n#define BIT_SDIO_ATIMEND_E_MSK_8822C BIT(26)\n#define BIT_SDIIO_ATIMEND_MSK_8822C BIT(25)\n#define BIT_SDIO_OCPINT_MSK_8822C BIT(24)\n#define BIT_SDIO_PSTIMEOUT_MSK_8822C BIT(23)\n#define BIT_SDIO_GTINT4_MSK_8822C BIT(22)\n#define BIT_SDIO_GTINT3_MSK_8822C BIT(21)\n#define BIT_SDIO_HSISR_IND_MSK_8822C BIT(20)\n#define BIT_SDIO_CPWM2_MSK_8822C BIT(19)\n#define BIT_SDIO_CPWM1_MSK_8822C BIT(18)\n#define BIT_SDIO_C2HCMD_INT_MSK_8822C BIT(17)\n#define BIT_SDIO_BCNERLY_INT_MSK_8822C BIT(16)\n#define BIT_SDIO_TXBCNERR_MSK_8822C BIT(7)\n#define BIT_SDIO_TXBCNOK_MSK_8822C BIT(6)\n#define BIT_SDIO_RXFOVW_MSK_8822C BIT(5)\n#define BIT_SDIO_TXFOVW_MSK_8822C BIT(4)\n#define BIT_SDIO_RXERR_MSK_8822C BIT(3)\n#define BIT_SDIO_TXERR_MSK_8822C BIT(2)\n#define BIT_SDIO_AVAL_MSK_8822C BIT(1)\n#define BIT_RX_REQUEST_MSK_8822C BIT(0)\n\n/* 2 REG_SDIO_HISR_8822C */\n#define BIT_SDIO_CRCERR_8822C BIT(31)\n#define BIT_SDIO_HSISR3_IND_8822C BIT(30)\n#define BIT_SDIO_HSISR2_IND_8822C BIT(29)\n#define BIT_SDIO_HEISR_IND_8822C BIT(28)\n#define BIT_SDIO_CTWEND_8822C BIT(27)\n#define BIT_SDIO_ATIMEND_E_8822C BIT(26)\n#define BIT_SDIO_ATIMEND_8822C BIT(25)\n#define BIT_SDIO_OCPINT_8822C BIT(24)\n#define BIT_SDIO_PSTIMEOUT_8822C BIT(23)\n#define BIT_SDIO_GTINT4_8822C BIT(22)\n#define BIT_SDIO_GTINT3_8822C BIT(21)\n#define BIT_SDIO_HSISR_IND_8822C BIT(20)\n#define BIT_SDIO_CPWM2_8822C BIT(19)\n#define BIT_SDIO_CPWM1_8822C BIT(18)\n#define BIT_SDIO_C2HCMD_INT_8822C BIT(17)\n#define BIT_SDIO_BCNERLY_INT_8822C BIT(16)\n#define BIT_SDIO_TXBCNERR_8822C BIT(7)\n#define BIT_SDIO_TXBCNOK_8822C BIT(6)\n#define BIT_SDIO_RXFOVW_8822C BIT(5)\n#define BIT_SDIO_TXFOVW_8822C BIT(4)\n#define BIT_SDIO_RXERR_8822C BIT(3)\n#define BIT_SDIO_TXERR_8822C BIT(2)\n#define BIT_SDIO_AVAL_8822C BIT(1)\n#define BIT_RX_REQUEST_8822C BIT(0)\n\n/* 2 REG_SDIO_RX_REQ_LEN_8822C */\n\n#define BIT_SHIFT_RX_REQ_LEN_V1_8822C 0\n#define BIT_MASK_RX_REQ_LEN_V1_8822C 0x3ffff\n#define BIT_RX_REQ_LEN_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_RX_REQ_LEN_V1_8822C) << BIT_SHIFT_RX_REQ_LEN_V1_8822C)\n#define BITS_RX_REQ_LEN_V1_8822C                                               \\\n\t(BIT_MASK_RX_REQ_LEN_V1_8822C << BIT_SHIFT_RX_REQ_LEN_V1_8822C)\n#define BIT_CLEAR_RX_REQ_LEN_V1_8822C(x) ((x) & (~BITS_RX_REQ_LEN_V1_8822C))\n#define BIT_GET_RX_REQ_LEN_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8822C) & BIT_MASK_RX_REQ_LEN_V1_8822C)\n#define BIT_SET_RX_REQ_LEN_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_RX_REQ_LEN_V1_8822C(x) | BIT_RX_REQ_LEN_V1_8822C(v))\n\n/* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8822C */\n\n#define BIT_SHIFT_FREE_TXPG_SEQ_8822C 0\n#define BIT_MASK_FREE_TXPG_SEQ_8822C 0xff\n#define BIT_FREE_TXPG_SEQ_8822C(x)                                             \\\n\t(((x) & BIT_MASK_FREE_TXPG_SEQ_8822C) << BIT_SHIFT_FREE_TXPG_SEQ_8822C)\n#define BITS_FREE_TXPG_SEQ_8822C                                               \\\n\t(BIT_MASK_FREE_TXPG_SEQ_8822C << BIT_SHIFT_FREE_TXPG_SEQ_8822C)\n#define BIT_CLEAR_FREE_TXPG_SEQ_8822C(x) ((x) & (~BITS_FREE_TXPG_SEQ_8822C))\n#define BIT_GET_FREE_TXPG_SEQ_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8822C) & BIT_MASK_FREE_TXPG_SEQ_8822C)\n#define BIT_SET_FREE_TXPG_SEQ_8822C(x, v)                                      \\\n\t(BIT_CLEAR_FREE_TXPG_SEQ_8822C(x) | BIT_FREE_TXPG_SEQ_8822C(v))\n\n/* 2 REG_SDIO_FREE_TXPG_8822C */\n\n#define BIT_SHIFT_MID_FREEPG_V1_8822C 16\n#define BIT_MASK_MID_FREEPG_V1_8822C 0xfff\n#define BIT_MID_FREEPG_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_MID_FREEPG_V1_8822C) << BIT_SHIFT_MID_FREEPG_V1_8822C)\n#define BITS_MID_FREEPG_V1_8822C                                               \\\n\t(BIT_MASK_MID_FREEPG_V1_8822C << BIT_SHIFT_MID_FREEPG_V1_8822C)\n#define BIT_CLEAR_MID_FREEPG_V1_8822C(x) ((x) & (~BITS_MID_FREEPG_V1_8822C))\n#define BIT_GET_MID_FREEPG_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_MID_FREEPG_V1_8822C) & BIT_MASK_MID_FREEPG_V1_8822C)\n#define BIT_SET_MID_FREEPG_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_MID_FREEPG_V1_8822C(x) | BIT_MID_FREEPG_V1_8822C(v))\n\n#define BIT_SHIFT_HIQ_FREEPG_V1_8822C 0\n#define BIT_MASK_HIQ_FREEPG_V1_8822C 0xfff\n#define BIT_HIQ_FREEPG_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_HIQ_FREEPG_V1_8822C) << BIT_SHIFT_HIQ_FREEPG_V1_8822C)\n#define BITS_HIQ_FREEPG_V1_8822C                                               \\\n\t(BIT_MASK_HIQ_FREEPG_V1_8822C << BIT_SHIFT_HIQ_FREEPG_V1_8822C)\n#define BIT_CLEAR_HIQ_FREEPG_V1_8822C(x) ((x) & (~BITS_HIQ_FREEPG_V1_8822C))\n#define BIT_GET_HIQ_FREEPG_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8822C) & BIT_MASK_HIQ_FREEPG_V1_8822C)\n#define BIT_SET_HIQ_FREEPG_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_HIQ_FREEPG_V1_8822C(x) | BIT_HIQ_FREEPG_V1_8822C(v))\n\n/* 2 REG_SDIO_FREE_TXPG2_8822C */\n\n#define BIT_SHIFT_PUB_FREEPG_V1_8822C 16\n#define BIT_MASK_PUB_FREEPG_V1_8822C 0xfff\n#define BIT_PUB_FREEPG_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_PUB_FREEPG_V1_8822C) << BIT_SHIFT_PUB_FREEPG_V1_8822C)\n#define BITS_PUB_FREEPG_V1_8822C                                               \\\n\t(BIT_MASK_PUB_FREEPG_V1_8822C << BIT_SHIFT_PUB_FREEPG_V1_8822C)\n#define BIT_CLEAR_PUB_FREEPG_V1_8822C(x) ((x) & (~BITS_PUB_FREEPG_V1_8822C))\n#define BIT_GET_PUB_FREEPG_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_PUB_FREEPG_V1_8822C) & BIT_MASK_PUB_FREEPG_V1_8822C)\n#define BIT_SET_PUB_FREEPG_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_PUB_FREEPG_V1_8822C(x) | BIT_PUB_FREEPG_V1_8822C(v))\n\n#define BIT_SHIFT_LOW_FREEPG_V1_8822C 0\n#define BIT_MASK_LOW_FREEPG_V1_8822C 0xfff\n#define BIT_LOW_FREEPG_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_LOW_FREEPG_V1_8822C) << BIT_SHIFT_LOW_FREEPG_V1_8822C)\n#define BITS_LOW_FREEPG_V1_8822C                                               \\\n\t(BIT_MASK_LOW_FREEPG_V1_8822C << BIT_SHIFT_LOW_FREEPG_V1_8822C)\n#define BIT_CLEAR_LOW_FREEPG_V1_8822C(x) ((x) & (~BITS_LOW_FREEPG_V1_8822C))\n#define BIT_GET_LOW_FREEPG_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_LOW_FREEPG_V1_8822C) & BIT_MASK_LOW_FREEPG_V1_8822C)\n#define BIT_SET_LOW_FREEPG_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_LOW_FREEPG_V1_8822C(x) | BIT_LOW_FREEPG_V1_8822C(v))\n\n/* 2 REG_SDIO_OQT_FREE_TXPG_V1_8822C */\n\n#define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C 24\n#define BIT_MASK_NOAC_OQT_FREEPG_V1_8822C 0xff\n#define BIT_NOAC_OQT_FREEPG_V1_8822C(x)                                        \\\n\t(((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822C)                             \\\n\t << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C)\n#define BITS_NOAC_OQT_FREEPG_V1_8822C                                          \\\n\t(BIT_MASK_NOAC_OQT_FREEPG_V1_8822C                                     \\\n\t << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C)\n#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822C(x)                                  \\\n\t((x) & (~BITS_NOAC_OQT_FREEPG_V1_8822C))\n#define BIT_GET_NOAC_OQT_FREEPG_V1_8822C(x)                                    \\\n\t(((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C) &                         \\\n\t BIT_MASK_NOAC_OQT_FREEPG_V1_8822C)\n#define BIT_SET_NOAC_OQT_FREEPG_V1_8822C(x, v)                                 \\\n\t(BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822C(x) |                               \\\n\t BIT_NOAC_OQT_FREEPG_V1_8822C(v))\n\n#define BIT_SHIFT_AC_OQT_FREEPG_V1_8822C 16\n#define BIT_MASK_AC_OQT_FREEPG_V1_8822C 0xff\n#define BIT_AC_OQT_FREEPG_V1_8822C(x)                                          \\\n\t(((x) & BIT_MASK_AC_OQT_FREEPG_V1_8822C)                               \\\n\t << BIT_SHIFT_AC_OQT_FREEPG_V1_8822C)\n#define BITS_AC_OQT_FREEPG_V1_8822C                                            \\\n\t(BIT_MASK_AC_OQT_FREEPG_V1_8822C << BIT_SHIFT_AC_OQT_FREEPG_V1_8822C)\n#define BIT_CLEAR_AC_OQT_FREEPG_V1_8822C(x)                                    \\\n\t((x) & (~BITS_AC_OQT_FREEPG_V1_8822C))\n#define BIT_GET_AC_OQT_FREEPG_V1_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8822C) &                           \\\n\t BIT_MASK_AC_OQT_FREEPG_V1_8822C)\n#define BIT_SET_AC_OQT_FREEPG_V1_8822C(x, v)                                   \\\n\t(BIT_CLEAR_AC_OQT_FREEPG_V1_8822C(x) | BIT_AC_OQT_FREEPG_V1_8822C(v))\n\n#define BIT_SHIFT_EXQ_FREEPG_V1_8822C 0\n#define BIT_MASK_EXQ_FREEPG_V1_8822C 0xfff\n#define BIT_EXQ_FREEPG_V1_8822C(x)                                             \\\n\t(((x) & BIT_MASK_EXQ_FREEPG_V1_8822C) << BIT_SHIFT_EXQ_FREEPG_V1_8822C)\n#define BITS_EXQ_FREEPG_V1_8822C                                               \\\n\t(BIT_MASK_EXQ_FREEPG_V1_8822C << BIT_SHIFT_EXQ_FREEPG_V1_8822C)\n#define BIT_CLEAR_EXQ_FREEPG_V1_8822C(x) ((x) & (~BITS_EXQ_FREEPG_V1_8822C))\n#define BIT_GET_EXQ_FREEPG_V1_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8822C) & BIT_MASK_EXQ_FREEPG_V1_8822C)\n#define BIT_SET_EXQ_FREEPG_V1_8822C(x, v)                                      \\\n\t(BIT_CLEAR_EXQ_FREEPG_V1_8822C(x) | BIT_EXQ_FREEPG_V1_8822C(v))\n\n/* 2 REG_SDIO_TXPKT_EMPTY_8822C */\n#define BIT_SDIO_BCNQ_EMPTY_8822C BIT(11)\n#define BIT_SDIO_HQQ_EMPTY_8822C BIT(10)\n#define BIT_SDIO_MQQ_EMPTY_8822C BIT(9)\n#define BIT_SDIO_MGQ_CPU_EMPTY_8822C BIT(8)\n#define BIT_SDIO_AC7Q_EMPTY_8822C BIT(7)\n#define BIT_SDIO_AC6Q_EMPTY_8822C BIT(6)\n#define BIT_SDIO_AC5Q_EMPTY_8822C BIT(5)\n#define BIT_SDIO_AC4Q_EMPTY_8822C BIT(4)\n#define BIT_SDIO_AC3Q_EMPTY_8822C BIT(3)\n#define BIT_SDIO_AC2Q_EMPTY_8822C BIT(2)\n#define BIT_SDIO_AC1Q_EMPTY_8822C BIT(1)\n#define BIT_SDIO_AC0Q_EMPTY_8822C BIT(0)\n\n/* 2 REG_SDIO_HTSFR_INFO_8822C */\n\n#define BIT_SHIFT_HTSFR1_8822C 16\n#define BIT_MASK_HTSFR1_8822C 0xffff\n#define BIT_HTSFR1_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_HTSFR1_8822C) << BIT_SHIFT_HTSFR1_8822C)\n#define BITS_HTSFR1_8822C (BIT_MASK_HTSFR1_8822C << BIT_SHIFT_HTSFR1_8822C)\n#define BIT_CLEAR_HTSFR1_8822C(x) ((x) & (~BITS_HTSFR1_8822C))\n#define BIT_GET_HTSFR1_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_HTSFR1_8822C) & BIT_MASK_HTSFR1_8822C)\n#define BIT_SET_HTSFR1_8822C(x, v)                                             \\\n\t(BIT_CLEAR_HTSFR1_8822C(x) | BIT_HTSFR1_8822C(v))\n\n#define BIT_SHIFT_HTSFR0_8822C 0\n#define BIT_MASK_HTSFR0_8822C 0xffff\n#define BIT_HTSFR0_8822C(x)                                                    \\\n\t(((x) & BIT_MASK_HTSFR0_8822C) << BIT_SHIFT_HTSFR0_8822C)\n#define BITS_HTSFR0_8822C (BIT_MASK_HTSFR0_8822C << BIT_SHIFT_HTSFR0_8822C)\n#define BIT_CLEAR_HTSFR0_8822C(x) ((x) & (~BITS_HTSFR0_8822C))\n#define BIT_GET_HTSFR0_8822C(x)                                                \\\n\t(((x) >> BIT_SHIFT_HTSFR0_8822C) & BIT_MASK_HTSFR0_8822C)\n#define BIT_SET_HTSFR0_8822C(x, v)                                             \\\n\t(BIT_CLEAR_HTSFR0_8822C(x) | BIT_HTSFR0_8822C(v))\n\n/* 2 REG_SDIO_HCPWM1_V2_8822C */\n#define BIT_TOGGLE_8822C BIT(7)\n#define BIT_CUR_PS_8822C BIT(0)\n\n/* 2 REG_SDIO_HCPWM2_V2_8822C */\n\n/* 2 REG_SDIO_INDIRECT_REG_CFG_8822C */\n#define BIT_INDIRECT_REG_RDY_8822C BIT(20)\n#define BIT_INDIRECT_REG_R_8822C BIT(19)\n#define BIT_INDIRECT_REG_W_8822C BIT(18)\n\n#define BIT_SHIFT_INDIRECT_REG_SIZE_8822C 16\n#define BIT_MASK_INDIRECT_REG_SIZE_8822C 0x3\n#define BIT_INDIRECT_REG_SIZE_8822C(x)                                         \\\n\t(((x) & BIT_MASK_INDIRECT_REG_SIZE_8822C)                              \\\n\t << BIT_SHIFT_INDIRECT_REG_SIZE_8822C)\n#define BITS_INDIRECT_REG_SIZE_8822C                                           \\\n\t(BIT_MASK_INDIRECT_REG_SIZE_8822C << BIT_SHIFT_INDIRECT_REG_SIZE_8822C)\n#define BIT_CLEAR_INDIRECT_REG_SIZE_8822C(x)                                   \\\n\t((x) & (~BITS_INDIRECT_REG_SIZE_8822C))\n#define BIT_GET_INDIRECT_REG_SIZE_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8822C) &                          \\\n\t BIT_MASK_INDIRECT_REG_SIZE_8822C)\n#define BIT_SET_INDIRECT_REG_SIZE_8822C(x, v)                                  \\\n\t(BIT_CLEAR_INDIRECT_REG_SIZE_8822C(x) | BIT_INDIRECT_REG_SIZE_8822C(v))\n\n#define BIT_SHIFT_INDIRECT_REG_ADDR_8822C 0\n#define BIT_MASK_INDIRECT_REG_ADDR_8822C 0xffff\n#define BIT_INDIRECT_REG_ADDR_8822C(x)                                         \\\n\t(((x) & BIT_MASK_INDIRECT_REG_ADDR_8822C)                              \\\n\t << BIT_SHIFT_INDIRECT_REG_ADDR_8822C)\n#define BITS_INDIRECT_REG_ADDR_8822C                                           \\\n\t(BIT_MASK_INDIRECT_REG_ADDR_8822C << BIT_SHIFT_INDIRECT_REG_ADDR_8822C)\n#define BIT_CLEAR_INDIRECT_REG_ADDR_8822C(x)                                   \\\n\t((x) & (~BITS_INDIRECT_REG_ADDR_8822C))\n#define BIT_GET_INDIRECT_REG_ADDR_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8822C) &                          \\\n\t BIT_MASK_INDIRECT_REG_ADDR_8822C)\n#define BIT_SET_INDIRECT_REG_ADDR_8822C(x, v)                                  \\\n\t(BIT_CLEAR_INDIRECT_REG_ADDR_8822C(x) | BIT_INDIRECT_REG_ADDR_8822C(v))\n\n/* 2 REG_SDIO_INDIRECT_REG_DATA_8822C */\n\n#define BIT_SHIFT_INDIRECT_REG_DATA_8822C 0\n#define BIT_MASK_INDIRECT_REG_DATA_8822C 0xffffffffL\n#define BIT_INDIRECT_REG_DATA_8822C(x)                                         \\\n\t(((x) & BIT_MASK_INDIRECT_REG_DATA_8822C)                              \\\n\t << BIT_SHIFT_INDIRECT_REG_DATA_8822C)\n#define BITS_INDIRECT_REG_DATA_8822C                                           \\\n\t(BIT_MASK_INDIRECT_REG_DATA_8822C << BIT_SHIFT_INDIRECT_REG_DATA_8822C)\n#define BIT_CLEAR_INDIRECT_REG_DATA_8822C(x)                                   \\\n\t((x) & (~BITS_INDIRECT_REG_DATA_8822C))\n#define BIT_GET_INDIRECT_REG_DATA_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8822C) &                          \\\n\t BIT_MASK_INDIRECT_REG_DATA_8822C)\n#define BIT_SET_INDIRECT_REG_DATA_8822C(x, v)                                  \\\n\t(BIT_CLEAR_INDIRECT_REG_DATA_8822C(x) | BIT_INDIRECT_REG_DATA_8822C(v))\n\n/* 2 REG_SDIO_H2C_8822C */\n\n#define BIT_SHIFT_SDIO_H2C_MSG_8822C 0\n#define BIT_MASK_SDIO_H2C_MSG_8822C 0xffffffffL\n#define BIT_SDIO_H2C_MSG_8822C(x)                                              \\\n\t(((x) & BIT_MASK_SDIO_H2C_MSG_8822C) << BIT_SHIFT_SDIO_H2C_MSG_8822C)\n#define BITS_SDIO_H2C_MSG_8822C                                                \\\n\t(BIT_MASK_SDIO_H2C_MSG_8822C << BIT_SHIFT_SDIO_H2C_MSG_8822C)\n#define BIT_CLEAR_SDIO_H2C_MSG_8822C(x) ((x) & (~BITS_SDIO_H2C_MSG_8822C))\n#define BIT_GET_SDIO_H2C_MSG_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_SDIO_H2C_MSG_8822C) & BIT_MASK_SDIO_H2C_MSG_8822C)\n#define BIT_SET_SDIO_H2C_MSG_8822C(x, v)                                       \\\n\t(BIT_CLEAR_SDIO_H2C_MSG_8822C(x) | BIT_SDIO_H2C_MSG_8822C(v))\n\n/* 2 REG_SDIO_C2H_8822C */\n\n#define BIT_SHIFT_SDIO_C2H_MSG_8822C 0\n#define BIT_MASK_SDIO_C2H_MSG_8822C 0xffffffffL\n#define BIT_SDIO_C2H_MSG_8822C(x)                                              \\\n\t(((x) & BIT_MASK_SDIO_C2H_MSG_8822C) << BIT_SHIFT_SDIO_C2H_MSG_8822C)\n#define BITS_SDIO_C2H_MSG_8822C                                                \\\n\t(BIT_MASK_SDIO_C2H_MSG_8822C << BIT_SHIFT_SDIO_C2H_MSG_8822C)\n#define BIT_CLEAR_SDIO_C2H_MSG_8822C(x) ((x) & (~BITS_SDIO_C2H_MSG_8822C))\n#define BIT_GET_SDIO_C2H_MSG_8822C(x)                                          \\\n\t(((x) >> BIT_SHIFT_SDIO_C2H_MSG_8822C) & BIT_MASK_SDIO_C2H_MSG_8822C)\n#define BIT_SET_SDIO_C2H_MSG_8822C(x, v)                                       \\\n\t(BIT_CLEAR_SDIO_C2H_MSG_8822C(x) | BIT_SDIO_C2H_MSG_8822C(v))\n\n/* 2 REG_SDIO_HRPWM1_8822C */\n#define BIT_TOGGLE_8822C BIT(7)\n#define BIT_ACK_8822C BIT(6)\n#define BIT_REQ_PS_8822C BIT(0)\n\n/* 2 REG_SDIO_HRPWM2_8822C */\n\n/* 2 REG_SDIO_HPS_CLKR_8822C */\n\n/* 2 REG_SDIO_BUS_CTRL_8822C */\n#define BIT_INT_MASK_DIS_8822C BIT(4)\n#define BIT_PAD_CLK_XHGE_EN_8822C BIT(3)\n#define BIT_INTER_CLK_EN_8822C BIT(2)\n#define BIT_EN_RPT_TXCRC_8822C BIT(1)\n#define BIT_DIS_RXDMA_STS_8822C BIT(0)\n\n/* 2 REG_SDIO_HSUS_CTRL_8822C */\n#define BIT_INTR_CTRL_8822C BIT(4)\n#define BIT_SDIO_VOLTAGE_8822C BIT(3)\n#define BIT_BYPASS_INIT_8822C BIT(2)\n#define BIT_HCI_RESUME_RDY_8822C BIT(1)\n#define BIT_HCI_SUS_REQ_8822C BIT(0)\n\n/* 2 REG_SDIO_RESPONSE_TIMER_8822C */\n\n#define BIT_SHIFT_CMDIN_2RESP_TIMER_8822C 0\n#define BIT_MASK_CMDIN_2RESP_TIMER_8822C 0xffff\n#define BIT_CMDIN_2RESP_TIMER_8822C(x)                                         \\\n\t(((x) & BIT_MASK_CMDIN_2RESP_TIMER_8822C)                              \\\n\t << BIT_SHIFT_CMDIN_2RESP_TIMER_8822C)\n#define BITS_CMDIN_2RESP_TIMER_8822C                                           \\\n\t(BIT_MASK_CMDIN_2RESP_TIMER_8822C << BIT_SHIFT_CMDIN_2RESP_TIMER_8822C)\n#define BIT_CLEAR_CMDIN_2RESP_TIMER_8822C(x)                                   \\\n\t((x) & (~BITS_CMDIN_2RESP_TIMER_8822C))\n#define BIT_GET_CMDIN_2RESP_TIMER_8822C(x)                                     \\\n\t(((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8822C) &                          \\\n\t BIT_MASK_CMDIN_2RESP_TIMER_8822C)\n#define BIT_SET_CMDIN_2RESP_TIMER_8822C(x, v)                                  \\\n\t(BIT_CLEAR_CMDIN_2RESP_TIMER_8822C(x) | BIT_CMDIN_2RESP_TIMER_8822C(v))\n\n/* 2 REG_SDIO_CMD_CRC_8822C */\n\n#define BIT_SHIFT_SDIO_CMD_CRC_V1_8822C 0\n#define BIT_MASK_SDIO_CMD_CRC_V1_8822C 0xff\n#define BIT_SDIO_CMD_CRC_V1_8822C(x)                                           \\\n\t(((x) & BIT_MASK_SDIO_CMD_CRC_V1_8822C)                                \\\n\t << BIT_SHIFT_SDIO_CMD_CRC_V1_8822C)\n#define BITS_SDIO_CMD_CRC_V1_8822C                                             \\\n\t(BIT_MASK_SDIO_CMD_CRC_V1_8822C << BIT_SHIFT_SDIO_CMD_CRC_V1_8822C)\n#define BIT_CLEAR_SDIO_CMD_CRC_V1_8822C(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8822C))\n#define BIT_GET_SDIO_CMD_CRC_V1_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8822C) &                            \\\n\t BIT_MASK_SDIO_CMD_CRC_V1_8822C)\n#define BIT_SET_SDIO_CMD_CRC_V1_8822C(x, v)                                    \\\n\t(BIT_CLEAR_SDIO_CMD_CRC_V1_8822C(x) | BIT_SDIO_CMD_CRC_V1_8822C(v))\n\n/* 2 REG_SDIO_HSISR_8822C */\n#define BIT_DRV_WLAN_INT_CLR_8822C BIT(1)\n#define BIT_DRV_WLAN_INT_8822C BIT(0)\n\n/* 2 REG_SDIO_HSIMR_8822C */\n#define BIT_HISR_MASK_8822C BIT(0)\n\n/* 2 REG_SDIO_DIOERR_RPT_8822C */\n#define BIT_SDIO_PAGE_ERR_8822C BIT(0)\n\n/* 2 REG_SDIO_CMD_ERRCNT_8822C */\n\n#define BIT_SHIFT_CMD_CRC_ERR_CNT_8822C 0\n#define BIT_MASK_CMD_CRC_ERR_CNT_8822C 0xff\n#define BIT_CMD_CRC_ERR_CNT_8822C(x)                                           \\\n\t(((x) & BIT_MASK_CMD_CRC_ERR_CNT_8822C)                                \\\n\t << BIT_SHIFT_CMD_CRC_ERR_CNT_8822C)\n#define BITS_CMD_CRC_ERR_CNT_8822C                                             \\\n\t(BIT_MASK_CMD_CRC_ERR_CNT_8822C << BIT_SHIFT_CMD_CRC_ERR_CNT_8822C)\n#define BIT_CLEAR_CMD_CRC_ERR_CNT_8822C(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8822C))\n#define BIT_GET_CMD_CRC_ERR_CNT_8822C(x)                                       \\\n\t(((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8822C) &                            \\\n\t BIT_MASK_CMD_CRC_ERR_CNT_8822C)\n#define BIT_SET_CMD_CRC_ERR_CNT_8822C(x, v)                                    \\\n\t(BIT_CLEAR_CMD_CRC_ERR_CNT_8822C(x) | BIT_CMD_CRC_ERR_CNT_8822C(v))\n\n/* 2 REG_SDIO_DATA_ERRCNT_8822C */\n\n#define BIT_SHIFT_DATA_CRC_ERR_CNT_8822C 0\n#define BIT_MASK_DATA_CRC_ERR_CNT_8822C 0xff\n#define BIT_DATA_CRC_ERR_CNT_8822C(x)                                          \\\n\t(((x) & BIT_MASK_DATA_CRC_ERR_CNT_8822C)                               \\\n\t << BIT_SHIFT_DATA_CRC_ERR_CNT_8822C)\n#define BITS_DATA_CRC_ERR_CNT_8822C                                            \\\n\t(BIT_MASK_DATA_CRC_ERR_CNT_8822C << BIT_SHIFT_DATA_CRC_ERR_CNT_8822C)\n#define BIT_CLEAR_DATA_CRC_ERR_CNT_8822C(x)                                    \\\n\t((x) & (~BITS_DATA_CRC_ERR_CNT_8822C))\n#define BIT_GET_DATA_CRC_ERR_CNT_8822C(x)                                      \\\n\t(((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8822C) &                           \\\n\t BIT_MASK_DATA_CRC_ERR_CNT_8822C)\n#define BIT_SET_DATA_CRC_ERR_CNT_8822C(x, v)                                   \\\n\t(BIT_CLEAR_DATA_CRC_ERR_CNT_8822C(x) | BIT_DATA_CRC_ERR_CNT_8822C(v))\n\n/* 2 REG_SDIO_CMD_ERR_CONTENT_8822C */\n\n#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C 0\n#define BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C 0xffffffffffL\n#define BIT_SDIO_CMD_ERR_CONTENT_8822C(x)                                      \\\n\t(((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C)                           \\\n\t << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C)\n#define BITS_SDIO_CMD_ERR_CONTENT_8822C                                        \\\n\t(BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C                                   \\\n\t << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C)\n#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822C(x)                                \\\n\t((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8822C))\n#define BIT_GET_SDIO_CMD_ERR_CONTENT_8822C(x)                                  \\\n\t(((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C) &                       \\\n\t BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C)\n#define BIT_SET_SDIO_CMD_ERR_CONTENT_8822C(x, v)                               \\\n\t(BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822C(x) |                             \\\n\t BIT_SDIO_CMD_ERR_CONTENT_8822C(v))\n\n/* 2 REG_SDIO_CRC_ERR_IDX_8822C */\n#define BIT_D3_CRC_ERR_8822C BIT(4)\n#define BIT_D2_CRC_ERR_8822C BIT(3)\n#define BIT_D1_CRC_ERR_8822C BIT(2)\n#define BIT_D0_CRC_ERR_8822C BIT(1)\n#define BIT_CMD_CRC_ERR_8822C BIT(0)\n\n/* 2 REG_SDIO_DATA_CRC_8822C */\n\n#define BIT_SHIFT_SDIO_DATA_CRC_8822C 0\n#define BIT_MASK_SDIO_DATA_CRC_8822C 0xffff\n#define BIT_SDIO_DATA_CRC_8822C(x)                                             \\\n\t(((x) & BIT_MASK_SDIO_DATA_CRC_8822C) << BIT_SHIFT_SDIO_DATA_CRC_8822C)\n#define BITS_SDIO_DATA_CRC_8822C                                               \\\n\t(BIT_MASK_SDIO_DATA_CRC_8822C << BIT_SHIFT_SDIO_DATA_CRC_8822C)\n#define BIT_CLEAR_SDIO_DATA_CRC_8822C(x) ((x) & (~BITS_SDIO_DATA_CRC_8822C))\n#define BIT_GET_SDIO_DATA_CRC_8822C(x)                                         \\\n\t(((x) >> BIT_SHIFT_SDIO_DATA_CRC_8822C) & BIT_MASK_SDIO_DATA_CRC_8822C)\n#define BIT_SET_SDIO_DATA_CRC_8822C(x, v)                                      \\\n\t(BIT_CLEAR_SDIO_DATA_CRC_8822C(x) | BIT_SDIO_DATA_CRC_8822C(v))\n\n/* 2 REG_SDIO_TRANS_FIFO_STATUS_8822C */\n#define BIT_TRANS_FIFO_UNDERFLOW_8822C BIT(1)\n#define BIT_TRANS_FIFO_OVERFLOW_8822C BIT(0)\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_fw_info.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_FW_INFO_H_\n#define _HALMAC_FW_INFO_H_\n\n#define H2C_FORMAT_VERSION\t\t12\n\n/* FW bin information */\n#define WLAN_FW_HDR_SIZE\t\t64\n#define WLAN_FW_HDR_CHKSUM_SIZE\t\t8\n\n#define WLAN_FW_HDR_VERSION\t\t4\n#define WLAN_FW_HDR_SUBVERSION\t\t6\n#define WLAN_FW_HDR_SUBINDEX\t\t7\n#define WLAN_FW_HDR_MONTH\t\t16\n#define WLAN_FW_HDR_DATE\t\t17\n#define WLAN_FW_HDR_HOUR\t\t18\n#define WLAN_FW_HDR_MIN\t\t\t19\n#define WLAN_FW_HDR_YEAR\t\t20\n#define WLAN_FW_HDR_MEM_USAGE\t\t24\n#define WLAN_FW_HDR_H2C_FMT_VER\t\t28\n#define WLAN_FW_HDR_DMEM_ADDR\t\t32\n#define WLAN_FW_HDR_DMEM_SIZE\t\t36\n#define WLAN_FW_HDR_IMEM_SIZE\t\t48\n#define WLAN_FW_HDR_EMEM_SIZE\t\t52\n#define WLAN_FW_HDR_EMEM_ADDR\t\t56\n#define WLAN_FW_HDR_IMEM_ADDR\t\t60\n\n#define H2C_ACK_HDR_CONTENT_LENGTH\t\t8\n#define CFG_PARAMETER_ACK_CONTENT_LENGTH\t16\n#define SCAN_STATUS_RPT_CONTENT_LENGTH\t\t4\n#define C2H_DBG_HDR_LEN\t\t\t\t4\n#define C2H_DBG_CONTENT_MAX_LENGTH\t\t228\n#define C2H_DBG_CONTENT_SEQ_OFFSET\t\t1\n\n/* Rename from FW SysHalCom_Debug_RAM.h */\n#define FW_REG_H2CPKT_DONE_SEQ\t\t0x1C8\n#define FW_REG_WOW_REASON\t\t0x1C7\n\nenum halmac_data_type {\n\tHALMAC_DATA_TYPE_MAC_REG = 0x00,\n\tHALMAC_DATA_TYPE_BB_REG = 0x01,\n\tHALMAC_DATA_TYPE_RADIO_A = 0x02,\n\tHALMAC_DATA_TYPE_RADIO_B = 0x03,\n\tHALMAC_DATA_TYPE_RADIO_C = 0x04,\n\tHALMAC_DATA_TYPE_RADIO_D = 0x05,\n\n\tHALMAC_DATA_TYPE_DRV_DEFINE_0 = 0x80,\n\tHALMAC_DATA_TYPE_DRV_DEFINE_1 = 0x81,\n\tHALMAC_DATA_TYPE_DRV_DEFINE_2 = 0x82,\n\tHALMAC_DATA_TYPE_DRV_DEFINE_3 = 0x83,\n\tHALMAC_DATA_TYPE_UNDEFINE = 0x7FFFFFFF,\n};\n\nenum halmac_packet_id {\n\tHALMAC_PACKET_PROBE_REQ = 0x00,\n\tHALMAC_PACKET_SYNC_BCN = 0x01,\n\tHALMAC_PACKET_DISCOVERY_BCN = 0x02,\n\tHALMAC_PACKET_PROBE_REQ_NLO = 0xF0,\n\tHALMAC_PACKET_SYNC_BCN_NLO = 0xF1,\n\tHALMAC_PACKET_DISCOVERY_BCN_NLO = 0xF2,\n\tHALMAC_PACKET_UNDEFINE = 0x7FFFFFFF,\n};\n\nenum halmac_cs_action_id {\n\tHALMAC_CS_ACTION_NONE = 0x00,\n\tHALMAC_CS_ACTIVE_SCAN = 0x01,\n\tHALMAC_CS_NAN_NONMASTER_DW = 0x02,\n\tHALMAC_CS_NAN_NONMASTER_NONDW = 0x03,\n\tHALMAC_CS_NAN_MASTER_NONDW = 0x04,\n\tHALMAC_CS_NAN_MASTER_DW = 0x05,\n\tHALMAC_CS_ACTION_UNDEFINE = 0x7FFFFFFF,\n};\n\nenum halmac_cs_extra_action_id {\n\tHALMAC_CS_EXTRA_ACTION_NONE = 0x00,\n\tHALMAC_CS_EXTRA_UPDATE_PROBE = 0x01,\n\tHALMAC_CS_EXTRA_UPDATE_BEACON = 0x02,\n\tHALMAC_CS_EXTRA_ACTION_UNDEFINE = 0x7FFFFFFF,\n};\n\nenum halmac_h2c_return_code {\n\tHALMAC_H2C_RETURN_SUCCESS = 0x00,\n\tHALMAC_H2C_RETURN_CFG_ERR_LEN = 0x01,\n\tHALMAC_H2C_RETURN_CFG_ERR_CMD = 0x02,\n\tHALMAC_H2C_RETURN_EFUSE_ERR_DUMP = 0x03,\n\tHALMAC_H2C_RETURN_DATAPACK_ERR_FULL = 0x04,\n\tHALMAC_H2C_RETURN_DATAPACK_ERR_ID = 0x05,\n\tHALMAC_H2C_RETURN_RUN_ERR_EMPTY = 0x06,\n\tHALMAC_H2C_RETURN_RUN_ERR_LEN = 0x07,\n\tHALMAC_H2C_RETURN_RUN_ERR_CMD = 0x08,\n\tHALMAC_H2C_RETURN_RUN_ERR_ID = 0x09,\n\tHALMAC_H2C_RETURN_PACKET_ERR_FULL = 0x0A,\n\tHALMAC_H2C_RETURN_PACKET_ERR_ID = 0x0B,\n\tHALMAC_H2C_RETURN_SCAN_ERR_FULL = 0x0C,\n\tHALMAC_H2C_RETURN_SCAN_ERR_PHYDM = 0x0D,\n\tHALMAC_H2C_RETURN_ORIG_ERR_ID = 0x0E,\n\tHALMAC_H2C_RETURN_UNDEFINE = 0x7FFFFFFF,\n};\n\nenum halmac_scan_report_code {\n\tHALMAC_SCAN_REPORT_DONE\t= 0x00,\n\tHALMAC_SCAN_REPORT_ERR_PHYDM = 0x01,\n\tHALMAC_SCAN_REPORT_ERR_ID = 0x02,\n\tHALMAC_SCAN_REPORT_ERR_TX = 0x03,\n\tHALMAC_SCAN_REPORT_UNDEFINE = 0x7FFFFFFF,\n};\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_fw_offload_c2h_ap.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_AP_H_\n#define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_AP_H_\n#define C2H_SUB_CMD_ID_C2H_DBG 0X00\n#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02\n#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03\n#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01\n#define C2H_SUB_CMD_ID_CFG_PARAM_ACK 0X01\n#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01\n#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01\n#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01\n#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01\n#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01\n#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01\n#define C2H_SUB_CMD_ID_IQK_ACK 0X01\n#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01\n#define C2H_SUB_CMD_ID_PSD_ACK 0X01\n#define C2H_SUB_CMD_ID_FW_MEM_DUMP_ACK 0X01\n#define C2H_SUB_CMD_ID_PSD_DATA 0X04\n#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05\n#define C2H_SUB_CMD_ID_IQK_DATA 0X06\n#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07\n#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08\n#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09\n#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A\n#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B\n#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C\n#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D\n#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E\n#define C2H_SUB_CMD_ID_CCX_RPT 0X0F\n#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10\n#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11\n#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C\n#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D\n#define C2H_SUB_CMD_ID_FW_DBG_MSG 0XFF\n#define C2H_SUB_CMD_ID_FW_SNDING_ACK 0X01\n#define C2H_SUB_CMD_ID_FW_FWCTRL_RPT 0X1F\n#define C2H_SUB_CMD_ID_H2C_LOOPBACK_ACK 0X20\n#define C2H_SUB_CMD_ID_FWCMD_LOOPBACK_ACK 0X21\n#define C2H_SUB_CMD_ID_SCAN_CH_NOTIFY 0X22\n#define C2H_SUB_CMD_ID_FW_TBTT_RPT 0X23\n#define C2H_SUB_CMD_ID_BCN_OFFLOAD 0X24\n#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM\n#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH\n#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX\n#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE\n#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT\n#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK\n#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK\n#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK\n#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK\n#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD\n#define H2C_SUB_CMD_ID_FW_MEM_DUMP_ACK SUB_CMD_ID_FW_MEM_DUMP\n#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT\n#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG\n#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING\n#define H2C_SUB_CMD_ID_FW_FWCTRL_RPT SUB_CMD_ID_FW_FWCTRL_RPT\n#define H2C_SUB_CMD_ID_H2C_LOOPBACK_ACK SUB_CMD_ID_H2C_LOOPBACK\n#define H2C_SUB_CMD_ID_FWCMD_LOOPBACK_ACK SUB_CMD_ID_FWCMD_LOOPBACK\n#define H2C_CMD_ID_CFG_PARAM_ACK 0XFF\n#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF\n#define H2C_CMD_ID_BT_COEX_ACK 0XFF\n#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF\n#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF\n#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF\n#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF\n#define H2C_CMD_ID_IQK_ACK 0XFF\n#define H2C_CMD_ID_PWR_TRK_ACK 0XFF\n#define H2C_CMD_ID_PSD_ACK 0XFF\n#define H2C_CMD_ID_FW_MEM_DUMP_ACK 0XFF\n#define H2C_CMD_ID_CCX_RPT 0XFF\n#define H2C_CMD_ID_FW_DBG_MSG 0XFF\n#define H2C_CMD_ID_FW_SNDING_ACK 0XFF\n#define H2C_CMD_ID_FW_FWCTRL_RPT 0XFF\n#define H2C_CMD_ID_H2C_LOOPBACK_ACK 0XFF\n#define H2C_CMD_ID_FWCMD_LOOPBACK_ACK 0XFF\n#define C2H_HDR_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)\n#define C2H_HDR_SET_CMD_ID(c2h_pkt, value)                                     \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_HDR_SET_CMD_ID_NO_CLR(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_HDR_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)\n#define C2H_HDR_SET_SEQ(c2h_pkt, value)                                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_HDR_SET_SEQ_NO_CLR(c2h_pkt, value)                                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)\n#define C2H_HDR_SET_C2H_SUB_CMD_ID(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)\n#define C2H_HDR_SET_C2H_SUB_CMD_ID_NO_CLR(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)\n#define C2H_HDR_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)\n#define C2H_HDR_SET_LEN(c2h_pkt, value)                                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_HDR_SET_LEN_NO_CLR(c2h_pkt, value)                                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_DBG_GET_DBG_MSG(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)\n#define C2H_DBG_SET_DBG_MSG(c2h_pkt, value)                                    \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define C2H_DBG_SET_DBG_MSG_NO_CLR(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define BT_COEX_INFO_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)\n#define BT_COEX_INFO_SET_DATA_START(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define BT_COEX_INFO_SET_DATA_START_NO_CLR(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(c2h_pkt)                           \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)\n#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(c2h_pkt, value)                    \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE_NO_CLR(c2h_pkt, value)             \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define SCAN_STATUS_RPT_GET_H2C_SEQ(c2h_pkt)                                   \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)\n#define SCAN_STATUS_RPT_SET_H2C_SEQ(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)\n#define SCAN_STATUS_RPT_SET_H2C_SEQ_NO_CLR(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)\n#define SCAN_STATUS_RPT_GET_TSF_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)\n#define SCAN_STATUS_RPT_SET_TSF_0(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)\n#define SCAN_STATUS_RPT_SET_TSF_0_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)\n#define SCAN_STATUS_RPT_GET_TSF_1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)\n#define SCAN_STATUS_RPT_SET_TSF_1(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)\n#define SCAN_STATUS_RPT_SET_TSF_1_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)\n#define SCAN_STATUS_RPT_GET_TSF_2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)\n#define SCAN_STATUS_RPT_SET_TSF_2(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)\n#define SCAN_STATUS_RPT_SET_TSF_2_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)\n#define SCAN_STATUS_RPT_GET_TSF_3(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8)\n#define SCAN_STATUS_RPT_SET_TSF_3(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value)\n#define SCAN_STATUS_RPT_SET_TSF_3_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value)\n#define SCAN_STATUS_RPT_GET_TSF_4(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 0, 8)\n#define SCAN_STATUS_RPT_SET_TSF_4(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 8, value)\n#define SCAN_STATUS_RPT_SET_TSF_4_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 8, value)\n#define SCAN_STATUS_RPT_GET_TSF_5(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 8, 8)\n#define SCAN_STATUS_RPT_SET_TSF_5(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0XC, 8, 8, value)\n#define SCAN_STATUS_RPT_SET_TSF_5_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 8, 8, value)\n#define SCAN_STATUS_RPT_GET_TSF_6(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 16, 8)\n#define SCAN_STATUS_RPT_SET_TSF_6(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0XC, 16, 8, value)\n#define SCAN_STATUS_RPT_SET_TSF_6_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 16, 8, value)\n#define SCAN_STATUS_RPT_GET_TSF_7(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 24, 8)\n#define SCAN_STATUS_RPT_SET_TSF_7(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0XC, 24, 8, value)\n#define SCAN_STATUS_RPT_SET_TSF_7_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 24, 8, value)\n#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_pkt)                               \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)\n#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define H2C_ACK_HDR_SET_H2C_RETURN_CODE_NO_CLR(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define H2C_ACK_HDR_GET_H2C_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)\n#define H2C_ACK_HDR_SET_H2C_CMD_ID(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define H2C_ACK_HDR_SET_H2C_CMD_ID_NO_CLR(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(c2h_pkt)                                \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)\n#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)\n#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID_NO_CLR(c2h_pkt, value)                  \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)\n#define H2C_ACK_HDR_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 16)\n#define H2C_ACK_HDR_SET_H2C_SEQ(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 16, value)\n#define H2C_ACK_HDR_SET_H2C_SEQ_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 16, value)\n#define CFG_PARAM_ACK_GET_OFFSET_ACCUMULATION(c2h_pkt)                         \\\n\tGET_C2H_FIELD(c2h_pkt + 0XC, 0, 32)\n#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION(c2h_pkt, value)                  \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 32, value)\n#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION_NO_CLR(c2h_pkt, value)           \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 32, value)\n#define CFG_PARAM_ACK_GET_VALUE_ACCUMULATION(c2h_pkt)                          \\\n\tGET_C2H_FIELD(c2h_pkt + 0X10, 0, 32)\n#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION(c2h_pkt, value)                   \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X10, 0, 32, value)\n#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION_NO_CLR(c2h_pkt, value)            \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 0, 32, value)\n#define CH_SWITCH_ACK_GET_TSF_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8)\n#define CH_SWITCH_ACK_SET_TSF_0(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value)\n#define CH_SWITCH_ACK_SET_TSF_0_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value)\n#define CH_SWITCH_ACK_GET_TSF_1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8)\n#define CH_SWITCH_ACK_SET_TSF_1(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value)\n#define CH_SWITCH_ACK_SET_TSF_1_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value)\n#define CH_SWITCH_ACK_GET_TSF_2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)\n#define CH_SWITCH_ACK_SET_TSF_2(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define CH_SWITCH_ACK_SET_TSF_2_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define CH_SWITCH_ACK_GET_TSF_3(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)\n#define CH_SWITCH_ACK_SET_TSF_3(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define CH_SWITCH_ACK_SET_TSF_3_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define CH_SWITCH_ACK_GET_TSF_4(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X10, 0, 8)\n#define CH_SWITCH_ACK_SET_TSF_4(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X10, 0, 8, value)\n#define CH_SWITCH_ACK_SET_TSF_4_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 0, 8, value)\n#define CH_SWITCH_ACK_GET_TSF_5(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X10, 8, 8)\n#define CH_SWITCH_ACK_SET_TSF_5(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X10, 8, 8, value)\n#define CH_SWITCH_ACK_SET_TSF_5_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 8, 8, value)\n#define CH_SWITCH_ACK_GET_TSF_6(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X10, 16, 8)\n#define CH_SWITCH_ACK_SET_TSF_6(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X10, 16, 8, value)\n#define CH_SWITCH_ACK_SET_TSF_6_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 16, 8, value)\n#define CH_SWITCH_ACK_GET_TSF_7(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X10, 24, 8)\n#define CH_SWITCH_ACK_SET_TSF_7(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X10, 24, 8, value)\n#define CH_SWITCH_ACK_SET_TSF_7_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 24, 8, value)\n#define BT_COEX_ACK_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 0, 8)\n#define BT_COEX_ACK_SET_DATA_START(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 8, value)\n#define BT_COEX_ACK_SET_DATA_START_NO_CLR(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 8, value)\n#define PSD_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7)\n#define PSD_DATA_SET_SEGMENT_ID(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value)\n#define PSD_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value)\n#define PSD_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1)\n#define PSD_DATA_SET_END_SEGMENT(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value)\n#define PSD_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value)\n#define PSD_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)\n#define PSD_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define PSD_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define PSD_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)\n#define PSD_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)\n#define PSD_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)\n#define PSD_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16)\n#define PSD_DATA_SET_H2C_SEQ(c2h_pkt, value)                                   \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value)\n#define PSD_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value)\n#define PSD_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)\n#define PSD_DATA_SET_DATA_START(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)\n#define PSD_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)\n#define EFUSE_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7)\n#define EFUSE_DATA_SET_SEGMENT_ID(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value)\n#define EFUSE_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value)\n#define EFUSE_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1)\n#define EFUSE_DATA_SET_END_SEGMENT(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value)\n#define EFUSE_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value)\n#define EFUSE_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)\n#define EFUSE_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define EFUSE_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define EFUSE_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)\n#define EFUSE_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)\n#define EFUSE_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)\n#define EFUSE_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16)\n#define EFUSE_DATA_SET_H2C_SEQ(c2h_pkt, value)                                 \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value)\n#define EFUSE_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value)                          \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value)\n#define EFUSE_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)\n#define EFUSE_DATA_SET_DATA_START(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)\n#define EFUSE_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)\n#define IQK_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7)\n#define IQK_DATA_SET_SEGMENT_ID(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value)\n#define IQK_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value)\n#define IQK_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1)\n#define IQK_DATA_SET_END_SEGMENT(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value)\n#define IQK_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value)\n#define IQK_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)\n#define IQK_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define IQK_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define IQK_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)\n#define IQK_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)\n#define IQK_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)\n#define IQK_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16)\n#define IQK_DATA_SET_H2C_SEQ(c2h_pkt, value)                                   \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value)\n#define IQK_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value)\n#define IQK_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)\n#define IQK_DATA_SET_DATA_START(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)\n#define IQK_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)\n#define CCX_RPT_GET_POLLUTED(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 0, 1)\n#define CCX_RPT_SET_POLLUTED(c2h_pkt, value)                                   \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X4, 0, 1, value)\n#define CCX_RPT_SET_POLLUTED_NO_CLR(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 0, 1, value)\n#define CCX_RPT_GET_RPT_SEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 5, 3)\n#define CCX_RPT_SET_RPT_SEL(c2h_pkt, value)                                    \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X4, 5, 3, value)\n#define CCX_RPT_SET_RPT_SEL_NO_CLR(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 5, 3, value)\n#define CCX_RPT_GET_QSEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 8, 5)\n#define CCX_RPT_SET_QSEL(c2h_pkt, value)                                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X4, 8, 5, value)\n#define CCX_RPT_SET_QSEL_NO_CLR(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 8, 5, value)\n#define CCX_RPT_GET_MISSED_RPT_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 13, 3)\n#define CCX_RPT_SET_MISSED_RPT_NUM(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X4, 13, 3, value)\n#define CCX_RPT_SET_MISSED_RPT_NUM_NO_CLR(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 13, 3, value)\n#define CCX_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 16, 7)\n#define CCX_RPT_SET_MACID(c2h_pkt, value)                                      \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X4, 16, 7, value)\n#define CCX_RPT_SET_MACID_NO_CLR(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 16, 7, value)\n#define CCX_RPT_GET_INITIAL_DATA_RATE(c2h_pkt)                                 \\\n\tGET_C2H_FIELD(c2h_pkt + 0X4, 24, 7)\n#define CCX_RPT_SET_INITIAL_DATA_RATE(c2h_pkt, value)                          \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X4, 24, 7, value)\n#define CCX_RPT_SET_INITIAL_DATA_RATE_NO_CLR(c2h_pkt, value)                   \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 24, 7, value)\n#define CCX_RPT_GET_INITIAL_SGI(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 31, 1)\n#define CCX_RPT_SET_INITIAL_SGI(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X4, 31, 1, value)\n#define CCX_RPT_SET_INITIAL_SGI_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 31, 1, value)\n#define CCX_RPT_GET_QUEUE_TIME(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16)\n#define CCX_RPT_SET_QUEUE_TIME(c2h_pkt, value)                                 \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value)\n#define CCX_RPT_SET_QUEUE_TIME_NO_CLR(c2h_pkt, value)                          \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value)\n#define CCX_RPT_GET_SW_DEFINE_BYTE0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)\n#define CCX_RPT_SET_SW_DEFINE_BYTE0(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)\n#define CCX_RPT_SET_SW_DEFINE_BYTE0_NO_CLR(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)\n#define CCX_RPT_GET_RTS_RETRY_COUNT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 24, 4)\n#define CCX_RPT_SET_RTS_RETRY_COUNT(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 4, value)\n#define CCX_RPT_SET_RTS_RETRY_COUNT_NO_CLR(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 4, value)\n#define CCX_RPT_GET_BMC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 29, 1)\n#define CCX_RPT_SET_BMC(c2h_pkt, value)                                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 29, 1, value)\n#define CCX_RPT_SET_BMC_NO_CLR(c2h_pkt, value)                                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 29, 1, value)\n#define CCX_RPT_GET_TX_STATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 30, 2)\n#define CCX_RPT_SET_TX_STATE(c2h_pkt, value)                                   \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 30, 2, value)\n#define CCX_RPT_SET_TX_STATE_NO_CLR(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 30, 2, value)\n#define CCX_RPT_GET_DATA_RETRY_COUNT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 0, 6)\n#define CCX_RPT_SET_DATA_RETRY_COUNT(c2h_pkt, value)                           \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 6, value)\n#define CCX_RPT_SET_DATA_RETRY_COUNT_NO_CLR(c2h_pkt, value)                    \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 6, value)\n#define CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 8, 7)\n#define CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0XC, 8, 7, value)\n#define CCX_RPT_SET_FINAL_DATA_RATE_NO_CLR(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 8, 7, value)\n#define CCX_RPT_GET_FINAL_SGI(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 15, 1)\n#define CCX_RPT_SET_FINAL_SGI(c2h_pkt, value)                                  \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0XC, 15, 1, value)\n#define CCX_RPT_SET_FINAL_SGI_NO_CLR(c2h_pkt, value)                           \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 15, 1, value)\n#define CCX_RPT_GET_RF_CH_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 16, 10)\n#define CCX_RPT_SET_RF_CH_NUM(c2h_pkt, value)                                  \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0XC, 16, 10, value)\n#define CCX_RPT_SET_RF_CH_NUM_NO_CLR(c2h_pkt, value)                           \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 16, 10, value)\n#define CCX_RPT_GET_SC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 26, 4)\n#define CCX_RPT_SET_SC(c2h_pkt, value)                                         \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0XC, 26, 4, value)\n#define CCX_RPT_SET_SC_NO_CLR(c2h_pkt, value)                                  \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 26, 4, value)\n#define CCX_RPT_GET_BW(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 30, 2)\n#define CCX_RPT_SET_BW(c2h_pkt, value)                                         \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0XC, 30, 2, value)\n#define CCX_RPT_SET_BW_NO_CLR(c2h_pkt, value)                                  \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 30, 2, value)\n#define FW_DBG_MSG_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)\n#define FW_DBG_MSG_SET_CMD_ID(c2h_pkt, value)                                  \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define FW_DBG_MSG_SET_CMD_ID_NO_CLR(c2h_pkt, value)                           \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define FW_DBG_MSG_GET_C2H_SUB_CMD_ID(c2h_pkt)                                 \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)\n#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID(c2h_pkt, value)                          \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)\n#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID_NO_CLR(c2h_pkt, value)                   \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)\n#define FW_DBG_MSG_GET_FULL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 1)\n#define FW_DBG_MSG_SET_FULL(c2h_pkt, value)                                    \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 1, value)\n#define FW_DBG_MSG_SET_FULL_NO_CLR(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 1, value)\n#define FW_DBG_MSG_GET_OWN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 31, 1)\n#define FW_DBG_MSG_SET_OWN(c2h_pkt, value)                                     \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 31, 1, value)\n#define FW_DBG_MSG_SET_OWN_NO_CLR(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 31, 1, value)\n#define FW_FWCTRL_RPT_GET_EVT_TYPE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)\n#define FW_FWCTRL_RPT_SET_EVT_TYPE(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define FW_FWCTRL_RPT_SET_EVT_TYPE_NO_CLR(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define FW_FWCTRL_RPT_GET_LENGTH(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)\n#define FW_FWCTRL_RPT_SET_LENGTH(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define FW_FWCTRL_RPT_SET_LENGTH_NO_CLR(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define FW_FWCTRL_RPT_GET_SEQ_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)\n#define FW_FWCTRL_RPT_SET_SEQ_NUM(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)\n#define FW_FWCTRL_RPT_SET_SEQ_NUM_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)\n#define FW_FWCTRL_RPT_GET_IS_ACK(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 1)\n#define FW_FWCTRL_RPT_SET_IS_ACK(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 1, value)\n#define FW_FWCTRL_RPT_SET_IS_ACK_NO_CLR(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 1, value)\n#define FW_FWCTRL_RPT_GET_MORE_CONTENT(c2h_pkt)                                \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 25, 1)\n#define FW_FWCTRL_RPT_SET_MORE_CONTENT(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 25, 1, value)\n#define FW_FWCTRL_RPT_SET_MORE_CONTENT_NO_CLR(c2h_pkt, value)                  \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 25, 1, value)\n#define FW_FWCTRL_RPT_GET_CONTENT_IDX(c2h_pkt)                                 \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 26, 6)\n#define FW_FWCTRL_RPT_SET_CONTENT_IDX(c2h_pkt, value)                          \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 26, 6, value)\n#define FW_FWCTRL_RPT_SET_CONTENT_IDX_NO_CLR(c2h_pkt, value)                   \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 26, 6, value)\n#define FW_FWCTRL_RPT_GET_CLASS_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)\n#define FW_FWCTRL_RPT_SET_CLASS_ID(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define FW_FWCTRL_RPT_SET_CLASS_ID_NO_CLR(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define FW_FWCTRL_RPT_GET_CONTENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)\n#define FW_FWCTRL_RPT_SET_CONTENT(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)\n#define FW_FWCTRL_RPT_SET_CONTENT_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)\n#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt)                               \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0_NO_CLR(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt)                               \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1_NO_CLR(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt)                               \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2_NO_CLR(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)\n#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt)                               \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3_NO_CLR(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)\n#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt)                               \\\n\tGET_C2H_FIELD(c2h_pkt + 0X8, 0, 8)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 8, value)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4_NO_CLR(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 8, value)\n#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt)                               \\\n\tGET_C2H_FIELD(c2h_pkt + 0X8, 8, 8)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 8, 8, value)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5_NO_CLR(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 8, 8, value)\n#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt)                               \\\n\tGET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6_NO_CLR(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)\n#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt)                               \\\n\tGET_C2H_FIELD(c2h_pkt + 0X8, 24, 8)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 8, value)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7_NO_CLR(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 8, value)\n#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt)                             \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0_NO_CLR(c2h_pkt, value)               \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt)                             \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1_NO_CLR(c2h_pkt, value)               \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt)                             \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2_NO_CLR(c2h_pkt, value)               \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)\n#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt)                             \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3_NO_CLR(c2h_pkt, value)               \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)\n#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt)                             \\\n\tGET_C2H_FIELD(c2h_pkt + 0X8, 0, 8)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 8, value)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4_NO_CLR(c2h_pkt, value)               \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 8, value)\n#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt)                             \\\n\tGET_C2H_FIELD(c2h_pkt + 0X8, 8, 8)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 8, 8, value)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5_NO_CLR(c2h_pkt, value)               \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 8, 8, value)\n#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt)                             \\\n\tGET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6_NO_CLR(c2h_pkt, value)               \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)\n#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt)                             \\\n\tGET_C2H_FIELD(c2h_pkt + 0X8, 24, 8)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 8, value)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7_NO_CLR(c2h_pkt, value)               \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 8, value)\n#define SCAN_CH_NOTIFY_GET_CH_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)\n#define SCAN_CH_NOTIFY_SET_CH_NUM(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define SCAN_CH_NOTIFY_SET_CH_NUM_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define SCAN_CH_NOTIFY_GET_NOTIFY_ID(c2h_pkt)                                  \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)\n#define SCAN_CH_NOTIFY_SET_NOTIFY_ID(c2h_pkt, value)                           \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define SCAN_CH_NOTIFY_SET_NOTIFY_ID_NO_CLR(c2h_pkt, value)                    \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define SCAN_CH_NOTIFY_GET_STATUS(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)\n#define SCAN_CH_NOTIFY_SET_STATUS(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)\n#define SCAN_CH_NOTIFY_SET_STATUS_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)\n#define SCAN_CH_NOTIFY_GET_TSF_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)\n#define SCAN_CH_NOTIFY_SET_TSF_0(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)\n#define SCAN_CH_NOTIFY_SET_TSF_0_NO_CLR(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)\n#define SCAN_CH_NOTIFY_GET_TSF_1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)\n#define SCAN_CH_NOTIFY_SET_TSF_1(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)\n#define SCAN_CH_NOTIFY_SET_TSF_1_NO_CLR(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)\n#define SCAN_CH_NOTIFY_GET_TSF_2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)\n#define SCAN_CH_NOTIFY_SET_TSF_2(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)\n#define SCAN_CH_NOTIFY_SET_TSF_2_NO_CLR(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)\n#define SCAN_CH_NOTIFY_GET_TSF_3(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8)\n#define SCAN_CH_NOTIFY_SET_TSF_3(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value)\n#define SCAN_CH_NOTIFY_SET_TSF_3_NO_CLR(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value)\n#define SCAN_CH_NOTIFY_GET_TSF_4(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8)\n#define SCAN_CH_NOTIFY_SET_TSF_4(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value)\n#define SCAN_CH_NOTIFY_SET_TSF_4_NO_CLR(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value)\n#define SCAN_CH_NOTIFY_GET_TSF_5(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8)\n#define SCAN_CH_NOTIFY_SET_TSF_5(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value)\n#define SCAN_CH_NOTIFY_SET_TSF_5_NO_CLR(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value)\n#define SCAN_CH_NOTIFY_GET_TSF_6(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)\n#define SCAN_CH_NOTIFY_SET_TSF_6(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define SCAN_CH_NOTIFY_SET_TSF_6_NO_CLR(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define SCAN_CH_NOTIFY_GET_TSF_7(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)\n#define SCAN_CH_NOTIFY_SET_TSF_7(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define SCAN_CH_NOTIFY_SET_TSF_7_NO_CLR(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define FW_TBTT_RPT_GET_PORT_NUMBER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)\n#define FW_TBTT_RPT_SET_PORT_NUMBER(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define FW_TBTT_RPT_SET_PORT_NUMBER_NO_CLR(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define BCN_OFFLOAD_GET_SUPPORT_VER(c2h_pkt)                                   \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)\n#define BCN_OFFLOAD_SET_SUPPORT_VER(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define BCN_OFFLOAD_SET_SUPPORT_VER_NO_CLR(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define BCN_OFFLOAD_GET_STATUS(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)\n#define BCN_OFFLOAD_SET_STATUS(c2h_pkt, value)                                 \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define BCN_OFFLOAD_SET_STATUS_NO_CLR(c2h_pkt, value)                          \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_fw_offload_c2h_nic.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_\n#define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_\n#define C2H_SUB_CMD_ID_C2H_DBG 0X00\n#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02\n#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03\n#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01\n#define C2H_SUB_CMD_ID_CFG_PARAM_ACK 0X01\n#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01\n#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01\n#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01\n#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01\n#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01\n#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01\n#define C2H_SUB_CMD_ID_IQK_ACK 0X01\n#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01\n#define C2H_SUB_CMD_ID_PSD_ACK 0X01\n#define C2H_SUB_CMD_ID_FW_MEM_DUMP_ACK 0X01\n#define C2H_SUB_CMD_ID_PSD_DATA 0X04\n#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05\n#define C2H_SUB_CMD_ID_IQK_DATA 0X06\n#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07\n#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08\n#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09\n#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A\n#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B\n#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C\n#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D\n#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E\n#define C2H_SUB_CMD_ID_CCX_RPT 0X0F\n#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10\n#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11\n#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C\n#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D\n#define C2H_SUB_CMD_ID_FW_DBG_MSG 0XFF\n#define C2H_SUB_CMD_ID_FW_SNDING_ACK 0X01\n#define C2H_SUB_CMD_ID_FW_FWCTRL_RPT 0X1F\n#define C2H_SUB_CMD_ID_H2C_LOOPBACK_ACK 0X20\n#define C2H_SUB_CMD_ID_FWCMD_LOOPBACK_ACK 0X21\n#define C2H_SUB_CMD_ID_SCAN_CH_NOTIFY 0X22\n#define C2H_SUB_CMD_ID_FW_TBTT_RPT 0X23\n#define C2H_SUB_CMD_ID_BCN_OFFLOAD 0X24\n#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM\n#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH\n#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX\n#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE\n#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT\n#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK\n#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK\n#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK\n#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK\n#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD\n#define H2C_SUB_CMD_ID_FW_MEM_DUMP_ACK SUB_CMD_ID_FW_MEM_DUMP\n#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT\n#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG\n#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING\n#define H2C_SUB_CMD_ID_FW_FWCTRL_RPT SUB_CMD_ID_FW_FWCTRL_RPT\n#define H2C_SUB_CMD_ID_H2C_LOOPBACK_ACK SUB_CMD_ID_H2C_LOOPBACK\n#define H2C_SUB_CMD_ID_FWCMD_LOOPBACK_ACK SUB_CMD_ID_FWCMD_LOOPBACK\n#define H2C_CMD_ID_CFG_PARAM_ACK 0XFF\n#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF\n#define H2C_CMD_ID_BT_COEX_ACK 0XFF\n#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF\n#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF\n#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF\n#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF\n#define H2C_CMD_ID_IQK_ACK 0XFF\n#define H2C_CMD_ID_PWR_TRK_ACK 0XFF\n#define H2C_CMD_ID_PSD_ACK 0XFF\n#define H2C_CMD_ID_FW_MEM_DUMP_ACK 0XFF\n#define H2C_CMD_ID_CCX_RPT 0XFF\n#define H2C_CMD_ID_FW_DBG_MSG 0XFF\n#define H2C_CMD_ID_FW_SNDING_ACK 0XFF\n#define H2C_CMD_ID_FW_FWCTRL_RPT 0XFF\n#define H2C_CMD_ID_H2C_LOOPBACK_ACK 0XFF\n#define H2C_CMD_ID_FWCMD_LOOPBACK_ACK 0XFF\n#define C2H_HDR_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)\n#define C2H_HDR_SET_CMD_ID(c2h_pkt, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_HDR_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)\n#define C2H_HDR_SET_SEQ(c2h_pkt, value)                                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)\n#define C2H_HDR_SET_C2H_SUB_CMD_ID(c2h_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)\n#define C2H_HDR_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)\n#define C2H_HDR_SET_LEN(c2h_pkt, value)                                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_DBG_GET_DBG_MSG(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)\n#define C2H_DBG_SET_DBG_MSG(c2h_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)\n#define BT_COEX_INFO_GET_DATA_START(c2h_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)\n#define BT_COEX_INFO_SET_DATA_START(c2h_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)\n#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(c2h_pkt)                           \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)\n#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(c2h_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)\n#define SCAN_STATUS_RPT_GET_H2C_SEQ(c2h_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)\n#define SCAN_STATUS_RPT_SET_H2C_SEQ(c2h_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)\n#define SCAN_STATUS_RPT_GET_TSF_0(c2h_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)\n#define SCAN_STATUS_RPT_SET_TSF_0(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)\n#define SCAN_STATUS_RPT_GET_TSF_1(c2h_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)\n#define SCAN_STATUS_RPT_SET_TSF_1(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)\n#define SCAN_STATUS_RPT_GET_TSF_2(c2h_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)\n#define SCAN_STATUS_RPT_SET_TSF_2(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)\n#define SCAN_STATUS_RPT_GET_TSF_3(c2h_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8)\n#define SCAN_STATUS_RPT_SET_TSF_3(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value)\n#define SCAN_STATUS_RPT_GET_TSF_4(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 8)\n#define SCAN_STATUS_RPT_SET_TSF_4(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 8, value)\n#define SCAN_STATUS_RPT_GET_TSF_5(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 8, 8)\n#define SCAN_STATUS_RPT_SET_TSF_5(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 8, 8, value)\n#define SCAN_STATUS_RPT_GET_TSF_6(c2h_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0XC, 16, 8)\n#define SCAN_STATUS_RPT_SET_TSF_6(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 16, 8, value)\n#define SCAN_STATUS_RPT_GET_TSF_7(c2h_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0XC, 24, 8)\n#define SCAN_STATUS_RPT_SET_TSF_7(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 24, 8, value)\n#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_pkt)                               \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)\n#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(c2h_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)\n#define H2C_ACK_HDR_GET_H2C_CMD_ID(c2h_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)\n#define H2C_ACK_HDR_SET_H2C_CMD_ID(c2h_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)\n#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(c2h_pkt)                                \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)\n#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(c2h_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)\n#define H2C_ACK_HDR_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 16)\n#define H2C_ACK_HDR_SET_H2C_SEQ(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 16, value)\n#define CFG_PARAM_ACK_GET_OFFSET_ACCUMULATION(c2h_pkt)                         \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 32)\n#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION(c2h_pkt, value)                  \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 32, value)\n#define CFG_PARAM_ACK_GET_VALUE_ACCUMULATION(c2h_pkt)                          \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X10, 0, 32)\n#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION(c2h_pkt, value)                   \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 0, 32, value)\n#define CH_SWITCH_ACK_GET_TSF_0(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8)\n#define CH_SWITCH_ACK_SET_TSF_0(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value)\n#define CH_SWITCH_ACK_GET_TSF_1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8)\n#define CH_SWITCH_ACK_SET_TSF_1(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value)\n#define CH_SWITCH_ACK_GET_TSF_2(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)\n#define CH_SWITCH_ACK_SET_TSF_2(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)\n#define CH_SWITCH_ACK_GET_TSF_3(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)\n#define CH_SWITCH_ACK_SET_TSF_3(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)\n#define CH_SWITCH_ACK_GET_TSF_4(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 0, 8)\n#define CH_SWITCH_ACK_SET_TSF_4(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 0, 8, value)\n#define CH_SWITCH_ACK_GET_TSF_5(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 8, 8)\n#define CH_SWITCH_ACK_SET_TSF_5(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 8, 8, value)\n#define CH_SWITCH_ACK_GET_TSF_6(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 16, 8)\n#define CH_SWITCH_ACK_SET_TSF_6(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 16, 8, value)\n#define CH_SWITCH_ACK_GET_TSF_7(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 24, 8)\n#define CH_SWITCH_ACK_SET_TSF_7(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 24, 8, value)\n#define BT_COEX_ACK_GET_DATA_START(c2h_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 8)\n#define BT_COEX_ACK_SET_DATA_START(c2h_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 8, value)\n#define PSD_DATA_GET_SEGMENT_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7)\n#define PSD_DATA_SET_SEGMENT_ID(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value)\n#define PSD_DATA_GET_END_SEGMENT(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1)\n#define PSD_DATA_SET_END_SEGMENT(c2h_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value)\n#define PSD_DATA_GET_SEGMENT_SIZE(c2h_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)\n#define PSD_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)\n#define PSD_DATA_GET_TOTAL_SIZE(c2h_pkt)                                       \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)\n#define PSD_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)\n#define PSD_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16)\n#define PSD_DATA_SET_H2C_SEQ(c2h_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value)\n#define PSD_DATA_GET_DATA_START(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)\n#define PSD_DATA_SET_DATA_START(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)\n#define EFUSE_DATA_GET_SEGMENT_ID(c2h_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7)\n#define EFUSE_DATA_SET_SEGMENT_ID(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value)\n#define EFUSE_DATA_GET_END_SEGMENT(c2h_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1)\n#define EFUSE_DATA_SET_END_SEGMENT(c2h_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value)\n#define EFUSE_DATA_GET_SEGMENT_SIZE(c2h_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)\n#define EFUSE_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)\n#define EFUSE_DATA_GET_TOTAL_SIZE(c2h_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)\n#define EFUSE_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)\n#define EFUSE_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16)\n#define EFUSE_DATA_SET_H2C_SEQ(c2h_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value)\n#define EFUSE_DATA_GET_DATA_START(c2h_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)\n#define EFUSE_DATA_SET_DATA_START(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)\n#define IQK_DATA_GET_SEGMENT_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7)\n#define IQK_DATA_SET_SEGMENT_ID(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value)\n#define IQK_DATA_GET_END_SEGMENT(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1)\n#define IQK_DATA_SET_END_SEGMENT(c2h_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value)\n#define IQK_DATA_GET_SEGMENT_SIZE(c2h_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)\n#define IQK_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)\n#define IQK_DATA_GET_TOTAL_SIZE(c2h_pkt)                                       \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)\n#define IQK_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)\n#define IQK_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16)\n#define IQK_DATA_SET_H2C_SEQ(c2h_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value)\n#define IQK_DATA_GET_DATA_START(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)\n#define IQK_DATA_SET_DATA_START(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)\n#define CCX_RPT_GET_POLLUTED(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 0, 1)\n#define CCX_RPT_SET_POLLUTED(c2h_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 0, 1, value)\n#define CCX_RPT_GET_RPT_SEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 5, 3)\n#define CCX_RPT_SET_RPT_SEL(c2h_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 5, 3, value)\n#define CCX_RPT_GET_QSEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 8, 5)\n#define CCX_RPT_SET_QSEL(c2h_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 8, 5, value)\n#define CCX_RPT_GET_MISSED_RPT_NUM(c2h_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X4, 13, 3)\n#define CCX_RPT_SET_MISSED_RPT_NUM(c2h_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 13, 3, value)\n#define CCX_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 16, 7)\n#define CCX_RPT_SET_MACID(c2h_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 16, 7, value)\n#define CCX_RPT_GET_INITIAL_DATA_RATE(c2h_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X4, 24, 7)\n#define CCX_RPT_SET_INITIAL_DATA_RATE(c2h_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 24, 7, value)\n#define CCX_RPT_GET_INITIAL_SGI(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 31, 1)\n#define CCX_RPT_SET_INITIAL_SGI(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 31, 1, value)\n#define CCX_RPT_GET_QUEUE_TIME(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16)\n#define CCX_RPT_SET_QUEUE_TIME(c2h_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value)\n#define CCX_RPT_GET_SW_DEFINE_BYTE0(c2h_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)\n#define CCX_RPT_SET_SW_DEFINE_BYTE0(c2h_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)\n#define CCX_RPT_GET_RTS_RETRY_COUNT(c2h_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 4)\n#define CCX_RPT_SET_RTS_RETRY_COUNT(c2h_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 4, value)\n#define CCX_RPT_GET_BMC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 29, 1)\n#define CCX_RPT_SET_BMC(c2h_pkt, value)                                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 29, 1, value)\n#define CCX_RPT_GET_TX_STATE(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 30, 2)\n#define CCX_RPT_SET_TX_STATE(c2h_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 30, 2, value)\n#define CCX_RPT_GET_DATA_RETRY_COUNT(c2h_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 6)\n#define CCX_RPT_SET_DATA_RETRY_COUNT(c2h_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 6, value)\n#define CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0XC, 8, 7)\n#define CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 8, 7, value)\n#define CCX_RPT_GET_FINAL_SGI(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 15, 1)\n#define CCX_RPT_SET_FINAL_SGI(c2h_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 15, 1, value)\n#define CCX_RPT_GET_RF_CH_NUM(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 16, 10)\n#define CCX_RPT_SET_RF_CH_NUM(c2h_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 16, 10, value)\n#define CCX_RPT_GET_SC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 26, 4)\n#define CCX_RPT_SET_SC(c2h_pkt, value)                                         \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 26, 4, value)\n#define CCX_RPT_GET_BW(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 30, 2)\n#define CCX_RPT_SET_BW(c2h_pkt, value)                                         \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 30, 2, value)\n#define FW_DBG_MSG_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)\n#define FW_DBG_MSG_SET_CMD_ID(c2h_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)\n#define FW_DBG_MSG_GET_C2H_SUB_CMD_ID(c2h_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)\n#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID(c2h_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)\n#define FW_DBG_MSG_GET_FULL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 1)\n#define FW_DBG_MSG_SET_FULL(c2h_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 1, value)\n#define FW_DBG_MSG_GET_OWN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 31, 1)\n#define FW_DBG_MSG_SET_OWN(c2h_pkt, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 31, 1, value)\n#define FW_FWCTRL_RPT_GET_EVT_TYPE(c2h_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)\n#define FW_FWCTRL_RPT_SET_EVT_TYPE(c2h_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)\n#define FW_FWCTRL_RPT_GET_LENGTH(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)\n#define FW_FWCTRL_RPT_SET_LENGTH(c2h_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)\n#define FW_FWCTRL_RPT_GET_SEQ_NUM(c2h_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)\n#define FW_FWCTRL_RPT_SET_SEQ_NUM(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)\n#define FW_FWCTRL_RPT_GET_IS_ACK(c2h_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 1)\n#define FW_FWCTRL_RPT_SET_IS_ACK(c2h_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 1, value)\n#define FW_FWCTRL_RPT_GET_MORE_CONTENT(c2h_pkt)                                \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 25, 1)\n#define FW_FWCTRL_RPT_SET_MORE_CONTENT(c2h_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 25, 1, value)\n#define FW_FWCTRL_RPT_GET_CONTENT_IDX(c2h_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 26, 6)\n#define FW_FWCTRL_RPT_SET_CONTENT_IDX(c2h_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 26, 6, value)\n#define FW_FWCTRL_RPT_GET_CLASS_ID(c2h_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)\n#define FW_FWCTRL_RPT_SET_CLASS_ID(c2h_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)\n#define FW_FWCTRL_RPT_GET_CONTENT(c2h_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)\n#define FW_FWCTRL_RPT_SET_CONTENT(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)\n#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt)                               \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)\n#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt)                               \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)\n#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt)                               \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)\n#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt)                               \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)\n#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt)                               \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 8)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 8, value)\n#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt)                               \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X8, 8, 8)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 8, 8, value)\n#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt)                               \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)\n#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt)                               \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 8)\n#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 8, value)\n#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt)                             \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)\n#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt)                             \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)\n#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt)                             \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)\n#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt)                             \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)\n#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt)                             \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 8)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 8, value)\n#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt)                             \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X8, 8, 8)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 8, 8, value)\n#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt)                             \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)\n#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt)                             \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 8)\n#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 8, value)\n#define SCAN_CH_NOTIFY_GET_CH_NUM(c2h_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)\n#define SCAN_CH_NOTIFY_SET_CH_NUM(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)\n#define SCAN_CH_NOTIFY_GET_NOTIFY_ID(c2h_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)\n#define SCAN_CH_NOTIFY_SET_NOTIFY_ID(c2h_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)\n#define SCAN_CH_NOTIFY_GET_STATUS(c2h_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)\n#define SCAN_CH_NOTIFY_SET_STATUS(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)\n#define SCAN_CH_NOTIFY_GET_TSF_0(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)\n#define SCAN_CH_NOTIFY_SET_TSF_0(c2h_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)\n#define SCAN_CH_NOTIFY_GET_TSF_1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)\n#define SCAN_CH_NOTIFY_SET_TSF_1(c2h_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)\n#define SCAN_CH_NOTIFY_GET_TSF_2(c2h_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)\n#define SCAN_CH_NOTIFY_SET_TSF_2(c2h_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)\n#define SCAN_CH_NOTIFY_GET_TSF_3(c2h_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8)\n#define SCAN_CH_NOTIFY_SET_TSF_3(c2h_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value)\n#define SCAN_CH_NOTIFY_GET_TSF_4(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8)\n#define SCAN_CH_NOTIFY_SET_TSF_4(c2h_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value)\n#define SCAN_CH_NOTIFY_GET_TSF_5(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8)\n#define SCAN_CH_NOTIFY_SET_TSF_5(c2h_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value)\n#define SCAN_CH_NOTIFY_GET_TSF_6(c2h_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)\n#define SCAN_CH_NOTIFY_SET_TSF_6(c2h_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)\n#define SCAN_CH_NOTIFY_GET_TSF_7(c2h_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)\n#define SCAN_CH_NOTIFY_SET_TSF_7(c2h_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)\n#define FW_TBTT_RPT_GET_PORT_NUMBER(c2h_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)\n#define FW_TBTT_RPT_SET_PORT_NUMBER(c2h_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)\n#define BCN_OFFLOAD_GET_SUPPORT_VER(c2h_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)\n#define BCN_OFFLOAD_SET_SUPPORT_VER(c2h_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)\n#define BCN_OFFLOAD_GET_STATUS(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)\n#define BCN_OFFLOAD_SET_STATUS(c2h_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_fw_offload_h2c_ap.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_\n#define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_\n#define CMD_ID_FW_OFFLOAD_H2C 0XFF\n#define CMD_ID_FW_ACCESS_TEST 0XFF\n#define CMD_ID_CH_SWITCH 0XFF\n#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF\n#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF\n#define CMD_ID_CFG_PARAM 0XFF\n#define CMD_ID_UPDATE_DATAPACK 0XFF\n#define CMD_ID_RUN_DATAPACK 0XFF\n#define CMD_ID_DOWNLOAD_FLASH 0XFF\n#define CMD_ID_UPDATE_PKT 0XFF\n#define CMD_ID_GENERAL_INFO 0XFF\n#define CMD_ID_IQK 0XFF\n#define CMD_ID_PWR_TRK 0XFF\n#define CMD_ID_PSD 0XFF\n#define CMD_ID_PHYDM_INFO 0XFF\n#define CMD_ID_FW_SNDING 0XFF\n#define CMD_ID_FW_FWCTRL 0XFF\n#define CMD_ID_H2C_LOOPBACK 0XFF\n#define CMD_ID_FWCMD_LOOPBACK 0XFF\n#define CMD_ID_UPDATE_SCAN_PKT 0XFF\n#define CMD_ID_BCN_OFFLOAD 0XFF\n#define CMD_ID_P2PPS 0XFF\n#define CMD_ID_BT_COEX 0XFF\n#define CMD_ID_NAN_CTRL 0XFF\n#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF\n#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF\n#define CATEGORY_H2C_CMD_HEADER 0X00\n#define CATEGORY_FW_OFFLOAD_H2C 0X01\n#define CATEGORY_FW_ACCESS_TEST 0X01\n#define CATEGORY_CH_SWITCH 0X01\n#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01\n#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01\n#define CATEGORY_CFG_PARAM 0X01\n#define CATEGORY_UPDATE_DATAPACK 0X01\n#define CATEGORY_RUN_DATAPACK 0X01\n#define CATEGORY_DOWNLOAD_FLASH 0X01\n#define CATEGORY_UPDATE_PKT 0X01\n#define CATEGORY_GENERAL_INFO 0X01\n#define CATEGORY_IQK 0X01\n#define CATEGORY_PWR_TRK 0X01\n#define CATEGORY_PSD 0X01\n#define CATEGORY_PHYDM_INFO 0X01\n#define CATEGORY_FW_SNDING 0X01\n#define CATEGORY_FW_FWCTRL 0X01\n#define CATEGORY_H2C_LOOPBACK 0X01\n#define CATEGORY_FWCMD_LOOPBACK 0X01\n#define CATEGORY_UPDATE_SCAN_PKT 0X01\n#define CATEGORY_BCN_OFFLOAD 0X01\n#define CATEGORY_P2PPS 0X01\n#define CATEGORY_BT_COEX 0X01\n#define CATEGORY_NAN_CTRL 0X01\n#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01\n#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01\n#define SUB_CMD_ID_FW_ACCESS_TEST 0X00\n#define SUB_CMD_ID_CH_SWITCH 0X02\n#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03\n#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05\n#define SUB_CMD_ID_CFG_PARAM 0X08\n#define SUB_CMD_ID_UPDATE_DATAPACK 0X09\n#define SUB_CMD_ID_RUN_DATAPACK 0X0A\n#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B\n#define SUB_CMD_ID_UPDATE_PKT 0X0C\n#define SUB_CMD_ID_GENERAL_INFO 0X0D\n#define SUB_CMD_ID_IQK 0X0E\n#define SUB_CMD_ID_PWR_TRK 0X0F\n#define SUB_CMD_ID_PSD 0X10\n#define SUB_CMD_ID_PHYDM_INFO 0X11\n#define SUB_CMD_ID_FW_SNDING 0X12\n#define SUB_CMD_ID_FW_FWCTRL 0X13\n#define SUB_CMD_ID_H2C_LOOPBACK 0X14\n#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15\n#define SUB_CMD_ID_UPDATE_SCAN_PKT 0X16\n#define SUB_CMD_ID_BCN_OFFLOAD 0X17\n#define SUB_CMD_ID_P2PPS 0X24\n#define SUB_CMD_ID_BT_COEX 0X60\n#define SUB_CMD_ID_NAN_CTRL 0XB2\n#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4\n#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5\n#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 7)\n#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 7, value)\n#define H2C_CMD_HEADER_SET_CATEGORY_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 7, value)\n#define H2C_CMD_HEADER_GET_ACK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 7, 1)\n#define H2C_CMD_HEADER_SET_ACK(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 7, 1, value)\n#define H2C_CMD_HEADER_SET_ACK_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 7, 1, value)\n#define H2C_CMD_HEADER_GET_TOTAL_LEN(h2c_pkt)                                  \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 0, 16)\n#define H2C_CMD_HEADER_SET_TOTAL_LEN(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 16, value)\n#define H2C_CMD_HEADER_SET_TOTAL_LEN_NO_CLR(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 16, value)\n#define H2C_CMD_HEADER_GET_SEQ_NUM(h2c_pkt)                                    \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 16, 16)\n#define H2C_CMD_HEADER_SET_SEQ_NUM(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 16, value)\n#define H2C_CMD_HEADER_SET_SEQ_NUM_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 16, value)\n#define FW_OFFLOAD_H2C_GET_CATEGORY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 7)\n#define FW_OFFLOAD_H2C_SET_CATEGORY(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 7, value)\n#define FW_OFFLOAD_H2C_SET_CATEGORY_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 7, value)\n#define FW_OFFLOAD_H2C_GET_ACK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 7, 1)\n#define FW_OFFLOAD_H2C_SET_ACK(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 7, 1, value)\n#define FW_OFFLOAD_H2C_SET_ACK_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 7, 1, value)\n#define FW_OFFLOAD_H2C_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define FW_OFFLOAD_H2C_SET_CMD_ID(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define FW_OFFLOAD_H2C_SET_CMD_ID_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(h2c_pkt)                                 \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 16)\n#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 16, value)\n#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID_NO_CLR(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 16, value)\n#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(h2c_pkt)                                  \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 0, 16)\n#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 16, value)\n#define FW_OFFLOAD_H2C_SET_TOTAL_LEN_NO_CLR(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 16, value)\n#define FW_OFFLOAD_H2C_GET_SEQ_NUM(h2c_pkt)                                    \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 16, 16)\n#define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 16, value)\n#define FW_OFFLOAD_H2C_SET_SEQ_NUM_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 16, value)\n#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_TXFF_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_RXFF_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_FWFF_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_PHYFF_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt)                             \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 4, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF_NO_CLR(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt)                                 \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 5, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_CAM_NO_CLR(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt)                             \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 6, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 6, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM_NO_CLR(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 6, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt)                              \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 7, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 7, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM_NO_CLR(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 7, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt)                              \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 8, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM_NO_CLR(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt)                          \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 9, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM_NO_CLR(h2c_pkt, value)            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 16, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE0_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 17, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 17, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE1_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 17, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 18, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 18, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE2_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 18, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 19, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 19, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE3_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 19, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 20, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 20, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE4_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 20, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 21, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 21, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE5_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 21, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 22, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 22, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE6_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 22, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 23, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 23, 1, value)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE7_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 23, 1, value)\n#define CH_SWITCH_GET_START(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)\n#define CH_SWITCH_SET_START(h2c_pkt, value)                                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)\n#define CH_SWITCH_SET_START_NO_CLR(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)\n#define CH_SWITCH_GET_DEST_CH_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)\n#define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)\n#define CH_SWITCH_SET_DEST_CH_EN_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)\n#define CH_SWITCH_GET_ABSOLUTE_TIME(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)\n#define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)\n#define CH_SWITCH_SET_ABSOLUTE_TIME_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)\n#define CH_SWITCH_GET_PERIODIC_OPT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 2)\n#define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 2, value)\n#define CH_SWITCH_SET_PERIODIC_OPT_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 2, value)\n#define CH_SWITCH_GET_SCAN_MODE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1)\n#define CH_SWITCH_SET_SCAN_MODE(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value)\n#define CH_SWITCH_SET_SCAN_MODE_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value)\n#define CH_SWITCH_GET_INFO_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)\n#define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)\n#define CH_SWITCH_SET_INFO_LOC_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)\n#define CH_SWITCH_GET_CH_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)\n#define CH_SWITCH_SET_CH_NUM(h2c_pkt, value)                                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define CH_SWITCH_SET_CH_NUM_NO_CLR(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define CH_SWITCH_GET_PRI_CH_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 4)\n#define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 4, value)\n#define CH_SWITCH_SET_PRI_CH_IDX_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 4, value)\n#define CH_SWITCH_GET_DEST_BW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 28, 4)\n#define CH_SWITCH_SET_DEST_BW(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 28, 4, value)\n#define CH_SWITCH_SET_DEST_BW_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 28, 4, value)\n#define CH_SWITCH_GET_DEST_CH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)\n#define CH_SWITCH_SET_DEST_CH(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)\n#define CH_SWITCH_SET_DEST_CH_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)\n#define CH_SWITCH_GET_NORMAL_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 6)\n#define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 6, value)\n#define CH_SWITCH_SET_NORMAL_PERIOD_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 6, value)\n#define CH_SWITCH_GET_NORMAL_PERIOD_SEL(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X0C, 14, 2)\n#define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 14, 2, value)\n#define CH_SWITCH_SET_NORMAL_PERIOD_SEL_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 14, 2, value)\n#define CH_SWITCH_GET_SLOW_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 6)\n#define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 6, value)\n#define CH_SWITCH_SET_SLOW_PERIOD_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 6, value)\n#define CH_SWITCH_GET_SLOW_PERIOD_SEL(h2c_pkt)                                 \\\n\tGET_H2C_FIELD(h2c_pkt + 0X0C, 22, 2)\n#define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 22, 2, value)\n#define CH_SWITCH_SET_SLOW_PERIOD_SEL_NO_CLR(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 22, 2, value)\n#define CH_SWITCH_GET_NORMAL_CYCLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 24, 8)\n#define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 24, 8, value)\n#define CH_SWITCH_SET_NORMAL_CYCLE_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 24, 8, value)\n#define CH_SWITCH_GET_TSF_HIGH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32)\n#define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value)\n#define CH_SWITCH_SET_TSF_HIGH_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value)\n#define CH_SWITCH_GET_TSF_LOW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 0, 32)\n#define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value)\n#define CH_SWITCH_SET_TSF_LOW_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value)\n#define CH_SWITCH_GET_INFO_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 0, 16)\n#define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 16, value)\n#define CH_SWITCH_SET_INFO_SIZE_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 16, value)\n#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)\n#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)\n#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)\n#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 8, 4)\n#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 4, value)\n#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 4, value)\n#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 12, 4)\n#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 12, 4, value)\n#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 12, 4, value)\n#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(h2c_pkt)                    \\\n\tGET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32)\n#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value)\n#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0_NO_CLR(h2c_pkt, value)      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value)\n#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(h2c_pkt)                    \\\n\tGET_H2C_FIELD(h2c_pkt + 0X10, 0, 32)\n#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value)\n#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1_NO_CLR(h2c_pkt, value)      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value)\n#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(h2c_pkt)                    \\\n\tGET_H2C_FIELD(h2c_pkt + 0X14, 0, 32)\n#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value)\n#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2_NO_CLR(h2c_pkt, value)      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value)\n#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(h2c_pkt)                    \\\n\tGET_H2C_FIELD(h2c_pkt + 0X18, 0, 32)\n#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 32, value)\n#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3_NO_CLR(h2c_pkt, value)      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 32, value)\n#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(h2c_pkt)                    \\\n\tGET_H2C_FIELD(h2c_pkt + 0X1C, 0, 32)\n#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 32, value)\n#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4_NO_CLR(h2c_pkt, value)      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 32, value)\n#define CFG_PARAM_GET_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)\n#define CFG_PARAM_SET_NUM(h2c_pkt, value)                                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)\n#define CFG_PARAM_SET_NUM_NO_CLR(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)\n#define CFG_PARAM_GET_INIT_CASE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 1)\n#define CFG_PARAM_SET_INIT_CASE(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 1, value)\n#define CFG_PARAM_SET_INIT_CASE_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 1, value)\n#define CFG_PARAM_GET_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)\n#define CFG_PARAM_SET_LOC(h2c_pkt, value)                                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)\n#define CFG_PARAM_SET_LOC_NO_CLR(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)\n#define UPDATE_DATAPACK_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)\n#define UPDATE_DATAPACK_SET_SIZE(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)\n#define UPDATE_DATAPACK_SET_SIZE_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)\n#define UPDATE_DATAPACK_GET_DATAPACK_ID(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)\n#define UPDATE_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define UPDATE_DATAPACK_SET_DATAPACK_ID_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define UPDATE_DATAPACK_GET_DATAPACK_LOC(h2c_pkt)                              \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)\n#define UPDATE_DATAPACK_SET_DATAPACK_LOC(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)\n#define UPDATE_DATAPACK_SET_DATAPACK_LOC_NO_CLR(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)\n#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(h2c_pkt)                          \\\n\tGET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)\n#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)\n#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT_NO_CLR(h2c_pkt, value)            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)\n#define UPDATE_DATAPACK_GET_END_SEGMENT(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X0C, 8, 1)\n#define UPDATE_DATAPACK_SET_END_SEGMENT(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 1, value)\n#define UPDATE_DATAPACK_SET_END_SEGMENT_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 1, value)\n#define RUN_DATAPACK_GET_DATAPACK_ID(h2c_pkt)                                  \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)\n#define RUN_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)\n#define RUN_DATAPACK_SET_DATAPACK_ID_NO_CLR(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)\n#define DOWNLOAD_FLASH_GET_SPI_CMD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)\n#define DOWNLOAD_FLASH_SET_SPI_CMD(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)\n#define DOWNLOAD_FLASH_SET_SPI_CMD_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)\n#define DOWNLOAD_FLASH_GET_LOCATION(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 8, 16)\n#define DOWNLOAD_FLASH_SET_LOCATION(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 16, value)\n#define DOWNLOAD_FLASH_SET_LOCATION_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 16, value)\n#define DOWNLOAD_FLASH_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32)\n#define DOWNLOAD_FLASH_SET_SIZE(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value)\n#define DOWNLOAD_FLASH_SET_SIZE_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value)\n#define DOWNLOAD_FLASH_GET_START_ADDR(h2c_pkt)                                 \\\n\tGET_H2C_FIELD(h2c_pkt + 0X10, 0, 32)\n#define DOWNLOAD_FLASH_SET_START_ADDR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value)\n#define DOWNLOAD_FLASH_SET_START_ADDR_NO_CLR(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value)\n#define UPDATE_PKT_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)\n#define UPDATE_PKT_SET_SIZE(h2c_pkt, value)                                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)\n#define UPDATE_PKT_SET_SIZE_NO_CLR(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)\n#define UPDATE_PKT_GET_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)\n#define UPDATE_PKT_SET_ID(h2c_pkt, value)                                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define UPDATE_PKT_SET_ID_NO_CLR(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define UPDATE_PKT_GET_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)\n#define UPDATE_PKT_SET_LOC(h2c_pkt, value)                                     \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)\n#define UPDATE_PKT_SET_LOC_NO_CLR(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)\n#define GENERAL_INFO_GET_FW_TX_BOUNDARY(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)\n#define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define GENERAL_INFO_SET_FW_TX_BOUNDARY_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define IQK_GET_CLEAR(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)\n#define IQK_SET_CLEAR(h2c_pkt, value)                                          \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)\n#define IQK_SET_CLEAR_NO_CLR(h2c_pkt, value)                                   \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)\n#define IQK_GET_SEGMENT_IQK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)\n#define IQK_SET_SEGMENT_IQK(h2c_pkt, value)                                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)\n#define IQK_SET_SEGMENT_IQK_NO_CLR(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)\n#define PWR_TRK_GET_ENABLE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)\n#define PWR_TRK_SET_ENABLE_A(h2c_pkt, value)                                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)\n#define PWR_TRK_SET_ENABLE_A_NO_CLR(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)\n#define PWR_TRK_GET_ENABLE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)\n#define PWR_TRK_SET_ENABLE_B(h2c_pkt, value)                                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)\n#define PWR_TRK_SET_ENABLE_B_NO_CLR(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)\n#define PWR_TRK_GET_ENABLE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)\n#define PWR_TRK_SET_ENABLE_C(h2c_pkt, value)                                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)\n#define PWR_TRK_SET_ENABLE_C_NO_CLR(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)\n#define PWR_TRK_GET_ENABLE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)\n#define PWR_TRK_SET_ENABLE_D(h2c_pkt, value)                                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)\n#define PWR_TRK_SET_ENABLE_D_NO_CLR(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)\n#define PWR_TRK_GET_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 4, 3)\n#define PWR_TRK_SET_TYPE(h2c_pkt, value)                                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 3, value)\n#define PWR_TRK_SET_TYPE_NO_CLR(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 3, value)\n#define PWR_TRK_GET_BBSWING_INDEX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)\n#define PWR_TRK_SET_BBSWING_INDEX(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)\n#define PWR_TRK_SET_BBSWING_INDEX_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)\n#define PWR_TRK_GET_TX_PWR_INDEX_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)\n#define PWR_TRK_SET_TX_PWR_INDEX_A(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)\n#define PWR_TRK_SET_TX_PWR_INDEX_A_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)\n#define PWR_TRK_GET_OFFSET_VALUE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 8)\n#define PWR_TRK_SET_OFFSET_VALUE_A(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 8, value)\n#define PWR_TRK_SET_OFFSET_VALUE_A_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 8, value)\n#define PWR_TRK_GET_TSSI_VALUE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 8)\n#define PWR_TRK_SET_TSSI_VALUE_A(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 8, value)\n#define PWR_TRK_SET_TSSI_VALUE_A_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 8, value)\n#define PWR_TRK_GET_TX_PWR_INDEX_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 0, 8)\n#define PWR_TRK_SET_TX_PWR_INDEX_B(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value)\n#define PWR_TRK_SET_TX_PWR_INDEX_B_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value)\n#define PWR_TRK_GET_OFFSET_VALUE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 8, 8)\n#define PWR_TRK_SET_OFFSET_VALUE_B(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value)\n#define PWR_TRK_SET_OFFSET_VALUE_B_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value)\n#define PWR_TRK_GET_TSSI_VALUE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 16, 8)\n#define PWR_TRK_SET_TSSI_VALUE_B(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X10, 16, 8, value)\n#define PWR_TRK_SET_TSSI_VALUE_B_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 16, 8, value)\n#define PWR_TRK_GET_TX_PWR_INDEX_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 0, 8)\n#define PWR_TRK_SET_TX_PWR_INDEX_C(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 8, value)\n#define PWR_TRK_SET_TX_PWR_INDEX_C_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 8, value)\n#define PWR_TRK_GET_OFFSET_VALUE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 8, 8)\n#define PWR_TRK_SET_OFFSET_VALUE_C(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X14, 8, 8, value)\n#define PWR_TRK_SET_OFFSET_VALUE_C_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 8, 8, value)\n#define PWR_TRK_GET_TSSI_VALUE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 16, 8)\n#define PWR_TRK_SET_TSSI_VALUE_C(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 8, value)\n#define PWR_TRK_SET_TSSI_VALUE_C_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 8, value)\n#define PWR_TRK_GET_TX_PWR_INDEX_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 0, 8)\n#define PWR_TRK_SET_TX_PWR_INDEX_D(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value)\n#define PWR_TRK_SET_TX_PWR_INDEX_D_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value)\n#define PWR_TRK_GET_OFFSET_VALUE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 8, 8)\n#define PWR_TRK_SET_OFFSET_VALUE_D(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value)\n#define PWR_TRK_SET_OFFSET_VALUE_D_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value)\n#define PWR_TRK_GET_TSSI_VALUE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 16, 8)\n#define PWR_TRK_SET_TSSI_VALUE_D(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X18, 16, 8, value)\n#define PWR_TRK_SET_TSSI_VALUE_D_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 16, 8, value)\n#define PSD_GET_START_PSD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)\n#define PSD_SET_START_PSD(h2c_pkt, value)                                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)\n#define PSD_SET_START_PSD_NO_CLR(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)\n#define PSD_GET_END_PSD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 16)\n#define PSD_SET_END_PSD(h2c_pkt, value)                                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 16, value)\n#define PSD_SET_END_PSD_NO_CLR(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 16, value)\n#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)\n#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)\n#define PHYDM_INFO_SET_REF_TYPE_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)\n#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)\n#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)\n#define PHYDM_INFO_SET_RF_TYPE_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)\n#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)\n#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define PHYDM_INFO_SET_CUT_VER_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt)                                  \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 24, 4)\n#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 4, value)\n#define PHYDM_INFO_SET_RX_ANT_STATUS_NO_CLR(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 4, value)\n#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt)                                  \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 28, 4)\n#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 28, 4, value)\n#define PHYDM_INFO_SET_TX_ANT_STATUS_NO_CLR(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 28, 4, value)\n#define FW_SNDING_GET_SU0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)\n#define FW_SNDING_SET_SU0(h2c_pkt, value)                                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)\n#define FW_SNDING_SET_SU0_NO_CLR(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)\n#define FW_SNDING_GET_SU1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)\n#define FW_SNDING_SET_SU1(h2c_pkt, value)                                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)\n#define FW_SNDING_SET_SU1_NO_CLR(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)\n#define FW_SNDING_GET_MU(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)\n#define FW_SNDING_SET_MU(h2c_pkt, value)                                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)\n#define FW_SNDING_SET_MU_NO_CLR(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)\n#define FW_SNDING_GET_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)\n#define FW_SNDING_SET_PERIOD(h2c_pkt, value)                                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)\n#define FW_SNDING_SET_PERIOD_NO_CLR(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)\n#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)\n#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define FW_SNDING_SET_NDPA0_HEAD_PG_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)\n#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)\n#define FW_SNDING_SET_NDPA1_HEAD_PG_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)\n#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt)                                 \\\n\tGET_H2C_FIELD(h2c_pkt + 0XC, 0, 8)\n#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0XC, 0, 8, value)\n#define FW_SNDING_SET_MU_NDPA_HEAD_PG_NO_CLR(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 0, 8, value)\n#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 8, 8)\n#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0XC, 8, 8, value)\n#define FW_SNDING_SET_RPT0_HEAD_PG_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 8, 8, value)\n#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 16, 8)\n#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0XC, 16, 8, value)\n#define FW_SNDING_SET_RPT1_HEAD_PG_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 16, 8, value)\n#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 24, 8)\n#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0XC, 24, 8, value)\n#define FW_SNDING_SET_RPT2_HEAD_PG_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 24, 8, value)\n#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)\n#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)\n#define FW_FWCTRL_SET_SEQ_NUM_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)\n#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1)\n#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value)\n#define FW_FWCTRL_SET_MORE_CONTENT_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value)\n#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 9, 7)\n#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 7, value)\n#define FW_FWCTRL_SET_CONTENT_IDX_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 7, value)\n#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)\n#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define FW_FWCTRL_SET_CLASS_ID_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define FW_FWCTRL_GET_LENGTH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)\n#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value)                                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)\n#define FW_FWCTRL_SET_LENGTH_NO_CLR(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)\n#define FW_FWCTRL_GET_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32)\n#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value)\n#define FW_FWCTRL_SET_CONTENT_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value)\n#define UPDATE_SCAN_PKT_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)\n#define UPDATE_SCAN_PKT_SET_SIZE(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)\n#define UPDATE_SCAN_PKT_SET_SIZE_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)\n#define UPDATE_SCAN_PKT_GET_INDEX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)\n#define UPDATE_SCAN_PKT_SET_INDEX(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define UPDATE_SCAN_PKT_SET_INDEX_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define UPDATE_SCAN_PKT_GET_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)\n#define UPDATE_SCAN_PKT_SET_LOC(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)\n#define UPDATE_SCAN_PKT_SET_LOC_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)\n#define BCN_OFFLOAD_GET_REQUEST_VERSION(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)\n#define BCN_OFFLOAD_SET_REQUEST_VERSION(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)\n#define BCN_OFFLOAD_SET_REQUEST_VERSION_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)\n#define BCN_OFFLOAD_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)\n#define BCN_OFFLOAD_SET_ENABLE(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)\n#define BCN_OFFLOAD_SET_ENABLE_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)\n#define BCN_OFFLOAD_GET_MORE_RULE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)\n#define BCN_OFFLOAD_SET_MORE_RULE(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)\n#define BCN_OFFLOAD_SET_MORE_RULE_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)\n#define BCN_OFFLOAD_GET_C2H_PERIODIC_REPORT(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)\n#define BCN_OFFLOAD_SET_C2H_PERIODIC_REPORT(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)\n#define BCN_OFFLOAD_SET_C2H_PERIODIC_REPORT_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)\n#define BCN_OFFLOAD_GET_REPORT_PERIOD(h2c_pkt)                                 \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)\n#define BCN_OFFLOAD_SET_REPORT_PERIOD(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)\n#define BCN_OFFLOAD_SET_REPORT_PERIOD_NO_CLR(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)\n#define BCN_OFFLOAD_GET_RULE_LENGTH(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)\n#define BCN_OFFLOAD_SET_RULE_LENGTH(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define BCN_OFFLOAD_SET_RULE_LENGTH_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define BCN_OFFLOAD_GET_RULE_CONTENT(h2c_pkt)                                  \\\n\tGET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)\n#define BCN_OFFLOAD_SET_RULE_CONTENT(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)\n#define BCN_OFFLOAD_SET_RULE_CONTENT_NO_CLR(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)\n#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)\n#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value)                                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)\n#define P2PPS_SET_OFFLOAD_EN_NO_CLR(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)\n#define P2PPS_GET_ROLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)\n#define P2PPS_SET_ROLE(h2c_pkt, value)                                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)\n#define P2PPS_SET_ROLE_NO_CLR(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)\n#define P2PPS_GET_CTWINDOW_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)\n#define P2PPS_SET_CTWINDOW_EN(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)\n#define P2PPS_SET_CTWINDOW_EN_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)\n#define P2PPS_GET_NOA_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)\n#define P2PPS_SET_NOA_EN(h2c_pkt, value)                                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)\n#define P2PPS_SET_NOA_EN_NO_CLR(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)\n#define P2PPS_GET_NOA_SEL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 4, 1)\n#define P2PPS_SET_NOA_SEL(h2c_pkt, value)                                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 1, value)\n#define P2PPS_SET_NOA_SEL_NO_CLR(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 1, value)\n#define P2PPS_GET_ALLSTASLEEP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1)\n#define P2PPS_SET_ALLSTASLEEP(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value)\n#define P2PPS_SET_ALLSTASLEEP_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value)\n#define P2PPS_GET_DISCOVERY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 6, 1)\n#define P2PPS_SET_DISCOVERY(h2c_pkt, value)                                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 6, 1, value)\n#define P2PPS_SET_DISCOVERY_NO_CLR(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 6, 1, value)\n#define P2PPS_GET_DISABLE_CLOSERF(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 7, 1)\n#define P2PPS_SET_DISABLE_CLOSERF(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 7, 1, value)\n#define P2PPS_SET_DISABLE_CLOSERF_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 7, 1, value)\n#define P2PPS_GET_P2P_PORT_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)\n#define P2PPS_SET_P2P_PORT_ID(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)\n#define P2PPS_SET_P2P_PORT_ID_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)\n#define P2PPS_GET_P2P_GROUP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)\n#define P2PPS_SET_P2P_GROUP(h2c_pkt, value)                                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define P2PPS_SET_P2P_GROUP_NO_CLR(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define P2PPS_GET_P2P_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)\n#define P2PPS_SET_P2P_MACID(h2c_pkt, value)                                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)\n#define P2PPS_SET_P2P_MACID_NO_CLR(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)\n#define P2PPS_GET_CTWINDOW_LENGTH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)\n#define P2PPS_SET_CTWINDOW_LENGTH(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)\n#define P2PPS_SET_CTWINDOW_LENGTH_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)\n#define P2PPS_GET_NOA_DURATION_PARA(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X10, 0, 32)\n#define P2PPS_SET_NOA_DURATION_PARA(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value)\n#define P2PPS_SET_NOA_DURATION_PARA_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value)\n#define P2PPS_GET_NOA_INTERVAL_PARA(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X14, 0, 32)\n#define P2PPS_SET_NOA_INTERVAL_PARA(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value)\n#define P2PPS_SET_NOA_INTERVAL_PARA_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value)\n#define P2PPS_GET_NOA_START_TIME_PARA(h2c_pkt)                                 \\\n\tGET_H2C_FIELD(h2c_pkt + 0X18, 0, 32)\n#define P2PPS_SET_NOA_START_TIME_PARA(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 32, value)\n#define P2PPS_SET_NOA_START_TIME_PARA_NO_CLR(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 32, value)\n#define P2PPS_GET_NOA_COUNT_PARA(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 32)\n#define P2PPS_SET_NOA_COUNT_PARA(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 32, value)\n#define P2PPS_SET_NOA_COUNT_PARA_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 32, value)\n#define BT_COEX_GET_DATA_START(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)\n#define BT_COEX_SET_DATA_START(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)\n#define BT_COEX_SET_DATA_START_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)\n#define NAN_CTRL_GET_NAN_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 2)\n#define NAN_CTRL_SET_NAN_EN(h2c_pkt, value)                                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 2, value)\n#define NAN_CTRL_SET_NAN_EN_NO_CLR(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 2, value)\n#define NAN_CTRL_GET_WARMUP_TIMER_FLAG(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)\n#define NAN_CTRL_SET_WARMUP_TIMER_FLAG(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)\n#define NAN_CTRL_SET_WARMUP_TIMER_FLAG_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)\n#define NAN_CTRL_GET_SUPPORT_BAND(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 2)\n#define NAN_CTRL_SET_SUPPORT_BAND(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 2, value)\n#define NAN_CTRL_SET_SUPPORT_BAND_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 2, value)\n#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(h2c_pkt)                              \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 10, 1)\n#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 10, 1, value)\n#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN_NO_CLR(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 10, 1, value)\n#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(h2c_pkt)                              \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 11, 1)\n#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 11, 1, value)\n#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN_NO_CLR(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 11, 1, value)\n#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(h2c_pkt)                             \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)\n#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET_NO_CLR(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)\n#define NAN_CTRL_GET_CHANNEL_2G(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)\n#define NAN_CTRL_SET_CHANNEL_2G(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)\n#define NAN_CTRL_SET_CHANNEL_2G_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)\n#define NAN_CTRL_GET_CHANNEL_5G(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)\n#define NAN_CTRL_SET_CHANNEL_5G(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)\n#define NAN_CTRL_SET_CHANNEL_5G_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)\n#define NAN_CTRL_GET_MASTERPREFERENCE_VALUE(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X0C, 8, 8)\n#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 8, value)\n#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 8, value)\n#define NAN_CTRL_GET_RANDOMFACTOR_VALUE(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X0C, 16, 8)\n#define NAN_CTRL_SET_RANDOMFACTOR_VALUE(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 8, value)\n#define NAN_CTRL_SET_RANDOMFACTOR_VALUE_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 8, value)\n#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(h2c_pkt)                       \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)\n#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)\n#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0_NO_CLR(h2c_pkt, value)         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)\n#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)\n#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)\n#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)\n#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(h2c_pkt)                      \\\n\tGET_H2C_FIELD(h2c_pkt + 0X0C, 0, 16)\n#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 16, value)\n#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0_NO_CLR(h2c_pkt, value)        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 16, value)\n#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(h2c_pkt)                             \\\n\tGET_H2C_FIELD(h2c_pkt + 0X0C, 16, 16)\n#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 16, value)\n#define NAN_CHANNEL_PLAN_0_SET_DURATION_0_NO_CLR(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 16, value)\n#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(h2c_pkt)                       \\\n\tGET_H2C_FIELD(h2c_pkt + 0X10, 0, 8)\n#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value)\n#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1_NO_CLR(h2c_pkt, value)         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value)\n#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X10, 8, 8)\n#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value)\n#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value)\n#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(h2c_pkt)                      \\\n\tGET_H2C_FIELD(h2c_pkt + 0X14, 0, 16)\n#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 16, value)\n#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1_NO_CLR(h2c_pkt, value)        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 16, value)\n#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(h2c_pkt)                             \\\n\tGET_H2C_FIELD(h2c_pkt + 0X14, 16, 16)\n#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 16, value)\n#define NAN_CHANNEL_PLAN_0_SET_DURATION_1_NO_CLR(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 16, value)\n#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(h2c_pkt)                       \\\n\tGET_H2C_FIELD(h2c_pkt + 0X18, 0, 8)\n#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value)\n#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2_NO_CLR(h2c_pkt, value)         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value)\n#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X18, 8, 8)\n#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value)\n#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value)\n#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(h2c_pkt)                      \\\n\tGET_H2C_FIELD(h2c_pkt + 0X1C, 0, 16)\n#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 16, value)\n#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2_NO_CLR(h2c_pkt, value)        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 16, value)\n#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(h2c_pkt)                             \\\n\tGET_H2C_FIELD(h2c_pkt + 0X1C, 16, 16)\n#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 16, 16, value)\n#define NAN_CHANNEL_PLAN_0_SET_DURATION_2_NO_CLR(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 16, 16, value)\n#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(h2c_pkt)                       \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)\n#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)\n#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3_NO_CLR(h2c_pkt, value)         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)\n#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)\n#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)\n#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)\n#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(h2c_pkt)                      \\\n\tGET_H2C_FIELD(h2c_pkt + 0X0C, 0, 16)\n#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 16, value)\n#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3_NO_CLR(h2c_pkt, value)        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 16, value)\n#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(h2c_pkt)                             \\\n\tGET_H2C_FIELD(h2c_pkt + 0X0C, 16, 16)\n#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 16, value)\n#define NAN_CHANNEL_PLAN_1_SET_DURATION_3_NO_CLR(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 16, value)\n#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(h2c_pkt)                       \\\n\tGET_H2C_FIELD(h2c_pkt + 0X10, 0, 8)\n#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value)\n#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4_NO_CLR(h2c_pkt, value)         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value)\n#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X10, 8, 8)\n#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value)\n#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value)\n#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(h2c_pkt)                      \\\n\tGET_H2C_FIELD(h2c_pkt + 0X14, 0, 16)\n#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 16, value)\n#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4_NO_CLR(h2c_pkt, value)        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 16, value)\n#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(h2c_pkt)                             \\\n\tGET_H2C_FIELD(h2c_pkt + 0X14, 16, 16)\n#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 16, value)\n#define NAN_CHANNEL_PLAN_1_SET_DURATION_4_NO_CLR(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 16, value)\n#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(h2c_pkt)                       \\\n\tGET_H2C_FIELD(h2c_pkt + 0X18, 0, 8)\n#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value)\n#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5_NO_CLR(h2c_pkt, value)         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value)\n#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X18, 8, 8)\n#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value)\n#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value)\n#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(h2c_pkt)                      \\\n\tGET_H2C_FIELD(h2c_pkt + 0X1C, 0, 16)\n#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 16, value)\n#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5_NO_CLR(h2c_pkt, value)        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 16, value)\n#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(h2c_pkt)                             \\\n\tGET_H2C_FIELD(h2c_pkt + 0X1C, 16, 16)\n#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 16, 16, value)\n#define NAN_CHANNEL_PLAN_1_SET_DURATION_5_NO_CLR(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 16, 16, value)\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_fw_offload_h2c_nic.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_\n#define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_\n#define CMD_ID_FW_OFFLOAD_H2C 0XFF\n#define CMD_ID_FW_ACCESS_TEST 0XFF\n#define CMD_ID_CH_SWITCH 0XFF\n#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF\n#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF\n#define CMD_ID_CFG_PARAM 0XFF\n#define CMD_ID_UPDATE_DATAPACK 0XFF\n#define CMD_ID_RUN_DATAPACK 0XFF\n#define CMD_ID_DOWNLOAD_FLASH 0XFF\n#define CMD_ID_UPDATE_PKT 0XFF\n#define CMD_ID_GENERAL_INFO 0XFF\n#define CMD_ID_IQK 0XFF\n#define CMD_ID_PWR_TRK 0XFF\n#define CMD_ID_PSD 0XFF\n#define CMD_ID_PHYDM_INFO 0XFF\n#define CMD_ID_FW_SNDING 0XFF\n#define CMD_ID_FW_FWCTRL 0XFF\n#define CMD_ID_H2C_LOOPBACK 0XFF\n#define CMD_ID_FWCMD_LOOPBACK 0XFF\n#define CMD_ID_UPDATE_SCAN_PKT 0XFF\n#define CMD_ID_BCN_OFFLOAD 0XFF\n#define CMD_ID_P2PPS 0XFF\n#define CMD_ID_BT_COEX 0XFF\n#define CMD_ID_NAN_CTRL 0XFF\n#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF\n#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF\n#define CATEGORY_H2C_CMD_HEADER 0X00\n#define CATEGORY_FW_OFFLOAD_H2C 0X01\n#define CATEGORY_FW_ACCESS_TEST 0X01\n#define CATEGORY_CH_SWITCH 0X01\n#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01\n#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01\n#define CATEGORY_CFG_PARAM 0X01\n#define CATEGORY_UPDATE_DATAPACK 0X01\n#define CATEGORY_RUN_DATAPACK 0X01\n#define CATEGORY_DOWNLOAD_FLASH 0X01\n#define CATEGORY_UPDATE_PKT 0X01\n#define CATEGORY_GENERAL_INFO 0X01\n#define CATEGORY_IQK 0X01\n#define CATEGORY_PWR_TRK 0X01\n#define CATEGORY_PSD 0X01\n#define CATEGORY_PHYDM_INFO 0X01\n#define CATEGORY_FW_SNDING 0X01\n#define CATEGORY_FW_FWCTRL 0X01\n#define CATEGORY_H2C_LOOPBACK 0X01\n#define CATEGORY_FWCMD_LOOPBACK 0X01\n#define CATEGORY_UPDATE_SCAN_PKT 0X01\n#define CATEGORY_BCN_OFFLOAD 0X01\n#define CATEGORY_P2PPS 0X01\n#define CATEGORY_BT_COEX 0X01\n#define CATEGORY_NAN_CTRL 0X01\n#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01\n#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01\n#define SUB_CMD_ID_FW_ACCESS_TEST 0X00\n#define SUB_CMD_ID_CH_SWITCH 0X02\n#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03\n#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05\n#define SUB_CMD_ID_CFG_PARAM 0X08\n#define SUB_CMD_ID_UPDATE_DATAPACK 0X09\n#define SUB_CMD_ID_RUN_DATAPACK 0X0A\n#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B\n#define SUB_CMD_ID_UPDATE_PKT 0X0C\n#define SUB_CMD_ID_GENERAL_INFO 0X0D\n#define SUB_CMD_ID_IQK 0X0E\n#define SUB_CMD_ID_PWR_TRK 0X0F\n#define SUB_CMD_ID_PSD 0X10\n#define SUB_CMD_ID_PHYDM_INFO 0X11\n#define SUB_CMD_ID_FW_SNDING 0X12\n#define SUB_CMD_ID_FW_FWCTRL 0X13\n#define SUB_CMD_ID_H2C_LOOPBACK 0X14\n#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15\n#define SUB_CMD_ID_UPDATE_SCAN_PKT 0X16\n#define SUB_CMD_ID_BCN_OFFLOAD 0X17\n#define SUB_CMD_ID_P2PPS 0X24\n#define SUB_CMD_ID_BT_COEX 0X60\n#define SUB_CMD_ID_NAN_CTRL 0XB2\n#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4\n#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5\n#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 7)\n#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 7, value)\n#define H2C_CMD_HEADER_GET_ACK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 7, 1)\n#define H2C_CMD_HEADER_SET_ACK(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 7, 1, value)\n#define H2C_CMD_HEADER_GET_TOTAL_LEN(h2c_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 16)\n#define H2C_CMD_HEADER_SET_TOTAL_LEN(h2c_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 16, value)\n#define H2C_CMD_HEADER_GET_SEQ_NUM(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 16)\n#define H2C_CMD_HEADER_SET_SEQ_NUM(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 16, value)\n#define FW_OFFLOAD_H2C_GET_CATEGORY(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 7)\n#define FW_OFFLOAD_H2C_SET_CATEGORY(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 7, value)\n#define FW_OFFLOAD_H2C_GET_ACK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 7, 1)\n#define FW_OFFLOAD_H2C_SET_ACK(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 7, 1, value)\n#define FW_OFFLOAD_H2C_GET_CMD_ID(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define FW_OFFLOAD_H2C_SET_CMD_ID(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(h2c_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 16)\n#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(h2c_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 16, value)\n#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(h2c_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 16)\n#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(h2c_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 16, value)\n#define FW_OFFLOAD_H2C_GET_SEQ_NUM(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 16)\n#define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 16, value)\n#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt)                             \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt)                             \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 6, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 6, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt)                              \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 7, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 7, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt)                              \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt)                          \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value)                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 17, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 17, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 18, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 18, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 19, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 19, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 20, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 20, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 21, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 21, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 22, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 22, 1, value)\n#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 23, 1)\n#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 23, 1, value)\n#define CH_SWITCH_GET_START(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)\n#define CH_SWITCH_SET_START(h2c_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)\n#define CH_SWITCH_GET_DEST_CH_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)\n#define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)\n#define CH_SWITCH_GET_ABSOLUTE_TIME(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)\n#define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)\n#define CH_SWITCH_GET_PERIODIC_OPT(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 2)\n#define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 2, value)\n#define CH_SWITCH_GET_SCAN_MODE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1)\n#define CH_SWITCH_SET_SCAN_MODE(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value)\n#define CH_SWITCH_GET_INFO_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)\n#define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)\n#define CH_SWITCH_GET_CH_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)\n#define CH_SWITCH_SET_CH_NUM(h2c_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)\n#define CH_SWITCH_GET_PRI_CH_IDX(h2c_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 4)\n#define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 4, value)\n#define CH_SWITCH_GET_DEST_BW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 28, 4)\n#define CH_SWITCH_SET_DEST_BW(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 28, 4, value)\n#define CH_SWITCH_GET_DEST_CH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)\n#define CH_SWITCH_SET_DEST_CH(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)\n#define CH_SWITCH_GET_NORMAL_PERIOD(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 6)\n#define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 6, value)\n#define CH_SWITCH_GET_NORMAL_PERIOD_SEL(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 14, 2)\n#define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 14, 2, value)\n#define CH_SWITCH_GET_SLOW_PERIOD(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 6)\n#define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 6, value)\n#define CH_SWITCH_GET_SLOW_PERIOD_SEL(h2c_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 22, 2)\n#define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 22, 2, value)\n#define CH_SWITCH_GET_NORMAL_CYCLE(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 24, 8)\n#define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 24, 8, value)\n#define CH_SWITCH_GET_TSF_HIGH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32)\n#define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value)\n#define CH_SWITCH_GET_TSF_LOW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32)\n#define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value)\n#define CH_SWITCH_GET_INFO_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 16)\n#define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 16, value)\n#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)\n#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)\n#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 4)\n#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 4, value)\n#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 12, 4)\n#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 12, 4, value)\n#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(h2c_pkt)                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32)\n#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(h2c_pkt, value)             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value)\n#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(h2c_pkt)                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32)\n#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(h2c_pkt, value)             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value)\n#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(h2c_pkt)                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32)\n#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(h2c_pkt, value)             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value)\n#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(h2c_pkt)                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 32)\n#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(h2c_pkt, value)             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 32, value)\n#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(h2c_pkt)                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 32)\n#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(h2c_pkt, value)             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 32, value)\n#define CFG_PARAM_GET_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)\n#define CFG_PARAM_SET_NUM(h2c_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)\n#define CFG_PARAM_GET_INIT_CASE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 1)\n#define CFG_PARAM_SET_INIT_CASE(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 1, value)\n#define CFG_PARAM_GET_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)\n#define CFG_PARAM_SET_LOC(h2c_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)\n#define UPDATE_DATAPACK_GET_SIZE(h2c_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)\n#define UPDATE_DATAPACK_SET_SIZE(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)\n#define UPDATE_DATAPACK_GET_DATAPACK_ID(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)\n#define UPDATE_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)\n#define UPDATE_DATAPACK_GET_DATAPACK_LOC(h2c_pkt)                              \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)\n#define UPDATE_DATAPACK_SET_DATAPACK_LOC(h2c_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)\n#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(h2c_pkt)                          \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)\n#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(h2c_pkt, value)                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)\n#define UPDATE_DATAPACK_GET_END_SEGMENT(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 1)\n#define UPDATE_DATAPACK_SET_END_SEGMENT(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 1, value)\n#define RUN_DATAPACK_GET_DATAPACK_ID(h2c_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)\n#define RUN_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)\n#define DOWNLOAD_FLASH_GET_SPI_CMD(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)\n#define DOWNLOAD_FLASH_SET_SPI_CMD(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)\n#define DOWNLOAD_FLASH_GET_LOCATION(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 16)\n#define DOWNLOAD_FLASH_SET_LOCATION(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 16, value)\n#define DOWNLOAD_FLASH_GET_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32)\n#define DOWNLOAD_FLASH_SET_SIZE(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value)\n#define DOWNLOAD_FLASH_GET_START_ADDR(h2c_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32)\n#define DOWNLOAD_FLASH_SET_START_ADDR(h2c_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value)\n#define UPDATE_PKT_GET_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)\n#define UPDATE_PKT_SET_SIZE(h2c_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)\n#define UPDATE_PKT_GET_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)\n#define UPDATE_PKT_SET_ID(h2c_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)\n#define UPDATE_PKT_GET_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)\n#define UPDATE_PKT_SET_LOC(h2c_pkt, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)\n#define GENERAL_INFO_GET_FW_TX_BOUNDARY(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)\n#define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)\n#define IQK_GET_CLEAR(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)\n#define IQK_SET_CLEAR(h2c_pkt, value)                                          \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)\n#define IQK_GET_SEGMENT_IQK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)\n#define IQK_SET_SEGMENT_IQK(h2c_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)\n#define PWR_TRK_GET_ENABLE_A(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)\n#define PWR_TRK_SET_ENABLE_A(h2c_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)\n#define PWR_TRK_GET_ENABLE_B(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)\n#define PWR_TRK_SET_ENABLE_B(h2c_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)\n#define PWR_TRK_GET_ENABLE_C(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)\n#define PWR_TRK_SET_ENABLE_C(h2c_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)\n#define PWR_TRK_GET_ENABLE_D(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)\n#define PWR_TRK_SET_ENABLE_D(h2c_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)\n#define PWR_TRK_GET_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 3)\n#define PWR_TRK_SET_TYPE(h2c_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 3, value)\n#define PWR_TRK_GET_BBSWING_INDEX(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)\n#define PWR_TRK_SET_BBSWING_INDEX(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)\n#define PWR_TRK_GET_TX_PWR_INDEX_A(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)\n#define PWR_TRK_SET_TX_PWR_INDEX_A(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)\n#define PWR_TRK_GET_OFFSET_VALUE_A(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 8)\n#define PWR_TRK_SET_OFFSET_VALUE_A(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 8, value)\n#define PWR_TRK_GET_TSSI_VALUE_A(h2c_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 8)\n#define PWR_TRK_SET_TSSI_VALUE_A(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 8, value)\n#define PWR_TRK_GET_TX_PWR_INDEX_B(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8)\n#define PWR_TRK_SET_TX_PWR_INDEX_B(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value)\n#define PWR_TRK_GET_OFFSET_VALUE_B(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8)\n#define PWR_TRK_SET_OFFSET_VALUE_B(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value)\n#define PWR_TRK_GET_TSSI_VALUE_B(h2c_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X10, 16, 8)\n#define PWR_TRK_SET_TSSI_VALUE_B(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 16, 8, value)\n#define PWR_TRK_GET_TX_PWR_INDEX_C(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 8)\n#define PWR_TRK_SET_TX_PWR_INDEX_C(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 8, value)\n#define PWR_TRK_GET_OFFSET_VALUE_C(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X14, 8, 8)\n#define PWR_TRK_SET_OFFSET_VALUE_C(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 8, 8, value)\n#define PWR_TRK_GET_TSSI_VALUE_C(h2c_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 8)\n#define PWR_TRK_SET_TSSI_VALUE_C(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 8, value)\n#define PWR_TRK_GET_TX_PWR_INDEX_D(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8)\n#define PWR_TRK_SET_TX_PWR_INDEX_D(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value)\n#define PWR_TRK_GET_OFFSET_VALUE_D(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8)\n#define PWR_TRK_SET_OFFSET_VALUE_D(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value)\n#define PWR_TRK_GET_TSSI_VALUE_D(h2c_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X18, 16, 8)\n#define PWR_TRK_SET_TSSI_VALUE_D(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 16, 8, value)\n#define PSD_GET_START_PSD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)\n#define PSD_SET_START_PSD(h2c_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)\n#define PSD_GET_END_PSD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 16)\n#define PSD_SET_END_PSD(h2c_pkt, value)                                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 16, value)\n#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)\n#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)\n#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)\n#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)\n#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)\n#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)\n#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 4)\n#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 4, value)\n#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 28, 4)\n#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 28, 4, value)\n#define FW_SNDING_GET_SU0(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)\n#define FW_SNDING_SET_SU0(h2c_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)\n#define FW_SNDING_GET_SU1(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)\n#define FW_SNDING_SET_SU1(h2c_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)\n#define FW_SNDING_GET_MU(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)\n#define FW_SNDING_SET_MU(h2c_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)\n#define FW_SNDING_GET_PERIOD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)\n#define FW_SNDING_SET_PERIOD(h2c_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)\n#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)\n#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)\n#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)\n#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)\n#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0XC, 0, 8)\n#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 0, 8, value)\n#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0XC, 8, 8)\n#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 8, 8, value)\n#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0XC, 16, 8)\n#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 16, 8, value)\n#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0XC, 24, 8)\n#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 24, 8, value)\n#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)\n#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)\n#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1)\n#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value)\n#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 7)\n#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 7, value)\n#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)\n#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)\n#define FW_FWCTRL_GET_LENGTH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)\n#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)\n#define FW_FWCTRL_GET_CONTENT(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32)\n#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value)\n#define UPDATE_SCAN_PKT_GET_SIZE(h2c_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)\n#define UPDATE_SCAN_PKT_SET_SIZE(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)\n#define UPDATE_SCAN_PKT_GET_INDEX(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)\n#define UPDATE_SCAN_PKT_SET_INDEX(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)\n#define UPDATE_SCAN_PKT_GET_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)\n#define UPDATE_SCAN_PKT_SET_LOC(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)\n#define BCN_OFFLOAD_GET_REQUEST_VERSION(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)\n#define BCN_OFFLOAD_SET_REQUEST_VERSION(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)\n#define BCN_OFFLOAD_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)\n#define BCN_OFFLOAD_SET_ENABLE(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)\n#define BCN_OFFLOAD_GET_MORE_RULE(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)\n#define BCN_OFFLOAD_SET_MORE_RULE(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)\n#define BCN_OFFLOAD_GET_C2H_PERIODIC_REPORT(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)\n#define BCN_OFFLOAD_SET_C2H_PERIODIC_REPORT(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)\n#define BCN_OFFLOAD_GET_REPORT_PERIOD(h2c_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)\n#define BCN_OFFLOAD_SET_REPORT_PERIOD(h2c_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)\n#define BCN_OFFLOAD_GET_RULE_LENGTH(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)\n#define BCN_OFFLOAD_SET_RULE_LENGTH(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)\n#define BCN_OFFLOAD_GET_RULE_CONTENT(h2c_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)\n#define BCN_OFFLOAD_SET_RULE_CONTENT(h2c_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)\n#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)\n#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)\n#define P2PPS_GET_ROLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)\n#define P2PPS_SET_ROLE(h2c_pkt, value)                                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)\n#define P2PPS_GET_CTWINDOW_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)\n#define P2PPS_SET_CTWINDOW_EN(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)\n#define P2PPS_GET_NOA_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)\n#define P2PPS_SET_NOA_EN(h2c_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)\n#define P2PPS_GET_NOA_SEL(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 1)\n#define P2PPS_SET_NOA_SEL(h2c_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 1, value)\n#define P2PPS_GET_ALLSTASLEEP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1)\n#define P2PPS_SET_ALLSTASLEEP(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value)\n#define P2PPS_GET_DISCOVERY(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 6, 1)\n#define P2PPS_SET_DISCOVERY(h2c_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 6, 1, value)\n#define P2PPS_GET_DISABLE_CLOSERF(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 7, 1)\n#define P2PPS_SET_DISABLE_CLOSERF(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 7, 1, value)\n#define P2PPS_GET_P2P_PORT_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)\n#define P2PPS_SET_P2P_PORT_ID(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)\n#define P2PPS_GET_P2P_GROUP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)\n#define P2PPS_SET_P2P_GROUP(h2c_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)\n#define P2PPS_GET_P2P_MACID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)\n#define P2PPS_SET_P2P_MACID(h2c_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)\n#define P2PPS_GET_CTWINDOW_LENGTH(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)\n#define P2PPS_SET_CTWINDOW_LENGTH(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)\n#define P2PPS_GET_NOA_DURATION_PARA(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32)\n#define P2PPS_SET_NOA_DURATION_PARA(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value)\n#define P2PPS_GET_NOA_INTERVAL_PARA(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32)\n#define P2PPS_SET_NOA_INTERVAL_PARA(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value)\n#define P2PPS_GET_NOA_START_TIME_PARA(h2c_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 32)\n#define P2PPS_SET_NOA_START_TIME_PARA(h2c_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 32, value)\n#define P2PPS_GET_NOA_COUNT_PARA(h2c_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 32)\n#define P2PPS_SET_NOA_COUNT_PARA(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 32, value)\n#define BT_COEX_GET_DATA_START(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)\n#define BT_COEX_SET_DATA_START(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)\n#define NAN_CTRL_GET_NAN_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 2)\n#define NAN_CTRL_SET_NAN_EN(h2c_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 2, value)\n#define NAN_CTRL_GET_WARMUP_TIMER_FLAG(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)\n#define NAN_CTRL_SET_WARMUP_TIMER_FLAG(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)\n#define NAN_CTRL_GET_SUPPORT_BAND(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 2)\n#define NAN_CTRL_SET_SUPPORT_BAND(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 2, value)\n#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(h2c_pkt)                              \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 10, 1)\n#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(h2c_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 10, 1, value)\n#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(h2c_pkt)                              \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 11, 1)\n#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(h2c_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 11, 1, value)\n#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(h2c_pkt)                             \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)\n#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(h2c_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)\n#define NAN_CTRL_GET_CHANNEL_2G(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)\n#define NAN_CTRL_SET_CHANNEL_2G(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)\n#define NAN_CTRL_GET_CHANNEL_5G(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)\n#define NAN_CTRL_SET_CHANNEL_5G(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)\n#define NAN_CTRL_GET_MASTERPREFERENCE_VALUE(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 8)\n#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 8, value)\n#define NAN_CTRL_GET_RANDOMFACTOR_VALUE(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 8)\n#define NAN_CTRL_SET_RANDOMFACTOR_VALUE(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 8, value)\n#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(h2c_pkt)                       \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)\n#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(h2c_pkt, value)                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)\n#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)\n#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)\n#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(h2c_pkt)                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 16)\n#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(h2c_pkt, value)               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 16, value)\n#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(h2c_pkt)                             \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 16)\n#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(h2c_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 16, value)\n#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(h2c_pkt)                       \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8)\n#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(h2c_pkt, value)                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value)\n#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8)\n#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value)\n#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(h2c_pkt)                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 16)\n#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(h2c_pkt, value)               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 16, value)\n#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(h2c_pkt)                             \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 16)\n#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(h2c_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 16, value)\n#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(h2c_pkt)                       \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8)\n#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(h2c_pkt, value)                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value)\n#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8)\n#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value)\n#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(h2c_pkt)                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 16)\n#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(h2c_pkt, value)               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 16, value)\n#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(h2c_pkt)                             \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 16, 16)\n#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(h2c_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 16, 16, value)\n#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(h2c_pkt)                       \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)\n#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(h2c_pkt, value)                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)\n#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)\n#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)\n#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(h2c_pkt)                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 16)\n#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(h2c_pkt, value)               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 16, value)\n#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(h2c_pkt)                             \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 16)\n#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(h2c_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 16, value)\n#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(h2c_pkt)                       \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8)\n#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(h2c_pkt, value)                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value)\n#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8)\n#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value)\n#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(h2c_pkt)                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 16)\n#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(h2c_pkt, value)               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 16, value)\n#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(h2c_pkt)                             \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 16)\n#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(h2c_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 16, value)\n#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(h2c_pkt)                       \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8)\n#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(h2c_pkt, value)                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value)\n#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8)\n#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value)\n#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(h2c_pkt)                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 16)\n#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(h2c_pkt, value)               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 16, value)\n#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(h2c_pkt)                             \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 16, 16)\n#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(h2c_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 16, 16, value)\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_gpio_cmd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef HALMAC_GPIO_CMD\n#define HALMAC_GPIO_CMD\n\n#include \"halmac_2_platform.h\"\n\n/* GPIO ID */\n#define HALMAC_GPIO0\t\t0\n#define HALMAC_GPIO1\t\t1\n#define HALMAC_GPIO2\t\t2\n#define HALMAC_GPIO3\t\t3\n#define HALMAC_GPIO4\t\t4\n#define HALMAC_GPIO5\t\t5\n#define HALMAC_GPIO6\t\t6\n#define HALMAC_GPIO7\t\t7\n#define HALMAC_GPIO8\t\t8\n#define HALMAC_GPIO9\t\t9\n#define HALMAC_GPIO10\t\t10\n#define HALMAC_GPIO11\t\t11\n#define HALMAC_GPIO12\t\t12\n#define HALMAC_GPIO13\t\t13\n#define HALMAC_GPIO14\t\t14\n#define HALMAC_GPIO15\t\t15\n#define HALMAC_GPIO_NUM\t\t16\n\n/* GPIO type */\n#define HALMAC_GPIO_IN\t\t0\n#define HALMAC_GPIO_OUT\t\t1\n#define HALMAC_GPIO_IN_OUT\t2\n\n/* Function name */\n#define HALMAC_WL_HWPDN\t\t\t0\n#define HALMAC_BT_HWPDN\t\t\t1\n#define HALMAC_BT_GPIO\t\t\t2\n#define HALMAC_WL_HW_EXTWOL\t\t3\n#define HALMAC_BT_HW_EXTWOL\t\t4\n#define HALMAC_BT_SFLASH\t\t5\n#define HALMAC_WL_SFLASH\t\t6\n#define HALMAC_WL_LED\t\t\t7\n#define HALMAC_SDIO_INT\t\t\t8\n#define HALMAC_UART0\t\t\t9\n#define HALMAC_EEPROM\t\t\t10\n#define HALMAC_JTAG\t\t\t11\n#define HALMAC_LTE_COEX_UART\t\t12\n#define HALMAC_3W_LTE_WL_GPIO\t\t13\n#define HALMAC_GPIO2_3_WL_CTRL_EN\t14\n#define HALMAC_GPIO13_14_WL_CTRL_EN\t15\n#define HALMAC_DBG_GNT_WL_BT\t\t16\n#define HALMAC_BT_3DDLS_A\t\t17\n#define HALMAC_BT_3DDLS_B\t\t18\n#define HALMAC_BT_PTA\t\t\t19\n#define HALMAC_WL_PTA\t\t\t20\n#define HALMAC_WL_UART\t\t\t21\n#define HALMAC_WLMAC_DBG\t\t22\n#define HALMAC_WLPHY_DBG\t\t23\n#define HALMAC_BT_DBG\t\t\t24\n#define HALMAC_WLPHY_RFE_CTRL2GPIO\t25\n#define HALMAC_EXT_XTAL\t\t\t26\n#define HALMAC_SW_IO\t\t\t27\n#define HALMAC_BT_SDIO_INT\t\t28\n#define HALMAC_BT_JTAG\t\t\t29\n#define HALMAC_WL_JTAG\t\t\t30\n#define HALMAC_BT_RF\t\t\t31\n#define HALMAC_WLPHY_RFE_CTRL2GPIO_2\t32\n#define HALMAC_MAILBOX_3W\t\t33\n#define HALMAC_MAILBOX_1W\t\t34\n#define HALMAC_SW_DPDT_SEL\t\t35\n#define HALMAC_BT_DPDT_SEL\t\t36\n#define HALMAC_WL_DPDT_SEL\t\t37\n#define HALMAC_BT_PAPE_SEL\t\t38\n#define HALMAC_SW_PAPE_SEL\t\t39\n#define HALMAC_WLBT_PAPE_SEL\t\t40\n#define HALMAC_SW_LNAON_SET\t\t41\n#define HALMAC_BT_LNAON_SEL\t\t42\n#define HALMAC_WLBT_LNAON_SEL\t\t43\n#define HALMAC_SWR_CTRL_EN\t\t44\n\nstruct halmac_gpio_pimux_list {\n\tu16 func;\n\tu8 id;\n\tu8 type;\n\tu16 offset;\n\tu8 msk;\n\tu8 value;\n};\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_h2c_extra_info_ap.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_\n#define _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_\n#define PARAM_INFO_GET_LEN(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 8)\n#define PARAM_INFO_SET_LEN(extra_info, value)                                  \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 0, 8, value)\n#define PARAM_INFO_SET_LEN_NO_CLR(extra_info, value)                           \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 8, value)\n#define PARAM_INFO_GET_IO_CMD(extra_info) GET_C2H_FIELD(extra_info + 0X00, 8, 7)\n#define PARAM_INFO_SET_IO_CMD(extra_info, value)                               \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 8, 7, value)\n#define PARAM_INFO_SET_IO_CMD_NO_CLR(extra_info, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 7, value)\n#define PARAM_INFO_GET_MSK_EN(extra_info)                                      \\\n\tGET_C2H_FIELD(extra_info + 0X00, 15, 1)\n#define PARAM_INFO_SET_MSK_EN(extra_info, value)                               \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 15, 1, value)\n#define PARAM_INFO_SET_MSK_EN_NO_CLR(extra_info, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 15, 1, value)\n#define PARAM_INFO_GET_LLT_PG_BNDY(extra_info)                                 \\\n\tGET_C2H_FIELD(extra_info + 0X00, 16, 8)\n#define PARAM_INFO_SET_LLT_PG_BNDY(extra_info, value)                          \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)\n#define PARAM_INFO_SET_LLT_PG_BNDY_NO_CLR(extra_info, value)                   \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)\n#define PARAM_INFO_GET_EFUSE_RSVDPAGE_LOC(extra_info)                          \\\n\tGET_C2H_FIELD(extra_info + 0X00, 16, 8)\n#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC(extra_info, value)                   \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)\n#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC_NO_CLR(extra_info, value)            \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)\n#define PARAM_INFO_GET_EFUSE_PATCH_EN(extra_info)                              \\\n\tGET_C2H_FIELD(extra_info + 0X00, 16, 8)\n#define PARAM_INFO_SET_EFUSE_PATCH_EN(extra_info, value)                       \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)\n#define PARAM_INFO_SET_EFUSE_PATCH_EN_NO_CLR(extra_info, value)                \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)\n#define PARAM_INFO_GET_RF_ADDR(extra_info)                                     \\\n\tGET_C2H_FIELD(extra_info + 0X00, 16, 8)\n#define PARAM_INFO_SET_RF_ADDR(extra_info, value)                              \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)\n#define PARAM_INFO_SET_RF_ADDR_NO_CLR(extra_info, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)\n#define PARAM_INFO_GET_IO_ADDR(extra_info)                                     \\\n\tGET_C2H_FIELD(extra_info + 0X00, 16, 16)\n#define PARAM_INFO_SET_IO_ADDR(extra_info, value)                              \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value)\n#define PARAM_INFO_SET_IO_ADDR_NO_CLR(extra_info, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value)\n#define PARAM_INFO_GET_DELAY_VAL(extra_info)                                   \\\n\tGET_C2H_FIELD(extra_info + 0X00, 16, 16)\n#define PARAM_INFO_SET_DELAY_VAL(extra_info, value)                            \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value)\n#define PARAM_INFO_SET_DELAY_VAL_NO_CLR(extra_info, value)                     \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value)\n#define PARAM_INFO_GET_RF_PATH(extra_info)                                     \\\n\tGET_C2H_FIELD(extra_info + 0X00, 24, 8)\n#define PARAM_INFO_SET_RF_PATH(extra_info, value)                              \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 24, 8, value)\n#define PARAM_INFO_SET_RF_PATH_NO_CLR(extra_info, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 24, 8, value)\n#define PARAM_INFO_GET_DATA(extra_info) GET_C2H_FIELD(extra_info + 0X04, 0, 32)\n#define PARAM_INFO_SET_DATA(extra_info, value)                                 \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X04, 0, 32, value)\n#define PARAM_INFO_SET_DATA_NO_CLR(extra_info, value)                          \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 32, value)\n#define PARAM_INFO_GET_MASK(extra_info) GET_C2H_FIELD(extra_info + 0X08, 0, 32)\n#define PARAM_INFO_SET_MASK(extra_info, value)                                 \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X08, 0, 32, value)\n#define PARAM_INFO_SET_MASK_NO_CLR(extra_info, value)                          \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X08, 0, 32, value)\n#define CH_INFO_GET_CH(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 8)\n#define CH_INFO_SET_CH(extra_info, value)                                      \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 0, 8, value)\n#define CH_INFO_SET_CH_NO_CLR(extra_info, value)                               \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 8, value)\n#define CH_INFO_GET_PRI_CH_IDX(extra_info)                                     \\\n\tGET_C2H_FIELD(extra_info + 0X00, 8, 4)\n#define CH_INFO_SET_PRI_CH_IDX(extra_info, value)                              \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 8, 4, value)\n#define CH_INFO_SET_PRI_CH_IDX_NO_CLR(extra_info, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 4, value)\n#define CH_INFO_GET_BW(extra_info) GET_C2H_FIELD(extra_info + 0X00, 12, 4)\n#define CH_INFO_SET_BW(extra_info, value)                                      \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 12, 4, value)\n#define CH_INFO_SET_BW_NO_CLR(extra_info, value)                               \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 12, 4, value)\n#define CH_INFO_GET_TIMEOUT(extra_info) GET_C2H_FIELD(extra_info + 0X00, 16, 8)\n#define CH_INFO_SET_TIMEOUT(extra_info, value)                                 \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)\n#define CH_INFO_SET_TIMEOUT_NO_CLR(extra_info, value)                          \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)\n#define CH_INFO_GET_ACTION_ID(extra_info)                                      \\\n\tGET_C2H_FIELD(extra_info + 0X00, 24, 7)\n#define CH_INFO_SET_ACTION_ID(extra_info, value)                               \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 24, 7, value)\n#define CH_INFO_SET_ACTION_ID_NO_CLR(extra_info, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 24, 7, value)\n#define CH_INFO_GET_EXTRA_INFO(extra_info)                                     \\\n\tGET_C2H_FIELD(extra_info + 0X00, 31, 1)\n#define CH_INFO_SET_EXTRA_INFO(extra_info, value)                              \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 31, 1, value)\n#define CH_INFO_SET_EXTRA_INFO_NO_CLR(extra_info, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 31, 1, value)\n#define CH_EXTRA_INFO_GET_ID(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 7)\n#define CH_EXTRA_INFO_SET_ID(extra_info, value)                                \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 0, 7, value)\n#define CH_EXTRA_INFO_SET_ID_NO_CLR(extra_info, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 7, value)\n#define CH_EXTRA_INFO_GET_INFO(extra_info)                                     \\\n\tGET_C2H_FIELD(extra_info + 0X00, 7, 1)\n#define CH_EXTRA_INFO_SET_INFO(extra_info, value)                              \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 7, 1, value)\n#define CH_EXTRA_INFO_SET_INFO_NO_CLR(extra_info, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 7, 1, value)\n#define CH_EXTRA_INFO_GET_SIZE(extra_info)                                     \\\n\tGET_C2H_FIELD(extra_info + 0X00, 8, 8)\n#define CH_EXTRA_INFO_SET_SIZE(extra_info, value)                              \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 8, 8, value)\n#define CH_EXTRA_INFO_SET_SIZE_NO_CLR(extra_info, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 8, value)\n#define CH_EXTRA_INFO_GET_DATA(extra_info)                                     \\\n\tGET_C2H_FIELD(extra_info + 0X00, 16, 1)\n#define CH_EXTRA_INFO_SET_DATA(extra_info, value)                              \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 16, 1, value)\n#define CH_EXTRA_INFO_SET_DATA_NO_CLR(extra_info, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 1, value)\n#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_L(extra_info)                       \\\n\tGET_C2H_FIELD(extra_info + 0X00, 0, 16)\n#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L(extra_info, value)                \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 0, 16, value)\n#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L_NO_CLR(extra_info, value)         \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 16, value)\n#define HIOE_INSTRUCTION_INFO_GET_BITDATA(extra_info)                          \\\n\tGET_C2H_FIELD(extra_info + 0X00, 0, 16)\n#define HIOE_INSTRUCTION_INFO_SET_BITDATA(extra_info, value)                   \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 0, 16, value)\n#define HIOE_INSTRUCTION_INFO_SET_BITDATA_NO_CLR(extra_info, value)            \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 16, value)\n#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_H(extra_info)                       \\\n\tGET_C2H_FIELD(extra_info + 0X00, 16, 16)\n#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H(extra_info, value)                \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value)\n#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H_NO_CLR(extra_info, value)         \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value)\n#define HIOE_INSTRUCTION_INFO_GET_BITMASK(extra_info)                          \\\n\tGET_C2H_FIELD(extra_info + 0X00, 16, 16)\n#define HIOE_INSTRUCTION_INFO_SET_BITMASK(extra_info, value)                   \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value)\n#define HIOE_INSTRUCTION_INFO_SET_BITMASK_NO_CLR(extra_info, value)            \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value)\n#define HIOE_INSTRUCTION_INFO_GET_REG_ADDR(extra_info)                         \\\n\tGET_C2H_FIELD(extra_info + 0X04, 0, 22)\n#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR(extra_info, value)                  \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X04, 0, 22, value)\n#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR_NO_CLR(extra_info, value)           \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 22, value)\n#define HIOE_INSTRUCTION_INFO_GET_DELAY_VALUE(extra_info)                      \\\n\tGET_C2H_FIELD(extra_info + 0X04, 0, 22)\n#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE(extra_info, value)               \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X04, 0, 22, value)\n#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE_NO_CLR(extra_info, value)        \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 22, value)\n#define HIOE_INSTRUCTION_INFO_GET_MODE_SELECT(extra_info)                      \\\n\tGET_C2H_FIELD(extra_info + 0X04, 22, 1)\n#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT(extra_info, value)               \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X04, 22, 1, value)\n#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT_NO_CLR(extra_info, value)        \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X04, 22, 1, value)\n#define HIOE_INSTRUCTION_INFO_GET_IO_DELAY(extra_info)                         \\\n\tGET_C2H_FIELD(extra_info + 0X04, 23, 1)\n#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY(extra_info, value)                  \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X04, 23, 1, value)\n#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY_NO_CLR(extra_info, value)           \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X04, 23, 1, value)\n#define HIOE_INSTRUCTION_INFO_GET_BYTEMASK(extra_info)                         \\\n\tGET_C2H_FIELD(extra_info + 0X04, 24, 4)\n#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK(extra_info, value)                  \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X04, 24, 4, value)\n#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK_NO_CLR(extra_info, value)           \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X04, 24, 4, value)\n#define HIOE_INSTRUCTION_INFO_GET_RD_EN(extra_info)                            \\\n\tGET_C2H_FIELD(extra_info + 0X04, 28, 1)\n#define HIOE_INSTRUCTION_INFO_SET_RD_EN(extra_info, value)                     \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X04, 28, 1, value)\n#define HIOE_INSTRUCTION_INFO_SET_RD_EN_NO_CLR(extra_info, value)              \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X04, 28, 1, value)\n#define HIOE_INSTRUCTION_INFO_GET_WR_EN(extra_info)                            \\\n\tGET_C2H_FIELD(extra_info + 0X04, 29, 1)\n#define HIOE_INSTRUCTION_INFO_SET_WR_EN(extra_info, value)                     \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X04, 29, 1, value)\n#define HIOE_INSTRUCTION_INFO_SET_WR_EN_NO_CLR(extra_info, value)              \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X04, 29, 1, value)\n#define HIOE_INSTRUCTION_INFO_GET_RAW_R(extra_info)                            \\\n\tGET_C2H_FIELD(extra_info + 0X04, 30, 1)\n#define HIOE_INSTRUCTION_INFO_SET_RAW_R(extra_info, value)                     \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X04, 30, 1, value)\n#define HIOE_INSTRUCTION_INFO_SET_RAW_R_NO_CLR(extra_info, value)              \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X04, 30, 1, value)\n#define HIOE_INSTRUCTION_INFO_GET_RAW(extra_info)                              \\\n\tGET_C2H_FIELD(extra_info + 0X04, 31, 1)\n#define HIOE_INSTRUCTION_INFO_SET_RAW(extra_info, value)                       \\\n\tSET_C2H_FIELD_CLR(extra_info + 0X04, 31, 1, value)\n#define HIOE_INSTRUCTION_INFO_SET_RAW_NO_CLR(extra_info, value)                \\\n\tSET_C2H_FIELD_NO_CLR(extra_info + 0X04, 31, 1, value)\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_h2c_extra_info_nic.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_\n#define _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_\n\n/* H2C extra info (rsvd page) usage, unit : page (128byte)*/\n/* dlfw : not include txdesc size*/\n/* update pkt : not include txdesc size*/\n/* cfg param : not include txdesc size*/\n/* scan info : not include txdesc size*/\n/* dl flash : not include txdesc size*/\n#define DLFW_RSVDPG_SIZE 2048\n#define UPDATE_PKT_RSVDPG_SIZE 2048\n#define CFG_PARAM_RSVDPG_SIZE 2048\n#define SCAN_INFO_RSVDPG_SIZE 256\n#define DL_FLASH_RSVDPG_SIZE 2048\n/* su0 snding pkt : include txdesc size */\n#define SU0_SNDING_PKT_OFFSET 0\n#define SU0_SNDING_PKT_RSVDPG_SIZE 128\n\n#define PARAM_INFO_GET_LEN(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 8)\n#define PARAM_INFO_SET_LEN(extra_info, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 8, value)\n#define PARAM_INFO_GET_IO_CMD(extra_info)                                      \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 8, 7)\n#define PARAM_INFO_SET_IO_CMD(extra_info, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 7, value)\n#define PARAM_INFO_GET_MSK_EN(extra_info)                                      \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 15, 1)\n#define PARAM_INFO_SET_MSK_EN(extra_info, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 15, 1, value)\n#define PARAM_INFO_GET_LLT_PG_BNDY(extra_info)                                 \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)\n#define PARAM_INFO_SET_LLT_PG_BNDY(extra_info, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)\n#define PARAM_INFO_GET_EFUSE_RSVDPAGE_LOC(extra_info)                          \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)\n#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC(extra_info, value)                   \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)\n#define PARAM_INFO_GET_EFUSE_PATCH_EN(extra_info)                              \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)\n#define PARAM_INFO_SET_EFUSE_PATCH_EN(extra_info, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)\n#define PARAM_INFO_GET_RF_ADDR(extra_info)                                     \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)\n#define PARAM_INFO_SET_RF_ADDR(extra_info, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)\n#define PARAM_INFO_GET_IO_ADDR(extra_info)                                     \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16)\n#define PARAM_INFO_SET_IO_ADDR(extra_info, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value)\n#define PARAM_INFO_GET_DELAY_VAL(extra_info)                                   \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16)\n#define PARAM_INFO_SET_DELAY_VAL(extra_info, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value)\n#define PARAM_INFO_GET_RF_PATH(extra_info)                                     \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 24, 8)\n#define PARAM_INFO_SET_RF_PATH(extra_info, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 24, 8, value)\n#define PARAM_INFO_GET_DATA(extra_info)                                        \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X04, 0, 32)\n#define PARAM_INFO_SET_DATA(extra_info, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 32, value)\n#define PARAM_INFO_GET_MASK(extra_info)                                        \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X08, 0, 32)\n#define PARAM_INFO_SET_MASK(extra_info, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X08, 0, 32, value)\n#define CH_INFO_GET_CH(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 8)\n#define CH_INFO_SET_CH(extra_info, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 8, value)\n#define CH_INFO_GET_PRI_CH_IDX(extra_info)                                     \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 8, 4)\n#define CH_INFO_SET_PRI_CH_IDX(extra_info, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 4, value)\n#define CH_INFO_GET_BW(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 12, 4)\n#define CH_INFO_SET_BW(extra_info, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 12, 4, value)\n#define CH_INFO_GET_TIMEOUT(extra_info)                                        \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)\n#define CH_INFO_SET_TIMEOUT(extra_info, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)\n#define CH_INFO_GET_ACTION_ID(extra_info)                                      \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 24, 7)\n#define CH_INFO_SET_ACTION_ID(extra_info, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 24, 7, value)\n#define CH_INFO_GET_EXTRA_INFO(extra_info)                                     \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 31, 1)\n#define CH_INFO_SET_EXTRA_INFO(extra_info, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 31, 1, value)\n#define CH_EXTRA_INFO_GET_ID(extra_info)                                       \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 0, 7)\n#define CH_EXTRA_INFO_SET_ID(extra_info, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 7, value)\n#define CH_EXTRA_INFO_GET_INFO(extra_info)                                     \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 7, 1)\n#define CH_EXTRA_INFO_SET_INFO(extra_info, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 7, 1, value)\n#define CH_EXTRA_INFO_GET_SIZE(extra_info)                                     \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 8, 8)\n#define CH_EXTRA_INFO_SET_SIZE(extra_info, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 8, value)\n#define CH_EXTRA_INFO_GET_DATA(extra_info)                                     \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 16, 1)\n#define CH_EXTRA_INFO_SET_DATA(extra_info, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 1, value)\n#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_L(extra_info)                       \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 0, 16)\n#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L(extra_info, value)                \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 16, value)\n#define HIOE_INSTRUCTION_INFO_GET_BITDATA(extra_info)                          \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 0, 16)\n#define HIOE_INSTRUCTION_INFO_SET_BITDATA(extra_info, value)                   \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 16, value)\n#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_H(extra_info)                       \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16)\n#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H(extra_info, value)                \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value)\n#define HIOE_INSTRUCTION_INFO_GET_BITMASK(extra_info)                          \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16)\n#define HIOE_INSTRUCTION_INFO_SET_BITMASK(extra_info, value)                   \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value)\n#define HIOE_INSTRUCTION_INFO_GET_REG_ADDR(extra_info)                         \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X04, 0, 22)\n#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR(extra_info, value)                  \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 22, value)\n#define HIOE_INSTRUCTION_INFO_GET_DELAY_VALUE(extra_info)                      \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X04, 0, 22)\n#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE(extra_info, value)               \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 22, value)\n#define HIOE_INSTRUCTION_INFO_GET_MODE_SELECT(extra_info)                      \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X04, 22, 1)\n#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT(extra_info, value)               \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X04, 22, 1, value)\n#define HIOE_INSTRUCTION_INFO_GET_IO_DELAY(extra_info)                         \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X04, 23, 1)\n#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY(extra_info, value)                  \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X04, 23, 1, value)\n#define HIOE_INSTRUCTION_INFO_GET_BYTEMASK(extra_info)                         \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X04, 24, 4)\n#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK(extra_info, value)                  \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X04, 24, 4, value)\n#define HIOE_INSTRUCTION_INFO_GET_RD_EN(extra_info)                            \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X04, 28, 1)\n#define HIOE_INSTRUCTION_INFO_SET_RD_EN(extra_info, value)                     \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X04, 28, 1, value)\n#define HIOE_INSTRUCTION_INFO_GET_WR_EN(extra_info)                            \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X04, 29, 1)\n#define HIOE_INSTRUCTION_INFO_SET_WR_EN(extra_info, value)                     \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X04, 29, 1, value)\n#define HIOE_INSTRUCTION_INFO_GET_RAW_R(extra_info)                            \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X04, 30, 1)\n#define HIOE_INSTRUCTION_INFO_SET_RAW_R(extra_info, value)                     \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X04, 30, 1, value)\n#define HIOE_INSTRUCTION_INFO_GET_RAW(extra_info)                              \\\n\tLE_BITS_TO_4BYTE(extra_info + 0X04, 31, 1)\n#define HIOE_INSTRUCTION_INFO_SET_RAW(extra_info, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(extra_info + 0X04, 31, 1, value)\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_hw_cfg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef __HALMAC__HW_CFG_H__\n#define __HALMAC__HW_CFG_H__\n\n#include <drv_conf.h>\t/* CONFIG_[IC], CONFIG_[INTF]_HCI */\n\n#ifdef CONFIG_RTL8723A\n#define HALMAC_8723A_SUPPORT\t1\n#else\n#define HALMAC_8723A_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8188E\n#define HALMAC_8188E_SUPPORT\t1\n#else\n#define HALMAC_8188E_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8821A\n#define HALMAC_8821A_SUPPORT\t1\n#else\n#define HALMAC_8821A_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8723B\n#define HALMAC_8723B_SUPPORT\t1\n#else\n#define HALMAC_8723B_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8812A\n#define HALMAC_8812A_SUPPORT\t1\n#else\n#define HALMAC_8812A_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8192E\n#define HALMAC_8192E_SUPPORT\t1\n#else\n#define HALMAC_8192E_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8881A\n#define HALMAC_8881A_SUPPORT\t1\n#else\n#define HALMAC_8881A_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8821B\n#define HALMAC_8821B_SUPPORT\t1\n#else\n#define HALMAC_8821B_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8814A\n#define HALMAC_8814A_SUPPORT\t1\n#else\n#define HALMAC_8814A_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8881A\n#define HALMAC_8881A_SUPPORT\t1\n#else\n#define HALMAC_8881A_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8703B\n#define HALMAC_8703B_SUPPORT\t1\n#else\n#define HALMAC_8703B_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8723D\n#define HALMAC_8723D_SUPPORT\t1\n#else\n#define HALMAC_8723D_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8188F\n#define HALMAC_8188F_SUPPORT\t1\n#else\n#define HALMAC_8188F_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8821BMP\n#define HALMAC_8821BMP_SUPPORT\t1\n#else\n#define HALMAC_8821BMP_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8814AMP\n#define HALMAC_8814AMP_SUPPORT\t1\n#else\n#define HALMAC_8814AMP_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8195A\n#define HALMAC_8195A_SUPPORT\t1\n#else\n#define HALMAC_8195A_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8821B\n#define HALMAC_8821B_SUPPORT\t1\n#else\n#define HALMAC_8821B_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8196F\n#define HALMAC_8196F_SUPPORT\t1\n#else\n#define HALMAC_8196F_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8197F\n#define HALMAC_8197F_SUPPORT\t1\n#else\n#define HALMAC_8197F_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8198F\n#define HALMAC_8198F_SUPPORT\t1\n#else\n#define HALMAC_8198F_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8192F\n#define HALMAC_8192F_SUPPORT\t1\n#else\n#define HALMAC_8192F_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8197G\n#define HALMAC_8197G_SUPPORT\t1\n#else\n#define HALMAC_8197G_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8812F\n#define HALMAC_8812F_SUPPORT\t1\n#else\n#define HALMAC_8812F_SUPPORT\t0\n#endif\n\n\n/* Halmac support IC version */\n\n#ifdef CONFIG_RTL8814B\n#define HALMAC_8814B_SUPPORT\t1\n#else\n#define HALMAC_8814B_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8821C\n#define HALMAC_8821C_SUPPORT\t1\n#else\n#define HALMAC_8821C_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8822B\n#define HALMAC_8822B_SUPPORT\t1\n#else\n#define HALMAC_8822B_SUPPORT\t0\n#endif\n\n#ifdef CONFIG_RTL8822C\n#define HALMAC_8822C_SUPPORT\t1\n#else\n#define HALMAC_8822C_SUPPORT\t0\n#endif\n\n\n/* Interface support */\n#ifdef CONFIG_SDIO_HCI\n#define HALMAC_SDIO_SUPPORT\t1\n#else\n#define HALMAC_SDIO_SUPPORT\t0\n#endif\n#ifdef CONFIG_USB_HCI\n#define HALMAC_USB_SUPPORT\t1\n#else\n#define HALMAC_USB_SUPPORT\t0\n#endif\n#ifdef CONFIG_PCI_HCI\n#define HALMAC_PCIE_SUPPORT\t1\n#else\n#define HALMAC_PCIE_SUPPORT\t0\n#endif\n\n#endif /* __HALMAC__HW_CFG_H__ */\n\n\n"
  },
  {
    "path": "hal/halmac/halmac_intf_phy_cmd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef HALMAC_INTF_PHY_CMD\n#define HALMAC_INTF_PHY_CMD\n\n/* Cut mask */\nenum halmac_intf_phy_cut {\n\tHALMAC_INTF_PHY_CUT_TESTCHIP = BIT(0),\n\tHALMAC_INTF_PHY_CUT_A = BIT(1),\n\tHALMAC_INTF_PHY_CUT_B = BIT(2),\n\tHALMAC_INTF_PHY_CUT_C = BIT(3),\n\tHALMAC_INTF_PHY_CUT_D = BIT(4),\n\tHALMAC_INTF_PHY_CUT_E = BIT(5),\n\tHALMAC_INTF_PHY_CUT_F = BIT(6),\n\tHALMAC_INTF_PHY_CUT_G = BIT(7),\n\tHALMAC_INTF_PHY_CUT_ALL = 0x7FFF,\n};\n\n/* IP selection */\nenum halmac_ip_sel {\n\tHALMAC_IP_INTF_PHY = 0,\n\tHALMAC_IP_SEL_MAC = 1,\n\tHALMAC_IP_PCIE_DBI = 2,\n\tHALMAC_IP_SEL_UNDEFINE = 0x7FFF,\n};\n\n/* Platform mask */\nenum halmac_intf_phy_platform {\n\tHALMAC_INTF_PHY_PLATFORM_ALL = 0x7FFF,\n};\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_original_c2h_ap.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_AP_H_\n#define _HAL_ORIGINALC2HFORMAT_H2C_C2H_AP_H_\n#define CMD_ID_C2H 0X00\n#define CMD_ID_DBG 0X00\n#define CMD_ID_C2H_LB 0X01\n#define CMD_ID_C2H_SND_TXBF 0X02\n#define CMD_ID_C2H_CCX_RPT 0X03\n#define CMD_ID_C2H_AP_REQ_TXRPT 0X04\n#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05\n#define CMD_ID_C2H_RA_RPT 0X0C\n#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D\n#define CMD_ID_C2H_RA_PARA_RPT 0X0E\n#define CMD_ID_C2H_CUR_CHANNEL 0X10\n#define CMD_ID_C2H_GPIO_WAKEUP 0X14\n#define CMD_ID_C2H_DROPID_RPT 0X2D\n#define C2H_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)\n#define C2H_SET_CMD_ID(c2h_pkt, value)                                         \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_SET_CMD_ID_NO_CLR(c2h_pkt, value)                                  \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)\n#define C2H_SET_SEQ(c2h_pkt, value)                                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_SET_SEQ_NO_CLR(c2h_pkt, value)                                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define DBG_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)\n#define DBG_SET_CMD_ID(c2h_pkt, value)                                         \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define DBG_SET_CMD_ID_NO_CLR(c2h_pkt, value)                                  \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define DBG_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)\n#define DBG_SET_SEQ(c2h_pkt, value)                                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define DBG_SET_SEQ_NO_CLR(c2h_pkt, value)                                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define DBG_GET_DBG_STR1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)\n#define DBG_SET_DBG_STR1(c2h_pkt, value)                                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)\n#define DBG_SET_DBG_STR1_NO_CLR(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)\n#define DBG_GET_DBG_STR2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)\n#define DBG_SET_DBG_STR2(c2h_pkt, value)                                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)\n#define DBG_SET_DBG_STR2_NO_CLR(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)\n#define DBG_GET_DBG_STR3(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)\n#define DBG_SET_DBG_STR3(c2h_pkt, value)                                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define DBG_SET_DBG_STR3_NO_CLR(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define DBG_GET_DBG_STR4(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)\n#define DBG_SET_DBG_STR4(c2h_pkt, value)                                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define DBG_SET_DBG_STR4_NO_CLR(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define DBG_GET_DBG_STR5(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)\n#define DBG_SET_DBG_STR5(c2h_pkt, value)                                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)\n#define DBG_SET_DBG_STR5_NO_CLR(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)\n#define DBG_GET_DBG_STR6(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)\n#define DBG_SET_DBG_STR6(c2h_pkt, value)                                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)\n#define DBG_SET_DBG_STR6_NO_CLR(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)\n#define DBG_GET_DBG_STR7(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)\n#define DBG_SET_DBG_STR7(c2h_pkt, value)                                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)\n#define DBG_SET_DBG_STR7_NO_CLR(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)\n#define DBG_GET_DBG_STR8(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)\n#define DBG_SET_DBG_STR8(c2h_pkt, value)                                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)\n#define DBG_SET_DBG_STR8_NO_CLR(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)\n#define DBG_GET_DBG_STR9(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)\n#define DBG_SET_DBG_STR9(c2h_pkt, value)                                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)\n#define DBG_SET_DBG_STR9_NO_CLR(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)\n#define DBG_GET_DBG_STR10(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8)\n#define DBG_SET_DBG_STR10(c2h_pkt, value)                                      \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value)\n#define DBG_SET_DBG_STR10_NO_CLR(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value)\n#define DBG_GET_DBG_STR11(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8)\n#define DBG_SET_DBG_STR11(c2h_pkt, value)                                      \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value)\n#define DBG_SET_DBG_STR11_NO_CLR(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value)\n#define DBG_GET_DBG_STR12(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8)\n#define DBG_SET_DBG_STR12(c2h_pkt, value)                                      \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value)\n#define DBG_SET_DBG_STR12_NO_CLR(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value)\n#define DBG_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)\n#define DBG_SET_LEN(c2h_pkt, value)                                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define DBG_SET_LEN_NO_CLR(c2h_pkt, value)                                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define DBG_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)\n#define DBG_SET_TRIGGER(c2h_pkt, value)                                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define DBG_SET_TRIGGER_NO_CLR(c2h_pkt, value)                                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_LB_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)\n#define C2H_LB_SET_CMD_ID(c2h_pkt, value)                                      \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_LB_SET_CMD_ID_NO_CLR(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_LB_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)\n#define C2H_LB_SET_SEQ(c2h_pkt, value)                                         \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_LB_SET_SEQ_NO_CLR(c2h_pkt, value)                                  \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_LB_GET_PAYLOAD1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 16)\n#define C2H_LB_SET_PAYLOAD1(c2h_pkt, value)                                    \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 16, value)\n#define C2H_LB_SET_PAYLOAD1_NO_CLR(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 16, value)\n#define C2H_LB_GET_PAYLOAD2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 32)\n#define C2H_LB_SET_PAYLOAD2(c2h_pkt, value)                                    \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 32, value)\n#define C2H_LB_SET_PAYLOAD2_NO_CLR(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 32, value)\n#define C2H_LB_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)\n#define C2H_LB_SET_LEN(c2h_pkt, value)                                         \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_LB_SET_LEN_NO_CLR(c2h_pkt, value)                                  \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_LB_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)\n#define C2H_LB_SET_TRIGGER(c2h_pkt, value)                                     \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_LB_SET_TRIGGER_NO_CLR(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_SND_TXBF_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)\n#define C2H_SND_TXBF_SET_CMD_ID(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_SND_TXBF_SET_CMD_ID_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_SND_TXBF_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)\n#define C2H_SND_TXBF_SET_SEQ(c2h_pkt, value)                                   \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_SND_TXBF_SET_SEQ_NO_CLR(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_SND_TXBF_GET_SND_RESULT(c2h_pkt)                                   \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 16, 1)\n#define C2H_SND_TXBF_SET_SND_RESULT(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 1, value)\n#define C2H_SND_TXBF_SET_SND_RESULT_NO_CLR(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 1, value)\n#define C2H_SND_TXBF_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)\n#define C2H_SND_TXBF_SET_LEN(c2h_pkt, value)                                   \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_SND_TXBF_SET_LEN_NO_CLR(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_SND_TXBF_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)\n#define C2H_SND_TXBF_SET_TRIGGER(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_SND_TXBF_SET_TRIGGER_NO_CLR(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_CCX_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)\n#define C2H_CCX_RPT_SET_CMD_ID(c2h_pkt, value)                                 \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_CCX_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value)                          \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_CCX_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)\n#define C2H_CCX_RPT_SET_SEQ(c2h_pkt, value)                                    \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_CCX_RPT_SET_SEQ_NO_CLR(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_CCX_RPT_GET_QSEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 5)\n#define C2H_CCX_RPT_SET_QSEL(c2h_pkt, value)                                   \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 5, value)\n#define C2H_CCX_RPT_SET_QSEL_NO_CLR(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 5, value)\n#define C2H_CCX_RPT_GET_BMC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 21, 1)\n#define C2H_CCX_RPT_SET_BMC(c2h_pkt, value)                                    \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 21, 1, value)\n#define C2H_CCX_RPT_SET_BMC_NO_CLR(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 21, 1, value)\n#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(c2h_pkt)                                \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 22, 1)\n#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 22, 1, value)\n#define C2H_CCX_RPT_SET_LIFE_TIME_OVER_NO_CLR(c2h_pkt, value)                  \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 22, 1, value)\n#define C2H_CCX_RPT_GET_RETRY_OVER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 23, 1)\n#define C2H_CCX_RPT_SET_RETRY_OVER(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 23, 1, value)\n#define C2H_CCX_RPT_SET_RETRY_OVER_NO_CLR(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 23, 1, value)\n#define C2H_CCX_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)\n#define C2H_CCX_RPT_SET_MACID(c2h_pkt, value)                                  \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_CCX_RPT_SET_MACID_NO_CLR(c2h_pkt, value)                           \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(c2h_pkt)                                \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 0, 6)\n#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 6, value)\n#define C2H_CCX_RPT_SET_DATA_RETRY_CNT_NO_CLR(c2h_pkt, value)                  \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 6, value)\n#define C2H_CCX_RPT_GET_QUEUE7_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)\n#define C2H_CCX_RPT_SET_QUEUE7_0(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define C2H_CCX_RPT_SET_QUEUE7_0_NO_CLR(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define C2H_CCX_RPT_GET_QUEUE15_8(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)\n#define C2H_CCX_RPT_SET_QUEUE15_8(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)\n#define C2H_CCX_RPT_SET_QUEUE15_8_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)\n#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt)                               \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)\n#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)\n#define C2H_CCX_RPT_SET_FINAL_DATA_RATE_NO_CLR(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)\n#define C2H_CCX_RPT_GET_SW_DEFINE_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)\n#define C2H_CCX_RPT_SET_SW_DEFINE_0(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)\n#define C2H_CCX_RPT_SET_SW_DEFINE_0_NO_CLR(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)\n#define C2H_CCX_RPT_GET_SW_DEFINE_1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 4)\n#define C2H_CCX_RPT_SET_SW_DEFINE_1(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 4, value)\n#define C2H_CCX_RPT_SET_SW_DEFINE_1_NO_CLR(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 4, value)\n#define C2H_CCX_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)\n#define C2H_CCX_RPT_SET_LEN(c2h_pkt, value)                                    \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_CCX_RPT_SET_LEN_NO_CLR(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_CCX_RPT_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)\n#define C2H_CCX_RPT_SET_TRIGGER(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_CCX_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)\n#define C2H_AP_REQ_TXRPT_SET_CMD_ID(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)\n#define C2H_AP_REQ_TXRPT_SET_SEQ(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_AP_REQ_TXRPT_SET_SEQ_NO_CLR(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(c2h_pkt)                               \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)\n#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)\n#define C2H_AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(c2h_pkt)                                 \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)\n#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(c2h_pkt, value)                          \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0_NO_CLR(c2h_pkt, value)                   \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(c2h_pkt)                                 \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)\n#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(c2h_pkt, value)                          \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1_NO_CLR(c2h_pkt, value)                   \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(c2h_pkt)                               \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)\n#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0_NO_CLR(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(c2h_pkt)                               \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)\n#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)\n#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1_NO_CLR(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(c2h_pkt)                            \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)\n#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)\n#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1_NO_CLR(c2h_pkt, value)              \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(c2h_pkt)                               \\\n\tGET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)\n#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)\n#define C2H_AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(c2h_pkt)                                 \\\n\tGET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)\n#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(c2h_pkt, value)                          \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)\n#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0_NO_CLR(c2h_pkt, value)                   \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(c2h_pkt)                                 \\\n\tGET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)\n#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(c2h_pkt, value)                          \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)\n#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1_NO_CLR(c2h_pkt, value)                   \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(c2h_pkt)                               \\\n\tGET_C2H_FIELD(c2h_pkt + 0X08, 24, 8)\n#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value)\n#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0_NO_CLR(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(c2h_pkt)                               \\\n\tGET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8)\n#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value)\n#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1_NO_CLR(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(c2h_pkt)                            \\\n\tGET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8)\n#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value)\n#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2_NO_CLR(c2h_pkt, value)              \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)\n#define C2H_AP_REQ_TXRPT_SET_LEN(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_AP_REQ_TXRPT_SET_LEN_NO_CLR(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TRIGGER(c2h_pkt)                                  \\\n\tGET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)\n#define C2H_AP_REQ_TXRPT_SET_TRIGGER(c2h_pkt, value)                           \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_AP_REQ_TXRPT_SET_TRIGGER_NO_CLR(c2h_pkt, value)                    \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(c2h_pkt)                        \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID_NO_CLR(c2h_pkt, value)          \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(c2h_pkt)                           \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(c2h_pkt, value)                    \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ_NO_CLR(c2h_pkt, value)             \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(c2h_pkt)                 \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 16, 7)\n#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(c2h_pkt, value)          \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 7, value)\n#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP_NO_CLR(c2h_pkt, value)   \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 7, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(c2h_pkt)                 \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(c2h_pkt, value)          \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1_NO_CLR(c2h_pkt, value)   \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(c2h_pkt)                 \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(c2h_pkt, value)          \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2_NO_CLR(c2h_pkt, value)   \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(c2h_pkt)                 \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(c2h_pkt, value)          \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3_NO_CLR(c2h_pkt, value)   \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(c2h_pkt)                 \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(c2h_pkt, value)          \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4_NO_CLR(c2h_pkt, value)   \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(c2h_pkt)                 \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(c2h_pkt, value)          \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5_NO_CLR(c2h_pkt, value)   \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(c2h_pkt)                 \\\n\tGET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(c2h_pkt, value)          \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6_NO_CLR(c2h_pkt, value)   \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(c2h_pkt)                 \\\n\tGET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(c2h_pkt, value)          \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7_NO_CLR(c2h_pkt, value)   \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(c2h_pkt)                           \\\n\tGET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(c2h_pkt, value)                    \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_SET_LEN_NO_CLR(c2h_pkt, value)             \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(c2h_pkt)                       \\\n\tGET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(c2h_pkt, value)                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER_NO_CLR(c2h_pkt, value)         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_RA_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)\n#define C2H_RA_RPT_SET_CMD_ID(c2h_pkt, value)                                  \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_RA_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value)                           \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_RA_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)\n#define C2H_RA_RPT_SET_SEQ(c2h_pkt, value)                                     \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_RA_RPT_SET_SEQ_NO_CLR(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_RA_RPT_GET_RATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)\n#define C2H_RA_RPT_SET_RATE(c2h_pkt, value)                                    \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)\n#define C2H_RA_RPT_SET_RATE_NO_CLR(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)\n#define C2H_RA_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)\n#define C2H_RA_RPT_SET_MACID(c2h_pkt, value)                                   \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_RA_RPT_SET_MACID_NO_CLR(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_RA_RPT_GET_USE_LDPC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 1)\n#define C2H_RA_RPT_SET_USE_LDPC(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 1, value)\n#define C2H_RA_RPT_SET_USE_LDPC_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 1, value)\n#define C2H_RA_RPT_GET_USE_TXBF(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 1, 1)\n#define C2H_RA_RPT_SET_USE_TXBF(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 1, 1, value)\n#define C2H_RA_RPT_SET_USE_TXBF_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 1, 1, value)\n#define C2H_RA_RPT_GET_COLLISION_STATE(c2h_pkt)                                \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)\n#define C2H_RA_RPT_SET_COLLISION_STATE(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define C2H_RA_RPT_SET_COLLISION_STATE_NO_CLR(c2h_pkt, value)                  \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define C2H_RA_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)\n#define C2H_RA_RPT_SET_LEN(c2h_pkt, value)                                     \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_RA_RPT_SET_LEN_NO_CLR(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_RA_RPT_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)\n#define C2H_RA_RPT_SET_TRIGGER(c2h_pkt, value)                                 \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_RA_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value)                          \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(c2h_pkt)                             \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)\n#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_SPECIAL_STATISTICS_SET_CMD_ID_NO_CLR(c2h_pkt, value)               \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_SEQ(c2h_pkt)                                \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)\n#define C2H_SPECIAL_STATISTICS_SET_SEQ(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_SPECIAL_STATISTICS_SET_SEQ_NO_CLR(c2h_pkt, value)                  \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(c2h_pkt)                     \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)\n#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(c2h_pkt, value)              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)\n#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX_NO_CLR(c2h_pkt, value)       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_DATA0(c2h_pkt)                              \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)\n#define C2H_SPECIAL_STATISTICS_SET_DATA0(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_SPECIAL_STATISTICS_SET_DATA0_NO_CLR(c2h_pkt, value)                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_DATA1(c2h_pkt)                              \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)\n#define C2H_SPECIAL_STATISTICS_SET_DATA1(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define C2H_SPECIAL_STATISTICS_SET_DATA1_NO_CLR(c2h_pkt, value)                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_DATA2(c2h_pkt)                              \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)\n#define C2H_SPECIAL_STATISTICS_SET_DATA2(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define C2H_SPECIAL_STATISTICS_SET_DATA2_NO_CLR(c2h_pkt, value)                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_DATA3(c2h_pkt)                              \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)\n#define C2H_SPECIAL_STATISTICS_SET_DATA3(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)\n#define C2H_SPECIAL_STATISTICS_SET_DATA3_NO_CLR(c2h_pkt, value)                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_DATA4(c2h_pkt)                              \\\n\tGET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)\n#define C2H_SPECIAL_STATISTICS_SET_DATA4(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)\n#define C2H_SPECIAL_STATISTICS_SET_DATA4_NO_CLR(c2h_pkt, value)                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_DATA5(c2h_pkt)                              \\\n\tGET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)\n#define C2H_SPECIAL_STATISTICS_SET_DATA5(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)\n#define C2H_SPECIAL_STATISTICS_SET_DATA5_NO_CLR(c2h_pkt, value)                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_DATA6(c2h_pkt)                              \\\n\tGET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)\n#define C2H_SPECIAL_STATISTICS_SET_DATA6(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)\n#define C2H_SPECIAL_STATISTICS_SET_DATA6_NO_CLR(c2h_pkt, value)                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_DATA7(c2h_pkt)                              \\\n\tGET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)\n#define C2H_SPECIAL_STATISTICS_SET_DATA7(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)\n#define C2H_SPECIAL_STATISTICS_SET_DATA7_NO_CLR(c2h_pkt, value)                \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_LEN(c2h_pkt)                                \\\n\tGET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)\n#define C2H_SPECIAL_STATISTICS_SET_LEN(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_SPECIAL_STATISTICS_SET_LEN_NO_CLR(c2h_pkt, value)                  \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(c2h_pkt)                            \\\n\tGET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)\n#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_SPECIAL_STATISTICS_SET_TRIGGER_NO_CLR(c2h_pkt, value)              \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_RA_PARA_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)\n#define C2H_RA_PARA_RPT_SET_CMD_ID(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_RA_PARA_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_RA_PARA_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)\n#define C2H_RA_PARA_RPT_SET_SEQ(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_RA_PARA_RPT_SET_SEQ_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_RA_PARA_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)\n#define C2H_RA_PARA_RPT_SET_LEN(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_RA_PARA_RPT_SET_LEN_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_RA_PARA_RPT_GET_TRIGGER(c2h_pkt)                                   \\\n\tGET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)\n#define C2H_RA_PARA_RPT_SET_TRIGGER(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_RA_PARA_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_CUR_CHANNEL_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)\n#define C2H_CUR_CHANNEL_SET_CMD_ID(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_CUR_CHANNEL_SET_CMD_ID_NO_CLR(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_CUR_CHANNEL_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)\n#define C2H_CUR_CHANNEL_SET_SEQ(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_CUR_CHANNEL_SET_SEQ_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(c2h_pkt)                               \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)\n#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)\n#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM_NO_CLR(c2h_pkt, value)                 \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)\n#define C2H_CUR_CHANNEL_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)\n#define C2H_CUR_CHANNEL_SET_LEN(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_CUR_CHANNEL_SET_LEN_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_CUR_CHANNEL_GET_TRIGGER(c2h_pkt)                                   \\\n\tGET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)\n#define C2H_CUR_CHANNEL_SET_TRIGGER(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_CUR_CHANNEL_SET_TRIGGER_NO_CLR(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_GPIO_WAKEUP_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)\n#define C2H_GPIO_WAKEUP_SET_CMD_ID(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_GPIO_WAKEUP_SET_CMD_ID_NO_CLR(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_GPIO_WAKEUP_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)\n#define C2H_GPIO_WAKEUP_SET_SEQ(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_GPIO_WAKEUP_SET_SEQ_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_GPIO_WAKEUP_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)\n#define C2H_GPIO_WAKEUP_SET_LEN(c2h_pkt, value)                                \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_GPIO_WAKEUP_SET_LEN_NO_CLR(c2h_pkt, value)                         \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_GPIO_WAKEUP_GET_TRIGGER(c2h_pkt)                                   \\\n\tGET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)\n#define C2H_GPIO_WAKEUP_SET_TRIGGER(c2h_pkt, value)                            \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_GPIO_WAKEUP_SET_TRIGGER_NO_CLR(c2h_pkt, value)                     \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_DROPID_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)\n#define C2H_DROPID_RPT_SET_CMD_ID(c2h_pkt, value)                              \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_DROPID_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value)                       \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_DROPID_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)\n#define C2H_DROPID_RPT_SET_SEQ(c2h_pkt, value)                                 \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_DROPID_RPT_SET_SEQ_NO_CLR(c2h_pkt, value)                          \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_DROPID_RPT_GET_DROPIDBIT(c2h_pkt)                                  \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 16, 4)\n#define C2H_DROPID_RPT_SET_DROPIDBIT(c2h_pkt, value)                           \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 4, value)\n#define C2H_DROPID_RPT_SET_DROPIDBIT_NO_CLR(c2h_pkt, value)                    \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 4, value)\n#define C2H_DROPID_RPT_GET_CURDROPID(c2h_pkt)                                  \\\n\tGET_C2H_FIELD(c2h_pkt + 0X00, 20, 2)\n#define C2H_DROPID_RPT_SET_CURDROPID(c2h_pkt, value)                           \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X00, 20, 2, value)\n#define C2H_DROPID_RPT_SET_CURDROPID_NO_CLR(c2h_pkt, value)                    \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 20, 2, value)\n#define C2H_DROPID_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)\n#define C2H_DROPID_RPT_SET_MACID(c2h_pkt, value)                               \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define C2H_DROPID_RPT_SET_MACID_NO_CLR(c2h_pkt, value)                        \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)\n#define C2H_DROPID_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)\n#define C2H_DROPID_RPT_SET_LEN(c2h_pkt, value)                                 \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_DROPID_RPT_SET_LEN_NO_CLR(c2h_pkt, value)                          \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_DROPID_RPT_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)\n#define C2H_DROPID_RPT_SET_TRIGGER(c2h_pkt, value)                             \\\n\tSET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_DROPID_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value)                      \\\n\tSET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_original_c2h_nic.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_\n#define _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_\n#define CMD_ID_C2H 0X00\n#define CMD_ID_DBG 0X00\n#define CMD_ID_C2H_LB 0X01\n#define CMD_ID_C2H_SND_TXBF 0X02\n#define CMD_ID_C2H_CCX_RPT 0X03\n#define CMD_ID_C2H_AP_REQ_TXRPT 0X04\n#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05\n#define CMD_ID_C2H_RA_RPT 0X0C\n#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D\n#define CMD_ID_C2H_RA_PARA_RPT 0X0E\n#define CMD_ID_C2H_CUR_CHANNEL 0X10\n#define CMD_ID_C2H_GPIO_WAKEUP 0X14\n#define CMD_ID_C2H_DROPID_RPT 0X2D\n#define C2H_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)\n#define C2H_SET_CMD_ID(c2h_pkt, value)                                         \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)\n#define C2H_SET_SEQ(c2h_pkt, value)                                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)\n#define DBG_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)\n#define DBG_SET_CMD_ID(c2h_pkt, value)                                         \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)\n#define DBG_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)\n#define DBG_SET_SEQ(c2h_pkt, value)                                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)\n#define DBG_GET_DBG_STR1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)\n#define DBG_SET_DBG_STR1(c2h_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)\n#define DBG_GET_DBG_STR2(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)\n#define DBG_SET_DBG_STR2(c2h_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)\n#define DBG_GET_DBG_STR3(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)\n#define DBG_SET_DBG_STR3(c2h_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)\n#define DBG_GET_DBG_STR4(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)\n#define DBG_SET_DBG_STR4(c2h_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)\n#define DBG_GET_DBG_STR5(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)\n#define DBG_SET_DBG_STR5(c2h_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)\n#define DBG_GET_DBG_STR6(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)\n#define DBG_SET_DBG_STR6(c2h_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)\n#define DBG_GET_DBG_STR7(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)\n#define DBG_SET_DBG_STR7(c2h_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)\n#define DBG_GET_DBG_STR8(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)\n#define DBG_SET_DBG_STR8(c2h_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)\n#define DBG_GET_DBG_STR9(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)\n#define DBG_SET_DBG_STR9(c2h_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)\n#define DBG_GET_DBG_STR10(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8)\n#define DBG_SET_DBG_STR10(c2h_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value)\n#define DBG_GET_DBG_STR11(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8)\n#define DBG_SET_DBG_STR11(c2h_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value)\n#define DBG_GET_DBG_STR12(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8)\n#define DBG_SET_DBG_STR12(c2h_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value)\n#define DBG_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)\n#define DBG_SET_LEN(c2h_pkt, value)                                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)\n#define DBG_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)\n#define DBG_SET_TRIGGER(c2h_pkt, value)                                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_LB_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)\n#define C2H_LB_SET_CMD_ID(c2h_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_LB_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)\n#define C2H_LB_SET_SEQ(c2h_pkt, value)                                         \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_LB_GET_PAYLOAD1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 16)\n#define C2H_LB_SET_PAYLOAD1(c2h_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 16, value)\n#define C2H_LB_GET_PAYLOAD2(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 32)\n#define C2H_LB_SET_PAYLOAD2(c2h_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 32, value)\n#define C2H_LB_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)\n#define C2H_LB_SET_LEN(c2h_pkt, value)                                         \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_LB_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)\n#define C2H_LB_SET_TRIGGER(c2h_pkt, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_SND_TXBF_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)\n#define C2H_SND_TXBF_SET_CMD_ID(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_SND_TXBF_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)\n#define C2H_SND_TXBF_SET_SEQ(c2h_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_SND_TXBF_GET_SND_RESULT(c2h_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 1)\n#define C2H_SND_TXBF_SET_SND_RESULT(c2h_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 1, value)\n#define C2H_SND_TXBF_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)\n#define C2H_SND_TXBF_SET_LEN(c2h_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_SND_TXBF_GET_TRIGGER(c2h_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)\n#define C2H_SND_TXBF_SET_TRIGGER(c2h_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_CCX_RPT_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)\n#define C2H_CCX_RPT_SET_CMD_ID(c2h_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_CCX_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)\n#define C2H_CCX_RPT_SET_SEQ(c2h_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_CCX_RPT_GET_QSEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 5)\n#define C2H_CCX_RPT_SET_QSEL(c2h_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 5, value)\n#define C2H_CCX_RPT_GET_BMC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 21, 1)\n#define C2H_CCX_RPT_SET_BMC(c2h_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 21, 1, value)\n#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(c2h_pkt)                                \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 22, 1)\n#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(c2h_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 22, 1, value)\n#define C2H_CCX_RPT_GET_RETRY_OVER(c2h_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 23, 1)\n#define C2H_CCX_RPT_SET_RETRY_OVER(c2h_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 23, 1, value)\n#define C2H_CCX_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)\n#define C2H_CCX_RPT_SET_MACID(c2h_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(c2h_pkt)                                \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 6)\n#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(c2h_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 6, value)\n#define C2H_CCX_RPT_GET_QUEUE7_0(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)\n#define C2H_CCX_RPT_SET_QUEUE7_0(c2h_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)\n#define C2H_CCX_RPT_GET_QUEUE15_8(c2h_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)\n#define C2H_CCX_RPT_SET_QUEUE15_8(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)\n#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt)                               \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)\n#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)\n#define C2H_CCX_RPT_GET_SW_DEFINE_0(c2h_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)\n#define C2H_CCX_RPT_SET_SW_DEFINE_0(c2h_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)\n#define C2H_CCX_RPT_GET_SW_DEFINE_1(c2h_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 4)\n#define C2H_CCX_RPT_SET_SW_DEFINE_1(c2h_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 4, value)\n#define C2H_CCX_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)\n#define C2H_CCX_RPT_SET_LEN(c2h_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_CCX_RPT_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)\n#define C2H_CCX_RPT_SET_TRIGGER(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_CMD_ID(c2h_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)\n#define C2H_AP_REQ_TXRPT_SET_CMD_ID(c2h_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)\n#define C2H_AP_REQ_TXRPT_SET_SEQ(c2h_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(c2h_pkt)                               \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)\n#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(c2h_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(c2h_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)\n#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(c2h_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(c2h_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)\n#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(c2h_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(c2h_pkt)                               \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)\n#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(c2h_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(c2h_pkt)                               \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)\n#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(c2h_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(c2h_pkt)                            \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)\n#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(c2h_pkt, value)                     \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(c2h_pkt)                               \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)\n#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(c2h_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(c2h_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)\n#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(c2h_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(c2h_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)\n#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(c2h_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(c2h_pkt)                               \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8)\n#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(c2h_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(c2h_pkt)                               \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8)\n#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(c2h_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(c2h_pkt)                            \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8)\n#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(c2h_pkt, value)                     \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_LEN(c2h_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)\n#define C2H_AP_REQ_TXRPT_SET_LEN(c2h_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_AP_REQ_TXRPT_GET_TRIGGER(c2h_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)\n#define C2H_AP_REQ_TXRPT_SET_TRIGGER(c2h_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(c2h_pkt)                        \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(c2h_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(c2h_pkt)                           \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(c2h_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(c2h_pkt)                 \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 7)\n#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(c2h_pkt, value)          \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 7, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(c2h_pkt)                 \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(c2h_pkt, value)          \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(c2h_pkt)                 \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(c2h_pkt, value)          \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(c2h_pkt)                 \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(c2h_pkt, value)          \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(c2h_pkt)                 \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(c2h_pkt, value)          \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(c2h_pkt)                 \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(c2h_pkt, value)          \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(c2h_pkt)                 \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(c2h_pkt, value)          \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(c2h_pkt)                 \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(c2h_pkt, value)          \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(c2h_pkt)                           \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(c2h_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(c2h_pkt)                       \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)\n#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(c2h_pkt, value)                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_RA_RPT_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)\n#define C2H_RA_RPT_SET_CMD_ID(c2h_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_RA_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)\n#define C2H_RA_RPT_SET_SEQ(c2h_pkt, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_RA_RPT_GET_RATE(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)\n#define C2H_RA_RPT_SET_RATE(c2h_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)\n#define C2H_RA_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)\n#define C2H_RA_RPT_SET_MACID(c2h_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_RA_RPT_GET_USE_LDPC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 1)\n#define C2H_RA_RPT_SET_USE_LDPC(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 1, value)\n#define C2H_RA_RPT_GET_USE_TXBF(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 1, 1)\n#define C2H_RA_RPT_SET_USE_TXBF(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 1, 1, value)\n#define C2H_RA_RPT_GET_COLLISION_STATE(c2h_pkt)                                \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)\n#define C2H_RA_RPT_SET_COLLISION_STATE(c2h_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)\n#define C2H_RA_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)\n#define C2H_RA_RPT_SET_LEN(c2h_pkt, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_RA_RPT_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)\n#define C2H_RA_RPT_SET_TRIGGER(c2h_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(c2h_pkt)                             \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)\n#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(c2h_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_SEQ(c2h_pkt)                                \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)\n#define C2H_SPECIAL_STATISTICS_SET_SEQ(c2h_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(c2h_pkt)                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)\n#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(c2h_pkt, value)              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_DATA0(c2h_pkt)                              \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)\n#define C2H_SPECIAL_STATISTICS_SET_DATA0(c2h_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_DATA1(c2h_pkt)                              \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)\n#define C2H_SPECIAL_STATISTICS_SET_DATA1(c2h_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_DATA2(c2h_pkt)                              \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)\n#define C2H_SPECIAL_STATISTICS_SET_DATA2(c2h_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_DATA3(c2h_pkt)                              \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)\n#define C2H_SPECIAL_STATISTICS_SET_DATA3(c2h_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_DATA4(c2h_pkt)                              \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)\n#define C2H_SPECIAL_STATISTICS_SET_DATA4(c2h_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_DATA5(c2h_pkt)                              \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)\n#define C2H_SPECIAL_STATISTICS_SET_DATA5(c2h_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_DATA6(c2h_pkt)                              \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)\n#define C2H_SPECIAL_STATISTICS_SET_DATA6(c2h_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_DATA7(c2h_pkt)                              \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)\n#define C2H_SPECIAL_STATISTICS_SET_DATA7(c2h_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_LEN(c2h_pkt)                                \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)\n#define C2H_SPECIAL_STATISTICS_SET_LEN(c2h_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(c2h_pkt)                            \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)\n#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(c2h_pkt, value)                     \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_RA_PARA_RPT_GET_CMD_ID(c2h_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)\n#define C2H_RA_PARA_RPT_SET_CMD_ID(c2h_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_RA_PARA_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)\n#define C2H_RA_PARA_RPT_SET_SEQ(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_RA_PARA_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)\n#define C2H_RA_PARA_RPT_SET_LEN(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_RA_PARA_RPT_GET_TRIGGER(c2h_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)\n#define C2H_RA_PARA_RPT_SET_TRIGGER(c2h_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_CUR_CHANNEL_GET_CMD_ID(c2h_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)\n#define C2H_CUR_CHANNEL_SET_CMD_ID(c2h_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_CUR_CHANNEL_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)\n#define C2H_CUR_CHANNEL_SET_SEQ(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(c2h_pkt)                               \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)\n#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(c2h_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)\n#define C2H_CUR_CHANNEL_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)\n#define C2H_CUR_CHANNEL_SET_LEN(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_CUR_CHANNEL_GET_TRIGGER(c2h_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)\n#define C2H_CUR_CHANNEL_SET_TRIGGER(c2h_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_GPIO_WAKEUP_GET_CMD_ID(c2h_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)\n#define C2H_GPIO_WAKEUP_SET_CMD_ID(c2h_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_GPIO_WAKEUP_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)\n#define C2H_GPIO_WAKEUP_SET_SEQ(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_GPIO_WAKEUP_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)\n#define C2H_GPIO_WAKEUP_SET_LEN(c2h_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_GPIO_WAKEUP_GET_TRIGGER(c2h_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)\n#define C2H_GPIO_WAKEUP_SET_TRIGGER(c2h_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)\n#define C2H_DROPID_RPT_GET_CMD_ID(c2h_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)\n#define C2H_DROPID_RPT_SET_CMD_ID(c2h_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)\n#define C2H_DROPID_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)\n#define C2H_DROPID_RPT_SET_SEQ(c2h_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)\n#define C2H_DROPID_RPT_GET_DROPIDBIT(c2h_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 4)\n#define C2H_DROPID_RPT_SET_DROPIDBIT(c2h_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 4, value)\n#define C2H_DROPID_RPT_GET_CURDROPID(c2h_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X00, 20, 2)\n#define C2H_DROPID_RPT_SET_CURDROPID(c2h_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 20, 2, value)\n#define C2H_DROPID_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)\n#define C2H_DROPID_RPT_SET_MACID(c2h_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)\n#define C2H_DROPID_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)\n#define C2H_DROPID_RPT_SET_LEN(c2h_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)\n#define C2H_DROPID_RPT_GET_TRIGGER(c2h_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)\n#define C2H_DROPID_RPT_SET_TRIGGER(c2h_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_original_h2c_ap.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HAL_ORIGINALH2CFORMAT_H2C_C2H_AP_H_\n#define _HAL_ORIGINALH2CFORMAT_H2C_C2H_AP_H_\n#define CMD_ID_ORIGINAL_H2C 0X00\n#define CMD_ID_H2C2H_LB 0X0\n#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06\n#define CMD_ID_RSVD_PAGE 0X0\n#define CMD_ID_MEDIA_STATUS_RPT 0X01\n#define CMD_ID_KEEP_ALIVE 0X03\n#define CMD_ID_DISCONNECT_DECISION 0X04\n#define CMD_ID_AP_OFFLOAD 0X08\n#define CMD_ID_BCN_RSVDPAGE 0X09\n#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A\n#define CMD_ID_SINGLE_CHANNELSWITCH 0X1C\n#define CMD_ID_SINGLE_CHANNELSWITCH_V2 0X1D\n#define CMD_ID_SET_PWR_MODE 0X00\n#define CMD_ID_PS_TUNING_PARA 0X01\n#define CMD_ID_PS_TUNING_PARA_II 0X02\n#define CMD_ID_PS_LPS_PARA 0X03\n#define CMD_ID_P2P_PS_OFFLOAD 0X04\n#define CMD_ID_PS_SCAN_EN 0X05\n#define CMD_ID_SAP_PS 0X06\n#define CMD_ID_INACTIVE_PS 0X07\n#define CMD_ID_MACID_CFG 0X00\n#define CMD_ID_TXBF 0X01\n#define CMD_ID_RSSI_SETTING 0X02\n#define CMD_ID_AP_REQ_TXRPT 0X03\n#define CMD_ID_INIT_RATE_COLLECTION 0X04\n#define CMD_ID_IQK_OFFLOAD 0X05\n#define CMD_ID_MACID_CFG_3SS 0X06\n#define CMD_ID_RA_PARA_ADJUST 0X07\n#define CMD_ID_WWLAN 0X00\n#define CMD_ID_REMOTE_WAKE_CTRL 0X01\n#define CMD_ID_AOAC_GLOBAL_INFO 0X02\n#define CMD_ID_AOAC_RSVD_PAGE 0X03\n#define CMD_ID_AOAC_RSVD_PAGE2 0X04\n#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05\n#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07\n#define CMD_ID_AOAC_RSVD_PAGE3 0X08\n#define CMD_ID_DBG_MSG_CTRL 0X1E\n#define CLASS_ORIGINAL_H2C 0X00\n#define CLASS_H2C2H_LB 0X07\n#define CLASS_D0_SCAN_OFFLOAD_CTRL 0X04\n#define CLASS_RSVD_PAGE 0X0\n#define CLASS_MEDIA_STATUS_RPT 0X0\n#define CLASS_KEEP_ALIVE 0X0\n#define CLASS_DISCONNECT_DECISION 0X0\n#define CLASS_AP_OFFLOAD 0X0\n#define CLASS_BCN_RSVDPAGE 0X0\n#define CLASS_PROBE_RSP_RSVDPAGE 0X0\n#define CLASS_SINGLE_CHANNELSWITCH 0X0\n#define CLASS_SINGLE_CHANNELSWITCH_V2 0X0\n#define CLASS_SET_PWR_MODE 0X01\n#define CLASS_PS_TUNING_PARA 0X01\n#define CLASS_PS_TUNING_PARA_II 0X01\n#define CLASS_PS_LPS_PARA 0X01\n#define CLASS_P2P_PS_OFFLOAD 0X01\n#define CLASS_PS_SCAN_EN 0X1\n#define CLASS_SAP_PS 0X1\n#define CLASS_INACTIVE_PS 0X1\n#define CLASS_MACID_CFG 0X2\n#define CLASS_TXBF 0X2\n#define CLASS_RSSI_SETTING 0X2\n#define CLASS_AP_REQ_TXRPT 0X2\n#define CLASS_INIT_RATE_COLLECTION 0X2\n#define CLASS_IQK_OFFLOAD 0X2\n#define CLASS_MACID_CFG_3SS 0X2\n#define CLASS_RA_PARA_ADJUST 0X02\n#define CLASS_WWLAN 0X4\n#define CLASS_REMOTE_WAKE_CTRL 0X4\n#define CLASS_AOAC_GLOBAL_INFO 0X04\n#define CLASS_AOAC_RSVD_PAGE 0X04\n#define CLASS_AOAC_RSVD_PAGE2 0X04\n#define CLASS_D0_SCAN_OFFLOAD_INFO 0X04\n#define CLASS_CHANNEL_SWITCH_OFFLOAD 0X04\n#define CLASS_AOAC_RSVD_PAGE3 0X04\n#define CLASS_DBG_MSG_CTRL 0X07\n#define ORIGINAL_H2C_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define ORIGINAL_H2C_SET_CMD_ID(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define ORIGINAL_H2C_SET_CMD_ID_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define ORIGINAL_H2C_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define ORIGINAL_H2C_SET_CLASS(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define ORIGINAL_H2C_SET_CLASS_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define H2C2H_LB_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define H2C2H_LB_SET_CMD_ID(h2c_pkt, value)                                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define H2C2H_LB_SET_CMD_ID_NO_CLR(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define H2C2H_LB_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define H2C2H_LB_SET_CLASS(h2c_pkt, value)                                     \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define H2C2H_LB_SET_CLASS_NO_CLR(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define H2C2H_LB_GET_SEQ(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define H2C2H_LB_SET_SEQ(h2c_pkt, value)                                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define H2C2H_LB_SET_SEQ_NO_CLR(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define H2C2H_LB_GET_PAYLOAD1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 16)\n#define H2C2H_LB_SET_PAYLOAD1(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 16, value)\n#define H2C2H_LB_SET_PAYLOAD1_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 16, value)\n#define H2C2H_LB_GET_PAYLOAD2(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 32)\n#define H2C2H_LB_SET_PAYLOAD2(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 32, value)\n#define H2C2H_LB_SET_PAYLOAD2_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 32, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(h2c_pkt)                       \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)\n#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN_NO_CLR(h2c_pkt, value)         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)\n#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(h2c_pkt)                       \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)\n#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)\n#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN_NO_CLR(h2c_pkt, value)         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)\n#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)\n#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 12, 1)\n#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value)\n#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(h2c_pkt)                     \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 17)\n#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(h2c_pkt, value)              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 17, value)\n#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET_NO_CLR(h2c_pkt, value)       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 17, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)\n#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)\n#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define RSVD_PAGE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define RSVD_PAGE_SET_CMD_ID(h2c_pkt, value)                                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define RSVD_PAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define RSVD_PAGE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define RSVD_PAGE_SET_CLASS(h2c_pkt, value)                                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define RSVD_PAGE_SET_CLASS_NO_CLR(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define RSVD_PAGE_GET_LOC_PROBE_RSP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define RSVD_PAGE_SET_LOC_PROBE_RSP(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define RSVD_PAGE_SET_LOC_PROBE_RSP_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define RSVD_PAGE_GET_LOC_PS_POLL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define RSVD_PAGE_SET_LOC_PS_POLL(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define RSVD_PAGE_SET_LOC_PS_POLL_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define RSVD_PAGE_GET_LOC_NULL_DATA(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)\n#define RSVD_PAGE_SET_LOC_NULL_DATA(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define RSVD_PAGE_SET_LOC_NULL_DATA_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define RSVD_PAGE_GET_LOC_QOS_NULL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)\n#define RSVD_PAGE_SET_LOC_QOS_NULL(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define RSVD_PAGE_SET_LOC_QOS_NULL_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(h2c_pkt)                                 \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)\n#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define RSVD_PAGE_SET_LOC_BT_QOS_NULL_NO_CLR(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define RSVD_PAGE_GET_LOC_CTS2SELF(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)\n#define RSVD_PAGE_SET_LOC_CTS2SELF(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)\n#define RSVD_PAGE_SET_LOC_CTS2SELF_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)\n#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(h2c_pkt)                             \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)\n#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)\n#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL_NO_CLR(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)\n#define MEDIA_STATUS_RPT_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define MEDIA_STATUS_RPT_SET_CMD_ID(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define MEDIA_STATUS_RPT_SET_CMD_ID_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define MEDIA_STATUS_RPT_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define MEDIA_STATUS_RPT_SET_CLASS(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define MEDIA_STATUS_RPT_SET_CLASS_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define MEDIA_STATUS_RPT_GET_OP_MODE(h2c_pkt)                                  \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)\n#define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define MEDIA_STATUS_RPT_SET_OP_MODE_NO_CLR(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define MEDIA_STATUS_RPT_GET_MACID_IN(h2c_pkt)                                 \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)\n#define MEDIA_STATUS_RPT_SET_MACID_IN(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define MEDIA_STATUS_RPT_SET_MACID_IN_NO_CLR(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define MEDIA_STATUS_RPT_GET_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define MEDIA_STATUS_RPT_SET_MACID_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define MEDIA_STATUS_RPT_GET_MACID_END(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)\n#define MEDIA_STATUS_RPT_SET_MACID_END(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define MEDIA_STATUS_RPT_SET_MACID_END_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define KEEP_ALIVE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define KEEP_ALIVE_SET_CMD_ID(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define KEEP_ALIVE_SET_CMD_ID_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define KEEP_ALIVE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define KEEP_ALIVE_SET_CLASS(h2c_pkt, value)                                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define KEEP_ALIVE_SET_CLASS_NO_CLR(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define KEEP_ALIVE_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)\n#define KEEP_ALIVE_SET_ENABLE(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define KEEP_ALIVE_SET_ENABLE_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(h2c_pkt)                             \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)\n#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define KEEP_ALIVE_SET_ADOPT_USER_SETTING_NO_CLR(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define KEEP_ALIVE_GET_PKT_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)\n#define KEEP_ALIVE_SET_PKT_TYPE(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)\n#define KEEP_ALIVE_SET_PKT_TYPE_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)\n#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define DISCONNECT_DECISION_GET_CMD_ID(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define DISCONNECT_DECISION_SET_CMD_ID(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define DISCONNECT_DECISION_SET_CMD_ID_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define DISCONNECT_DECISION_GET_CLASS(h2c_pkt)                                 \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define DISCONNECT_DECISION_SET_CLASS(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define DISCONNECT_DECISION_SET_CLASS_NO_CLR(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define DISCONNECT_DECISION_GET_ENABLE(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)\n#define DISCONNECT_DECISION_SET_ENABLE(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define DISCONNECT_DECISION_SET_ENABLE_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(h2c_pkt)                    \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)\n#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING_NO_CLR(h2c_pkt, value)      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt)              \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)\n#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt, value)       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)\n#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN_NO_CLR(h2c_pkt,       \\\n\t\t\t\t\t\t\t\tvalue)         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)\n#define DISCONNECT_DECISION_GET_DISCONNECT_EN(h2c_pkt)                         \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)\n#define DISCONNECT_DECISION_SET_DISCONNECT_EN(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)\n#define DISCONNECT_DECISION_SET_DISCONNECT_EN_NO_CLR(h2c_pkt, value)           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)\n#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt)          \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt, value)   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD_NO_CLR(h2c_pkt,   \\\n\t\t\t\t\t\t\t\t    value)     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)\n#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define DISCONNECT_DECISION_SET_TRY_PKT_NUM_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt)           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)\n#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt, value)    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT_NO_CLR(h2c_pkt,    \\\n\t\t\t\t\t\t\t\t   value)      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define AP_OFFLOAD_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define AP_OFFLOAD_SET_CMD_ID(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define AP_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define AP_OFFLOAD_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define AP_OFFLOAD_SET_CLASS(h2c_pkt, value)                                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define AP_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define AP_OFFLOAD_GET_ON(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)\n#define AP_OFFLOAD_SET_ON(h2c_pkt, value)                                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define AP_OFFLOAD_SET_ON_NO_CLR(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(h2c_pkt)                              \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)\n#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM_NO_CLR(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define AP_OFFLOAD_GET_LINKED(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)\n#define AP_OFFLOAD_SET_LINKED(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)\n#define AP_OFFLOAD_SET_LINKED_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)\n#define AP_OFFLOAD_GET_EN_AUTO_WAKE(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)\n#define AP_OFFLOAD_SET_EN_AUTO_WAKE(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)\n#define AP_OFFLOAD_SET_EN_AUTO_WAKE_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)\n#define AP_OFFLOAD_GET_WAKE_FLAG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1)\n#define AP_OFFLOAD_SET_WAKE_FLAG(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value)\n#define AP_OFFLOAD_SET_WAKE_FLAG_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value)\n#define AP_OFFLOAD_GET_HIDDEN_ROOT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 1)\n#define AP_OFFLOAD_SET_HIDDEN_ROOT(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 1, value)\n#define AP_OFFLOAD_SET_HIDDEN_ROOT_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 1, value)\n#define AP_OFFLOAD_GET_HIDDEN_VAP1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 17, 1)\n#define AP_OFFLOAD_SET_HIDDEN_VAP1(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 17, 1, value)\n#define AP_OFFLOAD_SET_HIDDEN_VAP1_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 17, 1, value)\n#define AP_OFFLOAD_GET_HIDDEN_VAP2(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 18, 1)\n#define AP_OFFLOAD_SET_HIDDEN_VAP2(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 18, 1, value)\n#define AP_OFFLOAD_SET_HIDDEN_VAP2_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 18, 1, value)\n#define AP_OFFLOAD_GET_HIDDEN_VAP3(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 19, 1)\n#define AP_OFFLOAD_SET_HIDDEN_VAP3(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 19, 1, value)\n#define AP_OFFLOAD_SET_HIDDEN_VAP3_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 19, 1, value)\n#define AP_OFFLOAD_GET_HIDDEN_VAP4(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 20, 1)\n#define AP_OFFLOAD_SET_HIDDEN_VAP4(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 20, 1, value)\n#define AP_OFFLOAD_SET_HIDDEN_VAP4_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 20, 1, value)\n#define AP_OFFLOAD_GET_DENYANY_ROOT(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 24, 1)\n#define AP_OFFLOAD_SET_DENYANY_ROOT(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 1, value)\n#define AP_OFFLOAD_SET_DENYANY_ROOT_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 1, value)\n#define AP_OFFLOAD_GET_DENYANY_VAP1(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 25, 1)\n#define AP_OFFLOAD_SET_DENYANY_VAP1(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 25, 1, value)\n#define AP_OFFLOAD_SET_DENYANY_VAP1_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 25, 1, value)\n#define AP_OFFLOAD_GET_DENYANY_VAP2(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 26, 1)\n#define AP_OFFLOAD_SET_DENYANY_VAP2(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 26, 1, value)\n#define AP_OFFLOAD_SET_DENYANY_VAP2_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 26, 1, value)\n#define AP_OFFLOAD_GET_DENYANY_VAP3(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 27, 1)\n#define AP_OFFLOAD_SET_DENYANY_VAP3(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 27, 1, value)\n#define AP_OFFLOAD_SET_DENYANY_VAP3_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 27, 1, value)\n#define AP_OFFLOAD_GET_DENYANY_VAP4(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 28, 1)\n#define AP_OFFLOAD_SET_DENYANY_VAP4(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 28, 1, value)\n#define AP_OFFLOAD_SET_DENYANY_VAP4_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 28, 1, value)\n#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(h2c_pkt)                                  \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)\n#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define AP_OFFLOAD_SET_WAIT_TBTT_CNT_NO_CLR(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define AP_OFFLOAD_GET_WAKE_TIMEOUT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)\n#define AP_OFFLOAD_SET_WAKE_TIMEOUT(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define AP_OFFLOAD_SET_WAKE_TIMEOUT_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define AP_OFFLOAD_GET_LEN_IV_PAIR(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)\n#define AP_OFFLOAD_SET_LEN_IV_PAIR(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)\n#define AP_OFFLOAD_SET_LEN_IV_PAIR_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)\n#define AP_OFFLOAD_GET_LEN_IV_GRP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)\n#define AP_OFFLOAD_SET_LEN_IV_GRP(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)\n#define AP_OFFLOAD_SET_LEN_IV_GRP_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)\n#define BCN_RSVDPAGE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define BCN_RSVDPAGE_SET_CMD_ID(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define BCN_RSVDPAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define BCN_RSVDPAGE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define BCN_RSVDPAGE_SET_CLASS(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define BCN_RSVDPAGE_SET_CLASS_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define BCN_RSVDPAGE_GET_LOC_ROOT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define BCN_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define BCN_RSVDPAGE_SET_LOC_ROOT_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define BCN_RSVDPAGE_GET_LOC_VAP1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define BCN_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define BCN_RSVDPAGE_SET_LOC_VAP1_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define BCN_RSVDPAGE_GET_LOC_VAP2(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)\n#define BCN_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define BCN_RSVDPAGE_SET_LOC_VAP2_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define BCN_RSVDPAGE_GET_LOC_VAP3(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)\n#define BCN_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define BCN_RSVDPAGE_SET_LOC_VAP3_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define BCN_RSVDPAGE_GET_LOC_VAP4(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)\n#define BCN_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define BCN_RSVDPAGE_SET_LOC_VAP4_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(h2c_pkt)                                 \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define PROBE_RSP_RSVDPAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define PROBE_RSP_RSVDPAGE_GET_CLASS(h2c_pkt)                                  \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define PROBE_RSP_RSVDPAGE_SET_CLASS(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define PROBE_RSP_RSVDPAGE_SET_CLASS_NO_CLR(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)\n#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)\n#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)\n#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define SINGLE_CHANNELSWITCH_GET_CMD_ID(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define SINGLE_CHANNELSWITCH_SET_CMD_ID(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define SINGLE_CHANNELSWITCH_SET_CMD_ID_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define SINGLE_CHANNELSWITCH_GET_CLASS(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define SINGLE_CHANNELSWITCH_SET_CLASS(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define SINGLE_CHANNELSWITCH_SET_CLASS_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define SINGLE_CHANNELSWITCH_GET_CHANNEL_NUM(h2c_pkt)                          \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define SINGLE_CHANNELSWITCH_SET_CHANNEL_NUM(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define SINGLE_CHANNELSWITCH_SET_CHANNEL_NUM_NO_CLR(h2c_pkt, value)            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define SINGLE_CHANNELSWITCH_GET_BW(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 2)\n#define SINGLE_CHANNELSWITCH_SET_BW(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 2, value)\n#define SINGLE_CHANNELSWITCH_SET_BW_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 2, value)\n#define SINGLE_CHANNELSWITCH_GET_BW40SC(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 18, 3)\n#define SINGLE_CHANNELSWITCH_SET_BW40SC(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 18, 3, value)\n#define SINGLE_CHANNELSWITCH_SET_BW40SC_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 18, 3, value)\n#define SINGLE_CHANNELSWITCH_GET_BW80SC(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 21, 3)\n#define SINGLE_CHANNELSWITCH_SET_BW80SC(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 21, 3, value)\n#define SINGLE_CHANNELSWITCH_SET_BW80SC_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 21, 3, value)\n#define SINGLE_CHANNELSWITCH_GET_RFE_TYPE(h2c_pkt)                             \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 24, 4)\n#define SINGLE_CHANNELSWITCH_SET_RFE_TYPE(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 4, value)\n#define SINGLE_CHANNELSWITCH_SET_RFE_TYPE_NO_CLR(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 4, value)\n#define SINGLE_CHANNELSWITCH_V2_GET_CMD_ID(h2c_pkt)                            \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define SINGLE_CHANNELSWITCH_V2_SET_CMD_ID(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define SINGLE_CHANNELSWITCH_V2_SET_CMD_ID_NO_CLR(h2c_pkt, value)              \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define SINGLE_CHANNELSWITCH_V2_GET_CLASS(h2c_pkt)                             \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define SINGLE_CHANNELSWITCH_V2_SET_CLASS(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define SINGLE_CHANNELSWITCH_V2_SET_CLASS_NO_CLR(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define SINGLE_CHANNELSWITCH_V2_GET_CENTRAL_CH(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define SINGLE_CHANNELSWITCH_V2_SET_CENTRAL_CH(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define SINGLE_CHANNELSWITCH_V2_SET_CENTRAL_CH_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define SINGLE_CHANNELSWITCH_V2_GET_PRIMARY_CH_IDX(h2c_pkt)                    \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 4)\n#define SINGLE_CHANNELSWITCH_V2_SET_PRIMARY_CH_IDX(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 4, value)\n#define SINGLE_CHANNELSWITCH_V2_SET_PRIMARY_CH_IDX_NO_CLR(h2c_pkt, value)      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 4, value)\n#define SINGLE_CHANNELSWITCH_V2_GET_BW(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 20, 4)\n#define SINGLE_CHANNELSWITCH_V2_SET_BW(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 20, 4, value)\n#define SINGLE_CHANNELSWITCH_V2_SET_BW_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 20, 4, value)\n#define SET_PWR_MODE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define SET_PWR_MODE_SET_CMD_ID(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define SET_PWR_MODE_SET_CMD_ID_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define SET_PWR_MODE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define SET_PWR_MODE_SET_CLASS(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define SET_PWR_MODE_SET_CLASS_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define SET_PWR_MODE_GET_MODE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 7)\n#define SET_PWR_MODE_SET_MODE(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 7, value)\n#define SET_PWR_MODE_SET_MODE_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 7, value)\n#define SET_PWR_MODE_GET_CLK_REQUEST(h2c_pkt)                                  \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 15, 1)\n#define SET_PWR_MODE_SET_CLK_REQUEST(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value)\n#define SET_PWR_MODE_SET_CLK_REQUEST_NO_CLR(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value)\n#define SET_PWR_MODE_GET_RLBM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 4)\n#define SET_PWR_MODE_SET_RLBM(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 4, value)\n#define SET_PWR_MODE_SET_RLBM_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 4, value)\n#define SET_PWR_MODE_GET_SMART_PS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 20, 4)\n#define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 20, 4, value)\n#define SET_PWR_MODE_SET_SMART_PS_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 20, 4, value)\n#define SET_PWR_MODE_GET_AWAKE_INTERVAL(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)\n#define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define SET_PWR_MODE_SET_AWAKE_INTERVAL_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(h2c_pkt)                            \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 0, 1)\n#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 1, value)\n#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD_NO_CLR(h2c_pkt, value)              \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 1, value)\n#define SET_PWR_MODE_GET_BCN_EARLY_RPT(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 2, 1)\n#define SET_PWR_MODE_SET_BCN_EARLY_RPT(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 2, 1, value)\n#define SET_PWR_MODE_SET_BCN_EARLY_RPT_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 2, 1, value)\n#define SET_PWR_MODE_GET_PORT_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 5, 3)\n#define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 5, 3, value)\n#define SET_PWR_MODE_SET_PORT_ID_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 5, 3, value)\n#define SET_PWR_MODE_GET_PWR_STATE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)\n#define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define SET_PWR_MODE_SET_PWR_STATE_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define SET_PWR_MODE_GET_RSVD_NOUSED(h2c_pkt)                                  \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)\n#define SET_PWR_MODE_SET_RSVD_NOUSED(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)\n#define SET_PWR_MODE_SET_RSVD_NOUSED_NO_CLR(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)\n#define SET_PWR_MODE_GET_BCN_RECEIVING_TIME(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 24, 5)\n#define SET_PWR_MODE_SET_BCN_RECEIVING_TIME(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 5, value)\n#define SET_PWR_MODE_SET_BCN_RECEIVING_TIME_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 5, value)\n#define SET_PWR_MODE_GET_BCN_LISTEN_INTERVAL(h2c_pkt)                          \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 29, 2)\n#define SET_PWR_MODE_SET_BCN_LISTEN_INTERVAL(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 29, 2, value)\n#define SET_PWR_MODE_SET_BCN_LISTEN_INTERVAL_NO_CLR(h2c_pkt, value)            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 29, 2, value)\n#define SET_PWR_MODE_GET_ADOPT_BCN_RECEIVING_TIME(h2c_pkt)                     \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 31, 1)\n#define SET_PWR_MODE_SET_ADOPT_BCN_RECEIVING_TIME(h2c_pkt, value)              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 31, 1, value)\n#define SET_PWR_MODE_SET_ADOPT_BCN_RECEIVING_TIME_NO_CLR(h2c_pkt, value)       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 31, 1, value)\n#define PS_TUNING_PARA_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define PS_TUNING_PARA_SET_CMD_ID(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define PS_TUNING_PARA_SET_CMD_ID_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define PS_TUNING_PARA_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define PS_TUNING_PARA_SET_CLASS(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define PS_TUNING_PARA_SET_CLASS_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 8, 7)\n#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 7, value)\n#define PS_TUNING_PARA_SET_BCN_TO_LIMIT_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 7, value)\n#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(h2c_pkt)                              \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 15, 1)\n#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value)\n#define PS_TUNING_PARA_SET_DTIM_TIME_OUT_NO_CLR(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value)\n#define PS_TUNING_PARA_GET_PS_TIME_OUT(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 4)\n#define PS_TUNING_PARA_SET_PS_TIME_OUT(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 4, value)\n#define PS_TUNING_PARA_SET_PS_TIME_OUT_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 4, value)\n#define PS_TUNING_PARA_GET_ADOPT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)\n#define PS_TUNING_PARA_SET_ADOPT(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define PS_TUNING_PARA_SET_ADOPT_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define PS_TUNING_PARA_II_GET_CMD_ID(h2c_pkt)                                  \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define PS_TUNING_PARA_II_SET_CMD_ID(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define PS_TUNING_PARA_II_SET_CMD_ID_NO_CLR(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define PS_TUNING_PARA_II_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define PS_TUNING_PARA_II_SET_CLASS(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define PS_TUNING_PARA_II_SET_CLASS_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 8, 7)\n#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 7, value)\n#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 7, value)\n#define PS_TUNING_PARA_II_GET_ADOPT(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 15, 1)\n#define PS_TUNING_PARA_II_SET_ADOPT(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value)\n#define PS_TUNING_PARA_II_SET_ADOPT_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value)\n#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define PS_LPS_PARA_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define PS_LPS_PARA_SET_CMD_ID(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define PS_LPS_PARA_SET_CMD_ID_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define PS_LPS_PARA_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define PS_LPS_PARA_SET_CLASS(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define PS_LPS_PARA_SET_CLASS_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define PS_LPS_PARA_GET_LPS_CONTROL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define PS_LPS_PARA_SET_LPS_CONTROL(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define PS_LPS_PARA_SET_LPS_CONTROL_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define P2P_PS_OFFLOAD_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define P2P_PS_OFFLOAD_SET_CMD_ID(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define P2P_PS_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define P2P_PS_OFFLOAD_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define P2P_PS_OFFLOAD_SET_CLASS(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define P2P_PS_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(h2c_pkt)                                 \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)\n#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN_NO_CLR(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define P2P_PS_OFFLOAD_GET_ROLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)\n#define P2P_PS_OFFLOAD_SET_ROLE(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define P2P_PS_OFFLOAD_SET_ROLE_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)\n#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)\n#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)\n#define P2P_PS_OFFLOAD_GET_NOA0_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)\n#define P2P_PS_OFFLOAD_SET_NOA0_EN(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)\n#define P2P_PS_OFFLOAD_SET_NOA0_EN_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)\n#define P2P_PS_OFFLOAD_GET_NOA1_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1)\n#define P2P_PS_OFFLOAD_SET_NOA1_EN(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value)\n#define P2P_PS_OFFLOAD_SET_NOA1_EN_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value)\n#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(h2c_pkt)                              \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 13, 1)\n#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 13, 1, value)\n#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP_NO_CLR(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 13, 1, value)\n#define P2P_PS_OFFLOAD_GET_DISCOVERY(h2c_pkt)                                  \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 14, 1)\n#define P2P_PS_OFFLOAD_SET_DISCOVERY(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 14, 1, value)\n#define P2P_PS_OFFLOAD_SET_DISCOVERY_NO_CLR(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 14, 1, value)\n#define PS_SCAN_EN_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define PS_SCAN_EN_SET_CMD_ID(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define PS_SCAN_EN_SET_CMD_ID_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define PS_SCAN_EN_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define PS_SCAN_EN_SET_CLASS(h2c_pkt, value)                                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define PS_SCAN_EN_SET_CLASS_NO_CLR(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define PS_SCAN_EN_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)\n#define PS_SCAN_EN_SET_ENABLE(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define PS_SCAN_EN_SET_ENABLE_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define SAP_PS_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define SAP_PS_SET_CMD_ID(h2c_pkt, value)                                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define SAP_PS_SET_CMD_ID_NO_CLR(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define SAP_PS_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define SAP_PS_SET_CLASS(h2c_pkt, value)                                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define SAP_PS_SET_CLASS_NO_CLR(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define SAP_PS_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)\n#define SAP_PS_SET_ENABLE(h2c_pkt, value)                                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define SAP_PS_SET_ENABLE_NO_CLR(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define SAP_PS_GET_EN_PS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)\n#define SAP_PS_SET_EN_PS(h2c_pkt, value)                                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define SAP_PS_SET_EN_PS_NO_CLR(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define SAP_PS_GET_EN_LP_RX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)\n#define SAP_PS_SET_EN_LP_RX(h2c_pkt, value)                                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)\n#define SAP_PS_SET_EN_LP_RX_NO_CLR(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)\n#define SAP_PS_GET_MANUAL_32K(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)\n#define SAP_PS_SET_MANUAL_32K(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)\n#define SAP_PS_SET_MANUAL_32K_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)\n#define SAP_PS_GET_DURATION(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define SAP_PS_SET_DURATION(h2c_pkt, value)                                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define SAP_PS_SET_DURATION_NO_CLR(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define INACTIVE_PS_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define INACTIVE_PS_SET_CMD_ID(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define INACTIVE_PS_SET_CMD_ID_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define INACTIVE_PS_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define INACTIVE_PS_SET_CLASS(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define INACTIVE_PS_SET_CLASS_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define INACTIVE_PS_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)\n#define INACTIVE_PS_SET_ENABLE(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define INACTIVE_PS_SET_ENABLE_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)\n#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define INACTIVE_PS_SET_IGNORE_PS_CONDITION_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define INACTIVE_PS_GET_FREQUENCY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define INACTIVE_PS_SET_FREQUENCY(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define INACTIVE_PS_SET_FREQUENCY_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define INACTIVE_PS_GET_DURATION(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)\n#define INACTIVE_PS_SET_DURATION(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define INACTIVE_PS_SET_DURATION_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define MACID_CFG_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define MACID_CFG_SET_CMD_ID(h2c_pkt, value)                                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define MACID_CFG_SET_CMD_ID_NO_CLR(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define MACID_CFG_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define MACID_CFG_SET_CLASS(h2c_pkt, value)                                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define MACID_CFG_SET_CLASS_NO_CLR(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define MACID_CFG_GET_MAC_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define MACID_CFG_SET_MAC_ID(h2c_pkt, value)                                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define MACID_CFG_SET_MAC_ID_NO_CLR(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define MACID_CFG_GET_RATE_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 5)\n#define MACID_CFG_SET_RATE_ID(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 5, value)\n#define MACID_CFG_SET_RATE_ID_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 5, value)\n#define MACID_CFG_GET_INIT_RATE_LV(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 21, 2)\n#define MACID_CFG_SET_INIT_RATE_LV(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 21, 2, value)\n#define MACID_CFG_SET_INIT_RATE_LV_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 21, 2, value)\n#define MACID_CFG_GET_SGI(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 23, 1)\n#define MACID_CFG_SET_SGI(h2c_pkt, value)                                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 23, 1, value)\n#define MACID_CFG_SET_SGI_NO_CLR(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 23, 1, value)\n#define MACID_CFG_GET_BW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 2)\n#define MACID_CFG_SET_BW(h2c_pkt, value)                                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 2, value)\n#define MACID_CFG_SET_BW_NO_CLR(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 2, value)\n#define MACID_CFG_GET_LDPC_CAP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 26, 1)\n#define MACID_CFG_SET_LDPC_CAP(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 26, 1, value)\n#define MACID_CFG_SET_LDPC_CAP_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 26, 1, value)\n#define MACID_CFG_GET_NO_UPDATE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 27, 1)\n#define MACID_CFG_SET_NO_UPDATE(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 27, 1, value)\n#define MACID_CFG_SET_NO_UPDATE_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 27, 1, value)\n#define MACID_CFG_GET_WHT_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 28, 2)\n#define MACID_CFG_SET_WHT_EN(h2c_pkt, value)                                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 28, 2, value)\n#define MACID_CFG_SET_WHT_EN_NO_CLR(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 28, 2, value)\n#define MACID_CFG_GET_DISPT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 30, 1)\n#define MACID_CFG_SET_DISPT(h2c_pkt, value)                                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 30, 1, value)\n#define MACID_CFG_SET_DISPT_NO_CLR(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 30, 1, value)\n#define MACID_CFG_GET_DISRA(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 31, 1)\n#define MACID_CFG_SET_DISRA(h2c_pkt, value)                                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 31, 1, value)\n#define MACID_CFG_SET_DISRA_NO_CLR(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 31, 1, value)\n#define MACID_CFG_GET_RATE_MASK7_0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)\n#define MACID_CFG_SET_RATE_MASK7_0(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define MACID_CFG_SET_RATE_MASK7_0_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define MACID_CFG_GET_RATE_MASK15_8(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)\n#define MACID_CFG_SET_RATE_MASK15_8(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define MACID_CFG_SET_RATE_MASK15_8_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define MACID_CFG_GET_RATE_MASK23_16(h2c_pkt)                                  \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)\n#define MACID_CFG_SET_RATE_MASK23_16(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)\n#define MACID_CFG_SET_RATE_MASK23_16_NO_CLR(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)\n#define MACID_CFG_GET_RATE_MASK31_24(h2c_pkt)                                  \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)\n#define MACID_CFG_SET_RATE_MASK31_24(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)\n#define MACID_CFG_SET_RATE_MASK31_24_NO_CLR(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)\n#define TXBF_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define TXBF_SET_CMD_ID(h2c_pkt, value)                                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define TXBF_SET_CMD_ID_NO_CLR(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define TXBF_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define TXBF_SET_CLASS(h2c_pkt, value)                                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define TXBF_SET_CLASS_NO_CLR(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define TXBF_GET_NDPA0_HEAD_PAGE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define TXBF_SET_NDPA0_HEAD_PAGE(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define TXBF_SET_NDPA0_HEAD_PAGE_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define TXBF_GET_NDPA1_HEAD_PAGE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define TXBF_SET_NDPA1_HEAD_PAGE(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define TXBF_SET_NDPA1_HEAD_PAGE_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define TXBF_GET_PERIOD_0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)\n#define TXBF_SET_PERIOD_0(h2c_pkt, value)                                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define TXBF_SET_PERIOD_0_NO_CLR(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define RSSI_SETTING_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define RSSI_SETTING_SET_CMD_ID(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define RSSI_SETTING_SET_CMD_ID_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define RSSI_SETTING_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define RSSI_SETTING_SET_CLASS(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define RSSI_SETTING_SET_CLASS_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define RSSI_SETTING_GET_MAC_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define RSSI_SETTING_SET_MAC_ID(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define RSSI_SETTING_SET_MAC_ID_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define RSSI_SETTING_GET_RSSI(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 7)\n#define RSSI_SETTING_SET_RSSI(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 7, value)\n#define RSSI_SETTING_SET_RSSI_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 7, value)\n#define RSSI_SETTING_GET_RA_INFO(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)\n#define RSSI_SETTING_SET_RA_INFO(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define RSSI_SETTING_SET_RA_INFO_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define AP_REQ_TXRPT_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define AP_REQ_TXRPT_SET_CMD_ID(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define AP_REQ_TXRPT_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define AP_REQ_TXRPT_SET_CLASS(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define AP_REQ_TXRPT_SET_CLASS_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define AP_REQ_TXRPT_GET_STA1_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define AP_REQ_TXRPT_SET_STA1_MACID(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define AP_REQ_TXRPT_GET_STA2_MACID(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define AP_REQ_TXRPT_SET_STA2_MACID(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(h2c_pkt)                                 \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 24, 1)\n#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 1, value)\n#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL_NO_CLR(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 1, value)\n#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 25, 1)\n#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 25, 1, value)\n#define AP_REQ_TXRPT_SET_RTY_CNT_MACID_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 25, 1, value)\n#define INIT_RATE_COLLECTION_GET_CMD_ID(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define INIT_RATE_COLLECTION_SET_CMD_ID(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define INIT_RATE_COLLECTION_SET_CMD_ID_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define INIT_RATE_COLLECTION_GET_CLASS(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define INIT_RATE_COLLECTION_SET_CLASS(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define INIT_RATE_COLLECTION_SET_CLASS_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define INIT_RATE_COLLECTION_GET_STA1_MACID(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define INIT_RATE_COLLECTION_SET_STA1_MACID(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define INIT_RATE_COLLECTION_SET_STA1_MACID_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define INIT_RATE_COLLECTION_GET_STA2_MACID(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define INIT_RATE_COLLECTION_SET_STA2_MACID(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define INIT_RATE_COLLECTION_SET_STA2_MACID_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define INIT_RATE_COLLECTION_GET_STA3_MACID(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)\n#define INIT_RATE_COLLECTION_SET_STA3_MACID(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define INIT_RATE_COLLECTION_SET_STA3_MACID_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define INIT_RATE_COLLECTION_GET_STA4_MACID(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)\n#define INIT_RATE_COLLECTION_SET_STA4_MACID(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define INIT_RATE_COLLECTION_SET_STA4_MACID_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define INIT_RATE_COLLECTION_GET_STA5_MACID(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)\n#define INIT_RATE_COLLECTION_SET_STA5_MACID(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define INIT_RATE_COLLECTION_SET_STA5_MACID_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define INIT_RATE_COLLECTION_GET_STA6_MACID(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)\n#define INIT_RATE_COLLECTION_SET_STA6_MACID(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)\n#define INIT_RATE_COLLECTION_SET_STA6_MACID_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)\n#define INIT_RATE_COLLECTION_GET_STA7_MACID(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)\n#define INIT_RATE_COLLECTION_SET_STA7_MACID(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)\n#define INIT_RATE_COLLECTION_SET_STA7_MACID_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)\n#define IQK_OFFLOAD_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define IQK_OFFLOAD_SET_CMD_ID(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define IQK_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define IQK_OFFLOAD_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define IQK_OFFLOAD_SET_CLASS(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define IQK_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define IQK_OFFLOAD_GET_CHANNEL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define IQK_OFFLOAD_SET_CHANNEL(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define IQK_OFFLOAD_SET_CHANNEL_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define IQK_OFFLOAD_GET_BWBAND(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define IQK_OFFLOAD_SET_BWBAND(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define IQK_OFFLOAD_SET_BWBAND_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define IQK_OFFLOAD_GET_EXTPALNA(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)\n#define IQK_OFFLOAD_SET_EXTPALNA(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define IQK_OFFLOAD_SET_EXTPALNA_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define MACID_CFG_3SS_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define MACID_CFG_3SS_SET_CMD_ID(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define MACID_CFG_3SS_SET_CMD_ID_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define MACID_CFG_3SS_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define MACID_CFG_3SS_SET_CLASS(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define MACID_CFG_3SS_SET_CLASS_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define MACID_CFG_3SS_GET_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define MACID_CFG_3SS_SET_MACID(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define MACID_CFG_3SS_SET_MACID_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define MACID_CFG_3SS_GET_RATE_MASK_39_32(h2c_pkt)                             \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)\n#define MACID_CFG_3SS_SET_RATE_MASK_39_32(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define MACID_CFG_3SS_SET_RATE_MASK_39_32_NO_CLR(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define MACID_CFG_3SS_GET_RATE_MASK_47_40(h2c_pkt)                             \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)\n#define MACID_CFG_3SS_SET_RATE_MASK_47_40(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define MACID_CFG_3SS_SET_RATE_MASK_47_40_NO_CLR(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define RA_PARA_ADJUST_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define RA_PARA_ADJUST_SET_CMD_ID(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define RA_PARA_ADJUST_SET_CMD_ID_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define RA_PARA_ADJUST_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define RA_PARA_ADJUST_SET_CLASS(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define RA_PARA_ADJUST_SET_CLASS_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define RA_PARA_ADJUST_GET_MAC_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define RA_PARA_ADJUST_SET_MAC_ID(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define RA_PARA_ADJUST_SET_MAC_ID_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(h2c_pkt)                            \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define RA_PARA_ADJUST_SET_PARAMETER_INDEX_NO_CLR(h2c_pkt, value)              \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define RA_PARA_ADJUST_GET_RATE_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)\n#define RA_PARA_ADJUST_SET_RATE_ID(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define RA_PARA_ADJUST_SET_RATE_ID_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define RA_PARA_ADJUST_GET_VALUE_BYTE0(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)\n#define RA_PARA_ADJUST_SET_VALUE_BYTE0(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define RA_PARA_ADJUST_SET_VALUE_BYTE0_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define RA_PARA_ADJUST_GET_VALUE_BYTE1(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)\n#define RA_PARA_ADJUST_SET_VALUE_BYTE1(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define RA_PARA_ADJUST_SET_VALUE_BYTE1_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(h2c_pkt)                         \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)\n#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)\n#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA_NO_CLR(h2c_pkt, value)           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)\n#define WWLAN_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define WWLAN_SET_CMD_ID(h2c_pkt, value)                                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define WWLAN_SET_CMD_ID_NO_CLR(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define WWLAN_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define WWLAN_SET_CLASS(h2c_pkt, value)                                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define WWLAN_SET_CLASS_NO_CLR(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define WWLAN_GET_FUNC_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)\n#define WWLAN_SET_FUNC_EN(h2c_pkt, value)                                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define WWLAN_SET_FUNC_EN_NO_CLR(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define WWLAN_GET_PATTERM_MAT_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)\n#define WWLAN_SET_PATTERM_MAT_EN(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define WWLAN_SET_PATTERM_MAT_EN_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define WWLAN_GET_MAGIC_PKT_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)\n#define WWLAN_SET_MAGIC_PKT_EN(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)\n#define WWLAN_SET_MAGIC_PKT_EN_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)\n#define WWLAN_GET_UNICAST_WAKEUP_EN(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)\n#define WWLAN_SET_UNICAST_WAKEUP_EN(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)\n#define WWLAN_SET_UNICAST_WAKEUP_EN_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)\n#define WWLAN_GET_ALL_PKT_DROP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1)\n#define WWLAN_SET_ALL_PKT_DROP(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value)\n#define WWLAN_SET_ALL_PKT_DROP_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value)\n#define WWLAN_GET_GPIO_ACTIVE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 13, 1)\n#define WWLAN_SET_GPIO_ACTIVE(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 13, 1, value)\n#define WWLAN_SET_GPIO_ACTIVE_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 13, 1, value)\n#define WWLAN_GET_REKEY_WAKEUP_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 14, 1)\n#define WWLAN_SET_REKEY_WAKEUP_EN(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 14, 1, value)\n#define WWLAN_SET_REKEY_WAKEUP_EN_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 14, 1, value)\n#define WWLAN_GET_DEAUTH_WAKEUP_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1)\n#define WWLAN_SET_DEAUTH_WAKEUP_EN(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value)\n#define WWLAN_SET_DEAUTH_WAKEUP_EN_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value)\n#define WWLAN_GET_GPIO_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 7)\n#define WWLAN_SET_GPIO_NUM(h2c_pkt, value)                                     \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 7, value)\n#define WWLAN_SET_GPIO_NUM_NO_CLR(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 7, value)\n#define WWLAN_GET_DATAPIN_WAKEUP_EN(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 23, 1)\n#define WWLAN_SET_DATAPIN_WAKEUP_EN(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 23, 1, value)\n#define WWLAN_SET_DATAPIN_WAKEUP_EN_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 23, 1, value)\n#define WWLAN_GET_GPIO_DURATION(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)\n#define WWLAN_SET_GPIO_DURATION(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define WWLAN_SET_GPIO_DURATION_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define WWLAN_GET_GPIO_PLUS_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 1)\n#define WWLAN_SET_GPIO_PLUS_EN(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 1, value)\n#define WWLAN_SET_GPIO_PLUS_EN_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 1, value)\n#define WWLAN_GET_GPIO_PULSE_COUNT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 1, 7)\n#define WWLAN_SET_GPIO_PULSE_COUNT(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 1, 7, value)\n#define WWLAN_SET_GPIO_PULSE_COUNT_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 1, 7, value)\n#define WWLAN_GET_DISABLE_UPHY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 1)\n#define WWLAN_SET_DISABLE_UPHY(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 1, value)\n#define WWLAN_SET_DISABLE_UPHY_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 1, value)\n#define WWLAN_GET_HST2DEV_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 9, 1)\n#define WWLAN_SET_HST2DEV_EN(h2c_pkt, value)                                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 9, 1, value)\n#define WWLAN_SET_HST2DEV_EN_NO_CLR(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 9, 1, value)\n#define WWLAN_GET_GPIO_DURATION_MS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 10, 1)\n#define WWLAN_SET_GPIO_DURATION_MS(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 10, 1, value)\n#define WWLAN_SET_GPIO_DURATION_MS_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 10, 1, value)\n#define REMOTE_WAKE_CTRL_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define REMOTE_WAKE_CTRL_SET_CMD_ID(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define REMOTE_WAKE_CTRL_SET_CMD_ID_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define REMOTE_WAKE_CTRL_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define REMOTE_WAKE_CTRL_SET_CLASS(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define REMOTE_WAKE_CTRL_SET_CLASS_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(h2c_pkt)                      \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)\n#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN_NO_CLR(h2c_pkt, value)        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define REMOTE_WAKE_CTRL_GET_ARP_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)\n#define REMOTE_WAKE_CTRL_SET_ARP_EN(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define REMOTE_WAKE_CTRL_SET_ARP_EN_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)\n#define REMOTE_WAKE_CTRL_GET_NDP_EN(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)\n#define REMOTE_WAKE_CTRL_SET_NDP_EN(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)\n#define REMOTE_WAKE_CTRL_SET_NDP_EN_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)\n#define REMOTE_WAKE_CTRL_GET_GTK_EN(h2c_pkt)                                   \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)\n#define REMOTE_WAKE_CTRL_SET_GTK_EN(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)\n#define REMOTE_WAKE_CTRL_SET_GTK_EN_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)\n#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 12, 1)\n#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value)\n#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value)\n#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 13, 1)\n#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 13, 1, value)\n#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 13, 1, value)\n#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 14, 1)\n#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 14, 1, value)\n#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 14, 1, value)\n#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 15, 1)\n#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value)\n#define REMOTE_WAKE_CTRL_SET_FW_UNICAST_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value)\n#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 1)\n#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 1, value)\n#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 1, value)\n#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(h2c_pkt)                            \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 17, 1)\n#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 17, 1, value)\n#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN_NO_CLR(h2c_pkt, value)              \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 17, 1, value)\n#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(h2c_pkt)                         \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 18, 1)\n#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 18, 1, value)\n#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN_NO_CLR(h2c_pkt, value)           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 18, 1, value)\n#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 24, 1)\n#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 1, value)\n#define REMOTE_WAKE_CTRL_SET_ARP_ACTION_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 1, value)\n#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt)                  \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 28, 1)\n#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt, value)           \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 28, 1, value)\n#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP_NO_CLR(h2c_pkt, value)    \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 28, 1, value)\n#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(h2c_pkt)                  \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 29, 1)\n#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(h2c_pkt, value)           \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 29, 1, value)\n#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP_NO_CLR(h2c_pkt, value)    \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 29, 1, value)\n#define AOAC_GLOBAL_INFO_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define AOAC_GLOBAL_INFO_SET_CMD_ID(h2c_pkt, value)                            \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define AOAC_GLOBAL_INFO_SET_CMD_ID_NO_CLR(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define AOAC_GLOBAL_INFO_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define AOAC_GLOBAL_INFO_SET_CLASS(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define AOAC_GLOBAL_INFO_SET_CLASS_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(h2c_pkt)                            \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG_NO_CLR(h2c_pkt, value)              \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define AOAC_RSVD_PAGE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define AOAC_RSVD_PAGE_SET_CMD_ID(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define AOAC_RSVD_PAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define AOAC_RSVD_PAGE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define AOAC_RSVD_PAGE_SET_CLASS(h2c_pkt, value)                               \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define AOAC_RSVD_PAGE_SET_CLASS_NO_CLR(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(h2c_pkt)                       \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO_NO_CLR(h2c_pkt, value)         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt)                 \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)\n#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT_NO_CLR(h2c_pkt, value)   \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)\n#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)\n#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(h2c_pkt)                            \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)\n#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(h2c_pkt, value)                     \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)\n#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM_NO_CLR(h2c_pkt, value)              \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)\n#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)\n#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)\n#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)\n#define AOAC_RSVD_PAGE2_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define AOAC_RSVD_PAGE2_SET_CMD_ID(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define AOAC_RSVD_PAGE2_SET_CMD_ID_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define AOAC_RSVD_PAGE2_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define AOAC_RSVD_PAGE2_SET_CLASS(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define AOAC_RSVD_PAGE2_SET_CLASS_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(h2c_pkt)                     \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(h2c_pkt, value)              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION_NO_CLR(h2c_pkt, value)       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(h2c_pkt)                         \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET_NO_CLR(h2c_pkt, value)           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)\n#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(h2c_pkt)                          \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)\n#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(h2c_pkt, value)                   \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO_NO_CLR(h2c_pkt, value)            \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)\n#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)\n#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)\n#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)\n#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)\n#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)\n#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)\n#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)\n#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)\n#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(h2c_pkt)                               \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(h2c_pkt, value)                        \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID_NO_CLR(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(h2c_pkt)                                \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define D0_SCAN_OFFLOAD_INFO_SET_CLASS_NO_CLR(h2c_pkt, value)                  \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(h2c_pkt)                     \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(h2c_pkt, value)              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO_NO_CLR(h2c_pkt, value)       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(h2c_pkt)                             \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(h2c_pkt)                              \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(h2c_pkt)                        \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(h2c_pkt, value)                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM_NO_CLR(h2c_pkt, value)          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(h2c_pkt)                             \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE_NO_CLR(h2c_pkt, value)               \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)\n#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)\n#define AOAC_RSVD_PAGE3_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define AOAC_RSVD_PAGE3_SET_CMD_ID(h2c_pkt, value)                             \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define AOAC_RSVD_PAGE3_SET_CMD_ID_NO_CLR(h2c_pkt, value)                      \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define AOAC_RSVD_PAGE3_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define AOAC_RSVD_PAGE3_SET_CLASS(h2c_pkt, value)                              \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define AOAC_RSVD_PAGE3_SET_CLASS_NO_CLR(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(h2c_pkt)                              \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)\n#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(h2c_pkt, value)                       \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO_NO_CLR(h2c_pkt, value)                \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)\n#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(h2c_pkt)                           \\\n\tGET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)\n#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(h2c_pkt, value)                    \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT_NO_CLR(h2c_pkt, value)             \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)\n#define DBG_MSG_CTRL_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)\n#define DBG_MSG_CTRL_SET_CMD_ID(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define DBG_MSG_CTRL_SET_CMD_ID_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)\n#define DBG_MSG_CTRL_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)\n#define DBG_MSG_CTRL_SET_CLASS(h2c_pkt, value)                                 \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define DBG_MSG_CTRL_SET_CLASS_NO_CLR(h2c_pkt, value)                          \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)\n#define DBG_MSG_CTRL_GET_FUN_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)\n#define DBG_MSG_CTRL_SET_FUN_EN(h2c_pkt, value)                                \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define DBG_MSG_CTRL_SET_FUN_EN_NO_CLR(h2c_pkt, value)                         \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)\n#define DBG_MSG_CTRL_GET_MODE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 4)\n#define DBG_MSG_CTRL_SET_MODE(h2c_pkt, value)                                  \\\n\tSET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 4, value)\n#define DBG_MSG_CTRL_SET_MODE_NO_CLR(h2c_pkt, value)                           \\\n\tSET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 4, value)\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_original_h2c_nic.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_\n#define _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_\n#define CMD_ID_ORIGINAL_H2C 0X00\n#define CMD_ID_H2C2H_LB 0X0\n#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06\n#define CMD_ID_RSVD_PAGE 0X0\n#define CMD_ID_MEDIA_STATUS_RPT 0X01\n#define CMD_ID_KEEP_ALIVE 0X03\n#define CMD_ID_DISCONNECT_DECISION 0X04\n#define CMD_ID_AP_OFFLOAD 0X08\n#define CMD_ID_BCN_RSVDPAGE 0X09\n#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A\n#define CMD_ID_SINGLE_CHANNELSWITCH 0X1C\n#define CMD_ID_SINGLE_CHANNELSWITCH_V2 0X1D\n#define CMD_ID_SET_PWR_MODE 0X00\n#define CMD_ID_PS_TUNING_PARA 0X01\n#define CMD_ID_PS_TUNING_PARA_II 0X02\n#define CMD_ID_PS_LPS_PARA 0X03\n#define CMD_ID_P2P_PS_OFFLOAD 0X04\n#define CMD_ID_PS_SCAN_EN 0X05\n#define CMD_ID_SAP_PS 0X06\n#define CMD_ID_INACTIVE_PS 0X07\n#define CMD_ID_MACID_CFG 0X00\n#define CMD_ID_TXBF 0X01\n#define CMD_ID_RSSI_SETTING 0X02\n#define CMD_ID_AP_REQ_TXRPT 0X03\n#define CMD_ID_INIT_RATE_COLLECTION 0X04\n#define CMD_ID_IQK_OFFLOAD 0X05\n#define CMD_ID_MACID_CFG_3SS 0X06\n#define CMD_ID_RA_PARA_ADJUST 0X07\n#define CMD_ID_WWLAN 0X00\n#define CMD_ID_REMOTE_WAKE_CTRL 0X01\n#define CMD_ID_AOAC_GLOBAL_INFO 0X02\n#define CMD_ID_AOAC_RSVD_PAGE 0X03\n#define CMD_ID_AOAC_RSVD_PAGE2 0X04\n#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05\n#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07\n#define CMD_ID_AOAC_RSVD_PAGE3 0X08\n#define CMD_ID_DBG_MSG_CTRL 0X1E\n#define CLASS_ORIGINAL_H2C 0X00\n#define CLASS_H2C2H_LB 0X07\n#define CLASS_D0_SCAN_OFFLOAD_CTRL 0X04\n#define CLASS_RSVD_PAGE 0X0\n#define CLASS_MEDIA_STATUS_RPT 0X0\n#define CLASS_KEEP_ALIVE 0X0\n#define CLASS_DISCONNECT_DECISION 0X0\n#define CLASS_AP_OFFLOAD 0X0\n#define CLASS_BCN_RSVDPAGE 0X0\n#define CLASS_PROBE_RSP_RSVDPAGE 0X0\n#define CLASS_SINGLE_CHANNELSWITCH 0X0\n#define CLASS_SINGLE_CHANNELSWITCH_V2 0X0\n#define CLASS_SET_PWR_MODE 0X01\n#define CLASS_PS_TUNING_PARA 0X01\n#define CLASS_PS_TUNING_PARA_II 0X01\n#define CLASS_PS_LPS_PARA 0X01\n#define CLASS_P2P_PS_OFFLOAD 0X01\n#define CLASS_PS_SCAN_EN 0X1\n#define CLASS_SAP_PS 0X1\n#define CLASS_INACTIVE_PS 0X1\n#define CLASS_MACID_CFG 0X2\n#define CLASS_TXBF 0X2\n#define CLASS_RSSI_SETTING 0X2\n#define CLASS_AP_REQ_TXRPT 0X2\n#define CLASS_INIT_RATE_COLLECTION 0X2\n#define CLASS_IQK_OFFLOAD 0X2\n#define CLASS_MACID_CFG_3SS 0X2\n#define CLASS_RA_PARA_ADJUST 0X02\n#define CLASS_WWLAN 0X4\n#define CLASS_REMOTE_WAKE_CTRL 0X4\n#define CLASS_AOAC_GLOBAL_INFO 0X04\n#define CLASS_AOAC_RSVD_PAGE 0X04\n#define CLASS_AOAC_RSVD_PAGE2 0X04\n#define CLASS_D0_SCAN_OFFLOAD_INFO 0X04\n#define CLASS_CHANNEL_SWITCH_OFFLOAD 0X04\n#define CLASS_AOAC_RSVD_PAGE3 0X04\n#define CLASS_DBG_MSG_CTRL 0X07\n#define ORIGINAL_H2C_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define ORIGINAL_H2C_SET_CMD_ID(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define ORIGINAL_H2C_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define ORIGINAL_H2C_SET_CLASS(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define H2C2H_LB_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define H2C2H_LB_SET_CMD_ID(h2c_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define H2C2H_LB_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define H2C2H_LB_SET_CLASS(h2c_pkt, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define H2C2H_LB_GET_SEQ(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define H2C2H_LB_SET_SEQ(h2c_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define H2C2H_LB_GET_PAYLOAD1(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 16)\n#define H2C2H_LB_SET_PAYLOAD1(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 16, value)\n#define H2C2H_LB_GET_PAYLOAD2(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 32)\n#define H2C2H_LB_SET_PAYLOAD2(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 32, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(h2c_pkt)                       \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)\n#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(h2c_pkt, value)                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)\n#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(h2c_pkt)                       \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)\n#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(h2c_pkt, value)                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)\n#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1)\n#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(h2c_pkt)                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 17)\n#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(h2c_pkt, value)              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 17, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)\n#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)\n#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)\n#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)\n#define RSVD_PAGE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define RSVD_PAGE_SET_CMD_ID(h2c_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define RSVD_PAGE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define RSVD_PAGE_SET_CLASS(h2c_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define RSVD_PAGE_GET_LOC_PROBE_RSP(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define RSVD_PAGE_SET_LOC_PROBE_RSP(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define RSVD_PAGE_GET_LOC_PS_POLL(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define RSVD_PAGE_SET_LOC_PS_POLL(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define RSVD_PAGE_GET_LOC_NULL_DATA(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)\n#define RSVD_PAGE_SET_LOC_NULL_DATA(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)\n#define RSVD_PAGE_GET_LOC_QOS_NULL(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)\n#define RSVD_PAGE_SET_LOC_QOS_NULL(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)\n#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(h2c_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)\n#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(h2c_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)\n#define RSVD_PAGE_GET_LOC_CTS2SELF(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)\n#define RSVD_PAGE_SET_LOC_CTS2SELF(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)\n#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(h2c_pkt)                             \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)\n#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(h2c_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)\n#define MEDIA_STATUS_RPT_GET_CMD_ID(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define MEDIA_STATUS_RPT_SET_CMD_ID(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define MEDIA_STATUS_RPT_GET_CLASS(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define MEDIA_STATUS_RPT_SET_CLASS(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define MEDIA_STATUS_RPT_GET_OP_MODE(h2c_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)\n#define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)\n#define MEDIA_STATUS_RPT_GET_MACID_IN(h2c_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)\n#define MEDIA_STATUS_RPT_SET_MACID_IN(h2c_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)\n#define MEDIA_STATUS_RPT_GET_MACID(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define MEDIA_STATUS_RPT_GET_MACID_END(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)\n#define MEDIA_STATUS_RPT_SET_MACID_END(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)\n#define KEEP_ALIVE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define KEEP_ALIVE_SET_CMD_ID(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define KEEP_ALIVE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define KEEP_ALIVE_SET_CLASS(h2c_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define KEEP_ALIVE_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)\n#define KEEP_ALIVE_SET_ENABLE(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)\n#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(h2c_pkt)                             \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)\n#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(h2c_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)\n#define KEEP_ALIVE_GET_PKT_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)\n#define KEEP_ALIVE_SET_PKT_TYPE(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)\n#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define DISCONNECT_DECISION_GET_CMD_ID(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define DISCONNECT_DECISION_SET_CMD_ID(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define DISCONNECT_DECISION_GET_CLASS(h2c_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define DISCONNECT_DECISION_SET_CLASS(h2c_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define DISCONNECT_DECISION_GET_ENABLE(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)\n#define DISCONNECT_DECISION_SET_ENABLE(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)\n#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(h2c_pkt)                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)\n#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(h2c_pkt, value)             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)\n#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt)              \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)\n#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt, value)       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)\n#define DISCONNECT_DECISION_GET_DISCONNECT_EN(h2c_pkt)                         \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)\n#define DISCONNECT_DECISION_SET_DISCONNECT_EN(h2c_pkt, value)                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)\n#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt)          \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt, value)   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)\n#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)\n#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt)           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)\n#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt, value)    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)\n#define AP_OFFLOAD_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define AP_OFFLOAD_SET_CMD_ID(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define AP_OFFLOAD_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define AP_OFFLOAD_SET_CLASS(h2c_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define AP_OFFLOAD_GET_ON(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)\n#define AP_OFFLOAD_SET_ON(h2c_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)\n#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(h2c_pkt)                              \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)\n#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(h2c_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)\n#define AP_OFFLOAD_GET_LINKED(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)\n#define AP_OFFLOAD_SET_LINKED(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)\n#define AP_OFFLOAD_GET_EN_AUTO_WAKE(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)\n#define AP_OFFLOAD_SET_EN_AUTO_WAKE(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)\n#define AP_OFFLOAD_GET_WAKE_FLAG(h2c_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1)\n#define AP_OFFLOAD_SET_WAKE_FLAG(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value)\n#define AP_OFFLOAD_GET_HIDDEN_ROOT(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 1)\n#define AP_OFFLOAD_SET_HIDDEN_ROOT(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 1, value)\n#define AP_OFFLOAD_GET_HIDDEN_VAP1(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 17, 1)\n#define AP_OFFLOAD_SET_HIDDEN_VAP1(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 17, 1, value)\n#define AP_OFFLOAD_GET_HIDDEN_VAP2(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 18, 1)\n#define AP_OFFLOAD_SET_HIDDEN_VAP2(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 18, 1, value)\n#define AP_OFFLOAD_GET_HIDDEN_VAP3(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 19, 1)\n#define AP_OFFLOAD_SET_HIDDEN_VAP3(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 19, 1, value)\n#define AP_OFFLOAD_GET_HIDDEN_VAP4(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 20, 1)\n#define AP_OFFLOAD_SET_HIDDEN_VAP4(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 20, 1, value)\n#define AP_OFFLOAD_GET_DENYANY_ROOT(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 1)\n#define AP_OFFLOAD_SET_DENYANY_ROOT(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 1, value)\n#define AP_OFFLOAD_GET_DENYANY_VAP1(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 25, 1)\n#define AP_OFFLOAD_SET_DENYANY_VAP1(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 25, 1, value)\n#define AP_OFFLOAD_GET_DENYANY_VAP2(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 26, 1)\n#define AP_OFFLOAD_SET_DENYANY_VAP2(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 26, 1, value)\n#define AP_OFFLOAD_GET_DENYANY_VAP3(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 27, 1)\n#define AP_OFFLOAD_SET_DENYANY_VAP3(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 27, 1, value)\n#define AP_OFFLOAD_GET_DENYANY_VAP4(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 28, 1)\n#define AP_OFFLOAD_SET_DENYANY_VAP4(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 28, 1, value)\n#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(h2c_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)\n#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(h2c_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)\n#define AP_OFFLOAD_GET_WAKE_TIMEOUT(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)\n#define AP_OFFLOAD_SET_WAKE_TIMEOUT(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)\n#define AP_OFFLOAD_GET_LEN_IV_PAIR(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)\n#define AP_OFFLOAD_SET_LEN_IV_PAIR(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)\n#define AP_OFFLOAD_GET_LEN_IV_GRP(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)\n#define AP_OFFLOAD_SET_LEN_IV_GRP(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)\n#define BCN_RSVDPAGE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define BCN_RSVDPAGE_SET_CMD_ID(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define BCN_RSVDPAGE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define BCN_RSVDPAGE_SET_CLASS(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define BCN_RSVDPAGE_GET_LOC_ROOT(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define BCN_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define BCN_RSVDPAGE_GET_LOC_VAP1(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define BCN_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define BCN_RSVDPAGE_GET_LOC_VAP2(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)\n#define BCN_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)\n#define BCN_RSVDPAGE_GET_LOC_VAP3(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)\n#define BCN_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)\n#define BCN_RSVDPAGE_GET_LOC_VAP4(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)\n#define BCN_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)\n#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(h2c_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(h2c_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define PROBE_RSP_RSVDPAGE_GET_CLASS(h2c_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define PROBE_RSP_RSVDPAGE_SET_CLASS(h2c_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)\n#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)\n#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)\n#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)\n#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)\n#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)\n#define SINGLE_CHANNELSWITCH_GET_CMD_ID(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define SINGLE_CHANNELSWITCH_SET_CMD_ID(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define SINGLE_CHANNELSWITCH_GET_CLASS(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define SINGLE_CHANNELSWITCH_SET_CLASS(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define SINGLE_CHANNELSWITCH_GET_CHANNEL_NUM(h2c_pkt)                          \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define SINGLE_CHANNELSWITCH_SET_CHANNEL_NUM(h2c_pkt, value)                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define SINGLE_CHANNELSWITCH_GET_BW(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 2)\n#define SINGLE_CHANNELSWITCH_SET_BW(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 2, value)\n#define SINGLE_CHANNELSWITCH_GET_BW40SC(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 18, 3)\n#define SINGLE_CHANNELSWITCH_SET_BW40SC(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 18, 3, value)\n#define SINGLE_CHANNELSWITCH_GET_BW80SC(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 21, 3)\n#define SINGLE_CHANNELSWITCH_SET_BW80SC(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 21, 3, value)\n#define SINGLE_CHANNELSWITCH_GET_RFE_TYPE(h2c_pkt)                             \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 4)\n#define SINGLE_CHANNELSWITCH_SET_RFE_TYPE(h2c_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 4, value)\n#define SINGLE_CHANNELSWITCH_V2_GET_CMD_ID(h2c_pkt)                            \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define SINGLE_CHANNELSWITCH_V2_SET_CMD_ID(h2c_pkt, value)                     \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define SINGLE_CHANNELSWITCH_V2_GET_CLASS(h2c_pkt)                             \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define SINGLE_CHANNELSWITCH_V2_SET_CLASS(h2c_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define SINGLE_CHANNELSWITCH_V2_GET_CENTRAL_CH(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define SINGLE_CHANNELSWITCH_V2_SET_CENTRAL_CH(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define SINGLE_CHANNELSWITCH_V2_GET_PRIMARY_CH_IDX(h2c_pkt)                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 4)\n#define SINGLE_CHANNELSWITCH_V2_SET_PRIMARY_CH_IDX(h2c_pkt, value)             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 4, value)\n#define SINGLE_CHANNELSWITCH_V2_GET_BW(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 20, 4)\n#define SINGLE_CHANNELSWITCH_V2_SET_BW(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 20, 4, value)\n#define SET_PWR_MODE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define SET_PWR_MODE_SET_CMD_ID(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define SET_PWR_MODE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define SET_PWR_MODE_SET_CLASS(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define SET_PWR_MODE_GET_MODE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 7)\n#define SET_PWR_MODE_SET_MODE(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 7, value)\n#define SET_PWR_MODE_GET_CLK_REQUEST(h2c_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1)\n#define SET_PWR_MODE_SET_CLK_REQUEST(h2c_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value)\n#define SET_PWR_MODE_GET_RLBM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 4)\n#define SET_PWR_MODE_SET_RLBM(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 4, value)\n#define SET_PWR_MODE_GET_SMART_PS(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 20, 4)\n#define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 20, 4, value)\n#define SET_PWR_MODE_GET_AWAKE_INTERVAL(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)\n#define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)\n#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(h2c_pkt)                            \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 1)\n#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c_pkt, value)                     \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 1, value)\n#define SET_PWR_MODE_GET_BCN_EARLY_RPT(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 2, 1)\n#define SET_PWR_MODE_SET_BCN_EARLY_RPT(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 2, 1, value)\n#define SET_PWR_MODE_GET_PORT_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 5, 3)\n#define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 5, 3, value)\n#define SET_PWR_MODE_GET_PWR_STATE(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)\n#define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)\n#define SET_PWR_MODE_GET_RSVD_NOUSED(h2c_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)\n#define SET_PWR_MODE_SET_RSVD_NOUSED(h2c_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)\n#define SET_PWR_MODE_GET_BCN_RECEIVING_TIME(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 5)\n#define SET_PWR_MODE_SET_BCN_RECEIVING_TIME(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 5, value)\n#define SET_PWR_MODE_GET_BCN_LISTEN_INTERVAL(h2c_pkt)                          \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 29, 2)\n#define SET_PWR_MODE_SET_BCN_LISTEN_INTERVAL(h2c_pkt, value)                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 29, 2, value)\n#define SET_PWR_MODE_GET_ADOPT_BCN_RECEIVING_TIME(h2c_pkt)                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 31, 1)\n#define SET_PWR_MODE_SET_ADOPT_BCN_RECEIVING_TIME(h2c_pkt, value)              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 31, 1, value)\n#define PS_TUNING_PARA_GET_CMD_ID(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define PS_TUNING_PARA_SET_CMD_ID(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define PS_TUNING_PARA_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define PS_TUNING_PARA_SET_CLASS(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 7)\n#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 7, value)\n#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(h2c_pkt)                              \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1)\n#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(h2c_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value)\n#define PS_TUNING_PARA_GET_PS_TIME_OUT(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 4)\n#define PS_TUNING_PARA_SET_PS_TIME_OUT(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 4, value)\n#define PS_TUNING_PARA_GET_ADOPT(h2c_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)\n#define PS_TUNING_PARA_SET_ADOPT(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)\n#define PS_TUNING_PARA_II_GET_CMD_ID(h2c_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define PS_TUNING_PARA_II_SET_CMD_ID(h2c_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define PS_TUNING_PARA_II_GET_CLASS(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define PS_TUNING_PARA_II_SET_CLASS(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 7)\n#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 7, value)\n#define PS_TUNING_PARA_II_GET_ADOPT(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1)\n#define PS_TUNING_PARA_II_SET_ADOPT(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value)\n#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define PS_LPS_PARA_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define PS_LPS_PARA_SET_CMD_ID(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define PS_LPS_PARA_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define PS_LPS_PARA_SET_CLASS(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define PS_LPS_PARA_GET_LPS_CONTROL(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define PS_LPS_PARA_SET_LPS_CONTROL(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define P2P_PS_OFFLOAD_GET_CMD_ID(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define P2P_PS_OFFLOAD_SET_CMD_ID(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define P2P_PS_OFFLOAD_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define P2P_PS_OFFLOAD_SET_CLASS(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(h2c_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)\n#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(h2c_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)\n#define P2P_PS_OFFLOAD_GET_ROLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)\n#define P2P_PS_OFFLOAD_SET_ROLE(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)\n#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)\n#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)\n#define P2P_PS_OFFLOAD_GET_NOA0_EN(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)\n#define P2P_PS_OFFLOAD_SET_NOA0_EN(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)\n#define P2P_PS_OFFLOAD_GET_NOA1_EN(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1)\n#define P2P_PS_OFFLOAD_SET_NOA1_EN(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value)\n#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(h2c_pkt)                              \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 13, 1)\n#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(h2c_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 13, 1, value)\n#define P2P_PS_OFFLOAD_GET_DISCOVERY(h2c_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 14, 1)\n#define P2P_PS_OFFLOAD_SET_DISCOVERY(h2c_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 14, 1, value)\n#define PS_SCAN_EN_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define PS_SCAN_EN_SET_CMD_ID(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define PS_SCAN_EN_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define PS_SCAN_EN_SET_CLASS(h2c_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define PS_SCAN_EN_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)\n#define PS_SCAN_EN_SET_ENABLE(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)\n#define SAP_PS_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define SAP_PS_SET_CMD_ID(h2c_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define SAP_PS_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define SAP_PS_SET_CLASS(h2c_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define SAP_PS_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)\n#define SAP_PS_SET_ENABLE(h2c_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)\n#define SAP_PS_GET_EN_PS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)\n#define SAP_PS_SET_EN_PS(h2c_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)\n#define SAP_PS_GET_EN_LP_RX(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)\n#define SAP_PS_SET_EN_LP_RX(h2c_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)\n#define SAP_PS_GET_MANUAL_32K(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)\n#define SAP_PS_SET_MANUAL_32K(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)\n#define SAP_PS_GET_DURATION(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define SAP_PS_SET_DURATION(h2c_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define INACTIVE_PS_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define INACTIVE_PS_SET_CMD_ID(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define INACTIVE_PS_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define INACTIVE_PS_SET_CLASS(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define INACTIVE_PS_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)\n#define INACTIVE_PS_SET_ENABLE(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)\n#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)\n#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)\n#define INACTIVE_PS_GET_FREQUENCY(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define INACTIVE_PS_SET_FREQUENCY(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define INACTIVE_PS_GET_DURATION(h2c_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)\n#define INACTIVE_PS_SET_DURATION(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)\n#define MACID_CFG_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define MACID_CFG_SET_CMD_ID(h2c_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define MACID_CFG_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define MACID_CFG_SET_CLASS(h2c_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define MACID_CFG_GET_MAC_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define MACID_CFG_SET_MAC_ID(h2c_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define MACID_CFG_GET_RATE_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 5)\n#define MACID_CFG_SET_RATE_ID(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 5, value)\n#define MACID_CFG_GET_INIT_RATE_LV(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 21, 2)\n#define MACID_CFG_SET_INIT_RATE_LV(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 21, 2, value)\n#define MACID_CFG_GET_SGI(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 23, 1)\n#define MACID_CFG_SET_SGI(h2c_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 23, 1, value)\n#define MACID_CFG_GET_BW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 2)\n#define MACID_CFG_SET_BW(h2c_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 2, value)\n#define MACID_CFG_GET_LDPC_CAP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 26, 1)\n#define MACID_CFG_SET_LDPC_CAP(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 26, 1, value)\n#define MACID_CFG_GET_NO_UPDATE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 27, 1)\n#define MACID_CFG_SET_NO_UPDATE(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 27, 1, value)\n#define MACID_CFG_GET_WHT_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 28, 2)\n#define MACID_CFG_SET_WHT_EN(h2c_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 28, 2, value)\n#define MACID_CFG_GET_DISPT(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 30, 1)\n#define MACID_CFG_SET_DISPT(h2c_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 30, 1, value)\n#define MACID_CFG_GET_DISRA(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 31, 1)\n#define MACID_CFG_SET_DISRA(h2c_pkt, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 31, 1, value)\n#define MACID_CFG_GET_RATE_MASK7_0(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)\n#define MACID_CFG_SET_RATE_MASK7_0(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)\n#define MACID_CFG_GET_RATE_MASK15_8(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)\n#define MACID_CFG_SET_RATE_MASK15_8(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)\n#define MACID_CFG_GET_RATE_MASK23_16(h2c_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)\n#define MACID_CFG_SET_RATE_MASK23_16(h2c_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)\n#define MACID_CFG_GET_RATE_MASK31_24(h2c_pkt)                                  \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)\n#define MACID_CFG_SET_RATE_MASK31_24(h2c_pkt, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)\n#define TXBF_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define TXBF_SET_CMD_ID(h2c_pkt, value)                                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define TXBF_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define TXBF_SET_CLASS(h2c_pkt, value)                                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define TXBF_GET_NDPA0_HEAD_PAGE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define TXBF_SET_NDPA0_HEAD_PAGE(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define TXBF_GET_NDPA1_HEAD_PAGE(h2c_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define TXBF_SET_NDPA1_HEAD_PAGE(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define TXBF_GET_PERIOD_0(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)\n#define TXBF_SET_PERIOD_0(h2c_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)\n#define RSSI_SETTING_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define RSSI_SETTING_SET_CMD_ID(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define RSSI_SETTING_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define RSSI_SETTING_SET_CLASS(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define RSSI_SETTING_GET_MAC_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define RSSI_SETTING_SET_MAC_ID(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define RSSI_SETTING_GET_RSSI(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 7)\n#define RSSI_SETTING_SET_RSSI(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 7, value)\n#define RSSI_SETTING_GET_RA_INFO(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)\n#define RSSI_SETTING_SET_RA_INFO(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)\n#define AP_REQ_TXRPT_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define AP_REQ_TXRPT_SET_CMD_ID(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define AP_REQ_TXRPT_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define AP_REQ_TXRPT_SET_CLASS(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define AP_REQ_TXRPT_GET_STA1_MACID(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define AP_REQ_TXRPT_SET_STA1_MACID(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define AP_REQ_TXRPT_GET_STA2_MACID(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define AP_REQ_TXRPT_SET_STA2_MACID(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(h2c_pkt)                                 \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 1)\n#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(h2c_pkt, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 1, value)\n#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 25, 1)\n#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 25, 1, value)\n#define INIT_RATE_COLLECTION_GET_CMD_ID(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define INIT_RATE_COLLECTION_SET_CMD_ID(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define INIT_RATE_COLLECTION_GET_CLASS(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define INIT_RATE_COLLECTION_SET_CLASS(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define INIT_RATE_COLLECTION_GET_STA1_MACID(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define INIT_RATE_COLLECTION_SET_STA1_MACID(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define INIT_RATE_COLLECTION_GET_STA2_MACID(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define INIT_RATE_COLLECTION_SET_STA2_MACID(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define INIT_RATE_COLLECTION_GET_STA3_MACID(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)\n#define INIT_RATE_COLLECTION_SET_STA3_MACID(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)\n#define INIT_RATE_COLLECTION_GET_STA4_MACID(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)\n#define INIT_RATE_COLLECTION_SET_STA4_MACID(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)\n#define INIT_RATE_COLLECTION_GET_STA5_MACID(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)\n#define INIT_RATE_COLLECTION_SET_STA5_MACID(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)\n#define INIT_RATE_COLLECTION_GET_STA6_MACID(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)\n#define INIT_RATE_COLLECTION_SET_STA6_MACID(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)\n#define INIT_RATE_COLLECTION_GET_STA7_MACID(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)\n#define INIT_RATE_COLLECTION_SET_STA7_MACID(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)\n#define IQK_OFFLOAD_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define IQK_OFFLOAD_SET_CMD_ID(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define IQK_OFFLOAD_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define IQK_OFFLOAD_SET_CLASS(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define IQK_OFFLOAD_GET_CHANNEL(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define IQK_OFFLOAD_SET_CHANNEL(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define IQK_OFFLOAD_GET_BWBAND(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define IQK_OFFLOAD_SET_BWBAND(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define IQK_OFFLOAD_GET_EXTPALNA(h2c_pkt)                                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)\n#define IQK_OFFLOAD_SET_EXTPALNA(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)\n#define MACID_CFG_3SS_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define MACID_CFG_3SS_SET_CMD_ID(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define MACID_CFG_3SS_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define MACID_CFG_3SS_SET_CLASS(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define MACID_CFG_3SS_GET_MACID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define MACID_CFG_3SS_SET_MACID(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define MACID_CFG_3SS_GET_RATE_MASK_39_32(h2c_pkt)                             \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)\n#define MACID_CFG_3SS_SET_RATE_MASK_39_32(h2c_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)\n#define MACID_CFG_3SS_GET_RATE_MASK_47_40(h2c_pkt)                             \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)\n#define MACID_CFG_3SS_SET_RATE_MASK_47_40(h2c_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)\n#define RA_PARA_ADJUST_GET_CMD_ID(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define RA_PARA_ADJUST_SET_CMD_ID(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define RA_PARA_ADJUST_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define RA_PARA_ADJUST_SET_CLASS(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define RA_PARA_ADJUST_GET_MAC_ID(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define RA_PARA_ADJUST_SET_MAC_ID(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(h2c_pkt)                            \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(h2c_pkt, value)                     \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define RA_PARA_ADJUST_GET_RATE_ID(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)\n#define RA_PARA_ADJUST_SET_RATE_ID(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)\n#define RA_PARA_ADJUST_GET_VALUE_BYTE0(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)\n#define RA_PARA_ADJUST_SET_VALUE_BYTE0(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)\n#define RA_PARA_ADJUST_GET_VALUE_BYTE1(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)\n#define RA_PARA_ADJUST_SET_VALUE_BYTE1(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)\n#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(h2c_pkt)                         \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)\n#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(h2c_pkt, value)                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)\n#define WWLAN_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define WWLAN_SET_CMD_ID(h2c_pkt, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define WWLAN_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define WWLAN_SET_CLASS(h2c_pkt, value)                                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define WWLAN_GET_FUNC_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)\n#define WWLAN_SET_FUNC_EN(h2c_pkt, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)\n#define WWLAN_GET_PATTERM_MAT_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)\n#define WWLAN_SET_PATTERM_MAT_EN(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)\n#define WWLAN_GET_MAGIC_PKT_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)\n#define WWLAN_SET_MAGIC_PKT_EN(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)\n#define WWLAN_GET_UNICAST_WAKEUP_EN(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)\n#define WWLAN_SET_UNICAST_WAKEUP_EN(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)\n#define WWLAN_GET_ALL_PKT_DROP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1)\n#define WWLAN_SET_ALL_PKT_DROP(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value)\n#define WWLAN_GET_GPIO_ACTIVE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 13, 1)\n#define WWLAN_SET_GPIO_ACTIVE(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 13, 1, value)\n#define WWLAN_GET_REKEY_WAKEUP_EN(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 14, 1)\n#define WWLAN_SET_REKEY_WAKEUP_EN(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 14, 1, value)\n#define WWLAN_GET_DEAUTH_WAKEUP_EN(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1)\n#define WWLAN_SET_DEAUTH_WAKEUP_EN(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value)\n#define WWLAN_GET_GPIO_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 7)\n#define WWLAN_SET_GPIO_NUM(h2c_pkt, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 7, value)\n#define WWLAN_GET_DATAPIN_WAKEUP_EN(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 23, 1)\n#define WWLAN_SET_DATAPIN_WAKEUP_EN(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 23, 1, value)\n#define WWLAN_GET_GPIO_DURATION(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)\n#define WWLAN_SET_GPIO_DURATION(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)\n#define WWLAN_GET_GPIO_PLUS_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 1)\n#define WWLAN_SET_GPIO_PLUS_EN(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 1, value)\n#define WWLAN_GET_GPIO_PULSE_COUNT(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 1, 7)\n#define WWLAN_SET_GPIO_PULSE_COUNT(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 1, 7, value)\n#define WWLAN_GET_DISABLE_UPHY(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 1)\n#define WWLAN_SET_DISABLE_UPHY(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 1, value)\n#define WWLAN_GET_HST2DEV_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 9, 1)\n#define WWLAN_SET_HST2DEV_EN(h2c_pkt, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 9, 1, value)\n#define WWLAN_GET_GPIO_DURATION_MS(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 10, 1)\n#define WWLAN_SET_GPIO_DURATION_MS(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 10, 1, value)\n#define REMOTE_WAKE_CTRL_GET_CMD_ID(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define REMOTE_WAKE_CTRL_SET_CMD_ID(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define REMOTE_WAKE_CTRL_GET_CLASS(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define REMOTE_WAKE_CTRL_SET_CLASS(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(h2c_pkt)                      \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)\n#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(h2c_pkt, value)               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)\n#define REMOTE_WAKE_CTRL_GET_ARP_EN(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)\n#define REMOTE_WAKE_CTRL_SET_ARP_EN(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)\n#define REMOTE_WAKE_CTRL_GET_NDP_EN(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)\n#define REMOTE_WAKE_CTRL_SET_NDP_EN(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)\n#define REMOTE_WAKE_CTRL_GET_GTK_EN(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)\n#define REMOTE_WAKE_CTRL_SET_GTK_EN(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)\n#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1)\n#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value)\n#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 13, 1)\n#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 13, 1, value)\n#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 14, 1)\n#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 14, 1, value)\n#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1)\n#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value)\n#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 1)\n#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 1, value)\n#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(h2c_pkt)                            \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 17, 1)\n#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(h2c_pkt, value)                     \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 17, 1, value)\n#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(h2c_pkt)                         \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 18, 1)\n#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(h2c_pkt, value)                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 18, 1, value)\n#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 1)\n#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 1, value)\n#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt)                  \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 28, 1)\n#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt, value)           \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 28, 1, value)\n#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(h2c_pkt)                  \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 29, 1)\n#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(h2c_pkt, value)           \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 29, 1, value)\n#define AOAC_GLOBAL_INFO_GET_CMD_ID(h2c_pkt)                                   \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define AOAC_GLOBAL_INFO_SET_CMD_ID(h2c_pkt, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define AOAC_GLOBAL_INFO_GET_CLASS(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define AOAC_GLOBAL_INFO_SET_CLASS(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(h2c_pkt)                            \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(h2c_pkt, value)                     \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define AOAC_RSVD_PAGE_GET_CMD_ID(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define AOAC_RSVD_PAGE_SET_CMD_ID(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define AOAC_RSVD_PAGE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define AOAC_RSVD_PAGE_SET_CLASS(h2c_pkt, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(h2c_pkt)                       \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(h2c_pkt, value)                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt)                 \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)\n#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt, value)          \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)\n#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)\n#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)\n#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)\n#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)\n#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(h2c_pkt)                            \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)\n#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(h2c_pkt, value)                     \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)\n#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)\n#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)\n#define AOAC_RSVD_PAGE2_GET_CMD_ID(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define AOAC_RSVD_PAGE2_SET_CMD_ID(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define AOAC_RSVD_PAGE2_GET_CLASS(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define AOAC_RSVD_PAGE2_SET_CLASS(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(h2c_pkt)                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(h2c_pkt, value)              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(h2c_pkt)                         \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(h2c_pkt, value)                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)\n#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)\n#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(h2c_pkt)                          \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)\n#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(h2c_pkt, value)                   \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)\n#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)\n#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)\n#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)\n#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)\n#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)\n#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)\n#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(h2c_pkt)                               \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(h2c_pkt, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(h2c_pkt)                                \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(h2c_pkt, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(h2c_pkt)                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(h2c_pkt, value)              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(h2c_pkt)                             \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(h2c_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(h2c_pkt)                              \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(h2c_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(h2c_pkt)                        \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(h2c_pkt, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(h2c_pkt)                             \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(h2c_pkt, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)\n#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)\n#define AOAC_RSVD_PAGE3_GET_CMD_ID(h2c_pkt)                                    \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define AOAC_RSVD_PAGE3_SET_CMD_ID(h2c_pkt, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define AOAC_RSVD_PAGE3_GET_CLASS(h2c_pkt)                                     \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define AOAC_RSVD_PAGE3_SET_CLASS(h2c_pkt, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(h2c_pkt)                              \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)\n#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(h2c_pkt, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)\n#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(h2c_pkt)                           \\\n\tLE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)\n#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)\n#define DBG_MSG_CTRL_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)\n#define DBG_MSG_CTRL_SET_CMD_ID(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)\n#define DBG_MSG_CTRL_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)\n#define DBG_MSG_CTRL_SET_CLASS(h2c_pkt, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)\n#define DBG_MSG_CTRL_GET_FUN_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)\n#define DBG_MSG_CTRL_SET_FUN_EN(h2c_pkt, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)\n#define DBG_MSG_CTRL_GET_MODE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 4)\n#define DBG_MSG_CTRL_SET_MODE(h2c_pkt, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 4, value)\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_pcie_reg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef __HALMAC_PCIE_REG_H__\n#define __HALMAC_PCIE_REG_H__\n\n/* PCIE PHY register */\n#define RAC_CTRL_PPR\t\t\t0x00\n#define RAC_SET_PPR\t\t\t0x20\n#define RAC_TRG_PPR\t\t\t0x21\n#define RAC_CTRL_PPR_V1\t\t\t0x30\n#define RAC_SET_PPR_V1\t\t\t0x31\n\n/* PCIE CFG register */\n#define PCIE_L1SS_CTRL\t\t\t0x718\n#define PCIE_L1_CTRL\t\t\t0x719\n#define PCIE_ASPM_CTRL\t\t\t0x70F\n#define PCIE_CLK_CTRL\t\t\t0x725\n#define PCIE_L1SS_CAP\t\t\t0x160\n#define PCIE_L1SS_SUP\t\t\t0x164\n#define PCIE_L1SS_STS\t\t\t0x168\n\n/* PCIE CFG bit */\n#define PCIE_BIT_WAKE\t\t\tBIT(2)\n#define PCIE_BIT_L1\t\t\tBIT(3)\n#define PCIE_BIT_CLK\t\t\tBIT(4)\n#define PCIE_BIT_L0S\t\t\tBIT(7)\n#define PCIE_BIT_L1SS\t\t\tBIT(5)\n#define PCIE_BIT_L1SSSUP\t\tBIT(4)\n\n/* PCIE ASPM mask*/\n#define SHFT_L1DLY\t\t\t3\n#define SHFT_L0SDLY\t\t\t0\n#define PCIE_ASPMDLY_MASK\t\t0x07\n#define PCIE_L1SS_MASK\t\t\t0x0F\n\n/* PCIE Capability */\n#define PCIE_L1SS_ID\t\t\t0x001E\n\n/* PCIE MAC register */\n#define LINK_CTRL2_REG_OFFSET\t\t0xA0\n#define GEN2_CTRL_OFFSET\t\t0x80C\n#define LINK_STATUS_REG_OFFSET\t\t0x82\n\n#define PCIE_GEN1_SPEED\t\t\t0x01\n#define PCIE_GEN2_SPEED\t\t\t0x02\n\n#endif/* __HALMAC_PCIE_REG_H__ */\n"
  },
  {
    "path": "hal/halmac/halmac_pwr_seq_cmd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef HALMAC_POWER_SEQUENCE_CMD\n#define HALMAC_POWER_SEQUENCE_CMD\n\n#include \"halmac_2_platform.h\"\n\n#define HALMAC_PWR_POLLING_CNT 20000\n\n/* The value of cmd : 4 bits */\n\n/* offset : the read register offset\n * msk : the mask of the read value\n * value : N/A, left by 0\n * Note : dirver shall implement this function by read & msk\n */\n#define\tHALMAC_PWR_CMD_READ\t\t0x00\n/* offset: the read register offset\n * msk: the mask of the write bits\n * value: write value\n * Note: driver shall implement this cmd by read & msk after write\n */\n#define\tHALMAC_PWR_CMD_WRITE\t0x01\n/* offset: the read register offset\n * msk: the mask of the polled value\n * value: the value to be polled, masked by the msd field.\n * Note: driver shall implement this cmd by\n * do{\n * if( (Read(offset) & msk) == (value & msk) )\n * break;\n * } while(not timeout);\n */\n#define\tHALMAC_PWR_CMD_POLLING\t0x02\n/* offset: the value to delay\n * msk: N/A\n * value: the unit of delay, 0: us, 1: ms\n */\n#define\tHALMAC_PWR_CMD_DELAY\t0x03\n/* offset: N/A\n * msk: N/A\n * value: N/A\n */\n#define\tHALMAC_PWR_CMD_END\t0x04\n\n/* The value of base : 4 bits */\n\n/* define the base address of each block */\n#define   HALMAC_PWR_ADDR_MAC\t0x00\n#define   HALMAC_PWR_ADDR_USB\t0x01\n#define   HALMAC_PWR_ADDR_PCIE\t0x02\n#define   HALMAC_PWR_ADDR_SDIO\t0x03\n\n/* The value of interface_msk : 4 bits */\n#define\tHALMAC_PWR_INTF_SDIO_MSK\tBIT(0)\n#define\tHALMAC_PWR_INTF_USB_MSK\t\tBIT(1)\n#define\tHALMAC_PWR_INTF_PCI_MSK\t\tBIT(2)\n#define\tHALMAC_PWR_INTF_ALL_MSK\t\t(BIT(0) | BIT(1) | BIT(2) | BIT(3))\n\n/* The value of cut_msk : 8 bits */\n#define\tHALMAC_PWR_CUT_TESTCHIP_MSK\t\tBIT(0)\n#define\tHALMAC_PWR_CUT_A_MSK\t\t\tBIT(1)\n#define\tHALMAC_PWR_CUT_B_MSK\t\t\tBIT(2)\n#define\tHALMAC_PWR_CUT_C_MSK\t\t\tBIT(3)\n#define\tHALMAC_PWR_CUT_D_MSK\t\t\tBIT(4)\n#define\tHALMAC_PWR_CUT_E_MSK\t\t\tBIT(5)\n#define\tHALMAC_PWR_CUT_F_MSK\t\t\tBIT(6)\n#define\tHALMAC_PWR_CUT_G_MSK\t\t\tBIT(7)\n#define\tHALMAC_PWR_CUT_ALL_MSK\t\t\t0xFF\n\nenum halmac_pwrseq_cmd_delay_unit {\n\tHALMAC_PWR_DELAY_US,\n\tHALMAC_PWR_DELAY_MS,\n};\n\nstruct halmac_wlan_pwr_cfg {\n\tu16 offset;\n\tu8 cut_msk;\n\tu8 interface_msk;\n\tu8 base:4;\n\tu8 cmd:4;\n\tu8 msk;\n\tu8 value;\n};\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_reg2.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef __HALMAC_COM_REG_H__\n#define __HALMAC_COM_REG_H__\n\n#include \"halmac_hw_cfg.h\"\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_SYS_ISO_CTRL 0x0000\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_TX_CTRL 0x10250000\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_SYS_FUNC_EN 0x0002\n#define REG_SYS_PW_CTRL 0x0004\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_CMD11_VOL_SWITCH 0x10250004\n#define REG_SDIO_CTRL 0x10250005\n#define REG_SDIO_DRIVING 0x10250006\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_SYS_CLK_CTRL 0x0008\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_MONITOR 0x10250008\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_SYS_EEPROM_CTRL 0x000A\n#define REG_EE_VPD 0x000C\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_MONITOR_2 0x1025000C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_SYS_SWR_CTRL1 0x0010\n#define REG_SYS_SWR_CTRL2 0x0014\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_HIMR 0x10250014\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_SYS_SWR_CTRL3 0x0018\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_HISR 0x10250018\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_RSV_CTRL 0x001C\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_RX_REQ_LEN 0x1025001C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_RF_CTRL 0x001F\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_RF0_CTRL 0x001F\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_FREE_TXPG_SEQ_V1 0x1025001F\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_AFE_LDO_CTRL 0x0020\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_FREE_TXPG 0x10250020\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_AFE_CTRL1 0x0024\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_FREE_TXPG2 0x10250024\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_AFE_CTRL2 0x0028\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_OQT_FREE_TXPG_V1 0x10250028\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_ANAPARSW_POW_MAC 0x0028\n#define REG_ANAPARLDO_POW_MAC 0x0029\n#define REG_ANAPAR_POW_MAC 0x002A\n#define REG_ANAPAR_POW_XTAL 0x002B\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_AFE_CTRL3 0x002C\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_ANAPARLDO_MAC 0x002C\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_TXPKT_EMPTY 0x1025002C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_EFUSE_CTRL 0x0030\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_HTSFR_INFO 0x10250030\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_LDO_EFUSE_CTRL 0x0034\n#define REG_PWR_OPTION_CTRL 0x0038\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_HCPWM1_V2 0x10250038\n#define REG_SDIO_HCPWM2_V2 0x1025003A\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_CAL_TIMER 0x003C\n#define REG_ACLK_MON 0x003E\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_GPIO_MUXCFG_2 0x003F\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_GPIO_MUXCFG 0x0040\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_INDIRECT_REG_CFG 0x10250040\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_GPIO_PIN_CTRL 0x0044\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_INDIRECT_REG_DATA 0x10250044\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_GPIO_INTM 0x0048\n#define REG_LED_CFG 0x004C\n#define REG_FSIMR 0x0050\n#define REG_FSISR 0x0054\n#define REG_HSIMR 0x0058\n#define REG_HSISR 0x005C\n#define REG_GPIO_EXT_CTRL 0x0060\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_H2C 0x10250060\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_PAD_CTRL1 0x0064\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_C2H 0x10250064\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_WL_BT_PWR_CTRL 0x0068\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_SDM_DEBUG 0x006C\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n#define REG_GSSR 0x006C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_SYS_SDIO_CTRL 0x0070\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n#define REG_SYS_CLKR 0x0070\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_HCI_OPT_CTRL 0x0074\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_AFE_CTRL4 0x0078\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_HCI_BG_CTRL 0x0078\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n#define REG_AFE_XTAL_CTRL_EXT 0x0078\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_HCI_LDO_CTRL 0x007A\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_LDO_SWR_CTRL 0x007C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_8051FW_CTRL 0x0080\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MCUFW_CTRL 0x0080\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_HRPWM1 0x10250080\n#define REG_SDIO_HRPWM2 0x10250082\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_MCU_TST_CFG 0x0084\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_HPS_CLKR 0x10250084\n#define REG_SDIO_BUS_CTRL 0x10250085\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_HSUS_CTRL 0x10250086\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_HMEBOX_E0_E1 0x0088\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_RESPONSE_TIMER 0x10250088\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_CMD_CRC 0x1025008A\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_HMEBOX_E2_E3 0x008C\n#define REG_WLLPS_CTRL 0x0090\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_HSISR 0x10250090\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_HSIMR 0x10250091\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT)\n\n#define REG_AFE_CTRL5 0x0094\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_GPIO_DEBOUNCE_CTRL 0x0098\n#define REG_RPWM2 0x009C\n#define REG_SYSON_FSM_MON 0x00A0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT)\n\n#define REG_AFE_CTRL6 0x00A4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_PMC_DBG_CTRL1 0x00A8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT)\n\n#define REG_AFE_CTRL7 0x00AC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_HIMR0 0x00B0\n#define REG_HISR0 0x00B4\n#define REG_HIMR1 0x00B8\n#define REG_HISR1 0x00BC\n#define REG_DBG_PORT_SEL 0x00C0\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_DIOERR_RPT 0x102500C0\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n#define REG_SDIO_ERR_RPT 0x102500C0\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_CMD_ERRCNT 0x102500C2\n#define REG_SDIO_DATA_ERRCNT 0x102500C3\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_PAD_CTRL2 0x00C4\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_CMD_ERR_CONTENT 0x102500C4\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n#define REG_MEM_RMC 0x00C8\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_CRC_ERR_IDX 0x102500C9\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_DATA_CRC 0x102500CA\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n#define REG_SDIO_DATA_REPLY_TIME 0x102500CB\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_PMC_DBG_CTRL2 0x00CC\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SDIO_TRANS_FIFO_STATUS 0x102500CC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BIST_CTRL 0x00D0\n#define REG_BIST_RPT 0x00D4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_MEM_CTRL 0x00D8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n#define REG_AFE_CTRL8 0x00DC\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n#define REG_WLAN_DBG 0x00DC\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_SYN_RFC_CTRL 0x00DC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_USB_SIE_INTF 0x00E0\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_SYS_PINMUX 0x00E0\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_PCIE_MIO_INTF 0x00E4\n#define REG_PCIE_MIO_INTD 0x00E8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_WLRF1 0x00EC\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n#define REG_HPON_FSM 0x00EC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_SYS_CFG1 0x00F0\n#define REG_SYS_STATUS1 0x00F4\n#define REG_SYS_STATUS2 0x00F8\n#define REG_SYS_CFG2 0x00FC\n#define REG_CR 0x0100\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_PG_SIZE 0x0104\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_PKT_BUFF_ACCESS_CTRL 0x0106\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_TSF_CLK_STATE 0x0108\n#define REG_TXDMA_PQ_MAP 0x010C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_TRXFF_BNDY 0x0114\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_RXFF_BNDY_V1 0x0114\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_PTA_I2C_MBOX 0x0118\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT)\n\n#define REG_FF_STATUS 0x0118\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_RXFF_PTR 0x011C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_RXFF_BNDY 0x011C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_FEIMR 0x0120\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_FE1IMR 0x0120\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_FEISR 0x0124\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_FE1ISR 0x0124\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_CPWM 0x012C\n#define REG_FWIMR 0x0130\n#define REG_FWISR 0x0134\n#define REG_FTIMR 0x0138\n#define REG_FTISR 0x013C\n#define REG_PKTBUF_DBG_CTRL 0x0140\n#define REG_PKTBUF_DBG_DATA_L 0x0144\n#define REG_PKTBUF_DBG_DATA_H 0x0148\n#define REG_CPWM2 0x014C\n#define REG_TC0_CTRL 0x0150\n#define REG_TC1_CTRL 0x0154\n#define REG_TC2_CTRL 0x0158\n#define REG_TC3_CTRL 0x015C\n#define REG_TC4_CTRL 0x0160\n#define REG_TCUNIT_BASE 0x0164\n#define REG_TC5_CTRL 0x0168\n#define REG_TC6_CTRL 0x016C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MBIST_FAIL 0x0170\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_MBIST_DRF_FAIL 0x0170\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MBIST_START_PAUSE 0x0174\n#define REG_MBIST_DONE 0x0178\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MBIST_ROM_CRC_DATA 0x017C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_MBIST_NRML_FAIL 0x017C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n#define REG_MBIST_FAIL_NRML 0x017C\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MBIST_READ_BIST_RPT 0x017C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_AES_DECRPT_DATA 0x0180\n#define REG_AES_DECRPT_CFG 0x0184\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_MBIST_READ_BIST_RPT_V1 0x0188\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_HIOE_CTRL 0x0188\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n#define REG_MACCLKFRQ 0x018C\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_HIOE_CFG_FILE 0x018C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_TMETER 0x0190\n#define REG_OSC_32K_CTRL 0x0194\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_32K_CAL_REG1 0x0198\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n#define REG_32K_CAL_REG0 0x0198\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_C2HEVT 0x01A0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_C2HEVT_1 0x01A4\n#define REG_C2HEVT_2 0x01A8\n#define REG_C2HEVT_3 0x01AC\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_MISC_CTRL_V1 0x01B0\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT)\n\n#define REG_TC7_CTRL 0x01B0\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_RXDESC_BUFF_RPTR 0x01B0\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT)\n\n#define REG_TC8_CTRL 0x01B4\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_RXDESC_BUFF_WPTR 0x01B4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_SW_DEFINED_PAGE1 0x01B8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SW_DEFINED_PAGE2 0x01BC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_MCUTST_I 0x01C0\n#define REG_MCUTST_II 0x01C4\n#define REG_FMETHR 0x01C8\n#define REG_HMETFR 0x01CC\n#define REG_HMEBOX0 0x01D0\n#define REG_HMEBOX1 0x01D4\n#define REG_HMEBOX2 0x01D8\n#define REG_HMEBOX3 0x01DC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_LLT_INIT 0x01E0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_LLT_IND_ACCESS 0x01E0\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_RXDESC_BUFF_BNDY 0x01E0\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_GENTST 0x01E4\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n#define REG_LLT_INIT_ADDR 0x01E4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_BB_ACCESS_CTRL 0x01E8\n#define REG_BB_ACCESS_DATA 0x01EC\n#define REG_HMEBOX_E0 0x01F0\n#define REG_HMEBOX_E1 0x01F4\n#define REG_HMEBOX_E2 0x01F8\n#define REG_HMEBOX_E3 0x01FC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_RQPN_CTRL_HLPQ 0x0200\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_FIFOPAGE_CTRL_1 0x0200\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_BCN_CTRL_0 0x0200\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_FIFOPAGE_INFO 0x0204\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_FIFOPAGE_CTRL_2 0x0204\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_BCN_CTRL_1 0x0204\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_DWBCN0_CTRL 0x0208\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_AUTO_LLT_V1 0x0208\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_TXDMA_OFFSET_CHK 0x020C\n#define REG_TXDMA_STATUS 0x0210\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_RQPN_NPQ 0x0214\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_TX_DMA_DBG 0x0214\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_TQPNT1 0x0218\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_DMA_RQPN_INFO_PUB 0x0218\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_TQPNT2 0x021C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_RQPN_CTRL_2_V1 0x021C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_TDE_DEBUG 0x0220\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TQPNT3 0x0220\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_BCN_CTRL_2 0x0220\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_AUTO_LLT 0x0224\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TQPNT4 0x0224\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_DWBCN1_CTRL 0x0228\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_RQPN_CTRL_1 0x0228\n#define REG_RQPN_CTRL_2 0x022C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_RQPN_EXQ1_EXQ2 0x0230\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_FIFOPAGE_INFO_1 0x0230\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_TXPKTNUM_0 0x0230\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_TQPNT3_V1 0x0234\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_FIFOPAGE_INFO_2 0x0234\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_TXPKTNUM_1 0x0234\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_FIFOPAGE_INFO_3 0x0238\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_TXPKTNUM_2 0x0238\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_FIFOPAGE_INFO_4 0x023C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_TXPKTNUM_3 0x023C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_FIFOPAGE_INFO_5 0x0240\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_TX_AGG_ALIGN 0x0240\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_H2C_HEAD 0x0244\n#define REG_H2C_TAIL 0x0248\n#define REG_H2C_READ_ADDR 0x024C\n#define REG_H2C_WR_ADDR 0x0250\n#define REG_H2C_INFO 0x0254\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define REG_FIFOPAGE_CTRL_5 0x0258\n#define REG_FIFOPAGE_CTRL_3 0x025C\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_TQPNT5 0x0260\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_DMA_OQT_0 0x0260\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_TQPNT6 0x0264\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_DMA_OQT_1 0x0264\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_FIFOPAGE_INFO_6 0x0268\n#define REG_FIFOPAGE_INFO_7 0x026C\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_PGSUB_CNT 0x026C\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define REG_FIFOPAGE_CTRL_4 0x0270\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_PGSUB_H 0x0270\n#define REG_PGSUB_N 0x0274\n#define REG_PGSUB_L 0x0278\n#define REG_PGSUB_E 0x027C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_RXDMA_AGG_PG_TH 0x0280\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_RXPKT_NUM 0x0284\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_RXDMA_CTRL 0x0284\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_RXDMA_STATUS 0x0288\n#define REG_RXDMA_DPR 0x028C\n#define REG_RXDMA_MODE 0x0290\n#define REG_C2H_PKT 0x0294\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_FWFF_C2H 0x0298\n#define REG_FWFF_CTRL 0x029C\n#define REG_FWFF_PKT_INFO 0x02A0\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_FC2H_INFO 0x02A4\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_FWFF_PKT_INFO2 0x02A4\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_RXPKTNUM 0x02B0\n#define REG_RXPKTNUM_TH 0x02B4\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_FW_UPD_RXDES_RDPTR 0x02B8\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_FW_MSG1 0x02E0\n#define REG_FW_MSG2 0x02E4\n#define REG_FW_MSG3 0x02E8\n#define REG_FW_MSG4 0x02EC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_PCIE_CTRL 0x0300\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_HCI_CTRL 0x0300\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n#define REG_LX_CTRL1 0x0300\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_INT_MIG 0x0304\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH_CTRL 0x0304\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BCNQ_TXBD_DESA 0x0308\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_HIQ_CTRL 0x0308\n#define REG_INT_MIG_V1 0x030C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MGQ_TXBD_DESA 0x0310\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0MGQ_TXBD_DESA_L 0x0310\n#define REG_P0MGQ_TXBD_DESA_H 0x0314\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_VOQ_TXBD_DESA 0x0318\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH0_TXBD_DESA_L 0x0318\n#define REG_ACH0_TXBD_DESA_H 0x031C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_VIQ_TXBD_DESA 0x0320\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH1_TXBD_DESA_L 0x0320\n#define REG_ACH1_TXBD_DESA_H 0x0324\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BEQ_TXBD_DESA 0x0328\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH2_TXBD_DESA_L 0x0328\n#define REG_ACH2_TXBD_DESA_H 0x032C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BKQ_TXBD_DESA 0x0330\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH3_TXBD_DESA_L 0x0330\n#define REG_ACH3_TXBD_DESA_H 0x0334\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_RXQ_RXBD_DESA 0x0338\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0RXQ_RXBD_DESA_L 0x0338\n#define REG_P0RXQ_RXBD_DESA_H 0x033C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI0Q_TXBD_DESA 0x0340\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0BCNQ_TXBD_DESA_L 0x0340\n#define REG_P0BCNQ_TXBD_DESA_H 0x0344\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI1Q_TXBD_DESA 0x0348\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_FWCMDQ_TXBD_DESA_L 0x0348\n#define REG_FWCMDQ_TXBD_DESA_H 0x034C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI2Q_TXBD_DESA 0x0350\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_PCIE_HRPWM1_HCPWM1_DCPU 0x0354\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI3Q_TXBD_DESA 0x0358\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0_MPRT_BCNQ_TXBD_DESA_L 0x0358\n#define REG_P0_MPRT_BCNQ_TXBD_DESA_H 0x035C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI4Q_TXBD_DESA 0x0360\n#define REG_HI5Q_TXBD_DESA 0x0368\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0_MPRT_BCNQ_TXRXBD_NUM 0x036C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI6Q_TXBD_DESA 0x0370\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_BD_RWPTR_CLR2 0x0370\n#define REG_BD_RWPTR_CLR3 0x0374\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI7Q_TXBD_DESA 0x0378\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0MGQ_RXQ_TXRXBD_NUM 0x0378\n#define REG_CHNL_DMA_CFG 0x037C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MGQ_TXBD_NUM 0x0380\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_FWCMDQ_TXBD_NUM 0x0380\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_RX_RXBD_NUM 0x0382\n#define REG_VOQ_TXBD_NUM 0x0384\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH0_ACH1_TXBD_NUM 0x0384\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_VIQ_TXBD_NUM 0x0386\n#define REG_BEQ_TXBD_NUM 0x0388\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH2_ACH3_TXBD_NUM 0x0388\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BKQ_TXBD_NUM 0x038A\n#define REG_HI0Q_TXBD_NUM 0x038C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0HI0Q_HI1Q_TXBD_NUM 0x038C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI1Q_TXBD_NUM 0x038E\n#define REG_HI2Q_TXBD_NUM 0x0390\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0HI2Q_HI3Q_TXBD_NUM 0x0390\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI3Q_TXBD_NUM 0x0392\n#define REG_HI4Q_TXBD_NUM 0x0394\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0HI4Q_HI5Q_TXBD_NUM 0x0394\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI5Q_TXBD_NUM 0x0396\n#define REG_HI6Q_TXBD_NUM 0x0398\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0HI6Q_HI7Q_TXBD_NUM 0x0398\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI7Q_TXBD_NUM 0x039A\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_TSFTIMER_HCI 0x039C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BD_RWPTR_CLR 0x039C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_BD_RWPTR_CLR1 0x039C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_VOQ_TXBD_IDX 0x03A0\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH0_TXBD_IDX 0x03A0\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_VIQ_TXBD_IDX 0x03A4\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH1_TXBD_IDX 0x03A4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BEQ_TXBD_IDX 0x03A8\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH2_TXBD_IDX 0x03A8\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BKQ_TXBD_IDX 0x03AC\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH3_TXBD_IDX 0x03AC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MGQ_TXBD_IDX 0x03B0\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0MGQ_TXBD_IDX 0x03B0\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_RXQ_RXBD_IDX 0x03B4\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0RXQ_RXBD_IDX 0x03B4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI0Q_TXBD_IDX 0x03B8\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0HI0Q_TXBD_IDX 0x03B8\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI1Q_TXBD_IDX 0x03BC\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0HI1Q_TXBD_IDX 0x03BC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI2Q_TXBD_IDX 0x03C0\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0HI2Q_TXBD_IDX 0x03C0\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI3Q_TXBD_IDX 0x03C4\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0HI3Q_TXBD_IDX 0x03C4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI4Q_TXBD_IDX 0x03C8\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0HI4Q_TXBD_IDX 0x03C8\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI5Q_TXBD_IDX 0x03CC\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0HI5Q_TXBD_IDX 0x03CC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI6Q_TXBD_IDX 0x03D0\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0HI6Q_TXBD_IDX 0x03D0\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HI7Q_TXBD_IDX 0x03D4\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0HI7Q_TXBD_IDX 0x03D4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_DBG_SEL_V1 0x03D8\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1 0x03D8\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_PCIE_HRPWM1_V1 0x03D9\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_HCI_HRPWM1_V1 0x03D9\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_PCIE_HCPWM1_V1 0x03DA\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_HCI_HCPWM1_V1 0x03DA\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_PCIE_CTRL2 0x03DB\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_HCI_CTRL2 0x03DB\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n#define REG_LX_CTRL2 0x03DB\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_PCIE_HRPWM2_V1 0x03DC\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_HCI_HRPWM2_V1 0x03DC\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_PCIE_HRPWM2_HCPWM2_V1 0x03DC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_PCIE_HCPWM2_V1 0x03DE\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_HCI_HCPWM2_V1 0x03DE\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_PCIE_H2C_MSG_V1 0x03E0\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_HCI_H2C_MSG_V1 0x03E0\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_PCIE_C2H_MSG_V1 0x03E4\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_HCI_C2H_MSG_V1 0x03E4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_DBI_WDATA_V1 0x03E8\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n#define REG_LX_DMA_ISR 0x03E8\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_DBI_RDATA_V1 0x03EC\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n#define REG_LX_DMA_IMR 0x03EC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_DBI_FLAG_V1 0x03F0\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_STUCK_FLAG_V1 0x03F0\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n#define REG_LX_DMA_DBG 0x03F0\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MDIO_V1 0x03F4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT)\n\n#define REG_MDIO2_V1 0x03F8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_PCIE_MIX_CFG 0x03F8\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_WDT_CFG 0x03F8\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n#define REG_BUS_MIX_CFG 0x03F8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_HCI_MIX_CFG 0x03FC\n\n#endif\n\n#if (HALMAC_8881A_SUPPORT)\n\n#define REG_BUS_MIX_CFG1 0x03FC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_Q0_INFO 0x0400\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n#define REG_QUEUELIST_INFO0 0x0400\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_QUEUE_INFO1 0x0400\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_Q1_INFO 0x0404\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n#define REG_QUEUELIST_INFO1 0x0404\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_QUEUE_INFO2 0x0404\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_Q2_INFO 0x0408\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_QUEUE_INFO3 0x0408\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_QUEUELIST_INFO2 0x0408\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_Q3_INFO 0x040C\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_QINFO_INDEX 0x040C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_QUEUELIST_INFO3 0x040C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MGQ_INFO 0x0410\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_QUEUE_EMPTY 0x0410\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_QUEUELIST_INFO_EMPTY 0x0410\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HIQ_INFO 0x0414\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_QUEUELIST_INFO2_V1 0x0414\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_ACQ_STOP_V1 0x0414\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_QUEUELIST_ACQ_EN 0x0414\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BCNQ_INFO 0x0418\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_TXPKT_EMPTY_V1 0x0418\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_BCNQ_BDNY_V2 0x0418\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_TXPKT_EMPTY 0x041A\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_CPU_MGQ_INFO 0x041C\n#define REG_FWHW_TXQ_CTRL 0x0420\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HWSEQ_CTRL 0x0423\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_DATAFB_SEL 0x0423\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BCNQ_BDNY 0x0424\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BCNQ_BDNY_V1 0x0424\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_TXBDNY 0x0424\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MGQ_BDNY 0x0425\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_LIFETIME_EN 0x0426\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_FW_FREE_TAIL 0x0427\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_SPEC_SIFS 0x0428\n#define REG_RETRY_LIMIT 0x042A\n#define REG_TXBF_CTRL 0x042C\n#define REG_DARFRC 0x0430\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_DARFRCH 0x0434\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_RARFRC 0x0438\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_RARFRCH 0x043C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_RRSR 0x0440\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define REG_RRSR_H 0x0443\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_ARFR0 0x0444\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_ARFRH0 0x0448\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_ARFR1_V1 0x044C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_ARFR1 0x044C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_REG_ARFR_WT0 0x044C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_ARFRH1 0x0450\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_ARFRH1_V1 0x0450\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_REG_ARFR_WT1 0x0450\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_CCK_CHECK 0x0454\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_AMPDU_BURST_CTRL 0x0455\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_BCNQ2_HEAD 0x0455\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_AMPDU_MAX_TIME_V1 0x0455\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_AMPDU_MAX_TIME 0x0456\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BCNQ1_BDNY_V1 0x0456\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_TAB_SEL 0x0456\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BCNQ1_BDNY 0x0457\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_BCN_INVALID_CTRL 0x0457\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_AMPDU_MAX_LENGTH 0x0458\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_AMPDU_MAX_LENGTH_HT 0x0458\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_ACQ_STOP 0x045C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_WMAC_LBK_BUF_HD 0x045D\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_NDPA_RATE 0x045D\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_TX_HANG_CTRL 0x045E\n#define REG_NDPA_OPT_CTRL 0x045F\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_FAST_EDCA_CTRL 0x0460\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_AMPDU_MAX_LENGTH_VHT 0x0460\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_RD_RESP_PKT_TH 0x0463\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_CMDQ_INFO 0x0464\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_NEW_EDCA_CTRL_V1 0x0464\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_Q4_INFO 0x0468\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACQ_STOP_V2 0x0468\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_Q5_INFO 0x046C\n#define REG_Q6_INFO 0x0470\n#define REG_Q7_INFO 0x0474\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_LBK_BUF_HD_V1 0x0478\n#define REG_MGQ_BDNY_V1 0x047A\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_TXRPT_CTRL 0x047C\n#define REG_INIRTS_RATE_SEL 0x0480\n#define REG_BASIC_CFEND_RATE 0x0481\n#define REG_STBC_CFEND_RATE 0x0482\n#define REG_DATA_SC 0x0483\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MACID_SLEEP3 0x0484\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_MOREDATA_V1 0x0484\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_MACID_SLEEP4 0x0485\n#define REG_MACID_SLEEP5 0x0487\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_DATA_SC1 0x0487\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MACID_SLEEP1 0x0488\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_ARFR2_V1 0x048C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_ARFR2 0x048C\n#define REG_ARFRH2 0x0490\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_ARFRH2_V1 0x0490\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_ARFR3_V1 0x0494\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_ARFR3 0x0494\n#define REG_ARFRH3 0x0498\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_ARFRH3_V1 0x0498\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_ARFR4 0x049C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_ARFRH4 0x04A0\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_ARFR5 0x04A4\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_ARFRH5 0x04A8\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_TXRPT_START_OFFSET 0x04AC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_TRYING_CNT_TH 0x04B0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_TRY_CNT_IDX 0x04B0\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n#define REG_RRSR_CTS 0x04B0\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_POWER_STAGE1 0x04B4\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_POWER_STAGE2 0x04B8\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC\n#define REG_PKT_LIFE_TIME 0x04C0\n#define REG_STBC_SETTING 0x04C4\n#define REG_STBC_SETTING2 0x04C5\n#define REG_QUEUE_CTRL 0x04C6\n#define REG_SINGLE_AMPDU_CTRL 0x04C7\n#define REG_PROT_MODE_CTRL 0x04C8\n#define REG_BAR_MODE_CTRL 0x04CC\n#define REG_RA_TRY_RATE_AGG_LMT 0x04CF\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MACID_SLEEP2 0x04D0\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_MACID_SLEEP_CTRL 0x04D0\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MACID_SLEEP 0x04D4\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_MACID_SLEEP_INFO 0x04D4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_HW_SEQ0 0x04D8\n#define REG_HW_SEQ1 0x04DA\n#define REG_HW_SEQ2 0x04DC\n#define REG_HW_SEQ3 0x04DE\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n#define REG_CSI_SEQ 0x04DE\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_NULL_PKT_STATUS 0x04E0\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_NULL_PKT_STATUS_V1 0x04E0\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_PTCL_ERR_STATUS 0x04E2\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n#define REG_PTCL_ERR_STATUS_V1 0x04E2\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_PTCL_PKT_NUM 0x04E3\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_NULL_PKT_STATUS_EXTEND 0x04E3\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n#define REG_TRXRPT_MISS_CNT 0x04E3\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_HQMGQ_DROP 0x04E4\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n#define REG_VIDEO_ENHANCEMENT_FUN 0x04E4\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_NULL_PKT_STATUS_V2 0x04E4\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_PRECNT_CTRL 0x04E5\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_NULL_PKT_STATUS_EXTEND_V1 0x04E7\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_BT_POLLUTE_PKTCNT_V1 0x04E8\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_BT_POLLUTE_PKT_CNT 0x04E8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_DROP_PKT_NUM 0x04EC\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_PTCL_DBG 0x04EC\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_DROP_NUM 0x04EC\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_PTCL_DBG_V1 0x04EC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_PTCL_TX_RPT 0x04F0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_TX_RPT_INFO_L32 0x04F0\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_TXOP_EXTRA_CTRL 0x04F0\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_BT_POLLUTE_PKTCNT 0x04F0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_TX_RPT_INFO_H32 0x04F4\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_CPUMGQ_TIMER_CTRL2 0x04F4\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_PTCL_DBG_OUT 0x04F8\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_DUMMY_PAGE4 0x04FC\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_DUMMY_PAGE4_V1 0x04FC\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n#define REG_DUMMY_PAGE4_1 0x04FE\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_MOREDATA 0x04FE\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_EDCA_VO_PARAM 0x0500\n#define REG_EDCA_VI_PARAM 0x0504\n#define REG_EDCA_BE_PARAM 0x0508\n#define REG_EDCA_BK_PARAM 0x050C\n#define REG_BCNTCFG 0x0510\n#define REG_PIFS 0x0512\n#define REG_RDG_PIFS 0x0513\n#define REG_SIFS 0x0514\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_TSFTR_SYN_OFFSET 0x0518\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_FORCE_BCN_IFS_V1 0x0518\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_AGGR_BREAK_TIME 0x051A\n#define REG_SLOT 0x051B\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_NOA_ON_ERLY_TIME 0x051C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_EDCA_CPUMGQ_PARAM 0x051C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_NOA_OFF_ERLY_TIME 0x051D\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_CPUMGQ_PAUSE 0x051E\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_PS_TIMER_CTRL 0x051F\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_TX_PTCL_CTRL 0x0520\n#define REG_TXPAUSE 0x0522\n#define REG_DIS_TXREQ_CLR 0x0523\n#define REG_RD_CTRL 0x0524\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MBSSID_CTRL 0x0526\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_P2PPS_CTRL 0x0527\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_PKT_LIFETIME_CTRL 0x0528\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_P2PPS_SPEC_STATE 0x052B\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_P2PPS0_SPEC_STATE 0x052B\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_PS_TIMER_A_V2 0x052C\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define REG_TBTT_AREA_BLK_4AC 0x052C\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_TXOP_LIMIT_CTRL 0x052C\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_BAR_TX_CTRL 0x0530\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_P2PON_DIS_TXTIME 0x0531\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_PS_TIMER_B_V2 0x0534\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define REG_EDCA_REF_CTRL 0x0534\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_CCA_TXEN_CNT 0x0534\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT)\n\n#define REG_QUEUE_INCOL_THR 0x0538\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MAX_INTER_COLLISION 0x0538\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT)\n\n#define REG_QUEUE_INCOL_EN 0x053C\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MAX_INTER_COLLISION_CNT 0x053C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_TBTT_PROHIBIT 0x0540\n#define REG_P2PPS_STATE 0x0543\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_RD_NAV_NXT 0x0544\n#define REG_NAV_PROT_LEN 0x0546\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_FTM_SETTING 0x0548\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_FTM_CTRL 0x0548\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_FTM_PTT 0x0548\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT)\n\n#define REG_FTM_TSF_CNT 0x054C\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_FTM_TSF 0x054C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BCN_CTRL 0x0550\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BCN_CTRL1 0x0551\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BCN_CTRL_CLINT0 0x0551\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MBID_NUM 0x0552\n#define REG_DUAL_TSF_RST 0x0553\n#define REG_MBSSID_BCN_SPACE 0x0554\n#define REG_DRVERLYINT 0x0558\n#define REG_BCNDMATIM 0x0559\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_ATIMWND 0x055A\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_USTIME_TSF 0x055C\n#define REG_BCN_MAX_ERR 0x055D\n#define REG_RXTSF_OFFSET_CCK 0x055E\n#define REG_RXTSF_OFFSET_OFDM 0x055F\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_TSFTR 0x0560\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_TSFTR0_L 0x0560\n#define REG_TSFTR0_H 0x0564\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_TSFTR_1 0x0564\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_TSFTR1 0x0568\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_TSFTR1_L 0x0568\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_FREERUN_CNT 0x0568\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_TSFTR1_H 0x056C\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_FREERUN_CNT_1 0x056C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_ATIMWND1 0x0570\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_ATIMWND1_V1 0x0570\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TBTT_PROHIBIT_INFRA 0x0571\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_CTWND 0x0572\n#define REG_BCNIVLCUNT 0x0573\n#define REG_BCNDROPCTRL 0x0574\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_HGQ_TIMEOUT_PERIOD 0x0575\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TXCMD_TIMEOUT_PERIOD 0x0576\n#define REG_MISC_CTRL 0x0577\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_TSFTR2_L 0x0578\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BCN_CTRL_CLINT1 0x0578\n#define REG_BCN_CTRL_CLINT2 0x0579\n#define REG_BCN_CTRL_CLINT3 0x057A\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_EXTEND_CTRL 0x057B\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_TSFTR2_H 0x057C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_P2PPS1_SPEC_STATE 0x057C\n#define REG_P2PPS1_STATE 0x057D\n#define REG_P2PPS2_SPEC_STATE 0x057E\n#define REG_P2PPS2_STATE 0x057F\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_PS_TIMER 0x0580\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_PS_TIMER0 0x0580\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_TIMER0 0x0584\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_PS_TIMER1 0x0584\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_TIMER1 0x0588\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_PS_TIMER2 0x0588\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_TBTT_CTN_AREA 0x058C\n#define REG_FORCE_BCN_IFS 0x058E\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_DRVERLYINT_V1 0x058F\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_TXOP_MIN 0x0590\n#define REG_PRE_BKF_TIME 0x0592\n#define REG_CROSS_TXOP_CTRL 0x0593\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_FREERUN_CNT_L 0x0594\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_TBTT_INT_SHIFT_CLI0 0x0594\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define REG_TBTT_INT_SHIFT_CLI 0x0594\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_TBTT_INT_SHIFT_CLI1 0x0595\n#define REG_TBTT_INT_SHIFT_CLI2 0x0596\n#define REG_TBTT_INT_SHIFT_CLI3 0x0597\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_FREERUN_CNT_H 0x0598\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_TBTT_INT_SHIFT_ENABLE 0x0598\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_RX_TBTT_SHIFT_V1 0x0598\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_ATIMWND2 0x05A0\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_ATIMWND_GROUP1 0x05A0\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_ATIMWND3 0x05A1\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_ATIMWND_GROUP2 0x05A1\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_ATIMWND4 0x05A2\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_ATIMWND_GROUP3 0x05A2\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_ATIMWND5 0x05A3\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_ATIMWND_GROUP4 0x05A3\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_ATIMWND6 0x05A4\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_DTIM_COUNT_GROUP1 0x05A4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_ATIMWND7 0x05A5\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_DTIM_COUNT_GROUP2 0x05A5\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_ATIMUGT 0x05A6\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_DTIM_COUNT_GROUP3 0x05A6\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_HIQ_NO_LMT_EN 0x05A7\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_DTIM_COUNT_GROUP4 0x05A7\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_DTIM_COUNTER_ROOT 0x05A8\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_HIQ_NO_LMT_EN_V2 0x05A8\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_DTIM_COUNTER_VAP1 0x05A9\n#define REG_DTIM_COUNTER_VAP2 0x05AA\n#define REG_DTIM_COUNTER_VAP3 0x05AB\n#define REG_DTIM_COUNTER_VAP4 0x05AC\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_MBID_BCNQ_EN 0x05AC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_DTIM_COUNTER_VAP5 0x05AD\n#define REG_DTIM_COUNTER_VAP6 0x05AE\n#define REG_DTIM_COUNTER_VAP7 0x05AF\n#define REG_DIS_ATIM 0x05B0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_EARLY_128US 0x05B1\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_TBTT_HOLD_PREDICT_P1 0x05B2\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_P2PPS1_CTRL 0x05B2\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_MULTI_BCN_CS 0x05B3\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_P2PPS2_CTRL 0x05B3\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_TSFT_SHIFT 0x05B4\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TIMER0_SRC_SEL 0x05B4\n#define REG_NOA_UNIT_SEL 0x05B5\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_P2POFF_DIS_TXTIME 0x05B7\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MBSSID_BCN_SPACE2 0x05B8\n#define REG_MBSSID_BCN_SPACE3 0x05BC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_ACMHWCTRL 0x05C0\n#define REG_ACMRSTCTRL 0x05C1\n#define REG_ACMAVG 0x05C2\n#define REG_VO_ADMTIME 0x05C4\n#define REG_VI_ADMTIME 0x05C6\n#define REG_BE_ADMTIME 0x05C8\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MAC_HEADER_NAV_OFFSET 0x05CA\n#define REG_DIS_NDPA_NAV_CHECK 0x05CB\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_EDCA_RANDOM_GEN 0x05CC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_TXCMD_NOA_SEL 0x05CF\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_TXCMD_SEL 0x05CF\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_DRVERLYINT2 0x05D0\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define REG_BCNERR_CFG 0x05D0\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_32K_CLK_SEL 0x05D0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_NAN_SETTING 0x05D4\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define REG_BCN_ELY_ADJ 0x05D4\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_EARLYINT_ADJUST 0x05D4\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_NAN_BCNSPACE 0x05D8\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define REG_BCNERR_CNT1 0x05D8\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BCNERR_CNT 0x05D8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_NAN_SETTING1 0x05DC\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define REG_BCNERR_CNT2 0x05DC\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BCNERR_CNT_2 0x05DC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_NOA_PARAM 0x05E0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_NOA_PARAM_1 0x05E4\n#define REG_NOA_PARAM_2 0x05E8\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_MU_DBG_INFO 0x05E8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_NOA_PARAM_3 0x05EC\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_MU_DBG_INFO_1 0x05EC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_NOA_SUBIE 0x05ED\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_P2P_RST 0x05F0\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_SCH_DBG_SEL 0x05F0\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SCHEDULER_RST 0x05F1\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_MU_DBG_ERR_FLAG 0x05F2\n#define REG_TX_ERR_RECOVERY_RST 0x05F3\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_SCH_DBG 0x05F4\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SCH_DBG_VALUE 0x05F4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_SCH_TXCMD 0x05F8\n#define REG_PAGE5_DUMMY 0x05FC\n#define REG_WMAC_CR 0x0600\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_FWPKT_CR 0x0601\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_FW_STS_FILTER 0x0602\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n#define REG_WMAC_BWOPMODE 0x0603\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n#define REG_BWOPMODE 0x0603\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_TCR 0x0604\n#define REG_RCR 0x0608\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_RX_PKT_LIMIT 0x060C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_RXPKT_LIMIT 0x060C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_RX_DLK_TIME 0x060D\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_SDIO_RXINT_LEN_TH 0x1025060E\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_RX_DRVINFO_SZ 0x060F\n#define REG_MACID 0x0610\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MACID_H 0x0614\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_BSSID 0x0618\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BSSID_H 0x061C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_MAR 0x0620\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MAR_H 0x0624\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MBIDCAMCFG_1 0x0628\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MBIDCAMCFG_2 0x062C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_MBIDCAM_CFG 0x062C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_WMAC_DEBUG_SEL 0x062C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MCU_TEST_1 0x0630\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_TCR_TSFT_OFS 0x0630\n#define REG_UDF_THSD 0x0632\n#define REG_ZLD_NUM 0x0633\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_MCU_TEST_2 0x0634\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_STMP_THSD 0x0634\n#define REG_WMAC_TXTIMEOUT 0x0635\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n#define REG_MCU_TEST_2_V1 0x0636\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_USTIME_EDCA 0x0638\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_ACKTO_CCK 0x0639\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_MAC_SPEC_SIFS 0x063A\n#define REG_RESP_SIFS_CCK 0x063C\n#define REG_RESP_SIFS_OFDM 0x063E\n#define REG_ACKTO 0x0640\n#define REG_CTS2TO 0x0641\n#define REG_EIFS 0x0642\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_RPFM_MAP0 0x0644\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_RPFM_MAP1 0x0646\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_RPFM_MAP1_V1 0x0646\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_RPFM_CAM_CMD 0x0648\n#define REG_RPFM_CAM_RWD 0x064C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_NAV_CTRL 0x0650\n#define REG_BACAMCMD 0x0654\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BACAMCONTENT 0x0658\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n#define REG_BACAM_WD 0x0658\n#define REG_BACAM_WD_H 0x065C\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_BACAMCONTENT_H 0x065C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_LBDLY 0x0660\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n#define REG_LBK_DLY 0x0660\n#define REG_BITMAP_CMD 0x0661\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_BACAM_RPMEN 0x0661\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_TX_RX 0x0662\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_BITMAP_CTL 0x0663\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_RXERR_RPT 0x0664\n#define REG_WMAC_TRXPTCL_CTL 0x0668\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_TRXPTCL_CTL_H 0x066C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_CAMCMD 0x0670\n#define REG_CAMWRITE 0x0674\n#define REG_CAMREAD 0x0678\n#define REG_CAMDBG 0x067C\n#define REG_SECCFG 0x0680\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_RXFILTER_CATEGORY_1 0x0682\n#define REG_RXFILTER_ACTION_1 0x0683\n#define REG_RXFILTER_CATEGORY_2 0x0684\n#define REG_RXFILTER_ACTION_2 0x0685\n#define REG_RXFILTER_CATEGORY_3 0x0686\n#define REG_RXFILTER_ACTION_3 0x0687\n#define REG_RXFLTMAP3 0x0688\n#define REG_RXFLTMAP4 0x068A\n#define REG_RXFLTMAP5 0x068C\n#define REG_RXFLTMAP6 0x068E\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_WOW_CTRL 0x0690\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_NAN_RX_TSF_FILTER 0x0691\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_PS_RX_INFO 0x0692\n#define REG_WMMPS_UAPSD_TID 0x0693\n#define REG_LPNAV_CTRL 0x0694\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_WKFMCAM_NUM 0x0698\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WKFMCAM_CMD 0x0698\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WKFMCAM_RWD 0x069C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_RXFLTMAP0 0x06A0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_RXFLTER0 0x06A0\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_RXFLTMAP1 0x06A2\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_RXFLTER1 0x06A2\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_RXFLTMAP 0x06A4\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_RXFLTER2 0x06A4\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_RXFLTMAP2 0x06A4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_BCN_PSR_RPT 0x06A8\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_FLC_RPC 0x06AC\n#define REG_FLC_RPCT 0x06AD\n#define REG_FLC_PTS 0x06AE\n#define REG_FLC_TRPC 0x06AF\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_RXPKTMON_CTRL 0x06B0\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_STATE_MON 0x06B4\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n#define REG_ERROR_EVT_CTL 0x06B8\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_ERROR_MON 0x06B8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_RESPINFO 0x06BC\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SEARCH_MACID 0x06BC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BT_COEX_TABLE 0x06C0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n#define REG_BT_COEX_TABLE_V1 0x06C0\n#define REG_BT_COEX_TABLE2_V1 0x06C4\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_BT_COEX_TABLE2 0x06C4\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BT_COEX_BREAK_TABLE 0x06C8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n#define REG_BT_COEX_TABLE_H_V1 0x06CC\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_BT_COEX_TABLE_H 0x06CC\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_RXCMD_0 0x06D0\n#define REG_RXCMD_1 0x06D4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_WMAC_RESP_TXINFO 0x06D8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n#define REG_RESP_TXINFO_CFG 0x06D8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BBPSF_CTRL 0x06DC\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n#define REG_RESP_TXINFO_RATE 0x06DE\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_P2P_RX_BCN_NOA 0x06E0\n#define REG_ASSOCIATED_BFMER0_INFO 0x06E4\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n#define REG_SOUNDING_CFG1 0x06E8\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_ASSOCIATED_BFMER0_INFO_H 0x06E8\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_ASSOCIATED_BFMER1_INFO 0x06EC\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n#define REG_SOUNDING_CFG2 0x06EC\n#define REG_SOUNDING_CFG3 0x06F0\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_ASSOCIATED_BFMER1_INFO_H 0x06F0\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_TX_CSI_RPT_PARAM_BW20 0x06F4\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n#define REG_SOUNDING_CFG0 0x06F4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_TX_CSI_RPT_PARAM_BW40 0x06F8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)\n\n#define REG_ANTCD_INFO 0x06F8\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_TX_CSI_RPT_PARAM_BW80 0x06FC\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_CSI_PTR 0x06FC\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_CSI_RRSR_V1 0x06FC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_MACID1 0x0700\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MACID1_1 0x0704\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BSSID1 0x0708\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_PCIE_CFG_FORCE_LINK_L 0x0709\n#define REG_PCIE_CFG_FORCE_LINK_H 0x070A\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BSSID1_1 0x070C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY 0x070C\n#define REG_PCIE_CFG_CX_NFTS 0x070D\n#define REG_PCIE_CFG_DEFAULT_ENTR_LATENCY 0x070F\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_BCN_PSR_RPT1 0x0710\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_PCIE_CFG_L1_MISC_SEL 0x0711\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_ASSOCIATED_BFMEE_SEL 0x0714\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_ASSOCIATED_BFMEE_SEL_1 0x0714\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_SND_PTCL_CTRL 0x0718\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x0718\n#define REG_PCIE_CFG_FORCE_CLKREQ_N_PAD 0x0719\n#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY 0x071A\n#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG 0x071B\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_RX_CSI_RPT_INFO 0x071C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_L 0x071C\n#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_H 0x071D\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_RX_CSI_RPT_INFO_H 0x071F\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_NS_ARP_CTRL 0x0720\n#define REG_NS_ARP_INFO 0x0724\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_PCIE_CFG_L1_UNIT_SEL 0x0724\n#define REG_PCIE_CFG_MIN_CLKREQ_SEL 0x0725\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_NS_ARP_IPADDR 0x0728\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_PWR_INT_CTRL 0x0728\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BEAMFORMING_INFO_NSARP_V1 0x0728\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_WRITE_RX_CSI_RPT_INFO 0x072C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_RX_CSI_RPT_INFO_V1 0x072C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_BEAMFORMING_INFO_NSARP 0x072C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_NS_ARP_IPV6_MYADDR 0x0730\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_POWER_MGT_0_V1 0x0730\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_IPV6 0x0730\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_POWER_MGT_1_V1 0x0734\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_IPV6_1 0x0734\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_POWER_MGT_2_V1 0x0738\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_IPV6_2 0x0738\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_POWER_MGT_3_V1 0x073C\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_IPV6_3 0x073C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_PLCP_HEADER 0x0740\n#define REG_TXDRXDMONITOR 0x0744\n#define REG_TXDRXDMONITOR_CTL 0x0748\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_RTX_CTX_SUBTYPE_CFG 0x0750\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_WMAC_SWAES_RD0_V1 0x0754\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_SWAES_DIO_B63_B32 0x0754\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_WMAC_SWAES_RD1_V1 0x0758\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_SWAES_DIO_B95_B64 0x0758\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_WMAC_SWAES_RD3_V1 0x075C\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_SWAES_DIO_B127_B96 0x075C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_SWAES_CFG 0x0760\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BT_COEX_V2 0x0762\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_BT_COEX 0x0764\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_WLAN_ACT_MSK_CTRL 0x0768\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WLAN_ACT_MASK_CTRL 0x0768\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WLAN_ACT_MASK_CTRL_1 0x076C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BT_STATISTICS_CTRL 0x076E\n#define REG_BT_COEX_ENH_INTF_CTRL 0x076E\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BT_COEX_ENHANCED_INTR_CTRL 0x076E\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8881A_SUPPORT)\n\n#define REG_BT_ACT_STATISTICS 0x0770\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BT_ACT_STATISTICS_1 0x0774\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BT_STATISTICS_OTH_CTRL 0x0778\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BT_STATISTICS_CONTROL_REGISTER 0x0778\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BT_CMD_ID 0x077C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BT_STATUS_REPORT_REGISTER 0x077C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BT__STATUS_RPT 0x077D\n#define REG_BT_DATA 0x0780\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BT_INTERRUPT_CONTROL_REGISTER 0x0780\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_WLAN_RPT_ 0x0781\n#define REG_BT_ISR_CTRL 0x0783\n#define REG_WLAN_RPT_TO_CTR 0x0784\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER 0x0784\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BT_ISOLATION_TABLE 0x0785\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER 0x0785\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 0x0788\n#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 0x078C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BT_ISR_STA 0x078F\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BT_INTERRUPT_STATUS_REGISTER 0x078F\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_TDMA_TIME_AND_RPT_SAM_SET 0x0790\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BT_TDMA_TIME_REGISTER 0x0790\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BT_CH_INFO 0x0794\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BT_ACT_REGISTER 0x0794\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_BT_STATIC_INFO_EXT 0x0795\n#define REG_LTR_IDLE_LATENCY 0x0798\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_LTR_IDLE_LATENCY_V2 0x0798\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_OBFF_CTRL_BASIC 0x0798\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_LTR_ACTIVE_LATENCY 0x079C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_LTR_ACTIVE_LATENCY_V2 0x079C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_OBFF_CTRL2_TIMER 0x079C\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_OBFF_CTRL 0x07A0\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_LTR_CTRL_BASIC 0x07A0\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_LTR_CTRL 0x07A4\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_LTR_CTRL2_TIMER_THRESHOLD 0x07A4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_LTR_CTRL2 0x07A8\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_LTR_IDLE_LATENCY_V1 0x07A8\n#define REG_LTR_ACTIVE_LATENCY_V1 0x07AC\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_ANTTRN_CTRL 0x07B0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_ANTTRN_CTR_V1 0x07B0\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_ANTENNA_TRAINING_CONTROL_REGISTER 0x07B0\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_SMART_ANT_CONDITION 0x07B0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_ANTTRN_CTR 0x07B4\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 0x07B4\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_SMART_ANT_CTRL 0x07B4\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_WMAC_PKTCNT_RWD 0x07B8\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_CONTROL_FRAME_REPORT 0x07B8\n\n#endif\n\n#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)\n\n#define REG_WMAC_PKTCNT_CTRL 0x07BC\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_CONTROL_FRAME_CNT_CTRL 0x07BC\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL 0x07C0\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_IQ_DUMP 0x07C0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA 0x07C4\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_IQ_DUMP_1 0x07C4\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA 0x07C8\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_IQ_DUMP_2 0x07C8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_FTM_CTL 0x07CC\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_IQ_MDPK_FUNC 0x07CE\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_IQ_DUMP_EXT 0x07CF\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)\n\n#define REG_OFDM_CCK_LEN_MASK 0x07D0\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_OPTION_FUNCTION 0x07D0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_FA_FILTER1 0x07D4\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_OPTION_FUNCTION_1 0x07D4\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_FA_FILTER2 0x07D8\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_OPTION_FUNCTION_2 0x07D8\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_RX_FILTER_FUNCTION 0x07DA\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_NAN_FUN 0x07DC\n#define REG_NAN_CTL 0x07E0\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_NDP_SIG 0x07E0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_RX_NAN_ADDR_FILTER 0x07E4\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_TXCMD_INFO_FOR_RSP_PKT 0x07E4\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_NAN_ADDR 0x07E8\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TXCMD_INFO_FOR_RSP_PKT_1 0x07E8\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT)\n\n#define REG_SEC_OPT 0x07E8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_RXA1_MASK 0x07EC\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_SEC_OPT_V2 0x07EC\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WSEC_OPTION 0x07EC\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_DUMP_FUNC 0x07F0\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_RTS_ADDRESS_0 0x07F0\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT)\n\n#define REG_RTS_ADDR0 0x07F0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_MASK_LA_MAC 0x07F4\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_RTS_ADDRESS_0_1 0x07F4\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_MATCH_REF_MAC 0x07F8\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_RTS_ADDRESS_1 0x07F8\n\n#endif\n\n#if (HALMAC_8814AMP_SUPPORT)\n\n#define REG_RTS_ADDR1 0x07F8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_LA_DUMP_FUNC_EXT 0x07FC\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_RTS_ADDRESS_1_1 0x07FC\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n#define REG__RPFM_MAP1 0x07FE\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SYS_CFG3 0x1000\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_ANAPARSW_MAC_0 0x1010\n#define REG_ANAPARSW_MAC_1 0x1014\n#define REG_ANAPAR_MAC_0 0x1018\n#define REG_ANAPAR_MAC_1 0x101C\n#define REG_ANAPAR_MAC_2 0x1020\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ANAPAR_MAC_3 0x1024\n#define REG_ANAPAR_MAC_4 0x1028\n#define REG_ANAPAR_MAC_5 0x102C\n#define REG_ANAPAR_MAC_6 0x1030\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n#define REG_SYS_CFG4 0x1034\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ANAPAR_MAC_7 0x1034\n#define REG_ANAPAR_MAC_8 0x1038\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_ANAPAR_XTAL_0 0x1040\n#define REG_ANAPAR_XTAL_1 0x1044\n#define REG_ANAPAR_XTAL_2 0x1048\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_ANAPAR_XTAL_3 0x104C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ANAPAR_XTAL_AAC 0x104C\n#define REG_ANAPAR_XTAL_R_ONLY 0x1050\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_ANAPAR_XTAL_AACK_0 0x1054\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_CPHY_LDO 0x1054\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_ANAPAR_XTAL_AACK_1 0x1058\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_CPHY_BG 0x1058\n#define REG_HIMR_4 0x1060\n\n#endif\n\n#if (HALMAC_8822C_SUPPORT)\n\n#define REG_XTAL_AAC_OUTPUT\t\t\t\t0x1060\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_ANAPAR_XTAL_MODE_DECODER 0x1064\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_HISR_4 0x1064\n#define REG_HIMR_5 0x1068\n#define REG_HISR_5 0x106C\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SYS_CFG5 0x1070\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n#define REG_REGU_32K_1 0x1078\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_HIMR_6 0x1078\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n#define REG_REGU_32K_2 0x107C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_HISR_6 0x107C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_CPU_DMEM_CON 0x1080\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BOOT_REASON 0x1088\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HIMR4 0x1090\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_DATA_CPU_CTL0 0x1090\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HISR4 0x1094\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_DATA_CPU_CTL1 0x1094\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HIMR5 0x1098\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_TXDMA_STOP_HIMR 0x1098\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HISR5 0x109C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_TXDMA_STOP_HISR 0x109C\n#define REG_TXDMA_START_HIMR 0x10A0\n#define REG_TXDMA_START_HISR 0x10A4\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define REG_NFC_PAD_CTRL 0x10A8\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n#define REG_NFCPAD_CTRL 0x10A8\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_HIMR2 0x10B0\n#define REG_HISR2 0x10B4\n#define REG_HIMR3 0x10B8\n#define REG_HISR3 0x10BC\n#define REG_SW_MDIO 0x10C0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n#define REG_SW_FLUSH 0x10C4\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_DBG_GPIO_BMUX 0x10C8\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_HIMR_7 0x10C8\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_FPGA_TAG 0x10CC\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_HISR_7 0x10CC\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_WL_DSS_CTRL0 0x10D0\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_H2C_PKT_READADDR 0x10D0\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_WL_DSS_STATUS0 0x10D4\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_H2C_PKT_WRITEADDR 0x10D4\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_WL_DSS_CTRL1 0x10D8\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MEM_PWR_CRTL 0x10D8\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_WL_DSS_STATUS1 0x10DC\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_FW_DRV_HANDSHAKE 0x10DC\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n#define REG_FW_DBG0 0x10E0\n#define REG_FW_DBG1 0x10E4\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)\n\n#define REG_FW_DBG2 0x10E8\n#define REG_FW_DBG3 0x10EC\n#define REG_FW_DBG4 0x10F0\n#define REG_FW_DBG5 0x10F4\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_FW_DBG6 0x10F8\n#define REG_FW_DBG7 0x10FC\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_CR_EXT 0x1100\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_TC9_CTRL 0x1104\n#define REG_TC10_CTRL 0x1108\n#define REG_TC11_CTRL 0x110C\n#define REG_TC12_CTRL 0x1110\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_FWFF 0x1114\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_RXFF_PTR_V1 0x1118\n#define REG_RXFF_WTR_V1 0x111C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_FE2IMR 0x1120\n#define REG_FE2ISR 0x1124\n#define REG_FE3IMR 0x1128\n#define REG_FE3ISR 0x112C\n#define REG_FE4IMR 0x1130\n#define REG_FE4ISR 0x1134\n#define REG_FT1IMR 0x1138\n#define REG_FT1ISR 0x113C\n#define REG_SPWR0 0x1140\n#define REG_SPWR1 0x1144\n#define REG_SPWR2 0x1148\n#define REG_SPWR3 0x114C\n#define REG_POWSEQ 0x1150\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TC7_CTRL_V1 0x1158\n#define REG_TC8_CTRL_V1 0x115C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_RXBCN_TBTT_INTERVAL_PORT0TO3 0x1160\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_RX_BCN_TBTT_ITVL0 0x1160\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_RXBCN_TBTT_INTERVAL_PORT4 0x1164\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_RX_BCN_TBTT_ITVL1 0x1164\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n#define REG_FWIMR1 0x1168\n#define REG_FWISR1 0x116C\n#define REG_FWIMR2 0x1170\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_IO_WRAP_ERR_FLAG 0x1170\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n#define REG_FWISR2 0x1174\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_FWIMR3 0x1178\n#define REG_FWISR3 0x117C\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_SPEED_SENSOR 0x1180\n#define REG_SPEED_SENSOR1 0x1184\n#define REG_SPEED_SENSOR2 0x1188\n#define REG_SPEED_SENSOR3 0x118C\n#define REG_SPEED_SENSOR4 0x1190\n#define REG_SPEED_SENSOR5 0x1194\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_RXPKTBUF_1_MAX_ADDR 0x1198\n#define REG_RXFWBUF_1_MAX_ADDR 0x119C\n#define REG_IO_WRAP_ERR_FLAG_V1 0x11A0\n#define REG_RXPKTBUF_1_READ 0x11A4\n#define REG_RXPKTBUF_1_WRITE 0x11A8\n#define REG_BUFF_DBGUG 0x11AC\n#define REG_RFE_CTRL_PAD_E2 0x11B0\n#define REG_RFE_CTRL_PAD_SR 0x11B4\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n#define REG_EXT_QUEUE_REG 0x11C0\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_H2C_PRIORITY_SEL 0x11C0\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n#define REG_COUNTER_CONTROL 0x11C4\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_COUNTER_CTRL 0x11C4\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n#define REG_COUNTER_TH 0x11C8\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_COUNTER_THRESHOLD 0x11C8\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_COUNTER_SET 0x11CC\n#define REG_COUNTER_OVERFLOW 0x11D0\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n#define REG_TDE_LEN_TH 0x11D4\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_TXDMA_LEN_THRESHOLD 0x11D4\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n#define REG_RDE_LEN_TH 0x11D8\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_RXDMA_LEN_THRESHOLD 0x11D8\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT)\n\n#define REG_PCIE_EXEC_TIME 0x11DC\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_PCIE_EXEC_TIME_THRESHOLD 0x11DC\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_FT2IMR 0x11E0\n#define REG_FT2ISR 0x11E4\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_MSG2 0x11F0\n#define REG_MSG3 0x11F4\n#define REG_MSG4 0x11F8\n#define REG_MSG5 0x11FC\n#define REG_DDMA_CH0SA 0x1200\n#define REG_DDMA_CH0DA 0x1204\n#define REG_DDMA_CH0CTRL 0x1208\n#define REG_DDMA_CH1SA 0x1210\n#define REG_DDMA_CH1DA 0x1214\n#define REG_DDMA_CH1CTRL 0x1218\n#define REG_DDMA_CH2SA 0x1220\n#define REG_DDMA_CH2DA 0x1224\n#define REG_DDMA_CH2CTRL 0x1228\n#define REG_DDMA_CH3SA 0x1230\n#define REG_DDMA_CH3DA 0x1234\n#define REG_DDMA_CH3CTRL 0x1238\n#define REG_DDMA_CH4SA 0x1240\n#define REG_DDMA_CH4DA 0x1244\n#define REG_DDMA_CH4CTRL 0x1248\n#define REG_DDMA_CH5SA 0x1250\n#define REG_DDMA_CH5DA 0x1254\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)\n\n#define REG_REG_DDMA_CH5CTRL 0x1258\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_DDMA_CH5CTRL 0x1258\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_DDMA_INT_MSK 0x12E0\n#define REG_DDMA_CHSTATUS 0x12E8\n#define REG_DDMA_CHKSUM 0x12F0\n#define REG_DDMA_MONITOR 0x12FC\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_STC_INT_CS 0x1300\n#define REG_ST_INT_CFG 0x1304\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH4_ACH5_TXBD_NUM 0x130C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n#define REG_CMU_DLY_CTRL 0x1310\n#define REG_CMU_DLY_CFG 0x1314\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_FWCMDQ_TXBD_IDX 0x1318\n#define REG_P0HI8Q_TXBD_IDX 0x131C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_H2CQ_TXBD_DESA 0x1320\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_H2CQ_TXBD_DESA_L 0x1320\n#define REG_H2CQ_TXBD_DESA_H 0x1324\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_H2CQ_TXBD_NUM 0x1328\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_H2CQ_TXBD_IDX 0x132C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_H2CQ_CSR 0x1330\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0HI9Q_TXBD_IDX 0x1334\n#define REG_P0HI10Q_TXBD_IDX 0x1338\n#define REG_P0HI11Q_TXBD_IDX 0x133C\n#define REG_P0HI12Q_TXBD_IDX 0x1340\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_CPL_BUFFER_MONITOR 0x1344\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0HI13Q_TXBD_IDX 0x1344\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_PTM_LOCAL_CLOCK 0x1348\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0HI14Q_TXBD_IDX 0x1348\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_PTM_LOCAL_CLOCK_H 0x134C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_P0HI15Q_TXBD_IDX 0x134C\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_TSFT_PTM_DIFF 0x1350\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_AXI_EXCEPT_CS 0x1350\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_CHANGE_PCIE_SPEED 0x1350\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_PTM_CTRL_STATUS 0x1354\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_AXI_EXCEPT_TIME 0x1354\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_DEBUG_STATE1 0x1354\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_QUEUE_HEADER_CUR_REMAIN 0x1358\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI8Q_TXBD_IDX 0x1358\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_DEBUG_STATE2 0x1358\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_QUEUE_HEADER_MIN_REMAIN 0x135C\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI9Q_TXBD_IDX 0x135C\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_DEBUG_STATE3 0x135C\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI10Q_TXBD_IDX 0x1360\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH5_TXBD_DESA_L 0x1360\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI11Q_TXBD_IDX 0x1364\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH5_TXBD_DESA_H 0x1364\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI12Q_TXBD_IDX 0x1368\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH6_TXBD_DESA_L 0x1368\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI13Q_TXBD_IDX 0x136C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH6_TXBD_DESA_H 0x136C\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI14Q_TXBD_IDX 0x1370\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH7_TXBD_DESA_L 0x1370\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI15Q_TXBD_IDX 0x1374\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH7_TXBD_DESA_H 0x1374\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI8Q_TXBD_DESA 0x1378\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH8_TXBD_DESA_L 0x1378\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_CHNL_DMA_CFG_V1 0x137C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH8_TXBD_DESA_H 0x137C\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI9Q_TXBD_DESA 0x1380\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH9_TXBD_DESA_L 0x1380\n#define REG_ACH9_TXBD_DESA_H 0x1384\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI10Q_TXBD_DESA 0x1388\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH10_TXBD_DESA_L 0x1388\n#define REG_ACH10_TXBD_DESA_H 0x138C\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI11Q_TXBD_DESA 0x1390\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH11_TXBD_DESA_L 0x1390\n#define REG_ACH11_TXBD_DESA_H 0x1394\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI12Q_TXBD_DESA 0x1398\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH12_TXBD_DESA_L 0x1398\n#define REG_ACH12_TXBD_DESA_H 0x139C\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI13Q_TXBD_DESA 0x13A0\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH13_TXBD_DESA_L 0x13A0\n#define REG_ACH13_TXBD_DESA_H 0x13A4\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI14Q_TXBD_DESA 0x13A8\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_HI0Q_TXBD_DESA_L 0x13A8\n#define REG_HI0Q_TXBD_DESA_H 0x13AC\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI15Q_TXBD_DESA 0x13B0\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_HI1Q_TXBD_DESA_L 0x13B0\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_PCIE_HISR0_V1 0x13B4\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_HI1Q_TXBD_DESA_H 0x13B4\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI8Q_TXBD_NUM 0x13B8\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_HI2Q_TXBD_DESA_L 0x13B8\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI9Q_TXBD_NUM 0x13BA\n#define REG_HI10Q_TXBD_NUM 0x13BC\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_PCIE_HISR1_V1 0x13BC\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_HI2Q_TXBD_DESA_H 0x13BC\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI11Q_TXBD_NUM 0x13BE\n#define REG_HI12Q_TXBD_NUM 0x13C0\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_HI3Q_TXBD_DESA_L 0x13C0\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI13Q_TXBD_NUM 0x13C2\n#define REG_HI14Q_TXBD_NUM 0x13C4\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_HI3Q_TXBD_DESA_H 0x13C4\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_HI15Q_TXBD_NUM 0x13C6\n#define REG_HIQ_DMA_STOP 0x13C8\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_HI4Q_TXBD_DESA_L 0x13C8\n#define REG_HI4Q_TXBD_DESA_H 0x13CC\n#define REG_HI5Q_TXBD_DESA_L 0x13D0\n#define REG_HI5Q_TXBD_DESA_H 0x13D4\n#define REG_HI6Q_TXBD_DESA_L 0x13D8\n#define REG_HI6Q_TXBD_DESA_H 0x13DC\n#define REG_HI7Q_TXBD_DESA_L 0x13E0\n#define REG_HI7Q_TXBD_DESA_H 0x13E4\n#define REG_ACH8_ACH9_TXBD_NUM 0x13E8\n#define REG_ACH10_ACH11_TXBD_NUM 0x13EC\n#define REG_ACH12_ACH13_TXBD_NUM 0x13F0\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)\n\n#define REG_OLD_DEHANG 0x13F4\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_ACH4_TXBD_DESA_L 0x13F8\n#define REG_ACH4_TXBD_DESA_H 0x13FC\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_Q0_Q1_INFO 0x1400\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_ARFR6 0x1400\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_MU_OFFSET 0x1400\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_Q2_Q3_INFO 0x1404\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define REG_ARFRH6 0x1404\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_Q4_Q5_INFO 0x1408\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_ARFR7 0x1408\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_Q6_Q7_INFO 0x140C\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define REG_ARFRH7 0x140C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_MGQ_HIQ_INFO 0x1410\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_ARFR8 0x1410\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \\\n     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_CMDQ_BCNQ_INFO 0x1414\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define REG_ARFRH8 0x1414\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n#define REG_USEREG_SETTING 0x1420\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_LOOPBACK_OPTION 0x1420\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_AESIV_SETTING 0x1424\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_BF0_TIME_SETTING 0x1428\n#define REG_BF1_TIME_SETTING 0x142C\n#define REG_BF_TIMEOUT_EN 0x1430\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MACID_RELEASE0 0x1434\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_MACID_RELEASE_INFO 0x1434\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MACID_RELEASE1 0x1438\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_MACID_RELEASE_SUCCESS_INFO 0x1438\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MACID_RELEASE2 0x143C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_MACID_RELEASE_CTRL 0x143C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MACID_RELEASE3 0x1440\n#define REG_MACID_RELEASE_SETTING 0x1444\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_FAST_EDCA_VOVI_SETTING 0x1448\n#define REG_FAST_EDCA_BEBK_SETTING 0x144C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MACID_DROP0 0x1450\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_MACID_DROP_INFO 0x1450\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MACID_DROP1 0x1454\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_MACID_DROP_CTRL 0x1454\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MACID_DROP2 0x1458\n#define REG_MACID_DROP3 0x145C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_R_MACID_RELEASE_SUCCESS_0 0x1460\n#define REG_R_MACID_RELEASE_SUCCESS_1 0x1464\n#define REG_R_MACID_RELEASE_SUCCESS_2 0x1468\n#define REG_R_MACID_RELEASE_SUCCESS_3 0x146C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n#define REG_MGG_FIFO_CRTL 0x1470\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MGQ_FIFO_WRITE_POINTER 0x1470\n#define REG_MGQ_FIFO_READ_POINTER 0x1472\n#define REG_MGQ_FIFO_ENABLE 0x1472\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n#define REG_MGG_FIFO_INT 0x1474\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MGQ_FIFO_RELEASE_INT_MASK 0x1474\n#define REG_MGQ_FIFO_RELEASE_INT_FLAG 0x1476\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n#define REG_MGG_FIFO_LIFETIME 0x1478\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MGQ_FIFO_VALID_MAP 0x1478\n#define REG_MGQ_FIFO_LIFETIME 0x147A\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x147C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SHCUT_SETTING 0x1480\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_PKT_TRANS 0x1480\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SHCUT_LLC_ETH_TYPE0 0x1484\n#define REG_SHCUT_LLC_ETH_TYPE1 0x1488\n#define REG_SHCUT_LLC_OUI0 0x148C\n#define REG_SHCUT_LLC_OUI1 0x1490\n#define REG_SHCUT_LLC_OUI2 0x1494\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8822B_SUPPORT)\n\n#define REG_SHCUT_LLC_OUI3 0x1498\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_FWCMDQ_CTRL 0x14A0\n#define REG_FWCMDQ_PAGE 0x14A4\n#define REG_FWCMDQ_INFO 0x14A8\n#define REG_FWCMDQ_HOLD_PKTNUM 0x14AC\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MU_TX_CTL 0x14C0\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_MU_TX_CTRL 0x14C0\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MU_STA_GID_VLD 0x14C4\n#define REG_MU_STA_USER_POS_INFO 0x14C8\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MU_STA_USER_POS_INFO_H 0x14CC\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_CHNL_INFO_CTRL 0x14D0\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)\n\n#define REG_MU_TRX_DBG_CNT 0x14D0\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_CHNL_IDLE_TIME 0x14D4\n#define REG_CHNL_BUSY_TIME 0x14D8\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MU_TRX_DBG_CNT_V1 0x14DC\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_NEW_EDCA_CTRL 0x14F0\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n#define REG_SU_DURATION 0x14F0\n#define REG_MU_DURATION 0x14F2\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n#define REG_SWPS_CTRL 0x14F4\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n#define REG_HW_NDPA_RTY_LIMIT 0x14F4\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n#define REG_SWPS_PKT_TH 0x14F6\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)\n\n#define REG_SWPS_TIME_TH 0x14F8\n#define REG_MACID_SWPS_EN 0x14FC\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_CPUMGQ_TX_TIMER 0x1500\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_PORT_CTRL_SEL 0x1500\n#define REG_PORT_CTRL_CFG 0x1501\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_PS_TIMER_A 0x1504\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_TBTT_PROHIBIT_CFG 0x1504\n#define REG_DRVERLYINT_CFG 0x1507\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_PS_TIMER_B 0x1508\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_BCNDMATIM_CFG 0x1508\n#define REG_CTWND_CFG 0x1509\n#define REG_BCNIVLCUNT_CFG 0x150A\n#define REG_EARLY_128US_CFG 0x150B\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_PS_TIMER_C 0x150C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_TSFTR_SYNC_OFFSET_CFG 0x150C\n#define REG_TSFTR_SYNC_CTRL_CFG 0x150F\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL 0x1510\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_BCN_SPACE_CFG 0x1510\n#define REG_EARLY_INT_ADJUST_CFG 0x1512\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_CPUMGQ_TX_TIMER_EARLY 0x1514\n#define REG_PS_TIMER_A_EARLY 0x1515\n#define REG_PS_TIMER_B_EARLY 0x1516\n#define REG_PS_TIMER_C_EARLY 0x1517\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_CPUMGQ_PARAMETER 0x1518\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_SW_TBTT_TSF_INFO 0x151C\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_TSF_SYN_CTRL0 0x1520\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TSF_SYNC_ADJ 0x1520\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_TSFTR_LOW 0x1520\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_TSF_SYN_CTRL1 0x1521\n#define REG_TSF_SYN_OFFSET0 0x1522\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_TSF_SYN_OFFSET1 0x1524\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TSF_ADJ_VLAUE 0x1524\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_TSFTR_HIGH 0x1524\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define REG_TSF_SYN_OFFSET2 0x1528\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TSF_ADJ_VLAUE_2 0x1528\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_BCN_ERR_CNT_MAC 0x1528\n#define REG_BCN_ERR_CNT_EDCCA 0x1529\n#define REG_BCN_ERR_CNT_CCA 0x152A\n#define REG_BCN_ERR_CNT_INVALID 0x152B\n#define REG_BCN_ERR_CNT_OTHERS 0x152C\n#define REG_RX_BCN_TIMER 0x152D\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define REG_TSF_SYN_COMPARE_VALUE_L 0x1530\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_TSF_SYN_COMPARE_VALUE 0x1530\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_TBTT_CTN_AREA_V1 0x1530\n#define REG_BCN_MAX_ERR_V1 0x1531\n#define REG_RXTSF_OFFSET_CCK_V1 0x1532\n#define REG_RXTSF_OFFSET_OFDM_V1 0x1533\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT)\n\n#define REG_TSF_SYN_COMPARE_VALUE_H 0x1534\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_SUB_BCN_SPACE 0x1534\n#define REG_MBID_NUM_V1 0x1535\n#define REG_MBSSID_CTRL_V1 0x1536\n#define REG_USTIME_TSF_V1 0x1538\n#define REG_BW_CFG 0x1539\n#define REG_ATIMWND_CFG 0x153A\n#define REG_DTIM_COUNTER_CFG 0x153B\n#define REG_ATIM_DTIM_CTRL_SEL 0x153C\n#define REG_ATIMUGT_V1 0x153D\n#define REG_BCNDROPCTRL_V1 0x153E\n#define REG_DIS_ATIM_V1 0x1540\n#define REG_HIQ_NO_LMT_EN_V1 0x1544\n#define REG_P2PPS_CTRL_V1 0x1548\n#define REG_P2PPS_SPEC_STATE_V1 0x154A\n#define REG_P2PPS_STATE_V1 0x154B\n#define REG_P2PPS1_CTRL_V1 0x154C\n#define REG_P2PPS1_SPEC_STATE_V1 0x154E\n#define REG_P2PPS1_STATE_V1 0x154F\n#define REG_P2PPS2_CTRL_V1 0x1550\n#define REG_P2PPS2_SPEC_STATE_V1 0x1552\n#define REG_P2PPS2_STATE_V1 0x1553\n#define REG_P2PON_DIS_TXTIME_V1 0x1554\n#define REG_P2POFF_DIS_TXTIME_V1 0x1555\n#define REG_CHG_POWER_BCN_AREA 0x1556\n#define REG_NOA_SEL 0x1557\n#define REG_NOA_PARAM_V1 0x1558\n#define REG_NOA_PARAM_1_V1 0x155C\n#define REG_NOA_PARAM_2_V1 0x1560\n#define REG_NOA_PARAM_3_V1 0x1564\n#define REG_NOA_ON_ERLY_TIME_V1 0x1568\n#define REG_NOA_OFF_ERLY_TIME_V1 0x1569\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_P2PPS_HW_AUTO_PAUSE_CTRL 0x156C\n#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL 0x1570\n#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL 0x1574\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_RX_TBTT_SHIFT 0x1578\n#define REG_FREERUN_CNT_LOW 0x1580\n#define REG_FREERUN_CNT_HIGH 0x1584\n#define REG_CPUMGQ_TX_TIMER_V1 0x1588\n#define REG_PS_TIMER_0 0x158C\n#define REG_PS_TIMER_1 0x1590\n#define REG_PS_TIMER_2 0x1594\n#define REG_PS_TIMER_3 0x1598\n#define REG_PS_TIMER_4 0x159C\n#define REG_PS_TIMER_5 0x15A0\n#define REG_PS_TIMER_01_CTRL 0x15A4\n#define REG_PS_TIMER_23_CTRL 0x15A8\n#define REG_PS_TIMER_45_CTRL 0x15AC\n#define REG_CPUMGQ_FREERUN_TIMER_CTRL 0x15B0\n#define REG_CPUMGQ_PROHIBIT 0x15B4\n#define REG_TIMER_COMPARE 0x15C0\n#define REG_TIMER_COMPARE_VALUE_LOW 0x15C4\n#define REG_TIMER_COMPARE_VALUE_HIGH 0x15C8\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_SCHEDULER_COUNTER 0x15D0\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_BCN_PSR_RPT2 0x1600\n#define REG_BCN_PSR_RPT3 0x1604\n#define REG_BCN_PSR_RPT4 0x1608\n#define REG_A1_ADDR_MASK 0x160C\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_RXPSF_CTRL 0x1610\n#define REG_RXPSF_TYPE_CTRL 0x1614\n#define REG_CAM_ACCESS_CTRL 0x1618\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_HT_SND_REF_RATE 0x161C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_CUT_AMSDU_CTRL 0x161C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_MACID2 0x1620\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MACID2_H 0x1624\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_BSSID2 0x1628\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BSSID2_H 0x162C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_MACID3 0x1630\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MACID3_H 0x1634\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_BSSID3 0x1638\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BSSID3_H 0x163C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_MACID4 0x1640\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MACID4_H 0x1644\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \\\n     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_BSSID4 0x1648\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_BSSID4_H 0x164C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_NOA_REPORT 0x1650\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_NOA_REPORT_1 0x1654\n#define REG_NOA_REPORT_2 0x1658\n#define REG_NOA_REPORT_3 0x165C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_PWRBIT_SETTING 0x1660\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_GENERAL_OPTION 0x1664\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_FWPHYFF_RCR 0x1668\n#define REG_ADDRCAM_WRITE_CONTENT 0x166C\n#define REG_ADDRCAM_READ_CONTENT 0x1670\n#define REG_ADDRCAM_CFG 0x1674\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_CSI_RRSR 0x1678\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define REG_WMAC_CSI_FRAME_RRSR_SETTING 0x1678\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)\n\n#define REG_WMAC_MU_BF_OPTION 0x167C\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_MU_BF_OPTION 0x167C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_PAUSE_BB_CLR_TH 0x167D\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT)\n\n#define REG_WMAC_MU_ARB 0x167E\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG__WMAC_MULBK_BUF 0x167E\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_WMAC_MULBK_BUF 0x167E\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_MU_OPTION 0x167F\n#define REG_WMAC_MU_BF_CTL 0x1680\n#define REG_WMAC_MU_BFRPT_PARA 0x1682\n#define REG_WMAC_ASSOCIATED_MU_BFMEE2 0x1684\n#define REG_WMAC_ASSOCIATED_MU_BFMEE3 0x1686\n#define REG_WMAC_ASSOCIATED_MU_BFMEE4 0x1688\n#define REG_WMAC_ASSOCIATED_MU_BFMEE5 0x168A\n#define REG_WMAC_ASSOCIATED_MU_BFMEE6 0x168C\n#define REG_WMAC_ASSOCIATED_MU_BFMEE7 0x168E\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_BB_STOP_RX_COUNTER 0x1690\n#define REG_WMAC_PLCP_MONITOR 0x1694\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_PLCP_MONITOR_MUTX 0x1698\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_WMAC_DEBUG_PORT 0x1698\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WMAC_CSIDMA_CFG 0x169C\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TRANSMIT_ADDRSS_0 0x16A0\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TRANSMIT_ADDRSS_0_H 0x16A4\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TRANSMIT_ADDRSS_1 0x16A8\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TRANSMIT_ADDRSS_1_H 0x16AC\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TRANSMIT_ADDRSS_2 0x16B0\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TRANSMIT_ADDRSS_2_H 0x16B4\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TRANSMIT_ADDRSS_3 0x16B8\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TRANSMIT_ADDRSS_3_H 0x16BC\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TRANSMIT_ADDRSS_4 0x16C0\n\n#endif\n\n#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_TRANSMIT_ADDRSS_4_H 0x16C4\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n#define REG_SND_AID12 0x16D0\n#define REG_SND_PKT_INFO 0x16D2\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_BIST_RSTN0 0x2100\n#define REG_BIST_RSTN2 0x2108\n#define REG_BIST_MODE_NRML0 0x2110\n#define REG_BIST_MODE_NRML1 0x2114\n#define REG_BIST_MODE_NRML2 0x2118\n#define REG_BIST_MODE_NRML3 0x211C\n#define REG_BIST_DONE_NRML_MAC 0x2150\n#define REG_BIST_DONE_NRML1 0x2158\n#define REG_BIST_DONE_DRF_MAC 0x2160\n#define REG_BIST_DONE_DRF 0x2164\n#define REG_BIST_DONE_DRF1 0x2168\n#define REG_BIST_FAIL_NRML_MAC 0x2170\n#define REG_BIST_FAIL_NRML 0x2174\n#define REG_BIST_FAIL_NRML1 0x2178\n#define REG_BIST_FAIL_NRML_MAC_V1 0x2180\n#define REG_BIST_FAIL_NRML_V1 0x2184\n#define REG_BIST_FAIL_NRML1_V1 0x2188\n#define REG_BIST_MISR_DATAOUT 0x2190\n#define REG_BIST_MISR_DATAOUT1 0x2194\n#define REG_BIST_MISR_DATAOUT_CPU 0x2198\n#define REG_BIST_MISR_DATAOUT_CPU1 0x219C\n#define REG_BIST_MISR_DATAOUT_CPU2 0x21A0\n#define REG_BIST_MISR_DATOUT_CPU3 0x21A4\n#define REG_DMA_RQPN_INFO_0 0x2200\n#define REG_DMA_RQPN_INFO_1 0x2204\n#define REG_DMA_RQPN_INFO_2 0x2208\n#define REG_DMA_RQPN_INFO_3 0x220C\n#define REG_DMA_RQPN_INFO_4 0x2210\n#define REG_DMA_RQPN_INFO_5 0x2214\n#define REG_DMA_RQPN_INFO_6 0x2218\n#define REG_DMA_RQPN_INFO_7 0x221C\n#define REG_DMA_RQPN_INFO_8 0x2220\n#define REG_DMA_RQPN_INFO_9 0x2224\n#define REG_DMA_RQPN_INFO_10 0x2228\n#define REG_DMA_RQPN_INFO_11 0x222C\n#define REG_DMA_RQPN_INFO_12 0x2230\n#define REG_DMA_RQPN_INFO_13 0x2234\n#define REG_DMA_RQPN_INFO_14 0x2238\n#define REG_DMA_RQPN_INFO_15 0x223C\n#define REG_DMA_RQPN_INFO_16 0x2240\n#define REG_HWAMSDU_CTL1 0x2250\n#define REG_HWAMSDU_CTL2 0x2254\n#define REG_HI8Q_TXBD_DESA_L 0x2300\n#define REG_HI8Q_TXBD_DESA_H 0x2304\n#define REG_HI9Q_TXBD_DESA_L 0x2308\n#define REG_HI9Q_TXBD_DESA_H 0x230C\n#define REG_HI10Q_TXBD_DESA_L 0x2310\n#define REG_HI10Q_TXBD_DESA_H 0x2314\n#define REG_HI11Q_TXBD_DESA_L 0x2318\n#define REG_HI11Q_TXBD_DESA_H 0x231C\n#define REG_HI12Q_TXBD_DESA_L 0x2320\n#define REG_HI12Q_TXBD_DESA_H 0x2324\n#define REG_HI13Q_TXBD_DESA_L 0x2328\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_H2CQ_TXBD_IDX_V1 0x232C\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_HI13Q_TXBD_DESA_H 0x232C\n#define REG_HI14Q_TXBD_DESA_L 0x2330\n#define REG_HI14Q_TXBD_DESA_H 0x2334\n#define REG_HI15Q_TXBD_DESA_L 0x2338\n#define REG_HI15Q_TXBD_DESA_H 0x233C\n#define REG_HI16Q_TXBD_DESA_L 0x2340\n#define REG_HI16Q_TXBD_DESA_H 0x2344\n#define REG_HI17Q_TXBD_DESA_L 0x2348\n#define REG_HI17Q_TXBD_DESA_H 0x234C\n#define REG_HI18Q_TXBD_DESA_L 0x2350\n#define REG_HI18Q_TXBD_DESA_H 0x2354\n#define REG_HI19Q_TXBD_DESA_L 0x2358\n#define REG_HI19Q_TXBD_DESA_H 0x235C\n#define REG_BD_RWPTR_CLR6 0x2364\n#define REG_P0HI16Q_TXBD_IDX 0x2370\n#define REG_P0HI17Q_TXBD_IDX 0x2374\n#define REG_P0HI18Q_TXBD_IDX 0x2378\n#define REG_P0HI19Q_TXBD_IDX 0x237C\n#define REG_P0HI16Q_HI17Q_TXBD_NUM 0x2380\n#define REG_P0HI18Q_HI19Q_TXBD_NUM 0x2384\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_PCIE_HISR2_V1 0x23B4\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_PCIE_HISR0 0x23B4\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define REG_PCIE_HISR3_V1 0x23BC\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_PCIE_HISR1 0x23BC\n#define REG_P0HI8Q_HI9Q_TXBD_NUM 0x23C0\n#define REG_P0HI10Q_HI11Q_TXBD_NUM 0x23C4\n#define REG_P0HI12Q_HI13Q_TXBD_NUM 0x23C8\n#define REG_P0HI14Q_HI15Q_TXBD_NUM 0x23CC\n#define REG_ACH6_ACH7_TXBD_NUM 0x23F0\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define REG_BF0_TIME_SETTING_V1 0x2428\n#define REG_BF1_TIME_SETTING_V1 0x242C\n#define REG_BF_TIMEOUT_EN_V1 0x2430\n#define REG_MACID_RELEASE0_V1 0x2434\n#define REG_MACID_RELEASE1_V1 0x2438\n#define REG_MACID_RELEASE2_V1 0x243C\n#define REG_MACID_RELEASE3_V1 0x2440\n#define REG_MACID_RELEASE_SETTING_V1 0x2444\n#define REG_FAST_EDCA_VOVI_SETTING_V1 0x2448\n#define REG_FAST_EDCA_BEBK_SETTING_V1 0x244C\n#define REG_R_MACID_RELEASE_SUCCESS_0_V1 0x2460\n#define REG_R_MACID_RELEASE_SUCCESS_1_V1 0x2464\n#define REG_R_MACID_RELEASE_SUCCESS_2_V1 0x2468\n#define REG_R_MACID_RELEASE_SUCCESS_3_V1 0x246C\n#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_V1 0x247C\n#define REG_NAN_INFO0 0x2480\n#define REG_NAN_INFO1 0x2484\n#define REG_NAN_INFO2 0x2488\n#define REG_NAN_INFO3 0x248C\n#define REG_NAN_INFO4 0x2490\n#define REG_NAN_INFO5 0x2494\n#define REG_NAN_INFO6 0x2498\n#define REG_NAN_INFO7 0x249C\n#define REG_NAN_INFO8 0x24A0\n#define REG_NAN_INFO9 0x24A4\n#define REG_CHNL_INFO_CTRL_V1 0x24D0\n#define REG_CHNL_IDLE_TIME_V1 0x24D4\n#define REG_CHNL_BUSY_TIME_V1 0x24D8\n#define REG_SWPS_CTRL_V1 0x24F4\n#define REG_SWPS_PKT_TH_V1 0x24F6\n#define REG_SWPS_TIME_TH_V1 0x24F8\n#define REG_MACID_SWPS_EN_V1 0x24FC\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define REG_TXPAGE_INT_CTRL_0 0x3200\n#define REG_TXPAGE_INT_CTRL_1 0x3204\n#define REG_TXPAGE_INT_CTRL_2 0x3208\n#define REG_TXPAGE_INT_CTRL_3 0x320C\n#define REG_TXPAGE_INT_CTRL_4 0x3210\n#define REG_TXPAGE_INT_CTRL_5 0x3214\n#define REG_TXPAGE_INT_CTRL_6 0x3218\n#define REG_TXPAGE_INT_CTRL_7 0x321C\n#define REG_TXPAGE_INT_CTRL_8 0x3220\n#define REG_TXPAGE_INT_CTRL_9 0x3224\n#define REG_TXPAGE_INT_CTRL_10 0x3228\n#define REG_TXPAGE_INT_CTRL_11 0x322C\n#define REG_TXPAGE_INT_CTRL_12 0x3230\n#define REG_TXPAGE_INT_CTRL_13 0x3234\n#define REG_TXPAGE_INT_CTRL_14 0x3238\n#define REG_TXPAGE_INT_CTRL_15 0x323C\n#define REG_TXPAGE_INT_CTRL_16 0x3240\n#define REG_ACH4_TXBD_IDX 0x3340\n#define REG_ACH5_TXBD_IDX 0x3344\n#define REG_ACH6_TXBD_IDX 0x3348\n#define REG_ACH7_TXBD_IDX 0x334C\n#define REG_ACH8_TXBD_IDX 0x3350\n#define REG_ACH9_TXBD_IDX 0x3354\n#define REG_ACH10_TXBD_IDX 0x3358\n#define REG_ACH11_TXBD_IDX 0x335C\n#define REG_ACH12_TXBD_IDX 0x3360\n#define REG_ACH13_TXBD_IDX 0x3364\n#define REG_AC_CHANNEL0_WEIGHT 0x3368\n#define REG_AC_CHANNEL1_WEIGHT 0x3369\n#define REG_AC_CHANNEL2_WEIGHT 0x336A\n#define REG_AC_CHANNEL3_WEIGHT 0x336B\n#define REG_AC_CHANNEL4_WEIGHT 0x336C\n#define REG_AC_CHANNEL5_WEIGHT 0x336D\n#define REG_AC_CHANNEL6_WEIGHT 0x336E\n#define REG_AC_CHANNEL7_WEIGHT 0x336F\n#define REG_AC_CHANNEL8_WEIGHT 0x3370\n#define REG_AC_CHANNEL9_WEIGHT 0x3371\n#define REG_AC_CHANNEL10_WEIGHT 0x3372\n#define REG_AC_CHANNEL11_WEIGHT 0x3373\n#define REG_AC_CHANNEL12_WEIGHT 0x3374\n#define REG_AC_CHANNEL13_WEIGHT 0x3375\n#define REG_PCIE_HISR2 0x33B4\n#define REG_PCIE_HISR3 0x33BC\n\n#endif\n\n/* ----------------------------------------------------- */\n/*\t*/\n/* 0xFB00h ~ 0xFCFFh\tTX/RX packet buffer affress */\n/*\t*/\n/* ----------------------------------------------------- */\n#define REG_RXPKTBUF_STARTADDR 0xFB00\n#define REG_TXPKTBUF_STARTADDR 0xFC00\n\n/* ----------------------------------------------------- */\n/*\t*/\n/* 0xFD00h ~ 0xFDFFh\t8051 CPU Local REG */\n/*\t*/\n/* ----------------------------------------------------- */\n#define REG_SYS_CTRL 0xFD00\n#define REG_PONSTS_RPT1 0xFD01\n#define REG_PONSTS_RPT2 0xFD02\n#define REG_PONSTS_RPT3 0xFD03\n#define REG_PONSTS_RPT4 0xFD04 /* 0x84 */\n#define REG_PONSTS_RPT5 0xFD05 /* 0x85 */\n#define REG_8051ERRFLAG 0xFD08\n#define REG_8051ERRFLAG_MASK 0xFD09\n#define REG_TXADDRH 0xFD10 /* Tx Packet High Address */\n#define REG_RXADDRH 0xFD11 /* Rx Packet High Address */\n#define REG_TXADDRH_EXT 0xFD12\n\n#define REG_U3_STATE 0xFD48\n\n/* for MAILBOX */\n#define REG_OUTDATA0 0xFD50\n#define REG_OUTDATA1 0xFD54\n#define REG_OUTRDY 0xFD58 /* bit[0] : OutReady, bit[1] : OutEmptyIntEn */\n\n#define REG_INDATA0 0xFD60\n#define REG_INDATA1 0xFD64\n#define REG_INRDY 0xFD68 /* bit[0] : InReady, bit[1] : InRdyIntEn */\n\n/* MCU ERROR debug REG */\n#define REG_MCUERR_PCLSB 0xFD90 /* PC[7:0] */\n#define REG_MCUERR_PCMSB 0xFD91 /* PC[15:8] */\n#define REG_MCUERR_ACC 0xFD92\n#define REG_MCUERR_B 0xFD93\n#define REG_MCUERR_DPTRLSB 0xFD94 /* DPTR[7:0] */\n#define REG_MCUERR_DPTRMSB 0xFD95 /* DPTR[15:8] */\n#define REG_MCUERR_SP 0xFD96 /* SP[7:0] */\n#define REG_MCUERR_IE 0xFD97 /* IE[7:0] */\n#define REG_MCUERR_EIE 0xFD98 /* EIE[7:0] */\n#define REG_VERA_SIM 0xFD9F\n/* 0xFD99~0xFD9F are reserved.. */\n\n/* ----------------------------------------------------- */\n/*\t*/\n/* 0xFE00h ~ 0xFEFFh\tUSB Configuration */\n/*\t*/\n/* ----------------------------------------------------- */\n\n/* RTS5101 USB Register Definition */\n#define REG_USB_SETUP_DEC_INT 0xFE00\n#define REG_USB_DMACTL 0xFE01\n#define REG_USB_IRQSTAT0 0xFE02\n#define REG_USB_IRQSTAT1 0xFE03\n#define REG_USB_IRQEN0 0xFE04\n#define REG_USB_IRQEN1 0xFE05\n#define REG_USB_AUTOPTRL 0xFE06\n#define REG_USB_AUTOPTRH 0xFE07\n#define REG_USB_AUTODAT 0xFE08\n\n#define REG_USB_SCRATCH0 0xFE09\n#define REG_USB_SCRATCH1 0xFE0A\n#define REG_USB_SEEPROM 0xFE0B\n#define REG_USB_GPIO0 0xFE0C\n#define REG_USB_GPIO0DIR 0xFE0D\n#define REG_USB_CLKSEL 0xFE0E\n#define REG_USB_BOOTCTL 0xFE0F\n\n#define REG_USB_USBCTL 0xFE10\n#define REG_USB_USBSTAT 0xFE11\n#define REG_USB_DEVADDR 0xFE12\n#define REG_USB_USBTEST 0xFE13\n#define REG_USB_FNUM0 0xFE14\n#define REG_USB_FNUM1 0xFE15\n\n#define REG_USB_EP_IDX 0xFE20\n#define REG_USB_EP_CFG 0xFE21\n#define REG_USB_EP_CTL 0xFE22\n#define REG_USB_EP_STAT 0xFE23\n#define REG_USB_EP_IRQ 0xFE24\n#define REG_USB_EP_IRQEN 0xFE25\n#define REG_USB_EP_MAXPKT0 0xFE26\n#define REG_USB_EP_MAXPKT1 0xFE27\n#define REG_USB_EP_DAT 0xFE28\n#define REG_USB_EP_BC0 0xFE29\n#define REG_USB_EP_BC1 0xFE2A\n#define REG_USB_EP_TC0 0xFE2B\n#define REG_USB_EP_TC1 0xFE2C\n#define REG_USB_EP_TC2 0xFE2D\n#define REG_USB_EP_CTL2 0xFE2E\n\n#define REG_USB_INFO 0xFE17\n#define REG_USB_SPECIAL_OPTION 0xFE55\n#define REG_USB_DMA_AGG_TO 0xFE5B\n#define REG_USB_AGG_TO 0xFE5C\n#define REG_USB_AGG_TH 0xFE5D\n\n#define REG_USB_VID 0xFE60\n#define REG_USB_PID 0xFE62\n#define REG_USB_OPT 0xFE64\n#define REG_USB_CONFIG 0xFE65\n\n#define REG_USB_PHY_PARA1 0xFE68\n#define REG_USB_PHY_PARA2 0xFE69\n#define REG_USB_PHY_PARA3 0xFE6A\n#define REG_USB_PHY_PARA4 0xFE6B\n#define REG_USB_OPT2 0xFE6C\n#define REG_USB_MAC_ADDR 0xFE70\n#define REG_USB_MANUFACTURE_SETTING 0xFE80\n#define REG_USB_PRODUCT_STRING 0xFEA0\n#define REG_USB_SERIAL_NUMBER_STRING 0xFED0\n\n#define REG_USB_ALTERNATE_SETTING 0xFE4F\n#define REG_USB_INT_BINTERVAL 0xFE6E\n#define REG_USB_GPS_EP_CONFIG 0xFE6D\n\n#endif /* __HALMAC_COM_REG_H__ */\n"
  },
  {
    "path": "hal/halmac/halmac_reg_8197f.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef __INC_HALMAC_REG_8197F_H\n#define __INC_HALMAC_REG_8197F_H\n\n#define REG_SYS_ISO_CTRL_8197F 0x0000\n#define REG_SYS_FUNC_EN_8197F 0x0002\n#define REG_SYS_PW_CTRL_8197F 0x0004\n#define REG_SYS_CLK_CTRL_8197F 0x0008\n#define REG_SYS_EEPROM_CTRL_8197F 0x000A\n#define REG_EE_VPD_8197F 0x000C\n#define REG_SYS_SWR_CTRL1_8197F 0x0010\n#define REG_SYS_SWR_CTRL2_8197F 0x0014\n#define REG_SYS_SWR_CTRL3_8197F 0x0018\n#define REG_RSV_CTRL_8197F 0x001C\n#define REG_RF0_CTRL_8197F 0x001F\n#define REG_AFE_LDO_CTRL_8197F 0x0020\n#define REG_AFE_CTRL1_8197F 0x0024\n#define REG_AFE_CTRL2_8197F 0x0028\n#define REG_AFE_CTRL3_8197F 0x002C\n#define REG_EFUSE_CTRL_8197F 0x0030\n#define REG_LDO_EFUSE_CTRL_8197F 0x0034\n#define REG_PWR_OPTION_CTRL_8197F 0x0038\n#define REG_CAL_TIMER_8197F 0x003C\n#define REG_ACLK_MON_8197F 0x003E\n#define REG_GPIO_MUXCFG_8197F 0x0040\n#define REG_GPIO_PIN_CTRL_8197F 0x0044\n#define REG_GPIO_INTM_8197F 0x0048\n#define REG_LED_CFG_8197F 0x004C\n#define REG_FSIMR_8197F 0x0050\n#define REG_FSISR_8197F 0x0054\n#define REG_HSIMR_8197F 0x0058\n#define REG_HSISR_8197F 0x005C\n#define REG_GPIO_EXT_CTRL_8197F 0x0060\n#define REG_PAD_CTRL1_8197F 0x0064\n#define REG_WL_BT_PWR_CTRL_8197F 0x0068\n#define REG_SDM_DEBUG_8197F 0x006C\n#define REG_SYS_SDIO_CTRL_8197F 0x0070\n#define REG_HCI_OPT_CTRL_8197F 0x0074\n#define REG_AFE_CTRL4_8197F 0x0078\n#define REG_LDO_SWR_CTRL_8197F 0x007C\n#define REG_MCUFW_CTRL_8197F 0x0080\n#define REG_MCU_TST_CFG_8197F 0x0084\n#define REG_HMEBOX_E0_E1_8197F 0x0088\n#define REG_HMEBOX_E2_E3_8197F 0x008C\n#define REG_WLLPS_CTRL_8197F 0x0090\n#define REG_AFE_CTRL5_8197F 0x0094\n#define REG_GPIO_DEBOUNCE_CTRL_8197F 0x0098\n#define REG_RPWM2_8197F 0x009C\n#define REG_SYSON_FSM_MON_8197F 0x00A0\n#define REG_AFE_CTRL6_8197F 0x00A4\n#define REG_PMC_DBG_CTRL1_8197F 0x00A8\n#define REG_AFE_CTRL7_8197F 0x00AC\n#define REG_HIMR0_8197F 0x00B0\n#define REG_HISR0_8197F 0x00B4\n#define REG_HIMR1_8197F 0x00B8\n#define REG_HISR1_8197F 0x00BC\n#define REG_DBG_PORT_SEL_8197F 0x00C0\n#define REG_PAD_CTRL2_8197F 0x00C4\n#define REG_PMC_DBG_CTRL2_8197F 0x00CC\n#define REG_BIST_CTRL_8197F 0x00D0\n#define REG_BIST_RPT_8197F 0x00D4\n#define REG_MEM_CTRL_8197F 0x00D8\n#define REG_AFE_CTRL8_8197F 0x00DC\n#define REG_USB_SIE_INTF_8197F 0x00E0\n#define REG_PCIE_MIO_INTF_8197F 0x00E4\n#define REG_PCIE_MIO_INTD_8197F 0x00E8\n#define REG_WLRF1_8197F 0x00EC\n#define REG_SYS_CFG1_8197F 0x00F0\n#define REG_SYS_STATUS1_8197F 0x00F4\n#define REG_SYS_STATUS2_8197F 0x00F8\n#define REG_SYS_CFG2_8197F 0x00FC\n#define REG_SYS_CFG3_8197F 0x1000\n#define REG_SYS_CFG4_8197F 0x1034\n#define REG_CPU_DMEM_CON_8197F 0x1080\n#define REG_HIMR2_8197F 0x10B0\n#define REG_HISR2_8197F 0x10B4\n#define REG_HIMR3_8197F 0x10B8\n#define REG_HISR3_8197F 0x10BC\n#define REG_SW_MDIO_8197F 0x10C0\n#define REG_SW_FLUSH_8197F 0x10C4\n#define REG_DBG_GPIO_BMUX_8197F 0x10C8\n#define REG_FPGA_TAG_8197F 0x10CC\n#define REG_WL_DSS_CTRL0_8197F 0x10D0\n#define REG_WL_DSS_CTRL1_8197F 0x10D8\n#define REG_WL_DSS_STATUS1_8197F 0x10DC\n#define REG_FW_DBG0_8197F 0x10E0\n#define REG_FW_DBG1_8197F 0x10E4\n#define REG_FW_DBG2_8197F 0x10E8\n#define REG_FW_DBG3_8197F 0x10EC\n#define REG_FW_DBG4_8197F 0x10F0\n#define REG_FW_DBG5_8197F 0x10F4\n#define REG_FW_DBG6_8197F 0x10F8\n#define REG_FW_DBG7_8197F 0x10FC\n#define REG_CR_8197F 0x0100\n#define REG_TSF_CLK_STATE_8197F 0x0108\n#define REG_TXDMA_PQ_MAP_8197F 0x010C\n#define REG_TRXFF_BNDY_8197F 0x0114\n#define REG_PTA_I2C_MBOX_8197F 0x0118\n#define REG_RXFF_BNDY_8197F 0x011C\n#define REG_FE1IMR_8197F 0x0120\n#define REG_FE1ISR_8197F 0x0124\n#define REG_CPWM_8197F 0x012C\n#define REG_FWIMR_8197F 0x0130\n#define REG_FWISR_8197F 0x0134\n#define REG_FTIMR_8197F 0x0138\n#define REG_FTISR_8197F 0x013C\n#define REG_PKTBUF_DBG_CTRL_8197F 0x0140\n#define REG_PKTBUF_DBG_DATA_L_8197F 0x0144\n#define REG_PKTBUF_DBG_DATA_H_8197F 0x0148\n#define REG_CPWM2_8197F 0x014C\n#define REG_TC0_CTRL_8197F 0x0150\n#define REG_TC1_CTRL_8197F 0x0154\n#define REG_TC2_CTRL_8197F 0x0158\n#define REG_TC3_CTRL_8197F 0x015C\n#define REG_TC4_CTRL_8197F 0x0160\n#define REG_TCUNIT_BASE_8197F 0x0164\n#define REG_TC5_CTRL_8197F 0x0168\n#define REG_TC6_CTRL_8197F 0x016C\n#define REG_MBIST_FAIL_8197F 0x0170\n#define REG_MBIST_START_PAUSE_8197F 0x0174\n#define REG_MBIST_DONE_8197F 0x0178\n#define REG_MBIST_FAIL_NRML_8197F 0x017C\n#define REG_AES_DECRPT_DATA_8197F 0x0180\n#define REG_AES_DECRPT_CFG_8197F 0x0184\n#define REG_MACCLKFRQ_8197F 0x018C\n#define REG_TMETER_8197F 0x0190\n#define REG_OSC_32K_CTRL_8197F 0x0194\n#define REG_32K_CAL_REG1_8197F 0x0198\n#define REG_C2HEVT_8197F 0x01A0\n#define REG_SW_DEFINED_PAGE1_8197F 0x01B8\n#define REG_MCUTST_I_8197F 0x01C0\n#define REG_MCUTST_II_8197F 0x01C4\n#define REG_FMETHR_8197F 0x01C8\n#define REG_HMETFR_8197F 0x01CC\n#define REG_HMEBOX0_8197F 0x01D0\n#define REG_HMEBOX1_8197F 0x01D4\n#define REG_HMEBOX2_8197F 0x01D8\n#define REG_HMEBOX3_8197F 0x01DC\n#define REG_LLT_INIT_8197F 0x01E0\n#define REG_LLT_INIT_ADDR_8197F 0x01E4\n#define REG_BB_ACCESS_CTRL_8197F 0x01E8\n#define REG_BB_ACCESS_DATA_8197F 0x01EC\n#define REG_HMEBOX_E0_8197F 0x01F0\n#define REG_HMEBOX_E1_8197F 0x01F4\n#define REG_HMEBOX_E2_8197F 0x01F8\n#define REG_HMEBOX_E3_8197F 0x01FC\n#define REG_CR_EXT_8197F 0x1100\n#define REG_FWFF_8197F 0x1114\n#define REG_RXFF_PTR_V1_8197F 0x1118\n#define REG_RXFF_WTR_V1_8197F 0x111C\n#define REG_FE2IMR_8197F 0x1120\n#define REG_FE2ISR_8197F 0x1124\n#define REG_FE3IMR_8197F 0x1128\n#define REG_FE3ISR_8197F 0x112C\n#define REG_FE4IMR_8197F 0x1130\n#define REG_FE4ISR_8197F 0x1134\n#define REG_FT1IMR_8197F 0x1138\n#define REG_FT1ISR_8197F 0x113C\n#define REG_SPWR0_8197F 0x1140\n#define REG_SPWR1_8197F 0x1144\n#define REG_SPWR2_8197F 0x1148\n#define REG_SPWR3_8197F 0x114C\n#define REG_POWSEQ_8197F 0x1150\n#define REG_TC7_CTRL_V1_8197F 0x1158\n#define REG_TC8_CTRL_V1_8197F 0x115C\n#define REG_RXBCN_TBTT_INTERVAL_PORT0TO3_8197F 0x1160\n#define REG_RXBCN_TBTT_INTERVAL_PORT4_8197F 0x1164\n#define REG_EXT_QUEUE_REG_8197F 0x11C0\n#define REG_COUNTER_CONTROL_8197F 0x11C4\n#define REG_COUNTER_TH_8197F 0x11C8\n#define REG_COUNTER_SET_8197F 0x11CC\n#define REG_COUNTER_OVERFLOW_8197F 0x11D0\n#define REG_TDE_LEN_TH_8197F 0x11D4\n#define REG_RDE_LEN_TH_8197F 0x11D8\n#define REG_PCIE_EXEC_TIME_8197F 0x11DC\n#define REG_FT2IMR_8197F 0x11E0\n#define REG_FT2ISR_8197F 0x11E4\n#define REG_MSG2_8197F 0x11F0\n#define REG_MSG3_8197F 0x11F4\n#define REG_MSG4_8197F 0x11F8\n#define REG_MSG5_8197F 0x11FC\n#define REG_FIFOPAGE_CTRL_1_8197F 0x0200\n#define REG_FIFOPAGE_CTRL_2_8197F 0x0204\n#define REG_AUTO_LLT_V1_8197F 0x0208\n#define REG_TXDMA_OFFSET_CHK_8197F 0x020C\n#define REG_TXDMA_STATUS_8197F 0x0210\n#define REG_TX_DMA_DBG_8197F 0x0214\n#define REG_TQPNT1_8197F 0x0218\n#define REG_TQPNT2_8197F 0x021C\n#define REG_TQPNT3_8197F 0x0220\n#define REG_TQPNT4_8197F 0x0224\n#define REG_RQPN_CTRL_1_8197F 0x0228\n#define REG_RQPN_CTRL_2_8197F 0x022C\n#define REG_FIFOPAGE_INFO_1_8197F 0x0230\n#define REG_FIFOPAGE_INFO_2_8197F 0x0234\n#define REG_FIFOPAGE_INFO_3_8197F 0x0238\n#define REG_FIFOPAGE_INFO_4_8197F 0x023C\n#define REG_FIFOPAGE_INFO_5_8197F 0x0240\n#define REG_H2C_HEAD_8197F 0x0244\n#define REG_H2C_TAIL_8197F 0x0248\n#define REG_H2C_READ_ADDR_8197F 0x024C\n#define REG_H2C_WR_ADDR_8197F 0x0250\n#define REG_H2C_INFO_8197F 0x0254\n#define REG_RXDMA_AGG_PG_TH_8197F 0x0280\n#define REG_RXPKT_NUM_8197F 0x0284\n#define REG_RXDMA_STATUS_8197F 0x0288\n#define REG_RXDMA_DPR_8197F 0x028C\n#define REG_RXDMA_MODE_8197F 0x0290\n#define REG_C2H_PKT_8197F 0x0294\n#define REG_FWFF_C2H_8197F 0x0298\n#define REG_FWFF_CTRL_8197F 0x029C\n#define REG_FWFF_PKT_INFO_8197F 0x02A0\n#define REG_FC2H_INFO_8197F 0x02A4\n#define REG_DDMA_CH0SA_8197F 0x1200\n#define REG_DDMA_CH0DA_8197F 0x1204\n#define REG_DDMA_CH0CTRL_8197F 0x1208\n#define REG_DDMA_CH1SA_8197F 0x1210\n#define REG_DDMA_CH1DA_8197F 0x1214\n#define REG_DDMA_CH1CTRL_8197F 0x1218\n#define REG_DDMA_CH2SA_8197F 0x1220\n#define REG_DDMA_CH2DA_8197F 0x1224\n#define REG_DDMA_CH2CTRL_8197F 0x1228\n#define REG_DDMA_CH3SA_8197F 0x1230\n#define REG_DDMA_CH3DA_8197F 0x1234\n#define REG_DDMA_CH3CTRL_8197F 0x1238\n#define REG_DDMA_CH4SA_8197F 0x1240\n#define REG_DDMA_CH4DA_8197F 0x1244\n#define REG_DDMA_CH4CTRL_8197F 0x1248\n#define REG_DDMA_CH5SA_8197F 0x1250\n#define REG_DDMA_CH5DA_8197F 0x1254\n#define REG_REG_DDMA_CH5CTRL_8197F 0x1258\n#define REG_DDMA_INT_MSK_8197F 0x12E0\n#define REG_DDMA_CHSTATUS_8197F 0x12E8\n#define REG_DDMA_CHKSUM_8197F 0x12F0\n#define REG_DDMA_MONITOR_8197F 0x12FC\n#define REG_HCI_CTRL_8197F 0x0300\n#define REG_INT_MIG_8197F 0x0304\n#define REG_BCNQ_TXBD_DESA_8197F 0x0308\n#define REG_MGQ_TXBD_DESA_8197F 0x0310\n#define REG_VOQ_TXBD_DESA_8197F 0x0318\n#define REG_VIQ_TXBD_DESA_8197F 0x0320\n#define REG_BEQ_TXBD_DESA_8197F 0x0328\n#define REG_BKQ_TXBD_DESA_8197F 0x0330\n#define REG_RXQ_RXBD_DESA_8197F 0x0338\n#define REG_HI0Q_TXBD_DESA_8197F 0x0340\n#define REG_HI1Q_TXBD_DESA_8197F 0x0348\n#define REG_HI2Q_TXBD_DESA_8197F 0x0350\n#define REG_HI3Q_TXBD_DESA_8197F 0x0358\n#define REG_HI4Q_TXBD_DESA_8197F 0x0360\n#define REG_HI5Q_TXBD_DESA_8197F 0x0368\n#define REG_HI6Q_TXBD_DESA_8197F 0x0370\n#define REG_HI7Q_TXBD_DESA_8197F 0x0378\n#define REG_MGQ_TXBD_NUM_8197F 0x0380\n#define REG_RX_RXBD_NUM_8197F 0x0382\n#define REG_VOQ_TXBD_NUM_8197F 0x0384\n#define REG_VIQ_TXBD_NUM_8197F 0x0386\n#define REG_BEQ_TXBD_NUM_8197F 0x0388\n#define REG_BKQ_TXBD_NUM_8197F 0x038A\n#define REG_HI0Q_TXBD_NUM_8197F 0x038C\n#define REG_HI1Q_TXBD_NUM_8197F 0x038E\n#define REG_HI2Q_TXBD_NUM_8197F 0x0390\n#define REG_HI3Q_TXBD_NUM_8197F 0x0392\n#define REG_HI4Q_TXBD_NUM_8197F 0x0394\n#define REG_HI5Q_TXBD_NUM_8197F 0x0396\n#define REG_HI6Q_TXBD_NUM_8197F 0x0398\n#define REG_HI7Q_TXBD_NUM_8197F 0x039A\n#define REG_TSFTIMER_HCI_8197F 0x039C\n#define REG_BD_RWPTR_CLR_8197F 0x039C\n#define REG_VOQ_TXBD_IDX_8197F 0x03A0\n#define REG_VIQ_TXBD_IDX_8197F 0x03A4\n#define REG_BEQ_TXBD_IDX_8197F 0x03A8\n#define REG_BKQ_TXBD_IDX_8197F 0x03AC\n#define REG_MGQ_TXBD_IDX_8197F 0x03B0\n#define REG_RXQ_RXBD_IDX_8197F 0x03B4\n#define REG_HI0Q_TXBD_IDX_8197F 0x03B8\n#define REG_HI1Q_TXBD_IDX_8197F 0x03BC\n#define REG_HI2Q_TXBD_IDX_8197F 0x03C0\n#define REG_HI3Q_TXBD_IDX_8197F 0x03C4\n#define REG_HI4Q_TXBD_IDX_8197F 0x03C8\n#define REG_HI5Q_TXBD_IDX_8197F 0x03CC\n#define REG_HI6Q_TXBD_IDX_8197F 0x03D0\n#define REG_HI7Q_TXBD_IDX_8197F 0x03D4\n#define REG_DBG_SEL_V1_8197F 0x03D8\n#define REG_HCI_HRPWM1_V1_8197F 0x03D9\n#define REG_HCI_HCPWM1_V1_8197F 0x03DA\n#define REG_HCI_CTRL2_8197F 0x03DB\n#define REG_HCI_HRPWM2_V1_8197F 0x03DC\n#define REG_HCI_HCPWM2_V1_8197F 0x03DE\n#define REG_HCI_H2C_MSG_V1_8197F 0x03E0\n#define REG_HCI_C2H_MSG_V1_8197F 0x03E4\n#define REG_DBI_WDATA_V1_8197F 0x03E8\n#define REG_DBI_RDATA_V1_8197F 0x03EC\n#define REG_STUCK_FLAG_V1_8197F 0x03F0\n#define REG_MDIO_V1_8197F 0x03F4\n#define REG_WDT_CFG_8197F 0x03F8\n#define REG_HCI_MIX_CFG_8197F 0x03FC\n#define REG_STC_INT_CS_8197F 0x1300\n#define REG_ST_INT_CFG_8197F 0x1304\n#define REG_CMU_DLY_CTRL_8197F 0x1310\n#define REG_CMU_DLY_CFG_8197F 0x1314\n#define REG_H2CQ_TXBD_DESA_8197F 0x1320\n#define REG_H2CQ_TXBD_NUM_8197F 0x1328\n#define REG_H2CQ_TXBD_IDX_8197F 0x132C\n#define REG_H2CQ_CSR_8197F 0x1330\n#define REG_AXI_EXCEPT_CS_8197F 0x1350\n#define REG_AXI_EXCEPT_TIME_8197F 0x1354\n#define REG_Q0_INFO_8197F 0x0400\n#define REG_Q1_INFO_8197F 0x0404\n#define REG_Q2_INFO_8197F 0x0408\n#define REG_Q3_INFO_8197F 0x040C\n#define REG_MGQ_INFO_8197F 0x0410\n#define REG_HIQ_INFO_8197F 0x0414\n#define REG_BCNQ_INFO_8197F 0x0418\n#define REG_TXPKT_EMPTY_8197F 0x041A\n#define REG_CPU_MGQ_INFO_8197F 0x041C\n#define REG_FWHW_TXQ_CTRL_8197F 0x0420\n#define REG_BCNQ_BDNY_V1_8197F 0x0424\n#define REG_LIFETIME_EN_8197F 0x0426\n#define REG_SPEC_SIFS_8197F 0x0428\n#define REG_RETRY_LIMIT_8197F 0x042A\n#define REG_TXBF_CTRL_8197F 0x042C\n#define REG_DARFRC_8197F 0x0430\n#define REG_RARFRC_8197F 0x0438\n#define REG_RRSR_8197F 0x0440\n#define REG_ARFR0_8197F 0x0444\n#define REG_ARFR1_V1_8197F 0x044C\n#define REG_CCK_CHECK_8197F 0x0454\n#define REG_AMPDU_MAX_TIME_V1_8197F 0x0455\n#define REG_BCNQ1_BDNY_V1_8197F 0x0456\n#define REG_AMPDU_MAX_LENGTH_8197F 0x0458\n#define REG_ACQ_STOP_8197F 0x045C\n#define REG_NDPA_RATE_8197F 0x045D\n#define REG_TX_HANG_CTRL_8197F 0x045E\n#define REG_NDPA_OPT_CTRL_8197F 0x045F\n#define REG_RD_RESP_PKT_TH_8197F 0x0463\n#define REG_CMDQ_INFO_8197F 0x0464\n#define REG_Q4_INFO_8197F 0x0468\n#define REG_Q5_INFO_8197F 0x046C\n#define REG_Q6_INFO_8197F 0x0470\n#define REG_Q7_INFO_8197F 0x0474\n#define REG_WMAC_LBK_BUF_HD_V1_8197F 0x0478\n#define REG_MGQ_BDNY_V1_8197F 0x047A\n#define REG_TXRPT_CTRL_8197F 0x047C\n#define REG_INIRTS_RATE_SEL_8197F 0x0480\n#define REG_BASIC_CFEND_RATE_8197F 0x0481\n#define REG_STBC_CFEND_RATE_8197F 0x0482\n#define REG_DATA_SC_8197F 0x0483\n#define REG_MACID_SLEEP3_8197F 0x0484\n#define REG_MACID_SLEEP1_8197F 0x0488\n#define REG_ARFR2_V1_8197F 0x048C\n#define REG_ARFR3_V1_8197F 0x0494\n#define REG_ARFR4_8197F 0x049C\n#define REG_ARFR5_8197F 0x04A4\n#define REG_TXRPT_START_OFFSET_8197F 0x04AC\n#define REG_POWER_STAGE1_8197F 0x04B4\n#define REG_POWER_STAGE2_8197F 0x04B8\n#define REG_SW_AMPDU_BURST_MODE_CTRL_8197F 0x04BC\n#define REG_PKT_LIFE_TIME_8197F 0x04C0\n#define REG_STBC_SETTING_8197F 0x04C4\n#define REG_STBC_SETTING2_8197F 0x04C5\n#define REG_QUEUE_CTRL_8197F 0x04C6\n#define REG_SINGLE_AMPDU_CTRL_8197F 0x04C7\n#define REG_PROT_MODE_CTRL_8197F 0x04C8\n#define REG_BAR_MODE_CTRL_8197F 0x04CC\n#define REG_RA_TRY_RATE_AGG_LMT_8197F 0x04CF\n#define REG_MACID_SLEEP2_8197F 0x04D0\n#define REG_MACID_SLEEP_8197F 0x04D4\n#define REG_HW_SEQ0_8197F 0x04D8\n#define REG_HW_SEQ1_8197F 0x04DA\n#define REG_HW_SEQ2_8197F 0x04DC\n#define REG_HW_SEQ3_8197F 0x04DE\n#define REG_NULL_PKT_STATUS_V1_8197F 0x04E0\n#define REG_PTCL_ERR_STATUS_8197F 0x04E2\n#define REG_NULL_PKT_STATUS_EXTEND_8197F 0x04E3\n#define REG_VIDEO_ENHANCEMENT_FUN_8197F 0x04E4\n#define REG_BT_POLLUTE_PKT_CNT_8197F 0x04E8\n#define REG_PTCL_DBG_8197F 0x04EC\n#define REG_TXOP_EXTRA_CTRL_8197F 0x04F0\n#define REG_CPUMGQ_TIMER_CTRL2_8197F 0x04F4\n#define REG_DUMMY_PAGE4_8197F 0x04FC\n#define REG_Q0_Q1_INFO_8197F 0x1400\n#define REG_Q2_Q3_INFO_8197F 0x1404\n#define REG_Q4_Q5_INFO_8197F 0x1408\n#define REG_Q6_Q7_INFO_8197F 0x140C\n#define REG_MGQ_HIQ_INFO_8197F 0x1410\n#define REG_CMDQ_BCNQ_INFO_8197F 0x1414\n#define REG_USEREG_SETTING_8197F 0x1420\n#define REG_AESIV_SETTING_8197F 0x1424\n#define REG_BF0_TIME_SETTING_8197F 0x1428\n#define REG_BF1_TIME_SETTING_8197F 0x142C\n#define REG_BF_TIMEOUT_EN_8197F 0x1430\n#define REG_MACID_RELEASE0_8197F 0x1434\n#define REG_MACID_RELEASE1_8197F 0x1438\n#define REG_MACID_RELEASE2_8197F 0x143C\n#define REG_MACID_RELEASE3_8197F 0x1440\n#define REG_MACID_RELEASE_SETTING_8197F 0x1444\n#define REG_FAST_EDCA_VOVI_SETTING_8197F 0x1448\n#define REG_FAST_EDCA_BEBK_SETTING_8197F 0x144C\n#define REG_MACID_DROP0_8197F 0x1450\n#define REG_MACID_DROP1_8197F 0x1454\n#define REG_MACID_DROP2_8197F 0x1458\n#define REG_MACID_DROP3_8197F 0x145C\n#define REG_R_MACID_RELEASE_SUCCESS_0_8197F 0x1460\n#define REG_R_MACID_RELEASE_SUCCESS_1_8197F 0x1464\n#define REG_R_MACID_RELEASE_SUCCESS_2_8197F 0x1468\n#define REG_R_MACID_RELEASE_SUCCESS_3_8197F 0x146C\n#define REG_MGG_FIFO_CRTL_8197F 0x1470\n#define REG_MGG_FIFO_INT_8197F 0x1474\n#define REG_MGG_FIFO_LIFETIME_8197F 0x1478\n#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0x147C\n#define REG_SHCUT_SETTING_8197F 0x1480\n#define REG_SHCUT_LLC_ETH_TYPE0_8197F 0x1484\n#define REG_SHCUT_LLC_ETH_TYPE1_8197F 0x1488\n#define REG_SHCUT_LLC_OUI0_8197F 0x148C\n#define REG_SHCUT_LLC_OUI1_8197F 0x1490\n#define REG_SHCUT_LLC_OUI2_8197F 0x1494\n#define REG_SHCUT_LLC_OUI3_8197F 0x1498\n#define REG_CHNL_INFO_CTRL_8197F 0x14D0\n#define REG_CHNL_IDLE_TIME_8197F 0x14D4\n#define REG_CHNL_BUSY_TIME_8197F 0x14D8\n#define REG_EDCA_VO_PARAM_8197F 0x0500\n#define REG_EDCA_VI_PARAM_8197F 0x0504\n#define REG_EDCA_BE_PARAM_8197F 0x0508\n#define REG_EDCA_BK_PARAM_8197F 0x050C\n#define REG_BCNTCFG_8197F 0x0510\n#define REG_PIFS_8197F 0x0512\n#define REG_RDG_PIFS_8197F 0x0513\n#define REG_SIFS_8197F 0x0514\n#define REG_TSFTR_SYN_OFFSET_8197F 0x0518\n#define REG_AGGR_BREAK_TIME_8197F 0x051A\n#define REG_SLOT_8197F 0x051B\n#define REG_TX_PTCL_CTRL_8197F 0x0520\n#define REG_TXPAUSE_8197F 0x0522\n#define REG_DIS_TXREQ_CLR_8197F 0x0523\n#define REG_RD_CTRL_8197F 0x0524\n#define REG_MBSSID_CTRL_8197F 0x0526\n#define REG_P2PPS_CTRL_8197F 0x0527\n#define REG_PKT_LIFETIME_CTRL_8197F 0x0528\n#define REG_P2PPS_SPEC_STATE_8197F 0x052B\n#define REG_QUEUE_INCOL_THR_8197F 0x0538\n#define REG_QUEUE_INCOL_EN_8197F 0x053C\n#define REG_TBTT_PROHIBIT_8197F 0x0540\n#define REG_P2PPS_STATE_8197F 0x0543\n#define REG_RD_NAV_NXT_8197F 0x0544\n#define REG_NAV_PROT_LEN_8197F 0x0546\n#define REG_FTM_CTRL_8197F 0x0548\n#define REG_FTM_TSF_CNT_8197F 0x054C\n#define REG_BCN_CTRL_8197F 0x0550\n#define REG_BCN_CTRL_CLINT0_8197F 0x0551\n#define REG_MBID_NUM_8197F 0x0552\n#define REG_DUAL_TSF_RST_8197F 0x0553\n#define REG_MBSSID_BCN_SPACE_8197F 0x0554\n#define REG_DRVERLYINT_8197F 0x0558\n#define REG_BCNDMATIM_8197F 0x0559\n#define REG_ATIMWND_8197F 0x055A\n#define REG_USTIME_TSF_8197F 0x055C\n#define REG_BCN_MAX_ERR_8197F 0x055D\n#define REG_RXTSF_OFFSET_CCK_8197F 0x055E\n#define REG_RXTSF_OFFSET_OFDM_8197F 0x055F\n#define REG_TSFTR_8197F 0x0560\n#define REG_FREERUN_CNT_8197F 0x0568\n#define REG_ATIMWND1_8197F 0x0570\n#define REG_TBTT_PROHIBIT_INFRA_8197F 0x0571\n#define REG_CTWND_8197F 0x0572\n#define REG_BCNIVLCUNT_8197F 0x0573\n#define REG_BCNDROPCTRL_8197F 0x0574\n#define REG_HGQ_TIMEOUT_PERIOD_8197F 0x0575\n#define REG_TXCMD_TIMEOUT_PERIOD_8197F 0x0576\n#define REG_MISC_CTRL_8197F 0x0577\n#define REG_BCN_CTRL_CLINT1_8197F 0x0578\n#define REG_BCN_CTRL_CLINT2_8197F 0x0579\n#define REG_BCN_CTRL_CLINT3_8197F 0x057A\n#define REG_EXTEND_CTRL_8197F 0x057B\n#define REG_P2PPS1_SPEC_STATE_8197F 0x057C\n#define REG_P2PPS1_STATE_8197F 0x057D\n#define REG_P2PPS2_SPEC_STATE_8197F 0x057E\n#define REG_P2PPS2_STATE_8197F 0x057F\n#define REG_PS_TIMER0_8197F 0x0580\n#define REG_PS_TIMER1_8197F 0x0584\n#define REG_PS_TIMER2_8197F 0x0588\n#define REG_TBTT_CTN_AREA_8197F 0x058C\n#define REG_FORCE_BCN_IFS_8197F 0x058E\n#define REG_TXOP_MIN_8197F 0x0590\n#define REG_PRE_BKF_TIME_8197F 0x0592\n#define REG_CROSS_TXOP_CTRL_8197F 0x0593\n#define REG_TBTT_INT_SHIFT_CLI0_8197F 0x0594\n#define REG_TBTT_INT_SHIFT_CLI1_8197F 0x0595\n#define REG_TBTT_INT_SHIFT_CLI2_8197F 0x0596\n#define REG_TBTT_INT_SHIFT_CLI3_8197F 0x0597\n#define REG_TBTT_INT_SHIFT_ENABLE_8197F 0x0598\n#define REG_ATIMWND2_8197F 0x05A0\n#define REG_ATIMWND3_8197F 0x05A1\n#define REG_ATIMWND4_8197F 0x05A2\n#define REG_ATIMWND5_8197F 0x05A3\n#define REG_ATIMWND6_8197F 0x05A4\n#define REG_ATIMWND7_8197F 0x05A5\n#define REG_ATIMUGT_8197F 0x05A6\n#define REG_HIQ_NO_LMT_EN_8197F 0x05A7\n#define REG_DTIM_COUNTER_ROOT_8197F 0x05A8\n#define REG_DTIM_COUNTER_VAP1_8197F 0x05A9\n#define REG_DTIM_COUNTER_VAP2_8197F 0x05AA\n#define REG_DTIM_COUNTER_VAP3_8197F 0x05AB\n#define REG_DTIM_COUNTER_VAP4_8197F 0x05AC\n#define REG_DTIM_COUNTER_VAP5_8197F 0x05AD\n#define REG_DTIM_COUNTER_VAP6_8197F 0x05AE\n#define REG_DTIM_COUNTER_VAP7_8197F 0x05AF\n#define REG_DIS_ATIM_8197F 0x05B0\n#define REG_EARLY_128US_8197F 0x05B1\n#define REG_P2PPS1_CTRL_8197F 0x05B2\n#define REG_P2PPS2_CTRL_8197F 0x05B3\n#define REG_TIMER0_SRC_SEL_8197F 0x05B4\n#define REG_NOA_UNIT_SEL_8197F 0x05B5\n#define REG_P2POFF_DIS_TXTIME_8197F 0x05B7\n#define REG_MBSSID_BCN_SPACE2_8197F 0x05B8\n#define REG_MBSSID_BCN_SPACE3_8197F 0x05BC\n#define REG_ACMHWCTRL_8197F 0x05C0\n#define REG_ACMRSTCTRL_8197F 0x05C1\n#define REG_ACMAVG_8197F 0x05C2\n#define REG_VO_ADMTIME_8197F 0x05C4\n#define REG_VI_ADMTIME_8197F 0x05C6\n#define REG_BE_ADMTIME_8197F 0x05C8\n#define REG_EDCA_RANDOM_GEN_8197F 0x05CC\n#define REG_TXCMD_NOA_SEL_8197F 0x05CF\n#define REG_NOA_PARAM_8197F 0x05E0\n#define REG_P2P_RST_8197F 0x05F0\n#define REG_SCHEDULER_RST_8197F 0x05F1\n#define REG_SCH_TXCMD_8197F 0x05F8\n#define REG_PAGE5_DUMMY_8197F 0x05FC\n#define REG_CPUMGQ_TX_TIMER_8197F 0x1500\n#define REG_PS_TIMER_A_8197F 0x1504\n#define REG_PS_TIMER_B_8197F 0x1508\n#define REG_PS_TIMER_C_8197F 0x150C\n#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8197F 0x1510\n#define REG_CPUMGQ_TX_TIMER_EARLY_8197F 0x1514\n#define REG_PS_TIMER_A_EARLY_8197F 0x1515\n#define REG_PS_TIMER_B_EARLY_8197F 0x1516\n#define REG_PS_TIMER_C_EARLY_8197F 0x1517\n#define REG_WMAC_CR_8197F 0x0600\n#define REG_WMAC_FWPKT_CR_8197F 0x0601\n#define REG_BWOPMODE_8197F 0x0603\n#define REG_TCR_8197F 0x0604\n#define REG_RCR_8197F 0x0608\n#define REG_RX_PKT_LIMIT_8197F 0x060C\n#define REG_RX_DLK_TIME_8197F 0x060D\n#define REG_RX_DRVINFO_SZ_8197F 0x060F\n#define REG_MACID_8197F 0x0610\n#define REG_BSSID_8197F 0x0618\n#define REG_MAR_8197F 0x0620\n#define REG_MBIDCAMCFG_1_8197F 0x0628\n#define REG_MBIDCAMCFG_2_8197F 0x062C\n#define REG_WMAC_TCR_TSFT_OFS_8197F 0x0630\n#define REG_UDF_THSD_8197F 0x0632\n#define REG_ZLD_NUM_8197F 0x0633\n#define REG_STMP_THSD_8197F 0x0634\n#define REG_WMAC_TXTIMEOUT_8197F 0x0635\n#define REG_MCU_TEST_2_V1_8197F 0x0636\n#define REG_USTIME_EDCA_8197F 0x0638\n#define REG_MAC_SPEC_SIFS_8197F 0x063A\n#define REG_RESP_SIFS_CCK_8197F 0x063C\n#define REG_RESP_SIFS_OFDM_8197F 0x063E\n#define REG_ACKTO_8197F 0x0640\n#define REG_CTS2TO_8197F 0x0641\n#define REG_EIFS_8197F 0x0642\n#define REG_NAV_CTRL_8197F 0x0650\n#define REG_BACAMCMD_8197F 0x0654\n#define REG_BACAMCONTENT_8197F 0x0658\n#define REG_LBDLY_8197F 0x0660\n#define REG_WMAC_BACAM_RPMEN_8197F 0x0661\n#define REG_WMAC_BITMAP_CTL_8197F 0x0663\n#define REG_RXERR_RPT_8197F 0x0664\n#define REG_WMAC_TRXPTCL_CTL_8197F 0x0668\n#define REG_CAMCMD_8197F 0x0670\n#define REG_CAMWRITE_8197F 0x0674\n#define REG_CAMREAD_8197F 0x0678\n#define REG_CAMDBG_8197F 0x067C\n#define REG_SECCFG_8197F 0x0680\n#define REG_RXFILTER_CATEGORY_1_8197F 0x0682\n#define REG_RXFILTER_ACTION_1_8197F 0x0683\n#define REG_RXFILTER_CATEGORY_2_8197F 0x0684\n#define REG_RXFILTER_ACTION_2_8197F 0x0685\n#define REG_RXFILTER_CATEGORY_3_8197F 0x0686\n#define REG_RXFILTER_ACTION_3_8197F 0x0687\n#define REG_RXFLTMAP3_8197F 0x0688\n#define REG_RXFLTMAP4_8197F 0x068A\n#define REG_RXFLTMAP5_8197F 0x068C\n#define REG_RXFLTMAP6_8197F 0x068E\n#define REG_WOW_CTRL_8197F 0x0690\n#define REG_PS_RX_INFO_8197F 0x0692\n#define REG_WMMPS_UAPSD_TID_8197F 0x0693\n#define REG_LPNAV_CTRL_8197F 0x0694\n#define REG_WKFMCAM_CMD_8197F 0x0698\n#define REG_WKFMCAM_RWD_8197F 0x069C\n#define REG_RXFLTMAP0_8197F 0x06A0\n#define REG_RXFLTMAP1_8197F 0x06A2\n#define REG_RXFLTMAP_8197F 0x06A4\n#define REG_BCN_PSR_RPT_8197F 0x06A8\n#define REG_RXPKTMON_CTRL_8197F 0x06B0\n#define REG_STATE_MON_8197F 0x06B4\n#define REG_ERROR_MON_8197F 0x06B8\n#define REG_SEARCH_MACID_8197F 0x06BC\n#define REG_BT_COEX_TABLE_8197F 0x06C0\n#define REG_RXCMD_0_8197F 0x06D0\n#define REG_RXCMD_1_8197F 0x06D4\n#define REG_WMAC_RESP_TXINFO_8197F 0x06D8\n#define REG_BBPSF_CTRL_8197F 0x06DC\n#define REG_P2P_RX_BCN_NOA_8197F 0x06E0\n#define REG_ASSOCIATED_BFMER0_INFO_8197F 0x06E4\n#define REG_ASSOCIATED_BFMER1_INFO_8197F 0x06EC\n#define REG_TX_CSI_RPT_PARAM_BW20_8197F 0x06F4\n#define REG_TX_CSI_RPT_PARAM_BW40_8197F 0x06F8\n#define REG_TX_CSI_RPT_PARAM_BW80_8197F 0x06FC\n#define REG_BCN_PSR_RPT2_8197F 0x1600\n#define REG_BCN_PSR_RPT3_8197F 0x1604\n#define REG_BCN_PSR_RPT4_8197F 0x1608\n#define REG_A1_ADDR_MASK_8197F 0x160C\n#define REG_MACID2_8197F 0x1620\n#define REG_BSSID2_8197F 0x1628\n#define REG_MACID3_8197F 0x1630\n#define REG_BSSID3_8197F 0x1638\n#define REG_MACID4_8197F 0x1640\n#define REG_BSSID4_8197F 0x1648\n#define REG_NOA_REPORT_8197F 0x1650\n#define REG_PWRBIT_SETTING_8197F 0x1660\n#define REG_WMAC_MU_BF_OPTION_8197F 0x167C\n#define REG_WMAC_PAUSE_BB_CLR_TH_8197F 0x167D\n#define REG_WMAC_MU_ARB_8197F 0x167E\n#define REG_WMAC_MU_OPTION_8197F 0x167F\n#define REG_WMAC_MU_BF_CTL_8197F 0x1680\n#define REG_WMAC_MU_BFRPT_PARA_8197F 0x1682\n#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8197F 0x1684\n#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8197F 0x1686\n#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8197F 0x1688\n#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8197F 0x168A\n#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8197F 0x168C\n#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8197F 0x168E\n#define REG_TRANSMIT_ADDRSS_0_8197F 0x16A0\n#define REG_TRANSMIT_ADDRSS_1_8197F 0x16A8\n#define REG_TRANSMIT_ADDRSS_2_8197F 0x16B0\n#define REG_TRANSMIT_ADDRSS_3_8197F 0x16B8\n#define REG_TRANSMIT_ADDRSS_4_8197F 0x16C0\n#define REG_MACID1_8197F 0x0700\n#define REG_BSSID1_8197F 0x0708\n#define REG_BCN_PSR_RPT1_8197F 0x0710\n#define REG_ASSOCIATED_BFMEE_SEL_8197F 0x0714\n#define REG_SND_PTCL_CTRL_8197F 0x0718\n#define REG_RX_CSI_RPT_INFO_8197F 0x071C\n#define REG_NS_ARP_CTRL_8197F 0x0720\n#define REG_NS_ARP_INFO_8197F 0x0724\n#define REG_BEAMFORMING_INFO_NSARP_V1_8197F 0x0728\n#define REG_BEAMFORMING_INFO_NSARP_8197F 0x072C\n#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8197F 0x0750\n#define REG_WMAC_SWAES_CFG_8197F 0x0760\n#define REG_BT_COEX_V2_8197F 0x0762\n#define REG_BT_COEX_8197F 0x0764\n#define REG_WLAN_ACT_MASK_CTRL_8197F 0x0768\n#define REG_BT_COEX_ENHANCED_INTR_CTRL_8197F 0x076E\n#define REG_BT_ACT_STATISTICS_8197F 0x0770\n#define REG_BT_STATISTICS_CONTROL_REGISTER_8197F 0x0778\n#define REG_BT_STATUS_REPORT_REGISTER_8197F 0x077C\n#define REG_BT_INTERRUPT_CONTROL_REGISTER_8197F 0x0780\n#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8197F 0x0784\n#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8197F 0x0785\n#define REG_BT_INTERRUPT_STATUS_REGISTER_8197F 0x078F\n#define REG_BT_TDMA_TIME_REGISTER_8197F 0x0790\n#define REG_BT_ACT_REGISTER_8197F 0x0794\n#define REG_OBFF_CTRL_BASIC_8197F 0x0798\n#define REG_OBFF_CTRL2_TIMER_8197F 0x079C\n#define REG_LTR_CTRL_BASIC_8197F 0x07A0\n#define REG_LTR_CTRL2_TIMER_THRESHOLD_8197F 0x07A4\n#define REG_LTR_IDLE_LATENCY_V1_8197F 0x07A8\n#define REG_LTR_ACTIVE_LATENCY_V1_8197F 0x07AC\n#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8197F 0x07B0\n#define REG_WMAC_PKTCNT_RWD_8197F 0x07B8\n#define REG_WMAC_PKTCNT_CTRL_8197F 0x07BC\n#define REG_IQ_DUMP_8197F 0x07C0\n#define REG_WMAC_FTM_CTL_8197F 0x07CC\n#define REG_IQ_DUMP_EXT_8197F 0x07CF\n#define REG_OFDM_CCK_LEN_MASK_8197F 0x07D0\n#define REG_RX_FILTER_FUNCTION_8197F 0x07DA\n#define REG_NDP_SIG_8197F 0x07E0\n#define REG_TXCMD_INFO_FOR_RSP_PKT_8197F 0x07E4\n#define REG_SEC_OPT_V2_8197F 0x07EC\n#define REG_RTS_ADDRESS_0_8197F 0x07F0\n#define REG_RTS_ADDRESS_1_8197F 0x07F8\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8197F 0x1700\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8197F 0x1704\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8197F 0x1708\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_reg_8814b.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef __INC_HALMAC_REG_8814B_H\n#define __INC_HALMAC_REG_8814B_H\n\n#define REG_SYS_ISO_CTRL_8814B 0x0000\n#define REG_SYS_FUNC_EN_8814B 0x0002\n#define REG_SYS_PW_CTRL_8814B 0x0004\n#define REG_SYS_CLK_CTRL_8814B 0x0008\n#define REG_SYS_EEPROM_CTRL_8814B 0x000A\n#define REG_EE_VPD_8814B 0x000C\n#define REG_SYS_SWR_CTRL1_8814B 0x0010\n#define REG_SYS_SWR_CTRL2_8814B 0x0014\n#define REG_SYS_SWR_CTRL3_8814B 0x0018\n#define REG_RSV_CTRL_8814B 0x001C\n#define REG_RF_CTRL_8814B 0x001F\n#define REG_AFE_LDO_CTRL_8814B 0x0020\n#define REG_AFE_CTRL1_8814B 0x0024\n#define REG_ANAPARSW_POW_MAC_8814B 0x0028\n#define REG_ANAPARLDO_POW_MAC_8814B 0x0029\n#define REG_ANAPAR_POW_MAC_8814B 0x002A\n#define REG_ANAPAR_POW_XTAL_8814B 0x002B\n#define REG_ANAPARLDO_MAC_8814B 0x002C\n#define REG_EFUSE_CTRL_8814B 0x0030\n#define REG_LDO_EFUSE_CTRL_8814B 0x0034\n#define REG_PWR_OPTION_CTRL_8814B 0x0038\n#define REG_CAL_TIMER_8814B 0x003C\n#define REG_ACLK_MON_8814B 0x003E\n#define REG_GPIO_MUXCFG_8814B 0x0040\n#define REG_GPIO_PIN_CTRL_8814B 0x0044\n#define REG_GPIO_INTM_8814B 0x0048\n#define REG_LED_CFG_8814B 0x004C\n#define REG_FSIMR_8814B 0x0050\n#define REG_FSISR_8814B 0x0054\n#define REG_HSIMR_8814B 0x0058\n#define REG_HSISR_8814B 0x005C\n#define REG_GPIO_EXT_CTRL_8814B 0x0060\n#define REG_PAD_CTRL1_8814B 0x0064\n#define REG_WL_BT_PWR_CTRL_8814B 0x0068\n#define REG_SDM_DEBUG_8814B 0x006C\n#define REG_SYS_SDIO_CTRL_8814B 0x0070\n#define REG_HCI_OPT_CTRL_8814B 0x0074\n#define REG_AFE_CTRL4_8814B 0x0078\n#define REG_LDO_SWR_CTRL_8814B 0x007C\n#define REG_MCUFW_CTRL_8814B 0x0080\n#define REG_MCU_TST_CFG_8814B 0x0084\n#define REG_HMEBOX_E0_E1_8814B 0x0088\n#define REG_HMEBOX_E2_E3_8814B 0x008C\n#define REG_WLLPS_CTRL_8814B 0x0090\n#define REG_AFE_CTRL5_8814B 0x0094\n#define REG_GPIO_DEBOUNCE_CTRL_8814B 0x0098\n#define REG_RPWM2_8814B 0x009C\n#define REG_SYSON_FSM_MON_8814B 0x00A0\n#define REG_AFE_CTRL6_8814B 0x00A4\n#define REG_PMC_DBG_CTRL1_8814B 0x00A8\n#define REG_AFE_CTRL7_8814B 0x00AC\n#define REG_HIMR0_8814B 0x00B0\n#define REG_HISR0_8814B 0x00B4\n#define REG_HIMR1_8814B 0x00B8\n#define REG_HISR1_8814B 0x00BC\n#define REG_DBG_PORT_SEL_8814B 0x00C0\n#define REG_PAD_CTRL2_8814B 0x00C4\n#define REG_PMC_DBG_CTRL2_8814B 0x00CC\n#define REG_MEM_CTRL_8814B 0x00D8\n#define REG_SYN_RFC_CTRL_8814B 0x00DC\n#define REG_USB_SIE_INTF_8814B 0x00E0\n#define REG_PCIE_MIO_INTF_8814B 0x00E4\n#define REG_PCIE_MIO_INTD_8814B 0x00E8\n#define REG_WLRF1_8814B 0x00EC\n#define REG_SYS_CFG1_8814B 0x00F0\n#define REG_SYS_STATUS1_8814B 0x00F4\n#define REG_SYS_STATUS2_8814B 0x00F8\n#define REG_SYS_CFG2_8814B 0x00FC\n#define REG_ANAPARSW_MAC_0_8814B 0x1010\n#define REG_ANAPARSW_MAC_1_8814B 0x1014\n#define REG_ANAPAR_MAC_0_8814B 0x1018\n#define REG_ANAPAR_MAC_1_8814B 0x101C\n#define REG_ANAPAR_MAC_2_8814B 0x1020\n#define REG_ANAPAR_MAC_3_8814B 0x1024\n#define REG_ANAPAR_MAC_4_8814B 0x1028\n#define REG_ANAPAR_MAC_5_8814B 0x102C\n#define REG_ANAPAR_MAC_6_8814B 0x1030\n#define REG_ANAPAR_MAC_7_8814B 0x1034\n#define REG_ANAPAR_MAC_8_8814B 0x1038\n#define REG_ANAPAR_XTAL_0_8814B 0x1040\n#define REG_ANAPAR_XTAL_1_8814B 0x1044\n#define REG_ANAPAR_XTAL_2_8814B 0x1048\n#define REG_ANAPAR_XTAL_AAC_8814B 0x104C\n#define REG_ANAPAR_XTAL_R_ONLY_8814B 0x1050\n#define REG_CPHY_LDO_8814B 0x1054\n#define REG_CPHY_BG_8814B 0x1058\n#define REG_HIMR_4_8814B 0x1060\n#define REG_HISR_4_8814B 0x1064\n#define REG_HIMR_5_8814B 0x1068\n#define REG_HISR_5_8814B 0x106C\n#define REG_SYS_CFG5_8814B 0x1070\n#define REG_HIMR_6_8814B 0x1078\n#define REG_HISR_6_8814B 0x107C\n#define REG_CPU_DMEM_CON_8814B 0x1080\n#define REG_BOOT_REASON_8814B 0x1088\n#define REG_DATA_CPU_CTL0_8814B 0x1090\n#define REG_DATA_CPU_CTL1_8814B 0x1094\n#define REG_TXDMA_STOP_HIMR_8814B 0x1098\n#define REG_TXDMA_STOP_HISR_8814B 0x109C\n#define REG_TXDMA_START_HIMR_8814B 0x10A0\n#define REG_TXDMA_START_HISR_8814B 0x10A4\n#define REG_NFCPAD_CTRL_8814B 0x10A8\n#define REG_HIMR2_8814B 0x10B0\n#define REG_HISR2_8814B 0x10B4\n#define REG_HIMR3_8814B 0x10B8\n#define REG_HISR3_8814B 0x10BC\n#define REG_SW_MDIO_8814B 0x10C0\n#define REG_HIMR_7_8814B 0x10C8\n#define REG_HISR_7_8814B 0x10CC\n#define REG_H2C_PKT_READADDR_8814B 0x10D0\n#define REG_H2C_PKT_WRITEADDR_8814B 0x10D4\n#define REG_MEM_PWR_CRTL_8814B 0x10D8\n#define REG_FW_DRV_HANDSHAKE_8814B 0x10DC\n#define REG_FW_DBG0_8814B 0x10E0\n#define REG_FW_DBG1_8814B 0x10E4\n#define REG_FW_DBG2_8814B 0x10E8\n#define REG_FW_DBG3_8814B 0x10EC\n#define REG_FW_DBG4_8814B 0x10F0\n#define REG_FW_DBG5_8814B 0x10F4\n#define REG_FW_DBG6_8814B 0x10F8\n#define REG_FW_DBG7_8814B 0x10FC\n#define REG_CR_8814B 0x0100\n#define REG_PG_SIZE_8814B 0x0104\n#define REG_PKT_BUFF_ACCESS_CTRL_8814B 0x0106\n#define REG_TSF_CLK_STATE_8814B 0x0108\n#define REG_TXDMA_PQ_MAP_8814B 0x010C\n#define REG_TRXFF_BNDY_8814B 0x0114\n#define REG_PTA_I2C_MBOX_8814B 0x0118\n#define REG_RXFF_BNDY_8814B 0x011C\n#define REG_FE1IMR_8814B 0x0120\n#define REG_FE1ISR_8814B 0x0124\n#define REG_CPWM_8814B 0x012C\n#define REG_FWIMR_8814B 0x0130\n#define REG_FWISR_8814B 0x0134\n#define REG_FTIMR_8814B 0x0138\n#define REG_FTISR_8814B 0x013C\n#define REG_PKTBUF_DBG_CTRL_8814B 0x0140\n#define REG_PKTBUF_DBG_DATA_L_8814B 0x0144\n#define REG_PKTBUF_DBG_DATA_H_8814B 0x0148\n#define REG_CPWM2_8814B 0x014C\n#define REG_TC0_CTRL_8814B 0x0150\n#define REG_TC1_CTRL_8814B 0x0154\n#define REG_TC2_CTRL_8814B 0x0158\n#define REG_TC3_CTRL_8814B 0x015C\n#define REG_TC4_CTRL_8814B 0x0160\n#define REG_TCUNIT_BASE_8814B 0x0164\n#define REG_TC5_CTRL_8814B 0x0168\n#define REG_TC6_CTRL_8814B 0x016C\n#define REG_AES_DECRPT_DATA_8814B 0x0180\n#define REG_AES_DECRPT_CFG_8814B 0x0184\n#define REG_HIOE_CTRL_8814B 0x0188\n#define REG_HIOE_CFG_FILE_8814B 0x018C\n#define REG_TMETER_8814B 0x0190\n#define REG_OSC_32K_CTRL_8814B 0x0194\n#define REG_32K_CAL_REG1_8814B 0x0198\n#define REG_C2HEVT_8814B 0x01A0\n#define REG_C2HEVT_1_8814B 0x01A4\n#define REG_C2HEVT_2_8814B 0x01A8\n#define REG_C2HEVT_3_8814B 0x01AC\n#define REG_RXDESC_BUFF_RPTR_8814B 0x01B0\n#define REG_RXDESC_BUFF_WPTR_8814B 0x01B4\n#define REG_SW_DEFINED_PAGE1_8814B 0x01B8\n#define REG_SW_DEFINED_PAGE2_8814B 0x01BC\n#define REG_MCUTST_I_8814B 0x01C0\n#define REG_MCUTST_II_8814B 0x01C4\n#define REG_FMETHR_8814B 0x01C8\n#define REG_HMETFR_8814B 0x01CC\n#define REG_HMEBOX0_8814B 0x01D0\n#define REG_HMEBOX1_8814B 0x01D4\n#define REG_HMEBOX2_8814B 0x01D8\n#define REG_HMEBOX3_8814B 0x01DC\n#define REG_RXDESC_BUFF_BNDY_8814B 0x01E0\n#define REG_BB_ACCESS_CTRL_8814B 0x01E8\n#define REG_BB_ACCESS_DATA_8814B 0x01EC\n#define REG_HMEBOX_E0_8814B 0x01F0\n#define REG_HMEBOX_E1_8814B 0x01F4\n#define REG_HMEBOX_E2_8814B 0x01F8\n#define REG_HMEBOX_E3_8814B 0x01FC\n#define REG_CR_EXT_8814B 0x1100\n#define REG_TC9_CTRL_8814B 0x1104\n#define REG_TC10_CTRL_8814B 0x1108\n#define REG_TC11_CTRL_8814B 0x110C\n#define REG_TC12_CTRL_8814B 0x1110\n#define REG_FWFF_8814B 0x1114\n#define REG_RXFF_PTR_V1_8814B 0x1118\n#define REG_RXFF_WTR_V1_8814B 0x111C\n#define REG_FE2IMR_8814B 0x1120\n#define REG_FE2ISR_8814B 0x1124\n#define REG_FE3IMR_8814B 0x1128\n#define REG_FE3ISR_8814B 0x112C\n#define REG_FE4IMR_8814B 0x1130\n#define REG_FE4ISR_8814B 0x1134\n#define REG_FT1IMR_8814B 0x1138\n#define REG_FT1ISR_8814B 0x113C\n#define REG_SPWR0_8814B 0x1140\n#define REG_SPWR1_8814B 0x1144\n#define REG_SPWR2_8814B 0x1148\n#define REG_SPWR3_8814B 0x114C\n#define REG_POWSEQ_8814B 0x1150\n#define REG_TC7_CTRL_V1_8814B 0x1158\n#define REG_TC8_CTRL_V1_8814B 0x115C\n#define REG_RX_BCN_TBTT_ITVL0_8814B 0x1160\n#define REG_RX_BCN_TBTT_ITVL1_8814B 0x1164\n#define REG_FWIMR1_8814B 0x1168\n#define REG_FWISR1_8814B 0x116C\n#define REG_FWIMR2_8814B 0x1170\n#define REG_FWISR2_8814B 0x1174\n#define REG_FWIMR3_8814B 0x1178\n#define REG_FWISR3_8814B 0x117C\n#define REG_SPEED_SENSOR_8814B 0x1180\n#define REG_SPEED_SENSOR1_8814B 0x1184\n#define REG_SPEED_SENSOR2_8814B 0x1188\n#define REG_SPEED_SENSOR3_8814B 0x118C\n#define REG_SPEED_SENSOR4_8814B 0x1190\n#define REG_SPEED_SENSOR5_8814B 0x1194\n#define REG_RXPKTBUF_1_MAX_ADDR_8814B 0x1198\n#define REG_RXFWBUF_1_MAX_ADDR_8814B 0x119C\n#define REG_IO_WRAP_ERR_FLAG_V1_8814B 0x11A0\n#define REG_RXPKTBUF_1_READ_8814B 0x11A4\n#define REG_RXPKTBUF_1_WRITE_8814B 0x11A8\n#define REG_BUFF_DBGUG_8814B 0x11AC\n#define REG_RFE_CTRL_PAD_E2_8814B 0x11B0\n#define REG_RFE_CTRL_PAD_SR_8814B 0x11B4\n#define REG_H2C_PRIORITY_SEL_8814B 0x11C0\n#define REG_COUNTER_CTRL_8814B 0x11C4\n#define REG_COUNTER_THRESHOLD_8814B 0x11C8\n#define REG_COUNTER_SET_8814B 0x11CC\n#define REG_COUNTER_OVERFLOW_8814B 0x11D0\n#define REG_TXDMA_LEN_THRESHOLD_8814B 0x11D4\n#define REG_RXDMA_LEN_THRESHOLD_8814B 0x11D8\n#define REG_PCIE_EXEC_TIME_THRESHOLD_8814B 0x11DC\n#define REG_FT2IMR_8814B 0x11E0\n#define REG_FT2ISR_8814B 0x11E4\n#define REG_MSG2_8814B 0x11F0\n#define REG_MSG3_8814B 0x11F4\n#define REG_MSG4_8814B 0x11F8\n#define REG_MSG5_8814B 0x11FC\n#define REG_BIST_RSTN0_8814B 0x2100\n#define REG_BIST_RSTN2_8814B 0x2108\n#define REG_BIST_MODE_NRML0_8814B 0x2110\n#define REG_BIST_MODE_NRML1_8814B 0x2114\n#define REG_BIST_MODE_NRML2_8814B 0x2118\n#define REG_BIST_MODE_NRML3_8814B 0x211C\n#define REG_BIST_DONE_NRML_MAC_8814B 0x2150\n#define REG_BIST_DONE_NRML1_8814B 0x2158\n#define REG_BIST_DONE_DRF_MAC_8814B 0x2160\n#define REG_BIST_DONE_DRF_8814B 0x2164\n#define REG_BIST_DONE_DRF1_8814B 0x2168\n#define REG_BIST_FAIL_NRML_MAC_8814B 0x2170\n#define REG_BIST_FAIL_NRML_8814B 0x2174\n#define REG_BIST_FAIL_NRML1_8814B 0x2178\n#define REG_BIST_FAIL_NRML_MAC_V1_8814B 0x2180\n#define REG_BIST_FAIL_NRML_V1_8814B 0x2184\n#define REG_BIST_FAIL_NRML1_V1_8814B 0x2188\n#define REG_BIST_MISR_DATAOUT_8814B 0x2190\n#define REG_BIST_MISR_DATAOUT1_8814B 0x2194\n#define REG_BIST_MISR_DATAOUT_CPU_8814B 0x2198\n#define REG_BIST_MISR_DATAOUT_CPU1_8814B 0x219C\n#define REG_BIST_MISR_DATAOUT_CPU2_8814B 0x21A0\n#define REG_BIST_MISR_DATOUT_CPU3_8814B 0x21A4\n#define REG_BCN_CTRL_0_8814B 0x0200\n#define REG_BCN_CTRL_1_8814B 0x0204\n#define REG_AUTO_LLT_V1_8814B 0x0208\n#define REG_TXDMA_OFFSET_CHK_8814B 0x020C\n#define REG_TXDMA_STATUS_8814B 0x0210\n#define REG_TX_DMA_DBG_8814B 0x0214\n#define REG_DMA_RQPN_INFO_PUB_8814B 0x0218\n#define REG_RQPN_CTRL_2_V1_8814B 0x021C\n#define REG_BCN_CTRL_2_8814B 0x0220\n#define REG_TXPKTNUM_0_8814B 0x0230\n#define REG_TXPKTNUM_1_8814B 0x0234\n#define REG_TXPKTNUM_2_8814B 0x0238\n#define REG_TXPKTNUM_3_8814B 0x023C\n#define REG_TX_AGG_ALIGN_8814B 0x0240\n#define REG_H2C_HEAD_8814B 0x0244\n#define REG_H2C_TAIL_8814B 0x0248\n#define REG_H2C_READ_ADDR_8814B 0x024C\n#define REG_H2C_WR_ADDR_8814B 0x0250\n#define REG_H2C_INFO_8814B 0x0254\n#define REG_DMA_OQT_0_8814B 0x0260\n#define REG_DMA_OQT_1_8814B 0x0264\n#define REG_RXDMA_AGG_PG_TH_8814B 0x0280\n#define REG_RXDMA_CTRL_8814B 0x0284\n#define REG_RXDMA_STATUS_8814B 0x0288\n#define REG_RXDMA_DPR_8814B 0x028C\n#define REG_RXDMA_MODE_8814B 0x0290\n#define REG_C2H_PKT_8814B 0x0294\n#define REG_FWFF_C2H_8814B 0x0298\n#define REG_FWFF_CTRL_8814B 0x029C\n#define REG_FWFF_PKT_INFO_8814B 0x02A0\n#define REG_FWFF_PKT_INFO2_8814B 0x02A4\n#define REG_RXPKTNUM_8814B 0x02B0\n#define REG_RXPKTNUM_TH_8814B 0x02B4\n#define REG_FW_UPD_RXDES_RDPTR_8814B 0x02B8\n#define REG_DDMA_CH0SA_8814B 0x1200\n#define REG_DDMA_CH0DA_8814B 0x1204\n#define REG_DDMA_CH0CTRL_8814B 0x1208\n#define REG_DDMA_CH1SA_8814B 0x1210\n#define REG_DDMA_CH1DA_8814B 0x1214\n#define REG_DDMA_CH1CTRL_8814B 0x1218\n#define REG_DDMA_CH2SA_8814B 0x1220\n#define REG_DDMA_CH2DA_8814B 0x1224\n#define REG_DDMA_CH2CTRL_8814B 0x1228\n#define REG_DDMA_CH3SA_8814B 0x1230\n#define REG_DDMA_CH3DA_8814B 0x1234\n#define REG_DDMA_CH3CTRL_8814B 0x1238\n#define REG_DDMA_CH4SA_8814B 0x1240\n#define REG_DDMA_CH4DA_8814B 0x1244\n#define REG_DDMA_CH4CTRL_8814B 0x1248\n#define REG_DDMA_CH5SA_8814B 0x1250\n#define REG_DDMA_CH5DA_8814B 0x1254\n#define REG_DDMA_CH5CTRL_8814B 0x1258\n#define REG_DDMA_INT_MSK_8814B 0x12E0\n#define REG_DDMA_CHSTATUS_8814B 0x12E8\n#define REG_DDMA_CHKSUM_8814B 0x12F0\n#define REG_DDMA_MONITOR_8814B 0x12FC\n#define REG_DMA_RQPN_INFO_0_8814B 0x2200\n#define REG_DMA_RQPN_INFO_1_8814B 0x2204\n#define REG_DMA_RQPN_INFO_2_8814B 0x2208\n#define REG_DMA_RQPN_INFO_3_8814B 0x220C\n#define REG_DMA_RQPN_INFO_4_8814B 0x2210\n#define REG_DMA_RQPN_INFO_5_8814B 0x2214\n#define REG_DMA_RQPN_INFO_6_8814B 0x2218\n#define REG_DMA_RQPN_INFO_7_8814B 0x221C\n#define REG_DMA_RQPN_INFO_8_8814B 0x2220\n#define REG_DMA_RQPN_INFO_9_8814B 0x2224\n#define REG_DMA_RQPN_INFO_10_8814B 0x2228\n#define REG_DMA_RQPN_INFO_11_8814B 0x222C\n#define REG_DMA_RQPN_INFO_12_8814B 0x2230\n#define REG_DMA_RQPN_INFO_13_8814B 0x2234\n#define REG_DMA_RQPN_INFO_14_8814B 0x2238\n#define REG_DMA_RQPN_INFO_15_8814B 0x223C\n#define REG_DMA_RQPN_INFO_16_8814B 0x2240\n#define REG_HWAMSDU_CTL1_8814B 0x2250\n#define REG_HWAMSDU_CTL2_8814B 0x2254\n#define REG_TXPAGE_INT_CTRL_0_8814B 0x3200\n#define REG_TXPAGE_INT_CTRL_1_8814B 0x3204\n#define REG_TXPAGE_INT_CTRL_2_8814B 0x3208\n#define REG_TXPAGE_INT_CTRL_3_8814B 0x320C\n#define REG_TXPAGE_INT_CTRL_4_8814B 0x3210\n#define REG_TXPAGE_INT_CTRL_5_8814B 0x3214\n#define REG_TXPAGE_INT_CTRL_6_8814B 0x3218\n#define REG_TXPAGE_INT_CTRL_7_8814B 0x321C\n#define REG_TXPAGE_INT_CTRL_8_8814B 0x3220\n#define REG_TXPAGE_INT_CTRL_9_8814B 0x3224\n#define REG_TXPAGE_INT_CTRL_10_8814B 0x3228\n#define REG_TXPAGE_INT_CTRL_11_8814B 0x322C\n#define REG_TXPAGE_INT_CTRL_12_8814B 0x3230\n#define REG_TXPAGE_INT_CTRL_13_8814B 0x3234\n#define REG_TXPAGE_INT_CTRL_14_8814B 0x3238\n#define REG_TXPAGE_INT_CTRL_15_8814B 0x323C\n#define REG_TXPAGE_INT_CTRL_16_8814B 0x3240\n#define REG_PCIE_CTRL_8814B 0x0300\n#define REG_ACH_CTRL_8814B 0x0304\n#define REG_HIQ_CTRL_8814B 0x0308\n#define REG_INT_MIG_V1_8814B 0x030C\n#define REG_P0MGQ_TXBD_DESA_L_8814B 0x0310\n#define REG_P0MGQ_TXBD_DESA_H_8814B 0x0314\n#define REG_ACH0_TXBD_DESA_L_8814B 0x0318\n#define REG_ACH0_TXBD_DESA_H_8814B 0x031C\n#define REG_ACH1_TXBD_DESA_L_8814B 0x0320\n#define REG_ACH1_TXBD_DESA_H_8814B 0x0324\n#define REG_ACH2_TXBD_DESA_L_8814B 0x0328\n#define REG_ACH2_TXBD_DESA_H_8814B 0x032C\n#define REG_ACH3_TXBD_DESA_L_8814B 0x0330\n#define REG_ACH3_TXBD_DESA_H_8814B 0x0334\n#define REG_P0RXQ_RXBD_DESA_L_8814B 0x0338\n#define REG_P0RXQ_RXBD_DESA_H_8814B 0x033C\n#define REG_P0BCNQ_TXBD_DESA_L_8814B 0x0340\n#define REG_P0BCNQ_TXBD_DESA_H_8814B 0x0344\n#define REG_FWCMDQ_TXBD_DESA_L_8814B 0x0348\n#define REG_FWCMDQ_TXBD_DESA_H_8814B 0x034C\n#define REG_PCIE_HRPWM1_HCPWM1_DCPU_8814B 0x0354\n#define REG_P0_MPRT_BCNQ_TXBD_DESA_L_8814B 0x0358\n#define REG_P0_MPRT_BCNQ_TXBD_DESA_H_8814B 0x035C\n#define REG_P0_MPRT_BCNQ_TXRXBD_NUM_8814B 0x036C\n#define REG_BD_RWPTR_CLR2_8814B 0x0370\n#define REG_BD_RWPTR_CLR3_8814B 0x0374\n#define REG_P0MGQ_RXQ_TXRXBD_NUM_8814B 0x0378\n#define REG_CHNL_DMA_CFG_8814B 0x037C\n#define REG_FWCMDQ_TXBD_NUM_8814B 0x0380\n#define REG_ACH0_ACH1_TXBD_NUM_8814B 0x0384\n#define REG_ACH2_ACH3_TXBD_NUM_8814B 0x0388\n#define REG_P0HI0Q_HI1Q_TXBD_NUM_8814B 0x038C\n#define REG_P0HI2Q_HI3Q_TXBD_NUM_8814B 0x0390\n#define REG_P0HI4Q_HI5Q_TXBD_NUM_8814B 0x0394\n#define REG_P0HI6Q_HI7Q_TXBD_NUM_8814B 0x0398\n#define REG_BD_RWPTR_CLR1_8814B 0x039C\n#define REG_TSFTIMER_HCI_8814B 0x039C\n#define REG_ACH0_TXBD_IDX_8814B 0x03A0\n#define REG_ACH1_TXBD_IDX_8814B 0x03A4\n#define REG_ACH2_TXBD_IDX_8814B 0x03A8\n#define REG_ACH3_TXBD_IDX_8814B 0x03AC\n#define REG_P0MGQ_TXBD_IDX_8814B 0x03B0\n#define REG_P0RXQ_RXBD_IDX_8814B 0x03B4\n#define REG_P0HI0Q_TXBD_IDX_8814B 0x03B8\n#define REG_P0HI1Q_TXBD_IDX_8814B 0x03BC\n#define REG_P0HI2Q_TXBD_IDX_8814B 0x03C0\n#define REG_P0HI3Q_TXBD_IDX_8814B 0x03C4\n#define REG_P0HI4Q_TXBD_IDX_8814B 0x03C8\n#define REG_P0HI5Q_TXBD_IDX_8814B 0x03CC\n#define REG_P0HI6Q_TXBD_IDX_8814B 0x03D0\n#define REG_P0HI7Q_TXBD_IDX_8814B 0x03D4\n#define REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1_8814B 0x03D8\n#define REG_PCIE_HRPWM2_HCPWM2_V1_8814B 0x03DC\n#define REG_PCIE_H2C_MSG_V1_8814B 0x03E0\n#define REG_PCIE_C2H_MSG_V1_8814B 0x03E4\n#define REG_DBI_WDATA_V1_8814B 0x03E8\n#define REG_DBI_RDATA_V1_8814B 0x03EC\n#define REG_DBI_FLAG_V1_8814B 0x03F0\n#define REG_MDIO_V1_8814B 0x03F4\n#define REG_PCIE_MIX_CFG_8814B 0x03F8\n#define REG_HCI_MIX_CFG_8814B 0x03FC\n#define REG_STC_INT_CS_8814B 0x1300\n#define REG_ST_INT_CFG_8814B 0x1304\n#define REG_ACH4_ACH5_TXBD_NUM_8814B 0x130C\n#define REG_FWCMDQ_TXBD_IDX_8814B 0x1318\n#define REG_P0HI8Q_TXBD_IDX_8814B 0x131C\n#define REG_H2CQ_TXBD_DESA_L_8814B 0x1320\n#define REG_H2CQ_TXBD_DESA_H_8814B 0x1324\n#define REG_H2CQ_TXBD_NUM_8814B 0x1328\n#define REG_H2CQ_TXBD_IDX_8814B 0x132C\n#define REG_H2CQ_CSR_8814B 0x1330\n#define REG_P0HI9Q_TXBD_IDX_8814B 0x1334\n#define REG_P0HI10Q_TXBD_IDX_8814B 0x1338\n#define REG_P0HI11Q_TXBD_IDX_8814B 0x133C\n#define REG_P0HI12Q_TXBD_IDX_8814B 0x1340\n#define REG_P0HI13Q_TXBD_IDX_8814B 0x1344\n#define REG_P0HI14Q_TXBD_IDX_8814B 0x1348\n#define REG_P0HI15Q_TXBD_IDX_8814B 0x134C\n#define REG_CHANGE_PCIE_SPEED_8814B 0x1350\n#define REG_DEBUG_STATE1_8814B 0x1354\n#define REG_DEBUG_STATE2_8814B 0x1358\n#define REG_DEBUG_STATE3_8814B 0x135C\n#define REG_ACH5_TXBD_DESA_L_8814B 0x1360\n#define REG_ACH5_TXBD_DESA_H_8814B 0x1364\n#define REG_ACH6_TXBD_DESA_L_8814B 0x1368\n#define REG_ACH6_TXBD_DESA_H_8814B 0x136C\n#define REG_ACH7_TXBD_DESA_L_8814B 0x1370\n#define REG_ACH7_TXBD_DESA_H_8814B 0x1374\n#define REG_ACH8_TXBD_DESA_L_8814B 0x1378\n#define REG_ACH8_TXBD_DESA_H_8814B 0x137C\n#define REG_ACH9_TXBD_DESA_L_8814B 0x1380\n#define REG_ACH9_TXBD_DESA_H_8814B 0x1384\n#define REG_ACH10_TXBD_DESA_L_8814B 0x1388\n#define REG_ACH10_TXBD_DESA_H_8814B 0x138C\n#define REG_ACH11_TXBD_DESA_L_8814B 0x1390\n#define REG_ACH11_TXBD_DESA_H_8814B 0x1394\n#define REG_ACH12_TXBD_DESA_L_8814B 0x1398\n#define REG_ACH12_TXBD_DESA_H_8814B 0x139C\n#define REG_ACH13_TXBD_DESA_L_8814B 0x13A0\n#define REG_ACH13_TXBD_DESA_H_8814B 0x13A4\n#define REG_HI0Q_TXBD_DESA_L_8814B 0x13A8\n#define REG_HI0Q_TXBD_DESA_H_8814B 0x13AC\n#define REG_HI1Q_TXBD_DESA_L_8814B 0x13B0\n#define REG_HI1Q_TXBD_DESA_H_8814B 0x13B4\n#define REG_HI2Q_TXBD_DESA_L_8814B 0x13B8\n#define REG_HI2Q_TXBD_DESA_H_8814B 0x13BC\n#define REG_HI3Q_TXBD_DESA_L_8814B 0x13C0\n#define REG_HI3Q_TXBD_DESA_H_8814B 0x13C4\n#define REG_HI4Q_TXBD_DESA_L_8814B 0x13C8\n#define REG_HI4Q_TXBD_DESA_H_8814B 0x13CC\n#define REG_HI5Q_TXBD_DESA_L_8814B 0x13D0\n#define REG_HI5Q_TXBD_DESA_H_8814B 0x13D4\n#define REG_HI6Q_TXBD_DESA_L_8814B 0x13D8\n#define REG_HI6Q_TXBD_DESA_H_8814B 0x13DC\n#define REG_HI7Q_TXBD_DESA_L_8814B 0x13E0\n#define REG_HI7Q_TXBD_DESA_H_8814B 0x13E4\n#define REG_ACH8_ACH9_TXBD_NUM_8814B 0x13E8\n#define REG_ACH10_ACH11_TXBD_NUM_8814B 0x13EC\n#define REG_ACH12_ACH13_TXBD_NUM_8814B 0x13F0\n#define REG_OLD_DEHANG_8814B 0x13F4\n#define REG_ACH4_TXBD_DESA_L_8814B 0x13F8\n#define REG_ACH4_TXBD_DESA_H_8814B 0x13FC\n#define REG_HI8Q_TXBD_DESA_L_8814B 0x2300\n#define REG_HI8Q_TXBD_DESA_H_8814B 0x2304\n#define REG_HI9Q_TXBD_DESA_L_8814B 0x2308\n#define REG_HI9Q_TXBD_DESA_H_8814B 0x230C\n#define REG_HI10Q_TXBD_DESA_L_8814B 0x2310\n#define REG_HI10Q_TXBD_DESA_H_8814B 0x2314\n#define REG_HI11Q_TXBD_DESA_L_8814B 0x2318\n#define REG_HI11Q_TXBD_DESA_H_8814B 0x231C\n#define REG_HI12Q_TXBD_DESA_L_8814B 0x2320\n#define REG_HI12Q_TXBD_DESA_H_8814B 0x2324\n#define REG_HI13Q_TXBD_DESA_L_8814B 0x2328\n#define REG_HI13Q_TXBD_DESA_H_8814B 0x232C\n#define REG_HI14Q_TXBD_DESA_L_8814B 0x2330\n#define REG_HI14Q_TXBD_DESA_H_8814B 0x2334\n#define REG_HI15Q_TXBD_DESA_L_8814B 0x2338\n#define REG_HI15Q_TXBD_DESA_H_8814B 0x233C\n#define REG_HI16Q_TXBD_DESA_L_8814B 0x2340\n#define REG_HI16Q_TXBD_DESA_H_8814B 0x2344\n#define REG_HI17Q_TXBD_DESA_L_8814B 0x2348\n#define REG_HI17Q_TXBD_DESA_H_8814B 0x234C\n#define REG_HI18Q_TXBD_DESA_L_8814B 0x2350\n#define REG_HI18Q_TXBD_DESA_H_8814B 0x2354\n#define REG_HI19Q_TXBD_DESA_L_8814B 0x2358\n#define REG_HI19Q_TXBD_DESA_H_8814B 0x235C\n#define REG_BD_RWPTR_CLR6_8814B 0x2364\n#define REG_P0HI16Q_TXBD_IDX_8814B 0x2370\n#define REG_P0HI17Q_TXBD_IDX_8814B 0x2374\n#define REG_P0HI18Q_TXBD_IDX_8814B 0x2378\n#define REG_P0HI19Q_TXBD_IDX_8814B 0x237C\n#define REG_P0HI16Q_HI17Q_TXBD_NUM_8814B 0x2380\n#define REG_P0HI18Q_HI19Q_TXBD_NUM_8814B 0x2384\n#define REG_PCIE_HISR0_8814B 0x23B4\n#define REG_PCIE_HISR1_8814B 0x23BC\n#define REG_P0HI8Q_HI9Q_TXBD_NUM_8814B 0x23C0\n#define REG_P0HI10Q_HI11Q_TXBD_NUM_8814B 0x23C4\n#define REG_P0HI12Q_HI13Q_TXBD_NUM_8814B 0x23C8\n#define REG_P0HI14Q_HI15Q_TXBD_NUM_8814B 0x23CC\n#define REG_ACH6_ACH7_TXBD_NUM_8814B 0x23F0\n#define REG_ACH4_TXBD_IDX_8814B 0x3340\n#define REG_ACH5_TXBD_IDX_8814B 0x3344\n#define REG_ACH6_TXBD_IDX_8814B 0x3348\n#define REG_ACH7_TXBD_IDX_8814B 0x334C\n#define REG_ACH8_TXBD_IDX_8814B 0x3350\n#define REG_ACH9_TXBD_IDX_8814B 0x3354\n#define REG_ACH10_TXBD_IDX_8814B 0x3358\n#define REG_ACH11_TXBD_IDX_8814B 0x335C\n#define REG_ACH12_TXBD_IDX_8814B 0x3360\n#define REG_ACH13_TXBD_IDX_8814B 0x3364\n#define REG_AC_CHANNEL0_WEIGHT_8814B 0x3368\n#define REG_AC_CHANNEL1_WEIGHT_8814B 0x3369\n#define REG_AC_CHANNEL2_WEIGHT_8814B 0x336A\n#define REG_AC_CHANNEL3_WEIGHT_8814B 0x336B\n#define REG_AC_CHANNEL4_WEIGHT_8814B 0x336C\n#define REG_AC_CHANNEL5_WEIGHT_8814B 0x336D\n#define REG_AC_CHANNEL6_WEIGHT_8814B 0x336E\n#define REG_AC_CHANNEL7_WEIGHT_8814B 0x336F\n#define REG_AC_CHANNEL8_WEIGHT_8814B 0x3370\n#define REG_AC_CHANNEL9_WEIGHT_8814B 0x3371\n#define REG_AC_CHANNEL10_WEIGHT_8814B 0x3372\n#define REG_AC_CHANNEL11_WEIGHT_8814B 0x3373\n#define REG_AC_CHANNEL12_WEIGHT_8814B 0x3374\n#define REG_AC_CHANNEL13_WEIGHT_8814B 0x3375\n#define REG_PCIE_HISR2_8814B 0x33B4\n#define REG_PCIE_HISR3_8814B 0x33BC\n#define REG_QUEUELIST_INFO0_8814B 0x0400\n#define REG_QUEUELIST_INFO1_8814B 0x0404\n#define REG_QUEUELIST_INFO2_8814B 0x0408\n#define REG_QUEUELIST_INFO3_8814B 0x040C\n#define REG_QUEUELIST_INFO_EMPTY_8814B 0x0410\n#define REG_QUEUELIST_ACQ_EN_8814B 0x0414\n#define REG_BCNQ_BDNY_V2_8814B 0x0418\n#define REG_CPU_MGQ_INFO_8814B 0x041C\n#define REG_FWHW_TXQ_CTRL_8814B 0x0420\n#define REG_DATAFB_SEL_8814B 0x0423\n#define REG_TXBDNY_8814B 0x0424\n#define REG_LIFETIME_EN_8814B 0x0426\n#define REG_SPEC_SIFS_8814B 0x0428\n#define REG_RETRY_LIMIT_8814B 0x042A\n#define REG_TXBF_CTRL_8814B 0x042C\n#define REG_DARFRC_8814B 0x0430\n#define REG_DARFRCH_8814B 0x0434\n#define REG_RARFRC_8814B 0x0438\n#define REG_RARFRCH_8814B 0x043C\n#define REG_RRSR_8814B 0x0440\n#define REG_ARFR0_8814B 0x0444\n#define REG_ARFRH0_8814B 0x0448\n#define REG_REG_ARFR_WT0_8814B 0x044C\n#define REG_REG_ARFR_WT1_8814B 0x0450\n#define REG_CCK_CHECK_8814B 0x0454\n#define REG_AMPDU_MAX_TIME_V1_8814B 0x0455\n#define REG_TAB_SEL_8814B 0x0456\n#define REG_BCN_INVALID_CTRL_8814B 0x0457\n#define REG_AMPDU_MAX_LENGTH_HT_8814B 0x0458\n#define REG_NDPA_RATE_8814B 0x045D\n#define REG_TX_HANG_CTRL_8814B 0x045E\n#define REG_NDPA_OPT_CTRL_8814B 0x045F\n#define REG_AMPDU_MAX_LENGTH_VHT_8814B 0x0460\n#define REG_RD_RESP_PKT_TH_8814B 0x0463\n#define REG_NEW_EDCA_CTRL_V1_8814B 0x0464\n#define REG_ACQ_STOP_V2_8814B 0x0468\n#define REG_WMAC_LBK_BUF_HD_V1_8814B 0x0478\n#define REG_MGQ_BDNY_V1_8814B 0x047A\n#define REG_TXRPT_CTRL_8814B 0x047C\n#define REG_INIRTS_RATE_SEL_8814B 0x0480\n#define REG_BASIC_CFEND_RATE_8814B 0x0481\n#define REG_STBC_CFEND_RATE_8814B 0x0482\n#define REG_DATA_SC_8814B 0x0483\n#define REG_MOREDATA_V1_8814B 0x0484\n#define REG_DATA_SC1_8814B 0x0487\n#define REG_TXRPT_START_OFFSET_8814B 0x04AC\n#define REG_POWER_STAGE1_8814B 0x04B4\n#define REG_POWER_STAGE2_8814B 0x04B8\n#define REG_SW_AMPDU_BURST_MODE_CTRL_8814B 0x04BC\n#define REG_PKT_LIFE_TIME_8814B 0x04C0\n#define REG_STBC_SETTING_8814B 0x04C4\n#define REG_STBC_SETTING2_8814B 0x04C5\n#define REG_QUEUE_CTRL_8814B 0x04C6\n#define REG_SINGLE_AMPDU_CTRL_8814B 0x04C7\n#define REG_PROT_MODE_CTRL_8814B 0x04C8\n#define REG_BAR_MODE_CTRL_8814B 0x04CC\n#define REG_RA_TRY_RATE_AGG_LMT_8814B 0x04CF\n#define REG_MACID_SLEEP_CTRL_8814B 0x04D0\n#define REG_MACID_SLEEP_INFO_8814B 0x04D4\n#define REG_HW_SEQ0_8814B 0x04D8\n#define REG_HW_SEQ1_8814B 0x04DA\n#define REG_HW_SEQ2_8814B 0x04DC\n#define REG_HW_SEQ3_8814B 0x04DE\n#define REG_PTCL_ERR_STATUS_V1_8814B 0x04E2\n#define REG_NULL_PKT_STATUS_V2_8814B 0x04E4\n#define REG_PRECNT_CTRL_8814B 0x04E5\n#define REG_NULL_PKT_STATUS_EXTEND_V1_8814B 0x04E7\n#define REG_PTCL_DBG_V1_8814B 0x04EC\n#define REG_BT_POLLUTE_PKTCNT_8814B 0x04F0\n#define REG_CPUMGQ_TIMER_CTRL2_8814B 0x04F4\n#define REG_PTCL_DBG_OUT_8814B 0x04F8\n#define REG_DUMMY_PAGE4_V1_8814B 0x04FC\n#define REG_DUMMY_PAGE4_1_8814B 0x04FE\n#define REG_MU_OFFSET_8814B 0x1400\n#define REG_BF0_TIME_SETTING_8814B 0x1428\n#define REG_BF1_TIME_SETTING_8814B 0x142C\n#define REG_BF_TIMEOUT_EN_8814B 0x1430\n#define REG_MACID_RELEASE_INFO_8814B 0x1434\n#define REG_MACID_RELEASE_SUCCESS_INFO_8814B 0x1438\n#define REG_MACID_RELEASE_CTRL_8814B 0x143C\n#define REG_FAST_EDCA_VOVI_SETTING_8814B 0x1448\n#define REG_FAST_EDCA_BEBK_SETTING_8814B 0x144C\n#define REG_MACID_DROP_INFO_8814B 0x1450\n#define REG_MACID_DROP_CTRL_8814B 0x1454\n#define REG_MGQ_FIFO_WRITE_POINTER_8814B 0x1470\n#define REG_MGQ_FIFO_READ_POINTER_8814B 0x1472\n#define REG_MGQ_FIFO_ENABLE_8814B 0x1472\n#define REG_MGQ_FIFO_RELEASE_INT_MASK_8814B 0x1474\n#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8814B 0x1476\n#define REG_MGQ_FIFO_VALID_MAP_8814B 0x1478\n#define REG_MGQ_FIFO_LIFETIME_8814B 0x147A\n#define REG_PKT_TRANS_8814B 0x1480\n#define REG_SHCUT_LLC_ETH_TYPE0_8814B 0x1484\n#define REG_SHCUT_LLC_ETH_TYPE1_8814B 0x1488\n#define REG_SHCUT_LLC_OUI0_8814B 0x148C\n#define REG_SHCUT_LLC_OUI1_8814B 0x1490\n#define REG_SHCUT_LLC_OUI2_8814B 0x1494\n#define REG_FWCMDQ_CTRL_8814B 0x14A0\n#define REG_FWCMDQ_PAGE_8814B 0x14A4\n#define REG_FWCMDQ_INFO_8814B 0x14A8\n#define REG_FWCMDQ_HOLD_PKTNUM_8814B 0x14AC\n#define REG_MU_TX_CTRL_8814B 0x14C0\n#define REG_MU_STA_GID_VLD_8814B 0x14C4\n#define REG_MU_STA_USER_POS_INFO_8814B 0x14C8\n#define REG_MU_STA_USER_POS_INFO_H_8814B 0x14CC\n#define REG_CHNL_INFO_CTRL_8814B 0x14D0\n#define REG_CHNL_IDLE_TIME_8814B 0x14D4\n#define REG_CHNL_BUSY_TIME_8814B 0x14D8\n#define REG_MU_TRX_DBG_CNT_V1_8814B 0x14DC\n#define REG_SWPS_CTRL_8814B 0x14F4\n#define REG_SWPS_PKT_TH_8814B 0x14F6\n#define REG_SWPS_TIME_TH_8814B 0x14F8\n#define REG_MACID_SWPS_EN_8814B 0x14FC\n#define REG_EDCA_VO_PARAM_8814B 0x0500\n#define REG_EDCA_VI_PARAM_8814B 0x0504\n#define REG_EDCA_BE_PARAM_8814B 0x0508\n#define REG_EDCA_BK_PARAM_8814B 0x050C\n#define REG_BCNTCFG_8814B 0x0510\n#define REG_PIFS_8814B 0x0512\n#define REG_RDG_PIFS_8814B 0x0513\n#define REG_SIFS_8814B 0x0514\n#define REG_FORCE_BCN_IFS_V1_8814B 0x0518\n#define REG_AGGR_BREAK_TIME_8814B 0x051A\n#define REG_SLOT_8814B 0x051B\n#define REG_EDCA_CPUMGQ_PARAM_8814B 0x051C\n#define REG_CPUMGQ_PAUSE_8814B 0x051E\n#define REG_TX_PTCL_CTRL_8814B 0x0520\n#define REG_TXPAUSE_8814B 0x0522\n#define REG_DIS_TXREQ_CLR_8814B 0x0523\n#define REG_RD_CTRL_8814B 0x0524\n#define REG_PKT_LIFETIME_CTRL_8814B 0x0528\n#define REG_TXOP_LIMIT_CTRL_8814B 0x052C\n#define REG_CCA_TXEN_CNT_8814B 0x0534\n#define REG_MAX_INTER_COLLISION_8814B 0x0538\n#define REG_MAX_INTER_COLLISION_CNT_8814B 0x053C\n#define REG_RD_NAV_NXT_8814B 0x0544\n#define REG_NAV_PROT_LEN_8814B 0x0546\n#define REG_FTM_PTT_8814B 0x0548\n#define REG_FTM_TSF_8814B 0x054C\n#define REG_HGQ_TIMEOUT_PERIOD_8814B 0x0575\n#define REG_TXCMD_TIMEOUT_PERIOD_8814B 0x0576\n#define REG_MISC_CTRL_8814B 0x0577\n#define REG_TXOP_MIN_8814B 0x0590\n#define REG_PRE_BKF_TIME_8814B 0x0592\n#define REG_CROSS_TXOP_CTRL_8814B 0x0593\n#define REG_ACMHWCTRL_8814B 0x05C0\n#define REG_ACMRSTCTRL_8814B 0x05C1\n#define REG_ACMAVG_8814B 0x05C2\n#define REG_VO_ADMTIME_8814B 0x05C4\n#define REG_VI_ADMTIME_8814B 0x05C6\n#define REG_BE_ADMTIME_8814B 0x05C8\n#define REG_MAC_HEADER_NAV_OFFSET_8814B 0x05CA\n#define REG_DIS_NDPA_NAV_CHECK_8814B 0x05CB\n#define REG_EDCA_RANDOM_GEN_8814B 0x05CC\n#define REG_TXCMD_SEL_8814B 0x05CF\n#define REG_MU_DBG_INFO_8814B 0x05E8\n#define REG_MU_DBG_INFO_1_8814B 0x05EC\n#define REG_SCH_DBG_SEL_8814B 0x05F0\n#define REG_SCHEDULER_RST_8814B 0x05F1\n#define REG_MU_DBG_ERR_FLAG_8814B 0x05F2\n#define REG_TX_ERR_RECOVERY_RST_8814B 0x05F3\n#define REG_SCH_DBG_VALUE_8814B 0x05F4\n#define REG_SCH_TXCMD_8814B 0x05F8\n#define REG_PAGE5_DUMMY_8814B 0x05FC\n#define REG_PORT_CTRL_SEL_8814B 0x1500\n#define REG_PORT_CTRL_CFG_8814B 0x1501\n#define REG_TBTT_PROHIBIT_CFG_8814B 0x1504\n#define REG_DRVERLYINT_CFG_8814B 0x1507\n#define REG_BCNDMATIM_CFG_8814B 0x1508\n#define REG_CTWND_CFG_8814B 0x1509\n#define REG_BCNIVLCUNT_CFG_8814B 0x150A\n#define REG_EARLY_128US_CFG_8814B 0x150B\n#define REG_TSFTR_SYNC_OFFSET_CFG_8814B 0x150C\n#define REG_TSFTR_SYNC_CTRL_CFG_8814B 0x150F\n#define REG_BCN_SPACE_CFG_8814B 0x1510\n#define REG_EARLY_INT_ADJUST_CFG_8814B 0x1512\n#define REG_SW_TBTT_TSF_INFO_8814B 0x151C\n#define REG_TSFTR_LOW_8814B 0x1520\n#define REG_TSFTR_HIGH_8814B 0x1524\n#define REG_BCN_ERR_CNT_MAC_8814B 0x1528\n#define REG_BCN_ERR_CNT_EDCCA_8814B 0x1529\n#define REG_BCN_ERR_CNT_CCA_8814B 0x152A\n#define REG_BCN_ERR_CNT_INVALID_8814B 0x152B\n#define REG_BCN_ERR_CNT_OTHERS_8814B 0x152C\n#define REG_RX_BCN_TIMER_8814B 0x152D\n#define REG_TBTT_CTN_AREA_V1_8814B 0x1530\n#define REG_BCN_MAX_ERR_V1_8814B 0x1531\n#define REG_RXTSF_OFFSET_CCK_V1_8814B 0x1532\n#define REG_RXTSF_OFFSET_OFDM_V1_8814B 0x1533\n#define REG_SUB_BCN_SPACE_8814B 0x1534\n#define REG_MBID_NUM_V1_8814B 0x1535\n#define REG_MBSSID_CTRL_V1_8814B 0x1536\n#define REG_USTIME_TSF_V1_8814B 0x1538\n#define REG_BW_CFG_8814B 0x1539\n#define REG_ATIMWND_CFG_8814B 0x153A\n#define REG_DTIM_COUNTER_CFG_8814B 0x153B\n#define REG_ATIM_DTIM_CTRL_SEL_8814B 0x153C\n#define REG_ATIMUGT_V1_8814B 0x153D\n#define REG_BCNDROPCTRL_V1_8814B 0x153E\n#define REG_DIS_ATIM_V1_8814B 0x1540\n#define REG_HIQ_NO_LMT_EN_V1_8814B 0x1544\n#define REG_P2PPS_CTRL_V1_8814B 0x1548\n#define REG_P2PPS_SPEC_STATE_V1_8814B 0x154A\n#define REG_P2PPS_STATE_V1_8814B 0x154B\n#define REG_P2PPS1_CTRL_V1_8814B 0x154C\n#define REG_P2PPS1_SPEC_STATE_V1_8814B 0x154E\n#define REG_P2PPS1_STATE_V1_8814B 0x154F\n#define REG_P2PPS2_CTRL_V1_8814B 0x1550\n#define REG_P2PPS2_SPEC_STATE_V1_8814B 0x1552\n#define REG_P2PPS2_STATE_V1_8814B 0x1553\n#define REG_P2PON_DIS_TXTIME_V1_8814B 0x1554\n#define REG_P2POFF_DIS_TXTIME_V1_8814B 0x1555\n#define REG_CHG_POWER_BCN_AREA_8814B 0x1556\n#define REG_NOA_SEL_8814B 0x1557\n#define REG_NOA_PARAM_V1_8814B 0x1558\n#define REG_NOA_PARAM_1_V1_8814B 0x155C\n#define REG_NOA_PARAM_2_V1_8814B 0x1560\n#define REG_NOA_PARAM_3_V1_8814B 0x1564\n#define REG_NOA_ON_ERLY_TIME_V1_8814B 0x1568\n#define REG_NOA_OFF_ERLY_TIME_V1_8814B 0x1569\n#define REG_P2PPS_HW_AUTO_PAUSE_CTRL_8814B 0x156C\n#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8814B 0x1570\n#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8814B 0x1574\n#define REG_RX_TBTT_SHIFT_8814B 0x1578\n#define REG_FREERUN_CNT_LOW_8814B 0x1580\n#define REG_FREERUN_CNT_HIGH_8814B 0x1584\n#define REG_CPUMGQ_TX_TIMER_V1_8814B 0x1588\n#define REG_PS_TIMER_0_8814B 0x158C\n#define REG_PS_TIMER_1_8814B 0x1590\n#define REG_PS_TIMER_2_8814B 0x1594\n#define REG_PS_TIMER_3_8814B 0x1598\n#define REG_PS_TIMER_4_8814B 0x159C\n#define REG_PS_TIMER_5_8814B 0x15A0\n#define REG_PS_TIMER_01_CTRL_8814B 0x15A4\n#define REG_PS_TIMER_23_CTRL_8814B 0x15A8\n#define REG_PS_TIMER_45_CTRL_8814B 0x15AC\n#define REG_CPUMGQ_FREERUN_TIMER_CTRL_8814B 0x15B0\n#define REG_CPUMGQ_PROHIBIT_8814B 0x15B4\n#define REG_TIMER_COMPARE_8814B 0x15C0\n#define REG_TIMER_COMPARE_VALUE_LOW_8814B 0x15C4\n#define REG_TIMER_COMPARE_VALUE_HIGH_8814B 0x15C8\n#define REG_SCHEDULER_COUNTER_8814B 0x15D0\n#define REG_WMAC_CR_8814B 0x0600\n#define REG_WMAC_FWPKT_CR_8814B 0x0601\n#define REG_FW_STS_FILTER_8814B 0x0602\n#define REG_TCR_8814B 0x0604\n#define REG_RCR_8814B 0x0608\n#define REG_RX_PKT_LIMIT_8814B 0x060C\n#define REG_RX_DLK_TIME_8814B 0x060D\n#define REG_RX_DRVINFO_SZ_8814B 0x060F\n#define REG_MACID_8814B 0x0610\n#define REG_MACID_H_8814B 0x0614\n#define REG_BSSID_8814B 0x0618\n#define REG_BSSID_H_8814B 0x061C\n#define REG_MAR_8814B 0x0620\n#define REG_MAR_H_8814B 0x0624\n#define REG_WMAC_DEBUG_SEL_8814B 0x062C\n#define REG_WMAC_TCR_TSFT_OFS_8814B 0x0630\n#define REG_UDF_THSD_8814B 0x0632\n#define REG_ZLD_NUM_8814B 0x0633\n#define REG_STMP_THSD_8814B 0x0634\n#define REG_WMAC_TXTIMEOUT_8814B 0x0635\n#define REG_MCU_TEST_2_V1_8814B 0x0636\n#define REG_USTIME_EDCA_8814B 0x0638\n#define REG_ACKTO_CCK_8814B 0x0639\n#define REG_MAC_SPEC_SIFS_8814B 0x063A\n#define REG_RESP_SIFS_CCK_8814B 0x063C\n#define REG_RESP_SIFS_OFDM_8814B 0x063E\n#define REG_ACKTO_8814B 0x0640\n#define REG_CTS2TO_8814B 0x0641\n#define REG_EIFS_8814B 0x0642\n#define REG_RPFM_MAP0_8814B 0x0644\n#define REG_RPFM_MAP1_V1_8814B 0x0646\n#define REG_RPFM_CAM_CMD_8814B 0x0648\n#define REG_RPFM_CAM_RWD_8814B 0x064C\n#define REG_NAV_CTRL_8814B 0x0650\n#define REG_BACAMCMD_8814B 0x0654\n#define REG_BACAMCONTENT_8814B 0x0658\n#define REG_BACAMCONTENT_H_8814B 0x065C\n#define REG_LBDLY_8814B 0x0660\n#define REG_WMAC_BACAM_RPMEN_8814B 0x0661\n#define REG_TX_RX_8814B 0x0662\n#define REG_WMAC_BITMAP_CTL_8814B 0x0663\n#define REG_RXERR_RPT_8814B 0x0664\n#define REG_WMAC_TRXPTCL_CTL_8814B 0x0668\n#define REG_WMAC_TRXPTCL_CTL_H_8814B 0x066C\n#define REG_CAMCMD_8814B 0x0670\n#define REG_CAMWRITE_8814B 0x0674\n#define REG_CAMREAD_8814B 0x0678\n#define REG_CAMDBG_8814B 0x067C\n#define REG_SECCFG_8814B 0x0680\n#define REG_RXFILTER_CATEGORY_1_8814B 0x0682\n#define REG_RXFILTER_ACTION_1_8814B 0x0683\n#define REG_RXFILTER_CATEGORY_2_8814B 0x0684\n#define REG_RXFILTER_ACTION_2_8814B 0x0685\n#define REG_RXFILTER_CATEGORY_3_8814B 0x0686\n#define REG_RXFILTER_ACTION_3_8814B 0x0687\n#define REG_RXFLTMAP3_8814B 0x0688\n#define REG_RXFLTMAP4_8814B 0x068A\n#define REG_RXFLTMAP5_8814B 0x068C\n#define REG_RXFLTMAP6_8814B 0x068E\n#define REG_WOW_CTRL_8814B 0x0690\n#define REG_NAN_RX_TSF_FILTER_8814B 0x0691\n#define REG_PS_RX_INFO_8814B 0x0692\n#define REG_WMMPS_UAPSD_TID_8814B 0x0693\n#define REG_LPNAV_CTRL_8814B 0x0694\n#define REG_WKFMCAM_CMD_8814B 0x0698\n#define REG_WKFMCAM_RWD_8814B 0x069C\n#define REG_RXFLTMAP0_8814B 0x06A0\n#define REG_RXFLTMAP1_8814B 0x06A2\n#define REG_RXFLTMAP2_8814B 0x06A4\n#define REG_BCN_PSR_RPT_8814B 0x06A8\n#define REG_FLC_RPC_8814B 0x06AC\n#define REG_FLC_RPCT_8814B 0x06AD\n#define REG_FLC_PTS_8814B 0x06AE\n#define REG_FLC_TRPC_8814B 0x06AF\n#define REG_RXPKTMON_CTRL_8814B 0x06B0\n#define REG_STATE_MON_8814B 0x06B4\n#define REG_ERROR_MON_8814B 0x06B8\n#define REG_SEARCH_MACID_8814B 0x06BC\n#define REG_BT_COEX_TABLE_8814B 0x06C0\n#define REG_BT_COEX_TABLE2_8814B 0x06C4\n#define REG_BT_COEX_BREAK_TABLE_8814B 0x06C8\n#define REG_BT_COEX_TABLE_H_8814B 0x06CC\n#define REG_RXCMD_0_8814B 0x06D0\n#define REG_RXCMD_1_8814B 0x06D4\n#define REG_WMAC_RESP_TXINFO_8814B 0x06D8\n#define REG_BBPSF_CTRL_8814B 0x06DC\n#define REG_P2P_RX_BCN_NOA_8814B 0x06E0\n#define REG_ASSOCIATED_BFMER0_INFO_8814B 0x06E4\n#define REG_ASSOCIATED_BFMER0_INFO_H_8814B 0x06E8\n#define REG_ASSOCIATED_BFMER1_INFO_8814B 0x06EC\n#define REG_ASSOCIATED_BFMER1_INFO_H_8814B 0x06F0\n#define REG_TX_CSI_RPT_PARAM_BW20_8814B 0x06F4\n#define REG_TX_CSI_RPT_PARAM_BW40_8814B 0x06F8\n#define REG_BCN_PSR_RPT2_8814B 0x1600\n#define REG_BCN_PSR_RPT3_8814B 0x1604\n#define REG_BCN_PSR_RPT4_8814B 0x1608\n#define REG_A1_ADDR_MASK_8814B 0x160C\n#define REG_RXPSF_CTRL_8814B 0x1610\n#define REG_RXPSF_TYPE_CTRL_8814B 0x1614\n#define REG_CAM_ACCESS_CTRL_8814B 0x1618\n#define REG_CUT_AMSDU_CTRL_8814B 0x161C\n#define REG_MACID2_8814B 0x1620\n#define REG_MACID2_H_8814B 0x1624\n#define REG_BSSID2_8814B 0x1628\n#define REG_BSSID2_H_8814B 0x162C\n#define REG_MACID3_8814B 0x1630\n#define REG_MACID3_H_8814B 0x1634\n#define REG_BSSID3_8814B 0x1638\n#define REG_BSSID3_H_8814B 0x163C\n#define REG_MACID4_8814B 0x1640\n#define REG_MACID4_H_8814B 0x1644\n#define REG_BSSID4_8814B 0x1648\n#define REG_BSSID4_H_8814B 0x164C\n#define REG_NOA_REPORT_8814B 0x1650\n#define REG_NOA_REPORT_1_8814B 0x1654\n#define REG_NOA_REPORT_2_8814B 0x1658\n#define REG_NOA_REPORT_3_8814B 0x165C\n#define REG_PWRBIT_SETTING_8814B 0x1660\n#define REG_GENERAL_OPTION_8814B 0x1664\n#define REG_FWPHYFF_RCR_8814B 0x1668\n#define REG_ADDRCAM_WRITE_CONTENT_8814B 0x166C\n#define REG_ADDRCAM_READ_CONTENT_8814B 0x1670\n#define REG_ADDRCAM_CFG_8814B 0x1674\n#define REG_CSI_RRSR_8814B 0x1678\n#define REG_MU_BF_OPTION_8814B 0x167C\n#define REG_WMAC_PAUSE_BB_CLR_TH_8814B 0x167D\n#define REG_WMAC_MULBK_BUF_8814B 0x167E\n#define REG_WMAC_MU_OPTION_8814B 0x167F\n#define REG_WMAC_MU_BF_CTL_8814B 0x1680\n#define REG_WMAC_MU_BFRPT_PARA_8814B 0x1682\n#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8814B 0x1684\n#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8814B 0x1686\n#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8814B 0x1688\n#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8814B 0x168A\n#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8814B 0x168C\n#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8814B 0x168E\n#define REG_WMAC_BB_STOP_RX_COUNTER_8814B 0x1690\n#define REG_WMAC_PLCP_MONITOR_8814B 0x1694\n#define REG_WMAC_DEBUG_PORT_8814B 0x1698\n#define REG_TRANSMIT_ADDRSS_0_8814B 0x16A0\n#define REG_TRANSMIT_ADDRSS_0_H_8814B 0x16A4\n#define REG_TRANSMIT_ADDRSS_1_8814B 0x16A8\n#define REG_TRANSMIT_ADDRSS_1_H_8814B 0x16AC\n#define REG_TRANSMIT_ADDRSS_2_8814B 0x16B0\n#define REG_TRANSMIT_ADDRSS_2_H_8814B 0x16B4\n#define REG_TRANSMIT_ADDRSS_3_8814B 0x16B8\n#define REG_TRANSMIT_ADDRSS_3_H_8814B 0x16BC\n#define REG_TRANSMIT_ADDRSS_4_8814B 0x16C0\n#define REG_TRANSMIT_ADDRSS_4_H_8814B 0x16C4\n#define REG_MACID1_8814B 0x0700\n#define REG_MACID1_1_8814B 0x0704\n#define REG_BSSID1_8814B 0x0708\n#define REG_BSSID1_1_8814B 0x070C\n#define REG_BCN_PSR_RPT1_8814B 0x0710\n#define REG_ASSOCIATED_BFMEE_SEL_8814B 0x0714\n#define REG_SND_PTCL_CTRL_8814B 0x0718\n#define REG_RX_CSI_RPT_INFO_8814B 0x071C\n#define REG_NS_ARP_CTRL_8814B 0x0720\n#define REG_NS_ARP_INFO_8814B 0x0724\n#define REG_BEAMFORMING_INFO_NSARP_V1_8814B 0x0728\n#define REG_BEAMFORMING_INFO_NSARP_8814B 0x072C\n#define REG_IPV6_8814B 0x0730\n#define REG_IPV6_1_8814B 0x0734\n#define REG_IPV6_2_8814B 0x0738\n#define REG_IPV6_3_8814B 0x073C\n#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8814B 0x0750\n#define REG_WMAC_SWAES_CFG_8814B 0x0760\n#define REG_BT_COEX_V2_8814B 0x0762\n#define REG_BT_COEX_8814B 0x0764\n#define REG_WLAN_ACT_MASK_CTRL_8814B 0x0768\n#define REG_WLAN_ACT_MASK_CTRL_1_8814B 0x076C\n#define REG_BT_COEX_ENHANCED_INTR_CTRL_8814B 0x076E\n#define REG_BT_ACT_STATISTICS_8814B 0x0770\n#define REG_BT_ACT_STATISTICS_1_8814B 0x0774\n#define REG_BT_STATISTICS_CONTROL_REGISTER_8814B 0x0778\n#define REG_BT_STATUS_REPORT_REGISTER_8814B 0x077C\n#define REG_BT_INTERRUPT_CONTROL_REGISTER_8814B 0x0780\n#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8814B 0x0784\n#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8814B 0x0785\n#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8814B 0x0788\n#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8814B 0x078C\n#define REG_BT_INTERRUPT_STATUS_REGISTER_8814B 0x078F\n#define REG_BT_TDMA_TIME_REGISTER_8814B 0x0790\n#define REG_BT_ACT_REGISTER_8814B 0x0794\n#define REG_OBFF_CTRL_BASIC_8814B 0x0798\n#define REG_OBFF_CTRL2_TIMER_8814B 0x079C\n#define REG_LTR_CTRL_BASIC_8814B 0x07A0\n#define REG_LTR_CTRL2_TIMER_THRESHOLD_8814B 0x07A4\n#define REG_LTR_IDLE_LATENCY_V1_8814B 0x07A8\n#define REG_LTR_ACTIVE_LATENCY_V1_8814B 0x07AC\n#define REG_SMART_ANT_CONDITION_8814B 0x07B0\n#define REG_SMART_ANT_CTRL_8814B 0x07B4\n#define REG_CONTROL_FRAME_REPORT_8814B 0x07B8\n#define REG_CONTROL_FRAME_CNT_CTRL_8814B 0x07BC\n#define REG_IQ_DUMP_8814B 0x07C0\n#define REG_IQ_DUMP_1_8814B 0x07C4\n#define REG_IQ_DUMP_2_8814B 0x07C8\n#define REG_WMAC_FTM_CTL_8814B 0x07CC\n#define REG_WMAC_IQ_MDPK_FUNC_8814B 0x07CE\n#define REG_WMAC_OPTION_FUNCTION_8814B 0x07D0\n#define REG_WMAC_OPTION_FUNCTION_1_8814B 0x07D4\n#define REG_WMAC_OPTION_FUNCTION_2_8814B 0x07D8\n#define REG_RX_FILTER_FUNCTION_8814B 0x07DA\n#define REG_NDP_SIG_8814B 0x07E0\n#define REG_TXCMD_INFO_FOR_RSP_PKT_8814B 0x07E4\n#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8814B 0x07E8\n#define REG_WSEC_OPTION_8814B 0x07EC\n#define REG_RTS_ADDRESS_0_8814B 0x07F0\n#define REG_RTS_ADDRESS_0_1_8814B 0x07F4\n#define REG_RTS_ADDRESS_1_8814B 0x07F8\n#define REG_RTS_ADDRESS_1_1_8814B 0x07FC\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8814B 0x1700\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8814B 0x1704\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8814B 0x1708\n#define REG_PCIE_CFG_FORCE_LINK_L_8814B 0x0709\n#define REG_PCIE_CFG_FORCE_LINK_H_8814B 0x070A\n#define REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B 0x070C\n#define REG_PCIE_CFG_CX_NFTS_8814B 0x070D\n#define REG_PCIE_CFG_DEFAULT_ENTR_LATENCY_8814B 0x070F\n#define REG_PCIE_CFG_L1_MISC_SEL_8814B 0x0711\n#define REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF_8814B 0x0718\n#define REG_PCIE_CFG_FORCE_CLKREQ_N_PAD_8814B 0x0719\n#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY_8814B 0x071A\n#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG_8814B 0x071B\n#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B 0x071C\n#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B 0x071D\n#define REG_PCIE_CFG_L1_UNIT_SEL_8814B 0x0724\n#define REG_PCIE_CFG_MIN_CLKREQ_SEL_8814B 0x0725\n#define REG_SDIO_TX_CTRL_8814B 0x10250000\n#define REG_SDIO_HIMR_8814B 0x10250014\n#define REG_SDIO_HISR_8814B 0x10250018\n#define REG_SDIO_RX_REQ_LEN_8814B 0x1025001C\n#define REG_SDIO_FREE_TXPG_SEQ_V1_8814B 0x1025001F\n#define REG_SDIO_FREE_TXPG_8814B 0x10250020\n#define REG_SDIO_FREE_TXPG2_8814B 0x10250024\n#define REG_SDIO_OQT_FREE_TXPG_V1_8814B 0x10250028\n#define REG_SDIO_HTSFR_INFO_8814B 0x10250030\n#define REG_SDIO_HCPWM1_V2_8814B 0x10250038\n#define REG_SDIO_HCPWM2_V2_8814B 0x1025003A\n#define REG_SDIO_INDIRECT_REG_CFG_8814B 0x10250040\n#define REG_SDIO_INDIRECT_REG_DATA_8814B 0x10250044\n#define REG_SDIO_H2C_8814B 0x10250060\n#define REG_SDIO_C2H_8814B 0x10250064\n#define REG_SDIO_HRPWM1_8814B 0x10250080\n#define REG_SDIO_HRPWM2_8814B 0x10250082\n#define REG_SDIO_HPS_CLKR_8814B 0x10250084\n#define REG_SDIO_BUS_CTRL_8814B 0x10250085\n#define REG_SDIO_HSUS_CTRL_8814B 0x10250086\n#define REG_SDIO_RESPONSE_TIMER_8814B 0x10250088\n#define REG_SDIO_CMD_CRC_8814B 0x1025008A\n#define REG_SDIO_HSISR_8814B 0x10250090\n#define REG_SDIO_ERR_RPT_8814B 0x102500C0\n#define REG_SDIO_CMD_ERRCNT_8814B 0x102500C2\n#define REG_SDIO_DATA_ERRCNT_8814B 0x102500C3\n#define REG_SDIO_CMD_ERR_CONTENT_8814B 0x102500C4\n#define REG_SDIO_CRC_ERR_IDX_8814B 0x102500C9\n#define REG_SDIO_DATA_CRC_8814B 0x102500CA\n#define REG_SDIO_DATA_REPLY_TIME_8814B 0x102500CB\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_reg_8821c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef __INC_HALMAC_REG_8821C_H\n#define __INC_HALMAC_REG_8821C_H\n\n#define REG_SYS_ISO_CTRL_8821C 0x0000\n#define REG_SYS_FUNC_EN_8821C 0x0002\n#define REG_SYS_PW_CTRL_8821C 0x0004\n#define REG_SYS_CLK_CTRL_8821C 0x0008\n#define REG_SYS_EEPROM_CTRL_8821C 0x000A\n#define REG_EE_VPD_8821C 0x000C\n#define REG_SYS_SWR_CTRL1_8821C 0x0010\n#define REG_SYS_SWR_CTRL2_8821C 0x0014\n#define REG_SYS_SWR_CTRL3_8821C 0x0018\n#define REG_RSV_CTRL_8821C 0x001C\n#define REG_RF_CTRL_8821C 0x001F\n#define REG_AFE_LDO_CTRL_8821C 0x0020\n#define REG_AFE_CTRL1_8821C 0x0024\n#define REG_AFE_CTRL2_8821C 0x0028\n#define REG_AFE_CTRL3_8821C 0x002C\n#define REG_EFUSE_CTRL_8821C 0x0030\n#define REG_LDO_EFUSE_CTRL_8821C 0x0034\n#define REG_PWR_OPTION_CTRL_8821C 0x0038\n#define REG_CAL_TIMER_8821C 0x003C\n#define REG_ACLK_MON_8821C 0x003E\n#define REG_GPIO_MUXCFG_8821C 0x0040\n#define REG_GPIO_PIN_CTRL_8821C 0x0044\n#define REG_GPIO_INTM_8821C 0x0048\n#define REG_LED_CFG_8821C 0x004C\n#define REG_FSIMR_8821C 0x0050\n#define REG_FSISR_8821C 0x0054\n#define REG_HSIMR_8821C 0x0058\n#define REG_HSISR_8821C 0x005C\n#define REG_GPIO_EXT_CTRL_8821C 0x0060\n#define REG_PAD_CTRL1_8821C 0x0064\n#define REG_WL_BT_PWR_CTRL_8821C 0x0068\n#define REG_SDM_DEBUG_8821C 0x006C\n#define REG_SYS_SDIO_CTRL_8821C 0x0070\n#define REG_HCI_OPT_CTRL_8821C 0x0074\n#define REG_AFE_CTRL4_8821C 0x0078\n#define REG_LDO_SWR_CTRL_8821C 0x007C\n#define REG_MCUFW_CTRL_8821C 0x0080\n#define REG_MCU_TST_CFG_8821C 0x0084\n#define REG_HMEBOX_E0_E1_8821C 0x0088\n#define REG_HMEBOX_E2_E3_8821C 0x008C\n#define REG_WLLPS_CTRL_8821C 0x0090\n#define REG_AFE_CTRL5_8821C 0x0094\n#define REG_GPIO_DEBOUNCE_CTRL_8821C 0x0098\n#define REG_RPWM2_8821C 0x009C\n#define REG_SYSON_FSM_MON_8821C 0x00A0\n#define REG_AFE_CTRL6_8821C 0x00A4\n#define REG_PMC_DBG_CTRL1_8821C 0x00A8\n#define REG_AFE_CTRL7_8821C 0x00AC\n#define REG_HIMR0_8821C 0x00B0\n#define REG_HISR0_8821C 0x00B4\n#define REG_HIMR1_8821C 0x00B8\n#define REG_HISR1_8821C 0x00BC\n#define REG_DBG_PORT_SEL_8821C 0x00C0\n#define REG_PAD_CTRL2_8821C 0x00C4\n#define REG_PMC_DBG_CTRL2_8821C 0x00CC\n#define REG_BIST_CTRL_8821C 0x00D0\n#define REG_BIST_RPT_8821C 0x00D4\n#define REG_MEM_CTRL_8821C 0x00D8\n#define REG_AFE_CTRL8_8821C 0x00DC\n#define REG_USB_SIE_INTF_8821C 0x00E0\n#define REG_PCIE_MIO_INTF_8821C 0x00E4\n#define REG_PCIE_MIO_INTD_8821C 0x00E8\n#define REG_WLRF1_8821C 0x00EC\n#define REG_SYS_CFG1_8821C 0x00F0\n#define REG_SYS_STATUS1_8821C 0x00F4\n#define REG_SYS_STATUS2_8821C 0x00F8\n#define REG_SYS_CFG2_8821C 0x00FC\n#define REG_SYS_CFG3_8821C 0x1000\n#define REG_SYS_CFG5_8821C 0x1070\n#define REG_CPU_DMEM_CON_8821C 0x1080\n#define REG_BOOT_REASON_8821C 0x1088\n#define REG_NFCPAD_CTRL_8821C 0x10A8\n#define REG_HIMR2_8821C 0x10B0\n#define REG_HISR2_8821C 0x10B4\n#define REG_HIMR3_8821C 0x10B8\n#define REG_HISR3_8821C 0x10BC\n#define REG_SW_MDIO_8821C 0x10C0\n#define REG_H2C_PKT_READADDR_8821C 0x10D0\n#define REG_H2C_PKT_WRITEADDR_8821C 0x10D4\n#define REG_MEM_PWR_CRTL_8821C 0x10D8\n#define REG_FW_DBG6_8821C 0x10F8\n#define REG_FW_DBG7_8821C 0x10FC\n#define REG_CR_8821C 0x0100\n#define REG_PG_SIZE_8821C 0x0104\n#define REG_PKT_BUFF_ACCESS_CTRL_8821C 0x0106\n#define REG_TSF_CLK_STATE_8821C 0x0108\n#define REG_TXDMA_PQ_MAP_8821C 0x010C\n#define REG_TRXFF_BNDY_8821C 0x0114\n#define REG_PTA_I2C_MBOX_8821C 0x0118\n#define REG_RXFF_BNDY_8821C 0x011C\n#define REG_FE1IMR_8821C 0x0120\n#define REG_FE1ISR_8821C 0x0124\n#define REG_CPWM_8821C 0x012C\n#define REG_FWIMR_8821C 0x0130\n#define REG_FWISR_8821C 0x0134\n#define REG_FTIMR_8821C 0x0138\n#define REG_FTISR_8821C 0x013C\n#define REG_PKTBUF_DBG_CTRL_8821C 0x0140\n#define REG_PKTBUF_DBG_DATA_L_8821C 0x0144\n#define REG_PKTBUF_DBG_DATA_H_8821C 0x0148\n#define REG_CPWM2_8821C 0x014C\n#define REG_TC0_CTRL_8821C 0x0150\n#define REG_TC1_CTRL_8821C 0x0154\n#define REG_TC2_CTRL_8821C 0x0158\n#define REG_TC3_CTRL_8821C 0x015C\n#define REG_TC4_CTRL_8821C 0x0160\n#define REG_TCUNIT_BASE_8821C 0x0164\n#define REG_TC5_CTRL_8821C 0x0168\n#define REG_TC6_CTRL_8821C 0x016C\n#define REG_MBIST_DRF_FAIL_8821C 0x0170\n#define REG_MBIST_START_PAUSE_8821C 0x0174\n#define REG_MBIST_DONE_8821C 0x0178\n#define REG_MBIST_READ_BIST_RPT_8821C 0x017C\n#define REG_AES_DECRPT_DATA_8821C 0x0180\n#define REG_AES_DECRPT_CFG_8821C 0x0184\n#define REG_TMETER_8821C 0x0190\n#define REG_OSC_32K_CTRL_8821C 0x0194\n#define REG_32K_CAL_REG1_8821C 0x0198\n#define REG_C2HEVT_8821C 0x01A0\n#define REG_C2HEVT_1_8821C 0x01A4\n#define REG_C2HEVT_2_8821C 0x01A8\n#define REG_C2HEVT_3_8821C 0x01AC\n#define REG_SW_DEFINED_PAGE1_8821C 0x01B8\n#define REG_SW_DEFINED_PAGE2_8821C 0x01BC\n#define REG_MCUTST_I_8821C 0x01C0\n#define REG_MCUTST_II_8821C 0x01C4\n#define REG_FMETHR_8821C 0x01C8\n#define REG_HMETFR_8821C 0x01CC\n#define REG_HMEBOX0_8821C 0x01D0\n#define REG_HMEBOX1_8821C 0x01D4\n#define REG_HMEBOX2_8821C 0x01D8\n#define REG_HMEBOX3_8821C 0x01DC\n#define REG_BB_ACCESS_CTRL_8821C 0x01E8\n#define REG_BB_ACCESS_DATA_8821C 0x01EC\n#define REG_HMEBOX_E0_8821C 0x01F0\n#define REG_HMEBOX_E1_8821C 0x01F4\n#define REG_HMEBOX_E2_8821C 0x01F8\n#define REG_HMEBOX_E3_8821C 0x01FC\n#define REG_CR_EXT_8821C 0x1100\n#define REG_FWFF_8821C 0x1114\n#define REG_RXFF_PTR_V1_8821C 0x1118\n#define REG_RXFF_WTR_V1_8821C 0x111C\n#define REG_FE2IMR_8821C 0x1120\n#define REG_FE2ISR_8821C 0x1124\n#define REG_FE3IMR_8821C 0x1128\n#define REG_FE3ISR_8821C 0x112C\n#define REG_FE4IMR_8821C 0x1130\n#define REG_FE4ISR_8821C 0x1134\n#define REG_FT1IMR_8821C 0x1138\n#define REG_FT1ISR_8821C 0x113C\n#define REG_SPWR0_8821C 0x1140\n#define REG_SPWR1_8821C 0x1144\n#define REG_SPWR2_8821C 0x1148\n#define REG_SPWR3_8821C 0x114C\n#define REG_POWSEQ_8821C 0x1150\n#define REG_TC7_CTRL_V1_8821C 0x1158\n#define REG_TC8_CTRL_V1_8821C 0x115C\n#define REG_RX_BCN_TBTT_ITVL0_8821C 0x1160\n#define REG_RX_BCN_TBTT_ITVL1_8821C 0x1164\n#define REG_IO_WRAP_ERR_FLAG_8821C 0x1170\n#define REG_SPEED_SENSOR_8821C 0x1180\n#define REG_SPEED_SENSOR1_8821C 0x1184\n#define REG_SPEED_SENSOR2_8821C 0x1188\n#define REG_SPEED_SENSOR3_8821C 0x118C\n#define REG_SPEED_SENSOR4_8821C 0x1190\n#define REG_SPEED_SENSOR5_8821C 0x1194\n#define REG_COUNTER_CTRL_8821C 0x11C4\n#define REG_COUNTER_THRESHOLD_8821C 0x11C8\n#define REG_COUNTER_SET_8821C 0x11CC\n#define REG_COUNTER_OVERFLOW_8821C 0x11D0\n#define REG_TXDMA_LEN_THRESHOLD_8821C 0x11D4\n#define REG_RXDMA_LEN_THRESHOLD_8821C 0x11D8\n#define REG_PCIE_EXEC_TIME_THRESHOLD_8821C 0x11DC\n#define REG_FT2IMR_8821C 0x11E0\n#define REG_FT2ISR_8821C 0x11E4\n#define REG_MSG2_8821C 0x11F0\n#define REG_MSG3_8821C 0x11F4\n#define REG_MSG4_8821C 0x11F8\n#define REG_MSG5_8821C 0x11FC\n#define REG_FIFOPAGE_CTRL_1_8821C 0x0200\n#define REG_FIFOPAGE_CTRL_2_8821C 0x0204\n#define REG_AUTO_LLT_V1_8821C 0x0208\n#define REG_TXDMA_OFFSET_CHK_8821C 0x020C\n#define REG_TXDMA_STATUS_8821C 0x0210\n#define REG_TX_DMA_DBG_8821C 0x0214\n#define REG_TQPNT1_8821C 0x0218\n#define REG_TQPNT2_8821C 0x021C\n#define REG_TQPNT3_8821C 0x0220\n#define REG_TQPNT4_8821C 0x0224\n#define REG_RQPN_CTRL_1_8821C 0x0228\n#define REG_RQPN_CTRL_2_8821C 0x022C\n#define REG_FIFOPAGE_INFO_1_8821C 0x0230\n#define REG_FIFOPAGE_INFO_2_8821C 0x0234\n#define REG_FIFOPAGE_INFO_3_8821C 0x0238\n#define REG_FIFOPAGE_INFO_4_8821C 0x023C\n#define REG_FIFOPAGE_INFO_5_8821C 0x0240\n#define REG_H2C_HEAD_8821C 0x0244\n#define REG_H2C_TAIL_8821C 0x0248\n#define REG_H2C_READ_ADDR_8821C 0x024C\n#define REG_H2C_WR_ADDR_8821C 0x0250\n#define REG_H2C_INFO_8821C 0x0254\n#define REG_RXDMA_AGG_PG_TH_8821C 0x0280\n#define REG_RXPKT_NUM_8821C 0x0284\n#define REG_RXDMA_STATUS_8821C 0x0288\n#define REG_RXDMA_DPR_8821C 0x028C\n#define REG_RXDMA_MODE_8821C 0x0290\n#define REG_C2H_PKT_8821C 0x0294\n#define REG_FWFF_C2H_8821C 0x0298\n#define REG_FWFF_CTRL_8821C 0x029C\n#define REG_FWFF_PKT_INFO_8821C 0x02A0\n#define REG_DDMA_CH0SA_8821C 0x1200\n#define REG_DDMA_CH0DA_8821C 0x1204\n#define REG_DDMA_CH0CTRL_8821C 0x1208\n#define REG_DDMA_CH1SA_8821C 0x1210\n#define REG_DDMA_CH1DA_8821C 0x1214\n#define REG_DDMA_CH1CTRL_8821C 0x1218\n#define REG_DDMA_CH2SA_8821C 0x1220\n#define REG_DDMA_CH2DA_8821C 0x1224\n#define REG_DDMA_CH2CTRL_8821C 0x1228\n#define REG_DDMA_CH3SA_8821C 0x1230\n#define REG_DDMA_CH3DA_8821C 0x1234\n#define REG_DDMA_CH3CTRL_8821C 0x1238\n#define REG_DDMA_CH4SA_8821C 0x1240\n#define REG_DDMA_CH4DA_8821C 0x1244\n#define REG_DDMA_CH4CTRL_8821C 0x1248\n#define REG_DDMA_CH5SA_8821C 0x1250\n#define REG_DDMA_CH5DA_8821C 0x1254\n#define REG_DDMA_CH5CTRL_8821C 0x1258\n#define REG_DDMA_INT_MSK_8821C 0x12E0\n#define REG_DDMA_CHSTATUS_8821C 0x12E8\n#define REG_DDMA_CHKSUM_8821C 0x12F0\n#define REG_DDMA_MONITOR_8821C 0x12FC\n#define REG_PCIE_CTRL_8821C 0x0300\n#define REG_INT_MIG_8821C 0x0304\n#define REG_BCNQ_TXBD_DESA_8821C 0x0308\n#define REG_MGQ_TXBD_DESA_8821C 0x0310\n#define REG_VOQ_TXBD_DESA_8821C 0x0318\n#define REG_VIQ_TXBD_DESA_8821C 0x0320\n#define REG_BEQ_TXBD_DESA_8821C 0x0328\n#define REG_BKQ_TXBD_DESA_8821C 0x0330\n#define REG_RXQ_RXBD_DESA_8821C 0x0338\n#define REG_HI0Q_TXBD_DESA_8821C 0x0340\n#define REG_HI1Q_TXBD_DESA_8821C 0x0348\n#define REG_HI2Q_TXBD_DESA_8821C 0x0350\n#define REG_HI3Q_TXBD_DESA_8821C 0x0358\n#define REG_HI4Q_TXBD_DESA_8821C 0x0360\n#define REG_HI5Q_TXBD_DESA_8821C 0x0368\n#define REG_HI6Q_TXBD_DESA_8821C 0x0370\n#define REG_HI7Q_TXBD_DESA_8821C 0x0378\n#define REG_MGQ_TXBD_NUM_8821C 0x0380\n#define REG_RX_RXBD_NUM_8821C 0x0382\n#define REG_VOQ_TXBD_NUM_8821C 0x0384\n#define REG_VIQ_TXBD_NUM_8821C 0x0386\n#define REG_BEQ_TXBD_NUM_8821C 0x0388\n#define REG_BKQ_TXBD_NUM_8821C 0x038A\n#define REG_HI0Q_TXBD_NUM_8821C 0x038C\n#define REG_HI1Q_TXBD_NUM_8821C 0x038E\n#define REG_HI2Q_TXBD_NUM_8821C 0x0390\n#define REG_HI3Q_TXBD_NUM_8821C 0x0392\n#define REG_HI4Q_TXBD_NUM_8821C 0x0394\n#define REG_HI5Q_TXBD_NUM_8821C 0x0396\n#define REG_HI6Q_TXBD_NUM_8821C 0x0398\n#define REG_HI7Q_TXBD_NUM_8821C 0x039A\n#define REG_TSFTIMER_HCI_8821C 0x039C\n#define REG_BD_RWPTR_CLR_8821C 0x039C\n#define REG_VOQ_TXBD_IDX_8821C 0x03A0\n#define REG_VIQ_TXBD_IDX_8821C 0x03A4\n#define REG_BEQ_TXBD_IDX_8821C 0x03A8\n#define REG_BKQ_TXBD_IDX_8821C 0x03AC\n#define REG_MGQ_TXBD_IDX_8821C 0x03B0\n#define REG_RXQ_RXBD_IDX_8821C 0x03B4\n#define REG_HI0Q_TXBD_IDX_8821C 0x03B8\n#define REG_HI1Q_TXBD_IDX_8821C 0x03BC\n#define REG_HI2Q_TXBD_IDX_8821C 0x03C0\n#define REG_HI3Q_TXBD_IDX_8821C 0x03C4\n#define REG_HI4Q_TXBD_IDX_8821C 0x03C8\n#define REG_HI5Q_TXBD_IDX_8821C 0x03CC\n#define REG_HI6Q_TXBD_IDX_8821C 0x03D0\n#define REG_HI7Q_TXBD_IDX_8821C 0x03D4\n#define REG_DBG_SEL_V1_8821C 0x03D8\n#define REG_PCIE_HRPWM1_V1_8821C 0x03D9\n#define REG_PCIE_HCPWM1_V1_8821C 0x03DA\n#define REG_PCIE_CTRL2_8821C 0x03DB\n#define REG_PCIE_HRPWM2_V1_8821C 0x03DC\n#define REG_PCIE_HCPWM2_V1_8821C 0x03DE\n#define REG_PCIE_H2C_MSG_V1_8821C 0x03E0\n#define REG_PCIE_C2H_MSG_V1_8821C 0x03E4\n#define REG_DBI_WDATA_V1_8821C 0x03E8\n#define REG_DBI_RDATA_V1_8821C 0x03EC\n#define REG_DBI_FLAG_V1_8821C 0x03F0\n#define REG_MDIO_V1_8821C 0x03F4\n#define REG_PCIE_MIX_CFG_8821C 0x03F8\n#define REG_HCI_MIX_CFG_8821C 0x03FC\n#define REG_STC_INT_CS_8821C 0x1300\n#define REG_ST_INT_CFG_8821C 0x1304\n#define REG_CMU_DLY_CTRL_8821C 0x1310\n#define REG_CMU_DLY_CFG_8821C 0x1314\n#define REG_H2CQ_TXBD_DESA_8821C 0x1320\n#define REG_H2CQ_TXBD_NUM_8821C 0x1328\n#define REG_H2CQ_TXBD_IDX_8821C 0x132C\n#define REG_H2CQ_CSR_8821C 0x1330\n#define REG_Q0_INFO_8821C 0x0400\n#define REG_Q1_INFO_8821C 0x0404\n#define REG_Q2_INFO_8821C 0x0408\n#define REG_Q3_INFO_8821C 0x040C\n#define REG_MGQ_INFO_8821C 0x0410\n#define REG_HIQ_INFO_8821C 0x0414\n#define REG_BCNQ_INFO_8821C 0x0418\n#define REG_TXPKT_EMPTY_8821C 0x041A\n#define REG_CPU_MGQ_INFO_8821C 0x041C\n#define REG_FWHW_TXQ_CTRL_8821C 0x0420\n#define REG_DATAFB_SEL_8821C 0x0423\n#define REG_BCNQ_BDNY_V1_8821C 0x0424\n#define REG_LIFETIME_EN_8821C 0x0426\n#define REG_SPEC_SIFS_8821C 0x0428\n#define REG_RETRY_LIMIT_8821C 0x042A\n#define REG_TXBF_CTRL_8821C 0x042C\n#define REG_DARFRC_8821C 0x0430\n#define REG_DARFRCH_8821C 0x0434\n#define REG_RARFRC_8821C 0x0438\n#define REG_RARFRCH_8821C 0x043C\n#define REG_RRSR_8821C 0x0440\n#define REG_ARFR0_8821C 0x0444\n#define REG_ARFRH0_8821C 0x0448\n#define REG_ARFR1_V1_8821C 0x044C\n#define REG_ARFRH1_V1_8821C 0x0450\n#define REG_CCK_CHECK_8821C 0x0454\n#define REG_AMPDU_MAX_TIME_V1_8821C 0x0455\n#define REG_BCNQ1_BDNY_V1_8821C 0x0456\n#define REG_AMPDU_MAX_LENGTH_8821C 0x0458\n#define REG_ACQ_STOP_8821C 0x045C\n#define REG_NDPA_RATE_8821C 0x045D\n#define REG_TX_HANG_CTRL_8821C 0x045E\n#define REG_NDPA_OPT_CTRL_8821C 0x045F\n#define REG_RD_RESP_PKT_TH_8821C 0x0463\n#define REG_CMDQ_INFO_8821C 0x0464\n#define REG_Q4_INFO_8821C 0x0468\n#define REG_Q5_INFO_8821C 0x046C\n#define REG_Q6_INFO_8821C 0x0470\n#define REG_Q7_INFO_8821C 0x0474\n#define REG_WMAC_LBK_BUF_HD_V1_8821C 0x0478\n#define REG_MGQ_BDNY_V1_8821C 0x047A\n#define REG_TXRPT_CTRL_8821C 0x047C\n#define REG_INIRTS_RATE_SEL_8821C 0x0480\n#define REG_BASIC_CFEND_RATE_8821C 0x0481\n#define REG_STBC_CFEND_RATE_8821C 0x0482\n#define REG_DATA_SC_8821C 0x0483\n#define REG_MACID_SLEEP3_8821C 0x0484\n#define REG_MACID_SLEEP1_8821C 0x0488\n#define REG_ARFR2_V1_8821C 0x048C\n#define REG_ARFRH2_V1_8821C 0x0490\n#define REG_ARFR3_V1_8821C 0x0494\n#define REG_ARFRH3_V1_8821C 0x0498\n#define REG_ARFR4_8821C 0x049C\n#define REG_ARFRH4_8821C 0x04A0\n#define REG_ARFR5_8821C 0x04A4\n#define REG_ARFRH5_8821C 0x04A8\n#define REG_TXRPT_START_OFFSET_8821C 0x04AC\n#define REG_POWER_STAGE1_8821C 0x04B4\n#define REG_POWER_STAGE2_8821C 0x04B8\n#define REG_SW_AMPDU_BURST_MODE_CTRL_8821C 0x04BC\n#define REG_PKT_LIFE_TIME_8821C 0x04C0\n#define REG_STBC_SETTING_8821C 0x04C4\n#define REG_STBC_SETTING2_8821C 0x04C5\n#define REG_QUEUE_CTRL_8821C 0x04C6\n#define REG_SINGLE_AMPDU_CTRL_8821C 0x04C7\n#define REG_PROT_MODE_CTRL_8821C 0x04C8\n#define REG_BAR_MODE_CTRL_8821C 0x04CC\n#define REG_RA_TRY_RATE_AGG_LMT_8821C 0x04CF\n#define REG_MACID_SLEEP2_8821C 0x04D0\n#define REG_MACID_SLEEP_8821C 0x04D4\n#define REG_HW_SEQ0_8821C 0x04D8\n#define REG_HW_SEQ1_8821C 0x04DA\n#define REG_HW_SEQ2_8821C 0x04DC\n#define REG_HW_SEQ3_8821C 0x04DE\n#define REG_NULL_PKT_STATUS_V1_8821C 0x04E0\n#define REG_PTCL_ERR_STATUS_8821C 0x04E2\n#define REG_NULL_PKT_STATUS_EXTEND_8821C 0x04E3\n#define REG_VIDEO_ENHANCEMENT_FUN_8821C 0x04E4\n#define REG_PRECNT_CTRL_8821C 0x04E5\n#define REG_BT_POLLUTE_PKT_CNT_8821C 0x04E8\n#define REG_PTCL_DBG_8821C 0x04EC\n#define REG_CPUMGQ_TIMER_CTRL2_8821C 0x04F4\n#define REG_DUMMY_PAGE4_V1_8821C 0x04FC\n#define REG_MOREDATA_8821C 0x04FE\n#define REG_Q0_Q1_INFO_8821C 0x1400\n#define REG_Q2_Q3_INFO_8821C 0x1404\n#define REG_Q4_Q5_INFO_8821C 0x1408\n#define REG_Q6_Q7_INFO_8821C 0x140C\n#define REG_MGQ_HIQ_INFO_8821C 0x1410\n#define REG_CMDQ_BCNQ_INFO_8821C 0x1414\n#define REG_USEREG_SETTING_8821C 0x1420\n#define REG_AESIV_SETTING_8821C 0x1424\n#define REG_BF0_TIME_SETTING_8821C 0x1428\n#define REG_BF1_TIME_SETTING_8821C 0x142C\n#define REG_BF_TIMEOUT_EN_8821C 0x1430\n#define REG_MACID_RELEASE0_8821C 0x1434\n#define REG_MACID_RELEASE1_8821C 0x1438\n#define REG_MACID_RELEASE2_8821C 0x143C\n#define REG_MACID_RELEASE3_8821C 0x1440\n#define REG_MACID_RELEASE_SETTING_8821C 0x1444\n#define REG_FAST_EDCA_VOVI_SETTING_8821C 0x1448\n#define REG_FAST_EDCA_BEBK_SETTING_8821C 0x144C\n#define REG_MACID_DROP0_8821C 0x1450\n#define REG_MACID_DROP1_8821C 0x1454\n#define REG_MACID_DROP2_8821C 0x1458\n#define REG_MACID_DROP3_8821C 0x145C\n#define REG_R_MACID_RELEASE_SUCCESS_0_8821C 0x1460\n#define REG_R_MACID_RELEASE_SUCCESS_1_8821C 0x1464\n#define REG_R_MACID_RELEASE_SUCCESS_2_8821C 0x1468\n#define REG_R_MACID_RELEASE_SUCCESS_3_8821C 0x146C\n#define REG_MGQ_FIFO_WRITE_POINTER_8821C 0x1470\n#define REG_MGQ_FIFO_READ_POINTER_8821C 0x1472\n#define REG_MGQ_FIFO_ENABLE_8821C 0x1472\n#define REG_MGQ_FIFO_RELEASE_INT_MASK_8821C 0x1474\n#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8821C 0x1476\n#define REG_MGQ_FIFO_VALID_MAP_8821C 0x1478\n#define REG_MGQ_FIFO_LIFETIME_8821C 0x147A\n#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0x147C\n#define REG_SHCUT_SETTING_8821C 0x1480\n#define REG_SHCUT_LLC_ETH_TYPE0_8821C 0x1484\n#define REG_SHCUT_LLC_ETH_TYPE1_8821C 0x1488\n#define REG_SHCUT_LLC_OUI0_8821C 0x148C\n#define REG_SHCUT_LLC_OUI1_8821C 0x1490\n#define REG_SHCUT_LLC_OUI2_8821C 0x1494\n#define REG_MU_TX_CTL_8821C 0x14C0\n#define REG_MU_STA_GID_VLD_8821C 0x14C4\n#define REG_MU_STA_USER_POS_INFO_8821C 0x14C8\n#define REG_MU_STA_USER_POS_INFO_H_8821C 0x14CC\n#define REG_MU_TRX_DBG_CNT_8821C 0x14D0\n#define REG_EDCA_VO_PARAM_8821C 0x0500\n#define REG_EDCA_VI_PARAM_8821C 0x0504\n#define REG_EDCA_BE_PARAM_8821C 0x0508\n#define REG_EDCA_BK_PARAM_8821C 0x050C\n#define REG_BCNTCFG_8821C 0x0510\n#define REG_PIFS_8821C 0x0512\n#define REG_RDG_PIFS_8821C 0x0513\n#define REG_SIFS_8821C 0x0514\n#define REG_TSFTR_SYN_OFFSET_8821C 0x0518\n#define REG_AGGR_BREAK_TIME_8821C 0x051A\n#define REG_SLOT_8821C 0x051B\n#define REG_NOA_ON_ERLY_TIME_8821C 0x051C\n#define REG_NOA_OFF_ERLY_TIME_8821C 0x051D\n#define REG_TX_PTCL_CTRL_8821C 0x0520\n#define REG_TXPAUSE_8821C 0x0522\n#define REG_DIS_TXREQ_CLR_8821C 0x0523\n#define REG_RD_CTRL_8821C 0x0524\n#define REG_MBSSID_CTRL_8821C 0x0526\n#define REG_P2PPS_CTRL_8821C 0x0527\n#define REG_PKT_LIFETIME_CTRL_8821C 0x0528\n#define REG_P2PPS_SPEC_STATE_8821C 0x052B\n#define REG_BAR_TX_CTRL_8821C 0x0530\n#define REG_P2PON_DIS_TXTIME_8821C 0x0531\n#define REG_TBTT_PROHIBIT_8821C 0x0540\n#define REG_P2PPS_STATE_8821C 0x0543\n#define REG_RD_NAV_NXT_8821C 0x0544\n#define REG_NAV_PROT_LEN_8821C 0x0546\n#define REG_BCN_CTRL_8821C 0x0550\n#define REG_BCN_CTRL_CLINT0_8821C 0x0551\n#define REG_MBID_NUM_8821C 0x0552\n#define REG_DUAL_TSF_RST_8821C 0x0553\n#define REG_MBSSID_BCN_SPACE_8821C 0x0554\n#define REG_DRVERLYINT_8821C 0x0558\n#define REG_BCNDMATIM_8821C 0x0559\n#define REG_ATIMWND_8821C 0x055A\n#define REG_USTIME_TSF_8821C 0x055C\n#define REG_BCN_MAX_ERR_8821C 0x055D\n#define REG_RXTSF_OFFSET_CCK_8821C 0x055E\n#define REG_RXTSF_OFFSET_OFDM_8821C 0x055F\n#define REG_TSFTR_8821C 0x0560\n#define REG_TSFTR_1_8821C 0x0564\n#define REG_FREERUN_CNT_8821C 0x0568\n#define REG_FREERUN_CNT_1_8821C 0x056C\n#define REG_ATIMWND1_V1_8821C 0x0570\n#define REG_TBTT_PROHIBIT_INFRA_8821C 0x0571\n#define REG_CTWND_8821C 0x0572\n#define REG_BCNIVLCUNT_8821C 0x0573\n#define REG_BCNDROPCTRL_8821C 0x0574\n#define REG_HGQ_TIMEOUT_PERIOD_8821C 0x0575\n#define REG_TXCMD_TIMEOUT_PERIOD_8821C 0x0576\n#define REG_MISC_CTRL_8821C 0x0577\n#define REG_BCN_CTRL_CLINT1_8821C 0x0578\n#define REG_BCN_CTRL_CLINT2_8821C 0x0579\n#define REG_BCN_CTRL_CLINT3_8821C 0x057A\n#define REG_EXTEND_CTRL_8821C 0x057B\n#define REG_P2PPS1_SPEC_STATE_8821C 0x057C\n#define REG_P2PPS1_STATE_8821C 0x057D\n#define REG_P2PPS2_SPEC_STATE_8821C 0x057E\n#define REG_P2PPS2_STATE_8821C 0x057F\n#define REG_PS_TIMER0_8821C 0x0580\n#define REG_PS_TIMER1_8821C 0x0584\n#define REG_PS_TIMER2_8821C 0x0588\n#define REG_TBTT_CTN_AREA_8821C 0x058C\n#define REG_FORCE_BCN_IFS_8821C 0x058E\n#define REG_TXOP_MIN_8821C 0x0590\n#define REG_PRE_BKF_TIME_8821C 0x0592\n#define REG_CROSS_TXOP_CTRL_8821C 0x0593\n#define REG_ATIMWND2_8821C 0x05A0\n#define REG_ATIMWND3_8821C 0x05A1\n#define REG_ATIMWND4_8821C 0x05A2\n#define REG_ATIMWND5_8821C 0x05A3\n#define REG_ATIMWND6_8821C 0x05A4\n#define REG_ATIMWND7_8821C 0x05A5\n#define REG_ATIMUGT_8821C 0x05A6\n#define REG_HIQ_NO_LMT_EN_8821C 0x05A7\n#define REG_DTIM_COUNTER_ROOT_8821C 0x05A8\n#define REG_DTIM_COUNTER_VAP1_8821C 0x05A9\n#define REG_DTIM_COUNTER_VAP2_8821C 0x05AA\n#define REG_DTIM_COUNTER_VAP3_8821C 0x05AB\n#define REG_DTIM_COUNTER_VAP4_8821C 0x05AC\n#define REG_DTIM_COUNTER_VAP5_8821C 0x05AD\n#define REG_DTIM_COUNTER_VAP6_8821C 0x05AE\n#define REG_DTIM_COUNTER_VAP7_8821C 0x05AF\n#define REG_DIS_ATIM_8821C 0x05B0\n#define REG_EARLY_128US_8821C 0x05B1\n#define REG_P2PPS1_CTRL_8821C 0x05B2\n#define REG_P2PPS2_CTRL_8821C 0x05B3\n#define REG_TIMER0_SRC_SEL_8821C 0x05B4\n#define REG_NOA_UNIT_SEL_8821C 0x05B5\n#define REG_P2POFF_DIS_TXTIME_8821C 0x05B7\n#define REG_MBSSID_BCN_SPACE2_8821C 0x05B8\n#define REG_MBSSID_BCN_SPACE3_8821C 0x05BC\n#define REG_ACMHWCTRL_8821C 0x05C0\n#define REG_ACMRSTCTRL_8821C 0x05C1\n#define REG_ACMAVG_8821C 0x05C2\n#define REG_VO_ADMTIME_8821C 0x05C4\n#define REG_VI_ADMTIME_8821C 0x05C6\n#define REG_BE_ADMTIME_8821C 0x05C8\n#define REG_EDCA_RANDOM_GEN_8821C 0x05CC\n#define REG_TXCMD_NOA_SEL_8821C 0x05CF\n#define REG_NOA_PARAM_8821C 0x05E0\n#define REG_NOA_PARAM_1_8821C 0x05E4\n#define REG_NOA_PARAM_2_8821C 0x05E8\n#define REG_NOA_PARAM_3_8821C 0x05EC\n#define REG_P2P_RST_8821C 0x05F0\n#define REG_SCHEDULER_RST_8821C 0x05F1\n#define REG_SCH_TXCMD_8821C 0x05F8\n#define REG_PAGE5_DUMMY_8821C 0x05FC\n#define REG_CPUMGQ_TX_TIMER_8821C 0x1500\n#define REG_PS_TIMER_A_8821C 0x1504\n#define REG_PS_TIMER_B_8821C 0x1508\n#define REG_PS_TIMER_C_8821C 0x150C\n#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8821C 0x1510\n#define REG_CPUMGQ_TX_TIMER_EARLY_8821C 0x1514\n#define REG_PS_TIMER_A_EARLY_8821C 0x1515\n#define REG_PS_TIMER_B_EARLY_8821C 0x1516\n#define REG_PS_TIMER_C_EARLY_8821C 0x1517\n#define REG_CPUMGQ_PARAMETER_8821C 0x1518\n#define REG_WMAC_CR_8821C 0x0600\n#define REG_WMAC_FWPKT_CR_8821C 0x0601\n#define REG_FW_STS_FILTER_8821C 0x0602\n#define REG_TCR_8821C 0x0604\n#define REG_RCR_8821C 0x0608\n#define REG_RX_PKT_LIMIT_8821C 0x060C\n#define REG_RX_DLK_TIME_8821C 0x060D\n#define REG_RX_DRVINFO_SZ_8821C 0x060F\n#define REG_MACID_8821C 0x0610\n#define REG_MACID_H_8821C 0x0614\n#define REG_BSSID_8821C 0x0618\n#define REG_BSSID_H_8821C 0x061C\n#define REG_MAR_8821C 0x0620\n#define REG_MAR_H_8821C 0x0624\n#define REG_MBIDCAMCFG_1_8821C 0x0628\n#define REG_MBIDCAMCFG_2_8821C 0x062C\n#define REG_WMAC_TCR_TSFT_OFS_8821C 0x0630\n#define REG_UDF_THSD_8821C 0x0632\n#define REG_ZLD_NUM_8821C 0x0633\n#define REG_STMP_THSD_8821C 0x0634\n#define REG_WMAC_TXTIMEOUT_8821C 0x0635\n#define REG_MCU_TEST_2_V1_8821C 0x0636\n#define REG_USTIME_EDCA_8821C 0x0638\n#define REG_ACKTO_CCK_8821C 0x0639\n#define REG_MAC_SPEC_SIFS_8821C 0x063A\n#define REG_RESP_SIFS_CCK_8821C 0x063C\n#define REG_RESP_SIFS_OFDM_8821C 0x063E\n#define REG_ACKTO_8821C 0x0640\n#define REG_CTS2TO_8821C 0x0641\n#define REG_EIFS_8821C 0x0642\n#define REG_RPFM_MAP0_8821C 0x0644\n#define REG_RPFM_MAP1_V1_8821C 0x0646\n#define REG_RPFM_CAM_CMD_8821C 0x0648\n#define REG_RPFM_CAM_RWD_8821C 0x064C\n#define REG_NAV_CTRL_8821C 0x0650\n#define REG_BACAMCMD_8821C 0x0654\n#define REG_BACAMCONTENT_8821C 0x0658\n#define REG_BACAMCONTENT_H_8821C 0x065C\n#define REG_LBDLY_8821C 0x0660\n#define REG_WMAC_BACAM_RPMEN_8821C 0x0661\n#define REG_TX_RX_8821C 0x0662\n#define REG_WMAC_BITMAP_CTL_8821C 0x0663\n#define REG_RXERR_RPT_8821C 0x0664\n#define REG_WMAC_TRXPTCL_CTL_8821C 0x0668\n#define REG_WMAC_TRXPTCL_CTL_H_8821C 0x066C\n#define REG_CAMCMD_8821C 0x0670\n#define REG_CAMWRITE_8821C 0x0674\n#define REG_CAMREAD_8821C 0x0678\n#define REG_CAMDBG_8821C 0x067C\n#define REG_SECCFG_8821C 0x0680\n#define REG_RXFILTER_CATEGORY_1_8821C 0x0682\n#define REG_RXFILTER_ACTION_1_8821C 0x0683\n#define REG_RXFILTER_CATEGORY_2_8821C 0x0684\n#define REG_RXFILTER_ACTION_2_8821C 0x0685\n#define REG_RXFILTER_CATEGORY_3_8821C 0x0686\n#define REG_RXFILTER_ACTION_3_8821C 0x0687\n#define REG_RXFLTMAP3_8821C 0x0688\n#define REG_RXFLTMAP4_8821C 0x068A\n#define REG_RXFLTMAP5_8821C 0x068C\n#define REG_RXFLTMAP6_8821C 0x068E\n#define REG_WOW_CTRL_8821C 0x0690\n#define REG_NAN_RX_TSF_FILTER_8821C 0x0691\n#define REG_PS_RX_INFO_8821C 0x0692\n#define REG_WMMPS_UAPSD_TID_8821C 0x0693\n#define REG_LPNAV_CTRL_8821C 0x0694\n#define REG_WKFMCAM_CMD_8821C 0x0698\n#define REG_WKFMCAM_RWD_8821C 0x069C\n#define REG_RXFLTMAP0_8821C 0x06A0\n#define REG_RXFLTMAP1_8821C 0x06A2\n#define REG_RXFLTMAP2_8821C 0x06A4\n#define REG_BCN_PSR_RPT_8821C 0x06A8\n#define REG_FLC_RPC_8821C 0x06AC\n#define REG_FLC_RPCT_8821C 0x06AD\n#define REG_FLC_PTS_8821C 0x06AE\n#define REG_FLC_TRPC_8821C 0x06AF\n#define REG_RXPKTMON_CTRL_8821C 0x06B0\n#define REG_STATE_MON_8821C 0x06B4\n#define REG_ERROR_MON_8821C 0x06B8\n#define REG_SEARCH_MACID_8821C 0x06BC\n#define REG_BT_COEX_TABLE_8821C 0x06C0\n#define REG_BT_COEX_TABLE2_8821C 0x06C4\n#define REG_BT_COEX_BREAK_TABLE_8821C 0x06C8\n#define REG_BT_COEX_TABLE_H_8821C 0x06CC\n#define REG_RXCMD_0_8821C 0x06D0\n#define REG_RXCMD_1_8821C 0x06D4\n#define REG_WMAC_RESP_TXINFO_8821C 0x06D8\n#define REG_BBPSF_CTRL_8821C 0x06DC\n#define REG_P2P_RX_BCN_NOA_8821C 0x06E0\n#define REG_ASSOCIATED_BFMER0_INFO_8821C 0x06E4\n#define REG_ASSOCIATED_BFMER0_INFO_H_8821C 0x06E8\n#define REG_ASSOCIATED_BFMER1_INFO_8821C 0x06EC\n#define REG_ASSOCIATED_BFMER1_INFO_H_8821C 0x06F0\n#define REG_TX_CSI_RPT_PARAM_BW20_8821C 0x06F4\n#define REG_TX_CSI_RPT_PARAM_BW40_8821C 0x06F8\n#define REG_BCN_PSR_RPT2_8821C 0x1600\n#define REG_BCN_PSR_RPT3_8821C 0x1604\n#define REG_BCN_PSR_RPT4_8821C 0x1608\n#define REG_A1_ADDR_MASK_8821C 0x160C\n#define REG_MACID2_8821C 0x1620\n#define REG_MACID2_H_8821C 0x1624\n#define REG_BSSID2_8821C 0x1628\n#define REG_BSSID2_H_8821C 0x162C\n#define REG_MACID3_8821C 0x1630\n#define REG_MACID3_H_8821C 0x1634\n#define REG_BSSID3_8821C 0x1638\n#define REG_BSSID3_H_8821C 0x163C\n#define REG_MACID4_8821C 0x1640\n#define REG_MACID4_H_8821C 0x1644\n#define REG_BSSID4_8821C 0x1648\n#define REG_BSSID4_H_8821C 0x164C\n#define REG_NOA_REPORT_8821C 0x1650\n#define REG_NOA_REPORT_1_8821C 0x1654\n#define REG_NOA_REPORT_2_8821C 0x1658\n#define REG_NOA_REPORT_3_8821C 0x165C\n#define REG_PWRBIT_SETTING_8821C 0x1660\n#define REG_MU_BF_OPTION_8821C 0x167C\n#define REG_WMAC_PAUSE_BB_CLR_TH_8821C 0x167D\n#define REG_WMAC_MU_ARB_8821C 0x167E\n#define REG_WMAC_MU_OPTION_8821C 0x167F\n#define REG_WMAC_MU_BF_CTL_8821C 0x1680\n#define REG_WMAC_MU_BFRPT_PARA_8821C 0x1682\n#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8821C 0x1684\n#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8821C 0x1686\n#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8821C 0x1688\n#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8821C 0x168A\n#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8821C 0x168C\n#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8821C 0x168E\n#define REG_WMAC_BB_STOP_RX_COUNTER_8821C 0x1690\n#define REG_WMAC_PLCP_MONITOR_8821C 0x1694\n#define REG_WMAC_PLCP_MONITOR_MUTX_8821C 0x1698\n#define REG_TRANSMIT_ADDRSS_0_8821C 0x16A0\n#define REG_TRANSMIT_ADDRSS_0_H_8821C 0x16A4\n#define REG_TRANSMIT_ADDRSS_1_8821C 0x16A8\n#define REG_TRANSMIT_ADDRSS_1_H_8821C 0x16AC\n#define REG_TRANSMIT_ADDRSS_2_8821C 0x16B0\n#define REG_TRANSMIT_ADDRSS_2_H_8821C 0x16B4\n#define REG_TRANSMIT_ADDRSS_3_8821C 0x16B8\n#define REG_TRANSMIT_ADDRSS_3_H_8821C 0x16BC\n#define REG_TRANSMIT_ADDRSS_4_8821C 0x16C0\n#define REG_TRANSMIT_ADDRSS_4_H_8821C 0x16C4\n#define REG_MACID1_8821C 0x0700\n#define REG_MACID1_1_8821C 0x0704\n#define REG_BSSID1_8821C 0x0708\n#define REG_BSSID1_1_8821C 0x070C\n#define REG_BCN_PSR_RPT1_8821C 0x0710\n#define REG_ASSOCIATED_BFMEE_SEL_8821C 0x0714\n#define REG_SND_PTCL_CTRL_8821C 0x0718\n#define REG_RX_CSI_RPT_INFO_8821C 0x071C\n#define REG_NS_ARP_CTRL_8821C 0x0720\n#define REG_NS_ARP_INFO_8821C 0x0724\n#define REG_BEAMFORMING_INFO_NSARP_V1_8821C 0x0728\n#define REG_BEAMFORMING_INFO_NSARP_8821C 0x072C\n#define REG_IPV6_8821C 0x0730\n#define REG_IPV6_1_8821C 0x0734\n#define REG_IPV6_2_8821C 0x0738\n#define REG_IPV6_3_8821C 0x073C\n#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8821C 0x0750\n#define REG_WMAC_SWAES_CFG_8821C 0x0760\n#define REG_BT_COEX_V2_8821C 0x0762\n#define REG_BT_COEX_8821C 0x0764\n#define REG_WLAN_ACT_MASK_CTRL_8821C 0x0768\n#define REG_WLAN_ACT_MASK_CTRL_1_8821C 0x076C\n#define REG_BT_COEX_ENHANCED_INTR_CTRL_8821C 0x076E\n#define REG_BT_ACT_STATISTICS_8821C 0x0770\n#define REG_BT_ACT_STATISTICS_1_8821C 0x0774\n#define REG_BT_STATISTICS_CONTROL_REGISTER_8821C 0x0778\n#define REG_BT_STATUS_REPORT_REGISTER_8821C 0x077C\n#define REG_BT_INTERRUPT_CONTROL_REGISTER_8821C 0x0780\n#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8821C 0x0784\n#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8821C 0x0785\n#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8821C 0x0788\n#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8821C 0x078C\n#define REG_BT_INTERRUPT_STATUS_REGISTER_8821C 0x078F\n#define REG_BT_TDMA_TIME_REGISTER_8821C 0x0790\n#define REG_BT_ACT_REGISTER_8821C 0x0794\n#define REG_OBFF_CTRL_BASIC_8821C 0x0798\n#define REG_OBFF_CTRL2_TIMER_8821C 0x079C\n#define REG_LTR_CTRL_BASIC_8821C 0x07A0\n#define REG_LTR_CTRL2_TIMER_THRESHOLD_8821C 0x07A4\n#define REG_LTR_IDLE_LATENCY_V1_8821C 0x07A8\n#define REG_LTR_ACTIVE_LATENCY_V1_8821C 0x07AC\n#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8821C 0x07B0\n#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8821C 0x07B4\n#define REG_WMAC_PKTCNT_RWD_8821C 0x07B8\n#define REG_WMAC_PKTCNT_CTRL_8821C 0x07BC\n#define REG_IQ_DUMP_8821C 0x07C0\n#define REG_IQ_DUMP_1_8821C 0x07C4\n#define REG_IQ_DUMP_2_8821C 0x07C8\n#define REG_WMAC_FTM_CTL_8821C 0x07CC\n#define REG_WMAC_IQ_MDPK_FUNC_8821C 0x07CE\n#define REG_WMAC_OPTION_FUNCTION_8821C 0x07D0\n#define REG_WMAC_OPTION_FUNCTION_1_8821C 0x07D4\n#define REG_WMAC_OPTION_FUNCTION_2_8821C 0x07D8\n#define REG_RX_FILTER_FUNCTION_8821C 0x07DA\n#define REG_NDP_SIG_8821C 0x07E0\n#define REG_TXCMD_INFO_FOR_RSP_PKT_8821C 0x07E4\n#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8821C 0x07E8\n#define REG_WSEC_OPTION_8821C 0x07EC\n#define REG_RTS_ADDRESS_0_8821C 0x07F0\n#define REG_RTS_ADDRESS_0_1_8821C 0x07F4\n#define REG_RTS_ADDRESS_1_8821C 0x07F8\n#define REG_RTS_ADDRESS_1_1_8821C 0x07FC\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8821C 0x1700\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8821C 0x1704\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8821C 0x1708\n#define REG_SDIO_TX_CTRL_8821C 0x10250000\n#define REG_SDIO_HIMR_8821C 0x10250014\n#define REG_SDIO_HISR_8821C 0x10250018\n#define REG_SDIO_RX_REQ_LEN_8821C 0x1025001C\n#define REG_SDIO_FREE_TXPG_SEQ_V1_8821C 0x1025001F\n#define REG_SDIO_FREE_TXPG_8821C 0x10250020\n#define REG_SDIO_FREE_TXPG2_8821C 0x10250024\n#define REG_SDIO_OQT_FREE_TXPG_V1_8821C 0x10250028\n#define REG_SDIO_HTSFR_INFO_8821C 0x10250030\n#define REG_SDIO_HCPWM1_V2_8821C 0x10250038\n#define REG_SDIO_HCPWM2_V2_8821C 0x1025003A\n#define REG_SDIO_INDIRECT_REG_CFG_8821C 0x10250040\n#define REG_SDIO_INDIRECT_REG_DATA_8821C 0x10250044\n#define REG_SDIO_H2C_8821C 0x10250060\n#define REG_SDIO_C2H_8821C 0x10250064\n#define REG_SDIO_HRPWM1_8821C 0x10250080\n#define REG_SDIO_HRPWM2_8821C 0x10250082\n#define REG_SDIO_HPS_CLKR_8821C 0x10250084\n#define REG_SDIO_BUS_CTRL_8821C 0x10250085\n#define REG_SDIO_HSUS_CTRL_8821C 0x10250086\n#define REG_SDIO_RESPONSE_TIMER_8821C 0x10250088\n#define REG_SDIO_CMD_CRC_8821C 0x1025008A\n#define REG_SDIO_HSISR_8821C 0x10250090\n#define REG_SDIO_ERR_RPT_8821C 0x102500C0\n#define REG_SDIO_CMD_ERRCNT_8821C 0x102500C2\n#define REG_SDIO_DATA_ERRCNT_8821C 0x102500C3\n#define REG_SDIO_CMD_ERR_CONTENT_8821C 0x102500C4\n#define REG_SDIO_CRC_ERR_IDX_8821C 0x102500C9\n#define REG_SDIO_DATA_CRC_8821C 0x102500CA\n#define REG_SDIO_DATA_REPLY_TIME_8821C 0x102500CB\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_reg_8822b.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef __INC_HALMAC_REG_8822B_H\n#define __INC_HALMAC_REG_8822B_H\n\n#define REG_SYS_ISO_CTRL_8822B 0x0000\n#define REG_SYS_FUNC_EN_8822B 0x0002\n#define REG_SYS_PW_CTRL_8822B 0x0004\n#define REG_SYS_CLK_CTRL_8822B 0x0008\n#define REG_SYS_EEPROM_CTRL_8822B 0x000A\n#define REG_EE_VPD_8822B 0x000C\n#define REG_SYS_SWR_CTRL1_8822B 0x0010\n#define REG_SYS_SWR_CTRL2_8822B 0x0014\n#define REG_SYS_SWR_CTRL3_8822B 0x0018\n#define REG_RSV_CTRL_8822B 0x001C\n#define REG_RF_CTRL_8822B 0x001F\n#define REG_AFE_LDO_CTRL_8822B 0x0020\n#define REG_AFE_CTRL1_8822B 0x0024\n#define REG_AFE_CTRL2_8822B 0x0028\n#define REG_AFE_CTRL3_8822B 0x002C\n#define REG_EFUSE_CTRL_8822B 0x0030\n#define REG_LDO_EFUSE_CTRL_8822B 0x0034\n#define REG_PWR_OPTION_CTRL_8822B 0x0038\n#define REG_CAL_TIMER_8822B 0x003C\n#define REG_ACLK_MON_8822B 0x003E\n#define REG_GPIO_MUXCFG_8822B 0x0040\n#define REG_GPIO_PIN_CTRL_8822B 0x0044\n#define REG_GPIO_INTM_8822B 0x0048\n#define REG_LED_CFG_8822B 0x004C\n#define REG_FSIMR_8822B 0x0050\n#define REG_FSISR_8822B 0x0054\n#define REG_HSIMR_8822B 0x0058\n#define REG_HSISR_8822B 0x005C\n#define REG_GPIO_EXT_CTRL_8822B 0x0060\n#define REG_PAD_CTRL1_8822B 0x0064\n#define REG_WL_BT_PWR_CTRL_8822B 0x0068\n#define REG_SDM_DEBUG_8822B 0x006C\n#define REG_SYS_SDIO_CTRL_8822B 0x0070\n#define REG_HCI_OPT_CTRL_8822B 0x0074\n#define REG_AFE_CTRL4_8822B 0x0078\n#define REG_LDO_SWR_CTRL_8822B 0x007C\n#define REG_MCUFW_CTRL_8822B 0x0080\n#define REG_MCU_TST_CFG_8822B 0x0084\n#define REG_HMEBOX_E0_E1_8822B 0x0088\n#define REG_HMEBOX_E2_E3_8822B 0x008C\n#define REG_WLLPS_CTRL_8822B 0x0090\n#define REG_AFE_CTRL5_8822B 0x0094\n#define REG_GPIO_DEBOUNCE_CTRL_8822B 0x0098\n#define REG_RPWM2_8822B 0x009C\n#define REG_SYSON_FSM_MON_8822B 0x00A0\n#define REG_AFE_CTRL6_8822B 0x00A4\n#define REG_PMC_DBG_CTRL1_8822B 0x00A8\n#define REG_AFE_CTRL7_8822B 0x00AC\n#define REG_HIMR0_8822B 0x00B0\n#define REG_HISR0_8822B 0x00B4\n#define REG_HIMR1_8822B 0x00B8\n#define REG_HISR1_8822B 0x00BC\n#define REG_DBG_PORT_SEL_8822B 0x00C0\n#define REG_PAD_CTRL2_8822B 0x00C4\n#define REG_PMC_DBG_CTRL2_8822B 0x00CC\n#define REG_BIST_CTRL_8822B 0x00D0\n#define REG_BIST_RPT_8822B 0x00D4\n#define REG_MEM_CTRL_8822B 0x00D8\n#define REG_AFE_CTRL8_8822B 0x00DC\n#define REG_USB_SIE_INTF_8822B 0x00E0\n#define REG_PCIE_MIO_INTF_8822B 0x00E4\n#define REG_PCIE_MIO_INTD_8822B 0x00E8\n#define REG_WLRF1_8822B 0x00EC\n#define REG_SYS_CFG1_8822B 0x00F0\n#define REG_SYS_STATUS1_8822B 0x00F4\n#define REG_SYS_STATUS2_8822B 0x00F8\n#define REG_SYS_CFG2_8822B 0x00FC\n#define REG_SYS_CFG3_8822B 0x1000\n#define REG_SYS_CFG4_8822B 0x1034\n#define REG_SYS_CFG5_8822B 0x1070\n#define REG_CPU_DMEM_CON_8822B 0x1080\n#define REG_BOOT_REASON_8822B 0x1088\n#define REG_NFCPAD_CTRL_8822B 0x10A8\n#define REG_HIMR2_8822B 0x10B0\n#define REG_HISR2_8822B 0x10B4\n#define REG_HIMR3_8822B 0x10B8\n#define REG_HISR3_8822B 0x10BC\n#define REG_SW_MDIO_8822B 0x10C0\n#define REG_SW_FLUSH_8822B 0x10C4\n#define REG_H2C_PKT_READADDR_8822B 0x10D0\n#define REG_H2C_PKT_WRITEADDR_8822B 0x10D4\n#define REG_MEM_PWR_CRTL_8822B 0x10D8\n#define REG_FW_DBG0_8822B 0x10E0\n#define REG_FW_DBG1_8822B 0x10E4\n#define REG_FW_DBG2_8822B 0x10E8\n#define REG_FW_DBG3_8822B 0x10EC\n#define REG_FW_DBG4_8822B 0x10F0\n#define REG_FW_DBG5_8822B 0x10F4\n#define REG_FW_DBG6_8822B 0x10F8\n#define REG_FW_DBG7_8822B 0x10FC\n#define REG_CR_8822B 0x0100\n#define REG_TSF_CLK_STATE_8822B 0x0108\n#define REG_TXDMA_PQ_MAP_8822B 0x010C\n#define REG_TRXFF_BNDY_8822B 0x0114\n#define REG_PTA_I2C_MBOX_8822B 0x0118\n#define REG_RXFF_BNDY_8822B 0x011C\n#define REG_FE1IMR_8822B 0x0120\n#define REG_FE1ISR_8822B 0x0124\n#define REG_CPWM_8822B 0x012C\n#define REG_FWIMR_8822B 0x0130\n#define REG_FWISR_8822B 0x0134\n#define REG_FTIMR_8822B 0x0138\n#define REG_FTISR_8822B 0x013C\n#define REG_PKTBUF_DBG_CTRL_8822B 0x0140\n#define REG_PKTBUF_DBG_DATA_L_8822B 0x0144\n#define REG_PKTBUF_DBG_DATA_H_8822B 0x0148\n#define REG_CPWM2_8822B 0x014C\n#define REG_TC0_CTRL_8822B 0x0150\n#define REG_TC1_CTRL_8822B 0x0154\n#define REG_TC2_CTRL_8822B 0x0158\n#define REG_TC3_CTRL_8822B 0x015C\n#define REG_TC4_CTRL_8822B 0x0160\n#define REG_TCUNIT_BASE_8822B 0x0164\n#define REG_TC5_CTRL_8822B 0x0168\n#define REG_TC6_CTRL_8822B 0x016C\n#define REG_MBIST_FAIL_8822B 0x0170\n#define REG_MBIST_START_PAUSE_8822B 0x0174\n#define REG_MBIST_DONE_8822B 0x0178\n#define REG_MBIST_FAIL_NRML_8822B 0x017C\n#define REG_AES_DECRPT_DATA_8822B 0x0180\n#define REG_AES_DECRPT_CFG_8822B 0x0184\n#define REG_TMETER_8822B 0x0190\n#define REG_OSC_32K_CTRL_8822B 0x0194\n#define REG_32K_CAL_REG1_8822B 0x0198\n#define REG_C2HEVT_8822B 0x01A0\n#define REG_C2HEVT_1_8822B 0x01A4\n#define REG_C2HEVT_2_8822B 0x01A8\n#define REG_C2HEVT_3_8822B 0x01AC\n#define REG_SW_DEFINED_PAGE1_8822B 0x01B8\n#define REG_MCUTST_I_8822B 0x01C0\n#define REG_MCUTST_II_8822B 0x01C4\n#define REG_FMETHR_8822B 0x01C8\n#define REG_HMETFR_8822B 0x01CC\n#define REG_HMEBOX0_8822B 0x01D0\n#define REG_HMEBOX1_8822B 0x01D4\n#define REG_HMEBOX2_8822B 0x01D8\n#define REG_HMEBOX3_8822B 0x01DC\n#define REG_LLT_INIT_8822B 0x01E0\n#define REG_LLT_INIT_ADDR_8822B 0x01E4\n#define REG_BB_ACCESS_CTRL_8822B 0x01E8\n#define REG_BB_ACCESS_DATA_8822B 0x01EC\n#define REG_HMEBOX_E0_8822B 0x01F0\n#define REG_HMEBOX_E1_8822B 0x01F4\n#define REG_HMEBOX_E2_8822B 0x01F8\n#define REG_HMEBOX_E3_8822B 0x01FC\n#define REG_CR_EXT_8822B 0x1100\n#define REG_FWFF_8822B 0x1114\n#define REG_RXFF_PTR_V1_8822B 0x1118\n#define REG_RXFF_WTR_V1_8822B 0x111C\n#define REG_FE2IMR_8822B 0x1120\n#define REG_FE2ISR_8822B 0x1124\n#define REG_FE3IMR_8822B 0x1128\n#define REG_FE3ISR_8822B 0x112C\n#define REG_FE4IMR_8822B 0x1130\n#define REG_FE4ISR_8822B 0x1134\n#define REG_FT1IMR_8822B 0x1138\n#define REG_FT1ISR_8822B 0x113C\n#define REG_SPWR0_8822B 0x1140\n#define REG_SPWR1_8822B 0x1144\n#define REG_SPWR2_8822B 0x1148\n#define REG_SPWR3_8822B 0x114C\n#define REG_POWSEQ_8822B 0x1150\n#define REG_TC7_CTRL_V1_8822B 0x1158\n#define REG_TC8_CTRL_V1_8822B 0x115C\n#define REG_FT2IMR_8822B 0x11E0\n#define REG_FT2ISR_8822B 0x11E4\n#define REG_MSG2_8822B 0x11F0\n#define REG_MSG3_8822B 0x11F4\n#define REG_MSG4_8822B 0x11F8\n#define REG_MSG5_8822B 0x11FC\n#define REG_FIFOPAGE_CTRL_1_8822B 0x0200\n#define REG_FIFOPAGE_CTRL_2_8822B 0x0204\n#define REG_AUTO_LLT_V1_8822B 0x0208\n#define REG_TXDMA_OFFSET_CHK_8822B 0x020C\n#define REG_TXDMA_STATUS_8822B 0x0210\n#define REG_TX_DMA_DBG_8822B 0x0214\n#define REG_TQPNT1_8822B 0x0218\n#define REG_TQPNT2_8822B 0x021C\n#define REG_TQPNT3_8822B 0x0220\n#define REG_TQPNT4_8822B 0x0224\n#define REG_RQPN_CTRL_1_8822B 0x0228\n#define REG_RQPN_CTRL_2_8822B 0x022C\n#define REG_FIFOPAGE_INFO_1_8822B 0x0230\n#define REG_FIFOPAGE_INFO_2_8822B 0x0234\n#define REG_FIFOPAGE_INFO_3_8822B 0x0238\n#define REG_FIFOPAGE_INFO_4_8822B 0x023C\n#define REG_FIFOPAGE_INFO_5_8822B 0x0240\n#define REG_H2C_HEAD_8822B 0x0244\n#define REG_H2C_TAIL_8822B 0x0248\n#define REG_H2C_READ_ADDR_8822B 0x024C\n#define REG_H2C_WR_ADDR_8822B 0x0250\n#define REG_H2C_INFO_8822B 0x0254\n#define REG_RXDMA_AGG_PG_TH_8822B 0x0280\n#define REG_RXPKT_NUM_8822B 0x0284\n#define REG_RXDMA_STATUS_8822B 0x0288\n#define REG_RXDMA_DPR_8822B 0x028C\n#define REG_RXDMA_MODE_8822B 0x0290\n#define REG_C2H_PKT_8822B 0x0294\n#define REG_FWFF_C2H_8822B 0x0298\n#define REG_FWFF_CTRL_8822B 0x029C\n#define REG_FWFF_PKT_INFO_8822B 0x02A0\n#define REG_DDMA_CH0SA_8822B 0x1200\n#define REG_DDMA_CH0DA_8822B 0x1204\n#define REG_DDMA_CH0CTRL_8822B 0x1208\n#define REG_DDMA_CH1SA_8822B 0x1210\n#define REG_DDMA_CH1DA_8822B 0x1214\n#define REG_DDMA_CH1CTRL_8822B 0x1218\n#define REG_DDMA_CH2SA_8822B 0x1220\n#define REG_DDMA_CH2DA_8822B 0x1224\n#define REG_DDMA_CH2CTRL_8822B 0x1228\n#define REG_DDMA_CH3SA_8822B 0x1230\n#define REG_DDMA_CH3DA_8822B 0x1234\n#define REG_DDMA_CH3CTRL_8822B 0x1238\n#define REG_DDMA_CH4SA_8822B 0x1240\n#define REG_DDMA_CH4DA_8822B 0x1244\n#define REG_DDMA_CH4CTRL_8822B 0x1248\n#define REG_DDMA_CH5SA_8822B 0x1250\n#define REG_DDMA_CH5DA_8822B 0x1254\n#define REG_REG_DDMA_CH5CTRL_8822B 0x1258\n#define REG_DDMA_INT_MSK_8822B 0x12E0\n#define REG_DDMA_CHSTATUS_8822B 0x12E8\n#define REG_DDMA_CHKSUM_8822B 0x12F0\n#define REG_DDMA_MONITOR_8822B 0x12FC\n#define REG_PCIE_CTRL_8822B 0x0300\n#define REG_INT_MIG_8822B 0x0304\n#define REG_BCNQ_TXBD_DESA_8822B 0x0308\n#define REG_MGQ_TXBD_DESA_8822B 0x0310\n#define REG_VOQ_TXBD_DESA_8822B 0x0318\n#define REG_VIQ_TXBD_DESA_8822B 0x0320\n#define REG_BEQ_TXBD_DESA_8822B 0x0328\n#define REG_BKQ_TXBD_DESA_8822B 0x0330\n#define REG_RXQ_RXBD_DESA_8822B 0x0338\n#define REG_HI0Q_TXBD_DESA_8822B 0x0340\n#define REG_HI1Q_TXBD_DESA_8822B 0x0348\n#define REG_HI2Q_TXBD_DESA_8822B 0x0350\n#define REG_HI3Q_TXBD_DESA_8822B 0x0358\n#define REG_HI4Q_TXBD_DESA_8822B 0x0360\n#define REG_HI5Q_TXBD_DESA_8822B 0x0368\n#define REG_HI6Q_TXBD_DESA_8822B 0x0370\n#define REG_HI7Q_TXBD_DESA_8822B 0x0378\n#define REG_MGQ_TXBD_NUM_8822B 0x0380\n#define REG_RX_RXBD_NUM_8822B 0x0382\n#define REG_VOQ_TXBD_NUM_8822B 0x0384\n#define REG_VIQ_TXBD_NUM_8822B 0x0386\n#define REG_BEQ_TXBD_NUM_8822B 0x0388\n#define REG_BKQ_TXBD_NUM_8822B 0x038A\n#define REG_HI0Q_TXBD_NUM_8822B 0x038C\n#define REG_HI1Q_TXBD_NUM_8822B 0x038E\n#define REG_HI2Q_TXBD_NUM_8822B 0x0390\n#define REG_HI3Q_TXBD_NUM_8822B 0x0392\n#define REG_HI4Q_TXBD_NUM_8822B 0x0394\n#define REG_HI5Q_TXBD_NUM_8822B 0x0396\n#define REG_HI6Q_TXBD_NUM_8822B 0x0398\n#define REG_HI7Q_TXBD_NUM_8822B 0x039A\n#define REG_TSFTIMER_HCI_8822B 0x039C\n#define REG_BD_RWPTR_CLR_8822B 0x039C\n#define REG_VOQ_TXBD_IDX_8822B 0x03A0\n#define REG_VIQ_TXBD_IDX_8822B 0x03A4\n#define REG_BEQ_TXBD_IDX_8822B 0x03A8\n#define REG_BKQ_TXBD_IDX_8822B 0x03AC\n#define REG_MGQ_TXBD_IDX_8822B 0x03B0\n#define REG_RXQ_RXBD_IDX_8822B 0x03B4\n#define REG_HI0Q_TXBD_IDX_8822B 0x03B8\n#define REG_HI1Q_TXBD_IDX_8822B 0x03BC\n#define REG_HI2Q_TXBD_IDX_8822B 0x03C0\n#define REG_HI3Q_TXBD_IDX_8822B 0x03C4\n#define REG_HI4Q_TXBD_IDX_8822B 0x03C8\n#define REG_HI5Q_TXBD_IDX_8822B 0x03CC\n#define REG_HI6Q_TXBD_IDX_8822B 0x03D0\n#define REG_HI7Q_TXBD_IDX_8822B 0x03D4\n#define REG_DBG_SEL_V1_8822B 0x03D8\n#define REG_PCIE_HRPWM1_V1_8822B 0x03D9\n#define REG_PCIE_HCPWM1_V1_8822B 0x03DA\n#define REG_PCIE_CTRL2_8822B 0x03DB\n#define REG_PCIE_HRPWM2_V1_8822B 0x03DC\n#define REG_PCIE_HCPWM2_V1_8822B 0x03DE\n#define REG_PCIE_H2C_MSG_V1_8822B 0x03E0\n#define REG_PCIE_C2H_MSG_V1_8822B 0x03E4\n#define REG_DBI_WDATA_V1_8822B 0x03E8\n#define REG_DBI_RDATA_V1_8822B 0x03EC\n#define REG_DBI_FLAG_V1_8822B 0x03F0\n#define REG_MDIO_V1_8822B 0x03F4\n#define REG_PCIE_MIX_CFG_8822B 0x03F8\n#define REG_HCI_MIX_CFG_8822B 0x03FC\n#define REG_STC_INT_CS_8822B 0x1300\n#define REG_ST_INT_CFG_8822B 0x1304\n#define REG_CMU_DLY_CTRL_8822B 0x1310\n#define REG_CMU_DLY_CFG_8822B 0x1314\n#define REG_H2CQ_TXBD_DESA_8822B 0x1320\n#define REG_H2CQ_TXBD_NUM_8822B 0x1328\n#define REG_H2CQ_TXBD_IDX_8822B 0x132C\n#define REG_H2CQ_CSR_8822B 0x1330\n#define REG_CHANGE_PCIE_SPEED_8822B 0x1350\n#define REG_OLD_DEHANG_8822B 0x13F4\n#define REG_Q0_INFO_8822B 0x0400\n#define REG_Q1_INFO_8822B 0x0404\n#define REG_Q2_INFO_8822B 0x0408\n#define REG_Q3_INFO_8822B 0x040C\n#define REG_MGQ_INFO_8822B 0x0410\n#define REG_HIQ_INFO_8822B 0x0414\n#define REG_BCNQ_INFO_8822B 0x0418\n#define REG_TXPKT_EMPTY_8822B 0x041A\n#define REG_CPU_MGQ_INFO_8822B 0x041C\n#define REG_FWHW_TXQ_CTRL_8822B 0x0420\n#define REG_DATAFB_SEL_8822B 0x0423\n#define REG_BCNQ_BDNY_V1_8822B 0x0424\n#define REG_LIFETIME_EN_8822B 0x0426\n#define REG_SPEC_SIFS_8822B 0x0428\n#define REG_RETRY_LIMIT_8822B 0x042A\n#define REG_TXBF_CTRL_8822B 0x042C\n#define REG_DARFRC_8822B 0x0430\n#define REG_RARFRC_8822B 0x0438\n#define REG_RRSR_8822B 0x0440\n#define REG_ARFR0_8822B 0x0444\n#define REG_ARFR1_V1_8822B 0x044C\n#define REG_CCK_CHECK_8822B 0x0454\n#define REG_AMPDU_MAX_TIME_V1_8822B 0x0455\n#define REG_BCNQ1_BDNY_V1_8822B 0x0456\n#define REG_AMPDU_MAX_LENGTH_8822B 0x0458\n#define REG_ACQ_STOP_8822B 0x045C\n#define REG_NDPA_RATE_8822B 0x045D\n#define REG_TX_HANG_CTRL_8822B 0x045E\n#define REG_NDPA_OPT_CTRL_8822B 0x045F\n#define REG_RD_RESP_PKT_TH_8822B 0x0463\n#define REG_CMDQ_INFO_8822B 0x0464\n#define REG_Q4_INFO_8822B 0x0468\n#define REG_Q5_INFO_8822B 0x046C\n#define REG_Q6_INFO_8822B 0x0470\n#define REG_Q7_INFO_8822B 0x0474\n#define REG_WMAC_LBK_BUF_HD_V1_8822B 0x0478\n#define REG_MGQ_BDNY_V1_8822B 0x047A\n#define REG_TXRPT_CTRL_8822B 0x047C\n#define REG_INIRTS_RATE_SEL_8822B 0x0480\n#define REG_BASIC_CFEND_RATE_8822B 0x0481\n#define REG_STBC_CFEND_RATE_8822B 0x0482\n#define REG_DATA_SC_8822B 0x0483\n#define REG_MACID_SLEEP3_8822B 0x0484\n#define REG_MACID_SLEEP1_8822B 0x0488\n#define REG_ARFR2_V1_8822B 0x048C\n#define REG_ARFR3_V1_8822B 0x0494\n#define REG_ARFR4_8822B 0x049C\n#define REG_ARFR5_8822B 0x04A4\n#define REG_TXRPT_START_OFFSET_8822B 0x04AC\n#define REG_POWER_STAGE1_8822B 0x04B4\n#define REG_POWER_STAGE2_8822B 0x04B8\n#define REG_SW_AMPDU_BURST_MODE_CTRL_8822B 0x04BC\n#define REG_PKT_LIFE_TIME_8822B 0x04C0\n#define REG_STBC_SETTING_8822B 0x04C4\n#define REG_STBC_SETTING2_8822B 0x04C5\n#define REG_QUEUE_CTRL_8822B 0x04C6\n#define REG_SINGLE_AMPDU_CTRL_8822B 0x04C7\n#define REG_PROT_MODE_CTRL_8822B 0x04C8\n#define REG_BAR_MODE_CTRL_8822B 0x04CC\n#define REG_RA_TRY_RATE_AGG_LMT_8822B 0x04CF\n#define REG_MACID_SLEEP2_8822B 0x04D0\n#define REG_MACID_SLEEP_8822B 0x04D4\n#define REG_HW_SEQ0_8822B 0x04D8\n#define REG_HW_SEQ1_8822B 0x04DA\n#define REG_HW_SEQ2_8822B 0x04DC\n#define REG_HW_SEQ3_8822B 0x04DE\n#define REG_NULL_PKT_STATUS_V1_8822B 0x04E0\n#define REG_PTCL_ERR_STATUS_8822B 0x04E2\n#define REG_NULL_PKT_STATUS_EXTEND_8822B 0x04E3\n#define REG_VIDEO_ENHANCEMENT_FUN_8822B 0x04E4\n#define REG_BT_POLLUTE_PKT_CNT_8822B 0x04E8\n#define REG_PTCL_DBG_8822B 0x04EC\n#define REG_CPUMGQ_TIMER_CTRL2_8822B 0x04F4\n#define REG_DUMMY_PAGE4_V1_8822B 0x04FC\n#define REG_MOREDATA_8822B 0x04FE\n#define REG_Q0_Q1_INFO_8822B 0x1400\n#define REG_Q2_Q3_INFO_8822B 0x1404\n#define REG_Q4_Q5_INFO_8822B 0x1408\n#define REG_Q6_Q7_INFO_8822B 0x140C\n#define REG_MGQ_HIQ_INFO_8822B 0x1410\n#define REG_CMDQ_BCNQ_INFO_8822B 0x1414\n#define REG_USEREG_SETTING_8822B 0x1420\n#define REG_AESIV_SETTING_8822B 0x1424\n#define REG_BF0_TIME_SETTING_8822B 0x1428\n#define REG_BF1_TIME_SETTING_8822B 0x142C\n#define REG_BF_TIMEOUT_EN_8822B 0x1430\n#define REG_MACID_RELEASE0_8822B 0x1434\n#define REG_MACID_RELEASE1_8822B 0x1438\n#define REG_MACID_RELEASE2_8822B 0x143C\n#define REG_MACID_RELEASE3_8822B 0x1440\n#define REG_MACID_RELEASE_SETTING_8822B 0x1444\n#define REG_FAST_EDCA_VOVI_SETTING_8822B 0x1448\n#define REG_FAST_EDCA_BEBK_SETTING_8822B 0x144C\n#define REG_MACID_DROP0_8822B 0x1450\n#define REG_MACID_DROP1_8822B 0x1454\n#define REG_MACID_DROP2_8822B 0x1458\n#define REG_MACID_DROP3_8822B 0x145C\n#define REG_R_MACID_RELEASE_SUCCESS_0_8822B 0x1460\n#define REG_R_MACID_RELEASE_SUCCESS_1_8822B 0x1464\n#define REG_R_MACID_RELEASE_SUCCESS_2_8822B 0x1468\n#define REG_R_MACID_RELEASE_SUCCESS_3_8822B 0x146C\n#define REG_MGG_FIFO_CRTL_8822B 0x1470\n#define REG_MGG_FIFO_INT_8822B 0x1474\n#define REG_MGG_FIFO_LIFETIME_8822B 0x1478\n#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0x147C\n#define REG_SHCUT_SETTING_8822B 0x1480\n#define REG_SHCUT_LLC_ETH_TYPE0_8822B 0x1484\n#define REG_SHCUT_LLC_ETH_TYPE1_8822B 0x1488\n#define REG_SHCUT_LLC_OUI0_8822B 0x148C\n#define REG_SHCUT_LLC_OUI1_8822B 0x1490\n#define REG_SHCUT_LLC_OUI2_8822B 0x1494\n#define REG_SHCUT_LLC_OUI3_8822B 0x1498\n#define REG_MU_TX_CTL_8822B 0x14C0\n#define REG_MU_TX_CTL_8822B 0x14C0\n#define REG_MU_STA_GID_VLD_8822B 0x14C4\n#define REG_MU_STA_GID_VLD_8822B 0x14C4\n#define REG_MU_STA_USER_POS_INFO_8822B 0x14C8\n#define REG_MU_STA_USER_POS_INFO_8822B 0x14C8\n#define REG_MU_TRX_DBG_CNT_8822B 0x14D0\n#define REG_MU_TRX_DBG_CNT_8822B 0x14D0\n#define REG_EDCA_VO_PARAM_8822B 0x0500\n#define REG_EDCA_VI_PARAM_8822B 0x0504\n#define REG_EDCA_BE_PARAM_8822B 0x0508\n#define REG_EDCA_BK_PARAM_8822B 0x050C\n#define REG_BCNTCFG_8822B 0x0510\n#define REG_PIFS_8822B 0x0512\n#define REG_RDG_PIFS_8822B 0x0513\n#define REG_SIFS_8822B 0x0514\n#define REG_TSFTR_SYN_OFFSET_8822B 0x0518\n#define REG_AGGR_BREAK_TIME_8822B 0x051A\n#define REG_SLOT_8822B 0x051B\n#define REG_TX_PTCL_CTRL_8822B 0x0520\n#define REG_TXPAUSE_8822B 0x0522\n#define REG_DIS_TXREQ_CLR_8822B 0x0523\n#define REG_RD_CTRL_8822B 0x0524\n#define REG_MBSSID_CTRL_8822B 0x0526\n#define REG_P2PPS_CTRL_8822B 0x0527\n#define REG_PKT_LIFETIME_CTRL_8822B 0x0528\n#define REG_P2PPS_SPEC_STATE_8822B 0x052B\n#define REG_TXOP_LIMIT_CTRL_8822B 0x052C\n#define REG_BAR_TX_CTRL_8822B 0x0530\n#define REG_P2PON_DIS_TXTIME_8822B 0x0531\n#define REG_QUEUE_INCOL_THR_8822B 0x0538\n#define REG_QUEUE_INCOL_EN_8822B 0x053C\n#define REG_TBTT_PROHIBIT_8822B 0x0540\n#define REG_P2PPS_STATE_8822B 0x0543\n#define REG_RD_NAV_NXT_8822B 0x0544\n#define REG_NAV_PROT_LEN_8822B 0x0546\n#define REG_BCN_CTRL_8822B 0x0550\n#define REG_BCN_CTRL_CLINT0_8822B 0x0551\n#define REG_MBID_NUM_8822B 0x0552\n#define REG_DUAL_TSF_RST_8822B 0x0553\n#define REG_MBSSID_BCN_SPACE_8822B 0x0554\n#define REG_DRVERLYINT_8822B 0x0558\n#define REG_BCNDMATIM_8822B 0x0559\n#define REG_ATIMWND_8822B 0x055A\n#define REG_USTIME_TSF_8822B 0x055C\n#define REG_BCN_MAX_ERR_8822B 0x055D\n#define REG_RXTSF_OFFSET_CCK_8822B 0x055E\n#define REG_RXTSF_OFFSET_OFDM_8822B 0x055F\n#define REG_TSFTR_8822B 0x0560\n#define REG_FREERUN_CNT_8822B 0x0568\n#define REG_ATIMWND1_V1_8822B 0x0570\n#define REG_TBTT_PROHIBIT_INFRA_8822B 0x0571\n#define REG_CTWND_8822B 0x0572\n#define REG_BCNIVLCUNT_8822B 0x0573\n#define REG_BCNDROPCTRL_8822B 0x0574\n#define REG_HGQ_TIMEOUT_PERIOD_8822B 0x0575\n#define REG_TXCMD_TIMEOUT_PERIOD_8822B 0x0576\n#define REG_MISC_CTRL_8822B 0x0577\n#define REG_BCN_CTRL_CLINT1_8822B 0x0578\n#define REG_BCN_CTRL_CLINT2_8822B 0x0579\n#define REG_BCN_CTRL_CLINT3_8822B 0x057A\n#define REG_EXTEND_CTRL_8822B 0x057B\n#define REG_P2PPS1_SPEC_STATE_8822B 0x057C\n#define REG_P2PPS1_STATE_8822B 0x057D\n#define REG_P2PPS2_SPEC_STATE_8822B 0x057E\n#define REG_P2PPS2_STATE_8822B 0x057F\n#define REG_PS_TIMER0_8822B 0x0580\n#define REG_PS_TIMER1_8822B 0x0584\n#define REG_PS_TIMER2_8822B 0x0588\n#define REG_TBTT_CTN_AREA_8822B 0x058C\n#define REG_FORCE_BCN_IFS_8822B 0x058E\n#define REG_TXOP_MIN_8822B 0x0590\n#define REG_PRE_BKF_TIME_8822B 0x0592\n#define REG_CROSS_TXOP_CTRL_8822B 0x0593\n#define REG_ATIMWND2_8822B 0x05A0\n#define REG_ATIMWND3_8822B 0x05A1\n#define REG_ATIMWND4_8822B 0x05A2\n#define REG_ATIMWND5_8822B 0x05A3\n#define REG_ATIMWND6_8822B 0x05A4\n#define REG_ATIMWND7_8822B 0x05A5\n#define REG_ATIMUGT_8822B 0x05A6\n#define REG_HIQ_NO_LMT_EN_8822B 0x05A7\n#define REG_DTIM_COUNTER_ROOT_8822B 0x05A8\n#define REG_DTIM_COUNTER_VAP1_8822B 0x05A9\n#define REG_DTIM_COUNTER_VAP2_8822B 0x05AA\n#define REG_DTIM_COUNTER_VAP3_8822B 0x05AB\n#define REG_DTIM_COUNTER_VAP4_8822B 0x05AC\n#define REG_DTIM_COUNTER_VAP5_8822B 0x05AD\n#define REG_DTIM_COUNTER_VAP6_8822B 0x05AE\n#define REG_DTIM_COUNTER_VAP7_8822B 0x05AF\n#define REG_DIS_ATIM_8822B 0x05B0\n#define REG_EARLY_128US_8822B 0x05B1\n#define REG_P2PPS1_CTRL_8822B 0x05B2\n#define REG_P2PPS2_CTRL_8822B 0x05B3\n#define REG_TIMER0_SRC_SEL_8822B 0x05B4\n#define REG_NOA_UNIT_SEL_8822B 0x05B5\n#define REG_P2POFF_DIS_TXTIME_8822B 0x05B7\n#define REG_MBSSID_BCN_SPACE2_8822B 0x05B8\n#define REG_MBSSID_BCN_SPACE3_8822B 0x05BC\n#define REG_ACMHWCTRL_8822B 0x05C0\n#define REG_ACMRSTCTRL_8822B 0x05C1\n#define REG_ACMAVG_8822B 0x05C2\n#define REG_VO_ADMTIME_8822B 0x05C4\n#define REG_VI_ADMTIME_8822B 0x05C6\n#define REG_BE_ADMTIME_8822B 0x05C8\n#define REG_EDCA_RANDOM_GEN_8822B 0x05CC\n#define REG_TXCMD_NOA_SEL_8822B 0x05CF\n#define REG_NOA_PARAM_8822B 0x05E0\n#define REG_P2P_RST_8822B 0x05F0\n#define REG_SCHEDULER_RST_8822B 0x05F1\n#define REG_SCH_TXCMD_8822B 0x05F8\n#define REG_PAGE5_DUMMY_8822B 0x05FC\n#define REG_CPUMGQ_TX_TIMER_8822B 0x1500\n#define REG_PS_TIMER_A_8822B 0x1504\n#define REG_PS_TIMER_B_8822B 0x1508\n#define REG_PS_TIMER_C_8822B 0x150C\n#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822B 0x1510\n#define REG_CPUMGQ_TX_TIMER_EARLY_8822B 0x1514\n#define REG_PS_TIMER_A_EARLY_8822B 0x1515\n#define REG_PS_TIMER_B_EARLY_8822B 0x1516\n#define REG_PS_TIMER_C_EARLY_8822B 0x1517\n#define REG_CPUMGQ_PARAMETER_8822B 0x1518\n#define REG_WMAC_CR_8822B 0x0600\n#define REG_WMAC_FWPKT_CR_8822B 0x0601\n#define REG_BWOPMODE_8822B 0x0603\n#define REG_TCR_8822B 0x0604\n#define REG_RCR_8822B 0x0608\n#define REG_RX_PKT_LIMIT_8822B 0x060C\n#define REG_RX_DLK_TIME_8822B 0x060D\n#define REG_RX_DRVINFO_SZ_8822B 0x060F\n#define REG_MACID_8822B 0x0610\n#define REG_BSSID_8822B 0x0618\n#define REG_MAR_8822B 0x0620\n#define REG_MBIDCAMCFG_1_8822B 0x0628\n#define REG_MBIDCAMCFG_2_8822B 0x062C\n#define REG_WMAC_TCR_TSFT_OFS_8822B 0x0630\n#define REG_UDF_THSD_8822B 0x0632\n#define REG_ZLD_NUM_8822B 0x0633\n#define REG_STMP_THSD_8822B 0x0634\n#define REG_WMAC_TXTIMEOUT_8822B 0x0635\n#define REG_MCU_TEST_2_V1_8822B 0x0636\n#define REG_USTIME_EDCA_8822B 0x0638\n#define REG_MAC_SPEC_SIFS_8822B 0x063A\n#define REG_RESP_SIFS_CCK_8822B 0x063C\n#define REG_RESP_SIFS_OFDM_8822B 0x063E\n#define REG_ACKTO_8822B 0x0640\n#define REG_CTS2TO_8822B 0x0641\n#define REG_EIFS_8822B 0x0642\n#define REG_NAV_CTRL_8822B 0x0650\n#define REG_BACAMCMD_8822B 0x0654\n#define REG_BACAMCONTENT_8822B 0x0658\n#define REG_LBDLY_8822B 0x0660\n#define REG_WMAC_BACAM_RPMEN_8822B 0x0661\n#define REG_TX_RX_8822B 0x0662\n#define REG_WMAC_BITMAP_CTL_8822B 0x0663\n#define REG_RXERR_RPT_8822B 0x0664\n#define REG_WMAC_TRXPTCL_CTL_8822B 0x0668\n#define REG_CAMCMD_8822B 0x0670\n#define REG_CAMWRITE_8822B 0x0674\n#define REG_CAMREAD_8822B 0x0678\n#define REG_CAMDBG_8822B 0x067C\n#define REG_SECCFG_8822B 0x0680\n#define REG_RXFILTER_CATEGORY_1_8822B 0x0682\n#define REG_RXFILTER_ACTION_1_8822B 0x0683\n#define REG_RXFILTER_CATEGORY_2_8822B 0x0684\n#define REG_RXFILTER_ACTION_2_8822B 0x0685\n#define REG_RXFILTER_CATEGORY_3_8822B 0x0686\n#define REG_RXFILTER_ACTION_3_8822B 0x0687\n#define REG_RXFLTMAP3_8822B 0x0688\n#define REG_RXFLTMAP4_8822B 0x068A\n#define REG_RXFLTMAP5_8822B 0x068C\n#define REG_RXFLTMAP6_8822B 0x068E\n#define REG_WOW_CTRL_8822B 0x0690\n#define REG_NAN_RX_TSF_FILTER_8822B 0x0691\n#define REG_PS_RX_INFO_8822B 0x0692\n#define REG_WMMPS_UAPSD_TID_8822B 0x0693\n#define REG_LPNAV_CTRL_8822B 0x0694\n#define REG_WKFMCAM_CMD_8822B 0x0698\n#define REG_WKFMCAM_RWD_8822B 0x069C\n#define REG_RXFLTMAP0_8822B 0x06A0\n#define REG_RXFLTMAP1_8822B 0x06A2\n#define REG_RXFLTMAP2_8822B 0x06A4\n#define REG_BCN_PSR_RPT_8822B 0x06A8\n#define REG_FLC_RPC_8822B 0x06AC\n#define REG_FLC_RPCT_8822B 0x06AD\n#define REG_FLC_PTS_8822B 0x06AE\n#define REG_FLC_TRPC_8822B 0x06AF\n#define REG_RXPKTMON_CTRL_8822B 0x06B0\n#define REG_STATE_MON_8822B 0x06B4\n#define REG_ERROR_MON_8822B 0x06B8\n#define REG_SEARCH_MACID_8822B 0x06BC\n#define REG_BT_COEX_TABLE_8822B 0x06C0\n#define REG_RXCMD_0_8822B 0x06D0\n#define REG_RXCMD_1_8822B 0x06D4\n#define REG_WMAC_RESP_TXINFO_8822B 0x06D8\n#define REG_BBPSF_CTRL_8822B 0x06DC\n#define REG_P2P_RX_BCN_NOA_8822B 0x06E0\n#define REG_ASSOCIATED_BFMER0_INFO_8822B 0x06E4\n#define REG_ASSOCIATED_BFMER1_INFO_8822B 0x06EC\n#define REG_TX_CSI_RPT_PARAM_BW20_8822B 0x06F4\n#define REG_TX_CSI_RPT_PARAM_BW40_8822B 0x06F8\n#define REG_TX_CSI_RPT_PARAM_BW80_8822B 0x06FC\n#define REG_BCN_PSR_RPT2_8822B 0x1600\n#define REG_BCN_PSR_RPT3_8822B 0x1604\n#define REG_BCN_PSR_RPT4_8822B 0x1608\n#define REG_A1_ADDR_MASK_8822B 0x160C\n#define REG_MACID2_8822B 0x1620\n#define REG_BSSID2_8822B 0x1628\n#define REG_MACID3_8822B 0x1630\n#define REG_BSSID3_8822B 0x1638\n#define REG_MACID4_8822B 0x1640\n#define REG_BSSID4_8822B 0x1648\n#define REG_NOA_REPORT_8822B 0x1650\n#define REG_PWRBIT_SETTING_8822B 0x1660\n#define REG_WMAC_MU_BF_OPTION_8822B 0x167C\n#define REG_WMAC_MU_ARB_8822B 0x167E\n#define REG_WMAC_MU_OPTION_8822B 0x167F\n#define REG_WMAC_MU_BF_CTL_8822B 0x1680\n#define REG_WMAC_MU_BFRPT_PARA_8822B 0x1682\n#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B 0x1684\n#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8822B 0x1686\n#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B 0x1688\n#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8822B 0x168A\n#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B 0x168C\n#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8822B 0x168E\n#define REG_TRANSMIT_ADDRSS_0_8822B 0x16A0\n#define REG_TRANSMIT_ADDRSS_1_8822B 0x16A8\n#define REG_TRANSMIT_ADDRSS_2_8822B 0x16B0\n#define REG_TRANSMIT_ADDRSS_3_8822B 0x16B8\n#define REG_TRANSMIT_ADDRSS_4_8822B 0x16C0\n#define REG_MACID1_8822B 0x0700\n#define REG_BSSID1_8822B 0x0708\n#define REG_BCN_PSR_RPT1_8822B 0x0710\n#define REG_ASSOCIATED_BFMEE_SEL_8822B 0x0714\n#define REG_SND_PTCL_CTRL_8822B 0x0718\n#define REG_RX_CSI_RPT_INFO_8822B 0x071C\n#define REG_NS_ARP_CTRL_8822B 0x0720\n#define REG_NS_ARP_INFO_8822B 0x0724\n#define REG_BEAMFORMING_INFO_NSARP_V1_8822B 0x0728\n#define REG_BEAMFORMING_INFO_NSARP_8822B 0x072C\n#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822B 0x0750\n#define REG_WMAC_SWAES_CFG_8822B 0x0760\n#define REG_BT_COEX_V2_8822B 0x0762\n#define REG_BT_COEX_8822B 0x0764\n#define REG_WLAN_ACT_MASK_CTRL_8822B 0x0768\n#define REG_BT_COEX_ENHANCED_INTR_CTRL_8822B 0x076E\n#define REG_BT_ACT_STATISTICS_8822B 0x0770\n#define REG_BT_STATISTICS_CONTROL_REGISTER_8822B 0x0778\n#define REG_BT_STATUS_REPORT_REGISTER_8822B 0x077C\n#define REG_BT_INTERRUPT_CONTROL_REGISTER_8822B 0x0780\n#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822B 0x0784\n#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822B 0x0785\n#define REG_BT_INTERRUPT_STATUS_REGISTER_8822B 0x078F\n#define REG_BT_TDMA_TIME_REGISTER_8822B 0x0790\n#define REG_BT_ACT_REGISTER_8822B 0x0794\n#define REG_OBFF_CTRL_BASIC_8822B 0x0798\n#define REG_OBFF_CTRL2_TIMER_8822B 0x079C\n#define REG_LTR_CTRL_BASIC_8822B 0x07A0\n#define REG_LTR_CTRL2_TIMER_THRESHOLD_8822B 0x07A4\n#define REG_LTR_IDLE_LATENCY_V1_8822B 0x07A8\n#define REG_LTR_ACTIVE_LATENCY_V1_8822B 0x07AC\n#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822B 0x07B0\n#define REG_WMAC_PKTCNT_RWD_8822B 0x07B8\n#define REG_WMAC_PKTCNT_CTRL_8822B 0x07BC\n#define REG_IQ_DUMP_8822B 0x07C0\n#define REG_WMAC_FTM_CTL_8822B 0x07CC\n#define REG_WMAC_IQ_MDPK_FUNC_8822B 0x07CE\n#define REG_WMAC_OPTION_FUNCTION_8822B 0x07D0\n#define REG_RX_FILTER_FUNCTION_8822B 0x07DA\n#define REG_NDP_SIG_8822B 0x07E0\n#define REG_TXCMD_INFO_FOR_RSP_PKT_8822B 0x07E4\n#define REG_RTS_ADDRESS_0_8822B 0x07F0\n#define REG_RTS_ADDRESS_1_8822B 0x07F8\n#define REG__RPFM_MAP1_8822B 0x07FE\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822B 0x1700\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822B 0x1704\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822B 0x1708\n#define REG_SDIO_TX_CTRL_8822B 0x10250000\n#define REG_SDIO_HIMR_8822B 0x10250014\n#define REG_SDIO_HISR_8822B 0x10250018\n#define REG_SDIO_RX_REQ_LEN_8822B 0x1025001C\n#define REG_SDIO_FREE_TXPG_SEQ_V1_8822B 0x1025001F\n#define REG_SDIO_FREE_TXPG_8822B 0x10250020\n#define REG_SDIO_FREE_TXPG2_8822B 0x10250024\n#define REG_SDIO_OQT_FREE_TXPG_V1_8822B 0x10250028\n#define REG_SDIO_HTSFR_INFO_8822B 0x10250030\n#define REG_SDIO_HCPWM1_V2_8822B 0x10250038\n#define REG_SDIO_HCPWM2_V2_8822B 0x1025003A\n#define REG_SDIO_INDIRECT_REG_CFG_8822B 0x10250040\n#define REG_SDIO_INDIRECT_REG_DATA_8822B 0x10250044\n#define REG_SDIO_H2C_8822B 0x10250060\n#define REG_SDIO_C2H_8822B 0x10250064\n#define REG_SDIO_HRPWM1_8822B 0x10250080\n#define REG_SDIO_HRPWM2_8822B 0x10250082\n#define REG_SDIO_HPS_CLKR_8822B 0x10250084\n#define REG_SDIO_BUS_CTRL_8822B 0x10250085\n#define REG_SDIO_HSUS_CTRL_8822B 0x10250086\n#define REG_SDIO_RESPONSE_TIMER_8822B 0x10250088\n#define REG_SDIO_CMD_CRC_8822B 0x1025008A\n#define REG_SDIO_HSISR_8822B 0x10250090\n#define REG_SDIO_ERR_RPT_8822B 0x102500C0\n#define REG_SDIO_CMD_ERRCNT_8822B 0x102500C2\n#define REG_SDIO_DATA_ERRCNT_8822B 0x102500C3\n#define REG_SDIO_CMD_ERR_CONTENT_8822B 0x102500C4\n#define REG_SDIO_CRC_ERR_IDX_8822B 0x102500C9\n#define REG_SDIO_DATA_CRC_8822B 0x102500CA\n#define REG_SDIO_DATA_REPLY_TIME_8822B 0x102500CB\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_reg_8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef __INC_HALMAC_REG_8822C_H\n#define __INC_HALMAC_REG_8822C_H\n\n#define REG_SYS_ISO_CTRL_8822C 0x0000\n#define REG_SYS_FUNC_EN_8822C 0x0002\n#define REG_SYS_PW_CTRL_8822C 0x0004\n#define REG_SYS_CLK_CTRL_8822C 0x0008\n#define REG_SYS_EEPROM_CTRL_8822C 0x000A\n#define REG_EE_VPD_8822C 0x000C\n#define REG_SYS_SWR_CTRL1_8822C 0x0010\n#define REG_SYS_SWR_CTRL2_8822C 0x0014\n#define REG_SYS_SWR_CTRL3_8822C 0x0018\n#define REG_RSV_CTRL_8822C 0x001C\n#define REG_RF_CTRL_8822C 0x001F\n#define REG_AFE_LDO_CTRL_8822C 0x0020\n#define REG_AFE_CTRL1_8822C 0x0024\n#define REG_ANAPARSW_POW_MAC_8822C 0x0028\n#define REG_ANAPARLDO_POW_MAC_8822C 0x0029\n#define REG_ANAPAR_POW_MAC_8822C 0x002A\n#define REG_ANAPAR_POW_XTAL_8822C 0x002B\n#define REG_ANAPARLDO_MAC_8822C 0x002C\n#define REG_EFUSE_CTRL_8822C 0x0030\n#define REG_LDO_EFUSE_CTRL_8822C 0x0034\n#define REG_PWR_OPTION_CTRL_8822C 0x0038\n#define REG_CAL_TIMER_8822C 0x003C\n#define REG_ACLK_MON_8822C 0x003E\n#define REG_GPIO_MUXCFG_2_8822C 0x003F\n#define REG_GPIO_MUXCFG_8822C 0x0040\n#define REG_GPIO_PIN_CTRL_8822C 0x0044\n#define REG_GPIO_INTM_8822C 0x0048\n#define REG_LED_CFG_8822C 0x004C\n#define REG_FSIMR_8822C 0x0050\n#define REG_FSISR_8822C 0x0054\n#define REG_HSIMR_8822C 0x0058\n#define REG_HSISR_8822C 0x005C\n#define REG_GPIO_EXT_CTRL_8822C 0x0060\n#define REG_PAD_CTRL1_8822C 0x0064\n#define REG_WL_BT_PWR_CTRL_8822C 0x0068\n#define REG_SDM_DEBUG_8822C 0x006C\n#define REG_SYS_SDIO_CTRL_8822C 0x0070\n#define REG_HCI_OPT_CTRL_8822C 0x0074\n#define REG_HCI_BG_CTRL_8822C 0x0078\n#define REG_HCI_LDO_CTRL_8822C 0x007A\n#define REG_LDO_SWR_CTRL_8822C 0x007C\n#define REG_MCUFW_CTRL_8822C 0x0080\n#define REG_MCU_TST_CFG_8822C 0x0084\n#define REG_HMEBOX_E0_E1_8822C 0x0088\n#define REG_HMEBOX_E2_E3_8822C 0x008C\n#define REG_WLLPS_CTRL_8822C 0x0090\n#define REG_GPIO_DEBOUNCE_CTRL_8822C 0x0098\n#define REG_RPWM2_8822C 0x009C\n#define REG_SYSON_FSM_MON_8822C 0x00A0\n#define REG_PMC_DBG_CTRL1_8822C 0x00A8\n#define REG_HIMR0_8822C 0x00B0\n#define REG_HISR0_8822C 0x00B4\n#define REG_HIMR1_8822C 0x00B8\n#define REG_HISR1_8822C 0x00BC\n#define REG_DBG_PORT_SEL_8822C 0x00C0\n#define REG_PAD_CTRL2_8822C 0x00C4\n#define REG_PMC_DBG_CTRL2_8822C 0x00CC\n#define REG_BIST_CTRL_8822C 0x00D0\n#define REG_BIST_RPT_8822C 0x00D4\n#define REG_MEM_CTRL_8822C 0x00D8\n#define REG_USB_SIE_INTF_8822C 0x00E0\n#define REG_PCIE_MIO_INTF_8822C 0x00E4\n#define REG_PCIE_MIO_INTD_8822C 0x00E8\n#define REG_WLRF1_8822C 0x00EC\n#define REG_SYS_CFG1_8822C 0x00F0\n#define REG_SYS_STATUS1_8822C 0x00F4\n#define REG_SYS_STATUS2_8822C 0x00F8\n#define REG_SYS_CFG2_8822C 0x00FC\n#define REG_SYS_CFG3_8822C 0x1000\n#define REG_ANAPARSW_MAC_0_8822C 0x1010\n#define REG_ANAPARSW_MAC_1_8822C 0x1014\n#define REG_ANAPAR_MAC_0_8822C 0x1018\n#define REG_ANAPAR_MAC_1_8822C 0x101C\n#define REG_ANAPAR_MAC_2_8822C 0x1020\n#define REG_ANAPAR_XTAL_0_8822C 0x1040\n#define REG_ANAPAR_XTAL_1_8822C 0x1044\n#define REG_ANAPAR_XTAL_2_8822C 0x1048\n#define REG_ANAPAR_XTAL_3_8822C 0x104C\n#define REG_ANAPAR_XTAL_AACK_0_8822C 0x1054\n#define REG_ANAPAR_XTAL_AACK_1_8822C 0x1058\n#define REG_ANAPAR_XTAL_MODE_DECODER_8822C 0x1064\n#define REG_SYS_CFG5_8822C 0x1070\n#define REG_CPU_DMEM_CON_8822C 0x1080\n#define REG_BOOT_REASON_8822C 0x1088\n#define REG_HIMR2_8822C 0x10B0\n#define REG_HISR2_8822C 0x10B4\n#define REG_HIMR3_8822C 0x10B8\n#define REG_HISR3_8822C 0x10BC\n#define REG_SW_MDIO_8822C 0x10C0\n#define REG_H2C_PKT_READADDR_8822C 0x10D0\n#define REG_H2C_PKT_WRITEADDR_8822C 0x10D4\n#define REG_MEM_PWR_CRTL_8822C 0x10D8\n#define REG_FW_DBG6_8822C 0x10F8\n#define REG_FW_DBG7_8822C 0x10FC\n#define REG_CR_8822C 0x0100\n#define REG_PG_SIZE_8822C 0x0104\n#define REG_PKT_BUFF_ACCESS_CTRL_8822C 0x0106\n#define REG_TSF_CLK_STATE_8822C 0x0108\n#define REG_TXDMA_PQ_MAP_8822C 0x010C\n#define REG_TRXFF_BNDY_8822C 0x0114\n#define REG_PTA_I2C_MBOX_8822C 0x0118\n#define REG_RXFF_BNDY_8822C 0x011C\n#define REG_FE1IMR_8822C 0x0120\n#define REG_FE1ISR_8822C 0x0124\n#define REG_CPWM_8822C 0x012C\n#define REG_FWIMR_8822C 0x0130\n#define REG_FWISR_8822C 0x0134\n#define REG_FTIMR_8822C 0x0138\n#define REG_FTISR_8822C 0x013C\n#define REG_PKTBUF_DBG_CTRL_8822C 0x0140\n#define REG_PKTBUF_DBG_DATA_L_8822C 0x0144\n#define REG_PKTBUF_DBG_DATA_H_8822C 0x0148\n#define REG_CPWM2_8822C 0x014C\n#define REG_TC0_CTRL_8822C 0x0150\n#define REG_TC1_CTRL_8822C 0x0154\n#define REG_TC2_CTRL_8822C 0x0158\n#define REG_TC3_CTRL_8822C 0x015C\n#define REG_TC4_CTRL_8822C 0x0160\n#define REG_TCUNIT_BASE_8822C 0x0164\n#define REG_TC5_CTRL_8822C 0x0168\n#define REG_TC6_CTRL_8822C 0x016C\n#define REG_MBIST_DRF_FAIL_8822C 0x0170\n#define REG_MBIST_START_PAUSE_8822C 0x0174\n#define REG_MBIST_DONE_8822C 0x0178\n#define REG_MBIST_READ_BIST_RPT_8822C 0x017C\n#define REG_AES_DECRPT_DATA_8822C 0x0180\n#define REG_AES_DECRPT_CFG_8822C 0x0184\n#define REG_HIOE_CTRL_8822C 0x0188\n#define REG_HIOE_CFG_FILE_8822C 0x018C\n#define REG_TMETER_8822C 0x0190\n#define REG_OSC_32K_CTRL_8822C 0x0194\n#define REG_32K_CAL_REG1_8822C 0x0198\n#define REG_C2HEVT_8822C 0x01A0\n#define REG_C2HEVT_1_8822C 0x01A4\n#define REG_C2HEVT_2_8822C 0x01A8\n#define REG_C2HEVT_3_8822C 0x01AC\n#define REG_SW_DEFINED_PAGE1_8822C 0x01B8\n#define REG_SW_DEFINED_PAGE2_8822C 0x01BC\n#define REG_MCUTST_I_8822C 0x01C0\n#define REG_MCUTST_II_8822C 0x01C4\n#define REG_FMETHR_8822C 0x01C8\n#define REG_HMETFR_8822C 0x01CC\n#define REG_HMEBOX0_8822C 0x01D0\n#define REG_HMEBOX1_8822C 0x01D4\n#define REG_HMEBOX2_8822C 0x01D8\n#define REG_HMEBOX3_8822C 0x01DC\n#define REG_BB_ACCESS_CTRL_8822C 0x01E8\n#define REG_BB_ACCESS_DATA_8822C 0x01EC\n#define REG_HMEBOX_E0_8822C 0x01F0\n#define REG_HMEBOX_E1_8822C 0x01F4\n#define REG_HMEBOX_E2_8822C 0x01F8\n#define REG_HMEBOX_E3_8822C 0x01FC\n#define REG_CR_EXT_8822C 0x1100\n#define REG_FWFF_8822C 0x1114\n#define REG_RXFF_PTR_V1_8822C 0x1118\n#define REG_RXFF_WTR_V1_8822C 0x111C\n#define REG_FE2IMR_8822C 0x1120\n#define REG_FE2ISR_8822C 0x1124\n#define REG_FE3IMR_8822C 0x1128\n#define REG_FE3ISR_8822C 0x112C\n#define REG_FE4IMR_8822C 0x1130\n#define REG_FE4ISR_8822C 0x1134\n#define REG_FT1IMR_8822C 0x1138\n#define REG_FT1ISR_8822C 0x113C\n#define REG_SPWR0_8822C 0x1140\n#define REG_SPWR1_8822C 0x1144\n#define REG_SPWR2_8822C 0x1148\n#define REG_SPWR3_8822C 0x114C\n#define REG_POWSEQ_8822C 0x1150\n#define REG_TC7_CTRL_V1_8822C 0x1158\n#define REG_TC8_CTRL_V1_8822C 0x115C\n#define REG_RX_BCN_TBTT_ITVL0_8822C 0x1160\n#define REG_RX_BCN_TBTT_ITVL1_8822C 0x1164\n#define REG_IO_WRAP_ERR_FLAG_8822C 0x1170\n#define REG_SPEED_SENSOR_8822C 0x1180\n#define REG_SPEED_SENSOR1_8822C 0x1184\n#define REG_SPEED_SENSOR2_8822C 0x1188\n#define REG_SPEED_SENSOR3_8822C 0x118C\n#define REG_SPEED_SENSOR4_8822C 0x1190\n#define REG_SPEED_SENSOR5_8822C 0x1194\n#define REG_COUNTER_CTRL_8822C 0x11C4\n#define REG_COUNTER_THRESHOLD_8822C 0x11C8\n#define REG_COUNTER_SET_8822C 0x11CC\n#define REG_COUNTER_OVERFLOW_8822C 0x11D0\n#define REG_TXDMA_LEN_THRESHOLD_8822C 0x11D4\n#define REG_RXDMA_LEN_THRESHOLD_8822C 0x11D8\n#define REG_PCIE_EXEC_TIME_THRESHOLD_8822C 0x11DC\n#define REG_FT2IMR_8822C 0x11E0\n#define REG_FT2ISR_8822C 0x11E4\n#define REG_MSG2_8822C 0x11F0\n#define REG_MSG3_8822C 0x11F4\n#define REG_MSG4_8822C 0x11F8\n#define REG_MSG5_8822C 0x11FC\n#define REG_FIFOPAGE_CTRL_1_8822C 0x0200\n#define REG_FIFOPAGE_CTRL_2_8822C 0x0204\n#define REG_AUTO_LLT_V1_8822C 0x0208\n#define REG_TXDMA_OFFSET_CHK_8822C 0x020C\n#define REG_TXDMA_STATUS_8822C 0x0210\n#define REG_TX_DMA_DBG_8822C 0x0214\n#define REG_TQPNT1_8822C 0x0218\n#define REG_TQPNT2_8822C 0x021C\n#define REG_TQPNT3_8822C 0x0220\n#define REG_TQPNT4_8822C 0x0224\n#define REG_RQPN_CTRL_1_8822C 0x0228\n#define REG_RQPN_CTRL_2_8822C 0x022C\n#define REG_FIFOPAGE_INFO_1_8822C 0x0230\n#define REG_FIFOPAGE_INFO_2_8822C 0x0234\n#define REG_FIFOPAGE_INFO_3_8822C 0x0238\n#define REG_FIFOPAGE_INFO_4_8822C 0x023C\n#define REG_FIFOPAGE_INFO_5_8822C 0x0240\n#define REG_H2C_HEAD_8822C 0x0244\n#define REG_H2C_TAIL_8822C 0x0248\n#define REG_H2C_READ_ADDR_8822C 0x024C\n#define REG_H2C_WR_ADDR_8822C 0x0250\n#define REG_H2C_INFO_8822C 0x0254\n#define REG_PGSUB_CNT_8822C 0x026C\n#define REG_PGSUB_H_8822C 0x0270\n#define REG_PGSUB_N_8822C 0x0274\n#define REG_PGSUB_L_8822C 0x0278\n#define REG_PGSUB_E_8822C 0x027C\n#define REG_RXDMA_AGG_PG_TH_8822C 0x0280\n#define REG_RXPKT_NUM_8822C 0x0284\n#define REG_RXDMA_STATUS_8822C 0x0288\n#define REG_RXDMA_DPR_8822C 0x028C\n#define REG_RXDMA_MODE_8822C 0x0290\n#define REG_C2H_PKT_8822C 0x0294\n#define REG_FWFF_C2H_8822C 0x0298\n#define REG_FWFF_CTRL_8822C 0x029C\n#define REG_FWFF_PKT_INFO_8822C 0x02A0\n#define REG_RXPKTNUM_8822C 0x02B0\n#define REG_RXPKTNUM_TH_8822C 0x02B4\n#define REG_FW_MSG1_8822C 0x02E0\n#define REG_FW_MSG2_8822C 0x02E4\n#define REG_FW_MSG3_8822C 0x02E8\n#define REG_FW_MSG4_8822C 0x02EC\n#define REG_DDMA_CH0SA_8822C 0x1200\n#define REG_DDMA_CH0DA_8822C 0x1204\n#define REG_DDMA_CH0CTRL_8822C 0x1208\n#define REG_DDMA_CH1SA_8822C 0x1210\n#define REG_DDMA_CH1DA_8822C 0x1214\n#define REG_DDMA_CH1CTRL_8822C 0x1218\n#define REG_DDMA_CH2SA_8822C 0x1220\n#define REG_DDMA_CH2DA_8822C 0x1224\n#define REG_DDMA_CH2CTRL_8822C 0x1228\n#define REG_DDMA_CH3SA_8822C 0x1230\n#define REG_DDMA_CH3DA_8822C 0x1234\n#define REG_DDMA_CH3CTRL_8822C 0x1238\n#define REG_DDMA_CH4SA_8822C 0x1240\n#define REG_DDMA_CH4DA_8822C 0x1244\n#define REG_DDMA_CH4CTRL_8822C 0x1248\n#define REG_DDMA_CH5SA_8822C 0x1250\n#define REG_DDMA_CH5DA_8822C 0x1254\n#define REG_DDMA_CH5CTRL_8822C 0x1258\n#define REG_DDMA_INT_MSK_8822C 0x12E0\n#define REG_DDMA_CHSTATUS_8822C 0x12E8\n#define REG_DDMA_CHKSUM_8822C 0x12F0\n#define REG_DDMA_MONITOR_8822C 0x12FC\n#define REG_PCIE_CTRL_8822C 0x0300\n#define REG_INT_MIG_8822C 0x0304\n#define REG_BCNQ_TXBD_DESA_8822C 0x0308\n#define REG_MGQ_TXBD_DESA_8822C 0x0310\n#define REG_VOQ_TXBD_DESA_8822C 0x0318\n#define REG_VIQ_TXBD_DESA_8822C 0x0320\n#define REG_BEQ_TXBD_DESA_8822C 0x0328\n#define REG_BKQ_TXBD_DESA_8822C 0x0330\n#define REG_RXQ_RXBD_DESA_8822C 0x0338\n#define REG_HI0Q_TXBD_DESA_8822C 0x0340\n#define REG_HI1Q_TXBD_DESA_8822C 0x0348\n#define REG_HI2Q_TXBD_DESA_8822C 0x0350\n#define REG_HI3Q_TXBD_DESA_8822C 0x0358\n#define REG_HI4Q_TXBD_DESA_8822C 0x0360\n#define REG_HI5Q_TXBD_DESA_8822C 0x0368\n#define REG_HI6Q_TXBD_DESA_8822C 0x0370\n#define REG_HI7Q_TXBD_DESA_8822C 0x0378\n#define REG_MGQ_TXBD_NUM_8822C 0x0380\n#define REG_RX_RXBD_NUM_8822C 0x0382\n#define REG_VOQ_TXBD_NUM_8822C 0x0384\n#define REG_VIQ_TXBD_NUM_8822C 0x0386\n#define REG_BEQ_TXBD_NUM_8822C 0x0388\n#define REG_BKQ_TXBD_NUM_8822C 0x038A\n#define REG_HI0Q_TXBD_NUM_8822C 0x038C\n#define REG_HI1Q_TXBD_NUM_8822C 0x038E\n#define REG_HI2Q_TXBD_NUM_8822C 0x0390\n#define REG_HI3Q_TXBD_NUM_8822C 0x0392\n#define REG_HI4Q_TXBD_NUM_8822C 0x0394\n#define REG_HI5Q_TXBD_NUM_8822C 0x0396\n#define REG_HI6Q_TXBD_NUM_8822C 0x0398\n#define REG_HI7Q_TXBD_NUM_8822C 0x039A\n#define REG_TSFTIMER_HCI_8822C 0x039C\n#define REG_BD_RWPTR_CLR_8822C 0x039C\n#define REG_VOQ_TXBD_IDX_8822C 0x03A0\n#define REG_VIQ_TXBD_IDX_8822C 0x03A4\n#define REG_BEQ_TXBD_IDX_8822C 0x03A8\n#define REG_BKQ_TXBD_IDX_8822C 0x03AC\n#define REG_MGQ_TXBD_IDX_8822C 0x03B0\n#define REG_RXQ_RXBD_IDX_8822C 0x03B4\n#define REG_HI0Q_TXBD_IDX_8822C 0x03B8\n#define REG_HI1Q_TXBD_IDX_8822C 0x03BC\n#define REG_HI2Q_TXBD_IDX_8822C 0x03C0\n#define REG_HI3Q_TXBD_IDX_8822C 0x03C4\n#define REG_HI4Q_TXBD_IDX_8822C 0x03C8\n#define REG_HI5Q_TXBD_IDX_8822C 0x03CC\n#define REG_HI6Q_TXBD_IDX_8822C 0x03D0\n#define REG_HI7Q_TXBD_IDX_8822C 0x03D4\n#define REG_DBG_SEL_V1_8822C 0x03D8\n#define REG_PCIE_HRPWM1_V1_8822C 0x03D9\n#define REG_PCIE_HCPWM1_V1_8822C 0x03DA\n#define REG_PCIE_CTRL2_8822C 0x03DB\n#define REG_PCIE_HRPWM2_V1_8822C 0x03DC\n#define REG_PCIE_HCPWM2_V1_8822C 0x03DE\n#define REG_PCIE_H2C_MSG_V1_8822C 0x03E0\n#define REG_PCIE_C2H_MSG_V1_8822C 0x03E4\n#define REG_DBI_WDATA_V1_8822C 0x03E8\n#define REG_DBI_RDATA_V1_8822C 0x03EC\n#define REG_DBI_FLAG_V1_8822C 0x03F0\n#define REG_MDIO_V1_8822C 0x03F4\n#define REG_PCIE_MIX_CFG_8822C 0x03F8\n#define REG_HCI_MIX_CFG_8822C 0x03FC\n#define REG_STC_INT_CS_8822C 0x1300\n#define REG_ST_INT_CFG_8822C 0x1304\n#define REG_H2CQ_TXBD_DESA_8822C 0x1320\n#define REG_H2CQ_TXBD_NUM_8822C 0x1328\n#define REG_H2CQ_TXBD_IDX_8822C 0x132C\n#define REG_H2CQ_CSR_8822C 0x1330\n#define REG_CHANGE_PCIE_SPEED_8822C 0x1350\n#define REG_DEBUG_STATE1_8822C 0x1354\n#define REG_DEBUG_STATE2_8822C 0x1358\n#define REG_DEBUG_STATE3_8822C 0x135C\n#define REG_CHNL_DMA_CFG_V1_8822C 0x137C\n#define REG_PCIE_HISR0_V1_8822C 0x13B4\n#define REG_PCIE_HISR1_V1_8822C 0x13BC\n#define REG_PCIE_HISR2_V1_8822C 0x23B4\n#define REG_PCIE_HISR3_V1_8822C 0x23BC\n#define REG_Q0_INFO_8822C 0x0400\n#define REG_Q1_INFO_8822C 0x0404\n#define REG_Q2_INFO_8822C 0x0408\n#define REG_Q3_INFO_8822C 0x040C\n#define REG_MGQ_INFO_8822C 0x0410\n#define REG_HIQ_INFO_8822C 0x0414\n#define REG_BCNQ_INFO_8822C 0x0418\n#define REG_TXPKT_EMPTY_8822C 0x041A\n#define REG_CPU_MGQ_INFO_8822C 0x041C\n#define REG_FWHW_TXQ_CTRL_8822C 0x0420\n#define REG_DATAFB_SEL_8822C 0x0423\n#define REG_BCNQ_BDNY_V1_8822C 0x0424\n#define REG_LIFETIME_EN_8822C 0x0426\n#define REG_SPEC_SIFS_8822C 0x0428\n#define REG_RETRY_LIMIT_8822C 0x042A\n#define REG_TXBF_CTRL_8822C 0x042C\n#define REG_DARFRC_8822C 0x0430\n#define REG_DARFRCH_8822C 0x0434\n#define REG_RARFRC_8822C 0x0438\n#define REG_RARFRCH_8822C 0x043C\n#define REG_RRSR_8822C 0x0440\n#define REG_ARFR0_8822C 0x0444\n#define REG_ARFRH0_8822C 0x0448\n#define REG_ARFR1_V1_8822C 0x044C\n#define REG_ARFRH1_V1_8822C 0x0450\n#define REG_CCK_CHECK_8822C 0x0454\n#define REG_AMPDU_MAX_TIME_V1_8822C 0x0455\n#define REG_BCNQ1_BDNY_V1_8822C 0x0456\n#define REG_AMPDU_MAX_LENGTH_HT_8822C 0x0458\n#define REG_ACQ_STOP_8822C 0x045C\n#define REG_NDPA_RATE_8822C 0x045D\n#define REG_TX_HANG_CTRL_8822C 0x045E\n#define REG_NDPA_OPT_CTRL_8822C 0x045F\n#define REG_AMPDU_MAX_LENGTH_VHT_8822C 0x0460\n#define REG_RD_RESP_PKT_TH_8822C 0x0463\n#define REG_CMDQ_INFO_8822C 0x0464\n#define REG_Q4_INFO_8822C 0x0468\n#define REG_Q5_INFO_8822C 0x046C\n#define REG_Q6_INFO_8822C 0x0470\n#define REG_Q7_INFO_8822C 0x0474\n#define REG_WMAC_LBK_BUF_HD_V1_8822C 0x0478\n#define REG_MGQ_BDNY_V1_8822C 0x047A\n#define REG_TXRPT_CTRL_8822C 0x047C\n#define REG_INIRTS_RATE_SEL_8822C 0x0480\n#define REG_BASIC_CFEND_RATE_8822C 0x0481\n#define REG_STBC_CFEND_RATE_8822C 0x0482\n#define REG_DATA_SC_8822C 0x0483\n#define REG_MACID_SLEEP3_8822C 0x0484\n#define REG_MACID_SLEEP1_8822C 0x0488\n#define REG_ARFR2_V1_8822C 0x048C\n#define REG_ARFRH2_V1_8822C 0x0490\n#define REG_ARFR3_V1_8822C 0x0494\n#define REG_ARFRH3_V1_8822C 0x0498\n#define REG_ARFR4_8822C 0x049C\n#define REG_ARFRH4_8822C 0x04A0\n#define REG_ARFR5_8822C 0x04A4\n#define REG_ARFRH5_8822C 0x04A8\n#define REG_TXRPT_START_OFFSET_8822C 0x04AC\n#define REG_POWER_STAGE1_8822C 0x04B4\n#define REG_POWER_STAGE2_8822C 0x04B8\n#define REG_SW_AMPDU_BURST_MODE_CTRL_8822C 0x04BC\n#define REG_PKT_LIFE_TIME_8822C 0x04C0\n#define REG_STBC_SETTING_8822C 0x04C4\n#define REG_STBC_SETTING2_8822C 0x04C5\n#define REG_QUEUE_CTRL_8822C 0x04C6\n#define REG_SINGLE_AMPDU_CTRL_8822C 0x04C7\n#define REG_PROT_MODE_CTRL_8822C 0x04C8\n#define REG_BAR_MODE_CTRL_8822C 0x04CC\n#define REG_RA_TRY_RATE_AGG_LMT_8822C 0x04CF\n#define REG_MACID_SLEEP2_8822C 0x04D0\n#define REG_MACID_SLEEP_8822C 0x04D4\n#define REG_HW_SEQ0_8822C 0x04D8\n#define REG_HW_SEQ1_8822C 0x04DA\n#define REG_HW_SEQ2_8822C 0x04DC\n#define REG_HW_SEQ3_8822C 0x04DE\n#define REG_NULL_PKT_STATUS_V1_8822C 0x04E0\n#define REG_PTCL_ERR_STATUS_8822C 0x04E2\n#define REG_NULL_PKT_STATUS_EXTEND_8822C 0x04E3\n#define REG_HQMGQ_DROP_8822C 0x04E4\n#define REG_PRECNT_CTRL_8822C 0x04E5\n#define REG_BT_POLLUTE_PKT_CNT_8822C 0x04E8\n#define REG_PTCL_DBG_8822C 0x04EC\n#define REG_CPUMGQ_TIMER_CTRL2_8822C 0x04F4\n#define REG_DUMMY_PAGE4_V1_8822C 0x04FC\n#define REG_MOREDATA_8822C 0x04FE\n#define REG_Q0_Q1_INFO_8822C 0x1400\n#define REG_Q2_Q3_INFO_8822C 0x1404\n#define REG_Q4_Q5_INFO_8822C 0x1408\n#define REG_Q6_Q7_INFO_8822C 0x140C\n#define REG_MGQ_HIQ_INFO_8822C 0x1410\n#define REG_CMDQ_BCNQ_INFO_8822C 0x1414\n#define REG_LOOPBACK_OPTION_8822C 0x1420\n#define REG_AESIV_SETTING_8822C 0x1424\n#define REG_BF0_TIME_SETTING_8822C 0x1428\n#define REG_BF1_TIME_SETTING_8822C 0x142C\n#define REG_BF_TIMEOUT_EN_8822C 0x1430\n#define REG_MACID_RELEASE0_8822C 0x1434\n#define REG_MACID_RELEASE1_8822C 0x1438\n#define REG_MACID_RELEASE2_8822C 0x143C\n#define REG_MACID_RELEASE3_8822C 0x1440\n#define REG_MACID_RELEASE_SETTING_8822C 0x1444\n#define REG_FAST_EDCA_VOVI_SETTING_8822C 0x1448\n#define REG_FAST_EDCA_BEBK_SETTING_8822C 0x144C\n#define REG_MACID_DROP0_8822C 0x1450\n#define REG_MACID_DROP1_8822C 0x1454\n#define REG_MACID_DROP2_8822C 0x1458\n#define REG_MACID_DROP3_8822C 0x145C\n#define REG_R_MACID_RELEASE_SUCCESS_0_8822C 0x1460\n#define REG_R_MACID_RELEASE_SUCCESS_1_8822C 0x1464\n#define REG_R_MACID_RELEASE_SUCCESS_2_8822C 0x1468\n#define REG_R_MACID_RELEASE_SUCCESS_3_8822C 0x146C\n#define REG_MGQ_FIFO_WRITE_POINTER_8822C 0x1470\n#define REG_MGQ_FIFO_READ_POINTER_8822C 0x1472\n#define REG_MGQ_FIFO_ENABLE_8822C 0x1472\n#define REG_MGQ_FIFO_RELEASE_INT_MASK_8822C 0x1474\n#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8822C 0x1476\n#define REG_MGQ_FIFO_VALID_MAP_8822C 0x1478\n#define REG_MGQ_FIFO_LIFETIME_8822C 0x147A\n#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C 0x147C\n#define REG_SHCUT_SETTING_8822C 0x1480\n#define REG_SHCUT_LLC_ETH_TYPE0_8822C 0x1484\n#define REG_SHCUT_LLC_ETH_TYPE1_8822C 0x1488\n#define REG_SHCUT_LLC_OUI0_8822C 0x148C\n#define REG_SHCUT_LLC_OUI1_8822C 0x1490\n#define REG_SHCUT_LLC_OUI2_8822C 0x1494\n#define REG_MU_TX_CTL_8822C 0x14C0\n#define REG_MU_STA_GID_VLD_8822C 0x14C4\n#define REG_MU_STA_USER_POS_INFO_8822C 0x14C8\n#define REG_MU_STA_USER_POS_INFO_H_8822C 0x14CC\n#define REG_CHNL_INFO_CTRL_8822C 0x14D0\n#define REG_CHNL_IDLE_TIME_8822C 0x14D4\n#define REG_CHNL_BUSY_TIME_8822C 0x14D8\n#define REG_MU_TRX_DBG_CNT_V1_8822C 0x14DC\n#define REG_EDCA_VO_PARAM_8822C 0x0500\n#define REG_EDCA_VI_PARAM_8822C 0x0504\n#define REG_EDCA_BE_PARAM_8822C 0x0508\n#define REG_EDCA_BK_PARAM_8822C 0x050C\n#define REG_BCNTCFG_8822C 0x0510\n#define REG_PIFS_8822C 0x0512\n#define REG_RDG_PIFS_8822C 0x0513\n#define REG_SIFS_8822C 0x0514\n#define REG_TSFTR_SYN_OFFSET_8822C 0x0518\n#define REG_AGGR_BREAK_TIME_8822C 0x051A\n#define REG_SLOT_8822C 0x051B\n#define REG_NOA_ON_ERLY_TIME_8822C 0x051C\n#define REG_NOA_OFF_ERLY_TIME_8822C 0x051D\n#define REG_TX_PTCL_CTRL_8822C 0x0520\n#define REG_TXPAUSE_8822C 0x0522\n#define REG_DIS_TXREQ_CLR_8822C 0x0523\n#define REG_RD_CTRL_8822C 0x0524\n#define REG_MBSSID_CTRL_8822C 0x0526\n#define REG_P2PPS_CTRL_8822C 0x0527\n#define REG_PKT_LIFETIME_CTRL_8822C 0x0528\n#define REG_P2PPS_SPEC_STATE_8822C 0x052B\n#define REG_TXOP_LIMIT_CTRL_8822C 0x052C\n#define REG_BAR_TX_CTRL_8822C 0x0530\n#define REG_P2PON_DIS_TXTIME_8822C 0x0531\n#define REG_CCA_TXEN_CNT_8822C 0x0534\n#define REG_MAX_INTER_COLLISION_8822C 0x0538\n#define REG_MAX_INTER_COLLISION_CNT_8822C 0x053C\n#define REG_TBTT_PROHIBIT_8822C 0x0540\n#define REG_P2PPS_STATE_8822C 0x0543\n#define REG_RD_NAV_NXT_8822C 0x0544\n#define REG_NAV_PROT_LEN_8822C 0x0546\n#define REG_FTM_PTT_8822C 0x0548\n#define REG_FTM_TSF_8822C 0x054C\n#define REG_BCN_CTRL_8822C 0x0550\n#define REG_BCN_CTRL_CLINT0_8822C 0x0551\n#define REG_MBID_NUM_8822C 0x0552\n#define REG_DUAL_TSF_RST_8822C 0x0553\n#define REG_MBSSID_BCN_SPACE_8822C 0x0554\n#define REG_DRVERLYINT_8822C 0x0558\n#define REG_BCNDMATIM_8822C 0x0559\n#define REG_ATIMWND_8822C 0x055A\n#define REG_USTIME_TSF_8822C 0x055C\n#define REG_BCN_MAX_ERR_8822C 0x055D\n#define REG_RXTSF_OFFSET_CCK_8822C 0x055E\n#define REG_RXTSF_OFFSET_OFDM_8822C 0x055F\n#define REG_TSFTR_8822C 0x0560\n#define REG_TSFTR_1_8822C 0x0564\n#define REG_FREERUN_CNT_8822C 0x0568\n#define REG_FREERUN_CNT_1_8822C 0x056C\n#define REG_ATIMWND1_V1_8822C 0x0570\n#define REG_TBTT_PROHIBIT_INFRA_8822C 0x0571\n#define REG_CTWND_8822C 0x0572\n#define REG_BCNIVLCUNT_8822C 0x0573\n#define REG_BCNDROPCTRL_8822C 0x0574\n#define REG_HGQ_TIMEOUT_PERIOD_8822C 0x0575\n#define REG_TXCMD_TIMEOUT_PERIOD_8822C 0x0576\n#define REG_MISC_CTRL_8822C 0x0577\n#define REG_BCN_CTRL_CLINT1_8822C 0x0578\n#define REG_BCN_CTRL_CLINT2_8822C 0x0579\n#define REG_BCN_CTRL_CLINT3_8822C 0x057A\n#define REG_EXTEND_CTRL_8822C 0x057B\n#define REG_P2PPS1_SPEC_STATE_8822C 0x057C\n#define REG_P2PPS1_STATE_8822C 0x057D\n#define REG_P2PPS2_SPEC_STATE_8822C 0x057E\n#define REG_P2PPS2_STATE_8822C 0x057F\n#define REG_PS_TIMER0_8822C 0x0580\n#define REG_PS_TIMER1_8822C 0x0584\n#define REG_PS_TIMER2_8822C 0x0588\n#define REG_TBTT_CTN_AREA_8822C 0x058C\n#define REG_FORCE_BCN_IFS_8822C 0x058E\n#define REG_TXOP_MIN_8822C 0x0590\n#define REG_PRE_BKF_TIME_8822C 0x0592\n#define REG_CROSS_TXOP_CTRL_8822C 0x0593\n#define REG_RX_TBTT_SHIFT_V1_8822C 0x0598\n#define REG_ATIMWND2_8822C 0x05A0\n#define REG_ATIMWND3_8822C 0x05A1\n#define REG_ATIMWND4_8822C 0x05A2\n#define REG_ATIMWND5_8822C 0x05A3\n#define REG_ATIMWND6_8822C 0x05A4\n#define REG_ATIMWND7_8822C 0x05A5\n#define REG_ATIMUGT_8822C 0x05A6\n#define REG_HIQ_NO_LMT_EN_8822C 0x05A7\n#define REG_DTIM_COUNTER_ROOT_8822C 0x05A8\n#define REG_DTIM_COUNTER_VAP1_8822C 0x05A9\n#define REG_DTIM_COUNTER_VAP2_8822C 0x05AA\n#define REG_DTIM_COUNTER_VAP3_8822C 0x05AB\n#define REG_DTIM_COUNTER_VAP4_8822C 0x05AC\n#define REG_DTIM_COUNTER_VAP5_8822C 0x05AD\n#define REG_DTIM_COUNTER_VAP6_8822C 0x05AE\n#define REG_DTIM_COUNTER_VAP7_8822C 0x05AF\n#define REG_DIS_ATIM_8822C 0x05B0\n#define REG_EARLY_128US_8822C 0x05B1\n#define REG_P2PPS1_CTRL_8822C 0x05B2\n#define REG_P2PPS2_CTRL_8822C 0x05B3\n#define REG_TIMER0_SRC_SEL_8822C 0x05B4\n#define REG_NOA_UNIT_SEL_8822C 0x05B5\n#define REG_P2POFF_DIS_TXTIME_8822C 0x05B7\n#define REG_MBSSID_BCN_SPACE2_8822C 0x05B8\n#define REG_MBSSID_BCN_SPACE3_8822C 0x05BC\n#define REG_ACMHWCTRL_8822C 0x05C0\n#define REG_ACMRSTCTRL_8822C 0x05C1\n#define REG_ACMAVG_8822C 0x05C2\n#define REG_VO_ADMTIME_8822C 0x05C4\n#define REG_VI_ADMTIME_8822C 0x05C6\n#define REG_BE_ADMTIME_8822C 0x05C8\n#define REG_MAC_HEADER_NAV_OFFSET_8822C 0x05CA\n#define REG_DIS_NDPA_NAV_CHECK_8822C 0x05CB\n#define REG_EDCA_RANDOM_GEN_8822C 0x05CC\n#define REG_TXCMD_NOA_SEL_8822C 0x05CF\n#define REG_32K_CLK_SEL_8822C 0x05D0\n#define REG_EARLYINT_ADJUST_8822C 0x05D4\n#define REG_BCNERR_CNT_8822C 0x05D8\n#define REG_BCNERR_CNT_2_8822C 0x05DC\n#define REG_NOA_PARAM_8822C 0x05E0\n#define REG_NOA_PARAM_1_8822C 0x05E4\n#define REG_NOA_PARAM_2_8822C 0x05E8\n#define REG_NOA_PARAM_3_8822C 0x05EC\n#define REG_P2P_RST_8822C 0x05F0\n#define REG_SCHEDULER_RST_8822C 0x05F1\n#define REG_SCH_DBG_VALUE_8822C 0x05F4\n#define REG_SCH_TXCMD_8822C 0x05F8\n#define REG_PAGE5_DUMMY_8822C 0x05FC\n#define REG_CPUMGQ_TX_TIMER_8822C 0x1500\n#define REG_PS_TIMER_A_8822C 0x1504\n#define REG_PS_TIMER_B_8822C 0x1508\n#define REG_PS_TIMER_C_8822C 0x150C\n#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822C 0x1510\n#define REG_CPUMGQ_TX_TIMER_EARLY_8822C 0x1514\n#define REG_PS_TIMER_A_EARLY_8822C 0x1515\n#define REG_PS_TIMER_B_EARLY_8822C 0x1516\n#define REG_PS_TIMER_C_EARLY_8822C 0x1517\n#define REG_CPUMGQ_PARAMETER_8822C 0x1518\n#define REG_TSF_SYNC_ADJ_8822C 0x1520\n#define REG_TSF_ADJ_VLAUE_8822C 0x1524\n#define REG_TSF_ADJ_VLAUE_2_8822C 0x1528\n#define REG_P2PPS_HW_AUTO_PAUSE_CTRL_8822C 0x156C\n#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8822C 0x1570\n#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8822C 0x1574\n#define REG_SCHEDULER_COUNTER_8822C 0x15D0\n#define REG_WMAC_CR_8822C 0x0600\n#define REG_WMAC_FWPKT_CR_8822C 0x0601\n#define REG_FW_STS_FILTER_8822C 0x0602\n#define REG_TCR_8822C 0x0604\n#define REG_RCR_8822C 0x0608\n#define REG_RX_PKT_LIMIT_8822C 0x060C\n#define REG_RX_DLK_TIME_8822C 0x060D\n#define REG_RX_DRVINFO_SZ_8822C 0x060F\n#define REG_MACID_8822C 0x0610\n#define REG_MACID_H_8822C 0x0614\n#define REG_BSSID_8822C 0x0618\n#define REG_BSSID_H_8822C 0x061C\n#define REG_MAR_8822C 0x0620\n#define REG_MAR_H_8822C 0x0624\n#define REG_MBIDCAMCFG_1_8822C 0x0628\n#define REG_MBIDCAMCFG_2_8822C 0x062C\n#define REG_WMAC_TCR_TSFT_OFS_8822C 0x0630\n#define REG_UDF_THSD_8822C 0x0632\n#define REG_ZLD_NUM_8822C 0x0633\n#define REG_STMP_THSD_8822C 0x0634\n#define REG_WMAC_TXTIMEOUT_8822C 0x0635\n#define REG_USTIME_EDCA_8822C 0x0638\n#define REG_ACKTO_CCK_8822C 0x0639\n#define REG_MAC_SPEC_SIFS_8822C 0x063A\n#define REG_RESP_SIFS_CCK_8822C 0x063C\n#define REG_RESP_SIFS_OFDM_8822C 0x063E\n#define REG_ACKTO_8822C 0x0640\n#define REG_CTS2TO_8822C 0x0641\n#define REG_EIFS_8822C 0x0642\n#define REG_RPFM_MAP0_8822C 0x0644\n#define REG_RPFM_MAP1_V1_8822C 0x0646\n#define REG_RPFM_CAM_CMD_8822C 0x0648\n#define REG_RPFM_CAM_RWD_8822C 0x064C\n#define REG_NAV_CTRL_8822C 0x0650\n#define REG_BACAMCMD_8822C 0x0654\n#define REG_BACAMCONTENT_8822C 0x0658\n#define REG_BACAMCONTENT_H_8822C 0x065C\n#define REG_LBDLY_8822C 0x0660\n#define REG_WMAC_BACAM_RPMEN_8822C 0x0661\n#define REG_TX_RX_8822C 0x0662\n#define REG_WMAC_BITMAP_CTL_8822C 0x0663\n#define REG_RXERR_RPT_8822C 0x0664\n#define REG_WMAC_TRXPTCL_CTL_8822C 0x0668\n#define REG_WMAC_TRXPTCL_CTL_H_8822C 0x066C\n#define REG_CAMCMD_8822C 0x0670\n#define REG_CAMWRITE_8822C 0x0674\n#define REG_CAMREAD_8822C 0x0678\n#define REG_CAMDBG_8822C 0x067C\n#define REG_SECCFG_8822C 0x0680\n#define REG_RXFILTER_CATEGORY_1_8822C 0x0682\n#define REG_RXFILTER_ACTION_1_8822C 0x0683\n#define REG_RXFILTER_CATEGORY_2_8822C 0x0684\n#define REG_RXFILTER_ACTION_2_8822C 0x0685\n#define REG_RXFILTER_CATEGORY_3_8822C 0x0686\n#define REG_RXFILTER_ACTION_3_8822C 0x0687\n#define REG_RXFLTMAP3_8822C 0x0688\n#define REG_RXFLTMAP4_8822C 0x068A\n#define REG_RXFLTMAP5_8822C 0x068C\n#define REG_RXFLTMAP6_8822C 0x068E\n#define REG_WOW_CTRL_8822C 0x0690\n#define REG_NAN_RX_TSF_FILTER_8822C 0x0691\n#define REG_PS_RX_INFO_8822C 0x0692\n#define REG_WMMPS_UAPSD_TID_8822C 0x0693\n#define REG_LPNAV_CTRL_8822C 0x0694\n#define REG_WKFMCAM_CMD_8822C 0x0698\n#define REG_WKFMCAM_RWD_8822C 0x069C\n#define REG_RXFLTMAP0_8822C 0x06A0\n#define REG_RXFLTMAP1_8822C 0x06A2\n#define REG_RXFLTMAP2_8822C 0x06A4\n#define REG_BCN_PSR_RPT_8822C 0x06A8\n#define REG_FLC_RPC_8822C 0x06AC\n#define REG_FLC_RPCT_8822C 0x06AD\n#define REG_FLC_PTS_8822C 0x06AE\n#define REG_FLC_TRPC_8822C 0x06AF\n#define REG_RXPKTMON_CTRL_8822C 0x06B0\n#define REG_STATE_MON_8822C 0x06B4\n#define REG_ERROR_MON_8822C 0x06B8\n#define REG_SEARCH_MACID_8822C 0x06BC\n#define REG_BT_COEX_TABLE_8822C 0x06C0\n#define REG_BT_COEX_TABLE2_8822C 0x06C4\n#define REG_BT_COEX_BREAK_TABLE_8822C 0x06C8\n#define REG_BT_COEX_TABLE_H_8822C 0x06CC\n#define REG_RXCMD_0_8822C 0x06D0\n#define REG_RXCMD_1_8822C 0x06D4\n#define REG_WMAC_RESP_TXINFO_8822C 0x06D8\n#define REG_BBPSF_CTRL_8822C 0x06DC\n#define REG_P2P_RX_BCN_NOA_8822C 0x06E0\n#define REG_ASSOCIATED_BFMER0_INFO_8822C 0x06E4\n#define REG_ASSOCIATED_BFMER0_INFO_H_8822C 0x06E8\n#define REG_ASSOCIATED_BFMER1_INFO_8822C 0x06EC\n#define REG_ASSOCIATED_BFMER1_INFO_H_8822C 0x06F0\n#define REG_TX_CSI_RPT_PARAM_BW20_8822C 0x06F4\n#define REG_TX_CSI_RPT_PARAM_BW40_8822C 0x06F8\n#define REG_CSI_PTR_8822C 0x06FC\n#define REG_BCN_PSR_RPT2_8822C 0x1600\n#define REG_BCN_PSR_RPT3_8822C 0x1604\n#define REG_BCN_PSR_RPT4_8822C 0x1608\n#define REG_A1_ADDR_MASK_8822C 0x160C\n#define REG_RXPSF_CTRL_8822C 0x1610\n#define REG_RXPSF_TYPE_CTRL_8822C 0x1614\n#define REG_CAM_ACCESS_CTRL_8822C 0x1618\n#define REG_HT_SND_REF_RATE_8822C 0x161C\n#define REG_MACID2_8822C 0x1620\n#define REG_MACID2_H_8822C 0x1624\n#define REG_BSSID2_8822C 0x1628\n#define REG_BSSID2_H_8822C 0x162C\n#define REG_MACID3_8822C 0x1630\n#define REG_MACID3_H_8822C 0x1634\n#define REG_BSSID3_8822C 0x1638\n#define REG_BSSID3_H_8822C 0x163C\n#define REG_MACID4_8822C 0x1640\n#define REG_MACID4_H_8822C 0x1644\n#define REG_BSSID4_8822C 0x1648\n#define REG_BSSID4_H_8822C 0x164C\n#define REG_NOA_REPORT_8822C 0x1650\n#define REG_NOA_REPORT_1_8822C 0x1654\n#define REG_NOA_REPORT_2_8822C 0x1658\n#define REG_NOA_REPORT_3_8822C 0x165C\n#define REG_PWRBIT_SETTING_8822C 0x1660\n#define REG_GENERAL_OPTION_8822C 0x1664\n#define REG_CSI_RRSR_8822C 0x1678\n#define REG_MU_BF_OPTION_8822C 0x167C\n#define REG_WMAC_PAUSE_BB_CLR_TH_8822C 0x167D\n#define REG__WMAC_MULBK_BUF_8822C 0x167E\n#define REG_WMAC_MU_OPTION_8822C 0x167F\n#define REG_WMAC_MU_BF_CTL_8822C 0x1680\n#define REG_WMAC_MU_BFRPT_PARA_8822C 0x1682\n#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8822C 0x1684\n#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8822C 0x1686\n#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8822C 0x1688\n#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8822C 0x168A\n#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8822C 0x168C\n#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8822C 0x168E\n#define REG_WMAC_BB_STOP_RX_COUNTER_8822C 0x1690\n#define REG_WMAC_PLCP_MONITOR_8822C 0x1694\n#define REG_WMAC_PLCP_MONITOR_MUTX_8822C 0x1698\n#define REG_WMAC_CSIDMA_CFG_8822C 0x169C\n#define REG_TRANSMIT_ADDRSS_0_8822C 0x16A0\n#define REG_TRANSMIT_ADDRSS_0_H_8822C 0x16A4\n#define REG_TRANSMIT_ADDRSS_1_8822C 0x16A8\n#define REG_TRANSMIT_ADDRSS_1_H_8822C 0x16AC\n#define REG_TRANSMIT_ADDRSS_2_8822C 0x16B0\n#define REG_TRANSMIT_ADDRSS_2_H_8822C 0x16B4\n#define REG_TRANSMIT_ADDRSS_3_8822C 0x16B8\n#define REG_TRANSMIT_ADDRSS_3_H_8822C 0x16BC\n#define REG_TRANSMIT_ADDRSS_4_8822C 0x16C0\n#define REG_TRANSMIT_ADDRSS_4_H_8822C 0x16C4\n#define REG_MACID1_8822C 0x0700\n#define REG_MACID1_1_8822C 0x0704\n#define REG_BSSID1_8822C 0x0708\n#define REG_BSSID1_1_8822C 0x070C\n#define REG_BCN_PSR_RPT1_8822C 0x0710\n#define REG_ASSOCIATED_BFMEE_SEL_8822C 0x0714\n#define REG_SND_PTCL_CTRL_8822C 0x0718\n#define REG_RX_CSI_RPT_INFO_8822C 0x071C\n#define REG_NS_ARP_CTRL_8822C 0x0720\n#define REG_NS_ARP_INFO_8822C 0x0724\n#define REG_BEAMFORMING_INFO_NSARP_V1_8822C 0x0728\n#define REG_BEAMFORMING_INFO_NSARP_8822C 0x072C\n#define REG_IPV6_8822C 0x0730\n#define REG_IPV6_1_8822C 0x0734\n#define REG_IPV6_2_8822C 0x0738\n#define REG_IPV6_3_8822C 0x073C\n#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822C 0x0750\n#define REG_WMAC_SWAES_DIO_B63_B32_8822C 0x0754\n#define REG_WMAC_SWAES_DIO_B95_B64_8822C 0x0758\n#define REG_WMAC_SWAES_DIO_B127_B96_8822C 0x075C\n#define REG_WMAC_SWAES_CFG_8822C 0x0760\n#define REG_BT_COEX_V2_8822C 0x0762\n#define REG_BT_COEX_8822C 0x0764\n#define REG_WLAN_ACT_MASK_CTRL_8822C 0x0768\n#define REG_WLAN_ACT_MASK_CTRL_1_8822C 0x076C\n#define REG_BT_COEX_ENHANCED_INTR_CTRL_8822C 0x076E\n#define REG_BT_ACT_STATISTICS_8822C 0x0770\n#define REG_BT_ACT_STATISTICS_1_8822C 0x0774\n#define REG_BT_STATISTICS_CONTROL_REGISTER_8822C 0x0778\n#define REG_BT_STATUS_REPORT_REGISTER_8822C 0x077C\n#define REG_BT_INTERRUPT_CONTROL_REGISTER_8822C 0x0780\n#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822C 0x0784\n#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822C 0x0785\n#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8822C 0x0788\n#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8822C 0x078C\n#define REG_BT_INTERRUPT_STATUS_REGISTER_8822C 0x078F\n#define REG_BT_TDMA_TIME_REGISTER_8822C 0x0790\n#define REG_BT_ACT_REGISTER_8822C 0x0794\n#define REG_OBFF_CTRL_BASIC_8822C 0x0798\n#define REG_OBFF_CTRL2_TIMER_8822C 0x079C\n#define REG_LTR_CTRL_BASIC_8822C 0x07A0\n#define REG_LTR_CTRL2_TIMER_THRESHOLD_8822C 0x07A4\n#define REG_LTR_IDLE_LATENCY_V1_8822C 0x07A8\n#define REG_LTR_ACTIVE_LATENCY_V1_8822C 0x07AC\n#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822C 0x07B0\n#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8822C 0x07B4\n#define REG_WMAC_PKTCNT_RWD_8822C 0x07B8\n#define REG_WMAC_PKTCNT_CTRL_8822C 0x07BC\n#define REG_IQ_DUMP_8822C 0x07C0\n#define REG_IQ_DUMP_1_8822C 0x07C4\n#define REG_IQ_DUMP_2_8822C 0x07C8\n#define REG_WMAC_FTM_CTL_8822C 0x07CC\n#define REG_WMAC_IQ_MDPK_FUNC_8822C 0x07CE\n#define REG_WMAC_OPTION_FUNCTION_8822C 0x07D0\n#define REG_WMAC_OPTION_FUNCTION_1_8822C 0x07D4\n#define REG_WMAC_OPTION_FUNCTION_2_8822C 0x07D8\n#define REG_RX_FILTER_FUNCTION_8822C 0x07DA\n#define REG_NDP_SIG_8822C 0x07E0\n#define REG_TXCMD_INFO_FOR_RSP_PKT_8822C 0x07E4\n#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8822C 0x07E8\n#define REG_WSEC_OPTION_8822C 0x07EC\n#define REG_RTS_ADDRESS_0_8822C 0x07F0\n#define REG_RTS_ADDRESS_0_1_8822C 0x07F4\n#define REG_RTS_ADDRESS_1_8822C 0x07F8\n#define REG_RTS_ADDRESS_1_1_8822C 0x07FC\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822C 0x1700\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822C 0x1704\n#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822C 0x1708\n#define REG_SDIO_TX_CTRL_8822C 0x10250000\n#define REG_SDIO_CMD11_VOL_SWITCH_8822C 0x10250004\n#define REG_SDIO_CTRL_8822C 0x10250005\n#define REG_SDIO_DRIVING_8822C 0x10250006\n#define REG_SDIO_MONITOR_8822C 0x10250008\n#define REG_SDIO_MONITOR_2_8822C 0x1025000C\n#define REG_SDIO_HIMR_8822C 0x10250014\n#define REG_SDIO_HISR_8822C 0x10250018\n#define REG_SDIO_RX_REQ_LEN_8822C 0x1025001C\n#define REG_SDIO_FREE_TXPG_SEQ_V1_8822C 0x1025001F\n#define REG_SDIO_FREE_TXPG_8822C 0x10250020\n#define REG_SDIO_FREE_TXPG2_8822C 0x10250024\n#define REG_SDIO_OQT_FREE_TXPG_V1_8822C 0x10250028\n#define REG_SDIO_TXPKT_EMPTY_8822C 0x1025002C\n#define REG_SDIO_HTSFR_INFO_8822C 0x10250030\n#define REG_SDIO_HCPWM1_V2_8822C 0x10250038\n#define REG_SDIO_HCPWM2_V2_8822C 0x1025003A\n#define REG_SDIO_INDIRECT_REG_CFG_8822C 0x10250040\n#define REG_SDIO_INDIRECT_REG_DATA_8822C 0x10250044\n#define REG_SDIO_H2C_8822C 0x10250060\n#define REG_SDIO_C2H_8822C 0x10250064\n#define REG_SDIO_HRPWM1_8822C 0x10250080\n#define REG_SDIO_HRPWM2_8822C 0x10250082\n#define REG_SDIO_HPS_CLKR_8822C 0x10250084\n#define REG_SDIO_BUS_CTRL_8822C 0x10250085\n#define REG_SDIO_HSUS_CTRL_8822C 0x10250086\n#define REG_SDIO_RESPONSE_TIMER_8822C 0x10250088\n#define REG_SDIO_CMD_CRC_8822C 0x1025008A\n#define REG_SDIO_HSISR_8822C 0x10250090\n#define REG_SDIO_HSIMR_8822C 0x10250091\n#define REG_SDIO_DIOERR_RPT_8822C 0x102500C0\n#define REG_SDIO_CMD_ERRCNT_8822C 0x102500C2\n#define REG_SDIO_DATA_ERRCNT_8822C 0x102500C3\n#define REG_SDIO_CMD_ERR_CONTENT_8822C 0x102500C4\n#define REG_SDIO_CRC_ERR_IDX_8822C 0x102500C9\n#define REG_SDIO_DATA_CRC_8822C 0x102500CA\n#define REG_SDIO_TRANS_FIFO_STATUS_8822C 0x102500CC\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_rx_bd_nic.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_RX_BD_NIC_H_\n#define _HALMAC_RX_BD_NIC_H_\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n\tHALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||\\\n\tHALMAC_8812F_SUPPORT)\n\n/*TXBD_DW0*/\n\n#define GET_RX_BD_RXFAIL(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 31, 1)\n#define GET_RX_BD_TOTALRXPKTSIZE(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 16, 13)\n#define GET_RX_BD_RXTAG(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 16, 13)\n#define GET_RX_BD_FS(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 15, 1)\n#define GET_RX_BD_LS(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 14, 1)\n#define GET_RX_BD_RXBUFFSIZE(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 0, 14)\n\n/*TXBD_DW1*/\n\n#define GET_RX_BD_PHYSICAL_ADDR_LOW(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x04, 0, 32)\n\n/*TXBD_DW2*/\n\n#define GET_RX_BD_PHYSICAL_ADDR_HIGH(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x08, 0, 32)\n\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_rx_desc_ap.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_RX_DESC_AP_H_\n#define _HALMAC_RX_DESC_AP_H_\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n/*RXDESC_WORD0*/\n\n#define GET_RX_DESC_EOR(rxdesc)                                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \\\n\t\t\t      30)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_PHYPKTIDC(rxdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \\\n\t\t\t      28)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_EVT_PKT(rxdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \\\n\t\t\t      28)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_SWDEC(rxdesc)                                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \\\n\t\t\t      27)\n#define GET_RX_DESC_PHYST(rxdesc)                                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \\\n\t\t\t      26)\n#define GET_RX_DESC_SHIFT(rxdesc)                                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x3,  \\\n\t\t\t      24)\n#define GET_RX_DESC_QOS(rxdesc)                                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \\\n\t\t\t      23)\n#define GET_RX_DESC_SECURITY(rxdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x7,  \\\n\t\t\t      20)\n#define GET_RX_DESC_DRV_INFO_SIZE(rxdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0xf,  \\\n\t\t\t      16)\n#define GET_RX_DESC_ICV_ERR(rxdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \\\n\t\t\t      15)\n#define GET_RX_DESC_CRC32(rxdesc)                                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \\\n\t\t\t      14)\n#define GET_RX_DESC_PKT_LEN(rxdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0,       \\\n\t\t\t      0x3fff, 0)\n\n/*RXDESC_WORD1*/\n\n#define GET_RX_DESC_BC(rxdesc)                                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      31)\n#define GET_RX_DESC_MC(rxdesc)                                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      30)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_TY_PE(rxdesc)                                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x3,  \\\n\t\t\t      28)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_TYPE(rxdesc)                                               \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x3,  \\\n\t\t\t      28)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_MF(rxdesc)                                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      27)\n#define GET_RX_DESC_MD(rxdesc)                                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      26)\n#define GET_RX_DESC_PWR(rxdesc)                                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      25)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_PAM(rxdesc)                                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_A1_MATCH(rxdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_CHK_VLD(rxdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      23)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_TCP_CHKSUM_VLD(rxdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      23)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      22)\n#define GET_RX_DESC_RX_IPV(rxdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      21)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_CHKERR(rxdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      20)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_TCP_CHKSUM_ERR(rxdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      20)\n#define GET_RX_DESC_PHY_PKT_IDC(rxdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      17)\n#define GET_RX_DESC_FW_FIFO_FULL(rxdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_PAGGR(rxdesc)                                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      15)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_AMPDU(rxdesc)                                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      15)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_RXID_MATCH(rxdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      14)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_RXCMD_IDC(rxdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      14)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_AMSDU(rxdesc)                                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      13)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_MACID_VLD(rxdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \\\n\t\t\t      12)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_TID(rxdesc)                                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0xf, 8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_MACID(rxdesc)                                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x7f, \\\n\t\t\t      0)\n\n/*RXDESC_WORD2*/\n\n#define GET_RX_DESC_FCS_OK(rxdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \\\n\t\t\t      31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_AMSDU_CUT(rxdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \\\n\t\t\t      31)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_PPDU_CNT(rxdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3,  \\\n\t\t\t      29)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_C2H(rxdesc)                                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \\\n\t\t\t      28)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)\n\n#define GET_RX_DESC_HWRSVD_V1(rxdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x7,  \\\n\t\t\t      25)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_HWRSVD(rxdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0xf,  \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)\n\n#define GET_RX_DESC_RXMAGPKT(rxdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_WLANHD_IV_LEN(rxdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3f, \\\n\t\t\t      18)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_LAST_MSDU(rxdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \\\n\t\t\t      17)\n\n#endif\n\n#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_RX_STATISTICS(rxdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \\\n\t\t\t      17)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_RX_IS_QOS(rxdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \\\n\t\t\t      16)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_EXT_SEC_TYPE(rxdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \\\n\t\t\t      16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_FRAG(rxdesc)                                               \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0xf,  \\\n\t\t\t      12)\n#define GET_RX_DESC_SEQ(rxdesc)                                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2,       \\\n\t\t\t      0xfff, 0)\n\n/*RXDESC_WORD3*/\n\n#define GET_RX_DESC_MAGIC_WAKE(rxdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \\\n\t\t\t      31)\n#define GET_RX_DESC_UNICAST_WAKE(rxdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \\\n\t\t\t      30)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_PATTERN_MATCH(rxdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \\\n\t\t\t      29)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_PATTERN_WAKE(rxdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \\\n\t\t\t      29)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \\\n\t\t\t      28)\n#define GET_RX_DESC_RXPAYLOAD_ID(rxdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0xf,  \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_DMA_AGG_NUM(rxdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0xff, \\\n\t\t\t      16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_BSSID_FIT_1_0(rxdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x3,  \\\n\t\t\t      12)\n#define GET_RX_DESC_EOSP(rxdesc)                                               \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \\\n\t\t\t      11)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_BSSID_FIT(rxdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1f, \\\n\t\t\t      11)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_HTC(rxdesc)                                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \\\n\t\t\t      10)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_AMPDU_END_PKT(rxdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 9)\n#define GET_RX_DESC_ADDRESS_CAM_VLD(rxdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_BSSID_FIT_4_2(rxdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7, 7)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_EOSP_V1(rxdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 7)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_RX_RATE(rxdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7f, \\\n\t\t\t      0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n/*RXDESC_WORD4*/\n\n#define GET_RX_DESC_A1_FIT(rxdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_ADDRESS_CAM(rxdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define GET_RX_DESC_A1_FIT_A1(rxdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_MACID_VLD_V1(rxdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1,  \\\n\t\t\t      23)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_MACID_RPT_BUFF(rxdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \\\n\t\t\t      17)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1,  \\\n\t\t\t      16)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define GET_RX_DESC_SWPS_RPT_V1(rxdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1,  \\\n\t\t\t      16)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_MACID_V1(rxdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \\\n\t\t\t      15)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define GET_RX_DESC_FC_POWER_V1(rxdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1,  \\\n\t\t\t      15)\n#define GET_RX_DESC_TXRPTMID_CTL_MASK_V1(rxdesc)                               \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1,  \\\n\t\t\t      14)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_RX_SCRAMBLER(rxdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \\\n\t\t\t      9)\n#define GET_RX_DESC_RX_EOF(rxdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define GET_RX_DESC_SNIF_INFO(rxdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x3f, \\\n\t\t\t      8)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define GET_RX_DESC_FC_POWER(rxdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 7)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 6)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define GET_RX_DESC_SWPS_RPT(rxdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 5)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_PATTERN_IDX(rxdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \\\n\t\t\t      0)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define GET_RX_DESC_PATTERN_IDX_V1(rxdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \\\n\t\t\t      0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_PATTERN_IDX_V2(rxdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \\\n\t\t\t      0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n/*RXDESC_WORD5*/\n\n#define GET_RX_DESC_TSFL(rxdesc)                                               \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword5,       \\\n\t\t\t      0xffffffff, 0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_FREERUN_CNT(rxdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword5,       \\\n\t\t\t      0xffffffff, 0)\n\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_rx_desc_chip.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_RX_DESC_CHIP_H_\n#define _HALMAC_RX_DESC_CHIP_H_\n#if (HALMAC_8814A_SUPPORT)\n\n/*RXDESC_WORD0*/\n\n#define GET_RX_DESC_EOR_8814A(rxdesc) GET_RX_DESC_EOR(rxdesc)\n#define GET_RX_DESC_PHYPKTIDC_8814A(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)\n#define GET_RX_DESC_SWDEC_8814A(rxdesc) GET_RX_DESC_SWDEC(rxdesc)\n#define GET_RX_DESC_PHYST_8814A(rxdesc) GET_RX_DESC_PHYST(rxdesc)\n#define GET_RX_DESC_SHIFT_8814A(rxdesc) GET_RX_DESC_SHIFT(rxdesc)\n#define GET_RX_DESC_QOS_8814A(rxdesc) GET_RX_DESC_QOS(rxdesc)\n#define GET_RX_DESC_SECURITY_8814A(rxdesc) GET_RX_DESC_SECURITY(rxdesc)\n#define GET_RX_DESC_DRV_INFO_SIZE_8814A(rxdesc)                                \\\n\tGET_RX_DESC_DRV_INFO_SIZE(rxdesc)\n#define GET_RX_DESC_ICV_ERR_8814A(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)\n#define GET_RX_DESC_CRC32_8814A(rxdesc) GET_RX_DESC_CRC32(rxdesc)\n#define GET_RX_DESC_PKT_LEN_8814A(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)\n\n/*RXDESC_WORD1*/\n\n#define GET_RX_DESC_BC_8814A(rxdesc) GET_RX_DESC_BC(rxdesc)\n#define GET_RX_DESC_MC_8814A(rxdesc) GET_RX_DESC_MC(rxdesc)\n#define GET_RX_DESC_TY_PE_8814A(rxdesc) GET_RX_DESC_TY_PE(rxdesc)\n#define GET_RX_DESC_MF_8814A(rxdesc) GET_RX_DESC_MF(rxdesc)\n#define GET_RX_DESC_MD_8814A(rxdesc) GET_RX_DESC_MD(rxdesc)\n#define GET_RX_DESC_PWR_8814A(rxdesc) GET_RX_DESC_PWR(rxdesc)\n#define GET_RX_DESC_PAM_8814A(rxdesc) GET_RX_DESC_PAM(rxdesc)\n#define GET_RX_DESC_CHK_VLD_8814A(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)\n#define GET_RX_DESC_RX_IS_TCP_UDP_8814A(rxdesc)                                \\\n\tGET_RX_DESC_RX_IS_TCP_UDP(rxdesc)\n#define GET_RX_DESC_RX_IPV_8814A(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)\n#define GET_RX_DESC_CHKERR_8814A(rxdesc) GET_RX_DESC_CHKERR(rxdesc)\n#define GET_RX_DESC_PAGGR_8814A(rxdesc) GET_RX_DESC_PAGGR(rxdesc)\n#define GET_RX_DESC_RXID_MATCH_8814A(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)\n#define GET_RX_DESC_AMSDU_8814A(rxdesc) GET_RX_DESC_AMSDU(rxdesc)\n#define GET_RX_DESC_MACID_VLD_8814A(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)\n#define GET_RX_DESC_TID_8814A(rxdesc) GET_RX_DESC_TID(rxdesc)\n#define GET_RX_DESC_MACID_8814A(rxdesc) GET_RX_DESC_MACID(rxdesc)\n\n/*RXDESC_WORD2*/\n\n#define GET_RX_DESC_FCS_OK_8814A(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)\n#define GET_RX_DESC_C2H_8814A(rxdesc) GET_RX_DESC_C2H(rxdesc)\n#define GET_RX_DESC_HWRSVD_8814A(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)\n#define GET_RX_DESC_WLANHD_IV_LEN_8814A(rxdesc)                                \\\n\tGET_RX_DESC_WLANHD_IV_LEN(rxdesc)\n#define GET_RX_DESC_RX_IS_QOS_8814A(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)\n#define GET_RX_DESC_FRAG_8814A(rxdesc) GET_RX_DESC_FRAG(rxdesc)\n#define GET_RX_DESC_SEQ_8814A(rxdesc) GET_RX_DESC_SEQ(rxdesc)\n\n/*RXDESC_WORD3*/\n\n#define GET_RX_DESC_MAGIC_WAKE_8814A(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)\n#define GET_RX_DESC_UNICAST_WAKE_8814A(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)\n#define GET_RX_DESC_PATTERN_MATCH_8814A(rxdesc)                                \\\n\tGET_RX_DESC_PATTERN_MATCH(rxdesc)\n#define GET_RX_DESC_DMA_AGG_NUM_8814A(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)\n#define GET_RX_DESC_BSSID_FIT_1_0_8814A(rxdesc)                                \\\n\tGET_RX_DESC_BSSID_FIT_1_0(rxdesc)\n#define GET_RX_DESC_EOSP_8814A(rxdesc) GET_RX_DESC_EOSP(rxdesc)\n#define GET_RX_DESC_HTC_8814A(rxdesc) GET_RX_DESC_HTC(rxdesc)\n#define GET_RX_DESC_BSSID_FIT_4_2_8814A(rxdesc)                                \\\n\tGET_RX_DESC_BSSID_FIT_4_2(rxdesc)\n#define GET_RX_DESC_RX_RATE_8814A(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)\n\n/*RXDESC_WORD4*/\n\n#define GET_RX_DESC_A1_FIT_8814A(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)\n#define GET_RX_DESC_MACID_RPT_BUFF_8814A(rxdesc)                               \\\n\tGET_RX_DESC_MACID_RPT_BUFF(rxdesc)\n#define GET_RX_DESC_RX_PRE_NDP_VLD_8814A(rxdesc)                               \\\n\tGET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)\n#define GET_RX_DESC_RX_SCRAMBLER_8814A(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)\n#define GET_RX_DESC_RX_EOF_8814A(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)\n#define GET_RX_DESC_PATTERN_IDX_8814A(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)\n\n/*RXDESC_WORD5*/\n\n#define GET_RX_DESC_TSFL_8814A(rxdesc) GET_RX_DESC_TSFL(rxdesc)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/*RXDESC_WORD0*/\n\n#define GET_RX_DESC_EOR_8822B(rxdesc) GET_RX_DESC_EOR(rxdesc)\n#define GET_RX_DESC_PHYPKTIDC_8822B(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)\n#define GET_RX_DESC_SWDEC_8822B(rxdesc) GET_RX_DESC_SWDEC(rxdesc)\n#define GET_RX_DESC_PHYST_8822B(rxdesc) GET_RX_DESC_PHYST(rxdesc)\n#define GET_RX_DESC_SHIFT_8822B(rxdesc) GET_RX_DESC_SHIFT(rxdesc)\n#define GET_RX_DESC_QOS_8822B(rxdesc) GET_RX_DESC_QOS(rxdesc)\n#define GET_RX_DESC_SECURITY_8822B(rxdesc) GET_RX_DESC_SECURITY(rxdesc)\n#define GET_RX_DESC_DRV_INFO_SIZE_8822B(rxdesc)                                \\\n\tGET_RX_DESC_DRV_INFO_SIZE(rxdesc)\n#define GET_RX_DESC_ICV_ERR_8822B(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)\n#define GET_RX_DESC_CRC32_8822B(rxdesc) GET_RX_DESC_CRC32(rxdesc)\n#define GET_RX_DESC_PKT_LEN_8822B(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)\n\n/*RXDESC_WORD1*/\n\n#define GET_RX_DESC_BC_8822B(rxdesc) GET_RX_DESC_BC(rxdesc)\n#define GET_RX_DESC_MC_8822B(rxdesc) GET_RX_DESC_MC(rxdesc)\n#define GET_RX_DESC_TY_PE_8822B(rxdesc) GET_RX_DESC_TY_PE(rxdesc)\n#define GET_RX_DESC_MF_8822B(rxdesc) GET_RX_DESC_MF(rxdesc)\n#define GET_RX_DESC_MD_8822B(rxdesc) GET_RX_DESC_MD(rxdesc)\n#define GET_RX_DESC_PWR_8822B(rxdesc) GET_RX_DESC_PWR(rxdesc)\n#define GET_RX_DESC_PAM_8822B(rxdesc) GET_RX_DESC_PAM(rxdesc)\n#define GET_RX_DESC_CHK_VLD_8822B(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)\n#define GET_RX_DESC_RX_IS_TCP_UDP_8822B(rxdesc)                                \\\n\tGET_RX_DESC_RX_IS_TCP_UDP(rxdesc)\n#define GET_RX_DESC_RX_IPV_8822B(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)\n#define GET_RX_DESC_CHKERR_8822B(rxdesc) GET_RX_DESC_CHKERR(rxdesc)\n#define GET_RX_DESC_PAGGR_8822B(rxdesc) GET_RX_DESC_PAGGR(rxdesc)\n#define GET_RX_DESC_RXID_MATCH_8822B(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)\n#define GET_RX_DESC_AMSDU_8822B(rxdesc) GET_RX_DESC_AMSDU(rxdesc)\n#define GET_RX_DESC_MACID_VLD_8822B(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)\n#define GET_RX_DESC_TID_8822B(rxdesc) GET_RX_DESC_TID(rxdesc)\n#define GET_RX_DESC_MACID_8822B(rxdesc) GET_RX_DESC_MACID(rxdesc)\n\n/*RXDESC_WORD2*/\n\n#define GET_RX_DESC_FCS_OK_8822B(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)\n#define GET_RX_DESC_PPDU_CNT_8822B(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)\n#define GET_RX_DESC_C2H_8822B(rxdesc) GET_RX_DESC_C2H(rxdesc)\n#define GET_RX_DESC_HWRSVD_8822B(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)\n#define GET_RX_DESC_WLANHD_IV_LEN_8822B(rxdesc)                                \\\n\tGET_RX_DESC_WLANHD_IV_LEN(rxdesc)\n#define GET_RX_DESC_RX_IS_QOS_8822B(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)\n#define GET_RX_DESC_FRAG_8822B(rxdesc) GET_RX_DESC_FRAG(rxdesc)\n#define GET_RX_DESC_SEQ_8822B(rxdesc) GET_RX_DESC_SEQ(rxdesc)\n\n/*RXDESC_WORD3*/\n\n#define GET_RX_DESC_MAGIC_WAKE_8822B(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)\n#define GET_RX_DESC_UNICAST_WAKE_8822B(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)\n#define GET_RX_DESC_PATTERN_MATCH_8822B(rxdesc)                                \\\n\tGET_RX_DESC_PATTERN_MATCH(rxdesc)\n#define GET_RX_DESC_RXPAYLOAD_MATCH_8822B(rxdesc)                              \\\n\tGET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)\n#define GET_RX_DESC_RXPAYLOAD_ID_8822B(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)\n#define GET_RX_DESC_DMA_AGG_NUM_8822B(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)\n#define GET_RX_DESC_BSSID_FIT_1_0_8822B(rxdesc)                                \\\n\tGET_RX_DESC_BSSID_FIT_1_0(rxdesc)\n#define GET_RX_DESC_EOSP_8822B(rxdesc) GET_RX_DESC_EOSP(rxdesc)\n#define GET_RX_DESC_HTC_8822B(rxdesc) GET_RX_DESC_HTC(rxdesc)\n#define GET_RX_DESC_BSSID_FIT_4_2_8822B(rxdesc)                                \\\n\tGET_RX_DESC_BSSID_FIT_4_2(rxdesc)\n#define GET_RX_DESC_RX_RATE_8822B(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)\n\n/*RXDESC_WORD4*/\n\n#define GET_RX_DESC_A1_FIT_8822B(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)\n#define GET_RX_DESC_MACID_RPT_BUFF_8822B(rxdesc)                               \\\n\tGET_RX_DESC_MACID_RPT_BUFF(rxdesc)\n#define GET_RX_DESC_RX_PRE_NDP_VLD_8822B(rxdesc)                               \\\n\tGET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)\n#define GET_RX_DESC_RX_SCRAMBLER_8822B(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)\n#define GET_RX_DESC_RX_EOF_8822B(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)\n#define GET_RX_DESC_PATTERN_IDX_8822B(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)\n\n/*RXDESC_WORD5*/\n\n#define GET_RX_DESC_TSFL_8822B(rxdesc) GET_RX_DESC_TSFL(rxdesc)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/*RXDESC_WORD0*/\n\n#define GET_RX_DESC_EOR_8197F(rxdesc) GET_RX_DESC_EOR(rxdesc)\n#define GET_RX_DESC_PHYPKTIDC_8197F(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)\n#define GET_RX_DESC_SWDEC_8197F(rxdesc) GET_RX_DESC_SWDEC(rxdesc)\n#define GET_RX_DESC_PHYST_8197F(rxdesc) GET_RX_DESC_PHYST(rxdesc)\n#define GET_RX_DESC_SHIFT_8197F(rxdesc) GET_RX_DESC_SHIFT(rxdesc)\n#define GET_RX_DESC_QOS_8197F(rxdesc) GET_RX_DESC_QOS(rxdesc)\n#define GET_RX_DESC_SECURITY_8197F(rxdesc) GET_RX_DESC_SECURITY(rxdesc)\n#define GET_RX_DESC_DRV_INFO_SIZE_8197F(rxdesc)                                \\\n\tGET_RX_DESC_DRV_INFO_SIZE(rxdesc)\n#define GET_RX_DESC_ICV_ERR_8197F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)\n#define GET_RX_DESC_CRC32_8197F(rxdesc) GET_RX_DESC_CRC32(rxdesc)\n#define GET_RX_DESC_PKT_LEN_8197F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)\n\n/*RXDESC_WORD1*/\n\n#define GET_RX_DESC_BC_8197F(rxdesc) GET_RX_DESC_BC(rxdesc)\n#define GET_RX_DESC_MC_8197F(rxdesc) GET_RX_DESC_MC(rxdesc)\n#define GET_RX_DESC_TY_PE_8197F(rxdesc) GET_RX_DESC_TY_PE(rxdesc)\n#define GET_RX_DESC_MF_8197F(rxdesc) GET_RX_DESC_MF(rxdesc)\n#define GET_RX_DESC_MD_8197F(rxdesc) GET_RX_DESC_MD(rxdesc)\n#define GET_RX_DESC_PWR_8197F(rxdesc) GET_RX_DESC_PWR(rxdesc)\n#define GET_RX_DESC_PAM_8197F(rxdesc) GET_RX_DESC_PAM(rxdesc)\n#define GET_RX_DESC_CHK_VLD_8197F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)\n#define GET_RX_DESC_RX_IS_TCP_UDP_8197F(rxdesc)                                \\\n\tGET_RX_DESC_RX_IS_TCP_UDP(rxdesc)\n#define GET_RX_DESC_RX_IPV_8197F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)\n#define GET_RX_DESC_CHKERR_8197F(rxdesc) GET_RX_DESC_CHKERR(rxdesc)\n#define GET_RX_DESC_PAGGR_8197F(rxdesc) GET_RX_DESC_PAGGR(rxdesc)\n#define GET_RX_DESC_RXID_MATCH_8197F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)\n#define GET_RX_DESC_AMSDU_8197F(rxdesc) GET_RX_DESC_AMSDU(rxdesc)\n#define GET_RX_DESC_MACID_VLD_8197F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)\n#define GET_RX_DESC_TID_8197F(rxdesc) GET_RX_DESC_TID(rxdesc)\n#define GET_RX_DESC_MACID_8197F(rxdesc) GET_RX_DESC_MACID(rxdesc)\n\n/*RXDESC_WORD2*/\n\n#define GET_RX_DESC_FCS_OK_8197F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)\n#define GET_RX_DESC_C2H_8197F(rxdesc) GET_RX_DESC_C2H(rxdesc)\n#define GET_RX_DESC_HWRSVD_8197F(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)\n#define GET_RX_DESC_WLANHD_IV_LEN_8197F(rxdesc)                                \\\n\tGET_RX_DESC_WLANHD_IV_LEN(rxdesc)\n#define GET_RX_DESC_RX_IS_QOS_8197F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)\n#define GET_RX_DESC_FRAG_8197F(rxdesc) GET_RX_DESC_FRAG(rxdesc)\n#define GET_RX_DESC_SEQ_8197F(rxdesc) GET_RX_DESC_SEQ(rxdesc)\n\n/*RXDESC_WORD3*/\n\n#define GET_RX_DESC_MAGIC_WAKE_8197F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)\n#define GET_RX_DESC_UNICAST_WAKE_8197F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)\n#define GET_RX_DESC_PATTERN_MATCH_8197F(rxdesc)                                \\\n\tGET_RX_DESC_PATTERN_MATCH(rxdesc)\n#define GET_RX_DESC_DMA_AGG_NUM_8197F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)\n#define GET_RX_DESC_BSSID_FIT_1_0_8197F(rxdesc)                                \\\n\tGET_RX_DESC_BSSID_FIT_1_0(rxdesc)\n#define GET_RX_DESC_EOSP_8197F(rxdesc) GET_RX_DESC_EOSP(rxdesc)\n#define GET_RX_DESC_HTC_8197F(rxdesc) GET_RX_DESC_HTC(rxdesc)\n#define GET_RX_DESC_BSSID_FIT_4_2_8197F(rxdesc)                                \\\n\tGET_RX_DESC_BSSID_FIT_4_2(rxdesc)\n#define GET_RX_DESC_RX_RATE_8197F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)\n\n/*RXDESC_WORD4*/\n\n#define GET_RX_DESC_A1_FIT_8197F(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)\n#define GET_RX_DESC_MACID_RPT_BUFF_8197F(rxdesc)                               \\\n\tGET_RX_DESC_MACID_RPT_BUFF(rxdesc)\n#define GET_RX_DESC_RX_PRE_NDP_VLD_8197F(rxdesc)                               \\\n\tGET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)\n#define GET_RX_DESC_RX_SCRAMBLER_8197F(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)\n#define GET_RX_DESC_RX_EOF_8197F(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)\n#define GET_RX_DESC_FC_POWER_8197F(rxdesc) GET_RX_DESC_FC_POWER(rxdesc)\n#define GET_RX_DESC_PATTERN_IDX_8197F(rxdesc) GET_RX_DESC_PATTERN_IDX_V1(rxdesc)\n\n/*RXDESC_WORD5*/\n\n#define GET_RX_DESC_TSFL_8197F(rxdesc) GET_RX_DESC_TSFL(rxdesc)\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT)\n\n/*RXDESC_WORD0*/\n\n#define GET_RX_DESC_EOR_8821C(rxdesc) GET_RX_DESC_EOR(rxdesc)\n#define GET_RX_DESC_PHYPKTIDC_8821C(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)\n#define GET_RX_DESC_SWDEC_8821C(rxdesc) GET_RX_DESC_SWDEC(rxdesc)\n#define GET_RX_DESC_PHYST_8821C(rxdesc) GET_RX_DESC_PHYST(rxdesc)\n#define GET_RX_DESC_SHIFT_8821C(rxdesc) GET_RX_DESC_SHIFT(rxdesc)\n#define GET_RX_DESC_QOS_8821C(rxdesc) GET_RX_DESC_QOS(rxdesc)\n#define GET_RX_DESC_SECURITY_8821C(rxdesc) GET_RX_DESC_SECURITY(rxdesc)\n#define GET_RX_DESC_DRV_INFO_SIZE_8821C(rxdesc)                                \\\n\tGET_RX_DESC_DRV_INFO_SIZE(rxdesc)\n#define GET_RX_DESC_ICV_ERR_8821C(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)\n#define GET_RX_DESC_CRC32_8821C(rxdesc) GET_RX_DESC_CRC32(rxdesc)\n#define GET_RX_DESC_PKT_LEN_8821C(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)\n\n/*RXDESC_WORD1*/\n\n#define GET_RX_DESC_BC_8821C(rxdesc) GET_RX_DESC_BC(rxdesc)\n#define GET_RX_DESC_MC_8821C(rxdesc) GET_RX_DESC_MC(rxdesc)\n#define GET_RX_DESC_TY_PE_8821C(rxdesc) GET_RX_DESC_TY_PE(rxdesc)\n#define GET_RX_DESC_MF_8821C(rxdesc) GET_RX_DESC_MF(rxdesc)\n#define GET_RX_DESC_MD_8821C(rxdesc) GET_RX_DESC_MD(rxdesc)\n#define GET_RX_DESC_PWR_8821C(rxdesc) GET_RX_DESC_PWR(rxdesc)\n#define GET_RX_DESC_PAM_8821C(rxdesc) GET_RX_DESC_PAM(rxdesc)\n#define GET_RX_DESC_CHK_VLD_8821C(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)\n#define GET_RX_DESC_RX_IS_TCP_UDP_8821C(rxdesc)                                \\\n\tGET_RX_DESC_RX_IS_TCP_UDP(rxdesc)\n#define GET_RX_DESC_RX_IPV_8821C(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)\n#define GET_RX_DESC_CHKERR_8821C(rxdesc) GET_RX_DESC_CHKERR(rxdesc)\n#define GET_RX_DESC_PAGGR_8821C(rxdesc) GET_RX_DESC_PAGGR(rxdesc)\n#define GET_RX_DESC_RXID_MATCH_8821C(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)\n#define GET_RX_DESC_AMSDU_8821C(rxdesc) GET_RX_DESC_AMSDU(rxdesc)\n#define GET_RX_DESC_MACID_VLD_8821C(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)\n#define GET_RX_DESC_TID_8821C(rxdesc) GET_RX_DESC_TID(rxdesc)\n#define GET_RX_DESC_MACID_8821C(rxdesc) GET_RX_DESC_MACID(rxdesc)\n\n/*RXDESC_WORD2*/\n\n#define GET_RX_DESC_FCS_OK_8821C(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)\n#define GET_RX_DESC_PPDU_CNT_8821C(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)\n#define GET_RX_DESC_C2H_8821C(rxdesc) GET_RX_DESC_C2H(rxdesc)\n#define GET_RX_DESC_HWRSVD_8821C(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)\n#define GET_RX_DESC_WLANHD_IV_LEN_8821C(rxdesc)                                \\\n\tGET_RX_DESC_WLANHD_IV_LEN(rxdesc)\n#define GET_RX_DESC_RX_IS_QOS_8821C(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)\n#define GET_RX_DESC_FRAG_8821C(rxdesc) GET_RX_DESC_FRAG(rxdesc)\n#define GET_RX_DESC_SEQ_8821C(rxdesc) GET_RX_DESC_SEQ(rxdesc)\n\n/*RXDESC_WORD3*/\n\n#define GET_RX_DESC_MAGIC_WAKE_8821C(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)\n#define GET_RX_DESC_UNICAST_WAKE_8821C(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)\n#define GET_RX_DESC_PATTERN_MATCH_8821C(rxdesc)                                \\\n\tGET_RX_DESC_PATTERN_MATCH(rxdesc)\n#define GET_RX_DESC_RXPAYLOAD_MATCH_8821C(rxdesc)                              \\\n\tGET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)\n#define GET_RX_DESC_RXPAYLOAD_ID_8821C(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)\n#define GET_RX_DESC_DMA_AGG_NUM_8821C(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)\n#define GET_RX_DESC_BSSID_FIT_1_0_8821C(rxdesc)                                \\\n\tGET_RX_DESC_BSSID_FIT_1_0(rxdesc)\n#define GET_RX_DESC_EOSP_8821C(rxdesc) GET_RX_DESC_EOSP(rxdesc)\n#define GET_RX_DESC_HTC_8821C(rxdesc) GET_RX_DESC_HTC(rxdesc)\n#define GET_RX_DESC_BSSID_FIT_4_2_8821C(rxdesc)                                \\\n\tGET_RX_DESC_BSSID_FIT_4_2(rxdesc)\n#define GET_RX_DESC_RX_RATE_8821C(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)\n\n/*RXDESC_WORD4*/\n\n#define GET_RX_DESC_A1_FIT_8821C(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)\n#define GET_RX_DESC_MACID_RPT_BUFF_8821C(rxdesc)                               \\\n\tGET_RX_DESC_MACID_RPT_BUFF(rxdesc)\n#define GET_RX_DESC_RX_PRE_NDP_VLD_8821C(rxdesc)                               \\\n\tGET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)\n#define GET_RX_DESC_RX_SCRAMBLER_8821C(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)\n#define GET_RX_DESC_RX_EOF_8821C(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)\n#define GET_RX_DESC_PATTERN_IDX_8821C(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)\n\n/*RXDESC_WORD5*/\n\n#define GET_RX_DESC_TSFL_8821C(rxdesc) GET_RX_DESC_TSFL(rxdesc)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/*RXDESC_WORD0*/\n\n#define GET_RX_DESC_EVT_PKT_8814B(rxdesc) GET_RX_DESC_EVT_PKT(rxdesc)\n#define GET_RX_DESC_SWDEC_8814B(rxdesc) GET_RX_DESC_SWDEC(rxdesc)\n#define GET_RX_DESC_PHYST_8814B(rxdesc) GET_RX_DESC_PHYST(rxdesc)\n#define GET_RX_DESC_SHIFT_8814B(rxdesc) GET_RX_DESC_SHIFT(rxdesc)\n#define GET_RX_DESC_QOS_8814B(rxdesc) GET_RX_DESC_QOS(rxdesc)\n#define GET_RX_DESC_SECURITY_8814B(rxdesc) GET_RX_DESC_SECURITY(rxdesc)\n#define GET_RX_DESC_DRV_INFO_SIZE_8814B(rxdesc)                                \\\n\tGET_RX_DESC_DRV_INFO_SIZE(rxdesc)\n#define GET_RX_DESC_ICV_ERR_8814B(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)\n#define GET_RX_DESC_CRC32_8814B(rxdesc) GET_RX_DESC_CRC32(rxdesc)\n#define GET_RX_DESC_PKT_LEN_8814B(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)\n\n/*RXDESC_WORD1*/\n\n#define GET_RX_DESC_BC_8814B(rxdesc) GET_RX_DESC_BC(rxdesc)\n#define GET_RX_DESC_MC_8814B(rxdesc) GET_RX_DESC_MC(rxdesc)\n#define GET_RX_DESC_TYPE_8814B(rxdesc) GET_RX_DESC_TYPE(rxdesc)\n#define GET_RX_DESC_MF_8814B(rxdesc) GET_RX_DESC_MF(rxdesc)\n#define GET_RX_DESC_MD_8814B(rxdesc) GET_RX_DESC_MD(rxdesc)\n#define GET_RX_DESC_PWR_8814B(rxdesc) GET_RX_DESC_PWR(rxdesc)\n#define GET_RX_DESC_A1_MATCH_8814B(rxdesc) GET_RX_DESC_A1_MATCH(rxdesc)\n#define GET_RX_DESC_TCP_CHKSUM_VLD_8814B(rxdesc)                               \\\n\tGET_RX_DESC_TCP_CHKSUM_VLD(rxdesc)\n#define GET_RX_DESC_RX_IS_TCP_UDP_8814B(rxdesc)                                \\\n\tGET_RX_DESC_RX_IS_TCP_UDP(rxdesc)\n#define GET_RX_DESC_RX_IPV_8814B(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)\n#define GET_RX_DESC_TCP_CHKSUM_ERR_8814B(rxdesc)                               \\\n\tGET_RX_DESC_TCP_CHKSUM_ERR(rxdesc)\n#define GET_RX_DESC_PHY_PKT_IDC_8814B(rxdesc) GET_RX_DESC_PHY_PKT_IDC(rxdesc)\n#define GET_RX_DESC_FW_FIFO_FULL_8814B(rxdesc) GET_RX_DESC_FW_FIFO_FULL(rxdesc)\n#define GET_RX_DESC_AMPDU_8814B(rxdesc) GET_RX_DESC_AMPDU(rxdesc)\n#define GET_RX_DESC_RXCMD_IDC_8814B(rxdesc) GET_RX_DESC_RXCMD_IDC(rxdesc)\n#define GET_RX_DESC_AMSDU_8814B(rxdesc) GET_RX_DESC_AMSDU(rxdesc)\n#define GET_RX_DESC_TID_8814B(rxdesc) GET_RX_DESC_TID(rxdesc)\n\n/*RXDESC_WORD2*/\n\n#define GET_RX_DESC_AMSDU_CUT_8814B(rxdesc) GET_RX_DESC_AMSDU_CUT(rxdesc)\n#define GET_RX_DESC_PPDU_CNT_8814B(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)\n#define GET_RX_DESC_C2H_8814B(rxdesc) GET_RX_DESC_C2H(rxdesc)\n#define GET_RX_DESC_WLANHD_IV_LEN_8814B(rxdesc)                                \\\n\tGET_RX_DESC_WLANHD_IV_LEN(rxdesc)\n#define GET_RX_DESC_LAST_MSDU_8814B(rxdesc) GET_RX_DESC_LAST_MSDU(rxdesc)\n#define GET_RX_DESC_EXT_SEC_TYPE_8814B(rxdesc) GET_RX_DESC_EXT_SEC_TYPE(rxdesc)\n#define GET_RX_DESC_FRAG_8814B(rxdesc) GET_RX_DESC_FRAG(rxdesc)\n#define GET_RX_DESC_SEQ_8814B(rxdesc) GET_RX_DESC_SEQ(rxdesc)\n\n/*RXDESC_WORD3*/\n\n#define GET_RX_DESC_MAGIC_WAKE_8814B(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)\n#define GET_RX_DESC_UNICAST_WAKE_8814B(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)\n#define GET_RX_DESC_PATTERN_WAKE_8814B(rxdesc) GET_RX_DESC_PATTERN_WAKE(rxdesc)\n#define GET_RX_DESC_RXPAYLOAD_MATCH_8814B(rxdesc)                              \\\n\tGET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)\n#define GET_RX_DESC_RXPAYLOAD_ID_8814B(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)\n#define GET_RX_DESC_DMA_AGG_NUM_8814B(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)\n#define GET_RX_DESC_BSSID_FIT_8814B(rxdesc) GET_RX_DESC_BSSID_FIT(rxdesc)\n#define GET_RX_DESC_HTC_8814B(rxdesc) GET_RX_DESC_HTC(rxdesc)\n#define GET_RX_DESC_AMPDU_END_PKT_8814B(rxdesc)                                \\\n\tGET_RX_DESC_AMPDU_END_PKT(rxdesc)\n#define GET_RX_DESC_ADDRESS_CAM_VLD_8814B(rxdesc)                              \\\n\tGET_RX_DESC_ADDRESS_CAM_VLD(rxdesc)\n#define GET_RX_DESC_EOSP_8814B(rxdesc) GET_RX_DESC_EOSP_V1(rxdesc)\n#define GET_RX_DESC_RX_RATE_8814B(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)\n\n/*RXDESC_WORD4*/\n\n#define GET_RX_DESC_ADDRESS_CAM_8814B(rxdesc) GET_RX_DESC_ADDRESS_CAM(rxdesc)\n#define GET_RX_DESC_MACID_VLD_8814B(rxdesc) GET_RX_DESC_MACID_VLD_V1(rxdesc)\n#define GET_RX_DESC_MACID_8814B(rxdesc) GET_RX_DESC_MACID_V1(rxdesc)\n#define GET_RX_DESC_SWPS_RPT_8814B(rxdesc) GET_RX_DESC_SWPS_RPT(rxdesc)\n#define GET_RX_DESC_PATTERN_IDX_8814B(rxdesc) GET_RX_DESC_PATTERN_IDX_V2(rxdesc)\n\n/*RXDESC_WORD5*/\n\n#define GET_RX_DESC_FREERUN_CNT_8814B(rxdesc) GET_RX_DESC_FREERUN_CNT(rxdesc)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/*RXDESC_WORD0*/\n\n#define GET_RX_DESC_EOR_8198F(rxdesc) GET_RX_DESC_EOR(rxdesc)\n#define GET_RX_DESC_PHYPKTIDC_8198F(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)\n#define GET_RX_DESC_SWDEC_8198F(rxdesc) GET_RX_DESC_SWDEC(rxdesc)\n#define GET_RX_DESC_PHYST_8198F(rxdesc) GET_RX_DESC_PHYST(rxdesc)\n#define GET_RX_DESC_SHIFT_8198F(rxdesc) GET_RX_DESC_SHIFT(rxdesc)\n#define GET_RX_DESC_QOS_8198F(rxdesc) GET_RX_DESC_QOS(rxdesc)\n#define GET_RX_DESC_SECURITY_8198F(rxdesc) GET_RX_DESC_SECURITY(rxdesc)\n#define GET_RX_DESC_DRV_INFO_SIZE_8198F(rxdesc)                                \\\n\tGET_RX_DESC_DRV_INFO_SIZE(rxdesc)\n#define GET_RX_DESC_ICV_ERR_8198F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)\n#define GET_RX_DESC_CRC32_8198F(rxdesc) GET_RX_DESC_CRC32(rxdesc)\n#define GET_RX_DESC_PKT_LEN_8198F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)\n\n/*RXDESC_WORD1*/\n\n#define GET_RX_DESC_BC_8198F(rxdesc) GET_RX_DESC_BC(rxdesc)\n#define GET_RX_DESC_MC_8198F(rxdesc) GET_RX_DESC_MC(rxdesc)\n#define GET_RX_DESC_TY_PE_8198F(rxdesc) GET_RX_DESC_TY_PE(rxdesc)\n#define GET_RX_DESC_MF_8198F(rxdesc) GET_RX_DESC_MF(rxdesc)\n#define GET_RX_DESC_MD_8198F(rxdesc) GET_RX_DESC_MD(rxdesc)\n#define GET_RX_DESC_PWR_8198F(rxdesc) GET_RX_DESC_PWR(rxdesc)\n#define GET_RX_DESC_PAM_8198F(rxdesc) GET_RX_DESC_PAM(rxdesc)\n#define GET_RX_DESC_CHK_VLD_8198F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)\n#define GET_RX_DESC_RX_IS_TCP_UDP_8198F(rxdesc)                                \\\n\tGET_RX_DESC_RX_IS_TCP_UDP(rxdesc)\n#define GET_RX_DESC_RX_IPV_8198F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)\n#define GET_RX_DESC_CHKERR_8198F(rxdesc) GET_RX_DESC_CHKERR(rxdesc)\n#define GET_RX_DESC_PAGGR_8198F(rxdesc) GET_RX_DESC_PAGGR(rxdesc)\n#define GET_RX_DESC_RXID_MATCH_8198F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)\n#define GET_RX_DESC_AMSDU_8198F(rxdesc) GET_RX_DESC_AMSDU(rxdesc)\n#define GET_RX_DESC_MACID_VLD_8198F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)\n#define GET_RX_DESC_TID_8198F(rxdesc) GET_RX_DESC_TID(rxdesc)\n#define GET_RX_DESC_MACID_8198F(rxdesc) GET_RX_DESC_MACID(rxdesc)\n\n/*RXDESC_WORD2*/\n\n#define GET_RX_DESC_FCS_OK_8198F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)\n#define GET_RX_DESC_PPDU_CNT_8198F(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)\n#define GET_RX_DESC_C2H_8198F(rxdesc) GET_RX_DESC_C2H(rxdesc)\n#define GET_RX_DESC_HWRSVD_8198F(rxdesc) GET_RX_DESC_HWRSVD_V1(rxdesc)\n#define GET_RX_DESC_RXMAGPKT_8198F(rxdesc) GET_RX_DESC_RXMAGPKT(rxdesc)\n#define GET_RX_DESC_WLANHD_IV_LEN_8198F(rxdesc)                                \\\n\tGET_RX_DESC_WLANHD_IV_LEN(rxdesc)\n#define GET_RX_DESC_RX_IS_QOS_8198F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)\n#define GET_RX_DESC_FRAG_8198F(rxdesc) GET_RX_DESC_FRAG(rxdesc)\n#define GET_RX_DESC_SEQ_8198F(rxdesc) GET_RX_DESC_SEQ(rxdesc)\n\n/*RXDESC_WORD3*/\n\n#define GET_RX_DESC_MAGIC_WAKE_8198F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)\n#define GET_RX_DESC_UNICAST_WAKE_8198F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)\n#define GET_RX_DESC_PATTERN_MATCH_8198F(rxdesc)                                \\\n\tGET_RX_DESC_PATTERN_MATCH(rxdesc)\n#define GET_RX_DESC_RXPAYLOAD_MATCH_8198F(rxdesc)                              \\\n\tGET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)\n#define GET_RX_DESC_RXPAYLOAD_ID_8198F(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)\n#define GET_RX_DESC_DMA_AGG_NUM_8198F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)\n#define GET_RX_DESC_BSSID_FIT_1_0_8198F(rxdesc)                                \\\n\tGET_RX_DESC_BSSID_FIT_1_0(rxdesc)\n#define GET_RX_DESC_EOSP_8198F(rxdesc) GET_RX_DESC_EOSP(rxdesc)\n#define GET_RX_DESC_HTC_8198F(rxdesc) GET_RX_DESC_HTC(rxdesc)\n#define GET_RX_DESC_BSSID_FIT_4_2_8198F(rxdesc)                                \\\n\tGET_RX_DESC_BSSID_FIT_4_2(rxdesc)\n#define GET_RX_DESC_RX_RATE_8198F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)\n\n/*RXDESC_WORD4*/\n\n#define GET_RX_DESC_A1_FIT_A1_8198F(rxdesc) GET_RX_DESC_A1_FIT_A1(rxdesc)\n#define GET_RX_DESC_MACID_RPT_BUFF_8198F(rxdesc)                               \\\n\tGET_RX_DESC_MACID_RPT_BUFF(rxdesc)\n#define GET_RX_DESC_RX_PRE_NDP_VLD_8198F(rxdesc)                               \\\n\tGET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)\n#define GET_RX_DESC_RX_SCRAMBLER_8198F(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)\n#define GET_RX_DESC_RX_EOF_8198F(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)\n#define GET_RX_DESC_FC_POWER_8198F(rxdesc) GET_RX_DESC_FC_POWER(rxdesc)\n#define GET_RX_DESC_TXRPTMID_CTL_MASK_8198F(rxdesc)                            \\\n\tGET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc)\n#define GET_RX_DESC_SWPS_RPT_8198F(rxdesc) GET_RX_DESC_SWPS_RPT(rxdesc)\n#define GET_RX_DESC_PATTERN_IDX_8198F(rxdesc) GET_RX_DESC_PATTERN_IDX_V1(rxdesc)\n\n/*RXDESC_WORD5*/\n\n#define GET_RX_DESC_TSFL_8198F(rxdesc) GET_RX_DESC_TSFL(rxdesc)\n\n#endif\n\n#if (HALMAC_8822C_SUPPORT)\n\n/*RXDESC_WORD0*/\n\n#define GET_RX_DESC_EOR_8822C(rxdesc) GET_RX_DESC_EOR(rxdesc)\n#define GET_RX_DESC_PHYPKTIDC_8822C(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)\n#define GET_RX_DESC_SWDEC_8822C(rxdesc) GET_RX_DESC_SWDEC(rxdesc)\n#define GET_RX_DESC_PHYST_8822C(rxdesc) GET_RX_DESC_PHYST(rxdesc)\n#define GET_RX_DESC_SHIFT_8822C(rxdesc) GET_RX_DESC_SHIFT(rxdesc)\n#define GET_RX_DESC_QOS_8822C(rxdesc) GET_RX_DESC_QOS(rxdesc)\n#define GET_RX_DESC_SECURITY_8822C(rxdesc) GET_RX_DESC_SECURITY(rxdesc)\n#define GET_RX_DESC_DRV_INFO_SIZE_8822C(rxdesc)                                \\\n\tGET_RX_DESC_DRV_INFO_SIZE(rxdesc)\n#define GET_RX_DESC_ICV_ERR_8822C(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)\n#define GET_RX_DESC_CRC32_8822C(rxdesc) GET_RX_DESC_CRC32(rxdesc)\n#define GET_RX_DESC_PKT_LEN_8822C(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)\n\n/*RXDESC_WORD1*/\n\n#define GET_RX_DESC_BC_8822C(rxdesc) GET_RX_DESC_BC(rxdesc)\n#define GET_RX_DESC_MC_8822C(rxdesc) GET_RX_DESC_MC(rxdesc)\n#define GET_RX_DESC_TY_PE_8822C(rxdesc) GET_RX_DESC_TY_PE(rxdesc)\n#define GET_RX_DESC_MF_8822C(rxdesc) GET_RX_DESC_MF(rxdesc)\n#define GET_RX_DESC_MD_8822C(rxdesc) GET_RX_DESC_MD(rxdesc)\n#define GET_RX_DESC_PWR_8822C(rxdesc) GET_RX_DESC_PWR(rxdesc)\n#define GET_RX_DESC_PAM_8822C(rxdesc) GET_RX_DESC_PAM(rxdesc)\n#define GET_RX_DESC_CHK_VLD_8822C(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)\n#define GET_RX_DESC_RX_IS_TCP_UDP_8822C(rxdesc)                                \\\n\tGET_RX_DESC_RX_IS_TCP_UDP(rxdesc)\n#define GET_RX_DESC_RX_IPV_8822C(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)\n#define GET_RX_DESC_CHKERR_8822C(rxdesc) GET_RX_DESC_CHKERR(rxdesc)\n#define GET_RX_DESC_PAGGR_8822C(rxdesc) GET_RX_DESC_PAGGR(rxdesc)\n#define GET_RX_DESC_RXID_MATCH_8822C(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)\n#define GET_RX_DESC_AMSDU_8822C(rxdesc) GET_RX_DESC_AMSDU(rxdesc)\n#define GET_RX_DESC_MACID_VLD_8822C(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)\n#define GET_RX_DESC_TID_8822C(rxdesc) GET_RX_DESC_TID(rxdesc)\n#define GET_RX_DESC_MACID_8822C(rxdesc) GET_RX_DESC_MACID(rxdesc)\n\n/*RXDESC_WORD2*/\n\n#define GET_RX_DESC_FCS_OK_8822C(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)\n#define GET_RX_DESC_PPDU_CNT_8822C(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)\n#define GET_RX_DESC_C2H_8822C(rxdesc) GET_RX_DESC_C2H(rxdesc)\n#define GET_RX_DESC_HWRSVD_8822C(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)\n#define GET_RX_DESC_WLANHD_IV_LEN_8822C(rxdesc)                                \\\n\tGET_RX_DESC_WLANHD_IV_LEN(rxdesc)\n#define GET_RX_DESC_RX_STATISTICS_8822C(rxdesc)                                \\\n\tGET_RX_DESC_RX_STATISTICS(rxdesc)\n#define GET_RX_DESC_RX_IS_QOS_8822C(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)\n#define GET_RX_DESC_FRAG_8822C(rxdesc) GET_RX_DESC_FRAG(rxdesc)\n#define GET_RX_DESC_SEQ_8822C(rxdesc) GET_RX_DESC_SEQ(rxdesc)\n\n/*RXDESC_WORD3*/\n\n#define GET_RX_DESC_MAGIC_WAKE_8822C(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)\n#define GET_RX_DESC_UNICAST_WAKE_8822C(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)\n#define GET_RX_DESC_PATTERN_MATCH_8822C(rxdesc)                                \\\n\tGET_RX_DESC_PATTERN_MATCH(rxdesc)\n#define GET_RX_DESC_RXPAYLOAD_MATCH_8822C(rxdesc)                              \\\n\tGET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)\n#define GET_RX_DESC_RXPAYLOAD_ID_8822C(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)\n#define GET_RX_DESC_DMA_AGG_NUM_8822C(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)\n#define GET_RX_DESC_BSSID_FIT_1_0_8822C(rxdesc)                                \\\n\tGET_RX_DESC_BSSID_FIT_1_0(rxdesc)\n#define GET_RX_DESC_EOSP_8822C(rxdesc) GET_RX_DESC_EOSP(rxdesc)\n#define GET_RX_DESC_HTC_8822C(rxdesc) GET_RX_DESC_HTC(rxdesc)\n#define GET_RX_DESC_BSSID_FIT_4_2_8822C(rxdesc)                                \\\n\tGET_RX_DESC_BSSID_FIT_4_2(rxdesc)\n#define GET_RX_DESC_RX_RATE_8822C(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)\n\n/*RXDESC_WORD4*/\n\n#define GET_RX_DESC_A1_FIT_8822C(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)\n#define GET_RX_DESC_MACID_RPT_BUFF_8822C(rxdesc)                               \\\n\tGET_RX_DESC_MACID_RPT_BUFF(rxdesc)\n#define GET_RX_DESC_RX_PRE_NDP_VLD_8822C(rxdesc)                               \\\n\tGET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)\n#define GET_RX_DESC_RX_SCRAMBLER_8822C(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)\n#define GET_RX_DESC_RX_EOF_8822C(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)\n#define GET_RX_DESC_PATTERN_IDX_8822C(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)\n\n/*RXDESC_WORD5*/\n\n#define GET_RX_DESC_TSFL_8822C(rxdesc) GET_RX_DESC_TSFL(rxdesc)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/*RXDESC_WORD0*/\n\n#define GET_RX_DESC_EOR_8192F(rxdesc) GET_RX_DESC_EOR(rxdesc)\n#define GET_RX_DESC_SWDEC_8192F(rxdesc) GET_RX_DESC_SWDEC(rxdesc)\n#define GET_RX_DESC_PHYST_8192F(rxdesc) GET_RX_DESC_PHYST(rxdesc)\n#define GET_RX_DESC_SHIFT_8192F(rxdesc) GET_RX_DESC_SHIFT(rxdesc)\n#define GET_RX_DESC_QOS_8192F(rxdesc) GET_RX_DESC_QOS(rxdesc)\n#define GET_RX_DESC_SECURITY_8192F(rxdesc) GET_RX_DESC_SECURITY(rxdesc)\n#define GET_RX_DESC_DRV_INFO_SIZE_8192F(rxdesc)                                \\\n\tGET_RX_DESC_DRV_INFO_SIZE(rxdesc)\n#define GET_RX_DESC_ICV_ERR_8192F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)\n#define GET_RX_DESC_CRC32_8192F(rxdesc) GET_RX_DESC_CRC32(rxdesc)\n#define GET_RX_DESC_PKT_LEN_8192F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)\n\n/*RXDESC_WORD1*/\n\n#define GET_RX_DESC_BC_8192F(rxdesc) GET_RX_DESC_BC(rxdesc)\n#define GET_RX_DESC_MC_8192F(rxdesc) GET_RX_DESC_MC(rxdesc)\n#define GET_RX_DESC_TY_PE_8192F(rxdesc) GET_RX_DESC_TY_PE(rxdesc)\n#define GET_RX_DESC_MF_8192F(rxdesc) GET_RX_DESC_MF(rxdesc)\n#define GET_RX_DESC_MD_8192F(rxdesc) GET_RX_DESC_MD(rxdesc)\n#define GET_RX_DESC_PWR_8192F(rxdesc) GET_RX_DESC_PWR(rxdesc)\n#define GET_RX_DESC_PAM_8192F(rxdesc) GET_RX_DESC_PAM(rxdesc)\n#define GET_RX_DESC_CHK_VLD_8192F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)\n#define GET_RX_DESC_RX_IS_TCP_UDP_8192F(rxdesc)                                \\\n\tGET_RX_DESC_RX_IS_TCP_UDP(rxdesc)\n#define GET_RX_DESC_RX_IPV_8192F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)\n#define GET_RX_DESC_CHKERR_8192F(rxdesc) GET_RX_DESC_CHKERR(rxdesc)\n#define GET_RX_DESC_PAGGR_8192F(rxdesc) GET_RX_DESC_PAGGR(rxdesc)\n#define GET_RX_DESC_RXID_MATCH_8192F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)\n#define GET_RX_DESC_AMSDU_8192F(rxdesc) GET_RX_DESC_AMSDU(rxdesc)\n#define GET_RX_DESC_MACID_VLD_8192F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)\n#define GET_RX_DESC_TID_8192F(rxdesc) GET_RX_DESC_TID(rxdesc)\n#define GET_RX_DESC_MACID_8192F(rxdesc) GET_RX_DESC_MACID(rxdesc)\n\n/*RXDESC_WORD2*/\n\n#define GET_RX_DESC_FCS_OK_8192F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)\n#define GET_RX_DESC_PPDU_CNT_8192F(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)\n#define GET_RX_DESC_C2H_8192F(rxdesc) GET_RX_DESC_C2H(rxdesc)\n#define GET_RX_DESC_HWRSVD_8192F(rxdesc) GET_RX_DESC_HWRSVD_V1(rxdesc)\n#define GET_RX_DESC_RXMAGPKT_8192F(rxdesc) GET_RX_DESC_RXMAGPKT(rxdesc)\n#define GET_RX_DESC_WLANHD_IV_LEN_8192F(rxdesc)                                \\\n\tGET_RX_DESC_WLANHD_IV_LEN(rxdesc)\n#define GET_RX_DESC_RX_IS_QOS_8192F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)\n#define GET_RX_DESC_FRAG_8192F(rxdesc) GET_RX_DESC_FRAG(rxdesc)\n#define GET_RX_DESC_SEQ_8192F(rxdesc) GET_RX_DESC_SEQ(rxdesc)\n\n/*RXDESC_WORD3*/\n\n#define GET_RX_DESC_MAGIC_WAKE_8192F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)\n#define GET_RX_DESC_UNICAST_WAKE_8192F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)\n#define GET_RX_DESC_PATTERN_MATCH_8192F(rxdesc)                                \\\n\tGET_RX_DESC_PATTERN_MATCH(rxdesc)\n#define GET_RX_DESC_DMA_AGG_NUM_8192F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)\n#define GET_RX_DESC_BSSID_FIT_1_0_8192F(rxdesc)                                \\\n\tGET_RX_DESC_BSSID_FIT_1_0(rxdesc)\n#define GET_RX_DESC_EOSP_8192F(rxdesc) GET_RX_DESC_EOSP(rxdesc)\n#define GET_RX_DESC_HTC_8192F(rxdesc) GET_RX_DESC_HTC(rxdesc)\n#define GET_RX_DESC_RX_RATE_8192F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)\n\n/*RXDESC_WORD4*/\n\n#define GET_RX_DESC_A1_FIT_8192F(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)\n#define GET_RX_DESC_MACID_RPT_BUFF_8192F(rxdesc)                               \\\n\tGET_RX_DESC_MACID_RPT_BUFF(rxdesc)\n#define GET_RX_DESC_SWPS_RPT_8192F(rxdesc) GET_RX_DESC_SWPS_RPT_V1(rxdesc)\n#define GET_RX_DESC_FC_POWER_8192F(rxdesc) GET_RX_DESC_FC_POWER_V1(rxdesc)\n#define GET_RX_DESC_TXRPTMID_CTL_MASK_8192F(rxdesc)                            \\\n\tGET_RX_DESC_TXRPTMID_CTL_MASK_V1(rxdesc)\n#define GET_RX_DESC_SNIF_INFO_8192F(rxdesc) GET_RX_DESC_SNIF_INFO(rxdesc)\n#define GET_RX_DESC_PATTERN_IDX_8192F(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)\n\n/*RXDESC_WORD5*/\n\n#define GET_RX_DESC_TSFL_8192F(rxdesc) GET_RX_DESC_TSFL(rxdesc)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n/*RXDESC_WORD0*/\n\n#define GET_RX_DESC_EOR_8812F(rxdesc) GET_RX_DESC_EOR(rxdesc)\n#define GET_RX_DESC_PHYPKTIDC_8812F(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)\n#define GET_RX_DESC_SWDEC_8812F(rxdesc) GET_RX_DESC_SWDEC(rxdesc)\n#define GET_RX_DESC_PHYST_8812F(rxdesc) GET_RX_DESC_PHYST(rxdesc)\n#define GET_RX_DESC_SHIFT_8812F(rxdesc) GET_RX_DESC_SHIFT(rxdesc)\n#define GET_RX_DESC_QOS_8812F(rxdesc) GET_RX_DESC_QOS(rxdesc)\n#define GET_RX_DESC_SECURITY_8812F(rxdesc) GET_RX_DESC_SECURITY(rxdesc)\n#define GET_RX_DESC_DRV_INFO_SIZE_8812F(rxdesc)                                \\\n\tGET_RX_DESC_DRV_INFO_SIZE(rxdesc)\n#define GET_RX_DESC_ICV_ERR_8812F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)\n#define GET_RX_DESC_CRC32_8812F(rxdesc) GET_RX_DESC_CRC32(rxdesc)\n#define GET_RX_DESC_PKT_LEN_8812F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)\n\n/*RXDESC_WORD1*/\n\n#define GET_RX_DESC_BC_8812F(rxdesc) GET_RX_DESC_BC(rxdesc)\n#define GET_RX_DESC_MC_8812F(rxdesc) GET_RX_DESC_MC(rxdesc)\n#define GET_RX_DESC_TY_PE_8812F(rxdesc) GET_RX_DESC_TY_PE(rxdesc)\n#define GET_RX_DESC_MF_8812F(rxdesc) GET_RX_DESC_MF(rxdesc)\n#define GET_RX_DESC_MD_8812F(rxdesc) GET_RX_DESC_MD(rxdesc)\n#define GET_RX_DESC_PWR_8812F(rxdesc) GET_RX_DESC_PWR(rxdesc)\n#define GET_RX_DESC_PAM_8812F(rxdesc) GET_RX_DESC_PAM(rxdesc)\n#define GET_RX_DESC_CHK_VLD_8812F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)\n#define GET_RX_DESC_RX_IS_TCP_UDP_8812F(rxdesc)                                \\\n\tGET_RX_DESC_RX_IS_TCP_UDP(rxdesc)\n#define GET_RX_DESC_RX_IPV_8812F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)\n#define GET_RX_DESC_CHKERR_8812F(rxdesc) GET_RX_DESC_CHKERR(rxdesc)\n#define GET_RX_DESC_PAGGR_8812F(rxdesc) GET_RX_DESC_PAGGR(rxdesc)\n#define GET_RX_DESC_RXID_MATCH_8812F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)\n#define GET_RX_DESC_AMSDU_8812F(rxdesc) GET_RX_DESC_AMSDU(rxdesc)\n#define GET_RX_DESC_MACID_VLD_8812F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)\n#define GET_RX_DESC_TID_8812F(rxdesc) GET_RX_DESC_TID(rxdesc)\n#define GET_RX_DESC_MACID_8812F(rxdesc) GET_RX_DESC_MACID(rxdesc)\n\n/*RXDESC_WORD2*/\n\n#define GET_RX_DESC_FCS_OK_8812F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)\n#define GET_RX_DESC_PPDU_CNT_8812F(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)\n#define GET_RX_DESC_C2H_8812F(rxdesc) GET_RX_DESC_C2H(rxdesc)\n#define GET_RX_DESC_HWRSVD_8812F(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)\n#define GET_RX_DESC_WLANHD_IV_LEN_8812F(rxdesc)                                \\\n\tGET_RX_DESC_WLANHD_IV_LEN(rxdesc)\n#define GET_RX_DESC_RX_STATISTICS_8812F(rxdesc)                                \\\n\tGET_RX_DESC_RX_STATISTICS(rxdesc)\n#define GET_RX_DESC_RX_IS_QOS_8812F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)\n#define GET_RX_DESC_FRAG_8812F(rxdesc) GET_RX_DESC_FRAG(rxdesc)\n#define GET_RX_DESC_SEQ_8812F(rxdesc) GET_RX_DESC_SEQ(rxdesc)\n\n/*RXDESC_WORD3*/\n\n#define GET_RX_DESC_MAGIC_WAKE_8812F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)\n#define GET_RX_DESC_UNICAST_WAKE_8812F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)\n#define GET_RX_DESC_PATTERN_MATCH_8812F(rxdesc)                                \\\n\tGET_RX_DESC_PATTERN_MATCH(rxdesc)\n#define GET_RX_DESC_RXPAYLOAD_MATCH_8812F(rxdesc)                              \\\n\tGET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)\n#define GET_RX_DESC_RXPAYLOAD_ID_8812F(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)\n#define GET_RX_DESC_DMA_AGG_NUM_8812F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)\n#define GET_RX_DESC_BSSID_FIT_1_0_8812F(rxdesc)                                \\\n\tGET_RX_DESC_BSSID_FIT_1_0(rxdesc)\n#define GET_RX_DESC_EOSP_8812F(rxdesc) GET_RX_DESC_EOSP(rxdesc)\n#define GET_RX_DESC_HTC_8812F(rxdesc) GET_RX_DESC_HTC(rxdesc)\n#define GET_RX_DESC_BSSID_FIT_4_2_8812F(rxdesc)                                \\\n\tGET_RX_DESC_BSSID_FIT_4_2(rxdesc)\n#define GET_RX_DESC_RX_RATE_8812F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)\n\n/*RXDESC_WORD4*/\n\n#define GET_RX_DESC_A1_FIT_8812F(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)\n#define GET_RX_DESC_MACID_RPT_BUFF_8812F(rxdesc)                               \\\n\tGET_RX_DESC_MACID_RPT_BUFF(rxdesc)\n#define GET_RX_DESC_RX_PRE_NDP_VLD_8812F(rxdesc)                               \\\n\tGET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)\n#define GET_RX_DESC_RX_SCRAMBLER_8812F(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)\n#define GET_RX_DESC_RX_EOF_8812F(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)\n#define GET_RX_DESC_PATTERN_IDX_8812F(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)\n\n/*RXDESC_WORD5*/\n\n#define GET_RX_DESC_TSFL_8812F(rxdesc) GET_RX_DESC_TSFL(rxdesc)\n\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_rx_desc_nic.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_RX_DESC_NIC_H_\n#define _HALMAC_RX_DESC_NIC_H_\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n/*RXDESC_WORD0*/\n\n#define GET_RX_DESC_EOR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 30, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_PHYPKTIDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 28, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_EVT_PKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 28, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_SWDEC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 27, 1)\n#define GET_RX_DESC_PHYST(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 26, 1)\n#define GET_RX_DESC_SHIFT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 24, 2)\n#define GET_RX_DESC_QOS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 23, 1)\n#define GET_RX_DESC_SECURITY(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 20, 3)\n#define GET_RX_DESC_DRV_INFO_SIZE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 16, 4)\n#define GET_RX_DESC_ICV_ERR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 15, 1)\n#define GET_RX_DESC_CRC32(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 14, 1)\n#define GET_RX_DESC_PKT_LEN(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 0, 14)\n\n/*RXDESC_WORD1*/\n\n#define GET_RX_DESC_BC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 31, 1)\n#define GET_RX_DESC_MC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 30, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_TY_PE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 28, 2)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_TYPE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 28, 2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_MF(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 27, 1)\n#define GET_RX_DESC_MD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 26, 1)\n#define GET_RX_DESC_PWR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 25, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_PAM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 24, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_A1_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 24, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_CHK_VLD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 23, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_TCP_CHKSUM_VLD(rxdesc)                                     \\\n\tLE_BITS_TO_4BYTE(rxdesc + 0x04, 23, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 22, 1)\n#define GET_RX_DESC_RX_IPV(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 21, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_CHKERR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 20, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_TCP_CHKSUM_ERR(rxdesc)                                     \\\n\tLE_BITS_TO_4BYTE(rxdesc + 0x04, 20, 1)\n#define GET_RX_DESC_PHY_PKT_IDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 17, 1)\n#define GET_RX_DESC_FW_FIFO_FULL(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 16, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_PAGGR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 15, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_AMPDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 15, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_RXID_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 14, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_RXCMD_IDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 14, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_AMSDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 13, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_MACID_VLD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 12, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_TID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 8, 4)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_MACID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 0, 7)\n\n/*RXDESC_WORD2*/\n\n#define GET_RX_DESC_FCS_OK(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 31, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_AMSDU_CUT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 31, 1)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_PPDU_CNT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 29, 2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_C2H(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 28, 1)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)\n\n#define GET_RX_DESC_HWRSVD_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 25, 3)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_HWRSVD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 24, 4)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)\n\n#define GET_RX_DESC_RXMAGPKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 24, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_WLANHD_IV_LEN(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 18, 6)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_LAST_MSDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 17, 1)\n\n#endif\n\n#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_RX_STATISTICS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 17, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_RX_IS_QOS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 16, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_EXT_SEC_TYPE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 16, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_FRAG(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 12, 4)\n#define GET_RX_DESC_SEQ(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 0, 12)\n\n/*RXDESC_WORD3*/\n\n#define GET_RX_DESC_MAGIC_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 31, 1)\n#define GET_RX_DESC_UNICAST_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 30, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_PATTERN_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 29, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_PATTERN_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 29, 1)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)                                    \\\n\tLE_BITS_TO_4BYTE(rxdesc + 0x0C, 28, 1)\n#define GET_RX_DESC_RXPAYLOAD_ID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 24, 4)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_DMA_AGG_NUM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 16, 8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_BSSID_FIT_1_0(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 12, 2)\n#define GET_RX_DESC_EOSP(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 11, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_BSSID_FIT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 11, 5)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_HTC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 10, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_AMPDU_END_PKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 9, 1)\n#define GET_RX_DESC_ADDRESS_CAM_VLD(rxdesc)                                    \\\n\tLE_BITS_TO_4BYTE(rxdesc + 0x0C, 8, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_BSSID_FIT_4_2(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 7, 3)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_EOSP_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 7, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_RX_RATE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 0, 7)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n/*RXDESC_WORD4*/\n\n#define GET_RX_DESC_A1_FIT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 5)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_ADDRESS_CAM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 8)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define GET_RX_DESC_A1_FIT_A1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 7)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_MACID_VLD_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 23, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_MACID_RPT_BUFF(rxdesc)                                     \\\n\tLE_BITS_TO_4BYTE(rxdesc + 0x10, 17, 7)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)                                     \\\n\tLE_BITS_TO_4BYTE(rxdesc + 0x10, 16, 1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define GET_RX_DESC_SWPS_RPT_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 16, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_MACID_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 15, 8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define GET_RX_DESC_FC_POWER_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 15, 1)\n#define GET_RX_DESC_TXRPTMID_CTL_MASK_V1(rxdesc)                               \\\n\tLE_BITS_TO_4BYTE(rxdesc + 0x10, 14, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_RX_SCRAMBLER(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 9, 7)\n#define GET_RX_DESC_RX_EOF(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 8, 1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define GET_RX_DESC_SNIF_INFO(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 8, 6)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define GET_RX_DESC_FC_POWER(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 7, 1)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc)                                  \\\n\tLE_BITS_TO_4BYTE(rxdesc + 0x10, 6, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define GET_RX_DESC_SWPS_RPT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 5, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define GET_RX_DESC_PATTERN_IDX(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 8)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define GET_RX_DESC_PATTERN_IDX_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 5)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_PATTERN_IDX_V2(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 5)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n/*RXDESC_WORD5*/\n\n#define GET_RX_DESC_TSFL(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x14, 0, 32)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define GET_RX_DESC_FREERUN_CNT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x14, 0, 32)\n\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_sdio_reg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef __HALMAC_SDIO_REG_H__\n#define __HALMAC_SDIO_REG_H__\n\n/* SDIO CMD address mapping */\n\n#define HALMAC_SDIO_4BYTE_LEN_MASK      0x1FFF\n#define HALMAC_SDIO_LOCAL_MSK           0x0FFF\n#define HALMAC_WLAN_MAC_REG_MSK\t\t0xFFFF\n#define\tHALMAC_WLAN_IOREG_MSK\t\t0xFFFF\n\n/* Sdio Address for SDIO Local Reg, TRX FIFO, MAC Reg */\nenum halmac_sdio_cmd_addr {\n\tHALMAC_SDIO_CMD_ADDR_SDIO_REG = 0,\n\tHALMAC_SDIO_CMD_ADDR_MAC_REG = 8,\n\tHALMAC_SDIO_CMD_ADDR_TXFF_HIGH = 4,\n\tHALMAC_SDIO_CMD_ADDR_TXFF_LOW = 6,\n\tHALMAC_SDIO_CMD_ADDR_TXFF_NORMAL = 5,\n\tHALMAC_SDIO_CMD_ADDR_TXFF_EXTRA = 7,\n\tHALMAC_SDIO_CMD_ADDR_RXFF = 7,\n};\n\n/* IO Bus domain address mapping */\n#define SDIO_LOCAL_OFFSET\t\t0x10250000\n#define WLAN_IOREG_OFFSET\t\t0x10260000\n#define FW_FIFO_OFFSET\t\t\t0x10270000\n#define TX_HIQ_OFFSET\t\t\t0x10310000\n#define TX_MIQ_OFFSET\t\t\t0x10320000\n#define TX_LOQ_OFFSET\t\t\t0x10330000\n#define TX_EXQ_OFFSET\t\t\t0x10350000\n#define RX_RXOFF_OFFSET\t\t\t0x10340000\n\n/* Get TX WLAN FIFO information in CMD53 addr  */\n#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT)\n#define GET_WLAN_TXFF_DEVICE_ID(cmd53_addr) \\\n\t\t\tLE_BITS_TO_4BYTE((u32 *)cmd53_addr, 13, 4)\n#define GET_WLAN_TXFF_PKT_SIZE(cmd53_addr) \\\n\t\t\t(LE_BITS_TO_4BYTE((u32 *)cmd53_addr, 0, 13) << 2)\n#endif\n\n#endif/* __HALMAC_SDIO_REG_H__ */\n"
  },
  {
    "path": "hal/halmac/halmac_state_machine.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_STATE_MACHINE_H_\n#define _HALMAC_STATE_MACHINE_H_\n\nenum halmac_dlfw_state {\n\tHALMAC_DLFW_NONE = 0,\n\tHALMAC_DLFW_DONE = 1,\n\tHALMAC_GEN_INFO_SENT = 2,\n\n\t/* Data CPU firmware download framework */\n\tHALMAC_DLFW_INIT = 0x11,\n\tHALMAC_DLFW_START = 0x12,\n\tHALMAC_DLFW_CONF_READY = 0x13,\n\tHALMAC_DLFW_CPU_READY = 0x14,\n\tHALMAC_DLFW_MEM_READY = 0x15,\n\tHALMAC_DLFW_SW_READY = 0x16,\n\tHALMAC_DLFW_OFLD_READY = 0x17,\n\n\tHALMAC_DLFW_UNDEFINED = 0x7F,\n};\n\nenum halmac_gpio_cfg_state {\n\tHALMAC_GPIO_CFG_STATE_IDLE = 0,\n\tHALMAC_GPIO_CFG_STATE_BUSY = 1,\n\tHALMAC_GPIO_CFG_STATE_UNDEFINED = 0x7F,\n};\n\nenum halmac_rsvd_pg_state {\n\tHALMAC_RSVD_PG_STATE_IDLE = 0,\n\tHALMAC_RSVD_PG_STATE_BUSY = 1,\n\tHALMAC_RSVD_PG_STATE_UNDEFINED = 0x7F,\n};\n\nenum halmac_api_state {\n\tHALMAC_API_STATE_INIT = 0,\n\tHALMAC_API_STATE_HALT = 1,\n\tHALMAC_API_STATE_UNDEFINED = 0x7F,\n};\n\nenum halmac_cmd_construct_state {\n\tHALMAC_CMD_CNSTR_IDLE = 0,\n\tHALMAC_CMD_CNSTR_BUSY = 1,\n\tHALMAC_CMD_CNSTR_H2C_SENT = 2,\n\tHALMAC_CMD_CNSTR_CNSTR = 3,\n\tHALMAC_CMD_CNSTR_BUF_CLR = 4,\n\tHALMAC_CMD_CNSTR_UNDEFINED = 0x7F,\n};\n\nenum halmac_cmd_process_status {\n\tHALMAC_CMD_PROCESS_IDLE = 0x01, /* Init status */\n\tHALMAC_CMD_PROCESS_SENDING = 0x02, /* Wait ack */\n\tHALMAC_CMD_PROCESS_RCVD = 0x03, /* Rcvd ack */\n\tHALMAC_CMD_PROCESS_DONE = 0x04, /* Event done */\n\tHALMAC_CMD_PROCESS_ERROR = 0x05, /* Return code error */\n\tHALMAC_CMD_PROCESS_UNDEFINE = 0x7F,\n};\n\nenum halmac_mac_power {\n\tHALMAC_MAC_POWER_OFF = 0x0,\n\tHALMAC_MAC_POWER_ON = 0x1,\n\tHALMAC_MAC_POWER_UNDEFINE = 0x7F,\n};\n\nenum halmac_wlcpu_mode {\n\tHALMAC_WLCPU_ACTIVE = 0x0,\n\tHALMAC_WLCPU_ENTER_SLEEP = 0x1,\n\tHALMAC_WLCPU_SLEEP = 0x2,\n\tHALMAC_WLCPU_UNDEFINE = 0x7F,\n};\n\nstruct halmac_efuse_state {\n\tenum halmac_cmd_construct_state cmd_cnstr_state;\n\tenum halmac_cmd_process_status proc_status;\n\tu8 fw_rc;\n\tu16 seq_num;\n};\n\nstruct halmac_cfg_param_state {\n\tenum halmac_cmd_construct_state cmd_cnstr_state;\n\tenum halmac_cmd_process_status proc_status;\n\tu8 fw_rc;\n\tu16 seq_num;\n};\n\nstruct halmac_scan_state {\n\tenum halmac_cmd_construct_state cmd_cnstr_state;\n\tenum halmac_cmd_process_status proc_status;\n\tu8 fw_rc;\n\tu16 seq_num;\n};\n\nstruct halmac_update_pkt_state {\n\tenum halmac_cmd_process_status proc_status;\n\tu8 fw_rc;\n\tu16 seq_num;\n};\n\nstruct halmac_iqk_state {\n\tenum halmac_cmd_process_status proc_status;\n\tu8 fw_rc;\n\tu16 seq_num;\n};\n\nstruct halmac_pwr_tracking_state {\n\tenum halmac_cmd_process_status\tproc_status;\n\tu8 fw_rc;\n\tu16 seq_num;\n};\n\nstruct halmac_psd_state {\n\tenum halmac_cmd_process_status proc_status;\n\tu16 data_size;\n\tu16 seg_size;\n\tu8 *data;\n\tu8 fw_rc;\n\tu16 seq_num;\n};\n\nstruct halmac_fw_snding_state {\n\tenum halmac_cmd_construct_state cmd_cnstr_state;\n\tenum halmac_cmd_process_status proc_status;\n\tu8 fw_rc;\n\tu16 seq_num;\n};\n\nstruct halmac_state {\n\tstruct halmac_efuse_state efuse_state;\n\tstruct halmac_cfg_param_state cfg_param_state;\n\tstruct halmac_scan_state scan_state;\n\tstruct halmac_update_pkt_state update_pkt_state;\n\tstruct halmac_iqk_state iqk_state;\n\tstruct halmac_pwr_tracking_state pwr_trk_state;\n\tstruct halmac_psd_state psd_state;\n\tstruct halmac_fw_snding_state fw_snding_state;\n\tenum halmac_api_state api_state;\n\tenum halmac_mac_power mac_pwr;\n\tenum halmac_dlfw_state dlfw_state;\n\tenum halmac_wlcpu_mode wlcpu_mode;\n\tenum halmac_gpio_cfg_state gpio_cfg_state;\n\tenum halmac_rsvd_pg_state rsvd_pg_state;\n};\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_tx_bd_nic.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_TX_BD_NIC_H_\n#define _HALMAC_TX_BD_NIC_H_\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n\tHALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||\\\n\tHALMAC_8812F_SUPPORT)\n\n/*TXBD_DW0*/\n\n#define SET_TX_BD_OWN(txbd, value)                                             \\\n\tSET_BITS_TO_LE_4BYTE(txbd + 0x00, 31, 1, value)\n#define GET_TX_BD_OWN(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 31, 1)\n#define SET_TX_BD_PSB(txbd, value)                                             \\\n\tSET_BITS_TO_LE_4BYTE(txbd + 0x00, 16, 8, value)\n#define GET_TX_BD_PSB(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 16, 8)\n#define SET_TX_BD_TX_BUFF_SIZE0(txbd, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txbd + 0x00, 0, 16, value)\n#define GET_TX_BD_TX_BUFF_SIZE0(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 0, 16)\n\n/*TXBD_DW1*/\n\n#define SET_TX_BD_PHYSICAL_ADDR0_LOW(txbd, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txbd + 0x04, 0, 32, value)\n#define GET_TX_BD_PHYSICAL_ADDR0_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x04, 0, 32)\n\n/*TXBD_DW2*/\n\n#define SET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txbd + 0x08, 0, 32, value)\n#define GET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x08, 0, 32)\n\n/*TXBD_DW4*/\n\n#define SET_TX_BD_A1(txbd, value)                                              \\\n\tSET_BITS_TO_LE_4BYTE(txbd + 0x10, 31, 1, value)\n#define GET_TX_BD_A1(txbd) LE_BITS_TO_4BYTE(txbd + 0x10, 31, 1)\n#define SET_TX_BD_TX_BUFF_SIZE1(txbd, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txbd + 0x10, 0, 16, value)\n#define GET_TX_BD_TX_BUFF_SIZE1(txbd) LE_BITS_TO_4BYTE(txbd + 0x10, 0, 16)\n\n/*TXBD_DW5*/\n\n#define SET_TX_BD_PHYSICAL_ADDR1_LOW(txbd, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txbd + 0x14, 0, 32, value)\n#define GET_TX_BD_PHYSICAL_ADDR1_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x14, 0, 32)\n\n/*TXBD_DW6*/\n\n#define SET_TX_BD_PHYSICAL_ADDR1_HIGH(txbd, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txbd + 0x18, 0, 32, value)\n#define GET_TX_BD_PHYSICAL_ADDR1_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x18, 0, 32)\n\n/*TXBD_DW8*/\n\n#define SET_TX_BD_A2(txbd, value)                                              \\\n\tSET_BITS_TO_LE_4BYTE(txbd + 0x20, 31, 1, value)\n#define GET_TX_BD_A2(txbd) LE_BITS_TO_4BYTE(txbd + 0x20, 31, 1)\n#define SET_TX_BD_TX_BUFF_SIZE2(txbd, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txbd + 0x20, 0, 16, value)\n#define GET_TX_BD_TX_BUFF_SIZE2(txbd) LE_BITS_TO_4BYTE(txbd + 0x20, 0, 16)\n\n/*TXBD_DW9*/\n\n#define SET_TX_BD_PHYSICAL_ADDR2_LOW(txbd, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txbd + 0x24, 0, 32, value)\n#define GET_TX_BD_PHYSICAL_ADDR2_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x24, 0, 32)\n\n/*TXBD_DW10*/\n\n#define SET_TX_BD_PHYSICAL_ADDR2_HIGH(txbd, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txbd + 0x28, 0, 32, value)\n#define GET_TX_BD_PHYSICAL_ADDR2_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x28, 0, 32)\n\n/*TXBD_DW12*/\n\n#define SET_TX_BD_A3(txbd, value)                                              \\\n\tSET_BITS_TO_LE_4BYTE(txbd + 0x30, 31, 1, value)\n#define GET_TX_BD_A3(txbd) LE_BITS_TO_4BYTE(txbd + 0x30, 31, 1)\n#define SET_TX_BD_TX_BUFF_SIZE3(txbd, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txbd + 0x30, 0, 16, value)\n#define GET_TX_BD_TX_BUFF_SIZE3(txbd) LE_BITS_TO_4BYTE(txbd + 0x30, 0, 16)\n\n/*TXBD_DW13*/\n\n#define SET_TX_BD_PHYSICAL_ADDR3_LOW(txbd, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txbd + 0x34, 0, 32, value)\n#define GET_TX_BD_PHYSICAL_ADDR3_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x34, 0, 32)\n\n/*TXBD_DW14*/\n\n#define SET_TX_BD_PHYSICAL_ADDR3_HIGH(txbd, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txbd + 0x38, 0, 32, value)\n#define GET_TX_BD_PHYSICAL_ADDR3_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x38, 0, 32)\n\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_tx_desc_ap.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_TX_DESC_AP_H_\n#define _HALMAC_TX_DESC_AP_H_\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n/*TXDESC_WORD0*/\n\n#define SET_TX_DESC_DISQSELSEQ(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0x1, 31)\n#define SET_TX_DESC_DISQSELSEQ_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 31)\n#define GET_TX_DESC_DISQSELSEQ(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \\\n\t\t\t      31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_IE_END_BODY(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0x1, 31)\n#define SET_TX_DESC_IE_END_BODY_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 31)\n#define GET_TX_DESC_IE_END_BODY(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \\\n\t\t\t      31)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_GF(txdesc, value)                                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0x1, 30)\n#define SET_TX_DESC_GF_NO_CLR(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 30)\n#define GET_TX_DESC_GF(txdesc)                                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \\\n\t\t\t      30)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_AGG_EN_V1(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0x1, 30)\n#define SET_TX_DESC_AGG_EN_V1_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 30)\n#define GET_TX_DESC_AGG_EN_V1(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \\\n\t\t\t      30)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_NO_ACM(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0x1, 29)\n#define SET_TX_DESC_NO_ACM_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 29)\n#define GET_TX_DESC_NO_ACM(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \\\n\t\t\t      29)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_BK_V1(txdesc, value)                                       \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0x1, 29)\n#define SET_TX_DESC_BK_V1_NO_CLR(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 29)\n#define GET_TX_DESC_BK_V1(txdesc)                                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \\\n\t\t\t      29)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0x1, 28)\n#define SET_TX_DESC_BCNPKT_TSF_CTRL_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 28)\n#define GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \\\n\t\t\t      28)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0x1, 27)\n#define SET_TX_DESC_AMSDU_PAD_EN_NO_CLR(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 27)\n#define GET_TX_DESC_AMSDU_PAD_EN(txdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \\\n\t\t\t      27)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_LS(txdesc, value)                                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0x1, 26)\n#define SET_TX_DESC_LS_NO_CLR(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 26)\n#define GET_TX_DESC_LS(txdesc)                                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \\\n\t\t\t      26)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_HTC(txdesc, value)                                         \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0x1, 25)\n#define SET_TX_DESC_HTC_NO_CLR(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 25)\n#define GET_TX_DESC_HTC(txdesc)                                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \\\n\t\t\t      25)\n#define SET_TX_DESC_BMC(txdesc, value)                                         \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0x1, 24)\n#define SET_TX_DESC_BMC_NO_CLR(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 24)\n#define GET_TX_DESC_BMC(txdesc)                                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_PKT_OFFSET_V1(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0x1f, 24)\n#define SET_TX_DESC_PKT_OFFSET_V1_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1f, 24)\n#define GET_TX_DESC_PKT_OFFSET_V1(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1f, \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_OFFSET(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0xff, 16)\n#define SET_TX_DESC_OFFSET_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0xff, 16)\n#define GET_TX_DESC_OFFSET(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0xff, \\\n\t\t\t      16)\n#define SET_TX_DESC_TXPKTSIZE(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0xffff, 0)\n#define SET_TX_DESC_TXPKTSIZE_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0xffff, 0)\n#define GET_TX_DESC_TXPKTSIZE(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0,       \\\n\t\t\t      0xffff, 0)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/*WORD1*/\n\n#define SET_TX_DESC_HW_AES_IV_V2(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 31)\n#define SET_TX_DESC_HW_AES_IV_V2_NO_CLR(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 31)\n#define GET_TX_DESC_HW_AES_IV_V2(txdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_AMSDU(txdesc, value)                                       \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 30)\n#define SET_TX_DESC_AMSDU_NO_CLR(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30)\n#define GET_TX_DESC_AMSDU(txdesc)                                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      30)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_FTM_EN_V1(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 30)\n#define SET_TX_DESC_FTM_EN_V1_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30)\n#define GET_TX_DESC_FTM_EN_V1(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      30)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_KEYID_SEL(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 30)\n#define SET_TX_DESC_KEYID_SEL_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30)\n#define GET_TX_DESC_KEYID_SEL(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      30)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_MOREDATA(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 29)\n#define SET_TX_DESC_MOREDATA_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 29)\n#define GET_TX_DESC_MOREDATA(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      29)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_HW_AES_IV_V1(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 29)\n#define SET_TX_DESC_HW_AES_IV_V1_NO_CLR(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 29)\n#define GET_TX_DESC_HW_AES_IV_V1(txdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      29)\n#define SET_TX_DESC_MHR_CP(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 25)\n#define SET_TX_DESC_MHR_CP_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 25)\n#define GET_TX_DESC_MHR_CP(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      25)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_PKT_OFFSET(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1f, 24)\n#define SET_TX_DESC_PKT_OFFSET_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 24)\n#define GET_TX_DESC_PKT_OFFSET(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_SMH_EN_V1(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 24)\n#define SET_TX_DESC_SMH_EN_V1_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 24)\n#define GET_TX_DESC_SMH_EN_V1(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_SEC_TYPE(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x3, 22)\n#define SET_TX_DESC_SEC_TYPE_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x3, 22)\n#define GET_TX_DESC_SEC_TYPE(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x3,  \\\n\t\t\t      22)\n#define SET_TX_DESC_EN_DESC_ID(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 21)\n#define SET_TX_DESC_EN_DESC_ID_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 21)\n#define GET_TX_DESC_EN_DESC_ID(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      21)\n#define SET_TX_DESC_RATE_ID(txdesc, value)                                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1f, 16)\n#define SET_TX_DESC_RATE_ID_NO_CLR(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 16)\n#define GET_TX_DESC_RATE_ID(txdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \\\n\t\t\t      16)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_SMH_CAM(txdesc, value)                                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0xff, 16)\n#define SET_TX_DESC_SMH_CAM_NO_CLR(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0xff, 16)\n#define GET_TX_DESC_SMH_CAM(txdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0xff, \\\n\t\t\t      16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_PIFS(txdesc, value)                                        \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 15)\n#define SET_TX_DESC_PIFS_NO_CLR(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 15)\n#define GET_TX_DESC_PIFS(txdesc)                                               \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      15)\n#define SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 14)\n#define SET_TX_DESC_LSIG_TXOP_EN_NO_CLR(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 14)\n#define GET_TX_DESC_LSIG_TXOP_EN(txdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      14)\n#define SET_TX_DESC_RD_NAV_EXT(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 13)\n#define SET_TX_DESC_RD_NAV_EXT_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 13)\n#define GET_TX_DESC_RD_NAV_EXT(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      13)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_EXT_EDCA(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 13)\n#define SET_TX_DESC_EXT_EDCA_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 13)\n#define GET_TX_DESC_EXT_EDCA(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      13)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_QSEL(txdesc, value)                                        \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1f, 8)\n#define SET_TX_DESC_QSEL_NO_CLR(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 8)\n#define GET_TX_DESC_QSEL(txdesc)                                               \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \\\n\t\t\t      8)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_SPECIAL_CW(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 7)\n#define SET_TX_DESC_SPECIAL_CW_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 7)\n#define GET_TX_DESC_SPECIAL_CW(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, 7)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_MACID(txdesc, value)                                       \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x7f, 0)\n#define SET_TX_DESC_MACID_NO_CLR(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x7f, 0)\n#define GET_TX_DESC_MACID(txdesc)                                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x7f, \\\n\t\t\t      0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_MACID_V1(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x7f, 0)\n#define SET_TX_DESC_MACID_V1_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x7f, 0)\n#define GET_TX_DESC_MACID_V1(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x7f, \\\n\t\t\t      0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n/*TXDESC_WORD2*/\n\n#define SET_TX_DESC_HW_AES_IV(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1, 31)\n#define SET_TX_DESC_HW_AES_IV_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 31)\n#define GET_TX_DESC_HW_AES_IV(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \\\n\t\t\t      31)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_CHK_EN_V1(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1, 31)\n#define SET_TX_DESC_CHK_EN_V1_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 31)\n#define GET_TX_DESC_CHK_EN_V1(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \\\n\t\t\t      31)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_FTM_EN(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1, 30)\n#define SET_TX_DESC_FTM_EN_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 30)\n#define GET_TX_DESC_FTM_EN(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \\\n\t\t\t      30)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANTCEL_D_V1(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0xf, 28)\n#define SET_TX_DESC_ANTCEL_D_V1_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0xf, 28)\n#define GET_TX_DESC_ANTCEL_D_V1(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xf,  \\\n\t\t\t      28)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_DMA_PRI(txdesc, value)                                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1, 27)\n#define SET_TX_DESC_DMA_PRI_NO_CLR(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 27)\n#define GET_TX_DESC_DMA_PRI(txdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \\\n\t\t\t      27)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_G_ID(txdesc, value)                                        \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x3f, 24)\n#define SET_TX_DESC_G_ID_NO_CLR(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x3f, 24)\n#define GET_TX_DESC_G_ID(txdesc)                                               \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x3f, \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_MAX_AMSDU_MODE(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x7, 24)\n#define SET_TX_DESC_MAX_AMSDU_MODE_NO_CLR(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x7, 24)\n#define GET_TX_DESC_MAX_AMSDU_MODE(txdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x7,  \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_C_V1(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0xf, 24)\n#define SET_TX_DESC_ANTSEL_C_V1_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0xf, 24)\n#define GET_TX_DESC_ANTSEL_C_V1(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xf,  \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_BT_NULL(txdesc, value)                                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1, 23)\n#define SET_TX_DESC_BT_NULL_NO_CLR(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 23)\n#define GET_TX_DESC_BT_NULL(txdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \\\n\t\t\t      23)\n#define SET_TX_DESC_AMPDU_DENSITY(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x7, 20)\n#define SET_TX_DESC_AMPDU_DENSITY_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x7, 20)\n#define GET_TX_DESC_AMPDU_DENSITY(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x7,  \\\n\t\t\t      20)\n#define SET_TX_DESC_SPE_RPT(txdesc, value)                                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1, 19)\n#define SET_TX_DESC_SPE_RPT_NO_CLR(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 19)\n#define GET_TX_DESC_SPE_RPT(txdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \\\n\t\t\t      19)\n#define SET_TX_DESC_RAW(txdesc, value)                                         \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1, 18)\n#define SET_TX_DESC_RAW_NO_CLR(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 18)\n#define GET_TX_DESC_RAW(txdesc)                                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \\\n\t\t\t      18)\n#define SET_TX_DESC_MOREFRAG(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1, 17)\n#define SET_TX_DESC_MOREFRAG_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 17)\n#define GET_TX_DESC_MOREFRAG(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \\\n\t\t\t      17)\n#define SET_TX_DESC_BK(txdesc, value)                                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1, 16)\n#define SET_TX_DESC_BK_NO_CLR(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 16)\n#define GET_TX_DESC_BK(txdesc)                                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \\\n\t\t\t      16)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0xff, 16)\n#define SET_TX_DESC_DMA_TXAGG_NUM_V1_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0xff, 16)\n#define GET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xff, \\\n\t\t\t      16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_NULL_1(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1, 15)\n#define SET_TX_DESC_NULL_1_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 15)\n#define GET_TX_DESC_NULL_1(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \\\n\t\t\t      15)\n#define SET_TX_DESC_NULL_0(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1, 14)\n#define SET_TX_DESC_NULL_0_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 14)\n#define GET_TX_DESC_NULL_0(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \\\n\t\t\t      14)\n#define SET_TX_DESC_RDG_EN(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1, 13)\n#define SET_TX_DESC_RDG_EN_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 13)\n#define GET_TX_DESC_RDG_EN(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \\\n\t\t\t      13)\n#define SET_TX_DESC_AGG_EN(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1, 12)\n#define SET_TX_DESC_AGG_EN_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 12)\n#define GET_TX_DESC_AGG_EN(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \\\n\t\t\t      12)\n#define SET_TX_DESC_CCA_RTS(txdesc, value)                                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x3, 10)\n#define SET_TX_DESC_CCA_RTS_NO_CLR(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x3, 10)\n#define GET_TX_DESC_CCA_RTS(txdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x3,  \\\n\t\t\t      10)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_TRI_FRAME(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1, 9)\n#define SET_TX_DESC_TRI_FRAME_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 9)\n#define GET_TX_DESC_TRI_FRAME(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, 9)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_P_AID(txdesc, value)                                       \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1ff, 0)\n#define SET_TX_DESC_P_AID_NO_CLR(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1ff, 0)\n#define GET_TX_DESC_P_AID(txdesc)                                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2,       \\\n\t\t\t      0x1ff, 0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0xffff, 0)\n#define SET_TX_DESC_TXDESC_CHECKSUM_V1_NO_CLR(txdesc, value)                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0xffff, 0)\n#define GET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc)                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2,       \\\n\t\t\t      0xffff, 0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n/*TXDESC_WORD3*/\n\n#define SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0xff, 24)\n#define SET_TX_DESC_AMPDU_MAX_TIME_NO_CLR(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0xff, 24)\n#define GET_TX_DESC_AMPDU_MAX_TIME(txdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0xff, \\\n\t\t\t      24)\n#define SET_TX_DESC_NDPA(txdesc, value)                                        \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x3, 22)\n#define SET_TX_DESC_NDPA_NO_CLR(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x3, 22)\n#define GET_TX_DESC_NDPA(txdesc)                                               \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x3,  \\\n\t\t\t      22)\n#define SET_TX_DESC_MAX_AGG_NUM(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x1f, 17)\n#define SET_TX_DESC_MAX_AGG_NUM_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 17)\n#define GET_TX_DESC_MAX_AGG_NUM(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \\\n\t\t\t      17)\n#define SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x1, 16)\n#define SET_TX_DESC_USE_MAX_TIME_EN_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 16)\n#define GET_TX_DESC_USE_MAX_TIME_EN(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1,  \\\n\t\t\t      16)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_OFFLOAD_SIZE(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x7fff, 16)\n#define SET_TX_DESC_OFFLOAD_SIZE_NO_CLR(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x7fff, 16)\n#define GET_TX_DESC_OFFLOAD_SIZE(txdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3,       \\\n\t\t\t      0x7fff, 16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_NAVUSEHDR(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x1, 15)\n#define SET_TX_DESC_NAVUSEHDR_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 15)\n#define GET_TX_DESC_NAVUSEHDR(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1,  \\\n\t\t\t      15)\n#define SET_TX_DESC_CHK_EN(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x1, 14)\n#define SET_TX_DESC_CHK_EN_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 14)\n#define GET_TX_DESC_CHK_EN(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1,  \\\n\t\t\t      14)\n#define SET_TX_DESC_HW_RTS_EN(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x1, 13)\n#define SET_TX_DESC_HW_RTS_EN_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 13)\n#define GET_TX_DESC_HW_RTS_EN(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1,  \\\n\t\t\t      13)\n#define SET_TX_DESC_RTSEN(txdesc, value)                                       \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x1, 12)\n#define SET_TX_DESC_RTSEN_NO_CLR(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 12)\n#define GET_TX_DESC_RTSEN(txdesc)                                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1,  \\\n\t\t\t      12)\n#define SET_TX_DESC_CTS2SELF(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x1, 11)\n#define SET_TX_DESC_CTS2SELF_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 11)\n#define GET_TX_DESC_CTS2SELF(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1,  \\\n\t\t\t      11)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_CHANNEL_DMA(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x1f, 11)\n#define SET_TX_DESC_CHANNEL_DMA_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 11)\n#define GET_TX_DESC_CHANNEL_DMA(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \\\n\t\t\t      11)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_DISDATAFB(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x1, 10)\n#define SET_TX_DESC_DISDATAFB_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 10)\n#define GET_TX_DESC_DISDATAFB(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1,  \\\n\t\t\t      10)\n#define SET_TX_DESC_DISRTSFB(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x1, 9)\n#define SET_TX_DESC_DISRTSFB_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 9)\n#define GET_TX_DESC_DISRTSFB(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 9)\n#define SET_TX_DESC_USE_RATE(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x1, 8)\n#define SET_TX_DESC_USE_RATE_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 8)\n#define GET_TX_DESC_USE_RATE(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 8)\n#define SET_TX_DESC_HW_SSN_SEL(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x3, 6)\n#define SET_TX_DESC_HW_SSN_SEL_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x3, 6)\n#define GET_TX_DESC_HW_SSN_SEL(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x3, 6)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_IE_CNT(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x7, 6)\n#define SET_TX_DESC_IE_CNT_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x7, 6)\n#define GET_TX_DESC_IE_CNT(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x7, 6)\n#define SET_TX_DESC_IE_CNT_EN(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x1, 5)\n#define SET_TX_DESC_IE_CNT_EN_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 5)\n#define GET_TX_DESC_IE_CNT_EN(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 5)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_WHEADER_LEN(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x1f, 0)\n#define SET_TX_DESC_WHEADER_LEN_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 0)\n#define GET_TX_DESC_WHEADER_LEN(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \\\n\t\t\t      0)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_WHEADER_LEN_V1(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x1f, 0)\n#define SET_TX_DESC_WHEADER_LEN_V1_NO_CLR(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 0)\n#define GET_TX_DESC_WHEADER_LEN_V1(txdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \\\n\t\t\t      0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n/*TXDESC_WORD4*/\n\n#define SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \\\n\t\t\t\t  value, 0x3, 30)\n#define SET_TX_DESC_PCTS_MASK_IDX_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword4, value, 0x3, 30)\n#define GET_TX_DESC_PCTS_MASK_IDX(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x3,  \\\n\t\t\t      30)\n#define SET_TX_DESC_PCTS_EN(txdesc, value)                                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \\\n\t\t\t\t  value, 0x1, 29)\n#define SET_TX_DESC_PCTS_EN_NO_CLR(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 29)\n#define GET_TX_DESC_PCTS_EN(txdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1,  \\\n\t\t\t      29)\n#define SET_TX_DESC_RTSRATE(txdesc, value)                                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \\\n\t\t\t\t  value, 0x1f, 24)\n#define SET_TX_DESC_RTSRATE_NO_CLR(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1f, 24)\n#define GET_TX_DESC_RTSRATE(txdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1f, \\\n\t\t\t      24)\n#define SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \\\n\t\t\t\t  value, 0x3f, 18)\n#define SET_TX_DESC_RTS_DATA_RTY_LMT_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword4, value, 0x3f, 18)\n#define GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x3f, \\\n\t\t\t      18)\n#define SET_TX_DESC_RTY_LMT_EN(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \\\n\t\t\t\t  value, 0x1, 17)\n#define SET_TX_DESC_RTY_LMT_EN_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 17)\n#define GET_TX_DESC_RTY_LMT_EN(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1,  \\\n\t\t\t      17)\n#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \\\n\t\t\t\t  value, 0xf, 13)\n#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_NO_CLR(txdesc, value)                  \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword4, value, 0xf, 13)\n#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0xf,  \\\n\t\t\t      13)\n#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \\\n\t\t\t\t  value, 0x1f, 8)\n#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_NO_CLR(txdesc, value)                 \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1f, 8)\n#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)                               \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1f, \\\n\t\t\t      8)\n#define SET_TX_DESC_TRY_RATE(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \\\n\t\t\t\t  value, 0x1, 7)\n#define SET_TX_DESC_TRY_RATE_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 7)\n#define GET_TX_DESC_TRY_RATE(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, 7)\n#define SET_TX_DESC_DATARATE(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \\\n\t\t\t\t  value, 0x7f, 0)\n#define SET_TX_DESC_DATARATE_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword4, value, 0x7f, 0)\n#define GET_TX_DESC_DATARATE(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x7f, \\\n\t\t\t      0)\n\n/*TXDESC_WORD5*/\n\n#define SET_TX_DESC_POLLUTED(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x1, 31)\n#define SET_TX_DESC_POLLUTED_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 31)\n#define GET_TX_DESC_POLLUTED(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \\\n\t\t\t      31)\n\n#endif\n\n#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_EN_V1(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x1, 30)\n#define SET_TX_DESC_ANTSEL_EN_V1_NO_CLR(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 30)\n#define GET_TX_DESC_ANTSEL_EN_V1(txdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \\\n\t\t\t      30)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_TXPWR_OFSET(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x7, 28)\n#define SET_TX_DESC_TXPWR_OFSET_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 28)\n#define GET_TX_DESC_TXPWR_OFSET(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7,  \\\n\t\t\t      28)\n\n#endif\n\n#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x3, 28)\n#define SET_TX_DESC_TXPWR_OFSET_TYPE_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 28)\n#define GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3,  \\\n\t\t\t      28)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x7, 28)\n#define SET_TX_DESC_TXPWR_OFSET_TYPE_V1_NO_CLR(txdesc, value)                  \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 28)\n#define GET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc)                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7,  \\\n\t\t\t      28)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_TX_ANT(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0xf, 24)\n#define SET_TX_DESC_TX_ANT_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 24)\n#define GET_TX_DESC_TX_ANT(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf,  \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_DROP_ID(txdesc, value)                                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x3, 24)\n#define SET_TX_DESC_DROP_ID_NO_CLR(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 24)\n#define GET_TX_DESC_DROP_ID(txdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3,  \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_DROP_ID_V1(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x3, 22)\n#define SET_TX_DESC_DROP_ID_V1_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 22)\n#define GET_TX_DESC_DROP_ID_V1(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3,  \\\n\t\t\t      22)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_PORT_ID(txdesc, value)                                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x7, 21)\n#define SET_TX_DESC_PORT_ID_NO_CLR(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 21)\n#define GET_TX_DESC_PORT_ID(txdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7,  \\\n\t\t\t      21)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_PORT_ID_V1(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x1, 21)\n#define SET_TX_DESC_PORT_ID_V1_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 21)\n#define GET_TX_DESC_PORT_ID_V1(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \\\n\t\t\t      21)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_MULTIPLE_PORT(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x7, 18)\n#define SET_TX_DESC_MULTIPLE_PORT_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 18)\n#define GET_TX_DESC_MULTIPLE_PORT(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7,  \\\n\t\t\t      18)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x1, 17)\n#define SET_TX_DESC_SIGNALING_TAPKT_EN_NO_CLR(txdesc, value)                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 17)\n#define GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \\\n\t\t\t      17)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_RTS_SC(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0xf, 13)\n#define SET_TX_DESC_RTS_SC_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 13)\n#define GET_TX_DESC_RTS_SC(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf,  \\\n\t\t\t      13)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0xf, 13)\n#define SET_TX_DESC_SIGNALING_TA_PKT_SC_NO_CLR(txdesc, value)                  \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 13)\n#define GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf,  \\\n\t\t\t      13)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_RTS_SHORT(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x1, 12)\n#define SET_TX_DESC_RTS_SHORT_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 12)\n#define GET_TX_DESC_RTS_SHORT(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \\\n\t\t\t      12)\n#define SET_TX_DESC_VCS_STBC(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x3, 10)\n#define SET_TX_DESC_VCS_STBC_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 10)\n#define GET_TX_DESC_VCS_STBC(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3,  \\\n\t\t\t      10)\n#define SET_TX_DESC_DATA_STBC(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x3, 8)\n#define SET_TX_DESC_DATA_STBC_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 8)\n#define GET_TX_DESC_DATA_STBC(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, 8)\n#define SET_TX_DESC_DATA_LDPC(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x1, 7)\n#define SET_TX_DESC_DATA_LDPC_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 7)\n#define GET_TX_DESC_DATA_LDPC(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 7)\n#define SET_TX_DESC_DATA_BW(txdesc, value)                                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x3, 5)\n#define SET_TX_DESC_DATA_BW_NO_CLR(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 5)\n#define GET_TX_DESC_DATA_BW(txdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, 5)\n#define SET_TX_DESC_DATA_SHORT(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x1, 4)\n#define SET_TX_DESC_DATA_SHORT_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 4)\n#define GET_TX_DESC_DATA_SHORT(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 4)\n#define SET_TX_DESC_DATA_SC(txdesc, value)                                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0xf, 0)\n#define SET_TX_DESC_DATA_SC_NO_CLR(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 0)\n#define GET_TX_DESC_DATA_SC(txdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf, 0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n/*TXDESC_WORD6*/\n\n#define SET_TX_DESC_ANTSEL_D(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 30)\n#define SET_TX_DESC_ANTSEL_D_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 30)\n#define GET_TX_DESC_ANTSEL_D(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      30)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPD_V1(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 30)\n#define SET_TX_DESC_ANT_MAPD_V1_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 30)\n#define GET_TX_DESC_ANT_MAPD_V1(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      30)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPC_V2(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 30)\n#define SET_TX_DESC_ANT_MAPC_V2_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 30)\n#define GET_TX_DESC_ANT_MAPC_V2(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      30)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPD(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 28)\n#define SET_TX_DESC_ANT_MAPD_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 28)\n#define GET_TX_DESC_ANT_MAPD(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      28)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPC_V1(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 28)\n#define SET_TX_DESC_ANT_MAPC_V1_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 28)\n#define GET_TX_DESC_ANT_MAPC_V1(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      28)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPB_V2(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 28)\n#define SET_TX_DESC_ANT_MAPB_V2_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 28)\n#define GET_TX_DESC_ANT_MAPB_V2(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      28)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPC(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 26)\n#define SET_TX_DESC_ANT_MAPC_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 26)\n#define GET_TX_DESC_ANT_MAPC(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      26)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPB_V1(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 26)\n#define SET_TX_DESC_ANT_MAPB_V1_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 26)\n#define GET_TX_DESC_ANT_MAPB_V1(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      26)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPA_V2(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 26)\n#define SET_TX_DESC_ANT_MAPA_V2_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 26)\n#define GET_TX_DESC_ANT_MAPA_V2(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      26)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPB(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 24)\n#define SET_TX_DESC_ANT_MAPB_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 24)\n#define GET_TX_DESC_ANT_MAPB(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPA_V1(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 24)\n#define SET_TX_DESC_ANT_MAPA_V1_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 24)\n#define GET_TX_DESC_ANT_MAPA_V1(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_D_V1(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 24)\n#define SET_TX_DESC_ANTSEL_D_V1_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 24)\n#define GET_TX_DESC_ANTSEL_D_V1(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPA(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 22)\n#define SET_TX_DESC_ANT_MAPA_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 22)\n#define GET_TX_DESC_ANT_MAPA(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      22)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_C_V2(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 22)\n#define SET_TX_DESC_ANTSEL_C_V2_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 22)\n#define GET_TX_DESC_ANTSEL_C_V2(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      22)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_C(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 20)\n#define SET_TX_DESC_ANTSEL_C_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 20)\n#define GET_TX_DESC_ANTSEL_C(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      20)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_B_V1(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0xf, 20)\n#define SET_TX_DESC_ANTSEL_B_V1_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0xf, 20)\n#define GET_TX_DESC_ANTSEL_B_V1(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0xf,  \\\n\t\t\t      20)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_B_V2(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x7, 19)\n#define SET_TX_DESC_ANTSEL_B_V2_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x7, 19)\n#define GET_TX_DESC_ANTSEL_B_V2(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x7,  \\\n\t\t\t      19)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_B(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 18)\n#define SET_TX_DESC_ANTSEL_B_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 18)\n#define GET_TX_DESC_ANTSEL_B(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      18)\n#define SET_TX_DESC_ANTSEL_A(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 16)\n#define SET_TX_DESC_ANTSEL_A_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 16)\n#define GET_TX_DESC_ANTSEL_A(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      16)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_A_V1(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0xf, 16)\n#define SET_TX_DESC_ANTSEL_A_V1_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0xf, 16)\n#define GET_TX_DESC_ANTSEL_A_V1(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0xf,  \\\n\t\t\t      16)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_A_V2(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x7, 16)\n#define SET_TX_DESC_ANTSEL_A_V2_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x7, 16)\n#define GET_TX_DESC_ANTSEL_A_V2(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x7,  \\\n\t\t\t      16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_MBSSID(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0xf, 12)\n#define SET_TX_DESC_MBSSID_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0xf, 12)\n#define GET_TX_DESC_MBSSID(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0xf,  \\\n\t\t\t      12)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_SW_DEFINE(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0xfff, 0)\n#define SET_TX_DESC_SW_DEFINE_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0xfff, 0)\n#define GET_TX_DESC_SW_DEFINE(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6,       \\\n\t\t\t      0xfff, 0)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_SWPS_SEQ(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0xfff, 0)\n#define SET_TX_DESC_SWPS_SEQ_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0xfff, 0)\n#define GET_TX_DESC_SWPS_SEQ(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6,       \\\n\t\t\t      0xfff, 0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n/*TXDESC_WORD7*/\n\n#define SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \\\n\t\t\t\t  value, 0xff, 24)\n#define SET_TX_DESC_DMA_TXAGG_NUM_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword7, value, 0xff, 24)\n#define GET_TX_DESC_DMA_TXAGG_NUM(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xff, \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \\\n\t\t\t\t  value, 0xff, 24)\n#define SET_TX_DESC_FINAL_DATA_RATE_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword7, value, 0xff, 24)\n#define GET_TX_DESC_FINAL_DATA_RATE(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xff, \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPD_V2(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \\\n\t\t\t\t  value, 0x3, 22)\n#define SET_TX_DESC_ANT_MAPD_V2_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword7, value, 0x3, 22)\n#define GET_TX_DESC_ANT_MAPD_V2(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x3,  \\\n\t\t\t      22)\n#define SET_TX_DESC_ANTSEL_EN_V2(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \\\n\t\t\t\t  value, 0x1, 21)\n#define SET_TX_DESC_ANTSEL_EN_V2_NO_CLR(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1, 21)\n#define GET_TX_DESC_ANTSEL_EN_V2(txdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1,  \\\n\t\t\t      21)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_NTX_MAP(txdesc, value)                                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \\\n\t\t\t\t  value, 0xf, 20)\n#define SET_TX_DESC_NTX_MAP_NO_CLR(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword7, value, 0xf, 20)\n#define GET_TX_DESC_NTX_MAP(txdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xf,  \\\n\t\t\t      20)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_EN(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \\\n\t\t\t\t  value, 0x1, 19)\n#define SET_TX_DESC_ANTSEL_EN_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1, 19)\n#define GET_TX_DESC_ANTSEL_EN(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1,  \\\n\t\t\t      19)\n#define SET_TX_DESC_MBSSID_EX(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \\\n\t\t\t\t  value, 0x7, 16)\n#define SET_TX_DESC_MBSSID_EX_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword7, value, 0x7, 16)\n#define GET_TX_DESC_MBSSID_EX(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x7,  \\\n\t\t\t      16)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_MBSSID_EX_V1(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \\\n\t\t\t\t  value, 0x1, 16)\n#define SET_TX_DESC_MBSSID_EX_V1_NO_CLR(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1, 16)\n#define GET_TX_DESC_MBSSID_EX_V1(txdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1,  \\\n\t\t\t      16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \\\n\t\t\t\t  value, 0xffff, 0)\n#define SET_TX_DESC_TX_BUFF_SIZE_NO_CLR(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword7, value, 0xffff, 0)\n#define GET_TX_DESC_TX_BUFF_SIZE(txdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7,       \\\n\t\t\t      0xffff, 0)\n#define SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \\\n\t\t\t\t  value, 0xffff, 0)\n#define SET_TX_DESC_TXDESC_CHECKSUM_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword7, value, 0xffff, 0)\n#define GET_TX_DESC_TXDESC_CHECKSUM(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7,       \\\n\t\t\t      0xffff, 0)\n#define SET_TX_DESC_TIMESTAMP(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \\\n\t\t\t\t  value, 0xffff, 0)\n#define SET_TX_DESC_TIMESTAMP_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword7, value, 0xffff, 0)\n#define GET_TX_DESC_TIMESTAMP(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7,       \\\n\t\t\t      0xffff, 0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n/*TXDESC_WORD8*/\n\n#define SET_TX_DESC_TXWIFI_CP(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x1, 31)\n#define SET_TX_DESC_TXWIFI_CP_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 31)\n#define GET_TX_DESC_TXWIFI_CP(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \\\n\t\t\t      31)\n#define SET_TX_DESC_MAC_CP(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x1, 30)\n#define SET_TX_DESC_MAC_CP_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 30)\n#define GET_TX_DESC_MAC_CP(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \\\n\t\t\t      30)\n#define SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x1, 29)\n#define SET_TX_DESC_STW_PKTRE_DIS_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 29)\n#define GET_TX_DESC_STW_PKTRE_DIS(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \\\n\t\t\t      29)\n#define SET_TX_DESC_STW_RB_DIS(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x1, 28)\n#define SET_TX_DESC_STW_RB_DIS_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 28)\n#define GET_TX_DESC_STW_RB_DIS(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \\\n\t\t\t      28)\n#define SET_TX_DESC_STW_RATE_DIS(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x1, 27)\n#define SET_TX_DESC_STW_RATE_DIS_NO_CLR(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 27)\n#define GET_TX_DESC_STW_RATE_DIS(txdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \\\n\t\t\t      27)\n#define SET_TX_DESC_STW_ANT_DIS(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x1, 26)\n#define SET_TX_DESC_STW_ANT_DIS_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 26)\n#define GET_TX_DESC_STW_ANT_DIS(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \\\n\t\t\t      26)\n#define SET_TX_DESC_STW_EN(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x1, 25)\n#define SET_TX_DESC_STW_EN_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 25)\n#define GET_TX_DESC_STW_EN(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \\\n\t\t\t      25)\n#define SET_TX_DESC_SMH_EN(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x1, 24)\n#define SET_TX_DESC_SMH_EN_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 24)\n#define GET_TX_DESC_SMH_EN(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_TAILPAGE_L(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0xff, 24)\n#define SET_TX_DESC_TAILPAGE_L_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0xff, 24)\n#define GET_TX_DESC_TAILPAGE_L(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xff, \\\n\t\t\t      24)\n#define SET_TX_DESC_SDIO_DMASEQ(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0xff, 16)\n#define SET_TX_DESC_SDIO_DMASEQ_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0xff, 16)\n#define GET_TX_DESC_SDIO_DMASEQ(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xff, \\\n\t\t\t      16)\n#define SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0xff, 16)\n#define SET_TX_DESC_NEXTHEADPAGE_L_NO_CLR(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0xff, 16)\n#define GET_TX_DESC_NEXTHEADPAGE_L(txdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xff, \\\n\t\t\t      16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_EN_HWSEQ(txdesc, value)                                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x1, 15)\n#define SET_TX_DESC_EN_HWSEQ_NO_CLR(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 15)\n#define GET_TX_DESC_EN_HWSEQ(txdesc)                                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \\\n\t\t\t      15)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define SET_TX_DESC_EN_HWEXSEQ(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x1, 14)\n#define SET_TX_DESC_EN_HWEXSEQ_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 14)\n#define GET_TX_DESC_EN_HWEXSEQ(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \\\n\t\t\t      14)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_EN_HWSEQ_MODE(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x3, 14)\n#define SET_TX_DESC_EN_HWSEQ_MODE_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 14)\n#define GET_TX_DESC_EN_HWSEQ_MODE(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3,  \\\n\t\t\t      14)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_DATA_RC(txdesc, value)                                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x3f, 8)\n#define SET_TX_DESC_DATA_RC_NO_CLR(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3f, 8)\n#define GET_TX_DESC_DATA_RC(txdesc)                                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3f, \\\n\t\t\t      8)\n#define SET_TX_DESC_BAR_RTY_TH(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x3, 6)\n#define SET_TX_DESC_BAR_RTY_TH_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 6)\n#define GET_TX_DESC_BAR_RTY_TH(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, 6)\n#define SET_TX_DESC_RTS_RC(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x3f, 0)\n#define SET_TX_DESC_RTS_RC_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3f, 0)\n#define GET_TX_DESC_RTS_RC(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3f, \\\n\t\t\t      0)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n/*TXDESC_WORD9*/\n\n#define SET_TX_DESC_TAILPAGE_H(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0xf, 28)\n#define SET_TX_DESC_TAILPAGE_H_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0xf, 28)\n#define GET_TX_DESC_TAILPAGE_H(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xf,  \\\n\t\t\t      28)\n#define SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0xf, 24)\n#define SET_TX_DESC_NEXTHEADPAGE_H_NO_CLR(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0xf, 24)\n#define GET_TX_DESC_NEXTHEADPAGE_H(txdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xf,  \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_FINAL_DATA_RATE_V1(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0xff, 24)\n#define SET_TX_DESC_FINAL_DATA_RATE_V1_NO_CLR(txdesc, value)                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0xff, 24)\n#define GET_TX_DESC_FINAL_DATA_RATE_V1(txdesc)                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xff, \\\n\t\t\t      24)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_SW_SEQ(txdesc, value)                                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0xfff, 12)\n#define SET_TX_DESC_SW_SEQ_NO_CLR(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0xfff, 12)\n#define GET_TX_DESC_SW_SEQ(txdesc)                                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9,       \\\n\t\t\t      0xfff, 12)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_TXBF_PATH(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0x1, 11)\n#define SET_TX_DESC_TXBF_PATH_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 11)\n#define GET_TX_DESC_TXBF_PATH(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1,  \\\n\t\t\t      11)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_PADDING_LEN(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0x7ff, 0)\n#define SET_TX_DESC_PADDING_LEN_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0x7ff, 0)\n#define GET_TX_DESC_PADDING_LEN(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9,       \\\n\t\t\t      0x7ff, 0)\n#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0xff, 0)\n#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_NO_CLR(txdesc, value)                  \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0xff, 0)\n#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xff, \\\n\t\t\t      0)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n/*WORD10*/\n\n#define SET_TX_DESC_HT_DATA_SND(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0x1, 31)\n#define SET_TX_DESC_HT_DATA_SND_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 31)\n#define GET_TX_DESC_HT_DATA_SND(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \\\n\t\t\t      31)\n#define SET_TX_DESC_SHCUT_CAM(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0x3f, 16)\n#define SET_TX_DESC_SHCUT_CAM_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0x3f, 16)\n#define GET_TX_DESC_SHCUT_CAM(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10,      \\\n\t\t\t      0x3f, 16)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_MU_DATARATE(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0xff, 8)\n#define SET_TX_DESC_MU_DATARATE_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0xff, 8)\n#define GET_TX_DESC_MU_DATARATE(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10,      \\\n\t\t\t      0xff, 8)\n#define SET_TX_DESC_MU_RC(txdesc, value)                                       \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0xf, 4)\n#define SET_TX_DESC_MU_RC_NO_CLR(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0xf, 4)\n#define GET_TX_DESC_MU_RC(txdesc)                                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0xf, \\\n\t\t\t      4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_NDPA_RATE_SEL(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0x1, 3)\n#define SET_TX_DESC_NDPA_RATE_SEL_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 3)\n#define GET_TX_DESC_NDPA_RATE_SEL(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \\\n\t\t\t      3)\n#define SET_TX_DESC_HW_NDPA_EN(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0x1, 2)\n#define SET_TX_DESC_HW_NDPA_EN_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 2)\n#define GET_TX_DESC_HW_NDPA_EN(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \\\n\t\t\t      2)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_SND_PKT_SEL(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0x3, 0)\n#define SET_TX_DESC_SND_PKT_SEL_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0x3, 0)\n#define GET_TX_DESC_SND_PKT_SEL(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x3, \\\n\t\t\t      0)\n\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_tx_desc_buffer_ap.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_TX_DESC_BUFFER_AP_H_\n#define _HALMAC_TX_DESC_BUFFER_AP_H_\n#if (HALMAC_8814B_SUPPORT)\n\n/*TXDESC_WORD0*/\n\n#define SET_TX_DESC_BUFFER_RDG_EN(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0x1, 31)\n#define SET_TX_DESC_BUFFER_RDG_EN_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 31)\n#define GET_TX_DESC_BUFFER_RDG_EN(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \\\n\t\t\t      31)\n#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0x1, 30)\n#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL_NO_CLR(txdesc, value)               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 30)\n#define GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc)                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \\\n\t\t\t      30)\n#define SET_TX_DESC_BUFFER_AGG_EN(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0x1, 29)\n#define SET_TX_DESC_BUFFER_AGG_EN_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 29)\n#define GET_TX_DESC_BUFFER_AGG_EN(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \\\n\t\t\t      29)\n#define SET_TX_DESC_BUFFER_PKT_OFFSET(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0x1f, 24)\n#define SET_TX_DESC_BUFFER_PKT_OFFSET_NO_CLR(txdesc, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1f, 24)\n#define GET_TX_DESC_BUFFER_PKT_OFFSET(txdesc)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1f, \\\n\t\t\t      24)\n#define SET_TX_DESC_BUFFER_OFFSET(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0xff, 16)\n#define SET_TX_DESC_BUFFER_OFFSET_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0xff, 16)\n#define GET_TX_DESC_BUFFER_OFFSET(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0xff, \\\n\t\t\t      16)\n#define SET_TX_DESC_BUFFER_TXPKTSIZE(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \\\n\t\t\t\t  value, 0xffff, 0)\n#define SET_TX_DESC_BUFFER_TXPKTSIZE_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword0, value, 0xffff, 0)\n#define GET_TX_DESC_BUFFER_TXPKTSIZE(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0,       \\\n\t\t\t      0xffff, 0)\n\n/*TXDESC_WORD1*/\n\n#define SET_TX_DESC_BUFFER_USERATE(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 31)\n#define SET_TX_DESC_BUFFER_USERATE_NO_CLR(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 31)\n#define GET_TX_DESC_BUFFER_USERATE(txdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      31)\n#define SET_TX_DESC_BUFFER_AMSDU(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 30)\n#define SET_TX_DESC_BUFFER_AMSDU_NO_CLR(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30)\n#define GET_TX_DESC_BUFFER_AMSDU(txdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      30)\n#define SET_TX_DESC_BUFFER_EN_HWSEQ(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 29)\n#define SET_TX_DESC_BUFFER_EN_HWSEQ_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 29)\n#define GET_TX_DESC_BUFFER_EN_HWSEQ(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      29)\n#define SET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 28)\n#define SET_TX_DESC_BUFFER_EN_HWEXSEQ_NO_CLR(txdesc, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 28)\n#define GET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      28)\n#define SET_TX_DESC_BUFFER_SW_SEQ(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0xfff, 16)\n#define SET_TX_DESC_BUFFER_SW_SEQ_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0xfff, 16)\n#define GET_TX_DESC_BUFFER_SW_SEQ(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1,       \\\n\t\t\t      0xfff, 16)\n#define SET_TX_DESC_BUFFER_DROP_ID(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x3, 14)\n#define SET_TX_DESC_BUFFER_DROP_ID_NO_CLR(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x3, 14)\n#define GET_TX_DESC_BUFFER_DROP_ID(txdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x3,  \\\n\t\t\t      14)\n#define SET_TX_DESC_BUFFER_MOREDATA(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1, 13)\n#define SET_TX_DESC_BUFFER_MOREDATA_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 13)\n#define GET_TX_DESC_BUFFER_MOREDATA(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \\\n\t\t\t      13)\n#define SET_TX_DESC_BUFFER_QSEL(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0x1f, 8)\n#define SET_TX_DESC_BUFFER_QSEL_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 8)\n#define GET_TX_DESC_BUFFER_QSEL(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \\\n\t\t\t      8)\n#define SET_TX_DESC_BUFFER_MACID(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \\\n\t\t\t\t  value, 0xff, 0)\n#define SET_TX_DESC_BUFFER_MACID_NO_CLR(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword1, value, 0xff, 0)\n#define GET_TX_DESC_BUFFER_MACID(txdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0xff, \\\n\t\t\t      0)\n\n/*TXDESC_WORD2*/\n\n#define SET_TX_DESC_BUFFER_CHK_EN(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1, 31)\n#define SET_TX_DESC_BUFFER_CHK_EN_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 31)\n#define GET_TX_DESC_BUFFER_CHK_EN(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \\\n\t\t\t      31)\n#define SET_TX_DESC_BUFFER_DISQSELSEQ(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1, 30)\n#define SET_TX_DESC_BUFFER_DISQSELSEQ_NO_CLR(txdesc, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 30)\n#define GET_TX_DESC_BUFFER_DISQSELSEQ(txdesc)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \\\n\t\t\t      30)\n#define SET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x3, 28)\n#define SET_TX_DESC_BUFFER_SND_PKT_SEL_NO_CLR(txdesc, value)                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x3, 28)\n#define GET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc)                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x3,  \\\n\t\t\t      28)\n#define SET_TX_DESC_BUFFER_DMA_PRI(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x1, 27)\n#define SET_TX_DESC_BUFFER_DMA_PRI_NO_CLR(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 27)\n#define GET_TX_DESC_BUFFER_DMA_PRI(txdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \\\n\t\t\t      27)\n#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0x7, 24)\n#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE_NO_CLR(txdesc, value)                \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0x7, 24)\n#define GET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc)                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x7,  \\\n\t\t\t      24)\n#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0xff, 16)\n#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM_NO_CLR(txdesc, value)                 \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0xff, 16)\n#define GET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc)                               \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xff, \\\n\t\t\t      16)\n#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \\\n\t\t\t\t  value, 0xffff, 0)\n#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM_NO_CLR(txdesc, value)               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword2, value, 0xffff, 0)\n#define GET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc)                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2,       \\\n\t\t\t      0xffff, 0)\n\n/*TXDESC_WORD3*/\n\n#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x7fff, 16)\n#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE_NO_CLR(txdesc, value)                  \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x7fff, 16)\n#define GET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc)                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3,       \\\n\t\t\t      0x7fff, 16)\n#define SET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x1f, 11)\n#define SET_TX_DESC_BUFFER_CHANNEL_DMA_NO_CLR(txdesc, value)                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 11)\n#define GET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc)                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \\\n\t\t\t      11)\n#define SET_TX_DESC_BUFFER_MBSSID(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0xf, 7)\n#define SET_TX_DESC_BUFFER_MBSSID_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0xf, 7)\n#define GET_TX_DESC_BUFFER_MBSSID(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0xf, 7)\n#define SET_TX_DESC_BUFFER_BK(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x1, 6)\n#define SET_TX_DESC_BUFFER_BK_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 6)\n#define GET_TX_DESC_BUFFER_BK(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 6)\n#define SET_TX_DESC_BUFFER_WHEADER_LEN(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \\\n\t\t\t\t  value, 0x1f, 0)\n#define SET_TX_DESC_BUFFER_WHEADER_LEN_NO_CLR(txdesc, value)                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 0)\n#define GET_TX_DESC_BUFFER_WHEADER_LEN(txdesc)                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \\\n\t\t\t      0)\n\n/*TXDESC_WORD4*/\n\n#define SET_TX_DESC_BUFFER_TRY_RATE(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \\\n\t\t\t\t  value, 0x1, 26)\n#define SET_TX_DESC_BUFFER_TRY_RATE_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 26)\n#define GET_TX_DESC_BUFFER_TRY_RATE(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1,  \\\n\t\t\t      26)\n#define SET_TX_DESC_BUFFER_DATA_BW(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \\\n\t\t\t\t  value, 0x3, 24)\n#define SET_TX_DESC_BUFFER_DATA_BW_NO_CLR(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword4, value, 0x3, 24)\n#define GET_TX_DESC_BUFFER_DATA_BW(txdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x3,  \\\n\t\t\t      24)\n#define SET_TX_DESC_BUFFER_DATA_SHORT(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \\\n\t\t\t\t  value, 0x1, 23)\n#define SET_TX_DESC_BUFFER_DATA_SHORT_NO_CLR(txdesc, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 23)\n#define GET_TX_DESC_BUFFER_DATA_SHORT(txdesc)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1,  \\\n\t\t\t      23)\n#define SET_TX_DESC_BUFFER_DATARATE(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \\\n\t\t\t\t  value, 0x7f, 16)\n#define SET_TX_DESC_BUFFER_DATARATE_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword4, value, 0x7f, 16)\n#define GET_TX_DESC_BUFFER_DATARATE(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x7f, \\\n\t\t\t      16)\n#define SET_TX_DESC_BUFFER_TXBF_PATH(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \\\n\t\t\t\t  value, 0x1, 11)\n#define SET_TX_DESC_BUFFER_TXBF_PATH_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 11)\n#define GET_TX_DESC_BUFFER_TXBF_PATH(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1,  \\\n\t\t\t      11)\n#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc, value)                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \\\n\t\t\t\t  value, 0x7ff, 0)\n#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET_NO_CLR(txdesc, value)           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword4, value, 0x7ff, 0)\n#define GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc)                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4,       \\\n\t\t\t      0x7ff, 0)\n\n/*TXDESC_WORD5*/\n\n#define SET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x1, 31)\n#define SET_TX_DESC_BUFFER_RTY_LMT_EN_NO_CLR(txdesc, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 31)\n#define GET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \\\n\t\t\t      31)\n#define SET_TX_DESC_BUFFER_HW_RTS_EN(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x1, 30)\n#define SET_TX_DESC_BUFFER_HW_RTS_EN_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 30)\n#define GET_TX_DESC_BUFFER_HW_RTS_EN(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \\\n\t\t\t      30)\n#define SET_TX_DESC_BUFFER_RTS_EN(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x1, 29)\n#define SET_TX_DESC_BUFFER_RTS_EN_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 29)\n#define GET_TX_DESC_BUFFER_RTS_EN(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \\\n\t\t\t      29)\n#define SET_TX_DESC_BUFFER_CTS2SELF(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x1, 28)\n#define SET_TX_DESC_BUFFER_CTS2SELF_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 28)\n#define GET_TX_DESC_BUFFER_CTS2SELF(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \\\n\t\t\t      28)\n#define SET_TX_DESC_BUFFER_TAILPAGE_H(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0xf, 24)\n#define SET_TX_DESC_BUFFER_TAILPAGE_H_NO_CLR(txdesc, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 24)\n#define GET_TX_DESC_BUFFER_TAILPAGE_H(txdesc)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf,  \\\n\t\t\t      24)\n#define SET_TX_DESC_BUFFER_TAILPAGE_L(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0xff, 16)\n#define SET_TX_DESC_BUFFER_TAILPAGE_L_NO_CLR(txdesc, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0xff, 16)\n#define GET_TX_DESC_BUFFER_TAILPAGE_L(txdesc)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xff, \\\n\t\t\t      16)\n#define SET_TX_DESC_BUFFER_NAVUSEHDR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x1, 15)\n#define SET_TX_DESC_BUFFER_NAVUSEHDR_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 15)\n#define GET_TX_DESC_BUFFER_NAVUSEHDR(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \\\n\t\t\t      15)\n#define SET_TX_DESC_BUFFER_BMC(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x1, 14)\n#define SET_TX_DESC_BUFFER_BMC_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 14)\n#define GET_TX_DESC_BUFFER_BMC(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \\\n\t\t\t      14)\n#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x3f, 8)\n#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT_NO_CLR(txdesc, value)              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3f, 8)\n#define GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc)                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3f, \\\n\t\t\t      8)\n#define SET_TX_DESC_BUFFER_HW_AES_IV(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x1, 7)\n#define SET_TX_DESC_BUFFER_HW_AES_IV_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 7)\n#define GET_TX_DESC_BUFFER_HW_AES_IV(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 7)\n#define SET_TX_DESC_BUFFER_BT_NULL(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x1, 3)\n#define SET_TX_DESC_BUFFER_BT_NULL_NO_CLR(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 3)\n#define GET_TX_DESC_BUFFER_BT_NULL(txdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 3)\n#define SET_TX_DESC_BUFFER_EN_DESC_ID(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x1, 2)\n#define SET_TX_DESC_BUFFER_EN_DESC_ID_NO_CLR(txdesc, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 2)\n#define GET_TX_DESC_BUFFER_EN_DESC_ID(txdesc)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 2)\n#define SET_TX_DESC_BUFFER_SECTYPE(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \\\n\t\t\t\t  value, 0x3, 0)\n#define SET_TX_DESC_BUFFER_SECTYPE_NO_CLR(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 0)\n#define GET_TX_DESC_BUFFER_SECTYPE(txdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, 0)\n\n/*TXDESC_WORD6*/\n\n#define SET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x7, 29)\n#define SET_TX_DESC_BUFFER_MULTIPLE_PORT_NO_CLR(txdesc, value)                 \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x7, 29)\n#define GET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc)                               \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x7,  \\\n\t\t\t      29)\n#define SET_TX_DESC_BUFFER_POLLUTED(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x1, 28)\n#define SET_TX_DESC_BUFFER_POLLUTED_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 28)\n#define GET_TX_DESC_BUFFER_POLLUTED(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1,  \\\n\t\t\t      28)\n#define SET_TX_DESC_BUFFER_NULL_1(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x1, 27)\n#define SET_TX_DESC_BUFFER_NULL_1_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 27)\n#define GET_TX_DESC_BUFFER_NULL_1(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1,  \\\n\t\t\t      27)\n#define SET_TX_DESC_BUFFER_NULL_0(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x1, 26)\n#define SET_TX_DESC_BUFFER_NULL_0_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 26)\n#define GET_TX_DESC_BUFFER_NULL_0(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1,  \\\n\t\t\t      26)\n#define SET_TX_DESC_BUFFER_TRI_FRAME(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x1, 25)\n#define SET_TX_DESC_BUFFER_TRI_FRAME_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 25)\n#define GET_TX_DESC_BUFFER_TRI_FRAME(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1,  \\\n\t\t\t      25)\n#define SET_TX_DESC_BUFFER_SPE_RPT(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x1, 24)\n#define SET_TX_DESC_BUFFER_SPE_RPT_NO_CLR(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 24)\n#define GET_TX_DESC_BUFFER_SPE_RPT(txdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1,  \\\n\t\t\t      24)\n#define SET_TX_DESC_BUFFER_FTM_EN(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x1, 23)\n#define SET_TX_DESC_BUFFER_FTM_EN_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 23)\n#define GET_TX_DESC_BUFFER_FTM_EN(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1,  \\\n\t\t\t      23)\n#define SET_TX_DESC_BUFFER_MU_DATARATE(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x7f, 16)\n#define SET_TX_DESC_BUFFER_MU_DATARATE_NO_CLR(txdesc, value)                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x7f, 16)\n#define GET_TX_DESC_BUFFER_MU_DATARATE(txdesc)                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x7f, \\\n\t\t\t      16)\n#define SET_TX_DESC_BUFFER_CCA_RTS(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 14)\n#define SET_TX_DESC_BUFFER_CCA_RTS_NO_CLR(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 14)\n#define GET_TX_DESC_BUFFER_CCA_RTS(txdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      14)\n#define SET_TX_DESC_BUFFER_NDPA(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 12)\n#define SET_TX_DESC_BUFFER_NDPA_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 12)\n#define GET_TX_DESC_BUFFER_NDPA(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \\\n\t\t\t      12)\n#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x3, 9)\n#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE_NO_CLR(txdesc, value)              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 9)\n#define GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc)                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, 9)\n#define SET_TX_DESC_BUFFER_P_AID(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \\\n\t\t\t\t  value, 0x1ff, 0)\n#define SET_TX_DESC_BUFFER_P_AID_NO_CLR(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1ff, 0)\n#define GET_TX_DESC_BUFFER_P_AID(txdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6,       \\\n\t\t\t      0x1ff, 0)\n\n/*TXDESC_WORD7*/\n\n#define SET_TX_DESC_BUFFER_SW_DEFINE(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \\\n\t\t\t\t  value, 0xfff, 16)\n#define SET_TX_DESC_BUFFER_SW_DEFINE_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword7, value, 0xfff, 16)\n#define GET_TX_DESC_BUFFER_SW_DEFINE(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7,       \\\n\t\t\t      0xfff, 16)\n#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \\\n\t\t\t\t  value, 0x1, 9)\n#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID_NO_CLR(txdesc, value)                \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1, 9)\n#define GET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc)                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1, 9)\n#define SET_TX_DESC_BUFFER_CTRL_CNT(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \\\n\t\t\t\t  value, 0xf, 5)\n#define SET_TX_DESC_BUFFER_CTRL_CNT_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword7, value, 0xf, 5)\n#define GET_TX_DESC_BUFFER_CTRL_CNT(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xf, 5)\n#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc, value)                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \\\n\t\t\t\t  value, 0x1f, 0)\n#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE_NO_CLR(txdesc, value)          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1f, 0)\n#define GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc)                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1f, \\\n\t\t\t      0)\n\n/*TXDESC_WORD8*/\n\n#define SET_TX_DESC_BUFFER_PATH_MAPA(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x3, 30)\n#define SET_TX_DESC_BUFFER_PATH_MAPA_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 30)\n#define GET_TX_DESC_BUFFER_PATH_MAPA(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3,  \\\n\t\t\t      30)\n#define SET_TX_DESC_BUFFER_PATH_MAPB(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x3, 28)\n#define SET_TX_DESC_BUFFER_PATH_MAPB_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 28)\n#define GET_TX_DESC_BUFFER_PATH_MAPB(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3,  \\\n\t\t\t      28)\n#define SET_TX_DESC_BUFFER_PATH_MAPC(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x3, 26)\n#define SET_TX_DESC_BUFFER_PATH_MAPC_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 26)\n#define GET_TX_DESC_BUFFER_PATH_MAPC(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3,  \\\n\t\t\t      26)\n#define SET_TX_DESC_BUFFER_PATH_MAPD(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x3, 24)\n#define SET_TX_DESC_BUFFER_PATH_MAPD_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 24)\n#define GET_TX_DESC_BUFFER_PATH_MAPD(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3,  \\\n\t\t\t      24)\n#define SET_TX_DESC_BUFFER_ANTSEL_A(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0xf, 20)\n#define SET_TX_DESC_BUFFER_ANTSEL_A_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 20)\n#define GET_TX_DESC_BUFFER_ANTSEL_A(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf,  \\\n\t\t\t      20)\n#define SET_TX_DESC_BUFFER_ANTSEL_B(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0xf, 16)\n#define SET_TX_DESC_BUFFER_ANTSEL_B_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 16)\n#define GET_TX_DESC_BUFFER_ANTSEL_B(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf,  \\\n\t\t\t      16)\n#define SET_TX_DESC_BUFFER_ANTSEL_C(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0xf, 12)\n#define SET_TX_DESC_BUFFER_ANTSEL_C_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 12)\n#define GET_TX_DESC_BUFFER_ANTSEL_C(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf,  \\\n\t\t\t      12)\n#define SET_TX_DESC_BUFFER_ANTSEL_D(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0xf, 8)\n#define SET_TX_DESC_BUFFER_ANTSEL_D_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 8)\n#define GET_TX_DESC_BUFFER_ANTSEL_D(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, 8)\n#define SET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0xf, 4)\n#define SET_TX_DESC_BUFFER_NTX_PATH_EN_NO_CLR(txdesc, value)                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 4)\n#define GET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc)                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, 4)\n#define SET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x1, 3)\n#define SET_TX_DESC_BUFFER_ANTLSEL_EN_NO_CLR(txdesc, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 3)\n#define GET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, 3)\n#define SET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \\\n\t\t\t\t  value, 0x7, 0)\n#define SET_TX_DESC_BUFFER_AMPDU_DENSITY_NO_CLR(txdesc, value)                 \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword8, value, 0x7, 0)\n#define GET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc)                               \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x7, 0)\n\n/*TXDESC_WORD9*/\n\n#define SET_TX_DESC_BUFFER_VCS_STBC(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0x3, 30)\n#define SET_TX_DESC_BUFFER_VCS_STBC_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0x3, 30)\n#define GET_TX_DESC_BUFFER_VCS_STBC(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x3,  \\\n\t\t\t      30)\n#define SET_TX_DESC_BUFFER_DATA_STBC(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0x3, 28)\n#define SET_TX_DESC_BUFFER_DATA_STBC_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0x3, 28)\n#define GET_TX_DESC_BUFFER_DATA_STBC(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x3,  \\\n\t\t\t      28)\n#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc, value)                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0xf, 24)\n#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE_NO_CLR(txdesc, value)           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0xf, 24)\n#define GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc)                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xf,  \\\n\t\t\t      24)\n#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc, value)                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0x1, 23)\n#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN_NO_CLR(txdesc, value)           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 23)\n#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc)                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1,  \\\n\t\t\t      23)\n#define SET_TX_DESC_BUFFER_MHR_CP(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0x1, 22)\n#define SET_TX_DESC_BUFFER_MHR_CP_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 22)\n#define GET_TX_DESC_BUFFER_MHR_CP(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1,  \\\n\t\t\t      22)\n#define SET_TX_DESC_BUFFER_SMH_EN(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0x1, 21)\n#define SET_TX_DESC_BUFFER_SMH_EN_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 21)\n#define GET_TX_DESC_BUFFER_SMH_EN(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1,  \\\n\t\t\t      21)\n#define SET_TX_DESC_BUFFER_RTSRATE(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0x1f, 16)\n#define SET_TX_DESC_BUFFER_RTSRATE_NO_CLR(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1f, 16)\n#define GET_TX_DESC_BUFFER_RTSRATE(txdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1f, \\\n\t\t\t      16)\n#define SET_TX_DESC_BUFFER_SMH_CAM(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0xff, 8)\n#define SET_TX_DESC_BUFFER_SMH_CAM_NO_CLR(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0xff, 8)\n#define GET_TX_DESC_BUFFER_SMH_CAM(txdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xff, \\\n\t\t\t      8)\n#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0x1, 7)\n#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL_NO_CLR(txdesc, value)                \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 7)\n#define GET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc)                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 7)\n#define SET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0x1, 6)\n#define SET_TX_DESC_BUFFER_ARFR_HT_EN_NO_CLR(txdesc, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 6)\n#define GET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 6)\n#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0x1, 5)\n#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN_NO_CLR(txdesc, value)                  \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 5)\n#define GET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc)                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 5)\n#define SET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0x1, 4)\n#define SET_TX_DESC_BUFFER_ARFR_CCK_EN_NO_CLR(txdesc, value)                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 4)\n#define GET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc)                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 4)\n#define SET_TX_DESC_BUFFER_RTS_SHORT(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0x1, 3)\n#define SET_TX_DESC_BUFFER_RTS_SHORT_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 3)\n#define GET_TX_DESC_BUFFER_RTS_SHORT(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 3)\n#define SET_TX_DESC_BUFFER_DISDATAFB(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0x1, 2)\n#define SET_TX_DESC_BUFFER_DISDATAFB_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 2)\n#define GET_TX_DESC_BUFFER_DISDATAFB(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 2)\n#define SET_TX_DESC_BUFFER_DISRTSFB(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0x1, 1)\n#define SET_TX_DESC_BUFFER_DISRTSFB_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 1)\n#define GET_TX_DESC_BUFFER_DISRTSFB(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 1)\n#define SET_TX_DESC_BUFFER_EXT_EDCA(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \\\n\t\t\t\t  value, 0x1, 0)\n#define SET_TX_DESC_BUFFER_EXT_EDCA_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 0)\n#define GET_TX_DESC_BUFFER_EXT_EDCA(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 0)\n\n/*TXDESC_WORD10*/\n\n#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0xff, 24)\n#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME_NO_CLR(txdesc, value)                \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0xff, 24)\n#define GET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc)                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10,      \\\n\t\t\t      0xff, 24)\n#define SET_TX_DESC_BUFFER_SPECIAL_CW(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0x1, 23)\n#define SET_TX_DESC_BUFFER_SPECIAL_CW_NO_CLR(txdesc, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 23)\n#define GET_TX_DESC_BUFFER_SPECIAL_CW(txdesc)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \\\n\t\t\t      23)\n#define SET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0x1, 22)\n#define SET_TX_DESC_BUFFER_RDG_NAV_EXT_NO_CLR(txdesc, value)                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 22)\n#define GET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc)                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \\\n\t\t\t      22)\n#define SET_TX_DESC_BUFFER_RAW(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0x1, 21)\n#define SET_TX_DESC_BUFFER_RAW_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 21)\n#define GET_TX_DESC_BUFFER_RAW(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \\\n\t\t\t      21)\n#define SET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0x1f, 16)\n#define SET_TX_DESC_BUFFER_MAX_AGG_NUM_NO_CLR(txdesc, value)                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1f, 16)\n#define GET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc)                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10,      \\\n\t\t\t      0x1f, 16)\n#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0xff, 8)\n#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE_NO_CLR(txdesc, value)               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0xff, 8)\n#define GET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc)                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10,      \\\n\t\t\t      0xff, 8)\n#define SET_TX_DESC_BUFFER_GF(txdesc, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0x1, 7)\n#define SET_TX_DESC_BUFFER_GF_NO_CLR(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 7)\n#define GET_TX_DESC_BUFFER_GF(txdesc)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \\\n\t\t\t      7)\n#define SET_TX_DESC_BUFFER_MOREFRAG(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0x1, 6)\n#define SET_TX_DESC_BUFFER_MOREFRAG_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 6)\n#define GET_TX_DESC_BUFFER_MOREFRAG(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \\\n\t\t\t      6)\n#define SET_TX_DESC_BUFFER_NOACM(txdesc, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0x1, 5)\n#define SET_TX_DESC_BUFFER_NOACM_NO_CLR(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 5)\n#define GET_TX_DESC_BUFFER_NOACM(txdesc)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \\\n\t\t\t      5)\n#define SET_TX_DESC_BUFFER_HTC(txdesc, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0x1, 4)\n#define SET_TX_DESC_BUFFER_HTC_NO_CLR(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 4)\n#define GET_TX_DESC_BUFFER_HTC(txdesc)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \\\n\t\t\t      4)\n#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc, value)                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0x1, 3)\n#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS_NO_CLR(txdesc, value)             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 3)\n#define GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc)                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \\\n\t\t\t      3)\n#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0x1, 2)\n#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN_NO_CLR(txdesc, value)               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 2)\n#define GET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc)                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \\\n\t\t\t      2)\n#define SET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \\\n\t\t\t\t  value, 0x3, 0)\n#define SET_TX_DESC_BUFFER_HW_SSN_SEL_NO_CLR(txdesc, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword10, value, 0x3, 0)\n#define GET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x3, \\\n\t\t\t      0)\n\n/*TXDESC_WORD11*/\n\n#define SET_TX_DESC_BUFFER_ADDR_CAM(txdesc, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11,  \\\n\t\t\t\t  value, 0xff, 24)\n#define SET_TX_DESC_BUFFER_ADDR_CAM_NO_CLR(txdesc, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword11, value, 0xff, 24)\n#define GET_TX_DESC_BUFFER_ADDR_CAM(txdesc)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11,      \\\n\t\t\t      0xff, 24)\n#define SET_TX_DESC_BUFFER_SND_TARGET(txdesc, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11,  \\\n\t\t\t\t  value, 0xff, 16)\n#define SET_TX_DESC_BUFFER_SND_TARGET_NO_CLR(txdesc, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword11, value, 0xff, 16)\n#define GET_TX_DESC_BUFFER_SND_TARGET(txdesc)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11,      \\\n\t\t\t      0xff, 16)\n#define SET_TX_DESC_BUFFER_DATA_LDPC(txdesc, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11,  \\\n\t\t\t\t  value, 0x1, 15)\n#define SET_TX_DESC_BUFFER_DATA_LDPC_NO_CLR(txdesc, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword11, value, 0x1, 15)\n#define GET_TX_DESC_BUFFER_DATA_LDPC(txdesc)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0x1, \\\n\t\t\t      15)\n#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc, value)                         \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11,  \\\n\t\t\t\t  value, 0x1, 14)\n#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN_NO_CLR(txdesc, value)                  \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword11, value, 0x1, 14)\n#define GET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc)                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0x1, \\\n\t\t\t      14)\n#define SET_TX_DESC_BUFFER_G_ID(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11,  \\\n\t\t\t\t  value, 0x3f, 8)\n#define SET_TX_DESC_BUFFER_G_ID_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword11, value, 0x3f, 8)\n#define GET_TX_DESC_BUFFER_G_ID(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11,      \\\n\t\t\t      0x3f, 8)\n#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc, value)                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11,  \\\n\t\t\t\t  value, 0xf, 4)\n#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC_NO_CLR(txdesc, value)           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword11, value, 0xf, 4)\n#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc)                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0xf, \\\n\t\t\t      4)\n#define SET_TX_DESC_BUFFER_DATA_SC(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11,  \\\n\t\t\t\t  value, 0xf, 0)\n#define SET_TX_DESC_BUFFER_DATA_SC_NO_CLR(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword11, value, 0xf, 0)\n#define GET_TX_DESC_BUFFER_DATA_SC(txdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0xf, \\\n\t\t\t      0)\n\n/*TXDESC_WORD12*/\n\n#define SET_TX_DESC_BUFFER_LEN1_L(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword12,  \\\n\t\t\t\t  value, 0x7f, 17)\n#define SET_TX_DESC_BUFFER_LEN1_L_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword12, value, 0x7f, 17)\n#define GET_TX_DESC_BUFFER_LEN1_L(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword12,      \\\n\t\t\t      0x7f, 17)\n#define SET_TX_DESC_BUFFER_LEN0(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword12,  \\\n\t\t\t\t  value, 0x1fff, 4)\n#define SET_TX_DESC_BUFFER_LEN0_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword12, value, 0x1fff, 4)\n#define GET_TX_DESC_BUFFER_LEN0(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword12,      \\\n\t\t\t      0x1fff, 4)\n#define SET_TX_DESC_BUFFER_PKT_NUM(txdesc, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword12,  \\\n\t\t\t\t  value, 0xf, 0)\n#define SET_TX_DESC_BUFFER_PKT_NUM_NO_CLR(txdesc, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword12, value, 0xf, 0)\n#define GET_TX_DESC_BUFFER_PKT_NUM(txdesc)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword12, 0xf, \\\n\t\t\t      0)\n\n/*TXDESC_WORD13*/\n\n#define SET_TX_DESC_BUFFER_LEN3(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword13,  \\\n\t\t\t\t  value, 0x1fff, 19)\n#define SET_TX_DESC_BUFFER_LEN3_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword13, value, 0x1fff, 19)\n#define GET_TX_DESC_BUFFER_LEN3(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword13,      \\\n\t\t\t      0x1fff, 19)\n#define SET_TX_DESC_BUFFER_LEN2(txdesc, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword13,  \\\n\t\t\t\t  value, 0x1fff, 6)\n#define SET_TX_DESC_BUFFER_LEN2_NO_CLR(txdesc, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword13, value, 0x1fff, 6)\n#define GET_TX_DESC_BUFFER_LEN2(txdesc)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword13,      \\\n\t\t\t      0x1fff, 6)\n#define SET_TX_DESC_BUFFER_LEN1_H(txdesc, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword13,  \\\n\t\t\t\t  value, 0x3f, 0)\n#define SET_TX_DESC_BUFFER_LEN1_H_NO_CLR(txdesc, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc)->dword13, value, 0x3f, 0)\n#define GET_TX_DESC_BUFFER_LEN1_H(txdesc)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword13,      \\\n\t\t\t      0x3f, 0)\n\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_tx_desc_buffer_chip.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_TX_DESC_BUFFER_CHIP_H_\n#define _HALMAC_TX_DESC_BUFFER_CHIP_H_\n#if (HALMAC_8814B_SUPPORT)\n\n/*TXDESC_WORD0*/\n\n#define SET_TX_DESC_BUFFER_RDG_EN_8814B(txdesc, value)                         \\\n\tSET_TX_DESC_BUFFER_RDG_EN(txdesc, value)\n#define GET_TX_DESC_BUFFER_RDG_EN_8814B(txdesc)                                \\\n\tGET_TX_DESC_BUFFER_RDG_EN(txdesc)\n#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL_8814B(txdesc, value)                \\\n\tSET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc, value)\n#define GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL_8814B(txdesc)                       \\\n\tGET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc)\n#define SET_TX_DESC_BUFFER_AGG_EN_8814B(txdesc, value)                         \\\n\tSET_TX_DESC_BUFFER_AGG_EN(txdesc, value)\n#define GET_TX_DESC_BUFFER_AGG_EN_8814B(txdesc)                                \\\n\tGET_TX_DESC_BUFFER_AGG_EN(txdesc)\n#define SET_TX_DESC_BUFFER_PKT_OFFSET_8814B(txdesc, value)                     \\\n\tSET_TX_DESC_BUFFER_PKT_OFFSET(txdesc, value)\n#define GET_TX_DESC_BUFFER_PKT_OFFSET_8814B(txdesc)                            \\\n\tGET_TX_DESC_BUFFER_PKT_OFFSET(txdesc)\n#define SET_TX_DESC_BUFFER_OFFSET_8814B(txdesc, value)                         \\\n\tSET_TX_DESC_BUFFER_OFFSET(txdesc, value)\n#define GET_TX_DESC_BUFFER_OFFSET_8814B(txdesc)                                \\\n\tGET_TX_DESC_BUFFER_OFFSET(txdesc)\n#define SET_TX_DESC_BUFFER_TXPKTSIZE_8814B(txdesc, value)                      \\\n\tSET_TX_DESC_BUFFER_TXPKTSIZE(txdesc, value)\n#define GET_TX_DESC_BUFFER_TXPKTSIZE_8814B(txdesc)                             \\\n\tGET_TX_DESC_BUFFER_TXPKTSIZE(txdesc)\n\n/*TXDESC_WORD1*/\n\n#define SET_TX_DESC_BUFFER_USERATE_8814B(txdesc, value)                        \\\n\tSET_TX_DESC_BUFFER_USERATE(txdesc, value)\n#define GET_TX_DESC_BUFFER_USERATE_8814B(txdesc)                               \\\n\tGET_TX_DESC_BUFFER_USERATE(txdesc)\n#define SET_TX_DESC_BUFFER_AMSDU_8814B(txdesc, value)                          \\\n\tSET_TX_DESC_BUFFER_AMSDU(txdesc, value)\n#define GET_TX_DESC_BUFFER_AMSDU_8814B(txdesc) GET_TX_DESC_BUFFER_AMSDU(txdesc)\n#define SET_TX_DESC_BUFFER_EN_HWSEQ_8814B(txdesc, value)                       \\\n\tSET_TX_DESC_BUFFER_EN_HWSEQ(txdesc, value)\n#define GET_TX_DESC_BUFFER_EN_HWSEQ_8814B(txdesc)                              \\\n\tGET_TX_DESC_BUFFER_EN_HWSEQ(txdesc)\n#define SET_TX_DESC_BUFFER_EN_HWEXSEQ_8814B(txdesc, value)                     \\\n\tSET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc, value)\n#define GET_TX_DESC_BUFFER_EN_HWEXSEQ_8814B(txdesc)                            \\\n\tGET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc)\n#define SET_TX_DESC_BUFFER_SW_SEQ_8814B(txdesc, value)                         \\\n\tSET_TX_DESC_BUFFER_SW_SEQ(txdesc, value)\n#define GET_TX_DESC_BUFFER_SW_SEQ_8814B(txdesc)                                \\\n\tGET_TX_DESC_BUFFER_SW_SEQ(txdesc)\n#define SET_TX_DESC_BUFFER_DROP_ID_8814B(txdesc, value)                        \\\n\tSET_TX_DESC_BUFFER_DROP_ID(txdesc, value)\n#define GET_TX_DESC_BUFFER_DROP_ID_8814B(txdesc)                               \\\n\tGET_TX_DESC_BUFFER_DROP_ID(txdesc)\n#define SET_TX_DESC_BUFFER_MOREDATA_8814B(txdesc, value)                       \\\n\tSET_TX_DESC_BUFFER_MOREDATA(txdesc, value)\n#define GET_TX_DESC_BUFFER_MOREDATA_8814B(txdesc)                              \\\n\tGET_TX_DESC_BUFFER_MOREDATA(txdesc)\n#define SET_TX_DESC_BUFFER_QSEL_8814B(txdesc, value)                           \\\n\tSET_TX_DESC_BUFFER_QSEL(txdesc, value)\n#define GET_TX_DESC_BUFFER_QSEL_8814B(txdesc) GET_TX_DESC_BUFFER_QSEL(txdesc)\n#define SET_TX_DESC_BUFFER_MACID_8814B(txdesc, value)                          \\\n\tSET_TX_DESC_BUFFER_MACID(txdesc, value)\n#define GET_TX_DESC_BUFFER_MACID_8814B(txdesc) GET_TX_DESC_BUFFER_MACID(txdesc)\n\n/*TXDESC_WORD2*/\n\n#define SET_TX_DESC_BUFFER_CHK_EN_8814B(txdesc, value)                         \\\n\tSET_TX_DESC_BUFFER_CHK_EN(txdesc, value)\n#define GET_TX_DESC_BUFFER_CHK_EN_8814B(txdesc)                                \\\n\tGET_TX_DESC_BUFFER_CHK_EN(txdesc)\n#define SET_TX_DESC_BUFFER_DISQSELSEQ_8814B(txdesc, value)                     \\\n\tSET_TX_DESC_BUFFER_DISQSELSEQ(txdesc, value)\n#define GET_TX_DESC_BUFFER_DISQSELSEQ_8814B(txdesc)                            \\\n\tGET_TX_DESC_BUFFER_DISQSELSEQ(txdesc)\n#define SET_TX_DESC_BUFFER_SND_PKT_SEL_8814B(txdesc, value)                    \\\n\tSET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc, value)\n#define GET_TX_DESC_BUFFER_SND_PKT_SEL_8814B(txdesc)                           \\\n\tGET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc)\n#define SET_TX_DESC_BUFFER_DMA_PRI_8814B(txdesc, value)                        \\\n\tSET_TX_DESC_BUFFER_DMA_PRI(txdesc, value)\n#define GET_TX_DESC_BUFFER_DMA_PRI_8814B(txdesc)                               \\\n\tGET_TX_DESC_BUFFER_DMA_PRI(txdesc)\n#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE_8814B(txdesc, value)                 \\\n\tSET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc, value)\n#define GET_TX_DESC_BUFFER_MAX_AMSDU_MODE_8814B(txdesc)                        \\\n\tGET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc)\n#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM_8814B(txdesc, value)                  \\\n\tSET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc, value)\n#define GET_TX_DESC_BUFFER_DMA_TXAGG_NUM_8814B(txdesc)                         \\\n\tGET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc)\n#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM_8814B(txdesc, value)                \\\n\tSET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc, value)\n#define GET_TX_DESC_BUFFER_TXDESC_CHECKSUM_8814B(txdesc)                       \\\n\tGET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc)\n\n/*TXDESC_WORD3*/\n\n#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE_8814B(txdesc, value)                   \\\n\tSET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc, value)\n#define GET_TX_DESC_BUFFER_OFFLOAD_SIZE_8814B(txdesc)                          \\\n\tGET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc)\n#define SET_TX_DESC_BUFFER_CHANNEL_DMA_8814B(txdesc, value)                    \\\n\tSET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc, value)\n#define GET_TX_DESC_BUFFER_CHANNEL_DMA_8814B(txdesc)                           \\\n\tGET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc)\n#define SET_TX_DESC_BUFFER_MBSSID_8814B(txdesc, value)                         \\\n\tSET_TX_DESC_BUFFER_MBSSID(txdesc, value)\n#define GET_TX_DESC_BUFFER_MBSSID_8814B(txdesc)                                \\\n\tGET_TX_DESC_BUFFER_MBSSID(txdesc)\n#define SET_TX_DESC_BUFFER_BK_8814B(txdesc, value)                             \\\n\tSET_TX_DESC_BUFFER_BK(txdesc, value)\n#define GET_TX_DESC_BUFFER_BK_8814B(txdesc) GET_TX_DESC_BUFFER_BK(txdesc)\n#define SET_TX_DESC_BUFFER_WHEADER_LEN_8814B(txdesc, value)                    \\\n\tSET_TX_DESC_BUFFER_WHEADER_LEN(txdesc, value)\n#define GET_TX_DESC_BUFFER_WHEADER_LEN_8814B(txdesc)                           \\\n\tGET_TX_DESC_BUFFER_WHEADER_LEN(txdesc)\n\n/*TXDESC_WORD4*/\n\n#define SET_TX_DESC_BUFFER_TRY_RATE_8814B(txdesc, value)                       \\\n\tSET_TX_DESC_BUFFER_TRY_RATE(txdesc, value)\n#define GET_TX_DESC_BUFFER_TRY_RATE_8814B(txdesc)                              \\\n\tGET_TX_DESC_BUFFER_TRY_RATE(txdesc)\n#define SET_TX_DESC_BUFFER_DATA_BW_8814B(txdesc, value)                        \\\n\tSET_TX_DESC_BUFFER_DATA_BW(txdesc, value)\n#define GET_TX_DESC_BUFFER_DATA_BW_8814B(txdesc)                               \\\n\tGET_TX_DESC_BUFFER_DATA_BW(txdesc)\n#define SET_TX_DESC_BUFFER_DATA_SHORT_8814B(txdesc, value)                     \\\n\tSET_TX_DESC_BUFFER_DATA_SHORT(txdesc, value)\n#define GET_TX_DESC_BUFFER_DATA_SHORT_8814B(txdesc)                            \\\n\tGET_TX_DESC_BUFFER_DATA_SHORT(txdesc)\n#define SET_TX_DESC_BUFFER_DATARATE_8814B(txdesc, value)                       \\\n\tSET_TX_DESC_BUFFER_DATARATE(txdesc, value)\n#define GET_TX_DESC_BUFFER_DATARATE_8814B(txdesc)                              \\\n\tGET_TX_DESC_BUFFER_DATARATE(txdesc)\n#define SET_TX_DESC_BUFFER_TXBF_PATH_8814B(txdesc, value)                      \\\n\tSET_TX_DESC_BUFFER_TXBF_PATH(txdesc, value)\n#define GET_TX_DESC_BUFFER_TXBF_PATH_8814B(txdesc)                             \\\n\tGET_TX_DESC_BUFFER_TXBF_PATH(txdesc)\n#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET_8814B(txdesc, value)            \\\n\tSET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc, value)\n#define GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET_8814B(txdesc)                   \\\n\tGET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc)\n\n/*TXDESC_WORD5*/\n\n#define SET_TX_DESC_BUFFER_RTY_LMT_EN_8814B(txdesc, value)                     \\\n\tSET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc, value)\n#define GET_TX_DESC_BUFFER_RTY_LMT_EN_8814B(txdesc)                            \\\n\tGET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc)\n#define SET_TX_DESC_BUFFER_HW_RTS_EN_8814B(txdesc, value)                      \\\n\tSET_TX_DESC_BUFFER_HW_RTS_EN(txdesc, value)\n#define GET_TX_DESC_BUFFER_HW_RTS_EN_8814B(txdesc)                             \\\n\tGET_TX_DESC_BUFFER_HW_RTS_EN(txdesc)\n#define SET_TX_DESC_BUFFER_RTS_EN_8814B(txdesc, value)                         \\\n\tSET_TX_DESC_BUFFER_RTS_EN(txdesc, value)\n#define GET_TX_DESC_BUFFER_RTS_EN_8814B(txdesc)                                \\\n\tGET_TX_DESC_BUFFER_RTS_EN(txdesc)\n#define SET_TX_DESC_BUFFER_CTS2SELF_8814B(txdesc, value)                       \\\n\tSET_TX_DESC_BUFFER_CTS2SELF(txdesc, value)\n#define GET_TX_DESC_BUFFER_CTS2SELF_8814B(txdesc)                              \\\n\tGET_TX_DESC_BUFFER_CTS2SELF(txdesc)\n#define SET_TX_DESC_BUFFER_TAILPAGE_H_8814B(txdesc, value)                     \\\n\tSET_TX_DESC_BUFFER_TAILPAGE_H(txdesc, value)\n#define GET_TX_DESC_BUFFER_TAILPAGE_H_8814B(txdesc)                            \\\n\tGET_TX_DESC_BUFFER_TAILPAGE_H(txdesc)\n#define SET_TX_DESC_BUFFER_TAILPAGE_L_8814B(txdesc, value)                     \\\n\tSET_TX_DESC_BUFFER_TAILPAGE_L(txdesc, value)\n#define GET_TX_DESC_BUFFER_TAILPAGE_L_8814B(txdesc)                            \\\n\tGET_TX_DESC_BUFFER_TAILPAGE_L(txdesc)\n#define SET_TX_DESC_BUFFER_NAVUSEHDR_8814B(txdesc, value)                      \\\n\tSET_TX_DESC_BUFFER_NAVUSEHDR(txdesc, value)\n#define GET_TX_DESC_BUFFER_NAVUSEHDR_8814B(txdesc)                             \\\n\tGET_TX_DESC_BUFFER_NAVUSEHDR(txdesc)\n#define SET_TX_DESC_BUFFER_BMC_8814B(txdesc, value)                            \\\n\tSET_TX_DESC_BUFFER_BMC(txdesc, value)\n#define GET_TX_DESC_BUFFER_BMC_8814B(txdesc) GET_TX_DESC_BUFFER_BMC(txdesc)\n#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT_8814B(txdesc, value)               \\\n\tSET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc, value)\n#define GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT_8814B(txdesc)                      \\\n\tGET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc)\n#define SET_TX_DESC_BUFFER_HW_AES_IV_8814B(txdesc, value)                      \\\n\tSET_TX_DESC_BUFFER_HW_AES_IV(txdesc, value)\n#define GET_TX_DESC_BUFFER_HW_AES_IV_8814B(txdesc)                             \\\n\tGET_TX_DESC_BUFFER_HW_AES_IV(txdesc)\n#define SET_TX_DESC_BUFFER_BT_NULL_8814B(txdesc, value)                        \\\n\tSET_TX_DESC_BUFFER_BT_NULL(txdesc, value)\n#define GET_TX_DESC_BUFFER_BT_NULL_8814B(txdesc)                               \\\n\tGET_TX_DESC_BUFFER_BT_NULL(txdesc)\n#define SET_TX_DESC_BUFFER_EN_DESC_ID_8814B(txdesc, value)                     \\\n\tSET_TX_DESC_BUFFER_EN_DESC_ID(txdesc, value)\n#define GET_TX_DESC_BUFFER_EN_DESC_ID_8814B(txdesc)                            \\\n\tGET_TX_DESC_BUFFER_EN_DESC_ID(txdesc)\n#define SET_TX_DESC_BUFFER_SECTYPE_8814B(txdesc, value)                        \\\n\tSET_TX_DESC_BUFFER_SECTYPE(txdesc, value)\n#define GET_TX_DESC_BUFFER_SECTYPE_8814B(txdesc)                               \\\n\tGET_TX_DESC_BUFFER_SECTYPE(txdesc)\n\n/*TXDESC_WORD6*/\n\n#define SET_TX_DESC_BUFFER_MULTIPLE_PORT_8814B(txdesc, value)                  \\\n\tSET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc, value)\n#define GET_TX_DESC_BUFFER_MULTIPLE_PORT_8814B(txdesc)                         \\\n\tGET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc)\n#define SET_TX_DESC_BUFFER_POLLUTED_8814B(txdesc, value)                       \\\n\tSET_TX_DESC_BUFFER_POLLUTED(txdesc, value)\n#define GET_TX_DESC_BUFFER_POLLUTED_8814B(txdesc)                              \\\n\tGET_TX_DESC_BUFFER_POLLUTED(txdesc)\n#define SET_TX_DESC_BUFFER_NULL_1_8814B(txdesc, value)                         \\\n\tSET_TX_DESC_BUFFER_NULL_1(txdesc, value)\n#define GET_TX_DESC_BUFFER_NULL_1_8814B(txdesc)                                \\\n\tGET_TX_DESC_BUFFER_NULL_1(txdesc)\n#define SET_TX_DESC_BUFFER_NULL_0_8814B(txdesc, value)                         \\\n\tSET_TX_DESC_BUFFER_NULL_0(txdesc, value)\n#define GET_TX_DESC_BUFFER_NULL_0_8814B(txdesc)                                \\\n\tGET_TX_DESC_BUFFER_NULL_0(txdesc)\n#define SET_TX_DESC_BUFFER_TRI_FRAME_8814B(txdesc, value)                      \\\n\tSET_TX_DESC_BUFFER_TRI_FRAME(txdesc, value)\n#define GET_TX_DESC_BUFFER_TRI_FRAME_8814B(txdesc)                             \\\n\tGET_TX_DESC_BUFFER_TRI_FRAME(txdesc)\n#define SET_TX_DESC_BUFFER_SPE_RPT_8814B(txdesc, value)                        \\\n\tSET_TX_DESC_BUFFER_SPE_RPT(txdesc, value)\n#define GET_TX_DESC_BUFFER_SPE_RPT_8814B(txdesc)                               \\\n\tGET_TX_DESC_BUFFER_SPE_RPT(txdesc)\n#define SET_TX_DESC_BUFFER_FTM_EN_8814B(txdesc, value)                         \\\n\tSET_TX_DESC_BUFFER_FTM_EN(txdesc, value)\n#define GET_TX_DESC_BUFFER_FTM_EN_8814B(txdesc)                                \\\n\tGET_TX_DESC_BUFFER_FTM_EN(txdesc)\n#define SET_TX_DESC_BUFFER_MU_DATARATE_8814B(txdesc, value)                    \\\n\tSET_TX_DESC_BUFFER_MU_DATARATE(txdesc, value)\n#define GET_TX_DESC_BUFFER_MU_DATARATE_8814B(txdesc)                           \\\n\tGET_TX_DESC_BUFFER_MU_DATARATE(txdesc)\n#define SET_TX_DESC_BUFFER_CCA_RTS_8814B(txdesc, value)                        \\\n\tSET_TX_DESC_BUFFER_CCA_RTS(txdesc, value)\n#define GET_TX_DESC_BUFFER_CCA_RTS_8814B(txdesc)                               \\\n\tGET_TX_DESC_BUFFER_CCA_RTS(txdesc)\n#define SET_TX_DESC_BUFFER_NDPA_8814B(txdesc, value)                           \\\n\tSET_TX_DESC_BUFFER_NDPA(txdesc, value)\n#define GET_TX_DESC_BUFFER_NDPA_8814B(txdesc) GET_TX_DESC_BUFFER_NDPA(txdesc)\n#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE_8814B(txdesc, value)               \\\n\tSET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc, value)\n#define GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE_8814B(txdesc)                      \\\n\tGET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc)\n#define SET_TX_DESC_BUFFER_P_AID_8814B(txdesc, value)                          \\\n\tSET_TX_DESC_BUFFER_P_AID(txdesc, value)\n#define GET_TX_DESC_BUFFER_P_AID_8814B(txdesc) GET_TX_DESC_BUFFER_P_AID(txdesc)\n\n/*TXDESC_WORD7*/\n\n#define SET_TX_DESC_BUFFER_SW_DEFINE_8814B(txdesc, value)                      \\\n\tSET_TX_DESC_BUFFER_SW_DEFINE(txdesc, value)\n#define GET_TX_DESC_BUFFER_SW_DEFINE_8814B(txdesc)                             \\\n\tGET_TX_DESC_BUFFER_SW_DEFINE(txdesc)\n#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID_8814B(txdesc, value)                 \\\n\tSET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc, value)\n#define GET_TX_DESC_BUFFER_CTRL_CNT_VALID_8814B(txdesc)                        \\\n\tGET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc)\n#define SET_TX_DESC_BUFFER_CTRL_CNT_8814B(txdesc, value)                       \\\n\tSET_TX_DESC_BUFFER_CTRL_CNT(txdesc, value)\n#define GET_TX_DESC_BUFFER_CTRL_CNT_8814B(txdesc)                              \\\n\tGET_TX_DESC_BUFFER_CTRL_CNT(txdesc)\n#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE_8814B(txdesc, value)           \\\n\tSET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE_8814B(txdesc)                  \\\n\tGET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc)\n\n/*TXDESC_WORD8*/\n\n#define SET_TX_DESC_BUFFER_PATH_MAPA_8814B(txdesc, value)                      \\\n\tSET_TX_DESC_BUFFER_PATH_MAPA(txdesc, value)\n#define GET_TX_DESC_BUFFER_PATH_MAPA_8814B(txdesc)                             \\\n\tGET_TX_DESC_BUFFER_PATH_MAPA(txdesc)\n#define SET_TX_DESC_BUFFER_PATH_MAPB_8814B(txdesc, value)                      \\\n\tSET_TX_DESC_BUFFER_PATH_MAPB(txdesc, value)\n#define GET_TX_DESC_BUFFER_PATH_MAPB_8814B(txdesc)                             \\\n\tGET_TX_DESC_BUFFER_PATH_MAPB(txdesc)\n#define SET_TX_DESC_BUFFER_PATH_MAPC_8814B(txdesc, value)                      \\\n\tSET_TX_DESC_BUFFER_PATH_MAPC(txdesc, value)\n#define GET_TX_DESC_BUFFER_PATH_MAPC_8814B(txdesc)                             \\\n\tGET_TX_DESC_BUFFER_PATH_MAPC(txdesc)\n#define SET_TX_DESC_BUFFER_PATH_MAPD_8814B(txdesc, value)                      \\\n\tSET_TX_DESC_BUFFER_PATH_MAPD(txdesc, value)\n#define GET_TX_DESC_BUFFER_PATH_MAPD_8814B(txdesc)                             \\\n\tGET_TX_DESC_BUFFER_PATH_MAPD(txdesc)\n#define SET_TX_DESC_BUFFER_ANTSEL_A_8814B(txdesc, value)                       \\\n\tSET_TX_DESC_BUFFER_ANTSEL_A(txdesc, value)\n#define GET_TX_DESC_BUFFER_ANTSEL_A_8814B(txdesc)                              \\\n\tGET_TX_DESC_BUFFER_ANTSEL_A(txdesc)\n#define SET_TX_DESC_BUFFER_ANTSEL_B_8814B(txdesc, value)                       \\\n\tSET_TX_DESC_BUFFER_ANTSEL_B(txdesc, value)\n#define GET_TX_DESC_BUFFER_ANTSEL_B_8814B(txdesc)                              \\\n\tGET_TX_DESC_BUFFER_ANTSEL_B(txdesc)\n#define SET_TX_DESC_BUFFER_ANTSEL_C_8814B(txdesc, value)                       \\\n\tSET_TX_DESC_BUFFER_ANTSEL_C(txdesc, value)\n#define GET_TX_DESC_BUFFER_ANTSEL_C_8814B(txdesc)                              \\\n\tGET_TX_DESC_BUFFER_ANTSEL_C(txdesc)\n#define SET_TX_DESC_BUFFER_ANTSEL_D_8814B(txdesc, value)                       \\\n\tSET_TX_DESC_BUFFER_ANTSEL_D(txdesc, value)\n#define GET_TX_DESC_BUFFER_ANTSEL_D_8814B(txdesc)                              \\\n\tGET_TX_DESC_BUFFER_ANTSEL_D(txdesc)\n#define SET_TX_DESC_BUFFER_NTX_PATH_EN_8814B(txdesc, value)                    \\\n\tSET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc, value)\n#define GET_TX_DESC_BUFFER_NTX_PATH_EN_8814B(txdesc)                           \\\n\tGET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc)\n#define SET_TX_DESC_BUFFER_ANTLSEL_EN_8814B(txdesc, value)                     \\\n\tSET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc, value)\n#define GET_TX_DESC_BUFFER_ANTLSEL_EN_8814B(txdesc)                            \\\n\tGET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc)\n#define SET_TX_DESC_BUFFER_AMPDU_DENSITY_8814B(txdesc, value)                  \\\n\tSET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc, value)\n#define GET_TX_DESC_BUFFER_AMPDU_DENSITY_8814B(txdesc)                         \\\n\tGET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc)\n\n/*TXDESC_WORD9*/\n\n#define SET_TX_DESC_BUFFER_VCS_STBC_8814B(txdesc, value)                       \\\n\tSET_TX_DESC_BUFFER_VCS_STBC(txdesc, value)\n#define GET_TX_DESC_BUFFER_VCS_STBC_8814B(txdesc)                              \\\n\tGET_TX_DESC_BUFFER_VCS_STBC(txdesc)\n#define SET_TX_DESC_BUFFER_DATA_STBC_8814B(txdesc, value)                      \\\n\tSET_TX_DESC_BUFFER_DATA_STBC(txdesc, value)\n#define GET_TX_DESC_BUFFER_DATA_STBC_8814B(txdesc)                             \\\n\tGET_TX_DESC_BUFFER_DATA_STBC(txdesc)\n#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE_8814B(txdesc, value)            \\\n\tSET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE_8814B(txdesc)                   \\\n\tGET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc)\n#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN_8814B(txdesc, value)            \\\n\tSET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc, value)\n#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN_8814B(txdesc)                   \\\n\tGET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc)\n#define SET_TX_DESC_BUFFER_MHR_CP_8814B(txdesc, value)                         \\\n\tSET_TX_DESC_BUFFER_MHR_CP(txdesc, value)\n#define GET_TX_DESC_BUFFER_MHR_CP_8814B(txdesc)                                \\\n\tGET_TX_DESC_BUFFER_MHR_CP(txdesc)\n#define SET_TX_DESC_BUFFER_SMH_EN_8814B(txdesc, value)                         \\\n\tSET_TX_DESC_BUFFER_SMH_EN(txdesc, value)\n#define GET_TX_DESC_BUFFER_SMH_EN_8814B(txdesc)                                \\\n\tGET_TX_DESC_BUFFER_SMH_EN(txdesc)\n#define SET_TX_DESC_BUFFER_RTSRATE_8814B(txdesc, value)                        \\\n\tSET_TX_DESC_BUFFER_RTSRATE(txdesc, value)\n#define GET_TX_DESC_BUFFER_RTSRATE_8814B(txdesc)                               \\\n\tGET_TX_DESC_BUFFER_RTSRATE(txdesc)\n#define SET_TX_DESC_BUFFER_SMH_CAM_8814B(txdesc, value)                        \\\n\tSET_TX_DESC_BUFFER_SMH_CAM(txdesc, value)\n#define GET_TX_DESC_BUFFER_SMH_CAM_8814B(txdesc)                               \\\n\tGET_TX_DESC_BUFFER_SMH_CAM(txdesc)\n#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL_8814B(txdesc, value)                 \\\n\tSET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc, value)\n#define GET_TX_DESC_BUFFER_ARFR_TABLE_SEL_8814B(txdesc)                        \\\n\tGET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc)\n#define SET_TX_DESC_BUFFER_ARFR_HT_EN_8814B(txdesc, value)                     \\\n\tSET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc, value)\n#define GET_TX_DESC_BUFFER_ARFR_HT_EN_8814B(txdesc)                            \\\n\tGET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc)\n#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN_8814B(txdesc, value)                   \\\n\tSET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc, value)\n#define GET_TX_DESC_BUFFER_ARFR_OFDM_EN_8814B(txdesc)                          \\\n\tGET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc)\n#define SET_TX_DESC_BUFFER_ARFR_CCK_EN_8814B(txdesc, value)                    \\\n\tSET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc, value)\n#define GET_TX_DESC_BUFFER_ARFR_CCK_EN_8814B(txdesc)                           \\\n\tGET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc)\n#define SET_TX_DESC_BUFFER_RTS_SHORT_8814B(txdesc, value)                      \\\n\tSET_TX_DESC_BUFFER_RTS_SHORT(txdesc, value)\n#define GET_TX_DESC_BUFFER_RTS_SHORT_8814B(txdesc)                             \\\n\tGET_TX_DESC_BUFFER_RTS_SHORT(txdesc)\n#define SET_TX_DESC_BUFFER_DISDATAFB_8814B(txdesc, value)                      \\\n\tSET_TX_DESC_BUFFER_DISDATAFB(txdesc, value)\n#define GET_TX_DESC_BUFFER_DISDATAFB_8814B(txdesc)                             \\\n\tGET_TX_DESC_BUFFER_DISDATAFB(txdesc)\n#define SET_TX_DESC_BUFFER_DISRTSFB_8814B(txdesc, value)                       \\\n\tSET_TX_DESC_BUFFER_DISRTSFB(txdesc, value)\n#define GET_TX_DESC_BUFFER_DISRTSFB_8814B(txdesc)                              \\\n\tGET_TX_DESC_BUFFER_DISRTSFB(txdesc)\n#define SET_TX_DESC_BUFFER_EXT_EDCA_8814B(txdesc, value)                       \\\n\tSET_TX_DESC_BUFFER_EXT_EDCA(txdesc, value)\n#define GET_TX_DESC_BUFFER_EXT_EDCA_8814B(txdesc)                              \\\n\tGET_TX_DESC_BUFFER_EXT_EDCA(txdesc)\n\n/*TXDESC_WORD10*/\n\n#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME_8814B(txdesc, value)                 \\\n\tSET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc, value)\n#define GET_TX_DESC_BUFFER_AMPDU_MAX_TIME_8814B(txdesc)                        \\\n\tGET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc)\n#define SET_TX_DESC_BUFFER_SPECIAL_CW_8814B(txdesc, value)                     \\\n\tSET_TX_DESC_BUFFER_SPECIAL_CW(txdesc, value)\n#define GET_TX_DESC_BUFFER_SPECIAL_CW_8814B(txdesc)                            \\\n\tGET_TX_DESC_BUFFER_SPECIAL_CW(txdesc)\n#define SET_TX_DESC_BUFFER_RDG_NAV_EXT_8814B(txdesc, value)                    \\\n\tSET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc, value)\n#define GET_TX_DESC_BUFFER_RDG_NAV_EXT_8814B(txdesc)                           \\\n\tGET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc)\n#define SET_TX_DESC_BUFFER_RAW_8814B(txdesc, value)                            \\\n\tSET_TX_DESC_BUFFER_RAW(txdesc, value)\n#define GET_TX_DESC_BUFFER_RAW_8814B(txdesc) GET_TX_DESC_BUFFER_RAW(txdesc)\n#define SET_TX_DESC_BUFFER_MAX_AGG_NUM_8814B(txdesc, value)                    \\\n\tSET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc, value)\n#define GET_TX_DESC_BUFFER_MAX_AGG_NUM_8814B(txdesc)                           \\\n\tGET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc)\n#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE_8814B(txdesc, value)                \\\n\tSET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc, value)\n#define GET_TX_DESC_BUFFER_FINAL_DATA_RATE_8814B(txdesc)                       \\\n\tGET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc)\n#define SET_TX_DESC_BUFFER_GF_8814B(txdesc, value)                             \\\n\tSET_TX_DESC_BUFFER_GF(txdesc, value)\n#define GET_TX_DESC_BUFFER_GF_8814B(txdesc) GET_TX_DESC_BUFFER_GF(txdesc)\n#define SET_TX_DESC_BUFFER_MOREFRAG_8814B(txdesc, value)                       \\\n\tSET_TX_DESC_BUFFER_MOREFRAG(txdesc, value)\n#define GET_TX_DESC_BUFFER_MOREFRAG_8814B(txdesc)                              \\\n\tGET_TX_DESC_BUFFER_MOREFRAG(txdesc)\n#define SET_TX_DESC_BUFFER_NOACM_8814B(txdesc, value)                          \\\n\tSET_TX_DESC_BUFFER_NOACM(txdesc, value)\n#define GET_TX_DESC_BUFFER_NOACM_8814B(txdesc) GET_TX_DESC_BUFFER_NOACM(txdesc)\n#define SET_TX_DESC_BUFFER_HTC_8814B(txdesc, value)                            \\\n\tSET_TX_DESC_BUFFER_HTC(txdesc, value)\n#define GET_TX_DESC_BUFFER_HTC_8814B(txdesc) GET_TX_DESC_BUFFER_HTC(txdesc)\n#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS_8814B(txdesc, value)              \\\n\tSET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc, value)\n#define GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS_8814B(txdesc)                     \\\n\tGET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc)\n#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN_8814B(txdesc, value)                \\\n\tSET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc, value)\n#define GET_TX_DESC_BUFFER_USE_MAX_TIME_EN_8814B(txdesc)                       \\\n\tGET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc)\n#define SET_TX_DESC_BUFFER_HW_SSN_SEL_8814B(txdesc, value)                     \\\n\tSET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc, value)\n#define GET_TX_DESC_BUFFER_HW_SSN_SEL_8814B(txdesc)                            \\\n\tGET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc)\n\n/*TXDESC_WORD11*/\n\n#define SET_TX_DESC_BUFFER_ADDR_CAM_8814B(txdesc, value)                       \\\n\tSET_TX_DESC_BUFFER_ADDR_CAM(txdesc, value)\n#define GET_TX_DESC_BUFFER_ADDR_CAM_8814B(txdesc)                              \\\n\tGET_TX_DESC_BUFFER_ADDR_CAM(txdesc)\n#define SET_TX_DESC_BUFFER_SND_TARGET_8814B(txdesc, value)                     \\\n\tSET_TX_DESC_BUFFER_SND_TARGET(txdesc, value)\n#define GET_TX_DESC_BUFFER_SND_TARGET_8814B(txdesc)                            \\\n\tGET_TX_DESC_BUFFER_SND_TARGET(txdesc)\n#define SET_TX_DESC_BUFFER_DATA_LDPC_8814B(txdesc, value)                      \\\n\tSET_TX_DESC_BUFFER_DATA_LDPC(txdesc, value)\n#define GET_TX_DESC_BUFFER_DATA_LDPC_8814B(txdesc)                             \\\n\tGET_TX_DESC_BUFFER_DATA_LDPC(txdesc)\n#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN_8814B(txdesc, value)                   \\\n\tSET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc, value)\n#define GET_TX_DESC_BUFFER_LSIG_TXOP_EN_8814B(txdesc)                          \\\n\tGET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc)\n#define SET_TX_DESC_BUFFER_G_ID_8814B(txdesc, value)                           \\\n\tSET_TX_DESC_BUFFER_G_ID(txdesc, value)\n#define GET_TX_DESC_BUFFER_G_ID_8814B(txdesc) GET_TX_DESC_BUFFER_G_ID(txdesc)\n#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC_8814B(txdesc, value)            \\\n\tSET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc, value)\n#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC_8814B(txdesc)                   \\\n\tGET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc)\n#define SET_TX_DESC_BUFFER_DATA_SC_8814B(txdesc, value)                        \\\n\tSET_TX_DESC_BUFFER_DATA_SC(txdesc, value)\n#define GET_TX_DESC_BUFFER_DATA_SC_8814B(txdesc)                               \\\n\tGET_TX_DESC_BUFFER_DATA_SC(txdesc)\n\n/*TXDESC_WORD12*/\n\n#define SET_TX_DESC_BUFFER_LEN1_L_8814B(txdesc, value)                         \\\n\tSET_TX_DESC_BUFFER_LEN1_L(txdesc, value)\n#define GET_TX_DESC_BUFFER_LEN1_L_8814B(txdesc)                                \\\n\tGET_TX_DESC_BUFFER_LEN1_L(txdesc)\n#define SET_TX_DESC_BUFFER_LEN0_8814B(txdesc, value)                           \\\n\tSET_TX_DESC_BUFFER_LEN0(txdesc, value)\n#define GET_TX_DESC_BUFFER_LEN0_8814B(txdesc) GET_TX_DESC_BUFFER_LEN0(txdesc)\n#define SET_TX_DESC_BUFFER_PKT_NUM_8814B(txdesc, value)                        \\\n\tSET_TX_DESC_BUFFER_PKT_NUM(txdesc, value)\n#define GET_TX_DESC_BUFFER_PKT_NUM_8814B(txdesc)                               \\\n\tGET_TX_DESC_BUFFER_PKT_NUM(txdesc)\n\n/*TXDESC_WORD13*/\n\n#define SET_TX_DESC_BUFFER_LEN3_8814B(txdesc, value)                           \\\n\tSET_TX_DESC_BUFFER_LEN3(txdesc, value)\n#define GET_TX_DESC_BUFFER_LEN3_8814B(txdesc) GET_TX_DESC_BUFFER_LEN3(txdesc)\n#define SET_TX_DESC_BUFFER_LEN2_8814B(txdesc, value)                           \\\n\tSET_TX_DESC_BUFFER_LEN2(txdesc, value)\n#define GET_TX_DESC_BUFFER_LEN2_8814B(txdesc) GET_TX_DESC_BUFFER_LEN2(txdesc)\n#define SET_TX_DESC_BUFFER_LEN1_H_8814B(txdesc, value)                         \\\n\tSET_TX_DESC_BUFFER_LEN1_H(txdesc, value)\n#define GET_TX_DESC_BUFFER_LEN1_H_8814B(txdesc)                                \\\n\tGET_TX_DESC_BUFFER_LEN1_H(txdesc)\n\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_tx_desc_buffer_nic.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_TX_DESC_BUFFER_NIC_H_\n#define _HALMAC_TX_DESC_BUFFER_NIC_H_\n#if (HALMAC_8814B_SUPPORT)\n\n/*TXDESC_WORD0*/\n\n#define SET_TX_DESC_BUFFER_RDG_EN(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value)\n#define GET_TX_DESC_BUFFER_RDG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1)\n#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value)\n#define GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc)                             \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1)\n#define SET_TX_DESC_BUFFER_AGG_EN(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value)\n#define GET_TX_DESC_BUFFER_AGG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1)\n#define SET_TX_DESC_BUFFER_PKT_OFFSET(txdesc, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 5, value)\n#define GET_TX_DESC_BUFFER_PKT_OFFSET(txdesc)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x00, 24, 5)\n#define SET_TX_DESC_BUFFER_OFFSET(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 16, 8, value)\n#define GET_TX_DESC_BUFFER_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 16, 8)\n#define SET_TX_DESC_BUFFER_TXPKTSIZE(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 0, 16, value)\n#define GET_TX_DESC_BUFFER_TXPKTSIZE(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x00, 0, 16)\n\n/*TXDESC_WORD1*/\n\n#define SET_TX_DESC_BUFFER_USERATE(txdesc, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 31, 1, value)\n#define GET_TX_DESC_BUFFER_USERATE(txdesc)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x04, 31, 1)\n#define SET_TX_DESC_BUFFER_AMSDU(txdesc, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value)\n#define GET_TX_DESC_BUFFER_AMSDU(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1)\n#define SET_TX_DESC_BUFFER_EN_HWSEQ(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value)\n#define GET_TX_DESC_BUFFER_EN_HWSEQ(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1)\n#define SET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 28, 1, value)\n#define GET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x04, 28, 1)\n#define SET_TX_DESC_BUFFER_SW_SEQ(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 12, value)\n#define GET_TX_DESC_BUFFER_SW_SEQ(txdesc)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x04, 16, 12)\n#define SET_TX_DESC_BUFFER_DROP_ID(txdesc, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 14, 2, value)\n#define GET_TX_DESC_BUFFER_DROP_ID(txdesc)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x04, 14, 2)\n#define SET_TX_DESC_BUFFER_MOREDATA(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value)\n#define GET_TX_DESC_BUFFER_MOREDATA(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1)\n#define SET_TX_DESC_BUFFER_QSEL(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 8, 5, value)\n#define GET_TX_DESC_BUFFER_QSEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 8, 5)\n#define SET_TX_DESC_BUFFER_MACID(txdesc, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 8, value)\n#define GET_TX_DESC_BUFFER_MACID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 8)\n\n/*TXDESC_WORD2*/\n\n#define SET_TX_DESC_BUFFER_CHK_EN(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value)\n#define GET_TX_DESC_BUFFER_CHK_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1)\n#define SET_TX_DESC_BUFFER_DISQSELSEQ(txdesc, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 30, 1, value)\n#define GET_TX_DESC_BUFFER_DISQSELSEQ(txdesc)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x08, 30, 1)\n#define SET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 28, 2, value)\n#define GET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc)                                 \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x08, 28, 2)\n#define SET_TX_DESC_BUFFER_DMA_PRI(txdesc, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 27, 1, value)\n#define GET_TX_DESC_BUFFER_DMA_PRI(txdesc)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x08, 27, 1)\n#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 3, value)\n#define GET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc)                              \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x08, 24, 3)\n#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 8, value)\n#define GET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc)                               \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x08, 16, 8)\n#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 16, value)\n#define GET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc)                             \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x08, 0, 16)\n\n/*TXDESC_WORD3*/\n\n#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 15, value)\n#define GET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc)                                \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 15)\n#define SET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 5, value)\n#define GET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc)                                 \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 5)\n#define SET_TX_DESC_BUFFER_MBSSID(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 7, 4, value)\n#define GET_TX_DESC_BUFFER_MBSSID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 7, 4)\n#define SET_TX_DESC_BUFFER_BK(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 1, value)\n#define GET_TX_DESC_BUFFER_BK(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 1)\n#define SET_TX_DESC_BUFFER_WHEADER_LEN(txdesc, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value)\n#define GET_TX_DESC_BUFFER_WHEADER_LEN(txdesc)                                 \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5)\n\n/*TXDESC_WORD4*/\n\n#define SET_TX_DESC_BUFFER_TRY_RATE(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x10, 26, 1, value)\n#define GET_TX_DESC_BUFFER_TRY_RATE(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x10, 26, 1)\n#define SET_TX_DESC_BUFFER_DATA_BW(txdesc, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x10, 24, 2, value)\n#define GET_TX_DESC_BUFFER_DATA_BW(txdesc)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x10, 24, 2)\n#define SET_TX_DESC_BUFFER_DATA_SHORT(txdesc, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x10, 23, 1, value)\n#define GET_TX_DESC_BUFFER_DATA_SHORT(txdesc)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x10, 23, 1)\n#define SET_TX_DESC_BUFFER_DATARATE(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x10, 16, 7, value)\n#define GET_TX_DESC_BUFFER_DATARATE(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x10, 16, 7)\n#define SET_TX_DESC_BUFFER_TXBF_PATH(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x10, 11, 1, value)\n#define GET_TX_DESC_BUFFER_TXBF_PATH(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x10, 11, 1)\n#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc, value)                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x10, 0, 11, value)\n#define GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc)                         \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x10, 0, 11)\n\n/*TXDESC_WORD5*/\n\n#define SET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 31, 1, value)\n#define GET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x14, 31, 1)\n#define SET_TX_DESC_BUFFER_HW_RTS_EN(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 30, 1, value)\n#define GET_TX_DESC_BUFFER_HW_RTS_EN(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x14, 30, 1)\n#define SET_TX_DESC_BUFFER_RTS_EN(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 29, 1, value)\n#define GET_TX_DESC_BUFFER_RTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 29, 1)\n#define SET_TX_DESC_BUFFER_CTS2SELF(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 1, value)\n#define GET_TX_DESC_BUFFER_CTS2SELF(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x14, 28, 1)\n#define SET_TX_DESC_BUFFER_TAILPAGE_H(txdesc, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 4, value)\n#define GET_TX_DESC_BUFFER_TAILPAGE_H(txdesc)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x14, 24, 4)\n#define SET_TX_DESC_BUFFER_TAILPAGE_L(txdesc, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 16, 8, value)\n#define GET_TX_DESC_BUFFER_TAILPAGE_L(txdesc)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x14, 16, 8)\n#define SET_TX_DESC_BUFFER_NAVUSEHDR(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 15, 1, value)\n#define GET_TX_DESC_BUFFER_NAVUSEHDR(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x14, 15, 1)\n#define SET_TX_DESC_BUFFER_BMC(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 14, 1, value)\n#define GET_TX_DESC_BUFFER_BMC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 14, 1)\n#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc, value)                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 8, 6, value)\n#define GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc)                            \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x14, 8, 6)\n#define SET_TX_DESC_BUFFER_HW_AES_IV(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 7, 1, value)\n#define GET_TX_DESC_BUFFER_HW_AES_IV(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x14, 7, 1)\n#define SET_TX_DESC_BUFFER_BT_NULL(txdesc, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 3, 1, value)\n#define GET_TX_DESC_BUFFER_BT_NULL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 3, 1)\n#define SET_TX_DESC_BUFFER_EN_DESC_ID(txdesc, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 2, 1, value)\n#define GET_TX_DESC_BUFFER_EN_DESC_ID(txdesc)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x14, 2, 1)\n#define SET_TX_DESC_BUFFER_SECTYPE(txdesc, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 0, 2, value)\n#define GET_TX_DESC_BUFFER_SECTYPE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 0, 2)\n\n/*TXDESC_WORD6*/\n\n#define SET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 29, 3, value)\n#define GET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc)                               \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x18, 29, 3)\n#define SET_TX_DESC_BUFFER_POLLUTED(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 1, value)\n#define GET_TX_DESC_BUFFER_POLLUTED(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x18, 28, 1)\n#define SET_TX_DESC_BUFFER_NULL_1(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 27, 1, value)\n#define GET_TX_DESC_BUFFER_NULL_1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 27, 1)\n#define SET_TX_DESC_BUFFER_NULL_0(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 1, value)\n#define GET_TX_DESC_BUFFER_NULL_0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 1)\n#define SET_TX_DESC_BUFFER_TRI_FRAME(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 25, 1, value)\n#define GET_TX_DESC_BUFFER_TRI_FRAME(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x18, 25, 1)\n#define SET_TX_DESC_BUFFER_SPE_RPT(txdesc, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 1, value)\n#define GET_TX_DESC_BUFFER_SPE_RPT(txdesc)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x18, 24, 1)\n#define SET_TX_DESC_BUFFER_FTM_EN(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 23, 1, value)\n#define GET_TX_DESC_BUFFER_FTM_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 23, 1)\n#define SET_TX_DESC_BUFFER_MU_DATARATE(txdesc, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 7, value)\n#define GET_TX_DESC_BUFFER_MU_DATARATE(txdesc)                                 \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x18, 16, 7)\n#define SET_TX_DESC_BUFFER_CCA_RTS(txdesc, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 14, 2, value)\n#define GET_TX_DESC_BUFFER_CCA_RTS(txdesc)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x18, 14, 2)\n#define SET_TX_DESC_BUFFER_NDPA(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 12, 2, value)\n#define GET_TX_DESC_BUFFER_NDPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 12, 2)\n#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc, value)                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 9, 2, value)\n#define GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc)                            \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x18, 9, 2)\n#define SET_TX_DESC_BUFFER_P_AID(txdesc, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 9, value)\n#define GET_TX_DESC_BUFFER_P_AID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 9)\n\n/*TXDESC_WORD7*/\n\n#define SET_TX_DESC_BUFFER_SW_DEFINE(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 16, 12, value)\n#define GET_TX_DESC_BUFFER_SW_DEFINE(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x1C, 16, 12)\n#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 9, 1, value)\n#define GET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc)                              \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x1C, 9, 1)\n#define SET_TX_DESC_BUFFER_CTRL_CNT(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 5, 4, value)\n#define GET_TX_DESC_BUFFER_CTRL_CNT(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x1C, 5, 4)\n#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 5, value)\n#define GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc)                        \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 5)\n\n/*TXDESC_WORD8*/\n\n#define SET_TX_DESC_BUFFER_PATH_MAPA(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 30, 2, value)\n#define GET_TX_DESC_BUFFER_PATH_MAPA(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x20, 30, 2)\n#define SET_TX_DESC_BUFFER_PATH_MAPB(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 28, 2, value)\n#define GET_TX_DESC_BUFFER_PATH_MAPB(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x20, 28, 2)\n#define SET_TX_DESC_BUFFER_PATH_MAPC(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 26, 2, value)\n#define GET_TX_DESC_BUFFER_PATH_MAPC(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x20, 26, 2)\n#define SET_TX_DESC_BUFFER_PATH_MAPD(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 2, value)\n#define GET_TX_DESC_BUFFER_PATH_MAPD(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x20, 24, 2)\n#define SET_TX_DESC_BUFFER_ANTSEL_A(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 20, 4, value)\n#define GET_TX_DESC_BUFFER_ANTSEL_A(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x20, 20, 4)\n#define SET_TX_DESC_BUFFER_ANTSEL_B(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 4, value)\n#define GET_TX_DESC_BUFFER_ANTSEL_B(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x20, 16, 4)\n#define SET_TX_DESC_BUFFER_ANTSEL_C(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 12, 4, value)\n#define GET_TX_DESC_BUFFER_ANTSEL_C(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x20, 12, 4)\n#define SET_TX_DESC_BUFFER_ANTSEL_D(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 8, 4, value)\n#define GET_TX_DESC_BUFFER_ANTSEL_D(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x20, 8, 4)\n#define SET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 4, 4, value)\n#define GET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc)                                 \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x20, 4, 4)\n#define SET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 3, 1, value)\n#define GET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x20, 3, 1)\n#define SET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 0, 3, value)\n#define GET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc)                               \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x20, 0, 3)\n\n/*TXDESC_WORD9*/\n\n#define SET_TX_DESC_BUFFER_VCS_STBC(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 30, 2, value)\n#define GET_TX_DESC_BUFFER_VCS_STBC(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x24, 30, 2)\n#define SET_TX_DESC_BUFFER_DATA_STBC(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 28, 2, value)\n#define GET_TX_DESC_BUFFER_DATA_STBC(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x24, 28, 2)\n#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc, value)                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 24, 4, value)\n#define GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc)                         \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x24, 24, 4)\n#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc, value)                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 23, 1, value)\n#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc)                         \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x24, 23, 1)\n#define SET_TX_DESC_BUFFER_MHR_CP(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 22, 1, value)\n#define GET_TX_DESC_BUFFER_MHR_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 22, 1)\n#define SET_TX_DESC_BUFFER_SMH_EN(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 21, 1, value)\n#define GET_TX_DESC_BUFFER_SMH_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 21, 1)\n#define SET_TX_DESC_BUFFER_RTSRATE(txdesc, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 16, 5, value)\n#define GET_TX_DESC_BUFFER_RTSRATE(txdesc)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x24, 16, 5)\n#define SET_TX_DESC_BUFFER_SMH_CAM(txdesc, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 8, 8, value)\n#define GET_TX_DESC_BUFFER_SMH_CAM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 8, 8)\n#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 7, 1, value)\n#define GET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc)                              \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x24, 7, 1)\n#define SET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 6, 1, value)\n#define GET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x24, 6, 1)\n#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 5, 1, value)\n#define GET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc)                                \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x24, 5, 1)\n#define SET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 4, 1, value)\n#define GET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc)                                 \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x24, 4, 1)\n#define SET_TX_DESC_BUFFER_RTS_SHORT(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 3, 1, value)\n#define GET_TX_DESC_BUFFER_RTS_SHORT(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x24, 3, 1)\n#define SET_TX_DESC_BUFFER_DISDATAFB(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 2, 1, value)\n#define GET_TX_DESC_BUFFER_DISDATAFB(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x24, 2, 1)\n#define SET_TX_DESC_BUFFER_DISRTSFB(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 1, 1, value)\n#define GET_TX_DESC_BUFFER_DISRTSFB(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x24, 1, 1)\n#define SET_TX_DESC_BUFFER_EXT_EDCA(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 1, value)\n#define GET_TX_DESC_BUFFER_EXT_EDCA(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x24, 0, 1)\n\n/*TXDESC_WORD10*/\n\n#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 24, 8, value)\n#define GET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc)                              \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x28, 24, 8)\n#define SET_TX_DESC_BUFFER_SPECIAL_CW(txdesc, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 23, 1, value)\n#define GET_TX_DESC_BUFFER_SPECIAL_CW(txdesc)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x28, 23, 1)\n#define SET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 22, 1, value)\n#define GET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc)                                 \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x28, 22, 1)\n#define SET_TX_DESC_BUFFER_RAW(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 21, 1, value)\n#define GET_TX_DESC_BUFFER_RAW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 21, 1)\n#define SET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 16, 5, value)\n#define GET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc)                                 \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x28, 16, 5)\n#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 8, 8, value)\n#define GET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc)                             \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x28, 8, 8)\n#define SET_TX_DESC_BUFFER_GF(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 7, 1, value)\n#define GET_TX_DESC_BUFFER_GF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 7, 1)\n#define SET_TX_DESC_BUFFER_MOREFRAG(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 6, 1, value)\n#define GET_TX_DESC_BUFFER_MOREFRAG(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x28, 6, 1)\n#define SET_TX_DESC_BUFFER_NOACM(txdesc, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 5, 1, value)\n#define GET_TX_DESC_BUFFER_NOACM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 5, 1)\n#define SET_TX_DESC_BUFFER_HTC(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 4, 1, value)\n#define GET_TX_DESC_BUFFER_HTC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 4, 1)\n#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 3, 1, value)\n#define GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc)                           \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x28, 3, 1)\n#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 2, 1, value)\n#define GET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc)                             \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x28, 2, 1)\n#define SET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 0, 2, value)\n#define GET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x28, 0, 2)\n\n/*TXDESC_WORD11*/\n\n#define SET_TX_DESC_BUFFER_ADDR_CAM(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 24, 8, value)\n#define GET_TX_DESC_BUFFER_ADDR_CAM(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x2C, 24, 8)\n#define SET_TX_DESC_BUFFER_SND_TARGET(txdesc, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 16, 8, value)\n#define GET_TX_DESC_BUFFER_SND_TARGET(txdesc)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x2C, 16, 8)\n#define SET_TX_DESC_BUFFER_DATA_LDPC(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 15, 1, value)\n#define GET_TX_DESC_BUFFER_DATA_LDPC(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x2C, 15, 1)\n#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 14, 1, value)\n#define GET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc)                                \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x2C, 14, 1)\n#define SET_TX_DESC_BUFFER_G_ID(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 8, 6, value)\n#define GET_TX_DESC_BUFFER_G_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x2C, 8, 6)\n#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc, value)                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 4, 4, value)\n#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc)                         \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x2C, 4, 4)\n#define SET_TX_DESC_BUFFER_DATA_SC(txdesc, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 0, 4, value)\n#define GET_TX_DESC_BUFFER_DATA_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x2C, 0, 4)\n\n/*TXDESC_WORD12*/\n\n#define SET_TX_DESC_BUFFER_LEN1_L(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x30, 17, 7, value)\n#define GET_TX_DESC_BUFFER_LEN1_L(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 17, 7)\n#define SET_TX_DESC_BUFFER_LEN0(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x30, 4, 13, value)\n#define GET_TX_DESC_BUFFER_LEN0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 4, 13)\n#define SET_TX_DESC_BUFFER_PKT_NUM(txdesc, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x30, 0, 4, value)\n#define GET_TX_DESC_BUFFER_PKT_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 0, 4)\n\n/*TXDESC_WORD13*/\n\n#define SET_TX_DESC_BUFFER_LEN3(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x34, 19, 13, value)\n#define GET_TX_DESC_BUFFER_LEN3(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 19, 13)\n#define SET_TX_DESC_BUFFER_LEN2(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x34, 6, 13, value)\n#define GET_TX_DESC_BUFFER_LEN2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 6, 13)\n#define SET_TX_DESC_BUFFER_LEN1_H(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x34, 0, 6, value)\n#define GET_TX_DESC_BUFFER_LEN1_H(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 0, 6)\n\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_tx_desc_chip.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_TX_DESC_CHIP_H_\n#define _HALMAC_TX_DESC_CHIP_H_\n#if (HALMAC_8814A_SUPPORT)\n\n/*TXDESC_WORD0*/\n\n#define SET_TX_DESC_DISQSELSEQ_8814A(txdesc, value)                            \\\n\tSET_TX_DESC_DISQSELSEQ(txdesc, value)\n#define GET_TX_DESC_DISQSELSEQ_8814A(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)\n#define SET_TX_DESC_GF_8814A(txdesc, value) SET_TX_DESC_GF(txdesc, value)\n#define GET_TX_DESC_GF_8814A(txdesc) GET_TX_DESC_GF(txdesc)\n#define SET_TX_DESC_NO_ACM_8814A(txdesc, value)                                \\\n\tSET_TX_DESC_NO_ACM(txdesc, value)\n#define GET_TX_DESC_NO_ACM_8814A(txdesc) GET_TX_DESC_NO_ACM(txdesc)\n#define SET_TX_DESC_AMSDU_PAD_EN_8814A(txdesc, value)                          \\\n\tSET_TX_DESC_AMSDU_PAD_EN(txdesc, value)\n#define GET_TX_DESC_AMSDU_PAD_EN_8814A(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)\n#define SET_TX_DESC_LS_8814A(txdesc, value) SET_TX_DESC_LS(txdesc, value)\n#define GET_TX_DESC_LS_8814A(txdesc) GET_TX_DESC_LS(txdesc)\n#define SET_TX_DESC_HTC_8814A(txdesc, value) SET_TX_DESC_HTC(txdesc, value)\n#define GET_TX_DESC_HTC_8814A(txdesc) GET_TX_DESC_HTC(txdesc)\n#define SET_TX_DESC_BMC_8814A(txdesc, value) SET_TX_DESC_BMC(txdesc, value)\n#define GET_TX_DESC_BMC_8814A(txdesc) GET_TX_DESC_BMC(txdesc)\n#define SET_TX_DESC_OFFSET_8814A(txdesc, value)                                \\\n\tSET_TX_DESC_OFFSET(txdesc, value)\n#define GET_TX_DESC_OFFSET_8814A(txdesc) GET_TX_DESC_OFFSET(txdesc)\n#define SET_TX_DESC_TXPKTSIZE_8814A(txdesc, value)                             \\\n\tSET_TX_DESC_TXPKTSIZE(txdesc, value)\n#define GET_TX_DESC_TXPKTSIZE_8814A(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)\n\n/*WORD1*/\n\n#define SET_TX_DESC_MOREDATA_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_MOREDATA(txdesc, value)\n#define GET_TX_DESC_MOREDATA_8814A(txdesc) GET_TX_DESC_MOREDATA(txdesc)\n#define SET_TX_DESC_PKT_OFFSET_8814A(txdesc, value)                            \\\n\tSET_TX_DESC_PKT_OFFSET(txdesc, value)\n#define GET_TX_DESC_PKT_OFFSET_8814A(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)\n#define SET_TX_DESC_SEC_TYPE_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_SEC_TYPE(txdesc, value)\n#define GET_TX_DESC_SEC_TYPE_8814A(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)\n#define SET_TX_DESC_EN_DESC_ID_8814A(txdesc, value)                            \\\n\tSET_TX_DESC_EN_DESC_ID(txdesc, value)\n#define GET_TX_DESC_EN_DESC_ID_8814A(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)\n#define SET_TX_DESC_RATE_ID_8814A(txdesc, value)                               \\\n\tSET_TX_DESC_RATE_ID(txdesc, value)\n#define GET_TX_DESC_RATE_ID_8814A(txdesc) GET_TX_DESC_RATE_ID(txdesc)\n#define SET_TX_DESC_PIFS_8814A(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)\n#define GET_TX_DESC_PIFS_8814A(txdesc) GET_TX_DESC_PIFS(txdesc)\n#define SET_TX_DESC_LSIG_TXOP_EN_8814A(txdesc, value)                          \\\n\tSET_TX_DESC_LSIG_TXOP_EN(txdesc, value)\n#define GET_TX_DESC_LSIG_TXOP_EN_8814A(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)\n#define SET_TX_DESC_RD_NAV_EXT_8814A(txdesc, value)                            \\\n\tSET_TX_DESC_RD_NAV_EXT(txdesc, value)\n#define GET_TX_DESC_RD_NAV_EXT_8814A(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)\n#define SET_TX_DESC_QSEL_8814A(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)\n#define GET_TX_DESC_QSEL_8814A(txdesc) GET_TX_DESC_QSEL(txdesc)\n#define SET_TX_DESC_MACID_8814A(txdesc, value) SET_TX_DESC_MACID(txdesc, value)\n#define GET_TX_DESC_MACID_8814A(txdesc) GET_TX_DESC_MACID(txdesc)\n\n/*TXDESC_WORD2*/\n\n#define SET_TX_DESC_HW_AES_IV_8814A(txdesc, value)                             \\\n\tSET_TX_DESC_HW_AES_IV(txdesc, value)\n#define GET_TX_DESC_HW_AES_IV_8814A(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)\n#define SET_TX_DESC_G_ID_8814A(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)\n#define GET_TX_DESC_G_ID_8814A(txdesc) GET_TX_DESC_G_ID(txdesc)\n#define SET_TX_DESC_BT_NULL_8814A(txdesc, value)                               \\\n\tSET_TX_DESC_BT_NULL(txdesc, value)\n#define GET_TX_DESC_BT_NULL_8814A(txdesc) GET_TX_DESC_BT_NULL(txdesc)\n#define SET_TX_DESC_AMPDU_DENSITY_8814A(txdesc, value)                         \\\n\tSET_TX_DESC_AMPDU_DENSITY(txdesc, value)\n#define GET_TX_DESC_AMPDU_DENSITY_8814A(txdesc)                                \\\n\tGET_TX_DESC_AMPDU_DENSITY(txdesc)\n#define SET_TX_DESC_SPE_RPT_8814A(txdesc, value)                               \\\n\tSET_TX_DESC_SPE_RPT(txdesc, value)\n#define GET_TX_DESC_SPE_RPT_8814A(txdesc) GET_TX_DESC_SPE_RPT(txdesc)\n#define SET_TX_DESC_RAW_8814A(txdesc, value) SET_TX_DESC_RAW(txdesc, value)\n#define GET_TX_DESC_RAW_8814A(txdesc) GET_TX_DESC_RAW(txdesc)\n#define SET_TX_DESC_MOREFRAG_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_MOREFRAG(txdesc, value)\n#define GET_TX_DESC_MOREFRAG_8814A(txdesc) GET_TX_DESC_MOREFRAG(txdesc)\n#define SET_TX_DESC_BK_8814A(txdesc, value) SET_TX_DESC_BK(txdesc, value)\n#define GET_TX_DESC_BK_8814A(txdesc) GET_TX_DESC_BK(txdesc)\n#define SET_TX_DESC_NULL_1_8814A(txdesc, value)                                \\\n\tSET_TX_DESC_NULL_1(txdesc, value)\n#define GET_TX_DESC_NULL_1_8814A(txdesc) GET_TX_DESC_NULL_1(txdesc)\n#define SET_TX_DESC_NULL_0_8814A(txdesc, value)                                \\\n\tSET_TX_DESC_NULL_0(txdesc, value)\n#define GET_TX_DESC_NULL_0_8814A(txdesc) GET_TX_DESC_NULL_0(txdesc)\n#define SET_TX_DESC_RDG_EN_8814A(txdesc, value)                                \\\n\tSET_TX_DESC_RDG_EN(txdesc, value)\n#define GET_TX_DESC_RDG_EN_8814A(txdesc) GET_TX_DESC_RDG_EN(txdesc)\n#define SET_TX_DESC_AGG_EN_8814A(txdesc, value)                                \\\n\tSET_TX_DESC_AGG_EN(txdesc, value)\n#define GET_TX_DESC_AGG_EN_8814A(txdesc) GET_TX_DESC_AGG_EN(txdesc)\n#define SET_TX_DESC_CCA_RTS_8814A(txdesc, value)                               \\\n\tSET_TX_DESC_CCA_RTS(txdesc, value)\n#define GET_TX_DESC_CCA_RTS_8814A(txdesc) GET_TX_DESC_CCA_RTS(txdesc)\n#define SET_TX_DESC_P_AID_8814A(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)\n#define GET_TX_DESC_P_AID_8814A(txdesc) GET_TX_DESC_P_AID(txdesc)\n\n/*TXDESC_WORD3*/\n\n#define SET_TX_DESC_AMPDU_MAX_TIME_8814A(txdesc, value)                        \\\n\tSET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)\n#define GET_TX_DESC_AMPDU_MAX_TIME_8814A(txdesc)                               \\\n\tGET_TX_DESC_AMPDU_MAX_TIME(txdesc)\n#define SET_TX_DESC_NDPA_8814A(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)\n#define GET_TX_DESC_NDPA_8814A(txdesc) GET_TX_DESC_NDPA(txdesc)\n#define SET_TX_DESC_MAX_AGG_NUM_8814A(txdesc, value)                           \\\n\tSET_TX_DESC_MAX_AGG_NUM(txdesc, value)\n#define GET_TX_DESC_MAX_AGG_NUM_8814A(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)\n#define SET_TX_DESC_USE_MAX_TIME_EN_8814A(txdesc, value)                       \\\n\tSET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)\n#define GET_TX_DESC_USE_MAX_TIME_EN_8814A(txdesc)                              \\\n\tGET_TX_DESC_USE_MAX_TIME_EN(txdesc)\n#define SET_TX_DESC_NAVUSEHDR_8814A(txdesc, value)                             \\\n\tSET_TX_DESC_NAVUSEHDR(txdesc, value)\n#define GET_TX_DESC_NAVUSEHDR_8814A(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)\n#define SET_TX_DESC_CHK_EN_8814A(txdesc, value)                                \\\n\tSET_TX_DESC_CHK_EN(txdesc, value)\n#define GET_TX_DESC_CHK_EN_8814A(txdesc) GET_TX_DESC_CHK_EN(txdesc)\n#define SET_TX_DESC_HW_RTS_EN_8814A(txdesc, value)                             \\\n\tSET_TX_DESC_HW_RTS_EN(txdesc, value)\n#define GET_TX_DESC_HW_RTS_EN_8814A(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)\n#define SET_TX_DESC_RTSEN_8814A(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)\n#define GET_TX_DESC_RTSEN_8814A(txdesc) GET_TX_DESC_RTSEN(txdesc)\n#define SET_TX_DESC_CTS2SELF_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_CTS2SELF(txdesc, value)\n#define GET_TX_DESC_CTS2SELF_8814A(txdesc) GET_TX_DESC_CTS2SELF(txdesc)\n#define SET_TX_DESC_DISDATAFB_8814A(txdesc, value)                             \\\n\tSET_TX_DESC_DISDATAFB(txdesc, value)\n#define GET_TX_DESC_DISDATAFB_8814A(txdesc) GET_TX_DESC_DISDATAFB(txdesc)\n#define SET_TX_DESC_DISRTSFB_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_DISRTSFB(txdesc, value)\n#define GET_TX_DESC_DISRTSFB_8814A(txdesc) GET_TX_DESC_DISRTSFB(txdesc)\n#define SET_TX_DESC_USE_RATE_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_USE_RATE(txdesc, value)\n#define GET_TX_DESC_USE_RATE_8814A(txdesc) GET_TX_DESC_USE_RATE(txdesc)\n#define SET_TX_DESC_HW_SSN_SEL_8814A(txdesc, value)                            \\\n\tSET_TX_DESC_HW_SSN_SEL(txdesc, value)\n#define GET_TX_DESC_HW_SSN_SEL_8814A(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)\n#define SET_TX_DESC_WHEADER_LEN_8814A(txdesc, value)                           \\\n\tSET_TX_DESC_WHEADER_LEN(txdesc, value)\n#define GET_TX_DESC_WHEADER_LEN_8814A(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)\n\n/*TXDESC_WORD4*/\n\n#define SET_TX_DESC_PCTS_MASK_IDX_8814A(txdesc, value)                         \\\n\tSET_TX_DESC_PCTS_MASK_IDX(txdesc, value)\n#define GET_TX_DESC_PCTS_MASK_IDX_8814A(txdesc)                                \\\n\tGET_TX_DESC_PCTS_MASK_IDX(txdesc)\n#define SET_TX_DESC_PCTS_EN_8814A(txdesc, value)                               \\\n\tSET_TX_DESC_PCTS_EN(txdesc, value)\n#define GET_TX_DESC_PCTS_EN_8814A(txdesc) GET_TX_DESC_PCTS_EN(txdesc)\n#define SET_TX_DESC_RTSRATE_8814A(txdesc, value)                               \\\n\tSET_TX_DESC_RTSRATE(txdesc, value)\n#define GET_TX_DESC_RTSRATE_8814A(txdesc) GET_TX_DESC_RTSRATE(txdesc)\n#define SET_TX_DESC_RTS_DATA_RTY_LMT_8814A(txdesc, value)                      \\\n\tSET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)\n#define GET_TX_DESC_RTS_DATA_RTY_LMT_8814A(txdesc)                             \\\n\tGET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)\n#define SET_TX_DESC_RTY_LMT_EN_8814A(txdesc, value)                            \\\n\tSET_TX_DESC_RTY_LMT_EN(txdesc, value)\n#define GET_TX_DESC_RTY_LMT_EN_8814A(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)\n#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8814A(txdesc, value)                   \\\n\tSET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8814A(txdesc)                          \\\n\tGET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)\n#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8814A(txdesc, value)                  \\\n\tSET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8814A(txdesc)                         \\\n\tGET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)\n#define SET_TX_DESC_TRY_RATE_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_TRY_RATE(txdesc, value)\n#define GET_TX_DESC_TRY_RATE_8814A(txdesc) GET_TX_DESC_TRY_RATE(txdesc)\n#define SET_TX_DESC_DATARATE_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_DATARATE(txdesc, value)\n#define GET_TX_DESC_DATARATE_8814A(txdesc) GET_TX_DESC_DATARATE(txdesc)\n\n/*TXDESC_WORD5*/\n\n#define SET_TX_DESC_POLLUTED_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_POLLUTED(txdesc, value)\n#define GET_TX_DESC_POLLUTED_8814A(txdesc) GET_TX_DESC_POLLUTED(txdesc)\n#define SET_TX_DESC_TXPWR_OFSET_8814A(txdesc, value)                           \\\n\tSET_TX_DESC_TXPWR_OFSET(txdesc, value)\n#define GET_TX_DESC_TXPWR_OFSET_8814A(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc)\n#define SET_TX_DESC_TX_ANT_8814A(txdesc, value)                                \\\n\tSET_TX_DESC_TX_ANT(txdesc, value)\n#define GET_TX_DESC_TX_ANT_8814A(txdesc) GET_TX_DESC_TX_ANT(txdesc)\n#define SET_TX_DESC_PORT_ID_8814A(txdesc, value)                               \\\n\tSET_TX_DESC_PORT_ID(txdesc, value)\n#define GET_TX_DESC_PORT_ID_8814A(txdesc) GET_TX_DESC_PORT_ID(txdesc)\n#define SET_TX_DESC_SIGNALING_TAPKT_EN_8814A(txdesc, value)                    \\\n\tSET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)\n#define GET_TX_DESC_SIGNALING_TAPKT_EN_8814A(txdesc)                           \\\n\tGET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)\n#define SET_TX_DESC_RTS_SC_8814A(txdesc, value)                                \\\n\tSET_TX_DESC_RTS_SC(txdesc, value)\n#define GET_TX_DESC_RTS_SC_8814A(txdesc) GET_TX_DESC_RTS_SC(txdesc)\n#define SET_TX_DESC_RTS_SHORT_8814A(txdesc, value)                             \\\n\tSET_TX_DESC_RTS_SHORT(txdesc, value)\n#define GET_TX_DESC_RTS_SHORT_8814A(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)\n#define SET_TX_DESC_VCS_STBC_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_VCS_STBC(txdesc, value)\n#define GET_TX_DESC_VCS_STBC_8814A(txdesc) GET_TX_DESC_VCS_STBC(txdesc)\n#define SET_TX_DESC_DATA_STBC_8814A(txdesc, value)                             \\\n\tSET_TX_DESC_DATA_STBC(txdesc, value)\n#define GET_TX_DESC_DATA_STBC_8814A(txdesc) GET_TX_DESC_DATA_STBC(txdesc)\n#define SET_TX_DESC_DATA_LDPC_8814A(txdesc, value)                             \\\n\tSET_TX_DESC_DATA_LDPC(txdesc, value)\n#define GET_TX_DESC_DATA_LDPC_8814A(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)\n#define SET_TX_DESC_DATA_BW_8814A(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_BW(txdesc, value)\n#define GET_TX_DESC_DATA_BW_8814A(txdesc) GET_TX_DESC_DATA_BW(txdesc)\n#define SET_TX_DESC_DATA_SHORT_8814A(txdesc, value)                            \\\n\tSET_TX_DESC_DATA_SHORT(txdesc, value)\n#define GET_TX_DESC_DATA_SHORT_8814A(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)\n#define SET_TX_DESC_DATA_SC_8814A(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_SC(txdesc, value)\n#define GET_TX_DESC_DATA_SC_8814A(txdesc) GET_TX_DESC_DATA_SC(txdesc)\n\n/*TXDESC_WORD6*/\n\n#define SET_TX_DESC_ANTSEL_D_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_D(txdesc, value)\n#define GET_TX_DESC_ANTSEL_D_8814A(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)\n#define SET_TX_DESC_ANT_MAPD_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPD(txdesc, value)\n#define GET_TX_DESC_ANT_MAPD_8814A(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)\n#define SET_TX_DESC_ANT_MAPC_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPC(txdesc, value)\n#define GET_TX_DESC_ANT_MAPC_8814A(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)\n#define SET_TX_DESC_ANT_MAPB_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPB(txdesc, value)\n#define GET_TX_DESC_ANT_MAPB_8814A(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)\n#define SET_TX_DESC_ANT_MAPA_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPA(txdesc, value)\n#define GET_TX_DESC_ANT_MAPA_8814A(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)\n#define SET_TX_DESC_ANTSEL_C_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_C(txdesc, value)\n#define GET_TX_DESC_ANTSEL_C_8814A(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)\n#define SET_TX_DESC_ANTSEL_B_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_B(txdesc, value)\n#define GET_TX_DESC_ANTSEL_B_8814A(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)\n#define SET_TX_DESC_ANTSEL_A_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_A(txdesc, value)\n#define GET_TX_DESC_ANTSEL_A_8814A(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)\n#define SET_TX_DESC_MBSSID_8814A(txdesc, value)                                \\\n\tSET_TX_DESC_MBSSID(txdesc, value)\n#define GET_TX_DESC_MBSSID_8814A(txdesc) GET_TX_DESC_MBSSID(txdesc)\n#define SET_TX_DESC_SW_DEFINE_8814A(txdesc, value)                             \\\n\tSET_TX_DESC_SW_DEFINE(txdesc, value)\n#define GET_TX_DESC_SW_DEFINE_8814A(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)\n\n/*TXDESC_WORD7*/\n\n#define SET_TX_DESC_DMA_TXAGG_NUM_8814A(txdesc, value)                         \\\n\tSET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)\n#define GET_TX_DESC_DMA_TXAGG_NUM_8814A(txdesc)                                \\\n\tGET_TX_DESC_DMA_TXAGG_NUM(txdesc)\n#define SET_TX_DESC_FINAL_DATA_RATE_8814A(txdesc, value)                       \\\n\tSET_TX_DESC_FINAL_DATA_RATE(txdesc, value)\n#define GET_TX_DESC_FINAL_DATA_RATE_8814A(txdesc)                              \\\n\tGET_TX_DESC_FINAL_DATA_RATE(txdesc)\n#define SET_TX_DESC_NTX_MAP_8814A(txdesc, value)                               \\\n\tSET_TX_DESC_NTX_MAP(txdesc, value)\n#define GET_TX_DESC_NTX_MAP_8814A(txdesc) GET_TX_DESC_NTX_MAP(txdesc)\n#define SET_TX_DESC_TX_BUFF_SIZE_8814A(txdesc, value)                          \\\n\tSET_TX_DESC_TX_BUFF_SIZE(txdesc, value)\n#define GET_TX_DESC_TX_BUFF_SIZE_8814A(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)\n#define SET_TX_DESC_TXDESC_CHECKSUM_8814A(txdesc, value)                       \\\n\tSET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)\n#define GET_TX_DESC_TXDESC_CHECKSUM_8814A(txdesc)                              \\\n\tGET_TX_DESC_TXDESC_CHECKSUM(txdesc)\n#define SET_TX_DESC_TIMESTAMP_8814A(txdesc, value)                             \\\n\tSET_TX_DESC_TIMESTAMP(txdesc, value)\n#define GET_TX_DESC_TIMESTAMP_8814A(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)\n\n/*TXDESC_WORD8*/\n\n#define SET_TX_DESC_TXWIFI_CP_8814A(txdesc, value)                             \\\n\tSET_TX_DESC_TXWIFI_CP(txdesc, value)\n#define GET_TX_DESC_TXWIFI_CP_8814A(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)\n#define SET_TX_DESC_MAC_CP_8814A(txdesc, value)                                \\\n\tSET_TX_DESC_MAC_CP(txdesc, value)\n#define GET_TX_DESC_MAC_CP_8814A(txdesc) GET_TX_DESC_MAC_CP(txdesc)\n#define SET_TX_DESC_STW_PKTRE_DIS_8814A(txdesc, value)                         \\\n\tSET_TX_DESC_STW_PKTRE_DIS(txdesc, value)\n#define GET_TX_DESC_STW_PKTRE_DIS_8814A(txdesc)                                \\\n\tGET_TX_DESC_STW_PKTRE_DIS(txdesc)\n#define SET_TX_DESC_STW_RB_DIS_8814A(txdesc, value)                            \\\n\tSET_TX_DESC_STW_RB_DIS(txdesc, value)\n#define GET_TX_DESC_STW_RB_DIS_8814A(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)\n#define SET_TX_DESC_STW_RATE_DIS_8814A(txdesc, value)                          \\\n\tSET_TX_DESC_STW_RATE_DIS(txdesc, value)\n#define GET_TX_DESC_STW_RATE_DIS_8814A(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)\n#define SET_TX_DESC_STW_ANT_DIS_8814A(txdesc, value)                           \\\n\tSET_TX_DESC_STW_ANT_DIS(txdesc, value)\n#define GET_TX_DESC_STW_ANT_DIS_8814A(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)\n#define SET_TX_DESC_STW_EN_8814A(txdesc, value)                                \\\n\tSET_TX_DESC_STW_EN(txdesc, value)\n#define GET_TX_DESC_STW_EN_8814A(txdesc) GET_TX_DESC_STW_EN(txdesc)\n#define SET_TX_DESC_SMH_EN_8814A(txdesc, value)                                \\\n\tSET_TX_DESC_SMH_EN(txdesc, value)\n#define GET_TX_DESC_SMH_EN_8814A(txdesc) GET_TX_DESC_SMH_EN(txdesc)\n#define SET_TX_DESC_TAILPAGE_L_8814A(txdesc, value)                            \\\n\tSET_TX_DESC_TAILPAGE_L(txdesc, value)\n#define GET_TX_DESC_TAILPAGE_L_8814A(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)\n#define SET_TX_DESC_SDIO_DMASEQ_8814A(txdesc, value)                           \\\n\tSET_TX_DESC_SDIO_DMASEQ(txdesc, value)\n#define GET_TX_DESC_SDIO_DMASEQ_8814A(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)\n#define SET_TX_DESC_NEXTHEADPAGE_L_8814A(txdesc, value)                        \\\n\tSET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)\n#define GET_TX_DESC_NEXTHEADPAGE_L_8814A(txdesc)                               \\\n\tGET_TX_DESC_NEXTHEADPAGE_L(txdesc)\n#define SET_TX_DESC_EN_HWSEQ_8814A(txdesc, value)                              \\\n\tSET_TX_DESC_EN_HWSEQ(txdesc, value)\n#define GET_TX_DESC_EN_HWSEQ_8814A(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)\n#define SET_TX_DESC_EN_HWEXSEQ_8814A(txdesc, value)                            \\\n\tSET_TX_DESC_EN_HWEXSEQ(txdesc, value)\n#define GET_TX_DESC_EN_HWEXSEQ_8814A(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)\n#define SET_TX_DESC_DATA_RC_8814A(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_RC(txdesc, value)\n#define GET_TX_DESC_DATA_RC_8814A(txdesc) GET_TX_DESC_DATA_RC(txdesc)\n#define SET_TX_DESC_BAR_RTY_TH_8814A(txdesc, value)                            \\\n\tSET_TX_DESC_BAR_RTY_TH(txdesc, value)\n#define GET_TX_DESC_BAR_RTY_TH_8814A(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)\n#define SET_TX_DESC_RTS_RC_8814A(txdesc, value)                                \\\n\tSET_TX_DESC_RTS_RC(txdesc, value)\n#define GET_TX_DESC_RTS_RC_8814A(txdesc) GET_TX_DESC_RTS_RC(txdesc)\n\n/*TXDESC_WORD9*/\n\n#define SET_TX_DESC_TAILPAGE_H_8814A(txdesc, value)                            \\\n\tSET_TX_DESC_TAILPAGE_H(txdesc, value)\n#define GET_TX_DESC_TAILPAGE_H_8814A(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)\n#define SET_TX_DESC_NEXTHEADPAGE_H_8814A(txdesc, value)                        \\\n\tSET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)\n#define GET_TX_DESC_NEXTHEADPAGE_H_8814A(txdesc)                               \\\n\tGET_TX_DESC_NEXTHEADPAGE_H(txdesc)\n#define SET_TX_DESC_SW_SEQ_8814A(txdesc, value)                                \\\n\tSET_TX_DESC_SW_SEQ(txdesc, value)\n#define GET_TX_DESC_SW_SEQ_8814A(txdesc) GET_TX_DESC_SW_SEQ(txdesc)\n#define SET_TX_DESC_TXBF_PATH_8814A(txdesc, value)                             \\\n\tSET_TX_DESC_TXBF_PATH(txdesc, value)\n#define GET_TX_DESC_TXBF_PATH_8814A(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)\n#define SET_TX_DESC_PADDING_LEN_8814A(txdesc, value)                           \\\n\tSET_TX_DESC_PADDING_LEN(txdesc, value)\n#define GET_TX_DESC_PADDING_LEN_8814A(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)\n#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8814A(txdesc, value)                   \\\n\tSET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)\n#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8814A(txdesc)                          \\\n\tGET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)\n\n/*WORD10*/\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT)\n\n/*TXDESC_WORD0*/\n\n#define SET_TX_DESC_DISQSELSEQ_8822B(txdesc, value)                            \\\n\tSET_TX_DESC_DISQSELSEQ(txdesc, value)\n#define GET_TX_DESC_DISQSELSEQ_8822B(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)\n#define SET_TX_DESC_GF_8822B(txdesc, value) SET_TX_DESC_GF(txdesc, value)\n#define GET_TX_DESC_GF_8822B(txdesc) GET_TX_DESC_GF(txdesc)\n#define SET_TX_DESC_NO_ACM_8822B(txdesc, value)                                \\\n\tSET_TX_DESC_NO_ACM(txdesc, value)\n#define GET_TX_DESC_NO_ACM_8822B(txdesc) GET_TX_DESC_NO_ACM(txdesc)\n#define SET_TX_DESC_BCNPKT_TSF_CTRL_8822B(txdesc, value)                       \\\n\tSET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)\n#define GET_TX_DESC_BCNPKT_TSF_CTRL_8822B(txdesc)                              \\\n\tGET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)\n#define SET_TX_DESC_AMSDU_PAD_EN_8822B(txdesc, value)                          \\\n\tSET_TX_DESC_AMSDU_PAD_EN(txdesc, value)\n#define GET_TX_DESC_AMSDU_PAD_EN_8822B(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)\n#define SET_TX_DESC_LS_8822B(txdesc, value) SET_TX_DESC_LS(txdesc, value)\n#define GET_TX_DESC_LS_8822B(txdesc) GET_TX_DESC_LS(txdesc)\n#define SET_TX_DESC_HTC_8822B(txdesc, value) SET_TX_DESC_HTC(txdesc, value)\n#define GET_TX_DESC_HTC_8822B(txdesc) GET_TX_DESC_HTC(txdesc)\n#define SET_TX_DESC_BMC_8822B(txdesc, value) SET_TX_DESC_BMC(txdesc, value)\n#define GET_TX_DESC_BMC_8822B(txdesc) GET_TX_DESC_BMC(txdesc)\n#define SET_TX_DESC_OFFSET_8822B(txdesc, value)                                \\\n\tSET_TX_DESC_OFFSET(txdesc, value)\n#define GET_TX_DESC_OFFSET_8822B(txdesc) GET_TX_DESC_OFFSET(txdesc)\n#define SET_TX_DESC_TXPKTSIZE_8822B(txdesc, value)                             \\\n\tSET_TX_DESC_TXPKTSIZE(txdesc, value)\n#define GET_TX_DESC_TXPKTSIZE_8822B(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)\n\n/*WORD1*/\n\n#define SET_TX_DESC_MOREDATA_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_MOREDATA(txdesc, value)\n#define GET_TX_DESC_MOREDATA_8822B(txdesc) GET_TX_DESC_MOREDATA(txdesc)\n#define SET_TX_DESC_PKT_OFFSET_8822B(txdesc, value)                            \\\n\tSET_TX_DESC_PKT_OFFSET(txdesc, value)\n#define GET_TX_DESC_PKT_OFFSET_8822B(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)\n#define SET_TX_DESC_SEC_TYPE_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_SEC_TYPE(txdesc, value)\n#define GET_TX_DESC_SEC_TYPE_8822B(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)\n#define SET_TX_DESC_EN_DESC_ID_8822B(txdesc, value)                            \\\n\tSET_TX_DESC_EN_DESC_ID(txdesc, value)\n#define GET_TX_DESC_EN_DESC_ID_8822B(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)\n#define SET_TX_DESC_RATE_ID_8822B(txdesc, value)                               \\\n\tSET_TX_DESC_RATE_ID(txdesc, value)\n#define GET_TX_DESC_RATE_ID_8822B(txdesc) GET_TX_DESC_RATE_ID(txdesc)\n#define SET_TX_DESC_PIFS_8822B(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)\n#define GET_TX_DESC_PIFS_8822B(txdesc) GET_TX_DESC_PIFS(txdesc)\n#define SET_TX_DESC_LSIG_TXOP_EN_8822B(txdesc, value)                          \\\n\tSET_TX_DESC_LSIG_TXOP_EN(txdesc, value)\n#define GET_TX_DESC_LSIG_TXOP_EN_8822B(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)\n#define SET_TX_DESC_RD_NAV_EXT_8822B(txdesc, value)                            \\\n\tSET_TX_DESC_RD_NAV_EXT(txdesc, value)\n#define GET_TX_DESC_RD_NAV_EXT_8822B(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)\n#define SET_TX_DESC_QSEL_8822B(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)\n#define GET_TX_DESC_QSEL_8822B(txdesc) GET_TX_DESC_QSEL(txdesc)\n#define SET_TX_DESC_MACID_8822B(txdesc, value) SET_TX_DESC_MACID(txdesc, value)\n#define GET_TX_DESC_MACID_8822B(txdesc) GET_TX_DESC_MACID(txdesc)\n\n/*TXDESC_WORD2*/\n\n#define SET_TX_DESC_HW_AES_IV_8822B(txdesc, value)                             \\\n\tSET_TX_DESC_HW_AES_IV(txdesc, value)\n#define GET_TX_DESC_HW_AES_IV_8822B(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)\n#define SET_TX_DESC_FTM_EN_8822B(txdesc, value)                                \\\n\tSET_TX_DESC_FTM_EN(txdesc, value)\n#define GET_TX_DESC_FTM_EN_8822B(txdesc) GET_TX_DESC_FTM_EN(txdesc)\n#define SET_TX_DESC_G_ID_8822B(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)\n#define GET_TX_DESC_G_ID_8822B(txdesc) GET_TX_DESC_G_ID(txdesc)\n#define SET_TX_DESC_BT_NULL_8822B(txdesc, value)                               \\\n\tSET_TX_DESC_BT_NULL(txdesc, value)\n#define GET_TX_DESC_BT_NULL_8822B(txdesc) GET_TX_DESC_BT_NULL(txdesc)\n#define SET_TX_DESC_AMPDU_DENSITY_8822B(txdesc, value)                         \\\n\tSET_TX_DESC_AMPDU_DENSITY(txdesc, value)\n#define GET_TX_DESC_AMPDU_DENSITY_8822B(txdesc)                                \\\n\tGET_TX_DESC_AMPDU_DENSITY(txdesc)\n#define SET_TX_DESC_SPE_RPT_8822B(txdesc, value)                               \\\n\tSET_TX_DESC_SPE_RPT(txdesc, value)\n#define GET_TX_DESC_SPE_RPT_8822B(txdesc) GET_TX_DESC_SPE_RPT(txdesc)\n#define SET_TX_DESC_RAW_8822B(txdesc, value) SET_TX_DESC_RAW(txdesc, value)\n#define GET_TX_DESC_RAW_8822B(txdesc) GET_TX_DESC_RAW(txdesc)\n#define SET_TX_DESC_MOREFRAG_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_MOREFRAG(txdesc, value)\n#define GET_TX_DESC_MOREFRAG_8822B(txdesc) GET_TX_DESC_MOREFRAG(txdesc)\n#define SET_TX_DESC_BK_8822B(txdesc, value) SET_TX_DESC_BK(txdesc, value)\n#define GET_TX_DESC_BK_8822B(txdesc) GET_TX_DESC_BK(txdesc)\n#define SET_TX_DESC_NULL_1_8822B(txdesc, value)                                \\\n\tSET_TX_DESC_NULL_1(txdesc, value)\n#define GET_TX_DESC_NULL_1_8822B(txdesc) GET_TX_DESC_NULL_1(txdesc)\n#define SET_TX_DESC_NULL_0_8822B(txdesc, value)                                \\\n\tSET_TX_DESC_NULL_0(txdesc, value)\n#define GET_TX_DESC_NULL_0_8822B(txdesc) GET_TX_DESC_NULL_0(txdesc)\n#define SET_TX_DESC_RDG_EN_8822B(txdesc, value)                                \\\n\tSET_TX_DESC_RDG_EN(txdesc, value)\n#define GET_TX_DESC_RDG_EN_8822B(txdesc) GET_TX_DESC_RDG_EN(txdesc)\n#define SET_TX_DESC_AGG_EN_8822B(txdesc, value)                                \\\n\tSET_TX_DESC_AGG_EN(txdesc, value)\n#define GET_TX_DESC_AGG_EN_8822B(txdesc) GET_TX_DESC_AGG_EN(txdesc)\n#define SET_TX_DESC_CCA_RTS_8822B(txdesc, value)                               \\\n\tSET_TX_DESC_CCA_RTS(txdesc, value)\n#define GET_TX_DESC_CCA_RTS_8822B(txdesc) GET_TX_DESC_CCA_RTS(txdesc)\n#define SET_TX_DESC_TRI_FRAME_8822B(txdesc, value)                             \\\n\tSET_TX_DESC_TRI_FRAME(txdesc, value)\n#define GET_TX_DESC_TRI_FRAME_8822B(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)\n#define SET_TX_DESC_P_AID_8822B(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)\n#define GET_TX_DESC_P_AID_8822B(txdesc) GET_TX_DESC_P_AID(txdesc)\n\n/*TXDESC_WORD3*/\n\n#define SET_TX_DESC_AMPDU_MAX_TIME_8822B(txdesc, value)                        \\\n\tSET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)\n#define GET_TX_DESC_AMPDU_MAX_TIME_8822B(txdesc)                               \\\n\tGET_TX_DESC_AMPDU_MAX_TIME(txdesc)\n#define SET_TX_DESC_NDPA_8822B(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)\n#define GET_TX_DESC_NDPA_8822B(txdesc) GET_TX_DESC_NDPA(txdesc)\n#define SET_TX_DESC_MAX_AGG_NUM_8822B(txdesc, value)                           \\\n\tSET_TX_DESC_MAX_AGG_NUM(txdesc, value)\n#define GET_TX_DESC_MAX_AGG_NUM_8822B(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)\n#define SET_TX_DESC_USE_MAX_TIME_EN_8822B(txdesc, value)                       \\\n\tSET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)\n#define GET_TX_DESC_USE_MAX_TIME_EN_8822B(txdesc)                              \\\n\tGET_TX_DESC_USE_MAX_TIME_EN(txdesc)\n#define SET_TX_DESC_NAVUSEHDR_8822B(txdesc, value)                             \\\n\tSET_TX_DESC_NAVUSEHDR(txdesc, value)\n#define GET_TX_DESC_NAVUSEHDR_8822B(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)\n#define SET_TX_DESC_CHK_EN_8822B(txdesc, value)                                \\\n\tSET_TX_DESC_CHK_EN(txdesc, value)\n#define GET_TX_DESC_CHK_EN_8822B(txdesc) GET_TX_DESC_CHK_EN(txdesc)\n#define SET_TX_DESC_HW_RTS_EN_8822B(txdesc, value)                             \\\n\tSET_TX_DESC_HW_RTS_EN(txdesc, value)\n#define GET_TX_DESC_HW_RTS_EN_8822B(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)\n#define SET_TX_DESC_RTSEN_8822B(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)\n#define GET_TX_DESC_RTSEN_8822B(txdesc) GET_TX_DESC_RTSEN(txdesc)\n#define SET_TX_DESC_CTS2SELF_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_CTS2SELF(txdesc, value)\n#define GET_TX_DESC_CTS2SELF_8822B(txdesc) GET_TX_DESC_CTS2SELF(txdesc)\n#define SET_TX_DESC_DISDATAFB_8822B(txdesc, value)                             \\\n\tSET_TX_DESC_DISDATAFB(txdesc, value)\n#define GET_TX_DESC_DISDATAFB_8822B(txdesc) GET_TX_DESC_DISDATAFB(txdesc)\n#define SET_TX_DESC_DISRTSFB_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_DISRTSFB(txdesc, value)\n#define GET_TX_DESC_DISRTSFB_8822B(txdesc) GET_TX_DESC_DISRTSFB(txdesc)\n#define SET_TX_DESC_USE_RATE_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_USE_RATE(txdesc, value)\n#define GET_TX_DESC_USE_RATE_8822B(txdesc) GET_TX_DESC_USE_RATE(txdesc)\n#define SET_TX_DESC_HW_SSN_SEL_8822B(txdesc, value)                            \\\n\tSET_TX_DESC_HW_SSN_SEL(txdesc, value)\n#define GET_TX_DESC_HW_SSN_SEL_8822B(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)\n#define SET_TX_DESC_WHEADER_LEN_8822B(txdesc, value)                           \\\n\tSET_TX_DESC_WHEADER_LEN(txdesc, value)\n#define GET_TX_DESC_WHEADER_LEN_8822B(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)\n\n/*TXDESC_WORD4*/\n\n#define SET_TX_DESC_PCTS_MASK_IDX_8822B(txdesc, value)                         \\\n\tSET_TX_DESC_PCTS_MASK_IDX(txdesc, value)\n#define GET_TX_DESC_PCTS_MASK_IDX_8822B(txdesc)                                \\\n\tGET_TX_DESC_PCTS_MASK_IDX(txdesc)\n#define SET_TX_DESC_PCTS_EN_8822B(txdesc, value)                               \\\n\tSET_TX_DESC_PCTS_EN(txdesc, value)\n#define GET_TX_DESC_PCTS_EN_8822B(txdesc) GET_TX_DESC_PCTS_EN(txdesc)\n#define SET_TX_DESC_RTSRATE_8822B(txdesc, value)                               \\\n\tSET_TX_DESC_RTSRATE(txdesc, value)\n#define GET_TX_DESC_RTSRATE_8822B(txdesc) GET_TX_DESC_RTSRATE(txdesc)\n#define SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(txdesc, value)                      \\\n\tSET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)\n#define GET_TX_DESC_RTS_DATA_RTY_LMT_8822B(txdesc)                             \\\n\tGET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)\n#define SET_TX_DESC_RTY_LMT_EN_8822B(txdesc, value)                            \\\n\tSET_TX_DESC_RTY_LMT_EN(txdesc, value)\n#define GET_TX_DESC_RTY_LMT_EN_8822B(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)\n#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(txdesc, value)                   \\\n\tSET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(txdesc)                          \\\n\tGET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)\n#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(txdesc, value)                  \\\n\tSET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(txdesc)                         \\\n\tGET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)\n#define SET_TX_DESC_TRY_RATE_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_TRY_RATE(txdesc, value)\n#define GET_TX_DESC_TRY_RATE_8822B(txdesc) GET_TX_DESC_TRY_RATE(txdesc)\n#define SET_TX_DESC_DATARATE_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_DATARATE(txdesc, value)\n#define GET_TX_DESC_DATARATE_8822B(txdesc) GET_TX_DESC_DATARATE(txdesc)\n\n/*TXDESC_WORD5*/\n\n#define SET_TX_DESC_POLLUTED_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_POLLUTED(txdesc, value)\n#define GET_TX_DESC_POLLUTED_8822B(txdesc) GET_TX_DESC_POLLUTED(txdesc)\n#define SET_TX_DESC_TXPWR_OFSET_8822B(txdesc, value)                           \\\n\tSET_TX_DESC_TXPWR_OFSET(txdesc, value)\n#define GET_TX_DESC_TXPWR_OFSET_8822B(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc)\n#define SET_TX_DESC_TX_ANT_8822B(txdesc, value)                                \\\n\tSET_TX_DESC_TX_ANT(txdesc, value)\n#define GET_TX_DESC_TX_ANT_8822B(txdesc) GET_TX_DESC_TX_ANT(txdesc)\n#define SET_TX_DESC_PORT_ID_8822B(txdesc, value)                               \\\n\tSET_TX_DESC_PORT_ID(txdesc, value)\n#define GET_TX_DESC_PORT_ID_8822B(txdesc) GET_TX_DESC_PORT_ID(txdesc)\n#define SET_TX_DESC_MULTIPLE_PORT_8822B(txdesc, value)                         \\\n\tSET_TX_DESC_MULTIPLE_PORT(txdesc, value)\n#define GET_TX_DESC_MULTIPLE_PORT_8822B(txdesc)                                \\\n\tGET_TX_DESC_MULTIPLE_PORT(txdesc)\n#define SET_TX_DESC_SIGNALING_TAPKT_EN_8822B(txdesc, value)                    \\\n\tSET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)\n#define GET_TX_DESC_SIGNALING_TAPKT_EN_8822B(txdesc)                           \\\n\tGET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)\n#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8822B(txdesc, value)                   \\\n\tSET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)\n#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8822B(txdesc)                          \\\n\tGET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)\n#define SET_TX_DESC_RTS_SHORT_8822B(txdesc, value)                             \\\n\tSET_TX_DESC_RTS_SHORT(txdesc, value)\n#define GET_TX_DESC_RTS_SHORT_8822B(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)\n#define SET_TX_DESC_VCS_STBC_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_VCS_STBC(txdesc, value)\n#define GET_TX_DESC_VCS_STBC_8822B(txdesc) GET_TX_DESC_VCS_STBC(txdesc)\n#define SET_TX_DESC_DATA_STBC_8822B(txdesc, value)                             \\\n\tSET_TX_DESC_DATA_STBC(txdesc, value)\n#define GET_TX_DESC_DATA_STBC_8822B(txdesc) GET_TX_DESC_DATA_STBC(txdesc)\n#define SET_TX_DESC_DATA_LDPC_8822B(txdesc, value)                             \\\n\tSET_TX_DESC_DATA_LDPC(txdesc, value)\n#define GET_TX_DESC_DATA_LDPC_8822B(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)\n#define SET_TX_DESC_DATA_BW_8822B(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_BW(txdesc, value)\n#define GET_TX_DESC_DATA_BW_8822B(txdesc) GET_TX_DESC_DATA_BW(txdesc)\n#define SET_TX_DESC_DATA_SHORT_8822B(txdesc, value)                            \\\n\tSET_TX_DESC_DATA_SHORT(txdesc, value)\n#define GET_TX_DESC_DATA_SHORT_8822B(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)\n#define SET_TX_DESC_DATA_SC_8822B(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_SC(txdesc, value)\n#define GET_TX_DESC_DATA_SC_8822B(txdesc) GET_TX_DESC_DATA_SC(txdesc)\n\n/*TXDESC_WORD6*/\n\n#define SET_TX_DESC_ANTSEL_D_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_D(txdesc, value)\n#define GET_TX_DESC_ANTSEL_D_8822B(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)\n#define SET_TX_DESC_ANT_MAPD_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPD(txdesc, value)\n#define GET_TX_DESC_ANT_MAPD_8822B(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)\n#define SET_TX_DESC_ANT_MAPC_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPC(txdesc, value)\n#define GET_TX_DESC_ANT_MAPC_8822B(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)\n#define SET_TX_DESC_ANT_MAPB_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPB(txdesc, value)\n#define GET_TX_DESC_ANT_MAPB_8822B(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)\n#define SET_TX_DESC_ANT_MAPA_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPA(txdesc, value)\n#define GET_TX_DESC_ANT_MAPA_8822B(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)\n#define SET_TX_DESC_ANTSEL_C_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_C(txdesc, value)\n#define GET_TX_DESC_ANTSEL_C_8822B(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)\n#define SET_TX_DESC_ANTSEL_B_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_B(txdesc, value)\n#define GET_TX_DESC_ANTSEL_B_8822B(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)\n#define SET_TX_DESC_ANTSEL_A_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_A(txdesc, value)\n#define GET_TX_DESC_ANTSEL_A_8822B(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)\n#define SET_TX_DESC_MBSSID_8822B(txdesc, value)                                \\\n\tSET_TX_DESC_MBSSID(txdesc, value)\n#define GET_TX_DESC_MBSSID_8822B(txdesc) GET_TX_DESC_MBSSID(txdesc)\n#define SET_TX_DESC_SW_DEFINE_8822B(txdesc, value)                             \\\n\tSET_TX_DESC_SW_DEFINE(txdesc, value)\n#define GET_TX_DESC_SW_DEFINE_8822B(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)\n\n/*TXDESC_WORD7*/\n\n#define SET_TX_DESC_DMA_TXAGG_NUM_8822B(txdesc, value)                         \\\n\tSET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)\n#define GET_TX_DESC_DMA_TXAGG_NUM_8822B(txdesc)                                \\\n\tGET_TX_DESC_DMA_TXAGG_NUM(txdesc)\n#define SET_TX_DESC_FINAL_DATA_RATE_8822B(txdesc, value)                       \\\n\tSET_TX_DESC_FINAL_DATA_RATE(txdesc, value)\n#define GET_TX_DESC_FINAL_DATA_RATE_8822B(txdesc)                              \\\n\tGET_TX_DESC_FINAL_DATA_RATE(txdesc)\n#define SET_TX_DESC_NTX_MAP_8822B(txdesc, value)                               \\\n\tSET_TX_DESC_NTX_MAP(txdesc, value)\n#define GET_TX_DESC_NTX_MAP_8822B(txdesc) GET_TX_DESC_NTX_MAP(txdesc)\n#define SET_TX_DESC_TX_BUFF_SIZE_8822B(txdesc, value)                          \\\n\tSET_TX_DESC_TX_BUFF_SIZE(txdesc, value)\n#define GET_TX_DESC_TX_BUFF_SIZE_8822B(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)\n#define SET_TX_DESC_TXDESC_CHECKSUM_8822B(txdesc, value)                       \\\n\tSET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)\n#define GET_TX_DESC_TXDESC_CHECKSUM_8822B(txdesc)                              \\\n\tGET_TX_DESC_TXDESC_CHECKSUM(txdesc)\n#define SET_TX_DESC_TIMESTAMP_8822B(txdesc, value)                             \\\n\tSET_TX_DESC_TIMESTAMP(txdesc, value)\n#define GET_TX_DESC_TIMESTAMP_8822B(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)\n\n/*TXDESC_WORD8*/\n\n#define SET_TX_DESC_TXWIFI_CP_8822B(txdesc, value)                             \\\n\tSET_TX_DESC_TXWIFI_CP(txdesc, value)\n#define GET_TX_DESC_TXWIFI_CP_8822B(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)\n#define SET_TX_DESC_MAC_CP_8822B(txdesc, value)                                \\\n\tSET_TX_DESC_MAC_CP(txdesc, value)\n#define GET_TX_DESC_MAC_CP_8822B(txdesc) GET_TX_DESC_MAC_CP(txdesc)\n#define SET_TX_DESC_STW_PKTRE_DIS_8822B(txdesc, value)                         \\\n\tSET_TX_DESC_STW_PKTRE_DIS(txdesc, value)\n#define GET_TX_DESC_STW_PKTRE_DIS_8822B(txdesc)                                \\\n\tGET_TX_DESC_STW_PKTRE_DIS(txdesc)\n#define SET_TX_DESC_STW_RB_DIS_8822B(txdesc, value)                            \\\n\tSET_TX_DESC_STW_RB_DIS(txdesc, value)\n#define GET_TX_DESC_STW_RB_DIS_8822B(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)\n#define SET_TX_DESC_STW_RATE_DIS_8822B(txdesc, value)                          \\\n\tSET_TX_DESC_STW_RATE_DIS(txdesc, value)\n#define GET_TX_DESC_STW_RATE_DIS_8822B(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)\n#define SET_TX_DESC_STW_ANT_DIS_8822B(txdesc, value)                           \\\n\tSET_TX_DESC_STW_ANT_DIS(txdesc, value)\n#define GET_TX_DESC_STW_ANT_DIS_8822B(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)\n#define SET_TX_DESC_STW_EN_8822B(txdesc, value)                                \\\n\tSET_TX_DESC_STW_EN(txdesc, value)\n#define GET_TX_DESC_STW_EN_8822B(txdesc) GET_TX_DESC_STW_EN(txdesc)\n#define SET_TX_DESC_SMH_EN_8822B(txdesc, value)                                \\\n\tSET_TX_DESC_SMH_EN(txdesc, value)\n#define GET_TX_DESC_SMH_EN_8822B(txdesc) GET_TX_DESC_SMH_EN(txdesc)\n#define SET_TX_DESC_TAILPAGE_L_8822B(txdesc, value)                            \\\n\tSET_TX_DESC_TAILPAGE_L(txdesc, value)\n#define GET_TX_DESC_TAILPAGE_L_8822B(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)\n#define SET_TX_DESC_SDIO_DMASEQ_8822B(txdesc, value)                           \\\n\tSET_TX_DESC_SDIO_DMASEQ(txdesc, value)\n#define GET_TX_DESC_SDIO_DMASEQ_8822B(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)\n#define SET_TX_DESC_NEXTHEADPAGE_L_8822B(txdesc, value)                        \\\n\tSET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)\n#define GET_TX_DESC_NEXTHEADPAGE_L_8822B(txdesc)                               \\\n\tGET_TX_DESC_NEXTHEADPAGE_L(txdesc)\n#define SET_TX_DESC_EN_HWSEQ_8822B(txdesc, value)                              \\\n\tSET_TX_DESC_EN_HWSEQ(txdesc, value)\n#define GET_TX_DESC_EN_HWSEQ_8822B(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)\n#define SET_TX_DESC_EN_HWEXSEQ_8822B(txdesc, value)                            \\\n\tSET_TX_DESC_EN_HWEXSEQ(txdesc, value)\n#define GET_TX_DESC_EN_HWEXSEQ_8822B(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)\n#define SET_TX_DESC_DATA_RC_8822B(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_RC(txdesc, value)\n#define GET_TX_DESC_DATA_RC_8822B(txdesc) GET_TX_DESC_DATA_RC(txdesc)\n#define SET_TX_DESC_BAR_RTY_TH_8822B(txdesc, value)                            \\\n\tSET_TX_DESC_BAR_RTY_TH(txdesc, value)\n#define GET_TX_DESC_BAR_RTY_TH_8822B(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)\n#define SET_TX_DESC_RTS_RC_8822B(txdesc, value)                                \\\n\tSET_TX_DESC_RTS_RC(txdesc, value)\n#define GET_TX_DESC_RTS_RC_8822B(txdesc) GET_TX_DESC_RTS_RC(txdesc)\n\n/*TXDESC_WORD9*/\n\n#define SET_TX_DESC_TAILPAGE_H_8822B(txdesc, value)                            \\\n\tSET_TX_DESC_TAILPAGE_H(txdesc, value)\n#define GET_TX_DESC_TAILPAGE_H_8822B(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)\n#define SET_TX_DESC_NEXTHEADPAGE_H_8822B(txdesc, value)                        \\\n\tSET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)\n#define GET_TX_DESC_NEXTHEADPAGE_H_8822B(txdesc)                               \\\n\tGET_TX_DESC_NEXTHEADPAGE_H(txdesc)\n#define SET_TX_DESC_SW_SEQ_8822B(txdesc, value)                                \\\n\tSET_TX_DESC_SW_SEQ(txdesc, value)\n#define GET_TX_DESC_SW_SEQ_8822B(txdesc) GET_TX_DESC_SW_SEQ(txdesc)\n#define SET_TX_DESC_TXBF_PATH_8822B(txdesc, value)                             \\\n\tSET_TX_DESC_TXBF_PATH(txdesc, value)\n#define GET_TX_DESC_TXBF_PATH_8822B(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)\n#define SET_TX_DESC_PADDING_LEN_8822B(txdesc, value)                           \\\n\tSET_TX_DESC_PADDING_LEN(txdesc, value)\n#define GET_TX_DESC_PADDING_LEN_8822B(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)\n#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(txdesc, value)                   \\\n\tSET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)\n#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(txdesc)                          \\\n\tGET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)\n\n/*WORD10*/\n\n#define SET_TX_DESC_MU_DATARATE_8822B(txdesc, value)                           \\\n\tSET_TX_DESC_MU_DATARATE(txdesc, value)\n#define GET_TX_DESC_MU_DATARATE_8822B(txdesc) GET_TX_DESC_MU_DATARATE(txdesc)\n#define SET_TX_DESC_MU_RC_8822B(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value)\n#define GET_TX_DESC_MU_RC_8822B(txdesc) GET_TX_DESC_MU_RC(txdesc)\n#define SET_TX_DESC_SND_PKT_SEL_8822B(txdesc, value)                           \\\n\tSET_TX_DESC_SND_PKT_SEL(txdesc, value)\n#define GET_TX_DESC_SND_PKT_SEL_8822B(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc)\n\n#endif\n\n#if (HALMAC_8197F_SUPPORT)\n\n/*TXDESC_WORD0*/\n\n#define SET_TX_DESC_DISQSELSEQ_8197F(txdesc, value)                            \\\n\tSET_TX_DESC_DISQSELSEQ(txdesc, value)\n#define GET_TX_DESC_DISQSELSEQ_8197F(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)\n#define SET_TX_DESC_GF_8197F(txdesc, value) SET_TX_DESC_GF(txdesc, value)\n#define GET_TX_DESC_GF_8197F(txdesc) GET_TX_DESC_GF(txdesc)\n#define SET_TX_DESC_NO_ACM_8197F(txdesc, value)                                \\\n\tSET_TX_DESC_NO_ACM(txdesc, value)\n#define GET_TX_DESC_NO_ACM_8197F(txdesc) GET_TX_DESC_NO_ACM(txdesc)\n#define SET_TX_DESC_BCNPKT_TSF_CTRL_8197F(txdesc, value)                       \\\n\tSET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)\n#define GET_TX_DESC_BCNPKT_TSF_CTRL_8197F(txdesc)                              \\\n\tGET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)\n#define SET_TX_DESC_AMSDU_PAD_EN_8197F(txdesc, value)                          \\\n\tSET_TX_DESC_AMSDU_PAD_EN(txdesc, value)\n#define GET_TX_DESC_AMSDU_PAD_EN_8197F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)\n#define SET_TX_DESC_LS_8197F(txdesc, value) SET_TX_DESC_LS(txdesc, value)\n#define GET_TX_DESC_LS_8197F(txdesc) GET_TX_DESC_LS(txdesc)\n#define SET_TX_DESC_HTC_8197F(txdesc, value) SET_TX_DESC_HTC(txdesc, value)\n#define GET_TX_DESC_HTC_8197F(txdesc) GET_TX_DESC_HTC(txdesc)\n#define SET_TX_DESC_BMC_8197F(txdesc, value) SET_TX_DESC_BMC(txdesc, value)\n#define GET_TX_DESC_BMC_8197F(txdesc) GET_TX_DESC_BMC(txdesc)\n#define SET_TX_DESC_OFFSET_8197F(txdesc, value)                                \\\n\tSET_TX_DESC_OFFSET(txdesc, value)\n#define GET_TX_DESC_OFFSET_8197F(txdesc) GET_TX_DESC_OFFSET(txdesc)\n#define SET_TX_DESC_TXPKTSIZE_8197F(txdesc, value)                             \\\n\tSET_TX_DESC_TXPKTSIZE(txdesc, value)\n#define GET_TX_DESC_TXPKTSIZE_8197F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)\n\n/*WORD1*/\n\n#define SET_TX_DESC_MOREDATA_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_MOREDATA(txdesc, value)\n#define GET_TX_DESC_MOREDATA_8197F(txdesc) GET_TX_DESC_MOREDATA(txdesc)\n#define SET_TX_DESC_PKT_OFFSET_8197F(txdesc, value)                            \\\n\tSET_TX_DESC_PKT_OFFSET(txdesc, value)\n#define GET_TX_DESC_PKT_OFFSET_8197F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)\n#define SET_TX_DESC_SEC_TYPE_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_SEC_TYPE(txdesc, value)\n#define GET_TX_DESC_SEC_TYPE_8197F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)\n#define SET_TX_DESC_EN_DESC_ID_8197F(txdesc, value)                            \\\n\tSET_TX_DESC_EN_DESC_ID(txdesc, value)\n#define GET_TX_DESC_EN_DESC_ID_8197F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)\n#define SET_TX_DESC_RATE_ID_8197F(txdesc, value)                               \\\n\tSET_TX_DESC_RATE_ID(txdesc, value)\n#define GET_TX_DESC_RATE_ID_8197F(txdesc) GET_TX_DESC_RATE_ID(txdesc)\n#define SET_TX_DESC_PIFS_8197F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)\n#define GET_TX_DESC_PIFS_8197F(txdesc) GET_TX_DESC_PIFS(txdesc)\n#define SET_TX_DESC_LSIG_TXOP_EN_8197F(txdesc, value)                          \\\n\tSET_TX_DESC_LSIG_TXOP_EN(txdesc, value)\n#define GET_TX_DESC_LSIG_TXOP_EN_8197F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)\n#define SET_TX_DESC_RD_NAV_EXT_8197F(txdesc, value)                            \\\n\tSET_TX_DESC_RD_NAV_EXT(txdesc, value)\n#define GET_TX_DESC_RD_NAV_EXT_8197F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)\n#define SET_TX_DESC_QSEL_8197F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)\n#define GET_TX_DESC_QSEL_8197F(txdesc) GET_TX_DESC_QSEL(txdesc)\n#define SET_TX_DESC_MACID_8197F(txdesc, value) SET_TX_DESC_MACID(txdesc, value)\n#define GET_TX_DESC_MACID_8197F(txdesc) GET_TX_DESC_MACID(txdesc)\n\n/*TXDESC_WORD2*/\n\n#define SET_TX_DESC_HW_AES_IV_8197F(txdesc, value)                             \\\n\tSET_TX_DESC_HW_AES_IV(txdesc, value)\n#define GET_TX_DESC_HW_AES_IV_8197F(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)\n#define SET_TX_DESC_FTM_EN_8197F(txdesc, value)                                \\\n\tSET_TX_DESC_FTM_EN(txdesc, value)\n#define GET_TX_DESC_FTM_EN_8197F(txdesc) GET_TX_DESC_FTM_EN(txdesc)\n#define SET_TX_DESC_G_ID_8197F(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)\n#define GET_TX_DESC_G_ID_8197F(txdesc) GET_TX_DESC_G_ID(txdesc)\n#define SET_TX_DESC_BT_NULL_8197F(txdesc, value)                               \\\n\tSET_TX_DESC_BT_NULL(txdesc, value)\n#define GET_TX_DESC_BT_NULL_8197F(txdesc) GET_TX_DESC_BT_NULL(txdesc)\n#define SET_TX_DESC_AMPDU_DENSITY_8197F(txdesc, value)                         \\\n\tSET_TX_DESC_AMPDU_DENSITY(txdesc, value)\n#define GET_TX_DESC_AMPDU_DENSITY_8197F(txdesc)                                \\\n\tGET_TX_DESC_AMPDU_DENSITY(txdesc)\n#define SET_TX_DESC_SPE_RPT_8197F(txdesc, value)                               \\\n\tSET_TX_DESC_SPE_RPT(txdesc, value)\n#define GET_TX_DESC_SPE_RPT_8197F(txdesc) GET_TX_DESC_SPE_RPT(txdesc)\n#define SET_TX_DESC_RAW_8197F(txdesc, value) SET_TX_DESC_RAW(txdesc, value)\n#define GET_TX_DESC_RAW_8197F(txdesc) GET_TX_DESC_RAW(txdesc)\n#define SET_TX_DESC_MOREFRAG_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_MOREFRAG(txdesc, value)\n#define GET_TX_DESC_MOREFRAG_8197F(txdesc) GET_TX_DESC_MOREFRAG(txdesc)\n#define SET_TX_DESC_BK_8197F(txdesc, value) SET_TX_DESC_BK(txdesc, value)\n#define GET_TX_DESC_BK_8197F(txdesc) GET_TX_DESC_BK(txdesc)\n#define SET_TX_DESC_NULL_1_8197F(txdesc, value)                                \\\n\tSET_TX_DESC_NULL_1(txdesc, value)\n#define GET_TX_DESC_NULL_1_8197F(txdesc) GET_TX_DESC_NULL_1(txdesc)\n#define SET_TX_DESC_NULL_0_8197F(txdesc, value)                                \\\n\tSET_TX_DESC_NULL_0(txdesc, value)\n#define GET_TX_DESC_NULL_0_8197F(txdesc) GET_TX_DESC_NULL_0(txdesc)\n#define SET_TX_DESC_RDG_EN_8197F(txdesc, value)                                \\\n\tSET_TX_DESC_RDG_EN(txdesc, value)\n#define GET_TX_DESC_RDG_EN_8197F(txdesc) GET_TX_DESC_RDG_EN(txdesc)\n#define SET_TX_DESC_AGG_EN_8197F(txdesc, value)                                \\\n\tSET_TX_DESC_AGG_EN(txdesc, value)\n#define GET_TX_DESC_AGG_EN_8197F(txdesc) GET_TX_DESC_AGG_EN(txdesc)\n#define SET_TX_DESC_CCA_RTS_8197F(txdesc, value)                               \\\n\tSET_TX_DESC_CCA_RTS(txdesc, value)\n#define GET_TX_DESC_CCA_RTS_8197F(txdesc) GET_TX_DESC_CCA_RTS(txdesc)\n#define SET_TX_DESC_TRI_FRAME_8197F(txdesc, value)                             \\\n\tSET_TX_DESC_TRI_FRAME(txdesc, value)\n#define GET_TX_DESC_TRI_FRAME_8197F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)\n#define SET_TX_DESC_P_AID_8197F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)\n#define GET_TX_DESC_P_AID_8197F(txdesc) GET_TX_DESC_P_AID(txdesc)\n\n/*TXDESC_WORD3*/\n\n#define SET_TX_DESC_AMPDU_MAX_TIME_8197F(txdesc, value)                        \\\n\tSET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)\n#define GET_TX_DESC_AMPDU_MAX_TIME_8197F(txdesc)                               \\\n\tGET_TX_DESC_AMPDU_MAX_TIME(txdesc)\n#define SET_TX_DESC_NDPA_8197F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)\n#define GET_TX_DESC_NDPA_8197F(txdesc) GET_TX_DESC_NDPA(txdesc)\n#define SET_TX_DESC_MAX_AGG_NUM_8197F(txdesc, value)                           \\\n\tSET_TX_DESC_MAX_AGG_NUM(txdesc, value)\n#define GET_TX_DESC_MAX_AGG_NUM_8197F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)\n#define SET_TX_DESC_USE_MAX_TIME_EN_8197F(txdesc, value)                       \\\n\tSET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)\n#define GET_TX_DESC_USE_MAX_TIME_EN_8197F(txdesc)                              \\\n\tGET_TX_DESC_USE_MAX_TIME_EN(txdesc)\n#define SET_TX_DESC_NAVUSEHDR_8197F(txdesc, value)                             \\\n\tSET_TX_DESC_NAVUSEHDR(txdesc, value)\n#define GET_TX_DESC_NAVUSEHDR_8197F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)\n#define SET_TX_DESC_CHK_EN_8197F(txdesc, value)                                \\\n\tSET_TX_DESC_CHK_EN(txdesc, value)\n#define GET_TX_DESC_CHK_EN_8197F(txdesc) GET_TX_DESC_CHK_EN(txdesc)\n#define SET_TX_DESC_HW_RTS_EN_8197F(txdesc, value)                             \\\n\tSET_TX_DESC_HW_RTS_EN(txdesc, value)\n#define GET_TX_DESC_HW_RTS_EN_8197F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)\n#define SET_TX_DESC_RTSEN_8197F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)\n#define GET_TX_DESC_RTSEN_8197F(txdesc) GET_TX_DESC_RTSEN(txdesc)\n#define SET_TX_DESC_CTS2SELF_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_CTS2SELF(txdesc, value)\n#define GET_TX_DESC_CTS2SELF_8197F(txdesc) GET_TX_DESC_CTS2SELF(txdesc)\n#define SET_TX_DESC_DISDATAFB_8197F(txdesc, value)                             \\\n\tSET_TX_DESC_DISDATAFB(txdesc, value)\n#define GET_TX_DESC_DISDATAFB_8197F(txdesc) GET_TX_DESC_DISDATAFB(txdesc)\n#define SET_TX_DESC_DISRTSFB_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_DISRTSFB(txdesc, value)\n#define GET_TX_DESC_DISRTSFB_8197F(txdesc) GET_TX_DESC_DISRTSFB(txdesc)\n#define SET_TX_DESC_USE_RATE_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_USE_RATE(txdesc, value)\n#define GET_TX_DESC_USE_RATE_8197F(txdesc) GET_TX_DESC_USE_RATE(txdesc)\n#define SET_TX_DESC_HW_SSN_SEL_8197F(txdesc, value)                            \\\n\tSET_TX_DESC_HW_SSN_SEL(txdesc, value)\n#define GET_TX_DESC_HW_SSN_SEL_8197F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)\n#define SET_TX_DESC_WHEADER_LEN_8197F(txdesc, value)                           \\\n\tSET_TX_DESC_WHEADER_LEN(txdesc, value)\n#define GET_TX_DESC_WHEADER_LEN_8197F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)\n\n/*TXDESC_WORD4*/\n\n#define SET_TX_DESC_PCTS_MASK_IDX_8197F(txdesc, value)                         \\\n\tSET_TX_DESC_PCTS_MASK_IDX(txdesc, value)\n#define GET_TX_DESC_PCTS_MASK_IDX_8197F(txdesc)                                \\\n\tGET_TX_DESC_PCTS_MASK_IDX(txdesc)\n#define SET_TX_DESC_PCTS_EN_8197F(txdesc, value)                               \\\n\tSET_TX_DESC_PCTS_EN(txdesc, value)\n#define GET_TX_DESC_PCTS_EN_8197F(txdesc) GET_TX_DESC_PCTS_EN(txdesc)\n#define SET_TX_DESC_RTSRATE_8197F(txdesc, value)                               \\\n\tSET_TX_DESC_RTSRATE(txdesc, value)\n#define GET_TX_DESC_RTSRATE_8197F(txdesc) GET_TX_DESC_RTSRATE(txdesc)\n#define SET_TX_DESC_RTS_DATA_RTY_LMT_8197F(txdesc, value)                      \\\n\tSET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)\n#define GET_TX_DESC_RTS_DATA_RTY_LMT_8197F(txdesc)                             \\\n\tGET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)\n#define SET_TX_DESC_RTY_LMT_EN_8197F(txdesc, value)                            \\\n\tSET_TX_DESC_RTY_LMT_EN(txdesc, value)\n#define GET_TX_DESC_RTY_LMT_EN_8197F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)\n#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8197F(txdesc, value)                   \\\n\tSET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8197F(txdesc)                          \\\n\tGET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)\n#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8197F(txdesc, value)                  \\\n\tSET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8197F(txdesc)                         \\\n\tGET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)\n#define SET_TX_DESC_TRY_RATE_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_TRY_RATE(txdesc, value)\n#define GET_TX_DESC_TRY_RATE_8197F(txdesc) GET_TX_DESC_TRY_RATE(txdesc)\n#define SET_TX_DESC_DATARATE_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_DATARATE(txdesc, value)\n#define GET_TX_DESC_DATARATE_8197F(txdesc) GET_TX_DESC_DATARATE(txdesc)\n\n/*TXDESC_WORD5*/\n\n#define SET_TX_DESC_POLLUTED_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_POLLUTED(txdesc, value)\n#define GET_TX_DESC_POLLUTED_8197F(txdesc) GET_TX_DESC_POLLUTED(txdesc)\n#define SET_TX_DESC_TXPWR_OFSET_8197F(txdesc, value)                           \\\n\tSET_TX_DESC_TXPWR_OFSET(txdesc, value)\n#define GET_TX_DESC_TXPWR_OFSET_8197F(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc)\n#define SET_TX_DESC_TX_ANT_8197F(txdesc, value)                                \\\n\tSET_TX_DESC_TX_ANT(txdesc, value)\n#define GET_TX_DESC_TX_ANT_8197F(txdesc) GET_TX_DESC_TX_ANT(txdesc)\n#define SET_TX_DESC_PORT_ID_8197F(txdesc, value)                               \\\n\tSET_TX_DESC_PORT_ID(txdesc, value)\n#define GET_TX_DESC_PORT_ID_8197F(txdesc) GET_TX_DESC_PORT_ID(txdesc)\n#define SET_TX_DESC_MULTIPLE_PORT_8197F(txdesc, value)                         \\\n\tSET_TX_DESC_MULTIPLE_PORT(txdesc, value)\n#define GET_TX_DESC_MULTIPLE_PORT_8197F(txdesc)                                \\\n\tGET_TX_DESC_MULTIPLE_PORT(txdesc)\n#define SET_TX_DESC_SIGNALING_TAPKT_EN_8197F(txdesc, value)                    \\\n\tSET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)\n#define GET_TX_DESC_SIGNALING_TAPKT_EN_8197F(txdesc)                           \\\n\tGET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)\n#define SET_TX_DESC_RTS_SC_8197F(txdesc, value)                                \\\n\tSET_TX_DESC_RTS_SC(txdesc, value)\n#define GET_TX_DESC_RTS_SC_8197F(txdesc) GET_TX_DESC_RTS_SC(txdesc)\n#define SET_TX_DESC_RTS_SHORT_8197F(txdesc, value)                             \\\n\tSET_TX_DESC_RTS_SHORT(txdesc, value)\n#define GET_TX_DESC_RTS_SHORT_8197F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)\n#define SET_TX_DESC_VCS_STBC_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_VCS_STBC(txdesc, value)\n#define GET_TX_DESC_VCS_STBC_8197F(txdesc) GET_TX_DESC_VCS_STBC(txdesc)\n#define SET_TX_DESC_DATA_STBC_8197F(txdesc, value)                             \\\n\tSET_TX_DESC_DATA_STBC(txdesc, value)\n#define GET_TX_DESC_DATA_STBC_8197F(txdesc) GET_TX_DESC_DATA_STBC(txdesc)\n#define SET_TX_DESC_DATA_LDPC_8197F(txdesc, value)                             \\\n\tSET_TX_DESC_DATA_LDPC(txdesc, value)\n#define GET_TX_DESC_DATA_LDPC_8197F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)\n#define SET_TX_DESC_DATA_BW_8197F(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_BW(txdesc, value)\n#define GET_TX_DESC_DATA_BW_8197F(txdesc) GET_TX_DESC_DATA_BW(txdesc)\n#define SET_TX_DESC_DATA_SHORT_8197F(txdesc, value)                            \\\n\tSET_TX_DESC_DATA_SHORT(txdesc, value)\n#define GET_TX_DESC_DATA_SHORT_8197F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)\n#define SET_TX_DESC_DATA_SC_8197F(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_SC(txdesc, value)\n#define GET_TX_DESC_DATA_SC_8197F(txdesc) GET_TX_DESC_DATA_SC(txdesc)\n\n/*TXDESC_WORD6*/\n\n#define SET_TX_DESC_ANTSEL_D_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_D(txdesc, value)\n#define GET_TX_DESC_ANTSEL_D_8197F(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)\n#define SET_TX_DESC_ANT_MAPD_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPD(txdesc, value)\n#define GET_TX_DESC_ANT_MAPD_8197F(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)\n#define SET_TX_DESC_ANT_MAPC_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPC(txdesc, value)\n#define GET_TX_DESC_ANT_MAPC_8197F(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)\n#define SET_TX_DESC_ANT_MAPB_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPB(txdesc, value)\n#define GET_TX_DESC_ANT_MAPB_8197F(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)\n#define SET_TX_DESC_ANT_MAPA_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPA(txdesc, value)\n#define GET_TX_DESC_ANT_MAPA_8197F(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)\n#define SET_TX_DESC_ANTSEL_C_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_C(txdesc, value)\n#define GET_TX_DESC_ANTSEL_C_8197F(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)\n#define SET_TX_DESC_ANTSEL_B_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_B(txdesc, value)\n#define GET_TX_DESC_ANTSEL_B_8197F(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)\n#define SET_TX_DESC_ANTSEL_A_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_A(txdesc, value)\n#define GET_TX_DESC_ANTSEL_A_8197F(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)\n#define SET_TX_DESC_MBSSID_8197F(txdesc, value)                                \\\n\tSET_TX_DESC_MBSSID(txdesc, value)\n#define GET_TX_DESC_MBSSID_8197F(txdesc) GET_TX_DESC_MBSSID(txdesc)\n#define SET_TX_DESC_SW_DEFINE_8197F(txdesc, value)                             \\\n\tSET_TX_DESC_SW_DEFINE(txdesc, value)\n#define GET_TX_DESC_SW_DEFINE_8197F(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)\n\n/*TXDESC_WORD7*/\n\n#define SET_TX_DESC_DMA_TXAGG_NUM_8197F(txdesc, value)                         \\\n\tSET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)\n#define GET_TX_DESC_DMA_TXAGG_NUM_8197F(txdesc)                                \\\n\tGET_TX_DESC_DMA_TXAGG_NUM(txdesc)\n#define SET_TX_DESC_FINAL_DATA_RATE_8197F(txdesc, value)                       \\\n\tSET_TX_DESC_FINAL_DATA_RATE(txdesc, value)\n#define GET_TX_DESC_FINAL_DATA_RATE_8197F(txdesc)                              \\\n\tGET_TX_DESC_FINAL_DATA_RATE(txdesc)\n#define SET_TX_DESC_NTX_MAP_8197F(txdesc, value)                               \\\n\tSET_TX_DESC_NTX_MAP(txdesc, value)\n#define GET_TX_DESC_NTX_MAP_8197F(txdesc) GET_TX_DESC_NTX_MAP(txdesc)\n#define SET_TX_DESC_TX_BUFF_SIZE_8197F(txdesc, value)                          \\\n\tSET_TX_DESC_TX_BUFF_SIZE(txdesc, value)\n#define GET_TX_DESC_TX_BUFF_SIZE_8197F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)\n#define SET_TX_DESC_TXDESC_CHECKSUM_8197F(txdesc, value)                       \\\n\tSET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)\n#define GET_TX_DESC_TXDESC_CHECKSUM_8197F(txdesc)                              \\\n\tGET_TX_DESC_TXDESC_CHECKSUM(txdesc)\n#define SET_TX_DESC_TIMESTAMP_8197F(txdesc, value)                             \\\n\tSET_TX_DESC_TIMESTAMP(txdesc, value)\n#define GET_TX_DESC_TIMESTAMP_8197F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)\n\n/*TXDESC_WORD8*/\n\n#define SET_TX_DESC_TXWIFI_CP_8197F(txdesc, value)                             \\\n\tSET_TX_DESC_TXWIFI_CP(txdesc, value)\n#define GET_TX_DESC_TXWIFI_CP_8197F(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)\n#define SET_TX_DESC_MAC_CP_8197F(txdesc, value)                                \\\n\tSET_TX_DESC_MAC_CP(txdesc, value)\n#define GET_TX_DESC_MAC_CP_8197F(txdesc) GET_TX_DESC_MAC_CP(txdesc)\n#define SET_TX_DESC_STW_PKTRE_DIS_8197F(txdesc, value)                         \\\n\tSET_TX_DESC_STW_PKTRE_DIS(txdesc, value)\n#define GET_TX_DESC_STW_PKTRE_DIS_8197F(txdesc)                                \\\n\tGET_TX_DESC_STW_PKTRE_DIS(txdesc)\n#define SET_TX_DESC_STW_RB_DIS_8197F(txdesc, value)                            \\\n\tSET_TX_DESC_STW_RB_DIS(txdesc, value)\n#define GET_TX_DESC_STW_RB_DIS_8197F(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)\n#define SET_TX_DESC_STW_RATE_DIS_8197F(txdesc, value)                          \\\n\tSET_TX_DESC_STW_RATE_DIS(txdesc, value)\n#define GET_TX_DESC_STW_RATE_DIS_8197F(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)\n#define SET_TX_DESC_STW_ANT_DIS_8197F(txdesc, value)                           \\\n\tSET_TX_DESC_STW_ANT_DIS(txdesc, value)\n#define GET_TX_DESC_STW_ANT_DIS_8197F(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)\n#define SET_TX_DESC_STW_EN_8197F(txdesc, value)                                \\\n\tSET_TX_DESC_STW_EN(txdesc, value)\n#define GET_TX_DESC_STW_EN_8197F(txdesc) GET_TX_DESC_STW_EN(txdesc)\n#define SET_TX_DESC_SMH_EN_8197F(txdesc, value)                                \\\n\tSET_TX_DESC_SMH_EN(txdesc, value)\n#define GET_TX_DESC_SMH_EN_8197F(txdesc) GET_TX_DESC_SMH_EN(txdesc)\n#define SET_TX_DESC_TAILPAGE_L_8197F(txdesc, value)                            \\\n\tSET_TX_DESC_TAILPAGE_L(txdesc, value)\n#define GET_TX_DESC_TAILPAGE_L_8197F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)\n#define SET_TX_DESC_SDIO_DMASEQ_8197F(txdesc, value)                           \\\n\tSET_TX_DESC_SDIO_DMASEQ(txdesc, value)\n#define GET_TX_DESC_SDIO_DMASEQ_8197F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)\n#define SET_TX_DESC_NEXTHEADPAGE_L_8197F(txdesc, value)                        \\\n\tSET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)\n#define GET_TX_DESC_NEXTHEADPAGE_L_8197F(txdesc)                               \\\n\tGET_TX_DESC_NEXTHEADPAGE_L(txdesc)\n#define SET_TX_DESC_EN_HWSEQ_8197F(txdesc, value)                              \\\n\tSET_TX_DESC_EN_HWSEQ(txdesc, value)\n#define GET_TX_DESC_EN_HWSEQ_8197F(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)\n#define SET_TX_DESC_EN_HWEXSEQ_8197F(txdesc, value)                            \\\n\tSET_TX_DESC_EN_HWEXSEQ(txdesc, value)\n#define GET_TX_DESC_EN_HWEXSEQ_8197F(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)\n#define SET_TX_DESC_DATA_RC_8197F(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_RC(txdesc, value)\n#define GET_TX_DESC_DATA_RC_8197F(txdesc) GET_TX_DESC_DATA_RC(txdesc)\n#define SET_TX_DESC_BAR_RTY_TH_8197F(txdesc, value)                            \\\n\tSET_TX_DESC_BAR_RTY_TH(txdesc, value)\n#define GET_TX_DESC_BAR_RTY_TH_8197F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)\n#define SET_TX_DESC_RTS_RC_8197F(txdesc, value)                                \\\n\tSET_TX_DESC_RTS_RC(txdesc, value)\n#define GET_TX_DESC_RTS_RC_8197F(txdesc) GET_TX_DESC_RTS_RC(txdesc)\n\n/*TXDESC_WORD9*/\n\n#define SET_TX_DESC_TAILPAGE_H_8197F(txdesc, value)                            \\\n\tSET_TX_DESC_TAILPAGE_H(txdesc, value)\n#define GET_TX_DESC_TAILPAGE_H_8197F(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)\n#define SET_TX_DESC_NEXTHEADPAGE_H_8197F(txdesc, value)                        \\\n\tSET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)\n#define GET_TX_DESC_NEXTHEADPAGE_H_8197F(txdesc)                               \\\n\tGET_TX_DESC_NEXTHEADPAGE_H(txdesc)\n#define SET_TX_DESC_SW_SEQ_8197F(txdesc, value)                                \\\n\tSET_TX_DESC_SW_SEQ(txdesc, value)\n#define GET_TX_DESC_SW_SEQ_8197F(txdesc) GET_TX_DESC_SW_SEQ(txdesc)\n#define SET_TX_DESC_TXBF_PATH_8197F(txdesc, value)                             \\\n\tSET_TX_DESC_TXBF_PATH(txdesc, value)\n#define GET_TX_DESC_TXBF_PATH_8197F(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)\n#define SET_TX_DESC_PADDING_LEN_8197F(txdesc, value)                           \\\n\tSET_TX_DESC_PADDING_LEN(txdesc, value)\n#define GET_TX_DESC_PADDING_LEN_8197F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)\n#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8197F(txdesc, value)                   \\\n\tSET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)\n#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8197F(txdesc)                          \\\n\tGET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)\n\n/*WORD10*/\n\n#endif\n\n#if (HALMAC_8821C_SUPPORT)\n\n/*TXDESC_WORD0*/\n\n#define SET_TX_DESC_DISQSELSEQ_8821C(txdesc, value)                            \\\n\tSET_TX_DESC_DISQSELSEQ(txdesc, value)\n#define GET_TX_DESC_DISQSELSEQ_8821C(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)\n#define SET_TX_DESC_GF_8821C(txdesc, value) SET_TX_DESC_GF(txdesc, value)\n#define GET_TX_DESC_GF_8821C(txdesc) GET_TX_DESC_GF(txdesc)\n#define SET_TX_DESC_NO_ACM_8821C(txdesc, value)                                \\\n\tSET_TX_DESC_NO_ACM(txdesc, value)\n#define GET_TX_DESC_NO_ACM_8821C(txdesc) GET_TX_DESC_NO_ACM(txdesc)\n#define SET_TX_DESC_BCNPKT_TSF_CTRL_8821C(txdesc, value)                       \\\n\tSET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)\n#define GET_TX_DESC_BCNPKT_TSF_CTRL_8821C(txdesc)                              \\\n\tGET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)\n#define SET_TX_DESC_AMSDU_PAD_EN_8821C(txdesc, value)                          \\\n\tSET_TX_DESC_AMSDU_PAD_EN(txdesc, value)\n#define GET_TX_DESC_AMSDU_PAD_EN_8821C(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)\n#define SET_TX_DESC_LS_8821C(txdesc, value) SET_TX_DESC_LS(txdesc, value)\n#define GET_TX_DESC_LS_8821C(txdesc) GET_TX_DESC_LS(txdesc)\n#define SET_TX_DESC_HTC_8821C(txdesc, value) SET_TX_DESC_HTC(txdesc, value)\n#define GET_TX_DESC_HTC_8821C(txdesc) GET_TX_DESC_HTC(txdesc)\n#define SET_TX_DESC_BMC_8821C(txdesc, value) SET_TX_DESC_BMC(txdesc, value)\n#define GET_TX_DESC_BMC_8821C(txdesc) GET_TX_DESC_BMC(txdesc)\n#define SET_TX_DESC_OFFSET_8821C(txdesc, value)                                \\\n\tSET_TX_DESC_OFFSET(txdesc, value)\n#define GET_TX_DESC_OFFSET_8821C(txdesc) GET_TX_DESC_OFFSET(txdesc)\n#define SET_TX_DESC_TXPKTSIZE_8821C(txdesc, value)                             \\\n\tSET_TX_DESC_TXPKTSIZE(txdesc, value)\n#define GET_TX_DESC_TXPKTSIZE_8821C(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)\n\n/*WORD1*/\n\n#define SET_TX_DESC_MOREDATA_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_MOREDATA(txdesc, value)\n#define GET_TX_DESC_MOREDATA_8821C(txdesc) GET_TX_DESC_MOREDATA(txdesc)\n#define SET_TX_DESC_PKT_OFFSET_8821C(txdesc, value)                            \\\n\tSET_TX_DESC_PKT_OFFSET(txdesc, value)\n#define GET_TX_DESC_PKT_OFFSET_8821C(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)\n#define SET_TX_DESC_SEC_TYPE_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_SEC_TYPE(txdesc, value)\n#define GET_TX_DESC_SEC_TYPE_8821C(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)\n#define SET_TX_DESC_EN_DESC_ID_8821C(txdesc, value)                            \\\n\tSET_TX_DESC_EN_DESC_ID(txdesc, value)\n#define GET_TX_DESC_EN_DESC_ID_8821C(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)\n#define SET_TX_DESC_RATE_ID_8821C(txdesc, value)                               \\\n\tSET_TX_DESC_RATE_ID(txdesc, value)\n#define GET_TX_DESC_RATE_ID_8821C(txdesc) GET_TX_DESC_RATE_ID(txdesc)\n#define SET_TX_DESC_PIFS_8821C(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)\n#define GET_TX_DESC_PIFS_8821C(txdesc) GET_TX_DESC_PIFS(txdesc)\n#define SET_TX_DESC_LSIG_TXOP_EN_8821C(txdesc, value)                          \\\n\tSET_TX_DESC_LSIG_TXOP_EN(txdesc, value)\n#define GET_TX_DESC_LSIG_TXOP_EN_8821C(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)\n#define SET_TX_DESC_RD_NAV_EXT_8821C(txdesc, value)                            \\\n\tSET_TX_DESC_RD_NAV_EXT(txdesc, value)\n#define GET_TX_DESC_RD_NAV_EXT_8821C(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)\n#define SET_TX_DESC_QSEL_8821C(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)\n#define GET_TX_DESC_QSEL_8821C(txdesc) GET_TX_DESC_QSEL(txdesc)\n#define SET_TX_DESC_MACID_8821C(txdesc, value) SET_TX_DESC_MACID(txdesc, value)\n#define GET_TX_DESC_MACID_8821C(txdesc) GET_TX_DESC_MACID(txdesc)\n\n/*TXDESC_WORD2*/\n\n#define SET_TX_DESC_HW_AES_IV_8821C(txdesc, value)                             \\\n\tSET_TX_DESC_HW_AES_IV(txdesc, value)\n#define GET_TX_DESC_HW_AES_IV_8821C(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)\n#define SET_TX_DESC_FTM_EN_8821C(txdesc, value)                                \\\n\tSET_TX_DESC_FTM_EN(txdesc, value)\n#define GET_TX_DESC_FTM_EN_8821C(txdesc) GET_TX_DESC_FTM_EN(txdesc)\n#define SET_TX_DESC_G_ID_8821C(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)\n#define GET_TX_DESC_G_ID_8821C(txdesc) GET_TX_DESC_G_ID(txdesc)\n#define SET_TX_DESC_BT_NULL_8821C(txdesc, value)                               \\\n\tSET_TX_DESC_BT_NULL(txdesc, value)\n#define GET_TX_DESC_BT_NULL_8821C(txdesc) GET_TX_DESC_BT_NULL(txdesc)\n#define SET_TX_DESC_AMPDU_DENSITY_8821C(txdesc, value)                         \\\n\tSET_TX_DESC_AMPDU_DENSITY(txdesc, value)\n#define GET_TX_DESC_AMPDU_DENSITY_8821C(txdesc)                                \\\n\tGET_TX_DESC_AMPDU_DENSITY(txdesc)\n#define SET_TX_DESC_SPE_RPT_8821C(txdesc, value)                               \\\n\tSET_TX_DESC_SPE_RPT(txdesc, value)\n#define GET_TX_DESC_SPE_RPT_8821C(txdesc) GET_TX_DESC_SPE_RPT(txdesc)\n#define SET_TX_DESC_RAW_8821C(txdesc, value) SET_TX_DESC_RAW(txdesc, value)\n#define GET_TX_DESC_RAW_8821C(txdesc) GET_TX_DESC_RAW(txdesc)\n#define SET_TX_DESC_MOREFRAG_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_MOREFRAG(txdesc, value)\n#define GET_TX_DESC_MOREFRAG_8821C(txdesc) GET_TX_DESC_MOREFRAG(txdesc)\n#define SET_TX_DESC_BK_8821C(txdesc, value) SET_TX_DESC_BK(txdesc, value)\n#define GET_TX_DESC_BK_8821C(txdesc) GET_TX_DESC_BK(txdesc)\n#define SET_TX_DESC_NULL_1_8821C(txdesc, value)                                \\\n\tSET_TX_DESC_NULL_1(txdesc, value)\n#define GET_TX_DESC_NULL_1_8821C(txdesc) GET_TX_DESC_NULL_1(txdesc)\n#define SET_TX_DESC_NULL_0_8821C(txdesc, value)                                \\\n\tSET_TX_DESC_NULL_0(txdesc, value)\n#define GET_TX_DESC_NULL_0_8821C(txdesc) GET_TX_DESC_NULL_0(txdesc)\n#define SET_TX_DESC_RDG_EN_8821C(txdesc, value)                                \\\n\tSET_TX_DESC_RDG_EN(txdesc, value)\n#define GET_TX_DESC_RDG_EN_8821C(txdesc) GET_TX_DESC_RDG_EN(txdesc)\n#define SET_TX_DESC_AGG_EN_8821C(txdesc, value)                                \\\n\tSET_TX_DESC_AGG_EN(txdesc, value)\n#define GET_TX_DESC_AGG_EN_8821C(txdesc) GET_TX_DESC_AGG_EN(txdesc)\n#define SET_TX_DESC_CCA_RTS_8821C(txdesc, value)                               \\\n\tSET_TX_DESC_CCA_RTS(txdesc, value)\n#define GET_TX_DESC_CCA_RTS_8821C(txdesc) GET_TX_DESC_CCA_RTS(txdesc)\n#define SET_TX_DESC_TRI_FRAME_8821C(txdesc, value)                             \\\n\tSET_TX_DESC_TRI_FRAME(txdesc, value)\n#define GET_TX_DESC_TRI_FRAME_8821C(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)\n#define SET_TX_DESC_P_AID_8821C(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)\n#define GET_TX_DESC_P_AID_8821C(txdesc) GET_TX_DESC_P_AID(txdesc)\n\n/*TXDESC_WORD3*/\n\n#define SET_TX_DESC_AMPDU_MAX_TIME_8821C(txdesc, value)                        \\\n\tSET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)\n#define GET_TX_DESC_AMPDU_MAX_TIME_8821C(txdesc)                               \\\n\tGET_TX_DESC_AMPDU_MAX_TIME(txdesc)\n#define SET_TX_DESC_NDPA_8821C(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)\n#define GET_TX_DESC_NDPA_8821C(txdesc) GET_TX_DESC_NDPA(txdesc)\n#define SET_TX_DESC_MAX_AGG_NUM_8821C(txdesc, value)                           \\\n\tSET_TX_DESC_MAX_AGG_NUM(txdesc, value)\n#define GET_TX_DESC_MAX_AGG_NUM_8821C(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)\n#define SET_TX_DESC_USE_MAX_TIME_EN_8821C(txdesc, value)                       \\\n\tSET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)\n#define GET_TX_DESC_USE_MAX_TIME_EN_8821C(txdesc)                              \\\n\tGET_TX_DESC_USE_MAX_TIME_EN(txdesc)\n#define SET_TX_DESC_NAVUSEHDR_8821C(txdesc, value)                             \\\n\tSET_TX_DESC_NAVUSEHDR(txdesc, value)\n#define GET_TX_DESC_NAVUSEHDR_8821C(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)\n#define SET_TX_DESC_CHK_EN_8821C(txdesc, value)                                \\\n\tSET_TX_DESC_CHK_EN(txdesc, value)\n#define GET_TX_DESC_CHK_EN_8821C(txdesc) GET_TX_DESC_CHK_EN(txdesc)\n#define SET_TX_DESC_HW_RTS_EN_8821C(txdesc, value)                             \\\n\tSET_TX_DESC_HW_RTS_EN(txdesc, value)\n#define GET_TX_DESC_HW_RTS_EN_8821C(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)\n#define SET_TX_DESC_RTSEN_8821C(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)\n#define GET_TX_DESC_RTSEN_8821C(txdesc) GET_TX_DESC_RTSEN(txdesc)\n#define SET_TX_DESC_CTS2SELF_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_CTS2SELF(txdesc, value)\n#define GET_TX_DESC_CTS2SELF_8821C(txdesc) GET_TX_DESC_CTS2SELF(txdesc)\n#define SET_TX_DESC_DISDATAFB_8821C(txdesc, value)                             \\\n\tSET_TX_DESC_DISDATAFB(txdesc, value)\n#define GET_TX_DESC_DISDATAFB_8821C(txdesc) GET_TX_DESC_DISDATAFB(txdesc)\n#define SET_TX_DESC_DISRTSFB_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_DISRTSFB(txdesc, value)\n#define GET_TX_DESC_DISRTSFB_8821C(txdesc) GET_TX_DESC_DISRTSFB(txdesc)\n#define SET_TX_DESC_USE_RATE_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_USE_RATE(txdesc, value)\n#define GET_TX_DESC_USE_RATE_8821C(txdesc) GET_TX_DESC_USE_RATE(txdesc)\n#define SET_TX_DESC_HW_SSN_SEL_8821C(txdesc, value)                            \\\n\tSET_TX_DESC_HW_SSN_SEL(txdesc, value)\n#define GET_TX_DESC_HW_SSN_SEL_8821C(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)\n#define SET_TX_DESC_WHEADER_LEN_8821C(txdesc, value)                           \\\n\tSET_TX_DESC_WHEADER_LEN(txdesc, value)\n#define GET_TX_DESC_WHEADER_LEN_8821C(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)\n\n/*TXDESC_WORD4*/\n\n#define SET_TX_DESC_PCTS_MASK_IDX_8821C(txdesc, value)                         \\\n\tSET_TX_DESC_PCTS_MASK_IDX(txdesc, value)\n#define GET_TX_DESC_PCTS_MASK_IDX_8821C(txdesc)                                \\\n\tGET_TX_DESC_PCTS_MASK_IDX(txdesc)\n#define SET_TX_DESC_PCTS_EN_8821C(txdesc, value)                               \\\n\tSET_TX_DESC_PCTS_EN(txdesc, value)\n#define GET_TX_DESC_PCTS_EN_8821C(txdesc) GET_TX_DESC_PCTS_EN(txdesc)\n#define SET_TX_DESC_RTSRATE_8821C(txdesc, value)                               \\\n\tSET_TX_DESC_RTSRATE(txdesc, value)\n#define GET_TX_DESC_RTSRATE_8821C(txdesc) GET_TX_DESC_RTSRATE(txdesc)\n#define SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(txdesc, value)                      \\\n\tSET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)\n#define GET_TX_DESC_RTS_DATA_RTY_LMT_8821C(txdesc)                             \\\n\tGET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)\n#define SET_TX_DESC_RTY_LMT_EN_8821C(txdesc, value)                            \\\n\tSET_TX_DESC_RTY_LMT_EN(txdesc, value)\n#define GET_TX_DESC_RTY_LMT_EN_8821C(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)\n#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(txdesc, value)                   \\\n\tSET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(txdesc)                          \\\n\tGET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)\n#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(txdesc, value)                  \\\n\tSET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(txdesc)                         \\\n\tGET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)\n#define SET_TX_DESC_TRY_RATE_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_TRY_RATE(txdesc, value)\n#define GET_TX_DESC_TRY_RATE_8821C(txdesc) GET_TX_DESC_TRY_RATE(txdesc)\n#define SET_TX_DESC_DATARATE_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_DATARATE(txdesc, value)\n#define GET_TX_DESC_DATARATE_8821C(txdesc) GET_TX_DESC_DATARATE(txdesc)\n\n/*TXDESC_WORD5*/\n\n#define SET_TX_DESC_POLLUTED_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_POLLUTED(txdesc, value)\n#define GET_TX_DESC_POLLUTED_8821C(txdesc) GET_TX_DESC_POLLUTED(txdesc)\n#define SET_TX_DESC_TXPWR_OFSET_8821C(txdesc, value)                           \\\n\tSET_TX_DESC_TXPWR_OFSET(txdesc, value)\n#define GET_TX_DESC_TXPWR_OFSET_8821C(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc)\n#define SET_TX_DESC_TX_ANT_8821C(txdesc, value)                                \\\n\tSET_TX_DESC_TX_ANT(txdesc, value)\n#define GET_TX_DESC_TX_ANT_8821C(txdesc) GET_TX_DESC_TX_ANT(txdesc)\n#define SET_TX_DESC_PORT_ID_8821C(txdesc, value)                               \\\n\tSET_TX_DESC_PORT_ID(txdesc, value)\n#define GET_TX_DESC_PORT_ID_8821C(txdesc) GET_TX_DESC_PORT_ID(txdesc)\n#define SET_TX_DESC_MULTIPLE_PORT_8821C(txdesc, value)                         \\\n\tSET_TX_DESC_MULTIPLE_PORT(txdesc, value)\n#define GET_TX_DESC_MULTIPLE_PORT_8821C(txdesc)                                \\\n\tGET_TX_DESC_MULTIPLE_PORT(txdesc)\n#define SET_TX_DESC_SIGNALING_TAPKT_EN_8821C(txdesc, value)                    \\\n\tSET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)\n#define GET_TX_DESC_SIGNALING_TAPKT_EN_8821C(txdesc)                           \\\n\tGET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)\n#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8821C(txdesc, value)                   \\\n\tSET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)\n#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8821C(txdesc)                          \\\n\tGET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)\n#define SET_TX_DESC_RTS_SHORT_8821C(txdesc, value)                             \\\n\tSET_TX_DESC_RTS_SHORT(txdesc, value)\n#define GET_TX_DESC_RTS_SHORT_8821C(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)\n#define SET_TX_DESC_VCS_STBC_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_VCS_STBC(txdesc, value)\n#define GET_TX_DESC_VCS_STBC_8821C(txdesc) GET_TX_DESC_VCS_STBC(txdesc)\n#define SET_TX_DESC_DATA_STBC_8821C(txdesc, value)                             \\\n\tSET_TX_DESC_DATA_STBC(txdesc, value)\n#define GET_TX_DESC_DATA_STBC_8821C(txdesc) GET_TX_DESC_DATA_STBC(txdesc)\n#define SET_TX_DESC_DATA_LDPC_8821C(txdesc, value)                             \\\n\tSET_TX_DESC_DATA_LDPC(txdesc, value)\n#define GET_TX_DESC_DATA_LDPC_8821C(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)\n#define SET_TX_DESC_DATA_BW_8821C(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_BW(txdesc, value)\n#define GET_TX_DESC_DATA_BW_8821C(txdesc) GET_TX_DESC_DATA_BW(txdesc)\n#define SET_TX_DESC_DATA_SHORT_8821C(txdesc, value)                            \\\n\tSET_TX_DESC_DATA_SHORT(txdesc, value)\n#define GET_TX_DESC_DATA_SHORT_8821C(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)\n#define SET_TX_DESC_DATA_SC_8821C(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_SC(txdesc, value)\n#define GET_TX_DESC_DATA_SC_8821C(txdesc) GET_TX_DESC_DATA_SC(txdesc)\n\n/*TXDESC_WORD6*/\n\n#define SET_TX_DESC_ANTSEL_D_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_D(txdesc, value)\n#define GET_TX_DESC_ANTSEL_D_8821C(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)\n#define SET_TX_DESC_ANT_MAPD_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPD(txdesc, value)\n#define GET_TX_DESC_ANT_MAPD_8821C(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)\n#define SET_TX_DESC_ANT_MAPC_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPC(txdesc, value)\n#define GET_TX_DESC_ANT_MAPC_8821C(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)\n#define SET_TX_DESC_ANT_MAPB_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPB(txdesc, value)\n#define GET_TX_DESC_ANT_MAPB_8821C(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)\n#define SET_TX_DESC_ANT_MAPA_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPA(txdesc, value)\n#define GET_TX_DESC_ANT_MAPA_8821C(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)\n#define SET_TX_DESC_ANTSEL_C_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_C(txdesc, value)\n#define GET_TX_DESC_ANTSEL_C_8821C(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)\n#define SET_TX_DESC_ANTSEL_B_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_B(txdesc, value)\n#define GET_TX_DESC_ANTSEL_B_8821C(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)\n#define SET_TX_DESC_ANTSEL_A_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_A(txdesc, value)\n#define GET_TX_DESC_ANTSEL_A_8821C(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)\n#define SET_TX_DESC_MBSSID_8821C(txdesc, value)                                \\\n\tSET_TX_DESC_MBSSID(txdesc, value)\n#define GET_TX_DESC_MBSSID_8821C(txdesc) GET_TX_DESC_MBSSID(txdesc)\n#define SET_TX_DESC_SW_DEFINE_8821C(txdesc, value)                             \\\n\tSET_TX_DESC_SW_DEFINE(txdesc, value)\n#define GET_TX_DESC_SW_DEFINE_8821C(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)\n\n/*TXDESC_WORD7*/\n\n#define SET_TX_DESC_DMA_TXAGG_NUM_8821C(txdesc, value)                         \\\n\tSET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)\n#define GET_TX_DESC_DMA_TXAGG_NUM_8821C(txdesc)                                \\\n\tGET_TX_DESC_DMA_TXAGG_NUM(txdesc)\n#define SET_TX_DESC_FINAL_DATA_RATE_8821C(txdesc, value)                       \\\n\tSET_TX_DESC_FINAL_DATA_RATE(txdesc, value)\n#define GET_TX_DESC_FINAL_DATA_RATE_8821C(txdesc)                              \\\n\tGET_TX_DESC_FINAL_DATA_RATE(txdesc)\n#define SET_TX_DESC_NTX_MAP_8821C(txdesc, value)                               \\\n\tSET_TX_DESC_NTX_MAP(txdesc, value)\n#define GET_TX_DESC_NTX_MAP_8821C(txdesc) GET_TX_DESC_NTX_MAP(txdesc)\n#define SET_TX_DESC_TX_BUFF_SIZE_8821C(txdesc, value)                          \\\n\tSET_TX_DESC_TX_BUFF_SIZE(txdesc, value)\n#define GET_TX_DESC_TX_BUFF_SIZE_8821C(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)\n#define SET_TX_DESC_TXDESC_CHECKSUM_8821C(txdesc, value)                       \\\n\tSET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)\n#define GET_TX_DESC_TXDESC_CHECKSUM_8821C(txdesc)                              \\\n\tGET_TX_DESC_TXDESC_CHECKSUM(txdesc)\n#define SET_TX_DESC_TIMESTAMP_8821C(txdesc, value)                             \\\n\tSET_TX_DESC_TIMESTAMP(txdesc, value)\n#define GET_TX_DESC_TIMESTAMP_8821C(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)\n\n/*TXDESC_WORD8*/\n\n#define SET_TX_DESC_TXWIFI_CP_8821C(txdesc, value)                             \\\n\tSET_TX_DESC_TXWIFI_CP(txdesc, value)\n#define GET_TX_DESC_TXWIFI_CP_8821C(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)\n#define SET_TX_DESC_MAC_CP_8821C(txdesc, value)                                \\\n\tSET_TX_DESC_MAC_CP(txdesc, value)\n#define GET_TX_DESC_MAC_CP_8821C(txdesc) GET_TX_DESC_MAC_CP(txdesc)\n#define SET_TX_DESC_STW_PKTRE_DIS_8821C(txdesc, value)                         \\\n\tSET_TX_DESC_STW_PKTRE_DIS(txdesc, value)\n#define GET_TX_DESC_STW_PKTRE_DIS_8821C(txdesc)                                \\\n\tGET_TX_DESC_STW_PKTRE_DIS(txdesc)\n#define SET_TX_DESC_STW_RB_DIS_8821C(txdesc, value)                            \\\n\tSET_TX_DESC_STW_RB_DIS(txdesc, value)\n#define GET_TX_DESC_STW_RB_DIS_8821C(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)\n#define SET_TX_DESC_STW_RATE_DIS_8821C(txdesc, value)                          \\\n\tSET_TX_DESC_STW_RATE_DIS(txdesc, value)\n#define GET_TX_DESC_STW_RATE_DIS_8821C(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)\n#define SET_TX_DESC_STW_ANT_DIS_8821C(txdesc, value)                           \\\n\tSET_TX_DESC_STW_ANT_DIS(txdesc, value)\n#define GET_TX_DESC_STW_ANT_DIS_8821C(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)\n#define SET_TX_DESC_STW_EN_8821C(txdesc, value)                                \\\n\tSET_TX_DESC_STW_EN(txdesc, value)\n#define GET_TX_DESC_STW_EN_8821C(txdesc) GET_TX_DESC_STW_EN(txdesc)\n#define SET_TX_DESC_SMH_EN_8821C(txdesc, value)                                \\\n\tSET_TX_DESC_SMH_EN(txdesc, value)\n#define GET_TX_DESC_SMH_EN_8821C(txdesc) GET_TX_DESC_SMH_EN(txdesc)\n#define SET_TX_DESC_TAILPAGE_L_8821C(txdesc, value)                            \\\n\tSET_TX_DESC_TAILPAGE_L(txdesc, value)\n#define GET_TX_DESC_TAILPAGE_L_8821C(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)\n#define SET_TX_DESC_SDIO_DMASEQ_8821C(txdesc, value)                           \\\n\tSET_TX_DESC_SDIO_DMASEQ(txdesc, value)\n#define GET_TX_DESC_SDIO_DMASEQ_8821C(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)\n#define SET_TX_DESC_NEXTHEADPAGE_L_8821C(txdesc, value)                        \\\n\tSET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)\n#define GET_TX_DESC_NEXTHEADPAGE_L_8821C(txdesc)                               \\\n\tGET_TX_DESC_NEXTHEADPAGE_L(txdesc)\n#define SET_TX_DESC_EN_HWSEQ_8821C(txdesc, value)                              \\\n\tSET_TX_DESC_EN_HWSEQ(txdesc, value)\n#define GET_TX_DESC_EN_HWSEQ_8821C(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)\n#define SET_TX_DESC_EN_HWEXSEQ_8821C(txdesc, value)                            \\\n\tSET_TX_DESC_EN_HWEXSEQ(txdesc, value)\n#define GET_TX_DESC_EN_HWEXSEQ_8821C(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)\n#define SET_TX_DESC_DATA_RC_8821C(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_RC(txdesc, value)\n#define GET_TX_DESC_DATA_RC_8821C(txdesc) GET_TX_DESC_DATA_RC(txdesc)\n#define SET_TX_DESC_BAR_RTY_TH_8821C(txdesc, value)                            \\\n\tSET_TX_DESC_BAR_RTY_TH(txdesc, value)\n#define GET_TX_DESC_BAR_RTY_TH_8821C(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)\n#define SET_TX_DESC_RTS_RC_8821C(txdesc, value)                                \\\n\tSET_TX_DESC_RTS_RC(txdesc, value)\n#define GET_TX_DESC_RTS_RC_8821C(txdesc) GET_TX_DESC_RTS_RC(txdesc)\n\n/*TXDESC_WORD9*/\n\n#define SET_TX_DESC_TAILPAGE_H_8821C(txdesc, value)                            \\\n\tSET_TX_DESC_TAILPAGE_H(txdesc, value)\n#define GET_TX_DESC_TAILPAGE_H_8821C(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)\n#define SET_TX_DESC_NEXTHEADPAGE_H_8821C(txdesc, value)                        \\\n\tSET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)\n#define GET_TX_DESC_NEXTHEADPAGE_H_8821C(txdesc)                               \\\n\tGET_TX_DESC_NEXTHEADPAGE_H(txdesc)\n#define SET_TX_DESC_SW_SEQ_8821C(txdesc, value)                                \\\n\tSET_TX_DESC_SW_SEQ(txdesc, value)\n#define GET_TX_DESC_SW_SEQ_8821C(txdesc) GET_TX_DESC_SW_SEQ(txdesc)\n#define SET_TX_DESC_TXBF_PATH_8821C(txdesc, value)                             \\\n\tSET_TX_DESC_TXBF_PATH(txdesc, value)\n#define GET_TX_DESC_TXBF_PATH_8821C(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)\n#define SET_TX_DESC_PADDING_LEN_8821C(txdesc, value)                           \\\n\tSET_TX_DESC_PADDING_LEN(txdesc, value)\n#define GET_TX_DESC_PADDING_LEN_8821C(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)\n#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(txdesc, value)                   \\\n\tSET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)\n#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(txdesc)                          \\\n\tGET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)\n\n/*WORD10*/\n\n#define SET_TX_DESC_MU_DATARATE_8821C(txdesc, value)                           \\\n\tSET_TX_DESC_MU_DATARATE(txdesc, value)\n#define GET_TX_DESC_MU_DATARATE_8821C(txdesc) GET_TX_DESC_MU_DATARATE(txdesc)\n#define SET_TX_DESC_MU_RC_8821C(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value)\n#define GET_TX_DESC_MU_RC_8821C(txdesc) GET_TX_DESC_MU_RC(txdesc)\n#define SET_TX_DESC_SND_PKT_SEL_8821C(txdesc, value)                           \\\n\tSET_TX_DESC_SND_PKT_SEL(txdesc, value)\n#define GET_TX_DESC_SND_PKT_SEL_8821C(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n/*TXDESC_WORD0*/\n\n#define SET_TX_DESC_IE_END_BODY_8814B(txdesc, value)                           \\\n\tSET_TX_DESC_IE_END_BODY(txdesc, value)\n#define GET_TX_DESC_IE_END_BODY_8814B(txdesc) GET_TX_DESC_IE_END_BODY(txdesc)\n#define SET_TX_DESC_AGG_EN_8814B(txdesc, value)                                \\\n\tSET_TX_DESC_AGG_EN_V1(txdesc, value)\n#define GET_TX_DESC_AGG_EN_8814B(txdesc) GET_TX_DESC_AGG_EN_V1(txdesc)\n#define SET_TX_DESC_BK_8814B(txdesc, value) SET_TX_DESC_BK_V1(txdesc, value)\n#define GET_TX_DESC_BK_8814B(txdesc) GET_TX_DESC_BK_V1(txdesc)\n#define SET_TX_DESC_PKT_OFFSET_8814B(txdesc, value)                            \\\n\tSET_TX_DESC_PKT_OFFSET_V1(txdesc, value)\n#define GET_TX_DESC_PKT_OFFSET_8814B(txdesc) GET_TX_DESC_PKT_OFFSET_V1(txdesc)\n#define SET_TX_DESC_OFFSET_8814B(txdesc, value)                                \\\n\tSET_TX_DESC_OFFSET(txdesc, value)\n#define GET_TX_DESC_OFFSET_8814B(txdesc) GET_TX_DESC_OFFSET(txdesc)\n#define SET_TX_DESC_TXPKTSIZE_8814B(txdesc, value)                             \\\n\tSET_TX_DESC_TXPKTSIZE(txdesc, value)\n#define GET_TX_DESC_TXPKTSIZE_8814B(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)\n\n/*WORD1*/\n\n#define SET_TX_DESC_AMSDU_8814B(txdesc, value) SET_TX_DESC_AMSDU(txdesc, value)\n#define GET_TX_DESC_AMSDU_8814B(txdesc) GET_TX_DESC_AMSDU(txdesc)\n#define SET_TX_DESC_HW_AES_IV_8814B(txdesc, value)                             \\\n\tSET_TX_DESC_HW_AES_IV_V1(txdesc, value)\n#define GET_TX_DESC_HW_AES_IV_8814B(txdesc) GET_TX_DESC_HW_AES_IV_V1(txdesc)\n#define SET_TX_DESC_MHR_CP_8814B(txdesc, value)                                \\\n\tSET_TX_DESC_MHR_CP(txdesc, value)\n#define GET_TX_DESC_MHR_CP_8814B(txdesc) GET_TX_DESC_MHR_CP(txdesc)\n#define SET_TX_DESC_SMH_EN_8814B(txdesc, value)                                \\\n\tSET_TX_DESC_SMH_EN_V1(txdesc, value)\n#define GET_TX_DESC_SMH_EN_8814B(txdesc) GET_TX_DESC_SMH_EN_V1(txdesc)\n#define SET_TX_DESC_SMH_CAM_8814B(txdesc, value)                               \\\n\tSET_TX_DESC_SMH_CAM(txdesc, value)\n#define GET_TX_DESC_SMH_CAM_8814B(txdesc) GET_TX_DESC_SMH_CAM(txdesc)\n#define SET_TX_DESC_EXT_EDCA_8814B(txdesc, value)                              \\\n\tSET_TX_DESC_EXT_EDCA(txdesc, value)\n#define GET_TX_DESC_EXT_EDCA_8814B(txdesc) GET_TX_DESC_EXT_EDCA(txdesc)\n#define SET_TX_DESC_QSEL_8814B(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)\n#define GET_TX_DESC_QSEL_8814B(txdesc) GET_TX_DESC_QSEL(txdesc)\n#define SET_TX_DESC_MACID_8814B(txdesc, value)                                 \\\n\tSET_TX_DESC_MACID_V1(txdesc, value)\n#define GET_TX_DESC_MACID_8814B(txdesc) GET_TX_DESC_MACID_V1(txdesc)\n\n/*TXDESC_WORD2*/\n\n#define SET_TX_DESC_CHK_EN_8814B(txdesc, value)                                \\\n\tSET_TX_DESC_CHK_EN_V1(txdesc, value)\n#define GET_TX_DESC_CHK_EN_8814B(txdesc) GET_TX_DESC_CHK_EN_V1(txdesc)\n#define SET_TX_DESC_DMA_PRI_8814B(txdesc, value)                               \\\n\tSET_TX_DESC_DMA_PRI(txdesc, value)\n#define GET_TX_DESC_DMA_PRI_8814B(txdesc) GET_TX_DESC_DMA_PRI(txdesc)\n#define SET_TX_DESC_MAX_AMSDU_MODE_8814B(txdesc, value)                        \\\n\tSET_TX_DESC_MAX_AMSDU_MODE(txdesc, value)\n#define GET_TX_DESC_MAX_AMSDU_MODE_8814B(txdesc)                               \\\n\tGET_TX_DESC_MAX_AMSDU_MODE(txdesc)\n#define SET_TX_DESC_DMA_TXAGG_NUM_8814B(txdesc, value)                         \\\n\tSET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc, value)\n#define GET_TX_DESC_DMA_TXAGG_NUM_8814B(txdesc)                                \\\n\tGET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc)\n#define SET_TX_DESC_TXDESC_CHECKSUM_8814B(txdesc, value)                       \\\n\tSET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc, value)\n#define GET_TX_DESC_TXDESC_CHECKSUM_8814B(txdesc)                              \\\n\tGET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc)\n\n/*TXDESC_WORD3*/\n\n#define SET_TX_DESC_OFFLOAD_SIZE_8814B(txdesc, value)                          \\\n\tSET_TX_DESC_OFFLOAD_SIZE(txdesc, value)\n#define GET_TX_DESC_OFFLOAD_SIZE_8814B(txdesc) GET_TX_DESC_OFFLOAD_SIZE(txdesc)\n#define SET_TX_DESC_CHANNEL_DMA_8814B(txdesc, value)                           \\\n\tSET_TX_DESC_CHANNEL_DMA(txdesc, value)\n#define GET_TX_DESC_CHANNEL_DMA_8814B(txdesc) GET_TX_DESC_CHANNEL_DMA(txdesc)\n#define SET_TX_DESC_IE_CNT_8814B(txdesc, value)                                \\\n\tSET_TX_DESC_IE_CNT(txdesc, value)\n#define GET_TX_DESC_IE_CNT_8814B(txdesc) GET_TX_DESC_IE_CNT(txdesc)\n#define SET_TX_DESC_IE_CNT_EN_8814B(txdesc, value)                             \\\n\tSET_TX_DESC_IE_CNT_EN(txdesc, value)\n#define GET_TX_DESC_IE_CNT_EN_8814B(txdesc) GET_TX_DESC_IE_CNT_EN(txdesc)\n#define SET_TX_DESC_WHEADER_LEN_8814B(txdesc, value)                           \\\n\tSET_TX_DESC_WHEADER_LEN_V1(txdesc, value)\n#define GET_TX_DESC_WHEADER_LEN_8814B(txdesc) GET_TX_DESC_WHEADER_LEN_V1(txdesc)\n\n/*TXDESC_WORD4*/\n\n/*TXDESC_WORD5*/\n\n/*TXDESC_WORD6*/\n\n/*TXDESC_WORD7*/\n\n/*TXDESC_WORD8*/\n\n/*TXDESC_WORD9*/\n\n/*WORD10*/\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/*TXDESC_WORD0*/\n\n#define SET_TX_DESC_DISQSELSEQ_8198F(txdesc, value)                            \\\n\tSET_TX_DESC_DISQSELSEQ(txdesc, value)\n#define GET_TX_DESC_DISQSELSEQ_8198F(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)\n#define SET_TX_DESC_GF_8198F(txdesc, value) SET_TX_DESC_GF(txdesc, value)\n#define GET_TX_DESC_GF_8198F(txdesc) GET_TX_DESC_GF(txdesc)\n#define SET_TX_DESC_NO_ACM_8198F(txdesc, value)                                \\\n\tSET_TX_DESC_NO_ACM(txdesc, value)\n#define GET_TX_DESC_NO_ACM_8198F(txdesc) GET_TX_DESC_NO_ACM(txdesc)\n#define SET_TX_DESC_BCNPKT_TSF_CTRL_8198F(txdesc, value)                       \\\n\tSET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)\n#define GET_TX_DESC_BCNPKT_TSF_CTRL_8198F(txdesc)                              \\\n\tGET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)\n#define SET_TX_DESC_AMSDU_PAD_EN_8198F(txdesc, value)                          \\\n\tSET_TX_DESC_AMSDU_PAD_EN(txdesc, value)\n#define GET_TX_DESC_AMSDU_PAD_EN_8198F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)\n#define SET_TX_DESC_LS_8198F(txdesc, value) SET_TX_DESC_LS(txdesc, value)\n#define GET_TX_DESC_LS_8198F(txdesc) GET_TX_DESC_LS(txdesc)\n#define SET_TX_DESC_HTC_8198F(txdesc, value) SET_TX_DESC_HTC(txdesc, value)\n#define GET_TX_DESC_HTC_8198F(txdesc) GET_TX_DESC_HTC(txdesc)\n#define SET_TX_DESC_BMC_8198F(txdesc, value) SET_TX_DESC_BMC(txdesc, value)\n#define GET_TX_DESC_BMC_8198F(txdesc) GET_TX_DESC_BMC(txdesc)\n#define SET_TX_DESC_OFFSET_8198F(txdesc, value)                                \\\n\tSET_TX_DESC_OFFSET(txdesc, value)\n#define GET_TX_DESC_OFFSET_8198F(txdesc) GET_TX_DESC_OFFSET(txdesc)\n#define SET_TX_DESC_TXPKTSIZE_8198F(txdesc, value)                             \\\n\tSET_TX_DESC_TXPKTSIZE(txdesc, value)\n#define GET_TX_DESC_TXPKTSIZE_8198F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)\n\n/*WORD1*/\n\n#define SET_TX_DESC_HW_AES_IV_8198F(txdesc, value)                             \\\n\tSET_TX_DESC_HW_AES_IV_V2(txdesc, value)\n#define GET_TX_DESC_HW_AES_IV_8198F(txdesc) GET_TX_DESC_HW_AES_IV_V2(txdesc)\n#define SET_TX_DESC_FTM_EN_8198F(txdesc, value)                                \\\n\tSET_TX_DESC_FTM_EN_V1(txdesc, value)\n#define GET_TX_DESC_FTM_EN_8198F(txdesc) GET_TX_DESC_FTM_EN_V1(txdesc)\n#define SET_TX_DESC_MOREDATA_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_MOREDATA(txdesc, value)\n#define GET_TX_DESC_MOREDATA_8198F(txdesc) GET_TX_DESC_MOREDATA(txdesc)\n#define SET_TX_DESC_PKT_OFFSET_8198F(txdesc, value)                            \\\n\tSET_TX_DESC_PKT_OFFSET(txdesc, value)\n#define GET_TX_DESC_PKT_OFFSET_8198F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)\n#define SET_TX_DESC_SEC_TYPE_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_SEC_TYPE(txdesc, value)\n#define GET_TX_DESC_SEC_TYPE_8198F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)\n#define SET_TX_DESC_EN_DESC_ID_8198F(txdesc, value)                            \\\n\tSET_TX_DESC_EN_DESC_ID(txdesc, value)\n#define GET_TX_DESC_EN_DESC_ID_8198F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)\n#define SET_TX_DESC_RATE_ID_8198F(txdesc, value)                               \\\n\tSET_TX_DESC_RATE_ID(txdesc, value)\n#define GET_TX_DESC_RATE_ID_8198F(txdesc) GET_TX_DESC_RATE_ID(txdesc)\n#define SET_TX_DESC_PIFS_8198F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)\n#define GET_TX_DESC_PIFS_8198F(txdesc) GET_TX_DESC_PIFS(txdesc)\n#define SET_TX_DESC_LSIG_TXOP_EN_8198F(txdesc, value)                          \\\n\tSET_TX_DESC_LSIG_TXOP_EN(txdesc, value)\n#define GET_TX_DESC_LSIG_TXOP_EN_8198F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)\n#define SET_TX_DESC_RD_NAV_EXT_8198F(txdesc, value)                            \\\n\tSET_TX_DESC_RD_NAV_EXT(txdesc, value)\n#define GET_TX_DESC_RD_NAV_EXT_8198F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)\n#define SET_TX_DESC_QSEL_8198F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)\n#define GET_TX_DESC_QSEL_8198F(txdesc) GET_TX_DESC_QSEL(txdesc)\n#define SET_TX_DESC_SPECIAL_CW_8198F(txdesc, value)                            \\\n\tSET_TX_DESC_SPECIAL_CW(txdesc, value)\n#define GET_TX_DESC_SPECIAL_CW_8198F(txdesc) GET_TX_DESC_SPECIAL_CW(txdesc)\n#define SET_TX_DESC_MACID_8198F(txdesc, value) SET_TX_DESC_MACID(txdesc, value)\n#define GET_TX_DESC_MACID_8198F(txdesc) GET_TX_DESC_MACID(txdesc)\n\n/*TXDESC_WORD2*/\n\n#define SET_TX_DESC_ANTCEL_D_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_ANTCEL_D_V1(txdesc, value)\n#define GET_TX_DESC_ANTCEL_D_8198F(txdesc) GET_TX_DESC_ANTCEL_D_V1(txdesc)\n#define SET_TX_DESC_ANTSEL_C_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_C_V1(txdesc, value)\n#define GET_TX_DESC_ANTSEL_C_8198F(txdesc) GET_TX_DESC_ANTSEL_C_V1(txdesc)\n#define SET_TX_DESC_BT_NULL_8198F(txdesc, value)                               \\\n\tSET_TX_DESC_BT_NULL(txdesc, value)\n#define GET_TX_DESC_BT_NULL_8198F(txdesc) GET_TX_DESC_BT_NULL(txdesc)\n#define SET_TX_DESC_AMPDU_DENSITY_8198F(txdesc, value)                         \\\n\tSET_TX_DESC_AMPDU_DENSITY(txdesc, value)\n#define GET_TX_DESC_AMPDU_DENSITY_8198F(txdesc)                                \\\n\tGET_TX_DESC_AMPDU_DENSITY(txdesc)\n#define SET_TX_DESC_SPE_RPT_8198F(txdesc, value)                               \\\n\tSET_TX_DESC_SPE_RPT(txdesc, value)\n#define GET_TX_DESC_SPE_RPT_8198F(txdesc) GET_TX_DESC_SPE_RPT(txdesc)\n#define SET_TX_DESC_RAW_8198F(txdesc, value) SET_TX_DESC_RAW(txdesc, value)\n#define GET_TX_DESC_RAW_8198F(txdesc) GET_TX_DESC_RAW(txdesc)\n#define SET_TX_DESC_MOREFRAG_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_MOREFRAG(txdesc, value)\n#define GET_TX_DESC_MOREFRAG_8198F(txdesc) GET_TX_DESC_MOREFRAG(txdesc)\n#define SET_TX_DESC_BK_8198F(txdesc, value) SET_TX_DESC_BK(txdesc, value)\n#define GET_TX_DESC_BK_8198F(txdesc) GET_TX_DESC_BK(txdesc)\n#define SET_TX_DESC_NULL_1_8198F(txdesc, value)                                \\\n\tSET_TX_DESC_NULL_1(txdesc, value)\n#define GET_TX_DESC_NULL_1_8198F(txdesc) GET_TX_DESC_NULL_1(txdesc)\n#define SET_TX_DESC_NULL_0_8198F(txdesc, value)                                \\\n\tSET_TX_DESC_NULL_0(txdesc, value)\n#define GET_TX_DESC_NULL_0_8198F(txdesc) GET_TX_DESC_NULL_0(txdesc)\n#define SET_TX_DESC_RDG_EN_8198F(txdesc, value)                                \\\n\tSET_TX_DESC_RDG_EN(txdesc, value)\n#define GET_TX_DESC_RDG_EN_8198F(txdesc) GET_TX_DESC_RDG_EN(txdesc)\n#define SET_TX_DESC_AGG_EN_8198F(txdesc, value)                                \\\n\tSET_TX_DESC_AGG_EN(txdesc, value)\n#define GET_TX_DESC_AGG_EN_8198F(txdesc) GET_TX_DESC_AGG_EN(txdesc)\n#define SET_TX_DESC_CCA_RTS_8198F(txdesc, value)                               \\\n\tSET_TX_DESC_CCA_RTS(txdesc, value)\n#define GET_TX_DESC_CCA_RTS_8198F(txdesc) GET_TX_DESC_CCA_RTS(txdesc)\n#define SET_TX_DESC_TRI_FRAME_8198F(txdesc, value)                             \\\n\tSET_TX_DESC_TRI_FRAME(txdesc, value)\n#define GET_TX_DESC_TRI_FRAME_8198F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)\n#define SET_TX_DESC_P_AID_8198F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)\n#define GET_TX_DESC_P_AID_8198F(txdesc) GET_TX_DESC_P_AID(txdesc)\n\n/*TXDESC_WORD3*/\n\n#define SET_TX_DESC_AMPDU_MAX_TIME_8198F(txdesc, value)                        \\\n\tSET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)\n#define GET_TX_DESC_AMPDU_MAX_TIME_8198F(txdesc)                               \\\n\tGET_TX_DESC_AMPDU_MAX_TIME(txdesc)\n#define SET_TX_DESC_NDPA_8198F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)\n#define GET_TX_DESC_NDPA_8198F(txdesc) GET_TX_DESC_NDPA(txdesc)\n#define SET_TX_DESC_MAX_AGG_NUM_8198F(txdesc, value)                           \\\n\tSET_TX_DESC_MAX_AGG_NUM(txdesc, value)\n#define GET_TX_DESC_MAX_AGG_NUM_8198F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)\n#define SET_TX_DESC_USE_MAX_TIME_EN_8198F(txdesc, value)                       \\\n\tSET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)\n#define GET_TX_DESC_USE_MAX_TIME_EN_8198F(txdesc)                              \\\n\tGET_TX_DESC_USE_MAX_TIME_EN(txdesc)\n#define SET_TX_DESC_NAVUSEHDR_8198F(txdesc, value)                             \\\n\tSET_TX_DESC_NAVUSEHDR(txdesc, value)\n#define GET_TX_DESC_NAVUSEHDR_8198F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)\n#define SET_TX_DESC_CHK_EN_8198F(txdesc, value)                                \\\n\tSET_TX_DESC_CHK_EN(txdesc, value)\n#define GET_TX_DESC_CHK_EN_8198F(txdesc) GET_TX_DESC_CHK_EN(txdesc)\n#define SET_TX_DESC_HW_RTS_EN_8198F(txdesc, value)                             \\\n\tSET_TX_DESC_HW_RTS_EN(txdesc, value)\n#define GET_TX_DESC_HW_RTS_EN_8198F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)\n#define SET_TX_DESC_RTSEN_8198F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)\n#define GET_TX_DESC_RTSEN_8198F(txdesc) GET_TX_DESC_RTSEN(txdesc)\n#define SET_TX_DESC_CTS2SELF_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_CTS2SELF(txdesc, value)\n#define GET_TX_DESC_CTS2SELF_8198F(txdesc) GET_TX_DESC_CTS2SELF(txdesc)\n#define SET_TX_DESC_DISDATAFB_8198F(txdesc, value)                             \\\n\tSET_TX_DESC_DISDATAFB(txdesc, value)\n#define GET_TX_DESC_DISDATAFB_8198F(txdesc) GET_TX_DESC_DISDATAFB(txdesc)\n#define SET_TX_DESC_DISRTSFB_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_DISRTSFB(txdesc, value)\n#define GET_TX_DESC_DISRTSFB_8198F(txdesc) GET_TX_DESC_DISRTSFB(txdesc)\n#define SET_TX_DESC_USE_RATE_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_USE_RATE(txdesc, value)\n#define GET_TX_DESC_USE_RATE_8198F(txdesc) GET_TX_DESC_USE_RATE(txdesc)\n#define SET_TX_DESC_HW_SSN_SEL_8198F(txdesc, value)                            \\\n\tSET_TX_DESC_HW_SSN_SEL(txdesc, value)\n#define GET_TX_DESC_HW_SSN_SEL_8198F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)\n#define SET_TX_DESC_WHEADER_LEN_8198F(txdesc, value)                           \\\n\tSET_TX_DESC_WHEADER_LEN(txdesc, value)\n#define GET_TX_DESC_WHEADER_LEN_8198F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)\n\n/*TXDESC_WORD4*/\n\n#define SET_TX_DESC_PCTS_MASK_IDX_8198F(txdesc, value)                         \\\n\tSET_TX_DESC_PCTS_MASK_IDX(txdesc, value)\n#define GET_TX_DESC_PCTS_MASK_IDX_8198F(txdesc)                                \\\n\tGET_TX_DESC_PCTS_MASK_IDX(txdesc)\n#define SET_TX_DESC_PCTS_EN_8198F(txdesc, value)                               \\\n\tSET_TX_DESC_PCTS_EN(txdesc, value)\n#define GET_TX_DESC_PCTS_EN_8198F(txdesc) GET_TX_DESC_PCTS_EN(txdesc)\n#define SET_TX_DESC_RTSRATE_8198F(txdesc, value)                               \\\n\tSET_TX_DESC_RTSRATE(txdesc, value)\n#define GET_TX_DESC_RTSRATE_8198F(txdesc) GET_TX_DESC_RTSRATE(txdesc)\n#define SET_TX_DESC_RTS_DATA_RTY_LMT_8198F(txdesc, value)                      \\\n\tSET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)\n#define GET_TX_DESC_RTS_DATA_RTY_LMT_8198F(txdesc)                             \\\n\tGET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)\n#define SET_TX_DESC_RTY_LMT_EN_8198F(txdesc, value)                            \\\n\tSET_TX_DESC_RTY_LMT_EN(txdesc, value)\n#define GET_TX_DESC_RTY_LMT_EN_8198F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)\n#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8198F(txdesc, value)                   \\\n\tSET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8198F(txdesc)                          \\\n\tGET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)\n#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8198F(txdesc, value)                  \\\n\tSET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8198F(txdesc)                         \\\n\tGET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)\n#define SET_TX_DESC_TRY_RATE_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_TRY_RATE(txdesc, value)\n#define GET_TX_DESC_TRY_RATE_8198F(txdesc) GET_TX_DESC_TRY_RATE(txdesc)\n#define SET_TX_DESC_DATARATE_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_DATARATE(txdesc, value)\n#define GET_TX_DESC_DATARATE_8198F(txdesc) GET_TX_DESC_DATARATE(txdesc)\n\n/*TXDESC_WORD5*/\n\n#define SET_TX_DESC_POLLUTED_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_POLLUTED(txdesc, value)\n#define GET_TX_DESC_POLLUTED_8198F(txdesc) GET_TX_DESC_POLLUTED(txdesc)\n#define SET_TX_DESC_TXPWR_OFSET_8198F(txdesc, value)                           \\\n\tSET_TX_DESC_TXPWR_OFSET(txdesc, value)\n#define GET_TX_DESC_TXPWR_OFSET_8198F(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc)\n#define SET_TX_DESC_DROP_ID_8198F(txdesc, value)                               \\\n\tSET_TX_DESC_DROP_ID(txdesc, value)\n#define GET_TX_DESC_DROP_ID_8198F(txdesc) GET_TX_DESC_DROP_ID(txdesc)\n#define SET_TX_DESC_PORT_ID_8198F(txdesc, value)                               \\\n\tSET_TX_DESC_PORT_ID(txdesc, value)\n#define GET_TX_DESC_PORT_ID_8198F(txdesc) GET_TX_DESC_PORT_ID(txdesc)\n#define SET_TX_DESC_MULTIPLE_PORT_8198F(txdesc, value)                         \\\n\tSET_TX_DESC_MULTIPLE_PORT(txdesc, value)\n#define GET_TX_DESC_MULTIPLE_PORT_8198F(txdesc)                                \\\n\tGET_TX_DESC_MULTIPLE_PORT(txdesc)\n#define SET_TX_DESC_SIGNALING_TAPKT_EN_8198F(txdesc, value)                    \\\n\tSET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)\n#define GET_TX_DESC_SIGNALING_TAPKT_EN_8198F(txdesc)                           \\\n\tGET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)\n#define SET_TX_DESC_RTS_SC_8198F(txdesc, value)                                \\\n\tSET_TX_DESC_RTS_SC(txdesc, value)\n#define GET_TX_DESC_RTS_SC_8198F(txdesc) GET_TX_DESC_RTS_SC(txdesc)\n#define SET_TX_DESC_RTS_SHORT_8198F(txdesc, value)                             \\\n\tSET_TX_DESC_RTS_SHORT(txdesc, value)\n#define GET_TX_DESC_RTS_SHORT_8198F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)\n#define SET_TX_DESC_VCS_STBC_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_VCS_STBC(txdesc, value)\n#define GET_TX_DESC_VCS_STBC_8198F(txdesc) GET_TX_DESC_VCS_STBC(txdesc)\n#define SET_TX_DESC_DATA_STBC_8198F(txdesc, value)                             \\\n\tSET_TX_DESC_DATA_STBC(txdesc, value)\n#define GET_TX_DESC_DATA_STBC_8198F(txdesc) GET_TX_DESC_DATA_STBC(txdesc)\n#define SET_TX_DESC_DATA_LDPC_8198F(txdesc, value)                             \\\n\tSET_TX_DESC_DATA_LDPC(txdesc, value)\n#define GET_TX_DESC_DATA_LDPC_8198F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)\n#define SET_TX_DESC_DATA_BW_8198F(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_BW(txdesc, value)\n#define GET_TX_DESC_DATA_BW_8198F(txdesc) GET_TX_DESC_DATA_BW(txdesc)\n#define SET_TX_DESC_DATA_SHORT_8198F(txdesc, value)                            \\\n\tSET_TX_DESC_DATA_SHORT(txdesc, value)\n#define GET_TX_DESC_DATA_SHORT_8198F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)\n#define SET_TX_DESC_DATA_SC_8198F(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_SC(txdesc, value)\n#define GET_TX_DESC_DATA_SC_8198F(txdesc) GET_TX_DESC_DATA_SC(txdesc)\n\n/*TXDESC_WORD6*/\n\n#define SET_TX_DESC_ANT_MAPD_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPD_V1(txdesc, value)\n#define GET_TX_DESC_ANT_MAPD_8198F(txdesc) GET_TX_DESC_ANT_MAPD_V1(txdesc)\n#define SET_TX_DESC_ANT_MAPC_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPC_V1(txdesc, value)\n#define GET_TX_DESC_ANT_MAPC_8198F(txdesc) GET_TX_DESC_ANT_MAPC_V1(txdesc)\n#define SET_TX_DESC_ANT_MAPB_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPB_V1(txdesc, value)\n#define GET_TX_DESC_ANT_MAPB_8198F(txdesc) GET_TX_DESC_ANT_MAPB_V1(txdesc)\n#define SET_TX_DESC_ANT_MAPA_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPA_V1(txdesc, value)\n#define GET_TX_DESC_ANT_MAPA_8198F(txdesc) GET_TX_DESC_ANT_MAPA_V1(txdesc)\n#define SET_TX_DESC_ANTSEL_B_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_B_V1(txdesc, value)\n#define GET_TX_DESC_ANTSEL_B_8198F(txdesc) GET_TX_DESC_ANTSEL_B_V1(txdesc)\n#define SET_TX_DESC_ANTSEL_A_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_A_V1(txdesc, value)\n#define GET_TX_DESC_ANTSEL_A_8198F(txdesc) GET_TX_DESC_ANTSEL_A_V1(txdesc)\n#define SET_TX_DESC_MBSSID_8198F(txdesc, value)                                \\\n\tSET_TX_DESC_MBSSID(txdesc, value)\n#define GET_TX_DESC_MBSSID_8198F(txdesc) GET_TX_DESC_MBSSID(txdesc)\n#define SET_TX_DESC_SWPS_SEQ_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_SWPS_SEQ(txdesc, value)\n#define GET_TX_DESC_SWPS_SEQ_8198F(txdesc) GET_TX_DESC_SWPS_SEQ(txdesc)\n\n/*TXDESC_WORD7*/\n\n#define SET_TX_DESC_DMA_TXAGG_NUM_8198F(txdesc, value)                         \\\n\tSET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)\n#define GET_TX_DESC_DMA_TXAGG_NUM_8198F(txdesc)                                \\\n\tGET_TX_DESC_DMA_TXAGG_NUM(txdesc)\n#define SET_TX_DESC_FINAL_DATA_RATE_8198F(txdesc, value)                       \\\n\tSET_TX_DESC_FINAL_DATA_RATE(txdesc, value)\n#define GET_TX_DESC_FINAL_DATA_RATE_8198F(txdesc)                              \\\n\tGET_TX_DESC_FINAL_DATA_RATE(txdesc)\n#define SET_TX_DESC_NTX_MAP_8198F(txdesc, value)                               \\\n\tSET_TX_DESC_NTX_MAP(txdesc, value)\n#define GET_TX_DESC_NTX_MAP_8198F(txdesc) GET_TX_DESC_NTX_MAP(txdesc)\n#define SET_TX_DESC_ANTSEL_EN_8198F(txdesc, value)                             \\\n\tSET_TX_DESC_ANTSEL_EN(txdesc, value)\n#define GET_TX_DESC_ANTSEL_EN_8198F(txdesc) GET_TX_DESC_ANTSEL_EN(txdesc)\n#define SET_TX_DESC_MBSSID_EX_8198F(txdesc, value)                             \\\n\tSET_TX_DESC_MBSSID_EX(txdesc, value)\n#define GET_TX_DESC_MBSSID_EX_8198F(txdesc) GET_TX_DESC_MBSSID_EX(txdesc)\n#define SET_TX_DESC_TX_BUFF_SIZE_8198F(txdesc, value)                          \\\n\tSET_TX_DESC_TX_BUFF_SIZE(txdesc, value)\n#define GET_TX_DESC_TX_BUFF_SIZE_8198F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)\n#define SET_TX_DESC_TXDESC_CHECKSUM_8198F(txdesc, value)                       \\\n\tSET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)\n#define GET_TX_DESC_TXDESC_CHECKSUM_8198F(txdesc)                              \\\n\tGET_TX_DESC_TXDESC_CHECKSUM(txdesc)\n#define SET_TX_DESC_TIMESTAMP_8198F(txdesc, value)                             \\\n\tSET_TX_DESC_TIMESTAMP(txdesc, value)\n#define GET_TX_DESC_TIMESTAMP_8198F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)\n\n/*TXDESC_WORD8*/\n\n#define SET_TX_DESC_TXWIFI_CP_8198F(txdesc, value)                             \\\n\tSET_TX_DESC_TXWIFI_CP(txdesc, value)\n#define GET_TX_DESC_TXWIFI_CP_8198F(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)\n#define SET_TX_DESC_MAC_CP_8198F(txdesc, value)                                \\\n\tSET_TX_DESC_MAC_CP(txdesc, value)\n#define GET_TX_DESC_MAC_CP_8198F(txdesc) GET_TX_DESC_MAC_CP(txdesc)\n#define SET_TX_DESC_STW_PKTRE_DIS_8198F(txdesc, value)                         \\\n\tSET_TX_DESC_STW_PKTRE_DIS(txdesc, value)\n#define GET_TX_DESC_STW_PKTRE_DIS_8198F(txdesc)                                \\\n\tGET_TX_DESC_STW_PKTRE_DIS(txdesc)\n#define SET_TX_DESC_STW_RB_DIS_8198F(txdesc, value)                            \\\n\tSET_TX_DESC_STW_RB_DIS(txdesc, value)\n#define GET_TX_DESC_STW_RB_DIS_8198F(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)\n#define SET_TX_DESC_STW_RATE_DIS_8198F(txdesc, value)                          \\\n\tSET_TX_DESC_STW_RATE_DIS(txdesc, value)\n#define GET_TX_DESC_STW_RATE_DIS_8198F(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)\n#define SET_TX_DESC_STW_ANT_DIS_8198F(txdesc, value)                           \\\n\tSET_TX_DESC_STW_ANT_DIS(txdesc, value)\n#define GET_TX_DESC_STW_ANT_DIS_8198F(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)\n#define SET_TX_DESC_STW_EN_8198F(txdesc, value)                                \\\n\tSET_TX_DESC_STW_EN(txdesc, value)\n#define GET_TX_DESC_STW_EN_8198F(txdesc) GET_TX_DESC_STW_EN(txdesc)\n#define SET_TX_DESC_SMH_EN_8198F(txdesc, value)                                \\\n\tSET_TX_DESC_SMH_EN(txdesc, value)\n#define GET_TX_DESC_SMH_EN_8198F(txdesc) GET_TX_DESC_SMH_EN(txdesc)\n#define SET_TX_DESC_TAILPAGE_L_8198F(txdesc, value)                            \\\n\tSET_TX_DESC_TAILPAGE_L(txdesc, value)\n#define GET_TX_DESC_TAILPAGE_L_8198F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)\n#define SET_TX_DESC_SDIO_DMASEQ_8198F(txdesc, value)                           \\\n\tSET_TX_DESC_SDIO_DMASEQ(txdesc, value)\n#define GET_TX_DESC_SDIO_DMASEQ_8198F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)\n#define SET_TX_DESC_NEXTHEADPAGE_L_8198F(txdesc, value)                        \\\n\tSET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)\n#define GET_TX_DESC_NEXTHEADPAGE_L_8198F(txdesc)                               \\\n\tGET_TX_DESC_NEXTHEADPAGE_L(txdesc)\n#define SET_TX_DESC_EN_HWSEQ_8198F(txdesc, value)                              \\\n\tSET_TX_DESC_EN_HWSEQ(txdesc, value)\n#define GET_TX_DESC_EN_HWSEQ_8198F(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)\n#define SET_TX_DESC_EN_HWEXSEQ_8198F(txdesc, value)                            \\\n\tSET_TX_DESC_EN_HWEXSEQ(txdesc, value)\n#define GET_TX_DESC_EN_HWEXSEQ_8198F(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)\n#define SET_TX_DESC_DATA_RC_8198F(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_RC(txdesc, value)\n#define GET_TX_DESC_DATA_RC_8198F(txdesc) GET_TX_DESC_DATA_RC(txdesc)\n#define SET_TX_DESC_BAR_RTY_TH_8198F(txdesc, value)                            \\\n\tSET_TX_DESC_BAR_RTY_TH(txdesc, value)\n#define GET_TX_DESC_BAR_RTY_TH_8198F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)\n#define SET_TX_DESC_RTS_RC_8198F(txdesc, value)                                \\\n\tSET_TX_DESC_RTS_RC(txdesc, value)\n#define GET_TX_DESC_RTS_RC_8198F(txdesc) GET_TX_DESC_RTS_RC(txdesc)\n\n/*TXDESC_WORD9*/\n\n#define SET_TX_DESC_TAILPAGE_H_8198F(txdesc, value)                            \\\n\tSET_TX_DESC_TAILPAGE_H(txdesc, value)\n#define GET_TX_DESC_TAILPAGE_H_8198F(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)\n#define SET_TX_DESC_NEXTHEADPAGE_H_8198F(txdesc, value)                        \\\n\tSET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)\n#define GET_TX_DESC_NEXTHEADPAGE_H_8198F(txdesc)                               \\\n\tGET_TX_DESC_NEXTHEADPAGE_H(txdesc)\n#define SET_TX_DESC_SW_SEQ_8198F(txdesc, value)                                \\\n\tSET_TX_DESC_SW_SEQ(txdesc, value)\n#define GET_TX_DESC_SW_SEQ_8198F(txdesc) GET_TX_DESC_SW_SEQ(txdesc)\n#define SET_TX_DESC_TXBF_PATH_8198F(txdesc, value)                             \\\n\tSET_TX_DESC_TXBF_PATH(txdesc, value)\n#define GET_TX_DESC_TXBF_PATH_8198F(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)\n#define SET_TX_DESC_PADDING_LEN_8198F(txdesc, value)                           \\\n\tSET_TX_DESC_PADDING_LEN(txdesc, value)\n#define GET_TX_DESC_PADDING_LEN_8198F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)\n#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8198F(txdesc, value)                   \\\n\tSET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)\n#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8198F(txdesc)                          \\\n\tGET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)\n\n/*WORD10*/\n\n#endif\n\n#if (HALMAC_8822C_SUPPORT)\n\n/*TXDESC_WORD0*/\n\n#define SET_TX_DESC_DISQSELSEQ_8822C(txdesc, value)                            \\\n\tSET_TX_DESC_DISQSELSEQ(txdesc, value)\n#define GET_TX_DESC_DISQSELSEQ_8822C(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)\n#define SET_TX_DESC_GF_8822C(txdesc, value) SET_TX_DESC_GF(txdesc, value)\n#define GET_TX_DESC_GF_8822C(txdesc) GET_TX_DESC_GF(txdesc)\n#define SET_TX_DESC_NO_ACM_8822C(txdesc, value)                                \\\n\tSET_TX_DESC_NO_ACM(txdesc, value)\n#define GET_TX_DESC_NO_ACM_8822C(txdesc) GET_TX_DESC_NO_ACM(txdesc)\n#define SET_TX_DESC_BCNPKT_TSF_CTRL_8822C(txdesc, value)                       \\\n\tSET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)\n#define GET_TX_DESC_BCNPKT_TSF_CTRL_8822C(txdesc)                              \\\n\tGET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)\n#define SET_TX_DESC_AMSDU_PAD_EN_8822C(txdesc, value)                          \\\n\tSET_TX_DESC_AMSDU_PAD_EN(txdesc, value)\n#define GET_TX_DESC_AMSDU_PAD_EN_8822C(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)\n#define SET_TX_DESC_LS_8822C(txdesc, value) SET_TX_DESC_LS(txdesc, value)\n#define GET_TX_DESC_LS_8822C(txdesc) GET_TX_DESC_LS(txdesc)\n#define SET_TX_DESC_HTC_8822C(txdesc, value) SET_TX_DESC_HTC(txdesc, value)\n#define GET_TX_DESC_HTC_8822C(txdesc) GET_TX_DESC_HTC(txdesc)\n#define SET_TX_DESC_BMC_8822C(txdesc, value) SET_TX_DESC_BMC(txdesc, value)\n#define GET_TX_DESC_BMC_8822C(txdesc) GET_TX_DESC_BMC(txdesc)\n#define SET_TX_DESC_OFFSET_8822C(txdesc, value)                                \\\n\tSET_TX_DESC_OFFSET(txdesc, value)\n#define GET_TX_DESC_OFFSET_8822C(txdesc) GET_TX_DESC_OFFSET(txdesc)\n#define SET_TX_DESC_TXPKTSIZE_8822C(txdesc, value)                             \\\n\tSET_TX_DESC_TXPKTSIZE(txdesc, value)\n#define GET_TX_DESC_TXPKTSIZE_8822C(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)\n\n/*WORD1*/\n\n#define SET_TX_DESC_MOREDATA_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_MOREDATA(txdesc, value)\n#define GET_TX_DESC_MOREDATA_8822C(txdesc) GET_TX_DESC_MOREDATA(txdesc)\n#define SET_TX_DESC_PKT_OFFSET_8822C(txdesc, value)                            \\\n\tSET_TX_DESC_PKT_OFFSET(txdesc, value)\n#define GET_TX_DESC_PKT_OFFSET_8822C(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)\n#define SET_TX_DESC_SEC_TYPE_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_SEC_TYPE(txdesc, value)\n#define GET_TX_DESC_SEC_TYPE_8822C(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)\n#define SET_TX_DESC_EN_DESC_ID_8822C(txdesc, value)                            \\\n\tSET_TX_DESC_EN_DESC_ID(txdesc, value)\n#define GET_TX_DESC_EN_DESC_ID_8822C(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)\n#define SET_TX_DESC_RATE_ID_8822C(txdesc, value)                               \\\n\tSET_TX_DESC_RATE_ID(txdesc, value)\n#define GET_TX_DESC_RATE_ID_8822C(txdesc) GET_TX_DESC_RATE_ID(txdesc)\n#define SET_TX_DESC_PIFS_8822C(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)\n#define GET_TX_DESC_PIFS_8822C(txdesc) GET_TX_DESC_PIFS(txdesc)\n#define SET_TX_DESC_LSIG_TXOP_EN_8822C(txdesc, value)                          \\\n\tSET_TX_DESC_LSIG_TXOP_EN(txdesc, value)\n#define GET_TX_DESC_LSIG_TXOP_EN_8822C(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)\n#define SET_TX_DESC_RD_NAV_EXT_8822C(txdesc, value)                            \\\n\tSET_TX_DESC_RD_NAV_EXT(txdesc, value)\n#define GET_TX_DESC_RD_NAV_EXT_8822C(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)\n#define SET_TX_DESC_QSEL_8822C(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)\n#define GET_TX_DESC_QSEL_8822C(txdesc) GET_TX_DESC_QSEL(txdesc)\n#define SET_TX_DESC_MACID_8822C(txdesc, value) SET_TX_DESC_MACID(txdesc, value)\n#define GET_TX_DESC_MACID_8822C(txdesc) GET_TX_DESC_MACID(txdesc)\n\n/*TXDESC_WORD2*/\n\n#define SET_TX_DESC_HW_AES_IV_8822C(txdesc, value)                             \\\n\tSET_TX_DESC_HW_AES_IV(txdesc, value)\n#define GET_TX_DESC_HW_AES_IV_8822C(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)\n#define SET_TX_DESC_FTM_EN_8822C(txdesc, value)                                \\\n\tSET_TX_DESC_FTM_EN(txdesc, value)\n#define GET_TX_DESC_FTM_EN_8822C(txdesc) GET_TX_DESC_FTM_EN(txdesc)\n#define SET_TX_DESC_G_ID_8822C(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)\n#define GET_TX_DESC_G_ID_8822C(txdesc) GET_TX_DESC_G_ID(txdesc)\n#define SET_TX_DESC_BT_NULL_8822C(txdesc, value)                               \\\n\tSET_TX_DESC_BT_NULL(txdesc, value)\n#define GET_TX_DESC_BT_NULL_8822C(txdesc) GET_TX_DESC_BT_NULL(txdesc)\n#define SET_TX_DESC_AMPDU_DENSITY_8822C(txdesc, value)                         \\\n\tSET_TX_DESC_AMPDU_DENSITY(txdesc, value)\n#define GET_TX_DESC_AMPDU_DENSITY_8822C(txdesc)                                \\\n\tGET_TX_DESC_AMPDU_DENSITY(txdesc)\n#define SET_TX_DESC_SPE_RPT_8822C(txdesc, value)                               \\\n\tSET_TX_DESC_SPE_RPT(txdesc, value)\n#define GET_TX_DESC_SPE_RPT_8822C(txdesc) GET_TX_DESC_SPE_RPT(txdesc)\n#define SET_TX_DESC_RAW_8822C(txdesc, value) SET_TX_DESC_RAW(txdesc, value)\n#define GET_TX_DESC_RAW_8822C(txdesc) GET_TX_DESC_RAW(txdesc)\n#define SET_TX_DESC_MOREFRAG_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_MOREFRAG(txdesc, value)\n#define GET_TX_DESC_MOREFRAG_8822C(txdesc) GET_TX_DESC_MOREFRAG(txdesc)\n#define SET_TX_DESC_BK_8822C(txdesc, value) SET_TX_DESC_BK(txdesc, value)\n#define GET_TX_DESC_BK_8822C(txdesc) GET_TX_DESC_BK(txdesc)\n#define SET_TX_DESC_NULL_1_8822C(txdesc, value)                                \\\n\tSET_TX_DESC_NULL_1(txdesc, value)\n#define GET_TX_DESC_NULL_1_8822C(txdesc) GET_TX_DESC_NULL_1(txdesc)\n#define SET_TX_DESC_NULL_0_8822C(txdesc, value)                                \\\n\tSET_TX_DESC_NULL_0(txdesc, value)\n#define GET_TX_DESC_NULL_0_8822C(txdesc) GET_TX_DESC_NULL_0(txdesc)\n#define SET_TX_DESC_RDG_EN_8822C(txdesc, value)                                \\\n\tSET_TX_DESC_RDG_EN(txdesc, value)\n#define GET_TX_DESC_RDG_EN_8822C(txdesc) GET_TX_DESC_RDG_EN(txdesc)\n#define SET_TX_DESC_AGG_EN_8822C(txdesc, value)                                \\\n\tSET_TX_DESC_AGG_EN(txdesc, value)\n#define GET_TX_DESC_AGG_EN_8822C(txdesc) GET_TX_DESC_AGG_EN(txdesc)\n#define SET_TX_DESC_CCA_RTS_8822C(txdesc, value)                               \\\n\tSET_TX_DESC_CCA_RTS(txdesc, value)\n#define GET_TX_DESC_CCA_RTS_8822C(txdesc) GET_TX_DESC_CCA_RTS(txdesc)\n#define SET_TX_DESC_TRI_FRAME_8822C(txdesc, value)                             \\\n\tSET_TX_DESC_TRI_FRAME(txdesc, value)\n#define GET_TX_DESC_TRI_FRAME_8822C(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)\n#define SET_TX_DESC_P_AID_8822C(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)\n#define GET_TX_DESC_P_AID_8822C(txdesc) GET_TX_DESC_P_AID(txdesc)\n\n/*TXDESC_WORD3*/\n\n#define SET_TX_DESC_AMPDU_MAX_TIME_8822C(txdesc, value)                        \\\n\tSET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)\n#define GET_TX_DESC_AMPDU_MAX_TIME_8822C(txdesc)                               \\\n\tGET_TX_DESC_AMPDU_MAX_TIME(txdesc)\n#define SET_TX_DESC_NDPA_8822C(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)\n#define GET_TX_DESC_NDPA_8822C(txdesc) GET_TX_DESC_NDPA(txdesc)\n#define SET_TX_DESC_MAX_AGG_NUM_8822C(txdesc, value)                           \\\n\tSET_TX_DESC_MAX_AGG_NUM(txdesc, value)\n#define GET_TX_DESC_MAX_AGG_NUM_8822C(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)\n#define SET_TX_DESC_USE_MAX_TIME_EN_8822C(txdesc, value)                       \\\n\tSET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)\n#define GET_TX_DESC_USE_MAX_TIME_EN_8822C(txdesc)                              \\\n\tGET_TX_DESC_USE_MAX_TIME_EN(txdesc)\n#define SET_TX_DESC_NAVUSEHDR_8822C(txdesc, value)                             \\\n\tSET_TX_DESC_NAVUSEHDR(txdesc, value)\n#define GET_TX_DESC_NAVUSEHDR_8822C(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)\n#define SET_TX_DESC_CHK_EN_8822C(txdesc, value)                                \\\n\tSET_TX_DESC_CHK_EN(txdesc, value)\n#define GET_TX_DESC_CHK_EN_8822C(txdesc) GET_TX_DESC_CHK_EN(txdesc)\n#define SET_TX_DESC_HW_RTS_EN_8822C(txdesc, value)                             \\\n\tSET_TX_DESC_HW_RTS_EN(txdesc, value)\n#define GET_TX_DESC_HW_RTS_EN_8822C(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)\n#define SET_TX_DESC_RTSEN_8822C(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)\n#define GET_TX_DESC_RTSEN_8822C(txdesc) GET_TX_DESC_RTSEN(txdesc)\n#define SET_TX_DESC_CTS2SELF_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_CTS2SELF(txdesc, value)\n#define GET_TX_DESC_CTS2SELF_8822C(txdesc) GET_TX_DESC_CTS2SELF(txdesc)\n#define SET_TX_DESC_DISDATAFB_8822C(txdesc, value)                             \\\n\tSET_TX_DESC_DISDATAFB(txdesc, value)\n#define GET_TX_DESC_DISDATAFB_8822C(txdesc) GET_TX_DESC_DISDATAFB(txdesc)\n#define SET_TX_DESC_DISRTSFB_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_DISRTSFB(txdesc, value)\n#define GET_TX_DESC_DISRTSFB_8822C(txdesc) GET_TX_DESC_DISRTSFB(txdesc)\n#define SET_TX_DESC_USE_RATE_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_USE_RATE(txdesc, value)\n#define GET_TX_DESC_USE_RATE_8822C(txdesc) GET_TX_DESC_USE_RATE(txdesc)\n#define SET_TX_DESC_HW_SSN_SEL_8822C(txdesc, value)                            \\\n\tSET_TX_DESC_HW_SSN_SEL(txdesc, value)\n#define GET_TX_DESC_HW_SSN_SEL_8822C(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)\n#define SET_TX_DESC_WHEADER_LEN_8822C(txdesc, value)                           \\\n\tSET_TX_DESC_WHEADER_LEN(txdesc, value)\n#define GET_TX_DESC_WHEADER_LEN_8822C(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)\n\n/*TXDESC_WORD4*/\n\n#define SET_TX_DESC_PCTS_MASK_IDX_8822C(txdesc, value)                         \\\n\tSET_TX_DESC_PCTS_MASK_IDX(txdesc, value)\n#define GET_TX_DESC_PCTS_MASK_IDX_8822C(txdesc)                                \\\n\tGET_TX_DESC_PCTS_MASK_IDX(txdesc)\n#define SET_TX_DESC_PCTS_EN_8822C(txdesc, value)                               \\\n\tSET_TX_DESC_PCTS_EN(txdesc, value)\n#define GET_TX_DESC_PCTS_EN_8822C(txdesc) GET_TX_DESC_PCTS_EN(txdesc)\n#define SET_TX_DESC_RTSRATE_8822C(txdesc, value)                               \\\n\tSET_TX_DESC_RTSRATE(txdesc, value)\n#define GET_TX_DESC_RTSRATE_8822C(txdesc) GET_TX_DESC_RTSRATE(txdesc)\n#define SET_TX_DESC_RTS_DATA_RTY_LMT_8822C(txdesc, value)                      \\\n\tSET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)\n#define GET_TX_DESC_RTS_DATA_RTY_LMT_8822C(txdesc)                             \\\n\tGET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)\n#define SET_TX_DESC_RTY_LMT_EN_8822C(txdesc, value)                            \\\n\tSET_TX_DESC_RTY_LMT_EN(txdesc, value)\n#define GET_TX_DESC_RTY_LMT_EN_8822C(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)\n#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822C(txdesc, value)                   \\\n\tSET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8822C(txdesc)                          \\\n\tGET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)\n#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822C(txdesc, value)                  \\\n\tSET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8822C(txdesc)                         \\\n\tGET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)\n#define SET_TX_DESC_TRY_RATE_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_TRY_RATE(txdesc, value)\n#define GET_TX_DESC_TRY_RATE_8822C(txdesc) GET_TX_DESC_TRY_RATE(txdesc)\n#define SET_TX_DESC_DATARATE_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_DATARATE(txdesc, value)\n#define GET_TX_DESC_DATARATE_8822C(txdesc) GET_TX_DESC_DATARATE(txdesc)\n\n/*TXDESC_WORD5*/\n\n#define SET_TX_DESC_POLLUTED_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_POLLUTED(txdesc, value)\n#define GET_TX_DESC_POLLUTED_8822C(txdesc) GET_TX_DESC_POLLUTED(txdesc)\n#define SET_TX_DESC_ANTSEL_EN_8822C(txdesc, value)                             \\\n\tSET_TX_DESC_ANTSEL_EN_V1(txdesc, value)\n#define GET_TX_DESC_ANTSEL_EN_8822C(txdesc) GET_TX_DESC_ANTSEL_EN_V1(txdesc)\n#define SET_TX_DESC_TXPWR_OFSET_TYPE_8822C(txdesc, value)                      \\\n\tSET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value)\n#define GET_TX_DESC_TXPWR_OFSET_TYPE_8822C(txdesc)                             \\\n\tGET_TX_DESC_TXPWR_OFSET_TYPE(txdesc)\n#define SET_TX_DESC_TX_ANT_8822C(txdesc, value)                                \\\n\tSET_TX_DESC_TX_ANT(txdesc, value)\n#define GET_TX_DESC_TX_ANT_8822C(txdesc) GET_TX_DESC_TX_ANT(txdesc)\n#define SET_TX_DESC_PORT_ID_8822C(txdesc, value)                               \\\n\tSET_TX_DESC_PORT_ID(txdesc, value)\n#define GET_TX_DESC_PORT_ID_8822C(txdesc) GET_TX_DESC_PORT_ID(txdesc)\n#define SET_TX_DESC_MULTIPLE_PORT_8822C(txdesc, value)                         \\\n\tSET_TX_DESC_MULTIPLE_PORT(txdesc, value)\n#define GET_TX_DESC_MULTIPLE_PORT_8822C(txdesc)                                \\\n\tGET_TX_DESC_MULTIPLE_PORT(txdesc)\n#define SET_TX_DESC_SIGNALING_TAPKT_EN_8822C(txdesc, value)                    \\\n\tSET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)\n#define GET_TX_DESC_SIGNALING_TAPKT_EN_8822C(txdesc)                           \\\n\tGET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)\n#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8822C(txdesc, value)                   \\\n\tSET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)\n#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8822C(txdesc)                          \\\n\tGET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)\n#define SET_TX_DESC_RTS_SHORT_8822C(txdesc, value)                             \\\n\tSET_TX_DESC_RTS_SHORT(txdesc, value)\n#define GET_TX_DESC_RTS_SHORT_8822C(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)\n#define SET_TX_DESC_VCS_STBC_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_VCS_STBC(txdesc, value)\n#define GET_TX_DESC_VCS_STBC_8822C(txdesc) GET_TX_DESC_VCS_STBC(txdesc)\n#define SET_TX_DESC_DATA_STBC_8822C(txdesc, value)                             \\\n\tSET_TX_DESC_DATA_STBC(txdesc, value)\n#define GET_TX_DESC_DATA_STBC_8822C(txdesc) GET_TX_DESC_DATA_STBC(txdesc)\n#define SET_TX_DESC_DATA_LDPC_8822C(txdesc, value)                             \\\n\tSET_TX_DESC_DATA_LDPC(txdesc, value)\n#define GET_TX_DESC_DATA_LDPC_8822C(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)\n#define SET_TX_DESC_DATA_BW_8822C(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_BW(txdesc, value)\n#define GET_TX_DESC_DATA_BW_8822C(txdesc) GET_TX_DESC_DATA_BW(txdesc)\n#define SET_TX_DESC_DATA_SHORT_8822C(txdesc, value)                            \\\n\tSET_TX_DESC_DATA_SHORT(txdesc, value)\n#define GET_TX_DESC_DATA_SHORT_8822C(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)\n#define SET_TX_DESC_DATA_SC_8822C(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_SC(txdesc, value)\n#define GET_TX_DESC_DATA_SC_8822C(txdesc) GET_TX_DESC_DATA_SC(txdesc)\n\n/*TXDESC_WORD6*/\n\n#define SET_TX_DESC_ANTSEL_D_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_D(txdesc, value)\n#define GET_TX_DESC_ANTSEL_D_8822C(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)\n#define SET_TX_DESC_ANT_MAPD_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPD(txdesc, value)\n#define GET_TX_DESC_ANT_MAPD_8822C(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)\n#define SET_TX_DESC_ANT_MAPC_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPC(txdesc, value)\n#define GET_TX_DESC_ANT_MAPC_8822C(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)\n#define SET_TX_DESC_ANT_MAPB_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPB(txdesc, value)\n#define GET_TX_DESC_ANT_MAPB_8822C(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)\n#define SET_TX_DESC_ANT_MAPA_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPA(txdesc, value)\n#define GET_TX_DESC_ANT_MAPA_8822C(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)\n#define SET_TX_DESC_ANTSEL_C_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_C(txdesc, value)\n#define GET_TX_DESC_ANTSEL_C_8822C(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)\n#define SET_TX_DESC_ANTSEL_B_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_B(txdesc, value)\n#define GET_TX_DESC_ANTSEL_B_8822C(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)\n#define SET_TX_DESC_ANTSEL_A_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_A(txdesc, value)\n#define GET_TX_DESC_ANTSEL_A_8822C(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)\n#define SET_TX_DESC_MBSSID_8822C(txdesc, value)                                \\\n\tSET_TX_DESC_MBSSID(txdesc, value)\n#define GET_TX_DESC_MBSSID_8822C(txdesc) GET_TX_DESC_MBSSID(txdesc)\n#define SET_TX_DESC_SW_DEFINE_8822C(txdesc, value)                             \\\n\tSET_TX_DESC_SW_DEFINE(txdesc, value)\n#define GET_TX_DESC_SW_DEFINE_8822C(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)\n\n/*TXDESC_WORD7*/\n\n#define SET_TX_DESC_DMA_TXAGG_NUM_8822C(txdesc, value)                         \\\n\tSET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)\n#define GET_TX_DESC_DMA_TXAGG_NUM_8822C(txdesc)                                \\\n\tGET_TX_DESC_DMA_TXAGG_NUM(txdesc)\n#define SET_TX_DESC_FINAL_DATA_RATE_8822C(txdesc, value)                       \\\n\tSET_TX_DESC_FINAL_DATA_RATE(txdesc, value)\n#define GET_TX_DESC_FINAL_DATA_RATE_8822C(txdesc)                              \\\n\tGET_TX_DESC_FINAL_DATA_RATE(txdesc)\n#define SET_TX_DESC_NTX_MAP_8822C(txdesc, value)                               \\\n\tSET_TX_DESC_NTX_MAP(txdesc, value)\n#define GET_TX_DESC_NTX_MAP_8822C(txdesc) GET_TX_DESC_NTX_MAP(txdesc)\n#define SET_TX_DESC_TX_BUFF_SIZE_8822C(txdesc, value)                          \\\n\tSET_TX_DESC_TX_BUFF_SIZE(txdesc, value)\n#define GET_TX_DESC_TX_BUFF_SIZE_8822C(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)\n#define SET_TX_DESC_TXDESC_CHECKSUM_8822C(txdesc, value)                       \\\n\tSET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)\n#define GET_TX_DESC_TXDESC_CHECKSUM_8822C(txdesc)                              \\\n\tGET_TX_DESC_TXDESC_CHECKSUM(txdesc)\n#define SET_TX_DESC_TIMESTAMP_8822C(txdesc, value)                             \\\n\tSET_TX_DESC_TIMESTAMP(txdesc, value)\n#define GET_TX_DESC_TIMESTAMP_8822C(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)\n\n/*TXDESC_WORD8*/\n\n#define SET_TX_DESC_TXWIFI_CP_8822C(txdesc, value)                             \\\n\tSET_TX_DESC_TXWIFI_CP(txdesc, value)\n#define GET_TX_DESC_TXWIFI_CP_8822C(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)\n#define SET_TX_DESC_MAC_CP_8822C(txdesc, value)                                \\\n\tSET_TX_DESC_MAC_CP(txdesc, value)\n#define GET_TX_DESC_MAC_CP_8822C(txdesc) GET_TX_DESC_MAC_CP(txdesc)\n#define SET_TX_DESC_STW_PKTRE_DIS_8822C(txdesc, value)                         \\\n\tSET_TX_DESC_STW_PKTRE_DIS(txdesc, value)\n#define GET_TX_DESC_STW_PKTRE_DIS_8822C(txdesc)                                \\\n\tGET_TX_DESC_STW_PKTRE_DIS(txdesc)\n#define SET_TX_DESC_STW_RB_DIS_8822C(txdesc, value)                            \\\n\tSET_TX_DESC_STW_RB_DIS(txdesc, value)\n#define GET_TX_DESC_STW_RB_DIS_8822C(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)\n#define SET_TX_DESC_STW_RATE_DIS_8822C(txdesc, value)                          \\\n\tSET_TX_DESC_STW_RATE_DIS(txdesc, value)\n#define GET_TX_DESC_STW_RATE_DIS_8822C(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)\n#define SET_TX_DESC_STW_ANT_DIS_8822C(txdesc, value)                           \\\n\tSET_TX_DESC_STW_ANT_DIS(txdesc, value)\n#define GET_TX_DESC_STW_ANT_DIS_8822C(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)\n#define SET_TX_DESC_STW_EN_8822C(txdesc, value)                                \\\n\tSET_TX_DESC_STW_EN(txdesc, value)\n#define GET_TX_DESC_STW_EN_8822C(txdesc) GET_TX_DESC_STW_EN(txdesc)\n#define SET_TX_DESC_SMH_EN_8822C(txdesc, value)                                \\\n\tSET_TX_DESC_SMH_EN(txdesc, value)\n#define GET_TX_DESC_SMH_EN_8822C(txdesc) GET_TX_DESC_SMH_EN(txdesc)\n#define SET_TX_DESC_TAILPAGE_L_8822C(txdesc, value)                            \\\n\tSET_TX_DESC_TAILPAGE_L(txdesc, value)\n#define GET_TX_DESC_TAILPAGE_L_8822C(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)\n#define SET_TX_DESC_SDIO_DMASEQ_8822C(txdesc, value)                           \\\n\tSET_TX_DESC_SDIO_DMASEQ(txdesc, value)\n#define GET_TX_DESC_SDIO_DMASEQ_8822C(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)\n#define SET_TX_DESC_NEXTHEADPAGE_L_8822C(txdesc, value)                        \\\n\tSET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)\n#define GET_TX_DESC_NEXTHEADPAGE_L_8822C(txdesc)                               \\\n\tGET_TX_DESC_NEXTHEADPAGE_L(txdesc)\n#define SET_TX_DESC_EN_HWSEQ_8822C(txdesc, value)                              \\\n\tSET_TX_DESC_EN_HWSEQ(txdesc, value)\n#define GET_TX_DESC_EN_HWSEQ_8822C(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)\n#define SET_TX_DESC_EN_HWEXSEQ_8822C(txdesc, value)                            \\\n\tSET_TX_DESC_EN_HWEXSEQ(txdesc, value)\n#define GET_TX_DESC_EN_HWEXSEQ_8822C(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)\n#define SET_TX_DESC_DATA_RC_8822C(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_RC(txdesc, value)\n#define GET_TX_DESC_DATA_RC_8822C(txdesc) GET_TX_DESC_DATA_RC(txdesc)\n#define SET_TX_DESC_BAR_RTY_TH_8822C(txdesc, value)                            \\\n\tSET_TX_DESC_BAR_RTY_TH(txdesc, value)\n#define GET_TX_DESC_BAR_RTY_TH_8822C(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)\n#define SET_TX_DESC_RTS_RC_8822C(txdesc, value)                                \\\n\tSET_TX_DESC_RTS_RC(txdesc, value)\n#define GET_TX_DESC_RTS_RC_8822C(txdesc) GET_TX_DESC_RTS_RC(txdesc)\n\n/*TXDESC_WORD9*/\n\n#define SET_TX_DESC_TAILPAGE_H_8822C(txdesc, value)                            \\\n\tSET_TX_DESC_TAILPAGE_H(txdesc, value)\n#define GET_TX_DESC_TAILPAGE_H_8822C(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)\n#define SET_TX_DESC_NEXTHEADPAGE_H_8822C(txdesc, value)                        \\\n\tSET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)\n#define GET_TX_DESC_NEXTHEADPAGE_H_8822C(txdesc)                               \\\n\tGET_TX_DESC_NEXTHEADPAGE_H(txdesc)\n#define SET_TX_DESC_SW_SEQ_8822C(txdesc, value)                                \\\n\tSET_TX_DESC_SW_SEQ(txdesc, value)\n#define GET_TX_DESC_SW_SEQ_8822C(txdesc) GET_TX_DESC_SW_SEQ(txdesc)\n#define SET_TX_DESC_TXBF_PATH_8822C(txdesc, value)                             \\\n\tSET_TX_DESC_TXBF_PATH(txdesc, value)\n#define GET_TX_DESC_TXBF_PATH_8822C(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)\n#define SET_TX_DESC_PADDING_LEN_8822C(txdesc, value)                           \\\n\tSET_TX_DESC_PADDING_LEN(txdesc, value)\n#define GET_TX_DESC_PADDING_LEN_8822C(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)\n#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8822C(txdesc, value)                   \\\n\tSET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)\n#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8822C(txdesc)                          \\\n\tGET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)\n\n/*WORD10*/\n\n#define SET_TX_DESC_MU_DATARATE_8822C(txdesc, value)                           \\\n\tSET_TX_DESC_MU_DATARATE(txdesc, value)\n#define GET_TX_DESC_MU_DATARATE_8822C(txdesc) GET_TX_DESC_MU_DATARATE(txdesc)\n#define SET_TX_DESC_MU_RC_8822C(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value)\n#define GET_TX_DESC_MU_RC_8822C(txdesc) GET_TX_DESC_MU_RC(txdesc)\n#define SET_TX_DESC_SND_PKT_SEL_8822C(txdesc, value)                           \\\n\tSET_TX_DESC_SND_PKT_SEL(txdesc, value)\n#define GET_TX_DESC_SND_PKT_SEL_8822C(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n/*TXDESC_WORD0*/\n\n#define SET_TX_DESC_GF_8192F(txdesc, value) SET_TX_DESC_GF(txdesc, value)\n#define GET_TX_DESC_GF_8192F(txdesc) GET_TX_DESC_GF(txdesc)\n#define SET_TX_DESC_NO_ACM_8192F(txdesc, value)                                \\\n\tSET_TX_DESC_NO_ACM(txdesc, value)\n#define GET_TX_DESC_NO_ACM_8192F(txdesc) GET_TX_DESC_NO_ACM(txdesc)\n#define SET_TX_DESC_AMSDU_PAD_EN_8192F(txdesc, value)                          \\\n\tSET_TX_DESC_AMSDU_PAD_EN(txdesc, value)\n#define GET_TX_DESC_AMSDU_PAD_EN_8192F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)\n#define SET_TX_DESC_HTC_8192F(txdesc, value) SET_TX_DESC_HTC(txdesc, value)\n#define GET_TX_DESC_HTC_8192F(txdesc) GET_TX_DESC_HTC(txdesc)\n#define SET_TX_DESC_BMC_8192F(txdesc, value) SET_TX_DESC_BMC(txdesc, value)\n#define GET_TX_DESC_BMC_8192F(txdesc) GET_TX_DESC_BMC(txdesc)\n#define SET_TX_DESC_OFFSET_8192F(txdesc, value)                                \\\n\tSET_TX_DESC_OFFSET(txdesc, value)\n#define GET_TX_DESC_OFFSET_8192F(txdesc) GET_TX_DESC_OFFSET(txdesc)\n#define SET_TX_DESC_TXPKTSIZE_8192F(txdesc, value)                             \\\n\tSET_TX_DESC_TXPKTSIZE(txdesc, value)\n#define GET_TX_DESC_TXPKTSIZE_8192F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)\n\n/*WORD1*/\n\n#define SET_TX_DESC_KEYID_SEL_8192F(txdesc, value)                             \\\n\tSET_TX_DESC_KEYID_SEL(txdesc, value)\n#define GET_TX_DESC_KEYID_SEL_8192F(txdesc) GET_TX_DESC_KEYID_SEL(txdesc)\n#define SET_TX_DESC_MOREDATA_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_MOREDATA(txdesc, value)\n#define GET_TX_DESC_MOREDATA_8192F(txdesc) GET_TX_DESC_MOREDATA(txdesc)\n#define SET_TX_DESC_PKT_OFFSET_8192F(txdesc, value)                            \\\n\tSET_TX_DESC_PKT_OFFSET(txdesc, value)\n#define GET_TX_DESC_PKT_OFFSET_8192F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)\n#define SET_TX_DESC_SEC_TYPE_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_SEC_TYPE(txdesc, value)\n#define GET_TX_DESC_SEC_TYPE_8192F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)\n#define SET_TX_DESC_EN_DESC_ID_8192F(txdesc, value)                            \\\n\tSET_TX_DESC_EN_DESC_ID(txdesc, value)\n#define GET_TX_DESC_EN_DESC_ID_8192F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)\n#define SET_TX_DESC_RATE_ID_8192F(txdesc, value)                               \\\n\tSET_TX_DESC_RATE_ID(txdesc, value)\n#define GET_TX_DESC_RATE_ID_8192F(txdesc) GET_TX_DESC_RATE_ID(txdesc)\n#define SET_TX_DESC_PIFS_8192F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)\n#define GET_TX_DESC_PIFS_8192F(txdesc) GET_TX_DESC_PIFS(txdesc)\n#define SET_TX_DESC_LSIG_TXOP_EN_8192F(txdesc, value)                          \\\n\tSET_TX_DESC_LSIG_TXOP_EN(txdesc, value)\n#define GET_TX_DESC_LSIG_TXOP_EN_8192F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)\n#define SET_TX_DESC_RD_NAV_EXT_8192F(txdesc, value)                            \\\n\tSET_TX_DESC_RD_NAV_EXT(txdesc, value)\n#define GET_TX_DESC_RD_NAV_EXT_8192F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)\n#define SET_TX_DESC_QSEL_8192F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)\n#define GET_TX_DESC_QSEL_8192F(txdesc) GET_TX_DESC_QSEL(txdesc)\n#define SET_TX_DESC_MACID_8192F(txdesc, value) SET_TX_DESC_MACID(txdesc, value)\n#define GET_TX_DESC_MACID_8192F(txdesc) GET_TX_DESC_MACID(txdesc)\n\n/*TXDESC_WORD2*/\n\n#define SET_TX_DESC_FTM_EN_8192F(txdesc, value)                                \\\n\tSET_TX_DESC_FTM_EN(txdesc, value)\n#define GET_TX_DESC_FTM_EN_8192F(txdesc) GET_TX_DESC_FTM_EN(txdesc)\n#define SET_TX_DESC_G_ID_8192F(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)\n#define GET_TX_DESC_G_ID_8192F(txdesc) GET_TX_DESC_G_ID(txdesc)\n#define SET_TX_DESC_BT_NULL_8192F(txdesc, value)                               \\\n\tSET_TX_DESC_BT_NULL(txdesc, value)\n#define GET_TX_DESC_BT_NULL_8192F(txdesc) GET_TX_DESC_BT_NULL(txdesc)\n#define SET_TX_DESC_AMPDU_DENSITY_8192F(txdesc, value)                         \\\n\tSET_TX_DESC_AMPDU_DENSITY(txdesc, value)\n#define GET_TX_DESC_AMPDU_DENSITY_8192F(txdesc)                                \\\n\tGET_TX_DESC_AMPDU_DENSITY(txdesc)\n#define SET_TX_DESC_SPE_RPT_8192F(txdesc, value)                               \\\n\tSET_TX_DESC_SPE_RPT(txdesc, value)\n#define GET_TX_DESC_SPE_RPT_8192F(txdesc) GET_TX_DESC_SPE_RPT(txdesc)\n#define SET_TX_DESC_RAW_8192F(txdesc, value) SET_TX_DESC_RAW(txdesc, value)\n#define GET_TX_DESC_RAW_8192F(txdesc) GET_TX_DESC_RAW(txdesc)\n#define SET_TX_DESC_MOREFRAG_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_MOREFRAG(txdesc, value)\n#define GET_TX_DESC_MOREFRAG_8192F(txdesc) GET_TX_DESC_MOREFRAG(txdesc)\n#define SET_TX_DESC_BK_8192F(txdesc, value) SET_TX_DESC_BK(txdesc, value)\n#define GET_TX_DESC_BK_8192F(txdesc) GET_TX_DESC_BK(txdesc)\n#define SET_TX_DESC_NULL_1_8192F(txdesc, value)                                \\\n\tSET_TX_DESC_NULL_1(txdesc, value)\n#define GET_TX_DESC_NULL_1_8192F(txdesc) GET_TX_DESC_NULL_1(txdesc)\n#define SET_TX_DESC_NULL_0_8192F(txdesc, value)                                \\\n\tSET_TX_DESC_NULL_0(txdesc, value)\n#define GET_TX_DESC_NULL_0_8192F(txdesc) GET_TX_DESC_NULL_0(txdesc)\n#define SET_TX_DESC_RDG_EN_8192F(txdesc, value)                                \\\n\tSET_TX_DESC_RDG_EN(txdesc, value)\n#define GET_TX_DESC_RDG_EN_8192F(txdesc) GET_TX_DESC_RDG_EN(txdesc)\n#define SET_TX_DESC_AGG_EN_8192F(txdesc, value)                                \\\n\tSET_TX_DESC_AGG_EN(txdesc, value)\n#define GET_TX_DESC_AGG_EN_8192F(txdesc) GET_TX_DESC_AGG_EN(txdesc)\n#define SET_TX_DESC_CCA_RTS_8192F(txdesc, value)                               \\\n\tSET_TX_DESC_CCA_RTS(txdesc, value)\n#define GET_TX_DESC_CCA_RTS_8192F(txdesc) GET_TX_DESC_CCA_RTS(txdesc)\n#define SET_TX_DESC_TRI_FRAME_8192F(txdesc, value)                             \\\n\tSET_TX_DESC_TRI_FRAME(txdesc, value)\n#define GET_TX_DESC_TRI_FRAME_8192F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)\n#define SET_TX_DESC_P_AID_8192F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)\n#define GET_TX_DESC_P_AID_8192F(txdesc) GET_TX_DESC_P_AID(txdesc)\n\n/*TXDESC_WORD3*/\n\n#define SET_TX_DESC_AMPDU_MAX_TIME_8192F(txdesc, value)                        \\\n\tSET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)\n#define GET_TX_DESC_AMPDU_MAX_TIME_8192F(txdesc)                               \\\n\tGET_TX_DESC_AMPDU_MAX_TIME(txdesc)\n#define SET_TX_DESC_NDPA_8192F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)\n#define GET_TX_DESC_NDPA_8192F(txdesc) GET_TX_DESC_NDPA(txdesc)\n#define SET_TX_DESC_MAX_AGG_NUM_8192F(txdesc, value)                           \\\n\tSET_TX_DESC_MAX_AGG_NUM(txdesc, value)\n#define GET_TX_DESC_MAX_AGG_NUM_8192F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)\n#define SET_TX_DESC_USE_MAX_TIME_EN_8192F(txdesc, value)                       \\\n\tSET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)\n#define GET_TX_DESC_USE_MAX_TIME_EN_8192F(txdesc)                              \\\n\tGET_TX_DESC_USE_MAX_TIME_EN(txdesc)\n#define SET_TX_DESC_NAVUSEHDR_8192F(txdesc, value)                             \\\n\tSET_TX_DESC_NAVUSEHDR(txdesc, value)\n#define GET_TX_DESC_NAVUSEHDR_8192F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)\n#define SET_TX_DESC_CHK_EN_8192F(txdesc, value)                                \\\n\tSET_TX_DESC_CHK_EN(txdesc, value)\n#define GET_TX_DESC_CHK_EN_8192F(txdesc) GET_TX_DESC_CHK_EN(txdesc)\n#define SET_TX_DESC_HW_RTS_EN_8192F(txdesc, value)                             \\\n\tSET_TX_DESC_HW_RTS_EN(txdesc, value)\n#define GET_TX_DESC_HW_RTS_EN_8192F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)\n#define SET_TX_DESC_RTSEN_8192F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)\n#define GET_TX_DESC_RTSEN_8192F(txdesc) GET_TX_DESC_RTSEN(txdesc)\n#define SET_TX_DESC_CTS2SELF_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_CTS2SELF(txdesc, value)\n#define GET_TX_DESC_CTS2SELF_8192F(txdesc) GET_TX_DESC_CTS2SELF(txdesc)\n#define SET_TX_DESC_DISDATAFB_8192F(txdesc, value)                             \\\n\tSET_TX_DESC_DISDATAFB(txdesc, value)\n#define GET_TX_DESC_DISDATAFB_8192F(txdesc) GET_TX_DESC_DISDATAFB(txdesc)\n#define SET_TX_DESC_DISRTSFB_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_DISRTSFB(txdesc, value)\n#define GET_TX_DESC_DISRTSFB_8192F(txdesc) GET_TX_DESC_DISRTSFB(txdesc)\n#define SET_TX_DESC_USE_RATE_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_USE_RATE(txdesc, value)\n#define GET_TX_DESC_USE_RATE_8192F(txdesc) GET_TX_DESC_USE_RATE(txdesc)\n#define SET_TX_DESC_HW_SSN_SEL_8192F(txdesc, value)                            \\\n\tSET_TX_DESC_HW_SSN_SEL(txdesc, value)\n#define GET_TX_DESC_HW_SSN_SEL_8192F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)\n#define SET_TX_DESC_WHEADER_LEN_8192F(txdesc, value)                           \\\n\tSET_TX_DESC_WHEADER_LEN(txdesc, value)\n#define GET_TX_DESC_WHEADER_LEN_8192F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)\n\n/*TXDESC_WORD4*/\n\n#define SET_TX_DESC_PCTS_MASK_IDX_8192F(txdesc, value)                         \\\n\tSET_TX_DESC_PCTS_MASK_IDX(txdesc, value)\n#define GET_TX_DESC_PCTS_MASK_IDX_8192F(txdesc)                                \\\n\tGET_TX_DESC_PCTS_MASK_IDX(txdesc)\n#define SET_TX_DESC_PCTS_EN_8192F(txdesc, value)                               \\\n\tSET_TX_DESC_PCTS_EN(txdesc, value)\n#define GET_TX_DESC_PCTS_EN_8192F(txdesc) GET_TX_DESC_PCTS_EN(txdesc)\n#define SET_TX_DESC_RTSRATE_8192F(txdesc, value)                               \\\n\tSET_TX_DESC_RTSRATE(txdesc, value)\n#define GET_TX_DESC_RTSRATE_8192F(txdesc) GET_TX_DESC_RTSRATE(txdesc)\n#define SET_TX_DESC_RTS_DATA_RTY_LMT_8192F(txdesc, value)                      \\\n\tSET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)\n#define GET_TX_DESC_RTS_DATA_RTY_LMT_8192F(txdesc)                             \\\n\tGET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)\n#define SET_TX_DESC_RTY_LMT_EN_8192F(txdesc, value)                            \\\n\tSET_TX_DESC_RTY_LMT_EN(txdesc, value)\n#define GET_TX_DESC_RTY_LMT_EN_8192F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)\n#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8192F(txdesc, value)                   \\\n\tSET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8192F(txdesc)                          \\\n\tGET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)\n#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8192F(txdesc, value)                  \\\n\tSET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8192F(txdesc)                         \\\n\tGET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)\n#define SET_TX_DESC_TRY_RATE_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_TRY_RATE(txdesc, value)\n#define GET_TX_DESC_TRY_RATE_8192F(txdesc) GET_TX_DESC_TRY_RATE(txdesc)\n#define SET_TX_DESC_DATARATE_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_DATARATE(txdesc, value)\n#define GET_TX_DESC_DATARATE_8192F(txdesc) GET_TX_DESC_DATARATE(txdesc)\n\n/*TXDESC_WORD5*/\n\n#define SET_TX_DESC_POLLUTED_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_POLLUTED(txdesc, value)\n#define GET_TX_DESC_POLLUTED_8192F(txdesc) GET_TX_DESC_POLLUTED(txdesc)\n#define SET_TX_DESC_TXPWR_OFSET_TYPE_8192F(txdesc, value)                      \\\n\tSET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc, value)\n#define GET_TX_DESC_TXPWR_OFSET_TYPE_8192F(txdesc)                             \\\n\tGET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc)\n#define SET_TX_DESC_TX_ANT_8192F(txdesc, value)                                \\\n\tSET_TX_DESC_TX_ANT(txdesc, value)\n#define GET_TX_DESC_TX_ANT_8192F(txdesc) GET_TX_DESC_TX_ANT(txdesc)\n#define SET_TX_DESC_DROP_ID_8192F(txdesc, value)                               \\\n\tSET_TX_DESC_DROP_ID_V1(txdesc, value)\n#define GET_TX_DESC_DROP_ID_8192F(txdesc) GET_TX_DESC_DROP_ID_V1(txdesc)\n#define SET_TX_DESC_PORT_ID_8192F(txdesc, value)                               \\\n\tSET_TX_DESC_PORT_ID_V1(txdesc, value)\n#define GET_TX_DESC_PORT_ID_8192F(txdesc) GET_TX_DESC_PORT_ID_V1(txdesc)\n#define SET_TX_DESC_RTS_SC_8192F(txdesc, value)                                \\\n\tSET_TX_DESC_RTS_SC(txdesc, value)\n#define GET_TX_DESC_RTS_SC_8192F(txdesc) GET_TX_DESC_RTS_SC(txdesc)\n#define SET_TX_DESC_RTS_SHORT_8192F(txdesc, value)                             \\\n\tSET_TX_DESC_RTS_SHORT(txdesc, value)\n#define GET_TX_DESC_RTS_SHORT_8192F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)\n#define SET_TX_DESC_VCS_STBC_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_VCS_STBC(txdesc, value)\n#define GET_TX_DESC_VCS_STBC_8192F(txdesc) GET_TX_DESC_VCS_STBC(txdesc)\n#define SET_TX_DESC_DATA_STBC_8192F(txdesc, value)                             \\\n\tSET_TX_DESC_DATA_STBC(txdesc, value)\n#define GET_TX_DESC_DATA_STBC_8192F(txdesc) GET_TX_DESC_DATA_STBC(txdesc)\n#define SET_TX_DESC_DATA_LDPC_8192F(txdesc, value)                             \\\n\tSET_TX_DESC_DATA_LDPC(txdesc, value)\n#define GET_TX_DESC_DATA_LDPC_8192F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)\n#define SET_TX_DESC_DATA_BW_8192F(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_BW(txdesc, value)\n#define GET_TX_DESC_DATA_BW_8192F(txdesc) GET_TX_DESC_DATA_BW(txdesc)\n#define SET_TX_DESC_DATA_SHORT_8192F(txdesc, value)                            \\\n\tSET_TX_DESC_DATA_SHORT(txdesc, value)\n#define GET_TX_DESC_DATA_SHORT_8192F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)\n#define SET_TX_DESC_DATA_SC_8192F(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_SC(txdesc, value)\n#define GET_TX_DESC_DATA_SC_8192F(txdesc) GET_TX_DESC_DATA_SC(txdesc)\n\n/*TXDESC_WORD6*/\n\n#define SET_TX_DESC_ANT_MAPC_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPC_V2(txdesc, value)\n#define GET_TX_DESC_ANT_MAPC_8192F(txdesc) GET_TX_DESC_ANT_MAPC_V2(txdesc)\n#define SET_TX_DESC_ANT_MAPB_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPB_V2(txdesc, value)\n#define GET_TX_DESC_ANT_MAPB_8192F(txdesc) GET_TX_DESC_ANT_MAPB_V2(txdesc)\n#define SET_TX_DESC_ANT_MAPA_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPA_V2(txdesc, value)\n#define GET_TX_DESC_ANT_MAPA_8192F(txdesc) GET_TX_DESC_ANT_MAPA_V2(txdesc)\n#define SET_TX_DESC_ANTSEL_D_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_D_V1(txdesc, value)\n#define GET_TX_DESC_ANTSEL_D_8192F(txdesc) GET_TX_DESC_ANTSEL_D_V1(txdesc)\n#define SET_TX_DESC_ANTSEL_C_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_C_V2(txdesc, value)\n#define GET_TX_DESC_ANTSEL_C_8192F(txdesc) GET_TX_DESC_ANTSEL_C_V2(txdesc)\n#define SET_TX_DESC_ANTSEL_B_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_B_V2(txdesc, value)\n#define GET_TX_DESC_ANTSEL_B_8192F(txdesc) GET_TX_DESC_ANTSEL_B_V2(txdesc)\n#define SET_TX_DESC_ANTSEL_A_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_A_V2(txdesc, value)\n#define GET_TX_DESC_ANTSEL_A_8192F(txdesc) GET_TX_DESC_ANTSEL_A_V2(txdesc)\n#define SET_TX_DESC_MBSSID_8192F(txdesc, value)                                \\\n\tSET_TX_DESC_MBSSID(txdesc, value)\n#define GET_TX_DESC_MBSSID_8192F(txdesc) GET_TX_DESC_MBSSID(txdesc)\n#define SET_TX_DESC_SWPS_SEQ_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_SWPS_SEQ(txdesc, value)\n#define GET_TX_DESC_SWPS_SEQ_8192F(txdesc) GET_TX_DESC_SWPS_SEQ(txdesc)\n\n/*TXDESC_WORD7*/\n\n#define SET_TX_DESC_DMA_TXAGG_NUM_8192F(txdesc, value)                         \\\n\tSET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)\n#define GET_TX_DESC_DMA_TXAGG_NUM_8192F(txdesc)                                \\\n\tGET_TX_DESC_DMA_TXAGG_NUM(txdesc)\n#define SET_TX_DESC_ANT_MAPD_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPD_V2(txdesc, value)\n#define GET_TX_DESC_ANT_MAPD_8192F(txdesc) GET_TX_DESC_ANT_MAPD_V2(txdesc)\n#define SET_TX_DESC_ANTSEL_EN_8192F(txdesc, value)                             \\\n\tSET_TX_DESC_ANTSEL_EN_V2(txdesc, value)\n#define GET_TX_DESC_ANTSEL_EN_8192F(txdesc) GET_TX_DESC_ANTSEL_EN_V2(txdesc)\n#define SET_TX_DESC_MBSSID_EX_8192F(txdesc, value)                             \\\n\tSET_TX_DESC_MBSSID_EX_V1(txdesc, value)\n#define GET_TX_DESC_MBSSID_EX_8192F(txdesc) GET_TX_DESC_MBSSID_EX_V1(txdesc)\n#define SET_TX_DESC_TX_BUFF_SIZE_8192F(txdesc, value)                          \\\n\tSET_TX_DESC_TX_BUFF_SIZE(txdesc, value)\n#define GET_TX_DESC_TX_BUFF_SIZE_8192F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)\n#define SET_TX_DESC_TXDESC_CHECKSUM_8192F(txdesc, value)                       \\\n\tSET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)\n#define GET_TX_DESC_TXDESC_CHECKSUM_8192F(txdesc)                              \\\n\tGET_TX_DESC_TXDESC_CHECKSUM(txdesc)\n#define SET_TX_DESC_TIMESTAMP_8192F(txdesc, value)                             \\\n\tSET_TX_DESC_TIMESTAMP(txdesc, value)\n#define GET_TX_DESC_TIMESTAMP_8192F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)\n\n/*TXDESC_WORD8*/\n\n#define SET_TX_DESC_TAILPAGE_L_8192F(txdesc, value)                            \\\n\tSET_TX_DESC_TAILPAGE_L(txdesc, value)\n#define GET_TX_DESC_TAILPAGE_L_8192F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)\n#define SET_TX_DESC_SDIO_DMASEQ_8192F(txdesc, value)                           \\\n\tSET_TX_DESC_SDIO_DMASEQ(txdesc, value)\n#define GET_TX_DESC_SDIO_DMASEQ_8192F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)\n#define SET_TX_DESC_NEXTHEADPAGE_L_8192F(txdesc, value)                        \\\n\tSET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)\n#define GET_TX_DESC_NEXTHEADPAGE_L_8192F(txdesc)                               \\\n\tGET_TX_DESC_NEXTHEADPAGE_L(txdesc)\n#define SET_TX_DESC_EN_HWSEQ_8192F(txdesc, value)                              \\\n\tSET_TX_DESC_EN_HWSEQ(txdesc, value)\n#define GET_TX_DESC_EN_HWSEQ_8192F(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)\n#define SET_TX_DESC_DATA_RC_8192F(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_RC(txdesc, value)\n#define GET_TX_DESC_DATA_RC_8192F(txdesc) GET_TX_DESC_DATA_RC(txdesc)\n#define SET_TX_DESC_BAR_RTY_TH_8192F(txdesc, value)                            \\\n\tSET_TX_DESC_BAR_RTY_TH(txdesc, value)\n#define GET_TX_DESC_BAR_RTY_TH_8192F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)\n#define SET_TX_DESC_RTS_RC_8192F(txdesc, value)                                \\\n\tSET_TX_DESC_RTS_RC(txdesc, value)\n#define GET_TX_DESC_RTS_RC_8192F(txdesc) GET_TX_DESC_RTS_RC(txdesc)\n\n/*TXDESC_WORD9*/\n\n#define SET_TX_DESC_FINAL_DATA_RATE_8192F(txdesc, value)                       \\\n\tSET_TX_DESC_FINAL_DATA_RATE_V1(txdesc, value)\n#define GET_TX_DESC_FINAL_DATA_RATE_8192F(txdesc)                              \\\n\tGET_TX_DESC_FINAL_DATA_RATE_V1(txdesc)\n#define SET_TX_DESC_SW_SEQ_8192F(txdesc, value)                                \\\n\tSET_TX_DESC_SW_SEQ(txdesc, value)\n#define GET_TX_DESC_SW_SEQ_8192F(txdesc) GET_TX_DESC_SW_SEQ(txdesc)\n#define SET_TX_DESC_PADDING_LEN_8192F(txdesc, value)                           \\\n\tSET_TX_DESC_PADDING_LEN(txdesc, value)\n#define GET_TX_DESC_PADDING_LEN_8192F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)\n#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8192F(txdesc, value)                   \\\n\tSET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)\n#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8192F(txdesc)                          \\\n\tGET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)\n\n/*WORD10*/\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n/*TXDESC_WORD0*/\n\n#define SET_TX_DESC_DISQSELSEQ_8812F(txdesc, value)                            \\\n\tSET_TX_DESC_DISQSELSEQ(txdesc, value)\n#define GET_TX_DESC_DISQSELSEQ_8812F(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)\n#define SET_TX_DESC_GF_8812F(txdesc, value) SET_TX_DESC_GF(txdesc, value)\n#define GET_TX_DESC_GF_8812F(txdesc) GET_TX_DESC_GF(txdesc)\n#define SET_TX_DESC_NO_ACM_8812F(txdesc, value)                                \\\n\tSET_TX_DESC_NO_ACM(txdesc, value)\n#define GET_TX_DESC_NO_ACM_8812F(txdesc) GET_TX_DESC_NO_ACM(txdesc)\n#define SET_TX_DESC_BCNPKT_TSF_CTRL_8812F(txdesc, value)                       \\\n\tSET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)\n#define GET_TX_DESC_BCNPKT_TSF_CTRL_8812F(txdesc)                              \\\n\tGET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)\n#define SET_TX_DESC_AMSDU_PAD_EN_8812F(txdesc, value)                          \\\n\tSET_TX_DESC_AMSDU_PAD_EN(txdesc, value)\n#define GET_TX_DESC_AMSDU_PAD_EN_8812F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)\n#define SET_TX_DESC_LS_8812F(txdesc, value) SET_TX_DESC_LS(txdesc, value)\n#define GET_TX_DESC_LS_8812F(txdesc) GET_TX_DESC_LS(txdesc)\n#define SET_TX_DESC_HTC_8812F(txdesc, value) SET_TX_DESC_HTC(txdesc, value)\n#define GET_TX_DESC_HTC_8812F(txdesc) GET_TX_DESC_HTC(txdesc)\n#define SET_TX_DESC_BMC_8812F(txdesc, value) SET_TX_DESC_BMC(txdesc, value)\n#define GET_TX_DESC_BMC_8812F(txdesc) GET_TX_DESC_BMC(txdesc)\n#define SET_TX_DESC_OFFSET_8812F(txdesc, value)                                \\\n\tSET_TX_DESC_OFFSET(txdesc, value)\n#define GET_TX_DESC_OFFSET_8812F(txdesc) GET_TX_DESC_OFFSET(txdesc)\n#define SET_TX_DESC_TXPKTSIZE_8812F(txdesc, value)                             \\\n\tSET_TX_DESC_TXPKTSIZE(txdesc, value)\n#define GET_TX_DESC_TXPKTSIZE_8812F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)\n\n/*WORD1*/\n\n#define SET_TX_DESC_MOREDATA_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_MOREDATA(txdesc, value)\n#define GET_TX_DESC_MOREDATA_8812F(txdesc) GET_TX_DESC_MOREDATA(txdesc)\n#define SET_TX_DESC_PKT_OFFSET_8812F(txdesc, value)                            \\\n\tSET_TX_DESC_PKT_OFFSET(txdesc, value)\n#define GET_TX_DESC_PKT_OFFSET_8812F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)\n#define SET_TX_DESC_SEC_TYPE_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_SEC_TYPE(txdesc, value)\n#define GET_TX_DESC_SEC_TYPE_8812F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)\n#define SET_TX_DESC_EN_DESC_ID_8812F(txdesc, value)                            \\\n\tSET_TX_DESC_EN_DESC_ID(txdesc, value)\n#define GET_TX_DESC_EN_DESC_ID_8812F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)\n#define SET_TX_DESC_RATE_ID_8812F(txdesc, value)                               \\\n\tSET_TX_DESC_RATE_ID(txdesc, value)\n#define GET_TX_DESC_RATE_ID_8812F(txdesc) GET_TX_DESC_RATE_ID(txdesc)\n#define SET_TX_DESC_PIFS_8812F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)\n#define GET_TX_DESC_PIFS_8812F(txdesc) GET_TX_DESC_PIFS(txdesc)\n#define SET_TX_DESC_LSIG_TXOP_EN_8812F(txdesc, value)                          \\\n\tSET_TX_DESC_LSIG_TXOP_EN(txdesc, value)\n#define GET_TX_DESC_LSIG_TXOP_EN_8812F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)\n#define SET_TX_DESC_RD_NAV_EXT_8812F(txdesc, value)                            \\\n\tSET_TX_DESC_RD_NAV_EXT(txdesc, value)\n#define GET_TX_DESC_RD_NAV_EXT_8812F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)\n#define SET_TX_DESC_QSEL_8812F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)\n#define GET_TX_DESC_QSEL_8812F(txdesc) GET_TX_DESC_QSEL(txdesc)\n#define SET_TX_DESC_MACID_8812F(txdesc, value) SET_TX_DESC_MACID(txdesc, value)\n#define GET_TX_DESC_MACID_8812F(txdesc) GET_TX_DESC_MACID(txdesc)\n\n/*TXDESC_WORD2*/\n\n#define SET_TX_DESC_HW_AES_IV_8812F(txdesc, value)                             \\\n\tSET_TX_DESC_HW_AES_IV(txdesc, value)\n#define GET_TX_DESC_HW_AES_IV_8812F(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)\n#define SET_TX_DESC_FTM_EN_8812F(txdesc, value)                                \\\n\tSET_TX_DESC_FTM_EN(txdesc, value)\n#define GET_TX_DESC_FTM_EN_8812F(txdesc) GET_TX_DESC_FTM_EN(txdesc)\n#define SET_TX_DESC_G_ID_8812F(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)\n#define GET_TX_DESC_G_ID_8812F(txdesc) GET_TX_DESC_G_ID(txdesc)\n#define SET_TX_DESC_BT_NULL_8812F(txdesc, value)                               \\\n\tSET_TX_DESC_BT_NULL(txdesc, value)\n#define GET_TX_DESC_BT_NULL_8812F(txdesc) GET_TX_DESC_BT_NULL(txdesc)\n#define SET_TX_DESC_AMPDU_DENSITY_8812F(txdesc, value)                         \\\n\tSET_TX_DESC_AMPDU_DENSITY(txdesc, value)\n#define GET_TX_DESC_AMPDU_DENSITY_8812F(txdesc)                                \\\n\tGET_TX_DESC_AMPDU_DENSITY(txdesc)\n#define SET_TX_DESC_SPE_RPT_8812F(txdesc, value)                               \\\n\tSET_TX_DESC_SPE_RPT(txdesc, value)\n#define GET_TX_DESC_SPE_RPT_8812F(txdesc) GET_TX_DESC_SPE_RPT(txdesc)\n#define SET_TX_DESC_RAW_8812F(txdesc, value) SET_TX_DESC_RAW(txdesc, value)\n#define GET_TX_DESC_RAW_8812F(txdesc) GET_TX_DESC_RAW(txdesc)\n#define SET_TX_DESC_MOREFRAG_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_MOREFRAG(txdesc, value)\n#define GET_TX_DESC_MOREFRAG_8812F(txdesc) GET_TX_DESC_MOREFRAG(txdesc)\n#define SET_TX_DESC_BK_8812F(txdesc, value) SET_TX_DESC_BK(txdesc, value)\n#define GET_TX_DESC_BK_8812F(txdesc) GET_TX_DESC_BK(txdesc)\n#define SET_TX_DESC_NULL_1_8812F(txdesc, value)                                \\\n\tSET_TX_DESC_NULL_1(txdesc, value)\n#define GET_TX_DESC_NULL_1_8812F(txdesc) GET_TX_DESC_NULL_1(txdesc)\n#define SET_TX_DESC_NULL_0_8812F(txdesc, value)                                \\\n\tSET_TX_DESC_NULL_0(txdesc, value)\n#define GET_TX_DESC_NULL_0_8812F(txdesc) GET_TX_DESC_NULL_0(txdesc)\n#define SET_TX_DESC_RDG_EN_8812F(txdesc, value)                                \\\n\tSET_TX_DESC_RDG_EN(txdesc, value)\n#define GET_TX_DESC_RDG_EN_8812F(txdesc) GET_TX_DESC_RDG_EN(txdesc)\n#define SET_TX_DESC_AGG_EN_8812F(txdesc, value)                                \\\n\tSET_TX_DESC_AGG_EN(txdesc, value)\n#define GET_TX_DESC_AGG_EN_8812F(txdesc) GET_TX_DESC_AGG_EN(txdesc)\n#define SET_TX_DESC_CCA_RTS_8812F(txdesc, value)                               \\\n\tSET_TX_DESC_CCA_RTS(txdesc, value)\n#define GET_TX_DESC_CCA_RTS_8812F(txdesc) GET_TX_DESC_CCA_RTS(txdesc)\n#define SET_TX_DESC_TRI_FRAME_8812F(txdesc, value)                             \\\n\tSET_TX_DESC_TRI_FRAME(txdesc, value)\n#define GET_TX_DESC_TRI_FRAME_8812F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)\n#define SET_TX_DESC_P_AID_8812F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)\n#define GET_TX_DESC_P_AID_8812F(txdesc) GET_TX_DESC_P_AID(txdesc)\n\n/*TXDESC_WORD3*/\n\n#define SET_TX_DESC_AMPDU_MAX_TIME_8812F(txdesc, value)                        \\\n\tSET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)\n#define GET_TX_DESC_AMPDU_MAX_TIME_8812F(txdesc)                               \\\n\tGET_TX_DESC_AMPDU_MAX_TIME(txdesc)\n#define SET_TX_DESC_NDPA_8812F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)\n#define GET_TX_DESC_NDPA_8812F(txdesc) GET_TX_DESC_NDPA(txdesc)\n#define SET_TX_DESC_MAX_AGG_NUM_8812F(txdesc, value)                           \\\n\tSET_TX_DESC_MAX_AGG_NUM(txdesc, value)\n#define GET_TX_DESC_MAX_AGG_NUM_8812F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)\n#define SET_TX_DESC_USE_MAX_TIME_EN_8812F(txdesc, value)                       \\\n\tSET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)\n#define GET_TX_DESC_USE_MAX_TIME_EN_8812F(txdesc)                              \\\n\tGET_TX_DESC_USE_MAX_TIME_EN(txdesc)\n#define SET_TX_DESC_NAVUSEHDR_8812F(txdesc, value)                             \\\n\tSET_TX_DESC_NAVUSEHDR(txdesc, value)\n#define GET_TX_DESC_NAVUSEHDR_8812F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)\n#define SET_TX_DESC_CHK_EN_8812F(txdesc, value)                                \\\n\tSET_TX_DESC_CHK_EN(txdesc, value)\n#define GET_TX_DESC_CHK_EN_8812F(txdesc) GET_TX_DESC_CHK_EN(txdesc)\n#define SET_TX_DESC_HW_RTS_EN_8812F(txdesc, value)                             \\\n\tSET_TX_DESC_HW_RTS_EN(txdesc, value)\n#define GET_TX_DESC_HW_RTS_EN_8812F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)\n#define SET_TX_DESC_RTSEN_8812F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)\n#define GET_TX_DESC_RTSEN_8812F(txdesc) GET_TX_DESC_RTSEN(txdesc)\n#define SET_TX_DESC_CTS2SELF_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_CTS2SELF(txdesc, value)\n#define GET_TX_DESC_CTS2SELF_8812F(txdesc) GET_TX_DESC_CTS2SELF(txdesc)\n#define SET_TX_DESC_DISDATAFB_8812F(txdesc, value)                             \\\n\tSET_TX_DESC_DISDATAFB(txdesc, value)\n#define GET_TX_DESC_DISDATAFB_8812F(txdesc) GET_TX_DESC_DISDATAFB(txdesc)\n#define SET_TX_DESC_DISRTSFB_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_DISRTSFB(txdesc, value)\n#define GET_TX_DESC_DISRTSFB_8812F(txdesc) GET_TX_DESC_DISRTSFB(txdesc)\n#define SET_TX_DESC_USE_RATE_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_USE_RATE(txdesc, value)\n#define GET_TX_DESC_USE_RATE_8812F(txdesc) GET_TX_DESC_USE_RATE(txdesc)\n#define SET_TX_DESC_HW_SSN_SEL_8812F(txdesc, value)                            \\\n\tSET_TX_DESC_HW_SSN_SEL(txdesc, value)\n#define GET_TX_DESC_HW_SSN_SEL_8812F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)\n#define SET_TX_DESC_WHEADER_LEN_8812F(txdesc, value)                           \\\n\tSET_TX_DESC_WHEADER_LEN(txdesc, value)\n#define GET_TX_DESC_WHEADER_LEN_8812F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)\n\n/*TXDESC_WORD4*/\n\n#define SET_TX_DESC_PCTS_MASK_IDX_8812F(txdesc, value)                         \\\n\tSET_TX_DESC_PCTS_MASK_IDX(txdesc, value)\n#define GET_TX_DESC_PCTS_MASK_IDX_8812F(txdesc)                                \\\n\tGET_TX_DESC_PCTS_MASK_IDX(txdesc)\n#define SET_TX_DESC_PCTS_EN_8812F(txdesc, value)                               \\\n\tSET_TX_DESC_PCTS_EN(txdesc, value)\n#define GET_TX_DESC_PCTS_EN_8812F(txdesc) GET_TX_DESC_PCTS_EN(txdesc)\n#define SET_TX_DESC_RTSRATE_8812F(txdesc, value)                               \\\n\tSET_TX_DESC_RTSRATE(txdesc, value)\n#define GET_TX_DESC_RTSRATE_8812F(txdesc) GET_TX_DESC_RTSRATE(txdesc)\n#define SET_TX_DESC_RTS_DATA_RTY_LMT_8812F(txdesc, value)                      \\\n\tSET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)\n#define GET_TX_DESC_RTS_DATA_RTY_LMT_8812F(txdesc)                             \\\n\tGET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)\n#define SET_TX_DESC_RTY_LMT_EN_8812F(txdesc, value)                            \\\n\tSET_TX_DESC_RTY_LMT_EN(txdesc, value)\n#define GET_TX_DESC_RTY_LMT_EN_8812F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)\n#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8812F(txdesc, value)                   \\\n\tSET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8812F(txdesc)                          \\\n\tGET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)\n#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8812F(txdesc, value)                  \\\n\tSET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)\n#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8812F(txdesc)                         \\\n\tGET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)\n#define SET_TX_DESC_TRY_RATE_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_TRY_RATE(txdesc, value)\n#define GET_TX_DESC_TRY_RATE_8812F(txdesc) GET_TX_DESC_TRY_RATE(txdesc)\n#define SET_TX_DESC_DATARATE_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_DATARATE(txdesc, value)\n#define GET_TX_DESC_DATARATE_8812F(txdesc) GET_TX_DESC_DATARATE(txdesc)\n\n/*TXDESC_WORD5*/\n\n#define SET_TX_DESC_POLLUTED_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_POLLUTED(txdesc, value)\n#define GET_TX_DESC_POLLUTED_8812F(txdesc) GET_TX_DESC_POLLUTED(txdesc)\n#define SET_TX_DESC_ANTSEL_EN_8812F(txdesc, value)                             \\\n\tSET_TX_DESC_ANTSEL_EN_V1(txdesc, value)\n#define GET_TX_DESC_ANTSEL_EN_8812F(txdesc) GET_TX_DESC_ANTSEL_EN_V1(txdesc)\n#define SET_TX_DESC_TXPWR_OFSET_TYPE_8812F(txdesc, value)                      \\\n\tSET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value)\n#define GET_TX_DESC_TXPWR_OFSET_TYPE_8812F(txdesc)                             \\\n\tGET_TX_DESC_TXPWR_OFSET_TYPE(txdesc)\n#define SET_TX_DESC_TX_ANT_8812F(txdesc, value)                                \\\n\tSET_TX_DESC_TX_ANT(txdesc, value)\n#define GET_TX_DESC_TX_ANT_8812F(txdesc) GET_TX_DESC_TX_ANT(txdesc)\n#define SET_TX_DESC_PORT_ID_8812F(txdesc, value)                               \\\n\tSET_TX_DESC_PORT_ID(txdesc, value)\n#define GET_TX_DESC_PORT_ID_8812F(txdesc) GET_TX_DESC_PORT_ID(txdesc)\n#define SET_TX_DESC_MULTIPLE_PORT_8812F(txdesc, value)                         \\\n\tSET_TX_DESC_MULTIPLE_PORT(txdesc, value)\n#define GET_TX_DESC_MULTIPLE_PORT_8812F(txdesc)                                \\\n\tGET_TX_DESC_MULTIPLE_PORT(txdesc)\n#define SET_TX_DESC_SIGNALING_TAPKT_EN_8812F(txdesc, value)                    \\\n\tSET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)\n#define GET_TX_DESC_SIGNALING_TAPKT_EN_8812F(txdesc)                           \\\n\tGET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)\n#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8812F(txdesc, value)                   \\\n\tSET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)\n#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8812F(txdesc)                          \\\n\tGET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)\n#define SET_TX_DESC_RTS_SHORT_8812F(txdesc, value)                             \\\n\tSET_TX_DESC_RTS_SHORT(txdesc, value)\n#define GET_TX_DESC_RTS_SHORT_8812F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)\n#define SET_TX_DESC_VCS_STBC_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_VCS_STBC(txdesc, value)\n#define GET_TX_DESC_VCS_STBC_8812F(txdesc) GET_TX_DESC_VCS_STBC(txdesc)\n#define SET_TX_DESC_DATA_STBC_8812F(txdesc, value)                             \\\n\tSET_TX_DESC_DATA_STBC(txdesc, value)\n#define GET_TX_DESC_DATA_STBC_8812F(txdesc) GET_TX_DESC_DATA_STBC(txdesc)\n#define SET_TX_DESC_DATA_LDPC_8812F(txdesc, value)                             \\\n\tSET_TX_DESC_DATA_LDPC(txdesc, value)\n#define GET_TX_DESC_DATA_LDPC_8812F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)\n#define SET_TX_DESC_DATA_BW_8812F(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_BW(txdesc, value)\n#define GET_TX_DESC_DATA_BW_8812F(txdesc) GET_TX_DESC_DATA_BW(txdesc)\n#define SET_TX_DESC_DATA_SHORT_8812F(txdesc, value)                            \\\n\tSET_TX_DESC_DATA_SHORT(txdesc, value)\n#define GET_TX_DESC_DATA_SHORT_8812F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)\n#define SET_TX_DESC_DATA_SC_8812F(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_SC(txdesc, value)\n#define GET_TX_DESC_DATA_SC_8812F(txdesc) GET_TX_DESC_DATA_SC(txdesc)\n\n/*TXDESC_WORD6*/\n\n#define SET_TX_DESC_ANTSEL_D_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_D(txdesc, value)\n#define GET_TX_DESC_ANTSEL_D_8812F(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)\n#define SET_TX_DESC_ANT_MAPD_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPD(txdesc, value)\n#define GET_TX_DESC_ANT_MAPD_8812F(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)\n#define SET_TX_DESC_ANT_MAPC_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPC(txdesc, value)\n#define GET_TX_DESC_ANT_MAPC_8812F(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)\n#define SET_TX_DESC_ANT_MAPB_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPB(txdesc, value)\n#define GET_TX_DESC_ANT_MAPB_8812F(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)\n#define SET_TX_DESC_ANT_MAPA_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_ANT_MAPA(txdesc, value)\n#define GET_TX_DESC_ANT_MAPA_8812F(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)\n#define SET_TX_DESC_ANTSEL_C_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_C(txdesc, value)\n#define GET_TX_DESC_ANTSEL_C_8812F(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)\n#define SET_TX_DESC_ANTSEL_B_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_B(txdesc, value)\n#define GET_TX_DESC_ANTSEL_B_8812F(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)\n#define SET_TX_DESC_ANTSEL_A_8812F(txdesc, value)                              \\\n\tSET_TX_DESC_ANTSEL_A(txdesc, value)\n#define GET_TX_DESC_ANTSEL_A_8812F(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)\n#define SET_TX_DESC_MBSSID_8812F(txdesc, value)                                \\\n\tSET_TX_DESC_MBSSID(txdesc, value)\n#define GET_TX_DESC_MBSSID_8812F(txdesc) GET_TX_DESC_MBSSID(txdesc)\n#define SET_TX_DESC_SW_DEFINE_8812F(txdesc, value)                             \\\n\tSET_TX_DESC_SW_DEFINE(txdesc, value)\n#define GET_TX_DESC_SW_DEFINE_8812F(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)\n\n/*TXDESC_WORD7*/\n\n#define SET_TX_DESC_DMA_TXAGG_NUM_8812F(txdesc, value)                         \\\n\tSET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)\n#define GET_TX_DESC_DMA_TXAGG_NUM_8812F(txdesc)                                \\\n\tGET_TX_DESC_DMA_TXAGG_NUM(txdesc)\n#define SET_TX_DESC_FINAL_DATA_RATE_8812F(txdesc, value)                       \\\n\tSET_TX_DESC_FINAL_DATA_RATE(txdesc, value)\n#define GET_TX_DESC_FINAL_DATA_RATE_8812F(txdesc)                              \\\n\tGET_TX_DESC_FINAL_DATA_RATE(txdesc)\n#define SET_TX_DESC_NTX_MAP_8812F(txdesc, value)                               \\\n\tSET_TX_DESC_NTX_MAP(txdesc, value)\n#define GET_TX_DESC_NTX_MAP_8812F(txdesc) GET_TX_DESC_NTX_MAP(txdesc)\n#define SET_TX_DESC_TX_BUFF_SIZE_8812F(txdesc, value)                          \\\n\tSET_TX_DESC_TX_BUFF_SIZE(txdesc, value)\n#define GET_TX_DESC_TX_BUFF_SIZE_8812F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)\n#define SET_TX_DESC_TXDESC_CHECKSUM_8812F(txdesc, value)                       \\\n\tSET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)\n#define GET_TX_DESC_TXDESC_CHECKSUM_8812F(txdesc)                              \\\n\tGET_TX_DESC_TXDESC_CHECKSUM(txdesc)\n#define SET_TX_DESC_TIMESTAMP_8812F(txdesc, value)                             \\\n\tSET_TX_DESC_TIMESTAMP(txdesc, value)\n#define GET_TX_DESC_TIMESTAMP_8812F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)\n\n/*TXDESC_WORD8*/\n\n#define SET_TX_DESC_TXWIFI_CP_8812F(txdesc, value)                             \\\n\tSET_TX_DESC_TXWIFI_CP(txdesc, value)\n#define GET_TX_DESC_TXWIFI_CP_8812F(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)\n#define SET_TX_DESC_MAC_CP_8812F(txdesc, value)                                \\\n\tSET_TX_DESC_MAC_CP(txdesc, value)\n#define GET_TX_DESC_MAC_CP_8812F(txdesc) GET_TX_DESC_MAC_CP(txdesc)\n#define SET_TX_DESC_STW_PKTRE_DIS_8812F(txdesc, value)                         \\\n\tSET_TX_DESC_STW_PKTRE_DIS(txdesc, value)\n#define GET_TX_DESC_STW_PKTRE_DIS_8812F(txdesc)                                \\\n\tGET_TX_DESC_STW_PKTRE_DIS(txdesc)\n#define SET_TX_DESC_STW_RB_DIS_8812F(txdesc, value)                            \\\n\tSET_TX_DESC_STW_RB_DIS(txdesc, value)\n#define GET_TX_DESC_STW_RB_DIS_8812F(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)\n#define SET_TX_DESC_STW_RATE_DIS_8812F(txdesc, value)                          \\\n\tSET_TX_DESC_STW_RATE_DIS(txdesc, value)\n#define GET_TX_DESC_STW_RATE_DIS_8812F(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)\n#define SET_TX_DESC_STW_ANT_DIS_8812F(txdesc, value)                           \\\n\tSET_TX_DESC_STW_ANT_DIS(txdesc, value)\n#define GET_TX_DESC_STW_ANT_DIS_8812F(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)\n#define SET_TX_DESC_STW_EN_8812F(txdesc, value)                                \\\n\tSET_TX_DESC_STW_EN(txdesc, value)\n#define GET_TX_DESC_STW_EN_8812F(txdesc) GET_TX_DESC_STW_EN(txdesc)\n#define SET_TX_DESC_SMH_EN_8812F(txdesc, value)                                \\\n\tSET_TX_DESC_SMH_EN(txdesc, value)\n#define GET_TX_DESC_SMH_EN_8812F(txdesc) GET_TX_DESC_SMH_EN(txdesc)\n#define SET_TX_DESC_TAILPAGE_L_8812F(txdesc, value)                            \\\n\tSET_TX_DESC_TAILPAGE_L(txdesc, value)\n#define GET_TX_DESC_TAILPAGE_L_8812F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)\n#define SET_TX_DESC_SDIO_DMASEQ_8812F(txdesc, value)                           \\\n\tSET_TX_DESC_SDIO_DMASEQ(txdesc, value)\n#define GET_TX_DESC_SDIO_DMASEQ_8812F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)\n#define SET_TX_DESC_NEXTHEADPAGE_L_8812F(txdesc, value)                        \\\n\tSET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)\n#define GET_TX_DESC_NEXTHEADPAGE_L_8812F(txdesc)                               \\\n\tGET_TX_DESC_NEXTHEADPAGE_L(txdesc)\n#define SET_TX_DESC_EN_HWSEQ_MODE_8812F(txdesc, value)                         \\\n\tSET_TX_DESC_EN_HWSEQ_MODE(txdesc, value)\n#define GET_TX_DESC_EN_HWSEQ_MODE_8812F(txdesc)                                \\\n\tGET_TX_DESC_EN_HWSEQ_MODE(txdesc)\n#define SET_TX_DESC_DATA_RC_8812F(txdesc, value)                               \\\n\tSET_TX_DESC_DATA_RC(txdesc, value)\n#define GET_TX_DESC_DATA_RC_8812F(txdesc) GET_TX_DESC_DATA_RC(txdesc)\n#define SET_TX_DESC_BAR_RTY_TH_8812F(txdesc, value)                            \\\n\tSET_TX_DESC_BAR_RTY_TH(txdesc, value)\n#define GET_TX_DESC_BAR_RTY_TH_8812F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)\n#define SET_TX_DESC_RTS_RC_8812F(txdesc, value)                                \\\n\tSET_TX_DESC_RTS_RC(txdesc, value)\n#define GET_TX_DESC_RTS_RC_8812F(txdesc) GET_TX_DESC_RTS_RC(txdesc)\n\n/*TXDESC_WORD9*/\n\n#define SET_TX_DESC_TAILPAGE_H_8812F(txdesc, value)                            \\\n\tSET_TX_DESC_TAILPAGE_H(txdesc, value)\n#define GET_TX_DESC_TAILPAGE_H_8812F(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)\n#define SET_TX_DESC_NEXTHEADPAGE_H_8812F(txdesc, value)                        \\\n\tSET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)\n#define GET_TX_DESC_NEXTHEADPAGE_H_8812F(txdesc)                               \\\n\tGET_TX_DESC_NEXTHEADPAGE_H(txdesc)\n#define SET_TX_DESC_SW_SEQ_8812F(txdesc, value)                                \\\n\tSET_TX_DESC_SW_SEQ(txdesc, value)\n#define GET_TX_DESC_SW_SEQ_8812F(txdesc) GET_TX_DESC_SW_SEQ(txdesc)\n#define SET_TX_DESC_TXBF_PATH_8812F(txdesc, value)                             \\\n\tSET_TX_DESC_TXBF_PATH(txdesc, value)\n#define GET_TX_DESC_TXBF_PATH_8812F(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)\n#define SET_TX_DESC_PADDING_LEN_8812F(txdesc, value)                           \\\n\tSET_TX_DESC_PADDING_LEN(txdesc, value)\n#define GET_TX_DESC_PADDING_LEN_8812F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)\n#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8812F(txdesc, value)                   \\\n\tSET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)\n#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8812F(txdesc)                          \\\n\tGET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)\n\n/*WORD10*/\n\n#define SET_TX_DESC_HT_DATA_SND_8812F(txdesc, value)                           \\\n\tSET_TX_DESC_HT_DATA_SND(txdesc, value)\n#define GET_TX_DESC_HT_DATA_SND_8812F(txdesc) GET_TX_DESC_HT_DATA_SND(txdesc)\n#define SET_TX_DESC_SHCUT_CAM_8812F(txdesc, value)                             \\\n\tSET_TX_DESC_SHCUT_CAM(txdesc, value)\n#define GET_TX_DESC_SHCUT_CAM_8812F(txdesc) GET_TX_DESC_SHCUT_CAM(txdesc)\n#define SET_TX_DESC_MU_DATARATE_8812F(txdesc, value)                           \\\n\tSET_TX_DESC_MU_DATARATE(txdesc, value)\n#define GET_TX_DESC_MU_DATARATE_8812F(txdesc) GET_TX_DESC_MU_DATARATE(txdesc)\n#define SET_TX_DESC_MU_RC_8812F(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value)\n#define GET_TX_DESC_MU_RC_8812F(txdesc) GET_TX_DESC_MU_RC(txdesc)\n#define SET_TX_DESC_NDPA_RATE_SEL_8812F(txdesc, value)                         \\\n\tSET_TX_DESC_NDPA_RATE_SEL(txdesc, value)\n#define GET_TX_DESC_NDPA_RATE_SEL_8812F(txdesc)                                \\\n\tGET_TX_DESC_NDPA_RATE_SEL(txdesc)\n#define SET_TX_DESC_HW_NDPA_EN_8812F(txdesc, value)                            \\\n\tSET_TX_DESC_HW_NDPA_EN(txdesc, value)\n#define GET_TX_DESC_HW_NDPA_EN_8812F(txdesc) GET_TX_DESC_HW_NDPA_EN(txdesc)\n#define SET_TX_DESC_SND_PKT_SEL_8812F(txdesc, value)                           \\\n\tSET_TX_DESC_SND_PKT_SEL(txdesc, value)\n#define GET_TX_DESC_SND_PKT_SEL_8812F(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc)\n\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_tx_desc_ie_ap.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_TX_DESC_IE_AP_H_\n#define _HALMAC_TX_DESC_IE_AP_H_\n#if (HALMAC_8814B_SUPPORT)\n\n#define IE0_GET_TX_DESC_IE_END(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 31)\n#define IE0_SET_TX_DESC_IE_END(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)\n#define IE0_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)\n#define IE0_GET_TX_DESC_IE_UP(txdesc_ie)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 30)\n#define IE0_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)\n#define IE0_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)\n#define IE0_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0xf, 24)\n#define IE0_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)\n#define IE0_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)\n#define IE0_GET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie)                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 19)\n#define IE0_SET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie, value)                       \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 19)\n#define IE0_SET_TX_DESC_ARFR_TABLE_SEL_NO_CLR(txdesc_ie, value)                \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 19)\n#define IE0_GET_TX_DESC_ARFR_HT_EN(txdesc_ie)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 18)\n#define IE0_SET_TX_DESC_ARFR_HT_EN(txdesc_ie, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 18)\n#define IE0_SET_TX_DESC_ARFR_HT_EN_NO_CLR(txdesc_ie, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 18)\n#define IE0_GET_TX_DESC_ARFR_OFDM_EN(txdesc_ie)                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 17)\n#define IE0_SET_TX_DESC_ARFR_OFDM_EN(txdesc_ie, value)                         \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 17)\n#define IE0_SET_TX_DESC_ARFR_OFDM_EN_NO_CLR(txdesc_ie, value)                  \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 17)\n#define IE0_GET_TX_DESC_ARFR_CCK_EN(txdesc_ie)                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 16)\n#define IE0_SET_TX_DESC_ARFR_CCK_EN(txdesc_ie, value)                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 16)\n#define IE0_SET_TX_DESC_ARFR_CCK_EN_NO_CLR(txdesc_ie, value)                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 16)\n#define IE0_GET_TX_DESC_HW_RTS_EN(txdesc_ie)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 9)\n#define IE0_SET_TX_DESC_HW_RTS_EN(txdesc_ie, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9)\n#define IE0_SET_TX_DESC_HW_RTS_EN_NO_CLR(txdesc_ie, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9)\n#define IE0_GET_TX_DESC_RTS_EN(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 8)\n#define IE0_SET_TX_DESC_RTS_EN(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8)\n#define IE0_SET_TX_DESC_RTS_EN_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8)\n#define IE0_GET_TX_DESC_CTS2SELF(txdesc_ie)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 7)\n#define IE0_SET_TX_DESC_CTS2SELF(txdesc_ie, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)\n#define IE0_SET_TX_DESC_CTS2SELF_NO_CLR(txdesc_ie, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)\n#define IE0_GET_TX_DESC_RTY_LMT_EN(txdesc_ie)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 6)\n#define IE0_SET_TX_DESC_RTY_LMT_EN(txdesc_ie, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)\n#define IE0_SET_TX_DESC_RTY_LMT_EN_NO_CLR(txdesc_ie, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)\n#define IE0_GET_TX_DESC_RTS_SHORT(txdesc_ie)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 5)\n#define IE0_SET_TX_DESC_RTS_SHORT(txdesc_ie, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5)\n#define IE0_SET_TX_DESC_RTS_SHORT_NO_CLR(txdesc_ie, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5)\n#define IE0_GET_TX_DESC_DISDATAFB(txdesc_ie)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 4)\n#define IE0_SET_TX_DESC_DISDATAFB(txdesc_ie, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4)\n#define IE0_SET_TX_DESC_DISDATAFB_NO_CLR(txdesc_ie, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4)\n#define IE0_GET_TX_DESC_DISRTSFB(txdesc_ie)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 3)\n#define IE0_SET_TX_DESC_DISRTSFB(txdesc_ie, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)\n#define IE0_SET_TX_DESC_DISRTSFB_NO_CLR(txdesc_ie, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)\n#define IE0_GET_TX_DESC_DATA_SHORT(txdesc_ie)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 2)\n#define IE0_SET_TX_DESC_DATA_SHORT(txdesc_ie, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)\n#define IE0_SET_TX_DESC_DATA_SHORT_NO_CLR(txdesc_ie, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)\n#define IE0_GET_TX_DESC_TRY_RATE(txdesc_ie)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 1)\n#define IE0_SET_TX_DESC_TRY_RATE(txdesc_ie, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)\n#define IE0_SET_TX_DESC_TRY_RATE_NO_CLR(txdesc_ie, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)\n#define IE0_GET_TX_DESC_USERATE(txdesc_ie)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 0)\n#define IE0_SET_TX_DESC_USERATE(txdesc_ie, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)\n#define IE0_SET_TX_DESC_USERATE_NO_CLR(txdesc_ie, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)\n#define IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie)                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0xf, 27)\n#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie, value)                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27)\n#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE_NO_CLR(txdesc_ie, value)           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27)\n#define IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie)                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x1f, 22)\n#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie, value)                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1f, 22)\n#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE_NO_CLR(txdesc_ie, value)          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1f, 22)\n#define IE0_GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie)                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x3f, 16)\n#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie, value)                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 16)\n#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT_NO_CLR(txdesc_ie, value)              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 16)\n#define IE0_GET_TX_DESC_DATA_BW(txdesc_ie)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x3, 12)\n#define IE0_SET_TX_DESC_DATA_BW(txdesc_ie, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12)\n#define IE0_SET_TX_DESC_DATA_BW_NO_CLR(txdesc_ie, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12)\n#define IE0_GET_TX_DESC_RTSRATE(txdesc_ie)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0xf, 7)\n#define IE0_SET_TX_DESC_RTSRATE(txdesc_ie, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 7)\n#define IE0_SET_TX_DESC_RTSRATE_NO_CLR(txdesc_ie, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 7)\n#define IE0_GET_TX_DESC_DATARATE(txdesc_ie)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x7f, 0)\n#define IE0_SET_TX_DESC_DATARATE(txdesc_ie, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0)\n#define IE0_SET_TX_DESC_DATARATE_NO_CLR(txdesc_ie, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0)\n#define IE1_GET_TX_DESC_IE_END(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 31)\n#define IE1_SET_TX_DESC_IE_END(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)\n#define IE1_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)\n#define IE1_GET_TX_DESC_IE_UP(txdesc_ie)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 30)\n#define IE1_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)\n#define IE1_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)\n#define IE1_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0xf, 24)\n#define IE1_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)\n#define IE1_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)\n#define IE1_GET_TX_DESC_AMPDU_DENSITY(txdesc_ie)                               \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x7, 21)\n#define IE1_SET_TX_DESC_AMPDU_DENSITY(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 21)\n#define IE1_SET_TX_DESC_AMPDU_DENSITY_NO_CLR(txdesc_ie, value)                 \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 21)\n#define IE1_GET_TX_DESC_MAX_AGG_NUM(txdesc_ie)                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1f, 16)\n#define IE1_SET_TX_DESC_MAX_AGG_NUM(txdesc_ie, value)                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1f, 16)\n#define IE1_SET_TX_DESC_MAX_AGG_NUM_NO_CLR(txdesc_ie, value)                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1f, 16)\n#define IE1_GET_TX_DESC_SECTYPE(txdesc_ie)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x3, 14)\n#define IE1_SET_TX_DESC_SECTYPE(txdesc_ie, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 14)\n#define IE1_SET_TX_DESC_SECTYPE_NO_CLR(txdesc_ie, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 14)\n#define IE1_GET_TX_DESC_MOREFRAG(txdesc_ie)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 13)\n#define IE1_SET_TX_DESC_MOREFRAG(txdesc_ie, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 13)\n#define IE1_SET_TX_DESC_MOREFRAG_NO_CLR(txdesc_ie, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 13)\n#define IE1_GET_TX_DESC_NOACM(txdesc_ie)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 12)\n#define IE1_SET_TX_DESC_NOACM(txdesc_ie, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 12)\n#define IE1_SET_TX_DESC_NOACM_NO_CLR(txdesc_ie, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 12)\n#define IE1_GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie)                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 11)\n#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie, value)                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11)\n#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL_NO_CLR(txdesc_ie, value)               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11)\n#define IE1_GET_TX_DESC_NAVUSEHDR(txdesc_ie)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 10)\n#define IE1_SET_TX_DESC_NAVUSEHDR(txdesc_ie, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10)\n#define IE1_SET_TX_DESC_NAVUSEHDR_NO_CLR(txdesc_ie, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10)\n#define IE1_GET_TX_DESC_HTC(txdesc_ie)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 9)\n#define IE1_SET_TX_DESC_HTC(txdesc_ie, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9)\n#define IE1_SET_TX_DESC_HTC_NO_CLR(txdesc_ie, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9)\n#define IE1_GET_TX_DESC_BMC(txdesc_ie)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 8)\n#define IE1_SET_TX_DESC_BMC(txdesc_ie, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8)\n#define IE1_SET_TX_DESC_BMC_NO_CLR(txdesc_ie, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8)\n#define IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie)                           \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 7)\n#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie, value)                    \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)\n#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS_NO_CLR(txdesc_ie, value)             \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)\n#define IE1_GET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie)                             \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 6)\n#define IE1_SET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie, value)                      \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)\n#define IE1_SET_TX_DESC_USE_MAX_TIME_EN_NO_CLR(txdesc_ie, value)               \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)\n#define IE1_GET_TX_DESC_HW_SSN_SEL(txdesc_ie)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x3, 4)\n#define IE1_SET_TX_DESC_HW_SSN_SEL(txdesc_ie, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 4)\n#define IE1_SET_TX_DESC_HW_SSN_SEL_NO_CLR(txdesc_ie, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 4)\n#define IE1_GET_TX_DESC_DISQSELSEQ(txdesc_ie)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 3)\n#define IE1_SET_TX_DESC_DISQSELSEQ(txdesc_ie, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)\n#define IE1_SET_TX_DESC_DISQSELSEQ_NO_CLR(txdesc_ie, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)\n#define IE1_GET_TX_DESC_EN_HWSEQ(txdesc_ie)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 2)\n#define IE1_SET_TX_DESC_EN_HWSEQ(txdesc_ie, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)\n#define IE1_SET_TX_DESC_EN_HWSEQ_NO_CLR(txdesc_ie, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)\n#define IE1_GET_TX_DESC_EN_HWEXSEQ(txdesc_ie)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 1)\n#define IE1_SET_TX_DESC_EN_HWEXSEQ(txdesc_ie, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)\n#define IE1_SET_TX_DESC_EN_HWEXSEQ_NO_CLR(txdesc_ie, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)\n#define IE1_GET_TX_DESC_EN_DESC_ID(txdesc_ie)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 0)\n#define IE1_SET_TX_DESC_EN_DESC_ID(txdesc_ie, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)\n#define IE1_SET_TX_DESC_EN_DESC_ID_NO_CLR(txdesc_ie, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)\n#define IE1_GET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie)                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0xff, 24)\n#define IE1_SET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie, value)                       \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 24)\n#define IE1_SET_TX_DESC_AMPDU_MAX_TIME_NO_CLR(txdesc_ie, value)                \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 24)\n#define IE1_GET_TX_DESC_P_AID(txdesc_ie)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x1ff, 15)\n#define IE1_SET_TX_DESC_P_AID(txdesc_ie, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1ff,    \\\n\t\t15)\n#define IE1_SET_TX_DESC_P_AID_NO_CLR(txdesc_ie, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1ff,    \\\n\t\t15)\n#define IE1_GET_TX_DESC_MOREDATA(txdesc_ie)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x1, 14)\n#define IE1_SET_TX_DESC_MOREDATA(txdesc_ie, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 14)\n#define IE1_SET_TX_DESC_MOREDATA_NO_CLR(txdesc_ie, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 14)\n#define IE1_GET_TX_DESC_SW_SEQ(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0xfff, 0)\n#define IE1_SET_TX_DESC_SW_SEQ(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0)\n#define IE1_SET_TX_DESC_SW_SEQ_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0)\n#define IE2_GET_TX_DESC_IE_END(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 31)\n#define IE2_SET_TX_DESC_IE_END(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)\n#define IE2_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)\n#define IE2_GET_TX_DESC_IE_UP(txdesc_ie)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 30)\n#define IE2_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)\n#define IE2_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)\n#define IE2_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0xf, 24)\n#define IE2_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)\n#define IE2_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)\n#define IE2_GET_TX_DESC_ADDR_CAM(txdesc_ie)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0xff, 16)\n#define IE2_SET_TX_DESC_ADDR_CAM(txdesc_ie, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xff, 16)\n#define IE2_SET_TX_DESC_ADDR_CAM_NO_CLR(txdesc_ie, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xff, 16)\n#define IE2_GET_TX_DESC_MULTIPLE_PORT(txdesc_ie)                               \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x7, 12)\n#define IE2_SET_TX_DESC_MULTIPLE_PORT(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 12)\n#define IE2_SET_TX_DESC_MULTIPLE_PORT_NO_CLR(txdesc_ie, value)                 \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 12)\n#define IE2_GET_TX_DESC_RAW(txdesc_ie)                                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 11)\n#define IE2_SET_TX_DESC_RAW(txdesc_ie, value)                                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11)\n#define IE2_SET_TX_DESC_RAW_NO_CLR(txdesc_ie, value)                           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11)\n#define IE2_GET_TX_DESC_RDG_EN(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 10)\n#define IE2_SET_TX_DESC_RDG_EN(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10)\n#define IE2_SET_TX_DESC_RDG_EN_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10)\n#define IE2_GET_TX_DESC_SPECIAL_CW(txdesc_ie)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 7)\n#define IE2_SET_TX_DESC_SPECIAL_CW(txdesc_ie, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)\n#define IE2_SET_TX_DESC_SPECIAL_CW_NO_CLR(txdesc_ie, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)\n#define IE2_GET_TX_DESC_POLLUTED(txdesc_ie)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 6)\n#define IE2_SET_TX_DESC_POLLUTED(txdesc_ie, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)\n#define IE2_SET_TX_DESC_POLLUTED_NO_CLR(txdesc_ie, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)\n#define IE2_GET_TX_DESC_BT_NULL(txdesc_ie)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 5)\n#define IE2_SET_TX_DESC_BT_NULL(txdesc_ie, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5)\n#define IE2_SET_TX_DESC_BT_NULL_NO_CLR(txdesc_ie, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5)\n#define IE2_GET_TX_DESC_NULL_1(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 4)\n#define IE2_SET_TX_DESC_NULL_1(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4)\n#define IE2_SET_TX_DESC_NULL_1_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4)\n#define IE2_GET_TX_DESC_NULL_0(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 3)\n#define IE2_SET_TX_DESC_NULL_0(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)\n#define IE2_SET_TX_DESC_NULL_0_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)\n#define IE2_GET_TX_DESC_TRI_FRAME(txdesc_ie)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 2)\n#define IE2_SET_TX_DESC_TRI_FRAME(txdesc_ie, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)\n#define IE2_SET_TX_DESC_TRI_FRAME_NO_CLR(txdesc_ie, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)\n#define IE2_GET_TX_DESC_SPE_RPT(txdesc_ie)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 1)\n#define IE2_SET_TX_DESC_SPE_RPT(txdesc_ie, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)\n#define IE2_SET_TX_DESC_SPE_RPT_NO_CLR(txdesc_ie, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)\n#define IE2_GET_TX_DESC_FTM_EN(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 0)\n#define IE2_SET_TX_DESC_FTM_EN(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)\n#define IE2_SET_TX_DESC_FTM_EN_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)\n#define IE2_GET_TX_DESC_MBSSID(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0xf, 27)\n#define IE2_SET_TX_DESC_MBSSID(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27)\n#define IE2_SET_TX_DESC_MBSSID_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27)\n#define IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie)                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x7ff, 16)\n#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie, value)                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7ff,    \\\n\t\t16)\n#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET_NO_CLR(txdesc_ie, value)           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7ff,    \\\n\t\t16)\n#define IE2_GET_TX_DESC_RDG_NAV_EXT(txdesc_ie)                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x1, 15)\n#define IE2_SET_TX_DESC_RDG_NAV_EXT(txdesc_ie, value)                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 15)\n#define IE2_SET_TX_DESC_RDG_NAV_EXT_NO_CLR(txdesc_ie, value)                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 15)\n#define IE2_GET_TX_DESC_DROP_ID(txdesc_ie)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x3, 12)\n#define IE2_SET_TX_DESC_DROP_ID(txdesc_ie, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12)\n#define IE2_SET_TX_DESC_DROP_ID_NO_CLR(txdesc_ie, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12)\n#define IE2_GET_TX_DESC_SW_DEFINE(txdesc_ie)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0xfff, 0)\n#define IE2_SET_TX_DESC_SW_DEFINE(txdesc_ie, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0)\n#define IE2_SET_TX_DESC_SW_DEFINE_NO_CLR(txdesc_ie, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0)\n#define IE3_GET_TX_DESC_IE_END(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 31)\n#define IE3_SET_TX_DESC_IE_END(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)\n#define IE3_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)\n#define IE3_GET_TX_DESC_IE_UP(txdesc_ie)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 30)\n#define IE3_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)\n#define IE3_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)\n#define IE3_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0xf, 24)\n#define IE3_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)\n#define IE3_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)\n#define IE3_GET_TX_DESC_DATA_SC(txdesc_ie)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0xf, 20)\n#define IE3_SET_TX_DESC_DATA_SC(txdesc_ie, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 20)\n#define IE3_SET_TX_DESC_DATA_SC_NO_CLR(txdesc_ie, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 20)\n#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie)                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0xf, 16)\n#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie, value)                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 16)\n#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC_NO_CLR(txdesc_ie, value)           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 16)\n#define IE3_GET_TX_DESC_CTRL_CNT(txdesc_ie)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0xf, 8)\n#define IE3_SET_TX_DESC_CTRL_CNT(txdesc_ie, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 8)\n#define IE3_SET_TX_DESC_CTRL_CNT_NO_CLR(txdesc_ie, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 8)\n#define IE3_GET_TX_DESC_CTRL_CNT_VALID(txdesc_ie)                              \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 1)\n#define IE3_SET_TX_DESC_CTRL_CNT_VALID(txdesc_ie, value)                       \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)\n#define IE3_SET_TX_DESC_CTRL_CNT_VALID_NO_CLR(txdesc_ie, value)                \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)\n#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie)                         \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 0)\n#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie, value)                  \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)\n#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN_NO_CLR(txdesc_ie, value)           \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)\n#define IE3_GET_TX_DESC_G_ID(txdesc_ie)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x3f, 24)\n#define IE3_SET_TX_DESC_G_ID(txdesc_ie, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 24)\n#define IE3_SET_TX_DESC_G_ID_NO_CLR(txdesc_ie, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 24)\n#define IE3_GET_TX_DESC_SND_TARGET(txdesc_ie)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0xff, 16)\n#define IE3_SET_TX_DESC_SND_TARGET(txdesc_ie, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 16)\n#define IE3_SET_TX_DESC_SND_TARGET_NO_CLR(txdesc_ie, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 16)\n#define IE3_GET_TX_DESC_CCA_RTS(txdesc_ie)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x3, 11)\n#define IE3_SET_TX_DESC_CCA_RTS(txdesc_ie, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 11)\n#define IE3_SET_TX_DESC_CCA_RTS_NO_CLR(txdesc_ie, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 11)\n#define IE3_GET_TX_DESC_SND_PKT_SEL(txdesc_ie)                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x3, 9)\n#define IE3_SET_TX_DESC_SND_PKT_SEL(txdesc_ie, value)                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 9)\n#define IE3_SET_TX_DESC_SND_PKT_SEL_NO_CLR(txdesc_ie, value)                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 9)\n#define IE3_GET_TX_DESC_NDPA(txdesc_ie)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x3, 7)\n#define IE3_SET_TX_DESC_NDPA(txdesc_ie, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 7)\n#define IE3_SET_TX_DESC_NDPA_NO_CLR(txdesc_ie, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 7)\n#define IE3_GET_TX_DESC_MU_DATARATE(txdesc_ie)                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x7f, 0)\n#define IE3_SET_TX_DESC_MU_DATARATE(txdesc_ie, value)                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0)\n#define IE3_SET_TX_DESC_MU_DATARATE_NO_CLR(txdesc_ie, value)                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0)\n#define IE4_GET_TX_DESC_IE_END(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 31)\n#define IE4_SET_TX_DESC_IE_END(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)\n#define IE4_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)\n#define IE4_GET_TX_DESC_IE_UP(txdesc_ie)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 30)\n#define IE4_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)\n#define IE4_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)\n#define IE4_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0xf, 24)\n#define IE4_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)\n#define IE4_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)\n#define IE4_GET_TX_DESC_VCS_STBC(txdesc_ie)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x3, 10)\n#define IE4_SET_TX_DESC_VCS_STBC(txdesc_ie, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 10)\n#define IE4_SET_TX_DESC_VCS_STBC_NO_CLR(txdesc_ie, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 10)\n#define IE4_GET_TX_DESC_DATA_STBC(txdesc_ie)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x3, 8)\n#define IE4_SET_TX_DESC_DATA_STBC(txdesc_ie, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 8)\n#define IE4_SET_TX_DESC_DATA_STBC_NO_CLR(txdesc_ie, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 8)\n#define IE4_GET_TX_DESC_DATA_LDPC(txdesc_ie)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 2)\n#define IE4_SET_TX_DESC_DATA_LDPC(txdesc_ie, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)\n#define IE4_SET_TX_DESC_DATA_LDPC_NO_CLR(txdesc_ie, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)\n#define IE4_GET_TX_DESC_GF(txdesc_ie)                                          \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 1)\n#define IE4_SET_TX_DESC_GF(txdesc_ie, value)                                   \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)\n#define IE4_SET_TX_DESC_GF_NO_CLR(txdesc_ie, value)                            \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)\n#define IE4_GET_TX_DESC_LSIG_TXOP_EN(txdesc_ie)                                \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 0)\n#define IE4_SET_TX_DESC_LSIG_TXOP_EN(txdesc_ie, value)                         \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)\n#define IE4_SET_TX_DESC_LSIG_TXOP_EN_NO_CLR(txdesc_ie, value)                  \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)\n#define IE4_GET_TX_DESC_PATH_MAPA(txdesc_ie)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x3, 30)\n#define IE4_SET_TX_DESC_PATH_MAPA(txdesc_ie, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 30)\n#define IE4_SET_TX_DESC_PATH_MAPA_NO_CLR(txdesc_ie, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 30)\n#define IE4_GET_TX_DESC_PATH_MAPB(txdesc_ie)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x3, 28)\n#define IE4_SET_TX_DESC_PATH_MAPB(txdesc_ie, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 28)\n#define IE4_SET_TX_DESC_PATH_MAPB_NO_CLR(txdesc_ie, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 28)\n#define IE4_GET_TX_DESC_PATH_MAPC(txdesc_ie)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x3, 26)\n#define IE4_SET_TX_DESC_PATH_MAPC(txdesc_ie, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 26)\n#define IE4_SET_TX_DESC_PATH_MAPC_NO_CLR(txdesc_ie, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 26)\n#define IE4_GET_TX_DESC_PATH_MAPD(txdesc_ie)                                   \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x3, 24)\n#define IE4_SET_TX_DESC_PATH_MAPD(txdesc_ie, value)                            \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 24)\n#define IE4_SET_TX_DESC_PATH_MAPD_NO_CLR(txdesc_ie, value)                     \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 24)\n#define IE4_GET_TX_DESC_ANTSEL_A(txdesc_ie)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0xf, 20)\n#define IE4_SET_TX_DESC_ANTSEL_A(txdesc_ie, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 20)\n#define IE4_SET_TX_DESC_ANTSEL_A_NO_CLR(txdesc_ie, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 20)\n#define IE4_GET_TX_DESC_ANTSEL_B(txdesc_ie)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0xf, 16)\n#define IE4_SET_TX_DESC_ANTSEL_B(txdesc_ie, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 16)\n#define IE4_SET_TX_DESC_ANTSEL_B_NO_CLR(txdesc_ie, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 16)\n#define IE4_GET_TX_DESC_ANTSEL_C(txdesc_ie)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0xf, 12)\n#define IE4_SET_TX_DESC_ANTSEL_C(txdesc_ie, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 12)\n#define IE4_SET_TX_DESC_ANTSEL_C_NO_CLR(txdesc_ie, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 12)\n#define IE4_GET_TX_DESC_ANTSEL_D(txdesc_ie)                                    \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0xf, 8)\n#define IE4_SET_TX_DESC_ANTSEL_D(txdesc_ie, value)                             \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 8)\n#define IE4_SET_TX_DESC_ANTSEL_D_NO_CLR(txdesc_ie, value)                      \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 8)\n#define IE4_GET_TX_DESC_NTX_PATH_EN(txdesc_ie)                                 \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0xf, 4)\n#define IE4_SET_TX_DESC_NTX_PATH_EN(txdesc_ie, value)                          \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 4)\n#define IE4_SET_TX_DESC_NTX_PATH_EN_NO_CLR(txdesc_ie, value)                   \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 4)\n#define IE4_GET_TX_DESC_ANTLSEL_EN(txdesc_ie)                                  \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x1, 3)\n#define IE4_SET_TX_DESC_ANTLSEL_EN(txdesc_ie, value)                           \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 3)\n#define IE4_SET_TX_DESC_ANTLSEL_EN_NO_CLR(txdesc_ie, value)                    \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 3)\n#define IE4_GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie)                            \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x3, 0)\n#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie, value)                     \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 0)\n#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE_NO_CLR(txdesc_ie, value)              \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 0)\n#define IE5_GET_TX_DESC_IE_END(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 31)\n#define IE5_SET_TX_DESC_IE_END(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)\n#define IE5_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)\n#define IE5_GET_TX_DESC_IE_UP(txdesc_ie)                                       \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1, 30)\n#define IE5_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)\n#define IE5_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value)                         \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)\n#define IE5_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0xf, 24)\n#define IE5_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)\n#define IE5_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)\n#define IE5_GET_TX_DESC_LEN1_L(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x7f, 17)\n#define IE5_SET_TX_DESC_LEN1_L(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7f, 17)\n#define IE5_SET_TX_DESC_LEN1_L_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7f, 17)\n#define IE5_GET_TX_DESC_LEN0(txdesc_ie)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0x1fff, 4)\n#define IE5_SET_TX_DESC_LEN0(txdesc_ie, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1fff,   \\\n\t\t4)\n#define IE5_SET_TX_DESC_LEN0_NO_CLR(txdesc_ie, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1fff,   \\\n\t\t4)\n#define IE5_GET_TX_DESC_PKT_NUM(txdesc_ie)                                     \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \\\n\t\t\t      0xf, 0)\n#define IE5_SET_TX_DESC_PKT_NUM(txdesc_ie, value)                              \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 0)\n#define IE5_SET_TX_DESC_PKT_NUM_NO_CLR(txdesc_ie, value)                       \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 0)\n#define IE5_GET_TX_DESC_LEN3(txdesc_ie)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x1fff, 19)\n#define IE5_SET_TX_DESC_LEN3(txdesc_ie, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff,   \\\n\t\t19)\n#define IE5_SET_TX_DESC_LEN3_NO_CLR(txdesc_ie, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff,   \\\n\t\t19)\n#define IE5_GET_TX_DESC_LEN2(txdesc_ie)                                        \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x1fff, 6)\n#define IE5_SET_TX_DESC_LEN2(txdesc_ie, value)                                 \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff,   \\\n\t\t6)\n#define IE5_SET_TX_DESC_LEN2_NO_CLR(txdesc_ie, value)                          \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff,   \\\n\t\t6)\n#define IE5_GET_TX_DESC_LEN1_H(txdesc_ie)                                      \\\n\tHALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \\\n\t\t\t      0x3f, 0)\n#define IE5_SET_TX_DESC_LEN1_H(txdesc_ie, value)                               \\\n\tHALMAC_SET_DESC_FIELD_CLR(                                             \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 0)\n#define IE5_SET_TX_DESC_LEN1_H_NO_CLR(txdesc_ie, value)                        \\\n\tHALMAC_SET_DESC_FIELD_NO_CLR(                                          \\\n\t\t((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 0)\n\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_tx_desc_ie_chip.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_TX_DESC_IE_CHIP_H_\n#define _HALMAC_TX_DESC_IE_CHIP_H_\n#if (HALMAC_8814B_SUPPORT)\n\n#define IE0_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \\\n\tIE0_GET_TX_DESC_IE_END(txdesc_ie)\n#define IE0_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \\\n\tIE0_SET_TX_DESC_IE_END(txdesc_ie, value)\n#define IE0_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE0_GET_TX_DESC_IE_UP(txdesc_ie)\n#define IE0_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \\\n\tIE0_SET_TX_DESC_IE_UP(txdesc_ie, value)\n#define IE0_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \\\n\tIE0_GET_TX_DESC_IE_NUM(txdesc_ie)\n#define IE0_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \\\n\tIE0_SET_TX_DESC_IE_NUM(txdesc_ie, value)\n#define IE0_GET_TX_DESC_ARFR_TABLE_SEL_8814B(txdesc_ie)                        \\\n\tIE0_GET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie)\n#define IE0_SET_TX_DESC_ARFR_TABLE_SEL_8814B(txdesc_ie, value)                 \\\n\tIE0_SET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie, value)\n#define IE0_GET_TX_DESC_ARFR_HT_EN_8814B(txdesc_ie)                            \\\n\tIE0_GET_TX_DESC_ARFR_HT_EN(txdesc_ie)\n#define IE0_SET_TX_DESC_ARFR_HT_EN_8814B(txdesc_ie, value)                     \\\n\tIE0_SET_TX_DESC_ARFR_HT_EN(txdesc_ie, value)\n#define IE0_GET_TX_DESC_ARFR_OFDM_EN_8814B(txdesc_ie)                          \\\n\tIE0_GET_TX_DESC_ARFR_OFDM_EN(txdesc_ie)\n#define IE0_SET_TX_DESC_ARFR_OFDM_EN_8814B(txdesc_ie, value)                   \\\n\tIE0_SET_TX_DESC_ARFR_OFDM_EN(txdesc_ie, value)\n#define IE0_GET_TX_DESC_ARFR_CCK_EN_8814B(txdesc_ie)                           \\\n\tIE0_GET_TX_DESC_ARFR_CCK_EN(txdesc_ie)\n#define IE0_SET_TX_DESC_ARFR_CCK_EN_8814B(txdesc_ie, value)                    \\\n\tIE0_SET_TX_DESC_ARFR_CCK_EN(txdesc_ie, value)\n#define IE0_GET_TX_DESC_HW_RTS_EN_8814B(txdesc_ie)                             \\\n\tIE0_GET_TX_DESC_HW_RTS_EN(txdesc_ie)\n#define IE0_SET_TX_DESC_HW_RTS_EN_8814B(txdesc_ie, value)                      \\\n\tIE0_SET_TX_DESC_HW_RTS_EN(txdesc_ie, value)\n#define IE0_GET_TX_DESC_RTS_EN_8814B(txdesc_ie)                                \\\n\tIE0_GET_TX_DESC_RTS_EN(txdesc_ie)\n#define IE0_SET_TX_DESC_RTS_EN_8814B(txdesc_ie, value)                         \\\n\tIE0_SET_TX_DESC_RTS_EN(txdesc_ie, value)\n#define IE0_GET_TX_DESC_CTS2SELF_8814B(txdesc_ie)                              \\\n\tIE0_GET_TX_DESC_CTS2SELF(txdesc_ie)\n#define IE0_SET_TX_DESC_CTS2SELF_8814B(txdesc_ie, value)                       \\\n\tIE0_SET_TX_DESC_CTS2SELF(txdesc_ie, value)\n#define IE0_GET_TX_DESC_RTY_LMT_EN_8814B(txdesc_ie)                            \\\n\tIE0_GET_TX_DESC_RTY_LMT_EN(txdesc_ie)\n#define IE0_SET_TX_DESC_RTY_LMT_EN_8814B(txdesc_ie, value)                     \\\n\tIE0_SET_TX_DESC_RTY_LMT_EN(txdesc_ie, value)\n#define IE0_GET_TX_DESC_RTS_SHORT_8814B(txdesc_ie)                             \\\n\tIE0_GET_TX_DESC_RTS_SHORT(txdesc_ie)\n#define IE0_SET_TX_DESC_RTS_SHORT_8814B(txdesc_ie, value)                      \\\n\tIE0_SET_TX_DESC_RTS_SHORT(txdesc_ie, value)\n#define IE0_GET_TX_DESC_DISDATAFB_8814B(txdesc_ie)                             \\\n\tIE0_GET_TX_DESC_DISDATAFB(txdesc_ie)\n#define IE0_SET_TX_DESC_DISDATAFB_8814B(txdesc_ie, value)                      \\\n\tIE0_SET_TX_DESC_DISDATAFB(txdesc_ie, value)\n#define IE0_GET_TX_DESC_DISRTSFB_8814B(txdesc_ie)                              \\\n\tIE0_GET_TX_DESC_DISRTSFB(txdesc_ie)\n#define IE0_SET_TX_DESC_DISRTSFB_8814B(txdesc_ie, value)                       \\\n\tIE0_SET_TX_DESC_DISRTSFB(txdesc_ie, value)\n#define IE0_GET_TX_DESC_DATA_SHORT_8814B(txdesc_ie)                            \\\n\tIE0_GET_TX_DESC_DATA_SHORT(txdesc_ie)\n#define IE0_SET_TX_DESC_DATA_SHORT_8814B(txdesc_ie, value)                     \\\n\tIE0_SET_TX_DESC_DATA_SHORT(txdesc_ie, value)\n#define IE0_GET_TX_DESC_TRY_RATE_8814B(txdesc_ie)                              \\\n\tIE0_GET_TX_DESC_TRY_RATE(txdesc_ie)\n#define IE0_SET_TX_DESC_TRY_RATE_8814B(txdesc_ie, value)                       \\\n\tIE0_SET_TX_DESC_TRY_RATE(txdesc_ie, value)\n#define IE0_GET_TX_DESC_USERATE_8814B(txdesc_ie)                               \\\n\tIE0_GET_TX_DESC_USERATE(txdesc_ie)\n#define IE0_SET_TX_DESC_USERATE_8814B(txdesc_ie, value)                        \\\n\tIE0_SET_TX_DESC_USERATE(txdesc_ie, value)\n#define IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE_8814B(txdesc_ie)                   \\\n\tIE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie)\n#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE_8814B(txdesc_ie, value)            \\\n\tIE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie, value)\n#define IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE_8814B(txdesc_ie)                  \\\n\tIE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie)\n#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE_8814B(txdesc_ie, value)           \\\n\tIE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie, value)\n#define IE0_GET_TX_DESC_RTS_DATA_RTY_LMT_8814B(txdesc_ie)                      \\\n\tIE0_GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie)\n#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT_8814B(txdesc_ie, value)               \\\n\tIE0_SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie, value)\n#define IE0_GET_TX_DESC_DATA_BW_8814B(txdesc_ie)                               \\\n\tIE0_GET_TX_DESC_DATA_BW(txdesc_ie)\n#define IE0_SET_TX_DESC_DATA_BW_8814B(txdesc_ie, value)                        \\\n\tIE0_SET_TX_DESC_DATA_BW(txdesc_ie, value)\n#define IE0_GET_TX_DESC_RTSRATE_8814B(txdesc_ie)                               \\\n\tIE0_GET_TX_DESC_RTSRATE(txdesc_ie)\n#define IE0_SET_TX_DESC_RTSRATE_8814B(txdesc_ie, value)                        \\\n\tIE0_SET_TX_DESC_RTSRATE(txdesc_ie, value)\n#define IE0_GET_TX_DESC_DATARATE_8814B(txdesc_ie)                              \\\n\tIE0_GET_TX_DESC_DATARATE(txdesc_ie)\n#define IE0_SET_TX_DESC_DATARATE_8814B(txdesc_ie, value)                       \\\n\tIE0_SET_TX_DESC_DATARATE(txdesc_ie, value)\n#define IE1_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \\\n\tIE1_GET_TX_DESC_IE_END(txdesc_ie)\n#define IE1_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \\\n\tIE1_SET_TX_DESC_IE_END(txdesc_ie, value)\n#define IE1_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE1_GET_TX_DESC_IE_UP(txdesc_ie)\n#define IE1_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \\\n\tIE1_SET_TX_DESC_IE_UP(txdesc_ie, value)\n#define IE1_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \\\n\tIE1_GET_TX_DESC_IE_NUM(txdesc_ie)\n#define IE1_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \\\n\tIE1_SET_TX_DESC_IE_NUM(txdesc_ie, value)\n#define IE1_GET_TX_DESC_AMPDU_DENSITY_8814B(txdesc_ie)                         \\\n\tIE1_GET_TX_DESC_AMPDU_DENSITY(txdesc_ie)\n#define IE1_SET_TX_DESC_AMPDU_DENSITY_8814B(txdesc_ie, value)                  \\\n\tIE1_SET_TX_DESC_AMPDU_DENSITY(txdesc_ie, value)\n#define IE1_GET_TX_DESC_MAX_AGG_NUM_8814B(txdesc_ie)                           \\\n\tIE1_GET_TX_DESC_MAX_AGG_NUM(txdesc_ie)\n#define IE1_SET_TX_DESC_MAX_AGG_NUM_8814B(txdesc_ie, value)                    \\\n\tIE1_SET_TX_DESC_MAX_AGG_NUM(txdesc_ie, value)\n#define IE1_GET_TX_DESC_SECTYPE_8814B(txdesc_ie)                               \\\n\tIE1_GET_TX_DESC_SECTYPE(txdesc_ie)\n#define IE1_SET_TX_DESC_SECTYPE_8814B(txdesc_ie, value)                        \\\n\tIE1_SET_TX_DESC_SECTYPE(txdesc_ie, value)\n#define IE1_GET_TX_DESC_MOREFRAG_8814B(txdesc_ie)                              \\\n\tIE1_GET_TX_DESC_MOREFRAG(txdesc_ie)\n#define IE1_SET_TX_DESC_MOREFRAG_8814B(txdesc_ie, value)                       \\\n\tIE1_SET_TX_DESC_MOREFRAG(txdesc_ie, value)\n#define IE1_GET_TX_DESC_NOACM_8814B(txdesc_ie) IE1_GET_TX_DESC_NOACM(txdesc_ie)\n#define IE1_SET_TX_DESC_NOACM_8814B(txdesc_ie, value)                          \\\n\tIE1_SET_TX_DESC_NOACM(txdesc_ie, value)\n#define IE1_GET_TX_DESC_BCNPKT_TSF_CTRL_8814B(txdesc_ie)                       \\\n\tIE1_GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie)\n#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL_8814B(txdesc_ie, value)                \\\n\tIE1_SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie, value)\n#define IE1_GET_TX_DESC_NAVUSEHDR_8814B(txdesc_ie)                             \\\n\tIE1_GET_TX_DESC_NAVUSEHDR(txdesc_ie)\n#define IE1_SET_TX_DESC_NAVUSEHDR_8814B(txdesc_ie, value)                      \\\n\tIE1_SET_TX_DESC_NAVUSEHDR(txdesc_ie, value)\n#define IE1_GET_TX_DESC_HTC_8814B(txdesc_ie) IE1_GET_TX_DESC_HTC(txdesc_ie)\n#define IE1_SET_TX_DESC_HTC_8814B(txdesc_ie, value)                            \\\n\tIE1_SET_TX_DESC_HTC(txdesc_ie, value)\n#define IE1_GET_TX_DESC_BMC_8814B(txdesc_ie) IE1_GET_TX_DESC_BMC(txdesc_ie)\n#define IE1_SET_TX_DESC_BMC_8814B(txdesc_ie, value)                            \\\n\tIE1_SET_TX_DESC_BMC(txdesc_ie, value)\n#define IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS_8814B(txdesc_ie)                     \\\n\tIE1_GET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie)\n#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS_8814B(txdesc_ie, value)              \\\n\tIE1_SET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie, value)\n#define IE1_GET_TX_DESC_USE_MAX_TIME_EN_8814B(txdesc_ie)                       \\\n\tIE1_GET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie)\n#define IE1_SET_TX_DESC_USE_MAX_TIME_EN_8814B(txdesc_ie, value)                \\\n\tIE1_SET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie, value)\n#define IE1_GET_TX_DESC_HW_SSN_SEL_8814B(txdesc_ie)                            \\\n\tIE1_GET_TX_DESC_HW_SSN_SEL(txdesc_ie)\n#define IE1_SET_TX_DESC_HW_SSN_SEL_8814B(txdesc_ie, value)                     \\\n\tIE1_SET_TX_DESC_HW_SSN_SEL(txdesc_ie, value)\n#define IE1_GET_TX_DESC_DISQSELSEQ_8814B(txdesc_ie)                            \\\n\tIE1_GET_TX_DESC_DISQSELSEQ(txdesc_ie)\n#define IE1_SET_TX_DESC_DISQSELSEQ_8814B(txdesc_ie, value)                     \\\n\tIE1_SET_TX_DESC_DISQSELSEQ(txdesc_ie, value)\n#define IE1_GET_TX_DESC_EN_HWSEQ_8814B(txdesc_ie)                              \\\n\tIE1_GET_TX_DESC_EN_HWSEQ(txdesc_ie)\n#define IE1_SET_TX_DESC_EN_HWSEQ_8814B(txdesc_ie, value)                       \\\n\tIE1_SET_TX_DESC_EN_HWSEQ(txdesc_ie, value)\n#define IE1_GET_TX_DESC_EN_HWEXSEQ_8814B(txdesc_ie)                            \\\n\tIE1_GET_TX_DESC_EN_HWEXSEQ(txdesc_ie)\n#define IE1_SET_TX_DESC_EN_HWEXSEQ_8814B(txdesc_ie, value)                     \\\n\tIE1_SET_TX_DESC_EN_HWEXSEQ(txdesc_ie, value)\n#define IE1_GET_TX_DESC_EN_DESC_ID_8814B(txdesc_ie)                            \\\n\tIE1_GET_TX_DESC_EN_DESC_ID(txdesc_ie)\n#define IE1_SET_TX_DESC_EN_DESC_ID_8814B(txdesc_ie, value)                     \\\n\tIE1_SET_TX_DESC_EN_DESC_ID(txdesc_ie, value)\n#define IE1_GET_TX_DESC_AMPDU_MAX_TIME_8814B(txdesc_ie)                        \\\n\tIE1_GET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie)\n#define IE1_SET_TX_DESC_AMPDU_MAX_TIME_8814B(txdesc_ie, value)                 \\\n\tIE1_SET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie, value)\n#define IE1_GET_TX_DESC_P_AID_8814B(txdesc_ie) IE1_GET_TX_DESC_P_AID(txdesc_ie)\n#define IE1_SET_TX_DESC_P_AID_8814B(txdesc_ie, value)                          \\\n\tIE1_SET_TX_DESC_P_AID(txdesc_ie, value)\n#define IE1_GET_TX_DESC_MOREDATA_8814B(txdesc_ie)                              \\\n\tIE1_GET_TX_DESC_MOREDATA(txdesc_ie)\n#define IE1_SET_TX_DESC_MOREDATA_8814B(txdesc_ie, value)                       \\\n\tIE1_SET_TX_DESC_MOREDATA(txdesc_ie, value)\n#define IE1_GET_TX_DESC_SW_SEQ_8814B(txdesc_ie)                                \\\n\tIE1_GET_TX_DESC_SW_SEQ(txdesc_ie)\n#define IE1_SET_TX_DESC_SW_SEQ_8814B(txdesc_ie, value)                         \\\n\tIE1_SET_TX_DESC_SW_SEQ(txdesc_ie, value)\n#define IE2_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \\\n\tIE2_GET_TX_DESC_IE_END(txdesc_ie)\n#define IE2_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \\\n\tIE2_SET_TX_DESC_IE_END(txdesc_ie, value)\n#define IE2_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE2_GET_TX_DESC_IE_UP(txdesc_ie)\n#define IE2_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \\\n\tIE2_SET_TX_DESC_IE_UP(txdesc_ie, value)\n#define IE2_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \\\n\tIE2_GET_TX_DESC_IE_NUM(txdesc_ie)\n#define IE2_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \\\n\tIE2_SET_TX_DESC_IE_NUM(txdesc_ie, value)\n#define IE2_GET_TX_DESC_ADDR_CAM_8814B(txdesc_ie)                              \\\n\tIE2_GET_TX_DESC_ADDR_CAM(txdesc_ie)\n#define IE2_SET_TX_DESC_ADDR_CAM_8814B(txdesc_ie, value)                       \\\n\tIE2_SET_TX_DESC_ADDR_CAM(txdesc_ie, value)\n#define IE2_GET_TX_DESC_MULTIPLE_PORT_8814B(txdesc_ie)                         \\\n\tIE2_GET_TX_DESC_MULTIPLE_PORT(txdesc_ie)\n#define IE2_SET_TX_DESC_MULTIPLE_PORT_8814B(txdesc_ie, value)                  \\\n\tIE2_SET_TX_DESC_MULTIPLE_PORT(txdesc_ie, value)\n#define IE2_GET_TX_DESC_RAW_8814B(txdesc_ie) IE2_GET_TX_DESC_RAW(txdesc_ie)\n#define IE2_SET_TX_DESC_RAW_8814B(txdesc_ie, value)                            \\\n\tIE2_SET_TX_DESC_RAW(txdesc_ie, value)\n#define IE2_GET_TX_DESC_RDG_EN_8814B(txdesc_ie)                                \\\n\tIE2_GET_TX_DESC_RDG_EN(txdesc_ie)\n#define IE2_SET_TX_DESC_RDG_EN_8814B(txdesc_ie, value)                         \\\n\tIE2_SET_TX_DESC_RDG_EN(txdesc_ie, value)\n#define IE2_GET_TX_DESC_SPECIAL_CW_8814B(txdesc_ie)                            \\\n\tIE2_GET_TX_DESC_SPECIAL_CW(txdesc_ie)\n#define IE2_SET_TX_DESC_SPECIAL_CW_8814B(txdesc_ie, value)                     \\\n\tIE2_SET_TX_DESC_SPECIAL_CW(txdesc_ie, value)\n#define IE2_GET_TX_DESC_POLLUTED_8814B(txdesc_ie)                              \\\n\tIE2_GET_TX_DESC_POLLUTED(txdesc_ie)\n#define IE2_SET_TX_DESC_POLLUTED_8814B(txdesc_ie, value)                       \\\n\tIE2_SET_TX_DESC_POLLUTED(txdesc_ie, value)\n#define IE2_GET_TX_DESC_BT_NULL_8814B(txdesc_ie)                               \\\n\tIE2_GET_TX_DESC_BT_NULL(txdesc_ie)\n#define IE2_SET_TX_DESC_BT_NULL_8814B(txdesc_ie, value)                        \\\n\tIE2_SET_TX_DESC_BT_NULL(txdesc_ie, value)\n#define IE2_GET_TX_DESC_NULL_1_8814B(txdesc_ie)                                \\\n\tIE2_GET_TX_DESC_NULL_1(txdesc_ie)\n#define IE2_SET_TX_DESC_NULL_1_8814B(txdesc_ie, value)                         \\\n\tIE2_SET_TX_DESC_NULL_1(txdesc_ie, value)\n#define IE2_GET_TX_DESC_NULL_0_8814B(txdesc_ie)                                \\\n\tIE2_GET_TX_DESC_NULL_0(txdesc_ie)\n#define IE2_SET_TX_DESC_NULL_0_8814B(txdesc_ie, value)                         \\\n\tIE2_SET_TX_DESC_NULL_0(txdesc_ie, value)\n#define IE2_GET_TX_DESC_TRI_FRAME_8814B(txdesc_ie)                             \\\n\tIE2_GET_TX_DESC_TRI_FRAME(txdesc_ie)\n#define IE2_SET_TX_DESC_TRI_FRAME_8814B(txdesc_ie, value)                      \\\n\tIE2_SET_TX_DESC_TRI_FRAME(txdesc_ie, value)\n#define IE2_GET_TX_DESC_SPE_RPT_8814B(txdesc_ie)                               \\\n\tIE2_GET_TX_DESC_SPE_RPT(txdesc_ie)\n#define IE2_SET_TX_DESC_SPE_RPT_8814B(txdesc_ie, value)                        \\\n\tIE2_SET_TX_DESC_SPE_RPT(txdesc_ie, value)\n#define IE2_GET_TX_DESC_FTM_EN_8814B(txdesc_ie)                                \\\n\tIE2_GET_TX_DESC_FTM_EN(txdesc_ie)\n#define IE2_SET_TX_DESC_FTM_EN_8814B(txdesc_ie, value)                         \\\n\tIE2_SET_TX_DESC_FTM_EN(txdesc_ie, value)\n#define IE2_GET_TX_DESC_MBSSID_8814B(txdesc_ie)                                \\\n\tIE2_GET_TX_DESC_MBSSID(txdesc_ie)\n#define IE2_SET_TX_DESC_MBSSID_8814B(txdesc_ie, value)                         \\\n\tIE2_SET_TX_DESC_MBSSID(txdesc_ie, value)\n#define IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET_8814B(txdesc_ie)                   \\\n\tIE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie)\n#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET_8814B(txdesc_ie, value)            \\\n\tIE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie, value)\n#define IE2_GET_TX_DESC_RDG_NAV_EXT_8814B(txdesc_ie)                           \\\n\tIE2_GET_TX_DESC_RDG_NAV_EXT(txdesc_ie)\n#define IE2_SET_TX_DESC_RDG_NAV_EXT_8814B(txdesc_ie, value)                    \\\n\tIE2_SET_TX_DESC_RDG_NAV_EXT(txdesc_ie, value)\n#define IE2_GET_TX_DESC_DROP_ID_8814B(txdesc_ie)                               \\\n\tIE2_GET_TX_DESC_DROP_ID(txdesc_ie)\n#define IE2_SET_TX_DESC_DROP_ID_8814B(txdesc_ie, value)                        \\\n\tIE2_SET_TX_DESC_DROP_ID(txdesc_ie, value)\n#define IE2_GET_TX_DESC_SW_DEFINE_8814B(txdesc_ie)                             \\\n\tIE2_GET_TX_DESC_SW_DEFINE(txdesc_ie)\n#define IE2_SET_TX_DESC_SW_DEFINE_8814B(txdesc_ie, value)                      \\\n\tIE2_SET_TX_DESC_SW_DEFINE(txdesc_ie, value)\n#define IE3_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \\\n\tIE3_GET_TX_DESC_IE_END(txdesc_ie)\n#define IE3_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \\\n\tIE3_SET_TX_DESC_IE_END(txdesc_ie, value)\n#define IE3_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE3_GET_TX_DESC_IE_UP(txdesc_ie)\n#define IE3_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \\\n\tIE3_SET_TX_DESC_IE_UP(txdesc_ie, value)\n#define IE3_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \\\n\tIE3_GET_TX_DESC_IE_NUM(txdesc_ie)\n#define IE3_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \\\n\tIE3_SET_TX_DESC_IE_NUM(txdesc_ie, value)\n#define IE3_GET_TX_DESC_DATA_SC_8814B(txdesc_ie)                               \\\n\tIE3_GET_TX_DESC_DATA_SC(txdesc_ie)\n#define IE3_SET_TX_DESC_DATA_SC_8814B(txdesc_ie, value)                        \\\n\tIE3_SET_TX_DESC_DATA_SC(txdesc_ie, value)\n#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC_8814B(txdesc_ie)                   \\\n\tIE3_GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie)\n#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC_8814B(txdesc_ie, value)            \\\n\tIE3_SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie, value)\n#define IE3_GET_TX_DESC_CTRL_CNT_8814B(txdesc_ie)                              \\\n\tIE3_GET_TX_DESC_CTRL_CNT(txdesc_ie)\n#define IE3_SET_TX_DESC_CTRL_CNT_8814B(txdesc_ie, value)                       \\\n\tIE3_SET_TX_DESC_CTRL_CNT(txdesc_ie, value)\n#define IE3_GET_TX_DESC_CTRL_CNT_VALID_8814B(txdesc_ie)                        \\\n\tIE3_GET_TX_DESC_CTRL_CNT_VALID(txdesc_ie)\n#define IE3_SET_TX_DESC_CTRL_CNT_VALID_8814B(txdesc_ie, value)                 \\\n\tIE3_SET_TX_DESC_CTRL_CNT_VALID(txdesc_ie, value)\n#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN_8814B(txdesc_ie)                   \\\n\tIE3_GET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie)\n#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN_8814B(txdesc_ie, value)            \\\n\tIE3_SET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie, value)\n#define IE3_GET_TX_DESC_G_ID_8814B(txdesc_ie) IE3_GET_TX_DESC_G_ID(txdesc_ie)\n#define IE3_SET_TX_DESC_G_ID_8814B(txdesc_ie, value)                           \\\n\tIE3_SET_TX_DESC_G_ID(txdesc_ie, value)\n#define IE3_GET_TX_DESC_SND_TARGET_8814B(txdesc_ie)                            \\\n\tIE3_GET_TX_DESC_SND_TARGET(txdesc_ie)\n#define IE3_SET_TX_DESC_SND_TARGET_8814B(txdesc_ie, value)                     \\\n\tIE3_SET_TX_DESC_SND_TARGET(txdesc_ie, value)\n#define IE3_GET_TX_DESC_CCA_RTS_8814B(txdesc_ie)                               \\\n\tIE3_GET_TX_DESC_CCA_RTS(txdesc_ie)\n#define IE3_SET_TX_DESC_CCA_RTS_8814B(txdesc_ie, value)                        \\\n\tIE3_SET_TX_DESC_CCA_RTS(txdesc_ie, value)\n#define IE3_GET_TX_DESC_SND_PKT_SEL_8814B(txdesc_ie)                           \\\n\tIE3_GET_TX_DESC_SND_PKT_SEL(txdesc_ie)\n#define IE3_SET_TX_DESC_SND_PKT_SEL_8814B(txdesc_ie, value)                    \\\n\tIE3_SET_TX_DESC_SND_PKT_SEL(txdesc_ie, value)\n#define IE3_GET_TX_DESC_NDPA_8814B(txdesc_ie) IE3_GET_TX_DESC_NDPA(txdesc_ie)\n#define IE3_SET_TX_DESC_NDPA_8814B(txdesc_ie, value)                           \\\n\tIE3_SET_TX_DESC_NDPA(txdesc_ie, value)\n#define IE3_GET_TX_DESC_MU_DATARATE_8814B(txdesc_ie)                           \\\n\tIE3_GET_TX_DESC_MU_DATARATE(txdesc_ie)\n#define IE3_SET_TX_DESC_MU_DATARATE_8814B(txdesc_ie, value)                    \\\n\tIE3_SET_TX_DESC_MU_DATARATE(txdesc_ie, value)\n#define IE4_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \\\n\tIE4_GET_TX_DESC_IE_END(txdesc_ie)\n#define IE4_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \\\n\tIE4_SET_TX_DESC_IE_END(txdesc_ie, value)\n#define IE4_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE4_GET_TX_DESC_IE_UP(txdesc_ie)\n#define IE4_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \\\n\tIE4_SET_TX_DESC_IE_UP(txdesc_ie, value)\n#define IE4_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \\\n\tIE4_GET_TX_DESC_IE_NUM(txdesc_ie)\n#define IE4_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \\\n\tIE4_SET_TX_DESC_IE_NUM(txdesc_ie, value)\n#define IE4_GET_TX_DESC_VCS_STBC_8814B(txdesc_ie)                              \\\n\tIE4_GET_TX_DESC_VCS_STBC(txdesc_ie)\n#define IE4_SET_TX_DESC_VCS_STBC_8814B(txdesc_ie, value)                       \\\n\tIE4_SET_TX_DESC_VCS_STBC(txdesc_ie, value)\n#define IE4_GET_TX_DESC_DATA_STBC_8814B(txdesc_ie)                             \\\n\tIE4_GET_TX_DESC_DATA_STBC(txdesc_ie)\n#define IE4_SET_TX_DESC_DATA_STBC_8814B(txdesc_ie, value)                      \\\n\tIE4_SET_TX_DESC_DATA_STBC(txdesc_ie, value)\n#define IE4_GET_TX_DESC_DATA_LDPC_8814B(txdesc_ie)                             \\\n\tIE4_GET_TX_DESC_DATA_LDPC(txdesc_ie)\n#define IE4_SET_TX_DESC_DATA_LDPC_8814B(txdesc_ie, value)                      \\\n\tIE4_SET_TX_DESC_DATA_LDPC(txdesc_ie, value)\n#define IE4_GET_TX_DESC_GF_8814B(txdesc_ie) IE4_GET_TX_DESC_GF(txdesc_ie)\n#define IE4_SET_TX_DESC_GF_8814B(txdesc_ie, value)                             \\\n\tIE4_SET_TX_DESC_GF(txdesc_ie, value)\n#define IE4_GET_TX_DESC_LSIG_TXOP_EN_8814B(txdesc_ie)                          \\\n\tIE4_GET_TX_DESC_LSIG_TXOP_EN(txdesc_ie)\n#define IE4_SET_TX_DESC_LSIG_TXOP_EN_8814B(txdesc_ie, value)                   \\\n\tIE4_SET_TX_DESC_LSIG_TXOP_EN(txdesc_ie, value)\n#define IE4_GET_TX_DESC_PATH_MAPA_8814B(txdesc_ie)                             \\\n\tIE4_GET_TX_DESC_PATH_MAPA(txdesc_ie)\n#define IE4_SET_TX_DESC_PATH_MAPA_8814B(txdesc_ie, value)                      \\\n\tIE4_SET_TX_DESC_PATH_MAPA(txdesc_ie, value)\n#define IE4_GET_TX_DESC_PATH_MAPB_8814B(txdesc_ie)                             \\\n\tIE4_GET_TX_DESC_PATH_MAPB(txdesc_ie)\n#define IE4_SET_TX_DESC_PATH_MAPB_8814B(txdesc_ie, value)                      \\\n\tIE4_SET_TX_DESC_PATH_MAPB(txdesc_ie, value)\n#define IE4_GET_TX_DESC_PATH_MAPC_8814B(txdesc_ie)                             \\\n\tIE4_GET_TX_DESC_PATH_MAPC(txdesc_ie)\n#define IE4_SET_TX_DESC_PATH_MAPC_8814B(txdesc_ie, value)                      \\\n\tIE4_SET_TX_DESC_PATH_MAPC(txdesc_ie, value)\n#define IE4_GET_TX_DESC_PATH_MAPD_8814B(txdesc_ie)                             \\\n\tIE4_GET_TX_DESC_PATH_MAPD(txdesc_ie)\n#define IE4_SET_TX_DESC_PATH_MAPD_8814B(txdesc_ie, value)                      \\\n\tIE4_SET_TX_DESC_PATH_MAPD(txdesc_ie, value)\n#define IE4_GET_TX_DESC_ANTSEL_A_8814B(txdesc_ie)                              \\\n\tIE4_GET_TX_DESC_ANTSEL_A(txdesc_ie)\n#define IE4_SET_TX_DESC_ANTSEL_A_8814B(txdesc_ie, value)                       \\\n\tIE4_SET_TX_DESC_ANTSEL_A(txdesc_ie, value)\n#define IE4_GET_TX_DESC_ANTSEL_B_8814B(txdesc_ie)                              \\\n\tIE4_GET_TX_DESC_ANTSEL_B(txdesc_ie)\n#define IE4_SET_TX_DESC_ANTSEL_B_8814B(txdesc_ie, value)                       \\\n\tIE4_SET_TX_DESC_ANTSEL_B(txdesc_ie, value)\n#define IE4_GET_TX_DESC_ANTSEL_C_8814B(txdesc_ie)                              \\\n\tIE4_GET_TX_DESC_ANTSEL_C(txdesc_ie)\n#define IE4_SET_TX_DESC_ANTSEL_C_8814B(txdesc_ie, value)                       \\\n\tIE4_SET_TX_DESC_ANTSEL_C(txdesc_ie, value)\n#define IE4_GET_TX_DESC_ANTSEL_D_8814B(txdesc_ie)                              \\\n\tIE4_GET_TX_DESC_ANTSEL_D(txdesc_ie)\n#define IE4_SET_TX_DESC_ANTSEL_D_8814B(txdesc_ie, value)                       \\\n\tIE4_SET_TX_DESC_ANTSEL_D(txdesc_ie, value)\n#define IE4_GET_TX_DESC_NTX_PATH_EN_8814B(txdesc_ie)                           \\\n\tIE4_GET_TX_DESC_NTX_PATH_EN(txdesc_ie)\n#define IE4_SET_TX_DESC_NTX_PATH_EN_8814B(txdesc_ie, value)                    \\\n\tIE4_SET_TX_DESC_NTX_PATH_EN(txdesc_ie, value)\n#define IE4_GET_TX_DESC_ANTLSEL_EN_8814B(txdesc_ie)                            \\\n\tIE4_GET_TX_DESC_ANTLSEL_EN(txdesc_ie)\n#define IE4_SET_TX_DESC_ANTLSEL_EN_8814B(txdesc_ie, value)                     \\\n\tIE4_SET_TX_DESC_ANTLSEL_EN(txdesc_ie, value)\n#define IE4_GET_TX_DESC_TXPWR_OFSET_TYPE_8814B(txdesc_ie)                      \\\n\tIE4_GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie)\n#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE_8814B(txdesc_ie, value)               \\\n\tIE4_SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie, value)\n#define IE5_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \\\n\tIE5_GET_TX_DESC_IE_END(txdesc_ie)\n#define IE5_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \\\n\tIE5_SET_TX_DESC_IE_END(txdesc_ie, value)\n#define IE5_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE5_GET_TX_DESC_IE_UP(txdesc_ie)\n#define IE5_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \\\n\tIE5_SET_TX_DESC_IE_UP(txdesc_ie, value)\n#define IE5_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \\\n\tIE5_GET_TX_DESC_IE_NUM(txdesc_ie)\n#define IE5_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \\\n\tIE5_SET_TX_DESC_IE_NUM(txdesc_ie, value)\n#define IE5_GET_TX_DESC_LEN1_L_8814B(txdesc_ie)                                \\\n\tIE5_GET_TX_DESC_LEN1_L(txdesc_ie)\n#define IE5_SET_TX_DESC_LEN1_L_8814B(txdesc_ie, value)                         \\\n\tIE5_SET_TX_DESC_LEN1_L(txdesc_ie, value)\n#define IE5_GET_TX_DESC_LEN0_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN0(txdesc_ie)\n#define IE5_SET_TX_DESC_LEN0_8814B(txdesc_ie, value)                           \\\n\tIE5_SET_TX_DESC_LEN0(txdesc_ie, value)\n#define IE5_GET_TX_DESC_PKT_NUM_8814B(txdesc_ie)                               \\\n\tIE5_GET_TX_DESC_PKT_NUM(txdesc_ie)\n#define IE5_SET_TX_DESC_PKT_NUM_8814B(txdesc_ie, value)                        \\\n\tIE5_SET_TX_DESC_PKT_NUM(txdesc_ie, value)\n#define IE5_GET_TX_DESC_LEN3_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN3(txdesc_ie)\n#define IE5_SET_TX_DESC_LEN3_8814B(txdesc_ie, value)                           \\\n\tIE5_SET_TX_DESC_LEN3(txdesc_ie, value)\n#define IE5_GET_TX_DESC_LEN2_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN2(txdesc_ie)\n#define IE5_SET_TX_DESC_LEN2_8814B(txdesc_ie, value)                           \\\n\tIE5_SET_TX_DESC_LEN2(txdesc_ie, value)\n#define IE5_GET_TX_DESC_LEN1_H_8814B(txdesc_ie)                                \\\n\tIE5_GET_TX_DESC_LEN1_H(txdesc_ie)\n#define IE5_SET_TX_DESC_LEN1_H_8814B(txdesc_ie, value)                         \\\n\tIE5_SET_TX_DESC_LEN1_H(txdesc_ie, value)\n\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_tx_desc_ie_nic.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_TX_DESC_IE_NIC_H_\n#define _HALMAC_TX_DESC_IE_NIC_H_\n#if (HALMAC_8814B_SUPPORT)\n\n#define IE0_GET_TX_DESC_IE_END(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)\n#define IE0_SET_TX_DESC_IE_END(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)\n#define IE0_GET_TX_DESC_IE_UP(txdesc_ie)                                       \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)\n#define IE0_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)\n#define IE0_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)\n#define IE0_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)\n#define IE0_GET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie)                              \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 19, 1)\n#define IE0_SET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 19, 1, value)\n#define IE0_GET_TX_DESC_ARFR_HT_EN(txdesc_ie)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 18, 1)\n#define IE0_SET_TX_DESC_ARFR_HT_EN(txdesc_ie, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 18, 1, value)\n#define IE0_GET_TX_DESC_ARFR_OFDM_EN(txdesc_ie)                                \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 17, 1)\n#define IE0_SET_TX_DESC_ARFR_OFDM_EN(txdesc_ie, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 17, 1, value)\n#define IE0_GET_TX_DESC_ARFR_CCK_EN(txdesc_ie)                                 \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 1)\n#define IE0_SET_TX_DESC_ARFR_CCK_EN(txdesc_ie, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 1, value)\n#define IE0_GET_TX_DESC_HW_RTS_EN(txdesc_ie)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 9, 1)\n#define IE0_SET_TX_DESC_HW_RTS_EN(txdesc_ie, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 9, 1, value)\n#define IE0_GET_TX_DESC_RTS_EN(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 1)\n#define IE0_SET_TX_DESC_RTS_EN(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 1, value)\n#define IE0_GET_TX_DESC_CTS2SELF(txdesc_ie)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1)\n#define IE0_SET_TX_DESC_CTS2SELF(txdesc_ie, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value)\n#define IE0_GET_TX_DESC_RTY_LMT_EN(txdesc_ie)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1)\n#define IE0_SET_TX_DESC_RTY_LMT_EN(txdesc_ie, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value)\n#define IE0_GET_TX_DESC_RTS_SHORT(txdesc_ie)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 5, 1)\n#define IE0_SET_TX_DESC_RTS_SHORT(txdesc_ie, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 5, 1, value)\n#define IE0_GET_TX_DESC_DISDATAFB(txdesc_ie)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 1)\n#define IE0_SET_TX_DESC_DISDATAFB(txdesc_ie, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 1, value)\n#define IE0_GET_TX_DESC_DISRTSFB(txdesc_ie)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1)\n#define IE0_SET_TX_DESC_DISRTSFB(txdesc_ie, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value)\n#define IE0_GET_TX_DESC_DATA_SHORT(txdesc_ie)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1)\n#define IE0_SET_TX_DESC_DATA_SHORT(txdesc_ie, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value)\n#define IE0_GET_TX_DESC_TRY_RATE(txdesc_ie)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)\n#define IE0_SET_TX_DESC_TRY_RATE(txdesc_ie, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)\n#define IE0_GET_TX_DESC_USERATE(txdesc_ie)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)\n#define IE0_SET_TX_DESC_USERATE(txdesc_ie, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)\n#define IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie)                         \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 27, 4)\n#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie, value)                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 27, 4, value)\n#define IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie)                        \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 22, 5)\n#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie, value)                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 22, 5, value)\n#define IE0_GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie)                            \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 6)\n#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie, value)                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 6, value)\n#define IE0_GET_TX_DESC_DATA_BW(txdesc_ie)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 2)\n#define IE0_SET_TX_DESC_DATA_BW(txdesc_ie, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 2, value)\n#define IE0_GET_TX_DESC_RTSRATE(txdesc_ie)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 7, 4)\n#define IE0_SET_TX_DESC_RTSRATE(txdesc_ie, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 7, 4, value)\n#define IE0_GET_TX_DESC_DATARATE(txdesc_ie)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 7)\n#define IE0_SET_TX_DESC_DATARATE(txdesc_ie, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 7, value)\n#define IE1_GET_TX_DESC_IE_END(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)\n#define IE1_SET_TX_DESC_IE_END(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)\n#define IE1_GET_TX_DESC_IE_UP(txdesc_ie)                                       \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)\n#define IE1_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)\n#define IE1_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)\n#define IE1_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)\n#define IE1_GET_TX_DESC_AMPDU_DENSITY(txdesc_ie)                               \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 21, 3)\n#define IE1_SET_TX_DESC_AMPDU_DENSITY(txdesc_ie, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 21, 3, value)\n#define IE1_GET_TX_DESC_MAX_AGG_NUM(txdesc_ie)                                 \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 5)\n#define IE1_SET_TX_DESC_MAX_AGG_NUM(txdesc_ie, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 5, value)\n#define IE1_GET_TX_DESC_SECTYPE(txdesc_ie)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 14, 2)\n#define IE1_SET_TX_DESC_SECTYPE(txdesc_ie, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 14, 2, value)\n#define IE1_GET_TX_DESC_MOREFRAG(txdesc_ie)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 13, 1)\n#define IE1_SET_TX_DESC_MOREFRAG(txdesc_ie, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 13, 1, value)\n#define IE1_GET_TX_DESC_NOACM(txdesc_ie)                                       \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 12, 1)\n#define IE1_SET_TX_DESC_NOACM(txdesc_ie, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 12, 1, value)\n#define IE1_GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie)                             \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 11, 1)\n#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 11, 1, value)\n#define IE1_GET_TX_DESC_NAVUSEHDR(txdesc_ie)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 1)\n#define IE1_SET_TX_DESC_NAVUSEHDR(txdesc_ie, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 1, value)\n#define IE1_GET_TX_DESC_HTC(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 9, 1)\n#define IE1_SET_TX_DESC_HTC(txdesc_ie, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 9, 1, value)\n#define IE1_GET_TX_DESC_BMC(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 1)\n#define IE1_SET_TX_DESC_BMC(txdesc_ie, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 1, value)\n#define IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie)                           \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1)\n#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value)\n#define IE1_GET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie)                             \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1)\n#define IE1_SET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie, value)                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value)\n#define IE1_GET_TX_DESC_HW_SSN_SEL(txdesc_ie)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 2)\n#define IE1_SET_TX_DESC_HW_SSN_SEL(txdesc_ie, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 2, value)\n#define IE1_GET_TX_DESC_DISQSELSEQ(txdesc_ie)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1)\n#define IE1_SET_TX_DESC_DISQSELSEQ(txdesc_ie, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value)\n#define IE1_GET_TX_DESC_EN_HWSEQ(txdesc_ie)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1)\n#define IE1_SET_TX_DESC_EN_HWSEQ(txdesc_ie, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value)\n#define IE1_GET_TX_DESC_EN_HWEXSEQ(txdesc_ie)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)\n#define IE1_SET_TX_DESC_EN_HWEXSEQ(txdesc_ie, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)\n#define IE1_GET_TX_DESC_EN_DESC_ID(txdesc_ie)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)\n#define IE1_SET_TX_DESC_EN_DESC_ID(txdesc_ie, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)\n#define IE1_GET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie)                              \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 8)\n#define IE1_SET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 8, value)\n#define IE1_GET_TX_DESC_P_AID(txdesc_ie)                                       \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 15, 9)\n#define IE1_SET_TX_DESC_P_AID(txdesc_ie, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 15, 9, value)\n#define IE1_GET_TX_DESC_MOREDATA(txdesc_ie)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 14, 1)\n#define IE1_SET_TX_DESC_MOREDATA(txdesc_ie, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 14, 1, value)\n#define IE1_GET_TX_DESC_SW_SEQ(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 12)\n#define IE1_SET_TX_DESC_SW_SEQ(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 12, value)\n#define IE2_GET_TX_DESC_IE_END(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)\n#define IE2_SET_TX_DESC_IE_END(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)\n#define IE2_GET_TX_DESC_IE_UP(txdesc_ie)                                       \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)\n#define IE2_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)\n#define IE2_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)\n#define IE2_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)\n#define IE2_GET_TX_DESC_ADDR_CAM(txdesc_ie)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 8)\n#define IE2_SET_TX_DESC_ADDR_CAM(txdesc_ie, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 8, value)\n#define IE2_GET_TX_DESC_MULTIPLE_PORT(txdesc_ie)                               \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 12, 3)\n#define IE2_SET_TX_DESC_MULTIPLE_PORT(txdesc_ie, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 12, 3, value)\n#define IE2_GET_TX_DESC_RAW(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 11, 1)\n#define IE2_SET_TX_DESC_RAW(txdesc_ie, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 11, 1, value)\n#define IE2_GET_TX_DESC_RDG_EN(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 1)\n#define IE2_SET_TX_DESC_RDG_EN(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 1, value)\n#define IE2_GET_TX_DESC_SPECIAL_CW(txdesc_ie)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1)\n#define IE2_SET_TX_DESC_SPECIAL_CW(txdesc_ie, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value)\n#define IE2_GET_TX_DESC_POLLUTED(txdesc_ie)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1)\n#define IE2_SET_TX_DESC_POLLUTED(txdesc_ie, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value)\n#define IE2_GET_TX_DESC_BT_NULL(txdesc_ie)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 5, 1)\n#define IE2_SET_TX_DESC_BT_NULL(txdesc_ie, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 5, 1, value)\n#define IE2_GET_TX_DESC_NULL_1(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 1)\n#define IE2_SET_TX_DESC_NULL_1(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 1, value)\n#define IE2_GET_TX_DESC_NULL_0(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1)\n#define IE2_SET_TX_DESC_NULL_0(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value)\n#define IE2_GET_TX_DESC_TRI_FRAME(txdesc_ie)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1)\n#define IE2_SET_TX_DESC_TRI_FRAME(txdesc_ie, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value)\n#define IE2_GET_TX_DESC_SPE_RPT(txdesc_ie)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)\n#define IE2_SET_TX_DESC_SPE_RPT(txdesc_ie, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)\n#define IE2_GET_TX_DESC_FTM_EN(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)\n#define IE2_SET_TX_DESC_FTM_EN(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)\n#define IE2_GET_TX_DESC_MBSSID(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 27, 4)\n#define IE2_SET_TX_DESC_MBSSID(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 27, 4, value)\n#define IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie)                         \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 11)\n#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie, value)                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 11, value)\n#define IE2_GET_TX_DESC_RDG_NAV_EXT(txdesc_ie)                                 \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 15, 1)\n#define IE2_SET_TX_DESC_RDG_NAV_EXT(txdesc_ie, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 15, 1, value)\n#define IE2_GET_TX_DESC_DROP_ID(txdesc_ie)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 2)\n#define IE2_SET_TX_DESC_DROP_ID(txdesc_ie, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 2, value)\n#define IE2_GET_TX_DESC_SW_DEFINE(txdesc_ie)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 12)\n#define IE2_SET_TX_DESC_SW_DEFINE(txdesc_ie, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 12, value)\n#define IE3_GET_TX_DESC_IE_END(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)\n#define IE3_SET_TX_DESC_IE_END(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)\n#define IE3_GET_TX_DESC_IE_UP(txdesc_ie)                                       \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)\n#define IE3_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)\n#define IE3_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)\n#define IE3_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)\n#define IE3_GET_TX_DESC_DATA_SC(txdesc_ie)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 20, 4)\n#define IE3_SET_TX_DESC_DATA_SC(txdesc_ie, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 20, 4, value)\n#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie)                         \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 4)\n#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie, value)                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 4, value)\n#define IE3_GET_TX_DESC_CTRL_CNT(txdesc_ie)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 4)\n#define IE3_SET_TX_DESC_CTRL_CNT(txdesc_ie, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 4, value)\n#define IE3_GET_TX_DESC_CTRL_CNT_VALID(txdesc_ie)                              \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)\n#define IE3_SET_TX_DESC_CTRL_CNT_VALID(txdesc_ie, value)                       \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)\n#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie)                         \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)\n#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie, value)                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)\n#define IE3_GET_TX_DESC_G_ID(txdesc_ie)                                        \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 6)\n#define IE3_SET_TX_DESC_G_ID(txdesc_ie, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 6, value)\n#define IE3_GET_TX_DESC_SND_TARGET(txdesc_ie)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 8)\n#define IE3_SET_TX_DESC_SND_TARGET(txdesc_ie, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 8, value)\n#define IE3_GET_TX_DESC_CCA_RTS(txdesc_ie)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 11, 2)\n#define IE3_SET_TX_DESC_CCA_RTS(txdesc_ie, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 11, 2, value)\n#define IE3_GET_TX_DESC_SND_PKT_SEL(txdesc_ie)                                 \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 9, 2)\n#define IE3_SET_TX_DESC_SND_PKT_SEL(txdesc_ie, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 9, 2, value)\n#define IE3_GET_TX_DESC_NDPA(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 7, 2)\n#define IE3_SET_TX_DESC_NDPA(txdesc_ie, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 7, 2, value)\n#define IE3_GET_TX_DESC_MU_DATARATE(txdesc_ie)                                 \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 7)\n#define IE3_SET_TX_DESC_MU_DATARATE(txdesc_ie, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 7, value)\n#define IE4_GET_TX_DESC_IE_END(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)\n#define IE4_SET_TX_DESC_IE_END(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)\n#define IE4_GET_TX_DESC_IE_UP(txdesc_ie)                                       \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)\n#define IE4_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)\n#define IE4_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)\n#define IE4_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)\n#define IE4_GET_TX_DESC_VCS_STBC(txdesc_ie)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 2)\n#define IE4_SET_TX_DESC_VCS_STBC(txdesc_ie, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 2, value)\n#define IE4_GET_TX_DESC_DATA_STBC(txdesc_ie)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 2)\n#define IE4_SET_TX_DESC_DATA_STBC(txdesc_ie, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 2, value)\n#define IE4_GET_TX_DESC_DATA_LDPC(txdesc_ie)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1)\n#define IE4_SET_TX_DESC_DATA_LDPC(txdesc_ie, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value)\n#define IE4_GET_TX_DESC_GF(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)\n#define IE4_SET_TX_DESC_GF(txdesc_ie, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)\n#define IE4_GET_TX_DESC_LSIG_TXOP_EN(txdesc_ie)                                \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)\n#define IE4_SET_TX_DESC_LSIG_TXOP_EN(txdesc_ie, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)\n#define IE4_GET_TX_DESC_PATH_MAPA(txdesc_ie)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 30, 2)\n#define IE4_SET_TX_DESC_PATH_MAPA(txdesc_ie, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 30, 2, value)\n#define IE4_GET_TX_DESC_PATH_MAPB(txdesc_ie)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 28, 2)\n#define IE4_SET_TX_DESC_PATH_MAPB(txdesc_ie, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 28, 2, value)\n#define IE4_GET_TX_DESC_PATH_MAPC(txdesc_ie)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 26, 2)\n#define IE4_SET_TX_DESC_PATH_MAPC(txdesc_ie, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 26, 2, value)\n#define IE4_GET_TX_DESC_PATH_MAPD(txdesc_ie)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 2)\n#define IE4_SET_TX_DESC_PATH_MAPD(txdesc_ie, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 2, value)\n#define IE4_GET_TX_DESC_ANTSEL_A(txdesc_ie)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 20, 4)\n#define IE4_SET_TX_DESC_ANTSEL_A(txdesc_ie, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 20, 4, value)\n#define IE4_GET_TX_DESC_ANTSEL_B(txdesc_ie)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 4)\n#define IE4_SET_TX_DESC_ANTSEL_B(txdesc_ie, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 4, value)\n#define IE4_GET_TX_DESC_ANTSEL_C(txdesc_ie)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 4)\n#define IE4_SET_TX_DESC_ANTSEL_C(txdesc_ie, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 4, value)\n#define IE4_GET_TX_DESC_ANTSEL_D(txdesc_ie)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 8, 4)\n#define IE4_SET_TX_DESC_ANTSEL_D(txdesc_ie, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 8, 4, value)\n#define IE4_GET_TX_DESC_NTX_PATH_EN(txdesc_ie)                                 \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 4, 4)\n#define IE4_SET_TX_DESC_NTX_PATH_EN(txdesc_ie, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 4, 4, value)\n#define IE4_GET_TX_DESC_ANTLSEL_EN(txdesc_ie)                                  \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 3, 1)\n#define IE4_SET_TX_DESC_ANTLSEL_EN(txdesc_ie, value)                           \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 3, 1, value)\n#define IE4_GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie)                            \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 2)\n#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie, value)                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 2, value)\n#define IE5_GET_TX_DESC_IE_END(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)\n#define IE5_SET_TX_DESC_IE_END(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)\n#define IE5_GET_TX_DESC_IE_UP(txdesc_ie)                                       \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)\n#define IE5_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)\n#define IE5_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)\n#define IE5_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)\n#define IE5_GET_TX_DESC_LEN1_L(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 17, 7)\n#define IE5_SET_TX_DESC_LEN1_L(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 17, 7, value)\n#define IE5_GET_TX_DESC_LEN0(txdesc_ie)                                        \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 13)\n#define IE5_SET_TX_DESC_LEN0(txdesc_ie, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 13, value)\n#define IE5_GET_TX_DESC_PKT_NUM(txdesc_ie)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 4)\n#define IE5_SET_TX_DESC_PKT_NUM(txdesc_ie, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 4, value)\n#define IE5_GET_TX_DESC_LEN3(txdesc_ie)                                        \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 19, 13)\n#define IE5_SET_TX_DESC_LEN3(txdesc_ie, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 19, 13, value)\n#define IE5_GET_TX_DESC_LEN2(txdesc_ie)                                        \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 6, 13)\n#define IE5_SET_TX_DESC_LEN2(txdesc_ie, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 6, 13, value)\n#define IE5_GET_TX_DESC_LEN1_H(txdesc_ie)                                      \\\n\tLE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 6)\n#define IE5_SET_TX_DESC_LEN1_H(txdesc_ie, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 6, value)\n\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_tx_desc_nic.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_TX_DESC_NIC_H_\n#define _HALMAC_TX_DESC_NIC_H_\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n/*TXDESC_WORD0*/\n\n#define SET_TX_DESC_DISQSELSEQ(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value)\n#define GET_TX_DESC_DISQSELSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_IE_END_BODY(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value)\n#define GET_TX_DESC_IE_END_BODY(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_GF(txdesc, value)                                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value)\n#define GET_TX_DESC_GF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_AGG_EN_V1(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value)\n#define GET_TX_DESC_AGG_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_NO_ACM(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value)\n#define GET_TX_DESC_NO_ACM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_BK_V1(txdesc, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value)\n#define GET_TX_DESC_BK_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 28, 1, value)\n#define GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x00, 28, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 27, 1, value)\n#define GET_TX_DESC_AMSDU_PAD_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 27, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_LS(txdesc, value)                                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 26, 1, value)\n#define GET_TX_DESC_LS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 26, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_HTC(txdesc, value)                                         \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 25, 1, value)\n#define GET_TX_DESC_HTC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 25, 1)\n#define SET_TX_DESC_BMC(txdesc, value)                                         \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 1, value)\n#define GET_TX_DESC_BMC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 24, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_PKT_OFFSET_V1(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 5, value)\n#define GET_TX_DESC_PKT_OFFSET_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 24, 5)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_OFFSET(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 16, 8, value)\n#define GET_TX_DESC_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 16, 8)\n#define SET_TX_DESC_TXPKTSIZE(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x00, 0, 16, value)\n#define GET_TX_DESC_TXPKTSIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 0, 16)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n/*WORD1*/\n\n#define SET_TX_DESC_HW_AES_IV_V2(txdesc, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 31, 1, value)\n#define GET_TX_DESC_HW_AES_IV_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 31, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_AMSDU(txdesc, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value)\n#define GET_TX_DESC_AMSDU(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_FTM_EN_V1(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value)\n#define GET_TX_DESC_FTM_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_KEYID_SEL(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value)\n#define GET_TX_DESC_KEYID_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_MOREDATA(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value)\n#define GET_TX_DESC_MOREDATA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_HW_AES_IV_V1(txdesc, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value)\n#define GET_TX_DESC_HW_AES_IV_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1)\n#define SET_TX_DESC_MHR_CP(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 25, 1, value)\n#define GET_TX_DESC_MHR_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 25, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_PKT_OFFSET(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 24, 5, value)\n#define GET_TX_DESC_PKT_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 24, 5)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_SMH_EN_V1(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 24, 1, value)\n#define GET_TX_DESC_SMH_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 24, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_SEC_TYPE(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 22, 2, value)\n#define GET_TX_DESC_SEC_TYPE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 22, 2)\n#define SET_TX_DESC_EN_DESC_ID(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 21, 1, value)\n#define GET_TX_DESC_EN_DESC_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 21, 1)\n#define SET_TX_DESC_RATE_ID(txdesc, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 5, value)\n#define GET_TX_DESC_RATE_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 16, 5)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_SMH_CAM(txdesc, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 8, value)\n#define GET_TX_DESC_SMH_CAM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 16, 8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_PIFS(txdesc, value)                                        \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 15, 1, value)\n#define GET_TX_DESC_PIFS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 15, 1)\n#define SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 14, 1, value)\n#define GET_TX_DESC_LSIG_TXOP_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 14, 1)\n#define SET_TX_DESC_RD_NAV_EXT(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value)\n#define GET_TX_DESC_RD_NAV_EXT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_EXT_EDCA(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value)\n#define GET_TX_DESC_EXT_EDCA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_QSEL(txdesc, value)                                        \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 8, 5, value)\n#define GET_TX_DESC_QSEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 8, 5)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_SPECIAL_CW(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 7, 1, value)\n#define GET_TX_DESC_SPECIAL_CW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 7, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_MACID(txdesc, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 7, value)\n#define GET_TX_DESC_MACID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 7)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_MACID_V1(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 7, value)\n#define GET_TX_DESC_MACID_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 7)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n/*TXDESC_WORD2*/\n\n#define SET_TX_DESC_HW_AES_IV(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value)\n#define GET_TX_DESC_HW_AES_IV(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_CHK_EN_V1(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value)\n#define GET_TX_DESC_CHK_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_FTM_EN(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 30, 1, value)\n#define GET_TX_DESC_FTM_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 30, 1)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANTCEL_D_V1(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 28, 4, value)\n#define GET_TX_DESC_ANTCEL_D_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 28, 4)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_DMA_PRI(txdesc, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 27, 1, value)\n#define GET_TX_DESC_DMA_PRI(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 27, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_G_ID(txdesc, value)                                        \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 6, value)\n#define GET_TX_DESC_G_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 6)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_MAX_AMSDU_MODE(txdesc, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 3, value)\n#define GET_TX_DESC_MAX_AMSDU_MODE(txdesc)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x08, 24, 3)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_C_V1(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 4, value)\n#define GET_TX_DESC_ANTSEL_C_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 4)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_BT_NULL(txdesc, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 23, 1, value)\n#define GET_TX_DESC_BT_NULL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 23, 1)\n#define SET_TX_DESC_AMPDU_DENSITY(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 20, 3, value)\n#define GET_TX_DESC_AMPDU_DENSITY(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 20, 3)\n#define SET_TX_DESC_SPE_RPT(txdesc, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 19, 1, value)\n#define GET_TX_DESC_SPE_RPT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 19, 1)\n#define SET_TX_DESC_RAW(txdesc, value)                                         \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 18, 1, value)\n#define GET_TX_DESC_RAW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 18, 1)\n#define SET_TX_DESC_MOREFRAG(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 17, 1, value)\n#define GET_TX_DESC_MOREFRAG(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 17, 1)\n#define SET_TX_DESC_BK(txdesc, value)                                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 1, value)\n#define GET_TX_DESC_BK(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 16, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 8, value)\n#define GET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x08, 16, 8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_NULL_1(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 15, 1, value)\n#define GET_TX_DESC_NULL_1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 15, 1)\n#define SET_TX_DESC_NULL_0(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 14, 1, value)\n#define GET_TX_DESC_NULL_0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 14, 1)\n#define SET_TX_DESC_RDG_EN(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 13, 1, value)\n#define GET_TX_DESC_RDG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 13, 1)\n#define SET_TX_DESC_AGG_EN(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 12, 1, value)\n#define GET_TX_DESC_AGG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 12, 1)\n#define SET_TX_DESC_CCA_RTS(txdesc, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 10, 2, value)\n#define GET_TX_DESC_CCA_RTS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 10, 2)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_TRI_FRAME(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 9, 1, value)\n#define GET_TX_DESC_TRI_FRAME(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 9, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_P_AID(txdesc, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 9, value)\n#define GET_TX_DESC_P_AID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 0, 9)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 16, value)\n#define GET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc)                                 \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x08, 0, 16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n/*TXDESC_WORD3*/\n\n#define SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 24, 8, value)\n#define GET_TX_DESC_AMPDU_MAX_TIME(txdesc)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x0C, 24, 8)\n#define SET_TX_DESC_NDPA(txdesc, value)                                        \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 22, 2, value)\n#define GET_TX_DESC_NDPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 22, 2)\n#define SET_TX_DESC_MAX_AGG_NUM(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 17, 5, value)\n#define GET_TX_DESC_MAX_AGG_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 17, 5)\n#define SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 1, value)\n#define GET_TX_DESC_USE_MAX_TIME_EN(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_OFFLOAD_SIZE(txdesc, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 15, value)\n#define GET_TX_DESC_OFFLOAD_SIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 15)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_NAVUSEHDR(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 15, 1, value)\n#define GET_TX_DESC_NAVUSEHDR(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 15, 1)\n#define SET_TX_DESC_CHK_EN(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 14, 1, value)\n#define GET_TX_DESC_CHK_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 14, 1)\n#define SET_TX_DESC_HW_RTS_EN(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 13, 1, value)\n#define GET_TX_DESC_HW_RTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 13, 1)\n#define SET_TX_DESC_RTSEN(txdesc, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 12, 1, value)\n#define GET_TX_DESC_RTSEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 12, 1)\n#define SET_TX_DESC_CTS2SELF(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 1, value)\n#define GET_TX_DESC_CTS2SELF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 1)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_CHANNEL_DMA(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 5, value)\n#define GET_TX_DESC_CHANNEL_DMA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 5)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_DISDATAFB(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 10, 1, value)\n#define GET_TX_DESC_DISDATAFB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 10, 1)\n#define SET_TX_DESC_DISRTSFB(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 9, 1, value)\n#define GET_TX_DESC_DISRTSFB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 9, 1)\n#define SET_TX_DESC_USE_RATE(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 8, 1, value)\n#define GET_TX_DESC_USE_RATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 8, 1)\n#define SET_TX_DESC_HW_SSN_SEL(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 2, value)\n#define GET_TX_DESC_HW_SSN_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 2)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_IE_CNT(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 3, value)\n#define GET_TX_DESC_IE_CNT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 3)\n#define SET_TX_DESC_IE_CNT_EN(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 5, 1, value)\n#define GET_TX_DESC_IE_CNT_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 5, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_WHEADER_LEN(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value)\n#define GET_TX_DESC_WHEADER_LEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5)\n\n#endif\n\n#if (HALMAC_8814B_SUPPORT)\n\n#define SET_TX_DESC_WHEADER_LEN_V1(txdesc, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value)\n#define GET_TX_DESC_WHEADER_LEN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n/*TXDESC_WORD4*/\n\n#define SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x10, 30, 2, value)\n#define GET_TX_DESC_PCTS_MASK_IDX(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 30, 2)\n#define SET_TX_DESC_PCTS_EN(txdesc, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x10, 29, 1, value)\n#define GET_TX_DESC_PCTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 29, 1)\n#define SET_TX_DESC_RTSRATE(txdesc, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x10, 24, 5, value)\n#define GET_TX_DESC_RTSRATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 24, 5)\n#define SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x10, 18, 6, value)\n#define GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x10, 18, 6)\n#define SET_TX_DESC_RTY_LMT_EN(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x10, 17, 1, value)\n#define GET_TX_DESC_RTY_LMT_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 17, 1)\n#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x10, 13, 4, value)\n#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)                                \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x10, 13, 4)\n#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)                        \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x10, 8, 5, value)\n#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)                               \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x10, 8, 5)\n#define SET_TX_DESC_TRY_RATE(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x10, 7, 1, value)\n#define GET_TX_DESC_TRY_RATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 7, 1)\n#define SET_TX_DESC_DATARATE(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x10, 0, 7, value)\n#define GET_TX_DESC_DATARATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 0, 7)\n\n/*TXDESC_WORD5*/\n\n#define SET_TX_DESC_POLLUTED(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 31, 1, value)\n#define GET_TX_DESC_POLLUTED(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 31, 1)\n\n#endif\n\n#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_EN_V1(txdesc, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 30, 1, value)\n#define GET_TX_DESC_ANTSEL_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 30, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_TXPWR_OFSET(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 3, value)\n#define GET_TX_DESC_TXPWR_OFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 3)\n\n#endif\n\n#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value)                            \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 2, value)\n#define GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc)                                   \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x14, 28, 2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 3, value)\n#define GET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc)                                \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x14, 28, 3)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_TX_ANT(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 4, value)\n#define GET_TX_DESC_TX_ANT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 24, 4)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_DROP_ID(txdesc, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 2, value)\n#define GET_TX_DESC_DROP_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 24, 2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_DROP_ID_V1(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 22, 2, value)\n#define GET_TX_DESC_DROP_ID_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 22, 2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_PORT_ID(txdesc, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 21, 3, value)\n#define GET_TX_DESC_PORT_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 21, 3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_PORT_ID_V1(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 21, 1, value)\n#define GET_TX_DESC_PORT_ID_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 21, 1)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \\\n     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_MULTIPLE_PORT(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 18, 3, value)\n#define GET_TX_DESC_MULTIPLE_PORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 18, 3)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 17, 1, value)\n#define GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)                                 \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x14, 17, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_RTS_SC(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 13, 4, value)\n#define GET_TX_DESC_RTS_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 13, 4)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 13, 4, value)\n#define GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)                                \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x14, 13, 4)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_RTS_SHORT(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 12, 1, value)\n#define GET_TX_DESC_RTS_SHORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 12, 1)\n#define SET_TX_DESC_VCS_STBC(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 10, 2, value)\n#define GET_TX_DESC_VCS_STBC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 10, 2)\n#define SET_TX_DESC_DATA_STBC(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 8, 2, value)\n#define GET_TX_DESC_DATA_STBC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 8, 2)\n#define SET_TX_DESC_DATA_LDPC(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 7, 1, value)\n#define GET_TX_DESC_DATA_LDPC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 7, 1)\n#define SET_TX_DESC_DATA_BW(txdesc, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 5, 2, value)\n#define GET_TX_DESC_DATA_BW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 5, 2)\n#define SET_TX_DESC_DATA_SHORT(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 4, 1, value)\n#define GET_TX_DESC_DATA_SHORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 4, 1)\n#define SET_TX_DESC_DATA_SC(txdesc, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x14, 0, 4, value)\n#define GET_TX_DESC_DATA_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 0, 4)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n/*TXDESC_WORD6*/\n\n#define SET_TX_DESC_ANTSEL_D(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 30, 2, value)\n#define GET_TX_DESC_ANTSEL_D(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 30, 2)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPD_V1(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 30, 2, value)\n#define GET_TX_DESC_ANT_MAPD_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 30, 2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPC_V2(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 30, 2, value)\n#define GET_TX_DESC_ANT_MAPC_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 30, 2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPD(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 2, value)\n#define GET_TX_DESC_ANT_MAPD(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 2)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPC_V1(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 2, value)\n#define GET_TX_DESC_ANT_MAPC_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPB_V2(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 2, value)\n#define GET_TX_DESC_ANT_MAPB_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPC(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 2, value)\n#define GET_TX_DESC_ANT_MAPC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 2)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPB_V1(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 2, value)\n#define GET_TX_DESC_ANT_MAPB_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPA_V2(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 2, value)\n#define GET_TX_DESC_ANT_MAPA_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPB(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 2, value)\n#define GET_TX_DESC_ANT_MAPB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 2)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPA_V1(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 2, value)\n#define GET_TX_DESC_ANT_MAPA_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_D_V1(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 2, value)\n#define GET_TX_DESC_ANTSEL_D_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPA(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 22, 2, value)\n#define GET_TX_DESC_ANT_MAPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 22, 2)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_C_V2(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 22, 2, value)\n#define GET_TX_DESC_ANTSEL_C_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 22, 2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_C(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 20, 2, value)\n#define GET_TX_DESC_ANTSEL_C(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 20, 2)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_B_V1(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 20, 4, value)\n#define GET_TX_DESC_ANTSEL_B_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 20, 4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_B_V2(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 19, 3, value)\n#define GET_TX_DESC_ANTSEL_B_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 19, 3)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_B(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 18, 2, value)\n#define GET_TX_DESC_ANTSEL_B(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 18, 2)\n#define SET_TX_DESC_ANTSEL_A(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 2, value)\n#define GET_TX_DESC_ANTSEL_A(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 2)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_A_V1(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 4, value)\n#define GET_TX_DESC_ANTSEL_A_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_A_V2(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 3, value)\n#define GET_TX_DESC_ANTSEL_A_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 3)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_MBSSID(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 12, 4, value)\n#define GET_TX_DESC_MBSSID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 12, 4)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_SW_DEFINE(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 12, value)\n#define GET_TX_DESC_SW_DEFINE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 12)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_SWPS_SEQ(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 12, value)\n#define GET_TX_DESC_SWPS_SEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 12)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n/*TXDESC_WORD7*/\n\n#define SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 24, 8, value)\n#define GET_TX_DESC_DMA_TXAGG_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 24, 8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 24, 8, value)\n#define GET_TX_DESC_FINAL_DATA_RATE(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x1C, 24, 8)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_ANT_MAPD_V2(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 22, 2, value)\n#define GET_TX_DESC_ANT_MAPD_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 22, 2)\n#define SET_TX_DESC_ANTSEL_EN_V2(txdesc, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 21, 1, value)\n#define GET_TX_DESC_ANTSEL_EN_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 21, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_NTX_MAP(txdesc, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 20, 4, value)\n#define GET_TX_DESC_NTX_MAP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 20, 4)\n\n#endif\n\n#if (HALMAC_8198F_SUPPORT)\n\n#define SET_TX_DESC_ANTSEL_EN(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 19, 1, value)\n#define GET_TX_DESC_ANTSEL_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 19, 1)\n#define SET_TX_DESC_MBSSID_EX(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 16, 3, value)\n#define GET_TX_DESC_MBSSID_EX(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 16, 3)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_MBSSID_EX_V1(txdesc, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 16, 1, value)\n#define GET_TX_DESC_MBSSID_EX_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 16, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value)\n#define GET_TX_DESC_TX_BUFF_SIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16)\n#define SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)                             \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value)\n#define GET_TX_DESC_TXDESC_CHECKSUM(txdesc)                                    \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16)\n#define SET_TX_DESC_TIMESTAMP(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value)\n#define GET_TX_DESC_TIMESTAMP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n/*TXDESC_WORD8*/\n\n#define SET_TX_DESC_TXWIFI_CP(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 31, 1, value)\n#define GET_TX_DESC_TXWIFI_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 31, 1)\n#define SET_TX_DESC_MAC_CP(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 30, 1, value)\n#define GET_TX_DESC_MAC_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 30, 1)\n#define SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 29, 1, value)\n#define GET_TX_DESC_STW_PKTRE_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 29, 1)\n#define SET_TX_DESC_STW_RB_DIS(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 28, 1, value)\n#define GET_TX_DESC_STW_RB_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 28, 1)\n#define SET_TX_DESC_STW_RATE_DIS(txdesc, value)                                \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 27, 1, value)\n#define GET_TX_DESC_STW_RATE_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 27, 1)\n#define SET_TX_DESC_STW_ANT_DIS(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 26, 1, value)\n#define GET_TX_DESC_STW_ANT_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 26, 1)\n#define SET_TX_DESC_STW_EN(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 25, 1, value)\n#define GET_TX_DESC_STW_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 25, 1)\n#define SET_TX_DESC_SMH_EN(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 1, value)\n#define GET_TX_DESC_SMH_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_TAILPAGE_L(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 8, value)\n#define GET_TX_DESC_TAILPAGE_L(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 8)\n#define SET_TX_DESC_SDIO_DMASEQ(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 8, value)\n#define GET_TX_DESC_SDIO_DMASEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 8)\n#define SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 8, value)\n#define GET_TX_DESC_NEXTHEADPAGE_L(txdesc)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x20, 16, 8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_EN_HWSEQ(txdesc, value)                                    \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 15, 1, value)\n#define GET_TX_DESC_EN_HWSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 15, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)\n\n#define SET_TX_DESC_EN_HWEXSEQ(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 14, 1, value)\n#define GET_TX_DESC_EN_HWEXSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 14, 1)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_EN_HWSEQ_MODE(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 14, 2, value)\n#define GET_TX_DESC_EN_HWSEQ_MODE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 14, 2)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_DATA_RC(txdesc, value)                                     \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 8, 6, value)\n#define GET_TX_DESC_DATA_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 8, 6)\n#define SET_TX_DESC_BAR_RTY_TH(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 6, 2, value)\n#define GET_TX_DESC_BAR_RTY_TH(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 6, 2)\n#define SET_TX_DESC_RTS_RC(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x20, 0, 6, value)\n#define GET_TX_DESC_RTS_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 0, 6)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n/*TXDESC_WORD9*/\n\n#define SET_TX_DESC_TAILPAGE_H(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 28, 4, value)\n#define GET_TX_DESC_TAILPAGE_H(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 28, 4)\n#define SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)                              \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 24, 4, value)\n#define GET_TX_DESC_NEXTHEADPAGE_H(txdesc)                                     \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x24, 24, 4)\n\n#endif\n\n#if (HALMAC_8192F_SUPPORT)\n\n#define SET_TX_DESC_FINAL_DATA_RATE_V1(txdesc, value)                          \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 24, 8, value)\n#define GET_TX_DESC_FINAL_DATA_RATE_V1(txdesc)                                 \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x24, 24, 8)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_SW_SEQ(txdesc, value)                                      \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 12, 12, value)\n#define GET_TX_DESC_SW_SEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 12, 12)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_TXBF_PATH(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 11, 1, value)\n#define GET_TX_DESC_TXBF_PATH(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 11, 1)\n\n#endif\n\n#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \\\n     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_PADDING_LEN(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 11, value)\n#define GET_TX_DESC_PADDING_LEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 11)\n#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)                         \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 8, value)\n#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)                                \\\n\tLE_BITS_TO_4BYTE(txdesc + 0x24, 0, 8)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n/*WORD10*/\n\n#define SET_TX_DESC_HT_DATA_SND(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 31, 1, value)\n#define GET_TX_DESC_HT_DATA_SND(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 31, 1)\n#define SET_TX_DESC_SHCUT_CAM(txdesc, value)                                   \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 16, 6, value)\n#define GET_TX_DESC_SHCUT_CAM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 16, 6)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_MU_DATARATE(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 8, 8, value)\n#define GET_TX_DESC_MU_DATARATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 8, 8)\n#define SET_TX_DESC_MU_RC(txdesc, value)                                       \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 4, 4, value)\n#define GET_TX_DESC_MU_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 4, 4)\n\n#endif\n\n#if (HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_NDPA_RATE_SEL(txdesc, value)                               \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 3, 1, value)\n#define GET_TX_DESC_NDPA_RATE_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 3, 1)\n#define SET_TX_DESC_HW_NDPA_EN(txdesc, value)                                  \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 2, 1, value)\n#define GET_TX_DESC_HW_NDPA_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 2, 1)\n\n#endif\n\n#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT ||   \\\n     HALMAC_8812F_SUPPORT)\n\n#define SET_TX_DESC_SND_PKT_SEL(txdesc, value)                                 \\\n\tSET_BITS_TO_LE_4BYTE(txdesc + 0x28, 0, 2, value)\n#define GET_TX_DESC_SND_PKT_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 0, 2)\n\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_type.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef _HALMAC_TYPE_H_\n#define _HALMAC_TYPE_H_\n\n#include \"halmac_2_platform.h\"\n#include \"halmac_hw_cfg.h\"\n#include \"halmac_fw_info.h\"\n#include \"halmac_intf_phy_cmd.h\"\n#include \"halmac_state_machine.h\"\n\n#define IN\n#define OUT\n#define INOUT\n\n#define HALMAC_BCN_IE_BMP_SIZE\t24 /* ID0~ID191, 192/8=24 */\n\n#ifndef HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE\n#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE\t80\n#endif\n\n#ifndef HALMAC_MSG_LEVEL_TRACE\n#define HALMAC_MSG_LEVEL_TRACE\t\t3\n#endif\n\n#ifndef HALMAC_MSG_LEVEL_WARNING\n#define HALMAC_MSG_LEVEL_WARNING\t2\n#endif\n\n#ifndef HALMAC_MSG_LEVEL_ERR\n#define HALMAC_MSG_LEVEL_ERR\t\t1\n#endif\n\n#ifndef HALMAC_MSG_LEVEL_NO_LOG\n#define HALMAC_MSG_LEVEL_NO_LOG\t\t0\n#endif\n\n#ifndef HALMAC_SDIO_SUPPORT\n#define HALMAC_SDIO_SUPPORT\t\t1\n#endif\n\n#ifndef HALMAC_USB_SUPPORT\n#define HALMAC_USB_SUPPORT\t\t1\n#endif\n\n#ifndef HALMAC_PCIE_SUPPORT\n#define HALMAC_PCIE_SUPPORT\t\t1\n#endif\n\n#ifndef HALMAC_MSG_LEVEL\n#define HALMAC_MSG_LEVEL HALMAC_MSG_LEVEL_TRACE\n#endif\n\n/* platform api */\n#define PLTFM_SDIO_CMD52_R(offset)                                             \\\n\tadapter->pltfm_api->SDIO_CMD52_READ(adapter->drv_adapter, offset)\n#define PLTFM_SDIO_CMD53_R8(offset)                                            \\\n\tadapter->pltfm_api->SDIO_CMD53_READ_8(adapter->drv_adapter, offset)\n#define PLTFM_SDIO_CMD53_R16(offset)                                           \\\n\tadapter->pltfm_api->SDIO_CMD53_READ_16(adapter->drv_adapter, offset)\n#define PLTFM_SDIO_CMD53_R32(offset)                                           \\\n\tadapter->pltfm_api->SDIO_CMD53_READ_32(adapter->drv_adapter, offset)\n#define PLTFM_SDIO_CMD53_RN(offset, size, data)                                \\\n\tadapter->pltfm_api->SDIO_CMD53_READ_N(adapter->drv_adapter, offset,    \\\n\t\t\t\t\t      size, data)\n#define PLTFM_SDIO_CMD52_W(offset, val)                                        \\\n\tadapter->pltfm_api->SDIO_CMD52_WRITE(adapter->drv_adapter, offset, val)\n#define PLTFM_SDIO_CMD53_W8(offset, val)                                       \\\n\tadapter->pltfm_api->SDIO_CMD53_WRITE_8(adapter->drv_adapter, offset,   \\\n\t\t\t\t\t       val)\n#define PLTFM_SDIO_CMD53_W16(offset, val)                                      \\\n\tadapter->pltfm_api->SDIO_CMD53_WRITE_16(adapter->drv_adapter, offset,  \\\n\t\t\t\t\t\tval)\n#define PLTFM_SDIO_CMD53_W32(offset, val)                                      \\\n\tadapter->pltfm_api->SDIO_CMD53_WRITE_32(adapter->drv_adapter, offset,  \\\n\t\t\t\t\t\tval)\n#define PLTFM_SDIO_CMD52_CIA_R(offset)                                         \\\n\tadapter->pltfm_api->SDIO_CMD52_CIA_READ(adapter->drv_adapter, offset)\n\n#define PLTFM_REG_R8(offset)                                                   \\\n\tadapter->pltfm_api->REG_READ_8(adapter->drv_adapter, offset)\n#define PLTFM_REG_R16(offset)                                                  \\\n\tadapter->pltfm_api->REG_READ_16(adapter->drv_adapter, offset)\n#define PLTFM_REG_R32(offset)                                                  \\\n\tadapter->pltfm_api->REG_READ_32(adapter->drv_adapter, offset)\n#define PLTFM_REG_W8(offset, val)                                              \\\n\tadapter->pltfm_api->REG_WRITE_8(adapter->drv_adapter, offset, val)\n#define PLTFM_REG_W16(offset, val)                                             \\\n\tadapter->pltfm_api->REG_WRITE_16(adapter->drv_adapter, offset, val)\n#define PLTFM_REG_W32(offset, val)                                             \\\n\tadapter->pltfm_api->REG_WRITE_32(adapter->drv_adapter, offset, val)\n\n#define PLTFM_SEND_RSVD_PAGE(buf, size)                                        \\\n\tadapter->pltfm_api->SEND_RSVD_PAGE(adapter->drv_adapter, buf, size)\n#define PLTFM_SEND_H2C_PKT(buf, size)                                          \\\n\tadapter->pltfm_api->SEND_H2C_PKT(adapter->drv_adapter, buf, size)\n\n#define PLTFM_FREE(buf, size)                                                  \\\n\tadapter->pltfm_api->RTL_FREE(adapter->drv_adapter, buf, size)\n#define PLTFM_MALLOC(size)                                                     \\\n\tadapter->pltfm_api->RTL_MALLOC(adapter->drv_adapter, size)\n#define PLTFM_MEMCPY(dest, src, size)                                          \\\n\tadapter->pltfm_api->RTL_MEMCPY(adapter->drv_adapter, dest, src, size)\n#define PLTFM_MEMSET(addr, value, size)                                        \\\n\tadapter->pltfm_api->RTL_MEMSET(adapter->drv_adapter, addr, value, size)\n#define PLTFM_DELAY_US(us)                                                     \\\n\tadapter->pltfm_api->RTL_DELAY_US(adapter->drv_adapter, us)\n\n#define PLTFM_MUTEX_INIT(mutex)                                                \\\n\tadapter->pltfm_api->MUTEX_INIT(adapter->drv_adapter, mutex)\n#define PLTFM_MUTEX_DEINIT(mutex)                                              \\\n\tadapter->pltfm_api->MUTEX_DEINIT(adapter->drv_adapter, mutex)\n#define PLTFM_MUTEX_LOCK(mutex)                                                \\\n\tadapter->pltfm_api->MUTEX_LOCK(adapter->drv_adapter, mutex)\n#define PLTFM_MUTEX_UNLOCK(mutex)                                              \\\n\tadapter->pltfm_api->MUTEX_UNLOCK(adapter->drv_adapter, mutex)\n\n#define PLTFM_EVENT_SIG(feature_id, proc_status, buf, size)                    \\\n\tadapter->pltfm_api->EVENT_INDICATION(adapter->drv_adapter, feature_id, \\\n\t\t\t\t\t     proc_status, buf, size)\n\n#if HALMAC_PLATFORM_WINDOWS\n#define PLTFM_MSG_PRINT\tadapter->pltfm_api->MSG_PRINT\n#endif\n\n#define PLTFM_MSG_ALWAYS(...)                                                  \\\n\tadapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT,   \\\n\t\t\t\t      HALMAC_DBG_ALWAYS, __VA_ARGS__)\n\n#if HALMAC_DBG_MSG_ENABLE\n\n/* Enable debug msg depends on  HALMAC_MSG_LEVEL */\n#if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_ERR)\n#define PLTFM_MSG_ERR(...)                                                     \\\n\tadapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT,   \\\n\t\t\t\t      HALMAC_DBG_ERR, __VA_ARGS__)\n#else\n#define PLTFM_MSG_ERR(...)\tdo {} while (0)\n#endif\n\n#if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_WARNING)\n#define PLTFM_MSG_WARN(...)                                                    \\\n\tadapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT,   \\\n\t\t\t\t      HALMAC_DBG_WARN, __VA_ARGS__)\n#else\n#define PLTFM_MSG_WARN(...)\tdo {} while (0)\n#endif\n\n#if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_TRACE)\n#define PLTFM_MSG_TRACE(...)                                                   \\\n\tadapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT,   \\\n\t\t\t\t      HALMAC_DBG_TRACE, __VA_ARGS__)\n#else\n#define PLTFM_MSG_TRACE(...)\tdo {} while (0)\n#endif\n\n#else\n\n/* Disable debug msg  */\n#define PLTFM_MSG_ERR(...)\tdo {} while (0)\n#define PLTFM_MSG_WARN(...)\tdo {} while (0)\n#define PLTFM_MSG_TRACE(...)\tdo {} while (0)\n\n#endif\n\n#define HALMAC_REG_R8(offset) api->halmac_reg_read_8(adapter, offset)\n#define HALMAC_REG_R16(offset) api->halmac_reg_read_16(adapter, offset)\n#define HALMAC_REG_R32(offset) api->halmac_reg_read_32(adapter, offset)\n#define HALMAC_REG_W8(offset, val) api->halmac_reg_write_8(adapter, offset, val)\n#define HALMAC_REG_W16(offset, val)                                            \\\n\tapi->halmac_reg_write_16(adapter, offset, val)\n#define HALMAC_REG_W32(offset, val)                                            \\\n\tapi->halmac_reg_write_32(adapter, offset, val)\n#define HALMAC_REG_SDIO_RN(offset, size, data)                                 \\\n\tapi->halmac_reg_sdio_cmd53_read_n(adapter, offset, size, data)\n\n#define HALMAC_REG_W8_CLR(offset, mask)                                        \\\n\tdo {                                                                   \\\n\t\tu32 __offset = (u32)offset;                                    \\\n\t\tHALMAC_REG_W8(__offset, HALMAC_REG_R8(__offset) & ~(mask));    \\\n\t} while (0)\n#define HALMAC_REG_W16_CLR(offset, mask)                                       \\\n\tdo {                                                                   \\\n\t\tu32 __offset = (u32)offset;                                    \\\n\t\tHALMAC_REG_W16(__offset, HALMAC_REG_R16(__offset) & ~(mask));  \\\n\t} while (0)\n#define HALMAC_REG_W32_CLR(offset, mask)                                       \\\n\tdo {                                                                   \\\n\t\tu32 __offset = (u32)offset;                                    \\\n\t\tHALMAC_REG_W32(__offset, HALMAC_REG_R32(__offset) & ~(mask));  \\\n\t} while (0)\n\n#define HALMAC_REG_W8_SET(offset, mask)                                        \\\n\tdo {                                                                   \\\n\t\tu32 __offset = (u32)offset;                                    \\\n\t\tHALMAC_REG_W8(__offset, HALMAC_REG_R8(__offset) | mask);       \\\n\t} while (0)\n#define HALMAC_REG_W16_SET(offset, mask)                                       \\\n\tdo {                                                                   \\\n\t\tu32 __offset = (u32)offset;                                    \\\n\t\tHALMAC_REG_W16(__offset, HALMAC_REG_R16(__offset) | mask);     \\\n\t} while (0)\n#define HALMAC_REG_W32_SET(offset, mask)                                       \\\n\tdo {                                                                   \\\n\t\tu32 __offset = (u32)offset;                                    \\\n\t\tHALMAC_REG_W32(__offset, HALMAC_REG_R32(__offset) | mask);     \\\n\t} while (0)\n\n/* Swap Little-endian <-> Big-endia*/\n#define SWAP32(x)                                                              \\\n\t((u32)((((u32)(x) & (u32)0x000000ff) << 24) |                          \\\n\t       (((u32)(x) & (u32)0x0000ff00) << 8) |                           \\\n\t       (((u32)(x) & (u32)0x00ff0000) >> 8) |                           \\\n\t       (((u32)(x) & (u32)0xff000000) >> 24)))\n\n#define SWAP16(x)                                                              \\\n\t((u16)((((u16)(x) & (u16)0x00ff) << 8) |                               \\\n\t       (((u16)(x) & (u16)0xff00) >> 8)))\n\n/*1->Little endian 0->Big endian*/\n#if HALMAC_SYSTEM_ENDIAN\n#ifndef rtk_le16_to_cpu\n#define rtk_cpu_to_le32(x)              ((u32)(x))\n#define rtk_le32_to_cpu(x)              ((u32)(x))\n#define rtk_cpu_to_le16(x)              ((u16)(x))\n#define rtk_le16_to_cpu(x)              ((u16)(x))\n#define rtk_cpu_to_be32(x)              SWAP32((x))\n#define rtk_be32_to_cpu(x)              SWAP32((x))\n#define rtk_cpu_to_be16(x)              SWAP16((x))\n#define rtk_be16_to_cpu(x)              SWAP16((x))\n#endif\n#else\n#ifndef rtk_le16_to_cpu\n#define rtk_cpu_to_le32(x)              SWAP32((x))\n#define rtk_le32_to_cpu(x)              SWAP32((x))\n#define rtk_cpu_to_le16(x)              SWAP16((x))\n#define rtk_le16_to_cpu(x)              SWAP16((x))\n#define rtk_cpu_to_be32(x)              ((u32)(x))\n#define rtk_be32_to_cpu(x)              ((u32)(x))\n#define rtk_cpu_to_be16(x)              ((u16)(x))\n#define rtk_be16_to_cpu(x)              ((u16)(x))\n#endif\n#endif\n\n#define HALMAC_ALIGN(x, a)               HALMAC_ALIGN_MASK(x, (a) - 1)\n#define HALMAC_ALIGN_MASK(x, mask)       (((x) + (mask)) & ~(mask))\n\n/* #if !HALMAC_PLATFORM_WINDOWS */\n#if !((HALMAC_PLATFORM_WINDOWS == 1) && (HALMAC_PLATFORM_TESTPROGRAM == 0))\n\n/* Byte Swapping routine */\n#ifndef EF1BYTE\n#define EF1BYTE (u8)\n#endif\n\n#ifndef EF2BYTE\n#define EF2BYTE rtk_le16_to_cpu\n#endif\n\n#ifndef EF4BYTE\n#define EF4BYTE rtk_le32_to_cpu\n#endif\n\n/* Example:\n * BIT_LEN_MASK_32(0) => 0x00000000\n * BIT_LEN_MASK_32(1) => 0x00000001\n * BIT_LEN_MASK_32(2) => 0x00000003\n * BIT_LEN_MASK_32(32) => 0xFFFFFFFF\n */\n#ifndef BIT_LEN_MASK_32\n#define BIT_LEN_MASK_32(__bitlen) (0xFFFFFFFF >> (32 - (__bitlen)))\n#endif\n\n/* Example:\n * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003\n * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000\n */\n#ifndef BIT_OFFSET_LEN_MASK_32\n#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)                          \\\n\t(BIT_LEN_MASK_32(__bitlen) << (__bitoffset))\n#endif\n\n/* Return 4-byte value in host byte ordering from\n * 4-byte pointer in litten-endian system\n */\n#ifndef LE_P4BYTE_TO_HOST_4BYTE\n#define LE_P4BYTE_TO_HOST_4BYTE(__start) (EF4BYTE(*((u32 *)(__start))))\n#endif\n\n/* Translate subfield (continuous bits in little-endian) of\n * 4-byte value in litten byte to 4-byte value in host byte ordering\n */\n#ifndef LE_BITS_TO_4BYTE\n#define LE_BITS_TO_4BYTE(__start, __bitoffset, __bitlen)                       \\\n\t((LE_P4BYTE_TO_HOST_4BYTE(__start) >> (__bitoffset)) &                 \\\n\t BIT_LEN_MASK_32(__bitlen))\n#endif\n\n/* Mask subfield (continuous bits in little-endian) of 4-byte\n * value in litten byte oredering and return the result in 4-byte\n * value in host byte ordering\n */\n#ifndef LE_BITS_CLEARED_TO_4BYTE\n#define LE_BITS_CLEARED_TO_4BYTE(__start, __bitoffset, __bitlen)               \\\n\t(LE_P4BYTE_TO_HOST_4BYTE(__start) &                                    \\\n\t (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)))\n#endif\n\n/* Set subfield of little-endian 4-byte value to specified value */\n#ifndef SET_BITS_TO_LE_4BYTE\n#define SET_BITS_TO_LE_4BYTE(__start, __bitoffset, __bitlen, __value)          \\\n\tdo {                                                                   \\\n\t\t*((u32 *)(__start)) = \\\n\t\tEF4BYTE( \\\n\t\tLE_BITS_CLEARED_TO_4BYTE(__start, __bitoffset, __bitlen) |     \\\n\t\t((((u32)__value) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset))\\\n\t\t);                                                             \\\n\t} while (0)\n#endif\n\n#ifndef HALMAC_BIT_OFFSET_VAL_MASK_32\n#define HALMAC_BIT_OFFSET_VAL_MASK_32(__bitval, __bitoffset)                   \\\n\t(__bitval << (__bitoffset))\n#endif\n\n#ifndef SET_MEM_OP\n#define SET_MEM_OP(dw, value32, mask, shift)                                   \\\n\t(((dw) & ~((mask) << (shift))) | (((value32) & (mask)) << (shift)))\n#endif\n\n#ifndef HALMAC_SET_DESC_FIELD_CLR\n#define HALMAC_SET_DESC_FIELD_CLR(dw, value32, mask, shift)                    \\\n\t(dw = (rtk_cpu_to_le32(                                                \\\n\t\t SET_MEM_OP(rtk_cpu_to_le32(dw), value32, mask, shift))))\n#endif\n\n#ifndef HALMAC_SET_DESC_FIELD_NO_CLR\n#define HALMAC_SET_DESC_FIELD_NO_CLR(dw, value32, mask, shift)                 \\\n\t(dw |= (rtk_cpu_to_le32(((value32) & (mask)) << (shift))))\n#endif\n\n#ifndef HALMAC_GET_DESC_FIELD\n#define HALMAC_GET_DESC_FIELD(dw, mask, shift)                                 \\\n\t((rtk_le32_to_cpu(dw) >> (shift)) & (mask))\n#endif\n\n#define HALMAC_SET_BD_FIELD_CLR HALMAC_SET_DESC_FIELD_CLR\n#define HALMAC_SET_BD_FIELD_NO_CLR HALMAC_SET_DESC_FIELD_NO_CLR\n#define HALMAC_GET_BD_FIELD HALMAC_GET_DESC_FIELD\n\n#ifndef GET_H2C_FIELD\n#define GET_H2C_FIELD   LE_BITS_TO_4BYTE\n#endif\n\n#ifndef SET_H2C_FIELD_CLR\n#define SET_H2C_FIELD_CLR       SET_BITS_TO_LE_4BYTE\n#endif\n\n#ifndef SET_H2C_FIELD_NO_CLR\n#define SET_H2C_FIELD_NO_CLR    SET_BITS_TO_LE_4BYTE\n#endif\n\n#ifndef GET_C2H_FIELD\n#define GET_C2H_FIELD   LE_BITS_TO_4BYTE\n#endif\n\n#ifndef SET_C2H_FIELD_CLR\n#define SET_C2H_FIELD_CLR       SET_BITS_TO_LE_4BYTE\n#endif\n\n#ifndef SET_C2H_FIELD_NO_CLR\n#define SET_C2H_FIELD_NO_CLR    SET_BITS_TO_LE_4BYTE\n#endif\n\n#endif /* #if !HALMAC_PLATFORM_WINDOWS */\n\n#ifndef BIT\n#define BIT(x)              (1 << (x))\n#endif\n\n#ifndef ARRAY_SIZE\n#define ARRAY_SIZE(arr)\t\t(sizeof(arr) / sizeof((arr)[0]))\n#endif\n\n/* HALMAC API return status*/\nenum halmac_ret_status {\n\tHALMAC_RET_SUCCESS = 0x00,\n\tHALMAC_RET_NOT_SUPPORT = 0x01,\n\tHALMAC_RET_SUCCESS_ENQUEUE = 0x01, /*Don't use this return code!!*/\n\tHALMAC_RET_PLATFORM_API_NULL = 0x02,\n\tHALMAC_RET_EFUSE_SIZE_INCORRECT = 0x03,\n\tHALMAC_RET_MALLOC_FAIL = 0x04,\n\tHALMAC_RET_ADAPTER_INVALID = 0x05,\n\tHALMAC_RET_ITF_INCORRECT = 0x06,\n\tHALMAC_RET_DLFW_FAIL = 0x07,\n\tHALMAC_RET_PORT_NOT_SUPPORT = 0x08,\n\tHALMAC_RET_TXAGG_OVERFLOW = 0x09,\n\tHALMAC_RET_INIT_LLT_FAIL = 0x0A,\n\tHALMAC_RET_POWER_STATE_INVALID = 0x0B,\n\tHALMAC_RET_H2C_ACK_NOT_RECEIVED = 0x0C,\n\tHALMAC_RET_DL_RSVD_PAGE_FAIL = 0x0D,\n\tHALMAC_RET_EFUSE_R_FAIL = 0x0E,\n\tHALMAC_RET_EFUSE_W_FAIL = 0x0F,\n\tHALMAC_RET_H2C_SW_RES_FAIL = 0x10,\n\tHALMAC_RET_SEND_H2C_FAIL = 0x11,\n\tHALMAC_RET_PARA_NOT_SUPPORT = 0x12,\n\tHALMAC_RET_PLATFORM_API_INCORRECT = 0x13,\n\tHALMAC_RET_ENDIAN_ERR = 0x14,\n\tHALMAC_RET_FW_SIZE_ERR = 0x15,\n\tHALMAC_RET_TRX_MODE_NOT_SUPPORT = 0x16,\n\tHALMAC_RET_FAIL = 0x17,\n\tHALMAC_RET_CHANGE_PS_FAIL = 0x18,\n\tHALMAC_RET_CFG_PARA_FAIL = 0x19,\n\tHALMAC_RET_UPDATE_PROBE_FAIL = 0x1A,\n\tHALMAC_RET_SCAN_FAIL = 0x1B,\n\tHALMAC_RET_STOP_SCAN_FAIL = 0x1C,\n\tHALMAC_RET_BCN_PARSER_CMD_FAIL = 0x1D,\n\tHALMAC_RET_POWER_ON_FAIL = 0x1E,\n\tHALMAC_RET_POWER_OFF_FAIL = 0x1F,\n\tHALMAC_RET_RX_AGG_MODE_FAIL = 0x20,\n\tHALMAC_RET_DATA_BUF_NULL = 0x21,\n\tHALMAC_RET_DATA_SIZE_INCORRECT = 0x22,\n\tHALMAC_RET_QSEL_INCORRECT = 0x23,\n\tHALMAC_RET_DMA_MAP_INCORRECT = 0x24,\n\tHALMAC_RET_SEND_ORIGINAL_H2C_FAIL = 0x25,\n\tHALMAC_RET_DDMA_FAIL = 0x26,\n\tHALMAC_RET_FW_CHECKSUM_FAIL = 0x27,\n\tHALMAC_RET_PWRSEQ_POLLING_FAIL = 0x28,\n\tHALMAC_RET_PWRSEQ_CMD_INCORRECT = 0x29,\n\tHALMAC_RET_WRITE_DATA_FAIL = 0x2A,\n\tHALMAC_RET_DUMP_FIFOSIZE_INCORRECT = 0x2B,\n\tHALMAC_RET_NULL_POINTER = 0x2C,\n\tHALMAC_RET_PROBE_NOT_FOUND = 0x2D,\n\tHALMAC_RET_FW_NO_MEMORY = 0x2E,\n\tHALMAC_RET_H2C_STATUS_ERR = 0x2F,\n\tHALMAC_RET_GET_H2C_SPACE_ERR = 0x30,\n\tHALMAC_RET_H2C_SPACE_FULL = 0x31,\n\tHALMAC_RET_DATAPACK_NO_FOUND = 0x32,\n\tHALMAC_RET_CANNOT_FIND_H2C_RESOURCE = 0x33,\n\tHALMAC_RET_TX_DMA_ERR = 0x34,\n\tHALMAC_RET_RX_DMA_ERR = 0x35,\n\tHALMAC_RET_CHIP_NOT_SUPPORT = 0x36,\n\tHALMAC_RET_FREE_SPACE_NOT_ENOUGH = 0x37,\n\tHALMAC_RET_CH_SW_SEQ_WRONG = 0x38,\n\tHALMAC_RET_CH_SW_NO_BUF = 0x39,\n\tHALMAC_RET_SW_CASE_NOT_SUPPORT = 0x3A,\n\tHALMAC_RET_CONVERT_SDIO_OFFSET_FAIL = 0x3B,\n\tHALMAC_RET_INVALID_SOUNDING_SETTING = 0x3C,\n\tHALMAC_RET_GEN_INFO_NOT_SENT = 0x3D,\n\tHALMAC_RET_STATE_INCORRECT = 0x3E,\n\tHALMAC_RET_H2C_BUSY = 0x3F,\n\tHALMAC_RET_INVALID_FEATURE_ID = 0x40,\n\tHALMAC_RET_BUFFER_TOO_SMALL = 0x41,\n\tHALMAC_RET_ZERO_LEN_RSVD_PACKET = 0x42,\n\tHALMAC_RET_BUSY_STATE = 0x43,\n\tHALMAC_RET_ERROR_STATE = 0x44,\n\tHALMAC_RET_API_INVALID = 0x45,\n\tHALMAC_RET_POLLING_BCN_VALID_FAIL = 0x46,\n\tHALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL = 0x47,\n\tHALMAC_RET_EEPROM_PARSING_FAIL = 0x48,\n\tHALMAC_RET_EFUSE_NOT_ENOUGH = 0x49,\n\tHALMAC_RET_WRONG_ARGUMENT = 0x4A,\n\tHALMAC_RET_C2H_NOT_HANDLED = 0x4C,\n\tHALMAC_RET_PARA_SENDING = 0x4D,\n\tHALMAC_RET_CFG_DLFW_SIZE_FAIL = 0x4E,\n\tHALMAC_RET_CFG_TXFIFO_PAGE_FAIL = 0x4F,\n\tHALMAC_RET_SWITCH_CASE_ERROR = 0x50,\n\tHALMAC_RET_EFUSE_BANK_INCORRECT = 0x51,\n\tHALMAC_RET_SWITCH_EFUSE_BANK_FAIL = 0x52,\n\tHALMAC_RET_USB_MODE_UNCHANGE = 0x53,\n\tHALMAC_RET_NO_DLFW = 0x54,\n\tHALMAC_RET_USB2_3_SWITCH_UNSUPPORT = 0x55,\n\tHALMAC_RET_BIP_NO_SUPPORT = 0x56,\n\tHALMAC_RET_ENTRY_INDEX_ERROR = 0x57,\n\tHALMAC_RET_ENTRY_KEY_ID_ERROR = 0x58,\n\tHALMAC_RET_DRV_DL_ERR = 0x59,\n\tHALMAC_RET_OQT_NOT_ENOUGH = 0x5A,\n\tHALMAC_RET_PWR_UNCHANGE = 0x5B,\n\tHALMAC_RET_WRONG_INTF = 0x5C,\n\tHALMAC_RET_POLLING_HIOE_REQ_FAIL = 0x5E,\n\tHALMAC_RET_HIOE_CHKSUM_FAIL = 0x5F,\n\tHALMAC_RET_HIOE_ERR = 0x60,\n\tHALMAC_RET_FW_NO_SUPPORT = 0x60,\n\tHALMAC_RET_TXFIFO_NO_EMPTY = 0x61,\n\tHALMAC_RET_SDIO_CLOCK_ERR = 0x62,\n\tHALMAC_RET_GET_PINMUX_ERR = 0x63,\n\tHALMAC_RET_PINMUX_USED = 0x64,\n\tHALMAC_RET_WRONG_GPIO = 0x65,\n\tHALMAC_RET_LTECOEX_READY_FAIL = 0x66,\n\tHALMAC_RET_IDMEM_CHKSUM_FAIL = 0x67,\n\tHALMAC_RET_ILLEGAL_KEY_FAIL = 0x68,\n\tHALMAC_RET_FW_READY_CHK_FAIL = 0x69,\n\tHALMAC_RET_RSVD_PG_OVERFLOW_FAIL = 0x70,\n\tHALMAC_RET_THRESHOLD_FAIL = 0x71,\n\tHALMAC_RET_SDIO_MIX_MODE = 0x72,\n\tHALMAC_RET_TXDESC_SET_FAIL = 0x73,\n\tHALMAC_RET_WLHDR_FAIL = 0x74,\n\tHALMAC_RET_WLAN_MODE_FAIL = 0x75,\n\tHALMAC_RET_SDIO_SEQ_FAIL = 0x72,\n\tHALMAC_RET_INIT_XTAL_AAC_FAIL = 0x76,\n\tHALMAC_RET_FWFF_NO_EMPTY = 0x78,\n};\n\nenum halmac_chip_id {\n\tHALMAC_CHIP_ID_8822B = 0,\n\tHALMAC_CHIP_ID_8821C = 1,\n\tHALMAC_CHIP_ID_8814B = 2,\n\tHALMAC_CHIP_ID_8197F = 3,\n\tHALMAC_CHIP_ID_8822C = 4,\n\tHALMAC_CHIP_ID_8812F = 5,\n\tHALMAC_CHIP_ID_UNDEFINE = 0x7F,\n};\n\nenum halmac_chip_ver {\n\tHALMAC_CHIP_VER_A_CUT = 0x00,\n\tHALMAC_CHIP_VER_B_CUT = 0x01,\n\tHALMAC_CHIP_VER_C_CUT = 0x02,\n\tHALMAC_CHIP_VER_D_CUT = 0x03,\n\tHALMAC_CHIP_VER_E_CUT = 0x04,\n\tHALMAC_CHIP_VER_F_CUT = 0x05,\n\tHALMAC_CHIP_VER_TEST = 0xFF,\n\tHALMAC_CHIP_VER_UNDEFINE = 0x7FFF,\n};\n\nenum halmac_network_type_select {\n\tHALMAC_NETWORK_NO_LINK = 0,\n\tHALMAC_NETWORK_ADHOC = 1,\n\tHALMAC_NETWORK_INFRASTRUCTURE = 2,\n\tHALMAC_NETWORK_AP = 3,\n\tHALMAC_NETWORK_UNDEFINE = 0x7F,\n};\n\nenum halmac_transfer_mode_select {\n\tHALMAC_TRNSFER_NORMAL = 0x0,\n\tHALMAC_TRNSFER_LOOPBACK_DIRECT = 0xB,\n\tHALMAC_TRNSFER_LOOPBACK_DELAY = 0x3,\n\tHALMAC_TRNSFER_UNDEFINE = 0x7F,\n};\n\nenum halmac_dma_mapping {\n\tHALMAC_DMA_MAPPING_EXTRA = 0,\n\tHALMAC_DMA_MAPPING_LOW = 1,\n\tHALMAC_DMA_MAPPING_NORMAL = 2,\n\tHALMAC_DMA_MAPPING_HIGH = 3,\n\tHALMAC_DMA_MAPPING_UNDEFINE = 0x7F,\n};\n\nenum halmac_io_size {\n\tHALMAC_IO_BYTE = 0x0,\n\tHALMAC_IO_WORD = 0x1,\n\tHALMAC_IO_DWORD = 0x2,\n\tHALMAC_IO_UNDEFINE = 0x7F,\n};\n\n#define HALMAC_MAP2_HQ\t\tHALMAC_DMA_MAPPING_HIGH\n#define HALMAC_MAP2_NQ\t\tHALMAC_DMA_MAPPING_NORMAL\n#define HALMAC_MAP2_LQ\t\tHALMAC_DMA_MAPPING_LOW\n#define HALMAC_MAP2_EXQ\t\tHALMAC_DMA_MAPPING_EXTRA\n#define HALMAC_MAP2_UNDEF\tHALMAC_DMA_MAPPING_UNDEFINE\n\nenum halmac_txdesc_queue_tid {\n\tHALMAC_TXDESC_QSEL_TID0 = 0,\n\tHALMAC_TXDESC_QSEL_TID1 = 1,\n\tHALMAC_TXDESC_QSEL_TID2 = 2,\n\tHALMAC_TXDESC_QSEL_TID3 = 3,\n\tHALMAC_TXDESC_QSEL_TID4 = 4,\n\tHALMAC_TXDESC_QSEL_TID5 = 5,\n\tHALMAC_TXDESC_QSEL_TID6 = 6,\n\tHALMAC_TXDESC_QSEL_TID7 = 7,\n\tHALMAC_TXDESC_QSEL_TID8 = 8,\n\tHALMAC_TXDESC_QSEL_TID9 = 9,\n\tHALMAC_TXDESC_QSEL_TIDA = 10,\n\tHALMAC_TXDESC_QSEL_TIDB = 11,\n\tHALMAC_TXDESC_QSEL_TIDC = 12,\n\tHALMAC_TXDESC_QSEL_TIDD = 13,\n\tHALMAC_TXDESC_QSEL_TIDE = 14,\n\tHALMAC_TXDESC_QSEL_TIDF = 15,\n\n\tHALMAC_TXDESC_QSEL_BEACON = 0x10,\n\tHALMAC_TXDESC_QSEL_HIGH = 0x11,\n\tHALMAC_TXDESC_QSEL_MGT = 0x12,\n\tHALMAC_TXDESC_QSEL_H2C_CMD = 0x13,\n\tHALMAC_TXDESC_QSEL_FWCMD = 0x14,\n\n\tHALMAC_TXDESC_QSEL_UNDEFINE = 0x7F,\n};\n\nenum halmac_pq_map_id {\n\tHALMAC_PQ_MAP_VO = 0x0,\n\tHALMAC_PQ_MAP_VI = 0x1,\n\tHALMAC_PQ_MAP_BE = 0x2,\n\tHALMAC_PQ_MAP_BK = 0x3,\n\tHALMAC_PQ_MAP_MG = 0x4,\n\tHALMAC_PQ_MAP_HI = 0x5,\n\tHALMAC_PQ_MAP_NUM = 0x6,\n\tHALMAC_PQ_MAP_UNDEF = 0x7F,\n};\n\nenum halmac_qsel {\n\tHALMAC_QSEL_VO = HALMAC_TXDESC_QSEL_TID6,\n\tHALMAC_QSEL_VI = HALMAC_TXDESC_QSEL_TID4,\n\tHALMAC_QSEL_BE = HALMAC_TXDESC_QSEL_TID0,\n\tHALMAC_QSEL_BK = HALMAC_TXDESC_QSEL_TID1,\n\tHALMAC_QSEL_VO_V2 = HALMAC_TXDESC_QSEL_TID7,\n\tHALMAC_QSEL_VI_V2 = HALMAC_TXDESC_QSEL_TID5,\n\tHALMAC_QSEL_BE_V2 = HALMAC_TXDESC_QSEL_TID3,\n\tHALMAC_QSEL_BK_V2 = HALMAC_TXDESC_QSEL_TID2,\n\tHALMAC_QSEL_TID8 = HALMAC_TXDESC_QSEL_TID8,\n\tHALMAC_QSEL_TID9 = HALMAC_TXDESC_QSEL_TID9,\n\tHALMAC_QSEL_TIDA = HALMAC_TXDESC_QSEL_TIDA,\n\tHALMAC_QSEL_TIDB = HALMAC_TXDESC_QSEL_TIDB,\n\tHALMAC_QSEL_TIDC = HALMAC_TXDESC_QSEL_TIDC,\n\tHALMAC_QSEL_TIDD = HALMAC_TXDESC_QSEL_TIDD,\n\tHALMAC_QSEL_TIDE = HALMAC_TXDESC_QSEL_TIDE,\n\tHALMAC_QSEL_TIDF = HALMAC_TXDESC_QSEL_TIDF,\n\tHALMAC_QSEL_BCN = HALMAC_TXDESC_QSEL_BEACON,\n\tHALMAC_QSEL_HIGH = HALMAC_TXDESC_QSEL_HIGH,\n\tHALMAC_QSEL_MGNT = HALMAC_TXDESC_QSEL_MGT,\n\tHALMAC_QSEL_CMD = HALMAC_TXDESC_QSEL_H2C_CMD,\n\tHALMAC_QSEL_FWCMD = HALMAC_TXDESC_QSEL_FWCMD,\n\tHALMAC_QSEL_UNDEFINE = 0x7F,\n};\n\nenum halmac_acq_id {\n\tHALMAC_ACQ_ID_VO = 0,\n\tHALMAC_ACQ_ID_VI = 1,\n\tHALMAC_ACQ_ID_BE = 2,\n\tHALMAC_ACQ_ID_BK = 3,\n\tHALMAC_ACQ_ID_MAX = 0x7F,\n};\n\nenum halmac_txdesc_dma_ch {\n\tHALMAC_TXDESC_DMA_CH0 = 0,\n\tHALMAC_TXDESC_DMA_CH1 = 1,\n\tHALMAC_TXDESC_DMA_CH2 = 2,\n\tHALMAC_TXDESC_DMA_CH3 = 3,\n\tHALMAC_TXDESC_DMA_CH4 = 4,\n\tHALMAC_TXDESC_DMA_CH5 = 5,\n\tHALMAC_TXDESC_DMA_CH6 = 6,\n\tHALMAC_TXDESC_DMA_CH7 = 7,\n\tHALMAC_TXDESC_DMA_CH8 = 8,\n\tHALMAC_TXDESC_DMA_CH9 = 9,\n\tHALMAC_TXDESC_DMA_CH10 = 10,\n\tHALMAC_TXDESC_DMA_CH11 = 11,\n\tHALMAC_TXDESC_DMA_CH12 = 12,\n\tHALMAC_TXDESC_DMA_CH13 = 13,\n\tHALMAC_TXDESC_DMA_CH14 = 14,\n\tHALMAC_TXDESC_DMA_CH15 = 15,\n\tHALMAC_TXDESC_DMA_CH16 = 16,\n\tHALMAC_TXDESC_DMA_CH17 = 17,\n\tHALMAC_TXDESC_DMA_CH18 = 18,\n\tHALMAC_TXDESC_DMA_CH19 = 19,\n\tHALMAC_TXDESC_DMA_CH20 = 20,\n\tHALMAC_TXDESC_DMA_CHMAX,\n\tHALMAC_TXDESC_DMA_CHUNDEFINE = 0x7F,\n};\n\nenum halmac_dma_ch {\n\tHALMAC_DMA_CH_0 = HALMAC_TXDESC_DMA_CH0,\n\tHALMAC_DMA_CH_1 = HALMAC_TXDESC_DMA_CH1,\n\tHALMAC_DMA_CH_2 = HALMAC_TXDESC_DMA_CH2,\n\tHALMAC_DMA_CH_3 = HALMAC_TXDESC_DMA_CH3,\n\tHALMAC_DMA_CH_4 = HALMAC_TXDESC_DMA_CH4,\n\tHALMAC_DMA_CH_5 = HALMAC_TXDESC_DMA_CH5,\n\tHALMAC_DMA_CH_6 = HALMAC_TXDESC_DMA_CH6,\n\tHALMAC_DMA_CH_7 = HALMAC_TXDESC_DMA_CH7,\n\tHALMAC_DMA_CH_8 = HALMAC_TXDESC_DMA_CH8,\n\tHALMAC_DMA_CH_9 = HALMAC_TXDESC_DMA_CH9,\n\tHALMAC_DMA_CH_10 = HALMAC_TXDESC_DMA_CH10,\n\tHALMAC_DMA_CH_11 = HALMAC_TXDESC_DMA_CH11,\n\tHALMAC_DMA_CH_S0 = HALMAC_TXDESC_DMA_CH12,\n\tHALMAC_DMA_CH_S1 = HALMAC_TXDESC_DMA_CH13,\n\tHALMAC_DMA_CH_MGQ = HALMAC_TXDESC_DMA_CH14,\n\tHALMAC_DMA_CH_HIGH = HALMAC_TXDESC_DMA_CH15,\n\tHALMAC_DMA_CH_FWCMD = HALMAC_TXDESC_DMA_CH16,\n\tHALMAC_DMA_CH_MGQ_BAND1 = HALMAC_TXDESC_DMA_CH17,\n\tHALMAC_DMA_CH_HIGH_BAND1 = HALMAC_TXDESC_DMA_CH18,\n\tHALMAC_DMA_CH_BCN = HALMAC_TXDESC_DMA_CH19,\n\tHALMAC_DMA_CH_H2C = HALMAC_TXDESC_DMA_CH20,\n\tHALMAC_DMA_CH_MAX = HALMAC_TXDESC_DMA_CHMAX,\n\tHALMAC_DMA_CH_UNDEFINE = 0x7F,\n};\n\nenum halmac_interface {\n\tHALMAC_INTERFACE_PCIE = 0x0,\n\tHALMAC_INTERFACE_USB = 0x1,\n\tHALMAC_INTERFACE_SDIO = 0x2,\n\tHALMAC_INTERFACE_AXI = 0x3,\n\tHALMAC_INTERFACE_UNDEFINE = 0x7F,\n};\n\nenum halmac_rx_agg_mode {\n\tHALMAC_RX_AGG_MODE_NONE = 0x0,\n\tHALMAC_RX_AGG_MODE_DMA = 0x1,\n\tHALMAC_RX_AGG_MODE_USB = 0x2,\n\tHALMAC_RX_AGG_MODE_UNDEFINE = 0x7F,\n};\n\nstruct halmac_rxagg_th {\n\tu8 drv_define;\n\tu8 timeout;\n\tu8 size;\n\tu8 size_limit_en;\n};\n\nstruct halmac_rxagg_cfg {\n\tenum halmac_rx_agg_mode mode;\n\tstruct halmac_rxagg_th threshold;\n};\n\nstruct halmac_api_registry {\n\tu8 rx_exp_en:1;\n\tu8 la_mode_en:1;\n\tu8 cfg_drv_rsvd_pg_en:1;\n\tu8 sdio_cmd53_4byte_en:1;\n\tu8 rsvd:4;\n};\n\nenum halmac_trx_mode {\n\tHALMAC_TRX_MODE_NORMAL = 0x0,\n\tHALMAC_TRX_MODE_TRXSHARE = 0x1,\n\tHALMAC_TRX_MODE_WMM = 0x2,\n\tHALMAC_TRX_MODE_P2P = 0x3,\n\tHALMAC_TRX_MODE_LOOPBACK = 0x4,\n\tHALMAC_TRX_MODE_DELAY_LOOPBACK = 0x5,\n\tHALMAC_TRX_MODE_MAX = 0x6,\n\tHALMAC_TRX_MODE_WMM_LINUX = 0x7E,\n\tHALMAC_TRX_MODE_UNDEFINE = 0x7F,\n};\n\nenum halmac_wireless_mode {\n\tHALMAC_WIRELESS_MODE_B = 0x0,\n\tHALMAC_WIRELESS_MODE_G = 0x1,\n\tHALMAC_WIRELESS_MODE_N = 0x2,\n\tHALMAC_WIRELESS_MODE_AC = 0x3,\n\tHALMAC_WIRELESS_MODE_UNDEFINE = 0x7F,\n};\n\nenum halmac_bw {\n\tHALMAC_BW_20 = 0x00,\n\tHALMAC_BW_40 = 0x01,\n\tHALMAC_BW_80 = 0x02,\n\tHALMAC_BW_160 = 0x03,\n\tHALMAC_BW_5 = 0x04,\n\tHALMAC_BW_10 = 0x05,\n\tHALMAC_BW_MAX = 0x06,\n\tHALMAC_BW_UNDEFINE = 0x7F,\n};\n\nenum halmac_efuse_read_cfg {\n\tHALMAC_EFUSE_R_AUTO = 0x00,\n\tHALMAC_EFUSE_R_DRV = 0x01,\n\tHALMAC_EFUSE_R_FW = 0x02,\n\tHALMAC_EFUSE_R_UNDEFINE = 0x7F,\n};\n\nenum halmac_dlfw_mem {\n\tHALMAC_DLFW_MEM_EMEM = 0x00,\n\tHALMAC_DLFW_MEM_EMEM_RSVD_PG = 0x01,\n\tHALMAC_DLFW_MEM_UNDEFINE = 0x7F,\n};\n\nstruct halmac_tx_desc {\n\tu32 dword0;\n\tu32 dword1;\n\tu32 dword2;\n\tu32 dword3;\n\tu32 dword4;\n\tu32 dword5;\n\tu32 dword6;\n\tu32 dword7;\n\tu32 dword8;\n\tu32 dword9;\n\tu32 dword10;\n\tu32 dword11;\n};\n\nstruct halmac_rx_desc {\n\tu32 dword0;\n\tu32 dword1;\n\tu32 dword2;\n\tu32 dword3;\n\tu32 dword4;\n\tu32 dword5;\n};\n\nstruct halmac_bcn_ie_info {\n\tu8 func_en;\n\tu8 size_th;\n\tu8 timeout;\n\tu8 ie_bmp[HALMAC_BCN_IE_BMP_SIZE];\n};\n\nenum halmac_parameter_cmd {\n\t/* HALMAC_PARAMETER_CMD_LLT\t= 0x1, */\n\t/* HALMAC_PARAMETER_CMD_R_EFUSE = 0x2, */\n\t/* HALMAC_PARAMETER_CMD_EFUSE_PATCH = 0x3, */\n\tHALMAC_PARAMETER_CMD_MAC_W8 = 0x4,\n\tHALMAC_PARAMETER_CMD_MAC_W16 = 0x5,\n\tHALMAC_PARAMETER_CMD_MAC_W32 = 0x6,\n\tHALMAC_PARAMETER_CMD_RF_W = 0x7,\n\tHALMAC_PARAMETER_CMD_BB_W8 = 0x8,\n\tHALMAC_PARAMETER_CMD_BB_W16 = 0x9,\n\tHALMAC_PARAMETER_CMD_BB_W32 = 0XA,\n\tHALMAC_PARAMETER_CMD_DELAY_US = 0X10,\n\tHALMAC_PARAMETER_CMD_DELAY_MS = 0X11,\n\tHALMAC_PARAMETER_CMD_END = 0XFF,\n};\n\nunion halmac_parameter_content {\n\tstruct _MAC_REG_W {\n\t\tu32 value;\n\t\tu32 msk;\n\t\tu16 offset;\n\t\tu8 msk_en;\n\t} MAC_REG_W;\n\tstruct _BB_REG_W {\n\t\tu32 value;\n\t\tu32 msk;\n\t\tu16 offset;\n\t\tu8 msk_en;\n\t} BB_REG_W;\n\tstruct _RF_REG_W {\n\t\tu32 value;\n\t\tu32 msk;\n\t\tu8 offset;\n\t\tu8 msk_en;\n\t\tu8 rf_path;\n\t} RF_REG_W;\n\tstruct _DELAY_TIME {\n\t\tu32 rsvd1;\n\t\tu32 rsvd2;\n\t\tu16 delay_time;\n\t\tu8 rsvd3;\n\t} DELAY_TIME;\n};\n\nstruct halmac_phy_parameter_info {\n\tenum halmac_parameter_cmd cmd_id;\n\tunion halmac_parameter_content content;\n};\n\nstruct halmac_pg_efuse_info {\n\tu8 *efuse_map;\n\tu32 efuse_map_size;\n\tu8 *efuse_mask;\n\tu32 efuse_mask_size;\n};\n\nstruct halmac_cfg_param_info {\n\tu32 buf_size;\n\tu8 *buf;\n\tu8 *buf_wptr;\n\tu32 num;\n\tu32 avl_buf_size;\n\tu32 offset_accum;\n\tu32 value_accum;\n\tenum halmac_data_type data_type;\n\tu8 full_fifo_mode;\n};\n\nstruct halmac_hw_cfg_info {\n\tu32 efuse_size;\n\tu32 eeprom_size;\n\tu32 bt_efuse_size;\n\tu32 tx_fifo_size;\n\tu32 rx_fifo_size;\n\tu32 rx_desc_fifo_size;\n\tu32 page_size;\n\tu16 tx_align_size;\n\tu8 txdesc_size;\n\tu8 rxdesc_size;\n\tu8 cam_entry_num;\n\tu8 chk_security_keyid;\n\tu8 txdesc_ie_max_num;\n\tu8 txdesc_body_size;\n\tu8 ac_oqt_size;\n\tu8 non_ac_oqt_size;\n\tu8 acq_num;\n\tu8 trx_mode;\n\tu8 usb_txagg_num;\n\tu32 prtct_efuse_size;\n};\n\nstruct halmac_sdio_free_space {\n\tu16 hiq_pg_num;\n\tu16 miq_pg_num;\n\tu16 lowq_pg_num;\n\tu16 pubq_pg_num;\n\tu16 exq_pg_num;\n\tu8 ac_oqt_num;\n\tu8 non_ac_oqt_num;\n\tu8 ac_empty;\n\tu8 *macid_map;\n\tu32 macid_map_size;\n};\n\nenum hal_fifo_sel {\n\tHAL_FIFO_SEL_TX,\n\tHAL_FIFO_SEL_RX,\n\tHAL_FIFO_SEL_RSVD_PAGE,\n\tHAL_FIFO_SEL_REPORT,\n\tHAL_FIFO_SEL_LLT,\n\tHAL_FIFO_SEL_RXBUF_FW,\n\tHAL_FIFO_SEL_RXBUF_PHY,\n\tHAL_FIFO_SEL_RXDESC,\n\tHAL_BUF_SECURITY_CAM,\n\tHAL_BUF_WOW_CAM,\n\tHAL_BUF_RX_FILTER_CAM,\n\tHAL_BUF_BA_CAM,\n\tHAL_BUF_MBSSID_CAM\n};\n\nenum halmac_drv_info {\n\t/* No information is appended in rx_pkt */\n\tHALMAC_DRV_INFO_NONE,\n\t/* PHY status is appended after rx_desc */\n\tHALMAC_DRV_INFO_PHY_STATUS,\n\t/* PHY status and sniffer info are appended after rx_desc */\n\tHALMAC_DRV_INFO_PHY_SNIFFER,\n\t/* PHY status and plcp header are appended after rx_desc */\n\tHALMAC_DRV_INFO_PHY_PLCP,\n\tHALMAC_DRV_INFO_UNDEFINE,\n};\n\nenum halmac_pri_ch_idx {\n\tHALMAC_CH_IDX_UNDEFINE = 0,\n\tHALMAC_CH_IDX_1 = 1,\n\tHALMAC_CH_IDX_2 = 2,\n\tHALMAC_CH_IDX_3 = 3,\n\tHALMAC_CH_IDX_4 = 4,\n\tHALMAC_CH_IDX_MAX = 5,\n};\n\nstruct halmac_ch_info {\n\tenum halmac_cs_action_id action_id;\n\tenum halmac_bw bw;\n\tenum halmac_pri_ch_idx pri_ch_idx;\n\tu8 channel;\n\tu8 timeout;\n\tu8 extra_info;\n};\n\nstruct halmac_ch_extra_info {\n\tu8 extra_info;\n\tenum halmac_cs_extra_action_id extra_action_id;\n\tu8 extra_info_size;\n\tu8 *extra_info_data;\n};\n\nenum halmac_cs_periodic_option {\n\tHALMAC_CS_PERIODIC_NONE,\n\tHALMAC_CS_PERIODIC_NORMAL,\n\tHALMAC_CS_PERIODIC_2_PHASE,\n\tHALMAC_CS_PERIODIC_SEAMLESS,\n};\n\nstruct halmac_ch_switch_option {\n\tenum halmac_bw dest_bw;\n\tenum halmac_cs_periodic_option periodic_option;\n\tenum halmac_pri_ch_idx dest_pri_ch_idx;\n\t/* u32 tsf_high; */\n\tu32 tsf_low;\n\tu8 switch_en;\n\tu8 dest_ch_en;\n\tu8 absolute_time_en;\n\tu8 dest_ch;\n\tu8 normal_period;\n\tu8 normal_period_sel;\n\tu8 normal_cycle;\n\tu8 phase_2_period;\n\tu8 phase_2_period_sel;\n\tu8 nlo_en;\n};\n\nstruct halmac_p2pps {\n\tu8 offload_en:1;\n\tu8 role:1;\n\tu8 ctwindow_en:1;\n\tu8 noa_en:1;\n\tu8 noa_sel:1;\n\tu8 all_sta_sleep:1;\n\tu8 discovery:1;\n\tu8 disable_close_rf:1;\n\tu8 p2p_port_id;\n\tu8 p2p_group;\n\tu8 p2p_macid;\n\tu8 ctwindow_length;\n\tu8 rsvd3;\n\tu8 rsvd4;\n\tu8 rsvd5;\n\tu32 noa_duration_para;\n\tu32 noa_interval_para;\n\tu32 noa_start_time_para;\n\tu32 noa_count_para;\n};\n\nstruct halmac_fw_build_time {\n\tu16 year;\n\tu8 month;\n\tu8 date;\n\tu8 hour;\n\tu8 min;\n};\n\nstruct halmac_fw_version {\n\tu16 version;\n\tu8 sub_version;\n\tu8 sub_index;\n\tu16 h2c_version;\n\tstruct halmac_fw_build_time build_time;\n};\n\nenum halmac_rf_type {\n\tHALMAC_RF_1T2R = 0,\n\tHALMAC_RF_2T4R = 1,\n\tHALMAC_RF_2T2R = 2,\n\tHALMAC_RF_2T3R = 3,\n\tHALMAC_RF_1T1R = 4,\n\tHALMAC_RF_2T2R_GREEN = 5,\n\tHALMAC_RF_3T3R = 6,\n\tHALMAC_RF_3T4R = 7,\n\tHALMAC_RF_4T4R = 8,\n\tHALMAC_RF_MAX_TYPE = 0xF,\n};\n\nstruct halmac_general_info {\n\tu8 rfe_type;\n\tenum halmac_rf_type rf_type;\n\tu8 tx_ant_status;\n\tu8 rx_ant_status;\n};\n\nstruct halmac_pwr_tracking_para {\n\tu8 enable;\n\tu8 tx_pwr_index;\n\tu8 pwr_tracking_offset_value;\n\tu8 tssi_value;\n};\n\nstruct halmac_pwr_tracking_option {\n\tu8 type;\n\tu8 bbswing_index;\n\t/* pathA, pathB, pathC, pathD */\n\tstruct halmac_pwr_tracking_para pwr_tracking_para[4];\n};\n\nstruct halmac_fast_edca_cfg {\n\tenum halmac_acq_id acq_id;\n\tu8 queue_to; /* unit : 32us*/\n};\n\nstruct halmac_txfifo_lifetime_cfg {\n\tu8 enable;\n\tu32 lifetime;\n};\n\nenum halmac_data_rate {\n\tHALMAC_CCK1,\n\tHALMAC_CCK2,\n\tHALMAC_CCK5_5,\n\tHALMAC_CCK11,\n\tHALMAC_OFDM6,\n\tHALMAC_OFDM9,\n\tHALMAC_OFDM12,\n\tHALMAC_OFDM18,\n\tHALMAC_OFDM24,\n\tHALMAC_OFDM36,\n\tHALMAC_OFDM48,\n\tHALMAC_OFDM54,\n\tHALMAC_MCS0,\n\tHALMAC_MCS1,\n\tHALMAC_MCS2,\n\tHALMAC_MCS3,\n\tHALMAC_MCS4,\n\tHALMAC_MCS5,\n\tHALMAC_MCS6,\n\tHALMAC_MCS7,\n\tHALMAC_MCS8,\n\tHALMAC_MCS9,\n\tHALMAC_MCS10,\n\tHALMAC_MCS11,\n\tHALMAC_MCS12,\n\tHALMAC_MCS13,\n\tHALMAC_MCS14,\n\tHALMAC_MCS15,\n\tHALMAC_MCS16,\n\tHALMAC_MCS17,\n\tHALMAC_MCS18,\n\tHALMAC_MCS19,\n\tHALMAC_MCS20,\n\tHALMAC_MCS21,\n\tHALMAC_MCS22,\n\tHALMAC_MCS23,\n\tHALMAC_MCS24,\n\tHALMAC_MCS25,\n\tHALMAC_MCS26,\n\tHALMAC_MCS27,\n\tHALMAC_MCS28,\n\tHALMAC_MCS29,\n\tHALMAC_MCS30,\n\tHALMAC_MCS31,\n\tHALMAC_VHT_NSS1_MCS0,\n\tHALMAC_VHT_NSS1_MCS1,\n\tHALMAC_VHT_NSS1_MCS2,\n\tHALMAC_VHT_NSS1_MCS3,\n\tHALMAC_VHT_NSS1_MCS4,\n\tHALMAC_VHT_NSS1_MCS5,\n\tHALMAC_VHT_NSS1_MCS6,\n\tHALMAC_VHT_NSS1_MCS7,\n\tHALMAC_VHT_NSS1_MCS8,\n\tHALMAC_VHT_NSS1_MCS9,\n\tHALMAC_VHT_NSS2_MCS0,\n\tHALMAC_VHT_NSS2_MCS1,\n\tHALMAC_VHT_NSS2_MCS2,\n\tHALMAC_VHT_NSS2_MCS3,\n\tHALMAC_VHT_NSS2_MCS4,\n\tHALMAC_VHT_NSS2_MCS5,\n\tHALMAC_VHT_NSS2_MCS6,\n\tHALMAC_VHT_NSS2_MCS7,\n\tHALMAC_VHT_NSS2_MCS8,\n\tHALMAC_VHT_NSS2_MCS9,\n\tHALMAC_VHT_NSS3_MCS0,\n\tHALMAC_VHT_NSS3_MCS1,\n\tHALMAC_VHT_NSS3_MCS2,\n\tHALMAC_VHT_NSS3_MCS3,\n\tHALMAC_VHT_NSS3_MCS4,\n\tHALMAC_VHT_NSS3_MCS5,\n\tHALMAC_VHT_NSS3_MCS6,\n\tHALMAC_VHT_NSS3_MCS7,\n\tHALMAC_VHT_NSS3_MCS8,\n\tHALMAC_VHT_NSS3_MCS9,\n\tHALMAC_VHT_NSS4_MCS0,\n\tHALMAC_VHT_NSS4_MCS1,\n\tHALMAC_VHT_NSS4_MCS2,\n\tHALMAC_VHT_NSS4_MCS3,\n\tHALMAC_VHT_NSS4_MCS4,\n\tHALMAC_VHT_NSS4_MCS5,\n\tHALMAC_VHT_NSS4_MCS6,\n\tHALMAC_VHT_NSS4_MCS7,\n\tHALMAC_VHT_NSS4_MCS8,\n\tHALMAC_VHT_NSS4_MCS9,\n\t /*FPGA only*/\n\tHALMAC_VHT_NSS5_MCS0,\n\tHALMAC_VHT_NSS6_MCS0,\n\tHALMAC_VHT_NSS7_MCS0,\n\tHALMAC_VHT_NSS8_MCS0\n};\n\nenum halmac_rf_path {\n\tHALMAC_RF_PATH_A,\n\tHALMAC_RF_PATH_B,\n\tHALMAC_RF_PATH_C,\n\tHALMAC_RF_PATH_D\n};\n\nenum hal_security_type {\n\tHAL_SECURITY_TYPE_NONE = 0,\n\tHAL_SECURITY_TYPE_WEP40 = 1,\n\tHAL_SECURITY_TYPE_WEP104 = 2,\n\tHAL_SECURITY_TYPE_TKIP = 3,\n\tHAL_SECURITY_TYPE_AES128 = 4,\n\tHAL_SECURITY_TYPE_WAPI = 5,\n\tHAL_SECURITY_TYPE_AES256 = 6,\n\tHAL_SECURITY_TYPE_GCMP128 = 7,\n\tHAL_SECURITY_TYPE_GCMP256 = 8,\n\tHAL_SECURITY_TYPE_GCMSMS4 = 9,\n\tHAL_SECURITY_TYPE_BIP = 10,\n\tHAL_SECURITY_TYPE_UNDEFINE = 0x7F,\n};\n\nenum hal_intf_phy {\n\tHAL_INTF_PHY_USB2 = 0,\n\tHAL_INTF_PHY_USB3 = 1,\n\tHAL_INTF_PHY_PCIE_GEN1 = 2,\n\tHAL_INTF_PHY_PCIE_GEN2 = 3,\n\tHAL_INTF_PHY_UNDEFINE = 0x7F,\n};\n\nstruct halmac_cut_amsdu_cfg {\n\tu8 cut_amsdu_en;\n\tu8 chk_len_en;\n\tu8 chk_len_def_val;\n\tu8 chk_len_l_th;\n\tu16 chk_len_h_th;\n};\n\nenum halmac_dbg_msg_info {\n\tHALMAC_DBG_ALWAYS,\n\tHALMAC_DBG_ERR,\n\tHALMAC_DBG_WARN,\n\tHALMAC_DBG_TRACE,\n};\n\nenum halmac_dbg_msg_type {\n\tHALMAC_MSG_INIT,\n\tHALMAC_MSG_EFUSE,\n\tHALMAC_MSG_FW,\n\tHALMAC_MSG_H2C,\n\tHALMAC_MSG_PWR,\n\tHALMAC_MSG_SND,\n\tHALMAC_MSG_COMMON,\n\tHALMAC_MSG_DBI,\n\tHALMAC_MSG_MDIO,\n\tHALMAC_MSG_USB,\n};\n\nenum halmac_feature_id {\n\tHALMAC_FEATURE_CFG_PARA,                /* Support */\n\tHALMAC_FEATURE_DUMP_PHYSICAL_EFUSE,     /* Support */\n\tHALMAC_FEATURE_DUMP_LOGICAL_EFUSE,      /* Support */\n\tHALMAC_FEATURE_UPDATE_PACKET,           /* Support */\n\tHALMAC_FEATURE_UPDATE_DATAPACK,\n\tHALMAC_FEATURE_RUN_DATAPACK,\n\tHALMAC_FEATURE_CHANNEL_SWITCH,  /* Support */\n\tHALMAC_FEATURE_IQK,             /* Support */\n\tHALMAC_FEATURE_POWER_TRACKING,  /* Support */\n\tHALMAC_FEATURE_PSD,             /* Support */\n\tHALMAC_FEATURE_FW_SNDING,       /* Support */\n\tHALMAC_FEATURE_ALL,             /* Support, only for reset */\n};\n\nenum halmac_drv_rsvd_pg_num {\n\tHALMAC_RSVD_PG_NUM8,\t/* 1K */\n\tHALMAC_RSVD_PG_NUM16,   /* 2K */\n\tHALMAC_RSVD_PG_NUM24,   /* 3K */\n\tHALMAC_RSVD_PG_NUM32,   /* 4K */\n\tHALMAC_RSVD_PG_NUM64,   /* 8K */\n\tHALMAC_RSVD_PG_NUM128,  /* 16K */\n\tHALMAC_RSVD_PG_NUM256,  /* 32K */\n};\n\nenum halmac_pcie_cfg {\n\tHALMAC_PCIE_GEN1,\n\tHALMAC_PCIE_GEN2,\n\tHALMAC_PCIE_CFG_UNDEFINE,\n};\n\nenum halmac_portid {\n\tHALMAC_PORTID0 = 0,\n\tHALMAC_PORTID1 = 1,\n\tHALMAC_PORTID2 = 2,\n\tHALMAC_PORTID3 = 3,\n\tHALMAC_PORTID4 = 4,\n\tHALMAC_PORTID_NUM = 5,\n};\n\nstruct halmac_bcn_ctrl {\n\tu8 dis_rx_bssid_fit;\n\tu8 en_txbcn_rpt;\n\tu8 dis_tsf_udt;\n\tu8 en_bcn;\n\tu8 en_rxbcn_rpt;\n\tu8 en_p2p_ctwin;\n\tu8 en_p2p_bcn_area;\n};\n\n/* User only can use  Address[6]*/\n/* Address[0] is lowest, Address[5] is highest */\nunion halmac_wlan_addr {\n\tu8 addr[6];\n\tstruct {\n\t\tunion {\n\t\t\t__le32 low;\n\t\t\tu8 low_byte[4];\n\t\t};\n\t\tunion {\n\t\t\t__le16 high;\n\t\t\tu8 high_byte[2];\n\t\t};\n\t} addr_l_h;\n};\n\nstruct halmac_platform_api {\n\t/* R/W register */\n\tu8 (*SDIO_CMD52_READ)(void *drv_adapter, u32 offset);\n\tu8 (*SDIO_CMD53_READ_8)(void *drv_adapter, u32 offset);\n\tu16 (*SDIO_CMD53_READ_16)(void *drv_adapter, u32 offset);\n\tu32 (*SDIO_CMD53_READ_32)(void *drv_adapter, u32 offset);\n\tu8 (*SDIO_CMD53_READ_N)(void *drv_adapter, u32 offset, u32 size,\n\t\t\t\tu8 *data);\n\tvoid (*SDIO_CMD52_WRITE)(void *drv_adapter, u32 offset, u8 value);\n\tvoid (*SDIO_CMD53_WRITE_8)(void *drv_adapter, u32 offset, u8 value);\n\tvoid (*SDIO_CMD53_WRITE_16)(void *drv_adapter, u32 offset, u16 value);\n\tvoid (*SDIO_CMD53_WRITE_32)(void *drv_adapter, u32 offset, u32 value);\n\tu8 (*REG_READ_8)(void *drv_adapter, u32 offset);\n\tu16 (*REG_READ_16)(void *drv_adapter, u32 offset);\n\tu32 (*REG_READ_32)(void *drv_adapter, u32 offset);\n\tvoid (*REG_WRITE_8)(void *drv_adapter, u32 offset, u8 value);\n\tvoid (*REG_WRITE_16)(void *drv_adapter, u32 offset, u16 value);\n\tvoid (*REG_WRITE_32)(void *drv_adapter, u32 offset, u32 value);\n\tu8 (*SDIO_CMD52_CIA_READ)(void *drv_adapter, u32 offset);\n\n\t/* send pBuf to reserved page, the tx_desc is not included in pBuf */\n\t/* driver need to fill tx_desc with qsel = bcn */\n\tu8 (*SEND_RSVD_PAGE)(void *drv_adapter, u8 *buf, u32 size);\n\t/* send pBuf to h2c queue, the tx_desc is not included in pBuf */\n\t/* driver need to fill tx_desc with qsel = h2c */\n\tu8 (*SEND_H2C_PKT)(void *drv_adapter, u8 *buf, u32 size);\n\n\tu8 (*RTL_FREE)(void *drv_adapter, void *buf, u32 size);\n\tvoid* (*RTL_MALLOC)(void *drv_adapter, u32 size);\n\tu8 (*RTL_MEMCPY)(void *drv_adapter, void *dest, void *src, u32 size);\n\tu8 (*RTL_MEMSET)(void *drv_adapter, void *addr, u8 value, u32 size);\n\tvoid (*RTL_DELAY_US)(void *drv_adapter, u32 us);\n\n\tu8 (*MUTEX_INIT)(void *drv_adapter, HALMAC_MUTEX *mutex);\n\tu8 (*MUTEX_DEINIT)(void *drv_adapter, HALMAC_MUTEX *mutex);\n\tu8 (*MUTEX_LOCK)(void *drv_adapter, HALMAC_MUTEX *mutex);\n\tu8 (*MUTEX_UNLOCK)(void *drv_adapter, HALMAC_MUTEX *mutex);\n\n\tu8 (*MSG_PRINT)(void *drv_adapter, u32 msg_type, u8 msg_level,\n\t\t\ts8 *fmt, ...);\n\tu8 (*BUFF_PRINT)(void *drv_adapter, u32 msg_type, u8 msg_level, s8 *buf,\n\t\t\t u32 size);\n\n\tu8 (*EVENT_INDICATION)(void *drv_adapter,\n\t\t\t       enum halmac_feature_id feature_id,\n\t\t\t       enum halmac_cmd_process_status process_status,\n\t\t\t       u8 *buf, u32 size);\n\n#if HALMAC_PLATFORM_TESTPROGRAM\n\tstruct halmisc_platform_api *halmisc_pltfm_api;\n#endif\n};\n\nenum halmac_snd_role {\n\tHAL_BFER = 0,\n\tHAL_BFEE = 1,\n};\n\nenum halmac_csi_seg_len {\n\tHAL_CSI_SEG_4K = 0,\n\tHAL_CSI_SEG_8K = 1,\n\tHAL_CSI_SEG_11K = 2,\n};\n\nstruct halmac_cfg_mumimo_para {\n\tenum halmac_snd_role role;\n\tu8 sounding_sts[6];\n\tu16 grouping_bitmap;\n\tu8 mu_tx_en;\n\tu32 given_gid_tab[2];\n\tu32 given_user_pos[4];\n};\n\nstruct halmac_su_bfer_init_para {\n\tu8 userid;\n\tu16 paid;\n\tu16 csi_para;\n\tunion halmac_wlan_addr bfer_address;\n};\n\nstruct halmac_mu_bfee_init_para {\n\tu8 userid;\n\tu16 paid;\n\tu32 user_position_l;\t/*for gid 0~15*/\n\tu32 user_position_h;\t/*for gid 16~31*/\n\tu32 user_position_l_1;\t/*for gid 32~47*/\n\tu32 user_position_h_1;\t/*for gid 48~63*/\n};\n\nstruct halmac_mu_bfer_init_para {\n\tu16 paid;\n\tu16 csi_para;\n\tu16 my_aid;\n\tenum halmac_csi_seg_len csi_length_sel;\n\tunion halmac_wlan_addr bfer_address;\n};\n\nstruct halmac_ch_sw_info {\n\tu8 *buf;\n\tu8 *buf_wptr;\n\tu8 extra_info_en;\n\tu32 buf_size;\n\tu32 avl_buf_size;\n\tu32 total_size;\n\tu32 ch_num;\n};\n\nstruct halmac_event_trigger {\n\tu32 phy_efuse_map : 1;\n\tu32 log_efuse_map : 1;\n\tu32 rsvd1 : 28;\n};\n\nstruct halmac_h2c_header_info {\n\tu16 sub_cmd_id;\n\tu16 content_size;\n\tu8 ack;\n};\n\nstruct halmac_ver {\n\tu8 major_ver;\n\tu8 prototype_ver;\n\tu8 minor_ver;\n};\n\nenum halmac_api_id {\n\t/*stuff, need to be the 1st*/\n\tHALMAC_API_STUFF = 0x0,\n\t/*stuff, need to be the 1st*/\n\tHALMAC_API_MAC_POWER_SWITCH = 0x1,\n\tHALMAC_API_DOWNLOAD_FIRMWARE = 0x2,\n\tHALMAC_API_CFG_MAC_ADDR = 0x3,\n\tHALMAC_API_CFG_BSSID = 0x4,\n\tHALMAC_API_CFG_MULTICAST_ADDR = 0x5,\n\tHALMAC_API_PRE_INIT_SYSTEM_CFG = 0x6,\n\tHALMAC_API_INIT_SYSTEM_CFG = 0x7,\n\tHALMAC_API_INIT_TRX_CFG = 0x8,\n\tHALMAC_API_CFG_RX_AGGREGATION = 0x9,\n\tHALMAC_API_INIT_PROTOCOL_CFG = 0xA,\n\tHALMAC_API_INIT_EDCA_CFG = 0xB,\n\tHALMAC_API_CFG_OPERATION_MODE = 0xC,\n\tHALMAC_API_CFG_CH_BW = 0xD,\n\tHALMAC_API_CFG_BW = 0xE,\n\tHALMAC_API_INIT_WMAC_CFG = 0xF,\n\tHALMAC_API_INIT_MAC_CFG = 0x10,\n\tHALMAC_API_INIT_SDIO_CFG = 0x11,\n\tHALMAC_API_INIT_USB_CFG = 0x12,\n\tHALMAC_API_INIT_PCIE_CFG = 0x13,\n\tHALMAC_API_INIT_INTERFACE_CFG = 0x14,\n\tHALMAC_API_DEINIT_SDIO_CFG = 0x15,\n\tHALMAC_API_DEINIT_USB_CFG = 0x16,\n\tHALMAC_API_DEINIT_PCIE_CFG = 0x17,\n\tHALMAC_API_DEINIT_INTERFACE_CFG = 0x18,\n\tHALMAC_API_GET_EFUSE_SIZE = 0x19,\n\tHALMAC_API_DUMP_EFUSE_MAP = 0x1A,\n\tHALMAC_API_GET_LOGICAL_EFUSE_SIZE = 0x1D,\n\tHALMAC_API_DUMP_LOGICAL_EFUSE_MAP = 0x1E,\n\tHALMAC_API_WRITE_LOGICAL_EFUSE = 0x1F,\n\tHALMAC_API_READ_LOGICAL_EFUSE = 0x20,\n\tHALMAC_API_PG_EFUSE_BY_MAP = 0x21,\n\tHALMAC_API_GET_C2H_INFO = 0x22,\n\tHALMAC_API_CFG_FWLPS_OPTION = 0x23,\n\tHALMAC_API_CFG_FWIPS_OPTION = 0x24,\n\tHALMAC_API_ENTER_WOWLAN = 0x25,\n\tHALMAC_API_LEAVE_WOWLAN = 0x26,\n\tHALMAC_API_ENTER_PS = 0x27,\n\tHALMAC_API_LEAVE_PS = 0x28,\n\tHALMAC_API_H2C_LB = 0x29,\n\tHALMAC_API_DEBUG = 0x2A,\n\tHALMAC_API_CFG_PARAMETER = 0x2B,\n\tHALMAC_API_UPDATE_PACKET = 0x2C,\n\tHALMAC_API_BCN_IE_FILTER = 0x2D,\n\tHALMAC_API_REG_READ_8 = 0x2E,\n\tHALMAC_API_REG_WRITE_8 = 0x2F,\n\tHALMAC_API_REG_READ_16 = 0x30,\n\tHALMAC_API_REG_WRITE_16 = 0x31,\n\tHALMAC_API_REG_READ_32 = 0x32,\n\tHALMAC_API_REG_WRITE_32 = 0x33,\n\tHALMAC_API_TX_ALLOWED_SDIO = 0x34,\n\tHALMAC_API_SET_BULKOUT_NUM = 0x35,\n\tHALMAC_API_GET_SDIO_TX_ADDR = 0x36,\n\tHALMAC_API_GET_USB_BULKOUT_ID = 0x37,\n\tHALMAC_API_TIMER_2S = 0x38,\n\tHALMAC_API_FILL_TXDESC_CHECKSUM = 0x39,\n\tHALMAC_API_SEND_ORIGINAL_H2C = 0x3A,\n\tHALMAC_API_UPDATE_DATAPACK = 0x3B,\n\tHALMAC_API_RUN_DATAPACK = 0x3C,\n\tHALMAC_API_CFG_DRV_INFO = 0x3D,\n\tHALMAC_API_SEND_BT_COEX = 0x3E,\n\tHALMAC_API_VERIFY_PLATFORM_API = 0x3F,\n\tHALMAC_API_GET_FIFO_SIZE = 0x40,\n\tHALMAC_API_DUMP_FIFO = 0x41,\n\tHALMAC_API_CFG_TXBF = 0x42,\n\tHALMAC_API_CFG_MUMIMO = 0x43,\n\tHALMAC_API_CFG_SOUNDING = 0x44,\n\tHALMAC_API_DEL_SOUNDING = 0x45,\n\tHALMAC_API_SU_BFER_ENTRY_INIT = 0x46,\n\tHALMAC_API_SU_BFEE_ENTRY_INIT = 0x47,\n\tHALMAC_API_MU_BFER_ENTRY_INIT = 0x48,\n\tHALMAC_API_MU_BFEE_ENTRY_INIT = 0x49,\n\tHALMAC_API_SU_BFER_ENTRY_DEL = 0x4A,\n\tHALMAC_API_SU_BFEE_ENTRY_DEL = 0x4B,\n\tHALMAC_API_MU_BFER_ENTRY_DEL = 0x4C,\n\tHALMAC_API_MU_BFEE_ENTRY_DEL = 0x4D,\n\tHALMAC_API_ADD_CH_INFO = 0x4E,\n\tHALMAC_API_ADD_EXTRA_CH_INFO = 0x4F,\n\tHALMAC_API_CTRL_CH_SWITCH = 0x50,\n\tHALMAC_API_CLEAR_CH_INFO = 0x51,\n\tHALMAC_API_SEND_GENERAL_INFO = 0x52,\n\tHALMAC_API_START_IQK = 0x53,\n\tHALMAC_API_CTRL_PWR_TRACKING = 0x54,\n\tHALMAC_API_PSD = 0x55,\n\tHALMAC_API_CFG_TX_AGG_ALIGN = 0x56,\n\tHALMAC_API_QUERY_STATE = 0x57,\n\tHALMAC_API_RESET_FEATURE = 0x58,\n\tHALMAC_API_CHECK_FW_STATUS = 0x59,\n\tHALMAC_API_DUMP_FW_DMEM = 0x5A,\n\tHALMAC_API_CFG_MAX_DL_SIZE = 0x5B,\n\tHALMAC_API_INIT_OBJ = 0x5C,\n\tHALMAC_API_DEINIT_OBJ = 0x5D,\n\tHALMAC_API_CFG_LA_MODE = 0x5E,\n\tHALMAC_API_GET_HW_VALUE = 0x5F,\n\tHALMAC_API_SET_HW_VALUE = 0x60,\n\tHALMAC_API_CFG_DRV_RSVD_PG_NUM = 0x61,\n\tHALMAC_API_WRITE_EFUSE_BT = 0x63,\n\tHALMAC_API_DUMP_EFUSE_MAP_BT = 0x64,\n\tHALMAC_API_DL_DRV_RSVD_PG = 0x65,\n\tHALMAC_API_PCIE_SWITCH = 0x66,\n\tHALMAC_API_PHY_CFG = 0x67,\n\tHALMAC_API_CFG_RX_FIFO_EXPANDING_MODE = 0x68,\n\tHALMAC_API_CFG_CSI_RATE = 0x69,\n\tHALMAC_API_P2PPS = 0x6A,\n\tHALMAC_API_CFG_TX_ADDR = 0x6B,\n\tHALMAC_API_CFG_NET_TYPE = 0x6C,\n\tHALMAC_API_CFG_TSF_RESET = 0x6D,\n\tHALMAC_API_CFG_BCN_SPACE = 0x6E,\n\tHALMAC_API_CFG_BCN_CTRL = 0x6F,\n\tHALMAC_API_CFG_SIDEBAND_INT = 0x70,\n\tHALMAC_API_REGISTER_API = 0x71,\n\tHALMAC_API_FREE_DOWNLOAD_FIRMWARE = 0x72,\n\tHALMAC_API_GET_FW_VERSION = 0x73,\n\tHALMAC_API_GET_EFUSE_AVAL_SIZE = 0x74,\n\tHALMAC_API_CHK_TXDESC = 0x75,\n\tHALMAC_API_SDIO_CMD53_4BYTE = 0x76,\n\tHALMAC_API_CFG_TRANS_ADDR = 0x77,\n\tHALMAC_API_INTF_INTEGRA_TUNING\t= 0x78,\n\tHALMAC_API_TXFIFO_IS_EMPTY = 0x79,\n\tHALMAC_API_DOWNLOAD_FLASH = 0x7A,\n\tHALMAC_API_READ_FLASH = 0x7B,\n\tHALMAC_API_ERASE_FLASH = 0x7C,\n\tHALMAC_API_CHECK_FLASH = 0x7D,\n\tHALMAC_API_SDIO_HW_INFO = 0x80,\n\tHALMAC_API_READ_EFUSE_BT = 0x81,\n\tHALMAC_API_CFG_EFUSE_AUTO_CHECK = 0x82,\n\tHALMAC_API_CFG_PINMUX_GET_FUNC = 0x83,\n\tHALMAC_API_CFG_PINMUX_SET_FUNC = 0x84,\n\tHALMAC_API_CFG_PINMUX_FREE_FUNC = 0x85,\n\tHALMAC_API_CFG_PINMUX_WL_LED_MODE = 0x86,\n\tHALMAC_API_CFG_PINMUX_WL_LED_SW_CTRL = 0x87,\n\tHALMAC_API_CFG_PINMUX_SDIO_INT_POLARITY = 0x88,\n\tHALMAC_API_CFG_PINMUX_GPIO_MODE = 0x89,\n\tHALMAC_API_CFG_PINMUX_GPIO_OUTPUT = 0x90,\n\tHALMAC_API_REG_READ_INDIRECT_32 = 0x91,\n\tHALMAC_API_REG_SDIO_CMD53_READ_N = 0x92,\n\tHALMAC_API_PINMUX_PIN_STATUS = 0x94,\n\tHALMAC_API_OFLD_FUNC_CFG = 0x95,\n\tHALMAC_API_MASK_LOGICAL_EFUSE = 0x96,\n\tHALMAC_API_RX_CUT_AMSDU_CFG = 0x97,\n\tHALMAC_API_FW_SNDING = 0x98,\n\tHALMAC_API_ENTER_CPU_SLEEP_MODE = 0x99,\n\tHALMAC_API_GET_CPU_MODE = 0x9A,\n\tHALMAC_API_DRV_FWCTRL = 0x9B,\n\tHALMAC_API_EN_REF_AUTOK = 0x9C,\n\tHALMAC_API_RESET_WIFI_FW = 0x9D,\n\tHALMAC_API_CFGSPC_SET_PCIE = 0x9E,\n\tHALMAC_API_MAX\n};\n\nenum halmac_la_mode {\n\tHALMAC_LA_MODE_DISABLE = 0,\n\tHALMAC_LA_MODE_PARTIAL = 1,\n\tHALMAC_LA_MODE_FULL = 2,\n\tHALMAC_LA_MODE_UNDEFINE = 0x7F,\n};\n\nenum halmac_rx_fifo_expanding_mode {\n\tHALMAC_RX_FIFO_EXPANDING_MODE_DISABLE = 0,\n\tHALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK = 1,\n\tHALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK = 2,\n\tHALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK = 3,\n\tHALMAC_RX_FIFO_EXPANDING_MODE_4_BLOCK = 4,\n\tHALMAC_RX_FIFO_EXPANDING_MODE_UNDEFINE = 0x7F,\n};\n\nenum halmac_sdio_cmd53_4byte_mode {\n\tHALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE = 0,\n\tHALMAC_SDIO_CMD53_4BYTE_MODE_RW = 1,\n\tHALMAC_SDIO_CMD53_4BYTE_MODE_R = 2,\n\tHALMAC_SDIO_CMD53_4BYTE_MODE_W = 3,\n\tHALMAC_SDIO_CMD53_4BYTE_MODE_UNDEFINE = 0x7F,\n};\n\nenum halmac_usb_mode {\n\tHALMAC_USB_MODE_U2 = 1,\n\tHALMAC_USB_MODE_U3 = 2,\n};\n\nenum halmac_sdio_tx_format {\n\tHALMAC_SDIO_AGG_MODE = 1,\n\tHALMAC_SDIO_DUMMY_BLOCK_MODE = 2,\n\tHALMAC_SDIO_DUMMY_AUTO_MODE = 3,\n};\n\nenum halmac_sdio_clk_monitor {\n\tHALMAC_MONITOR_5US = 1,\n\tHALMAC_MONITOR_50US = 2,\n\tHALMAC_MONITOR_9MS = 3,\n};\n\nenum halmac_hw_id {\n\t/* Get HW value */\n\tHALMAC_HW_RQPN_MAPPING = 0x00,\n\tHALMAC_HW_EFUSE_SIZE = 0x01,\n\tHALMAC_HW_EEPROM_SIZE = 0x02,\n\tHALMAC_HW_BT_BANK_EFUSE_SIZE = 0x03,\n\tHALMAC_HW_BT_BANK1_EFUSE_SIZE = 0x04,\n\tHALMAC_HW_BT_BANK2_EFUSE_SIZE = 0x05,\n\tHALMAC_HW_TXFIFO_SIZE = 0x06,\n\tHALMAC_HW_RXFIFO_SIZE = 0x07,\n\tHALMAC_HW_RSVD_PG_BNDY = 0x08,\n\tHALMAC_HW_CAM_ENTRY_NUM = 0x09,\n\tHALMAC_HW_IC_VERSION = 0x0A,\n\tHALMAC_HW_PAGE_SIZE = 0x0B,\n\tHALMAC_HW_TX_AGG_ALIGN_SIZE = 0x0C,\n\tHALMAC_HW_RX_AGG_ALIGN_SIZE = 0x0D,\n\tHALMAC_HW_DRV_INFO_SIZE = 0x0E,\n\tHALMAC_HW_TXFF_ALLOCATION = 0x0F,\n\tHALMAC_HW_RSVD_EFUSE_SIZE = 0x10,\n\tHALMAC_HW_FW_HDR_SIZE = 0x11,\n\tHALMAC_HW_TX_DESC_SIZE = 0x12,\n\tHALMAC_HW_RX_DESC_SIZE = 0x13,\n\tHALMAC_HW_FW_MAX_SIZE = 0x14,\n\tHALMAC_HW_ORI_H2C_SIZE = 0x15,\n\tHALMAC_HW_RSVD_DRV_PGNUM = 0x16,\n\tHALMAC_HW_TX_PAGE_SIZE = 0x17,\n\tHALMAC_HW_USB_TXAGG_DESC_NUM = 0x18,\n\tHALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 0x19,\n\tHALMAC_HW_AC_OQT_SIZE = 0x1C,\n\tHALMAC_HW_NON_AC_OQT_SIZE = 0x1D,\n\tHALMAC_HW_AC_QUEUE_NUM = 0x1E,\n\tHALMAC_HW_RQPN_CH_MAPPING = 0x1F,\n\tHALMAC_HW_PWR_STATE = 0x20,\n\tHALMAC_HW_SDIO_INT_LAT = 0x21,\n\tHALMAC_HW_SDIO_CLK_CNT = 0x22,\n\t/* Set HW value */\n\tHALMAC_HW_USB_MODE = 0x60,\n\tHALMAC_HW_SEQ_EN = 0x61,\n\tHALMAC_HW_BANDWIDTH = 0x62,\n\tHALMAC_HW_CHANNEL = 0x63,\n\tHALMAC_HW_PRI_CHANNEL_IDX = 0x64,\n\tHALMAC_HW_EN_BB_RF = 0x65,\n\tHALMAC_HW_SDIO_TX_PAGE_THRESHOLD = 0x66,\n\tHALMAC_HW_AMPDU_CONFIG = 0x67,\n\tHALMAC_HW_RX_SHIFT = 0x68,\n\tHALMAC_HW_TXDESC_CHECKSUM = 0x69,\n\tHALMAC_HW_RX_CLK_GATE = 0x6A,\n\tHALMAC_HW_RXGCK_FIFO = 0x6B,\n\tHALMAC_HW_RX_IGNORE = 0x6C,\n\tHALMAC_HW_SDIO_TX_FORMAT = 0x6D,\n\tHALMAC_HW_FAST_EDCA = 0x6E,\n\tHALMAC_HW_LDO25_EN = 0x6F,\n\tHALMAC_HW_PCIE_REF_AUTOK = 0x70,\n\tHALMAC_HW_RTS_FULL_BW = 0x71,\n\tHALMAC_HW_FREE_CNT_EN = 0x72,\n\tHALMAC_HW_SDIO_WT_EN = 0x73,\n\tHALMAC_HW_SDIO_CLK_MONITOR = 0x74,\n\tHALMAC_HW_TXFIFO_LIFETIME = 0x75,\n\tHALMAC_HW_ID_UNDEFINE = 0x7F,\n};\n\nenum halmac_efuse_bank {\n\tHALMAC_EFUSE_BANK_WIFI = 0,\n\tHALMAC_EFUSE_BANK_BT = 1,\n\tHALMAC_EFUSE_BANK_BT_1 = 2,\n\tHALMAC_EFUSE_BANK_BT_2 = 3,\n\tHALMAC_EFUSE_BANK_MAX,\n\tHALMAC_EFUSE_BANK_UNDEFINE = 0X7F,\n};\n\nenum halmac_sdio_spec_ver {\n\tHALMAC_SDIO_SPEC_VER_2_00 = 0,\n\tHALMAC_SDIO_SPEC_VER_3_00 = 1,\n\tHALMAC_SDIO_SPEC_VER_UNDEFINE = 0X7F,\n};\n\nenum halmac_gpio_func {\n\tHALMAC_GPIO_FUNC_WL_LED = 0,\n\tHALMAC_GPIO_FUNC_SDIO_INT = 1,\n\tHALMAC_GPIO_FUNC_SW_IO_0 = 2,\n\tHALMAC_GPIO_FUNC_SW_IO_1 = 3,\n\tHALMAC_GPIO_FUNC_SW_IO_2 = 4,\n\tHALMAC_GPIO_FUNC_SW_IO_3 = 5,\n\tHALMAC_GPIO_FUNC_SW_IO_4 = 6,\n\tHALMAC_GPIO_FUNC_SW_IO_5 = 7,\n\tHALMAC_GPIO_FUNC_SW_IO_6 = 8,\n\tHALMAC_GPIO_FUNC_SW_IO_7 = 9,\n\tHALMAC_GPIO_FUNC_SW_IO_8 = 10,\n\tHALMAC_GPIO_FUNC_SW_IO_9 = 11,\n\tHALMAC_GPIO_FUNC_SW_IO_10 = 12,\n\tHALMAC_GPIO_FUNC_SW_IO_11 = 13,\n\tHALMAC_GPIO_FUNC_SW_IO_12 = 14,\n\tHALMAC_GPIO_FUNC_SW_IO_13 = 15,\n\tHALMAC_GPIO_FUNC_SW_IO_14 = 16,\n\tHALMAC_GPIO_FUNC_SW_IO_15 = 17,\n\tHALMAC_GPIO_FUNC_BT_HOST_WAKE1 = 18,\n\tHALMAC_GPIO_FUNC_BT_DEV_WAKE1 = 19,\n\tHALMAC_GPIO_FUNC_UNDEFINE = 0X7F,\n};\n\nenum halmac_wlled_mode {\n\tHALMAC_WLLED_MODE_TRX = 0,\n\tHALMAC_WLLED_MODE_TX = 1,\n\tHALMAC_WLLED_MODE_RX = 2,\n\tHALMAC_WLLED_MODE_SW_CTRL = 3,\n\tHALMAC_WLLED_MODE_UNDEFINE = 0X7F,\n};\n\nenum halmac_psf_fcs_chk_thr {\n\tHALMAC_PSF_FCS_CHK_THR_1 = 0,\n\tHALMAC_PSF_FCS_CHK_THR_4 = 1,\n\tHALMAC_PSF_FCS_CHK_THR_8 = 2,\n\tHALMAC_PSF_FCS_CHK_THR_12 = 3,\n\tHALMAC_PSF_FCS_CHK_THR_16 = 4,\n\tHALMAC_PSF_FCS_CHK_THR_20 = 5,\n\tHALMAC_PSF_FCS_CHK_THR_24 = 6,\n\tHALMAC_PSF_FCS_CHK_THR_28 = 7,\n};\n\nenum halmac_func_ctrl {\n\tHALMAC_DISABLE = 0,\n\tHALMAC_ENABLE = 1,\n\tHALMAC_DEFAULT = 0xFE,\n\tHALMAC_IGNORE = 0xFF\n};\n\nenum halmac_pcie_clkdly {\n\tHALMAC_CLKDLY_0 = 0,\n\tHALMAC_CLKDLY_5US = 1,\n\tHALMAC_CLKDLY_6US = 2,\n\tHALMAC_CLKDLY_11US = 3,\n\tHALMAC_CLKDLY_15US = 4,\n\tHALMAC_CLKDLY_19US = 5,\n\tHALMAC_CLKDLY_25US = 6,\n\tHALMAC_CLKDLY_30US = 7,\n\tHALMAC_CLKDLY_38US = 8,\n\tHALMAC_CLKDLY_50US = 9,\n\tHALMAC_CLKDLY_64US = 10,\n\tHALMAC_CLKDLY_100US = 11,\n\tHALMAC_CLKDLY_128US = 12,\n\tHALMAC_CLKDLY_150US = 13,\n\tHALMAC_CLKDLY_192US = 14,\n\tHALMAC_CLKDLY_200US = 15,\n\tHALMAC_CLKDLY_R_ERR = 0xFD,\n\tHALMAC_CLKDLY_DEF = 0xFE,\n\tHALMAC_CLKDLY_IGNORE = 0xFF\n};\n\nenum halmac_pcie_l1dly {\n\tHALMAC_L1DLY_16US = 0,\n\tHALMAC_L1DLY_32US = 1,\n\tHALMAC_L1DLY_64US = 2,\n\tHALMAC_L1DLY_INFI = 3,\n\tHALMAC_L1DLY_R_ERR = 0xFD,\n\tHALMAC_L1DLY_DEF = 0xFE,\n\tHALMAC_L1DLY_IGNORE = 0xFF\n};\n\nenum halmac_pcie_l0sdly {\n\tHALMAC_L0SDLY_1US = 0,\n\tHALMAC_L0SDLY_3US = 1,\n\tHALMAC_L0SDLY_5US = 2,\n\tHALMAC_L0SDLY_7US = 3,\n\tHALMAC_L0SDLY_R_ERR = 0xFD,\n\tHALMAC_L0SDLY_DEF = 0xFE,\n\tHALMAC_L0SDLY_IGNORE = 0xFF\n};\n\nstruct halmac_pcie_cfgspc_param {\n\tu8 write;\n\tu8 read;\n\tenum halmac_func_ctrl l0s_ctrl;\n\tenum halmac_func_ctrl l1_ctrl;\n\tenum halmac_func_ctrl l1ss_ctrl;\n\tenum halmac_func_ctrl wake_ctrl;\n\tenum halmac_func_ctrl crq_ctrl;\n\tenum halmac_pcie_clkdly clkdly_ctrl;\n\tenum halmac_pcie_l0sdly l0sdly_ctrl;\n\tenum halmac_pcie_l1dly l1dly_ctrl;\n};\n\nstruct halmac_txff_allocation {\n\tu16 tx_fifo_pg_num;\n\tu16 rsvd_pg_num;\n\tu16 rsvd_drv_pg_num;\n\tu16 acq_pg_num;\n\tu16 high_queue_pg_num;\n\tu16 low_queue_pg_num;\n\tu16 normal_queue_pg_num;\n\tu16 extra_queue_pg_num;\n\tu16 pub_queue_pg_num;\n\tu16 rsvd_boundary;\n\tu16 rsvd_drv_addr;\n\tu16 rsvd_h2c_info_addr;\n\tu16 rsvd_h2c_sta_info_addr;\n\tu16 rsvd_h2cq_addr;\n\tu16 rsvd_cpu_instr_addr;\n\tu16 rsvd_fw_txbuf_addr;\n\tu16 rsvd_csibuf_addr;\n\tenum halmac_la_mode la_mode;\n\tenum halmac_rx_fifo_expanding_mode rx_fifo_exp_mode;\n};\n\nstruct halmac_rqpn_map {\n\tenum halmac_dma_mapping dma_map_vo;\n\tenum halmac_dma_mapping dma_map_vi;\n\tenum halmac_dma_mapping dma_map_be;\n\tenum halmac_dma_mapping dma_map_bk;\n\tenum halmac_dma_mapping dma_map_mg;\n\tenum halmac_dma_mapping dma_map_hi;\n};\n\nstruct halmac_rqpn_ch_map {\n\tenum halmac_dma_ch dma_map_vo;\n\tenum halmac_dma_ch dma_map_vi;\n\tenum halmac_dma_ch dma_map_be;\n\tenum halmac_dma_ch dma_map_bk;\n\tenum halmac_dma_ch dma_map_mg;\n\tenum halmac_dma_ch dma_map_hi;\n};\n\nstruct halmac_security_setting {\n\tu8 tx_encryption;\n\tu8 rx_decryption;\n\tu8 bip_enable;\n\tu8 compare_keyid;\n};\n\nstruct halmac_cam_entry_info {\n\tenum hal_security_type security_type;\n\tu32 key[4];\n\tu32 key_ext[4];\n\tu8 mac_address[6];\n\tu8 unicast;\n\tu8 key_id;\n\tu8 valid;\n};\n\nstruct halmac_cam_entry_format {\n\tu16 key_id : 2;\n\tu16 type : 3;\n\tu16 mic : 1;\n\tu16 grp : 1;\n\tu16 spp_mode : 1;\n\tu16 rpt_md : 1;\n\tu16 ext_sectype : 1;\n\tu16 mgnt : 1;\n\tu16 rsvd1 : 4;\n\tu16 valid : 1;\n\tu8 mac_address[6];\n\tu32 key[4];\n\tu32 rsvd[2];\n};\n\nstruct halmac_tx_page_threshold_info {\n\tu32\tthreshold;\n\tenum halmac_dma_mapping dma_queue_sel;\n\tu8 enable;\n};\n\nstruct halmac_ampdu_config {\n\tu8 max_agg_num;\n\tu8 max_len_en;\n\tu32 ht_max_len;\n\tu32 vht_max_len;\n};\n\nstruct halmac_rqpn {\n\tenum halmac_trx_mode mode;\n\tenum halmac_dma_mapping dma_map_vo;\n\tenum halmac_dma_mapping dma_map_vi;\n\tenum halmac_dma_mapping dma_map_be;\n\tenum halmac_dma_mapping dma_map_bk;\n\tenum halmac_dma_mapping dma_map_mg;\n\tenum halmac_dma_mapping dma_map_hi;\n};\n\nstruct halmac_ch_mapping {\n\tenum halmac_trx_mode mode;\n\tenum halmac_dma_ch dma_map_vo;\n\tenum halmac_dma_ch dma_map_vi;\n\tenum halmac_dma_ch dma_map_be;\n\tenum halmac_dma_ch dma_map_bk;\n\tenum halmac_dma_ch dma_map_mg;\n\tenum halmac_dma_ch dma_map_hi;\n};\n\nstruct halmac_pg_num {\n\tenum halmac_trx_mode mode;\n\tu16 hq_num;\n\tu16 nq_num;\n\tu16 lq_num;\n\tu16 exq_num;\n\tu16 gap_num;/*used for loopback mode*/\n};\n\nstruct halmac_ch_pg_num {\n\tenum halmac_trx_mode mode;\n\tu16 ch_num[HALMAC_TXDESC_DMA_CH16 + 1];\n\tu16 gap_num;\n};\n\nstruct halmac_intf_phy_para {\n\tu16 offset;\n\tu16 value;\n\tu16 ip_sel;\n\tu16 cut;\n\tu16 plaform;\n};\n\nstruct halmac_iqk_para {\n\tu8 clear;\n\tu8 segment_iqk;\n};\n\nstruct halmac_txdesc_ie_param {\n\tu8 *start_offset;\n\tu8 *end_offset;\n\tu8 *ie_offset;\n\tu8 *ie_exist;\n};\n\nstruct halmac_sdio_hw_info {\n\tenum halmac_sdio_spec_ver spec_ver;\n\tu32 clock_speed;\n\tu8 io_hi_speed_flag; /* Halmac internal use */\n\tenum halmac_sdio_tx_format tx_addr_format;\n\tu16 block_size;\n\tu8 tx_seq;\n\tu8 io_indir_flag; /* Halmac internal use */\n};\n\nstruct halmac_edca_para {\n\tu8 aifs;\n\tu8 cw;\n\tu16 txop_limit;\n};\n\nstruct halmac_mac_rx_ignore_cfg {\n\tu8 hdr_chk_en;\n\tu8 fcs_chk_en;\n\tu8 cck_rst_en;\n\tenum halmac_psf_fcs_chk_thr fcs_chk_thr;\n};\n\nstruct halmac_rx_ignore_info {\n\tu8 hdr_chk_mask;\n\tu8 fcs_chk_mask;\n\tu8 hdr_chk_en;\n\tu8 fcs_chk_en;\n\tu8 cck_rst_en;\n\tenum halmac_psf_fcs_chk_thr fcs_chk_thr;\n};\n\nstruct halmac_pinmux_info {\n\t/* byte0 */\n\tu8 wl_led:1;\n\tu8 sdio_int:1;\n\tu8 bt_host_wake:1;\n\tu8 bt_dev_wake:1;\n\tu8 rsvd1:4;\n\t/* byte1 */\n\tu8 sw_io_0:1;\n\tu8 sw_io_1:1;\n\tu8 sw_io_2:1;\n\tu8 sw_io_3:1;\n\tu8 sw_io_4:1;\n\tu8 sw_io_5:1;\n\tu8 sw_io_6:1;\n\tu8 sw_io_7:1;\n\t/* byte2 */\n\tu8 sw_io_8:1;\n\tu8 sw_io_9:1;\n\tu8 sw_io_10:1;\n\tu8 sw_io_11:1;\n\tu8 sw_io_12:1;\n\tu8 sw_io_13:1;\n\tu8 sw_io_14:1;\n\tu8 sw_io_15:1;\n};\n\nstruct halmac_ofld_func_info {\n\tu32 halmac_malloc_max_sz;\n\tu32 rsvd_pg_drv_buf_max_sz;\n};\n\nstruct halmac_pltfm_cfg_info {\n\tu32 malloc_size;\n\tu32 rsvd_pg_size;\n};\n\nstruct halmac_su_snding_info {\n\tu8 su0_en;\n\tu8 *su0_ndpa_pkt;\n\tu32 su0_pkt_sz;\n};\n\nstruct halmac_mu_snding_info {\n\tu8 tmp;\n};\n\nstruct halmac_h2c_info {\n\tu32 buf_fs;\n\tu32 buf_size;\n\tu8 seq_num;\n};\n\nstruct halmac_adapter {\n\tenum halmac_dma_mapping pq_map[HALMAC_PQ_MAP_NUM];\n\tenum halmac_dma_ch ch_map[HALMAC_PQ_MAP_NUM];\n\tHALMAC_MUTEX h2c_seq_mutex; /* protect h2c seq num */\n\tHALMAC_MUTEX efuse_mutex; /*protect adapter efuse map */\n\tHALMAC_MUTEX sdio_indir_mutex; /*protect sdio indirect access */\n\tstruct halmac_cfg_param_info cfg_param_info;\n\tstruct halmac_ch_sw_info ch_sw_info;\n\tstruct halmac_event_trigger evnt;\n\tstruct halmac_hw_cfg_info hw_cfg_info;\n\tstruct halmac_sdio_free_space sdio_fs;\n\tstruct halmac_api_registry api_registry;\n\tstruct halmac_pinmux_info pinmux_info;\n\tstruct halmac_pltfm_cfg_info pltfm_info;\n\tstruct halmac_h2c_info h2c_info;\n\tvoid *drv_adapter;\n\tu8 *efuse_map;\n\tvoid *halmac_api;\n\tstruct halmac_platform_api *pltfm_api;\n\tu32 efuse_end;\n\tu32 dlfw_pkt_size;\n\tenum halmac_chip_id chip_id;\n\tenum halmac_chip_ver chip_ver;\n\tstruct halmac_fw_version fw_ver;\n\tstruct halmac_state halmac_state;\n\tenum halmac_interface intf;\n\tenum halmac_trx_mode trx_mode;\n\tstruct halmac_txff_allocation txff_alloc;\n\tu8 efuse_map_valid;\n\tu8 efuse_seg_size;\n\tu8 rpwm;\n\tu8 bulkout_num;\n\tu8 drv_info_size;\n\tenum halmac_sdio_cmd53_4byte_mode sdio_cmd53_4byte;\n\tstruct halmac_sdio_hw_info sdio_hw_info;\n\tu8 tx_desc_transfer;\n\tu8 tx_desc_checksum;\n\tu8 efuse_auto_check_en;\n\tu8 pcie_refautok_en;\n\tu8 pwr_off_flow_flag;\n\tu8 nlo_flag;\n\tstruct halmac_rx_ignore_info rx_ignore_info;\n#if HALMAC_PLATFORM_TESTPROGRAM\n\tstruct halmisc_adapter *halmisc_adapter;\n#endif\n};\n\nstruct halmac_api {\n\tenum halmac_ret_status\n\t(*halmac_register_api)(struct halmac_adapter *adapter,\n\t\t\t       struct halmac_api_registry *registry);\n\tenum halmac_ret_status\n\t(*halmac_mac_power_switch)(struct halmac_adapter *adapter,\n\t\t\t\t   enum halmac_mac_power pwr);\n\tenum halmac_ret_status\n\t(*halmac_download_firmware)(struct halmac_adapter *adapter, u8 *fw_bin,\n\t\t\t\t    u32 size);\n\tenum halmac_ret_status\n\t(*halmac_free_download_firmware)(struct halmac_adapter *adapter,\n\t\t\t\t\t enum halmac_dlfw_mem mem_sel,\n\t\t\t\t\t u8 *fw_bin, u32 size);\n\tenum halmac_ret_status\n\t(*halmac_reset_wifi_fw)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_get_fw_version)(struct halmac_adapter *adapter,\n\t\t\t\t struct halmac_fw_version *ver);\n\tenum halmac_ret_status\n\t(*halmac_cfg_mac_addr)(struct halmac_adapter *adapter,\n\t\t\t       u8 port, union halmac_wlan_addr *addr);\n\tenum halmac_ret_status\n\t(*halmac_cfg_bssid)(struct halmac_adapter *adapter, u8 port,\n\t\t\t    union halmac_wlan_addr *addr);\n\tenum halmac_ret_status\n\t(*halmac_cfg_multicast_addr)(struct halmac_adapter *adapter,\n\t\t\t\t     union halmac_wlan_addr *addr);\n\tenum halmac_ret_status\n\t(*halmac_pre_init_system_cfg)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_init_system_cfg)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_init_trx_cfg)(struct halmac_adapter *adapter,\n\t\t\t       enum halmac_trx_mode mode);\n\tenum halmac_ret_status\n\t(*halmac_init_h2c)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_cfg_rx_aggregation)(struct halmac_adapter *adapter,\n\t\t\t\t     struct halmac_rxagg_cfg *cfg);\n\tenum halmac_ret_status\n\t(*halmac_init_protocol_cfg)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_init_edca_cfg)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_cfg_operation_mode)(struct halmac_adapter *adapter,\n\t\t\t\t     enum halmac_wireless_mode mode);\n\tenum halmac_ret_status\n\t(*halmac_cfg_ch_bw)(struct halmac_adapter *adapter, u8 ch,\n\t\t\t    enum halmac_pri_ch_idx idx, enum halmac_bw bw);\n\tenum halmac_ret_status\n\t(*halmac_cfg_bw)(struct halmac_adapter *adapter, enum halmac_bw bw);\n\tenum halmac_ret_status\n\t(*halmac_init_wmac_cfg)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_init_mac_cfg)(struct halmac_adapter *adapter,\n\t\t\t       enum halmac_trx_mode mode);\n\tenum halmac_ret_status\n\t(*halmac_init_interface_cfg)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_deinit_interface_cfg)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_init_sdio_cfg)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_init_usb_cfg)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_init_pcie_cfg)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_deinit_sdio_cfg)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_deinit_usb_cfg)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_deinit_pcie_cfg)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_get_efuse_size)(struct halmac_adapter *adapter, u32 *size);\n\tenum halmac_ret_status\n\t(*halmac_get_efuse_available_size)(struct halmac_adapter *adapter,\n\t\t\t\t\t   u32 *size);\n\tenum halmac_ret_status\n\t(*halmac_dump_efuse_map)(struct halmac_adapter *adapter,\n\t\t\t\t enum halmac_efuse_read_cfg cfg);\n\tenum halmac_ret_status\n\t(*halmac_dump_efuse_map_bt)(struct halmac_adapter *adapter,\n\t\t\t\t    enum halmac_efuse_bank bank, u32 size,\n\t\t\t\t    u8 *map);\n\tenum halmac_ret_status\n\t(*halmac_write_efuse_bt)(struct halmac_adapter *adapter, u32 offset,\n\t\t\t\t u8 value, enum halmac_efuse_bank bank);\n\tenum halmac_ret_status\n\t(*halmac_read_efuse_bt)(struct halmac_adapter *adapter, u32 offset,\n\t\t\t\tu8 *value, enum halmac_efuse_bank bank);\n\tenum halmac_ret_status\n\t(*halmac_cfg_efuse_auto_check)(struct halmac_adapter *adapter,\n\t\t\t\t       u8 enable);\n\tenum halmac_ret_status\n\t(*halmac_get_logical_efuse_size)(struct halmac_adapter *adapter,\n\t\t\t\t\t u32 *size);\n\tenum halmac_ret_status\n\t(*halmac_dump_logical_efuse_map)(struct halmac_adapter *adapter,\n\t\t\t\t\t enum halmac_efuse_read_cfg cfg);\n\tenum halmac_ret_status\n\t(*halmac_write_logical_efuse)(struct halmac_adapter *adapter,\n\t\t\t\t      u32 offset, u8 value);\n\tenum halmac_ret_status\n\t(*halmac_read_logical_efuse)(struct halmac_adapter *adapter, u32 offset,\n\t\t\t\t     u8 *value);\n\tenum halmac_ret_status\n\t(*halmac_pg_efuse_by_map)(struct halmac_adapter *adapter,\n\t\t\t\t  struct halmac_pg_efuse_info *info,\n\t\t\t\t  enum halmac_efuse_read_cfg cfg);\n\tenum halmac_ret_status\n\t(*halmac_mask_logical_efuse)(struct halmac_adapter *adapter,\n\t\t\t\t     struct halmac_pg_efuse_info *info);\n\tenum halmac_ret_status\n\t(*halmac_get_c2h_info)(struct halmac_adapter *adapter, u8 *buf,\n\t\t\t       u32 size);\n\tenum halmac_ret_status\n\t(*halmac_h2c_lb)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_debug)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_cfg_parameter)(struct halmac_adapter *adapter,\n\t\t\t\tstruct halmac_phy_parameter_info *info,\n\t\t\t\tu8 full_fifo);\n\tenum halmac_ret_status\n\t(*halmac_update_packet)(struct halmac_adapter *adapter,\n\t\t\t\tenum halmac_packet_id pkt_id, u8 *pkt,\n\t\t\t\tu32 size);\n\tenum halmac_ret_status\n\t(*halmac_bcn_ie_filter)(struct halmac_adapter *adapter,\n\t\t\t\tstruct halmac_bcn_ie_info *info);\n\tu8\n\t(*halmac_reg_read_8)(struct halmac_adapter *adapter, u32 offset);\n\tenum halmac_ret_status\n\t(*halmac_reg_write_8)(struct halmac_adapter *adapter, u32 offset,\n\t\t\t      u8 value);\n\tu16\n\t(*halmac_reg_read_16)(struct halmac_adapter *adapter, u32 offset);\n\tenum halmac_ret_status\n\t(*halmac_reg_write_16)(struct halmac_adapter *adapter, u32 offset,\n\t\t\t       u16 value);\n\tu32\n\t(*halmac_reg_read_32)(struct halmac_adapter *adapter, u32 offset);\n\tenum halmac_ret_status\n\t(*halmac_reg_write_32)(struct halmac_adapter *adapter, u32 offset,\n\t\t\t       u32 value);\n\tu32\n\t(*halmac_reg_read_indirect_32)(struct halmac_adapter *adapter,\n\t\t\t\t       u32 offset);\n\tenum halmac_ret_status\n\t(*halmac_reg_sdio_cmd53_read_n)(struct halmac_adapter *adapter,\n\t\t\t\t\tu32 offset, u32 size, u8 *value);\n\tenum halmac_ret_status\n\t(*halmac_tx_allowed_sdio)(struct halmac_adapter *adapter, u8 *buf,\n\t\t\t\t  u32 size);\n\tenum halmac_ret_status\n\t(*halmac_set_bulkout_num)(struct halmac_adapter *adapter, u8 num);\n\tenum halmac_ret_status\n\t(*halmac_get_sdio_tx_addr)(struct halmac_adapter *adapter, u8 *buf,\n\t\t\t\t   u32 size, u32 *cmd53_addr);\n\tenum halmac_ret_status\n\t(*halmac_get_usb_bulkout_id)(struct halmac_adapter *adapter, u8 *buf,\n\t\t\t\t     u32 size, u8 *id);\n\tenum halmac_ret_status\n\t(*halmac_fill_txdesc_checksum)(struct halmac_adapter *adapter,\n\t\t\t\t       u8 *txdesc);\n\tenum halmac_ret_status\n\t(*halmac_update_datapack)(struct halmac_adapter *adapter,\n\t\t\t\t  enum halmac_data_type data_type,\n\t\t\t\t  struct halmac_phy_parameter_info *info);\n\tenum halmac_ret_status\n\t(*halmac_run_datapack)(struct halmac_adapter *adapter,\n\t\t\t       enum halmac_data_type data_type);\n\tenum halmac_ret_status\n\t(*halmac_cfg_drv_info)(struct halmac_adapter *adapter,\n\t\t\t       enum halmac_drv_info drv_info);\n\tenum halmac_ret_status\n\t(*halmac_send_bt_coex)(struct halmac_adapter *adapter, u8 *buf,\n\t\t\t       u32 size, u8 ack);\n\tenum halmac_ret_status\n\t(*halmac_verify_platform_api)(struct halmac_adapter *adapter);\n\tu32\n\t(*halmac_get_fifo_size)(struct halmac_adapter *adapter,\n\t\t\t\tenum hal_fifo_sel sel);\n\tenum halmac_ret_status\n\t(*halmac_dump_fifo)(struct halmac_adapter *adapter,\n\t\t\t    enum hal_fifo_sel sel, u32 start_addr, u32 size,\n\t\t\t    u8 *data);\n\tenum halmac_ret_status\n\t(*halmac_cfg_txbf)(struct halmac_adapter *adapter, u8 userid,\n\t\t\t   enum halmac_bw bw, u8 txbf_en);\n\tenum halmac_ret_status\n\t(*halmac_cfg_mumimo)(struct halmac_adapter *adapter,\n\t\t\t     struct halmac_cfg_mumimo_para *param);\n\tenum halmac_ret_status\n\t(*halmac_cfg_sounding)(struct halmac_adapter *adapter,\n\t\t\t       enum halmac_snd_role role,\n\t\t\t       enum halmac_data_rate rate);\n\tenum halmac_ret_status\n\t(*halmac_del_sounding)(struct halmac_adapter *adapter,\n\t\t\t       enum halmac_snd_role role);\n\tenum halmac_ret_status\n\t(*halmac_su_bfer_entry_init)(struct halmac_adapter *adapter,\n\t\t\t\t     struct halmac_su_bfer_init_para *param);\n\tenum halmac_ret_status\n\t(*halmac_su_bfee_entry_init)(struct halmac_adapter *adapter, u8 userid,\n\t\t\t\t     u16 paid);\n\tenum halmac_ret_status\n\t(*halmac_mu_bfer_entry_init)(struct halmac_adapter *adapter,\n\t\t\t\t     struct halmac_mu_bfer_init_para *param);\n\tenum halmac_ret_status\n\t(*halmac_mu_bfee_entry_init)(struct halmac_adapter *adapter,\n\t\t\t\t     struct halmac_mu_bfee_init_para *param);\n\tenum halmac_ret_status\n\t(*halmac_su_bfer_entry_del)(struct halmac_adapter *adapter, u8 userid);\n\tenum halmac_ret_status\n\t(*halmac_su_bfee_entry_del)(struct halmac_adapter *adapter, u8 userid);\n\tenum halmac_ret_status\n\t(*halmac_mu_bfer_entry_del)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_mu_bfee_entry_del)(struct halmac_adapter *adapter, u8 userid);\n\tenum halmac_ret_status\n\t(*halmac_add_ch_info)(struct halmac_adapter *adapter,\n\t\t\t      struct halmac_ch_info *info);\n\tenum halmac_ret_status\n\t(*halmac_add_extra_ch_info)(struct halmac_adapter *adapter,\n\t\t\t\t    struct halmac_ch_extra_info *info);\n\tenum halmac_ret_status\n\t(*halmac_ctrl_ch_switch)(struct halmac_adapter *adapter,\n\t\t\t\t struct halmac_ch_switch_option *opt);\n\tenum halmac_ret_status\n\t(*halmac_p2pps)(struct halmac_adapter *adapter,\n\t\t\tstruct halmac_p2pps *info);\n\tenum halmac_ret_status\n\t(*halmac_clear_ch_info)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_send_general_info)(struct halmac_adapter *adapter,\n\t\t\t\t    struct halmac_general_info *info);\n\tenum halmac_ret_status\n\t(*halmac_start_iqk)(struct halmac_adapter *adapter,\n\t\t\t    struct halmac_iqk_para *param);\n\tenum halmac_ret_status\n\t(*halmac_ctrl_pwr_tracking)(struct halmac_adapter *adapter,\n\t\t\t\t    struct halmac_pwr_tracking_option *opt);\n\tenum halmac_ret_status\n\t(*halmac_psd)(struct halmac_adapter *adapter, u16 start_psd,\n\t\t      u16 end_psd);\n\tenum halmac_ret_status\n\t(*halmac_cfg_tx_agg_align)(struct halmac_adapter *adapter, u8 enable,\n\t\t\t\t   u16 align_size);\n\tenum halmac_ret_status\n\t(*halmac_query_status)(struct halmac_adapter *adapter,\n\t\t\t       enum halmac_feature_id feature_id,\n\t\t\t       enum halmac_cmd_process_status *proc_status,\n\t\t\t       u8 *data, u32 *size);\n\tenum halmac_ret_status\n\t(*halmac_reset_feature)(struct halmac_adapter *adapter,\n\t\t\t\tenum halmac_feature_id feature_id);\n\tenum halmac_ret_status\n\t(*halmac_check_fw_status)(struct halmac_adapter *adapter,\n\t\t\t\t  u8 *fw_status);\n\tenum halmac_ret_status\n\t(*halmac_dump_fw_dmem)(struct halmac_adapter *adapter, u8 *dmem,\n\t\t\t       u32 *size);\n\tenum halmac_ret_status\n\t(*halmac_cfg_max_dl_size)(struct halmac_adapter *adapter, u32 size);\n\tenum halmac_ret_status\n\t(*halmac_cfg_la_mode)(struct halmac_adapter *adapter,\n\t\t\t      enum halmac_la_mode mode);\n\tenum halmac_ret_status\n\t(*halmac_cfg_rxff_expand_mode)(struct halmac_adapter *adapter,\n\t\t\t\t       enum halmac_rx_fifo_expanding_mode mode);\n\tenum halmac_ret_status\n\t(*halmac_config_security)(struct halmac_adapter *adapter,\n\t\t\t\t  struct halmac_security_setting *setting);\n\tu8\n\t(*halmac_get_used_cam_entry_num)(struct halmac_adapter *adapter,\n\t\t\t\t\t enum hal_security_type sec_type);\n\tenum halmac_ret_status\n\t(*halmac_write_cam)(struct halmac_adapter *adapter, u32 idx,\n\t\t\t    struct halmac_cam_entry_info *info);\n\tenum halmac_ret_status\n\t(*halmac_read_cam_entry)(struct halmac_adapter *adapter, u32 idx,\n\t\t\t\t struct halmac_cam_entry_format *content);\n\tenum halmac_ret_status\n\t(*halmac_clear_cam_entry)(struct halmac_adapter *adapter, u32 idx);\n\tenum halmac_ret_status\n\t(*halmac_get_hw_value)(struct halmac_adapter *adapter,\n\t\t\t       enum halmac_hw_id hw_id, void *value);\n\tenum halmac_ret_status\n\t(*halmac_set_hw_value)(struct halmac_adapter *adapter,\n\t\t\t       enum halmac_hw_id hw_id, void *value);\n\tenum halmac_ret_status\n\t(*halmac_cfg_drv_rsvd_pg_num)(struct halmac_adapter *adapter,\n\t\t\t\t      enum halmac_drv_rsvd_pg_num pg_num);\n\tenum halmac_ret_status\n\t(*halmac_get_chip_version)(struct halmac_adapter *adapter,\n\t\t\t\t   struct halmac_ver *ver);\n\tenum halmac_ret_status\n\t(*halmac_chk_txdesc)(struct halmac_adapter *adapter, u8 *buf, u32 size);\n\tenum halmac_ret_status\n\t(*halmac_dl_drv_rsvd_page)(struct halmac_adapter *adapter, u8 pg_offset,\n\t\t\t\t   u8 *buf, u32 size);\n\tenum halmac_ret_status\n\t(*halmac_pcie_switch)(struct halmac_adapter *adapter,\n\t\t\t      enum halmac_pcie_cfg cfg);\n\tenum halmac_ret_status\n\t(*halmac_phy_cfg)(struct halmac_adapter *adapter,\n\t\t\t  enum halmac_intf_phy_platform pltfm);\n\tenum halmac_ret_status\n\t(*halmac_cfg_csi_rate)(struct halmac_adapter *adapter, u8 rssi,\n\t\t\t       u8 cur_rate, u8 fixrate_en, u8 *new_rate,\n\t\t\t       u8 *bmp_ofdm54);\n#if HALMAC_SDIO_SUPPORT\n\tenum halmac_ret_status\n\t(*halmac_sdio_cmd53_4byte)(struct halmac_adapter *adapter,\n\t\t\t\t   enum halmac_sdio_cmd53_4byte_mode mode);\n\tenum halmac_ret_status\n\t(*halmac_sdio_hw_info)(struct halmac_adapter *adapter,\n\t\t\t       struct halmac_sdio_hw_info *info);\n#endif\n\tenum halmac_ret_status\n\t(*halmac_cfg_transmitter_addr)(struct halmac_adapter *adapter, u8 port,\n\t\t\t\t       union halmac_wlan_addr *addr);\n\tenum halmac_ret_status\n\t(*halmac_cfg_net_type)(struct halmac_adapter *adapter, u8 port,\n\t\t\t       enum halmac_network_type_select net_type);\n\tenum halmac_ret_status\n\t(*halmac_cfg_tsf_rst)(struct halmac_adapter *adapter, u8 port);\n\tenum halmac_ret_status\n\t(*halmac_cfg_bcn_space)(struct halmac_adapter *adapter, u8 port,\n\t\t\t\tu32 bcn_space);\n\tenum halmac_ret_status\n\t(*halmac_rw_bcn_ctrl)(struct halmac_adapter *adapter, u8 port,\n\t\t\t      u8 write_en, struct halmac_bcn_ctrl *ctrl);\n\tenum halmac_ret_status\n\t(*halmac_interface_integration_tuning)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_txfifo_is_empty)(struct halmac_adapter *adapter, u32 chk_num);\n\tenum halmac_ret_status\n\t(*halmac_download_flash)(struct halmac_adapter *adapter, u8 *fw_bin,\n\t\t\t\t u32 size, u32 rom_addr);\n\tenum halmac_ret_status\n\t(*halmac_read_flash)(struct halmac_adapter *adapter, u32 addr,\n\t\t\t     u32 length);\n\tenum halmac_ret_status\n\t(*halmac_erase_flash)(struct halmac_adapter *adapter, u8 erase_cmd,\n\t\t\t      u32 addr);\n\tenum halmac_ret_status\n\t(*halmac_check_flash)(struct halmac_adapter *adapter, u8 *fw_bin,\n\t\t\t      u32 size, u32 addr);\n\tenum halmac_ret_status\n\t(*halmac_cfg_edca_para)(struct halmac_adapter *adapter,\n\t\t\t\tenum halmac_acq_id acq_id,\n\t\t\t\tstruct halmac_edca_para *param);\n\tenum halmac_ret_status\n\t(*halmac_pinmux_get_func)(struct halmac_adapter *adapter,\n\t\t\t\t  enum halmac_gpio_func gpio_func, u8 *enable);\n\tenum halmac_ret_status\n\t(*halmac_pinmux_set_func)(struct halmac_adapter *adapter,\n\t\t\t\t  enum halmac_gpio_func gpio_func);\n\tenum halmac_ret_status\n\t(*halmac_pinmux_free_func)(struct halmac_adapter *adapter,\n\t\t\t\t   enum halmac_gpio_func gpio_func);\n\tenum halmac_ret_status\n\t(*halmac_pinmux_wl_led_mode)(struct halmac_adapter *adapter,\n\t\t\t\t     enum halmac_wlled_mode mode);\n\tvoid\n\t(*halmac_pinmux_wl_led_sw_ctrl)(struct halmac_adapter *adapter, u8 on);\n\tvoid\n\t(*halmac_pinmux_sdio_int_polarity)(struct halmac_adapter *adapter,\n\t\t\t\t\t   u8 low_active);\n\tenum halmac_ret_status\n\t(*halmac_pinmux_gpio_mode)(struct halmac_adapter *adapter, u8 gpio_id,\n\t\t\t\t   u8 output);\n\tenum halmac_ret_status\n\t(*halmac_pinmux_gpio_output)(struct halmac_adapter *adapter, u8 gpio_id,\n\t\t\t\t     u8 high);\n\tenum halmac_ret_status\n\t(*halmac_pinmux_pin_status)(struct halmac_adapter *adapter, u8 pin_id,\n\t\t\t\t    u8 *high);\n\tenum halmac_ret_status\n\t(*halmac_ofld_func_cfg)(struct halmac_adapter *adapter,\n\t\t\t\tstruct halmac_ofld_func_info *info);\n\tenum halmac_ret_status\n\t(*halmac_rx_cut_amsdu_cfg)(struct halmac_adapter *adapter,\n\t\t\t\t   struct halmac_cut_amsdu_cfg *cfg);\n\tenum halmac_ret_status\n\t(*halmac_fw_snding)(struct halmac_adapter *adapter,\n\t\t\t    struct halmac_su_snding_info *su_info,\n\t\t\t    struct halmac_mu_snding_info *mu_info, u8 period);\n\tenum halmac_ret_status\n\t(*halmac_get_mac_addr)(struct halmac_adapter *adapter, u8 port,\n\t\t\t       union halmac_wlan_addr *addr);\n\tenum halmac_ret_status\n\t(*halmac_init_low_pwr)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_enter_cpu_sleep_mode)(struct halmac_adapter *adapter);\n\tenum halmac_ret_status\n\t(*halmac_get_cpu_mode)(struct halmac_adapter *adapter,\n\t\t\t       enum halmac_wlcpu_mode *mode);\n\tenum halmac_ret_status\n\t(*halmac_drv_fwctrl)(struct halmac_adapter *adapter, u8 *payload,\n\t\t\t     u32 size, u8 ack);\n\tenum halmac_ret_status\n\t(*halmac_read_efuse)(struct halmac_adapter *adapter, u32 offset,\n\t\t\t     u8 *value);\n\tenum halmac_ret_status\n\t(*halmac_write_efuse)(struct halmac_adapter *adapter, u32 offset,\n\t\t\t      u8 value);\n#if HALMAC_PCIE_SUPPORT\n\tenum halmac_ret_status\n\t(*halmac_cfgspc_set_pcie)(struct halmac_adapter *adapter,\n\t\t\t\t  struct halmac_pcie_cfgspc_param *param);\n\tvoid\n\t(*halmac_en_ref_autok_pcie)(struct halmac_adapter *adapter, u8 en);\n#endif\n#if HALMAC_PLATFORM_TESTPROGRAM\n\tstruct halmisc_api *halmisc_api;\n#endif\n};\n\n#define HALMAC_GET_API(halmac_adapter)                                         \\\n\t((struct halmac_api *)halmac_adapter->halmac_api)\n\nstatic HALMAC_INLINE enum halmac_ret_status\nhalmac_fw_validate(struct halmac_adapter *adapter)\n{\n\tif (adapter->halmac_state.dlfw_state != HALMAC_DLFW_DONE &&\n\t    adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT)\n\t\treturn HALMAC_RET_NO_DLFW;\n\n\treturn HALMAC_RET_SUCCESS;\n}\n\n#endif\n"
  },
  {
    "path": "hal/halmac/halmac_usb_reg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n ******************************************************************************/\n\n#ifndef __HALMAC_USB_REG_H__\n#define __HALMAC_USB_REG_H__\n\n#endif/* __HALMAC_USB_REG_H__ */\n"
  },
  {
    "path": "hal/led/hal_led.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include <drv_types.h>\n#include <hal_data.h>\n\n#ifdef CONFIG_RTW_LED\nvoid dump_led_config(void *sel, _adapter *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct led_priv\t*ledpriv = adapter_to_led(adapter);\n\tint i;\n\n\tRTW_PRINT_SEL(sel, \"strategy:%u\\n\", ledpriv->LedStrategy);\n#ifdef CONFIG_RTW_SW_LED\n\tRTW_PRINT_SEL(sel, \"bRegUseLed:%u\\n\", ledpriv->bRegUseLed);\n\tRTW_PRINT_SEL(sel, \"iface_en_mask:0x%02X\\n\", ledpriv->iface_en_mask);\n\tfor (i = 0; i < dvobj->iface_nums; i++)\n\t\tRTW_PRINT_SEL(sel, \"ctl_en_mask[%d]:0x%08X\\n\", i, ledpriv->ctl_en_mask[i]);\n#endif\n}\n\nvoid rtw_led_set_strategy(_adapter *adapter, u8 strategy)\n{\n\tstruct led_priv *ledpriv = adapter_to_led(adapter);\n\t_adapter *pri_adapter = GET_PRIMARY_ADAPTER(adapter);\n\n#ifndef CONFIG_RTW_SW_LED\n\tif (IS_SW_LED_STRATEGY(strategy)) {\n\t\tRTW_WARN(\"CONFIG_RTW_SW_LED is not defined\\n\");\n\t\treturn;\n\t}\n#endif\n\n#ifdef CONFIG_RTW_SW_LED\n\tif (!ledpriv->bRegUseLed)\n\t\treturn;\n#endif\n\n\tif (ledpriv->LedStrategy == strategy)\n\t\treturn;\n\n\tif (IS_HW_LED_STRATEGY(strategy) || IS_HW_LED_STRATEGY(ledpriv->LedStrategy)) {\n\t\tRTW_WARN(\"switching on/off HW_LED strategy is not supported\\n\");\n\t\treturn;\n\t}\n\n\tledpriv->LedStrategy = strategy;\n\n#ifdef CONFIG_RTW_SW_LED\n\trtw_hal_sw_led_deinit(pri_adapter);\n#endif\n\n\trtw_led_control(pri_adapter, RTW_LED_OFF);\n}\n\n#ifdef CONFIG_RTW_SW_LED\n#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY\nvoid rtw_sw_led_blink_uc_trx_only(LED_DATA *led)\n{\n\t_adapter *adapter = led->padapter;\n\tBOOLEAN bStopBlinking = _FALSE;\n\n\tif (led->BlinkingLedState == RTW_LED_ON)\n\t\tSwLedOn(adapter, led);\n\telse\n\t\tSwLedOff(adapter, led);\n\n\tswitch (led->CurrLedState) {\n\tcase RTW_LED_ON:\n\t\tSwLedOn(adapter, led);\n\t\tbreak;\n\n\tcase RTW_LED_OFF:\n\t\tSwLedOff(adapter, led);\n\t\tbreak;\n\n\tcase LED_BLINK_TXRX:\n\t\tled->BlinkTimes--;\n\t\tif (led->BlinkTimes == 0)\n\t\t\tbStopBlinking = _TRUE;\n\n\t\tif (adapter_to_pwrctl(adapter)->rf_pwrstate != rf_on\n\t\t\t&& adapter_to_pwrctl(adapter)->rfoff_reason > RF_CHANGE_BY_PS\n\t\t) {\n\t\t\tSwLedOff(adapter, led);\n\t\t\tled->bLedBlinkInProgress = _FALSE;\n\t\t} else {\n\t\t\tif (led->bLedOn)\n\t\t\t\tled->BlinkingLedState = RTW_LED_OFF;\n\t\t\telse\n\t\t\t\tled->BlinkingLedState = RTW_LED_ON;\n\t\t\t\n\t\t\tif (bStopBlinking) {\n\t\t\t\tled->CurrLedState = RTW_LED_OFF;\n\t\t\t\tled->bLedBlinkInProgress = _FALSE;\n\t\t\t}\n\t\t\t_set_timer(&(led->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);\n\t\t}\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid rtw_sw_led_ctl_mode_uc_trx_only(_adapter *adapter, LED_CTL_MODE ctl)\n{\n\tstruct led_priv\t*ledpriv = adapter_to_led(adapter);\n\tLED_DATA *led = &(ledpriv->SwLed0);\n\tLED_DATA *led1 = &(ledpriv->SwLed1);\n\tLED_DATA *led2 = &(ledpriv->SwLed2);\n\n\tswitch (ctl) {\n\tcase LED_CTL_UC_TX:\n\tcase LED_CTL_UC_RX:\n\t\tif (led->bLedBlinkInProgress == _FALSE) {\n\t\t\tled->bLedBlinkInProgress = _TRUE;\n\t\t\tled->CurrLedState = LED_BLINK_TXRX;\n\t\t\tled->BlinkTimes = 2;\n\t\t\tif (led->bLedOn)\n\t\t\t\tled->BlinkingLedState = RTW_LED_OFF;\n\t\t\telse\n\t\t\t\tled->BlinkingLedState = RTW_LED_ON;\n\t\t\t_set_timer(&(led->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_POWER_OFF:\n\t\tled->CurrLedState = RTW_LED_OFF;\n\t\tled->BlinkingLedState = RTW_LED_OFF;\n\n\t\tif (led->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(led->BlinkTimer));\n\t\t\tled->bLedBlinkInProgress = _FALSE;\n\t\t}\n\n\t\tSwLedOff(adapter, led);\n\t\tSwLedOff(adapter, led1);\n\t\tSwLedOff(adapter, led2);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n}\n#endif /* CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY */\n\nvoid rtw_led_control(_adapter *adapter, LED_CTL_MODE ctl)\n{\n\tstruct led_priv\t*ledpriv = adapter_to_led(adapter);\n\n\tif (ledpriv->LedControlHandler) {\n\t\t#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY\n\t\tif (ledpriv->LedStrategy != SW_LED_MODE_UC_TRX_ONLY) {\n\t\t\tif (ctl == LED_CTL_UC_TX || ctl == LED_CTL_BMC_TX) {\n\t\t\t\tif (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(LED_CTL_TX))\n\t\t\t\t\tctl = LED_CTL_TX; /* transform specific TX ctl to general TX ctl */\n\t\t\t} else if (ctl == LED_CTL_UC_RX || ctl == LED_CTL_BMC_RX) {\n\t\t\t\tif (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(LED_CTL_RX))\n\t\t\t\t\tctl = LED_CTL_RX; /* transform specific RX ctl to general RX ctl */\n\t\t\t}\n\t\t}\n\t\t#endif\n\n\t\tif ((ledpriv->iface_en_mask & BIT(adapter->iface_id))\n\t\t\t&& (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(ctl)))\n\t\t\tledpriv->LedControlHandler(adapter, ctl);\n\t}\n}\n\nvoid rtw_led_tx_control(_adapter *adapter, const u8 *da)\n{\n#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY\n\tif (IS_MCAST(da))\n\t\trtw_led_control(adapter, LED_CTL_BMC_TX);\n\telse\n\t\trtw_led_control(adapter, LED_CTL_UC_TX);\n#else\n\trtw_led_control(adapter, LED_CTL_TX);\n#endif\n}\n\nvoid rtw_led_rx_control(_adapter *adapter, const u8 *da)\n{\n#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY\n\tif (IS_MCAST(da))\n\t\trtw_led_control(adapter, LED_CTL_BMC_RX);\n\telse\n\t\trtw_led_control(adapter, LED_CTL_UC_RX);\n#else\n\trtw_led_control(adapter, LED_CTL_RX);\n#endif\n}\n\nvoid rtw_led_set_iface_en(_adapter *adapter, u8 en)\n{\n\tstruct led_priv *ledpriv = adapter_to_led(adapter);\n\n\tif (en)\n\t\tledpriv->iface_en_mask |= BIT(adapter->iface_id);\n\telse\n\t\tledpriv->iface_en_mask &= ~BIT(adapter->iface_id);\n}\n\nvoid rtw_led_set_iface_en_mask(_adapter *adapter, u8 mask)\n{\n\tstruct led_priv *ledpriv = adapter_to_led(adapter);\n\n\tledpriv->iface_en_mask = mask;\n}\n\nvoid rtw_led_set_ctl_en_mask(_adapter *adapter, u32 ctl_mask)\n{\n\tstruct led_priv *ledpriv = adapter_to_led(adapter);\n\t\n#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY\n\tif (ctl_mask & BIT(LED_CTL_TX))\n\t\tctl_mask |= BIT(LED_CTL_UC_TX) | BIT(LED_CTL_BMC_TX);\n\tif (ctl_mask & BIT(LED_CTL_RX))\n\t\tctl_mask |= BIT(LED_CTL_UC_RX) | BIT(LED_CTL_BMC_RX);\n#endif\n\n\tledpriv->ctl_en_mask[adapter->iface_id] = ctl_mask;\n}\n\nvoid rtw_led_set_ctl_en_mask_primary(_adapter *adapter)\n{\n\trtw_led_set_ctl_en_mask(adapter, 0xFFFFFFFF);\n}\n\nvoid rtw_led_set_ctl_en_mask_virtual(_adapter *adapter)\n{\n\trtw_led_set_ctl_en_mask(adapter\n\t\t, BIT(LED_CTL_POWER_ON) | BIT(LED_CTL_POWER_OFF)\n\t\t| BIT(LED_CTL_TX) | BIT(LED_CTL_RX)\n\t);\n}\n#endif /* CONFIG_RTW_SW_LED */\n\n#endif /* CONFIG_RTW_LED */\n\n"
  },
  {
    "path": "hal/led/hal_pci_led.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include <drv_types.h>\n#include <hal_data.h>\n#ifdef CONFIG_RTW_SW_LED\n\n/*\n *\tDescription:\n *\t\tTurn on LED according to LedPin specified.\n *   */\nvoid\nHwLedBlink(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tPLED_PCIE\t\t\tpLed\n)\n{\n\n\n\tswitch (pLed->LedPin) {\n\tcase LED_PIN_GPIO0:\n\t\tbreak;\n\n\tcase LED_PIN_LED0:\n\t\t/* rtw_write8(Adapter, LED0Cfg, 0x2); */\n\t\tbreak;\n\n\tcase LED_PIN_LED1:\n\t\t/* rtw_write8(Adapter, LED1Cfg, 0x2); */\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\tpLed->bLedOn = _TRUE;\n}\n\n/*\n *\tDescription:\n *\t\tImplement LED blinking behavior for SW_LED_MODE0.\n *\t\tIt toggle off LED and schedule corresponding timer if necessary.\n *   */\nvoid\nSwLedBlink(\n\tPLED_PCIE\t\tpLed\n)\n{\n\tPADAPTER\t\tAdapter = pLed->padapter;\n\tstruct mlme_priv\t*pmlmepriv = &(Adapter->mlmepriv);\n\tBOOLEAN bStopBlinking = _FALSE;\n\n\t/* Change LED according to BlinkingLedState specified. */\n\tif (pLed->BlinkingLedState == RTW_LED_ON) {\n\t\tSwLedOn(Adapter, pLed);\n\t} else {\n\t\tSwLedOff(Adapter, pLed);\n\t}\n\n\t/* Determine if we shall change LED state again. */\n\tpLed->BlinkTimes--;\n\tswitch (pLed->CurrLedState) {\n\tcase LED_BLINK_NORMAL:\n\tcase LED_BLINK_TXRX:\n\tcase LED_BLINK_RUNTOP:\n\t\tif (pLed->BlinkTimes == 0)\n\t\t\tbStopBlinking = _TRUE;\n\t\tbreak;\n\n\tcase LED_BLINK_SCAN:\n\t\tif (((check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED)) ||\n\t\t     (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE))) &&     /* Linked. */\n\t\t    (!check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) && /* Not in scan stage. */\n\t\t    (pLed->BlinkTimes % 2 == 0)) /* Even */\n\t\t\tbStopBlinking = _TRUE;\n\t\tbreak;\n\n\tcase LED_BLINK_NO_LINK:\n\tcase LED_BLINK_StartToBlink:\n\t\tif (check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE))\n\t\t\tbStopBlinking = _TRUE;\n\t\telse if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) &&\n\t\t\t(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)))\n\t\t\tbStopBlinking = _TRUE;\n\t\telse if (pLed->BlinkTimes == 0)\n\t\t\tbStopBlinking = _TRUE;\n\t\tbreak;\n\n\tcase LED_BLINK_CAMEO:\n\t\tif (check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE))\n\t\t\tbStopBlinking = _TRUE;\n\t\telse if (check_fwstate(pmlmepriv, _FW_LINKED) &&\n\t\t\t(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)))\n\t\t\tbStopBlinking = _TRUE;\n\t\tbreak;\n\n\tdefault:\n\t\tbStopBlinking = _TRUE;\n\t\tbreak;\n\t}\n\n\tif (bStopBlinking) {\n\t\tif (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on)\n\t\t\tSwLedOff(Adapter, pLed);\n\t\telse if (pLed->CurrLedState == LED_BLINK_TXRX)\n\t\t\tSwLedOff(Adapter, pLed);\n\t\telse if (pLed->CurrLedState == LED_BLINK_RUNTOP)\n\t\t\tSwLedOff(Adapter, pLed);\n\t\telse if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) && pLed->bLedOn == _FALSE)\n\t\t\tSwLedOn(Adapter, pLed);\n\t\telse if ((check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) &&  pLed->bLedOn == _TRUE)\n\t\t\tSwLedOff(Adapter, pLed);\n\n\t\tpLed->BlinkTimes = 0;\n\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t} else {\n\t\t/* Assign LED state to toggle. */\n\t\tif (pLed->BlinkingLedState == RTW_LED_ON)\n\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\telse\n\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\n\t\t/* Schedule a timer to toggle LED state. */\n\t\tswitch (pLed->CurrLedState) {\n\t\tcase LED_BLINK_NORMAL:\n\t\tcase LED_BLINK_TXRX:\n\t\tcase LED_BLINK_StartToBlink:\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);\n\t\t\tbreak;\n\n\t\tcase LED_BLINK_SLOWLY:\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);\n\t\t\tbreak;\n\n\t\tcase LED_BLINK_SCAN:\n\t\tcase LED_BLINK_NO_LINK:\n\t\t\tif (pLed->bLedOn)\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);\n\t\t\telse\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_OFF_INTERVAL);\n\t\t\tbreak;\n\n\t\tcase LED_BLINK_RUNTOP:\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_RunTop_BLINK_INTERVAL);\n\t\t\tbreak;\n\n\t\tcase LED_BLINK_CAMEO:\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_PORNET);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\t/* RTW_INFO(\"SwLedCm2Blink(): unexpected state!\\n\"); */\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\nvoid\nSwLedBlink5(\n\tPLED_PCIE\t\tpLed\n)\n{\n\tPADAPTER\t\tAdapter = pLed->padapter;\n\tstruct mlme_priv\t*pmlmepriv = &(Adapter->mlmepriv);\n\tBOOLEAN bStopBlinking = _FALSE;\n\n\t/* Change LED according to BlinkingLedState specified. */\n\tif (pLed->BlinkingLedState == RTW_LED_ON) {\n\t\tSwLedOn(Adapter, pLed);\n\t} else {\n\t\tSwLedOff(Adapter, pLed);\n\t}\n\n\tswitch (pLed->CurrLedState) {\n\tcase RTW_LED_OFF:\n\t\tSwLedOff(Adapter, pLed);\n\t\tbreak;\n\n\tcase LED_BLINK_SLOWLY:\n\t\tif (pLed->bLedOn)\n\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\telse\n\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_NETTRONIX);\n\t\tbreak;\n\n\tcase LED_BLINK_NORMAL:\n\t\tpLed->BlinkTimes--;\n\t\tif (pLed->BlinkTimes == 0)\n\t\t\tbStopBlinking = _TRUE;\n\t\tif (bStopBlinking) {\n\t\t\tif (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on)\n\t\t\t\tSwLedOff(Adapter, pLed);\n\t\t\telse {\n\t\t\t\tpLed->bLedSlowBlinkInProgress = _TRUE;\n\t\t\t\tpLed->CurrLedState = LED_BLINK_SLOWLY;\n\t\t\t\tif (pLed->bLedOn)\n\t\t\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\t\telse\n\t\t\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_NETTRONIX);\n\t\t\t}\n\t\t\tpLed->BlinkTimes = 0;\n\t\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t\t} else {\n\t\t\tif (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on)\n\t\t\t\tSwLedOff(Adapter, pLed);\n\t\t\telse {\n\t\t\t\tif (pLed->bLedOn)\n\t\t\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\t\telse\n\t\t\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL_NETTRONIX);\n\t\t\t}\n\t\t}\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n}\n\n\nvoid\nSwLedBlink6(\n\tPLED_PCIE\t\tpLed\n)\n{\n\tPADAPTER\t\tAdapter = pLed->padapter;\n\tstruct mlme_priv\t*pmlmepriv = &(Adapter->mlmepriv);\n\tBOOLEAN bStopBlinking = _FALSE;\n\n\t/* Change LED according to BlinkingLedState specified. */\n\tif (pLed->BlinkingLedState == RTW_LED_ON) {\n\t\tSwLedOn(Adapter, pLed);\n\t} else {\n\t\tSwLedOff(Adapter, pLed);\n\t}\n\n\tswitch (pLed->CurrLedState) {\n\tcase RTW_LED_OFF:\n\t\tSwLedOff(Adapter, pLed);\n\t\tbreak;\n\n\tcase LED_BLINK_SLOWLY:\n\t\tif (pLed->bLedOn)\n\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\telse\n\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_PORNET);\n\t\tbreak;\n\n\tcase LED_BLINK_NORMAL:\n\t\tpLed->BlinkTimes--;\n\t\tif (pLed->BlinkTimes == 0)\n\t\t\tbStopBlinking = _TRUE;\n\t\tif (bStopBlinking) {\n\t\t\tif (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on)\n\t\t\t\tSwLedOff(Adapter, pLed);\n\t\t\telse {\n\t\t\t\tpLed->bLedSlowBlinkInProgress = _TRUE;\n\t\t\t\tpLed->CurrLedState = LED_BLINK_SLOWLY;\n\t\t\t\tif (pLed->bLedOn)\n\t\t\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\t\telse\n\t\t\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_PORNET);\n\t\t\t}\n\t\t\tpLed->BlinkTimes = 0;\n\t\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t\t} else {\n\t\t\tif (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on)\n\t\t\t\tSwLedOff(Adapter, pLed);\n\t\t\telse {\n\t\t\t\tif (pLed->bLedOn)\n\t\t\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\t\telse\n\t\t\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL_PORNET);\n\t\t\t}\n\t\t}\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n}\n\nvoid\nSwLedBlink7(\n\tPLED_PCIE\t\tpLed\n)\n{\n\tPADAPTER\t\tAdapter = pLed->padapter;\n\n\tSwLedOn(Adapter, pLed);\n}\n\n\n\n/*\n *\tDescription:\n *\t\tImplement LED blinking behavior for SW_LED_MODE8.\n *\t\tIt toggle off LED and schedule corresponding timer if necessary.\n *   */\nvoid\nSwLedBlink8(\n\tPLED_PCIE\t\tpLed\n)\n{\n\tPADAPTER\t\tAdapter = pLed->padapter;\n\tstruct mlme_priv\t*pmlmepriv = &(Adapter->mlmepriv);\n\tBOOLEAN bStopBlinking = _FALSE;\n\n\t/* Change LED according to BlinkingLedState specified. */\n\tif (pLed->BlinkingLedState == RTW_LED_ON) {\n\t\tSwLedOn(Adapter, pLed);\n\t} else {\n\t\tSwLedOff(Adapter, pLed);\n\t}\n\n\n\t/* Determine if we shall change LED state again. */\n\tif (pLed->CurrLedState != LED_BLINK_NO_LINK)\n\t\tpLed->BlinkTimes--;\n\n\tswitch (pLed->CurrLedState) {\n\tcase LED_BLINK_NORMAL:\n\tcase LED_BLINK_SCAN:\n\t\tif (pLed->BlinkTimes == 0)\n\t\t\tbStopBlinking = _TRUE;\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (bStopBlinking) {\n\t\tif (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) {\n\t\t\tpLed->CurrLedState = RTW_LED_OFF;\n\t\t\tSwLedOff(Adapter, pLed);\n\t\t} else {\n\t\t\tpLed->CurrLedState = RTW_LED_ON;\n\t\t\tSwLedOn(Adapter, pLed);\n\t\t}\n\n\t\tpLed->BlinkTimes = 0;\n\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t} else {\n\t\t/* Assign LED state to toggle. */\n\t\tif (pLed->BlinkingLedState == RTW_LED_ON)\n\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\telse\n\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\n\t\t/* Schedule a timer to toggle LED state. */\n\t\tswitch (pLed->CurrLedState) {\n\t\tcase LED_BLINK_NORMAL:\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\t/* RTW_INFO(\"SwLedCm8Blink(): unexpected state!\\n\"); */\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\nvoid\nSwLedBlink9(\n\tPLED_PCIE\t\tpLed\n)\n{\n\tPADAPTER\t\tAdapter = pLed->padapter;\n\tstruct mlme_priv\t*pmlmepriv = &(Adapter->mlmepriv);\n\tBOOLEAN bStopBlinking = _FALSE;\n\n\t/* Change LED according to BlinkingLedState specified. */\n\tif (pLed->BlinkingLedState == RTW_LED_ON) {\n\t\tSwLedOn(Adapter, pLed);\n\t} else {\n\t\tSwLedOff(Adapter, pLed);\n\t}\n\n\t/* Determine if we shall change LED state again. */\n\tif (pLed->CurrLedState != LED_BLINK_NO_LINK)\n\t\tpLed->BlinkTimes--;\n\n\tswitch (pLed->CurrLedState) {\n\tcase LED_BLINK_NORMAL:\n\tcase LED_BLINK_SCAN:\n\t\tif (pLed->BlinkTimes == 0)\n\t\t\tbStopBlinking = _TRUE;\n\t\tbreak;\n\n\tcase LED_BLINK_NO_LINK:\n\t\tif (check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE))\n\t\t\tbStopBlinking = _TRUE;\n\t\telse if (check_fwstate(pmlmepriv, _FW_LINKED) &&\n\t\t\t(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)))\n\t\t\tbStopBlinking = _TRUE;\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (bStopBlinking) {\n\t\tif (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) {\n\t\t\tpLed->CurrLedState = RTW_LED_OFF;\n\t\t\tSwLedOff(Adapter, pLed);\n\t\t} else if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {\n\t\t\tpLed->CurrLedState = RTW_LED_ON;\n\t\t\tSwLedOn(Adapter, pLed);\n\t\t} else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) {\n\t\t\tpLed->CurrLedState = LED_BLINK_NO_LINK;\n\t\t\tif (pLed->bLedOn)\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);\n\t\t\telse\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);\n\t\t}\n\n\t\tpLed->BlinkTimes = 0;\n\t\tif (pLed->CurrLedState != LED_BLINK_NO_LINK)\n\t\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t} else {\n\t\t/* Assign LED state to toggle. */\n\t\tif (pLed->BlinkingLedState == RTW_LED_ON)\n\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\telse\n\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\n\t\t/* Schedule a timer to toggle LED state. */\n\t\tswitch (pLed->CurrLedState) {\n\t\tcase LED_BLINK_NORMAL:\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_BLINK_FAST_INTERVAL_BITLAND);\n\t\t\tbreak;\n\n\t\tcase LED_BLINK_SCAN:\n\t\tcase LED_BLINK_NO_LINK:\n\t\t\tif (pLed->bLedOn)\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);\n\t\t\telse\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\t/* RTW_INFO(\"SwLedCm2Blink(): unexpected state!\\n\"); */\n\t\t\tbreak;\n\t\t}\n\t}\n\n\n}\n\n\nvoid\nSwLedBlink10(\n\tPLED_PCIE\t\tpLed\n)\n{\n\tPADAPTER\t\tAdapter = pLed->padapter;\n\tstruct mlme_priv\t*pmlmepriv = &(Adapter->mlmepriv);\n\tBOOLEAN bStopBlinking = _FALSE;\n\n\t/* Change LED according to BlinkingLedState specified. */\n\tif (pLed->BlinkingLedState == RTW_LED_ON) {\n\t\tSwLedOn(Adapter, pLed);\n\t} else {\n\t\tSwLedOff(Adapter, pLed);\n\t}\n\n\t/* Determine if we shall change LED state again. */\n\tif (pLed->CurrLedState != LED_BLINK_NO_LINK)\n\t\tpLed->BlinkTimes--;\n\n\tswitch (pLed->CurrLedState) {\n\tcase LED_BLINK_NORMAL:\n\tcase LED_BLINK_SCAN:\n\t\tif (pLed->BlinkTimes == 0)\n\t\t\tbStopBlinking = _TRUE;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (bStopBlinking) {\n\t\tpLed->CurrLedState = RTW_LED_OFF;\n\t\tSwLedOff(Adapter, pLed);\n\n\t\tpLed->BlinkTimes = 0;\n\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t} else {\n\t\t/* Assign LED state to toggle. */\n\t\tif (pLed->BlinkingLedState == RTW_LED_ON)\n\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\telse\n\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\n\t\t/* Schedule a timer to toggle LED state. */\n\t\tswitch (pLed->CurrLedState) {\n\t\tcase LED_BLINK_NORMAL:\n\t\tcase LED_BLINK_SCAN:\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_BLINK_FAST_INTERVAL_BITLAND);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\t/* RT_ASSERT(_FALSE, (\"SwLedCm2Blink(): unexpected state!\\n\")); */\n\t\t\tbreak;\n\t\t}\n\t}\n\n\n}\n\n\nvoid\nSwLedBlink11(\n\tPLED_PCIE\t\tpLed\n)\n{\n\tPADAPTER\t\tAdapter = pLed->padapter;\n\tBOOLEAN bStopBlinking = _FALSE;\n\n\t/* Change LED according to BlinkingLedState specified. */\n\tif (pLed->bLedBlinkInProgress == _TRUE) {\n\t\tif (pLed->BlinkingLedState == RTW_LED_ON) {\n\t\t\tSwLedOn(Adapter, pLed);\n\t\t} else {\n\t\t\tSwLedOff(Adapter, pLed);\n\t\t}\n\t}\n\n\t/* Determine if we shall change LED state again. */\n\tif (pLed->CurrLedState != LED_BLINK_NO_LINK)\n\t\tpLed->BlinkTimes--;\n\n\tswitch (pLed->CurrLedState) {\n\tcase RTW_LED_ON:\n\t\tbStopBlinking = _TRUE;\t/* LED on for 3 seconds */\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (bStopBlinking) {\n\t\tpLed->CurrLedState = RTW_LED_OFF;\n\t\tSwLedOff(Adapter, pLed);\n\n\t\tpLed->BlinkTimes = 0;\n\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t} else {\n\t\t/* Assign LED state to toggle. */\n\t\tif (pLed->BlinkingLedState == RTW_LED_ON)\n\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\telse\n\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\n\t\t/* Schedule a timer to toggle LED state. */\n\t\tswitch (pLed->CurrLedState) {\n\t\tcase LED_BLINK_XAVI:\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM11_BLINK_INTERVAL);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\t/* RT_ASSERT(_FALSE, (\"SwLedCm11Blink(): unexpected state!\\n\")); */\n\t\t\tbreak;\n\t\t}\n\t}\n\n\n}\n\n\nvoid\nSwLedBlink12(\n\tPLED_PCIE\t\tpLed\n)\n{\n\tPADAPTER\t\tAdapter = pLed->padapter;\n\tstruct mlme_priv\t*pmlmepriv = &(Adapter->mlmepriv);\n\tBOOLEAN bStopBlinking = _FALSE;\n\n\t/* Change LED according to BlinkingLedState specified. */\n\tif (pLed->BlinkingLedState == RTW_LED_ON) {\n\t\tSwLedOn(Adapter, pLed);\n\t} else {\n\t\tSwLedOff(Adapter, pLed);\n\t}\n\n\t/* Determine if we shall change LED state again. */\n\tif (pLed->CurrLedState != LED_BLINK_NO_LINK && pLed->CurrLedState != LED_BLINK_Azurewave_5Mbps\n\t    && pLed->CurrLedState != LED_BLINK_Azurewave_10Mbps && pLed->CurrLedState != LED_BLINK_Azurewave_20Mbps\n\t    && pLed->CurrLedState != LED_BLINK_Azurewave_40Mbps && pLed->CurrLedState != LED_BLINK_Azurewave_80Mbps\n\t    && pLed->CurrLedState != LED_BLINK_Azurewave_MAXMbps)\n\t\tpLed->BlinkTimes--;\n\n\tswitch (pLed->CurrLedState) {\n\tcase LED_BLINK_NORMAL:\n\tcase LED_BLINK_SCAN:\n\t\tif (pLed->BlinkTimes == 0)\n\t\t\tbStopBlinking = _TRUE;\n\t\tbreak;\n\n\tcase LED_BLINK_NO_LINK:\n\t\tif (check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE))\n\t\t\tbStopBlinking = _TRUE;\n\t\telse if (check_fwstate(pmlmepriv, _FW_LINKED) &&\n\t\t\t(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)))\n\t\t\tbStopBlinking = _TRUE;\n\t\tbreak;\n\n\tcase LED_BLINK_Azurewave_5Mbps:\n\tcase LED_BLINK_Azurewave_10Mbps:\n\tcase LED_BLINK_Azurewave_20Mbps:\n\tcase LED_BLINK_Azurewave_40Mbps:\n\tcase LED_BLINK_Azurewave_80Mbps:\n\tcase LED_BLINK_Azurewave_MAXMbps:\n\t/* if(pTurboCa->TxThroughput + pTurboCa->RxThroughput == 0) */\n\t/*\tbStopBlinking = _TRUE; */\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (bStopBlinking) {\n\t\tif (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) {\n\t\t\tpLed->CurrLedState = RTW_LED_OFF;\n\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\tSwLedOff(Adapter, pLed);\n\t\t} else if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {\n\t\t\tpLed->CurrLedState = RTW_LED_ON;\n\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t\tSwLedOn(Adapter, pLed);\n\t\t} else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) {\n\t\t\tpLed->CurrLedState = LED_BLINK_NO_LINK;\n\t\t\tif (pLed->bLedOn) {\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);\n\t\t\t} else {\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);\n\t\t\t}\n\t\t}\n\n\t\tpLed->BlinkTimes = 0;\n\t\tif (pLed->CurrLedState != LED_BLINK_NO_LINK)\n\t\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t} else {\n\t\t/* Assign LED state to toggle. */\n\t\tif (pLed->BlinkingLedState == RTW_LED_ON)\n\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\telse\n\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\n\t\t/* Schedule a timer to toggle LED state. */\n\t\tswitch (pLed->CurrLedState) {\n\t\tcase LED_BLINK_Azurewave_5Mbps:\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_5Mbps);\n\t\t\tbreak;\n\n\t\tcase LED_BLINK_Azurewave_10Mbps:\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_10Mbps);\n\t\t\tbreak;\n\n\t\tcase LED_BLINK_Azurewave_20Mbps:\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_20Mbps);\n\t\t\tbreak;\n\n\t\tcase LED_BLINK_Azurewave_40Mbps:\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_40Mbps);\n\t\t\tbreak;\n\n\t\tcase LED_BLINK_Azurewave_80Mbps:\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_80Mbps);\n\t\t\tbreak;\n\n\t\tcase LED_BLINK_Azurewave_MAXMbps:\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_MAXMbps);\n\t\t\tbreak;\n\n\t\tcase LED_BLINK_SCAN:\n\t\tcase LED_BLINK_NO_LINK:\n\t\t\tif (pLed->bLedOn)\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);\n\t\t\telse\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\t/* RT_ASSERT(_FALSE, (\"SwLedCm12Blink(): unexpected state!\\n\")); */\n\t\t\tbreak;\n\t\t}\n\t}\n\n\n}\n\n/*\n *\tDescription:\n *\t\tHandler function of LED Blinking.\n *\t\tWe dispatch acture LED blink action according to LedStrategy.\n *   */\nvoid BlinkHandler(PLED_PCIE pLed)\n{\n\t_adapter\t\t\t*padapter = pLed->padapter;\n\tstruct led_priv\t*ledpriv = adapter_to_led(padapter);\n\n\tif (RTW_CANNOT_RUN(padapter))\n\t\treturn;\n\n\tif (IS_HARDWARE_TYPE_8188E(padapter) ||\n\t    IS_HARDWARE_TYPE_JAGUAR(padapter) ||\n\t    IS_HARDWARE_TYPE_8723B(padapter) ||\n\t    IS_HARDWARE_TYPE_8192E(padapter))\n\t\treturn;\n\n\tswitch (ledpriv->LedStrategy) {\n\t#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY\n\tcase SW_LED_MODE_UC_TRX_ONLY:\n\t\trtw_sw_led_blink_uc_trx_only(pLed);\n\t\tbreak;\n\t#endif\n\n\tcase SW_LED_MODE1:\n\t\t/* SwLedBlink(pLed); */\n\t\tbreak;\n\tcase SW_LED_MODE2:\n\t\t/* SwLedBlink(pLed); */\n\t\tbreak;\n\tcase SW_LED_MODE3:\n\t\t/* SwLedBlink(pLed); */\n\t\tbreak;\n\tcase SW_LED_MODE5:\n\t\t/* SwLedBlink5(pLed); */\n\t\tbreak;\n\tcase SW_LED_MODE6:\n\t\t/* SwLedBlink6(pLed); */\n\t\tbreak;\n\tcase SW_LED_MODE7:\n\t\tSwLedBlink7(pLed);\n\t\tbreak;\n\tcase SW_LED_MODE8:\n\t\tSwLedBlink8(pLed);\n\t\tbreak;\n\n\tcase SW_LED_MODE9:\n\t\tSwLedBlink9(pLed);\n\t\tbreak;\n\n\tcase SW_LED_MODE10:\n\t\tSwLedBlink10(pLed);\n\t\tbreak;\n\n\tcase SW_LED_MODE11:\n\t\tSwLedBlink11(pLed);\n\t\tbreak;\n\n\tcase SW_LED_MODE12:\n\t\tSwLedBlink12(pLed);\n\t\tbreak;\n\n\tdefault:\n\t\t/* SwLedBlink(pLed); */\n\t\tbreak;\n\t}\n}\n\n/*\n *\tDescription:\n *\t\tCallback function of LED BlinkTimer,\n *\t\tit just schedules to corresponding BlinkWorkItem/led_blink_hdl\n *   */\nvoid BlinkTimerCallback(void *data)\n{\n\tPLED_PCIE\t pLed = (PLED_PCIE)data;\n\t_adapter\t\t*padapter = pLed->padapter;\n\n\t/* RTW_INFO(\"%s\\n\", __FUNCTION__); */\n\n\tif (RTW_CANNOT_RUN(padapter) || (!rtw_is_hw_init_completed(padapter))) {\n\t\t/*RTW_INFO(\"%s bDriverStopped:%s, bSurpriseRemoved:%s\\n\"\n\t\t\t, __func__\n\t\t\t, rtw_is_drv_stopped(padapter)?\"True\":\"False\"\n\t\t\t, rtw_is_surprise_removed(padapter)?\"True\":\"False\" );\n\t\t*/\n\t\treturn;\n\t}\n\n#ifdef CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD\n\trtw_led_blink_cmd(padapter, pLed);\n#else\n\tBlinkHandler(pLed);\n#endif\n}\n\n/*\n *\tDescription:\n *\t\tImplement each led action for SW_LED_MODE0. */\nvoid\nSwLedControlMode0(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tLED_CTL_MODE\t\tLedAction\n)\n{\n\tstruct led_priv\t*ledpriv = adapter_to_led(Adapter);\n\tPLED_PCIE pLed0 = &(ledpriv->SwLed0);\n\tPLED_PCIE pLed1 = &(ledpriv->SwLed1);\n\n\tswitch (LedAction) {\n\tcase LED_CTL_TX:\n\tcase LED_CTL_RX:\n\t\tbreak;\n\n\tcase LED_CTL_LINK:\n\t\tpLed0->CurrLedState = RTW_LED_ON;\n\t\tSwLedOn(Adapter, pLed0);\n\n\t\tpLed1->CurrLedState = LED_BLINK_NORMAL;\n\t\tHwLedBlink(Adapter, pLed1);\n\t\tbreak;\n\n\tcase LED_CTL_POWER_ON:\n\t\tpLed0->CurrLedState = RTW_LED_OFF;\n\t\tSwLedOff(Adapter, pLed0);\n\n\t\tpLed1->CurrLedState = LED_BLINK_NORMAL;\n\t\tHwLedBlink(Adapter, pLed1);\n\n\t\tbreak;\n\n\tcase LED_CTL_POWER_OFF:\n\t\tpLed0->CurrLedState = RTW_LED_OFF;\n\t\tSwLedOff(Adapter, pLed0);\n\n\t\tpLed1->CurrLedState = RTW_LED_OFF;\n\t\tSwLedOff(Adapter, pLed1);\n\t\tbreak;\n\n\tcase LED_CTL_SITE_SURVEY:\n\t\tbreak;\n\n\tcase LED_CTL_NO_LINK:\n\t\tpLed0->CurrLedState = RTW_LED_OFF;\n\t\tSwLedOff(Adapter, pLed0);\n\n\t\tpLed1->CurrLedState = LED_BLINK_NORMAL;\n\t\tHwLedBlink(Adapter, pLed1);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n}\n\n\nvoid\nSwLedControlMode1(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tLED_CTL_MODE\t\tLedAction\n)\n{\n\tstruct led_priv\t*ledpriv = adapter_to_led(Adapter);\n\tstruct mlme_priv\t*pmlmepriv = &(Adapter->mlmepriv);\n\tPLED_PCIE\tpLed = &(ledpriv->SwLed1);\n\n\t/* Decide led state */\n\tswitch (LedAction) {\n\tcase LED_CTL_TX:\n\tcase LED_CTL_RX:\n\t\tif (pLed->bLedBlinkInProgress == _FALSE) {\n\t\t\tpLed->bLedBlinkInProgress = _TRUE;\n\n\t\t\tpLed->CurrLedState = LED_BLINK_NORMAL;\n\t\t\tpLed->BlinkTimes = 2;\n\n\t\t\tif (pLed->bLedOn)\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\telse\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_SITE_SURVEY:\n\t\tif (pLed->bLedBlinkInProgress == _FALSE) {\n\t\t\tpLed->bLedBlinkInProgress = _TRUE;\n\n\t\t\tif ((check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE)) ||\n\t\t\t    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE))) {\n\t\t\t\tpLed->CurrLedState = LED_BLINK_SCAN;\n\t\t\t\tpLed->BlinkTimes = 4;\n\t\t\t} else {\n\t\t\t\tpLed->CurrLedState = LED_BLINK_NO_LINK;\n\t\t\t\tpLed->BlinkTimes = 24;\n\t\t\t}\n\n\t\t\tif (pLed->bLedOn) {\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);\n\t\t\t} else {\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_OFF_INTERVAL);\n\t\t\t}\n\t\t} else {\n\t\t\tif (pLed->CurrLedState != LED_BLINK_NO_LINK) {\n\t\t\t\tif ((check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE)) ||\n\t\t\t\t    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)))\n\t\t\t\t\tpLed->CurrLedState = LED_BLINK_SCAN;\n\t\t\t\telse\n\t\t\t\t\tpLed->CurrLedState = LED_BLINK_NO_LINK;\n\t\t\t}\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_NO_LINK:\n\t\tif (pLed->bLedBlinkInProgress == _FALSE) {\n\t\t\tpLed->bLedBlinkInProgress = _TRUE;\n\n\t\t\tpLed->CurrLedState = LED_BLINK_NO_LINK;\n\t\t\tpLed->BlinkTimes = 24;\n\n\t\t\tif (pLed->bLedOn) {\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);\n\t\t\t} else {\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_OFF_INTERVAL);\n\t\t\t}\n\t\t} else\n\t\t\tpLed->CurrLedState = LED_BLINK_NO_LINK;\n\t\tbreak;\n\n\tcase LED_CTL_LINK:\n\t\tpLed->CurrLedState = RTW_LED_ON;\n\t\tif (pLed->bLedBlinkInProgress == _FALSE)\n\t\t\tSwLedOn(Adapter, pLed);\n\t\tbreak;\n\n\tcase LED_CTL_POWER_OFF:\n\t\tpLed->CurrLedState = RTW_LED_OFF;\n\t\tif (pLed->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed->BlinkTimer));\n\t\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOff(Adapter, pLed);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n}\n\nvoid\nSwLedControlMode2(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tLED_CTL_MODE\t\tLedAction\n)\n{\n\tstruct led_priv\t*ledpriv = adapter_to_led(Adapter);\n\tstruct mlme_priv\t*pmlmepriv = &(Adapter->mlmepriv);\n\tPLED_PCIE pLed0 = &(ledpriv->SwLed0);\n\tPLED_PCIE pLed1 = &(ledpriv->SwLed1);\n\n\t/* Decide led state */\n\tswitch (LedAction) {\n\tcase LED_CTL_POWER_ON:\n\t\tpLed0->CurrLedState = RTW_LED_OFF;\n\t\tSwLedOff(Adapter, pLed0);\n\n\t\tpLed1->CurrLedState = LED_BLINK_CAMEO;\n\t\tif (pLed1->bLedBlinkInProgress == _FALSE) {\n\t\t\tpLed1->bLedBlinkInProgress = _TRUE;\n\n\t\t\tpLed1->BlinkTimes = 6;\n\n\t\t\tif (pLed1->bLedOn)\n\t\t\t\tpLed1->BlinkingLedState = RTW_LED_OFF;\n\t\t\telse\n\t\t\t\tpLed1->BlinkingLedState = RTW_LED_ON;\n\t\t\t_set_timer(&(pLed1->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_PORNET);\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_TX:\n\tcase LED_CTL_RX:\n\t\tif (pLed0->bLedBlinkInProgress == _FALSE) {\n\t\t\tpLed0->bLedBlinkInProgress = _TRUE;\n\n\t\t\tpLed0->CurrLedState = LED_BLINK_TXRX;\n\t\t\tpLed0->BlinkTimes = 2;\n\n\t\t\tif (pLed0->bLedOn)\n\t\t\t\tpLed0->BlinkingLedState = RTW_LED_OFF;\n\t\t\telse\n\t\t\t\tpLed0->BlinkingLedState = RTW_LED_ON;\n\n\t\t\t_set_timer(&(pLed0->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_NO_LINK:\n\t\tpLed1->CurrLedState = LED_BLINK_CAMEO;\n\t\tif (pLed1->bLedBlinkInProgress == _FALSE) {\n\t\t\tpLed1->bLedBlinkInProgress = _TRUE;\n\n\t\t\tpLed1->BlinkTimes = 6;\n\n\t\t\tif (pLed1->bLedOn)\n\t\t\t\tpLed1->BlinkingLedState = RTW_LED_OFF;\n\t\t\telse\n\t\t\t\tpLed1->BlinkingLedState = RTW_LED_ON;\n\t\t\t_set_timer(&(pLed1->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_PORNET);\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_LINK:\n\t\tpLed1->CurrLedState = RTW_LED_ON;\n\t\tif (pLed1->bLedBlinkInProgress == _FALSE)\n\t\t\tSwLedOn(Adapter, pLed1);\n\t\tbreak;\n\n\tcase LED_CTL_POWER_OFF:\n\t\tpLed0->CurrLedState = RTW_LED_OFF;\n\t\tpLed1->CurrLedState = RTW_LED_OFF;\n\t\tif (pLed0->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed0->BlinkTimer));\n\t\t\tpLed0->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tif (pLed1->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed1->BlinkTimer));\n\t\t\tpLed1->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOff(Adapter, pLed0);\n\t\tSwLedOff(Adapter, pLed1);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n}\n\n\n\nvoid\nSwLedControlMode3(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tLED_CTL_MODE\t\tLedAction\n)\n{\n\tstruct led_priv\t*ledpriv = adapter_to_led(Adapter);\n\tPLED_PCIE pLed0 = &(ledpriv->SwLed0);\n\tPLED_PCIE pLed1 = &(ledpriv->SwLed1);\n\n\t/* Decide led state */\n\tswitch (LedAction) {\n\tcase LED_CTL_POWER_ON:\n\t\tpLed0->CurrLedState = RTW_LED_ON;\n\t\tSwLedOn(Adapter, pLed0);\n\t\tpLed1->CurrLedState = RTW_LED_OFF;\n\t\tSwLedOff(Adapter, pLed1);\n\t\tbreak;\n\n\tcase LED_CTL_TX:\n\tcase LED_CTL_RX:\n\t\tif (pLed1->bLedBlinkInProgress == _FALSE) {\n\t\t\tpLed1->bLedBlinkInProgress = _TRUE;\n\n\t\t\tpLed1->CurrLedState = LED_BLINK_RUNTOP;\n\t\t\tpLed1->BlinkTimes = 2;\n\n\t\t\tif (pLed1->bLedOn)\n\t\t\t\tpLed1->BlinkingLedState = RTW_LED_OFF;\n\t\t\telse\n\t\t\t\tpLed1->BlinkingLedState = RTW_LED_ON;\n\n\t\t\t_set_timer(&(pLed1->BlinkTimer), LED_RunTop_BLINK_INTERVAL);\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_POWER_OFF:\n\t\tpLed0->CurrLedState = RTW_LED_OFF;\n\t\tpLed1->CurrLedState = RTW_LED_OFF;\n\t\tif (pLed0->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed0->BlinkTimer));\n\t\t\tpLed0->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tif (pLed1->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed1->BlinkTimer));\n\t\t\tpLed1->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOff(Adapter, pLed0);\n\t\tSwLedOff(Adapter, pLed1);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n}\n\n\nvoid\nSwLedControlMode4(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tLED_CTL_MODE\t\tLedAction\n)\n{\n\tstruct led_priv\t*ledpriv = adapter_to_led(Adapter);\n\tPLED_PCIE pLed0 = &(ledpriv->SwLed0);\n\tPLED_PCIE pLed1 = &(ledpriv->SwLed1);\n\n\t/* Decide led state */\n\tswitch (LedAction) {\n\tcase LED_CTL_POWER_ON:\n\t\tpLed1->CurrLedState = RTW_LED_ON;\n\t\tSwLedOn(Adapter, pLed1);\n\t\tpLed0->CurrLedState = RTW_LED_OFF;\n\t\tSwLedOff(Adapter, pLed0);\n\t\tbreak;\n\n\tcase LED_CTL_TX:\n\tcase LED_CTL_RX:\n\t\tif (pLed0->bLedBlinkInProgress == _FALSE) {\n\t\t\tpLed0->bLedBlinkInProgress = _TRUE;\n\n\t\t\tpLed0->CurrLedState = LED_BLINK_RUNTOP;\n\t\t\tpLed0->BlinkTimes = 2;\n\n\t\t\tif (pLed0->bLedOn)\n\t\t\t\tpLed0->BlinkingLedState = RTW_LED_OFF;\n\t\t\telse\n\t\t\t\tpLed0->BlinkingLedState = RTW_LED_ON;\n\n\t\t\t_set_timer(&(pLed0->BlinkTimer), LED_RunTop_BLINK_INTERVAL);\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_POWER_OFF:\n\t\tpLed0->CurrLedState = RTW_LED_OFF;\n\t\tpLed1->CurrLedState = RTW_LED_OFF;\n\t\tif (pLed0->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed0->BlinkTimer));\n\t\t\tpLed0->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tif (pLed1->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed1->BlinkTimer));\n\t\t\tpLed1->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOff(Adapter, pLed0);\n\t\tSwLedOff(Adapter, pLed1);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n}\n\n/* added by vivi, for led new mode */\nvoid\nSwLedControlMode5(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tLED_CTL_MODE\t\tLedAction\n)\n{\n\tstruct led_priv\t*ledpriv = adapter_to_led(Adapter);\n\tPLED_PCIE pLed0 = &(ledpriv->SwLed0);\n\tPLED_PCIE pLed1 = &(ledpriv->SwLed1);\n\t/* Decide led state */\n\tswitch (LedAction) {\n\tcase LED_CTL_POWER_ON:\n\tcase LED_CTL_START_TO_LINK:\n\tcase LED_CTL_NO_LINK:\n\t\tpLed1->CurrLedState = RTW_LED_OFF;\n\t\tSwLedOff(Adapter, pLed1);\n\n\n\t\tif (pLed0->bLedSlowBlinkInProgress == _FALSE) {\n\t\t\tpLed0->bLedSlowBlinkInProgress = _TRUE;\n\t\t\tpLed0->CurrLedState = LED_BLINK_SLOWLY;\n\t\t\tif (pLed0->bLedOn)\n\t\t\t\tpLed0->BlinkingLedState = RTW_LED_OFF;\n\t\t\telse\n\t\t\t\tpLed0->BlinkingLedState = RTW_LED_ON;\n\t\t\t_set_timer(&(pLed0->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_NETTRONIX);\n\t\t}\n\n\t\tbreak;\n\n\tcase LED_CTL_TX:\n\tcase LED_CTL_RX:\n\t\tpLed1->CurrLedState = RTW_LED_ON;\n\t\tSwLedOn(Adapter, pLed1);\n\n\t\tif (pLed0->bLedBlinkInProgress == _FALSE) {\n\t\t\t_cancel_timer_ex(&(pLed0->BlinkTimer));\n\t\t\tpLed0->bLedSlowBlinkInProgress = _FALSE;\n\t\t\tpLed0->bLedBlinkInProgress = _TRUE;\n\t\t\tpLed0->CurrLedState = LED_BLINK_NORMAL;\n\t\t\tpLed0->BlinkTimes = 2;\n\n\t\t\tif (pLed0->bLedOn)\n\t\t\t\tpLed0->BlinkingLedState = RTW_LED_OFF;\n\t\t\telse\n\t\t\t\tpLed0->BlinkingLedState = RTW_LED_ON;\n\t\t\t_set_timer(&(pLed0->BlinkTimer), LED_BLINK_NORMAL_INTERVAL_NETTRONIX);\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_LINK:\n\t\tpLed1->CurrLedState = RTW_LED_ON;\n\t\tSwLedOn(Adapter, pLed1);\n\n\t\tif (pLed0->bLedSlowBlinkInProgress == _FALSE) {\n\t\t\tpLed0->bLedSlowBlinkInProgress = _TRUE;\n\t\t\tpLed0->CurrLedState = LED_BLINK_SLOWLY;\n\t\t\tif (pLed0->bLedOn)\n\t\t\t\tpLed0->BlinkingLedState = RTW_LED_OFF;\n\t\t\telse\n\t\t\t\tpLed0->BlinkingLedState = RTW_LED_ON;\n\t\t\t_set_timer(&(pLed0->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_NETTRONIX);\n\t\t}\n\t\tbreak;\n\n\n\tcase LED_CTL_POWER_OFF:\n\t\tpLed0->CurrLedState = RTW_LED_OFF;\n\t\tpLed1->CurrLedState = RTW_LED_OFF;\n\t\tif (pLed0->bLedSlowBlinkInProgress == _TRUE) {\n\t\t\t_cancel_timer_ex(&(pLed0->BlinkTimer));\n\t\t\tpLed0->bLedSlowBlinkInProgress = _FALSE;\n\t\t}\n\t\tif (pLed0->bLedBlinkInProgress == _TRUE) {\n\t\t\t_cancel_timer_ex(&(pLed0->BlinkTimer));\n\t\t\tpLed0->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOff(Adapter, pLed0);\n\t\tSwLedOff(Adapter, pLed1);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\n}\n\n/* added by vivi, for led new mode */\nvoid\nSwLedControlMode6(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tLED_CTL_MODE\t\tLedAction\n)\n{\n\tstruct led_priv\t*ledpriv = adapter_to_led(Adapter);\n\tPLED_PCIE pLed0 = &(ledpriv->SwLed0);\n\tPLED_PCIE pLed1 = &(ledpriv->SwLed1);\n\n\n\tswitch (LedAction) {\n\tcase LED_CTL_POWER_ON:\n\tcase LED_CTL_START_TO_LINK:\n\tcase LED_CTL_NO_LINK:\n\tcase LED_CTL_LINK:\n\tcase LED_CTL_SITE_SURVEY:\n\t\tpLed1->CurrLedState = RTW_LED_OFF;\n\t\tSwLedOff(Adapter, pLed1);\n\n\t\tif (pLed0->bLedSlowBlinkInProgress == _FALSE) {\n\t\t\tpLed0->bLedSlowBlinkInProgress = _TRUE;\n\t\t\tpLed0->CurrLedState = LED_BLINK_SLOWLY;\n\t\t\tif (pLed0->bLedOn)\n\t\t\t\tpLed0->BlinkingLedState = RTW_LED_OFF;\n\t\t\telse\n\t\t\t\tpLed0->BlinkingLedState = RTW_LED_ON;\n\t\t\t_set_timer(&(pLed0->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_PORNET);\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_TX:\n\tcase LED_CTL_RX:\n\t\tpLed1->CurrLedState = RTW_LED_OFF;\n\t\tSwLedOff(Adapter, pLed1);\n\t\tif (pLed0->bLedBlinkInProgress == _FALSE) {\n\t\t\t_cancel_timer_ex(&(pLed0->BlinkTimer));\n\t\t\tpLed0->bLedSlowBlinkInProgress = _FALSE;\n\t\t\tpLed0->bLedBlinkInProgress = _TRUE;\n\t\t\tpLed0->CurrLedState = LED_BLINK_NORMAL;\n\t\t\tpLed0->BlinkTimes = 2;\n\t\t\tif (pLed0->bLedOn)\n\t\t\t\tpLed0->BlinkingLedState = RTW_LED_OFF;\n\t\t\telse\n\t\t\t\tpLed0->BlinkingLedState = RTW_LED_ON;\n\t\t\t_set_timer(&(pLed0->BlinkTimer), LED_BLINK_NORMAL_INTERVAL_PORNET);\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_POWER_OFF:\n\t\tpLed1->CurrLedState = RTW_LED_OFF;\n\t\tSwLedOff(Adapter, pLed1);\n\n\t\tpLed0->CurrLedState = RTW_LED_OFF;\n\t\tif (pLed0->bLedSlowBlinkInProgress == _TRUE) {\n\t\t\t_cancel_timer_ex(&(pLed0->BlinkTimer));\n\t\t\tpLed0->bLedSlowBlinkInProgress = _FALSE;\n\t\t}\n\t\tif (pLed0->bLedBlinkInProgress == _TRUE) {\n\t\t\t_cancel_timer_ex(&(pLed0->BlinkTimer));\n\t\t\tpLed0->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOff(Adapter, pLed0);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\n\t}\n}\n\n\n/* added by chiyokolin, for Lenovo */\nvoid\nSwLedControlMode7(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tLED_CTL_MODE\t\tLedAction\n)\n{\n\tstruct led_priv\t*ledpriv = adapter_to_led(Adapter);\n\tPLED_PCIE\tpLed0 = &(ledpriv->SwLed0);\n\n\tswitch (LedAction) {\n\tcase LED_CTL_POWER_ON:\n\tcase LED_CTL_LINK:\n\tcase LED_CTL_NO_LINK:\n\t\tSwLedOn(Adapter, pLed0);\n\t\tbreak;\n\n\tcase LED_CTL_POWER_OFF:\n\t\tSwLedOff(Adapter, pLed0);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n/* added by chiyokolin, for QMI */\nvoid\nSwLedControlMode8(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tLED_CTL_MODE\t\tLedAction\n)\n{\n\tstruct led_priv\t*ledpriv = adapter_to_led(Adapter);\n\tPLED_PCIE pLed = &(ledpriv->SwLed0);\n\tstruct mlme_priv\t*pmlmepriv = &(Adapter->mlmepriv);\n\n\t/* Decide led state */\n\tswitch (LedAction) {\n\tcase LED_CTL_TX:\n\tcase LED_CTL_RX:\n\t\tif (pLed->bLedBlinkInProgress == _FALSE && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {\n\t\t\tpLed->bLedBlinkInProgress = _TRUE;\n\n\t\t\tpLed->CurrLedState = LED_BLINK_NORMAL;\n\t\t\tpLed->BlinkTimes = 2;\n\n\t\t\tif (pLed->bLedOn)\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\telse\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_SITE_SURVEY:\n\tcase LED_CTL_POWER_ON:\n\tcase LED_CTL_NO_LINK:\n\tcase LED_CTL_LINK:\n\t\tpLed->CurrLedState = RTW_LED_ON;\n\t\tif (pLed->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed->BlinkTimer));\n\t\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOn(Adapter, pLed);\n\t\tbreak;\n\n\tcase LED_CTL_POWER_OFF:\n\t\tpLed->CurrLedState = RTW_LED_OFF;\n\t\tif (pLed->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed->BlinkTimer));\n\t\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOff(Adapter, pLed);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n/* added by chiyokolin, for MSI */\nvoid\nSwLedControlMode9(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tLED_CTL_MODE\t\tLedAction\n)\n{\n\tstruct led_priv\t*ledpriv = adapter_to_led(Adapter);\n\tPLED_PCIE pLed = &(ledpriv->SwLed0);\n\tstruct mlme_priv\t*pmlmepriv = &(Adapter->mlmepriv);\n\n\t/* Decide led state */\n\tswitch (LedAction) {\n\tcase LED_CTL_TX:\n\tcase LED_CTL_RX:\n\t\tif (pLed->bLedBlinkInProgress == _FALSE && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {\n\t\t\tpLed->bLedBlinkInProgress = _TRUE;\n\n\t\t\tpLed->CurrLedState = LED_BLINK_NORMAL;\n\t\t\tpLed->BlinkTimes = 2;\n\n\t\t\tif (pLed->bLedOn)\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\telse\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_BLINK_FAST_INTERVAL_BITLAND);\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_SITE_SURVEY:\n\t\tif (pLed->bLedBlinkInProgress == _FALSE) {\n\t\t\tpLed->bLedBlinkInProgress = _TRUE;\n\t\t\tpLed->CurrLedState = LED_BLINK_SCAN;\n\t\t\tpLed->BlinkTimes = 2;\n\n\t\t\tif (pLed->bLedOn) {\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);\n\t\t\t} else {\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);\n\t\t\t}\n\t\t} else if (pLed->CurrLedState != LED_BLINK_SCAN) {\n\t\t\t_cancel_timer_ex(&(pLed->BlinkTimer));\n\t\t\tpLed->CurrLedState = LED_BLINK_SCAN;\n\t\t\tpLed->BlinkTimes = 2;\n\n\t\t\tif (pLed->bLedOn) {\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);\n\t\t\t} else {\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);\n\t\t\t}\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_POWER_ON:\n\tcase LED_CTL_NO_LINK:\n\t\tif (pLed->bLedBlinkInProgress == _FALSE) {\n\t\t\tpLed->bLedBlinkInProgress = _TRUE;\n\n\t\t\tpLed->CurrLedState = LED_BLINK_NO_LINK;\n\t\t\tpLed->BlinkTimes = 24;\n\n\t\t\tif (pLed->bLedOn) {\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);\n\t\t\t} else {\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);\n\t\t\t}\n\t\t} else if (pLed->CurrLedState != LED_BLINK_SCAN && pLed->CurrLedState != LED_BLINK_NO_LINK) {\n\t\t\tpLed->CurrLedState = LED_BLINK_NO_LINK;\n\t\t\tpLed->BlinkTimes = 24;\n\n\t\t\tif (pLed->bLedOn) {\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);\n\t\t\t} else {\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);\n\t\t\t}\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_LINK:\n\t\tpLed->CurrLedState = RTW_LED_ON;\n\t\tif (pLed->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed->BlinkTimer));\n\t\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOn(Adapter, pLed);\n\t\tbreak;\n\n\tcase LED_CTL_POWER_OFF:\n\t\tpLed->CurrLedState = RTW_LED_OFF;\n\t\tif (pLed->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed->BlinkTimer));\n\t\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOff(Adapter, pLed);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\n}\n\n\n/* added by chiyokolin, for Edimax-ASUS */\nvoid\nSwLedControlMode10(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tLED_CTL_MODE\t\tLedAction\n)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(Adapter);\n\tstruct led_priv\t*ledpriv = adapter_to_led(Adapter);\n\tPLED_PCIE\tpLed0 = &(ledpriv->SwLed0);\n\tPLED_PCIE\tpLed1 = &(ledpriv->SwLed1);\n\tstruct mlme_priv\t*pmlmepriv = &(Adapter->mlmepriv);\n\n\t/* Decide led state */\n\tswitch (LedAction) {\n\tcase LED_CTL_TX:\n\tcase LED_CTL_RX:\n\t\tif (pLed1->bLedBlinkInProgress == _FALSE && pLed1->bLedWPSBlinkInProgress == _FALSE &&\n\t\t    (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {\n\t\t\tpLed1->bLedBlinkInProgress = _TRUE;\n\n\t\t\tpLed1->CurrLedState = LED_BLINK_NORMAL;\n\t\t\tpLed1->BlinkTimes = 2;\n\n\t\t\tif (pLed1->bLedOn)\n\t\t\t\tpLed1->BlinkingLedState = RTW_LED_OFF;\n\t\t\telse\n\t\t\t\tpLed1->BlinkingLedState = RTW_LED_ON;\n\t\t\t_set_timer(&(pLed1->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_SITE_SURVEY:\n\t\tif (pLed1->bLedBlinkInProgress == _FALSE && pLed1->bLedWPSBlinkInProgress == _FALSE) {\n\t\t\tpLed1->bLedBlinkInProgress = _TRUE;\n\t\t\tpLed1->CurrLedState = LED_BLINK_SCAN;\n\t\t\tpLed1->BlinkTimes = 12;\n\n\t\t\tif (pLed1->bLedOn) {\n\t\t\t\tpLed1->BlinkingLedState = RTW_LED_OFF;\n\t\t\t\t_set_timer(&(pLed1->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);\n\t\t\t} else {\n\t\t\t\tpLed1->BlinkingLedState = RTW_LED_ON;\n\t\t\t\t_set_timer(&(pLed1->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);\n\t\t\t}\n\t\t} else if (pLed1->CurrLedState != LED_BLINK_SCAN && pLed1->bLedWPSBlinkInProgress == _FALSE) {\n\t\t\t_cancel_timer_ex(&(pLed1->BlinkTimer));\n\t\t\tpLed1->CurrLedState = LED_BLINK_SCAN;\n\t\t\tpLed1->BlinkTimes = 24;\n\n\t\t\tif (pLed1->bLedOn) {\n\t\t\t\tpLed1->BlinkingLedState = RTW_LED_OFF;\n\t\t\t\t_set_timer(&(pLed1->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);\n\t\t\t} else {\n\t\t\t\tpLed1->BlinkingLedState = RTW_LED_ON;\n\t\t\t\t_set_timer(&(pLed1->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);\n\t\t\t}\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_START_WPS:\n\tcase LED_CTL_START_WPS_BOTTON:\n\t\tpLed1->CurrLedState = RTW_LED_ON;\n\t\tif (pLed1->bLedBlinkInProgress == _TRUE) {\n\t\t\t_cancel_timer_ex(&(pLed1->BlinkTimer));\n\t\t\tpLed1->bLedBlinkInProgress = _FALSE;\n\t\t}\n\n\t\tif (pLed1->bLedWPSBlinkInProgress == _FALSE) {\n\t\t\tpLed1->bLedWPSBlinkInProgress = _TRUE;\n\t\t\tSwLedOn(Adapter, pLed1);\n\t\t}\n\t\tbreak;\n\n\tcase\tLED_CTL_STOP_WPS:\n\tcase\tLED_CTL_STOP_WPS_FAIL:\n\tcase\tLED_CTL_STOP_WPS_FAIL_OVERLAP:\n\t\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {\n\t\t\tpLed0->CurrLedState = RTW_LED_ON;\n\t\t\tif (pLed0->bLedBlinkInProgress) {\n\t\t\t\t_cancel_timer_ex(&(pLed0->BlinkTimer));\n\t\t\t\tpLed0->bLedBlinkInProgress = _FALSE;\n\t\t\t}\n\t\t\tSwLedOn(Adapter, pLed0);\n\t\t} else {\n\t\t\tpLed0->CurrLedState = RTW_LED_OFF;\n\t\t\tif (pLed0->bLedBlinkInProgress) {\n\t\t\t\t_cancel_timer_ex(&(pLed0->BlinkTimer));\n\t\t\t\tpLed0->bLedBlinkInProgress = _FALSE;\n\t\t\t}\n\t\t\tSwLedOff(Adapter, pLed0);\n\t\t}\n\n\t\tpLed1->CurrLedState = RTW_LED_OFF;\n\t\tif (pLed1->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed1->BlinkTimer));\n\t\t\tpLed1->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOff(Adapter, pLed1);\n\n\t\tpLed1->bLedWPSBlinkInProgress = _FALSE;\n\n\t\tbreak;\n\n\tcase LED_CTL_LINK:\n\t\tpLed0->CurrLedState = RTW_LED_ON;\n\t\tif (pLed0->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed0->BlinkTimer));\n\t\t\tpLed0->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOn(Adapter, pLed0);\n\t\tbreak;\n\n\tcase LED_CTL_NO_LINK:\n\t\tif (pLed1->bLedWPSBlinkInProgress == _TRUE) {\n\t\t\tSwLedOn(Adapter, pLed1);\n\t\t\tbreak;\n\t\t}\n\n\t\tif (pLed1->CurrLedState == LED_BLINK_SCAN)\n\t\t\tbreak;\n\n\t\tpLed0->CurrLedState = RTW_LED_OFF;\n\t\tif (pLed0->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed0->BlinkTimer));\n\t\t\tpLed0->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOff(Adapter, pLed0);\n\n\t\tpLed1->CurrLedState = RTW_LED_OFF;\n\t\tif (pLed1->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed1->BlinkTimer));\n\t\t\tpLed1->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOff(Adapter, pLed1);\n\n\t\tbreak;\n\n\n\tcase LED_CTL_POWER_ON:\n\tcase LED_CTL_POWER_OFF:\n\t\tif (pLed1->bLedWPSBlinkInProgress == _TRUE) {\n\t\t\tSwLedOn(Adapter, pLed1);\n\t\t\tbreak;\n\t\t}\n\t\tpLed0->CurrLedState = RTW_LED_OFF;\n\t\tif (pLed0->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed0->BlinkTimer));\n\t\t\tpLed0->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOff(Adapter, pLed0);\n\n\t\tpLed1->CurrLedState = RTW_LED_OFF;\n\t\tif (pLed1->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed1->BlinkTimer));\n\t\t\tpLed1->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOff(Adapter, pLed1);\n\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\n\t}\n\n\n}\n\n\n/* added by hpfan, for Xavi */\nvoid\nSwLedControlMode11(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tLED_CTL_MODE\t\tLedAction\n)\n{\n\tstruct led_priv\t*ledpriv = adapter_to_led(Adapter);\n\tPLED_PCIE\tpLed = &(ledpriv->SwLed0);\n\n\t/* Decide led state */\n\tswitch (LedAction) {\n\tcase LED_CTL_START_WPS:\n\tcase LED_CTL_START_WPS_BOTTON:\n\t\tpLed->bLedWPSBlinkInProgress = _TRUE;\n\t\tif (pLed->bLedBlinkInProgress == _FALSE) {\n\t\t\tpLed->bLedBlinkInProgress = _TRUE;\n\t\t\tpLed->CurrLedState = LED_BLINK_XAVI;\n\n\t\t\tif (pLed->bLedOn) {\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM11_BLINK_INTERVAL);\n\t\t\t} else {\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM11_BLINK_INTERVAL);\n\t\t\t}\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_STOP_WPS:\n\tcase LED_CTL_STOP_WPS_FAIL:\n\tcase LED_CTL_STOP_WPS_FAIL_OVERLAP:\n\t\tpLed->bLedWPSBlinkInProgress = _FALSE;\n\t\tif (pLed->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed->BlinkTimer));\n\t\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t\t\tpLed->CurrLedState = RTW_LED_OFF;\n\t\t}\n\t\tSwLedOff(Adapter, pLed);\n\t\tbreak;\n\n\tcase LED_CTL_LINK:\n\t\tif (pLed->bLedWPSBlinkInProgress)\n\t\t\tbreak;\n\n\t\tif (pLed->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed->BlinkTimer));\n\t\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t\t\tpLed->CurrLedState = RTW_LED_ON;\n\n\t\t\tif (!pLed->bLedOn)\n\t\t\t\tSwLedOn(Adapter, pLed);\n\t\t} else {\n\t\t\tpLed->CurrLedState = RTW_LED_ON;\n\t\t\tSwLedOn(Adapter, pLed);\n\t\t}\n\n\t\t_set_timer(&(pLed->BlinkTimer), LED_CM11_LINK_ON_INTERVEL);\n\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\tbreak;\n\n\tcase LED_CTL_NO_LINK:\n\t\tif (pLed->bLedWPSBlinkInProgress)\n\t\t\tbreak;\n\n\t\tif (pLed->bLedBlinkInProgress == _TRUE) {\n\t\t\t_cancel_timer_ex(&(pLed->BlinkTimer));\n\t\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tpLed->CurrLedState = RTW_LED_OFF;\n\t\tSwLedOff(Adapter, pLed);\n\t\tbreak;\n\n\tcase LED_CTL_POWER_ON:\n\tcase LED_CTL_POWER_OFF:\n\t\tif (pLed->bLedBlinkInProgress == _TRUE) {\n\t\t\t_cancel_timer_ex(&(pLed->BlinkTimer));\n\t\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t\t}\n\n\t\tpLed->CurrLedState = RTW_LED_OFF;\n\t\tSwLedOff(Adapter, pLed);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\n\t}\n\n\n}\n\n/* added by chiyokolin, for Azurewave */\nvoid\nSwLedControlMode12(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tLED_CTL_MODE\t\tLedAction\n)\n{\n\tstruct led_priv\t*ledpriv = adapter_to_led(Adapter);\n\tPLED_PCIE\tpLed = &(ledpriv->SwLed0);\n\tstruct mlme_priv\t*pmlmepriv = &(Adapter->mlmepriv);\n\tLED_STATE\tLedState = LED_UNKNOWN;\n\n\n\t/* Decide led state */\n\tswitch (LedAction) {\n\tcase LED_CTL_TX:\n\tcase LED_CTL_RX:\n\t\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {\n\t\t\tif (pLed->CurrLedState == LED_BLINK_SCAN)\n\t\t\t\tbreak;\n\n\t\t\tpLed->BlinkTimes = 0;\n\n\t\t\tif (pLed->bLedOn)\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\telse\n\t\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\n\t\t\t/*if(pTurboCa->TotalThroughput <= 5)\n\t\t\t\tLedState = LED_BLINK_Azurewave_5Mbps;\n\t\t\telse if(pTurboCa->TotalThroughput <= 10)\n\t\t\t\tLedState = LED_BLINK_Azurewave_10Mbps;\n\t\t\telse if(pTurboCa->TotalThroughput <=20)\n\t\t\t\tLedState = LED_BLINK_Azurewave_20Mbps;\n\t\t\telse if(pTurboCa->TotalThroughput <=40)\n\t\t\t\tLedState = LED_BLINK_Azurewave_40Mbps;\n\t\t\telse if(pTurboCa->TotalThroughput <=80)\n\t\t\t\tLedState = LED_BLINK_Azurewave_80Mbps;\n\t\t\telse*/\n\t\t\tLedState = LED_BLINK_Azurewave_MAXMbps;\n\n\t\t\tif (pLed->bLedBlinkInProgress == _FALSE || pLed->CurrLedState != LedState) {\n\t\t\t\t_cancel_timer_ex(&(pLed->BlinkTimer));\n\t\t\t\tpLed->CurrLedState = LedState;\n\t\t\t\tpLed->bLedBlinkInProgress = _TRUE;\n\n\t\t\t\tswitch (LedState) {\n\t\t\t\tcase LED_BLINK_Azurewave_5Mbps:\n\t\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_5Mbps);\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase LED_BLINK_Azurewave_10Mbps:\n\t\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_10Mbps);\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase LED_BLINK_Azurewave_20Mbps:\n\t\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_20Mbps);\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase LED_BLINK_Azurewave_40Mbps:\n\t\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_40Mbps);\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase LED_BLINK_Azurewave_80Mbps:\n\t\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_80Mbps);\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase LED_BLINK_Azurewave_MAXMbps:\n\t\t\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_MAXMbps);\n\t\t\t\t\tbreak;\n\n\t\t\t\tdefault:\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tbreak;\n\n\tcase LED_CTL_SITE_SURVEY:\n\tcase LED_CTL_START_WPS:\n\tcase LED_CTL_START_WPS_BOTTON:\n\t\tif (pLed->bLedBlinkInProgress == _FALSE)\n\t\t\tpLed->bLedBlinkInProgress = _TRUE;\n\t\telse if (pLed->CurrLedState != LED_BLINK_SCAN)\n\t\t\t_cancel_timer_ex(&(pLed->BlinkTimer));\n\n\t\tpLed->CurrLedState = LED_BLINK_SCAN;\n\t\tpLed->BlinkTimes = 2;\n\n\t\tif (pLed->bLedOn) {\n\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);\n\t\t} else {\n\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_LINK:\n\t\tpLed->CurrLedState = RTW_LED_ON;\n\t\tif (pLed->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed->BlinkTimer));\n\t\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOn(Adapter, pLed);\n\t\tbreak;\n\n\tcase LED_CTL_NO_LINK:\n\tcase LED_CTL_POWER_ON:\n\t\tif (pLed->CurrLedState == LED_BLINK_SCAN)\n\t\t\tbreak;\n\n\t\tpLed->CurrLedState = LED_BLINK_NO_LINK;\n\t\tpLed->bLedBlinkInProgress = _TRUE;\n\n\t\tif (pLed->bLedOn) {\n\t\t\tpLed->BlinkingLedState = RTW_LED_OFF;\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);\n\t\t} else {\n\t\t\tpLed->BlinkingLedState = RTW_LED_ON;\n\t\t\t_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);\n\t\t}\n\t\tbreak;\n\n\tcase LED_CTL_POWER_OFF:\n\t\tpLed->CurrLedState = RTW_LED_OFF;\n\t\tif (pLed->bLedBlinkInProgress) {\n\t\t\t_cancel_timer_ex(&(pLed->BlinkTimer));\n\t\t\tpLed->bLedBlinkInProgress = _FALSE;\n\t\t}\n\t\tSwLedOff(Adapter, pLed);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\n\t}\n\n\n}\n\nvoid\nLedControlPCIE(\n\t_adapter\t\t\t\t*padapter,\n\tLED_CTL_MODE\t\tLedAction\n)\n{\n\tstruct led_priv\t*ledpriv = adapter_to_led(padapter);\n\n#if (MP_DRIVER == 1)\n\tif (padapter->registrypriv.mp_mode == 1)\n\t\treturn;\n#endif\n\n\tif (RTW_CANNOT_RUN(padapter) || (!rtw_is_hw_init_completed(padapter)))\n\t\treturn;\n\n\t/* if(priv->bInHctTest) */\n\t/*\treturn; */\n\n\tif ((adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) &&\n\t    (LedAction == LED_CTL_TX ||\n\t     LedAction == LED_CTL_RX ||\n\t     LedAction == LED_CTL_SITE_SURVEY ||\n\t     LedAction == LED_CTL_LINK ||\n\t     LedAction == LED_CTL_NO_LINK ||\n\t     LedAction == LED_CTL_START_TO_LINK ||\n\t     LedAction == LED_CTL_POWER_ON)) {\n\t\treturn;\n\t}\n\n\tswitch (ledpriv->LedStrategy) {\n\t#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY\n\tcase SW_LED_MODE_UC_TRX_ONLY:\n\t\trtw_sw_led_ctl_mode_uc_trx_only(padapter, LedAction);\n\t\tbreak;\n\t#endif\n\n\tcase SW_LED_MODE0:\n\t\t/* SwLedControlMode0(padapter, LedAction); */\n\t\tbreak;\n\n\tcase SW_LED_MODE1:\n\t\t/* SwLedControlMode1(padapter, LedAction); */\n\t\tbreak;\n\n\tcase SW_LED_MODE2:\n\t\t/* SwLedControlMode2(padapter, LedAction); */\n\t\tbreak;\n\n\tcase SW_LED_MODE3:\n\t\t/* SwLedControlMode3(padapter, LedAction); */\n\t\tbreak;\n\n\tcase SW_LED_MODE4:\n\t\t/* SwLedControlMode4(padapter, LedAction); */\n\t\tbreak;\n\n\tcase SW_LED_MODE5:\n\t\t/* SwLedControlMode5(padapter, LedAction); */\n\t\tbreak;\n\n\tcase SW_LED_MODE6:\n\t\t/* SwLedControlMode6(padapter, LedAction); */\n\t\tbreak;\n\n\tcase SW_LED_MODE7:\n\t\tSwLedControlMode7(padapter, LedAction);\n\t\tbreak;\n\n\tcase SW_LED_MODE8:\n\t\tSwLedControlMode8(padapter, LedAction);\n\t\tbreak;\n\n\tcase SW_LED_MODE9:\n\t\tSwLedControlMode9(padapter, LedAction);\n\t\tbreak;\n\n\tcase SW_LED_MODE10:\n\t\tSwLedControlMode10(padapter, LedAction);\n\t\tbreak;\n\n\tcase SW_LED_MODE11:\n\t\tSwLedControlMode11(padapter, LedAction);\n\t\tbreak;\n\n\tcase SW_LED_MODE12:\n\t\tSwLedControlMode12(padapter, LedAction);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n/*-----------------------------------------------------------------------------\n * Function:\tgen_RefreshLedState()\n *\n * Overview:\tWhen we call the function, media status is no link. It must be in SW/HW\n *\t\t\tradio off. Or IPS state. If IPS no link we will turn on LED, otherwise, we must turn off.\n *\t\t\tAfter MAC IO reset, we must write LED control 0x2f2 again.\n *\n * Input:\t\t\tPADAPTER\t\t\tAdapter)\n *\n * Output:\t\tNONE\n *\n * Return:\t\tNONE\n *\n * Revised History:\n *\tWhen\t\tWho\t\tRemark\n *\t03/27/2009\tMHC\t\tCreate for LED judge only~!!\n *\n *---------------------------------------------------------------------------*/\nvoid\ngen_RefreshLedState(\n\t\tPADAPTER\t\t\tAdapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(Adapter);\n\tstruct pwrctrl_priv\t*pwrctrlpriv = adapter_to_pwrctl(Adapter);\n\tstruct led_priv\t*pledpriv = adapter_to_led(Adapter);\n\tPLED_PCIE\t\tpLed0 = &(pledpriv->SwLed0);\n\n\tRTW_INFO(\"gen_RefreshLedState:() pwrctrlpriv->rfoff_reason=%x\\n\", pwrctrlpriv->rfoff_reason);\n\n\tif (Adapter->bDriverIsGoingToUnload) {\n\t\tswitch (pledpriv->LedStrategy) {\n\t\tcase SW_LED_MODE9:\n\t\tcase SW_LED_MODE10:\n\t\t\trtw_led_control(Adapter, LED_CTL_POWER_OFF);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\t/* Turn off LED if RF is not ON. */\n\t\t\tSwLedOff(Adapter, pLed0);\n\t\t\tbreak;\n\t\t}\n\t} else if (pwrctrlpriv->rfoff_reason == RF_CHANGE_BY_IPS) {\n\t\tswitch (pledpriv->LedStrategy) {\n\t\tcase SW_LED_MODE7:\n\t\t\tSwLedOn(Adapter, pLed0);\n\t\t\tbreak;\n\n\t\tcase SW_LED_MODE8:\n\t\tcase SW_LED_MODE9:\n\t\t\trtw_led_control(Adapter, LED_CTL_NO_LINK);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tSwLedOn(Adapter, pLed0);\n\t\t\tbreak;\n\t\t}\n\t} else if (pwrctrlpriv->rfoff_reason == RF_CHANGE_BY_INIT) {\n\t\tswitch (pledpriv->LedStrategy) {\n\t\tcase SW_LED_MODE7:\n\t\t\tSwLedOn(Adapter, pLed0);\n\t\t\tbreak;\n\n\t\tcase SW_LED_MODE9:\n\t\t\trtw_led_control(Adapter, LED_CTL_NO_LINK);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tSwLedOn(Adapter, pLed0);\n\t\t\tbreak;\n\n\t\t}\n\t} else {\t/* SW/HW radio off */\n\n\t\tswitch (pledpriv->LedStrategy) {\n\t\tcase SW_LED_MODE9:\n\t\t\trtw_led_control(Adapter, LED_CTL_POWER_OFF);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\t/* Turn off LED if RF is not ON. */\n\t\t\tSwLedOff(Adapter, pLed0);\n\t\t\tbreak;\n\t\t}\n\t}\n\n}\n\n/*\n *\tDescription:\n *\t\tReset status of LED_871x object.\n *   */\nvoid ResetLedStatus(PLED_PCIE pLed)\n{\n\n\tpLed->CurrLedState = RTW_LED_OFF; /* Current LED state. */\n\tpLed->bLedOn = _FALSE; /* true if LED is ON, false if LED is OFF. */\n\n\tpLed->bLedBlinkInProgress = _FALSE; /* true if it is blinking, false o.w.. */\n\tpLed->bLedWPSBlinkInProgress = _FALSE;\n\tpLed->bLedSlowBlinkInProgress = _FALSE;\n\n\tpLed->BlinkTimes = 0; /* Number of times to toggle led state for blinking. */\n\tpLed->BlinkingLedState = LED_UNKNOWN; /* Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are. */\n}\n\n/*\n*\tDescription:\n*\t\tInitialize an LED_871x object.\n*   */\nvoid\nInitLed(\n\t_adapter\t\t\t*padapter,\n\tPLED_PCIE\t\tpLed,\n\tLED_PIN\t\t\tLedPin\n)\n{\n\tpLed->padapter = padapter;\n\tpLed->LedPin = LedPin;\n\n\tResetLedStatus(pLed);\n\n\trtw_init_timer(&(pLed->BlinkTimer), padapter, BlinkTimerCallback, pLed);\n}\n\n\n/*\n *\tDescription:\n *\t\tDeInitialize an LED_871x object.\n *   */\nvoid\nDeInitLed(\n\tPLED_PCIE\t\tpLed\n)\n{\n\t_cancel_timer_ex(&(pLed->BlinkTimer));\n\tResetLedStatus(pLed);\n}\n#endif\n"
  },
  {
    "path": "hal/phydm/ap_makefile.mk",
    "content": "\n_PHYDM_FILES :=\\\n\tphydm/phydm.o \\\n\tphydm/phydm_dig.o\\\n\tphydm/phydm_antdiv.o\\\n\tphydm/phydm_soml.o\\\n\tphydm/phydm_smt_ant.o\\\n\tphydm/phydm_pathdiv.o\\\n\tphydm/phydm_rainfo.o\\\n\tphydm/phydm_dynamictxpower.o\\\n\tphydm/phydm_adaptivity.o\\\n\tphydm/phydm_debug.o\\\n\tphydm/phydm_interface.o\\\n\tphydm/phydm_phystatus.o\\\n\tphydm/phydm_hwconfig.o\\\n\tphydm/phydm_dfs.o\\\n\tphydm/phydm_cfotracking.o\\\n\tphydm/phydm_adc_sampling.o\\\n\tphydm/phydm_ccx.o\\\n\tphydm/phydm_primary_cca.o\\\n\tphydm/phydm_cck_pd.o\\\n\tphydm/phydm_rssi_monitor.o\\\n\tphydm/phydm_auto_dbg.o\\\n\tphydm/phydm_math_lib.o\\\n\tphydm/phydm_noisemonitor.o\\\n\tphydm/phydm_api.o\\\n\tphydm/phydm_pow_train.o\\\n\tphydm/phydm_lna_sat.o\\\n\tphydm/phydm_pmac_tx_setting.o\\\n\tphydm/phydm_mp.o\\\n\tphydm/txbf/phydm_hal_txbf_api.o\\\n\tEdcaTurboCheck.o\\\n\tphydm/halrf/halrf.o\\\n\tphydm/halrf/halrf_debug.o\\\n\tphydm/halrf/halphyrf_ap.o\\\n\tphydm/halrf/halrf_powertracking_ap.o\\\n\tphydm/halrf/halrf_powertracking.o\\\n\tphydm/halrf/halrf_kfree.o\n\nifeq ($(CONFIG_RTL_88E_SUPPORT),y)\n\tifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)\n\t\t_PHYDM_FILES += \\\n\t\tphydm/rtl8188e/halhwimg8188e_bb.o\\\n\t\tphydm/rtl8188e/halhwimg8188e_mac.o\\\n\t\tphydm/rtl8188e/halhwimg8188e_rf.o\\\n\t\tphydm/rtl8188e/phydm_regconfig8188e.o\\\n\t\tphydm/rtl8188e/hal8188erateadaptive.o\\\n\t\tphydm/rtl8188e/phydm_rtl8188e.o\\\n\t\tphydm/halrf/rtl8188e/halrf_8188e_ap.o\n\tendif\nendif\n\nifeq ($(CONFIG_RTL_8812_SUPPORT),y)\n\tifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)\n\t\t_PHYDM_FILES += ./phydm/halrf/rtl8812a/halrf_8812a_ap.o\n\tendif\n\t_PHYDM_FILES += phydm/rtl8812a/phydm_rtl8812a.o\nendif\n\nifeq ($(CONFIG_WLAN_HAL_8881A),y)\n\t_PHYDM_FILES += phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.o\nendif\n\nifeq ($(CONFIG_WLAN_HAL_8192EE),y)\n\t_PHYDM_FILES += \\\n\tphydm/halrf/rtl8192e/halrf_8192e_ap.o\\\n\tphydm/rtl8192e/phydm_rtl8192e.o\nendif\n\nifeq ($(CONFIG_WLAN_HAL_8814AE),y)\n\trtl8192cd-objs += phydm/halrf/rtl8814a/halrf_8814a_ap.o\n\trtl8192cd-objs += phydm/halrf/rtl8814a/halrf_iqk_8814a.o\n\tifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)\n\t\trtl8192cd-objs += \\\n\t\tphydm/rtl8814a/halhwimg8814a_bb.o\\\n\t\tphydm/rtl8814a/halhwimg8814a_mac.o\\\n\t\tphydm/rtl8814a/halhwimg8814a_rf.o\\\n\t\tphydm/rtl8814a/phydm_regconfig8814a.o\\\n\t\tphydm/rtl8814a/phydm_rtl8814a.o\n\tendif\nendif\n\nifeq ($(CONFIG_WLAN_HAL_8822BE),y)\n\t_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_8822b.o\n\t_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_iqk_8822b.o\n\t_PHYDM_FILES += phydm/halrf/rtl8822b/halhwimg8822b_rf.o\n\tifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)\n\t\t_PHYDM_FILES += \\\n\t\tphydm/rtl8822b/halhwimg8822b_bb.o\\\n\t\tphydm/rtl8822b/halhwimg8822b_mac.o\\\n\t\tphydm/rtl8822b/phydm_regconfig8822b.o\\\n\t\tphydm/rtl8822b/phydm_hal_api8822b.o\\\n\t\tphydm/rtl8822b/phydm_rtl8822b.o\n\tendif\nendif\n\nifeq ($(CONFIG_WLAN_HAL_8822CE),y)\n\t_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_8822c.o\n\t_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_iqk_8822c.o\n\t_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_dpk_8822c.o\n\t_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_rfk_init_8822c.o\n\t_PHYDM_FILES += phydm/halrf/rtl8822c/halhwimg8822c_rf.o\n\tifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)\n\t\t_PHYDM_FILES += \\\n\t\tphydm/rtl8822c/halhwimg8822c_bb.o\\\n\t\tphydm/rtl8822c/phydm_regconfig8822c.o\\\n\t\tphydm/rtl8822c/phydm_hal_api8822c.o\n\tendif\nendif\n\nifeq ($(CONFIG_WLAN_HAL_8812FE),y)\n\t_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_8812f.o\n\t_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_iqk_8812f.o\n\t_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_dpk_8812f.o\n\t_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_tssi_8812f.o\n\t_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_rfk_init_8812f.o\n\t_PHYDM_FILES += phydm/halrf/rtl8812f/halhwimg8812f_rf.o\n\tifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)\n\t\t_PHYDM_FILES += \\\n\t\tphydm/rtl8812f/halhwimg8812f_bb.o\\\n\t\tphydm/rtl8812f/halhwimg8812f_mac.o\\\n\t\tphydm/rtl8812f/phydm_regconfig8812f.o\\\n\t\tphydm/rtl8812f/phydm_hal_api8812f.o\n\tendif\nendif\n\nifeq ($(CONFIG_WLAN_HAL_8821CE),y)\n\t_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_8821c.o\n\t_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_iqk_8821c.o\n\t_PHYDM_FILES += phydm/halrf/rtl8821c/halhwimg8821c_rf.o\n\tifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)\n\t\t_PHYDM_FILES += \\\n\t\tphydm/rtl8821c/halhwimg8821c_bb.o\\\n\t\tphydm/rtl8821c/halhwimg8821c_mac.o\\\n\t\tphydm/rtl8821c/phydm_regconfig8821c.o\\\n\t\tphydm/rtl8821c/phydm_hal_api8821c.o\n\tendif\nendif\n\nifeq ($(CONFIG_WLAN_HAL_8197F),y)\n\t\t_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_8197f.o\n\t\t_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_iqk_8197f.o\n\t\t_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_dpk_8197f.o\n\t\t_PHYDM_FILES += phydm/halrf/rtl8197f/halhwimg8197f_rf.o\n\t\t_PHYDM_FILES += efuse_97f/efuse.o\n\tifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)\n\t\t_PHYDM_FILES += \\\n\t\tphydm/rtl8197f/halhwimg8197f_bb.o\\\n\t\tphydm/rtl8197f/halhwimg8197f_mac.o\\\n\t\tphydm/rtl8197f/phydm_hal_api8197f.o\\\n\t\tphydm/rtl8197f/phydm_regconfig8197f.o\\\n\t\tphydm/rtl8197f/phydm_rtl8197f.o\n\tendif\nendif\n\n\nifeq ($(CONFIG_WLAN_HAL_8192FE),y)\n\t\t_PHYDM_FILES += phydm/halrf/rtl8192f/halrf_8192f.o\n\t\t_PHYDM_FILES += phydm/halrf/rtl8192f/halrf_dpk_8192f.o\n\t\t_PHYDM_FILES += phydm/halrf/rtl8192f/halhwimg8192f_rf.o\n\tifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)\n\t\t_PHYDM_FILES += \\\n\t\tphydm/rtl8192f/halhwimg8192f_bb.o\\\n\t\tphydm/rtl8192f/halhwimg8192f_mac.o\\\n\t\tphydm/rtl8192f/phydm_hal_api8192f.o\\\n\t\tphydm/rtl8192f/phydm_regconfig8192f.o\\\n\t\tphydm/rtl8192f/phydm_rtl8192f.o\n\tendif\nendif\n\nifeq ($(CONFIG_WLAN_HAL_8198F),y)\n\t\t_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_8198f.o\n\t\t_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_iqk_8198f.o\n\t\t_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_dpk_8198f.o\n\t\t_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_rfk_init_8198f.o\n\t\t_PHYDM_FILES += phydm/halrf/rtl8198f/halhwimg8198f_rf.o\n\tifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)\n\t\t_PHYDM_FILES += \\\n\t\tphydm/rtl8198f/phydm_hal_api8198f.o\\\n\t\tphydm/rtl8198f/halhwimg8198f_bb.o\\\n\t\tphydm/rtl8198f/halhwimg8198f_mac.o\\\n\t\tphydm/rtl8198f/phydm_regconfig8198f.o \\\n\t\tphydm/halrf/rtl8198f/halrf_8198f.o\n\tendif\nendif\n\nifeq ($(CONFIG_WLAN_HAL_8814BE),y)\n\t\t_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_8814b.o\n\t\t_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_iqk_8814b.o\n\t\t_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_dpk_8814b.o\n\t\t_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_rfk_init_8814b.o\n\t\t_PHYDM_FILES += phydm/halrf/rtl8814b/halhwimg8814b_rf.o\n\tifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)\n\t\t_PHYDM_FILES += \\\n\t\tphydm/rtl8814b/phydm_hal_api8814b.o\\\n\t\tphydm/rtl8814b/halhwimg8814b_bb.o\\\n\t\tphydm/rtl8814b/halhwimg8814b_mac.o\\\n\t\tphydm/rtl8814b/phydm_regconfig8814b.o \\\n\t\tphydm/halrf/rtl8814b/halrf_8814b.o\n\tendif\nendif\n\n\n\n"
  },
  {
    "path": "hal/phydm/halhwimg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#pragma once\n#ifndef __INC_HW_IMG_H\n#define __INC_HW_IMG_H\n\n/*@\n * 2011/03/15 MH Add for different IC HW image file selection. code size consideration.\n *   */\n#if RT_PLATFORM == PLATFORM_LINUX\n\n\t#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)\n\t\t/* @For 92C */\n\t\t#define\t\tRTL8192CE_HWIMG_SUPPORT\t\t\t\t\t1\n\t\t#define\t\tRTL8192CE_TEST_HWIMG_SUPPORT\t\t\t0\n\t\t#define\t\tRTL8192CU_HWIMG_SUPPORT\t\t\t\t\t0\n\t\t#define\t\tRTL8192CU_TEST_HWIMG_SUPPORT\t\t\t0\n\n\t\t/* @For 92D */\n\t\t#define\t\tRTL8192DE_HWIMG_SUPPORT\t\t\t\t\t1\n\t\t#define\t\tRTL8192DE_TEST_HWIMG_SUPPORT\t\t\t0\n\t\t#define\t\tRTL8192DU_HWIMG_SUPPORT\t\t\t\t\t0\n\t\t#define\t\tRTL8192DU_TEST_HWIMG_SUPPORT\t\t\t0\n\n\t\t/* @For 8723 */\n\t\t#define\t\tRTL8723E_HWIMG_SUPPORT\t\t\t\t\t1\n\t\t#define\t\tRTL8723U_HWIMG_SUPPORT\t\t\t\t\t0\n\t\t#define\t\tRTL8723S_HWIMG_SUPPORT\t\t\t\t\t0\n\n\t\t/* @For 88E */\n\t\t#define\t\tRTL8188EE_HWIMG_SUPPORT\t\t\t\t\t0\n\t\t#define\t\tRTL8188EU_HWIMG_SUPPORT\t\t\t\t\t0\n\t\t#define\t\tRTL8188ES_HWIMG_SUPPORT\t\t\t\t\t0\n\n\t#elif (DEV_BUS_TYPE == RT_USB_INTERFACE)\n\t\t/* @For 92C */\n\t\t#define\tRTL8192CE_HWIMG_SUPPORT\t\t\t\t0\n\t\t#define\tRTL8192CE_TEST_HWIMG_SUPPORT\t\t\t0\n\t\t#define\tRTL8192CU_HWIMG_SUPPORT\t\t\t\t1\n\t\t#define\tRTL8192CU_TEST_HWIMG_SUPPORT\t\t\t0\n\n\t\t/* @For 92D */\n\t\t#define\tRTL8192DE_HWIMG_SUPPORT\t\t\t\t0\n\t\t#define\tRTL8192DE_TEST_HWIMG_SUPPORT\t\t\t0\n\t\t#define\tRTL8192DU_HWIMG_SUPPORT\t\t\t\t1\n\t\t#define\tRTL8192DU_TEST_HWIMG_SUPPORT\t\t\t0\n\n\t\t/* @For 8723 */\n\t\t#define\tRTL8723E_HWIMG_SUPPORT\t\t\t\t\t0\n\t\t#define\tRTL8723U_HWIMG_SUPPORT\t\t\t\t\t1\n\t\t#define\tRTL8723S_HWIMG_SUPPORT\t\t\t\t\t0\n\n\t\t/* @For 88E */\n\t\t#define\t\tRTL8188EE_HWIMG_SUPPORT\t\t\t\t\t0\n\t\t#define\t\tRTL8188EU_HWIMG_SUPPORT\t\t\t\t\t0\n\t\t#define\t\tRTL8188ES_HWIMG_SUPPORT\t\t\t\t\t0\n\n\t#elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE)\n\t\t/* @For 92C */\n\t\t#define\tRTL8192CE_HWIMG_SUPPORT\t\t\t\t0\n\t\t#define\tRTL8192CE_TEST_HWIMG_SUPPORT\t\t\t0\n\t\t#define\tRTL8192CU_HWIMG_SUPPORT\t\t\t\t1\n\t\t#define\tRTL8192CU_TEST_HWIMG_SUPPORT\t\t\t0\n\n\t\t/* @For 92D */\n\t\t#define\tRTL8192DE_HWIMG_SUPPORT\t\t\t\t0\n\t\t#define\tRTL8192DE_TEST_HWIMG_SUPPORT\t\t\t0\n\t\t#define\tRTL8192DU_HWIMG_SUPPORT\t\t\t\t1\n\t\t#define\tRTL8192DU_TEST_HWIMG_SUPPORT\t\t\t0\n\n\t\t/* @For 8723 */\n\t\t#define\tRTL8723E_HWIMG_SUPPORT\t\t\t\t\t0\n\t\t#define\tRTL8723U_HWIMG_SUPPORT\t\t\t\t\t0\n\t\t#define\tRTL8723S_HWIMG_SUPPORT\t\t\t\t\t1\n\n\t\t/* @For 88E */\n\t\t#define\t\tRTL8188EE_HWIMG_SUPPORT\t\t\t\t\t0\n\t\t#define\t\tRTL8188EU_HWIMG_SUPPORT\t\t\t\t\t0\n\t\t#define\t\tRTL8188ES_HWIMG_SUPPORT\t\t\t\t\t0\n\t#endif\n\n#else\t/* PLATFORM_WINDOWS & MacOSX */\n\n\t/* @For 92C */\n\t#define\t\tRTL8192CE_HWIMG_SUPPORT\t\t\t\t\t\t1\n\t#define\t\tRTL8192CE_TEST_HWIMG_SUPPORT\t\t\t\t1\n\t#define\t\tRTL8192CU_HWIMG_SUPPORT\t\t\t\t\t\t1\n\t#define\t\tRTL8192CU_TEST_HWIMG_SUPPORT\t\t\t\t1\n\n\t/* @For 92D */\n\t#define\t\tRTL8192DE_HWIMG_SUPPORT\t\t\t\t\t1\n\t#define\t\tRTL8192DE_TEST_HWIMG_SUPPORT\t\t\t\t1\n\t#define\t\tRTL8192DU_HWIMG_SUPPORT\t\t\t\t\t1\n\t#define\t\tRTL8192DU_TEST_HWIMG_SUPPORT\t\t\t\t1\n\n\t#if defined(UNDER_CE)\n\t\t/* @For 8723 */\n\t\t#define\t\tRTL8723E_HWIMG_SUPPORT\t\t\t\t\t0\n\t\t#define\t\tRTL8723U_HWIMG_SUPPORT\t\t\t\t\t0\n\t\t#define\t\tRTL8723S_HWIMG_SUPPORT\t\t\t\t\t1\n\n\t\t/* @For 88E */\n\t\t#define\t\tRTL8188EE_HWIMG_SUPPORT\t\t\t\t\t0\n\t\t#define\t\tRTL8188EU_HWIMG_SUPPORT\t\t\t\t\t0\n\t\t#define\t\tRTL8188ES_HWIMG_SUPPORT\t\t\t\t\t0\n\n\t#else\n\n\t\t/* @For 8723 */\n\t\t#define\t\tRTL8723E_HWIMG_SUPPORT\t\t\t\t\t1\n\t\t/* @#define\t\tRTL_8723E_TEST_HWIMG_SUPPORT\t\t\t1 */\n\t\t#define\t\tRTL8723U_HWIMG_SUPPORT\t\t\t\t\t1\n\t\t/* @#define\t\tRTL_8723U_TEST_HWIMG_SUPPORT\t\t\t1 */\n\t\t#define\t\tRTL8723S_HWIMG_SUPPORT\t\t\t\t\t1\n\t\t/* @#define\t\tRTL_8723S_TEST_HWIMG_SUPPORT\t\t\t1 */\n\n\t\t/* @For 88E */\n\t\t#define\t\tRTL8188EE_HWIMG_SUPPORT\t\t\t\t\t1\n\t\t#define\t\tRTL8188EU_HWIMG_SUPPORT\t\t\t\t\t1\n\t\t#define\t\tRTL8188ES_HWIMG_SUPPORT\t\t\t\t\t1\n\t#endif\n\n#endif\n\n#endif /* @__INC_HW_IMG_H */\n"
  },
  {
    "path": "hal/phydm/halrf/halphyrf_ap.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#ifndef index_mapping_NUM_88E\n\t#define\tindex_mapping_NUM_88E\t15\n#endif\n\n/* #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) */\n\n#define\tCALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \\\n\tdo {\\\n\t\tfor (_offset = 0; _offset < _size; _offset++) { \\\n\t\t\t\\\n\t\t\tif (_delta_thermal < thermal_threshold[_direction][_offset]) { \\\n\t\t\t\t\\\n\t\t\t\tif (_offset != 0)\\\n\t\t\t\t\t_offset--;\\\n\t\t\t\tbreak;\\\n\t\t\t} \\\n\t\t}\t\t\t\\\n\t\tif (_offset >= _size)\\\n\t\t\t_offset = _size-1;\\\n\t} while (0)\n\nvoid odm_clear_txpowertracking_state(\t\n\tvoid *dm_void\n)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);\n\tstruct rtl8192cd_priv *priv = dm->priv;\n\n\tu8 i;\n\t\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"===>%s\\n\", __func__);\n\n\tfor (i = 0; i < MAX_RF_PATH; i++) {\n\t\tcali_info->absolute_ofdm_swing_idx[i] = 0;\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"cali_info->absolute_ofdm_swing_idx[%d]=%d\\n\",\n\t\t\ti, cali_info->absolute_ofdm_swing_idx[i]);\n\t}\n\n \tdm->rf_calibrate_info.thermal_value = 0;\n\tdm->rf_calibrate_info.thermal_value_lck = 0;\n\tdm->rf_calibrate_info.thermal_value_iqk = 0;\n}\n\nvoid configure_txpower_track(\n\tvoid\t\t*dm_void,\n\tstruct txpwrtrack_cfg\t*config\n)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n#if RTL8812A_SUPPORT\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t/* if (IS_HARDWARE_TYPE_8812(dm->adapter)) */\n\tif (dm->support_ic_type == ODM_RTL8812)\n\t\tconfigure_txpower_track_8812a(config);\n\t/* else */\n#endif\n#endif\n\n#if RTL8814A_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8814A)\n\t\tconfigure_txpower_track_8814a(config);\n#endif\n\n\n#if RTL8188E_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8188E)\n\t\tconfigure_txpower_track_8188e(config);\n#endif\n\n#if RTL8197F_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8197F)\n\t\tconfigure_txpower_track_8197f(config);\n#endif\n\n#if RTL8822B_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8822B)\n\t\tconfigure_txpower_track_8822b(config);\n#endif\n\n#if RTL8192F_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8192F)\n\t\tconfigure_txpower_track_8192f(config);\n#endif\n\n#if RTL8198F_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8198F)\n\t\tconfigure_txpower_track_8198f(config);\n#endif\n\n#if RTL8814B_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8814B)\n\t\tconfigure_txpower_track_8814b(config);\n#endif\n\n}\n\n#if (RTL8192E_SUPPORT == 1)\nvoid\nodm_txpowertracking_callback_thermal_meter_92e(\n\tvoid\t\t*dm_void\n)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info\t*iqk_info = &dm->IQK_info;\n\tu8\tthermal_value = 0, delta, delta_IQK, delta_LCK, channel, is_decrease, rf_mimo_mode;\n\tu8\tthermal_value_avg_count = 0;\n\tu8     OFDM_min_index = 10; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur */\n\ts8\tOFDM_index[2], index ;\n\tu32\tthermal_value_avg = 0, reg0x18;\n\tu32\ti = 0, j = 0, rf;\n\ts32\tvalue32, CCK_index = 0, ele_A, ele_D, ele_C, X, Y;\n\tstruct rtl8192cd_priv\t*priv = dm->priv;\n\n\trf_mimo_mode = dm->rf_type;\n\t/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK,\"%s:%d rf_mimo_mode:%d\\n\", __FUNCTION__, __LINE__, rf_mimo_mode); */\n\n#ifdef MP_TEST\n\tif ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {\n\t\tchannel = priv->pshare->working_channel;\n\t\tif (priv->pshare->mp_txpwr_tracking == false)\n\t\t\treturn;\n\t} else\n#endif\n\t{\n\t\tchannel = (priv->pmib->dot11RFEntry.dot11channel);\n\t}\n\n\tthermal_value = (unsigned char)odm_get_rf_reg(dm, RF_PATH_A, ODM_RF_T_METER_92E, 0xfc00);\t/* 0x42: RF Reg[15:10] 88E */\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"\\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\\n\", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);\n\n\n\tswitch (rf_mimo_mode) {\n\tcase RF_1T1R:\n\t\trf = 1;\n\t\tbreak;\n\tcase RF_2T2R:\n\t\trf = 2;\n\t\tbreak;\n\tdefault:\n\t\trf = 2;\n\t\tbreak;\n\t}\n\n\t/* Query OFDM path A default setting \tBit[31:21] */\n\tele_D = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D);\n\tfor (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {\n\t\tif (ele_D == (ofdm_swing_table_92e[i] >> 22)) {\n\t\t\tOFDM_index[0] = (unsigned char)i;\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\\n\", ele_D, OFDM_index[0]);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* Query OFDM path B default setting */\n\tif (rf_mimo_mode == RF_2T2R) {\n\t\tele_D = phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKOFDM_D);\n\t\tfor (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {\n\t\t\tif (ele_D == (ofdm_swing_table_92e[i] >> 22)) {\n\t\t\t\tOFDM_index[1] = (unsigned char)i;\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\\n\", ele_D, OFDM_index[1]);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* calculate average thermal meter */\n\t{\n\t\tpriv->pshare->thermal_value_avg_88xx[priv->pshare->thermal_value_avg_index_88xx] = thermal_value;\n\t\tpriv->pshare->thermal_value_avg_index_88xx++;\n\t\tif (priv->pshare->thermal_value_avg_index_88xx == AVG_THERMAL_NUM_88XX)\n\t\t\tpriv->pshare->thermal_value_avg_index_88xx = 0;\n\n\t\tfor (i = 0; i < AVG_THERMAL_NUM_88XX; i++) {\n\t\t\tif (priv->pshare->thermal_value_avg_88xx[i]) {\n\t\t\t\tthermal_value_avg += priv->pshare->thermal_value_avg_88xx[i];\n\t\t\t\tthermal_value_avg_count++;\n\t\t\t}\n\t\t}\n\n\t\tif (thermal_value_avg_count) {\n\t\t\tthermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count);\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"AVG Thermal Meter = 0x%x\\n\", thermal_value);\n\t\t}\n\t}\n\n\t/* Initialize */\n\tif (!priv->pshare->thermal_value) {\n\t\tpriv->pshare->thermal_value = priv->pmib->dot11RFEntry.ther;\n\t\tpriv->pshare->thermal_value_iqk = thermal_value;\n\t\tpriv->pshare->thermal_value_lck = thermal_value;\n\t}\n\n\tif (thermal_value != priv->pshare->thermal_value) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"\\n******** START POWER TRACKING ********\\n\");\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"\\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\\n\", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);\n\n\t\tdelta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);\n\t\tdelta_IQK = RTL_ABS(thermal_value, priv->pshare->thermal_value_iqk);\n\t\tdelta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck);\n\t\tis_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0);\n\n#ifdef _TRACKING_TABLE_FILE\n\t\tif (priv->pshare->rf_ft_var.pwr_track_file) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"diff: (%s)%d ==> get index from table : %d)\\n\", (is_decrease ? \"-\" : \"+\"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));\n\n\t\t\tif (is_decrease) {\n\t\t\t\tfor (i = 0; i < rf; i++) {\n\t\t\t\t\tOFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);\n\t\t\t\t\tOFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E- 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]);\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\\n\", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));\n\t\t\t\t\tCCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);\n\t\t\t\t\tCCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index);\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\\n\",  CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tfor (i = 0; i < rf; i++) {\n\t\t\t\t\tOFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);\n\t\t\t\t\tOFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ?  OFDM_min_index : OFDM_index[i]);\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\\n\", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));\n\t\t\t\t\tCCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);\n\t\t\t\t\tCCK_index = ((CCK_index < 0) ? 0 : CCK_index);\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\\n\", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));\n\t\t\t\t}\n\t\t\t}\n\t\t}\n#endif /* CFG_TRACKING_TABLE_FILE */\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] = %x\\n\", ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]);\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] = %x\\n\", ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]);\n\n\t\t/* Adujst OFDM Ant_A according to IQK result */\n\t\tele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22;\n\t\tX = priv->pshare->rege94;\n\t\tY = priv->pshare->rege9c;\n\n\t\tif (X != 0) {\n\t\t\tif ((X & 0x00000200) != 0)\n\t\t\t\tX = X | 0xFFFFFC00;\n\t\t\tele_A = ((X * ele_D) >> 8) & 0x000003FF;\n\n\t\t\t/* new element C = element D x Y */\n\t\t\tif ((Y & 0x00000200) != 0)\n\t\t\t\tY = Y | 0xFFFFFC00;\n\t\t\tele_C = ((Y * ele_D) >> 8) & 0x000003FF;\n\n\t\t\t/* wirte new elements A, C, D to regC80 and regC94, element B is always 0 */\n\t\t\tvalue32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;\n\t\t\tphy_set_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, value32);\n\n\t\t\tvalue32 = (ele_C & 0x000003C0) >> 6;\n\t\t\tphy_set_bb_reg(priv, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, value32);\n\n\t\t\tvalue32 = ((X * ele_D) >> 7) & 0x01;\n\t\t\tphy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), value32);\n\t\t} else {\n\t\t\tphy_set_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]);\n\t\t\tphy_set_bb_reg(priv, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, 0x00);\n\t\t\tphy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), 0x00);\n\t\t}\n\n\t\tset_CCK_swing_index(priv, CCK_index);\n\n\t\tif (rf == 2) {\n\t\t\tele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] & 0xFFC00000) >> 22;\n\t\t\tX = priv->pshare->regeb4;\n\t\t\tY = priv->pshare->regebc;\n\n\t\t\tif (X != 0) {\n\t\t\t\tif ((X & 0x00000200) != 0)\t/* consider minus */\n\t\t\t\t\tX = X | 0xFFFFFC00;\n\t\t\t\tele_A = ((X * ele_D) >> 8) & 0x000003FF;\n\n\t\t\t\t/* new element C = element D x Y */\n\t\t\t\tif ((Y & 0x00000200) != 0)\n\t\t\t\t\tY = Y | 0xFFFFFC00;\n\t\t\t\tele_C = ((Y * ele_D) >> 8) & 0x00003FF;\n\n\t\t\t\t/* wirte new elements A, C, D to regC88 and regC9C, element B is always 0 */\n\t\t\t\tvalue32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;\n\t\t\t\tphy_set_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, value32);\n\n\t\t\t\tvalue32 = (ele_C & 0x000003C0) >> 6;\n\t\t\t\tphy_set_bb_reg(priv, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, value32);\n\n\t\t\t\tvalue32 = ((X * ele_D) >> 7) & 0x01;\n\t\t\t\tphy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), value32);\n\t\t\t} else {\n\t\t\t\tphy_set_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]);\n\t\t\t\tphy_set_bb_reg(priv, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, 0x00);\n\t\t\t\tphy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), 0x00);\n\t\t\t}\n\n\t\t}\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"0xc80 = 0x%x\\n\", phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD));\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"0xc88 = 0x%x\\n\", phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD));\n\n\t\tif ((delta_IQK > 3) && (!iqk_info->rfk_forbidden)) {\n\t\t\tpriv->pshare->thermal_value_iqk = thermal_value;\n#ifdef MP_TEST\n#endif\t\t\tif (!(*(dm->mp_mode) && (OPMODE & (WIFI_MP_CTX_BACKGROUND | WIFI_MP_CTX_PACKET))))\n\n\t\t\t\thalrf_iqk_trigger(dm, false);\n\t\t}\n\n\t\tif ((delta_LCK > 8)  && (!iqk_info->rfk_forbidden)) {\n\t\t\tRTL_W8(0x522, 0xff);\n\t\t\treg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1);\n\t\t\tphy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1);\n\t\t\tphy_set_rf_reg(priv, RF_PATH_A, 0x18, BIT(15), 1);\n\t\t\tdelay_ms(1);\n\t\t\tphy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 0);\n\t\t\tphy_set_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, reg0x18);\n\t\t\tRTL_W8(0x522, 0x0);\n\t\t\tpriv->pshare->thermal_value_lck = thermal_value;\n\t\t}\n\t}\n\n\t/* update thermal meter value */\n\tpriv->pshare->thermal_value = thermal_value;\n\tfor (i = 0 ; i < rf ; i++)\n\t\tpriv->pshare->OFDM_index[i] = OFDM_index[i];\n\tpriv->pshare->CCK_index = CCK_index;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"\\n******** END:%s() ********\\n\", __FUNCTION__);\n}\n#endif\n\n#if (RTL8814B_SUPPORT == 1)\nvoid\nodm_txpowertracking_callback_thermal_meter_jaguar_series4(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);\n \tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\tstruct rtl8192cd_priv *priv = dm->priv;\n\tstruct txpwrtrack_cfg c;\n\n\tif (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))\n\t\treturn;\n\n\tu8 thermal_value[MAX_RF_PATH] = {0}, delta[MAX_RF_PATH] = {0};\n\tu8 delta_swing_table_idx_tup[DELTA_SWINGIDX_SIZE] = {0};\n\tu8 delta_swing_table_idx_tdown[DELTA_SWINGIDX_SIZE] = {0};\n\tu8 delta_LCK = 0, delta_IQK = 0, i = 0, j = 0, p;\n\tu8 thermal_value_avg_count[MAX_RF_PATH] = {0};\n\tu32 thermal_value_avg[MAX_RF_PATH] = {0};\n\ts8 thermal_value_temp[MAX_RF_PATH] = {0};\n\n\tu8 *pwrtrk_tab_up_a = NULL;\n\tu8 *pwrtrk_tab_down_a = NULL;\n\tu8 *pwrtrk_tab_up_b = NULL;\n\tu8 *pwrtrk_tab_down_b = NULL;\n\tu8 *pwrtrk_tab_up_c = NULL;\n\tu8 *pwrtrk_tab_down_c = NULL;\n\tu8 *pwrtrk_tab_up_d = NULL;\n\tu8 *pwrtrk_tab_down_d = NULL;\n\n\tconfigure_txpower_track(dm, &c);\n\n\t(*c.get_delta_swing_table)(dm,\n\t\t(u8 **)&pwrtrk_tab_up_a, (u8 **)&pwrtrk_tab_down_a,\n\t\t(u8 **)&pwrtrk_tab_up_b, (u8 **)&pwrtrk_tab_down_b);\n\n\tif (GET_CHIP_VER(priv) == VERSION_8814B) {\n\t\t(*c.get_delta_swing_table8814only)(dm,\n\t\t\t(u8 **)&pwrtrk_tab_up_c, (u8 **)&pwrtrk_tab_down_c,\n\t\t\t(u8 **)&pwrtrk_tab_up_d, (u8 **)&pwrtrk_tab_down_d);\n\t}\n\n\tcali_info->txpowertracking_callback_cnt++;\n\tcali_info->is_txpowertracking_init = true;\n\n\t/* Initialize */\n\tif (!dm->rf_calibrate_info.thermal_value)\n\t\tdm->rf_calibrate_info.thermal_value =\n\t\t\tpriv->pmib->dot11RFEntry.thermal[RF_PATH_A];\n\n\tif (!dm->rf_calibrate_info.thermal_value_lck)\n\t\tdm->rf_calibrate_info.thermal_value_lck =\n\t\t\tpriv->pmib->dot11RFEntry.thermal[RF_PATH_A];\n\n\tif (!dm->rf_calibrate_info.thermal_value_iqk)\n\t\tdm->rf_calibrate_info.thermal_value_iqk =\n\t\t\tpriv->pmib->dot11RFEntry.thermal[RF_PATH_A];\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"===>odm_txpowertracking_callback_thermal_meter\\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\\n\",\n\t\tcali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base_path[RF_PATH_A], cali_info->default_ofdm_index);\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"cali_info->txpowertrack_control=%d\\n\", cali_info->txpowertrack_control);\n\n\tfor (i = 0; i < c.rf_path_count; i++) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\"PGthermal[%d]=0x%x(%d)\\n\", i, \n\t\t\tpriv->pmib->dot11RFEntry.thermal[i],\n\t\t\tpriv->pmib->dot11RFEntry.thermal[i]);\n\n\t\tif (priv->pmib->dot11RFEntry.thermal[i] == 0xff ||\n\t\t\tpriv->pmib->dot11RFEntry.thermal[i] == 0x0)\n\t\t\treturn;\n\t}\n\n\tfor (i = 0; i < c.rf_path_count; i++) {\n\t\tthermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0xfc00);\t/* 0x42: RF Reg[15:10] 88E */\n\n\t\tthermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + power_time_thermal(%d)\\n\", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));\n\n\t\tif (thermal_value_temp[i] > 63)\n\t\t\tthermal_value[i] = 63;\n\t\telse if (thermal_value_temp[i] < 0)\n\t\t\tthermal_value[i] = 0;\n\t\telse\n\t\t\tthermal_value[i] = thermal_value_temp[i];\n\t}\n\n\tfor (j = 0; j < c.rf_path_count; j++) {\n\t\tcali_info->thermal_value_avg_path[j][cali_info->thermal_value_avg_index_path[j]] = thermal_value[j];\n\t\tcali_info->thermal_value_avg_index_path[j]++;\n\t\tif (cali_info->thermal_value_avg_index_path[j] == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/\n\t\t\tcali_info->thermal_value_avg_index_path[j] = 0;\n\n\n\t\tfor (i = 0; i < c.average_thermal_num; i++) {\n\t\t\tif (cali_info->thermal_value_avg_path[j][i]) {\n\t\t\t\tthermal_value_avg[j] += cali_info->thermal_value_avg_path[j][i];\n\t\t\t\tthermal_value_avg_count[j]++;\n\t\t\t}\n\t\t}\n\n\t\tif (thermal_value_avg_count[j]) {            /* Calculate Average thermal_value after average enough times */\n\t\t\tthermal_value[j] = (u8)(thermal_value_avg[j] / thermal_value_avg_count[j]);\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"PGthermal[%d] = 0x%x(%d),   AVG Thermal Meter = 0x%x(%d)\\n\", j,\n\t\t\t\tpriv->pmib->dot11RFEntry.thermal[j],\n\t\t\t\tpriv->pmib->dot11RFEntry.thermal[j],\n\t\t\t\tthermal_value[j],\n\t\t\t\tthermal_value[j]);\n\t\t}\n\t\t/* 4 5. Calculate delta, delta_LCK, delta_IQK. */\n\n\t\t/* \"delta\" here is used to determine whether thermal value changes or not. */\n\t\tdelta[j] = RTL_ABS(thermal_value[j], priv->pmib->dot11RFEntry.thermal[j]);\n\t\tdelta_LCK = RTL_ABS(thermal_value[RF_PATH_A], dm->rf_calibrate_info.thermal_value_lck);\n\t\tdelta_IQK = RTL_ABS(thermal_value[RF_PATH_A], dm->rf_calibrate_info.thermal_value_iqk);\n\t}\n\n\t/*4 6. If necessary, do LCK.*/\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"(delta[%d], delta_LCK, delta_IQK) = (%d, %d, %d)\\n\", RF_PATH_A, delta[RF_PATH_A], delta_LCK, delta_IQK);\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"(delta[%d], delta_LCK, delta_IQK) = (%d, %d, %d)\\n\", RF_PATH_B, delta[RF_PATH_B], delta_LCK, delta_IQK);\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"(delta[%d], delta_LCK, delta_IQK) = (%d, %d, %d)\\n\", RF_PATH_C, delta[RF_PATH_C], delta_LCK, delta_IQK);\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"(delta[%d], delta_LCK, delta_IQK) = (%d, %d, %d)\\n\", RF_PATH_D, delta[RF_PATH_D], delta_LCK, delta_IQK);\n\n\t/* Wait sacn to do LCK by RF Jenyu*/\n\tif( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {\n\t\t/* Delta temperature is equal to or larger than 20 centigrade.*/\n\t\tif (delta_LCK >= c.threshold_iqk) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"delta_LCK(%d) >= threshold_iqk(%d)\\n\", delta_LCK, c.threshold_iqk);\n\t\t\tcali_info->thermal_value_lck = thermal_value[RF_PATH_A];\n\n\t\t\t/*Use RTLCK, so close power tracking driver LCK*/\n\t\t\tif ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {\n\t\t\t\tif (c.phy_lc_calibrate)\n\t\t\t\t\t(*c.phy_lc_calibrate)(dm);\n\t\t\t} else\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"Do not do LCK\\n\");\n\t\t}\n\t}\n\n\t/*3 7. If necessary, move the index of swing table to adjust Tx power.*/\n#ifdef _TRACKING_TABLE_FILE\n\tfor (i = 0; i < c.rf_path_count; i++) {\n\t\tif (i == RF_PATH_B) {\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tup, pwrtrk_tab_up_b, DELTA_SWINGIDX_SIZE);\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tdown, pwrtrk_tab_down_b, DELTA_SWINGIDX_SIZE);\n\t\t} else if (i == RF_PATH_C) {\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tup, pwrtrk_tab_up_c, DELTA_SWINGIDX_SIZE);\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tdown, pwrtrk_tab_down_c, DELTA_SWINGIDX_SIZE);\n\t\t} else if (i == RF_PATH_D) {\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tup, pwrtrk_tab_up_d, DELTA_SWINGIDX_SIZE);\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tdown, pwrtrk_tab_down_d, DELTA_SWINGIDX_SIZE);\n\t\t} else {\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tup, pwrtrk_tab_up_a, DELTA_SWINGIDX_SIZE);\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tdown, pwrtrk_tab_down_a, DELTA_SWINGIDX_SIZE);\n\t\t}\n\n\t\tcali_info->delta_power_index_last_path[i] = cali_info->delta_power_index_path[i];\t/*recording poer index offset*/\n\t\tdelta[i] = thermal_value[i] > priv->pmib->dot11RFEntry.thermal[i] ? (thermal_value[i] - priv->pmib->dot11RFEntry.thermal[i]) : (priv->pmib->dot11RFEntry.thermal[i] - thermal_value[i]);\n\t\t\t\t\n\t\tif (delta[i] >= TXPWR_TRACK_TABLE_SIZE)\n\t\t\tdelta[i] = TXPWR_TRACK_TABLE_SIZE - 1;\n\n\t\tif (thermal_value[i] > priv->pmib->dot11RFEntry.thermal[i]) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"delta_swing_table_idx_tup[%d]=%d Path=%d\\n\", delta[i], delta_swing_table_idx_tup[delta[i]], i);\n\t\t\t\t\n\t\t\tcali_info->delta_power_index_path[i] = delta_swing_table_idx_tup[delta[i]];\n\t\t\tcali_info->absolute_ofdm_swing_idx[i] =  delta_swing_table_idx_tup[delta[i]];\t    /*Record delta swing for mix mode power tracking*/\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"******Temp is higher and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\\n\", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);\n\t\t} else {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"delta_swing_table_idx_tdown[%d]=%d Path=%d\\n\", delta[i], delta_swing_table_idx_tdown[delta[i]], i);\n\t\t\tcali_info->delta_power_index_path[i] = -1 * delta_swing_table_idx_tdown[delta[i]];\n\t\t\tcali_info->absolute_ofdm_swing_idx[i] = -1 * delta_swing_table_idx_tdown[delta[i]];        /*Record delta swing for mix mode power tracking*/\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"******Temp is lower and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\\n\", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);\n\t\t}\n\t}\n\n#endif\n\n\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\t\n\t\tif (cali_info->delta_power_index_path[p] == cali_info->delta_power_index_last_path[p])\t     /*If Thermal value changes but lookup table value still the same*/\n\t\t\tcali_info->power_index_offset_path[p] = 0;\n\t\telse\n\t\t\tcali_info->power_index_offset_path[p] = cali_info->delta_power_index_path[p] - cali_info->delta_power_index_last_path[p];\t/*Power index diff between 2 times Power Tracking*/\n\t}\n\n\tif ((cali_info->power_index_offset_path[RF_PATH_A] != 0 ||\n\t\tcali_info->power_index_offset_path[RF_PATH_B] != 0 ||\n\t\tcali_info->power_index_offset_path[RF_PATH_C] != 0 ||\n\t\tcali_info->power_index_offset_path[RF_PATH_D] != 0)) {\n\n\t\tif (dm->support_ic_type == ODM_RTL8814B) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking MIX_MODE**********\\n\");\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t\t} else {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking BBSWING_MODE**********\\n\");\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);\n\t\t}\n\t} else\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"TXAGC offset is unchanged\\n\");\n\n\t/* Wait sacn to do IQK by RF Jenyu*/\n\tif ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {\n\t\t/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/\n\t\tif (delta_IQK >= c.threshold_iqk) {\n\t\t\tcali_info->thermal_value_iqk = thermal_value[RF_PATH_A];\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"delta_IQK(%d) >= threshold_iqk(%d)\\n\", delta_IQK, c.threshold_iqk);\n\t\t\tif (!cali_info->is_iqk_in_progress)\n\t\t\t\t(*c.do_iqk)(dm, delta_IQK, thermal_value[RF_PATH_A], 8);\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"Do IQK\\n\");\n\t\t}\n\t}\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"<===%s\\n\", __func__);\n\n\tcali_info->tx_powercount = 0;\n}\n#endif\n\n#if (RTL8197F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\\\n\tRTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)\nvoid\nodm_txpowertracking_callback_thermal_meter_jaguar_series3(\n\tvoid\t\t*dm_void\n)\n{\n#if 1\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase;\n\tu8 thermal_value_avg_count = 0, p = 0, i = 0;\n\tu32 thermal_value_avg = 0;\n\tstruct rtl8192cd_priv *priv = dm->priv;\n\tstruct txpwrtrack_cfg c;\n\tstruct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\t/*The following tables decide the final index of OFDM/CCK swing table.*/\n\tu8 *pwrtrk_tab_up_a = NULL, *pwrtrk_tab_down_a = NULL;\n\tu8 *pwrtrk_tab_up_b = NULL, *pwrtrk_tab_down_b = NULL;\n\tu8 *pwrtrk_tab_up_cck_a = NULL, *pwrtrk_tab_down_cck_a = NULL;\n\tu8 *pwrtrk_tab_up_cck_b = NULL, *pwrtrk_tab_down_cck_b = NULL;\n\t/*for 8814 add by Yu Chen*/\n\tu8 *pwrtrk_tab_up_c = NULL, *pwrtrk_tab_down_c = NULL;\n\tu8 *pwrtrk_tab_up_d = NULL, *pwrtrk_tab_down_d = NULL;\n\tu8 *pwrtrk_tab_up_cck_c = NULL, *pwrtrk_tab_down_cck_c = NULL;\n\tu8 *pwrtrk_tab_up_cck_d = NULL, *pwrtrk_tab_down_cck_d = NULL;\n\ts8 thermal_value_temp = 0;\n\n#ifdef MP_TEST\n\tif ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {\n\t\tchannel = priv->pshare->working_channel;\n\t\tif (priv->pshare->mp_txpwr_tracking == false)\n\t\t\treturn;\n\t} else\n#endif\n\t{\n\t\tchannel = (priv->pmib->dot11RFEntry.dot11channel);\n\t}\n\n\tconfigure_txpower_track(dm, &c);\n\n\t(*c.get_delta_all_swing_table)(dm,\n\t\t(u8 **)&pwrtrk_tab_up_a, (u8 **)&pwrtrk_tab_down_a,\n\t\t(u8 **)&pwrtrk_tab_up_b, (u8 **)&pwrtrk_tab_down_b,\n\t\t(u8 **)&pwrtrk_tab_up_cck_a, (u8 **)&pwrtrk_tab_down_cck_a,\n\t\t(u8 **)&pwrtrk_tab_up_cck_b, (u8 **)&pwrtrk_tab_down_cck_b);\n\n\tif (GET_CHIP_VER(priv) == VERSION_8198F) {\n\t\t(*c.get_delta_all_swing_table_ex)(dm,\n\t\t\t(u8 **)&pwrtrk_tab_up_c, (u8 **)&pwrtrk_tab_down_c,\n\t\t\t(u8 **)&pwrtrk_tab_up_d, (u8 **)&pwrtrk_tab_down_d,\n\t\t\t(u8 **)&pwrtrk_tab_up_cck_c, (u8 **)&pwrtrk_tab_down_cck_c,\n\t\t\t(u8 **)&pwrtrk_tab_up_cck_d, (u8 **)&pwrtrk_tab_down_cck_d);\n\t}\n\t/*0x42: RF Reg[15:10] 88E*/\n\tthermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);\n#ifdef THER_TRIM\n\tif (GET_CHIP_VER(priv) == VERSION_8197F) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"orig thermal_value=%d, ther_trim_val=%d\\n\", thermal_value, priv->pshare->rf_ft_var.ther_trim_val);\n\n\t\tthermal_value += priv->pshare->rf_ft_var.ther_trim_val;\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"after thermal trim, thermal_value=%d\\n\", thermal_value);\n\t}\n\n\tif (GET_CHIP_VER(priv) == VERSION_8198F) {\n\t\tthermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"thermal_value_temp(%d) = ther_value(%d) + ther_trim_ther(%d)\\n\",\n\t\t       thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));\n\n\t\tif (thermal_value_temp > 63)\n\t\t\tthermal_value = 63;\n\t\telse if (thermal_value_temp < 0)\n\t\t\tthermal_value = 0;\n\t\telse\n\t\t\tthermal_value = thermal_value_temp;\n\t}\n#endif\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"\\n\\n\\nCurrent Thermal = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\\n\"\n\t\t, thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther);\n\n\t/* Initialize */\n\tif (!dm->rf_calibrate_info.thermal_value)\n\t\tdm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther;\n\n\tif (!dm->rf_calibrate_info.thermal_value_lck)\n\t\tdm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther;\n\n\tif (!dm->rf_calibrate_info.thermal_value_iqk)\n\t\tdm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther;\n\n\t/* calculate average thermal meter */\n\tdm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;\n\tdm->rf_calibrate_info.thermal_value_avg_index++;\n\n\tif (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/\n\t\tdm->rf_calibrate_info.thermal_value_avg_index = 0;\n\n\tfor (i = 0; i < c.average_thermal_num; i++) {\n\t\tif (dm->rf_calibrate_info.thermal_value_avg[i]) {\n\t\t\tthermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i];\n\t\t\tthermal_value_avg_count++;\n\t\t}\n\t}\n\n\tif (thermal_value_avg_count) {/*Calculate Average thermal_value after average enough times*/\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"thermal_value_avg=0x%x(%d)  thermal_value_avg_count = %d\\n\"\n\t\t\t, thermal_value_avg, thermal_value_avg, thermal_value_avg_count);\n\n\t\tthermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\\n\", thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther);\n\t}\n\n\t/*4 Calculate delta, delta_LCK, delta_IQK.*/\n\tdelta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);\n\tdelta_LCK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_lck);\n\tdelta_IQK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_iqk);\n\tis_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1);\n\n\tif (delta > 29) { /* power track table index(thermal diff.) upper bound*/\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"delta(%d) > 29, set delta to 29\\n\", delta);\n\t\tdelta = 29;\n\t}\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\\n\", delta, delta_LCK, delta_IQK);\n\n\t/*4 if necessary, do LCK.*/\n\tif ((delta_LCK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"delta_LCK(%d) >= threshold_iqk(%d)\\n\", delta_LCK, c.threshold_iqk);\n\t\tdm->rf_calibrate_info.thermal_value_lck = thermal_value;\n#if (RTL8822B_SUPPORT != 1)\n\t\tif (!(dm->support_ic_type & ODM_RTL8822B)) {\n\t\t\tif (c.phy_lc_calibrate)\n\t\t\t\t(*c.phy_lc_calibrate)(dm);\n\t\t}\n#endif\n\t}\n\n\tif (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/\n\t\treturn;\n\n\t/*4 Do Power Tracking*/\n\n\tif (thermal_value != dm->rf_calibrate_info.thermal_value) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"******** START POWER TRACKING ********\\n\");\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\\n\",\n\t\t       thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);\n\n#ifdef _TRACKING_TABLE_FILE\n\t\tif (priv->pshare->rf_ft_var.pwr_track_file) {\n\t\t\tif (is_increase) { /*thermal is higher than base*/\n\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\t\t\t\tswitch (p) {\n\t\t\t\t\tcase RF_PATH_B:\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"pwrtrk_tab_up_b[%d] = %d pwrtrk_tab_up_cck_b[%d] = %d\\n\", delta, pwrtrk_tab_up_b[delta], delta, pwrtrk_tab_up_cck_b[delta]);\n\t\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_b[delta];\n\t\t\t\t\t\tcali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_b[delta];\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);\n\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase RF_PATH_C:\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"pwrtrk_tab_up_c[%d] = %d pwrtrk_tab_up_cck_c[%d] = %d\\n\", delta, pwrtrk_tab_up_c[delta], delta, pwrtrk_tab_up_cck_c[delta]);\n\t\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_c[delta];\n\t\t\t\t\t\tcali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_c[delta];\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);\n\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase RF_PATH_D:\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"pwrtrk_tab_up_d[%d] = %d pwrtrk_tab_up_cck_d[%d] = %d\\n\", delta, pwrtrk_tab_up_d[delta], delta, pwrtrk_tab_up_cck_d[delta]);\n\t\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_d[delta];\n\t\t\t\t\t\tcali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_d[delta];\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tdefault:\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"pwrtrk_tab_up_a[%d] = %d pwrtrk_tab_up_cck_a[%d] = %d\\n\", delta, pwrtrk_tab_up_a[delta], delta, pwrtrk_tab_up_cck_a[delta]);\n\t\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_a[delta];\n\t\t\t\t\t\tcali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_a[delta];\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else { /* thermal is lower than base*/\n\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\t\t\t\tswitch (p) {\n\t\t\t\t\tcase RF_PATH_B:\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"pwrtrk_tab_down_b[%d] = %d   pwrtrk_tab_down_cck_b[%d] = %d\\n\", delta, pwrtrk_tab_down_b[delta], delta, pwrtrk_tab_down_cck_b[delta]);\n\t\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_b[delta];\n\t\t\t\t\t\tcali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_b[delta];\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d   pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);\n\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase RF_PATH_C:\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"pwrtrk_tab_down_c[%d] = %d   pwrtrk_tab_down_cck_c[%d] = %d\\n\", delta, pwrtrk_tab_down_c[delta], delta, pwrtrk_tab_down_cck_c[delta]);\n\t\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_c[delta];\n\t\t\t\t\t\tcali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_c[delta];\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d   pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);\n\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase RF_PATH_D:\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"pwrtrk_tab_down_d[%d] = %d   pwrtrk_tab_down_cck_d[%d] = %d\\n\", delta, pwrtrk_tab_down_d[delta], delta, pwrtrk_tab_down_cck_d[delta]);\n\t\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_d[delta];\n\t\t\t\t\t\tcali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_d[delta];\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d   pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);\n\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tdefault:\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"pwrtrk_tab_down_a[%d] = %d   pwrtrk_tab_down_cck_a[%d] = %d\\n\", delta, pwrtrk_tab_down_a[delta], delta, pwrtrk_tab_down_cck_a[delta]);\n\t\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_a[delta];\n\t\t\t\t\t\tcali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_a[delta];\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d   pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (is_increase) {\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \">>> increse power --->\\n\");\n\t\t\t\tif (GET_CHIP_VER(priv) == VERSION_8197F) {\n\t\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);\n\t\t\t\t//}  else if (GET_CHIP_VER(priv) == VERSION_8192F) {\n\t\t\t\t//\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t//\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t\t\t\t} else if (GET_CHIP_VER(priv) == VERSION_8822B) {\n\t\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t\t\t\t} else if (GET_CHIP_VER(priv) == VERSION_8821C) {\n\t\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t\t\t\t}  else if (GET_CHIP_VER(priv) == VERSION_8198F) {\n\t\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \">>> decrese power --->\\n\");\n\t\t\t\tif (GET_CHIP_VER(priv) == VERSION_8197F) {\n\t\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);\n\t\t\t\t//} else if (GET_CHIP_VER(priv) == VERSION_8192F) {\n\t\t\t\t//\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t//\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t\t\t\t} else if (GET_CHIP_VER(priv) == VERSION_8822B) {\n\t\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t\t\t\t} else if (GET_CHIP_VER(priv) == VERSION_8821C) {\n\t\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t\t\t\t} else if (GET_CHIP_VER(priv) == VERSION_8198F) {\n\t\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n#endif\n\n\t\tif (GET_CHIP_VER(priv) != VERSION_8198F) {\n\t\t\tif ((delta_IQK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"delta_IQK(%d) >= threshold_iqk(%d)\\n\", delta_IQK, c.threshold_iqk);\n\t\t\t\tdm->rf_calibrate_info.thermal_value_iqk = thermal_value;\n\t\t\t\tif (!(dm->support_ic_type & ODM_RTL8197F)) {\n\t\t\t\t\tif (c.do_iqk)\n\t\t\t\t\t\t(*c.do_iqk)(dm, false, thermal_value, 0);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"\\n******** END:%s() ********\\n\\n\", __func__);\n\t\t/*update thermal meter value*/\n\t\tdm->rf_calibrate_info.thermal_value =  thermal_value;\n\n\t}\n\n#endif\n}\n#endif\n\n/*#if (RTL8814A_SUPPORT == 1)*/\n#if (RTL8814A_SUPPORT == 1)\n\nvoid\nodm_txpowertracking_callback_thermal_meter_jaguar_series2(\n\tvoid\t\t*dm_void\n)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\tu8\t\t\tthermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase;\n\tu8\t\t\tthermal_value_avg_count = 0, p = 0, i = 0;\n\tu32\t\t\tthermal_value_avg = 0, reg0x18;\n\tu32\t\t\tbb_swing_reg[4] = {REG_A_TX_SCALE_JAGUAR, REG_B_TX_SCALE_JAGUAR, REG_C_TX_SCALE_JAGUAR2, REG_D_TX_SCALE_JAGUAR2};\n\ts32\t\t\tele_D;\n\tu32\t\t\tbb_swing_idx;\n\tstruct rtl8192cd_priv\t*priv = dm->priv;\n\tstruct txpwrtrack_cfg\tc;\n\tboolean\t\t\tis_tssi_enable = false;\n\tstruct dm_rf_calibration_struct\t*cali_info = &(dm->rf_calibrate_info);\n\tstruct dm_iqk_info\t*iqk_info = &dm->IQK_info;\n\n\t/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */\n\tu8\t\t\t*delta_swing_table_idx_tup_a = NULL, *delta_swing_table_idx_tdown_a = NULL;\n\tu8\t\t\t*delta_swing_table_idx_tup_b = NULL, *delta_swing_table_idx_tdown_b = NULL;\n\t/* for 8814 add by Yu Chen */\n\tu8\t\t\t*delta_swing_table_idx_tup_c = NULL, *delta_swing_table_idx_tdown_c = NULL;\n\tu8\t\t\t*delta_swing_table_idx_tup_d = NULL, *delta_swing_table_idx_tdown_d = NULL;\n\n#ifdef MP_TEST\n\tif ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {\n\t\tchannel = priv->pshare->working_channel;\n\t\tif (priv->pshare->mp_txpwr_tracking == false)\n\t\t\treturn;\n\t} else\n#endif\n\t{\n\t\tchannel = (priv->pmib->dot11RFEntry.dot11channel);\n\t}\n\n\tconfigure_txpower_track(dm, &c);\n\tcali_info->default_ofdm_index = priv->pshare->OFDM_index0[RF_PATH_A];\n\n\t(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,\n\t\t(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);\n\n\tif (dm->support_ic_type & ODM_RTL8814A)\t/* for 8814 path C & D */\n\t\t(*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,\n\t\t\t(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);\n\n\tthermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"\\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\\n\", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);\n\n\t/* Initialize */\n\tif (!dm->rf_calibrate_info.thermal_value)\n\t\tdm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther;\n\n\tif (!dm->rf_calibrate_info.thermal_value_lck)\n\t\tdm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther;\n\n\tif (!dm->rf_calibrate_info.thermal_value_iqk)\n\t\tdm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther;\n\n\tis_tssi_enable = (boolean)odm_get_rf_reg(dm, RF_PATH_A, REG_RF_TX_GAIN_OFFSET, BIT(7));\t/* check TSSI enable */\n\n\t/* 4 Query OFDM BB swing default setting \tBit[31:21] */\n\tfor (p = RF_PATH_A ; p < c.rf_path_count ; p++) {\n\t\tele_D = odm_get_bb_reg(dm, bb_swing_reg[p], 0xffe00000);\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"0x%x:0x%x ([31:21] = 0x%x)\\n\", bb_swing_reg[p], odm_get_bb_reg(dm, bb_swing_reg[p], MASKDWORD), ele_D);\n\n\t\tfor (bb_swing_idx = 0; bb_swing_idx < TXSCALE_TABLE_SIZE; bb_swing_idx++) {/* 4 */\n\t\t\tif (ele_D == tx_scaling_table_jaguar[bb_swing_idx]) {\n\t\t\t\tdm->rf_calibrate_info.OFDM_index[p] = (u8)bb_swing_idx;\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"OFDM_index[%d]=%d\\n\", p, dm->rf_calibrate_info.OFDM_index[p]);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"kfree_offset[%d]=%d\\n\", p, cali_info->kfree_offset[p]);\n\n\t}\n\n\t/* calculate average thermal meter */\n\tdm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;\n\tdm->rf_calibrate_info.thermal_value_avg_index++;\n\tif (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num)  /* Average times =  c.average_thermal_num */\n\t\tdm->rf_calibrate_info.thermal_value_avg_index = 0;\n\n\tfor (i = 0; i < c.average_thermal_num; i++) {\n\t\tif (dm->rf_calibrate_info.thermal_value_avg[i]) {\n\t\t\tthermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i];\n\t\t\tthermal_value_avg_count++;\n\t\t}\n\t}\n\n\tif (thermal_value_avg_count) {            /* Calculate Average thermal_value after average enough times */\n\t\tthermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\\n\", thermal_value, priv->pmib->dot11RFEntry.ther);\n\t}\n\n\t/* 4 Calculate delta, delta_LCK, delta_IQK. */\n\tdelta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);\n\tdelta_LCK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_lck);\n\tdelta_IQK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_iqk);\n\tis_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1);\n\n\t/* 4 if necessary, do LCK. */\n\tif (!(dm->support_ic_type & ODM_RTL8821)) {\n\t\tif ((delta_LCK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"delta_LCK(%d) >= threshold_iqk(%d)\\n\", delta_LCK, c.threshold_iqk);\n\t\t\tdm->rf_calibrate_info.thermal_value_lck = thermal_value;\n\n\t\t\t/*Use RTLCK, so close power tracking driver LCK*/\n#if (RTL8814A_SUPPORT != 1)\n\t\t\tif (!(dm->support_ic_type & ODM_RTL8814A)) {\n\t\t\t\tif (c.phy_lc_calibrate)\n\t\t\t\t\t(*c.phy_lc_calibrate)(dm);\n\t\t\t}\n#endif\n\t\t}\n\t}\n\n\tif ((delta_IQK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {\n\t\tpanic_printk(\"%s(%d)\\n\", __FUNCTION__, __LINE__);\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"delta_IQK(%d) >= threshold_iqk(%d)\\n\", delta_IQK, c.threshold_iqk);\n\t\tdm->rf_calibrate_info.thermal_value_iqk = thermal_value;\n\t\tif (c.do_iqk)\n\t\t\t(*c.do_iqk)(dm, true, 0, 0);\n\t}\n\n\tif (!priv->pmib->dot11RFEntry.ther)\t/*Don't do power tracking since no calibrated thermal value*/\n\t\treturn;\n\n\t/* 4 Do Power Tracking */\n\n\tif (is_tssi_enable == true) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter PURE TSSI MODE**********\\n\");\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0);\n\t} else if (thermal_value != dm->rf_calibrate_info.thermal_value) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"\\n******** START POWER TRACKING ********\\n\");\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"\\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\\n\", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);\n\n#ifdef _TRACKING_TABLE_FILE\n\t\tif (priv->pshare->rf_ft_var.pwr_track_file) {\n\t\t\tif (is_increase) {\t\t/* thermal is higher than base */\n\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\t\t\t\tswitch (p) {\n\t\t\t\t\tcase RF_PATH_B:\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"delta_swing_table_idx_tup_b[%d] = %d\\n\", delta, delta_swing_table_idx_tup_b[delta]);\n\t\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta];       /* Record delta swing for mix mode power tracking */\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase RF_PATH_C:\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"delta_swing_table_idx_tup_c[%d] = %d\\n\", delta, delta_swing_table_idx_tup_c[delta]);\n\t\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta];       /* Record delta swing for mix mode power tracking */\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase RF_PATH_D:\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"delta_swing_table_idx_tup_d[%d] = %d\\n\", delta, delta_swing_table_idx_tup_d[delta]);\n\t\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta];       /* Record delta swing for mix mode power tracking */\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tdefault:\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"delta_swing_table_idx_tup_a[%d] = %d\\n\", delta, delta_swing_table_idx_tup_a[delta]);\n\t\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta];        /* Record delta swing for mix mode power tracking */\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else {\t\t\t\t/* thermal is lower than base */\n\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\t\t\t\tswitch (p) {\n\t\t\t\t\tcase RF_PATH_B:\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"delta_swing_table_idx_tdown_b[%d] = %d\\n\", delta, delta_swing_table_idx_tdown_b[delta]);\n\t\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta];        /* Record delta swing for mix mode power tracking */\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase RF_PATH_C:\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"delta_swing_table_idx_tdown_c[%d] = %d\\n\", delta, delta_swing_table_idx_tdown_c[delta]);\n\t\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta];        /* Record delta swing for mix mode power tracking */\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase RF_PATH_D:\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"delta_swing_table_idx_tdown_d[%d] = %d\\n\", delta, delta_swing_table_idx_tdown_d[delta]);\n\t\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta];        /* Record delta swing for mix mode power tracking */\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tdefault:\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"delta_swing_table_idx_tdown_a[%d] = %d\\n\", delta, delta_swing_table_idx_tdown_a[delta]);\n\t\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta];        /* Record delta swing for mix mode power tracking */\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (is_increase) {\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \">>> increse power --->\\n\");\n\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t\t\t} else {\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \">>> decrese power --->\\n\");\n\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t\t\t}\n\t\t}\n#endif\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"\\n******** END:%s() ********\\n\", __FUNCTION__);\n\t\t/* update thermal meter value */\n\t\tdm->rf_calibrate_info.thermal_value =  thermal_value;\n\n\t}\n}\n#endif\n\n#if (RTL8812A_SUPPORT == 1 || RTL8881A_SUPPORT == 1)\nvoid\nodm_txpowertracking_callback_thermal_meter_jaguar_series(\n\tvoid\t\t*dm_void\n)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\tunsigned char\t\t\tthermal_value = 0, delta, delta_LCK, channel, is_decrease;\n\tunsigned char\t\t\tthermal_value_avg_count = 0;\n\tunsigned int\t\t\tthermal_value_avg = 0, reg0x18;\n\tunsigned int\t\t\tbb_swing_reg[4] = {0xc1c, 0xe1c, 0x181c, 0x1a1c};\n\tint\t\t\t\t\tele_D, value32;\n\tchar\t\t\t\t\tOFDM_index[2], index;\n\tunsigned int\t\t\ti = 0, j = 0, rf_path, max_rf_path = 2, rf;\n\tstruct rtl8192cd_priv\t\t*priv = dm->priv;\n\tunsigned char\t\t\tOFDM_min_index = 7; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur and Mimic */\n\tstruct dm_iqk_info\t*iqk_info = &dm->IQK_info;\n\n\n#ifdef MP_TEST\n\tif ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {\n\t\tchannel = priv->pshare->working_channel;\n\t\tif (priv->pshare->mp_txpwr_tracking == false)\n\t\t\treturn;\n\t} else\n#endif\n\t{\n\t\tchannel = (priv->pmib->dot11RFEntry.dot11channel);\n\t}\n\n#if RTL8881A_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8881A) {\n\t\tmax_rf_path = 1;\n\t\tif ((get_bonding_type_8881A() == BOND_8881AM || get_bonding_type_8881A() == BOND_8881AN)\n\t\t    && priv->pshare->rf_ft_var.use_intpa8881A && (*dm->band_type == ODM_BAND_2_4G))\n\t\t\tOFDM_min_index = 6;\t\t/* intPA - upper bond set to +3 dB (base: -2 dB)ot11RFEntry.phy_band_select == PHY_BAND_2G)) */\n\t\telse\n\t\t\tOFDM_min_index = 10;\t\t/* OFDM BB Swing should be less than +1dB, which is required by Arthur and Mimic */\n\t}\n#endif\n\n\n\tthermal_value = (unsigned char)phy_query_rf_reg(priv, RF_PATH_A, 0x42, 0xfc00, 1); /* 0x42: RF Reg[15:10] 88E */\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"\\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\\n\", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);\n\n\n\t/* 4 Query OFDM BB swing default setting \tBit[31:21] */\n\tfor (rf_path = 0 ; rf_path < max_rf_path ; rf_path++) {\n\t\tele_D = phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000);\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"0x%x:0x%x ([31:21] = 0x%x)\\n\", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], MASKDWORD), ele_D);\n\t\tfor (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */\n\t\t\tif (ele_D == ofdm_swing_table_8812[i]) {\n\t\t\t\tOFDM_index[rf_path] = (unsigned char)i;\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"OFDM_index[%d]=%d\\n\", rf_path, OFDM_index[rf_path]);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n#if 0\n\t/* Query OFDM path A default setting \tBit[31:21] */\n\tele_D = phy_query_bb_reg(priv, 0xc1c, 0xffe00000);\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"0xc1c:0x%x ([31:21] = 0x%x)\\n\", phy_query_bb_reg(priv, 0xc1c, MASKDWORD), ele_D);\n\tfor (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */\n\t\tif (ele_D == ofdm_swing_table_8812[i]) {\n\t\t\tOFDM_index[0] = (unsigned char)i;\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"OFDM_index[0]=%d\\n\", OFDM_index[0]);\n\t\t\tbreak;\n\t\t}\n\t}\n\t/* Query OFDM path B default setting */\n\tif (rf == 2) {\n\t\tele_D = phy_query_bb_reg(priv, 0xe1c, 0xffe00000);\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"0xe1c:0x%x ([32:21] = 0x%x)\\n\", phy_query_bb_reg(priv, 0xe1c, MASKDWORD), ele_D);\n\t\tfor (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {\n\t\t\tif (ele_D == ofdm_swing_table_8812[i]) {\n\t\t\t\tOFDM_index[1] = (unsigned char)i;\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"OFDM_index[1]=%d\\n\", OFDM_index[1]);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n#endif\n\t/* Initialize */\n\tif (!priv->pshare->thermal_value) {\n\t\tpriv->pshare->thermal_value = priv->pmib->dot11RFEntry.ther;\n\t\tpriv->pshare->thermal_value_lck = thermal_value;\n\t}\n\n\t/* calculate average thermal meter */\n\t{\n\t\tpriv->pshare->thermal_value_avg_8812[priv->pshare->thermal_value_avg_index_8812] = thermal_value;\n\t\tpriv->pshare->thermal_value_avg_index_8812++;\n\t\tif (priv->pshare->thermal_value_avg_index_8812 == AVG_THERMAL_NUM_8812)\n\t\t\tpriv->pshare->thermal_value_avg_index_8812 = 0;\n\n\t\tfor (i = 0; i < AVG_THERMAL_NUM_8812; i++) {\n\t\t\tif (priv->pshare->thermal_value_avg_8812[i]) {\n\t\t\t\tthermal_value_avg += priv->pshare->thermal_value_avg_8812[i];\n\t\t\t\tthermal_value_avg_count++;\n\t\t\t}\n\t\t}\n\n\t\tif (thermal_value_avg_count) {\n\t\t\tthermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count);\n\t\t\t/* printk(\"AVG Thermal Meter = 0x%x\\n\", thermal_value); */\n\t\t}\n\t}\n\n\n\t/* 4 If necessary,  do power tracking */\n\n\tif (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/\n\t\treturn;\n\n\tif (thermal_value != priv->pshare->thermal_value) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"\\n******** START POWER TRACKING ********\\n\");\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"\\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\\n\", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);\n\t\tdelta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);\n\t\tdelta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck);\n\t\tis_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0);\n\t\t/* if (*dm->band_type == ODM_BAND_5G) */\n\t\t{\n#ifdef _TRACKING_TABLE_FILE\n\t\t\tif (priv->pshare->rf_ft_var.pwr_track_file) {\n\t\t\t\tfor (rf_path = 0; rf_path < max_rf_path; rf_path++) {\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"diff: (%s)%d ==> get index from table : %d)\\n\", (is_decrease ? \"-\" : \"+\"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));\n\t\t\t\t\tif (is_decrease) {\n\t\t\t\t\t\tOFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] + get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0);\n\t\t\t\t\t\tOFDM_index[rf_path] = ((OFDM_index[rf_path] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[rf_path]);\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\\n\", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));\n#if 0/* RTL8881A_SUPPORT */\n\t\t\t\t\t\tif (dm->support_ic_type == ODM_RTL8881A) {\n\t\t\t\t\t\t\tif (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) {\n\t\t\t\t\t\t\t\tif (priv->pshare->add_tx_agc) { /* tx_agc has been added */\n\t\t\t\t\t\t\t\t\tadd_tx_power88xx_ac(priv, 0);\n\t\t\t\t\t\t\t\t\tpriv->pshare->add_tx_agc = 0;\n\t\t\t\t\t\t\t\t\tpriv->pshare->add_tx_agc_index = 0;\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n#endif\n\t\t\t\t\t} else {\n\n\t\t\t\t\t\tOFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] - get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0);\n#if 0/* RTL8881A_SUPPORT */\n\t\t\t\t\t\tif (dm->support_ic_type == ODM_RTL8881A) {\n\t\t\t\t\t\t\tif (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) {\n\t\t\t\t\t\t\t\tif (OFDM_index[i] < OFDM_min_index) {\n\t\t\t\t\t\t\t\t\tpriv->pshare->add_tx_agc_index = (OFDM_min_index - OFDM_index[i]) / 2; /* Calculate Remnant tx_agc value,  2 index for 1 tx_agc */\n\t\t\t\t\t\t\t\t\tadd_tx_power88xx_ac(priv, priv->pshare->add_tx_agc_index);\n\t\t\t\t\t\t\t\t\tpriv->pshare->add_tx_agc = 1;     /* add_tx_agc Flag = 1 */\n\t\t\t\t\t\t\t\t\tOFDM_index[i] = OFDM_min_index;\n\t\t\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t\t\tif (priv->pshare->add_tx_agc) { /* tx_agc been added */\n\t\t\t\t\t\t\t\t\t\tpriv->pshare->add_tx_agc = 0;\n\t\t\t\t\t\t\t\t\t\tpriv->pshare->add_tx_agc_index = 0;\n\t\t\t\t\t\t\t\t\t\tadd_tx_power88xx_ac(priv, 0); /* minus the added TPI */\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n#else\n\t\t\t\t\t\tOFDM_index[rf_path] = ((OFDM_index[rf_path] < OFDM_min_index) ?  OFDM_min_index : OFDM_index[rf_path]);\n#endif\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\\n\", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n#endif\n\t\t\t/* 4 Set new BB swing index */\n\t\t\tfor (rf_path = 0; rf_path < max_rf_path; rf_path++) {\n\t\t\t\tphy_set_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000, ofdm_swing_table_8812[(unsigned int)OFDM_index[rf_path]]);\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\\n\", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000), OFDM_index[rf_path]);\n\t\t\t}\n\n\t\t}\n\t\tif ((delta_LCK > 8) && (!iqk_info->rfk_forbidden)) {\n\t\t\tRTL_W8(0x522, 0xff);\n\t\t\treg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1);\n\t\t\tphy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1);\n\t\t\tphy_set_rf_reg(priv, RF_PATH_A, 0x18, BIT(15), 1);\n\t\t\tdelay_ms(200); /* frequency deviation */\n\t\t\tphy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 0);\n\t\t\tphy_set_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, reg0x18);\n#ifdef CONFIG_RTL_8812_SUPPORT\n\t\t\tif (GET_CHIP_VER(priv) == VERSION_8812E)\n\t\t\t\tupdate_bbrf_val8812(priv, priv->pmib->dot11RFEntry.dot11channel);\n#endif\n\t\t\tRTL_W8(0x522, 0x0);\n\t\t\tpriv->pshare->thermal_value_lck = thermal_value;\n\t\t}\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"\\n******** END:%s() ********\\n\", __FUNCTION__);\n\n\t\t/* update thermal meter value */\n\t\tpriv->pshare->thermal_value = thermal_value;\n\t\tfor (rf_path = 0; rf_path < max_rf_path; rf_path++)\n\t\t\tpriv->pshare->OFDM_index[rf_path] = OFDM_index[rf_path];\n\t}\n}\n\n#endif\n\n\nvoid\nodm_txpowertracking_callback_thermal_meter(\n\tvoid\t\t*dm_void\n)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct\t*cali_info = &(dm->rf_calibrate_info);\n\tstruct dm_iqk_info\t*iqk_info = &dm->IQK_info;\n\n\t\n#if (RTL8814B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8814B) {\n\t\todm_txpowertracking_callback_thermal_meter_jaguar_series4(dm);\n\t}\n#endif\n#if (RTL8197F_SUPPORT == 1 ||RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8197F || dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8822B\n\t\t|| dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8198F) {\n\t\todm_txpowertracking_callback_thermal_meter_jaguar_series3(dm);\n\t\treturn;\n\t}\n#endif\n#if (RTL8814A_SUPPORT == 1)\t\t/*use this function to do power tracking after 8814 by YuChen*/\n\tif (dm->support_ic_type & ODM_RTL8814A) {\n\t\todm_txpowertracking_callback_thermal_meter_jaguar_series2(dm);\n\t\treturn;\n\t}\n#endif\n#if (RTL8881A_SUPPORT || RTL8812A_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8812 || dm->support_ic_type & ODM_RTL8881A) {\n\t\todm_txpowertracking_callback_thermal_meter_jaguar_series(dm);\n\t\treturn;\n\t}\n#endif\n\n#if (RTL8192E_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8192E) {\n\t\todm_txpowertracking_callback_thermal_meter_92e(dm);\n\t\treturn;\n\t}\n#endif\n\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\n\tHAL_DATA_TYPE\t*hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\t/* PMGNT_INFO      \t\tmgnt_info = &adapter->mgnt_info; */\n#endif\n\n\n\tu8\t\t\tthermal_value = 0, delta, delta_LCK, delta_IQK, offset;\n\tu8\t\t\tthermal_value_avg_count = 0;\n\tu32\t\t\tthermal_value_avg = 0;\n\t/*\ts32\t\t\tele_A=0, ele_D, TempCCk, X, value32;\n\t *\ts32\t\t\tY, ele_C=0;\n\t *\ts8\t\t\tOFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index;\n\t *\ts8\t\t\tdeltaPowerIndex = 0; */\n\tu32\t\t\ti = 0;/* , j = 0; */\n\tboolean\t\tis2T = false;\n\t/*\tbool \t\tbInteralPA = false; */\n\n\tu8\t\t\tOFDM_max_index = 34, rf = (is2T) ? 2 : 1; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */\n\tu8\t\t\tindexforchannel = 0;/*get_right_chnl_place_for_iqk(hal_data->current_channel)*/\n\tenum            _POWER_DEC_INC { POWER_DEC, POWER_INC };\n\n\tstruct txpwrtrack_cfg\tc;\n\n\n\t/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */\n\ts8\t\t\tdelta_swing_table_idx[2][index_mapping_NUM_88E] = {\n\t\t/* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */\n\t\t{0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11}, {0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 7, 8, 9, 9, 10}\n\t};\n\tu8\t\t\tthermal_threshold[2][index_mapping_NUM_88E] = {\n\t\t/* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */\n\t\t{0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 27}, {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 25, 25}\n\t};\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\tstruct rtl8192cd_priv\t*priv = dm->priv;\n#endif\n\n\t/* 4 2. Initilization ( 7 steps in total ) */\n\n\tconfigure_txpower_track(dm, &c);\n\n\tdm->rf_calibrate_info.txpowertracking_callback_cnt++; /* cosa add for debug */\n\tdm->rf_calibrate_info.is_txpowertracking_init = true;\n\n#if (MP_DRIVER == 1)\n\tdm->rf_calibrate_info.txpowertrack_control = hal_data->txpowertrack_control; /* <Kordan> We should keep updating the control variable according to HalData.\n     * <Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */\n\tdm->rf_calibrate_info.rega24 = 0x090e1317;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(MP_TEST)\n\tif ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {\n\t\tif (dm->priv->pshare->mp_txpwr_tracking == false)\n\t\t\treturn;\n\t}\n#endif\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"===>odm_txpowertracking_callback_thermal_meter_8188e, dm->bb_swing_idx_cck_base: %d, dm->bb_swing_idx_ofdm_base: %d\\n\", cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base);\n\t/*\n\t\tif (!dm->rf_calibrate_info.tm_trigger) {\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, BIT(17) | BIT(16), 0x3);\n\t\t\tdm->rf_calibrate_info.tm_trigger = 1;\n\t\t\treturn;\n\t\t}\n\t*/\n\tthermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);\t/* 0x42: RF Reg[15:10] 88E */\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\n\tif (!thermal_value || !dm->rf_calibrate_info.txpowertrack_control)\n#else\n\tif (!dm->rf_calibrate_info.txpowertrack_control)\n#endif\n\t\treturn;\n\n\t/* 4 3. Initialize ThermalValues of rf_calibrate_info */\n\n\tif (!dm->rf_calibrate_info.thermal_value) {\n\t\tdm->rf_calibrate_info.thermal_value_lck = thermal_value;\n\t\tdm->rf_calibrate_info.thermal_value_iqk = thermal_value;\n\t}\n\n\tif (dm->rf_calibrate_info.is_reloadtxpowerindex)\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"reload ofdm index for band switch\\n\");\n\n\t/* 4 4. Calculate average thermal meter */\n\n\tdm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;\n\tdm->rf_calibrate_info.thermal_value_avg_index++;\n\tif (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num)\n\t\tdm->rf_calibrate_info.thermal_value_avg_index = 0;\n\n\tfor (i = 0; i < c.average_thermal_num; i++) {\n\t\tif (dm->rf_calibrate_info.thermal_value_avg[i]) {\n\t\t\tthermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i];\n\t\t\tthermal_value_avg_count++;\n\t\t}\n\t}\n\n\tif (thermal_value_avg_count) {\n\t\t/* Give the new thermo value a weighting */\n\t\tthermal_value_avg += (thermal_value * 4);\n\n\t\tthermal_value = (u8)(thermal_value_avg / (thermal_value_avg_count + 4));\n\t\tcali_info->thermal_value_delta = thermal_value - priv->pmib->dot11RFEntry.ther;\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"AVG Thermal Meter = 0x%x\\n\", thermal_value);\n\t}\n\n\t/* 4 5. Calculate delta, delta_LCK, delta_IQK. */\n\n\tdelta\t  = (thermal_value > dm->rf_calibrate_info.thermal_value) ? (thermal_value - dm->rf_calibrate_info.thermal_value) : (dm->rf_calibrate_info.thermal_value - thermal_value);\n\tdelta_LCK = (thermal_value > dm->rf_calibrate_info.thermal_value_lck) ? (thermal_value - dm->rf_calibrate_info.thermal_value_lck) : (dm->rf_calibrate_info.thermal_value_lck - thermal_value);\n\tdelta_IQK = (thermal_value > dm->rf_calibrate_info.thermal_value_iqk) ? (thermal_value - dm->rf_calibrate_info.thermal_value_iqk) : (dm->rf_calibrate_info.thermal_value_iqk - thermal_value);\n\n\t/* 4 6. If necessary, do LCK. */\n\tif (!(dm->support_ic_type & ODM_RTL8821)) {\n\t\t/*if((delta_LCK > hal_data->delta_lck) && (hal_data->delta_lck != 0))*/\n\t\tif ((delta_LCK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {\n\t\t\t/*Delta temperature is equal to or larger than 20 centigrade.*/\n\t\t\tdm->rf_calibrate_info.thermal_value_lck = thermal_value;\n\t\t\t(*c.phy_lc_calibrate)(dm);\n\t\t}\n\t}\n\n\t/* 3 7. If necessary, move the index of swing table to adjust Tx power. */\n\n\tif (delta > 0 && dm->rf_calibrate_info.txpowertrack_control) {\n\n\t\tdelta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value);\n\n\t\t/* 4 7.1 The Final Power index = BaseIndex + power_index_offset */\n\n\t\tif (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {\n\t\t\tCALCULATE_SWINGTALBE_OFFSET(offset, POWER_INC, index_mapping_NUM_88E, delta);\n\t\t\tdm->rf_calibrate_info.delta_power_index_last = dm->rf_calibrate_info.delta_power_index;\n\t\t\tdm->rf_calibrate_info.delta_power_index =  delta_swing_table_idx[POWER_INC][offset];\n\n\t\t} else {\n\n\t\t\tCALCULATE_SWINGTALBE_OFFSET(offset, POWER_DEC, index_mapping_NUM_88E, delta);\n\t\t\tdm->rf_calibrate_info.delta_power_index_last = dm->rf_calibrate_info.delta_power_index;\n\t\t\tdm->rf_calibrate_info.delta_power_index = (-1) * delta_swing_table_idx[POWER_DEC][offset];\n\t\t}\n\n\t\tif (dm->rf_calibrate_info.delta_power_index == dm->rf_calibrate_info.delta_power_index_last)\n\t\t\tdm->rf_calibrate_info.power_index_offset = 0;\n\t\telse\n\t\t\tdm->rf_calibrate_info.power_index_offset = dm->rf_calibrate_info.delta_power_index - dm->rf_calibrate_info.delta_power_index_last;\n\n\t\tfor (i = 0; i < rf; i++)\n\t\t\tdm->rf_calibrate_info.OFDM_index[i] = cali_info->bb_swing_idx_ofdm_base + dm->rf_calibrate_info.power_index_offset;\n\t\tdm->rf_calibrate_info.CCK_index = cali_info->bb_swing_idx_cck_base + dm->rf_calibrate_info.power_index_offset;\n\n\t\tcali_info->bb_swing_idx_cck = dm->rf_calibrate_info.CCK_index;\n\t\tcali_info->bb_swing_idx_ofdm[RF_PATH_A] = dm->rf_calibrate_info.OFDM_index[RF_PATH_A];\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\\n\", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, dm->rf_calibrate_info.power_index_offset);\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"The 'OFDM' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\\n\", cali_info->bb_swing_idx_ofdm[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base, dm->rf_calibrate_info.power_index_offset);\n\n\t\t/* 4 7.1 Handle boundary conditions of index. */\n\n\n\t\tfor (i = 0; i < rf; i++) {\n\t\t\tif (dm->rf_calibrate_info.OFDM_index[i] > OFDM_max_index)\n\t\t\t\tdm->rf_calibrate_info.OFDM_index[i] = OFDM_max_index;\n\t\t\telse if (dm->rf_calibrate_info.OFDM_index[i] < 0)\n\t\t\t\tdm->rf_calibrate_info.OFDM_index[i] = 0;\n\t\t}\n\n\t\tif (dm->rf_calibrate_info.CCK_index > c.swing_table_size_cck - 1)\n\t\t\tdm->rf_calibrate_info.CCK_index = c.swing_table_size_cck - 1;\n\t\telse if (dm->rf_calibrate_info.CCK_index < 0)\n\t\t\tdm->rf_calibrate_info.CCK_index = 0;\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"The thermal meter is unchanged or TxPowerTracking OFF: thermal_value: %d, dm->rf_calibrate_info.thermal_value: %d)\\n\", thermal_value, dm->rf_calibrate_info.thermal_value);\n\t\tdm->rf_calibrate_info.power_index_offset = 0;\n\t}\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\\n\", dm->rf_calibrate_info.CCK_index, cali_info->bb_swing_idx_cck_base);\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index: %d\\n\", dm->rf_calibrate_info.OFDM_index[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base);\n\n\tif (dm->rf_calibrate_info.power_index_offset != 0 && dm->rf_calibrate_info.txpowertrack_control) {\n\t\t/* 4 7.2 Configure the Swing Table to adjust Tx Power. */\n\n\t\tdm->rf_calibrate_info.is_tx_power_changed = true; /* Always true after Tx Power is adjusted by power tracking. */\n\t\t/*  */\n\t\t/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */\n\t\t/* to increase TX power. Otherwise, EVM will be bad. */\n\t\t/*  */\n\t\t/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */\n\t\tif (thermal_value > dm->rf_calibrate_info.thermal_value) {\n\t\t\t/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK, */\n\t\t\t/*\t\"Temperature Increasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\\n\", */\n\t\t\t/*\tdm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */\n\t\t} else if (thermal_value < dm->rf_calibrate_info.thermal_value) { /* Low temperature */\n\t\t\t/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK, */\n\t\t\t/*\t\"Temperature Decreasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\\n\", */\n\t\t\t/*\t\tdm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */\n\t\t}\n\t\tif (thermal_value > dm->priv->pmib->dot11RFEntry.ther)\n\t\t{\n\t\t\t/*\t\t\t\tRF_DBG(dm,DBG_RF_TX_PWR_TRACK,\"Temperature(%d) hugher than PG value(%d), increases the power by tx_agc\\n\", thermal_value, hal_data->eeprom_thermal_meter); */\n\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, TXAGC, 0, 0);\n\t\t} else {\n\t\t\t/*\t\t\tRF_DBG(dm,DBG_RF_TX_PWR_TRACK,\"Temperature(%d) lower than PG value(%d), increases the power by tx_agc\\n\", thermal_value, hal_data->eeprom_thermal_meter); */\n\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_A, indexforchannel);\n\t\t\tif (is2T)\n\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_B, indexforchannel);\n\t\t}\n\n\t\tcali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;\n\t\tcali_info->bb_swing_idx_ofdm_base = cali_info->bb_swing_idx_ofdm[RF_PATH_A];\n\t\tdm->rf_calibrate_info.thermal_value = thermal_value;\n\n\t}\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\\n\");\n\n\tdm->rf_calibrate_info.tx_powercount = 0;\n}\n\n/* 3============================================================\n * 3 IQ Calibration\n * 3============================================================ */\n\nvoid\nodm_reset_iqk_result(\n\tvoid\t\t*dm_void\n)\n{\n\treturn;\n}\n#if 1/* !(DM_ODM_SUPPORT_TYPE & ODM_AP) */\nu8 odm_get_right_chnl_place_for_iqk(u8 chnl)\n{\n\tu8\tchannel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {\n\t\t1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165\n\t};\n\tu8\tplace = chnl;\n\n\n\tif (chnl > 14) {\n\t\tfor (place = 14; place < sizeof(channel_all); place++) {\n\t\t\tif (channel_all[place] == chnl)\n\t\t\t\treturn place - 13;\n\t\t}\n\t}\n\treturn 0;\n\n}\n#endif\n\nvoid\nodm_iq_calibrate(\n\tstruct dm_struct\t*dm\n)\n{\n\tstruct dm_iqk_info\t*iqk_info = &dm->IQK_info;\n\n\tif ((dm->is_linked) && (!iqk_info->rfk_forbidden)) {\n\t\tif ((*dm->channel != dm->pre_channel) && (!*dm->is_scan_in_process)) {\n\t\t\tdm->pre_channel = *dm->channel;\n\t\t\tdm->linked_interval = 0;\n\t\t}\n\n\t\tif (dm->linked_interval < 3)\n\t\t\tdm->linked_interval++;\n\n\t\tif (dm->linked_interval == 2)\n\t\t\thalrf_iqk_trigger(dm, false);\n\t} else\n\t\tdm->linked_interval = 0;\n\n}\n\nvoid phydm_rf_init(void\t\t*dm_void)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\todm_txpowertracking_init(dm);\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n#if (RTL8814A_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8814A)\n\t\tphy_iq_calibrate_8814a_init(dm);\n#endif\n#endif\n\n}\n\nvoid phydm_rf_watchdog(void\t\t*dm_void)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\n\todm_txpowertracking_check(dm);\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES)\n\t\todm_iq_calibrate(dm);\n#endif\n}\n"
  },
  {
    "path": "hal/phydm/halrf/halphyrf_ap.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef __HALPHYRF_H__\n#define __HALPHYRF_H__\n\n#include \"halrf/halrf_powertracking_ap.h\"\n#include \"halrf/halrf_kfree.h\"\n\n#if (RTL8814A_SUPPORT == 1)\n\t#include \"halrf/rtl8814a/halrf_iqk_8814a.h\"\n#endif\n\n#if (RTL8822B_SUPPORT == 1)\n\t#include \"halrf/rtl8822b/halrf_iqk_8822b.h\"\n#endif\n\n#if (RTL8821C_SUPPORT == 1)\n\t#include \"halrf/rtl8821c/halrf_iqk_8821c.h\"\n#endif\n\n#if (RTL8195B_SUPPORT == 1)\n//\t#include \"halrf/rtl8195b/halrf.h\"\n\t#include \"halrf/rtl8195b/halrf_iqk_8195b.h\"\n\t#include \"halrf/rtl8195b/halrf_txgapk_8195b.h\"\n\t#include \"halrf/rtl8195b/halrf_dpk_8195b.h\"\n#endif\n\n#if (RTL8198F_SUPPORT == 1)\n\t#include \"halrf/rtl8198f/halrf_iqk_8198f.h\"\n\t#include \"halrf/rtl8198f/halrf_dpk_8198f.h\"\n#endif\n\n#if (RTL8812F_SUPPORT == 1)\n\t#include \"halrf/rtl8812f/halrf_iqk_8812f.h\"\n\t#include \"halrf/rtl8812f/halrf_dpk_8812f.h\"\n\t#include \"halrf/rtl8812f/halrf_tssi_8812f.h\"\n#endif\n\n#if (RTL8814B_SUPPORT == 1)\n\t#include \"halrf/rtl8814b/halrf_iqk_8814b.h\"\t\n\t#include \"halrf/rtl8814b/halrf_dpk_8814b.h\"\n#endif\n\nenum pwrtrack_method {\n\tBBSWING,\n\tTXAGC,\n\tMIX_MODE,\n\tTSSI_MODE,\n\tMIX_2G_TSSI_5G_MODE,\n\tMIX_5G_TSSI_2G_MODE,\n\tCLEAN_MODE\n};\n\ntypedef void\t(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);\ntypedef void(*func_iqk)(void *, u8, u8, u8);\ntypedef void\t(*func_lck)(void *);\n/* refine by YuChen for 8814A */\ntypedef void\t(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);\ntypedef void\t(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);\ntypedef void\t(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);\ntypedef void\t(*func_all_swing_ex)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);\n\nstruct txpwrtrack_cfg {\n\tu8\t\tswing_table_size_cck;\n\tu8\t\tswing_table_size_ofdm;\n\tu8\t\tthreshold_iqk;\n\tu8\t\tthreshold_dpk;\n\tu8\t\taverage_thermal_num;\n\tu8\t\trf_path_count;\n\tu32\t\tthermal_reg_addr;\n\tfunc_set_pwr\todm_tx_pwr_track_set_pwr;\n\tfunc_iqk\tdo_iqk;\n\tfunc_lck\t\tphy_lc_calibrate;\n\tfunc_swing\tget_delta_swing_table;\n\tfunc_swing8814only\tget_delta_swing_table8814only;\n\tfunc_all_swing\t\tget_delta_all_swing_table;\n\tfunc_all_swing_ex\tget_delta_all_swing_table_ex;\n};\n\nvoid\nodm_clear_txpowertracking_state(\n\tvoid *dm_void\n);\n\nvoid\nconfigure_txpower_track(\n\tvoid\t\t*dm_void,\n\tstruct txpwrtrack_cfg\t*config\n);\n\n\nvoid\nodm_txpowertracking_callback_thermal_meter(\n\tvoid\t\t*dm_void\n);\n\n#if (RTL8192E_SUPPORT == 1)\nvoid\nodm_txpowertracking_callback_thermal_meter_92e(\n\tvoid\t\t*dm_void\n);\n#endif\n\n#if (RTL8814A_SUPPORT == 1)\nvoid\nodm_txpowertracking_callback_thermal_meter_jaguar_series2(\n\tvoid\t\t*dm_void\n);\n\n#elif ODM_IC_11AC_SERIES_SUPPORT\nvoid\nodm_txpowertracking_callback_thermal_meter_jaguar_series(\n\tvoid\t\t*dm_void\n);\n\n#elif (RTL8197F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\\\n\tRTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)\nvoid\nodm_txpowertracking_callback_thermal_meter_jaguar_series3(\n\tvoid\t\t*dm_void\n);\n\n#elif (RTL8814B_SUPPORT == 1)\nvoid\nodm_txpowertracking_callback_thermal_meter_jaguar_series4(\n\tvoid\t\t*dm_void\n);\n\n#endif\n\n#define IS_CCK_RATE(_rate)\t\t\t\t(ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M)\n\n#define ODM_TARGET_CHNL_NUM_2G_5G\t59\n\n\nvoid\nodm_reset_iqk_result(\n\tvoid\t\t*dm_void\n);\nu8\nodm_get_right_chnl_place_for_iqk(\n\tu8 chnl\n);\n\nvoid phydm_rf_init(void\t\t*dm_void);\nvoid phydm_rf_watchdog(void\t\t*dm_void);\n\n#endif\t/*#ifndef __HALPHYRF_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/halphyrf_ce.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal)\\\n\tdo {                                                                   \\\n\t\tu32 __offset = (u32)_offset;                                   \\\n\t\tu32 __size = (u32)_size;                                       \\\n\t\tfor (__offset = 0; __offset < __size; __offset++) {            \\\n\t\t\tif (_delta_thermal <                                   \\\n\t\t\t\tthermal_threshold[_direction][__offset]) {     \\\n\t\t\t\tif (__offset != 0)                             \\\n\t\t\t\t\t__offset--;                            \\\n\t\t\t\tbreak;                                         \\\n\t\t\t}                                                      \\\n\t\t}                                                              \\\n\t\tif (__offset >= __size)                                        \\\n\t\t\t__offset = __size - 1;                                 \\\n\t} while (0)\n\nvoid configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if RTL8192E_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8192E)\n\t\tconfigure_txpower_track_8192e(config);\n#endif\n#if RTL8821A_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8821)\n\t\tconfigure_txpower_track_8821a(config);\n#endif\n#if RTL8812A_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8812)\n\t\tconfigure_txpower_track_8812a(config);\n#endif\n#if RTL8188E_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8188E)\n\t\tconfigure_txpower_track_8188e(config);\n#endif\n\n#if RTL8723B_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8723B)\n\t\tconfigure_txpower_track_8723b(config);\n#endif\n\n#if RTL8814A_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8814A)\n\t\tconfigure_txpower_track_8814a(config);\n#endif\n\n#if RTL8703B_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8703B)\n\t\tconfigure_txpower_track_8703b(config);\n#endif\n\n#if RTL8188F_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8188F)\n\t\tconfigure_txpower_track_8188f(config);\n#endif\n#if RTL8723D_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8723D)\n\t\tconfigure_txpower_track_8723d(config);\n#endif\n/*@ JJ ADD 20161014 */\n#if RTL8710B_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8710B)\n\t\tconfigure_txpower_track_8710b(config);\n#endif\n#if RTL8822B_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8822B)\n\t\tconfigure_txpower_track_8822b(config);\n#endif\n#if RTL8821C_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8821C)\n\t\tconfigure_txpower_track_8821c(config);\n#endif\n\n#if RTL8192F_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8192F)\n\t\tconfigure_txpower_track_8192f(config);\n#endif\n\n#if RTL8822C_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8822C)\n\t\tconfigure_txpower_track_8822c(config);\n#endif\n\n}\n\n/*@ **********************************************************************\n * <20121113, Kordan> This function should be called when tx_agc changed.\n * Otherwise the previous compensation is gone, because we record the\n * delta of temperature between two TxPowerTracking watch dogs.\n *\n * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still\n * need to call this function.\n * **********************************************************************\n */\nvoid odm_clear_txpowertracking_state(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tu8 p = 0;\n\tstruct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;\n\n\tcali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;\n\tcali_info->bb_swing_idx_cck = cali_info->default_cck_index;\n\tdm->rf_calibrate_info.CCK_index = 0;\n\n\tfor (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {\n\t\tcali_info->bb_swing_idx_ofdm_base[p]\n\t\t\t\t\t\t= cali_info->default_ofdm_index;\n\t\tcali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;\n\t\tcali_info->OFDM_index[p] = cali_info->default_ofdm_index;\n\n\t\tcali_info->power_index_offset[p] = 0;\n\t\tcali_info->delta_power_index[p] = 0;\n\t\tcali_info->delta_power_index_last[p] = 0;\n\n\t\t/* Initial Mix mode power tracking*/\n\t\tcali_info->absolute_ofdm_swing_idx[p] = 0;\n\t\tcali_info->remnant_ofdm_swing_idx[p] = 0;\n\t\tcali_info->kfree_offset[p] = 0;\n\t}\n\t/* Initial Mix mode power tracking*/\n\tcali_info->modify_tx_agc_flag_path_a = false;\n\tcali_info->modify_tx_agc_flag_path_b = false;\n\tcali_info->modify_tx_agc_flag_path_c = false;\n\tcali_info->modify_tx_agc_flag_path_d = false;\n\tcali_info->remnant_cck_swing_idx = 0;\n\tcali_info->thermal_value = rf->eeprom_thermal;\n\tcali_info->modify_tx_agc_value_cck = 0;\n\tcali_info->modify_tx_agc_value_ofdm = 0;\n}\n\nvoid odm_get_tracking_table(void *dm_void, u8 thermal_value, u8 delta)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct txpwrtrack_cfg c = {0};\n\n\tu8 p;\n\t/* 4 1. TWO tables decide the final index of OFDM/CCK swing table. */\n\tu8 *pwrtrk_tab_up_a = NULL;\n\tu8 *pwrtrk_tab_down_a = NULL;\n\tu8 *pwrtrk_tab_up_b = NULL;\n\tu8 *pwrtrk_tab_down_b = NULL;\n\t/*for 8814 add by Yu Chen*/\n\tu8 *pwrtrk_tab_up_c = NULL;\n\tu8 *pwrtrk_tab_down_c = NULL;\n\tu8 *pwrtrk_tab_up_d = NULL;\n\tu8 *pwrtrk_tab_down_d = NULL;\n\t/*for Xtal Offset by James.Tung*/\n\ts8 *xtal_tab_up = NULL;\n\ts8 *xtal_tab_down = NULL;\n\n\tconfigure_txpower_track(dm, &c);\n\n\t(*c.get_delta_swing_table)(dm,\n\t\t\t\t   (u8 **)&pwrtrk_tab_up_a,\n\t\t\t\t   (u8 **)&pwrtrk_tab_down_a,\n\t\t\t\t   (u8 **)&pwrtrk_tab_up_b,\n\t\t\t\t   (u8 **)&pwrtrk_tab_down_b);\n\n\tif (dm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/\n\t\t(*c.get_delta_swing_table8814only)(dm,\n\t\t\t\t\t\t   (u8 **)&pwrtrk_tab_up_c,\n\t\t\t\t\t\t   (u8 **)&pwrtrk_tab_down_c,\n\t\t\t\t\t\t   (u8 **)&pwrtrk_tab_up_d,\n\t\t\t\t\t\t   (u8 **)&pwrtrk_tab_down_d);\n\t/*for Xtal Offset*/\n\tif (dm->support_ic_type &\n\t    (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F))\n\t\t(*c.get_delta_swing_xtal_table)(dm,\n\t\t\t\t\t\t(s8 **)&xtal_tab_up,\n\t\t\t\t\t\t(s8 **)&xtal_tab_down);\n\n\tif (thermal_value > rf->eeprom_thermal) {\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\t\t/*recording power index offset*/\n\t\t\tcali_info->delta_power_index_last[p] =\n\t\t\t\t\tcali_info->delta_power_index[p];\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"******Temp is higher******\\n\");\n\t\t\tswitch (p) {\n\t\t\tcase RF_PATH_B:\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"pwrtrk_tab_up_b[%d] = %d\\n\", delta,\n\t\t\t\t       pwrtrk_tab_up_b[delta]);\n\n\t\t\t\tcali_info->delta_power_index[p] =\n\t\t\t\t\t\t\tpwrtrk_tab_up_b[delta];\n\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =\n\t\t\t\t\t\t\tpwrtrk_tab_up_b[delta];\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"absolute_ofdm_swing_idx[PATH_B] = %d\\n\",\n\t\t\t\t       cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\tbreak;\n\n\t\t\tcase RF_PATH_C:\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"pwrtrk_tab_up_c[%d] = %d\\n\", delta,\n\t\t\t\t       pwrtrk_tab_up_c[delta]);\n\n\t\t\t\tcali_info->delta_power_index[p] =\n\t\t\t\t\t\t\tpwrtrk_tab_up_c[delta];\n\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =\n\t\t\t\t\t\t\tpwrtrk_tab_up_c[delta];\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"absolute_ofdm_swing_idx[PATH_C] = %d\\n\",\n\t\t\t\t       cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\tbreak;\n\n\t\t\tcase RF_PATH_D:\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"pwrtrk_tab_up_d[%d] = %d\\n\", delta,\n\t\t\t\t       pwrtrk_tab_up_d[delta]);\n\n\t\t\t\tcali_info->delta_power_index[p] =\n\t\t\t\t\t\t\tpwrtrk_tab_up_d[delta];\n\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =\n\t\t\t\t\t\t\tpwrtrk_tab_up_d[delta];\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"absolute_ofdm_swing_idx[PATH_D] = %d\\n\",\n\t\t\t\t       cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\tbreak;\n\n\t\t\tdefault:\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"pwrtrk_tab_up_a[%d] = %d\\n\", delta,\n\t\t\t\t       pwrtrk_tab_up_a[delta]);\n\n\t\t\t\tcali_info->delta_power_index[p] =\n\t\t\t\t\t\t\tpwrtrk_tab_up_a[delta];\n\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =\n\t\t\t\t\t\t\tpwrtrk_tab_up_a[delta];\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"absolute_ofdm_swing_idx[PATH_A] = %d\\n\",\n\t\t\t\t       cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* @JJ ADD 20161014 */\n\t\t/*Save xtal_offset from Xtal table*/\n\t\tif (dm->support_ic_type &\n\t\t    (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B |\n\t\t    ODM_RTL8192F)) {\n\t\t\t/*recording last Xtal offset*/\n\t\t\tcali_info->xtal_offset_last = cali_info->xtal_offset;\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"[Xtal] xtal_tab_up[%d] = %d\\n\",\n\t\t\t       delta, xtal_tab_up[delta]);\n\t\t\tcali_info->xtal_offset = xtal_tab_up[delta];\n\t\t\tif (cali_info->xtal_offset_last != xtal_tab_up[delta])\n\t\t\t\tcali_info->xtal_offset_eanble = 1;\n\t\t}\n\t} else {\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\t\t/*recording power index offset*/\n\t\t\tcali_info->delta_power_index_last[p] =\n\t\t\t\t\t\tcali_info->delta_power_index[p];\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"******Temp is lower******\\n\");\n\t\t\tswitch (p) {\n\t\t\tcase RF_PATH_B:\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"pwrtrk_tab_down_b[%d] = %d\\n\", delta,\n\t\t\t\t       pwrtrk_tab_down_b[delta]);\n\t\t\t\tcali_info->delta_power_index[p] =\n\t\t\t\t\t\t-1 * pwrtrk_tab_down_b[delta];\n\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =\n\t\t\t\t\t\t-1 * pwrtrk_tab_down_b[delta];\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"absolute_ofdm_swing_idx[PATH_B] = %d\\n\",\n\t\t\t\t       cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\tbreak;\n\n\t\t\tcase RF_PATH_C:\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"pwrtrk_tab_down_c[%d] = %d\\n\", delta,\n\t\t\t\t       pwrtrk_tab_down_c[delta]);\n\t\t\t\tcali_info->delta_power_index[p] =\n\t\t\t\t\t\t-1 * pwrtrk_tab_down_c[delta];\n\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =\n\t\t\t\t\t\t-1 * pwrtrk_tab_down_c[delta];\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"absolute_ofdm_swing_idx[PATH_C] = %d\\n\",\n\t\t\t\t       cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\tbreak;\n\n\t\t\tcase RF_PATH_D:\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"pwrtrk_tab_down_d[%d] = %d\\n\", delta,\n\t\t\t\t       pwrtrk_tab_down_d[delta]);\n\t\t\t\tcali_info->delta_power_index[p] =\n\t\t\t\t\t\t-1 * pwrtrk_tab_down_d[delta];\n\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =\n\t\t\t\t\t\t-1 * pwrtrk_tab_down_d[delta];\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"absolute_ofdm_swing_idx[PATH_D] = %d\\n\",\n\t\t\t\t       cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\tbreak;\n\n\t\t\tdefault:\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"pwrtrk_tab_down_a[%d] = %d\\n\", delta,\n\t\t\t\t       pwrtrk_tab_down_a[delta]);\n\t\t\t\tcali_info->delta_power_index[p] =\n\t\t\t\t\t\t-1 * pwrtrk_tab_down_a[delta];\n\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =\n\t\t\t\t\t\t-1 * pwrtrk_tab_down_a[delta];\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"absolute_ofdm_swing_idx[PATH_A] = %d\\n\",\n\t\t\t\t       cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* @JJ ADD 20161014 */\n\t\tif (dm->support_ic_type &\n\t\t    (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B |\n\t\t    ODM_RTL8192F)) {\n\t\t\t/*recording last Xtal offset*/\n\t\t\tcali_info->xtal_offset_last = cali_info->xtal_offset;\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"[Xtal] xtal_tab_down[%d] = %d\\n\", delta,\n\t\t\t       xtal_tab_down[delta]);\n\t\t\t/*Save xtal_offset from Xtal table*/\n\t\t\tcali_info->xtal_offset = xtal_tab_down[delta];\n\t\t\tif (cali_info->xtal_offset_last != xtal_tab_down[delta])\n\t\t\t\tcali_info->xtal_offset_eanble = 1;\n\t\t}\n\t}\n}\n\nvoid odm_pwrtrk_method(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 p, idxforchnl = 0;\n\n\tstruct txpwrtrack_cfg c = {0};\n\n\tconfigure_txpower_track(dm, &c);\n\n\tif (dm->support_ic_type &\n\t\t(ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8821 | ODM_RTL8812 |\n\t\tODM_RTL8723B | ODM_RTL8814A | ODM_RTL8703B | ODM_RTL8188F |\n\t\tODM_RTL8822B | ODM_RTL8821C | ODM_RTL8710B |\n\t\tODM_RTL8192F)) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"***Enter PwrTrk MIX_MODE***\\n\");\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t} else if (dm->support_ic_type & ODM_RTL8723D) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"***Enter PwrTrk MIX_MODE***\\n\");\n\t\tp = (u8)odm_get_bb_reg(dm, R_0x948, 0x00000080);\n\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t\t/*if open ant_div 0x948=140,do 2 path pwr_track*/\n\t\tif (odm_get_bb_reg(dm, R_0x948, 0x00000040))\n\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, 1, 0);\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"***Enter PwrTrk BBSWING_MODE***\\n\");\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t(*c.odm_tx_pwr_track_set_pwr)\n\t\t\t\t(dm, BBSWING, p, idxforchnl);\n\t}\n}\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\nvoid odm_txpowertracking_callback_thermal_meter(struct dm_struct *dm)\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\nvoid odm_txpowertracking_callback_thermal_meter(void *dm_void)\n#else\nvoid odm_txpowertracking_callback_thermal_meter(void *adapter)\n#endif\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#endif\n\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tu8 thermal_value = 0, delta, delta_lck, delta_iqk, p = 0, i = 0;\n\tu8 thermal_value_avg_count = 0;\n\tu32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;\n\n\t/* OFDM BB Swing should be less than +3.0dB, required by Arthur */\n#if 0\n\tu8 OFDM_min_index = 0;\n#endif\n#if 0\n\t/* get_right_chnl_place_for_iqk(hal_data->current_channel) */\n#endif\n\tu8 power_tracking_type = rf->pwt_type;\n\ts8 thermal_value_temp = 0;\n\n\tstruct txpwrtrack_cfg c = {0};\n\n\t/* @4 2. Initialization ( 7 steps in total ) */\n\n\tconfigure_txpower_track(dm, &c);\n\n\tcali_info->txpowertracking_callback_cnt++;\n\tcali_info->is_txpowertracking_init = true;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"\\n\\n\\n===>%s bbsw_idx_cck_base=%d\\n\",\n\t       __func__, cali_info->bb_swing_idx_cck_base);\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"bbsw_idx_ofdm_base[A]=%d default_ofdm_idx=%d\\n\",\n\t       cali_info->bb_swing_idx_ofdm_base[RF_PATH_A],\n\t       cali_info->default_ofdm_index);\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"cali_info->txpowertrack_control=%d, rf->eeprom_thermal %d\\n\",\n\t       cali_info->txpowertrack_control, rf->eeprom_thermal);\n\n\t /* 0x42: RF Reg[15:10] 88E */\n\tthermal_value =\n\t\t(u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);\n\n\tthermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"thermal_value_temp(%d) = ther_value(%d) + pwr_trim_ther(%d)\\n\",\n\t       thermal_value_temp, thermal_value,\n\t       phydm_get_thermal_offset(dm));\n\n\tif (thermal_value_temp > 63)\n\t\tthermal_value = 63;\n\telse if (thermal_value_temp < 0)\n\t\tthermal_value = 0;\n\telse\n\t\tthermal_value = thermal_value_temp;\n\n\t/*@add log by zhao he, check c80/c94/c14/ca0 value*/\n\tif (dm->support_ic_type &\n\t    (ODM_RTL8723D | ODM_RTL8710B)) {\n\t\tregc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);\n\t\tregcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);\n\t\tregcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);\n\t\tregab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF);\n\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t       \"0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\\n\",\n\t\t       regc80, regcd0, regcd4, regab4);\n\t}\n\n\tif (!cali_info->txpowertrack_control)\n\t\treturn;\n\n\tif (rf->eeprom_thermal == 0xff) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"no pg, hal_data->eeprom_thermal_meter = 0x%x\\n\",\n\t\t       rf->eeprom_thermal);\n\t\treturn;\n\t}\n\n\t/*@4 3. Initialize ThermalValues of rf_calibrate_info*/\n\n\tif (cali_info->is_reloadtxpowerindex)\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"reload ofdm index for band switch\\n\");\n\n\t/*@4 4. Calculate average thermal meter*/\n\n\tcali_info->thermal_value_avg[cali_info->thermal_value_avg_index]\n\t\t= thermal_value;\n\n\tcali_info->thermal_value_avg_index++;\n\t/*Average times =  c.average_thermal_num*/\n\tif (cali_info->thermal_value_avg_index == c.average_thermal_num)\n\t\tcali_info->thermal_value_avg_index = 0;\n\n\tfor (i = 0; i < c.average_thermal_num; i++) {\n\t\tif (cali_info->thermal_value_avg[i]) {\n\t\t\tthermal_value_avg += cali_info->thermal_value_avg[i];\n\t\t\tthermal_value_avg_count++;\n\t\t}\n\t}\n\n\t/* Calculate Average thermal_value after average enough times */\n\tif (thermal_value_avg_count) {\n\t\tthermal_value =\n\t\t\t(u8)(thermal_value_avg / thermal_value_avg_count);\n\t\tcali_info->thermal_value_delta\n\t\t\t= thermal_value - rf->eeprom_thermal;\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\\n\",\n\t\t       thermal_value, rf->eeprom_thermal);\n\t}\n\n\t/* @4 5. Calculate delta, delta_lck, delta_iqk. */\n\t/* \"delta\" here is used to determine thermal value changes or not. */\n\tif (thermal_value > cali_info->thermal_value)\n\t\tdelta = thermal_value - cali_info->thermal_value;\n\telse\n\t\tdelta = cali_info->thermal_value - thermal_value;\n\n\tif (thermal_value > cali_info->thermal_value_lck)\n\t\tdelta_lck = thermal_value - cali_info->thermal_value_lck;\n\telse\n\t\tdelta_lck = cali_info->thermal_value_lck - thermal_value;\n\n\tif (thermal_value > cali_info->thermal_value_iqk)\n\t\tdelta_iqk = thermal_value - cali_info->thermal_value_iqk;\n\telse\n\t\tdelta_iqk = cali_info->thermal_value_iqk - thermal_value;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"(delta, delta_lck, delta_iqk) = (%d, %d, %d)\\n\", delta,\n\t       delta_lck, delta_iqk);\n\n\t/*@4 6. If necessary, do LCK.*/\n\t/* Wait sacn to do LCK by RF Jenyu*/\n\tif (!(*dm->is_scan_in_process) && !iqk_info->rfk_forbidden) {\n\t\t/* Delta temperature is equal to or larger than 20 centigrade.*/\n\t\tif (delta_lck >= c.threshold_iqk) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"delta_lck(%d) >= threshold_iqk(%d)\\n\",\n\t\t\t       delta_lck, c.threshold_iqk);\n\t\t\tcali_info->thermal_value_lck = thermal_value;\n\n\t\t\t/*Use RTLCK, close power tracking driver LCK*/\n\t\t\t/*8821 don't do LCK*/\n\t\t\tif (!(dm->support_ic_type &\n\t\t\t\t(ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B)) &&\n\t\t\t\tc.phy_lc_calibrate) {\n\t\t\t\t(*c.phy_lc_calibrate)(dm);\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"do pwrtrk lck\\n\");\n\t\t\t}\n\t\t}\n\t}\n\n\t/*@3 7. If necessary, move the index of swing table to adjust Tx power.*/\n\t/* \"delta\" here is used to record the absolute value of difference. */\n\tif (delta > 0 && cali_info->txpowertrack_control) {\n\t\tif (thermal_value > rf->eeprom_thermal)\n\t\t\tdelta = thermal_value - rf->eeprom_thermal;\n\t\telse\n\t\t\tdelta = rf->eeprom_thermal - thermal_value;\n\n\t\tif (delta >= TXPWR_TRACK_TABLE_SIZE)\n\t\t\tdelta = TXPWR_TRACK_TABLE_SIZE - 1;\n\n\t\todm_get_tracking_table(dm, thermal_value, delta);\n\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"\\n[path-%d] Calculate pwr_idx_offset\\n\", p);\n\n\t\t\t/*If Thermal value changes but table value is the same*/\n\t\t\tif (cali_info->delta_power_index[p] ==\n\t\t\t\tcali_info->delta_power_index_last[p])\n\t\t\t\tcali_info->power_index_offset[p] = 0;\n\t\t\telse\n\t\t\t\tcali_info->power_index_offset[p] =\n\t\t\t\tcali_info->delta_power_index[p] -\n\t\t\t\tcali_info->delta_power_index_last[p];\n\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"path-%d pwridx_diff%d=pwr_idx%d - last_idx%d\\n\",\n\t\t\t       p, cali_info->power_index_offset[p],\n\t\t\t       cali_info->delta_power_index[p],\n\t\t\t       cali_info->delta_power_index_last[p]);\n#if 0\n\n\t\t\tcali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];\n\t\t\tcali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];\n\n\t\t\tcali_info->bb_swing_idx_cck = cali_info->CCK_index;\n\t\t\tcali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];\n\n\t\t\t/*************Print BB Swing base and index Offset*************/\n\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\\n\",\n\t\t\t       cali_info->bb_swing_idx_cck,\n\t\t\t       cali_info->bb_swing_idx_cck_base,\n\t\t\t       cali_info->power_index_offset[p]);\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\\n\",\n\t\t\t       cali_info->bb_swing_idx_ofdm[p], p,\n\t\t\t       cali_info->bb_swing_idx_ofdm_base[p],\n\t\t\t       cali_info->power_index_offset[p]);\n\n\t\t\t/*4 7.1 Handle boundary conditions of index.*/\n\n\t\t\tif (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)\n\t\t\t\tcali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;\n\t\t\telse if (cali_info->OFDM_index[p] <= OFDM_min_index)\n\t\t\t\tcali_info->OFDM_index[p] = OFDM_min_index;\n#endif\n\t\t}\n#if 0\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"\\n\\n========================================================================================================\\n\");\n\n\t\tif (cali_info->CCK_index > c.swing_table_size_cck - 1)\n\t\t\tcali_info->CCK_index = c.swing_table_size_cck - 1;\n\t\telse if (cali_info->CCK_index <= 0)\n\t\t\tcali_info->CCK_index = 0;\n#endif\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"Thermal is unchanged thermal=%d last_thermal=%d\\n\",\n\t\t       thermal_value,\n\t\t       cali_info->thermal_value);\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\tcali_info->power_index_offset[p] = 0;\n\t}\n\n#if 0\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\\n\",\n\t       cali_info->CCK_index,\n\t       cali_info->bb_swing_idx_cck_base); /*Print Swing base & current*/\n\n\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\\n\",\n\t\t       cali_info->OFDM_index[p], p,\n\t\t       cali_info->bb_swing_idx_ofdm_base[p]);\n\t}\n#endif\n\n\tif ((dm->support_ic_type & ODM_RTL8814A)) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"power_tracking_type=%d\\n\",\n\t\t       power_tracking_type);\n\n\t\tif (power_tracking_type == 0) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"***Enter PwrTrk MIX_MODE***\\n\");\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)\n\t\t\t\t\t(dm, MIX_MODE, p, 0);\n\t\t} else if (power_tracking_type == 1) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"***Enter PwrTrk MIX(2G) TSSI(5G) MODE***\\n\");\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)\n\t\t\t\t\t(dm, MIX_2G_TSSI_5G_MODE, p, 0);\n\t\t} else if (power_tracking_type == 2) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"***Enter PwrTrk MIX(5G) TSSI(2G)MODE***\\n\");\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)\n\t\t\t\t\t(dm, MIX_5G_TSSI_2G_MODE, p, 0);\n\t\t} else if (power_tracking_type == 3) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"***Enter PwrTrk TSSI MODE***\\n\");\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)\n\t\t\t\t\t(dm, TSSI_MODE, p, 0);\n\t\t}\n\t} else if ((cali_info->power_index_offset[RF_PATH_A] != 0 ||\n\t\t    cali_info->power_index_offset[RF_PATH_B] != 0 ||\n\t\t    cali_info->power_index_offset[RF_PATH_C] != 0 ||\n\t\t    cali_info->power_index_offset[RF_PATH_D] != 0)) {\n#if 0\n\t\t/* 4 7.2 Configure the Swing Table to adjust Tx Power. */\n\t\t/*Always true after Tx Power is adjusted by power tracking.*/\n\n\t\tcali_info->is_tx_power_changed = true;\n\t\t/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital\n\t\t * to increase TX power. Otherwise, EVM will be bad.\n\t\t *\n\t\t * 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E.\n\t\t */\n\t\tif (thermal_value > cali_info->thermal_value) {\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\\n\",\n\t\t\t\t       p, cali_info->power_index_offset[p],\n\t\t\t\t       delta, thermal_value, rf->eeprom_thermal,\n\t\t\t\t       cali_info->thermal_value);\n\t\t\t}\n\t\t} else if (thermal_value < cali_info->thermal_value) { /*Low temperature*/\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\\n\",\n\t\t\t\t       p, cali_info->power_index_offset[p],\n\t\t\t\t       delta, thermal_value, rf->eeprom_thermal,\n\t\t\t\t       cali_info->thermal_value);\n\t\t\t}\n\t\t}\n#endif\n\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\n\t\tif (thermal_value > rf->eeprom_thermal) {\n#else\n\t\tif (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {\n#endif\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"Temperature(%d) higher than PG value(%d)\\n\",\n\t\t\t       thermal_value, rf->eeprom_thermal);\n\n\t\t\todm_pwrtrk_method(dm);\n\t\t} else {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"Temperature(%d) lower than PG value(%d)\\n\",\n\t\t\t       thermal_value, rf->eeprom_thermal);\n\n\t\t\todm_pwrtrk_method(dm);\n\t\t}\n\n#if 0\n\t\t/*Record last time Power Tracking result as base.*/\n\t\tcali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\tcali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];\n#endif\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"cali_info->thermal_value = %d thermal_value= %d\\n\",\n\t\t       cali_info->thermal_value, thermal_value);\n\t}\n\t/*Record last Power Tracking Thermal value*/\n\tcali_info->thermal_value = thermal_value;\n\n\tif (dm->support_ic_type &\n\t\t(ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8192F | ODM_RTL8710B)) {\n\t\tif (cali_info->xtal_offset_eanble != 0 &&\n\t\t    cali_info->txpowertrack_control &&\n\t\t    rf->eeprom_thermal != 0xff) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"**********Enter Xtal Tracking**********\\n\");\n\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\n\t\t\tif (thermal_value > rf->eeprom_thermal) {\n#else\n\t\t\tif (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {\n#endif\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"Temperature(%d) higher than PG (%d)\\n\",\n\t\t\t\t       thermal_value, rf->eeprom_thermal);\n\t\t\t\t(*c.odm_txxtaltrack_set_xtal)(dm);\n\t\t\t} else {\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"Temperature(%d) lower than PG (%d)\\n\",\n\t\t\t\t       thermal_value, rf->eeprom_thermal);\n\t\t\t\t(*c.odm_txxtaltrack_set_xtal)(dm);\n\t\t\t}\n\t\t}\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"**********End Xtal Tracking**********\\n\");\n\t}\n\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\n\n\t/* Wait sacn to do IQK by RF Jenyu*/\n\tif (!(*dm->is_scan_in_process) && !iqk_info->rfk_forbidden &&\n\t    !cali_info->is_iqk_in_progress) {\n\t\tif (!(dm->support_ic_type & ODM_RTL8723B)) {\n\t\t\t/*Delta temperature is equal or larger than 20 Celsius*/\n\t\t\t/*When threshold is 8*/\n\t\t\tif (delta_iqk >= c.threshold_iqk) {\n\t\t\t\tcali_info->thermal_value_iqk = thermal_value;\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"delta_iqk(%d) >= threshold_iqk(%d)\\n\",\n\t\t\t\t       delta_iqk, c.threshold_iqk);\n\t\t\t\t(*c.do_iqk)(dm, delta_iqk, thermal_value, 8);\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"do pwrtrk iqk\\n\");\n\t\t\t}\n\t\t}\n\t}\n\n#if 0\n\tif (cali_info->dpk_thermal[RF_PATH_A] != 0) {\n\t\tif (diff_DPK[RF_PATH_A] >= c.threshold_dpk) {\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk));\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);\n\t\t} else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) {\n\t\t\ts32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk);\n\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);\n\t\t}\n\t}\n\tif (cali_info->dpk_thermal[RF_PATH_B] != 0) {\n\t\tif (diff_DPK[RF_PATH_B] >= c.threshold_dpk) {\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk));\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);\n\t\t} else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) {\n\t\t\ts32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk);\n\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);\n\t\t}\n\t}\n#endif\n\n#endif\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"<===%s\\n\", __func__);\n\n\tcali_info->tx_powercount = 0;\n}\n\n#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)\nvoid\nodm_txpowertracking_new_callback_thermal_meter(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);\n \tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\tu8 thermal_value[MAX_RF_PATH] = {0}, delta[MAX_RF_PATH] = {0};\n\tu8 delta_swing_table_idx_tup[DELTA_SWINGIDX_SIZE] = {0};\n\tu8 delta_swing_table_idx_tdown[DELTA_SWINGIDX_SIZE] = {0};\n\tu8 delta_LCK = 0, delta_IQK = 0, i = 0, j = 0, p;\n\tu8 thermal_value_avg_count[MAX_RF_PATH] = {0};\n\tu32 thermal_value_avg[MAX_RF_PATH] = {0};\n\ts8 thermal_value_temp[MAX_RF_PATH] = {0};\n\tu8 tracking_method = MIX_MODE;\n\n\tstruct txpwrtrack_cfg c;\n\n\tu8 *delta_swing_table_idx_tup_a = NULL;\n\tu8 *delta_swing_table_idx_tdown_a = NULL;\n\tu8 *delta_swing_table_idx_tup_b = NULL;\n\tu8 *delta_swing_table_idx_tdown_b = NULL;\n\tu8 *delta_swing_table_idx_tup_c = NULL;\n\tu8 *delta_swing_table_idx_tdown_c = NULL;\n\tu8 *delta_swing_table_idx_tup_d = NULL;\n\tu8 *delta_swing_table_idx_tdown_d = NULL;\n\n\tconfigure_txpower_track(dm, &c);\n\n\t(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,\n\t\t(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);\n\n\tif (dm->support_ic_type == ODM_RTL8814B) {\n\t\t(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,\n\t\t\t(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);\n\t}\n\n\tcali_info->txpowertracking_callback_cnt++;\n\tcali_info->is_txpowertracking_init = true;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"===>odm_txpowertracking_callback_thermal_meter\\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\\n\",\n\t\tcali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"cali_info->txpowertrack_control=%d, tssi->thermal[RF_PATH_A]=%d tssi->thermal[RF_PATH_B]=%d\\n\",\n\t\tcali_info->txpowertrack_control,  tssi->thermal[RF_PATH_A], tssi->thermal[RF_PATH_B]);\n\n\tif (dm->support_ic_type == ODM_RTL8822C) {\n\t\tfor (i = 0; i < c.rf_path_count; i++)\n\t\t\tthermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0x7e); /* 0x42: RF Reg[6:1] Thermal Trim*/\n\t} else {\n\t\tfor (i = 0; i < c.rf_path_count; i++) {\n\t\t\tthermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0xfc00);\t/* 0x42: RF Reg[15:10] 88E */\n\n\t\t\tthermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + thermal_trim(%d)\\n\", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));\n\n\t\t\tif (thermal_value_temp[i] > 63)\n\t\t\t\tthermal_value[i] = 63;\n\t\t\telse if (thermal_value_temp[i] < 0)\n\t\t\t\tthermal_value[i] = 0;\n\t\t\telse\n\t\t\t\tthermal_value[i] = thermal_value_temp[i];\n\t\t}\n\t}\n\n\tif ((tssi->thermal[RF_PATH_A] == 0xff || tssi->thermal[RF_PATH_B] == 0xff) &&\n\t\tcali_info->txpowertrack_control != 3) {\n\t\tfor (i = 0; i < c.rf_path_count; i++)\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"no pg, tssi->thermal[%d] = 0x%x\\n\",\n\t\t\t\ti, tssi->thermal[i]);\n\t\treturn;\n\t}\n\n\tfor (j = 0; j < c.rf_path_count; j++) {\n\t\tcali_info->thermal_value_avg_path[j][cali_info->thermal_value_avg_index_path[j]] = thermal_value[j];\n\t\tcali_info->thermal_value_avg_index_path[j]++;\n\t\tif (cali_info->thermal_value_avg_index_path[j] == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/\n\t\t\tcali_info->thermal_value_avg_index_path[j] = 0;\n\n\n\t\tfor (i = 0; i < c.average_thermal_num; i++) {\n\t\t\tif (cali_info->thermal_value_avg_path[j][i]) {\n\t\t\t\tthermal_value_avg[j] += cali_info->thermal_value_avg_path[j][i];\n\t\t\t\tthermal_value_avg_count[j]++;\n\t\t\t}\n\t\t}\n\n\t\tif (thermal_value_avg_count[j]) {            /* Calculate Average thermal_value after average enough times */\n\t\t\tthermal_value[j] = (u8)(thermal_value_avg[j] / thermal_value_avg_count[j]);\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"AVG Thermal Meter = 0x%X, tssi->thermal[%d] = 0x%x\\n\",\n\t\t\t\tthermal_value[j], j, tssi->thermal[j]);\n\t\t}\n\t\t/* 4 5. Calculate delta, delta_LCK, delta_IQK. */\n\n\t\t/* \"delta\" here is used to determine whether thermal value changes or not. */\n\t\tdelta[j] = (thermal_value[j] > cali_info->thermal_value_path[j]) ? (thermal_value[j] - cali_info->thermal_value_path[j]) : (cali_info->thermal_value_path[j] - thermal_value[j]);\n\t\tdelta_LCK = (thermal_value[0] > cali_info->thermal_value_lck) ? (thermal_value[0] - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value[0]);\n\t\tdelta_IQK = (thermal_value[0] > cali_info->thermal_value_iqk) ? (thermal_value[0] - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value[0]);\n\t}\n\n\t/*4 6. If necessary, do LCK.*/\n\n\tfor (i = 0; i < c.rf_path_count; i++)\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"(delta[%d], delta_LCK, delta_IQK) = (%d, %d, %d)\\n\", i, delta[i], delta_LCK, delta_IQK);\n\n\t/* Wait sacn to do LCK by RF Jenyu*/\n\tif( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {\n\t\t/* Delta temperature is equal to or larger than 20 centigrade.*/\n\t\tif (delta_LCK >= c.threshold_iqk) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"delta_LCK(%d) >= threshold_iqk(%d)\\n\", delta_LCK, c.threshold_iqk);\n\t\t\tcali_info->thermal_value_lck = thermal_value[RF_PATH_A];\n\n\t\t\t/*Use RTLCK, so close power tracking driver LCK*/\n\t\t\tif ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {\n\t\t\t\tif (c.phy_lc_calibrate)\n\t\t\t\t\t(*c.phy_lc_calibrate)(dm);\n\t\t\t} else\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"Do not do LCK\\n\");\n\t\t}\n\t}\n\n\t/*3 7. If necessary, move the index of swing table to adjust Tx power.*/\n\tfor (i = 0; i < c.rf_path_count; i++) {\n\t\tif (i == RF_PATH_B) {\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_b, DELTA_SWINGIDX_SIZE);\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_b, DELTA_SWINGIDX_SIZE);\n\t\t} else if (i == RF_PATH_C) {\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_c, DELTA_SWINGIDX_SIZE);\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_c, DELTA_SWINGIDX_SIZE);\n\t\t} else if (i == RF_PATH_D) {\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_d, DELTA_SWINGIDX_SIZE);\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_d, DELTA_SWINGIDX_SIZE);\n\t\t} else {\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_a, DELTA_SWINGIDX_SIZE);\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_a, DELTA_SWINGIDX_SIZE);\n\t\t}\n\n\t\tcali_info->delta_power_index_last[i] = cali_info->delta_power_index[i];\t/*recording poer index offset*/\n\t\tdelta[i] = thermal_value[i] > tssi->thermal[i] ? (thermal_value[i] - tssi->thermal[i]) : (tssi->thermal[i] - thermal_value[i]);\n\t\t\t\t\n\t\tif (delta[i] >= TXPWR_TRACK_TABLE_SIZE)\n\t\t\tdelta[i] = TXPWR_TRACK_TABLE_SIZE - 1;\n\n\t\tif (thermal_value[i] > tssi->thermal[i]) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"delta_swing_table_idx_tup[%d]=%d Path=%d\\n\", delta[i], delta_swing_table_idx_tup[delta[i]], i);\n\t\t\t\t\n\t\t\tcali_info->delta_power_index[i] = delta_swing_table_idx_tup[delta[i]];\n\t\t\tcali_info->absolute_ofdm_swing_idx[i] =  delta_swing_table_idx_tup[delta[i]];\t    /*Record delta swing for mix mode power tracking*/\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"******Temp is higher and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\\n\", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);\n\t\t} else {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"delta_swing_table_idx_tdown[%d]=%d Path=%d\\n\", delta[i], delta_swing_table_idx_tdown[delta[i]], i);\n\t\t\tcali_info->delta_power_index[i] = -1 * delta_swing_table_idx_tdown[delta[i]];\n\t\t\tcali_info->absolute_ofdm_swing_idx[i] = -1 * delta_swing_table_idx_tdown[delta[i]];        /*Record delta swing for mix mode power tracking*/\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"******Temp is lower and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\\n\", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);\n\t\t}\n\t}\n\n\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\t\n\t\tif (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p])\t     /*If Thermal value changes but lookup table value still the same*/\n\t\t\tcali_info->power_index_offset[p] = 0;\n\t\telse\n\t\t\tcali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p];\t/*Power index diff between 2 times Power Tracking*/\n\t}\n\n#if 0\n\tif (dm->support_ic_type == ODM_RTL8822C) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking MIX_MODE**********\\n\");\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking BBSWING_MODE**********\\n\");\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);\n\t}\n#endif\n\tif (*dm->mp_mode == 1) {\n\t\tif (cali_info->txpowertrack_control == 1) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking MIX_MODE**********\\n\");\n\t\t\ttracking_method = MIX_MODE;\n\t\t} else if (cali_info->txpowertrack_control == 3) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking TSSI_MODE**********\\n\");\n\t\t\ttracking_method = TSSI_MODE;\n\t\t}\n\t} else {\n\t\tif (rf->power_track_type >= 0 && rf->power_track_type <= 3) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking MIX_MODE**********\\n\");\n\t\t\ttracking_method = MIX_MODE;\n\t\t} else if (rf->power_track_type >= 4 && rf->power_track_type <= 7) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking TSSI_MODE**********\\n\");\n\t\t\ttracking_method = TSSI_MODE;\n\t\t}\n\t}\n\n\tif (dm->support_ic_type == ODM_RTL8822C || dm->support_ic_type == ODM_RTL8814B)\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, tracking_method, p, 0);\n\n\t/* Wait sacn to do IQK by RF Jenyu*/\n\tif ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden) && dm->is_linked) {\n\t\t/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/\n\t\tif (delta_IQK >= c.threshold_iqk) {\n\t\t\tcali_info->thermal_value_iqk = thermal_value[RF_PATH_A];\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"delta_IQK(%d) >= threshold_iqk(%d)\\n\", delta_IQK, c.threshold_iqk);\n\t\t\t/*if (!cali_info->is_iqk_in_progress)*/\n\t\t\t/*\t(*c.do_iqk)(dm, delta_IQK, thermal_value[RF_PATH_A], 8);*/\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"Do IQK\\n\");\n\n\t\t\t/*if (!cali_info->is_iqk_in_progress)*/\n\t\t\t/*\t(*c.do_tssi_dck)(dm, true);*/\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"Do TSSI DCK\\n\");\n\t\t}\n\t}\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"<===%s\\n\", __func__);\n\n\tcali_info->tx_powercount = 0;\n}\n#endif\n\n/*@3============================================================\n * 3 IQ Calibration\n * 3============================================================\n */\n\nvoid odm_reset_iqk_result(void *dm_void)\n{\n}\n\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\nu8 odm_get_right_chnl_place_for_iqk(u8 chnl)\n{\n\tu8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {\n\t\t1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,\n\t\t36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64,\n\t\t100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122,\n\t\t124, 126, 128, 130, 132, 134, 136, 138, 140,\n\t\t149, 151, 153, 155, 157, 159, 161, 163, 165};\n\tu8 place = chnl;\n\n\tif (chnl > 14) {\n\t\tfor (place = 14; place < sizeof(channel_all); place++) {\n\t\t\tif (channel_all[place] == chnl)\n\t\t\t\treturn place - 13;\n\t\t}\n\t}\n\treturn 0;\n}\n#endif\n\nvoid odm_iq_calibrate(struct dm_struct *dm)\n{\n\tvoid *adapter = dm->adapter;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tif (*dm->is_fcs_mode_enable)\n\t\treturn;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))\n\tif (IS_HARDWARE_TYPE_8812AU(adapter))\n\t\treturn;\n#endif\n\n\tif (dm->is_linked && !iqk_info->rfk_forbidden) {\n\t\tif ((*dm->channel != dm->pre_channel) &&\n\t\t    (!*dm->is_scan_in_process)) {\n\t\t\tdm->pre_channel = *dm->channel;\n\t\t\tdm->linked_interval = 0;\n\t\t}\n\n\t\tif (dm->linked_interval < 3)\n\t\t\tdm->linked_interval++;\n\n\t\tif (dm->linked_interval == 2)\n\t\t\thalrf_iqk_trigger(dm, false);\n\t} else {\n\t\tdm->linked_interval = 0;\n\t}\n}\n\nvoid phydm_rf_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\todm_txpowertracking_init(dm);\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\todm_clear_txpowertracking_state(dm);\n#endif\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n#if (RTL8814A_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8814A)\n\t\tphy_iq_calibrate_8814a_init(dm);\n#endif\n#endif\n}\n\nvoid phydm_rf_watchdog(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\todm_txpowertracking_check(dm);\n#if 0\n/*if (dm->support_ic_type & ODM_IC_11AC_SERIES)*/\n/*odm_iq_calibrate(dm);*/\n#endif\n#endif\n}\n"
  },
  {
    "path": "hal/phydm/halrf/halphyrf_ce.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALPHYRF_H__\n#define __HALPHYRF_H__\n\n#include \"halrf/halrf_kfree.h\"\n#if (RTL8814A_SUPPORT == 1)\n#include \"halrf/rtl8814a/halrf_iqk_8814a.h\"\n#endif\n\n#if (RTL8822B_SUPPORT == 1)\n#include \"halrf/rtl8822b/halrf_iqk_8822b.h\"\n#endif\n\n#if (RTL8821C_SUPPORT == 1)\n#include \"halrf/rtl8821c/halrf_iqk_8821c.h\"\n#endif\n\n#if (RTL8195B_SUPPORT == 1)\n/* #include \"halrf/rtl8195b/halrf.h\" */\n#include \"halrf/rtl8195b/halrf_iqk_8195b.h\"\n#include \"halrf/rtl8195b/halrf_txgapk_8195b.h\"\n#include \"halrf/rtl8195b/halrf_dpk_8195b.h\"\n#endif\n\n#if (RTL8814B_SUPPORT == 1)\n\t#include \"halrf/rtl8814b/halrf_iqk_8814b.h\"\t\n\t#include \"halrf/rtl8814b/halrf_dpk_8814b.h\"\n#endif\n\n#include \"halrf/halrf_powertracking_ce.h\"\n\nenum spur_cal_method {\n\tPLL_RESET,\n\tAFE_PHASE_SEL\n};\n\nenum pwrtrack_method {\n\tBBSWING,\n\tTXAGC,\n\tMIX_MODE,\n\tTSSI_MODE,\n\tMIX_2G_TSSI_5G_MODE,\n\tMIX_5G_TSSI_2G_MODE,\n\tCLEAN_MODE\n};\n\ntypedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);\ntypedef void (*func_iqk)(void *, u8, u8, u8);\ntypedef void (*func_lck)(void *);\ntypedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);\ntypedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);\ntypedef void (*func_swing_xtal)(void *, s8 **, s8 **);\ntypedef void (*func_set_xtal)(void *);\n\nstruct txpwrtrack_cfg {\n\tu8 swing_table_size_cck;\n\tu8 swing_table_size_ofdm;\n\tu8 threshold_iqk;\n\tu8 threshold_dpk;\n\tu8 average_thermal_num;\n\tu8 rf_path_count;\n\tu32 thermal_reg_addr;\n\tfunc_set_pwr odm_tx_pwr_track_set_pwr;\n\tfunc_iqk do_iqk;\n\tfunc_lck phy_lc_calibrate;\n\tfunc_swing get_delta_swing_table;\n\tfunc_swing8814only get_delta_swing_table8814only;\n\tfunc_swing_xtal get_delta_swing_xtal_table;\n\tfunc_set_xtal odm_txxtaltrack_set_xtal;\n};\n\nvoid configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config);\n\nvoid odm_clear_txpowertracking_state(void *dm_void);\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\nvoid odm_txpowertracking_callback_thermal_meter(void *dm_void);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\nvoid odm_txpowertracking_callback_thermal_meter(void *dm);\n#else\nvoid odm_txpowertracking_callback_thermal_meter(void *adapter);\n#endif\n\n#if (RTL8822C_SUPPORT == 1)\nvoid odm_txpowertracking_new_callback_thermal_meter(void *dm_void);\n#endif\n\n#define ODM_TARGET_CHNL_NUM_2G_5G 59\n\nvoid odm_reset_iqk_result(void *dm_void);\nu8 odm_get_right_chnl_place_for_iqk(u8 chnl);\n\nvoid phydm_rf_init(void *dm_void);\nvoid phydm_rf_watchdog(void *dm_void);\n\n#endif /*__HALPHYRF_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/halphyrf_iot.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#define\tCALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \\\n\tdo {\\\n\t\tfor (_offset = 0; _offset < _size; _offset++) { \\\n\t\t\tif (_delta_thermal < thermal_threshold[_direction][_offset]) { \\\n\t\t\t\tif (_offset != 0)\\\n\t\t\t\t\t_offset--;\\\n\t\t\t\tbreak;\\\n\t\t\t} \\\n\t\t}\t\t\t\\\n\t\tif (_offset >= _size)\\\n\t\t\t_offset = _size-1;\\\n\t} while (0)\n\nvoid configure_txpower_track(\n\tvoid\t\t\t\t\t*dm_void,\n\tstruct txpwrtrack_cfg\t*config\n)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#if RTL8195B_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8195B)\n\t\tconfigure_txpower_track_8195b(config);\n#endif\n#if RTL8710C_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8710C)\n\t\tconfigure_txpower_track_8710c(config);\n#endif\n#if RTL8721D_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8721D)\n\t\tconfigure_txpower_track_8721d(config);\n#endif\n\n}\n\n/* **********************************************************************\n * <20121113, Kordan> This function should be called when tx_agc changed.\n * Otherwise the previous compensation is gone, because we record the\n * delta of temperature between two TxPowerTracking watch dogs.\n *\n * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still\n * need to call this function.\n * ********************************************************************** */\nvoid\nodm_clear_txpowertracking_state(\n\tvoid\t\t\t\t\t*dm_void\n)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tu8\t\t\tp = 0;\n\tstruct dm_rf_calibration_struct\t*cali_info = &dm->rf_calibrate_info;\n\n\tcali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;\n\tcali_info->bb_swing_idx_cck = cali_info->default_cck_index;\n\tdm->rf_calibrate_info.CCK_index = 0;\n\n\tfor (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {\n\t\tcali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;\n\t\tcali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;\n\t\tcali_info->OFDM_index[p] = cali_info->default_ofdm_index;\n\n\t\tcali_info->power_index_offset[p] = 0;\n\t\tcali_info->delta_power_index[p] = 0;\n\t\tcali_info->delta_power_index_last[p] = 0;\n\n\t\tcali_info->absolute_ofdm_swing_idx[p] = 0;\n\t\tcali_info->remnant_ofdm_swing_idx[p] = 0;\n\t\tcali_info->kfree_offset[p] = 0;\n\t}\n\n\tcali_info->modify_tx_agc_flag_path_a = false;\n\tcali_info->modify_tx_agc_flag_path_b = false;\n\tcali_info->modify_tx_agc_flag_path_c = false;\n\tcali_info->modify_tx_agc_flag_path_d = false;\n\tcali_info->remnant_cck_swing_idx = 0;\n\tcali_info->thermal_value = rf->eeprom_thermal;\n\tcali_info->modify_tx_agc_value_cck = 0;\n\tcali_info->modify_tx_agc_value_ofdm = 0;\n}\n\nvoid\nodm_txpowertracking_callback_thermal_meter(\n\tvoid\t*dm_void\n)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;\n\tstruct\tdm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tu8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;\n\tu8 thermal_value_avg_count = 0;\n\tu32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;\n\n\tu8 OFDM_min_index = 0;  /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */\n\tu8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */\n\tu8 power_tracking_type = rf->pwt_type;\n\tu8 xtal_offset_eanble = 0;\n\ts8 thermal_value_temp = 0;\n\n\tstruct txpwrtrack_cfg\tc = {0};\n\n\t/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */\n\tu8 *delta_swing_table_idx_tup_a = NULL;\n\tu8 *delta_swing_table_idx_tdown_a = NULL;\n\tu8 *delta_swing_table_idx_tup_b = NULL;\n\tu8 *delta_swing_table_idx_tdown_b = NULL;\n#if (RTL8721D_SUPPORT == 1)\n\tu8 *delta_swing_table_idx_tup_a_cck = NULL;\n\tu8 *delta_swing_table_idx_tdown_a_cck = NULL;\n\tu8 *delta_swing_table_idx_tup_b_cck = NULL;\n\tu8 *delta_swing_table_idx_tdown_b_cck = NULL;\n#endif\n\t/*for Xtal Offset by James.Tung*/\n\ts8 *delta_swing_table_xtal_up = NULL;\n\ts8 *delta_swing_table_xtal_down = NULL;\n\n\t/* 4 2. Initialization ( 7 steps in total ) */\n\n\tconfigure_txpower_track(dm, &c);\n#if (RTL8721D_SUPPORT == 1)\n\t(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,\n\t\t(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b,\n\t\t(u8 **)&delta_swing_table_idx_tup_a_cck, (u8 **)&delta_swing_table_idx_tdown_a_cck,\n\t\t(u8 **)&delta_swing_table_idx_tup_b_cck, (u8 **)&delta_swing_table_idx_tdown_b_cck);\n#else\n\t(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,\n\t\t(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);\n#endif\n\n\t/*for Xtal Offset*/\n\tif (dm->support_ic_type == ODM_RTL8195B ||\n\t    dm->support_ic_type == ODM_RTL8721D)\n\t\t(*c.get_delta_swing_xtal_table)(dm,\n\t\t (s8 **)&delta_swing_table_xtal_up,\n\t\t (s8 **)&delta_swing_table_xtal_down);\n\n\tcali_info->txpowertracking_callback_cnt++;\t/*cosa add for debug*/\n\tcali_info->is_txpowertracking_init = true;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"===>odm_txpowertracking_callback_thermal_meter\\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\\n\",\n\t       cali_info->bb_swing_idx_cck_base,\n\t       cali_info->bb_swing_idx_ofdm_base[RF_PATH_A],\n\t       cali_info->default_ofdm_index);\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"cali_info->txpowertrack_control = %d, hal_data->eeprom_thermal_meter %d\\n\",\n\t       cali_info->txpowertrack_control, rf->eeprom_thermal);\n\n\tif (dm->support_ic_type == ODM_RTL8721D)\n\t\tthermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A,\n\t\t\t\t\t\t   c.thermal_reg_addr, 0x7e0);\n\t\t/* 0x42: RF Reg[10:5] 8721D */\n\telse\n\t\tthermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A,\n\t\t\t\t\t\t   c.thermal_reg_addr, 0xfc00);\n\t\t/* 0x42: RF Reg[15:10] 88E */\n\n\tthermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"thermal_value_temp(%d) = thermal_value(%d) + power_trim_thermal(%d)\\n\", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));\n\n\tif (thermal_value_temp > 63)\n\t\tthermal_value = 63;\n\telse if (thermal_value_temp < 0)\n\t\tthermal_value = 0;\n\telse\n\t\tthermal_value = thermal_value_temp;\n\n\tif (!cali_info->txpowertrack_control)\n\t\treturn;\n\n\tif (rf->eeprom_thermal == 0xff) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"no pg, hal_data->eeprom_thermal_meter = 0x%x\\n\", rf->eeprom_thermal);\n\t\treturn;\n\t}\n#if 0\n\t/*4 3. Initialize ThermalValues of rf_calibrate_info*/\n\t//if (cali_info->is_reloadtxpowerindex)\n\t//\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"reload ofdm index for band switch\\n\");\n#endif\n\t/*4 4. Calculate average thermal meter*/\n\n\tcali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value;\n\tcali_info->thermal_value_avg_index++;\n\tif (cali_info->thermal_value_avg_index == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/\n\t\tcali_info->thermal_value_avg_index = 0;\n\n\tfor (i = 0; i < c.average_thermal_num; i++) {\n\t\tif (cali_info->thermal_value_avg[i]) {\n\t\t\tthermal_value_avg += cali_info->thermal_value_avg[i];\n\t\t\tthermal_value_avg_count++;\n\t\t}\n\t}\n\n\tif (thermal_value_avg_count) {\t\t\t  /* Calculate Average thermal_value after average enough times */\n\t\tthermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);\n\t\tcali_info->thermal_value_delta = thermal_value - rf->eeprom_thermal;\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\\n\", thermal_value, rf->eeprom_thermal);\n\t}\n\n\t/* 4 5. Calculate delta, delta_LCK, delta_IQK. */\n\t/* \"delta\" here is used to determine whether thermal value changes or not. */\n\tdelta\t= (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value);\n\tdelta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);\n\tdelta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);\n\n\t/*4 6. If necessary, do LCK.*/\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\\n\", delta, delta_LCK, delta_IQK);\n\n\t/* Wait sacn to do LCK by RF Jenyu*/\n\tif ((!*dm->is_scan_in_process) && !iqk_info->rfk_forbidden &&\n\t    (!*dm->is_tdma)) {\n\t\t/* Delta temperature is equal to or larger than 20 centigrade.*/\n\t\tif (delta_LCK >= c.threshold_iqk) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"delta_LCK(%d) >= threshold_iqk(%d)\\n\", delta_LCK, c.threshold_iqk);\n\t\t\tcali_info->thermal_value_lck = thermal_value;\n\n\t\t\t/*Use RTLCK, so close power tracking driver LCK*/\n\t\t\t(*c.phy_lc_calibrate)(dm);\n\t\t}\n\t}\n\n\t/*3 7. If necessary, move the index of swing table to adjust Tx power.*/\n\tif (delta > 0 && cali_info->txpowertrack_control) {\n\t\t/* \"delta\" here is used to record the absolute value of difference. */\n\t\tdelta = thermal_value > rf->eeprom_thermal ? (thermal_value - rf->eeprom_thermal) : (rf->eeprom_thermal - thermal_value);\n\n\t\tif (delta >= TXPWR_TRACK_TABLE_SIZE)\n\t\t\tdelta = TXPWR_TRACK_TABLE_SIZE - 1;\n\n\t\t/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/\n\t\tif (thermal_value > rf->eeprom_thermal) {\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\t\t\tcali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/\n\t\t\t\tswitch (p) {\n\t\t\t\tcase RF_PATH_B:\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t       \"delta_swing_table_idx_tup_b[%d] = %d\\n\", delta, delta_swing_table_idx_tup_b[delta]);\n#if (RTL8721D_SUPPORT == 1)\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t       \"delta_swing_table_idx_tup_b_cck[%d] = %d\\n\", delta, delta_swing_table_idx_tup_b_cck[delta]);\n\n\t\t\t\t\tcali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_b_cck[delta];\n\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t       \"******Temp is higher and cali_info->absolute_cck_swing_idx[RF_PATH_B] = %d\\n\",\n\t\t\t\t\t       cali_info->absolute_cck_swing_idx[p]);\n#endif\n\t\t\t\t\tcali_info->delta_power_index[p] =\n\t\t\t\t\t\tdelta_swing_table_idx_tup_b\n\t\t\t\t\t\t[delta];\n\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =\n\t\t\t\t\t\tdelta_swing_table_idx_tup_b\n\t\t\t\t\t\t[delta];\n\t\t\t\t\t/*Record delta swing for mix mode*/\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t       \"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\tbreak;\n\n\t\t\t\tdefault:\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t       \"delta_swing_table_idx_tup_a[%d] = %d\\n\", delta, delta_swing_table_idx_tup_a[delta]);\n#if (RTL8721D_SUPPORT == 1)\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t       \"delta_swing_table_idx_tup_a_cck[%d] = %d\\n\", delta, delta_swing_table_idx_tup_a_cck[delta]);\n\n\t\t\t\t\tcali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_a_cck[delta];\n\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t       \"******Temp is higher and cali_info->absolute_cck_swing_idx[RF_PATH_A] = %d\\n\", cali_info->absolute_cck_swing_idx[p]);\n#endif\n\t\t\t\t\tcali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];\n\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =\n\t\t\t\t\tdelta_swing_table_idx_tup_a[delta];\n\t\t\t\t\t/*Record delta swing*/\n\t\t\t\t\t/*for mix mode power tracking*/\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t       \"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\t/* JJ ADD 20161014 */\n\t\t\tif (dm->support_ic_type == ODM_RTL8195B ||\n\t\t\t    dm->support_ic_type == ODM_RTL8721D) {\n\t\t\t\t/*Save xtal_offset from Xtal table*/\n\t\t\t\tcali_info->xtal_offset_last = cali_info->xtal_offset;\t/*recording last Xtal offset*/\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"[Xtal] delta_swing_table_xtal_up[%d] = %d\\n\", delta, delta_swing_table_xtal_up[delta]);\n\t\t\t\tcali_info->xtal_offset = delta_swing_table_xtal_up[delta];\n\t\t\t\txtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset);\n\t\t\t}\n\n\t\t} else {\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\t\t\tcali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/\n\n\t\t\t\tswitch (p) {\n\t\t\t\tcase RF_PATH_B:\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t       \"delta_swing_table_idx_tdown_b[%d] = %d\\n\", delta, delta_swing_table_idx_tdown_b[delta]);\n#if (RTL8721D_SUPPORT == 1)\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t       \"delta_swing_table_idx_tdown_b_cck[%d] = %d\\n\", delta, delta_swing_table_idx_tdown_b_cck[delta]);\n\n\t\t\t\t\tcali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b_cck[delta];\n\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t       \"******Temp is lower and cali_info->absolute_cck_swing_idx[RF_PATH_B] = %d\\n\", cali_info->absolute_cck_swing_idx[p]);\n#endif\n\t\t\t\t\tcali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];\n\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t       \"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\tbreak;\n\n\t\t\t\tdefault:\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t       \"delta_swing_table_idx_tdown_a[%d] = %d\\n\", delta, delta_swing_table_idx_tdown_a[delta]);\n#if (RTL8721D_SUPPORT == 1)\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t       \"delta_swing_table_idx_tdown_a_cck[%d] = %d\\n\", delta, delta_swing_table_idx_tdown_a_cck[delta]);\n\n\t\t\t\t\tcali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a_cck[delta];\n\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t       \"******Temp is lower and cali_info->absolute_cck_swing_idx[RF_PATH_A] = %d\\n\", cali_info->absolute_cck_swing_idx[p]);\n#endif\n\t\t\t\t\tcali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];\n\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t       \"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\t/* JJ ADD 20161014 */\n\n\t\t\tif (dm->support_ic_type == ODM_RTL8195B ||\n\t\t\t    dm->support_ic_type == ODM_RTL8721D) {\n\t\t\t\t/*Save xtal_offset from Xtal table*/\n\t\t\t\tcali_info->xtal_offset_last = cali_info->xtal_offset;\t/*recording last Xtal offset*/\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"[Xtal] delta_swing_table_xtal_down[%d] = %d\\n\", delta, delta_swing_table_xtal_down[delta]);\n\t\t\t\tcali_info->xtal_offset = delta_swing_table_xtal_down[delta];\n\t\t\t\txtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset);\n\t\t\t}\n\t\t}\n#if 0\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"\\n\\n=========================== [path-%d] Calculating power_index_offset===========================\\n\", p);\n\n\t\t\tif (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p])\t\t /*If Thermal value changes but lookup table value still the same*/\n\t\t\t\tcali_info->power_index_offset[p] = 0;\n\t\t\telse\n\t\t\t\tcali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p];\t\t/*Power index diff between 2 times Power Tracking*/\n\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\\n\", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]);\n\n\t\t\tcali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];\n\t\t\tcali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];\n\n\t\t\tcali_info->bb_swing_idx_cck = cali_info->CCK_index;\n\t\t\tcali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];\n\n\t\t\t/*************Print BB Swing base and index Offset*************/\n\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\\n\", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]);\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\\n\", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]);\n\n\t\t\t/*4 7.1 Handle boundary conditions of index.*/\n\n\t\t\tif (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)\n\t\t\t\tcali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;\n\t\t\telse if (cali_info->OFDM_index[p] <= OFDM_min_index)\n\t\t\t\tcali_info->OFDM_index[p] = OFDM_min_index;\n\t\t}\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"\\n\\n========================================================================================================\\n\");\n\n\t\tif (cali_info->CCK_index > c.swing_table_size_cck - 1)\n\t\t\tcali_info->CCK_index = c.swing_table_size_cck - 1;\n\t\telse if (cali_info->CCK_index <= 0)\n\t\t\tcali_info->CCK_index = 0;\n#endif\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\\n\",\n\t\t       cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value);\n\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\tcali_info->power_index_offset[p] = 0;\n\t}\n#if 0\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\\n\",\n\t       cali_info->CCK_index, cali_info->bb_swing_idx_cck_base);\t   /*Print Swing base & current*/\n\n\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\\n\",\n\t\t       cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);\n\t}\n#endif\n\tif (thermal_value > rf->eeprom_thermal) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"Temperature(%d) higher than PG value(%d)\\n\", thermal_value, rf->eeprom_thermal);\n\n\t\tif (dm->support_ic_type == ODM_RTL8188E ||\n\t\t    dm->support_ic_type == ODM_RTL8192E ||\n\t\t    dm->support_ic_type == ODM_RTL8821 ||\n\t\t    dm->support_ic_type == ODM_RTL8812 ||\n\t\t    dm->support_ic_type == ODM_RTL8723B ||\n\t\t    dm->support_ic_type == ODM_RTL8814A ||\n\t\t    dm->support_ic_type == ODM_RTL8703B ||\n\t\t    dm->support_ic_type == ODM_RTL8188F ||\n\t\t    dm->support_ic_type == ODM_RTL8822B ||\n\t\t    dm->support_ic_type == ODM_RTL8723D ||\n\t\t    dm->support_ic_type == ODM_RTL8821C ||\n\t\t    dm->support_ic_type == ODM_RTL8710B ||\n\t\t    dm->support_ic_type == ODM_RTL8192F ||\n\t\t    dm->support_ic_type == ODM_RTL8195B ||\n\t\t    dm->support_ic_type == ODM_RTL8721D){\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking MIX_MODE**********\\n\");\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t\t} else {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking BBSWING_MODE**********\\n\");\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);\n\t\t}\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"Temperature(%d) lower than PG value(%d)\\n\", thermal_value, rf->eeprom_thermal);\n\n\t\tif (dm->support_ic_type == ODM_RTL8188E ||\n\t\t    dm->support_ic_type == ODM_RTL8192E ||\n\t\t    dm->support_ic_type == ODM_RTL8821 ||\n\t\t    dm->support_ic_type == ODM_RTL8812 ||\n\t\t    dm->support_ic_type == ODM_RTL8723B ||\n\t\t    dm->support_ic_type == ODM_RTL8814A ||\n\t\t    dm->support_ic_type == ODM_RTL8703B ||\n\t\t    dm->support_ic_type == ODM_RTL8188F ||\n\t\t    dm->support_ic_type == ODM_RTL8822B ||\n\t\t    dm->support_ic_type == ODM_RTL8723D ||\n\t\t    dm->support_ic_type == ODM_RTL8821C ||\n\t\t    dm->support_ic_type == ODM_RTL8710B ||\n\t\t    dm->support_ic_type == ODM_RTL8192F ||\n\t\t    dm->support_ic_type == ODM_RTL8195B ||\n\t\t    dm->support_ic_type == ODM_RTL8721D) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking MIX_MODE**********\\n\");\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel);\n\t\t} else {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking BBSWING_MODE**********\\n\");\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);\n\t\t}\n\n\t\tcali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;    /*Record last time Power Tracking result as base.*/\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\tcali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"cali_info->thermal_value = %d thermal_value= %d\\n\", cali_info->thermal_value, thermal_value);\n\n\t\tcali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/\n\t}\n\n\t/* JJ ADD 20161014 */\n\tif (dm->support_ic_type == ODM_RTL8195B ||\n\t    dm->support_ic_type == ODM_RTL8721D) {\n\t\tif (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (rf->eeprom_thermal != 0xff)) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter Xtal Tracking**********\\n\");\n\n\t\t\tif (thermal_value > rf->eeprom_thermal) {\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"Temperature(%d) higher than PG value(%d)\\n\", thermal_value, rf->eeprom_thermal);\n\t\t\t\t(*c.odm_txxtaltrack_set_xtal)(dm);\n\t\t\t} else {\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t       \"Temperature(%d) lower than PG value(%d)\\n\", thermal_value, rf->eeprom_thermal);\n\t\t\t\t(*c.odm_txxtaltrack_set_xtal)(dm);\n\t\t\t}\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********End Xtal Tracking**********\\n\");\n\t\t}\n\t}\n#if (!RTL8721D_SUPPORT)\n\t/* Wait sacn to do IQK by RF Jenyu*/\n\tif ((!*dm->is_scan_in_process) && (!iqk_info->rfk_forbidden)) {\n\t\t/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/\n\t\tif (delta_IQK >= c.threshold_iqk) {\n\t\t\tcali_info->thermal_value_iqk = thermal_value;\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"delta_IQK(%d) >= threshold_iqk(%d)\\n\", delta_IQK, c.threshold_iqk);\n\t\t\tif (!cali_info->is_iqk_in_progress)\n\t\t\t\t(*c.do_iqk)(dm, delta_IQK, thermal_value, 8);\n\t\t}\n\t}\n#endif\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"<===odm_txpowertracking_callback_thermal_meter\\n\");\n\n\tcali_info->tx_powercount = 0;\n}\n\n/* 3============================================================\n * 3 IQ Calibration\n * 3============================================================\n */\n\nvoid\nodm_reset_iqk_result(\n\tvoid\t\t\t\t\t*dm_void\n)\n{\n\treturn;\n}\n\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\nu8 odm_get_right_chnl_place_for_iqk(u8 chnl)\n{\n\tu8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {\n\t\t1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,\n\t\t36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64,\n\t\t100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122,\n\t\t124, 126, 128, 130, 132, 134, 136, 138, 140,\n\t\t149, 151, 153, 155, 157, 159, 161, 163, 165};\n\tu8 place = chnl;\n\n\tif (chnl > 14) {\n\t\tfor (place = 14; place < sizeof(channel_all); place++) {\n\t\t\tif (channel_all[place] == chnl)\n\t\t\t\treturn place - 13;\n\t\t}\n\t}\n\treturn 0;\n}\n#endif\n\nvoid\nodm_iq_calibrate(\n\tstruct dm_struct\t*dm\n)\n{\n#if (RTL8721D_SUPPORT == 1)\n\tstruct dm_iqk_info\t*iqk_info = &dm->IQK_info;\n\n\tif (dm->is_linked && !iqk_info->rfk_forbidden) {\n\t\tif ((*dm->channel != dm->pre_channel) &&\n\t\t    (!*dm->is_scan_in_process)) {\n\t\t\tdm->pre_channel = *dm->channel;\n\t\t\tdm->linked_interval = 0;\n\t\t}\n\n\t\tif (dm->linked_interval < 3)\n\t\t\tdm->linked_interval++;\n\n\t\tif (dm->linked_interval == 2)\n\t\t\thalrf_iqk_trigger(dm, false);\n\t} else {\n\t\tdm->linked_interval = 0;\n\t}\n#endif\n}\n\nvoid phydm_rf_init(void\t\t*dm_void)\n{\n\tstruct dm_struct\t*dm = (struct dm_struct *)dm_void;\n\n\todm_txpowertracking_init(dm);\n\t\n\todm_clear_txpowertracking_state(dm);\n}\n\nvoid phydm_rf_watchdog(void\t\t*dm_void)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\n\todm_txpowertracking_check(dm);\n#if (RTL8721D_SUPPORT == 1)\n\todm_iq_calibrate(dm);\n#endif\n}\n"
  },
  {
    "path": "hal/phydm/halrf/halphyrf_iot.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALPHYRF_H__\n#define __HALPHYRF_H__\n\n#include \"halrf/halrf_kfree.h\"\n\n#if (RTL8821C_SUPPORT == 1)\n\t#include \"halrf/rtl8821c/halrf_iqk_8821c.h\"\n#endif\n\n#if (RTL8195B_SUPPORT == 1)\n//\t#include \"halrf/rtl8195b/halrf.h\"\n\t#include \"halrf/rtl8195b/halrf_iqk_8195b.h\"\n\t#include \"halrf/rtl8195b/halrf_txgapk_8195b.h\"\n\t#include \"halrf/rtl8195b/halrf_dpk_8195b.h\"\n#endif\n\n#include \"halrf/halrf_powertracking_iot.h\"\n\n\nenum spur_cal_method {\n\tPLL_RESET,\n\tAFE_PHASE_SEL\n};\n\nenum pwrtrack_method {\n\tBBSWING,\n\tTXAGC,\n\tMIX_MODE,\n\tTSSI_MODE,\n\tMIX_2G_TSSI_5G_MODE,\n\tMIX_5G_TSSI_2G_MODE\n};\n\ntypedef void\t(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);\ntypedef void(*func_iqk)(void *, u8, u8, u8);\ntypedef void\t(*func_lck)(void *);\n#if (RTL8721D_SUPPORT == 1)\n\ttypedef void\t(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **,\n\t\t\t\t      u8 **, u8 **, u8 **, u8 **);\n#else\n\ttypedef void\t(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);\n#endif\ntypedef void\t(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);\ntypedef void(*func_swing_xtal)(void *, s8 **, s8 **);\ntypedef void(*func_set_xtal)(void *);\n\nstruct txpwrtrack_cfg {\n\tu8\t\tswing_table_size_cck;\n\tu8\t\tswing_table_size_ofdm;\n\tu8\t\tthreshold_iqk;\n\tu8\t\tthreshold_dpk;\n\tu8\t\taverage_thermal_num;\n\tu8\t\trf_path_count;\n\tu32\t\tthermal_reg_addr;\n\tfunc_set_pwr\todm_tx_pwr_track_set_pwr;\n\tfunc_iqk\tdo_iqk;\n\tfunc_lck\t\tphy_lc_calibrate;\n\tfunc_swing\tget_delta_swing_table;\n\tfunc_swing8814only\tget_delta_swing_table8814only;\n\tfunc_swing_xtal\t\t\tget_delta_swing_xtal_table;\n\tfunc_set_xtal\t\t\todm_txxtaltrack_set_xtal;\n};\n\nvoid\nconfigure_txpower_track(\n\tvoid\t\t\t\t\t*dm_void,\n\tstruct txpwrtrack_cfg\t*config\n);\n\n\nvoid\nodm_clear_txpowertracking_state(\n\tvoid\t\t\t\t\t*dm_void\n);\n\nvoid\nodm_txpowertracking_callback_thermal_meter(\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\tvoid\t\t\t\t\t*dm_void\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\tvoid\t*dm\n#else\n\tvoid\t*adapter\n#endif\n);\n\n\n\n#define ODM_TARGET_CHNL_NUM_2G_5G\t59\n\n\nvoid\nodm_reset_iqk_result(\n\tvoid\t\t\t\t\t*dm_void\n);\nu8\nodm_get_right_chnl_place_for_iqk(\n\tu8 chnl\n);\n\nvoid phydm_rf_init(void\t\t\t\t\t*dm_void);\nvoid phydm_rf_watchdog(void\t\t\t\t\t*dm_void);\n\n#endif\t/*#ifndef __HALPHYRF_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/halphyrf_win.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#define\tCALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \\\n\tdo {\\\n\t\tfor (_offset = 0; _offset < _size; _offset++) { \\\n\t\t\t\\\n\t\t\tif (_delta_thermal < thermal_threshold[_direction][_offset]) { \\\n\t\t\t\t\\\n\t\t\t\tif (_offset != 0)\\\n\t\t\t\t\t_offset--;\\\n\t\t\t\tbreak;\\\n\t\t\t} \\\n\t\t}\t\t\t\\\n\t\tif (_offset >= _size)\\\n\t\t\t_offset = _size-1;\\\n\t} while (0)\n\nvoid configure_txpower_track(\n\tstruct dm_struct\t\t*dm,\n\tstruct txpwrtrack_cfg\t*config\n)\n{\n#if RTL8192E_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8192E)\n\t\tconfigure_txpower_track_8192e(config);\n#endif\n#if RTL8821A_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8821)\n\t\tconfigure_txpower_track_8821a(config);\n#endif\n#if RTL8812A_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8812)\n\t\tconfigure_txpower_track_8812a(config);\n#endif\n#if RTL8188E_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8188E)\n\t\tconfigure_txpower_track_8188e(config);\n#endif\n\n#if RTL8188F_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8188F)\n\t\tconfigure_txpower_track_8188f(config);\n#endif\n\n#if RTL8723B_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8723B)\n\t\tconfigure_txpower_track_8723b(config);\n#endif\n\n#if RTL8814A_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8814A)\n\t\tconfigure_txpower_track_8814a(config);\n#endif\n\n#if RTL8703B_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8703B)\n\t\tconfigure_txpower_track_8703b(config);\n#endif\n\n#if RTL8822B_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8822B)\n\t\tconfigure_txpower_track_8822b(config);\n#endif\n\n#if RTL8723D_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8723D)\n\t\tconfigure_txpower_track_8723d(config);\n#endif\n\n/* JJ ADD 20161014 */\n#if RTL8710B_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8710B)\n\t\tconfigure_txpower_track_8710b(config);\n#endif\n\n#if RTL8821C_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8821C)\n\t\tconfigure_txpower_track_8821c(config);\n#endif\n\n#if RTL8192F_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8192F)\n\t\tconfigure_txpower_track_8192f(config);\n#endif\n\n#if RTL8822C_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8822C)\n\t\tconfigure_txpower_track_8822c(config);\n#endif\n\n#if RTL8814B_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8814B)\n\t\tconfigure_txpower_track_8814b(config);\n#endif\n\n\n}\n\n/* **********************************************************************\n * <20121113, Kordan> This function should be called when tx_agc changed.\n * Otherwise the previous compensation is gone, because we record the\n * delta of temperature between two TxPowerTracking watch dogs.\n *\n * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still\n * need to call this function.\n * ********************************************************************** */\nvoid\nodm_clear_txpowertracking_state(\n\tstruct dm_struct\t\t*dm\n)\n{\n\tPHAL_DATA_TYPE\thal_data = GET_HAL_DATA((PADAPTER)(dm->adapter));\n\tu8\t\t\tp = 0;\n\tstruct dm_rf_calibration_struct\t*cali_info = &(dm->rf_calibrate_info);\n\n\tcali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;\n\tcali_info->bb_swing_idx_cck = cali_info->default_cck_index;\n\tcali_info->CCK_index = 0;\n\n\tfor (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {\n\t\tcali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;\n\t\tcali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;\n\t\tcali_info->OFDM_index[p] = cali_info->default_ofdm_index;\n\n\t\tcali_info->power_index_offset[p] = 0;\n\t\tcali_info->delta_power_index[p] = 0;\n\t\tcali_info->delta_power_index_last[p] = 0;\n\n\t\tcali_info->absolute_ofdm_swing_idx[p] = 0;    /* Initial Mix mode power tracking*/\n\t\tcali_info->remnant_ofdm_swing_idx[p] = 0;\n\t\tcali_info->kfree_offset[p] = 0;\n\t}\n\n\tcali_info->modify_tx_agc_flag_path_a = false;       /*Initial at Modify Tx Scaling mode*/\n\tcali_info->modify_tx_agc_flag_path_b = false;       /*Initial at Modify Tx Scaling mode*/\n\tcali_info->modify_tx_agc_flag_path_c = false;       /*Initial at Modify Tx Scaling mode*/\n\tcali_info->modify_tx_agc_flag_path_d = false;       /*Initial at Modify Tx Scaling mode*/\n\tcali_info->remnant_cck_swing_idx = 0;\n\tcali_info->thermal_value = hal_data->eeprom_thermal_meter;\n\n\tcali_info->modify_tx_agc_value_cck = 0;\t\t\t/* modify by Mingzhi.Guo */\n\tcali_info->modify_tx_agc_value_ofdm = 0;\t\t/* modify by Mingzhi.Guo */\n\n}\n\nvoid\nodm_txpowertracking_callback_thermal_meter(\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\tstruct dm_struct\t\t*dm\n#else\n\tvoid\t*adapter\n#endif\n)\n{\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\n\tHAL_DATA_TYPE\t*hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tstruct dm_struct\t\t*dm = &hal_data->DM_OutSrc;\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tstruct dm_struct\t\t*dm = &hal_data->odmpriv;\n#endif\n#endif\n\n\tstruct dm_rf_calibration_struct\t*cali_info = &(dm->rf_calibrate_info);\n \tstruct dm_iqk_info\t*iqk_info = &dm->IQK_info;\n\tu8\t\t\tthermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;\n\ts8\t\t\tdiff_DPK[4] = {0};\n\tu8\t\t\tthermal_value_avg_count = 0;\n\tu32\t\t\tthermal_value_avg = 0, regc80, regcd0, regcd4, regab4, regc88, rege14, reg848,reg838, reg86c;\n\n\tu8\t\t\tOFDM_min_index = 0;  /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */\n\tu8\t\t\tindexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */\n\tu8\t\t\tpower_tracking_type = hal_data->RfPowerTrackingType;\n\tu8\t\t\txtal_offset_eanble = 0;\n\ts8\t\t\tthermal_value_temp = 0;\n\n\tstruct txpwrtrack_cfg\tc;\n\n\t/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */\n\tu8\t\t\t*delta_swing_table_idx_tup_a = NULL;\n\tu8\t\t\t*delta_swing_table_idx_tdown_a = NULL;\n\tu8\t\t\t*delta_swing_table_idx_tup_b = NULL;\n\tu8\t\t\t*delta_swing_table_idx_tdown_b = NULL;\n\t/*for 8814 add by Yu Chen*/\n\tu8\t\t\t*delta_swing_table_idx_tup_c = NULL;\n\tu8\t\t\t*delta_swing_table_idx_tdown_c = NULL;\n\tu8\t\t\t*delta_swing_table_idx_tup_d = NULL;\n\tu8\t\t\t*delta_swing_table_idx_tdown_d = NULL;\n\t/*for Xtal Offset by James.Tung*/\n\ts8\t\t\t*delta_swing_table_xtal_up = NULL;\n\ts8\t\t\t*delta_swing_table_xtal_down = NULL;\n\n\t/* 4 2. Initilization ( 7 steps in total ) */\n\n\tconfigure_txpower_track(dm, &c);\n\n\t(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,\n\t\t(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);\n\n\tif (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8814B))\t/*for 8814 path C & D*/\n\t\t(*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,\n\t\t\t(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);\n\t/* JJ ADD 20161014 */\n\tif (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F))\t/*for Xtal Offset*/\n\t\t(*c.get_delta_swing_xtal_table)(dm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down);\n\n\n\tcali_info->txpowertracking_callback_cnt++;\t/*cosa add for debug*/\n\tcali_info->is_txpowertracking_init = true;\n\n\t/*cali_info->txpowertrack_control = hal_data->txpowertrack_control;\n\t<Kordan> We should keep updating the control variable according to HalData.\n\t<Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n#if (MP_DRIVER == 1)\n\tcali_info->rega24 = 0x090e1317;\n#endif\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\tif (*(dm->mp_mode) == true)\n\t\tcali_info->rega24 = 0x090e1317;\n#endif\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"===>odm_txpowertracking_callback_thermal_meter\\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\\n\",\n\t\tcali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"cali_info->txpowertrack_control=%d,  hal_data->eeprom_thermal_meter %d\\n\", cali_info->txpowertrack_control,  hal_data->eeprom_thermal_meter);\n\tthermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);\t/* 0x42: RF Reg[15:10] 88E */\n\n\tthermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"thermal_value_temp(%d) = thermal_value(%d) + power_time_thermal(%d)\\n\", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));\n\n\tif (thermal_value_temp > 63)\n\t\tthermal_value = 63;\n\telse if (thermal_value_temp < 0)\n\t\tthermal_value = 0;\n\telse\n\t\tthermal_value = thermal_value_temp;\n\n\t/*add log by zhao he, check c80/c94/c14/ca0 value*/\n\tif (dm->support_ic_type == ODM_RTL8723D) {\n\t\tregc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);\n\t\tregcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);\n\t\tregcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);\n\t\tregab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\\n\", regc80, regcd0, regcd4, regab4);\n\t}\n\n\t/* JJ ADD 20161014 */\n\tif (dm->support_ic_type == ODM_RTL8710B) {\n\t\tregc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);\n\t\tregcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);\n\t\tregcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);\n\t\tregab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\\n\", regc80, regcd0, regcd4, regab4);\n\t}\n\t/* Winnita add 20171205 */\n\tif (dm->support_ic_type == ODM_RTL8192F) {\n\t\tregc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);\n\t\tregc88 = odm_get_bb_reg(dm, R_0xc88, MASKDWORD);\n\t\tregab4 = odm_get_bb_reg(dm, R_0xab4, MASKDWORD);\n\t\trege14 = odm_get_bb_reg(dm, R_0xe14, MASKDWORD);\n\t\treg848 = odm_get_bb_reg(dm, R_0x848, MASKDWORD);\n\t\treg838 = odm_get_bb_reg(dm, R_0x838, MASKDWORD);\n\t\treg86c = odm_get_bb_reg(dm, R_0x86c, MASKDWORD);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"0xc80 = 0x%x 0xc88 = 0x%x 0xab4 = 0x%x 0xe14 = 0x%x\\n\", regc80, regc88, regab4, rege14);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"0x848 = 0x%x 0x838 = 0x%x 0x86c = 0x%x\\n\", reg848, reg838, reg86c);\n\t}\n\n\tif (!cali_info->txpowertrack_control)\n\t\treturn;\n\n\tif (hal_data->eeprom_thermal_meter == 0xff) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"no pg, hal_data->eeprom_thermal_meter = 0x%x\\n\", hal_data->eeprom_thermal_meter);\n\t\treturn;\n\t}\n\n\t/*4 3. Initialize ThermalValues of rf_calibrate_info*/\n\n\tif (cali_info->is_reloadtxpowerindex)\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"reload ofdm index for band switch\\n\");\n\n\t/*4 4. Calculate average thermal meter*/\n\n\tcali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value;\n\tcali_info->thermal_value_avg_index++;\n\tif (cali_info->thermal_value_avg_index == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/\n\t\tcali_info->thermal_value_avg_index = 0;\n\n\tfor (i = 0; i < c.average_thermal_num; i++) {\n\t\tif (cali_info->thermal_value_avg[i]) {\n\t\t\tthermal_value_avg += cali_info->thermal_value_avg[i];\n\t\t\tthermal_value_avg_count++;\n\t\t}\n\t}\n\n\tif (thermal_value_avg_count) {            /* Calculate Average thermal_value after average enough times */\n\t\tthermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);\n\t\tcali_info->thermal_value_delta = thermal_value - hal_data->eeprom_thermal_meter;\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\"AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\\n\", thermal_value, hal_data->eeprom_thermal_meter);\n\t}\n\n\t/* 4 5. Calculate delta, delta_LCK, delta_IQK. */\n\n\t/* \"delta\" here is used to determine whether thermal value changes or not. */\n\tdelta\t= (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value);\n\tdelta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);\n\tdelta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);\n\n\tif (cali_info->thermal_value_iqk == 0xff) {\t/*no PG, use thermal value for IQK*/\n\t\tcali_info->thermal_value_iqk = thermal_value;\n\t\tdelta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"no PG, use thermal_value for IQK\\n\");\n\t}\n\n\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\tdiff_DPK[p] = (s8)thermal_value - (s8)cali_info->dpk_thermal[p];\n\n\t/*4 6. If necessary, do LCK.*/\n\n\tif (!(dm->support_ic_type & ODM_RTL8821)) {\t/*no PG, do LCK at initial status*/\n\t\tif (cali_info->thermal_value_lck == 0xff) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"no PG, do LCK\\n\");\n\t\t\tcali_info->thermal_value_lck = thermal_value;\n\n\t\t\t/*Use RTLCK, so close power tracking driver LCK*/\n\t\t\tif ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {\n\t\t\t\tif (c.phy_lc_calibrate)\n\t\t\t\t\t(*c.phy_lc_calibrate)(dm);\n\t\t\t}\n\n\t\t\tdelta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);\n\t\t}\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\\n\", delta, delta_LCK, delta_IQK);\n\n\t\t/* Wait sacn to do LCK by RF Jenyu*/\n\t\tif( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {\n\t\t\t/* Delta temperature is equal to or larger than 20 centigrade.*/\n\t\t\tif (delta_LCK >= c.threshold_iqk) {\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"delta_LCK(%d) >= threshold_iqk(%d)\\n\", delta_LCK, c.threshold_iqk);\n\t\t\t\tcali_info->thermal_value_lck = thermal_value;\n\n\t\t\t\t/*Use RTLCK, so close power tracking driver LCK*/\n\t\t\t\tif ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {\n\t\t\t\t\tif (c.phy_lc_calibrate)\n\t\t\t\t\t\t(*c.phy_lc_calibrate)(dm);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t/*3 7. If necessary, move the index of swing table to adjust Tx power.*/\n\n\tif (delta > 0 && cali_info->txpowertrack_control) {\n\t\t/* \"delta\" here is used to record the absolute value of differrence. */\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\t\tdelta = thermal_value > hal_data->eeprom_thermal_meter ? (thermal_value - hal_data->eeprom_thermal_meter) : (hal_data->eeprom_thermal_meter - thermal_value);\n#else\n\t\tdelta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value);\n#endif\n\t\tif (delta >= TXPWR_TRACK_TABLE_SIZE)\n\t\t\tdelta = TXPWR_TRACK_TABLE_SIZE - 1;\n\n\t\t/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\t\tif (thermal_value > hal_data->eeprom_thermal_meter) {\n#else\n\t\tif (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {\n#endif\n\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\t\t\tcali_info->delta_power_index_last[p] = cali_info->delta_power_index[p];\t/*recording poer index offset*/\n\t\t\t\tswitch (p) {\n\t\t\t\tcase RF_PATH_B:\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\t\"delta_swing_table_idx_tup_b[%d] = %d\\n\", delta, delta_swing_table_idx_tup_b[delta]);\n\n\t\t\t\t\tcali_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta];\n\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_b[delta];       /*Record delta swing for mix mode power tracking*/\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\t\"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase RF_PATH_C:\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\t\"delta_swing_table_idx_tup_c[%d] = %d\\n\", delta, delta_swing_table_idx_tup_c[delta]);\n\n\t\t\t\t\tcali_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta];\n\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_c[delta];       /*Record delta swing for mix mode power tracking*/\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\t\"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase RF_PATH_D:\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\t\"delta_swing_table_idx_tup_d[%d] = %d\\n\", delta, delta_swing_table_idx_tup_d[delta]);\n\n\t\t\t\t\tcali_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta];\n\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_d[delta];       /*Record delta swing for mix mode power tracking*/\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\t\"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\tbreak;\n\n\t\t\t\tdefault:\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\t\"delta_swing_table_idx_tup_a[%d] = %d\\n\", delta, delta_swing_table_idx_tup_a[delta]);\n\n\t\t\t\t\tcali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];\n\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_a[delta];        /*Record delta swing for mix mode power tracking*/\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\t\"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\t/* JJ ADD 20161014 */\n\t\t\tif (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) {\n\t\t\t\t/*Save xtal_offset from Xtal table*/\n\t\t\t\tcali_info->xtal_offset_last = cali_info->xtal_offset;\t/*recording last Xtal offset*/\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\"[Xtal] delta_swing_table_xtal_up[%d] = %d\\n\", delta, delta_swing_table_xtal_up[delta]);\n\t\t\t\tcali_info->xtal_offset = delta_swing_table_xtal_up[delta];\n\n\t\t\t\tif (cali_info->xtal_offset_last == cali_info->xtal_offset)\n\t\t\t\t\txtal_offset_eanble = 0;\n\t\t\t\telse\n\t\t\t\t\txtal_offset_eanble = 1;\n\t\t\t}\n\n\t\t} else {\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\t\t\tcali_info->delta_power_index_last[p] = cali_info->delta_power_index[p];\t/*recording poer index offset*/\n\n\t\t\t\tswitch (p) {\n\t\t\t\tcase RF_PATH_B:\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\t\"delta_swing_table_idx_tdown_b[%d] = %d\\n\", delta, delta_swing_table_idx_tdown_b[delta]);\n\t\t\t\t\tcali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];\n\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_b[delta];        /*Record delta swing for mix mode power tracking*/\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\t\"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase RF_PATH_C:\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\t\"delta_swing_table_idx_tdown_c[%d] = %d\\n\", delta, delta_swing_table_idx_tdown_c[delta]);\n\t\t\t\t\tcali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta];\n\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_c[delta];        /*Record delta swing for mix mode power tracking*/\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\t\"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase RF_PATH_D:\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\t\"delta_swing_table_idx_tdown_d[%d] = %d\\n\", delta, delta_swing_table_idx_tdown_d[delta]);\n\t\t\t\t\tcali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta];\n\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_d[delta];        /*Record delta swing for mix mode power tracking*/\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\t\"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\tbreak;\n\n\t\t\t\tdefault:\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\t\"delta_swing_table_idx_tdown_a[%d] = %d\\n\", delta, delta_swing_table_idx_tdown_a[delta]);\n\t\t\t\t\tcali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];\n\t\t\t\t\tcali_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_a[delta];        /*Record delta swing for mix mode power tracking*/\n\t\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\t\"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\\n\", cali_info->absolute_ofdm_swing_idx[p]);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\t/* JJ ADD 20161014 */\n\t\t\tif (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) {\n\t\t\t\t/*Save xtal_offset from Xtal table*/\n\t\t\t\tcali_info->xtal_offset_last = cali_info->xtal_offset;\t/*recording last Xtal offset*/\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\"[Xtal] delta_swing_table_xtal_down[%d] = %d\\n\", delta, delta_swing_table_xtal_down[delta]);\n\t\t\t\tcali_info->xtal_offset = delta_swing_table_xtal_down[delta];\n\n\t\t\t\tif (cali_info->xtal_offset_last == cali_info->xtal_offset)\n\t\t\t\t\txtal_offset_eanble = 0;\n\t\t\t\telse\n\t\t\t\t\txtal_offset_eanble = 1;\n\t\t\t}\n\n\t\t}\n\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"\\n\\n=========================== [path-%d] Calculating power_index_offset===========================\\n\", p);\n\n\t\t\tif (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p])         /*If Thermal value changes but lookup table value still the same*/\n\t\t\t\tcali_info->power_index_offset[p] = 0;\n\t\t\telse\n\t\t\t\tcali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p];      /*Power index diff between 2 times Power Tracking*/\n\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\\n\", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]);\n\n\t\t\tcali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];\n\t\t\tcali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];\n\n\t\t\tcali_info->bb_swing_idx_cck = cali_info->CCK_index;\n\t\t\tcali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];\n\n\t\t\t/*************Print BB Swing base and index Offset*************/\n\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\\n\", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]);\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\\n\", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]);\n\n\t\t\t/*4 7.1 Handle boundary conditions of index.*/\n\n\t\t\tif (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)\n\t\t\t\tcali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;\n\t\t\telse if (cali_info->OFDM_index[p] <= OFDM_min_index)\n\t\t\t\tcali_info->OFDM_index[p] = OFDM_min_index;\n\t\t}\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\"\\n\\n========================================================================================================\\n\");\n\n\t\tif (cali_info->CCK_index > c.swing_table_size_cck - 1)\n\t\t\tcali_info->CCK_index = c.swing_table_size_cck - 1;\n\t\telse if (cali_info->CCK_index <= 0)\n\t\t\tcali_info->CCK_index = 0;\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\"The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\\n\",\n\t\t\tcali_info->txpowertrack_control, thermal_value, cali_info->thermal_value);\n\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\tcali_info->power_index_offset[p] = 0;\n\t}\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\\n\",\n\t\tcali_info->CCK_index, cali_info->bb_swing_idx_cck_base);       /*Print Swing base & current*/\n\n\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\\n\",\n\t\t\tcali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);\n\t}\n\n\tif (dm->support_ic_type & ODM_RTL8814B)\n\t\tpower_tracking_type = TSSI_MODE;\n\n\tif (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8814B)) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"power_tracking_type=%d\\n\", power_tracking_type);\n\n\t\tif (power_tracking_type == 0) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking MIX_MODE**********\\n\");\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t\t} else if (power_tracking_type == 1) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\\n\");\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_2G_TSSI_5G_MODE, p, 0);\n\t\t} else if (power_tracking_type == 2) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\\n\");\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_5G_TSSI_2G_MODE, p, 0);\n\t\t} else if (power_tracking_type == 3) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking TSSI MODE**********\\n\");\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0);\n\t\t}\n\t\tcali_info->thermal_value = thermal_value;         /*Record last Power Tracking Thermal value*/\n\n\t} else if ((cali_info->power_index_offset[RF_PATH_A] != 0 ||\n\t\tcali_info->power_index_offset[RF_PATH_B] != 0 ||\n\t\tcali_info->power_index_offset[RF_PATH_C] != 0 ||\n\t\tcali_info->power_index_offset[RF_PATH_D] != 0) &&\n\t\tcali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {\n\t\t/* 4 7.2 Configure the Swing Table to adjust Tx Power. */\n\n\t\tcali_info->is_tx_power_changed = true;\t/*Always true after Tx Power is adjusted by power tracking.*/\n\t\t/*  */\n\t\t/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */\n\t\t/* to increase TX power. Otherwise, EVM will be bad. */\n\t\t/*  */\n\t\t/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */\n\t\tif (thermal_value > cali_info->thermal_value) {\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\"Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\\n\",\n\t\t\t\t\tp, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);\n\t\t\t}\n\t\t} else if (thermal_value < cali_info->thermal_value) {\t/*Low temperature*/\n\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\"Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\\n\",\n\t\t\t\t\tp, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);\n\t\t\t}\n\t\t}\n\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\n\t\tif (thermal_value > hal_data->eeprom_thermal_meter)\n#else\n\t\tif (thermal_value > dm->priv->pmib->dot11RFEntry.ther)\n#endif\n\t\t{\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"Temperature(%d) higher than PG value(%d)\\n\", thermal_value, hal_data->eeprom_thermal_meter);\n\n\t\t\tif (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||\n\t\t\t    dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||\n\t\t\t    dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||\n\t\t\t    dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B ||\n\t\t\t    dm->support_ic_type == ODM_RTL8192F) {\n\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking MIX_MODE**********\\n\");\n\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t\t\t} else {\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking BBSWING_MODE**********\\n\");\n\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);\n\t\t\t}\n\t\t} else {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"Temperature(%d) lower than PG value(%d)\\n\", thermal_value, hal_data->eeprom_thermal_meter);\n\n\t\t\tif (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||\n\t\t\t    dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||\n\t\t\t    dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||\n\t\t\t    dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B ||\n\t\t\t\tdm->support_ic_type == ODM_RTL8192F) {\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking MIX_MODE**********\\n\");\n\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel);\n\t\t\t} else {\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking BBSWING_MODE**********\\n\");\n\t\t\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);\n\t\t\t}\n\n\t\t}\n\n\t\tcali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;    /*Record last time Power Tracking result as base.*/\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\tcali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\"cali_info->thermal_value = %d thermal_value= %d\\n\", cali_info->thermal_value, thermal_value);\n\n\t\tcali_info->thermal_value = thermal_value;         /*Record last Power Tracking Thermal value*/\n\n\t}\n\n\n\tif (dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D ||\n\t\tdm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */\n\n\t\tif (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {\n\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter Xtal Tracking**********\\n\");\n\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\n\t\t\tif (thermal_value > hal_data->eeprom_thermal_meter) {\n#else\n\t\t\tif (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {\n#endif\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\"Temperature(%d) higher than PG value(%d)\\n\", thermal_value, hal_data->eeprom_thermal_meter);\n\t\t\t\t(*c.odm_txxtaltrack_set_xtal)(dm);\n\t\t\t} else {\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\t\"Temperature(%d) lower than PG value(%d)\\n\", thermal_value, hal_data->eeprom_thermal_meter);\n\t\t\t\t(*c.odm_txxtaltrack_set_xtal)(dm);\n\t\t\t}\n\t\t}\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********End Xtal Tracking**********\\n\");\n\t}\n\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\n\n\t/* Wait sacn to do IQK by RF Jenyu*/\n\tif ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {\n\t\tif (!IS_HARDWARE_TYPE_8723B(adapter)) {\n\t\t\t/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/\n\t\t\tif (delta_IQK >= c.threshold_iqk) {\n\t\t\t\tcali_info->thermal_value_iqk = thermal_value;\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"delta_IQK(%d) >= threshold_iqk(%d)\\n\", delta_IQK, c.threshold_iqk);\n\t\t\t\tif (!cali_info->is_iqk_in_progress)\n\t\t\t\t\t(*c.do_iqk)(dm, delta_IQK, thermal_value, 8);\n\t\t\t}\n\t\t}\n\t}\n\tif (cali_info->dpk_thermal[RF_PATH_A] != 0) {\n\t\tif (diff_DPK[RF_PATH_A] >= c.threshold_dpk) {\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk));\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);\n\t\t} else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) {\n\t\t\ts32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk);\n\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);\n\t\t}\n\t}\n\tif (cali_info->dpk_thermal[RF_PATH_B] != 0) {\n\t\tif (diff_DPK[RF_PATH_B] >= c.threshold_dpk) {\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk));\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);\n\t\t} else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) {\n\t\t\ts32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk);\n\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);\n\t\t}\n\t}\n\n#endif\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"<===odm_txpowertracking_callback_thermal_meter\\n\");\n\n\tcali_info->tx_powercount = 0;\n}\n\n#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)\nvoid\nodm_txpowertracking_new_callback_thermal_meter(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);\n \tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\tu8 thermal_value[MAX_RF_PATH] = {0}, delta[MAX_RF_PATH] = {0};\n\tu8 delta_swing_table_idx_tup[DELTA_SWINGIDX_SIZE] = {0};\n\tu8 delta_swing_table_idx_tdown[DELTA_SWINGIDX_SIZE] = {0};\n\tu8 delta_LCK = 0, delta_IQK = 0, i = 0, j = 0, p;\n\tu8 thermal_value_avg_count[MAX_RF_PATH] = {0};\n\tu32 thermal_value_avg[MAX_RF_PATH] = {0};\n\ts8 thermal_value_temp[MAX_RF_PATH] = {0};\n\tu8 tracking_method = MIX_MODE;\n\n\tstruct txpwrtrack_cfg c;\n\n\tu8 *delta_swing_table_idx_tup_a = NULL;\n\tu8 *delta_swing_table_idx_tdown_a = NULL;\n\tu8 *delta_swing_table_idx_tup_b = NULL;\n\tu8 *delta_swing_table_idx_tdown_b = NULL;\n\tu8 *delta_swing_table_idx_tup_c = NULL;\n\tu8 *delta_swing_table_idx_tdown_c = NULL;\n\tu8 *delta_swing_table_idx_tup_d = NULL;\n\tu8 *delta_swing_table_idx_tdown_d = NULL;\n\n\tconfigure_txpower_track(dm, &c);\n\n\t(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,\n\t\t(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);\n\n\tif (dm->support_ic_type == ODM_RTL8814B) {\n\t\t(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,\n\t\t\t(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);\n\t}\n\n\tcali_info->txpowertracking_callback_cnt++;\n\tcali_info->is_txpowertracking_init = true;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"===>odm_txpowertracking_callback_thermal_meter\\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\\n\",\n\t\tcali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"cali_info->txpowertrack_control=%d, tssi->thermal[RF_PATH_A]=%d tssi->thermal[RF_PATH_B]=%d\\n\",\n\t\tcali_info->txpowertrack_control,  tssi->thermal[RF_PATH_A], tssi->thermal[RF_PATH_B]);\n\n\tif (dm->support_ic_type == ODM_RTL8822C) {\n\t\tfor (i = 0; i < c.rf_path_count; i++)\n\t\t\tthermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0x7e);\t/* 0x42: RF Reg[6:1] Thermal Trim*/\n\t} else {\n\t\tfor (i = 0; i < c.rf_path_count; i++) {\n\t\t\tthermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0xfc00);\t/* 0x42: RF Reg[15:10]*/\n\t\t\tthermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);\n\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + power_time_thermal(%d)\\n\", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));\n\n\t\t\tif (thermal_value_temp[i] > 63)\n\t\t\t\tthermal_value[i] = 63;\n\t\t\telse if (thermal_value_temp[i] < 0)\n\t\t\t\tthermal_value[i] = 0;\n\t\t\telse\n\t\t\t\tthermal_value[i] = thermal_value_temp[i];\n\t\t}\n\t}\n\n\tif ((tssi->thermal[RF_PATH_A] == 0xff || tssi->thermal[RF_PATH_B] == 0xff)) {\n\t\tfor (i = 0; i < c.rf_path_count; i++)\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"no pg, tssi->thermal[%d] = 0x%x\\n\",\n\t\t\t\ti, tssi->thermal[i]);\n\t\treturn;\n\t}\n\n\tfor (j = 0; j < c.rf_path_count; j++) {\n\t\tcali_info->thermal_value_avg_path[j][cali_info->thermal_value_avg_index_path[j]] = thermal_value[j];\n\t\tcali_info->thermal_value_avg_index_path[j]++;\n\t\tif (cali_info->thermal_value_avg_index_path[j] == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/\n\t\t\tcali_info->thermal_value_avg_index_path[j] = 0;\n\n\n\t\tfor (i = 0; i < c.average_thermal_num; i++) {\n\t\t\tif (cali_info->thermal_value_avg_path[j][i]) {\n\t\t\t\tthermal_value_avg[j] += cali_info->thermal_value_avg_path[j][i];\n\t\t\t\tthermal_value_avg_count[j]++;\n\t\t\t}\n\t\t}\n\n\t\tif (thermal_value_avg_count[j]) {            /* Calculate Average thermal_value after average enough times */\n\t\t\tthermal_value[j] = (u8)(thermal_value_avg[j] / thermal_value_avg_count[j]);\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"AVG Thermal Meter = 0x%X, tssi->thermal[%d] = 0x%x\\n\",\n\t\t\t\tthermal_value[j], j, tssi->thermal[j]);\n\t\t}\n\t\t/* 4 5. Calculate delta, delta_LCK, delta_IQK. */\n\n\t\t/* \"delta\" here is used to determine whether thermal value changes or not. */\n\t\tdelta[j] = (thermal_value[j] > cali_info->thermal_value_path[j]) ? (thermal_value[j] - cali_info->thermal_value_path[j]) : (cali_info->thermal_value_path[j] - thermal_value[j]);\n\t\tdelta_LCK = (thermal_value[0] > cali_info->thermal_value_lck) ? (thermal_value[0] - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value[0]);\n\t\tdelta_IQK = (thermal_value[0] > cali_info->thermal_value_iqk) ? (thermal_value[0] - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value[0]);\n\t}\n\n\t/*4 6. If necessary, do LCK.*/\n\n\tfor (i = 0; i < c.rf_path_count; i++)\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"(delta[%d], delta_LCK, delta_IQK) = (%d, %d, %d)\\n\", i, delta[i], delta_LCK, delta_IQK);\n\n\t/* Wait sacn to do LCK by RF Jenyu*/\n\tif( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {\n\t\t/* Delta temperature is equal to or larger than 20 centigrade.*/\n\t\tif (delta_LCK >= c.threshold_iqk) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"delta_LCK(%d) >= threshold_iqk(%d)\\n\", delta_LCK, c.threshold_iqk);\n\t\t\tcali_info->thermal_value_lck = thermal_value[RF_PATH_A];\n\n\t\t\t/*Use RTLCK, so close power tracking driver LCK*/\n\t\t\tif ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {\n\t\t\t\tif (c.phy_lc_calibrate)\n\t\t\t\t\t(*c.phy_lc_calibrate)(dm);\n\t\t\t} else\n\t\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"Do not do LCK\\n\");\n\t\t}\n\t}\n\n\t/*3 7. If necessary, move the index of swing table to adjust Tx power.*/\n\tfor (i = 0; i < c.rf_path_count; i++) {\n\t\tif (i == RF_PATH_B) {\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_b, DELTA_SWINGIDX_SIZE);\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_b, DELTA_SWINGIDX_SIZE);\n\t\t} else if (i == RF_PATH_C) {\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_c, DELTA_SWINGIDX_SIZE);\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_c, DELTA_SWINGIDX_SIZE);\n\t\t} else if (i == RF_PATH_D) {\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_d, DELTA_SWINGIDX_SIZE);\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_d, DELTA_SWINGIDX_SIZE);\n\t\t} else {\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_a, DELTA_SWINGIDX_SIZE);\n\t\t\todm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_a, DELTA_SWINGIDX_SIZE);\n\t\t}\n\n\t\tcali_info->delta_power_index_last[i] = cali_info->delta_power_index[i];\t/*recording poer index offset*/\n\t\tdelta[i] = thermal_value[i] > tssi->thermal[i] ? (thermal_value[i] - tssi->thermal[i]) : (tssi->thermal[i] - thermal_value[i]);\n\t\t\t\t\n\t\tif (delta[i] >= TXPWR_TRACK_TABLE_SIZE)\n\t\t\tdelta[i] = TXPWR_TRACK_TABLE_SIZE - 1;\n\n\t\tif (thermal_value[i] > tssi->thermal[i]) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"delta_swing_table_idx_tup[%d]=%d Path=%d\\n\", delta[i], delta_swing_table_idx_tup[delta[i]], i);\n\t\t\t\t\n\t\t\tcali_info->delta_power_index[i] = delta_swing_table_idx_tup[delta[i]];\n\t\t\tcali_info->absolute_ofdm_swing_idx[i] =  delta_swing_table_idx_tup[delta[i]];\t    /*Record delta swing for mix mode power tracking*/\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"******Temp is higher and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\\n\", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);\n\t\t} else {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"delta_swing_table_idx_tdown[%d]=%d Path=%d\\n\", delta[i], delta_swing_table_idx_tdown[delta[i]], i);\n\t\t\tcali_info->delta_power_index[i] = -1 * delta_swing_table_idx_tdown[delta[i]];\n\t\t\tcali_info->absolute_ofdm_swing_idx[i] = -1 * delta_swing_table_idx_tdown[delta[i]];        /*Record delta swing for mix mode power tracking*/\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\t\"******Temp is lower and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\\n\", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);\n\t\t}\n\t}\n\n\tfor (p = RF_PATH_A; p < c.rf_path_count; p++) {\t\n\t\tif (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p])\t     /*If Thermal value changes but lookup table value still the same*/\n\t\t\tcali_info->power_index_offset[p] = 0;\n\t\telse\n\t\t\tcali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p];\t/*Power index diff between 2 times Power Tracking*/\n\t}\n\n#if 0\n\tif (dm->support_ic_type == ODM_RTL8822C) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking MIX_MODE**********\\n\");\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking BBSWING_MODE**********\\n\");\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);\n\t}\n#endif\n\tif (*dm->mp_mode == 1) {\n\t\tif (cali_info->txpowertrack_control == 1) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking MIX_MODE**********\\n\");\n\t\t\ttracking_method = MIX_MODE;\n\t\t} else if (cali_info->txpowertrack_control == 3) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking TSSI_MODE**********\\n\");\n\t\t\ttracking_method = TSSI_MODE;\n\t\t}\t\n\t} else {\n\t\tif (rf->power_track_type >= 0 && rf->power_track_type <= 3) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking MIX_MODE**********\\n\");\n\t\t\ttracking_method = MIX_MODE;\n\t\t} else if (rf->power_track_type >= 4 && rf->power_track_type <= 7) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"**********Enter POWER Tracking TSSI_MODE**********\\n\");\n\t\t\ttracking_method = TSSI_MODE;\n\t\t}\t\n\t}\n\n\tif (dm->support_ic_type == ODM_RTL8822C || dm->support_ic_type == ODM_RTL8814B)\n\t\tfor (p = RF_PATH_A; p < c.rf_path_count; p++)\n\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, tracking_method, p, 0);\n\n\t/* Wait sacn to do IQK by RF Jenyu*/\n\tif ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {\n\t\t/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/\n\t\tif (delta_IQK >= c.threshold_iqk) {\n\t\t\tcali_info->thermal_value_iqk = thermal_value[RF_PATH_A];\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"delta_IQK(%d) >= threshold_iqk(%d)\\n\", delta_IQK, c.threshold_iqk);\n\t\t\t/*if (!cali_info->is_iqk_in_progress)*/\n\t\t\t/*\t(*c.do_iqk)(dm, delta_IQK, thermal_value[RF_PATH_A], 8);*/\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"Do IQK\\n\");\n\n\t\t\t/*if (!cali_info->is_iqk_in_progress)*/\n\t\t\t/*\t(*c.do_tssi_dck)(dm, true);*/\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"Do TSSI DCK\\n\");\n\t\t}\n\t}\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"<===%s\\n\", __func__);\n\n\tcali_info->tx_powercount = 0;\n}\n#endif\n\n/* 3============================================================\n * 3 IQ Calibration\n * 3============================================================ */\n\nvoid\nodm_reset_iqk_result(\n\tstruct dm_struct\t*dm\n)\n{\n\treturn;\n}\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\nu8 odm_get_right_chnl_place_for_iqk(u8 chnl)\n{\n\tu8\tchannel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {\n\t\t1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165\n\t};\n\tu8\tplace = chnl;\n\n\n\tif (chnl > 14) {\n\t\tfor (place = 14; place < sizeof(channel_all); place++) {\n\t\t\tif (channel_all[place] == chnl)\n\t\t\t\treturn place - 13;\n\t\t}\n\t}\n\treturn 0;\n\n}\n#endif\n\nvoid\nodm_iq_calibrate(\n\tstruct dm_struct\t*dm\n)\n{\n\tvoid\t*adapter = dm->adapter;\n\tstruct dm_iqk_info\t*iqk_info = &dm->IQK_info;\n\t\n\tRF_DBG(dm, DBG_RF_IQK, \"=>%s\\n\",__FUNCTION__);\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tif (*dm->is_fcs_mode_enable)\n\t\treturn;\n#endif\n\n\tif ((dm->is_linked) && (!iqk_info->rfk_forbidden)) {\n\t\tRF_DBG(dm, DBG_RF_IQK, \"interval=%d ch=%d prech=%d scan=%s\\n\", dm->linked_interval,\n\t\t       *dm->channel,  dm->pre_channel, *dm->is_scan_in_process == TRUE ? \"TRUE\":\"FALSE\");\n\n\t\tif (*dm->channel != dm->pre_channel) {\n\t\t\tdm->pre_channel = *dm->channel;\n\t\t\tdm->linked_interval = 0;\n\t\t}\n\n\t\tif ((dm->linked_interval < 3) && (!*dm->is_scan_in_process))\n\t\t\tdm->linked_interval++;\n\n\t\tif (dm->linked_interval == 2)\n\t\t\tPHY_IQCalibrate(adapter, false);\n\t} else\n\t\tdm->linked_interval = 0;\n\n\t\tRF_DBG(dm, DBG_RF_IQK, \"<=%s interval=%d ch=%d prech=%d scan=%s\\n\", __FUNCTION__, dm->linked_interval,\n\t\t\t*dm->channel,  dm->pre_channel, *dm->is_scan_in_process == TRUE?\"TRUE\":\"FALSE\");\n}\n\nvoid phydm_rf_init(struct dm_struct\t\t*dm)\n{\n\n\todm_txpowertracking_init(dm);\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\todm_clear_txpowertracking_state(dm);\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n#if (RTL8814A_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8814A)\n\t\tphy_iq_calibrate_8814a_init(dm);\n#endif\n#endif\n\n}\n\nvoid phydm_rf_watchdog(struct dm_struct *dm)\n{\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n#if (MP_DRIVER == 1)\n\t/*struct _ADAPTER *adapter = dm->adapter;*/\n\t/*PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx);*/\n#endif\n\tFunctionIn(COMP_MLME);\n\n\tif (*dm->mp_mode == 1) {\n#if (MP_DRIVER == 1)\n\t\t/*if (p_mpt_ctx->bTxPowerTrackOn)*/\n\t\t\todm_txpowertracking_check(dm);\n#endif\n\t} else {\n\t\todm_txpowertracking_check(dm);\n\n\t\tif (dm->support_ic_type & (ODM_IC_11AC_SERIES |  ODM_IC_JGR3_SERIES))\n\t\t\todm_iq_calibrate(dm);\n\t}\n#endif\n}\n"
  },
  {
    "path": "hal/phydm/halrf/halphyrf_win.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef __HALPHYRF_H__\n#define __HALPHYRF_H__\n\n#if (RTL8814A_SUPPORT == 1)\n\t#include \"halrf/rtl8814a/halrf_iqk_8814a.h\"\n#endif\n\n#if (RTL8822B_SUPPORT == 1)\n\t#include \"halrf/rtl8822b/halrf_iqk_8822b.h\"\n\t#include \"../mac/Halmac_type.h\"\n#endif\n#include \"halrf/halrf_powertracking_win.h\"\n#include \"halrf/halrf_kfree.h\"\n#include \"halrf/halrf_txgapcal.h\"\n#if (RTL8821C_SUPPORT == 1)\n\t#include \"halrf/rtl8821c/halrf_iqk_8821c.h\"\n#endif\n\n#if (RTL8195B_SUPPORT == 1)\n//\t#include \"halrf/rtl8195b/halrf.h\"\n\t#include \"halrf/rtl8195b/halrf_iqk_8195b.h\"\n\t#include \"halrf/rtl8195b/halrf_txgapk_8195b.h\"\n\t#include \"halrf/rtl8195b/halrf_dpk_8195b.h\"\n#endif\n\n#if (RTL8814B_SUPPORT == 1)\n\t#include \"halrf/rtl8814b/halrf_iqk_8814b.h\"\n#endif\n\nenum spur_cal_method {\n\tPLL_RESET,\n\tAFE_PHASE_SEL\n};\n\nenum pwrtrack_method {\n\tBBSWING,\n\tTXAGC,\n\tMIX_MODE,\n\tTSSI_MODE,\n\tMIX_2G_TSSI_5G_MODE,\n\tMIX_5G_TSSI_2G_MODE,\n\tCLEAN_MODE\n};\n\ntypedef void(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);\ntypedef void(*func_iqk)(void *, u8, u8, u8);\ntypedef void(*func_lck)(void *);\ntypedef void(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);\ntypedef void(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);\ntypedef void (*func_swing_xtal)(void *, s8 **, s8 **);\ntypedef void (*func_set_xtal)(void *);\ntypedef void(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);\n\nstruct txpwrtrack_cfg {\n\tu8\t\tswing_table_size_cck;\n\tu8\t\tswing_table_size_ofdm;\n\tu8\t\tthreshold_iqk;\n\tu8\t\tthreshold_dpk;\n\tu8\t\taverage_thermal_num;\n\tu8\t\trf_path_count;\n\tu32\t\tthermal_reg_addr;\n\tfunc_set_pwr\todm_tx_pwr_track_set_pwr;\n\tfunc_iqk\tdo_iqk;\n\tfunc_lck\t\tphy_lc_calibrate;\n\tfunc_swing\tget_delta_swing_table;\n\tfunc_swing8814only\tget_delta_swing_table8814only;\n\tfunc_swing_xtal\t\t\tget_delta_swing_xtal_table;\n\tfunc_set_xtal\t\t\todm_txxtaltrack_set_xtal;\n\tfunc_all_swing\tget_delta_all_swing_table;\n};\n\nvoid\nconfigure_txpower_track(\n\tstruct dm_struct\t\t*dm,\n\tstruct txpwrtrack_cfg\t*config\n);\n\n\nvoid\nodm_clear_txpowertracking_state(\n\tstruct dm_struct\t\t*dm\n);\n\nvoid\nodm_txpowertracking_callback_thermal_meter(\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\tstruct dm_struct\t\t*dm\n#else\n\tvoid\t*adapter\n#endif\n);\n\n#if (RTL8822C_SUPPORT == 1)\nvoid\nodm_txpowertracking_new_callback_thermal_meter(void *dm_void);\n#endif\n\n#define ODM_TARGET_CHNL_NUM_2G_5G\t59\n\n\nvoid\nodm_reset_iqk_result(\n\tstruct dm_struct\t*dm\n);\nu8\nodm_get_right_chnl_place_for_iqk(\n\tu8 chnl\n);\n\nvoid odm_iq_calibrate(struct dm_struct\t*dm);\nvoid phydm_rf_init(struct dm_struct\t\t*dm);\nvoid phydm_rf_watchdog(struct dm_struct\t\t*dm);\n\n#endif\t/*#ifndef __HALPHYRF_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/halrf.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n * ************************************************************\n */\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\\\n\tRTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\\\n\tRTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\\\n\tRTL8812F_SUPPORT == 1)\n\nvoid _iqk_check_if_reload(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tiqk_info->is_reload = (boolean)odm_get_bb_reg(dm, R_0x1bf0, BIT(16));\n}\n\nvoid _iqk_page_switch(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type == ODM_RTL8821C)\n\t\todm_write_4byte(dm, 0x1b00, 0xf8000008);\n\telse\n\t\todm_write_4byte(dm, 0x1b00, 0xf800000a);\n}\n\nu32 halrf_psd_log2base(u32 val)\n{\n\tu8 j;\n\tu32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;\n\tu32 result, val_fractiond_b = 0;\n\tu32 table_fraction[21] = {\n\t\t0, 432, 332, 274, 232, 200, 174, 151, 132, 115,\n\t\t100, 86, 74, 62, 51, 42, 32, 23, 15, 7, 0};\n\n\tif (val == 0)\n\t\treturn 0;\n\n\ttmp = val;\n\n\twhile (1) {\n\t\tif (tmp == 1)\n\t\t\tbreak;\n\n\t\ttmp = (tmp >> 1);\n\t\tshiftcount++;\n\t}\n\n\tval_integerd_b = shiftcount + 1;\n\n\ttmp2 = 1;\n\tfor (j = 1; j <= val_integerd_b; j++)\n\t\ttmp2 = tmp2 * 2;\n\n\ttmp = (val * 100) / tmp2;\n\ttindex = tmp / 5;\n\n\tif (tindex > 20)\n\t\ttindex = 20;\n\n\tval_fractiond_b = table_fraction[tindex];\n\n\tresult = val_integerd_b * 100 - val_fractiond_b;\n\n\treturn result;\n}\n\nvoid phydm_get_iqk_cfir(void *dm_void, u8 idx, u8 path, boolean debug)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tu8 i, ch;\n\tu32 tmp;\n\tu32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);\n\n\tif (debug)\n\t\tch = 2;\n\telse\n\t\tch = 0;\n\n\todm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0xf8000008 | path << 1);\n\tif (idx == 0)\n\t\todm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x3);\n\telse\n\t\todm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x1);\n\todm_set_bb_reg(dm, R_0x1bd4, bit_mask_20_16, 0x10);\n\tfor (i = 0; i < 8; i++) {\n\t\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001 + (i * 4));\n\t\ttmp = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);\n\t\tiqk_info->iqk_cfir_real[ch][path][idx][i] =\n\t\t\t\t\t\t(u16)((tmp & 0x0fff0000) >> 16);\n\t\tiqk_info->iqk_cfir_imag[ch][path][idx][i] = (u16)(tmp & 0xfff);\n\t}\n\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);\n\todm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x0);\n}\n\nvoid halrf_iqk_xym_enable(struct dm_struct *dm, u8 xym_enable)\n{\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tif (xym_enable == 0)\n\t\tiqk_info->xym_read = false;\n\telse\n\t\tiqk_info->xym_read = true;\n\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]%-20s %s\\n\", \"xym_read = \",\n\t       (iqk_info->xym_read ? \"true\" : \"false\"));\n}\n\n/*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/\nvoid halrf_iqk_xym_read(void *dm_void, u8 path, u8 xym_type)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tu8 i, start, num;\n\tu32 tmp1, tmp2;\n\n\tif (!iqk_info->xym_read)\n\t\treturn;\n\n\tif (*dm->band_width == 0) {\n\t\tstart = 3;\n\t\tnum = 4;\n\t} else if (*dm->band_width == 1) {\n\t\tstart = 2;\n\t\tnum = 6;\n\t} else {\n\t\tstart = 0;\n\t\tnum = 10;\n\t}\n\n\todm_write_4byte(dm, 0x1b00, 0xf8000008);\n\ttmp1 = odm_read_4byte(dm, 0x1b1c);\n\todm_write_4byte(dm, 0x1b1c, 0xa2193c32);\n\n\todm_write_4byte(dm, 0x1b00, 0xf800000a);\n\ttmp2 = odm_read_4byte(dm, 0x1b1c);\n\todm_write_4byte(dm, 0x1b1c, 0xa2193c32);\n\n\tfor (path = 0; path < 2; path++) {\n\t\todm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);\n\t\tswitch (xym_type) {\n\t\tcase 0:\n\t\t\tfor (i = 0; i < num; i++) {\n\t\t\t\todm_write_4byte(dm, 0x1b14, 0xe6 + start + i);\n\t\t\t\todm_write_4byte(dm, 0x1b14, 0x0);\n\t\t\t\tiqk_info->rx_xym[path][i] =\n\t\t\t\t\t\todm_read_4byte(dm, 0x1b38);\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tfor (i = 0; i < num; i++) {\n\t\t\t\todm_write_4byte(dm, 0x1b14, 0xe6 + start + i);\n\t\t\t\todm_write_4byte(dm, 0x1b14, 0x0);\n\t\t\t\tiqk_info->tx_xym[path][i] =\n\t\t\t\t\t\todm_read_4byte(dm, 0x1b38);\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tfor (i = 0; i < 6; i++) {\n\t\t\t\todm_write_4byte(dm, 0x1b14, 0xe0 + i);\n\t\t\t\todm_write_4byte(dm, 0x1b14, 0x0);\n\t\t\t\tiqk_info->gs1_xym[path][i] =\n\t\t\t\t\t\todm_read_4byte(dm, 0x1b38);\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\tfor (i = 0; i < 6; i++) {\n\t\t\t\todm_write_4byte(dm, 0x1b14, 0xe0 + i);\n\t\t\t\todm_write_4byte(dm, 0x1b14, 0x0);\n\t\t\t\tiqk_info->gs2_xym[path][i] =\n\t\t\t\t\t\todm_read_4byte(dm, 0x1b38);\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\tfor (i = 0; i < 6; i++) {\n\t\t\t\todm_write_4byte(dm, 0x1b14, 0xe0 + i);\n\t\t\t\todm_write_4byte(dm, 0x1b14, 0x0);\n\t\t\t\tiqk_info->rxk1_xym[path][i] =\n\t\t\t\t\t\todm_read_4byte(dm, 0x1b38);\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t\todm_write_4byte(dm, 0x1b38, 0x20000000);\n\t\todm_write_4byte(dm, 0x1b00, 0xf8000008);\n\t\todm_write_4byte(dm, 0x1b1c, tmp1);\n\t\todm_write_4byte(dm, 0x1b00, 0xf800000a);\n\t\todm_write_4byte(dm, 0x1b1c, tmp2);\n\t\t_iqk_page_switch(dm);\n\t}\n}\n\n/*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/\nvoid halrf_iqk_xym_show(struct dm_struct *dm, u8 xym_type)\n{\n\tu8 num, path, path_num, i;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tif (dm->rf_type == RF_1T1R)\n\t\tpath_num = 0x1;\n\telse if (dm->rf_type == RF_2T2R)\n\t\tpath_num = 0x2;\n\telse\n\t\tpath_num = 0x4;\n\n\tif (*dm->band_width == CHANNEL_WIDTH_20)\n\t\tnum = 4;\n\telse if (*dm->band_width == CHANNEL_WIDTH_40)\n\t\tnum = 6;\n\telse\n\t\tnum = 10;\n\n\tfor (path = 0; path < path_num; path++) {\n\t\tswitch (xym_type) {\n\t\tcase 0:\n\t\t\tfor (i = 0; i < num; i++)\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\t       \"[IQK]%-20s %-2d: 0x%x\\n\",\n\t\t\t\t       (path == 0) ? \"PATH A RX-XYM \" :\n\t\t\t\t       \"PATH B RX-XYM\", i,\n\t\t\t\t       iqk_info->rx_xym[path][i]);\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tfor (i = 0; i < num; i++)\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\t       \"[IQK]%-20s %-2d: 0x%x\\n\",\n\t\t\t\t       (path == 0) ? \"PATH A TX-XYM \" :\n\t\t\t\t       \"PATH B TX-XYM\", i,\n\t\t\t\t       iqk_info->tx_xym[path][i]);\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\t       \"[IQK]%-20s %-2d: 0x%x\\n\",\n\t\t\t\t       (path == 0) ? \"PATH A GS1-XYM \" :\n\t\t\t\t       \"PATH B GS1-XYM\", i,\n\t\t\t\t       iqk_info->gs1_xym[path][i]);\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\t       \"[IQK]%-20s %-2d: 0x%x\\n\",\n\t\t\t\t       (path == 0) ? \"PATH A GS2-XYM \" :\n\t\t\t\t       \"PATH B GS2-XYM\", i,\n\t\t\t\t       iqk_info->gs2_xym[path][i]);\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\t       \"[IQK]%-20s %-2d: 0x%x\\n\",\n\t\t\t\t       (path == 0) ? \"PATH A RXK1-XYM \" :\n\t\t\t\t       \"PATH B RXK1-XYM\", i,\n\t\t\t\t       iqk_info->rxk1_xym[path][i]);\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\nvoid halrf_iqk_xym_dump(void *dm_void)\n{\n\tu32 tmp1, tmp2;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\todm_write_4byte(dm, 0x1b00, 0xf8000008);\n\ttmp1 = odm_read_4byte(dm, 0x1b1c);\n\todm_write_4byte(dm, 0x1b00, 0xf800000a);\n\ttmp2 = odm_read_4byte(dm, 0x1b1c);\n#if 0\n\t/*halrf_iqk_xym_read(dm, xym_type);*/\n#endif\n\todm_write_4byte(dm, 0x1b00, 0xf8000008);\n\todm_write_4byte(dm, 0x1b1c, tmp1);\n\todm_write_4byte(dm, 0x1b00, 0xf800000a);\n\todm_write_4byte(dm, 0x1b1c, tmp2);\n\t_iqk_page_switch(dm);\n}\n\nvoid halrf_iqk_info_dump(void *dm_void, u32 *_used, char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu8 rf_path, j, reload_iqk = 0;\n\tu32 tmp;\n\t/*two channel, PATH, TX/RX, 0:pass 1 :fail*/\n\tboolean iqk_result[2][NUM][2];\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tif (!(dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)))\n\t\treturn;\n\n\t/* IQK INFO */\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"%-20s\\n\",\n\t\t \"% IQK Info %\");\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"%-20s\\n\",\n\t\t (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? \"FW-IQK\" :\n\t\t \"Driver-IQK\");\n\n\treload_iqk = (u8)odm_get_bb_reg(dm, R_0x1bf0, BIT(16));\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"%-20s: %s\\n\",\n\t\t \"reload\", (reload_iqk) ? \"True\" : \"False\");\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"%-20s: %s\\n\",\n\t\t \"rfk_forbidden\", (iqk_info->rfk_forbidden) ? \"True\" : \"False\");\n#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \\\n\tRTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\\\n\tRTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"%-20s: %s\\n\",\n\t\t \"segment_iqk\", (iqk_info->segment_iqk) ? \"True\" : \"False\");\n#endif\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"%-20s:%d %d\\n\",\n\t\t \"iqk count / fail count\", dm->n_iqk_cnt, dm->n_iqk_fail_cnt);\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"%-20s: %d\\n\",\n\t\t \"channel\", *dm->channel);\n\n\tif (*dm->band_width == CHANNEL_WIDTH_20)\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"%-20s: %s\\n\", \"bandwidth\", \"BW_20\");\n\telse if (*dm->band_width == CHANNEL_WIDTH_40)\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"%-20s: %s\\n\", \"bandwidth\", \"BW_40\");\n\telse if (*dm->band_width == CHANNEL_WIDTH_80)\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"%-20s: %s\\n\", \"bandwidth\", \"BW_80\");\n\telse if (*dm->band_width == CHANNEL_WIDTH_160)\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"%-20s: %s\\n\", \"bandwidth\", \"BW_160\");\n\telse\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"%-20s: %s\\n\", \"bandwidth\", \"BW_UNKNOWN\");\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"%-20s: %llu %s\\n\", \"progressing_time\",\n\t\t dm->rf_calibrate_info.iqk_total_progressing_time, \"(ms)\");\n\n\ttmp = odm_read_4byte(dm, 0x1bf0);\n\tfor (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)\n\t\tfor (j = 0; j < 2; j++)\n\t\t\tiqk_result[0][rf_path][j] = (boolean)\n\t\t\t(tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))));\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"%-20s: 0x%08x\\n\", \"Reg0x1bf0\", tmp);\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"%-20s: %s\\n\",\n\t\t \"PATH_A-Tx result\",\n\t\t (iqk_result[0][RF_PATH_A][0]) ? \"Fail\" : \"Pass\");\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"%-20s: %s\\n\",\n\t\t \"PATH_A-Rx result\",\n\t\t (iqk_result[0][RF_PATH_A][1]) ? \"Fail\" : \"Pass\");\n#if (RTL8822B_SUPPORT == 1)\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"%-20s: %s\\n\",\n\t\t \"PATH_B-Tx result\",\n\t\t (iqk_result[0][RF_PATH_B][0]) ? \"Fail\" : \"Pass\");\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"%-20s: %s\\n\",\n\t\t \"PATH_B-Rx result\",\n\t\t (iqk_result[0][RF_PATH_B][1]) ? \"Fail\" : \"Pass\");\n#endif\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid halrf_get_fw_version(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\trf->fw_ver = (dm->fw_version << 16) | dm->fw_sub_version;\n}\n\nvoid halrf_iqk_dbg(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 rf_path, j;\n\tu32 tmp;\n\t/*two channel, PATH, TX/RX, 0:pass 1 :fail*/\n\tboolean iqk_result[2][NUM][2];\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\t/* IQK INFO */\n\tRF_DBG(dm, DBG_RF_IQK, \"%-20s\\n\", \"====== IQK Info ======\");\n\n\tRF_DBG(dm, DBG_RF_IQK, \"%-20s\\n\",\n\t       (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? \"FW-IQK\" :\n\t       \"Driver-IQK\");\n\n\tif (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) {\n\t\thalrf_get_fw_version(dm);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: 0x%x\\n\", \"FW_VER\", rf->fw_ver);\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %s\\n\", \"IQK_VER\", HALRF_IQK_VER);\n\t}\n\n\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %s\\n\", \"reload\",\n\t       (iqk_info->is_reload) ? \"True\" : \"False\");\n\n\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %d %d\\n\", \"iqk count / fail count\",\n\t       dm->n_iqk_cnt, dm->n_iqk_fail_cnt);\n\n\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %d\\n\", \"channel\", *dm->channel);\n\n\tif (*dm->band_width == CHANNEL_WIDTH_20)\n\t\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %s\\n\", \"bandwidth\", \"BW_20\");\n\telse if (*dm->band_width == CHANNEL_WIDTH_40)\n\t\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %s\\n\", \"bandwidth\", \"BW_40\");\n\telse if (*dm->band_width == CHANNEL_WIDTH_80)\n\t\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %s\\n\", \"bandwidth\", \"BW_80\");\n\telse if (*dm->band_width == CHANNEL_WIDTH_160)\n\t\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %s\\n\", \"bandwidth\", \"BW_160\");\n\telse\n\t\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %s\\n\", \"bandwidth\",\n\t\t       \"BW_UNKNOWN\");\n#if 0\n/*\n *\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %llu %s\\n\",\n *\t       \"progressing_time\",\n *\t       dm->rf_calibrate_info.iqk_total_progressing_time, \"(ms)\");\n */\n#endif\n\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %s\\n\", \"rfk_forbidden\",\n\t       (iqk_info->rfk_forbidden) ? \"True\" : \"False\");\n#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \\\n\tRTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\\\n\tRTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)\n\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %s\\n\", \"segment_iqk\",\n\t       (iqk_info->segment_iqk) ? \"True\" : \"False\");\n#endif\n\n\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %llu %s\\n\", \"progressing_time\",\n\t       dm->rf_calibrate_info.iqk_progressing_time, \"(ms)\");\n\n\ttmp = odm_read_4byte(dm, 0x1bf0);\n\tfor (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)\n\t\tfor (j = 0; j < 2; j++)\n\t\t\tiqk_result[0][rf_path][j] = (boolean)\n\t\t\t(tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))));\n\n\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: 0x%08x\\n\", \"Reg0x1bf0\", tmp);\n\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: 0x%08x\\n\", \"Reg0x1be8\",\n\t       odm_read_4byte(dm, 0x1be8));\n\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %s\\n\", \"PATH_A-Tx result\",\n\t       (iqk_result[0][RF_PATH_A][0]) ? \"Fail\" : \"Pass\");\n\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %s\\n\", \"PATH_A-Rx result\",\n\t       (iqk_result[0][RF_PATH_A][1]) ? \"Fail\" : \"Pass\");\n#if (RTL8822B_SUPPORT == 1)\n\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %s\\n\", \"PATH_B-Tx result\",\n\t       (iqk_result[0][RF_PATH_B][0]) ? \"Fail\" : \"Pass\");\n\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %s\\n\", \"PATH_B-Rx result\",\n\t       (iqk_result[0][RF_PATH_B][1]) ? \"Fail\" : \"Pass\");\n#endif\n}\n\nvoid halrf_lck_dbg(struct dm_struct *dm)\n{\n\tRF_DBG(dm, DBG_RF_IQK, \"%-20s\\n\", \"====== LCK Info ======\");\n#if 0\n\t/*RF_DBG(dm, DBG_RF_IQK, \"%-20s\\n\",\n\t *\t (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? \"LCK\" : \"RTK\"));\n\t */\n#endif\n\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: %llu %s\\n\", \"progressing_time\",\n\t       dm->rf_calibrate_info.lck_progressing_time, \"(ms)\");\n}\n\nvoid halrf_iqk_dbg_cfir_backup(struct dm_struct *dm)\n{\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tu8 path, idx, i;\n\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]%-20s\\n\", \"backup TX/RX CFIR\");\n\n\tfor (path = 0; path < 2; path++)\n\t\tfor (idx = 0; idx < 2; idx++)\n\t\t\tphydm_get_iqk_cfir(dm, idx, path, true);\n\n\tfor (path = 0; path < 2; path++) {\n\t\tfor (idx = 0; idx < 2; idx++) {\n\t\t\tfor (i = 0; i < 8; i++) {\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\t       \"[IQK]%-7s %-3s CFIR_real: %-2d: 0x%x\\n\",\n\t\t\t\t       (path == 0) ? \"PATH A\" : \"PATH B\",\n\t\t\t\t       (idx == 0) ? \"TX\" : \"RX\", i,\n\t\t\t\t       iqk_info->iqk_cfir_real[2][path][idx][i])\n\t\t\t\t       ;\n\t\t\t}\n\t\t\tfor (i = 0; i < 8; i++) {\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\t       \"[IQK]%-7s %-3s CFIR_img:%-2d: 0x%x\\n\",\n\t\t\t\t       (path == 0) ? \"PATH A\" : \"PATH B\",\n\t\t\t\t       (idx == 0) ? \"TX\" : \"RX\", i,\n\t\t\t\t       iqk_info->iqk_cfir_imag[2][path][idx][i])\n\t\t\t\t       ;\n\t\t\t}\n\t\t}\n\t}\n}\n\nvoid halrf_iqk_dbg_cfir_backup_update(struct dm_struct *dm)\n{\n\tstruct dm_iqk_info *iqk = &dm->IQK_info;\n\tu8 i, path, idx;\n\tu32 bmask13_12 = BIT(13) | BIT(12);\n\tu32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);\n\tu32 data;\n\n\tif (iqk->iqk_cfir_real[2][0][0][0] == 0) {\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]%-20s\\n\", \"CFIR is invalid\");\n\t\treturn;\n\t}\n\tfor (path = 0; path < 2; path++) {\n\t\tfor (idx = 0; idx < 2; idx++) {\n\t\t\todm_set_bb_reg(dm, R_0x1b00, MASKDWORD,\n\t\t\t\t       0xf8000008 | path << 1);\n\t\t\todm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7);\n\t\t\todm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x20000000);\n\t\t\todm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x20000000);\n\t\t\todm_set_bb_reg(dm, R_0x1bcc, MASKDWORD, 0x00000000);\n\t\t\tif (idx == 0)\n\t\t\t\todm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x3);\n\t\t\telse\n\t\t\t\todm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x1);\n\t\t\todm_set_bb_reg(dm, R_0x1bd4, bmask20_16, 0x10);\n\t\t\tfor (i = 0; i < 8; i++) {\n\t\t\t\tdata = ((0xc0000000 >> idx) + 0x3) + (i * 4) +\n\t\t\t\t\t(iqk->iqk_cfir_real[2][path][idx][i]\n\t\t\t\t\t<< 9);\n\t\t\t\todm_write_4byte(dm, 0x1bd8, data);\n\t\t\t\tdata = ((0xc0000000 >> idx) + 0x1) + (i * 4) +\n\t\t\t\t\t(iqk->iqk_cfir_imag[2][path][idx][i]\n\t\t\t\t\t<< 9);\n\t\t\t\todm_write_4byte(dm, 0x1bd8, data);\n#if 0\n\t\t\t\t/*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_real[2][path][idx][i]);*/\n\t\t\t\t/*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_imag[2][path][idx][i]);*/\n#endif\n\t\t\t}\n\t\t}\n\t\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x0);\n\t}\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]%-20s\\n\", \"update new CFIR\");\n}\n\nvoid halrf_iqk_dbg_cfir_reload(struct dm_struct *dm)\n{\n\tstruct dm_iqk_info *iqk = &dm->IQK_info;\n\tu8 i, path, idx;\n\tu32 bmask13_12 = BIT(13) | BIT(12);\n\tu32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);\n\tu32 data;\n\n\tif (iqk->iqk_cfir_real[0][0][0][0] == 0) {\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]%-20s\\n\", \"CFIR is invalid\");\n\t\treturn;\n\t}\n\tfor (path = 0; path < 2; path++) {\n\t\tfor (idx = 0; idx < 2; idx++) {\n\t\t\todm_set_bb_reg(dm, R_0x1b00, MASKDWORD,\n\t\t\t\t       0xf8000008 | path << 1);\n\t\t\todm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7);\n\t\t\todm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x20000000);\n\t\t\todm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x20000000);\n\t\t\todm_set_bb_reg(dm, R_0x1bcc, MASKDWORD, 0x00000000);\n\t\t\tif (idx == 0)\n\t\t\t\todm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x3);\n\t\t\telse\n\t\t\t\todm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x1);\n\t\t\todm_set_bb_reg(dm, R_0x1bd4, bmask20_16, 0x10);\n\t\t\tfor (i = 0; i < 8; i++) {\n#if 0\n\t\t\t\t/*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_real[0][path][idx][i]);*/\n\t\t\t\t/*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_imag[0][path][idx][i]);*/\n#endif\n\t\t\t\tdata = ((0xc0000000 >> idx) + 0x3) + (i * 4) +\n\t\t\t\t\t(iqk->iqk_cfir_real[0][path][idx][i]\n\t\t\t\t\t<< 9);\n\t\t\t\todm_write_4byte(dm, 0x1bd8, data);\n\t\t\t\tdata = ((0xc0000000 >> idx) + 0x1) + (i * 4) +\n\t\t\t\t\t(iqk->iqk_cfir_imag[0][path][idx][i]\n\t\t\t\t\t<< 9);\n\t\t\t\todm_write_4byte(dm, 0x1bd8, data);\n\t\t\t}\n\t\t}\n\t\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x0);\n\t}\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]%-20s\\n\", \"write CFIR with default value\");\n}\n\nvoid halrf_iqk_dbg_cfir_write(struct dm_struct *dm, u8 type, u32 path, u32 idx,\n\t\t\t      u32 i, u32 data)\n{\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tif (type == 0)\n\t\tiqk_info->iqk_cfir_real[2][path][idx][i] = (u16)data;\n\telse\n\t\tiqk_info->iqk_cfir_imag[2][path][idx][i] = (u16)data;\n}\n\nvoid halrf_iqk_dbg_cfir_backup_show(struct dm_struct *dm)\n{\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tu8 path, idx, i;\n\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]%-20s\\n\", \"backup TX/RX CFIR\");\n\n\tfor (path = 0; path < 2; path++) {\n\t\tfor (idx = 0; idx < 2; idx++) {\n\t\t\tfor (i = 0; i < 8; i++) {\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\t       \"[IQK]%-10s %-3s CFIR_real:%-2d: 0x%x\\n\",\n\t\t\t\t       (path == 0) ? \"PATH A\" : \"PATH B\",\n\t\t\t\t       (idx == 0) ? \"TX\" : \"RX\", i,\n\t\t\t\t       iqk_info->iqk_cfir_real[2][path][idx][i])\n\t\t\t\t       ;\n\t\t\t}\n\t\t\tfor (i = 0; i < 8; i++) {\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\t       \"[IQK]%-10s %-3s CFIR_img:%-2d: 0x%x\\n\",\n\t\t\t\t       (path == 0) ? \"PATH A\" : \"PATH B\",\n\t\t\t\t       (idx == 0) ? \"TX\" : \"RX\", i,\n\t\t\t\t       iqk_info->iqk_cfir_imag[2][path][idx][i])\n\t\t\t\t       ;\n\t\t\t}\n\t\t}\n\t}\n}\n\nvoid halrf_do_imr_test(void *dm_void, u8 flag_imr_test)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (flag_imr_test != 0x0)\n\t\tswitch (dm->support_ic_type) {\n#if (RTL8822B_SUPPORT == 1)\n\t\tcase ODM_RTL8822B:\n\t\t\tdo_imr_test_8822b(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8821C_SUPPORT == 1)\n\t\tcase ODM_RTL8821C:\n\t\t\tdo_imr_test_8821c(dm);\n\t\t\tbreak;\n#endif\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n}\n\nvoid halrf_iqk_debug(void *dm_void, u32 *const dm_value, u32 *_used,\n\t\t     char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if 0\n\t/*dm_value[0]=0x0: backup from SRAM & show*/\n\t/*dm_value[0]=0x1: write backup CFIR to SRAM*/\n\t/*dm_value[0]=0x2: reload default CFIR to SRAM*/\n\t/*dm_value[0]=0x3: show backup*/\n\t/*dm_value[0]=0x10: write backup CFIR real part*/\n\t/*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/\n\t/*dm_value[0]=0x11: write backup CFIR imag*/\n\t/*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/\n\t/*dm_value[0]=0x20 :xym_read enable*/\n\t/*--> dm_value[1]:0:disable, 1:enable*/\n\t/*if dm_value[0]=0x20 = enable, */\n\t/*0x1:show rx_sym; 0x2: tx_xym; 0x3:gs1_xym; 0x4:gs2_sym; 0x5:rxk1_xym*/\n#endif\n\tif (dm_value[0] == 0x0)\n\t\thalrf_iqk_dbg_cfir_backup(dm);\n\telse if (dm_value[0] == 0x1)\n\t\thalrf_iqk_dbg_cfir_backup_update(dm);\n\telse if (dm_value[0] == 0x2)\n\t\thalrf_iqk_dbg_cfir_reload(dm);\n\telse if (dm_value[0] == 0x3)\n\t\thalrf_iqk_dbg_cfir_backup_show(dm);\n\telse if (dm_value[0] == 0x10)\n\t\thalrf_iqk_dbg_cfir_write(dm, 0, dm_value[1], dm_value[2],\n\t\t\t\t\t dm_value[3], dm_value[4]);\n\telse if (dm_value[0] == 0x11)\n\t\thalrf_iqk_dbg_cfir_write(dm, 1, dm_value[1], dm_value[2],\n\t\t\t\t\t dm_value[3], dm_value[4]);\n\telse if (dm_value[0] == 0x20)\n\t\thalrf_iqk_xym_enable(dm, (u8)dm_value[1]);\n\telse if (dm_value[0] == 0x21)\n\t\thalrf_iqk_xym_show(dm, (u8)dm_value[1]);\n\telse if (dm_value[0] == 0x30)\n\t\thalrf_do_imr_test(dm, (u8)dm_value[1]);\n}\n\nvoid halrf_iqk_hwtx_check(void *dm_void, boolean is_check)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tu32 tmp_b04;\n\n\tif (is_check) {\n\t\tiqk_info->is_hwtx = (boolean)odm_get_bb_reg(dm, R_0xb00, BIT(8));\n\t} else {\n\t\tif (iqk_info->is_hwtx) {\n\t\t\ttmp_b04 = odm_read_4byte(dm, 0xb04);\n\t\t\todm_set_bb_reg(dm, R_0xb04, BIT(3) | BIT(2), 0x0);\n\t\t\todm_write_4byte(dm, 0xb04, tmp_b04);\n\t\t}\n\t}\n#endif\n}\n\n\n#endif\n\nu8 halrf_match_iqk_version(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tu32 iqk_version = 0;\n\tchar temp[10] = {0};\n\n\todm_move_memory(dm, temp, HALRF_IQK_VER, sizeof(temp));\n\tPHYDM_SSCANF(temp + 2, DCMD_HEX, &iqk_version);\n\n\tif (dm->support_ic_type == ODM_RTL8822B) {\n\t\tif (iqk_version >= 0x24 && (odm_get_hw_img_version(dm) >= 72))\n\t\t\treturn 1;\n\t\telse if ((iqk_version <= 0x23) &&\n\t\t\t (odm_get_hw_img_version(dm) <= 71))\n\t\t\treturn 1;\n\t\telse\n\t\t\treturn 0;\n\t}\n\n\tif (dm->support_ic_type == ODM_RTL8821C) {\n\t\tif (iqk_version >= 0x18 && (odm_get_hw_img_version(dm) >= 37))\n\t\t\treturn 1;\n\t\telse\n\t\t\treturn 0;\n\t}\n\n\treturn 1;\n}\n\nvoid halrf_rf_lna_setting(void *dm_void, enum halrf_lna_set type)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tswitch (dm->support_ic_type) {\n#if (RTL8188E_SUPPORT == 1)\n\tcase ODM_RTL8188E:\n\t\thalrf_rf_lna_setting_8188e(dm, type);\n\t\tbreak;\n#endif\n#if (RTL8192E_SUPPORT == 1)\n\tcase ODM_RTL8192E:\n\t\thalrf_rf_lna_setting_8192e(dm, type);\n\t\tbreak;\n#endif\n#if (RTL8192F_SUPPORT == 1)\n\tcase ODM_RTL8192F:\n\t\thalrf_rf_lna_setting_8192f(dm, type);\n\t\tbreak;\n#endif\n\n#if (RTL8723B_SUPPORT == 1)\n\tcase ODM_RTL8723B:\n\t\thalrf_rf_lna_setting_8723b(dm, type);\n\t\tbreak;\n#endif\n#if (RTL8812A_SUPPORT == 1)\n\tcase ODM_RTL8812:\n\t\thalrf_rf_lna_setting_8812a(dm, type);\n\t\tbreak;\n#endif\n#if ((RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1))\n\tcase ODM_RTL8881A:\n\tcase ODM_RTL8821:\n\t\thalrf_rf_lna_setting_8821a(dm, type);\n\t\tbreak;\n#endif\n#if (RTL8822B_SUPPORT == 1)\n\tcase ODM_RTL8822B:\n\t\thalrf_rf_lna_setting_8822b(dm_void, type);\n\t\tbreak;\n#endif\n#if (RTL8822C_SUPPORT == 1)\n\tcase ODM_RTL8822C:\n\t\thalrf_rf_lna_setting_8822c(dm_void, type);\n\t\tbreak;\n#endif\n#if (RTL8812F_SUPPORT == 1)\n\tcase ODM_RTL8812F:\n\t\thalrf_rf_lna_setting_8812f(dm_void, type);\n\t\tbreak;\n#endif\n#if (RTL8821C_SUPPORT == 1)\n\tcase ODM_RTL8821C:\n\t\thalrf_rf_lna_setting_8821c(dm_void, type);\n\t\tbreak;\n#endif\n#if (RTL8814B_SUPPORT == 1)\n\t\tcase ODM_RTL8814B:\n\t\t\tbreak;\n#endif\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid halrf_support_ability_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t\t\t char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tu32 dm_value[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu8 i;\n\n\tfor (i = 0; i < 5; i++)\n\t\tif (input[i + 1])\n\t\t\tPHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]);\n\n\tif (dm_value[0] == 100) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\n[RF Supportability]\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"00. (( %s ))Power Tracking\\n\",\n\t\t\t ((rf->rf_supportability & HAL_RF_TX_PWR_TRACK) ?\n\t\t\t (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"01. (( %s ))IQK\\n\",\n\t\t\t ((rf->rf_supportability & HAL_RF_IQK) ? (\"V\") :\n\t\t\t (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"02. (( %s ))LCK\\n\",\n\t\t\t ((rf->rf_supportability & HAL_RF_LCK) ? (\"V\") :\n\t\t\t (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"03. (( %s ))DPK\\n\",\n\t\t\t ((rf->rf_supportability & HAL_RF_DPK) ? (\"V\") :\n\t\t\t (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"04. (( %s ))HAL_RF_TXGAPK\\n\",\n\t\t\t ((rf->rf_supportability & HAL_RF_TXGAPK) ? (\"V\") :\n\t\t\t (\".\")));\n\t} else {\n\t\tif (dm_value[1] == 1) /* enable */\n\t\t\trf->rf_supportability |= BIT(dm_value[0]);\n\t\telse if (dm_value[1] == 2) /* disable */\n\t\t\trf->rf_supportability &= ~(BIT(dm_value[0]));\n\t\telse\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[Warning!!!]  1:enable,  2:disable\\n\");\n\t}\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\nCurr-RF_supportability =  0x%x\\n\\n\", rf->rf_supportability);\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid halrf_cmn_info_init(void *dm_void, enum halrf_cmninfo_init cmn_info,\n\t\t\t u32 value)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tswitch (cmn_info) {\n\tcase HALRF_CMNINFO_EEPROM_THERMAL_VALUE:\n\t\trf->eeprom_thermal = (u8)value;\n\t\tbreak;\n\tcase HALRF_CMNINFO_PWT_TYPE:\n\t\trf->pwt_type = (u8)value;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid halrf_cmn_info_hook(void *dm_void, enum halrf_cmninfo_hook cmn_info,\n\t\t\t void *value)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tswitch (cmn_info) {\n\tcase HALRF_CMNINFO_CON_TX:\n\t\trf->is_con_tx = (boolean *)value;\n\t\tbreak;\n\tcase HALRF_CMNINFO_SINGLE_TONE:\n\t\trf->is_single_tone = (boolean *)value;\n\t\tbreak;\n\tcase HALRF_CMNINFO_CARRIER_SUPPRESSION:\n\t\trf->is_carrier_suppresion = (boolean *)value;\n\t\tbreak;\n\tcase HALRF_CMNINFO_MP_RATE_INDEX:\n\t\trf->mp_rate_index = (u8 *)value;\n\t\tbreak;\n\tcase HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY:\n\t\trf->manual_rf_supportability = (u32 *)value;\n\t\tbreak;\n\tdefault:\n\t\t/*do nothing*/\n\t\tbreak;\n\t}\n}\n\nvoid halrf_cmn_info_set(void *dm_void, u32 cmn_info, u64 value)\n{\n\t/* This init variable may be changed in run time. */\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tswitch (cmn_info) {\n\tcase HALRF_CMNINFO_ABILITY:\n\t\trf->rf_supportability = (u32)value;\n\t\tbreak;\n\n\tcase HALRF_CMNINFO_DPK_EN:\n\t\trf->dpk_en = (u8)value;\n\t\tbreak;\n\tcase HALRF_CMNINFO_RFK_FORBIDDEN:\n\t\tdm->IQK_info.rfk_forbidden = (boolean)value;\n\t\tbreak;\n#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \\\n\tRTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\\\n\tRTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)\n\tcase HALRF_CMNINFO_IQK_SEGMENT:\n\t\tdm->IQK_info.segment_iqk = (boolean)value;\n\t\tbreak;\n#endif\n\tcase HALRF_CMNINFO_RATE_INDEX:\n\t\trf->p_rate_index = (u32)value;\n\t\tbreak;\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tcase HALRF_CMNINFO_MP_PSD_POINT:\n\t\trf->halrf_psd_data.point = (u32)value;\n\t\tbreak;\n\tcase HALRF_CMNINFO_MP_PSD_START_POINT:\n\t\trf->halrf_psd_data.start_point = (u32)value;\n\t\tbreak;\n\tcase HALRF_CMNINFO_MP_PSD_STOP_POINT:\n\t\trf->halrf_psd_data.stop_point = (u32)value;\n\t\tbreak;\n\tcase HALRF_CMNINFO_MP_PSD_AVERAGE:\n\t\trf->halrf_psd_data.average = (u32)value;\n\t\tbreak;\n#endif\n\tdefault:\n\t\t/* do nothing */\n\t\tbreak;\n\t}\n}\n\nu64 halrf_cmn_info_get(void *dm_void, u32 cmn_info)\n{\n\t/* This init variable may be changed in run time. */\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tu64 return_value = 0;\n\n\tswitch (cmn_info) {\n\tcase HALRF_CMNINFO_ABILITY:\n\t\treturn_value = (u32)rf->rf_supportability;\n\t\tbreak;\n\tcase HALRF_CMNINFO_RFK_FORBIDDEN:\n\t\treturn_value = dm->IQK_info.rfk_forbidden;\n\t\tbreak;\n#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \\\n\tRTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\\\n\tRTL8814B_SUPPORT == 1  || RTL8822C_SUPPORT == 1)\n\tcase HALRF_CMNINFO_IQK_SEGMENT:\n\t\treturn_value = dm->IQK_info.segment_iqk;\n\t\tbreak;\n\tcase HALRF_CMNINFO_IQK_TIMES:\n\t\treturn_value = dm->IQK_info.iqk_times;\n\t\tbreak;\n#endif\n\tdefault:\n\t\t/* do nothing */\n\t\tbreak;\n\t}\n\n\treturn return_value;\n}\n\nvoid halrf_supportability_init_mp(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tswitch (dm->support_ic_type) {\n\tcase ODM_RTL8814B:\n#if (RTL8814B_SUPPORT == 1)\n\t\trf->rf_supportability =\n\t\t\t/*HAL_RF_TX_PWR_TRACK |*/\n\t\t\tHAL_RF_IQK |\n\t\t\tHAL_RF_LCK |\n\t\t\tHAL_RF_DPK |\n\t\t\tHAL_RF_DACK |\n\t\t\tHAL_RF_DPK_TRACK |\n\t\t\t0;\n#endif\n\t\tbreak;\n#if (RTL8822B_SUPPORT == 1)\n\tcase ODM_RTL8822B:\n\t\trf->rf_supportability =\n\t\t\t/*HAL_RF_TX_PWR_TRACK |*/\n\t\t\tHAL_RF_IQK |\n\t\t\tHAL_RF_LCK |\n\t\t\t/*@HAL_RF_DPK |*/\n\t\t\t0;\n\t\tbreak;\n#endif\n#if (RTL8822C_SUPPORT == 1)\n\tcase ODM_RTL8822C:\n\t\trf->rf_supportability =\n\t\t\t/*HAL_RF_TX_PWR_TRACK |*/\n\t\t\tHAL_RF_IQK |\n\t\t\tHAL_RF_LCK |\n\t\t\tHAL_RF_DPK |\n\t\t\tHAL_RF_DACK |\n\t\t\tHAL_RF_DPK_TRACK |\n\t\t\t0;\n\t\tbreak;\n#endif\n#if (RTL8821C_SUPPORT == 1)\n\tcase ODM_RTL8821C:\n\t\trf->rf_supportability =\n\t\t\t/*HAL_RF_TX_PWR_TRACK |*/\n\t\t\tHAL_RF_IQK |\n\t\t\tHAL_RF_LCK |\n\t\t\t/*@HAL_RF_DPK |*/\n\t\t\t/*@HAL_RF_TXGAPK |*/\n\t\t\t0;\n\t\tbreak;\n#endif\n#if (RTL8195B_SUPPORT == 1)\n\tcase ODM_RTL8195B:\n\t\trf->rf_supportability =\n\t\t\tHAL_RF_TX_PWR_TRACK |\n\t\t\tHAL_RF_IQK |\n\t\t\tHAL_RF_LCK |\n\t\t\tHAL_RF_DPK |\n\t\t\tHAL_RF_TXGAPK |\n\t\t\tHAL_RF_DPK_TRACK |\n\t\t\t0;\n\t\tbreak;\n#endif\n#if (RTL8812F_SUPPORT == 1)\n\t\tcase ODM_RTL8812F:\n\t\t\trf->rf_supportability =\n\t\t\t\t/*HAL_RF_TX_PWR_TRACK |*/\n\t\t\t\tHAL_RF_IQK |\n\t\t\t\tHAL_RF_LCK |\n\t\t\t\tHAL_RF_DPK |\n\t\t\t\tHAL_RF_DACK |\n\t\t\t\tHAL_RF_DPK_TRACK |\n\t\t\t\t0;\n\t\t\tbreak;\n#endif\n\n#if (RTL8198F_SUPPORT == 1)\n\t\tcase ODM_RTL8198F:\n\t\t\trf->rf_supportability =\n\t\t\t\t/*HAL_RF_TX_PWR_TRACK |*/\n\t\t\t\tHAL_RF_IQK |\n\t\t\t\tHAL_RF_LCK |\n\t\t\t\tHAL_RF_DPK |\n\t\t\t\t/*@HAL_RF_TXGAPK |*/\n\t\t\t\t0;\n\t\t\tbreak;\n#endif\n\n#if (RTL8192F_SUPPORT == 1)\n\t\tcase ODM_RTL8192F:\n\t\t\trf->rf_supportability =\n\t\t\t\t/*HAL_RF_TX_PWR_TRACK |*/\n\t\t\t\tHAL_RF_IQK |\n\t\t\t\tHAL_RF_LCK |\n\t\t\t\tHAL_RF_DPK |\n\t\t\t\t/*@HAL_RF_TXGAPK |*/\n\t\t\t\t0;\n\t\t\tbreak;\n#endif\n\n#if (RTL8197F_SUPPORT == 1)\n\t\tcase ODM_RTL8197F:\n\t\t\trf->rf_supportability =\n\t\t\t\t/*HAL_RF_TX_PWR_TRACK |*/\n\t\t\t\tHAL_RF_IQK |\n\t\t\t\tHAL_RF_LCK |\n\t\t\t\tHAL_RF_DPK |\n\t\t\t\t/*@HAL_RF_TXGAPK |*/\n\t\t\t\t0;\n\t\t\tbreak;\n#endif\n\n\tdefault:\n\t\trf->rf_supportability =\n\t\t\t/*HAL_RF_TX_PWR_TRACK |*/\n\t\t\tHAL_RF_IQK |\n\t\t\tHAL_RF_LCK |\n\t\t\t/*@HAL_RF_DPK |*/\n\t\t\t/*@HAL_RF_TXGAPK |*/\n\t\t\t0;\n\t\tbreak;\n\t}\n\n\tRF_DBG(dm, DBG_RF_INIT,\n\t       \"IC = ((0x%x)), RF_Supportability Init MP = ((0x%x))\\n\",\n\t       dm->support_ic_type, rf->rf_supportability);\n}\n\nvoid halrf_supportability_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tswitch (dm->support_ic_type) {\n\tcase ODM_RTL8814B:\n#if (RTL8814B_SUPPORT == 1)\n\t\trf->rf_supportability =\n\t\t\tHAL_RF_TX_PWR_TRACK |\n\t\t\tHAL_RF_IQK |\n\t\t\tHAL_RF_LCK |\n\t\t\tHAL_RF_DPK |\n\t\t\tHAL_RF_DPK_TRACK |\n\t\t\t0;\n#endif\n\t\tbreak;\n#if (RTL8822B_SUPPORT == 1)\n\tcase ODM_RTL8822B:\n\t\trf->rf_supportability =\n\t\t\tHAL_RF_TX_PWR_TRACK |\n\t\t\tHAL_RF_IQK |\n\t\t\tHAL_RF_LCK |\n\t\t\t/*@HAL_RF_DPK |*/\n\t\t\t0;\n\t\tbreak;\n#endif\n#if (RTL8822C_SUPPORT == 1)\n\tcase ODM_RTL8822C:\n\t\trf->rf_supportability =\n\t\t\tHAL_RF_TX_PWR_TRACK |\n\t\t\tHAL_RF_IQK |\n\t\t\tHAL_RF_LCK |\n\t\t\tHAL_RF_DPK |\n\t\t\tHAL_RF_DACK |\n\t\t\tHAL_RF_DPK_TRACK |\n\t\t\t0;\n\t\tbreak;\n#endif\n#if (RTL8821C_SUPPORT == 1)\n\tcase ODM_RTL8821C:\n\t\trf->rf_supportability =\n\t\t\tHAL_RF_TX_PWR_TRACK |\n\t\t\tHAL_RF_IQK |\n\t\t\tHAL_RF_LCK |\n\t\t\t/*@HAL_RF_DPK |*/\n\t\t\t/*@HAL_RF_TXGAPK |*/\n\t\t\t0;\n\t\tbreak;\n#endif\n#if (RTL8195B_SUPPORT == 1)\n\tcase ODM_RTL8195B:\n\t\trf->rf_supportability =\n\t\t\tHAL_RF_TX_PWR_TRACK |\n\t\t\tHAL_RF_IQK |\n\t\t\tHAL_RF_LCK |\n\t\t\tHAL_RF_DPK |\n\t\t\tHAL_RF_TXGAPK |\n\t\t\tHAL_RF_DPK_TRACK |\n\t\t\t0;\n\t\tbreak;\n#endif\n#if (RTL8812F_SUPPORT == 1)\n\t\tcase ODM_RTL8812F:\n\t\t\trf->rf_supportability =\n\t\t\t\tHAL_RF_TX_PWR_TRACK |\n\t\t\t\tHAL_RF_IQK |\n\t\t\t\tHAL_RF_LCK |\n\t\t\t\tHAL_RF_DPK |\n\t\t\t\tHAL_RF_DACK |\n\t\t\t\tHAL_RF_DPK_TRACK |\n\t\t\t\t0;\n\t\t\tbreak;\n#endif\n\n#if (RTL8198F_SUPPORT == 1)\n\t\tcase ODM_RTL8198F:\n\t\t\trf->rf_supportability =\n\t\t\t\tHAL_RF_TX_PWR_TRACK |\n\t\t\t\tHAL_RF_IQK |\n\t\t\t\tHAL_RF_LCK |\n\t\t\t\tHAL_RF_DPK |\n\t\t\t\t/*@HAL_RF_TXGAPK |*/\n\t\t\t\t0;\n\t\t\tbreak;\n#endif\n\n#if (RTL8192F_SUPPORT == 1)\n\t\tcase ODM_RTL8192F:\n\t\t\trf->rf_supportability =\n\t\t\t\tHAL_RF_TX_PWR_TRACK |\n\t\t\t\tHAL_RF_IQK |\n\t\t\t\tHAL_RF_LCK |\n\t\t\t\tHAL_RF_DPK |\n\t\t\t\t/*@HAL_RF_TXGAPK |*/\n\t\t\t\t0;\n\t\t\tbreak;\n#endif\n\n#if (RTL8197F_SUPPORT == 1)\n\t\tcase ODM_RTL8197F:\n\t\t\trf->rf_supportability =\n\t\t\t\tHAL_RF_TX_PWR_TRACK |\n\t\t\t\tHAL_RF_IQK |\n\t\t\t\tHAL_RF_LCK |\n\t\t\t\tHAL_RF_DPK |\n\t\t\t\t/*@HAL_RF_TXGAPK |*/\n\t\t\t\t0;\n\t\t\tbreak;\n#endif\n\n\tdefault:\n\t\trf->rf_supportability =\n\t\t\tHAL_RF_TX_PWR_TRACK |\n\t\t\tHAL_RF_IQK |\n\t\t\tHAL_RF_LCK |\n\t\t\t/*@HAL_RF_DPK |*/\n\t\t\t0;\n\t\tbreak;\n\t}\n\n\tRF_DBG(dm, DBG_RF_INIT,\n\t       \"IC = ((0x%x)), RF_Supportability Init = ((0x%x))\\n\",\n\t       dm->support_ic_type, rf->rf_supportability);\n}\n\nvoid halrf_watchdog(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n#if 0\n\t/*RF_DBG(dm, DBG_RF_TMP, \"%s\\n\", __func__);*/\n#endif\n\n\tif (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress)\n\t\treturn;\n\n\tphydm_rf_watchdog(dm);\n\thalrf_dpk_track(dm);\n}\n\n#if 0\nvoid\nhalrf_iqk_init(\n\tvoid\t\t\t*dm_void\n)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tswitch (dm->support_ic_type) {\n#if (RTL8814B_SUPPORT == 1)\n\tcase ODM_RTL8814B:\n\t\tbreak;\n#endif\n#if (RTL8822B_SUPPORT == 1)\n\tcase ODM_RTL8822B:\n\t\t_iq_calibrate_8822b_init(dm);\n\t\tbreak;\n#endif\n#if (RTL8822C_SUPPORT == 1)\n\tcase ODM_RTL8822C:\n\t\t_iq_calibrate_8822c_init(dm);\n\t\tbreak;\n#endif\n#if (RTL8821C_SUPPORT == 1)\n\tcase ODM_RTL8821C:\n\t\tbreak;\n#endif\n\n\tdefault:\n\t\tbreak;\n\t}\n}\n#endif\n\nvoid halrf_rfk_handshake(void *dm_void, boolean is_before_k)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (*dm->mp_mode)\n\t\treturn;\n\n\tswitch (dm->support_ic_type) {\n#if (RTL8822C_SUPPORT == 1)\n\t\tcase ODM_RTL8822C:\n\t\t\thalrf_rfk_handshake_8822c(dm, is_before_k);\n\t\t\tbreak;\n#endif\n\t\tdefault:\n\t\t\tbreak;\n\t}\n}\n\nvoid halrf_rf_k_connect_trigger(void *dm_void, boolean is_recovery,\n\t\t\t\tenum halrf_k_segment_time seg_time)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\t\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tif (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&\n\t    rf->is_carrier_suppresion) {\n\t\tif (*dm->mp_mode &&\n\t\t    (*rf->is_con_tx || *rf->is_single_tone ||\n\t\t    *rf->is_carrier_suppresion))\n\t\t\treturn;\n\t}\n\t/*[TX GAP K]*/\n\n\t/*[LOK, IQK]*/\n\thalrf_segment_iqk_trigger(dm, true, seg_time);\n\n\t/*[TSSI Trk]*/\n\t/*halrf_do_tssi(dm);*/\n\t/*halrf_do_tssi(dm);*/\n\t/*halrf_tssi_set_de(dm);*/\n\n\t/*[DPK]*/\n\tif(dpk_info->is_dpk_by_channel == true)\n\t\thalrf_dpk_trigger(dm);\n\telse\n\t\thalrf_dpk_reload(dm);\n}\n\nvoid halrf_dack_trigger(void *dm_void, boolean force)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tu64 start_time;\n\n\tif (!(rf->rf_supportability & HAL_RF_DACK))\n\t\treturn;\n\n\tstart_time = odm_get_current_time(dm);\n\n\tswitch (dm->support_ic_type) {\n#if (RTL8822C_SUPPORT == 1)\n\tcase ODM_RTL8822C:\n\t\thalrf_dac_cal_8822c(dm, force);\n\t\tbreak;\n#endif\n#if (RTL8812F_SUPPORT == 1)\n\tcase ODM_RTL8812F:\n\t\thalrf_dac_cal_8812f(dm);\n\t\tbreak;\n#endif\n#if (RTL8814B_SUPPORT == 1)\n\tcase ODM_RTL8814B:\n\t\thalrf_dac_cal_8814b(dm);\n\t\tbreak;\n#endif\n\tdefault:\n\t\tbreak;\n\t}\n\trf->dpk_progressing_time = odm_get_progressing_time(dm, start_time);\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]DACK progressing_time = %lld ms\\n\",\n\t       rf->dpk_progressing_time);\n}\n\n\nvoid halrf_dack_dbg(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tu64 start_time;\n\n\tif (!(rf->rf_supportability & HAL_RF_DACK))\n\t\treturn;\n\n\tswitch (dm->support_ic_type) {\n#if (RTL8822C_SUPPORT == 1)\n\tcase ODM_RTL8822C:\n\t\thalrf_dack_dbg_8822c(dm);\n\t\tbreak;\n#endif\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n\nvoid halrf_segment_iqk_trigger(void *dm_void, boolean clear,\n\t\t\t       boolean segment_iqk)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tu64 start_time;\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\n\tif (odm_check_power_status(dm) == false)\n\t\treturn;\n#endif\n\n\tif (dm->mp_mode &&\n\t    rf->is_con_tx &&\n\t    rf->is_single_tone &&\n\t    rf->is_carrier_suppresion)\n\t\tif (*dm->mp_mode &&\n\t\t    ((*rf->is_con_tx ||\n\t\t     *rf->is_single_tone ||\n\t\t     *rf->is_carrier_suppresion)))\n\t\t\treturn;\n\n\tif (!(rf->rf_supportability & HAL_RF_IQK))\n\t\treturn;\n\n#if DISABLE_BB_RF\n\treturn;\n#endif\n\tif (iqk_info->rfk_forbidden)\n\t\treturn;\n\n\thalrf_rfk_handshake(dm, true);\n\n\tif (!dm->rf_calibrate_info.is_iqk_in_progress) {\n\t\todm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);\n\t\tdm->rf_calibrate_info.is_iqk_in_progress = true;\n\t\todm_release_spin_lock(dm, RT_IQK_SPINLOCK);\n\t\tstart_time = odm_get_current_time(dm);\n\t\tdm->IQK_info.segment_iqk = segment_iqk;\n\n\t\tswitch (dm->support_ic_type) {\n#if (RTL8822B_SUPPORT == 1)\n\t\tcase ODM_RTL8822B:\n\t\t\tphy_iq_calibrate_8822b(dm, clear, segment_iqk);\n\t\t\tbreak;\n#endif\n#if (RTL8822C_SUPPORT == 1)\n\t\tcase ODM_RTL8822C:\n\t\t\tphy_iq_calibrate_8822c(dm, clear, segment_iqk);\n\t\t\tbreak;\n#endif\n#if (RTL8821C_SUPPORT == 1)\n\t\tcase ODM_RTL8821C:\n\t\t\tphy_iq_calibrate_8821c(dm, clear, segment_iqk);\n\t\t\tbreak;\n#endif\n#if (RTL8814B_SUPPORT == 1)\n\t\tcase ODM_RTL8814B:\n\t\t\tphy_iq_calibrate_8814b(dm, clear, segment_iqk);\n\t\t\tbreak;\n#endif\n#if (RTL8195B_SUPPORT == 1)\n\t\tcase ODM_RTL8195B:\n\t\t\tphy_iq_calibrate_8195b(dm, clear, segment_iqk);\n\t\t\tbreak;\n#endif\n/*\n#if (RTL8710C_SUPPORT == 1)\n\t\tcase ODM_RTL8710C:\n\t\t\tphy_iq_calibrate_8710c(dm, clear, segment_iqk);\n\t\t\tbreak;\n#endif\n*/\n#if (RTL8198F_SUPPORT == 1)\n\t\tcase ODM_RTL8198F:\n\t\t\tphy_iq_calibrate_8198f(dm, clear, segment_iqk);\n\t\t\tbreak;\n#endif\n#if (RTL8812F_SUPPORT == 1)\n\t\tcase ODM_RTL8812F:\n\t\t\tphy_iq_calibrate_8812f(dm, clear, segment_iqk);\n\t\t\tbreak;\n#endif\n#if (RTL8197G_SUPPORT == 1)\n\t\tcase ODM_RTL8197G:\n\t\t\tphy_iq_calibrate_8197g(dm, clear, segment_iqk);\n\t\t\tbreak;\n#endif\n#if (RTL8188E_SUPPORT == 1)\n\t\tcase ODM_RTL8188E:\n\t\t\tphy_iq_calibrate_8188e(dm, false);\n\t\t\tbreak;\n#endif\n#if (RTL8188F_SUPPORT == 1)\n\t\tcase ODM_RTL8188F:\n\t\t\tphy_iq_calibrate_8188f(dm, false);\n\t\t\tbreak;\n#endif\n#if (RTL8192E_SUPPORT == 1)\n\t\tcase ODM_RTL8192E:\n\t\t\tphy_iq_calibrate_8192e(dm, false);\n\t\t\tbreak;\n#endif\n#if (RTL8197F_SUPPORT == 1)\n\t\tcase ODM_RTL8197F:\n\t\t\tphy_iq_calibrate_8197f(dm, false);\n\t\t\tbreak;\n#endif\n#if (RTL8192F_SUPPORT == 1)\n\t\tcase ODM_RTL8192F:\n\t\t\tphy_iq_calibrate_8192f(dm, false);\n\t\t\tbreak;\n#endif\n#if (RTL8703B_SUPPORT == 1)\n\t\tcase ODM_RTL8703B:\n\t\t\tphy_iq_calibrate_8703b(dm, false);\n\t\t\tbreak;\n#endif\n#if (RTL8710B_SUPPORT == 1)\n\t\tcase ODM_RTL8710B:\n\t\t\tphy_iq_calibrate_8710b(dm, false);\n\t\t\tbreak;\n#endif\n#if (RTL8723B_SUPPORT == 1)\n\t\tcase ODM_RTL8723B:\n\t\t\tphy_iq_calibrate_8723b(dm, false);\n\t\t\tbreak;\n#endif\n#if (RTL8723D_SUPPORT == 1)\n\t\tcase ODM_RTL8723D:\n\t\t\tphy_iq_calibrate_8723d(dm, false);\n\t\t\tbreak;\n#endif\n#if (RTL8721D_SUPPORT == 1)\n\t\tcase ODM_RTL8721D:\n\t\t\tphy_iq_calibrate_8721d(dm, false);\n\t\t\tbreak;\n#endif\n#if (RTL8812A_SUPPORT == 1)\n\t\tcase ODM_RTL8812:\n\t\t\tphy_iq_calibrate_8812a(dm, false);\n\t\t\tbreak;\n#endif\n#if (RTL8821A_SUPPORT == 1)\n\t\tcase ODM_RTL8821:\n\t\t\tphy_iq_calibrate_8821a(dm, false);\n\t\t\tbreak;\n#endif\n#if (RTL8814A_SUPPORT == 1)\n\t\tcase ODM_RTL8814A:\n\t\t\tphy_iq_calibrate_8814a(dm, false);\n\t\t\tbreak;\n#endif\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t\tdm->rf_calibrate_info.iqk_progressing_time =\n\t\t\t\todm_get_progressing_time(dm, start_time);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]IQK progressing_time = %lld ms\\n\",\n\t\t       dm->rf_calibrate_info.iqk_progressing_time);\n\n\t\todm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);\n\t\tdm->rf_calibrate_info.is_iqk_in_progress = false;\n\t\todm_release_spin_lock(dm, RT_IQK_SPINLOCK);\n\n\t\thalrf_rfk_handshake(dm, false);\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t       \"== Return the IQK CMD, because RFKs in Progress ==\\n\");\n\t}\n}\n\n\nvoid halrf_iqk_trigger(void *dm_void, boolean is_recovery)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tu64 start_time;\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\n\tif (odm_check_power_status(dm) == false)\n\t\treturn;\n#endif\n\n\tif (dm->mp_mode &&\n\t    rf->is_con_tx &&\n\t    rf->is_single_tone &&\n\t    rf->is_carrier_suppresion)\n\t\tif (*dm->mp_mode &&\n\t\t    ((*rf->is_con_tx ||\n\t\t     *rf->is_single_tone ||\n\t\t     *rf->is_carrier_suppresion)))\n\t\t\treturn;\n\n\tif (!(rf->rf_supportability & HAL_RF_IQK))\n\t\treturn;\n\n#if DISABLE_BB_RF\n\treturn;\n#endif\n\n\tif (iqk_info->rfk_forbidden)\n\t\treturn;\n\n\thalrf_rfk_handshake(dm, true);\n\n\tif (!dm->rf_calibrate_info.is_iqk_in_progress) {\n\t\todm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);\n\t\tdm->rf_calibrate_info.is_iqk_in_progress = true;\n\t\todm_release_spin_lock(dm, RT_IQK_SPINLOCK);\n\t\tstart_time = odm_get_current_time(dm);\n\t\tswitch (dm->support_ic_type) {\n#if (RTL8188E_SUPPORT == 1)\n\t\tcase ODM_RTL8188E:\n\t\t\tphy_iq_calibrate_8188e(dm, is_recovery);\n\t\t\tbreak;\n#endif\n#if (RTL8188F_SUPPORT == 1)\n\t\tcase ODM_RTL8188F:\n\t\t\tphy_iq_calibrate_8188f(dm, is_recovery);\n\t\t\tbreak;\n#endif\n#if (RTL8192E_SUPPORT == 1)\n\t\tcase ODM_RTL8192E:\n\t\t\tphy_iq_calibrate_8192e(dm, is_recovery);\n\t\t\tbreak;\n#endif\n#if (RTL8197F_SUPPORT == 1)\n\t\tcase ODM_RTL8197F:\n\t\t\tphy_iq_calibrate_8197f(dm, is_recovery);\n\t\t\tbreak;\n#endif\n#if (RTL8192F_SUPPORT == 1)\n\t\tcase ODM_RTL8192F:\n\t\t\tphy_iq_calibrate_8192f(dm, is_recovery);\n\t\t\tbreak;\n#endif\n#if (RTL8703B_SUPPORT == 1)\n\t\tcase ODM_RTL8703B:\n\t\t\tphy_iq_calibrate_8703b(dm, is_recovery);\n\t\t\tbreak;\n#endif\n#if (RTL8710B_SUPPORT == 1)\n\t\tcase ODM_RTL8710B:\n\t\t\tphy_iq_calibrate_8710b(dm, is_recovery);\n\t\t\tbreak;\n#endif\n#if (RTL8723B_SUPPORT == 1)\n\t\tcase ODM_RTL8723B:\n\t\t\tphy_iq_calibrate_8723b(dm, is_recovery);\n\t\t\tbreak;\n#endif\n#if (RTL8723D_SUPPORT == 1)\n\t\tcase ODM_RTL8723D:\n\t\t\tphy_iq_calibrate_8723d(dm, is_recovery);\n\t\t\tbreak;\n#endif\n#if (RTL8721D_SUPPORT == 1)\n\t\tcase ODM_RTL8721D:\n\t\t\tphy_iq_calibrate_8721d(dm, is_recovery);\n\t\t\tbreak;\n#endif\n#if (RTL8812A_SUPPORT == 1)\n\t\tcase ODM_RTL8812:\n\t\t\tphy_iq_calibrate_8812a(dm, is_recovery);\n\t\t\tbreak;\n#endif\n#if (RTL8821A_SUPPORT == 1)\n\t\tcase ODM_RTL8821:\n\t\t\tphy_iq_calibrate_8821a(dm, is_recovery);\n\t\t\tbreak;\n#endif\n#if (RTL8814A_SUPPORT == 1)\n\t\tcase ODM_RTL8814A:\n\t\t\tphy_iq_calibrate_8814a(dm, is_recovery);\n\t\t\tbreak;\n#endif\n#if (RTL8822B_SUPPORT == 1)\n\t\tcase ODM_RTL8822B:\n\t\t\tphy_iq_calibrate_8822b(dm, false, false);\n\t\t\tbreak;\n#endif\n#if (RTL8822C_SUPPORT == 1)\n\t\tcase ODM_RTL8822C:\n\t\t\tphy_iq_calibrate_8822c(dm, false, false);\n\t\t\tbreak;\n#endif\n#if (RTL8821C_SUPPORT == 1)\n\t\tcase ODM_RTL8821C:\n\t\t\tphy_iq_calibrate_8821c(dm, false, false);\n\t\t\tbreak;\n#endif\n#if (RTL8814B_SUPPORT == 1)\n\t\tcase ODM_RTL8814B:\n\t\t\tphy_iq_calibrate_8814b(dm, false, false);\n\t\t\t//_do_dpk_8814b(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8195B_SUPPORT == 1)\n\t\tcase ODM_RTL8195B:\n\t\t\tphy_iq_calibrate_8195b(dm, false, false);\n\t\t\tbreak;\n#endif\n#if (RTL8198F_SUPPORT == 1)\n\t\tcase ODM_RTL8198F:\n\t\t\tphy_iq_calibrate_8198f(dm, false, false);\n\t\t\tbreak;\n#endif\n#if (RTL8812F_SUPPORT == 1)\n\t\tcase ODM_RTL8812F:\n\t\t\tphy_iq_calibrate_8812f(dm, false, false);\n\t\t\tbreak;\n#endif\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\trf->iqk_progressing_time = odm_get_progressing_time(dm, start_time);\n\tRF_DBG(dm, DBG_RF_LCK, \"[IQK]Trigger IQK progressing_time = %lld ms\\n\",\n\t       rf->iqk_progressing_time);\n\t\todm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);\n\t\tdm->rf_calibrate_info.is_iqk_in_progress = false;\n\t\todm_release_spin_lock(dm, RT_IQK_SPINLOCK);\n\n\t\thalrf_rfk_handshake(dm, false);\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t       \"== Return the IQK CMD, because RFKs in Progress ==\\n\");\n\t}\n}\n\nvoid halrf_lck_trigger(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tu64 start_time;\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\n\tif (odm_check_power_status(dm) == false)\n\t\treturn;\n#endif\n\n\tif (dm->mp_mode &&\n\t    rf->is_con_tx &&\n\t    rf->is_single_tone &&\n\t    rf->is_carrier_suppresion)\n\t\tif (*dm->mp_mode &&\n\t\t    ((*rf->is_con_tx ||\n\t\t     *rf->is_single_tone ||\n\t\t     *rf->is_carrier_suppresion)))\n\t\t\treturn;\n\n\tif (!(rf->rf_supportability & HAL_RF_LCK))\n\t\treturn;\n\n#if DISABLE_BB_RF\n\treturn;\n#endif\n\tif (iqk_info->rfk_forbidden)\n\t\treturn;\n\twhile (*dm->is_scan_in_process) {\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[LCK]scan is in process, bypass LCK\\n\");\n\t\treturn;\n\t}\n\n\tif (!dm->rf_calibrate_info.is_lck_in_progress) {\n\t\todm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);\n\t\tdm->rf_calibrate_info.is_lck_in_progress = true;\n\t\todm_release_spin_lock(dm, RT_IQK_SPINLOCK);\n\t\tstart_time = odm_get_current_time(dm);\n\t\tswitch (dm->support_ic_type) {\n#if (RTL8188E_SUPPORT == 1)\n\t\tcase ODM_RTL8188E:\n\t\t\tphy_lc_calibrate_8188e(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8188F_SUPPORT == 1)\n\t\tcase ODM_RTL8188F:\n\t\t\tphy_lc_calibrate_8188f(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8192E_SUPPORT == 1)\n\t\tcase ODM_RTL8192E:\n\t\t\tphy_lc_calibrate_8192e(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8197F_SUPPORT == 1)\n\t\tcase ODM_RTL8197F:\n\t\t\tphy_lc_calibrate_8197f(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8192F_SUPPORT == 1)\n\t\tcase ODM_RTL8192F:\n\t\t\tphy_lc_calibrate_8192f(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8703B_SUPPORT == 1)\n\t\tcase ODM_RTL8703B:\n\t\t\tphy_lc_calibrate_8703b(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8710B_SUPPORT == 1)\n\t\tcase ODM_RTL8710B:\n\t\t\tphy_lc_calibrate_8710b(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8721D_SUPPORT == 1)\n\t\tcase ODM_RTL8721D:\n\t\t\tphy_lc_calibrate_8721d(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8723B_SUPPORT == 1)\n\t\tcase ODM_RTL8723B:\n\t\t\tphy_lc_calibrate_8723b(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8723D_SUPPORT == 1)\n\t\tcase ODM_RTL8723D:\n\t\t\tphy_lc_calibrate_8723d(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8812A_SUPPORT == 1)\n\t\tcase ODM_RTL8812:\n\t\t\tphy_lc_calibrate_8812a(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8821A_SUPPORT == 1)\n\t\tcase ODM_RTL8821:\n\t\t\tphy_lc_calibrate_8821a(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8814A_SUPPORT == 1)\n\t\tcase ODM_RTL8814A:\n\t\t\tphy_lc_calibrate_8814a(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8822B_SUPPORT == 1)\n\t\tcase ODM_RTL8822B:\n\t\t\tphy_lc_calibrate_8822b(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8822C_SUPPORT == 1)\n\t\tcase ODM_RTL8822C:\n\t\t\tphy_lc_calibrate_8822c(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8812F_SUPPORT == 1)\n\t\tcase ODM_RTL8812F:\n\t\t\tphy_lc_calibrate_8812f(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8821C_SUPPORT == 1)\n\t\tcase ODM_RTL8821C:\n\t\t\tphy_lc_calibrate_8821c(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8814B_SUPPORT == 1)\n\t\tcase ODM_RTL8814B:\n\t\t\tbreak;\n#endif\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t\tdm->rf_calibrate_info.lck_progressing_time =\n\t\t\t\todm_get_progressing_time(dm, start_time);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]LCK progressing_time = %lld ms\\n\",\n\t\t       dm->rf_calibrate_info.lck_progressing_time);\n#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)\n\t\thalrf_lck_dbg(dm);\n#endif\n\t\todm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);\n\t\tdm->rf_calibrate_info.is_lck_in_progress = false;\n\t\todm_release_spin_lock(dm, RT_IQK_SPINLOCK);\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t       \"= Return the LCK CMD, because RFK is in Progress =\\n\");\n\t}\n}\n\nvoid halrf_aac_check(struct dm_struct *dm)\n{\n\tswitch (dm->support_ic_type) {\n#if (RTL8821C_SUPPORT == 1)\n\tcase ODM_RTL8821C:\n#if 0\n\t\taac_check_8821c(dm);\n#endif\n\t\tbreak;\n#endif\n#if (RTL8822B_SUPPORT == 1)\n\tcase ODM_RTL8822B:\n#if 1\n\t\taac_check_8822b(dm);\n#endif\n\t\tbreak;\n#endif\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid halrf_x2k_check(struct dm_struct *dm)\n{\n\n\tswitch (dm->support_ic_type) {\n\tcase ODM_RTL8821C:\n#if (RTL8821C_SUPPORT == 1)\n#endif\n\t\tbreak;\n\tcase ODM_RTL8822C:\n#if (RTL8822C_SUPPORT == 1)\n\t\tphy_x2_check_8822c(dm);\n\t\tbreak;\n#endif\n\tcase ODM_RTL8812F:\n#if (RTL8812F_SUPPORT == 1)\n\t\tphy_x2_check_8812f(dm);\n\t\tbreak;\n#endif\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid halrf_set_rfsupportability(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tif (rf->manual_rf_supportability &&\n\t    *rf->manual_rf_supportability != 0xffffffff) {\n\t\trf->rf_supportability = *rf->manual_rf_supportability;\n\t} else if (*dm->mp_mode) {\n\t\thalrf_supportability_init_mp(dm);\n\t} else {\n\t\thalrf_supportability_init(dm);\n\t}\n}\n\nvoid halrf_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tRF_DBG(dm, DBG_RF_INIT, \"HALRF_Init\\n\");\n\trf->aac_checked = false;\n\thalrf_init_debug_setting(dm);\n\thalrf_set_rfsupportability(dm);\n#if 1\n\t/*Init all RF funciton*/\n\thalrf_aac_check(dm);\n\thalrf_dack_trigger(dm, false);\n\thalrf_x2k_check(dm);\n#endif\n\n\t/*power trim, thrmal trim, pa bias*/\n\tphydm_config_new_kfree(dm);\n\n\t/*TSSI Init*/\n\thalrf_tssi_get_efuse(dm);\n}\n\nvoid halrf_dpk_trigger(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tu64 start_time;\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\n\tif (odm_check_power_status(dm) == false)\n\t\treturn;\n#endif\n\n\tif (dm->mp_mode &&\n\t    rf->is_con_tx &&\n\t    rf->is_single_tone &&\n\t    rf->is_carrier_suppresion)\n\t\tif (*dm->mp_mode &&\n\t\t    ((*rf->is_con_tx ||\n\t\t     *rf->is_single_tone ||\n\t\t     *rf->is_carrier_suppresion)))\n\t\t\treturn;\n\n\tif (!(rf->rf_supportability & HAL_RF_DPK))\n\t\treturn;\n\n#if DISABLE_BB_RF\n\treturn;\n#endif\n\n\tif (iqk_info->rfk_forbidden)\n\t\treturn;\n\n\thalrf_rfk_handshake(dm, true);\n\n\tif (!rf->is_dpk_in_progress) {\n\t\todm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);\n\t\trf->is_dpk_in_progress = true;\n\t\todm_release_spin_lock(dm, RT_IQK_SPINLOCK);\n\t\tstart_time = odm_get_current_time(dm);\n\n\t\tswitch (dm->support_ic_type) {\n#if (RTL8822C_SUPPORT == 1)\n\t\tcase ODM_RTL8822C:\n\t\t\tdo_dpk_8822c(dm);\n\t\t\tbreak;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n#if (RTL8197F_SUPPORT == 1)\n\t\tcase ODM_RTL8197F:\n\t\t\tdo_dpk_8197f(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8192F_SUPPORT == 1)\n\t\tcase ODM_RTL8192F:\n\t\t\tdo_dpk_8192f(dm);\n\t\t\tbreak;\n#endif\n\n#if (RTL8198F_SUPPORT == 1)\n\t\tcase ODM_RTL8198F:\n\t\t\tdo_dpk_8198f(dm);\n\t\t\tbreak;\n#endif\n#if (RTL8812F_SUPPORT == 1)\n\t\tcase ODM_RTL8812F:\n\t\t\tdo_dpk_8812f(dm);\n\t\t\tbreak;\n#endif\n\n#endif\n\n#if (RTL8814B_SUPPORT == 1)\n\t\tcase ODM_RTL8814B:\n\t\t\tdo_dpk_8814b(dm);\n\t\t\tbreak;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))\n#if (RTL8195B_SUPPORT == 1)\n\t\tcase ODM_RTL8195B:\n\t\t\tdo_dpk_8195b(dm);\n\t\t\tbreak;\n#endif\n#endif\n\t\tdefault:\n\t\t\tbreak;\n\t}\n\trf->dpk_progressing_time = odm_get_progressing_time(dm, start_time);\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK]DPK progressing_time = %lld ms\\n\",\n\t       rf->dpk_progressing_time);\n\n\t\todm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);\n\t\trf->is_dpk_in_progress = false;\n\t\todm_release_spin_lock(dm, RT_IQK_SPINLOCK);\n\n\t\thalrf_rfk_handshake(dm, false);\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t       \"== Return the DPK CMD, because RFKs in Progress ==\\n\");\n\t}\n}\n\nvoid halrf_set_dpkbychannel(void *dm_void, boolean dpk_by_ch)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\t\n\tswitch (dm->support_ic_type) {\n#if (RTL8814B_SUPPORT == 1)\n\t\tcase ODM_RTL8814B:\n\t\t\tdpk_set_dpkbychannel_8814b(dm, dpk_by_ch);\n\t\tbreak;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))\n#if (RTL8195B_SUPPORT == 1)\n\t\tcase ODM_RTL8195B:\n\t\t\tdpk_set_dpkbychannel_8195b(dm,dpk_by_ch);\n\t\tbreak;\n#endif\n#endif\n\t\tdefault:\n\t\t\tif (dpk_by_ch)\n\t\t\t\tdpk_info->is_dpk_by_channel = 1;\n\t\t\telse\n\t\t\t\tdpk_info->is_dpk_by_channel = 0;\n\t\tbreak;\n\t}\n\n}\n\nvoid halrf_set_dpkenable(void *dm_void, boolean is_dpk_enable)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\t\n\tswitch (dm->support_ic_type) {\n#if (RTL8814B_SUPPORT == 1)\n\t\tcase ODM_RTL8814B:\n\t\t\tdpk_set_is_dpk_enable_8814b(dm, is_dpk_enable);\n\t\tbreak;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))\n#if (RTL8195B_SUPPORT == 1)\n\t\tcase ODM_RTL8195B:\n\t\t\tdpk_set_is_dpk_enable_8195b(dm, is_dpk_enable);\n\t\tbreak;\n#endif\n#endif\n\t\t\n\t\n\t\tdefault:\n\t\tbreak;\n\t}\n\n}\nboolean halrf_get_dpkbychannel(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tboolean is_dpk_by_channel = true;\n\t\n\tswitch (dm->support_ic_type) {\n#if (RTL8814B_SUPPORT == 1)\n\t\tcase ODM_RTL8814B:\n\t\t\tis_dpk_by_channel = dpk_get_dpkbychannel_8814b(dm);\n\t\tbreak;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))\n#if (RTL8195B_SUPPORT == 1)\n\t\tcase ODM_RTL8195B:\n\t\t\tis_dpk_by_channel = dpk_get_dpkbychannel_8195b(dm);\n\t\tbreak;\n#endif\n#endif\n\n\tdefault:\n\tbreak;\n\t}\n\treturn is_dpk_by_channel;\n\n}\n\n\nboolean halrf_get_dpkenable(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tboolean is_dpk_enable = true;\n\n\t\n\tswitch (dm->support_ic_type) {\n#if (RTL8814B_SUPPORT == 1)\n\t\tcase ODM_RTL8814B:\n\t\t\tis_dpk_enable = dpk_get_is_dpk_enable_8814b(dm);\n\t\tbreak;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))\n#if (RTL8195B_SUPPORT == 1)\n\t\tcase ODM_RTL8195B:\n\t\t\tis_dpk_enable = dpk_get_is_dpk_enable_8195b(dm);\n\t\tbreak;\n#endif\n#endif\n\t\tdefault:\n\t\tbreak;\n\t}\n\treturn is_dpk_enable;\n\n}\n\nu8 halrf_dpk_result_check(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu8 result = 0;\n\n\tswitch (dm->support_ic_type) {\n#if (RTL8822C_SUPPORT == 1)\n\tcase ODM_RTL8822C:\n\t\tif (dpk_info->dpk_path_ok == 0x3)\n\t\t\tresult = 1;\n\t\telse\n\t\t\tresult = 0;\n\t\tbreak;\n#endif\n\n#if (RTL8195B_SUPPORT == 1)\n\tcase ODM_RTL8195B:\n\t\tif (dpk_info->dpk_path_ok == 0x1)\n\t\t\tresult = 1;\n\t\telse\n\t\t\tresult = 0;\n\t\tbreak;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\n#if (RTL8197F_SUPPORT == 1)\n\tcase ODM_RTL8197F:\n\t\tif (dpk_info->dpk_path_ok == 0x3)\n\t\t\tresult = 1;\n\t\telse\n\t\t\tresult = 0;\n\t\tbreak;\n#endif\n\n#if (RTL8192F_SUPPORT == 1)\n\tcase ODM_RTL8192F:\n\t\tif (dpk_info->dpk_path_ok == 0x3)\n\t\t\tresult = 1;\n\t\telse\n\t\t\tresult = 0;\n\t\tbreak;\n#endif\n\n#if (RTL8198F_SUPPORT == 1)\n\tcase ODM_RTL8198F:\n\t\tif (dpk_info->dpk_path_ok == 0xf)\n\t\t\tresult = 1;\n\t\telse\n\t\t\tresult = 0;\n\t\tbreak;\n#endif\n\n#if (RTL8814B_SUPPORT == 1)\n\tcase ODM_RTL8814B:\n\t\tif (dpk_info->dpk_path_ok == 0xf)\n\t\t\tresult = 1;\n\t\telse\n\t\t\tresult = 0;\n\t\tbreak;\n#endif\n\n#if (RTL8812F_SUPPORT == 1)\n\tcase ODM_RTL8812F:\n\t\tif (dpk_info->dpk_path_ok == 0x3)\n\t\t\tresult = 1;\n\t\telse\n\t\t\tresult = 0;\n\t\tbreak;\n#endif\n\n#endif\n\tdefault:\n\t\tbreak;\n\t}\n\treturn result;\n}\n\nvoid halrf_dpk_sram_read(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tu8 path, group;\n\n\tswitch (dm->support_ic_type) {\n#if (RTL8822C_SUPPORT == 1)\n\tcase ODM_RTL8822C:\n\t\tdpk_coef_read_8822c(dm);\n\t\tbreak;\n#endif\n\n#if (RTL8195B_SUPPORT == 1)\n\tcase ODM_RTL8195B:\n\t\tdpk_sram_read_8195b(dm);\n\t\tbreak;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\n#if (RTL8197F_SUPPORT == 1)\n\tcase ODM_RTL8197F:\n\t\tdpk_sram_read_8197f(dm);\n\t\tbreak;\n#endif\n\n#if (RTL8192F_SUPPORT == 1)\n\tcase ODM_RTL8192F:\n\t\tdpk_sram_read_8192f(dm);\n\t\tbreak;\n#endif\n\n#if (RTL8198F_SUPPORT == 1)\n\tcase ODM_RTL8198F:\n\t\tdpk_sram_read_8198f(dm);\n\t\tbreak;\n#endif\n\n#if (RTL8814B_SUPPORT == 1)\n\tcase ODM_RTL8814B:\n\t\tdpk_sram_read_8814b(dm);\n\t\tbreak;\n#endif\n\n#if (RTL8812F_SUPPORT == 1)\n\tcase ODM_RTL8812F:\n\t\tdpk_coef_read_8812f(dm);\n\t\tbreak;\n#endif\n\n\n#endif\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid halrf_dpk_enable_disable(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tif (!(rf->rf_supportability & HAL_RF_DPK))\n\t\treturn;\n\n\tif (!rf->is_dpk_in_progress) {\n\t\todm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);\n\t\trf->is_dpk_in_progress = true;\n\t\todm_release_spin_lock(dm, RT_IQK_SPINLOCK);\n\n\tswitch (dm->support_ic_type) {\n#if (RTL8822C_SUPPORT == 1)\n\tcase ODM_RTL8822C:\n\t\tdpk_enable_disable_8822c(dm);\n\t\tbreak;\n#endif\n#if (RTL8195B_SUPPORT == 1)\n\tcase ODM_RTL8195B:\n\t\tdpk_enable_disable_8195b(dm);\n\t\tbreak;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\n#if (RTL8197F_SUPPORT == 1)\n\tcase ODM_RTL8197F:\n\t\tphy_dpk_enable_disable_8197f(dm);\n\t\tbreak;\n#endif\n#if (RTL8192F_SUPPORT == 1)\n\tcase ODM_RTL8192F:\n\t\tphy_dpk_enable_disable_8192f(dm);\n\t\tbreak;\n#endif\n\n#if (RTL8198F_SUPPORT == 1)\n\tcase ODM_RTL8198F:\n\t\tdpk_enable_disable_8198f(dm);\n\t\tbreak;\n#endif\n\n#if (RTL8814B_SUPPORT == 1)\n\tcase ODM_RTL8814B:\n\t\tdpk_enable_disable_8814b(dm);\n\t\tbreak;\n#endif\n\n#if (RTL8812F_SUPPORT == 1)\n\tcase ODM_RTL8812F:\n\t\tdpk_enable_disable_8812f(dm);\n\t\tbreak;\n#endif\n\n\n#endif\n\tdefault:\n\t\tbreak;\n\t}\n\n\t\todm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);\n\t\trf->is_dpk_in_progress = false;\n\t\todm_release_spin_lock(dm, RT_IQK_SPINLOCK);\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t       \"== Return the DPK CMD, because RFKs in Progress ==\\n\");\n\t}\n}\n\nvoid halrf_dpk_track(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tif (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||\n\t    dm->is_psd_in_process || (dpk_info->dpk_path_ok == 0) ||\n\t    !(rf->rf_supportability & HAL_RF_DPK_TRACK))\n\t\treturn;\n\n\tswitch (dm->support_ic_type) {\n#if (RTL8814B_SUPPORT == 1)\n\tcase ODM_RTL8814B:\n\t\tdpk_track_8814b(dm);\n\t\tbreak;\t\t\n#endif\n\n#if (RTL8822C_SUPPORT == 1)\n\tcase ODM_RTL8822C:\n\t\tdpk_track_8822c(dm);\n\t\tbreak;\t\t\n#endif\n\n#if (RTL8195B_SUPPORT == 1)\n\tcase ODM_RTL8195B:\n\t\tdpk_track_8195b(dm);\n\t\tbreak;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\n#if (RTL8197F_SUPPORT == 1)\n\tcase ODM_RTL8197F:\n\t\tphy_dpk_track_8197f(dm);\n\t\tbreak;\n#endif\n\n#if (RTL8192F_SUPPORT == 1)\n\tcase ODM_RTL8192F:\n\t\tphy_dpk_track_8192f(dm);\n\t\tbreak;\n#endif\n\n#if (RTL8198F_SUPPORT == 1)\n\tcase ODM_RTL8198F:\n\t\tdpk_track_8198f(dm);\n\t\tbreak;\t\t\n#endif\n\n#if (RTL8812F_SUPPORT == 1)\n\tcase ODM_RTL8812F:\n\t\tdpk_track_8812f(dm);\n\t\tbreak;\t\t\n#endif\n\n#endif\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid halrf_set_dpk_track(void *dm_void, u8 enable)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &(dm->rf_table);\n\n\tif (enable)\n\t\trf->rf_supportability = rf->rf_supportability | HAL_RF_DPK_TRACK;\n\telse\n\t\trf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK_TRACK;\n}\n\nvoid halrf_dpk_reload(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tswitch (dm->support_ic_type) {\n#if (RTL8195B_SUPPORT == 1)\n\tcase ODM_RTL8195B:\n\t\tif (dpk_info->dpk_path_ok > 0)\n\t\t\tdpk_reload_8195b(dm);\n\t\tbreak;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\n#if (RTL8197F_SUPPORT == 1)\n\tcase ODM_RTL8197F:\n\t\tif (dpk_info->dpk_path_ok > 0)\n\t\t\tdpk_reload_8197f(dm);\n\t\tbreak;\n#endif\n\n#if (RTL8192F_SUPPORT == 1)\n\tcase ODM_RTL8192F:\n\t\tif (dpk_info->dpk_path_ok > 0)\n\t\t\tdpk_reload_8192f(dm);\n\n\t\tbreak;\n#endif\n\n#if (RTL8198F_SUPPORT == 1)\n\tcase ODM_RTL8198F:\n\t\tif (dpk_info->dpk_path_ok > 0)\n\t\t\tdpk_reload_8198f(dm);\n\t\tbreak;\t\t\n#endif\n\n#if (RTL8814B_SUPPORT == 1)\n\tcase ODM_RTL8814B:\n\t\tif (dpk_info->dpk_path_ok > 0)\n\t\t\tdpk_reload_8814b(dm);\n\t\tbreak;\t\t\n#endif\n\n#endif\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid halrf_dpk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tif (!(rf->rf_supportability & HAL_RF_DPK) || rf->is_dpk_in_progress)\n\t\treturn;\n\n\tswitch (dm->support_ic_type) {\n#if (RTL8822C_SUPPORT == 1)\n\tcase ODM_RTL8822C:\n\t\tdpk_info_rsvd_page_8822c(dm, buf, buf_size);\n\t\tbreak;\n#endif\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid halrf_iqk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tif (!(rf->rf_supportability & HAL_RF_IQK))\n\t\treturn;\n\n\tif (dm->rf_calibrate_info.is_iqk_in_progress)\n\t\treturn;\n\n\tswitch (dm->support_ic_type) {\n#if (RTL8822C_SUPPORT == 1)\n\tcase ODM_RTL8822C:\n\t\tiqk_info_rsvd_page_8822c(dm, buf, buf_size);\n\t\tbreak;\n#endif\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nenum hal_status\nhalrf_config_rfk_with_header_file(void *dm_void, u32 config_type)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tenum hal_status result = HAL_STATUS_SUCCESS;\n#if 0\n#if (RTL8822B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8822B) {\n\t\tif (config_type == CONFIG_BB_RF_CAL_INIT)\n\t\t\todm_read_and_config_mp_8822b_cal_init(dm);\n\t}\n#endif\n#endif\n#if (RTL8198F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8198F) {\n\t\tif (config_type == CONFIG_BB_RF_CAL_INIT)\n\t\t\todm_read_and_config_mp_8198f_cal_init(dm);\n\t}\n#endif\n#if (RTL8812F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8812F) {\n\t\tif (config_type == CONFIG_BB_RF_CAL_INIT)\n\t\t\todm_read_and_config_mp_8812f_cal_init(dm);\n\t}\n#endif\n#if (RTL8822C_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8822C) {\n\t\tif (config_type == CONFIG_BB_RF_CAL_INIT)\n\t\t\todm_read_and_config_mp_8822c_cal_init(dm);\n\t}\n#endif\n#if (RTL8814B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8814B) {\n\t\tif (config_type == CONFIG_BB_RF_CAL_INIT)\n\t\t\todm_read_and_config_mp_8814b_cal_init(dm);\n\t}\n#endif\n#if (RTL8195B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8195B) {\n\t\tif (config_type == CONFIG_BB_RF_CAL_INIT)\n\t\t\todm_read_and_config_mp_8195b_cal_init(dm);\n\t}\n#endif\n\treturn result;\n}\n\nvoid halrf_txgapk_trigger(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tu64 start_time;\n\n\tstart_time = odm_get_current_time(dm);\n\n\tswitch (dm->support_ic_type) {\n#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))\n#if (RTL8195B_SUPPORT == 1)\n\tcase ODM_RTL8195B:\n\t\tphy_txgap_calibrate_8195b(dm, false);\n\tbreak;\n#endif\n#endif\n\n\tdefault:\n\t\tbreak;\n\t}\n\trf->dpk_progressing_time =\n\t\todm_get_progressing_time(dm_void, start_time);\n\tRF_DBG(dm, DBG_RF_TXGAPK, \"[TGGC]TXGAPK progressing_time = %lld ms\\n\",\n\t       rf->dpk_progressing_time);\n}\n\nvoid halrf_tssi_get_efuse(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\t\n#if (RTL8822C_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8822C) {\n\t\t/*halrf_tssi_get_efuse_8822c(dm);*/\n\t\t/*halrf_tssi_get_kfree_efuse_8822c(dm);*/\n\t\thalrf_get_efuse_thermal_pwrtype_8822c(dm);\n\t}\n#endif\n\n#if (RTL8814B_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8814B) {\n\t\thalrf_tssi_get_efuse_8814b(dm);\n\t}\n#endif\n\n}\n\nvoid halrf_do_tssi(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if (RTL8822C_SUPPORT == 1)\n\t/*halrf_do_tssi_8822c(dm);*/\n\thalrf_do_thermal_8822c(dm);\n\n#endif\n}\n\nvoid halrf_do_thermal(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if (RTL8822C_SUPPORT == 1)\n\thalrf_do_thermal_8822c(dm);\n#endif\n}\n\n\n\nu32 halrf_set_tssi_value(void *dm_void, u32 tssi_value)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if (RTL8822C_SUPPORT == 1)\n\treturn halrf_set_tssi_value_8822c(dm, tssi_value);\n#endif\n\treturn 0;\n}\n\nvoid halrf_set_tssi_power(void *dm_void, s8 power)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if (RTL8822C_SUPPORT == 1)\n\t/*halrf_set_tssi_poewr_8822c(dm, power);*/\n#endif\n}\n\nvoid halrf_tssi_set_de_for_tx_verify(void *dm_void, u32 tssi_de, u8 path)\n{\n\treturn;\n}\nu32 halrf_query_tssi_value(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if (RTL8822C_SUPPORT == 1)\n\t/*return halrf_query_tssi_value_8822c(dm);*/\n#endif\n\treturn 0;\n}\n\nvoid halrf_tssi_cck(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if (RTL8822C_SUPPORT == 1)\n\t/*halrf_tssi_cck_8822c(dm);*/\n\thalrf_thermal_cck_8822c(dm);\n#endif\n\n}\n\nvoid halrf_thermal_cck(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if (RTL8822C_SUPPORT == 1)\n\thalrf_thermal_cck_8822c(dm);\n#endif\n\n}\n\nvoid halrf_tssi_set_de(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\t\n#if (RTL8814B_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8814B)\n\t\thalrf_tssi_set_de_8814b(dm);\n#endif\t\n}\n\nvoid halrf_tssi_dck(void *dm_void, u8 direct_do)\n{\n\n}\n\nvoid halrf_calculate_tssi_codeword(void *dm_void)\n{\n\t\n}\n\nvoid halrf_set_tssi_codeword(void *dm_void)\n{\n\n}\n\nu8 halrf_get_tssi_codeword_for_txindex(void *dm_void)\n{\n\treturn 0;\n}\n\n\nu32 halrf_tssi_get_de(void *dm_void, u8 path)\n{\n\treturn 0;\n}\n\n/*Golbal function*/\nvoid halrf_reload_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 i;\n\n\tfor (i = 0; i < num; i++)\n\t\todm_write_4byte(dm, bp_reg[i], bp[i]);\n}\n\nvoid halrf_reload_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num,\n\t\t       u8 ss)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 i, path;\n\n\tfor (i = 0; i < num; i++) {\n\t\tfor (path = 0; path < ss; path++)\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path, bp_reg[i],\n\t\t\t\t       MASK20BITS, bp[i][path]);\n\t}\n}\n\nvoid halrf_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 i;\n\n\tfor (i = 0; i < num; i++)\n\t\tbp[i] = odm_read_4byte(dm, bp_reg[i]);\n}\n\nvoid halrf_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num, u8 ss)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 i, path;\n\n\tfor (i = 0; i < num; i++) {\n\t\tfor (path = 0; path < ss; path++) {\n\t\t\tbp[i][path] =\n\t\t\t\todm_get_rf_reg(dm, (enum rf_path)path,\n\t\t\t\t\t       bp_reg[i], MASK20BITS);\n\t\t}\n\t}\n}\n\nvoid halrf_swap(void *dm_void, u32 *v1, u32 *v2)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 temp;\n\n\ttemp = *v1;\n\t*v1 = *v2;\n\t*v2 = temp;\n}\n\nvoid halrf_bubble(void *dm_void, u32 *v1, u32 *v2)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 temp;\n\n\tif (*v1 >= 0x200 && *v2 >= 0x200) {\n\t\tif (*v1 > *v2)\n\t\t\thalrf_swap(dm, v1, v2);\n\t} else if (*v1 < 0x200 && *v2 < 0x200) {\n\t\tif (*v1 > *v2)\n\t\t\thalrf_swap(dm, v1, v2);\n\t} else if (*v1 < 0x200 && *v2 >= 0x200) {\n\t\thalrf_swap(dm, v1, v2);\n\t}\n}\n\nvoid halrf_b_sort(void *dm_void, u32 *iv, u32 *qv)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 temp;\n\tu32 i, j;\n\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]bubble!!!!!!!!!!!!\");\n\tfor (i = 0; i < SN - 1; i++) {\n\t\tfor (j = 0; j < (SN - 1 - i) ; j++) {\n\t\t\thalrf_bubble(dm, &iv[j], &iv[j + 1]);\n\t\t\thalrf_bubble(dm, &qv[j], &qv[j + 1]);\n\t\t}\n\t}\n}\n\nvoid halrf_minmax_compare(void *dm_void, u32 value, u32 *min,\n\t\t\t  u32 *max)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (value >= 0x200) {\n\t\tif (*min >= 0x200) {\n\t\t\tif (*min > value)\n\t\t\t\t*min = value;\n\t\t} else {\n\t\t\t*min = value;\n\t\t}\n\t\tif (*max >= 0x200) {\n\t\t\tif (*max < value)\n\t\t\t\t*max = value;\n\t\t}\n\t} else {\n\t\tif (*min < 0x200) {\n\t\t\tif (*min > value)\n\t\t\t\t*min = value;\n\t\t}\n\n\t\tif (*max  >= 0x200) {\n\t\t\t*max = value;\n\t\t} else {\n\t\t\tif (*max < value)\n\t\t\t\t*max = value;\n\t\t}\n\t}\n}\n\nu32 halrf_delta(void *dm_void, u32 v1, u32 v2)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (v1 >= 0x200 && v2 >= 0x200) {\n\t\tif (v1 > v2)\n\t\t\treturn v1 - v2;\n\t\telse\n\t\t\treturn v2 - v1;\n\t} else if (v1 >= 0x200 && v2 < 0x200) {\n\t\treturn v2 + (0x400 - v1);\n\t} else if (v1 < 0x200 && v2 >= 0x200) {\n\t\treturn v1 + (0x400 - v2);\n\t}\n\n\tif (v1 > v2)\n\t\treturn v1 - v2;\n\telse\n\t\treturn v2 - v1;\n}\n\nboolean halrf_compare(void *dm_void, u32 value)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tboolean fail = false;\n\n\tif (value >= 0x200 && (0x400 - value) > 0x64)\n\t\tfail = true;\n\telse if (value < 0x200 && value > 0x64)\n\t\tfail = true;\n\n\tif (fail)\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]overflow!!!!!!!!!!!!!!!\");\n\treturn fail;\n}\n\nvoid halrf_mode(void *dm_void, u32 *i_value, u32 *q_value)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 iv[SN], qv[SN], im[SN], qm[SN], temp, temp1, temp2;\n\tu32 p, m, t;\n\tu32 i_max = 0, q_max = 0, i_min = 0x0, q_min = 0x0, c = 0x0;\n\tu32 i_delta, q_delta;\n\tu8 i, j, ii = 0, qi = 0;\n\tboolean fail = false;\n\n\tODM_delay_ms(10);\n\tfor (i = 0; i < SN; i++) {\n\t\tim[i] = 0;\n\t\tqm[i] = 0;\n\t}\n\ti = 0;\n\tc = 0;\n\twhile (i < SN && c < 1000) {\n\t\tc++;\n\t\ttemp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);\n\t\tiv[i] = (temp & 0x3ff000) >> 12;\n\t\tqv[i] = temp & 0x3ff;\n\n\t\tfail = false;\n\t\tif (halrf_compare(dm, iv[i]))\n\t\t\tfail = true;\n\t\tif (halrf_compare(dm, qv[i]))\n\t\t\tfail = true;\n\t\tif (!fail)\n\t\t\ti++;\n\t}\n\tc = 0;\n\tdo {\n\t\tc++;\n\t\ti_min = iv[0];\n\t\ti_max = iv[0];\n\t\tq_min = qv[0];\n\t\tq_max = qv[0];\n\t\tfor (i = 0; i < SN; i++) {\n\t\t\thalrf_minmax_compare(dm, iv[i], &i_min, &i_max);\n\t\t\thalrf_minmax_compare(dm, qv[i], &q_min, &q_max);\n\t\t}\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]i_min=0x%x, i_max=0x%x\",\n\t\t       i_min, i_max);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]q_min=0x%x, q_max=0x%x\",\n\t\t       q_min, q_max);\n\t\tif (i_max < 0x200 && i_min < 0x200)\n\t\t\ti_delta = i_max - i_min;\n\t\telse if (i_max >= 0x200 && i_min >= 0x200)\n\t\t\ti_delta = i_max - i_min;\n\t\telse\n\t\t\ti_delta = i_max + (0x400 - i_min);\n\n\t\tif (q_max < 0x200 && q_min < 0x200)\n\t\t\tq_delta = q_max - q_min;\n\t\telse if (q_max >= 0x200 && q_min >= 0x200)\n\t\t\tq_delta = q_max - q_min;\n\t\telse\n\t\t\tq_delta = q_max + (0x400 - q_min);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]i_delta=0x%x, q_delta=0x%x\",\n\t\t       i_delta, q_delta);\n\t\thalrf_b_sort(dm, iv, qv);\n\t\tif (i_delta > 5 || q_delta > 5) {\n\t\t\ttemp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);\n\t\t\tiv[0] = (temp & 0x3ff000) >> 12;\n\t\t\tqv[0] = temp & 0x3ff;\n\t\t\ttemp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);\n\t\t\tiv[SN - 1] = (temp & 0x3ff000) >> 12;\n\t\t\tqv[SN - 1] = temp & 0x3ff;\n\t\t} else {\n\t\t\tbreak;\n\t\t}\n\t} while (c < 100);\n#if 1\n#if 0\n\tfor (i = 0; i < SN; i++)\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]iv[%d] = 0x%x\\n\", i, iv[i]);\n\tfor (i = 0; i < SN; i++)\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]qv[%d] = 0x%x\\n\", i, qv[i]);\n#endif\n\t/*i*/\n\tm = 0;\n\tp = 0;\n\tfor (i = 10; i < SN - 10; i++) {\n\t\tif (iv[i] > 0x200)\n\t\t\tm = (0x400 - iv[i]) + m;\n\t\telse\n\t\t\tp = iv[i] + p;\n\t}\n\n\tif (p > m) {\n\t\tt = p - m;\n\t\tt = t / (SN - 20);\n\t} else {\n\t\tt = m - p;\n\t\tt = t / (SN - 20);\n\t\tif (t != 0x0)\n\t\t\tt = 0x400 - t;\n\t}\n\t*i_value = t;\n\t/*q*/\n\tm = 0;\n\tp = 0;\n\tfor (i = 10; i < SN - 10; i++) {\n\t\tif (qv[i] > 0x200)\n\t\t\tm = (0x400 - qv[i]) + m;\n\t\telse\n\t\t\tp = qv[i] + p;\n\t}\n\tif (p > m) {\n\t\tt = p - m;\n\t\tt = t / (SN - 20);\n\t} else {\n\t\tt = m - p;\n\t\tt = t / (SN - 20);\n\t\tif (t != 0x0)\n\t\t\tt = 0x400 - t;\n\t}\n\t*q_value = t;\n#endif\n}\n\n"
  },
  {
    "path": "hal/phydm/halrf/halrf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALRF_H__\n#define __HALRF_H__\n\n/*@============================================================*/\n/*@include files*/\n/*@============================================================*/\n#include \"halrf/halrf_psd.h\"\n#if (RTL8822B_SUPPORT == 1)\n#include \"halrf/rtl8822b/halrf_rfk_init_8822b.h\"\n#endif\n#if (RTL8822C_SUPPORT == 1)\n#include \"halrf/rtl8822c/halrf_rfk_init_8822c.h\"\n#include \"halrf/rtl8822c/halrf_iqk_8822c.h\"\n#include \"halrf/rtl8822c/halrf_tssi_8822c.h\"\n#include \"halrf/rtl8822c/halrf_dpk_8822c.h\"\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n#if (RTL8198F_SUPPORT == 1)\n#include \"halrf/rtl8198f/halrf_rfk_init_8198f.h\"\n#endif\n#if (RTL8812F_SUPPORT == 1)\n#include \"halrf/rtl8812f/halrf_rfk_init_8812f.h\"\n#endif\n\n#endif\n\n#if (RTL8814B_SUPPORT == 1)\n#include \"halrf/rtl8814b/halrf_rfk_init_8814b.h\"\n#include \"halrf/rtl8814b/halrf_iqk_8814b.h\"\n#include \"halrf/rtl8814b/halrf_dpk_8814b.h\"\n#endif\n\n/*@============================================================*/\n/*@Definition */\n/*@============================================================*/\n/*IQK version*/\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\n#define IQK_VER_8188E \"0x14\"\n#define IQK_VER_8192E \"0x01\"\n#define IQK_VER_8192F \"0x01\"\n#define IQK_VER_8723B \"0x1e\"\n#define IQK_VER_8812A \"0x02\"\n#define IQK_VER_8821A \"0x02\"\n#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))\n#define IQK_VER_8188E \"0x01\"\n#define IQK_VER_8192E \"0x01\"\n#define IQK_VER_8192F \"0x01\"\n#define IQK_VER_8723B \"0x1e\"\n#define IQK_VER_8812A \"0x01\"\n#define IQK_VER_8821A \"0x01\"\n#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n#define IQK_VER_8188E \"0x01\"\n#define IQK_VER_8192E \"0x01\"\n#define IQK_VER_8192F \"0x01\"\n#define IQK_VER_8723B \"0x1e\"\n#define IQK_VER_8812A \"0x01\"\n#define IQK_VER_8821A \"0x01\"\n#elif (DM_ODM_SUPPORT_TYPE & (ODM_IOT))\n#define IQK_VER_8188E \"0x01\"\n#define IQK_VER_8192E \"0x01\"\n#define IQK_VER_8192F \"0x01\"\n#define IQK_VER_8723B \"0x1e\"\n#define IQK_VER_8812A \"0x01\"\n#define IQK_VER_8821A \"0x01\"\n#endif\n#define IQK_VER_8814A \"0x0f\"\n#define IQK_VER_8188F \"0x01\"\n#define IQK_VER_8197F \"0x1d\"\n#define IQK_VER_8703B \"0x05\"\n#define IQK_VER_8710B \"0x01\"\n#define IQK_VER_8723D \"0x02\"\n#define IQK_VER_8822B \"0x30\"\n#define IQK_VER_8822C \"0x0d\"\n#define IQK_VER_8821C \"0x23\"\n#define IQK_VER_8198F \"0x09\"\n#define IQK_VER_8814B \"0x0b\"\n#define IQK_VER_8812F \"0x07\"\n\n/*LCK version*/\n#define LCK_VER_8188E \"0x02\"\n#define LCK_VER_8192E \"0x02\"\n#define LCK_VER_8192F \"0x01\"\n#define LCK_VER_8723B \"0x02\"\n#define LCK_VER_8812A \"0x01\"\n#define LCK_VER_8821A \"0x01\"\n#define LCK_VER_8814A \"0x01\"\n#define LCK_VER_8188F \"0x01\"\n#define LCK_VER_8197F \"0x01\"\n#define LCK_VER_8703B \"0x01\"\n#define LCK_VER_8710B \"0x01\"\n#define LCK_VER_8723D \"0x01\"\n#define LCK_VER_8822B \"0x02\"\n#define LCK_VER_8822C \"0x00\"\n#define LCK_VER_8821C \"0x02\"\n#define LCK_VER_8814B \"0x00\"\n#define LCK_VER_8195B \"0x02\"\n\n/*power tracking version*/\n#define PWRTRK_VER_8188E \"0x01\"\n#define PWRTRK_VER_8192E \"0x01\"\n#define PWRTRK_VER_8192F \"0x01\"\n#define PWRTRK_VER_8723B \"0x01\"\n#define PWRTRK_VER_8812A \"0x01\"\n#define PWRTRK_VER_8821A \"0x01\"\n#define PWRTRK_VER_8814A \"0x01\"\n#define PWRTRK_VER_8188F \"0x01\"\n#define PWRTRK_VER_8197F \"0x01\"\n#define PWRTRK_VER_8703B \"0x01\"\n#define PWRTRK_VER_8710B \"0x01\"\n#define PWRTRK_VER_8723D \"0x01\"\n#define PWRTRK_VER_8822B \"0x01\"\n#define PWRTRK_VER_8822C \"0x00\"\n#define PWRTRK_VER_8821C \"0x01\"\n#define PWRTRK_VER_8814B \"0x00\"\n\n/*DPK version*/\n#define DPK_VER_8188E \"NONE\"\n#define DPK_VER_8192E \"NONE\"\n#define DPK_VER_8723B \"NONE\"\n#define DPK_VER_8812A \"NONE\"\n#define DPK_VER_8821A \"NONE\"\n#define DPK_VER_8814A \"NONE\"\n#define DPK_VER_8188F \"NONE\"\n#define DPK_VER_8197F \"0x08\"\n#define DPK_VER_8703B \"NONE\"\n#define DPK_VER_8710B \"NONE\"\n#define DPK_VER_8723D \"NONE\"\n#define DPK_VER_8822B \"NONE\"\n#define DPK_VER_8822C \"0x19\"\n#define DPK_VER_8821C \"NONE\"\n#define DPK_VER_8192F \"0x0d\"\n#define DPK_VER_8198F \"0x0a\"\n#define DPK_VER_8814B \"0x04\"\n#define DPK_VER_8195B \"0x0a\"\n#define DPK_VER_8812F \"0x02\"\n\n/*RFK_INIT version*/\n#define RFK_INIT_VER_8822B \"0x8\"\n#define RFK_INIT_VER_8822C \"0x7\"\n#define RFK_INIT_VER_8195B \"0x1\"\n#define RFK_INIT_VER_8198F \"0x5\"\n#define RFK_INIT_VER_8814B \"0x5\"\n#define RFK_INIT_VER_8812F \"0x2\"\n\n\n/*DACK version*/\n#define DACK_VER_8822C \"0xa\"\n#define DACK_VER_8814B \"0x3\"\n\n/*Kfree tracking version*/\n#define KFREE_VER_8188E \\\n\t\t(dm->power_trim_data.flag & KFREE_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define KFREE_VER_8192E \\\n\t\t(dm->power_trim_data.flag & KFREE_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define KFREE_VER_8192F \\\n\t\t(dm->power_trim_data.flag & KFREE_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define KFREE_VER_8723B \\\n\t\t(dm->power_trim_data.flag & KFREE_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define KFREE_VER_8812A \\\n\t\t(dm->power_trim_data.flag & KFREE_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define KFREE_VER_8821A \\\n\t\t(dm->power_trim_data.flag & KFREE_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define KFREE_VER_8814A \\\n\t\t(dm->power_trim_data.flag & KFREE_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define KFREE_VER_8188F \\\n\t\t(dm->power_trim_data.flag & KFREE_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define KFREE_VER_8197F \\\n\t\t(dm->power_trim_data.flag & KFREE_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define KFREE_VER_8703B \\\n\t\t(dm->power_trim_data.flag & KFREE_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define KFREE_VER_8710B \\\n\t\t(dm->power_trim_data.flag & KFREE_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define KFREE_VER_8723D \\\n\t\t(dm->power_trim_data.flag & KFREE_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define KFREE_VER_8822B \\\n\t\t(dm->power_trim_data.flag & KFREE_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define KFREE_VER_8822C \\\n\t\t(dm->power_trim_data.flag & KFREE_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define KFREE_VER_8821C \\\n\t\t(dm->power_trim_data.flag & KFREE_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define KFREE_VER_8814B \\\n\t\t(dm->power_trim_data.flag & KFREE_FLAG_ON) ? \"0x01\" : \"NONE\"\n\n/*PA Bias Calibration version*/\n#define PABIASK_VER_8188E \\\n\t(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define PABIASK_VER_8192E \\\n\t(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define PABIASK_VER_8192F \\\n\t(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define PABIASK_VER_8723B \\\n\t(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define PABIASK_VER_8812A \\\n\t(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define PABIASK_VER_8821A \\\n\t(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define PABIASK_VER_8814A \\\n\t(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define PABIASK_VER_8188F \\\n\t(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define PABIASK_VER_8197F \\\n\t(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define PABIASK_VER_8703B \\\n\t(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define PABIASK_VER_8710B \\\n\t(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define PABIASK_VER_8723D \\\n\t(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define PABIASK_VER_8822B \\\n\t(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define PABIASK_VER_8822C \\\n\t(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define PABIASK_VER_8821C \\\n\t(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? \"0x01\" : \"NONE\"\n#define PABIASK_VER_8814B \\\n\t(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? \"0x01\" : \"NONE\"\n\n#define HALRF_IQK_VER \\\n\t(dm->support_ic_type == ODM_RTL8188E) ? IQK_VER_8188E : \\\n\t(dm->support_ic_type == ODM_RTL8192E) ? IQK_VER_8192E : \\\n\t(dm->support_ic_type == ODM_RTL8192F) ? IQK_VER_8192F : \\\n\t(dm->support_ic_type == ODM_RTL8723B) ? IQK_VER_8723B : \\\n\t(dm->support_ic_type == ODM_RTL8812) ? IQK_VER_8812A : \\\n\t(dm->support_ic_type == ODM_RTL8821) ? IQK_VER_8821A : \\\n\t(dm->support_ic_type == ODM_RTL8814A) ? IQK_VER_8814A : \\\n\t(dm->support_ic_type == ODM_RTL8188F) ? IQK_VER_8188F : \\\n\t(dm->support_ic_type == ODM_RTL8197F) ? IQK_VER_8197F : \\\n\t(dm->support_ic_type == ODM_RTL8703B) ? IQK_VER_8703B : \\\n\t(dm->support_ic_type == ODM_RTL8710B) ? IQK_VER_8710B : \\\n\t(dm->support_ic_type == ODM_RTL8723D) ? IQK_VER_8723D : \\\n\t(dm->support_ic_type == ODM_RTL8822B) ? IQK_VER_8822B : \\\n\t(dm->support_ic_type == ODM_RTL8822C) ? IQK_VER_8822C : \\\n\t(dm->support_ic_type == ODM_RTL8821C) ? IQK_VER_8821C : \\\n\t(dm->support_ic_type == ODM_RTL8814B) ? IQK_VER_8814B : \"unknown\"\n\n#define HALRF_LCK_VER \\\n\t(dm->support_ic_type == ODM_RTL8188E) ? LCK_VER_8188E : \\\n\t(dm->support_ic_type == ODM_RTL8192E) ? LCK_VER_8192E : \\\n\t(dm->support_ic_type == ODM_RTL8192F) ? LCK_VER_8192F : \\\n\t(dm->support_ic_type == ODM_RTL8723B) ? LCK_VER_8723B : \\\n\t(dm->support_ic_type == ODM_RTL8812) ? LCK_VER_8812A : \\\n\t(dm->support_ic_type == ODM_RTL8821) ? LCK_VER_8821A : \\\n\t(dm->support_ic_type == ODM_RTL8814A) ? LCK_VER_8814A : \\\n\t(dm->support_ic_type == ODM_RTL8188F) ? LCK_VER_8188F : \\\n\t(dm->support_ic_type == ODM_RTL8197F) ? LCK_VER_8197F : \\\n\t(dm->support_ic_type == ODM_RTL8703B) ? LCK_VER_8703B : \\\n\t(dm->support_ic_type == ODM_RTL8710B) ? LCK_VER_8710B : \\\n\t(dm->support_ic_type == ODM_RTL8723D) ? LCK_VER_8723D : \\\n\t(dm->support_ic_type == ODM_RTL8822B) ? LCK_VER_8822B : \\\n\t(dm->support_ic_type == ODM_RTL8822C) ? LCK_VER_8822C : \\\n\t(dm->support_ic_type == ODM_RTL8821C) ? LCK_VER_8821C : \\\n\t(dm->support_ic_type == ODM_RTL8814B) ? LCK_VER_8814B : \"unknown\"\n\n#define HALRF_POWRTRACKING_VER \\\n\t(dm->support_ic_type == ODM_RTL8188E) ? PWRTRK_VER_8188E : \\\n\t(dm->support_ic_type == ODM_RTL8192E) ? PWRTRK_VER_8192E : \\\n\t(dm->support_ic_type == ODM_RTL8192F) ? PWRTRK_VER_8192F : \\\n\t(dm->support_ic_type == ODM_RTL8723B) ? PWRTRK_VER_8723B : \\\n\t(dm->support_ic_type == ODM_RTL8812) ? PWRTRK_VER_8812A : \\\n\t(dm->support_ic_type == ODM_RTL8821) ? PWRTRK_VER_8821A : \\\n\t(dm->support_ic_type == ODM_RTL8814A) ? PWRTRK_VER_8814A : \\\n\t(dm->support_ic_type == ODM_RTL8188F) ? PWRTRK_VER_8188F : \\\n\t(dm->support_ic_type == ODM_RTL8197F) ? PWRTRK_VER_8197F : \\\n\t(dm->support_ic_type == ODM_RTL8703B) ? PWRTRK_VER_8703B : \\\n\t(dm->support_ic_type == ODM_RTL8710B) ? PWRTRK_VER_8710B : \\\n\t(dm->support_ic_type == ODM_RTL8723D) ? PWRTRK_VER_8723D : \\\n\t(dm->support_ic_type == ODM_RTL8822B) ? PWRTRK_VER_8822B : \\\n\t(dm->support_ic_type == ODM_RTL8822C) ? PWRTRK_VER_8822C : \\\n\t(dm->support_ic_type == ODM_RTL8821C) ? PWRTRK_VER_8821C : \\\n\t(dm->support_ic_type == ODM_RTL8814B) ? PWRTRK_VER_8814B : \"unknown\"\n\n#define HALRF_DPK_VER \\\n\t(dm->support_ic_type == ODM_RTL8188E) ? DPK_VER_8188E : \\\n\t(dm->support_ic_type == ODM_RTL8192E) ? DPK_VER_8192E : \\\n\t(dm->support_ic_type == ODM_RTL8192F) ? DPK_VER_8192F : \\\n\t(dm->support_ic_type == ODM_RTL8723B) ? DPK_VER_8723B : \\\n\t(dm->support_ic_type == ODM_RTL8812) ? DPK_VER_8812A : \\\n\t(dm->support_ic_type == ODM_RTL8821) ? DPK_VER_8821A : \\\n\t(dm->support_ic_type == ODM_RTL8814A) ? DPK_VER_8814A : \\\n\t(dm->support_ic_type == ODM_RTL8188F) ? DPK_VER_8188F : \\\n\t(dm->support_ic_type == ODM_RTL8197F) ? DPK_VER_8197F : \\\n\t(dm->support_ic_type == ODM_RTL8198F) ? DPK_VER_8198F : \\\n\t(dm->support_ic_type == ODM_RTL8703B) ? DPK_VER_8703B : \\\n\t(dm->support_ic_type == ODM_RTL8710B) ? DPK_VER_8710B : \\\n\t(dm->support_ic_type == ODM_RTL8723D) ? DPK_VER_8723D : \\\n\t(dm->support_ic_type == ODM_RTL8822B) ? DPK_VER_8822B : \\\n\t(dm->support_ic_type == ODM_RTL8822C) ? DPK_VER_8822C : \\\n\t(dm->support_ic_type == ODM_RTL8821C) ? DPK_VER_8821C : \\\n\t(dm->support_ic_type == ODM_RTL8814B) ? DPK_VER_8814B : \"unknown\"\n\n#define HALRF_KFREE_VER \\\n\t(dm->support_ic_type == ODM_RTL8188E) ? KFREE_VER_8188E : \\\n\t(dm->support_ic_type == ODM_RTL8192E) ? KFREE_VER_8192E : \\\n\t(dm->support_ic_type == ODM_RTL8192F) ? KFREE_VER_8192F : \\\n\t(dm->support_ic_type == ODM_RTL8723B) ? KFREE_VER_8723B : \\\n\t(dm->support_ic_type == ODM_RTL8812) ? KFREE_VER_8812A : \\\n\t(dm->support_ic_type == ODM_RTL8821) ? KFREE_VER_8821A : \\\n\t(dm->support_ic_type == ODM_RTL8814A) ? KFREE_VER_8814A : \\\n\t(dm->support_ic_type == ODM_RTL8188F) ? KFREE_VER_8188F : \\\n\t(dm->support_ic_type == ODM_RTL8197F) ? KFREE_VER_8197F : \\\n\t(dm->support_ic_type == ODM_RTL8703B) ? KFREE_VER_8703B : \\\n\t(dm->support_ic_type == ODM_RTL8710B) ? KFREE_VER_8710B : \\\n\t(dm->support_ic_type == ODM_RTL8723D) ? KFREE_VER_8723D : \\\n\t(dm->support_ic_type == ODM_RTL8822B) ? KFREE_VER_8822B : \\\n\t(dm->support_ic_type == ODM_RTL8822C) ? KFREE_VER_8822C : \\\n\t(dm->support_ic_type == ODM_RTL8821C) ? KFREE_VER_8821C : \\\n\t(dm->support_ic_type == ODM_RTL8814B) ? KFREE_VER_8814B : \"unknown\"\n\n#define HALRF_PABIASK_VER \\\n\t(dm->support_ic_type == ODM_RTL8188E) ? PABIASK_VER_8188E : \\\n\t(dm->support_ic_type == ODM_RTL8192E) ? PABIASK_VER_8192E : \\\n\t(dm->support_ic_type == ODM_RTL8192F) ? PABIASK_VER_8192F : \\\n\t(dm->support_ic_type == ODM_RTL8723B) ? PABIASK_VER_8723B : \\\n\t(dm->support_ic_type == ODM_RTL8812) ? PABIASK_VER_8812A : \\\n\t(dm->support_ic_type == ODM_RTL8821) ? PABIASK_VER_8821A : \\\n\t(dm->support_ic_type == ODM_RTL8814A) ? PABIASK_VER_8814A : \\\n\t(dm->support_ic_type == ODM_RTL8188F) ? PABIASK_VER_8188F : \\\n\t(dm->support_ic_type == ODM_RTL8197F) ? PABIASK_VER_8197F : \\\n\t(dm->support_ic_type == ODM_RTL8703B) ? PABIASK_VER_8703B : \\\n\t(dm->support_ic_type == ODM_RTL8710B) ? PABIASK_VER_8710B : \\\n\t(dm->support_ic_type == ODM_RTL8723D) ? PABIASK_VER_8723D : \\\n\t(dm->support_ic_type == ODM_RTL8822B) ? PABIASK_VER_8822B : \\\n\t(dm->support_ic_type == ODM_RTL8822C) ? PABIASK_VER_8822C : \\\n\t(dm->support_ic_type == ODM_RTL8821C) ? PABIASK_VER_8821C : \\\n\t(dm->support_ic_type == ODM_RTL8814B) ? PABIASK_VER_8814B : \"unknown\"\n\n#define HALRF_RFK_INIT_VER \\\n\t(dm->support_ic_type == ODM_RTL8822B) ? RFK_INIT_VER_8822B : \\\n\t(dm->support_ic_type == ODM_RTL8822C) ? RFK_INIT_VER_8822C : \\\n\t(dm->support_ic_type == ODM_RTL8198F) ? RFK_INIT_VER_8198F : \\\n\t(dm->support_ic_type == ODM_RTL8814B) ? RFK_INIT_VER_8814B : \"unknown\"\n\n#define HALRF_DACK_VER \\\n\t(dm->support_ic_type == ODM_RTL8822C) ? DACK_VER_8822C : \"unknown\"\n\n#define IQK_THRESHOLD 8\n#define DPK_THRESHOLD 4\n#define HALRF_ABS(a,b) ((a>b) ? (a-b) : (b-a))\n#define SN 100\n\n#define CCK_TSSI_NUM 6\n#define OFDM_2G_TSSI_NUM 5\n#define OFDM_5G_TSSI_NUM 14\n\n\n\n/*@===========================================================*/\n/*AGC RX High Power mode*/\n/*@===========================================================*/\n#define lna_low_gain_1 0x64\n#define lna_low_gain_2 0x5A\n#define lna_low_gain_3 0x58\n\n/*@============================================================*/\n/*@ enumeration */\n/*@============================================================*/\n\n#define POWER_INDEX_DIFF 4\n#define TSSI_TXAGC_DIFF 2\n\n#define TSSI_CODE_NUM 84\n\n#define TSSI_SLOPE_2G 8\n#define TSSI_SLOPE_5G 5\n\n#define TSSI_EFUSE_NUM 25\n#define TSSI_EFUSE_KFREE_NUM 4\n\n\nenum halrf_func_idx { /*F_XXX = PHYDM XXX function*/\n\tRF00_PWR_TRK = 0, /*Pow_trk, TSSI_trk*/\n\tRF01_IQK = 1,\t  /*LOK, IQK*/\n\tRF02_LCK = 2,\n\tRF03_DPK = 3,\n\tRF04_TXGAPK = 4,\n\tRF05_DACK = 5,\n\tRF06_DPK_TRK = 6,\n};\n\nenum halrf_ability {\n\tHAL_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),\n\tHAL_RF_IQK = BIT(RF01_IQK),\n\tHAL_RF_LCK = BIT(RF02_LCK),\n\tHAL_RF_DPK = BIT(RF03_DPK),\n\tHAL_RF_TXGAPK = BIT(RF04_TXGAPK),\n\tHAL_RF_DACK = BIT(RF05_DACK),\n\tHAL_RF_DPK_TRACK = BIT(RF06_DPK_TRK)\n};\n\nenum halrf_dbg_comp {\n\tDBG_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),\n\tDBG_RF_IQK = BIT(RF01_IQK),\n\tDBG_RF_LCK = BIT(RF02_LCK),\n\tDBG_RF_DPK = BIT(RF03_DPK),\n\tDBG_RF_TXGAPK = BIT(RF04_TXGAPK),\n\tDBG_RF_DACK = BIT(RF05_DACK),\n\tDBG_RF_MP = BIT(29),\n\tDBG_RF_TMP = BIT(30),\n\tDBG_RF_INIT = BIT(31)\n};\n\nenum halrf_cmninfo_init {\n\tHALRF_CMNINFO_ABILITY = 0,\n\tHALRF_CMNINFO_DPK_EN = 1,\n\tHALRF_CMNINFO_EEPROM_THERMAL_VALUE,\n\tHALRF_CMNINFO_RFK_FORBIDDEN,\n\tHALRF_CMNINFO_IQK_SEGMENT,\n\tHALRF_CMNINFO_RATE_INDEX,\n\tHALRF_CMNINFO_PWT_TYPE,\n\tHALRF_CMNINFO_MP_PSD_POINT,\n\tHALRF_CMNINFO_MP_PSD_START_POINT,\n\tHALRF_CMNINFO_MP_PSD_STOP_POINT,\n\tHALRF_CMNINFO_MP_PSD_AVERAGE,\n\tHALRF_CMNINFO_IQK_TIMES\n};\n\nenum halrf_cmninfo_hook {\n\tHALRF_CMNINFO_CON_TX,\n\tHALRF_CMNINFO_SINGLE_TONE,\n\tHALRF_CMNINFO_CARRIER_SUPPRESSION,\n\tHALRF_CMNINFO_MP_RATE_INDEX,\n\tHALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY\n};\n\nenum halrf_lna_set {\n\tHALRF_LNA_DISABLE = 0,\n\tHALRF_LNA_ENABLE = 1,\n};\n\nenum halrf_k_segment_time {\n\tSEGMENT_FREE = 0,\n\tSEGMENT_10MS = 10, /*10ms*/\n\tSEGMENT_30MS = 30, /*30ms*/\n\tSEGMENT_50MS = 50, /*50ms*/\n};\n\n\n#if (RTL8822C_SUPPORT == 1 || RTL8812F_SUPPORT == 1 || RTL8814B_SUPPORT)\n\n#define POWER_INDEX_DIFF 4\n#define TSSI_TXAGC_DIFF 2\n\n#define TSSI_CODE_NUM 84\n\n#define TSSI_SLOPE_2G 8\n#define TSSI_SLOPE_5G 5\n\n#define TSSI_EFUSE_NUM 25\n#define TSSI_EFUSE_KFREE_NUM 4\n\nstruct _halrf_tssi_data {\n\ts32 cck_offset_patha;\n\ts32 cck_offset_pathb;\n\ts32 power_track_offset[PHYDM_MAX_RF_PATH];\n\ts16 txagc_codeword[TSSI_CODE_NUM];\n\tu16 tssi_codeword[TSSI_CODE_NUM];\n\ts8 tssi_efuse[PHYDM_MAX_RF_PATH][TSSI_EFUSE_NUM];\n\ts8 tssi_kfree_efuse[PHYDM_MAX_RF_PATH][TSSI_EFUSE_KFREE_NUM];\n\tu8 thermal[PHYDM_MAX_RF_PATH];\n\tu32 index[PHYDM_MAX_RF_PATH][14];\n\tu8 do_tssi;\n\tu8 get_thermal;\n};\n#endif\n\n/*@============================================================*/\n/*@ structure */\n/*@============================================================*/\n\nstruct _hal_rf_ {\n\t/*hook*/\n\tu8 *test1;\n\n\t/*update*/\n\tu32 rf_supportability;\n\n\tu8 eeprom_thermal;\n\tu8 dpk_en; /*Enable Function DPK OFF/ON = 0/1*/\n\tboolean dpk_done;\n\tu64 dpk_progressing_time;\n\tu64 iqk_progressing_time;\n\tu32 fw_ver;\n\n\tboolean *is_con_tx;\n\tboolean *is_single_tone;\n\tboolean *is_carrier_suppresion;\n\tboolean is_dpk_in_progress;\n\tboolean is_tssi_in_progress;\n\tboolean is_bt_iqk_timeout;\n\tboolean aac_checked;\n\n\tu8 *mp_rate_index;\n\tu32 *manual_rf_supportability;\n\tu32 p_rate_index;\n\tu8 pwt_type;\n\tu32 rf_dbg_comp;\n\tstruct _halrf_psd_data halrf_psd_data;\n#if (RTL8822C_SUPPORT == 1 || RTL8812F_SUPPORT == 1 || RTL8814B_SUPPORT == 1)\n\tstruct _halrf_tssi_data halrf_tssi_data;\n#endif\n\tu8 power_track_type;\n};\n\n/*@============================================================*/\n/*@ function prototype */\n/*@============================================================*/\n\n#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\\\n\tRTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\\\n\tRTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\\\n\tRTL8812F_SUPPORT == 1)\nvoid halrf_iqk_info_dump(void *dm_void, u32 *_used, char *output,\n\t\t\t u32 *_out_len);\n\nvoid halrf_iqk_hwtx_check(void *dm_void, boolean is_check);\n#endif\n\nu8 halrf_match_iqk_version(void *dm_void);\n\nvoid halrf_support_ability_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t\t\t char *output, u32 *_out_len);\n\nvoid halrf_cmn_info_init(void *dm_void, enum halrf_cmninfo_init cmn_info,\n\t\t\t u32 value);\n\nvoid halrf_cmn_info_hook(void *dm_void, enum halrf_cmninfo_hook cmn_info,\n\t\t\t void *value);\n\nvoid halrf_cmn_info_set(void *dm_void, u32 cmn_info, u64 value);\n\nu64 halrf_cmn_info_get(void *dm_void, u32 cmn_info);\n\nvoid halrf_watchdog(void *dm_void);\n\nvoid halrf_supportability_init(void *dm_void);\n\nvoid halrf_init(void *dm_void);\n\nvoid halrf_iqk_trigger(void *dm_void, boolean is_recovery);\n\nvoid halrf_rfk_handshake(void *dm_void, boolean is_before_k);\n\nvoid halrf_rf_k_connect_trigger(void *dm_void, boolean is_recovery,\n\t\t\t\tenum halrf_k_segment_time seg_time);\n\nvoid halrf_segment_iqk_trigger(void *dm_void, boolean clear,\n\t\t\t       boolean segment_iqk);\n\nvoid halrf_lck_trigger(void *dm_void);\n\nvoid halrf_iqk_debug(void *dm_void, u32 *const dm_value, u32 *_used,\n\t\t     char *output, u32 *_out_len);\n\nvoid phydm_get_iqk_cfir(void *dm_void, u8 idx, u8 path, boolean debug);\n\nvoid halrf_iqk_xym_read(void *dm_void, u8 path, u8 xym_type);\n\nvoid halrf_rf_lna_setting(void *dm_void, enum halrf_lna_set type);\n\nvoid halrf_do_imr_test(void *dm_void, u8 data);\n\nu32 halrf_psd_log2base(u32 val);\n\nvoid halrf_dpk_trigger(void *dm_void);\n\nu8 halrf_dpk_result_check(void *dm_void);\n\nvoid halrf_dpk_sram_read(void *dm_void);\n\nvoid halrf_dpk_enable_disable(void *dm_void);\n\nvoid halrf_dpk_track(void *dm_void);\n\nvoid halrf_dpk_reload(void *dm_void);\n\nvoid halrf_dpk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size);\n\n/*Global function*/\n\nvoid halrf_reload_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num);\n\nvoid halrf_reload_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num,\n\t\t       u8 ss);\n\nvoid halrf_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num);\n\nvoid halrf_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num, u8 ss);\n\nvoid halrf_mode(void *dm_void, u32 *i_value, u32 *q_value);\n\nboolean halrf_compare(void *dm_void, u32 value);\n\nu32 halrf_delta(void *dm_void, u32 v1, u32 v2);\n\nvoid halrf_minmax_compare(void *dm_void, u32 value, u32 *min, u32 *max);\n\nvoid halrf_b_sort(void *dm_void, u32 *iv, u32 *qv);\n\nvoid halrf_bubble(void *dm_void, u32 *v1, u32 *v2);\n\nvoid halrf_swap(void *dm_void, u32 *v1, u32 *v2);\n\nenum hal_status\nhalrf_config_rfk_with_header_file(void *dm_void, u32 config_type);\n\n#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\\\n\tRTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\\\n\tRTL8814B_SUPPORT == 1  || RTL8822C_SUPPORT == 1 ||\\\n\tRTL8812F_SUPPORT == 1)\nvoid halrf_iqk_dbg(void *dm_void);\n#endif\n\nvoid halrf_tssi_get_efuse(void *dm_void);\n\nvoid halrf_do_tssi(void *dm_void);\n\nvoid halrf_do_thermal(void *dm_void);\n\nu32 halrf_set_tssi_value(void *dm_void, u32 tssi_value);\n\nvoid halrf_tssi_set_de_for_tx_verify(void *dm_void, u32 tssi_de, u8 path);\n\nvoid halrf_set_tssi_power(void *dm_void, s8 power);\n\nu32 halrf_query_tssi_value(void *dm_void);\n\nvoid halrf_tssi_cck(void *dm_void);\n\nvoid halrf_thermal_cck(void *dm_void);\n\nvoid halrf_tssi_set_de(void *dm_void);\n\nvoid halrf_tssi_dck(void *dm_void, u8 direct_do);\n\nvoid halrf_calculate_tssi_codeword(void *dm_void);\n\nvoid halrf_set_tssi_codeword(void *dm_void);\n\nu8 halrf_get_tssi_codeword_for_txindex(void *dm_void);\n\nu32 halrf_tssi_get_de(void *dm_void, u8 path);\n\nvoid halrf_set_dpk_track(void *dm_void, u8 enable);\n\nvoid halrf_set_dpkbychannel(void *dm_void, boolean dpk_by_ch);\n\nvoid halrf_set_dpkenable(void *dm_void, boolean is_dpk_enable);\n\nboolean halrf_get_dpkbychannel(void *dm_void);\n\nboolean halrf_get_dpkenable(void *dm_void);\n\nvoid _iqk_check_if_reload(void *dm_void);\n\nvoid halrf_dack_dbg(void *dm_void);\n\nvoid halrf_iqk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size);\n\nvoid halrf_set_rfsupportability(void *dm_void);\n#endif /*__HALRF_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_debug.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n * ************************************************************\n */\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\nvoid halrf_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len)\n{\n#ifdef CONFIG_PHYDM_DEBUG_FUNCTION\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 rf_release_ver = 0;\n\n#if (RTL8822C_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8822C) {\n\t\trf_release_ver = RF_RELEASE_VERSION_8822C;\n\t}\n#endif\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %d\\n\",\n\t\t \"RF Para Release Ver\", rf_release_ver);\n\n\t/* HAL RF version List */\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"%-35s\\n\",\n\t\t \"% HAL RF version %\");\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"Power Tracking\", HALRF_POWRTRACKING_VER);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"  %-35s: %s %s\\n\", \"IQK\",\n\t\t (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? \"FW\" :\n\t\t HALRF_IQK_VER,\n\t\t (halrf_match_iqk_version(dm_void)) ? \"(match)\" : \"(mismatch)\");\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"LCK\", HALRF_LCK_VER);\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"DPK\", HALRF_DPK_VER);\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"KFREE\", HALRF_KFREE_VER);\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"TX 2G Current Calibration\", HALRF_PABIASK_VER);\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"RFK Init. Parameter\", HALRF_RFK_INIT_VER);\n\n\t*_used = used;\n\t*_out_len = out_len;\n#endif\n}\n\nvoid halrf_debug_trace(void *dm_void, char input[][16], u32 *_used,\n\t\t       char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tu32 one = 1;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 rf_var[10] = {0};\n\tu8 i;\n\n\tfor (i = 0; i < 5; i++)\n\t\tif (input[i + 1])\n\t\t\tPHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &rf_var[i]);\n\n\tif (rf_var[0] == 100) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\n[DBG MSG] RF Selection\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"00. (( %s ))TX_PWR_TRACK\\n\",\n\t\t\t ((rf->rf_dbg_comp & DBG_RF_TX_PWR_TRACK) ? (\"V\") :\n\t\t\t (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"01. (( %s ))IQK\\n\",\n\t\t\t ((rf->rf_dbg_comp & DBG_RF_IQK) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"02. (( %s ))LCK\\n\",\n\t\t\t ((rf->rf_dbg_comp & DBG_RF_LCK) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"03. (( %s ))DPK\\n\",\n\t\t\t ((rf->rf_dbg_comp & DBG_RF_DPK) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"04. (( %s ))TXGAPK\\n\",\n\t\t\t ((rf->rf_dbg_comp & DBG_RF_TXGAPK) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"29. (( %s ))MP\\n\",\n\t\t\t ((rf->rf_dbg_comp & DBG_RF_MP) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"30. (( %s ))TMP\\n\",\n\t\t\t ((rf->rf_dbg_comp & DBG_RF_TMP) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"31. (( %s ))INIT\\n\",\n\t\t\t ((rf->rf_dbg_comp & DBG_RF_INIT) ? (\"V\") : (\".\")));\n\n\t} else if (rf_var[0] == 101) {\n\t\trf->rf_dbg_comp = 0;\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Disable all DBG COMP\\n\");\n\t} else {\n\t\tif (rf_var[1] == 1) /*enable*/\n\t\t\trf->rf_dbg_comp |= (one << rf_var[0]);\n\t\telse if (rf_var[1] == 2) /*disable*/\n\t\t\trf->rf_dbg_comp &= ~(one << rf_var[0]);\n\t}\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\nCurr-RF_Dbg_Comp = 0x%x\\n\", rf->rf_dbg_comp);\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nstruct halrf_command {\n\tchar name[16];\n\tu8 id;\n};\n\nenum halrf_CMD_ID {\n\tHALRF_HELP,\n\tHALRF_SUPPORTABILITY,\n\tHALRF_DBG_COMP,\n\tHALRF_PROFILE,\n\tHALRF_IQK_INFO,\n\tHALRF_IQK,\n\tHALRF_IQK_DEBUG,\n};\n\nstruct halrf_command halrf_cmd_ary[] = {\n\t{\"-h\", HALRF_HELP},\n\t{\"ability\", HALRF_SUPPORTABILITY},\n\t{\"dbg\", HALRF_DBG_COMP},\n\t{\"profile\", HALRF_PROFILE},\n\t{\"iqk_info\", HALRF_IQK_INFO},\n\t{\"iqk\", HALRF_IQK},\n\t{\"iqk_dbg\", HALRF_IQK_DEBUG},\n};\n\nvoid halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t      u32 *_out_len, u32 input_num)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#ifdef CONFIG_PHYDM_DEBUG_FUNCTION\n\tu8 id = 0;\n\tu32 rf_var[10] = {0};\n\tu32 i, input_idx = 0;\n\tu32 halrf_ary_size =\n\t\t\tsizeof(halrf_cmd_ary) / sizeof(struct halrf_command);\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\t/* Parsing Cmd ID */\n\tfor (i = 0; i < halrf_ary_size; i++) {\n\t\tif (strcmp(halrf_cmd_ary[i].name, input[1]) == 0) {\n\t\t\tid = halrf_cmd_ary[i].id;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (i == halrf_ary_size) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"RF Cmd not found\\n\");\n\t\treturn;\n\t}\n\n\tswitch (id) {\n\tcase HALRF_HELP:\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"RF cmd ==>\\n\");\n\n\t\tfor (i = 0; i < halrf_ary_size - 1; i++) {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"  %-5d: %s\\n\", i, halrf_cmd_ary[i + 1].name);\n\t\t}\n\t\tbreak;\n\tcase HALRF_SUPPORTABILITY:\n\t\thalrf_support_ability_debug(dm, &input[0], &used, output,\n\t\t\t\t\t    &out_len);\n\t\tbreak;\n\tcase HALRF_DBG_COMP:\n\t\thalrf_debug_trace(dm, &input[0], &used, output, &out_len);\n\t\tbreak;\n\tcase HALRF_PROFILE:\n\t\thalrf_basic_profile(dm, &used, output, &out_len);\n\t\tbreak;\n\tcase HALRF_IQK_INFO:\n#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)\n\t\thalrf_iqk_info_dump(dm, &used, output, &out_len);\n#endif\n\t\tbreak;\n\tcase HALRF_IQK:\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"TRX IQK Trigger\\n\");\n\t\thalrf_iqk_trigger(dm, false);\n#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)\n\t\thalrf_iqk_info_dump(dm, &used, output, &out_len);\n#endif\n\t\tbreak;\n\tcase HALRF_IQK_DEBUG:\n\n\t\tfor (i = 0; i < 5; i++) {\n\t\t\tif (input[i + 1]) {\n\t\t\t\tPHYDM_SSCANF(input[i + 2], DCMD_HEX,\n\t\t\t\t\t     &rf_var[i]);\n\t\t\t\tinput_idx++;\n\t\t\t}\n\t\t}\n\n\t\tif (input_idx >= 1) {\n#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)\n\t\t\tif (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C))\n\t\t\t\thalrf_iqk_debug(dm, (u32 *)rf_var, &used,\n\t\t\t\t\t\toutput, &out_len);\n#endif\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n#endif\n}\n\nvoid halrf_init_debug_setting(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\trf->rf_dbg_comp =\n#if DBG\n#if 0\n\t/*DBG_RF_TX_PWR_TRACK\t|*/\n\t/*DBG_RF_IQK\t\t| */\n\t/*DBG_RF_LCK\t\t| */\n\t/*DBG_RF_DPK\t\t| */\n\t/*DBG_RF_DACK\t\t| */\n\t/*DBG_RF_TXGAPK\t\t| */\n\t/*DBG_RF_MP\t\t\t| */\n\t/*DBG_RF_TMP\t\t| */\n\t/*DBG_RF_INIT\t\t| */\n#endif\n#endif\n\t0;\n}\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_debug.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALRF_DEBUG_H__\n#define __HALRF_DEBUG_H__\n\n/*@============================================================*/\n/*@include files*/\n/*@============================================================*/\n\n/*@============================================================*/\n/*@Definition */\n/*@============================================================*/\n\n#if DBG\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n#define RF_DBG(dm, comp, fmt, args...)                     \\\n\tdo {                                               \\\n\t\tif ((comp) & dm->rf_table.rf_dbg_comp) { \\\n\t\t\tpr_debug(\"[RF] \");                 \\\n\t\t\tRT_PRINTK(fmt, ##args);            \\\n\t\t}                                          \\\n\t} while (0)\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\nstatic __inline void RF_DBG(PDM_ODM_T dm, int comp, char *fmt, ...)\n{\n\tRT_STATUS rt_status;\n\tva_list args;\n\tchar buf[PRINT_MAX_SIZE] = {0};\n\n\tif ((comp & dm->rf_table.rf_dbg_comp) == 0)\n\t\treturn;\n\n\tif (fmt == NULL)\n\t\treturn;\n\n\tva_start(args, fmt);\n\trt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);\n\tva_end(args);\n\n\tif (rt_status != RT_STATUS_SUCCESS) {\n\t\tDbgPrint(\"Failed (%d) to print message to buffer\\n\", rt_status);\n\t\treturn;\n\t}\n\n\tDbgPrint(\"[RF] %s\", buf);\n}\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)\n\n#define RF_DBG(dm, comp, fmt, args...)                     \\\n\tdo {                                               \\\n\t\tif ((comp) & dm->rf_table.rf_dbg_comp) { \\\n\t\t\tRT_DEBUG(COMP_PHYDM, DBG_DMESG, \"[RF] \" fmt, ##args);  \\\n\t\t}                                          \\\n\t} while (0)\n\n#else\n#define RF_DBG(dm, comp, fmt, args...)                                         \\\n\tdo {                                                                   \\\n\t\tstruct dm_struct *__dm = dm;                                   \\\n\t\tif ((comp) & __dm->rf_table.rf_dbg_comp) {                     \\\n\t\t\tRT_TRACE(((struct rtl_priv *)__dm->adapter),           \\\n\t\t\t\t COMP_PHYDM, DBG_DMESG, \"[RF] \" fmt, ##args);  \\\n\t\t}                                                              \\\n\t} while (0)\n#endif\n\n#else /*#if DBG*/\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nstatic __inline void RF_DBG(struct dm_struct *dm, int comp, char *fmt, ...)\n{\n}\n#else\n#define RF_DBG(dm, comp, fmt, args...)\n#endif\n\n#endif /*#if DBG*/\n\n/*@============================================================*/\n/*@ enumeration */\n/*@============================================================*/\n\n/*@============================================================*/\n/*@ structure */\n/*@============================================================*/\n\n/*@============================================================*/\n/*@ function prototype */\n/*@============================================================*/\n\nvoid halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t      u32 *_out_len, u32 input_num);\n\nvoid halrf_init_debug_setting(void *dm_void);\n\n#endif /*__HALRF_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_dpk.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALRF_DPK_H__\n#define __HALRF_DPK_H__\n\n/*@--------------------------Define Parameters-------------------------------*/\n#define GAIN_LOSS 1\n#define DO_DPK 2\n#define DPK_ON 3\n#define DPK_LOK 4\n#define DPK_TXK 5\n\n#define DAGC 4\n#define LOSS_CHK 0\n#define GAIN_CHK 1\n#define PAS_READ 2\n#define AVG_THERMAL_NUM 8\n#define AVG_THERMAL_NUM_DPK 8\n#define THERMAL_DPK_AVG_NUM 4\n\n/*@---------------------------End Define Parameters---------------------------*/\n\nstruct dm_dpk_info {\n\n\tboolean\tis_dpk_enable;\n\tboolean\tis_dpk_pwr_on;\n\tboolean\tis_dpk_by_channel;\n\tboolean is_tssi_mode;\n\tboolean is_reload;\n\tu16 dpk_path_ok;\n\t/*@BIT(15)~BIT(12) : 5G reserved, BIT(11)~BIT(8) 5G_S3~5G_S0*/\n\t/*@BIT(7)~BIT(4) : 2G reserved, BIT(3)~BIT(0) 2G_S3~2G_S0*/\n\tu8\tthermal_dpk[4];\t\t\t\t\t/*path*/\t\n\tu8\tthermal_dpk_avg[4][AVG_THERMAL_NUM_DPK];\t/*path*/\n\tu8\tthermal_dpk_avg_index;\n\tu8\tpre_pwsf[4];\n\tu32\tgnt_control;\n\tu32\tgnt_value;\n\tu8\tdpk_ch;\n\tu8\tdpk_band;\n\tu8\tdpk_bw;\n\n#if (RTL8822C_SUPPORT == 1 || RTL8812F_SUPPORT == 1)\n\tu8\tresult[2];\t\t\t/*path*/\n\tu8\tdpk_txagc[2];\t\t\t/*path*/\n\tu32\tcoef[2][20];\t\t\t/*path/MDPD coefficient*/\n\tu16\tdpk_gs[2];\t\t\t/*MDPD coef gs*/\n\tu8\tthermal_dpk_delta[2];\t\t/*path*/\n#endif\n\n#if (RTL8198F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8814B_SUPPORT)\n\t/*2G DPK data*/\n\tu8 \tdpk_result[4][3];\t\t/*path/group*/\n\tu8 \tpwsf_2g[4][3];\t\t\t/*path/group*/\t\n\tu32\tlut_2g_even[4][3][64];\t\t/*path/group/LUT data*/\n\tu32\tlut_2g_odd[4][3][64];\t\t/*path/group/LUT data*/\n\t/*5G DPK data*/\n\tu8\tdpk_5g_result[4][6];\t\t/*path/group*/\n\tu8\tpwsf_5g[4][6];\t\t\t/*path/group*/\n\tu32\tlut_5g[4][6][64];\t\t/*path/group/LUT data*/\n\tu32\tlut_2g[4][3][64];\t\t/*path/group/LUT data*/\n\t/*8814B*/\n\tu8\trxbb[4];\t\t\t/*path/group*/\n\tu8\ttxbb[4];\t\t\t/*path/group*/\n\tu8\ttx_gain;\n#endif\n\n#if (RTL8195B_SUPPORT == 1)\n\t\t/*2G DPK data*/\n\t\tu8\tdpk_2g_result[1][3];\t\t/*path/group*/\n\t\tu8\tpwsf_2g[1][3];\t\t\t/*path/group*/\n\t\tu32\tlut_2g_even[1][3][16];\t\t/*path/group/LUT data*/\n\t\tu32\tlut_2g_odd[1][3][16];\t\t/*path/group/LUT data*/\n\t\t/*5G DPK data*/\n\t\tu8\tdpk_5g_result[1][13];\t\t/*path/group*/\n\t\tu8\tpwsf_5g[1][13];\t\t\t/*path/group*/\n\t\tu32\tlut_5g_even[1][13][16];\t\t/*path/group/LUT data*/\n\t\tu32\tlut_5g_odd[1][13][16];\t\t/*path/group/LUT data*/\n#endif\n\n};\n\n#endif /*__HALRF_DPK_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_features.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALRF_FEATURES_H__\n#define __HALRF_FEATURES_H__\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\n#define CONFIG_HALRF_POWERTRACKING 1\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\n#define CONFIG_HALRF_POWERTRACKING 1\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\n#define CONFIG_HALRF_POWERTRACKING 1\n\n#endif\n\n#endif /*#ifndef __HALRF_FEATURES_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_iqk.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALRF_IQK_H__\n#define __HALRF_IQK_H__\n\n/*@--------------------------Define Parameters-------------------------------*/\n#define LOK_delay 1\n#define WBIQK_delay 10\n#define TX_IQK 0\n#define RX_IQK 1\n#define TXIQK 0\n#define RXIQK1 1\n#define RXIQK2 2\n#define kcount_limit_80m 2\n#define kcount_limit_others 4\n#define rxiqk_gs_limit 6\n#define TXWBIQK_EN 1\n#define RXWBIQK_EN 1\n#define NUM 4\n/*@-----------------------End Define Parameters-----------------------*/\n\nstruct dm_dack_info {\n\tu32 ic_a;\n\tu32 qc_a;\n\tu32 ic_b;\n\tu32 qc_b;\n\tboolean dack_en;\n\tu16 msbk_d[2][2][15];\n\tu8 dck_d[2][2][2];\n\tu16 biask_d[2][2];\n};\n\nstruct dm_iqk_info {\n\tboolean lok_fail[NUM];\n\tboolean iqk_fail[2][NUM];\n\tu32 iqc_matrix[2][NUM];\n\tu8 iqk_times;\n\tu32 rf_reg18;\n\tu32 rf_reg08;\n\tu32 lna_idx;\n\tu8 iqk_step;\n\tu8 rxiqk_step;\n\tu8 tmp1bcc;\n\tu8 txgain;\n\tu32 txgain56;\n\tu8 kcount;\n\tu8 rfk_ing; /*bit0:IQKing, bit1:LCKing, bit2:DPKing*/\n\tboolean rfk_forbidden;\n\tu8 rxbb;\n\tu32 rf_reg58;\n\tboolean segment_iqk;\n#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\\\n\tRTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\\\n\tRTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\\\n\tRTL8812F_SUPPORT == 1 || RTL8197G_SUPPORT == 1 )\n\tu32 iqk_channel[2];\n\tboolean iqk_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */\n\t/*channel / path / TRX(TX:0, RX:1) / CFIR_real*/\n\t/*channel index = 2 is just for debug*/\n#if (RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 )\n\tu16 iqk_cfir_real[3][2][2][17];\n\t/*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/\n\t/*channel index = 2 is just for debug*/\n\tu16 iqk_cfir_imag[3][2][2][17];\n\tu32 rx_cfir_real[2][2][17];\n\tu32 rx_cfir_imag[2][2][17];\n\tu32 rx_cfir[2][2];\n\t/*times/path*/\n#else\n\tu32 iqk_cfir_real[3][4][2][8];\n\t/*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/\n\t/*channel index = 2 is just for debug*/\n\tu32 iqk_cfir_imag[3][4][2][8];\n#endif\n\tu8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */\n\tu8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */\n\t/* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */\n\tu8 rxiqk_fail_code[2][4];\n\tu32 lok_idac[2][4]; /*channel / path*/\n\tu16 rxiqk_agc[2][4]; /*channel / path*/\n\tu32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/\n\tu32 txgap_result[8]; /*txagpK result  */\n\tu32 tmp_gntwl;\n\tboolean is_btg;\n\tboolean isbnd;\n\tboolean is_reload;\n\tboolean is_hwtx;\n\tboolean xym_read;\n\tboolean trximr_enable;\n\tu32 rx_xym[2][10];\n\tu32 tx_xym[2][10];\n\tu32 gs1_xym[2][6];\n\tu32 gs2_xym[2][6];\n\tu32 rxk1_xym[2][6];\n\tu32 txxy[2][2];\n\tu32 rxxy[2][2];\n#endif\n};\n\n#endif /*__HALRF_IQK_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_kfree.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@============================================================*/\n/*@include files*/\n/*@============================================================*/\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n/*@<YuChen, 150720> Add for KFree Feature Requested by RF David.*/\n/*@This is a phydm API*/\n\nvoid phydm_set_kfree_to_rf_8814a(void *dm_void, u8 e_rf_path, u8 data)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;\n\tboolean is_odd;\n\tu32 tx_gain_bitmask = (BIT(17) | BIT(16) | BIT(15));\n\n\tif ((data % 2) != 0) { /*odd->positive*/\n\t\tdata = data - 1;\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), 1);\n\t\tis_odd = true;\n\t} else { /*even->negative*/\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), 0);\n\t\tis_odd = false;\n\t}\n\tRF_DBG(dm, DBG_RF_MP, \"phy_ConfigKFree8814A(): RF_0x55[19]= %d\\n\",\n\t       is_odd);\n\tswitch (data) {\n\tcase 0:\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 0);\n\t\tcali_info->kfree_offset[e_rf_path] = 0;\n\t\tbreak;\n\tcase 2:\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 0);\n\t\tcali_info->kfree_offset[e_rf_path] = 0;\n\t\tbreak;\n\tcase 4:\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 1);\n\t\tcali_info->kfree_offset[e_rf_path] = 1;\n\t\tbreak;\n\tcase 6:\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 1);\n\t\tcali_info->kfree_offset[e_rf_path] = 1;\n\t\tbreak;\n\tcase 8:\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 2);\n\t\tcali_info->kfree_offset[e_rf_path] = 2;\n\t\tbreak;\n\tcase 10:\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 2);\n\t\tcali_info->kfree_offset[e_rf_path] = 2;\n\t\tbreak;\n\tcase 12:\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 3);\n\t\tcali_info->kfree_offset[e_rf_path] = 3;\n\t\tbreak;\n\tcase 14:\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 3);\n\t\tcali_info->kfree_offset[e_rf_path] = 3;\n\t\tbreak;\n\tcase 16:\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 4);\n\t\tcali_info->kfree_offset[e_rf_path] = 4;\n\t\tbreak;\n\tcase 18:\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 4);\n\t\tcali_info->kfree_offset[e_rf_path] = 4;\n\t\tbreak;\n\tcase 20:\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 5);\n\t\tcali_info->kfree_offset[e_rf_path] = 5;\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (!is_odd) {\n\t\t/*that means Kfree offset is negative, we need to record it.*/\n\t\tcali_info->kfree_offset[e_rf_path] =\n\t\t\t\t(-1) * cali_info->kfree_offset[e_rf_path];\n\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t       \"phy_ConfigKFree8814A(): kfree_offset = %d\\n\",\n\t\t       cali_info->kfree_offset[e_rf_path]);\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t       \"phy_ConfigKFree8814A(): kfree_offset = %d\\n\",\n\t\t       cali_info->kfree_offset[e_rf_path]);\n\t}\n}\n\nvoid phydm_get_thermal_trim_offset_8821c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *power_trim_info = &dm->power_trim_data;\n\n\tu8 pg_therm = 0xff;\n\n\todm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_21C, &pg_therm, false);\n\n\tif (pg_therm != 0xff) {\n\t\tpg_therm = pg_therm & 0x1f;\n\t\tif ((pg_therm & BIT(0)) == 0)\n\t\t\tpower_trim_info->thermal = (-1 * (pg_therm >> 1));\n\t\telse\n\t\t\tpower_trim_info->thermal = (pg_therm >> 1);\n\n\t\tpower_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;\n\t}\n\n\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8821c thermal trim flag:0x%02x\\n\",\n\t       power_trim_info->flag);\n\n\tif (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)\n\t\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8821c thermal:%d\\n\",\n\t\t       power_trim_info->thermal);\n}\n\nvoid phydm_get_power_trim_offset_8821c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *power_trim_info = &dm->power_trim_data;\n\n\tu8 pg_power = 0xff, i;\n\n\todm_efuse_one_byte_read(dm, PPG_2G_TXAB_21C, &pg_power, false);\n\n\tif (pg_power != 0xff) {\n\t\tpower_trim_info->bb_gain[0][0] = pg_power;\n\t\todm_efuse_one_byte_read(dm, PPG_5GL1_TXA_21C, &pg_power, false);\n\t\tpower_trim_info->bb_gain[1][0] = pg_power;\n\t\todm_efuse_one_byte_read(dm, PPG_5GL2_TXA_21C, &pg_power, false);\n\t\tpower_trim_info->bb_gain[2][0] = pg_power;\n\t\todm_efuse_one_byte_read(dm, PPG_5GM1_TXA_21C, &pg_power, false);\n\t\tpower_trim_info->bb_gain[3][0] = pg_power;\n\t\todm_efuse_one_byte_read(dm, PPG_5GM2_TXA_21C, &pg_power, false);\n\t\tpower_trim_info->bb_gain[4][0] = pg_power;\n\t\todm_efuse_one_byte_read(dm, PPG_5GH1_TXA_21C, &pg_power, false);\n\t\tpower_trim_info->bb_gain[5][0] = pg_power;\n\t\tpower_trim_info->flag =\n\t\t\tpower_trim_info->flag | KFREE_FLAG_ON |\n\t\t\tKFREE_FLAG_ON_2G | KFREE_FLAG_ON_5G;\n\t}\n\n\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8821c power trim flag:0x%02x\\n\",\n\t       power_trim_info->flag);\n\n\tif (power_trim_info->flag & KFREE_FLAG_ON) {\n\t\tfor (i = 0; i < KFREE_BAND_NUM; i++)\n\t\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t\t       \"[kfree] 8821c pwr_trim->bb_gain[%d][0]=0x%X\\n\",\n\t\t\t       i, power_trim_info->bb_gain[i][0]);\n\t}\n}\n\nvoid phydm_set_kfree_to_rf_8821c(void *dm_void, u8 e_rf_path, boolean wlg_btg,\n\t\t\t\t u8 data)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 wlg, btg;\n\tu32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));\n\tu32 s_gain_bmask = (BIT(19) | BIT(18) | BIT(17) |\n\t\t\t    BIT(16) | BIT(15) | BIT(14));\n\n\todm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);\n\todm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 1);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 1);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 1);\n\n\tif (wlg_btg) {\n\t\twlg = data & 0xf;\n\t\tbtg = (data & 0xf0) >> 4;\n\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (wlg & BIT(0)));\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, (wlg >> 1));\n\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(19), (btg & BIT(0)));\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x65, gain_bmask, (btg >> 1));\n\t} else {\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), data & BIT(0));\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,\n\t\t\t       ((data & 0x1f) >> 1));\n\t}\n\n\tRF_DBG(dm, DBG_RF_MP,\n\t       \"[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\\n\",\n\t       odm_get_rf_reg(dm, e_rf_path, RF_0x55, s_gain_bmask),\n\t       odm_get_rf_reg(dm, e_rf_path, RF_0x65, s_gain_bmask));\n}\n\nvoid phydm_clear_kfree_to_rf_8821c(void *dm_void, u8 e_rf_path, u8 data)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));\n\tu32 s_gain_bmask = (BIT(19) | BIT(18) | BIT(17) |\n\t\t\t    BIT(16) | BIT(15) | BIT(14));\n\n\todm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);\n\todm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 1);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 1);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 1);\n\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, (data >> 1));\n\n\todm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(19), (data & BIT(0)));\n\todm_set_rf_reg(dm, e_rf_path, RF_0x65, gain_bmask, (data >> 1));\n\n\todm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 0);\n\todm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 0);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 0);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 0);\n\n\tRF_DBG(dm, DBG_RF_MP,\n\t       \"[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\\n\",\n\t       odm_get_rf_reg(dm, e_rf_path, RF_0x55, s_gain_bmask),\n\t       odm_get_rf_reg(dm, e_rf_path, RF_0x65, s_gain_bmask));\n}\n\nvoid phydm_get_thermal_trim_offset_8822b(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *power_trim_info = &dm->power_trim_data;\n\n\tu8 pg_therm = 0xff;\n\n\todm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_22B, &pg_therm, false);\n\n\tif (pg_therm != 0xff) {\n\t\tpg_therm = pg_therm & 0x1f;\n\t\tif ((pg_therm & BIT(0)) == 0)\n\t\t\tpower_trim_info->thermal = (-1 * (pg_therm >> 1));\n\t\telse\n\t\t\tpower_trim_info->thermal = (pg_therm >> 1);\n\n\t\tpower_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;\n\t}\n\n\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8822b thermal trim flag:0x%02x\\n\",\n\t       power_trim_info->flag);\n\n\tif (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)\n\t\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8822b thermal:%d\\n\",\n\t\t       power_trim_info->thermal);\n}\n\nvoid phydm_get_power_trim_offset_8822b(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *power_trim_info = &dm->power_trim_data;\n\n\tu8 pg_power = 0xff, i, j;\n\n\todm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false);\n\n\tif (pg_power != 0xff) {\n\t\t/*Path A*/\n\t\todm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false);\n\t\tpower_trim_info->bb_gain[0][0] = (pg_power & 0xf);\n\n\t\t/*Path B*/\n\t\todm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false);\n\t\tpower_trim_info->bb_gain[0][1] = ((pg_power & 0xf0) >> 4);\n\n\t\tpower_trim_info->flag |= KFREE_FLAG_ON_2G;\n\t\tpower_trim_info->flag |= KFREE_FLAG_ON;\n\t}\n\n\todm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22B, &pg_power, false);\n\n\tif (pg_power != 0xff) {\n\t\t/*Path A*/\n\t\todm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22B, &pg_power, false);\n\t\tpower_trim_info->bb_gain[1][0] = pg_power;\n\t\todm_efuse_one_byte_read(dm, PPG_5GL2_TXA_22B, &pg_power, false);\n\t\tpower_trim_info->bb_gain[2][0] = pg_power;\n\t\todm_efuse_one_byte_read(dm, PPG_5GM1_TXA_22B, &pg_power, false);\n\t\tpower_trim_info->bb_gain[3][0] = pg_power;\n\t\todm_efuse_one_byte_read(dm, PPG_5GM2_TXA_22B, &pg_power, false);\n\t\tpower_trim_info->bb_gain[4][0] = pg_power;\n\t\todm_efuse_one_byte_read(dm, PPG_5GH1_TXA_22B, &pg_power, false);\n\t\tpower_trim_info->bb_gain[5][0] = pg_power;\n\n\t\t/*Path B*/\n\t\todm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22B, &pg_power, false);\n\t\tpower_trim_info->bb_gain[1][1] = pg_power;\n\t\todm_efuse_one_byte_read(dm, PPG_5GL2_TXB_22B, &pg_power, false);\n\t\tpower_trim_info->bb_gain[2][1] = pg_power;\n\t\todm_efuse_one_byte_read(dm, PPG_5GM1_TXB_22B, &pg_power, false);\n\t\tpower_trim_info->bb_gain[3][1] = pg_power;\n\t\todm_efuse_one_byte_read(dm, PPG_5GM2_TXB_22B, &pg_power, false);\n\t\tpower_trim_info->bb_gain[4][1] = pg_power;\n\t\todm_efuse_one_byte_read(dm, PPG_5GH1_TXB_22B, &pg_power, false);\n\t\tpower_trim_info->bb_gain[5][1] = pg_power;\n\n\t\tpower_trim_info->flag |= KFREE_FLAG_ON_5G;\n\t\tpower_trim_info->flag |= KFREE_FLAG_ON;\n\t}\n\n\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8822b power trim flag:0x%02x\\n\",\n\t       power_trim_info->flag);\n\n\tif (!(power_trim_info->flag & KFREE_FLAG_ON))\n\t\treturn;\n\n\tfor (i = 0; i < KFREE_BAND_NUM; i++) {\n\t\tfor (j = 0; j < 2; j++)\n\t\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t\t       \"[kfree] 8822b PwrTrim->bb_gain[%d][%d]=0x%X\\n\",\n\t\t\t       i, j, power_trim_info->bb_gain[i][j]);\n\t}\n}\n\nvoid phydm_set_pa_bias_to_rf_8822b(void *dm_void, u8 e_rf_path, s8 tx_pa_bias)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 rf_reg_51 = 0, rf_reg_52 = 0, rf_reg_3f = 0;\n\tu32 tx_pa_bias_bmask = (BIT(12) | BIT(11) | BIT(10) | BIT(9));\n\n\trf_reg_51 = odm_get_rf_reg(dm, e_rf_path, RF_0x51, RFREGOFFSETMASK);\n\trf_reg_52 = odm_get_rf_reg(dm, e_rf_path, RF_0x52, RFREGOFFSETMASK);\n\n\tRF_DBG(dm, DBG_RF_MP,\n\t       \"[kfree] 8822b 2g rf(0x51)=0x%X rf(0x52)=0x%X path=%d\\n\",\n\t       rf_reg_51, rf_reg_52, e_rf_path);\n\n#if 0\n\t/*rf3f => rf52[19:17] = rf3f[2:0] rf52[16:15] = rf3f[4:3] rf52[3:0] = rf3f[8:5]*/\n\t/*rf3f => rf51[6:3] = rf3f[12:9] rf52[13] = rf3f[13]*/\n#endif\n\trf_reg_3f = ((rf_reg_52 & 0xe0000) >> 17) |\n\t\t    (((rf_reg_52 & 0x18000) >> 15) << 3) |\n\t\t    ((rf_reg_52 & 0xf) << 5) |\n\t\t    (((rf_reg_51 & 0x78) >> 3) << 9) |\n\t\t    (((rf_reg_52 & 0x2000) >> 13) << 13);\n\n\tRF_DBG(dm, DBG_RF_MP,\n\t       \"[kfree] 8822b 2g original pa_bias=%d rf_reg_3f=0x%X path=%d\\n\",\n\t       tx_pa_bias, rf_reg_3f, e_rf_path);\n\n\ttx_pa_bias = (s8)((rf_reg_3f & tx_pa_bias_bmask) >> 9) + tx_pa_bias;\n\n\tif (tx_pa_bias < 0)\n\t\ttx_pa_bias = 0;\n\telse if (tx_pa_bias > 7)\n\t\ttx_pa_bias = 7;\n\n\trf_reg_3f = ((rf_reg_3f & 0xfe1ff) | (tx_pa_bias << 9));\n\n\tRF_DBG(dm, DBG_RF_MP,\n\t       \"[kfree] 8822b 2g 0x%X 0x%X pa_bias=%d rfreg_3f=0x%X path=%d\\n\",\n\t       PPG_PABIAS_2GA_22B, PPG_PABIAS_2GB_22B,\n\t       tx_pa_bias, rf_reg_3f, e_rf_path);\n\n\todm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(10), 0x1);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x0);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, BIT(0), 0x1);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, BIT(1), 0x1);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, (BIT(1) | BIT(0)), 0x3);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);\n\todm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(10), 0x0);\n\n\tRF_DBG(dm, DBG_RF_MP,\n\t       \"[kfree] 8822b 2g tx pa bias rf_0x3f(0x%X) path=%d\\n\",\n\t       odm_get_rf_reg(dm, e_rf_path, RF_0x3f,\n\t\t\t      (BIT(12) | BIT(11) | BIT(10) | BIT(9))),\n\t\t\t      e_rf_path);\n}\n\nvoid phydm_get_pa_bias_offset_8822b(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *power_trim_info = &dm->power_trim_data;\n\n\tu8 pg_pa_bias = 0xff, e_rf_path = 0;\n\ts8 tx_pa_bias[2] = {0};\n\n\todm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22B, &pg_pa_bias, false);\n\n\tif (pg_pa_bias != 0xff) {\n\t\t/*paht a*/\n\t\todm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22B,\n\t\t\t\t\t&pg_pa_bias, false);\n\t\tpg_pa_bias = pg_pa_bias & 0xf;\n\n\t\tif ((pg_pa_bias & BIT(0)) == 0)\n\t\t\ttx_pa_bias[0] = (-1 * (pg_pa_bias >> 1));\n\t\telse\n\t\t\ttx_pa_bias[0] = (pg_pa_bias >> 1);\n\n\t\t/*paht b*/\n\t\todm_efuse_one_byte_read(dm, PPG_PABIAS_2GB_22B,\n\t\t\t\t\t&pg_pa_bias, false);\n\t\tpg_pa_bias = pg_pa_bias & 0xf;\n\n\t\tif ((pg_pa_bias & BIT(0)) == 0)\n\t\t\ttx_pa_bias[1] = (-1 * (pg_pa_bias >> 1));\n\t\telse\n\t\t\ttx_pa_bias[1] = (pg_pa_bias >> 1);\n\n\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t       \"[kfree] 8822b 2g PathA_pa_bias:%d PathB_pa_bias:%d\\n\",\n\t\t       tx_pa_bias[0], tx_pa_bias[1]);\n\n\t\tfor (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++)\n\t\t\tphydm_set_pa_bias_to_rf_8822b(dm, e_rf_path,\n\t\t\t\t\t\t      tx_pa_bias[e_rf_path]);\n\n\t\tpower_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8822b 2g tx pa bias no pg\\n\");\n\t}\n}\n\nvoid phydm_set_kfree_to_rf_8822b(void *dm_void, u8 e_rf_path, u8 data)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));\n\n\todm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);\n\todm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);\n\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,\n\t\t       ((data & 0x1f) >> 1));\n\n\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8822b 0x55[19:14]=0x%X path=%d\\n\",\n\t       odm_get_rf_reg(dm, e_rf_path, RF_0x55,\n\t\t\t      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |\n\t\t\t      BIT(15) | BIT(14))), e_rf_path);\n}\n\nvoid phydm_clear_kfree_to_rf_8822b(void *dm_void, u8 e_rf_path, u8 data)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));\n\n\todm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);\n\todm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);\n\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,\n\t\t       ((data & 0x1f) >> 1));\n\n\todm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 0);\n\todm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 0);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(7), 0);\n\n\tRF_DBG(dm, DBG_RF_MP,\n\t       \"[kfree] 8822b clear power trim 0x55[19:14]=0x%X path=%d\\n\",\n\t       odm_get_rf_reg(dm, e_rf_path, RF_0x55,\n\t\t\t      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |\n\t\t\t      BIT(15) | BIT(14))), e_rf_path);\n}\n\nvoid phydm_get_thermal_trim_offset_8710b(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *power_trim_info = &dm->power_trim_data;\n\n\tu8 pg_therm = 0xff;\n\n\todm_efuse_one_byte_read(dm, 0x0EF, &pg_therm, false);\n\n\tif (pg_therm != 0xff) {\n\t\tpg_therm = pg_therm & 0x1f;\n\t\tif ((pg_therm & BIT(0)) == 0)\n\t\t\tpower_trim_info->thermal = (-1 * (pg_therm >> 1));\n\t\telse\n\t\t\tpower_trim_info->thermal = (pg_therm >> 1);\n\n\t\tpower_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;\n\t}\n\n\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8710b thermal trim flag:0x%02x\\n\",\n\t       power_trim_info->flag);\n\n\tif (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)\n\t\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8710b thermal:%d\\n\",\n\t\t       power_trim_info->thermal);\n}\n\nvoid phydm_get_power_trim_offset_8710b(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *power_trim_info = &dm->power_trim_data;\n\n\tu8 pg_power = 0xff;\n\n\todm_efuse_one_byte_read(dm, 0xEE, &pg_power, false);\n\n\tif (pg_power != 0xff) {\n\t\t/*Path A*/\n\t\todm_efuse_one_byte_read(dm, 0xEE, &pg_power, false);\n\t\tpower_trim_info->bb_gain[0][0] = (pg_power & 0xf);\n\n\t\tpower_trim_info->flag |= KFREE_FLAG_ON_2G;\n\t\tpower_trim_info->flag |= KFREE_FLAG_ON;\n\t}\n\n\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8710b power trim flag:0x%02x\\n\",\n\t       power_trim_info->flag);\n\n\tif (power_trim_info->flag & KFREE_FLAG_ON)\n\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t       \"[kfree] 8710b power_trim_data->bb_gain[0][0]=0x%X\\n\",\n\t\t       power_trim_info->bb_gain[0][0]);\n}\n\nvoid phydm_set_kfree_to_rf_8710b(void *dm_void, u8 e_rf_path, u8 data)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15));\n\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, ((data & 0xf) >> 1));\n\n\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8710b 0x55[19:14]=0x%X path=%d\\n\",\n\t       odm_get_rf_reg(dm, e_rf_path, RF_0x55,\n\t\t\t      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |\n\t\t\t      BIT(15) | BIT(14))), e_rf_path);\n}\n\nvoid phydm_clear_kfree_to_rf_8710b(void *dm_void, u8 e_rf_path, u8 data)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));\n\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,\n\t\t       ((data & 0x1f) >> 1));\n\n\tRF_DBG(dm, DBG_RF_MP,\n\t       \"[kfree] 8710b clear power trim 0x55[19:14]=0x%X path=%d\\n\",\n\t       odm_get_rf_reg(dm, e_rf_path, RF_0x55,\n\t\t\t      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |\n\t\t\t      BIT(15) | BIT(14))), e_rf_path);\n}\n\nvoid phydm_get_thermal_trim_offset_8192f(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *power_trim_info = &dm->power_trim_data;\n\n\tu8 pg_therm = 0xff;\n\n\todm_efuse_one_byte_read(dm, 0x1EF, &pg_therm, false);\n\n\tif (pg_therm != 0xff) {\n\t\tpg_therm = pg_therm & 0x1f;\n\t\tif ((pg_therm & BIT(0)) == 0)\n\t\t\tpower_trim_info->thermal = (-1 * (pg_therm >> 1));\n\t\telse\n\t\t\tpower_trim_info->thermal = (pg_therm >> 1);\n\n\t\tpower_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;\n\t}\n\n\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8192f thermal trim flag:0x%02x\\n\",\n\t       power_trim_info->flag);\n\n\tif (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)\n\t\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8192f thermal:%d\\n\",\n\t\t       power_trim_info->thermal);\n}\n\nvoid phydm_get_power_trim_offset_8192f(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *power_trim_info = &dm->power_trim_data;\n\n\tu8 pg_power1 = 0xff, pg_power2 = 0xff, pg_power3 = 0xff, i, j;\n\n\todm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false); /*CH4-9*/\n\n\tif (pg_power1 != 0xff) {\n\t\t/*Path A*/\n\t\todm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false);\n\t\tpower_trim_info->bb_gain[1][0] = (pg_power1 & 0xf);\n\t\t/*Path B*/\n\t\todm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false);\n\t\tpower_trim_info->bb_gain[1][1] = ((pg_power1 & 0xf0) >> 4);\n\n\t\tpower_trim_info->flag |= KFREE_FLAG_ON_2G;\n\t\tpower_trim_info->flag |= KFREE_FLAG_ON;\n\t}\n\n\todm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false); /*CH1-3*/\n\n\tif (pg_power2 != 0xff) {\n\t\t/*Path A*/\n\t\todm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false);\n\t\tpower_trim_info->bb_gain[0][0] = (pg_power2 & 0xf);\n\t\t/*Path B*/\n\t\todm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false);\n\t\tpower_trim_info->bb_gain[0][1] = ((pg_power2 & 0xf0) >> 4);\n\n\t\tpower_trim_info->flag |= KFREE_FLAG_ON_2G;\n\t\tpower_trim_info->flag |= KFREE_FLAG_ON;\n\t} else {\n\t\tpower_trim_info->bb_gain[0][0] = (pg_power1 & 0xf);\n\t\tpower_trim_info->bb_gain[0][1] = ((pg_power1 & 0xf0) >> 4);\n\t}\n\n\todm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false); /*CH10-14*/\n\n\tif (pg_power3 != 0xff) {\n\t\t/*Path A*/\n\t\todm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false);\n\t\tpower_trim_info->bb_gain[2][0] = (pg_power3 & 0xf);\n\t\t/*Path B*/\n\t\todm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false);\n\t\tpower_trim_info->bb_gain[2][1] = ((pg_power3 & 0xf0) >> 4);\n\n\t\tpower_trim_info->flag |= KFREE_FLAG_ON_2G;\n\t\tpower_trim_info->flag |= KFREE_FLAG_ON;\n\t} else {\n\t\tpower_trim_info->bb_gain[2][0] = (pg_power1 & 0xf);\n\t\tpower_trim_info->bb_gain[2][1] = ((pg_power1 & 0xf0) >> 4);\n\t}\n\n\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8192F power trim flag:0x%02x\\n\",\n\t       power_trim_info->flag);\n\n\tif (!(power_trim_info->flag & KFREE_FLAG_ON))\n\t\treturn;\n\n\tfor (i = 0; i < KFREE_CH_NUM; i++) {\n\t\tfor (j = 0; j < 2; j++)\n\t\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t\t       \"[kfree] 8192F PwrTrim->bb_gain[%d][%d]=0x%X\\n\",\n\t\t\t       i, j, power_trim_info->bb_gain[i][j]);\n\t}\n}\n\nvoid phydm_set_kfree_to_rf_8192f(void *dm_void, u8 e_rf_path, u8 channel_idx,\n\t\t\t\t u8 data)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\t/*power_trim based on 55[19:14]*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);\n\t/*enable 55[14] for 0.5db step*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 1);\n\t/*enter power_trim debug mode*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 1);\n\t/*write enable*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 1);\n\n\tif (e_rf_path == 0) {\n\t\tif (channel_idx == 0) {\n\t\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);\n\t\t\todm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);\n\n\t\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);\n\t\t\todm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);\n\n\t\t} else if (channel_idx == 1) {\n\t\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);\n\t\t\todm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);\n\n\t\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);\n\t\t\todm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);\n\t\t} else if (channel_idx == 2) {\n\t\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);\n\t\t\todm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);\n\n\t\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);\n\t\t\todm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);\n\t\t}\n\t} else if (e_rf_path == 1) {\n\t\tif (channel_idx == 0) {\n\t\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);\n\t\t\todm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);\n\n\t\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);\n\t\t\todm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);\n\t\t} else if (channel_idx == 1) {\n\t\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);\n\t\t\todm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);\n\n\t\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);\n\t\t\todm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);\n\t\t} else if (channel_idx == 2) {\n\t\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);\n\t\t\todm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);\n\n\t\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);\n\t\t\todm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);\n\t\t}\n\t}\n\n\t/*leave power_trim debug mode*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);\n\t/*write disable*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 0);\n\n\tRF_DBG(dm, DBG_RF_MP,\n\t       \"[kfree] 8192F 0x55[19:14]=0x%X path=%d channel=%d\\n\",\n\t       odm_get_rf_reg(dm, e_rf_path, RF_0x55,\n\t\t\t      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |\n\t\t\t      BIT(15) | BIT(14))), e_rf_path, channel_idx);\n}\n\n#if 0\n/*\nvoid phydm_clear_kfree_to_rf_8192f(void *dm_void, u8 e_rf_path, u8 data)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct\t*cali_info = &dm->rf_calibrate_info;\n\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1));\n\n\tRF_DBG(dm, DBG_RF_MP,\n\t\t\"[kfree] 8192F clear power trim 0x55[19:14]=0x%X path=%d\\n\",\n\t\todm_get_rf_reg(dm, e_rf_path, RF_0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),\n\t\te_rf_path\n\t\t);\n}\n*/\n#endif\n\nvoid phydm_get_thermal_trim_offset_8198f(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *power_trim_info = &dm->power_trim_data;\n\n\tu8 pg_therm = 0xff;\n\n\todm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_98F, &pg_therm, false);\n\n\tif (pg_therm != 0xff) {\n\t\tpg_therm = pg_therm & 0x1f;\n\t\tif ((pg_therm & BIT(0)) == 0)\n\t\t\tpower_trim_info->thermal = (-1 * (pg_therm >> 1));\n\t\telse\n\t\t\tpower_trim_info->thermal = (pg_therm >> 1);\n\n\t\tpower_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;\n\t}\n\n\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8198f thermal trim flag:0x%02x\\n\",\n\t       power_trim_info->flag);\n\n\tif (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)\n\t\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8198f thermal:%d\\n\",\n\t\t       power_trim_info->thermal);\n}\n\nvoid phydm_get_power_trim_offset_8198f(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *power_trim_info = &dm->power_trim_data;\n\n\tu8 pg_power = 0xff, i, j;\n\n\todm_efuse_one_byte_read(dm, PPG_2GL_TXAB_98F, &pg_power, false);\n\n\tif (pg_power != 0xff) {\n\t\tpower_trim_info->bb_gain[0][0] = pg_power & 0xf;\n\t\tpower_trim_info->bb_gain[0][1] = (pg_power & 0xf0) >> 4;\n\n\t\todm_efuse_one_byte_read(dm, PPG_2GL_TXCD_98F, &pg_power, false);\n\t\tpower_trim_info->bb_gain[0][2] = pg_power & 0xf;\n\t\tpower_trim_info->bb_gain[0][3] = (pg_power & 0xf0) >> 4;\n\n\t\todm_efuse_one_byte_read(dm, PPG_2GM_TXAB_98F, &pg_power, false);\n\t\tpower_trim_info->bb_gain[1][0] = pg_power & 0xf;\n\t\tpower_trim_info->bb_gain[1][1] = (pg_power & 0xf0) >> 4;\n\n\t\todm_efuse_one_byte_read(dm, PPG_2GM_TXCD_98F, &pg_power, false);\n\t\tpower_trim_info->bb_gain[1][2] = pg_power & 0xf;\n\t\tpower_trim_info->bb_gain[1][3] = (pg_power & 0xf0) >> 4;\n\n\t\todm_efuse_one_byte_read(dm, PPG_2GH_TXAB_98F, &pg_power, false);\n\t\tpower_trim_info->bb_gain[2][0] = pg_power & 0xf;\n\t\tpower_trim_info->bb_gain[2][1] = (pg_power & 0xf0) >> 4;\n\n\t\todm_efuse_one_byte_read(dm, PPG_2GH_TXCD_98F, &pg_power, false);\n\t\tpower_trim_info->bb_gain[2][2] = pg_power & 0xf;\n\t\tpower_trim_info->bb_gain[2][3] = (pg_power & 0xf0) >> 4;\n\n\t\tpower_trim_info->flag =\n\t\t\tpower_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G;\n\t}\n\n\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8198f power trim flag:0x%02x\\n\",\n\t       power_trim_info->flag);\n\n\tif (power_trim_info->flag & KFREE_FLAG_ON) {\n\t\tfor (i = 0; i < KFREE_BAND_NUM; i++) {\n\t\t\tfor (j = 0; j < MAX_RF_PATH; j++) {\n\t\t\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t\t\t       \"[kfree] 8198f pwr_trim->bb_gain[%d][%d]=0x%X\\n\",\n\t\t\t\t       i, j, power_trim_info->bb_gain[i][j]);\n\t\t\t}\n\t\t}\n\t}\n}\n\nvoid phydm_set_kfree_to_rf_8198f(void *dm_void, u8 e_rf_path, u8 data)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *power_trim_info = &dm->power_trim_data;\n\tu32 band, i;\n\ts8 pwr_offset[3];\n\n\tRF_DBG(dm, DBG_RF_MP,\n\t\t   \"[kfree] %s:Set kfree to rf 0x33\\n\", __func__);\n\n\t/*power_trim based on 55[19:14]*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);\n\t/*enable 55[14] for 0.5db step*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 1);\n\t/*enter power_trim debug mode*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);\n\t/*write enable*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 1);\n\n\tfor (i =0; i < 3; i++)\n\t\tpwr_offset[i] = power_trim_info->bb_gain[i][e_rf_path];\n\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[0]);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[0]);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[1]);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[1]);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[2]);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[2]);\n\n\t/*leave power_trim debug mode*/\n\t/*odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);*/\n\t/*write disable*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 0);\n\n}\n\nvoid phydm_clear_kfree_to_rf_8198f(void *dm_void, u8 e_rf_path, u8 data)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tRF_DBG(dm, DBG_RF_MP,\n\t\t   \"[kfree] %s:Clear kfree to rf 0x55\\n\", __func__);\n#if 0\n\t/*power_trim based on 55[19:14]*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);\n\t/*enable 55[14] for 0.5db step*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 1);\n\t/*enter power_trim debug mode*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);\n\t/*write enable*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 1);\n\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);\n\todm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);\n\n\t/*leave power_trim debug mode*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);\n\t/*enable 55[14] for 0.5db step*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 0);\n\t/*write disable*/\n\todm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 0);\n#else\n\n\todm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 1);\n\t/*odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 0);*/\n\n#endif\n\n}\n\nvoid phydm_get_set_thermal_trim_offset_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *power_trim_info = &dm->power_trim_data;\n\n\tu8 pg_therm = 0xff, thermal[2] = {0};\n\n\todm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_22C, &pg_therm, false);\n\n\tif (pg_therm != 0xff) {\n\t\t/*s0*/\n\t\tpg_therm = pg_therm & 0x1f;\n\n\t\tthermal[RF_PATH_A] =\n\t\t\t((pg_therm & 0x1) << 3) | ((pg_therm >> 1) & 0x7);\n\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x43, 0x000f0000, thermal[RF_PATH_A]);\n\n\t\t/*s1*/\n\t\todm_efuse_one_byte_read(dm, PPG_THERMAL_B_OFFSET_22C, &pg_therm, false);\n\n\t\tpg_therm = pg_therm & 0x1f;\n\n\t\tthermal[RF_PATH_B] = ((pg_therm & 0x1) << 3) | ((pg_therm >> 1) & 0x7);\n\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x43, 0x000f0000, thermal[RF_PATH_B]);\n\n\t\tpower_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;\n\n\t}\n\n\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8822c thermal trim flag:0x%02x\\n\",\n\t       power_trim_info->flag);\n\n\tif (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)\n\t\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8822c thermalA:%d thermalB:%d\\n\",\n\t\t\tthermal[RF_PATH_A],\n\t\t\tthermal[RF_PATH_B]);\t\n}\n\nvoid phydm_set_power_trim_offset_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *power_trim_info = &dm->power_trim_data;\n\tu8 e_rf_path;\n\n\tfor (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++)\n\t{\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 1);\n\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x0);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,\n\t\t\tpower_trim_info->bb_gain[0][e_rf_path]);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x1);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,\n\t\t\tpower_trim_info->bb_gain[1][e_rf_path]);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x2);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,\n\t\t\tpower_trim_info->bb_gain[2][e_rf_path]);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x3);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,\n\t\t\tpower_trim_info->bb_gain[2][e_rf_path]);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x4);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,\n\t\t\tpower_trim_info->bb_gain[3][e_rf_path]);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x5);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,\n\t\t\tpower_trim_info->bb_gain[4][e_rf_path]);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x6);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,\n\t\t\tpower_trim_info->bb_gain[5][e_rf_path]);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x7);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,\n\t\t\tpower_trim_info->bb_gain[6][e_rf_path]);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x8);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,\n\t\t\tpower_trim_info->bb_gain[7][e_rf_path]);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x9);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,\n\t\t\tpower_trim_info->bb_gain[3][e_rf_path]);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xa);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,\n\t\t\tpower_trim_info->bb_gain[4][e_rf_path]);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xb);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,\n\t\t\tpower_trim_info->bb_gain[5][e_rf_path]);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xc);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,\n\t\t\tpower_trim_info->bb_gain[6][e_rf_path]);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xd);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,\n\t\t\tpower_trim_info->bb_gain[7][e_rf_path]);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xe);\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,\n\t\t\tpower_trim_info->bb_gain[7][e_rf_path]);\n\n\t\todm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 0);\n\t}\n}\n\nvoid phydm_get_power_trim_offset_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *power_trim_info = &dm->power_trim_data;\n\n\tu8 pg_power = 0xff, i, j;\n\tu8 pg_power1, pg_power2 , pg_power3, pg_power4, pg_power5;\n\n\todm_efuse_one_byte_read(dm, PPG_2GL_TXAB_22C, &pg_power1, false);\n\todm_efuse_one_byte_read(dm, PPG_2GM_TXAB_22C, &pg_power2, false);\n\todm_efuse_one_byte_read(dm, PPG_2GH_TXAB_22C, &pg_power3, false);\n\todm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22C, &pg_power4, false);\n\todm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22C, &pg_power5, false);\n\n\tif (pg_power1 != 0xff || pg_power2 != 0xff || pg_power3 != 0xff ||\n\t\tpg_power4 != 0xff || pg_power5 != 0xff) {\n\t\todm_efuse_one_byte_read(dm, PPG_2GL_TXAB_22C, &pg_power, false);\n\t\tif (pg_power == 0xff)\n\t\t\tpg_power = 0;\n\t\tpower_trim_info->bb_gain[0][0] = pg_power & 0xf;\n\t\tpower_trim_info->bb_gain[0][1] = (pg_power & 0xf0) >> 4;\n\n\t\todm_efuse_one_byte_read(dm, PPG_2GM_TXAB_22C, &pg_power, false);\n\t\tif (pg_power == 0xff)\n\t\t\tpg_power = 0;\n\t\tpower_trim_info->bb_gain[1][0] = pg_power & 0xf;\n\t\tpower_trim_info->bb_gain[1][1] = (pg_power & 0xf0) >> 4;\n\n\t\todm_efuse_one_byte_read(dm, PPG_2GH_TXAB_22C, &pg_power, false);\n\t\tif (pg_power == 0xff)\n\t\t\tpg_power = 0;\n\t\tpower_trim_info->bb_gain[2][0] = pg_power & 0xf;\n\t\tpower_trim_info->bb_gain[2][1] = (pg_power & 0xf0) >> 4;\n\n\t\todm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22C, &pg_power, false);\n\t\tif (pg_power == 0xff)\n\t\t\tpg_power = 0;\n\t\tpower_trim_info->bb_gain[3][0] = pg_power & 0x1f;\n\t\todm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22C, &pg_power, false);\n\t\tif (pg_power == 0xff)\n\t\t\tpg_power = 0;\n\t\tpower_trim_info->bb_gain[3][1] = pg_power & 0x1f;\n\n\t\todm_efuse_one_byte_read(dm, PPG_5GL2_TXA_22C, &pg_power, false);\n\t\tif (pg_power == 0xff)\n\t\t\tpg_power = 0;\n\t\tpower_trim_info->bb_gain[4][0] = pg_power & 0x1f;\n\t\todm_efuse_one_byte_read(dm, PPG_5GL2_TXB_22C, &pg_power, false);\n\t\tif (pg_power == 0xff)\n\t\t\tpg_power = 0;\n\t\tpower_trim_info->bb_gain[4][1] = pg_power & 0x1f;\n\n\t\todm_efuse_one_byte_read(dm, PPG_5GM1_TXA_22C, &pg_power, false);\n\t\tif (pg_power == 0xff)\n\t\t\tpg_power = 0;\n\t\tpower_trim_info->bb_gain[5][0] = pg_power & 0x1f;\n\t\todm_efuse_one_byte_read(dm, PPG_5GM1_TXB_22C, &pg_power, false);\n\t\tif (pg_power == 0xff)\n\t\t\tpg_power = 0;\n\t\tpower_trim_info->bb_gain[5][1] = pg_power & 0x1f;\n\n\t\todm_efuse_one_byte_read(dm, PPG_5GM2_TXA_22C, &pg_power, false);\n\t\tif (pg_power == 0xff)\n\t\t\tpg_power = 0;\n\t\tpower_trim_info->bb_gain[6][0] = pg_power & 0x1f;\n\t\todm_efuse_one_byte_read(dm, PPG_5GM2_TXB_22C, &pg_power, false);\n\t\tif (pg_power == 0xff)\n\t\t\tpg_power = 0;\n\t\tpower_trim_info->bb_gain[6][1] = pg_power & 0x1f;\n\n\t\todm_efuse_one_byte_read(dm, PPG_5GH1_TXA_22C, &pg_power, false);\n\t\tif (pg_power == 0xff)\n\t\t\tpg_power = 0;\n\t\tpower_trim_info->bb_gain[7][0] = pg_power & 0x1f;\n\t\todm_efuse_one_byte_read(dm, PPG_5GH1_TXB_22C, &pg_power, false);\n\t\tif (pg_power == 0xff)\n\t\t\tpg_power = 0;\n\t\tpower_trim_info->bb_gain[7][1] = pg_power & 0x1f;\n\n\t\tpower_trim_info->flag =\n\t\t\tpower_trim_info->flag | KFREE_FLAG_ON |\n\t\t\t\t\t\tKFREE_FLAG_ON_2G |\n\t\t\t\t\t\tKFREE_FLAG_ON_5G;\n\n\t\tphydm_set_power_trim_offset_8822c(dm);\n\t}\n\n\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8822c power trim flag:0x%02x\\n\",\n\t       power_trim_info->flag);\n\n\tif (power_trim_info->flag & KFREE_FLAG_ON) {\n\t\tfor (i = 0; i < KFREE_BAND_NUM; i++) {\n\t\t\tfor (j = 0; j < 2; j++) {\n\t\t\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t\t\t       \"[kfree] 8822c pwr_trim->bb_gain[%d][%d]=0x%X\\n\",\n\t\t\t\t       i, j, power_trim_info->bb_gain[i][j]);\n\t\t\t}\n\t\t}\n\t}\n}\n\nvoid phydm_get_set_pa_bias_offset_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *power_trim_info = &dm->power_trim_data;\n\n\tu8 pg_pa_bias = 0xff;\n\n\tRF_DBG(dm, DBG_RF_MP, \"======>%s\\n\", __func__);\n\n\todm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22C, &pg_pa_bias, false);\n\n\tif (pg_pa_bias != 0xff) {\n\t\t/*2G s0*/\n\t\todm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22C,\n\t\t\t\t\t&pg_pa_bias, false);\n\t\tpg_pa_bias = pg_pa_bias & 0xf;\n\n\t\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 2G s0 pa_bias=0x%x\\n\", pg_pa_bias);\n\n\t\todm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x0000f000, pg_pa_bias);\n\n\t\t/*2G s1*/\n\t\todm_efuse_one_byte_read(dm, PPG_PABIAS_2GB_22C,\n\t\t\t\t\t&pg_pa_bias, false);\n\t\tpg_pa_bias = pg_pa_bias & 0xf;\n\n\t\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 2G s1 pa_bias=0x%x\\n\", pg_pa_bias);\n\n\t\todm_set_rf_reg(dm, RF_PATH_B, 0x60, 0x0000f000, pg_pa_bias);\n\n\t\t/*5G s0*/\n\t\todm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_22C,\n\t\t\t\t\t&pg_pa_bias, false);\n\t\tpg_pa_bias = pg_pa_bias & 0xf;\n\n\t\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 5G s0 pa_bias=0x%x\\n\", pg_pa_bias);\n\n\t\todm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x000f0000, pg_pa_bias);\n\n\t\t/*5G s1*/\n\t\todm_efuse_one_byte_read(dm, PPG_PABIAS_5GB_22C,\n\t\t\t\t\t&pg_pa_bias, false);\n\t\tpg_pa_bias = pg_pa_bias & 0xf;\n\n\t\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 5G s1 pa_bias=0x%x\\n\", pg_pa_bias);\n\n\t\todm_set_rf_reg(dm, RF_PATH_B, 0x60, 0x000f0000, pg_pa_bias);\n\n\t\tpower_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_MP, \"[kfree] 8822c tx pa bias no pg\\n\");\n\t}\n\n}\n\nvoid phydm_do_new_kfree(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_RTL8822C) {\n\t\tphydm_get_set_thermal_trim_offset_8822c(dm);\n\t\tphydm_get_power_trim_offset_8822c(dm);\n\t\tphydm_get_set_pa_bias_offset_8822c(dm);\n\t}\n}\n\n\n\nvoid phydm_set_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_RTL8814A)\n\t\tphydm_set_kfree_to_rf_8814a(dm, e_rf_path, data);\n\n\tif ((dm->support_ic_type & ODM_RTL8821C) &&\n\t    (*dm->band_type == ODM_BAND_2_4G))\n\t\tphydm_set_kfree_to_rf_8821c(dm, e_rf_path, true, data);\n\telse if (dm->support_ic_type & ODM_RTL8821C)\n\t\tphydm_set_kfree_to_rf_8821c(dm, e_rf_path, false, data);\n\n\tif (dm->support_ic_type & ODM_RTL8822B)\n\t\tphydm_set_kfree_to_rf_8822b(dm, e_rf_path, data);\n\n\tif (dm->support_ic_type & ODM_RTL8710B)\n\t\tphydm_set_kfree_to_rf_8710b(dm, e_rf_path, data);\n\n\tif (dm->support_ic_type & ODM_RTL8198F)\n\t\tphydm_set_kfree_to_rf_8198f(dm, e_rf_path, data);\n}\n\nvoid phydm_clear_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_RTL8822B)\n\t\tphydm_clear_kfree_to_rf_8822b(dm, e_rf_path, 1);\n\n\tif (dm->support_ic_type & ODM_RTL8821C)\n\t\tphydm_clear_kfree_to_rf_8821c(dm, e_rf_path, 1);\n\n\tif (dm->support_ic_type & ODM_RTL8198F)\n\t\tphydm_clear_kfree_to_rf_8198f(dm, e_rf_path, 0);\n}\n\nvoid phydm_get_thermal_trim_offset(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tPEFUSE_HAL pEfuseHal = &hal_data->EfuseHal;\n\tu1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];\n\n\tif (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)\n\t\tRF_DBG(dm, DBG_RF_MP, \"[kfree] dump efuse fail !!!\\n\");\n#endif\n\n\tif (dm->support_ic_type & ODM_RTL8821C)\n\t\tphydm_get_thermal_trim_offset_8821c(dm_void);\n\telse if (dm->support_ic_type & ODM_RTL8822B)\n\t\tphydm_get_thermal_trim_offset_8822b(dm_void);\n\telse if (dm->support_ic_type & ODM_RTL8710B)\n\t\tphydm_get_thermal_trim_offset_8710b(dm_void);\n\telse if (dm->support_ic_type & ODM_RTL8192F)\n\t\tphydm_get_thermal_trim_offset_8192f(dm_void);\n\telse if (dm->support_ic_type & ODM_RTL8198F)\n\t\tphydm_get_thermal_trim_offset_8198f(dm_void);\n}\n\nvoid phydm_get_power_trim_offset(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if 0 //(DM_ODM_SUPPORT_TYPE & ODM_WIN)\t// 2017 MH DM Should use the same code.s\n\tvoid\t\t*adapter = dm->adapter;\n\tHAL_DATA_TYPE\t*hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tPEFUSE_HAL\t\tpEfuseHal = &hal_data->EfuseHal;\n\tu1Byte\t\t\teFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];\n\n\tif (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO(adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)\n\t\tRF_DBG(dm, DBG_RF_MP, \"[kfree] dump efuse fail !!!\\n\");\n#endif\n\n\tif (dm->support_ic_type & ODM_RTL8821C)\n\t\tphydm_get_power_trim_offset_8821c(dm_void);\n\telse if (dm->support_ic_type & ODM_RTL8822B)\n\t\tphydm_get_power_trim_offset_8822b(dm_void);\n\telse if (dm->support_ic_type & ODM_RTL8710B)\n\t\tphydm_get_power_trim_offset_8710b(dm_void);\n\telse if (dm->support_ic_type & ODM_RTL8192F)\n\t\tphydm_get_power_trim_offset_8192f(dm_void);\n\telse if (dm->support_ic_type & ODM_RTL8198F)\n\t\tphydm_get_power_trim_offset_8198f(dm_void);\n}\n\nvoid phydm_get_pa_bias_offset(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tPEFUSE_HAL pEfuseHal = &hal_data->EfuseHal;\n\tu1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];\n\n\tif (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)\n\t\tRF_DBG(dm, DBG_RF_MP, \"[kfree] dump efuse fail !!!\\n\");\n#endif\n\n\tif (dm->support_ic_type & ODM_RTL8822B)\n\t\tphydm_get_pa_bias_offset_8822b(dm_void);\n}\n\ns8 phydm_get_thermal_offset(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *power_trim_info = &dm->power_trim_data;\n\n\tif (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)\n\t\treturn power_trim_info->thermal;\n\telse\n\t\treturn 0;\n}\n\nvoid phydm_do_kfree(void *dm_void, u8 channel_to_sw)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_power_trim_data *pwrtrim = &dm->power_trim_data;\n\tu8 channel_idx = 0, rfpath = 0, max_path = 0, kfree_band_num = 0;\n\tu8 i, j;\n\ts8 bb_gain;\n\n\tif (dm->support_ic_type & ODM_RTL8814A)\n\t\tmax_path = 4; /*0~3*/\n\telse if (dm->support_ic_type &\n\t\t (ODM_RTL8812 | ODM_RTL8822B | ODM_RTL8192F)) {\n\t\tmax_path = 2; /*0~1*/\n\t\tkfree_band_num = KFREE_BAND_NUM;\n\t} else if (dm->support_ic_type & ODM_RTL8821C) {\n\t\tmax_path = 1;\n\t\tkfree_band_num = KFREE_BAND_NUM;\n\t} else if (dm->support_ic_type & ODM_RTL8710B) {\n\t\tmax_path = 1;\n\t\tkfree_band_num = 1;\n\t} else if (dm->support_ic_type & ODM_RTL8198F) {\n\t\tmax_path = 4;\n\t\tkfree_band_num = 3;\n\t}\n\n\tif (dm->support_ic_type &\n\t    (ODM_RTL8192F | ODM_RTL8822B | ODM_RTL8821C |\n\t    ODM_RTL8814A | ODM_RTL8710B)) {\n\t\tfor (i = 0; i < kfree_band_num; i++) {\n\t\t\tfor (j = 0; j < max_path; j++)\n\t\t\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t\t\t       \"[kfree] PwrTrim->gain[%d][%d]=0x%X\\n\",\n\t\t\t\t       i, j, pwrtrim->bb_gain[i][j]);\n\t\t}\n\t}\n\tif (*dm->band_type == ODM_BAND_2_4G &&\n\t    pwrtrim->flag & KFREE_FLAG_ON_2G) {\n\t\tif (!(dm->support_ic_type & ODM_RTL8192F)) {\n\t\t\tif (channel_to_sw >= 1 && channel_to_sw <= 14)\n\t\t\t\tchannel_idx = PHYDM_2G;\n\t\t\tfor (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {\n\t\t\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t\t\t       \"[kfree] %s:chnl=%d PATH=%d gain:0x%X\\n\",\n\t\t\t\t       __func__, channel_to_sw, rfpath,\n\t\t\t\t       pwrtrim->bb_gain[channel_idx][rfpath]);\n\t\t\t\tbb_gain = pwrtrim->bb_gain[channel_idx][rfpath];\n\t\t\t\tphydm_set_kfree_to_rf(dm, rfpath, bb_gain);\n\t\t\t}\n\t\t} else if (dm->support_ic_type & ODM_RTL8192F) {\n\t\t\tif (channel_to_sw >= 1 && channel_to_sw <= 3)\n\t\t\t\tchannel_idx = 0;\n\t\t\tif (channel_to_sw >= 4 && channel_to_sw <= 9)\n\t\t\t\tchannel_idx = 1;\n\t\t\tif (channel_to_sw >= 10 && channel_to_sw <= 14)\n\t\t\t\tchannel_idx = 2;\n\t\t\tfor (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {\n\t\t\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t\t\t       \"[kfree] %s:chnl=%d PATH=%d gain:0x%X\\n\",\n\t\t\t\t       __func__, channel_to_sw, rfpath,\n\t\t\t\t       pwrtrim->bb_gain[channel_idx][rfpath]);\n\t\t\t\tbb_gain = pwrtrim->bb_gain[channel_idx][rfpath];\n\t\t\t\tphydm_set_kfree_to_rf_8192f(dm, rfpath,\n\t\t\t\t\t\t\t    channel_idx,\n\t\t\t\t\t\t\t    bb_gain);\n\t\t\t}\n\t\t}\n\t} else if (*dm->band_type == ODM_BAND_5G &&\n\t\t   pwrtrim->flag & KFREE_FLAG_ON_5G) {\n\t\tif (channel_to_sw >= 36 && channel_to_sw <= 48)\n\t\t\tchannel_idx = PHYDM_5GLB1;\n\t\tif (channel_to_sw >= 52 && channel_to_sw <= 64)\n\t\t\tchannel_idx = PHYDM_5GLB2;\n\t\tif (channel_to_sw >= 100 && channel_to_sw <= 120)\n\t\t\tchannel_idx = PHYDM_5GMB1;\n\t\tif (channel_to_sw >= 122 && channel_to_sw <= 144)\n\t\t\tchannel_idx = PHYDM_5GMB2;\n\t\tif (channel_to_sw >= 149 && channel_to_sw <= 177)\n\t\t\tchannel_idx = PHYDM_5GHB;\n\n\t\tfor (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {\n\t\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t\t       \"[kfree] %s: channel=%d PATH=%d bb_gain:0x%X\\n\",\n\t\t\t       __func__, channel_to_sw, rfpath,\n\t\t\t       pwrtrim->bb_gain[channel_idx][rfpath]);\n\t\t\tbb_gain = pwrtrim->bb_gain[channel_idx][rfpath];\n\t\t\tphydm_set_kfree_to_rf(dm, rfpath, bb_gain);\n\t\t}\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_MP, \"[kfree] Set default Register\\n\");\n\t\tif (!(dm->support_ic_type & ODM_RTL8192F)) {\n\t\t\tfor (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {\n\t\t\t\tbb_gain = pwrtrim->bb_gain[channel_idx][rfpath];\n\t\t\t\tphydm_clear_kfree_to_rf(dm, rfpath, bb_gain);\n\t\t\t}\n\t\t}\n#if 0\n\t\t/*else if(dm->support_ic_type & ODM_RTL8192F){\n\t\t\tif (channel_to_sw >= 1 && channel_to_sw <= 3)\n\t\t\t\tchannel_idx = 0;\n\t\t\tif (channel_to_sw >= 4 && channel_to_sw <= 9)\n\t\t\t\tchannel_idx = 1;\n\t\t\tif (channel_to_sw >= 9 && channel_to_sw <= 14)\n\t\t\t\tchannel_idx = 2;\n\t\t\tfor (rfpath = RF_PATH_A;  rfpath < max_path; rfpath++)\n\t\t\t\tphydm_clear_kfree_to_rf_8192f(dm, rfpath, pwrtrim->bb_gain[channel_idx][rfpath]);\n\t\t}*/\n#endif\n\t}\n}\n\nvoid phydm_config_new_kfree(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;\n\n\tif (cali_info->reg_rf_kfree_enable == 2) {\n\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t       \"[kfree] %s: reg_rf_kfree_enable == 2, Disable\\n\",\n\t\t       __func__);\n\t\treturn;\n\t} else if (cali_info->reg_rf_kfree_enable == 1 ||\n\t\t\tcali_info->reg_rf_kfree_enable == 0) {\n\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t       \"[kfree] %s: reg_rf_kfree_enable == true\\n\", __func__);\n\t\n\t\tphydm_do_new_kfree(dm);\n\t}\n}\n\nvoid phydm_config_kfree(void *dm_void, u8 channel_to_sw)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;\n\tstruct odm_power_trim_data *pwrtrim = &dm->power_trim_data;\n\n\tRF_DBG(dm, DBG_RF_MP, \"===>[kfree] phy_ConfigKFree()\\n\");\n\n\tif (cali_info->reg_rf_kfree_enable == 2) {\n\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t       \"[kfree] %s: reg_rf_kfree_enable == 2, Disable\\n\",\n\t\t       __func__);\n\t\treturn;\n\t} else if (cali_info->reg_rf_kfree_enable == 1 ||\n\t\t\tcali_info->reg_rf_kfree_enable == 0) {\n\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t       \"[kfree] %s: reg_rf_kfree_enable == true\\n\", __func__);\n\t\t/*Make sure the targetval is defined*/\n\t\tif (!(pwrtrim->flag & KFREE_FLAG_ON)) {\n\t\t\tRF_DBG(dm, DBG_RF_MP,\n\t\t\t       \"[kfree] %s: efuse is 0xff, KFree not work\\n\",\n\t\t\t       __func__);\n\t\t\treturn;\n\t\t}\n#if 0\n\t\t/*if kfree_table[0] == 0xff, means no Kfree*/\n#endif\n\t\tphydm_do_kfree(dm, channel_to_sw);\n\t}\n\tRF_DBG(dm, DBG_RF_MP, \"<===[kfree] phy_ConfigKFree()\\n\");\n}\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_kfree.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALRF_KFREE_H__\n#define __HALRF_KFREE_H__\n\n#define KFREE_VERSION \"1.0\"\n\n#define KFREE_BAND_NUM 8\n#define KFREE_CH_NUM 3\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))\n\n#define BB_GAIN_NUM 6\n\n#endif\n\n#define KFREE_FLAG_ON BIT(0)\n#define KFREE_FLAG_THERMAL_K_ON BIT(1)\n\n#define KFREE_FLAG_ON_2G BIT(2)\n#define KFREE_FLAG_ON_5G BIT(3)\n\n#define PA_BIAS_FLAG_ON BIT(4)\n\n#define PPG_THERMAL_OFFSET_98F 0x50\n#define PPG_2GM_TXAB_98F 0x51\n#define PPG_2GM_TXCD_98F 0x52\n#define PPG_2GL_TXAB_98F 0x53\n#define PPG_2GL_TXCD_98F 0x54\n#define PPG_2GH_TXAB_98F 0x55\n#define PPG_2GH_TXCD_98F 0x56\n\n#define PPG_THERMAL_OFFSET_21C 0x1EF\n#define PPG_2G_TXAB_21C 0x1EE\n#define PPG_5GL1_TXA_21C 0x1EC\n#define PPG_5GL2_TXA_21C 0x1E8\n#define PPG_5GM1_TXA_21C 0x1E4\n#define PPG_5GM2_TXA_21C 0x1E0\n#define PPG_5GH1_TXA_21C 0x1DC\n\n#define PPG_THERMAL_OFFSET_22B 0x3EF\n#define PPG_2G_TXAB_22B 0x3EE\n#define PPG_2G_TXCD_22B 0x3ED\n#define PPG_5GL1_TXA_22B 0x3EC\n#define PPG_5GL1_TXB_22B 0x3EB\n#define PPG_5GL1_TXC_22B 0x3EA\n#define PPG_5GL1_TXD_22B 0x3E9\n#define PPG_5GL2_TXA_22B 0x3E8\n#define PPG_5GL2_TXB_22B 0x3E7\n#define PPG_5GL2_TXC_22B 0x3E6\n#define PPG_5GL2_TXD_22B 0x3E5\n#define PPG_5GM1_TXA_22B 0x3E4\n#define PPG_5GM1_TXB_22B 0x3E3\n#define PPG_5GM1_TXC_22B 0x3E2\n#define PPG_5GM1_TXD_22B 0x3E1\n#define PPG_5GM2_TXA_22B 0x3E0\n#define PPG_5GM2_TXB_22B 0x3DF\n#define PPG_5GM2_TXC_22B 0x3DE\n#define PPG_5GM2_TXD_22B 0x3DD\n#define PPG_5GH1_TXA_22B 0x3DC\n#define PPG_5GH1_TXB_22B 0x3DB\n#define PPG_5GH1_TXC_22B 0x3DA\n#define PPG_5GH1_TXD_22B 0x3D9\n\n#define PPG_PABIAS_2GA_22B 0x3D5\n#define PPG_PABIAS_2GB_22B 0x3D6\n\n#define PPG_THERMAL_A_OFFSET_22C 0x1ef\n#define PPG_THERMAL_B_OFFSET_22C 0x1b0\n#define PPG_2GL_TXAB_22C 0x1d4\n#define PPG_2GM_TXAB_22C 0x1ee\n#define PPG_2GH_TXAB_22C 0x1d2\n#define PPG_5GL1_TXA_22C 0x1ec\n#define PPG_5GL1_TXB_22C 0x1eb\n#define PPG_5GL2_TXA_22C 0x1e8\n#define PPG_5GL2_TXB_22C 0x1e7\n#define PPG_5GM1_TXA_22C 0x1e4\n#define PPG_5GM1_TXB_22C 0x1e3\n#define PPG_5GM2_TXA_22C 0x1e0\n#define PPG_5GM2_TXB_22C 0x1df\n#define PPG_5GH1_TXA_22C 0x1dc\n#define PPG_5GH1_TXB_22C 0x1db\n\n#define PPG_PABIAS_2GA_22C 0x1d6\n#define PPG_PABIAS_2GB_22C 0x1d5\n#define PPG_PABIAS_5GA_22C 0x1d8\n#define PPG_PABIAS_5GB_22C 0x1d7\n\nstruct odm_power_trim_data {\n\tu8 flag;\n\tu8 pa_bias_flag;\n\ts8 bb_gain[KFREE_BAND_NUM][MAX_RF_PATH];\n\ts8 thermal;\n};\n\nenum phydm_kfree_channeltosw {\n\tPHYDM_2G = 0,\n\tPHYDM_5GLB1 = 1,\n\tPHYDM_5GLB2 = 2,\n\tPHYDM_5GMB1 = 3,\n\tPHYDM_5GMB2 = 4,\n\tPHYDM_5GHB = 5,\n};\n\nvoid phydm_get_thermal_trim_offset(void *dm_void);\n\nvoid phydm_get_power_trim_offset(void *dm_void);\n\nvoid phydm_get_pa_bias_offset(void *dm_void);\n\ns8 phydm_get_thermal_offset(void *dm_void);\n\nvoid phydm_clear_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data);\n\nvoid phydm_config_new_kfree(void *dm_void);\n\nvoid phydm_config_kfree(void *dm_void, u8 channel_to_sw);\n\n#endif /*__HALRF_KFREE_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_powertracking.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n * ************************************************************\n */\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\nboolean\nodm_check_power_status(void *dm_void)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tPADAPTER *adapter = dm->adapter;\n\n\tRT_RF_POWER_STATE rt_state;\n\tMGNT_INFO *mgnt_info = &((PADAPTER)adapter)->MgntInfo;\n\n\t/* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */\n\tif (mgnt_info->init_adpt_in_progress == true) {\n\t\tRF_DBG(dm, DBG_RF_INIT,\n\t\t       \"check_pow_status Return true, due to initadapter\\n\");\n\t\treturn true;\n\t}\n\n\t/*\n\t *\t2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.\n\t */\n\t((PADAPTER)adapter)->HalFunc.GetHwRegHandler((PADAPTER)adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state));\n\tif (((PADAPTER)adapter)->bDriverStopped || ((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) {\n\t\tRF_DBG(dm, DBG_RF_INIT,\n\t\t       \"check_pow_status Return false, due to %d/%d/%d\\n\",\n\t\t       ((PADAPTER)adapter)->bDriverStopped,\n\t\t       ((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep,\n\t\t       rt_state);\n\t\treturn false;\n\t}\n#endif\n\treturn true;\n}\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\nvoid halrf_update_pwr_track(void *dm_void, u8 rate)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tu8 path_idx = 0;\n#endif\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"Pwr Track Get rate=0x%x\\n\", rate);\n\n\tdm->tx_rate = rate;\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#if DEV_BUS_TYPE == RT_PCI_INTERFACE\n#if USE_WORKITEM\n\todm_schedule_work_item(&dm->ra_rpt_workitem);\n#else\n\tif (dm->support_ic_type == ODM_RTL8821) {\n#if (RTL8821A_SUPPORT == 1)\n\t\todm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);\n#endif\n\t} else if (dm->support_ic_type == ODM_RTL8812) {\n\t\tfor (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8812A; path_idx++) {\n#if (RTL8812A_SUPPORT == 1)\n\t\t\todm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, path_idx, 0);\n#endif\n\t\t}\n\t} else if (dm->support_ic_type == ODM_RTL8723B) {\n#if (RTL8723B_SUPPORT == 1)\n\t\todm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);\n#endif\n\t} else if (dm->support_ic_type == ODM_RTL8192E) {\n\t\tfor (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8192E; path_idx++) {\n#if (RTL8192E_SUPPORT == 1)\n\t\t\todm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, path_idx, 0);\n#endif\n\t\t}\n\t} else if (dm->support_ic_type == ODM_RTL8188E) {\n#if (RTL8188E_SUPPORT == 1)\n\t\todm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);\n#endif\n\t}\n#endif\n#else\n\todm_schedule_work_item(&dm->ra_rpt_workitem);\n#endif\n#endif\n}\n\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid halrf_update_init_rate_work_item_callback(\n\tvoid *context)\n{\n\tvoid *adapter = (void *)context;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\tu8 p = 0;\n\n\tif (dm->support_ic_type == ODM_RTL8821) {\n#if (RTL8821A_SUPPORT == 1)\n\t\todm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);\n#endif\n\t} else if (dm->support_ic_type == ODM_RTL8812) {\n#if (RTL8812A_SUPPORT == 1)\n\t\t/*Don't know how to include &c*/\n\t\tfor (p = RF_PATH_A; p < MAX_PATH_NUM_8812A; p++)\n\t\t\todm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, p, 0);\n#endif\n\t} else if (dm->support_ic_type == ODM_RTL8723B) {\n#if (RTL8723B_SUPPORT == 1)\n\t\todm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);\n#endif\n\t} else if (dm->support_ic_type == ODM_RTL8192E) {\n#if (RTL8192E_SUPPORT == 1)\n\t\t/*Don't know how to include &c*/\n\t\tfor (p = RF_PATH_A; p < MAX_PATH_NUM_8192E; p++)\n\t\t\todm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, p, 0);\n#endif\n\t} else if (dm->support_ic_type == ODM_RTL8188E) {\n#if (RTL8188E_SUPPORT == 1)\n\t\todm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);\n#endif\n\t}\n}\n#endif\n\nvoid halrf_set_pwr_track(void *dm_void, u8 enable)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &(dm->rf_table);\n\tstruct txpwrtrack_cfg c;\n\tu8 i;\n\n\tconfigure_txpower_track(dm, &c);\n\tif (enable)\n\t\trf->rf_supportability = rf->rf_supportability | HAL_RF_TX_PWR_TRACK;\n\telse {\n\t\trf->rf_supportability = rf->rf_supportability & ~HAL_RF_TX_PWR_TRACK;\n\t\todm_clear_txpowertracking_state(dm);\n\t\tfor (i = 0; i < c.rf_path_count; i++)\n\t\t\t(*c.odm_tx_pwr_track_set_pwr)(dm, CLEAN_MODE, i, 0);\n\t}\n\n\t/*halrf_do_tssi(dm);*/\n}\n\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_powertracking.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALRF_POWER_TRACKING_H__\n#define __HALRF_POWER_TRACKING_H__\n\nboolean\nodm_check_power_status(void *dm_void);\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\nvoid halrf_update_pwr_track(void *dm_void, u8 rate);\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid halrf_update_init_rate_work_item_callback(\n\tvoid *context);\n#endif\n\nvoid halrf_set_pwr_track(void *dm_void, u8 enable);\n\n#endif /*#ifndef __HALRF_POWERTRACKING_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_powertracking_ap.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n/* ************************************************************\n * include files\n * ************************************************************ */\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#if !defined(_OUTSRC_COEXIST)\n/* ************************************************************\n * Global var\n * ************************************************************ */\n\n\nu32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D] = {\n\t0x0b40002d, /* 0,  -15.0dB */\n\t0x0c000030, /* 1,  -14.5dB */\n\t0x0cc00033, /* 2,  -14.0dB */\n\t0x0d800036, /* 3,  -13.5dB */\n\t0x0e400039, /* 4,  -13.0dB */\n\t0x0f00003c, /* 5,  -12.5dB */\n\t0x10000040, /* 6,  -12.0dB */\n\t0x11000044, /* 7,  -11.5dB */\n\t0x12000048, /* 8,  -11.0dB */\n\t0x1300004c, /* 9,  -10.5dB */\n\t0x14400051, /* 10, -10.0dB */\n\t0x15800056, /* 11, -9.5dB */\n\t0x16c0005b, /* 12, -9.0dB */\n\t0x18000060, /* 13, -8.5dB */\n\t0x19800066, /* 14, -8.0dB */\n\t0x1b00006c, /* 15, -7.5dB */\n\t0x1c800072, /* 16, -7.0dB */\n\t0x1e400079, /* 17, -6.5dB */\n\t0x20000080, /* 18, -6.0dB */\n\t0x22000088, /* 19, -5.5dB */\n\t0x24000090, /* 20, -5.0dB */\n\t0x26000098, /* 21, -4.5dB */\n\t0x288000a2, /* 22, -4.0dB */\n\t0x2ac000ab, /* 23, -3.5dB */\n\t0x2d4000b5, /* 24, -3.0dB */\n\t0x300000c0, /* 25, -2.5dB */\n\t0x32c000cb, /* 26, -2.0dB */\n\t0x35c000d7, /* 27, -1.5dB */\n\t0x390000e4, /* 28, -1.0dB */\n\t0x3c8000f2, /* 29, -0.5dB */\n\t0x40000100, /* 30, +0dB */\n\t0x43c0010f, /* 31, +0.5dB */\n\t0x47c0011f, /* 32, +1.0dB */\n\t0x4c000130, /* 33, +1.5dB */\n\t0x50800142, /* 34, +2.0dB */\n\t0x55400155, /* 35, +2.5dB */\n\t0x5a400169, /* 36, +3.0dB */\n\t0x5fc0017f, /* 37, +3.5dB */\n\t0x65400195, /* 38, +4.0dB */\n\t0x6b8001ae, /* 39, +4.5dB */\n\t0x71c001c7, /* 40, +5.0dB */\n\t0x788001e2, /* 41, +5.5dB */\n\t0x7f8001fe  /* 42, +6.0dB */\n};\n\nu8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {\n\t{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},\t/* 0, -16.0dB */\n\t{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},\t/* 1, -15.5dB */\n\t{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},\t/* 2, -15.0dB */\n\t{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},\t/* 3, -14.5dB */\n\t{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},\t/* 4, -14.0dB */\n\t{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},\t/* 5, -13.5dB */\n\t{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},\t/* 6, -13.0dB */\n\t{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},\t/* 7, -12.5dB */\n\t{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},\t/* 8, -12.0dB */\n\t{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},\t/* 9, -11.5dB */\n\t{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},\t/* 10, -11.0dB */\n\t{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},\t/* 11, -10.5dB */\n\t{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},\t/* 12, -10.0dB */\n\t{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},\t/* 13, -9.5dB */\n\t{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},\t/* 14, -9.0dB */\n\t{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},\t/* 15, -8.5dB */\n\t{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},\t/* 16, -8.0dB */\n\t{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},\t/* 17, -7.5dB */\n\t{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},\t/* 18, -7.0dB */\n\t{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},\t/* 19, -6.5dB */\n\t{0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02},\t/* 20, -6.0dB */\n\t{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},\t/* 21, -5.5dB */\n\t{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},\t/* 22, -5.0dB */\n\t{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},\t/* 23, -4.5dB */\n\t{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},\t/* 24, -4.0dB */\n\t{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},\t/* 25, -3.5dB */\n\t{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},\t/* 26, -3.0dB */\n\t{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},\t/* 27, -2.5dB */\n\t{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},\t/* 28, -2.0dB */\n\t{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},\t/* 29, -1.5dB */\n\t{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},\t/* 30, -1.0dB */\n\t{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},\t/* 31, -0.5dB */\n\t{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}\t/* 32, +0dB */\n};\n\n\nu8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {\n\t{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},\t/* 0, -16.0dB */\n\t{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 1, -15.5dB */\n\t{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 2, -15.0dB */\n\t{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 3, -14.5dB */\n\t{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 4, -14.0dB */\n\t{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},\t/* 5, -13.5dB */\n\t{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},\t/* 6, -13.0dB */\n\t{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},\t/* 7, -12.5dB */\n\t{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},\t/* 8, -12.0dB */\n\t{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},\t/* 9, -11.5dB */\n\t{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},\t/* 10, -11.0dB */\n\t{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},\t/* 11, -10.5dB */\n\t{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},\t/* 12, -10.0dB */\n\t{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},\t/* 13, -9.5dB */\n\t{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},\t/* 14, -9.0dB */\n\t{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},\t/* 15, -8.5dB */\n\t{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},\t/* 16, -8.0dB */\n\t{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},\t/* 17, -7.5dB */\n\t{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},\t/* 18, -7.0dB */\n\t{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},\t/* 19, -6.5dB */\n\t{0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},\t/* 20, -6.0dB */\n\t{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},\t/* 21, -5.5dB */\n\t{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},\t/* 22, -5.0dB */\n\t{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},\t/* 23, -4.5dB */\n\t{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},\t/* 24, -4.0dB */\n\t{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},\t/* 25, -3.5dB */\n\t{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},\t/* 26, -3.0dB */\n\t{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},\t/* 27, -2.5dB */\n\t{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},\t/* 28, -2.0dB */\n\t{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},\t/* 29, -1.5dB */\n\t{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},\t/* 30, -1.0dB */\n\t{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},\t/* 31, -0.5dB */\n\t{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}\t/* 32, +0dB */\n};\n\nu32 ofdm_swing_table[OFDM_TABLE_SIZE_92D] = {\n\t0x0b40002d, /* 0,  -15.0dB */\n\t0x0c000030, /* 1,  -14.5dB */\n\t0x0cc00033, /* 2,  -14.0dB */\n\t0x0d800036, /* 3,  -13.5dB */\n\t0x0e400039, /* 4,  -13.0dB */\n\t0x0f00003c, /* 5,  -12.5dB */\n\t0x10000040, /* 6,  -12.0dB */\n\t0x11000044, /* 7,  -11.5dB */\n\t0x12000048, /* 8,  -11.0dB */\n\t0x1300004c, /* 9,  -10.5dB */\n\t0x14400051, /* 10, -10.0dB */\n\t0x15800056, /* 11, -9.5dB */\n\t0x16c0005b, /* 12, -9.0dB */\n\t0x18000060, /* 13, -8.5dB */\n\t0x19800066, /* 14, -8.0dB */\n\t0x1b00006c, /* 15, -7.5dB */\n\t0x1c800072, /* 16, -7.0dB */\n\t0x1e400079, /* 17, -6.5dB */\n\t0x20000080, /* 18, -6.0dB */\n\t0x22000088, /* 19, -5.5dB */\n\t0x24000090, /* 20, -5.0dB */\n\t0x26000098, /* 21, -4.5dB */\n\t0x288000a2, /* 22, -4.0dB */\n\t0x2ac000ab, /* 23, -3.5dB */\n\t0x2d4000b5, /* 24, -3.0dB */\n\t0x300000c0, /* 25, -2.5dB */\n\t0x32c000cb, /* 26, -2.0dB */\n\t0x35c000d7, /* 27, -1.5dB */\n\t0x390000e4, /* 28, -1.0dB */\n\t0x3c8000f2, /* 29, -0.5dB */\n\t0x40000100, /* 30, +0dB */\n\t0x43c0010f, /* 31, +0.5dB */\n\t0x47c0011f, /* 32, +1.0dB */\n\t0x4c000130, /* 33, +1.5dB */\n\t0x50800142, /* 34, +2.0dB */\n\t0x55400155, /* 35, +2.5dB */\n\t0x5a400169, /* 36, +3.0dB */\n\t0x5fc0017f, /* 37, +3.5dB */\n\t0x65400195, /* 38, +4.0dB */\n\t0x6b8001ae, /* 39, +4.5dB */\n\t0x71c001c7, /* 40, +5.0dB */\n\t0x788001e2, /* 41, +5.5dB */\n\t0x7f8001fe  /* 42, +6.0dB */\n};\n\n\nu8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {\n\t{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},\t/* 0, -16.0dB */\n\t{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},\t/* 1, -15.5dB */\n\t{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},\t/* 2, -15.0dB */\n\t{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},\t/* 3, -14.5dB */\n\t{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},\t/* 4, -14.0dB */\n\t{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},\t/* 5, -13.5dB */\n\t{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},\t/* 6, -13.0dB */\n\t{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},\t/* 7, -12.5dB */\n\t{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},\t/* 8, -12.0dB */\n\t{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},\t/* 9, -11.5dB */\n\t{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},\t/* 10, -11.0dB */\n\t{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},\t/* 11, -10.5dB */\n\t{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},\t/* 12, -10.0dB */\n\t{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},\t/* 13, -9.5dB */\n\t{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},\t/* 14, -9.0dB */\n\t{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},\t/* 15, -8.5dB */\n\t{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},\t/* 16, -8.0dB */\n\t{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},\t/* 17, -7.5dB */\n\t{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},\t/* 18, -7.0dB */\n\t{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},\t/* 19, -6.5dB */\n\t{0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02},\t/* 20, -6.0dB */\n\t{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},\t/* 21, -5.5dB */\n\t{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},\t/* 22, -5.0dB */\n\t{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},\t/* 23, -4.5dB */\n\t{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},\t/* 24, -4.0dB */\n\t{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},\t/* 25, -3.5dB */\n\t{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},\t/* 26, -3.0dB */\n\t{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},\t/* 27, -2.5dB */\n\t{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},\t/* 28, -2.0dB */\n\t{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},\t/* 29, -1.5dB */\n\t{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},\t/* 30, -1.0dB */\n\t{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},\t/* 31, -0.5dB */\n\t{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}\t/* 32, +0dB */\n};\n\n\nu8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {\n\t{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},\t/* 0, -16.0dB */\n\t{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 1, -15.5dB */\n\t{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 2, -15.0dB */\n\t{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 3, -14.5dB */\n\t{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 4, -14.0dB */\n\t{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},\t/* 5, -13.5dB */\n\t{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},\t/* 6, -13.0dB */\n\t{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},\t/* 7, -12.5dB */\n\t{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},\t/* 8, -12.0dB */\n\t{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},\t/* 9, -11.5dB */\n\t{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},\t/* 10, -11.0dB */\n\t{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},\t/* 11, -10.5dB */\n\t{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},\t/* 12, -10.0dB */\n\t{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},\t/* 13, -9.5dB */\n\t{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},\t/* 14, -9.0dB */\n\t{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},\t/* 15, -8.5dB */\n\t{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},\t/* 16, -8.0dB */\n\t{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},\t/* 17, -7.5dB */\n\t{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},\t/* 18, -7.0dB */\n\t{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},\t/* 19, -6.5dB */\n\t{0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},\t/* 20, -6.0dB */\n\t{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},\t/* 21, -5.5dB */\n\t{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},\t/* 22, -5.0dB */\n\t{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},\t/* 23, -4.5dB */\n\t{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},\t/* 24, -4.0dB */\n\t{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},\t/* 25, -3.5dB */\n\t{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},\t/* 26, -3.0dB */\n\t{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},\t/* 27, -2.5dB */\n\t{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},\t/* 28, -2.0dB */\n\t{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},\t/* 29, -1.5dB */\n\t{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},\t/* 30, -1.0dB */\n\t{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},\t/* 31, -0.5dB */\n\t{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}\t/* 32, +0dB */\n};\n\nu8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {\n\t{0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 0  -16dB */\n\t{0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 1  -15.5dB */\n\t{0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 2  -15dB */\n\t{0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 3  -14.5dB */\n\t{0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 4  -14dB */\n\t{0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 5  -13.5dB */\n\t{0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 6  -13dB */\n\t{0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 7  -12.5dB */\n\t{0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 8  -12dB */\n\t{0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 9  -11.5dB */\n\t{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 10  -11dB */\n\t{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 11  -10.5dB */\n\t{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 12  -10dB */\n\t{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 13  -9.5dB */\n\t{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 14  -9dB */\n\t{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 15  -8.5dB */\n\t{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 16  -8dB */\n\t{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 17  -7.5dB */\n\t{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 18  -7dB */\n\t{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 19  -6.5dB */\n\t{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}      /* 20  -6dB */\n};\n\n\nu8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {\n\t{0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 0  -16dB */\n\t{0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 1  -15.5dB */\n\t{0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 2  -15dB */\n\t{0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 3  -14.5dB */\n\t{0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 4  -14dB */\n\t{0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 5  -13.5dB */\n\t{0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 6  -13dB */\n\t{0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 7  -12.5dB */\n\t{0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 8  -12dB */\n\t{0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 9  -11.5dB */\n\t{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 10  -11dB */\n\t{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 11  -10.5dB */\n\t{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 12  -10dB */\n\t{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 13  -9.5dB */\n\t{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 14  -9dB */\n\t{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 15  -8.5dB */\n\t{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 16  -8dB */\n\t{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 17  -7.5dB */\n\t{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 18  -7dB */\n\t{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 19  -6.5dB */\n\t{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}      /* 20  -6dB */\n};\n\n\nu8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {\n\t{0x44,\t 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/\n\t{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/\n\t{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/\n\t{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\t    /*-14.5dB*/\n\t{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/\n\t{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/\n\t{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/\n\t{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/\n\t{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/\n\t{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/\n\t{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/\n\t{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/\n\t{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/\n\t{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/\n\t{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/\n\t{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/\n\t{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/\n\t{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/\n\t{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/\n\t{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/\n\t{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/\n};\n\n/* Winnita ADD 20171113 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/\nu32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {\n\t0x0CD,\t\t\t /*0 ,    -20dB*/\n\t0x0D9,\n\t0x0E6,\n\t0x0F3,\n\t0x102,\n\t0x111,\n\t0x121,\n\t0x132,\n\t0x144,\n\t0x158,\n\t0x16C,\n\t0x182,\n\t0x198,\n\t0x1B1,\n\t0x1CA,\n\t0x1E5,\n\t0x202,\n\t0x221,\n\t0x241,\n\t0x263,\t\t/*19*/\n\t0x287,\t\t/*20*/\n\t0x2AE,\t\t/*21*/\n\t0x2D6,\t\t/*22*/\n\t0x301,\t\t/*23*/\n\t0x32F,\t\t/*24*/\n\t0x35F,\t\t/*25*/\n\t0x392,\t\t/*26*/\n\t0x3C9,\t\t/*27*/\n\t0x402,\t\t/*28*/\n\t0x43F,\t\t/*29*/\n\t0x47F,\t\t/*30*/\n\t0x4C3,\t\t/*31*/\n\t0x50C,\t\t/*32*/\n\t0x558,\t\t/*33*/\n\t0x5A9,\t\t/*34*/\n\t0x5FF,\t\t/*35*/\n\t0x65A,\t\t/*36*/\n\t0x6BA,\n\t0x720,\n\t0x78C,\n\t0x7FF,\n};\n\n\n#if 0\nu32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E] = {\n\t/* Index0   6  dB */ 0x7fc001ff,\n\t/* Index1   5.7dB */ 0x7b4001ed,\n\t/* Index2   5.4dB */ 0x774001dd,\n\t/* Index3   5.1dB */ 0x734001cd,\n\t/* Index4   4.8dB */ 0x6f4001bd,\n\t/* Index5   4.5dB */ 0x6b8001ae,\n\t/* Index6   4.2dB */ 0x67c0019f,\n\t/* Index7   3.9dB */ 0x64400191,\n\t/* Index8   3.6dB */ 0x60c00183,\n\t/* Index9   3.3dB */ 0x5d800176,\n\t/* Index10  3  dB */ 0x5a80016a,\n\t/* Index11  2.7dB */ 0x5740015d,\n\t/* Index12  2.4dB */ 0x54400151,\n\t/* Index13  2.1dB */ 0x51800146,\n\t/* Index14  1.8dB */ 0x4ec0013b,\n\t/* Index15  1.5dB */ 0x4c000130,\n\t/* Index16  1.2dB */ 0x49800126,\n\t/* Index17  0.9dB */ 0x4700011c,\n\t/* Index18  0.6dB */ 0x44800112,\n\t/* Index19  0.3dB */ 0x42000108,\n\t/* Index20  0  dB */ 0x40000100, /* 20 This is OFDM base index */\n\t/* Index21 -0.3dB */ 0x3dc000f7,\n\t/* Index22 -0.6dB */ 0x3bc000ef,\n\t/* Index23 -0.9dB */ 0x39c000e7,\n\t/* Index24 -1.2dB */ 0x37c000df,\n\t/* Index25 -1.5dB */ 0x35c000d7,\n\t/* Index26 -1.8dB */ 0x340000d0,\n\t/* Index27 -2.1dB */ 0x324000c9,\n\t/* Index28 -2.4dB */ 0x308000c2,\n\t/* Index29 -2.7dB */ 0x2f0000bc,\n\t/* Index30 -3  dB */ 0x2d4000b5,\n\t/* Index31 -3.3dB */ 0x2bc000af,\n\t/* Index32 -3.6dB */ 0x2a4000a9,\n\t/* Index33 -3.9dB */ 0x28c000a3,\n\t/* Index34 -4.2dB */ 0x2780009e,\n\t/* Index35 -4.5dB */ 0x26000098,\n\t/* Index36 -4.8dB */ 0x24c00093,\n\t/* Index37 -5.1dB */ 0x2380008e,\n\t/* Index38 -5.4dB */ 0x22400089,\n\t/* Index39 -5.7dB */ 0x21400085,\n\t/* Index40 -6  dB */ 0x20000080,\n\t/* Index41 -6.3dB */ 0x1f00007c,\n\t/* Index42 -6.6dB */ 0x1e000078,\n\t/* Index43 -6.9dB */ 0x1d000074,\n\t/* Index44 -7.2dB */ 0x1c000070,\n\t/* Index45 -7.5dB */ 0x1b00006c,\n\t/* Index46 -7.8dB */ 0x1a000068,\n\t/* Index47 -8.1dB */ 0x19400065,\n\t/* Index48 -8.4dB */ 0x18400061,\n\t/* Index49 -8.7dB */ 0x1780005e,\n\t/* Index50 -9  dB */ 0x16c0005b,\n\t/* Index51 -9.3dB */ 0x16000058,\n\t/* Index52 -9.6dB */ 0x15400055,\n\t/* Index53 -9.9dB */ 0x14800052\n};\nu8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8] = {\n\t/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x1C, 0x12, 0x08, 0x04},\n\t/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x1B, 0x11, 0x08, 0x04},\n\t/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x1A, 0x11, 0x07, 0x04},\n\t/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x19, 0x10, 0x07, 0x04},\n\t/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x18, 0x10, 0x07, 0x03},\n\t/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x18, 0x0F, 0x07, 0x03},\n\t/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x17, 0x0F, 0x06, 0x03},\n\t/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x16, 0x0E, 0x06, 0x03},\n\t/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x15, 0x0E, 0x06, 0x03},\n\t/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x14, 0x0D, 0x06, 0x03},\n\t/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x14, 0x0D, 0x06, 0x03},\n\t/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x13, 0x0C, 0x05, 0x03},\n\t/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x12, 0x0C, 0x05, 0x03},\n\t/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x12, 0x0B, 0x05, 0x03},\n\t/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x11, 0x0B, 0x05, 0x02},\n\t/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x11, 0x0B, 0x05, 0x02},\n\t/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x10, 0x0A, 0x05, 0x02},\n\t/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x10, 0x0A, 0x04, 0x02},\n\t/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x0F, 0x0A, 0x04, 0x02},\n\t/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x0E, 0x09, 0x04, 0x02},\n\t/* Index20  -6.0dB */    {0x1B, 0x1A, 0x17, 0x13, 0x0E, 0x09, 0x04, 0x02}, /* 20 This is CCK base index */\n\t/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x0E, 0x09, 0x04, 0x02},\n\t/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x0D, 0x08, 0x04, 0x02},\n\t/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x0D, 0x08, 0x04, 0x02},\n\t/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x0C, 0x08, 0x03, 0x02},\n\t/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x0C, 0x08, 0x03, 0x02},\n\t/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x0B, 0x07, 0x03, 0x02},\n\t/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x0B, 0x07, 0x03, 0x02},\n\t/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x0B, 0x07, 0x03, 0x02},\n\t/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x0A, 0x07, 0x03, 0x01},\n\t/* Index30  -9.0dB */    {0x13, 0x12, 0x10, 0x0D, 0x0A, 0x06, 0x03, 0x01}, /* 30 This is hp CCK base index */\n\t/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x0A, 0x06, 0x03, 0x01},\n\t/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x09, 0x06, 0x03, 0x01},\n\t/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x09, 0x06, 0x03, 0x01},\n\t/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x09, 0x06, 0x02, 0x01},\n\t/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x08, 0x05, 0x02, 0x01},\n\t/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x08, 0x05, 0x02, 0x01},\n\t/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x08, 0x05, 0x02, 0x01},\n\t/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},\n\t/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},\n\t/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},\n\t/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},\n\t/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},\n\t/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x06, 0x04, 0x02, 0x01},\n\t/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},\n\t/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},\n\t/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},\n\t/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x06, 0x04, 0x02, 0x01},\n\t/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},\n\t/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},\n\t/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},\n\t/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},\n\t/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},\n\t/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}\n};\nu8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = {\n\t/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x00, 0x00, 0x00, 0x00},\n\t/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x00, 0x00, 0x00, 0x00},\n\t/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x00, 0x00, 0x00, 0x00},\n\t/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x00, 0x00, 0x00, 0x00},\n\t/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x00, 0x00, 0x00, 0x00},\n\t/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x00, 0x00, 0x00, 0x00},\n\t/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x00, 0x00, 0x00, 0x00},\n\t/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x00, 0x00, 0x00, 0x00},\n\t/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x00, 0x00, 0x00, 0x00},\n\t/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x00, 0x00, 0x00, 0x00},\n\t/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x00, 0x00, 0x00, 0x00},\n\t/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x00, 0x00, 0x00, 0x00},\n\t/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x00, 0x00, 0x00, 0x00},\n\t/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x00, 0x00, 0x00, 0x00},\n\t/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x00},\n\t/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x00, 0x00, 0x00, 0x00},\n\t/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x00, 0x00, 0x00, 0x00},\n\t/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x00, 0x00, 0x00, 0x00},\n\t/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x00, 0x00, 0x00, 0x00},\n\t/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x00, 0x00, 0x00, 0x00},\n\t/* Index20  -6  dB */     {0x1B, 0x1A, 0x17, 0x13, 0x00, 0x00, 0x00, 0x00},\n\t/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00},\n\t/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x00, 0x00, 0x00, 0x00},\n\t/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x00, 0x00, 0x00, 0x00},\n\t/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x00, 0x00, 0x00, 0x00},\n\t/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x00, 0x00, 0x00, 0x00},\n\t/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x00, 0x00, 0x00, 0x00},\n\t/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x00, 0x00, 0x00, 0x00},\n\t/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},\n\t/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},\n\t/* Index30  -9  dB */    {0x13, 0x12, 0x10, 0x0D, 0x00, 0x00, 0x00, 0x00},\n\t/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},\n\t/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},\n\t/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x00, 0x00, 0x00, 0x00},\n\t/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00},\n\t/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x00, 0x00, 0x00, 0x00},\n\t/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x00, 0x00, 0x00, 0x00},\n\t/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x00, 0x00, 0x00, 0x00},\n\t/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},\n\t/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},\n\t/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},\n\t/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},\n\t/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},\n\t/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x00, 0x00, 0x00, 0x00},\n\t/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},\n\t/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},\n\t/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x00, 0x00, 0x00, 0x00},\n\t/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},\n\t/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},\n\t/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},\n\t/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},\n\t/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},\n\t/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},\n\t/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00}\n};\n#endif\n#endif\n\n\nu8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3\n\t, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9\n\t\t\t\t\t\t\t      };\nu8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4\n\t, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11\n\t\t\t\t\t\t\t      };\n\n\n#ifdef CONFIG_WLAN_HAL_8192EE\nu32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E] = {\n\t/* Index0   6  dB */ 0x7fc001ff,\n\t/* Index1   5.7dB */ 0x7b4001ed,\n\t/* Index2   5.4dB */ 0x774001dd,\n\t/* Index3   5.1dB */ 0x734001cd,\n\t/* Index4   4.8dB */ 0x6f4001bd,\n\t/* Index5   4.5dB */ 0x6b8001ae,\n\t/* Index6   4.2dB */ 0x67c0019f,\n\t/* Index7   3.9dB */ 0x64400191,\n\t/* Index8   3.6dB */ 0x60c00183,\n\t/* Index9   3.3dB */ 0x5d800176,\n\t/* Index10  3  dB */ 0x5a80016a,\n\t/* Index11  2.7dB */ 0x5740015d,\n\t/* Index12  2.4dB */ 0x54400151,\n\t/* Index13  2.1dB */ 0x51800146,\n\t/* Index14  1.8dB */ 0x4ec0013b,\n\t/* Index15  1.5dB */ 0x4c000130,\n\t/* Index16  1.2dB */ 0x49800126,\n\t/* Index17  0.9dB */ 0x4700011c,\n\t/* Index18  0.6dB */ 0x44800112,\n\t/* Index19  0.3dB */ 0x42000108,\n\t/* Index20  0  dB */ 0x40000100, /* 20 This is OFDM base index */\n\t/* Index21 -0.3dB */ 0x3dc000f7,\n\t/* Index22 -0.6dB */ 0x3bc000ef,\n\t/* Index23 -0.9dB */ 0x39c000e7,\n\t/* Index24 -1.2dB */ 0x37c000df,\n\t/* Index25 -1.5dB */ 0x35c000d7,\n\t/* Index26 -1.8dB */ 0x340000d0,\n\t/* Index27 -2.1dB */ 0x324000c9,\n\t/* Index28 -2.4dB */ 0x308000c2,\n\t/* Index29 -2.7dB */ 0x2f0000bc,\n\t/* Index30 -3  dB */ 0x2d4000b5,\n\t/* Index31 -3.3dB */ 0x2bc000af,\n\t/* Index32 -3.6dB */ 0x2a4000a9,\n\t/* Index33 -3.9dB */ 0x28c000a3,\n\t/* Index34 -4.2dB */ 0x2780009e,\n\t/* Index35 -4.5dB */ 0x26000098,\n\t/* Index36 -4.8dB */ 0x24c00093,\n\t/* Index37 -5.1dB */ 0x2380008e,\n\t/* Index38 -5.4dB */ 0x22400089,\n\t/* Index39 -5.7dB */ 0x21400085,\n\t/* Index40 -6  dB */ 0x20000080,\n\t/* Index41 -6.3dB */ 0x1f00007c,\n\t/* Index42 -6.6dB */ 0x1e000078,\n\t/* Index43 -6.9dB */ 0x1d000074,\n\t/* Index44 -7.2dB */ 0x1c000070,\n\t/* Index45 -7.5dB */ 0x1b00006c,\n\t/* Index46 -7.8dB */ 0x1a000068,\n\t/* Index47 -8.1dB */ 0x19400065,\n\t/* Index48 -8.4dB */ 0x18400061,\n\t/* Index49 -8.7dB */ 0x1780005e,\n\t/* Index50 -9  dB */ 0x16c0005b,\n\t/* Index51 -9.3dB */ 0x16000058,\n\t/* Index52 -9.6dB */ 0x15400055,\n\t/* Index53 -9.9dB */ 0x14800052\n};\nu8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8] = {\n\t/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x1C, 0x12, 0x08, 0x04},\n\t/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x1B, 0x11, 0x08, 0x04},\n\t/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x1A, 0x11, 0x07, 0x04},\n\t/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x19, 0x10, 0x07, 0x04},\n\t/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x18, 0x10, 0x07, 0x03},\n\t/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x18, 0x0F, 0x07, 0x03},\n\t/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x17, 0x0F, 0x06, 0x03},\n\t/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x16, 0x0E, 0x06, 0x03},\n\t/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x15, 0x0E, 0x06, 0x03},\n\t/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x14, 0x0D, 0x06, 0x03},\n\t/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x14, 0x0D, 0x06, 0x03},\n\t/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x13, 0x0C, 0x05, 0x03},\n\t/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x12, 0x0C, 0x05, 0x03},\n\t/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x12, 0x0B, 0x05, 0x03},\n\t/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x11, 0x0B, 0x05, 0x02},\n\t/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x11, 0x0B, 0x05, 0x02},\n\t/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x10, 0x0A, 0x05, 0x02},\n\t/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x10, 0x0A, 0x04, 0x02},\n\t/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x0F, 0x0A, 0x04, 0x02},\n\t/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x0E, 0x09, 0x04, 0x02},\n\t/* Index20  -6.0dB */    {0x1B, 0x1A, 0x17, 0x13, 0x0E, 0x09, 0x04, 0x02}, /* 20 This is CCK base index */\n\t/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x0E, 0x09, 0x04, 0x02},\n\t/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x0D, 0x08, 0x04, 0x02},\n\t/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x0D, 0x08, 0x04, 0x02},\n\t/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x0C, 0x08, 0x03, 0x02},\n\t/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x0C, 0x08, 0x03, 0x02},\n\t/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x0B, 0x07, 0x03, 0x02},\n\t/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x0B, 0x07, 0x03, 0x02},\n\t/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x0B, 0x07, 0x03, 0x02},\n\t/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x0A, 0x07, 0x03, 0x01},\n\t/* Index30  -9.0dB */    {0x13, 0x12, 0x10, 0x0D, 0x0A, 0x06, 0x03, 0x01}, /* 30 This is hp CCK base index */\n\t/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x0A, 0x06, 0x03, 0x01},\n\t/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x09, 0x06, 0x03, 0x01},\n\t/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x09, 0x06, 0x03, 0x01},\n\t/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x09, 0x06, 0x02, 0x01},\n\t/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x08, 0x05, 0x02, 0x01},\n\t/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x08, 0x05, 0x02, 0x01},\n\t/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x08, 0x05, 0x02, 0x01},\n\t/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},\n\t/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},\n\t/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},\n\t/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},\n\t/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},\n\t/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x06, 0x04, 0x02, 0x01},\n\t/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},\n\t/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},\n\t/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},\n\t/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x06, 0x04, 0x02, 0x01},\n\t/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},\n\t/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},\n\t/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},\n\t/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},\n\t/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},\n\t/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}\n};\nu8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = {\n\t/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x00, 0x00, 0x00, 0x00},\n\t/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x00, 0x00, 0x00, 0x00},\n\t/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x00, 0x00, 0x00, 0x00},\n\t/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x00, 0x00, 0x00, 0x00},\n\t/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x00, 0x00, 0x00, 0x00},\n\t/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x00, 0x00, 0x00, 0x00},\n\t/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x00, 0x00, 0x00, 0x00},\n\t/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x00, 0x00, 0x00, 0x00},\n\t/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x00, 0x00, 0x00, 0x00},\n\t/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x00, 0x00, 0x00, 0x00},\n\t/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x00, 0x00, 0x00, 0x00},\n\t/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x00, 0x00, 0x00, 0x00},\n\t/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x00, 0x00, 0x00, 0x00},\n\t/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x00, 0x00, 0x00, 0x00},\n\t/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x00},\n\t/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x00, 0x00, 0x00, 0x00},\n\t/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x00, 0x00, 0x00, 0x00},\n\t/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x00, 0x00, 0x00, 0x00},\n\t/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x00, 0x00, 0x00, 0x00},\n\t/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x00, 0x00, 0x00, 0x00},\n\t/* Index20  -6  dB */     {0x1B, 0x1A, 0x17, 0x13, 0x00, 0x00, 0x00, 0x00},\n\t/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00},\n\t/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x00, 0x00, 0x00, 0x00},\n\t/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x00, 0x00, 0x00, 0x00},\n\t/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x00, 0x00, 0x00, 0x00},\n\t/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x00, 0x00, 0x00, 0x00},\n\t/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x00, 0x00, 0x00, 0x00},\n\t/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x00, 0x00, 0x00, 0x00},\n\t/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},\n\t/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},\n\t/* Index30  -9  dB */    {0x13, 0x12, 0x10, 0x0D, 0x00, 0x00, 0x00, 0x00},\n\t/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},\n\t/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},\n\t/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x00, 0x00, 0x00, 0x00},\n\t/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00},\n\t/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x00, 0x00, 0x00, 0x00},\n\t/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x00, 0x00, 0x00, 0x00},\n\t/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x00, 0x00, 0x00, 0x00},\n\t/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},\n\t/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},\n\t/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},\n\t/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},\n\t/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},\n\t/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x00, 0x00, 0x00, 0x00},\n\t/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},\n\t/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},\n\t/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x00, 0x00, 0x00, 0x00},\n\t/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},\n\t/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},\n\t/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},\n\t/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},\n\t/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},\n\t/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},\n\t/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00}\n};\n#endif\n\n#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\\\n\tRTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\\\n\tRTL8814B_SUPPORT == 1)\nu32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {\n\t0x081, /* 0,  -12.0dB */\n\t0x088, /* 1,  -11.5dB */\n\t0x090, /* 2,  -11.0dB */\n\t0x099, /* 3,  -10.5dB */\n\t0x0A2, /* 4,  -10.0dB */\n\t0x0AC, /* 5,  -9.5dB */\n\t0x0B6, /* 6,  -9.0dB */\n\t0x0C0, /* 7,  -8.5dB */\n\t0x0CC, /* 8,  -8.0dB */\n\t0x0D8, /* 9,  -7.5dB */\n\t0x0E5, /* 10, -7.0dB */\n\t0x0F2, /* 11, -6.5dB */\n\t0x101, /* 12, -6.0dB */\n\t0x110, /* 13, -5.5dB */\n\t0x120, /* 14, -5.0dB */\n\t0x131, /* 15, -4.5dB */\n\t0x143, /* 16, -4.0dB */\n\t0x156, /* 17, -3.5dB */\n\t0x16A, /* 18, -3.0dB */\n\t0x180, /* 19, -2.5dB */\n\t0x197, /* 20, -2.0dB */\n\t0x1AF, /* 21, -1.5dB */\n\t0x1C8, /* 22, -1.0dB */\n\t0x1E3, /* 23, -0.5dB */\n\t0x200, /* 24, +0  dB */\n\t0x21E, /* 25, +0.5dB */\n\t0x23E, /* 26, +1.0dB */\n\t0x261, /* 27, +1.5dB */\n\t0x285, /* 28, +2.0dB */\n\t0x2AB, /* 29, +2.5dB */\n\t0x2D3, /* 30, +3.0dB */\n\t0x2FE, /* 31, +3.5dB */\n\t0x32B, /* 32, +4.0dB */\n\t0x35C, /* 33, +4.5dB */\n\t0x38E, /* 34, +5.0dB */\n\t0x3C4, /* 35, +5.5dB */\n\t0x3FE  /* 36, +6.0dB */\n};\n#elif(ODM_IC_11AC_SERIES_SUPPORT)\nu32 ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812] = {\n\t0x3FE, /* 0,  (6dB) */\n\t0x3C4, /* 1,  (5.5dB) */\n\t0x38E, /* 2,  (5dB) */\n\t0x35C, /* 3,  (4.5dB) */\n\t0x32B, /* 4,  (4dB) */\n\t0x2FE, /* 5,  (3.5dB) */\n\t0x2D3, /* 6,  (3dB) */\n\t0x2AB, /* 7,  (2.5dB) */\n\t0x285, /* 8,  (2dB) */\n\t0x261, /* 9,  (1.5dB */\n\t0x23E, /* 10, (1dB) */\n\t0x21E, /* 11, (0.5dB) */\n\t0x200, /* 12, (0dB)\t\t8814 int PA 2G default */\n\t0x1E3, /* 13, (-0.5dB) */\n\t0x1C8, /* 14, (-1dB) */\n\t0x1AF, /* 15, (-1.5dB) */\n\t0x197, /* 16, (-2dB) */\n\t0x180, /* 17, (-2.5dB) */\n\t0x16A, /* 18, (-3dB)\t\t8812 / 8814 int PA 5G / 8814 ext PA 2G5G default */\n\t0x156, /* 19, (-3.5dB) */\n\t0x143, /* 20, (-4dB)\t\t8812 HP default */\n\t0x131, /* 21, (-4.5dB) */\n\t0x120, /* 22, (-5dB) */\n\t0x110, /* 23, (-5.5dB) */\n\t0x101, /* 24, (-6dB) */\n\t0x0F2, /* 25, (-6.5dB) */\n\t0x0E5, /* 26, (-7dB) */\n\t0x0D8, /* 27, (-7.5dB) */\n\t0x0CC, /* 28, (-8dB) */\n\t0x0C0, /* 29, (-8.5dB) */\n\t0x0B6, /* 30, (-9dB) */\n\t0x0AC, /* 31, (-9.5dB) */\n\t0x0A2, /* 32, (-10dB) */\n\t0x099, /* 33, (-10.5dB) */\n\t0x090, /* 34, (-11dB) */\n\t0x088, /* 35, (-11.5dB) */\n\t0x081, /* 36, (-12dB) */\n\t0x079, /* 37, (-12.5dB) */\n\t0x072, /* 38, (-13dB) */\n\t0x06c, /* 39, (-13.5dB) */\n\t0x066, /* 40, (-14dB) */\n\t0x060, /* 41, (-14.5dB) */\n\t0x05B  /* 42, (-15dB) */\n};\n#endif\n\nu32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {\n\t0x0CD,\n\t0x0D9,\n\t0x0E6,\n\t0x0F3,\n\t0x102,\n\t0x111,\n\t0x121,\n\t0x132,\n\t0x144,\n\t0x158,\n\t0x16C,\n\t0x182,\n\t0x198,\n\t0x1B1,\n\t0x1CA,\n\t0x1E5,\n\t0x202,\n\t0x221,\n\t0x241,\n\t0x263,\n\t0x287,\n\t0x2AE,\n\t0x2D6,\n\t0x301,\n\t0x32F,\n\t0x35F,\n\t0x392,\n\t0x3C9,\n\t0x402,\n\t0x43F,\n\t0x47F,\n\t0x4C3,\n\t0x50C,\n\t0x558,\n\t0x5A9,\n\t0x5FF,\n\t0x65A,\n\t0x6BA,\n\t0x720,\n\t0x78C,\n\t0x7FF,\n};\n/* JJ ADD 20161014 */\nu32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {\n\t0x0CD,\n\t0x0D9,\n\t0x0E6,\n\t0x0F3,\n\t0x102,\n\t0x111,\n\t0x121,\n\t0x132,\n\t0x144,\n\t0x158,\n\t0x16C,\n\t0x182,\n\t0x198,\n\t0x1B1,\n\t0x1CA,\n\t0x1E5,\n\t0x202,\n\t0x221,\n\t0x241,\n\t0x263,\n\t0x287,\n\t0x2AE,\n\t0x2D6,\n\t0x301,\n\t0x32F,\n\t0x35F,\n\t0x392,\n\t0x3C9,\n\t0x402,\n\t0x43F,\n\t0x47F,\n\t0x4C3,\n\t0x50C,\n\t0x558,\n\t0x5A9,\n\t0x5FF,\n\t0x65A,\n\t0x6BA,\n\t0x720,\n\t0x78C,\n\t0x7FF,\n};\n\n\n/* #endif */\n/* 3============================================================\n * 3 Tx Power Tracking\n * 3============================================================ */\n\nvoid\nodm_txpowertracking_init(\n\tvoid\t\t*dm_void\n)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tif (!(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_IC_11N_SERIES)))\n\t\treturn;\n#endif\n\n\todm_txpowertracking_thermal_meter_init(dm);\n}\n\n\nu8\nget_swing_index(\n\tvoid\t\t*dm_void\n)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\tu8\t\t\ti = 0, bb_swing_mask = 0;\n\tu32\t\t\tbb_swing = 0;\n\tu32\t\t\tswing_table_size = 0;\n\tu32\t\t\t*swing_table = 0;\n\tstruct rtl8192cd_priv\t*priv = dm->priv;\n\n#if (RTL8197F_SUPPORT == 1)\n\tif (GET_CHIP_VER(priv) == VERSION_8197F) {\n\t\tbb_swing = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D);\n\t\tswing_table = ofdm_swing_table_new;\n\t\tswing_table_size = OFDM_TABLE_SIZE_92D;\n\t\tbb_swing_mask = 22;\n\t}\n#endif\n\n#if (RTL8192F_SUPPORT == 1)\n\tif (GET_CHIP_VER(priv) == VERSION_8192F) {\n\t\tbb_swing = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D);\n\t\tswing_table = ofdm_swing_table_new;\n\t\tswing_table_size = OFDM_TABLE_SIZE_92D;\n\t\tbb_swing_mask = 22;\n\t}\n#endif\n\n#if (RTL8822B_SUPPORT == 1)\n\tif (GET_CHIP_VER(priv) == VERSION_8822B) {\n\t\tbb_swing = phy_query_bb_reg(priv, REG_A_TX_SCALE_JAGUAR, 0xFFE00000);\n\t\tswing_table = tx_scaling_table_jaguar;\n\t\tswing_table_size = TXSCALE_TABLE_SIZE;\n\t\tbb_swing_mask = 0;\n\t}\n#endif\n\n\tfor (i = 0; i < swing_table_size - 1; i++) {\n\t\tu32 table_value = swing_table[i] >> bb_swing_mask;\n\n\t\tif (bb_swing == table_value)\n\t\t\tbreak;\n\t}\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"bb_swing=0x%x bbswing_index=%d\\n\", bb_swing, i);\n\n\n\treturn i;\n}\n\n\nvoid\nodm_txpowertracking_thermal_meter_init(\n\tvoid\t\t*dm_void\n)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct\t*cali_info = &(dm->rf_calibrate_info);\n\tstruct rtl8192cd_priv\t\t*priv = dm->priv;\n\tu8 p;\n\tu8 default_swing_index;\n#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1)\n\tif ((GET_CHIP_VER(priv) == VERSION_8197F) || (GET_CHIP_VER(priv) == VERSION_8822B) ||(GET_CHIP_VER(priv) == VERSION_8192F))\n\t\tdefault_swing_index = get_swing_index(dm);\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid\t\t*adapter = dm->adapter;\n\tPMGNT_INFO\tmgnt_info = &adapter->MgntInfo;\n\tHAL_DATA_TYPE\t\t*hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\n\tmgnt_info->is_txpowertracking = true;\n\thal_data->tx_powercount       = 0;\n\thal_data->is_txpowertracking_init = false;\n\n\tif (*(dm->mp_mode) == false)\n\t\thal_data->txpowertrack_control = true;\n\tRF_DBG(dm, COMP_POWER_TRACKING, \"mgnt_info->is_txpowertracking = %d\\n\", mgnt_info->is_txpowertracking);\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n#ifdef CONFIG_RTL8188E\n\t{\n\t\tdm->rf_calibrate_info.is_txpowertracking = true;\n\t\tdm->rf_calibrate_info.tx_powercount = 0;\n\t\tdm->rf_calibrate_info.is_txpowertracking_init = false;\n\n\t\tif (*(dm->mp_mode) == false)\n\t\t\tdm->rf_calibrate_info.txpowertrack_control = true;\n\n\t\tMSG_8192C(\"dm txpowertrack_control = %d\\n\", dm->rf_calibrate_info.txpowertrack_control);\n\t}\n#else\n\t{\n\t\tvoid\t\t*adapter = dm->adapter;\n\t\tHAL_DATA_TYPE\t*hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\t\tstruct dm_priv\t*pdmpriv = &hal_data->dmpriv;\n\t\t\n\t\tpdmpriv->is_txpowertracking = true;\n\t\tpdmpriv->tx_powercount = 0;\n\t\tpdmpriv->is_txpowertracking_init = false;\n\n\t\tif (*(dm->mp_mode) == false)\t\t/* for mp driver, turn off txpwrtracking as default */\n\t\t\tpdmpriv->txpowertrack_control = true;\n\n\t\tMSG_8192C(\"pdmpriv->txpowertrack_control = %d\\n\", pdmpriv->txpowertrack_control);\n\n\t}\n#endif/* endif (CONFIG_RTL8188E==1) */\n#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\n#ifdef RTL8188E_SUPPORT\n\t{\n\t\tdm->rf_calibrate_info.is_txpowertracking = true;\n\t\tdm->rf_calibrate_info.tx_powercount = 0;\n\t\tdm->rf_calibrate_info.is_txpowertracking_init = false;\n\t\tdm->rf_calibrate_info.txpowertrack_control = true;\n\t\tdm->rf_calibrate_info.tm_trigger = 0;\n\t}\n#endif\n#endif\n\n\tdm->rf_calibrate_info.txpowertrack_control = true;\n\tdm->rf_calibrate_info.delta_power_index = 0;\n\tdm->rf_calibrate_info.delta_power_index_last = 0;\n\tdm->rf_calibrate_info.power_index_offset = 0;\n\tdm->rf_calibrate_info.thermal_value = 0;\n\tcali_info->default_ofdm_index = 28;\n\n#if (RTL8197F_SUPPORT == 1)\n\tif (GET_CHIP_VER(priv) == VERSION_8197F) {\n\t\tcali_info->default_ofdm_index = (default_swing_index >= (OFDM_TABLE_SIZE_92D - 1)) ? 30 : default_swing_index;\n\t\tcali_info->default_cck_index = 28;\n\t}\n#endif\n\n#if (RTL8192F_SUPPORT == 1)\n\tif (GET_CHIP_VER(priv) == VERSION_8192F) {\n\t\tcali_info->default_ofdm_index = 30;\n\t\tcali_info->default_cck_index = 28;\n\t}\n#endif\n\n#if (RTL8822B_SUPPORT == 1)\n\tif (GET_CHIP_VER(priv) == VERSION_8822B) {\n\t\tcali_info->default_ofdm_index = (default_swing_index >= (TXSCALE_TABLE_SIZE - 1)) ? 24 : default_swing_index;\n\t\tcali_info->default_cck_index = 20;\n\t}\n#endif\n\n\n#if RTL8188E_SUPPORT\n\tcali_info->default_cck_index = 20;\t/* -6 dB */\n#elif RTL8192E_SUPPORT\n\tcali_info->default_cck_index = 8;\t/* -12 dB */\n#endif\n\tcali_info->bb_swing_idx_ofdm_base = cali_info->default_ofdm_index;\n\tcali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;\n\tdm->rf_calibrate_info.CCK_index = cali_info->default_cck_index;\n\n\tfor (p = 0; p < MAX_RF_PATH; p++) {\n\t\tdm->rf_calibrate_info.OFDM_index[p] = cali_info->default_ofdm_index;\n\t\tcali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;\n\t\tcali_info->kfree_offset[p] = 0;\t/* for 8814 kfree*/\n\t}\n\tcali_info->bb_swing_idx_cck = cali_info->default_cck_index;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"cali_info->default_ofdm_index=%d cali_info->default_cck_index=%d\\n\", cali_info->default_ofdm_index, cali_info->default_cck_index);\n\n\tcali_info->tm_trigger = 0;\n}\n\n\nvoid\nodm_txpowertracking_check(\n\tvoid\t\t*dm_void\n)\n{\n\t/*  */\n\t/* For AP/ADSL use struct rtl8192cd_priv* */\n\t/* For CE/NIC use struct void* */\n\t/*  */\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_\t\t\t\t*rf = &(dm->rf_table);\n\n\tif (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))\n\t\treturn;\n\n\t/*  */\n\t/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */\n\t/* at the same time. In the stage2/3, we need to prive universal interface and merge all */\n\t/* HW dynamic mechanism. */\n\t/*  */\n\tswitch\t(dm->support_platform) {\n\tcase\tODM_WIN:\n\t\todm_txpowertracking_check_mp(dm);\n\t\tbreak;\n\n\tcase\tODM_CE:\n\t\todm_txpowertracking_check_ce(dm);\n\t\tbreak;\n\n\tcase\tODM_AP:\n\t\todm_txpowertracking_check_ap(dm);\n\t\tbreak;\n\t}\n\n}\n\nvoid\nodm_txpowertracking_check_ce(\n\tvoid\t\t*dm_void\n)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\tvoid\t*adapter = dm->adapter;\n\tstruct _hal_rf_\t\t\t\t*rf = &(dm->rf_table);\n\n#if (RTL8188E_SUPPORT == 1)\n\n\t/* if(!mgnt_info->is_txpowertracking || (!pdmpriv->txpowertrack_control && pdmpriv->is_ap_kdone)) */\n\n\tif (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))\n\t\treturn;\n\n\tif (!dm->rf_calibrate_info.tm_trigger) {\t/* at least delay 1 sec */\n\t\t/* hal_data->TxPowerCheckCnt++;\t */ /* cosa add for debug */\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);\n\t\t/* DBG_8192C(\"Trigger 92C Thermal Meter!!\\n\"); */\n\n\t\tdm->rf_calibrate_info.tm_trigger = 1;\n\t\treturn;\n\n\t} else {\n\t\t/* DBG_8192C(\"Schedule TxPowerTracking direct call!!\\n\"); */\n\t\todm_txpowertracking_callback_thermal_meter_8188e(adapter);\n\t\tdm->rf_calibrate_info.tm_trigger = 0;\n\t}\n#endif\n\n#endif\n}\n\nvoid\nodm_txpowertracking_check_mp(\n\tvoid\t\t*dm_void\n)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\tvoid\t*adapter = dm->adapter;\n\n\tif (odm_check_power_status(adapter) == false)\n\t\treturn;\n\n\tif (!adapter->is_slave_of_dmsp || adapter->dual_mac_smart_concurrent == false)\n\t\todm_txpowertracking_thermal_meter_check(adapter);\n#endif\n\n}\n\n\nvoid\nodm_txpowertracking_check_ap(\n\tvoid\t\t*dm_void\n)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1) || (RTL8198F_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8812F_SUPPORT == 1))\n\tif (!dm->rf_calibrate_info.tm_trigger) {\n\t\tif (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8192F | ODM_RTL8198F)) {\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, 0x42, (BIT(17) | BIT(16)), 0x3);\n\t\t} else if (dm->support_ic_type & ODM_RTL8812F) {\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);\n\t\t\t\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);\n\t\t} else if (dm->support_ic_type & ODM_RTL8814B) {\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, 0x42, BIT(17), 0x1);\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, 0x42, BIT(17), 0x1);\n\t\t\todm_set_rf_reg(dm, RF_PATH_C, 0x42, BIT(17), 0x1);\n\t\t\todm_set_rf_reg(dm, RF_PATH_D, 0x42, BIT(17), 0x1);\n\t\t}\n\n\t\tdm->rf_calibrate_info.tm_trigger = 1;\n\t} else {\n\t\todm_txpowertracking_callback_thermal_meter(dm);\n\t\tdm->rf_calibrate_info.tm_trigger = 0;\n\t}\n#endif\n\n}\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_powertracking_ap.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef __HALRF_POWERTRACKING_H__\n#define __HALRF_POWERTRACKING_H__\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t#ifdef RTK_AC_SUPPORT\n\t\t#define ODM_IC_11AC_SERIES_SUPPORT\t\t1\n\t#else\n\t\t#define ODM_IC_11AC_SERIES_SUPPORT\t\t0\n\t#endif\n#else\n\t#define ODM_IC_11AC_SERIES_SUPPORT\t\t1\n#endif\n\n#define\t\tDPK_DELTA_MAPPING_NUM\t13\n#define\t\tindex_mapping_HP_NUM\t15\n#define\t\tDELTA_SWINGIDX_SIZE     30\n#define\t\tDELTA_SWINTSSI_SIZE     61\n#define\t\tBAND_NUM\t\t\t\t3\n#define\t\tMAX_RF_PATH\t4\n#define\t\tTXSCALE_TABLE_SIZE\t\t37\n#define\t\tCCK_TABLE_SIZE_8723D\t\t41\n/* JJ ADD 20161014 */\n#define\t\tCCK_TABLE_SIZE_8710B\t\t41\n\n#define IQK_MAC_REG_NUM\t\t4\n#define IQK_ADDA_REG_NUM\t\t16\n#define IQK_BB_REG_NUM_MAX\t10\n\n#define IQK_BB_REG_NUM\t\t9\n\n#define AVG_THERMAL_NUM\t\t8\n#define AVG_THERMAL_NUM_DPK\t\t8\n#define THERMAL_DPK_AVG_NUM\t\t4\n\n#define iqk_matrix_reg_num\t8\n/* #define IQK_MATRIX_SETTINGS_NUM\t1+24+21 */\n#define IQK_MATRIX_SETTINGS_NUM\t(14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */\n\n#if !defined(_OUTSRC_COEXIST)\n\t#define\tOFDM_TABLE_SIZE_92D\t43\n\t#define\tOFDM_TABLE_SIZE\t37\n\t#define\tCCK_TABLE_SIZE\t\t33\n\t#define\tCCK_TABLE_SIZE_88F\t21\n\t#define\tCCK_TABLE_SIZE_8192F\t41\n\n\n\n\t/* #define\tOFDM_TABLE_SIZE_92E\t54 */\n\t/* #define\tCCK_TABLE_SIZE_92E\t54 */\n\textern\tu32 ofdm_swing_table[OFDM_TABLE_SIZE_92D];\n\textern\tu8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];\n\textern\tu8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];\n\n\n\textern\tu32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D];\n\textern\tu8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];\n\textern\tu8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];\n\textern\tu8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];\n\textern\tu8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];\n\textern\tu8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];\n\textern\tu32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];\n\n#endif\n\n#define\tODM_OFDM_TABLE_SIZE\t37\n#define\tODM_CCK_TABLE_SIZE\t\t33\n#define TXPWR_TRACK_TABLE_SIZE 30\n/* <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */\nextern u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE];\nextern u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE];\n\nstatic u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};\nstatic u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11};\n\n/* extern\tu32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];\n * extern\tu8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];\n * extern\tu8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8]; */\n\n#ifdef CONFIG_WLAN_HAL_8192EE\n\t#define\tOFDM_TABLE_SIZE_92E\t54\n\t#define\tCCK_TABLE_SIZE_92E\t54\n\textern\tu32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];\n\textern\tu8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];\n\textern\tu8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8];\n#endif\n\n#define\tOFDM_TABLE_SIZE_8812\t43\n#define\tAVG_THERMAL_NUM_8812\t4\n\n#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\\\n\tRTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\\\n\tRTL8814B_SUPPORT == 1)\n\textern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];\n\t#elif(ODM_IC_11AC_SERIES_SUPPORT)\n\textern unsigned int ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812];\n#endif\n\nextern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];\n/* JJ ADD 20161014 */\nextern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];\n\n#define dm_check_txpowertracking\todm_txpowertracking_check\n\nstruct iqk_matrix_regs_setting {\n\tboolean\tis_iqk_done;\n\ts32\t\tvalue[1][iqk_matrix_reg_num];\n};\n\nstruct dm_rf_calibration_struct {\n\t/* for tx power tracking */\n\n\tu32\trega24; /* for TempCCK */\n\ts32\trege94;\n\ts32\trege9c;\n\ts32\tregeb4;\n\ts32\tregebc;\n\n\t/* u8 is_txpowertracking; */\n\tu8\ttx_powercount;\n\tboolean is_txpowertracking_init;\n\tboolean is_txpowertracking;\n\tu8  \ttxpowertrack_control; /* for mp mode, turn off txpwrtracking as default */\n\tu8\ttm_trigger;\n\tu8  \tinternal_pa_5g[2];\t/* pathA / pathB */\n\n\tu8  \tthermal_meter[2];    /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */\n\tu8\tthermal_value;\n\tu8\tthermal_value_path[MAX_RF_PATH];\n\tu8\tthermal_value_lck;\n\tu8\tthermal_value_iqk;\n\ts8  \tthermal_value_delta; /* delta of thermal_value and efuse thermal */\n\tu8\tthermal_value_avg[AVG_THERMAL_NUM];\n\tu8\tthermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM];\n\tu8\tthermal_value_avg_index;\n\tu8\tthermal_value_avg_index_path[MAX_RF_PATH];\n\ts8\tpower_index_offset_path[MAX_RF_PATH];\n\n\tu8\tthermal_value_rx_gain;\n\tu8\tthermal_value_crystal;\n\tu8\tthermal_value_dpk_store;\n\tu8\tthermal_value_dpk_track;\n\tboolean\ttxpowertracking_in_progress;\n\n\n\tboolean\tis_reloadtxpowerindex;\n\tu8\tis_rf_pi_enable;\n\tu32 \ttxpowertracking_callback_cnt; /* cosa add for debug */\n\n\tu8\tis_cck_in_ch14;\n\tu8\tCCK_index;\n\tu8\tOFDM_index[MAX_RF_PATH];\n\ts8\tpower_index_offset;\n\ts8\tdelta_power_index;\n\ts8\tdelta_power_index_path[MAX_RF_PATH];\n\ts8\tdelta_power_index_last;\n\ts8\tdelta_power_index_last_path[MAX_RF_PATH];\n\tboolean is_tx_power_changed;\n\n\tstruct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];\n\tu8\tdelta_lck;\n\tu8  delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];\n\ts8  delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];\n\ts8  delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];\n\n\tu8\t\t\tbb_swing_idx_ofdm[MAX_RF_PATH];\n\tu8\t\t\tbb_swing_idx_ofdm_current;\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\tu8\t\t\tbb_swing_idx_ofdm_base[MAX_RF_PATH];\n#else\n\tu8\t\t\tbb_swing_idx_ofdm_base;\n\tu8\t\t\tbb_swing_idx_ofdm_base_path[MAX_RF_PATH];\n#endif\n\tboolean\t\t\tbb_swing_flag_ofdm;\n\tu8\t\t\tbb_swing_idx_cck;\n\tu8\t\t\tbb_swing_idx_cck_current;\n\tu8\t\t\tbb_swing_idx_cck_base;\n\tu8\t\t\tdefault_ofdm_index;\n\tu8\t\t\tdefault_cck_index;\n\tboolean\t\t\tbb_swing_flag_cck;\n\n\ts8\t\t\tabsolute_ofdm_swing_idx[MAX_RF_PATH];\n\ts8\t\t\tremnant_ofdm_swing_idx[MAX_RF_PATH];\n\ts8\t\t\tabsolute_cck_swing_idx[MAX_RF_PATH];\n\ts8\t\t\tremnant_cck_swing_idx;\n\ts8\t\t\tmodify_tx_agc_value;       /*Remnat compensate value at tx_agc */\n\tboolean\t\t\tmodify_tx_agc_flag_path_a;\n\tboolean\t\t\tmodify_tx_agc_flag_path_b;\n\tboolean\t\t\tmodify_tx_agc_flag_path_c;\n\tboolean\t\t\tmodify_tx_agc_flag_path_d;\n\tboolean\t\t\tmodify_tx_agc_flag_path_a_cck;\n\tboolean\t\t\tmodify_tx_agc_flag_path_b_cck;\n\n\ts8\t\t\tkfree_offset[MAX_RF_PATH];\n\n\t/* -------------------------------------------------------------------- */\n\n\t/* for IQK */\n\tu32\tregc04;\n\tu32\treg874;\n\tu32\tregc08;\n\tu32\tregb68;\n\tu32\tregb6c;\n\tu32\treg870;\n\tu32\treg860;\n\tu32\treg864;\n\n\tboolean\tis_iqk_initialized;\n\tboolean is_lck_in_progress;\n\tboolean\tis_antenna_detected;\n\tboolean\tis_need_iqk;\n\tboolean\tis_iqk_in_progress;\n\tboolean\tis_iqk_pa_off;\n\tu8\tdelta_iqk;\n\tu32\tADDA_backup[IQK_ADDA_REG_NUM];\n\tu32\tIQK_MAC_backup[IQK_MAC_REG_NUM];\n\tu32\tIQK_BB_backup_recover[9];\n\tu32\tIQK_BB_backup[IQK_BB_REG_NUM];\n\tu32\ttx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */\n\tu32\trx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */\n\tu32\ttx_iqc_8703b[3][2];\t/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/\n\tu32\trx_iqc_8703b[2][2];\t/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/\n\n\tu64\tiqk_start_time;\n\tu64\tiqk_total_progressing_time;\n\tu64\tiqk_progressing_time;\n\tu64\tlck_progressing_time;\n\tu32  lok_result;\n\tu8\tiqk_step;\n\tu8\tkcount;\n\tu8\tretry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */\n\tboolean\tis_mp_mode;\n\n\t/* for APK */\n\tu32 \tap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */\n\tu8\tis_ap_kdone;\n\tu8\tis_apk_thermal_meter_ignore;\n\tu8\tis_dp_done;\n#if 0 /*move below members to halrf_dpk.h*/\n\tu8\tis_dp_path_aok;\n\tu8\tis_dp_path_bok;\n\tu8\tis_dp_path_cok;\n\tu8\tis_dp_path_dok;\n\tu8 \tdp_path_a_result[3];\n\tu8 \tdp_path_b_result[3];\n\tu8 \tdp_path_c_result[3];\n\tu8 \tdp_path_d_result[3];\n\tboolean\tis_dpk_enable;\n\tu32\ttxrate[11];\n\tu8 \tpwsf_2g_a[3];\n\tu8 \tpwsf_2g_b[3];\n\tu8 \tpwsf_2g_c[3];\n\tu8 \tpwsf_2g_d[3];\n\tu32\tlut_2g_even_a[3][64];\n\tu32\tlut_2g_odd_a[3][64];\n\tu32\tlut_2g_even_b[3][64];\n\tu32\tlut_2g_odd_b[3][64];\n\tu32\tlut_2g_even_c[3][64];\n\tu32\tlut_2g_odd_c[3][64];\n\tu32\tlut_2g_even_d[3][64];\n\tu32\tlut_2g_odd_d[3][64];\n\tu1Byte \tis_5g_pdk_a_ok;\n\tu1Byte \tis_5g_pdk_b_ok;\n\tu1Byte \tis_5g_pdk_c_ok;\n\tu1Byte \tis_5g_pdk_d_ok;\n\tu1Byte \tpwsf_5g_a[9];\n\tu1Byte \tpwsf_5g_b[9];\n\tu1Byte \tpwsf_5g_c[9];\n\tu1Byte \tpwsf_5g_d[9];\n\tu4Byte\tlut_5g_even_a[9][16];\n\tu4Byte\tlut_5g_odd_a[9][16];\n\tu4Byte\tlut_5g_even_b[9][16];\n\tu4Byte\tlut_5g_odd_b[9][16];\n\tu4Byte\tlut_5g_even_c[9][16];\n\tu4Byte\tlut_5g_odd_c[9][16];\n\tu4Byte\tlut_5g_even_d[9][16];\n\tu4Byte\tlut_5g_odd_d[9][16];\n\tu8\tthermal_value_dpk;\n\tu8\tthermal_value_dpk_avg[AVG_THERMAL_NUM_DPK];\n\tu8\tthermal_value_dpk_avg_index;\n#endif\n\ts8  modify_tx_agc_value_ofdm;\n\ts8  modify_tx_agc_value_cck;\n\n\t/*Add by Yuchen for Kfree Phydm*/\n\tu8\t\t\treg_rf_kfree_enable;\t/*for registry*/\n\tu8\t\t\trf_kfree_enable;\t\t/*for efuse enable check*/\n\tu32\ttx_lok[2];\n};\n\nvoid\nodm_txpowertracking_check_ap(\n\tvoid\t\t*dm_void\n);\n\nvoid\nodm_txpowertracking_check(\n\tvoid\t\t*dm_void\n);\n\n\nvoid\nodm_txpowertracking_thermal_meter_init(\n\tvoid\t\t*dm_void\n);\n\nvoid\nodm_txpowertracking_init(\n\tvoid\t\t*dm_void\n);\n\nvoid\nodm_txpowertracking_check_mp(\n\tvoid\t\t*dm_void\n);\n\n\nvoid\nodm_txpowertracking_check_ce(\n\tvoid\t\t*dm_void\n);\n\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\n\nvoid\nodm_txpowertracking_callback_thermal_meter92c(\n\tvoid\t*adapter\n);\n\nvoid\nodm_txpowertracking_callback_rx_gain_thermal_meter92d(\n\tvoid\t*adapter\n);\n\nvoid\nodm_txpowertracking_callback_thermal_meter92d(\n\tvoid\t*adapter\n);\n\nvoid\nodm_txpowertracking_direct_call92c(\n\tvoid\t\t*adapter\n);\n\nvoid\nodm_txpowertracking_thermal_meter_check(\n\tvoid\t\t*adapter\n);\n\n#endif\n\n\n\n#endif\t/*#ifndef __HALRF_POWER_TRACKING_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_powertracking_ce.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@===========================================================\n * include files\n *============================================================\n */\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n/*@************************************************************\n * Global var\n * ************************************************************\n */\n\nu32 ofdm_swing_table[OFDM_TABLE_SIZE] = {\n\t0x7f8001fe, /* 0, +6.0dB */\n\t0x788001e2, /* 1, +5.5dB */\n\t0x71c001c7, /* 2, +5.0dB*/\n\t0x6b8001ae, /* 3, +4.5dB*/\n\t0x65400195, /* 4, +4.0dB*/\n\t0x5fc0017f, /* 5, +3.5dB*/\n\t0x5a400169, /* 6, +3.0dB*/\n\t0x55400155, /* 7, +2.5dB*/\n\t0x50800142, /* 8, +2.0dB*/\n\t0x4c000130, /* 9, +1.5dB*/\n\t0x47c0011f, /* 10, +1.0dB*/\n\t0x43c0010f, /* 11, +0.5dB*/\n\t0x40000100, /* 12, +0dB*/\n\t0x3c8000f2, /* 13, -0.5dB*/\n\t0x390000e4, /* 14, -1.0dB*/\n\t0x35c000d7, /* 15, -1.5dB*/\n\t0x32c000cb, /* 16, -2.0dB*/\n\t0x300000c0, /* 17, -2.5dB*/\n\t0x2d4000b5, /* 18, -3.0dB*/\n\t0x2ac000ab, /* 19, -3.5dB*/\n\t0x288000a2, /* 20, -4.0dB*/\n\t0x26000098, /* 21, -4.5dB*/\n\t0x24000090, /* 22, -5.0dB*/\n\t0x22000088, /* 23, -5.5dB*/\n\t0x20000080, /* 24, -6.0dB*/\n\t0x1e400079, /* 25, -6.5dB*/\n\t0x1c800072, /* 26, -7.0dB*/\n\t0x1b00006c, /* 27. -7.5dB*/\n\t0x19800066, /* 28, -8.0dB*/\n\t0x18000060, /* 29, -8.5dB*/\n\t0x16c0005b, /* 30, -9.0dB*/\n\t0x15800056, /* 31, -9.5dB*/\n\t0x14400051, /* 32, -10.0dB*/\n\t0x1300004c, /* 33, -10.5dB*/\n\t0x12000048, /* 34, -11.0dB*/\n\t0x11000044, /* 35, -11.5dB*/\n\t0x10000040, /* 36, -12.0dB*/\n};\n\nu8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {\n\t{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */\n\t{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */\n\t{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */\n\t{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */\n\t{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */\n\t{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */\n\t{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */\n\t{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */\n\t{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */\n\t{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */\n\t{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */\n\t{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */\n\t{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0 default*/\n\t{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */\n\t{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */\n\t{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */\n\t{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */\n\t{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */\n\t{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */\n\t{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */\n\t{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */\n\t{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */\n\t{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */\n\t{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */\n\t{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */\n\t{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */\n\t{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */\n\t{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */\n\t{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */\n\t{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */\n\t{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */\n\t{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */\n\t{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */\n};\n\nu8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {\n\t{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */\n\t{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */\n\t{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */\n\t{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */\n\t{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */\n\t{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */\n\t{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */\n\t{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */\n\t{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */\n\t{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */\n\t{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */\n\t{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */\n\t{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0 default*/\n\t{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */\n\t{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */\n\t{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */\n\t{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */\n\t{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */\n\t{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */\n\t{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */\n\t{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */\n\t{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */\n\t{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */\n\t{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */\n\t{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */\n\t{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */\n\t{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */\n\t{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */\n\t{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */\n\t{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */\n\t{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */\n\t{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */\n\t{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */\n};\n\nu32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {\n\t0x0b40002d, /* 0,  -15.0dB */\n\t0x0c000030, /* 1,  -14.5dB */\n\t0x0cc00033, /* 2,  -14.0dB */\n\t0x0d800036, /* 3,  -13.5dB */\n\t0x0e400039, /* 4,  -13.0dB */\n\t0x0f00003c, /* 5,  -12.5dB */\n\t0x10000040, /* 6,  -12.0dB */\n\t0x11000044, /* 7,  -11.5dB */\n\t0x12000048, /* 8,  -11.0dB */\n\t0x1300004c, /* 9,  -10.5dB */\n\t0x14400051, /* 10, -10.0dB */\n\t0x15800056, /* 11, -9.5dB */\n\t0x16c0005b, /* 12, -9.0dB */\n\t0x18000060, /* 13, -8.5dB */\n\t0x19800066, /* 14, -8.0dB */\n\t0x1b00006c, /* 15, -7.5dB */\n\t0x1c800072, /* 16, -7.0dB */\n\t0x1e400079, /* 17, -6.5dB */\n\t0x20000080, /* 18, -6.0dB */\n\t0x22000088, /* 19, -5.5dB */\n\t0x24000090, /* 20, -5.0dB */\n\t0x26000098, /* 21, -4.5dB */\n\t0x288000a2, /* 22, -4.0dB */\n\t0x2ac000ab, /* 23, -3.5dB */\n\t0x2d4000b5, /* 24, -3.0dB */\n\t0x300000c0, /* 25, -2.5dB */\n\t0x32c000cb, /* 26, -2.0dB */\n\t0x35c000d7, /* 27, -1.5dB */\n\t0x390000e4, /* 28, -1.0dB */\n\t0x3c8000f2, /* 29, -0.5dB */\n\t0x40000100, /* 30, +0dB */\n\t0x43c0010f, /* 31, +0.5dB */\n\t0x47c0011f, /* 32, +1.0dB */\n\t0x4c000130, /* 33, +1.5dB */\n\t0x50800142, /* 34, +2.0dB */\n\t0x55400155, /* 35, +2.5dB */\n\t0x5a400169, /* 36, +3.0dB */\n\t0x5fc0017f, /* 37, +3.5dB */\n\t0x65400195, /* 38, +4.0dB */\n\t0x6b8001ae, /* 39, +4.5dB */\n\t0x71c001c7, /* 40, +5.0dB */\n\t0x788001e2, /* 41, +5.5dB */\n\t0x7f8001fe /* 42, +6.0dB */\n};\n\nu8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {\n\t{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/\n\t{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/\n\t{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/\n\t{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/\n\t{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/\n\t{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/\n\t{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/\n\t{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/\n\t{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/\n\t{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/\n\t{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/\n\t{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/\n\t{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/\n\t{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/\n\t{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/\n\t{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/\n\t{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/\n\t{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/\n\t{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/\n\t{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/\n\t{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/\n};\n\nu8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {\n\t{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/\n\t{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/\n\t{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/\n\t{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/\n\t{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/\n\t{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/\n\t{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/\n\t{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/\n\t{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/\n\t{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/\n\t{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/\n\t{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/\n\t{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/\n\t{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/\n\t{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/\n\t{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/\n\t{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/\n\t{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/\n\t{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/\n\t{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/\n\t{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/\n};\n\nu8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {\n\t{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/\n\t{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/\n\t{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/\n\t{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/\n\t{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/\n\t{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/\n\t{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/\n\t{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/\n\t{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/\n\t{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/\n\t{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/\n\t{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/\n\t{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/\n\t{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/\n\t{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/\n\t{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/\n\t{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/\n\t{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/\n\t{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/\n\t{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/\n\t{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/\n};\n\nu8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {\n\t{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /*   0, -16.0dB*/\n\t{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /*   1, -15.5dB*/\n\t{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /*   2, -15.0dB*/\n\t{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /*   3, -14.5dB*/\n\t{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /*   4, -14.0dB*/\n\t{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /*   5, -13.5dB*/\n\t{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /*   6, -13.0dB*/\n\t{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /*   7, -12.5dB*/\n\t{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /*   8, -12.0dB*/\n\t{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /*   9, -11.5dB*/\n\t{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  10, -11.0dB*/\n\t{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  11, -10.5dB*/\n\t{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  12, -10.0dB*/\n\t{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  13, -9.5dB*/\n\t{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /*  14, -9.0dB */\n\t{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /*  15, -8.5dB*/\n\t{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /*  16, -8.0dB */\n\t{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /*  17, -7.5dB*/\n\t{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /*  18, -7.0dB */\n\t{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /*  19, -6.5dB*/\n\t{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*  20, -6.0dB */\n\t{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /*  21, -5.5dB*/\n\t{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /*  22, -5.0dB */\n\t{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /*  23, -4.5dB*/\n\t{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /*  24, -4.0dB */\n\t{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /*  25, -3.5dB*/\n\t{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /*  26, -3.0dB*/\n\t{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /*  27, -2.5dB*/\n\t{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /*  28, -2.0dB */\n\t{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /*  29, -1.5dB*/\n\t{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /*  30, -1.0dB*/\n\t{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /*  31, -0.5dB*/\n\t{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /*   32, +0dB*/\n};\n\nu8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {\n\t{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /*  0, -16.0dB*/\n\t{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/\n\t{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  2, -15.0dB*/\n\t{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/\n\t{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  4, -14.0dB*/\n\t{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/\n\t{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/\n\t{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  7, -12.5dB*/\n\t{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/\n\t{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/\n\t{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/\n\t{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/\n\t{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/\n\t{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/\n\t{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */\n\t{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/\n\t{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */\n\t{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/\n\t{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */\n\t{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */\n\t{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */\n\t{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/\n\t{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */\n\t{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/\n\t{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */\n\t{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */\n\t{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */\n\t{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/\n\t{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */\n\t{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/\n\t{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */\n\t{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */\n\t{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB\t*/\n};\n\nu32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {\n\t0x0CD, /*0 ,    -20dB*/\n\t0x0D9,\n\t0x0E6,\n\t0x0F3,\n\t0x102,\n\t0x111,\n\t0x121,\n\t0x132,\n\t0x144,\n\t0x158,\n\t0x16C,\n\t0x182,\n\t0x198,\n\t0x1B1,\n\t0x1CA,\n\t0x1E5,\n\t0x202,\n\t0x221,\n\t0x241,\n\t0x263,\n\t0x287,\n\t0x2AE,\n\t0x2D6,\n\t0x301,\n\t0x32F,\n\t0x35F,\n\t0x392,\n\t0x3C9,\n\t0x402,\n\t0x43F,\n\t0x47F,\n\t0x4C3,\n\t0x50C,\n\t0x558,\n\t0x5A9,\n\t0x5FF,\n\t0x65A,\n\t0x6BA,\n\t0x720,\n\t0x78C,\n\t0x7FF,\n};\n\n/*@JJ ADD 20161014 */\nu32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {\n\t0x0CD, /*0 ,    -20dB*/\n\t0x0D9,\n\t0x0E6,\n\t0x0F3,\n\t0x102,\n\t0x111,\n\t0x121,\n\t0x132,\n\t0x144,\n\t0x158,\n\t0x16C,\n\t0x182,\n\t0x198,\n\t0x1B1,\n\t0x1CA,\n\t0x1E5,\n\t0x202,\n\t0x221,\n\t0x241,\n\t0x263,\n\t0x287,\n\t0x2AE,\n\t0x2D6,\n\t0x301,\n\t0x32F,\n\t0x35F,\n\t0x392,\n\t0x3C9,\n\t0x402,\n\t0x43F,\n\t0x47F,\n\t0x4C3,\n\t0x50C,\n\t0x558,\n\t0x5A9,\n\t0x5FF,\n\t0x65A,\n\t0x6BA,\n\t0x720,\n\t0x78C,\n\t0x7FF,\n};\n\n/*@Winnita ADD 20171116 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/\nu32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {\n\t0x0CD, /*0 ,    -20dB*/\n\t0x0D9,\n\t0x0E6,\n\t0x0F3,\n\t0x102,\n\t0x111,\n\t0x121,\n\t0x132,\n\t0x144,\n\t0x158,\n\t0x16C,\n\t0x182,\n\t0x198,\n\t0x1B1,\n\t0x1CA,\n\t0x1E5,\n\t0x202,\n\t0x221,\n\t0x241,\n\t0x263, /*19*/\n\t0x287, /*20*/\n\t0x2AE, /*21*/\n\t0x2D6, /*22*/\n\t0x301, /*23*/\n\t0x32F, /*24*/\n\t0x35F, /*25*/\n\t0x392, /*26*/\n\t0x3C9, /*27*/\n\t0x402, /*28*/\n\t0x43F, /*29*/\n\t0x47F, /*30*/\n\t0x4C3, /*31*/\n\t0x50C, /*32*/\n\t0x558, /*33*/\n\t0x5A9, /*34*/\n\t0x5FF, /*35*/\n\t0x65A, /*36*/\n\t0x6BA,\n\t0x720,\n\t0x78C,\n\t0x7FF,\n};\n\nu32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {\n\t0x081, /* 0,  -12.0dB*/\n\t0x088, /* 1,  -11.5dB*/\n\t0x090, /* 2,  -11.0dB*/\n\t0x099, /* 3,  -10.5dB*/\n\t0x0A2, /* 4,  -10.0dB*/\n\t0x0AC, /* 5,  -9.5dB*/\n\t0x0B6, /* 6,  -9.0dB*/\n\t0x0C0, /*7,  -8.5dB*/\n\t0x0CC, /* 8,  -8.0dB*/\n\t0x0D8, /* 9,  -7.5dB*/\n\t0x0E5, /* 10, -7.0dB*/\n\t0x0F2, /* 11, -6.5dB*/\n\t0x101, /* 12, -6.0dB*/\n\t0x110, /* 13, -5.5dB*/\n\t0x120, /* 14, -5.0dB*/\n\t0x131, /* 15, -4.5dB*/\n\t0x143, /* 16, -4.0dB*/\n\t0x156, /* 17, -3.5dB*/\n\t0x16A, /* 18, -3.0dB*/\n\t0x180, /* 19, -2.5dB*/\n\t0x197, /* 20, -2.0dB*/\n\t0x1AF, /* 21, -1.5dB*/\n\t0x1C8, /* 22, -1.0dB*/\n\t0x1E3, /* 23, -0.5dB*/\n\t0x200, /* 24, +0  dB*/\n\t0x21E, /* 25, +0.5dB*/\n\t0x23E, /* 26, +1.0dB*/\n\t0x261, /* 27, +1.5dB*/\n\t0x285, /* 28, +2.0dB*/\n\t0x2AB, /* 29, +2.5dB*/\n\t0x2D3, /*30, +3.0dB*/\n\t0x2FE, /* 31, +3.5dB*/\n\t0x32B, /* 32, +4.0dB*/\n\t0x35C, /* 33, +4.5dB*/\n\t0x38E, /* 34, +5.0dB*/\n\t0x3C4, /* 35, +5.5dB*/\n\t0x3FE /* 36, +6.0dB\t*/\n};\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)\n#else\nu8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3,\n\t\t\t\t\t  4, 4, 4, 4, 4, 4, 4, 4, 5, 5,\n\t\t\t\t\t  7, 7, 8, 8, 8, 9, 9, 9, 9, 9};\nu8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4,\n\t\t\t\t\t  4, 5, 5, 6, 6, 7, 7, 7, 7, 8,\n\t\t\t\t\t  8, 9, 9, 10, 10, 10, 11, 11, 11, 11};\n#endif\n\nvoid odm_txpowertracking_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\todm_txpowertracking_thermal_meter_init(dm);\n}\n\nu8 get_swing_index(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))\n\tvoid *adapter = dm->adapter;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n#endif\n\tu8 i = 0;\n\tu32 bb_swing, table_value;\n\n\tif (dm->support_ic_type &\n\t\t(ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |\n\t\tODM_RTL8188F | ODM_RTL8703B | ODM_RTL8723D |\n\t\tODM_RTL8710B | ODM_RTL8821)) {\n#if (RTL8821A_SUPPORT == 1)\n\t\tbb_swing =\n\t\tphy_get_tx_bb_swing_8812a(adapter,\n\t\t\t\t\t  hal_data->current_band_type,\n\t\t\t\t\t  RF_PATH_A);\n#else\n\t\tbb_swing = odm_get_bb_reg(dm, R_0xc80, 0xFFC00000);\n#endif\n\t\tfor (i = 0; i < OFDM_TABLE_SIZE; i++) {\n\t\t\ttable_value = ofdm_swing_table_new[i];\n\n\t\t\tif (table_value >= 0x100000)\n\t\t\t\ttable_value >>= 22;\n\t\t\tif (bb_swing == table_value)\n\t\t\t\tbreak;\n\t\t}\n\t} else {\n#if (RTL8812A_SUPPORT == 1)\n\t\tbb_swing =\n\t\tphy_get_tx_bb_swing_8812a(adapter,\n\t\t\t\t\t  hal_data->current_band_type,\n\t\t\t\t\t  RF_PATH_A);\n#else\n\t\tbb_swing = odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000);\n#endif\n\t\tfor (i = 0; i < TXSCALE_TABLE_SIZE; i++) {\n\t\t\ttable_value = tx_scaling_table_jaguar[i];\n\n\t\t\tif (bb_swing == table_value)\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn i;\n}\n\nu8 get_cck_swing_index(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tu8 i = 0;\n\tu32 bb_cck_swing;\n\n\tif (dm->support_ic_type &\n\t\t(ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E)) {\n\t\tbb_cck_swing = odm_read_1byte(dm, 0xa22);\n\n\t\tfor (i = 0; i < CCK_TABLE_SIZE; i++) {\n\t\t\tif (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])\n\t\t\t\tbreak;\n\t\t}\n\t} else if (dm->support_ic_type & ODM_RTL8703B) {\n\t\tbb_cck_swing = odm_read_1byte(dm, 0xa22);\n\n\t\tfor (i = 0; i < CCK_TABLE_SIZE_88F; i++) {\n\t\t\tif (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn i;\n}\n\nvoid odm_txpowertracking_thermal_meter_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n#if (RTL8822C_SUPPORT == 1)\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n#endif\n\n\tu8 swing_idx = get_swing_index(dm);\n\tu8 cckswing_idx = get_cck_swing_index(dm);\n\tu8 p = 0;\n\n\tcali_info->is_txpowertracking = true;\n\tcali_info->tx_powercount = 0;\n\tcali_info->is_txpowertracking_init = false;\n\n\tif (!(*dm->mp_mode))\n\t\tcali_info->txpowertrack_control = true;\n\telse\n\t\tcali_info->txpowertrack_control = false;\n\n\tif (!(*dm->mp_mode))\n\t\tcali_info->txpowertrack_control = true;\n\n\tRF_DBG(dm, DBG_RF_IQK, \"dm txpowertrack_control = %d\\n\",\n\t       cali_info->txpowertrack_control);\n#if 0\n\t/* dm->rf_calibrate_info.txpowertrack_control = true; */\n#endif\n\tcali_info->thermal_value = rf->eeprom_thermal;\n\tcali_info->thermal_value_iqk = rf->eeprom_thermal;\n\tcali_info->thermal_value_lck = rf->eeprom_thermal;\n\n#if (RTL8822C_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8822C) {\n\t\tcali_info->thermal_value_path[RF_PATH_A] = tssi->thermal[RF_PATH_A];\n\t\tcali_info->thermal_value_path[RF_PATH_B] = tssi->thermal[RF_PATH_B];\n\t\tcali_info->thermal_value_iqk = tssi->thermal[RF_PATH_A];\n\t\tcali_info->thermal_value_lck = tssi->thermal[RF_PATH_A];\n\t}\n#endif\n\n\tif (!cali_info->default_bb_swing_index_flag) {\n\t\tif (dm->support_ic_type &\n\t\t\t(ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |\n\t\t\tODM_RTL8703B | ODM_RTL8821)) {\n\t\t\tif (swing_idx >= OFDM_TABLE_SIZE)\n\t\t\t\tcali_info->default_ofdm_index = 30;\n\t\t\telse\n\t\t\t\tcali_info->default_ofdm_index = swing_idx;\n\n\t\t\tif (cckswing_idx >= CCK_TABLE_SIZE)\n\t\t\t\tcali_info->default_cck_index = 20;\n\t\t\telse\n\t\t\t\tcali_info->default_cck_index = cckswing_idx;\n\t\t/*@add by Mingzhi.Guo  2015-03-23*/\n\t\t} else if (dm->support_ic_type == ODM_RTL8188F) {\n\t\t\tcali_info->default_ofdm_index = 28; /*OFDM: -1dB*/\n\t\t\tcali_info->default_cck_index = 20; /*CCK:-6dB*/\n\t\t/*@add by zhaohe  2015-10-27*/\n\t\t} else if (dm->support_ic_type == ODM_RTL8723D) {\n\t\t\tcali_info->default_ofdm_index = 28; /*OFDM: -1dB*/\n\t\t\tcali_info->default_cck_index = 28; /*CCK:   -6dB*/\n\t\t/*@JJ ADD 20161014 */\n\t\t} else if (dm->support_ic_type == ODM_RTL8710B) {\n\t\t\tcali_info->default_ofdm_index = 28; /*OFDM: -1dB*/\n\t\t\tcali_info->default_cck_index = 28; /*CCK:   -6dB*/\n\t\t} else if (dm->support_ic_type == ODM_RTL8192F) {\n\t\t\tcali_info->default_ofdm_index = 30;/*OFDM: 0dB*/\n\t\t\tcali_info->default_cck_index = 28; /*CCK:   -6dB*/\n\t\t} else {\n\t\t\tif (swing_idx >= TXSCALE_TABLE_SIZE)\n\t\t\t\tcali_info->default_ofdm_index = 24;\n\t\t\telse\n\t\t\t\tcali_info->default_ofdm_index = swing_idx;\n\n\t\t\tcali_info->default_cck_index = 24;\n\t\t}\n\t\tcali_info->default_bb_swing_index_flag = true;\n\t}\n\n\tcali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;\n\tcali_info->CCK_index = cali_info->default_cck_index;\n\n\tfor (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {\n\t\tcali_info->bb_swing_idx_ofdm_base[p] =\n\t\t\t\t\t\tcali_info->default_ofdm_index;\n\t\tcali_info->OFDM_index[p] = cali_info->default_ofdm_index;\n\t\tcali_info->delta_power_index[p] = 0;\n\t\tcali_info->delta_power_index_last[p] = 0;\n\t\tcali_info->power_index_offset[p] = 0;\n\t}\n\tcali_info->modify_tx_agc_value_ofdm = 0;\n\tcali_info->modify_tx_agc_value_cck = 0;\n\tcali_info->tm_trigger = 0;\n}\n\nvoid odm_txpowertracking_check(void *dm_void)\n{\n\t/*@2011/09/29 MH In HW integration first stage\n\t * we provide 4 different handle to operate at the same time.\n\t * In the stage2/3, we need to prive universal interface and merge all\n\t * HW dynamic mechanism.\n\t */\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tswitch (dm->support_platform) {\n\tcase ODM_WIN:\n\t\todm_txpowertracking_check_mp(dm);\n\t\tbreak;\n\n\tcase ODM_CE:\n\t\todm_txpowertracking_check_ce(dm);\n\t\tbreak;\n\n\tcase ODM_AP:\n\t\todm_txpowertracking_check_ap(dm);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid odm_txpowertracking_check_ce(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n#if (RTL8822C_SUPPORT == 1)\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tif (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))\n\t\treturn;\n\n \tif (dm->support_ic_type & ODM_RTL8814B)\n\t\treturn;\n\n\tif ((rf->power_track_type & 0xf0) >> 4 != 0) {\n\t\tif (dm->support_ic_type & ODM_RTL8822C) {\n\t\t\t/*halrf_tssi_cck(dm);*/\n\t\t\t/*halrf_thermal_cck(dm);*/\n\t\t\treturn;\n\t\t}\n\t}\n\n\tif (!dm->rf_calibrate_info.tm_trigger) {\n\t\tif (dm->support_ic_type &\n\t\t\t(ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8192E |\n\t\t\tODM_RTL8723B | ODM_RTL8812 | ODM_RTL8821 |\n\t\t\tODM_RTL8814A | ODM_RTL8703B | ODM_RTL8723D |\n\t\t\tODM_RTL8822B | ODM_RTL8821C | ODM_RTL8710B |\n\t\t\tODM_RTL8192F))\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW,\n\t\t\t\t       (BIT(17) | BIT(16)), 0x03);\n\t\telse if (dm->support_ic_type & ODM_RTL8822C) {\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);\n\t\t\t\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);\n\t\t} else\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_OLD,\n\t\t\t\t       RFREGOFFSETMASK, 0x60);\n\n\t\tdm->rf_calibrate_info.tm_trigger = 1;\n\t\treturn;\n\t}\n\t\n\tif (dm->support_ic_type & ODM_RTL8822C) {\n#if (RTL8822C_SUPPORT == 1)\n\t\todm_txpowertracking_new_callback_thermal_meter(dm);\n#endif\n\t} else\n\t\todm_txpowertracking_callback_thermal_meter(dm);\n\tdm->rf_calibrate_info.tm_trigger = 0;\n#endif\n}\n\nvoid\nodm_txpowertracking_direct_ce(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\n\tif (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))\n\t\treturn;\n\n\tif (dm->support_ic_type & ODM_RTL8814B)\n\t\treturn;\n\n\tif (dm->support_ic_type & ODM_RTL8822C) {\n\t\t/*halrf_tssi_cck(dm);*/\n\t\t/*halrf_thermal_cck(dm);*/\n\t\treturn;\n\t}\n\n\tif (dm->support_ic_type &\n\t\t(ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8192E |\n\t\tODM_RTL8723B | ODM_RTL8812 | ODM_RTL8821 |\n\t\tODM_RTL8814A | ODM_RTL8703B | ODM_RTL8723D |\n\t\tODM_RTL8822B | ODM_RTL8821C | ODM_RTL8710B |\n\t\tODM_RTL8192F))\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03);\n\telse if (dm->support_ic_type & ODM_RTL8822C) {\n\t\todm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);\n\t\todm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);\n\t\todm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);\n\t\t\t\n\t\todm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);\n\t\todm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);\n\t\todm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);\n\t} else\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_OLD, RFREGOFFSETMASK, 0x60);\n\n\todm_txpowertracking_callback_thermal_meter(dm);\n#endif\n\n}\n\n\nvoid odm_txpowertracking_check_mp(void *dm_void)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tvoid *adapter = dm->adapter;\n\n\tif (odm_check_power_status(adapter) == false) {\n\t\tRT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,\n\t\t\t (\"check_pow_status, return false\\n\"));\n\t\treturn;\n\t}\n\n\todm_txpowertracking_thermal_meter_check(adapter);\n#endif\n}\n\nvoid odm_txpowertracking_check_ap(void *dm_void)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rtl8192cd_priv *priv = dm->priv;\n\n\treturn;\n\n#endif\n}\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_powertracking_ce.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALRF_POWERTRACKING_H__\n#define __HALRF_POWERTRACKING_H__\n\n#define DPK_DELTA_MAPPING_NUM 13\n#define index_mapping_HP_NUM 15\n#define OFDM_TABLE_SIZE 43\n#define CCK_TABLE_SIZE 33\n#define CCK_TABLE_SIZE_88F 21\n#define TXSCALE_TABLE_SIZE 37\n#define CCK_TABLE_SIZE_8723D 41\n/*@JJ ADD 20161014 */\n#define CCK_TABLE_SIZE_8710B 41\n#define CCK_TABLE_SIZE_8192F 41\n\n#define TXPWR_TRACK_TABLE_SIZE 30\n#define DELTA_SWINGIDX_SIZE 30\n#define DELTA_SWINTSSI_SIZE 61\n#define BAND_NUM 4\n\n#define AVG_THERMAL_NUM 8\n#define IQK_MAC_REG_NUM 4\n#define IQK_ADDA_REG_NUM 16\n#define IQK_BB_REG_NUM_MAX 10\n\n#define IQK_BB_REG_NUM 9\n\n#define iqk_matrix_reg_num 8\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)\n#else\n/* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */\n#define IQK_MATRIX_SETTINGS_NUM (14 + 24 + 21)\n#endif\n\nextern u32 ofdm_swing_table[OFDM_TABLE_SIZE];\nextern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];\nextern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];\n\nextern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];\nextern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];\nextern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];\nextern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];\nextern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];\nextern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];\nextern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];\n/*@JJ ADD 20161014 */\nextern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];\nextern u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];\n\nextern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];\n\n/*@<20121018, Kordan> In case fail to read TxPowerTrack.txt */\n/* we use the table of 88E as the default table. */\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)\n#else\nextern u8 delta_swing_table_idx_2ga_p_8188e[];\nextern u8 delta_swing_table_idx_2ga_n_8188e[];\n#endif\n\n#define dm_check_txpowertracking odm_txpowertracking_check\n\nstruct iqk_matrix_regs_setting {\n\tboolean is_iqk_done;\n\ts32 value[3][iqk_matrix_reg_num];\n\tboolean is_bw_iqk_result_saved[3];\n};\n\nstruct dm_rf_calibration_struct {\n\t/* for tx power tracking */\n\n\tu32 rega24; /* for TempCCK */\n\ts32 rege94;\n\ts32 rege9c;\n\ts32 regeb4;\n\ts32 regebc;\n\n\tu8 tx_powercount;\n\tboolean is_txpowertracking_init;\n\tboolean is_txpowertracking;\n\t/* for mp mode, turn off txpwrtracking as default */\n\tu8 txpowertrack_control;\n\tu8 tm_trigger;\n\tu8 internal_pa_5g[2]; /* pathA / pathB */\n\n\t/* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */\n\tu8 thermal_meter[2];\n\tu8 thermal_value;\n\tu8 thermal_value_path[MAX_RF_PATH];\n\tu8 thermal_value_lck;\n\tu8 thermal_value_iqk;\n\ts8 thermal_value_delta; /* delta of thermal_value and efuse thermal */\n\tu8 thermal_value_dpk;\n\tu8 thermal_value_avg[AVG_THERMAL_NUM];\n\tu8 thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM];\n\tu8 thermal_value_avg_index;\n\tu8 thermal_value_avg_index_path[MAX_RF_PATH];\n\tu8 thermal_value_rx_gain;\n\tu8 thermal_value_crystal;\n\tu8 thermal_value_dpk_store;\n\tu8 thermal_value_dpk_track;\n\tboolean txpowertracking_in_progress;\n\n\tboolean is_reloadtxpowerindex;\n\tu8 is_rf_pi_enable;\n\tu32 txpowertracking_callback_cnt; /* cosa add for debug */\n\n\t/*@---------------------- Tx power Tracking ---------------------- */\n\tu8 is_cck_in_ch14;\n\tu8 CCK_index;\n\tu8 OFDM_index[MAX_RF_PATH];\n\ts8 power_index_offset[MAX_RF_PATH];\n\ts8 delta_power_index[MAX_RF_PATH];\n\ts8 delta_power_index_last[MAX_RF_PATH];\n\tboolean is_tx_power_changed;\n\ts8 xtal_offset;\n\ts8 xtal_offset_last;\n\tu8 xtal_offset_eanble;\n\n\tstruct iqk_matrix_regs_setting\n\t\t\t\tiqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];\n\tu8 delta_lck;\n\ts8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */\n\tu8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];\n\tu8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];\n\tu8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];\n\tu8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];\n\tu8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];\n\tu8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];\n\tu8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];\n\tu8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];\n\tu8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];\n\tu8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];\n\tu8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];\n\tu8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];\n\ts8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];\n\ts8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];\n\tu8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];\n\n\tu8 bb_swing_idx_ofdm[MAX_RF_PATH];\n\tu8 bb_swing_idx_ofdm_current;\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\tu8 bb_swing_idx_ofdm_base[MAX_RF_PATH];\n#else\n\tu8 bb_swing_idx_ofdm_base;\n#endif\n\tboolean default_bb_swing_index_flag;\n\tboolean bb_swing_flag_ofdm;\n\tu8 bb_swing_idx_cck;\n\tu8 bb_swing_idx_cck_current;\n\tu8 bb_swing_idx_cck_base;\n\tu8 default_ofdm_index;\n\tu8 default_cck_index;\n\tboolean bb_swing_flag_cck;\n\n\ts8 absolute_ofdm_swing_idx[MAX_RF_PATH];\n\ts8 remnant_ofdm_swing_idx[MAX_RF_PATH];\n\ts8 absolute_cck_swing_idx[MAX_RF_PATH];\n\ts8 remnant_cck_swing_idx;\n\ts8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */\n\tboolean modify_tx_agc_flag_path_a;\n\tboolean modify_tx_agc_flag_path_b;\n\tboolean modify_tx_agc_flag_path_c;\n\tboolean modify_tx_agc_flag_path_d;\n\tboolean modify_tx_agc_flag_path_a_cck;\n\tboolean modify_tx_agc_flag_path_b_cck;\n\n\ts8 kfree_offset[MAX_RF_PATH];\n\n\t/*@----------------------------------------------------------------- */\n\n\t/* for IQK */\n\tu32 regc04;\n\tu32 reg874;\n\tu32 regc08;\n\tu32 regb68;\n\tu32 regb6c;\n\tu32 reg870;\n\tu32 reg860;\n\tu32 reg864;\n\n\tboolean is_iqk_initialized;\n\tboolean is_lck_in_progress;\n\tboolean is_antenna_detected;\n\tboolean is_need_iqk;\n\tboolean is_iqk_in_progress;\n\tboolean is_iqk_pa_off;\n\tu8 delta_iqk;\n\tu32 ADDA_backup[IQK_ADDA_REG_NUM];\n\tu32 IQK_MAC_backup[IQK_MAC_REG_NUM];\n\tu32 IQK_BB_backup_recover[9];\n\tu32 IQK_BB_backup[IQK_BB_REG_NUM];\n\t/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */\n\tu32 tx_iqc_8723b[2][3][2];\n\t/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */\n\tu32 rx_iqc_8723b[2][2][2];\n\t/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */\n\tu32 tx_iqc_8703b[3][2];\n\t/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */\n\tu32 rx_iqc_8703b[2][2];\n\t/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */\n\tu32 tx_iqc_8723d[2][3][2];\n\t/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */\n\tu32 rx_iqc_8723d[2][2][2];\n\t/* JJ ADD 20161014 */\n\t/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */\n\tu32 tx_iqc_8710b[2][3][2];\n\t/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */\n\tu32 rx_iqc_8710b[2][2][2];\n\n\tu8 iqk_step;\n\tu8 kcount;\n\tu8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */\n\tboolean is_mp_mode;\n\n\t/*@<James> IQK time measurement */\n\tu64 iqk_start_time;\n\tu64 iqk_progressing_time;\n\tu64 iqk_total_progressing_time;\n\tu64 lck_progressing_time;\n\n\tu32 lok_result;\n\n\t/* for APK */\n\tu32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */\n\tu8 is_ap_kdone;\n\tu8 is_apk_thermal_meter_ignore;\n\n\t/* DPK */\n\tboolean is_dpk_fail;\n\tu8 is_dp_done;\n\tu8 is_dp_path_aok;\n\tu8 is_dp_path_bok;\n\n\tu32 tx_lok[2];\n\tu32 dpk_tx_agc;\n\ts32 dpk_gain;\n\tu32 dpk_thermal[4];\n\ts8 modify_tx_agc_value_ofdm;\n\ts8 modify_tx_agc_value_cck;\n\n\t/*@Add by Yuchen for Kfree Phydm*/\n\tu8 reg_rf_kfree_enable; /*for registry*/\n\tu8 rf_kfree_enable; /*for efuse enable check*/\n};\n\nvoid odm_txpowertracking_check(void *dm_void);\n\nvoid odm_txpowertracking_init(void *dm_void);\n\nvoid odm_txpowertracking_check_ap(void *dm_void);\n\nvoid odm_txpowertracking_thermal_meter_init(void *dm_void);\n\nvoid odm_txpowertracking_init(void *dm_void);\n\nvoid odm_txpowertracking_check_mp(void *dm_void);\n\nvoid odm_txpowertracking_check_ce(void *dm_void);\n\nvoid odm_txpowertracking_direct_ce(void *dm_void);\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\n\nvoid odm_txpowertracking_callback_thermal_meter92c(\n\tvoid *adapter);\n\nvoid odm_txpowertracking_callback_rx_gain_thermal_meter92d(\n\tvoid *adapter);\n\nvoid odm_txpowertracking_callback_thermal_meter92d(\n\tvoid *adapter);\n\nvoid odm_txpowertracking_direct_call92c(\n\tvoid *adapter);\n\nvoid odm_txpowertracking_thermal_meter_check(\n\tvoid *adapter);\n\n#endif\n\n#endif /*__HALRF_POWER_TRACKING_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_powertracking_iot.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*============================================================\t*/\n/* include files\t\t\t\t\t\t\t\t\t\t\t\t*/\n/*============================================================\t*/\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n/* ************************************************************\n * Global var\n * ************************************************************\n */\n\nu32\tofdm_swing_table[OFDM_TABLE_SIZE] = {\n\t0x7f8001fe,\t/* 0, +6.0dB */\n\t0x788001e2,\t/* 1, +5.5dB */\n\t0x71c001c7,\t/* 2, +5.0dB*/\n\t0x6b8001ae,\t/* 3, +4.5dB*/\n\t0x65400195,\t/* 4, +4.0dB*/\n\t0x5fc0017f,\t/* 5, +3.5dB*/\n\t0x5a400169,\t/* 6, +3.0dB*/\n\t0x55400155,\t/* 7, +2.5dB*/\n\t0x50800142,\t/* 8, +2.0dB*/\n\t0x4c000130,\t/* 9, +1.5dB*/\n\t0x47c0011f,\t/* 10, +1.0dB*/\n\t0x43c0010f,\t/* 11, +0.5dB*/\n\t0x40000100,\t/* 12, +0dB*/\n\t0x3c8000f2,\t/* 13, -0.5dB*/\n\t0x390000e4,\t/* 14, -1.0dB*/\n\t0x35c000d7,\t/* 15, -1.5dB*/\n\t0x32c000cb,\t/* 16, -2.0dB*/\n\t0x300000c0,\t/* 17, -2.5dB*/\n\t0x2d4000b5,\t/* 18, -3.0dB*/\n\t0x2ac000ab,\t/* 19, -3.5dB*/\n\t0x288000a2,\t/* 20, -4.0dB*/\n\t0x26000098,\t/* 21, -4.5dB*/\n\t0x24000090,\t/* 22, -5.0dB*/\n\t0x22000088,\t/* 23, -5.5dB*/\n\t0x20000080,\t/* 24, -6.0dB*/\n\t0x1e400079,\t/* 25, -6.5dB*/\n\t0x1c800072,\t/* 26, -7.0dB*/\n\t0x1b00006c,\t/* 27. -7.5dB*/\n\t0x19800066,\t/* 28, -8.0dB*/\n\t0x18000060,\t/* 29, -8.5dB*/\n\t0x16c0005b,\t/* 30, -9.0dB*/\n\t0x15800056,\t/* 31, -9.5dB*/\n\t0x14400051,\t/* 32, -10.0dB*/\n\t0x1300004c,\t/* 33, -10.5dB*/\n\t0x12000048,\t/* 34, -11.0dB*/\n\t0x11000044,\t/* 35, -11.5dB*/\n\t0x10000040,\t/* 36, -12.0dB*/\n};\n\nu8\tcck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {\n\t{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},\t/* 0, +0dB */\n\t{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},\t/* 1, -0.5dB */\n\t{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},\t/* 2, -1.0dB*/\n\t{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},\t/* 3, -1.5dB*/\n\t{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},\t/* 4, -2.0dB */\n\t{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},\t/* 5, -2.5dB*/\n\t{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},\t/* 6, -3.0dB*/\n\t{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},\t/* 7, -3.5dB*/\n\t{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},\t/* 8, -4.0dB */\n\t{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},\t/* 9, -4.5dB*/\n\t{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},\t/* 10, -5.0dB */\n\t{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},\t/* 11, -5.5dB*/\n\t{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},\t/* 12, -6.0dB <== default */\n\t{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},\t/* 13, -6.5dB*/\n\t{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},\t/* 14, -7.0dB */\n\t{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},\t/* 15, -7.5dB*/\n\t{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},\t/* 16, -8.0dB */\n\t{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},\t/* 17, -8.5dB*/\n\t{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},\t/* 18, -9.0dB */\n\t{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},\t/* 19, -9.5dB*/\n\t{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},\t/* 20, -10.0dB*/\n\t{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},\t/* 21, -10.5dB*/\n\t{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},\t/* 22, -11.0dB*/\n\t{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},\t/* 23, -11.5dB*/\n\t{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},\t/* 24, -12.0dB*/\n\t{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},\t/* 25, -12.5dB*/\n\t{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},\t/* 26, -13.0dB*/\n\t{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},\t/* 27, -13.5dB*/\n\t{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},\t/* 28, -14.0dB*/\n\t{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},\t/* 29, -14.5dB*/\n\t{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},\t/* 30, -15.0dB*/\n\t{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},\t/* 31, -15.5dB*/\n\t{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}\t/* 32, -16.0dB*/\n};\n\nu8\tcck_swing_table_ch14[CCK_TABLE_SIZE][8] = {\n\t{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},\t/* 0, +0dB */\n\t{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},\t/* 1, -0.5dB */\n\t{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},\t/* 2, -1.0dB */\n\t{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},\t/* 3, -1.5dB*/\n\t{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},\t/* 4, -2.0dB */\n\t{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},\t/* 5, -2.5dB*/\n\t{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},\t/* 6, -3.0dB */\n\t{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},\t/* 7, -3.5dB */\n\t{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},\t/* 8, -4.0dB */\n\t{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},\t/* 9, -4.5dB*/\n\t{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},\t/* 10, -5.0dB */\n\t{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},\t/* 11, -5.5dB*/\n\t{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},\t/* 12, -6.0dB  <== default*/\n\t{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},\t/* 13, -6.5dB */\n\t{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},\t/* 14, -7.0dB */\n\t{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},\t/* 15, -7.5dB*/\n\t{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},\t/* 16, -8.0dB */\n\t{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},\t/* 17, -8.5dB*/\n\t{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},\t/* 18, -9.0dB */\n\t{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},\t/* 19, -9.5dB*/\n\t{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},\t/* 20, -10.0dB*/\n\t{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},\t/* 21, -10.5dB*/\n\t{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},\t/* 22, -11.0dB*/\n\t{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},\t/* 23, -11.5dB*/\n\t{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},\t/* 24, -12.0dB*/\n\t{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},\t/* 25, -12.5dB*/\n\t{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},\t/* 26, -13.0dB*/\n\t{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},\t/* 27, -13.5dB*/\n\t{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 28, -14.0dB*/\n\t{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 29, -14.5dB*/\n\t{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 30, -15.0dB*/\n\t{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 31, -15.5dB*/\n\t{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}\t/* 32, -16.0dB*/\n};\n\nu32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {\n\t0x0b40002d, /* 0,  -15.0dB\t*/\n\t0x0c000030, /* 1,  -14.5dB*/\n\t0x0cc00033, /* 2,  -14.0dB*/\n\t0x0d800036, /* 3,  -13.5dB*/\n\t0x0e400039, /* 4,  -13.0dB */\n\t0x0f00003c, /* 5,  -12.5dB*/\n\t0x10000040, /* 6,  -12.0dB*/\n\t0x11000044, /* 7,  -11.5dB*/\n\t0x12000048, /* 8,  -11.0dB*/\n\t0x1300004c, /* 9,  -10.5dB*/\n\t0x14400051, /* 10, -10.0dB*/\n\t0x15800056, /* 11, -9.5dB*/\n\t0x16c0005b, /* 12, -9.0dB*/\n\t0x18000060, /* 13, -8.5dB*/\n\t0x19800066, /* 14, -8.0dB*/\n\t0x1b00006c, /* 15, -7.5dB*/\n\t0x1c800072, /* 16, -7.0dB*/\n\t0x1e400079, /* 17, -6.5dB*/\n\t0x20000080, /* 18, -6.0dB*/\n\t0x22000088, /* 19, -5.5dB*/\n\t0x24000090, /* 20, -5.0dB*/\n\t0x26000098, /* 21, -4.5dB*/\n\t0x288000a2, /* 22, -4.0dB*/\n\t0x2ac000ab, /* 23, -3.5dB*/\n\t0x2d4000b5, /* 24, -3.0dB*/\n\t0x300000c0, /* 25, -2.5dB*/\n\t0x32c000cb, /* 26, -2.0dB*/\n\t0x35c000d7, /* 27, -1.5dB*/\n\t0x390000e4, /* 28, -1.0dB*/\n\t0x3c8000f2, /* 29, -0.5dB*/\n\t0x40000100, /* 30, +0dB*/\n\t0x43c0010f, /* 31, +0.5dB*/\n\t0x47c0011f, /* 32, +1.0dB*/\n\t0x4c000130, /* 33, +1.5dB*/\n\t0x50800142, /* 34, +2.0dB*/\n\t0x55400155, /* 35, +2.5dB*/\n\t0x5a400169, /* 36, +3.0dB*/\n\t0x5fc0017f, /* 37, +3.5dB*/\n\t0x65400195, /* 38, +4.0dB*/\n\t0x6b8001ae, /* 39, +4.5dB*/\n\t0x71c001c7, /* 40, +5.0dB*/\n\t0x788001e2, /* 41, +5.5dB*/\n\t0x7f8001fe  /* 42, +6.0dB*/\n};\n\nu8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {\n\t{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/\n\t{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/\n\t{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/\n\t{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/\n\t{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/\n\t{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/\n\t{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/\n\t{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/\n\t{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/\n\t{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/\n\t{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/\n\t{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/\n\t{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/\n\t{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/\n\t{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/\n\t{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/\n\t{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/\n\t{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/\n\t{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/\n\t{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/\n\t{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/\n};\n\nu8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {\n\t{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/\n\t{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/\n\t{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/\n\t{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/\n\t{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/\n\t{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/\n\t{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/\n\t{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/\n\t{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/\n\t{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/\n\t{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/\n\t{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/\n\t{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/\n\t{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/\n\t{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/\n\t{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/\n\t{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/\n\t{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/\n\t{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/\n\t{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/\n\t{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/\n};\n\nu8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {\n\t{0x44,\t 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/\n\t{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/\n\t{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/\n\t{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\t    /*-14.5dB*/\n\t{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/\n\t{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/\n\t{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/\n\t{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/\n\t{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/\n\t{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/\n\t{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/\n\t{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/\n\t{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/\n\t{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/\n\t{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/\n\t{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/\n\t{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/\n\t{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/\n\t{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/\n\t{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/\n\t{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/\n};\n\nu8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {\n\t{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},\t/*  0, -16.0dB*/\n\t{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},\t/*   1, -15.5dB*/\n\t{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},\t/*  2, -15.0dB*/\n\t{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},\t/*   3, -14.5dB*/\n\t{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},\t/*   4, -14.0dB*/\n\t{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},\t/*   5, -13.5dB*/\n\t{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},\t/*   6, -13.0dB*/\n\t{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},\t/*   7, -12.5dB*/\n\t{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},\t/*  8, -12.0dB*/\n\t{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},\t/*   9, -11.5dB*/\n\t{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},\t/*  10, -11.0dB*/\n\t{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},\t/*  11, -10.5dB*/\n\t{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},\t/*  12, -10.0dB*/\n\t{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},\t/*  13, -9.5dB*/\n\t{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},\t/*  14, -9.0dB */\n\t{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},\t/*  15, -8.5dB*/\n\t{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},\t/*  16, -8.0dB */\n\t{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},\t/*  17, -7.5dB*/\n\t{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},\t/*  18, -7.0dB */\n\t{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},\t/*  19, -6.5dB*/\n\t{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},\t/*20, -6.0dB */\n\t{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},\t/*  21, -5.5dB*/\n\t{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},\t/* 22, -5.0dB */\n\t{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},\t/*  23, -4.5dB*/\n\t{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},\t/*  24, -4.0dB */\n\t{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},\t/*  25, -3.5dB*/\n\t{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},\t/*  26, -3.0dB*/\n\t{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},\t/*  27, -2.5dB*/\n\t{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},\t/*  28, -2.0dB */\n\t{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},\t/*  29, -1.5dB*/\n\t{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},\t/*  30, -1.0dB*/\n\t{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},\t/*  31, -0.5dB*/\n\t{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}\t/*  32, +0dB*/\n};\n\nu8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {\n\t{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},\t/*  0, -16.0dB*/\n\t{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 1, -15.5dB*/\n\t{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},\t/*  2, -15.0dB*/\n\t{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 3, -14.5dB*/\n\t{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},\t/*  4, -14.0dB*/\n\t{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},\t/*5, -13.5dB*/\n\t{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},\t/* 6, -13.0dB*/\n\t{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},\t/*  7, -12.5dB*/\n\t{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},\t/* 8, -12.0dB*/\n\t{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},\t/* 9, -11.5dB*/\n\t{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},\t/* 10, -11.0dB*/\n\t{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},\t/*11, -10.5dB*/\n\t{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},\t/* 12, -10.0dB*/\n\t{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},\t/* 13, -9.5dB*/\n\t{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},\t/*14, -9.0dB */\n\t{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},\t/* 15, -8.5dB*/\n\t{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},\t/* 16, -8.0dB */\n\t{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},\t/* 17, -7.5dB*/\n\t{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},\t/* 18, -7.0dB */\n\t{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},\t/* 19, -6.5dB */\n\t{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},\t/* 20, -6.0dB */\n\t{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},\t/* 21, -5.5dB*/\n\t{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},\t/* 22, -5.0dB */\n\t{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},\t/*23, -4.5dB*/\n\t{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},\t/* 24, -4.0dB */\n\t{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},\t/* 25, -3.5dB */\n\t{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},\t/* 26, -3.0dB */\n\t{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},\t/*27, -2.5dB*/\n\t{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},\t/* 28, -2.0dB */\n\t{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},\t/*29, -1.5dB*/\n\t{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},\t/* 30, -1.0dB */\n\t{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},\t/* 31, -0.5dB */\n\t{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}\t/* 32, +0dB\t*/\n};\n\nu32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {\n\t0x0CD,          /*0 ,    -20dB*/\n\t0x0D9,\n\t0x0E6,\n\t0x0F3,\n\t0x102,\n\t0x111,\n\t0x121,\n\t0x132,\n\t0x144,\n\t0x158,\n\t0x16C,\n\t0x182,\n\t0x198,\n\t0x1B1,\n\t0x1CA,\n\t0x1E5,\n\t0x202,\n\t0x221,\n\t0x241,\n\t0x263,\n\t0x287,\n\t0x2AE,\n\t0x2D6,\n\t0x301,\n\t0x32F,\n\t0x35F,\n\t0x392,\n\t0x3C9,\n\t0x402,\n\t0x43F,\n\t0x47F,\n\t0x4C3,\n\t0x50C,\n\t0x558,\n\t0x5A9,\n\t0x5FF,\n\t0x65A,\n\t0x6BA,\n\t0x720,\n\t0x78C,\n\t0x7FF,\n};\n\n/* JJ ADD 20161014 */\nu32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {\n\t0x0CD,          /*0 ,    -20dB*/\n\t0x0D9,\n\t0x0E6,\n\t0x0F3,\n\t0x102,\n\t0x111,\n\t0x121,\n\t0x132,\n\t0x144,\n\t0x158,\n\t0x16C,\n\t0x182,\n\t0x198,\n\t0x1B1,\n\t0x1CA,\n\t0x1E5,\n\t0x202,\n\t0x221,\n\t0x241,\n\t0x263,\n\t0x287,\n\t0x2AE,\n\t0x2D6,\n\t0x301,\n\t0x32F,\n\t0x35F,\n\t0x392,\n\t0x3C9,\n\t0x402,\n\t0x43F,\n\t0x47F,\n\t0x4C3,\n\t0x50C,\n\t0x558,\n\t0x5A9,\n\t0x5FF,\n\t0x65A,\n\t0x6BA,\n\t0x720,\n\t0x78C,\n\t0x7FF,\n};\n\n/* Winnita ADD 20171116 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/\nu32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {\n\t0x0CD,\t\t\t /*0 ,    -20dB*/\n\t0x0D9,\n\t0x0E6,\n\t0x0F3,\n\t0x102,\n\t0x111,\n\t0x121,\n\t0x132,\n\t0x144,\n\t0x158,\n\t0x16C,\n\t0x182,\n\t0x198,\n\t0x1B1,\n\t0x1CA,\n\t0x1E5,\n\t0x202,\n\t0x221,\n\t0x241,\n\t0x263,\t\t/*19*/\n\t0x287,\t\t/*20*/\n\t0x2AE,\t\t/*21*/\n\t0x2D6,\t\t/*22*/\n\t0x301,\t\t/*23*/\n\t0x32F,\t\t/*24*/\n\t0x35F,\t\t/*25*/\n\t0x392,\t\t/*26*/\n\t0x3C9,\t\t/*27*/\n\t0x402,\t\t/*28*/\n\t0x43F,\t\t/*29*/\n\t0x47F,\t\t/*30*/\n\t0x4C3,\t\t/*31*/\n\t0x50C,\t\t/*32*/\n\t0x558,\t\t/*33*/\n\t0x5A9,\t\t/*34*/\n\t0x5FF,\t\t/*35*/\n\t0x65A,\t\t/*36*/\n\t0x6BA,\n\t0x720,\n\t0x78C,\n\t0x7FF,\n};\n\n/* Winnita ADD 201805 PathA 0xAB4[10:0]*/\nu32 cck_swing_table_ch1_ch14_8721d[CCK_TABLE_SIZE_8721D] = {\n\t0x0CD,\t\t\t /*0 ,    -20dB*/\n\t0x0D9,\n\t0x0E6,\n\t0x0F3,\n\t0x102,\n\t0x111,\n\t0x121,\n\t0x132,\n\t0x144,\n\t0x158,\n\t0x16C,\n\t0x182,\n\t0x198,\n\t0x1B1,\n\t0x1CA,\n\t0x1E5,\n\t0x202,\n\t0x221,\n\t0x241,\n\t0x263,\t\t/*19*/\n\t0x287,\t\t/*20*/\n\t0x2AE,\t\t/*21*/\n\t0x2D6,\t\t/*22*/\n\t0x301,\t\t/*23*/\n\t0x32F,\t\t/*24*/\n\t0x35F,\t\t/*25*/\n\t0x392,\t\t/*26*/\n\t0x3C9,\t\t/*27*/\n\t0x402,\t\t/*28*/\n\t0x43F,\t\t/*29*/\n\t0x47F,\t\t/*30*/\n\t0x4C3,\t\t/*31*/\n\t0x50C,\t\t/*32*/\n\t0x558,\t\t/*33*/\n\t0x5A9,\t\t/*34*/\n\t0x5FF,\t\t/*35*/\n\t0x65A,\t\t/*36*/\n\t0x6BA,\n\t0x720,\n\t0x78C,\n\t0x7FF,\n};\n\nu32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {\n\t0x081, /* 0,  -12.0dB*/\n\t0x088, /* 1,  -11.5dB*/\n\t0x090, /* 2,  -11.0dB*/\n\t0x099, /* 3,  -10.5dB*/\n\t0x0A2, /* 4,  -10.0dB*/\n\t0x0AC, /* 5,  -9.5dB*/\n\t0x0B6, /* 6,  -9.0dB*/\n\t0x0C0, /*7,  -8.5dB*/\n\t0x0CC, /* 8,  -8.0dB*/\n\t0x0D8, /* 9,  -7.5dB*/\n\t0x0E5, /* 10, -7.0dB*/\n\t0x0F2, /* 11, -6.5dB*/\n\t0x101, /* 12, -6.0dB*/\n\t0x110, /* 13, -5.5dB*/\n\t0x120, /* 14, -5.0dB*/\n\t0x131, /* 15, -4.5dB*/\n\t0x143, /* 16, -4.0dB*/\n\t0x156, /* 17, -3.5dB*/\n\t0x16A, /* 18, -3.0dB*/\n\t0x180, /* 19, -2.5dB*/\n\t0x197, /* 20, -2.0dB*/\n\t0x1AF, /* 21, -1.5dB*/\n\t0x1C8, /* 22, -1.0dB*/\n\t0x1E3, /* 23, -0.5dB*/\n\t0x200, /* 24, +0  dB*/\n\t0x21E, /* 25, +0.5dB*/\n\t0x23E, /* 26, +1.0dB*/\n\t0x261, /* 27, +1.5dB*/\n\t0x285,/* 28, +2.0dB*/\n\t0x2AB, /* 29, +2.5dB*/\n\t0x2D3, /*30, +3.0dB*/\n\t0x2FE, /* 31, +3.5dB*/\n\t0x32B, /* 32, +4.0dB*/\n\t0x35C, /* 33, +4.5dB*/\n\t0x38E, /* 34, +5.0dB*/\n\t0x3C4, /* 35, +5.5dB*/\n\t0x3FE  /* 36, +6.0dB\t*/\n};\n\nvoid\nodm_txpowertracking_init(\n\tvoid\t*dm_void\n)\n{\n\tstruct dm_struct\t*dm = (struct dm_struct *)dm_void;\n\n\todm_txpowertracking_thermal_meter_init(dm);\n}\n\nu8\nget_swing_index(\n\tvoid\t*dm_void\n)\n{\n\tstruct dm_struct\t*dm = (struct dm_struct *)dm_void;\n\n\tu8\ti = 0;\n\tu32\tbb_swing;\n\tu32\tswing_table_size;\n\tu32\t*swing_table;\n\n\tif (dm->support_ic_type == ODM_RTL8195B) {\n\t\tbb_swing = odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000);\n\t\tswing_table = tx_scaling_table_jaguar;\n\t\tswing_table_size = TXSCALE_TABLE_SIZE;\n\t}\n\n\tfor (i = 0; i < swing_table_size; i++) {\n\t\tu32 table_value = swing_table[i];\n\n\t\ttable_value = table_value;\n\t\tif (bb_swing == table_value)\n\t\t\tbreak;\n\t}\n\n\treturn i;\n}\n\nu8\nget_cck_swing_index(\n\tvoid\t\t*dm_void\n)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\n\tu8\t\t\ti = 0;\n\tu32\t\t\tbb_cck_swing;\n\n\tif (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||\n\t    dm->support_ic_type == ODM_RTL8192E) {\n\t\tbb_cck_swing = odm_read_1byte(dm, 0xa22);\n\n\t\tfor (i = 0; i < CCK_TABLE_SIZE; i++) {\n\t\t\tif (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])\n\t\t\t\tbreak;\n\t\t}\n\t} else if (dm->support_ic_type == ODM_RTL8703B) {\n\t\tbb_cck_swing = odm_read_1byte(dm, 0xa22);\n\n\t\tfor (i = 0; i < CCK_TABLE_SIZE_88F; i++) {\n\t\t\tif (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn i;\n}\n\nvoid\nodm_txpowertracking_thermal_meter_init(\n\tvoid\t*dm_void\n)\n{\n\tstruct dm_struct\t*dm = (struct dm_struct *)dm_void;\n\tu8 default_swing_index = get_swing_index(dm);\n\tu8 p = 0;\n\tstruct dm_rf_calibration_struct\t*cali_info = &dm->rf_calibrate_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tif (!(*dm->mp_mode))\n\t\tcali_info->txpowertrack_control = true;\n\telse\n\t\tcali_info->txpowertrack_control = false;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"dm txpowertrack_control = %d\\n\", cali_info->txpowertrack_control);\n\n\t/* dm->rf_calibrate_info.txpowertrack_control = true; */\n\tcali_info->thermal_value = rf->eeprom_thermal;\n\tcali_info->thermal_value_iqk = rf->eeprom_thermal;\n\tcali_info->thermal_value_lck = rf->eeprom_thermal;\n\n\tif (!cali_info->default_bb_swing_index_flag) {\n\t\tif (dm->support_ic_type == ODM_RTL8195B) {\n\t\t\tcali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;\n\t\t\tcali_info->default_cck_index = 24;\n\t\t} else if (dm->support_ic_type == ODM_RTL8721D) {\n\t\t\tcali_info->default_ofdm_index = 28;\t/*OFDM: -1dB*/\n\t\t\tcali_info->default_cck_index = 28;\t/*CCK: -6dB*/\n\t\t}\n\t\tcali_info->default_bb_swing_index_flag = true;\n\t}\n\n\tcali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;\n\tcali_info->CCK_index = cali_info->default_cck_index;\n\n\tfor (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {\n\t\tcali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;\n\t\tcali_info->OFDM_index[p] = cali_info->default_ofdm_index;\n\t\tcali_info->delta_power_index[p] = 0;\n\t\tcali_info->delta_power_index_last[p] = 0;\n\t\tcali_info->power_index_offset[p] = 0;\n\t}\n\tcali_info->modify_tx_agc_value_ofdm = 0;\n\tcali_info->modify_tx_agc_value_cck = 0;\n\tcali_info->tm_trigger = 0;\n}\n\nvoid\nodm_txpowertracking_check(\n\tvoid\t*dm_void\n)\n{\n\tstruct dm_struct\t*dm = (struct dm_struct *)dm_void;\n\n\todm_txpowertracking_check_iot(dm);\n}\n\nvoid\nodm_txpowertracking_check_iot(\n\tvoid\t*dm_void\n)\n{\n\tstruct dm_struct\t*dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_\t\t*rf = &dm->rf_table;\n\n\tif (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))\n\t\treturn;\n\n\tif (!dm->rf_calibrate_info.tm_trigger) {\n\t\tif (dm->support_ic_type == ODM_RTL8195B)\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03);\n\t\telse if (dm->support_ic_type == ODM_RTL8721D)\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW,\n\t\t\t\t       (BIT(12) | BIT(11)), 0x03);\n\n\t\tdm->rf_calibrate_info.tm_trigger = 1;\n\t\treturn;\n\t}\n\todm_txpowertracking_callback_thermal_meter(dm);\n\tdm->rf_calibrate_info.tm_trigger = 0;\n}\n\nvoid\nodm_txpowertracking_check_mp(\n\tvoid\t*dm_void\n)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\tvoid\t*adapter = dm->adapter;\n\n\tif (odm_check_power_status(adapter) == false) {\n\t\tRT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, (\"check_pow_status, return false\\n\"));\n\t\treturn;\n\t}\n\n\todm_txpowertracking_thermal_meter_check(adapter);\n#endif\n}\n\nvoid\nodm_txpowertracking_check_ap(\n\tvoid\t*dm_void\n)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\tstruct rtl8192cd_priv\t*priv\t\t= dm->priv;\n\n\treturn;\n\n#endif\n}\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_powertracking_iot.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALRF_POWERTRACKING_H__\n#define __HALRF_POWERTRACKING_H__\n\n#define\t\tDPK_DELTA_MAPPING_NUM\t13\n#define\t\tindex_mapping_HP_NUM\t15\n#define\tOFDM_TABLE_SIZE\t43\n#define\tCCK_TABLE_SIZE\t\t\t33\n#define\tCCK_TABLE_SIZE_88F\t21\n#define TXSCALE_TABLE_SIZE\t\t37\n#define CCK_TABLE_SIZE_8723D\t41\n/* JJ ADD 20161014 */\n#define CCK_TABLE_SIZE_8710B\t41\n#define\tCCK_TABLE_SIZE_8192F   41\n#define\tCCK_TABLE_SIZE_8721D   41\n\n\n#define TXPWR_TRACK_TABLE_SIZE\t30\n#define DELTA_SWINGIDX_SIZE     30\n#define DELTA_SWINTSSI_SIZE     61\n#define BAND_NUM\t\t\t\t4\n\n#define AVG_THERMAL_NUM\t\t8\n#define IQK_MAC_REG_NUM\t\t4\n#define IQK_ADDA_REG_NUM\t\t16\n#define IQK_BB_REG_NUM_MAX\t10\n\n#define IQK_BB_REG_NUM\t\t9\n\n\n\n#define iqk_matrix_reg_num\t8\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)\n#else\n#define IQK_MATRIX_SETTINGS_NUM\t(14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */\n#endif\n\nextern\tu32 ofdm_swing_table[OFDM_TABLE_SIZE];\nextern\tu8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];\nextern\tu8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];\n\nextern\tu32 ofdm_swing_table_new[OFDM_TABLE_SIZE];\nextern\tu8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];\nextern\tu8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];\nextern\tu8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];\nextern\tu8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];\nextern\tu8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];\nextern\tu32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];\n/* JJ ADD 20161014 */\nextern\tu32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];\nextern\tu32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];\nextern\tu32 cck_swing_table_ch1_ch14_8721d[CCK_TABLE_SIZE_8721D];\n\nextern  u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];\n\n/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)\n#else\nstatic u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};\nstatic u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11};\n#endif\n\nvoid\nodm_txpowertracking_init(\n\tvoid\t\t*dm_void\n);\n\n#define dm_check_txpowertracking\todm_txpowertracking_check\n\nstruct iqk_matrix_regs_setting {\n\tboolean\tis_iqk_done;\n\ts32\t\tvalue[3][iqk_matrix_reg_num];\n\tboolean\tis_bw_iqk_result_saved[3];\n};\n\nstruct dm_rf_calibration_struct {\n\t/* for tx power tracking */\n\n\tu32\trega24; /* for TempCCK */\n\ts32\trege94;\n\ts32\trege9c;\n\ts32\tregeb4;\n\ts32\tregebc;\n\n\tu8\ttx_powercount;\n\tboolean is_txpowertracking_init;\n\tboolean is_txpowertracking;\n\tu8  \ttxpowertrack_control; /* for mp mode, turn off txpwrtracking as default */\n\tu8\ttm_trigger;\n\tu8  \tinternal_pa_5g[2];\t/* pathA / pathB */\n\n\tu8  \tthermal_meter[2];    /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */\n\tu8\tthermal_value;\n\tu8\tthermal_value_lck;\n\tu8\tthermal_value_iqk;\n\ts8  \tthermal_value_delta; /* delta of thermal_value and efuse thermal */\n\tu8\tthermal_value_dpk;\n\tu8\tthermal_value_avg[AVG_THERMAL_NUM];\n\tu8\tthermal_value_avg_index;\n\tu8\tthermal_value_rx_gain;\n\tu8\tthermal_value_crystal;\n\tu8\tthermal_value_dpk_store;\n\tu8\tthermal_value_dpk_track;\n\tboolean\ttxpowertracking_in_progress;\n\n\tboolean\tis_reloadtxpowerindex;\n\tu8\tis_rf_pi_enable;\n\tu32 \ttxpowertracking_callback_cnt; /* cosa add for debug */\n\n\n\t/* ------------------------- Tx power Tracking ------------------------- */\n\tu8\tis_cck_in_ch14;\n\tu8\tCCK_index;\n\tu8\tOFDM_index[MAX_RF_PATH];\n\ts8\tpower_index_offset[MAX_RF_PATH];\n\ts8\tdelta_power_index[MAX_RF_PATH];\n\ts8\tdelta_power_index_last[MAX_RF_PATH];\n\tboolean is_tx_power_changed;\n\ts8\txtal_offset;\n\ts8\txtal_offset_last;\n\n\tstruct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];\n\tu8\tdelta_lck;\n\ts8  bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */\n\tu8  delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];\n\ts8  delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];\n\ts8  delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];\n\n\tu8\t\t\tbb_swing_idx_ofdm[MAX_RF_PATH];\n\tu8\t\t\tbb_swing_idx_ofdm_current;\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))\n\tu8\t\t\tbb_swing_idx_ofdm_base[MAX_RF_PATH];\n#else\n\tu8\t\t\tbb_swing_idx_ofdm_base;\n#endif\n\tboolean\t\tdefault_bb_swing_index_flag;\n\tboolean\t\t\tbb_swing_flag_ofdm;\n\tu8\t\t\tbb_swing_idx_cck;\n\tu8\t\t\tbb_swing_idx_cck_current;\n\tu8\t\t\tbb_swing_idx_cck_base;\n\tu8\t\t\tdefault_ofdm_index;\n\tu8\t\t\tdefault_cck_index;\n\tboolean\t\t\tbb_swing_flag_cck;\n\n\ts8\t\t\tabsolute_ofdm_swing_idx[MAX_RF_PATH];\n\ts8\t\t\tremnant_ofdm_swing_idx[MAX_RF_PATH];\n\ts8\t\t\tabsolute_cck_swing_idx[MAX_RF_PATH];\n\ts8\t\t\tremnant_cck_swing_idx;\n\ts8\t\t\tmodify_tx_agc_value;       /*Remnat compensate value at tx_agc */\n\tboolean\t\t\tmodify_tx_agc_flag_path_a;\n\tboolean\t\t\tmodify_tx_agc_flag_path_b;\n\tboolean\t\t\tmodify_tx_agc_flag_path_c;\n\tboolean\t\t\tmodify_tx_agc_flag_path_d;\n\tboolean\t\t\tmodify_tx_agc_flag_path_a_cck;\n\tboolean\t\t\tmodify_tx_agc_flag_path_b_cck;\n\n\ts8\t\t\tkfree_offset[MAX_RF_PATH];\n\n\t/* -------------------------------------------------------------------- */\n\n\t/* for IQK */\n\tu32\tregc04;\n\tu32\treg874;\n\tu32\tregc08;\n\tu32\tregb68;\n\tu32\tregb6c;\n\tu32\treg870;\n\tu32\treg860;\n\tu32\treg864;\n\n\tboolean\tis_iqk_initialized;\n\tboolean is_lck_in_progress;\n\tboolean\tis_antenna_detected;\n\tboolean\tis_need_iqk;\n\tboolean\tis_iqk_in_progress;\n\tboolean is_iqk_pa_off;\n\tu8\tdelta_iqk;\n\tu32\tADDA_backup[IQK_ADDA_REG_NUM];\n\tu32\tIQK_MAC_backup[IQK_MAC_REG_NUM];\n\tu32\tIQK_BB_backup_recover[9];\n\tu32\tIQK_BB_backup[IQK_BB_REG_NUM];\n\tu32 \ttx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */\n\tu32 \trx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */\n\tu32\ttx_iqc_8703b[3][2];\t/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/\n\tu32\trx_iqc_8703b[2][2];\t/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/\n\tu32\ttx_iqc_8723d[2][3][2];\t/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/\n\tu32\trx_iqc_8723d[2][2][2];\t/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/\n\t/* JJ ADD 20161014 */\n\tu32\ttx_iqc_8710b[2][3][2];\t/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/\n\tu32\trx_iqc_8710b[2][2][2];\t/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/\n\n\tu8\tiqk_step;\n\tu8\tkcount;\n\tu8\tretry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */\n\tboolean\tis_mp_mode;\n\n\n\n\t/* <James> IQK time measurement */\n\tu32\tiqk_start_time;\n\tu32\tiqk_progressing_time;\n\tu32\tiqk_total_progressing_time;\n\tu32\tlck_progressing_time;\n\n\tu32  lok_result;\n\n\t/* for APK */\n\tu32 \tap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */\n\tu8\tis_ap_kdone;\n\tu8\tis_apk_thermal_meter_ignore;\n\n\t/* DPK */\n\tboolean is_dpk_fail;\n\tu8\tis_dp_done;\n\tu8\tis_dp_path_aok;\n\tu8\tis_dp_path_bok;\n\n\tu32\ttx_lok[2];\n\tu32  dpk_tx_agc;\n\ts32  dpk_gain;\n\tu32  dpk_thermal[4];\n\ts8 modify_tx_agc_value_ofdm;\n\ts8 modify_tx_agc_value_cck;\n\n\t/*Add by Yuchen for Kfree Phydm*/\n\tu8\t\t\treg_rf_kfree_enable;\t/*for registry*/\n\tu8\t\t\trf_kfree_enable;\t\t/*for efuse enable check*/\n\n};\n\n\nvoid\nodm_txpowertracking_check(\n\tvoid\t\t*dm_void\n);\n\nvoid\nodm_txpowertracking_check_ap(\n\tvoid\t\t*dm_void\n);\n\nvoid\nodm_txpowertracking_thermal_meter_init(\n\tvoid\t\t*dm_void\n);\n\n\nvoid\nodm_txpowertracking_check_mp(\n\tvoid\t\t*dm_void\n);\n\n\nvoid\nodm_txpowertracking_check_iot(\n\tvoid\t\t*dm_void\n);\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\n\nvoid\nodm_txpowertracking_callback_thermal_meter92c(\n\tvoid\t*adapter\n);\n\nvoid\nodm_txpowertracking_callback_rx_gain_thermal_meter92d(\n\tvoid\t*adapter\n);\n\nvoid\nodm_txpowertracking_callback_thermal_meter92d(\n\tvoid\t*adapter\n);\n\nvoid\nodm_txpowertracking_direct_call92c(\n\tvoid\t\t*adapter\n);\n\nvoid\nodm_txpowertracking_thermal_meter_check(\n\tvoid\t\t*adapter\n);\n\n#endif\n\n#endif\t/*#ifndef __HALRF_POWER_TRACKING_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_powertracking_win.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n/*============================================================\t*/\n/* include files\t\t\t\t\t\t\t\t\t\t\t\t*/\n/*============================================================\t*/\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n/* ************************************************************\n * Global var\n * ************************************************************ */\n\nu32\tofdm_swing_table[OFDM_TABLE_SIZE] = {\n\t0x7f8001fe,\t/* 0, +6.0dB */\n\t0x788001e2,\t/* 1, +5.5dB */\n\t0x71c001c7,\t/* 2, +5.0dB */\n\t0x6b8001ae,\t/* 3, +4.5dB */\n\t0x65400195,\t/* 4, +4.0dB */\n\t0x5fc0017f,\t/* 5, +3.5dB */\n\t0x5a400169,\t/* 6, +3.0dB */\n\t0x55400155,\t/* 7, +2.5dB */\n\t0x50800142,\t/* 8, +2.0dB */\n\t0x4c000130,\t/* 9, +1.5dB */\n\t0x47c0011f,\t/* 10, +1.0dB */\n\t0x43c0010f,\t/* 11, +0.5dB */\n\t0x40000100,\t/* 12, +0dB */\n\t0x3c8000f2,\t/* 13, -0.5dB */\n\t0x390000e4,\t/* 14, -1.0dB */\n\t0x35c000d7,\t/* 15, -1.5dB */\n\t0x32c000cb,\t/* 16, -2.0dB */\n\t0x300000c0,\t/* 17, -2.5dB */\n\t0x2d4000b5,\t/* 18, -3.0dB */\n\t0x2ac000ab,\t/* 19, -3.5dB */\n\t0x288000a2,\t/* 20, -4.0dB */\n\t0x26000098,\t/* 21, -4.5dB */\n\t0x24000090,\t/* 22, -5.0dB */\n\t0x22000088,\t/* 23, -5.5dB */\n\t0x20000080,\t/* 24, -6.0dB */\n\t0x1e400079,\t/* 25, -6.5dB */\n\t0x1c800072,\t/* 26, -7.0dB */\n\t0x1b00006c,\t/* 27. -7.5dB */\n\t0x19800066,\t/* 28, -8.0dB */\n\t0x18000060,\t/* 29, -8.5dB */\n\t0x16c0005b,\t/* 30, -9.0dB */\n\t0x15800056,\t/* 31, -9.5dB */\n\t0x14400051,\t/* 32, -10.0dB */\n\t0x1300004c,\t/* 33, -10.5dB */\n\t0x12000048,\t/* 34, -11.0dB */\n\t0x11000044,\t/* 35, -11.5dB */\n\t0x10000040,\t/* 36, -12.0dB */\n};\n\nu8\tcck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {\n\t{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},\t/* 0, +0dB */\n\t{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},\t/* 1, -0.5dB */\n\t{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},\t/* 2, -1.0dB */\n\t{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},\t/* 3, -1.5dB */\n\t{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},\t/* 4, -2.0dB */\n\t{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},\t/* 5, -2.5dB */\n\t{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},\t/* 6, -3.0dB */\n\t{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},\t/* 7, -3.5dB */\n\t{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},\t/* 8, -4.0dB */\n\t{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},\t/* 9, -4.5dB */\n\t{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},\t/* 10, -5.0dB */\n\t{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},\t/* 11, -5.5dB */\n\t{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},\t/* 12, -6.0dB <== default */\n\t{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},\t/* 13, -6.5dB */\n\t{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},\t/* 14, -7.0dB */\n\t{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},\t/* 15, -7.5dB */\n\t{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},\t/* 16, -8.0dB */\n\t{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},\t/* 17, -8.5dB */\n\t{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},\t/* 18, -9.0dB */\n\t{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},\t/* 19, -9.5dB */\n\t{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},\t/* 20, -10.0dB */\n\t{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},\t/* 21, -10.5dB */\n\t{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},\t/* 22, -11.0dB */\n\t{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},\t/* 23, -11.5dB */\n\t{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},\t/* 24, -12.0dB */\n\t{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},\t/* 25, -12.5dB */\n\t{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},\t/* 26, -13.0dB */\n\t{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},\t/* 27, -13.5dB */\n\t{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},\t/* 28, -14.0dB */\n\t{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},\t/* 29, -14.5dB */\n\t{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},\t/* 30, -15.0dB */\n\t{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},\t/* 31, -15.5dB */\n\t{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}\t/* 32, -16.0dB */\n};\n\n\nu8\tcck_swing_table_ch14[CCK_TABLE_SIZE][8] = {\n\t{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},\t/* 0, +0dB */\n\t{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},\t/* 1, -0.5dB */\n\t{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},\t/* 2, -1.0dB */\n\t{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},\t/* 3, -1.5dB */\n\t{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},\t/* 4, -2.0dB */\n\t{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},\t/* 5, -2.5dB */\n\t{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},\t/* 6, -3.0dB */\n\t{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},\t/* 7, -3.5dB */\n\t{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},\t/* 8, -4.0dB */\n\t{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},\t/* 9, -4.5dB */\n\t{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},\t/* 10, -5.0dB */\n\t{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},\t/* 11, -5.5dB */\n\t{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},\t/* 12, -6.0dB  <== default */\n\t{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},\t/* 13, -6.5dB */\n\t{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},\t/* 14, -7.0dB */\n\t{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},\t/* 15, -7.5dB */\n\t{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},\t/* 16, -8.0dB */\n\t{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},\t/* 17, -8.5dB */\n\t{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},\t/* 18, -9.0dB */\n\t{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},\t/* 19, -9.5dB */\n\t{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},\t/* 20, -10.0dB */\n\t{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},\t/* 21, -10.5dB */\n\t{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},\t/* 22, -11.0dB */\n\t{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},\t/* 23, -11.5dB */\n\t{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},\t/* 24, -12.0dB */\n\t{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},\t/* 25, -12.5dB */\n\t{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},\t/* 26, -13.0dB */\n\t{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},\t/* 27, -13.5dB */\n\t{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 28, -14.0dB */\n\t{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 29, -14.5dB */\n\t{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 30, -15.0dB */\n\t{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 31, -15.5dB */\n\t{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}\t/* 32, -16.0dB */\n};\n\n\nu32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {\n\t0x0b40002d, /* 0,  -15.0dB */\n\t0x0c000030, /* 1,  -14.5dB */\n\t0x0cc00033, /* 2,  -14.0dB */\n\t0x0d800036, /* 3,  -13.5dB */\n\t0x0e400039, /* 4,  -13.0dB */\n\t0x0f00003c, /* 5,  -12.5dB */\n\t0x10000040, /* 6,  -12.0dB */\n\t0x11000044, /* 7,  -11.5dB */\n\t0x12000048, /* 8,  -11.0dB */\n\t0x1300004c, /* 9,  -10.5dB */\n\t0x14400051, /* 10, -10.0dB */\n\t0x15800056, /* 11, -9.5dB */\n\t0x16c0005b, /* 12, -9.0dB */\n\t0x18000060, /* 13, -8.5dB */\n\t0x19800066, /* 14, -8.0dB */\n\t0x1b00006c, /* 15, -7.5dB */\n\t0x1c800072, /* 16, -7.0dB */\n\t0x1e400079, /* 17, -6.5dB */\n\t0x20000080, /* 18, -6.0dB */\n\t0x22000088, /* 19, -5.5dB */\n\t0x24000090, /* 20, -5.0dB */\n\t0x26000098, /* 21, -4.5dB */\n\t0x288000a2, /* 22, -4.0dB */\n\t0x2ac000ab, /* 23, -3.5dB */\n\t0x2d4000b5, /* 24, -3.0dB */\n\t0x300000c0, /* 25, -2.5dB */\n\t0x32c000cb, /* 26, -2.0dB */\n\t0x35c000d7, /* 27, -1.5dB */\n\t0x390000e4, /* 28, -1.0dB */\n\t0x3c8000f2, /* 29, -0.5dB */\n\t0x40000100, /* 30, +0dB */\n\t0x43c0010f, /* 31, +0.5dB */\n\t0x47c0011f, /* 32, +1.0dB */\n\t0x4c000130, /* 33, +1.5dB */\n\t0x50800142, /* 34, +2.0dB */\n\t0x55400155, /* 35, +2.5dB */\n\t0x5a400169, /* 36, +3.0dB */\n\t0x5fc0017f, /* 37, +3.5dB */\n\t0x65400195, /* 38, +4.0dB */\n\t0x6b8001ae, /* 39, +4.5dB */\n\t0x71c001c7, /* 40, +5.0dB */\n\t0x788001e2, /* 41, +5.5dB */\n\t0x7f8001fe  /* 42, +6.0dB */\n};\n\n\nu8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {\n\t{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/\n\t{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/\n\t{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/\n\t{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/\n\t{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/\n\t{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/\n\t{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/\n\t{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/\n\t{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/\n\t{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/\n\t{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/\n\t{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/\n\t{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/\n\t{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/\n\t{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/\n\t{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/\n\t{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/\n\t{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/\n\t{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/\n\t{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/\n\t{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/\n};\n\n\nu8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {\n\t{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/\n\t{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/\n\t{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/\n\t{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/\n\t{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/\n\t{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/\n\t{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/\n\t{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/\n\t{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/\n\t{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/\n\t{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/\n\t{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/\n\t{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/\n\t{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/\n\t{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/\n\t{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/\n\t{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/\n\t{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/\n\t{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/\n\t{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/\n\t{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/\n};\n\n\nu8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {\n\t{0x44,\t 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/\n\t{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/\n\t{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/\n\t{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\t    /*-14.5dB*/\n\t{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/\n\t{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/\n\t{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/\n\t{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/\n\t{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/\n\t{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/\n\t{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/\n\t{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/\n\t{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/\n\t{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/\n\t{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/\n\t{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/\n\t{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/\n\t{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/\n\t{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/\n\t{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/\n\t{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/\n};\n\n\nu8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {\n\t{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},\t/* 0, -16.0dB */\n\t{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},\t/* 1, -15.5dB */\n\t{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},\t/* 2, -15.0dB */\n\t{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},\t/* 3, -14.5dB */\n\t{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},\t/* 4, -14.0dB */\n\t{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},\t/* 5, -13.5dB */\n\t{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},\t/* 6, -13.0dB */\n\t{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},\t/* 7, -12.5dB */\n\t{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},\t/* 8, -12.0dB */\n\t{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},\t/* 9, -11.5dB */\n\t{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},\t/* 10, -11.0dB */\n\t{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},\t/* 11, -10.5dB */\n\t{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},\t/* 12, -10.0dB */\n\t{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},\t/* 13, -9.5dB */\n\t{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},\t/* 14, -9.0dB */\n\t{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},\t/* 15, -8.5dB */\n\t{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},\t/* 16, -8.0dB */\n\t{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},\t/* 17, -7.5dB */\n\t{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},\t/* 18, -7.0dB */\n\t{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},\t/* 19, -6.5dB */\n\t{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},\t/* 20, -6.0dB */\n\t{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},\t/* 21, -5.5dB */\n\t{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},\t/* 22, -5.0dB */\n\t{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},\t/* 23, -4.5dB */\n\t{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},\t/* 24, -4.0dB */\n\t{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},\t/* 25, -3.5dB */\n\t{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},\t/* 26, -3.0dB */\n\t{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},\t/* 27, -2.5dB */\n\t{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},\t/* 28, -2.0dB */\n\t{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},\t/* 29, -1.5dB */\n\t{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},\t/* 30, -1.0dB */\n\t{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},\t/* 31, -0.5dB */\n\t{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}\t/* 32, +0dB */\n};\n\n\nu8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {\n\t{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},\t/* 0, -16.0dB */\n\t{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 1, -15.5dB */\n\t{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 2, -15.0dB */\n\t{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 3, -14.5dB */\n\t{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},\t/* 4, -14.0dB */\n\t{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},\t/* 5, -13.5dB */\n\t{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},\t/* 6, -13.0dB */\n\t{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},\t/* 7, -12.5dB */\n\t{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},\t/* 8, -12.0dB */\n\t{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},\t/* 9, -11.5dB */\n\t{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},\t/* 10, -11.0dB */\n\t{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},\t/* 11, -10.5dB */\n\t{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},\t/* 12, -10.0dB */\n\t{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},\t/* 13, -9.5dB */\n\t{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},\t/* 14, -9.0dB */\n\t{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},\t/* 15, -8.5dB */\n\t{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},\t/* 16, -8.0dB */\n\t{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},\t/* 17, -7.5dB */\n\t{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},\t/* 18, -7.0dB */\n\t{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},\t/* 19, -6.5dB */\n\t{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},\t/* 20, -6.0dB */\n\t{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},\t/* 21, -5.5dB */\n\t{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},\t/* 22, -5.0dB */\n\t{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},\t/* 23, -4.5dB */\n\t{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},\t/* 24, -4.0dB */\n\t{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},\t/* 25, -3.5dB */\n\t{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},\t/* 26, -3.0dB */\n\t{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},\t/* 27, -2.5dB */\n\t{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},\t/* 28, -2.0dB */\n\t{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},\t/* 29, -1.5dB */\n\t{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},\t/* 30, -1.0dB */\n\t{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},\t/* 31, -0.5dB */\n\t{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}\t/* 32, +0dB */\n};\nu32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {\n\t0x0CD,\n\t0x0D9,\n\t0x0E6,\n\t0x0F3,\n\t0x102,\n\t0x111,\n\t0x121,\n\t0x132,\n\t0x144,\n\t0x158,\n\t0x16C,\n\t0x182,\n\t0x198,\n\t0x1B1,\n\t0x1CA,\n\t0x1E5,\n\t0x202,\n\t0x221,\n\t0x241,\n\t0x263,\n\t0x287,\n\t0x2AE,\n\t0x2D6,\n\t0x301,\n\t0x32F,\n\t0x35F,\n\t0x392,\n\t0x3C9,\n\t0x402,\n\t0x43F,\n\t0x47F,\n\t0x4C3,\n\t0x50C,\n\t0x558,\n\t0x5A9,\n\t0x5FF,\n\t0x65A,\n\t0x6BA,\n\t0x720,\n\t0x78C,\n\t0x7FF,\n};\n/* JJ ADD 20161014 */\nu32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {\n\t0x0CD,\t\t\t /*0 ,    -20dB*/\n\t0x0D9,\n\t0x0E6,\n\t0x0F3,\n\t0x102,\n\t0x111,\n\t0x121,\n\t0x132,\n\t0x144,\n\t0x158,\n\t0x16C,\n\t0x182,\n\t0x198,\n\t0x1B1,\n\t0x1CA,\n\t0x1E5,\n\t0x202,\n\t0x221,\n\t0x241,\n\t0x263,\t\t/*19*/\n\t0x287,\t\t/*20*/\n\t0x2AE,\t\t/*21*/\n\t0x2D6,\t\t/*22*/\n\t0x301,\t\t/*23*/\n\t0x32F,\t\t/*24*/\n\t0x35F,\t\t/*25*/\n\t0x392,\t\t/*26*/\n\t0x3C9,\t\t/*27*/\n\t0x402,\t\t/*28*/\n\t0x43F,\t\t/*29*/\n\t0x47F,\t\t/*30*/\n\t0x4C3,\t\t/*31*/\n\t0x50C,\t\t/*32*/\n\t0x558,\t\t/*33*/\n\t0x5A9,\t\t/*34*/\n\t0x5FF,\t\t/*35*/\n\t0x65A,\t\t/*36*/\n\t0x6BA,\n\t0x720,\n\t0x78C,\n\t0x7FF,\n};\n\n/* Winnita ADD 20170828 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/\nu32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {\n\t0x0CD,\t\t\t /*0 ,    -20dB*/\n\t0x0D9,\n\t0x0E6,\n\t0x0F3,\n\t0x102,\n\t0x111,\n\t0x121,\n\t0x132,\n\t0x144,\n\t0x158,\n\t0x16C,\n\t0x182,\n\t0x198,\n\t0x1B1,\n\t0x1CA,\n\t0x1E5,\n\t0x202,\n\t0x221,\n\t0x241,\n\t0x263,\t\t/*19*/\n\t0x287,\t\t/*20*/\n\t0x2AE,\t\t/*21*/\n\t0x2D6,\t\t/*22*/\n\t0x301,\t\t/*23*/\n\t0x32F,\t\t/*24*/\n\t0x35F,\t\t/*25*/\n\t0x392,\t\t/*26*/\n\t0x3C9,\t\t/*27*/\n\t0x402,\t\t/*28*/\n\t0x43F,\t\t/*29*/\n\t0x47F,\t\t/*30*/\n\t0x4C3,\t\t/*31*/\n\t0x50C,\t\t/*32*/\n\t0x558,\t\t/*33*/\n\t0x5A9,\t\t/*34*/\n\t0x5FF,\t\t/*35*/\n\t0x65A,\t\t/*36*/\n\t0x6BA,\n\t0x720,\n\t0x78C,\n\t0x7FF,\n};\n\nu32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {\n\t0x081, /* 0,  -12.0dB */\n\t0x088, /* 1,  -11.5dB */\n\t0x090, /* 2,  -11.0dB */\n\t0x099, /* 3,  -10.5dB */\n\t0x0A2, /* 4,  -10.0dB */\n\t0x0AC, /* 5,  -9.5dB */\n\t0x0B6, /* 6,  -9.0dB */\n\t0x0C0, /* 7,  -8.5dB */\n\t0x0CC, /* 8,  -8.0dB */\n\t0x0D8, /* 9,  -7.5dB */\n\t0x0E5, /* 10, -7.0dB */\n\t0x0F2, /* 11, -6.5dB */\n\t0x101, /* 12, -6.0dB */\n\t0x110, /* 13, -5.5dB */\n\t0x120, /* 14, -5.0dB */\n\t0x131, /* 15, -4.5dB */\n\t0x143, /* 16, -4.0dB */\n\t0x156, /* 17, -3.5dB */\n\t0x16A, /* 18, -3.0dB */\n\t0x180, /* 19, -2.5dB */\n\t0x197, /* 20, -2.0dB */\n\t0x1AF, /* 21, -1.5dB */\n\t0x1C8, /* 22, -1.0dB */\n\t0x1E3, /* 23, -0.5dB */\n\t0x200, /* 24, +0  dB */\n\t0x21E, /* 25, +0.5dB */\n\t0x23E, /* 26, +1.0dB */\n\t0x261, /* 27, +1.5dB */\n\t0x285, /* 28, +2.0dB */\n\t0x2AB, /* 29, +2.5dB */\n\t0x2D3, /* 30, +3.0dB */\n\t0x2FE, /* 31, +3.5dB */\n\t0x32B, /* 32, +4.0dB */\n\t0x35C, /* 33, +4.5dB */\n\t0x38E, /* 34, +5.0dB */\n\t0x3C4, /* 35, +5.5dB */\n\t0x3FE  /* 36, +6.0dB */\n};\n\nvoid\nodm_txpowertracking_init(\n\tvoid\t\t*dm_void\n)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tif (!(dm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B)))\n\t\treturn;\n#endif\n\n\todm_txpowertracking_thermal_meter_init(dm);\n}\n\nu8\nget_swing_index(\n\tvoid\t\t*dm_void\n)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\tvoid\t\t*adapter = dm->adapter;\n\tHAL_DATA_TYPE\t*hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tu8\t\t\ti = 0;\n\tu32\t\t\tbb_swing, table_value;\n\n\tif (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||\n\t    dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8188F || \n\t    dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || \n\t    dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8710B ||\n\t    dm->support_ic_type == ODM_RTL8821) {\n\t\tbb_swing = odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000);\n\n\t\tfor (i = 0; i < OFDM_TABLE_SIZE; i++) {\n\t\t\ttable_value = ofdm_swing_table_new[i];\n\n\t\t\tif (table_value >= 0x100000)\n\t\t\t\ttable_value >>= 22;\n\t\t\tif (bb_swing == table_value)\n\t\t\t\tbreak;\n\t\t}\n\t} else {\n\t\tbb_swing = PHY_GetTxBBSwing_8812A(adapter, hal_data->CurrentBandType, RF_PATH_A);\n\n\t\tfor (i = 0; i < TXSCALE_TABLE_SIZE; i++) {\n\t\t\ttable_value = tx_scaling_table_jaguar[i];\n\n\t\t\tif (bb_swing == table_value)\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn i;\n}\n\nu8\nget_cck_swing_index(\n\tvoid\t\t*dm_void\n)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\n\tu8\t\t\ti = 0;\n\tu32\t\t\tbb_cck_swing;\n\n\tif (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||\n\t    dm->support_ic_type == ODM_RTL8192E) {\n\t\tbb_cck_swing = odm_read_1byte(dm, 0xa22);\n\n\t\tfor (i = 0; i < CCK_TABLE_SIZE; i++) {\n\t\t\tif (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])\n\t\t\t\tbreak;\n\t\t}\n\t} else if (dm->support_ic_type == ODM_RTL8703B) {\n\t\tbb_cck_swing = odm_read_1byte(dm, 0xa22);\n\n\t\tfor (i = 0; i < CCK_TABLE_SIZE_88F; i++) {\n\t\t\tif (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn i;\n}\n\n\nvoid\nodm_txpowertracking_thermal_meter_init(\n\tvoid\t\t*dm_void\n)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\tu8 default_swing_index = get_swing_index(dm);\n\tu8 default_cck_swing_index = get_cck_swing_index(dm);\n\tstruct dm_rf_calibration_struct\t*cali_info = &(dm->rf_calibrate_info);\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n#if (RTL8822C_SUPPORT == 1)\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid\t\t*adapter = dm->adapter;\n\tHAL_DATA_TYPE\t*hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tu8\t\t\tp = 0;\n\n\tif (*(dm->mp_mode) == false)\n\t\tcali_info->txpowertrack_control = true;\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n#ifdef CONFIG_RTL8188E\n\t{\n\t\tcali_info->is_txpowertracking = true;\n\t\tcali_info->tx_powercount = 0;\n\t\tcali_info->is_txpowertracking_init = false;\n\n\t\tif (*(dm->mp_mode) == false)\n\t\t\tcali_info->txpowertrack_control = true;\n\n\t\tMSG_8192C(\"dm txpowertrack_control = %d\\n\", cali_info->txpowertrack_control);\n\t}\n#else\n\t{\n\t\tvoid\t\t*adapter = dm->adapter;\n\t\tHAL_DATA_TYPE\t*hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\t\tstruct dm_priv\t*pdmpriv = &hal_data->dmpriv;\n\n\t\tpdmpriv->is_txpowertracking = true;\n\t\tpdmpriv->tx_powercount = 0;\n\t\tpdmpriv->is_txpowertracking_init = false;\n\n\t\tif (*(dm->mp_mode) == false)\n\t\t\tpdmpriv->txpowertrack_control = true;\n\n\t\tMSG_8192C(\"pdmpriv->txpowertrack_control = %d\\n\", pdmpriv->txpowertrack_control);\n\n\t}\n#endif\n#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n#ifdef RTL8188E_SUPPORT\n\t{\n\t\tcali_info->is_txpowertracking = true;\n\t\tcali_info->tx_powercount = 0;\n\t\tcali_info->is_txpowertracking_init = false;\n\t\tcali_info->txpowertrack_control = true;\n\t}\n#endif\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#if (MP_DRIVER == 1)\n\tcali_info->txpowertrack_control = false;\n#else\n\tcali_info->txpowertrack_control = true;\n#endif\n#else\n\tcali_info->txpowertrack_control = true;\n#endif\n\n\tcali_info->thermal_value\t= hal_data->eeprom_thermal_meter;\n\tcali_info->thermal_value_iqk\t= hal_data->eeprom_thermal_meter;\n\tcali_info->thermal_value_lck\t= hal_data->eeprom_thermal_meter;\n\n#if (RTL8822C_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8822C) {\n\t\tcali_info->thermal_value_path[RF_PATH_A] = tssi->thermal[RF_PATH_A];\n\t\tcali_info->thermal_value_path[RF_PATH_B] = tssi->thermal[RF_PATH_B];\n\t\tcali_info->thermal_value_iqk = tssi->thermal[RF_PATH_A];\n\t\tcali_info->thermal_value_lck = tssi->thermal[RF_PATH_A];\n\t}\n#endif\n\n\tif (cali_info->default_bb_swing_index_flag != true) {\n\t\t/*The index of \"0 dB\" in SwingTable.*/\n\t\tif (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||\n\t\t    dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8703B ||\n\t\t    dm->support_ic_type == ODM_RTL8821) {\n\t\t\tcali_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index;\n\t\t\tcali_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index;\n\t\t} else if (dm->support_ic_type == ODM_RTL8188F) {          /*add by Mingzhi.Guo  2015-03-23*/\n\t\t\tcali_info->default_ofdm_index = 28;\t\t\t\t\t\t\t/*OFDM: -1dB*/\n\t\t\tcali_info->default_cck_index = 20;\t\t\t\t\t\t\t/*CCK:-6dB*/\n\t\t} else if (dm->support_ic_type == ODM_RTL8723D) {\t\t\t /*add by zhaohe  2015-10-27*/\n\t\t\tcali_info->default_ofdm_index = 28;\t\t\t\t\t\t \t   /*OFDM: -1dB*/\n\t\t\tcali_info->default_cck_index = 28;\t\t\t\t\t\t\t/*CCK:   -6dB*/\n\t\t\t/* JJ ADD 20161014 */\n\t\t} else if (dm->support_ic_type == ODM_RTL8710B) {\t\t\t\n\t\t\tcali_info->default_ofdm_index = 28;\t\t\t\t\t/*OFDM: -1dB*/\n\t\t\tcali_info->default_cck_index = 28;\t\t\t\t\t/*CCK:   -6dB*/\n\t\t/*Winnita add 20170828*/\n\t\t} else if (dm->support_ic_type == ODM_RTL8192F) {\t\t\t\n\t\t\tcali_info->default_ofdm_index = 30;\t\t\t\t\t/*OFDM: 0dB*/\n\t\t\tcali_info->default_cck_index = 28;\t\t\t\t\t/*CCK:   -6dB*/\n\t\t} else {\n\t\t\tcali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;\n\t\t\tcali_info->default_cck_index = 24;\n\t\t}\n\t\tcali_info->default_bb_swing_index_flag = true;\n\t}\n\n\tcali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;\n\tcali_info->CCK_index = cali_info->default_cck_index;\n\n\tfor (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {\n\t\tcali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;\n\t\tcali_info->OFDM_index[p] = cali_info->default_ofdm_index;\n\t\tcali_info->delta_power_index[p] = 0;\n\t\tcali_info->delta_power_index_last[p] = 0;\n\t\tcali_info->power_index_offset[p] = 0;\n\t\tcali_info->kfree_offset[p] = 0;\n\t}\n\tcali_info->modify_tx_agc_value_ofdm = 0;\n\tcali_info->modify_tx_agc_value_cck = 0;\n\tcali_info->tm_trigger = 0;\n}\n\n\nvoid\nodm_txpowertracking_check(\n\tvoid\t\t*dm_void\n)\n{\n\n#if 0\n\t/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */\n\t/*  at the same time. In the stage2/3, we need to prive universal interface and merge all */\n\t/* HW dynamic mechanism. */\n#endif\n\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\tswitch\t(dm->support_platform) {\n\tcase\tODM_WIN:\n\t\todm_txpowertracking_check_mp(dm);\n\t\tbreak;\n\n\tcase\tODM_CE:\n\t\todm_txpowertracking_check_ce(dm);\n\t\tbreak;\n\n\tcase\tODM_AP:\n\t\todm_txpowertracking_check_ap(dm);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n}\n\nvoid\nodm_txpowertracking_check_ce(\n\tvoid\t\t*dm_void\n)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_\t\t\t\t*rf = &(dm->rf_table);\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tvoid\t*adapter = dm->adapter;\n#if ((RTL8188F_SUPPORT == 1))\n\trtl8192c_odm_check_txpowertracking(adapter);\n#endif\n\n#if (RTL8188E_SUPPORT == 1)\n\n\tif (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))\n\t\treturn;\n\n\tif (!cali_info->tm_trigger) {\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);\n\t\t/*DBG_8192C(\"Trigger 92C Thermal Meter!!\\n\");*/\n\n\t\tcali_info->tm_trigger = 1;\n\t\treturn;\n\n\t} else {\n\t\t/*DBG_8192C(\"Schedule TxPowerTracking direct call!!\\n\");*/\n\t\todm_txpowertracking_callback_thermal_meter_8188e(adapter);\n\t\tcali_info->tm_trigger = 0;\n\t}\n#endif\n#endif\n}\n\nvoid\nodm_txpowertracking_check_mp(\n\tvoid\t\t*dm_void\n)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid\t*adapter = dm->adapter;\n\n\tif (*dm->is_fcs_mode_enable)\n\t\treturn;\n\n\tif (odm_check_power_status(dm) == false) {\n\t\tRT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, (\"check_pow_status return false\\n\"));\n\t\treturn;\n\t}\n\n\tif (IS_HARDWARE_TYPE_8821B(adapter)) /* TODO: Don't Do PowerTracking*/\n\t\treturn;\n\n\todm_txpowertracking_thermal_meter_check(adapter);\n\n\n#endif\n\n}\n\n\nvoid\nodm_txpowertracking_check_ap(\n\tvoid\t\t*dm_void\n)\n{\n\treturn;\n\n}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\nvoid\nodm_txpowertracking_direct_call(\n\tvoid\t\t*adapter\n)\n{\n\tHAL_DATA_TYPE\t\t*hal_data\t= GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct\t\t\t*dm = &hal_data->DM_OutSrc;\n\n\tif (dm->support_ic_type & ODM_RTL8822C) {\n#if (RTL8822C_SUPPORT == 1)\n\t\todm_txpowertracking_new_callback_thermal_meter(dm);\n#endif\n\t} else\n\t\todm_txpowertracking_callback_thermal_meter(adapter);\n}\n\nvoid\nodm_txpowertracking_thermal_meter_check(\n\tvoid\t\t*adapter\n)\n{\n\tstatic u8\t\t\ttm_trigger = 0;\n\tHAL_DATA_TYPE\t\t\t*pHalData = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct\t*dm = &(pHalData->DM_OutSrc);\n\tstruct _hal_rf_\t\t\t*rf = &(dm->rf_table);\n\n\tif (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) {\n\t\tRT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,\n\t\t\t(\"===>odm_txpowertracking_thermal_meter_check(),mgnt_info->is_txpowertracking is false, return!!\\n\"));\n\t\treturn;\n\t}\n\n\tif (rf->power_track_type != 0) {\n\t\tif (IS_HARDWARE_TYPE_8822C(adapter)) {\n\t\t\t/*halrf_tssi_cck(dm);*/\n\t\t\t/*halrf_thermal_cck(dm);*/\n\t\t\treturn;\n\t\t}\n\t}\n\n\tif (!tm_trigger) {\n\t\tif (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8192E(adapter) || IS_HARDWARE_TYPE_8192F(adapter)\n\t\t    ||IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8703B(adapter)\n\t\t    || IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8821C(adapter) || IS_HARDWARE_TYPE_8710B(adapter)\n\t\t    || IS_HARDWARE_TYPE_8814B(adapter))/* JJ ADD 20161014 */\n\t\t\tPHY_SetRFReg(adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);\n\t\telse if (IS_HARDWARE_TYPE_8822C(adapter)) {\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);\n\t\t\t\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);\n\t\t}\n\t\telse\n\t\t\tPHY_SetRFReg(adapter, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);\n\n\t\tRT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, (\"Trigger Thermal Meter!!\\n\"));\n\n\t\ttm_trigger = 1;\n\t\treturn;\n\t} else {\n\t\tRT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, (\"Schedule TxPowerTracking direct call!!\\n\"));\n\t\todm_txpowertracking_direct_call(adapter);\n\t\ttm_trigger = 0;\n\t}\n}\n\n#endif\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_powertracking_win.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef __HALRF_POWERTRACKING_H__\n#define __HALRF_POWERTRACKING_H__\n\n#define\tDPK_DELTA_MAPPING_NUM\t13\n#define\tindex_mapping_HP_NUM\t15\n#define\tTXSCALE_TABLE_SIZE\t\t37\n#define\tOFDM_TABLE_SIZE\t\t\t43\n#define\tCCK_TABLE_SIZE\t\t\t33\n#define\tCCK_TABLE_SIZE_8723D    41\n#define\tTXPWR_TRACK_TABLE_SIZE\t30\n#define\tDELTA_SWINGIDX_SIZE     30\n#define\tDELTA_SWINTSSI_SIZE     61\n#define\tBAND_NUM\t\t\t\t3\n#define\tMAX_RF_PATH\t4\n#define\tCCK_TABLE_SIZE_88F\t21\n/* JJ ADD 20161014 */\n#define\tCCK_TABLE_SIZE_8710B   41\n#define\tCCK_TABLE_SIZE_8192F   41\n\n\n#define\tdm_check_txpowertracking\todm_txpowertracking_check\n\n#define IQK_MATRIX_SETTINGS_NUM\t(14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */\n#define\tAVG_THERMAL_NUM\t\t8\n#define\tiqk_matrix_reg_num\t8\n#define\tIQK_MAC_REG_NUM\t\t4\n#define\tIQK_ADDA_REG_NUM\t\t16\n\n#define\tIQK_BB_REG_NUM\t\t9\n\n\nextern\tu32 ofdm_swing_table[OFDM_TABLE_SIZE];\nextern\tu8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];\nextern\tu8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];\n\nextern\tu32 ofdm_swing_table_new[OFDM_TABLE_SIZE];\nextern\tu8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];\nextern\tu8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];\nextern\tu8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];\nextern\tu8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];\nextern\tu8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];\nextern\tu32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];\n/* JJ ADD 20161014 */\nextern\tu32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];\nextern\tu32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];\n\nextern  u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];\n\n/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */\nstatic u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};\nstatic u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11};\n\nvoid\nodm_txpowertracking_check(\n\tvoid\t\t*dm_void\n);\n\nvoid\nodm_txpowertracking_check_ap(\n\tvoid\t\t*dm_void\n);\n\nvoid\nodm_txpowertracking_thermal_meter_init(\n\tvoid\t\t*dm_void\n);\n\nvoid\nodm_txpowertracking_init(\n\tvoid\t\t*dm_void\n);\n\nvoid\nodm_txpowertracking_check_mp(\n\tvoid\t\t*dm_void\n);\n\n\nvoid\nodm_txpowertracking_check_ce(\n\tvoid\t\t*dm_void\n);\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\n\n\nvoid\nodm_txpowertracking_thermal_meter_check(\n\tvoid\t\t*adapter\n);\n\n#endif\n\nstruct iqk_matrix_regs_setting {\n\tboolean\tis_iqk_done;\n\ts32\t\tvalue[3][iqk_matrix_reg_num];\n\tboolean\tis_bw_iqk_result_saved[3];\n};\n\nstruct dm_rf_calibration_struct {\n\t/* for tx power tracking */\n\n\tu32\trega24; /* for TempCCK */\n\ts32\trege94;\n\ts32\trege9c;\n\ts32\tregeb4;\n\ts32\tregebc;\n\t/* u8 is_txpowertracking; */\n\tu8\ttx_powercount;\n\tboolean is_txpowertracking_init;\n\tboolean is_txpowertracking;\n\tu8  \ttxpowertrack_control; /* for mp mode, turn off txpwrtracking as default */\n\tu8\ttm_trigger;\n\tu8  \tinternal_pa_5g[2];\t/* pathA / pathB */\n\n\tu8  \tthermal_meter[2];    /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */\n\tu8\tthermal_value;\n\tu8\tthermal_value_path[MAX_RF_PATH];\n\tu8\tthermal_value_lck;\n\tu8\tthermal_value_iqk;\n\tu8\tthermal_value_dpk;\n\ts8\tthermal_value_delta; /* delta of thermal_value and efuse thermal */\n\tu8\tthermal_value_avg[AVG_THERMAL_NUM];\n\tu8\tthermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM];\n\tu8\tthermal_value_avg_index;\n\tu8\tthermal_value_avg_index_path[MAX_RF_PATH];\n\tu8\tthermal_value_rx_gain;\n\n\n\tboolean\tis_reloadtxpowerindex;\n\tu8\tis_rf_pi_enable;\n\tu32 \ttxpowertracking_callback_cnt; /* cosa add for debug */\n\n\n\t/* ------------------------- Tx power Tracking ------------------------- */\n\tu8\tis_cck_in_ch14;\n\tu8\tCCK_index;\n\tu8\tOFDM_index[MAX_RF_PATH];\n\ts8\tpower_index_offset[MAX_RF_PATH];\n\ts8\tdelta_power_index[MAX_RF_PATH];\n\ts8\tdelta_power_index_last[MAX_RF_PATH];\n\tboolean is_tx_power_changed;\n\ts8\txtal_offset;\n\ts8\txtal_offset_last;\n\n\tstruct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];\n\tu8\tdelta_lck;\n\ts8  bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */\n\tu8  delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];\n\tu8  delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];\n\ts8  delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];\n\ts8  delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];\n\tu8  delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];\n\n\tu8\t\t\tbb_swing_idx_ofdm[MAX_RF_PATH];\n\tu8\t\t\tbb_swing_idx_ofdm_current;\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\tu8\t\t\tbb_swing_idx_ofdm_base[MAX_RF_PATH];\n#else\n\tu8\t\t\tbb_swing_idx_ofdm_base;\n#endif\n\tboolean\t\tdefault_bb_swing_index_flag;\n\tboolean\t\t\tbb_swing_flag_ofdm;\n\tu8\t\t\tbb_swing_idx_cck;\n\tu8\t\t\tbb_swing_idx_cck_current;\n\tu8\t\t\tbb_swing_idx_cck_base;\n\tu8\t\t\tdefault_ofdm_index;\n\tu8\t\t\tdefault_cck_index;\n\tboolean\t\t\tbb_swing_flag_cck;\n\n\ts8\t\t\tabsolute_ofdm_swing_idx[MAX_RF_PATH];\n\ts8\t\t\tremnant_ofdm_swing_idx[MAX_RF_PATH];\n\ts8\t\t\tabsolute_cck_swing_idx[MAX_RF_PATH];\n\ts8\t\t\tremnant_cck_swing_idx;\n\ts8\t\t\tmodify_tx_agc_value;       /*Remnat compensate value at tx_agc */\n\tboolean\t\t\tmodify_tx_agc_flag_path_a;\n\tboolean\t\t\tmodify_tx_agc_flag_path_b;\n\tboolean\t\t\tmodify_tx_agc_flag_path_c;\n\tboolean\t\t\tmodify_tx_agc_flag_path_d;\n\tboolean\t\t\tmodify_tx_agc_flag_path_a_cck;\n\tboolean\t\t\tmodify_tx_agc_flag_path_b_cck;\n\n\ts8\t\t\tkfree_offset[MAX_RF_PATH];\n\n\t/* -------------------------------------------------------------------- */\n\n\t/* for IQK */\n\tu32\tregc04;\n\tu32\treg874;\n\tu32\tregc08;\n\tu32\tregb68;\n\tu32\tregb6c;\n\tu32\treg870;\n\tu32\treg860;\n\tu32\treg864;\n\n\tboolean\tis_iqk_initialized;\n\tboolean is_lck_in_progress;\n\tboolean\tis_antenna_detected;\n\tboolean\tis_need_iqk;\n\tboolean\tis_iqk_in_progress;\n\tboolean\tis_iqk_pa_off;\n\tu8\tdelta_iqk;\n\tu32\tADDA_backup[IQK_ADDA_REG_NUM];\n\tu32\tIQK_MAC_backup[IQK_MAC_REG_NUM];\n\tu32\tIQK_BB_backup_recover[9];\n\tu32\tIQK_BB_backup[IQK_BB_REG_NUM];\n\tu32\ttx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */\n\tu32\trx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */\n\tu32\ttx_iqc_8703b[3][2];\t/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/\n\tu32\trx_iqc_8703b[2][2];\t/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/\n\tu32\ttx_iqc_8723d[2][3][2];\t/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/\n\tu32\trx_iqc_8723d[2][2][2];\t/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/\n\t/* JJ ADD 20161014 */\n\tu32\ttx_iqc_8710b[2][3][2];\t/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/\n\tu32\trx_iqc_8710b[2][2][2];\t/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/\n\n\tu64\tiqk_start_time;\n\tu64\tiqk_total_progressing_time;\n\tu64\tiqk_progressing_time;\n\tu64\tlck_progressing_time;\n\tu32  lok_result;\n\tu8\tiqk_step;\n\tu8\tkcount;\n\tu8\tretry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */\n\tboolean\tis_mp_mode;\n\n\t/* for APK */\n\tu32 \tap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */\n\tu8\tis_ap_kdone;\n\tu8\tis_apk_thermal_meter_ignore;\n\n\t/* DPK */\n\tboolean is_dpk_fail;\n\tu8\tis_dp_done;\n\tu8\tis_dp_path_aok;\n\tu8\tis_dp_path_bok;\n\n\tu32\ttx_lok[2];\n\tu32  dpk_tx_agc;\n\ts32  dpk_gain;\n\tu32  dpk_thermal[4];\n\n\ts8 modify_tx_agc_value_ofdm;\n\ts8 modify_tx_agc_value_cck;\n\n\t/*Add by Yuchen for Kfree Phydm*/\n\tu8\t\t\treg_rf_kfree_enable;\t/*for registry*/\n\tu8\t\t\trf_kfree_enable;\t\t/*for efuse enable check*/\n};\n\n\n\n\n#endif\t/*#ifndef __HALRF_POWER_TRACKING_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_psd.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n/*@===========================================================\n * include files\n *============================================================\n */\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\nu64 _sqrt(u64 x)\n{\n\tu64 i = 0;\n\tu64 j = (x >> 1) + 1;\n\n\twhile (i <= j) {\n\t\tu64 mid = (i + j) >> 1;\n\n\t\tu64 sq = mid * mid;\n\n\t\tif (sq == x)\n\t\t\treturn mid;\n\t\telse if (sq < x)\n\t\t\ti = mid + 1;\n\t\telse\n\t\t\tj = mid - 1;\n\t}\n\n\treturn j;\n}\n\nu32 halrf_get_psd_data(\n\tstruct dm_struct *dm,\n\tu32 point)\n{\n\tstruct _hal_rf_ *rf = &(dm->rf_table);\n\tstruct _halrf_psd_data *psd = &(rf->halrf_psd_data);\n\tu32 psd_val = 0, psd_reg, psd_report, psd_point, psd_start, i, delay_time = 0;\n\n#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)\n\tif (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) {\n\t\tif (psd->average == 0)\n\t\t\tdelay_time = 100;\n\t\telse\n\t\t\tdelay_time = 0;\n\t}\n#endif\n#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)\n\tif (dm->support_interface == ODM_ITRF_PCIE) {\n\t\tif (psd->average == 0)\n\t\t\tdelay_time = 1000;\n\t\telse\n\t\t\tdelay_time = 100;\n\t}\n#endif\n\n\tif (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {\n\t\tpsd_reg = R_0x910;\n\t\tpsd_report = R_0xf44;\n\t} else {\n\t\tpsd_reg = R_0x808;\n\t\tpsd_report = R_0x8b4;\n\t}\n\n\tif (dm->support_ic_type & ODM_RTL8710B) {\n\t\tpsd_point = 0xeffffc00;\n\t\tpsd_start = 0x10000000;\n\t} else {\n\t\tpsd_point = 0xffbffc00;\n\t\tpsd_start = 0x00400000;\n\t}\n\n\tpsd_val = odm_get_bb_reg(dm, psd_reg, MASKDWORD);\n\n\tpsd_val &= psd_point;\n\tpsd_val |= point;\n\n\todm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);\n\n\tpsd_val |= psd_start;\n\n\todm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);\n\n\tfor (i = 0; i < delay_time; i++)\n\t\tODM_delay_us(1);\n\n\tpsd_val = odm_get_bb_reg(dm, psd_report, MASKDWORD);\n\n\tif (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8710B)) {\n\t\tpsd_val &= MASKL3BYTES;\n\t\tpsd_val = psd_val / 32;\n\t} else {\n\t\tpsd_val &= MASKLWORD;\n\t}\n\n\treturn psd_val;\n}\n\nvoid halrf_psd(\n\tstruct dm_struct *dm,\n\tu32 point,\n\tu32 start_point,\n\tu32 stop_point,\n\tu32 average)\n{\n\tstruct _hal_rf_ *rf = &(dm->rf_table);\n\tstruct _halrf_psd_data *psd = &(rf->halrf_psd_data);\n\n\tu32 i = 0, j = 0, k = 0;\n\tu32 psd_reg, avg_org, point_temp, average_tmp, mode;\n\tu64 data_tatal = 0, data_temp[64] = {0};\n\n\tpsd->buf_size = 256;\n\n\tmode = average >> 16;\n\t\n\tif (mode == 2)\n\t\taverage_tmp = 1;\n\telse\n\t\taverage_tmp = average & 0xffff;\n\n\tif (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))\n\t\tpsd_reg = R_0x910;\n\telse\n\t\tpsd_reg = R_0x808;\n\n#if 0\n\tdbg_print(\"[PSD]point=%d, start_point=%d, stop_point=%d, average=%d, average_tmp=%d, buf_size=%d\\n\",\n\t\tpoint, start_point, stop_point, average, average_tmp, psd->buf_size);\n#endif\n\n\tfor (i = 0; i < psd->buf_size; i++)\n\t\tpsd->psd_data[i] = 0;\n\n\tif (dm->support_ic_type & ODM_RTL8710B)\n\t\tavg_org = odm_get_bb_reg(dm, psd_reg, 0x30000);\n\telse\n\t\tavg_org = odm_get_bb_reg(dm, psd_reg, 0x3000);\n\n\tif (mode == 1) {\n\t\tif (dm->support_ic_type & ODM_RTL8710B)\n\t\t\todm_set_bb_reg(dm, psd_reg, 0x30000, 0x1);\n\t\telse\n\t\t\todm_set_bb_reg(dm, psd_reg, 0x3000, 0x1);\n\t}\n\n#if 0\n\tif (avg_temp == 0)\n\t\tavg = 1;\n\telse if (avg_temp == 1)\n\t\tavg = 8;\n\telse if (avg_temp == 2)\n\t\tavg = 16;\n\telse if (avg_temp == 3)\n\t\tavg = 32;\n#endif\n\n\ti = start_point;\n\twhile (i < stop_point) {\n\t\tdata_tatal = 0;\n\n\t\tif (i >= point)\n\t\t\tpoint_temp = i - point;\n\t\telse\n\t\t\tpoint_temp = i;\n\n\t\tfor (k = 0; k < average_tmp; k++) {\n\t\t\tdata_temp[k] = halrf_get_psd_data(dm, point_temp);\n\t\t\tdata_tatal = data_tatal + (data_temp[k] * data_temp[k]);\n\n#if 0\n\t\t\tif ((k % 20) == 0)\n\t\t\t\tdbg_print(\"\\n \");\n\n\t\t\tdbg_print(\"0x%x \", data_temp[k]);\n#endif\n\t\t}\n#if 0\n\t\t/*dbg_print(\"\\n\");*/\n#endif\n\n\t\tdata_tatal = phydm_division64((data_tatal * 100), average_tmp);\n\t\tpsd->psd_data[j] = (u32)_sqrt(data_tatal);\n\n\t\ti++;\n\t\tj++;\n\t}\n\n#if 0\n\tfor (i = 0; i < psd->buf_size; i++) {\n\t\tif ((i % 20) == 0)\n\t\t\tdbg_print(\"\\n \");\n\n\t\tdbg_print(\"0x%x \", psd->psd_data[i]);\n\t}\n\tdbg_print(\"\\n\\n\");\n#endif\n\n\tif (dm->support_ic_type & ODM_RTL8710B)\n\t\todm_set_bb_reg(dm, psd_reg, 0x30000, avg_org);\n\telse\n\t\todm_set_bb_reg(dm, psd_reg, 0x3000, avg_org);\n}\n\nvoid backup_bb_register(struct dm_struct *dm, u32 *bb_backup, u32 *backup_bb_reg, u32 counter)\n{\n\tu32 i ;\n\n\tfor (i = 0; i < counter; i++)\n\t\tbb_backup[i] = odm_get_bb_reg(dm, backup_bb_reg[i], MASKDWORD);\n}\n\nvoid restore_bb_register(struct dm_struct *dm, u32 *bb_backup, u32 *backup_bb_reg, u32 counter)\n{\n\tu32 i ;\n\n\tfor (i = 0; i < counter; i++)\n\t\todm_set_bb_reg(dm, backup_bb_reg[i], MASKDWORD, bb_backup[i]);\n}\n\n\n\nvoid _halrf_psd_iqk_init(struct dm_struct *dm)\n{\n\todm_set_bb_reg(dm, 0x1b04, MASKDWORD, 0x0);\n\todm_set_bb_reg(dm, 0x1b08, MASKDWORD, 0x80);\n\todm_set_bb_reg(dm, 0x1b0c, 0xc00, 0x3);\n\todm_set_bb_reg(dm, 0x1b14, MASKDWORD, 0x0);\n\todm_set_bb_reg(dm, 0x1b18, BIT(0), 0x1);\n\n\tif (dm->support_ic_type & ODM_RTL8197G)\n\t\todm_set_bb_reg(dm, 0x1b20, MASKDWORD, 0x00040008);\n\tif (dm->support_ic_type & ODM_RTL8198F) {\n\t\todm_set_bb_reg(dm, 0x1b20, MASKDWORD, 0x00000000);\n\t\todm_set_bb_reg(dm, 0x1b1c, 0xfff, 0xd21);\n\t\todm_set_bb_reg(dm, 0x1b1c, 0xfff00000, 0x821);\n\t}\n\n\tif (dm->support_ic_type & (ODM_RTL8197G | ODM_RTL8198F)) {\n\t\todm_set_bb_reg(dm, 0x1b24, MASKDWORD, 0x00030000);\n\t\todm_set_bb_reg(dm, 0x1b28, MASKDWORD, 0x00000000);\n\t\todm_set_bb_reg(dm, 0x1b2c, MASKDWORD, 0x00180018);\n\t\todm_set_bb_reg(dm, 0x1b30, MASKDWORD, 0x20000000);\n\t\t/*odm_set_bb_reg(dm, 0x1b38, MASKDWORD, 0x20000000);*/\n\t\t/*odm_set_bb_reg(dm, 0x1b3C, MASKDWORD, 0x20000000);*/\n\t}\n\n\todm_set_bb_reg(dm, 0x1b28, MASKDWORD, 0x0);\n\todm_set_bb_reg(dm, 0x1bcc, 0x3f, 0x3f);\t\n}\n\n\nu32 halrf_get_iqk_psd_data(\n\tstruct dm_struct *dm,\n\tu32 point)\n{\n\tstruct _hal_rf_ *rf = &(dm->rf_table);\n\tstruct _halrf_psd_data *psd = &(rf->halrf_psd_data);\n\tu32 psd_val, psd_val1, psd_val2, psd_point, i, delay_time = 0;\n\n#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)\n\tif (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) {\n\t\tif (dm->support_ic_type & ODM_RTL8822C)\n\t\t\tdelay_time = 1000;\n\t\telse\n\t\t\tdelay_time = 0;\n\t}\n#endif\n#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)\n\tif (dm->support_interface == ODM_ITRF_PCIE) {\n\t\tif (dm->support_ic_type & ODM_RTL8822C)\n\t\t\tdelay_time = 1000;\n\t\telse\n\t\t\tdelay_time = 150;\n\t}\n#endif\n\tpsd_point = odm_get_bb_reg(dm, R_0x1b2c, MASKDWORD);\n\n\tpsd_point &= 0xF000FFFF;\n\n\tpoint &= 0xFFF;\n\n\tpsd_point = psd_point | (point << 16);\n\n\todm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, psd_point);\n\n\todm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x1);\n\n\todm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x0);\n\n\tfor (i = 0; i < delay_time; i++)\n\t\tODM_delay_us(1);\n\n\tif (dm->support_ic_type & (ODM_RTL8197G | ODM_RTL8198F)) {\n\t\tif (dm->support_ic_type & ODM_RTL8197G)\n\t\t\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x001a0001);\n\t\telse\n\t\t\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001);\n\n\t\tpsd_val1 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);\n\n\t\tpsd_val1 = (psd_val1 & 0x001f0000) >> 16;\n\n\t\tif (dm->support_ic_type & ODM_RTL8197G)\n\t\t\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x001b0001);\n\t\telse\n\t\t\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x002e0001);\n\n\t\tpsd_val2 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);\n\n\t\tpsd_val = (psd_val1 << 27) + (psd_val2 >> 5);\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001);\n\n\t\tpsd_val1 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);\n\n\t\tpsd_val1 = (psd_val1 & 0x07FF0000) >> 16;\n\n\t\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x002e0001);\n\n\t\tpsd_val2 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);\n\n\t\tpsd_val = (psd_val1 << 21) + (psd_val2 >> 11);\n\t}\n\n\treturn psd_val;\n}\n\nvoid halrf_iqk_psd(\n\tstruct dm_struct *dm,\n\tu32 point,\n\tu32 start_point,\n\tu32 stop_point,\n\tu32 average)\n{\n\tstruct _hal_rf_ *rf = &(dm->rf_table);\n\tstruct _halrf_psd_data *psd = &(rf->halrf_psd_data);\n\n\tu32 i = 0, j = 0, k = 0;\n\tu32 psd_reg, avg_org, point_temp, average_tmp = 32, mode, reg_tmp = 5;\n\tu64 data_tatal = 0, data_temp[64] = {0};\n\ts32 s_point_tmp;\n\n\tpsd->buf_size = 256;\n\n\tmode = average >> 16;\n\n\tif (mode == 2) {\n\t\tif (dm->support_ic_type & ODM_RTL8822C)\n\t\t\taverage_tmp = 1;\n\t\telse {\n\t\t\treg_tmp = odm_get_bb_reg(dm, R_0x1b1c, 0x000e0000);\n\t\t\tif (reg_tmp == 0)\n\t\t\t\taverage_tmp = 1;\n\t\t\telse if (reg_tmp == 3)\n\t\t\t\taverage_tmp = 8;\n\t\t\telse if (reg_tmp == 4)\n\t\t\t\taverage_tmp = 16;\n\t\t\telse if (reg_tmp == 5)\n\t\t\t\taverage_tmp = 32;\n\t\t\todm_set_bb_reg(dm, R_0x1b1c, 0x000e0000, 0x0);\n\t\t}\n\t} else {\n\t\treg_tmp = odm_get_bb_reg(dm, R_0x1b1c, 0x000e0000);\n\t\tif (reg_tmp == 0)\n\t\t\taverage_tmp = 1;\n\t\telse if (reg_tmp == 3)\n\t\t\taverage_tmp = 8;\n\t\telse if (reg_tmp == 4)\n\t\t\taverage_tmp = 16;\n\t\telse if (reg_tmp == 5)\n\t\t\taverage_tmp = 32;\n\t\todm_set_bb_reg(dm, R_0x1b1c, 0x000e0000, 0x0);\n\t}\n\n#if 0\n\tDbgPrint(\"[PSD]point=%d, start_point=%d, stop_point=%d, average=0x%x, average_tmp=%d, buf_size=%d, mode=%d\\n\",\n\t\tpoint, start_point, stop_point, average, average_tmp, psd->buf_size, mode);\n#endif\n\n\tfor (i = 0; i < psd->buf_size; i++)\n\t\tpsd->psd_data[i] = 0;\n\n\ti = start_point;\n\twhile (i < stop_point) {\n\t\tdata_tatal = 0;\n\n\t\tif (i >= point)\n\t\t\tpoint_temp = i - point;\n\t\telse\n\t\t{\n\t\t\tif (dm->support_ic_type & ODM_RTL8814B)\n\t\t\t{\n\t\t\t\ts_point_tmp = i - point - 1;\n\t\t\t\tpoint_temp = s_point_tmp & 0xfff;\n\t\t\t}\n\t\t\telse\n\t\t\t\tpoint_temp = i;\n\t\t}\n\n\t\tfor (k = 0; k < average_tmp; k++) {\n\t\t\tdata_temp[k] = halrf_get_iqk_psd_data(dm, point_temp);\n\t\t\t/*data_tatal = data_tatal + (data_temp[k] * data_temp[k]);*/\n\t\t\tdata_tatal = data_tatal + data_temp[k];\n\n#if 0\n\t\t\tif ((k % 20) == 0)\n\t\t\t\tDbgPrint(\"\\n \");\n\n\t\t\tDbgPrint(\"0x%x \", data_temp[k]);\n#endif\n\t\t}\n\n\t\tdata_tatal = phydm_division64((data_tatal * 10), average_tmp);\n\t\tpsd->psd_data[j] = (u32)data_tatal;\n\n\t\ti++;\n\t\tj++;\n\t}\n\n\tif (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8198F | ODM_RTL8197G))\n\t\todm_set_bb_reg(dm, R_0x1b1c, 0x000e0000, reg_tmp);\n\n#if 0\n\tDbgPrint(\"\\n [iqk psd]psd result:\\n\");\n\n\tfor (i = 0; i < psd->buf_size; i++) {\n\t\tif ((i % 20) == 0)\n\t\t\tDbgPrint(\"\\n \");\n\n\t\tDbgPrint(\"0x%x \", psd->psd_data[i]);\n\t}\n\tDbgPrint(\"\\n\\n\");\n#endif\n}\n\n\nu32\nhalrf_psd_init(\n\tvoid *dm_void)\n{\n\tenum rt_status ret_status = RT_STATUS_SUCCESS;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &(dm->rf_table);\n\tstruct _halrf_psd_data *psd = &(rf->halrf_psd_data);\n\n#if 0\n\tu32 bb_backup[12];\n\tu32 backup_bb_reg[12] = {0x1b04, 0x1b08, 0x1b0c, 0x1b14, 0x1b18,\n\t\t\t\t0x1b1c, 0x1b28, 0x1bcc, 0x1b2c, 0x1b34,\n\t\t\t\t0x1bd4, 0x1bfc};\n#endif\n\n\tif (psd->psd_progress) {\n\t\tret_status = RT_STATUS_PENDING;\n\t} else {\n\t\tpsd->psd_progress = 1;\n\t\tif (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8198F | ODM_RTL8197G)) {\n\t\t\t/*backup_bb_register(dm, bb_backup, backup_bb_reg, 12);*/\n\t\t\t_halrf_psd_iqk_init(dm);\n\t\t\thalrf_iqk_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);\n\t\t\t/*restore_bb_register(dm, bb_backup, backup_bb_reg, 12);*/\n\t\t} else\n\t\t\thalrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);\n\t\tpsd->psd_progress = 0;\n\t}\n\treturn ret_status;\n}\n\nu32\nhalrf_psd_query(\n\tvoid *dm_void,\n\tu32 *outbuf,\n\tu32 buf_size)\n{\n\tenum rt_status ret_status = RT_STATUS_SUCCESS;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &(dm->rf_table);\n\tstruct _halrf_psd_data *psd = &(rf->halrf_psd_data);\n\n\tif (psd->psd_progress)\n\t\tret_status = RT_STATUS_PENDING;\n\telse\n\t\todm_move_memory(dm, outbuf, psd->psd_data,\n\t\t\t\tsizeof(u32) * psd->buf_size);\n\n\treturn ret_status;\n}\n\nu32\nhalrf_psd_init_query(\n\tvoid *dm_void,\n\tu32 *outbuf,\n\tu32 point,\n\tu32 start_point,\n\tu32 stop_point,\n\tu32 average,\n\tu32 buf_size)\n{\n\tenum rt_status ret_status = RT_STATUS_SUCCESS;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &(dm->rf_table);\n\tstruct _halrf_psd_data *psd = &(rf->halrf_psd_data);\n\n\tpsd->point = point;\n\tpsd->start_point = start_point;\n\tpsd->stop_point = stop_point;\n\tpsd->average = average;\n\n\tif (psd->psd_progress) {\n\t\tret_status = RT_STATUS_PENDING;\n\t} else {\n\t\tpsd->psd_progress = 1;\n\t\thalrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);\n\t\todm_move_memory(dm, outbuf, psd->psd_data, 0x400);\n\t\tpsd->psd_progress = 0;\n\t}\n\n\treturn ret_status;\n}\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_psd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef __HALRF_PSD_H__\n#define __HALRF_PSD_H__\n\n\nstruct _halrf_psd_data {\n\tu32 point;\n\tu32 start_point;\n\tu32 stop_point;\n\tu32 average;\n\tu32 buf_size;\n\tu32 psd_data[256];\n\tu32 psd_progress;\n};\n\nu32\nhalrf_psd_init(\n\tvoid *dm_void);\n\nu32\nhalrf_psd_query(\n\tvoid *dm_void,\n\tu32 *outbuf,\n\tu32 buf_size);\n\nu32\nhalrf_psd_init_query(\n\tvoid *dm_void,\n\tu32 *outbuf,\n\tu32 point,\n\tu32 start_point,\n\tu32 stop_point,\n\tu32 average,\n\tu32 buf_size);\n\n#endif /*#__HALRF_PSD_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_txgapcal.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\nvoid odm_bub_sort(u32 *data, u32 n)\n{\n\tint i, j, temp, sp;\n\n\tfor (i = n - 1; i >= 0; i--) {\n\t\tsp = 1;\n\t\tfor (j = 0; j < i; j++) {\n\t\t\tif (data[j] < data[j + 1]) {\n\t\t\t\ttemp = data[j];\n\t\t\t\tdata[j] = data[j + 1];\n\t\t\t\tdata[j + 1] = temp;\n\t\t\t\tsp = 0;\n\t\t\t}\n\t\t}\n\t\tif (sp == 1)\n\t\t\tbreak;\n\t}\n}\n\n#if (RTL8197F_SUPPORT == 1)\n\nu4Byte\nodm_tx_gain_gap_psd_8197f(\n\tvoid *dm_void,\n\tu1Byte rf_path,\n\tu4Byte rf56)\n{\n\tPDM_ODM_T dm = (PDM_ODM_T)dm_void;\n\n\tu1Byte i, j;\n\tu4Byte psd_vaule[5], psd_avg_time = 5, psd_vaule_temp;\n\n\tu4Byte iqk_ctl_addr[2][6] = {{0xe30, 0xe34, 0xe50, 0xe54, 0xe38, 0xe3c},\n\t\t\t\t     {0xe50, 0xe54, 0xe30, 0xe34, 0xe58, 0xe5c}};\n\n\tu4Byte psd_finish_bit[2] = {0x04000000, 0x20000000};\n\tu4Byte psd_fail_bit[2] = {0x08000000, 0x40000000};\n\n\tu4Byte psd_cntl_value[2][2] = {{0x38008c1c, 0x10008c1c},\n\t\t\t\t       {0x38008c2c, 0x10008c2c}};\n\n\tu4Byte psd_report_addr[2] = {0xea0, 0xec0};\n\n\todm_set_rf_reg(dm, rf_path, RF_0xdf, bRFRegOffsetMask, 0x00e02);\n\n\tODM_delay_us(100);\n\n\todm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x0);\n\n\todm_set_rf_reg(dm, rf_path, RF_0x56, 0xfff, rf56);\n\twhile (rf56 != (odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff)))\n\t\todm_set_rf_reg(dm, rf_path, RF_0x56, 0xfff, rf56);\n\n\todm_set_bb_reg(dm, R_0xd94, 0xffffffff, 0x44FFBB44);\n\todm_set_bb_reg(dm, R_0xe70, 0xffffffff, 0x00400040);\n\todm_set_bb_reg(dm, R_0xc04, 0xffffffff, 0x6f005403);\n\todm_set_bb_reg(dm, R_0xc08, 0xffffffff, 0x000804e4);\n\todm_set_bb_reg(dm, R_0x874, 0xffffffff, 0x04203400);\n\todm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x80800000);\n\n\todm_set_bb_reg(dm, iqk_ctl_addr[rf_path][0], 0xffffffff, psd_cntl_value[rf_path][0]);\n\todm_set_bb_reg(dm, iqk_ctl_addr[rf_path][1], 0xffffffff, psd_cntl_value[rf_path][1]);\n\todm_set_bb_reg(dm, iqk_ctl_addr[rf_path][2], 0xffffffff, psd_cntl_value[rf_path][0]);\n\todm_set_bb_reg(dm, iqk_ctl_addr[rf_path][3], 0xffffffff, psd_cntl_value[rf_path][0]);\n\todm_set_bb_reg(dm, iqk_ctl_addr[rf_path][4], 0xffffffff, 0x8215001F);\n\todm_set_bb_reg(dm, iqk_ctl_addr[rf_path][5], 0xffffffff, 0x2805001F);\n\n\todm_set_bb_reg(dm, R_0xe40, 0xffffffff, 0x81007C00);\n\todm_set_bb_reg(dm, R_0xe44, 0xffffffff, 0x81004800);\n\todm_set_bb_reg(dm, R_0xe4c, 0xffffffff, 0x0046a8d0);\n\n\tfor (i = 0; i < psd_avg_time; i++) {\n\t\tfor (j = 0; j < 1000; j++) {\n\t\t\todm_set_bb_reg(dm, R_0xe48, 0xffffffff, 0xfa005800);\n\t\t\todm_set_bb_reg(dm, R_0xe48, 0xffffffff, 0xf8005800);\n\n\t\t\twhile (!odm_get_bb_reg(dm, R_0xeac, psd_finish_bit[rf_path]))\n\t\t\t\t; /*wait finish bit*/\n\n\t\t\tif (!odm_get_bb_reg(dm, R_0xeac, psd_fail_bit[rf_path])) { /*check fail bit*/\n\n\t\t\t\tpsd_vaule[i] = odm_get_bb_reg(dm, psd_report_addr[rf_path], 0xffffffff);\n\n\t\t\t\tif (psd_vaule[i] > 0xffff)\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t       \"[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x time=%d psd_vaule=0x%x\\n\",\n\t\t       odm_get_rf_reg(dm, rf_path, RF_0x0, 0xff), rf56,\n\t\t       odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff), j,\n\t\t       psd_vaule[i]);\n\t}\n\n\todm_bub_sort(psd_vaule, psd_avg_time);\n\n\tpsd_vaule_temp = psd_vaule[(UINT)(psd_avg_time / 2)];\n\n\todm_set_bb_reg(dm, R_0xd94, 0xffffffff, 0x44BBBB44);\n\todm_set_bb_reg(dm, R_0xe70, 0xffffffff, 0x80408040);\n\todm_set_bb_reg(dm, R_0xc04, 0xffffffff, 0x6f005433);\n\todm_set_bb_reg(dm, R_0xc08, 0xffffffff, 0x000004e4);\n\todm_set_bb_reg(dm, R_0x874, 0xffffffff, 0x04003400);\n\todm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x00000000);\n\n\tRF_DBG(dm, DBG_RF_IQK,\n\t       \"[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x psd_vaule_temp=0x%x\\n\",\n\t       odm_get_rf_reg(dm, rf_path, RF_0x0, 0xff), rf56,\n\t       odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff), psd_vaule_temp);\n\n\todm_set_rf_reg(dm, rf_path, RF_0xdf, bRFRegOffsetMask, 0x00602);\n\n\treturn psd_vaule_temp;\n}\n\nvoid odm_tx_gain_gap_calibration_8197f(\n\tvoid *dm_void)\n{\n\tPDM_ODM_T dm = (PDM_ODM_T)dm_void;\n\n\tu1Byte rf_path, rf0_idx, rf0_idx_current, rf0_idx_next, i, delta_gain_retry = 3;\n\n\ts1Byte delta_gain_gap_pre, delta_gain_gap[2][11];\n\tu4Byte rf56_current, rf56_next, psd_value_current, psd_value_next;\n\tu4Byte psd_gap, rf56_current_temp[2][11];\n\ts4Byte rf33[2][11];\n\n\tmemset(rf33, 0x0, sizeof(rf33));\n\n\tfor (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {\n\t\tif (rf_path == RF_PATH_A)\n\t\t\todm_set_bb_reg(dm, R_0x88c, (BIT(21) | BIT(20)), 0x3); /*disable 3-wire*/\n\t\telse if (rf_path == RF_PATH_B)\n\t\t\todm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22)), 0x3); /*disable 3-wire*/\n\n\t\tODM_delay_us(100);\n\n\t\tfor (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {\n\t\t\trf0_idx_current = 3 * (rf0_idx - 1) + 1;\n\t\t\todm_set_rf_reg(dm, rf_path, RF_0x0, 0xff, rf0_idx_current);\n\t\t\tODM_delay_us(100);\n\t\t\trf56_current_temp[rf_path][rf0_idx] = odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff);\n\t\t\trf56_current = rf56_current_temp[rf_path][rf0_idx];\n\n\t\t\trf0_idx_next = 3 * rf0_idx + 1;\n\t\t\todm_set_rf_reg(dm, rf_path, RF_0x0, 0xff, rf0_idx_next);\n\t\t\tODM_delay_us(100);\n\t\t\trf56_next = odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff);\n\n\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t       \"[TGGC] rf56_current[%d][%d]=0x%x rf56_next[%d][%d]=0x%x\\n\",\n\t\t\t       rf_path, rf0_idx, rf56_current, rf_path, rf0_idx,\n\t\t\t       rf56_next);\n\n\t\t\tif ((rf56_current >> 5) == (rf56_next >> 5)) {\n\t\t\t\tdelta_gain_gap[rf_path][rf0_idx] = 0;\n\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\t       \"[TGGC] rf56_current[11:5] == rf56_next[%d][%d][11:5]=0x%x delta_gain_gap[%d][%d]=%d\\n\",\n\t\t\t\t       rf_path, rf0_idx, (rf56_next >> 5),\n\t\t\t\t       rf_path, rf0_idx,\n\t\t\t\t       delta_gain_gap[rf_path][rf0_idx]);\n\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t       \"[TGGC] rf56_current[%d][%d][11:5]=0x%x != rf56_next[%d][%d][11:5]=0x%x\\n\",\n\t\t\t       rf_path, rf0_idx, (rf56_current >> 5), rf_path,\n\t\t\t       rf0_idx, (rf56_next >> 5));\n\n\t\t\tfor (i = 0; i < delta_gain_retry; i++) {\n\t\t\t\tpsd_value_current = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_current);\n\n\t\t\t\tpsd_value_next = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_next - 2);\n\n\t\t\t\tpsd_gap = psd_value_next / (psd_value_current / 1000);\n\n#if 0\n\t\t\t\tif (psd_gap > 1413)\n\t\t\t\t\tdelta_gain_gap[rf_path][rf0_idx] = 1;\n\t\t\t\telse if (psd_gap > 1122)\n\t\t\t\t\tdelta_gain_gap[rf_path][rf0_idx] = 0;\n\t\t\t\telse\n\t\t\t\t\tdelta_gain_gap[rf_path][rf0_idx] = -1;\n#endif\n\n\t\t\t\tif (psd_gap > 1445)\n\t\t\t\t\tdelta_gain_gap[rf_path][rf0_idx] = 1;\n\t\t\t\telse if (psd_gap > 1096)\n\t\t\t\t\tdelta_gain_gap[rf_path][rf0_idx] = 0;\n\t\t\t\telse\n\t\t\t\t\tdelta_gain_gap[rf_path][rf0_idx] = -1;\n\n\t\t\t\tif (i == 0)\n\t\t\t\t\tdelta_gain_gap_pre = delta_gain_gap[rf_path][rf0_idx];\n\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\t       \"[TGGC] psd_value_current=0x%x psd_value_next=0x%x psd_value_next/psd_value_current=%d delta_gain_gap[%d][%d]=%d\\n\",\n\t\t\t\t       psd_value_current, psd_value_next,\n\t\t\t\t       psd_gap, rf_path, rf0_idx,\n\t\t\t\t       delta_gain_gap[rf_path][rf0_idx]);\n\n\t\t\t\tif (i == 0 && delta_gain_gap[rf_path][rf0_idx] == 0)\n\t\t\t\t\tbreak;\n\n\t\t\t\tif (delta_gain_gap_pre != delta_gain_gap[rf_path][rf0_idx]) {\n\t\t\t\t\tdelta_gain_gap[rf_path][rf0_idx] = 0;\n\n\t\t\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[TGGC] delta_gain_gap_pre(%d) != delta_gain_gap[%d][%d](%d) time=%d\\n\",\n\t\t\t\t\t       delta_gain_gap_pre, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx], i);\n\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\t       \"[TGGC] delta_gain_gap_pre(%d) == delta_gain_gap[%d][%d](%d) time=%d\\n\",\n\t\t\t\t       delta_gain_gap_pre, rf_path, rf0_idx,\n\t\t\t\t       delta_gain_gap[rf_path][rf0_idx], i);\n\t\t\t}\n\t\t}\n\n\t\tif (rf_path == RF_PATH_A)\n\t\t\todm_set_bb_reg(dm, R_0x88c, (BIT(21) | BIT(20)), 0x0); /*enable 3-wire*/\n\t\telse if (rf_path == RF_PATH_B)\n\t\t\todm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22)), 0x0); /*enable 3-wire*/\n\n\t\tODM_delay_us(100);\n\t}\n\n#if 0\n\t/*odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22) | BIT(21) | BIT(20)), 0x0);*/ /*enable 3-wire*/\n#endif\n\n\tfor (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {\n\t\todm_set_rf_reg(dm, rf_path, RF_0xef, bRFRegOffsetMask, 0x00100);\n\n\t\tfor (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {\n\t\t\trf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + (rf56_current_temp[rf_path][rf0_idx] & 0x1f);\n\n\t\t\tfor (i = rf0_idx; i <= 10; i++)\n\t\t\t\trf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + delta_gain_gap[rf_path][i];\n\n\t\t\tif (rf33[rf_path][rf0_idx] >= 0x1d)\n\t\t\t\trf33[rf_path][rf0_idx] = 0x1d;\n\t\t\telse if (rf33[rf_path][rf0_idx] <= 0x2)\n\t\t\t\trf33[rf_path][rf0_idx] = 0x2;\n\n\t\t\trf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + ((rf0_idx - 1) * 0x4000) + (rf56_current_temp[rf_path][rf0_idx] & 0xfffe0);\n\n\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t       \"[TGGC] rf56[%d][%d]=0x%05x rf33[%d][%d]=0x%05x\\n\",\n\t\t\t       rf_path, rf0_idx,\n\t\t\t       rf56_current_temp[rf_path][rf0_idx], rf_path,\n\t\t\t       rf0_idx, rf33[rf_path][rf0_idx]);\n\n\t\t\todm_set_rf_reg(dm, rf_path, RF_0x33, bRFRegOffsetMask, rf33[rf_path][rf0_idx]);\n\t\t}\n\n\t\todm_set_rf_reg(dm, rf_path, RF_0xef, bRFRegOffsetMask, 0x00000);\n\t}\n}\n#endif\n\nvoid odm_tx_gain_gap_calibration(void *dm_void)\n{\n\tPDM_ODM_T dm = (PDM_ODM_T)dm_void;\n#if (RTL8197F_SUPPORT == 1)\n\tif (dm->SupportICType & ODM_RTL8197F)\n\t\todm_tx_gain_gap_calibration_8197f(dm_void);\n#endif\n}\n"
  },
  {
    "path": "hal/phydm/halrf/halrf_txgapcal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALRF_TXGAPCAL_H__\n#define __HALRF_TXGAPCAL_H__\n\nvoid odm_tx_gain_gap_calibration(void *dm_void);\n\n#endif /*__HALRF_TXGAPCAL_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/rtl8822c/halhwimg8822c_rf.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*Image2HeaderVersion: R3 1.5.8*/\n#include \"mp_precomp.h\"\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#if RT_PLATFORM == PLATFORM_MACOSX\n#include \"phydm_precomp.h\"\n#else\n#include \"../phydm_precomp.h\"\n#endif\n#else\n#include \"../../phydm_precomp.h\"\n#endif\n\n#define D_S_SIZE DELTA_SWINGIDX_SIZE\n#define D_ST_SIZE DELTA_SWINTSSI_SIZE\n\n#if (RTL8822C_SUPPORT == 1)\nstatic boolean\ncheck_positive(struct dm_struct *dm,\n\t       const u32\tcondition1,\n\t       const u32\tcondition2,\n\t       const u32\tcondition3,\n\t       const u32\tcondition4\n)\n{\n\tu32\tcond1 = condition1, cond2 = condition2,\n\t\tcond3 = condition3, cond4 = condition4;\n\n\tu8\tcut_version_for_para =\n\t\t(dm->cut_version ==  ODM_CUT_A) ? 15 : dm->cut_version;\n\n\tu8\tpkg_type_for_para =\n\t\t(dm->package_type == 0) ? 15 : dm->package_type;\n\n\tu32\tdriver1 = cut_version_for_para << 24 |\n\t\t\t(dm->support_interface & 0xF0) << 16 |\n\t\t\tdm->support_platform << 16 |\n\t\t\tpkg_type_for_para << 12 |\n\t\t\t(dm->support_interface & 0x0F) << 8  |\n\t\t\tdm->rfe_type;\n\n\tu32\tdriver2 = (dm->type_glna & 0xFF) <<  0 |\n\t\t\t(dm->type_gpa & 0xFF)  <<  8 |\n\t\t\t(dm->type_alna & 0xFF) << 16 |\n\t\t\t(dm->type_apa & 0xFF)  << 24;\n\n\tu32\tdriver3 = 0;\n\n\tu32\tdriver4 = (dm->type_glna & 0xFF00) >>  8 |\n\t\t\t(dm->type_gpa & 0xFF00) |\n\t\t\t(dm->type_alna & 0xFF00) << 8 |\n\t\t\t(dm->type_apa & 0xFF00)  << 16;\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t  \"===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\\n\",\n\t\t  __func__, cond1, cond2, cond3, cond4);\n\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t  \"===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\\n\",\n\t\t  __func__, driver1, driver2, driver3, driver4);\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t  \"\t(Platform, Interface) = (0x%X, 0x%X)\\n\",\n\t\t  dm->support_platform, dm->support_interface);\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"\t(RFE, Package) = (0x%X, 0x%X)\\n\",\n\t\t  dm->rfe_type, dm->package_type);\n\n\t/*============== value Defined Check ===============*/\n\t/*cut version [27:24] need to do value check*/\n\tif (((cond1 & 0x0F000000) != 0) &&\n\t    ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))\n\t\treturn false;\n\n\t/*pkg type [15:12] need to do value check*/\n\tif (((cond1 & 0x0000F000) != 0) &&\n\t    ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))\n\t\treturn false;\n\n\t/*interface [11:8] need to do value check*/\n\tif (((cond1 & 0x00000F00) != 0) &&\n\t    ((cond1 & 0x00000F00) != (driver1 & 0x00000F00)))\n\t\treturn false;\n\t/*=============== Bit Defined Check ================*/\n\t/* We don't care [31:28] */\n\n\tcond1 &= 0x000000FF;\n\tdriver1 &= 0x000000FF;\n\n\tif (cond1 == driver1)\n\t\treturn true;\n\telse\n\t\treturn false;\n}\n\n\n/******************************************************************************\n *                           radioa.TXT\n ******************************************************************************/\n\nconst u32 array_mp_8822c_radioa[] = {\n\t\t0x000, 0x00030000,\n\t\t0x018, 0x00013124,\n\t\t0x093, 0x0008483F,\n\t\t0x0DE, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x08E, 0x000B9140,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x08E, 0x000B9140,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x08E, 0x000A5540,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x08E, 0x000A5540,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x08E, 0x000A5540,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x08E, 0x000A5540,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x08E, 0x000A5540,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x08E, 0x000A5540,\n\t0xA0000000,\t0x00000000,\n\t\t0x08E, 0x000A5540,\n\t0xB0000000,\t0x00000000,\n\t\t0x081, 0x0000FC01,\n\t\t0x081, 0x0002FC01,\n\t\t0x081, 0x0003FC01,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x085, 0x0006A06C,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x085, 0x0006A06C,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x085, 0x0006A06C,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x085, 0x0006A06C,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x085, 0x0006A06C,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x085, 0x0006A06C,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x085, 0x0006A06C,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x085, 0x0006A06C,\n\t0xA0000000,\t0x00000000,\n\t\t0x085, 0x0006A06C,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EE, 0x00000010,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000002,\n\t\t0x03F, 0x0000002A,\n\t\t0x0EE, 0x00000000,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EE, 0x00000010,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000002,\n\t\t0x03F, 0x0000002A,\n\t\t0x0EE, 0x00000000,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EE, 0x00000010,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000002,\n\t\t0x03F, 0x0000002A,\n\t\t0x0EE, 0x00000000,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EE, 0x00000010,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000002,\n\t\t0x03F, 0x0000002A,\n\t\t0x0EE, 0x00000000,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EE, 0x00000010,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000002,\n\t\t0x03F, 0x0000002A,\n\t\t0x0EE, 0x00000000,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EE, 0x00000010,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000002,\n\t\t0x03F, 0x0000002A,\n\t\t0x0EE, 0x00000000,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EE, 0x00000010,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000002,\n\t\t0x03F, 0x0000002A,\n\t\t0x0EE, 0x00000000,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EE, 0x00000010,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000002,\n\t\t0x03F, 0x0000002A,\n\t\t0x0EE, 0x00000000,\n\t0xA0000000,\t0x00000000,\n\t\t0x0EE, 0x00000010,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000003F,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000003F,\n\t\t0x033, 0x00000002,\n\t\t0x03F, 0x0000003F,\n\t\t0x0EE, 0x00000000,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EF, 0x00010000,\n\t\t0x033, 0x0000000F,\n\t\t0x03F, 0x000773C0,\n\t\t0x033, 0x0000000E,\n\t\t0x03F, 0x000FF3C0,\n\t\t0x033, 0x0000000D,\n\t\t0x03F, 0x000773E8,\n\t\t0x033, 0x0000000C,\n\t\t0x03F, 0x000FF3E8,\n\t\t0x033, 0x0000000B,\n\t\t0x03F, 0x000FF3A0,\n\t\t0x033, 0x0000000A,\n\t\t0x03F, 0x000002A8,\n\t\t0x033, 0x00000009,\n\t\t0x03F, 0x00000280,\n\t\t0x033, 0x00000008,\n\t\t0x03F, 0x000FF280,\n\t\t0x033, 0x00000007,\n\t\t0x03F, 0x00000200,\n\t\t0x033, 0x00000006,\n\t\t0x03F, 0x000001C0,\n\t\t0x033, 0x00000005,\n\t\t0x03F, 0x00000180,\n\t\t0x033, 0x00000004,\n\t\t0x03F, 0x00000040,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EF, 0x00010000,\n\t\t0x033, 0x0000000F,\n\t\t0x03F, 0x000773C0,\n\t\t0x033, 0x0000000E,\n\t\t0x03F, 0x000FF3C0,\n\t\t0x033, 0x0000000D,\n\t\t0x03F, 0x000773E8,\n\t\t0x033, 0x0000000C,\n\t\t0x03F, 0x000FF3E8,\n\t\t0x033, 0x0000000B,\n\t\t0x03F, 0x000FF3A0,\n\t\t0x033, 0x0000000A,\n\t\t0x03F, 0x000002A8,\n\t\t0x033, 0x00000009,\n\t\t0x03F, 0x00000280,\n\t\t0x033, 0x00000008,\n\t\t0x03F, 0x000FF280,\n\t\t0x033, 0x00000007,\n\t\t0x03F, 0x00000200,\n\t\t0x033, 0x00000006,\n\t\t0x03F, 0x000001C0,\n\t\t0x033, 0x00000005,\n\t\t0x03F, 0x00000180,\n\t\t0x033, 0x00000004,\n\t\t0x03F, 0x00000040,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EF, 0x00010000,\n\t\t0x033, 0x0000000F,\n\t\t0x03F, 0x000773C0,\n\t\t0x033, 0x0000000E,\n\t\t0x03F, 0x000FF3C0,\n\t\t0x033, 0x0000000D,\n\t\t0x03F, 0x000773E8,\n\t\t0x033, 0x0000000C,\n\t\t0x03F, 0x000FF3E8,\n\t\t0x033, 0x0000000B,\n\t\t0x03F, 0x000FF3A0,\n\t\t0x033, 0x0000000A,\n\t\t0x03F, 0x000002A8,\n\t\t0x033, 0x00000009,\n\t\t0x03F, 0x00000280,\n\t\t0x033, 0x00000008,\n\t\t0x03F, 0x000FF280,\n\t\t0x033, 0x00000007,\n\t\t0x03F, 0x00000200,\n\t\t0x033, 0x00000006,\n\t\t0x03F, 0x000001C0,\n\t\t0x033, 0x00000005,\n\t\t0x03F, 0x00000180,\n\t\t0x033, 0x00000004,\n\t\t0x03F, 0x00000040,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EF, 0x00010000,\n\t\t0x033, 0x0000000F,\n\t\t0x03F, 0x000773C0,\n\t\t0x033, 0x0000000E,\n\t\t0x03F, 0x000FF3C0,\n\t\t0x033, 0x0000000D,\n\t\t0x03F, 0x000773E8,\n\t\t0x033, 0x0000000C,\n\t\t0x03F, 0x000FF3E8,\n\t\t0x033, 0x0000000B,\n\t\t0x03F, 0x000FF3A0,\n\t\t0x033, 0x0000000A,\n\t\t0x03F, 0x000002A8,\n\t\t0x033, 0x00000009,\n\t\t0x03F, 0x00000280,\n\t\t0x033, 0x00000008,\n\t\t0x03F, 0x000FF280,\n\t\t0x033, 0x00000007,\n\t\t0x03F, 0x00000200,\n\t\t0x033, 0x00000006,\n\t\t0x03F, 0x000001C0,\n\t\t0x033, 0x00000005,\n\t\t0x03F, 0x00000180,\n\t\t0x033, 0x00000004,\n\t\t0x03F, 0x00000040,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EF, 0x00010000,\n\t\t0x033, 0x0000000F,\n\t\t0x03F, 0x000773C0,\n\t\t0x033, 0x0000000E,\n\t\t0x03F, 0x000FF3C0,\n\t\t0x033, 0x0000000D,\n\t\t0x03F, 0x000773E8,\n\t\t0x033, 0x0000000C,\n\t\t0x03F, 0x000FF3E8,\n\t\t0x033, 0x0000000B,\n\t\t0x03F, 0x000FF3A0,\n\t\t0x033, 0x0000000A,\n\t\t0x03F, 0x000002A8,\n\t\t0x033, 0x00000009,\n\t\t0x03F, 0x00000280,\n\t\t0x033, 0x00000008,\n\t\t0x03F, 0x000FF280,\n\t\t0x033, 0x00000007,\n\t\t0x03F, 0x00000200,\n\t\t0x033, 0x00000006,\n\t\t0x03F, 0x000001C0,\n\t\t0x033, 0x00000005,\n\t\t0x03F, 0x00000180,\n\t\t0x033, 0x00000004,\n\t\t0x03F, 0x00000040,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EF, 0x00010000,\n\t\t0x033, 0x0000000F,\n\t\t0x03F, 0x000773C0,\n\t\t0x033, 0x0000000E,\n\t\t0x03F, 0x000FF3C0,\n\t\t0x033, 0x0000000D,\n\t\t0x03F, 0x000773E8,\n\t\t0x033, 0x0000000C,\n\t\t0x03F, 0x000FF3E8,\n\t\t0x033, 0x0000000B,\n\t\t0x03F, 0x000FF3A0,\n\t\t0x033, 0x0000000A,\n\t\t0x03F, 0x000002A8,\n\t\t0x033, 0x00000009,\n\t\t0x03F, 0x00000280,\n\t\t0x033, 0x00000008,\n\t\t0x03F, 0x000FF280,\n\t\t0x033, 0x00000007,\n\t\t0x03F, 0x00000200,\n\t\t0x033, 0x00000006,\n\t\t0x03F, 0x000001C0,\n\t\t0x033, 0x00000005,\n\t\t0x03F, 0x00000180,\n\t\t0x033, 0x00000004,\n\t\t0x03F, 0x00000040,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EF, 0x00010000,\n\t\t0x033, 0x0000000F,\n\t\t0x03F, 0x000773C0,\n\t\t0x033, 0x0000000E,\n\t\t0x03F, 0x000FF3C0,\n\t\t0x033, 0x0000000D,\n\t\t0x03F, 0x000773E8,\n\t\t0x033, 0x0000000C,\n\t\t0x03F, 0x000FF3E8,\n\t\t0x033, 0x0000000B,\n\t\t0x03F, 0x00000287,\n\t\t0x033, 0x0000000A,\n\t\t0x03F, 0x000002A8,\n\t\t0x033, 0x00000009,\n\t\t0x03F, 0x00000207,\n\t\t0x033, 0x00000008,\n\t\t0x03F, 0x000FF280,\n\t\t0x033, 0x00000007,\n\t\t0x03F, 0x00000200,\n\t\t0x033, 0x00000006,\n\t\t0x03F, 0x000001C0,\n\t\t0x033, 0x00000005,\n\t\t0x03F, 0x00000180,\n\t\t0x033, 0x00000004,\n\t\t0x03F, 0x00000040,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EF, 0x00010000,\n\t\t0x033, 0x0000000F,\n\t\t0x03F, 0x000773C0,\n\t\t0x033, 0x0000000E,\n\t\t0x03F, 0x000FF3C0,\n\t\t0x033, 0x0000000D,\n\t\t0x03F, 0x000773E8,\n\t\t0x033, 0x0000000C,\n\t\t0x03F, 0x000FF3E8,\n\t\t0x033, 0x0000000B,\n\t\t0x03F, 0x00000287,\n\t\t0x033, 0x0000000A,\n\t\t0x03F, 0x000002A8,\n\t\t0x033, 0x00000009,\n\t\t0x03F, 0x00000207,\n\t\t0x033, 0x00000008,\n\t\t0x03F, 0x000FF280,\n\t\t0x033, 0x00000007,\n\t\t0x03F, 0x00000200,\n\t\t0x033, 0x00000006,\n\t\t0x03F, 0x000001C0,\n\t\t0x033, 0x00000005,\n\t\t0x03F, 0x00000180,\n\t\t0x033, 0x00000004,\n\t\t0x03F, 0x00000040,\n\t0xA0000000,\t0x00000000,\n\t\t0x0EF, 0x00010000,\n\t\t0x033, 0x0000000F,\n\t\t0x03F, 0x000773E8,\n\t\t0x033, 0x0000000E,\n\t\t0x03F, 0x000FF3A0,\n\t\t0x033, 0x0000000D,\n\t\t0x03F, 0x00000380,\n\t\t0x033, 0x0000000C,\n\t\t0x03F, 0x000FF380,\n\t\t0x033, 0x0000000B,\n\t\t0x03F, 0x00000300,\n\t\t0x033, 0x0000000A,\n\t\t0x03F, 0x000002A8,\n\t\t0x033, 0x00000009,\n\t\t0x03F, 0x00000280,\n\t\t0x033, 0x00000008,\n\t\t0x03F, 0x000FF280,\n\t\t0x033, 0x00000007,\n\t\t0x03F, 0x00000200,\n\t\t0x033, 0x00000006,\n\t\t0x03F, 0x000001C0,\n\t\t0x033, 0x00000005,\n\t\t0x03F, 0x00000180,\n\t\t0x033, 0x00000004,\n\t\t0x03F, 0x00000040,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000003,\n\t\t0x03F, 0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x0000001F,\n\t\t0x03F, 0x000773C0,\n\t\t0x033, 0x0000001E,\n\t\t0x03F, 0x000FF3C0,\n\t\t0x033, 0x0000001D,\n\t\t0x03F, 0x000773E8,\n\t\t0x033, 0x0000001C,\n\t\t0x03F, 0x000FF3E8,\n\t\t0x033, 0x0000001B,\n\t\t0x03F, 0x000FF3A0,\n\t\t0x033, 0x0000001A,\n\t\t0x03F, 0x000002A8,\n\t\t0x033, 0x00000019,\n\t\t0x03F, 0x00000280,\n\t\t0x033, 0x00000018,\n\t\t0x03F, 0x000FF280,\n\t\t0x033, 0x00000017,\n\t\t0x03F, 0x00000200,\n\t\t0x033, 0x00000016,\n\t\t0x03F, 0x000001C0,\n\t\t0x033, 0x00000015,\n\t\t0x03F, 0x00000180,\n\t\t0x033, 0x00000014,\n\t\t0x03F, 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0x00015239,\n\t\t0x030, 0x00016209,\n\t\t0x030, 0x00017239,\n\t\t0x030, 0x00018209,\n\t\t0x030, 0x00019239,\n\t0xA0000000,\t0x00000000,\n\t\t0x030, 0x00000233,\n\t\t0x030, 0x00001233,\n\t\t0x030, 0x00002233,\n\t\t0x030, 0x00003233,\n\t\t0x030, 0x00004203,\n\t\t0x030, 0x00005233,\n\t\t0x030, 0x00006233,\n\t\t0x030, 0x00007233,\n\t\t0x030, 0x00008203,\n\t\t0x030, 0x00009233,\n\t\t0x030, 0x0000A233,\n\t\t0x030, 0x0000B233,\n\t\t0x030, 0x0000C233,\n\t\t0x030, 0x0000D233,\n\t\t0x030, 0x0000E203,\n\t\t0x030, 0x0000F233,\n\t\t0x030, 0x00010233,\n\t\t0x030, 0x00011233,\n\t\t0x030, 0x00012203,\n\t\t0x030, 0x00013233,\n\t\t0x030, 0x00014233,\n\t\t0x030, 0x00015233,\n\t\t0x030, 0x00016203,\n\t\t0x030, 0x00017233,\n\t\t0x030, 0x00018203,\n\t\t0x030, 0x00019233,\n\t0xB0000000,\t0x00000000,\n\t\t0x0EF, 0x00000000,\n\t\t0x0EF, 0x00000080,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x030, 0x00000334,\n\t\t0x030, 0x00001334,\n\t\t0x030, 0x00002334,\n\t\t0x030, 0x00003334,\n\t\t0x030, 0x00004334,\n\t\t0x030, 0x00005334,\n\t\t0x030, 0x00006334,\n\t\t0x030, 0x00007334,\n\t\t0x030, 0x00008334,\n\t\t0x030, 0x00009334,\n\t\t0x030, 0x0000A334,\n\t\t0x030, 0x0000B334,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x030, 0x00000334,\n\t\t0x030, 0x00001334,\n\t\t0x030, 0x00002334,\n\t\t0x030, 0x00003334,\n\t\t0x030, 0x00004334,\n\t\t0x030, 0x00005334,\n\t\t0x030, 0x00006334,\n\t\t0x030, 0x00007334,\n\t\t0x030, 0x00008334,\n\t\t0x030, 0x00009334,\n\t\t0x030, 0x0000A334,\n\t\t0x030, 0x0000B334,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x030, 0x00000334,\n\t\t0x030, 0x00001334,\n\t\t0x030, 0x00002334,\n\t\t0x030, 0x00003334,\n\t\t0x030, 0x00004334,\n\t\t0x030, 0x00005334,\n\t\t0x030, 0x00006334,\n\t\t0x030, 0x00007334,\n\t\t0x030, 0x00008334,\n\t\t0x030, 0x00009334,\n\t\t0x030, 0x0000A334,\n\t\t0x030, 0x0000B334,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x030, 0x00000334,\n\t\t0x030, 0x00001334,\n\t\t0x030, 0x00002334,\n\t\t0x030, 0x00003334,\n\t\t0x030, 0x00004334,\n\t\t0x030, 0x00005334,\n\t\t0x030, 0x00006334,\n\t\t0x030, 0x00007334,\n\t\t0x030, 0x00008334,\n\t\t0x030, 0x00009334,\n\t\t0x030, 0x0000A334,\n\t\t0x030, 0x0000B334,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x030, 0x00000334,\n\t\t0x030, 0x00001334,\n\t\t0x030, 0x00002334,\n\t\t0x030, 0x00003334,\n\t\t0x030, 0x00004334,\n\t\t0x030, 0x00005334,\n\t\t0x030, 0x00006334,\n\t\t0x030, 0x00007334,\n\t\t0x030, 0x00008334,\n\t\t0x030, 0x00009334,\n\t\t0x030, 0x0000A334,\n\t\t0x030, 0x0000B334,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x030, 0x00000334,\n\t\t0x030, 0x00001334,\n\t\t0x030, 0x00002334,\n\t\t0x030, 0x00003334,\n\t\t0x030, 0x00004334,\n\t\t0x030, 0x00005334,\n\t\t0x030, 0x00006334,\n\t\t0x030, 0x00007334,\n\t\t0x030, 0x00008334,\n\t\t0x030, 0x00009334,\n\t\t0x030, 0x0000A334,\n\t\t0x030, 0x0000B334,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x030, 0x00000334,\n\t\t0x030, 0x00001334,\n\t\t0x030, 0x00002334,\n\t\t0x030, 0x00003334,\n\t\t0x030, 0x00004334,\n\t\t0x030, 0x00005334,\n\t\t0x030, 0x00006334,\n\t\t0x030, 0x00007334,\n\t\t0x030, 0x00008334,\n\t\t0x030, 0x00009334,\n\t\t0x030, 0x0000A334,\n\t\t0x030, 0x0000B334,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x030, 0x00000334,\n\t\t0x030, 0x00001334,\n\t\t0x030, 0x00002334,\n\t\t0x030, 0x00003334,\n\t\t0x030, 0x00004334,\n\t\t0x030, 0x00005334,\n\t\t0x030, 0x00006334,\n\t\t0x030, 0x00007334,\n\t\t0x030, 0x00008334,\n\t\t0x030, 0x00009334,\n\t\t0x030, 0x0000A334,\n\t\t0x030, 0x0000B334,\n\t0xA0000000,\t0x00000000,\n\t\t0x030, 0x00000232,\n\t\t0x030, 0x00001232,\n\t\t0x030, 0x00002232,\n\t\t0x030, 0x00003232,\n\t\t0x030, 0x00004232,\n\t\t0x030, 0x00005232,\n\t\t0x030, 0x00006232,\n\t\t0x030, 0x00007232,\n\t\t0x030, 0x00008232,\n\t\t0x030, 0x00009232,\n\t\t0x030, 0x0000A232,\n\t\t0x030, 0x0000B232,\n\t0xB0000000,\t0x00000000,\n\t\t0x0EF, 0x00000000,\n\t\t0x0EF, 0x00000040,\n\t\t0x030, 0x00000770,\n\t\t0x030, 0x00001770,\n\t\t0x030, 0x00002440,\n\t\t0x030, 0x00003440,\n\t\t0x030, 0x00004330,\n\t\t0x030, 0x00005330,\n\t\t0x030, 0x00008770,\n\t\t0x030, 0x0000A440,\n\t\t0x030, 0x0000C330,\n\t\t0x0EF, 0x00000000,\n\t\t0x0EE, 0x00010000,\n\t\t0x033, 0x00000200,\n\t\t0x03F, 0x0000006A,\n\t\t0x033, 0x00000201,\n\t\t0x03F, 0x0000006D,\n\t\t0x033, 0x00000202,\n\t\t0x03F, 0x0000046A,\n\t\t0x033, 0x00000203,\n\t\t0x03F, 0x0000086A,\n\t\t0x033, 0x00000204,\n\t\t0x03F, 0x00000C89,\n\t\t0x033, 0x00000205,\n\t\t0x03F, 0x00000CE8,\n\t\t0x033, 0x00000206,\n\t\t0x03F, 0x00000CEB,\n\t\t0x033, 0x00000207,\n\t\t0x03F, 0x00000CEE,\n\t\t0x033, 0x00000208,\n\t\t0x03F, 0x00000CF1,\n\t\t0x033, 0x00000209,\n\t\t0x03F, 0x00000CF4,\n\t\t0x033, 0x0000020A,\n\t\t0x03F, 0x00000CF7,\n\t\t0x033, 0x00000280,\n\t\t0x03F, 0x0000006A,\n\t\t0x033, 0x00000281,\n\t\t0x03F, 0x0000006D,\n\t\t0x033, 0x00000282,\n\t\t0x03F, 0x0000046A,\n\t\t0x033, 0x00000283,\n\t\t0x03F, 0x0000086A,\n\t\t0x033, 0x00000284,\n\t\t0x03F, 0x00000C89,\n\t\t0x033, 0x00000285,\n\t\t0x03F, 0x00000CE8,\n\t\t0x033, 0x00000286,\n\t\t0x03F, 0x00000CEB,\n\t\t0x033, 0x00000287,\n\t\t0x03F, 0x00000CEE,\n\t\t0x033, 0x00000288,\n\t\t0x03F, 0x00000CF1,\n\t\t0x033, 0x00000289,\n\t\t0x03F, 0x00000CF4,\n\t\t0x033, 0x0000028A,\n\t\t0x03F, 0x00000CF7,\n\t\t0x033, 0x00000300,\n\t\t0x03F, 0x0000006A,\n\t\t0x033, 0x00000301,\n\t\t0x03F, 0x0000006D,\n\t\t0x033, 0x00000302,\n\t\t0x03F, 0x0000046A,\n\t\t0x033, 0x00000303,\n\t\t0x03F, 0x0000086A,\n\t\t0x033, 0x00000304,\n\t\t0x03F, 0x00000C89,\n\t\t0x033, 0x00000305,\n\t\t0x03F, 0x00000CE8,\n\t\t0x033, 0x00000306,\n\t\t0x03F, 0x00000CEB,\n\t\t0x033, 0x00000307,\n\t\t0x03F, 0x00000CEE,\n\t\t0x033, 0x00000308,\n\t\t0x03F, 0x00000CF1,\n\t\t0x033, 0x00000309,\n\t\t0x03F, 0x00000CF4,\n\t\t0x033, 0x0000030A,\n\t\t0x03F, 0x00000CF7,\n\t\t0x0EE, 0x00000000,\n\t\t0x051, 0x0003C800,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x052, 0x000902CA,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x052, 0x000902CA,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x052, 0x000902CA,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x052, 0x000902CA,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x052, 0x000902CA,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x052, 0x000902CA,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x052, 0x000902CA,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x052, 0x000902CA,\n\t0xA0000000,\t0x00000000,\n\t\t0x052, 0x000942CA,\n\t0xB0000000,\t0x00000000,\n\t\t0x053, 0x000090F9,\n\t\t0x054, 0x00088000,\n\t\t0x057, 0x0004C80A,\n\t\t0x0EF, 0x00000020,\n\t\t0x033, 0x00000000,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00010E46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00010E46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00010E46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00010E46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00028246,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00028246,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00028246,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00028246,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00002A46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000001,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00010E46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00010E46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00010E46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00010E46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00028246,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00028246,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00028246,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00028246,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00002A46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000002,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00010E46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00010E46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00010E46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00010E46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00030246,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00030246,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00030246,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00030246,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00002A46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000003,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00010E46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00010E46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00010E46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00010E46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00028246,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00028246,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00028246,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00028246,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00002A46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000004,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 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0x00000020,\n\t\t0x03F, 0x00000468,\n\t\t0x033, 0x00000021,\n\t\t0x03F, 0x00000868,\n\t\t0x033, 0x00000022,\n\t\t0x03F, 0x00000909,\n\t\t0x033, 0x00000023,\n\t\t0x03F, 0x00000D0A,\n\t\t0x033, 0x00000024,\n\t\t0x03F, 0x00000D4A,\n\t\t0x033, 0x00000025,\n\t\t0x03F, 0x00000D8B,\n\t\t0x033, 0x00000026,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000027,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000028,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000029,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000002A,\n\t\t0x03F, 0x00000DF7,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000020,\n\t\t0x03F, 0x00000467,\n\t\t0x033, 0x00000021,\n\t\t0x03F, 0x00000867,\n\t\t0x033, 0x00000022,\n\t\t0x03F, 0x00000908,\n\t\t0x033, 0x00000023,\n\t\t0x03F, 0x00000D09,\n\t\t0x033, 0x00000024,\n\t\t0x03F, 0x00000D49,\n\t\t0x033, 0x00000025,\n\t\t0x03F, 0x00000D8A,\n\t\t0x033, 0x00000026,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000027,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000028,\n\t\t0x03F, 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0x00000025,\n\t\t0x03F, 0x00000D8A,\n\t\t0x033, 0x00000026,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000027,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000028,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000029,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000002A,\n\t\t0x03F, 0x00000DF7,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000020,\n\t\t0x03F, 0x00000467,\n\t\t0x033, 0x00000021,\n\t\t0x03F, 0x00000867,\n\t\t0x033, 0x00000022,\n\t\t0x03F, 0x00000908,\n\t\t0x033, 0x00000023,\n\t\t0x03F, 0x00000D09,\n\t\t0x033, 0x00000024,\n\t\t0x03F, 0x00000D49,\n\t\t0x033, 0x00000025,\n\t\t0x03F, 0x00000D8A,\n\t\t0x033, 0x00000026,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000027,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000028,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000029,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000002A,\n\t\t0x03F, 0x00000DF7,\n\t0xA0000000,\t0x00000000,\n\t\t0x033, 0x00000020,\n\t\t0x03F, 0x00000487,\n\t\t0x033, 0x00000021,\n\t\t0x03F, 0x00000887,\n\t\t0x033, 0x00000022,\n\t\t0x03F, 0x00000947,\n\t\t0x033, 0x00000023,\n\t\t0x03F, 0x00000D48,\n\t\t0x033, 0x00000024,\n\t\t0x03F, 0x00000D88,\n\t\t0x033, 0x00000025,\n\t\t0x03F, 0x00000DE8,\n\t\t0x033, 0x00000026,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000027,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000028,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000029,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000002A,\n\t\t0x03F, 0x00000DF7,\n\t0xB0000000,\t0x00000000,\n\t\t0x0EE, 0x00000000,\n\t\t0x05C, 0x000FCC00,\n\t\t0x067, 0x0000A505,\n\t\t0x0D3, 0x00000542,\n\t\t0x043, 0x00005000,\n\t\t0x07F, 0x00000000,\n\t\t0x0B0, 0x0001F0FC,\n\t\t0x0B1, 0x0007DBE4,\n\t\t0x0B2, 0x00022400,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x0007C760,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x0007C760,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x0007C760,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x0007C760,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x000FC760,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x000FC760,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x000FC760,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x000FC760,\n\t0xA0000000,\t0x00000000,\n\t\t0x0B3, 0x0007C760,\n\t0xB0000000,\t0x00000000,\n\t\t0x0B4, 0x00099D40,\n\t\t0x0B5, 0x0004103F,\n\t0x83000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B6, 0x000387F8,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B6, 0x000387F8,\n\t0xA0000000,\t0x00000000,\n\t\t0x0B6, 0x000187F8,\n\t0xB0000000,\t0x00000000,\n\t\t0x0B7, 0x00030018,\n\t\t0x0BC, 0x00000008,\n\t\t0x0D3, 0x00000542,\n\t\t0x0DD, 0x00000500,\n\t\t0x0BB, 0x00040010,\n\t\t0x0B0, 0x0001F0FA,\n\t\t0x0FE, 0x00000000,\n\t\t0x0CA, 0x00080000,\n\t\t0x0CA, 0x00080001,\n\t\t0x0FE, 0x00000000,\n\t\t0x0B0, 0x0001F0F8,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x0007C700,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x0007C700,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x0007C700,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x0007C700,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x000FC760,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x000FC760,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x000FC760,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x000FC760,\n\t0xA0000000,\t0x00000000,\n\t\t0x0B3, 0x0007C700,\n\t0xB0000000,\t0x00000000,\n\t\t0x018, 0x0001B124,\n\t\t0xFFE, 0x00000000,\n\t\t0xFFE, 0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x0007C760,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x0007C760,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x0007C760,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x0007C760,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x000FC760,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x000FC760,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x000FC760,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0B3, 0x000FC760,\n\t0xA0000000,\t0x00000000,\n\t\t0x0B3, 0x0007C760,\n\t0xB0000000,\t0x00000000,\n\t\t0x018, 0x00013124,\n\t\t0x0CC, 0x0000F000,\n\t\t0x0CD, 0x00089600,\n\t\t0x018, 0x00013108,\n\t\t0x0FE, 0x00000000,\n\t\t0x0FE, 0x00000000,\n\t\t0x0B8, 0x000C0440,\n\t\t0x0BA, 0x000E840D,\n\t\t0x0FE, 0x00000000,\n\t\t0x0FE, 0x00000000,\n\t\t0x018, 0x00013124,\n\t\t0x0FE, 0x00000000,\n\t\t0x0FE, 0x00000000,\n\t\t0x059, 0x000A0000,\n\t\t0x05A, 0x00060000,\n\t\t0x05B, 0x00014000,\n\t\t0x0ED, 0x00000008,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000000F,\n\t\t0x0ED, 0x00000000,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0DD, 0x00000540,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0DD, 0x00000540,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0DD, 0x00000540,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0DD, 0x00000540,\n\t0xA0000000,\t0x00000000,\n\t\t0x0DD, 0x00000500,\n\t0xB0000000,\t0x00000000,\n\t\t0x0BC, 0x00000004,\n\t\t0x0EE, 0x00000002,\n\t\t0x033, 0x00000017,\n\t\t0x03F, 0x0000003F,\n\t\t0x033, 0x00000018,\n\t\t0x03F, 0x0000003F,\n\t\t0x033, 0x00000019,\n\t\t0x03F, 0x00000000,\n\t\t0x033, 0x0000001A,\n\t\t0x03F, 0x0000003F,\n\t\t0x033, 0x0000001B,\n\t\t0x03F, 0x0000003F,\n\t\t0x033, 0x0000001C,\n\t\t0x03F, 0x0000003F,\n\t\t0x0EE, 0x00000000,\n\t\t0x0ED, 0x00000200,\n\t\t0x033, 0x00000000,\n\t\t0x03F, 0x000F45A4,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x000F49A4,\n\t\t0x033, 0x00000002,\n\t\t0x03F, 0x000F49A4,\n\t\t0x033, 0x00000003,\n\t\t0x03F, 0x000F69A4,\n\t\t0x033, 0x00000004,\n\t\t0x03F, 0x000F69A4,\n\t\t0x033, 0x00000005,\n\t\t0x03F, 0x000F69A4,\n\t\t0x033, 0x00000006,\n\t\t0x03F, 0x000F6DA4,\n\t\t0x033, 0x00000007,\n\t\t0x03F, 0x000F6DA4,\n\t\t0x033, 0x00000008,\n\t\t0x03F, 0x000F6DA4,\n\t\t0x033, 0x00000009,\n\t\t0x03F, 0x000F8DA4,\n\t\t0x033, 0x0000000A,\n\t\t0x03F, 0x000F8DA4,\n\t\t0x033, 0x0000000B,\n\t\t0x03F, 0x000F8DA4,\n\t\t0x033, 0x0000000C,\n\t\t0x03F, 0x000F91A4,\n\t\t0x033, 0x0000000D,\n\t\t0x03F, 0x000F91A4,\n\t\t0x033, 0x0000000E,\n\t\t0x03F, 0x000F91A4,\n\t\t0x033, 0x0000000F,\n\t\t0x03F, 0x000FB1A4,\n\t\t0x033, 0x00000010,\n\t\t0x03F, 0x000FB1A4,\n\t\t0x033, 0x00000011,\n\t\t0x03F, 0x000FB1A4,\n\t\t0x033, 0x00000012,\n\t\t0x03F, 0x000FB5A4,\n\t\t0x033, 0x00000013,\n\t\t0x03F, 0x000FB5A4,\n\t\t0x033, 0x00000014,\n\t\t0x03F, 0x000FD9A4,\n\t\t0x033, 0x00000015,\n\t\t0x03F, 0x000FD9A4,\n\t\t0x033, 0x00000016,\n\t\t0x03F, 0x000FF9A4,\n\t\t0x033, 0x00000017,\n\t\t0x03F, 0x000FF9A4,\n\t\t0x033, 0x00000018,\n\t\t0x03F, 0x000FFDA4,\n\t\t0x033, 0x00000019,\n\t\t0x03F, 0x000FFDA4,\n\t\t0x033, 0x0000001A,\n\t\t0x03F, 0x000FFDA4,\n\t\t0x0ED, 0x00000000,\n\t\t0x092, 0x00084800,\n\t\t0x092, 0x00084801,\n\t\t0x0FE, 0x00000000,\n\t\t0x0FE, 0x00000000,\n\t\t0x0FE, 0x00000000,\n\t\t0x0FE, 0x00000000,\n\t\t0x092, 0x00084800,\n\t\t0x08F, 0x00001B4C,\n\t\t0x088, 0x0004326B,\n\t\t0x019, 0x00000005,\n\t\t0x0EF, 0x00080000,\n\t\t0x033, 0x00000004,\n\t\t0x03E, 0x00000003,\n\t\t0x03F, 0x000F60FF,\n\t\t0x0EF, 0x00000000,\n\t\t0x0EF, 0x00080000,\n\t\t0x033, 0x00000006,\n\t\t0x03E, 0x00000003,\n\t\t0x03F, 0x000760FF,\n\t\t0x0EF, 0x00000000,\n\t\t0x0EF, 0x00080000,\n\t\t0x033, 0x00000007,\n\t\t0x03E, 0x00000003,\n\t\t0x03F, 0x0007DEFF,\n\t\t0x0EF, 0x00000000,\n\n};\n\nvoid\nodm_read_and_config_mp_8822c_radioa(struct dm_struct *dm)\n{\n\tu32\ti = 0;\n\tu8\tc_cond;\n\tboolean\tis_matched = true, is_skipped = false;\n\tu32\tarray_len =\n\t\t\tsizeof(array_mp_8822c_radioa) / sizeof(u32);\n\tu32\t*array = (u32 *)array_mp_8822c_radioa;\n\n\tu32\tv1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;\n\tu32\ta1 = 0, a2 = 0, a3 = 0, a4 = 0;\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"===> %s\\n\", __func__);\n\n\twhile ((i + 1) < array_len) {\n\t\tv1 = array[i];\n\t\tv2 = array[i + 1];\n\n\t\tif (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/\n\t\t\tif (v1 & BIT(31)) {/* positive condition*/\n\t\t\t\tc_cond  =\n\t\t\t\t\t(u8)((v1 & (BIT(29) | BIT(28))) >> 28);\n\t\t\t\tif (c_cond == COND_ENDIF) {/*end*/\n\t\t\t\t\tis_matched = true;\n\t\t\t\t\tis_skipped = false;\n\t\t\t\t\tPHYDM_DBG(dm, ODM_COMP_INIT, \"ENDIF\\n\");\n\t\t\t\t} else if (c_cond == COND_ELSE) { /*else*/\n\t\t\t\t\tis_matched = is_skipped ? false : true;\n\t\t\t\t\tPHYDM_DBG(dm, ODM_COMP_INIT, \"ELSE\\n\");\n\t\t\t\t} else {/*if , else if*/\n\t\t\t\t\tpre_v1 = v1;\n\t\t\t\t\tpre_v2 = v2;\n\t\t\t\t\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t\t\t\t\t  \"IF or ELSE IF\\n\");\n\t\t\t\t}\n\t\t\t} else if (v1 & BIT(30)) { /*negative condition*/\n\t\t\t\tif (!is_skipped) {\n\t\t\t\t\ta1 = pre_v1; a2 = pre_v2;\n\t\t\t\t\ta3 = v1; a4 = v2;\n\t\t\t\t\tif (check_positive(dm,\n\t\t\t\t\t\t\t   a1, a2, a3, a4)) {\n\t\t\t\t\t\tis_matched = true;\n\t\t\t\t\t\tis_skipped = true;\n\t\t\t\t\t} else {\n\t\t\t\t\t\tis_matched = false;\n\t\t\t\t\t\tis_skipped = false;\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tis_matched = false;\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tif (is_matched)\n\t\t\t\todm_config_rf_radio_a_8822c(dm, v1, v2);\n\t\t}\n\t\ti = i + 2;\n\t}\n}\n\nu32\nodm_get_version_mp_8822c_radioa(void)\n{\n\t\treturn 41;\n}\n\n/******************************************************************************\n *                           radiob.TXT\n ******************************************************************************/\n\nconst u32 array_mp_8822c_radiob[] = {\n\t\t0x000, 0x00030000,\n\t\t0x018, 0x00013124,\n\t\t0x093, 0x0008483F,\n\t\t0x0EF, 0x00080000,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x00091230,\n\t\t0x0EF, 0x00000000,\n\t\t0x0DE, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x08E, 0x000B9140,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x08E, 0x000B9140,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x08E, 0x000A5540,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x08E, 0x000A5540,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x08E, 0x000A5540,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x08E, 0x000A5540,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x08E, 0x000A5540,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x08E, 0x000A5540,\n\t0xA0000000,\t0x00000000,\n\t\t0x08E, 0x000A5540,\n\t0xB0000000,\t0x00000000,\n\t\t0x081, 0x0000FC01,\n\t\t0x081, 0x0002FC01,\n\t\t0x081, 0x0003FC01,\n\t\t0x085, 0x0006A06C,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EE, 0x00000010,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000002,\n\t\t0x03F, 0x0000002A,\n\t\t0x0EE, 0x00000000,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EE, 0x00000010,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000002,\n\t\t0x03F, 0x0000002A,\n\t\t0x0EE, 0x00000000,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EE, 0x00000010,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000002,\n\t\t0x03F, 0x0000002A,\n\t\t0x0EE, 0x00000000,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EE, 0x00000010,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 0x00000002,\n\t\t0x03F, 0x0000002A,\n\t\t0x0EE, 0x00000000,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x0EE, 0x00000010,\n\t\t0x033, 0x00000001,\n\t\t0x03F, 0x0000002A,\n\t\t0x033, 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0x00002334,\n\t\t0x030, 0x00003334,\n\t\t0x030, 0x00004334,\n\t\t0x030, 0x00005334,\n\t\t0x030, 0x00006334,\n\t\t0x030, 0x00007334,\n\t\t0x030, 0x00008334,\n\t\t0x030, 0x00009334,\n\t\t0x030, 0x0000A334,\n\t\t0x030, 0x0000B334,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x030, 0x00000334,\n\t\t0x030, 0x00001334,\n\t\t0x030, 0x00002334,\n\t\t0x030, 0x00003334,\n\t\t0x030, 0x00004334,\n\t\t0x030, 0x00005334,\n\t\t0x030, 0x00006334,\n\t\t0x030, 0x00007334,\n\t\t0x030, 0x00008334,\n\t\t0x030, 0x00009334,\n\t\t0x030, 0x0000A334,\n\t\t0x030, 0x0000B334,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x030, 0x00000334,\n\t\t0x030, 0x00001334,\n\t\t0x030, 0x00002334,\n\t\t0x030, 0x00003334,\n\t\t0x030, 0x00004334,\n\t\t0x030, 0x00005334,\n\t\t0x030, 0x00006334,\n\t\t0x030, 0x00007334,\n\t\t0x030, 0x00008334,\n\t\t0x030, 0x00009334,\n\t\t0x030, 0x0000A334,\n\t\t0x030, 0x0000B334,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x030, 0x00000334,\n\t\t0x030, 0x00001334,\n\t\t0x030, 0x00002334,\n\t\t0x030, 0x00003334,\n\t\t0x030, 0x00004334,\n\t\t0x030, 0x00005334,\n\t\t0x030, 0x00006334,\n\t\t0x030, 0x00007334,\n\t\t0x030, 0x00008334,\n\t\t0x030, 0x00009334,\n\t\t0x030, 0x0000A334,\n\t\t0x030, 0x0000B334,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x030, 0x00000334,\n\t\t0x030, 0x00001334,\n\t\t0x030, 0x00002334,\n\t\t0x030, 0x00003334,\n\t\t0x030, 0x00004334,\n\t\t0x030, 0x00005334,\n\t\t0x030, 0x00006334,\n\t\t0x030, 0x00007334,\n\t\t0x030, 0x00008334,\n\t\t0x030, 0x00009334,\n\t\t0x030, 0x0000A334,\n\t\t0x030, 0x0000B334,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x030, 0x00000334,\n\t\t0x030, 0x00001334,\n\t\t0x030, 0x00002334,\n\t\t0x030, 0x00003334,\n\t\t0x030, 0x00004334,\n\t\t0x030, 0x00005334,\n\t\t0x030, 0x00006334,\n\t\t0x030, 0x00007334,\n\t\t0x030, 0x00008334,\n\t\t0x030, 0x00009334,\n\t\t0x030, 0x0000A334,\n\t\t0x030, 0x0000B334,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x030, 0x00000334,\n\t\t0x030, 0x00001334,\n\t\t0x030, 0x00002334,\n\t\t0x030, 0x00003334,\n\t\t0x030, 0x00004334,\n\t\t0x030, 0x00005334,\n\t\t0x030, 0x00006334,\n\t\t0x030, 0x00007334,\n\t\t0x030, 0x00008334,\n\t\t0x030, 0x00009334,\n\t\t0x030, 0x0000A334,\n\t\t0x030, 0x0000B334,\n\t0xA0000000,\t0x00000000,\n\t\t0x030, 0x00000232,\n\t\t0x030, 0x00001232,\n\t\t0x030, 0x00002232,\n\t\t0x030, 0x00003232,\n\t\t0x030, 0x00004232,\n\t\t0x030, 0x00005232,\n\t\t0x030, 0x00006232,\n\t\t0x030, 0x00007232,\n\t\t0x030, 0x00008232,\n\t\t0x030, 0x00009232,\n\t\t0x030, 0x0000A232,\n\t\t0x030, 0x0000B232,\n\t0xB0000000,\t0x00000000,\n\t\t0x0EF, 0x00000000,\n\t\t0x0EF, 0x00000040,\n\t\t0x030, 0x00000770,\n\t\t0x030, 0x00001770,\n\t\t0x030, 0x00002440,\n\t\t0x030, 0x00003440,\n\t\t0x030, 0x00004330,\n\t\t0x030, 0x00005330,\n\t\t0x030, 0x00008770,\n\t\t0x030, 0x0000A440,\n\t\t0x030, 0x0000C330,\n\t\t0x0EF, 0x00000000,\n\t\t0x0EE, 0x00010000,\n\t\t0x033, 0x00000200,\n\t\t0x03F, 0x0000006A,\n\t\t0x033, 0x00000201,\n\t\t0x03F, 0x0000006D,\n\t\t0x033, 0x00000202,\n\t\t0x03F, 0x0000046A,\n\t\t0x033, 0x00000203,\n\t\t0x03F, 0x0000086A,\n\t\t0x033, 0x00000204,\n\t\t0x03F, 0x00000C89,\n\t\t0x033, 0x00000205,\n\t\t0x03F, 0x00000CE8,\n\t\t0x033, 0x00000206,\n\t\t0x03F, 0x00000CEB,\n\t\t0x033, 0x00000207,\n\t\t0x03F, 0x00000CEE,\n\t\t0x033, 0x00000208,\n\t\t0x03F, 0x00000CF1,\n\t\t0x033, 0x00000209,\n\t\t0x03F, 0x00000CF4,\n\t\t0x033, 0x0000020A,\n\t\t0x03F, 0x00000CF7,\n\t\t0x033, 0x00000280,\n\t\t0x03F, 0x0000006A,\n\t\t0x033, 0x00000281,\n\t\t0x03F, 0x0000006D,\n\t\t0x033, 0x00000282,\n\t\t0x03F, 0x0000046A,\n\t\t0x033, 0x00000283,\n\t\t0x03F, 0x0000086A,\n\t\t0x033, 0x00000284,\n\t\t0x03F, 0x00000C89,\n\t\t0x033, 0x00000285,\n\t\t0x03F, 0x00000CE8,\n\t\t0x033, 0x00000286,\n\t\t0x03F, 0x00000CEB,\n\t\t0x033, 0x00000287,\n\t\t0x03F, 0x00000CEE,\n\t\t0x033, 0x00000288,\n\t\t0x03F, 0x00000CF1,\n\t\t0x033, 0x00000289,\n\t\t0x03F, 0x00000CF4,\n\t\t0x033, 0x0000028A,\n\t\t0x03F, 0x00000CF7,\n\t\t0x033, 0x00000300,\n\t\t0x03F, 0x0000006A,\n\t\t0x033, 0x00000301,\n\t\t0x03F, 0x0000006D,\n\t\t0x033, 0x00000302,\n\t\t0x03F, 0x0000046A,\n\t\t0x033, 0x00000303,\n\t\t0x03F, 0x0000086A,\n\t\t0x033, 0x00000304,\n\t\t0x03F, 0x00000C89,\n\t\t0x033, 0x00000305,\n\t\t0x03F, 0x00000CE8,\n\t\t0x033, 0x00000306,\n\t\t0x03F, 0x00000CEB,\n\t\t0x033, 0x00000307,\n\t\t0x03F, 0x00000CEE,\n\t\t0x033, 0x00000308,\n\t\t0x03F, 0x00000CF1,\n\t\t0x033, 0x00000309,\n\t\t0x03F, 0x00000CF4,\n\t\t0x033, 0x0000030A,\n\t\t0x03F, 0x00000CF7,\n\t\t0x0EE, 0x00000000,\n\t\t0x051, 0x0003C800,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x052, 0x000902CA,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x052, 0x000902CA,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x052, 0x000902CA,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x052, 0x000902CA,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x052, 0x000902CA,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x052, 0x000902CA,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x052, 0x000902CA,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x052, 0x000902CA,\n\t0xA0000000,\t0x00000000,\n\t\t0x052, 0x000942C0,\n\t0xB0000000,\t0x00000000,\n\t\t0x053, 0x000090F9,\n\t\t0x054, 0x00088000,\n\t\t0x057, 0x0004C80A,\n\t\t0x0EF, 0x00000020,\n\t\t0x033, 0x00000000,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x0000C246,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000001,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x0000C246,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000002,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x0000C246,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000003,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x0000C246,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000004,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x0000C246,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000005,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x0000C246,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000006,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 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0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x0000C246,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000008,\n\t\t0x03E, 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0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x0000000B,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x0000000C,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x0000000D,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x0000000E,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x0000000F,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000010,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000241C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000011,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x00024246,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002C246,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000012,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000013,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000014,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000015,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000016,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000017,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000018,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000019,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x0000001A,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x0000001B,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x0000001C,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x0000001D,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x0000001E,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x0000001F,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000020,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000021,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000022,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000023,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000024,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000025,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000026,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000027,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000028,\n\t0x83000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03E, 0x00000030,\n\t0xA0000000,\t0x00000000,\n\t\t0x03E, 0x00000020,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x000209C6,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x00000029,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0002CA46,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x033, 0x0000002A,\n\t\t0x03E, 0x00000020,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x03F, 0x0001CA46,\n\t0xA0000000,\t0x00000000,\n\t\t0x03F, 0x00008E46,\n\t0xB0000000,\t0x00000000,\n\t\t0x0EF, 0x00000000,\n\t\t0x0EE, 0x00010000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000060,\n\t\t0x03F, 0x00000468,\n\t\t0x033, 0x00000061,\n\t\t0x03F, 0x00000868,\n\t\t0x033, 0x00000062,\n\t\t0x03F, 0x00000909,\n\t\t0x033, 0x00000063,\n\t\t0x03F, 0x00000D0A,\n\t\t0x033, 0x00000064,\n\t\t0x03F, 0x00000D4A,\n\t\t0x033, 0x00000065,\n\t\t0x03F, 0x00000D8B,\n\t\t0x033, 0x00000066,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000067,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000068,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000069,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000006A,\n\t\t0x03F, 0x00000DF7,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000060,\n\t\t0x03F, 0x00000468,\n\t\t0x033, 0x00000061,\n\t\t0x03F, 0x00000868,\n\t\t0x033, 0x00000062,\n\t\t0x03F, 0x00000909,\n\t\t0x033, 0x00000063,\n\t\t0x03F, 0x00000D0A,\n\t\t0x033, 0x00000064,\n\t\t0x03F, 0x00000D4A,\n\t\t0x033, 0x00000065,\n\t\t0x03F, 0x00000D8B,\n\t\t0x033, 0x00000066,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000067,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000068,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000069,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000006A,\n\t\t0x03F, 0x00000DF7,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000060,\n\t\t0x03F, 0x00000468,\n\t\t0x033, 0x00000061,\n\t\t0x03F, 0x00000868,\n\t\t0x033, 0x00000062,\n\t\t0x03F, 0x00000909,\n\t\t0x033, 0x00000063,\n\t\t0x03F, 0x00000D0A,\n\t\t0x033, 0x00000064,\n\t\t0x03F, 0x00000D4A,\n\t\t0x033, 0x00000065,\n\t\t0x03F, 0x00000D8B,\n\t\t0x033, 0x00000066,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000067,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000068,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000069,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000006A,\n\t\t0x03F, 0x00000DF7,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000060,\n\t\t0x03F, 0x00000468,\n\t\t0x033, 0x00000061,\n\t\t0x03F, 0x00000868,\n\t\t0x033, 0x00000062,\n\t\t0x03F, 0x00000909,\n\t\t0x033, 0x00000063,\n\t\t0x03F, 0x00000D0A,\n\t\t0x033, 0x00000064,\n\t\t0x03F, 0x00000D4A,\n\t\t0x033, 0x00000065,\n\t\t0x03F, 0x00000D8B,\n\t\t0x033, 0x00000066,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000067,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000068,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000069,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000006A,\n\t\t0x03F, 0x00000DF7,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000060,\n\t\t0x03F, 0x00000467,\n\t\t0x033, 0x00000061,\n\t\t0x03F, 0x00000867,\n\t\t0x033, 0x00000062,\n\t\t0x03F, 0x00000908,\n\t\t0x033, 0x00000063,\n\t\t0x03F, 0x00000D09,\n\t\t0x033, 0x00000064,\n\t\t0x03F, 0x00000D49,\n\t\t0x033, 0x00000065,\n\t\t0x03F, 0x00000D8A,\n\t\t0x033, 0x00000066,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000067,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000068,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000069,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000006A,\n\t\t0x03F, 0x00000DF7,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000060,\n\t\t0x03F, 0x00000467,\n\t\t0x033, 0x00000061,\n\t\t0x03F, 0x00000867,\n\t\t0x033, 0x00000062,\n\t\t0x03F, 0x00000908,\n\t\t0x033, 0x00000063,\n\t\t0x03F, 0x00000D09,\n\t\t0x033, 0x00000064,\n\t\t0x03F, 0x00000D49,\n\t\t0x033, 0x00000065,\n\t\t0x03F, 0x00000D8A,\n\t\t0x033, 0x00000066,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000067,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000068,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000069,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000006A,\n\t\t0x03F, 0x00000DF7,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000060,\n\t\t0x03F, 0x00000467,\n\t\t0x033, 0x00000061,\n\t\t0x03F, 0x00000867,\n\t\t0x033, 0x00000062,\n\t\t0x03F, 0x00000908,\n\t\t0x033, 0x00000063,\n\t\t0x03F, 0x00000D09,\n\t\t0x033, 0x00000064,\n\t\t0x03F, 0x00000D49,\n\t\t0x033, 0x00000065,\n\t\t0x03F, 0x00000D8A,\n\t\t0x033, 0x00000066,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000067,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000068,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000069,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000006A,\n\t\t0x03F, 0x00000DF7,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000060,\n\t\t0x03F, 0x00000467,\n\t\t0x033, 0x00000061,\n\t\t0x03F, 0x00000867,\n\t\t0x033, 0x00000062,\n\t\t0x03F, 0x00000908,\n\t\t0x033, 0x00000063,\n\t\t0x03F, 0x00000D09,\n\t\t0x033, 0x00000064,\n\t\t0x03F, 0x00000D49,\n\t\t0x033, 0x00000065,\n\t\t0x03F, 0x00000D8A,\n\t\t0x033, 0x00000066,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000067,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000068,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000069,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000006A,\n\t\t0x03F, 0x00000DF7,\n\t0xA0000000,\t0x00000000,\n\t\t0x033, 0x00000060,\n\t\t0x03F, 0x00000487,\n\t\t0x033, 0x00000061,\n\t\t0x03F, 0x00000887,\n\t\t0x033, 0x00000062,\n\t\t0x03F, 0x00000947,\n\t\t0x033, 0x00000063,\n\t\t0x03F, 0x00000D48,\n\t\t0x033, 0x00000064,\n\t\t0x03F, 0x00000D88,\n\t\t0x033, 0x00000065,\n\t\t0x03F, 0x00000DE8,\n\t\t0x033, 0x00000066,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000067,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000068,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000069,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000006A,\n\t\t0x03F, 0x00000DF7,\n\t0xB0000000,\t0x00000000,\n\t0x81000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000020,\n\t\t0x03F, 0x00000468,\n\t\t0x033, 0x00000021,\n\t\t0x03F, 0x00000868,\n\t\t0x033, 0x00000022,\n\t\t0x03F, 0x00000909,\n\t\t0x033, 0x00000023,\n\t\t0x03F, 0x00000D0A,\n\t\t0x033, 0x00000024,\n\t\t0x03F, 0x00000D4A,\n\t\t0x033, 0x00000025,\n\t\t0x03F, 0x00000D8B,\n\t\t0x033, 0x00000026,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000027,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000028,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000029,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000002A,\n\t\t0x03F, 0x00000DF7,\n\t0x91000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000020,\n\t\t0x03F, 0x00000468,\n\t\t0x033, 0x00000021,\n\t\t0x03F, 0x00000868,\n\t\t0x033, 0x00000022,\n\t\t0x03F, 0x00000909,\n\t\t0x033, 0x00000023,\n\t\t0x03F, 0x00000D0A,\n\t\t0x033, 0x00000024,\n\t\t0x03F, 0x00000D4A,\n\t\t0x033, 0x00000025,\n\t\t0x03F, 0x00000D8B,\n\t\t0x033, 0x00000026,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000027,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000028,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000029,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000002A,\n\t\t0x03F, 0x00000DF7,\n\t0x92000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000020,\n\t\t0x03F, 0x00000468,\n\t\t0x033, 0x00000021,\n\t\t0x03F, 0x00000868,\n\t\t0x033, 0x00000022,\n\t\t0x03F, 0x00000909,\n\t\t0x033, 0x00000023,\n\t\t0x03F, 0x00000D0A,\n\t\t0x033, 0x00000024,\n\t\t0x03F, 0x00000D4A,\n\t\t0x033, 0x00000025,\n\t\t0x03F, 0x00000D8B,\n\t\t0x033, 0x00000026,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000027,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000028,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000029,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000002A,\n\t\t0x03F, 0x00000DF7,\n\t0x92000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000020,\n\t\t0x03F, 0x00000468,\n\t\t0x033, 0x00000021,\n\t\t0x03F, 0x00000868,\n\t\t0x033, 0x00000022,\n\t\t0x03F, 0x00000909,\n\t\t0x033, 0x00000023,\n\t\t0x03F, 0x00000D0A,\n\t\t0x033, 0x00000024,\n\t\t0x03F, 0x00000D4A,\n\t\t0x033, 0x00000025,\n\t\t0x03F, 0x00000D8B,\n\t\t0x033, 0x00000026,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000027,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000028,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000029,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000002A,\n\t\t0x03F, 0x00000DF7,\n\t0x93000001,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000020,\n\t\t0x03F, 0x00000467,\n\t\t0x033, 0x00000021,\n\t\t0x03F, 0x00000867,\n\t\t0x033, 0x00000022,\n\t\t0x03F, 0x00000908,\n\t\t0x033, 0x00000023,\n\t\t0x03F, 0x00000D09,\n\t\t0x033, 0x00000024,\n\t\t0x03F, 0x00000D49,\n\t\t0x033, 0x00000025,\n\t\t0x03F, 0x00000D8A,\n\t\t0x033, 0x00000026,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000027,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000028,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000029,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000002A,\n\t\t0x03F, 0x00000DF7,\n\t0x93000002,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000020,\n\t\t0x03F, 0x00000467,\n\t\t0x033, 0x00000021,\n\t\t0x03F, 0x00000867,\n\t\t0x033, 0x00000022,\n\t\t0x03F, 0x00000908,\n\t\t0x033, 0x00000023,\n\t\t0x03F, 0x00000D09,\n\t\t0x033, 0x00000024,\n\t\t0x03F, 0x00000D49,\n\t\t0x033, 0x00000025,\n\t\t0x03F, 0x00000D8A,\n\t\t0x033, 0x00000026,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000027,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000028,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000029,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000002A,\n\t\t0x03F, 0x00000DF7,\n\t0x93000003,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000020,\n\t\t0x03F, 0x00000467,\n\t\t0x033, 0x00000021,\n\t\t0x03F, 0x00000867,\n\t\t0x033, 0x00000022,\n\t\t0x03F, 0x00000908,\n\t\t0x033, 0x00000023,\n\t\t0x03F, 0x00000D09,\n\t\t0x033, 0x00000024,\n\t\t0x03F, 0x00000D49,\n\t\t0x033, 0x00000025,\n\t\t0x03F, 0x00000D8A,\n\t\t0x033, 0x00000026,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000027,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000028,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000029,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000002A,\n\t\t0x03F, 0x00000DF7,\n\t0x93000004,\t0x00000000,\t0x40000000,\t0x00000000,\n\t\t0x033, 0x00000020,\n\t\t0x03F, 0x00000467,\n\t\t0x033, 0x00000021,\n\t\t0x03F, 0x00000867,\n\t\t0x033, 0x00000022,\n\t\t0x03F, 0x00000908,\n\t\t0x033, 0x00000023,\n\t\t0x03F, 0x00000D09,\n\t\t0x033, 0x00000024,\n\t\t0x03F, 0x00000D49,\n\t\t0x033, 0x00000025,\n\t\t0x03F, 0x00000D8A,\n\t\t0x033, 0x00000026,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000027,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000028,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000029,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000002A,\n\t\t0x03F, 0x00000DF7,\n\t0xA0000000,\t0x00000000,\n\t\t0x033, 0x00000020,\n\t\t0x03F, 0x00000487,\n\t\t0x033, 0x00000021,\n\t\t0x03F, 0x00000887,\n\t\t0x033, 0x00000022,\n\t\t0x03F, 0x00000947,\n\t\t0x033, 0x00000023,\n\t\t0x03F, 0x00000D48,\n\t\t0x033, 0x00000024,\n\t\t0x03F, 0x00000D88,\n\t\t0x033, 0x00000025,\n\t\t0x03F, 0x00000DE8,\n\t\t0x033, 0x00000026,\n\t\t0x03F, 0x00000DEB,\n\t\t0x033, 0x00000027,\n\t\t0x03F, 0x00000DEE,\n\t\t0x033, 0x00000028,\n\t\t0x03F, 0x00000DF1,\n\t\t0x033, 0x00000029,\n\t\t0x03F, 0x00000DF4,\n\t\t0x033, 0x0000002A,\n\t\t0x03F, 0x00000DF7,\n\t0xB0000000,\t0x00000000,\n\t\t0x0EE, 0x00000000,\n\t\t0x05C, 0x000FCC00,\n\t\t0x067, 0x0000A505,\n\t\t0x0D3, 0x00000542,\n\t\t0x043, 0x00005000,\n\t\t0x059, 0x000A0000,\n\t\t0x05A, 0x00060000,\n\t\t0x05B, 0x00014000,\n\t\t0x001, 0x00040000,\n\t\t0x0EE, 0x00000002,\n\t\t0x033, 0x00000017,\n\t\t0x03F, 0x0000003F,\n\t\t0x033, 0x00000018,\n\t\t0x03F, 0x0000003F,\n\t\t0x033, 0x00000019,\n\t\t0x03F, 0x00000000,\n\t\t0x033, 0x0000001A,\n\t\t0x03F, 0x0000003F,\n\t\t0x033, 0x0000001B,\n\t\t0x03F, 0x0000003F,\n\t\t0x033, 0x0000001C,\n\t\t0x03F, 0x0000003F,\n\t\t0x0EE, 0x00000000,\n\t\t0x092, 0x00084800,\n\t\t0x092, 0x00084801,\n\t\t0x0FE, 0x00000000,\n\t\t0x0FE, 0x00000000,\n\t\t0x0FE, 0x00000000,\n\t\t0x0FE, 0x00000000,\n\t\t0x092, 0x00084800,\n\t\t0x08F, 0x00001B4C,\n\t\t0x088, 0x0004326B,\n\t\t0x019, 0x00000005,\n\t\t0x0EF, 0x00080000,\n\t\t0x033, 0x00000004,\n\t\t0x03F, 0x000FD83F,\n\t\t0x0EF, 0x00000000,\n\t\t0x0EF, 0x00080000,\n\t\t0x033, 0x00000006,\n\t\t0x03F, 0x000DD83F,\n\t\t0x0EF, 0x00000000,\n\t\t0x0EF, 0x00080000,\n\t\t0x033, 0x00000007,\n\t\t0x03F, 0x000DF7BF,\n\t\t0x0EF, 0x00000000,\n\t\t0x0EF, 0x00040000,\n\t\t0x033, 0x00000006,\n\t\t0x03F, 0x00000002,\n\t\t0x033, 0x00000007,\n\t\t0x03F, 0x00000002,\n\t\t0x0EF, 0x00000000,\n\n};\n\nvoid\nodm_read_and_config_mp_8822c_radiob(struct dm_struct *dm)\n{\n\tu32\ti = 0;\n\tu8\tc_cond;\n\tboolean\tis_matched = true, is_skipped = false;\n\tu32\tarray_len =\n\t\t\tsizeof(array_mp_8822c_radiob) / sizeof(u32);\n\tu32\t*array = (u32 *)array_mp_8822c_radiob;\n\n\tu32\tv1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;\n\tu32\ta1 = 0, a2 = 0, a3 = 0, a4 = 0;\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"===> %s\\n\", __func__);\n\n\twhile ((i + 1) < array_len) {\n\t\tv1 = array[i];\n\t\tv2 = array[i + 1];\n\n\t\tif (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/\n\t\t\tif (v1 & BIT(31)) {/* positive condition*/\n\t\t\t\tc_cond  =\n\t\t\t\t\t(u8)((v1 & (BIT(29) | BIT(28))) >> 28);\n\t\t\t\tif (c_cond == COND_ENDIF) {/*end*/\n\t\t\t\t\tis_matched = true;\n\t\t\t\t\tis_skipped = false;\n\t\t\t\t\tPHYDM_DBG(dm, ODM_COMP_INIT, \"ENDIF\\n\");\n\t\t\t\t} else if (c_cond == COND_ELSE) { /*else*/\n\t\t\t\t\tis_matched = is_skipped ? false : true;\n\t\t\t\t\tPHYDM_DBG(dm, ODM_COMP_INIT, \"ELSE\\n\");\n\t\t\t\t} else {/*if , else if*/\n\t\t\t\t\tpre_v1 = v1;\n\t\t\t\t\tpre_v2 = v2;\n\t\t\t\t\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t\t\t\t\t  \"IF or ELSE IF\\n\");\n\t\t\t\t}\n\t\t\t} else if (v1 & BIT(30)) { /*negative condition*/\n\t\t\t\tif (!is_skipped) {\n\t\t\t\t\ta1 = pre_v1; a2 = pre_v2;\n\t\t\t\t\ta3 = v1; a4 = v2;\n\t\t\t\t\tif (check_positive(dm,\n\t\t\t\t\t\t\t   a1, a2, a3, a4)) {\n\t\t\t\t\t\tis_matched = true;\n\t\t\t\t\t\tis_skipped = true;\n\t\t\t\t\t} else {\n\t\t\t\t\t\tis_matched = false;\n\t\t\t\t\t\tis_skipped = false;\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tis_matched = false;\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tif (is_matched)\n\t\t\t\todm_config_rf_radio_b_8822c(dm, v1, v2);\n\t\t}\n\t\ti = i + 2;\n\t}\n}\n\nu32\nodm_get_version_mp_8822c_radiob(void)\n{\n\t\treturn 41;\n}\n\n/******************************************************************************\n *                           txpowertrack.TXT\n ******************************************************************************/\n\n#ifdef CONFIG_8822C\nconst u8 delta_swingidx_mp_5gb_n_txpwrtrk_8822c[][D_S_SIZE] = {\n\t{0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18,\n\t 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32},\n\t{0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18,\n\t 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32},\n\t{0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18,\n\t 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32},\n};\n\nconst u8 delta_swingidx_mp_5gb_p_txpwrtrk_8822c[][D_S_SIZE] = {\n\t{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15,\n\t 16, 17, 18, 19, 20, 21, 22, 22, 23, 24, 25, 26, 27},\n\t{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15,\n\t 16, 17, 18, 19, 20, 21, 22, 22, 23, 24, 25, 26, 27},\n\t{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15,\n\t 16, 17, 18, 19, 20, 21, 22, 22, 23, 24, 25, 26, 27},\n};\n\nconst u8 delta_swingidx_mp_5ga_n_txpwrtrk_8822c[][D_S_SIZE] = {\n\t{0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18,\n\t 19, 20, 21, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33},\n\t{0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18,\n\t 19, 20, 21, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33},\n\t{0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18,\n\t 19, 20, 21, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33},\n};\n\nconst u8 delta_swingidx_mp_5ga_p_txpwrtrk_8822c[][D_S_SIZE] = {\n\t{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,\n\t 17, 18, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30},\n\t{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,\n\t 17, 18, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30},\n\t{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,\n\t 17, 18, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30},\n};\n\nconst u8 delta_swingidx_mp_2gb_n_txpwrtrk_8822c[]    = {\n\t0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14,\n\t 15, 15, 16, 17, 18, 19, 20, 20, 21, 22, 23, 24, 25};\nconst u8 delta_swingidx_mp_2gb_p_txpwrtrk_8822c[]    = {\n\t0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 14, 15,\n\t 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28};\nconst u8 delta_swingidx_mp_2ga_n_txpwrtrk_8822c[]    = {\n\t0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11,\n\t 11, 12, 13, 13, 14, 15, 15, 16, 17, 17, 18, 19, 19};\nconst u8 delta_swingidx_mp_2ga_p_txpwrtrk_8822c[]    = {\n\t0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15,\n\t 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27};\nconst u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_8822c[] = {\n\t0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14,\n\t 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 23, 24, 25};\nconst u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_8822c[] = {\n\t0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,\n\t 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29};\nconst u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_8822c[] = {\n\t0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12,\n\t 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 22};\nconst u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_8822c[] = {\n\t0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14,\n\t 15, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 24, 25};\n#endif\n\nvoid\nodm_read_and_config_mp_8822c_txpowertrack(struct dm_struct *dm)\n{\n#ifdef CONFIG_8822C\n\nstruct dm_rf_calibration_struct  *cali_info = &dm->rf_calibrate_info;\n\nPHYDM_DBG(dm, ODM_COMP_INIT, \"===> ODM_ReadAndConfig_MP_mp_8822c\\n\");\n\nodm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,\n\t\t(void *)delta_swingidx_mp_2ga_p_txpwrtrk_8822c,\n\t\tDELTA_SWINGIDX_SIZE);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,\n\t\t(void *)delta_swingidx_mp_2ga_n_txpwrtrk_8822c,\n\t\tDELTA_SWINGIDX_SIZE);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,\n\t\t(void *)delta_swingidx_mp_2gb_p_txpwrtrk_8822c,\n\t\tDELTA_SWINGIDX_SIZE);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,\n\t\t(void *)delta_swingidx_mp_2gb_n_txpwrtrk_8822c,\n\t\tDELTA_SWINGIDX_SIZE);\n\nodm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,\n\t\t(void *)delta_swingidx_mp_2g_cck_a_p_txpwrtrk_8822c,\n\t\tDELTA_SWINGIDX_SIZE);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,\n\t\t(void *)delta_swingidx_mp_2g_cck_a_n_txpwrtrk_8822c,\n\t\tDELTA_SWINGIDX_SIZE);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,\n\t\t(void *)delta_swingidx_mp_2g_cck_b_p_txpwrtrk_8822c,\n\t\tDELTA_SWINGIDX_SIZE);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,\n\t\t(void *)delta_swingidx_mp_2g_cck_b_n_txpwrtrk_8822c,\n\t\tDELTA_SWINGIDX_SIZE);\n\nodm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,\n\t\t(void *)delta_swingidx_mp_5ga_p_txpwrtrk_8822c,\n\t\tDELTA_SWINGIDX_SIZE * 3);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,\n\t\t(void *)delta_swingidx_mp_5ga_n_txpwrtrk_8822c,\n\t\tDELTA_SWINGIDX_SIZE * 3);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,\n\t\t(void *)delta_swingidx_mp_5gb_p_txpwrtrk_8822c,\n\t\tDELTA_SWINGIDX_SIZE * 3);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,\n\t\t(void *)delta_swingidx_mp_5gb_n_txpwrtrk_8822c,\n\t\tDELTA_SWINGIDX_SIZE * 3);\n#endif\n}\n\n/******************************************************************************\n *                           txpowertracktssi.TXT\n ******************************************************************************/\n\n#ifdef CONFIG_8822CTSSI\nconst u8 delta_swingidx_mp_5gb_n_txpwrtrktssi_8822c[][D_S_SIZE] = {\n\t{0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4,\n\t 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9},\n\t{0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4,\n\t 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9},\n\t{0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4,\n\t 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9},\n};\n\nconst u8 delta_swingidx_mp_5gb_p_txpwrtrktssi_8822c[][D_S_SIZE] = {\n\t{0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4,\n\t 5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 9},\n\t{0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4,\n\t 5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 9},\n\t{0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4,\n\t 5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 9},\n};\n\nconst u8 delta_swingidx_mp_5ga_n_txpwrtrktssi_8822c[][D_S_SIZE] = {\n\t{0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5,\n\t 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10},\n\t{0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5,\n\t 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10},\n\t{0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5,\n\t 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10},\n};\n\nconst u8 delta_swingidx_mp_5ga_p_txpwrtrktssi_8822c[][D_S_SIZE] = {\n\t{0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4,\n\t 5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 9},\n\t{0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4,\n\t 5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 9},\n\t{0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4,\n\t 5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 9},\n};\n\nconst u8 delta_swingidx_mp_2gb_n_txpwrtrktssi_8822c[]    = {\n\t0, 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6,\n\t 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12};\nconst u8 delta_swingidx_mp_2gb_p_txpwrtrktssi_8822c[]    = {\n\t0, 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6,\n\t 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11};\nconst u8 delta_swingidx_mp_2ga_n_txpwrtrktssi_8822c[]    = {\n\t0, 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6,\n\t 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12};\nconst u8 delta_swingidx_mp_2ga_p_txpwrtrktssi_8822c[]    = {\n\t0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7,\n\t 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13};\nconst u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrktssi_8822c[] = {\n\t0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5,\n\t 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10};\nconst u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrktssi_8822c[] = {\n\t0, 0, 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,\n\t 6, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11};\nconst u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrktssi_8822c[] = {\n\t0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7,\n\t 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13};\nconst u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrktssi_8822c[] = {\n\t0, 0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6,\n\t 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12};\n#endif\n\nvoid\nodm_read_and_config_mp_8822c_txpowertracktssi(struct dm_struct *dm)\n{\n#ifdef CONFIG_8822CTSSI\n\nstruct dm_rf_calibration_struct  *cali_info = &dm->rf_calibrate_info;\n\nPHYDM_DBG(dm, ODM_COMP_INIT, \"===> ODM_ReadAndConfig_MP_mp_8822c\\n\");\n\nodm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,\n\t\t(void *)delta_swingidx_mp_2ga_p_txpwrtrktssi_8822c,\n\t\tDELTA_SWINGIDX_SIZE);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,\n\t\t(void *)delta_swingidx_mp_2ga_n_txpwrtrktssi_8822c,\n\t\tDELTA_SWINGIDX_SIZE);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,\n\t\t(void *)delta_swingidx_mp_2gb_p_txpwrtrktssi_8822c,\n\t\tDELTA_SWINGIDX_SIZE);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,\n\t\t(void *)delta_swingidx_mp_2gb_n_txpwrtrktssi_8822c,\n\t\tDELTA_SWINGIDX_SIZE);\n\nodm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,\n\t\t(void *)delta_swingidx_mp_2g_cck_a_p_txpwrtrktssi_8822c,\n\t\tDELTA_SWINGIDX_SIZE);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,\n\t\t(void *)delta_swingidx_mp_2g_cck_a_n_txpwrtrktssi_8822c,\n\t\tDELTA_SWINGIDX_SIZE);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,\n\t\t(void *)delta_swingidx_mp_2g_cck_b_p_txpwrtrktssi_8822c,\n\t\tDELTA_SWINGIDX_SIZE);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,\n\t\t(void *)delta_swingidx_mp_2g_cck_b_n_txpwrtrktssi_8822c,\n\t\tDELTA_SWINGIDX_SIZE);\n\nodm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,\n\t\t(void *)delta_swingidx_mp_5ga_p_txpwrtrktssi_8822c,\n\t\tDELTA_SWINGIDX_SIZE * 3);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,\n\t\t(void *)delta_swingidx_mp_5ga_n_txpwrtrktssi_8822c,\n\t\tDELTA_SWINGIDX_SIZE * 3);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,\n\t\t(void *)delta_swingidx_mp_5gb_p_txpwrtrktssi_8822c,\n\t\tDELTA_SWINGIDX_SIZE * 3);\nodm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,\n\t\t(void *)delta_swingidx_mp_5gb_n_txpwrtrktssi_8822c,\n\t\tDELTA_SWINGIDX_SIZE * 3);\n#endif\n}\n\n/******************************************************************************\n *                           txpwr_lmt.TXT\n ******************************************************************************/\n\n#ifdef CONFIG_8822C\nconst char *array_mp_8822c_txpwr_lmt[] = {\n\t\"FCC\", \"2.4G\", \"20M\", \"CCK\", \"1T\", \"01\", \"72\",\n\t\"ETSI\", \"2.4G\", \"20M\", \"CCK\", \"1T\", \"01\", \"60\",\n\t\"MKK\", \"2.4G\", \"20M\", \"CCK\", \"1T\", \"01\", \"68\",\n\t\"IC\", \"2.4G\", \"20M\", \"CCK\", \"1T\", \"01\", \"72\",\n\t\"KCC\", \"2.4G\", \"20M\", \"CCK\", \"1T\", \"01\", \"76\",\n\t\"ACMA\", \"2.4G\", \"20M\", \"CCK\", \"1T\", \"01\", \"60\",\n\t\"CHILE\", \"2.4G\", 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\"52\",\n\t\"ETSI\", \"5G\", \"80M\", \"VHT\", \"2T\", \"58\", \"40\",\n\t\"MKK\", \"5G\", \"80M\", \"VHT\", \"2T\", \"58\", \"50\",\n\t\"IC\", \"5G\", \"80M\", \"VHT\", \"2T\", \"58\", \"40\",\n\t\"KCC\", \"5G\", \"80M\", \"VHT\", \"2T\", \"58\", \"56\",\n\t\"ACMA\", \"5G\", \"80M\", \"VHT\", \"2T\", \"58\", \"40\",\n\t\"CHILE\", \"5G\", \"80M\", \"VHT\", \"2T\", \"58\", \"52\",\n\t\"UKRAINE\", \"5G\", \"80M\", \"VHT\", \"2T\", \"58\", \"30\",\n\t\"MEXICO\", \"5G\", \"80M\", \"VHT\", \"2T\", \"58\", \"52\",\n\t\"FCC\", \"5G\", \"80M\", \"VHT\", \"2T\", \"106\", \"50\",\n\t\"ETSI\", \"5G\", \"80M\", \"VHT\", \"2T\", \"106\", \"40\",\n\t\"MKK\", \"5G\", \"80M\", \"VHT\", \"2T\", \"106\", \"72\",\n\t\"IC\", \"5G\", \"80M\", \"VHT\", \"2T\", \"106\", \"50\",\n\t\"KCC\", \"5G\", \"80M\", \"VHT\", \"2T\", \"106\", \"56\",\n\t\"ACMA\", \"5G\", \"80M\", \"VHT\", \"2T\", \"106\", \"40\",\n\t\"CHILE\", \"5G\", \"80M\", \"VHT\", \"2T\", \"106\", \"50\",\n\t\"UKRAINE\", \"5G\", \"80M\", \"VHT\", \"2T\", \"106\", \"30\",\n\t\"MEXICO\", \"5G\", \"80M\", \"VHT\", \"2T\", \"106\", \"50\",\n\t\"FCC\", \"5G\", \"80M\", \"VHT\", \"2T\", \"122\", \"66\",\n\t\"ETSI\", \"5G\", \"80M\", \"VHT\", \"2T\", \"122\", \"40\",\n\t\"MKK\", \"5G\", \"80M\", \"VHT\", \"2T\", \"122\", \"72\",\n\t\"IC\", \"5G\", \"80M\", \"VHT\", \"2T\", \"122\", \"127\",\n\t\"KCC\", \"5G\", \"80M\", \"VHT\", \"2T\", \"122\", \"56\",\n\t\"ACMA\", \"5G\", \"80M\", \"VHT\", \"2T\", \"122\", \"127\",\n\t\"CHILE\", \"5G\", \"80M\", \"VHT\", \"2T\", \"122\", \"66\",\n\t\"UKRAINE\", \"5G\", \"80M\", \"VHT\", \"2T\", \"122\", \"30\",\n\t\"MEXICO\", \"5G\", \"80M\", \"VHT\", \"2T\", \"122\", \"66\",\n\t\"FCC\", \"5G\", \"80M\", \"VHT\", \"2T\", \"138\", \"66\",\n\t\"ETSI\", \"5G\", \"80M\", \"VHT\", \"2T\", \"138\", \"127\",\n\t\"MKK\", \"5G\", \"80M\", \"VHT\", \"2T\", \"138\", \"127\",\n\t\"IC\", \"5G\", \"80M\", \"VHT\", \"2T\", \"138\", \"66\",\n\t\"KCC\", \"5G\", \"80M\", \"VHT\", \"2T\", \"138\", \"58\",\n\t\"ACMA\", \"5G\", \"80M\", \"VHT\", \"2T\", \"138\", \"127\",\n\t\"CHILE\", \"5G\", \"80M\", \"VHT\", \"2T\", \"138\", \"66\",\n\t\"UKRAINE\", \"5G\", \"80M\", \"VHT\", \"2T\", \"138\", \"127\",\n\t\"MEXICO\", \"5G\", \"80M\", \"VHT\", \"2T\", \"138\", \"66\",\n\t\"FCC\", \"5G\", \"80M\", \"VHT\", \"2T\", \"155\", \"62\",\n\t\"ETSI\", \"5G\", \"80M\", \"VHT\", \"2T\", \"155\", \"-128\",\n\t\"MKK\", \"5G\", \"80M\", \"VHT\", \"2T\", \"155\", \"127\",\n\t\"IC\", \"5G\", \"80M\", \"VHT\", \"2T\", \"155\", \"62\",\n\t\"KCC\", \"5G\", \"80M\", \"VHT\", \"2T\", \"155\", \"58\",\n\t\"ACMA\", \"5G\", \"80M\", \"VHT\", \"2T\", \"155\", \"72\",\n\t\"CHILE\", \"5G\", \"80M\", \"VHT\", \"2T\", \"155\", \"62\",\n\t\"UKRAINE\", \"5G\", \"80M\", \"VHT\", \"2T\", \"155\", \"30\",\n\t\"MEXICO\", \"5G\", \"80M\", \"VHT\", \"2T\", \"155\", \"62\"\n};\n#endif\n\nvoid\nodm_read_and_config_mp_8822c_txpwr_lmt(struct dm_struct *dm)\n{\n#ifdef CONFIG_8822C\n\n\tu32\ti = 0;\n#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)\n\tu32\tarray_len =\n\t\t\tsizeof(array_mp_8822c_txpwr_lmt) / sizeof(u8);\n\tu8\t*array = (u8 *)array_mp_8822c_txpwr_lmt;\n#else\n\tu32\tarray_len =\n\t\t\tsizeof(array_mp_8822c_txpwr_lmt) / sizeof(u8 *);\n\tu8\t**array = (u8 **)array_mp_8822c_txpwr_lmt;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid\t*adapter = dm->adapter;\n\tHAL_DATA_TYPE\t*hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\n\todm_memory_set(dm, hal_data->BufOfLinesPwrLmt, 0,\n\t\t       MAX_LINES_HWCONFIG_TXT *\n\t\t       MAX_BYTES_LINE_HWCONFIG_TXT);\n\thal_data->nLinesReadPwrLmt = array_len / 7;\n#endif\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"===> %s\\n\", __func__);\n\n\tfor (i = 0; i < array_len; i += 7) {\n#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)\n\t\tu8\tregulation = array[i];\n\t\tu8\tband = array[i + 1];\n\t\tu8\tbandwidth = array[i + 2];\n\t\tu8\trate = array[i + 3];\n\t\tu8\trf_path = array[i + 4];\n\t\tu8\tchnl = array[i + 5];\n\t\tu8\tval = array[i + 6];\n#else\n\t\tu8\t*regulation = array[i];\n\t\tu8\t*band = array[i + 1];\n\t\tu8\t*bandwidth = array[i + 2];\n\t\tu8\t*rate = array[i + 3];\n\t\tu8\t*rf_path = array[i + 4];\n\t\tu8\t*chnl = array[i + 5];\n\t\tu8\t*val = array[i + 6];\n#endif\n\n\t\todm_config_bb_txpwr_lmt_8822c(dm, regulation, band, bandwidth,\n\t\t\t\t\t      rate, rf_path, chnl, val);\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t\trsprintf((char *)hal_data->BufOfLinesPwrLmt[i / 7], 100, \"\\\"%s\\\", \\\"%s\\\", \\\"%s\\\", \\\"%s\\\", \\\"%s\\\", \\\"%s\\\", \\\"%s\\\",\",\n\t\t\t regulation, band, bandwidth, rate, rf_path, chnl, val);\n#endif\n\t}\n\n#endif\n}\n\n#endif /* end of HWIMG_SUPPORT*/\n\n"
  },
  {
    "path": "hal/phydm/halrf/rtl8822c/halhwimg8822c_rf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*Image2HeaderVersion: R3 1.5.8*/\n#if (RTL8822C_SUPPORT == 1)\n#ifndef __INC_MP_RF_HW_IMG_8822C_H\n#define __INC_MP_RF_HW_IMG_8822C_H\n\n/* Please add following compiler flags definition (#define CONFIG_XXX_DRV_DIS)\n * into driver source code to reduce code size if necessary.\n * #define CONFIG_8822C_DRV_DIS\n * #define CONFIG_8822CTSSI_DRV_DIS\n */\n\n#define CONFIG_8822C\n#ifdef CONFIG_8822C_DRV_DIS\n    #undef CONFIG_8822C\n#endif\n\n#define CONFIG_8822CTSSI\n#ifdef CONFIG_8822CTSSI_DRV_DIS\n    #undef CONFIG_8822CTSSI\n#endif\n\n/******************************************************************************\n *                           radioa.TXT\n ******************************************************************************/\n\n/* tc: Test Chip, mp: mp Chip*/\nvoid\nodm_read_and_config_mp_8822c_radioa(struct dm_struct *dm);\nu32 odm_get_version_mp_8822c_radioa(void);\n\n/******************************************************************************\n *                           radiob.TXT\n ******************************************************************************/\n\n/* tc: Test Chip, mp: mp Chip*/\nvoid\nodm_read_and_config_mp_8822c_radiob(struct dm_struct *dm);\nu32 odm_get_version_mp_8822c_radiob(void);\n\n/******************************************************************************\n *                           txpowertrack.TXT\n ******************************************************************************/\n\n/* tc: Test Chip, mp: mp Chip*/\nvoid\nodm_read_and_config_mp_8822c_txpowertrack(struct dm_struct *dm);\nu32 odm_get_version_mp_8822c_txpowertrack(void);\n\n/******************************************************************************\n *                           txpowertracktssi.TXT\n ******************************************************************************/\n\n/* tc: Test Chip, mp: mp Chip*/\nvoid\nodm_read_and_config_mp_8822c_txpowertracktssi(struct dm_struct *dm);\nu32 odm_get_version_mp_8822c_txpowertracktssi(void);\n\n/******************************************************************************\n *                           txpwr_lmt.TXT\n ******************************************************************************/\n\n/* tc: Test Chip, mp: mp Chip*/\nvoid\nodm_read_and_config_mp_8822c_txpwr_lmt(struct dm_struct *dm);\nu32 odm_get_version_mp_8822c_txpwr_lmt(void);\n\n#endif\n#endif /* end of HWIMG_SUPPORT*/\n\n"
  },
  {
    "path": "hal/phydm/halrf/rtl8822c/halrf_8822c.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#include \"mp_precomp.h\"\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#if RT_PLATFORM == PLATFORM_MACOSX\n#include \"phydm_precomp.h\"\n#else\n#include \"../phydm_precomp.h\"\n#endif\n#else\n#include \"../../phydm_precomp.h\"\n#endif\n\n#if (RTL8822C_SUPPORT == 1)\nvoid halrf_rf_lna_setting_8822c(struct dm_struct *dm_void,\n\t\t\t\tenum halrf_lna_set type)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 path = 0x0;\n\n\tfor (path = 0x0; path < 2; path++)\n\t\tif (type == HALRF_LNA_DISABLE) {\n\t\t\t/*S0*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19),\n\t\t\t\t       0x1);\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x33,\n\t\t\t\t       RFREGOFFSETMASK, 0x00003);\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e,\n\t\t\t\t       RFREGOFFSETMASK, 0x00064);\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f,\n\t\t\t\t       RFREGOFFSETMASK, 0x0afce);\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19),\n\t\t\t\t       0x0);\n\t\t} else if (type == HALRF_LNA_ENABLE) {\n\t\t\t/*S0*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19),\n\t\t\t\t       0x1);\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x33,\n\t\t\t\t       RFREGOFFSETMASK, 0x00003);\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e,\n\t\t\t\t       RFREGOFFSETMASK, 0x00064);\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f,\n\t\t\t\t       RFREGOFFSETMASK, 0x1afce);\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19),\n\t\t\t\t       0x0);\n\t\t}\n}\n\nvoid odm_tx_pwr_track_set_pwr8822c(void *dm_void, enum pwrtrack_method method,\n\t\t\t\t   u8 rf_path, u8 channel_mapped_index)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);\n\n\tu32 bitmask_6_0 = BIT(6) | BIT(5) | BIT(4) | BIT(3) |\n\t\t\t\tBIT(2) | BIT(1) | BIT(0);\n\t\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"pRF->absolute_ofdm_swing_idx=%d   pRF->remnant_ofdm_swing_idx=%d   pRF->absolute_cck_swing_idx=%d   pRF->remnant_cck_swing_idx=%d   rf_path=%d\\n\",\n\t       cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->remnant_ofdm_swing_idx[rf_path], cali_info->absolute_cck_swing_idx[rf_path], cali_info->remnant_cck_swing_idx, rf_path);\n\n\tif (method == BBSWING) { /*use for mp driver clean power tracking status*/\n\t\tswitch (rf_path) {\n\t\tcase RF_PATH_A:\n\t\t\todm_set_bb_reg(dm, R_0x18a0, bitmask_6_0, (cali_info->absolute_ofdm_swing_idx[rf_path] & 0x7f));\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"Path-%d 0x%x=0x%x\\n\", rf_path, R_0x18a0, odm_get_bb_reg(dm, R_0x18a0, bitmask_6_0));\n\t\t\tbreak;\n\t\tcase RF_PATH_B:\n\t\t\todm_set_bb_reg(dm, R_0x41a0, bitmask_6_0, (cali_info->absolute_ofdm_swing_idx[rf_path] & 0x7f));\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"Path-%d 0x%x=0x%x\\n\", rf_path, R_0x41a0, odm_get_bb_reg(dm, R_0x41a0, bitmask_6_0));\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t} else if (method == MIX_MODE) {\n\t\tswitch (rf_path) {\n\t\tcase RF_PATH_A:\n\t\t\todm_set_bb_reg(dm, R_0x18a0, bitmask_6_0, (cali_info->absolute_ofdm_swing_idx[rf_path] & 0x7f));\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"Path-%d 0x%x=0x%x\\n\", rf_path, R_0x18a0, odm_get_bb_reg(dm, R_0x18a0, bitmask_6_0));\n\t\t\tbreak;\n\t\tcase RF_PATH_B:\n\t\t\todm_set_bb_reg(dm, R_0x41a0, bitmask_6_0, (cali_info->absolute_ofdm_swing_idx[rf_path] & 0x7f));\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"Path-%d 0x%x=0x%x\\n\", rf_path, R_0x41a0, odm_get_bb_reg(dm, R_0x41a0, bitmask_6_0));\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\t\n\t}\n}\n\nvoid get_delta_swing_table_8822c(void *dm_void,\n\tu8 **temperature_up_a,\n\tu8 **temperature_down_a,\n\tu8 **temperature_up_b,\n\tu8 **temperature_down_b)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;\n\tu8 channel = *dm->channel;\n\tu8 tx_rate = phydm_get_tx_rate(dm);\n\n\tif (channel >= 1 && channel <= 14) {\n\t\tif (IS_CCK_RATE(tx_rate)) {\n\t\t\t*temperature_up_a = cali_info->delta_swing_table_idx_2g_cck_a_p;\n\t\t\t*temperature_down_a = cali_info->delta_swing_table_idx_2g_cck_a_n;\n\t\t\t*temperature_up_b = cali_info->delta_swing_table_idx_2g_cck_b_p;\n\t\t\t*temperature_down_b = cali_info->delta_swing_table_idx_2g_cck_b_n;\n\t\t} else {\n\t\t\t*temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;\n\t\t\t*temperature_down_a = cali_info->delta_swing_table_idx_2ga_n;\n\t\t\t*temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;\n\t\t\t*temperature_down_b = cali_info->delta_swing_table_idx_2gb_n;\n\t\t}\n\t}\n\n\tif (channel >= 36 && channel <= 64) {\n\t\t*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[0];\n\t\t*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[0];\n\t\t*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[0];\n\t\t*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[0];\n\t} else if (channel >= 100 && channel <= 144) {\n\t\t*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[1];\n\t\t*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[1];\n\t\t*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[1];\n\t\t*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[1];\n\t} else if (channel >= 149 && channel <= 177) {\n\t\t*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[2];\n\t\t*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[2];\n\t\t*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[2];\n\t\t*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[2];\n\t}\n}\n\nvoid _phy_aac_calibrate_8822c(struct dm_struct *dm)\n{\n#if 1\n\tu32 cnt = 0;\n\n\tRF_DBG(dm, DBG_RF_LCK, \"[AACK]AACK start!!!!!!!\\n\");\n\todm_set_rf_reg(dm, RF_PATH_A, 0xbb, RFREGOFFSETMASK, 0x80010);\n\todm_set_rf_reg(dm, RF_PATH_A, 0xb0, RFREGOFFSETMASK, 0x1F0FA);\n\tODM_delay_ms(1);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0xca, RFREGOFFSETMASK, 0x80000);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0xc9, RFREGOFFSETMASK, 0x80001);\n\tfor (cnt = 0; cnt < 100; cnt++) {\n\t\tODM_delay_ms(1);\n\t\tif (odm_get_rf_reg(dm, RF_PATH_A, RF_0xca, 0x1000) != 0x1)\n\t\t\tbreak;\n\t}\n\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0xb0, RFREGOFFSETMASK, 0x1F0F8);\n\todm_set_rf_reg(dm, RF_PATH_B, 0xbb, RFREGOFFSETMASK, 0x80010);\n\n\tRF_DBG(dm, DBG_RF_IQK, \"[AACK]AACK end!!!!!!!\\n\");\n#endif\n}\nvoid _phy_rt_calibrate_8822c(struct dm_struct *dm)\n{\n\tRF_DBG(dm, DBG_RF_IQK, \"[RTK]RTK start!!!!!!!\\n\");\n\todm_set_rf_reg(dm, RF_PATH_A, 0xcc, RFREGOFFSETMASK, 0x0f000);\n\todm_set_rf_reg(dm, RF_PATH_A, 0xcc, RFREGOFFSETMASK, 0x4f000);\n\tODM_delay_ms(1);\n\todm_set_rf_reg(dm, RF_PATH_A, 0xcc, RFREGOFFSETMASK, 0x0f000);\n\tRF_DBG(dm, DBG_RF_IQK, \"[RTK]RTK end!!!!!!!\\n\");\n}\n\nvoid halrf_reload_bp_8822c(struct dm_struct *dm, u32 *bp_reg, u32 *bp)\n{\n\tu32 i;\n\n\tfor (i = 0; i < DACK_REG_8822C; i++)\n\t\todm_write_4byte(dm, bp_reg[i], bp[i]);\n}\n\nvoid halrf_reload_bprf_8822c(struct dm_struct *dm, u32 *bp_reg, u32 bp[][2])\n{\n\tu32 i;\n\n\tfor (i = 0; i < DACK_RF_8822C; i++) {\n\t\todm_set_rf_reg(dm, RF_PATH_A, bp_reg[i], MASK20BITS,\n\t\t\t       bp[i][RF_PATH_A]);\n\t\todm_set_rf_reg(dm, RF_PATH_B, bp_reg[i], MASK20BITS,\n\t\t\t       bp[i][RF_PATH_B]);\n\t}\n}\n\nvoid halrf_bp_8822c(struct dm_struct *dm, u32 *bp_reg, u32 *bp)\n{\n\tu32 i;\n\n\tfor (i = 0; i < DACK_REG_8822C; i++)\n\t\tbp[i] = odm_read_4byte(dm, bp_reg[i]);\n}\n\nvoid halrf_bprf_8822c(struct dm_struct *dm, u32 *bp_reg, u32 bp[][2])\n{\n\tu32 i;\n\n\tfor (i = 0; i < DACK_RF_8822C; i++) {\n\t\tbp[i][RF_PATH_A] =\n\t\t\todm_get_rf_reg(dm, RF_PATH_A, bp_reg[i], MASK20BITS);\n\t\tbp[i][RF_PATH_B] =\n\t\t\todm_get_rf_reg(dm, RF_PATH_B, bp_reg[i], MASK20BITS);\n\t}\n}\n\nvoid halrf_swap_8822c(struct dm_struct *dm, u32 *v1, u32 *v2)\n{\n\tu32 temp;\n\n\ttemp = *v1;\n\t*v1 = *v2;\n\t*v2 = temp;\n}\n\nvoid halrf_bubble_8822c(struct dm_struct *dm, u32 *v1, u32 *v2)\n{\n\tu32 temp;\n\n\tif (*v1 >= 0x200 && *v2 >= 0x200) {\n\t\tif (*v1 > *v2)\n\t\t\thalrf_swap_8822c(dm, v1, v2);\n\t} else if (*v1 < 0x200 && *v2 < 0x200) {\n\t\tif (*v1 > *v2)\n\t\t\thalrf_swap_8822c(dm, v1, v2);\n\t} else if (*v1 < 0x200 && *v2 >= 0x200) {\n\t\thalrf_swap_8822c(dm, v1, v2);\n\t}\n}\n\nvoid halrf_b_sort_8822c(struct dm_struct *dm, u32 *iv, u32 *qv)\n{\n\tu32 temp;\n\tu32 i, j;\n\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]bubble!!!!!!!!!!!!\");\n\tfor (i = 0; i < SN - 1; i++) {\n\t\tfor (j = 0; j < (SN - 1 - i) ; j++) {\n\t\t\thalrf_bubble_8822c(dm, &iv[j], &iv[j + 1]);\n\t\t\thalrf_bubble_8822c(dm, &qv[j], &qv[j + 1]);\n\t\t}\n\t}\n}\n\nvoid halrf_minmax_compare_8822c(struct dm_struct *dm, u32 value, u32 *min,\n\t\t\t\tu32 *max)\n{\n\tif (value >= 0x200) {\n\t\tif (*min >= 0x200) {\n\t\t\tif (*min > value)\n\t\t\t\t*min = value;\n\t\t} else {\n\t\t\t*min = value;\n\t\t}\n\t\tif (*max >= 0x200) {\n\t\t\tif (*max < value)\n\t\t\t\t*max = value;\n\t\t}\n\t} else {\n\t\tif (*min < 0x200) {\n\t\t\tif (*min > value)\n\t\t\t\t*min = value;\n\t\t}\n\n\t\tif (*max  >= 0x200) {\n\t\t\t*max = value;\n\t\t} else {\n\t\t\tif (*max < value)\n\t\t\t\t*max = value;\n\t\t}\n\t}\n}\n\nboolean halrf_compare_8822c(struct dm_struct *dm, u32 value)\n{\n\tboolean fail = false;\n\n\tif (value >= 0x200 && (0x400 - value) > 0x64)\n\t\tfail = true;\n\telse if (value < 0x200 && value > 0x64)\n\t\tfail = true;\n\n\tif (fail)\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]overflow!!!!!!!!!!!!!!!\");\n\treturn fail;\n}\n\nvoid halrf_mode_8822c(struct dm_struct *dm, u32 *i_value, u32 *q_value)\n{\n\tu32 iv[SN], qv[SN], im[SN], qm[SN], temp, temp1, temp2;\n\tu32 p, m, t;\n\tu32 i_max = 0, q_max = 0, i_min = 0x0, q_min = 0x0, c = 0x0;\n\tu32 i_delta, q_delta;\n\tu8 i, j, ii = 0, qi = 0;\n\tboolean fail = false;\n\n//\tODM_delay_ms(10);\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]pathA RF0x0 = 0x%x\",\n\t       odm_get_rf_reg(dm, 0x0, 0x0, 0xfffff));\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]pathB RF0x0 = 0x%x\",\n\t       odm_get_rf_reg(dm, 0x1, 0x0, 0xfffff));\n\n\tfor (i = 0; i < SN; i++) {\n\t\tim[i] = 0;\n\t\tqm[i] = 0;\n\t}\n\n\ti = 0;\n\tc = 0;\n\twhile (i < SN && c < 10000) {\n\t\tc++;\n\t\ttemp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);\n\t\tiv[i] = (temp & 0x3ff000) >> 12;\n\t\tqv[i] = temp & 0x3ff;\n\n\t\tfail = false;\n\t\tif (halrf_compare_8822c(dm, iv[i]))\n\t\t\tfail = true;\n\t\tif (halrf_compare_8822c(dm, qv[i]))\n\t\t\tfail = true;\n\t\tif (!fail)\n\t\t\ti++;\n\t}\n\n\tc = 0;\n\tdo {\n\t\ti_min = iv[0];\n\t\ti_max = iv[0];\n\t\tq_min = qv[0];\n\t\tq_max = qv[0];\n\t\tfor (i = 0; i < SN; i++) {\n\t\t\thalrf_minmax_compare_8822c(dm, iv[i], &i_min, &i_max);\n\t\t\thalrf_minmax_compare_8822c(dm, qv[i], &q_min, &q_max);\n\t\t}\n\n\t\tc++;\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]i_min=0x%x, i_max=0x%x\",\n\t\t       i_min, i_max);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]q_min=0x%x, q_max=0x%x\",\n\t\t       q_min, q_max);\n\n\t\tif (i_max < 0x200 && i_min < 0x200)\n\t\t\ti_delta = i_max - i_min;\n\t\telse if (i_max >= 0x200 && i_min >= 0x200)\n\t\t\ti_delta = i_max - i_min;\n\t\telse\n\t\t\ti_delta = i_max + (0x400 - i_min);\n\n\t\tif (q_max < 0x200 && q_min < 0x200)\n\t\t\tq_delta = q_max - q_min;\n\t\telse if (q_max >= 0x200 && q_min >= 0x200)\n\t\t\tq_delta = q_max - q_min;\n\t\telse\n\t\t\tq_delta = q_max + (0x400 - q_min);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]i_delta=0x%x, q_delta=0x%x\",\n\t\t       i_delta, q_delta);\n\t\thalrf_b_sort_8822c(dm, iv, qv);\n\t\tif (i_delta > 5 || q_delta > 5) {\n//\t\t\thalrf_b_sort_8822c(dm, iv, qv);\n\t\t\ttemp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);\n\t\t\tiv[0] = (temp & 0x3ff000) >> 12;\n\t\t\tqv[0] = temp & 0x3ff;\n\t\t\ttemp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);\n\t\t\tiv[SN - 1] = (temp & 0x3ff000) >> 12;\n\t\t\tqv[SN - 1] = temp & 0x3ff;\n\t\t} else {\n\t\t\tbreak;\n\t\t}\n\t} while (c < 100);\n#if 0\n\tfor (i = 0; i < SN; i++) {\n\t\tfor (j = 0; j < SN; j++) {\n\t\t\tif (i != j) {\n\t\t\t\tif (iv[i] == iv[j])\n\t\t\t\t\tim[i]++;\n\t\t\t\tif (qv[i] == qv[j])\n\t\t\t\t\tqm[i]++;\n\t\t\t}\n\t\t}\n\t}\n\n\tfor (i = 0; i < SN; i++)\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]iv[%d] = 0x%x\\n\", i, iv[i]);\n\n\tfor (i = 0; i < SN; i++)\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]qv[%d] = 0x%x\\n\", i, qv[i]);\n\n\tfor (i = 1; i < SN; i++) {\n\t\tif (im[ii] < im[i])\n\t\t\tii = i;\n\t\tif (qm[qi] < qm[i])\n\t\t\tqi = i;\n\t}\n\n\t*i_value = iv[ii];\n\t*q_value = qv[qi];\n#endif\n#if 1\n#if 0\n\tfor (i = 0; i < SN; i++)\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]iv[%d] = 0x%x\\n\", i, iv[i]);\n\n\tfor (i = 0; i < SN; i++)\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]qv[%d] = 0x%x\\n\", i, qv[i]);\n#endif\n\t/*i*/\n\tm = 0;\n\tp = 0;\n\tfor (i = 10; i < SN - 10; i++) {\n\t\tif (iv[i] > 0x200)\n\t\t\tm = (0x400 - iv[i]) + m;\n\t\telse\n\t\t\tp = iv[i] + p;\n\t}\n\n\tif (p > m) {\n\t\tt = p - m;\n\t\tt = t / (SN - 20);\n\t} else {\n\t\tt = m - p;\n\t\tt = t / (SN - 20);\n\t\tif (t != 0x0)\n\t\t\tt = 0x400 - t;\n\t}\n\t*i_value = t;\n\t/*q*/\n\tm = 0;\n\tp = 0;\n\tfor (i = 10; i < SN - 10; i++) {\n\t\tif (qv[i] > 0x200)\n\t\t\tm = (0x400 - qv[i]) + m;\n\t\telse\n\t\t\tp = qv[i] + p;\n\t}\n\tif (p > m) {\n\t\tt = p - m;\n\t\tt = t / (SN - 20);\n\t} else {\n\t\tt = m - p;\n\t\tt = t / (SN - 20);\n\t\tif (t != 0x0)\n\t\t\tt = 0x400 - t;\n\t}\n\t*q_value = t;\n#endif\n}\n\nvoid halrf_biask_backup_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dack_info *dack = &dm->dack_info;\n\n\tdack->biask_d[0][0]= (u8)odm_get_bb_reg(dm, 0x2810, 0x1ff8);\n\tdack->biask_d[0][1]= (u8)odm_get_bb_reg(dm, 0x283c, 0x1ff8);\n\tdack->biask_d[1][0]= (u8)odm_get_bb_reg(dm, 0x4510, 0x1ff8);\n\tdack->biask_d[1][1]= (u8)odm_get_bb_reg(dm, 0x453c, 0x1ff8);\n}\n\nvoid halrf_dck_backup_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dack_info *dack = &dm->dack_info;\n\n\tdack->dck_d[0][0][0] = (u8)odm_get_bb_reg(dm, 0x18bc, 0xf0000000);\n\tdack->dck_d[0][0][1] = (u8)odm_get_bb_reg(dm, 0x18c0, 0xf);\n\tdack->dck_d[0][1][0] = (u8)odm_get_bb_reg(dm, 0x18d8, 0xf0000000);\n\tdack->dck_d[0][1][1] = (u8)odm_get_bb_reg(dm, 0x18dc, 0xf);\n\n\tdack->dck_d[1][0][0] = (u8)odm_get_bb_reg(dm, 0x41bc, 0xf0000000);\n\tdack->dck_d[1][0][1] = (u8)odm_get_bb_reg(dm, 0x41c0, 0xf);\n\tdack->dck_d[1][1][0] = (u8)odm_get_bb_reg(dm, 0x41d8, 0xf0000000);\n\tdack->dck_d[1][1][1] = (u8)odm_get_bb_reg(dm, 0x41dc, 0xf);\n}\nvoid halrf_dack_backup_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dack_info *dack = &dm->dack_info;\n\n\tu8 i;\n\tu32 temp1, temp2, temp3;\n\n\ttemp1 = odm_get_bb_reg(dm, 0x1860, MASKDWORD);\n\ttemp2 = odm_get_bb_reg(dm, 0x4160, MASKDWORD);\n\ttemp3 = odm_get_bb_reg(dm, 0x9b4, MASKDWORD);\n\n\todm_set_bb_reg(dm, 0x9b4, MASKDWORD, 0xdb66db00);\n\n\todm_set_bb_reg(dm, 0x1830, BIT(30), 0x0);\n\todm_set_bb_reg(dm, 0x1860, 0xfc000000, 0x3c);\n\n\tfor (i = 0; i < 0xf; i++) {\n\t\todm_set_bb_reg(dm, 0x18b0, 0xf0000000, i);\n\t\tdack->msbk_d[0][0][i] = (u16)odm_get_bb_reg(dm, 0x2810,\n\t\t\t\t\t\t\t    0x7fc0000);\n\t}\n\n\tfor (i = 0; i < 0xf; i++) {\n\t\todm_set_bb_reg(dm, 0x18cc, 0xf0000000, i);\n\t\tdack->msbk_d[0][1][i] = (u16)odm_get_bb_reg(dm, 0x283c,\n\t\t\t\t\t\t\t    0x7fc0000);\n\t}\n\n\todm_set_bb_reg(dm, 0x4130, BIT(30), 0x0);\n\todm_set_bb_reg(dm, 0x4160, 0xfc000000, 0x3c);\n\n\tfor (i = 0; i < 0xf; i++) {\n\t\todm_set_bb_reg(dm, 0x41b0, 0xf0000000, i);\n\t\tdack->msbk_d[1][0][i] = (u16)odm_get_bb_reg(dm, 0x4510,\n\t\t\t\t\t\t\t    0x7fc0000);\n\t}\n\n\tfor (i = 0; i < 0xf; i++) {\n\t\todm_set_bb_reg(dm, 0x41cc, 0xf0000000, i);\n\t\tdack->msbk_d[1][1][i] = (u16)odm_get_bb_reg(dm, 0x453c,\n\t\t\t\t\t\t\t    0x7fc0000);\n\t}\n\thalrf_dck_backup_8822c(dm);\n\todm_set_bb_reg(dm, 0x1830, BIT(30), 0x1);\n\todm_set_bb_reg(dm, 0x4130, BIT(30), 0x1);\n\todm_set_bb_reg(dm, 0x1860, MASKDWORD, temp1);\n\todm_set_bb_reg(dm, 0x4160, MASKDWORD, temp2);\n\todm_set_bb_reg(dm, 0x9b4, MASKDWORD, temp3);\n\thalrf_biask_backup_8822c(dm);\n}\n\nvoid halrf_biask_restore_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dack_info *dack = &dm->dack_info;\n\n\todm_set_bb_reg(dm, 0x18b0, 0x1ff8000, dack->biask_d[0][0]);\n\todm_set_bb_reg(dm, 0x18cc, 0x1ff8000, dack->biask_d[0][1]);\n\todm_set_bb_reg(dm, 0x41b0, 0x1ff8000, dack->biask_d[1][0]);\n\todm_set_bb_reg(dm, 0x41cc, 0x1ff8000, dack->biask_d[1][1]);\n}\n\nvoid halrf_dck_restore_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dack_info *dack = &dm->dack_info;\n\n\todm_set_bb_reg(dm, 0x18bc, BIT(19), 0x1);\n\todm_set_bb_reg(dm, 0x18bc, 0xf0000000, dack->dck_d[0][0][0]);\n\todm_set_bb_reg(dm, 0x18c0, 0xf, dack->dck_d[0][0][1]);\n\todm_set_bb_reg(dm, 0x18d8, BIT(19), 0x1);\n\todm_set_bb_reg(dm, 0x18d8, 0xf0000000, dack->dck_d[0][1][0]);\n\todm_set_bb_reg(dm, 0x18dc, 0xf, dack->dck_d[0][1][1]);\n\n\todm_set_bb_reg(dm, 0x41bc, BIT(19), 0x1);\n\todm_set_bb_reg(dm, 0x41bc, 0xf0000000, dack->dck_d[1][0][0]);\n\todm_set_bb_reg(dm, 0x41c0, 0xf, dack->dck_d[1][0][1]);\n\todm_set_bb_reg(dm, 0x41d8, BIT(19), 0x1);\n\todm_set_bb_reg(dm, 0x41d8, 0xf0000000, dack->dck_d[1][1][0]);\n\todm_set_bb_reg(dm, 0x41dc, 0xf, dack->dck_d[1][1][1]);\n}\nvoid halrf_dack_restore_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dack_info *dack = &dm->dack_info;\n\tu8 i;\n\tu32 c = 0x0;\n\tu32 temp1, temp2, temp3;\n\n\tif (dack->dack_en == false)\n\t\treturn;\n\n\ttemp1 = odm_get_bb_reg(dm, 0x1860, MASKDWORD);\n\ttemp2 = odm_get_bb_reg(dm, 0x4160, MASKDWORD);\n\ttemp3 = odm_get_bb_reg(dm, 0x9b4, MASKDWORD);\n\n\todm_set_bb_reg(dm, 0x9b4, MASKDWORD, 0xdb66db00);\n\n\todm_set_bb_reg(dm, 0x18b0, BIT(27), 0x0);\n\todm_set_bb_reg(dm, 0x18cc, BIT(27), 0x0);\n\todm_set_bb_reg(dm, 0x41b0, BIT(27), 0x0);\n\todm_set_bb_reg(dm, 0x41cc, BIT(27), 0x0);\n\n\todm_set_bb_reg(dm, 0x1830, BIT(30), 0x0);\n\todm_set_bb_reg(dm, 0x1860, 0xfc000000, 0x3c);\n\todm_set_bb_reg(dm, 0x18b4, BIT(0), 0x1);\n\todm_set_bb_reg(dm, 0x18d0, BIT(0), 0x1);\n\n\todm_set_bb_reg(dm, 0x4130, BIT(30), 0x0);\n\todm_set_bb_reg(dm, 0x4160, 0xfc000000, 0x3c);\n\todm_set_bb_reg(dm, 0x41b4, BIT(0), 0x1);\n\todm_set_bb_reg(dm, 0x41d0, BIT(0), 0x1);\n\n\todm_set_bb_reg(dm, 0x18b0, 0xf00, 0x0);\n\todm_set_bb_reg(dm, 0x18c0, BIT(14), 0x0);\n\todm_set_bb_reg(dm, 0x18cc, 0xf00, 0x0);\n\todm_set_bb_reg(dm, 0x18dc, BIT(14), 0x0);\n\n\todm_set_bb_reg(dm, 0x18b0, BIT(0), 0x0);\n\todm_set_bb_reg(dm, 0x18cc, BIT(0), 0x0);\n\todm_set_bb_reg(dm, 0x18b0, BIT(0), 0x1);\n\todm_set_bb_reg(dm, 0x18cc, BIT(0), 0x1);\n\n\thalrf_dck_restore_8822c(dm);\n\n\todm_set_bb_reg(dm, 0x18c0, 0x38000, 0x7);\n\todm_set_bb_reg(dm, 0x18dc, 0x38000, 0x7);\n\todm_set_bb_reg(dm, 0x41c0, 0x38000, 0x7);\n\todm_set_bb_reg(dm, 0x41dc, 0x38000, 0x7);\n\n\todm_set_bb_reg(dm, 0x18b8, BIT(26) | BIT(25), 0x1);\n\todm_set_bb_reg(dm, 0x18d4, BIT(26) | BIT(25), 0x1);\n\n\todm_set_bb_reg(dm, 0x41b0, 0xf00, 0x0);\n\todm_set_bb_reg(dm, 0x41c0, BIT(14), 0x0);\n\todm_set_bb_reg(dm, 0x41cc, 0xf00, 0x0);\n\todm_set_bb_reg(dm, 0x41dc, BIT(14), 0x0);\n\n\todm_set_bb_reg(dm, 0x41b0, BIT(0), 0x0);\n\todm_set_bb_reg(dm, 0x41cc, BIT(0), 0x0);\n\todm_set_bb_reg(dm, 0x41b0, BIT(0), 0x1);\n\todm_set_bb_reg(dm, 0x41cc, BIT(0), 0x1);\n\n \todm_set_bb_reg(dm, 0x41b8, BIT(26) | BIT(25), 0x1);\n\todm_set_bb_reg(dm, 0x41d4, BIT(26) | BIT(25), 0x1);\n#if 1\n\tc = 0x0;\n\twhile (c < 10000) {\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x2808=0x%x\",\n\t\t      odm_get_bb_reg(dm, 0x2808, 0x7fff80));\t\n\t\tc++;\n\t\tif (odm_get_bb_reg(dm, 0x2808, 0x7fff80) == 0xffff)\n\t\t\tbreak;\n\t}\n\tc = 0x0;\n\twhile (c < 10000) {\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x2834=0x%x\",\n\t\t      odm_get_bb_reg(dm, 0x2834, 0x7fff80));\t\n\t\tc++;\n\t\tif (odm_get_bb_reg(dm, 0x2834, 0x7fff80) == 0xffff)\n\t\t\tbreak;\n\t}\n\tc = 0x0;\n\twhile (c < 10000) {\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x4508=0x%x\",\n\t\t      odm_get_bb_reg(dm, 0x4508, 0x7fff80));\t\n\t\tc++;\n\t\tif (odm_get_bb_reg(dm, 0x4508, 0x7fff80) == 0xffff)\n\t\t\tbreak;\n\t}\n\tc = 0x0;\n\twhile (c < 10000) {\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x4534=0x%x\",\n\t\t      odm_get_bb_reg(dm, 0x4534, 0x7fff80));\t\n\t\tc++;\n\t\tif (odm_get_bb_reg(dm, 0x4534, 0x7fff80) == 0xffff)\n\t\t\tbreak;\n\t}\n#endif\n\todm_set_bb_reg(dm, 0x18b8, BIT(26) | BIT(25), 0x0);\n\todm_set_bb_reg(dm, 0x18b8, BIT(26) | BIT(25), 0x2);\n\tc = 0x0;\n\twhile (c < 10000) {\n\t\tc++;\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x2808=0x%x\",\n\t\t      odm_get_bb_reg(dm, 0x2808, 0xff));\t\t\n\t\tif (odm_get_bb_reg(dm, 0x2808, 0xf) == 0x6)\n\t\t\tbreak;\n\t\todm_set_bb_reg(dm, 0x18b8, BIT(26) | BIT(25), 0x0);\n\t\todm_set_bb_reg(dm, 0x18b8, BIT(26) | BIT(25), 0x2);\n\t}\n\tfor (i = 0; i < 0xf; i++) {\n\t\todm_set_bb_reg(dm, 0x18b4, BIT(2), 0x0);\n\t\todm_set_bb_reg(dm, 0x18b4, 0xff8, dack->msbk_d[0][0][i]);\n\t\todm_set_bb_reg(dm, 0x18b0, 0xf0000000, i);\n\t\todm_set_bb_reg(dm, 0x18b4, BIT(2), 0x1);\n\t}\n\todm_set_bb_reg(dm, 0x18b4, BIT(2), 0x0);\n\todm_set_bb_reg(dm, 0x18d4, BIT(26) | BIT(25), 0x0);\n\todm_set_bb_reg(dm, 0x18d4, BIT(26) | BIT(25), 0x2);\n\tc = 0x0;\n\twhile (c < 10000) {\n\t\tc++;\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x2834=0x%x\",\n\t\t      odm_get_bb_reg(dm, 0x2834, 0xff));\n\t\tif (odm_get_bb_reg(dm,0x2834,0xf) == 0x6)\n\t\t\tbreak;\n\t\todm_set_bb_reg(dm, 0x18d4, BIT(26) | BIT(25), 0x0);\n\t\todm_set_bb_reg(dm, 0x18d4, BIT(26) | BIT(25), 0x2);\n\t}\n\n\tfor (i = 0; i < 0xf; i++) {\n\t\todm_set_bb_reg(dm, 0x18d0, BIT(2), 0x0);\n\t\todm_set_bb_reg(dm, 0x18d0, 0xff8, dack->msbk_d[0][1][i]);\n\t\todm_set_bb_reg(dm, 0x18cc, 0xf0000000, i);\n\t\todm_set_bb_reg(dm, 0x18d0, BIT(2), 0x1);\n\t}\n\todm_set_bb_reg(dm, 0x18d0, BIT(2), 0x0);\n\todm_set_bb_reg(dm, 0x18b8, BIT(26) | BIT(25), 0x0);\n\todm_set_bb_reg(dm, 0x18d4, BIT(26) | BIT(25), 0x0);\n\todm_set_bb_reg(dm, 0x18b4, BIT(0), 0x0);\n\todm_set_bb_reg(dm, 0x18d0, BIT(0), 0x0);\n\todm_set_bb_reg(dm, 0x41b8, BIT(26) | BIT(25), 0x0);\n\todm_set_bb_reg(dm, 0x41b8, BIT(26) | BIT(25), 0x2);\n\tc = 0x0;\n\twhile (c < 10000) {\n\t\tc++;\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x4508=0x%x\",\n\t\t      odm_get_bb_reg(dm, 0x4508, 0xff));\n\t\tif (odm_get_bb_reg(dm,0x4508,0xf) == 0x6)\n\t\t\tbreak;\n\t\todm_set_bb_reg(dm, 0x41b8, BIT(26) | BIT(25), 0x0);\n\t\todm_set_bb_reg(dm, 0x41b8, BIT(26) | BIT(25), 0x2);\n\t}\n\tfor (i = 0; i < 0xf; i++) {\n\t\todm_set_bb_reg(dm, 0x41b4, BIT(2), 0x0);\n\t\todm_set_bb_reg(dm, 0x41b4, 0xff8, dack->msbk_d[1][0][i]);\n\t\todm_set_bb_reg(dm, 0x41b0, 0xf0000000, i);\n\t\todm_set_bb_reg(dm, 0x41b4, BIT(2), 0x1);\n\t}\n\todm_set_bb_reg(dm, 0x41b4, BIT(2), 0x0);\n\todm_set_bb_reg(dm, 0x41d4, BIT(26) | BIT(25), 0x0);\n\todm_set_bb_reg(dm, 0x41d4, BIT(26) | BIT(25), 0x2);\n\tc = 0x0;\n\twhile (c < 10000) {\n\t\tc++;\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x4534=0x%x\",\n\t\t      odm_get_bb_reg(dm, 0x4534, 0xff));\n\t\tif (odm_get_bb_reg(dm,0x4534,0xf) == 0x6)\n\t\t\tbreak;\n\t\todm_set_bb_reg(dm, 0x41d4, BIT(26) | BIT(25), 0x0);\n\t\todm_set_bb_reg(dm, 0x41d4, BIT(26) | BIT(25), 0x2);\n\t}\n\tfor (i = 0x0; i < 0xf; i++) {\n\t\todm_set_bb_reg(dm, 0x41d0, BIT(2), 0x0);\n\t\todm_set_bb_reg(dm, 0x41d0, 0xff8, dack->msbk_d[1][1][i]);\n\t\todm_set_bb_reg(dm, 0x41cc, 0xf0000000, i);\n\t\todm_set_bb_reg(dm, 0x41d0, BIT(2), 0x1);\n\t}\n\todm_set_bb_reg(dm, 0x41d0, BIT(2), 0x0);\n \todm_set_bb_reg(dm, 0x41b8, BIT(26) | BIT(25), 0x0);\n \todm_set_bb_reg(dm, 0x41d4, BIT(26) | BIT(25), 0x0);\n\todm_set_bb_reg(dm, 0x41b4, BIT(0), 0x0);\n\todm_set_bb_reg(dm, 0x41d0, BIT(0), 0x0);\n\n\todm_set_bb_reg(dm, 0x1830, BIT(30), 0x1);\n\todm_set_bb_reg(dm, 0x4130, BIT(30), 0x1);\n\todm_set_bb_reg(dm, 0x1860, MASKDWORD, temp1);\n\todm_set_bb_reg(dm, 0x4160, MASKDWORD, temp2);\n\todm_set_bb_reg(dm, 0x18b0, BIT(27), 0x1);\n\todm_set_bb_reg(dm, 0x18cc, BIT(27), 0x1);\n\todm_set_bb_reg(dm, 0x41b0, BIT(27), 0x1);\n\todm_set_bb_reg(dm, 0x41cc, BIT(27), 0x1);\n\todm_set_bb_reg(dm, 0x9b4, MASKDWORD, temp3);\n\n\thalrf_biask_restore_8822c(dm);\n}\n\nvoid halrf_polling_check(void *dm_void, u32 add, u32 bmask, u32 data)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 c = 0;\n\n\tc = 0;\n\twhile (c < 100000) {\n\t\tc++;\n\t\tif (odm_get_bb_reg(dm, add, bmask) == data)\n\t\t\tbreak;\n\t}\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]c=%d\\n\",c);\n}\n\nvoid halrf_dac_cal_8822c(void *dm_void, boolean force)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dack_info *dack = &dm->dack_info;\n\tstatic u32 count = 1;\n#if 1\n\tu32 ic = 0, qc = 0, temp = 0, temp1 = 0, i = 0;\n\tu32 bp[DACK_REG_8822C];\n\tu32 bp_reg[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110, 0x1c3c, 0x1c24,\n\t\t\t\t      0x1d70, 0x9b4, 0x1a00, 0x1a14, 0x1d58,\n\t\t\t\t      0x1c38, 0x1e24, 0x1e28, 0x1860, 0x4160};\n\tu32 bp_rf[DACK_RF_8822C][2];\n\tu32 bp_rfreg[DACK_RF_8822C] = {0x8f};\n\tu32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0;\n\tu32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0;\n\tu32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0;\n#if 1\n\tif (dack->dack_en) {\n\t\tif (!force) {\n\t\t\thalrf_dack_restore_8822c(dm);\n\t\t\treturn;\n\t\t}\n\t} else {\n\t\tdack->dack_en = true;\n\t}\n#endif\n\tcount++;\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]count = %d\", count);\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]DACK start!!!!!!!\");\n\thalrf_bp_8822c(dm, bp_reg, bp);\n\thalrf_bprf_8822c(dm, bp_rfreg, bp_rf);\n\t/*BB setting*/\n\todm_set_bb_reg(dm, 0x1d58, 0xff8, 0x1ff);\n\todm_set_bb_reg(dm, 0x1a00, 0x3, 0x2);\n\todm_set_bb_reg(dm, 0x1a14, 0x300, 0x3);\n\todm_write_4byte(dm, 0x1d70, 0x7e7e7e7e);\n\todm_set_bb_reg(dm, 0x180c, 0x3, 0x0);\n\todm_set_bb_reg(dm, 0x410c, 0x3, 0x0);\n\todm_write_4byte(dm, 0x1b00, 0x00000008);\n\todm_write_1byte(dm, 0x1bcc, 0x3f);\n\todm_write_4byte(dm, 0x1b00, 0x0000000a);\n\todm_write_1byte(dm, 0x1bcc, 0x3f);\n\todm_set_bb_reg(dm, 0x1e24, BIT(31), 0x0);\n\todm_set_bb_reg(dm, 0x1e28, 0xf, 0x3);\n/*path-A*/\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]pathA DACK!!!!!!!!!!!!!!!!!!!!!!!!!!!\");\n/*1.ADCK step1*/\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]step1 ADCK!!!!!!!!!!!!!!!!!!!!!!!!!!!\");\n\todm_set_bb_reg(dm, 0x1830, BIT(30), 0x0);\n\todm_write_4byte(dm, 0x1860, 0xf0040ff0);\n\todm_write_4byte(dm, 0x180c, 0xdff00220);\n\todm_write_4byte(dm, 0x1810, 0x02dd08c4);\n\todm_write_4byte(dm, 0x180c, 0x10000260);\n\todm_set_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x10000);\n\todm_set_rf_reg(dm, RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x10000);\n\n\ti = 0;\n\twhile (i < 10) {\n\t\ti++;\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]ADCK count=%d\", i);\n\t\todm_write_4byte(dm, 0x1c3c, 0x00088003);\n\t\todm_write_4byte(dm, 0x1c24, 0x00010002);\n\t\thalrf_mode_8822c(dm, &ic, &qc);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]before ADCK i=0x%x, q=0x%x\",\n\t\t       ic, qc);\n\t\t/*compensation value*/\n\t\tif (ic != 0x0) {\n\t\t\tic = 0x400 - ic;\n\t\t\tadc_ic_a = ic;\n\t\t}\n\t\tif (qc != 0x0) {\n\t\t\tqc = 0x400 - qc;\n\t\t\tadc_qc_a = qc;\n\t\t}\n\t\ttemp = (ic & 0x3ff) | ((qc & 0x3ff) << 10);\n\t\todm_write_4byte(dm, 0x1868, temp);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]ADCK 0x1868 =0x%x\\n\", temp);\n#if 1\n\t\t/*check ADC DC offset*/\n\t\todm_write_4byte(dm, 0x1c3c, 0x00088103);\n\t\thalrf_mode_8822c(dm, &ic, &qc);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]after ADCK i=0x%x, q=0x%x\",\n\t\t       ic, qc);\n#endif\n\t\tif (ic >= 0x200)\n\t\t\tic = 0x400 - ic;\n\t\tif (qc >= 0x200)\n\t\t\tqc = 0x400 - qc;\n\t\tif (ic < 5 && qc < 5)\n\t\t\tbreak;\n\t}\n\t/*2.ADCK step2*/\n\todm_write_4byte(dm, 0x1c3c, 0x00000003);\n\todm_write_4byte(dm, 0x180c, 0x10000260);\n\todm_write_4byte(dm, 0x1810, 0x02d508c4);\n\t/*3.release pull low switch on IQ path*/\n\todm_set_rf_reg(dm, RF_PATH_A, 0x8f, BIT(13), 0x1);\n\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]step2 DACK!!!!!!!!!!!!!!!!!!!!!!!!!!!\");\n\ti = 0;\n\twhile (i < 10) {\n\t\todm_write_4byte(dm, 0x1868, temp);\n\t\t/*DACK step1*/\n\t\ti++;\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]DACK count=%d\\n\", i);\n\t\todm_write_4byte(dm, 0x180c, 0xdff00220);\n\t\todm_write_4byte(dm, 0x1860, 0xf0040ff0);\n\t\todm_write_4byte(dm, 0x1c38, 0xffffffff);\n\t\todm_write_4byte(dm, 0x1810, 0x02d508c5);\n\t\todm_write_4byte(dm, 0x9b4, 0xdb66db00);\n\t\todm_write_4byte(dm, 0x18b0, 0x0a11fb88);\n\t\todm_write_4byte(dm, 0x18bc, 0x0008ff81);\n\t\todm_write_4byte(dm, 0x18c0, 0x0003d208);\n\t\todm_write_4byte(dm, 0x18cc, 0x0a11fb88);\n\t\todm_write_4byte(dm, 0x18d8, 0x0008ff81);\n\t\todm_write_4byte(dm, 0x18dc, 0x0003d208);\n\n\t\todm_write_4byte(dm, 0x18b8, 0x60000000);\n\t\tODM_delay_ms(2);\n\t\todm_write_4byte(dm, 0x18bc, 0x000aff8d);\n\t\tODM_delay_ms(2);\n\t\todm_write_4byte(dm, 0x18b0, 0x0a11fb89);\n\t\todm_write_4byte(dm, 0x18cc, 0x0a11fb89);\n\t\tODM_delay_ms(1);\n\t\todm_write_4byte(dm, 0x18b8, 0x62000000);\n//\t\tODM_delay_ms(20);\n\t\todm_write_4byte(dm, 0x18d4, 0x62000000);\n\t\tODM_delay_ms(1);\n\t\thalrf_polling_check(dm, 0x2808, 0x7fff80, 0xffff);\n\t\thalrf_polling_check(dm, 0x2834, 0x7fff80, 0xffff);\n\t\todm_write_4byte(dm, 0x18b8, 0x02000000);\n\t\tODM_delay_ms(1);\n\t\todm_write_4byte(dm, 0x18bc, 0x0008ff87);\n\t\todm_write_4byte(dm, 0x9b4, 0xdb6db600);\n\n\t\todm_write_4byte(dm, 0x1810, 0x02d508c5);\n\t\todm_write_4byte(dm, 0x18bc, 0x0008ff87);\n\t\todm_write_4byte(dm, 0x1860, 0xf0000000);\n\t\t/*4.DACK step2*/\n\t\todm_set_bb_reg(dm, 0x18bc, 0xf0000000, 0x0);\n\t\todm_set_bb_reg(dm, 0x18c0, 0xf, 0x8);\n\t\todm_set_bb_reg(dm, 0x18d8, 0xf0000000, 0x0);\n\t\todm_set_bb_reg(dm, 0x18dc, 0xf, 0x8);\n\n\t\todm_write_4byte(dm, 0x1b00, 0x00000008);\n\t\todm_write_1byte(dm, 0x1bcc, 0x03f);\n\t\todm_write_4byte(dm, 0x180c, 0xdff00220);\n\t\todm_write_4byte(dm, 0x1810, 0x02d508c5);\n\t\todm_write_4byte(dm, 0x1c3c, 0x00088103);\n\t\thalrf_mode_8822c(dm, &ic, &qc);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]before DACK i =0x%x, q = 0x%x\",\n\t\t       ic, qc);\n\t\t/*compensation value*/\n\t\tif (ic != 0x0)\n\t\t\tic = 0x400 - ic;\n\t\tif (qc != 0x0)\n\t\t\tqc = 0x400 - qc;\n\t\tif (ic < 0x300) {\n\t\t\tic = ic * 2 * 6 / 5;\n\t\t\tic = ic + 0x80;\n\t\t} else {\n\t\t\tic = (0x400 - ic) * 2 * 6 / 5;\n\t\t\tic = 0x7f - ic;\n\t\t}\n\t\tif (qc < 0x300) {\n\t\t\tqc = qc * 2 * 6 / 5;\n\t\t\tqc = qc + 0x80;\n\t\t} else {\n\t\t\tqc = (0x400 - qc) * 2 * 6 / 5;\n\t\t\tqc = 0x7f - qc;\n\t\t}\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]DACK ic =0x%x, qc = 0x%x\\n\",\n\t\t       ic, qc);\n\t\tic_a = ic;\n\t\tqc_a = qc;\n\t/*5.DACK step3*/\n\t\todm_write_4byte(dm, 0x180c, 0xdff00220);\n\t\todm_write_4byte(dm, 0x1810, 0x02d508c5);\n\t\todm_write_4byte(dm, 0x9b4, 0xdb66db00);\n\t\todm_write_4byte(dm, 0x18b0, 0x0a11fb88);\n\t\todm_write_4byte(dm, 0x18bc, 0xc008ff81);\n\t\todm_write_4byte(dm, 0x18c0, 0x0003d208);\n\t\todm_set_bb_reg(dm, 0x18bc, 0xf0000000, ic & 0xf);\n\t\todm_set_bb_reg(dm, 0x18c0, 0xf, (ic & 0xf0) >> 4);\n\t\todm_write_4byte(dm, 0x18cc, 0x0a11fb88);\n\t\todm_write_4byte(dm, 0x18d8, 0xe008ff81);\n\t\todm_write_4byte(dm, 0x18dc, 0x0003d208);\n\t\todm_set_bb_reg(dm, 0x18d8, 0xf0000000, qc & 0xf);\n\t\todm_set_bb_reg(dm, 0x18dc, 0xf, (qc & 0xf0) >> 4);\n\t\todm_write_4byte(dm, 0x18b8, 0x60000000);\n\t\tODM_delay_ms(2);\n\t\todm_set_bb_reg(dm, 0x18bc, 0xe, 0x6);\n\t\tODM_delay_ms(2);\n\t\todm_write_4byte(dm, 0x18b0, 0x0a11fb89);\n\t\todm_write_4byte(dm, 0x18cc, 0x0a11fb89);\n\t\tODM_delay_ms(1);\n\t\todm_write_4byte(dm, 0x18b8, 0x62000000);\n\t\todm_write_4byte(dm, 0x18d4, 0x62000000);\n\t\tODM_delay_ms(1);\n\t\thalrf_polling_check(dm, 0x2824, 0x07f80000, ic);\n\t\thalrf_polling_check(dm, 0x2850, 0x07f80000, qc);\n\t\todm_write_4byte(dm, 0x18b8, 0x02000000);\n\t\tODM_delay_ms(1);\n\t\todm_set_bb_reg(dm, 0x18bc, 0xe, 0x3);\n\t\todm_write_4byte(dm, 0x9b4, 0xdb6db600);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x18bc =0x%x\",\n\t\t       odm_read_4byte(dm, 0x18bc));\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x18c0 =0x%x\",\n\t\t       odm_read_4byte(dm, 0x18c0));\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x18d8 =0x%x\",\n\t\t       odm_read_4byte(dm, 0x18d8));\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x18dc =0x%x\",\n\t\t       odm_read_4byte(dm, 0x18dc));\n#if 1\n\t\t/*check DAC DC offset*/\n\t\ttemp1 = ((adc_ic_a + 0x10) & 0x3ff) |\n\t\t       (((adc_qc_a + 0x10) & 0x3ff) << 10);\n\t\todm_write_4byte(dm, 0x1868, temp1);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]shift 0x1868 =0x%x\",\n\t\t       odm_read_4byte(dm, 0x1868));\n\t\todm_write_4byte(dm, 0x1810, 0x02d508c5);\n\t\todm_write_4byte(dm, 0x1860, 0xf0000000);\n\t\thalrf_mode_8822c(dm, &ic, &qc);\n\t\tif (ic >= 0x10)\n\t\t\tic = ic - 0x10;\n\t\telse\n\t\t\tic = 0x400 - (0x10 - ic);\n\n\t\tif (qc >= 0x10)\n\t\t\tqc = qc - 0x10;\n\t\telse\n\t\t\tqc = 0x400 - (0x10 - qc);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]after DACK i=0x%x, q=0x%x\",\n\t\t       ic, qc);\n\t\ti_a = ic;\n\t\tq_a = qc;\n\t\tif (ic >= 0x200)\n\t\t\tic = 0x400 - ic;\n\t\tif (qc >= 0x200)\n\t\t\tqc = 0x400 - qc;\n\t\tif (ic < 5 && qc < 5)\n\t\t\tbreak;\n#endif\n\t}\n\todm_write_4byte(dm, 0x1868, 0x0);\n\todm_write_4byte(dm, 0x1810, 0x02d508c4);\n\todm_set_bb_reg(dm, 0x18bc, 0x1, 0x0);\n\todm_set_bb_reg(dm, 0x1830, BIT(30), 0x1);\n#if 1\n/*path-B*/\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]pathB DACK!!!!!!!!!!!!!!!!!!!!!!!!!!!\");\n/*1.ADCK step1*/\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]step1 ADCK!!!!!!!!!!!!!!!!!!!!!!!!!!!\");\n\todm_set_bb_reg(dm, 0x4130, BIT(30), 0x0);\n\todm_write_4byte(dm, 0x4130, 0x30db8041);\n\todm_write_4byte(dm, 0x4160, 0xf0040ff0);\n\todm_write_4byte(dm, 0x410c, 0xdff00220);\n\todm_write_4byte(dm, 0x4110, 0x02dd08c4);\n\todm_write_4byte(dm, 0x410c, 0x10000260);\n\todm_set_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x10000);\n\todm_set_rf_reg(dm, RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x10000);\n\ti = 0;\n\twhile (i < 10) {\n\t\ti++;\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]ADCK count=%d\\n\", i);\n\t\todm_write_4byte(dm, 0x1c3c, 0x000a8003);\n\t\todm_write_4byte(dm, 0x1c24, 0x00010002);\n\t\thalrf_mode_8822c(dm, &ic, &qc);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]before ADCK i=0x%x, q=0x%x\",\n\t\t       ic, qc);\n\t\t/*compensation value*/\n\t\tif (ic != 0x0) {\n\t\t\tic = 0x400 - ic;\n\t\t\tadc_ic_b = ic;\n\t\t}\n\t\tif (qc != 0x0) {\n\t\t\tqc = 0x400 - qc;\n\t\t\tadc_qc_b = qc;\n\t\t}\n\t\ttemp = (ic & 0x3ff) | ((qc & 0x3ff) << 10);\n\t\todm_write_4byte(dm, 0x4168, temp);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]ADCK 0x4168 =0x%x\\n\", temp);\n#if 1\n\t\t/*check ADC DC offset*/\n\t\todm_write_4byte(dm, 0x1c3c, 0x000a8103);\n\t\thalrf_mode_8822c(dm, &ic, &qc);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]after ADCK i=0x%x, q=0x%x\",\n\t\t       ic, qc);\n#endif\n\t\tif (ic >= 0x200)\n\t\t\tic = 0x400 - ic;\n\t\tif (qc >= 0x200)\n\t\t\tqc = 0x400 - qc;\n\t\tif (ic < 5 && qc < 5)\n\t\t\tbreak;\n\t}\n/*2.ADCK step2*/\n\todm_write_4byte(dm, 0x1c3c, 0x00000003);\n\todm_write_4byte(dm, 0x410c, 0x10000260);\n\todm_write_4byte(dm, 0x4110, 0x02d508c4);\n\n\t/*3.release pull low switch on IQ path*/\n\todm_set_rf_reg(dm, RF_PATH_B, 0x8f, BIT(13), 0x1);\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]step2 DACK!!!!!!!!!!!!!!!!!!!!!!!!!!!\");\n\ti = 0;\n\twhile (i < 10) {\n\t\todm_write_4byte(dm, 0x4168, temp);\n/*DACK step1*/\n\t\ti++;\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]DACK count=%d\\n\", i);\n\todm_write_4byte(dm, 0x410c, 0xdff00220);\n\todm_write_4byte(dm, 0x4110, 0x02d508c5);\n\t\todm_write_4byte(dm, 0x9b4, 0xdb66db00);\n\todm_write_4byte(dm, 0x41b0, 0x0a11fb88);\n\todm_write_4byte(dm, 0x41bc, 0x0008ff81);\n\todm_write_4byte(dm, 0x41c0, 0x0003d208);\n\todm_write_4byte(dm, 0x41cc, 0x0a11fb88);\n\todm_write_4byte(dm, 0x41d8, 0x0008ff81);\n\todm_write_4byte(dm, 0x41dc, 0x0003d208);\n\n\todm_write_4byte(dm, 0x41b8, 0x60000000);\n\t\tODM_delay_ms(2);\n\todm_write_4byte(dm, 0x41bc, 0x000aff8d);\n\t\tODM_delay_ms(2);\n\todm_write_4byte(dm, 0x41b0, 0x0a11fb89);\n\todm_write_4byte(dm, 0x41cc, 0x0a11fb89);\n\t\tODM_delay_ms(1);\n\todm_write_4byte(dm, 0x41b8, 0x62000000);\n\todm_write_4byte(dm, 0x41d4, 0x62000000);\n\t\tODM_delay_ms(1);\n\t\thalrf_polling_check(dm, 0x4508, 0x7fff80, 0xffff);\n\t\thalrf_polling_check(dm, 0x4534, 0x7fff80, 0xffff);\n\todm_write_4byte(dm, 0x41b8, 0x02000000);\n\t\tODM_delay_ms(1);\n\todm_write_4byte(dm, 0x41bc, 0x0008ff87);\n\todm_write_4byte(dm, 0x9b4, 0xdb6db600);\n\n\t\todm_write_4byte(dm, 0x4110, 0x02d508c5);\n\t\todm_write_4byte(dm, 0x41bc, 0x0008ff87);\n\t\todm_write_4byte(dm, 0x4160, 0xf0000000);\n\t/*4.DACK step2*/\n\t\todm_set_bb_reg(dm, 0x41bc, 0xf0000000, 0x0);\n\t\todm_set_bb_reg(dm, 0x41c0, 0xf, 0x8);\n\t\todm_set_bb_reg(dm, 0x41d8, 0xf0000000, 0x0);\n\t\todm_set_bb_reg(dm, 0x41dc, 0xf, 0x8);\n\t\todm_write_4byte(dm, 0x1b00, 0x0000000a);\n\t\todm_write_1byte(dm, 0x1bcc, 0x3f);\n\t\todm_write_4byte(dm, 0x410c, 0xdff00220);\n\t\todm_write_4byte(dm, 0x4110, 0x02d508c5);\n\t\todm_write_4byte(dm, 0x1c3c, 0x000a8103);\n\t\thalrf_mode_8822c(dm, &ic, &qc);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]before DACK i=0x%x, q=0x%x\",\n\t\t       ic, qc);\n\t\t/*compensation value*/\n\t\tif (ic != 0x0)\n\t\t\tic = 0x400 - ic;\n\t\tif (qc != 0x0)\n\t\t\tqc = 0x400 - qc;\n\t\tif (ic < 0x300) {\n\t\t\tic = ic  * 2 * 6 / 5;\n\t\t\tic = ic + 0x80;\n\t\t} else {\n\t\t\tic = (0x400 - ic) * 2 * 6 / 5;\n\t\t\tic = 0x7f - ic;\n\t\t}\n\t\tif (qc < 0x300) {\n\t\t\tqc = qc * 2 * 6 / 5;\n\t\t\tqc = qc + 0x80;\n\t\t} else {\n\t\t\tqc = (0x400 - qc) * 2 * 6 / 5;\n\t\t\tqc = 0x7f - qc;\n\t\t}\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]DACK ic=0x%x, qc=0x%x\",\n\t\t       ic, qc);\n\t\tic_b = ic;\n\t\tqc_b = qc;\n\t/*5.DACK step3*/\n\t\todm_write_4byte(dm, 0x410c, 0xdff00220);\n\t\todm_write_4byte(dm, 0x4110, 0x02d508c5);\n\t\todm_write_4byte(dm, 0x9b4, 0xdb66db00);\n\t\todm_write_4byte(dm, 0x41b0, 0x0a11fb88);\n\t\todm_write_4byte(dm, 0x41bc, 0xc008ff81);\n\t\todm_write_4byte(dm, 0x41c0, 0x0003d208);\n\t\todm_set_bb_reg(dm, 0x41bc, 0xf0000000, ic & 0xf);\n\t\todm_set_bb_reg(dm, 0x41c0, 0xf, (ic & 0xf0) >> 4);\n\t\todm_write_4byte(dm, 0x41cc, 0x0a11fb88);\n\t\todm_write_4byte(dm, 0x41d8, 0xe008ff81);\n\t\todm_write_4byte(dm, 0x41dc, 0x0003d208);\n\t\todm_set_bb_reg(dm, 0x41d8, 0xf0000000, qc & 0xf);\n\t\todm_set_bb_reg(dm, 0x41dc, 0xf, (qc & 0xf0) >> 4);\n\t\todm_write_4byte(dm, 0x41b8, 0x60000000);\n\t\tODM_delay_ms(2);\n\t\todm_set_bb_reg(dm, 0x41bc, 0xe, 0x6);\n\t\tODM_delay_ms(2);\n\t\todm_write_4byte(dm, 0x41b0, 0x0a11fb89);\n\t\todm_write_4byte(dm, 0x41cc, 0x0a11fb89);\n\t\tODM_delay_ms(1);\n\t\todm_write_4byte(dm, 0x41b8, 0x62000000);\n\t\todm_write_4byte(dm, 0x41d4, 0x62000000);\n\t\tODM_delay_ms(1);\n\t\thalrf_polling_check(dm, 0x4524, 0x07f80000, ic);\n\t\thalrf_polling_check(dm, 0x4550, 0x07f80000, qc);\n\t\todm_write_4byte(dm, 0x41b8, 0x02000000);\n\t\tODM_delay_ms(1);\n\t\todm_set_bb_reg(dm, 0x41bc, 0xe, 0x3);\n\t\todm_write_4byte(dm, 0x9b4, 0xdb6db600);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x41bc =0x%x\",\n\t\t       odm_read_4byte(dm, 0x41bc));\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x41c0 =0x%x\",\n\t\t       odm_read_4byte(dm, 0x41c0));\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x41d8 =0x%x\",\n\t\t       odm_read_4byte(dm, 0x41d8));\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x41dc =0x%x\",\n\t\t       odm_read_4byte(dm, 0x41dc));\n#if 1\n\t\t/*check DAC DC offset*/\n\t\ttemp1 = ((adc_ic_b + 0x10) & 0x3ff) |\n\t\t       (((adc_qc_b + 0x10) & 0x3ff) << 10);\n\t\todm_write_4byte(dm, 0x4168, temp1);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]shift 0x4168 =0x%x\\n\",\n\t\t       odm_read_4byte(dm, 0x4168));\n\t\todm_write_4byte(dm, 0x4110, 0x02d508c5);\n\t\todm_write_4byte(dm, 0x4160, 0xf0000000);\n\t\thalrf_mode_8822c(dm, &ic, &qc);\n\t\tif (ic >= 0x10)\n\t\t\tic = ic - 0x10;\n\t\telse\n\t\t\tic = 0x400 - (0x10 - ic);\n\n\t\tif (qc >= 0x10)\n\t\t\tqc = qc - 0x10;\n\t\telse\n\t\t\tqc = 0x400 - (0x10 - qc);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]after DACK i=0x%x, q=0x%x\",\n\t\t       ic, qc);\n\t\ti_b = ic;\n\t\tq_b = qc;\n#endif\n\t\tif (ic >= 0x200)\n\t\t\tic = 0x400 - ic;\n\t\tif (qc >= 0x200)\n\t\t\tqc = 0x400 - qc;\n\t\tif (ic < 5 && qc < 5)\n\t\t\tbreak;\n\t}\n#endif\n\todm_write_4byte(dm, 0x4168, 0x0);\n\todm_write_4byte(dm, 0x4110, 0x02d508c4);\n\todm_set_bb_reg(dm, 0x41bc, 0x1, 0x0);\n\todm_set_bb_reg(dm, 0x4130, BIT(30), 0x1);\n\todm_write_4byte(dm, 0x1b00, 0x00000008);\n\todm_set_bb_reg(dm, 0x4130, BIT(30), 0x1);\n\todm_write_1byte(dm, 0x1bcc, 0x0);\n\todm_write_4byte(dm, 0x1b00, 0x0000000a);\n\todm_write_1byte(dm, 0x1bcc, 0x0);\n\ti_b = ic;\n\tq_b = qc;\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]PATH A:ic=0x%x, qc=0x%x\", ic_a, qc_a);\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]PATH B:ic=0x%x, qc=0x%x\", ic_b, qc_b);\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]PATH A:i=0x%x, q=0x%x\", i_a, q_a);\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]PATH B:i=0x%x, q=0x%x\", i_b, q_b);\n\thalrf_reload_bp_8822c(dm, bp_reg, bp);\n\thalrf_reload_bprf_8822c(dm, bp_rfreg, bp_rf);\n\thalrf_dack_backup_8822c(dm);\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]DACK end!!!!!!!\\n\");\n#endif\n}\n\nvoid halrf_dack_dbg_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i;\n\tu32 temp1, temp2, temp3;\n\n\ttemp1 = odm_get_bb_reg(dm, 0x1860, MASKDWORD);\n\ttemp2 = odm_get_bb_reg(dm, 0x4160, MASKDWORD);\n\ttemp3 = odm_get_bb_reg(dm, 0x9b4, MASKDWORD);\n\n\todm_set_bb_reg(dm, 0x9b4, MASKDWORD, 0xdb66db00);\n\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]MSBK result\\n\");\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]PATH A\\n\");\t\n\t//pathA\n\todm_set_bb_reg(dm, 0x1830, BIT(30), 0x0);\n\todm_set_bb_reg(dm, 0x1860, 0xfc000000, 0x3c);\n\t//i\n\tfor (i = 0; i < 0xf; i++) {\n\t\todm_set_bb_reg(dm, 0x18b0, 0xf0000000, i);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]msbk_d[0][0][%d]=0x%x\\n\", i,\n\t\t       odm_get_bb_reg(dm,0x2810,0x7fc0000));\n\t}\n\t//q\n\tfor (i = 0; i < 0xf; i++) {\n\t\todm_set_bb_reg(dm, 0x18cc, 0xf0000000, i);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]msbk_d[0][1][%d]=0x%x\\n\", i,\n\t\t       odm_get_bb_reg(dm,0x283c,0x7fc0000));\n\t}\n\t//pathB\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]PATH A\\n\");\n\todm_set_bb_reg(dm, 0x4130, BIT(30), 0x0);\n\todm_set_bb_reg(dm, 0x4160, 0xfc000000, 0x3c);\n\t//i\n\tfor (i = 0; i < 0xf; i++) {\n\t\todm_set_bb_reg(dm, 0x41b0, 0xf0000000, i);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]msbk_d[1][0][%d]=0x%x\\n\", i,\n\t\t       odm_get_bb_reg(dm,0x4510,0x7fc0000));\n\t}\n\t//q\n\tfor (i = 0; i < 0xf; i++) {\n\t\todm_set_bb_reg(dm, 0x41cc, 0xf0000000, i);\n\t\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]msbk_d[1][1][%d]=0x%x\\n\", i,\n\t\t       odm_get_bb_reg(dm,0x453c,0x7fc0000));\n\t}\n\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]DCK result\\n\");\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]PATH A\\n\");\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x18bc[31:28]=0x%x\\n\",\n\t\t       odm_get_bb_reg(dm,0x18bc,0xf0000000));\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x18c0[3:0]=0x%x\\n\",\n\t\t       odm_get_bb_reg(dm,0x18c0,0xf));\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x18d8[31:28]=0x%x\\n\",\n\t\t       odm_get_bb_reg(dm,0x18d8,0xf0000000));\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x18dc[3:0]=0x%x\\n\",\n\t\t       odm_get_bb_reg(dm,0x18dc,0xf));\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]PATH B\\n\");\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x41bc[31:28]=0x%x\\n\",\n\t\t       odm_get_bb_reg(dm,0x41bc,0xf0000000));\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x41c0[3:0]=0x%x\\n\",\n\t\t       odm_get_bb_reg(dm,0x41c0,0xf));\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x41d8[31:28]=0x%x\\n\",\n\t\t       odm_get_bb_reg(dm,0x41d8,0xf0000000));\n\tRF_DBG(dm, DBG_RF_DACK, \"[DACK]0x41dc[3:0]=0x%x\\n\",\n\t\t       odm_get_bb_reg(dm,0x41dc,0xf));\n\n\n\t//restore to normal\n\todm_set_bb_reg(dm, 0x1830, BIT(30), 0x1);\n\todm_set_bb_reg(dm, 0x4130, BIT(30), 0x1);\n\todm_set_bb_reg(dm, 0x1860, MASKDWORD, temp1);\n\todm_set_bb_reg(dm, 0x4160, MASKDWORD, temp2);\n\todm_set_bb_reg(dm, 0x9b4, MASKDWORD, temp3);\n}\n\nvoid _phy_x2_calibrate_8822c(struct dm_struct *dm)\n{\n\tRF_DBG(dm, DBG_RF_IQK, \"[X2K]X2K start!!!!!!!\\n\");\n\t/*X2K*/\n\t//Path A\n\todm_set_rf_reg(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK, 0x13108);\n\tODM_delay_ms(1);\n\todm_set_rf_reg(dm, RF_PATH_A, 0xb8, RFREGOFFSETMASK, 0xC0440);\t\n\todm_set_rf_reg(dm, RF_PATH_A, 0xba, RFREGOFFSETMASK, 0xE840D);\n\tODM_delay_ms(1);\n\todm_set_rf_reg(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK, 0x13124);\n\t//Path B\n\t// SYN is in the path A\n\tRF_DBG(dm, DBG_RF_IQK, \"[X2K]X2K end!!!!!!!\\n\");\n}\n\nvoid phy_x2_check_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 X2K_BUSY;\n\n\tRF_DBG(dm, DBG_RF_IQK, \"[X2K]X2K check start!!!!!!!\\n\");\n\t/*X2K*/\n\t//Path A\n\tODM_delay_ms(1);\n\tX2K_BUSY = (u8) odm_get_rf_reg(dm, RF_PATH_A, 0xb8, BIT(15));\n\tif (X2K_BUSY == 1) {\n\t\todm_set_rf_reg(dm, RF_PATH_A, 0xb8, RFREGOFFSETMASK, 0xC4440);\t\n\t\todm_set_rf_reg(dm, RF_PATH_A, 0xba, RFREGOFFSETMASK, 0x6840D);\n\t\todm_set_rf_reg(dm, RF_PATH_A, 0xb8, RFREGOFFSETMASK, 0x80440);\t\t\n\t\tODM_delay_ms(1);\n\t}\n\t//Path B\n\t// SYN is in the path A\n\tRF_DBG(dm, DBG_RF_IQK, \"[X2K]X2K check end!!!!!!!\\n\");\n}\n\n/*LCK VERSION:0x1*/\nvoid phy_lc_calibrate_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#if 1\n\t_phy_aac_calibrate_8822c(dm);\n\t_phy_rt_calibrate_8822c(dm);\n#endif\n}\n\nvoid configure_txpower_track_8822c(struct txpwrtrack_cfg *config)\n{\n\tconfig->swing_table_size_cck = TXSCALE_TABLE_SIZE;\n\tconfig->swing_table_size_ofdm = TXSCALE_TABLE_SIZE;\n\tconfig->threshold_iqk = IQK_THRESHOLD;\n\tconfig->threshold_dpk = DPK_THRESHOLD;\n\tconfig->average_thermal_num = AVG_THERMAL_NUM_8822C;\n\tconfig->rf_path_count = MAX_PATH_NUM_8822C;\n\tconfig->thermal_reg_addr = RF_T_METER_8822C;\n\n\tconfig->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr8822c;\n\tconfig->do_iqk = do_iqk_8822c;\n\tconfig->phy_lc_calibrate = halrf_lck_trigger;\n\tconfig->get_delta_swing_table = get_delta_swing_table_8822c;\n}\n\n#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))\nvoid phy_set_rf_path_switch_8822c(struct dm_struct *dm, boolean is_main)\n#else\nvoid phy_set_rf_path_switch_8822c(void *adapter, boolean is_main)\n#endif\n{\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n#endif\n#endif\n\t/*BY mida Request */\n\tif (is_main) {\n\t\t/*WiFi*/\n\t\todm_set_bb_reg(dm, R_0x70, BIT(26), 0x1);\n\t} else {\n\t\t/*BT*/\n\t\todm_set_bb_reg(dm, R_0x70, BIT(26), 0x0);\n\t}\n}\n\n#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))\nboolean _phy_query_rf_path_switch_8822c(struct dm_struct *dm)\n#else\nboolean _phy_query_rf_path_switch_8822c(void *adapter)\n#endif\n{\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n#endif\n#endif\n\tif (odm_get_bb_reg(dm, R_0x70, BIT(26)) == 0x1)\n\t\treturn true;\t/*WiFi*/\n\telse\n\t\treturn false;\n}\n\n#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))\nboolean phy_query_rf_path_switch_8822c(struct dm_struct *dm)\n#else\nboolean phy_query_rf_path_switch_8822c(void *adapter)\n#endif\n{\n#if DISABLE_BB_RF\n\treturn true;\n#endif\n#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))\n\treturn _phy_query_rf_path_switch_8822c(dm);\n#else\n\treturn _phy_query_rf_path_switch_8822c(adapter);\n#endif\n}\n\nvoid halrf_rxbb_dc_cal_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tu8 path;\n\n\tfor (path = 0; path < 2; path++) {\n\t\todm_set_rf_reg(dm, (enum rf_path)path, 0x92, RFREG_MASK, 0x84800);\n\t\tODM_delay_us(5);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, 0x92, RFREG_MASK, 0x84801);\n\t\tODM_delay_us(600);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, 0x92, RFREG_MASK, 0x84800);\n\t}\n}\n\nvoid halrf_rfk_handshake_8822c(void *dm_void, boolean is_before_k)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tu8 u1b_tmp, h2c_parameter;\n\tu16 count;\n\n\tif (is_before_k) {\n\t\tRF_DBG(dm, DBG_RF_IQK | DBG_RF_DPK | DBG_RF_TX_PWR_TRACK,\n\t\t       \"[RFK] WiFi / BT RFK handshake start!!\\n\");\n\n\t\tif (!rf->is_bt_iqk_timeout) {\n\t\t\t/* Check if BT request to do IQK (0xaa[6]) or is doing IQK (0xaa[5]), 600ms timeout*/\n\t\tcount = 0;\n\t\t\tu1b_tmp = (u8)odm_get_mac_reg(dm, 0xa8, BIT(22) | BIT(21));\n\t\t\twhile (u1b_tmp != 0 && count < 30000) {\n\t\t\tODM_delay_us(20);\n\t\t\t\tu1b_tmp = (u8)odm_get_mac_reg(dm, 0xa8, BIT(22) | BIT(21));\n\t\t\tcount++;\n\t\t}\n\n\t\t\tif (count >= 30000) {\n\t\t\tRF_DBG(dm, DBG_RF_IQK | DBG_RF_DPK | DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"[RFK] Wait BT IQK finish timeout!!\\n\");\n\n\t\t\t\trf->is_bt_iqk_timeout = true;\n\t\t\t}\n\t\t}\n\n\t\t/* Send RFK start H2C cmd*/\n\t\th2c_parameter = 1;\n\t\todm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);\n\n\t\t/* Check 0x49c[0] or 100ms timeout*/\n\t\tcount = 0;\n\t\tu1b_tmp = (u8)odm_get_mac_reg(dm, 0x49c, BIT(0));\n\t\twhile (u1b_tmp != 0x1 && count < 5000) {\n\t\t\tODM_delay_us(20);\n\t\t\tu1b_tmp = (u8)odm_get_mac_reg(dm, 0x49c, BIT(0));\n\t\t\tcount++;\n\t\t}\n\n\t\tif (count >= 5000)\n\t\t\tRF_DBG(dm, DBG_RF_IQK | DBG_RF_DPK | DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"[RFK] Send WiFi RFK start H2C cmd FAIL!!\\n\");\n\n\t} else {\n\t\t/* Send RFK finish H2C cmd*/\n\t\th2c_parameter = 0;\n\t\todm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);\n\t\t/* Check 0x49c[0] or 100ms timeout*/\n\t\tcount = 0;\n\t\tu1b_tmp = (u8)odm_get_mac_reg(dm, 0x49c, BIT(0));\n\t\twhile (u1b_tmp != 0 && count < 5000) {\n\t\t\tODM_delay_us(20);\n\t\t\tu1b_tmp = (u8)odm_get_mac_reg(dm, 0x49c, BIT(0));\n\t\t\tcount++;\n\t\t}\n\n\t\tif (count >= 5000)\n\t\t\tRF_DBG(dm, DBG_RF_IQK | DBG_RF_DPK | DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"[RFK] Send WiFi RFK finish H2C cmd FAIL!!\\n\");\n\n\t\tRF_DBG(dm, DBG_RF_IQK | DBG_RF_DPK | DBG_RF_TX_PWR_TRACK,\n\t\t       \"[RFK] WiFi / BT RFK handshake finish!!\\n\");\n\t}\n}\n\n#endif /*(RTL8822C_SUPPORT == 0)*/\n"
  },
  {
    "path": "hal/phydm/halrf/rtl8822c/halrf_8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALRF_8822C_H__\n#define __HALRF_8822C_H__\n\n#define AVG_THERMAL_NUM_8822C 4\n#define RF_T_METER_8822C 0x42\n#define DACK_REG_8822C 16\n#define DACK_RF_8822C 1\nvoid halrf_rf_lna_setting_8822c(\n\tstruct dm_struct *p_dm_void,\n\tenum halrf_lna_set type);\n\nvoid configure_txpower_track_8822c(\n\tstruct txpwrtrack_cfg *config);\n\nvoid odm_tx_pwr_track_set_pwr8822c(\n\tvoid *dm_void,\n\tenum pwrtrack_method method,\n\tu8 rf_path,\n\tu8 channel_mapped_index);\n\nvoid get_delta_swing_table_8198f(\n\tvoid *dm_void,\n\tu8 **temperature_up_a,\n\tu8 **temperature_down_a,\n\tu8 **temperature_up_b,\n\tu8 **temperature_down_b,\n\tu8 **temperature_up_cck_a,\n\tu8 **temperature_down_cck_a,\n\tu8 **temperature_up_cck_b,\n\tu8 **temperature_down_cck_b\n\t);\n\nvoid get_delta_swing_table_8822c_ex(\n\tvoid *p_dm_void,\n\tu8 **temperature_up_c,\n\tu8 **temperature_down_c,\n\tu8 **temperature_up_d,\n\tu8 **temperature_down_d,\n\tu8 **temperature_up_cck_c,\n\tu8 **temperature_down_cck_c,\n\tu8 **temperature_up_cck_d,\n\tu8 **temperature_down_cck_d\n\t);\n\nvoid halrf_dac_cal_all_8822c(void *dm_void);\n\nvoid halrf_dac_cal_8822c(void *dm_void, boolean force);\n\nvoid halrf_dack_dbg_8822c(void *dm_void);\n\nvoid phy_lc_calibrate_8822c(\n\tvoid *dm_void);\n\nvoid phy_x2_check_8822c(void *dm_void);\n\nvoid phy_set_rf_path_switch_8822c(\n#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))\n\tstruct dm_struct *dm,\n#else\n\tvoid *adapter,\n#endif\n\tboolean is_main);\n\nvoid halrf_rxbb_dc_cal_8822c(void *dm_void);\n\nvoid halrf_rfk_handshake_8822c(void *dm_void, boolean is_before_k);\n\nvoid halrf_dack_restore_8822c(void *dm_void);\n#endif /*__HALRF_8822C_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/rtl8822c/halrf_dpk_8822c.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#include \"mp_precomp.h\"\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#if RT_PLATFORM == PLATFORM_MACOSX\n#include \"phydm_precomp.h\"\n#else\n#include \"../phydm_precomp.h\"\n#endif\n#else\n#include \"../../phydm_precomp.h\"\n#endif\n\n#if (RTL8822C_SUPPORT == 1)\n\n/*---------------------------Define Local Constant---------------------------*/\n\n/*8822C DPK ver:0x19 20190425*/\n\nstatic u32\n_btc_wait_indirect_reg_ready_8822c(\n\tstruct dm_struct *dm)\n{\n\tu32 delay_count = 0;\n\t\n\t/* wait for ready bit before access 0x1700 */\n\twhile (1) {\n\t\tif ((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) {\n\t\t\tdelay_ms(10);\n\t\t\tif (++delay_count >= 10)\n\t\t\tbreak;\n\t\t} else {\n\t\t\tbreak;\n\t\t}\n\t}\n\t\n\treturn delay_count;\n}\n\nstatic u32\n_btc_read_indirect_reg_8822c(\n\tstruct dm_struct *dm,\n\tu16 reg_addr)\n{\n\tu32 delay_count = 0;\n\n\t/* wait for ready bit before access 0x1700 */\n\t_btc_wait_indirect_reg_ready_8822c(dm);\n\n\todm_write_4byte(dm, 0x1700, 0x800F0000 | reg_addr);\n\n\treturn odm_read_4byte(dm, 0x1708); /* get read data */\n}\n\nstatic void\n_btc_write_indirect_reg_8822c(\n\tstruct dm_struct *dm,\n\tu16 reg_addr,\n\tu32 bit_mask,\n\tu32 reg_value)\n{\n\tu32 val, i = 0, bitpos = 0, delay_count = 0;\n\n\tif (bit_mask == 0x0)\n\t\treturn;\n\n\tif (bit_mask == 0xffffffff) {\n\t/* wait for ready bit before access 0x1700 */\n\t_btc_wait_indirect_reg_ready_8822c(dm);\n\n\t/* put write data */\n\todm_write_4byte(dm, 0x1704, reg_value);\n\n\todm_write_4byte(dm, 0x1700, 0xc00F0000 | reg_addr);\n\t} else {\n\t\tfor (i = 0; i <= 31; i++) {\n\t\t\tif (((bit_mask >> i) & 0x1) == 0x1) {\n\t\t\t\tbitpos = i;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\t/* read back register value before write */\n\t\tval = _btc_read_indirect_reg_8822c(dm, reg_addr);\n\t\tval = (val & (~bit_mask)) | (reg_value << bitpos);\n\n\t\t/* wait for ready bit before access 0x1700 */\n\t\t_btc_wait_indirect_reg_ready_8822c(dm);\n\n\t\todm_write_4byte(dm, 0x1704, val); /* put write data */\n\t\todm_write_4byte(dm, 0x1700, 0xc00F0000 | reg_addr);\n\t}\n}\n\nvoid btc_set_gnt_wl_bt_8822c(\n\tvoid *dm_void,\n\tboolean is_before_k)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tif (is_before_k) {\n\t\tdpk_info->gnt_control = odm_get_mac_reg(dm, R_0x70, MASKDWORD);\n\t\tdpk_info->gnt_value = _btc_read_indirect_reg_8822c(dm, 0x38);\n\t\t\n\t\t/*force GNT control to WL*/\n\t\todm_set_mac_reg(dm, R_0x70, BIT(26), 0x1);\n\t\t/*force GNT_WL=1, GNT_BT=0*/\n\t\t_btc_write_indirect_reg_8822c(dm, 0x38, 0xFF00, 0x77);\n#if 0\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] ori 0x70 / 0x38 = 0x%x / 0x%x\\n\",\n\t\t       dpk_info->gnt_control, dpk_info->gnt_value);\n\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] set 0x70/0x38 = 0x%x/0x%x\\n\",\n\t\t       odm_get_mac_reg(dm, R_0x70, MASKDWORD),\n\t\t       _btc_read_indirect_reg_8822c(dm, 0x38));\n#endif\n\t} else {\n\t\t_btc_write_indirect_reg_8822c(dm, 0x38, MASKDWORD, dpk_info->gnt_value);\n\t\todm_set_mac_reg(dm, R_0x70, MASKDWORD, dpk_info->gnt_control);\n#if 0\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] load 0x70 / 0x38 = 0x%x / 0x%x\\n\",\n\t\t       odm_get_mac_reg(dm, R_0x70, MASKDWORD),\n\t\t       _btc_read_indirect_reg_8822c(dm, 0x38));\n#endif\n\t}\n}\n\nvoid _backup_mac_bb_registers_8822c(\n\tstruct dm_struct *dm,\n\tu32 *reg,\n\tu32 *reg_backup,\n\tu32 reg_num)\n{\n\tu32 i;\n\n\tfor (i = 0; i < reg_num; i++) {\n\t\treg_backup[i] = odm_read_4byte(dm, reg[i]);\n#if 0\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] Backup MAC/BB 0x%x = 0x%x\\n\",\n\t\t       reg[i], reg_backup[i]);\n#endif\n\t}\n}\n\nvoid _backup_rf_registers_8822c(\n\tstruct dm_struct *dm,\n\tu32 *rf_reg,\n\tu32 rf_reg_backup[][2])\n{\n\tu32 i;\n\n\tfor (i = 0; i < DPK_RF_REG_NUM_8822C; i++) {\n\t\trf_reg_backup[i][RF_PATH_A] = odm_get_rf_reg(dm, RF_PATH_A,\n\t\t\trf_reg[i], RFREG_MASK);\n\t\trf_reg_backup[i][RF_PATH_B] = odm_get_rf_reg(dm, RF_PATH_B,\n\t\t\trf_reg[i], RFREG_MASK);\n#if 0\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] Backup RF_A 0x%x = 0x%x\\n\",\n\t\t       rf_reg[i], rf_reg_backup[i][RF_PATH_A]);\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] Backup RF_B 0x%x = 0x%x\\n\",\n\t\t       rf_reg[i], rf_reg_backup[i][RF_PATH_B]);\n#endif\n\t}\n}\n\nvoid _reload_mac_bb_registers_8822c(\n\tstruct dm_struct *dm,\n\tu32 *reg,\n\tu32 *reg_backup,\n\tu32 reg_num)\n\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu32 i;\n\n\t/*toggle IGI*/\n\todm_write_4byte(dm, 0x1d70, 0x50505050);\n\n\tfor (i = 0; i < reg_num; i++) {\n\t\todm_write_4byte(dm, reg[i], reg_backup[i]);\n#if 0\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] Reload MAC/BB 0x%x = 0x%x\\n\",\n\t\t       reg[i], reg_backup[i]);\n#endif\n\t}\n\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc); /*subpage 2*/\n\todm_set_bb_reg(dm, R_0x1bd4, 0x000000f0, 0x4); /*force CLK off for power saving*/\n}\n\nvoid _reload_rf_registers_8822c(\n\tstruct dm_struct *dm,\n\tu32 *rf_reg,\n\tu32 rf_reg_backup[][2])\n{\n\tu32 i, rf_reg_8f[DPK_RF_PATH_NUM_8822C] = {0x0};\n\n\tfor (i = 0; i < DPK_RF_REG_NUM_8822C; i++) {\n\t\todm_set_rf_reg(dm, RF_PATH_A, rf_reg[i], RFREG_MASK,\n\t\t\t       rf_reg_backup[i][RF_PATH_A]);\n\t\todm_set_rf_reg(dm, RF_PATH_B, rf_reg[i], RFREG_MASK,\n\t\t\t       rf_reg_backup[i][RF_PATH_B]);\n#if 0\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] Reload RF_A 0x%x = 0x%x\\n\",\n\t\t       rf_reg[i], rf_reg_backup[i][RF_PATH_A]);\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] Reload RF_B 0x%x = 0x%x\\n\",\n\t\t       rf_reg[i], rf_reg_backup[i][RF_PATH_B]);\n#endif\n\t}\n#if 0\n\t/*reload RF 0x8f for non-saving power mode*/\n\tfor (i = 0; i < DPK_RF_PATH_NUM_8822C; i++) {\n\t\trf_reg_8f[i] = odm_get_rf_reg(dm, (enum rf_path)i,\n\t\t\tRF_0x8f, 0x00fff);\n\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x8f, RFREG_MASK,\n\t\t\t       0xa8000 | rf_reg_8f[i]);\n\t}\n#endif\n}\n\nvoid _dpk_information_8822c(\n\tstruct dm_struct *dm)\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu32  reg_rf18;\n\n\tif (odm_get_bb_reg(dm, R_0x1e7c, BIT(30)))\n\t\tdpk_info->is_tssi_mode = true;\n\telse\n\t\tdpk_info->is_tssi_mode = false;\n\n\treg_rf18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK);\n\n\tdpk_info->dpk_band = (u8)((reg_rf18 & BIT(16)) >> 16); /*0/1:G/A*/\n\tdpk_info->dpk_ch = (u8)reg_rf18 & 0xff;\n\tdpk_info->dpk_bw = (u8)((reg_rf18 & 0x3000) >> 12); /*3/2/1:20/40/80*/\n\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] TSSI/ Band/ CH/ BW = %d / %s / %d / %s\\n\",\n\t       dpk_info->is_tssi_mode, dpk_info->dpk_band == 0 ? \"2G\" : \"5G\",\n\t       dpk_info->dpk_ch,\n\t       dpk_info->dpk_bw == 3 ? \"20M\" : (dpk_info->dpk_bw == 2 ? \"40M\" : \"80M\"));\n}\n\nvoid _dpk_rxbb_dc_cal_8822c(\n\tstruct dm_struct *dm,\n\tu8 path)\n{\n\todm_set_rf_reg(dm, (enum rf_path)path, 0x92, RFREG_MASK, 0x84800);\n\tODM_delay_us(5);\n\todm_set_rf_reg(dm, (enum rf_path)path, 0x92, RFREG_MASK, 0x84801);\n\tODM_delay_us(600);\n\todm_set_rf_reg(dm, (enum rf_path)path, 0x92, RFREG_MASK, 0x84800);\n}\n\nu8 _dpk_dc_corr_check_8822c(\n\tstruct dm_struct *dm,\n\tu8 path)\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu16 dc_i, dc_q;\n\tu8 corr_val, corr_idx;\n\n\todm_write_4byte(dm, 0x1bd4, 0x000900F0);\n\tdc_i = (u16)odm_get_bb_reg(dm, 0x1bfc, 0x0fff0000);\n\tdc_q = (u16)odm_get_bb_reg(dm, 0x1bfc, 0x00000fff);\n\n\tif (dc_i >> 11 == 1)\n\t\tdc_i = 0x1000 - dc_i;\n\tif (dc_q >> 11 == 1)\n\t\tdc_q = 0x1000 - dc_q;\n\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] S%d DC I/Q, = %d / %d\\n\", path, dc_i, dc_q);\n\n\todm_write_4byte(dm, 0x1bd4, 0x000000F0);\n\tcorr_idx = (u8)odm_get_bb_reg(dm, 0x1bfc, 0x000000ff);\n\tcorr_val = (u8)odm_get_bb_reg(dm, 0x1bfc, 0x0000ff00);\n\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] S%d Corr_idx / Corr_val = %d / %d\\n\",\n\t       path, corr_idx, corr_val);\n\n\tif ((dc_i > 200) || (dc_q > 200) || (corr_idx < 40) || (corr_idx > 65))\n\t\treturn 1;\n\telse\n\t\treturn 0;\n\n}\n\nvoid _dpk_tx_pause_8822c(\n\tstruct dm_struct *dm)\n{\n\tu8 reg_rf0_a, reg_rf0_b;\n\tu16 count = 0;\n\n\todm_write_1byte(dm, R_0x522, 0xff);\n\todm_set_bb_reg(dm, R_0x1e70, 0x0000000f, 0x2); /*hw tx stop*/\n\n\treg_rf0_a = (u8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, 0xF0000);\n\treg_rf0_b = (u8)odm_get_rf_reg(dm, RF_PATH_B, RF_0x00, 0xF0000);\n\n\twhile (((reg_rf0_a == 2) || (reg_rf0_b == 2)) && count < 2500) {\n\t\treg_rf0_a = (u8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, 0xF0000);\n\t\treg_rf0_b = (u8)odm_get_rf_reg(dm, RF_PATH_B, RF_0x00, 0xF0000);\n\t\tODM_delay_us(2);\n\t\tcount++;\n\t}\n\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] Tx pause!!\\n\");\n}\n\nvoid _dpk_mac_bb_setting_8822c(\n\tstruct dm_struct *dm)\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\t_dpk_tx_pause_8822c(dm);\n\n\tif (dpk_info->is_tssi_mode) {\n\t\todm_set_bb_reg(dm, R_0x1e7c, BIT(30), 0x0);\n\t\todm_set_bb_reg(dm, R_0x18a4, BIT(28), 0x0);\n\t\todm_set_bb_reg(dm, R_0x41a4, BIT(28), 0x0);\n\t}\n\n\todm_set_bb_reg(dm, R_0x1e24, BIT(17), 0x1); /*r_gothrough_iqkdpk*/\n\n\todm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff); /*BB CCA off*/\n\n\t/*r_rftxen_gck_force*/\n\todm_set_bb_reg(dm, R_0x1864, BIT(31), 0x1);\n\todm_set_bb_reg(dm, R_0x4164, BIT(31), 0x1);\n\t/*r_dis_sharerx_txgat*/\n\todm_set_bb_reg(dm, R_0x180c, BIT(27), 0x1);\n\todm_set_bb_reg(dm, R_0x410c, BIT(27), 0x1);\n\n\todm_set_bb_reg(dm, R_0x186c, BIT(7), 0x1);\n\todm_set_bb_reg(dm, R_0x416c, BIT(7), 0x1);\n\n\todm_set_bb_reg(dm, R_0x180c, BIT(1) | BIT(0), 0x0);\n\todm_set_bb_reg(dm, R_0x410c, BIT(1) | BIT(0), 0x0);\n\n\todm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3); /*CCK RXIQ weighting=0*/\n\n\todm_set_bb_reg(dm, R_0x80c, 0x0000000f, 0x8); /*freq shap filter*/\n\n\t/*odm_write_1byte(dm, R_0x820, 0x33);*/\n\todm_set_bb_reg(dm, R_0x824, 0x000f0000, 0x3);\n\todm_set_bb_reg(dm, R_0x824, 0x0f000000, 0x3);\n\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] MAC/BB setting for DPK mode\\n\");\n}\n\nvoid _dpk_manual_txagc_8822c(\n\tstruct dm_struct *dm,\n\tboolean is_manual)\n{\n\todm_set_bb_reg(dm, R_0x18a4, BIT(7), is_manual);\n\todm_set_bb_reg(dm, R_0x41a4, BIT(7), is_manual);\n}\n\nvoid _dpk_set_txagc_8822c(\n\tstruct dm_struct *dm)\n{\n\todm_set_bb_reg(dm, R_0x18a0, 0x007C0000, 0x1f);\n\todm_set_bb_reg(dm, R_0x41a0, 0x007C0000, 0x1f);\n\todm_set_bb_reg(dm, 0x18e8, 0x0001F000, 0x1f);\n\todm_set_bb_reg(dm, 0x41e8, 0x0001F000, 0x1f);\n}\n\nvoid _dpk_afe_setting_8822c(\n\tstruct dm_struct *dm,\n\tboolean is_do_dpk)\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tif (is_do_dpk) {\n\t\todm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xFFFFFFFF);\n\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700f0001);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700f0001);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x701f0001);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x702f0001);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x703f0001);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x704f0001);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705f0001);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x706f0001);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x707f0001);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x708f0001);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x709f0001);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70af0001);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70bf0001);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70cf0001);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70df0001);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ef0001);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ff0001);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ff0001);\n\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700f0001);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700f0001);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x701f0001);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x702f0001);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x703f0001);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x704f0001);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705f0001);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x706f0001);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x707f0001);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x708f0001);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x709f0001);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70af0001);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70bf0001);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70cf0001);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70df0001);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ef0001);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ff0001);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ff0001);\n\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] AFE for DPK mode\\n\");\n\t} else {\n\t\tif (dpk_info->is_tssi_mode) {\n\t\t\todm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xf7d5005e);\n\n\t\t\todm_set_bb_reg(dm, R_0x1860, 0x00007000, 0x4 >> dpk_info->dpk_band);\n\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8041);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x701f0040 | (0x4 >> dpk_info->dpk_band));\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x702f0040 | (0x4 >> dpk_info->dpk_band));\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x703f0040 | (0x4 >> dpk_info->dpk_band));\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x704f0040 | (0x4 >> dpk_info->dpk_band));\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705b8041);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x706f0040 | (0x4 >> dpk_info->dpk_band));\n\n\t\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700b8041);\n\t\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x701f0040 | (0x4 >> dpk_info->dpk_band));\n\t\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x702f0040 | (0x4 >> dpk_info->dpk_band));\n\t\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x703f0040 | (0x4 >> dpk_info->dpk_band));\n\t\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x704f0040 | (0x4 >> dpk_info->dpk_band));\n\t\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705b8041);\n\t\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x706f0040 | (0x4 >> dpk_info->dpk_band));\n\n\t\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] AFE for TSSI mode\\n\");\n\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xFFA1005E);\n\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8041);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70144041);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70244041);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70344041);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70444041);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705b8041);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70644041);\n\n\t\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700b8041);\n\t\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70144041);\n\t\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70244041);\n\t\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70344041);\n\t\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70444041);\n\t\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705b8041);\n\t\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70644041);\n\n\t\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] AFE for non-TSSI mode\\n\");\n\t\t}\n\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x707b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x708b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x709b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ab8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70bb8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70cb8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70db8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70eb8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70fb8041);\n\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x707b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x708b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x709b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ab8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70bb8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70cb8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70db8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70eb8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70fb8041);\n\t}\n}\n\nvoid _dpk_pre_setting_8822c(\n\tstruct dm_struct *dm)\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu8 path;\n\n\tfor (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {\n\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x19, RFREG_MASK, 0x0);\n\n\t\todm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | (path << 1));\n\t\tif (dpk_info->dpk_band == 0x0) /*txagc bnd*/\n\t\t\todm_set_bb_reg(dm, R_0x1b60, MASKDWORD, 0x1f100000);\n\t\telse\n\t\t\todm_set_bb_reg(dm, R_0x1b60, MASKDWORD, 0x1f0d0000);\n\t\todm_set_bb_reg(dm, R_0x1b44, 0x00007000, 0x4); /*GL = val*0.5+1*/\n\t\todm_set_bb_reg(dm, R_0x1b20, 0xc0000000, 0x3); /*CFIR to TX*/\n\t}\n\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc);  /*one-shot 6ms*/\n\todm_set_bb_reg(dm, R_0x1be4, MASKDWORD, 0x3b23170b);\n\todm_set_bb_reg(dm, R_0x1be8, MASKDWORD, 0x775f5347);\n}\n\nu32 _dpk_rf_setting_8822c(\n\tstruct dm_struct *dm,\n\tu8 path)\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\ts8 txidx_offset = 0x0;\n\tu32 value32 = 0, ori_txbb = 0;\n\n#if 0\n\tif (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x944 | (path << 9))) {\n\t\tvalue32 = phydm_get_bb_dbg_port_val(dm);\n\t\tphydm_release_bb_dbg_port(dm);\n\t}\t\n\n\ttxidx_offset = (value32 >> 8) & 0x7f;\n\n\tif ((txidx_offset >> 6) == 1)\n\t\ttxidx_offset = (txidx_offset - 0x80) / 4;\n\telse \n\t\ttxidx_offset = txidx_offset / 4;\t\n\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] S%d txidx_offset = 0x%x\\n\",\n\t       path, txidx_offset);\n#endif\n\tif (dpk_info->dpk_band == 0x0) { /*2G*/\n\t\t/*TXAGC for gainloss*/\n\t\todm_set_rf_reg(dm, (enum rf_path)path,\n\t\t\t       RF_0x00, RFREG_MASK, 0x50017 + txidx_offset);\n\n\t\tori_txbb = odm_get_rf_reg(dm, (enum rf_path)path,\n\t\t\t\t  RF_0x56, RFREG_MASK);\n\t\t/*debug TX Gain*/\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);\n\t\t/*debug power trim*/\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(19), 0x1);\n\t\t/*set offset to zero*/\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x55, 0x7C000, 0x0);\n\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x56,\n\t\t\t       RFREG_MASK, ori_txbb);\n\n\t\t/*ATT Gain*/\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x55,\n\t\t\t       BIT(4) | BIT(3) | BIT(2), 0x1);\n\t\t/*mixer*/\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x87,\n\t\t\t       BIT(18), 0x0);\n\t\t/*PGA2*/\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x00,\n\t\t\t       0x003e0, 0xf);\n\t} else { /*5G*/\n\t\n\t\t/*TXAGC for gainloss*/\n\t\todm_set_rf_reg(dm, (enum rf_path)path,\n\t\t\t       RF_0x00, RFREG_MASK, 0x50017 + txidx_offset);\n\n\t\tori_txbb = odm_get_rf_reg(dm, (enum rf_path)path,\n\t\t\t\t  RF_0x56, RFREG_MASK);\n\t\t/*debug TX Gain*/\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);\n\t\t/*debug power trim*/\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(19), 0x1);\n\t\t/*set offset to zero*/\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x55, 0x7C000, 0x0);\n\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x56,\n\t\t\t       RFREG_MASK, ori_txbb);\n\n\t\t/*ATT Gain*/\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x63,\n\t\t\t       BIT(15) | BIT(14), 0x0);\n\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x63,\n\t\t\t       BIT(4) | BIT(3) | BIT(2), 0x6);\n\t\t/*switch*/\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x63,\n\t\t\t       BIT(13) | BIT(12), 0x1);\n\t\t/*mixer*/\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x8a,\n\t\t\t       BIT(4) | BIT(3), 0x0);\n\t\t/*PGA2*/\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x00,\n\t\t\t       0x003e0, 0xf);\n\t}\n\n\t\t/*Bypass RXBB filter*/\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xde,\n\t\t\t       BIT(2), 0x1);\n\t\t/*BW of RXBB*/\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x1a,\n\t\t\t       BIT(11) | BIT(10), 0x0);\n\t\t/*BW of TXBB*/\n\t\tif (dpk_info->dpk_bw == 0x1) /*80M*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x1a,\n\t\t\t\t       BIT(14) | BIT(13) | BIT(12), 0x2);\n\t\telse\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x1a,\n\t\t\t\t       BIT(14) | BIT(13) | BIT(12), 0x1);\n\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x8f,\n\t\t\t       BIT(1), 0x1);\n\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] ori TXAGC/TXBB/offset = 0x%x / 0x%x / %+d\\n\",\n\t       odm_get_rf_reg(dm, (enum rf_path)path, RF_0x00, 0x0001f),\n\t       odm_get_rf_reg(dm, (enum rf_path)path, RF_0x56, 0x0001f),\n\t       (ori_txbb & 0x1f) - 0xf);  /*txagc 0x17 = txbb 0xf*/\n\n\tODM_delay_us(100); /*delay for TIA SV loop*/\n\n\treturn ori_txbb & 0x1f;\n}\n\nu8 _dpk_one_shot_8822c(\n\tstruct dm_struct *dm,\n\tu8 path,\n\tu8 action)\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu8 temp = 0x0, bw = 0x0, reg_2d9c = 0x0, sync_done = 0x0, result = 0;\n\tu16 dpk_cmd = 0x0, count = 0;\n\n\tif (dpk_info->dpk_bw == 0x1) /*80M*/\n\t\tbw = 2;\n\telse\n\t\tbw = 0;\n\n\tif (action == GAIN_LOSS)\n\t\ttemp = 0x14 + path;\n\telse if (action == DO_DPK)\n\t\ttemp = 0x16 + path + bw;\n\telse if (action == DPK_ON)\n\t\ttemp = 0x1a + path;\n\telse if (action == DAGC)\n\t\ttemp = 0x1c + path + bw;\n\n\tbtc_set_gnt_wl_bt_8822c(dm, true);\n\n\tif (action ==0) {\n\t\todm_set_bb_reg(dm, R_0x1bb4, BIT(12), 0x1);\n\t\todm_set_bb_reg(dm, R_0x1bb4, BIT(12), 0x0);\n\n\t\todm_set_bb_reg(dm, R_0x1bd4, 0x001f0000, 0x0);\n\t\tODM_delay_us(20);\n\t\tsync_done = (u8)odm_get_bb_reg(dm, R_0x1bfc, BIT(31));\n\t\twhile (sync_done != 0x1 && count < 1000) {\n\t\t\tODM_delay_us(20);\n\t\t\tsync_done = (u8)odm_get_bb_reg(dm, R_0x1bfc, BIT(31));\n\t\t\tcount++;\n\t\t}\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));\n\t\todm_set_bb_reg(dm, R_0x1bcc, 0x0000003f, 0x9); /*ItQt -6dB*/\n\n\t\tdpk_cmd = (temp << 8) | 0x48;\n\t\todm_set_bb_reg(dm, R_0x1b00, MASKDWORD, dpk_cmd);\n\t\todm_set_bb_reg(dm, R_0x1b00, MASKDWORD, dpk_cmd + 1);\n\n\t\treg_2d9c = odm_read_1byte(dm, R_0x2d9c);\n\t\twhile (reg_2d9c != 0x55 && count < 1000) {\n\t\t\tODM_delay_us(20);\n\t\t\treg_2d9c = odm_read_1byte(dm, R_0x2d9c);\n\t\t\tcount++;\n\t\t}\n\t\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));\n\t\todm_set_bb_reg(dm, R_0x1bcc, 0x0000003f, 0x0); /*ItQt 0dB*/\n\t}\n\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] one-shot for S%d %s = 0x%x (count=%d)\\n\",\n\t       path, action == 1 ? \"GL\" : (action == 2 ? \"DO_DPK\" :\n\t       (action == 3 ? \"DPK_ON\" : (action == 0 ? \"Cal_PWR\" : \"DAGC\"))),\n\t       \tdpk_cmd, count);\n\n\tif (count == 1000) {\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] one-shot over 20ms!!!!\\n\");\n\t\tresult = 1;\n\t}\n\n\tbtc_set_gnt_wl_bt_8822c(dm, false);\n\n\todm_write_1byte(dm, 0x1b10, 0x0);\n\n\treturn result;\n}\n\nu16 _dpk_dgain_read_8822c(\n\tstruct dm_struct *dm,\n\tu8 path)\n{\n\tu16 dgain = 0x0;\n\n\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc); /*subpage 2*/\n\todm_set_bb_reg(dm, R_0x1bd4, 0x00ff0000, 0x0);\n\n\tdgain = (u16)odm_get_bb_reg(dm, R_0x1bfc, 0x0FFF0000); /*[27:16]*/\n\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] DGain = 0x%x (%d)\\n\", dgain, dgain);\n\n\treturn dgain;\n}\n\nu8 _dpk_thermal_read_8822c(\n\tvoid *dm_void,\n\tu8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x42, BIT(19), 0x1);\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x42, BIT(19), 0x0);\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x42, BIT(19), 0x1);\n\tODM_delay_us(15);\n\n\treturn (u8)odm_get_rf_reg(dm, (enum rf_path)path, RF_0x42, 0x0007e);\n}\n\nu32 _dpk_pas_read_8822c(\n\tstruct dm_struct *dm,\n\tu8 path,\n\tu8 action)\n{\n\tu8 k;\n\tu32 reg_1bfc, i_val = 0, q_val = 0;\n\n\todm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | (path << 1));\n\todm_set_bb_reg(dm, R_0x1b48, BIT(14), 0x0);\n\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00060001);\n\todm_set_bb_reg(dm, R_0x1b4c, MASKDWORD, 0x00000000);\n\n\tswitch (action) {\n\tcase LOSS_CHK:\n\n\t\todm_set_bb_reg(dm, R_0x1b4c, MASKDWORD, 0x00080000);\n\n\t\tq_val = odm_get_bb_reg(dm, R_0x1bfc, MASKHWORD);\n\t\ti_val = odm_get_bb_reg(dm, R_0x1bfc, MASKLWORD);\n\n\t\tif (i_val >> 15 != 0)\n\t\t\ti_val = 0x10000 - i_val;\n\t\tif (q_val >> 15 != 0)\n\t\t\tq_val = 0x10000 - q_val;\n\t\n#if (DPK_PAS_CHK_DBG_8822C)\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK][%s] i=0x%x,q=0x%x,i^2+q^2=0x%x\\n\",\n\t\t       \"LOSS\", i_val, q_val, i_val*i_val + q_val*q_val);\n#endif\n\t\tbreak;\n\n\tcase PAS_READ:\n\n\t\tfor (k = 0; k < 64; k++) {\n\t\t\todm_set_bb_reg(dm, R_0x1b4c, MASKDWORD,\n\t\t\t\t       (0x00080000 | (k << 24)));\n#if 0\n\t\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] 0x1b4c[%d] = 0x%x\\n\", k,\n\t\t\t       odm_get_bb_reg(dm, R_0x1b4c, MASKDWORD));\n#endif\n\t\t\treg_1bfc = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);\n\t\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] PA scan_S%d = 0x%08x\\n\",\n\t\t\t       path, reg_1bfc);\n\t\t}\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\todm_set_bb_reg(dm, R_0x1b4c, MASKDWORD, 0x00000000);\n\treturn i_val*i_val + q_val*q_val;\n}\n\nu8 _dpk_gainloss_result_8822c(\n\tstruct dm_struct *dm,\n\tu8 path)\n{\n\tu8 result;\n\n\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));\n\todm_set_bb_reg(dm, R_0x1b48, BIT(14), 0x1);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00060000);\n\n\tresult = (u8)odm_get_bb_reg(dm, R_0x1bfc, 0x000000f0);\n\n\todm_set_bb_reg(dm, R_0x1b48, BIT(14), 0x0);\n\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] tmp GL = %d\\n\", result);\n\treturn result;\n}\n\nu8 _dpk_agc_chk_8822c(\n\tstruct dm_struct *dm,\n\tu8 path,\n\tu8 limited_pga,\n\tu8 check)\n{\n\tu8 result = 0;\n\tu16 dgain =0;\n\tu32 loss = 0;\n\tu32 loss_db = 0;\n\n\tif (check == GAIN_CHK) {\n\t\t_dpk_one_shot_8822c(dm, path, DAGC);\n\t\tdgain = _dpk_dgain_read_8822c(dm, path);\n\n\t\tif ((dgain > 1535) && !limited_pga) { /*DGain > 1535 happen*/\n\t\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] Small DGain!!\\n\");\n\t\t\tresult = 2;\n\t\t\treturn result;\n\t\t} else if ((dgain < 768) && !limited_pga) { /*DGain < 768 happen*/\n\t\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] Large DGain!!\\n\");\n\t\t\tresult = 1;\n\t\t\treturn result;\n\t\t} else\n\t\t\treturn result;\n\n\t} else if (check == LOSS_CHK) {\n\t\tloss = _dpk_pas_read_8822c(dm, path, LOSS_CHK);\n\n\t\tif (loss < 0x4000000) {\n\t\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] GLoss < 0dB happen!!\\n\");\n\t\t\tresult = 4;\n\t\t\treturn result;\n\t\t}\n\t\tloss_db = 3 * halrf_psd_log2base(loss >> 13);\n\t\t\t\n#if (DPK_PAS_CHK_DBG_8822C)\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] GLoss = %d.%02ddB\\n\",\n\t\t       (loss_db - 3870) / 100, (loss_db -3870) % 100);\n#endif\t\n\t\tif ((loss_db - 3870) > 1000) { /*GL > 10dB*/\n\t\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] GLoss > 10dB happen!!\\n\");\n\t\t\tresult = 3;\n\t\t\treturn result;\n\t\t} else if ((loss_db - 3870) < 250) { /*GL < 2.5dB*/\n\t\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] GLoss < 2.5dB happen!!\\n\");\n\t\t\tresult = 4;\n\t\t\treturn result;\n\t\t}  else\n\t\t\treturn result;\n\t} else\n\t\treturn result;\n\n}\n\nu8 _dpk_pas_agc_8822c(\n\tstruct dm_struct *dm,\n\tu8 path,\n\tu8 gain_only,\n\tu8 loss_only)\n{\n\tu8 tmp_txbb = 0, tmp_pga = 0, i = 0;\n\tu8 goout = 0, limited_pga = 0, agc_cnt = 0;\n\n\tdo {\n\t\tswitch (i) {\n\t\tcase 0: /*Gain check first*/\n\t\t\ttmp_txbb = (u8)odm_get_rf_reg(dm, (enum rf_path)path,\n\t\t\t\t\t\t       RF_0x56, 0x0001f);\n\t\t\ttmp_pga = (u8)odm_get_rf_reg(dm, (enum rf_path)path,\n\t\t\t\t\t\t     RF_0x00, 0x003e0);\n\n\t\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t\t       \"[DPK][AGC] Start TXBB=0x%x, PGA=0x%x\\n\",\n\t\t\t       tmp_txbb, tmp_pga);\n\n\t\t\tif (loss_only)\n\t\t\t\ti = 5;\n\t\t\telse {\n\t\t\t\ti = _dpk_agc_chk_8822c(dm, path, limited_pga,\n\t\t\t\t\t\t       GAIN_CHK);\n\n\t\t\tif ((i == 0) && gain_only)\n\t\t\t\tgoout = 1;\n\t\t\telse if (i == 0)\n\t\t\t\ti =5;\n\t\t\t}\n\n\t\t\tagc_cnt++;\n\t\t\tbreak;\n\n\t\tcase 1: /*Gain > criterion*/\n\t\t\tif (tmp_pga > 0xe) {\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path,\n\t\t\t\t\t       RF_0x00, 0x003e0, 0xc);\n\t\t\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t\t\t       \"[DPK][AGC] PGA(-1) = 0xc\\n\");\n\t\t\t} else if ((0xb < tmp_pga) && (tmp_pga < 0xf)) {\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path,\n\t\t\t\t\t       RF_0x00, 0x003e0, 0x0);\n\t\t\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t\t\t       \"[DPK][AGC] PGA(-1) = 0x0\\n\");\n\t\t\t} else if (tmp_pga < 0xc) {\n\t\t\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t\t\t       \"[DPK][AGC] PGA@ lower bound!!\\n\");\n\t\t\t\tlimited_pga = 1;\n\t\t\t}\n\t\t\ti = 0;\n\t\t\tbreak;\n\n\t\tcase 2: /*Gain < criterion*/\n\t\t\tif (tmp_pga < 0xc) {\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path,\n\t\t\t\t\t       RF_0x00, 0x003e0, 0xc);\n\t\t\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t\t\t       \"[DPK][AGC] PGA(+1) = 0xc\\n\");\n\t\t\t} else if ((0xb < tmp_pga) && (tmp_pga < 0xf)) {\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path,\n\t\t\t\t\t       RF_0x00, 0x003e0, 0xf);\n\t\t\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t\t\t       \"[DPK][AGC] PGA(+1) = 0xf\\n\");\n\t\t\t} else if (tmp_pga > 0xe) {\n\t\t\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t\t\t       \"[DPK][AGC] PGA@ upper bound!!\\n\");\n\t\t\t\tlimited_pga = 1;\n\t\t\t}\n\t\t\ti = 0;\n\t\t\tbreak;\n\n\t\tcase 3: /*GL > criterion*/\n\t\t\tif (tmp_txbb == 0x0) {\n\t\t\t\tgoout = 1;\n\t\t\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t\t\t       \"[DPK][AGC] TXBB@ lower bound!!\\n\");\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\ttmp_txbb = tmp_txbb - 2;\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path,\n\t\t\t\t       RF_0x56, 0x0001f, tmp_txbb);\n\t\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK][AGC] TXBB(-2) = 0x%x\\n\",\n\t\t\t       tmp_txbb);\n\t\t\tlimited_pga = 0;\n\t\t\ti = 0;\n\t\t\tbreak;\n\n\t\tcase 4:\t/*GL < criterion*/\n\t\t\tif (tmp_txbb == 0x1f) {\n\t\t\t\tgoout = 1;\n\t\t\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t\t\t       \"[DPK][AGC] TXBB@ upper bound!!\\n\");\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\ttmp_txbb = tmp_txbb + 3;\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path,\n\t\t\t\t       RF_0x56, 0x0001f, tmp_txbb);\n\t\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK][AGC] TXBB(+3) = 0x%x\\n\",\n\t\t\t       tmp_txbb);\n\t\t\tlimited_pga = 0;\n\t\t\ti = 0;\n\t\t\tbreak;\n\n\t\tcase 5: /*Loss check*/\n\t\t\t_dpk_one_shot_8822c(dm, path, GAIN_LOSS);\n\t\t\ti = _dpk_agc_chk_8822c(dm, path, limited_pga, LOSS_CHK);\n\n#if (DPK_PAS_DBG_8822C)\n\t\t\t_dpk_pas_read_8822c(dm, path, PAS_READ);\n#endif\n\t\t\tif (i == 0)\n\t\t\t\tgoout = 1;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tgoout = 1;\n\t\t\tbreak;\n\t\t}\t\n\t} while (!goout && (agc_cnt < 6));\n\n\treturn tmp_txbb;\n}\n\nboolean _dpk_coef_iq_check_8822c(\n\tstruct dm_struct *dm,\n\tu16 coef_i,\n\tu16 coef_q)\n{\n\tif ((coef_i == 0x1000) || (coef_i == 0x0fff) ||\n\t    (coef_q == 0x1000) || (coef_q == 0x0fff))\n\t\treturn 1;\n\telse\n\t\treturn 0;\n}\n\nu32 _dpk_coef_transfer_8822c(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu32 reg_1bfc = 0;\n\tu16 coef_i = 0, coef_q = 0;\n\n\treg_1bfc = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);\n\n#if (DPK_COEF_DBG_8822C)\n\tRF_DBG(dm, DBG_RF_DPK,\n\t       \"[DPK][coef_r] 0x1bfc = 0x%08x\\n\", reg_1bfc);\n#endif\n\n#if 1\n\tcoef_i = (u16)odm_get_bb_reg(dm, R_0x1bfc, MASKHWORD) & 0x1fff;\n\tcoef_q = (u16)odm_get_bb_reg(dm, R_0x1bfc, MASKLWORD) & 0x1fff;\n\n\tcoef_q = ((0x2000 - coef_q) & 0x1fff) - 1;\n\n\treg_1bfc = (coef_i << 16) | coef_q;\n#endif\n\treturn reg_1bfc;\n}\n\nvoid _dpk_get_coef_8822c(\n\tvoid *dm_void,\n\tu8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\todm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x0000000c);\n\t\n\tif (path == RF_PATH_A) {\n\t\todm_set_bb_reg(dm, R_0x1bb4, BIT(24), 0x0);\n\t\todm_set_bb_reg(dm, R_0x1b04, MASKDWORD, 0x30000080);\n\t} else if (path == RF_PATH_B) {\n\t\todm_set_bb_reg(dm, R_0x1bb4, BIT(24), 0x1);\n\t\todm_set_bb_reg(dm, R_0x1b5c, MASKDWORD, 0x30000080);\n\t}\n\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x000400F0);\n\tdpk_info->coef[path][0] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x040400F0);\n\tdpk_info->coef[path][1] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x080400F0);\n\tdpk_info->coef[path][2] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x010400F0);\n\tdpk_info->coef[path][3] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x050400F0);\n\tdpk_info->coef[path][4] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x090400F0);\n\tdpk_info->coef[path][5] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x020400F0);\n\tdpk_info->coef[path][6] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x060400F0);\n\tdpk_info->coef[path][7] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0A0400F0);\n\tdpk_info->coef[path][8] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x030400F0);\n\tdpk_info->coef[path][9] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x070400F0);\n\tdpk_info->coef[path][10] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0B0400F0);\n\tdpk_info->coef[path][11] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0C0400F0);\n\tdpk_info->coef[path][12] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x100400F0);\n\tdpk_info->coef[path][13] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0D0400F0);\n\tdpk_info->coef[path][14] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x110400F0);\n\tdpk_info->coef[path][15] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0E0400F0);\n\tdpk_info->coef[path][16] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x120400F0);\n\tdpk_info->coef[path][17] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x0F0400F0);\n\tdpk_info->coef[path][18] = _dpk_coef_transfer_8822c(dm);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x130400F0);\n\tdpk_info->coef[path][19] = _dpk_coef_transfer_8822c(dm);\n\n}\n\nu8 _dpk_coef_read_8822c(\n\tvoid *dm_void,\n\tu8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu8 addr, result = 1;\n\tu16 coef_i, coef_q;\n\n\tfor (addr = 0; addr < 20; addr++) {\n\t\tcoef_i = (u16)((dpk_info->coef[path][addr] & 0x1fff0000) >> 16);\n\t\tcoef_q = (u16)(dpk_info->coef[path][addr] & 0x1fff);\n\n\t\tif (_dpk_coef_iq_check_8822c(dm, coef_i, coef_q)) {\n\t\t\tresult = 0;\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn result;\n}\n\nvoid _dpk_coef_write_8822c(\n\tvoid *dm_void,\n\tu8 path,\n\tu8 result)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu8 addr;\n\tu16 tmp_reg;\n\tu32 coef;\n\n\todm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x0000000c);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x000000F0);\n\n\tfor (addr = 0; addr < 20; addr++) {\n\t\tif (path == RF_PATH_A)\n\t\t\ttmp_reg = 0x1b0c + addr * 4;\n\t\telse\n\t\t\ttmp_reg = 0x1b64 + addr * 4;\n\n\t\tif (!result) {\n\t\t\tif (addr == 3)\n\t\t\t\tcoef = 0x04001fff;\n\t\t\telse\n\t\t\t\tcoef = 0x00001fff;\n\t\t} else\n\t\t\tcoef = dpk_info->coef[path][addr];\n\t\todm_set_bb_reg(dm, tmp_reg, MASKDWORD, coef);\n\n#if (DPK_COEF_DBG_8822C)\n\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t       \"[DPK][coef_w] S%d 0x%x = 0x%08x\\n\", path, tmp_reg, coef);\n#endif\n\t}\n}\n\nvoid _dpk_coef_default_8822c(\n\tvoid *dm_void,\n\tu8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu8 addr;\n\tu16 tmp_reg;\n\tu32 coef;\n\n\todm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x0000000c);\n\todm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x000000F0);\n\n\tfor (addr = 0; addr < 20; addr++) {\n\t\tif (path == RF_PATH_A)\n\t\t\ttmp_reg = 0x1b0c + addr * 4;\n\t\telse\n\t\t\ttmp_reg = 0x1b64 + addr * 4;\n\n\t\tif (addr == 3)\n\t\t\tcoef = 0x04001fff;\n\t\telse\n\t\t\tcoef = 0x00001fff;\n\t\todm_set_bb_reg(dm, tmp_reg, MASKDWORD, coef);\n\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t       \"[DPK][Coef write] 0x%x = 0x%x\\n\", tmp_reg, coef);\n\t}\n}\n\nvoid _dpk_fill_result_8822c(\n\tvoid *dm_void,\n\tu32 dpk_txagc,\n\tu8 path,\n\tu8 result)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));\n\n\tif (result) /*check PASS*/\n\t\todm_write_1byte(dm, R_0x1b67, (u8)(dpk_txagc - 6)); /*ItQt -6dB*/\n\telse\n\t\todm_write_1byte(dm, R_0x1b67, 0x00);\t\n\n\tdpk_info->result[path] = result;\n\tdpk_info->dpk_txagc[path] = odm_read_1byte(dm, R_0x1b67);\n\n\tRF_DBG(dm, DBG_RF_DPK,\n\t       \"[DPK] S%d 0x1b67 = 0x%x\\n\", path, odm_read_1byte(dm, R_0x1b67));\n\n\t_dpk_coef_write_8822c(dm, path, result);\n}\n\nu32 _dpk_gainloss_8822c(\n\tstruct dm_struct *dm,\n\tu8 path)\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu8 k = 0, tx_agc_search = 0x0, t1 = 0, t2 = 0;\n\tu8 tx_agc, tx_bb, ori_txbb, ori_txagc;\n\ts8 txidx_offset = 0x0;\n\n\tori_txbb = (u8)_dpk_rf_setting_8822c(dm, path);\n\n\tori_txagc = (u8)odm_get_rf_reg(dm, (enum rf_path)path, RF_0x00, 0x0001f);\n\n\t_dpk_rxbb_dc_cal_8822c(dm, path); /*DCK for DPK*/\n\n\t_dpk_one_shot_8822c(dm, path, DAGC);\n\t_dpk_dgain_read_8822c(dm, path);\n\n\tif (_dpk_dc_corr_check_8822c(dm, path)) {\n\t\t_dpk_rxbb_dc_cal_8822c(dm, path); /*re-do DCK for DPK*/\n\t\t_dpk_one_shot_8822c(dm, path, DAGC);\n\t\t_dpk_dc_corr_check_8822c(dm, path);\n\t}\n\n\tt1 = _dpk_thermal_read_8822c(dm, path);\n#if 1\n\ttx_bb = _dpk_pas_agc_8822c(dm, path, false, true);\n#else\n\t_dpk_one_shot_8822c(dm, path, GAIN_LOSS);\n#endif\n\n#if 0\n\tRF_DBG(dm, DBG_RF_DPK,\n\t       \"[DPK][GL] S%d RF_0x0=0x%x, 0x63=0x%x, 0x8a=0x%x, 0x1a=0x%x, 0x8f=0x%x\\n\",\n\t       path, odm_get_rf_reg(dm, (enum rf_path)path, RF_0x00, RFREG_MASK),\n\t       odm_get_rf_reg(dm, (enum rf_path)path, RF_0x63, RFREG_MASK),\n\t       odm_get_rf_reg(dm, (enum rf_path)path, RF_0x8a, RFREG_MASK),\n\t       odm_get_rf_reg(dm, (enum rf_path)path, RF_0x1a, RFREG_MASK),\n\t       odm_get_rf_reg(dm, (enum rf_path)path, RF_0x8f, RFREG_MASK));\n#endif\n\ttx_agc_search = _dpk_gainloss_result_8822c(dm, path);\n\n\tif (tx_bb < tx_agc_search) /*aviod txbb < 0*/\n\t\ttx_bb = 0;\n\telse\n\t\ttx_bb = tx_bb - tx_agc_search;\n\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0x0001f, tx_bb);\n\t\n\ttx_agc = ori_txagc - (ori_txbb - tx_bb);\n\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK][GL] S%d TXAGC=0x%x, TXBB=0x%x\\n\",\n\t       path, tx_agc, tx_bb);\n\n\tt2 = _dpk_thermal_read_8822c(dm, path);\n\n\tdpk_info->thermal_dpk_delta[path] = HALRF_ABS(t2, t1);\n\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] S%d thermal delta of GL = %d (%d - %d)\\n\",\n\t       path, dpk_info->thermal_dpk_delta[path], t2, t1);\n\n\treturn tx_agc;\n}\n\nu8 _dpk_by_path_8822c(\n\tstruct dm_struct *dm,\n\tu32 tx_agc,\n\tu8 path)\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu8 result = 1;\n\tu16 dc_i, dc_q;\n#if 0\n\ttx_agc = (odm_get_rf_reg(dm, (enum rf_path)path, RF_0x00,\n\t\t\t\t RFREG_MASK) & ~0x1f) | tx_agc;\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK][DO_DPK] RF0x0 = 0x%x\\n\", tx_agc);\n\n\t/*TXAGC for DPK*/\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x00, RFREG_MASK, tx_agc);\n\n\tRF_DBG(dm, DBG_RF_DPK,\n\t       \"[DPK][GL] S%d RF 0x63=0x%x, 0x8a=0x%x, 0x1a=0x%x, 0x8f=0x%x\\n\",\n\t       path, odm_get_rf_reg(dm, (enum rf_path)path, RF_0x63, RFREG_MASK),\n\t       odm_get_rf_reg(dm, (enum rf_path)path, RF_0x8a, RFREG_MASK),\n\t       odm_get_rf_reg(dm, (enum rf_path)path, RF_0x1a, RFREG_MASK),\n\t       odm_get_rf_reg(dm, (enum rf_path)path, RF_0x8f, RFREG_MASK));\n#endif\n\tresult = _dpk_one_shot_8822c(dm, path, DO_DPK);\n\n\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));\n\n\tresult = result | (u8)odm_get_bb_reg(dm, R_0x1b08, BIT(26));\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK][DO_DPK] DPK Fail = %x\\n\", result);\n\n\t/*set RX high gain for RXBB DCK*/\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x00, RFREG_MASK, 0x33e14);\n\n\t_dpk_get_coef_8822c(dm, path);\n\n#if 0\n\todm_write_4byte(dm, 0x1bd4, 0x000900F0);\n\tdc_i = (u16)odm_get_bb_reg(dm, 0x1bfc, 0x0fff0000);\n\tdc_q = (u16)odm_get_bb_reg(dm, 0x1bfc, 0x00000fff);\n\n\tif (dc_i >> 11 == 1)\n\t\tdc_i = 0x1000 - dc_i;\n\tif (dc_q >> 11 == 1)\n\t\tdc_q = 0x1000 - dc_q;\n\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] S%d DC i/q = %d / %d\\n\", path, dc_i, dc_q);\n#endif\n#if (DPK_PAS_DBG_8822C)\n\t_dpk_pas_read_8822c(dm, path, PAS_READ);\n#endif\n\treturn result;\n}\n\nvoid _dpk_cal_pwr_8822c(\n\tstruct dm_struct *dm,\n\tu8 path)\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu16 tmp_gs = 0;\n\n\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));\n\n\todm_set_bb_reg(dm, R_0x1b20, BIT(25), 0x0);\t/*BypassDPD=0*/\n\todm_set_bb_reg(dm, R_0x1b20, 0xc0000000, 0x0);\t/* disable CFIR to TX*/\n\todm_set_bb_reg(dm, R_0x1bcc, 0xc000003f, 0x9);\t/* ItQt shift 1 bit*/\n\todm_set_bb_reg(dm, R_0x1bcc, BIT(21), 0x1);\t/* inner loopback*/\n\t\n\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc);\n\todm_set_bb_reg(dm, R_0x1bd4, 0x000000f0, 0xf);\n\n\tif (path == RF_PATH_A) {\n\t\t/*manual pwsf+gs*/\n\t\todm_set_bb_reg(dm, R_0x1b04, 0x0fffffff, 0x1066680);\n\t\t/*enable MDPD*/\n\t\todm_set_bb_reg(dm, R_0x1b08, BIT(31), 0x1);\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x1b5c, 0x0fffffff, 0x1066680);\n\t\todm_set_bb_reg(dm, R_0x1b60, BIT(31), 0x1);\n\t}\n\t\n\tif (dpk_info->dpk_bw == 0x1) { /*80M*/\n\t\t/*TPG DC*/\n\t\todm_write_4byte(dm, R_0x1bf8, 0x80001310);\n\t\todm_write_4byte(dm, R_0x1bf8, 0x00001310);\n\t\todm_write_4byte(dm, R_0x1bf8, 0x810000DB);\n\t\todm_write_4byte(dm, R_0x1bf8, 0x010000DB);\n\t\todm_write_4byte(dm, R_0x1bf8, 0x0000B428);\n\t\t/*set TPG*/\n\t\todm_write_4byte(dm, R_0x1bf4, 0x05020000 | (BIT(path) << 28));\n\t} else {\n\t\todm_write_4byte(dm, R_0x1bf8, 0x8200190C);\n\t\todm_write_4byte(dm, R_0x1bf8, 0x0200190C);\n\t\todm_write_4byte(dm, R_0x1bf8, 0x8301EE14);\n\t\todm_write_4byte(dm, R_0x1bf8, 0x0301EE14);\n\t\todm_write_4byte(dm, R_0x1bf8, 0x0000B428);\n\t\todm_write_4byte(dm, R_0x1bf4, 0x05020008 | (BIT(path) << 28));\n\t}\n\n\todm_set_bb_reg(dm, R_0x1bb4, 0xff000000, 0x8 | path);\n\n\t_dpk_one_shot_8822c(dm, path, 0);\n\n\t/*restore*/\n\todm_set_bb_reg(dm, R_0x1bf4, 0xff000000, 0x0); /*TPG off*/\n\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));\n\todm_set_bb_reg(dm, R_0x1bcc, 0xc000003f, 0x0);\t/* ItQt*/\n\todm_set_bb_reg(dm, R_0x1bcc, BIT(21), 0x0);\t/* inner loopback off*/\n\t\n\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc);\n\n\tif (path == RF_PATH_A)\n\t\todm_set_bb_reg(dm, R_0x1b04, 0x0fffffff, 0x5b);\n\telse \n\t\todm_set_bb_reg(dm, R_0x1b5c, 0x0fffffff, 0x5b);\n\n\todm_set_bb_reg(dm, R_0x1bd4, 0x001f0000, 0x0);\n\n\ttmp_gs = (u16)odm_get_bb_reg(dm, R_0x1bfc, 0x0FFF0000);\n#if 0\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] tmp_gs = 0x%x\\n\", tmp_gs);\n#endif\n\ttmp_gs = (tmp_gs * 910) >> 10; /*910 = 0x5b * 10*/\n\n\tif ((tmp_gs % 10) >= 5)\n\t\ttmp_gs = tmp_gs / 10 + 1;\n\telse\n\t\ttmp_gs = tmp_gs / 10;\n\n\tif (path == RF_PATH_A)\n\t\todm_set_bb_reg(dm, R_0x1b04, 0x0fffffff, tmp_gs);\n\telse \n\t\todm_set_bb_reg(dm, R_0x1b5c, 0x0fffffff, tmp_gs);\n\n\tdpk_info->dpk_gs[path] = tmp_gs;\n\n}\n\nvoid _dpk_on_8822c(\n\tstruct dm_struct *dm,\n\tu8 path)\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\t_dpk_one_shot_8822c(dm, path, DPK_ON);\n\t\n\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));\n\todm_set_bb_reg(dm, R_0x1b20, 0xc0000000, 0x0); /* disable CFIR to TX*/\n\n\tif ((dpk_info->dpk_path_ok & BIT(path)) >> path)\n\t\t_dpk_cal_pwr_8822c(dm, path);\n\t\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] S%d DPD on!!!\\n\\n\", path);\n}\n\nvoid dpk_coef_read_8822c(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu8 path, addr;\n\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] ========= Coef Read Start =========\\n\");\n\n\tfor (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {\n\t\tfor (addr = 0; addr < 20; addr++)\n\t\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t\t       \"[DPK] Read S%d coef[%2d]= 0x%x\\n\",\n\t\t\t       path, addr, dpk_info->coef[path][addr]);\n\t}\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] ========= Coef Read Finish =========\\n\");\n}\n\nu8 _dpk_check_fail_8822c(\n\tstruct dm_struct *dm,\n\tboolean is_fail,\n\tu32 dpk_txagc,\n\tu8 path)\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu8 result;\n\n\tif (!is_fail)\n\t\tif (_dpk_coef_read_8822c(dm, path))\n\t\t\tresult = 1; /*check PASS*/\n\t\telse\n\t\t\tresult = 0; /*check FAIL*/\n\telse\n\t\tresult = 0; /*check FAIL*/\n\t\n\t_dpk_fill_result_8822c(dm, dpk_txagc, path, result);\n\treturn result;\n}\n\nvoid _dpk_result_reset_8822c(\n\tstruct dm_struct *dm)\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu8 path;\n\n\tdpk_info->dpk_path_ok = 0;\n\n\tfor (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {\n\n\t\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));\n\t\todm_set_bb_reg(dm, R_0x1b58, 0x0000007f, 0x0);\n\n\t\tdpk_info->dpk_txagc[path] = 0;\n\t\tdpk_info->result[path] = 0;\n\t\tdpk_info->dpk_gs[path] = 0x5b;\n\t\tdpk_info->pre_pwsf[path] = 0;\n\n\t\tdpk_info->thermal_dpk[path] = _dpk_thermal_read_8822c(dm, path);\n\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] init thermal S%d = %d\\n\", path,\n\t\t       dpk_info->thermal_dpk[path]);\n#if 0\n\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t       \"[DPK][reset] S%d pwsf=0x%x, dpk_result=%d\\n\",\n\t\t       path, dpk_info->pwsf[path], dpk_info->result[path],\n#endif\n\t}\n}\n\nvoid _dpk_calibrate_8822c(\n\tstruct dm_struct *dm,\n\tu8 path)\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu8 dpk_fail = 1, retry_cnt;\n\tu32 dpk_txagc = 0;\n\n\tRF_DBG(dm, DBG_RF_DPK,\n\t       \"[DPK] =========== S%d DPK Start ===========\\n\", path);\n\n\tfor (retry_cnt = 0; retry_cnt < 1; retry_cnt++) {\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] retry = %d\\n\", retry_cnt);\n\n\t\tdpk_txagc = _dpk_gainloss_8822c(dm, path);\n\n\t\tdpk_fail = _dpk_by_path_8822c(dm, dpk_txagc, path);\n\n\t\tif (_dpk_check_fail_8822c(dm, dpk_fail, dpk_txagc, path))\n\t\t\tbreak;\n\t\t}\n\n\tRF_DBG(dm, DBG_RF_DPK,\n\t       \"[DPK] =========== S%d DPK Finish ==========\\n\", path);\n\n\tif (dpk_info->result[path])\n\t\tdpk_info->dpk_path_ok = dpk_info->dpk_path_ok | BIT(path);\n\n}\n\nvoid _dpk_path_select_8822c(\n\tstruct dm_struct *dm)\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n#if (DPK_PATH_A_8822C)\n\t_dpk_calibrate_8822c(dm, RF_PATH_A);\n#endif\n\n#if (DPK_PATH_B_8822C)\n\t_dpk_calibrate_8822c(dm, RF_PATH_B);\n#endif\n\t_dpk_on_8822c(dm, RF_PATH_A);\n\t_dpk_on_8822c(dm, RF_PATH_B);\n}\n\nvoid _dpk_result_summary_8822c(\n\tstruct dm_struct *dm)\n{\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu8 path;\n\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] ======== DPK Result Summary =======\\n\");\n\n\tfor (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {\n\n\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t       \"[DPK] S%d dpk_txagc = 0x%x, dpk_result = %d\\n\",\n\t\t       path, dpk_info->dpk_txagc[path], dpk_info->result[path]);\n\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] S%d gain scaling = 0x%x\\n\",\n\t\t       path, dpk_info->dpk_gs[path]);\n\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] S%d DPK is %s\\n\", path,\n\t\t       ((dpk_info->dpk_path_ok & BIT(path)) >> path) ?\n\t\t       \"Success\" : \"Fail\");\n\t}\n\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] dpk_path_ok = 0x%x\\n\",\n\t       dpk_info->dpk_path_ok);\n\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] ======== DPK Result Summary =======\\n\");\n\n}\n\nvoid _dpk_reload_data_8822c(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu8 path;\n\n\tif ((dpk_info->dpk_path_ok == 0) && (dpk_info->dpk_ch == 0))\n\t\treturn; /*never do DPK before*/\n\n\tfor (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {\n\n\t\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));\n\t\tif (dpk_info->dpk_band == 0x0) /*txagc bnd*/\n\t\t\todm_set_bb_reg(dm, R_0x1b60, MASKDWORD, 0x1f100000);\n\t\telse\n\t\t\todm_set_bb_reg(dm, R_0x1b60, MASKDWORD, 0x1f0d0000);\n\n\t\todm_write_1byte(dm, R_0x1b67, dpk_info->dpk_txagc[path]);\n\n\t\t_dpk_coef_write_8822c(dm, path, (dpk_info->dpk_path_ok & BIT(path)) >> path);\n\n\t\t_dpk_one_shot_8822c(dm, path, DPK_ON);\n\n\t\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc);\n\n\t\tif (path == RF_PATH_A)\n\t\t\todm_set_bb_reg(dm, R_0x1b04, 0x0fffffff, dpk_info->dpk_gs[0]);\n\t\telse\n\t\t\todm_set_bb_reg(dm, R_0x1b5c, 0x0fffffff, dpk_info->dpk_gs[1]);\n\t}\n}\n\nu8 dpk_reload_8822c(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu8 channel;\n\n\tdpk_info->is_reload = false;\n\n\tchannel = (u8)(odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK) & 0xff);\n\n\tif (channel == dpk_info->dpk_ch) {\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] DPK reload for CH%d!!\\n\", dpk_info->dpk_ch);\n\t\t_dpk_reload_data_8822c(dm);\n\t\tdpk_info->is_reload = true;\n\t}\n\n\treturn dpk_info->is_reload;\n}\n\nvoid do_dpk_8822c(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu32 bb_reg_backup[DPK_BB_REG_NUM_8822C];\n\tu32 rf_reg_backup[DPK_RF_REG_NUM_8822C][DPK_RF_PATH_NUM_8822C];\n\n\tu32 bb_reg[DPK_BB_REG_NUM_8822C] = {\n\t\tR_0x520, R_0x820, R_0x824, R_0x1c3c, R_0x1d58,\n\t\tR_0x1864, R_0x4164, R_0x180c, R_0x410c, R_0x186c,\n\t\tR_0x416c, R_0x1a14, R_0x1e70, R_0x80c, R_0x1d70,\n\t\tR_0x1e7c, R_0x18a4, R_0x41a4};\n\tu32 rf_reg[DPK_RF_REG_NUM_8822C] = {\n\t\tRF_0x19, RF_0x1a, RF_0x55, RF_0x63, RF_0x87,\n\t\tRF_0x8f, RF_0xde};\n\n\tif (dm->ext_pa && (*dm->band_type == ODM_BAND_2_4G)) {\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] Skip DPK due to ext_PA exist!!\\n\");\n\t\treturn;\n\t} else if (dm->ext_pa_5g && (*dm->band_type == ODM_BAND_5G)) {\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] Skip DPK due to 5G_ext_PA exist!!\\n\");\n\t\treturn;\n\t} else if (!dpk_info->is_dpk_pwr_on) {\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] Skip DPK due to DPD PWR off !!\\n\");\n\t\treturn;\n\t} else if (!(*dm->mp_mode) && dpk_reload_8822c(dm))\n\t\treturn;\n\n\tRF_DBG(dm, DBG_RF_DPK,\n\t       \"[DPK] ****** DPK Start (Ver: %s), Cut: %d ******\\n\",\n\t       DPK_VER_8822C, dm->cut_version);\n\n\t_dpk_information_8822c(dm);\n\n\t_backup_mac_bb_registers_8822c(dm, bb_reg, bb_reg_backup,\n\t\t\t\t       DPK_BB_REG_NUM_8822C);\n\n\t_backup_rf_registers_8822c(dm, rf_reg, rf_reg_backup);\n\n\t_dpk_mac_bb_setting_8822c(dm);\n\t_dpk_afe_setting_8822c(dm, true);\n\t_dpk_manual_txagc_8822c(dm, true);\n\t_dpk_pre_setting_8822c(dm);\n\n\t_dpk_result_reset_8822c(dm);\n\t_dpk_path_select_8822c(dm);\n\t_dpk_result_summary_8822c(dm);\n\n\t_dpk_manual_txagc_8822c(dm, false);\n\t_dpk_afe_setting_8822c(dm, false);\n\n\tdpk_enable_disable_8822c(dm);\n\n\t_reload_rf_registers_8822c(dm, rf_reg, rf_reg_backup);\n\n\thalrf_rxbb_dc_cal_8822c(dm); /*DCK for Rx*/\n\n\t_reload_mac_bb_registers_8822c(dm, bb_reg, bb_reg_backup,\n\t\t\t\t       DPK_BB_REG_NUM_8822C);\n}\n\nvoid dpk_enable_disable_8822c(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc); /*subpage 2*/\n\n\todm_set_bb_reg(dm, R_0x1b08, BIT(31), dpk_info->is_dpk_pwr_on);\n\todm_set_bb_reg(dm, R_0x1b60, BIT(31), dpk_info->is_dpk_pwr_on);\n\n\tif (dpk_info->is_dpk_enable) {\n\t\tif (dpk_info->dpk_path_ok & BIT(0)) {\n\t\t\todm_set_bb_reg(dm, R_0x1b08, BIT(15) | BIT(14), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0x1b04, 0x0fffffff,\n\t\t\t\t       dpk_info->dpk_gs[RF_PATH_A]);\n\t\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] S0 DPK enable !!!\\n\");\n\t\t}\n\t\tif ((dpk_info->dpk_path_ok & BIT(1)) >> 1) {\n\t\t\todm_set_bb_reg(dm, R_0x1b60, BIT(15) | BIT(14), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0x1b5c, 0x0fffffff,\n\t\t\t\t       dpk_info->dpk_gs[RF_PATH_B]);\n\t\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] S1 DPK enable !!!\\n\");\n\t\t}\n\t} else {\n\t\tif (dpk_info->dpk_path_ok & BIT(0)) {\n\t\t\todm_set_bb_reg(dm, R_0x1b08, BIT(15) | BIT(14), 0x3);\n\t\t\todm_set_bb_reg(dm, R_0x1b04, 0x0fffffff,0x5b);\n\t\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] S0 DPK bypass !!!\\n\");\n\t\t}\n\t\tif ((dpk_info->dpk_path_ok & BIT(1)) >> 1) {\n\t\t\todm_set_bb_reg(dm, R_0x1b60, BIT(15) | BIT(14), 0x3);\n\t\t\todm_set_bb_reg(dm, R_0x1b5c, 0x0fffffff,0x5b);\n\t\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK] S1 DPK bypass !!!\\n\");\n\t\t}\n\t}\n}\n\nvoid dpk_track_8822c(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tu8 is_increase, i = 0, k = 0, path;\n\tu8 thermal_dpk_avg_count = 0, thermal_value[2] = {0};\n\tu32 thermal_dpk_avg[2] = {0};\n\ts8 offset[2], delta_dpk[2];\n\n\tif ((dpk_info->thermal_dpk[0] == 0) && (dpk_info->thermal_dpk[1] == 0)) {\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[DPK_track] Bypass DPK tracking!!!!\\n\");\n\t\t\treturn;\n\t} else\n\t\tRF_DBG(dm, DBG_RF_DPK | DBG_RF_TX_PWR_TRACK,\n\t\t       \"[DPK_track] =======================================\\n\");\n\n\t/*get thermal meter*/\n\tfor (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {\n\t\tthermal_value[path] = _dpk_thermal_read_8822c(dm, path);\n\n\t\tRF_DBG(dm, DBG_RF_DPK | DBG_RF_TX_PWR_TRACK,\n\t\t       \"[DPK_track] S%d thermal now = %d\\n\", path, thermal_value[path]);\n\t}\n\n\tdpk_info->thermal_dpk_avg[0][dpk_info->thermal_dpk_avg_index] =\n\t\tthermal_value[0];\n\tdpk_info->thermal_dpk_avg[1][dpk_info->thermal_dpk_avg_index] =\n\t\tthermal_value[1];\n\tdpk_info->thermal_dpk_avg_index++;\n\n\t/*Average times */\n\tif (dpk_info->thermal_dpk_avg_index == THERMAL_DPK_AVG_NUM)\n\t\tdpk_info->thermal_dpk_avg_index = 0;\n\n\tfor (i = 0; i < THERMAL_DPK_AVG_NUM; i++) {\n\t\tif (dpk_info->thermal_dpk_avg[0][i] ||\n\t\t    dpk_info->thermal_dpk_avg[1][i]) {\n\t\t\tthermal_dpk_avg[0] += dpk_info->thermal_dpk_avg[0][i];\n\t\t\tthermal_dpk_avg[1] += dpk_info->thermal_dpk_avg[1][i];\n\t\t\tthermal_dpk_avg_count++;\n\t\t}\n\t}\n\n\t/*Calculate Average ThermalValue after average enough times*/\n\tif (thermal_dpk_avg_count) {\n#if 0\n\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t       \"[DPK_track] S0 ThermalValue_DPK_AVG (count) = %d (%d))\\n\",\n\t\t       thermal_dpk_avg[0], thermal_dpk_avg_count);\n\n\t\tRF_DBG(dm, DBG_RF_DPK,\n\t\t       \"[DPK_track] S1 ThermalValue_DPK_AVG (count) = %d (%d))\\n\",\n\t\t       thermal_dpk_avg[1], thermal_dpk_avg_count);\n#endif\n\t\tthermal_value[0] = (u8)(thermal_dpk_avg[0] / thermal_dpk_avg_count);\n\t\tthermal_value[1] = (u8)(thermal_dpk_avg[1] / thermal_dpk_avg_count);\n\n\t\tRF_DBG(dm, DBG_RF_DPK | DBG_RF_TX_PWR_TRACK,\n\t\t       \"[DPK_track] S0 thermal avg = %d (DPK @ %d)\\n\",\n\t\t       thermal_value[0], dpk_info->thermal_dpk[0]);\n\n\t\tRF_DBG(dm, DBG_RF_DPK | DBG_RF_TX_PWR_TRACK,\n\t\t       \"[DPK_track] S1 thermal avg = %d (DPK @ %d)\\n\",\n\t\t       thermal_value[1], dpk_info->thermal_dpk[1]);\n\t}\n\n\tfor (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {\n\t\tdelta_dpk[path] = dpk_info->thermal_dpk[path] - thermal_value[path];\n\n\t\toffset[path] = (delta_dpk[path] - dpk_info->thermal_dpk_delta[path]) & 0x7f;\n\n\tRF_DBG(dm, DBG_RF_DPK | DBG_RF_TX_PWR_TRACK,\n\t\t       \"[DPK_track] S%d thermal_diff= %d, cal_diff= %d, offset= %d\\n\",\n\t\t       path, delta_dpk[path], dpk_info->thermal_dpk_delta[path],\n\t\t       offset[path] > 64 ? offset[path] - 128 : offset[path]);\n\t}\n\n\tif (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||\n\t\trf->is_tssi_in_progress)\n\t\treturn;\n\n\tfor (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {\n\t\tif (offset[path] != dpk_info->pre_pwsf[path]) {\n\t\t\todm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0x8 | (path << 1));\n\t\t\todm_set_bb_reg(dm, R_0x1b58, 0x0000007f, offset[path]);\n\t\t\tdpk_info->pre_pwsf[path] = offset[path];\n\t\t\tRF_DBG(dm, DBG_RF_DPK | DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"[DPK_track] S%d new pwsf is 0x%x, 0x1b58=0x%x\\n\",\n\t\t\t       path, dpk_info->pre_pwsf[path],\n\t\t\t       odm_get_bb_reg(dm, R_0x1b58, MASKDWORD));\n\t\t} else\n\t\t\tRF_DBG(dm, DBG_RF_DPK | DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"[DPK_track] S%d pwsf unchanged (0x%x)\\n\",\n\t\t\t       path, dpk_info->pre_pwsf[path]);\n\t}\n}\n\nvoid dpk_info_rsvd_page_8822c(\n\tvoid *dm_void,\n\tu8 *buf,\n\tu32 *buf_size)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tif (buf) {\n\t\todm_move_memory(dm, buf, &(dpk_info->dpk_path_ok), 2);\n\t\todm_move_memory(dm, buf + 2, dpk_info->dpk_txagc, 2);\n\t\todm_move_memory(dm, buf + 4, dpk_info->dpk_gs, 4);\n\t\todm_move_memory(dm, buf + 8, dpk_info->coef, 160);\n\t\todm_move_memory(dm, buf + 168, &(dpk_info->dpk_ch), 1);\n\t}\n\n\tif (buf_size)\n\t\t*buf_size = DPK_INFO_RSVD_LEN_8822C;\n}\n\n#endif\n"
  },
  {
    "path": "hal/phydm/halrf/rtl8822c/halrf_dpk_8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALRF_DPK_8822C_H__\n#define __HALRF_DPK_8822C_H__\n\n#if (RTL8822C_SUPPORT == 1)\n/*--------------------------Define Parameters-------------------------------*/\n#define DPK_RF_PATH_NUM_8822C 2\n#define DPK_GROUP_NUM_8822C 1\n#define DPK_MAC_REG_NUM_8822C 2\n#define DPK_BB_REG_NUM_8822C 18\n#define DPK_RF_REG_NUM_8822C 7\n#define DPK_PAS_CHK_DBG_8822C 0\n#define DPK_COEF_DBG_8822C 0\n#define DPK_PAS_DBG_8822C 0\n#define DPK_SRAM_IQ_DBG_8822C 0\n#define DPK_SRAM_read_DBG_8822C 0\n#define DPK_SRAM_write_DBG_8822C 0\n#define DPK_PATH_A_8822C 1\n#define DPK_PATH_B_8822C 1\n#define DPK_THRESHOLD_8822C 6\n#define DPK_INFO_RSVD_LEN_8822C 169\n/*---------------------------End Define Parameters----------------------------*/\n\nvoid btc_set_gnt_wl_bt_8822c(\n\tvoid *dm_void,\n\tboolean is_before_k);\n\nvoid dpk_coef_read_8822c(\n\tvoid *dm_void);\n\nvoid dpk_enable_disable_8822c(\n\tvoid *dm_void);\n\nu8 dpk_reload_8822c(\n\tvoid *dm_void);\n\nvoid do_dpk_8822c(\n\tvoid *dm_void);\n\nvoid dpk_track_8822c(\n\tvoid *dm_void);\n\nvoid dpk_info_rsvd_page_8822c(\n\tvoid *dm_void,\n\tu8 *buf,\n\tu32 *buf_size);\n\n#endif /* RTL8822C_SUPPORT */\n\n#endif /*#ifndef __HALRF_DPK_8822C_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/rtl8822c/halrf_iqk_8822c.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#include \"mp_precomp.h\"\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#if RT_PLATFORM == PLATFORM_MACOSX\n#include \"phydm_precomp.h\"\n#else\n#include \"../phydm_precomp.h\"\n#endif\n#else\n#include \"../../phydm_precomp.h\"\n#endif\n\n#if (RTL8822C_SUPPORT == 1)\n\n#if 1\nboolean\n_iqk_check_cal_8822c(\n\tstruct dm_struct *dm,\n\tu8 path,\n\tu8 cmd)\n{\n\tboolean notready = true, fail = true;\n\tu32 delay_count = 0x0;\n\n\twhile (notready) {\n\t\tif (odm_read_1byte(dm, 0x2d9c) == 0x55) {\n\t\t\tif (cmd == 0x0) /*LOK*/\n\t\t\t\tfail = false;\n\t\t\telse\n\t\t\t\tfail = (boolean)odm_get_bb_reg(dm, R_0x1b08, BIT(26));\n\t\t\tnotready = false;\n\t\t} else {\n\t\t\tODM_delay_us(10);\n\t\t\tdelay_count++;\n\t\t}\n\n\t\tif (delay_count >= 30000) {\n\t\t\tfail = true;\n\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]IQK timeout!!!\\n\");\n\t\t\tbreak;\n\t\t}\n\t}\n\todm_write_1byte(dm, 0x1b10, 0x0);\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]delay count = 0x%x!!!\\n\", delay_count);\n\t//return fail;\t\n\treturn false;\n}\n\nvoid _iqk_idft(struct dm_struct *dm)\n{\n\n\todm_write_4byte(dm, 0x1b00, 0x8);\n\todm_write_4byte(dm, 0x1bd8, 0xe0000001);\n\todm_write_4byte(dm, 0x1b00, 0x00000e18);\n\todm_write_4byte(dm, 0x1b00, 0x00000e19);\n\t_iqk_check_cal_8822c(dm, RF_PATH_A, 0x0);\n\todm_write_4byte(dm, 0x1b00, 0xa);\n\todm_write_4byte(dm, 0x1bd8, 0xe0000001);\n\todm_write_4byte(dm, 0x1b00, 0x00000e2a);\n\todm_write_4byte(dm, 0x1b00, 0x00000e2b);\n\t_iqk_check_cal_8822c(dm, RF_PATH_B, 0x0);\n\n\todm_write_4byte(dm, 0x1b00, 0x8);\n\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);\t\n\todm_write_4byte(dm, 0x1b00, 0xa);\n\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);\t\n}\n\nvoid _iqk_rx_cfir_check_8822c(struct dm_struct *dm, u8 t)\n{\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tu8 j;\n\n\tfor (j = 0; j <= 16; j++) {\n\t\tif (iqk_info->rx_cfir_real[0][0][j] != iqk_info->rx_cfir_real[1][0][j] ||\n\t\tiqk_info->rx_cfir_imag[0][0][j] != iqk_info->rx_cfir_imag[1][0][j]) {\n\t\t\tif (t == 0) {\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[ABC]bypass pathA RXCFIR\\n\");\n\t\t\t\todm_set_bb_reg(dm, 0x180c, BIT(31), 0x0);\n\t\t\t} else {\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[ABC]pathA RX CFIR is changed\\n\");\n\t\t\t}\n\t\t\tbreak;\n\t\t\t\n\t\t}\n\n\t\tif (iqk_info->rx_cfir_real[0][1][j] != iqk_info->rx_cfir_real[1][1][j] ||\n\t\tiqk_info->rx_cfir_imag[0][1][j] != iqk_info->rx_cfir_imag[1][1][j]) {\n\t\t\tif (t ==0) {\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[ABC]bypass pathB RXCFIR\\n\");\n\t\t\t\todm_set_bb_reg(dm, 0x410c, BIT(31), 0x0);\n\t\t\t} else {\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[ABC]pathB RX CFIR is changed\\n\");\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\n\nvoid _iqk_get_rxcfir_8822c(void *dm_void, u8 path, u8 t)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tu8 i;\n\tu32 tmp;\n\tu32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);\n\n\n\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n\n//\tfor (i = 0; i <  0x100/4; i++)\n//\t\tRF_DBG(dm, DBG_RF_DPK, \"[CC] (1) 1b%x = 0x%x\\n\",\n//\t\t       i*4, odm_read_4byte(dm, (0x1b00 + i*4)));\n\n\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);\t\t\n\n\todm_set_bb_reg(dm, R_0x1bd4, BIT(21), 0x1);\n\todm_set_bb_reg(dm, R_0x1bd4, bit_mask_20_16, 0x10);\n\tfor (i = 0; i <= 16; i++) {\n\t\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001 | i << 2);\n\t\ttmp = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);\n\t\tiqk_info->rx_cfir_real[t][path][i] = (tmp & 0x0fff0000) >> 16;\n\t\tiqk_info->rx_cfir_imag[t][path][i] = tmp & 0x0fff;\t\t\n\t}\n//\tfor (i = 0; i <= 16; i++)\n//\t\tRF_DBG(dm, DBG_RF_IQK, \"[CC](7) rx_cfir_real[%d][%d][%x] = %2x\\n\", t, path, i, iqk_info->rx_cfir_real[t][path][i]);\t\t\n//\tfor (i = 0; i <= 16; i++)\n//\t\tRF_DBG(dm, DBG_RF_IQK, \"[CC](7) rx_cfir_imag[%d][%d][%x] = %2x\\n\", t, path, i, iqk_info->rx_cfir_imag[t][path][i]); \n\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);\n//\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);\n}\n\nvoid _iqk_reload_rxcfir_8822c(struct dm_struct *dm, u8 path)\n{\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n#if 1\n\tu8 i;\n\tu32 tmp = 0x0, tmp1 = 0x0, tmp2 =0x0;\n\n\todm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0x8 | path << 1);\n//\todm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7);\n//\todm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x40000000);\n//\todm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x40000000);\n//\todm_write_1byte(dm, 0x1bcc, 0x0);\n\todm_set_bb_reg(dm, 0x1b20, BIT(31) | BIT(30), 0x1);\n\ttmp1 = 0x60000001;\n//\todm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x60012303);\n//\todm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x60045601);\n\tODM_delay_us(10);\n#if 1\n\tfor (i = 0; i <= 16; i++) {\n\t\ttmp2 = tmp1 | iqk_info->rx_cfir_real[0][path][i]<< 8;\n\t\ttmp2 = (tmp2 | i << 2) + 2;\n\t\todm_set_bb_reg(dm, 0x1bd8, MASKDWORD, tmp2);\n\t\tODM_delay_us(10);\n\t\todm_set_bb_reg(dm, 0x1bd8, BIT(30), 0x0);\n//\t\todm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0xe0000001);\n\t}\n\tfor (i = 0; i <= 16; i++) {\n\t\ttmp2 = tmp1 | iqk_info->rx_cfir_imag[0][path][i]<< 8;\n\t\ttmp2 = (tmp2 | i << 2);\n\t\todm_set_bb_reg(dm, 0x1bd8, MASKDWORD, tmp2);\t\t\n\t\tODM_delay_us(10);\n\t\todm_set_bb_reg(dm, 0x1bd8, BIT(30), 0x0);\n//\t\todm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0xe0000001);\n\t}\n#endif\t\n\t// end for write CFIR SRAM\n\todm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0xe0000001);\n\tODM_delay_ms(10);\n//\todm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0xe0000000);\n//\tODM_delay_ms(10);\n\todm_set_bb_reg(dm, 0x1b20, BIT(31) | BIT(30), 0x0);\n//\tODM_delay_ms(10);\n//\todm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x0);\n#endif\n}\n\nvoid _iqk_rx_cfir_8822c(struct dm_struct *dm, u8 path)\n{\n\n\tu32 xym_tmp[6], cfir_tmp[3];\n\tu32 i;\n\n\todm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | path << 1);\n\todm_set_bb_reg(dm, 0x1b20, 0xff000000, 0x41);\n\todm_set_bb_reg(dm, 0x1bd8, 0xffffffff, 0xe0000001);\n\todm_set_bb_reg(dm, 0x1bd4, 0xffffffff, 0x00300001);\n\n\todm_set_bb_reg(dm, 0x1bd8, 0xff, 0x01);\n\tcfir_tmp[0] = odm_get_bb_reg(dm, 0x1bfc, 0xffffffff);\n\todm_set_bb_reg(dm, 0x1bd8, 0xff, 0x05);\n\tcfir_tmp[1] = odm_get_bb_reg(dm, 0x1bfc, 0xffffffff);\n\todm_set_bb_reg(dm, 0x1bd8, 0xff, 0x09);\n\tcfir_tmp[2] = odm_get_bb_reg(dm, 0x1bfc, 0xffffffff);\n\n\todm_set_bb_reg(dm, 0x1b20, 0xff000000, 0x05);\n//\todm_set_bb_reg(dm, 0x1bd8, 0xff, 0x00);\n\n\tRF_DBG(dm, DBG_RF_IQK, \"[CC] S%d RX CFIR = 0x%x, 0x%x, 0x%x\\n\",\n\t\tpath, cfir_tmp[0], cfir_tmp[1], cfir_tmp[2]);\n}\n\nvoid _iqk_tx_cfir_8822c(struct dm_struct *dm, u8 path)\n{\n\tu32 xym_tmp[6], cfir_tmp[3];\n\tu32 i;\n\n\todm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | path << 1);\n\todm_set_bb_reg(dm, 0x1b20, 0xff000000, 0xc1);\n\todm_set_bb_reg(dm, 0x1bd8, 0xffffffff, 0xe0000001);\n\todm_set_bb_reg(dm, 0x1bd4, 0xffffffff, 0x00300001);\n\n\todm_set_bb_reg(dm, 0x1bd8, 0xff, 0x01);\n\tcfir_tmp[0] = odm_get_bb_reg(dm, 0x1bfc, 0xffffffff);\n\todm_set_bb_reg(dm, 0x1bd8, 0xff, 0x05);\n\tcfir_tmp[1] = odm_get_bb_reg(dm, 0x1bfc, 0xffffffff);\n\todm_set_bb_reg(dm, 0x1bd8, 0xff, 0x09);\n\tcfir_tmp[2] = odm_get_bb_reg(dm, 0x1bfc, 0xffffffff);\n\n\todm_set_bb_reg(dm, 0x1b20, 0xff000000, 0x05);\n//\todm_set_bb_reg(dm, 0x1bd8, 0xff, 0x00);\n\n\tRF_DBG(dm, DBG_RF_IQK, \"[CC] TX CFIR = 0x%x, 0x%x, 0x%x\\n\",\n\t\tcfir_tmp[0], cfir_tmp[1], cfir_tmp[2]);\n}\n\n#endif\n\nu8 _iqk_get_efuse_thermal_8822c(\n\tstruct dm_struct *dm,\n\tu8 path)\n{\n\tu32 thermal_tmp;\n\tu8 eeprom_thermal;\n\n\tif (path == RF_PATH_A) /*path s0*/\n\t\todm_efuse_logical_map_read(dm, 1, 0xd0, &thermal_tmp);\n\telse /*path s1*/\n\t\todm_efuse_logical_map_read(dm, 1, 0xd1, &thermal_tmp);\n\teeprom_thermal = (u8)thermal_tmp;\n\n\treturn eeprom_thermal;\n}\n\n\n/*---------------------------Define Local Constant---------------------------*/\nvoid phydm_get_read_counter_8822c(struct dm_struct *dm)\n{\n\tu32 counter = 0x0;\n\n\twhile (1) {\n\t\tif ((odm_get_rf_reg(dm, RF_PATH_A, RF_0x8, RFREGOFFSETMASK) == 0xabcde) || counter > 300)\n\t\t\tbreak;\n\t\tcounter++;\n\t\tODM_delay_us(10);\n\t};\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x8, RFREGOFFSETMASK, 0x0);\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]counter = %d\\n\", counter);\n}\n\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\nvoid do_iqk_8822c(\n\tvoid *dm_void,\n\tu8 delta_thermal_index,\n\tu8 thermal_value,\n\tu8 threshold)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tdm->rf_calibrate_info.thermal_value_iqk = thermal_value;\n\thalrf_segment_iqk_trigger(dm, true, false);\n}\n#else\n/*Originally config->do_iqk is hooked phy_iq_calibrate_8822C, but do_iqk_8822C and phy_iq_calibrate_8822C have different arguments*/\nvoid do_iqk_8822c(\n\tvoid *dm_void,\n\tu8 delta_thermal_index,\n\tu8 thermal_value,\n\tu8 threshold)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tboolean is_recovery = (boolean)delta_thermal_index;\n\n\thalrf_segment_iqk_trigger(dm, true, false);\n}\n#endif\n\nvoid iqk_info_rsvd_page_8822c(\n\tvoid *dm_void,\n\tu8 *buf,\n\tu32 *buf_size)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk = &dm->IQK_info;\n\tu32 i = 0;\n\t\n\tif (buf) {\n\t\todm_move_memory(dm, buf, iqk->iqk_channel,\n\t\t\t\tsizeof(iqk->iqk_channel));\n\t\ti += sizeof(iqk->iqk_channel);\n\t\todm_move_memory(dm, buf + i, &iqk->iqk_cfir_real[0][0],\n\t\t\t\tsizeof(iqk->iqk_cfir_real[0][0]));\n\t\ti += sizeof(iqk->iqk_cfir_real[0][0]);\n\t\todm_move_memory(dm, buf + i, &iqk->iqk_cfir_real[0][1],\n\t\t\t\tsizeof(iqk->iqk_cfir_real[0][1]));\n\t\ti += sizeof(iqk->iqk_cfir_real[0][1]);\n\t\todm_move_memory(dm, buf + i, &iqk->iqk_cfir_real[1][0],\n\t\t\t\tsizeof(iqk->iqk_cfir_real[1][0]));\n\t\ti += sizeof(iqk->iqk_cfir_real[1][0]);\n\t\todm_move_memory(dm, buf + i, &iqk->iqk_cfir_real[1][1],\n\t\t\t\tsizeof(iqk->iqk_cfir_real[1][1]));\n\t\ti += sizeof(iqk->iqk_cfir_real[1][1]);\n\t\todm_move_memory(dm, buf + i, &iqk->iqk_cfir_imag[0][0],\n\t\t\t\tsizeof(iqk->iqk_cfir_imag[0][0]));\n\t\ti += sizeof(iqk->iqk_cfir_imag[0][0]);\n\t\todm_move_memory(dm, buf + i, &iqk->iqk_cfir_imag[0][1],\n\t\t\t\tsizeof(iqk->iqk_cfir_imag[0][1]));\n\t\ti += sizeof(iqk->iqk_cfir_imag[0][1]);\n\t\todm_move_memory(dm, buf + i, &iqk->iqk_cfir_imag[1][0],\n\t\t\t\tsizeof(iqk->iqk_cfir_imag[1][0]));\n\t\ti += sizeof(iqk->iqk_cfir_imag[1][0]);\n\t\todm_move_memory(dm, buf + i, &iqk->iqk_cfir_imag[1][1],\n\t\t\t\tsizeof(iqk->iqk_cfir_imag[1][1]));\n\t\ti += sizeof(iqk->iqk_cfir_imag[1][1]);\n\t\todm_move_memory(dm, buf + i, &iqk->lok_idac[0][0],\n\t\t\t\tsizeof(iqk->lok_idac[0][0]));\n\t\ti += sizeof(iqk->lok_idac[0][0]);\n\t\todm_move_memory(dm, buf + i, &iqk->lok_idac[0][1],\n\t\t\t\tsizeof(iqk->lok_idac[0][1]));\n\t\ti += sizeof(iqk->lok_idac[0][1]);\n\t\todm_move_memory(dm, buf + i, &iqk->lok_idac[1][0],\n\t\t\t\tsizeof(iqk->lok_idac[1][0]));\n\t\ti += sizeof(iqk->lok_idac[1][0]);\n\t\todm_move_memory(dm, buf + i, &iqk->lok_idac[1][1],\n\t\t\t\tsizeof(iqk->lok_idac[1][1]));\n\t\ti += sizeof(iqk->lok_idac[1][1]);\n\t}\n\n\tif (buf_size)\n\t\t*buf_size = IQK_INFO_RSVD_LEN_8822C;\n}\n\nboolean _iqk_xym_read_8822c(struct dm_struct *dm, u8 path)\n{\n\tu32 i = 0x0;\n\tu32 xym = 0x0;\n\tboolean kfail = false;\n\tu32 xvalue = 0x0;\n\tu32 yvalue = 0x0;\n\tu8 x_thr = 100, y_thr = 100;\n\n\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\t\n\todm_set_bb_reg(dm, 0x1b1c, BIT(1) | BIT(0), 0x2);\n\n\tfor (i = 0x0; i < 24; i++ ) {\n\t\todm_set_bb_reg(dm, 0x1b14, MASKDWORD, 0x000000e0 + i);\n\t\todm_set_bb_reg(dm, 0x1b14, MASKDWORD, 0x0);\n\t\txym = odm_get_bb_reg(dm, 0x1b38, MASKDWORD);\n\t\txvalue = odm_get_bb_reg(dm, 0x1b38, 0xfff00000);\t\t\n\t\tyvalue = odm_get_bb_reg(dm, 0x1b38, 0x000fff00);\t\t\n\n\t\tif (xvalue < 0x400) {// \"- vale\n\t\t\tif ((0x400 - xvalue) > x_thr)\n\t\t\t\tkfail = true;\t\t\t\t\n\t\t} else { //\"+\" vale\n\t\t\tif ((xvalue - 0x400) > x_thr)\n\t\t\t\tkfail = true;\t\t\t\n\t\t}\n\n\t\tif (yvalue > 0x800) { // \"- vale\n\t\t\tif ((0xfff - yvalue) > y_thr)\n\t\t\t\tkfail = true;\t\t\t\n\t\t} else { // \"+\" vale\n\t\t\tif (yvalue > y_thr)\n\t\t\t\tkfail = true;\n\t\t}\n\t\t\n\t\tif (kfail == true) {\n\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S%d XYM > thr happen\\n\", path);\n\t\t\tbreak;\n\t\t}\n\t\t\n\t}\n\todm_set_bb_reg(dm, 0x1b38, MASKDWORD, 0x40000000);\n\treturn kfail;\n}\n\n\nstatic u32\n_iqk_btc_wait_indirect_reg_ready_8822c(struct dm_struct *dm)\n{\n\tu32 delay_count = 0;\n\t\n\t/* wait for ready bit before access 0x1700 */\n\twhile (1) {\n\t\tif ((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) {\n\t\t\tdelay_ms(10);\n\t\t\tif (++delay_count >= 10)\n\t\t\tbreak;\n\t\t} else {\n\t\t\tbreak;\n\t\t}\n\t}\n\t\n\treturn delay_count;\n}\n\nstatic u32\n_iqk_btc_read_indirect_reg_8822c(struct dm_struct *dm, u16 reg_addr)\n{\n\tu32 delay_count = 0;\n\n\t/* wait for ready bit before access 0x1700 */\n\t_iqk_btc_wait_indirect_reg_ready_8822c(dm);\n\n\todm_write_4byte(dm, 0x1700, 0x800F0000 | reg_addr);\n\n\treturn odm_read_4byte(dm, 0x1708); /* get read data */\n}\n\nstatic void\n_iqk_btc_write_indirect_reg_8822c(struct dm_struct *dm, u16 reg_addr,\n\t\t       u32 bit_mask, u32 reg_value)\n{\n\tu32 val, i = 0, bitpos = 0, delay_count = 0;\n\n\tif (bit_mask == 0x0)\n\t\treturn;\n\n\tif (bit_mask == 0xffffffff) {\n\t/* wait for ready bit before access 0x1700 */\n\t_iqk_btc_wait_indirect_reg_ready_8822c(dm);\n\n\t/* put write data */\n\todm_write_4byte(dm, 0x1704, reg_value);\n\n\todm_write_4byte(dm, 0x1700, 0xc00F0000 | reg_addr);\n\t} else {\n\t\tfor (i = 0; i <= 31; i++) {\n\t\t\tif (((bit_mask >> i) & 0x1) == 0x1) {\n\t\t\t\tbitpos = i;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\t/* read back register value before write */\n\t\tval = _iqk_btc_read_indirect_reg_8822c(dm, reg_addr);\n\t\tval = (val & (~bit_mask)) | (reg_value << bitpos);\n\n\t\t/* wait for ready bit before access 0x1700 */\n\t\t_iqk_btc_wait_indirect_reg_ready_8822c(dm);\n\n\t\todm_write_4byte(dm, 0x1704, val); /* put write data */\n\t\todm_write_4byte(dm, 0x1700, 0xc00F0000 | reg_addr);\n\t}\n}\n\nvoid _iqk_set_gnt_wl_high_8822c(struct dm_struct *dm)\n{\n\tu32 val = 0;\n\tu8 state = 0x1;\n\n\t/*GNT_WL = 1*/\n\tval = (state << 1) | 0x1;\n\t_iqk_btc_write_indirect_reg_8822c(dm, 0x38, 0x3000, val); /*0x38[13:12]*/\n\t_iqk_btc_write_indirect_reg_8822c(dm, 0x38, 0x0300, val); /*0x38[9:8]*/\n}\n\nvoid _iqk_set_gnt_bt_low_8822c(struct dm_struct *dm)\n{\n\tu32 val = 0;\n\tu8 state = 0x0, sw_control = 0x1;\n\n\t/*GNT_BT = 0*/\n\tval = (sw_control) ? ((state << 1) | 0x1) : 0;\n\t_iqk_btc_write_indirect_reg_8822c(dm, 0x38, 0xc000, val); /*0x38[15:14]*/\n\t_iqk_btc_write_indirect_reg_8822c(dm, 0x38, 0x0c00, val); /*0x38[11:10]*/\n}\n\nvoid _iqk_set_gnt_wl_gnt_bt_8822c(struct dm_struct *dm, boolean beforeK)\n{\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tif (beforeK) {\n\t\t_iqk_set_gnt_wl_high_8822c(dm);\n\t\t_iqk_set_gnt_bt_low_8822c(dm);\n\t} else {\n\t\t_iqk_btc_write_indirect_reg_8822c(dm, 0x38, MASKDWORD, iqk_info->tmp_gntwl);\n\t}\n}\n\n\n\nvoid _iqk_nctl_8822c(struct dm_struct *dm)\n{\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]==========IQK NCTL!!!!!========\\n\");\n\t//odm_write_4byte(dm 0x1CD0, 0x7 [31:28]);\t\n\todm_set_bb_reg(dm, 0x1cd0, 0xf0000000, 0x7);\n\t//====== Subpage 0 Init_Setting ======================= //\n\todm_write_4byte(dm, 0x1b00, 0x00000008);\n\todm_write_4byte(dm, 0x1b00, 0x00D70008);\n\todm_write_4byte(dm, 0x1b00, 0x00150008);\n\todm_write_4byte(dm, 0x1b00, 0x00000008);\n\n\todm_write_4byte(dm, 0x1b04, 0xE2462952);\n\todm_write_4byte(dm, 0x1b08, 0x00000080);\n\todm_write_4byte(dm, 0x1b0c, 0x00000000);\n\todm_write_4byte(dm, 0x1b10, 0x00011800);\n\todm_write_4byte(dm, 0x1b14, 0x00000000);\n\todm_write_4byte(dm, 0x1b18, 0x00292903);\n\todm_write_4byte(dm, 0x1b1c, 0xA2193C32);\n\todm_write_4byte(dm, 0x1b20, 0x03040008);\n\todm_write_4byte(dm, 0x1b24, 0x00060008);\n\todm_write_4byte(dm, 0x1b28, 0x00060300);\n\todm_write_4byte(dm, 0x1b2C, 0x00180018);\n\todm_write_4byte(dm, 0x1b30, 0x40000000);\n\todm_write_4byte(dm, 0x1b34, 0x00000800);\n\todm_write_4byte(dm, 0x1b38, 0x40000000 );\n\todm_write_4byte(dm, 0x1b3C, 0x40000000 );\n\t// TxGainGapK\n\todm_write_4byte(dm, 0x1b98, 0x00000000);\n\todm_write_4byte(dm, 0x1b9c, 0x00000000);\n\todm_write_4byte(dm, 0x1bc0, 0x01000000);\n\todm_write_4byte(dm, 0x1bcc, 0x00000000);\n\t//odm_write_4byte(dm, 0x1be4, 0x0 [1:0]);\t\n\todm_set_bb_reg(dm, 0x1be4, BIT(1) | BIT(0), 0x0);\n\todm_write_4byte(dm, 0x1bec, 0x40000000);\n\t// ---------------------------------- DPD -------------------------- //\n\t//DPD associated settings\n\todm_write_4byte(dm, 0x1b40, 0x40000000);\n\todm_write_4byte(dm, 0x1b44, 0x20001064);\n\todm_write_4byte(dm, 0x1b48, 0x0005002D);\n\todm_write_4byte(dm, 0x1b4c, 0x00000000);\n\todm_write_4byte(dm, 0x1b54, 0x00009802);\n\todm_write_4byte(dm, 0x1b60, 0x1F150000);\n\todm_write_4byte(dm, 0x1b64, 0x19140000);\n\todm_write_4byte(dm, 0x1b58, 0x00008F00);\n\todm_write_4byte(dm, 0x1b5C, 0x00000000);\n\t//0dB amp\n\todm_write_4byte(dm, 0x1b4c, 0x00000000);\n\todm_write_4byte(dm, 0x1b4c, 0x008a0000);\n\todm_write_4byte(dm, 0x1b50, 0x000003BE);\n\todm_write_4byte(dm, 0x1b4c, 0x018a0000);\n\todm_write_4byte(dm, 0x1b50, 0x0000057A);\n\todm_write_4byte(dm, 0x1b4c, 0x028a0000);\n\todm_write_4byte(dm, 0x1b50, 0x000006C8);\n\todm_write_4byte(dm, 0x1b4c, 0x038a0000);\n\todm_write_4byte(dm, 0x1b50, 0x000007E0);\n\todm_write_4byte(dm, 0x1b4c, 0x048a0000);\n\todm_write_4byte(dm, 0x1b50, 0x000008D5);\n\todm_write_4byte(dm, 0x1b4c, 0x058a0000);\n\todm_write_4byte(dm, 0x1b50, 0x000009B2);\n\todm_write_4byte(dm, 0x1b4c, 0x068a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00000A7D);\n\todm_write_4byte(dm, 0x1b4c, 0x078a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00000B3A);\n\todm_write_4byte(dm, 0x1b4c, 0x088a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00000BEB);\n\todm_write_4byte(dm, 0x1b4c, 0x098a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00000C92);\n\todm_write_4byte(dm, 0x1b4c, 0x0A8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00000D31);\n\todm_write_4byte(dm, 0x1b4c, 0x0B8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00000DC9);\n\todm_write_4byte(dm, 0x1b4c, 0x0C8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00000E5A);\n\todm_write_4byte(dm, 0x1b4c, 0x0D8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00000EE6);\n\todm_write_4byte(dm, 0x1b4c, 0x0E8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00000F6D);\n\todm_write_4byte(dm, 0x1b4c, 0x0F8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00000FF0);\n\todm_write_4byte(dm, 0x1b4c, 0x108a0000);\n\todm_write_4byte(dm, 0x1b50, 0x0000106F);\n\todm_write_4byte(dm, 0x1b4c, 0x118a0000);\n\todm_write_4byte(dm, 0x1b50, 0x000010E9);\n\todm_write_4byte(dm, 0x1b4c, 0x128a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001161);\n\todm_write_4byte(dm, 0x1b4c, 0x138a0000);\n\todm_write_4byte(dm, 0x1b50, 0x000011D5);\n\todm_write_4byte(dm, 0x1b4c, 0x148a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001247);\n\todm_write_4byte(dm, 0x1b4c, 0x158a0000);\n\todm_write_4byte(dm, 0x1b50, 0x000012B5);\n\todm_write_4byte(dm, 0x1b4c, 0x168a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001322);\n\todm_write_4byte(dm, 0x1b4c, 0x178a0000);\n\todm_write_4byte(dm, 0x1b50, 0x0000138B);\n\todm_write_4byte(dm, 0x1b4c, 0x188a0000);\n\todm_write_4byte(dm, 0x1b50, 0x000013F3);\n\todm_write_4byte(dm, 0x1b4c, 0x198a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001459);\n\todm_write_4byte(dm, 0x1b4c, 0x1A8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x000014BD);\n\todm_write_4byte(dm, 0x1b4c, 0x1B8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x0000151E);\n\todm_write_4byte(dm, 0x1b4c, 0x1C8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x0000157F);\n\todm_write_4byte(dm, 0x1b4c, 0x1D8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x000015DD);\n\todm_write_4byte(dm, 0x1b4c, 0x1E8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x0000163A);\n\todm_write_4byte(dm, 0x1b4c, 0x1F8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001695);\n\todm_write_4byte(dm, 0x1b4c, 0x208a0000);\n\todm_write_4byte(dm, 0x1b50, 0x000016EF);\n\todm_write_4byte(dm, 0x1b4c, 0x218a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001748);\n\todm_write_4byte(dm, 0x1b4c, 0x228a0000);\n\todm_write_4byte(dm, 0x1b50, 0x0000179F);\n\todm_write_4byte(dm, 0x1b4c, 0x238a0000);\n\todm_write_4byte(dm, 0x1b50, 0x000017F5);\n\todm_write_4byte(dm, 0x1b4c, 0x248a0000);\n\todm_write_4byte(dm, 0x1b50, 0x0000184A);\n\todm_write_4byte(dm, 0x1b4c, 0x258a0000);\n\todm_write_4byte(dm, 0x1b50, 0x0000189E);\n\todm_write_4byte(dm, 0x1b4c, 0x268a0000);\n\todm_write_4byte(dm, 0x1b50, 0x000018F1);\n\todm_write_4byte(dm, 0x1b4c, 0x278a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001942);\n\todm_write_4byte(dm, 0x1b4c, 0x288a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001993);\n\todm_write_4byte(dm, 0x1b4c, 0x298a0000);\n\todm_write_4byte(dm, 0x1b50, 0x000019E2);\n\todm_write_4byte(dm, 0x1b4c, 0x2A8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001A31);\n\todm_write_4byte(dm, 0x1b4c, 0x2B8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001A7F);\n\todm_write_4byte(dm, 0x1b4c, 0x2C8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001ACC);\n\todm_write_4byte(dm, 0x1b4c, 0x2D8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001B18);\n\todm_write_4byte(dm, 0x1b4c, 0x2E8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001B63);\n\todm_write_4byte(dm, 0x1b4c, 0x2F8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001BAD);\n\todm_write_4byte(dm, 0x1b4c, 0x308a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001BF7);\n\todm_write_4byte(dm, 0x1b4c, 0x318a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001C40);\n\todm_write_4byte(dm, 0x1b4c, 0x328a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001C88);\n\todm_write_4byte(dm, 0x1b4c, 0x338a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001CCF);\n\todm_write_4byte(dm, 0x1b4c, 0x348a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001D16);\n\todm_write_4byte(dm, 0x1b4c, 0x358a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001D5C);\n\todm_write_4byte(dm, 0x1b4c, 0x368a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001DA2);\n\todm_write_4byte(dm, 0x1b4c, 0x378a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001DE6);\n\todm_write_4byte(dm, 0x1b4c, 0x388a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001E2B);\n\todm_write_4byte(dm, 0x1b4c, 0x398a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001E6E);\n\todm_write_4byte(dm, 0x1b4c, 0x3A8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001EB1);\n\todm_write_4byte(dm, 0x1b4c, 0x3B8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001EF4);\n\todm_write_4byte(dm, 0x1b4c, 0x3C8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001F35);\n\todm_write_4byte(dm, 0x1b4c, 0x3D8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001F77);\n\todm_write_4byte(dm, 0x1b4c, 0x3E8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001FB8);\n\todm_write_4byte(dm, 0x1b4c, 0x3F8a0000);\n\todm_write_4byte(dm, 0x1b50, 0x00001FF8);\n\todm_write_4byte(dm, 0x1b4c, 0x00000000);\n\todm_write_4byte(dm, 0x1b50, 0x00000000);\n\t// write pwsf table \n\todm_write_4byte(dm, 0x1b58, 0x00890000);\n\todm_write_4byte(dm, 0x1b5C, 0x3C6B3FFF);\n\todm_write_4byte(dm, 0x1b58, 0x02890000);\n\todm_write_4byte(dm, 0x1b5C, 0x35D9390A);\n\todm_write_4byte(dm, 0x1b58, 0x04890000);\n\todm_write_4byte(dm, 0x1b5C, 0x2FFE32D6);\n\todm_write_4byte(dm, 0x1b58, 0x06890000);\n\todm_write_4byte(dm, 0x1b5C, 0x2AC62D4F);\n\todm_write_4byte(dm, 0x1b58, 0x08890000);\n\todm_write_4byte(dm, 0x1b5C, 0x261F2862);\n\todm_write_4byte(dm, 0x1b58, 0x0A890000);\n\todm_write_4byte(dm, 0x1b5C, 0x21FA23FD);\n\todm_write_4byte(dm, 0x1b58, 0x0C890000);\n\todm_write_4byte(dm, 0x1b5C, 0x1E482013);\n\todm_write_4byte(dm, 0x1b58, 0x0E890000);\n\todm_write_4byte(dm, 0x1b5C, 0x1AFD1C96);\n\todm_write_4byte(dm, 0x1b58, 0x10890000);\n\todm_write_4byte(dm, 0x1b5C, 0x180E197B);\n\todm_write_4byte(dm, 0x1b58, 0x12890000);\n\todm_write_4byte(dm, 0x1b5C, 0x157016B5);\n\todm_write_4byte(dm, 0x1b58, 0x14890000);\n\todm_write_4byte(dm, 0x1b5C, 0x131B143D);\n\todm_write_4byte(dm, 0x1b58, 0x16890000);\n\todm_write_4byte(dm, 0x1b5C, 0x1107120A);\n\todm_write_4byte(dm, 0x1b58, 0x18890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0F2D1013);\n\todm_write_4byte(dm, 0x1b58, 0x1A890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0D870E54);\n\todm_write_4byte(dm, 0x1b58, 0x1C890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0C0E0CC5);\n\todm_write_4byte(dm, 0x1b58, 0x1E890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0ABF0B62);\n\todm_write_4byte(dm, 0x1b58, 0x20890000);\n\todm_write_4byte(dm, 0x1b5C, 0x09930A25);\n\todm_write_4byte(dm, 0x1b58, 0x22890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0889090A);\n\todm_write_4byte(dm, 0x1b58, 0x24890000);\n\todm_write_4byte(dm, 0x1b5C, 0x079B080F);\n\todm_write_4byte(dm, 0x1b58, 0x26890000);\n\todm_write_4byte(dm, 0x1b5C, 0x06C7072E);\n\todm_write_4byte(dm, 0x1b58, 0x28890000);\n\todm_write_4byte(dm, 0x1b5C, 0x060B0666);\n\todm_write_4byte(dm, 0x1b58, 0x2A890000);\n\todm_write_4byte(dm, 0x1b5C, 0x056305B4);\n\todm_write_4byte(dm, 0x1b58, 0x2C890000);\n\todm_write_4byte(dm, 0x1b5C, 0x04CD0515);\n\todm_write_4byte(dm, 0x1b58, 0x2E890000);\n\todm_write_4byte(dm, 0x1b5C, 0x04470488);\n\todm_write_4byte(dm, 0x1b58, 0x30890000);\n\todm_write_4byte(dm, 0x1b5C, 0x03D0040A);\n\todm_write_4byte(dm, 0x1b58, 0x32890000);\n\todm_write_4byte(dm, 0x1b5C, 0x03660399);\n\todm_write_4byte(dm, 0x1b58, 0x34890000);\n\todm_write_4byte(dm, 0x1b5C, 0x03070335);\n\todm_write_4byte(dm, 0x1b58, 0x36890000);\n\todm_write_4byte(dm, 0x1b5C, 0x02B302DC);\n\todm_write_4byte(dm, 0x1b58, 0x38890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0268028C);\n\todm_write_4byte(dm, 0x1b58, 0x3A890000);\n\todm_write_4byte(dm, 0x1b5C, 0x02250245);\n\todm_write_4byte(dm, 0x1b58, 0x3C890000);\n\todm_write_4byte(dm, 0x1b5C, 0x01E90206);\n\todm_write_4byte(dm, 0x1b58, 0x3E890000);\n\todm_write_4byte(dm, 0x1b5C, 0x01B401CE);\n\todm_write_4byte(dm, 0x1b58, 0x40890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0185019C);\n\todm_write_4byte(dm, 0x1b58, 0x42890000);\n\todm_write_4byte(dm, 0x1b5C, 0x015A016F);\n\todm_write_4byte(dm, 0x1b58, 0x44890000);\n\todm_write_4byte(dm, 0x1b5C, 0x01350147);\n\todm_write_4byte(dm, 0x1b58, 0x46890000);\n\todm_write_4byte(dm, 0x1b5C, 0x01130123);\n\todm_write_4byte(dm, 0x1b58, 0x48890000);\n\todm_write_4byte(dm, 0x1b5C, 0x00F50104);\n\todm_write_4byte(dm, 0x1b58, 0x4A890000);\n\todm_write_4byte(dm, 0x1b5C, 0x00DA00E7);\n\todm_write_4byte(dm, 0x1b58, 0x4C890000);\n\todm_write_4byte(dm, 0x1b5C, 0x00C300CE);\n\todm_write_4byte(dm, 0x1b58, 0x4E890000);\n\todm_write_4byte(dm, 0x1b5C, 0x00AE00B8);\n\todm_write_4byte(dm, 0x1b58, 0x50890000);\n\todm_write_4byte(dm, 0x1b5C, 0x009B00A4);\n\todm_write_4byte(dm, 0x1b58, 0x52890000);\n\todm_write_4byte(dm, 0x1b5C, 0x008A0092);\n\todm_write_4byte(dm, 0x1b58, 0x54890000);\n\todm_write_4byte(dm, 0x1b5C, 0x007B0082);\n\todm_write_4byte(dm, 0x1b58, 0x56890000);\n\todm_write_4byte(dm, 0x1b5C, 0x006E0074);\n\todm_write_4byte(dm, 0x1b58, 0x58890000);\n\todm_write_4byte(dm, 0x1b5C, 0x00620067);\n\todm_write_4byte(dm, 0x1b58, 0x5A890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0057005C);\n\todm_write_4byte(dm, 0x1b58, 0x5C890000);\n\todm_write_4byte(dm, 0x1b5C, 0x004E0052);\n\todm_write_4byte(dm, 0x1b58, 0x5E890000);\n\todm_write_4byte(dm, 0x1b5C, 0x00450049);\n\todm_write_4byte(dm, 0x1b58, 0x60890000);\n\todm_write_4byte(dm, 0x1b5C, 0x003E0041);\n\todm_write_4byte(dm, 0x1b58, 0x62890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0037003A);\n\todm_write_4byte(dm, 0x1b58, 0x62010000);\n\t// ======================= Subpage 1 Init_Setting ===============\n\todm_write_4byte(dm, 0x1b00, 0x0000000A);\n\t// --------------------------- WIQK --------------------------- //\n\todm_write_4byte(dm, 0x1b00, 0x00D7000A);\n\todm_write_4byte(dm, 0x1b00, 0x0015000A);\n\todm_write_4byte(dm, 0x1b00, 0x0000000A);\n\todm_write_4byte(dm, 0x1b04, 0xE2462952);\n\todm_write_4byte(dm, 0x1b08, 0x00000080);\n\todm_write_4byte(dm, 0x1b0c, 0x00000000);\n\todm_write_4byte(dm, 0x1b10, 0x00011800);\n\todm_write_4byte(dm, 0x1b14, 0x00000000);\n\todm_write_4byte(dm, 0x1b18, 0x00292903);\n\todm_write_4byte(dm, 0x1b1c, 0xA2193C32);\n\todm_write_4byte(dm, 0x1b20, 0x03040008);\n\todm_write_4byte(dm, 0x1b24, 0x00060008);\n\todm_write_4byte(dm, 0x1b28, 0x00060300);\n\todm_write_4byte(dm, 0x1b2C, 0x00180018);\n\todm_write_4byte(dm, 0x1b30, 0x40000000);\n\todm_write_4byte(dm, 0x1b34, 0x00000800);\n\todm_write_4byte(dm, 0x1b38, 0x40000000 );\n\todm_write_4byte(dm, 0x1b3C, 0x40000000 );\n\t// TxGainGapK\n\todm_write_4byte(dm, 0x1b98, 0x00000000);\n\todm_write_4byte(dm, 0x1b9c, 0x00000000);\n\todm_write_4byte(dm, 0x1bc0, 0x01000000);\n\todm_write_4byte(dm, 0x1bcc, 0x00000000);\n\t//odm_write_4byte(dm, 0x1be4, 0x0 [1:0]);\n\todm_set_bb_reg(dm, 0x1be4, BIT(1) | BIT(0), 0x0);\n\todm_write_4byte(dm, 0x1bec, 0x40000000);\n\t// --------------------------- DPD --------------------------- //\n\t//DPD associated settings\n\todm_write_4byte(dm, 0x1b54, 0x00009802 );\n\todm_write_4byte(dm, 0x1b60, 0x1F150000);\n\todm_write_4byte(dm, 0x1b64, 0x19140000);\n\todm_write_4byte(dm, 0x1b58, 0x00008F00);\n\todm_write_4byte(dm, 0x1b5C, 0x00000000);\n\t// write pwsf table );\n\todm_write_4byte(dm, 0x1b58, 0x00890000);\n\todm_write_4byte(dm, 0x1b5C, 0x3C6B3FFF);\n\todm_write_4byte(dm, 0x1b58, 0x02890000);\n\todm_write_4byte(dm, 0x1b5C, 0x35D9390A);\n\todm_write_4byte(dm, 0x1b58, 0x04890000);\n\todm_write_4byte(dm, 0x1b5C, 0x2FFE32D6);\n\todm_write_4byte(dm, 0x1b58, 0x06890000);\n\todm_write_4byte(dm, 0x1b5C, 0x2AC62D4F);\n\todm_write_4byte(dm, 0x1b58, 0x08890000);\n\todm_write_4byte(dm, 0x1b5C, 0x261F2862);\n\todm_write_4byte(dm, 0x1b58, 0x0A890000);\n\todm_write_4byte(dm, 0x1b5C, 0x21FA23FD);\n\todm_write_4byte(dm, 0x1b58, 0x0C890000);\n\todm_write_4byte(dm, 0x1b5C, 0x1E482013);\n\todm_write_4byte(dm, 0x1b58, 0x0E890000);\n\todm_write_4byte(dm, 0x1b5C, 0x1AFD1C96);\n\todm_write_4byte(dm, 0x1b58, 0x10890000);\n\todm_write_4byte(dm, 0x1b5C, 0x180E197B);\n\todm_write_4byte(dm, 0x1b58, 0x12890000);\n\todm_write_4byte(dm, 0x1b5C, 0x157016B5);\n\todm_write_4byte(dm, 0x1b58, 0x14890000);\n\todm_write_4byte(dm, 0x1b5C, 0x131B143D);\n\todm_write_4byte(dm, 0x1b58, 0x16890000);\n\todm_write_4byte(dm, 0x1b5C, 0x1107120A);\n\todm_write_4byte(dm, 0x1b58, 0x18890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0F2D1013);\n\todm_write_4byte(dm, 0x1b58, 0x1A890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0D870E54);\n\todm_write_4byte(dm, 0x1b58, 0x1C890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0C0E0CC5);\n\todm_write_4byte(dm, 0x1b58, 0x1E890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0ABF0B62);\n\todm_write_4byte(dm, 0x1b58, 0x20890000);\n\todm_write_4byte(dm, 0x1b5C, 0x09930A25);\n\todm_write_4byte(dm, 0x1b58, 0x22890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0889090A);\n\todm_write_4byte(dm, 0x1b58, 0x24890000);\n\todm_write_4byte(dm, 0x1b5C, 0x079B080F);\n\todm_write_4byte(dm, 0x1b58, 0x26890000);\n\todm_write_4byte(dm, 0x1b5C, 0x06C7072E);\n\todm_write_4byte(dm, 0x1b58, 0x28890000);\n\todm_write_4byte(dm, 0x1b5C, 0x060B0666);\n\todm_write_4byte(dm, 0x1b58, 0x2A890000);\n\todm_write_4byte(dm, 0x1b5C, 0x056305B4);\n\todm_write_4byte(dm, 0x1b58, 0x2C890000);\n\todm_write_4byte(dm, 0x1b5C, 0x04CD0515);\n\todm_write_4byte(dm, 0x1b58, 0x2E890000);\n\todm_write_4byte(dm, 0x1b5C, 0x04470488);\n\todm_write_4byte(dm, 0x1b58, 0x30890000);\n\todm_write_4byte(dm, 0x1b5C, 0x03D0040A);\n\todm_write_4byte(dm, 0x1b58, 0x32890000);\n\todm_write_4byte(dm, 0x1b5C, 0x03660399);\n\todm_write_4byte(dm, 0x1b58, 0x34890000);\n\todm_write_4byte(dm, 0x1b5C, 0x03070335);\n\todm_write_4byte(dm, 0x1b58, 0x36890000);\n\todm_write_4byte(dm, 0x1b5C, 0x02B302DC);\n\todm_write_4byte(dm, 0x1b58, 0x38890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0268028C);\n\todm_write_4byte(dm, 0x1b58, 0x3A890000);\n\todm_write_4byte(dm, 0x1b5C, 0x02250245);\n\todm_write_4byte(dm, 0x1b58, 0x3C890000);\n\todm_write_4byte(dm, 0x1b5C, 0x01E90206);\n\todm_write_4byte(dm, 0x1b58, 0x3E890000);\n\todm_write_4byte(dm, 0x1b5C, 0x01B401CE);\n\todm_write_4byte(dm, 0x1b58, 0x40890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0185019C);\n\todm_write_4byte(dm, 0x1b58, 0x42890000);\n\todm_write_4byte(dm, 0x1b5C, 0x015A016F);\n\todm_write_4byte(dm, 0x1b58, 0x44890000);\n\todm_write_4byte(dm, 0x1b5C, 0x01350147);\n\todm_write_4byte(dm, 0x1b58, 0x46890000);\n\todm_write_4byte(dm, 0x1b5C, 0x01130123);\n\todm_write_4byte(dm, 0x1b58, 0x48890000);\n\todm_write_4byte(dm, 0x1b5C, 0x00F50104);\n\todm_write_4byte(dm, 0x1b58, 0x4A890000);\n\todm_write_4byte(dm, 0x1b5C, 0x00DA00E7);\n\todm_write_4byte(dm, 0x1b58, 0x4C890000);\n\todm_write_4byte(dm, 0x1b5C, 0x00C300CE);\n\todm_write_4byte(dm, 0x1b58, 0x4E890000);\n\todm_write_4byte(dm, 0x1b5C, 0x00AE00B8);\n\todm_write_4byte(dm, 0x1b58, 0x50890000);\n\todm_write_4byte(dm, 0x1b5C, 0x009B00A4);\n\todm_write_4byte(dm, 0x1b58, 0x52890000);\n\todm_write_4byte(dm, 0x1b5C, 0x008A0092);\n\todm_write_4byte(dm, 0x1b58, 0x54890000);\n\todm_write_4byte(dm, 0x1b5C, 0x007B0082);\n\todm_write_4byte(dm, 0x1b58, 0x56890000);\n\todm_write_4byte(dm, 0x1b5C, 0x006E0074);\n\todm_write_4byte(dm, 0x1b58, 0x58890000);\n\todm_write_4byte(dm, 0x1b5C, 0x00620067);\n\todm_write_4byte(dm, 0x1b58, 0x5A890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0057005C);\n\todm_write_4byte(dm, 0x1b58, 0x5C890000);\n\todm_write_4byte(dm, 0x1b5C, 0x004E0052);\n\todm_write_4byte(dm, 0x1b58, 0x5E890000);\n\todm_write_4byte(dm, 0x1b5C, 0x00450049);\n\todm_write_4byte(dm, 0x1b58, 0x60890000);\n\todm_write_4byte(dm, 0x1b5C, 0x003E0041);\n\todm_write_4byte(dm, 0x1b58, 0x62890000);\n\todm_write_4byte(dm, 0x1b5C, 0x0037003A);\n\todm_write_4byte(dm, 0x1b58, 0x62010000);\n\t// ============== Subpage 2 Init_Setting =========== //);\n\todm_write_4byte(dm, 0x1b00, 0x0000000C);\n\t// set LMS parameters \n\todm_write_4byte(dm, 0x1bB8, 0x20202020);\n\todm_write_4byte(dm, 0x1bBC, 0x20202020);\n\todm_write_4byte(dm, 0x1bC0, 0x20202020);\n\todm_write_4byte(dm, 0x1bC4, 0x20202020);\n\todm_write_4byte(dm, 0x1bC8, 0x20202020);\n\todm_write_4byte(dm, 0x1bCC, 0x20202020);\n\todm_write_4byte(dm, 0x1bD0, 0x20202020);\n\todm_write_4byte(dm, 0x1bD8, 0x20202020);\n\todm_write_4byte(dm, 0x1bDC, 0x20202020);\n\todm_write_4byte(dm, 0x1bE0, 0x20202020);\n\todm_write_4byte(dm, 0x1bE4, 0x09050301);\n\todm_write_4byte(dm, 0x1bE8, 0x130F0D0B);\n\todm_write_4byte(dm, 0x1bEC, 0x00000000);\n\todm_write_4byte(dm, 0x1bF0, 0x00000000);\n\t// MDPK init reg settings\n\todm_write_4byte(dm, 0x1b04, 0x30000080);\n\todm_write_4byte(dm, 0x1b08, 0x00004000);\n\todm_write_4byte(dm, 0x1b5C, 0x30000080);\n\todm_write_4byte(dm, 0x1b60, 0x00004000);\n\todm_write_4byte(dm, 0x1bb4, 0x20000000);\n\t// ================= NCTL ============ //\n\t// nctl_8822C_20180626_wi_iqk_dpk_v1_driver\n\todm_write_4byte(dm, 0x1b00, 0x00000008);\n\todm_write_4byte(dm, 0x1b80, 0x00000007);\n\todm_write_4byte(dm, 0x1b80, 0x00080005);\n\todm_write_4byte(dm, 0x1b80, 0x00080007);\n\todm_write_4byte(dm, 0x1b80, 0x80000015);\n\todm_write_4byte(dm, 0x1b80, 0x80000017);\n\todm_write_4byte(dm, 0x1b80, 0x09080025);\n\todm_write_4byte(dm, 0x1b80, 0x09080027);\n\todm_write_4byte(dm, 0x1b80, 0x0f020035);\n\todm_write_4byte(dm, 0x1b80, 0x0f020037);\n\todm_write_4byte(dm, 0x1b80, 0x00220045);\n\todm_write_4byte(dm, 0x1b80, 0x00220047);\n\todm_write_4byte(dm, 0x1b80, 0x00040055);\n\todm_write_4byte(dm, 0x1b80, 0x00040057);\n\todm_write_4byte(dm, 0x1b80, 0x05c00065);\n\todm_write_4byte(dm, 0x1b80, 0x05c00067);\n\todm_write_4byte(dm, 0x1b80, 0x00070075);\n\todm_write_4byte(dm, 0x1b80, 0x00070077);\n\todm_write_4byte(dm, 0x1b80, 0x64020085);\n\todm_write_4byte(dm, 0x1b80, 0x64020087);\n\todm_write_4byte(dm, 0x1b80, 0x00020095);\n\todm_write_4byte(dm, 0x1b80, 0x00020097);\n\todm_write_4byte(dm, 0x1b80, 0x000400a5);\n\todm_write_4byte(dm, 0x1b80, 0x000400a7);\n\todm_write_4byte(dm, 0x1b80, 0x4a0000b5);\n\todm_write_4byte(dm, 0x1b80, 0x4a0000b7);\n\todm_write_4byte(dm, 0x1b80, 0x4b0400c5);\n\todm_write_4byte(dm, 0x1b80, 0x4b0400c7);\n\todm_write_4byte(dm, 0x1b80, 0x860300d5);\n\todm_write_4byte(dm, 0x1b80, 0x860300d7);\n\todm_write_4byte(dm, 0x1b80, 0x400900e5);\n\todm_write_4byte(dm, 0x1b80, 0x400900e7);\n\todm_write_4byte(dm, 0x1b80, 0xe02700f5);\n\todm_write_4byte(dm, 0x1b80, 0xe02700f7);\n\todm_write_4byte(dm, 0x1b80, 0x4b050105);\n\todm_write_4byte(dm, 0x1b80, 0x4b050107);\n\todm_write_4byte(dm, 0x1b80, 0x87030115);\n\todm_write_4byte(dm, 0x1b80, 0x87030117);\n\todm_write_4byte(dm, 0x1b80, 0x400b0125);\n\todm_write_4byte(dm, 0x1b80, 0x400b0127);\n\todm_write_4byte(dm, 0x1b80, 0xe0270135);\n\todm_write_4byte(dm, 0x1b80, 0xe0270137);\n\todm_write_4byte(dm, 0x1b80, 0x4b060145);\n\todm_write_4byte(dm, 0x1b80, 0x4b060147);\n\todm_write_4byte(dm, 0x1b80, 0x88030155);\n\todm_write_4byte(dm, 0x1b80, 0x88030157);\n\todm_write_4byte(dm, 0x1b80, 0x400d0165);\n\todm_write_4byte(dm, 0x1b80, 0x400d0167);\n\todm_write_4byte(dm, 0x1b80, 0xe0270175);\n\todm_write_4byte(dm, 0x1b80, 0xe0270177);\n\todm_write_4byte(dm, 0x1b80, 0x4b000185);\n\todm_write_4byte(dm, 0x1b80, 0x4b000187);\n\todm_write_4byte(dm, 0x1b80, 0x00070195);\n\todm_write_4byte(dm, 0x1b80, 0x00070197);\n\todm_write_4byte(dm, 0x1b80, 0x4c0001a5);\n\todm_write_4byte(dm, 0x1b80, 0x4c0001a7);\n\todm_write_4byte(dm, 0x1b80, 0x000401b5);\n\todm_write_4byte(dm, 0x1b80, 0x000401b7);\n\todm_write_4byte(dm, 0x1b80, 0x400801c5);\n\todm_write_4byte(dm, 0x1b80, 0x400801c7);\n\todm_write_4byte(dm, 0x1b80, 0x505501d5);\n\todm_write_4byte(dm, 0x1b80, 0x505501d7);\n\todm_write_4byte(dm, 0x1b80, 0x090a01e5);\n\todm_write_4byte(dm, 0x1b80, 0x090a01e7);\n\todm_write_4byte(dm, 0x1b80, 0x0ffe01f5);\n\todm_write_4byte(dm, 0x1b80, 0x0ffe01f7);\n\todm_write_4byte(dm, 0x1b80, 0x00220205);\n\todm_write_4byte(dm, 0x1b80, 0x00220207);\n\todm_write_4byte(dm, 0x1b80, 0x00040215);\n\todm_write_4byte(dm, 0x1b80, 0x00040217);\n\todm_write_4byte(dm, 0x1b80, 0x05c00225);\n\todm_write_4byte(dm, 0x1b80, 0x05c00227);\n\todm_write_4byte(dm, 0x1b80, 0x00070235);\n\todm_write_4byte(dm, 0x1b80, 0x00070237);\n\todm_write_4byte(dm, 0x1b80, 0x64000245);\n\todm_write_4byte(dm, 0x1b80, 0x64000247);\n\todm_write_4byte(dm, 0x1b80, 0x00020255);\n\todm_write_4byte(dm, 0x1b80, 0x00020257);\n\todm_write_4byte(dm, 0x1b80, 0x30000265);\n\todm_write_4byte(dm, 0x1b80, 0x30000267);\n\todm_write_4byte(dm, 0x1b80, 0xa50d0275);\n\todm_write_4byte(dm, 0x1b80, 0xa50d0277);\n\todm_write_4byte(dm, 0x1b80, 0xe2a60285);\n\todm_write_4byte(dm, 0x1b80, 0xe2a60287);\n\todm_write_4byte(dm, 0x1b80, 0xf0180295);\n\todm_write_4byte(dm, 0x1b80, 0xf0180297);\n\todm_write_4byte(dm, 0x1b80, 0xf11802a5);\n\todm_write_4byte(dm, 0x1b80, 0xf11802a7);\n\todm_write_4byte(dm, 0x1b80, 0xf21802b5);\n\todm_write_4byte(dm, 0x1b80, 0xf21802b7);\n\todm_write_4byte(dm, 0x1b80, 0xf31802c5);\n\todm_write_4byte(dm, 0x1b80, 0xf31802c7);\n\todm_write_4byte(dm, 0x1b80, 0xf41802d5);\n\todm_write_4byte(dm, 0x1b80, 0xf41802d7);\n\todm_write_4byte(dm, 0x1b80, 0xf51802e5);\n\todm_write_4byte(dm, 0x1b80, 0xf51802e7);\n\todm_write_4byte(dm, 0x1b80, 0xf61802f5);\n\todm_write_4byte(dm, 0x1b80, 0xf61802f7);\n\todm_write_4byte(dm, 0x1b80, 0xf7180305);\n\todm_write_4byte(dm, 0x1b80, 0xf7180307);\n\todm_write_4byte(dm, 0x1b80, 0xf8180315);\n\todm_write_4byte(dm, 0x1b80, 0xf8180317);\n\todm_write_4byte(dm, 0x1b80, 0xf9180325);\n\todm_write_4byte(dm, 0x1b80, 0xf9180327);\n\todm_write_4byte(dm, 0x1b80, 0xfa180335);\n\todm_write_4byte(dm, 0x1b80, 0xfa180337);\n\todm_write_4byte(dm, 0x1b80, 0xf2180345);\n\todm_write_4byte(dm, 0x1b80, 0xf2180347);\n\todm_write_4byte(dm, 0x1b80, 0xf3180355);\n\todm_write_4byte(dm, 0x1b80, 0xf3180357);\n\todm_write_4byte(dm, 0x1b80, 0xf6180365);\n\todm_write_4byte(dm, 0x1b80, 0xf6180367);\n\todm_write_4byte(dm, 0x1b80, 0xf7180375);\n\todm_write_4byte(dm, 0x1b80, 0xf7180377);\n\todm_write_4byte(dm, 0x1b80, 0xf8180385);\n\todm_write_4byte(dm, 0x1b80, 0xf8180387);\n\todm_write_4byte(dm, 0x1b80, 0xf9180395);\n\todm_write_4byte(dm, 0x1b80, 0xf9180397);\n\todm_write_4byte(dm, 0x1b80, 0xfa1803a5);\n\todm_write_4byte(dm, 0x1b80, 0xfa1803a7);\n\todm_write_4byte(dm, 0x1b80, 0xfb1803b5);\n\todm_write_4byte(dm, 0x1b80, 0xfb1803b7);\n\todm_write_4byte(dm, 0x1b80, 0xfc1803c5);\n\todm_write_4byte(dm, 0x1b80, 0xfc1803c7);\n\todm_write_4byte(dm, 0x1b80, 0xfd1803d5);\n\todm_write_4byte(dm, 0x1b80, 0xfd1803d7);\n\todm_write_4byte(dm, 0x1b80, 0xfe1803e5);\n\todm_write_4byte(dm, 0x1b80, 0xfe1803e7);\n\todm_write_4byte(dm, 0x1b80, 0xff1803f5);\n\todm_write_4byte(dm, 0x1b80, 0xff1803f7);\n\todm_write_4byte(dm, 0x1b80, 0x00010405);\n\todm_write_4byte(dm, 0x1b80, 0x00010407);\n\todm_write_4byte(dm, 0x1b80, 0x30610415);\n\todm_write_4byte(dm, 0x1b80, 0x30610417);\n\todm_write_4byte(dm, 0x1b80, 0x30790425);\n\todm_write_4byte(dm, 0x1b80, 0x30790427);\n\todm_write_4byte(dm, 0x1b80, 0x30e20435);\n\todm_write_4byte(dm, 0x1b80, 0x30e20437);\n\todm_write_4byte(dm, 0x1b80, 0x307b0445);\n\todm_write_4byte(dm, 0x1b80, 0x307b0447);\n\todm_write_4byte(dm, 0x1b80, 0x30860455);\n\todm_write_4byte(dm, 0x1b80, 0x30860457);\n\todm_write_4byte(dm, 0x1b80, 0x30910465);\n\todm_write_4byte(dm, 0x1b80, 0x30910467);\n\todm_write_4byte(dm, 0x1b80, 0x30e60475);\n\todm_write_4byte(dm, 0x1b80, 0x30e60477);\n\todm_write_4byte(dm, 0x1b80, 0x30f10485);\n\todm_write_4byte(dm, 0x1b80, 0x30f10487);\n\todm_write_4byte(dm, 0x1b80, 0x30fc0495);\n\todm_write_4byte(dm, 0x1b80, 0x30fc0497);\n\todm_write_4byte(dm, 0x1b80, 0x316104a5);\n\todm_write_4byte(dm, 0x1b80, 0x316104a7);\n\todm_write_4byte(dm, 0x1b80, 0x305804b5);\n\todm_write_4byte(dm, 0x1b80, 0x305804b7);\n\todm_write_4byte(dm, 0x1b80, 0x307904c5);\n\todm_write_4byte(dm, 0x1b80, 0x307904c7);\n\todm_write_4byte(dm, 0x1b80, 0x30e004d5);\n\todm_write_4byte(dm, 0x1b80, 0x30e004d7);\n\todm_write_4byte(dm, 0x1b80, 0x317e04e5);\n\todm_write_4byte(dm, 0x1b80, 0x317e04e7);\n\todm_write_4byte(dm, 0x1b80, 0x318504f5);\n\todm_write_4byte(dm, 0x1b80, 0x318504f7);\n\todm_write_4byte(dm, 0x1b80, 0x318c0505);\n\todm_write_4byte(dm, 0x1b80, 0x318c0507);\n\todm_write_4byte(dm, 0x1b80, 0x31930515);\n\todm_write_4byte(dm, 0x1b80, 0x31930517);\n\todm_write_4byte(dm, 0x1b80, 0x319a0525);\n\todm_write_4byte(dm, 0x1b80, 0x319a0527);\n\todm_write_4byte(dm, 0x1b80, 0x31a30535);\n\todm_write_4byte(dm, 0x1b80, 0x31a30537);\n\todm_write_4byte(dm, 0x1b80, 0x31ac0545);\n\todm_write_4byte(dm, 0x1b80, 0x31ac0547);\n\todm_write_4byte(dm, 0x1b80, 0x31b20555);\n\todm_write_4byte(dm, 0x1b80, 0x31b20557);\n\todm_write_4byte(dm, 0x1b80, 0x31b80565);\n\todm_write_4byte(dm, 0x1b80, 0x31b80567);\n\todm_write_4byte(dm, 0x1b80, 0x31be0575);\n\todm_write_4byte(dm, 0x1b80, 0x31be0577);\n\todm_write_4byte(dm, 0x1b80, 0x4d040585);\n\todm_write_4byte(dm, 0x1b80, 0x4d040587);\n\todm_write_4byte(dm, 0x1b80, 0x20810595);\n\todm_write_4byte(dm, 0x1b80, 0x20810597);\n\todm_write_4byte(dm, 0x1b80, 0x234505a5);\n\todm_write_4byte(dm, 0x1b80, 0x234505a7);\n\todm_write_4byte(dm, 0x1b80, 0x200405b5);\n\todm_write_4byte(dm, 0x1b80, 0x200405b7);\n\todm_write_4byte(dm, 0x1b80, 0x001705c5);\n\todm_write_4byte(dm, 0x1b80, 0x001705c7);\n\todm_write_4byte(dm, 0x1b80, 0x234605d5);\n\todm_write_4byte(dm, 0x1b80, 0x234605d7);\n\todm_write_4byte(dm, 0x1b80, 0x789a05e5);\n\todm_write_4byte(dm, 0x1b80, 0x789a05e7);\n\todm_write_4byte(dm, 0x1b80, 0x4d0005f5);\n\todm_write_4byte(dm, 0x1b80, 0x4d0005f7);\n\todm_write_4byte(dm, 0x1b80, 0x00010605);\n\todm_write_4byte(dm, 0x1b80, 0x00010607);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0615);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0617);\n\todm_write_4byte(dm, 0x1b80, 0x4d040625);\n\todm_write_4byte(dm, 0x1b80, 0x4d040627);\n\todm_write_4byte(dm, 0x1b80, 0x20800635);\n\todm_write_4byte(dm, 0x1b80, 0x20800637);\n\todm_write_4byte(dm, 0x1b80, 0x00000645);\n\todm_write_4byte(dm, 0x1b80, 0x00000647);\n\todm_write_4byte(dm, 0x1b80, 0x4d000655);\n\todm_write_4byte(dm, 0x1b80, 0x4d000657);\n\todm_write_4byte(dm, 0x1b80, 0x55070665);\n\todm_write_4byte(dm, 0x1b80, 0x55070667);\n\todm_write_4byte(dm, 0x1b80, 0xe2370675);\n\todm_write_4byte(dm, 0x1b80, 0xe2370677);\n\todm_write_4byte(dm, 0x1b80, 0xe2370685);\n\todm_write_4byte(dm, 0x1b80, 0xe2370687);\n\todm_write_4byte(dm, 0x1b80, 0x4d040695);\n\todm_write_4byte(dm, 0x1b80, 0x4d040697);\n\todm_write_4byte(dm, 0x1b80, 0x208806a5);\n\todm_write_4byte(dm, 0x1b80, 0x208806a7);\n\todm_write_4byte(dm, 0x1b80, 0x020006b5);\n\todm_write_4byte(dm, 0x1b80, 0x020006b7);\n\todm_write_4byte(dm, 0x1b80, 0x4d0006c5);\n\todm_write_4byte(dm, 0x1b80, 0x4d0006c7);\n\todm_write_4byte(dm, 0x1b80, 0x550f06d5);\n\todm_write_4byte(dm, 0x1b80, 0x550f06d7);\n\todm_write_4byte(dm, 0x1b80, 0xe23706e5);\n\todm_write_4byte(dm, 0x1b80, 0xe23706e7);\n\todm_write_4byte(dm, 0x1b80, 0x4f0206f5);\n\todm_write_4byte(dm, 0x1b80, 0x4f0206f7);\n\todm_write_4byte(dm, 0x1b80, 0x4e000705);\n\todm_write_4byte(dm, 0x1b80, 0x4e000707);\n\todm_write_4byte(dm, 0x1b80, 0x53020715);\n\todm_write_4byte(dm, 0x1b80, 0x53020717);\n\todm_write_4byte(dm, 0x1b80, 0x52010725);\n\todm_write_4byte(dm, 0x1b80, 0x52010727);\n\todm_write_4byte(dm, 0x1b80, 0xe23b0735);\n\todm_write_4byte(dm, 0x1b80, 0xe23b0737);\n\todm_write_4byte(dm, 0x1b80, 0x4d080745);\n\todm_write_4byte(dm, 0x1b80, 0x4d080747);\n\todm_write_4byte(dm, 0x1b80, 0x57100755);\n\todm_write_4byte(dm, 0x1b80, 0x57100757);\n\todm_write_4byte(dm, 0x1b80, 0x57000765);\n\todm_write_4byte(dm, 0x1b80, 0x57000767);\n\todm_write_4byte(dm, 0x1b80, 0x4d000775);\n\todm_write_4byte(dm, 0x1b80, 0x4d000777);\n\todm_write_4byte(dm, 0x1b80, 0x00010785);\n\todm_write_4byte(dm, 0x1b80, 0x00010787);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0795);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0797);\n\todm_write_4byte(dm, 0x1b80, 0x000107a5);\n\todm_write_4byte(dm, 0x1b80, 0x000107a7);\n\todm_write_4byte(dm, 0x1b80, 0x30a607b5);\n\todm_write_4byte(dm, 0x1b80, 0x30a607b7);\n\todm_write_4byte(dm, 0x1b80, 0x002607c5);\n\todm_write_4byte(dm, 0x1b80, 0x002607c7);\n\todm_write_4byte(dm, 0x1b80, 0xe29907d5);\n\todm_write_4byte(dm, 0x1b80, 0xe29907d7);\n\todm_write_4byte(dm, 0x1b80, 0x000207e5);\n\todm_write_4byte(dm, 0x1b80, 0x000207e7);\n\todm_write_4byte(dm, 0x1b80, 0x54ec07f5);\n\todm_write_4byte(dm, 0x1b80, 0x54ec07f7);\n\todm_write_4byte(dm, 0x1b80, 0x0ba60805);\n\todm_write_4byte(dm, 0x1b80, 0x0ba60807);\n\todm_write_4byte(dm, 0x1b80, 0x00260815);\n\todm_write_4byte(dm, 0x1b80, 0x00260817);\n\todm_write_4byte(dm, 0x1b80, 0xe2990825);\n\todm_write_4byte(dm, 0x1b80, 0xe2990827);\n\todm_write_4byte(dm, 0x1b80, 0x00020835);\n\todm_write_4byte(dm, 0x1b80, 0x00020837);\n\todm_write_4byte(dm, 0x1b80, 0x63c30845);\n\todm_write_4byte(dm, 0x1b80, 0x63c30847);\n\todm_write_4byte(dm, 0x1b80, 0x30d00855);\n\todm_write_4byte(dm, 0x1b80, 0x30d00857);\n\todm_write_4byte(dm, 0x1b80, 0x309e0865);\n\todm_write_4byte(dm, 0x1b80, 0x309e0867);\n\todm_write_4byte(dm, 0x1b80, 0x00240875);\n\todm_write_4byte(dm, 0x1b80, 0x00240877);\n\todm_write_4byte(dm, 0x1b80, 0xe2990885);\n\todm_write_4byte(dm, 0x1b80, 0xe2990887);\n\todm_write_4byte(dm, 0x1b80, 0x00020895);\n\todm_write_4byte(dm, 0x1b80, 0x00020897);\n\todm_write_4byte(dm, 0x1b80, 0x54ea08a5);\n\todm_write_4byte(dm, 0x1b80, 0x54ea08a7);\n\todm_write_4byte(dm, 0x1b80, 0x0ba608b5);\n\todm_write_4byte(dm, 0x1b80, 0x0ba608b7);\n\todm_write_4byte(dm, 0x1b80, 0x002408c5);\n\todm_write_4byte(dm, 0x1b80, 0x002408c7);\n\todm_write_4byte(dm, 0x1b80, 0xe29908d5);\n\todm_write_4byte(dm, 0x1b80, 0xe29908d7);\n\todm_write_4byte(dm, 0x1b80, 0x000208e5);\n\todm_write_4byte(dm, 0x1b80, 0x000208e7);\n\todm_write_4byte(dm, 0x1b80, 0x63c308f5);\n\todm_write_4byte(dm, 0x1b80, 0x63c308f7);\n\todm_write_4byte(dm, 0x1b80, 0x30d00905);\n\todm_write_4byte(dm, 0x1b80, 0x30d00907);\n\todm_write_4byte(dm, 0x1b80, 0x6c100915);\n\todm_write_4byte(dm, 0x1b80, 0x6c100917);\n\todm_write_4byte(dm, 0x1b80, 0x6d0f0925);\n\todm_write_4byte(dm, 0x1b80, 0x6d0f0927);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0935);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0937);\n\todm_write_4byte(dm, 0x1b80, 0xe2990945);\n\todm_write_4byte(dm, 0x1b80, 0xe2990947);\n\todm_write_4byte(dm, 0x1b80, 0x6c240955);\n\todm_write_4byte(dm, 0x1b80, 0x6c240957);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0965);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0967);\n\todm_write_4byte(dm, 0x1b80, 0xe2990975);\n\todm_write_4byte(dm, 0x1b80, 0xe2990977);\n\todm_write_4byte(dm, 0x1b80, 0x6c440985);\n\todm_write_4byte(dm, 0x1b80, 0x6c440987);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0995);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0997);\n\todm_write_4byte(dm, 0x1b80, 0xe29909a5);\n\todm_write_4byte(dm, 0x1b80, 0xe29909a7);\n\todm_write_4byte(dm, 0x1b80, 0x6c6409b5);\n\todm_write_4byte(dm, 0x1b80, 0x6c6409b7);\n\todm_write_4byte(dm, 0x1b80, 0xe23f09c5);\n\todm_write_4byte(dm, 0x1b80, 0xe23f09c7);\n\todm_write_4byte(dm, 0x1b80, 0xe29909d5);\n\todm_write_4byte(dm, 0x1b80, 0xe29909d7);\n\todm_write_4byte(dm, 0x1b80, 0x0baa09e5);\n\todm_write_4byte(dm, 0x1b80, 0x0baa09e7);\n\todm_write_4byte(dm, 0x1b80, 0x6c8409f5);\n\todm_write_4byte(dm, 0x1b80, 0x6c8409f7);\n\todm_write_4byte(dm, 0x1b80, 0x6d0f0a05);\n\todm_write_4byte(dm, 0x1b80, 0x6d0f0a07);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0a15);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0a17);\n\todm_write_4byte(dm, 0x1b80, 0xe2990a25);\n\todm_write_4byte(dm, 0x1b80, 0xe2990a27);\n\todm_write_4byte(dm, 0x1b80, 0x6ca40a35);\n\todm_write_4byte(dm, 0x1b80, 0x6ca40a37);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0a45);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0a47);\n\todm_write_4byte(dm, 0x1b80, 0xe2990a55);\n\todm_write_4byte(dm, 0x1b80, 0xe2990a57);\n\todm_write_4byte(dm, 0x1b80, 0x0bac0a65);\n\todm_write_4byte(dm, 0x1b80, 0x0bac0a67);\n\todm_write_4byte(dm, 0x1b80, 0x6cc40a75);\n\todm_write_4byte(dm, 0x1b80, 0x6cc40a77);\n\todm_write_4byte(dm, 0x1b80, 0x6d0f0a85);\n\todm_write_4byte(dm, 0x1b80, 0x6d0f0a87);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0a95);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0a97);\n\todm_write_4byte(dm, 0x1b80, 0xe2990aa5);\n\todm_write_4byte(dm, 0x1b80, 0xe2990aa7);\n\todm_write_4byte(dm, 0x1b80, 0x6ce40ab5);\n\todm_write_4byte(dm, 0x1b80, 0x6ce40ab7);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0ac5);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0ac7);\n\todm_write_4byte(dm, 0x1b80, 0xe2990ad5);\n\todm_write_4byte(dm, 0x1b80, 0xe2990ad7);\n\todm_write_4byte(dm, 0x1b80, 0x6cf40ae5);\n\todm_write_4byte(dm, 0x1b80, 0x6cf40ae7);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0af5);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0af7);\n\todm_write_4byte(dm, 0x1b80, 0xe2990b05);\n\todm_write_4byte(dm, 0x1b80, 0xe2990b07);\n\todm_write_4byte(dm, 0x1b80, 0x6c0c0b15);\n\todm_write_4byte(dm, 0x1b80, 0x6c0c0b17);\n\todm_write_4byte(dm, 0x1b80, 0x6d000b25);\n\todm_write_4byte(dm, 0x1b80, 0x6d000b27);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0b35);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0b37);\n\todm_write_4byte(dm, 0x1b80, 0xe2990b45);\n\todm_write_4byte(dm, 0x1b80, 0xe2990b47);\n\todm_write_4byte(dm, 0x1b80, 0x6c1c0b55);\n\todm_write_4byte(dm, 0x1b80, 0x6c1c0b57);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0b65);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0b67);\n\todm_write_4byte(dm, 0x1b80, 0xe2990b75);\n\todm_write_4byte(dm, 0x1b80, 0xe2990b77);\n\todm_write_4byte(dm, 0x1b80, 0x6c3c0b85);\n\todm_write_4byte(dm, 0x1b80, 0x6c3c0b87);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0b95);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0b97);\n\todm_write_4byte(dm, 0x1b80, 0xe2990ba5);\n\todm_write_4byte(dm, 0x1b80, 0xe2990ba7);\n\todm_write_4byte(dm, 0x1b80, 0xf3c10bb5);\n\todm_write_4byte(dm, 0x1b80, 0xf3c10bb7);\n\todm_write_4byte(dm, 0x1b80, 0x6c5c0bc5);\n\todm_write_4byte(dm, 0x1b80, 0x6c5c0bc7);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0bd5);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0bd7);\n\todm_write_4byte(dm, 0x1b80, 0xe2990be5);\n\todm_write_4byte(dm, 0x1b80, 0xe2990be7);\n\todm_write_4byte(dm, 0x1b80, 0x6c7c0bf5);\n\todm_write_4byte(dm, 0x1b80, 0x6c7c0bf7);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0c05);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0c07);\n\todm_write_4byte(dm, 0x1b80, 0xe2990c15);\n\todm_write_4byte(dm, 0x1b80, 0xe2990c17);\n\todm_write_4byte(dm, 0x1b80, 0xf4c50c25);\n\todm_write_4byte(dm, 0x1b80, 0xf4c50c27);\n\todm_write_4byte(dm, 0x1b80, 0x6c9c0c35);\n\todm_write_4byte(dm, 0x1b80, 0x6c9c0c37);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0c45);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0c47);\n\todm_write_4byte(dm, 0x1b80, 0xe2990c55);\n\todm_write_4byte(dm, 0x1b80, 0xe2990c57);\n\todm_write_4byte(dm, 0x1b80, 0x6cbc0c65);\n\todm_write_4byte(dm, 0x1b80, 0x6cbc0c67);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0c75);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0c77);\n\todm_write_4byte(dm, 0x1b80, 0xe2990c85);\n\todm_write_4byte(dm, 0x1b80, 0xe2990c87);\n\todm_write_4byte(dm, 0x1b80, 0x6cdc0c95);\n\todm_write_4byte(dm, 0x1b80, 0x6cdc0c97);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0ca5);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0ca7);\n\todm_write_4byte(dm, 0x1b80, 0xe2990cb5);\n\todm_write_4byte(dm, 0x1b80, 0xe2990cb7);\n\todm_write_4byte(dm, 0x1b80, 0x6cf00cc5);\n\todm_write_4byte(dm, 0x1b80, 0x6cf00cc7);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0cd5);\n\todm_write_4byte(dm, 0x1b80, 0xe23f0cd7);\n\todm_write_4byte(dm, 0x1b80, 0xe2990ce5);\n\todm_write_4byte(dm, 0x1b80, 0xe2990ce7);\n\todm_write_4byte(dm, 0x1b80, 0x63c30cf5);\n\todm_write_4byte(dm, 0x1b80, 0x63c30cf7);\n\todm_write_4byte(dm, 0x1b80, 0x55010d05);\n\todm_write_4byte(dm, 0x1b80, 0x55010d07);\n\todm_write_4byte(dm, 0x1b80, 0x57040d15);\n\todm_write_4byte(dm, 0x1b80, 0x57040d17);\n\todm_write_4byte(dm, 0x1b80, 0x57000d25);\n\todm_write_4byte(dm, 0x1b80, 0x57000d27);\n\todm_write_4byte(dm, 0x1b80, 0x96000d35);\n\todm_write_4byte(dm, 0x1b80, 0x96000d37);\n\todm_write_4byte(dm, 0x1b80, 0x57080d45);\n\todm_write_4byte(dm, 0x1b80, 0x57080d47);\n\todm_write_4byte(dm, 0x1b80, 0x57000d55);\n\todm_write_4byte(dm, 0x1b80, 0x57000d57);\n\todm_write_4byte(dm, 0x1b80, 0x95000d65);\n\todm_write_4byte(dm, 0x1b80, 0x95000d67);\n\todm_write_4byte(dm, 0x1b80, 0x4d000d75);\n\todm_write_4byte(dm, 0x1b80, 0x4d000d77);\n\todm_write_4byte(dm, 0x1b80, 0x63070d85);\n\todm_write_4byte(dm, 0x1b80, 0x63070d87);\n\todm_write_4byte(dm, 0x1b80, 0x7b400d95);\n\todm_write_4byte(dm, 0x1b80, 0x7b400d97);\n\todm_write_4byte(dm, 0x1b80, 0x7a000da5);\n\todm_write_4byte(dm, 0x1b80, 0x7a000da7);\n\todm_write_4byte(dm, 0x1b80, 0x79000db5);\n\todm_write_4byte(dm, 0x1b80, 0x79000db7);\n\todm_write_4byte(dm, 0x1b80, 0x7f400dc5);\n\todm_write_4byte(dm, 0x1b80, 0x7f400dc7);\n\todm_write_4byte(dm, 0x1b80, 0x7e000dd5);\n\todm_write_4byte(dm, 0x1b80, 0x7e000dd7);\n\todm_write_4byte(dm, 0x1b80, 0x7d000de5);\n\todm_write_4byte(dm, 0x1b80, 0x7d000de7);\n\todm_write_4byte(dm, 0x1b80, 0x00010df5);\n\todm_write_4byte(dm, 0x1b80, 0x00010df7);\n\todm_write_4byte(dm, 0x1b80, 0xe26b0e05);\n\todm_write_4byte(dm, 0x1b80, 0xe26b0e07);\n\todm_write_4byte(dm, 0x1b80, 0x00010e15);\n\todm_write_4byte(dm, 0x1b80, 0x00010e17);\n\todm_write_4byte(dm, 0x1b80, 0x5c320e25);\n\todm_write_4byte(dm, 0x1b80, 0x5c320e27);\n\todm_write_4byte(dm, 0x1b80, 0xe2950e35);\n\todm_write_4byte(dm, 0x1b80, 0xe2950e37);\n\todm_write_4byte(dm, 0x1b80, 0xe26b0e45);\n\todm_write_4byte(dm, 0x1b80, 0xe26b0e47);\n\todm_write_4byte(dm, 0x1b80, 0x00010e55);\n\todm_write_4byte(dm, 0x1b80, 0x00010e57);\n\todm_write_4byte(dm, 0x1b80, 0x311d0e65);\n\todm_write_4byte(dm, 0x1b80, 0x311d0e67);\n\todm_write_4byte(dm, 0x1b80, 0x00260e75);\n\todm_write_4byte(dm, 0x1b80, 0x00260e77);\n\todm_write_4byte(dm, 0x1b80, 0xe29e0e85);\n\todm_write_4byte(dm, 0x1b80, 0xe29e0e87);\n\todm_write_4byte(dm, 0x1b80, 0x00020e95);\n\todm_write_4byte(dm, 0x1b80, 0x00020e97);\n\todm_write_4byte(dm, 0x1b80, 0x54ec0ea5);\n\todm_write_4byte(dm, 0x1b80, 0x54ec0ea7);\n\todm_write_4byte(dm, 0x1b80, 0x0ba60eb5);\n\todm_write_4byte(dm, 0x1b80, 0x0ba60eb7);\n\todm_write_4byte(dm, 0x1b80, 0x00260ec5);\n\todm_write_4byte(dm, 0x1b80, 0x00260ec7);\n\todm_write_4byte(dm, 0x1b80, 0xe29e0ed5);\n\todm_write_4byte(dm, 0x1b80, 0xe29e0ed7);\n\todm_write_4byte(dm, 0x1b80, 0x00020ee5);\n\todm_write_4byte(dm, 0x1b80, 0x00020ee7);\n\todm_write_4byte(dm, 0x1b80, 0x63830ef5);\n\todm_write_4byte(dm, 0x1b80, 0x63830ef7);\n\todm_write_4byte(dm, 0x1b80, 0x30d00f05);\n\todm_write_4byte(dm, 0x1b80, 0x30d00f07);\n\todm_write_4byte(dm, 0x1b80, 0x31110f15);\n\todm_write_4byte(dm, 0x1b80, 0x31110f17);\n\todm_write_4byte(dm, 0x1b80, 0x00240f25);\n\todm_write_4byte(dm, 0x1b80, 0x00240f27);\n\todm_write_4byte(dm, 0x1b80, 0xe29e0f35);\n\todm_write_4byte(dm, 0x1b80, 0xe29e0f37);\n\todm_write_4byte(dm, 0x1b80, 0x00020f45);\n\todm_write_4byte(dm, 0x1b80, 0x00020f47);\n\todm_write_4byte(dm, 0x1b80, 0x54ea0f55);\n\todm_write_4byte(dm, 0x1b80, 0x54ea0f57);\n\todm_write_4byte(dm, 0x1b80, 0x0ba60f65);\n\todm_write_4byte(dm, 0x1b80, 0x0ba60f67);\n\todm_write_4byte(dm, 0x1b80, 0x00240f75);\n\todm_write_4byte(dm, 0x1b80, 0x00240f77);\n\todm_write_4byte(dm, 0x1b80, 0xe29e0f85);\n\todm_write_4byte(dm, 0x1b80, 0xe29e0f87);\n\todm_write_4byte(dm, 0x1b80, 0x00020f95);\n\todm_write_4byte(dm, 0x1b80, 0x00020f97);\n\todm_write_4byte(dm, 0x1b80, 0x63830fa5);\n\todm_write_4byte(dm, 0x1b80, 0x63830fa7);\n\todm_write_4byte(dm, 0x1b80, 0x30d00fb5);\n\todm_write_4byte(dm, 0x1b80, 0x30d00fb7);\n\todm_write_4byte(dm, 0x1b80, 0x5c320fc5);\n\todm_write_4byte(dm, 0x1b80, 0x5c320fc7);\n\todm_write_4byte(dm, 0x1b80, 0x54e60fd5);\n\todm_write_4byte(dm, 0x1b80, 0x54e60fd7);\n\todm_write_4byte(dm, 0x1b80, 0x6e100fe5);\n\todm_write_4byte(dm, 0x1b80, 0x6e100fe7);\n\todm_write_4byte(dm, 0x1b80, 0x6f0f0ff5);\n\todm_write_4byte(dm, 0x1b80, 0x6f0f0ff7);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1005);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1007);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1015);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1017);\n\todm_write_4byte(dm, 0x1b80, 0x5c321025);\n\todm_write_4byte(dm, 0x1b80, 0x5c321027);\n\todm_write_4byte(dm, 0x1b80, 0x54e71035);\n\todm_write_4byte(dm, 0x1b80, 0x54e71037);\n\todm_write_4byte(dm, 0x1b80, 0x6e241045);\n\todm_write_4byte(dm, 0x1b80, 0x6e241047);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1055);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1057);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1065);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1067);\n\todm_write_4byte(dm, 0x1b80, 0x5c321075);\n\todm_write_4byte(dm, 0x1b80, 0x5c321077);\n\todm_write_4byte(dm, 0x1b80, 0x54e81085);\n\todm_write_4byte(dm, 0x1b80, 0x54e81087);\n\todm_write_4byte(dm, 0x1b80, 0x6e441095);\n\todm_write_4byte(dm, 0x1b80, 0x6e441097);\n\todm_write_4byte(dm, 0x1b80, 0xe26b10a5);\n\todm_write_4byte(dm, 0x1b80, 0xe26b10a7);\n\todm_write_4byte(dm, 0x1b80, 0xe29e10b5);\n\todm_write_4byte(dm, 0x1b80, 0xe29e10b7);\n\todm_write_4byte(dm, 0x1b80, 0x5c3210c5);\n\todm_write_4byte(dm, 0x1b80, 0x5c3210c7);\n\todm_write_4byte(dm, 0x1b80, 0x54e910d5);\n\todm_write_4byte(dm, 0x1b80, 0x54e910d7);\n\todm_write_4byte(dm, 0x1b80, 0x6e6410e5);\n\todm_write_4byte(dm, 0x1b80, 0x6e6410e7);\n\todm_write_4byte(dm, 0x1b80, 0xe26b10f5);\n\todm_write_4byte(dm, 0x1b80, 0xe26b10f7);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1105);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1107);\n\todm_write_4byte(dm, 0x1b80, 0x5c321115);\n\todm_write_4byte(dm, 0x1b80, 0x5c321117);\n\todm_write_4byte(dm, 0x1b80, 0x54ea1125);\n\todm_write_4byte(dm, 0x1b80, 0x54ea1127);\n\todm_write_4byte(dm, 0x1b80, 0x0baa1135);\n\todm_write_4byte(dm, 0x1b80, 0x0baa1137);\n\todm_write_4byte(dm, 0x1b80, 0x6e841145);\n\todm_write_4byte(dm, 0x1b80, 0x6e841147);\n\todm_write_4byte(dm, 0x1b80, 0x6f0f1155);\n\todm_write_4byte(dm, 0x1b80, 0x6f0f1157);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1165);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1167);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1175);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1177);\n\todm_write_4byte(dm, 0x1b80, 0x5c321185);\n\todm_write_4byte(dm, 0x1b80, 0x5c321187);\n\todm_write_4byte(dm, 0x1b80, 0x54eb1195);\n\todm_write_4byte(dm, 0x1b80, 0x54eb1197);\n\todm_write_4byte(dm, 0x1b80, 0x6ea411a5);\n\todm_write_4byte(dm, 0x1b80, 0x6ea411a7);\n\todm_write_4byte(dm, 0x1b80, 0xe26b11b5);\n\todm_write_4byte(dm, 0x1b80, 0xe26b11b7);\n\todm_write_4byte(dm, 0x1b80, 0xe29e11c5);\n\todm_write_4byte(dm, 0x1b80, 0xe29e11c7);\n\todm_write_4byte(dm, 0x1b80, 0x5c3211d5);\n\todm_write_4byte(dm, 0x1b80, 0x5c3211d7);\n\todm_write_4byte(dm, 0x1b80, 0x54ec11e5);\n\todm_write_4byte(dm, 0x1b80, 0x54ec11e7);\n\todm_write_4byte(dm, 0x1b80, 0x0bac11f5);\n\todm_write_4byte(dm, 0x1b80, 0x0bac11f7);\n\todm_write_4byte(dm, 0x1b80, 0x6ec41205);\n\todm_write_4byte(dm, 0x1b80, 0x6ec41207);\n\todm_write_4byte(dm, 0x1b80, 0x6f0f1215);\n\todm_write_4byte(dm, 0x1b80, 0x6f0f1217);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1225);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1227);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1235);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1237);\n\todm_write_4byte(dm, 0x1b80, 0x5c321245);\n\todm_write_4byte(dm, 0x1b80, 0x5c321247);\n\todm_write_4byte(dm, 0x1b80, 0x54ed1255);\n\todm_write_4byte(dm, 0x1b80, 0x54ed1257);\n\todm_write_4byte(dm, 0x1b80, 0x6ee41265);\n\todm_write_4byte(dm, 0x1b80, 0x6ee41267);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1275);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1277);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1285);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1287);\n\todm_write_4byte(dm, 0x1b80, 0x5c321295);\n\todm_write_4byte(dm, 0x1b80, 0x5c321297);\n\todm_write_4byte(dm, 0x1b80, 0x54ee12a5);\n\todm_write_4byte(dm, 0x1b80, 0x54ee12a7);\n\todm_write_4byte(dm, 0x1b80, 0x6ef412b5);\n\todm_write_4byte(dm, 0x1b80, 0x6ef412b7);\n\todm_write_4byte(dm, 0x1b80, 0xe26b12c5);\n\todm_write_4byte(dm, 0x1b80, 0xe26b12c7);\n\todm_write_4byte(dm, 0x1b80, 0xe29e12d5);\n\todm_write_4byte(dm, 0x1b80, 0xe29e12d7);\n\todm_write_4byte(dm, 0x1b80, 0x5c3212e5);\n\todm_write_4byte(dm, 0x1b80, 0x5c3212e7);\n\todm_write_4byte(dm, 0x1b80, 0x54ef12f5);\n\todm_write_4byte(dm, 0x1b80, 0x54ef12f7);\n\todm_write_4byte(dm, 0x1b80, 0x6e0c1305);\n\todm_write_4byte(dm, 0x1b80, 0x6e0c1307);\n\todm_write_4byte(dm, 0x1b80, 0x6f001315);\n\todm_write_4byte(dm, 0x1b80, 0x6f001317);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1325);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1327);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1335);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1337);\n\todm_write_4byte(dm, 0x1b80, 0x5c321345);\n\todm_write_4byte(dm, 0x1b80, 0x5c321347);\n\todm_write_4byte(dm, 0x1b80, 0x54f01355);\n\todm_write_4byte(dm, 0x1b80, 0x54f01357);\n\todm_write_4byte(dm, 0x1b80, 0x6e1c1365);\n\todm_write_4byte(dm, 0x1b80, 0x6e1c1367);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1375);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1377);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1385);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1387);\n\todm_write_4byte(dm, 0x1b80, 0x5c321395);\n\todm_write_4byte(dm, 0x1b80, 0x5c321397);\n\todm_write_4byte(dm, 0x1b80, 0x54f113a5);\n\todm_write_4byte(dm, 0x1b80, 0x54f113a7);\n\todm_write_4byte(dm, 0x1b80, 0x6e3c13b5);\n\todm_write_4byte(dm, 0x1b80, 0x6e3c13b7);\n\todm_write_4byte(dm, 0x1b80, 0xe26b13c5);\n\todm_write_4byte(dm, 0x1b80, 0xe26b13c7);\n\todm_write_4byte(dm, 0x1b80, 0xe29e13d5);\n\todm_write_4byte(dm, 0x1b80, 0xe29e13d7);\n\todm_write_4byte(dm, 0x1b80, 0xf6a913e5);\n\todm_write_4byte(dm, 0x1b80, 0xf6a913e7);\n\todm_write_4byte(dm, 0x1b80, 0x5c3213f5);\n\todm_write_4byte(dm, 0x1b80, 0x5c3213f7);\n\todm_write_4byte(dm, 0x1b80, 0x54f21405);\n\todm_write_4byte(dm, 0x1b80, 0x54f21407);\n\todm_write_4byte(dm, 0x1b80, 0x6e5c1415);\n\todm_write_4byte(dm, 0x1b80, 0x6e5c1417);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1425);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1427);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1435);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1437);\n\todm_write_4byte(dm, 0x1b80, 0x5c321445);\n\todm_write_4byte(dm, 0x1b80, 0x5c321447);\n\todm_write_4byte(dm, 0x1b80, 0x54f31455);\n\todm_write_4byte(dm, 0x1b80, 0x54f31457);\n\todm_write_4byte(dm, 0x1b80, 0x6e7c1465);\n\todm_write_4byte(dm, 0x1b80, 0x6e7c1467);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1475);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1477);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1485);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1487);\n\todm_write_4byte(dm, 0x1b80, 0xf7a91495);\n\todm_write_4byte(dm, 0x1b80, 0xf7a91497);\n\todm_write_4byte(dm, 0x1b80, 0x5c3214a5);\n\todm_write_4byte(dm, 0x1b80, 0x5c3214a7);\n\todm_write_4byte(dm, 0x1b80, 0x54f414b5);\n\todm_write_4byte(dm, 0x1b80, 0x54f414b7);\n\todm_write_4byte(dm, 0x1b80, 0x6e9c14c5);\n\todm_write_4byte(dm, 0x1b80, 0x6e9c14c7);\n\todm_write_4byte(dm, 0x1b80, 0xe26b14d5);\n\todm_write_4byte(dm, 0x1b80, 0xe26b14d7);\n\todm_write_4byte(dm, 0x1b80, 0xe29e14e5);\n\todm_write_4byte(dm, 0x1b80, 0xe29e14e7);\n\todm_write_4byte(dm, 0x1b80, 0x5c3214f5);\n\todm_write_4byte(dm, 0x1b80, 0x5c3214f7);\n\todm_write_4byte(dm, 0x1b80, 0x54f51505);\n\todm_write_4byte(dm, 0x1b80, 0x54f51507);\n\todm_write_4byte(dm, 0x1b80, 0x6ebc1515);\n\todm_write_4byte(dm, 0x1b80, 0x6ebc1517);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1525);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1527);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1535);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1537);\n\todm_write_4byte(dm, 0x1b80, 0x5c321545);\n\todm_write_4byte(dm, 0x1b80, 0x5c321547);\n\todm_write_4byte(dm, 0x1b80, 0x54f61555);\n\todm_write_4byte(dm, 0x1b80, 0x54f61557);\n\todm_write_4byte(dm, 0x1b80, 0x6edc1565);\n\todm_write_4byte(dm, 0x1b80, 0x6edc1567);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1575);\n\todm_write_4byte(dm, 0x1b80, 0xe26b1577);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1585);\n\todm_write_4byte(dm, 0x1b80, 0xe29e1587);\n\todm_write_4byte(dm, 0x1b80, 0x5c321595);\n\todm_write_4byte(dm, 0x1b80, 0x5c321597);\n\todm_write_4byte(dm, 0x1b80, 0x54f715a5);\n\todm_write_4byte(dm, 0x1b80, 0x54f715a7);\n\todm_write_4byte(dm, 0x1b80, 0x6ef015b5);\n\todm_write_4byte(dm, 0x1b80, 0x6ef015b7);\n\todm_write_4byte(dm, 0x1b80, 0xe26b15c5);\n\todm_write_4byte(dm, 0x1b80, 0xe26b15c7);\n\todm_write_4byte(dm, 0x1b80, 0xe29e15d5);\n\todm_write_4byte(dm, 0x1b80, 0xe29e15d7);\n\todm_write_4byte(dm, 0x1b80, 0x638315e5);\n\todm_write_4byte(dm, 0x1b80, 0x638315e7);\n\todm_write_4byte(dm, 0x1b80, 0x30d015f5);\n\todm_write_4byte(dm, 0x1b80, 0x30d015f7);\n\todm_write_4byte(dm, 0x1b80, 0x00011605);\n\todm_write_4byte(dm, 0x1b80, 0x00011607);\n\todm_write_4byte(dm, 0x1b80, 0x00041615);\n\todm_write_4byte(dm, 0x1b80, 0x00041617);\n\todm_write_4byte(dm, 0x1b80, 0x55011625);\n\todm_write_4byte(dm, 0x1b80, 0x55011627);\n\todm_write_4byte(dm, 0x1b80, 0x5c311635);\n\todm_write_4byte(dm, 0x1b80, 0x5c311637);\n\todm_write_4byte(dm, 0x1b80, 0x5f821645);\n\todm_write_4byte(dm, 0x1b80, 0x5f821647);\n\todm_write_4byte(dm, 0x1b80, 0x66051655);\n\todm_write_4byte(dm, 0x1b80, 0x66051657);\n\todm_write_4byte(dm, 0x1b80, 0x00061665);\n\todm_write_4byte(dm, 0x1b80, 0x00061667);\n\todm_write_4byte(dm, 0x1b80, 0x5d801675);\n\todm_write_4byte(dm, 0x1b80, 0x5d801677);\n\todm_write_4byte(dm, 0x1b80, 0x09001685);\n\todm_write_4byte(dm, 0x1b80, 0x09001687);\n\todm_write_4byte(dm, 0x1b80, 0x0a011695);\n\todm_write_4byte(dm, 0x1b80, 0x0a011697);\n\todm_write_4byte(dm, 0x1b80, 0x0b4016a5);\n\todm_write_4byte(dm, 0x1b80, 0x0b4016a7);\n\todm_write_4byte(dm, 0x1b80, 0x0d0016b5);\n\todm_write_4byte(dm, 0x1b80, 0x0d0016b7);\n\todm_write_4byte(dm, 0x1b80, 0x0f0116c5);\n\todm_write_4byte(dm, 0x1b80, 0x0f0116c7);\n\todm_write_4byte(dm, 0x1b80, 0x002a16d5);\n\todm_write_4byte(dm, 0x1b80, 0x002a16d7);\n\todm_write_4byte(dm, 0x1b80, 0x055a16e5);\n\todm_write_4byte(dm, 0x1b80, 0x055a16e7);\n\todm_write_4byte(dm, 0x1b80, 0x05db16f5);\n\todm_write_4byte(dm, 0x1b80, 0x05db16f7);\n\todm_write_4byte(dm, 0x1b80, 0xe2891705);\n\todm_write_4byte(dm, 0x1b80, 0xe2891707);\n\todm_write_4byte(dm, 0x1b80, 0xe2371715);\n\todm_write_4byte(dm, 0x1b80, 0xe2371717);\n\todm_write_4byte(dm, 0x1b80, 0x00061725);\n\todm_write_4byte(dm, 0x1b80, 0x00061727);\n\todm_write_4byte(dm, 0x1b80, 0x06da1735);\n\todm_write_4byte(dm, 0x1b80, 0x06da1737);\n\todm_write_4byte(dm, 0x1b80, 0x07db1745);\n\todm_write_4byte(dm, 0x1b80, 0x07db1747);\n\todm_write_4byte(dm, 0x1b80, 0xe2891755);\n\todm_write_4byte(dm, 0x1b80, 0xe2891757);\n\todm_write_4byte(dm, 0x1b80, 0xe2371765);\n\todm_write_4byte(dm, 0x1b80, 0xe2371767);\n\todm_write_4byte(dm, 0x1b80, 0xe2801775);\n\todm_write_4byte(dm, 0x1b80, 0xe2801777);\n\todm_write_4byte(dm, 0x1b80, 0x00021785);\n\todm_write_4byte(dm, 0x1b80, 0x00021787);\n\todm_write_4byte(dm, 0x1b80, 0xe2851795);\n\todm_write_4byte(dm, 0x1b80, 0xe2851797);\n\todm_write_4byte(dm, 0x1b80, 0x5d0017a5);\n\todm_write_4byte(dm, 0x1b80, 0x5d0017a7);\n\todm_write_4byte(dm, 0x1b80, 0x000417b5);\n\todm_write_4byte(dm, 0x1b80, 0x000417b7);\n\todm_write_4byte(dm, 0x1b80, 0x5fa217c5);\n\todm_write_4byte(dm, 0x1b80, 0x5fa217c7);\n\todm_write_4byte(dm, 0x1b80, 0x000117d5);\n\todm_write_4byte(dm, 0x1b80, 0x000117d7);\n\todm_write_4byte(dm, 0x1b80, 0xe1c417e5);\n\todm_write_4byte(dm, 0x1b80, 0xe1c417e7);\n\todm_write_4byte(dm, 0x1b80, 0x740817f5);\n\todm_write_4byte(dm, 0x1b80, 0x740817f7);\n\todm_write_4byte(dm, 0x1b80, 0xe2021805);\n\todm_write_4byte(dm, 0x1b80, 0xe2021807);\n\todm_write_4byte(dm, 0x1b80, 0xe1e41815);\n\todm_write_4byte(dm, 0x1b80, 0xe1e41817);\n\todm_write_4byte(dm, 0x1b80, 0xe2161825);\n\todm_write_4byte(dm, 0x1b80, 0xe2161827);\n\todm_write_4byte(dm, 0x1b80, 0xe2221835);\n\todm_write_4byte(dm, 0x1b80, 0xe2221837);\n\todm_write_4byte(dm, 0x1b80, 0x00011845);\n\todm_write_4byte(dm, 0x1b80, 0x00011847);\n\todm_write_4byte(dm, 0x1b80, 0xe1c41855);\n\todm_write_4byte(dm, 0x1b80, 0xe1c41857);\n\todm_write_4byte(dm, 0x1b80, 0x74081865);\n\todm_write_4byte(dm, 0x1b80, 0x74081867);\n\todm_write_4byte(dm, 0x1b80, 0xe20c1875);\n\todm_write_4byte(dm, 0x1b80, 0xe20c1877);\n\todm_write_4byte(dm, 0x1b80, 0xe1e41885);\n\todm_write_4byte(dm, 0x1b80, 0xe1e41887);\n\todm_write_4byte(dm, 0x1b80, 0xe21c1895);\n\todm_write_4byte(dm, 0x1b80, 0xe21c1897);\n\todm_write_4byte(dm, 0x1b80, 0xe22218a5);\n\todm_write_4byte(dm, 0x1b80, 0xe22218a7);\n\todm_write_4byte(dm, 0x1b80, 0x000118b5);\n\todm_write_4byte(dm, 0x1b80, 0x000118b7);\n\todm_write_4byte(dm, 0x1b80, 0xe1d418c5);\n\todm_write_4byte(dm, 0x1b80, 0xe1d418c7);\n\todm_write_4byte(dm, 0x1b80, 0x740018d5);\n\todm_write_4byte(dm, 0x1b80, 0x740018d7);\n\todm_write_4byte(dm, 0x1b80, 0xe20218e5);\n\todm_write_4byte(dm, 0x1b80, 0xe20218e7);\n\todm_write_4byte(dm, 0x1b80, 0xe1f318f5);\n\todm_write_4byte(dm, 0x1b80, 0xe1f318f7);\n\todm_write_4byte(dm, 0x1b80, 0xe2161905);\n\todm_write_4byte(dm, 0x1b80, 0xe2161907);\n\todm_write_4byte(dm, 0x1b80, 0xe2221915);\n\todm_write_4byte(dm, 0x1b80, 0xe2221917);\n\todm_write_4byte(dm, 0x1b80, 0x00011925);\n\todm_write_4byte(dm, 0x1b80, 0x00011927);\n\todm_write_4byte(dm, 0x1b80, 0xe1d41935);\n\todm_write_4byte(dm, 0x1b80, 0xe1d41937);\n\todm_write_4byte(dm, 0x1b80, 0x74001945);\n\todm_write_4byte(dm, 0x1b80, 0x74001947);\n\todm_write_4byte(dm, 0x1b80, 0xe20c1955);\n\todm_write_4byte(dm, 0x1b80, 0xe20c1957);\n\todm_write_4byte(dm, 0x1b80, 0xe1f31965);\n\todm_write_4byte(dm, 0x1b80, 0xe1f31967);\n\todm_write_4byte(dm, 0x1b80, 0xe21c1975);\n\todm_write_4byte(dm, 0x1b80, 0xe21c1977);\n\todm_write_4byte(dm, 0x1b80, 0xe2221985);\n\todm_write_4byte(dm, 0x1b80, 0xe2221987);\n\todm_write_4byte(dm, 0x1b80, 0x00011995);\n\todm_write_4byte(dm, 0x1b80, 0x00011997);\n\todm_write_4byte(dm, 0x1b80, 0x000419a5);\n\todm_write_4byte(dm, 0x1b80, 0x000419a7);\n\todm_write_4byte(dm, 0x1b80, 0x445b19b5);\n\todm_write_4byte(dm, 0x1b80, 0x445b19b7);\n\todm_write_4byte(dm, 0x1b80, 0x470019c5);\n\todm_write_4byte(dm, 0x1b80, 0x470019c7);\n\todm_write_4byte(dm, 0x1b80, 0x000619d5);\n\todm_write_4byte(dm, 0x1b80, 0x000619d7);\n\todm_write_4byte(dm, 0x1b80, 0x772819e5);\n\todm_write_4byte(dm, 0x1b80, 0x772819e7);\n\todm_write_4byte(dm, 0x1b80, 0x000419f5);\n\todm_write_4byte(dm, 0x1b80, 0x000419f7);\n\todm_write_4byte(dm, 0x1b80, 0x4b801a05);\n\todm_write_4byte(dm, 0x1b80, 0x4b801a07);\n\todm_write_4byte(dm, 0x1b80, 0x40081a15);\n\todm_write_4byte(dm, 0x1b80, 0x40081a17);\n\todm_write_4byte(dm, 0x1b80, 0x00011a25);\n\todm_write_4byte(dm, 0x1b80, 0x00011a27);\n\todm_write_4byte(dm, 0x1b80, 0x00051a35);\n\todm_write_4byte(dm, 0x1b80, 0x00051a37);\n\todm_write_4byte(dm, 0x1b80, 0x5c5b1a45);\n\todm_write_4byte(dm, 0x1b80, 0x5c5b1a47);\n\todm_write_4byte(dm, 0x1b80, 0x5f001a55);\n\todm_write_4byte(dm, 0x1b80, 0x5f001a57);\n\todm_write_4byte(dm, 0x1b80, 0x00061a65);\n\todm_write_4byte(dm, 0x1b80, 0x00061a67);\n\todm_write_4byte(dm, 0x1b80, 0x77291a75);\n\todm_write_4byte(dm, 0x1b80, 0x77291a77);\n\todm_write_4byte(dm, 0x1b80, 0x00041a85);\n\todm_write_4byte(dm, 0x1b80, 0x00041a87);\n\todm_write_4byte(dm, 0x1b80, 0x63801a95);\n\todm_write_4byte(dm, 0x1b80, 0x63801a97);\n\todm_write_4byte(dm, 0x1b80, 0x40081aa5);\n\todm_write_4byte(dm, 0x1b80, 0x40081aa7);\n\todm_write_4byte(dm, 0x1b80, 0x00011ab5);\n\todm_write_4byte(dm, 0x1b80, 0x00011ab7);\n\todm_write_4byte(dm, 0x1b80, 0xe1c41ac5);\n\todm_write_4byte(dm, 0x1b80, 0xe1c41ac7);\n\todm_write_4byte(dm, 0x1b80, 0x74081ad5);\n\todm_write_4byte(dm, 0x1b80, 0x74081ad7);\n\todm_write_4byte(dm, 0x1b80, 0xe2021ae5);\n\todm_write_4byte(dm, 0x1b80, 0xe2021ae7);\n\todm_write_4byte(dm, 0x1b80, 0x00041af5);\n\todm_write_4byte(dm, 0x1b80, 0x00041af7);\n\todm_write_4byte(dm, 0x1b80, 0x40081b05);\n\todm_write_4byte(dm, 0x1b80, 0x40081b07);\n\todm_write_4byte(dm, 0x1b80, 0x00011b15);\n\todm_write_4byte(dm, 0x1b80, 0x00011b17);\n\todm_write_4byte(dm, 0x1b80, 0xe1c41b25);\n\todm_write_4byte(dm, 0x1b80, 0xe1c41b27);\n\todm_write_4byte(dm, 0x1b80, 0x74081b35);\n\todm_write_4byte(dm, 0x1b80, 0x74081b37);\n\todm_write_4byte(dm, 0x1b80, 0xe20c1b45);\n\todm_write_4byte(dm, 0x1b80, 0xe20c1b47);\n\todm_write_4byte(dm, 0x1b80, 0x00041b55);\n\todm_write_4byte(dm, 0x1b80, 0x00041b57);\n\todm_write_4byte(dm, 0x1b80, 0x40081b65);\n\todm_write_4byte(dm, 0x1b80, 0x40081b67);\n\todm_write_4byte(dm, 0x1b80, 0x00011b75);\n\todm_write_4byte(dm, 0x1b80, 0x00011b77);\n\todm_write_4byte(dm, 0x1b80, 0xe1d41b85);\n\todm_write_4byte(dm, 0x1b80, 0xe1d41b87);\n\todm_write_4byte(dm, 0x1b80, 0x74001b95);\n\todm_write_4byte(dm, 0x1b80, 0x74001b97);\n\todm_write_4byte(dm, 0x1b80, 0xe2021ba5);\n\todm_write_4byte(dm, 0x1b80, 0xe2021ba7);\n\todm_write_4byte(dm, 0x1b80, 0x00041bb5);\n\todm_write_4byte(dm, 0x1b80, 0x00041bb7);\n\todm_write_4byte(dm, 0x1b80, 0x40081bc5);\n\todm_write_4byte(dm, 0x1b80, 0x40081bc7);\n\todm_write_4byte(dm, 0x1b80, 0x00011bd5);\n\todm_write_4byte(dm, 0x1b80, 0x00011bd7);\n\todm_write_4byte(dm, 0x1b80, 0xe1d41be5);\n\todm_write_4byte(dm, 0x1b80, 0xe1d41be7);\n\todm_write_4byte(dm, 0x1b80, 0x74001bf5);\n\todm_write_4byte(dm, 0x1b80, 0x74001bf7);\n\todm_write_4byte(dm, 0x1b80, 0xe20c1c05);\n\todm_write_4byte(dm, 0x1b80, 0xe20c1c07);\n\todm_write_4byte(dm, 0x1b80, 0x00041c15);\n\todm_write_4byte(dm, 0x1b80, 0x00041c17);\n\todm_write_4byte(dm, 0x1b80, 0x40081c25);\n\todm_write_4byte(dm, 0x1b80, 0x40081c27);\n\todm_write_4byte(dm, 0x1b80, 0x00011c35);\n\todm_write_4byte(dm, 0x1b80, 0x00011c37);\n\todm_write_4byte(dm, 0x1b80, 0x00071c45);\n\todm_write_4byte(dm, 0x1b80, 0x00071c47);\n\todm_write_4byte(dm, 0x1b80, 0x780c1c55);\n\todm_write_4byte(dm, 0x1b80, 0x780c1c57);\n\todm_write_4byte(dm, 0x1b80, 0x79191c65);\n\todm_write_4byte(dm, 0x1b80, 0x79191c67);\n\todm_write_4byte(dm, 0x1b80, 0x7a001c75);\n\todm_write_4byte(dm, 0x1b80, 0x7a001c77);\n\todm_write_4byte(dm, 0x1b80, 0x7b821c85);\n\todm_write_4byte(dm, 0x1b80, 0x7b821c87);\n\todm_write_4byte(dm, 0x1b80, 0x7b021c95);\n\todm_write_4byte(dm, 0x1b80, 0x7b021c97);\n\todm_write_4byte(dm, 0x1b80, 0x78141ca5);\n\todm_write_4byte(dm, 0x1b80, 0x78141ca7);\n\todm_write_4byte(dm, 0x1b80, 0x79ee1cb5);\n\todm_write_4byte(dm, 0x1b80, 0x79ee1cb7);\n\todm_write_4byte(dm, 0x1b80, 0x7a011cc5);\n\todm_write_4byte(dm, 0x1b80, 0x7a011cc7);\n\todm_write_4byte(dm, 0x1b80, 0x7b831cd5);\n\todm_write_4byte(dm, 0x1b80, 0x7b831cd7);\n\todm_write_4byte(dm, 0x1b80, 0x7b031ce5);\n\todm_write_4byte(dm, 0x1b80, 0x7b031ce7);\n\todm_write_4byte(dm, 0x1b80, 0x780f1cf5);\n\todm_write_4byte(dm, 0x1b80, 0x780f1cf7);\n\todm_write_4byte(dm, 0x1b80, 0x79b41d05);\n\todm_write_4byte(dm, 0x1b80, 0x79b41d07);\n\todm_write_4byte(dm, 0x1b80, 0x7a001d15);\n\todm_write_4byte(dm, 0x1b80, 0x7a001d17);\n\todm_write_4byte(dm, 0x1b80, 0x7b001d25);\n\todm_write_4byte(dm, 0x1b80, 0x7b001d27);\n\todm_write_4byte(dm, 0x1b80, 0x00011d35);\n\todm_write_4byte(dm, 0x1b80, 0x00011d37);\n\todm_write_4byte(dm, 0x1b80, 0x00071d45);\n\todm_write_4byte(dm, 0x1b80, 0x00071d47);\n\todm_write_4byte(dm, 0x1b80, 0x78101d55);\n\todm_write_4byte(dm, 0x1b80, 0x78101d57);\n\todm_write_4byte(dm, 0x1b80, 0x79131d65);\n\todm_write_4byte(dm, 0x1b80, 0x79131d67);\n\todm_write_4byte(dm, 0x1b80, 0x7a001d75);\n\todm_write_4byte(dm, 0x1b80, 0x7a001d77);\n\todm_write_4byte(dm, 0x1b80, 0x7b801d85);\n\todm_write_4byte(dm, 0x1b80, 0x7b801d87);\n\todm_write_4byte(dm, 0x1b80, 0x7b001d95);\n\todm_write_4byte(dm, 0x1b80, 0x7b001d97);\n\todm_write_4byte(dm, 0x1b80, 0x78db1da5);\n\todm_write_4byte(dm, 0x1b80, 0x78db1da7);\n\todm_write_4byte(dm, 0x1b80, 0x79001db5);\n\todm_write_4byte(dm, 0x1b80, 0x79001db7);\n\todm_write_4byte(dm, 0x1b80, 0x7a001dc5);\n\todm_write_4byte(dm, 0x1b80, 0x7a001dc7);\n\todm_write_4byte(dm, 0x1b80, 0x7b811dd5);\n\todm_write_4byte(dm, 0x1b80, 0x7b811dd7);\n\todm_write_4byte(dm, 0x1b80, 0x7b011de5);\n\todm_write_4byte(dm, 0x1b80, 0x7b011de7);\n\todm_write_4byte(dm, 0x1b80, 0x780f1df5);\n\todm_write_4byte(dm, 0x1b80, 0x780f1df7);\n\todm_write_4byte(dm, 0x1b80, 0x79b41e05);\n\todm_write_4byte(dm, 0x1b80, 0x79b41e07);\n\todm_write_4byte(dm, 0x1b80, 0x7a001e15);\n\todm_write_4byte(dm, 0x1b80, 0x7a001e17);\n\todm_write_4byte(dm, 0x1b80, 0x7b001e25);\n\todm_write_4byte(dm, 0x1b80, 0x7b001e27);\n\todm_write_4byte(dm, 0x1b80, 0x00011e35);\n\todm_write_4byte(dm, 0x1b80, 0x00011e37);\n\todm_write_4byte(dm, 0x1b80, 0x00071e45);\n\todm_write_4byte(dm, 0x1b80, 0x00071e47);\n\todm_write_4byte(dm, 0x1b80, 0x783e1e55);\n\todm_write_4byte(dm, 0x1b80, 0x783e1e57);\n\todm_write_4byte(dm, 0x1b80, 0x79f91e65);\n\todm_write_4byte(dm, 0x1b80, 0x79f91e67);\n\todm_write_4byte(dm, 0x1b80, 0x7a011e75);\n\todm_write_4byte(dm, 0x1b80, 0x7a011e77);\n\todm_write_4byte(dm, 0x1b80, 0x7b821e85);\n\todm_write_4byte(dm, 0x1b80, 0x7b821e87);\n\todm_write_4byte(dm, 0x1b80, 0x7b021e95);\n\todm_write_4byte(dm, 0x1b80, 0x7b021e97);\n\todm_write_4byte(dm, 0x1b80, 0x78a91ea5);\n\todm_write_4byte(dm, 0x1b80, 0x78a91ea7);\n\todm_write_4byte(dm, 0x1b80, 0x79ed1eb5);\n\todm_write_4byte(dm, 0x1b80, 0x79ed1eb7);\n\todm_write_4byte(dm, 0x1b80, 0x7b831ec5);\n\todm_write_4byte(dm, 0x1b80, 0x7b831ec7);\n\todm_write_4byte(dm, 0x1b80, 0x7b031ed5);\n\todm_write_4byte(dm, 0x1b80, 0x7b031ed7);\n\todm_write_4byte(dm, 0x1b80, 0x780f1ee5);\n\todm_write_4byte(dm, 0x1b80, 0x780f1ee7);\n\todm_write_4byte(dm, 0x1b80, 0x79b41ef5);\n\todm_write_4byte(dm, 0x1b80, 0x79b41ef7);\n\todm_write_4byte(dm, 0x1b80, 0x7a001f05);\n\todm_write_4byte(dm, 0x1b80, 0x7a001f07);\n\todm_write_4byte(dm, 0x1b80, 0x7b001f15);\n\todm_write_4byte(dm, 0x1b80, 0x7b001f17);\n\todm_write_4byte(dm, 0x1b80, 0x00011f25);\n\todm_write_4byte(dm, 0x1b80, 0x00011f27);\n\todm_write_4byte(dm, 0x1b80, 0x00071f35);\n\todm_write_4byte(dm, 0x1b80, 0x00071f37);\n\todm_write_4byte(dm, 0x1b80, 0x78ae1f45);\n\todm_write_4byte(dm, 0x1b80, 0x78ae1f47);\n\todm_write_4byte(dm, 0x1b80, 0x79fa1f55);\n\todm_write_4byte(dm, 0x1b80, 0x79fa1f57);\n\todm_write_4byte(dm, 0x1b80, 0x7a011f65);\n\todm_write_4byte(dm, 0x1b80, 0x7a011f67);\n\todm_write_4byte(dm, 0x1b80, 0x7b801f75);\n\todm_write_4byte(dm, 0x1b80, 0x7b801f77);\n\todm_write_4byte(dm, 0x1b80, 0x7b001f85);\n\todm_write_4byte(dm, 0x1b80, 0x7b001f87);\n\todm_write_4byte(dm, 0x1b80, 0x787a1f95);\n\todm_write_4byte(dm, 0x1b80, 0x787a1f97);\n\todm_write_4byte(dm, 0x1b80, 0x79f11fa5);\n\todm_write_4byte(dm, 0x1b80, 0x79f11fa7);\n\todm_write_4byte(dm, 0x1b80, 0x7b811fb5);\n\todm_write_4byte(dm, 0x1b80, 0x7b811fb7);\n\todm_write_4byte(dm, 0x1b80, 0x7b011fc5);\n\todm_write_4byte(dm, 0x1b80, 0x7b011fc7);\n\todm_write_4byte(dm, 0x1b80, 0x780f1fd5);\n\todm_write_4byte(dm, 0x1b80, 0x780f1fd7);\n\todm_write_4byte(dm, 0x1b80, 0x79b41fe5);\n\todm_write_4byte(dm, 0x1b80, 0x79b41fe7);\n\todm_write_4byte(dm, 0x1b80, 0x7a001ff5);\n\todm_write_4byte(dm, 0x1b80, 0x7a001ff7);\n\todm_write_4byte(dm, 0x1b80, 0x7b002005);\n\todm_write_4byte(dm, 0x1b80, 0x7b002007);\n\todm_write_4byte(dm, 0x1b80, 0x00012015);\n\todm_write_4byte(dm, 0x1b80, 0x00012017);\n\todm_write_4byte(dm, 0x1b80, 0x77102025);\n\todm_write_4byte(dm, 0x1b80, 0x77102027);\n\todm_write_4byte(dm, 0x1b80, 0x00062035);\n\todm_write_4byte(dm, 0x1b80, 0x00062037);\n\todm_write_4byte(dm, 0x1b80, 0x74002045);\n\todm_write_4byte(dm, 0x1b80, 0x74002047);\n\todm_write_4byte(dm, 0x1b80, 0x76002055);\n\todm_write_4byte(dm, 0x1b80, 0x76002057);\n\todm_write_4byte(dm, 0x1b80, 0x77002065);\n\todm_write_4byte(dm, 0x1b80, 0x77002067);\n\todm_write_4byte(dm, 0x1b80, 0x75102075);\n\todm_write_4byte(dm, 0x1b80, 0x75102077);\n\todm_write_4byte(dm, 0x1b80, 0x75002085);\n\todm_write_4byte(dm, 0x1b80, 0x75002087);\n\todm_write_4byte(dm, 0x1b80, 0xb3002095);\n\todm_write_4byte(dm, 0x1b80, 0xb3002097);\n\todm_write_4byte(dm, 0x1b80, 0x930020a5);\n\todm_write_4byte(dm, 0x1b80, 0x930020a7);\n\todm_write_4byte(dm, 0x1b80, 0x000120b5);\n\todm_write_4byte(dm, 0x1b80, 0x000120b7);\n\todm_write_4byte(dm, 0x1b80, 0x772020c5);\n\todm_write_4byte(dm, 0x1b80, 0x772020c7);\n\todm_write_4byte(dm, 0x1b80, 0x000620d5);\n\todm_write_4byte(dm, 0x1b80, 0x000620d7);\n\todm_write_4byte(dm, 0x1b80, 0x740020e5);\n\todm_write_4byte(dm, 0x1b80, 0x740020e7);\n\todm_write_4byte(dm, 0x1b80, 0x760020f5);\n\todm_write_4byte(dm, 0x1b80, 0x760020f7);\n\todm_write_4byte(dm, 0x1b80, 0x77012105);\n\todm_write_4byte(dm, 0x1b80, 0x77012107);\n\todm_write_4byte(dm, 0x1b80, 0x75102115);\n\todm_write_4byte(dm, 0x1b80, 0x75102117);\n\todm_write_4byte(dm, 0x1b80, 0x75002125);\n\todm_write_4byte(dm, 0x1b80, 0x75002127);\n\todm_write_4byte(dm, 0x1b80, 0xb3002135);\n\todm_write_4byte(dm, 0x1b80, 0xb3002137);\n\todm_write_4byte(dm, 0x1b80, 0x93002145);\n\todm_write_4byte(dm, 0x1b80, 0x93002147);\n\todm_write_4byte(dm, 0x1b80, 0x00012155);\n\todm_write_4byte(dm, 0x1b80, 0x00012157);\n\todm_write_4byte(dm, 0x1b80, 0x00042165);\n\todm_write_4byte(dm, 0x1b80, 0x00042167);\n\todm_write_4byte(dm, 0x1b80, 0x44802175);\n\todm_write_4byte(dm, 0x1b80, 0x44802177);\n\todm_write_4byte(dm, 0x1b80, 0x47302185);\n\todm_write_4byte(dm, 0x1b80, 0x47302187);\n\todm_write_4byte(dm, 0x1b80, 0x00062195);\n\todm_write_4byte(dm, 0x1b80, 0x00062197);\n\todm_write_4byte(dm, 0x1b80, 0x776c21a5);\n\todm_write_4byte(dm, 0x1b80, 0x776c21a7);\n\todm_write_4byte(dm, 0x1b80, 0x000121b5);\n\todm_write_4byte(dm, 0x1b80, 0x000121b7);\n\todm_write_4byte(dm, 0x1b80, 0x000521c5);\n\todm_write_4byte(dm, 0x1b80, 0x000521c7);\n\todm_write_4byte(dm, 0x1b80, 0x5c8021d5);\n\todm_write_4byte(dm, 0x1b80, 0x5c8021d7);\n\todm_write_4byte(dm, 0x1b80, 0x5f3021e5);\n\todm_write_4byte(dm, 0x1b80, 0x5f3021e7);\n\todm_write_4byte(dm, 0x1b80, 0x000621f5);\n\todm_write_4byte(dm, 0x1b80, 0x000621f7);\n\todm_write_4byte(dm, 0x1b80, 0x776d2205);\n\todm_write_4byte(dm, 0x1b80, 0x776d2207);\n\todm_write_4byte(dm, 0x1b80, 0x00012215);\n\todm_write_4byte(dm, 0x1b80, 0x00012217);\n\todm_write_4byte(dm, 0x1b80, 0xb9002225);\n\todm_write_4byte(dm, 0x1b80, 0xb9002227);\n\todm_write_4byte(dm, 0x1b80, 0x99002235);\n\todm_write_4byte(dm, 0x1b80, 0x99002237);\n\todm_write_4byte(dm, 0x1b80, 0x77202245);\n\todm_write_4byte(dm, 0x1b80, 0x77202247);\n\todm_write_4byte(dm, 0x1b80, 0x00042255);\n\todm_write_4byte(dm, 0x1b80, 0x00042257);\n\todm_write_4byte(dm, 0x1b80, 0x40082265);\n\todm_write_4byte(dm, 0x1b80, 0x40082267);\n\todm_write_4byte(dm, 0x1b80, 0x98032275);\n\todm_write_4byte(dm, 0x1b80, 0x98032277);\n\todm_write_4byte(dm, 0x1b80, 0x4a022285);\n\todm_write_4byte(dm, 0x1b80, 0x4a022287);\n\todm_write_4byte(dm, 0x1b80, 0x30192295);\n\todm_write_4byte(dm, 0x1b80, 0x30192297);\n\todm_write_4byte(dm, 0x1b80, 0x000122a5);\n\todm_write_4byte(dm, 0x1b80, 0x000122a7);\n\todm_write_4byte(dm, 0x1b80, 0x7b4822b5);\n\todm_write_4byte(dm, 0x1b80, 0x7b4822b7);\n\todm_write_4byte(dm, 0x1b80, 0x7a9022c5);\n\todm_write_4byte(dm, 0x1b80, 0x7a9022c7);\n\todm_write_4byte(dm, 0x1b80, 0x790022d5);\n\todm_write_4byte(dm, 0x1b80, 0x790022d7);\n\todm_write_4byte(dm, 0x1b80, 0x550322e5);\n\todm_write_4byte(dm, 0x1b80, 0x550322e7);\n\todm_write_4byte(dm, 0x1b80, 0x323722f5);\n\todm_write_4byte(dm, 0x1b80, 0x323722f7);\n\todm_write_4byte(dm, 0x1b80, 0x7b382305);\n\todm_write_4byte(dm, 0x1b80, 0x7b382307);\n\todm_write_4byte(dm, 0x1b80, 0x7a802315);\n\todm_write_4byte(dm, 0x1b80, 0x7a802317);\n\todm_write_4byte(dm, 0x1b80, 0x550b2325);\n\todm_write_4byte(dm, 0x1b80, 0x550b2327);\n\todm_write_4byte(dm, 0x1b80, 0x32372335);\n\todm_write_4byte(dm, 0x1b80, 0x32372337);\n\todm_write_4byte(dm, 0x1b80, 0x7b402345);\n\todm_write_4byte(dm, 0x1b80, 0x7b402347);\n\todm_write_4byte(dm, 0x1b80, 0x7a002355);\n\todm_write_4byte(dm, 0x1b80, 0x7a002357);\n\todm_write_4byte(dm, 0x1b80, 0x55132365);\n\todm_write_4byte(dm, 0x1b80, 0x55132367);\n\todm_write_4byte(dm, 0x1b80, 0x74012375);\n\todm_write_4byte(dm, 0x1b80, 0x74012377);\n\todm_write_4byte(dm, 0x1b80, 0x74002385);\n\todm_write_4byte(dm, 0x1b80, 0x74002387);\n\todm_write_4byte(dm, 0x1b80, 0x8e002395);\n\todm_write_4byte(dm, 0x1b80, 0x8e002397);\n\todm_write_4byte(dm, 0x1b80, 0x000123a5);\n\todm_write_4byte(dm, 0x1b80, 0x000123a7);\n\todm_write_4byte(dm, 0x1b80, 0x570223b5);\n\todm_write_4byte(dm, 0x1b80, 0x570223b7);\n\todm_write_4byte(dm, 0x1b80, 0x570023c5);\n\todm_write_4byte(dm, 0x1b80, 0x570023c7);\n\todm_write_4byte(dm, 0x1b80, 0x970023d5);\n\todm_write_4byte(dm, 0x1b80, 0x970023d7);\n\todm_write_4byte(dm, 0x1b80, 0x000123e5);\n\todm_write_4byte(dm, 0x1b80, 0x000123e7);\n\todm_write_4byte(dm, 0x1b80, 0x4f7823f5);\n\todm_write_4byte(dm, 0x1b80, 0x4f7823f7);\n\todm_write_4byte(dm, 0x1b80, 0x53882405);\n\todm_write_4byte(dm, 0x1b80, 0x53882407);\n\todm_write_4byte(dm, 0x1b80, 0xe24b2415);\n\todm_write_4byte(dm, 0x1b80, 0xe24b2417);\n\todm_write_4byte(dm, 0x1b80, 0x54802425);\n\todm_write_4byte(dm, 0x1b80, 0x54802427);\n\todm_write_4byte(dm, 0x1b80, 0x54002435);\n\todm_write_4byte(dm, 0x1b80, 0x54002437);\n\todm_write_4byte(dm, 0x1b80, 0x54812445);\n\todm_write_4byte(dm, 0x1b80, 0x54812447);\n\todm_write_4byte(dm, 0x1b80, 0x54002455);\n\todm_write_4byte(dm, 0x1b80, 0x54002457);\n\todm_write_4byte(dm, 0x1b80, 0x54822465);\n\todm_write_4byte(dm, 0x1b80, 0x54822467);\n\todm_write_4byte(dm, 0x1b80, 0x54002475);\n\todm_write_4byte(dm, 0x1b80, 0x54002477);\n\todm_write_4byte(dm, 0x1b80, 0xe2562485);\n\todm_write_4byte(dm, 0x1b80, 0xe2562487);\n\todm_write_4byte(dm, 0x1b80, 0xbf1d2495);\n\todm_write_4byte(dm, 0x1b80, 0xbf1d2497);\n\todm_write_4byte(dm, 0x1b80, 0x301924a5);\n\todm_write_4byte(dm, 0x1b80, 0x301924a7);\n\todm_write_4byte(dm, 0x1b80, 0xe22b24b5);\n\todm_write_4byte(dm, 0x1b80, 0xe22b24b7);\n\todm_write_4byte(dm, 0x1b80, 0xe23024c5);\n\todm_write_4byte(dm, 0x1b80, 0xe23024c7);\n\todm_write_4byte(dm, 0x1b80, 0xe23424d5);\n\todm_write_4byte(dm, 0x1b80, 0xe23424d7);\n\todm_write_4byte(dm, 0x1b80, 0xe23b24e5);\n\todm_write_4byte(dm, 0x1b80, 0xe23b24e7);\n\todm_write_4byte(dm, 0x1b80, 0xe29524f5);\n\todm_write_4byte(dm, 0x1b80, 0xe29524f7);\n\todm_write_4byte(dm, 0x1b80, 0x55132505);\n\todm_write_4byte(dm, 0x1b80, 0x55132507);\n\todm_write_4byte(dm, 0x1b80, 0xe2372515);\n\todm_write_4byte(dm, 0x1b80, 0xe2372517);\n\todm_write_4byte(dm, 0x1b80, 0x55152525);\n\todm_write_4byte(dm, 0x1b80, 0x55152527);\n\todm_write_4byte(dm, 0x1b80, 0xe23b2535);\n\todm_write_4byte(dm, 0x1b80, 0xe23b2537);\n\todm_write_4byte(dm, 0x1b80, 0xe2952545);\n\todm_write_4byte(dm, 0x1b80, 0xe2952547);\n\todm_write_4byte(dm, 0x1b80, 0x00012555);\n\todm_write_4byte(dm, 0x1b80, 0x00012557);\n\todm_write_4byte(dm, 0x1b80, 0x54bf2565);\n\todm_write_4byte(dm, 0x1b80, 0x54bf2567);\n\todm_write_4byte(dm, 0x1b80, 0x54c02575);\n\todm_write_4byte(dm, 0x1b80, 0x54c02577);\n\todm_write_4byte(dm, 0x1b80, 0x54a32585);\n\todm_write_4byte(dm, 0x1b80, 0x54a32587);\n\todm_write_4byte(dm, 0x1b80, 0x54c12595);\n\todm_write_4byte(dm, 0x1b80, 0x54c12597);\n\todm_write_4byte(dm, 0x1b80, 0x54a425a5);\n\todm_write_4byte(dm, 0x1b80, 0x54a425a7);\n\todm_write_4byte(dm, 0x1b80, 0x4c1825b5);\n\todm_write_4byte(dm, 0x1b80, 0x4c1825b7);\n\todm_write_4byte(dm, 0x1b80, 0xbf0725c5);\n\todm_write_4byte(dm, 0x1b80, 0xbf0725c7);\n\todm_write_4byte(dm, 0x1b80, 0x54c225d5);\n\todm_write_4byte(dm, 0x1b80, 0x54c225d7);\n\todm_write_4byte(dm, 0x1b80, 0x54a425e5);\n\todm_write_4byte(dm, 0x1b80, 0x54a425e7);\n\todm_write_4byte(dm, 0x1b80, 0xbf0425f5);\n\todm_write_4byte(dm, 0x1b80, 0xbf0425f7);\n\todm_write_4byte(dm, 0x1b80, 0x54c12605);\n\todm_write_4byte(dm, 0x1b80, 0x54c12607);\n\todm_write_4byte(dm, 0x1b80, 0x54a32615);\n\todm_write_4byte(dm, 0x1b80, 0x54a32617);\n\todm_write_4byte(dm, 0x1b80, 0xbf012625);\n\todm_write_4byte(dm, 0x1b80, 0xbf012627);\n\todm_write_4byte(dm, 0x1b80, 0xe2a32635);\n\todm_write_4byte(dm, 0x1b80, 0xe2a32637);\n\todm_write_4byte(dm, 0x1b80, 0x54df2645);\n\todm_write_4byte(dm, 0x1b80, 0x54df2647);\n\todm_write_4byte(dm, 0x1b80, 0x00012655);\n\todm_write_4byte(dm, 0x1b80, 0x00012657);\n\todm_write_4byte(dm, 0x1b80, 0x54bf2665);\n\todm_write_4byte(dm, 0x1b80, 0x54bf2667);\n\todm_write_4byte(dm, 0x1b80, 0x54e52675);\n\todm_write_4byte(dm, 0x1b80, 0x54e52677);\n\todm_write_4byte(dm, 0x1b80, 0x050a2685);\n\todm_write_4byte(dm, 0x1b80, 0x050a2687);\n\todm_write_4byte(dm, 0x1b80, 0x54df2695);\n\todm_write_4byte(dm, 0x1b80, 0x54df2697);\n\todm_write_4byte(dm, 0x1b80, 0x000126a5);\n\todm_write_4byte(dm, 0x1b80, 0x000126a7);\n\todm_write_4byte(dm, 0x1b80, 0x7f4026b5);\n\todm_write_4byte(dm, 0x1b80, 0x7f4026b7);\n\todm_write_4byte(dm, 0x1b80, 0x7e0026c5);\n\todm_write_4byte(dm, 0x1b80, 0x7e0026c7);\n\todm_write_4byte(dm, 0x1b80, 0x7d0026d5);\n\todm_write_4byte(dm, 0x1b80, 0x7d0026d7);\n\todm_write_4byte(dm, 0x1b80, 0x550126e5);\n\todm_write_4byte(dm, 0x1b80, 0x550126e7);\n\todm_write_4byte(dm, 0x1b80, 0x5c3126f5);\n\todm_write_4byte(dm, 0x1b80, 0x5c3126f7);\n\todm_write_4byte(dm, 0x1b80, 0xe2372705);\n\todm_write_4byte(dm, 0x1b80, 0xe2372707);\n\todm_write_4byte(dm, 0x1b80, 0xe23b2715);\n\todm_write_4byte(dm, 0x1b80, 0xe23b2717);\n\todm_write_4byte(dm, 0x1b80, 0x54802725);\n\todm_write_4byte(dm, 0x1b80, 0x54802727);\n\todm_write_4byte(dm, 0x1b80, 0x54002735);\n\todm_write_4byte(dm, 0x1b80, 0x54002737);\n\todm_write_4byte(dm, 0x1b80, 0x54812745);\n\todm_write_4byte(dm, 0x1b80, 0x54812747);\n\todm_write_4byte(dm, 0x1b80, 0x54002755);\n\todm_write_4byte(dm, 0x1b80, 0x54002757);\n\todm_write_4byte(dm, 0x1b80, 0x54822765);\n\todm_write_4byte(dm, 0x1b80, 0x54822767);\n\todm_write_4byte(dm, 0x1b80, 0x54002775);\n\todm_write_4byte(dm, 0x1b80, 0x54002777);\n\todm_write_4byte(dm, 0x1b80, 0xe2562785);\n\todm_write_4byte(dm, 0x1b80, 0xe2562787);\n\todm_write_4byte(dm, 0x1b80, 0xbfed2795);\n\todm_write_4byte(dm, 0x1b80, 0xbfed2797);\n\todm_write_4byte(dm, 0x1b80, 0x301927a5);\n\todm_write_4byte(dm, 0x1b80, 0x301927a7);\n\todm_write_4byte(dm, 0x1b80, 0x740227b5);\n\todm_write_4byte(dm, 0x1b80, 0x740227b7);\n\todm_write_4byte(dm, 0x1b80, 0x003f27c5);\n\todm_write_4byte(dm, 0x1b80, 0x003f27c7);\n\todm_write_4byte(dm, 0x1b80, 0x740027d5);\n\todm_write_4byte(dm, 0x1b80, 0x740027d7);\n\todm_write_4byte(dm, 0x1b80, 0x000227e5);\n\todm_write_4byte(dm, 0x1b80, 0x000227e7);\n\todm_write_4byte(dm, 0x1b80, 0x000127f5);\n\todm_write_4byte(dm, 0x1b80, 0x000127f7);\n\todm_write_4byte(dm, 0x1b80, 0x00062805);\n\todm_write_4byte(dm, 0x1b80, 0x00062807);\n\todm_write_4byte(dm, 0x1b80, 0x5a802815);\n\todm_write_4byte(dm, 0x1b80, 0x5a802817);\n\todm_write_4byte(dm, 0x1b80, 0x5a002825);\n\todm_write_4byte(dm, 0x1b80, 0x5a002827);\n\todm_write_4byte(dm, 0x1b80, 0x92002835);\n\todm_write_4byte(dm, 0x1b80, 0x92002837);\n\todm_write_4byte(dm, 0x1b80, 0x00012845);\n\todm_write_4byte(dm, 0x1b80, 0x00012847);\n\todm_write_4byte(dm, 0x1b80, 0x5b8f2855);\n\todm_write_4byte(dm, 0x1b80, 0x5b8f2857);\n\todm_write_4byte(dm, 0x1b80, 0x5b0f2865);\n\todm_write_4byte(dm, 0x1b80, 0x5b0f2867);\n\todm_write_4byte(dm, 0x1b80, 0x91002875);\n\todm_write_4byte(dm, 0x1b80, 0x91002877);\n\todm_write_4byte(dm, 0x1b80, 0x00012885);\n\todm_write_4byte(dm, 0x1b80, 0x00012887);\n\todm_write_4byte(dm, 0x1b80, 0x00062895);\n\todm_write_4byte(dm, 0x1b80, 0x00062897);\n\todm_write_4byte(dm, 0x1b80, 0x5d8028a5);\n\todm_write_4byte(dm, 0x1b80, 0x5d8028a7);\n\todm_write_4byte(dm, 0x1b80, 0x5e5628b5);\n\todm_write_4byte(dm, 0x1b80, 0x5e5628b7);\n\todm_write_4byte(dm, 0x1b80, 0x000428c5);\n\todm_write_4byte(dm, 0x1b80, 0x000428c7);\n\todm_write_4byte(dm, 0x1b80, 0x4d0828d5);\n\todm_write_4byte(dm, 0x1b80, 0x4d0828d7);\n\todm_write_4byte(dm, 0x1b80, 0x571028e5);\n\todm_write_4byte(dm, 0x1b80, 0x571028e7);\n\todm_write_4byte(dm, 0x1b80, 0x570028f5);\n\todm_write_4byte(dm, 0x1b80, 0x570028f7);\n\todm_write_4byte(dm, 0x1b80, 0x4d002905);\n\todm_write_4byte(dm, 0x1b80, 0x4d002907);\n\todm_write_4byte(dm, 0x1b80, 0x00062915);\n\todm_write_4byte(dm, 0x1b80, 0x00062917);\n\todm_write_4byte(dm, 0x1b80, 0x5d002925);\n\todm_write_4byte(dm, 0x1b80, 0x5d002927);\n\todm_write_4byte(dm, 0x1b80, 0x00042935);\n\todm_write_4byte(dm, 0x1b80, 0x00042937);\n\todm_write_4byte(dm, 0x1b80, 0x00012945);\n\todm_write_4byte(dm, 0x1b80, 0x00012947);\n\todm_write_4byte(dm, 0x1b80, 0x549f2955);\n\todm_write_4byte(dm, 0x1b80, 0x549f2957);\n\todm_write_4byte(dm, 0x1b80, 0x54ff2965);\n\todm_write_4byte(dm, 0x1b80, 0x54ff2967);\n\todm_write_4byte(dm, 0x1b80, 0x54002975);\n\todm_write_4byte(dm, 0x1b80, 0x54002977);\n\todm_write_4byte(dm, 0x1b80, 0x00012985);\n\todm_write_4byte(dm, 0x1b80, 0x00012987);\n\todm_write_4byte(dm, 0x1b80, 0x5c312995);\n\todm_write_4byte(dm, 0x1b80, 0x5c312997);\n\todm_write_4byte(dm, 0x1b80, 0x071429a5);\n\todm_write_4byte(dm, 0x1b80, 0x071429a7);\n\todm_write_4byte(dm, 0x1b80, 0x540029b5);\n\todm_write_4byte(dm, 0x1b80, 0x540029b7);\n\todm_write_4byte(dm, 0x1b80, 0x5c3229c5);\n\todm_write_4byte(dm, 0x1b80, 0x5c3229c7);\n\todm_write_4byte(dm, 0x1b80, 0x000129d5);\n\todm_write_4byte(dm, 0x1b80, 0x000129d7);\n\todm_write_4byte(dm, 0x1b80, 0x5c3229e5);\n\todm_write_4byte(dm, 0x1b80, 0x5c3229e7);\n\todm_write_4byte(dm, 0x1b80, 0x071429f5);\n\todm_write_4byte(dm, 0x1b80, 0x071429f7);\n\todm_write_4byte(dm, 0x1b80, 0x54002a05);\n\todm_write_4byte(dm, 0x1b80, 0x54002a07);\n\todm_write_4byte(dm, 0x1b80, 0x5c312a15);\n\todm_write_4byte(dm, 0x1b80, 0x5c312a17);\n\todm_write_4byte(dm, 0x1b80, 0x00012a25);\n\todm_write_4byte(dm, 0x1b80, 0x00012a27);\n\todm_write_4byte(dm, 0x1b80, 0x4c982a35);\n\todm_write_4byte(dm, 0x1b80, 0x4c982a37);\n\todm_write_4byte(dm, 0x1b80, 0x4c182a45);\n\todm_write_4byte(dm, 0x1b80, 0x4c182a47);\n\todm_write_4byte(dm, 0x1b80, 0x00012a55);\n\todm_write_4byte(dm, 0x1b80, 0x00012a57);\n\todm_write_4byte(dm, 0x1b80, 0x5c322a65);\n\todm_write_4byte(dm, 0x1b80, 0x5c322a67);\n\todm_write_4byte(dm, 0x1b80, 0x62042a75);\n\todm_write_4byte(dm, 0x1b80, 0x62042a77);\n\todm_write_4byte(dm, 0x1b80, 0x63032a85);\n\todm_write_4byte(dm, 0x1b80, 0x63032a87);\n\todm_write_4byte(dm, 0x1b80, 0x66072a95);\n\todm_write_4byte(dm, 0x1b80, 0x66072a97);\n\todm_write_4byte(dm, 0x1b80, 0x7b402aa5);\n\todm_write_4byte(dm, 0x1b80, 0x7b402aa7);\n\todm_write_4byte(dm, 0x1b80, 0x7a002ab5);\n\todm_write_4byte(dm, 0x1b80, 0x7a002ab7);\n\todm_write_4byte(dm, 0x1b80, 0x79002ac5);\n\todm_write_4byte(dm, 0x1b80, 0x79002ac7);\n\todm_write_4byte(dm, 0x1b80, 0x7f402ad5);\n\todm_write_4byte(dm, 0x1b80, 0x7f402ad7);\n\todm_write_4byte(dm, 0x1b80, 0x7e002ae5);\n\todm_write_4byte(dm, 0x1b80, 0x7e002ae7);\n\todm_write_4byte(dm, 0x1b80, 0x7d002af5);\n\todm_write_4byte(dm, 0x1b80, 0x7d002af7);\n\todm_write_4byte(dm, 0x1b80, 0x09012b05);\n\todm_write_4byte(dm, 0x1b80, 0x09012b07);\n\todm_write_4byte(dm, 0x1b80, 0x0c012b15);\n\todm_write_4byte(dm, 0x1b80, 0x0c012b17);\n\todm_write_4byte(dm, 0x1b80, 0x0ba62b25);\n\todm_write_4byte(dm, 0x1b80, 0x0ba62b27);\n\todm_write_4byte(dm, 0x1b80, 0x00012b35);\n\todm_write_4byte(dm, 0x1b80, 0x00012b37);\n\todm_write_4byte(dm, 0x1b80, 0x00000006);\n\todm_write_4byte(dm, 0x1b80, 0x00000002);\n\n}\n\n\nvoid _iqk_cal_path_off_8822c(struct dm_struct *dm)\n{\n\tu8 path;\n\n\todm_set_bb_reg(dm, 0x1bb8, BIT(20), 0x0);\n\tfor(path = 0; path < SS_8822C; path++) {\n\t\t//odm_set_rf_reg(dm, (enum rf_path)path, 0x0, 0xfffff, 0x10000);\t\t\n\t\t//odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | path << 1);\n\t\todm_set_bb_reg(dm, R_0x1b00, BIT(2)| BIT(1), path);\n\t\todm_set_bb_reg(dm, 0x1bcc, 0x3f, 0x3f);\n\t}\n}\n\nvoid _iqk_con_tx_8822c(\n\tstruct dm_struct *dm,\n\tboolean is_contx)\n{\n\tif (is_contx) {\n\t\todm_set_bb_reg(dm, 0x180c, 0x3, 0x0);\n\t\todm_set_bb_reg(dm, 0x410c, 0x3, 0x0);\n\t\t//odm_set_bb_reg(dm, 0x520c, 0x3, 0x0);\n\t\t//odm_set_bb_reg(dm, 0x530c, 0x3, 0x0);\n\t\todm_set_bb_reg(dm, 0x1d08, BIT(0), 0x1);\n\t\todm_set_bb_reg(dm, 0x1ca4, BIT(0), 0x1);\n\t\todm_set_bb_reg(dm, 0x1e70, BIT(1), 0x1);\n\t\todm_set_bb_reg(dm, 0x1e70, BIT(1), 0x0);\n\t\todm_set_bb_reg(dm, 0x1e70, BIT(2), 0x0);\n\t\todm_set_bb_reg(dm, 0x1e70, BIT(2), 0x1);\n\t} else {\n\t\todm_set_bb_reg(dm, 0x1d08, BIT(0), 0x0);\n\t\todm_set_bb_reg(dm, 0x1ca4, BIT(0), 0x0);\n\t}\n}\n\nvoid _iqk_rf_set_check_8822c(\n\tstruct dm_struct *dm,\n\tu8 path,\n\tu16 add,\n\tu32 data)\n{\n\tu32 i;\n\n\todm_set_rf_reg(dm, (enum rf_path)path, add, RFREGOFFSETMASK, data);\n\n\tfor (i = 0; i < 100; i++) {\n\t\tif (odm_get_rf_reg(dm, (enum rf_path)path, add, RFREGOFFSETMASK) == data)\n\t\t\tbreak;\n\t\telse {\n\t\t\tODM_delay_us(10);\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path, add, RFREGOFFSETMASK, data);\n\t\t}\n\t}\n}\n\nvoid _iqk_rf0xb0_workaround_8822c(\n\tstruct dm_struct *dm)\n{\n\t/*add 0xb8 control for the bad phase noise after switching channel*/\n\todm_set_rf_reg(dm, (enum rf_path)0x0, RF_0xb8, RFREGOFFSETMASK, 0x00a00);\n\todm_set_rf_reg(dm, (enum rf_path)0x0, RF_0xb8, RFREGOFFSETMASK, 0x80a00);\n}\n\nvoid _iqk_fill_iqk_report_8822c(\n\tvoid *dm_void,\n\tu8 ch)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk = &dm->IQK_info;\n\tu32 tmp1 = 0x0, tmp2 = 0x0, tmp3 = 0x0, data;\n\tu8 i;\n\n\tfor (i = 0; i < SS_8822C; i++) {\n\t\ttmp1 += ((iqk->iqk_fail_report[ch][i][TX_IQK] & 1) << i);\n\t\ttmp2 += ((iqk->iqk_fail_report[ch][i][RX_IQK] & 1) << (i + 4));\n\t\ttmp3 += ((iqk->rxiqk_fail_code[ch][i] & 0x3) << (i * 2 + 8));\n\t\tdata = iqk->rxiqk_agc[ch][i];\n\n\t\todm_write_4byte(dm, R_0x1b00, IQK_CMD_8822C | i << 1 );\n\t\todm_set_bb_reg(dm, R_0x1bf0, 0x0000ffff, tmp1 | tmp2 | tmp3);\n\t\todm_write_4byte(dm, R_0x1be8, data);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S%d 0x1bf0 =0x%x,0x1be8=0x%x\\n\", i,\n\t\t       odm_read_4byte(dm, 0x1bf0), odm_read_4byte(dm, 0x1be8));\n\t}\n\n\t\n}\n\nvoid _iqk_fail_count_8822c(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tu8 i;\n\n\tdm->n_iqk_cnt++;\n\tif (odm_get_rf_reg(dm, RF_PATH_A, RF_0x1bf0, BIT(16)) == 1)\n\t\tiqk_info->is_reload = true;\n\telse\n\t\tiqk_info->is_reload = false;\n\n\tif (!iqk_info->is_reload) {\n\t\tfor (i = 0; i < 8; i++) {\n\t\t\tif (odm_get_bb_reg(dm, R_0x1bf0, BIT(i)) == 1)\n\t\t\t\tdm->n_iqk_fail_cnt++;\n\t\t}\n\t}\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]All/Fail = %d %d\\n\", dm->n_iqk_cnt, dm->n_iqk_fail_cnt);\n}\n\nvoid _iqk_iqk_fail_report_8822c(\n\tstruct dm_struct *dm)\n{\n\tu32 tmp1bf0 = 0x0;\n\tu8 i;\n\n\ttmp1bf0 = odm_read_4byte(dm, 0x1bf0);\n\n\tfor (i = 0; i < 4; i++) {\n\t\tif (tmp1bf0 & (0x1 << i))\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\n\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK] please check S%d TXIQK\\n\", i);\n#else\n\t\t\tpanic_printk(\"[IQK] please check S%d TXIQK\\n\", i);\n#endif\n\t\tif (tmp1bf0 & (0x1 << (i + 12)))\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\n\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK] please check S%d RXIQK\\n\", i);\n#else\n\t\t\tpanic_printk(\"[IQK] please check S%d RXIQK\\n\", i);\n#endif\n\t}\n}\n\nvoid _iqk_backup_mac_bb_8822c(\n\tstruct dm_struct *dm,\n\tu32 *MAC_backup,\n\tu32 *BB_backup,\n\tu32 *backup_mac_reg,\n\tu32 *backup_bb_reg)\n{\n\tu32 i;\n\tfor (i = 0; i < MAC_REG_NUM_8822C; i++){\n\t\tMAC_backup[i] = odm_read_4byte(dm, backup_mac_reg[i]);\n\t\t//RF_DBG(dm, DBG_RF_IQK, \"[IQK]Backup mac addr = %x, value =% x\\n\", backup_mac_reg[i], MAC_backup[i]);\n\t}\n\tfor (i = 0; i < BB_REG_NUM_8822C; i++){\n\t\tBB_backup[i] = odm_read_4byte(dm, backup_bb_reg[i]);\t\t\n\t\t//RF_DBG(dm, DBG_RF_IQK, \"[IQK]Backup bbaddr = %x, value =% x\\n\", backup_bb_reg[i], BB_backup[i]);\n\t}\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]BackupMacBB Success!!!!\\n\"); \n}\n\nvoid _iqk_backup_rf_8822c(\n\tstruct dm_struct *dm,\n\tu32 RF_backup[][SS_8822C],\n\tu32 *backup_rf_reg)\n{\n\tu32 i;\n\n\tfor (i = 0; i < RF_REG_NUM_8822C; i++) {\n\t\tRF_backup[i][RF_PATH_A] = odm_get_rf_reg(dm, RF_PATH_A, backup_rf_reg[i], RFREGOFFSETMASK);\n\t\tRF_backup[i][RF_PATH_B] = odm_get_rf_reg(dm, RF_PATH_B, backup_rf_reg[i], RFREGOFFSETMASK);\n\t\t//RF_backup[i][RF_PATH_C] = odm_get_rf_reg(dm, RF_PATH_C, backup_rf_reg[i], RFREGOFFSETMASK);\n\t\t//RF_backup[i][RF_PATH_D] = odm_get_rf_reg(dm, RF_PATH_D, backup_rf_reg[i], RFREGOFFSETMASK);\n\t}\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]BackupRF Success!!!!\\n\"); \n}\n\nvoid _iqk_agc_bnd_int_8822c(\n\tstruct dm_struct *dm)\n{\n\treturn;\n#if 0\n\t/*initialize RX AGC bnd, it must do after bbreset*/\n\todm_write_4byte(dm, 0x1b00, 0x8);\n\todm_write_4byte(dm, 0x1b00, 0x00A70008);\n\todm_write_4byte(dm, 0x1b00, 0x00150008);\n\todm_write_4byte(dm, 0x1b00, 0x8);\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]init. rx agc bnd\\n\");\n#endif\n}\n\nvoid _iqk_bb_reset_8822c(\n\tstruct dm_struct *dm)\n{\n\tboolean cca_ing = false;\n\tu32 count = 0;\n\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK, 0x10000);\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0x0, RFREGOFFSETMASK, 0x10000);\n\t/*reset BB report*/\n\todm_set_bb_reg(dm, R_0x8f8, 0x0ff00000, 0x0);\n\n\twhile (1) {\n\t\todm_write_4byte(dm, 0x8fc, 0x0);\n\t\todm_set_bb_reg(dm, R_0x198c, 0x7, 0x7);\n\t\tcca_ing = (boolean)odm_get_bb_reg(dm, R_0xfa0, BIT(3));\n\n\t\tif (count > 3000)\n\t\t\tcca_ing = false;\n\n\t\tif (cca_ing) {\n\t\t\tODM_delay_us(10);\n\t\t\tcount++;\n\t\t} else {\n\t\t\todm_write_1byte(dm, 0x808, 0x0); /*RX ant off*/\n\t\t\todm_set_bb_reg(dm, R_0xa04, BIT(27) | BIT(26) | BIT(25) | BIT(24), 0x0); /*CCK RX path off*/\n\n\t\t\t/*BBreset*/\n\t\t\todm_set_bb_reg(dm, R_0x0, BIT(16), 0x0);\n\t\t\todm_set_bb_reg(dm, R_0x0, BIT(16), 0x1);\n\n\t\t\tif (odm_get_bb_reg(dm, R_0x660, BIT(16)))\n\t\t\t\todm_write_4byte(dm, 0x6b4, 0x89000006);\n\t\t\t/*RF_DBG(dm, DBG_RF_IQK, \"[IQK]BBreset!!!!\\n\");*/\n\t\t\tbreak;\n\t\t}\n\t}\n}\nvoid _iqk_bb_for_dpk_setting_8822c(struct dm_struct *dm)\n{\n\todm_set_bb_reg(dm, R_0x1e24, BIT(17), 0x1);\n\todm_set_bb_reg(dm, R_0x1cd0, BIT(28), 0x1);\n\todm_set_bb_reg(dm, R_0x1cd0, BIT(29), 0x1);\n\todm_set_bb_reg(dm, R_0x1cd0, BIT(30), 0x1);\n\todm_set_bb_reg(dm, R_0x1cd0, BIT(31), 0x0);\n\t//odm_set_bb_reg(dm, R_0x1c68, 0x0f000000, 0xf);\t\n\todm_set_bb_reg(dm, 0x1d58, 0xff8, 0x1ff);\n\todm_set_bb_reg(dm, 0x1864, BIT(31), 0x1);\n\todm_set_bb_reg(dm, 0x4164, BIT(31), 0x1);\n\todm_set_bb_reg(dm, R_0x180c, BIT(27), 0x1);\n\todm_set_bb_reg(dm, R_0x410c, BIT(27), 0x1);\n\todm_set_bb_reg(dm, R_0x186c, BIT(7), 0x1);\n\todm_set_bb_reg(dm, 0x416c, BIT(7), 0x1);\n\todm_set_bb_reg(dm, R_0x180c, 0x3, 0x0); //S0 -3 wire\n\todm_set_bb_reg(dm, R_0x410c, 0x3, 0x0); //S1 -3wire\n\todm_set_bb_reg(dm, 0x1a00, BIT(1) | BIT(0), 0x2);\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]_iqk_bb_for_dpk_setting_8822c!!!!\\n\");\n}\n\nvoid _iqk_rf_setting_8822c(struct dm_struct *dm)\n{\t\n\todm_set_bb_reg(dm, 0x1bb8, BIT(20), 0x0);\n\t/*TxIQK mode S0,RF0x00[19:16]=0x4*/\n\todm_set_rf_reg(dm, RF_PATH_A, 0xef, 0xfffff, 0x80000);\n\todm_set_rf_reg(dm, RF_PATH_A, 0x33, 0x0000f, 0x4);\n\todm_set_rf_reg(dm, RF_PATH_A, 0x3e, 0xfffff, 0x00003);\n\todm_set_rf_reg(dm, RF_PATH_A, 0x3f, 0xfffff, 0xF60FF);//3F[15]=0, iPA off \n\todm_set_rf_reg(dm, RF_PATH_A, 0xef, 0xfffff, 0x00000);\n\n\t/*TxIQK mode S1,RF0x00[19:16]=0x4*/\n\todm_set_rf_reg(dm, RF_PATH_B, 0xef, 0xfffff, 0x80000);\n\todm_set_rf_reg(dm, RF_PATH_B, 0x33, 0x0000f, 0x4);\n\todm_set_rf_reg(dm, RF_PATH_B, 0x3f, 0xfffff, 0xFD83F);//3F[15]=0, iPA off \n\todm_set_rf_reg(dm, RF_PATH_B, 0xef, 0xfffff, 0x00000);\n\n\t// RxIQK1 mode S0, RF0x00[19:16]=0x6\n\todm_set_rf_reg(dm, RF_PATH_A, 0xef, 0xfffff, 0x80000); //[19]: WE_LUT_RFMODE\n\todm_set_rf_reg(dm, RF_PATH_A, 0x33, 0x0000f, 0x6); //RFMODE\n\todm_set_rf_reg(dm, RF_PATH_A, 0x3e, 0xfffff, 0x00003);\n\todm_set_rf_reg(dm, RF_PATH_A, 0x3f, 0xfffff, 0x760FF);//3F[15]=0, iPA off , 3F[19]=0, POW_TXBB off\n\todm_set_rf_reg(dm, RF_PATH_A, 0xef, 0xfffff, 0x00000);\n\n\t// RxIQK1 mode S1, RF0x00[19:16]=0x6\n\todm_set_rf_reg(dm, RF_PATH_B, 0xef, 0xfffff, 0x80000);\n\todm_set_rf_reg(dm, RF_PATH_B, 0x33, 0x0000f, 0x6);\n\todm_set_rf_reg(dm, RF_PATH_B, 0x3f, 0xfffff, 0xDD83F);//3F[15]=0, iPA off \n\todm_set_rf_reg(dm, RF_PATH_B, 0xef, 0xfffff, 0x00000);\n\n\t// RxIQK2 mode S0, RF0x00[19:16]=0x7\t\n\todm_set_rf_reg(dm, RF_PATH_A, 0xef, 0xfffff, 0x80000); //[19]: WE_LUT_RFMODE\n\todm_set_rf_reg(dm, RF_PATH_A, 0x33, 0x0000f, 0x7); //RFMODE\n\todm_set_rf_reg(dm, RF_PATH_A, 0x3e, 0xfffff, 0x00003);\n\todm_set_rf_reg(dm, RF_PATH_A, 0x3f, 0xfffff, 0x7DEFF);//3F[15]=1, iPA on ,3F[19]=0, POW_TXBB off\n\todm_set_rf_reg(dm, RF_PATH_A, 0xef, 0xfffff, 0x00000);\n\n\t// RxIQK2 mode S1, RF0x00[19:16]=0x7\n\todm_set_rf_reg(dm, RF_PATH_B, 0xef, 0xfffff, 0x80000); //[19]: WE_LUT_RFMODE\n\todm_set_rf_reg(dm, RF_PATH_B, 0x33, 0x0000f, 0x7); //RFMODE\n\todm_set_rf_reg(dm, RF_PATH_B, 0x3f, 0xfffff, 0xDF7BF);//3F[13]=1, iPA on ,3F[17]=0, POW_TXBB off\n\todm_set_rf_reg(dm, RF_PATH_B, 0xef, 0xfffff, 0x00000);\n\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x19, RFREG_MASK, 0x0);\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0x19, RFREG_MASK, 0x0);\n\n\t\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]_iqk_rf_setting_8822c RF01!!!!\\n\");\n}\n\nvoid _iqk_afe_setting_8822c(\n\tstruct dm_struct *dm,\n\tboolean do_iqk)\n{\n\tu8 i;\n\n\tif (do_iqk) {\n\t\t/*03_8822C_AFE_for_DPK.txt*/\n\t\t// AFE on Settings\n\t\todm_write_4byte(dm, 0x1c38, 0xFFFFFFFF); //AD/DA both on\n\t\todm_write_4byte(dm, 0x1830, 0x700f0001);\n\t\todm_write_4byte(dm, 0x1830, 0x700f0001);\n\t\todm_write_4byte(dm, 0x1830, 0x701f0001);\n\t\todm_write_4byte(dm, 0x1830, 0x702f0001);\n\t\todm_write_4byte(dm, 0x1830, 0x703f0001);\n\t\todm_write_4byte(dm, 0x1830, 0x704f0001);\n\t\todm_write_4byte(dm, 0x1830, 0x705f0001);\n\t\todm_write_4byte(dm, 0x1830, 0x706f0001);\n\t\todm_write_4byte(dm, 0x1830, 0x707f0001);\n\t\todm_write_4byte(dm, 0x1830, 0x708f0001);\n\t\todm_write_4byte(dm, 0x1830, 0x709f0001);\n\t\todm_write_4byte(dm, 0x1830, 0x70af0001);\n\t\todm_write_4byte(dm, 0x1830, 0x70bf0001);\n\t\todm_write_4byte(dm, 0x1830, 0x70cf0001);\n\t\todm_write_4byte(dm, 0x1830, 0x70df0001);\n\t\todm_write_4byte(dm, 0x1830, 0x70ef0001);\n\t\todm_write_4byte(dm, 0x1830, 0x70ff0001);\n\t\todm_write_4byte(dm, 0x1830, 0x70ff0001);\n\t\todm_write_4byte(dm, 0x4130, 0x700f0001);\n\t\todm_write_4byte(dm, 0x4130, 0x700f0001);\n\t\todm_write_4byte(dm, 0x4130, 0x701f0001);\n\t\todm_write_4byte(dm, 0x4130, 0x702f0001);\n\t\todm_write_4byte(dm, 0x4130, 0x703f0001);\n\t\todm_write_4byte(dm, 0x4130, 0x704f0001);\n\t\todm_write_4byte(dm, 0x4130, 0x705f0001);\n\t\todm_write_4byte(dm, 0x4130, 0x706f0001);\n\t\todm_write_4byte(dm, 0x4130, 0x707f0001);\n\t\todm_write_4byte(dm, 0x4130, 0x708f0001);\n\t\todm_write_4byte(dm, 0x4130, 0x709f0001);\n\t\todm_write_4byte(dm, 0x4130, 0x70af0001);\n\t\todm_write_4byte(dm, 0x4130, 0x70bf0001);\n\t\todm_write_4byte(dm, 0x4130, 0x70cf0001);\n\t\todm_write_4byte(dm, 0x4130, 0x70df0001);\n\t\todm_write_4byte(dm, 0x4130, 0x70ef0001);\n\t\todm_write_4byte(dm, 0x4130, 0x70ff0001);\n\t\todm_write_4byte(dm, 0x4130, 0x70ff0001);\t\t\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]AFE setting for IQK mode!!!!\\n\");\n\t} else {\n\t\t// AFE Restore Settings\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70144041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70244041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70344041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70444041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70644041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x707b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x708b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x709b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ab8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70bb8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70cb8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70db8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70eb8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70fb8041);\n\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70144041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70244041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70344041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70444041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70644041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x707b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x708b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x709b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ab8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70bb8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70cb8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70db8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70eb8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70fb8041);\n\n\t\t/*11_8822C_BB_for_DPK_restore*/\n\t\todm_set_bb_reg(dm, 0x1d0c, BIT(16), 0x1);\n\t\todm_set_bb_reg(dm, 0x1d0c, BIT(16), 0x0);\n\t\todm_set_bb_reg(dm, 0x1d0c, BIT(16), 0x1);\n\n\t\todm_set_bb_reg(dm, 0x1bb8, BIT(20), 0x0);\n\t\todm_set_bb_reg(dm, 0x1bcc, 0x000000ff, 0x0);\n\n\t\t// BB Restore Settings\n\t\t//odm_set_bb_reg(dm, 0x1c68, 0x0f000000, 0x0);\n\t\todm_set_bb_reg(dm, 0x1d58, 0xff8, 0x0);\n\t\t//odm_set_bb_reg(dm, 0x1c3c, BIT(0), 0x1);\n\t\t//odm_set_bb_reg(dm, 0x1c3c, BIT(1), 0x1);\n\t\todm_set_bb_reg(dm, 0x1864, BIT(31), 0x0);\n\t\todm_set_bb_reg(dm, 0x4164, BIT(31), 0x0);\n\t\todm_set_bb_reg(dm, 0x180c, BIT(27), 0x0);\n\t\todm_set_bb_reg(dm, 0x410c, BIT(27), 0x0);\n\t\todm_set_bb_reg(dm, 0x186c, BIT(7), 0x0);\n\t\todm_set_bb_reg(dm, 0x416c, BIT(7), 0x0);\n\t\todm_set_bb_reg(dm, 0x180c, BIT(1) | BIT(0), 0x3);\n\t\todm_set_bb_reg(dm, 0x410c, BIT(1) | BIT(0), 0x3);\n\t\todm_set_bb_reg(dm, 0x1a00, BIT(1) | BIT(0), 0x0);\n\n\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]AFE setting for Normal mode!!!!\\n\");\n\t}\n}\n\nvoid _iqk_restore_mac_bb_8822c(\n\tstruct dm_struct *dm,\n\tu32 *MAC_backup,\n\tu32 *BB_backup,\n\tu32 *backup_mac_reg,\n\tu32 *backup_bb_reg)\n{\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tu32 i;\t\n\n\t/*toggle IGI*/\n\todm_write_4byte(dm, 0x1d70, 0x50505050);\n\n\tfor (i = 0; i < MAC_REG_NUM_8822C; i++){\n\t\todm_write_4byte(dm, backup_mac_reg[i], MAC_backup[i]);\n\t\t//RF_DBG(dm, DBG_RF_IQK, \"[IQK]restore mac = %x, value = %x\\n\",backup_mac_reg[i],MAC_backup[i]);\n\t\t}\n\tfor (i = 0; i < BB_REG_NUM_8822C; i++){\n\t\todm_write_4byte(dm, backup_bb_reg[i], BB_backup[i]);\t\t\n\t\t//RF_DBG(dm, DBG_RF_IQK, \"[IQK]restore bb = %x, value = %x\\n\",backup_bb_reg[i],BB_backup[i]);\n\t\t}\n\t/*rx go throughput IQK*/\n#if 0\n\todm_set_bb_reg(dm, 0x180c, BIT(31), 0x1);\n\todm_set_bb_reg(dm, 0x410c, BIT(31), 0x1);\n#else\n\tif (iqk_info->iqk_fail_report[0][0][RXIQK] == true) \n\t\todm_set_bb_reg(dm, 0x180c, BIT(31), 0x0);\n\telse\n\t\todm_set_bb_reg(dm, 0x180c, BIT(31), 0x1);\n\n\tif (iqk_info->iqk_fail_report[0][1][RXIQK] == true) \n\t\todm_set_bb_reg(dm, 0x410c, BIT(31), 0x0);\n\telse\n\t\todm_set_bb_reg(dm, 0x410c, BIT(31), 0x1);\n#endif\n\t//odm_set_bb_reg(dm, 0x520c, BIT(31), 0x1);\n\t//odm_set_bb_reg(dm, 0x530c, BIT(31), 0x1);\n\t/*\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]RestoreMacBB Success!!!!\\n\"); */\n}\n\nvoid _iqk_restore_rf_8822c(\n\tstruct dm_struct *dm,\n\tu32 *rf_reg,\n\tu32 temp[][SS_8822C])\n{\n\tu32 i;\n\t\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0xfffff, 0x0);\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0xfffff, 0x0);\n\t/*0xdf[4]=0*/\n\t//_iqk_rf_set_check_8822c(dm, RF_PATH_A, 0xdf, temp[0][RF_PATH_A] & (~BIT(4)));\n\t//_iqk_rf_set_check_8822c(dm, RF_PATH_B, 0xdf, temp[0][RF_PATH_B] & (~BIT(4)));\n\n\tfor (i = 0; i < RF_REG_NUM_8822C; i++) {\n\t\todm_set_rf_reg(dm, RF_PATH_A, rf_reg[i],\n\t\t\t       0xfffff, temp[i][RF_PATH_A]);\n\t\todm_set_rf_reg(dm, RF_PATH_B, rf_reg[i],\n\t\t\t       0xfffff, temp[i][RF_PATH_B]);\n\t}\n\t\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0xde, BIT(16), 0x0);\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0xde, BIT(16), 0x0);\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]RestoreRF Success!!!!\\n\"); \n}\n\nvoid _iqk_backup_iqk_8822c(\n\tstruct dm_struct *dm,\n\tu8 step,\n\tu8 path)\n{\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tu8 i, j, k;\n\n\tswitch (step) {\n\tcase 0:\n\t\tiqk_info->iqk_channel[1] = iqk_info->iqk_channel[0];\n\t\t//RF_DBG(dm, DBG_RF_IQK, \"[IQK](0)iqk_info->iqk_channel[1] = %2x\\n\",iqk_info->iqk_channel[1]);\n\t\tfor (i = 0; i < SS_8822C; i++) {\n\t\t\tiqk_info->lok_idac[1][i] = iqk_info->lok_idac[0][i];\n\t\t\tiqk_info->rxiqk_agc[1][i] = iqk_info->rxiqk_agc[0][i];\n\t\t\tiqk_info->bypass_iqk[1][i] = iqk_info->bypass_iqk[0][i];\n\t\t\tiqk_info->rxiqk_fail_code[1][i] = iqk_info->rxiqk_fail_code[0][i];\n\t\t\tfor (j = 0; j < 2; j++) {\n\t\t\t\tiqk_info->iqk_fail_report[1][i][j] = iqk_info->iqk_fail_report[0][i][j];\t\t\t\n\t\t\t\t//RF_DBG(dm, DBG_RF_IQK, \"[IQK](2)iqk_info->iqk_fail_report[0][%x][%x] = %2x\\n\",i,j,iqk_info->iqk_fail_report[1][i][j] );\n\t\t\t\tfor (k = 0; k <= 16; k++) {\n\t\t\t\t\tiqk_info->iqk_cfir_real[1][i][j][k] = iqk_info->iqk_cfir_real[0][i][j][k];\n\t\t\t\t\tiqk_info->iqk_cfir_imag[1][i][j][k] = iqk_info->iqk_cfir_imag[0][i][j][k];\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tfor (i = 0; i < SS_8822C; i++) {\n\t\t\tiqk_info->rxiqk_fail_code[0][i] = 0x0;\n\t\t\tiqk_info->rxiqk_agc[0][i] = 0x0;\n\t\t\tfor (j = 0; j < 2; j++) {\n\t\t\t\tiqk_info->iqk_fail_report[0][i][j] = true;\n\t\t\t\tiqk_info->gs_retry_count[0][i][j] = 0x0;\n\t\t\t}\n\t\t\tfor (j = 0; j < 3; j++)\n\t\t\t\tiqk_info->retry_count[0][i][j] = 0x0;\n\t\t}\n\t\t/*backup channel*/\n\t\tiqk_info->iqk_channel[0] = iqk_info->rf_reg18;\n\t\tbreak;\n\tcase 1: /*LOK backup*/\n\t\tiqk_info->lok_idac[0][path] = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, RFREGOFFSETMASK);\t\n\t\t//RF_DBG(dm, DBG_RF_IQK, \"[IQK](4) iqk_info->lok_idac[0][%d]= %2x\\n\", path, iqk_info->lok_idac[0][path]);\n\t\tbreak;\n\tcase 2: /*TXIQK backup*/\n\t\tiqk_get_cfir_8822c(dm, TX_IQK, path, false);\n\t\tbreak;\t\t\n\tcase 3: /*RXIQK backup*/\t\t\n\t\tiqk_get_cfir_8822c(dm, RX_IQK, path, false);\n\t\tbreak;\n\t}\n}\n\nvoid _iqk_reload_iqk_setting_8822c(\n\tstruct dm_struct *dm,\n\tu8 ch,\n\tu8 reload_idx /*1: reload TX, 2: reload LO, TX, RX*/\n\t)\n{\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n#if 1\n\tu8 i, path, idx;\n\tu16 iqk_apply[2] = {0x180c, 0x410c};\n\tu32 tmp = 0x0, tmp1 = 0x0, tmp2 =0x0;\n\n\tfor (path = 0; path < SS_8822C; path++) {\n\t\tif (reload_idx == 2) {\n\t\t\t/*odm_set_rf_reg(dm, (enum rf_path)path, RF_0xdf, BIT(4), 0x1);*/\n\t\t\ttmp = odm_get_rf_reg(dm, (enum rf_path)path, RF_0xdf, RFREGOFFSETMASK) | BIT(4);\n\t\t\t_iqk_rf_set_check_8822c(dm, (enum rf_path)path, 0xdf, tmp);\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x58, RFREGOFFSETMASK, iqk_info->lok_idac[ch][path]);\t\t\t\n\t\t}\n\n\t\tfor (idx = 0; idx < reload_idx; idx++) {\n\t\t\todm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | path << 1);\n\t\t\todm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7);\n\t\t\todm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x40000000);\n\t\t\todm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x40000000);\n\t\t\todm_write_1byte(dm, 0x1bcc, 0x0);\n\n\t\t\tif (idx == TX_IQK) {//TXCFIR\n\t\t\t\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x3);\t\t\n\t\t\t\ttmp1 = 0xc0000001;\n\t\t\t} else {//RXCFIR\n\t\t\t\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);\n\t\t\t\ttmp1 = 0x60000001;\n\t\t\t}\n\t\t\tfor (i = 0; i <= 16; i++) {\n\t\t\t\ttmp2 = tmp1 | iqk_info->iqk_cfir_real[ch][path][idx][i] << 8;\n\t\t\t\ttmp2 = (tmp2 | i << 2) + 2;\n\t\t\t\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, tmp2);\n\t\t\t}\n\t\t\tfor (i = 0; i <= 16; i++) {\n\t\t\t\ttmp2 = tmp1 | iqk_info->iqk_cfir_imag[ch][path][idx][i] << 8;\n\t\t\t\ttmp2 = (tmp2 | i << 2);\n\t\t\t\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, tmp2);\t\t\n\t\t\t}\n\t\t\tif (idx == RX_IQK) {\n\t\t\t\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);\n\t\t\t\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001);\t\t\n\t\t\t\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);\n\t\t\t\t//odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);\n\t\t\t}\n\t\t}\n\t\t// end for write CFIR SRAM\n//\t\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000000);\n\t\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);\n//\t\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);\n\t}\n#endif\n}\n\nboolean\n_iqk_reload_iqk_8822c(\n\tstruct dm_struct *dm,\n\tboolean reset)\n{\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tu8 i;\n\tiqk_info->is_reload = false;\n\n\tif (reset) {\n\t\tfor (i = 0; i < 2; i++)\n\t\t\tiqk_info->iqk_channel[i] = 0x0;\n\t} else {\n\t\tiqk_info->rf_reg18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK);\n\n\t\tfor (i = 0; i < 2; i++) {\n\t\t\tif (iqk_info->rf_reg18 == iqk_info->iqk_channel[i]) {\n\t\t\t\t_iqk_reload_iqk_setting_8822c(dm, i, 2);\n\t\t\t\t_iqk_fill_iqk_report_8822c(dm, i);\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]reload IQK result before!!!!\\n\");\n\t\t\t\tiqk_info->is_reload = true;\n\t\t\t}\n\t\t}\n\t}\n\t/*report*/\n\todm_set_bb_reg(dm, R_0x1bf0, BIT(16), (u8)iqk_info->is_reload);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, BIT(4), 0x0);\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0xdf, BIT(4), 0x0);\n\treturn iqk_info->is_reload;\n}\n\nvoid _iqk_rfe_setting_8822c(\n\tstruct dm_struct *dm,\n\tboolean ext_pa_on)\n{\n\t/*TBD*/\n\treturn;\n#if 0\n\tif (ext_pa_on) {\n\t\t/*RFE setting*/\n\t\todm_write_4byte(dm, 0xcb0, 0x77777777);\n\t\todm_write_4byte(dm, 0xcb4, 0x00007777);\n\t\todm_write_4byte(dm, 0xcbc, 0x0000083B);\n\t\todm_write_4byte(dm, 0xeb0, 0x77777777);\n\t\todm_write_4byte(dm, 0xeb4, 0x00007777);\n\t\todm_write_4byte(dm, 0xebc, 0x0000083B);\n\t\t/*odm_write_4byte(dm, 0x1990, 0x00000c30);*/\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]external PA on!!!!\\n\");\n\t} else {\n\t\t/*RFE setting*/\n\t\todm_write_4byte(dm, 0xcb0, 0x77777777);\n\t\todm_write_4byte(dm, 0xcb4, 0x00007777);\n\t\todm_write_4byte(dm, 0xcbc, 0x00000100);\n\t\todm_write_4byte(dm, 0xeb0, 0x77777777);\n\t\todm_write_4byte(dm, 0xeb4, 0x00007777);\n\t\todm_write_4byte(dm, 0xebc, 0x00000100);\n\t\t/*odm_write_4byte(dm, 0x1990, 0x00000c30);*/\n\t\t/*RF_DBG(dm, DBG_RF_IQK, \"[IQK]external PA off!!!!\\n\");*/\n\t}\n#endif\n}\n\nvoid _iqk_setrf_bypath_8822c(\n\tstruct dm_struct *dm)\n{\n\tu8 path;\n\tu32 tmp;\n\n\t/*TBD*/\n}\nvoid _iqk_rf_direct_access_8822c(\n\tstruct dm_struct *dm,\n\tu8 path,\n\tboolean direct_access)\n{\n\tif(!direct_access) {//PI\t\n\t\tif ((enum rf_path)path == RF_PATH_A)\n\t\t\todm_set_bb_reg(dm, 0x1c, BIT(31) | BIT(30), 0x0);\n\t\telse if((enum rf_path)path == RF_PATH_B)\n\t\t\todm_set_bb_reg(dm, 0xec, BIT(31) | BIT(30), 0x0);\n\t\t//odm_set_bb_reg(dm, 0x1c, BIT(31) | BIT(30), 0x0);\t\n\t\t//odm_set_bb_reg(dm, 0xec, BIT(31) | BIT(30), 0x0);\n\t} else {//direct access\n\t\tif ((enum rf_path)path == RF_PATH_A)\n\t\t\todm_set_bb_reg(dm, 0x1c, BIT(31) | BIT(30), 0x2);\n\t\telse if((enum rf_path)path == RF_PATH_B)\n\t\t\todm_set_bb_reg(dm, 0xec, BIT(31) | BIT(30), 0x2);\n\t\t//odm_set_bb_reg(dm, 0x1c, BIT(31) | BIT(30), 0x2);\n\t\t//odm_set_bb_reg(dm, 0xec, BIT(31) | BIT(30), 0x2);\n\t}\n\t/*\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]0x1c = 0x%x, 0xec = 0x%x\\n\",\n\t       odm_read_4byte(dm, 0x1c), odm_read_4byte(dm, 0xec));\n\t*/\n}\n\nvoid _iqk_bbtx_path_8822c(\n\tstruct dm_struct *dm,\n\tu8 path)\n{\n\tu32 temp1 = 0, temp2 = 0;\n\n\tswitch (path) {\n\tcase RF_PATH_A:\n\t\ttemp1 = 0x11111111;\n\t\ttemp2 = 0x1;\n\t\tbreak;\n\tcase RF_PATH_B:\n\t\ttemp1 = 0x22222222;\n\t\ttemp2 = 0x2;\n\t\tbreak;\n\t}\n\todm_write_4byte(dm, 0x820, temp1);\n\todm_set_bb_reg(dm, 0x824, 0xf0000, temp2);\n}\n\nvoid _iqk_iqk_mode_8822c(\n\tstruct dm_struct *dm,\n\tboolean is_iqkmode)\n{\n\tu32 temp1, temp2;\n\t/*RF can't be write in iqk mode*/\n\t/*page 1b can't */\n\tif (is_iqkmode)\n\t\todm_set_bb_reg(dm, 0x1cd0, BIT(31), 0x1);\n\telse\n\t\todm_set_bb_reg(dm, 0x1cd0, BIT(31), 0x0);\t\n}\n\nvoid _iqk_macbb_8822c(\n\tstruct dm_struct *dm)\n{\n\t/*MACBB register setting*/\n\todm_write_1byte(dm, REG_TXPAUSE, 0xff);\n\t//0x73[2] = 1 (PTA control path is at WLAN)\n\todm_set_bb_reg(dm, 0x70, 0xff000000, 0x06);\n\t/*BB CCA off*/\n\t//odm_set_bb_reg(dm, 0x1c68, BIT(27) | BIT(26) | BIT(25) | BIT(24), 0xf);\n\t//odm_set_bb_reg(dm, 0x1d58, 0xff8, 0x1ff);\n\t//odm_set_bb_reg(dm, 0x1c68, 0xff8, 0x1ff);\n\t/*tx go throughput IQK*/\n\todm_set_bb_reg(dm, 0x1e24, BIT(17), 0x1);\n\t/*enable IQK block*/\n\todm_set_bb_reg(dm, 0x1cd0, BIT(30) | BIT(29) | BIT(28), 0x7);\t\n\t/*enable IQK loop back in BB*/\n\todm_set_bb_reg(dm, 0x1d60, BIT(31), 0x1);\n\t/*ADDA FIFO reset*/\n\todm_write_4byte(dm, 0x1c38, 0xffffffff);\n\t/*CCK off*/\n\t//odm_set_bb_reg(dm, 0x1c3c, BIT(0), 0x0);\n\t//odm_set_bb_reg(dm, 0x1c3c, BIT(1), 0x0);\n\todm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);\n\n\t/*r_iqk_dpk_clock_src*/\n\t//odm_set_bb_reg(dm, R_0x1cd0, 0xf0000000, 0x7);\n\n\t/*rx path on*/\n\todm_set_bb_reg(dm, 0x824, 0x30000, 0x3);\n\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]_iqk_macbb_8822c!!!!\\n\");\n}\n\nvoid _iqk_lok_setting_8822c(\n\tstruct dm_struct *dm,\n\tu8 path,\n\tu8 idac_bs)\n{\n\tu32 temp;\n\t_iqk_cal_path_off_8822c(dm);\n\t//_iqk_bbtx_path_8822c(dm, path);\n\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\t\n\todm_set_bb_reg(dm, 0x1b20, BIT(31) | BIT(30), 0x0);\n\todm_set_bb_reg(dm, 0x1b20, 0x3e0, 0x12);// 12dB\n\t\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xdf, BIT(4), 0x0);\n\t// Disable bypass TXBB @ RF0x0[19:16]=0x6 and 0x7\n\todm_set_rf_reg(dm, (enum rf_path)path, 0x9e, BIT(5), 0x0);\t\t\n\todm_set_rf_reg(dm, (enum rf_path)path, 0x9e, BIT(10), 0x0);\n\n\t\n\t//LOK_RES Table\n\tif (*dm->band_type == ODM_BAND_2_4G) {\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, 0x887);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(2), 0x1);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x18, BIT(16), 0x0);\n\t\t//odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, BIT(0), 0x0);\t\t\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x08, 0x70, idac_bs);\t\t\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(2), 0x0);\t\t\n\t} else {\t\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, 0x868);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(2), 0x1);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x18, BIT(16), 0x1);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, BIT(0), 0x0);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x08, 0x70, idac_bs);\t\t\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(2), 0x0);\n\t}\t\n\todm_set_rf_reg(dm, (enum rf_path)path, 0x57, BIT(0), 0x0);\n\n//TX_LOK\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x1);\n\tif (*dm->band_type == ODM_BAND_2_4G) {\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, 0x7f, 0x00);\n\t\todm_write_1byte(dm, 0x1bcc, 0x09);\t\t\n\t\todm_set_bb_reg(dm, 0x1b2c, 0xfff, 0x38);\n\t} else {\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, 0x7f, 0x20);\n\t\todm_write_1byte(dm, 0x1bcc, 0x09);\n\t\todm_set_bb_reg(dm, 0x1b2c, 0xfff, 0x38);\n\t}\n\todm_write_1byte(dm, 0x1b10, 0x0);\n}\n\nvoid _iqk_reload_lok_setting_8822c(\n\tstruct dm_struct *dm,\n\tu8 path)\n{\n#if 1\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tu32 tmp;\n\tu8 idac_i, idac_q;\n\tu8 i;\n\n\tidac_i = (u8)((iqk_info->rf_reg58 & 0xfc000) >> 14);\n\tidac_q = (u8)((iqk_info->rf_reg58 & 0x3f00) >> 8);\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xdf, BIT(4), 0x0);//W LOK table\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x1);\n\n\tif (*dm->band_type == ODM_BAND_2_4G)\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, 0x7f, 0x00);\n\telse\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, 0x7f, 0x20);\n\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x08, 0xfc000, idac_i);\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x08, 0x003f0, idac_q);\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x0);// stop write\n\t\n\ttmp = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, 0xfffff);\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S%d,reload 0x58 = 0x%x\\n\", path, tmp);\n#endif\n}\n\nvoid _iqk_txk_setting_8822c(\n\tstruct dm_struct *dm,\n\tu8 path)\n{\n\tu32 rf_reg64 = 0x0;\n\tu32 curr_thermal = 0x0, ee_thermal = 0x0;\n\tu32 rf_0x56 = 0x0;\n\tboolean flag = false;\n\tu8 threshold = 0x10;\n\t//_iqk_bbtx_path_8822c(dm, path);\n\t//_iqk_cal_path_off_8822c(dm);\n\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\t\n\todm_set_bb_reg(dm, 0x1bb8, BIT(20), 0x0);\n\todm_write_4byte(dm, 0x1b20, 0x00040008);\n\t//odm_write_4byte(dm, 0x1bd8, 0x0);\n\n\tpath = (enum rf_path)path;\n\tif (*dm->band_type == ODM_BAND_2_4G) {\n\t\trf_0x56 = 0x887;\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, rf_0x56);\n\t\todm_write_1byte(dm, 0x1bcc, 0x09);\n\t\todm_write_1byte(dm, 0x1b2c, 0x38);\n\t} else {\n\t\trf_0x56 = 0x8c6;\n#if 1\n\t\t//TANK \n\t\trf_reg64 = odm_get_rf_reg(dm, path, RF_0x64, MASK20BITS);\n\t\trf_reg64 = (rf_reg64 & 0xfff0f) | 0x010;\n\t\todm_set_rf_reg(dm, path, RF_0xdf, BIT(6), 0x1);\n\t\todm_set_rf_reg(dm, path, RF_0x64, MASK20BITS, rf_reg64);\n#endif\n#if 1\n\t\t/*get thermal meter*/\n\t\tee_thermal = _iqk_get_efuse_thermal_8822c(dm, path);\n\t\todm_set_rf_reg(dm, path, 0x42, BIT(17) | BIT(16), 0x3);\n\t\tODM_delay_us(50);\n\t\tODM_delay_us(50);\n\t\tcurr_thermal = (u8)odm_get_rf_reg(dm, path, 0x42, 0xfc00);\n\t\tif (ee_thermal > curr_thermal)\n\t\t\tflag = ee_thermal - curr_thermal > threshold ? true : false;\n\t\tif (flag)\n\t\t\trf_0x56 = 0x886;\n\t\todm_set_rf_reg(dm, path, RF_0x56, 0xfff, rf_0x56);\n#endif\n\t\todm_write_1byte(dm, 0x1bcc, 0x09);\t\n\t\todm_write_1byte(dm, 0x1b2c, 0x38);\n\t}\n}\n\nvoid _iqk_lok_for_rxk_setting_8822c(\n\tstruct dm_struct *dm,\n\tu8 path)\n{\n\t_iqk_cal_path_off_8822c(dm);\n\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n\todm_set_bb_reg(dm, 0x1bb8, BIT(20), 0x0);\t\n\todm_set_bb_reg(dm, 0x1b20, BIT(31) | BIT(30), 0x0);\n\t//odm_write_4byte(dm, 0x1bd8, 0x0);\n\n\n\t//LOK_RES Table\n\tif (*dm->band_type == ODM_BAND_2_4G) {\n\t\todm_set_rf_reg(dm, (enum rf_path)path, 0x00, 0xf0000, 0x7);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, 0x9e, BIT(5), 0x1);\t\t\n\t\todm_set_rf_reg(dm, (enum rf_path)path, 0x9e, BIT(10), 0x1);\n\t\todm_set_bb_reg(dm, 0x1b20, 0x3e0, 0x12);// 12dB\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, 020);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(2), 0x1);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x18, BIT(16), 0x0);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, BIT(0), 0x0);\t\t\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x08, 0x70, 0x4);\t\t\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(2), 0x0);\t\t\n\t} else {\n\t\todm_set_rf_reg(dm, (enum rf_path)path, 0x00, 0xf0000, 0x7);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, 0x9e, BIT(5), 0x1);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, 0x9e, BIT(10), 0x1);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, 0x000);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(2), 0x1);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x18, BIT(16), 0x1);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, BIT(0), 0x1);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x08, 0x70, 0x4);\t\t\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(2), 0x0);\n\t}\t\n\t\todm_set_rf_reg(dm, (enum rf_path)path, 0x57, BIT(0), 0x0);\n\t\n\t//TX_LOK\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x1);\n\tif (*dm->band_type == ODM_BAND_2_4G) {\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, 0x7f, 0x00);\n\t\todm_write_1byte(dm, 0x1bcc, 0x09);\t\t\n\t\todm_set_bb_reg(dm, 0x1b2c, 0xfff, 0x38);\n\t} else {\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, 0x7f, 0x20);\n\t\todm_write_1byte(dm, 0x1bcc, 0x09);\n\t\todm_set_bb_reg(dm, 0x1b2c, 0xfff, 0x38);\n\t}\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x1); //LOK _Write_en\n\todm_write_1byte(dm, 0x1b10, 0x0);\t\t\n\todm_write_1byte(dm, 0x1bcc, 0x12);\n\todm_set_bb_reg(dm, 0x1b2c, 0xfff, 0x038);\n}\n\n//static u8 wlg_lna[5] = {0x0, 0x1, 0x2, 0x3, 0x5};\n//static u8 wla_lna[5] = {0x0, 0x1, 0x3, 0x4, 0x5};\nvoid _iqk_rxk1_setting_8822c(\n\tstruct dm_struct *dm,\n\tu8 path)\n{\n\tstruct dm_iqk_info *iqk = &dm->IQK_info;\n#if 1\n\t_iqk_cal_path_off_8822c(dm);\n\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n\todm_set_bb_reg(dm, 0x1bb8, BIT(20), 0x0);\n\todm_set_bb_reg(dm, 0x1b20, BIT(31) | BIT(30), 0x0);\n\t//odm_write_4byte(dm, 0x1bd8, 0x0);\n\n\todm_set_bb_reg(dm, 0x1b20, 0x3e0, 0x12); // 12dB\n\tif (*dm->band_type == ODM_BAND_2_4G) {\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, 0x020);\n\t\todm_write_1byte(dm, 0x1b2c, 0x38);\n\t\todm_write_1byte(dm, 0x1bcc, 0x12);\n\t} else {\t\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, 0x000);\n\t\todm_write_1byte(dm, 0x1b2c, 0x38);\n\t\todm_write_1byte(dm, 0x1bcc, 0x12);\n\t}\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]Set RXK1 setting!!!!\\n\");\n#endif\n}\n\nvoid _iqk_rxk2_setting_8822c(\n\tstruct dm_struct *dm,\n\tu8 path,\n\tboolean is_gs)\n{\n\tstruct dm_iqk_info *iqk = &dm->IQK_info;\n\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n\todm_set_bb_reg(dm, 0x1b20, BIT(31) | BIT(30), 0x0);\n\t//odm_write_4byte(dm, 0x1bd8, 0x0);\n\n\tif (*dm->band_type == ODM_BAND_2_4G) {\n\t\tif (is_gs) {\n\t\t\tiqk->tmp1bcc = 0x12;\n\t\t}\t\t\n\t\todm_write_1byte(dm, 0x1bcc, iqk->tmp1bcc);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, 0x020);\n\t\todm_set_bb_reg(dm, 0x1b18, BIT(1), 0x1);\n\t\todm_write_4byte(dm, 0x1b24, 0x00071808); //LNA=0110, RXBB=00000\n\t\todm_write_1byte(dm, 0x1b10, 0x0);\t\t\n\t\todm_set_bb_reg(dm, 0x1b2c, 0xfff, 0x018);\n\t} else {\n\t\n\t\tif (is_gs) {\n\t\t\tiqk->tmp1bcc = 0x12;\n\t\t}\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xde, BIT(16), 0x1);\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x56, 0xfff, 0x000);\t\n\t\todm_write_1byte(dm, 0x1bcc, iqk->tmp1bcc);\n\t\todm_set_bb_reg(dm, 0x1b18, BIT(1), 0x1);\n\t\todm_write_4byte(dm, 0x1b24, 0x00070c08); //LNA=011\t\n\t\todm_write_1byte(dm, 0x1b10, 0x0);\n\t\todm_set_bb_reg(dm, 0x1b2c, 0xfff, 0x038);\n\t}\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]Set RXK2 0x56 = %x, 0x0 = %x, 0x1b24=%x\\n\",\n\t\todm_get_rf_reg(dm, (enum rf_path)path, 0x56, MASK20BITS),\n\t\todm_get_rf_reg(dm, (enum rf_path)path, 0x00, MASK20BITS),\n\t\todm_read_4byte(dm, 0x1b24));\n}\n\n\n\nvoid\n_iqk_set_lok_lut_8822c(\n\tstruct dm_struct *dm,\n\tu8 path)\n{\n#if 0\n\tu32 temp;\n\tu8 idac_i, idac_q;\n\tu8 i;\n\n\ttemp = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, 0xfffff);\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]setlut_0x58 = 0x%x\\n\", temp);\n\tidac_i = (u8)((temp & 0xfc000) >> 14);\n\tidac_q = (u8)((temp & 0x3f0) >> 4);\n\ttemp =  (idac_i << 6) | idac_q;\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xdf, BIT(4), 0x0);\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x1);\n\tfor (i = 0; i < 8; i++) {\n\t\ttemp = (i << 14) | (temp & 0xfff);\n\t\tif (*dm->band_type == ODM_BAND_2_4G)\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path, 0x33, 0xfffff, temp);\n\t\telse\n\t\t\todm_set_rf_reg(dm, (enum rf_path)path, 0x33, 0xfffff, 0x20 | temp);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]path =%d,0x33  = 0x%x!!!\\n\", path, temp);\n\t}\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x0);\n#endif\n}\n\nboolean\n_iqk_rx_iqk_gain_search_fail_8822c(\n\tstruct dm_struct *dm,\n\tu8 path,\n\tu8 step)\n{\n\n\n\tstruct dm_iqk_info *iqk = &dm->IQK_info;\n\tboolean fail = true, k2fail = true;\n\tu32 IQK_CMD = 0x0, rf_reg0 = 0x0, tmp = 0x0, bb_idx = 0x0;\n\tu8 IQMUX[5] = {0x9, 0x12, 0x1b, 0x24, 0x24};\n\tu8 idx;\n\n\tif (step == RXIQK1) {\n\t\tRF_DBG(dm, DBG_RF_IQK,\n\t       \t       \"[IQK]============ S%d RXIQK GainSearch ============\\n\",\n\t       \t       path);\n\t\tIQK_CMD = 0x00000208 | (1 << (path + 4));\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S%d GS%d_Trigger = 0x%x\\n\", path,\n\t       \t       step, IQK_CMD);\n\t\todm_write_4byte(dm, 0x1b00, IQK_CMD);\n\t\todm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);\n\t\tfail = _iqk_check_cal_8822c(dm, path, 0x1);\n\t} else if (step == RXIQK2) {\n\t\tfor (idx = 0; idx < 4; idx++) {\n\t\t\tif (iqk->tmp1bcc == IQMUX[idx])\n\t\t\t\tbreak;\n\t\t}\n\t\tif (idx == 4)\n\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK] rx_gs overflow\\n\");\n\n\t\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\t\n\t\todm_write_4byte(dm, 0x1bcc, iqk->tmp1bcc);\n\n\t\tIQK_CMD = 0x00000308 | (1 << (path + 4));\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S%d GS%d_Trigger = 0x%x\\n\", path,\n\t\t       step, IQK_CMD);\n\t\todm_write_4byte(dm, 0x1b00, IQK_CMD);\n\t\todm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);\n\t\tk2fail = _iqk_check_cal_8822c(dm, path, 0x1);\n\n\t\tif (k2fail == true) {\n\t\t\tiqk->tmp1bcc = IQMUX[idx++];\n\t\t\treturn true;\n\t\t}\n\n\t\trf_reg0 = odm_get_rf_reg(dm, (enum rf_path)path,\n\t\t\t\t\t RF_0x0, MASK20BITS);\n\t\todm_write_4byte(dm, 0x1b00, 0x00000008 | path << 1);\n\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t       \"[IQK]S%d (0) RF0x0=0x%x tmp1bcc=0x%x idx=%d 0x1b3c=0x%x\\n\",\n\t\t       path, rf_reg0, iqk->tmp1bcc, idx,\n\t\t       odm_read_4byte(dm, 0x1b3c));\n\t\t\n\t\ttmp = (rf_reg0 & 0x1fe0) >> 5;\n\t\tiqk->lna_idx = tmp >> 5; // lna value\n\t\tbb_idx = tmp & 0x1f;\n\t\tif (bb_idx <= 0x1) {\n\t\t\tif (idx != 3)\n\t\t\t\tidx++;\n\t\t\telse\n\t\t\t\tiqk->isbnd = true;\n\t\t\tfail = true;\n\t\t} else if (bb_idx >= 0xa) {\n\t\t\tif (idx != 0)\n\t\t\t\tidx--;\n\t\t\telse\n\t\t\t\tiqk->isbnd = true;\n\t\t\tfail = true;\n\t\t} else {\n\t\t\tfail = false;\n\t\t\tiqk->isbnd = false;\n\t\t}\n\t\t\n\t\tif (iqk->isbnd)\n\t\t\tfail = false;\n\t\t\n\t\tiqk->tmp1bcc = IQMUX[idx];\n\n\t\tif (fail == false){\n\t\t\ttmp = iqk->tmp1bcc << 8 |  bb_idx ;\n\t\t\todm_write_4byte(dm, 0x1be8, tmp);\n\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S%d 0x1be8 = %x\\n\",path, tmp);\n\t\t}\n#if 0\n\tif (bb_idx <= 0x1) {\n\t\tif (iqk->lna_idx != 0x0)\n\t\t\tiqk->lna_idx--;\n\t\telse if (idx != 3)\n\t\t\tidx++;\n\t\telse\n\t\t\tiqk->isbnd = true;\n\t\tfail = true;\n\t} else if (bb_idx >= 0xa) {\n\t\tif (idx != 0)\n\t\t\tidx--;\n\t\telse if (iqk->lna_idx != 0x7)\n\t\t\tiqk->lna_idx++;\n\t\telse\n\t\t\tiqk->isbnd = true;\n\t\tfail = true;\n\t} else {\n\t\tfail = false;\n\t}\n\n\tif (iqk->isbnd)\n\t\tfail = false;\n\n\tiqk->tmp1bcc = IQMUX[idx];\n\n\tRF_DBG(dm, DBG_RF_IQK,\n\t       \"[IQK]S%d RF0x0=0x%x, tmp1bcc=0x%x, idx=%d,lna_idx=%d,bb_idx =%d \\n\",\n\t       path, rf_reg0, iqk->tmp1bcc, idx,iqk->lna_idx, bb_idx);\n\n\tif (fail) {\n\t\todm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);\n\t\ttmp = (odm_read_4byte(dm, 0x1b24) & 0xffffe3ff) |\n\t\t\t(iqk->lna_idx << 10);\n\t\todm_write_4byte(dm, 0x1b24, tmp);\n\t}\n#endif\n}\n\t\nreturn fail;\n\n\t\n}\n\nboolean\n_lok_check_8822c(void *dm_void, u8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tu32 temp;\n\tu8 idac_i, idac_q;\n\tu8 i;\n\n\t_iqk_cal_path_off_8822c(dm);\n\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\t\n\n\ttemp = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, 0xfffff);\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK](1)setlut_0x58 = 0x%x\\n\", temp);\n\tidac_i = (u8)((temp & 0xfc000) >> 14);\n\tidac_q = (u8)((temp & 0x03f00) >> 8);\n\n\tif (idac_i <= 0x3 || idac_i >= 0x3c || idac_q <= 0x3 || idac_q >= 0x3c)\n\t\treturn false;\n\telse\n\t\treturn true;\n\n}\n\n\nboolean\n_lok_one_shot_8822c(\n\tvoid *dm_void,\n\tu8 path,\n\tboolean for_rxk)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tu8 delay_count = 0;\n\tboolean LOK_notready = false;\n\tu32 temp = 0;\n\tu32 IQK_CMD = 0x0;\n\tu8 idac_i, idac_q;\n\tu8 i = 0x0;\n\n\tif (for_rxk) {\n\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\"[IQK]======S%d LOK for RXK======\\n\", path);\n\t\tIQK_CMD = 0x8 | (1 << (4 + path)) | (path << 1);\n\t} else { \n\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\"[IQK]======S%d LOK======\\n\", path);\n\t\tIQK_CMD = 0x8 | (1 << (4 + path)) | (path << 1);\n\t}\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]LOK_Trigger = 0x%x\\n\", IQK_CMD);\n\t_iqk_set_gnt_wl_gnt_bt_8822c(dm, true);\n\t_iqk_rf_direct_access_8822c(dm, (enum rf_path)path, false);\n\todm_write_4byte(dm, 0x1b00, IQK_CMD);\n\todm_write_4byte(dm, 0x1b00, IQK_CMD + 1);\t\n\tfor(i =0;i < 20; i++)\n\t\tODM_delay_us(50);\n\t_iqk_rf_direct_access_8822c(dm, (enum rf_path)path, true);\n\t/*LOK: CMD ID = 0\t{0xf8000018, 0xf8000028}*/\n\t/*LOK: CMD ID = 0\t{0xf8000019, 0xf8000029}*/\n\n\t// idx of LOK LUT table, EF[4]:WE_LUT_TX_LOK\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x0);\n\n\tLOK_notready = _iqk_check_cal_8822c(dm, path, 0x0);\n#if 1\n\tif (path == RF_PATH_B)\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x00, 0xf0000, 0x1);\n#endif\n\n\t_iqk_set_gnt_wl_gnt_bt_8822c(dm, false);\n\tif(!for_rxk)\n\t\tiqk_info->rf_reg58 = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, 0xfffff);\n\n\tif (!LOK_notready) {\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]0x58 = 0x%x\\n\",\n\t\t       odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, 0xfffff));\n\t\t_iqk_backup_iqk_8822c(dm, 0x1, path);\n\t} else\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]==>S%d LOK Fail!!!\\n\", path);\n\tiqk_info->lok_fail[path] = LOK_notready;\n\treturn LOK_notready;\n}\n\nboolean\n_iqk_one_shot_8822c(\n\tvoid *dm_void,\n\tu8 path,\n\tu8 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tboolean notready = true, fail = true;\n\tu32 iqk_cmd = 0x0 , temp = 0x0;\n\n\tif (idx == TXIQK)\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]============ S%d WBTXIQK ============\\n\", path);\n\telse if (idx == RXIQK1)\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]============ S%d WBRXIQK STEP1============\\n\", path);\n\telse\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]============ S%d WBRXIQK STEP2============\\n\", path);\n\n\tif (idx == TXIQK) {\n\t\t//temp = ((*dm->band_width + 4) << 8) | (1 << (path + 4)) | (path << 1);\t\t\n\t\ttemp = ((*dm->band_width + 4) << 8) | (1 << (path + 4)) | (path << 1);\n\t\tiqk_cmd = 0x8 | temp;\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]TXK_Trigger = 0x%x\\n\", iqk_cmd);\n\t\t/*{0xf8000418, 0xf800042a} ==> 20 WBTXK (CMD = 3)*/\n\t\t/*{0xf8000518, 0xf800052a} ==> 40 WBTXK (CMD = 4)*/\n\t\t/*{0xf8000618, 0xf800062a} ==> 80 WBTXK (CMD = 5)*/\n\t} else if (idx == RXIQK1) {\n\t\ttemp = ((*dm->band_width + 7) << 8) | (1 << (path + 4)) | (path << 1);\t\t\n\t\tiqk_cmd = 0x8 | temp;\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]RXK1_Trigger = 0x%x\\n\", iqk_cmd);\n\t\t/*{0xf8000718, 0xf8000718} ==> 20 WBTXK (CMD = 7)*/\n\t\t/*{0xf8000718, 0xf8000818} ==> 40 WBTXK (CMD = 8)*/\n\t\t/*{0xf8000818, 0xf8000918} ==> 80 WBTXK (CMD = 9)*/\n\t} else if (idx == RXIQK2) {\n\t\ttemp = ((*dm->band_width + 0xa) << 8) | (1 << (path + 4)) | (path << 1);\n\t\tiqk_cmd = 0x8 | temp;\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]RXK2_Trigger = 0x%x\\n\", iqk_cmd);\n\t\t/*{0xf8000918, 0xf8000a18} ==> 20 WBRXK (CMD = a)*/\n\t\t/*{0xf8000a18, 0xf8000b18} ==> 40 WBRXK (CMD = b)*/\n\t\t/*{0xf8000b18, 0xf8000c18} ==> 80 WBRXK (CMD = c)*/\n//\t\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n//\t\todm_write_4byte(dm, 0x1b24, (odm_read_4byte(dm, 0x1b24) & 0xffffe3ff) | ((iqk_info->lna_idx & 0x7) << 10));\n\t}\n\tif (rf->rf_dbg_comp & DBG_RF_IQK) {\n\t\tif (idx != TXIQK) {\n\t\t\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]0x1bcc =0x%x\\n\", odm_read_1byte(dm, 0x1bcc));\n\t\t}\n\t}\n\t_iqk_set_gnt_wl_gnt_bt_8822c(dm, true);\n\todm_write_4byte(dm, 0x1b00, iqk_cmd);\n\todm_write_4byte(dm, 0x1b00, iqk_cmd + 0x1);\n\tfail = _iqk_check_cal_8822c(dm, path, 0x1);\n#if 1\n\tif (path == RF_PATH_B)\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x00, 0xf0000, 0x1);\n#endif\n\t_iqk_set_gnt_wl_gnt_bt_8822c(dm, false);\n/*\n\tif (rf->rf_dbg_comp & DBG_RF_IQK) {\n\t\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]0x1b00 = 0x%x, 0x1b08 = 0x%x\\n\", odm_read_4byte(dm, 0x1b00), odm_read_4byte(dm, 0x1b08));\n\t\tif (idx != TXIQK) {\n\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]RF0x0 = 0x%x, RF0x56 = 0x%x\\n\",\n\t\t\t\todm_get_rf_reg(dm, (enum rf_path)path, RF_0x0, RFREGOFFSETMASK),\n\t\t\t\todm_get_rf_reg(dm, (enum rf_path)path, RF_0x56, RFREGOFFSETMASK));\n\t\t}\n\t}\n\n\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n*/\n\n\tif (idx == TXIQK) {\n\t\tiqk_info->iqk_fail_report[0][path][TXIQK] = fail;\n\t\tif (!fail)\n\t\t\t_iqk_backup_iqk_8822c(dm, 0x2, path);\n\t}\n\tif (idx == RXIQK2) {\n\t\ttemp = odm_get_rf_reg(dm,(enum rf_path)path, RF_0x0, MASK20BITS) >> 5;\n\t\ttemp = temp & 0xff;\n\t\ttemp = temp | (iqk_info->tmp1bcc << 8);\n\t\tiqk_info->rxiqk_agc[0][path] = (u16)temp;\n\t\tiqk_info->iqk_fail_report[0][path][RXIQK] = fail;\n\t\tif (!fail)\n\t\t\t_iqk_backup_iqk_8822c(dm, 0x3, path);\n\t}\n#if 0\n\tif (fail) {\n\t\tif (idx == TXIQK)\n\t\t\tiqk_clean_cfir_8822c(dm, TXIQK, path);\n\t\telse if (idx == RXIQK2)\n\t\t\tiqk_clean_cfir_8822c(dm, RXIQK, path);\n\t}\n\tif (idx == TXIQK)\n\t\tiqk_info->iqk_fail_report[0][path][TXIQK] = fail;\n\telse\n\t\tiqk_info->iqk_fail_report[0][path][RXIQK] = fail;\n#endif\n\n\treturn fail;\n}\n\nboolean\n_iqk_rx_iqk_by_path_8822c(\n\tvoid *dm_void,\n\tu8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tboolean KFAIL = false, gonext;\n\tu32 tmp;\n\nRF_DBG(dm, DBG_RF_IQK, \"[IQK]rx_iqk_step = 0x%x\\n\", iqk_info->rxiqk_step);\n\n#if 1\n\tswitch (iqk_info->rxiqk_step) {\n\tcase 0: //LOK for RXK \n#if 1\n\t\t_iqk_lok_for_rxk_setting_8822c(dm, path);\n\t\t_lok_one_shot_8822c(dm, path, true);\n#endif\n\t\tiqk_info->rxiqk_step++;\n\t\tbreak;\n\tcase 1: /*gain search_RXK1*/\n#if 0\n\t\t_iqk_rxk1_setting_8822c(dm, path);\n\t\tgonext = false;\n\t\twhile (1) {\n\t\t\tKFAIL = _iqk_rx_iqk_gain_search_fail_8822c(dm, path, RXIQK1);\n\t\t\tif (KFAIL && iqk_info->gs_retry_count[0][path][0] < 2)\n\t\t\t\tiqk_info->gs_retry_count[0][path][0]++;\n\t\t\telse if (KFAIL) {\n\t\t\t\tiqk_info->rxiqk_fail_code[0][path] = 0;\n\t\t\t\tiqk_info->rxiqk_step = RXK_STEP_8822C;\n\t\t\t\tgonext = true;\n\t\t\t} else {\n\t\t\t\tiqk_info->rxiqk_step++;\n\t\t\t\tgonext = true;\n\t\t\t}\n\t\t\tif (gonext)\n\t\t\t\tbreak;\n\t\t}\n\t\t//halrf_iqk_xym_read(dm, path, 0x2);\n#else\n\t\tiqk_info->rxiqk_step++;\n#endif\n\t\tbreak;\n\tcase 2: /*RXK1*/\n#if 1\n\t\t_iqk_rxk1_setting_8822c(dm, path);\n\t\tgonext = false;\n\t\twhile (1) {\n\t\t\tKFAIL = _iqk_one_shot_8822c(dm, path, RXIQK1);\t\t\t\n\t\t\tif (KFAIL && iqk_info->retry_count[0][path][RXIQK1] < 2)\n\t\t\t\tiqk_info->retry_count[0][path][RXIQK1]++;\n\t\t\telse if (KFAIL) {\n\t\t\t\tiqk_info->rxiqk_fail_code[0][path] = 1;\n\t\t\t\tiqk_info->rxiqk_step = RXK_STEP_8822C;\n\t\t\t\tgonext = true;\n\t\t\t} else {\n\t\t\t\tiqk_info->rxiqk_step++;\n\t\t\t\tgonext = true;\n\t\t\t}\n\t\t\tif (gonext)\n\t\t\t\tbreak;\n\t\t}\n#else\n\t\tiqk_info->rxiqk_step++;\n#endif\n\t\t\tbreak;\n\n\tcase 3: /*gain search_RXK2*/\n#if 1\n\t\t_iqk_rxk2_setting_8822c(dm, path, true);\n\t\tiqk_info->isbnd = false;\n\t\twhile (1) {\n\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]gs2_retry = %d\\n\", iqk_info->gs_retry_count[0][path][1]);\n\t\t\tKFAIL = _iqk_rx_iqk_gain_search_fail_8822c(dm, path, RXIQK2);\n\t\t\tif (KFAIL && (iqk_info->gs_retry_count[0][path][1] < rxiqk_gs_limit))\n\t\t\t\tiqk_info->gs_retry_count[0][path][1]++;\n\t\t\telse {\n\t\t\t\tiqk_info->rxiqk_step++;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t//halrf_iqk_xym_read(dm, path, 0x3);\n#else\n\t\tiqk_info->rxiqk_step++;\n#endif\n\t\tbreak;\n\tcase 4: /*RXK2*/\n#if 1\n\t\t_iqk_rxk2_setting_8822c(dm, path, false);\n\t\tgonext = false;\n\t\twhile (1) {\n\t\t\tKFAIL = _iqk_one_shot_8822c(dm, path, RXIQK2);\t\t\t\n\t\t\tif (KFAIL && iqk_info->retry_count[0][path][RXIQK2] < 2)\n\t\t\t\tiqk_info->retry_count[0][path][RXIQK2]++;\n\t\t\telse if (KFAIL) {\n\t\t\t\tiqk_info->rxiqk_fail_code[0][path] = 2;\n\t\t\t\tiqk_info->rxiqk_step = RXK_STEP_8822C;\n\t\t\t\tgonext = true;\n\t\t\t} else {\n\t\t\t\tiqk_info->rxiqk_step++;\n\t\t\t\tgonext = true;\n\t\t\t}\n\t\t\tif (gonext)\n\t\t\t\tbreak;\n\t\t}\n#else\n\tiqk_info->rxiqk_step++;\n#endif\n\t\tbreak;\n\tcase 5: /*check RX XYM*/\n#if 0\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK] check RX XYM step =%d\\n\", iqk_info->rxiqk_step);\n\t\tKFAIL = _iqk_xym_read_8822c(dm, path);\n\t\tif (KFAIL)\n\t\t\tiqk_info->rxiqk_step = 0x0;\n\t\telse\n\t\t\tiqk_info->rxiqk_step++;\t\n\n\t\tiqk_info->iqk_fail_report[0][path][RXIQK] = KFAIL;\n#else\n\t\tiqk_info->rxiqk_step++;\n#endif\n\t\tbreak;\n\n\t}\n\treturn KFAIL;\n#endif\n}\n\nvoid _iqk_lok_tune_8822c(void *dm_void, u8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 idac_bs = 0x4;\n\n\twhile (1) {\n\t\t_iqk_lok_setting_8822c(dm, path, idac_bs);\n\t\t_lok_one_shot_8822c(dm, path, false);\t\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]ibs = %d\\n\", idac_bs);\n\t\tif(!_lok_check_8822c(dm, path)) {\t\n\t\t\tif(idac_bs == 0x6)\n\t\t\t\tbreak;\n\t\t\telse\n\t\t\t\tidac_bs++;\n\t\t} else {\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\nboolean\n_lok_load_default_8822c(void *dm_void, u8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tu32 temp;\n\tu8 idac_i, idac_q;\n\tu8 i;\n\n\t_iqk_cal_path_off_8822c(dm);\n\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\t\n\n\ttemp = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, 0xfffff);\n\t//RF_DBG(dm, DBG_RF_IQK, \"[IQK](1)setlut_0x58 = 0x%x\\n\", temp);\n\tidac_i = (u8)((temp & 0xfc000) >> 14);\n\tidac_q = (u8)((temp & 0x3f00) >> 8);\n\n\tif (!(idac_i == 0x0 || idac_i == 0x3f || idac_q == 0x0 || idac_q == 0x3f)) {\t\t\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]LOK 0x58 = 0x%x\\n\", temp);\n\t\treturn false;\n\t}\n\n\tidac_i = 0x20;\n\tidac_q = 0x20;\n\n\todm_set_rf_reg(dm, (enum rf_path)path, 0x57, BIT(0), 0x0);\t\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x1);\n\n\tif (*dm->band_type == ODM_BAND_2_4G)\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, 0x7f, 0x0);\n\telse\n\t\todm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, 0x7f, 0x20);\n\n\t//_iqk_rf_direct_access_8822c(dm, (enum rf_path)path, false);\n\n\todm_set_rf_reg(dm, (enum rf_path)path, 0x08, 0x003f0, idac_i);\n\todm_set_rf_reg(dm, (enum rf_path)path, 0x08, 0xfc000, idac_q);\n\t\n\ttemp = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x08, 0xfffff);\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK](2)setlut_0x08 = 0x%x\\n\", temp);\n\t\n\ttemp = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, 0xfffff);\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK](2)setlut_0x58 = 0x%x\\n\", temp);\n\n\t//_iqk_rf_direct_access_8822c(dm, (enum rf_path)path, true);\n\t\n\todm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(4), 0x0);\n\n\treturn true;\n\n}\n\nvoid _iqk_iqk_by_path_8822c(\n\tvoid *dm_void,\n\tboolean segment_iqk)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tboolean KFAIL = true;\n\tu8 i= 0x0, kcount_limit, path;\n\tu32 counter = 0x0;\n\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]iqk_step = 0x%x\\n\", iqk_info->iqk_step);\n#if 1\n\tswitch (iqk_info->iqk_step) {\n\tcase 0: /*S0 RXIQK*/\n#if 1\n\t\tcounter = 0x0;\n\t\twhile (1) {\n\t\t\tcounter++;\n\t\t\tKFAIL = _iqk_rx_iqk_by_path_8822c(dm, RF_PATH_A);\n\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S0RXK KFail = 0x%x\\n\", KFAIL);\n\n\t\t\tif ((!KFAIL) && (iqk_info->rxiqk_step == RXK_STEP_8822C)){ //do lok\n\t\t\t\tiqk_info->iqk_step++;\n\t\t\t\tiqk_info->rxiqk_step = 0;\n\t\t\t\tif (KFAIL)\n\t\t\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S0RXK fail code: %d!!!\\n\", iqk_info->rxiqk_fail_code[0][RF_PATH_A]);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif ((counter > 60) && (iqk_info->rxiqk_step == 0x0)) { // do lok\n\t\t\t\tiqk_info->iqk_step++;\t\t\t\t\n \t\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK] counter > 10\\n\");\n\t\t\t\tbreak;\n\t\t\t} \n\t\t}\n\t\t_iqk_get_rxcfir_8822c(dm, RF_PATH_A, 0);\n\t\t_iqk_rx_cfir_8822c(dm, RF_PATH_A);\n\t\tiqk_info->kcount++;\t\t\n#else\n\t\tiqk_info->iqk_step++;\n#endif\n\t\t\t\t\tbreak;\n\n\tcase 1: /*S0 LOK*/\n#if 1\n\t\t_iqk_lok_tune_8822c(dm, RF_PATH_A);\n\t\t//if(_lok_load_default_8822c(dm, RF_PATH_A))\n\t\t//\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S1 Load LOK to default\\n\");\n\n#endif\n\t\tiqk_info->iqk_step++;\n\t\tbreak;\n\tcase 2: /*S0 TXIQK*/\n#if 1\n\t\t_iqk_txk_setting_8822c(dm, RF_PATH_A);\n\t\tKFAIL = _iqk_one_shot_8822c(dm, RF_PATH_A, TXIQK);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(4), 0x0);\n\t\tiqk_info->kcount++;\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S0TXK KFail = 0x%x\\n\", KFAIL);\n\t\tiqk_info->iqk_step++;\n\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[CC]CFIR after S0 TXIQK\\n\");\n\t\t_iqk_rx_cfir_8822c(dm, RF_PATH_A);\n\n#else\n\t\t\tiqk_info->iqk_step++;\n#endif\n\t\tbreak;\n\tcase 3: /*S1 RXIQK*/\n#if 1\n\t\tcounter = 0x0;\n\t\twhile (1) {\n\t\t\tcounter++;\n\t\t\tKFAIL = _iqk_rx_iqk_by_path_8822c(dm, RF_PATH_B);\n\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S1RXK KFail = 0x%x\\n\", KFAIL);\n\n\t\t\tif ((!KFAIL) && (iqk_info->rxiqk_step == RXK_STEP_8822C)){ //do lok\n\t\t\t\tiqk_info->iqk_step++;\n\t\t\t\tiqk_info->rxiqk_step = 0;\n\t\t\t\tif (KFAIL)\n\t\t\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S1RXK fail code: %d!!!\\n\", iqk_info->rxiqk_fail_code[0][RF_PATH_B]);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif ((counter > 60) && (iqk_info->rxiqk_step == 0x0)) { // do lok\n\t\t\t\tiqk_info->iqk_step++;\t\t\t\t\n \t\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK] counter > 10\\n\");\n\t\t\t\tbreak;\n\t\t\t} \n\t\t}\n\t\tiqk_info->kcount++;\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[CC]CFIR after S1 RXIQK\\n\");\n\t\t_iqk_get_rxcfir_8822c(dm, RF_PATH_B, 0);\n\t\t_iqk_rx_cfir_8822c(dm,RF_PATH_B);\n#else\n\t\tiqk_info->iqk_step++;\n#endif\n\t\tbreak;\n\n\tcase 4: /*S1 LOK*/\n#if 1\n\t\t_iqk_lok_tune_8822c(dm, RF_PATH_B);\n\t\t//if(_lok_load_default_8822c(dm, RF_PATH_B))\n\t\t//\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S1 Load LOK to default\\n\");\n\n#endif\n\t\tiqk_info->iqk_step++;\n\t\tbreak;\n\t\n\tcase 5: /*S1 TXIQK*/\n#if 1\n\t\t_iqk_txk_setting_8822c(dm, RF_PATH_B);\n\t\tKFAIL = _iqk_one_shot_8822c(dm, RF_PATH_B, TXIQK);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(4), 0x0);\n\t\tiqk_info->kcount++;\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]5G S1TXK KFail = 0x%x\\n\", KFAIL);\n\t\tif (KFAIL && iqk_info->retry_count[0][RF_PATH_B][TXIQK] < 3)\n\t\t\tiqk_info->retry_count[0][RF_PATH_B][TXIQK]++;\n\t\telse\n\t\t\tiqk_info->iqk_step++;\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]iqk_info->iqk_step = 0x%x\\n\", iqk_info->iqk_step);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[CC]CFIR after S1 TXIQK\\n\");\n\t\t_iqk_rx_cfir_8822c(dm, RF_PATH_B);\n#else\n\t\t\t\tiqk_info->iqk_step++;\n#endif\n\t\tbreak;\n\tcase 6: /*IDFT*/\n#if 0\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[CC]IDFT\\n\");\n\t\t_iqk_idft(dm);\n\t\tiqk_info->iqk_step++;\n#else\n\t\t\t\tiqk_info->iqk_step++;\n#endif\n\t\tbreak;\n\t}\n\n\tif (iqk_info->iqk_step == IQK_STEP_8822C) {\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]========LOK summary =========\\n\");\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S0_LOK_fail= %d, S1_LOK_fail= %d\\n\",\n\t\t       iqk_info->lok_fail[RF_PATH_A],\n\t\t       iqk_info->lok_fail[RF_PATH_B]);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]========IQK summary ==========\\n\");\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S0_TXIQK_fail = %d, S1_TXIQK_fail = %d\\n\"\n\t\t       ,iqk_info->iqk_fail_report[0][RF_PATH_A][TXIQK],\n\t\t       iqk_info->iqk_fail_report[0][RF_PATH_B][TXIQK]);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S0_RXIQK_fail= %d, S1_RXIQK_fail= %d\\n\"\n\t\t       ,iqk_info->iqk_fail_report[0][RF_PATH_A][RXIQK],\n\t\t       iqk_info->iqk_fail_report[0][RF_PATH_B][RXIQK]);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S0_TK_retry = %d, S1_TXIQK_retry = %d\\n\"\n\t\t       ,iqk_info->retry_count[0][RF_PATH_A][TXIQK],\n\t\t       iqk_info->retry_count[0][RF_PATH_B][TXIQK]);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S0_RXK1_retry = %d, S0_RXK2_retry = %d\\n\"\n\t\t       ,iqk_info->retry_count[0][RF_PATH_A][RXIQK1], \n\t\t       iqk_info->retry_count[0][RF_PATH_A][RXIQK2]);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S2_RXK1_retry = %d, S2_RXK2_retry = %d\\n\"\n\t\t       ,iqk_info->retry_count[0][RF_PATH_B][RXIQK1],\n\t\t       iqk_info->retry_count[0][RF_PATH_B][RXIQK2]);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]S0_GS1_retry = %d, S0_GS2_retry = %d, S1_GS1_retry = %d, S1_GS2_retry = %d\\n\"\n\t\t       ,iqk_info->gs_retry_count[0][RF_PATH_A][0],\n\t\t       iqk_info->gs_retry_count[0][RF_PATH_A][1],\n\t\t       iqk_info->gs_retry_count[0][RF_PATH_B][0],\n\t\t       iqk_info->gs_retry_count[0][RF_PATH_B][1]);\n\n\t\tfor (path = 0; path < SS_8822C; path++) {\n\t\t\todm_set_bb_reg(dm, 0x1b00, bMaskDWord, 0x8 | i << 1);\n\t\t\todm_set_bb_reg(dm, R_0x1b20, BIT(26), 0x1);\n\t\t\todm_set_bb_reg(dm, 0x1bcc, MASKBYTE0, 0x0);\n\t\t\todm_set_bb_reg(dm, 0x1b38, bMaskDWord, 0x40000000);\n\t\t\t// force return to rx mode\n\t\t\todm_set_bb_reg(dm, 0x1bb8, BIT(20), 0x0);\n\t\t\todm_set_rf_reg(dm, path, RF_0x0, 0xf0000, 0x3);\n\t\t}\n\n\t}\n#endif\n\n}\n\nvoid _iqk_dpd_in_sel(\n\tstruct dm_struct *dm,\n\tu8 input)\n{\n\tu8 path;\n\t/*input =1: DPD input = single tone, 0: DPD input = OFDM*/\n\tfor (path = 0; path < SS_8822C; path++) {\n\t\todm_write_4byte(dm, 0x1b00, IQK_CMD_8822C | (path << 1));\n\t\t/*dpd_in_sel*/\n\t\todm_set_bb_reg(dm, 0x1bcc, BIT(13), input);\n\t}\n\n}\n\nvoid _iqk_start_iqk_8822c(\n\tstruct dm_struct *dm,\n\tboolean segment_iqk)\n{\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tu8 i = 0;\n\tu8 kcount_limit;\n\t\n\tif (*dm->band_width == 2)\n\t\tkcount_limit = kcount_limit_80m;\n\telse\n\t\tkcount_limit = kcount_limit_others;\n\n\twhile (i <  100) {\n\t\t_iqk_iqk_by_path_8822c(dm, segment_iqk);\n\t\tif (iqk_info->iqk_step == IQK_STEP_8822C)\n\t\t\tbreak;\n\t\tif (segment_iqk && (iqk_info->kcount == kcount_limit))\n\t\t\tbreak;\n\t\ti++;\n\t}\n}\n\nvoid _iq_calibrate_8822c_init(\n\tstruct dm_struct *dm)\n{\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tu8 i, j, k, m;\n\tstatic boolean firstrun = true;\n\n\tif (firstrun) {\n\t\tfirstrun = false;\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]=====>PHY_IQCalibrate_8822c_Init\\n\");\n\n\t\tfor (i = 0; i < SS_8822C; i++) {\n\t\t\tfor (j = 0; j < 2; j++) {\n\t\t\t\tiqk_info->lok_fail[i] = true;\n\t\t\t\tiqk_info->iqk_fail[j][i] = true;\n\t\t\t\tiqk_info->iqc_matrix[j][i] = 0x20000000;\n\t\t\t}\n\t\t}\n\n\t\tfor (i = 0; i < 2; i++) {\n\t\t\tiqk_info->iqk_channel[i] = 0x0;\n\n\t\t\tfor (j = 0; j < SS_8822C; j++) {\n\t\t\t\tiqk_info->lok_idac[i][j] = 0x0;\n\t\t\t\tiqk_info->rxiqk_agc[i][j] = 0x0;\n\t\t\t\tiqk_info->bypass_iqk[i][j] = 0x0;\n\n\t\t\t\tfor (k = 0; k < 2; k++) {\n\t\t\t\t\tiqk_info->iqk_fail_report[i][j][k] = true;\n\t\t\t\t\tfor (m = 0; m <= 16; m++) {\n\t\t\t\t\t\tiqk_info->iqk_cfir_real[i][j][k][m] = 0x0;\n\t\t\t\t\t\tiqk_info->iqk_cfir_imag[i][j][k][m] = 0x0;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tfor (k = 0; k < 3; k++)\n\t\t\t\t\tiqk_info->retry_count[i][j][k] = 0x0;\n\t\t\t}\n\t\t}\n\t}\n\n}\n\nboolean\n_iqk_rximr_rxk1_test_8822c(\n\tstruct dm_struct *dm,\n\tu8 path,\n\tu32 tone_index)\n{\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tboolean fail = true;\n\tu32 IQK_CMD;\n\n\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n\todm_write_4byte(dm, 0x1b20, (odm_read_4byte(dm, 0x1b20) & 0x000fffff) | ((tone_index & 0xfff) << 20));\n\todm_write_4byte(dm, 0x1b24, (odm_read_4byte(dm, 0x1b24) & 0x000fffff) | ((tone_index & 0xfff) << 20));\n\n\tIQK_CMD = 0xf8000208 | (1 << (path + 4));\n\todm_write_4byte(dm, 0x1b00, IQK_CMD);\n\todm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);\n\n\tfail = _iqk_check_cal_8822c(dm, path, 0x1);\n\treturn fail;\n}\n\nu32 _iqk_tximr_selfcheck_8822c(\n\tvoid *dm_void,\n\tu8 tone_index,\n\tu8 path)\n{\n\tu32 tx_ini_power_H[2], tx_ini_power_L[2];\n\tu32 tmp1, tmp2, tmp3, tmp4, tmp5;\n\tu32 IQK_CMD;\n\tu32 tximr = 0x0;\n\tu8 i;\n\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\t/*backup*/\n\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n\todm_write_4byte(dm, 0x1bc8, 0x80000000);\n\todm_write_4byte(dm, 0x8f8, 0x41400080);\n\ttmp1 = odm_read_4byte(dm, 0x1b0c);\n\ttmp2 = odm_read_4byte(dm, 0x1b14);\n\ttmp3 = odm_read_4byte(dm, 0x1b1c);\n\ttmp4 = odm_read_4byte(dm, 0x1b20);\n\ttmp5 = odm_read_4byte(dm, 0x1b24);\n\t/*setup*/\n\todm_write_4byte(dm, 0x1b0c, 0x00003000);\n\todm_write_4byte(dm, 0x1b1c, 0xA2193C32);\n\todm_write_1byte(dm, 0x1b15, 0x00);\n\todm_write_4byte(dm, 0x1b20, (u32)(tone_index << 20 | 0x00040008));\n\todm_write_4byte(dm, 0x1b24, (u32)(tone_index << 20 | 0x00060008));\n\todm_write_4byte(dm, 0x1b2c, 0x07);\n\todm_write_4byte(dm, 0x1b38, 0x40000000);\n\todm_write_4byte(dm, 0x1b3c, 0x40000000);\n\t/* ======derive pwr1========*/\n\tfor (i = 0; i < 2; i++) {\n\t\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n\t\tif (i == 0)\n\t\t\todm_write_1byte(dm, 0x1bcc, 0x0f);\n\t\telse\n\t\t\todm_write_1byte(dm, 0x1bcc, 0x09);\n\t\t/* One Shot*/\n\t\tIQK_CMD = 0x00000800;\n\t\todm_write_4byte(dm, 0x1b34, IQK_CMD + 1);\n\t\todm_write_4byte(dm, 0x1b34, IQK_CMD);\n\t\tODM_delay_us(50);\n\t\todm_write_4byte(dm, 0x1bd4, 0x00040001);\n\t\ttx_ini_power_H[i] = odm_read_4byte(dm, 0x1bfc);\n\t\todm_write_4byte(dm, 0x1bd4, 0x000C0001);\n\t\ttx_ini_power_L[i] = odm_read_4byte(dm, 0x1bfc);\n\t}\n\t/*restore*/\n\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n\todm_write_4byte(dm, 0x1b0c, tmp1);\n\todm_write_4byte(dm, 0x1b14, tmp2);\n\todm_write_4byte(dm, 0x1b1c, tmp3);\n\todm_write_4byte(dm, 0x1b20, tmp4);\n\todm_write_4byte(dm, 0x1b24, tmp5);\n\n\tif (tx_ini_power_H[1] == tx_ini_power_H[0])\n\t\ttximr = (3 * (halrf_psd_log2base(tx_ini_power_L[0] << 2) - halrf_psd_log2base(tx_ini_power_L[1]))) / 100;\n\telse\n\t\ttximr = 0;\n\treturn tximr;\n}\n\nvoid _iqk_start_tximr_test_8822c(\n\tstruct dm_struct *dm,\n\tu8 imr_limit)\n{\n\tboolean KFAIL;\n\tu8 path, i, tone_index;\n\tu32 imr_result;\n\n\tfor (path = 0; path < SS_8822C; path++) {\n\t\t_iqk_txk_setting_8822c(dm, path);\n\t\tKFAIL = _iqk_one_shot_8822c(dm, path, TXIQK);\n\t\tfor (i = 0x0; i < imr_limit; i++) {\n\t\t\ttone_index = (u8)(0x08 | i << 4);\n\t\t\timr_result = _iqk_tximr_selfcheck_8822c(dm, tone_index, path);\n\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]path=%x, toneindex = %x, TXIMR = %d\\n\", path, tone_index, imr_result);\n\t\t}\n\t\tRF_DBG(dm, DBG_RF_IQK, \"\\n\");\n\t}\n}\n\nu32 _iqk_rximr_selfcheck_8822c(\n\tvoid *dm_void,\n\tu32 tone_index,\n\tu8 path,\n\tu32 tmp1b38)\n{\n\tu32 rx_ini_power_H[2], rx_ini_power_L[2]; /*[0]: psd tone; [1]: image tone*/\n\tu32 tmp1, tmp2, tmp3, tmp4, tmp5;\n\tu32 IQK_CMD, tmp1bcc;\n\tu8 i, num_k1, rximr_step, count = 0x0;\n\tu32 rximr = 0x0;\n\tboolean KFAIL = true;\n\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\t/*backup*/\n\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n\ttmp1 = odm_read_4byte(dm, 0x1b0c);\n\ttmp2 = odm_read_4byte(dm, 0x1b14);\n\ttmp3 = odm_read_4byte(dm, 0x1b1c);\n\ttmp4 = odm_read_4byte(dm, 0x1b20);\n\ttmp5 = odm_read_4byte(dm, 0x1b24);\n\n\todm_write_4byte(dm, 0x1b0c, 0x00001000);\n\todm_write_1byte(dm, 0x1b15, 0x00);\n\todm_write_4byte(dm, 0x1b1c, 0x82193d31);\n\todm_write_4byte(dm, 0x1b20, (u32)(tone_index << 20 | 0x00040008));\n\todm_write_4byte(dm, 0x1b24, (u32)(tone_index << 20 | 0x00060048));\n\todm_write_4byte(dm, 0x1b2c, 0x07);\n\todm_write_4byte(dm, 0x1b38, tmp1b38);\n\todm_write_4byte(dm, 0x1b3c, 0x40000000);\n\n\tfor (i = 0; i < 2; i++) {\n\t\tif (i == 0)\n\t\t\todm_write_4byte(dm, 0x1b1c, 0x82193d31);\n\t\telse\n\t\t\todm_write_4byte(dm, 0x1b1c, 0xa2193d31);\n\t\tIQK_CMD = 0x00000800;\n\t\todm_write_4byte(dm, 0x1b34, IQK_CMD + 1);\n\t\todm_write_4byte(dm, 0x1b34, IQK_CMD);\n\t\tODM_delay_us(200);\n\t\todm_write_1byte(dm, 0x1bd6, 0xb);\n\t\twhile (count < 100) {\n\t\t\tcount++;\n\t\t\tif (odm_get_bb_reg(dm, R_0x1bfc, BIT(1)) == 1)\n\t\t\t\tbreak;\n\t\t\telse\n\t\t\t\tODM_delay_us(50);\n\t\t}\n\t\tif (1) {\n\t\t\todm_write_1byte(dm, 0x1bd6, 0x5);\n\t\t\trx_ini_power_H[i] = odm_read_4byte(dm, 0x1bfc);\n\t\t\todm_write_1byte(dm, 0x1bd6, 0xe);\n\t\t\trx_ini_power_L[i] = odm_read_4byte(dm, 0x1bfc);\n\t\t} else {\n\t\t\trx_ini_power_H[i] = 0x0;\n\t\t\trx_ini_power_L[i] = 0x0;\n\t\t}\n\t}\n\t/*restore*/\n\todm_write_4byte(dm, 0x1b0c, tmp1);\n\todm_write_4byte(dm, 0x1b14, tmp2);\n\todm_write_4byte(dm, 0x1b1c, tmp3);\n\todm_write_4byte(dm, 0x1b20, tmp4);\n\todm_write_4byte(dm, 0x1b24, tmp5);\n\tfor (i = 0; i < 2; i++)\n\t\trx_ini_power_H[i] = (rx_ini_power_H[i] & 0xf8000000) >> 27;\n\n\tif (rx_ini_power_H[0] != rx_ini_power_H[1])\n\t\tswitch (rx_ini_power_H[0]) {\n\t\tcase 1:\n\t\t\trx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 1) | 0x80000000);\n\t\t\trx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 1;\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\trx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 2) | 0x80000000);\n\t\t\trx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 2;\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\trx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 2) | 0xc0000000);\n\t\t\trx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 2;\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\trx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0x80000000);\n\t\t\trx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3;\n\t\t\tbreak;\n\t\tcase 5:\n\t\t\trx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0xa0000000);\n\t\t\trx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3;\n\t\t\tbreak;\n\t\tcase 6:\n\t\t\trx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0xc0000000);\n\t\t\trx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3;\n\t\t\tbreak;\n\t\tcase 7:\n\t\t\trx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0xe0000000);\n\t\t\trx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\trximr = (u32)(3 * ((halrf_psd_log2base(rx_ini_power_L[0] / 100) - halrf_psd_log2base(rx_ini_power_L[1] / 100))) / 100);\n\t/*\n\t\tRF_DBG(dm, DBG_RF_IQK, \"%-20s: 0x%x, 0x%x, 0x%x, 0x%x,0x%x, tone_index=%x, rximr= %d\\n\",\n\t\t(path == 0) ? \"PATH A RXIMR \": \"PATH B RXIMR\",\n\t\trx_ini_power_H[0], rx_ini_power_L[0], rx_ini_power_H[1], rx_ini_power_L[1], tmp1bcc, tone_index, rximr);\n*/\n\treturn rximr;\n}\n\nvoid _iqk_rximr_test_8822c(\n\tstruct dm_struct *dm,\n\tu8 path,\n\tu8 imr_limit)\n{\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tboolean kfail;\n\tu8 i, step, count, side;\n\tu32 imr_result = 0, tone_index;\n\tu32 temp = 0, temp1b38[2][15];\n\tchar *freq[15] = {\"1.25MHz\", \"3.75MHz\", \"6.25MHz\", \"8.75MHz\", \"11.25MHz\",\n\t\t\t  \"13.75MHz\", \"16.25MHz\", \"18.75MHz\", \"21.25MHz\", \"23.75MHz\",\n\t\t\t  \"26.25MHz\", \"28.75MHz\", \"31.25MHz\", \"33.75MHz\", \"36.25MHz\"};\n\n\tfor (step = 1; step < 5; step++) {\n\t\tcount = 0;\n\t\tswitch (step) {\n\t\tcase 1: /*gain search_RXK1*/\n\t\t\t_iqk_rxk1_setting_8822c(dm, path);\n\t\t\twhile (count < 3) {\n\t\t\t\tkfail = _iqk_rx_iqk_gain_search_fail_8822c(dm, path, RXIQK1);\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]path = %x, kfail = %x\\n\", path, kfail);\n\t\t\t\tif (kfail) {\n\t\t\t\t\tcount++;\n\t\t\t\t\tif (count == 3)\n\t\t\t\t\t\tstep = 5;\n\t\t\t\t} else {\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 2: /*gain search_RXK2*/\n\t\t\t_iqk_rxk2_setting_8822c(dm, path, true);\n\t\t\tiqk_info->isbnd = false;\n\t\t\twhile (count < 8) {\n\t\t\t\tkfail = _iqk_rx_iqk_gain_search_fail_8822c(dm, path, RXIQK2);\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]path = %x, kfail = %x\\n\", path, kfail);\n\t\t\t\tif (kfail) {\n\t\t\t\t\tcount++;\n\t\t\t\t\tif (count == 8)\n\t\t\t\t\t\tstep = 5;\n\t\t\t\t} else {\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 3: /*get RXK1 IQC*/\n\t\t\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n\t\t\ttemp = odm_read_4byte(dm, 0x1b1c);\n\t\t\tfor (side = 0; side < 2; side++) {\n\t\t\t\tfor (i = 0; i < imr_limit; i++) {\n\t\t\t\t\tif (side == 0)\n\t\t\t\t\t\ttone_index = 0xff8 - (i << 4);\n\t\t\t\t\telse\n\t\t\t\t\t\ttone_index = 0x08 | (i << 4);\n\t\t\t\t\twhile (count < 3) {\n\t\t\t\t\t\t_iqk_rxk1_setting_8822c(dm, path);\n\t\t\t\t\t\tkfail = _iqk_rximr_rxk1_test_8822c(dm, path, tone_index);\n\t\t\t\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]path = %x, kfail = %x\\n\", path, kfail);\n\t\t\t\t\t\tif (kfail) {\n\t\t\t\t\t\t\tcount++;\n\t\t\t\t\t\t\tif (count == 3) {\n\t\t\t\t\t\t\t\tstep = 5;\n\t\t\t\t\t\t\t\ttemp1b38[side][i] = 0x20000000;\n\t\t\t\t\t\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]path = %x, toneindex = %x rxk1 fail\\n\", path, tone_index);\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n\t\t\t\t\t\t\todm_write_4byte(dm, 0x1b1c, 0xa2193c32);\n\t\t\t\t\t\t\todm_write_4byte(dm, 0x1b14, 0xe5);\n\t\t\t\t\t\t\todm_write_4byte(dm, 0x1b14, 0x0);\n\t\t\t\t\t\t\ttemp1b38[side][i] = odm_read_4byte(dm, 0x1b38);\n\t\t\t\t\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]path = 0x%x, tone_idx = 0x%x, tmp1b38 = 0x%x\\n\", path, tone_index, temp1b38[side][i]);\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 4: /*get RX IMR*/\n\t\t\tfor (side = 0; side < 2; side++) {\n\t\t\t\tfor (i = 0x0; i < imr_limit; i++) {\n\t\t\t\t\tif (side == 0)\n\t\t\t\t\t\ttone_index = 0xff8 - (i << 4);\n\t\t\t\t\telse\n\t\t\t\t\t\ttone_index = 0x08 | (i << 4);\n\t\t\t\t\t_iqk_rxk2_setting_8822c(dm, path, false);\n\t\t\t\t\timr_result = _iqk_rximr_selfcheck_8822c(dm, tone_index, path, temp1b38[side][i]);\n\t\t\t\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]tone_idx = 0x%5x, freq = %s%10s, RXIMR = %5d dB\\n\", tone_index, (side == 0) ? \"-\" : \" \", freq[i], imr_result);\n\t\t\t\t}\n\t\t\t\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n\t\t\t\todm_write_4byte(dm, 0x1b1c, temp);\n\t\t\t\todm_write_4byte(dm, 0x1b38, 0x20000000);\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\nvoid _iqk_start_rximr_test_8822c(\n\tstruct dm_struct *dm,\n\tu8 imr_limit)\n{\n\tu8 path;\n\n\tfor (path = 0; path < SS_8822C; path++)\n\t\t_iqk_rximr_test_8822c(dm, path, imr_limit);\n}\n\nvoid _iqk_start_imr_test_8822c(\n\tvoid *dm_void)\n{\n\tu8 imr_limit;\n\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tif (*dm->band_width == 2)\n\t\timr_limit = 0xf;\n\telse if (*dm->band_width == 1)\n\t\timr_limit = 0x8;\n\telse\n\t\timr_limit = 0x4;\n\t//\t_iqk_start_tximr_test_8822c(dm, imr_limit);\n\t_iqk_start_rximr_test_8822c(dm, imr_limit);\n}\n\n\n\nvoid _phy_iq_calibrate_8822c(\n\tstruct dm_struct *dm,\n\tboolean reset,\n\tboolean segment_iqk)\n{\n\tu32 MAC_backup[MAC_REG_NUM_8822C] = {0};\n\tu32 BB_backup[BB_REG_NUM_8822C] = {0};\n\tu32 RF_backup[RF_REG_NUM_8822C][SS_8822C] = {{0}};\n\tu32 backup_mac_reg[MAC_REG_NUM_8822C] = {0x520, 0x1c, 0x70};\n\tu32 backup_bb_reg[BB_REG_NUM_8822C] = {0x820, 0x824, 0x1c38, 0x1c68, 0x1d60, 0x180c, 0x410c, 0x1c3c, 0x1a14, 0x1d58, 0x1d70};\n\tu32 backup_rf_reg[RF_REG_NUM_8822C] = {0x19, 0xdf, 0x9e};\n\tboolean is_mp = false;\n\tu8 i = 0;\n\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tif (*dm->mp_mode)\n\t\tis_mp = true;\n#if 0\n\tif (!is_mp)\n\t\tif (_iqk_reload_iqk_8822c(dm, reset))\n\t\t\treturn;\n#endif\n\tiqk_info->rf_reg18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK);\n\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]==========IQK strat!!!!!==========\\n\");\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\\n\", (*dm->band_type == ODM_BAND_5G) ? \"5G\" : \"2G\", *dm->band_width, dm->ext_pa, dm->ext_pa_5g);\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]Interface = %d, Cv = %x\\n\", dm->support_interface, dm->cut_version);\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK] Test V10 \\n\");\n\tiqk_info->iqk_times++;\n\tiqk_info->kcount = 0;\n\tiqk_info->iqk_step = 0;\n\tiqk_info->rxiqk_step = 0;\n\tiqk_info->tmp_gntwl = _iqk_btc_read_indirect_reg_8822c(dm, 0x38);\n\n\t_iqk_backup_iqk_8822c(dm, 0x0, 0x0);\n\t_iqk_backup_mac_bb_8822c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg);\n\t_iqk_backup_rf_8822c(dm, RF_backup, backup_rf_reg);\n\n\twhile (i < 3) {\n\t\ti++;\n\t\t_iqk_macbb_8822c(dm);\t\t\n\t\t//odm_read_and_config_mp_8822c_cal_init(dm);\n\t\t//_iqk_rf_setting_8822c(dm);\n\t\t_iqk_bb_for_dpk_setting_8822c(dm);\n\t\t_iqk_afe_setting_8822c(dm, true);\n\t\t_iqk_rfe_setting_8822c(dm, false);\n\t\t_iqk_agc_bnd_int_8822c(dm);\n\t\t//_iqk_con_tx_8822c(dm, true);\n\t\t_iqk_start_iqk_8822c(dm, segment_iqk);\n\t\t//_iqk_con_tx_8822c(dm,false);\n\t\t_iqk_afe_setting_8822c(dm, false);\n\t\t_iqk_restore_rf_8822c(dm, backup_rf_reg, RF_backup);\n\t\t_iqk_restore_mac_bb_8822c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg);\n\t\tif (iqk_info->iqk_step == IQK_STEP_8822C)\n\t\t\tbreak;\n\t\tiqk_info->kcount = 0;\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]delay 50ms!!!\\n\");\n\t\tfor (i = 0; i<1000; i++)\n\t\t\tODM_delay_us(10);\n\n\t};\n\n\t_iqk_fill_iqk_report_8822c(dm, 0);\n\n\t/*check cfir value*/\n\t_iqk_get_rxcfir_8822c(dm, RF_PATH_A , 1);\n\t_iqk_get_rxcfir_8822c(dm, RF_PATH_B , 1);\n\t_iqk_rx_cfir_check_8822c(dm, 1);\n\n\t_iqk_rx_cfir_8822c(dm, RF_PATH_A);\n\t_iqk_rx_cfir_8822c(dm, RF_PATH_B);\n\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]==========IQK end!!!!!==========\\n\");\n}\n\nvoid _check_fwiqk_done_8822c(struct dm_struct *dm)\n{\n\tu32 counter = 0x0;\n#if 1\n\twhile (1) {\n\t\tif (odm_read_1byte(dm, 0x2d9c) == 0xaa  || counter > 3000)\n\t\t\tbreak;\n\t\tcounter++;\n\t\tODM_delay_us(50);\n\t};\n\todm_write_1byte(dm, 0x1b10, 0x0);\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]counter = %d\\n\", counter);\n#else\n\tODM_delay_ms(50);\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK] delay 50ms\\n\");\n\n#endif\n}\n\n\nvoid _phy_iq_calibrate_by_fw_8822c(\n\tvoid *dm_void,\n\tu8 clear,\n\tu8 segment_iqk)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tenum hal_status status = HAL_STATUS_FAILURE;\n\n\tif (*dm->mp_mode)\n\t\tclear = 0x1;\n\t//\telse if (dm->is_linked)\n\t//\t\tsegment_iqk = 0x1;\n\n\tiqk_info->iqk_times++;\n\tstatus = odm_iq_calibrate_by_fw(dm, clear, segment_iqk);\n\n\tif (status == HAL_STATUS_SUCCESS)\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]FWIQK OK!!!\\n\");\n\telse\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]FWIQK fail!!!\\n\");\n}\n\n/*IQK_version:0x8, NCTL:0x5*/\n/*1.max tx pause while IQK*/\n/*2.CCK off while IQK*/\nvoid phy_iq_calibrate_8822c(\n\tvoid *dm_void,\n\tboolean clear,\n\tboolean segment_iqk)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\n\tif (!(rf->rf_supportability & HAL_RF_IQK))\n\t\treturn;\n\n\tif (dm->mp_mode)\t\n\t\tif (*dm->mp_mode)\n\t\thalrf_iqk_hwtx_check(dm, true);\n\t\n\t//if (!(*dm->mp_mode))\n\t//\t_iqk_check_coex_status(dm, true);\n\n\tdm->rf_calibrate_info.is_iqk_in_progress = true;\n\n\t/*FW IQK*/\n\t\n\tif (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) {\n\t\t_phy_iq_calibrate_by_fw_8822c(dm, clear, (u8)(segment_iqk));\n\t\t_check_fwiqk_done_8822c(dm);\n\t\t_iqk_check_if_reload(dm);\n\t\tRF_DBG(dm, DBG_RF_IQK, \"!!!!!  FW IQK   !!!!!\\n\");\n\t} else {\n\t\t_iq_calibrate_8822c_init(dm);\n\t\t_phy_iq_calibrate_8822c(dm, clear, segment_iqk);\n\t}\n\t_iqk_fail_count_8822c(dm);\n\tif (dm->mp_mode)\t\n\t\tif (*dm->mp_mode)\n\t\t\thalrf_iqk_hwtx_check(dm, false);\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\t_iqk_iqk_fail_report_8822c(dm);\n#endif\n\thalrf_iqk_dbg(dm);\n\n\tdm->rf_calibrate_info.is_iqk_in_progress = false;\n\n}\n\nvoid _phy_imr_measure_8822c(\n\tstruct dm_struct *dm)\n{\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tu32 MAC_backup[MAC_REG_NUM_8822C] = {0};\n\tu32 BB_backup[BB_REG_NUM_8822C] = {0};\n\tu32 RF_backup[RF_REG_NUM_8822C][SS_8822C] = {{0}};\n\tu32 backup_mac_reg[MAC_REG_NUM_8822C] = {0x520, 0x1c, 0x70};\n\tu32 backup_bb_reg[BB_REG_NUM_8822C] = {0x820, 0x824, 0x1c38, 0x1c68, 0x1d60, 0x180c, 0x410c, 0x1c3c, 0x1a14, 0x1d58, 0x1d70};\n\tu32 backup_rf_reg[RF_REG_NUM_8822C] = {0x19, 0xdf, 0x9e};\n\n\t_iqk_backup_iqk_8822c(dm, 0x0, 0x0);\n\t_iqk_backup_mac_bb_8822c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg);\n\t_iqk_backup_rf_8822c(dm, RF_backup, backup_rf_reg);\n\t_iqk_macbb_8822c(dm);\n\t_iqk_afe_setting_8822c(dm, true);\n\t_iqk_rfe_setting_8822c(dm, false);\n//\t_iqk_agc_bnd_int_8822c(dm);\n//\t_iqk_rf_setting_8822c(dm);\n\t_iqk_start_imr_test_8822c(dm);\n\t_iqk_afe_setting_8822c(dm, false);\n\t_iqk_restore_mac_bb_8822c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg);\n\t_iqk_restore_rf_8822c(dm, backup_rf_reg, RF_backup);\n}\n\nvoid do_imr_test_8822c(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]  ************IMR Test *****************\\n\");\n\t_phy_imr_measure_8822c(dm);\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]  **********End IMR Test *******************\\n\");\n}\nvoid do_lok_8822c(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\t\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\t\n\tu32 MAC_backup[MAC_REG_NUM_8822C] = {0};\n\tu32 BB_backup[BB_REG_NUM_8822C] = {0};\n\tu32 RF_backup[RF_REG_NUM_8822C][SS_8822C] = {{0}};\n\tu32 backup_mac_reg[MAC_REG_NUM_8822C] = {0x520, 0x1c};\n\tu32 backup_bb_reg[BB_REG_NUM_8822C] = {0x820, 0x824, 0x1c38, 0x1c68, 0x1d60, 0x180c, 0x410c, 0x1c3c, 0x1a14, 0x1d58, 0x1d70};\n\tu32 backup_rf_reg[RF_REG_NUM_8822C] = {0x19, 0xdf, 0x9e};\n\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]  ************do Lok *****************\\n\");\n\t_iqk_macbb_8822c(dm);\t\t\n\t_iqk_rf_setting_8822c(dm);\n\t_iqk_bb_for_dpk_setting_8822c(dm);\n\t_iqk_afe_setting_8822c(dm, true);\n\t_iqk_rfe_setting_8822c(dm, false);\n\t_iqk_agc_bnd_int_8822c(dm);\n\n\t_iqk_lok_setting_8822c(dm, RF_PATH_A, 0x4);\n\t_lok_one_shot_8822c(dm, RF_PATH_A, false);\n\n\t_iqk_lok_setting_8822c(dm, RF_PATH_B, 0x4);\n\t_lok_one_shot_8822c(dm, RF_PATH_B, false);\n\n\t_iqk_afe_setting_8822c(dm, false);\n\t_iqk_restore_mac_bb_8822c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg);\n\t_iqk_restore_rf_8822c(dm, backup_rf_reg, RF_backup);\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]  **********End Do Lok *******************\\n\");\n}\n\n\nvoid iqk_reload_iqk_8822c(void *dm_void, boolean reset)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\t_iqk_reload_iqk_8822c(dm, reset);\n\n}\n\nvoid iqk_get_cfir_8822c(void *dm_void, u8 idx, u8 path, boolean debug)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tu8 i, ch;\n\tu32 tmp;\n\tu32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);\n\n\tif (debug)\n\t\tch = 2;\n\telse\n\t\tch = 0;\n\n\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n\n\tfor (i = 0; i <  0x100/4; i++)\n\t\tRF_DBG(dm, DBG_RF_DPK, \"[IQK] (1) 1b%x = 0x%x\\n\",\n\t\t       i*4, odm_read_4byte(dm, (0x1b00 + i*4)));\n\n\tif (idx == TX_IQK) {//TXCFIR\n\t\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x3);\n\t} else {//RXCFIR\n\t\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);\t\t\n\t}\n\todm_set_bb_reg(dm, R_0x1bd4, BIT(21), 0x1);\n\todm_set_bb_reg(dm, R_0x1bd4, bit_mask_20_16, 0x10);\n\tfor (i = 0; i <= 16; i++) {\n\t\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001 | i << 2);\n\t\ttmp = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);\n\t\tiqk_info->iqk_cfir_real[ch][path][idx][i] =\n\t\t\t\t\t\t(u16)((tmp & 0x0fff0000) >> 16);\n\t\tiqk_info->iqk_cfir_imag[ch][path][idx][i] = (u16)(tmp & 0x0fff);\t\t\n\t}\n#if 0\n\tfor (i = 0; i <= 16; i++)\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK](7) cfir_real[0][%d][%d][%x] = %2x\\n\", path, idx, i, iqk_info->iqk_cfir_real[0][path][idx][i]);\t\t\n\tfor (i = 0; i <= 16; i++)\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK](7) cfir_imag[0][%d][%d][%x] = %2x\\n\", path, idx, i, iqk_info->iqk_cfir_imag[0][path][idx][i]); \n#endif\n\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);\n\t//odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);\n}\n\nvoid iqk_set_cfir_8822c(void *dm_void, u8 idx, u8 path, boolean debug)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tu8 i = 0x0, ch = 0x0;\n\tu32 tmp1 = 0x0, tmp2 = 0x0;\n\t//u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);\n\n\tif (debug)\n\t\tch = 2;\n\telse\n\t\tch = 0;\n\n\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n\n\tif (idx == TX_IQK) {//TXCFIR\n\t\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x3);\t\t\n\t\ttmp1 = 0xc0000001;\n\t} else {//RXCFIR\n\t\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);\n\t\ttmp1 = 0x60000001;\n\t}\n\t\n\tfor (i = 0; i <= 16; i++) {\n\t\ttmp2 = tmp1 | iqk_info->iqk_cfir_real[ch][path][idx][i]<< 8;\n\t\ttmp2 = (tmp2 | i << 2) + 2;\n\t\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, tmp2);\n\t\t//RF_DBG(dm, DBG_RF_IQK, \"[IQK]iqk_cfir_real = 0x%x\\n\", tmp2);\n\t}\n\tfor (i = 0; i <= 16; i++) {\n\t\ttmp2 = tmp1 | iqk_info->iqk_cfir_imag[ch][path][idx][i]<< 8;\n\t\ttmp2 = (tmp2 | i << 2);\n\t\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, tmp2);\t\t\n\t\t//RF_DBG(dm, DBG_RF_IQK, \"[IQK]iqk_cfir_imag = 0x%x\\n\", tmp2);\n\t}\t\t\n\t\t\n\t// end for write CFIR SRAM\n\t//odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001);\n\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);\n\t//odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);\n}\n\n\nvoid iqk_clean_cfir_8822c(void *dm_void, u8 mode, u8 path)\n{\t\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\t\n\tu32 bit_mask_6_2 = 0x7c;\t\n\tu32 bit_mask_19_8 = 0xfff00;\n\tu8 i = 0x0;\n\tu32 tmp = 0x0;\n\t\n\todm_write_4byte(dm, 0x1b00, 0x8 | path << 1);\n//TX_IQK\n\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x3);\t\t\n\t// clear real part\n\ttmp = 0xc0000003;\n\tfor (i =0x0; i<= 16; i++)\t\t\n\t\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, tmp | i << 2);\n\t//clear img part\n\ttmp = 0xc0000001;\n\tfor (i =0x0; i<= 16; i++)\t\t\n\t\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, tmp | i << 2);\n//RX_IQK\n\todm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);\n\t// clear real part\n\ttmp = 0x60000003;\n\tfor (i =0x0; i<= 16; i++)\t\t\n\t\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, tmp | i << 2);\n\t//clear img part\n\ttmp = 0x60000001;\n\tfor (i =0x0; i<= 16; i++)\t\t\n\t\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, tmp | i << 2);\n\n\t// end for write CFIR SRAM\n\todm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001);\n\t\t\n}\nvoid phy_get_iqk_cfir_8822c(void *dm_void, u8 idx, u8 path, boolean debug)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tiqk_get_cfir_8822c(dm, idx, path, debug);\n}\n\n\nvoid phy_iqk_dbg_cfir_backup_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tu8 path, idx, i;\n\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]%-20s\\n\", \"backup TX/RX CFIR\");\n\n\tfor (path = 0; path < SS_8822C; path++)\n\t\tfor (idx = 0; idx < 2; idx++)\n\t\t\tphydm_get_iqk_cfir(dm, idx, path, true);\n\n\tfor (path = 0; path < SS_8822C; path++) {\n\t\tfor (idx = 0; idx < 2; idx++) {\n\t\t\tfor (i = 0; i <= 16; i++) {\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\t       \"[IQK]%-7s %-3s CFIR_real: %-2d: 0x%x\\n\",\n\t\t\t\t       (path == 0) ? \"PATH A\" : \"PATH B\",\n\t\t\t\t       (idx == 0) ? \"TX\" : \"RX\", i,\n\t\t\t\t       iqk_info->iqk_cfir_real[2][path][idx][i])\n\t\t\t\t       ;\n\t\t\t}\n\t\t\tfor (i = 0; i <= 16; i++) {\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\t       \"[IQK]%-7s %-3s CFIR_img:%-2d: 0x%x\\n\",\n\t\t\t\t       (path == 0) ? \"PATH A\" : \"PATH B\",\n\t\t\t\t       (idx == 0) ? \"TX\" : \"RX\", i,\n\t\t\t\t       iqk_info->iqk_cfir_imag[2][path][idx][i])\n\t\t\t\t       ;\n\t\t\t}\n\t\t}\n\t}\n}\n\nvoid phy_iqk_dbg_cfir_backup_update_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk = &dm->IQK_info;\n\tu8 i, path, idx;\n\tu32 bmask13_12 = BIT(13) | BIT(12);\n\tu32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);\n\tu32 data;\n\n\tif (iqk->iqk_cfir_real[2][0][0][0] == 0) {\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]%-20s\\n\", \"CFIR is invalid\");\n\t\treturn;\n\t}\n\tfor (path = 0; path < SS_8822C; path++) {\n\t\tfor (idx = 0; idx < 2; idx++) {\n\t\t\todm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | path << 1);\n\t\t\todm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7);\n\t\t\todm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x40000000);\n\t\t\todm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x40000000);\n\t\t\todm_set_bb_reg(dm, R_0x1bcc, MASKDWORD, 0x00000000);\n\t\t\tiqk_get_cfir_8822c(dm, idx, path, false);\n\t\t}\n\t}\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]%-20s\\n\", \"update new CFIR\");\n}\n\nvoid phy_iqk_dbg_cfir_reload_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk = &dm->IQK_info;\n\tu8 i, path, idx;\n\tu32 bmask13_12 = BIT(13) | BIT(12);\n\tu32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);\n\tu32 data;\n\n\tif (iqk->iqk_cfir_real[0][0][0][0] == 0) {\n\t\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]%-20s\\n\", \"CFIR is invalid\");\n\t\treturn;\n\t}\n\tfor (path = 0; path < SS_8822C; path++) {\n\t\tfor (idx = 0; idx < 2; idx++) {\n\t\t\todm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | path << 1);\n\t\t\todm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7);\n\t\t\todm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x40000000);\n\t\t\todm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x40000000);\n\t\t\todm_set_bb_reg(dm, R_0x1bcc, MASKDWORD, 0x00000000);\t\t\t\n\t\t\tiqk_set_cfir_8822c(dm, idx, path, false);\n\t\t}\n\t}\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]%-20s\\n\", \"write CFIR with default value\");\n}\n\nvoid phy_iqk_dbg_cfir_write_8822c(void *dm_void, u8 type, u32 path, u32 idx,\n\t\t\t      u32 i, u32 data)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\n\tif (type == 0)\n\t\tiqk_info->iqk_cfir_real[2][path][idx][i] = (u16)data;\n\telse\n\t\tiqk_info->iqk_cfir_imag[2][path][idx][i] = (u16)data;\n}\n\nvoid phy_iqk_dbg_cfir_backup_show_8822c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_iqk_info *iqk_info = &dm->IQK_info;\n\tu8 path, idx, i;\n\n\tRF_DBG(dm, DBG_RF_IQK, \"[IQK]%-20s\\n\", \"backup TX/RX CFIR\");\n\n\tfor (path = 0; path < SS_8822C; path++) {\n\t\tfor (idx = 0; idx < 2; idx++) {\n\t\t\tfor (i = 0; i <= 16; i++) {\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\t       \"[IQK]%-10s %-3s CFIR_real:%-2d: 0x%x\\n\",\n\t\t\t\t       (path == 0) ? \"PATH A\" : \"PATH B\",\n\t\t\t\t       (idx == 0) ? \"TX\" : \"RX\", i,\n\t\t\t\t       iqk_info->iqk_cfir_real[2][path][idx][i])\n\t\t\t\t       ;\n\t\t\t}\n\t\t\tfor (i = 0; i <= 16; i++) {\n\t\t\t\tRF_DBG(dm, DBG_RF_IQK,\n\t\t\t\t       \"[IQK]%-10s %-3s CFIR_img:%-2d: 0x%x\\n\",\n\t\t\t\t       (path == 0) ? \"PATH A\" : \"PATH B\",\n\t\t\t\t       (idx == 0) ? \"TX\" : \"RX\", i,\n\t\t\t\t       iqk_info->iqk_cfir_imag[2][path][idx][i])\n\t\t\t\t       ;\n\t\t\t}\n\t\t}\n\t}\n}\n\n#endif\n"
  },
  {
    "path": "hal/phydm/halrf/rtl8822c/halrf_iqk_8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALRF_IQK_8822C_H__\n#define __HALRF_IQK_8822C_H__\n\n#if (RTL8822C_SUPPORT == 1)\n/*--------------------------Define Parameters-------------------------------*/\n#define MAC_REG_NUM_8822C 3\n#define BB_REG_NUM_8822C 11\n#define RF_REG_NUM_8822C 3\n#define IQK_DELAY_8822C 2\n#define IQK_STEP_8822C 7\n#define RXK_STEP_8822C 6\n#define IQK_CMD_8822C 0x8\n\n#define TXIQK 0\n#define RXIQK 1\n#define SS_8822C 2\n\n#define IQK_INFO_RSVD_LEN_8822C\t568\n/*---------------------------End Define Parameters-------------------------------*/\n#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\nvoid do_iqk_8822c(\n\tvoid *dm_void,\n\tu8 delta_thermal_index,\n\tu8 thermal_value,\n\tu8 threshold);\n#else\nvoid do_iqk_8822c(\n\tvoid *dm_void,\n\tu8 delta_thermal_index,\n\tu8 thermal_value,\n\tu8 threshold);\n#endif\n\nvoid phy_iq_calibrate_8822c(\n\tvoid *dm_void,\n\tboolean clear,\n\tboolean segment_iqk);\n\nvoid do_imr_test_8822c(\n\tvoid *dm_void);\n\nvoid do_lok_8822c(\n\tvoid *dm_void);\n\nvoid iqk_get_cfir_8822c(void *dm_void, u8 idx, u8 path, boolean debug);\n\nvoid iqk_set_cfir_8822c(void *dm_void, u8 idx, u8 path, boolean debug);\n\nvoid iqk_reload_iqk_8822c(void *dm_void, boolean reset);\n\nvoid phy_get_iqk_cfir_8822c(void *dm_void, u8 idx, u8 path, boolean debug);\n\nvoid phy_iqk_dbg_cfir_backup_8822c(void *dm_void);\n\nvoid phy_iqk_dbg_cfir_backup_update_8822c(void *dm_void);\n\nvoid phy_iqk_dbg_cfir_reload_8822c(void *dm_void);\n\nvoid phy_iqk_dbg_cfir_write_8822c(void *dm_void, u8 type, u32 path, u32 idx, u32 i, u32 data);\n\nvoid phy_iqk_dbg_cfir_backup_show_8822b(void *dm_void);\n\nvoid iqk_info_rsvd_page_8822c(void *dm_void, u8 *buf, u32 *buf_size);\n\n\n#else /* (RTL8822C_SUPPORT == 0)*/\n\n#define phy_iq_calibrate_8822c(_pdm_void, clear, segment_iqk)\n\n#endif /* RTL8822C_SUPPORT */\n\n#endif /*__HALRF_IQK_8822C_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/rtl8822c/halrf_rfk_init_8822c.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include \"mp_precomp.h\"\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#if RT_PLATFORM == PLATFORM_MACOSX\n#include \"phydm_precomp.h\"\n#else\n#include \"../phydm_precomp.h\"\n#endif\n#else\n#include \"../../phydm_precomp.h\"\n#endif\n\n#if (RTL8822C_SUPPORT == 1)\n\n#if 1\nu32 array_mp_8822c_cal_init[] = {\t\n\t0x1b00, 0x00000008,\n\t0x1b00, 0x00A70008,\n\t0x1b00, 0x00150008,\n\t0x1b00, 0x00000008,\n\t0x1b04, 0xE2462952,\n\t0x1b08, 0x00000080,\n\t0x1b0c, 0x00000000,\n\t0x1b10, 0x00010C00,\n\t0x1b14, 0x00000000,\n\t0x1b18, 0x00292903,\n\t0x1b1c, 0xA218FC32,\n\t0x1b20, 0x01040008,\n\t0x1b24, 0x00060008,\n\t0x1b28, 0x00060300,\n\t0x1b2C, 0x00180018,\n\t0x1b30, 0x40000000,\n\t0x1b34, 0x00000800,\n\t0x1b38, 0x40000000,\n\t0x1b3C, 0x40000000,\n\t0x1b98, 0x00000000,\n\t0x1b9c, 0x00000000,\n\t0x1bc0, 0x01000000,\n\t0x1bcc, 0x00000000,\n\t0x1bd8, 0xe0000001,\n\t0x1be4, 0x00000000,\n\t0x1bec, 0x40000000,\n\t0x1b40, 0x40000000,\n\t0x1b44, 0x20004064,\n\t0x1b48, 0x0005002D,\n\t0x1b4c, 0x00000000,\n\t0x1b60, 0x1F100000,\n\t0x1b64, 0x12000000,\n\t0x1b4c, 0x00000000,\n\t0x1b4c, 0x008a0000,\n\t0x1b50, 0x000003BE,\n\t0x1b4c, 0x018a0000,\n\t0x1b50, 0x0000057A,\n\t0x1b4c, 0x028a0000,\n\t0x1b50, 0x000006C8,\n\t0x1b4c, 0x038a0000,\n\t0x1b50, 0x000007E0,\n\t0x1b4c, 0x048a0000,\n\t0x1b50, 0x000008D5,\n\t0x1b4c, 0x058a0000,\n\t0x1b50, 0x000009B2,\n\t0x1b4c, 0x068a0000,\n\t0x1b50, 0x00000A7D,\n\t0x1b4c, 0x078a0000,\n\t0x1b50, 0x00000B3A,\n\t0x1b4c, 0x088a0000,\n\t0x1b50, 0x00000BEB,\n\t0x1b4c, 0x098a0000,\n\t0x1b50, 0x00000C92,\n\t0x1b4c, 0x0A8a0000,\n\t0x1b50, 0x00000D31,\n\t0x1b4c, 0x0B8a0000,\n\t0x1b50, 0x00000DC9,\n\t0x1b4c, 0x0C8a0000,\n\t0x1b50, 0x00000E5A,\n\t0x1b4c, 0x0D8a0000,\n\t0x1b50, 0x00000EE6,\n\t0x1b4c, 0x0E8a0000,\n\t0x1b50, 0x00000F6D,\n\t0x1b4c, 0x0F8a0000,\n\t0x1b50, 0x00000FF0,\n\t0x1b4c, 0x108a0000,\n\t0x1b50, 0x0000106F,\n\t0x1b4c, 0x118a0000,\n\t0x1b50, 0x000010E9,\n\t0x1b4c, 0x128a0000,\n\t0x1b50, 0x00001161,\n\t0x1b4c, 0x138a0000,\n\t0x1b50, 0x000011D5,\n\t0x1b4c, 0x148a0000,\n\t0x1b50, 0x00001247,\n\t0x1b4c, 0x158a0000,\n\t0x1b50, 0x000012B5,\n\t0x1b4c, 0x168a0000,\n\t0x1b50, 0x00001322,\n\t0x1b4c, 0x178a0000,\n\t0x1b50, 0x0000138B,\n\t0x1b4c, 0x188a0000,\n\t0x1b50, 0x000013F3,\n\t0x1b4c, 0x198a0000,\n\t0x1b50, 0x00001459,\n\t0x1b4c, 0x1A8a0000,\n\t0x1b50, 0x000014BD,\n\t0x1b4c, 0x1B8a0000,\n\t0x1b50, 0x0000151E,\n\t0x1b4c, 0x1C8a0000,\n\t0x1b50, 0x0000157F,\n\t0x1b4c, 0x1D8a0000,\n\t0x1b50, 0x000015DD,\n\t0x1b4c, 0x1E8a0000,\n\t0x1b50, 0x0000163A,\n\t0x1b4c, 0x1F8a0000,\n\t0x1b50, 0x00001695,\n\t0x1b4c, 0x208a0000,\n\t0x1b50, 0x000016EF,\n\t0x1b4c, 0x218a0000,\n\t0x1b50, 0x00001748,\n\t0x1b4c, 0x228a0000,\n\t0x1b50, 0x0000179F,\n\t0x1b4c, 0x238a0000,\n\t0x1b50, 0x000017F5,\n\t0x1b4c, 0x248a0000,\n\t0x1b50, 0x0000184A,\n\t0x1b4c, 0x258a0000,\n\t0x1b50, 0x0000189E,\n\t0x1b4c, 0x268a0000,\n\t0x1b50, 0x000018F1,\n\t0x1b4c, 0x278a0000,\n\t0x1b50, 0x00001942,\n\t0x1b4c, 0x288a0000,\n\t0x1b50, 0x00001993,\n\t0x1b4c, 0x298a0000,\n\t0x1b50, 0x000019E2,\n\t0x1b4c, 0x2A8a0000,\n\t0x1b50, 0x00001A31,\n\t0x1b4c, 0x2B8a0000,\n\t0x1b50, 0x00001A7F,\n\t0x1b4c, 0x2C8a0000,\n\t0x1b50, 0x00001ACC,\n\t0x1b4c, 0x2D8a0000,\n\t0x1b50, 0x00001B18,\n\t0x1b4c, 0x2E8a0000,\n\t0x1b50, 0x00001B63,\n\t0x1b4c, 0x2F8a0000,\n\t0x1b50, 0x00001BAD,\n\t0x1b4c, 0x308a0000,\n\t0x1b50, 0x00001BF7,\n\t0x1b4c, 0x318a0000,\n\t0x1b50, 0x00001C40,\n\t0x1b4c, 0x328a0000,\n\t0x1b50, 0x00001C88,\n\t0x1b4c, 0x338a0000,\n\t0x1b50, 0x00001CCF,\n\t0x1b4c, 0x348a0000,\n\t0x1b50, 0x00001D16,\n\t0x1b4c, 0x358a0000,\n\t0x1b50, 0x00001D5C,\n\t0x1b4c, 0x368a0000,\n\t0x1b50, 0x00001DA2,\n\t0x1b4c, 0x378a0000,\n\t0x1b50, 0x00001DE6,\n\t0x1b4c, 0x388a0000,\n\t0x1b50, 0x00001E2B,\n\t0x1b4c, 0x398a0000,\n\t0x1b50, 0x00001E6E,\n\t0x1b4c, 0x3A8a0000,\n\t0x1b50, 0x00001EB1,\n\t0x1b4c, 0x3B8a0000,\n\t0x1b50, 0x00001EF4,\n\t0x1b4c, 0x3C8a0000,\n\t0x1b50, 0x00001F35,\n\t0x1b4c, 0x3D8a0000,\n\t0x1b50, 0x00001F77,\n\t0x1b4c, 0x3E8a0000,\n\t0x1b50, 0x00001FB8,\n\t0x1b4c, 0x3F8a0000,\n\t0x1b50, 0x00001FF8,\n\t0x1b4c, 0x00000000,\n\t0x1b50, 0x00000000,\n\t0x1b58, 0x00890000,\n\t0x1b5C, 0x3C6B3FFF,\n\t0x1b58, 0x02890000,\n\t0x1b5C, 0x35D9390A,\n\t0x1b58, 0x04890000,\n\t0x1b5C, 0x2FFE32D6,\n\t0x1b58, 0x06890000,\n\t0x1b5C, 0x2AC62D4F,\n\t0x1b58, 0x08890000,\n\t0x1b5C, 0x261F2862,\n\t0x1b58, 0x0A890000,\n\t0x1b5C, 0x21FA23FD,\n\t0x1b58, 0x0C890000,\n\t0x1b5C, 0x1E482013,\n\t0x1b58, 0x0E890000,\n\t0x1b5C, 0x1AFD1C96,\n\t0x1b58, 0x10890000,\n\t0x1b5C, 0x180E197B,\n\t0x1b58, 0x12890000,\n\t0x1b5C, 0x157016B5,\n\t0x1b58, 0x14890000,\n\t0x1b5C, 0x131B143D,\n\t0x1b58, 0x16890000,\n\t0x1b5C, 0x1107120A,\n\t0x1b58, 0x18890000,\n\t0x1b5C, 0x0F2D1013,\n\t0x1b58, 0x1A890000,\n\t0x1b5C, 0x0D870E54,\n\t0x1b58, 0x1C890000,\n\t0x1b5C, 0x0C0E0CC5,\n\t0x1b58, 0x1E890000,\n\t0x1b5C, 0x0ABF0B62,\n\t0x1b58, 0x20890000,\n\t0x1b5C, 0x09930A25,\n\t0x1b58, 0x22890000,\n\t0x1b5C, 0x0889090A,\n\t0x1b58, 0x24890000,\n\t0x1b5C, 0x079B080F,\n\t0x1b58, 0x26890000,\n\t0x1b5C, 0x06C7072E,\n\t0x1b58, 0x28890000,\n\t0x1b5C, 0x060B0666,\n\t0x1b58, 0x2A890000,\n\t0x1b5C, 0x056305B4,\n\t0x1b58, 0x2C890000,\n\t0x1b5C, 0x04CD0515,\n\t0x1b58, 0x2E890000,\n\t0x1b5C, 0x04470488,\n\t0x1b58, 0x30890000,\n\t0x1b5C, 0x03D0040A,\n\t0x1b58, 0x32890000,\n\t0x1b5C, 0x03660399,\n\t0x1b58, 0x34890000,\n\t0x1b5C, 0x03070335,\n\t0x1b58, 0x36890000,\n\t0x1b5C, 0x02B302DC,\n\t0x1b58, 0x38890000,\n\t0x1b5C, 0x0268028C,\n\t0x1b58, 0x3A890000,\n\t0x1b5C, 0x02250245,\n\t0x1b58, 0x3C890000,\n\t0x1b5C, 0x01E90206,\n\t0x1b58, 0x3E890000,\n\t0x1b5C, 0x01B401CE,\n\t0x1b58, 0x40890000,\n\t0x1b5C, 0x0185019C,\n\t0x1b58, 0x42890000,\n\t0x1b5C, 0x015A016F,\n\t0x1b58, 0x44890000,\n\t0x1b5C, 0x01350147,\n\t0x1b58, 0x46890000,\n\t0x1b5C, 0x01130123,\n\t0x1b58, 0x48890000,\n\t0x1b5C, 0x00F50104,\n\t0x1b58, 0x4A890000,\n\t0x1b5C, 0x00DA00E7,\n\t0x1b58, 0x4C890000,\n\t0x1b5C, 0x00C300CE,\n\t0x1b58, 0x4E890000,\n\t0x1b5C, 0x00AE00B8,\n\t0x1b58, 0x50890000,\n\t0x1b5C, 0x009B00A4,\n\t0x1b58, 0x52890000,\n\t0x1b5C, 0x008A0092,\n\t0x1b58, 0x54890000,\n\t0x1b5C, 0x007B0082,\n\t0x1b58, 0x56890000,\n\t0x1b5C, 0x006E0074,\n\t0x1b58, 0x58890000,\n\t0x1b5C, 0x00620067,\n\t0x1b58, 0x5A890000,\n\t0x1b5C, 0x0057005C,\n\t0x1b58, 0x5C890000,\n\t0x1b5C, 0x004E0052,\n\t0x1b58, 0x5E890000,\n\t0x1b5C, 0x00450049,\n\t0x1b58, 0x60890000,\n\t0x1b5C, 0x003E0041,\n\t0x1b58, 0x62890000,\n\t0x1b5C, 0x0037003A,\n\t0x1b58, 0x62010000,\n\t0x1b00, 0x0000000A,\n\t0x1b00, 0x00A7000A,\n\t0x1b00, 0x0015000A,\n\t0x1b00, 0x0000000A,\n\t0x1b04, 0xE2462952,\n\t0x1b08, 0x00000080,\n\t0x1b0c, 0x00000000,\n\t0x1b10, 0x00010C00,\n\t0x1b14, 0x00000000,\n\t0x1b18, 0x00292903,\n\t0x1b1c, 0xA218FC32,\n\t0x1b20, 0x01040008,\n\t0x1b24, 0x00060008,\n\t0x1b28, 0x00060300,\n\t0x1b2C, 0x00180018,\n\t0x1b30, 0x40000000,\n\t0x1b34, 0x00000800,\n\t0x1b38, 0x40000000,\n\t0x1b3C, 0x40000000,\n\t0x1b98, 0x00000000,\n\t0x1b9c, 0x00000000,\n\t0x1bc0, 0x01000000,\n\t0x1bcc, 0x00000000,\n\t0x1bd8, 0xe0000001,\n\t0x1be4, 0x00000000,\n\t0x1bec, 0x40000000,\n\t0x1b60, 0x1F100000,\n\t0x1b64, 0x12000000,\n\t0x1b58, 0x00890000,\n\t0x1b5C, 0x3C6B3FFF,\n\t0x1b58, 0x02890000,\n\t0x1b5C, 0x35D9390A,\n\t0x1b58, 0x04890000,\n\t0x1b5C, 0x2FFE32D6,\n\t0x1b58, 0x06890000,\n\t0x1b5C, 0x2AC62D4F,\n\t0x1b58, 0x08890000,\n\t0x1b5C, 0x261F2862,\n\t0x1b58, 0x0A890000,\n\t0x1b5C, 0x21FA23FD,\n\t0x1b58, 0x0C890000,\n\t0x1b5C, 0x1E482013,\n\t0x1b58, 0x0E890000,\n\t0x1b5C, 0x1AFD1C96,\n\t0x1b58, 0x10890000,\n\t0x1b5C, 0x180E197B,\n\t0x1b58, 0x12890000,\n\t0x1b5C, 0x157016B5,\n\t0x1b58, 0x14890000,\n\t0x1b5C, 0x131B143D,\n\t0x1b58, 0x16890000,\n\t0x1b5C, 0x1107120A,\n\t0x1b58, 0x18890000,\n\t0x1b5C, 0x0F2D1013,\n\t0x1b58, 0x1A890000,\n\t0x1b5C, 0x0D870E54,\n\t0x1b58, 0x1C890000,\n\t0x1b5C, 0x0C0E0CC5,\n\t0x1b58, 0x1E890000,\n\t0x1b5C, 0x0ABF0B62,\n\t0x1b58, 0x20890000,\n\t0x1b5C, 0x09930A25,\n\t0x1b58, 0x22890000,\n\t0x1b5C, 0x0889090A,\n\t0x1b58, 0x24890000,\n\t0x1b5C, 0x079B080F,\n\t0x1b58, 0x26890000,\n\t0x1b5C, 0x06C7072E,\n\t0x1b58, 0x28890000,\n\t0x1b5C, 0x060B0666,\n\t0x1b58, 0x2A890000,\n\t0x1b5C, 0x056305B4,\n\t0x1b58, 0x2C890000,\n\t0x1b5C, 0x04CD0515,\n\t0x1b58, 0x2E890000,\n\t0x1b5C, 0x04470488,\n\t0x1b58, 0x30890000,\n\t0x1b5C, 0x03D0040A,\n\t0x1b58, 0x32890000,\n\t0x1b5C, 0x03660399,\n\t0x1b58, 0x34890000,\n\t0x1b5C, 0x03070335,\n\t0x1b58, 0x36890000,\n\t0x1b5C, 0x02B302DC,\n\t0x1b58, 0x38890000,\n\t0x1b5C, 0x0268028C,\n\t0x1b58, 0x3A890000,\n\t0x1b5C, 0x02250245,\n\t0x1b58, 0x3C890000,\n\t0x1b5C, 0x01E90206,\n\t0x1b58, 0x3E890000,\n\t0x1b5C, 0x01B401CE,\n\t0x1b58, 0x40890000,\n\t0x1b5C, 0x0185019C,\n\t0x1b58, 0x42890000,\n\t0x1b5C, 0x015A016F,\n\t0x1b58, 0x44890000,\n\t0x1b5C, 0x01350147,\n\t0x1b58, 0x46890000,\n\t0x1b5C, 0x01130123,\n\t0x1b58, 0x48890000,\n\t0x1b5C, 0x00F50104,\n\t0x1b58, 0x4A890000,\n\t0x1b5C, 0x00DA00E7,\n\t0x1b58, 0x4C890000,\n\t0x1b5C, 0x00C300CE,\n\t0x1b58, 0x4E890000,\n\t0x1b5C, 0x00AE00B8,\n\t0x1b58, 0x50890000,\n\t0x1b5C, 0x009B00A4,\n\t0x1b58, 0x52890000,\n\t0x1b5C, 0x008A0092,\n\t0x1b58, 0x54890000,\n\t0x1b5C, 0x007B0082,\n\t0x1b58, 0x56890000,\n\t0x1b5C, 0x006E0074,\n\t0x1b58, 0x58890000,\n\t0x1b5C, 0x00620067,\n\t0x1b58, 0x5A890000,\n\t0x1b5C, 0x0057005C,\n\t0x1b58, 0x5C890000,\n\t0x1b5C, 0x004E0052,\n\t0x1b58, 0x5E890000,\n\t0x1b5C, 0x00450049,\n\t0x1b58, 0x60890000,\n\t0x1b5C, 0x003E0041,\n\t0x1b58, 0x62890000,\n\t0x1b5C, 0x0037003A,\n\t0x1b58, 0x62010000,\n\t0x1b00, 0x0000000C,\n\t0x1bd4, 0x000000F0,\n\t0x1bb8, 0x20202020,\n\t0x1bbc, 0x20202020,\n\t0x1bc0, 0x20202020,\n\t0x1bc4, 0x20202020,\n\t0x1bc8, 0x04040404,\n\t0x1bcc, 0x04040404,\n\t0x1bd0, 0x04040404,\n\t0x1bd8, 0x04040404,\n\t0x1bdc, 0x20202020,\n\t0x1be0, 0x04040404,\n\t0x1be4, 0x77472F17,\n\t0x1be8, 0xEFBFA78F,\n\t0x1bec, 0x00000000,\n\t0x1bf0, 0x1F1F1939,\n\t0x1b04, 0x0000005B,\n\t0x1b08, 0xB000C000,\n\t0x1b5c, 0x0000005B,\n\t0x1b60, 0xB000C000,\n\t0x1bb4, 0x20000000,\n\t\t0x1b00, 0x00000008,\n\t\t0x1b80, 0x00000007,\n\t\t0x1b80, 0x00080005,\n\t\t0x1b80, 0x00080007,\n\t\t0x1b80, 0x80000015,\n\t\t0x1b80, 0x80000017,\n\t\t0x1b80, 0x09080025,\n\t\t0x1b80, 0x09080027,\n\t\t0x1b80, 0x0f020035,\n\t\t0x1b80, 0x0f020037,\n\t\t0x1b80, 0x00220045,\n\t\t0x1b80, 0x00220047,\n\t\t0x1b80, 0x00040055,\n\t\t0x1b80, 0x00040057,\n\t\t0x1b80, 0x05c00065,\n\t\t0x1b80, 0x05c00067,\n\t\t0x1b80, 0x00070075,\n\t\t0x1b80, 0x00070077,\n\t\t0x1b80, 0x64020085,\n\t\t0x1b80, 0x64020087,\n\t\t0x1b80, 0x00020095,\n\t\t0x1b80, 0x00020097,\n\t\t0x1b80, 0x000400a5,\n\t\t0x1b80, 0x000400a7,\n\t\t0x1b80, 0x4a0000b5,\n\t\t0x1b80, 0x4a0000b7,\n\t\t0x1b80, 0x4b0400c5,\n\t\t0x1b80, 0x4b0400c7,\n\t\t0x1b80, 0x860300d5,\n\t\t0x1b80, 0x860300d7,\n\t\t0x1b80, 0x400900e5,\n\t\t0x1b80, 0x400900e7,\n\t\t0x1b80, 0xe02700f5,\n\t\t0x1b80, 0xe02700f7,\n\t\t0x1b80, 0x4b050105,\n\t\t0x1b80, 0x4b050107,\n\t\t0x1b80, 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0x000136d5,\n\t\t0x1b80, 0x000136d7,\n\t\t0x1b80, 0x000636e5,\n\t\t0x1b80, 0x000636e7,\n\t\t0x1b80, 0x5a8036f5,\n\t\t0x1b80, 0x5a8036f7,\n\t\t0x1b80, 0x5a003705,\n\t\t0x1b80, 0x5a003707,\n\t\t0x1b80, 0x92003715,\n\t\t0x1b80, 0x92003717,\n\t\t0x1b80, 0x00013725,\n\t\t0x1b80, 0x00013727,\n\t\t0x1b80, 0x5b8f3735,\n\t\t0x1b80, 0x5b8f3737,\n\t\t0x1b80, 0x5b0f3745,\n\t\t0x1b80, 0x5b0f3747,\n\t\t0x1b80, 0x91003755,\n\t\t0x1b80, 0x91003757,\n\t\t0x1b80, 0x00013765,\n\t\t0x1b80, 0x00013767,\n\t\t0x1b80, 0x00063775,\n\t\t0x1b80, 0x00063777,\n\t\t0x1b80, 0x5d803785,\n\t\t0x1b80, 0x5d803787,\n\t\t0x1b80, 0x5e563795,\n\t\t0x1b80, 0x5e563797,\n\t\t0x1b80, 0x000437a5,\n\t\t0x1b80, 0x000437a7,\n\t\t0x1b80, 0x4d0837b5,\n\t\t0x1b80, 0x4d0837b7,\n\t\t0x1b80, 0x571037c5,\n\t\t0x1b80, 0x571037c7,\n\t\t0x1b80, 0x570037d5,\n\t\t0x1b80, 0x570037d7,\n\t\t0x1b80, 0x4d0037e5,\n\t\t0x1b80, 0x4d0037e7,\n\t\t0x1b80, 0x000637f5,\n\t\t0x1b80, 0x000637f7,\n\t\t0x1b80, 0x5d003805,\n\t\t0x1b80, 0x5d003807,\n\t\t0x1b80, 0x00043815,\n\t\t0x1b80, 0x00043817,\n\t\t0x1b80, 0x00013825,\n\t\t0x1b80, 0x00013827,\n\t\t0x1b80, 0x549f3835,\n\t\t0x1b80, 0x549f3837,\n\t\t0x1b80, 0x54ff3845,\n\t\t0x1b80, 0x54ff3847,\n\t\t0x1b80, 0x54003855,\n\t\t0x1b80, 0x54003857,\n\t\t0x1b80, 0x00013865,\n\t\t0x1b80, 0x00013867,\n\t\t0x1b80, 0x5c313875,\n\t\t0x1b80, 0x5c313877,\n\t\t0x1b80, 0x07143885,\n\t\t0x1b80, 0x07143887,\n\t\t0x1b80, 0x54003895,\n\t\t0x1b80, 0x54003897,\n\t\t0x1b80, 0x5c3238a5,\n\t\t0x1b80, 0x5c3238a7,\n\t\t0x1b80, 0x000138b5,\n\t\t0x1b80, 0x000138b7,\n\t\t0x1b80, 0x5c3238c5,\n\t\t0x1b80, 0x5c3238c7,\n\t\t0x1b80, 0x071438d5,\n\t\t0x1b80, 0x071438d7,\n\t\t0x1b80, 0x540038e5,\n\t\t0x1b80, 0x540038e7,\n\t\t0x1b80, 0x5c3138f5,\n\t\t0x1b80, 0x5c3138f7,\n\t\t0x1b80, 0x00013905,\n\t\t0x1b80, 0x00013907,\n\t\t0x1b80, 0x4c983915,\n\t\t0x1b80, 0x4c983917,\n\t\t0x1b80, 0x4c183925,\n\t\t0x1b80, 0x4c183927,\n\t\t0x1b80, 0x00013935,\n\t\t0x1b80, 0x00013937,\n\t\t0x1b80, 0x5c323945,\n\t\t0x1b80, 0x5c323947,\n\t\t0x1b80, 0x62043955,\n\t\t0x1b80, 0x62043957,\n\t\t0x1b80, 0x63033965,\n\t\t0x1b80, 0x63033967,\n\t\t0x1b80, 0x66073975,\n\t\t0x1b80, 0x66073977,\n\t\t0x1b80, 0x7b403985,\n\t\t0x1b80, 0x7b403987,\n\t\t0x1b80, 0x7a003995,\n\t\t0x1b80, 0x7a003997,\n\t\t0x1b80, 0x790039a5,\n\t\t0x1b80, 0x790039a7,\n\t\t0x1b80, 0x7f4039b5,\n\t\t0x1b80, 0x7f4039b7,\n\t\t0x1b80, 0x7e0039c5,\n\t\t0x1b80, 0x7e0039c7,\n\t\t0x1b80, 0x7d0039d5,\n\t\t0x1b80, 0x7d0039d7,\n\t\t0x1b80, 0x090139e5,\n\t\t0x1b80, 0x090139e7,\n\t\t0x1b80, 0x0c0139f5,\n\t\t0x1b80, 0x0c0139f7,\n\t\t0x1b80, 0x0ba63a05,\n\t\t0x1b80, 0x0ba63a07,\n\t\t0x1b80, 0x00013a15,\n\t\t0x1b80, 0x00013a17,\n\t\t0x1b80, 0x00000006,\n\t\t0x1b80, 0x00000002,\n};\n#endif\n\nvoid odm_read_and_config_mp_8822c_cal_init(void *dm_void)\n{\n#if 1\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_dpk_info *dpk_info = &dm->dpk_info;\n\n\tu32\ti = 0;\n\tu32\tarray_len = sizeof(array_mp_8822c_cal_init)/sizeof(u32);\n\tu32\t*array = array_mp_8822c_cal_init;\n\tu32\tv1 = 0, v2 = 0;\n\n\todm_set_bb_reg(dm, R_0x1cd0, BIT(28), 0x1);// r_iqk_dpk_clock_src\n\todm_set_bb_reg(dm, R_0x1cd0, BIT(29), 0x1);// r_iqk_dpk_reset_src\n\todm_set_bb_reg(dm, R_0x1cd0, BIT(30), 0x1);// r_en_IOQ_iqk_dpk\n\todm_set_bb_reg(dm, R_0x1cd0, BIT(31), 0x0);// r_tst_iqk2set_src\n\n\twhile ((i + 1) < array_len) {\n\t\tv1 = array[i];\n\t\tv2 = array[i + 1];\n\t\todm_config_bb_phy_8822c(dm, v1, MASKDWORD, v2);\t\t\n\t\tRF_DBG(dm, DBG_RF_IQK, \"v1 = 0x%x, v2 = 0x%x \\n\",v1,v2);\n\t\ti = i + 2;\n\t}\n\n\tdpk_info->is_dpk_pwr_on = 1;\n\tdpk_info->is_dpk_enable = 1;\n\tdpk_info->is_dpk_by_channel= 1;\n#endif\n}\n\n#endif\n"
  },
  {
    "path": "hal/phydm/halrf/rtl8822c/halrf_rfk_init_8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#ifndef __HALRF_RFK_INIT_8822C_H__\n#define __HALRF_RFK_INIT_8822C_H__\n\nvoid odm_read_and_config_mp_8822c_cal_init(void *dm_void);\n#endif"
  },
  {
    "path": "hal/phydm/halrf/rtl8822c/halrf_tssi_8822c.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#include \"mp_precomp.h\"\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#if RT_PLATFORM == PLATFORM_MACOSX\n#include \"phydm_precomp.h\"\n#else\n#include \"../phydm_precomp.h\"\n#endif\n#else\n#include \"../../phydm_precomp.h\"\n#endif\n\n#if (RTL8822C_SUPPORT == 1)\n\nvoid _halrf_dc_offset_calibration_8822c(\n\tvoid *dm_void)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 reg = 0;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"===>_halrf_dc_offset_calibration_8822c\\n\");\n\n\t/*path s0*/\n\todm_set_bb_reg(dm, R_0x1d08, 0x00000001, 0x1);\n\todm_set_bb_reg(dm, R_0x900, 0x0f000000, 0x0);\n\todm_set_bb_reg(dm, R_0x900, 0x30000000, 0x0);\n\todm_set_bb_reg(dm, R_0x900, 0xc0000000, 0x0);\n\todm_set_bb_reg(dm, R_0x900, 0x00000001, 0x1);\n\todm_set_bb_reg(dm, R_0x900, 0x00000002, 0x0);\n\todm_set_bb_reg(dm, R_0x900, 0x00000004, 0x0);\n\todm_set_bb_reg(dm, R_0x9b0, 0x00000003, 0x0);\n\todm_set_bb_reg(dm, R_0x9b0, 0x00000f00, 0x0);\n\todm_set_bb_reg(dm, R_0x1eb4, 0x000fffff, 0x0);\n\todm_set_bb_reg(dm, R_0x9b8, 0xffff0000, 0x80);\n\todm_set_bb_reg(dm, R_0xa58, 0x003f8000, 0x13);\n\todm_set_bb_reg(dm, R_0x908, 0x00ffffff, 0x020d2b);\n\todm_set_bb_reg(dm, R_0x90c, 0x00ffffff, 0x040007);\n\todm_set_bb_reg(dm, R_0x910, 0x00ffffff, 0x029007);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0xde, 0x10000, 0x1);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x56, 0x00fff, 0xc00);\n\todm_set_bb_reg(dm, R_0x1e70, 0x0000000f, 0x4);\n\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0x881);\n\n\treg = odm_get_bb_reg(dm, R_0x2dbc, 0x00000fff);\n\treg = (1024 - ((reg >> 2) & 0x000003ff)) & 0x000003ff;\n\todm_set_bb_reg(dm, R_0x189c, 0x0003ff00, reg);\n\n\todm_set_bb_reg(dm, R_0x1e70, 0x0000000f, 0x2);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0xde, 0x10000, 0x0);\n\todm_set_bb_reg(dm, R_0x1d08, 0x00000001, 0x0);\n\n\t/*path s1*/\n\todm_set_bb_reg(dm, R_0x1d08, 0x00000001, 0x1);\n\todm_set_bb_reg(dm, R_0x900, 0x0f000000, 0x0);\n\todm_set_bb_reg(dm, R_0x900, 0x30000000, 0x0);\n\todm_set_bb_reg(dm, R_0x900, 0xc0000000, 0x0);\n\todm_set_bb_reg(dm, R_0x900, 0x00000001, 0x1);\n\todm_set_bb_reg(dm, R_0x900, 0x00000002, 0x0);\n\todm_set_bb_reg(dm, R_0x900, 0x00000004, 0x0);\n\todm_set_bb_reg(dm, R_0x9b0, 0x00000003, 0x0);\n\todm_set_bb_reg(dm, R_0x9b0, 0x00000f00, 0x0);\n\todm_set_bb_reg(dm, R_0x1eb4, 0x000fffff, 0x0);\n\todm_set_bb_reg(dm, R_0x9b8, 0xffff0000, 0x80);\n\todm_set_bb_reg(dm, R_0xa58, 0x003f8000, 0x13);\n\todm_set_bb_reg(dm, R_0x908, 0x00ffffff, 0x020d2b);\n\todm_set_bb_reg(dm, R_0x90c, 0x00ffffff, 0x040007);\n\todm_set_bb_reg(dm, R_0x910, 0x00ffffff, 0x029007);\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0xde, 0x10000, 0x1);\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0x56, 0x00fff, 0xc00);\n\todm_set_bb_reg(dm, R_0x1e70, 0x0000000f, 0x4);\n\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0xa81);\n\n\treg = odm_get_bb_reg(dm, R_0x2dbc, 0x00000fff);\n\treg = (1024 - ((reg >> 2) & 0x000003ff)) & 0x000003ff;\n\todm_set_bb_reg(dm, R_0x419c, 0x0003ff00, reg);\n\n\todm_set_bb_reg(dm, R_0x1e70, 0x0000000f, 0x2);\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0xde, 0x10000, 0x0);\n\todm_set_bb_reg(dm, R_0x1d08, 0x00000001, 0x0);\n#endif\n}\n\nu8 _halrf_driver_rate_to_tssi_rate_8822c(\n\tvoid *dm_void, u8 rate)\n{\n\tu8 tssi_rate = 0;\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (rate == MGN_1M)\n\t\ttssi_rate = 0;\n\telse if (rate == MGN_2M)\n\t\ttssi_rate = 1;\n\telse if (rate == MGN_5_5M)\n\t\ttssi_rate = 2;\n\telse if (rate == MGN_11M)\n\t\ttssi_rate = 3;\n\telse if (rate == MGN_6M)\n\t\ttssi_rate = 4;\n\telse if (rate == MGN_9M)\n\t\ttssi_rate = 5;\n\telse if (rate == MGN_12M)\n\t\ttssi_rate = 6;\n\telse if (rate == MGN_18M)\n\t\ttssi_rate = 7;\n\telse if (rate == MGN_24M)\n\t\ttssi_rate = 8;\n\telse if (rate == MGN_36M)\n\t\ttssi_rate = 9;\n\telse if (rate == MGN_48M)\n\t\ttssi_rate = 10;\n\telse if (rate == MGN_54M)\n\t\ttssi_rate = 11;\n\telse if (rate >= MGN_MCS0 && rate <= MGN_VHT4SS_MCS9)\n\t\ttssi_rate = rate - MGN_MCS0 + 12;\n\telse\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s not exit tx rate\\n\", __func__);\n#endif\n\treturn tssi_rate;\n}\n\nu8 _halrf_tssi_rate_to_driver_rate_8822c(\n\tvoid *dm_void, u8 rate)\n{\n\tu8 driver_rate = 0;\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (rate == 0)\n\t\tdriver_rate = MGN_1M;\n\telse if (rate == 1)\n\t\tdriver_rate = MGN_2M;\n\telse if (rate == 2)\n\t\tdriver_rate = MGN_5_5M;\n\telse if (rate == 3)\n\t\tdriver_rate = MGN_11M;\n\telse if (rate == 4)\n\t\tdriver_rate = MGN_6M;\n\telse if (rate == 5)\n\t\tdriver_rate = MGN_9M;\n\telse if (rate == 6)\n\t\tdriver_rate = MGN_12M;\n\telse if (rate == 7)\n\t\tdriver_rate = MGN_18M;\n\telse if (rate == 8)\n\t\tdriver_rate = MGN_24M;\n\telse if (rate == 9)\n\t\tdriver_rate = MGN_36M;\n\telse if (rate == 10)\n\t\tdriver_rate = MGN_48M;\n\telse if (rate == 11)\n\t\tdriver_rate = MGN_54M;\n\telse if (rate >= 12 && rate <= 83)\n\t\tdriver_rate = rate + MGN_MCS0 - 12;\n\telse\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s not exit tx rate\\n\", __func__);\n#endif\n\treturn driver_rate;\n}\n\nvoid _halrf_calculate_txagc_codeword_8822c(\n\tvoid *dm_void, u16 *tssi_value,  s16 *txagc_value)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\n\tu32 i, mcs7 = 19;\n\n\tfor (i = 0; i < TSSI_CODE_NUM; i++) {\n\t\ttxagc_value[i] =\n\t\t\t((tssi_value[i] - tssi->tssi_codeword[mcs7]) / TSSI_TXAGC_DIFF) & 0x7f;\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s txagc_value[%d](0x%x) = ((tssi_value[%d](%d) - tssi_value[mcs7](%d)) / %d) & 0x7f\\n\",\n\t\t       __func__, i, txagc_value[i], i, tssi_value[i], tssi_value[mcs7], TSSI_TXAGC_DIFF);\n\t}\n#endif\n}\n\ns8 _halrf_get_efuse_tssi_offset_8822c(\n\tvoid *dm_void, u8 rate)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\tu8 channel = *dm->channel;\n\ts8 offset = 0;\n\tu32 offset_index = 0;\n\t//u8 bandwidth = *dm->band_width;\n\t//u8 rate = phydm_get_tx_rate(dm);\n\n\tif (rate >= 0 && rate <= 3) {\n\t\tif (channel >= 1 && channel <= 2)\n\t\t\toffset_index = 0;\n\t\telse if (channel >= 3 && channel <= 5)\n\t\t\toffset_index = 1;\n\t\telse if (channel >= 6 && channel <= 8)\n\t\t\toffset_index = 2;\n\t\telse if (channel >= 9 && channel <= 11)\n\t\t\toffset_index = 3;\n\t\telse if (channel >= 12 && channel <= 13)\n\t\t\toffset_index = 4;\n\t\telse if (channel == 14)\n\t\t\toffset_index = 5;\n\t} else {\n\t\tif (channel >= 1 && channel <= 2)\n\t\t\toffset_index = 6;\n\t\telse if (channel >= 3 && channel <= 5)\n\t\t\toffset_index = 7;\n\t\telse if (channel >= 6 && channel <= 8)\n\t\t\toffset_index = 8;\n\t\telse if (channel >= 9 && channel <= 11)\n\t\t\toffset_index = 9;\n\t\telse if (channel >= 12 && channel <= 14)\n\t\t\toffset_index = 10;\n\t\telse if (channel >= 36 && channel <= 40)\n\t\t\toffset_index = 11;\n\t\telse if (channel >= 44 && channel <= 48)\n\t\t\toffset_index = 12;\n\t\telse if (channel >= 52 && channel <= 56)\n\t\t\toffset_index = 13;\n\t\telse if (channel >= 60 && channel <= 64)\n\t\t\toffset_index = 14;\n\t\telse if (channel >= 100 && channel <= 104)\n\t\t\toffset_index = 15;\n\t\telse if (channel >= 108 && channel <= 112)\n\t\t\toffset_index = 16;\n\t\telse if (channel >= 116 && channel <= 120)\n\t\t\toffset_index = 17;\n\t\telse if (channel >= 124 && channel <= 128)\n\t\t\toffset_index = 18;\n\t\telse if (channel >= 132 && channel <= 136)\n\t\t\toffset_index = 19;\n\t\telse if (channel >= 140 && channel <= 144)\n\t\t\toffset_index = 20;\n\t\telse if (channel >= 149 && channel <= 153)\n\t\t\toffset_index = 21;\n\t\telse if (channel >= 157 && channel <= 161)\n\t\t\toffset_index = 22;\n\t\telse if (channel >= 165 && channel <= 169)\n\t\t\toffset_index = 23;\n\t\telse if (channel >= 173 && channel <= 177)\n\t\t\toffset_index = 24;\n\n\t}\n\n\treturn offset = tssi->tssi_efuse[0][offset_index];\n}\n\ns8 _halrf_get_kfree_tssi_offset_8822c(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\tu8 channel = *dm->channel;\n\ts8 offset = 0;\n\tu32 offset_index = 0;\n\n\tif (channel >= 1 && channel <= 14)\n\t\toffset_index = 0;\n\telse if (channel >= 36 && channel <= 64)\n\t\toffset_index = 1;\n\telse if (channel >= 100 && channel <= 144)\n\t\toffset_index = 2;\n\telse if (channel >= 149 && channel <= 177)\n\t\toffset_index = 3;\n\n\treturn offset = tssi->tssi_kfree_efuse[0][offset_index];\n}\n\n\nvoid _halrf_calculate_tssi_codeword_8822c(\n\tvoid *dm_void)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\n\tu8 i, band, base_rate_power = 0, base_rate_index = 0, rate_index = 0, base_mcs = 0;\n\ts8 diff_base_pwr, diff_pwr;\n\tu8 channel = *dm->channel, bandwidth = *dm->band_width, tssi_slope;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"===>%s channel=%d bandwidth=%d\\n\", __func__, channel, bandwidth);\n\n\tif (channel >= 1 && channel <= 14) {\n\t\tband = BAND_ON_2_4G;\n\t\ttssi_slope = TSSI_SLOPE_2G;\n\t} else {\n\t\tband = BAND_ON_5G;\n\t\ttssi_slope = TSSI_SLOPE_5G;\n\t}\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"===>%s CCK=%d OFDM=%d MCS7=%d VHTMCS7=%d\\n\",\n\t       __func__,\n\t       phydm_get_tx_power_by_rate_base(dm, band,\n\t\t\t\t\tRF_PATH_A, RF_1TX, CCK),\n\t       phydm_get_tx_power_by_rate_base(dm, band,\n\t\t\t\t\tRF_PATH_A, RF_1TX, OFDM),\n\t       phydm_get_tx_power_by_rate_base(dm, band,\n\t\t\t\t\tRF_PATH_A, RF_1TX, HT_MCS0_MCS7),\n\t       phydm_get_tx_power_by_rate_base(dm, band,\n\t\t\t\t\tRF_PATH_A, RF_1TX, VHT_1SSMCS0_1SSMCS9)\n\t       );\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"===>%s base rate drff  MCS7=%d MCS6=%d MCS5=%d MCS4=%d\\n\",\n\t       __func__,\n\t       odm_get_tx_power_index(dm, RF_PATH_A, MGN_MCS7, bandwidth, channel),\n\t       odm_get_tx_power_index(dm, RF_PATH_A, MGN_MCS6, bandwidth, channel),\n\t       odm_get_tx_power_index(dm, RF_PATH_A, MGN_MCS5, bandwidth, channel),\n\t       odm_get_tx_power_index(dm, RF_PATH_A, MGN_MCS4, bandwidth, channel)\n\t       );\n\n\tbase_mcs = phydm_get_tx_power_by_rate_base(dm, band,\n\t\t\t\t\tRF_PATH_A, RF_1TX, HT_MCS0_MCS7) / POWER_INDEX_DIFF;\n\n\tfor (i = 0; i < TSSI_CODE_NUM; i++) {\n\t\tif (i >= 28 && i <= 43)\n\t\t\tcontinue;\n\t\tif (i >= 64 && i < TSSI_CODE_NUM)\n\t\t\tcontinue;\n\t\t\n\t\t/*cck 1m ~ cck11m*/\n\t\tif (i >= 0 && i <= 3) {\n\t\t\tbase_rate_power = phydm_get_tx_power_by_rate_base(dm, BAND_ON_2_4G,\n\t\t\t\t\t\tRF_PATH_A, RF_1TX, CCK) / POWER_INDEX_DIFF;\n\t\t\tbase_rate_index = odm_get_tx_power_index(dm, RF_PATH_A, MGN_11M, bandwidth, channel);\n\t\t\trate_index = odm_get_tx_power_index(dm, RF_PATH_A, _halrf_tssi_rate_to_driver_rate_8822c(dm, i), bandwidth, channel);\n\t\t} else if (i >= 4 && i <= 11) { /*ofdm6m~ofdm54m*/\n\t\t\tbase_rate_power = phydm_get_tx_power_by_rate_base(dm, band,\n\t\t\t\t\t\tRF_PATH_A, RF_1TX, OFDM) / POWER_INDEX_DIFF;\n\t\t\tbase_rate_index = odm_get_tx_power_index(dm, RF_PATH_A, MGN_54M, bandwidth, channel);\n\t\t\trate_index = odm_get_tx_power_index(dm, RF_PATH_A, _halrf_tssi_rate_to_driver_rate_8822c(dm, i), bandwidth, channel);\n\t\t} else if (i >= 12 && i <= 19) { /*mcs0~mcs7*/\n\t\t\tbase_rate_power = phydm_get_tx_power_by_rate_base(dm, band,\n\t\t\t\t\t\tRF_PATH_A, RF_1TX, HT_MCS0_MCS7) / POWER_INDEX_DIFF;\n\t\t\tbase_rate_index = odm_get_tx_power_index(dm, RF_PATH_A, MGN_MCS7, bandwidth, channel);\n\t\t\trate_index = odm_get_tx_power_index(dm, RF_PATH_A, _halrf_tssi_rate_to_driver_rate_8822c(dm, i), bandwidth, channel);\n\t\t} else if (i >= 20 && i <= 27) { /*mcs8~mcs15*/\n\t\t\tbase_rate_power = phydm_get_tx_power_by_rate_base(dm, band,\n\t\t\t\t\t\tRF_PATH_A, RF_2TX, HT_MCS8_MCS15) / POWER_INDEX_DIFF;\n\t\t\tbase_rate_index = odm_get_tx_power_index(dm, RF_PATH_A, MGN_MCS15, bandwidth, channel);\n\t\t\trate_index = odm_get_tx_power_index(dm, RF_PATH_A, _halrf_tssi_rate_to_driver_rate_8822c(dm, i), bandwidth, channel);\n\t\t} else if (i >= 44 && i <= 53) { /*vhtmcs0~vhtmcs9*/\n\t\t\tbase_rate_power = phydm_get_tx_power_by_rate_base(dm, band,\n\t\t\t\t\t\tRF_PATH_A, RF_1TX, VHT_1SSMCS0_1SSMCS9) / POWER_INDEX_DIFF;\n\t\t\t\n\t\t\tbase_rate_index = odm_get_tx_power_index(dm, RF_PATH_A, MGN_VHT1SS_MCS7, bandwidth, channel);\n\t\t\trate_index = odm_get_tx_power_index(dm, RF_PATH_A, _halrf_tssi_rate_to_driver_rate_8822c(dm, i), bandwidth, channel);\n\t\t} else if (i >= 54 && i <= 63) { /*vht2mcs0~vht2mcs9*/\n\t\t\tbase_rate_power = phydm_get_tx_power_by_rate_base(dm, band,\n\t\t\t\t\t\tRF_PATH_A, RF_2TX, VHT_2SSMCS0_2SSMCS9) / POWER_INDEX_DIFF;\n\t\t\t\n\t\t\tbase_rate_index = odm_get_tx_power_index(dm, RF_PATH_A, MGN_VHT2SS_MCS7, bandwidth, channel);\n\t\t\trate_index = odm_get_tx_power_index(dm, RF_PATH_A, _halrf_tssi_rate_to_driver_rate_8822c(dm, i), bandwidth, channel);\n\t\t}\n\n\t\tdiff_base_pwr = base_rate_power - base_mcs;\n\n\t\tdiff_pwr = (rate_index - base_rate_index) / POWER_INDEX_DIFF;\n\t\ttssi->tssi_codeword[i] = (base_mcs + diff_base_pwr + diff_pwr) * tssi_slope;\n\t\t/*tssi->tssi_codeword[i] = tssi->tssi_codeword[i] + _halrf_get_efuse_tssi_offset_8822c(dm, i);*/\n\t\t/*tssi->tssi_codeword[i] = tssi->tssi_codeword[i] + _halrf_get_kfree_tssi_offset_8822c(dm);*/\n\n\t\tif (((s16)tssi->tssi_codeword[i]) < 0)\n\t\t\ttssi->tssi_codeword[i] = 0;\n\t\telse if (tssi->tssi_codeword[i] > 255)\n\t\t\ttssi->tssi_codeword[i] = 255;\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s diff_base_pwr(%d) = base_rate_power(%d) - base_mcs(%d)\\n\",\n\t\t       __func__, diff_base_pwr, base_rate_power, base_mcs);\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s diff_pwr(%d) = (rate_index(%d) - base_rate_index(%d)) / POWER_INDEX_DIFF(%d)\\n\",\n\t\t       __func__, diff_pwr, rate_index, base_rate_index, POWER_INDEX_DIFF);\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s tssi->tssi_codeword[%d]=0x%x = (base_mcs(%d) + diff_base_pwr(%d) + diff_pwr(%d)) * tssi_slope(%d)\\n\\n\",\n\t\t       __func__, i, tssi->tssi_codeword[i], base_mcs, diff_base_pwr, diff_pwr, tssi_slope);\n\t}\n\n\tfor (i = 28; i <= 35; i++)\n\t\ttssi->tssi_codeword[i] = tssi->tssi_codeword[i - 8];\n\n\tfor (i = 36; i <= 43; i++)\n\t\ttssi->tssi_codeword[i] = tssi->tssi_codeword[i - 16];\n\n\tfor (i = 64; i <= 73; i++) \n\t\ttssi->tssi_codeword[i] = tssi->tssi_codeword[i - 10];\n\n\tfor (i = 74; i <= 83; i++)\n\t\ttssi->tssi_codeword[i] = tssi->tssi_codeword[i - 20];\n#endif\n}\n\n\n\n\nvoid _halrf_calculate_set_thermal_codeword_8822c(\n\tvoid *dm_void)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\n\tu8 channel = *dm->channel, i, thermal;\n\ts8 j;\n\tu8 rate = phydm_get_tx_rate(dm);\n\tu32 thermal_offset_tmp = 0, thermal_offset_index = 0x10, thermal_tmp;\n\ts8 thermal_offset[64] = {0};\n\tu8 thermal_up_a[DELTA_SWINGIDX_SIZE] = {0}, thermal_down_a[DELTA_SWINGIDX_SIZE] = {0};\n\tu8 thermal_up_b[DELTA_SWINGIDX_SIZE] = {0}, thermal_down_b[DELTA_SWINGIDX_SIZE] = {0};\n\n\ttssi->thermal[RF_PATH_A] = 0xff;\n\ttssi->thermal[RF_PATH_B] = 0xff;\n\n\t/*path s0*/\n\todm_efuse_logical_map_read(dm, 1, 0xd0, &thermal_tmp);\n\tthermal = (u8)thermal_tmp;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"===>%s channel=%d thermal pahtA=0x%x\\n\", __func__, channel, thermal);\n\n\tif (thermal == 0xff) {\n\t\t/*thermal = 0x20;*/\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s thermal=0x%x return!!!\\n\", __func__, thermal);\n\t\treturn;\n\t}\n\n\ttssi->thermal[RF_PATH_A] = thermal;\n\n\t/*path s0*/\n\todm_set_bb_reg(dm, R_0x1c20, 0x000fc000, (thermal & 0x3f));\n\n\tif (rate == MGN_1M || rate == MGN_2M || rate == MGN_5_5M || rate == MGN_11M) {\n\t\todm_move_memory(dm, thermal_up_a, cali_info->delta_swing_table_idx_2g_cck_a_p, sizeof(thermal_up_a));\n\t\todm_move_memory(dm, thermal_down_a, cali_info->delta_swing_table_idx_2g_cck_a_n, sizeof(thermal_down_a));\n\t\todm_move_memory(dm, thermal_up_b, cali_info->delta_swing_table_idx_2g_cck_b_p, sizeof(thermal_up_b));\n\t\todm_move_memory(dm, thermal_down_b, cali_info->delta_swing_table_idx_2g_cck_b_n, sizeof(thermal_down_b));\n\t} else if (channel >= 1 && channel <= 14) {\n\t\todm_move_memory(dm, thermal_up_a, cali_info->delta_swing_table_idx_2ga_p, sizeof(thermal_up_a));\n\t\todm_move_memory(dm, thermal_down_a, cali_info->delta_swing_table_idx_2ga_n, sizeof(thermal_down_a));\n\t\todm_move_memory(dm, thermal_up_b, cali_info->delta_swing_table_idx_2gb_p, sizeof(thermal_up_b));\n\t\todm_move_memory(dm, thermal_down_b, cali_info->delta_swing_table_idx_2gb_n, sizeof(thermal_down_b));\n\t} else if (channel >= 36 && channel <= 64) {\n\t\todm_move_memory(dm, thermal_up_a, cali_info->delta_swing_table_idx_5ga_p[0], sizeof(thermal_up_a));\n\t\todm_move_memory(dm, thermal_down_a, cali_info->delta_swing_table_idx_5ga_n[0], sizeof(thermal_down_a));\n\t\todm_move_memory(dm, thermal_up_b, cali_info->delta_swing_table_idx_5gb_p[0], sizeof(thermal_up_b));\n\t\todm_move_memory(dm, thermal_down_b, cali_info->delta_swing_table_idx_5gb_n[0], sizeof(thermal_down_b));\n\t} else if (channel >= 100 && channel <= 144) {\n\t\todm_move_memory(dm, thermal_up_a, cali_info->delta_swing_table_idx_5ga_p[1], sizeof(thermal_up_a));\n\t\todm_move_memory(dm, thermal_down_a, cali_info->delta_swing_table_idx_5ga_n[1], sizeof(thermal_down_a));\n\t\todm_move_memory(dm, thermal_up_b, cali_info->delta_swing_table_idx_5gb_p[1], sizeof(thermal_up_b));\n\t\todm_move_memory(dm, thermal_down_b, cali_info->delta_swing_table_idx_5gb_n[1], sizeof(thermal_down_b));\n\t} else if (channel >= 149 && channel <= 177) {\n\t\todm_move_memory(dm, thermal_up_a, cali_info->delta_swing_table_idx_5ga_p[2], sizeof(thermal_up_a));\n\t\todm_move_memory(dm, thermal_down_a, cali_info->delta_swing_table_idx_5ga_n[2], sizeof(thermal_down_a));\n\t\todm_move_memory(dm, thermal_up_b, cali_info->delta_swing_table_idx_5gb_p[2], sizeof(thermal_up_b));\n\t\todm_move_memory(dm, thermal_down_b, cali_info->delta_swing_table_idx_5gb_n[2], sizeof(thermal_down_b));\n\t}\n\n\t/*path s0*/\n\ti = 0;\n\tfor (j = thermal; j >= 0; j--) {\n\t\tif (i < DELTA_SWINGIDX_SIZE)\n\t\t\tthermal_offset[j] = thermal_down_a[i++];\n\t\telse\n\t\t\tthermal_offset[j] = thermal_down_a[DELTA_SWINGIDX_SIZE - 1];\n\t}\n\n\ti = 0;\n\tfor (j = thermal; j < 64; j++) {\n\t\tif (i < DELTA_SWINGIDX_SIZE)\n\t\t\tthermal_offset[j] = -1 * thermal_up_a[i++];\n\t\telse\n\t\t\tthermal_offset[j] = -1 * thermal_up_a[DELTA_SWINGIDX_SIZE - 1];\n\t}\n\n\tfor (i = 0; i < 64; i = i + 4) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s thermal_offset[%.2d]=%.2x %.2x %.2x %.2x\\n\",\n\t\t       __func__, i, thermal_offset[i] & 0xff, thermal_offset[i + 1] & 0xff,\n\t\t       thermal_offset[i + 2] & 0xff, thermal_offset[i + 3] & 0xff);\n\t}\n\n\ti = 0;\n\twhile (i < 64) {\n\t\tthermal_offset_tmp = 0;\n\t\tfor (j = 0; j < 23; j = j + 6)\n\t\t\tthermal_offset_tmp = thermal_offset_tmp | ((thermal_offset[i++] & 0x3f) << j);\n\n\t\tthermal_offset_tmp = thermal_offset_tmp | ((thermal_offset_index++ & 0xff) << 24);\n\n\t\todm_set_bb_reg(dm, 0x18f4, MASKDWORD, thermal_offset_tmp);\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s write addr:0x%x value=0x%08x\\n\",\n\t\t       __func__, 0x18f4, thermal_offset_tmp);\n\t}\n\n\n\n\t/*path s1*/\n\todm_efuse_logical_map_read(dm, 1, 0xd1, &thermal_tmp);\n\tthermal = (u8)thermal_tmp;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"===>%s channel=%d thermal pahtB=0x%x\\n\", __func__, channel, thermal);\n\n\tif (thermal == 0xff) {\n\t\t/*thermal = 0x20;*/\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s thermal=0x%x return!!!\\n\", __func__, thermal);\n\t\treturn;\n\t}\n\n\ttssi->thermal[RF_PATH_B] = thermal;\n\n\t/*path s1*/\n\todm_set_bb_reg(dm, R_0x1c20, 0x03f00000, (thermal & 0x3f));\n\n\t/*path s1*/\n\ti = 0;\n\tfor (j = thermal; j >= 0; j--) {\n\t\tif (i < DELTA_SWINGIDX_SIZE)\n\t\t\tthermal_offset[j] = thermal_down_b[i++];\n\t\telse\n\t\t\tthermal_offset[j] = thermal_down_b[DELTA_SWINGIDX_SIZE - 1];\n\t}\n\n\ti = 0;\n\tfor (j = thermal; j < 64; j++) {\n\t\tif (i < DELTA_SWINGIDX_SIZE)\n\t\t\tthermal_offset[j] = -1 * thermal_up_b[i++];\n\t\telse\n\t\t\tthermal_offset[j] = -1 * thermal_up_b[DELTA_SWINGIDX_SIZE - 1];\n\t}\n\n\tfor (i = 0; i < 64; i = i + 4) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s thermal_offset[%.2d]=%.2x %.2x %.2x %.2x\\n\",\n\t\t       __func__, i, thermal_offset[i] & 0xff, thermal_offset[i + 1] & 0xff,\n\t\t       thermal_offset[i + 2] & 0xff, thermal_offset[i + 3] & 0xff);\n\t}\n\n\tthermal_offset_index = 0x10;\n\ti = 0;\n\twhile (i < 64) {\n\t\tthermal_offset_tmp = 0;\n\t\tfor (j = 0; j < 23; j = j + 6)\n\t\t\tthermal_offset_tmp = thermal_offset_tmp | ((thermal_offset[i++] & 0x3f) << j);\n\n\t\tthermal_offset_tmp = thermal_offset_tmp | ((thermal_offset_index++ & 0xff) << 24);\n\n\t\todm_set_bb_reg(dm, 0x41f4, MASKDWORD, thermal_offset_tmp);\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s write addr:0x%x value=0x%08x\\n\",\n\t\t       __func__, 0x41f4, thermal_offset_tmp);\n\t}\n#endif\n}\n\n\n\nvoid _halrf_set_txagc_codeword_8822c(\n\tvoid *dm_void, s16 *tssi_value)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 i, j, k = 0, tssi_value_tmp;\n\n\t/*power by rate table (tssi codeword)*/\n\tfor (i = 0x3a00; i <= R_0x3a50; i = i + 4) {\n\t\ttssi_value_tmp = 0;\n\n\t\tfor (j = 0; j < 31; j = j + 8)\n\t\t\ttssi_value_tmp = tssi_value_tmp | ((tssi_value[k++] & 0x7f) << j);\n\n\t\todm_set_bb_reg(dm, i, MASKDWORD, tssi_value_tmp);\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s write addr:0x%x value=0x%08x\\n\",\n\t\t       __func__, i, tssi_value_tmp);\n\t}\n#endif\n}\n\nvoid _halrf_set_tssi_codeword_8822c(\n\tvoid *dm_void, u16 *tssi_value)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 i, j, k = 0, tssi_value_tmp;\n\n\t/*power by rate table (tssi codeword)*/\n\tfor (i = 0x3a54; i <= 0x3aa4; i = i + 4) {\n\t\ttssi_value_tmp = 0;\n\n\t\tfor (j = 0; j < 31; j = j + 8)\n\t\t\ttssi_value_tmp = tssi_value_tmp | ((tssi_value[k++] & 0xff) << j);\n\n\t\todm_set_bb_reg(dm, i, MASKDWORD, tssi_value_tmp);\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s write addr:0x%x value=0x%08x\\n\",\n\t\t       __func__, i, tssi_value_tmp);\n\t}\n#endif\n}\n\nvoid _halrf_set_efuse_kfree_offset_8822c(\n\tvoid *dm_void)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\n\ts32 offset = 0;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"===>%s\\n\", __func__);\n\n\t/*path s0*/\n\t/*2G CCK*/\n\toffset = (_halrf_get_efuse_tssi_offset_8822c(dm, 3) +\n\t \t_halrf_get_kfree_tssi_offset_8822c(dm)) & 0xff;\n\todm_set_bb_reg(dm, R_0x18e8, 0x01fe0000, (u32)offset);\n\t\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s write addr:0x%x value=0x%08x\\n\",\n\t\t       __func__, R_0x18e8, offset);\n\n\t/*2G & 5G OFDM*/\n\toffset = (_halrf_get_efuse_tssi_offset_8822c(dm, 19) +\n\t \t_halrf_get_kfree_tssi_offset_8822c(dm)) & 0xff;\n\todm_set_bb_reg(dm, R_0x18a8, 0xff000000, (u32)offset);\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s write addr:0x%x value=0x%08x\\n\",\n\t\t       __func__, R_0x18a8, offset);\n\n\t/*path s1*/\n\t/*2G CCK*/\n\toffset = (_halrf_get_efuse_tssi_offset_8822c(dm, 3) +\n\t \t_halrf_get_kfree_tssi_offset_8822c(dm)) & 0xff;\n\todm_set_bb_reg(dm, R_0x1ef0, 0x0001fe00, (u32)offset);\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s write addr:0x%x value=0x%08x\\n\",\n\t\t       __func__, R_0x1ef0, offset);\n\n\t/*2G & 5G OFDM*/\n\toffset = (_halrf_get_efuse_tssi_offset_8822c(dm, 19) +\n\t \t_halrf_get_kfree_tssi_offset_8822c(dm)) & 0xff;\n\todm_set_bb_reg(dm, R_0x1eec, 0x3fc00000, (u32)offset);\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s write addr:0x%x value=0x%08x\\n\",\n\t\t       __func__, R_0x1eec, offset);\n#endif\n}\n\nvoid _halrf_tssi_init_8822c(\n\tvoid *dm_void)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\n\t_halrf_calculate_set_thermal_codeword_8822c(dm);\n\t_halrf_calculate_tssi_codeword_8822c(dm);\n\t_halrf_calculate_txagc_codeword_8822c(dm, tssi->tssi_codeword, tssi->txagc_codeword);\n\t_halrf_set_txagc_codeword_8822c(dm, tssi->txagc_codeword);\n\t_halrf_set_tssi_codeword_8822c(dm, tssi->tssi_codeword);\n\t_halrf_set_efuse_kfree_offset_8822c(dm);\n#endif\n}\n\nvoid _halrf_thermal_init_8822c(\n\tvoid *dm_void)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\n\t_halrf_calculate_set_thermal_codeword_8822c(dm);\n\t/*_halrf_calculate_tssi_codeword_8822c(dm);*/\n\t/*_halrf_calculate_txagc_codeword_8822c(dm, tssi->tssi_codeword, tssi->txagc_codeword);*/\n\t/*_halrf_set_txagc_codeword_8822c(dm, tssi->txagc_codeword);*/\n\t/*_halrf_set_tssi_codeword_8822c(dm, tssi->tssi_codeword);*/\n\t/*_halrf_set_efuse_kfree_offset_8822c(dm);*/\n#endif\n}\n\nvoid halrf_tssi_get_efuse_8822c(\n\tvoid *dm_void)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\n\tu8 pg_tssi = 0xff, i, j;\n\tu32 pg_tssi_tmp = 0xff;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"===>%s\\n\", __func__);\n\n\t/*path s0*/\n\tj = 0;\n\tfor (i = 0x10; i <= 0x1a; i++) {\n\t\todm_efuse_logical_map_read(dm, 1, i, &pg_tssi_tmp);\n\t\tpg_tssi = (u8)pg_tssi_tmp;\n\t\tif ((pg_tssi & BIT(6) >> 6) == 0) {\n\t\t\tpg_tssi = (pg_tssi | ((pg_tssi & BIT(7)) >> 1)) & 0x7f;\n\t\t\tif (pg_tssi & BIT(6))\n\t\t\t\ttssi->tssi_efuse[0][j] = (s8)(pg_tssi - 128);\n\t\t\telse\n\t\t\t\ttssi->tssi_efuse[0][j] = (s8)pg_tssi;\n\t\t}\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\"tssi->tssi_efuse[%d][%d]=%d\\n\", 0, j, tssi->tssi_efuse[0][j]);\n\t\tj++;\n\t}\n\n\tfor (i = 0x22; i <= 0x2f; i++) {\n\t\todm_efuse_logical_map_read(dm, 1, i, &pg_tssi_tmp);\n\t\tpg_tssi = (u8)pg_tssi_tmp;\n\t\tif ((pg_tssi & BIT(6) >> 6) == 0) {\n\t\t\tpg_tssi = (pg_tssi | ((pg_tssi & BIT(7)) >> 1)) & 0x7f;\n\t\t\tif (pg_tssi & BIT(6))\n\t\t\t\ttssi->tssi_efuse[0][j] = (s8)(pg_tssi - 128);\n\t\t\telse\n\t\t\t\ttssi->tssi_efuse[0][j] = (s8)pg_tssi;\n\t\t}\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\"tssi->tssi_efuse[%d][%d]=%d\\n\", 0, j, tssi->tssi_efuse[0][j]);\n\t\tj++;\n\t}\n\n\t/*path s1*/\n\tj = 0;\n\tfor (i = 0x3a; i <= 0x44; i++) {\n\t\todm_efuse_logical_map_read(dm, 1, i, &pg_tssi_tmp);\n\t\tpg_tssi = (u8)pg_tssi_tmp;\n\t\tif ((pg_tssi & BIT(6) >> 6) == 0) {\n\t\t\tpg_tssi = (pg_tssi | ((pg_tssi & BIT(7)) >> 1)) & 0x7f;\n\t\t\tif (pg_tssi & BIT(6))\n\t\t\t\ttssi->tssi_efuse[1][j] = (s8)(pg_tssi - 128);\n\t\t\telse\n\t\t\t\ttssi->tssi_efuse[1][j] = (s8)pg_tssi;\n\t\t}\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\"tssi->tssi_efuse[%d][%d]=%d\\n\", 1, j, tssi->tssi_efuse[1][j]);\n\t\tj++;\n\t}\n\n\tfor (i = 0x4c; i <= 0x59; i++) {\n\t\todm_efuse_logical_map_read(dm, 1, i, &pg_tssi_tmp);\n\t\tpg_tssi = (u8)pg_tssi_tmp;\n\t\tif ((pg_tssi & BIT(6) >> 6) == 0) {\n\t\t\tpg_tssi = (pg_tssi | ((pg_tssi & BIT(7)) >> 1)) & 0x7f;\n\t\t\tif (pg_tssi & BIT(6))\n\t\t\t\ttssi->tssi_efuse[1][j] = (s8)(pg_tssi - 128);\n\t\t\telse\n\t\t\t\ttssi->tssi_efuse[1][j] = (s8)pg_tssi;\n\t\t}\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t\"tssi->tssi_efuse[%d][%d]=%d\\n\", 1, j, tssi->tssi_efuse[1][j]);\n\t\tj++;\n\t}\n#endif\n}\n\nvoid halrf_tssi_get_kfree_efuse_8822c(\n\tvoid *dm_void)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\n\tu8 pg_tssi = 0xff, i, j;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"===>%s\\n\", __func__);\n\n\t/*path s0*/\n\tj = 0;\n\todm_efuse_one_byte_read(dm, 0x1c0, &pg_tssi, false);\n\tif (((pg_tssi & BIT(7)) >> 7) == 0) {\n\t\tif ((pg_tssi & BIT(0)) == 0)\n\t\t\ttssi->tssi_kfree_efuse[0][j] = (-1 * (pg_tssi >> 1));\n\t\telse\n\t\t\ttssi->tssi_kfree_efuse[0][j] = (pg_tssi >> 1);\n\t}\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"tssi->tssi_kfree_efuse[%d][%d]=%d\\n\", 0, j, tssi->tssi_kfree_efuse[0][j]);\n\tj++;\n\n\todm_efuse_one_byte_read(dm, 0x1bc, &pg_tssi, false);\n\tif (((pg_tssi & BIT(7)) >> 7) == 0) {\n\t\tif ((pg_tssi & BIT(0)) == 0)\n\t\t\ttssi->tssi_kfree_efuse[0][j] = (-1 * (pg_tssi >> 1));\n\t\telse\n\t\t\ttssi->tssi_kfree_efuse[0][j] = (pg_tssi >> 1);\n\t}\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"tssi->tssi_kfree_efuse[%d][%d]=%d\\n\", 0, j, tssi->tssi_kfree_efuse[0][j]);\n\tj++;\n\n\todm_efuse_one_byte_read(dm, 0x1b8, &pg_tssi, false);\n\tif (((pg_tssi & BIT(7)) >> 7) == 0) {\n\t\tif ((pg_tssi & BIT(0)) == 0)\n\t\t\ttssi->tssi_kfree_efuse[0][j] = (-1 * (pg_tssi >> 1));\n\t\telse\n\t\t\ttssi->tssi_kfree_efuse[0][j] = (pg_tssi >> 1);\n\t}\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"tssi->tssi_kfree_efuse[%d][%d]=%d\\n\", 0, j, tssi->tssi_kfree_efuse[0][j]);\n\tj++;\n\n\todm_efuse_one_byte_read(dm, 0x3b4, &pg_tssi, false);\n\tif (((pg_tssi & BIT(7)) >> 7) == 0) {\n\t\tif ((pg_tssi & BIT(0)) == 0)\n\t\t\ttssi->tssi_kfree_efuse[0][j] = (-1 * (pg_tssi >> 1));\n\t\telse\n\t\t\ttssi->tssi_kfree_efuse[0][j] = (pg_tssi >> 1);\n\t}\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"tssi->tssi_kfree_efuse[%d][%d]=%d\\n\", 0, j, tssi->tssi_kfree_efuse[0][j]);\n\tj++;\n\n\t/*path s0*/\n\tj = 0;\n\todm_efuse_one_byte_read(dm, 0x1bf, &pg_tssi, false);\n\tif (((pg_tssi & BIT(7)) >> 7) == 0) {\n\t\tif ((pg_tssi & BIT(0)) == 0)\n\t\t\ttssi->tssi_kfree_efuse[0][j] = (-1 * (pg_tssi >> 1));\n\t\telse\n\t\t\ttssi->tssi_kfree_efuse[0][j] = (pg_tssi >> 1);\n\t}\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"tssi->tssi_kfree_efuse[%d][%d]=%d\\n\", 1, j, tssi->tssi_kfree_efuse[1][j]);\n\tj++;\n\n\todm_efuse_one_byte_read(dm, 0x1bb, &pg_tssi, false);\n\tif (((pg_tssi & BIT(7)) >> 7) == 0) {\n\t\tif ((pg_tssi & BIT(0)) == 0)\n\t\t\ttssi->tssi_kfree_efuse[0][j] = (-1 * (pg_tssi >> 1));\n\t\telse\n\t\t\ttssi->tssi_kfree_efuse[0][j] = (pg_tssi >> 1);\n\t}\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"tssi->tssi_kfree_efuse[%d][%d]=%d\\n\", 1, j, tssi->tssi_kfree_efuse[1][j]);\n\tj++;\n\n\todm_efuse_one_byte_read(dm, 0x3b7, &pg_tssi, false);\n\tif (((pg_tssi & BIT(7)) >> 7) == 0) {\n\t\tif ((pg_tssi & BIT(0)) == 0)\n\t\t\ttssi->tssi_kfree_efuse[0][j] = (-1 * (pg_tssi >> 1));\n\t\telse\n\t\t\ttssi->tssi_kfree_efuse[0][j] = (pg_tssi >> 1);\n\t}\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"tssi->tssi_kfree_efuse[%d][%d]=%d\\n\", 1, j, tssi->tssi_kfree_efuse[1][j]);\n\tj++;\n\n\todm_efuse_one_byte_read(dm, 0x3b3, &pg_tssi, false);\n\tif (((pg_tssi & BIT(7)) >> 7) == 0) {\n\t\tif ((pg_tssi & BIT(0)) == 0)\n\t\t\ttssi->tssi_kfree_efuse[0][j] = (-1 * (pg_tssi >> 1));\n\t\telse\n\t\t\ttssi->tssi_kfree_efuse[0][j] = (pg_tssi >> 1);\n\t}\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\"tssi->tssi_kfree_efuse[%d][%d]=%d\\n\", 1, j, tssi->tssi_kfree_efuse[1][j]);\n\tj++;\n\n#endif\n\n}\n\n\nvoid halrf_enable_tssi_8822c(\n\tvoid *dm_void)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"===>halrf_enable_tssi_8822c\\n\");\n\n\t/*path s0*/\n\todm_set_bb_reg(dm, R_0x1860, 0x00000800, 0x0);\n\todm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);\n\todm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x1);\n\n\t/*path s1*/\n\todm_set_bb_reg(dm, R_0x1860, 0x00000800, 0x0);\n\todm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);\n\todm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x1);\n#endif\n}\n\nvoid halrf_disable_tssi_8822c(\n\tvoid *dm_void)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"===>halrf_disable_tssi_8822c\\n\");\n\n\todm_set_bb_reg(dm, R_0x1e7c, 0x00800000, 0);\n\todm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xffa1005e);\n\n\t/*path s0*/\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70144041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70244041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70344041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70444041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705b8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70644041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x707b8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x708b8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x709b8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ab8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70bb8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70cb8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70db8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70eb8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70fb8041);\n\n\todm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1860, 0x00000800, 0x0);\n\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\todm_set_bb_reg(dm, R_0x18a0, 0x7f, 0x0);\n\n\t/*path s1*/\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700b8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70144041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70244041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70344041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70444041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705b8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70644041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x707b8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x708b8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x709b8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ab8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70bb8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70cb8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70db8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70eb8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70fb8041);\n\n\todm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1860, 0x00000800, 0x0);\n\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\todm_set_bb_reg(dm, R_0x41a0, 0x7f, 0x0);\n#endif\n}\n\nvoid halrf_do_tssi_8822c(\n\tvoid *dm_void)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);\n\tstruct _hal_rf_ *rf = &(dm->rf_table);\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\n\tu8 channel = *dm->channel;\n\tu8 rate = phydm_get_tx_rate(dm);\n\n\tif (tssi->index[RF_PATH_A][channel - 1] != 0 || tssi->index[RF_PATH_B][channel - 1] != 0) {\n\t\todm_set_bb_reg(dm, R_0x18e8, 0x0001fc00,\n\t\t\t       (tssi->index[RF_PATH_A][channel - 1] & 0x7f));\n\t\todm_set_bb_reg(dm, R_0x41e8, 0x0001fc00,\n\t\t\t       (tssi->index[RF_PATH_B][channel - 1] & 0x7f));\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s Set coex power index PathA:%d PathB:%d\\n\",\n\t\t       __func__, tssi->index[RF_PATH_A][channel - 1],\n\t\t       tssi->index[RF_PATH_B][channel - 1]);\n\t}\n\n\tif ((rf->rf_supportability & HAL_RF_TX_PWR_TRACK) == 1) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s\\n\", __func__);\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"rf_supportability HAL_RF_TX_PWR_TRACK on\\n\");\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s, return!\\n\", __func__);\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"rf_supportability HAL_RF_TX_PWR_TRACK off, return!!\\n\");\n\n\t\thalrf_disable_tssi_8822c(dm);\n\t\treturn;\n\t}\n\n\thalrf_disable_tssi_8822c(dm);\n\t_halrf_tssi_init_8822c(dm);\n\t/*_halrf_dc_offset_calibration_8822c(dm);*/\n\n\tif (rate == MGN_1M || rate == MGN_2M || rate == MGN_5_5M || rate == MGN_11M) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s, in CCK Rate return!!!\\n\", __func__);\n\t\treturn;\n\t}\n\n\t/*path s0*/\n\tif (channel >= 1 && channel <= 14) {\n\t\todm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xffff00bc);\n\t\todm_set_bb_reg(dm, R_0x1860, 0x00007000, 0x4);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x701f0044);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x702f0044);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x703f0044);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x704f0044);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x706f0044);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x707b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x708b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x709b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ab8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70bb8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70cb8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70db8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70eb8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70fb8041);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c24, 0x0001fe00, 0x20);\n\t\todm_set_bb_reg(dm, R_0x18ec, 0x00c00000, 0x2);\n\t\todm_set_bb_reg(dm, R_0x1834, 0x80000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18e0, 0x00000001, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18a8, 0x00000003, 0x2);\n\t\todm_set_bb_reg(dm, R_0x18a8, 0x00007ffc, 0x1266);\n\t\todm_set_bb_reg(dm, R_0x18a8, 0x00ff8000, 0x000);\n\t\todm_set_bb_reg(dm, R_0x18a8, 0xff000000, 0x00);\n\t\todm_set_bb_reg(dm, R_0x18e8, 0x000003fe, 0x110);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x7f, 0x00002, 0x1);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x65, 0x03000, 0x3);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x0000c, 0x3);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x000c0, 0x3);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x6e, 0x001e0, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x00800000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x180c, 0x08000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x180c, 0x40000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x1800, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x1804, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x1800, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1804, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18ec, 0x20000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18ec, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x186c, 0x0000ff00, 0xff);\n\t\todm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x18a0, 0x0000007f, 0x00);\n\t\todm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xffff00bc);\n\t\todm_set_bb_reg(dm, R_0x1860, 0x00007000, 0x2);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x701f0042);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x702f0042);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x703f0042);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x704f0042);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x706f0042);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x707b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x708b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x709b8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ab8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70bb8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70cb8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70db8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70eb8041);\n\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70fb8041);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c24, 0x0001fe00, 0x20);\n\t\todm_set_bb_reg(dm, R_0x18ec, 0x00c00000, 0x2);\n\t\todm_set_bb_reg(dm, R_0x1834, 0x80000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18e0, 0x00000001, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18a8, 0x00000003, 0x2);\n\t\todm_set_bb_reg(dm, R_0x18a8, 0x00007ffc, 0x1266);\n\t\todm_set_bb_reg(dm, R_0x18a8, 0x00ff8000, 0x000);\n\t\todm_set_bb_reg(dm, R_0x18a8, 0xff000000, 0x00);\n\t\todm_set_bb_reg(dm, R_0x18e8, 0x000003fe, 0x110);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x7f, 0x00100, 0x1);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x65, 0x03000, 0x3);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x00003, 0x3);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x00030, 0x3);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x6f, 0x001e0, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x00800000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x180c, 0x08000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x180c, 0x40000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x1800, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x1804, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x1800, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1804, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18ec, 0x20000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18ec, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x186c, 0x0000ff00, 0xff);\n\t\todm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x18a0, 0x0000007f, 0x00);\n\t\todm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);\n\t}\n\n#if 1\n\t/*path s1*/\n\tif (channel >= 1 && channel <= 14) {\n\t\todm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xffff00bc);\n\t\todm_set_bb_reg(dm, R_0x1860, 0x00007000, 0x4);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x701f0044);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x702f0044);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x703f0044);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x704f0044);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x706f0044);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x707b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x708b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x709b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ab8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70bb8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70cb8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70db8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70eb8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70fb8041);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1d04, 0x000ff000, 0x20);\n\t\todm_set_bb_reg(dm, R_0x41ec, 0x00c00000, 0x2);\n\t\todm_set_bb_reg(dm, R_0x4134, 0x80000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41e0, 0x00000001, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41a8, 0x00000003, 0x2);\n\t\todm_set_bb_reg(dm, R_0x1eec, 0x00001fff, 0x1266);\n\t\todm_set_bb_reg(dm, R_0x1eec, 0x003fe000, 0x000);\n\t\todm_set_bb_reg(dm, R_0x1eec, 0x3fc00000, 0x00);\n\t\todm_set_bb_reg(dm, R_0x1ef0, 0x000001ff, 0x110);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x7f, 0x00002, 0x1);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x65, 0x03000, 0x3);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x0000c, 0x3);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x000c0, 0x3);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x6e, 0x001e0, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x00800000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x410c, 0x08000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x410c, 0x40000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x4100, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x4104, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x4100, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x4104, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41ec, 0x20000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41ec, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1ef0, 0x01fe0000, 0xff);\n\t\todm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x41a0, 0x0000007f, 0x00);\n\t\todm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xffff00bc);\n\t\todm_set_bb_reg(dm, R_0x1860, 0x00007000, 0x2);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x701f0042);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x702f0042);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x703f0042);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x704f0042);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x706f0042);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x707b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x708b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x709b8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ab8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70bb8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70cb8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70db8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70eb8041);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70fb8041);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1d04, 0x000ff000, 0x20);\n\t\todm_set_bb_reg(dm, R_0x41ec, 0x00c00000, 0x2);\n\t\todm_set_bb_reg(dm, R_0x4134, 0x80000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41e0, 0x00000001, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41a8, 0x00000003, 0x2);\n\t\todm_set_bb_reg(dm, R_0x1eec, 0x00001fff, 0x1266);\n\t\todm_set_bb_reg(dm, R_0x1eec, 0x003fe000, 0x000);\n\t\todm_set_bb_reg(dm, R_0x1eec, 0x3fc00000, 0x00);\n\t\todm_set_bb_reg(dm, R_0x1ef0, 0x000001ff, 0x110);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x7f, 0x00100, 0x1);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x65, 0x03000, 0x3);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x00003, 0x3);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x00030, 0x3);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x6f, 0x001e0, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x00800000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x410c, 0x08000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x410c, 0x40000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x4100, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x4104, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x4100, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x4104, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41ec, 0x20000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41ec, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1ef0, 0x01fe0000, 0xff);\n\t\todm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x41a0, 0x0000007f, 0x00);\n\t\todm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);\n\t}\n#endif\n\thalrf_enable_tssi_8822c(dm);\n#endif\n}\n\nvoid halrf_do_thermal_8822c(\n\tvoid *dm_void)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);\n\tstruct _hal_rf_ *rf = &(dm->rf_table);\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\n\tu8 channel = *dm->channel;\n\tu8 rate = phydm_get_tx_rate(dm);\n\n\tif (tssi->index[RF_PATH_A][channel - 1] != 0 || tssi->index[RF_PATH_B][channel - 1] != 0) {\n\t\todm_set_bb_reg(dm, R_0x18e8, 0x0001fc00,\n\t\t\t       (tssi->index[RF_PATH_A][channel - 1] & 0x7f));\n\t\todm_set_bb_reg(dm, R_0x41e8, 0x0001fc00,\n\t\t\t       (tssi->index[RF_PATH_B][channel - 1] & 0x7f));\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s Set coex power index PathA:%d PathB:%d\\n\",\n\t\t       __func__, tssi->index[RF_PATH_A][channel - 1],\n\t\t       tssi->index[RF_PATH_B][channel - 1]);\n\t}\n\n\tif ((rf->rf_supportability & HAL_RF_TX_PWR_TRACK) == 1) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s\\n\", __func__);\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"rf_supportability HAL_RF_TX_PWR_TRACK on\\n\");\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s, return!\\n\", __func__);\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"rf_supportability HAL_RF_TX_PWR_TRACK off, return!!\\n\");\n\n\t\thalrf_disable_tssi_8822c(dm);\n\t\treturn;\n\t}\n\n\tif (tssi->thermal[0] == 0xff || tssi->thermal[1] == 0xff) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s thermal[0]=0x%x thermal[1]=0x%x return!!!\\n\",\n\t\t       __func__, tssi->thermal[RF_PATH_A], tssi->thermal[RF_PATH_B]);\n\t\treturn;\n\t}\n\n\thalrf_disable_tssi_8822c(dm);\n\t_halrf_thermal_init_8822c(dm);\n\t\n\t/*_halrf_dc_offset_calibration_8822c(dm);*/\n\n\tif (rate == MGN_1M || rate == MGN_2M || rate == MGN_5_5M || rate == MGN_11M) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s, in CCK Rate return!!!\\n\", __func__);\n\t\treturn;\n\t}\n\n\t/*path s0*/\n\tif (channel >= 1 && channel <= 14) {\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c24, 0x0001fe00, 0x20);\n\t\todm_set_bb_reg(dm, R_0x18ec, 0x00c00000, 0x3);\n\t\todm_set_bb_reg(dm, R_0x1834, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18e0, 0x00000001, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18a8, 0x00000003, 0x2);\n\t\todm_set_bb_reg(dm, R_0x18a8, 0x00007ffc, 0x0000);\n\t\todm_set_bb_reg(dm, R_0x18a8, 0x00ff8000, 0x000);\n\t\todm_set_bb_reg(dm, R_0x18a8, 0xff000000, 0x00);\n\t\todm_set_bb_reg(dm, R_0x18e8, 0x000003fe, 0x000);\n\t\todm_set_bb_reg(dm, R_0x18ec, 0x20000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x186c, 0x0000ff00, 0xff);\n\t\todm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);\n\t\todm_set_bb_reg(dm, R_0x18a0, 0x0000007f, 0x00);\n\t\todm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x1);\t\t\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c24, 0x0001fe00, 0x20);\n\t\todm_set_bb_reg(dm, R_0x18ec, 0x00c00000, 0x3);\n\t\todm_set_bb_reg(dm, R_0x1834, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18e0, 0x00000001, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18a8, 0x00000003, 0x2);\n\t\todm_set_bb_reg(dm, R_0x18a8, 0x00007ffc, 0x0000);\n\t\todm_set_bb_reg(dm, R_0x18a8, 0x00ff8000, 0x000);\n\t\todm_set_bb_reg(dm, R_0x18a8, 0xff000000, 0x00);\n\t\todm_set_bb_reg(dm, R_0x18e8, 0x000003fe, 0x000);\n\t\todm_set_bb_reg(dm, R_0x18ec, 0x20000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x186c, 0x0000ff00, 0xff);\n\t\todm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x18a0, 0x0000007f, 0x00);\n\t\todm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x1);\n\t}\n\n#if 1\n\t/*path s1*/\n\tif (channel >= 1 && channel <= 14) {\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1d04, 0x000ff000, 0x20);\n\t\todm_set_bb_reg(dm, R_0x41ec, 0x00c00000, 0x3);\n\t\todm_set_bb_reg(dm, R_0x4134, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41e0, 0x00000001, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41a8, 0x00000003, 0x2);\n\t\todm_set_bb_reg(dm, R_0x1eec, 0x00001fff, 0x0000);\n\t\todm_set_bb_reg(dm, R_0x1eec, 0x003fe000, 0x000);\n\t\todm_set_bb_reg(dm, R_0x1eec, 0x3fc00000, 0x00);\n\t\todm_set_bb_reg(dm, R_0x1ef0, 0x000001ff, 0x000);\n\t\todm_set_bb_reg(dm, R_0x41ec, 0x20000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x1ef0, 0x01fe0000, 0xff);\n\t\todm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x41a0, 0x0000007f, 0x00);\n\t\todm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x1);\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1d04, 0x000ff000, 0x20);\n\t\todm_set_bb_reg(dm, R_0x41ec, 0x00c00000, 0x3);\n\t\todm_set_bb_reg(dm, R_0x4134, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41e0, 0x00000001, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41a8, 0x00000003, 0x2);\n\t\todm_set_bb_reg(dm, R_0x1eec, 0x00001fff, 0x0000);\n\t\todm_set_bb_reg(dm, R_0x1eec, 0x003fe000, 0x000);\n\t\todm_set_bb_reg(dm, R_0x1eec, 0x3fc00000, 0x00);\n\t\todm_set_bb_reg(dm, R_0x1ef0, 0x000001ff, 0x000);\n\t\todm_set_bb_reg(dm, R_0x41ec, 0x20000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1ef0, 0x01fe0000, 0xff);\n\t\todm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x41a0, 0x0000007f, 0x00);\n\t\todm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x1);\n\t}\n#endif\n\thalrf_enable_tssi_8822c(dm);\n#endif\n\n}\n\n\nu32 halrf_set_tssi_value_8822c(\n\tvoid *dm_void,\n\tu32 tssi_value)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\tu16 tssi_codeword_tmp[TSSI_CODE_NUM] = {0};\n\ts16 txagc_codeword_tmp[TSSI_CODE_NUM] = {0};\n\tu8 tx_rate = phydm_get_tx_rate(dm);\n\tu8 tssi_rate = _halrf_driver_rate_to_tssi_rate_8822c(dm, tx_rate);\n\tu8 rate = phydm_get_tx_rate(dm);\n\ts8 efuse, kfree;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"Call:%s tx_rate=0x%X tssi_rate=%d\\n\"\n\t       , __func__, tx_rate, tssi_rate);\n\n\todm_move_memory(dm, tssi_codeword_tmp, tssi->tssi_codeword,\n\t\t\tsizeof(tssi_codeword_tmp));\n\n\ttssi_codeword_tmp[tssi_rate] = (u8)tssi_value;\n\n\t_halrf_calculate_txagc_codeword_8822c(dm, tssi_codeword_tmp, txagc_codeword_tmp);\n\t_halrf_set_txagc_codeword_8822c(dm, txagc_codeword_tmp);\n\t_halrf_set_tssi_codeword_8822c(dm, tssi_codeword_tmp);\n\n\tkfree = _halrf_get_kfree_tssi_offset_8822c(dm);\n\n\ttssi_value = tssi_value - tssi->tssi_codeword[tssi_rate] - kfree;\n\n\t/*path s0*/\n\t/*2G CCK*/\n\todm_set_bb_reg(dm, R_0x18e8, 0x01fe0000, 0);\n\n\t/*2G & 5G OFDM*/\n\todm_set_bb_reg(dm, R_0x18a8, 0xff000000, 0);\n\n\t/*path s1*/\n\t/*2G CCK*/\n\todm_set_bb_reg(dm, R_0x1ef0, 0x0001fe00, 0);\n\n\t/*2G & 5G OFDM*/\n\todm_set_bb_reg(dm, R_0x1eec, 0x3fc00000, 0);\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s Set DE = 0\\n\", __func__);\n\n\treturn tssi_value;\n#endif\n\treturn 0;\n}\n\n\nvoid halrf_set_tssi_poewr_8822c(\n\tvoid *dm_void,\n\ts8 power)\n{\n\ts32 tssi_codeword = 0;\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\tu16 tssi_codeword_tmp[TSSI_CODE_NUM] = {0};\n\ts16 txagc_codeword_tmp[TSSI_CODE_NUM] = {0};\n\tu8 tx_rate = phydm_get_tx_rate(dm);\n\tu8 tssi_rate = _halrf_driver_rate_to_tssi_rate_8822c(dm, tx_rate);\n\tu8 rate = phydm_get_tx_rate(dm), i;\n\tu8 channel = *dm->channel, bw = *dm->band_width;\n\ts8 efuse, kfree;\n\ts32 index_tmp_a = 0, index_tmp_b = 0;\n\tu8 indexa , indexb;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"Call:%s tx_rate=0x%X tssi_rate=%d channel=%d\\n\"\n\t       , __func__, tx_rate, tssi_rate, channel);\n\n\tif (channel > 14) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"Not in 2G channel=%d\\n\", channel);\n\t\treturn;\n\t}\n\n\tif ((power >= -13 && power <= 13) || power == 0x7f)\n\t{\n#if 0\n\t\tpower = power * TSSI_SLOPE_2G;\n\n\t\todm_move_memory(dm, tssi_codeword_tmp, tssi->tssi_codeword,\n\t\t\t\tsizeof(tssi_codeword_tmp));\n\n\t\tif (power != 0x7f) {\n\t\t\tfor (i = 0; i < TSSI_CODE_NUM; i++) {\n\t\t\t\ttssi_codeword_tmp[i] = tssi_codeword_tmp[i] + power;\n\n\t\t\t\tif (tssi_codeword_tmp[i] > 255)\n\t\t\t\t\ttssi_codeword_tmp[i] = 255;\n\t\t\t\telse if ((s16)tssi_codeword_tmp[i] < 0)\n\t\t\t\t\ttssi_codeword_tmp[i] = 0;\n\t\t\t}\n\t\t}\n\n\t\t_halrf_calculate_txagc_codeword_8822c(dm, tssi_codeword_tmp, txagc_codeword_tmp);\n\t\t_halrf_set_txagc_codeword_8822c(dm, txagc_codeword_tmp);\n\t\t/*_halrf_set_tssi_codeword_8822c(dm, tssi_codeword_tmp);*/\n#endif\n#if 0\n\t\tif (power != 0x7f) {\n\t\t\tfor (i = 0; i < TSSI_CODE_NUM; i++) {\n\t\t\t\ttxagc_codeword_tmp[i] = power * 4;\n\n\t\t\t\tif (txagc_codeword_tmp[i] > 63)\n\t\t\t\t\ttssi_codeword_tmp[i] = 63;\n\t\t\t\telse if (txagc_codeword_tmp[i] < -64)\n\t\t\t\t\ttssi_codeword_tmp[i] = -64;\n\t\t\t}\n\t\t}\n\n\t\t_halrf_set_txagc_codeword_8822c(dm, txagc_codeword_tmp);\n\n#endif\n\t\t\t  \n\t\tif (power != 0x7f) {\n\t\t\tindexa = odm_get_tx_power_index(dm, RF_PATH_A, rate, bw, channel);\n\t\t\tindexb = odm_get_tx_power_index(dm, RF_PATH_B, rate, bw, channel);\n\t\t\t\n\t\t\tindex_tmp_a = indexa + power * 4;\n\n\t\t\tif (index_tmp_a > 127)\n\t\t\t\tindex_tmp_a = 127;\n\t\t\telse if (index_tmp_a < 0)\n\t\t\t\tindex_tmp_a = 0;\n\n\t\t\ttssi->index[RF_PATH_A][channel - 1] = (u32)index_tmp_a;\n\n\t\t\tindex_tmp_b = indexb + power * 4;\n\n\t\t\tif (index_tmp_b > 127)\n\t\t\t\tindex_tmp_b = 127;\n\t\t\telse if (index_tmp_b < 0)\n\t\t\t\tindex_tmp_b = 0;\n\n\t\t\ttssi->index[RF_PATH_B][channel - 1] = (u32)index_tmp_b;\n\n\t\t\todm_set_bb_reg(dm, R_0x18e8, 0x0001fc00, (index_tmp_a & 0x7f));\n\t\t\todm_set_bb_reg(dm, R_0x41e8, 0x0001fc00, (index_tmp_b & 0x7f));\n\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"===>%s Set coex Tx index PathA:%d PathB:%d\\n\",\n\t\t\t       __func__,\n\t\t\t       odm_get_bb_reg(dm, R_0x18e8, 0x0001fc00),\n\t\t\t       odm_get_bb_reg(dm, R_0x41e8, 0x0001fc00));\n\t\t} else {\n\t\t\tindexa = odm_get_tx_power_index(dm, RF_PATH_A, rate, bw, channel);\n\t\t\tindexb = odm_get_tx_power_index(dm, RF_PATH_B, rate, bw, channel);\n\n\t\t\todm_set_bb_reg(dm, R_0x18e8, 0x0001fc00, (indexa & 0x7f));\n\t\t\todm_set_bb_reg(dm, R_0x41e8, 0x0001fc00, (indexb & 0x7f));\n\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t\t       \"===>%s Set coex Tx default index PathA:%d PathB:%d\\n\",\n\t\t\t       __func__,\n\t\t\t       odm_get_bb_reg(dm, R_0x18e8, 0x0001fc00),\n\t\t\t       odm_get_bb_reg(dm, R_0x41e8, 0x0001fc00));\n\n\t\t\tfor (i = 1; i <= 14; i++) {\n\t\t\t\ttssi->index[RF_PATH_A][i - 1] = 0;\n\t\t\t\ttssi->index[RF_PATH_B][i - 1] = 0;\n\t\t\t}\n\t\t}\n\n\t}\n#endif\n\n}\n\nvoid halrf_get_efuse_thermal_pwrtype_8822c(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\n\tu32 thermal_tmp;\n\n\ttssi->thermal[RF_PATH_A] = 0xff;\n\ttssi->thermal[RF_PATH_B] = 0xff;\n\n\t/*path s0*/\n\todm_efuse_logical_map_read(dm, 1, 0xd0, &thermal_tmp);\n\ttssi->thermal[RF_PATH_A] = (u8)thermal_tmp;\n\n\t/*path s1*/\n\todm_efuse_logical_map_read(dm, 1, 0xd1, &thermal_tmp);\n\ttssi->thermal[RF_PATH_B] = (u8)thermal_tmp;\n\n\t/*power tracking type*/\n\todm_efuse_logical_map_read(dm, 1, 0xc8, &thermal_tmp);\n\trf->power_track_type = (u8)(thermal_tmp & 0xff);\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"===>%s thermal pahtA=0x%x pahtB=0x%x power_track_type=0x%x\\n\",\n\t       __func__, tssi->thermal[RF_PATH_A],  tssi->thermal[RF_PATH_B],\n\t       rf->power_track_type);\n\t\n}\n\nu32 halrf_query_tssi_value_8822c(\n\tvoid *dm_void)\n{\n\ts32 tssi_codeword = 0;\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\tu8 tssi_rate;\n\tu8 rate = phydm_get_tx_rate(dm);\n\ts8 efuse, kfree;\n\n\ttssi_rate = _halrf_driver_rate_to_tssi_rate_8822c(dm, phydm_get_tx_rate(dm));\n\ttssi_codeword = tssi->tssi_codeword[tssi_rate];\n\n\tif (rate == MGN_1M || rate == MGN_2M || rate == MGN_5_5M || rate == MGN_11M) {\n\t\tefuse = _halrf_get_efuse_tssi_offset_8822c(dm, 3);\n\t\tkfree = _halrf_get_kfree_tssi_offset_8822c(dm);\n\t} else {\n\t\tefuse = _halrf_get_efuse_tssi_offset_8822c(dm, 19);\n\t\tkfree = _halrf_get_kfree_tssi_offset_8822c(dm);\n\t}\n\n\ttssi_codeword = tssi_codeword + efuse + kfree;\n\n\tif (tssi_codeword <= 0)\n\t\ttssi_codeword = 0;\n\telse if (tssi_codeword >= 255)\n\t\ttssi_codeword = 255;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"===>%s tx_rate=0x%X tssi_codeword(0x%x) = tssi_codeword(%d) + efuse(%d) + kfree(%d)\\n\",\n\t       __func__, phydm_get_tx_rate(dm), tssi_codeword,\n\t       tssi->tssi_codeword[tssi_rate], efuse, kfree);\n#endif\n\n\treturn (u32)tssi_codeword;\n}\n\nvoid halrf_tssi_cck_8822c(\n\tvoid *dm_void)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\tu8 rate = phydm_get_tx_rate(dm);\n\tu32 alogk, regc, regde, regf;\n\ts32 sregde, sregf;\n\n\tif (!(rate == MGN_1M || rate == MGN_2M || rate == MGN_5_5M || rate == MGN_11M))\n\t\treturn;\n\n\t/*path s0*/\n\todm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xffff00bc);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x701f0044);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x702f0044);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x703f0044);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x704f0044);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705b8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x706f0044);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x707b8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x708b8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x709b8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ab8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70bb8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70cb8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70db8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70eb8041);\n\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70fb8041);\n\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1c24, 0x0001fe00, 0x20);\n\todm_set_bb_reg(dm, R_0x18ec, 0x00c00000, 0x2);\n\todm_set_bb_reg(dm, R_0x1834, 0x80000000, 0x1);\n\todm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);\n\todm_set_bb_reg(dm, R_0x18e0, 0x00000001, 0x0);\n\todm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);\n\todm_set_bb_reg(dm, R_0x18a8, 0x00000003, 0x2);\n\todm_set_bb_reg(dm, R_0x18a8, 0x00007ffc, 0x1266);\n\todm_set_bb_reg(dm, R_0x18a8, 0x00ff8000, 0x000);\n\todm_set_bb_reg(dm, R_0x18a8, 0xff000000, 0x00);\n\todm_set_bb_reg(dm, R_0x18e8, 0x01fe0000, 0x00);\n\todm_set_bb_reg(dm, R_0x18e8, 0x000003fe, 0x110);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x7f, 0x00002, 0x1);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x65, 0x03000, 0x3);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x0000c, 0x3);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x000c0, 0x3);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x6e, 0x001e0, 0x0);\n\todm_set_bb_reg(dm, R_0x1e7c, 0x00800000, 0x0);\n\todm_set_bb_reg(dm, R_0x180c, 0x08000000, 0x1);\n\todm_set_bb_reg(dm, R_0x180c, 0x40000000, 0x1);\n\todm_set_bb_reg(dm, R_0x1800, 0x80000000, 0x1);\n\todm_set_bb_reg(dm, R_0x1804, 0x80000000, 0x1);\n\todm_set_bb_reg(dm, R_0x1800, 0x40000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1804, 0x40000000, 0x0);\n\todm_set_bb_reg(dm, R_0x18ec, 0x20000000, 0x0);\n\todm_set_bb_reg(dm, R_0x18ec, 0x40000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1860, 0x00000800, 0x0);\n\todm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x1);\n\todm_set_bb_reg(dm, R_0x186c, 0x0000ff00, 0xff);\n\todm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);\n\todm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);\n\todm_set_bb_reg(dm, R_0x18a0, 0x0000007f, 0x00);\n\todm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);\n\n\t/*read AlogK u9bit*/\n\todm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0x936);\n\todm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);\n\todm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x1);\n\talogk = odm_get_bb_reg(dm, R_0x2dbc, 0xff800000);\n\n\t/*read c u8bit*/\n\todm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0x933);\n\tregc = odm_get_bb_reg(dm, R_0x2dbc, 0x003fc000);\n\t\n\t/*read de s8bit*/\n\todm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0x933);\n\tregde = odm_get_bb_reg(dm, R_0x2dbc, 0x3fc00000);\n\n\tif (regde & 0x80)\n\t\tsregde = regde - 256;\n\telse\n\t\tsregde = regde;\n\t\n\t/*read f s7bit*/\n\todm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0x934);\n\tregf = odm_get_bb_reg(dm, R_0x2dbc, 0x0000007f);\n\t\n\tif (regf & 0x40)\n\t\tsregf = regf - 128;\n\telse\n\t\tsregf = regf;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"tssi->cck_offset_patha(%d)\\n\",\n\t\ttssi->cck_offset_patha);\n\n\ttssi->cck_offset_patha = tssi->cck_offset_patha + ((s32)(regc - sregde - alogk - sregf) / 2);\n\n\tif (tssi->cck_offset_patha >= 63)\n\t\ttssi->cck_offset_patha = 63;\n\telse if (tssi->cck_offset_patha <= -64)\n\t\ttssi->cck_offset_patha = -64;\n\t\n\todm_set_bb_reg(dm, R_0x18a0, 0x0000007f, (tssi->cck_offset_patha & 0x7f));\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"tssi->cck_offset_patha(%d) = (regc(%d) - sregde(%d) - alogk(%d) - sregf(%d)) / 2\\n\",\n\t\ttssi->cck_offset_patha, regc, sregde, alogk, sregf);\n\n\n\t/*path s1*/\n\todm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xffff00bc);\n\todm_set_bb_reg(dm, R_0x1860, 0x00007000, 0x4);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700b8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x701f0044);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x702f0044);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x703f0044);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x704f0044);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x705b8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x706f0044);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x707b8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x708b8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x709b8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70ab8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70bb8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70cb8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70db8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70eb8041);\n\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70fb8041);\n\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1d04, 0x000ff000, 0x20);\n\todm_set_bb_reg(dm, R_0x41ec, 0x00c00000, 0x2);\n\todm_set_bb_reg(dm, R_0x4134, 0x80000000, 0x1);\n\todm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);\n\todm_set_bb_reg(dm, R_0x41e0, 0x00000001, 0x0);\n\todm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);\n\todm_set_bb_reg(dm, R_0x41a8, 0x00000003, 0x2);\n\todm_set_bb_reg(dm, R_0x1eec, 0x00001fff, 0x1266);\n\todm_set_bb_reg(dm, R_0x1eec, 0x003fe000, 0x000);\n\todm_set_bb_reg(dm, R_0x1eec, 0x3fc00000, 0x00);\n\todm_set_bb_reg(dm, R_0x1ef0, 0x0001fe00, 0x00);\n\todm_set_bb_reg(dm, R_0x1ef0, 0x000001ff, 0x110);\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0x7f, 0x00002, 0x1);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x65, 0x03000, 0x3);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x0000c, 0x3);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x67, 0x000c0, 0x3);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x6e, 0x001e0, 0x0);\n\todm_set_bb_reg(dm, R_0x1e7c, 0x00800000, 0x0);\n\todm_set_bb_reg(dm, R_0x410c, 0x08000000, 0x1);\n\todm_set_bb_reg(dm, R_0x410c, 0x40000000, 0x1);\n\todm_set_bb_reg(dm, R_0x4100, 0x80000000, 0x1);\n\todm_set_bb_reg(dm, R_0x4104, 0x80000000, 0x1);\n\todm_set_bb_reg(dm, R_0x4100, 0x40000000, 0x0);\n\todm_set_bb_reg(dm, R_0x4104, 0x40000000, 0x0);\n\todm_set_bb_reg(dm, R_0x41ec, 0x20000000, 0x0);\n\todm_set_bb_reg(dm, R_0x41ec, 0x40000000, 0x0);\n\todm_set_bb_reg(dm, R_0x4160, 0x00000800, 0x0);\n\todm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x1);\n\todm_set_bb_reg(dm, R_0x1ef0, 0x01fe0000, 0xff);\n\todm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);\n\todm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);\n\todm_set_bb_reg(dm, R_0x41a0, 0x0000007f, 0x00);\n\todm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);\n\n\t/*read AlogK u9bit*/\n\todm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0xb36);\n\todm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);\n\todm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x1);\n\talogk = odm_get_bb_reg(dm, R_0x2dbc, 0xff800000);\n\n\t/*read c u8bit*/\n\todm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0xb33);\n\tregc = odm_get_bb_reg(dm, R_0x2dbc, 0x003fc000);\n\t\n\t/*read de s8bit*/\n\todm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0xb33);\n\tregde = odm_get_bb_reg(dm, R_0x2dbc, 0x3fc00000);\n\n\tif (regde & 0x80)\n\t\tsregde = regde - 256;\n\telse\n\t\tsregde = regde;\n\t\n\t/*read f s7bit*/\n\todm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0xb34);\n\tregf = odm_get_bb_reg(dm, R_0x2dbc, 0x0000007f);\n\t\n\tif (regf & 0x40)\n\t\tsregf = regf - 128;\n\telse\n\t\tsregf = regf;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"tssi->cck_offset_pathb(%d)\\n\",\n\t\ttssi->cck_offset_pathb);\n\n\ttssi->cck_offset_pathb = tssi->cck_offset_pathb + ((s32)(regc - sregde - alogk - sregf) / 2);\n\n\tif (tssi->cck_offset_pathb >= 63)\n\t\ttssi->cck_offset_pathb = 63;\n\telse if (tssi->cck_offset_pathb <= -64)\n\t\ttssi->cck_offset_pathb = -64;\n\t\n\todm_set_bb_reg(dm, R_0x41a0, 0x0000007f, (tssi->cck_offset_pathb & 0x7f));\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"tssi->cck_offset_pathb(%d) = (regc(%d) - sregde(%d) - alogk(%d) - sregf(%d)) / 2\\n\",\n\t\ttssi->cck_offset_pathb, regc, sregde, alogk, sregf);\n#endif\n\n}\n\nvoid halrf_thermal_cck_8822c(\n\tvoid *dm_void)\n{\n#if 0\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n\tstruct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;\n\tu8 rate = phydm_get_tx_rate(dm);\n\tu32 alogk, regc, regde, regf;\n\ts32 sregde, sregf;\n\n\tif ((rf->rf_supportability & HAL_RF_TX_PWR_TRACK) == 1) {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s\\n\", __func__);\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"rf_supportability HAL_RF_TX_PWR_TRACK on\\n\");\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"===>%s, return!\\n\", __func__);\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t\t       \"rf_supportability HAL_RF_TX_PWR_TRACK off, return!!\\n\");\n\n\t\t/*halrf_disable_tssi_8822c(dm);*/\n\t\treturn;\n\t}\n\n\tif (!tssi->get_thermal) {\n\t\todm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);\n\t\todm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);\n\t\todm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);\n\t\t\n\t\todm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);\n\t\todm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);\n\t\todm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);\n\n\t\ttssi->get_thermal = 1;\n\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"Trigger current thmermal\\n\");\n\t} else {\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"s0 current thmermal=0x%x(%d)\\n\",\n\t\t       odm_get_rf_reg(dm, RF_PATH_A, R_0x42, 0xfc00),\n\t\t       odm_get_rf_reg(dm, RF_PATH_A, R_0x42, 0xfc00));\n\t\t\n\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"s1 current thmermal=0x%x(%d)\\n\",\n\t\t       odm_get_rf_reg(dm, RF_PATH_B, R_0x42, 0xfc00),\n\t\t       odm_get_rf_reg(dm, RF_PATH_B, R_0x42, 0xfc00));\n\n\t\ttssi->get_thermal = 0;\n\t}\n\n\tif ((DBG_RF_TX_PWR_TRACK & dm->rf_table.rf_dbg_comp) == 1) {\n\t\t/*set debug port to 0x944*/\n\t\tif (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x944)) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"s0 Power Tracking offset %d\\n\",\n\t\t\t       (phydm_get_bb_dbg_port_val(dm) & 0x7f00) >> 8);\n\t\t\tphydm_release_bb_dbg_port(dm);\n\t\t}\n\n\t\t/*set debug port to 0xb44*/\n\t\tif (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0xb44)) {\n\t\t\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"s1 Power Tracking offset %d\\n\",\n\t\t\t       (phydm_get_bb_dbg_port_val(dm) & 0x7f00) >> 8);\n\t\t\tphydm_release_bb_dbg_port(dm);\n\t\t}\n\t}\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK, \"===>%s \\n\", __func__);\n\n\tif (!(rate == MGN_1M || rate == MGN_2M || rate == MGN_5_5M || rate == MGN_11M))\n\t\treturn;\n\n\t/*path s0*/\n\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1c24, 0x0001fe00, 0x20);\n\todm_set_bb_reg(dm, R_0x18ec, 0x00c00000, 0x3);\n\todm_set_bb_reg(dm, R_0x1834, 0x80000000, 0x1);\n\todm_set_bb_reg(dm, R_0x18a4, 0x10000000, 0x0);\n\todm_set_bb_reg(dm, R_0x18e0, 0x00000001, 0x0);\n\todm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);\n\todm_set_bb_reg(dm, R_0x18a8, 0x00000003, 0x2);\n\todm_set_bb_reg(dm, R_0x18a8, 0x00007ffc, 0x0000);\n\todm_set_bb_reg(dm, R_0x18a8, 0x00ff8000, 0x000);\n\todm_set_bb_reg(dm, R_0x18a8, 0xff000000, 0x00);\n\todm_set_bb_reg(dm, R_0x18e8, 0x01fe0000, 0x00);\n\todm_set_bb_reg(dm, R_0x18e8, 0x000003fe, 0x000);\n\todm_set_bb_reg(dm, R_0x18ec, 0x20000000, 0x1);\n\todm_set_bb_reg(dm, R_0x186c, 0x0000ff00, 0xff);\n\todm_set_bb_reg(dm, R_0x18a4, 0xe0000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);\n\todm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);\n\todm_set_bb_reg(dm, R_0x18a0, 0x0000007f, 0x00);\n\todm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);\n\t\n\t/*read f s7bit*/\n\todm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0x934);\n\tregf = odm_get_bb_reg(dm, R_0x2dbc, 0x0000007f);\n\t\n\tif (regf & 0x40)\n\t\tsregf = regf - 128;\n\telse\n\t\tsregf = regf;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"tssi->cck_offset_patha(%d)\\n\",\n\t\ttssi->cck_offset_patha);\n\n\t//tssi->cck_offset_patha = tssi->cck_offset_patha + sregf;\n\ttssi->cck_offset_patha = sregf;\n\n\tif (tssi->cck_offset_patha >= 63)\n\t\ttssi->cck_offset_patha = 63;\n\telse if (tssi->cck_offset_patha <= -64)\n\t\ttssi->cck_offset_patha = -64;\n\t\n\todm_set_bb_reg(dm, R_0x18a0, 0x0000007f, (tssi->cck_offset_patha & 0x7f));\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"tssi->cck_offset_patha(%d)\\n\", tssi->cck_offset_patha);\n\n\n\t/*path s1*/\n\todm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1c64, 0x20000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1d04, 0x000ff000, 0x20);\n\todm_set_bb_reg(dm, R_0x41ec, 0x00c00000, 0x3);\n\todm_set_bb_reg(dm, R_0x4134, 0x80000000, 0x1);\n\todm_set_bb_reg(dm, R_0x41a4, 0x10000000, 0x0);\n\todm_set_bb_reg(dm, R_0x41e0, 0x00000001, 0x0);\n\todm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);\n\todm_set_bb_reg(dm, R_0x41a8, 0x00000003, 0x2);\n\todm_set_bb_reg(dm, R_0x1eec, 0x00001fff, 0x0000);\n\todm_set_bb_reg(dm, R_0x1eec, 0x003fe000, 0x000);\n\todm_set_bb_reg(dm, R_0x1eec, 0x3fc00000, 0x00);\n\todm_set_bb_reg(dm, R_0x1ef0, 0x0001fe00, 0x00);\n\todm_set_bb_reg(dm, R_0x1ef0, 0x000001ff, 0x000);\n\todm_set_bb_reg(dm, R_0x41ec, 0x20000000, 0x1);\n\todm_set_bb_reg(dm, R_0x1ef0, 0x01fe0000, 0xff);\n\todm_set_bb_reg(dm, R_0x41a4, 0xe0000000, 0x0);\n\todm_set_bb_reg(dm, R_0x1c64, 0x1fffff00, 0x000000);\n\todm_set_bb_reg(dm, R_0x1e7c, 0x80000000, 0x1);\n\todm_set_bb_reg(dm, R_0x41a0, 0x0000007f, 0x00);\n\todm_set_bb_reg(dm, R_0x1d04, 0x07f00000, 0x00);\n\t\n\t/*read f s7bit*/\n\todm_set_bb_reg(dm, R_0x1c3c, 0x000fff00, 0xb34);\n\tregf = odm_get_bb_reg(dm, R_0x2dbc, 0x0000007f);\n\t\n\tif (regf & 0x40)\n\t\tsregf = regf - 128;\n\telse\n\t\tsregf = regf;\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"tssi->cck_offset_pathb(%d)\\n\",\n\t\ttssi->cck_offset_pathb);\n\n\t//tssi->cck_offset_pathb = tssi->cck_offset_pathb + sregf;\n\ttssi->cck_offset_pathb = sregf;\n\n\tif (tssi->cck_offset_pathb >= 63)\n\t\ttssi->cck_offset_pathb = 63;\n\telse if (tssi->cck_offset_pathb <= -64)\n\t\ttssi->cck_offset_pathb = -64;\n\t\n\todm_set_bb_reg(dm, R_0x41a0, 0x0000007f, (tssi->cck_offset_pathb & 0x7f));\n\n\tRF_DBG(dm, DBG_RF_TX_PWR_TRACK,\n\t       \"tssi->cck_offset_pathb(%d)\\n\", tssi->cck_offset_pathb);\n#endif\n\n}\n\n#endif\n"
  },
  {
    "path": "hal/phydm/halrf/rtl8822c/halrf_tssi_8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALRF_TSSI_8822C_H__\n#define __HALRF_TSSI_8822C_H__\n\n#if (RTL8822C_SUPPORT == 1)\n/*--------------------------Define Parameters-------------------------------*/\n#if 0\n/*efuse defind*/\n#define CCK_PATHA_G1 0x10\n#define CCK_PATHA_G2 0x11\n#define CCK_PATHA_G3 0x12\n#define CCK_PATHA_G4 0x13\n#define CCK_PATHA_G5 0x14\n#define CCK_PATHA_G6 0x15\n#define OFDM_2G_OFDM_PATHA_G7 0x16\n#define OFDM_2G_OFDM_PATHA_G8 0x17\n#define OFDM_2G_OFDM_PATHA_G9 0x18\n#define OFDM_2G_OFDM_PATHA_G10 0x19\n#define OFDM_2G_OFDM_PATHA_G11 0x1a\n#define OFDM_5G_OFDM_PATHA_G12 0x22\n#define OFDM_5G_OFDM_PATHA_G13 0x23\n#define OFDM_5G_OFDM_PATHA_G14 0x24\n#define OFDM_5G_OFDM_PATHA_G15 0x25\n#define OFDM_5G_OFDM_PATHA_G16 0x26\n#define OFDM_5G_OFDM_PATHA_G17 0x27\n#define OFDM_5G_OFDM_PATHA_G18 0x28\n#define OFDM_5G_OFDM_PATHA_G19 0x29\n#define OFDM_5G_OFDM_PATHA_G20 0x2a\n#define OFDM_5G_OFDM_PATHA_G21 0x2b\n#define OFDM_5G_OFDM_PATHA_G22 0x2c\n#define OFDM_5G_OFDM_PATHA_G23 0x2d\n#define OFDM_5G_OFDM_PATHA_G24 0x2e\n#define OFDM_5G_OFDM_PATHA_G25 0x2f\n\n\n#define CCK_PATHB_G1 0x3a\n#define CCK_PATHB_G2 0x3b\n#define CCK_PATHB_G3 0x3c\n#define CCK_PATHB_G4 0x3d\n#define CCK_PATHB_G5 0x3e\n#define CCK_PATHB_G6 0x3f\n#define OFDM_2G_OFDM_PATHB_G7 0x40\n#define OFDM_2G_OFDM_PATHB_G8 0x41\n#define OFDM_2G_OFDM_PATHB_G9 0x42\n#define OFDM_2G_OFDM_PATHB_G10 0x43\n#define OFDM_2G_OFDM_PATHB_G11 0x44\n#define OFDM_5G_OFDM_PATHB_G12 0x4c\n#define OFDM_5G_OFDM_PATHB_G13 0x4d\n#define OFDM_5G_OFDM_PATHB_G14 0x4e\n#define OFDM_5G_OFDM_PATHB_G15 0x4f\n#define OFDM_5G_OFDM_PATHB_G16 0x50\n#define OFDM_5G_OFDM_PATHB_G17 0x51\n#define OFDM_5G_OFDM_PATHB_G18 0x52\n#define OFDM_5G_OFDM_PATHB_G19 0x53\n#define OFDM_5G_OFDM_PATHB_G20 0x54\n#define OFDM_5G_OFDM_PATHB_G21 0x55\n#define OFDM_5G_OFDM_PATHB_G22 0x56\n#define OFDM_5G_OFDM_PATHB_G23 0x57\n#define OFDM_5G_OFDM_PATHB_G24 0x58\n#define OFDM_5G_OFDM_PATHB_G25 0x59\n#endif\n\n/*---------------------------End Define Parameters----------------------------*/\n\n\nvoid halrf_tssi_get_efuse_8822c(\n\tvoid *dm_void);\n\nvoid halrf_tssi_get_kfree_efuse_8822c(\n\tvoid *dm_void);\n\nvoid halrf_enable_tssi_8822c(\n\tvoid *dm_void);\n\nvoid halrf_disable_tssi_8822c(\n\tvoid *dm_void);\n\nvoid halrf_do_tssi_8822c(\n\tvoid *dm_void);\n\nvoid halrf_do_thermal_8822c(\n\tvoid *dm_void);\n\nu32 halrf_set_tssi_value_8822c(\n\tvoid *dm_void,\n\tu32 tssi_value);\n\nvoid halrf_set_tssi_poewr_8822c(\n\tvoid *dm_void,\n\ts8 power);\n\nvoid halrf_get_efuse_thermal_pwrtype_8822c(\n\tvoid *dm_void);\n\nu32 halrf_query_tssi_value_8822c(\n\tvoid *dm_void);\n\nvoid halrf_tssi_cck_8822c(\n\tvoid *dm_void);\n\nvoid halrf_thermal_cck_8822c(\n\tvoid *dm_void);\n\n#endif /* RTL8822C_SUPPORT */\n#endif /*#ifndef __HALRF_TSSI_8822C_H__*/\n"
  },
  {
    "path": "hal/phydm/halrf/rtl8822c/version_rtl8822c_rf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n/*RTL8822C RF Parameters*/\n#define\tRF_RELEASE_VERSION_8822C\t23\n"
  },
  {
    "path": "hal/phydm/mp_precomp.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n"
  },
  {
    "path": "hal/phydm/phydm.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n ************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\nconst u16 phy_rate_table[] = {\n\t/*@20M*/\n\t1, 2, 5, 11,\n\t6, 9, 12, 18, 24, 36, 48, 54,\n\t6, 13, 19, 26, 39, 52, 58, 65, /*@MCS0~7*/\n\t13, 26, 39, 52, 78, 104, 117, 130, /*@MCS8~15*/\n\t19, 39, 58, 78, 117, 156, 175, 195, /*@MCS16~23*/\n\t26, 52, 78, 104, 156, 208, 234, 260, /*@MCS24~31*/\n\t6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1ss MCS0~9*/\n\t13, 26, 39, 52, 78, 104, 117, 130, 156, 180, /*@2ss MCS0~9*/\n\t19, 39, 58, 78, 117, 156, 175, 195, 234, 260, /*@3ss MCS0~9*/\n\t26, 52, 78, 104, 156, 208, 234, 260, 312, 360 /*@4ss MCS0~9*/\n};\n\nvoid phydm_traffic_load_decision(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 shift = 0;\n\n\t/*@---TP & Trafic-load calculation---*/\n\n\tif (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)\n\t\tdm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;\n\n\tif (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)\n\t\tdm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;\n\n\tdm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;\n\tdm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;\n\tdm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;\n\tdm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;\n\n\t/*@AP:  <<3(8bit), >>20(10^6,M), >>0(1sec)*/\n\tshift = 17 + (PHYDM_WATCH_DOG_PERIOD - 1);\n\t/*@WIN&CE:  <<3(8bit), >>20(10^6,M), >>1(2sec)*/\n\n\tdm->tx_tp = (dm->tx_tp >> 1) + (u32)((dm->cur_tx_ok_cnt >> shift) >> 1);\n\tdm->rx_tp = (dm->rx_tp >> 1) + (u32)((dm->cur_rx_ok_cnt >> shift) >> 1);\n\n\tdm->total_tp = dm->tx_tp + dm->rx_tp;\n\n\t/*@[Calculate TX/RX state]*/\n\tif (dm->tx_tp > (dm->rx_tp << 1))\n\t\tdm->txrx_state_all = TX_STATE;\n\telse if (dm->rx_tp > (dm->tx_tp << 1))\n\t\tdm->txrx_state_all = RX_STATE;\n\telse\n\t\tdm->txrx_state_all = BI_DIRECTION_STATE;\n\n\t/*@[Traffic load decision]*/\n\tdm->pre_traffic_load = dm->traffic_load;\n\n\tif (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) {\n\t\t/* @( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/\n\t\tdm->traffic_load = TRAFFIC_HIGH;\n\t} else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) {\n\t\t/*@( 0.5M * 8bit ) / 2sec =  2M bits /sec )*/\n\t\tdm->traffic_load = TRAFFIC_MID;\n\t} else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) {\n\t\t/*@( 0.1M * 8bit ) / 2sec =  0.4M bits /sec )*/\n\t\tdm->traffic_load = TRAFFIC_LOW;\n\t} else if (dm->cur_tx_ok_cnt > 25000 || dm->cur_rx_ok_cnt > 25000) {\n\t\t/*@( 0.025M * 8bit ) / 2sec =  0.1M bits /sec )*/\n\t\tdm->traffic_load = TRAFFIC_ULTRA_LOW;\n\t} else {\n\t\tdm->traffic_load = TRAFFIC_NO_TP;\n\t}\n\n\t/*@[Calculate consecutive idlel time]*/\n\tif (dm->traffic_load == 0)\n\t\tdm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD;\n\telse\n\t\tdm->consecutive_idlel_time = 0;\n\n\t#if 0\n\tPHYDM_DBG(dm, DBG_COMMON_FLOW,\n\t\t  \"cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\\n\",\n\t\t  dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt,\n\t\t  dm->last_rx_ok_cnt);\n\n\tPHYDM_DBG(dm, DBG_COMMON_FLOW, \"tx_tp = %d, rx_tp = %d\\n\", dm->tx_tp,\n\t\t  dm->rx_tp);\n\t#endif\n}\n\nvoid phydm_cck_new_agc_chk(struct dm_struct *dm)\n{\n\tdm->cck_new_agc = 0;\n\n#if (RTL8723D_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT ||\\\n\tRTL8197F_SUPPORT || RTL8710B_SUPPORT || RTL8192F_SUPPORT ||\\\n\tRTL8195B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\\\n\tRTL8721D_SUPPORT)\n\tif (dm->support_ic_type &\n\t    (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8197F |\n\t    ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8195B | ODM_RTL8721D)) {\n\t\t/*@1: new agc  0: old agc*/\n\t\tdm->cck_new_agc = (boolean)odm_get_bb_reg(dm, R_0xa9c, BIT(17));\n\t} else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C)) {\n\t\t/*@1: new agc  0: old agc*/\n\t\tdm->cck_new_agc = (boolean)odm_get_bb_reg(dm, R_0x1a9c,\n\t\t\t\t\t\t\t  BIT(17));\n\t}\n#endif\n}\n\n/*select 3 or 4 bit LNA */\nvoid phydm_cck_lna_bit_num_chk(struct dm_struct *dm)\n{\n\tboolean report_type = 0;\n\t#if (RTL8192E_SUPPORT)\n\tu32 value_824, value_82c;\n\t#endif\n\n\t#if (RTL8192E_SUPPORT)\n\tif (dm->support_ic_type & (ODM_RTL8192E)) {\n\t/* @0x824[9] = 0x82C[9] = 0xA80[7] those registers setting\n\t * should be equal or CCK RSSI report may be incorrect\n\t */\n\t\tvalue_824 = odm_get_bb_reg(dm, R_0x824, BIT(9));\n\t\tvalue_82c = odm_get_bb_reg(dm, R_0x82c, BIT(9));\n\n\t\tif (value_824 != value_82c)\n\t\t\todm_set_bb_reg(dm, R_0x82c, BIT(9), value_824);\n\t\todm_set_bb_reg(dm, R_0xa80, BIT(7), value_824);\n\t\treport_type = (boolean)value_824;\n\t}\n\t#endif\n\n\t#if (RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8710B_SUPPORT)\n\tif (dm->support_ic_type &\n\t    (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {\n\t\treport_type = (boolean)odm_get_bb_reg(dm, R_0x950, BIT(11));\n\n\t\tif (report_type != 1)\n\t\t\tpr_debug(\"[Warning] CCK should be 4bit LNA\\n\");\n\t}\n\t#endif\n\n\t#if (RTL8821C_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8821C) {\n\t\tif (dm->default_rf_set_8821c == SWITCH_TO_BTG)\n\t\t\treport_type = 1;\n\t}\n\t#endif\n\n\tdm->cck_agc_report_type = report_type;\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"cck_agc_report_type=((%d))\\n\",\n\t\t  dm->cck_agc_report_type);\n}\n\nvoid phydm_init_cck_setting(struct dm_struct *dm)\n{\n\tu32 reg_tmp = 0;\n\tu32 mask_tmp = 0;\n\n\tphydm_cck_new_agc_chk(dm);\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\treturn;\n\n\treg_tmp = ODM_REG(CCK_RPT_FORMAT, dm);\n\tmask_tmp = ODM_BIT(CCK_RPT_FORMAT, dm);\n\tdm->is_cck_high_power = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"ext_lna_gain=((%d))\\n\", dm->ext_lna_gain);\n\n\tphydm_config_cck_rx_antenna_init(dm);\n\n\tif (dm->support_ic_type & ODM_RTL8192F)\n\t\tphydm_config_cck_rx_path(dm, BB_PATH_AB);\n\telse if (dm->valid_path_set == BB_PATH_A)\n\t\tphydm_config_cck_rx_path(dm, BB_PATH_A);\n\telse if (dm->valid_path_set == BB_PATH_B)\n\t\tphydm_config_cck_rx_path(dm, BB_PATH_B);\n\n\tphydm_cck_lna_bit_num_chk(dm);\n\tphydm_get_cck_rssi_table_from_reg(dm);\n}\n\nvoid phydm_init_hw_info_by_rfe(struct dm_struct *dm)\n{\n#if (RTL8822B_SUPPORT)\n\t/*@if (dm->support_ic_type & ODM_RTL8822B)*/\n\t\t/*@phydm_init_hw_info_by_rfe_type_8822b(dm);*/\n#endif\n#if (RTL8821C_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8821C)\n\t\tphydm_init_hw_info_by_rfe_type_8821c(dm);\n#endif\n#if (RTL8197F_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8197F)\n\t\tphydm_init_hw_info_by_rfe_type_8197f(dm);\n#endif\n}\n\nvoid phydm_common_info_self_init(struct dm_struct *dm)\n{\n\tu32 reg_tmp = 0;\n\tu32 mask_tmp = 0;\n\n\tdm->run_in_drv_fw = RUN_IN_DRIVER;\n\n\t/*@BB IP Generation*/\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tdm->ic_ip_series = PHYDM_IC_JGR3;\n\telse if (dm->support_ic_type & ODM_IC_11AC_SERIES)\n\t\tdm->ic_ip_series = PHYDM_IC_AC;\n\telse if (dm->support_ic_type & ODM_IC_11N_SERIES)\n\t\tdm->ic_ip_series = PHYDM_IC_N;\n\n\t/*@BB phy-status Generation*/\n\tif (dm->support_ic_type & PHYSTS_3RD_TYPE_IC)\n\t\tdm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_3;\n\telse if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)\n\t\tdm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_2;\n\telse\n\t\tdm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_1;\n\n\tphydm_init_cck_setting(dm);\n\n\treg_tmp = ODM_REG(BB_RX_PATH, dm);\n\tmask_tmp = ODM_BIT(BB_RX_PATH, dm);\n\tdm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, reg_tmp, mask_tmp);\n#if (DM_ODM_SUPPORT_TYPE != ODM_CE)\n\tdm->is_net_closed = &dm->BOOLEAN_temp;\n\n\tphydm_init_debug_setting(dm);\n#endif\n\tphydm_init_soft_ml_setting(dm);\n\n\tdm->phydm_sys_up_time = 0;\n\n\tif (dm->support_ic_type & ODM_IC_1SS)\n\t\tdm->num_rf_path = 1;\n\telse if (dm->support_ic_type & ODM_IC_2SS)\n\t\tdm->num_rf_path = 2;\n\t#if 0\n\t/* @RTK do not has IC which is equipped with 3 RF paths,\n\t * so ODM_IC_3SS is an enpty macro and result in coverity check errors\n\t */\n\telse if (dm->support_ic_type & ODM_IC_3SS)\n\t\tdm->num_rf_path = 3;\n\t#endif\n\telse if (dm->support_ic_type & ODM_IC_4SS)\n\t\tdm->num_rf_path = 4;\n\telse\n\t\tdm->num_rf_path = 1;\n\n\tphydm_trx_antenna_setting_init(dm, dm->num_rf_path);\n\n\tdm->tx_rate = 0xFF;\n\tdm->rssi_min_by_path = 0xFF;\n\n\tdm->number_linked_client = 0;\n\tdm->pre_number_linked_client = 0;\n\tdm->number_active_client = 0;\n\tdm->pre_number_active_client = 0;\n\n\tdm->last_tx_ok_cnt = 0;\n\tdm->last_rx_ok_cnt = 0;\n\tdm->tx_tp = 0;\n\tdm->rx_tp = 0;\n\tdm->total_tp = 0;\n\tdm->traffic_load = TRAFFIC_LOW;\n\n\tdm->nbi_set_result = 0;\n\tdm->is_init_hw_info_by_rfe = false;\n\tdm->pre_dbg_priority = DBGPORT_RELEASE;\n\tdm->tp_active_th = 5;\n\tdm->disable_phydm_watchdog = 0;\n\n\tdm->u8_dummy = 0xf;\n\tdm->u16_dummy = 0xffff;\n\tdm->u32_dummy = 0xffffffff;\n\n\tdm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;\n\tdm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;\n\tdm->pre_is_linked = false;\n\tdm->is_linked = false;\n\n\tif (!(dm->is_fcs_mode_enable)) {\n\t\tdm->is_fcs_mode_enable = &dm->boolean_dummy;\n\t\tpr_debug(\"[Warning] is_fcs_mode_enable=NULL\\n\");\n\t}\n}\n\nvoid phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_iot_center\t*iot_table = &dm->iot_table;\n\n\tPHYDM_DBG(dm, DBG_CMN, \"[IOT] 0x%x = %d\\n\", iot_idx, en);\n\tswitch (iot_idx) {\n\tcase 0x021f0800:\n\t\tiot_table->patch_id_021f0800 = en;\n\t\tPHYDM_DBG(dm, DBG_CMN, \"[IOT] patch_id_021f0800 = %d\\n\",\n\t\t\t  iot_table->patch_id_021f0800);\n\t\tbreak;\n\tdefault:\n\t\tpr_debug(\"[%s] warning!\\n\", __func__);\n\t\tbreak;\n\t}\n}\n\nvoid phydm_cmn_sta_info_update(void *dm_void, u8 macid)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct cmn_sta_info *sta = dm->phydm_sta_info[macid];\n\tstruct ra_sta_info *ra = NULL;\n\n\tif (is_sta_active(sta)) {\n\t\tra = &sta->ra_info;\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_RA_MASK, \"[Warning] %s invalid sta_info\\n\",\n\t\t\t  __func__);\n\t\treturn;\n\t}\n\n\tPHYDM_DBG(dm, DBG_RA_MASK, \"%s ======>\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_RA_MASK, \"MACID=%d\\n\", sta->mac_id);\n\n\t/*@[Calculate TX/RX state]*/\n\tif (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1))\n\t\tra->txrx_state = TX_STATE;\n\telse if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1))\n\t\tra->txrx_state = RX_STATE;\n\telse\n\t\tra->txrx_state = BI_DIRECTION_STATE;\n\n\tra->is_noisy = dm->noisy_decision;\n}\n\nvoid phydm_common_info_self_update(struct dm_struct *dm)\n{\n\tu8 sta_cnt = 0, num_active_client = 0;\n\tu32 i, one_entry_macid = 0;\n\tu32 ma_rx_tp = 0;\n\tu32 tp_diff = 0;\n\tstruct cmn_sta_info *sta;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tPADAPTER adapter = (PADAPTER)dm->adapter;\n\tPMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;\n\n\tsta = dm->phydm_sta_info[0];\n\tif (mgnt_info->mAssoc) {\n\t\tsta->dm_ctrl |= STA_DM_CTRL_ACTIVE;\n\t\tfor (i = 0; i < 6; i++)\n\t\t\tsta->mac_addr[i] = mgnt_info->Bssid[i];\n\t} else if (GetFirstClientPort(adapter)) {\n\t\tstruct _ADAPTER *client_adapter = GetFirstClientPort(adapter);\n\n\t\tsta->dm_ctrl |= STA_DM_CTRL_ACTIVE;\n\t\tfor (i = 0; i < 6; i++)\n\t\t\tsta->mac_addr[i] = client_adapter->MgntInfo.Bssid[i];\n\t} else {\n\t\tsta->dm_ctrl = sta->dm_ctrl & (~STA_DM_CTRL_ACTIVE);\n\t\tfor (i = 0; i < 6; i++)\n\t\t\tsta->mac_addr[i] = 0;\n\t}\n\n\t/* STA mode is linked to AP */\n\tif (is_sta_active(sta) && !ACTING_AS_AP(adapter))\n\t\tdm->bsta_state = true;\n\telse\n\t\tdm->bsta_state = false;\n#endif\n\n\tfor (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {\n\t\tsta = dm->phydm_sta_info[i];\n\t\tif (is_sta_active(sta)) {\n\t\t\tsta_cnt++;\n\n\t\t\tif (sta_cnt == 1)\n\t\t\t\tone_entry_macid = i;\n\n\t\t\tphydm_cmn_sta_info_update(dm, (u8)i);\n\t\t\t#ifdef PHYDM_BEAMFORMING_SUPPORT\n\t\t\t/*@phydm_get_txbf_device_num(dm, (u8)i);*/\n\t\t\t#endif\n\n\t\t\tma_rx_tp = sta->rx_moving_average_tp +\n\t\t\t\t   sta->tx_moving_average_tp;\n\n\t\t\tPHYDM_DBG(dm, DBG_COMMON_FLOW,\n\t\t\t\t  \"TP[%d]: ((%d )) bit/sec\\n\", i, ma_rx_tp);\n\n\t\t\tif (ma_rx_tp > ACTIVE_TP_THRESHOLD)\n\t\t\t\tnum_active_client++;\n\t\t}\n\t}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tdm->is_linked = (sta_cnt != 0) ? true : false;\n#endif\n\n\tif (sta_cnt == 1) {\n\t\tdm->is_one_entry_only = true;\n\t\tdm->one_entry_macid = one_entry_macid;\n\t\tdm->one_entry_tp = ma_rx_tp;\n\n\t\tdm->tp_active_occur = 0;\n\n\t\tPHYDM_DBG(dm, DBG_COMMON_FLOW,\n\t\t\t  \"one_entry_tp=((%d)), pre_one_entry_tp=((%d))\\n\",\n\t\t\t  dm->one_entry_tp, dm->pre_one_entry_tp);\n\n\t\tif (dm->one_entry_tp > dm->pre_one_entry_tp &&\n\t\t    dm->pre_one_entry_tp <= 2) {\n\t\t\ttp_diff = dm->one_entry_tp - dm->pre_one_entry_tp;\n\n\t\t\tif (tp_diff > dm->tp_active_th)\n\t\t\t\tdm->tp_active_occur = 1;\n\t\t}\n\t\tdm->pre_one_entry_tp = dm->one_entry_tp;\n\t} else {\n\t\tdm->is_one_entry_only = false;\n\t}\n\n\tdm->pre_number_linked_client = dm->number_linked_client;\n\tdm->pre_number_active_client = dm->number_active_client;\n\n\tdm->number_linked_client = sta_cnt;\n\tdm->number_active_client = num_active_client;\n\n\t/*Traffic load information update*/\n\tphydm_traffic_load_decision(dm);\n\n\tdm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD;\n\n\tdm->is_dfs_band = phydm_is_dfs_band(dm);\n\tdm->phy_dbg_info.show_phy_sts_cnt = 0;\n\n\t/*[Link Status Check]*/\n\tdm->first_connect = dm->is_linked && !dm->pre_is_linked;\n\tdm->first_disconnect = !dm->is_linked && dm->pre_is_linked;\n\tdm->pre_is_linked = dm->is_linked;\n}\n\nvoid phydm_common_info_self_reset(struct dm_struct *dm)\n{\n\tstruct odm_phy_dbg_info\t\t*dbg_t = &dm->phy_dbg_info;\n\n\tdbg_t->beacon_cnt_in_period = dbg_t->num_qry_beacon_pkt;\n\tdbg_t->num_qry_beacon_pkt = 0;\n\n\tdm->rxsc_l = 0xff;\n\tdm->rxsc_20 = 0xff;\n\tdm->rxsc_40 = 0xff;\n\tdm->rxsc_80 = 0xff;\n}\n\nvoid *\nphydm_get_structure(struct dm_struct *dm, u8 structure_type)\n\n{\n\tvoid *structure = NULL;\n\n\tswitch (structure_type) {\n\tcase PHYDM_FALSEALMCNT:\n\t\tstructure = &dm->false_alm_cnt;\n\t\tbreak;\n\n\tcase PHYDM_CFOTRACK:\n\t\tstructure = &dm->dm_cfo_track;\n\t\tbreak;\n\n\tcase PHYDM_ADAPTIVITY:\n\t\tstructure = &dm->adaptivity;\n\t\tbreak;\n\n\tcase PHYDM_DFS:\n\t\tstructure = &dm->dfs;\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn structure;\n}\n\nvoid phydm_phy_info_update(struct dm_struct *dm)\n{\n#if (RTL8822B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8822B)\n\t\tdm->phy_dbg_info.condi_num = phydm_get_condi_num_8822b(dm);\n#endif\n}\n\nvoid phydm_hw_setting(struct dm_struct *dm)\n{\n#if (RTL8821A_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8821)\n\t\todm_hw_setting_8821a(dm);\n#endif\n\n#if (RTL8814A_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8814A)\n\t\tphydm_hwsetting_8814a(dm);\n#endif\n\n#if (RTL8822B_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8822B)\n\t\tphydm_hwsetting_8822b(dm);\n#endif\n\n#if (RTL8812A_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8812)\n\t\tphydm_hwsetting_8812a(dm);\n#endif\n\n#if (RTL8197F_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8197F)\n\t\tphydm_hwsetting_8197f(dm);\n#endif\n\n#if (RTL8192F_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8192F)\n\t\tphydm_hwsetting_8192f(dm);\n#endif\n\n#if (RTL8822C_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8822C)\n\t\tphydm_hwsetting_8822c(dm);\n#endif\n}\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\nu64 phydm_supportability_init_win(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu64 support_ability = 0;\n\n\tswitch (dm->support_ic_type) {\n/*@---------------N Series--------------------*/\n#if (RTL8188E_SUPPORT)\n\tcase ODM_RTL8188E:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR |\n\t\t\tODM_BB_PRIMARY_CCA;\n\t\tbreak;\n#endif\n\n#if (RTL8192E_SUPPORT)\n\tcase ODM_RTL8192E:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR |\n\t\t\tODM_BB_PRIMARY_CCA;\n\t\tbreak;\n#endif\n\n#if (RTL8723B_SUPPORT)\n\tcase ODM_RTL8723B:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR |\n\t\t\tODM_BB_PRIMARY_CCA;\n\t\tbreak;\n#endif\n\n#if (RTL8703B_SUPPORT)\n\tcase ODM_RTL8703B:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8723D_SUPPORT)\n\tcase ODM_RTL8723D:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\tODM_BB_PWR_TRAIN\t|\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8710B_SUPPORT)\n\tcase ODM_RTL8710B:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\tODM_BB_PWR_TRAIN\t|\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8188F_SUPPORT)\n\tcase ODM_RTL8188F:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8192F_SUPPORT)\n\tcase ODM_RTL8192F:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\tODM_BB_PWR_TRAIN\t|\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ADAPTIVE_SOML |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\t/*ODM_BB_LNA_SAT_CHK\t\t|*/\n\t\t/*ODM_BB_PRIMARY_CCA*/\n\n\t\tbreak;\n#endif\n\n/*@---------------AC Series-------------------*/\n\n#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)\n\tcase ODM_RTL8812:\n\tcase ODM_RTL8821:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\tODM_BB_DYNAMIC_TXPWR |\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8814A_SUPPORT)\n\tcase ODM_RTL8814A:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\tODM_BB_DYNAMIC_TXPWR |\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8822B_SUPPORT)\n\tcase ODM_RTL8822B:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\t/*ODM_BB_ADAPTIVE_SOML |*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\t/*ODM_BB_PATH_DIV |*/\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8821C_SUPPORT)\n\tcase ODM_RTL8821C:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n/*@---------------JGR3 Series-------------------*/\n\n#if (RTL8822C_SUPPORT)\n\tcase ODM_RTL8822C:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/* ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_PATH_DIV |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8814B_SUPPORT)\n\tcase ODM_RTL8814B:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\t/*ODM_BB_CCK_PD |*/\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING;\n\t\t\t/*ODM_BB_ENV_MONITOR;*/\n\t\tbreak;\n#endif\n\n\tdefault:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\n\t\tpr_debug(\"[Warning] Supportability Init Warning !!!\\n\");\n\t\tbreak;\n\t}\n\n\treturn support_ability;\n}\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))\nu64 phydm_supportability_init_ce(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu64 support_ability = 0;\n\n\tswitch (dm->support_ic_type) {\n/*@---------------N Series--------------------*/\n#if (RTL8188E_SUPPORT)\n\tcase ODM_RTL8188E:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*@ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*@ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR |\n\t\t\tODM_BB_PRIMARY_CCA;\n\t\tbreak;\n#endif\n\n#if (RTL8192E_SUPPORT)\n\tcase ODM_RTL8192E:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*@ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*@ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR |\n\t\t\tODM_BB_PRIMARY_CCA;\n\t\tbreak;\n#endif\n\n#if (RTL8723B_SUPPORT)\n\tcase ODM_RTL8723B:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*@ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*@ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR |\n\t\t\tODM_BB_PRIMARY_CCA;\n\t\tbreak;\n#endif\n\n#if (RTL8703B_SUPPORT)\n\tcase ODM_RTL8703B:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*@ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*@ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8723D_SUPPORT)\n\tcase ODM_RTL8723D:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*@ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\tODM_BB_PWR_TRAIN\t|\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8710B_SUPPORT)\n\tcase ODM_RTL8710B:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*@ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*@ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8188F_SUPPORT)\n\tcase ODM_RTL8188F:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*@ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*@ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8192F_SUPPORT)\n\tcase ODM_RTL8192F:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\tODM_BB_PWR_TRAIN\t\t|\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\t/*@ODM_BB_ADAPTIVE_SOML |*/\n\t\t\tODM_BB_ENV_MONITOR;\n\t\t/*@ODM_BB_LNA_SAT_CHK\t\t|*/\n\t\t/*@ODM_BB_PRIMARY_CCA*/\n\t\tbreak;\n#endif\n/*@---------------AC Series-------------------*/\n\n#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)\n\tcase ODM_RTL8812:\n\tcase ODM_RTL8821:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*@ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*@ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8814A_SUPPORT)\n\tcase ODM_RTL8814A:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*@ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*@ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8822B_SUPPORT)\n\tcase ODM_RTL8822B:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*@ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*@ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\t/*ODM_BB_PATH_DIV |*/\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8821C_SUPPORT)\n\tcase ODM_RTL8821C:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*@ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*@ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n/*@---------------JGR3 Series-------------------*/\n\n#if (RTL8822C_SUPPORT)\n\tcase ODM_RTL8822C:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/* ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\t/* ODM_BB_PATH_DIV | */\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8814B_SUPPORT)\n\tcase ODM_RTL8814B:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*@ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR;\n\t\t\t/*ODM_BB_CCK_PD |*/\n\t\t\t/*@ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\t/*ODM_BB_RATE_ADAPTIVE |*/\n\t\t\t/*ODM_BB_CFO_TRACKING |*/\n\t\t\t/*ODM_BB_ENV_MONITOR;*/\n\t\tbreak;\n#endif\n\n\tdefault:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*@ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*@ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\n\t\tpr_debug(\"[Warning] Supportability Init Warning !!!\\n\");\n\t\tbreak;\n\t}\n\n\treturn support_ability;\n}\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\nu64 phydm_supportability_init_ap(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu64 support_ability = 0;\n\n\tswitch (dm->support_ic_type) {\n/*@---------------N Series--------------------*/\n#if (RTL8188E_SUPPORT)\n\tcase ODM_RTL8188E:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR |\n\t\t\tODM_BB_PRIMARY_CCA;\n\t\tbreak;\n#endif\n\n#if (RTL8192E_SUPPORT)\n\tcase ODM_RTL8192E:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR |\n\t\t\tODM_BB_PRIMARY_CCA;\n\t\tbreak;\n#endif\n\n#if (RTL8723B_SUPPORT)\n\tcase ODM_RTL8723B:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8198F_SUPPORT || RTL8197F_SUPPORT)\n\tcase ODM_RTL8198F:\n\t\tsupport_ability |=\n\t\t\t/*ODM_BB_DIG\t\t\t\t|*/\n\t\t\tODM_BB_RA_MASK |\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR;\n\t\t/*ODM_BB_CCK_PD\t\t\t|*/\n\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t/*ODM_BB_RATE_ADAPTIVE\t|*/\n\t\t/*ODM_BB_CFO_TRACKING\t\t|*/\n\t\t/*ODM_BB_ADAPTIVE_SOML\t|*/\n\t\t/*ODM_BB_ENV_MONITOR\t\t|*/\n\t\t/*ODM_BB_LNA_SAT_CHK\t\t|*/\n\t\t/*ODM_BB_PRIMARY_CCA;*/\n\t\tbreak;\n\tcase ODM_RTL8197F:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ADAPTIVE_SOML |\n\t\t\tODM_BB_ENV_MONITOR |\n\t\t\tODM_BB_LNA_SAT_CHK |\n\t\t\tODM_BB_PRIMARY_CCA;\n\t\tbreak;\n#endif\n\n#if (RTL8192F_SUPPORT)\n\tcase ODM_RTL8192F:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\t/*ODM_BB_CFO_TRACKING\t\t|*/\n\t\t\tODM_BB_ADAPTIVE_SOML |\n\t\t\tODM_BB_ENV_MONITOR\t\t|\n\t\t\t/*ODM_BB_LNA_SAT_CHK\t\t|*/\n\t\t\t/*ODM_BB_PRIMARY_CCA\t\t|*/\n\t\t\t0;\n\t\tbreak;\n#endif\n\n/*@---------------AC Series-------------------*/\n\n#if (RTL8881A_SUPPORT)\n\tcase ODM_RTL8881A:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8814A_SUPPORT)\n\tcase ODM_RTL8814A:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8822B_SUPPORT)\n\tcase ODM_RTL8822B:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\t/*ODM_BB_ADAPTIVE_SOML\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8821C_SUPPORT)\n\tcase ODM_RTL8821C:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\n\t\tbreak;\n#endif\n\n/*@---------------JGR3 Series-------------------*/\n\n#if (RTL8814B_SUPPORT)\n\tcase ODM_RTL8814B:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR;\n\t\t\t/*ODM_BB_CCK_PD |*/\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\t/*ODM_BB_RATE_ADAPTIVE |*/\n\t\t\t/*ODM_BB_CFO_TRACKING |*/\n\t\t\t/*ODM_BB_ENV_MONITOR;*/\n\t\tbreak;\n#endif\n\n\tdefault:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\n\t\tpr_debug(\"[Warning] Supportability Init Warning !!!\\n\");\n\t\tbreak;\n\t}\n\n#if 0\n\t/*@[Config Antenna Diveristy]*/\n\tif (*dm->enable_antdiv)\n\t\tsupport_ability |= ODM_BB_ANT_DIV;\n\n\t/*@[Config Adaptivity]*/\n\tif (*dm->enable_adaptivity)\n\t\tsupport_ability |= ODM_BB_ADAPTIVITY;\n#endif\n\n\treturn support_ability;\n}\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))\nu64 phydm_supportability_init_iot(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu64 support_ability = 0;\n\n\tswitch (dm->support_ic_type) {\n#if (RTL8710B_SUPPORT)\n\tcase ODM_RTL8710B:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8195A_SUPPORT)\n\tcase ODM_RTL8195A:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n#if (RTL8195B_SUPPORT)\n\tcase ODM_RTL8195B:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING;\n\t\t\t/*ODM_BB_ENV_MONITOR*/\n\t\tbreak;\n#endif\n\n#if (RTL8721D_SUPPORT)\n\tcase ODM_RTL8721D:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\t\tbreak;\n#endif\n\n\tdefault:\n\t\tsupport_ability |=\n\t\t\tODM_BB_DIG |\n\t\t\tODM_BB_RA_MASK |\n\t\t\t/*ODM_BB_DYNAMIC_TXPWR\t|*/\n\t\t\tODM_BB_FA_CNT |\n\t\t\tODM_BB_RSSI_MONITOR |\n\t\t\tODM_BB_CCK_PD |\n\t\t\t/*ODM_BB_PWR_TRAIN\t\t|*/\n\t\t\tODM_BB_RATE_ADAPTIVE |\n\t\t\tODM_BB_CFO_TRACKING |\n\t\t\tODM_BB_ENV_MONITOR;\n\n\t\tpr_debug(\"[Warning] Supportability Init Warning !!!\\n\");\n\t\tbreak;\n\t}\n\n\treturn support_ability;\n}\n#endif\n\nvoid phydm_fwoffload_ability_init(struct dm_struct *dm,\n\t\t\t\t  enum phydm_offload_ability offload_ability)\n{\n\tswitch (offload_ability) {\n\tcase PHYDM_PHY_PARAM_OFFLOAD:\n\t\tif (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)\n\t\t\tdm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;\n\t\tbreak;\n\n\tcase PHYDM_RF_IQK_OFFLOAD:\n\t\tdm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;\n\t\tbreak;\n\n\tdefault:\n\t\tPHYDM_DBG(dm, ODM_COMP_INIT, \"fwofflad, wrong init type!!\\n\");\n\t\tbreak;\n\t}\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"fw_offload_ability = %x\\n\",\n\t\t  dm->fw_offload_ability);\n}\n\nvoid phydm_fwoffload_ability_clear(struct dm_struct *dm,\n\t\t\t\t   enum phydm_offload_ability offload_ability)\n{\n\tswitch (offload_ability) {\n\tcase PHYDM_PHY_PARAM_OFFLOAD:\n\t\tif (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)\n\t\t\tdm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);\n\t\tbreak;\n\n\tcase PHYDM_RF_IQK_OFFLOAD:\n\t\tdm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);\n\t\tbreak;\n\n\tdefault:\n\t\tPHYDM_DBG(dm, ODM_COMP_INIT, \"fwofflad, wrong init type!!\\n\");\n\t\tbreak;\n\t}\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"fw_offload_ability = %x\\n\",\n\t\t  dm->fw_offload_ability);\n}\n\nvoid phydm_supportability_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu64 support_ability;\n\n\tif (dm->manual_supportability &&\n\t    *dm->manual_supportability != 0xffffffff) {\n\t\tsupport_ability = *dm->manual_supportability;\n\t} else if (*dm->mp_mode) {\n\t\tsupport_ability = 0;\n\t} else {\n\t\t#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\n\t\tsupport_ability = phydm_supportability_init_win(dm);\n\t\t#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\t\tsupport_ability = phydm_supportability_init_ap(dm);\n\t\t#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))\n\t\tsupport_ability = phydm_supportability_init_ce(dm);\n\t\t#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))\n\t\tsupport_ability = phydm_supportability_init_iot(dm);\n\t\t#endif\n\n\t\t/*@[Config Antenna Diversity]*/\n\t\tif (IS_FUNC_EN(dm->enable_antdiv))\n\t\t\tsupport_ability |= ODM_BB_ANT_DIV;\n\n\t\t/*@[Config TXpath Diversity]*/\n\t\tif (IS_FUNC_EN(dm->enable_pathdiv))\n\t\t\tsupport_ability |= ODM_BB_PATH_DIV;\n\n\t\t/*@[Config Adaptive SOML]*/\n\t\tif (IS_FUNC_EN(dm->en_adap_soml))\n\t\t\tsupport_ability |= ODM_BB_ADAPTIVE_SOML;\n\n\t\t/* @[Config Adaptivity]*/\n\t\tif (IS_FUNC_EN(dm->enable_adaptivity))\n\t\t\tsupport_ability |= ODM_BB_ADAPTIVITY;\n\t}\n\tdm->support_ability = support_ability;\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"IC=0x%x, mp=%d, Supportability=0x%llx\\n\",\n\t\t  dm->support_ic_type, *dm->mp_mode, dm->support_ability);\n}\n\nvoid phydm_rfe_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"RFE_Init\\n\");\n#if (RTL8822B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8822B)\n\t\tphydm_rfe_8822b_init(dm);\n#endif\n}\n\nvoid phydm_dm_early_init(struct dm_struct *dm)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tphydm_init_debug_setting(dm);\n#endif\n}\n\nvoid odm_dm_init(struct dm_struct *dm)\n{\n\thalrf_init(dm);\n\tphydm_supportability_init(dm);\n\tphydm_rfe_init(dm);\n\tphydm_common_info_self_init(dm);\n\tphydm_rx_phy_status_init(dm);\n#ifdef PHYDM_AUTO_DEGBUG\n\tphydm_auto_dbg_engine_init(dm);\n#endif\n\tphydm_dig_init(dm);\n#ifdef PHYDM_SUPPORT_CCKPD\n\tphydm_cck_pd_init(dm);\n#endif\n\tphydm_env_monitor_init(dm);\n\tphydm_adaptivity_init(dm);\n\tphydm_ra_info_init(dm);\n\tphydm_rssi_monitor_init(dm);\n\tphydm_cfo_tracking_init(dm);\n\tphydm_rf_init(dm);\n\tphydm_dc_cancellation(dm);\n#ifdef PHYDM_TXA_CALIBRATION\n\tphydm_txcurrentcalibration(dm);\n\tphydm_get_pa_bias_offset(dm);\n#endif\n#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\todm_antenna_diversity_init(dm);\n#endif\n#ifdef CONFIG_ADAPTIVE_SOML\n\tphydm_adaptive_soml_init(dm);\n#endif\n#ifdef CONFIG_PATH_DIVERSITY\n\tphydm_tx_path_diversity_init(dm);\n#endif\n#ifdef CONFIG_DYNAMIC_TX_TWR\n\tphydm_dynamic_tx_power_init(dm);\n#endif\n#if (PHYDM_LA_MODE_SUPPORT == 1)\n\tphydm_la_init(dm);\n#endif\n\n#ifdef PHYDM_BEAMFORMING_VERSION1\n\tphydm_beamforming_init(dm);\n#endif\n\n#if (RTL8188E_SUPPORT == 1)\n\todm_ra_info_init_all(dm);\n#endif\n#ifdef PHYDM_PRIMARY_CCA\n\tphydm_primary_cca_init(dm);\n#endif\n#ifdef CONFIG_PSD_TOOL\n\tphydm_psd_init(dm);\n#endif\n\n#ifdef CONFIG_SMART_ANTENNA\n\tphydm_smt_ant_init(dm);\n#endif\n#ifdef PHYDM_LNA_SAT_CHK_SUPPORT\n\tphydm_lna_sat_check_init(dm);\n#endif\n#ifdef CONFIG_MCC_DM\n\tphydm_mcc_init(dm);\n#endif\n\n#ifdef CONFIG_MU_RSOML\n\tphydm_mu_rsoml_init(dm);\n#endif\n}\n\nvoid odm_dm_reset(struct dm_struct *dm)\n{\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\n\t#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\todm_ant_div_reset(dm);\n\t#endif\n\tphydm_set_edcca_threshold_api(dm, dig_t->cur_ig_value);\n}\n\nvoid phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,\n\t\t\t     char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 dm_value[10] = {0};\n\tu64 pre_support_ability, one = 1;\n\tu64 comp = 0;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu8 i;\n\n\tfor (i = 0; i < 5; i++) {\n\t\tif (input[i + 1])\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);\n\t}\n\n\tpre_support_ability = dm->support_ability;\n\tcomp = dm->support_ability;\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\n================================\\n\");\n\n\tif (dm_value[0] == 100) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[Supportability] PhyDM Selection\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"================================\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"00. (( %s ))DIG\\n\",\n\t\t\t ((comp & ODM_BB_DIG) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"01. (( %s ))RA_MASK\\n\",\n\t\t\t ((comp & ODM_BB_RA_MASK) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"02. (( %s ))DYN_TXPWR\\n\",\n\t\t\t ((comp & ODM_BB_DYNAMIC_TXPWR) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"03. (( %s ))FA_CNT\\n\",\n\t\t\t ((comp & ODM_BB_FA_CNT) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"04. (( %s ))RSSI_MNTR\\n\",\n\t\t\t ((comp & ODM_BB_RSSI_MONITOR) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"05. (( %s ))CCK_PD\\n\",\n\t\t\t ((comp & ODM_BB_CCK_PD) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"06. (( %s ))ANT_DIV\\n\",\n\t\t\t ((comp & ODM_BB_ANT_DIV) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"07. (( %s ))SMT_ANT\\n\",\n\t\t\t ((comp & ODM_BB_SMT_ANT) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"08. (( %s ))PWR_TRAIN\\n\",\n\t\t\t ((comp & ODM_BB_PWR_TRAIN) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"09. (( %s ))RA\\n\",\n\t\t\t ((comp & ODM_BB_RATE_ADAPTIVE) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"10. (( %s ))PATH_DIV\\n\",\n\t\t\t ((comp & ODM_BB_PATH_DIV) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"11. (( %s ))DFS\\n\",\n\t\t\t ((comp & ODM_BB_DFS) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"12. (( %s ))DYN_ARFR\\n\",\n\t\t\t ((comp & ODM_BB_DYNAMIC_ARFR) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"13. (( %s ))ADAPTIVITY\\n\",\n\t\t\t ((comp & ODM_BB_ADAPTIVITY) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"14. (( %s ))CFO_TRACK\\n\",\n\t\t\t ((comp & ODM_BB_CFO_TRACKING) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"15. (( %s ))ENV_MONITOR\\n\",\n\t\t\t ((comp & ODM_BB_ENV_MONITOR) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"16. (( %s ))PRI_CCA\\n\",\n\t\t\t ((comp & ODM_BB_PRIMARY_CCA) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"17. (( %s ))ADPTV_SOML\\n\",\n\t\t\t ((comp & ODM_BB_ADAPTIVE_SOML) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"18. (( %s ))LNA_SAT_CHK\\n\",\n\t\t\t ((comp & ODM_BB_LNA_SAT_CHK) ? (\"V\") : (\".\")));\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"================================\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[Supportability] PhyDM offload ability\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"================================\\n\");\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"00. (( %s ))PHY PARAM OFFLOAD\\n\",\n\t\t\t ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ?\n\t\t\t (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"01. (( %s ))RF IQK OFFLOAD\\n\",\n\t\t\t ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ?\n\t\t\t (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"================================\\n\");\n\n\t} else if (dm_value[0] == 101) {\n\t\tdm->support_ability = 0;\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Disable all support_ability components\\n\");\n\t} else {\n\t\tif (dm_value[1] == 1) { /* @enable */\n\t\t\tdm->support_ability |= (one << dm_value[0]);\n\t\t} else if (dm_value[1] == 2) {/* @disable */\n\t\t\tdm->support_ability &= ~(one << dm_value[0]);\n\t\t} else {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[Warning!!!]  1:enable,  2:disable\\n\");\n\t\t}\n\t}\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"pre-supportability = 0x%llx\\n\", pre_support_ability);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"Cur-supportability = 0x%llx\\n\", dm->support_ability);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"================================\\n\");\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_watchdog_lps_32k(struct dm_struct *dm)\n{\n\tPHYDM_DBG(dm, DBG_COMMON_FLOW, \"%s ======>\\n\", __func__);\n\n\tphydm_common_info_self_update(dm);\n\tphydm_rssi_monitor_check(dm);\n\tphydm_dig_lps_32k(dm);\n\tphydm_common_info_self_reset(dm);\n}\n\nvoid phydm_watchdog_lps(struct dm_struct *dm)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))\n\tPHYDM_DBG(dm, DBG_COMMON_FLOW, \"%s ======>\\n\", __func__);\n\n\tphydm_common_info_self_update(dm);\n\tphydm_rssi_monitor_check(dm);\n\tphydm_basic_dbg_message(dm);\n\tphydm_receiver_blocking(dm);\n\tphydm_false_alarm_counter_statistics(dm);\n\tphydm_dig_by_rssi_lps(dm);\n\t#ifdef PHYDM_SUPPORT_CCKPD\n\tphydm_cck_pd_th(dm);\n\t#endif\n\tphydm_adaptivity(dm);\n\t#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))\n\t#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\t/*@enable AntDiv in PS mode, request from SD4 Jeff*/\n\todm_antenna_diversity(dm);\n\t#endif\n\t#endif\n\tphydm_common_info_self_reset(dm);\n#endif\n}\n\nvoid phydm_watchdog_mp(struct dm_struct *dm)\n{\n}\n\nvoid phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (pause_type == PHYDM_PAUSE) {\n\t\tdm->disable_phydm_watchdog = 1;\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"PHYDM Stop\\n\");\n\t} else {\n\t\tdm->disable_phydm_watchdog = 0;\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"PHYDM Start\\n\");\n\t}\n}\n\nu8 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,\n\t\t    enum phydm_pause_type pause_type,\n\t\t    enum phydm_pause_level pause_lv, u8 val_lehgth,\n\t\t    u32 *val_buf)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_func_poiner *func_t = &dm->phydm_func_handler;\n\ts8 *pause_lv_pre = &dm->s8_dummy;\n\tu32 *bkp_val = &dm->u32_dummy;\n\tu32 ori_val[5] = {0};\n\tu64 pause_func_bitmap = (u64)BIT(pause_func);\n\tu8 i = 0;\n\tu8 en_2rcca = 0;\n\tu8 en_bw40m = 0;\n\tu8 pause_result = PAUSE_FAIL;\n\n\tPHYDM_DBG(dm, ODM_COMP_API, \"\\n\");\n\tPHYDM_DBG(dm, ODM_COMP_API, \"[%s][%s] LV=%d, Len=%d\\n\", __func__,\n\t\t  ((pause_type == PHYDM_PAUSE) ? \"Pause\" :\n\t\t  ((pause_type == PHYDM_RESUME) ? \"Resume\" : \"Pause no_set\")),\n\t\t  pause_lv, val_lehgth);\n\n\tif (pause_lv >= PHYDM_PAUSE_MAX_NUM) {\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[WARNING]Wrong LV=%d\\n\", pause_lv);\n\t\treturn PAUSE_FAIL;\n\t}\n\n\tif (pause_func == F00_DIG) {\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[DIG]\\n\");\n\n\t\tif (val_lehgth != 1) {\n\t\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[WARNING] length != 1\\n\");\n\t\t\treturn PAUSE_FAIL;\n\t\t}\n\n\t\tori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value);\n\t\tpause_lv_pre = &dm->pause_lv_table.lv_dig;\n\t\tbkp_val = (u32 *)(&dm->dm_dig_table.rvrt_val);\n\t\t/*@function pointer hook*/\n\t\tfunc_t->pause_phydm_handler = phydm_set_dig_val;\n\n#ifdef PHYDM_SUPPORT_CCKPD\n\t} else if (pause_func == F05_CCK_PD) {\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[CCK_PD]\\n\");\n\n\t\tif (val_lehgth != 1) {\n\t\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[WARNING] length != 1\\n\");\n\t\t\treturn PAUSE_FAIL;\n\t\t}\n\n\t\tori_val[0] = (u32)dm->dm_cckpd_table.cck_pd_lv;\n\t\tpause_lv_pre = &dm->pause_lv_table.lv_cckpd;\n\t\tbkp_val = (u32 *)(&dm->dm_cckpd_table.rvrt_val);\n\t\t/*@function pointer hook*/\n\t\tfunc_t->pause_phydm_handler = phydm_set_cckpd_val;\n#endif\n\n#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\t} else if (pause_func == F06_ANT_DIV) {\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[AntDiv]\\n\");\n\n\t\tif (val_lehgth != 1) {\n\t\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[WARNING] length != 1\\n\");\n\t\t\treturn PAUSE_FAIL;\n\t\t}\n\t\t/*@default antenna*/\n\t\tori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant);\n\t\tpause_lv_pre = &dm->pause_lv_table.lv_antdiv;\n\t\tbkp_val = (u32 *)(&dm->dm_fat_table.rvrt_val);\n\t\t/*@function pointer hook*/\n\t\tfunc_t->pause_phydm_handler = phydm_set_antdiv_val;\n\n#endif\n#ifdef PHYDM_SUPPORT_ADAPTIVITY\n\t} else if (pause_func == F13_ADPTVTY) {\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[Adaptivity]\\n\");\n\n\t\tif (val_lehgth != 2) {\n\t\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[WARNING] length != 2\\n\");\n\t\t\treturn PAUSE_FAIL;\n\t\t}\n\n\t\tori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/\n\t\tori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/\n\t\tpause_lv_pre = &dm->pause_lv_table.lv_adapt;\n\t\tbkp_val = (u32 *)(&dm->adaptivity.rvrt_val);\n\t\t/*@function pointer hook*/\n\t\tfunc_t->pause_phydm_handler = phydm_set_edcca_val;\n\n#endif\n#ifdef CONFIG_ADAPTIVE_SOML\n\t} else if (pause_func == F17_ADPTV_SOML) {\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[AD-SOML]\\n\");\n\n\t\tif (val_lehgth != 1) {\n\t\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[WARNING] length != 1\\n\");\n\t\t\treturn PAUSE_FAIL;\n\t\t}\n\t\t/*SOML_ON/OFF*/\n\t\tori_val[0] = (u32)(dm->dm_soml_table.soml_on_off);\n\n\t\tpause_lv_pre = &dm->pause_lv_table.lv_adsl;\n\t\tbkp_val = (u32 *)(&dm->dm_soml_table.rvrt_val);\n\t\t /*@function pointer hook*/\n\t\tfunc_t->pause_phydm_handler = phydm_set_adsl_val;\n\n#endif\n\t} else {\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[WARNING] error func idx\\n\");\n\t\treturn PAUSE_FAIL;\n\t}\n\n\tPHYDM_DBG(dm, ODM_COMP_API, \"Pause_LV{new , pre} = {%d ,%d}\\n\",\n\t\t  pause_lv, *pause_lv_pre);\n\n\tif (pause_type == PHYDM_PAUSE || pause_type == PHYDM_PAUSE_NO_SET) {\n\t\tif (pause_lv <= *pause_lv_pre) {\n\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t  \"[PAUSE FAIL] Pre_LV >= Curr_LV\\n\");\n\t\t\treturn PAUSE_FAIL;\n\t\t}\n\n\t\tif (!(dm->pause_ability & pause_func_bitmap)) {\n\t\t\tfor (i = 0; i < val_lehgth; i++)\n\t\t\t\tbkp_val[i] = ori_val[i];\n\t\t}\n\n\t\tdm->pause_ability |= pause_func_bitmap;\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"pause_ability=0x%llx\\n\",\n\t\t\t  dm->pause_ability);\n\n\t\tif (pause_type == PHYDM_PAUSE) {\n\t\t\tfor (i = 0; i < val_lehgth; i++)\n\t\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t\t  \"[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\\n\",\n\t\t\t\t\t  i, val_buf[i], bkp_val[i]);\n\t\t\tfunc_t->pause_phydm_handler(dm, val_buf, val_lehgth);\n\t\t} else {\n\t\t\tfor (i = 0; i < val_lehgth; i++)\n\t\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t\t  \"[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\\n\",\n\t\t\t\t\t  i, bkp_val[i]);\n\t\t}\n\n\t\t*pause_lv_pre = pause_lv;\n\t\tpause_result = PAUSE_SUCCESS;\n\n\t} else if (pause_type == PHYDM_RESUME) {\n\t\tif ((dm->pause_ability & pause_func_bitmap) == 0) {\n\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t  \"[RESUME] No Need to Revert\\n\");\n\t\t\treturn PAUSE_SUCCESS;\n\t\t}\n\n\t\tdm->pause_ability &= ~pause_func_bitmap;\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"pause_ability=0x%llx\\n\",\n\t\t\t  dm->pause_ability);\n\n\t\t*pause_lv_pre = PHYDM_PAUSE_RELEASE;\n\n\t\tfor (i = 0; i < val_lehgth; i++) {\n\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t  \"[RESUME] val_idx[%d]={0x%x}\\n\", i,\n\t\t\t\t  bkp_val[i]);\n\t\t}\n\n\t\tfunc_t->pause_phydm_handler(dm, bkp_val, val_lehgth);\n\n\t\tpause_result = PAUSE_SUCCESS;\n\t} else {\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[WARNING] error pause_type\\n\");\n\t\tpause_result = PAUSE_FAIL;\n\t}\n\treturn pause_result;\n}\n\nvoid phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,\n\t\t\t      char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tchar help[] = \"-h\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 i;\n\tu8 length = 0;\n\tu32 buf[5] = {0};\n\tu8 set_result = 0;\n\tenum phydm_func_idx func = 0;\n\tenum phydm_pause_type type = 0;\n\tenum phydm_pause_level lv = 0;\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{Func} {1:pause,2:pause no set 3:Resume} {lv:0~3} Val[5:0]\\n\");\n\n\t\tgoto out;\n\t}\n\n\tfor (i = 0; i < 10; i++) {\n\t\tif (input[i + 1])\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);\n\t}\n\n\tfunc = (enum phydm_func_idx)var1[0];\n\ttype = (enum phydm_pause_type)var1[1];\n\tlv = (enum phydm_pause_level)var1[2];\n\n\tfor (i = 0; i < 5; i++)\n\t\tbuf[i] = var1[3 + i];\n\n\tif (func == F00_DIG) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[DIG]\\n\");\n\t\tlength = 1;\n\n\t} else if (func == F05_CCK_PD) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[CCK_PD]\\n\");\n\t\tlength = 1;\n\t} else if (func == F06_ANT_DIV) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[Ant_Div]\\n\");\n\t\tlength = 1;\n\t} else if (func == F13_ADPTVTY) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[Adaptivity]\\n\");\n\t\tlength = 2;\n\t} else if (func == F17_ADPTV_SOML) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[ADSL]\\n\");\n\t\tlength = 1;\n\t} else {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[Set Function Error]\\n\");\n\t\tlength = 0;\n\t}\n\n\tif (length != 0) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{%s, lv=%d} val = %d, %d}\\n\",\n\t\t\t ((type == PHYDM_PAUSE) ? \"Pause\" :\n\t\t\t ((type == PHYDM_RESUME) ? \"Resume\" : \"Pause no_set\")),\n\t\t\t lv, var1[3], var1[4]);\n\n\t\tset_result = phydm_pause_func(dm, func, type, lv, length, buf);\n\t}\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"set_result = %d\\n\", set_result);\n\nout:\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nu8 phydm_stop_dm_watchdog_check(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->disable_phydm_watchdog == 1) {\n\t\tPHYDM_DBG(dm, DBG_COMMON_FLOW, \"Disable phydm\\n\");\n\t\treturn true;\n\t} else {\n\t\treturn false;\n\t}\n}\n\nvoid phydm_watchdog(struct dm_struct *dm)\n{\n\tPHYDM_DBG(dm, DBG_COMMON_FLOW, \"%s ======>\\n\", __func__);\n\n\tphydm_common_info_self_update(dm);\n\tphydm_phy_info_update(dm);\n\tphydm_rssi_monitor_check(dm);\n\tphydm_basic_dbg_message(dm);\n\tphydm_dm_summary(dm, FIRST_MACID);\n#ifdef PHYDM_AUTO_DEGBUG\n\tphydm_auto_dbg_engine(dm);\n#endif\n\tphydm_receiver_blocking(dm);\n\n\tif (phydm_stop_dm_watchdog_check(dm) == true)\n\t\treturn;\n\n\tphydm_hw_setting(dm);\n\n\t#ifdef PHYDM_TDMA_DIG_SUPPORT\n\tif (dm->original_dig_restore == 0)\n\t\tphydm_tdma_dig_timer_check(dm);\n\telse\n\t#endif\n\t{\n\t\tphydm_false_alarm_counter_statistics(dm);\n\t\tphydm_noisy_detection(dm);\n\t\tphydm_dig(dm);\n\t\t#ifdef PHYDM_SUPPORT_CCKPD\n\t\tphydm_cck_pd_th(dm);\n\t\t#endif\n\t}\n\n#ifdef PHYDM_POWER_TRAINING_SUPPORT\n\tphydm_update_power_training_state(dm);\n#endif\n\tphydm_adaptivity(dm);\n\tphydm_ra_info_watchdog(dm);\n#ifdef CONFIG_PATH_DIVERSITY\n\tphydm_tx_path_diversity(dm);\n#endif\n\tphydm_cfo_tracking(dm);\n#ifdef CONFIG_DYNAMIC_TX_TWR\n\tphydm_dynamic_tx_power(dm);\n#endif\n#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\todm_antenna_diversity(dm);\n#endif\n#ifdef CONFIG_ADAPTIVE_SOML\n\tphydm_adaptive_soml(dm);\n#endif\n\n#ifdef PHYDM_BEAMFORMING_VERSION1\n\tphydm_beamforming_watchdog(dm);\n#endif\n\n\thalrf_watchdog(dm);\n#ifdef PHYDM_PRIMARY_CCA\n\tphydm_primary_cca(dm);\n#endif\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\todm_dtc(dm);\n#endif\n\n\tphydm_env_mntr_watchdog(dm);\n\n#ifdef PHYDM_LNA_SAT_CHK_SUPPORT\n\tphydm_lna_sat_chk_watchdog(dm);\n#endif\n#ifdef CONFIG_MCC_DM\n\tphydm_mcc_switch(dm);\n#endif\n\n#ifdef CONFIG_MU_RSOML\n\tphydm_mu_rsoml_decision(dm);\n#endif\n\n\tphydm_common_info_self_reset(dm);\n}\n\n/*@\n * Init /.. Fixed HW value. Only init time.\n */\nvoid odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info,\n\t\t       u64 value)\n{\n\t/* This section is used for init value */\n\tswitch (cmn_info) {\n\t/* @Fixed ODM value. */\n\tcase ODM_CMNINFO_ABILITY:\n\t\tdm->support_ability = (u64)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_RF_TYPE:\n\t\tdm->rf_type = (u8)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_PLATFORM:\n\t\tdm->support_platform = (u8)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_INTERFACE:\n\t\tdm->support_interface = (u8)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_MP_TEST_CHIP:\n\t\tdm->is_mp_chip = (u8)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_IC_TYPE:\n\t\tdm->support_ic_type = (u32)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_CUT_VER:\n\t\tdm->cut_version = (u8)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_FAB_VER:\n\t\tdm->fab_version = (u8)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_FW_VER:\n\t\tdm->fw_version = (u8)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_FW_SUB_VER:\n\t\tdm->fw_sub_version = (u8)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_RFE_TYPE:\n#if (RTL8821C_SUPPORT)\n\t\tif (dm->support_ic_type & ODM_RTL8821C)\n\t\t\tdm->rfe_type_expand = (u8)value;\n\t\telse\n#endif\n\t\t\tdm->rfe_type = (u8)value;\n\t\tphydm_init_hw_info_by_rfe(dm);\n\t\tbreak;\n\n\tcase ODM_CMNINFO_RF_ANTENNA_TYPE:\n\t\tdm->ant_div_type = (u8)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:\n\t\tdm->with_extenal_ant_switch = (u8)value;\n\t\tbreak;\n\n#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\tcase ODM_CMNINFO_BE_FIX_TX_ANT:\n\t\tdm->dm_fat_table.b_fix_tx_ant = (u8)value;\n\t\tbreak;\n#endif\n\n\tcase ODM_CMNINFO_BOARD_TYPE:\n\t\tif (!dm->is_init_hw_info_by_rfe)\n\t\t\tdm->board_type = (u8)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_PACKAGE_TYPE:\n\t\tif (!dm->is_init_hw_info_by_rfe)\n\t\t\tdm->package_type = (u8)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_EXT_LNA:\n\t\tif (!dm->is_init_hw_info_by_rfe)\n\t\t\tdm->ext_lna = (u8)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_5G_EXT_LNA:\n\t\tif (!dm->is_init_hw_info_by_rfe)\n\t\t\tdm->ext_lna_5g = (u8)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_EXT_PA:\n\t\tif (!dm->is_init_hw_info_by_rfe)\n\t\t\tdm->ext_pa = (u8)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_5G_EXT_PA:\n\t\tif (!dm->is_init_hw_info_by_rfe)\n\t\t\tdm->ext_pa_5g = (u8)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_GPA:\n\t\tif (!dm->is_init_hw_info_by_rfe)\n\t\t\tdm->type_gpa = (u16)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_APA:\n\t\tif (!dm->is_init_hw_info_by_rfe)\n\t\t\tdm->type_apa = (u16)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_GLNA:\n\t\tif (!dm->is_init_hw_info_by_rfe)\n\t\t\tdm->type_glna = (u16)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_ALNA:\n\t\tif (!dm->is_init_hw_info_by_rfe)\n\t\t\tdm->type_alna = (u16)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_EXT_TRSW:\n\t\tif (!dm->is_init_hw_info_by_rfe)\n\t\t\tdm->ext_trsw = (u8)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_EXT_LNA_GAIN:\n\t\tdm->ext_lna_gain = (u8)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_PATCH_ID:\n\t\tdm->iot_table.win_patch_id = (u8)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_BINHCT_TEST:\n\t\tdm->is_in_hct_test = (boolean)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_BWIFI_TEST:\n\t\tdm->wifi_test = (u8)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_SMART_CONCURRENT:\n\t\tdm->is_dual_mac_smart_concurrent = (boolean)value;\n\t\tbreak;\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tcase ODM_CMNINFO_CONFIG_BB_RF:\n\t\tdm->config_bbrf = (boolean)value;\n\t\tbreak;\n#endif\n\tcase ODM_CMNINFO_IQKPAOFF:\n\t\tdm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_REGRFKFREEENABLE:\n\t\tdm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_RFKFREEENABLE:\n\t\tdm->rf_calibrate_info.rf_kfree_enable = (u8)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:\n\t\tdm->normal_rx_path = (u8)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_VALID_PATH_SET:\n\t\tdm->valid_path_set = (u8)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_EFUSE0X3D8:\n\t\tdm->efuse0x3d8 = (u8)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_EFUSE0X3D7:\n\t\tdm->efuse0x3d7 = (u8)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_ADVANCE_OTA:\n\t\tdm->p_advance_ota = (u8)value;\n\t\tbreak;\n\n#ifdef CONFIG_PHYDM_DFS_MASTER\n\tcase ODM_CMNINFO_DFS_REGION_DOMAIN:\n\t\tdm->dfs_region_domain = (u8)value;\n\t\tbreak;\n#endif\n\tcase ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING:\n\t\tdm->soft_ap_special_setting = (u32)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_X_CAP_SETTING:\n\t\tdm->dm_cfo_track.crystal_cap_default = (u8)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_DPK_EN:\n\t\t/*@dm->dpk_en = (u1Byte)value;*/\n\t\thalrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value);\n\t\tbreak;\n\n\tcase ODM_CMNINFO_HP_HWID:\n\t\tdm->hp_hw_id = (boolean)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_DIS_DPD:\n\t\tdm->en_dis_dpd = (boolean)value;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info,\n\t\t       void *value)\n{\n\t/* @Hook call by reference pointer. */\n\tswitch (cmn_info) {\n\t/* @Dynamic call by reference pointer. */\n\tcase ODM_CMNINFO_TX_UNI:\n\t\tdm->num_tx_bytes_unicast = (u64 *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_RX_UNI:\n\t\tdm->num_rx_bytes_unicast = (u64 *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_BAND:\n\t\tdm->band_type = (u8 *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_SEC_CHNL_OFFSET:\n\t\tdm->sec_ch_offset = (u8 *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_SEC_MODE:\n\t\tdm->security = (u8 *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_BW:\n\t\tdm->band_width = (u8 *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_CHNL:\n\t\tdm->channel = (u8 *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_SCAN:\n\t\tdm->is_scan_in_process = (boolean *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_POWER_SAVING:\n\t\tdm->is_power_saving = (boolean *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_TDMA:\n\t\tdm->is_tdma = (boolean *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_ONE_PATH_CCA:\n\t\tdm->one_path_cca = (u8 *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_DRV_STOP:\n\t\tdm->is_driver_stopped = (boolean *)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_INIT_ON:\n\t\tdm->pinit_adpt_in_progress = (boolean *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_ANT_TEST:\n\t\tdm->antenna_test = (u8 *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_NET_CLOSED:\n\t\tdm->is_net_closed = (boolean *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_FORCED_RATE:\n\t\tdm->forced_data_rate = (u16 *)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_ANT_DIV:\n\t\tdm->enable_antdiv = (u8 *)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_PATH_DIV:\n\t\tdm->enable_pathdiv = (u8 *)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_ADAPTIVE_SOML:\n\t\tdm->en_adap_soml = (u8 *)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_ADAPTIVITY:\n\t\tdm->enable_adaptivity = (u8 *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_P2P_LINK:\n\t\tdm->dm_dig_table.is_p2p_in_process = (u8 *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_IS1ANTENNA:\n\t\tdm->is_1_antenna = (boolean *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_RFDEFAULTPATH:\n\t\tdm->rf_default_path = (u8 *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_FCS_MODE: /* @fast channel switch (= MCC mode)*/\n\t\tdm->is_fcs_mode_enable = (boolean *)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_HUBUSBMODE:\n\t\tdm->hub_usb_mode = (u8 *)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:\n\t\tdm->is_fw_dw_rsvd_page_in_progress = (boolean *)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_TX_TP:\n\t\tdm->current_tx_tp = (u32 *)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_RX_TP:\n\t\tdm->current_rx_tp = (u32 *)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_SOUNDING_SEQ:\n\t\tdm->sounding_seq = (u8 *)value;\n\t\tbreak;\n#ifdef CONFIG_PHYDM_DFS_MASTER\n\tcase ODM_CMNINFO_DFS_MASTER_ENABLE:\n\t\tdm->dfs_master_enabled = (u8 *)value;\n\t\tbreak;\n#endif\n\n#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\tcase ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:\n\t\tdm->dm_fat_table.p_force_tx_by_desc = (u8 *)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:\n\t\tdm->dm_fat_table.p_default_s0_s1 = (u8 *)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_BF_ANTDIV_DECISION:\n\t\tdm->dm_fat_table.is_no_csi_feedback = (boolean *)value;\n\t\tbreak;\n#endif\n\n\tcase ODM_CMNINFO_SOFT_AP_MODE:\n\t\tdm->soft_ap_mode = (u32 *)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_MP_MODE:\n\t\tdm->mp_mode = (u8 *)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_INTERRUPT_MASK:\n\t\tdm->interrupt_mask = (u32 *)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_BB_OPERATION_MODE:\n\t\tdm->bb_op_mode = (u8 *)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_MANUAL_SUPPORTABILITY:\n\t\tdm->manual_supportability = (u32 *)value;\n\t\tbreak;\n\tdefault:\n\t\t/*do nothing*/\n\t\tbreak;\n\t}\n}\n\n/*@\n * Update band/CHannel/.. The values are dynamic but non-per-packet.\n */\nvoid odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value)\n{\n\t/* This init variable may be changed in run time. */\n\tswitch (cmn_info) {\n\tcase ODM_CMNINFO_LINK_IN_PROGRESS:\n\t\tdm->is_link_in_process = (boolean)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_ABILITY:\n\t\tdm->support_ability = (u64)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_RF_TYPE:\n\t\tdm->rf_type = (u8)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_WIFI_DIRECT:\n\t\tdm->is_wifi_direct = (boolean)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_WIFI_DISPLAY:\n\t\tdm->is_wifi_display = (boolean)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_LINK:\n\t\tdm->is_linked = (boolean)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_CMW500LINK:\n\t\tdm->iot_table.is_linked_cmw500 = (boolean)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_STATION_STATE:\n\t\tdm->bsta_state = (boolean)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_RSSI_MIN:\n\t\tdm->rssi_min = (u8)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_RSSI_MIN_BY_PATH:\n\t\tdm->rssi_min_by_path = (u8)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_DBG_COMP:\n\t\tdm->debug_components = (u64)value;\n\t\tbreak;\n\n#ifdef ODM_CONFIG_BT_COEXIST\n\t/* The following is for BT HS mode and BT coexist mechanism. */\n\tcase ODM_CMNINFO_BT_ENABLED:\n\t\tdm->bt_info_table.is_bt_enabled = (boolean)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_BT_HS_CONNECT_PROCESS:\n\t\tdm->bt_info_table.is_bt_connect_process = (boolean)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_BT_HS_RSSI:\n\t\tdm->bt_info_table.bt_hs_rssi = (u8)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_BT_OPERATION:\n\t\tdm->bt_info_table.is_bt_hs_operation = (boolean)value;\n\t\tbreak;\n\n\tcase ODM_CMNINFO_BT_LIMITED_DIG:\n\t\tdm->bt_info_table.is_bt_limited_dig = (boolean)value;\n\t\tbreak;\n#endif\n\n\tcase ODM_CMNINFO_AP_TOTAL_NUM:\n\t\tdm->ap_total_num = (u8)value;\n\t\tbreak;\n\n#ifdef CONFIG_PHYDM_DFS_MASTER\n\tcase ODM_CMNINFO_DFS_REGION_DOMAIN:\n\t\tdm->dfs_region_domain = (u8)value;\n\t\tbreak;\n#endif\n\n\tcase ODM_CMNINFO_BT_CONTINUOUS_TURN:\n\t\tdm->is_bt_continuous_turn = (boolean)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_IS_DOWNLOAD_FW:\n\t\tdm->is_download_fw = (boolean)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_PHYDM_PATCH_ID:\n\t\tdm->iot_table.phydm_patch_id = (u32)value;\n\t\tbreak;\n\tcase ODM_CMNINFO_RRSR_VAL:\n\t\tdm->dm_ra_table.rrsr_val_init = (u32)value;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nu32 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type)\n{\n\tstruct phydm_fa_struct *fa_t = &dm->false_alm_cnt;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct ccx_info *ccx_info = &dm->dm_ccx_info;\n\n\tswitch (info_type) {\n\t/*@=== [FA Relative] ===========================================*/\n\tcase PHYDM_INFO_FA_OFDM:\n\t\treturn fa_t->cnt_ofdm_fail;\n\n\tcase PHYDM_INFO_FA_CCK:\n\t\treturn fa_t->cnt_cck_fail;\n\n\tcase PHYDM_INFO_FA_TOTAL:\n\t\treturn fa_t->cnt_all;\n\n\tcase PHYDM_INFO_CCA_OFDM:\n\t\treturn fa_t->cnt_ofdm_cca;\n\n\tcase PHYDM_INFO_CCA_CCK:\n\t\treturn fa_t->cnt_cck_cca;\n\n\tcase PHYDM_INFO_CCA_ALL:\n\t\treturn fa_t->cnt_cca_all;\n\n\tcase PHYDM_INFO_CRC32_OK_VHT:\n\t\treturn fa_t->cnt_vht_crc32_ok;\n\n\tcase PHYDM_INFO_CRC32_OK_HT:\n\t\treturn fa_t->cnt_ht_crc32_ok;\n\n\tcase PHYDM_INFO_CRC32_OK_LEGACY:\n\t\treturn fa_t->cnt_ofdm_crc32_ok;\n\n\tcase PHYDM_INFO_CRC32_OK_CCK:\n\t\treturn fa_t->cnt_cck_crc32_ok;\n\n\tcase PHYDM_INFO_CRC32_ERROR_VHT:\n\t\treturn fa_t->cnt_vht_crc32_error;\n\n\tcase PHYDM_INFO_CRC32_ERROR_HT:\n\t\treturn fa_t->cnt_ht_crc32_error;\n\n\tcase PHYDM_INFO_CRC32_ERROR_LEGACY:\n\t\treturn fa_t->cnt_ofdm_crc32_error;\n\n\tcase PHYDM_INFO_CRC32_ERROR_CCK:\n\t\treturn fa_t->cnt_cck_crc32_error;\n\n\tcase PHYDM_INFO_EDCCA_FLAG:\n\t\treturn fa_t->edcca_flag;\n\n\tcase PHYDM_INFO_OFDM_ENABLE:\n\t\treturn fa_t->ofdm_block_enable;\n\n\tcase PHYDM_INFO_CCK_ENABLE:\n\t\treturn fa_t->cck_block_enable;\n\n\tcase PHYDM_INFO_DBG_PORT_0:\n\t\treturn fa_t->dbg_port0;\n\n\tcase PHYDM_INFO_CRC32_OK_HT_AGG:\n\t\treturn fa_t->cnt_ht_crc32_ok_agg;\n\n\tcase PHYDM_INFO_CRC32_ERROR_HT_AGG:\n\t\treturn fa_t->cnt_ht_crc32_error_agg;\n\n\t/*@=== [DIG] ================================================*/\n\n\tcase PHYDM_INFO_CURR_IGI:\n\t\treturn dig_t->cur_ig_value;\n\n\t/*@=== [RSSI] ===============================================*/\n\tcase PHYDM_INFO_RSSI_MIN:\n\t\treturn (u32)dm->rssi_min;\n\n\tcase PHYDM_INFO_RSSI_MAX:\n\t\treturn (u32)dm->rssi_max;\n\n\tcase PHYDM_INFO_CLM_RATIO:\n\t\treturn (u32)ccx_info->clm_ratio;\n\tcase PHYDM_INFO_NHM_RATIO:\n\t\treturn (u32)ccx_info->nhm_ratio;\n\tdefault:\n\t\treturn 0xffffffff;\n\t}\n}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid odm_init_all_work_items(struct dm_struct *dm)\n{\n\tvoid *adapter = dm->adapter;\n#if USE_WORKITEM\n\n#ifdef CONFIG_ADAPTIVE_SOML\n\todm_initialize_work_item(dm,\n\t\t\t\t &dm->dm_soml_table.phydm_adaptive_soml_workitem,\n\t\t\t\t (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback,\n\t\t\t\t (void *)adapter,\n\t\t\t\t \"AdaptiveSOMLWorkitem\");\n#endif\n\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\todm_initialize_work_item(dm,\n\t\t\t\t &dm->phydm_evm_antdiv_workitem,\n\t\t\t\t (RT_WORKITEM_CALL_BACK)phydm_evm_antdiv_workitem_callback,\n\t\t\t\t (void *)adapter,\n\t\t\t\t \"EvmAntdivWorkitem\");\n#endif\n\n#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\todm_initialize_work_item(dm,\n\t\t\t\t &dm->dm_swat_table.phydm_sw_antenna_switch_workitem,\n\t\t\t\t (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,\n\t\t\t\t (void *)adapter,\n\t\t\t\t \"AntennaSwitchWorkitem\");\n#endif\n#if (defined(CONFIG_HL_SMART_ANTENNA))\n\todm_initialize_work_item(dm,\n\t\t\t\t &dm->dm_sat_table.hl_smart_antenna_workitem,\n\t\t\t\t (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,\n\t\t\t\t (void *)adapter,\n\t\t\t\t \"hl_smart_ant_workitem\");\n\n\todm_initialize_work_item(dm,\n\t\t\t\t &dm->dm_sat_table.hl_smart_antenna_decision_workitem,\n\t\t\t\t (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,\n\t\t\t\t (void *)adapter,\n\t\t\t\t \"hl_smart_ant_decision_workitem\");\n#endif\n\n\todm_initialize_work_item(\n\t\tdm,\n\t\t&dm->ra_rpt_workitem,\n\t\t(RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback,\n\t\t(void *)adapter,\n\t\t\"ra_rpt_workitem\");\n\n#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))\n\todm_initialize_work_item(\n\t\tdm,\n\t\t&dm->fast_ant_training_workitem,\n\t\t(RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,\n\t\t(void *)adapter,\n\t\t\"fast_ant_training_workitem\");\n#endif\n\n#endif /*#if USE_WORKITEM*/\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\todm_initialize_work_item(\n\t\tdm,\n\t\t&dm->beamforming_info.txbf_info.txbf_enter_work_item,\n\t\t(RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,\n\t\t(void *)adapter,\n\t\t\"txbf_enter_work_item\");\n\n\todm_initialize_work_item(\n\t\tdm,\n\t\t&dm->beamforming_info.txbf_info.txbf_leave_work_item,\n\t\t(RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,\n\t\t(void *)adapter,\n\t\t\"txbf_leave_work_item\");\n\n\todm_initialize_work_item(\n\t\tdm,\n\t\t&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item,\n\t\t(RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,\n\t\t(void *)adapter,\n\t\t\"txbf_fw_ndpa_work_item\");\n\n\todm_initialize_work_item(\n\t\tdm,\n\t\t&dm->beamforming_info.txbf_info.txbf_clk_work_item,\n\t\t(RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,\n\t\t(void *)adapter,\n\t\t\"txbf_clk_work_item\");\n\n\todm_initialize_work_item(\n\t\tdm,\n\t\t&dm->beamforming_info.txbf_info.txbf_rate_work_item,\n\t\t(RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,\n\t\t(void *)adapter,\n\t\t\"txbf_rate_work_item\");\n\n\todm_initialize_work_item(\n\t\tdm,\n\t\t&dm->beamforming_info.txbf_info.txbf_status_work_item,\n\t\t(RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,\n\t\t(void *)adapter,\n\t\t\"txbf_status_work_item\");\n\n\todm_initialize_work_item(\n\t\tdm,\n\t\t&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item,\n\t\t(RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,\n\t\t(void *)adapter,\n\t\t\"txbf_reset_tx_path_work_item\");\n\n\todm_initialize_work_item(\n\t\tdm,\n\t\t&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item,\n\t\t(RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,\n\t\t(void *)adapter,\n\t\t\"txbf_get_tx_rate_work_item\");\n#endif\n\n#if (PHYDM_LA_MODE_SUPPORT == 1)\n\todm_initialize_work_item(\n\t\tdm,\n\t\t&dm->adcsmp.adc_smp_work_item,\n\t\t(RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,\n\t\t(void *)adapter,\n\t\t\"adc_smp_work_item\");\n\n\todm_initialize_work_item(\n\t\tdm,\n\t\t&dm->adcsmp.adc_smp_work_item_1,\n\t\t(RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,\n\t\t(void *)adapter,\n\t\t\"adc_smp_work_item_1\");\n#endif\n}\n\nvoid odm_free_all_work_items(struct dm_struct *dm)\n{\n#if USE_WORKITEM\n\n#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\todm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem);\n#endif\n\n#ifdef CONFIG_ADAPTIVE_SOML\n\todm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem);\n#endif\n\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\todm_free_work_item(&dm->phydm_evm_antdiv_workitem);\n#endif\n\n#if (defined(CONFIG_HL_SMART_ANTENNA))\n\todm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem);\n\todm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem);\n#endif\n\n#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))\n\todm_free_work_item(&dm->fast_ant_training_workitem);\n#endif\n\todm_free_work_item(&dm->ra_rpt_workitem);\n/*odm_free_work_item((&dm->sbdcnt_workitem));*/\n#endif\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\todm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item));\n\todm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item));\n\todm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));\n\todm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item));\n\todm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item));\n\todm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item));\n\todm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));\n\todm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));\n#endif\n\n#if (PHYDM_LA_MODE_SUPPORT == 1)\n\todm_free_work_item((&dm->adcsmp.adc_smp_work_item));\n\todm_free_work_item((&dm->adcsmp.adc_smp_work_item_1));\n#endif\n}\n#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/\n\nvoid odm_init_all_timers(struct dm_struct *dm)\n{\n#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))\n\todm_ant_div_timers(dm, INIT_ANTDIV_TIMMER);\n#endif\n#if (defined(PHYDM_TDMA_DIG_SUPPORT))\n#ifdef IS_USE_NEW_TDMA\n\tphydm_tdma_dig_timers(dm, INIT_TDMA_DIG_TIMMER);\n#endif\n#endif\n#ifdef CONFIG_ADAPTIVE_SOML\n\tphydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER);\n#endif\n#ifdef PHYDM_LNA_SAT_CHK_SUPPORT\n#ifdef PHYDM_LNA_SAT_CHK_TYPE1\n\tphydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER);\n#endif\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\todm_initialize_timer(dm, &dm->sbdcnt_timer,\n\t\t\t     (void *)phydm_sbd_callback, NULL, \"SbdTimer\");\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\todm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,\n\t\t\t     (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL,\n\t\t\t     \"txbf_fw_ndpa_timer\");\n#endif\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\todm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer,\n\t\t\t     (void *)beamforming_sw_timer_callback, NULL,\n\t\t\t     \"beamforming_timer\");\n#endif\n#endif\n}\n\nvoid odm_cancel_all_timers(struct dm_struct *dm)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t/* @2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/\n\tif (dm->adapter == NULL)\n\t\treturn;\n#endif\n\n#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))\n\todm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER);\n#endif\n#ifdef PHYDM_TDMA_DIG_SUPPORT\n#ifdef IS_USE_NEW_TDMA\n\tphydm_tdma_dig_timers(dm, CANCEL_TDMA_DIG_TIMMER);\n#endif\n#endif\n#ifdef CONFIG_ADAPTIVE_SOML\n\tphydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER);\n#endif\n#ifdef PHYDM_LNA_SAT_CHK_SUPPORT\n#ifdef PHYDM_LNA_SAT_CHK_TYPE1\n\tphydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER);\n#endif\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\todm_cancel_timer(dm, &dm->sbdcnt_timer);\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\todm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);\n#endif\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\todm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer);\n#endif\n#endif\n}\n\nvoid odm_release_all_timers(struct dm_struct *dm)\n{\n#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))\n\todm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER);\n#endif\n#ifdef PHYDM_TDMA_DIG_SUPPORT\n#ifdef IS_USE_NEW_TDMA\n\tphydm_tdma_dig_timers(dm, RELEASE_TDMA_DIG_TIMMER);\n#endif\n#endif\n#ifdef CONFIG_ADAPTIVE_SOML\n\tphydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER);\n#endif\n#ifdef PHYDM_LNA_SAT_CHK_SUPPORT\n#ifdef PHYDM_LNA_SAT_CHK_TYPE1\n\tphydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER);\n#endif\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\todm_release_timer(dm, &dm->sbdcnt_timer);\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\todm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);\n#endif\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\todm_release_timer(dm, &dm->beamforming_info.beamforming_timer);\n#endif\n#endif\n}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\nvoid odm_init_all_threads(\n\tstruct dm_struct *dm)\n{\n#ifdef TPT_THREAD\n\tk_tpt_task_init(dm->priv);\n#endif\n}\n\nvoid odm_stop_all_threads(\n\tstruct dm_struct *dm)\n{\n#ifdef TPT_THREAD\n\tk_tpt_task_stop(dm->priv);\n#endif\n}\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n/* @Justin: According to the current RRSI to adjust Response Frame TX power,\n * 2012/11/05\n */\nvoid odm_dtc(struct dm_struct *dm)\n{\n#ifdef CONFIG_DM_RESP_TXAGC\n/* RSSI higher than this value, start to decade TX power */\n#define DTC_BASE 35\n\n/* RSSI lower than this value, start to increase TX power */\n#define DTC_DWN_BASE (DTC_BASE - 5)\n\n\t/* RSSI vs TX power step mapping: decade TX power */\n\tstatic const u8 dtc_table_down[] = {\n\t\tDTC_BASE,\n\t\t(DTC_BASE + 5),\n\t\t(DTC_BASE + 10),\n\t\t(DTC_BASE + 15),\n\t\t(DTC_BASE + 20),\n\t\t(DTC_BASE + 25)};\n\n\t/* RSSI vs TX power step mapping: increase TX power */\n\tstatic const u8 dtc_table_up[] = {\n\t\tDTC_DWN_BASE,\n\t\t(DTC_DWN_BASE - 5),\n\t\t(DTC_DWN_BASE - 10),\n\t\t(DTC_DWN_BASE - 15),\n\t\t(DTC_DWN_BASE - 15),\n\t\t(DTC_DWN_BASE - 20),\n\t\t(DTC_DWN_BASE - 20),\n\t\t(DTC_DWN_BASE - 25),\n\t\t(DTC_DWN_BASE - 25),\n\t\t(DTC_DWN_BASE - 30),\n\t\t(DTC_DWN_BASE - 35)};\n\n\tu8 i;\n\tu8 dtc_steps = 0;\n\tu8 sign;\n\tu8 resp_txagc = 0;\n\n#if 0\n\t/* @As DIG is disabled, DTC is also disable */\n\tif (!(dm->support_ability & ODM_XXXXXX))\n\t\treturn;\n#endif\n\n\tif (dm->rssi_min > DTC_BASE) {\n\t\t/* need to decade the CTS TX power */\n\t\tsign = 1;\n\t\tfor (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {\n\t\t\tif (dtc_table_down[i] >= dm->rssi_min || dtc_steps >= 6)\n\t\t\t\tbreak;\n\t\t\telse\n\t\t\t\tdtc_steps++;\n\t\t}\n\t}\n#if 0\n\telse if (dm->rssi_min > DTC_DWN_BASE) {\n\t\t/* needs to increase the CTS TX power */\n\t\tsign = 0;\n\t\tdtc_steps = 1;\n\t\tfor (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {\n\t\t\tif (dtc_table_up[i] <= dm->rssi_min || dtc_steps >= 10)\n\t\t\t\tbreak;\n\t\t\telse\n\t\t\t\tdtc_steps++;\n\t\t}\n\t}\n#endif\n\telse {\n\t\tsign = 0;\n\t\tdtc_steps = 0;\n\t}\n\n\tresp_txagc = dtc_steps | (sign << 4);\n\tresp_txagc = resp_txagc | (resp_txagc << 5);\n\todm_write_1byte(dm, 0x06d9, resp_txagc);\n\n\tPHYDM_DBG(dm, ODM_COMP_PWR_TRAIN,\n\t\t  \"%s rssi_min:%u, set RESP_TXAGC to %s %u\\n\", __func__,\n\t\t  dm->rssi_min, sign ? \"minus\" : \"plus\", dtc_steps);\n#endif /* @CONFIG_RESP_TXAGC_ADJUST */\n}\n\n#endif /* @#if (DM_ODM_SUPPORT_TYPE == ODM_CE) */\n\n/*@<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/\nvoid phydm_dc_cancellation(struct dm_struct *dm)\n{\n#ifdef PHYDM_DC_CANCELLATION\n\tu32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0};\n\tu32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0};\n\tu32 reg_value32[PHYDM_MAX_RF_PATH] = {0};\n\tu8 path = RF_PATH_A;\n\tu8 set_result;\n\n\tif (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT))\n\t\treturn;\n\tif ((dm->support_ic_type & ODM_RTL8188F) &&\n\t    dm->cut_version < ODM_CUT_D)\n\t\treturn;\n\tif ((dm->support_ic_type & ODM_RTL8192F) &&\n\t    dm->cut_version == ODM_CUT_A)\n\t\treturn;\n\n\tPHYDM_DBG(dm, ODM_COMP_API, \"%s ======>\\n\", __func__);\n\n\t/*@DC_Estimation (only for 2x2 ic now) */\n\n\tfor (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) {\n\t\tif (path > RF_PATH_A &&\n\t\t    dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8188F |\n\t\t\t\t\t  ODM_RTL8710B | ODM_RTL8723D |\n\t\t\t\t\t  ODM_RTL8721D))\n\t\t\tbreak;\n\t\telse if (path > RF_PATH_B &&\n\t\t\t dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8192F))\n\t\t\tbreak;\n\t\tif (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {\n\t\t\tPHYDM_DBG(dm, ODM_COMP_API, \"STOP_TRX_FAIL\\n\");\n\t\t\treturn;\n\t\t}\n\t\todm_write_dig(dm, 0x7e);\n\t\t/*@Disable LNA*/\n\t\tif (dm->support_ic_type & ODM_RTL8821C)\n\t\t\thalrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);\n\t\t/*Turn off 3-wire*/\n\t\tphydm_stop_3_wire(dm, PHYDM_SET);\n\t\tif (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B |\n\t\t\tODM_RTL8723D)) {\n\t\t\t/*set debug port to 0x235*/\n\t\t\tif (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {\n\t\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t\t  \"Set Debug port Fail\\n\");\n\t\t\t\treturn;\n\t\t\t}\n\t\t} else if (dm->support_ic_type & ODM_RTL8721D) {\n\t\t\t/*set debug port to 0x200*/\n\t\t\tif (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) {\n\t\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t\t  \"Set Debug port Fail\\n\");\n\t\t\t\treturn;\n\t\t\t}\n\t\t} else if (dm->support_ic_type & ODM_RTL8821C) {\n\t\t\tif (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {\n\t\t\t\t/*set debug port to 0x200*/\n\t\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t\t  \"Set Debug port Fail\\n\");\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tphydm_bb_dbg_port_header_sel(dm, 0x0);\n\t\t} else if (dm->support_ic_type & ODM_RTL8822B) {\n\t\t\tif (path == RF_PATH_A &&\n\t\t\t    !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {\n\t\t\t\t/*set debug port to 0x200*/\n\t\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t\t  \"Set Debug port Fail\\n\");\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tif (path == RF_PATH_B &&\n\t\t\t    !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x202)) {\n\t\t\t\t/*set debug port to 0x200*/\n\t\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t\t  \"Set Debug port Fail\\n\");\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tphydm_bb_dbg_port_header_sel(dm, 0x0);\n\t\t} else if (dm->support_ic_type & ODM_RTL8192F) {\n\t\t\tif (path == RF_PATH_A &&\n\t\t\t    !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {\n\t\t\t\t/*set debug port to 0x235*/\n\t\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t\t  \"Set Debug port Fail\\n\");\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tif (path == RF_PATH_B &&\n\t\t\t    !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x23d)) {\n\t\t\t\t/*set debug port to 0x23d*/\n\t\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t\t  \"Set Debug port Fail\\n\");\n\t\t\t\treturn;\n\t\t\t}\n\t\t}\n\n\t\t/*@disable CCK DCNF*/\n\t\todm_set_bb_reg(dm, R_0xa78, MASKBYTE1, 0x0);\n\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"DC cancellation Begin!!!\\n\");\n\n\t\tphydm_stop_ck320(dm, true); /*stop ck320*/\n\n\t\t/* the same debug port both for path-a and path-b*/\n\t\treg_value32[path] = phydm_get_bb_dbg_port_val(dm);\n\n\t\tphydm_stop_ck320(dm, false); /*start ck320*/\n\n\t\tphydm_release_bb_dbg_port(dm);\n\t\t/* @Turn on 3-wire*/\n\t\tphydm_stop_3_wire(dm, PHYDM_REVERT);\n\t\t/* @Enable LNA*/\n\t\tif (dm->support_ic_type & ODM_RTL8821C)\n\t\t\thalrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);\n\n\t\todm_write_dig(dm, 0x20);\n\n\t\tset_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);\n\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"DC cancellation OK!!!\\n\");\n\t}\n\n\t/*@DC_Cancellation*/\n\t/*@DC compensation to CCK data path*/\n\todm_set_bb_reg(dm, R_0xa9c, BIT(20), 0x1);\n\tif (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B |\n\t\tODM_RTL8723D)) {\n\t\toffset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;\n\t\toffset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;\n\n\t\t/*@Before filling into registers,\n\t\t *offset should be multiplexed (-1)\n\t\t */\n\t\toffset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?\n\t\t\t\t  (0x400 - offset_i_hex[0]) :\n\t\t\t\t  (0x1ff - offset_i_hex[0]);\n\t\toffset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?\n\t\t\t\t  (0x400 - offset_q_hex[0]) :\n\t\t\t\t  (0x1ff - offset_q_hex[0]);\n\n\t\todm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);\n\t\todm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);\n\t} else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {\n\t\t/* Path-a */\n\t\toffset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10;\n\t\toffset_q_hex[0] = reg_value32[0] & 0x3ff;\n\n\t\t/*@Before filling into registers,\n\t\t *offset should be multiplexed (-1)\n\t\t */\n\t\toffset_i_hex[0] = 0x400 - offset_i_hex[0];\n\t\toffset_q_hex[0] = 0x400 - offset_q_hex[0];\n\n\t\todm_set_bb_reg(dm, R_0xc10, 0x3c000000,\n\t\t\t       (0x3c0 & offset_i_hex[0]) >> 6);\n\t\todm_set_bb_reg(dm, R_0xc10, 0xfc00, 0x3f & offset_i_hex[0]);\n\t\todm_set_bb_reg(dm, R_0xc14, 0x3c000000,\n\t\t\t       (0x3c0 & offset_q_hex[0]) >> 6);\n\t\todm_set_bb_reg(dm, R_0xc14, 0xfc00, 0x3f & offset_q_hex[0]);\n\n\t\t/* Path-b */\n\t\tif (dm->rf_type > RF_1T1R) {\n\t\t\toffset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10;\n\t\t\toffset_q_hex[1] = reg_value32[1] & 0x3ff;\n\n\t\t\t/*@Before filling into registers,\n\t\t\t *offset should be multiplexed (-1)\n\t\t\t */\n\t\t\toffset_i_hex[1] = 0x400 - offset_i_hex[1];\n\t\t\toffset_q_hex[1] = 0x400 - offset_q_hex[1];\n\n\t\t\todm_set_bb_reg(dm, R_0xe10, 0x3c000000,\n\t\t\t\t       (0x3c0 & offset_i_hex[1]) >> 6);\n\t\t\todm_set_bb_reg(dm, R_0xe10, 0xfc00,\n\t\t\t\t       0x3f & offset_i_hex[1]);\n\t\t\todm_set_bb_reg(dm, R_0xe14, 0x3c000000,\n\t\t\t\t       (0x3c0 & offset_q_hex[1]) >> 6);\n\t\t\todm_set_bb_reg(dm, R_0xe14, 0xfc00,\n\t\t\t\t       0x3f & offset_q_hex[1]);\n\t\t}\n\t} else if (dm->support_ic_type & (ODM_RTL8192F)) {\n\t\t/* Path-a I:df4[27:18],Q:df4[17:8]*/\n\t\toffset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;\n\t\toffset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;\n\n\t\t/*@Before filling into registers,\n\t\t *offset should be multiplexed (-1)\n\t\t */\n\t\toffset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?\n\t\t\t\t  (0x400 - offset_i_hex[0]) :\n\t\t\t\t  (0xff - offset_i_hex[0]);\n\t\toffset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?\n\t\t\t\t  (0x400 - offset_q_hex[0]) :\n\t\t\t\t  (0xff - offset_q_hex[0]);\n\t\t/*Path-a I:c10[7:0],Q:c10[15:8]*/\n\t\todm_set_bb_reg(dm, R_0xc10, 0xff, offset_i_hex[0]);\n\t\todm_set_bb_reg(dm, R_0xc10, 0xff00, offset_q_hex[0]);\n\n\t\t/* Path-b */\n\t\tif (dm->rf_type > RF_1T1R) {\n\t\t\t/* @I:df4[27:18],Q:df4[17:8]*/\n\t\t\toffset_i_hex[1] = (reg_value32[1] & 0xffc0000) >> 18;\n\t\t\toffset_q_hex[1] = (reg_value32[1] & 0x3ff00) >> 8;\n\n\t\t\t/*@Before filling into registers,\n\t\t\t *offset should be multiplexed (-1)\n\t\t\t */\n\t\t\toffset_i_hex[1] = (offset_i_hex[1] >= 0x200) ?\n\t\t\t\t\t  (0x400 - offset_i_hex[1]) :\n\t\t\t\t\t  (0xff - offset_i_hex[1]);\n\t\t\toffset_q_hex[1] = (offset_q_hex[1] >= 0x200) ?\n\t\t\t\t\t  (0x400 - offset_q_hex[1]) :\n\t\t\t\t\t  (0xff - offset_q_hex[1]);\n\t\t\t/*Path-b I:c18[7:0],Q:c18[15:8]*/\n\t\t\todm_set_bb_reg(dm, R_0xc18, 0xff, offset_i_hex[1]);\n\t\t\todm_set_bb_reg(dm, R_0xc18, 0xff00, offset_q_hex[1]);\n\t\t}\n\t} else if (dm->support_ic_type & (ODM_RTL8721D)) {\n\t /*judy modified 20180517*/\n\t\toffset_i_hex[0] = (reg_value32[0] & 0xff80000) >> 19;\n\t\toffset_q_hex[0] = (reg_value32[0] & 0x3fe00) >> 9;\n\n\t\t/*@Before filling into registers,\n\t\t *offset should be multiplexed (-1)\n\t\t */\n\t\toffset_i_hex[0] = 0x200 - offset_i_hex[0];\n\t\toffset_q_hex[0] = 0x200 - offset_q_hex[0];\n\n\t\todm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);\n\t\todm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);\n\t}\n#endif\n}\n\nvoid phydm_receiver_blocking(void *dm_void)\n{\n#ifdef CONFIG_RECEIVER_BLOCKING\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 chnl = *dm->channel;\n\tu8 bw = *dm->band_width;\n\tu32 bb_regf0 = odm_get_bb_reg(dm, R_0xf0, 0xf000);\n\n\tif (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT) ||\n\t    !(dm->support_ability & ODM_BB_ADAPTIVITY))\n\t\treturn;\n\n\tif ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 < 8) ||\n\t    dm->support_ic_type & ODM_RTL8192E) {\n\t    /*@8188E_T version*/\n\t\tif (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)\n\t\t\tgoto end;\n\n\t\tif (bw == CHANNEL_WIDTH_20 && chnl == 1) {\n\t\t\tphydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2410,\n\t\t\t\t\t  PHYDM_DONT_CARE);\n\t\t\tdm->is_rx_blocking_en = true;\n\t\t} else if ((bw == CHANNEL_WIDTH_20) && (chnl == 13)) {\n\t\t\tphydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,\n\t\t\t\t\t  PHYDM_DONT_CARE);\n\t\t\tdm->is_rx_blocking_en = true;\n\t\t} else if (dm->is_rx_blocking_en && chnl != 1 && chnl != 13) {\n\t\t\tphydm_nbi_enable(dm, FUNC_DISABLE);\n\t\t\todm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);\n\t\t\tdm->is_rx_blocking_en = false;\n\t\t}\n\t\treturn;\n\t} else if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 >= 8)) {\n\t/*@8188E_S version*/\n\t\tif (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)\n\t\t\tgoto end;\n\n\t\tif (bw == CHANNEL_WIDTH_20 && chnl == 13) {\n\t\t\tphydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,\n\t\t\t\t\t  PHYDM_DONT_CARE);\n\t\t\tdm->is_rx_blocking_en = true;\n\t\t} else if (dm->is_rx_blocking_en && chnl != 13) {\n\t\t\tphydm_nbi_enable(dm, FUNC_DISABLE);\n\t\t\todm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);\n\t\t\tdm->is_rx_blocking_en = false;\n\t\t}\n\t\treturn;\n\t}\n\nend:\n\tif (dm->is_rx_blocking_en) {\n\t\tphydm_nbi_enable(dm, FUNC_DISABLE);\n\t\todm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);\n\t\tdm->is_rx_blocking_en = false;\n\t}\n#endif\n}\n"
  },
  {
    "path": "hal/phydm/phydm.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALDMOUTSRC_H__\n#define __HALDMOUTSRC_H__\n\n/*@============================================================*/\n/*@include files*/\n/*@============================================================*/\n/*PHYDM header*/\n#include \"phydm_pre_define.h\"\n#include \"phydm_features.h\"\n#include \"phydm_dig.h\"\n#ifdef CONFIG_PATH_DIVERSITY\n#include \"phydm_pathdiv.h\"\n#endif\n#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n#include \"phydm_antdiv.h\"\n#endif\n\n#include \"phydm_soml.h\"\n\n#ifdef CONFIG_SMART_ANTENNA\n#include \"phydm_smt_ant.h\"\n#endif\n#ifdef CONFIG_ANT_DETECTION\n#include \"phydm_antdect.h\"\n#endif\n#include \"phydm_rainfo.h\"\n#ifdef CONFIG_DYNAMIC_TX_TWR\n#include \"phydm_dynamictxpower.h\"\n#endif\n#include \"phydm_cfotracking.h\"\n#include \"phydm_adaptivity.h\"\n#include \"phydm_dfs.h\"\n#include \"phydm_ccx.h\"\n#include \"txbf/phydm_hal_txbf_api.h\"\n#if (PHYDM_LA_MODE_SUPPORT)\n#include \"phydm_adc_sampling.h\"\n#endif\n#ifdef CONFIG_PSD_TOOL\n#include \"phydm_psd.h\"\n#endif\n#ifdef PHYDM_PRIMARY_CCA\n#include \"phydm_primary_cca.h\"\n#endif\n#include \"phydm_cck_pd.h\"\n#include \"phydm_rssi_monitor.h\"\n#ifdef PHYDM_AUTO_DEGBUG\n#include \"phydm_auto_dbg.h\"\n#endif\n#include \"phydm_math_lib.h\"\n#include \"phydm_noisemonitor.h\"\n#include \"phydm_api.h\"\n#ifdef PHYDM_POWER_TRAINING_SUPPORT\n#include \"phydm_pow_train.h\"\n#endif\n#ifdef PHYDM_LNA_SAT_CHK_SUPPORT\n#include \"phydm_lna_sat.h\"\n#endif\n#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT\n#include \"phydm_pmac_tx_setting.h\"\n#endif\n#ifdef PHYDM_MP_SUPPORT\n#include \"phydm_mp.h\"\n#endif\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\t#include \"phydm_beamforming.h\"\n#endif\n\n#ifdef CONFIG_DIRECTIONAL_BF\n#include \"phydm_direct_bf.h\"\n#endif\n\n#include \"phydm_regtable.h\"\n\n/*@HALRF header*/\n#include \"halrf/halrf_iqk.h\"\n#include \"halrf/halrf_dpk.h\"\n#include \"halrf/halrf.h\"\n#include \"halrf/halrf_powertracking.h\"\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\t#include \"halrf/halphyrf_ap.h\"\n#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))\n\t#include \"halrf/halphyrf_ce.h\"\n#elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\n\t#include \"halrf/halphyrf_win.h\"\n#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))\n\t#include \"halrf/halphyrf_iot.h\"\n#endif\n\nextern const u16\tphy_rate_table[84];\n\n/*@============================================================*/\n/*@Definition */\n/*@============================================================*/\n\n/* Traffic load decision */\n#define TRAFFIC_NO_TP\t\t\t0\n#define\tTRAFFIC_ULTRA_LOW\t\t1\n#define\tTRAFFIC_LOW\t\t\t2\n#define\tTRAFFIC_MID\t\t\t3\n#define\tTRAFFIC_HIGH\t\t\t4\n\n#define\tNONE\t\t\t\t0\n\n#if defined(DM_ODM_CE_MAC80211)\n#define MAX_2(x, y)\t\t\t\t\t\\\n\t__max2(typeof(x), typeof(y),\t\t\t\\\n\t      x, y)\n#define __max2(t1, t2, x, y) ({\t\t\\\n\tt1 m80211_max1 = (x);\t\t\t\t\t\\\n\tt2 m80211_max2 = (y);\t\t\t\t\t\\\n\tm80211_max1 > m80211_max2 ? m80211_max1 : m80211_max2; })\n\n#define MIN_2(x, y)\t\t\t\t\t\\\n\t__min2(typeof(x), typeof(y),\t\t\t\\\n\t      x, y)\n#define __min2(t1, t2, x, y) ({\t\t\\\n\tt1 m80211_min1 = (x);\t\t\t\t\t\\\n\tt2 m80211_min2 = (y);\t\t\t\t\t\\\n\tm80211_min1 < m80211_min2 ? m80211_min1 : m80211_min2; })\n\n#define DIFF_2(x, y)\t\t\t\t\t\\\n\t__diff2(typeof(x), typeof(y),\t\t\t\\\n\t      x, y)\n#define __diff2(t1, t2, x, y) ({\t\t\\\n\tt1 __d1 = (x);\t\t\t\t\t\\\n\tt2 __d2 = (y);\t\t\t\t\t\\\n\t(__d1 >= __d2) ? (__d1 - __d2) : (__d2 - __d1); })\n#else\n#define MAX_2(_x_, _y_)\t(((_x_) > (_y_)) ? (_x_) : (_y_))\n#define MIN_2(_x_, _y_)\t(((_x_) < (_y_)) ? (_x_) : (_y_))\n#define DIFF_2(_x_, _y_)\t((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_))\n#endif\n\n#define IS_GREATER(_x_, _y_)\t(((_x_) >= (_y_)) ? true : false)\n#define IS_LESS(_x_, _y_)\t(((_x_) < (_y_)) ? true : false)\n\n#if defined(DM_ODM_CE_MAC80211)\n#define BYTE_DUPLICATE_2_DWORD(B0) ({\t\\\n\tu32 __b_dup = (B0);\\\n\t(((__b_dup) << 24) | ((__b_dup) << 16) | ((__b_dup) << 8) | (__b_dup));\\\n\t})\n#else\n#define BYTE_DUPLICATE_2_DWORD(B0)\t\\\n\t(((B0) << 24) | ((B0) << 16) | ((B0) << 8) | (B0))\n#endif\n#define BYTE_2_DWORD(B3, B2, B1, B0)\t\\\n\t(((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0))\n#define BIT_2_BYTE(B3, B2, B1, B0)\t\\\n\t(((B3) << 3) | ((B2) << 2) | ((B1) << 1) | (B0))\n\n/*@For cmn sta info*/\n#if defined(DM_ODM_CE_MAC80211)\n#define is_sta_active(sta) ({\t\\\n\tstruct cmn_sta_info *__sta = (sta);\t\\\n\t((__sta) && (__sta->dm_ctrl & STA_DM_CTRL_ACTIVE));\t\\\n\t})\n\n#define IS_FUNC_EN(name) ({\t\\\n\tu8 *__is_func_name = (name);\t\\\n\t(__is_func_name) && (*__is_func_name);\t\\\n\t})\n#else\n#define is_sta_active(sta)\t((sta) && (sta->dm_ctrl & STA_DM_CTRL_ACTIVE))\n\n#define IS_FUNC_EN(name)\t((name) && (*name))\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t#define PHYDM_WATCH_DOG_PERIOD\t1 /*second*/\n#else\n\t#define PHYDM_WATCH_DOG_PERIOD\t2 /*second*/\n#endif\n\n#define PHY_HIST_SIZE\t\t12\n\n/*@============================================================*/\n/*structure and define*/\n/*@============================================================*/\n\n#define\t\tdm_type_by_fw\t\t0\n#define\t\tdm_type_by_driver\t1\n\n#ifdef BB_RAM_SUPPORT\n\nstruct phydm_bb_ram_per_sta {\n\t/* @Reg0x1E84 for RAM I/O*/\n\tboolean\t\t\thw_igi_en;\n\tboolean\t\t\ttx_pwr_offset0_en;\n\tboolean\t\t\ttx_pwr_offset1_en;\n\t/* @ macid from 0 to 63, above 63 => mapping to 63*/\n\tu8\t\t\tmacid_addr;\n\t/* @hw_igi value for paths after packet Tx in a period of time*/\n\tu8\t\t\thw_igi;\n\t/* @tx_pwr_offset0 offset for Tx power index*/\n\ts8\t\t\ttx_pwr_offset0;\n\ts8\t\t\ttx_pwr_offset1;\n\n};\n\nstruct phydm_bb_ram_ctrl {\n\t/*@ For 98F/14B/22C/12F, each TxAGC step will be 0.25dB*/\n\tstruct phydm_bb_ram_per_sta pram_sta_ctrl[ODM_ASSOCIATE_ENTRY_NUM];\n\t/*------------ For table2 do not set power offset by macid --------*/\n\t/* For type == 2'b10, 0x1e70[22:16] = tx_pwr_offset_reg0, 0x1e70[23] = enable */\n\tboolean\t\t\ttx_pwr_offset_reg0_en;\n\tu8\t\t\ttx_pwr_offset_reg0;\n\t/* For type == 2'b11, 0x1e70[30:24] = tx_pwr_offset_reg1, 0x1e70[31] = enable */\n\tboolean\t\t\ttx_pwr_offset_reg1_en;\n\tu8\t\t\ttx_pwr_offset_reg1;\n};\n\n#endif\n\nstruct phydm_phystatus_statistic {\n\t/*@[CCK]*/\n\tu32\t\t\trssi_cck_sum;\n\tu32\t\t\trssi_cck_cnt;\n\tu32\t\t\trssi_beacon_sum;\n\tu32\t\t\trssi_beacon_cnt;\n\t/*@[OFDM]*/\n\tu32\t\t\trssi_ofdm_sum[RF_PATH_MEM_SIZE];\n\tu32\t\t\trssi_ofdm_cnt;\n\tu32\t\t\tevm_ofdm_sum;\n\tu32\t\t\tsnr_ofdm_sum[RF_PATH_MEM_SIZE];\n\tu16\t\t\tevm_ofdm_hist[PHY_HIST_SIZE];\n\tu16\t\t\tsnr_ofdm_hist[PHY_HIST_SIZE];\n\t/*@[1SS]*/\n\tu32\t\t\trssi_1ss_cnt;\n\tu32\t\t\trssi_1ss_sum[RF_PATH_MEM_SIZE];\n\tu32\t\t\tevm_1ss_sum;\n\tu32\t\t\tsnr_1ss_sum[RF_PATH_MEM_SIZE];\n\tu16\t\t\tevm_1ss_hist[PHY_HIST_SIZE];\n\tu16\t\t\tsnr_1ss_hist[PHY_HIST_SIZE];\n\t/*@[2SS]*/\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tu32\t\t\trssi_2ss_cnt;\n\tu32\t\t\trssi_2ss_sum[RF_PATH_MEM_SIZE];\n\tu32\t\t\tevm_2ss_sum[2];\n\tu32\t\t\tsnr_2ss_sum[RF_PATH_MEM_SIZE];\n\tu16\t\t\tevm_2ss_hist[2][PHY_HIST_SIZE];\n\tu16\t\t\tsnr_2ss_hist[2][PHY_HIST_SIZE];\n\t#endif\n\t/*@[3SS]*/\n\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\tu32\t\t\trssi_3ss_cnt;\n\tu32\t\t\trssi_3ss_sum[RF_PATH_MEM_SIZE];\n\tu32\t\t\tevm_3ss_sum[3];\n\tu32\t\t\tsnr_3ss_sum[RF_PATH_MEM_SIZE];\n\tu16\t\t\tevm_3ss_hist[3][PHY_HIST_SIZE];\n\tu16\t\t\tsnr_3ss_hist[3][PHY_HIST_SIZE];\n\t#endif\n\t/*@[4SS]*/\n\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\tu32\t\t\trssi_4ss_cnt;\n\tu32\t\t\trssi_4ss_sum[RF_PATH_MEM_SIZE];\n\tu32\t\t\tevm_4ss_sum[4];\n\tu32\t\t\tsnr_4ss_sum[RF_PATH_MEM_SIZE];\n\tu16\t\t\tevm_4ss_hist[4][PHY_HIST_SIZE];\n\tu16\t\t\tsnr_4ss_hist[4][PHY_HIST_SIZE];\n\t#endif\n};\n\nstruct phydm_phystatus_avg {\n\t/*@[CCK]*/\n\tu8\t\t\trssi_cck_avg;\n\tu8\t\t\trssi_beacon_avg;\n\t/*@[OFDM]*/\n\tu8\t\t\trssi_ofdm_avg[RF_PATH_MEM_SIZE];\n\tu8\t\t\tevm_ofdm_avg;\n\tu8\t\t\tsnr_ofdm_avg[RF_PATH_MEM_SIZE];\n\t/*@[1SS]*/\n\tu8\t\t\trssi_1ss_avg[RF_PATH_MEM_SIZE];\n\tu8\t\t\tevm_1ss_avg;\n\tu8\t\t\tsnr_1ss_avg[RF_PATH_MEM_SIZE];\n\t/*@[2SS]*/\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tu8\t\t\trssi_2ss_avg[RF_PATH_MEM_SIZE];\n\tu8\t\t\tevm_2ss_avg[2];\n\tu8\t\t\tsnr_2ss_avg[RF_PATH_MEM_SIZE];\n\t#endif\n\t/*@[3SS]*/\n\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\tu8\t\t\trssi_3ss_avg[RF_PATH_MEM_SIZE];\n\tu8\t\t\tevm_3ss_avg[3];\n\tu8\t\t\tsnr_3ss_avg[RF_PATH_MEM_SIZE];\n\t#endif\n\t/*@[4SS]*/\n\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\tu8\t\t\trssi_4ss_avg[RF_PATH_MEM_SIZE];\n\tu8\t\t\tevm_4ss_avg[4];\n\tu8\t\t\tsnr_4ss_avg[RF_PATH_MEM_SIZE];\n\t#endif\n};\n\nstruct odm_phy_dbg_info {\n\t/*@ODM Write,debug info*/\n\tu32\t\t\tnum_qry_phy_status_cck;\n\tu32\t\t\tnum_qry_phy_status_ofdm;\n#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) || (defined(PHYSTS_3RD_TYPE_SUPPORT))\n\tu32\t\t\tnum_qry_mu_pkt;\n\tu32\t\t\tnum_qry_bf_pkt;\n\tu16\t\t\tnum_mu_vht_pkt[VHT_RATE_NUM];\n\tboolean\t\t\tis_ldpc_pkt;\n\tboolean\t\t\tis_stbc_pkt;\n\tu8\t\t\tnum_of_ppdu[4];\n\tu8\t\t\tgid_num[4];\n#endif\n\tu32\t\t\tcondi_num; /*@condition number U(18,4)*/\n\tu8\t\t\tcondi_num_cdf[CN_CNT_MAX];\n\tu8\t\t\tnum_qry_beacon_pkt;\n\tu8\t\t\tbeacon_cnt_in_period; /*@beacon cnt within watchdog period*/\n\tu8\t\t\tbeacon_phy_rate;\n\tu8\t\t\tshow_phy_sts_all_pkt;\t/*@Show phy status witch not match BSSID*/\n\tu16\t\t\tshow_phy_sts_max_cnt;\t/*@show number of phy-status row data per PHYDM watchdog*/\n\tu16\t\t\tshow_phy_sts_cnt;\n\tu16\t\t\tnum_qry_legacy_pkt[LEGACY_RATE_NUM];\n\tu16\t\t\tnum_qry_ht_pkt[HT_RATE_NUM];\n\tu16\t\t\tnum_qry_pkt_sc_20m[LOW_BW_RATE_NUM]; /*@20M SC*/\n\tboolean\t\t\tht_pkt_not_zero;\n\tboolean\t\t\tlow_bw_20_occur;\n\t#if ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT)\n\tu16\t\t\tnum_qry_vht_pkt[VHT_RATE_NUM];\n\tu16\t\t\tnum_qry_pkt_sc_40m[LOW_BW_RATE_NUM]; /*@40M SC*/\n\tboolean\t\t\tvht_pkt_not_zero;\n\tboolean\t\t\tlow_bw_40_occur;\n\t#endif\n\tu16\t\t\tsnr_hist_th[PHY_HIST_SIZE - 1];\n\tu16\t\t\tevm_hist_th[PHY_HIST_SIZE - 1];\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\ts16 cfo_tail[4]; /* per-path's cfo_tail */\n\t#endif\n\tstruct phydm_phystatus_statistic\tphysts_statistic_info;\n\tstruct phydm_phystatus_avg\tphystatus_statistic_avg;\n};\n\nenum odm_cmninfo {\n\t/*@Fixed value*/\n\t/*@-----------HOOK BEFORE REG INIT-----------*/\n\tODM_CMNINFO_PLATFORM = 0,\n\tODM_CMNINFO_ABILITY,\n\tODM_CMNINFO_INTERFACE,\n\tODM_CMNINFO_MP_TEST_CHIP,\n\tODM_CMNINFO_IC_TYPE,\n\tODM_CMNINFO_CUT_VER,\n\tODM_CMNINFO_FAB_VER,\n\tODM_CMNINFO_FW_VER,\n\tODM_CMNINFO_FW_SUB_VER,\n\tODM_CMNINFO_RF_TYPE,\n\tODM_CMNINFO_RFE_TYPE,\n\tODM_CMNINFO_DPK_EN,\n\tODM_CMNINFO_BOARD_TYPE,\n\tODM_CMNINFO_PACKAGE_TYPE,\n\tODM_CMNINFO_EXT_LNA,\n\tODM_CMNINFO_5G_EXT_LNA,\n\tODM_CMNINFO_EXT_PA,\n\tODM_CMNINFO_5G_EXT_PA,\n\tODM_CMNINFO_GPA,\n\tODM_CMNINFO_APA,\n\tODM_CMNINFO_GLNA,\n\tODM_CMNINFO_ALNA,\n\tODM_CMNINFO_TDMA,\n\tODM_CMNINFO_EXT_TRSW,\n\tODM_CMNINFO_EXT_LNA_GAIN,\n\tODM_CMNINFO_PATCH_ID,\n\tODM_CMNINFO_BINHCT_TEST,\n\tODM_CMNINFO_BWIFI_TEST,\n\tODM_CMNINFO_SMART_CONCURRENT,\n\tODM_CMNINFO_CONFIG_BB_RF,\n\tODM_CMNINFO_IQKPAOFF,\n\tODM_CMNINFO_HUBUSBMODE,\n\tODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,\n\tODM_CMNINFO_TX_TP,\n\tODM_CMNINFO_RX_TP,\n\tODM_CMNINFO_SOUNDING_SEQ,\n\tODM_CMNINFO_REGRFKFREEENABLE,\n\tODM_CMNINFO_RFKFREEENABLE,\n\tODM_CMNINFO_NORMAL_RX_PATH_CHANGE,\n\tODM_CMNINFO_VALID_PATH_SET,\n\tODM_CMNINFO_EFUSE0X3D8,\n\tODM_CMNINFO_EFUSE0X3D7,\n\tODM_CMNINFO_SOFT_AP_SPECIAL_SETTING,\n\tODM_CMNINFO_X_CAP_SETTING,\n\tODM_CMNINFO_ADVANCE_OTA,\n\tODM_CMNINFO_HP_HWID,\n\tODM_CMNINFO_DIS_DPD,\n\t/*@-----------HOOK BEFORE REG INIT-----------*/\n\n\t/*@Dynamic value:*/\n\n\t/*@--------- POINTER REFERENCE-----------*/\n\tODM_CMNINFO_TX_UNI,\n\tODM_CMNINFO_RX_UNI,\n\tODM_CMNINFO_BAND,\n\tODM_CMNINFO_SEC_CHNL_OFFSET,\n\tODM_CMNINFO_SEC_MODE,\n\tODM_CMNINFO_BW,\n\tODM_CMNINFO_CHNL,\n\tODM_CMNINFO_FORCED_RATE,\n\tODM_CMNINFO_ANT_DIV,\n\tODM_CMNINFO_PATH_DIV,\n\tODM_CMNINFO_ADAPTIVE_SOML,\n\tODM_CMNINFO_ADAPTIVITY,\n\tODM_CMNINFO_SCAN,\n\tODM_CMNINFO_POWER_SAVING,\n\tODM_CMNINFO_ONE_PATH_CCA,\n\tODM_CMNINFO_DRV_STOP,\n\tODM_CMNINFO_PNP_IN,\n\tODM_CMNINFO_INIT_ON,\n\tODM_CMNINFO_ANT_TEST,\n\tODM_CMNINFO_NET_CLOSED,\n\tODM_CMNINFO_P2P_LINK,\n\tODM_CMNINFO_FCS_MODE,\n\tODM_CMNINFO_IS1ANTENNA,\n\tODM_CMNINFO_RFDEFAULTPATH,\n\tODM_CMNINFO_DFS_MASTER_ENABLE,\n\tODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC,\n\tODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA,\n\tODM_CMNINFO_SOFT_AP_MODE,\n\tODM_CMNINFO_MP_MODE,\n\tODM_CMNINFO_INTERRUPT_MASK,\n\tODM_CMNINFO_BB_OPERATION_MODE,\n\tODM_CMNINFO_BF_ANTDIV_DECISION,\n\tODM_CMNINFO_MANUAL_SUPPORTABILITY,\n\t/*@--------- POINTER REFERENCE-----------*/\n\n\t/*@------------CALL BY VALUE-------------*/\n\tODM_CMNINFO_WIFI_DIRECT,\n\tODM_CMNINFO_WIFI_DISPLAY,\n\tODM_CMNINFO_LINK_IN_PROGRESS,\n\tODM_CMNINFO_LINK,\n\tODM_CMNINFO_CMW500LINK,\n\tODM_CMNINFO_STATION_STATE,\n\tODM_CMNINFO_RSSI_MIN,\n\tODM_CMNINFO_RSSI_MIN_BY_PATH,\n\tODM_CMNINFO_DBG_COMP,\n\tODM_CMNINFO_RA_THRESHOLD_HIGH,\t/*to be removed*/\n\tODM_CMNINFO_RA_THRESHOLD_LOW,\t/*to be removed*/\n\tODM_CMNINFO_RF_ANTENNA_TYPE,\n\tODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH,\n\tODM_CMNINFO_BE_FIX_TX_ANT,\n\tODM_CMNINFO_BT_ENABLED,\n\tODM_CMNINFO_BT_HS_CONNECT_PROCESS,\n\tODM_CMNINFO_BT_HS_RSSI,\n\tODM_CMNINFO_BT_OPERATION,\n\tODM_CMNINFO_BT_LIMITED_DIG,\n\tODM_CMNINFO_AP_TOTAL_NUM,\n\tODM_CMNINFO_POWER_TRAINING,\n\tODM_CMNINFO_DFS_REGION_DOMAIN,\n\tODM_CMNINFO_BT_CONTINUOUS_TURN,\n\tODM_CMNINFO_IS_DOWNLOAD_FW,\n\tODM_CMNINFO_PHYDM_PATCH_ID,\n\tODM_CMNINFO_RRSR_VAL,\n\t/*@------------CALL BY VALUE-------------*/\n\n\t/*@Dynamic ptr array hook itms.*/\n\tODM_CMNINFO_STA_STATUS,\n\tODM_CMNINFO_MAX,\n\n};\n\nenum phydm_rfe_bb_source_sel {\n\tPAPE_2G\t\t\t= 0,\n\tPAPE_5G\t\t\t= 1,\n\tLNA0N_2G\t\t= 2,\n\tLNAON_5G\t\t= 3,\n\tTRSW\t\t\t= 4,\n\tTRSW_B\t\t\t= 5,\n\tGNT_BT\t\t\t= 6,\n\tZERO\t\t\t= 7,\n\tANTSEL_0\t\t= 8,\n\tANTSEL_1\t\t= 9,\n\tANTSEL_2\t\t= 0xa,\n\tANTSEL_3\t\t= 0xb,\n\tANTSEL_4\t\t= 0xc,\n\tANTSEL_5\t\t= 0xd,\n\tANTSEL_6\t\t= 0xe,\n\tANTSEL_7\t\t= 0xf\n};\n\nenum phydm_info_query {\n\tPHYDM_INFO_FA_OFDM,\n\tPHYDM_INFO_FA_CCK,\n\tPHYDM_INFO_FA_TOTAL,\n\tPHYDM_INFO_CCA_OFDM,\n\tPHYDM_INFO_CCA_CCK,\n\tPHYDM_INFO_CCA_ALL,\n\tPHYDM_INFO_CRC32_OK_VHT,\n\tPHYDM_INFO_CRC32_OK_HT,\n\tPHYDM_INFO_CRC32_OK_LEGACY,\n\tPHYDM_INFO_CRC32_OK_CCK,\n\tPHYDM_INFO_CRC32_ERROR_VHT,\n\tPHYDM_INFO_CRC32_ERROR_HT,\n\tPHYDM_INFO_CRC32_ERROR_LEGACY,\n\tPHYDM_INFO_CRC32_ERROR_CCK,\n\tPHYDM_INFO_EDCCA_FLAG,\n\tPHYDM_INFO_OFDM_ENABLE,\n\tPHYDM_INFO_CCK_ENABLE,\n\tPHYDM_INFO_CRC32_OK_HT_AGG,\n\tPHYDM_INFO_CRC32_ERROR_HT_AGG,\n\tPHYDM_INFO_DBG_PORT_0,\n\tPHYDM_INFO_CURR_IGI,\n\tPHYDM_INFO_RSSI_MIN,\n\tPHYDM_INFO_RSSI_MAX,\n\tPHYDM_INFO_CLM_RATIO,\n\tPHYDM_INFO_NHM_RATIO,\n};\n\nenum phydm_api {\n\tPHYDM_API_NBI\t\t= 1,\n\tPHYDM_API_CSI_MASK\t= 2,\n};\n\nenum phydm_func_idx { /*@F_XXX = PHYDM XXX function*/\n\n\tF00_DIG\t\t\t= 0,\n\tF01_RA_MASK\t\t= 1,\n\tF02_DYN_TXPWR\t\t= 2,\n\tF03_FA_CNT\t\t= 3,\n\tF04_RSSI_MNTR\t\t= 4,\n\tF05_CCK_PD\t\t= 5,\n\tF06_ANT_DIV\t\t= 6,\n\tF07_SMT_ANT\t\t= 7,\n\tF08_PWR_TRAIN\t\t= 8,\n\tF09_RA\t\t\t= 9,\n\tF10_PATH_DIV\t\t= 10,\n\tF11_DFS\t\t\t= 11,\n\tF12_DYN_ARFR\t\t= 12,\n\tF13_ADPTVTY\t\t= 13,\n\tF14_CFO_TRK\t\t= 14,\n\tF15_ENV_MNTR\t\t= 15,\n\tF16_PRI_CCA\t\t= 16,\n\tF17_ADPTV_SOML\t\t= 17,\n\tF18_LNA_SAT_CHK\t\t= 18,\n};\n\n/*@=[PHYDM supportability]==========================================*/\nenum odm_ability {\n\tODM_BB_DIG\t\t= BIT(F00_DIG),\n\tODM_BB_RA_MASK\t\t= BIT(F01_RA_MASK),\n\tODM_BB_DYNAMIC_TXPWR\t= BIT(F02_DYN_TXPWR),\n\tODM_BB_FA_CNT\t\t= BIT(F03_FA_CNT),\n\tODM_BB_RSSI_MONITOR\t= BIT(F04_RSSI_MNTR),\n\tODM_BB_CCK_PD\t\t= BIT(F05_CCK_PD),\n\tODM_BB_ANT_DIV\t\t= BIT(F06_ANT_DIV),\n\tODM_BB_SMT_ANT\t\t= BIT(F07_SMT_ANT),\n\tODM_BB_PWR_TRAIN\t= BIT(F08_PWR_TRAIN),\n\tODM_BB_RATE_ADAPTIVE\t= BIT(F09_RA),\n\tODM_BB_PATH_DIV\t\t= BIT(F10_PATH_DIV),\n\tODM_BB_DFS\t\t= BIT(F11_DFS),\n\tODM_BB_DYNAMIC_ARFR\t= BIT(F12_DYN_ARFR),\n\tODM_BB_ADAPTIVITY\t= BIT(F13_ADPTVTY),\n\tODM_BB_CFO_TRACKING\t= BIT(F14_CFO_TRK),\n\tODM_BB_ENV_MONITOR\t= BIT(F15_ENV_MNTR),\n\tODM_BB_PRIMARY_CCA\t= BIT(F16_PRI_CCA),\n\tODM_BB_ADAPTIVE_SOML\t= BIT(F17_ADPTV_SOML),\n\tODM_BB_LNA_SAT_CHK\t= BIT(F18_LNA_SAT_CHK),\n};\n\n/*@=[PHYDM Debug Component]=====================================*/\nenum phydm_dbg_comp {\n\t/*@BB Driver Functions*/\n\tDBG_DIG\t\t\t= BIT(F00_DIG),\n\tDBG_RA_MASK\t\t= BIT(F01_RA_MASK),\n\tDBG_DYN_TXPWR\t\t= BIT(F02_DYN_TXPWR),\n\tDBG_FA_CNT\t\t= BIT(F03_FA_CNT),\n\tDBG_RSSI_MNTR\t\t= BIT(F04_RSSI_MNTR),\n\tDBG_CCKPD\t\t= BIT(F05_CCK_PD),\n\tDBG_ANT_DIV\t\t= BIT(F06_ANT_DIV),\n\tDBG_SMT_ANT\t\t= BIT(F07_SMT_ANT),\n\tDBG_PWR_TRAIN\t\t= BIT(F08_PWR_TRAIN),\n\tDBG_RA\t\t\t= BIT(F09_RA),\n\tDBG_PATH_DIV\t\t= BIT(F10_PATH_DIV),\n\tDBG_DFS\t\t\t= BIT(F11_DFS),\n\tDBG_DYN_ARFR\t\t= BIT(F12_DYN_ARFR),\n\tDBG_ADPTVTY\t\t= BIT(F13_ADPTVTY),\n\tDBG_CFO_TRK\t\t= BIT(F14_CFO_TRK),\n\tDBG_ENV_MNTR\t\t= BIT(F15_ENV_MNTR),\n\tDBG_PRI_CCA\t\t= BIT(F16_PRI_CCA),\n\tDBG_ADPTV_SOML\t\t= BIT(F17_ADPTV_SOML),\n\tDBG_LNA_SAT_CHK\t\t= BIT(F18_LNA_SAT_CHK),\n\t/*BIT(19)*/\n\t/*Neet to re-arrange*/\n\tDBG_PHY_STATUS\t\t= BIT(20),\n\tDBG_TMP\t\t\t= BIT(21),\n\tDBG_FW_TRACE\t\t= BIT(22),\n\tDBG_TXBF\t\t= BIT(23),\n\tDBG_COMMON_FLOW\t\t= BIT(24),\n\tDBG_COMP_MCC\t\t= BIT(25),\n\t/*BIT(26)*/\n\tDBG_DM_SUMMARY\t\t= BIT(27),\n\tODM_PHY_CONFIG\t\t= BIT(28),\n\tODM_COMP_INIT\t\t= BIT(29),\n\tDBG_CMN\t\t\t= BIT(30),/*@common*/\n\tODM_COMP_API\t\t= BIT(31)\n};\n\n/*@=========================================================*/\n\n/*@ODM_CMNINFO_ONE_PATH_CCA*/\nenum odm_cca_path {\n\tODM_CCA_2R\t\t= 0,\n\tODM_CCA_1R_A\t\t= 1,\n\tODM_CCA_1R_B\t\t= 2,\n};\n\nenum phy_reg_pg_type {\n\tPHY_REG_PG_RELATIVE_VALUE = 0,\n\tPHY_REG_PG_EXACT_VALUE\t= 1\n};\n\nenum phydm_offload_ability {\n\tPHYDM_PHY_PARAM_OFFLOAD = BIT(0),\n\tPHYDM_RF_IQK_OFFLOAD\t= BIT(1),\n};\n\nstruct phydm_pause_lv {\n\ts8\t\t\tlv_dig;\n\ts8\t\t\tlv_cckpd;\n\ts8\t\t\tlv_antdiv;\n\ts8\t\t\tlv_adapt;\n\ts8\t\t\tlv_adsl;\n};\n\nstruct phydm_func_poiner {\n\tvoid (*pause_phydm_handler)(void *dm_void, u32 *val_buf, u8 val_len);\n};\n\nstruct pkt_process_info {\n\tu8\t\t\tphystatus_smp_mode_en; /*@send phystatus every sampling time*/\n\tu8\t\t\tpre_ppdu_cnt;\n\tu8\t\t\tlna_idx;\n\tu8\t\t\tvga_idx;\n};\n\n#ifdef ODM_CONFIG_BT_COEXIST\nstruct\tphydm_bt_info {\n\tboolean\t\t\tis_bt_enabled;\t\t/*@BT is enabled*/\n\tboolean\t\t\tis_bt_connect_process;\t/*@BT HS is under connection progress.*/\n\tu8\t\t\tbt_hs_rssi;\t\t/*@BT HS mode wifi rssi value.*/\n\tboolean\t\t\tis_bt_hs_operation;\t/*@BT HS mode is under progress*/\n\tboolean\t\t\tis_bt_limited_dig;\t/*@BT is busy.*/\n};\n#endif\n\nstruct\tphydm_iot_center {\n\tboolean\t\t\tis_linked_cmw500;\n\tu8\t\t\twin_patch_id;\t\t/*Customer ID*/\n\tboolean\t\t\tpatch_id_021f0800;\n\tu32\t\t\tphydm_patch_id;\t\t/*temp for CCX IOT */\n\n};\n\n#if (RTL8822B_SUPPORT)\nstruct drp_rtl8822b_struct {\n\tenum bb_path path_judge;\n\tu16 path_a_cck_fa;\n\tu16 path_b_cck_fa;\n};\n#endif\n\n#ifdef CONFIG_MCC_DM\n#define MCC_DM_REG_NUM\t32\nstruct _phydm_mcc_dm_ {\n\tu8\t\tmcc_pre_status;\n\tu8\t\tmcc_reg_id[MCC_DM_REG_NUM];\n\tu16\t\tmcc_dm_reg[MCC_DM_REG_NUM];\n\tu8\t\tmcc_dm_val[MCC_DM_REG_NUM][2];\n\t/*mcc DIG*/\n\tu8\t\tmcc_rssi[2];\n\t/*u8\t\tmcc_igi[2];*/\n\n\t/* need to be config by driver*/\n\tu8\t\tmcc_status;\n\tu8\t\tsta_macid[2][NUM_STA];\n\tu16\t\tmcc_rf_ch[2];\n\n};\n#endif\n\n#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT)\nstruct phydm_physts {\n\tu8\t\t\tcck_gi_u_bnd;\n\tu8\t\t\tcck_gi_l_bnd;\n};\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t#if (RT_PLATFORM != PLATFORM_LINUX)\n\t\ttypedef\n\t#endif\n\nstruct dm_struct {\n#else/*for AP, CE Team*/\nstruct dm_struct {\n#endif\n\t/*@Add for different team use temporarily*/\n\tvoid\t\t\t*adapter;\t\t/*@For CE/NIC team*/\n\tstruct rtl8192cd_priv\t*priv;\t\t\t/*@For AP team*/\n\tboolean\t\t\todm_ready;\n\tenum phy_reg_pg_type\tphy_reg_pg_value_type;\n\tu8\t\t\tphy_reg_pg_version;\n\tu64\t\t\tsupport_ability;\t/*@PHYDM function Supportability*/\n\tu64\t\t\tpause_ability;\t\t/*@PHYDM function pause Supportability*/\n\tu64\t\t\tdebug_components;\n\tu8\t\t\tcmn_dbg_msg_period;\n\tu8\t\t\tcmn_dbg_msg_cnt;\n\tu32\t\t\tfw_debug_components;\n\tu32\t\t\tnum_qry_phy_status_all;\t/*@CCK + OFDM*/\n\tu32\t\t\tlast_num_qry_phy_status_all;\n\tu32\t\t\trx_pwdb_ave;\n\tboolean\t\t\tis_init_hw_info_by_rfe;\n\n\t/*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/\n\tboolean\t\t\tis_cck_high_power;\n\tu8\t\t\trf_path_rx_enable;\n\t/*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/\n\n\t/* @COMMON INFORMATION */\n\n\t/*@Init value*/\n\t/*@-----------HOOK BEFORE REG INIT-----------*/\n\n\tu8\t\t\tsupport_platform;\t/*@PHYDM Platform info WIN/AP/CE = 1/2/3 */\n\tu8\t\t\tnormal_rx_path;\n\tu8\t\t\tvalid_path_set;\t/*@use for single rx path only*/\n\tboolean\t\t\tbrxagcswitch;\t\t/* @for rx AGC table switch in Microsoft case */\n\tu8\t\t\tsupport_interface;\t/*@PHYDM PCIE/USB/SDIO = 1/2/3*/\n\tu32\t\t\tsupport_ic_type;\t/*@PHYDM supported IC*/\n\tenum phydm_api_host\trun_in_drv_fw;\t\t/*@PHYDM API is using in FW or Driver*/\n\tu8\t\t\tic_ip_series;\t\t/*N/AC/JGR3*/\n\tenum phydm_phy_sts_type\tic_phy_sts_type;\t/*@Type1/type2/type3*/\n\tu8\t\t\tcut_version;\t\t/*@cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/\n\tu8\t\t\tfab_version;\t\t/*@Fab version TSMC/UMC = 0/1*/\n\tu8\t\t\tfw_version;\n\tu8\t\t\tfw_sub_version;\n\tu8\t\t\trf_type;\t\t/*@RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/\n\tu8\t\t\trfe_type;\n\tu8\t\t\tboard_type;\n\tu8\t\t\tpackage_type;\n\tu16\t\t\ttype_glna;\n\tu16\t\t\ttype_gpa;\n\tu16\t\t\ttype_alna;\n\tu16\t\t\ttype_apa;\n\tu8\t\t\text_lna;\t\t/*@with 2G external LNA  NO/Yes = 0/1*/\n\tu8\t\t\text_lna_5g;\t\t/*@with 5G external LNA  NO/Yes = 0/1*/\n\tu8\t\t\text_pa;\t\t\t/*@with 2G external PNA  NO/Yes = 0/1*/\n\tu8\t\t\text_pa_5g;\t\t/*@with 5G external PNA  NO/Yes = 0/1*/\n\tu8\t\t\tefuse0x3d7;\t\t/*@with Efuse number*/\n\tu8\t\t\tefuse0x3d8;\n\tu8\t\t\text_trsw;\t\t/*@with external TRSW  NO/Yes = 0/1*/\n\tu8\t\t\text_lna_gain;\t\t/*@gain of external lna*/\n\tboolean\t\t\tis_in_hct_test;\n\tu8\t\t\twifi_test;\n\tboolean\t\t\tis_dual_mac_smart_concurrent;\n\tu32\t\t\tbk_support_ability;\t/*SD4 only*/\n\tu8\t\t\twith_extenal_ant_switch;\n\t/*@cck agc relative*/\n\tboolean\t\t\tcck_new_agc;\n\ts8\t\t\tcck_lna_gain_table[8];\n\t/*@-------------------------------------*/\n\tu32\t\t\tphydm_sys_up_time;\n\tu8\t\t\tnum_rf_path;\t\t/*@ex: 8821C=1, 8192E=2, 8814B=4*/\n\tu32\t\t\tsoft_ap_special_setting;\n\tboolean\t\t\tboolean_dummy;\n\ts8\t\t\ts8_dummy;\n\tu8\t\t\tu8_dummy;\n\tu16\t\t\tu16_dummy;\n\tu32\t\t\tu32_dummy;\n\tu8\t\t\trfe_hwsetting_band;\n\tu8\t\t\tp_advance_ota;\n\tboolean\t\t\thp_hw_id;\n\tboolean\t\t\tBOOLEAN_temp;\n\tboolean\t\t\tis_dfs_band;\n\tu8\t\t\tis_rx_blocking_en;\n\tu16\t\t\tfw_offload_ability;\n\tboolean\t\t\tis_download_fw;\n\tboolean\t\t\ten_dis_dpd;\n\tu16\t\t\tdis_dpd_rate;\n\t#if (RTL8822C_SUPPORT)\n\tu8\t\t\ttxagc_buff[2][NUM_RATE_AC_2SS];\n\tu32\t\t\tbp_0x9b0;\n\t#endif\n/*@-----------HOOK BEFORE REG INIT-----------*/\n/*@===========================================================*/\n/*@====[ CALL BY Reference ]=========================================*/\n/*@===========================================================*/\n\n\tu64\t\t\t*num_tx_bytes_unicast;\t/*@TX Unicast byte cnt*/\n\tu64\t\t\t*num_rx_bytes_unicast;\t/*@RX Unicast byte cnt*/\n\tu8\t\t\t*band_type;\t\t/*@2.4G/5G = 0/1*/\n\tu8\t\t\t*sec_ch_offset;\t\t/*@Secondary channel offset don't_care/below/above = 0/1/2*/\n\tu8\t\t\t*security;\t\t/*@security mode Open/WEP/AES/TKIP = 0/1/2/3*/\n\tu8\t\t\t*band_width;\t\t/*@20M/40M/80M = 0/1/2*/\n\tu8\t\t\t*channel;\t\t/*@central CH number*/\n\tboolean\t\t\t*is_scan_in_process;\n\tboolean\t\t\t*is_power_saving;\n\tboolean\t\t\t*is_tdma;\n\tu8\t\t\t*one_path_cca;\t\t/*@CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/\n\tu8\t\t\t*antenna_test;\n\tboolean\t\t\t*is_net_closed;\n\tboolean\t\t\t*is_fcs_mode_enable;\t/*@fast channel switch (= MCC mode)*/\n\t/*@--------- For 8723B IQK-------------------------------------*/\n\tboolean\t\t\t*is_1_antenna;\n\tu8\t\t\t*rf_default_path;\t/* @0:S1, 1:S0 */\n\t/*@-----------------------------------------------------------*/\n\n\tu16\t\t\t*forced_data_rate;\n\tu8\t\t\t*enable_antdiv;\n\tu8\t\t\t*enable_pathdiv;\n\tu8\t\t\t*en_adap_soml;\n\tu8\t\t\t*enable_adaptivity;\n\tu8\t\t\t*hub_usb_mode;\t\t/*@1:USB2.0, 2:USB3.0*/\n\tboolean\t\t\t*is_fw_dw_rsvd_page_in_progress;\n\tu32\t\t\t*current_tx_tp;\n\tu32\t\t\t*current_rx_tp;\n\tu8\t\t\t*sounding_seq;\n\tu32\t\t\t*soft_ap_mode;\n\tu8\t\t\t*mp_mode;\n\tu32\t\t\t*interrupt_mask;\n\tu8\t\t\t*bb_op_mode;\n\tu32\t\t\t*manual_supportability;\n/*@===========================================================*/\n/*@====[ CALL BY VALUE ]===========================================*/\n/*@===========================================================*/\n\n\tu8\t\t\tdisable_phydm_watchdog;\n\tboolean\t\t\tis_link_in_process;\n\tboolean\t\t\tis_wifi_direct;\n\tboolean\t\t\tis_wifi_display;\n\tboolean\t\t\tis_linked;\n\tboolean\t\t\tpre_is_linked;\n\tboolean\t\t\tfirst_connect;\n\tboolean\t\t\tfirst_disconnect;\n\tboolean\t\t\tbsta_state;\n\tu8\t\t\trssi_min;\n\tu8\t\t\trssi_min_macid;\n\tu8\t\t\tpre_rssi_min;\n\tu8\t\t\trssi_max;\n\tu8\t\t\trssi_max_macid;\n\tu8\t\t\trssi_min_by_path;\n\tboolean\t\t\tis_mp_chip;\n\tboolean\t\t\tis_one_entry_only;\n\tu32\t\t\tone_entry_macid;\n\tu32\t\t\tone_entry_tp;\n\tu32\t\t\tpre_one_entry_tp;\n\tu8\t\t\tpre_number_linked_client;\n\tu8\t\t\tnumber_linked_client;\n\tu8\t\t\tpre_number_active_client;\n\tu8\t\t\tnumber_active_client;\n\tboolean\t\t\tis_disable_phy_api;\n\tu8\t\t\trssi_a;\n\tu8\t\t\trssi_b;\n\tu8\t\t\trssi_c;\n\tu8\t\t\trssi_d;\n\ts8\t\t\trxsc_80;\n\ts8\t\t\trxsc_40;\n\ts8\t\t\trxsc_20;\n\ts8\t\t\trxsc_l;\n\tu64\t\t\trssi_trsw;\n\tu64\t\t\trssi_trsw_h;\n\tu64\t\t\trssi_trsw_l;\n\tu64\t\t\trssi_trsw_iso;\n\tu8\t\t\ttx_ant_status; /*TX path enable*/\n\tu8\t\t\trx_ant_status; /*RX path enable*/\n\t#ifdef PHYDM_COMPILE_ABOVE_4SS\n\tenum bb_path\t\ttx_4ss_status; /*@Use N-X for 4STS rate*/\n\t#endif\n\t#ifdef PHYDM_COMPILE_ABOVE_3SS\n\tenum bb_path\t\ttx_3ss_status; /*@Use N-X for 3STS rate*/\n\t#endif\n\t#ifdef PHYDM_COMPILE_ABOVE_2SS\n\tenum bb_path\t\ttx_2ss_status; /*@Use N-X for 2STS rate*/\n\t#endif\n\tenum bb_path\t\ttx_1ss_status; /*@Use N-X for 1STS rate*/\n\tu8\t\t\tcck_lna_idx;\n\tu8\t\t\tcck_vga_idx;\n\tu8\t\t\tcurr_station_id;\n\tu8\t\t\tofdm_agc_idx[4];\n\tu8\t\t\trx_rate;\n\tu8\t\t\trate_ss;\n\tu8\t\t\ttx_rate;\n\tu8\t\t\tlinked_interval;\n\tu8\t\t\tpre_channel;\n\tu32\t\t\ttxagc_offset_value_a;\n\tboolean\t\t\tis_txagc_offset_positive_a;\n\tu32\t\t\ttxagc_offset_value_b;\n\tboolean\t\t\tis_txagc_offset_positive_b;\n\tu8\t\t\tap_total_num;\n\t/*@[traffic]*/\n\tu8\t\t\ttraffic_load;\n\tu8\t\t\tpre_traffic_load;\n\tu32\t\t\ttx_tp;\t\t\t/*@Mbps*/\n\tu32\t\t\trx_tp;\t\t\t/*@Mbps*/\n\tu32\t\t\ttotal_tp;\t\t/*@Mbps*/\n\tu8\t\t\ttxrx_state_all;\t\t/*@0:tx, 1:rx, 2:bi-dir*/\n\tu64\t\t\tcur_tx_ok_cnt;\n\tu64\t\t\tcur_rx_ok_cnt;\n\tu64\t\t\tlast_tx_ok_cnt;\n\tu64\t\t\tlast_rx_ok_cnt;\n\tu16\t\t\tconsecutive_idlel_time;\t/*@unit: second*/\n\t/*@---------------------------*/\n\tboolean\t\t\tis_bb_swing_offset_positive_a;\n\tboolean\t\t\tis_bb_swing_offset_positive_b;\n\n\t/*@[DIG]*/\n\tboolean\t\t\tMPDIG_2G;\t\t/*off MPDIG*/\n\tu8\t\t\ttimes_2g;\t\t/*@for MP DIG*/\n\tu8\t\t\tforce_igi;\t\t/*@for debug*/\n\n\t/*@[TDMA-DIG]*/\n\tu8\t\t\ttdma_dig_timer_ms;\n\tu8\t\t\ttdma_dig_state_number;\n\tu8\t\t\ttdma_dig_low_upper_bond;\n\tu8\t\t\tforce_tdma_low_igi;\n\tu8\t\t\tforce_tdma_high_igi;\n\tu8\t\t\tfix_expire_to_zero;\n\tboolean\t\t\toriginal_dig_restore;\n\t/*@---------------------------*/\n\n\t/*@[AntDiv]*/\n\tu8\t\t\tant_div_type;\n\tu8\t\t\tantdiv_rssi;\n\tu8\t\t\tfat_comb_a;\n\tu8\t\t\tfat_comb_b;\n\tu8\t\t\tantdiv_intvl;\n\tu8\t\t\tantdiv_delay;\n\tu8\t\t\tant_type;\n\tu8\t\t\tant_type2;\n\tu8\t\t\tpre_ant_type;\n\tu8\t\t\tpre_ant_type2;\n\tu8\t\t\tantdiv_period;\n\tu8\t\t\tevm_antdiv_period;\n\tu8\t\t\tantdiv_select;\n\tu8\t\t\tantdiv_train_num; /*@training time for each antenna in EVM method*/\n\tu8\t\t\tstop_antdiv_rssi_th;\n\tu16\t\t\tstop_antdiv_tp_diff_th;\n\tu16\t\t\tstop_antdiv_tp_th;\n\tu8\t\t\tantdiv_tp_period;\n\tu16\t\t\ttp_active_th;\n\tu8\t\t\ttp_active_occur;\n\tu8\t\t\tpath_select;\n\tu8\t\t\tantdiv_evm_en;\n\tu8\t\t\tbdc_holdstate;\n\tu8\t\t\tantdiv_counter;\n\t/*@---------------------------*/\n\n\tu8\t\t\tndpa_period;\n\tboolean\t\t\th2c_rarpt_connect;\n\tboolean\t\t\tcck_agc_report_type; /*@1:4bit LNA, 0:3bit LNA */\n\tu8\t\t\tprint_agc;\n\tu8\t\t\tla_mode;\n\t/*@---8821C Antenna and RF Set BTG/WLG/WLA Select---------------*/\n\tu8\t\t\tcurrent_rf_set_8821c;\n\tu8\t\t\tdefault_rf_set_8821c;\n\tu8\t\t\tcurrent_ant_num_8821c;\n\tu8\t\t\tdefault_ant_num_8821c;\n\tu8\t\t\trfe_type_expand;\n\t/*@-----------------------------------------------------------*/\n\t/*@---For Adaptivtiy---------------------------------------------*/\n\ts8\t\t\tTH_L2H_default;\n\ts8\t\t\tth_edcca_hl_diff_default;\n\ts8\t\t\tth_l2h_ini;\n\ts8\t\t\tth_edcca_hl_diff;\n\tboolean\t\t\tcarrier_sense_enable;\n\t/*@-----------------------------------------------------------*/\n\tu8\t\t\tpre_dbg_priority;\n\tu8\t\t\tnbi_set_result;\n\tu8\t\t\tc2h_cmd_start;\n\tu8\t\t\tfw_debug_trace[60];\n\tu8\t\t\tpre_c2h_seq;\n\tboolean\t\t\tfw_buff_is_enpty;\n\tu32\t\t\tdata_frame_num;\n#if (RTL8814B_SUPPORT)\n\t/*@--- for spur detection ---------------------------------------*/\n\tu8\t\t\tdsde_sel;\n\tu8\t\t\tnbi_path_sel;\n\tu8\t\t\tcsi_wgt;\n\t/*@------------------------------------------*/\n#endif\n\t/*@--- for noise detection ---------------------------------------*/\n\tboolean\t\t\tis_noisy_state;\n\tboolean\t\t\tnoisy_decision; /*@b_noisy*/\n\tboolean\t\t\tpre_b_noisy;\n\tu32\t\t\tnoisy_decision_smooth;\n\t/*@-----------------------------------------------------------*/\n\n\t/*@--- for MCC ant weighting ------------------------------------*/\n\tboolean\t\t\tis_stop_dym_ant_weighting;\n\t/*@-----------------------------------------------------------*/\n\n\tboolean\t\t\tis_disable_dym_ecs;\n\tboolean\t\t\tis_disable_dym_ant_weighting;\n\tstruct cmn_sta_info\t*phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];\n\tu8\t\t\tphydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];/*@sta_idx = phydm_macid_table[HW_macid]*/\n\n#if (RATE_ADAPTIVE_SUPPORT)\n\tu16\t\t\tcurrmin_rpt_time;\n\tstruct _phydm_txstatistic_ hw_stats;\n\tstruct _odm_ra_info_\tra_info[ODM_ASSOCIATE_ENTRY_NUM];\n/*Use mac_id as array index. STA mac_id=0*/\n/*VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/\n#endif\n\t/*@2012/02/14 MH Add to share 88E ra with other SW team*/\n\t/*We need to colelct all support abilit to a proper area.*/\n\tboolean\t\t\tra_support88e;\n\tboolean\t\t\t*is_driver_stopped;\n\tboolean\t\t\t*is_driver_is_going_to_pnp_set_power_sleep;\n\tboolean\t\t\t*pinit_adpt_in_progress;\n\tboolean\t\t\tis_user_assign_level;\n\tu8\t\t\tRSSI_BT;\t\t/*@come from BT*/\n\n\t/*@---PSD Relative ---------------------------------------------*/\n\tboolean\t\t\tis_psd_in_process;\n\tboolean\t\t\tis_psd_active;\n\t/*@-----------------------------------------------------------*/\n\n\tboolean\t\t\tbsomlenabled;\t/* @D-SoML control */\n\tu8\t\t\tno_ndp_cnts;\n\tu8\t\t\tndp_cnt_pre;\n\tboolean\t\t\tis_beamformed;\n\tboolean\t\t\tbhtstfdisabled;\t/* @dynamic HTSTF gain control*/\n\tu32\t\t\tn_iqk_cnt;\n\tu32\t\t\tn_iqk_ok_cnt;\n\tu32\t\t\tn_iqk_fail_cnt;\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\tboolean\t\t\tconfig_bbrf;\n#endif\n\tboolean\t\t\tis_disable_power_training;\n\tboolean\t\t\tis_bt_continuous_turn;\n\tu8\t\t\tenhance_pwr_th[3];\n\tu8\t\t\tset_pwr_th[3];\n\t/*@----------Dyn Tx Pwr ---------------------------------------*/\n#ifdef BB_RAM_SUPPORT\n\tstruct phydm_bb_ram_ctrl p_bb_ram_ctrl;\n#endif\n\tu8\t\t\tdynamic_tx_high_power_lvl;\n\tvoid\t(*fill_desc_dyntxpwr)(void *dm, u8 *desc, u8 dyn_tx_power);\n\tu8\t\t\tlast_dtp_lvl;\n\tu8\t\t\tmin_power_index;\n\tu32\t\t\ttx_agc_ofdm_18_6;\n\t/*-------------------------------------------------------------*/\n\tu8\t\t\trx_pkt_type;\n\n#ifdef CONFIG_PHYDM_DFS_MASTER\n\tu8\t\t\tdfs_region_domain;\n\tu8\t\t\t*dfs_master_enabled;\n\t/*@---phydm_radar_detect_with_dbg_parm start --------------------*/\n\tu8\t\t\tradar_detect_dbg_parm_en;\n\tu32\t\t\tradar_detect_reg_918;\n\tu32\t\t\tradar_detect_reg_91c;\n\tu32\t\t\tradar_detect_reg_920;\n\tu32\t\t\tradar_detect_reg_924;\n\n\tu32\t\t\tradar_detect_reg_a40;\n\tu32\t\t\tradar_detect_reg_a44;\n\tu32\t\t\tradar_detect_reg_a48;\n\tu32\t\t\tradar_detect_reg_a4c;\n\tu32\t\t\tradar_detect_reg_a50;\n\tu32\t\t\tradar_detect_reg_a54;\n\n\tu32\t\t\tradar_detect_reg_f54;\n\tu32\t\t\tradar_detect_reg_f58;\n\tu32\t\t\tradar_detect_reg_f5c;\n\tu32\t\t\tradar_detect_reg_f70;\n\tu32\t\t\tradar_detect_reg_f74;\n\t/*@---For zero-wait DFS---------------------------------------*/\n\tboolean\t\t\tseg1_dfs_flag;\n\t/*@-----------------------------------------------------------*/\n/*@-----------------------------------------------------------*/\n#endif\n\n/*@=== RTL8721D ADC clock 80MHz only for CBW20MHz ===*/\n#if (RTL8721D_SUPPORT)\n\tboolean\t\t\tcbw20_adc80;\n#endif\n\n/*@=== PHYDM Timer ========================================== (start)*/\n\n\tstruct phydm_timer_list\tmpt_dig_timer;\n\tstruct phydm_timer_list\tfast_ant_training_timer;\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\tstruct phydm_timer_list\tevm_fast_ant_training_timer;\n#endif\n#ifdef PHYDM_TDMA_DIG_SUPPORT\n\tstruct phydm_timer_list tdma_dig_timer;\n#endif\n\tstruct phydm_timer_list\tsbdcnt_timer;\n\n/*@=== PHYDM Workitem ======================================= (start)*/\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#if USE_WORKITEM\n\tRT_WORK_ITEM\t\tfast_ant_training_workitem;\n\tRT_WORK_ITEM\t\tra_rpt_workitem;\n\tRT_WORK_ITEM\t\tsbdcnt_workitem;\n\tRT_WORK_ITEM\t\tphydm_evm_antdiv_workitem;\n#endif\n#endif\n\n/*@=== PHYDM Structure ======================================== (start)*/\n\tstruct\tphydm_func_poiner\tphydm_func_handler;\n\tstruct\tphydm_iot_center\tiot_table;\n\n#ifdef ODM_CONFIG_BT_COEXIST\n\tstruct\tphydm_bt_info\t\tbt_info_table;\n#endif\n\n\tstruct\tpkt_process_info\tpkt_proc_struct;\n\tstruct phydm_adaptivity_struct\tadaptivity;\n\tstruct _DFS_STATISTICS\t\tdfs;\n\tstruct odm_noise_monitor\tnoise_level;\n\tstruct odm_phy_dbg_info\t\tphy_dbg_info;\n\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\tstruct phydm_bf_rate_info_jgr3 bf_rate_info_jgr3;\n#endif\n\n#ifdef CONFIG_ADAPTIVE_SOML\n\tstruct adaptive_soml\t\tdm_soml_table;\n#endif\n\n#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))\n\t#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tstruct _BF_DIV_COEX_\t\tdm_bdc_table;\n\t#endif\n\n\t#if (defined(CONFIG_HL_SMART_ANTENNA))\n\tstruct smt_ant_honbo\t\tdm_sat_table;\n\t#endif\n#endif\n\n#if (defined(CONFIG_SMART_ANTENNA))\n\tstruct smt_ant\t\t\tsmtant_table;\n#endif\n\n\tstruct _hal_rf_\t\t\trf_table;\t/*@for HALRF function*/\n\tstruct dm_rf_calibration_struct\trf_calibrate_info;\n\tstruct dm_iqk_info\t\tIQK_info;\n\tstruct dm_dpk_info\t\tdpk_info;\n\tstruct dm_dack_info\t\tdack_info;\n\n#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\tstruct phydm_fat_struct\t\tdm_fat_table;\n\tstruct sw_antenna_switch\tdm_swat_table;\n#endif\n\tstruct phydm_dig_struct\t\tdm_dig_table;\n#ifdef PHYDM_LNA_SAT_CHK_SUPPORT\n\tstruct phydm_lna_sat_t\t\tdm_lna_sat_info;\n#endif\n\n#ifdef CONFIG_MCC_DM\n\tstruct _phydm_mcc_dm_ mcc_dm;\n#endif\n\n#ifdef PHYDM_SUPPORT_CCKPD\n\tstruct phydm_cckpd_struct\tdm_cckpd_table;\n#endif\n\n#ifdef PHYDM_PRIMARY_CCA\n\tstruct phydm_pricca_struct\tdm_pri_cca;\n#endif\n\n\tstruct ra_table\t\t\tdm_ra_table;\n\tstruct phydm_fa_struct\t\tfalse_alm_cnt;\n#ifdef PHYDM_TDMA_DIG_SUPPORT\n\tstruct phydm_fa_acc_struct\tfalse_alm_cnt_acc;\n#ifdef IS_USE_NEW_TDMA\n\tstruct phydm_fa_acc_struct\tfalse_alm_cnt_acc_low;\n#endif\n#endif\n\tstruct phydm_cfo_track_struct\tdm_cfo_track;\n\tstruct ccx_info\t\t\tdm_ccx_info;\n\n\tstruct odm_power_trim_data\tpower_trim_data;\n#if (RTL8822B_SUPPORT)\n\tstruct drp_rtl8822b_struct\tphydm_rtl8822b;\n#endif\n\n#ifdef CONFIG_PSD_TOOL\n\tstruct psd_info\t\t\tdm_psd_table;\n#endif\n\n#if (PHYDM_LA_MODE_SUPPORT)\n\tstruct rt_adcsmp\t\tadcsmp;\n#endif\n\n#if (defined(CONFIG_PATH_DIVERSITY))\n\tstruct _ODM_PATH_DIVERSITY_\tdm_path_div;\n#endif\n\n#if (defined(CONFIG_ANT_DETECTION))\n\tstruct _ANT_DETECTED_INFO\tant_detected_info;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\tstruct _RT_BEAMFORMING_INFO \tbeamforming_info;\n#endif\n#endif\n#ifdef PHYDM_AUTO_DEGBUG\n\tstruct\tphydm_auto_dbg_struct\tauto_dbg_table;\n#endif\n\n\tstruct\tphydm_pause_lv\t\tpause_lv_table;\n\tstruct\tphydm_api_stuc\t\tapi_table;\n#ifdef PHYDM_POWER_TRAINING_SUPPORT\n\tstruct\tphydm_pow_train_stuc\tpow_train_table;\n#endif\n\n#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT\n\tstruct phydm_pmac_tx dm_pmac_tx_table;\n#endif\n\n#ifdef PHYDM_MP_SUPPORT\n\tstruct phydm_mp dm_mp_table;\n#endif\n/*@==========================================================*/\n\n#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT)\n\t/*@-------------------phydm_phystatus report --------------------*/\n\tstruct phydm_physts dm_physts_table;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\n#if (RT_PLATFORM != PLATFORM_LINUX)\n} dm_struct;\t/*@DM_Dynamic_Mechanism_Structure*/\n#else\n};\n#endif\n\n#else\t/*@for AP,CE Team*/\n};\n#endif\n\nenum phydm_adv_ota {\n\tPHYDM_PATHB_1RCCA\t\t= BIT(0),\n\tPHYDM_HP_OTA_SETTING_A\t\t= BIT(1),\n\tPHYDM_HP_OTA_SETTING_B\t\t= BIT(2),\n\tPHYDM_ASUS_OTA_SETTING\t\t= BIT(3),\n\tPHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4),\n\tPHYDM_HP_OTA_SETTING_CCK_PATH\t= BIT(5),\n\tPHYDM_LENOVO_OTA_SETTING_NBI_CSI = BIT(6),\n\n};\n\nenum phydm_bb_op_mode {\n\tPHYDM_PERFORMANCE_MODE\t= 0,\t\t/*Service one device*/\n\tPHYDM_BALANCE_MODE\t= 1,\t\t/*@Service more than one device*/\n};\n\nenum phydm_structure_type {\n\tPHYDM_FALSEALMCNT,\n\tPHYDM_CFOTRACK,\n\tPHYDM_ADAPTIVITY,\n\tPHYDM_DFS,\n\tPHYDM_ROMINFO,\n\n};\n\nenum odm_bb_config_type {\n\tCONFIG_BB_PHY_REG,\n\tCONFIG_BB_AGC_TAB,\n\tCONFIG_BB_AGC_TAB_2G,\n\tCONFIG_BB_AGC_TAB_5G,\n\tCONFIG_BB_PHY_REG_PG,\n\tCONFIG_BB_PHY_REG_MP,\n\tCONFIG_BB_AGC_TAB_DIFF,\n\tCONFIG_BB_RF_CAL_INIT,\n};\n\nenum odm_rf_config_type {\n\tCONFIG_RF_RADIO,\n\tCONFIG_RF_TXPWR_LMT,\n\tCONFIG_RF_SYN_RADIO,\n};\n\nenum odm_fw_config_type {\n\tCONFIG_FW_NIC,\n\tCONFIG_FW_NIC_2,\n\tCONFIG_FW_AP,\n\tCONFIG_FW_AP_2,\n\tCONFIG_FW_MP,\n\tCONFIG_FW_WOWLAN,\n\tCONFIG_FW_WOWLAN_2,\n\tCONFIG_FW_AP_WOWLAN,\n\tCONFIG_FW_BT,\n};\n\n/*status code*/\n#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)\nenum rt_status {\n\tRT_STATUS_SUCCESS,\n\tRT_STATUS_FAILURE,\n\tRT_STATUS_PENDING,\n\tRT_STATUS_RESOURCE,\n\tRT_STATUS_INVALID_CONTEXT,\n\tRT_STATUS_INVALID_PARAMETER,\n\tRT_STATUS_NOT_SUPPORT,\n\tRT_STATUS_OS_API_FAILED,\n};\n#endif\t/*@end of enum rt_status definition*/\n\nvoid\nphydm_watchdog_lps(struct dm_struct *dm);\n\nvoid\nphydm_watchdog_lps_32k(struct dm_struct *dm);\n\nvoid\nphydm_txcurrentcalibration(struct dm_struct *dm);\n\nvoid\nphydm_dm_early_init(struct dm_struct *dm);\n\nvoid\nodm_dm_init(struct dm_struct *dm);\n\nvoid\nodm_dm_reset(struct dm_struct *dm);\n\nvoid\nphydm_fwoffload_ability_init(struct dm_struct *dm,\n\t\t\t     enum phydm_offload_ability offload_ability);\n\nvoid\nphydm_fwoffload_ability_clear(struct dm_struct *dm,\n\t\t\t      enum phydm_offload_ability offload_ability);\n\nvoid\nphydm_supportability_en(void *dm_void, char input[][16], u32 *_used,\n\t\t\tchar *output, u32 *_out_len);\n\nvoid\nphydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type);\n\nvoid\nphydm_watchdog(struct dm_struct *dm);\n\nvoid\nphydm_watchdog_mp(struct dm_struct *dm);\n\nu8\nphydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,\n\t\t enum phydm_pause_type pause_type,\n\t\t enum phydm_pause_level pause_lv, u8 val_lehgth, u32 *val_buf);\n\nvoid\nphydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,\n\t\t\t char *output, u32 *_out_len);\n\nvoid\nodm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, u64 value);\n\nvoid\nodm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info, void *value);\n\nvoid\nodm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value);\n\nu32\nphydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type);\n\nvoid\nodm_init_all_timers(struct dm_struct *dm);\n\nvoid\nodm_cancel_all_timers(struct dm_struct *dm);\n\nvoid\nodm_release_all_timers(struct dm_struct *dm);\n\nvoid *\nphydm_get_structure(struct dm_struct *dm, u8 structure_type);\n\nvoid\nphydm_dc_cancellation(struct dm_struct *dm);\n\nvoid\nphydm_receiver_blocking(void *dm_void);\n\nvoid\nphydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en);\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid\nodm_init_all_work_items(\n\tstruct dm_struct\t*dm\n);\nvoid\nodm_free_all_work_items(\n\tstruct dm_struct\t*dm\n);\n#endif\t/*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\nvoid\nodm_dtc(struct dm_struct *dm);\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\nvoid\nodm_init_all_threads(\n\tstruct dm_struct\t*dm\n);\n\nvoid\nodm_stop_all_threads(\n\tstruct dm_struct\t*dm\n);\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm.mk",
    "content": "EXTRA_CFLAGS += -I$(src)/hal/phydm\n\n_PHYDM_FILES := hal/phydm/phydm_debug.o\t\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_antdiv.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_soml.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_smt_ant.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_antdect.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_interface.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_phystatus.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_hwconfig.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_dig.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_pathdiv.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_rainfo.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_dynamictxpower.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_adaptivity.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_cfotracking.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_noisemonitor.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_beamforming.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_direct_bf.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_dfs.o\\\n\t\t\t\t\t\t\t\thal/phydm/txbf/halcomtxbf.o\\\n\t\t\t\t\t\t\t\thal/phydm/txbf/haltxbfinterface.o\\\n\t\t\t\t\t\t\t\thal/phydm/txbf/phydm_hal_txbf_api.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_adc_sampling.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_ccx.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_psd.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_primary_cca.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_cck_pd.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_rssi_monitor.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_auto_dbg.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_math_lib.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_api.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_pow_train.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_lna_sat.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_pmac_tx_setting.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_mp.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/halrf.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/halrf_debug.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/halphyrf_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/halrf_powertracking_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/halrf_powertracking.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/halrf_kfree.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/halrf_psd.o\n\t\t\nifeq ($(CONFIG_RTL8188E), y)\nRTL871X = rtl8188e\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8188e_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8188e_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8188e.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/hal8188erateadaptive.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8188e.o\nendif\n\nifeq ($(CONFIG_RTL8192E), y)\nRTL871X = rtl8192e\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8192e_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8192e_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8192e.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8192e.o\nendif\n\n\nifeq ($(CONFIG_RTL8812A), y)\nRTL871X = rtl8812a\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8812a_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8812a_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8812a.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8812a.o\\\n\t\t\t\t\t\t\t\thal/phydm/txbf/haltxbfjaguar.o\nendif\n\nifeq ($(CONFIG_RTL8821A), y)\nRTL871X = rtl8821a\n_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/rtl8821a/halhwimg8821a_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/rtl8821a/halhwimg8821a_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/rtl8821a/phydm_regconfig8821a.o\\\n\t\t\t\t\t\t\t\thal/phydm/rtl8821a/phydm_rtl8821a.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/txbf/haltxbfjaguar.o\nendif\n\n\nifeq ($(CONFIG_RTL8723B), y)\nRTL871X = rtl8723b\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8723b_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8723b_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8723b_mp.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8723b.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8723b.o\nendif\n\n\nifeq ($(CONFIG_RTL8814A), y)\nRTL871X = rtl8814a\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8814a_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8814a_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8814a.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8814a.o\\\n\t\t\t\t\t\t\t\thal/phydm/txbf/haltxbf8814a.o\nendif\n\n\nifeq ($(CONFIG_RTL8723C), y)\nRTL871X = rtl8703b\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8703b_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8703b_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8703b.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8703b.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8703b.o\nendif\n\nifeq ($(CONFIG_RTL8723D), y)\nRTL871X = rtl8723d\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8723d_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8723d_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8723d.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8723d.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8723d.o\nendif\n\n\nifeq ($(CONFIG_RTL8710B), y)\nRTL871X = rtl8710b\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8710b_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8710b.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8710b.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halhwimg8710b_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8710b.o\nendif\n\n\nifeq ($(CONFIG_RTL8188F), y)\nRTL871X = rtl8188f\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8188f_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8188f_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8188f.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8188f.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8188f.o\nendif\n\nifeq ($(CONFIG_RTL8822B), y)\nRTL871X = rtl8822b\n_PHYDM_FILES +=\thal/phydm/$(RTL871X)/halhwimg8822b_bb.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8822b_mac.o \\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8822b.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_hal_api8822b.o \\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halhwimg8822b_rf.o \\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8822b.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8822b.o\n\n_PHYDM_FILES +=\thal/phydm/txbf/haltxbf8822b.o\nendif\n\n\nifeq ($(CONFIG_RTL8821C), y)\nRTL871X = rtl8821c\n_PHYDM_FILES +=\thal/phydm/$(RTL871X)/halhwimg8821c_bb.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8821c_mac.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_hal_api8821c.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8821c.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halhwimg8821c_rf.o \\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8821c.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o\nendif\nifeq ($(CONFIG_RTL8192F), y)\nRTL871X = rtl8192f\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8192f_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_hal_api8192f.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8192f.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8192f.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halhwimg8192f_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8192f.o\t\nendif\n\nifeq ($(CONFIG_RTL8198F), y)\nRTL871X = rtl8198f\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8198f_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_hal_api8198f.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8198f.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halhwimg8198f_rf.o\nendif\n\nifeq ($(CONFIG_RTL8822C), y)\nRTL871X = rtl8822c\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822c_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_hal_api8822c.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8822c.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8822c.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8822c.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_iqk_8822c.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_tssi_8822c.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_dpk_8822c.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822c.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halhwimg8822c_rf.o\nendif\n\nifeq ($(CONFIG_RTL8814B), y)\nRTL871X = rtl8814b\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814b_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8814b_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_hal_api8814b.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8814b.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halhwimg8814b_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8814b.o \\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_iqk_8814b.o \\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_dpk_8814b.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8814b.o\nendif"
  },
  {
    "path": "hal/phydm/phydm_adaptivity.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n ************************************************************/\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t#if WPP_SOFTWARE_TRACE\n\t\t#include \"PhyDM_Adaptivity.tmh\"\n\t#endif\n#endif\n#ifdef PHYDM_SUPPORT_ADAPTIVITY\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nboolean\nphydm_check_channel_plan(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_adaptivity_struct *adapt = &dm->adaptivity;\n\tvoid *adapter = dm->adapter;\n\tPMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;\n\n\tif (mgnt_info->RegEnableAdaptivity != 2)\n\t\treturn false;\n\n\tif (!dm->carrier_sense_enable) { /*@check domain Code for adaptivity or CarrierSense*/\n\t\tif ((*dm->band_type == ODM_BAND_5G) &&\n\t\t    !(adapt->regulation_5g == REGULATION_ETSI || adapt->regulation_5g == REGULATION_WW)) {\n\t\t\tPHYDM_DBG(dm, DBG_ADPTVTY,\n\t\t\t\t  \"adaptivity skip 5G domain code : %d\\n\",\n\t\t\t\t  adapt->regulation_5g);\n\t\t\treturn true;\n\t\t} else if ((*dm->band_type == ODM_BAND_2_4G) &&\n\t\t\t   !(adapt->regulation_2g == REGULATION_ETSI || adapt->regulation_2g == REGULATION_WW)) {\n\t\t\tPHYDM_DBG(dm, DBG_ADPTVTY,\n\t\t\t\t  \"adaptivity skip 2.4G domain code : %d\\n\",\n\t\t\t\t  adapt->regulation_2g);\n\t\t\treturn true;\n\t\t} else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) {\n\t\t\tPHYDM_DBG(dm, DBG_ADPTVTY,\n\t\t\t\t  \"adaptivity neither 2G nor 5G band, return\\n\");\n\t\t\treturn true;\n\t\t}\n\t} else {\n\t\tif ((*dm->band_type == ODM_BAND_5G) &&\n\t\t    !(adapt->regulation_5g == REGULATION_MKK || adapt->regulation_5g == REGULATION_WW)) {\n\t\t\tPHYDM_DBG(dm, DBG_ADPTVTY,\n\t\t\t\t  \"CarrierSense skip 5G domain code : %d\\n\",\n\t\t\t\t  adapt->regulation_5g);\n\t\t\treturn true;\n\t\t} else if ((*dm->band_type == ODM_BAND_2_4G) &&\n\t\t\t   !(adapt->regulation_2g == REGULATION_MKK || adapt->regulation_2g == REGULATION_WW)) {\n\t\t\tPHYDM_DBG(dm, DBG_ADPTVTY,\n\t\t\t\t  \"CarrierSense skip 2.4G domain code : %d\\n\",\n\t\t\t\t  adapt->regulation_2g);\n\t\t\treturn true;\n\t\t} else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) {\n\t\t\tPHYDM_DBG(dm, DBG_ADPTVTY,\n\t\t\t\t  \"CarrierSense neither 2G nor 5G band, return\\n\");\n\t\t\treturn true;\n\t\t}\n\t}\n\n\treturn false;\n}\n\nboolean\nphydm_soft_ap_special_set(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_adaptivity_struct *adapt = &dm->adaptivity;\n\tu8 disable_ap_adapt_setting = false;\n\n\tif (dm->soft_ap_mode != NULL) {\n\t\tif (*dm->soft_ap_mode != 0 &&\n\t\t    (dm->soft_ap_special_setting & BIT(0)))\n\t\t\tdisable_ap_adapt_setting = true;\n\t\telse\n\t\t\tdisable_ap_adapt_setting = false;\n\t\tPHYDM_DBG(dm, DBG_ADPTVTY,\n\t\t\t  \"soft_ap_setting = %x, soft_ap = %d, dis_ap_adapt = %d\\n\",\n\t\t\t  dm->soft_ap_special_setting, *dm->soft_ap_mode,\n\t\t\t  disable_ap_adapt_setting);\n\t}\n\n\treturn disable_ap_adapt_setting;\n}\n\nboolean\nphydm_ap_num_check(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_adaptivity_struct *adapt = &dm->adaptivity;\n\tboolean dis_adapt = false;\n\n\tif  (dm->ap_total_num > adapt->ap_num_th) {\n\t\tdis_adapt = true;\n\t\tPHYDM_DBG(dm, DBG_ADPTVTY, \"AP total num > %d, disable adapt\\n\",\n\t\t\t  adapt->ap_num_th);\n\t} else {\n\t\tdis_adapt = false;\n\t}\n\treturn dis_adapt;\n}\n\nvoid phydm_set_l2h_th_ini_win(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\t /*@ [New Format: JGR3]IGI-idx:45 = RSSI:35 = -65dBm*/\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tif (dm->support_ic_type & ODM_RTL8822C)\n\t\t\tdm->th_l2h_ini = 45;\n\t\telse if (dm->support_ic_type & ODM_RTL8814B)\n\t\t\tdm->th_l2h_ini = 49;\n\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t /*@ [Old Format] -11+base(50) = IGI_idx:39 = RSSI:29 = -71dBm*/\n\t\tif (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812)) {\n\t\t\tdm->th_l2h_ini = -17;\n\t\t} else {\n\t\t\tif (*dm->band_type == ODM_BAND_5G)\n\t\t\t\tdm->th_l2h_ini = -14;\n\t\t\telse if (*dm->band_type == ODM_BAND_2_4G)\n\t\t\t\tdm->th_l2h_ini = -9;\n\t\t}\n\t} else { /*ODM_IC_11N_SERIES*/\n\t\tdm->th_l2h_ini = -9;\n\t}\n}\n#endif\n\nvoid phydm_dig_up_bound_lmt_en(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_adaptivity_struct *adapt = &dm->adaptivity;\n\n\tif (!(dm->support_ability & ODM_BB_ADAPTIVITY) ||\n\t    !dm->is_linked ||\n\t    !adapt->is_adapt_en) {\n\t\tadapt->igi_up_bound_lmt_cnt = 0;\n\t\tadapt->igi_lmt_en = false;\n\t\treturn;\n\t}\n\n\tif (dm->total_tp > 1) {\n\t\tadapt->igi_lmt_en = true;\n\t\tadapt->igi_up_bound_lmt_cnt = adapt->igi_up_bound_lmt_val;\n\t\tPHYDM_DBG(dm, DBG_ADPTVTY,\n\t\t\t  \"TP >1, Start limit IGI upper bound\\n\");\n\t} else {\n\t\tif (adapt->igi_up_bound_lmt_cnt == 0)\n\t\t\tadapt->igi_lmt_en = false;\n\t\telse\n\t\t\tadapt->igi_up_bound_lmt_cnt--;\n\t}\n\n\tPHYDM_DBG(dm, DBG_ADPTVTY, \"IGI_lmt_cnt = %d\\n\",\n\t\t  adapt->igi_up_bound_lmt_cnt);\n}\n\nvoid phydm_check_adaptivity(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_adaptivity_struct *adapt = &dm->adaptivity;\n\n\tif (!(dm->support_ability & ODM_BB_ADAPTIVITY)) {\n\t\tadapt->is_adapt_en = false;\n\t\tPHYDM_DBG(dm, DBG_ADPTVTY, \"adaptivity disable\\n\");\n\t\treturn;\n\t}\n\n\tadapt->is_adapt_en = true;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tif (phydm_check_channel_plan(dm) ||\n\t    phydm_ap_num_check(dm) ||\n\t    phydm_soft_ap_special_set(dm))\n\t\tadapt->is_adapt_en = false;\n#endif\n}\n\nvoid phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\todm_set_bb_reg(dm, R_0x84c, MASKBYTE2, (u8)L2H + 0x80);\n\t\todm_set_bb_reg(dm, R_0x84c, MASKBYTE3, (u8)H2L + 0x80);\n\t} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\todm_set_bb_reg(dm, R_0xc4c, MASKBYTE0, (u8)L2H);\n\t\todm_set_bb_reg(dm, R_0xc4c, MASKBYTE2, (u8)H2L);\n\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\todm_set_bb_reg(dm, R_0x8a4, MASKBYTE0, (u8)L2H);\n\t\todm_set_bb_reg(dm, R_0x8a4, MASKBYTE1, (u8)H2L);\n\t}\n}\n\nvoid phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (state == PHYDM_IGNORE_EDCCA) {\n\t\todm_set_mac_reg(dm, R_0x520, BIT(15), 1); /*@ignore EDCCA*/\n#if 0\n\t\t/*odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 0);*/\n#endif\n\t} else { /*@don't set MAC ignore EDCCA signal*/\n\t\todm_set_mac_reg(dm, R_0x520, BIT(15), 0); /*@don't ignore EDCCA*/\n#if 0\n\t\t/*odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 1);*/\n#endif\n\t}\n\tPHYDM_DBG(dm, DBG_ADPTVTY, \"EDCCA enable state = %d\\n\", state);\n}\n\nvoid phydm_search_pwdb_lower_bound(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_adaptivity_struct *adapt = &dm->adaptivity;\n\tu32 value32 = 0, reg_value32 = 0;\n\tu8 cnt = 0, try_count = 0;\n\tu8 tx_edcca1 = 0;\n\tboolean is_adjust = true;\n\ts8 th_l2h_dmc, th_h2l_dmc, igi_target = 0x32;\n\ts8 diff = 0;\n\ts8 IGI = adapt->igi_base + 30 + dm->th_l2h_ini - dm->th_edcca_hl_diff;\n\n\thalrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);\n\tdiff = igi_target - IGI;\n\tth_l2h_dmc = dm->th_l2h_ini + diff;\n\tif (th_l2h_dmc > 10)\n\t\tth_l2h_dmc = 10;\n\n\tth_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;\n\tphydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);\n\tODM_delay_ms(30);\n\n\twhile (is_adjust) {\n\t\t/*@check CCA status*/\n\t\t/*set debug port to 0x0*/\n\t\tif (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) {\n\t\t\treg_value32 = phydm_get_bb_dbg_port_val(dm);\n\n\t\t\twhile (reg_value32 & BIT(3) && try_count < 3) {\n\t\t\t\tODM_delay_ms(3);\n\t\t\t\ttry_count = try_count + 1;\n\t\t\t\treg_value32 = phydm_get_bb_dbg_port_val(dm);\n\t\t\t}\n\t\t\tphydm_release_bb_dbg_port(dm);\n\t\t\ttry_count = 0;\n\t\t}\n\n\t\t/*@count EDCCA signal = 1 times*/\n\t\tfor (cnt = 0; cnt < 20; cnt++) {\n\t\t\tif (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1,\n\t\t\t\t\t\t  adapt->adaptivity_dbg_port)) {\n\t\t\t\tvalue32 = phydm_get_bb_dbg_port_val(dm);\n\t\t\t\tphydm_release_bb_dbg_port(dm);\n\t\t\t}\n\n\t\t\tif (value32 & BIT(30) && dm->support_ic_type &\n\t\t\t\t\t\t (ODM_RTL8723B | ODM_RTL8188E))\n\t\t\t\ttx_edcca1 = tx_edcca1 + 1;\n\t\t\telse if (value32 & BIT(29))\n\t\t\t\ttx_edcca1 = tx_edcca1 + 1;\n\t\t}\n\n\t\tif (tx_edcca1 > 1) {\n\t\t\tIGI = IGI - 1;\n\t\t\tth_l2h_dmc = th_l2h_dmc + 1;\n\t\t\tif (th_l2h_dmc > 10)\n\t\t\t\tth_l2h_dmc = 10;\n\n\t\t\tth_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;\n\t\t\tphydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);\n\t\t\ttx_edcca1 = 0;\n\t\t\tif (th_l2h_dmc == 10)\n\t\t\t\tis_adjust = false;\n\n\t\t} else {\n\t\t\tis_adjust = false;\n\t\t}\n\t}\n\n\tadapt->adapt_igi_up = IGI - ADAPT_DC_BACKOFF;\n\tadapt->h2l_lb = th_h2l_dmc + ADAPT_DC_BACKOFF;\n\tadapt->l2h_lb = th_l2h_dmc + ADAPT_DC_BACKOFF;\n\n\thalrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);\n\tphydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/\n}\n\nboolean\nphydm_re_search_condition(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;\n\tu8 adaptivity_igi_upper = adaptivity->adapt_igi_up + ADAPT_DC_BACKOFF;\n\n\tif (adaptivity_igi_upper <= 0x26)\n\t\treturn true;\n\telse\n\t\treturn false;\n}\n\nvoid phydm_set_l2h_th_ini(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\tif (dm->support_ic_type &\n\t\t    (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A))\n\t\t\tdm->th_l2h_ini = 0xf2;\n\t\telse\n\t\t\tdm->th_l2h_ini = 0xef;\n\t} else  if (dm->support_ic_type & ODM_RTL8822C) {\n\t\tdm->th_l2h_ini = 0x2d;\n\t} else  if (dm->support_ic_type & ODM_RTL8814B) {\n\t\tdm->th_l2h_ini = 0x31;\n\t} else {\n\t\tdm->th_l2h_ini = 0xf5;\n\t}\n}\n\nvoid phydm_set_l2h_th_ini_carrier_sense(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tdm->th_l2h_ini = 0x3c;\n\telse\n\t\tdm->th_l2h_ini = 0xa;\n}\n\nvoid phydm_set_forgetting_factor(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ability & ODM_BB_ADAPTIVITY) {\n\t\tif (dm->support_ic_type &\n\t\t    (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A))\n\t\t\todm_set_bb_reg(dm, R_0x8a0, BIT(1) | BIT(0), 0);\n\t}\n}\n\nvoid phydm_set_pwdb_mode(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ability & ODM_BB_ADAPTIVITY) {\n\t\tif (dm->support_ic_type & ODM_RTL8822B)\n\t\t\todm_set_bb_reg(dm, R_0x8dc, BIT(5), 0x1);\n\t\telse if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))\n\t\t\todm_set_bb_reg(dm, R_0xce8, BIT(13), 0x1);\n\t\telse if (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\t\todm_set_bb_reg(dm, R_0x844, BIT(30) | BIT(29), 0x0);\n\t}\n}\n\nvoid phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t\t    char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tchar help[] = \"-h\";\n\tu32 dm_value[10] = {0};\n\tu8 i = 0, input_idx = 0;\n\tu32 reg_value32 = 0;\n\ts8 h2l_diff = 0;\n\n\tfor (i = 0; i < 5; i++) {\n\t\tif (input[i + 1]) {\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);\n\t\t\tinput_idx++;\n\t\t}\n\t}\n\tif (strcmp(input[1], help) == 0) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Show adaptivity message: {0}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Enter debug mode: {1} {th_l2h_ini} {th_edcca_hl_diff}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Leave debug mode: {2}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Disable EDCCA thr: {3}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Enable EDCCA thr: {4}\\n\");\n\t\tgoto out;\n\t}\n\n\tif (input_idx == 0)\n\t\treturn;\n\n\tif (dm_value[0] == PHYDM_ADAPT_DEBUG) {\n\t\tadaptivity->debug_mode = true;\n\t\tif (dm_value[1] != 0)\n\t\t\tdm->th_l2h_ini = (s8)dm_value[1];\n\t\tif (dm_value[2] != 0)\n\t\t\tdm->th_edcca_hl_diff = (s8)dm_value[2];\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"th_l2h_ini = %d, th_edcca_hl_diff = %d\\n\",\n\t\t\t dm->th_l2h_ini, dm->th_edcca_hl_diff);\n\t} else if (dm_value[0] == PHYDM_ADAPT_RESUME) {\n\t\tadaptivity->debug_mode = false;\n\t\tdm->th_l2h_ini = adaptivity->th_l2h_ini_backup;\n\t\tdm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup;\n\t} else if (dm_value[0] == PHYDM_EDCCA_TH_PAUSE) {\n\t\tadaptivity->edcca_en = false;\n\t} else if (dm_value[0] == PHYDM_EDCCA_TH_RESUME) {\n\t\tadaptivity->edcca_en = true;\n\t} else if (dm_value[0] == PHYDM_ADAPT_MSG) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"debug_mode = %s, th_l2h_ini = %d\\n\",\n\t\t\t (adaptivity->debug_mode ? \"TRUE\" : \"FALSE\"),\n\t\t\t dm->th_l2h_ini);\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t\treg_value32 = odm_get_bb_reg(dm, R_0x84c, MASKDWORD);\n\t\t\th2l_diff = (s8)((0x00ff0000 & reg_value32) >> 16) -\n\t\t\t\t   (s8)((0xff000000 & reg_value32) >> 24);\n\t\t} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\t\treg_value32 = odm_get_bb_reg(dm, R_0xc4c, MASKDWORD);\n\t\t\th2l_diff = (s8)(0x000000ff & reg_value32) -\n\t\t\t\t   (s8)((0x00ff0000 & reg_value32) >> 16);\n\t\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\t\treg_value32 = odm_get_bb_reg(dm, R_0x8a4, MASKDWORD);\n\t\t\th2l_diff = (s8)(0x000000ff & reg_value32) -\n\t\t\t\t   (s8)((0x0000ff00 & reg_value32) >> 8);\n\t\t}\n\n\t\tif (h2l_diff == 7)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"adaptivity enable\\n\");\n\t\telse\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"adaptivity disable\\n\");\n\t}\n\nout:\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (val_len != 2) {\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"[Error][adaptivity]Need val_len = 2\\n\");\n\t\treturn;\n\t}\n\tphydm_set_edcca_threshold(dm, (s8)val_buf[1], (s8)val_buf[0]);\n}\n\nboolean phydm_edcca_abort(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_adaptivity_struct *adapt = &dm->adaptivity;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tu32 is_fw_in_psmode = false;\n#endif\n\n\tif (dm->pause_ability & ODM_BB_ADAPTIVITY) {\n\t\tPHYDM_DBG(dm, DBG_ADPTVTY, \"Return: Pause ADPTVTY in LV=%d\\n\",\n\t\t\t  dm->pause_lv_table.lv_adapt);\n\t\treturn true;\n\t}\n\n\tif (!adapt->edcca_en) {\n\t\tPHYDM_DBG(dm, DBG_ADPTVTY, \"Disable EDCCA!!!\\n\");\n\t\treturn true;\n\t}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t((PADAPTER)adapter)->HalFunc.GetHwRegHandler(adapter,\n\t\t\t\t\t\t      HW_VAR_FW_PSMODE_STATUS,\n\t\t\t\t\t\t      (u8 *)(&is_fw_in_psmode));\n\n\t/*@Disable EDCCA while under LPS mode, added by Roger, 2012.09.14.*/\n\tif (is_fw_in_psmode)\n\t\treturn true;\n#endif\n\n\treturn false;\n}\n#endif\nvoid phydm_set_edcca_threshold_api(void *dm_void, u8 IGI)\n{\n#ifdef PHYDM_SUPPORT_ADAPTIVITY\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;\n\ts8 th_l2h_dmc = 0, th_h2l_dmc = 0;\n\ts8 diff = 0, igi_target = 0x32;\n\n\tif (dm->support_ability & ODM_BB_ADAPTIVITY) {\n\t\tif (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {\n\t\t\tif (adaptivity->adjust_l2h > IGI)\n\t\t\t\tdiff = adaptivity->adjust_l2h - IGI;\n\n\t\t\tth_l2h_dmc = dm->th_l2h_ini - diff + igi_target;\n\t\t\tth_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;\n\t\t} else {\n\t\t\tdiff = igi_target - (s8)IGI;\n\t\t\tth_l2h_dmc = dm->th_l2h_ini + diff;\n\t\t\tif (th_l2h_dmc > 10)\n\t\t\t\tth_l2h_dmc = 10;\n\n\t\t\tth_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;\n\n\t\t\t/*replace lower bound to prevent EDCCA always equal 1*/\n\t\t\tif (th_h2l_dmc < adaptivity->h2l_lb)\n\t\t\t\tth_h2l_dmc = adaptivity->h2l_lb;\n\t\t\tif (th_l2h_dmc < adaptivity->l2h_lb)\n\t\t\t\tth_l2h_dmc = adaptivity->l2h_lb;\n\t\t}\n\n\t\tPHYDM_DBG(dm, DBG_ADPTVTY,\n\t\t\t  \"API :IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\\n\",\n\t\t\t  IGI, th_l2h_dmc, th_h2l_dmc);\n\n\t\tphydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);\n\t}\n#endif\n}\n\nvoid phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,\n\t\t\t\tu32 value)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;\n\n\tswitch (cmn_info) {\n\tcase PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:\n\t\tdm->carrier_sense_enable = (boolean)value;\n\t\tbreak;\n\tcase PHYDM_ADAPINFO_TH_L2H_INI:\n\t\tdm->th_l2h_ini = (s8)value;\n\t\tbreak;\n\tcase PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:\n\t\tdm->th_edcca_hl_diff = (s8)value;\n\t\tbreak;\n\tcase PHYDM_ADAPINFO_AP_NUM_TH:\n\t\tadaptivity->ap_num_th = (u8)value;\n\t\tbreak;\n\tcase PHYDM_ADAPINFO_SWITCH_TH_L2H_INI_IN_BAND:\n\t\tadaptivity->switch_th_l2h_ini_in_band = (u8)value;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info,\n\t\t\t\t  u32 value)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_adaptivity_struct *adapt = &dm->adaptivity;\n\n\t/*This init variable may be changed in run time.*/\n\tswitch (cmn_info) {\n\tcase PHYDM_ADAPINFO_DOMAIN_CODE_2G:\n\t\tadapt->regulation_2g = (u8)value;\n\t\tbreak;\n\tcase PHYDM_ADAPINFO_DOMAIN_CODE_5G:\n\t\tadapt->regulation_5g = (u8)value;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid phydm_adaptivity_init(void *dm_void)\n{\n#ifdef PHYDM_SUPPORT_ADAPTIVITY\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))\n\n\tif (!dm->carrier_sense_enable) {\n\t\tif (dm->th_l2h_ini == 0 &&\n\t\t    !adaptivity->switch_th_l2h_ini_in_band)\n\t\t\tphydm_set_l2h_th_ini(dm);\n\t} else {\n\t\tphydm_set_l2h_th_ini_carrier_sense(dm);\n\t}\n\n\tif (dm->th_edcca_hl_diff == 0)\n\t\tdm->th_edcca_hl_diff = 7;\n#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))\n\tif (dm->wifi_test || *dm->mp_mode)\n#else\n\tif (dm->wifi_test & RT_WIFI_LOGO) /*@AP side use mib control*/\n#endif\n\t\t/*@even no adaptivity, we still enable EDCCA*/\n\t\tadaptivity->edcca_en = false;\n\telse\n\t\tadaptivity->edcca_en = true;\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\tif (dm->carrier_sense_enable) {\n\t\tphydm_set_l2h_th_ini_carrier_sense(dm);\n\t\tdm->th_edcca_hl_diff = 7;\n\t} else {\n\t\tdm->th_l2h_ini = dm->TH_L2H_default; /*set by mib*/\n\t\tdm->th_edcca_hl_diff = dm->th_edcca_hl_diff_default;\n\t}\n\n\tadaptivity->edcca_en = true;\n#endif\n\n\tadaptivity->is_adapt_en = false; /*@decide enable or not*/\n\tadaptivity->debug_mode = false;\n\tadaptivity->th_l2h_ini_backup = dm->th_l2h_ini;\n\tadaptivity->th_edcca_hl_diff_backup = dm->th_edcca_hl_diff;\n\tadaptivity->igi_base = 0x32;\n\tadaptivity->adapt_igi_up = 0;\n\tadaptivity->h2l_lb = 0;\n\tadaptivity->l2h_lb = 0;\n\tadaptivity->adjust_l2h = 0;\n\tadaptivity->th_l2h = 0x7f;\n\tadaptivity->th_h2l = 0x7f;\n\tphydm_mac_edcca_state(dm, PHYDM_DONT_IGNORE_EDCCA);\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tadaptivity->adaptivity_dbg_port = 0x000;\n\t\todm_set_bb_reg(dm, R_0x1d6c, BIT(0), 1);\n\t} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\tadaptivity->adaptivity_dbg_port = 0x208;\n\t} else {\n\t\tadaptivity->adaptivity_dbg_port = 0x209;\n\t}\n\tif (dm->support_ic_type & ODM_IC_11N_SERIES &&\n\t    !(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {\n\t\t/*@interfernce need > 2^x us, and then EDCCA will be 1*/\n#if 0\n\t\t/*odm_set_bb_reg(dm, 0x948, 0x1c00, 0x7);*/\n#endif\n\t\tif (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) {\n\t\t\t/*set to page B1*/\n\t\t\todm_set_bb_reg(dm, R_0xe28, BIT(30), 0x1);\n\t\t\t/*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/\n\t\t\todm_set_bb_reg(dm, R_0xbc0, BIT(27) | BIT(26), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0xe28, BIT(30), 0x0);\n\t\t} else {\n\t\t\t/*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/\n\t\t\todm_set_bb_reg(dm, R_0xe24, BIT(21) | BIT(20), 0x1);\n\t\t}\n\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES &&\n\t\t   !(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {\n\t\t/*@interfernce need > 2^x us, and then EDCCA will be 1*/\n#if 0\n\t\t/*odm_set_bb_reg(dm, 0x900, 0x70000000, 0x7);*/\n#endif\n\t\t/*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/\n\t\todm_set_bb_reg(dm, R_0x944, BIT(29) | BIT(28), 0x1);\n\t}\n\n\tif (dm->support_ic_type & ODM_IC_PWDB_EDCCA) {\n\t\tphydm_search_pwdb_lower_bound(dm);\n\t\tif (phydm_re_search_condition(dm))\n\t\t\tphydm_search_pwdb_lower_bound(dm);\n\t} else {\n\t\t/*resume to no link state*/\n\t\tphydm_set_edcca_threshold(dm, 0x7f, 0x7f);\n\t}\n\n\t/*@forgetting factor setting*/\n\tphydm_set_forgetting_factor(dm);\n\n\t/*pwdb mode setting with 0: mean, 1:max*/\n\tphydm_set_pwdb_mode(dm);\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\tadaptivity->igi_up_bound_lmt_val = 180;\n#else\n\tadaptivity->igi_up_bound_lmt_val = 90;\n#endif\n\tadaptivity->igi_up_bound_lmt_cnt = 0;\n\tadaptivity->igi_lmt_en = false;\n#endif\n}\n\nvoid phydm_adaptivity(void *dm_void)\n{\n#ifdef PHYDM_SUPPORT_ADAPTIVITY\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct phydm_adaptivity_struct *adapt = &dm->adaptivity;\n\tu8 igi = dig_t->cur_ig_value;\n\ts8 th_l2h_dmc = 0, th_h2l_dmc = 0;\n\ts8 diff = 0, igi_target = adapt->igi_base;\n\n\tif (phydm_edcca_abort(dm))\n\t\treturn;\n\n\t/*@fix AC series when enable EDCCA hang issue*/\n\tif (dm->support_ic_type & ODM_RTL8812) {\n\t\todm_set_bb_reg(dm, R_0x800, BIT(10), 1); /*@ADC_mask disable*/\n\t\todm_set_bb_reg(dm, R_0x800, BIT(10), 0); /*@ADC_mask enable*/\n\t}\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tif (!dm->carrier_sense_enable &&\n\t    !adapt->debug_mode &&\n\t    adapt->switch_th_l2h_ini_in_band)\n\t\tphydm_set_l2h_th_ini_win(dm);\n#endif\n\tif (!adapt->debug_mode)\n\t\tphydm_check_adaptivity(dm); /*@Check adaptivity enable*/\n\n\tPHYDM_DBG(dm, DBG_ADPTVTY, \"%s ====>\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_ADPTVTY, \"th_l2h_ini = %d, th_edcca_hl_diff = %d\\n\",\n\t\t  dm->th_l2h_ini, dm->th_edcca_hl_diff);\n\tPHYDM_DBG(dm, DBG_ADPTVTY, \"is_adapt_en = %d, debug_mode = %d\\n\",\n\t\t  adapt->is_adapt_en, adapt->debug_mode);\n\n\tif (dm->support_ic_type & ODM_IC_PWDB_EDCCA) {\n\t\tif (adapt->is_adapt_en) {\n\t\t\t/*@Limit IGI upper bound for adaptivity*/\n\t\t\tphydm_dig_up_bound_lmt_en(dm);\n\t\t\tdiff = igi_target - (s8)igi;\n\t\t\tth_l2h_dmc = dm->th_l2h_ini + diff;\n\t\t\tif (th_l2h_dmc > 10)\n\t\t\t\tth_l2h_dmc = 10;\n\n\t\t\tth_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;\n\t\t} else {\n\t\t\tth_l2h_dmc = 0x46 - igi;\n\t\t\tth_h2l_dmc = th_l2h_dmc - EDCCA_HL_DIFF_NORMAL;\n\t\t}\n\t\t/*replace lower bound to prevent EDCCA always equal 1*/\n\t\tif (th_h2l_dmc < adapt->h2l_lb)\n\t\t\tth_h2l_dmc = adapt->h2l_lb;\n\t\tif (th_l2h_dmc < adapt->l2h_lb)\n\t\t\tth_l2h_dmc = adapt->l2h_lb;\n\t\tPHYDM_DBG(dm, DBG_ADPTVTY,\n\t\t\t  \"adapt_igi_up=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\\n\",\n\t\t\t  adapt->adapt_igi_up, adapt->h2l_lb, adapt->l2h_lb);\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tif (adapt->is_adapt_en) {\n\t\t\t/*need to prevent pwdB clipping*/\n\t\t\tadapt->adjust_l2h = (u8)(dm->th_l2h_ini - ADC_BACKOFF);\n\t\t\tdiff = adapt->adjust_l2h > igi ?\n\t\t\t       adapt->adjust_l2h - igi :\n\t\t\t       0;\n\t\t\tth_l2h_dmc = dm->th_l2h_ini - diff;\n\t\t\tth_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;\n\t\t} else {\n\t\t\tth_l2h_dmc = igi + TH_L2H_DIFF_IGI > EDCCA_TH_L2H_LB ?\n\t\t\t\t     igi + TH_L2H_DIFF_IGI :\n\t\t\t\t     EDCCA_TH_L2H_LB;\n\t\t\tth_h2l_dmc = th_l2h_dmc - EDCCA_HL_DIFF_NORMAL;\n\t\t}\n\t} else {\n\t\tif (adapt->is_adapt_en) {\n\t\t\t/*need to consider PwdB upper bound for 8814 later IC*/\n\t\t\tadapt->adjust_l2h = (u8)(dm->th_l2h_ini + igi_target -\n\t\t\t\t\t    PWDB_UPPER_BOUND + DFIR_LOSS);\n\t\t\tdiff = adapt->adjust_l2h > igi ?\n\t\t\t       adapt->adjust_l2h - igi :\n\t\t\t       0;\n\t\t\tth_l2h_dmc = dm->th_l2h_ini - diff + igi_target;\n\t\t\tth_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;\n\t\t} else {\n\t\t\tth_l2h_dmc = igi + TH_L2H_DIFF_IGI > EDCCA_TH_L2H_LB ?\n\t\t\t\t     igi + TH_L2H_DIFF_IGI :\n\t\t\t\t     EDCCA_TH_L2H_LB;\n\t\t\tth_h2l_dmc = th_l2h_dmc - EDCCA_HL_DIFF_NORMAL;\n\t\t}\n\t}\n\n\tadapt->th_l2h = th_l2h_dmc;\n\tadapt->th_h2l = th_h2l_dmc;\n\tPHYDM_DBG(dm, DBG_ADPTVTY, \"IGI=0x%x, th_l2h_dmc=%d, th_h2l_dmc=%d\\n\",\n\t\t  igi, th_l2h_dmc, th_h2l_dmc);\n\tphydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);\n\n\tif (adapt->is_adapt_en)\n\t\todm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 1);\n\n\treturn;\n#endif\n}\n"
  },
  {
    "path": "hal/phydm/phydm_adaptivity.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDMADAPTIVITY_H__\n#define __PHYDMADAPTIVITY_H__\n\n#define ADAPTIVITY_VERSION \"9.6.07\" /*@20181107 changed by Kevin,\n\t\t\t\t     *remove pwdB mode with non-adaptivity case\n\t\t\t\t     */\n\n#define PWDB_UPPER_BOUND 7\n#define DFIR_LOSS 7\n#define ADC_BACKOFF 12\n#define EDCCA_TH_L2H_LB 0x30\n#define TH_L2H_DIFF_IGI 8\n#define EDCCA_HL_DIFF_NORMAL 8\n\n#define ODM_IC_PWDB_EDCCA (ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |\\\n\t\t\t   ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8812)\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))\n\t#define ADAPT_DC_BACKOFF 2\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t#define ADAPT_DC_BACKOFF 4\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\t#define ADAPT_DC_BACKOFF 0\n#endif\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\nenum phydm_regulation_type {\n\tREGULATION_FCC\t\t= 0,\n\tREGULATION_MKK\t\t= 1,\n\tREGULATION_ETSI\t\t= 2,\n\tREGULATION_WW\t\t= 3,\n\tMAX_REGULATION_NUM\t= 4\n};\n#endif\n\nenum phydm_adapinfo {\n\tPHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,\n\tPHYDM_ADAPINFO_TH_L2H_INI,\n\tPHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,\n\tPHYDM_ADAPINFO_AP_NUM_TH,\n\tPHYDM_ADAPINFO_DOMAIN_CODE_2G,\n\tPHYDM_ADAPINFO_DOMAIN_CODE_5G,\n\tPHYDM_ADAPINFO_SWITCH_TH_L2H_INI_IN_BAND\n};\n\nenum phydm_mac_edcca_type {\n\tPHYDM_IGNORE_EDCCA\t\t= 0,\n\tPHYDM_DONT_IGNORE_EDCCA\t\t= 1\n};\n\nenum phydm_adaptivity_mode {\n\tPHYDM_ADAPT_MSG\t\t\t= 0,\n\tPHYDM_ADAPT_DEBUG\t\t= 1,\n\tPHYDM_ADAPT_RESUME\t\t= 2,\n\tPHYDM_EDCCA_TH_PAUSE\t\t= 3,\n\tPHYDM_EDCCA_TH_RESUME\t\t= 4\n};\n\nstruct phydm_adaptivity_struct {\n\ts8\t\t\tth_l2h_ini_backup;\n\ts8\t\t\tth_edcca_hl_diff_backup;\n\ts8\t\t\tigi_base;\n\ts8\t\t\th2l_lb;\n\ts8\t\t\tl2h_lb;\n\tu8\t\t\tap_num_th;\n\tu8\t\t\tadjust_l2h;\n\tu32\t\t\tadaptivity_dbg_port; /*N:0x208, AC:0x209*/\n\tu8\t\t\tdebug_mode;\n\tu16\t\t\tigi_up_bound_lmt_cnt;\t/*@When igi_up_bound_lmt_cnt !=0, limit IGI upper bound to \"adapt_igi_up\"*/\n\tu16\t\t\tigi_up_bound_lmt_val;\t/*@max value of igi_up_bound_lmt_cnt*/\n\tboolean\t\t\tigi_lmt_en;\n\tu8\t\t\tadapt_igi_up;\n\tu32\t\t\trvrt_val[2];\n\ts8\t\t\tth_l2h;\n\ts8\t\t\tth_h2l;\n\tu8\t\t\tregulation_2g;\n\tu8\t\t\tregulation_5g;\n\tboolean\t\t\tis_adapt_en;\n\tboolean\t\t\tedcca_en;\n\tu8\t\t\tswitch_th_l2h_ini_in_band;\n};\n\n#ifdef PHYDM_SUPPORT_ADAPTIVITY\nvoid phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t\t    char *output, u32 *_out_len);\n\nvoid phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len);\n#endif\n\nvoid phydm_set_edcca_threshold_api(void *dm_void, u8 IGI);\n\nvoid phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,\n\t\t\t\tu32 value);\n\nvoid phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info,\n\t\t\t\t  u32 value);\n\nvoid phydm_adaptivity_init(void *dm_void);\n\nvoid phydm_adaptivity(void *dm_void);\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_adc_sampling.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#if (PHYDM_LA_MODE_SUPPORT)\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\t#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8192F_SUPPORT)\n\t#include \"rtl8197f/Hal8197FPhyReg.h\"\n\t#include \"WlanHAL/HalMac88XX/halmac_reg2.h\"\n\t#else\n\t#include \"WlanHAL/HalHeader/HalComReg.h\"\n\t#endif\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t#if WPP_SOFTWARE_TRACE\n\t#include \"phydm_adc_sampling.tmh\"\n\t#endif\n#endif\n\n#if RTL8814B_SUPPORT\nboolean phydm_la_finish_addr_recover_8814B(void *dm_void, u32 *finish_addr)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tboolean recover_success;\n\n\tif (dm->support_ic_type != ODM_RTL8814B)\n\t\treturn false;\n\n\tif (smp->la_buff_mode == ADCSMP_BUFF_HALF) {\n\t\tif (*finish_addr < 0x4000) /*0~0x4000*/\n\t\t\t*finish_addr += 0x8000;\n\n\t\trecover_success = true;\n\t} else {\n\t\tif (*finish_addr >= 0x4000 && *finish_addr < 0x8000)\n\t\t\trecover_success = true;\n\t\telse\n\t\t\trecover_success = false;\n\t}\n\tpr_debug(\"[8814B] recover_success=(%d)\\n\", recover_success);\n\n\treturn recover_success;\n}\n#endif\n\n#if RTL8198F_SUPPORT\nvoid phydm_la_pre_run(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tstruct rt_adcsmp_string *buf = &smp->adc_smp_buf;\n\tu8 i = 0;\n\tu8 tmp = 0;\n\tu8 target_polling_bit = BIT(1);\n\n\tif (!(dm->support_ic_type & ODM_RTL8198F))\n\t\treturn;\n\n\tif (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG)\n\t\treturn;\n\n\t/*pre run */\n\t/*force to bb trigger*/\n\todm_set_mac_reg(dm, R_0x7c0, BIT(3), 0);\n\t/*dma_trig_and(AND1) output 1*/\n\todm_set_bb_reg(dm, R_0x1ce4, 0xf0000000, 0x0);\n\t/*r_dma_trigger_AND1_inv = 1*/\n\todm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/\n\t/* polling bit for BB ADC mode */\n\todm_set_mac_reg(dm, 0x7c0, BIT(1), 1);\n\n\tpr_debug(\"buf[end:start]=(0x%x~0x%x)\\n\", buf->end_pos, buf->start_pos);\n\n\tdo {\n\t\ttmp = odm_read_1byte(dm, R_0x7c0);\n\t\tif ((tmp & target_polling_bit) == false) {\n\t\t\tpr_debug(\"LA pre-run fail.\\n\");\n\t\t\tphydm_la_stop(dm);\n\t\t\tphydm_release_bb_dbg_port(dm);\n\t\t} else {\n\t\t\tODM_delay_ms(100);\n\t\t\tpr_debug(\"LA pre-run while_cnt = %d.\\n\", i);\n\t\t\ti++;\n\t\t}\n\t} while (i < 3);\n\n\t/*r_dma_trigger_AND1_inv = 0*/\n\todm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/\n\n\tif (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG)\n\t\todm_set_mac_reg(dm, R_0x7c0, BIT(3), 1);\n}\n#endif\n\n#if (RTL8821C_SUPPORT | RTL8195B_SUPPORT)\nvoid\nphydm_la_clk_en(void *dm_void, boolean enable)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 val = (enable) ? 1 : 0;\n\n\tif (!(dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)))\n\t\treturn;\n\n\tif (dm->support_ic_type == ODM_RTL8821C &&\n\t    dm->cut_version == ODM_CUT_A)\n\t\treturn;\n\n\todm_set_bb_reg(dm, R_0x95c, BIT(23), val);\n}\n#endif\n\n#if (RTL8197F_SUPPORT)\nvoid\nphydm_la_stop_dma_8197f(void *dm_void, enum phydm_backup_type opt)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\n\tif (dm->support_ic_type != ODM_RTL8197F)\n\t\treturn;\n\n\tif (opt == PHYDM_BACKUP) {\n\t\t/*Stop DMA*/\n\t\tsmp->backup_dma = odm_get_mac_reg(dm, R_0x300, 0xffff);\n\t\todm_set_mac_reg(dm, R_0x300, 0x7fff, 0x7fff);\n\t} else { /*restore*/\n\t\t/*Resume DMA*/\n\t\todm_set_mac_reg(dm, R_0x300, 0x7fff, smp->backup_dma);\n\t}\n}\n#endif\n\n#ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM\nvoid\nphydm_la_mv_data_2_tx_buffer(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tstruct rt_adcsmp_string *buf = &smp->adc_smp_buf;\n\n\tif (!(dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC))\n\t\treturn;\n\n\tpr_debug(\"98F GetTxPktBuf from iMEM\\n\");\n\todm_set_bb_reg(dm, R_0x7c0, BIT(0), 0x0); /*Disable LA mode HW block*/\n\n\t/* 98F LA memory loccation is separate from normal\n\t * driver use, DMA is no longer required to stop\n\t */\n\t#if (RTL8197F_SUPPORT)\n\tphydm_la_stop_dma_8197f(dm, PHYDM_BACKUP);\n\t#endif\n\n\t/* @move LA mode content from IMEM to TxPktBuffer\n\t * Source : OCPBASE_IMEM 0x00000000\n\t * Destination : OCPBASE_TXBUF 0x18780000\n\t * Length : 64K\n\t */\n\tGET_HAL_INTERFACE(dm->priv)->init_ddma_handler(dm->priv,\n\t\t\t\t\t\t       OCPBASE_IMEM,\n\t\t\t\t\t\t       OCPBASE_TXBUF\n\t\t\t\t\t\t       + buf->start_pos,\n\t\t\t\t\t\t       0x10000);\n}\n#endif\n\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\nvoid phydm_la_bb_adv_reset_jgr3(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tstruct la_adv_trig *adv = &smp->adv_trig_table;\n\n#if 1\n\todm_memory_set(dm, adv, 0, sizeof(struct la_adv_trig));\n#else\n\tadv->la_en_new_bbtrigger = false;\n\tadv->la_ori_bb_dis = false;\n\tadv->la_and1_sel = 0;\n\tadv->la_and1_val = 0;\n\tadv->la_and2_sel = 0;\n\tadv->la_and2_val = 0;\n\tadv->la_and3_sel = 0;\n\tadv->la_and3_val = 0;\n\tadv->la_and4_mask = 0;\n\tadv->la_and4_bitmap = 0;\n#endif\n}\n\nvoid phydm_la_bb_adv_trig_setting_jgr3(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tstruct la_adv_trig *adv = &smp->adv_trig_table;\n\tboolean adv_bb_trig_en = adv->la_en_new_bbtrigger;\n\n\tpr_debug(\" *ADV BB-trig = %d\\n\", adv_bb_trig_en);\n\n\tif (!adv_bb_trig_en) { /*normal LA mode & back to default*/\n\t\t/*@AND0*/\n\t\todm_set_bb_reg(dm, R_0x1ce4, BIT(27), 0);\n\n\t\t/*@AND1*/\n\t\todm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, 0);\n\t\todm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/\n\t\t/*@AND2*/\n\t\todm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0);\n\t\todm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/\n\t\t/*@AND3*/\n\t\todm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0);\n\t\todm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/\n\t\t/*@AND4*/\n\t\todm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, 0); /*@AND 4 mask en*/\n\t\todm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/\n\t} else {\n\t\t/* @AND0 */\n\t\t/*path 1 default: enable ori. BB trigger*/\n\t\todm_set_bb_reg(dm, R_0x1ce4, BIT(27),\n\t\t\t       (adv->la_ori_bb_dis ? 1 : 0));\n\n\t\t/* @AND1 */\n\t\todm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv);\n\t\todm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, adv->la_and1_sel);\n\t\todm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val);\n\n\t\t/* @AND2 */\n\t\todm_set_bb_reg(dm, R_0x1ce8, BIT(15), adv->la_and2_inv);\n\t\todm_set_bb_reg(dm, R_0x1ce8, 0x3c0, adv->la_and2_sel);\n\t\todm_set_bb_reg(dm, R_0x1ce8, 0x7c00, adv->la_and2_val);\n\n\t\t/* @AND3 */\n\t\todm_set_bb_reg(dm, R_0x1ce8, BIT(25), adv->la_and3_inv);\n\t\todm_set_bb_reg(dm, R_0x1ce8, 0xf0000, adv->la_and3_sel);\n\t\todm_set_bb_reg(dm, R_0x1ce8, 0x1f00000, adv->la_and3_val);\n\n\t\t/* @AND4 */\n\t\todm_set_bb_reg(dm, R_0x1ce8, BIT(26), adv->la_and4_inv);\n\t\todm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, adv->la_and4_mask);\n\t\todm_set_bb_reg(dm, R_0x1cec, MASKDWORD, adv->la_and4_bitmap);\n\t}\n}\n\nvoid phydm_la_bb_adv_cmd_show_jgr3(void *dm_void, u32 *_used,\n\t\t\t\t   char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tstruct la_adv_trig *adv = &smp->adv_trig_table;\n\n\tPDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,\n\t\t \"  *And0 Disable=%d\\n\", adv->la_ori_bb_dis);\n\tPDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,\n\t\t \"  *And1{sel,val,inv}={0x%x,0x%x,%d}\\n  *And2{sel,val,inv}={0x%x,0x%x,%d}\\n  *And3{sel,val,inv}={0x%x,0x%x,%d}\\n\",\n\t\t adv->la_and1_sel, adv->la_and1_val, adv->la_and1_inv,\n\t\t adv->la_and2_sel, adv->la_and2_val, adv->la_and2_inv,\n\t\t adv->la_and3_sel, adv->la_and3_val, adv->la_and3_inv);\n\tPDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,\n\t\t \"  *And4{mask,bitmap,inv}={0x%x,0x%x,%d}\\n\",\n\t\t adv->la_and4_mask, adv->la_and4_bitmap, adv->la_and4_inv);\n}\n\nvoid phydm_la_bb_adv_cmd_jgr3(void *dm_void, char input[][16], u32 *_used,\n\t\t\t      char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tstruct la_adv_trig *adv = &smp->adv_trig_table;\n\tu32 var1[10] = {0};\n\tu32 adv_trig_en;\n\n\tif (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))\n\t\treturn;\n\n\tif ((strcmp(input[2], \"show\") == 0)) {\n\t\tphydm_la_bb_adv_cmd_show_jgr3(dm, _used, output, _out_len);\n\t\treturn;\n\t}\n\n\tPHYDM_SSCANF(input[2], DCMD_HEX, &var1[0]);\n\tPHYDM_SSCANF(input[3], DCMD_HEX, &var1[1]);\n\tPHYDM_SSCANF(input[4], DCMD_HEX, &var1[2]);\n\tPHYDM_SSCANF(input[5], DCMD_HEX, &var1[3]);\n\tPHYDM_SSCANF(input[6], DCMD_HEX, &var1[4]);\n\n\tadv_trig_en = var1[0];\n\n\tif (adv_trig_en != 1) {\n\t\tPDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,\n\t\t\t \"Back to Ori-BB-trig\\n\");\n\t\tphydm_la_bb_adv_reset_jgr3(dm);\n\t\treturn;\n\t}\n\n\tadv->la_en_new_bbtrigger = true;\n\n\tif (var1[1] == 0) {\n\t\tadv->la_ori_bb_dis = (boolean)var1[2];\n\t} else if (var1[1] == 1) {\n\t\tadv->la_and1_sel = (u8)var1[2];\n\t\tadv->la_and1_val = (u8)var1[3];\n\t\tadv->la_and1_inv = (boolean)var1[4];\n\t} else if (var1[1] == 2) {\n\t\tadv->la_and2_sel = (u8)var1[2];\n\t\tadv->la_and2_val = (u8)var1[3];\n\t\tadv->la_and2_inv = (boolean)var1[4];\n\t} else if (var1[1] == 3) {\n\t\tadv->la_and3_sel = (u8)var1[2];\n\t\tadv->la_and3_val = (u8)var1[3];\n\t\tadv->la_and2_inv = (boolean)var1[4];\n\t}  else if (var1[1] == 4) {\n\t\tadv->la_and4_mask = (u8)var1[2];\n\t\tadv->la_and4_bitmap = (u8)var1[3];\n\t\tadv->la_and4_inv = (boolean)var1[4];\n\t}\n\n\tPDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,\n\t\t \"[Adv_trig_en=%d]\\n\\n\", adv_trig_en);\n\n\tphydm_la_bb_adv_cmd_show_jgr3(dm, _used, output, _out_len);\n}\n\n#endif\n\nvoid\nphydm_la_buffer_print(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tstruct rt_adcsmp_string *buf = &smp->adc_smp_buf;\n\tu32 i;\n\tu32 idx;\n\n\tif (!buf->octet || buf->length == 0 || buf->length < smp->smp_number)\n\t\treturn;\n\n\tpr_debug(\"[LA Data Dump] smp_number = %d\\n\", smp->smp_number);\n\n\tfor (i = 0; i < smp->smp_number; i++) {\n\t\tidx = i << 1;\n\n\t\t#if 0 /*((DM_ODM_SUPPORT_TYPE & ODM_WIN) && !DBG)*/\n\t\t/*WIN driver free build*/\n\t\tRT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, (\"%08x%08x\\n\",\n\t\t\t    buf->octet[idx], buf->octet[idx + 1]));\n\t\t#else\n\t\tpr_debug(\"%08x%08x\\n\", buf->octet[idx], buf->octet[idx + 1]);\n\t\t#endif\n\t}\n\tpr_debug(\"Dump Finished\\n\\n\");\n}\n\nvoid\nphydm_la_buffer_release(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tstruct rt_adcsmp_string *buf = &smp->adc_smp_buf;\n\n\tif (buf->length != 0x0) {\n\t\todm_free_memory(dm, buf->octet, buf->length);\n\t\tbuf->length = 0x0;\n\t}\n}\n\nboolean\nphydm_la_buffer_allocate(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\t#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\t#endif\n\tstruct rt_adcsmp_string *buf = &smp->adc_smp_buf;\n\tboolean ret = true;\n\n\tpr_debug(\"[LA mode BufferAllocate]\\n\");\n\n\tif (buf->length == 0) {\n\t#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t\tif (PlatformAllocateMemoryWithZero(adapter, (void **)&\n\t\t\t\t\t\t   buf->octet,\n\t\t\t\t\t\t   buf->buffer_size) !=\n\t\t\t\t\t\t   RT_STATUS_SUCCESS)\n\t\t\tret = false;\n\t#else\n\t\todm_allocate_memory(dm, (void **)&buf->octet, buf->buffer_size);\n\n\t\tif (!buf->octet)\n\t\t\tret = false;\n\t#endif\n\n\t\tif (ret)\n\t\t\tbuf->length = buf->buffer_size;\n\t}\n\n\treturn ret;\n}\n\nvoid phydm_la_access_tx_pkt_buf(void *dm_void, u32 addr, u32 buff_idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tstruct rt_adcsmp_string *buf = &smp->adc_smp_buf;\n\tu32 page;\n\tu32 data_l = 0, data_h = 0;\n\n\t#if (RTL8192F_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8192F) {\n\t\t#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t\tindirect_access_sdram_8192f(dm->adapter, TX_PACKET_BUFFER,\n\t\t\t\t\t    TRUE, (u16)addr >> 3, 0,\n\t\t\t\t\t    &data_h, &data_l);\n\t\t#else\n\t\todm_write_1byte(dm, R_0x0106, 0x69);\n\t\todm_set_bb_reg(dm, R_0x0140, MASKDWORD, addr >> 3);\n\t\tdata_l = odm_get_bb_reg(dm, R_0x0144, MASKDWORD);\n\t\tdata_h = odm_get_bb_reg(dm, R_0x0148, MASKDWORD);\n\t\todm_write_1byte(dm, R_0x0106, 0x0);\n\t\t#endif\n\t} else\n\t#endif\n\t{\n\t\t/* Reg140=0x780+(addr>>12),\n\t\t * addr=0x30~0x3F, total 16 pages\n\t\t */\n\t\tpage = addr >> 12;\n\n\t\tif (page != smp->txff_page) {\n\t\t\tsmp->txff_page = page;\n\t\t\todm_set_bb_reg(dm, R_0x0140, MASKLWORD, 0x780 + page);\n\t\t}\n\t\tdata_l = odm_read_4byte(dm, 0x8000 + (addr & 0xfff));\n\t\tdata_h = odm_read_4byte(dm, 0x8000 + (addr & 0xfff) + 4);\n\t}\n\n\tbuf->octet[buff_idx] = data_h;\n\tbuf->octet[buff_idx + 1] = data_l;\n}\n\nvoid phydm_la_get_tx_pkt_buf(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tstruct rt_adcsmp_string *buf = &smp->adc_smp_buf;\n\tu32 i = 0, value32 = 0;\n\tu32 addr = 0, finish_addr = 0; /* @(unit: 8Byte)*/\n\tboolean is_round_up = false;\n\tu32 addr_8byte = 0;\n\tu32 round_up_point = 0;\n\t#if (RTL8814B_SUPPORT)\n\tboolean recover_success = true;\n\t#endif\n\n\todm_memory_set(dm, buf->octet, 0, buf->length);\n\tpr_debug(\"GetTxPktBuf\\n\");\n\n\t/*@==== [Get LA Report] ==============================================*/\n\tif (dm->support_ic_type & ODM_RTL8192F) {\n\t\tvalue32 = odm_read_4byte(dm, R_0x7f0);\n\t\tis_round_up = (boolean)((value32 & BIT(31)) >> 31);\n\t\tfinish_addr = (value32 & 0x7FFF8000) >> 15; /*@16 bit (unit: 8Byte)*/\n\t} else {\n\t\todm_write_1byte(dm, R_0x0106, 0x69);\n\t\tvalue32 = odm_read_4byte(dm, R_0x7c0);\n\t\tis_round_up = (boolean)((value32 & BIT(31)) >> 31);\n\n\t\tif (dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC)\n\t\t\tfinish_addr = (value32 & 0x7FFF8000) >> 15; /*@16 bit (unit: 8Byte)*/\n\t\telse\n\t\t\tfinish_addr = (value32 & 0x7FFF0000) >> 16; /*@15bit (unit: 8Byte)*/\n\t}\n\n\t#if (RTL8814B_SUPPORT)\n\trecover_success = phydm_la_finish_addr_recover_8814B(dm, &finish_addr);\n\t#endif\n\n\tpr_debug(\"start_addr = ((0x%x)), end_addr = ((0x%x)), buffer_size = ((0x%x))\\n\",\n\t\t buf->start_pos, buf->end_pos, buf->buffer_size);\n\tif (is_round_up) {\n\t\tpr_debug(\"buf_start(0x%x)|----2---->|finish_addr(0x%x)|----1---->|buf_end(0x%x)\\n\",\n\t\t\t buf->start_pos, finish_addr << 3, buf->end_pos);\n\t\taddr = (finish_addr + 2) << 3; /*+1 or +2 ??*/\n\t\tround_up_point = (buf->end_pos - addr) >> 3; /*@Byte to 8Byte*/\n\t\tsmp->smp_number = smp->smp_number_max;\n\t\tpr_debug(\"is_round_up=(%d), round_up_point=(%d), 0x7c0/0x7F0=(0x%x), smp_number=(%d)\\n\",\n\t\t\t is_round_up, round_up_point, value32, smp->smp_number);\n\t} else {\n\t\tpr_debug(\"buf_start(0x%x)|------->|finish_addr(0x%x)             |buf_end(0x%x)\\n\",\n\t\t\t buf->start_pos, finish_addr << 3, buf->end_pos);\n\t\taddr = buf->start_pos;\n\t\taddr_8byte = addr >> 3;\n\t\tsmp->smp_number = DIFF_2(addr_8byte, finish_addr);\n\n\t\tpr_debug(\"is_round_up=(%d), smp_number=(%d)\\n\",\n\t\t\t is_round_up, smp->smp_number);\n\t}\n\n\t/*@==== [Get LA Patterns in TXFF] ====================================*/\n\t#ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM\n\tphydm_la_mv_data_2_tx_buffer(dm);\n\t#endif\n\n\t#if (RTL8814B_SUPPORT)\n\tif ((dm->support_ic_type & ODM_RTL8814B) && !recover_success) {\n\t\taddr = buf->start_pos;\n\t\tsmp->smp_number = smp->smp_number_max;\n\t}\n\t#endif\n\n\tfor (i = 0; i < smp->smp_number; i++) {\n\t\tphydm_la_access_tx_pkt_buf(dm, addr, i << 1);\n\t\taddr += 8;\n\n\t\tif (addr >= buf->end_pos)\n\t\t\taddr = buf->start_pos; /*Ring buffer*/\n\t}\n\n\t/*@==== [Print LA Patterns] ==========================================*/\n\tif (smp->is_la_print)\n\t\tphydm_la_buffer_print(dm);\n\n\t#if (RTL8197F_SUPPORT)\n\tphydm_la_stop_dma_8197f(dm, PHYDM_RESTORE);\n\t#endif\n}\n\nvoid phydm_la_set_trig_src(void *dm_void, u8 la_trig_mode)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 reg = (dm->support_ic_type == ODM_RTL8192F) ? R_0x7f0 : R_0x7c0;\n\n\tif (la_trig_mode == PHYDM_ADC_MAC_TRIG)\n\t\todm_set_mac_reg(dm, reg, BIT(3), 1);\n\telse\n\t\todm_set_mac_reg(dm, reg, BIT(3), 0);\n}\n\nvoid phydm_la_set_mac_iq_dump(void *dm_void, boolean impossible_trig_condi)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tu32 reg_value = 0;\n\tu32 reg1 = 0, reg2 = 0, reg3 = 0;\n\n\tif (dm->support_ic_type & ODM_RTL8192F) {\n\t\treg1 = R_0x7f0;\n\t\treg2 = R_0x7f4;\n\t\treg3 = R_0x7f8;\n\t} else {\n\t\treg1 = R_0x7c0;\n\t\treg2 = R_0x7c4;\n\t\treg3 = R_0x7c8;\n\t}\n\n\todm_write_1byte(dm, reg1, 0); /*@clear all reg1*/\n\t/*@Enable LA mode HW block*/\n\todm_set_mac_reg(dm, reg1, BIT(0), 1);\n\n\tif (smp->la_trig_mode == PHYDM_MAC_TRIG) {\n\t\tsmp->la_dump_mode = LA_MAC_DBG_DUMP;\n\t\t/*polling bit for MAC mode*/\n\t\todm_set_mac_reg(dm, reg1, BIT(2), 1);\n\t\t/*trigger mode for MAC*/\n\t\todm_set_mac_reg(dm, reg1, 0x18,\tsmp->la_trigger_edge);\n\t\tpr_debug(\"[MAC_trig] ref_mask=(0x%x), ref_value=(0x%x), dbg_port =(0x%x)\\n\",\n\t\t\t smp->la_mac_mask_or_hdr_sel, smp->la_trig_sig_sel,\n\t\t\t smp->la_dbg_port);\n\t\t/*@[Set MAC Debug Port]*/\n\t\todm_set_mac_reg(dm, R_0xf4, BIT(16), 1);\n\t\todm_set_mac_reg(dm, R_0x38, 0xff0000, smp->la_dbg_port);\n\t\todm_set_mac_reg(dm, reg2, MASKDWORD,\n\t\t\t\tsmp->la_mac_mask_or_hdr_sel);\n\t\todm_set_mac_reg(dm, reg3, MASKDWORD, smp->la_trig_sig_sel);\n\t} else {\n\t\tsmp->la_dump_mode = LA_BB_ADC_DUMP;\n\n\t\tif (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {\n\t\t\t/*polling bit for MAC trigger event*/\n\t\t\tif (impossible_trig_condi)\n\t\t\t\tphydm_la_set_trig_src(dm, PHYDM_ADC_BB_TRIG);\n\t\t\telse\n\t\t\t\tphydm_la_set_trig_src(dm, PHYDM_ADC_MAC_TRIG);\n\n\t\t\todm_set_mac_reg(dm, reg1, 0xc0,\tsmp->la_trig_sig_sel);\n\n\t\t\tif (smp->la_trig_sig_sel == ADCSMP_TRIG_REG) {\n\t\t\t\t/* @manual trigger reg1[5] = 0->1*/\n\t\t\t\todm_set_mac_reg(dm, reg1, BIT(5), 1);\n\t\t\t}\n\t\t}\n\t\t/*polling bit for BB ADC mode*/\n\t\todm_set_mac_reg(dm, reg1, BIT(1), 1);\n\t}\n\n\treg_value = odm_get_bb_reg(dm, reg1, 0xff);\n\tpr_debug(\"4. [Set MAC IQ dump] 0x%x[7:0]=(0x%x)\\n\", reg1, reg_value);\n\n\t#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tRT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,\n\t\t    (\"4. [Set MAC IQ dump] 0x%x[7:0]=(0x%x)\\n\", reg1,\n\t\t    reg_value));\n\t#endif\n}\n\nvoid phydm_la_set_bb_dbg_port(void *dm_void, boolean impossible_trig_condi)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\n\tu8\ttrig_mode = smp->la_trig_mode;\n\tu32\ttrig_sel = smp->la_trig_sig_sel;\n\tu32\tdbg_port = smp->la_dbg_port;\n\n\tif (trig_mode == PHYDM_MAC_TRIG)\n\t\ttrig_sel = 0; /*@ignore this setting*/\n\n\t/*set BB debug port*/\n\tif (impossible_trig_condi) {\n\t\tdbg_port = 0xf;\n\t\ttrig_sel = 0;\n\t\tpr_debug(\"[BB Setting] fake-trigger!\\n\");\n\t}\n\n\tif (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port)) {\n\t\tpr_debug(\" *Set dbg_port=(0x%x)\\n\", dbg_port);\n\t} else {\n\t\tdbg_port = phydm_get_bb_dbg_port_idx(dm);\n\t\tpr_debug(\"[Set dbg_port fail!] Curr-DbgPort=0x%x\\n\", dbg_port);\n\t}\n\n\t/*@debug port bit*/\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\todm_set_bb_reg(dm, R_0x95c, 0x1f, trig_sel);\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\todm_set_bb_reg(dm, R_0x1ce4, 0x3e000, trig_sel);\n\t#endif\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x9a0, 0x1f, trig_sel);\n\t}\n\n\tif (smp->la_trig_mode == PHYDM_ADC_BB_TRIG) {\n\t\tpr_debug(\" *Set dbg_port[BIT] = %d\\n\", trig_sel);\n\n\t\t#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t\tRT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,\n\t\t\t    (\" *Set dbg_port[BIT] = %d\\n\", trig_sel));\n\t\t#endif\n\t}\n}\n\nvoid phydm_la_set_bb(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\n\tu8\ttrig_mode = smp->la_trig_mode;\n\tu8\tedge = smp->la_trigger_edge;\n\tu8\tsmp_rate = smp->la_smp_rate;\n\tu8\tdma_type = smp->la_dma_type;\n\tu32\tdbg_port_hdr_sel = 0;\n\tchar\t*trig_mode_word = NULL;\n\n\tpr_debug(\"3. [BB Setting] mode=(%d), Edge=(%s), smp_rate=(%dM), Dma_type=(%d)\\n\",\n\t\t trig_mode,\n\t\t (edge == 0) ? \"P\" : \"N\", 80 >> smp_rate, dma_type);\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\tif (trig_mode == PHYDM_ADC_RF0_TRIG)\n\t\t\tdbg_port_hdr_sel = 9; /*@DBGOUT_RFC_a[31:0]*/\n\t\telse if (trig_mode == PHYDM_ADC_RF1_TRIG)\n\t\t\tdbg_port_hdr_sel = 8; /*@DBGOUT_RFC_b[31:0]*/\n\t\telse if ((trig_mode == PHYDM_ADC_BB_TRIG) ||\n\t\t\t (trig_mode == PHYDM_ADC_MAC_TRIG)) {\n\t\t\tif (smp->la_mac_mask_or_hdr_sel <= 0xf)\n\t\t\t\tdbg_port_hdr_sel = smp->la_mac_mask_or_hdr_sel;\n\t\t\telse\n\t\t\t\tdbg_port_hdr_sel = 0;\n\t\t}\n\n\t\tphydm_bb_dbg_port_header_sel(dm, dbg_port_hdr_sel);\n\n\t\todm_set_bb_reg(dm, R_0x8b4, BIT(7), 1);/*@update rpt every pkt*/\n\t\todm_set_bb_reg(dm, R_0x95c, 0xf00, dma_type);\n\t\t/*@0: posedge, 1: negedge*/\n\t\todm_set_bb_reg(dm, R_0x95c, BIT(31), edge);\n\t\todm_set_bb_reg(dm, R_0x95c, 0xe0, smp_rate);\n\t\t/*\t@(0:) '80MHz'\n\t\t *\t(1:) '40MHz'\n\t\t *\t(2:) '20MHz'\n\t\t *\t(3:) '10MHz'\n\t\t *\t(4:) '5MHz'\n\t\t *\t(5:) '2.5MHz'\n\t\t *\t(6:) '1.25MHz'\n\t\t *\t(7:) '160MHz (for BW160 ic)'\n\t\t */\n\t\t#if (RTL8821C_SUPPORT | RTL8195B_SUPPORT)\n\t\tphydm_la_clk_en(dm, true);\n\t\t#endif\n\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\todm_set_bb_reg(dm, R_0x1eb4, BIT(23), 0x1);/*@update rpt every pkt*/\n\t\t/*@MAC-PHY timing*/\n\t\todm_set_bb_reg(dm, R_0x1ce4, BIT(7) | BIT(6), 0);\n\t\todm_set_bb_reg(dm, R_0x1cf4, BIT(23), 1); /*@LA mode on*/\n\t\todm_set_bb_reg(dm, R_0x1ce4, 0x3f, dma_type);\n\t\t/*@0: posedge, 1: negedge ??*/\n\t\todm_set_bb_reg(dm, R_0x1ce4, BIT(26), edge);\n\t\todm_set_bb_reg(dm, R_0x1ce4, 0x700, smp_rate);\n\n\t\tphydm_la_bb_adv_trig_setting_jgr3(dm);\n\t#endif\n\t} else {\n\t\tif (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))\n\t\t\todm_set_bb_reg(dm, R_0xd00, BIT(26), 0x1); /*@update rpt every pkt*/\n\n\t\t#if (RTL8192F_SUPPORT)\n\t\tif ((dm->support_ic_type & ODM_RTL8192F))\n\t\t\t/*@LA reset HW block enable for true-mac asic*/\n\t\t\todm_set_bb_reg(dm, R_0x9a0, BIT(15), 1);\n\t\t#endif\n\n\t\todm_set_bb_reg(dm, R_0x9a0, 0xf00, dma_type);\n\t\t/*@0: posedge, 1: negedge*/\n\t\todm_set_bb_reg(dm, R_0x9a0, BIT(31), edge);\n\t\todm_set_bb_reg(dm, R_0x9a0, 0xe0, smp_rate);\n\t\t/*\t@(0:) '80MHz'\n\t\t *\t(1:) '40MHz'\n\t\t *\t(2:) '20MHz'\n\t\t *\t(3:) '10MHz'\n\t\t *\t(4:) '5MHz'\n\t\t *\t(5:) '2.5MHz'\n\t\t *\t(6:) '1.25MHz'\n\t\t *\t(7:) '160MHz (for BW160 ic)'\n\t\t */\n\t}\n}\n\nvoid phydm_la_set_mac_trigger_time(void *dm_void, u32 trigger_time_mu_sec)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 time_unit_num = 0;\n\tu32 unit = 0;\n\n\tif (trigger_time_mu_sec < 128)\n\t\tunit = 0; /*unit: 1mu sec*/\n\telse if (trigger_time_mu_sec < 256)\n\t\tunit = 1; /*unit: 2mu sec*/\n\telse if (trigger_time_mu_sec < 512)\n\t\tunit = 2; /*unit: 4mu sec*/\n\telse if (trigger_time_mu_sec < 1024)\n\t\tunit = 3; /*unit: 8mu sec*/\n\telse if (trigger_time_mu_sec < 2048)\n\t\tunit = 4; /*unit: 16mu sec*/\n\telse if (trigger_time_mu_sec < 4096)\n\t\tunit = 5; /*unit: 32mu sec*/\n\telse if (trigger_time_mu_sec < 8192)\n\t\tunit = 6; /*unit: 64mu sec*/\n\n\ttime_unit_num = (u8)(trigger_time_mu_sec >> unit);\n\n\tpr_debug(\"2. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\\n\",\n\t\t time_unit_num, unit);\n\t#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tRT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, (\n\t\t    \"3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\\n\",\n\t\t    time_unit_num, unit));\n\t#endif\n\n\tif (dm->support_ic_type & ODM_RTL8192F) {\n\t\todm_set_mac_reg(dm, R_0x7fc, BIT(2) | BIT(1) | BIT(0), unit);\n\t\todm_set_mac_reg(dm, R_0x7f0, 0x7f00, (time_unit_num & 0x7f));\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\todm_set_mac_reg(dm, R_0x7cc, BIT(18) | BIT(17) | BIT(16), unit);\n\t\todm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));\n\t#endif\n\t} else {\n\t\todm_set_mac_reg(dm, R_0x7cc, BIT(20) | BIT(19) | BIT(18), unit);\n\t\todm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));\n\t}\n}\n\nvoid phydm_la_set_buff_mode(void *dm_void, enum la_buff_mode mode)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tstruct rt_adcsmp_string *buf = &smp->adc_smp_buf;\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\tstruct rtl8192cd_priv\t\t*priv = dm->priv;\n\tu8 normal_LA_on = priv->pmib->miscEntry.normal_LA_on;\n#endif\n\tu32 buff_size_base = 0;\n\tu32 end_pos_tmp = 0;\n\n\tsmp->la_buff_mode = mode;\n\tswitch (dm->support_ic_type) {\n\tcase ODM_RTL8814A:\n\t\tbuff_size_base = 0x10000;\n\t\tend_pos_tmp = 0x40000;\n\t\tbreak;\n\tcase ODM_RTL8822B:\n\tcase ODM_RTL8822C:\n\tcase ODM_RTL8812F:\n\t\tbuff_size_base = 0x20000; /*@WIN: TX_FIFO_SIZE_LA_8822C*/\n\t\tend_pos_tmp = 0x40000;\n\t\tbreak;\n\tcase ODM_RTL8814B:\n\t\tbuff_size_base = 0x30000;\n\t\tend_pos_tmp = 0x60000;\n\t\tbreak;\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\tcase ODM_RTL8197F:\n\tcase ODM_RTL8198F:\n\tcase ODM_RTL8197G:\n\t\tbuff_size_base = 0x10000;\n\t\tend_pos_tmp = (normal_LA_on == 1) ? 0x20000 : 0x10000;\n\t\tbreak;\n#endif\n\tcase ODM_RTL8192F:\n\t\tbuff_size_base = 0xE000;\n\t\tend_pos_tmp = 0x10000;\n\t\tbreak;\n\tcase ODM_RTL8821C:\n\t\tbuff_size_base = 0x8000;\n\t\tend_pos_tmp = 0x10000;\n\t\tbreak;\n\tcase ODM_RTL8195B:\n\t\tbuff_size_base = 0x4000;\n\t\tend_pos_tmp = 0x8000;\n\t\tbreak;\n\tdefault:\n\t\tpr_debug(\"[%s] Warning!\", __func__);\n\t\tbreak;\n\t}\n\n\tbuf->buffer_size = buff_size_base;\n\n\tif (dm->support_ic_type & FULL_BUFF_MODE_SUPPORT) {\n\t\tif (mode == ADCSMP_BUFF_HALF) {\n\t\t\todm_set_mac_reg(dm, R_0x7cc, BIT(30), 0);\n\t\t} else {\n\t\t\tbuf->buffer_size = buf->buffer_size << 1;\n\t\t\todm_set_mac_reg(dm, R_0x7cc, BIT(30), 1);\n\t\t}\n\t}\n\n\tbuf->end_pos = end_pos_tmp;\n\tbuf->start_pos = end_pos_tmp - buf->buffer_size;\n\tsmp->smp_number_max = buf->buffer_size >> 3;\n\n\tPHYDM_DBG(dm, DBG_TMP,\n\t\t  \"start_addr=(0x%x), end_addr=(0x%x), buffer_size=(0x%x), smp_number_max=(%d)\\n\",\n\t\t  buf->start_pos, buf->end_pos, buf->buffer_size,\n\t\t  smp->smp_number_max);\n}\n\nvoid phydm_la_adc_smp_start(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tu8 tmp_u1b = 0;\n\tu8 i = 0;\n\tu8 polling_bit = 0;\n\tboolean polling_ok = false;\n\tboolean impossible_trig_condi = (smp->en_fake_trig) ? true : false;\n\n\t#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tRT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,\n\t\t    (\"1. [BB Setting] Mode=(%d), DbgPort=(0x%x), Edge=(%d), SmpRate=(%d), Trig_Sel=(0x%x), Dma_type=(%d)\\n\",\n\t\t    smp->la_trig_mode, smp->la_dbg_port, smp->la_trigger_edge,\n\t\t    smp->la_smp_rate, smp->la_trig_sig_sel, smp->la_dma_type));\n\t#endif\n\tpr_debug(\"1. [BB Setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\\n\",\n\t\t smp->la_trig_mode, smp->la_dbg_port, smp->la_trigger_edge,\n\t\t smp->la_smp_rate, smp->la_trig_sig_sel, smp->la_dma_type);\n\n\tphydm_la_set_mac_trigger_time(dm, smp->la_trigger_time);\n\tphydm_la_set_bb(dm);\n\tphydm_la_set_bb_dbg_port(dm, impossible_trig_condi);\n\tphydm_la_set_mac_iq_dump(dm, impossible_trig_condi);\n\n\t#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\twatchdog_stop(dm->priv);\n\t#endif\n\n\tif (impossible_trig_condi) {\n\t\tODM_delay_ms(100);\n\t\tphydm_la_set_bb_dbg_port(dm, false);\n\n\t\tif (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {\n\t\t\tphydm_la_set_trig_src(dm, PHYDM_ADC_MAC_TRIG);\n\t\t}\n\t}\n#if RTL8198F_SUPPORT\n\tphydm_la_pre_run(dm);\n#endif\n\tpolling_bit = (smp->la_dump_mode == LA_BB_ADC_DUMP) ? BIT(1) : BIT(2);\n\tdo { /*Polling time always use 100ms, when it exceed 2s, break loop*/\n\t\tif (dm->support_ic_type & ODM_RTL8192F)\n\t\t\ttmp_u1b = odm_read_1byte(dm, R_0x7f0);\n\t\telse\n\t\t\ttmp_u1b = odm_read_1byte(dm, R_0x7c0);\n\n\t\tpr_debug(\"[%d] polling rpt=((0x%x))\\n\", i, tmp_u1b);\n\n\t\tif (smp->adc_smp_state != ADCSMP_STATE_SET) {\n\t\t\tpr_debug(\"[state Error] state != ADCSMP_STATE_SET\\n\");\n\t\t\tbreak;\n\n\t\t} else if (tmp_u1b & polling_bit) {\n\t\t\tODM_delay_ms(100);\n\t\t\ti++;\n\t\t\tcontinue;\n\t\t} else {\n\t\t\tpr_debug(\"[LA Query OK] polling_bit=%d\\n\", polling_bit);\n\t\t\tpolling_ok = true;\n\t\t\tbreak;\n\t\t}\n\t} while (i < 20);\n\n\tif (smp->adc_smp_state == ADCSMP_STATE_SET) {\n\t\tif (polling_ok)\n\t\t\tphydm_la_get_tx_pkt_buf(dm);\n\t\telse\n\t\t\tpr_debug(\"[Polling timeout]\\n\");\n\t}\n\n\t#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\twatchdog_resume(dm->priv);\n\t#endif\n\n\t#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\tif (smp->adc_smp_state == ADCSMP_STATE_SET)\n\t\tsmp->adc_smp_state = ADCSMP_STATE_QUERY;\n\t#endif\n\n\tpr_debug(\"[LA mode] la_count = ((%d))\\n\", smp->la_count);\n\t#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tRT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,\n\t\t    (\"[LA mode] la_count = ((%d))\\n\", smp->la_count));\n\t#endif\n\n\tphydm_la_stop(dm);\n\n\tif (smp->la_count == 0) {\n\t\tpr_debug(\"LA Dump finished ---------->\\n\\n\\n\");\n\t\tphydm_release_bb_dbg_port(dm);\n\n\t\t#if (RTL8821C_SUPPORT | RTL8195B_SUPPORT)\n\t\tphydm_la_clk_en(dm, false);\n\t\t#endif\n\t} else {\n\t\tsmp->la_count--;\n\t\tpr_debug(\"LA Dump more ---------->\\n\\n\\n\");\n\t\tphydm_la_set(dm);\n\t}\n}\n\nvoid phydm_la_set(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tboolean is_set_success = true;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\n\tif (smp->adc_smp_state != ADCSMP_STATE_IDLE)\n\t\tis_set_success = false;\n\telse if (smp->adc_smp_buf.length == 0)\n\t\tis_set_success = phydm_la_buffer_allocate(dm);\n\n\tif (!is_set_success) {\n\t\tpr_debug(\"[LA Set Fail] LA_State=(%d)\\n\", smp->adc_smp_state);\n\t\treturn;\n\t}\n\n\tsmp->adc_smp_state = ADCSMP_STATE_SET;\n\n\tpr_debug(\"[LA Set Success] LA_State=(%d)\\n\", smp->adc_smp_state);\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\n\tpr_debug(\"ADCSmp_work_item_index=(%d)\\n\", smp->la_work_item_index);\n\n\tif (smp->la_work_item_index != 0) {\n\t\todm_schedule_work_item(&smp->adc_smp_work_item_1);\n\t\tsmp->la_work_item_index = 0;\n\t} else {\n\t\todm_schedule_work_item(&smp->adc_smp_work_item);\n\t\tsmp->la_work_item_index = 1;\n\t}\n#else\n\tphydm_la_adc_smp_start(dm);\n#endif\n}\n\nvoid phydm_la_cmd_fast(void *dm_void, char input[][16], u32 *_used,\n\t\t       char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tu32 var[10] = {0};\n\tu8 bw = *dm->band_width;\n\n\tif (bw > 2) {\n\t\tPDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,\n\t\t\t \"Not Support for BW > %dM\\n\", 20 << bw);\n\t\treturn;\n\t}\n\n\tPHYDM_SSCANF(input[2], DCMD_HEX, &var[0]);\n\n\tif (var[0] <= 10) { /* CCA P-edge trigger*/\n\t\tsmp->la_trig_mode = 1;\n\t\tsmp->la_trig_sig_sel = 2;\n\t\tsmp->la_trigger_time = ((smp->smp_number_max >> (bw + 1)) / 10)\n\t\t\t\t\t - (2 << (2 - bw)) - (2 - bw);\n\t\tsmp->la_mac_mask_or_hdr_sel = 0;\n\t\tsmp->la_trigger_edge = 0;\n\t\tsmp->la_smp_rate = 2 - bw;\n\t\tsmp->la_count = 0;\n\t\tif (var[0] == 0) {\n\t\t\tsmp->la_dma_type = 5;\n\t\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\t\t\tsmp->la_dbg_port = 0x870;\n\t\t\telse\n\t\t\t\tsmp->la_dbg_port = 0x210;\n\t\t} else if (var[0] == 1) {\n\t\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t\t\tsmp->la_dma_type = 4;\n\t\t\t\tsmp->la_dbg_port = 0x392;\n\t\t\t} else {\n\t\t\t\tsmp->la_dma_type = 5;\n\t\t\t\tsmp->la_dbg_port = 0xa44;\n\t\t\t}\n\t\t}\n\t}\n\n\tPDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,\n\t\t \"echo lamode 1 %d %d %d %d %d %x %d %d %d\\n\",\n\t\t smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type,\n\t\t smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel,\n\t\t smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate,\n\t\t smp->la_count);\n\n\tphydm_la_set(dm);\n}\n\nvoid phydm_la_cmd(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t  u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tu8 trig_mode = 0, dma_data_sig_sel = 0;\n\tu32 trig_sig_sel = 0;\n\tu32 trigger_time_mu_sec = 0;\n\tchar help[] = \"-h\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\tif (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE))\n\t\treturn;\n\n#ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM\n\tif (dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC) {\n\t\tif (dm->is_download_fw)\n\t\t\treturn;\n\t}\n\t#if RTL8198F_SUPPORT\n\tif (dm->support_ic_type & ODM_RTL8198F) {\n\t\tif (!*dm->mp_mode && !dm->priv->pmib->miscEntry.normal_LA_on) {\n\t\t\tpr_debug(\"plz re-set normal_LA_on = 1 & DnUp.\\n\");\n\t\t\treturn;\n\t\t}\n\t}\n\t#endif\n#endif\n\n\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);\n\n\t/*@dbg_print(\"echo cmd input_num = %d\\n\", input_num);*/\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"=====[LA Mode Help] =============================\\n\");\n\t\t/*Trigger*/\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"BB_trig:  1 0 {DbgPort Bit} {DMA#} {TrigTime} {DbgPort_head(Jgr2)}\\n\\t{DbgPort} {Edge: 0(P),1(N)} {f_smp:80 >> N} {Capture num}\\n\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"MAC_trig: 1 1 {0-ok/1-fail/2-cca} {DMA#} {TrigTime} {DbgPort_head(Jgr2)}\\n\\t{DbgPort} {N/A} {f_smp:80 >> N} {Cpture num}\\n\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"All: {En} {0:ADC_BB_trig,1:ADC MAC_trig,2:RF0,3:RF1,4:MAC}\\n\\t{BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA#} {TrigTime}\\n\\t{DbgPort_head/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\\n\\n\");\n\t\t/*Adv-Trig*/\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"adv show\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"adv {adv_trig_en} {0:And[0]_disable} {en}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"adv {adv_trig_en} {1~3: And[3:0]} {Sel} {Val} {Inv}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"adv {adv_trig_en} {4: And[4]} {BitMask} {BitVal} {Inv}\\n\\n\");\n\t\t#endif\n\t\t/*Setting*/\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"set {1:tx_buff_size} {0: half, 1:full}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"set {2:Fake Trigger} {en}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"set {3:Auto Print} {en}\\n\\n\");\n\t\t/*Print*/\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"print\\n\\n\");\n\n\t\t/*Fast Trigger*/\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"fast {0: CCA trig & CCA Dbg Port}\\n\");\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"fast {1: CCA trig & EVM Dbg Port}\\n\");\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"=================================================\\n\");\n\t} else if ((strcmp(input[1], \"print\") == 0)) {\n\t\tphydm_la_buffer_print(dm);\n\t} else if ((strcmp(input[1], \"fast\") == 0)) {\n\t\tphydm_la_cmd_fast(dm, input, &used, output, &out_len);\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t} else if ((strcmp(input[1], \"adv\") == 0)) {\n\t\tphydm_la_bb_adv_cmd_jgr3(dm, input, &used, output, &out_len);\n#endif\n\t} else if ((strcmp(input[1], \"set\") == 0)) {\n\t\tPHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);\n\n\t\tif (var1[1] == 1) {\n\t\t\tPHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);\n\t\t\tphydm_la_set_buff_mode(dm, (enum la_buff_mode)var1[2]);\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"Buff_mode=(%d/2)\\n\", smp->la_buff_mode + 1);\n\t\t} else if (var1[1] == 2) {\n\t\t\tPHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);\n\t\t\tsmp->en_fake_trig = (boolean)var1[2];\n\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"en_fake_trig=(%d)\\n\", smp->en_fake_trig);\n\t\t} else if (var1[1] == 3) {\n\t\t\tPHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);\n\t\t\tsmp->is_la_print = (boolean)var1[2];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"Auto print=(%d)\\n\", smp->is_la_print);\n\t\t}\n\t} else if (var1[0] == 1) {\n\t\tPHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);\n\n\t\tsmp->la_trig_mode = (u8)var1[1];\n\n\t\tif (trig_mode == PHYDM_MAC_TRIG)\n\t\t\tPHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);\n\t\telse\n\t\t\tPHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);\n\t\tsmp->la_trig_sig_sel = var1[2];\n\n\t\tPHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);\n\t\tPHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);\n\t\tPHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);\n\t\tPHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]);\n\t\tPHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]);\n\t\tPHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]);\n\t\tPHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]);\n\n\t\tsmp->la_dma_type = (u8)var1[3];\n\t\tsmp->la_trigger_time = var1[4]; /*unit: us*/\n\t\tsmp->la_mac_mask_or_hdr_sel = var1[5];\n\t\tsmp->la_dbg_port = var1[6];\n\t\tsmp->la_trigger_edge = (u8)var1[7];\n\t\tsmp->la_smp_rate = (u8)(var1[8] & 0x7);\n\t\tsmp->la_count = var1[9];\n\n\t\tpr_debug(\"echo lamode %d %d %d %d %d %d %x %d %d %d\\n\",\n\t\t\t var1[0], var1[1], var1[2], var1[3], var1[4],\n\t\t\t var1[5], var1[6], var1[7], var1[8], var1[9]);\n\t\t#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t\tRT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,\n\t\t\t    (\"echo lamode %d %d %d %d %d %d %x %d %d %d\\n\",\n\t\t\t    var1[0], var1[1], var1[2], var1[3],\n\t\t\t    var1[4], var1[5], var1[6], var1[7],\n\t\t\t    var1[8], var1[9]));\n\t\t#endif\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"a.En= ((1)),  b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\\n\",\n\t\t\t trig_mode, trig_sig_sel, dma_data_sig_sel);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"e.Trig_Time = ((%dus)), f.Dbg_head/mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\\n\",\n\t\t\t trigger_time_mu_sec,\n\t\t\t smp->la_mac_mask_or_hdr_sel, smp->la_dbg_port);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\\n\",\n\t\t\t smp->la_trigger_edge, (80 >> smp->la_smp_rate),\n\t\t\t smp->la_count);\n\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"k.en_new_bbtrigger = ((%d))\\n\",\n\t\t\t smp->adv_trig_table.la_en_new_bbtrigger);\n\t\t#endif\n\n\t\tphydm_la_set(dm);\n\t} else {\n\t\tphydm_la_stop(dm);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Disable LA mode\\n\");\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_la_stop(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\n\tsmp->adc_smp_state = ADCSMP_STATE_IDLE;\n\n\tPHYDM_DBG(dm, DBG_TMP, \"[LA_Stop] LA_state = %d\\n\", smp->adc_smp_state);\n}\n\nvoid phydm_la_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tstruct rt_adcsmp_string *buf = &smp->adc_smp_buf;\n\n\tsmp->adc_smp_state = ADCSMP_STATE_IDLE;\n\tsmp->is_la_print = true;\n\tsmp->en_fake_trig = false;\n\tsmp->txff_page = 0xffffffff;\n\tphydm_la_set_buff_mode(dm, ADCSMP_BUFF_HALF);\n\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\tphydm_la_bb_adv_reset_jgr3(dm);\n\t#endif\n}\n\nvoid adc_smp_de_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tphydm_la_stop(dm);\n\tphydm_la_buffer_release(dm);\n}\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\nvoid adc_smp_work_item_callback(void *context)\n{\n\tvoid *adapter = (void *)context;\n\tPHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\n\tpr_debug(\"[WorkItem Call back] LA_State=(%d)\\n\", smp->adc_smp_state);\n\tphydm_la_adc_smp_start(dm);\n}\n#endif\n\n#if 0\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\nenum rt_status\nadc_smp_query(void *dm_void, ULONG info_buf_length, void *info_buf,\n\t      PULONG bytes_written)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tenum rt_status ret_status = RT_STATUS_SUCCESS;\n\tstruct rt_adcsmp_string *buf = &smp->adc_smp_buf;\n\n\tpr_debug(\"[%s] LA_State=((%d))\", __func__, smp->adc_smp_state);\n\n\tif (info_buf_length != buf->buffer_size) {\n\t\t*bytes_written = 0;\n\t\tret_status = RT_STATUS_RESOURCE;\n\t} else if (buf->length != buf->buffer_size) {\n\t\t*bytes_written = 0;\n\t\tret_status = RT_STATUS_RESOURCE;\n\t} else if (smp->adc_smp_state != ADCSMP_STATE_QUERY) {\n\t\t*bytes_written = 0;\n\t\tret_status = RT_STATUS_PENDING;\n\t} else {\n\t\todm_move_memory(dm, info_buf, buf->octet, buf->buffer_size);\n\t\t*bytes_written = buf->buffer_size;\n\n\t\tsmp->adc_smp_state = ADCSMP_STATE_IDLE;\n\t}\n\n\tpr_debug(\"Return status %d\\n\", ret_status);\n\n\treturn ret_status;\n}\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\nvoid adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tstruct rt_adcsmp_string *buf = &smp->adc_smp_buf;\n\tu32 used = *pused;\n\tu32 i = 0;\n#if 0\n\t/* struct timespec t; */\n\t/* rtw_get_current_timespec(&t); */\n#endif\n\n\tpr_debug(\"%s adc_smp_state %d\", __func__, smp->adc_smp_state);\n\n\tfor (i = 0; i < (buf->length >> 2) - 2; i += 2) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"%08x%08x\\n\", buf->octet[i], buf->octet[i + 1]);\n\t}\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"\\n\");\n\t/* PDM_SNPF(output + used, out_len - used, \"\\n[%lu.%06lu]\\n\", */\n\t/*\t    t.tv_sec, t.tv_nsec); */\n\t*pused = used;\n}\n\ns32 adc_smp_get_sample_counts(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tstruct rt_adcsmp_string *buf = &smp->adc_smp_buf;\n\n\treturn (buf->length >> 2) - 2;\n}\n\ns32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len, u32 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct rt_adcsmp *smp = &dm->adcsmp;\n\tstruct rt_adcsmp_string *buf = &smp->adc_smp_buf;\n\tu32 used = 0;\n\n\t/* @dbg_print(\"%s adc_smp_state %d\\n\", __func__,*/\n\t/*\t      smp->adc_smp_state);*/\n\tif (smp->adc_smp_state != ADCSMP_STATE_QUERY) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Error: la data is not ready yet ...\\n\");\n\t\treturn -1;\n\t}\n\n\tif (idx < ((buf->length >> 2) - 2)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"%08x%08x\\n\", buf->octet[idx], buf->octet[idx + 1]);\n\t}\n\treturn 0;\n}\n#endif\n#endif\n\n#endif /*@endif PHYDM_LA_MODE_SUPPORT*/\n"
  },
  {
    "path": "hal/phydm/phydm_adc_sampling.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __INC_ADCSMP_H\n#define __INC_ADCSMP_H\n\n#if (PHYDM_LA_MODE_SUPPORT)\n\n#define DYNAMIC_LA_MODE \"4.0\"\n\n/* @1 ============================================================\n * 1  Definition\n * 1 ============================================================\n */\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n#if (RTL8197F_SUPPORT || RTL8198F_SUPPORT || RTL8197G_SUPPORT)\n\t#define PHYDM_COMPILE_LA_STORE_IN_IMEM\n#endif\n#endif\n\n#define PHYDM_LA_STORE_IN_IMEM_IC (ODM_RTL8197F | ODM_RTL8198F | ODM_RTL8197G)\n\n#define FULL_BUFF_MODE_SUPPORT (ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\\\n\t\t\t\tODM_RTL8812F | ODM_RTL8814B)\n\n/* @ ============================================================\n *  enumrate\n *  ============================================================\n */\nenum la_dump_mode {\n\tLA_BB_ADC_DUMP\t\t= 0,\n\tLA_MAC_DBG_DUMP\t\t= 1\n};\n\nenum rt_adcsmp_trig_sel {\n\tPHYDM_ADC_BB_TRIG\t= 0,\n\tPHYDM_ADC_MAC_TRIG\t= 1,\n\tPHYDM_ADC_RF0_TRIG\t= 2,\n\tPHYDM_ADC_RF1_TRIG\t= 3,\n\tPHYDM_MAC_TRIG\t\t= 4\n};\n\nenum rt_adcsmp_trig_sig_sel {\n\tADCSMP_TRIG_CRCOK\t= 0,\n\tADCSMP_TRIG_CRCFAIL\t= 1,\n\tADCSMP_TRIG_CCA\t\t= 2,\n\tADCSMP_TRIG_REG\t\t= 3\n};\n\nenum rt_adcsmp_state {\n\tADCSMP_STATE_IDLE\t= 0,\n\tADCSMP_STATE_SET\t= 1,\n\tADCSMP_STATE_QUERY\t= 2\n};\n\nenum la_buff_mode {\n\tADCSMP_BUFF_HALF\t= 0,\n\tADCSMP_BUFF_ALL\t\t= 1\t/*Only use in MP Driver*/\n};\n\n/* @ ============================================================\n *   structure\n *  ============================================================\n */\n\nstruct rt_adcsmp_string {\n\tu32\t\t\t*octet;\n\tu32\t\t\tlength;\n\tu32\t\t\tbuffer_size;\n\tu32\t\t\tstart_pos;\n\tu32\t\t\tend_pos;\t/*@buf addr*/\n};\n\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\nstruct la_adv_trig {\n\tboolean\t\t\tla_en_new_bbtrigger;\n\tboolean\t\t\tla_ori_bb_dis;\n\tu8\t\t\tla_and1_sel;\n\tu8\t\t\tla_and1_val;\n\tboolean\t\t\tla_and1_inv;\n\tu8\t\t\tla_and2_sel;\n\tu8\t\t\tla_and2_val;\n\tboolean\t\t\tla_and2_inv;\n\tu8\t\t\tla_and3_sel;\n\tu8\t\t\tla_and3_val;\n\tboolean\t\t\tla_and3_inv;\n\tu32\t\t\tla_and4_mask;\n\tu32\t\t\tla_and4_bitmap;\n\tboolean\t\t\tla_and4_inv;\n};\n#endif\n\nstruct rt_adcsmp {\n\tstruct rt_adcsmp_string\tadc_smp_buf;\n\tenum rt_adcsmp_state\tadc_smp_state;\n\tenum la_buff_mode\tla_buff_mode;\n\tenum la_dump_mode\tla_dump_mode;\n\tu8\t\t\tla_trig_mode;\n\tu32\t\t\tla_trig_sig_sel;\n\tu8\t\t\tla_dma_type;\n\tu32\t\t\tla_trigger_time;\n\t/*@1.BB mode: Dbg port header sel, 2.MAC mode: for reference mask*/\n\tu32\t\t\tla_mac_mask_or_hdr_sel;\n\tu32\t\t\tla_dbg_port;\n\tu8\t\t\tla_trigger_edge;\n\tu8\t\t\tla_smp_rate;\n\tu32\t\t\tla_count;\n\tu32\t\t\tsmp_number;\n\tu32\t\t\tsmp_number_max;\n\tu32\t\t\ttxff_page;\n\tboolean\t\t\tis_la_print;\n\tboolean\t\t\ten_fake_trig;\n#if (RTL8197F_SUPPORT)\n\tu32\t\t\tbackup_dma;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tu8\t\t\tla_work_item_index;\n\tRT_WORK_ITEM\t\tadc_smp_work_item;\n\tRT_WORK_ITEM\t\tadc_smp_work_item_1;\n#endif\n\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\tstruct la_adv_trig\tadv_trig_table;\n#endif\n};\n\n/* @ ============================================================\n *  Function Prototype\n *  ============================================================\n */\n\nvoid phydm_la_set(void *dm_void);\n\nvoid phydm_la_cmd(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t  u32 *_out_len);\n\nvoid phydm_la_stop(void *dm_void);\n\nvoid phydm_la_init(void *dm_void);\n\nvoid adc_smp_de_init(void *dm_void);\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\nvoid adc_smp_work_item_callback(void *context);\n#endif\n\n#if 0\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\nenum rt_status adc_smp_query(void *dm_void, ULONG info_buf_length,\n\t\t\t     void *info_buf, PULONG bytes_written);\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\nvoid adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused);\n\ns32 adc_smp_get_sample_counts(void *dm_void);\n\ns32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len,\n\t\t\t      u32 idx);\n#endif\n#endif\n\n#endif\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_antdect.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/* ************************************************************\n * include files\n * ************************************************************ */\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#ifdef CONFIG_ANT_DETECTION\n\n/* @IS_ANT_DETECT_SUPPORT_SINGLE_TONE(adapter)\n * IS_ANT_DETECT_SUPPORT_RSSI(adapter)\n * IS_ANT_DETECT_SUPPORT_PSD(adapter) */\n\n/* @1 [1. Single Tone method] =================================================== */\n\n/*@\n * Description:\n *\tSet Single/Dual Antenna default setting for products that do not do detection in advance.\n *\n * Added by Joseph, 2012.03.22\n *   */\nvoid odm_sw_ant_div_construct_scan_chnl(\n\tvoid *adapter,\n\tu8 scan_chnl)\n{\n}\n\nu8 odm_sw_ant_div_select_scan_chnl(\n\tvoid *adapter)\n{\n\treturn 0;\n}\n\nvoid odm_single_dual_antenna_default_setting(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;\n\tvoid *adapter = dm->adapter;\n\n\tu8 bt_ant_num = BT_GetPgAntNum(adapter);\n\t/* Set default antenna A and B status */\n\tif (bt_ant_num == 2) {\n\t\tdm_swat_table->ANTA_ON = true;\n\t\tdm_swat_table->ANTB_ON = true;\n\n\t} else if (bt_ant_num == 1) {\n\t\t/* Set antenna A as default */\n\t\tdm_swat_table->ANTA_ON = true;\n\t\tdm_swat_table->ANTB_ON = false;\n\n\t} else\n\t\tRT_ASSERT(false, (\"Incorrect antenna number!!\\n\"));\n}\n\n/* @2 8723A ANT DETECT\n *\n * Description:\n *\tImplement IQK single tone for RF DPK loopback and BB PSD scanning.\n *\tThis function is cooperated with BB team Neil.\n *\n * Added by Roger, 2011.12.15\n *   */\nboolean\nodm_single_dual_antenna_detection(\n\tvoid *dm_void,\n\tu8 mode)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tvoid *adapter = dm->adapter;\n\tstruct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;\n\tu32 current_channel, rf_loop_reg;\n\tu8 n;\n\tu32 reg88c, regc08, reg874, regc50, reg948, regb2c, reg92c, reg930, reg064, afe_rrx_wait_cca;\n\tu8 initial_gain = 0x5a;\n\tu32 PSD_report_tmp;\n\tu32 ant_a_report = 0x0, ant_b_report = 0x0, ant_0_report = 0x0;\n\tboolean is_result = true;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"%s============>\\n\", __func__);\n\n\tif (!(dm->support_ic_type & ODM_RTL8723B))\n\t\treturn is_result;\n\n\t/* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */\n\tif (!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(((PADAPTER)adapter)))\n\t\treturn is_result;\n\n\t/* @1 Backup Current RF/BB Settings */\n\n\tcurrent_channel = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);\n\trf_loop_reg = odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK);\n\tif (dm->support_ic_type & ODM_RTL8723B) {\n\t\treg92c = odm_get_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD);\n\t\treg930 = odm_get_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD);\n\t\treg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD);\n\t\tregb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);\n\t\treg064 = odm_get_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29));\n\t\todm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x1);\n\t\todm_set_bb_reg(dm, rfe_ctrl_anta_src, 0xff, 0x77);\n\t\todm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* @dbg 7 */\n\t\todm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0); /* @dbg 8 */\n\t\todm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x0);\n\t}\n\n\tODM_delay_us(10);\n\n\t/* Store A path Register 88c, c08, 874, c50 */\n\treg88c = odm_get_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD);\n\tregc08 = odm_get_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD);\n\treg874 = odm_get_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD);\n\tregc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);\n\n\t/* Store AFE Registers */\n\tif (dm->support_ic_type & ODM_RTL8723B)\n\t\tafe_rrx_wait_cca = odm_get_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD);\n\n\t/* Set PSD 128 pts */\n\todm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* @128 pts */\n\n\t/* To SET CH1 to do */\n\todm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* @channel 1 */\n\n\t/* @AFE all on step */\n\tif (dm->support_ic_type & ODM_RTL8723B)\n\t\todm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, 0x01c00016);\n\n\t/* @3 wire Disable */\n\todm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, 0xCCF000C0);\n\n\t/* @BB IQK setting */\n\todm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800E4);\n\todm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22208000);\n\n\t/* @IQK setting tone@ 4.34Mhz */\n\todm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008C1C);\n\todm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00);\n\n\t/* Page B init */\n\todm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x00080000);\n\todm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x0f600000);\n\todm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);\n\todm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1f);\n\tif (dm->support_ic_type & ODM_RTL8723B) {\n\t\todm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82150016);\n\t\todm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28150016);\n\t}\n\todm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d0);\n\todm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7f, initial_gain);\n\n\t/* @IQK Single tone start */\n\todm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000);\n\todm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);\n\todm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);\n\n\tODM_delay_us(10000);\n\n\t/* PSD report of antenna A */\n\tPSD_report_tmp = 0x0;\n\tfor (n = 0; n < 2; n++) {\n\t\tPSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain);\n\t\tif (PSD_report_tmp > ant_a_report)\n\t\t\tant_a_report = PSD_report_tmp;\n\t}\n\n\t/* @change to Antenna B */\n\tif (dm->support_ic_type & ODM_RTL8723B) {\n#if 0\n\t\t/* odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x2); */\n#endif\n\t\todm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);\n\t\todm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);\n\t}\n\n\tODM_delay_us(10);\n\n\t/* PSD report of antenna B */\n\tPSD_report_tmp = 0x0;\n\tfor (n = 0; n < 2; n++) {\n\t\tPSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain);\n\t\tif (PSD_report_tmp > ant_b_report)\n\t\t\tant_b_report = PSD_report_tmp;\n\t}\n\n\t/* @Close IQK Single Tone function */\n\todm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);\n\n\t/* @1 Return to antanna A */\n\tif (dm->support_ic_type & ODM_RTL8723B) {\n\t\t/* @external DPDT */\n\t\todm_set_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD, reg92c);\n\n\t\t/* @internal S0/S1 */\n\t\todm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);\n\t\todm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);\n\t\todm_set_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD, reg930);\n\t\todm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), reg064);\n\t}\n\n\todm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, reg88c);\n\todm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, regc08);\n\todm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, reg874);\n\todm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7F, 0x40);\n\todm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD, regc50);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, current_channel);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_loop_reg);\n\n\t/* Reload AFE Registers */\n\tif (dm->support_ic_type & ODM_RTL8723B)\n\t\todm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, afe_rrx_wait_cca);\n\n\tif (dm->support_ic_type & ODM_RTL8723B) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"psd_report_A[%d]= %d\\n\", 2416,\n\t\t\t  ant_a_report);\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"psd_report_B[%d]= %d\\n\", 2416,\n\t\t\t  ant_b_report);\n\n\t\t/* @2 Test ant B based on ant A is ON */\n\t\tif (ant_a_report >= 100 && ant_b_report >= 100 && ant_a_report <= 135 && ant_b_report <= 135) {\n\t\t\tu8 TH1 = 2, TH2 = 6;\n\n\t\t\tif ((ant_a_report - ant_b_report < TH1) || (ant_b_report - ant_a_report < TH1)) {\n\t\t\t\tdm_swat_table->ANTA_ON = true;\n\t\t\t\tdm_swat_table->ANTB_ON = true;\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"%s: Dual Antenna\\n\",\n\t\t\t\t\t  __func__);\n\t\t\t} else if (((ant_a_report - ant_b_report >= TH1) && (ant_a_report - ant_b_report <= TH2)) ||\n\t\t\t\t   ((ant_b_report - ant_a_report >= TH1) && (ant_b_report - ant_a_report <= TH2))) {\n\t\t\t\tdm_swat_table->ANTA_ON = false;\n\t\t\t\tdm_swat_table->ANTB_ON = false;\n\t\t\t\tis_result = false;\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"%s: Need to check again\\n\",\n\t\t\t\t\t  __func__);\n\t\t\t} else {\n\t\t\t\tdm_swat_table->ANTA_ON = true;\n\t\t\t\tdm_swat_table->ANTB_ON = false;\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"%s: Single Antenna\\n\", __func__);\n\t\t\t}\n\t\t\tdm->ant_detected_info.is_ant_detected = true;\n\t\t\tdm->ant_detected_info.db_for_ant_a = ant_a_report;\n\t\t\tdm->ant_detected_info.db_for_ant_b = ant_b_report;\n\t\t\tdm->ant_detected_info.db_for_ant_o = ant_0_report;\n\n\t\t} else {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"return false!!\\n\");\n\t\t\tis_result = false;\n\t\t}\n\t}\n\treturn is_result;\n}\n\n/* @1 [2. Scan AP RSSI method] ================================================== */\n\nboolean\nodm_sw_ant_div_check_before_link(\n\tvoid *dm_void)\n{\n#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)\n\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tvoid *adapter = dm->adapter;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\t//PMGNT_INFO\t\tmgnt_info = &adapter->MgntInfo;\n\tPMGNT_INFO mgnt_info = &(((PADAPTER)(adapter))->MgntInfo);\n\tstruct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\ts8 score = 0;\n\tPRT_WLAN_BSS p_tmp_bss_desc, p_test_bss_desc;\n\tu8 power_target_L = 9, power_target_H = 16;\n\tu8 tmp_power_diff = 0, power_diff = 0, avg_power_diff = 0, max_power_diff = 0, min_power_diff = 0xff;\n\tu16 index, counter = 0;\n\tstatic u8 scan_channel;\n\tu32 tmp_swas_no_link_bk_reg948;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\\n\",\n\t\t  dm->dm_swat_table.ANTA_ON, dm->dm_swat_table.ANTB_ON);\n\n\t/* @if(HP id) */\n\t{\n\t\tif (dm->dm_swat_table.rssi_ant_dect_result == true && dm->support_ic_type == ODM_RTL8723B) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"8723B RSSI-based Antenna Detection is done\\n\");\n\t\t\treturn false;\n\t\t}\n\n\t\tif (dm->support_ic_type == ODM_RTL8723B) {\n\t\t\tif (dm_swat_table->swas_no_link_bk_reg948 == 0xff)\n\t\t\t\tdm_swat_table->swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH);\n\t\t}\n\t}\n\n\tif (dm->adapter == NULL) { /* @For BSOD when plug/unplug fast.  //By YJ,120413 */\n\t\t/* The ODM structure is not initialized. */\n\t\treturn false;\n\t}\n\n\t/* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */\n\tif (!IS_ANT_DETECT_SUPPORT_RSSI(((PADAPTER)adapter)))\n\t\treturn false;\n\telse\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Antenna Detection: RSSI method\\n\");\n\n\t/* Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. */\n\todm_acquire_spin_lock(dm, RT_RF_STATE_SPINLOCK);\n\tif (hal_data->eRFPowerState != eRfOn || mgnt_info->RFChangeInProgress || mgnt_info->bMediaConnect) {\n\t\todm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);\n\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"%s: rf_change_in_progress(%x), e_rf_power_state(%x)\\n\",\n\t\t\t  __func__, mgnt_info->RFChangeInProgress,\n\t\t\t  hal_data->eRFPowerState);\n\n\t\tdm_swat_table->swas_no_link_state = 0;\n\n\t\treturn false;\n\t} else\n\t\todm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"dm_swat_table->swas_no_link_state = %d\\n\",\n\t\t  dm_swat_table->swas_no_link_state);\n\t/* @1 Run AntDiv mechanism \"Before Link\" part. */\n\tif (dm_swat_table->swas_no_link_state == 0) {\n\t\t/* @1 Prepare to do Scan again to check current antenna state. */\n\n\t\t/* Set check state to next step. */\n\t\tdm_swat_table->swas_no_link_state = 1;\n\n\t\t/* @Copy Current Scan list. */\n\t\tmgnt_info->tmpNumBssDesc = mgnt_info->NumBssDesc;\n\t\tPlatformMoveMemory((void *)mgnt_info->tmpbssDesc, (void *)mgnt_info->bssDesc, sizeof(RT_WLAN_BSS) * MAX_BSS_DESC);\n\n\t\t/* @Go back to scan function again. */\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"%s: Scan one more time\\n\",\n\t\t\t  __func__);\n\t\tmgnt_info->ScanStep = 0;\n\t\tmgnt_info->bScanAntDetect = true;\n\t\tscan_channel = odm_sw_ant_div_select_scan_chnl(adapter);\n\n\t\tif (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {\n\t\t\tif (fat_tab->rx_idle_ant == MAIN_ANT)\n\t\t\t\todm_update_rx_idle_ant(dm, AUX_ANT);\n\t\t\telse\n\t\t\t\todm_update_rx_idle_ant(dm, MAIN_ANT);\n\t\t\tif (scan_channel == 0) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"%s: No AP List Avaiable, Using ant(%s)\\n\",\n\t\t\t\t\t  __func__,\n\t\t\t\t\t  (fat_tab->rx_idle_ant == MAIN_ANT) ?\n\t\t\t\t\t  \"AUX_ANT\" : \"MAIN_ANT\");\n\n\t\t\t\tif (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {\n\t\t\t\t\tdm_swat_table->ant_5g = fat_tab->rx_idle_ant;\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"dm_swat_table->ant_5g=%s\\n\", (fat_tab->rx_idle_ant == MAIN_ANT) ? \"MAIN_ANT\" : \"AUX_ANT\");\n\t\t\t\t} else {\n\t\t\t\t\tdm_swat_table->ant_2g = fat_tab->rx_idle_ant;\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"dm_swat_table->ant_2g=%s\\n\", (fat_tab->rx_idle_ant == MAIN_ANT) ? \"MAIN_ANT\" : \"AUX_ANT\");\n\t\t\t\t}\n\t\t\t\treturn false;\n\t\t\t}\n\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"%s: Change to %s for testing.\\n\", __func__,\n\t\t\t\t  ((fat_tab->rx_idle_ant == MAIN_ANT) ?\n\t\t\t\t  \"MAIN_ANT\" : \"AUX_ANT\"));\n\t\t} else if (dm->support_ic_type & (ODM_RTL8723B)) {\n\t\t\t/*Switch Antenna to another one.*/\n\n\t\t\ttmp_swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH);\n\n\t\t\tif (dm_swat_table->cur_antenna == MAIN_ANT && tmp_swas_no_link_bk_reg948 == 0x200) {\n\t\t\t\todm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);\n\t\t\t\todm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);\n\t\t\t\tdm_swat_table->cur_antenna = AUX_ANT;\n\t\t\t} else {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"Reg[948]= (( %x )) was in wrong state\\n\",\n\t\t\t\t\t  tmp_swas_no_link_bk_reg948);\n\t\t\t\treturn false;\n\t\t\t}\n\t\t\tODM_delay_us(10);\n\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"%s: Change to (( %s-ant))  for testing.\\n\",\n\t\t\t\t  __func__,\n\t\t\t\t  (dm_swat_table->cur_antenna == MAIN_ANT) ?\n\t\t\t\t  \"MAIN\" : \"AUX\");\n\t\t}\n\n\t\todm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);\n\t\tPlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);\n\n\t\treturn true;\n\t} else { /* @dm_swat_table->swas_no_link_state == 1 */\n\t\t/* @1 ScanComple() is called after antenna swiched. */\n\t\t/* @1 Check scan result and determine which antenna is going */\n\t\t/* @1 to be used. */\n\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \" tmp_num_bss_desc= (( %d ))\\n\",\n\t\t\t  mgnt_info->tmpNumBssDesc); /* @debug for Dino */\n\n\t\tfor (index = 0; index < mgnt_info->tmpNumBssDesc; index++) {\n\t\t\tp_tmp_bss_desc = &mgnt_info->tmpbssDesc[index]; /* @Antenna 1 */\n\t\t\tp_test_bss_desc = &mgnt_info->bssDesc[index]; /* @Antenna 2 */\n\n\t\t\tif (PlatformCompareMemory(p_test_bss_desc->bdBssIdBuf, p_tmp_bss_desc->bdBssIdBuf, 6) != 0) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"%s: ERROR!! This shall not happen.\\n\",\n\t\t\t\t\t  __func__);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (dm->support_ic_type != ODM_RTL8723B) {\n\t\t\t\tif (p_tmp_bss_desc->ChannelNumber == scan_channel) {\n\t\t\t\t\tif (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) {\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"%s: Compare scan entry: score++\\n\", __func__);\n\t\t\t\t\t\tRT_PRINT_STR(COMP_SCAN, DBG_WARNING, \"GetScanInfo(): new Bss SSID:\", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"at ch %d, Original: %d, Test: %d\\n\\n\", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);\n\n\t\t\t\t\t\tscore++;\n\t\t\t\t\t\tPlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));\n\t\t\t\t\t} else if (p_tmp_bss_desc->RecvSignalPower < p_test_bss_desc->RecvSignalPower) {\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"%s: Compare scan entry: score--\\n\", __func__);\n\t\t\t\t\t\tRT_PRINT_STR(COMP_SCAN, DBG_WARNING, \"GetScanInfo(): new Bss SSID:\", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"at ch %d, Original: %d, Test: %d\\n\\n\", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);\n\t\t\t\t\t\tscore--;\n\t\t\t\t\t} else {\n\t\t\t\t\t\tif (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp < 5000) {\n\t\t\t\t\t\t\tRT_PRINT_STR(COMP_SCAN, DBG_WARNING, \"GetScanInfo(): new Bss SSID:\", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);\n\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"at ch %d, Original: %d, Test: %d\\n\", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);\n\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"The 2nd Antenna didn't get this AP\\n\\n\");\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else { /* @8723B */\n\t\t\t\tif (p_tmp_bss_desc->ChannelNumber == scan_channel) {\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"channel_number == scan_channel->(( %d ))\\n\", p_tmp_bss_desc->ChannelNumber);\n\n\t\t\t\t\tif (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { /* Pow(Ant1) > Pow(Ant2) */\n\t\t\t\t\t\tcounter++;\n\t\t\t\t\t\ttmp_power_diff = (u8)(p_tmp_bss_desc->RecvSignalPower - p_test_bss_desc->RecvSignalPower);\n\t\t\t\t\t\tpower_diff = power_diff + tmp_power_diff;\n\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Original: %d, Test: %d\\n\", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);\n\t\t\t\t\t\tPHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, \"SSID:\", p_tmp_bss_desc->bdSsIdBuf);\n\t\t\t\t\t\tPHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, \"BSSID:\", p_tmp_bss_desc->bdSsIdBuf);\n\n#if 0\n\t\t\t\t\t\t/* PHYDM_DBG(dm,DBG_ANT_DIV, \"tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d))\\n\", tmp_power_diff,max_power_diff,min_power_diff); */\n#endif\n\t\t\t\t\t\tif (tmp_power_diff > max_power_diff)\n\t\t\t\t\t\t\tmax_power_diff = tmp_power_diff;\n\t\t\t\t\t\tif (tmp_power_diff < min_power_diff)\n\t\t\t\t\t\t\tmin_power_diff = tmp_power_diff;\n#if 0\n\t\t\t\t\t\t/* PHYDM_DBG(dm,DBG_ANT_DIV, \"max_power_diff: (( %d)),min_power_diff: (( %d))\\n\",max_power_diff,min_power_diff); */\n#endif\n\n\t\t\t\t\t\tPlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));\n\t\t\t\t\t} else if (p_test_bss_desc->RecvSignalPower > p_tmp_bss_desc->RecvSignalPower) { /* Pow(Ant1) < Pow(Ant2) */\n\t\t\t\t\t\tcounter++;\n\t\t\t\t\t\ttmp_power_diff = (u8)(p_test_bss_desc->RecvSignalPower - p_tmp_bss_desc->RecvSignalPower);\n\t\t\t\t\t\tpower_diff = power_diff + tmp_power_diff;\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Original: %d, Test: %d\\n\", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);\n\t\t\t\t\t\tPHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, \"SSID:\", p_tmp_bss_desc->bdSsIdBuf);\n\t\t\t\t\t\tPHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, \"BSSID:\", p_tmp_bss_desc->bdSsIdBuf);\n\t\t\t\t\t\tif (tmp_power_diff > max_power_diff)\n\t\t\t\t\t\t\tmax_power_diff = tmp_power_diff;\n\t\t\t\t\t\tif (tmp_power_diff < min_power_diff)\n\t\t\t\t\t\t\tmin_power_diff = tmp_power_diff;\n\t\t\t\t\t} else { /* Pow(Ant1) = Pow(Ant2) */\n\t\t\t\t\t\tif (p_test_bss_desc->bdTstamp > p_tmp_bss_desc->bdTstamp) { /* Stamp(Ant1) < Stamp(Ant2) */\n\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"time_diff: %lld\\n\", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000);\n\t\t\t\t\t\t\tif (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp > 5000) {\n\t\t\t\t\t\t\t\tcounter++;\n\t\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Original: %d, Test: %d\\n\", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);\n\t\t\t\t\t\t\t\tPHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, \"SSID:\", p_tmp_bss_desc->bdSsIdBuf);\n\t\t\t\t\t\t\t\tPHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, \"BSSID:\", p_tmp_bss_desc->bdSsIdBuf);\n\t\t\t\t\t\t\t\tmin_power_diff = 0;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t} else\n\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[Error !!!]: Time_diff: %lld\\n\", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {\n\t\t\tif (mgnt_info->NumBssDesc != 0 && score < 0) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"%s: Using ant(%s)\\n\", __func__,\n\t\t\t\t\t  (fat_tab->rx_idle_ant == MAIN_ANT) ?\n\t\t\t\t\t  \"MAIN_ANT\" : \"AUX_ANT\");\n\t\t\t} else {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"%s: Remain ant(%s)\\n\", __func__,\n\t\t\t\t\t  (fat_tab->rx_idle_ant == MAIN_ANT) ?\n\t\t\t\t\t  \"AUX_ANT\" : \"MAIN_ANT\");\n\n\t\t\t\tif (fat_tab->rx_idle_ant == MAIN_ANT)\n\t\t\t\t\todm_update_rx_idle_ant(dm, AUX_ANT);\n\t\t\t\telse\n\t\t\t\t\todm_update_rx_idle_ant(dm, MAIN_ANT);\n\t\t\t}\n\n\t\t\tif (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {\n\t\t\t\tdm_swat_table->ant_5g = fat_tab->rx_idle_ant;\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"dm_swat_table->ant_5g=%s\\n\",\n\t\t\t\t\t  (fat_tab->rx_idle_ant == MAIN_ANT) ?\n\t\t\t\t\t  \"MAIN_ANT\" : \"AUX_ANT\");\n\t\t\t} else {\n\t\t\t\tdm_swat_table->ant_2g = fat_tab->rx_idle_ant;\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"dm_swat_table->ant_2g=%s\\n\",\n\t\t\t\t\t  (fat_tab->rx_idle_ant == MAIN_ANT) ?\n\t\t\t\t\t  \"MAIN_ANT\" : \"AUX_ANT\");\n\t\t\t}\n\t\t} else if (dm->support_ic_type == ODM_RTL8723B) {\n\t\t\tif (counter == 0) {\n\t\t\t\tif (dm->dm_swat_table.pre_aux_fail_detec == false) {\n\t\t\t\t\tdm->dm_swat_table.pre_aux_fail_detec = true;\n\t\t\t\t\tdm->dm_swat_table.rssi_ant_dect_result = false;\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] ->  Scan Target-channel again\\n\");\n\n\t\t\t\t\t/* @3 [ Scan again ] */\n\t\t\t\t\todm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);\n\t\t\t\t\tPlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);\n\t\t\t\t\treturn true;\n\t\t\t\t} else { /* pre_aux_fail_detec == true */\n\t\t\t\t\t/* @2 [ Single Antenna ] */\n\t\t\t\t\tdm->dm_swat_table.pre_aux_fail_detec = false;\n\t\t\t\t\tdm->dm_swat_table.rssi_ant_dect_result = true;\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"counter=(( 0 )) , [[  Still cannot find any AP ]]\\n\");\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"%s: Single antenna\\n\", __func__);\n\t\t\t\t}\n\t\t\t\tdm->dm_swat_table.aux_fail_detec_counter++;\n\t\t\t} else {\n\t\t\t\tdm->dm_swat_table.pre_aux_fail_detec = false;\n\n\t\t\t\tif (counter == 3) {\n\t\t\t\t\tavg_power_diff = ((power_diff - max_power_diff - min_power_diff) >> 1) + ((max_power_diff + min_power_diff) >> 2);\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"counter: (( %d )) ,  power_diff: (( %d ))\\n\", counter, power_diff);\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) ,  min_power_diff: (( %d ))\\n\", avg_power_diff, max_power_diff, min_power_diff);\n\t\t\t\t} else if (counter >= 4) {\n\t\t\t\t\tavg_power_diff = (power_diff - max_power_diff - min_power_diff) / (counter - 2);\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"counter: (( %d )) ,  power_diff: (( %d ))\\n\", counter, power_diff);\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) ,  min_power_diff: (( %d ))\\n\", avg_power_diff, max_power_diff, min_power_diff);\n\n\t\t\t\t} else { /* @counter==1,2 */\n\t\t\t\t\tavg_power_diff = power_diff / counter;\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"avg_power_diff: (( %d )) , counter: (( %d )) ,  power_diff: (( %d ))\\n\", avg_power_diff, counter, power_diff);\n\t\t\t\t}\n\n\t\t\t\t/* @2 [ Retry ] */\n\t\t\t\tif (avg_power_diff >= power_target_L && avg_power_diff <= power_target_H) {\n\t\t\t\t\tdm->dm_swat_table.retry_counter++;\n\n\t\t\t\t\tif (dm->dm_swat_table.retry_counter <= 3) {\n\t\t\t\t\t\tdm->dm_swat_table.rssi_ant_dect_result = false;\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[[ Low confidence result ]] avg_power_diff= (( %d ))  ->  Scan Target-channel again ]]\\n\", avg_power_diff);\n\n\t\t\t\t\t\t/* @3 [ Scan again ] */\n\t\t\t\t\t\todm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);\n\t\t\t\t\t\tPlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);\n\t\t\t\t\t\treturn true;\n\t\t\t\t\t} else {\n\t\t\t\t\t\tdm->dm_swat_table.rssi_ant_dect_result = true;\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[[ Still Low confidence result ]]  (( retry_counter > 3 ))\\n\");\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"%s: Single antenna\\n\", __func__);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t/* @2 [ Dual Antenna ] */\n\t\t\t\telse if ((mgnt_info->NumBssDesc != 0) && (avg_power_diff < power_target_L)) {\n\t\t\t\t\tdm->dm_swat_table.rssi_ant_dect_result = true;\n\t\t\t\t\tif (dm->dm_swat_table.ANTB_ON == false) {\n\t\t\t\t\t\tdm->dm_swat_table.ANTA_ON = true;\n\t\t\t\t\t\tdm->dm_swat_table.ANTB_ON = true;\n\t\t\t\t\t}\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"%s: Dual antenna\\n\", __func__);\n\t\t\t\t\tdm->dm_swat_table.dual_ant_counter++;\n\n\t\t\t\t\t/* set bt coexDM from 1ant coexDM to 2ant coexDM */\n\t\t\t\t\tBT_SetBtCoexAntNum(adapter, BT_COEX_ANT_TYPE_DETECTED, 2);\n\n\t\t\t\t\t/* @3 [ Init antenna diversity ] */\n\t\t\t\t\tdm->support_ability |= ODM_BB_ANT_DIV;\n\t\t\t\t\todm_ant_div_init(dm);\n\t\t\t\t}\n\t\t\t\t/* @2 [ Single Antenna ] */\n\t\t\t\telse if (avg_power_diff > power_target_H) {\n\t\t\t\t\tdm->dm_swat_table.rssi_ant_dect_result = true;\n\t\t\t\t\tif (dm->dm_swat_table.ANTB_ON == true) {\n\t\t\t\t\t\tdm->dm_swat_table.ANTA_ON = true;\n\t\t\t\t\t\tdm->dm_swat_table.ANTB_ON = false;\n#if 0\n\t\t\t\t\t\t/* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 1); */\n#endif\n\t\t\t\t\t}\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"%s: Single antenna\\n\", __func__);\n\t\t\t\t\tdm->dm_swat_table.single_ant_counter++;\n\t\t\t\t}\n\t\t\t}\n#if 0\n\t\t\t/* PHYDM_DBG(dm,DBG_ANT_DIV, \"is_result=(( %d ))\\n\",dm->dm_swat_table.rssi_ant_dect_result); */\n#endif\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\\n\\n\\n\",\n\t\t\t\t  dm->dm_swat_table.dual_ant_counter,\n\t\t\t\t  dm->dm_swat_table.single_ant_counter,\n\t\t\t\t  dm->dm_swat_table.retry_counter,\n\t\t\t\t  dm->dm_swat_table.aux_fail_detec_counter);\n\n\t\t\t/* @2 recover the antenna setting */\n\n\t\t\tif (dm->dm_swat_table.ANTB_ON == false)\n\t\t\t\todm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, (dm_swat_table->swas_no_link_bk_reg948));\n\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"is_result=(( %d )), Recover  Reg[948]= (( %x ))\\n\\n\",\n\t\t\t\t  dm->dm_swat_table.rssi_ant_dect_result,\n\t\t\t\t  dm_swat_table->swas_no_link_bk_reg948);\n\t\t}\n\n\t\t/* @Check state reset to default and wait for next time. */\n\t\tdm_swat_table->swas_no_link_state = 0;\n\t\tmgnt_info->bScanAntDetect = false;\n\n\t\treturn false;\n\t}\n\n#else\n\treturn false;\n#endif\n\n\treturn false;\n}\n\n/* @1 [3. PSD method] ========================================================== */\nvoid odm_single_dual_antenna_detection_psd(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 channel_ori;\n\tu8 initial_gain = 0x36;\n\tu8 tone_idx;\n\tu8 tone_lenth_1 = 7, tone_lenth_2 = 4;\n\tu16 tone_idx_1[7] = {88, 104, 120, 8, 24, 40, 56};\n\tu16 tone_idx_2[4] = {8, 24, 40, 56};\n\tu32 psd_report_main[11] = {0}, psd_report_aux[11] = {0};\n\t/* u8\ttone_lenth_1=4, tone_lenth_2=2; */\n\t/* u16\ttone_idx_1[4]={88, 120, 24, 56}; */\n\t/* u16\ttone_idx_2[2]={ 24,  56}; */\n\t/* u32\tpsd_report_main[6]={0}, psd_report_aux[6]={0}; */\n\n\tu32 PSD_report_temp, max_psd_report_main = 0, max_psd_report_aux = 0;\n\tu32 PSD_power_threshold;\n\tu32 main_psd_result = 0, aux_psd_result = 0;\n\tu32 regc50, reg948, regb2c, regc14, reg908;\n\tu32 i = 0, test_num = 8;\n\n\tif (dm->support_ic_type != ODM_RTL8723B)\n\t\treturn;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"%s============>\\n\", __func__);\n\n\t/* @2 [ Backup Current RF/BB Settings ] */\n\n\tchannel_ori = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);\n\treg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD);\n\tregb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);\n\tregc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);\n\tregc14 = odm_get_bb_reg(dm, R_0xc14, MASKDWORD);\n\treg908 = odm_get_bb_reg(dm, R_0x908, MASKDWORD);\n\n\t/* @2 [ setting for doing PSD function (CH4)] */\n\todm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 0); /* @disable whole CCK block */\n\todm_write_1byte(dm, REG_TXPAUSE, 0xFF); /* Turn off TX  ->  Pause TX Queue */\n\todm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */\n\n\t/* PHYTXON while loop */\n\todm_set_bb_reg(dm, R_0x908, MASKDWORD, 0x803);\n\twhile (odm_get_bb_reg(dm, R_0xdf4, BIT(6))) {\n\t\ti++;\n\t\tif (i > 1000000) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"Wait in %s() more than %d times!\\n\",\n\t\t\t\t  __FUNCTION__, i);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\todm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain);\n\todm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */\n\todm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable    88c[23:20]=0xf */\n\todm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt\t */ /* Set PSD 128 ptss */\n\tODM_delay_us(3000);\n\n\t/* @2 [ Doing PSD Function in (CH4)] */\n\n\t/* @Antenna A */\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Switch to Main-ant   (CH4)\\n\");\n\todm_set_bb_reg(dm, R_0x948, 0xfff, 0x200);\n\tODM_delay_us(10);\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"dbg\\n\");\n\tfor (i = 0; i < test_num; i++) {\n\t\tfor (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {\n\t\t\tPSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);\n\t\t\t/* @if(  PSD_report_temp>psd_report_main[tone_idx]  ) */\n\t\t\tpsd_report_main[tone_idx] += PSD_report_temp;\n\t\t}\n\t}\n\t/* @Antenna B */\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Switch to Aux-ant   (CH4)\\n\");\n\todm_set_bb_reg(dm, R_0x948, 0xfff, 0x280);\n\tODM_delay_us(10);\n\tfor (i = 0; i < test_num; i++) {\n\t\tfor (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {\n\t\t\tPSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);\n\t\t\t/* @if(  PSD_report_temp>psd_report_aux[tone_idx]  ) */\n\t\t\tpsd_report_aux[tone_idx] += PSD_report_temp;\n\t\t}\n\t}\n\t/* @2 [ Doing PSD Function in (CH8)] */\n\n\todm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable    88c[23:20]=0x0 */\n\tODM_delay_us(3000);\n\n\todm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain);\n\todm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */\n\n\todm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable    88c[23:20]=0xf */\n\tODM_delay_us(3000);\n\n\t/* @Antenna A */\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Switch to Main-ant   (CH8)\\n\");\n\todm_set_bb_reg(dm, R_0x948, 0xfff, 0x200);\n\tODM_delay_us(10);\n\n\tfor (i = 0; i < test_num; i++) {\n\t\tfor (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {\n\t\t\tPSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);\n\t\t\t/* @if(  PSD_report_temp>psd_report_main[tone_idx]  ) */\n\t\t\tpsd_report_main[tone_lenth_1 + tone_idx] += PSD_report_temp;\n\t\t}\n\t}\n\n\t/* @Antenna B */\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Switch to Aux-ant   (CH8)\\n\");\n\todm_set_bb_reg(dm, R_0x948, 0xfff, 0x280);\n\tODM_delay_us(10);\n\n\tfor (i = 0; i < test_num; i++) {\n\t\tfor (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {\n\t\t\tPSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);\n\t\t\t/* @if(  PSD_report_temp>psd_report_aux[tone_idx]  ) */\n\t\t\tpsd_report_aux[tone_lenth_1 + tone_idx] += PSD_report_temp;\n\t\t}\n\t}\n\n\t/* @2 [ Calculate Result ] */\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"\\nMain PSD Result: (ALL)\\n\");\n\tfor (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[Tone-%d]: %d,\\n\", (tone_idx + 1),\n\t\t\t  psd_report_main[tone_idx]);\n\t\tmain_psd_result += psd_report_main[tone_idx];\n\t\tif (psd_report_main[tone_idx] > max_psd_report_main)\n\t\t\tmax_psd_report_main = psd_report_main[tone_idx];\n\t}\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"--------------------------- \\nTotal_Main= (( %d ))\\n\",\n\t\t  main_psd_result);\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"MAX_Main = (( %d ))\\n\",\n\t\t  max_psd_report_main);\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"\\nAux PSD Result: (ALL)\\n\");\n\tfor (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[Tone-%d]: %d,\\n\", (tone_idx + 1),\n\t\t\t  psd_report_aux[tone_idx]);\n\t\taux_psd_result += psd_report_aux[tone_idx];\n\t\tif (psd_report_aux[tone_idx] > max_psd_report_aux)\n\t\t\tmax_psd_report_aux = psd_report_aux[tone_idx];\n\t}\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"--------------------------- \\nTotal_Aux= (( %d ))\\n\",\n\t\t  aux_psd_result);\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"MAX_Aux = (( %d ))\\n\\n\",\n\t\t  max_psd_report_aux);\n\n\t/* @main_psd_result=main_psd_result-max_psd_report_main; */\n\t/* @aux_psd_result=aux_psd_result-max_psd_report_aux; */\n\tPSD_power_threshold = (main_psd_result * 7) >> 3;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\\n\",\n\t\t  main_psd_result, aux_psd_result, PSD_power_threshold);\n\n\t/* @3 [ Dual Antenna ] */\n\tif (aux_psd_result >= PSD_power_threshold) {\n\t\tif (dm->dm_swat_table.ANTB_ON == false) {\n\t\t\tdm->dm_swat_table.ANTA_ON = true;\n\t\t\tdm->dm_swat_table.ANTB_ON = true;\n\t\t}\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"odm_sw_ant_div_check_before_link(): Dual antenna\\n\");\n\n#if 0\n\t\t/* set bt coexDM from 1ant coexDM to 2ant coexDM */\n\t\t/* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */\n#endif\n\n\t\t/* @Init antenna diversity */\n\t\tdm->support_ability |= ODM_BB_ANT_DIV;\n\t\todm_ant_div_init(dm);\n\t}\n\t/* @3 [ Single Antenna ] */\n\telse {\n\t\tif (dm->dm_swat_table.ANTB_ON == true) {\n\t\t\tdm->dm_swat_table.ANTA_ON = true;\n\t\t\tdm->dm_swat_table.ANTB_ON = false;\n\t\t}\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"odm_sw_ant_div_check_before_link(): Single antenna\\n\");\n\t}\n\n\t/* @2 [ Recover all parameters ] */\n\n\todm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, channel_ori);\n\todm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable    88c[23:20]=0x0 */\n\todm_set_bb_reg(dm, R_0xc50, 0x7f, regc50);\n\n\todm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);\n\todm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);\n\n\todm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 1); /* @enable whole CCK block */\n\todm_write_1byte(dm, REG_TXPAUSE, 0x0); /* Turn on TX\t */ /* Resume TX Queue */\n\todm_set_bb_reg(dm, R_0xc14, MASKDWORD, regc14); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */\n\todm_set_bb_reg(dm, R_0x908, MASKDWORD, reg908);\n\n\treturn;\n}\n\nvoid odm_sw_ant_detect_init(void *dm_void)\n{\n#if (RTL8723B_SUPPORT == 1)\n\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;\n\n\tif (dm->support_ic_type != ODM_RTL8723B)\n\t\treturn;\n\n\t/* @dm_swat_table->pre_antenna = MAIN_ANT; */\n\t/* @dm_swat_table->cur_antenna = MAIN_ANT; */\n\tdm_swat_table->swas_no_link_state = 0;\n\tdm_swat_table->pre_aux_fail_detec = false;\n\tdm_swat_table->swas_no_link_bk_reg948 = 0xff;\n\n#ifdef CONFIG_PSD_TOOL\n\tphydm_psd_init(dm);\n#endif\n#endif\n}\n#endif\n\n"
  },
  {
    "path": "hal/phydm/phydm_antdect.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDMANTDECT_H__\n#define __PHYDMANTDECT_H__\n\n#define ANTDECT_VERSION \"2.1\"\n\n#if (defined(CONFIG_ANT_DETECTION))\n/* @#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */\n/* @ANT Test */\n#define ANTTESTALL 0x00 /*@ant A or B will be Testing*/\n#define ANTTESTA 0x01 /*@ant A will be Testing*/\n#define ANTTESTB 0x02 /*@ant B will be testing*/\n\n#define MAX_ANTENNA_DETECTION_CNT 10\n\nstruct _ANT_DETECTED_INFO {\n\tboolean is_ant_detected;\n\tu32 db_for_ant_a;\n\tu32 db_for_ant_b;\n\tu32 db_for_ant_o;\n};\n\nenum dm_swas {\n\tantenna_a = 1,\n\tantenna_b = 2,\n\tantenna_max = 3,\n};\n\n/* @1 [1. Single Tone method] =================================================== */\n\nvoid odm_single_dual_antenna_default_setting(\n\tvoid *dm_void);\n\nboolean\nodm_single_dual_antenna_detection(\n\tvoid *dm_void,\n\tu8 mode);\n\n/* @1 [2. Scan AP RSSI method] ================================================== */\n\n#define sw_ant_div_check_before_link odm_sw_ant_div_check_before_link\n\nboolean\nodm_sw_ant_div_check_before_link(\n\tvoid *dm_void);\n\n/* @1 [3. PSD method] ========================================================== */\n\nvoid odm_single_dual_antenna_detection_psd(\n\tvoid *dm_void);\n\nvoid odm_sw_ant_detect_init(void *dm_void);\n#endif\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_antdiv.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*************************************************************\n * include files\n ************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n/*******************************************************\n * when antenna test utility is on or some testing need to disable antenna\n * diversity call this function to disable all ODM related mechanisms which\n * will switch antenna.\n *****************************************************\n */\n#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\nvoid odm_stop_antenna_switch_dm(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\t/* @disable ODM antenna diversity */\n\tdm->support_ability &= ~ODM_BB_ANT_DIV;\n\tif (fat_tab->div_path_type == ANT_PATH_A)\n\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);\n\telse if (fat_tab->div_path_type == ANT_PATH_B)\n\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);\n\telse if (fat_tab->div_path_type == ANT_PATH_AB)\n\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);\n\todm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"STOP Antenna Diversity\\n\");\n}\n\nvoid phydm_enable_antenna_diversity(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tdm->support_ability |= ODM_BB_ANT_DIV;\n\tdm->antdiv_select = 0;\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"AntDiv is enabled & Re-Init AntDiv\\n\");\n\todm_antenna_diversity_init(dm);\n}\n\nvoid odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C,...*/)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type == ODM_RTL8723B) {\n\t\tif (ant_setting == 0) /* @ant A*/\n\t\t\todm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000000);\n\t\telse if (ant_setting == 1)\n\t\t\todm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000280);\n\t} else if (dm->support_ic_type == ODM_RTL8723D) {\n\t\tif (ant_setting == 0) /* @ant A*/\n\t\t\todm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0000);\n\t\telse if (ant_setting == 1)\n\t\t\todm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0280);\n\t}\n}\n\n/* ****************************************************** */\n\nvoid odm_sw_ant_div_rest_after_link(void *dm_void)\n{\n#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct sw_antenna_switch *swat_tab = &dm->dm_swat_table;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tu32 i;\n\n\tif (dm->ant_div_type == S0S1_SW_ANTDIV) {\n\t\tswat_tab->try_flag = SWAW_STEP_INIT;\n\t\tswat_tab->rssi_trying = 0;\n\t\tswat_tab->double_chk_flag = 0;\n\t\tfat_tab->rx_idle_ant = MAIN_ANT;\n\n\t\tfor (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)\n\t\t\tphydm_antdiv_reset_statistic(dm, i);\n\t}\n\n#endif\n}\n\nvoid phydm_n_on_off(void *dm_void, u8 swch, u8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\tif (path == ANT_PATH_A) {\n\t\todm_set_bb_reg(dm, R_0xc50, BIT(7), swch);\n\t} else if (path == ANT_PATH_B) {\n\t\todm_set_bb_reg(dm, R_0xc58, BIT(7), swch);\n\t} else if (path == ANT_PATH_AB) {\n\t\todm_set_bb_reg(dm, R_0xc50, BIT(7), swch);\n\t\todm_set_bb_reg(dm, R_0xc58, BIT(7), swch);\n\t}\n\todm_set_bb_reg(dm, R_0xa00, BIT(15), swch);\n#if (RTL8723D_SUPPORT == 1)\n\t/*@Mingzhi 2017-05-08*/\n\tif (dm->support_ic_type == ODM_RTL8723D) {\n\t\tif (swch == ANTDIV_ON) {\n\t\t\todm_set_bb_reg(dm, R_0xce0, BIT(1), 1);\n\t\t\todm_set_bb_reg(dm, R_0x948, BIT(6), 1);\n\t\t\t/*@1:HW ctrl  0:SW ctrl*/\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0xce0, BIT(1), 0);\n\t\t\todm_set_bb_reg(dm, R_0x948, BIT(6), 0);\n\t\t\t/*@1:HW ctrl  0:SW ctrl*/\n\t\t}\n\t}\n#endif\n}\n\nvoid phydm_ac_on_off(void *dm_void, u8 swch, u8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\tif (dm->support_ic_type & ODM_RTL8812) {\n\t\todm_set_bb_reg(dm, R_0xc50, BIT(7), swch);\n\t\t/* OFDM AntDiv function block enable */\n\t\todm_set_bb_reg(dm, R_0xa00, BIT(15), swch);\n\t\t/* @CCK AntDiv function block enable */\n\t} else if (dm->support_ic_type & ODM_RTL8822B) {\n\t\todm_set_bb_reg(dm, R_0x800, BIT(25), swch);\n\t\todm_set_bb_reg(dm, R_0xa00, BIT(15), swch);\n\t\tif (path == ANT_PATH_A) {\n\t\t\todm_set_bb_reg(dm, R_0xc50, BIT(7), swch);\n\t\t} else if (path == ANT_PATH_B) {\n\t\t\todm_set_bb_reg(dm, R_0xe50, BIT(7), swch);\n\t\t} else if (path == ANT_PATH_AB) {\n\t\t\todm_set_bb_reg(dm, R_0xc50, BIT(7), swch);\n\t\t\todm_set_bb_reg(dm, R_0xe50, BIT(7), swch);\n\t\t}\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x8d4, BIT(24), swch);\n\t\t/* OFDM AntDiv function block enable */\n\n\t\tif (dm->cut_version >= ODM_CUT_C &&\n\t\t    dm->support_ic_type == ODM_RTL8821 &&\n\t\t    dm->ant_div_type != S0S1_SW_ANTDIV) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"(Turn %s) CCK HW-AntDiv\\n\",\n\t\t\t\t  (swch == ANTDIV_ON) ? \"ON\" : \"OFF\");\n\t\t\todm_set_bb_reg(dm, R_0x800, BIT(25), swch);\n\t\t\todm_set_bb_reg(dm, R_0xa00, BIT(15), swch);\n\t\t\t/* @CCK AntDiv function block enable */\n\t\t} else if (dm->support_ic_type == ODM_RTL8821C) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"(Turn %s) CCK HW-AntDiv\\n\",\n\t\t\t\t  (swch == ANTDIV_ON) ? \"ON\" : \"OFF\");\n\t\t\todm_set_bb_reg(dm, R_0x800, BIT(25), swch);\n\t\t\todm_set_bb_reg(dm, R_0xa00, BIT(15), swch);\n\t\t\t/* @CCK AntDiv function block enable */\n\t\t}\n\t}\n}\n\nvoid odm_ant_div_on_off(void *dm_void, u8 swch, u8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\tif (fat_tab->ant_div_on_off != swch) {\n\t\tif (dm->ant_div_type == S0S1_SW_ANTDIV)\n\t\t\treturn;\n\n\t\tif (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"(( Turn %s )) N-Series HW-AntDiv block\\n\",\n\t\t\t\t  (swch == ANTDIV_ON) ? \"ON\" : \"OFF\");\n\t\t\tphydm_n_on_off(dm, swch, path);\n\n\t\t} else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"(( Turn %s )) AC-Series HW-AntDiv block\\n\",\n\t\t\t\t  (swch == ANTDIV_ON) ? \"ON\" : \"OFF\");\n\t\t\tphydm_ac_on_off(dm, swch, path);\n\t\t}\n\t}\n\tfat_tab->ant_div_on_off = swch;\n}\n\nvoid odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tu8 enable;\n\n\tif (fat_tab->b_fix_tx_ant == NO_FIX_TX_ANT)\n\t\tenable = (swch == TX_BY_DESC) ? 1 : 0;\n\telse\n\t\tenable = 0; /*@Force TX by Reg*/\n\n\tif (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {\n\t\tif (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)\n\t\t\todm_set_bb_reg(dm, R_0x80c, BIT(21), enable);\n\t\telse if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT)\n\t\t\todm_set_bb_reg(dm, R_0x900, BIT(18), enable);\n\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[AntDiv] TX_Ant_BY (( %s ))\\n\",\n\t\t\t  (enable == TX_BY_DESC) ? \"DESC\" : \"REG\");\n\t}\n}\n\nvoid phydm_antdiv_reset_statistic(void *dm_void, u32 macid)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\tfat_tab->main_sum[macid] = 0;\n\tfat_tab->aux_sum[macid] = 0;\n\tfat_tab->main_cnt[macid] = 0;\n\tfat_tab->aux_cnt[macid] = 0;\n\tfat_tab->main_sum_cck[macid] = 0;\n\tfat_tab->aux_sum_cck[macid] = 0;\n\tfat_tab->main_cnt_cck[macid] = 0;\n\tfat_tab->aux_cnt_cck[macid] = 0;\n}\n\nvoid phydm_fast_training_enable(void *dm_void, u8 swch)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 enable;\n\n\tif (swch == FAT_ON)\n\t\tenable = 1;\n\telse\n\t\tenable = 0;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Fast ant Training_en = ((%d))\\n\", enable);\n\n\tif (dm->support_ic_type == ODM_RTL8188E) {\n\t\todm_set_bb_reg(dm, R_0xe08, BIT(16), enable);\n\t\t\t/*@enable fast training*/\n\t} else if (dm->support_ic_type == ODM_RTL8192E) {\n\t\todm_set_bb_reg(dm, R_0xb34, BIT(28), enable);\n\t\t\t/*@enable fast training (path-A)*/\n#if 0\n\t\todm_set_bb_reg(dm, R_0xb34, BIT(29), enable);\n\t\t\t/*enable fast training (path-B)*/\n#endif\n\t} else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8822B)) {\n\t\todm_set_bb_reg(dm, R_0x900, BIT(19), enable);\n\t\t\t/*@enable fast training */\n\t}\n}\n\nvoid phydm_keep_rx_ack_ant_by_tx_ant_time(void *dm_void, u32 time)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\t/* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/\n\tif (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)\n\t\todm_set_bb_reg(dm, R_0xe20, 0xf00000, time);\n\telse if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT)\n\t\todm_set_bb_reg(dm, R_0x818, 0xf00000, time);\n}\n\nvoid phydm_update_rx_idle_ac(void *dm_void, u8 ant, u32 default_ant,\n\t\t\t     u32 optional_ant, u32 default_tx_ant)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tu16 value16 = odm_read_2byte(dm, ODM_REG_TRMUX_11AC + 2);\n\t/* @2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to  */\n\t/* @prevnt incorrect 0xc08 bit0-15.We still not know why it is changed*/\n\tvalue16 &= ~(BIT(11) | BIT(10) | BIT(9) | BIT(8) | BIT(7) | BIT(6) |\n\t\t   BIT(5) | BIT(4) | BIT(3));\n\tvalue16 |= ((u16)default_ant << 3);\n\tvalue16 |= ((u16)optional_ant << 6);\n\tvalue16 |= ((u16)default_tx_ant << 9);\n\todm_write_2byte(dm, ODM_REG_TRMUX_11AC + 2, value16);\n#if 0\n\todm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0x380000, default_ant);\n\t\t/* @Default RX */\n\todm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0x1c00000, optional_ant);\n\t\t/* Optional RX */\n\todm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0xe000000, default_ant);\n\t\t/* @Default TX */\n#endif\n}\n\nvoid phydm_update_rx_idle_n(void *dm_void, u8 ant, u32 default_ant,\n\t\t\t    u32 optional_ant, u32 default_tx_ant)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 value32;\n\n\tif (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F)) {\n\t\todm_set_bb_reg(dm, R_0xb38, 0x38, default_ant);\n\t\t\t/* @Default RX */\n\t\todm_set_bb_reg(dm, R_0xb38, 0x1c0, optional_ant);\n\t\t\t/* Optional RX */\n\t\todm_set_bb_reg(dm, R_0x860, 0x7000, default_ant);\n\t\t\t/* @Default TX */\n#if (RTL8723B_SUPPORT == 1)\n\t} else if (dm->support_ic_type == ODM_RTL8723B) {\n\t\tvalue32 = odm_get_bb_reg(dm, R_0x948, 0xFFF);\n\n\t\tif (value32 != 0x280)\n\t\t\todm_update_rx_idle_ant_8723b(dm, ant, default_ant,\n\t\t\t\t\t\t     optional_ant);\n\t\telse\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\\n\");\n#endif\n\n#if (RTL8723D_SUPPORT == 1) /*@Mingzhi 2017-05-08*/\n\t} else if (dm->support_ic_type == ODM_RTL8723D) {\n\t\tphydm_set_tx_ant_pwr_8723d(dm, ant);\n\t\todm_update_rx_idle_ant_8723d(dm, ant, default_ant,\n\t\t\t\t\t     optional_ant);\n#endif\n\n#if (RTL8721D_SUPPORT == 1)\n\t} else if (dm->support_ic_type == ODM_RTL8721D) {\n\t\todm_update_rx_idle_ant_8721d(dm, ant, default_ant,\n\t\t\t\t\t     optional_ant);\n#endif\n\t} else {\n/*@8188E & 8188F*/\n/*@\t\tif (dm->support_ic_type == ODM_RTL8723D) {*/\n/*#if (RTL8723D_SUPPORT == 1)*/\n/*\t\t\tphydm_set_tx_ant_pwr_8723d(dm, ant);*/\n/*#endif*/\n/*\t\t}*/\n#if (RTL8188F_SUPPORT == 1)\n\t\tif (dm->support_ic_type == ODM_RTL8188F)\n\t\t\tphydm_update_rx_idle_antenna_8188F(dm, default_ant);\n#endif\n\n\t\todm_set_bb_reg(dm, R_0x864, 0x38, default_ant);/*@Default RX*/\n\t\todm_set_bb_reg(dm, R_0x864, 0x1c0, optional_ant);\n\t\t\t/*Optional RX*/\n\t\todm_set_bb_reg(dm, R_0x860, 0x7000, default_tx_ant);\n\t\t\t/*@Default TX*/\n\t}\n}\n\nvoid odm_update_rx_idle_ant(void *dm_void, u8 ant)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tu32 default_ant, optional_ant, value32, default_tx_ant;\n\n\tif (fat_tab->rx_idle_ant != ant) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ Update Rx-Idle-ant ] rx_idle_ant =%s\\n\",\n\t\t\t  (ant == MAIN_ANT) ? \"MAIN_ANT\" : \"AUX_ANT\");\n\n\t\tif (!(dm->support_ic_type & ODM_RTL8723B))\n\t\t\tfat_tab->rx_idle_ant = ant;\n\n\t\tif (ant == MAIN_ANT) {\n\t\t\tdefault_ant = ANT1_2G;\n\t\t\toptional_ant = ANT2_2G;\n\t\t} else {\n\t\t\tdefault_ant = ANT2_2G;\n\t\t\toptional_ant = ANT1_2G;\n\t\t}\n\n\t\tif (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)\n\t\t\tdefault_tx_ant = (fat_tab->b_fix_tx_ant ==\n\t\t\t\t\t FIX_TX_AT_MAIN) ? 0 : 1;\n\t\telse\n\t\t\tdefault_tx_ant = default_ant;\n\n\t\tif (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {\n\t\t\tphydm_update_rx_idle_n(dm, ant, default_ant,\n\t\t\t\t\t       optional_ant, default_tx_ant);\n\t\t} else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {\n\t\t\tphydm_update_rx_idle_ac(dm, ant, default_ant,\n\t\t\t\t\t\toptional_ant, default_tx_ant);\n\t\t}\n\t\t/*PathA Resp Tx*/\n\t\tif (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B |\n\t\t    ODM_RTL8814A))\n\t\t\todm_set_mac_reg(dm, R_0x6d8, 0x7, default_tx_ant);\n\t\telse if (dm->support_ic_type == ODM_RTL8188E)\n\t\t\todm_set_mac_reg(dm, R_0x6d8, 0xc0, default_tx_ant);\n\t\telse\n\t\t\todm_set_mac_reg(dm, R_0x6d8, 0x700, default_tx_ant);\n\n\t} else { /* @fat_tab->rx_idle_ant == ant */\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ Stay in Ori-ant ]  rx_idle_ant =%s\\n\",\n\t\t\t  (ant == MAIN_ANT) ? \"MAIN_ANT\" : \"AUX_ANT\");\n\t\tfat_tab->rx_idle_ant = ant;\n\t}\n}\n\nvoid phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tu32 default_ant, optional_ant, value32, default_tx_ant;\n\n\tif (fat_tab->rx_idle_ant2 != ant) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ Update Rx-Idle-ant2 ] rx_idle_ant2 =%s\\n\",\n\t\t\t  (ant == MAIN_ANT) ? \"MAIN_ANT\" : \"AUX_ANT\");\n\t\tif (ant == MAIN_ANT) {\n\t\t\tdefault_ant = ANT1_2G;\n\t\t\toptional_ant = ANT2_2G;\n\t\t} else {\n\t\t\tdefault_ant = ANT2_2G;\n\t\t\toptional_ant = ANT1_2G;\n\t\t}\n\n\t\tif (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)\n\t\t\tdefault_tx_ant = (fat_tab->b_fix_tx_ant ==\n\t\t\t\t\t  FIX_TX_AT_MAIN) ? 0 : 1;\n\t\telse\n\t\t\tdefault_tx_ant = default_ant;\n\t\tif (dm->support_ic_type & ODM_RTL8822B) {\n\t\t\tu16 v16 = odm_read_2byte(dm, ODM_REG_ANT_11AC_B + 2);\n\n\t\t\tv16 &= ~(0xff8);/*0xE08[11:3]*/\n\t\t\tv16 |= ((u16)default_ant << 3);\n\t\t\tv16 |= ((u16)optional_ant << 6);\n\t\t\tv16 |= ((u16)default_tx_ant << 9);\n\t\t\todm_write_2byte(dm, ODM_REG_ANT_11AC_B + 2, v16);\n\t\t\todm_set_mac_reg(dm, R_0x6d8, 0x38, default_tx_ant);\n\t\t\t/*PathB Resp Tx*/\n\t\t}\n\t} else {\n\t\t/* fat_tab->rx_idle_ant2 == ant */\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[Stay Ori Ant] rx_idle_ant2 = %s\\n\",\n\t\t\t  (ant == MAIN_ANT) ? \"MAIN_ANT\" : \"AUX_ANT\");\n\t\tfat_tab->rx_idle_ant2 = ant;\n\t}\n}\n\nvoid phydm_set_antdiv_val(void *dm_void, u32 *val_buf,\tu8 val_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (val_len != 1) {\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[Error][antdiv]Need val_len=1\\n\");\n\t\treturn;\n\t}\n\n\todm_update_rx_idle_ant(dm, (u8)(*val_buf));\n}\n\nvoid odm_update_tx_ant(void *dm_void, u8 ant, u32 mac_id)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tu8 tx_ant;\n\n\tif (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)\n\t\tant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ?\n\t\t       MAIN_ANT : AUX_ANT;\n\n\tif (dm->ant_div_type == CG_TRX_SMART_ANTDIV)\n\t\ttx_ant = ant;\n\telse {\n\t\tif (ant == MAIN_ANT)\n\t\t\ttx_ant = ANT1_2G;\n\t\telse\n\t\t\ttx_ant = ANT2_2G;\n\t}\n\n\tfat_tab->antsel_a[mac_id] = tx_ant & BIT(0);\n\tfat_tab->antsel_b[mac_id] = (tx_ant & BIT(1)) >> 1;\n\tfat_tab->antsel_c[mac_id] = (tx_ant & BIT(2)) >> 2;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[Set TX-DESC value]: mac_id:(( %d )),  tx_ant = (( %s ))\\n\",\n\t\t  mac_id, (ant == MAIN_ANT) ? \"MAIN_ANT\" : \"AUX_ANT\");\n#if 0\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"antsel_tr_mux=(( 3'b%d%d%d ))\\n\",\n\t\t  fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],\n\t\t  fat_tab->antsel_a[mac_id]);\n#endif\n}\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\nvoid odm_bdc_init(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"\\n[ BDC Initialization......]\\n\");\n\tdm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;\n\tdm_bdc_table->bdc_mode = BDC_MODE_NULL;\n\tdm_bdc_table->bdc_try_flag = 0;\n\tdm_bdc_table->bd_ccoex_type_wbfer = 0;\n\tdm->bdc_holdstate = 0xff;\n\n\tif (dm->support_ic_type == ODM_RTL8192E) {\n\t\todm_set_bb_reg(dm, R_0xd7c, 0x0FFFFFFF, 0x1081008);\n\t\todm_set_bb_reg(dm, R_0xd80, 0x0FFFFFFF, 0);\n\t} else if (dm->support_ic_type == ODM_RTL8812) {\n\t\todm_set_bb_reg(dm, R_0x9b0, 0x0FFFFFFF, 0x1081008);\n\t\t\t/* @0x9b0[30:0] = 01081008 */\n\t\todm_set_bb_reg(dm, R_0x9b4, 0x0FFFFFFF, 0);\n\t\t\t/* @0x9b4[31:0] = 00000000 */\n\t}\n}\n\nvoid odm_CSI_on_off(\n\tvoid *dm_void,\n\tu8 CSI_en)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tif (CSI_en == CSI_ON) {\n\t\tif (dm->support_ic_type == ODM_RTL8192E)\n\t\t\todm_set_mac_reg(dm, R_0xd84, BIT(11), 1);\n\t\t\t\t/* @0xd84[11]=1 */\n\t\telse if (dm->support_ic_type == ODM_RTL8812)\n\t\t\todm_set_mac_reg(dm, R_0x9b0, BIT(31), 1);\n\t\t\t\t/* @0x9b0[31]=1 */\n\n\t} else if (CSI_en == CSI_OFF) {\n\t\tif (dm->support_ic_type == ODM_RTL8192E)\n\t\t\todm_set_mac_reg(dm, R_0xd84, BIT(11), 0);\n\t\t\t\t/* @0xd84[11]=0 */\n\t\telse if (dm->support_ic_type == ODM_RTL8812)\n\t\t\todm_set_mac_reg(dm, R_0x9b0, BIT(31), 0);\n\t\t\t\t/* @0x9b0[31]=0 */\n\t}\n}\n\nvoid odm_bd_ccoex_type_with_bfer_client(\n\tvoid *dm_void,\n\tu8 swch)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;\n\tu8 bd_ccoex_type_wbfer;\n\n\tif (swch == DIVON_CSIOFF) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[BDCcoexType: 1] {DIV,CSI} ={1,0}\\n\");\n\t\tbd_ccoex_type_wbfer = 1;\n\n\t\tif (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {\n\t\t\todm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);\n\t\t\todm_CSI_on_off(dm, CSI_OFF);\n\t\t\tdm_bdc_table->bd_ccoex_type_wbfer = 1;\n\t\t}\n\t} else if (swch == DIVOFF_CSION) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[BDCcoexType: 2] {DIV,CSI} ={0,1}\\n\");\n\t\tbd_ccoex_type_wbfer = 2;\n\n\t\tif (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {\n\t\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);\n\t\t\todm_CSI_on_off(dm, CSI_ON);\n\t\t\tdm_bdc_table->bd_ccoex_type_wbfer = 2;\n\t\t}\n\t}\n}\n\nvoid odm_bf_ant_div_mode_arbitration(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;\n\tu8 current_bdc_mode;\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"\\n\");\n\n\t/* @2 mode 1 */\n\tif (dm_bdc_table->num_txbfee_client != 0 &&\n\t    dm_bdc_table->num_txbfer_client == 0) {\n\t\tcurrent_bdc_mode = BDC_MODE_1;\n\n\t\tif (current_bdc_mode != dm_bdc_table->bdc_mode) {\n\t\t\tdm_bdc_table->bdc_mode = BDC_MODE_1;\n\t\t\todm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);\n\t\t\tdm_bdc_table->bdc_rx_idle_update_counter = 1;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Change to (( Mode1 ))\\n\");\n\t\t}\n\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[Antdiv + BF coextance mode] : (( Mode1 ))\\n\");\n\t}\n\t/* @2 mode 2 */\n\telse if ((dm_bdc_table->num_txbfee_client == 0) &&\n\t\t (dm_bdc_table->num_txbfer_client != 0)) {\n\t\tcurrent_bdc_mode = BDC_MODE_2;\n\n\t\tif (current_bdc_mode != dm_bdc_table->bdc_mode) {\n\t\t\tdm_bdc_table->bdc_mode = BDC_MODE_2;\n\t\t\tdm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;\n\t\t\tdm_bdc_table->bdc_try_flag = 0;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Change to (( Mode2 ))\\n\");\n\t\t}\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[Antdiv + BF coextance mode] : (( Mode2 ))\\n\");\n\t}\n\t/* @2 mode 3 */\n\telse if ((dm_bdc_table->num_txbfee_client != 0) &&\n\t\t (dm_bdc_table->num_txbfer_client != 0)) {\n\t\tcurrent_bdc_mode = BDC_MODE_3;\n\n\t\tif (current_bdc_mode != dm_bdc_table->bdc_mode) {\n\t\t\tdm_bdc_table->bdc_mode = BDC_MODE_3;\n\t\t\tdm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;\n\t\t\tdm_bdc_table->bdc_try_flag = 0;\n\t\t\tdm_bdc_table->bdc_rx_idle_update_counter = 1;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Change to (( Mode3 ))\\n\");\n\t\t}\n\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[Antdiv + BF coextance mode] : (( Mode3 ))\\n\");\n\t}\n\t/* @2 mode 4 */\n\telse if ((dm_bdc_table->num_txbfee_client == 0) &&\n\t\t (dm_bdc_table->num_txbfer_client == 0)) {\n\t\tcurrent_bdc_mode = BDC_MODE_4;\n\n\t\tif (current_bdc_mode != dm_bdc_table->bdc_mode) {\n\t\t\tdm_bdc_table->bdc_mode = BDC_MODE_4;\n\t\t\todm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Change to (( Mode4 ))\\n\");\n\t\t}\n\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[Antdiv + BF coextance mode] : (( Mode4 ))\\n\");\n\t}\n#endif\n}\n\nvoid odm_div_train_state_setting(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"\\n*****[S T A R T ]*****  [2-0. DIV_TRAIN_STATE]\\n\");\n\tdm_bdc_table->bdc_try_counter = 2;\n\tdm_bdc_table->bdc_try_flag = 1;\n\tdm_bdc_table->BDC_state = bdc_bfer_train_state;\n\todm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);\n}\n\nvoid odm_bd_ccoex_bfee_rx_div_arbitration(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;\n\tboolean stop_bf_flag;\n\tu8 bdc_active_mode;\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"***{ num_BFee,  num_BFer, num_client}  = (( %d  ,  %d  ,  %d))\\n\",\n\t\t  dm_bdc_table->num_txbfee_client,\n\t\t  dm_bdc_table->num_txbfer_client, dm_bdc_table->num_client);\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"***{ num_BF_tars,  num_DIV_tars }  = ((  %d  ,  %d ))\\n\",\n\t\t  dm_bdc_table->num_bf_tar, dm_bdc_table->num_div_tar);\n\n\t/* @2 [ MIB control ] */\n\tif (dm->bdc_holdstate == 2) {\n\t\todm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);\n\t\tdm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Force in [ BF STATE]\\n\");\n\t\treturn;\n\t} else if (dm->bdc_holdstate == 1) {\n\t\tdm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;\n\t\todm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Force in [ DIV STATE]\\n\");\n\t\treturn;\n\t}\n\n\t/* @------------------------------------------------------------ */\n\n\t/* @2 mode 2 & 3 */\n\tif (dm_bdc_table->bdc_mode == BDC_MODE_2 ||\n\t    dm_bdc_table->bdc_mode == BDC_MODE_3) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"\\n{ Try_flag,  Try_counter } = {  %d , %d  }\\n\",\n\t\t\t  dm_bdc_table->bdc_try_flag,\n\t\t\t  dm_bdc_table->bdc_try_counter);\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"BDCcoexType = (( %d ))\\n\\n\",\n\t\t\t  dm_bdc_table->bd_ccoex_type_wbfer);\n\n\t\t/* @All Client have Bfer-Cap------------------------------- */\n\t\tif (dm_bdc_table->num_txbfer_client == dm_bdc_table->num_client) {\n\t\t\t/* @BFer STA Only?: yes */\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"BFer STA only?  (( Yes ))\\n\");\n\t\t\tdm_bdc_table->bdc_try_flag = 0;\n\t\t\tdm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;\n\t\t\todm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);\n\t\t\treturn;\n\t\t} else\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"BFer STA only?  (( No ))\\n\");\n\t\tif (dm_bdc_table->is_all_bf_sta_idle == false && dm_bdc_table->is_all_div_sta_idle == true) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"All DIV-STA are idle, but BF-STA not\\n\");\n\t\t\tdm_bdc_table->bdc_try_flag = 0;\n\t\t\tdm_bdc_table->BDC_state = bdc_bfer_train_state;\n\t\t\todm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);\n\t\t\treturn;\n\t\t} else if (dm_bdc_table->is_all_bf_sta_idle == true && dm_bdc_table->is_all_div_sta_idle == false) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"All BF-STA are idle, but DIV-STA not\\n\");\n\t\t\tdm_bdc_table->bdc_try_flag = 0;\n\t\t\tdm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;\n\t\t\todm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);\n\t\t\treturn;\n\t\t}\n\n\t\t/* Select active mode-------------------------------------- */\n\t\tif (dm_bdc_table->num_bf_tar == 0) { /* Selsect_1,  Selsect_2 */\n\t\t\tif (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"Select active mode (( 1 ))\\n\");\n\t\t\t\tdm_bdc_table->bdc_active_mode = 1;\n\t\t\t} else {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"Select active mode  (( 2 ))\\n\");\n\t\t\t\tdm_bdc_table->bdc_active_mode = 2;\n\t\t\t}\n\t\t\tdm_bdc_table->bdc_try_flag = 0;\n\t\t\tdm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;\n\t\t\todm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);\n\t\t\treturn;\n\t\t} else { /* num_bf_tar > 0 */\n\t\t\tif (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"Select active mode (( 3 ))\\n\");\n\t\t\t\tdm_bdc_table->bdc_active_mode = 3;\n\t\t\t\tdm_bdc_table->bdc_try_flag = 0;\n\t\t\t\tdm_bdc_table->BDC_state = bdc_bfer_train_state;\n\t\t\t\todm_bd_ccoex_type_with_bfer_client(dm,\n\t\t\t\t\t\t\t\t   DIVOFF_CSION)\n\t\t\t\t\t\t\t\t   ;\n\t\t\t\treturn;\n\t\t\t} else { /* Selsect_4 */\n\t\t\t\tbdc_active_mode = 4;\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"Select active mode (( 4 ))\\n\");\n\n\t\t\t\tif (bdc_active_mode != dm_bdc_table->bdc_active_mode) {\n\t\t\t\t\tdm_bdc_table->bdc_active_mode = 4;\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Change to active mode (( 4 ))  &  return!!!\\n\");\n\t\t\t\t\treturn;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n#if 1\n\t\tif (dm->bdc_holdstate == 0xff) {\n\t\t\tdm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;\n\t\t\todm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Force in [ DIV STATE]\\n\");\n\t\t\treturn;\n\t\t}\n#endif\n\n\t\t/* @Does Client number changed ? ------------------------------- */\n\t\tif (dm_bdc_table->num_client != dm_bdc_table->pre_num_client) {\n\t\t\tdm_bdc_table->bdc_try_flag = 0;\n\t\t\tdm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[  The number of client has been changed !!!]   return to (( BDC_DIV_TRAIN_STATE ))\\n\");\n\t\t}\n\t\tdm_bdc_table->pre_num_client = dm_bdc_table->num_client;\n\n\t\tif (dm_bdc_table->bdc_try_flag == 0) {\n\t\t\t/* @2 DIV_TRAIN_STATE (mode 2-0) */\n\t\t\tif (dm_bdc_table->BDC_state == BDC_DIV_TRAIN_STATE)\n\t\t\t\todm_div_train_state_setting(dm);\n\t\t\t/* @2 BFer_TRAIN_STATE (mode 2-1) */\n\t\t\telse if (dm_bdc_table->BDC_state == bdc_bfer_train_state) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"*****[2-1. BFer_TRAIN_STATE ]*****\\n\");\n\n#if 0\n\t\t\t\t/* @if(dm_bdc_table->num_bf_tar==0) */\n\t\t\t\t/* @{ */\n\t\t\t\t/*\tPHYDM_DBG(dm,DBG_ANT_DIV, \"BF_tars exist?  : (( No )),   [ bdc_bfer_train_state ] >> [BDC_DIV_TRAIN_STATE]\\n\"); */\n\t\t\t\t/*\todm_div_train_state_setting( dm); */\n\t\t\t\t/* @} */\n\t\t\t\t/* else */ /* num_bf_tar != 0 */\n\t\t\t\t/* @{ */\n#endif\n\t\t\t\tdm_bdc_table->bdc_try_counter = 2;\n\t\t\t\tdm_bdc_table->bdc_try_flag = 1;\n\t\t\t\tdm_bdc_table->BDC_state = BDC_DECISION_STATE;\n\t\t\t\todm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"BF_tars exist?  : (( Yes )),   [ bdc_bfer_train_state ] >> [BDC_DECISION_STATE]\\n\");\n\t\t\t\t/* @} */\n\t\t\t}\n\t\t\t/* @2 DECISION_STATE (mode 2-2) */\n\t\t\telse if (dm_bdc_table->BDC_state == BDC_DECISION_STATE) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"*****[2-2. DECISION_STATE]*****\\n\");\n#if 0\n\t\t\t\t/* @if(dm_bdc_table->num_bf_tar==0) */\n\t\t\t\t/* @{ */\n\t\t\t\t/*\tODM_AntDiv_Printk((\"BF_tars exist?  : (( No )),   [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE]\\n\")); */\n\t\t\t\t/*\todm_div_train_state_setting( dm); */\n\t\t\t\t/* @} */\n\t\t\t\t/* else */ /* num_bf_tar != 0 */\n\t\t\t\t/* @{ */\n#endif\n\t\t\t\tif (dm_bdc_table->BF_pass == false || dm_bdc_table->DIV_pass == false)\n\t\t\t\t\tstop_bf_flag = true;\n\t\t\t\telse\n\t\t\t\t\tstop_bf_flag = false;\n\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"BF_tars exist?  : (( Yes )),  {BF_pass, DIV_pass, stop_bf_flag }  = { %d, %d, %d }\\n\",\n\t\t\t\t\t  dm_bdc_table->BF_pass,\n\t\t\t\t\t  dm_bdc_table->DIV_pass, stop_bf_flag);\n\n\t\t\t\tif (stop_bf_flag == true) { /* @DIV_en */\n\t\t\t\t\tdm_bdc_table->bdc_hold_counter = 10; /* @20 */\n\t\t\t\t\todm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);\n\t\t\t\t\tdm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[ stop_bf_flag= ((true)),   BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE]\\n\");\n\t\t\t\t} else { /* @BF_en */\n\t\t\t\t\tdm_bdc_table->bdc_hold_counter = 10; /* @20 */\n\t\t\t\t\todm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);\n\t\t\t\t\tdm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[stop_bf_flag= ((false)),   BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE]\\n\");\n\t\t\t\t}\n\t\t\t\t/* @} */\n\t\t\t}\n\t\t\t/* @2 BF-HOLD_STATE (mode 2-3) */\n\t\t\telse if (dm_bdc_table->BDC_state == BDC_BF_HOLD_STATE) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"*****[2-3. BF_HOLD_STATE ]*****\\n\");\n\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"bdc_hold_counter = (( %d ))\\n\",\n\t\t\t\t\t  dm_bdc_table->bdc_hold_counter);\n\n\t\t\t\tif (dm_bdc_table->bdc_hold_counter == 1) {\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\\n\");\n\t\t\t\t\todm_div_train_state_setting(dm);\n\t\t\t\t} else {\n\t\t\t\t\tdm_bdc_table->bdc_hold_counter--;\n\n#if 0\n\t\t\t\t\t/* @if(dm_bdc_table->num_bf_tar==0) */\n\t\t\t\t\t/* @{ */\n\t\t\t\t\t/*\tPHYDM_DBG(dm,DBG_ANT_DIV, \"BF_tars exist?  : (( No )),   [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\\n\"); */\n\t\t\t\t\t/*\todm_div_train_state_setting( dm); */\n\t\t\t\t\t/* @} */\n\t\t\t\t\t/* else */ /* num_bf_tar != 0 */\n\t\t\t\t\t/* @{ */\n\t\t\t\t\t/* PHYDM_DBG(dm,DBG_ANT_DIV, \"BF_tars exist?  : (( Yes ))\\n\"); */\n#endif\n\t\t\t\t\tdm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;\n\t\t\t\t\todm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE]\\n\");\n\t\t\t\t\t/* @} */\n\t\t\t\t}\n\t\t\t}\n\t\t\t/* @2 DIV-HOLD_STATE (mode 2-4) */\n\t\t\telse if (dm_bdc_table->BDC_state == BDC_DIV_HOLD_STATE) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"*****[2-4. DIV_HOLD_STATE ]*****\\n\");\n\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"bdc_hold_counter = (( %d ))\\n\",\n\t\t\t\t\t  dm_bdc_table->bdc_hold_counter);\n\n\t\t\t\tif (dm_bdc_table->bdc_hold_counter == 1) {\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\\n\");\n\t\t\t\t\todm_div_train_state_setting(dm);\n\t\t\t\t} else {\n\t\t\t\t\tdm_bdc_table->bdc_hold_counter--;\n\t\t\t\t\tdm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;\n\t\t\t\t\todm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE]\\n\");\n\t\t\t\t}\n\t\t\t}\n\n\t\t} else if (dm_bdc_table->bdc_try_flag == 1) {\n\t\t\t/* @2 Set Training counter */\n\t\t\tif (dm_bdc_table->bdc_try_counter > 1) {\n\t\t\t\tdm_bdc_table->bdc_try_counter--;\n\t\t\t\tif (dm_bdc_table->bdc_try_counter == 1)\n\t\t\t\t\tdm_bdc_table->bdc_try_flag = 0;\n\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Training !!\\n\");\n\t\t\t\t/* return ; */\n\t\t\t}\n\t\t}\n\t}\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"\\n[end]\\n\");\n\n#endif /* @#if(DM_ODM_SUPPORT_TYPE  == ODM_AP) */\n}\n\n#endif\n#endif /* @#ifdef PHYDM_BEAMFORMING_SUPPORT*/\n\n#if (RTL8188E_SUPPORT == 1)\n\nvoid odm_rx_hw_ant_div_init_88e(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 value32;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[%s]=====>\\n\", __func__);\n\n\t/* @MAC setting */\n\tvalue32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);\n\todm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD,\n\t\t\tvalue32 | (BIT(23) | BIT(25)));\n\t\t\t/* Reg4C[25]=1, Reg4C[23]=1 for pin output */\n\t/* Pin Settings */\n\todm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);\n\t\t\t/* reg870[8]=1'b0, reg870[9]=1'b0 */\n\t\t\t/* antsel antselb by HW */\n\todm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);\n\t\t\t/* reg864[10]=1'b0 */ /* antsel2 by HW */\n\todm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1);\n\t\t\t/* regb2c[22]=1'b0 */ /* disable CS/CG switch */\n\todm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);\n\t\t\t/* regb2c[31]=1'b1 */ /* output at CG only */\n\t/* OFDM Settings */\n\todm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);\n\t/* @CCK Settings */\n\todm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);\n\t\t\t/* @Fix CCK PHY status report issue */\n\todm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);\n\t\t\t/* @CCK complete HW AntDiv within 64 samples */\n\n\todm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0001);\n\t\t\t/* @antenna mapping table */\n\n\tfat_tab->enable_ctrl_frame_antdiv = 1;\n}\n\nvoid odm_trx_hw_ant_div_init_88e(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 value32;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[%s]=====>\\n\", __func__);\n\n\t/* @MAC setting */\n\tvalue32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);\n\todm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD,\n\t\t\tvalue32 | (BIT(23) | BIT(25)));\n\t\t\t/* Reg4C[25]=1, Reg4C[23]=1 for pin output */\n\t/* Pin Settings */\n\todm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);\n\t\t\t/* reg870[8]=1'b0, reg870[9]=1'b0 */\n\t\t\t/* antsel antselb by HW */\n\todm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);\n\t\t\t/* reg864[10]=1'b0 */ /* antsel2 by HW */\n\todm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0);\n\t\t\t/* regb2c[22]=1'b0 */ /* disable CS/CG switch */\n\todm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);\n\t\t\t/* regb2c[31]=1'b1 */ /* output at CG only */\n\t/* OFDM Settings */\n\todm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);\n\t/* @CCK Settings */\n\todm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);\n\t\t\t/* @Fix CCK PHY status report issue */\n\todm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);\n\t\t\t/* @CCK complete HW AntDiv within 64 samples */\n\n\t/* @antenna mapping table */\n\tif (!dm->is_mp_chip) { /* testchip */\n\t\todm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, 0x700, 1);\n\t\t\t\t/* Reg858[10:8]=3'b001 */\n\t\todm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, 0x3800, 2);\n\t\t\t\t/* Reg858[13:11]=3'b010 */\n\t} else /* @MPchip */\n\t\todm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, MASKDWORD, 0x0201);\n\t\t\t\t/*Reg914=3'b010, Reg915=3'b001*/\n\n\tfat_tab->enable_ctrl_frame_antdiv = 1;\n}\n\n#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))\nvoid odm_smart_hw_ant_div_init_88e(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 value32, i;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"***8188E AntDiv_Init =>  ant_div_type=[CG_TRX_SMART_ANTDIV]\\n\");\n\n#if 0\n\tif (*dm->mp_mode == true) {\n\t\tPHYDM_DBG(dm, ODM_COMP_INIT, \"dm->ant_div_type: %d\\n\",\n\t\t\t  dm->ant_div_type);\n\t\treturn;\n\t}\n#endif\n\n\tfat_tab->train_idx = 0;\n\tfat_tab->fat_state = FAT_PREPARE_STATE;\n\n\tdm->fat_comb_a = 5;\n\tdm->antdiv_intvl = 0x64; /* @100ms */\n\n\tfor (i = 0; i < 6; i++)\n\t\tfat_tab->bssid[i] = 0;\n\tfor (i = 0; i < (dm->fat_comb_a); i++) {\n\t\tfat_tab->ant_sum_rssi[i] = 0;\n\t\tfat_tab->ant_rssi_cnt[i] = 0;\n\t\tfat_tab->ant_ave_rssi[i] = 0;\n\t}\n\n\t/* @MAC setting */\n\tvalue32 = odm_get_mac_reg(dm, R_0x4c, MASKDWORD);\n\todm_set_mac_reg(dm, R_0x4c, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */\n\tvalue32 = odm_get_mac_reg(dm, R_0x7b4, MASKDWORD);\n\todm_set_mac_reg(dm, R_0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */\n\t/* value32 = platform_efio_read_4byte(adapter, 0x7B4); */\n\t/* platform_efio_write_4byte(adapter, 0x7b4, value32|BIT(18));\t */ /* append MACID in reponse packet */\n\n\t/* @Match MAC ADDR */\n\todm_set_mac_reg(dm, R_0x7b4, 0xFFFF, 0);\n\todm_set_mac_reg(dm, R_0x7b0, MASKDWORD, 0);\n\n\todm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); /* reg870[8]=1'b0, reg870[9]=1'b0\t\t */ /* antsel antselb by HW */\n\todm_set_bb_reg(dm, R_0x864, BIT(10), 0); /* reg864[10]=1'b0\t */ /* antsel2 by HW */\n\todm_set_bb_reg(dm, R_0xb2c, BIT(22), 0); /* regb2c[22]=1'b0\t */ /* disable CS/CG switch */\n\todm_set_bb_reg(dm, R_0xb2c, BIT(31), 0); /* regb2c[31]=1'b1\t */ /* output at CS only */\n\todm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x000000a0);\n\n\t/* @antenna mapping table */\n\tif (dm->fat_comb_a == 2) {\n\t\tif (!dm->is_mp_chip) { /* testchip */\n\t\t\todm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */\n\t\t\todm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */\n\t\t} else { /* @MPchip */\n\t\t\todm_set_bb_reg(dm, R_0x914, MASKBYTE0, 1);\n\t\t\todm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2);\n\t\t}\n\t} else {\n\t\tif (!dm->is_mp_chip) { /* testchip */\n\t\t\todm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 0); /* Reg858[10:8]=3'b000 */\n\t\t\todm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 1); /* Reg858[13:11]=3'b001 */\n\t\t\todm_set_bb_reg(dm, R_0x878, BIT(16), 0);\n\t\t\todm_set_bb_reg(dm, R_0x858, BIT(15) | BIT(14), 2); /* @(Reg878[0],Reg858[14:15])=3'b010 */\n\t\t\todm_set_bb_reg(dm, R_0x878, BIT(19) | BIT(18) | BIT(17), 3); /* Reg878[3:1]=3b'011 */\n\t\t\todm_set_bb_reg(dm, R_0x878, BIT(22) | BIT(21) | BIT(20), 4); /* Reg878[6:4]=3b'100 */\n\t\t\todm_set_bb_reg(dm, R_0x878, BIT(25) | BIT(24) | BIT(23), 5); /* Reg878[9:7]=3b'101 */\n\t\t\todm_set_bb_reg(dm, R_0x878, BIT(28) | BIT(27) | BIT(26), 6); /* Reg878[12:10]=3b'110 */\n\t\t\todm_set_bb_reg(dm, R_0x878, BIT(31) | BIT(30) | BIT(29), 7); /* Reg878[15:13]=3b'111 */\n\t\t} else { /* @MPchip */\n\t\t\todm_set_bb_reg(dm, R_0x914, MASKBYTE0, 4); /* @0: 3b'000 */\n\t\t\todm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2); /* @1: 3b'001 */\n\t\t\todm_set_bb_reg(dm, R_0x914, MASKBYTE2, 0); /* @2: 3b'010 */\n\t\t\todm_set_bb_reg(dm, R_0x914, MASKBYTE3, 1); /* @3: 3b'011 */\n\t\t\todm_set_bb_reg(dm, R_0x918, MASKBYTE0, 3); /* @4: 3b'100 */\n\t\t\todm_set_bb_reg(dm, R_0x918, MASKBYTE1, 5); /* @5: 3b'101 */\n\t\t\todm_set_bb_reg(dm, R_0x918, MASKBYTE2, 6); /* @6: 3b'110 */\n\t\t\todm_set_bb_reg(dm, R_0x918, MASKBYTE3, 255); /* @7: 3b'111 */\n\t\t}\n\t}\n\n\t/* @Default ant setting when no fast training */\n\todm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), 0); /* @Default RX */\n\todm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */\n\todm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), 0); /* @Default TX */\n\n\t/* @Enter Traing state */\n\todm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), (dm->fat_comb_a - 1)); /* reg864[2:0]=3'd6\t */ /* ant combination=reg864[2:0]+1 */\n\n#if 0\n\t/* SW Control */\n\t/* phy_set_bb_reg(adapter, 0x864, BIT10, 1); */\n\t/* phy_set_bb_reg(adapter, 0x870, BIT9, 1); */\n\t/* phy_set_bb_reg(adapter, 0x870, BIT8, 1); */\n\t/* phy_set_bb_reg(adapter, 0x864, BIT11, 1); */\n\t/* phy_set_bb_reg(adapter, 0x860, BIT9, 0); */\n\t/* phy_set_bb_reg(adapter, 0x860, BIT8, 0); */\n#endif\n}\n#endif\n\n#endif /* @#if (RTL8188E_SUPPORT == 1) */\n\n#if (RTL8192E_SUPPORT == 1)\nvoid odm_rx_hw_ant_div_init_92e(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n#if 0\n\tif (*dm->mp_mode == true) {\n\t\todm_ant_div_on_off(dm, ANTDIV_OFF);\n\t\todm_set_bb_reg(dm, R_0xc50, BIT(8), 0);\n\t\t/* r_rxdiv_enable_anta  regc50[8]=1'b0  0: control by c50[9] */\n\t\todm_set_bb_reg(dm, R_0xc50, BIT(9), 1);\n\t\t/* @1:CG, 0:CS */\n\t\treturn;\n\t}\n#endif\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[%s]=====>\\n\", __func__);\n\n\t/* Pin Settings */\n\todm_set_bb_reg(dm, R_0x870, BIT(8), 0);\n\t\t/* reg870[8]=1'b0,   antsel is controled by HWs */\n\todm_set_bb_reg(dm, R_0xc50, BIT(8), 1);\n\t\t/* regc50[8]=1'b1    CS/CG switching is controled by HWs*/\n\n\t/* @Mapping table */\n\todm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);\n\t\t/* @antenna mapping table */\n\n\t/* OFDM Settings */\n\todm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */\n\todm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */\n\n\t/* @CCK Settings */\n\todm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);\n\t\t/* Select which path to receive for CCK_1 & CCK_2 */\n\todm_set_bb_reg(dm, R_0xb34, BIT(30), 0);\n\t\t/* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */\n\todm_set_bb_reg(dm, R_0xa74, BIT(7), 1);\n\t\t/* @Fix CCK PHY status report issue */\n\todm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);\n\t\t/* @CCK complete HW AntDiv within 64 samples */\n\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\tphydm_evm_sw_antdiv_init(dm);\n#endif\n}\n\nvoid odm_trx_hw_ant_div_init_92e(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if 0\n\tif (*dm->mp_mode == true) {\n\t\todm_ant_div_on_off(dm, ANTDIV_OFF);\n\t\todm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* r_rxdiv_enable_anta  regc50[8]=1'b0  0: control by c50[9] */\n\t\todm_set_bb_reg(dm, R_0xc50, BIT(9), 1);  /* @1:CG, 0:CS */\n\t\treturn;\n\t}\n#endif\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[%s]=====>\\n\", __func__);\n\n\t/* @3 --RFE pin setting--------- */\n\t/* @[MAC] */\n\todm_set_mac_reg(dm, R_0x38, BIT(11), 1);\n\t\t/* @DBG PAD Driving control (GPIO 8) */\n\todm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* path-A, RFE_CTRL_3 */\n\todm_set_mac_reg(dm, R_0x4c, BIT(29), 1); /* path-A, RFE_CTRL_8 */\n\t/* @[BB] */\n\todm_set_bb_reg(dm, R_0x944, BIT(3), 1); /* RFE_buffer */\n\todm_set_bb_reg(dm, R_0x944, BIT(8), 1);\n\todm_set_bb_reg(dm, R_0x940, BIT(7) | BIT(6), 0x0);\n\t\t/* r_rfe_path_sel_   (RFE_CTRL_3) */\n\todm_set_bb_reg(dm, R_0x940, BIT(17) | BIT(16), 0x0);\n\t\t/* r_rfe_path_sel_   (RFE_CTRL_8) */\n\todm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer */\n\todm_set_bb_reg(dm, R_0x92c, BIT(3), 0); /* rfe_inv  (RFE_CTRL_3) */\n\todm_set_bb_reg(dm, R_0x92c, BIT(8), 1); /* rfe_inv  (RFE_CTRL_8) */\n\todm_set_bb_reg(dm, R_0x930, 0xF000, 0x8); /* path-A, RFE_CTRL_3 */\n\todm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */\n\t/* @3 ------------------------- */\n\n\t/* Pin Settings */\n\todm_set_bb_reg(dm, R_0xc50, BIT(8), 0);\n\t\t/* path-A  */ /* disable CS/CG switch */\n\n#if 0\n\t/* @Let it follows PHY_REG for bit9 setting */\n\tif (dm->priv->pshare->rf_ft_var.use_ext_pa ||\n\t    dm->priv->pshare->rf_ft_var.use_ext_lna)\n\t\todm_set_bb_reg(dm, R_0xc50, BIT(9), 1);/* path-A output at CS */\n\telse\n\t\todm_set_bb_reg(dm, R_0xc50, BIT(9), 0);\n\t\t\t/* path-A output at CG ->normal power */\n#endif\n\n\todm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);\n\t\t/* path-A*/ /* antsel antselb by HW */\n\todm_set_bb_reg(dm, R_0xb38, BIT(10), 0);/* path-A*/ /* antsel2 by HW */\n\n\t/* @Mapping table */\n\todm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);\n\t\t/* @antenna mapping table */\n\n\t/* OFDM Settings */\n\todm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */\n\todm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */\n\n\t/* @CCK Settings */\n\todm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);\n\t\t/* Select which path to receive for CCK_1 & CCK_2 */\n\todm_set_bb_reg(dm, R_0xb34, BIT(30), 0);\n\t\t/* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */\n\todm_set_bb_reg(dm, R_0xa74, BIT(7), 1);\n\t\t/* @Fix CCK PHY status report issue */\n\todm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);\n\t\t/* @CCK complete HW AntDiv within 64 samples */\n\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\tphydm_evm_sw_antdiv_init(dm);\n#endif\n}\n\n#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))\nvoid odm_smart_hw_ant_div_init_92e(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"***8192E AntDiv_Init =>  ant_div_type=[CG_TRX_SMART_ANTDIV]\\n\");\n}\n#endif\n\n#endif /* @#if (RTL8192E_SUPPORT == 1) */\n\n#if (RTL8192F_SUPPORT == 1)\nvoid odm_rx_hw_ant_div_init_92f(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[%s]=====>\\n\", __func__);\n\n\t/* Pin Settings */\n\todm_set_bb_reg(dm, R_0x870, BIT(8), 0);\n\t\t/* reg870[8]=1'b0, \"antsel\" is controlled by HWs */\n\todm_set_bb_reg(dm, R_0xc50, BIT(8), 1);\n\t\t/* regc50[8]=1'b1, \" CS/CG switching\" is controlled by HWs */\n\n\t/* @Mapping table */\n\todm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);\n\t\t/* @antenna mapping table */\n\n\t/* OFDM Settings */\n\todm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */\n\todm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */\n\n\t/* @CCK Settings */\n\todm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);\n\t\t/* Select which path to receive for CCK_1 & CCK_2 */\n\todm_set_bb_reg(dm, R_0xb34, BIT(30), 0);\n\t\t/* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */\n\todm_set_bb_reg(dm, R_0xa74, BIT(7), 1);\n\t\t/* @Fix CCK PHY status report issue */\n\todm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);\n\t\t/* @CCK complete HW AntDiv within 64 samples */\n\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\tphydm_evm_sw_antdiv_init(dm);\n#endif\n}\n\nvoid odm_trx_hw_ant_div_init_92f(void *dm_void)\n\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[%s]=====>\\n\", __func__);\n\t/* @3 --RFE pin setting--------- */\n\t/* @[MAC] */\n\todm_set_mac_reg(dm, R_0x1048, BIT(0), 1);\n\t\t/* @DBG PAD Driving control (gpioA_0) */\n\todm_set_mac_reg(dm, R_0x1048, BIT(1), 1);\n\t\t/* @DBG PAD Driving control (gpioA_1) */\n\todm_set_mac_reg(dm, R_0x4c, BIT(24), 1);\n\todm_set_mac_reg(dm, R_0x1038, BIT(25) | BIT(24) | BIT(23), 0);\n\t\t/* @gpioA_0,gpioA_1*/\n\todm_set_mac_reg(dm, R_0x4c, BIT(23), 0);\n\t/* @[BB] */\n\todm_set_bb_reg(dm, R_0x944, BIT(8), 1); /* output enable */\n\todm_set_bb_reg(dm, R_0x944, BIT(9), 1);\n\todm_set_bb_reg(dm, R_0x940, BIT(16) | BIT(17), 0x0);\n\t\t/* r_rfe_path_sel_   (RFE_CTRL_8) */\n\todm_set_bb_reg(dm, R_0x940, BIT(18) | BIT(19), 0x0);\n\t\t/* r_rfe_path_sel_   (RFE_CTRL_9) */\n\todm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer_en */\n\todm_set_bb_reg(dm, R_0x92c, BIT(8), 0); /* rfe_inv  (RFE_CTRL_8) */\n\todm_set_bb_reg(dm, R_0x92c, BIT(9), 1); /* rfe_inv  (RFE_CTRL_9) */\n\todm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */\n\todm_set_bb_reg(dm, R_0x934, 0xF0, 0x8); /* path-A, RFE_CTRL_9 */\n\t/* @3 ------------------------- */\n\n\t/* Pin Settings */\n\todm_set_bb_reg(dm, R_0xc50, BIT(8), 0);\n\t\t/* path-A,disable CS/CG switch */\n\todm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);\n\t\t/* path-A*, antsel antselb by HW */\n\todm_set_bb_reg(dm, R_0xb38, BIT(10), 0); /* path-A ,antsel2 by HW */\n\n\t/* @Mapping table */\n\todm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);\n\t\t/* @antenna mapping table */\n\n\t/* OFDM Settings */\n\todm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */\n\todm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */\n\n\t/* @CCK Settings */\n\todm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);\n\t\t/* Select which path to receive for CCK_1 & CCK_2 */\n\todm_set_bb_reg(dm, R_0xb34, BIT(30), 0);\n\t\t/* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */\n\todm_set_bb_reg(dm, R_0xa74, BIT(7), 1);\n\t\t/* @Fix CCK PHY status report issue */\n\todm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);\n\t\t/* @CCK complete HW AntDiv within 64 samples */\n\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\tphydm_evm_sw_antdiv_init(dm);\n#endif\n}\n\n#endif /* @#if (RTL8192F_SUPPORT == 1) */\n\n#if (RTL8822B_SUPPORT == 1)\nvoid phydm_trx_hw_ant_div_init_22b(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[%s]=====>\\n\", __func__);\n\n\t/* Pin Settings */\n\todm_set_bb_reg(dm, R_0xcb8, BIT(21) | BIT(20), 0x1);\n\todm_set_bb_reg(dm, R_0xcb8, BIT(23) | BIT(22), 0x1);\n\todm_set_bb_reg(dm, R_0xc1c, BIT(7) | BIT(6), 0x0);\n\t/* @------------------------- */\n\n\t/* @Mapping table */\n\t/* @antenna mapping table */\n\todm_set_bb_reg(dm, R_0xca4, 0xFFFF, 0x0100);\n\n\t/* OFDM Settings */\n\t/* thershold */\n\todm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0);\n\t/* @bias */\n\todm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0);\n\todm_set_bb_reg(dm, R_0x668, BIT(3), 0x1);\n\n\t/* @CCK Settings */\n\t/* Select which path to receive for CCK_1 & CCK_2 */\n\todm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);\n\t/* @Fix CCK PHY status report issue */\n\todm_set_bb_reg(dm, R_0xa74, BIT(7), 1);\n\t/* @CCK complete HW AntDiv within 64 samples */\n\todm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);\n\t/* @BT Coexistence */\n\t/* @keep antsel_map when GNT_BT = 1 */\n\todm_set_bb_reg(dm, R_0xcac, BIT(9), 1);\n\t/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */\n\todm_set_bb_reg(dm, R_0x804, BIT(4), 1);\n\t/* response TX ant by RX ant */\n\todm_set_mac_reg(dm, R_0x668, BIT(3), 1);\n#if (defined(CONFIG_2T4R_ANTENNA))\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"***8822B AntDiv_Init =>  2T4R case\\n\");\n\t/* Pin Settings */\n\todm_set_bb_reg(dm, R_0xeb8, BIT(21) | BIT(20), 0x1);\n\todm_set_bb_reg(dm, R_0xeb8, BIT(23) | BIT(22), 0x1);\n\todm_set_bb_reg(dm, R_0xe1c, BIT(7) | BIT(6), 0x0);\n\t/* @BT Coexistence */\n\todm_set_bb_reg(dm, R_0xeac, BIT(9), 1);\n\t/* @keep antsel_map when GNT_BT = 1 */\n\t/* Mapping table */\n\t/* antenna mapping table */\n\todm_set_bb_reg(dm, R_0xea4, 0xFFFF, 0x0100);\n\t/*odm_set_bb_reg(dm, R_0x900, 0x30000, 0x3);*/\n#endif\n\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\tphydm_evm_sw_antdiv_init(dm);\n#endif\n}\n#endif /* @#if (RTL8822B_SUPPORT == 1) */\n\n#if (RTL8197F_SUPPORT == 1)\nvoid phydm_rx_hw_ant_div_init_97f(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n#if 0\n\tif (*dm->mp_mode == true) {\n\t\todm_ant_div_on_off(dm, ANTDIV_OFF);\n\t\todm_set_bb_reg(dm, R_0xc50, BIT(8), 0);\n\t\t/* r_rxdiv_enable_anta  regc50[8]=1'b0  0: control by c50[9] */\n\t\todm_set_bb_reg(dm, R_0xc50, BIT(9), 1);  /* @1:CG, 0:CS */\n\t\treturn;\n\t}\n#endif\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[%s]=====>\\n\", __func__);\n\n\t/* Pin Settings */\n\todm_set_bb_reg(dm, R_0x870, BIT(8), 0);\n\t\t/* reg870[8]=1'b0, */ /* \"antsel\" is controlled by HWs */\n\todm_set_bb_reg(dm, R_0xc50, BIT(8), 1);\n\t\t/* regc50[8]=1'b1 *//*\"CS/CG switching\" is controlled by HWs */\n\n\t/* @Mapping table */\n\todm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);\n\t\t/* @antenna mapping table */\n\n\t/* OFDM Settings */\n\todm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */\n\todm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */\n\n\t/* @CCK Settings */\n\todm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);\n\t\t/* Select which path to receive for CCK_1 & CCK_2 */\n\todm_set_bb_reg(dm, R_0xb34, BIT(30), 0);\n\t\t/* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */\n\todm_set_bb_reg(dm, R_0xa74, BIT(7), 1);\n\t\t/* @Fix CCK PHY status report issue */\n\todm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);\n\t\t/* @CCK complete HW AntDiv within 64 samples */\n\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\tphydm_evm_sw_antdiv_init(dm);\n#endif\n}\n#endif //#if (RTL8197F_SUPPORT == 1)\n\n#if (RTL8723D_SUPPORT == 1)\nvoid odm_trx_hw_ant_div_init_8723d(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[%s]=====>\\n\", __func__);\n\n\t/*@BT Coexistence*/\n\t/*@keep antsel_map when GNT_BT = 1*/\n\todm_set_bb_reg(dm, R_0x864, BIT(12), 1);\n\t/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */\n\todm_set_bb_reg(dm, R_0x874, BIT(23), 0);\n\t/* @Disable hw antsw & fast_train.antsw when BT TX/RX */\n\todm_set_bb_reg(dm, R_0xe64, 0xFFFF0000, 0x000c);\n\n\todm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);\n#if 0\n\t/*PTA setting: WL_BB_SEL_BTG_TRXG_anta,  (1: HW CTRL  0: SW CTRL)*/\n\t/*odm_set_bb_reg(dm, R_0x948, BIT6, 0);*/\n\t/*odm_set_bb_reg(dm, R_0x948, BIT8, 0);*/\n#endif\n\t/*@GNT_WL tx*/\n\todm_set_bb_reg(dm, R_0x950, BIT(29), 0);\n\n\t/*@Mapping Table*/\n\todm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);\n\todm_set_bb_reg(dm, R_0x914, MASKBYTE1, 3);\n#if 0\n\t/* odm_set_bb_reg(dm, R_0x864, BIT5|BIT4|BIT3, 0); */\n\t/* odm_set_bb_reg(dm, R_0x864, BIT8|BIT7|BIT6, 1); */\n#endif\n\n\t/* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */\n\todm_set_bb_reg(dm, R_0xccc, BIT(12), 0);\n\t/* @Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable */\n\todm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01);\n\t/* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable */\n\todm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0);\n\t/* @b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable (CCK)*/\n\todm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06);\n\t/* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable (CCK) */\n\todm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00);\n\n\t/*OFDM HW AntDiv Parameters*/\n\todm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0);\n\todm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00);\n\todm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04);\n\n\t/*@CCK HW AntDiv Parameters*/\n\todm_set_bb_reg(dm, R_0xa74, BIT(7), 1);\n\todm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);\n\todm_set_bb_reg(dm, R_0xaa8, BIT(8), 0);\n\n\todm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf);\n\todm_set_bb_reg(dm, R_0xa14, 0x1F, 0x8);\n\todm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1);\n\todm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0);\n\todm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1);\n\n\t/*@disable antenna training\t*/\n\todm_set_bb_reg(dm, R_0xe08, BIT(16), 0);\n\todm_set_bb_reg(dm, R_0xc50, BIT(8), 0);\n}\n/*@Mingzhi 2017-05-08*/\n\nvoid odm_s0s1_sw_ant_div_init_8723d(void *dm_void)\n{\n\tstruct dm_struct\t\t*dm = (struct dm_struct *)dm_void;\n\tstruct sw_antenna_switch\t*swat_tab = &dm->dm_swat_table;\n\tstruct phydm_fat_struct\t\t*fat_tab = &dm->dm_fat_table;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"***8723D AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\\n\");\n\n\t/*@keep antsel_map when GNT_BT = 1*/\n\todm_set_bb_reg(dm, R_0x864, BIT(12), 1);\n\n\t/* @Disable antsw when GNT_BT=1 */\n\todm_set_bb_reg(dm, R_0x874, BIT(23), 0);\n\n\t/* @Mapping Table */\n\todm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);\n\todm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);\n\n\t/* Output Pin Settings */\n#if 0\n\t/* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */\n#endif\n\todm_set_bb_reg(dm, R_0x870, BIT(8), 1);\n\todm_set_bb_reg(dm, R_0x870, BIT(9), 1);\n\n\t/* Status init */\n\tfat_tab->is_become_linked  = false;\n\tswat_tab->try_flag = SWAW_STEP_INIT;\n\tswat_tab->double_chk_flag = 0;\n\tswat_tab->cur_antenna = MAIN_ANT;\n\tswat_tab->pre_ant = MAIN_ANT;\n\tdm->antdiv_counter = CONFIG_ANTDIV_PERIOD;\n\n\t/* @2 [--For HW Bug setting] */\n\todm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant  by Reg */\n}\n\nvoid odm_update_rx_idle_ant_8723d(void *dm_void, u8 ant, u32 default_ant,\n\t\t\t\t  u32 optional_ant)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tvoid *adapter = dm->adapter;\n\tu8 count = 0;\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))\n\t/*score board to BT ,a002:WL to do ant-div*/\n\todm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa002);\n\tODM_delay_us(50);\n#endif\n#if 0\n\t/*\todm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);\t*/\n#endif\n\tif (dm->ant_div_type == S0S1_SW_ANTDIV) {\n\todm_set_bb_reg(dm, R_0x860, BIT(8), default_ant);\n\todm_set_bb_reg(dm, R_0x860, BIT(9), default_ant);\n\t}\n\todm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);\n\t\t/*@Default RX*/\n\todm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);\n\t\t/*Optional RX*/\n\todm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);\n\t\t/*@Default TX*/\n\tfat_tab->rx_idle_ant = ant;\n#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))\n\t/*score board to BT ,a000:WL@S1 a001:WL@S0*/\n\tif (default_ant == ANT1_2G)\n\t\todm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa000);\n\telse\n\t\todm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa001);\n#endif\n}\n\nvoid phydm_set_tx_ant_pwr_8723d(void *dm_void, u8 ant)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tvoid *adapter = dm->adapter;\n\n\tfat_tab->rx_idle_ant = ant;\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel);\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\trtw_hal_set_tx_power_level(adapter, *dm->channel);\n#endif\n}\n#endif\n\n#if (RTL8721D_SUPPORT == 1)\n\nvoid odm_update_rx_idle_ant_8721d(void *dm_void, u8 ant, u32 default_ant,\n\t\t\t\t  u32 optional_ant)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\todm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);\n\t/*@Default RX*/\n\todm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);\n\t/*@Optional RX*/\n\todm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);\n\t/*@Default TX*/\n\tfat_tab->rx_idle_ant = ant;\n}\n\nvoid odm_trx_hw_ant_div_init_8721d(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[8721D] AntDiv_Init =>  ant_div_type=[CG_TRX_HW_ANTDIV]\\n\");\n\n\t/*@BT Coexistence*/\n\t/*@keep antsel_map when GNT_BT = 1*/\n\todm_set_bb_reg(dm, R_0x864, BIT(12), 1);\n\t/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */\n\todm_set_bb_reg(dm, R_0x874, BIT(23), 0);\n\t/* @Disable hw antsw & fast_train.antsw when BT TX/RX */\n\todm_set_bb_reg(dm, R_0xe64, 0xFFFF0000, 0x000c);\n\n\tu32 sysreg408 = HAL_READ32(SYSTEM_CTRL_BASE_LP, 0x0408);\n\n\tsysreg408 &= ~0x0000001F;\n\tsysreg408 |= 0x12;\n\tHAL_WRITE32(SYSTEM_CTRL_BASE_LP, 0x0408, sysreg408);\n\n\tu32 sysreg410 = HAL_READ32(SYSTEM_CTRL_BASE_LP, 0x0410);\n\n\tsysreg410 &= ~0x0000001F;\n\tsysreg410 |= 0x12;\n\tHAL_WRITE32(SYSTEM_CTRL_BASE_LP, 0x0410, sysreg410);\n\n\tu32 sysreg208 = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0);\n\n\tsysreg208 |= BIT(28);\n\tHAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0, sysreg208);\n\n\tu32 sysreg344 =\n\t\t      HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL);\n\n\tsysreg344 |= BIT(9);\n\tHAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344);\n\n\tu32 sysreg280 = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0);\n\n\tsysreg280 |= 0x7;\n\tHAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0, sysreg280);\n\n\tsysreg344 |= BIT(8);\n\tHAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344);\n\n\tsysreg344 |= BIT(0);\n\tHAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344);\n\n\todm_set_bb_reg(dm, R_0x930, 0xF00, 8); /* RFE CTRL_2 ANTSEL0 */\n\todm_set_bb_reg(dm, R_0x930, 0xF000, 8); /* RFE CTRL_3 ANTSEL0 */\n\todm_set_bb_reg(dm, R_0x92c, BIT(3) | BIT(2), 2);\n\n\todm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);\n\todm_set_bb_reg(dm, R_0x804, 0xF00, 1); /* r_keep_rfpin */\n\todm_set_bb_reg(dm, R_0x944, 0x0000000C, 0x3); /* PAD in/output CTRL */\n\n\t/*PTA setting: WL_BB_SEL_BTG_TRXG_anta,  (1: HW CTRL  0: SW CTRL)*/\n\t/*odm_set_bb_reg(dm, R_0x948, BIT6, 0);*/\n\t/*odm_set_bb_reg(dm, R_0x948, BIT8, 0);*/\n\t/*@GNT_WL tx*/\n\todm_set_bb_reg(dm, R_0x950, BIT(29), 0);\n\n\t/*@Mapping Table*/\n\todm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);\n\todm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);\n\t/* odm_set_bb_reg(dm, R_0x864, BIT5|BIT4|BIT3, 0); */\n\t/* odm_set_bb_reg(dm, R_0x864, BIT8|BIT7|BIT6, 1); */\n\n\t/* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */\n\todm_set_bb_reg(dm, R_0xccc, BIT(12), 0);\n\t/* @Low-to-High threshold for WLBB_SEL_RF_ON */\n\t/*when OFDM enable */\n\todm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01);\n\t/* @High-to-Low threshold for WLBB_SEL_RF_ON */\n\t/* when OFDM enable */\n\todm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0);\n\t/* @b Low-to-High threshold for WLBB_SEL_RF_ON*/\n\t/*when OFDM disable ( only CCK ) */\n\todm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06);\n\t/* @High-to-Low threshold for WLBB_SEL_RF_ON*/\n\t/* when OFDM disable ( only CCK ) */\n\todm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00);\n\n\t/*OFDM HW AntDiv Parameters*/\n\todm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0);\n\todm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00);\n\todm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04);\n\n\t/*@CCK HW AntDiv Parameters*/\n\todm_set_bb_reg(dm, R_0xa74, BIT(7), 1);\n\todm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);\n\todm_set_bb_reg(dm, R_0xaa8, BIT(8), 0);\n\n\todm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf);\n\todm_set_bb_reg(dm, R_0xa14, 0x1F, 0x8);\n\todm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1);\n\todm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0);\n\todm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1);\n\n\t/*@disable antenna training\t*/\n\todm_set_bb_reg(dm, R_0xe08, BIT(16), 0);\n\todm_set_bb_reg(dm, R_0xc50, BIT(8), 0);\n}\n#endif\n#if (RTL8723B_SUPPORT == 1)\nvoid odm_trx_hw_ant_div_init_8723b(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"***8723B AntDiv_Init =>  ant_div_type=[CG_TRX_HW_ANTDIV(DPDT)]\\n\");\n\n\t/* @Mapping Table */\n\todm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);\n\todm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);\n\n\t/* OFDM HW AntDiv Parameters */\n\todm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0); /* thershold */\n\todm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00); /* @bias */\n\n\t/* @CCK HW AntDiv Parameters */\n\todm_set_bb_reg(dm, R_0xa74, BIT(7), 1);\n\t\t/* patch for clk from 88M to 80M */\n\todm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);\n\t\t/* @do 64 samples */\n\n\t/* @BT Coexistence */\n\todm_set_bb_reg(dm, R_0x864, BIT(12), 0);\n\t\t/* @keep antsel_map when GNT_BT = 1 */\n\todm_set_bb_reg(dm, R_0x874, BIT(23), 0);\n\t\t/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */\n\n\t/* Output Pin Settings */\n\todm_set_bb_reg(dm, R_0x870, BIT(8), 0);\n\n\todm_set_bb_reg(dm, R_0x948, BIT(6), 0);\n\t\t/* WL_BB_SEL_BTG_TRXG_anta,  (1: HW CTRL  0: SW CTRL) */\n\todm_set_bb_reg(dm, R_0x948, BIT(7), 0);\n\n\todm_set_mac_reg(dm, R_0x40, BIT(3), 1);\n\todm_set_mac_reg(dm, R_0x38, BIT(11), 1);\n\todm_set_mac_reg(dm, R_0x4c, BIT(24) | BIT(23), 2);\n\t\t/* select DPDT_P and DPDT_N as output pin */\n\n\todm_set_bb_reg(dm, R_0x944, BIT(0) | BIT(1), 3); /* @in/out */\n\todm_set_bb_reg(dm, R_0x944, BIT(31), 0);\n\n\todm_set_bb_reg(dm, R_0x92c, BIT(1), 0); /* @DPDT_P non-inverse */\n\todm_set_bb_reg(dm, R_0x92c, BIT(0), 1); /* @DPDT_N inverse */\n\n\todm_set_bb_reg(dm, R_0x930, 0xF0, 8); /* @DPDT_P = ANTSEL[0] */\n\todm_set_bb_reg(dm, R_0x930, 0xF, 8); /* @DPDT_N = ANTSEL[0] */\n\n\t/* @2 [--For HW Bug setting] */\n\tif (dm->ant_type == ODM_AUTO_ANT)\n\t\todm_set_bb_reg(dm, R_0xa00, BIT(15), 0);\n\t\t\t/* @CCK AntDiv function block enable */\n}\n\nvoid odm_s0s1_sw_ant_div_init_8723b(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct sw_antenna_switch *swat_tab = &dm->dm_swat_table;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"***8723B AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\\n\");\n\n\t/* @Mapping Table */\n\todm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);\n\todm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);\n\n#if 0\n\t/* Output Pin Settings */\n\t/* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */\n#endif\n\todm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);\n\n\tfat_tab->is_become_linked = false;\n\tswat_tab->try_flag = SWAW_STEP_INIT;\n\tswat_tab->double_chk_flag = 0;\n\n\t/* @2 [--For HW Bug setting] */\n\todm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant  by Reg */\n}\n\nvoid odm_update_rx_idle_ant_8723b(\n\tvoid *dm_void,\n\tu8 ant,\n\tu32 default_ant,\n\tu32 optional_ant)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tvoid *adapter = dm->adapter;\n\tu8 count = 0;\n\t/*u8\t\t\tu1_temp;*/\n\t/*u8\t\t\th2c_parameter;*/\n\n\tif (!dm->is_linked && dm->ant_type == ODM_AUTO_ANT) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to no link\\n\");\n\t\treturn;\n\t}\n\n#if 0\n\t/* Send H2C command to FW */\n\t/* @Enable wifi calibration */\n\th2c_parameter = true;\n\todm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);\n\n\t/* @Check if H2C command sucess or not (0x1e6) */\n\tu1_temp = odm_read_1byte(dm, 0x1e6);\n\twhile ((u1_temp != 0x1) && (count < 100)) {\n\t\tODM_delay_us(10);\n\t\tu1_temp = odm_read_1byte(dm, 0x1e6);\n\t\tcount++;\n\t}\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[ Update Rx-Idle-ant ] 8723B: H2C command status = %d, count = %d\\n\",\n\t\t  u1_temp, count);\n\n\tif (u1_temp == 0x1) {\n\t\t/* @Check if BT is doing IQK (0x1e7) */\n\t\tcount = 0;\n\t\tu1_temp = odm_read_1byte(dm, 0x1e7);\n\t\twhile ((!(u1_temp & BIT(0)))  && (count < 100)) {\n\t\t\tODM_delay_us(50);\n\t\t\tu1_temp = odm_read_1byte(dm, 0x1e7);\n\t\t\tcount++;\n\t\t}\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ Update Rx-Idle-ant ] 8723B: BT IQK status = %d, count = %d\\n\",\n\t\t\t  u1_temp, count);\n\n\t\tif (u1_temp & BIT(0)) {\n\t\t\todm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0x948, BIT(9), default_ant);\n\t\t\todm_set_bb_reg(dm, R_0x864, 0x38, default_ant);\n\t\t\t\t\t/* @Default RX */\n\t\t\todm_set_bb_reg(dm, R_0x864, 0x1c0, optional_ant);\n\t\t\t\t\t/* @Optional RX */\n\t\t\todm_set_bb_reg(dm, R_0x860, 0x7000, default_ant);\n\t\t\t\t\t/* @Default TX */\n\t\t\tfat_tab->rx_idle_ant = ant;\n\n\t\t\t/* Set TX AGC by S0/S1 */\n\t\t\t/* Need to consider Linux driver */\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t\t\tadapter->hal_func.set_tx_power_level_handler(adapter, *dm->channel);\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t\trtw_hal_set_tx_power_level(adapter, *dm->channel);\n#endif\n\n\t\t\t/* Set IQC by S0/S1 */\n\t\t\todm_set_iqc_by_rfpath(dm, default_ant);\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\\n\");\n\t\t} else\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to BT IQK\\n\");\n\t} else\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to H2C command fail\\n\");\n\n\t/* Send H2C command to FW */\n\t/* @Disable wifi calibration */\n\th2c_parameter = false;\n\todm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);\n#else\n\n\todm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);\n\todm_set_bb_reg(dm, R_0x948, BIT(9), default_ant);\n\todm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);\n\t\t\t/*@Default RX*/\n\todm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);\n\t\t\t/*Optional RX*/\n\todm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);\n\t\t\t/*@Default TX*/\n\tfat_tab->rx_idle_ant = ant;\n\n/* Set TX AGC by S0/S1 */\n/* Need to consider Linux driver */\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel);\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\trtw_hal_set_tx_power_level(adapter, *dm->channel);\n#endif\n\n\t/* Set IQC by S0/S1 */\n\todm_set_iqc_by_rfpath(dm, default_ant);\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\\n\");\n\n#endif\n}\n\nboolean\nphydm_is_bt_enable_8723b(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 bt_state;\n#if 0\n\t/*u32\t\t\treg75;*/\n\n\t/*reg75 = odm_get_bb_reg(dm, R_0x74, BIT8);*/\n\t/*odm_set_bb_reg(dm, R_0x74, BIT8, 0x0);*/\n#endif\n\todm_set_bb_reg(dm, R_0xa0, BIT(24) | BIT(25) | BIT(26), 0x5);\n\tbt_state = odm_get_bb_reg(dm, R_0xa0, 0xf);\n#if 0\n\t/*odm_set_bb_reg(dm, R_0x74, BIT8, reg75);*/\n#endif\n\n\tif (bt_state == 4 || bt_state == 7 || bt_state == 9 || bt_state == 13)\n\t\treturn true;\n\telse\n\t\treturn false;\n}\n#endif /* @#if (RTL8723B_SUPPORT == 1) */\n\n#if (RTL8821A_SUPPORT == 1)\n\nvoid odm_trx_hw_ant_div_init_8821a(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[%s]=====>\\n\", __func__);\n\n\t/* Output Pin Settings */\n\todm_set_mac_reg(dm, R_0x4c, BIT(25), 0);\n\n\todm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */\n\todm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */\n\n\todm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);\n\n\todm_set_mac_reg(dm, R_0x4c, BIT(23), 0);\n\t\t\t/* select DPDT_P and DPDT_N as output pin */\n\todm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */\n\todm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */\n\todm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */\n\todm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */\n\todm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */\n\n\t/* @Mapping Table */\n\todm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);\n\todm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);\n\n\t/* OFDM HW AntDiv Parameters */\n\todm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */\n\todm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */\n\n\t/* @CCK HW AntDiv Parameters */\n\todm_set_bb_reg(dm, R_0xa74, BIT(7), 1);\n\t\t/* patch for clk from 88M to 80M */\n\todm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */\n\n\todm_set_bb_reg(dm, R_0x800, BIT(25), 0);\n\t\t/* @ANTSEL_CCK sent to the smart_antenna circuit */\n\todm_set_bb_reg(dm, R_0xa00, BIT(15), 0);\n\t\t/* @CCK AntDiv function block enable */\n\n\t/* @BT Coexistence */\n\todm_set_bb_reg(dm, R_0xcac, BIT(9), 1);\n\t\t/* @keep antsel_map when GNT_BT = 1 */\n\todm_set_bb_reg(dm, R_0x804, BIT(4), 1);\n\t\t/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */\n\n\todm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);\n\t\t/* settling time of antdiv by RF LNA = 100ns */\n\n\t/* response TX ant by RX ant */\n\todm_set_mac_reg(dm, R_0x668, BIT(3), 1);\n}\n\nvoid odm_s0s1_sw_ant_div_init_8821a(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct sw_antenna_switch *swat_tab = &dm->dm_swat_table;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[%s]=====>\\n\", __func__);\n\n\t/* Output Pin Settings */\n\todm_set_mac_reg(dm, R_0x4c, BIT(25), 0);\n\n\todm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */\n\todm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */\n\n\todm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);\n\n\todm_set_mac_reg(dm, R_0x4c, BIT(23), 0);\n\t\t/* select DPDT_P and DPDT_N as output pin */\n\todm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */\n\todm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */\n\todm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */\n\todm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */\n\todm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */\n\n\t/* @Mapping Table */\n\todm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);\n\todm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);\n\n\t/* OFDM HW AntDiv Parameters */\n\todm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */\n\todm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */\n\n\t/* @CCK HW AntDiv Parameters */\n\todm_set_bb_reg(dm, R_0xa74, BIT(7), 1);\n\t\t/* patch for clk from 88M to 80M */\n\todm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */\n\n\todm_set_bb_reg(dm, R_0x800, BIT(25), 0);\n\t\t/* @ANTSEL_CCK sent to the smart_antenna circuit */\n\todm_set_bb_reg(dm, R_0xa00, BIT(15), 0);\n\t\t/* @CCK AntDiv function block enable */\n\n\t/* @BT Coexistence */\n\todm_set_bb_reg(dm, R_0xcac, BIT(9), 1);\n\t\t/* @keep antsel_map when GNT_BT = 1 */\n\todm_set_bb_reg(dm, R_0x804, BIT(4), 1);\n\t\t/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */\n\n\todm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);\n\t\t/* settling time of antdiv by RF LNA = 100ns */\n\n\t/* response TX ant by RX ant */\n\todm_set_mac_reg(dm, R_0x668, BIT(3), 1);\n\n\todm_set_bb_reg(dm, R_0x900, BIT(18), 0);\n\n\tswat_tab->try_flag = SWAW_STEP_INIT;\n\tswat_tab->double_chk_flag = 0;\n\tswat_tab->cur_antenna = MAIN_ANT;\n\tswat_tab->pre_ant = MAIN_ANT;\n\tswat_tab->swas_no_link_state = 0;\n}\n#endif /* @#if (RTL8821A_SUPPORT == 1) */\n\n#if (RTL8821C_SUPPORT == 1)\nvoid odm_trx_hw_ant_div_init_8821c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[%s]=====>\\n\", __func__);\n\t/* Output Pin Settings */\n\todm_set_mac_reg(dm, R_0x4c, BIT(25), 0);\n\n\todm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */\n\todm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */\n\n\todm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);\n\n\todm_set_mac_reg(dm, R_0x4c, BIT(23), 0);\n\t\t/* select DPDT_P and DPDT_N as output pin */\n\todm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */\n\todm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */\n\todm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */\n\todm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */\n\todm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */\n\n\t/* @Mapping Table */\n\todm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);\n\todm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);\n\n\t/* OFDM HW AntDiv Parameters */\n\todm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */\n\todm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */\n\n\t/* @CCK HW AntDiv Parameters */\n\todm_set_bb_reg(dm, R_0xa74, BIT(7), 1);\n\t\t/* patch for clk from 88M to 80M */\n\todm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */\n\n\todm_set_bb_reg(dm, R_0x800, BIT(25), 0);\n\t\t/* @ANTSEL_CCK sent to the smart_antenna circuit */\n\todm_set_bb_reg(dm, R_0xa00, BIT(15), 0);\n\t\t/* @CCK AntDiv function block enable */\n\n\t/* @BT Coexistence */\n\todm_set_bb_reg(dm, R_0xcac, BIT(9), 1);\n\t\t/* @keep antsel_map when GNT_BT = 1 */\n\todm_set_bb_reg(dm, R_0x804, BIT(4), 1);\n\t\t/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */\n\n\t/* Timming issue */\n\todm_set_bb_reg(dm, R_0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), 0);\n\t\t/*@keep antidx after tx for ACK ( unit x 3.2 mu sec)*/\n\todm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);\n\t\t/* settling time of antdiv by RF LNA = 100ns */\n\n\t/* response TX ant by RX ant */\n\todm_set_mac_reg(dm, R_0x668, BIT(3), 1);\n}\n\nvoid phydm_s0s1_sw_ant_div_init_8821c(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct sw_antenna_switch *swat_tab = &dm->dm_swat_table;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[%s]=====>\\n\", __func__);\n\n\t/* Output Pin Settings */\n\todm_set_mac_reg(dm, R_0x4c, BIT(25), 0);\n\n\todm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */\n\todm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */\n\n\todm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);\n\n\todm_set_mac_reg(dm, R_0x4c, BIT(23), 0);\n\t\t/* select DPDT_P and DPDT_N as output pin */\n\todm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */\n\todm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */\n\todm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */\n\todm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */\n\todm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */\n\n\t/* @Mapping Table */\n\todm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);\n\todm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);\n\n\t/* OFDM HW AntDiv Parameters */\n\todm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */\n\todm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x00); /* @bias */\n\n\t/* @CCK HW AntDiv Parameters */\n\todm_set_bb_reg(dm, R_0xa74, BIT(7), 1);\n\t\t/* patch for clk from 88M to 80M */\n\todm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */\n\n\todm_set_bb_reg(dm, R_0x800, BIT(25), 0);\n\t\t/* @ANTSEL_CCK sent to the smart_antenna circuit */\n\todm_set_bb_reg(dm, R_0xa00, BIT(15), 0);\n\t\t/* @CCK AntDiv function block enable */\n\n\t/* @BT Coexistence */\n\todm_set_bb_reg(dm, R_0xcac, BIT(9), 1);\n\t\t/* @keep antsel_map when GNT_BT = 1 */\n\todm_set_bb_reg(dm, R_0x804, BIT(4), 1);\n\t\t/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */\n\n\todm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);\n\t\t/* settling time of antdiv by RF LNA = 100ns */\n\n\t/* response TX ant by RX ant */\n\todm_set_mac_reg(dm, R_0x668, BIT(3), 1);\n\n\todm_set_bb_reg(dm, R_0x900, BIT(18), 0);\n\n\tswat_tab->try_flag = SWAW_STEP_INIT;\n\tswat_tab->double_chk_flag = 0;\n\tswat_tab->cur_antenna = MAIN_ANT;\n\tswat_tab->pre_ant = MAIN_ANT;\n\tswat_tab->swas_no_link_state = 0;\n}\n#endif /* @#if (RTL8821C_SUPPORT == 1) */\n\n#if (RTL8881A_SUPPORT == 1)\nvoid odm_trx_hw_ant_div_init_8881a(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[%s]=====>\\n\", __func__);\n\n\t/* Output Pin Settings */\n\t/* @[SPDT related] */\n\todm_set_mac_reg(dm, R_0x4c, BIT(25), 0);\n\todm_set_mac_reg(dm, R_0x4c, BIT(26), 0);\n\todm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */\n\todm_set_bb_reg(dm, R_0xcb4, BIT(22), 0);\n\todm_set_bb_reg(dm, R_0xcb4, BIT(24), 1);\n\todm_set_bb_reg(dm, R_0xcb0, 0xF00, 8); /* @DPDT_P = ANTSEL[0] */\n\todm_set_bb_reg(dm, R_0xcb0, 0xF0000, 8); /* @DPDT_N = ANTSEL[0] */\n\n\t/* @Mapping Table */\n\todm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);\n\todm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);\n\n\t/* OFDM HW AntDiv Parameters */\n\todm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */\n\todm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */\n\todm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);\n\t\t/* settling time of antdiv by RF LNA = 100ns */\n\n\t/* @CCK HW AntDiv Parameters */\n\todm_set_bb_reg(dm, R_0xa74, BIT(7), 1);\n\t\t/* patch for clk from 88M to 80M */\n\todm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */\n\n\t/* @2 [--For HW Bug setting] */\n\n\todm_set_bb_reg(dm, R_0x900, BIT(18), 0);\n\t\t/* TX ant  by Reg *//* A-cut bug */\n}\n\n#endif /* @#if (RTL8881A_SUPPORT == 1) */\n\n#if (RTL8812A_SUPPORT == 1)\nvoid odm_trx_hw_ant_div_init_8812a(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[%s]=====>\\n\", __func__);\n\n\t/* @3 */ /* @3 --RFE pin setting--------- */\n\t/* @[BB] */\n\todm_set_bb_reg(dm, R_0x900, BIT(10) | BIT(9) | BIT(8), 0x0);\n\t\t/* @disable SW switch */\n\todm_set_bb_reg(dm, R_0x900, BIT(17) | BIT(16), 0x0);\n\todm_set_bb_reg(dm, R_0x974, BIT(7) | BIT(6), 0x3); /* @in/out */\n\todm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */\n\todm_set_bb_reg(dm, R_0xcb4, BIT(26), 0);\n\todm_set_bb_reg(dm, R_0xcb4, BIT(27), 1);\n\todm_set_bb_reg(dm, R_0xcb0, 0xF000000, 8); /* @DPDT_P = ANTSEL[0] */\n\todm_set_bb_reg(dm, R_0xcb0, 0xF0000000, 8); /* @DPDT_N = ANTSEL[0] */\n\t/* @3 ------------------------- */\n\n\t/* @Mapping Table */\n\todm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);\n\todm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);\n\n\t/* OFDM HW AntDiv Parameters */\n\todm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */\n\todm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */\n\todm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);\n\t\t/* settling time of antdiv by RF LNA = 100ns */\n\n\t/* @CCK HW AntDiv Parameters */\n\todm_set_bb_reg(dm, R_0xa74, BIT(7), 1);\n\t\t/* patch for clk from 88M to 80M */\n\todm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */\n\n\t/* @2 [--For HW Bug setting] */\n\n\todm_set_bb_reg(dm, R_0x900, BIT(18), 0);\n\t\t/* TX ant  by Reg */ /* A-cut bug */\n}\n\n#endif /* @#if (RTL8812A_SUPPORT == 1) */\n\n#if (RTL8188F_SUPPORT == 1)\nvoid odm_s0s1_sw_ant_div_init_8188f(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct sw_antenna_switch *swat_tab = &dm->dm_swat_table;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[%s]=====>\\n\", __func__);\n\n#if 0\n\t/*@GPIO setting*/\n\t/*odm_set_mac_reg(dm, R_0x64, BIT(18), 0); */\n\t/*odm_set_mac_reg(dm, R_0x44, BIT(28)|BIT(27), 0);*/\n\t/*odm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3);*/\n\t\t/*enable_output for P_GPIO[4:3]*/\n\t/*odm_set_mac_reg(dm, R_0x44, BIT(12)|BIT(11), 0);*/ /*output value*/\n\t/*odm_set_mac_reg(dm, R_0x40, BIT(1)|BIT(0), 0);*/ /*GPIO function*/\n#endif\n\n\tif (dm->support_ic_type == ODM_RTL8188F) {\n\t\tif (dm->support_interface == ODM_ITRF_USB)\n\t\t\todm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3);\n\t\t\t\t/*@enable_output for P_GPIO[4:3]*/\n\t\telse if (dm->support_interface == ODM_ITRF_SDIO)\n\t\t\todm_set_mac_reg(dm, R_0x44, BIT(18), 0x1);\n\t\t\t\t/*@enable_output for P_GPIO[2]*/\n\t}\n\n\tfat_tab->is_become_linked = false;\n\tswat_tab->try_flag = SWAW_STEP_INIT;\n\tswat_tab->double_chk_flag = 0;\n}\n\nvoid phydm_update_rx_idle_antenna_8188F(void *dm_void, u32 default_ant)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 codeword;\n\n\tif (dm->support_ic_type == ODM_RTL8188F) {\n\t\tif (dm->support_interface == ODM_ITRF_USB) {\n\t\t\tif (default_ant == ANT1_2G)\n\t\t\t\tcodeword = 1; /*@2'b01*/\n\t\t\telse\n\t\t\t\tcodeword = 2; /*@2'b10*/\n\t\t\todm_set_mac_reg(dm, R_0x44, 0x1800, codeword);\n\t\t\t\t/*@GPIO[4:3] output value*/\n\t\t} else if (dm->support_interface == ODM_ITRF_SDIO) {\n\t\t\tif (default_ant == ANT1_2G) {\n\t\t\t\tcodeword = 0; /*@1'b0*/\n\t\t\t\todm_set_bb_reg(dm, R_0x870, 0x300, 0x3);\n\t\t\t\todm_set_bb_reg(dm, R_0x860, 0x300, 0x1);\n\t\t\t} else {\n\t\t\t\tcodeword = 1; /*@1'b1*/\n\t\t\t\todm_set_bb_reg(dm, R_0x870, 0x300, 0x3);\n\t\t\t\todm_set_bb_reg(dm, R_0x860, 0x300, 0x2);\n\t\t\t}\n\t\t\todm_set_mac_reg(dm, R_0x44, BIT(10), codeword);\n\t\t\t\t/*@GPIO[2] output value*/\n\t\t}\n\t}\n}\n#endif\n\n#ifdef ODM_EVM_ENHANCE_ANTDIV\nvoid phydm_rx_rate_for_antdiv(void *dm_void, void *pkt_info_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tstruct phydm_perpkt_info_struct *pktinfo = NULL;\n\tu8 data_rate = 0;\n\n\tpktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;\n\tdata_rate = pktinfo->data_rate & 0x7f;\n\n\tif (!fat_tab->get_stats)\n\t\treturn;\n\n\tif (fat_tab->antsel_rx_keep_0 == ANT1_2G) {\n\t\tif (data_rate >= ODM_RATEMCS0 &&\n\t\t    data_rate <= ODM_RATEMCS15)\n\t\t\tfat_tab->main_ht_cnt[data_rate - ODM_RATEMCS0]++;\n\t\telse if (data_rate >= ODM_RATEVHTSS1MCS0 &&\n\t\t\t data_rate <= ODM_RATEVHTSS2MCS9)\n\t\t\tfat_tab->main_vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++;\n\t} else { /*ANT2_2G*/\n\t\tif (data_rate >= ODM_RATEMCS0 &&\n\t\t    data_rate <= ODM_RATEMCS15)\n\t\t\tfat_tab->aux_ht_cnt[data_rate - ODM_RATEMCS0]++;\n\t\telse if (data_rate >= ODM_RATEVHTSS1MCS0 &&\n\t\t\t data_rate <= ODM_RATEVHTSS2MCS9)\n\t\t\tfat_tab->aux_vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++;\n\t}\n}\n\nvoid phydm_antdiv_reset_rx_rate(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\todm_memory_set(dm, &fat_tab->main_ht_cnt[0], 0, HT_IDX * 2);\n\todm_memory_set(dm, &fat_tab->aux_ht_cnt[0], 0, HT_IDX * 2);\n\todm_memory_set(dm, &fat_tab->main_vht_cnt[0], 0, VHT_IDX * 2);\n\todm_memory_set(dm, &fat_tab->aux_vht_cnt[0], 0, VHT_IDX * 2);\n}\n\nvoid phydm_statistics_evm_1ss(void *dm_void,\tvoid *phy_info_void,\n\t\t\t      u8 antsel_tr_mux, u32 id, u32 utility)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tstruct phydm_phyinfo_struct *phy_info = NULL;\n\n\tphy_info = (struct phydm_phyinfo_struct *)phy_info_void;\n\tif (antsel_tr_mux == ANT1_2G) {\n\t\tfat_tab->main_evm_sum[id] += ((phy_info->rx_mimo_evm_dbm[0])\n\t\t\t\t\t     << 5);\n\t\tfat_tab->main_evm_cnt[id]++;\n\t} else {\n\t\tfat_tab->aux_evm_sum[id] += ((phy_info->rx_mimo_evm_dbm[0])\n\t\t\t\t\t    << 5);\n\t\tfat_tab->aux_evm_cnt[id]++;\n\t}\n}\n\nvoid phydm_statistics_evm_2ss(void *dm_void,\tvoid *phy_info_void,\n\t\t\t      u8 antsel_tr_mux, u32 id, u32 utility)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tstruct phydm_phyinfo_struct *phy_info = NULL;\n\n\tphy_info = (struct phydm_phyinfo_struct *)phy_info_void;\n\tif (antsel_tr_mux == ANT1_2G) {\n\t\tfat_tab->main_evm_2ss_sum[id][0] += phy_info->rx_mimo_evm_dbm[0]\n\t\t\t\t\t\t    << 5;\n\t\tfat_tab->main_evm_2ss_sum[id][1] += phy_info->rx_mimo_evm_dbm[1]\n\t\t\t\t\t\t    << 5;\n\t\tfat_tab->main_evm_2ss_cnt[id]++;\n\n\t} else {\n\t\tfat_tab->aux_evm_2ss_sum[id][0] += (phy_info->rx_mimo_evm_dbm[0]\n\t\t\t\t\t\t   << 5);\n\t\tfat_tab->aux_evm_2ss_sum[id][1] += (phy_info->rx_mimo_evm_dbm[1]\n\t\t\t\t\t\t   << 5);\n\t\tfat_tab->aux_evm_2ss_cnt[id]++;\n\t}\n}\n\nvoid phydm_evm_sw_antdiv_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\t/*@EVM enhance AntDiv method init----------------*/\n\tfat_tab->evm_method_enable = 0;\n\tfat_tab->fat_state = NORMAL_STATE_MIAN;\n\tfat_tab->fat_state_cnt = 0;\n\tfat_tab->pre_antdiv_rssi = 0;\n\n\tdm->antdiv_intvl = 30;\n\tdm->antdiv_delay = 20;\n\tdm->antdiv_train_num = 4;\n\todm_set_bb_reg(dm, R_0x910, 0x3f, 0xf);\n\tdm->antdiv_evm_en = 1;\n\t/*@dm->antdiv_period=1;*/\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\tdm->evm_antdiv_period = 1;\n#else\n\tdm->evm_antdiv_period = 3;\n#endif\n\tdm->stop_antdiv_rssi_th = 3;\n\tdm->stop_antdiv_tp_th = 80;\n\tdm->antdiv_tp_period = 3;\n\tdm->stop_antdiv_tp_diff_th = 5;\n}\n\nvoid odm_evm_fast_ant_reset(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\tfat_tab->evm_method_enable = 0;\n\tif (fat_tab->div_path_type == ANT_PATH_A)\n\t\todm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);\n\telse if (fat_tab->div_path_type == ANT_PATH_B)\n\t\todm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);\n\telse if (fat_tab->div_path_type == ANT_PATH_AB)\n\t\todm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);\n\tfat_tab->fat_state = NORMAL_STATE_MIAN;\n\tfat_tab->fat_state_cnt = 0;\n\tdm->antdiv_period = 0;\n\todm_set_mac_reg(dm, R_0x608, BIT(8), 0);\n}\n\nvoid odm_evm_enhance_ant_div(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 main_rssi, aux_rssi;\n\tu32 main_crc_utility = 0, aux_crc_utility = 0, utility_ratio = 1;\n\tu32 main_evm, aux_evm, diff_rssi = 0, diff_EVM = 0;\n\tu32 main_2ss_evm[2], aux_2ss_evm[2];\n\tu32 main_1ss_evm, aux_1ss_evm;\n\tu32 main_2ss_evm_sum, aux_2ss_evm_sum;\n\tu8 score_EVM = 0, score_CRC = 0;\n\tu8 rssi_larger_ant = 0;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tu32 value32, i, mac_id;\n\tboolean main_above1 = false, aux_above1 = false;\n\tboolean force_antenna = false;\n\tstruct cmn_sta_info *sta;\n\tu32 main_tp_avg, aux_tp_avg;\n\tu8 curr_rssi, rssi_diff;\n\tu32 tp_diff, tp_diff_avg;\n\tu16 main_max_cnt = 0, aux_max_cnt = 0;\n\tu16 main_max_idx = 0, aux_max_idx = 0;\n\tu16 main_cnt_all = 0, aux_cnt_all = 0;\n\tu8 rate_num = dm->num_rf_path;\n\tu8 rate_ss_shift = 0;\n\tu8 tp_diff_return = 0, tp_return = 0, rssi_return = 0;\n\tu8 target_ant_evm_1ss, target_ant_evm_2ss;\n\tu8 decision_evm_ss;\n\tu8 next_ant;\n\n\tfat_tab->target_ant_enhance = 0xFF;\n\n\tif ((dm->support_ic_type & ODM_EVM_ANTDIV_IC)) {\n\t\tif (dm->is_one_entry_only) {\n#if 0\n\t\t\t/* PHYDM_DBG(dm,DBG_ANT_DIV, \"[One Client only]\\n\"); */\n#endif\n\t\t\tmac_id = dm->one_entry_macid;\n\t\t\tsta = dm->phydm_sta_info[mac_id];\n\n\t\t\tmain_rssi = (fat_tab->main_cnt[mac_id] != 0) ? (fat_tab->main_sum[mac_id] / fat_tab->main_cnt[mac_id]) : 0;\n\t\t\taux_rssi = (fat_tab->aux_cnt[mac_id] != 0) ? (fat_tab->aux_sum[mac_id] / fat_tab->aux_cnt[mac_id]) : 0;\n\n\t\t\tif ((main_rssi == 0 && aux_rssi != 0 && aux_rssi >= FORCE_RSSI_DIFF) || (main_rssi != 0 && aux_rssi == 0 && main_rssi >= FORCE_RSSI_DIFF))\n\t\t\t\tdiff_rssi = FORCE_RSSI_DIFF;\n\t\t\telse if (main_rssi != 0 && aux_rssi != 0)\n\t\t\t\tdiff_rssi = (main_rssi >= aux_rssi) ? (main_rssi - aux_rssi) : (aux_rssi - main_rssi);\n\n\t\t\tif (main_rssi >= aux_rssi)\n\t\t\t\trssi_larger_ant = MAIN_ANT;\n\t\t\telse\n\t\t\t\trssi_larger_ant = AUX_ANT;\n\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"Main_Cnt=(( %d )), main_rssi=(( %d ))\\n\",\n\t\t\t\t  fat_tab->main_cnt[mac_id], main_rssi);\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"Aux_Cnt=(( %d )), aux_rssi=(( %d ))\\n\",\n\t\t\t\t  fat_tab->aux_cnt[mac_id], aux_rssi);\n\n\t\t\tif (((main_rssi >= evm_rssi_th_high || aux_rssi >= evm_rssi_th_high) || fat_tab->evm_method_enable == 1)\n\t\t\t    /* @&& (diff_rssi <= FORCE_RSSI_DIFF + 1) */\n\t\t\t    ) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"> TH_H || evm_method_enable==1\\n\");\n\n\t\t\t\tif ((main_rssi >= evm_rssi_th_low || aux_rssi >= evm_rssi_th_low)) {\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"> TH_L, fat_state_cnt =((%d))\\n\", fat_tab->fat_state_cnt);\n\n\t\t\t\t\t/*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)============================================================*/\n\t\t\t\t\tif (fat_tab->fat_state_cnt < (dm->antdiv_train_num << 1)) {\n\t\t\t\t\t\tif (fat_tab->fat_state_cnt == 0) {\n\t\t\t\t\t\t\t/*Reset EVM 1SS Method */\n\t\t\t\t\t\t\tfat_tab->main_evm_sum[mac_id] = 0;\n\t\t\t\t\t\t\tfat_tab->aux_evm_sum[mac_id] = 0;\n\t\t\t\t\t\t\tfat_tab->main_evm_cnt[mac_id] = 0;\n\t\t\t\t\t\t\tfat_tab->aux_evm_cnt[mac_id] = 0;\n\t\t\t\t\t\t\t/*Reset EVM 2SS Method */\n\t\t\t\t\t\t\tfat_tab->main_evm_2ss_sum[mac_id][0] = 0;\n\t\t\t\t\t\t\tfat_tab->main_evm_2ss_sum[mac_id][1] = 0;\n\t\t\t\t\t\t\tfat_tab->aux_evm_2ss_sum[mac_id][0] = 0;\n\t\t\t\t\t\t\tfat_tab->aux_evm_2ss_sum[mac_id][1] = 0;\n\t\t\t\t\t\t\tfat_tab->main_evm_2ss_cnt[mac_id] = 0;\n\t\t\t\t\t\t\tfat_tab->aux_evm_2ss_cnt[mac_id] = 0;\n\n\t\t\t\t\t\t\t/*Reset TP Method */\n\t\t\t\t\t\t\tfat_tab->main_tp = 0;\n\t\t\t\t\t\t\tfat_tab->aux_tp = 0;\n\t\t\t\t\t\t\tfat_tab->main_tp_cnt = 0;\n\t\t\t\t\t\t\tfat_tab->aux_tp_cnt = 0;\n\t\t\t\t\t\t\tphydm_antdiv_reset_rx_rate(dm);\n\n\t\t\t\t\t\t\t/*Reset CRC Method */\n\t\t\t\t\t\t\tfat_tab->main_crc32_ok_cnt = 0;\n\t\t\t\t\t\t\tfat_tab->main_crc32_fail_cnt = 0;\n\t\t\t\t\t\t\tfat_tab->aux_crc32_ok_cnt = 0;\n\t\t\t\t\t\t\tfat_tab->aux_crc32_fail_cnt = 0;\n\n#ifdef SKIP_EVM_ANTDIV_TRAINING_PATCH\n\t\t\t\t\t\t\tif ((*dm->band_width == CHANNEL_WIDTH_20) && sta->mimo_type == RF_2T2R) {\n\t\t\t\t\t\t\t\t/*@1. Skip training: RSSI*/\n#if 0\n\t\t\t\t\t\t\t\t/*PHYDM_DBG(pDM_Odm,DBG_ANT_DIV, \"TargetAnt_enhance=((%d)), RxIdleAnt=((%d))\\n\", pDM_FatTable->TargetAnt_enhance, pDM_FatTable->RxIdleAnt);*/\n#endif\n\t\t\t\t\t\t\t\tcurr_rssi = (u8)((fat_tab->rx_idle_ant == MAIN_ANT) ? main_rssi : aux_rssi);\n\t\t\t\t\t\t\t\trssi_diff = (curr_rssi > fat_tab->pre_antdiv_rssi) ? (curr_rssi - fat_tab->pre_antdiv_rssi) : (fat_tab->pre_antdiv_rssi - curr_rssi);\n\n\t\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[1] rssi_return, curr_rssi=((%d)), pre_rssi=((%d))\\n\", curr_rssi, fat_tab->pre_antdiv_rssi);\n\n\t\t\t\t\t\t\t\tfat_tab->pre_antdiv_rssi = curr_rssi;\n\t\t\t\t\t\t\t\tif (rssi_diff < dm->stop_antdiv_rssi_th && curr_rssi != 0)\n\t\t\t\t\t\t\t\t\trssi_return = 1;\n\n\t\t\t\t\t\t\t\t/*@2. Skip training: TP Diff*/\n\t\t\t\t\t\t\t\ttp_diff = (dm->rx_tp > fat_tab->pre_antdiv_tp) ? (dm->rx_tp - fat_tab->pre_antdiv_tp) : (fat_tab->pre_antdiv_tp - dm->rx_tp);\n\n\t\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[2] tp_diff_return, curr_tp=((%d)), pre_tp=((%d))\\n\", dm->rx_tp, fat_tab->pre_antdiv_tp);\n\t\t\t\t\t\t\t\tfat_tab->pre_antdiv_tp = dm->rx_tp;\n\t\t\t\t\t\t\t\tif ((tp_diff < (u32)(dm->stop_antdiv_tp_diff_th) && dm->rx_tp != 0))\n\t\t\t\t\t\t\t\t\ttp_diff_return = 1;\n\n\t\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[3] tp_return, curr_rx_tp=((%d))\\n\", dm->rx_tp);\n\t\t\t\t\t\t\t\t/*@3. Skip training: TP*/\n\t\t\t\t\t\t\t\tif (dm->rx_tp >= (u32)(dm->stop_antdiv_tp_th))\n\t\t\t\t\t\t\t\t\ttp_return = 1;\n\n\t\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[4] Return {rssi, tp_diff, tp} = {%d, %d, %d}\\n\", rssi_return, tp_diff_return, tp_return);\n\t\t\t\t\t\t\t\t/*@4. Joint Return Decision*/\n\t\t\t\t\t\t\t\tif (tp_return) {\n\t\t\t\t\t\t\t\t\tif (tp_diff_return || rssi_diff) {\n\t\t\t\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"***Return EVM SW AntDiv\\n\");\n\t\t\t\t\t\t\t\t\t\treturn;\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n#endif\n\n\t\t\t\t\t\t\tfat_tab->evm_method_enable = 1;\n\t\t\t\t\t\t\tif (fat_tab->div_path_type == ANT_PATH_A)\n\t\t\t\t\t\t\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);\n\t\t\t\t\t\t\telse if (fat_tab->div_path_type == ANT_PATH_B)\n\t\t\t\t\t\t\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);\n\t\t\t\t\t\t\telse if (fat_tab->div_path_type == ANT_PATH_AB)\n\t\t\t\t\t\t\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);\n\t\t\t\t\t\t\tdm->antdiv_period = dm->evm_antdiv_period;\n\t\t\t\t\t\t\todm_set_mac_reg(dm, R_0x608, BIT(8), 1); /*RCR accepts CRC32-Error packets*/\n\t\t\t\t\t\t\tfat_tab->fat_state_cnt++;\n\t\t\t\t\t\t\tfat_tab->get_stats = false;\n\t\t\t\t\t\t\tnext_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? MAIN_ANT : AUX_ANT;\n\t\t\t\t\t\t\todm_update_rx_idle_ant(dm, next_ant);\n\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[Antdiv Delay ]\\n\");\n\t\t\t\t\t\t\todm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_delay); //ms\n\t\t\t\t\t\t} else if ((fat_tab->fat_state_cnt % 2) != 0) {\n\t\t\t\t\t\t\tfat_tab->fat_state_cnt++;\n\t\t\t\t\t\t\tfat_tab->get_stats = true;\n\t\t\t\t\t\t\todm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_intvl); //ms\n\t\t\t\t\t\t} else if ((fat_tab->fat_state_cnt % 2) == 0) {\n\t\t\t\t\t\t\tfat_tab->fat_state_cnt++;\n\t\t\t\t\t\t\tfat_tab->get_stats = false;\n\t\t\t\t\t\t\tnext_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;\n\t\t\t\t\t\t\todm_update_rx_idle_ant(dm, next_ant);\n\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[Antdiv Delay ]\\n\");\n\t\t\t\t\t\t\todm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_delay); //ms\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\t/*@Decision state: 4==============================================================*/\n\t\t\t\t\telse {\n\t\t\t\t\t\tfat_tab->get_stats = false;\n\t\t\t\t\t\tfat_tab->fat_state_cnt = 0;\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[Decisoin state ]\\n\");\n\n/* @3 [CRC32 statistic] */\n#if 0\n\t\t\t\t\t\tif ((fat_tab->main_crc32_ok_cnt > (fat_tab->aux_crc32_ok_cnt << 1)) || (diff_rssi >= 40 && rssi_larger_ant == MAIN_ANT)) {\n\t\t\t\t\t\t\tfat_tab->target_ant_crc32 = MAIN_ANT;\n\t\t\t\t\t\t\tforce_antenna = true;\n\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"CRC32 Force Main\\n\");\n\t\t\t\t\t\t} else if ((fat_tab->aux_crc32_ok_cnt > ((fat_tab->main_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == AUX_ANT))) {\n\t\t\t\t\t\t\tfat_tab->target_ant_crc32 = AUX_ANT;\n\t\t\t\t\t\t\tforce_antenna = true;\n\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"CRC32 Force Aux\\n\");\n\t\t\t\t\t\t} else\n#endif\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif (fat_tab->main_crc32_fail_cnt <= 5)\n\t\t\t\t\t\t\t\tfat_tab->main_crc32_fail_cnt = 5;\n\n\t\t\t\t\t\t\tif (fat_tab->aux_crc32_fail_cnt <= 5)\n\t\t\t\t\t\t\t\tfat_tab->aux_crc32_fail_cnt = 5;\n\n\t\t\t\t\t\t\tif (fat_tab->main_crc32_ok_cnt > fat_tab->main_crc32_fail_cnt)\n\t\t\t\t\t\t\t\tmain_above1 = true;\n\n\t\t\t\t\t\t\tif (fat_tab->aux_crc32_ok_cnt > fat_tab->aux_crc32_fail_cnt)\n\t\t\t\t\t\t\t\taux_above1 = true;\n\n\t\t\t\t\t\t\tif (main_above1 == true && aux_above1 == false) {\n\t\t\t\t\t\t\t\tforce_antenna = true;\n\t\t\t\t\t\t\t\tfat_tab->target_ant_crc32 = MAIN_ANT;\n\t\t\t\t\t\t\t} else if (main_above1 == false && aux_above1 == true) {\n\t\t\t\t\t\t\t\tforce_antenna = true;\n\t\t\t\t\t\t\t\tfat_tab->target_ant_crc32 = AUX_ANT;\n\t\t\t\t\t\t\t} else if (main_above1 == true && aux_above1 == true) {\n\t\t\t\t\t\t\t\tmain_crc_utility = ((fat_tab->main_crc32_ok_cnt) << 7) / fat_tab->main_crc32_fail_cnt;\n\t\t\t\t\t\t\t\taux_crc_utility = ((fat_tab->aux_crc32_ok_cnt) << 7) / fat_tab->aux_crc32_fail_cnt;\n\t\t\t\t\t\t\t\tfat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility >= aux_crc_utility) ? MAIN_ANT : AUX_ANT);\n\n\t\t\t\t\t\t\t\tif (main_crc_utility != 0 && aux_crc_utility != 0) {\n\t\t\t\t\t\t\t\t\tif (main_crc_utility >= aux_crc_utility)\n\t\t\t\t\t\t\t\t\t\tutility_ratio = (main_crc_utility << 1) / aux_crc_utility;\n\t\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\t\tutility_ratio = (aux_crc_utility << 1) / main_crc_utility;\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t} else if (main_above1 == false && aux_above1 == false) {\n\t\t\t\t\t\t\t\tif (fat_tab->main_crc32_ok_cnt == 0)\n\t\t\t\t\t\t\t\t\tfat_tab->main_crc32_ok_cnt = 1;\n\t\t\t\t\t\t\t\tif (fat_tab->aux_crc32_ok_cnt == 0)\n\t\t\t\t\t\t\t\t\tfat_tab->aux_crc32_ok_cnt = 1;\n\n\t\t\t\t\t\t\t\tmain_crc_utility = ((fat_tab->main_crc32_fail_cnt) << 7) / fat_tab->main_crc32_ok_cnt;\n\t\t\t\t\t\t\t\taux_crc_utility = ((fat_tab->aux_crc32_fail_cnt) << 7) / fat_tab->aux_crc32_ok_cnt;\n\t\t\t\t\t\t\t\tfat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility <= aux_crc_utility) ? MAIN_ANT : AUX_ANT);\n\n\t\t\t\t\t\t\t\tif (main_crc_utility != 0 && aux_crc_utility != 0) {\n\t\t\t\t\t\t\t\t\tif (main_crc_utility >= aux_crc_utility)\n\t\t\t\t\t\t\t\t\t\tutility_ratio = (main_crc_utility << 1) / (aux_crc_utility);\n\t\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\t\tutility_ratio = (aux_crc_utility << 1) / (main_crc_utility);\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\todm_set_mac_reg(dm, R_0x608, BIT(8), 0); /* NOT Accept CRC32 Error packets. */\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"MAIN_CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\\n\", fat_tab->main_crc32_ok_cnt, fat_tab->main_crc32_fail_cnt, main_crc_utility);\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"AUX__CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\\n\", fat_tab->aux_crc32_ok_cnt, fat_tab->aux_crc32_fail_cnt, aux_crc_utility);\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"***1.TargetAnt_CRC32 = ((%s))\\n\", (fat_tab->target_ant_crc32 == MAIN_ANT) ? \"MAIN_ANT\" : \"AUX_ANT\");\n\n\t\t\t\t\t\tfor (i = 0; i < HT_IDX; i++) {\n\t\t\t\t\t\t\tmain_cnt_all += fat_tab->main_ht_cnt[i];\n\t\t\t\t\t\t\taux_cnt_all += fat_tab->aux_ht_cnt[i];\n\n\t\t\t\t\t\t\tif (fat_tab->main_ht_cnt[i] > main_max_cnt) {\n\t\t\t\t\t\t\t\tmain_max_cnt = fat_tab->main_ht_cnt[i];\n\t\t\t\t\t\t\t\tmain_max_idx = i;\n\t\t\t\t\t\t\t}\n\n\t\t\t\t\t\t\tif (fat_tab->aux_ht_cnt[i] > aux_max_cnt) {\n\t\t\t\t\t\t\t\taux_max_cnt = fat_tab->aux_ht_cnt[i];\n\t\t\t\t\t\t\t\taux_max_idx = i;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\n\t\t\t\t\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\t\t\t\t\trate_ss_shift = (i << 3);\n\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"*main_ht_cnt  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t\t\t\t\t\t(rate_ss_shift), (rate_ss_shift + 7),\n\t\t\t\t\t\t\tfat_tab->main_ht_cnt[rate_ss_shift + 0], fat_tab->main_ht_cnt[rate_ss_shift + 1],\n\t\t\t\t\t\t\tfat_tab->main_ht_cnt[rate_ss_shift + 2], fat_tab->main_ht_cnt[rate_ss_shift + 3],\n\t\t\t\t\t\t\tfat_tab->main_ht_cnt[rate_ss_shift + 4], fat_tab->main_ht_cnt[rate_ss_shift + 5],\n\t\t\t\t\t\t\tfat_tab->main_ht_cnt[rate_ss_shift + 6], fat_tab->main_ht_cnt[rate_ss_shift + 7]);\n\t\t\t\t\t\t}\n\n\t\t\t\t\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\t\t\t\t\trate_ss_shift = (i << 3);\n\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"*aux_ht_cnt  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t\t\t\t\t\t(rate_ss_shift), (rate_ss_shift + 7),\n\t\t\t\t\t\t\tfat_tab->aux_ht_cnt[rate_ss_shift + 0], fat_tab->aux_ht_cnt[rate_ss_shift + 1],\n\t\t\t\t\t\t\tfat_tab->aux_ht_cnt[rate_ss_shift + 2], fat_tab->aux_ht_cnt[rate_ss_shift + 3],\n\t\t\t\t\t\t\tfat_tab->aux_ht_cnt[rate_ss_shift + 4], fat_tab->aux_ht_cnt[rate_ss_shift + 5],\n\t\t\t\t\t\t\tfat_tab->aux_ht_cnt[rate_ss_shift + 6], fat_tab->aux_ht_cnt[rate_ss_shift + 7]);\n\t\t\t\t\t\t}\n\n\t\t\t\t\t\t/* @3 [EVM statistic] */\n\t\t\t\t\t\t/*@1SS EVM*/\n\t\t\t\t\t\tmain_1ss_evm = (fat_tab->main_evm_cnt[mac_id] != 0) ? (fat_tab->main_evm_sum[mac_id] / fat_tab->main_evm_cnt[mac_id]) : 0;\n\t\t\t\t\t\taux_1ss_evm = (fat_tab->aux_evm_cnt[mac_id] != 0) ? (fat_tab->aux_evm_sum[mac_id] / fat_tab->aux_evm_cnt[mac_id]) : 0;\n\t\t\t\t\t\ttarget_ant_evm_1ss = (main_1ss_evm == aux_1ss_evm) ? (fat_tab->pre_target_ant_enhance) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT);\n\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Cnt = ((%d)), Main1ss_EVM= ((  %d ))\\n\", fat_tab->main_evm_cnt[mac_id], main_1ss_evm);\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Cnt = ((%d)), Aux_1ss_EVM = ((  %d ))\\n\", fat_tab->aux_evm_cnt[mac_id], aux_1ss_evm);\n\n\t\t\t\t\t\t/*@2SS EVM*/\n\t\t\t\t\t\tmain_2ss_evm[0] = (fat_tab->main_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->main_evm_2ss_sum[mac_id][0] / fat_tab->main_evm_2ss_cnt[mac_id]) : 0;\n\t\t\t\t\t\tmain_2ss_evm[1] = (fat_tab->main_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->main_evm_2ss_sum[mac_id][1] / fat_tab->main_evm_2ss_cnt[mac_id]) : 0;\n\t\t\t\t\t\tmain_2ss_evm_sum = main_2ss_evm[0] + main_2ss_evm[1];\n\n\t\t\t\t\t\taux_2ss_evm[0] = (fat_tab->aux_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->aux_evm_2ss_sum[mac_id][0] / fat_tab->aux_evm_2ss_cnt[mac_id]) : 0;\n\t\t\t\t\t\taux_2ss_evm[1] = (fat_tab->aux_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->aux_evm_2ss_sum[mac_id][1] / fat_tab->aux_evm_2ss_cnt[mac_id]) : 0;\n\t\t\t\t\t\taux_2ss_evm_sum = aux_2ss_evm[0] + aux_2ss_evm[1];\n\n\t\t\t\t\t\ttarget_ant_evm_2ss = (main_2ss_evm_sum == aux_2ss_evm_sum) ? (fat_tab->pre_target_ant_enhance) : ((main_2ss_evm_sum >= aux_2ss_evm_sum) ? MAIN_ANT : AUX_ANT);\n\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Cnt = ((%d)), Main2ss_EVM{A,B,Sum} = {%d, %d, %d}\\n\",\n\t\t\t\t\t\t\t  fat_tab->main_evm_2ss_cnt[mac_id], main_2ss_evm[0], main_2ss_evm[1], main_2ss_evm_sum);\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Cnt = ((%d)), Aux_2ss_EVM{A,B,Sum} = {%d, %d, %d}\\n\",\n\t\t\t\t\t\t\t  fat_tab->aux_evm_2ss_cnt[mac_id], aux_2ss_evm[0], aux_2ss_evm[1], aux_2ss_evm_sum);\n\n\t\t\t\t\t\tif ((main_2ss_evm_sum + aux_2ss_evm_sum) != 0) {\n\t\t\t\t\t\t\tdecision_evm_ss = 2;\n\t\t\t\t\t\t\tmain_evm = main_2ss_evm_sum;\n\t\t\t\t\t\t\taux_evm = aux_2ss_evm_sum;\n\t\t\t\t\t\t\tfat_tab->target_ant_evm = target_ant_evm_2ss;\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tdecision_evm_ss = 1;\n\t\t\t\t\t\t\tmain_evm = main_1ss_evm;\n\t\t\t\t\t\t\taux_evm = aux_1ss_evm;\n\t\t\t\t\t\t\tfat_tab->target_ant_evm = target_ant_evm_1ss;\n\t\t\t\t\t\t}\n\n\t\t\t\t\t\tif ((main_evm == 0 || aux_evm == 0))\n\t\t\t\t\t\t\tdiff_EVM = 100;\n\t\t\t\t\t\telse if (main_evm >= aux_evm)\n\t\t\t\t\t\t\tdiff_EVM = main_evm - aux_evm;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tdiff_EVM = aux_evm - main_evm;\n\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"***2.TargetAnt_EVM((%d-ss)) = ((%s))\\n\", decision_evm_ss, (fat_tab->target_ant_evm == MAIN_ANT) ? \"MAIN_ANT\" : \"AUX_ANT\");\n\n\t\t\t\t\t\t//3 [TP statistic]\n\t\t\t\t\t\tmain_tp_avg = (fat_tab->main_tp_cnt != 0) ? (fat_tab->main_tp / fat_tab->main_tp_cnt) : 0;\n\t\t\t\t\t\taux_tp_avg = (fat_tab->aux_tp_cnt != 0) ? (fat_tab->aux_tp / fat_tab->aux_tp_cnt) : 0;\n\t\t\t\t\t\ttp_diff_avg = DIFF_2(main_tp_avg, aux_tp_avg);\n\t\t\t\t\t\tfat_tab->target_ant_tp = (tp_diff_avg < 100) ? (fat_tab->pre_target_ant_enhance) : ((main_tp_avg >= aux_tp_avg) ? MAIN_ANT : AUX_ANT);\n\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Cnt = ((%d)), Main_TP = ((%d))\\n\", fat_tab->main_tp_cnt, main_tp_avg);\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Cnt = ((%d)), Aux_TP = ((%d))\\n\", fat_tab->aux_tp_cnt, aux_tp_avg);\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"***3.TargetAnt_TP = ((%s))\\n\", (fat_tab->target_ant_tp == MAIN_ANT) ? \"MAIN_ANT\" : \"AUX_ANT\");\n\n\t\t\t\t\t\t/*Reset TP Method */\n\t\t\t\t\t\tfat_tab->main_tp = 0;\n\t\t\t\t\t\tfat_tab->aux_tp = 0;\n\t\t\t\t\t\tfat_tab->main_tp_cnt = 0;\n\t\t\t\t\t\tfat_tab->aux_tp_cnt = 0;\n\n\t\t\t\t\t\t/* @2 [ Decision state ] */\n\t\t\t\t\t\t#if 1\n\t\t\t\t\t\tif (main_max_idx == aux_max_idx && ((main_cnt_all + aux_cnt_all) != 0)) {\n\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Decision EVM, main_max_idx = ((MCS%d)), aux_max_idx = ((MCS%d))\\n\", main_max_idx, aux_max_idx);\n\t\t\t\t\t\t\tfat_tab->target_ant_enhance = fat_tab->target_ant_evm;\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Decision TP, main_max_idx = ((MCS%d)), aux_max_idx = ((MCS%d))\\n\", main_max_idx, aux_max_idx);\n\t\t\t\t\t\t\tfat_tab->target_ant_enhance = fat_tab->target_ant_tp;\n\t\t\t\t\t\t}\n\t\t\t\t\t\t#else\n\t\t\t\t\t\tif (fat_tab->target_ant_evm == fat_tab->target_ant_crc32) {\n\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Decision type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\\n\", utility_ratio, diff_EVM);\n\n\t\t\t\t\t\t\tif ((utility_ratio < 2 && force_antenna == false) && diff_EVM <= 30)\n\t\t\t\t\t\t\t\tfat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tfat_tab->target_ant_enhance = fat_tab->target_ant_evm;\n\t\t\t\t\t\t}\n\t\t\t\t\t\t#if 0\n\t\t\t\t\t\telse if ((diff_EVM <= 50 && (utility_ratio > 4 && force_antenna == false)) || (force_antenna == true)) {\n\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Decision type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\\n\", utility_ratio, diff_EVM);\n\t\t\t\t\t\t\tfat_tab->target_ant_enhance = fat_tab->target_ant_crc32;\n\t\t\t\t\t\t}\n\t\t\t\t\t\t#endif\n\t\t\t\t\t\telse if (diff_EVM >= 20) {\n\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Decision type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\\n\", utility_ratio, diff_EVM);\n\t\t\t\t\t\t\tfat_tab->target_ant_enhance = fat_tab->target_ant_evm;\n\t\t\t\t\t\t} else if (utility_ratio >= 6 && force_antenna == false) {\n\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Decision type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\\n\", utility_ratio, diff_EVM);\n\t\t\t\t\t\t\tfat_tab->target_ant_enhance = fat_tab->target_ant_crc32;\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Decision type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\\n\", utility_ratio, diff_EVM);\n\n\t\t\t\t\t\t\tif (force_antenna == true)\n\t\t\t\t\t\t\t\tscore_CRC = 2;\n\t\t\t\t\t\t\telse if (utility_ratio >= 5) /*@>2.5*/\n\t\t\t\t\t\t\t\tscore_CRC = 2;\n\t\t\t\t\t\t\telse if (utility_ratio >= 4) /*@>2*/\n\t\t\t\t\t\t\t\tscore_CRC = 1;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tscore_CRC = 0;\n\n\t\t\t\t\t\t\tif (diff_EVM >= 15)\n\t\t\t\t\t\t\t\tscore_EVM = 3;\n\t\t\t\t\t\t\telse if (diff_EVM >= 10)\n\t\t\t\t\t\t\t\tscore_EVM = 2;\n\t\t\t\t\t\t\telse if (diff_EVM >= 5)\n\t\t\t\t\t\t\t\tscore_EVM = 1;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tscore_EVM = 0;\n\n\t\t\t\t\t\t\tif (score_CRC > score_EVM)\n\t\t\t\t\t\t\t\tfat_tab->target_ant_enhance = fat_tab->target_ant_crc32;\n\t\t\t\t\t\t\telse if (score_CRC < score_EVM)\n\t\t\t\t\t\t\t\tfat_tab->target_ant_enhance = fat_tab->target_ant_evm;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tfat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance;\n\t\t\t\t\t\t}\n\t\t\t\t\t\t#endif\n\t\t\t\t\t\tfat_tab->pre_target_ant_enhance = fat_tab->target_ant_enhance;\n\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"*** 4.TargetAnt_enhance = (( %s ))******\\n\", (fat_tab->target_ant_enhance == MAIN_ANT) ? \"MAIN_ANT\" : \"AUX_ANT\");\n\t\t\t\t\t}\n\t\t\t\t} else { /* RSSI< = evm_rssi_th_low */\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[ <TH_L: escape from > TH_L ]\\n\");\n\t\t\t\t\todm_evm_fast_ant_reset(dm);\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"[escape from> TH_H || evm_method_enable==1]\\n\");\n\t\t\t\todm_evm_fast_ant_reset(dm);\n\t\t\t}\n\t\t} else {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[multi-Client]\\n\");\n\t\t\todm_evm_fast_ant_reset(dm);\n\t\t}\n\t}\n}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid phydm_evm_antdiv_callback(\n\tstruct phydm_timer_list *timer)\n{\n\tvoid *adapter = (void *)timer->Adapter;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\n\t#if DEV_BUS_TYPE == RT_PCI_INTERFACE\n\t#if USE_WORKITEM\n\todm_schedule_work_item(&dm->phydm_evm_antdiv_workitem);\n\t#else\n\t{\n\t\todm_hw_ant_div(dm);\n\t}\n\t#endif\n\t#else\n\todm_schedule_work_item(&dm->phydm_evm_antdiv_workitem);\n\t#endif\n}\n\nvoid phydm_evm_antdiv_workitem_callback(\n\tvoid *context)\n{\n\tvoid *adapter = (void *)context;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\n\todm_hw_ant_div(dm);\n}\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\nvoid phydm_evm_antdiv_callback(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tvoid *padapter = dm->adapter;\n\n\tif (*dm->is_net_closed)\n\t\treturn;\n\tif (dm->support_interface == ODM_ITRF_PCIE) {\n\t\todm_hw_ant_div(dm);\n\t} else {\n\t\t/* @Can't do I/O in timer callback*/\n\t\tphydm_run_in_thread_cmd(dm,\n\t\t\t\t\tphydm_evm_antdiv_workitem_callback,\n\t\t\t\t\tpadapter);\n\t}\n}\n\nvoid phydm_evm_antdiv_workitem_callback(void *context)\n{\n\tvoid *adapter = (void *)context;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->odmpriv;\n\n\todm_hw_ant_div(dm);\n}\n\n#else\nvoid phydm_evm_antdiv_callback(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"******AntDiv_Callback******\\n\");\n\todm_hw_ant_div(dm);\n}\n#endif\n\n#endif\n\nvoid odm_hw_ant_div(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 i, min_max_rssi = 0xFF, ant_div_max_rssi = 0, max_rssi = 0;\n\tu32 main_rssi, aux_rssi, mian_cnt, aux_cnt, local_max_rssi;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tu8 rx_idle_ant = fat_tab->rx_idle_ant, target_ant = 7;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct cmn_sta_info *sta;\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\tstruct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;\n\tu32 TH1 = 500000;\n\tu32 TH2 = 10000000;\n\tu32 ma_rx_temp, degrade_TP_temp, improve_TP_temp;\n\tu8 monitor_rssi_threshold = 30;\n\n\tdm_bdc_table->BF_pass = true;\n\tdm_bdc_table->DIV_pass = true;\n\tdm_bdc_table->is_all_div_sta_idle = true;\n\tdm_bdc_table->is_all_bf_sta_idle = true;\n\tdm_bdc_table->num_bf_tar = 0;\n\tdm_bdc_table->num_div_tar = 0;\n\tdm_bdc_table->num_client = 0;\n#endif\n#endif\n\n\tif (!dm->is_linked) { /* @is_linked==False */\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[No Link!!!]\\n\");\n\n\t\tif (fat_tab->is_become_linked) {\n\t\t\tif (fat_tab->div_path_type == ANT_PATH_A)\n\t\t\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);\n\t\t\telse if (fat_tab->div_path_type == ANT_PATH_B)\n\t\t\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);\n\t\t\telse if (fat_tab->div_path_type == ANT_PATH_AB)\n\t\t\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);\n\t\t\todm_update_rx_idle_ant(dm, MAIN_ANT);\n\t\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);\n\t\t\tdm->antdiv_period = 0;\n\n\t\t\tfat_tab->is_become_linked = dm->is_linked;\n\t\t}\n\t\treturn;\n\t} else {\n\t\tif (!fat_tab->is_become_linked) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[Linked !!!]\\n\");\n\t\t\tif (fat_tab->div_path_type == ANT_PATH_A)\n\t\t\t\todm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);\n\t\t\telse if (fat_tab->div_path_type == ANT_PATH_B)\n\t\t\t\todm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);\n\t\t\telse if (fat_tab->div_path_type == ANT_PATH_AB)\n\t\t\t\todm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);\n\t\t\t#if 0\n\t\t\t/*odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);*/\n\n\t\t\t/* @if(dm->support_ic_type == ODM_RTL8821 ) */\n\t\t\t/* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */\n\t\t\t/* CCK AntDiv function disable */\n\n\t\t\t/* @#if(DM_ODM_SUPPORT_TYPE  == ODM_AP) */\n\t\t\t/* @else if(dm->support_ic_type == ODM_RTL8881A) */\n\t\t\t/* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */\n\t\t\t/* CCK AntDiv function disable */\n\t\t\t/* @#endif */\n\n\t\t\t/* @else if(dm->support_ic_type == ODM_RTL8723B ||*/\n\t\t\t/* @dm->support_ic_type == ODM_RTL8812) */\n\t\t\t/* odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); */\n\t\t\t/* CCK AntDiv function disable */\n\t\t\t#endif\n\n\t\t\tfat_tab->is_become_linked = dm->is_linked;\n\n\t\t\tif (dm->support_ic_type == ODM_RTL8723B &&\n\t\t\t    dm->ant_div_type == CG_TRX_HW_ANTDIV) {\n\t\t\t\todm_set_bb_reg(dm, R_0x930, 0xF0, 8);\n\t\t\t\t/* @DPDT_P = ANTSEL[0] for 8723B AntDiv */\n\t\t\t\todm_set_bb_reg(dm, R_0x930, 0xF, 8);\n\t\t\t\t/* @DPDT_N = ANTSEL[0] */\n\t\t\t}\n\n\t\t\t/* @ BDC Init */\n\t\t\t#ifdef PHYDM_BEAMFORMING_SUPPORT\n\t\t\t#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t\t\todm_bdc_init(dm);\n\t\t\t#endif\n\t\t\t#endif\n\n\t\t\t#ifdef ODM_EVM_ENHANCE_ANTDIV\n\t\t\todm_evm_fast_ant_reset(dm);\n\t\t\t#endif\n\t\t}\n\t}\n\n\tif (!(*fat_tab->p_force_tx_by_desc)) {\n\t\tif (dm->is_one_entry_only)\n\t\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);\n\t\telse\n\t\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);\n\t}\n\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\tif (dm->antdiv_evm_en == 1) {\n\t\todm_evm_enhance_ant_div(dm);\n\t\tif (fat_tab->fat_state_cnt != 0)\n\t\t\treturn;\n\t} else\n\t\todm_evm_fast_ant_reset(dm);\n#endif\n\n/* @2 BDC mode Arbitration */\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\tif (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0)\n\t\todm_bf_ant_div_mode_arbitration(dm);\n#endif\n#endif\n\n\tfor (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {\n\t\tsta = dm->phydm_sta_info[i];\n\t\tif (!is_sta_active(sta)) {\n\t\t\tphydm_antdiv_reset_statistic(dm, i);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* @2 Caculate RSSI per Antenna */\n\t\tif (fat_tab->main_cnt[i] != 0 || fat_tab->aux_cnt[i] != 0) {\n\t\t\tmian_cnt = fat_tab->main_cnt[i];\n\t\t\taux_cnt = fat_tab->aux_cnt[i];\n\t\t\tmain_rssi = (mian_cnt != 0) ?\n\t\t\t\t    (fat_tab->main_sum[i] / mian_cnt) : 0;\n\t\t\taux_rssi = (aux_cnt != 0) ?\n\t\t\t\t   (fat_tab->aux_sum[i] / aux_cnt) : 0;\n\t\t\ttarget_ant = (mian_cnt == aux_cnt) ?\n\t\t\t\t     fat_tab->rx_idle_ant :\n\t\t\t\t     ((mian_cnt >= aux_cnt) ?\n\t\t\t\t     MAIN_ANT : AUX_ANT);\n\t\t\t\t     /*Use counter number for OFDM*/\n\n\t\t} else { /*@CCK only case*/\n\t\t\tmian_cnt = fat_tab->main_cnt_cck[i];\n\t\t\taux_cnt = fat_tab->aux_cnt_cck[i];\n\t\t\tmain_rssi = (mian_cnt != 0) ?\n\t\t\t\t    (fat_tab->main_sum_cck[i] / mian_cnt) : 0;\n\t\t\taux_rssi = (aux_cnt != 0) ?\n\t\t\t\t   (fat_tab->aux_sum_cck[i] / aux_cnt) : 0;\n\t\t\ttarget_ant = (main_rssi == aux_rssi) ?\n\t\t\t\t     fat_tab->rx_idle_ant :\n\t\t\t\t     ((main_rssi >= aux_rssi) ?\n\t\t\t\t     MAIN_ANT : AUX_ANT);\n\t\t\t\t     /*Use RSSI for CCK only case*/\n\t\t}\n\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"*** Client[ %d ] : Main_Cnt = (( %d ))  ,  CCK_Main_Cnt = (( %d )) ,  main_rssi= ((  %d ))\\n\",\n\t\t\t  i, fat_tab->main_cnt[i],\n\t\t\t  fat_tab->main_cnt_cck[i], main_rssi);\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"*** Client[ %d ] : Aux_Cnt   = (( %d ))  , CCK_Aux_Cnt   = (( %d )) ,  aux_rssi = ((  %d ))\\n\",\n\t\t\t  i, fat_tab->aux_cnt[i],\n\t\t\t  fat_tab->aux_cnt_cck[i], aux_rssi);\n\n\t\tlocal_max_rssi = (main_rssi > aux_rssi) ? main_rssi : aux_rssi;\n\t\t/* @ Select max_rssi for DIG */\n\t\tif (local_max_rssi > ant_div_max_rssi && local_max_rssi < 40)\n\t\t\tant_div_max_rssi = local_max_rssi;\n\t\tif (local_max_rssi > max_rssi)\n\t\t\tmax_rssi = local_max_rssi;\n\n\t\t/* @ Select RX Idle Antenna */\n\t\tif (local_max_rssi != 0 && local_max_rssi < min_max_rssi) {\n\t\t\trx_idle_ant = target_ant;\n\t\t\tmin_max_rssi = local_max_rssi;\n\t\t}\n\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\t\tif (dm->antdiv_evm_en == 1) {\n\t\t\tif (fat_tab->target_ant_enhance != 0xFF) {\n\t\t\t\ttarget_ant = fat_tab->target_ant_enhance;\n\t\t\t\trx_idle_ant = fat_tab->target_ant_enhance;\n\t\t\t}\n\t\t}\n#endif\n\n\t\t/* @2 Select TX Antenna */\n\t\tif (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {\n\t\t\t#ifdef PHYDM_BEAMFORMING_SUPPORT\n\t\t\t#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t\t\tif (dm_bdc_table->w_bfee_client[i] == 0)\n\t\t\t#endif\n\t\t\t#endif\n\t\t\t{\n\t\t\t\todm_update_tx_ant(dm, target_ant, i);\n\t\t\t}\n\t\t}\n\n/* @------------------------------------------------------------ */\n\n\t\t#ifdef PHYDM_BEAMFORMING_SUPPORT\n\t\t#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\n\t\tdm_bdc_table->num_client++;\n\n\t\tif (dm_bdc_table->bdc_mode == BDC_MODE_2 || dm_bdc_table->bdc_mode == BDC_MODE_3) {\n\t\t\t/* @2 Byte counter */\n\n\t\t\tma_rx_temp = sta->rx_moving_average_tp; /* RX  TP   ( bit /sec) */\n\n\t\t\tif (dm_bdc_table->BDC_state == bdc_bfer_train_state)\n\t\t\t\tdm_bdc_table->MA_rx_TP_DIV[i] = ma_rx_temp;\n\t\t\telse\n\t\t\t\tdm_bdc_table->MA_rx_TP[i] = ma_rx_temp;\n\n\t\t\tif (ma_rx_temp < TH2 && ma_rx_temp > TH1 && local_max_rssi <= monitor_rssi_threshold) {\n\t\t\t\tif (dm_bdc_table->w_bfer_client[i] == 1) { /* @Bfer_Target */\n\t\t\t\t\tdm_bdc_table->num_bf_tar++;\n\n\t\t\t\t\tif (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) {\n\t\t\t\t\t\timprove_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 9) >> 3; /* @* 1.125 */\n\t\t\t\t\t\tdm_bdc_table->BF_pass = (dm_bdc_table->MA_rx_TP[i] > improve_TP_temp) ? true : false;\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"*** Client[ %d ] :  { MA_rx_TP,improve_TP_temp, MA_rx_TP_DIV,  BF_pass}={ %d,  %d, %d , %d }\\n\", i, dm_bdc_table->MA_rx_TP[i], improve_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->BF_pass);\n\t\t\t\t\t}\n\t\t\t\t} else { /* @DIV_Target */\n\t\t\t\t\tdm_bdc_table->num_div_tar++;\n\n\t\t\t\t\tif (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) {\n\t\t\t\t\t\tdegrade_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 5) >> 3; /* @* 0.625 */\n\t\t\t\t\t\tdm_bdc_table->DIV_pass = (dm_bdc_table->MA_rx_TP[i] > degrade_TP_temp) ? true : false;\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"*** Client[ %d ] :  { MA_rx_TP, degrade_TP_temp, MA_rx_TP_DIV,  DIV_pass}=\\n{ %d,  %d, %d , %d }\\n\", i, dm_bdc_table->MA_rx_TP[i], degrade_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->DIV_pass);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (ma_rx_temp > TH1) {\n\t\t\t\tif (dm_bdc_table->w_bfer_client[i] == 1) /* @Bfer_Target */\n\t\t\t\t\tdm_bdc_table->is_all_bf_sta_idle = false;\n\t\t\t\telse /* @DIV_Target */\n\t\t\t\t\tdm_bdc_table->is_all_div_sta_idle = false;\n\t\t\t}\n\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"*** Client[ %d ] :  { BFmeeCap, BFmerCap}  = { %d , %d }\\n\",\n\t\t\t\t  i, dm_bdc_table->w_bfee_client[i],\n\t\t\t\t  dm_bdc_table->w_bfer_client[i]);\n\n\t\t\tif (dm_bdc_table->BDC_state == bdc_bfer_train_state)\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"*** Client[ %d ] :    MA_rx_TP_DIV = (( %d ))\\n\", i, dm_bdc_table->MA_rx_TP_DIV[i]);\n\n\t\t\telse\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"*** Client[ %d ] :    MA_rx_TP = (( %d ))\\n\", i, dm_bdc_table->MA_rx_TP[i]);\n\t\t}\n\t\t#endif\n\t\t#endif\n\n\t\t#ifdef PHYDM_BEAMFORMING_SUPPORT\n\t\t#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t\tif (dm_bdc_table->bdc_try_flag == 0)\n\t\t#endif\n\t\t#endif\n\t\t{\n\t\t\tphydm_antdiv_reset_statistic(dm, i);\n\t\t}\n\t}\n\n/* @2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) */\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"*** rx_idle_ant = (( %s ))\\n\",\n\t\t  (rx_idle_ant == MAIN_ANT) ? \"MAIN_ANT\" : \"AUX_ANT\");\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\tif (dm_bdc_table->bdc_mode == BDC_MODE_1 || dm_bdc_table->bdc_mode == BDC_MODE_3) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"*** bdc_rx_idle_update_counter = (( %d ))\\n\",\n\t\t\t  dm_bdc_table->bdc_rx_idle_update_counter);\n\n\t\tif (dm_bdc_table->bdc_rx_idle_update_counter == 1) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"***Update RxIdle Antenna!!!\\n\");\n\t\t\tdm_bdc_table->bdc_rx_idle_update_counter = 30;\n\t\t\todm_update_rx_idle_ant(dm, rx_idle_ant);\n\t\t} else {\n\t\t\tdm_bdc_table->bdc_rx_idle_update_counter--;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"***NOT update RxIdle Antenna because of BF  ( need to fix TX-ant)\\n\");\n\t\t}\n\t} else\n#endif\n#endif\n\t\todm_update_rx_idle_ant(dm, rx_idle_ant);\n#else\n\n\todm_update_rx_idle_ant(dm, rx_idle_ant);\n\n#endif /* @#if(DM_ODM_SUPPORT_TYPE  == ODM_AP) */\n\n/* @2 BDC Main Algorithm */\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\tif (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0)\n\t\todm_bd_ccoex_bfee_rx_div_arbitration(dm);\n\n\tdm_bdc_table->num_txbfee_client = 0;\n\tdm_bdc_table->num_txbfer_client = 0;\n#endif\n#endif\n\n\tif (ant_div_max_rssi == 0)\n\t\tdig_t->ant_div_rssi_max = dm->rssi_min;\n\telse\n\t\tdig_t->ant_div_rssi_max = ant_div_max_rssi;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"***AntDiv End***\\n\\n\");\n}\n\n#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\nvoid odm_s0s1_sw_ant_div_reset(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct sw_antenna_switch *swat_tab = &dm->dm_swat_table;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\tfat_tab->is_become_linked = false;\n\tswat_tab->try_flag = SWAW_STEP_INIT;\n\tswat_tab->double_chk_flag = 0;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"%s: fat_tab->is_become_linked = %d\\n\",\n\t\t  __func__, fat_tab->is_become_linked);\n}\n\nvoid phydm_sw_antdiv_train_time(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct sw_antenna_switch *swat_tab = &dm->dm_swat_table;\n\tu8 high_traffic_train_time_u = 0x32, high_traffic_train_time_l = 0;\n\tu8 low_traffic_train_time_u = 200, low_traffic_train_time_l = 0;\n\tu8 train_time_temp;\n\n\tif (dm->traffic_load == TRAFFIC_HIGH) {\n\t\ttrain_time_temp = swat_tab->train_time;\n\n\t\tif (swat_tab->train_time_flag == 3) {\n\t\t\thigh_traffic_train_time_l = 0xa;\n\n\t\t\tif (train_time_temp <= 16)\n\t\t\t\ttrain_time_temp = high_traffic_train_time_l;\n\t\t\telse\n\t\t\t\ttrain_time_temp -= 16;\n\n\t\t} else if (swat_tab->train_time_flag == 2) {\n\t\t\ttrain_time_temp -= 8;\n\t\t\thigh_traffic_train_time_l = 0xf;\n\t\t} else if (swat_tab->train_time_flag == 1) {\n\t\t\ttrain_time_temp -= 4;\n\t\t\thigh_traffic_train_time_l = 0x1e;\n\t\t} else if (swat_tab->train_time_flag == 0) {\n\t\t\ttrain_time_temp += 8;\n\t\t\thigh_traffic_train_time_l = 0x28;\n\t\t}\n\n\t\tif (dm->support_ic_type == ODM_RTL8188F) {\n\t\t\tif (dm->support_interface == ODM_ITRF_SDIO)\n\t\t\t\thigh_traffic_train_time_l += 0xa;\n\t\t}\n\n\t\t/* @-- */\n\t\tif (train_time_temp > high_traffic_train_time_u)\n\t\t\ttrain_time_temp = high_traffic_train_time_u;\n\n\t\telse if (train_time_temp < high_traffic_train_time_l)\n\t\t\ttrain_time_temp = high_traffic_train_time_l;\n\n\t\tswat_tab->train_time = train_time_temp; /*@10ms~200ms*/\n\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"train_time_flag=((%d)), train_time=((%d))\\n\",\n\t\t\t  swat_tab->train_time_flag,\n\t\t\t  swat_tab->train_time);\n\n\t} else if ((dm->traffic_load == TRAFFIC_MID) ||\n\t\t   (dm->traffic_load == TRAFFIC_LOW)) {\n\t\ttrain_time_temp = swat_tab->train_time;\n\n\t\tif (swat_tab->train_time_flag == 3) {\n\t\t\tlow_traffic_train_time_l = 10;\n\t\t\tif (train_time_temp < 50)\n\t\t\t\ttrain_time_temp = low_traffic_train_time_l;\n\t\t\telse\n\t\t\t\ttrain_time_temp -= 50;\n\t\t} else if (swat_tab->train_time_flag == 2) {\n\t\t\ttrain_time_temp -= 30;\n\t\t\tlow_traffic_train_time_l = 36;\n\t\t} else if (swat_tab->train_time_flag == 1) {\n\t\t\ttrain_time_temp -= 10;\n\t\t\tlow_traffic_train_time_l = 40;\n\t\t} else {\n\t\t\ttrain_time_temp += 10;\n\t\t\tlow_traffic_train_time_l = 50;\n\t\t}\n\n\t\tif (dm->support_ic_type == ODM_RTL8188F) {\n\t\t\tif (dm->support_interface == ODM_ITRF_SDIO)\n\t\t\t\tlow_traffic_train_time_l += 10;\n\t\t}\n\n\t\t/* @-- */\n\t\tif (train_time_temp >= low_traffic_train_time_u)\n\t\t\ttrain_time_temp = low_traffic_train_time_u;\n\n\t\telse if (train_time_temp <= low_traffic_train_time_l)\n\t\t\ttrain_time_temp = low_traffic_train_time_l;\n\n\t\tswat_tab->train_time = train_time_temp; /*@10ms~200ms*/\n\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"train_time_flag=((%d)) , train_time=((%d))\\n\",\n\t\t\t  swat_tab->train_time_flag, swat_tab->train_time);\n\n\t} else {\n\t\tswat_tab->train_time = 0xc8; /*@200ms*/\n\t}\n}\n\nvoid phydm_sw_antdiv_decision(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct sw_antenna_switch *swat_tab = &dm->dm_swat_table;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tu32 i, min_max_rssi = 0xFF, local_max_rssi, local_min_rssi;\n\tu32 main_rssi, aux_rssi;\n\tu8 rx_idle_ant = swat_tab->pre_ant;\n\tu8 target_ant = swat_tab->pre_ant, next_ant = 0;\n\tstruct cmn_sta_info *entry = NULL;\n\tu32 main_cnt = 0, aux_cnt = 0, main_sum = 0, aux_sum = 0;\n\tu32 main_ctrl_cnt = 0, aux_ctrl_cnt = 0;\n\tboolean is_by_ctrl_frame = false;\n\tboolean cond_23d_main, cond_23d_aux;\n\tu64 pkt_cnt_total = 0;\n\n\tfor (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {\n\t\tentry = dm->phydm_sta_info[i];\n\t\tif (!is_sta_active(entry)) {\n\t\t\tphydm_antdiv_reset_statistic(dm, i);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* @2 Caculate RSSI per Antenna */\n\t\tif (fat_tab->main_cnt[i] != 0 || fat_tab->aux_cnt[i] != 0) {\n\t\t\tmain_cnt = (u32)fat_tab->main_cnt[i];\n\t\t\taux_cnt = (u32)fat_tab->aux_cnt[i];\n\t\t\tmain_rssi = (main_cnt != 0) ?\n\t\t\t\t    (fat_tab->main_sum[i] / main_cnt) : 0;\n\t\t\taux_rssi = (aux_cnt != 0) ?\n\t\t\t\t   (fat_tab->aux_sum[i] / aux_cnt) : 0;\n\t\t\tif (dm->support_ic_type == ODM_RTL8723D) {\n\t\t\t\tcond_23d_main = (aux_cnt > main_cnt) &&\n\t\t\t\t\t\t((main_rssi - aux_rssi < 5) ||\n\t\t\t\t\t\t(aux_rssi > main_rssi));\n\t\t\t\tcond_23d_aux = (main_cnt > aux_cnt) &&\n\t\t\t\t\t       ((aux_rssi - main_rssi < 5) ||\n\t\t\t\t\t       (main_rssi > aux_rssi));\n\t\t\t\tif (swat_tab->pre_ant == MAIN_ANT) {\n\t\t\t\t\tif (main_cnt == 0)\n\t\t\t\t\t\ttarget_ant = (aux_cnt != 0) ?\n\t\t\t\t\t\t\t     AUX_ANT :\n\t\t\t\t\t\t\t     swat_tab->pre_ant;\n\t\t\t\t\telse\n\t\t\t\t\t\ttarget_ant = cond_23d_main ?\n\t\t\t\t\t\t\t     AUX_ANT :\n\t\t\t\t\t\t\t     swat_tab->pre_ant;\n\t\t\t\t} else {\n\t\t\t\t\tif (aux_cnt == 0)\n\t\t\t\t\t\ttarget_ant = (main_cnt != 0) ?\n\t\t\t\t\t\t\t     MAIN_ANT :\n\t\t\t\t\t\t\t     swat_tab->pre_ant;\n\t\t\t\t\telse\n\t\t\t\t\t\ttarget_ant = cond_23d_aux ?\n\t\t\t\t\t\t\t     MAIN_ANT :\n\t\t\t\t\t\t\t     swat_tab->pre_ant;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif (swat_tab->pre_ant == MAIN_ANT) {\n\t\t\t\t\ttarget_ant = (aux_rssi > main_rssi) ?\n\t\t\t\t\t\t     AUX_ANT :\n\t\t\t\t\t\t     swat_tab->pre_ant;\n\t\t\t\t} else if (swat_tab->pre_ant == AUX_ANT) {\n\t\t\t\t\ttarget_ant = (main_rssi > aux_rssi) ?\n\t\t\t\t\t\t     MAIN_ANT :\n\t\t\t\t\t\t     swat_tab->pre_ant;\n\t\t\t\t}\n\t\t\t}\n\t\t} else { /*@CCK only case*/\n\t\t\tmain_cnt = fat_tab->main_cnt_cck[i];\n\t\t\taux_cnt = fat_tab->aux_cnt_cck[i];\n\t\t\tmain_rssi = (main_cnt != 0) ?\n\t\t\t\t    (fat_tab->main_sum_cck[i] / main_cnt) : 0;\n\t\t\taux_rssi = (aux_cnt != 0) ?\n\t\t\t\t   (fat_tab->aux_sum_cck[i] / aux_cnt) : 0;\n\t\t\ttarget_ant = (main_rssi == aux_rssi) ?\n\t\t\t\t     swat_tab->pre_ant :\n\t\t\t\t     ((main_rssi >= aux_rssi) ?\n\t\t\t\t     MAIN_ANT : AUX_ANT);\n\t\t\t\t     /*Use RSSI for CCK only case*/\n\t\t}\n\t\tlocal_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi;\n\t\tlocal_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi;\n\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"***  CCK_counter_main = (( %d ))  , CCK_counter_aux= ((  %d ))\\n\",\n\t\t\t  fat_tab->main_cnt_cck[i], fat_tab->aux_cnt_cck[i]);\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"***  OFDM_counter_main = (( %d ))  , OFDM_counter_aux= ((  %d ))\\n\",\n\t\t\t  fat_tab->main_cnt[i], fat_tab->aux_cnt[i]);\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"***  main_Cnt = (( %d ))  , aux_Cnt   = (( %d ))\\n\",\n\t\t\t  main_cnt, aux_cnt);\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"***  main_rssi= ((  %d )) , aux_rssi = ((  %d ))\\n\",\n\t\t\t  main_rssi, aux_rssi);\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"*** MAC ID:[ %d ] , target_ant = (( %s ))\\n\", i,\n\t\t\t  (target_ant == MAIN_ANT) ? \"MAIN_ANT\" : \"AUX_ANT\");\n\n\t\t/* @2 Select RX Idle Antenna */\n\n\t\tif (local_max_rssi != 0 && local_max_rssi < min_max_rssi) {\n\t\t\trx_idle_ant = target_ant;\n\t\t\tmin_max_rssi = local_max_rssi;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"*** local_max_rssi-local_min_rssi = ((%d))\\n\",\n\t\t\t\t  (local_max_rssi - local_min_rssi));\n\n\t\t\tif ((local_max_rssi - local_min_rssi) > 8) {\n\t\t\t\tif (local_min_rssi != 0) {\n\t\t\t\t\tswat_tab->train_time_flag = 3;\n\t\t\t\t} else {\n\t\t\t\t\tif (min_max_rssi > RSSI_CHECK_THRESHOLD)\n\t\t\t\t\t\tswat_tab->train_time_flag = 0;\n\t\t\t\t\telse\n\t\t\t\t\t\tswat_tab->train_time_flag = 3;\n\t\t\t\t}\n\t\t\t} else if ((local_max_rssi - local_min_rssi) > 5) {\n\t\t\t\tswat_tab->train_time_flag = 2;\n\t\t\t} else if ((local_max_rssi - local_min_rssi) > 2) {\n\t\t\t\tswat_tab->train_time_flag = 1;\n\t\t\t} else {\n\t\t\t\tswat_tab->train_time_flag = 0;\n\t\t\t}\n\t\t}\n\n\t\t/* @2 Select TX Antenna */\n\t\tif (target_ant == MAIN_ANT)\n\t\t\tfat_tab->antsel_a[i] = ANT1_2G;\n\t\telse\n\t\t\tfat_tab->antsel_a[i] = ANT2_2G;\n\n\t\tphydm_antdiv_reset_statistic(dm, i);\n\t\tpkt_cnt_total += (main_cnt + aux_cnt);\n\t}\n\n\tif (swat_tab->is_sw_ant_div_by_ctrl_frame) {\n\t\todm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_DETERMINE);\n\t\tis_by_ctrl_frame = true;\n\t}\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"Control frame packet counter = %d, data frame packet counter = %llu\\n\",\n\t\t  swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame, pkt_cnt_total);\n\n\tif (min_max_rssi == 0xff || ((pkt_cnt_total <\n\t    (swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame >> 1)) &&\n\t    dm->phy_dbg_info.num_qry_beacon_pkt < 2)) {\n\t\tmin_max_rssi = 0;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"Check RSSI of control frame because min_max_rssi == 0xff\\n\");\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"is_by_ctrl_frame = %d\\n\",\n\t\t\t  is_by_ctrl_frame);\n\n\t\tif (is_by_ctrl_frame) {\n\t\t\tmain_ctrl_cnt = fat_tab->main_ctrl_cnt;\n\t\t\taux_ctrl_cnt = fat_tab->aux_ctrl_cnt;\n\t\t\tmain_rssi = (main_ctrl_cnt != 0) ?\n\t\t\t\t    (fat_tab->main_ctrl_sum / main_ctrl_cnt) :\n\t\t\t\t    0;\n\t\t\taux_rssi = (aux_ctrl_cnt != 0) ?\n\t\t\t\t   (fat_tab->aux_ctrl_sum / aux_ctrl_cnt) : 0;\n\n\t\t\tif (main_ctrl_cnt <= 1 &&\n\t\t\t    fat_tab->cck_ctrl_frame_cnt_main >= 1)\n\t\t\t\tmain_rssi = 0;\n\n\t\t\tif (aux_ctrl_cnt <= 1 &&\n\t\t\t    fat_tab->cck_ctrl_frame_cnt_aux >= 1)\n\t\t\t\taux_rssi = 0;\n\n\t\t\tif (main_rssi != 0 || aux_rssi != 0) {\n\t\t\t\trx_idle_ant = (main_rssi == aux_rssi) ?\n\t\t\t\t\t      swat_tab->pre_ant :\n\t\t\t\t\t      ((main_rssi >= aux_rssi) ?\n\t\t\t\t\t      MAIN_ANT : AUX_ANT);\n\t\t\t\tlocal_max_rssi = (main_rssi >= aux_rssi) ?\n\t\t\t\t\t\t main_rssi : aux_rssi;\n\t\t\t\tlocal_min_rssi = (main_rssi >= aux_rssi) ?\n\t\t\t\t\t\t aux_rssi : main_rssi;\n\n\t\t\t\tif ((local_max_rssi - local_min_rssi) > 8)\n\t\t\t\t\tswat_tab->train_time_flag = 3;\n\t\t\t\telse if ((local_max_rssi - local_min_rssi) > 5)\n\t\t\t\t\tswat_tab->train_time_flag = 2;\n\t\t\t\telse if ((local_max_rssi - local_min_rssi) > 2)\n\t\t\t\t\tswat_tab->train_time_flag = 1;\n\t\t\t\telse\n\t\t\t\t\tswat_tab->train_time_flag = 0;\n\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"Control frame: main_rssi = %d, aux_rssi = %d\\n\",\n\t\t\t\t\t  main_rssi, aux_rssi);\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"rx_idle_ant decided by control frame = %s\\n\",\n\t\t\t\t\t  (rx_idle_ant == MAIN_ANT ?\n\t\t\t\t\t  \"MAIN\" : \"AUX\"));\n\t\t\t}\n\t\t}\n\t}\n\n\tfat_tab->min_max_rssi = min_max_rssi;\n\tswat_tab->try_flag = SWAW_STEP_PEEK;\n\n\tif (swat_tab->double_chk_flag == 1) {\n\t\tswat_tab->double_chk_flag = 0;\n\n\t\tif (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \" [Double check] min_max_rssi ((%d)) > %d again!!\\n\",\n\t\t\t\t  fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD);\n\n\t\t\todm_update_rx_idle_ant(dm, rx_idle_ant);\n\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[reset try_flag = 0] Training accomplished !!!]\\n\\n\\n\");\n\t\t} else {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \" [Double check] min_max_rssi ((%d)) <= %d !!\\n\",\n\t\t\t\t  fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD);\n\n\t\t\tnext_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ?\n\t\t\t\t   AUX_ANT : MAIN_ANT;\n\t\t\tswat_tab->try_flag = SWAW_STEP_PEEK;\n\t\t\tswat_tab->reset_idx = RSSI_CHECK_RESET_PERIOD;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[set try_flag=0]  Normal state:  Need to tryg again!!\\n\\n\\n\");\n\t\t}\n\t} else {\n\t\tif (fat_tab->min_max_rssi < RSSI_CHECK_THRESHOLD)\n\t\t\tswat_tab->reset_idx = RSSI_CHECK_RESET_PERIOD;\n\n\t\tswat_tab->pre_ant = rx_idle_ant;\n\t\todm_update_rx_idle_ant(dm, rx_idle_ant);\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[reset try_flag = 0] Training accomplished !!!]\\n\\n\\n\");\n\t}\n}\n\nvoid odm_s0s1_sw_ant_div(void *dm_void, u8 step)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct sw_antenna_switch *swat_tab = &dm->dm_swat_table;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tu32 value32;\n\tu8 next_ant = 0;\n\n\tif (!dm->is_linked) { /* @is_linked==False */\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[No Link!!!]\\n\");\n\t\tif (fat_tab->is_become_linked == true) {\n\t\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);\n\t\t\tif (dm->support_ic_type == ODM_RTL8723B) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"Set REG 948[9:6]=0x0\\n\");\n\t\t\t\todm_set_bb_reg(dm, R_0x948, 0x3c0, 0x0);\n\t\t\t}\n\t\t\tfat_tab->is_become_linked = dm->is_linked;\n\t\t}\n\t\treturn;\n\t} else {\n\t\tif (fat_tab->is_become_linked == false) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[Linked !!!]\\n\");\n\n\t\t\tif (dm->support_ic_type == ODM_RTL8723B) {\n\t\t\t\tvalue32 = odm_get_bb_reg(dm, R_0x864, 0x38);\n\n#if (RTL8723B_SUPPORT == 1)\n\t\t\t\tif (value32 == 0x0)\n\t\t\t\t\todm_update_rx_idle_ant_8723b(dm,\n\t\t\t\t\t\t\t\t     MAIN_ANT,\n\t\t\t\t\t\t\t\t     ANT1_2G,\n\t\t\t\t\t\t\t\t     ANT2_2G);\n\t\t\t\telse if (value32 == 0x1)\n\t\t\t\t\todm_update_rx_idle_ant_8723b(dm,\n\t\t\t\t\t\t\t\t     AUX_ANT,\n\t\t\t\t\t\t\t\t     ANT2_2G,\n\t\t\t\t\t\t\t\t     ANT1_2G);\n#endif\n\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"8723B: First link! Force antenna to  %s\\n\",\n\t\t\t\t\t  (value32 == 0x0 ? \"MAIN\" : \"AUX\"));\n\t\t\t}\n\n\t\t\tif (dm->support_ic_type == ODM_RTL8723D) {\n\t\t\t\tvalue32 = odm_get_bb_reg(dm, R_0x864, 0x38);\n#if (RTL8723D_SUPPORT == 1)\n\t\t\t\tif (value32 == 0x0)\n\t\t\t\t\todm_update_rx_idle_ant_8723d(dm,\n\t\t\t\t\t\t\t\t     MAIN_ANT,\n\t\t\t\t\t\t\t\t     ANT1_2G,\n\t\t\t\t\t\t\t\t     ANT2_2G);\n\t\t\t\telse if (value32 == 0x1)\n\t\t\t\t\todm_update_rx_idle_ant_8723d(dm,\n\t\t\t\t\t\t\t\t     AUX_ANT,\n\t\t\t\t\t\t\t\t     ANT2_2G,\n\t\t\t\t\t\t\t\t     ANT1_2G);\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"8723D: First link! Force antenna to  %s\\n\",\n\t\t\t\t\t  (value32 == 0x0 ? \"MAIN\" : \"AUX\"));\n#endif\n\t\t\t}\n\t\t\tfat_tab->is_become_linked = dm->is_linked;\n\t\t}\n\t}\n\n\tif (!(*fat_tab->p_force_tx_by_desc)) {\n\t\tif (dm->is_one_entry_only == true)\n\t\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);\n\t\telse\n\t\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);\n\t}\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[%d] { try_flag=(( %d )), step=(( %d )), double_chk_flag = (( %d )) }\\n\",\n\t\t  __LINE__, swat_tab->try_flag, step,\n\t\t  swat_tab->double_chk_flag);\n\n\t/* @ Handling step mismatch condition. */\n\t/* @ Peak step is not finished at last time. */\n\t/* @ Recover the variable and check again. */\n\tif (step != swat_tab->try_flag) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[step != try_flag]    Need to Reset After Link\\n\");\n\t\todm_sw_ant_div_rest_after_link(dm);\n\t}\n\n\tif (swat_tab->try_flag == SWAW_STEP_INIT) {\n\t\tswat_tab->try_flag = SWAW_STEP_PEEK;\n\t\tswat_tab->train_time_flag = 0;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[set try_flag = 0]  Prepare for peek!\\n\\n\");\n\t\treturn;\n\n\t} else {\n\t\t/* @1 Normal state (Begin Trying) */\n\t\tif (swat_tab->try_flag == SWAW_STEP_PEEK) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), traffic_load = (%d))\\n\",\n\t\t\t\t  dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt,\n\t\t\t\t  dm->traffic_load);\n\t\t\tphydm_sw_antdiv_train_time(dm);\n\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"Current min_max_rssi is ((%d))\\n\",\n\t\t\t\t  fat_tab->min_max_rssi);\n\n\t\t\t/* @---reset index--- */\n\t\t\tif (swat_tab->reset_idx >= RSSI_CHECK_RESET_PERIOD) {\n\t\t\t\tfat_tab->min_max_rssi = 0;\n\t\t\t\tswat_tab->reset_idx = 0;\n\t\t\t}\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"reset_idx = (( %d ))\\n\",\n\t\t\t\t  swat_tab->reset_idx);\n\n\t\t\tswat_tab->reset_idx++;\n\n\t\t\t/* @---double check flag--- */\n\t\t\tif (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD &&\n\t\t\t    swat_tab->double_chk_flag == 0) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \" min_max_rssi is ((%d)), and > %d\\n\",\n\t\t\t\t\t  fat_tab->min_max_rssi,\n\t\t\t\t\t  RSSI_CHECK_THRESHOLD);\n\n\t\t\t\tswat_tab->double_chk_flag = 1;\n\t\t\t\tswat_tab->try_flag = SWAW_STEP_DETERMINE;\n\t\t\t\tswat_tab->rssi_trying = 0;\n\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"Test the current ant for (( %d )) ms again\\n\",\n\t\t\t\t\t  swat_tab->train_time);\n\t\t\t\todm_update_rx_idle_ant(dm,\n\t\t\t\t\t\t       fat_tab->rx_idle_ant);\n\t\t\t\todm_set_timer(dm, &swat_tab->sw_antdiv_timer,\n\t\t\t\t\t      swat_tab->train_time); /*@ms*/\n\t\t\t\treturn;\n\t\t\t}\n\n\t\t\tnext_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ?\n\t\t\t\t   AUX_ANT : MAIN_ANT;\n\n\t\t\tswat_tab->try_flag = SWAW_STEP_DETERMINE;\n\n\t\t\tif (swat_tab->reset_idx <= 1)\n\t\t\t\tswat_tab->rssi_trying = 2;\n\t\t\telse\n\t\t\t\tswat_tab->rssi_trying = 1;\n\n\t\t\todm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_PEEK);\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[set try_flag=1]  Normal state:  Begin Trying!!\\n\");\n\n\t\t} else if ((swat_tab->try_flag == SWAW_STEP_DETERMINE) &&\n\t\t\t   (swat_tab->double_chk_flag == 0)) {\n\t\t\tnext_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ?\n\t\t\t\t   AUX_ANT : MAIN_ANT;\n\t\t\tswat_tab->rssi_trying--;\n\t\t}\n\n\t\t/* @1 Decision state */\n\t\tif (swat_tab->try_flag == SWAW_STEP_DETERMINE &&\n\t\t    swat_tab->rssi_trying == 0) {\n\t\t\tphydm_sw_antdiv_decision(dm);\n\t\t\treturn;\n\t\t}\n\t}\n\n\t/* @1 4.Change TRX antenna */\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"rssi_trying = (( %d )),    ant: (( %s )) >>> (( %s ))\\n\",\n\t\t  swat_tab->rssi_trying,\n\t\t  (fat_tab->rx_idle_ant == MAIN_ANT ? \"MAIN\" : \"AUX\"),\n\t\t  (next_ant == MAIN_ANT ? \"MAIN\" : \"AUX\"));\n\n\todm_update_rx_idle_ant(dm, next_ant);\n\n\t/* @1 5.Reset Statistics */\n\n\tfat_tab->rx_idle_ant = next_ant;\n\n\tif (dm->support_ic_type == ODM_RTL8723D) {\n\t\tif (fat_tab->rx_idle_ant == MAIN_ANT) {\n\t\t\tfat_tab->main_sum[0] = 0;\n\t\t\tfat_tab->main_cnt[0] = 0;\n\t\t\tfat_tab->main_sum_cck[0] = 0;\n\t\t\tfat_tab->main_cnt_cck[0] = 0;\n\t\t} else {\n\t\t\tfat_tab->aux_sum[0] = 0;\n\t\t\tfat_tab->aux_cnt[0] = 0;\n\t\t\tfat_tab->aux_sum_cck[0] = 0;\n\t\t\tfat_tab->aux_cnt_cck[0] = 0;\n\t\t}\n\t}\n\n\tif (dm->support_ic_type == ODM_RTL8188F) {\n\t\tif (dm->support_interface == ODM_ITRF_SDIO) {\n\t\t\tODM_delay_us(200);\n\n\t\t\tif (fat_tab->rx_idle_ant == MAIN_ANT) {\n\t\t\t\tfat_tab->main_sum[0] = 0;\n\t\t\t\tfat_tab->main_cnt[0] = 0;\n\t\t\t\tfat_tab->main_sum_cck[0] = 0;\n\t\t\t\tfat_tab->main_cnt_cck[0] = 0;\n\t\t\t} else {\n\t\t\t\tfat_tab->aux_sum[0] = 0;\n\t\t\t\tfat_tab->aux_cnt[0] = 0;\n\t\t\t\tfat_tab->aux_sum_cck[0] = 0;\n\t\t\t\tfat_tab->aux_cnt_cck[0] = 0;\n\t\t\t}\n\t\t}\n\t}\n\t/* @1 6.Set next timer   (Trying state) */\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \" Test ((%s)) ant for (( %d )) ms\\n\",\n\t\t  (next_ant == MAIN_ANT ? \"MAIN\" : \"AUX\"),\n\t\t  swat_tab->train_time);\n\todm_set_timer(dm, &swat_tab->sw_antdiv_timer, swat_tab->train_time);\n\t\t\t\t\t\t\t\t/*@ms*/\n}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid odm_sw_antdiv_callback(struct phydm_timer_list *timer)\n{\n\tvoid *adapter = (void *)timer->Adapter;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct sw_antenna_switch *swat_tab = &hal_data->DM_OutSrc.dm_swat_table;\n\n#if DEV_BUS_TYPE == RT_PCI_INTERFACE\n#if USE_WORKITEM\n\todm_schedule_work_item(&swat_tab->phydm_sw_antenna_switch_workitem);\n#else\n\t{\n#if 0\n\t\t/* @dbg_print(\"SW_antdiv_Callback\"); */\n#endif\n\t\todm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE);\n\t}\n#endif\n#else\n\todm_schedule_work_item(&swat_tab->phydm_sw_antenna_switch_workitem);\n#endif\n}\n\nvoid odm_sw_antdiv_workitem_callback(void *context)\n{\n\tvoid *adapter = (void *)context;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\n#if 0\n\t/* @dbg_print(\"SW_antdiv_Workitem_Callback\"); */\n#endif\n\todm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE);\n}\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\nvoid odm_sw_antdiv_workitem_callback(void *context)\n{\n\tvoid *\n\t\tadapter = (void *)context;\n\tHAL_DATA_TYPE\n\t*hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\n#if 0\n\t/*@dbg_print(\"SW_antdiv_Workitem_Callback\");*/\n#endif\n\todm_s0s1_sw_ant_div(&hal_data->odmpriv, SWAW_STEP_DETERMINE);\n}\n\nvoid odm_sw_antdiv_callback(void *function_context)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)function_context;\n\tvoid *padapter = dm->adapter;\n\tif (*dm->is_net_closed == true)\n\t\treturn;\n\n#if 0 /* @Can't do I/O in timer callback*/\n\todm_s0s1_sw_ant_div(dm, SWAW_STEP_DETERMINE);\n#else\n\trtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback,\n\t\t\t      padapter);\n#endif\n}\n\n#endif\n\nvoid odm_s0s1_sw_ant_div_by_ctrl_frame(void *dm_void, u8 step)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct sw_antenna_switch *swat_tab = &dm->dm_swat_table;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\tswitch (step) {\n\tcase SWAW_STEP_PEEK:\n\t\tswat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame = 0;\n\t\tswat_tab->is_sw_ant_div_by_ctrl_frame = true;\n\t\tfat_tab->main_ctrl_cnt = 0;\n\t\tfat_tab->aux_ctrl_cnt = 0;\n\t\tfat_tab->main_ctrl_sum = 0;\n\t\tfat_tab->aux_ctrl_sum = 0;\n\t\tfat_tab->cck_ctrl_frame_cnt_main = 0;\n\t\tfat_tab->cck_ctrl_frame_cnt_aux = 0;\n\t\tfat_tab->ofdm_ctrl_frame_cnt_main = 0;\n\t\tfat_tab->ofdm_ctrl_frame_cnt_aux = 0;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\\n\");\n\t\tbreak;\n\tcase SWAW_STEP_DETERMINE:\n\t\tswat_tab->is_sw_ant_div_by_ctrl_frame = false;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"odm_S0S1_SwAntDivForAPMode(): Stop peek\\n\");\n\t\tbreak;\n\tdefault:\n\t\tswat_tab->is_sw_ant_div_by_ctrl_frame = false;\n\t\tbreak;\n\t}\n}\n\nvoid odm_antsel_statistics_ctrl(void *dm_void, u8 antsel_tr_mux,\n\t\t\t\tu32 rx_pwdb_all)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\tif (antsel_tr_mux == ANT1_2G) {\n\t\tfat_tab->main_ctrl_sum += rx_pwdb_all;\n\t\tfat_tab->main_ctrl_cnt++;\n\t} else {\n\t\tfat_tab->aux_ctrl_sum += rx_pwdb_all;\n\t\tfat_tab->aux_ctrl_cnt++;\n\t}\n}\n\nvoid odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void *dm_void,\n\t\t\t\t\t\t    void *phy_info_void,\n\t\t\t\t\t\t    void *pkt_info_void\n\t/*\tstruct phydm_phyinfo_struct*\t\tphy_info, */\n\t/*\tstruct phydm_perpkt_info_struct*\t\tpktinfo */\n\t)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_phyinfo_struct *phy_info = NULL;\n\tstruct phydm_perpkt_info_struct *pktinfo = NULL;\n\tstruct sw_antenna_switch *swat_tab = &dm->dm_swat_table;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tu8 rssi_cck;\n\n\tphy_info = (struct phydm_phyinfo_struct *)phy_info_void;\n\tpktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;\n\n\tif (!(dm->support_ability & ODM_BB_ANT_DIV))\n\t\treturn;\n\n\tif (dm->ant_div_type != S0S1_SW_ANTDIV)\n\t\treturn;\n\n\t/* @In try state */\n\tif (!swat_tab->is_sw_ant_div_by_ctrl_frame)\n\t\treturn;\n\n\t/* No HW error and match receiver address */\n\tif (!pktinfo->is_to_self)\n\t\treturn;\n\n\tswat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame++;\n\n\tif (pktinfo->is_cck_rate) {\n\t\trssi_cck = phy_info->rx_mimo_signal_strength[RF_PATH_A];\n\t\tfat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ?\n\t\t\t\t\t    ANT1_2G : ANT2_2G;\n\n\t\tif (fat_tab->antsel_rx_keep_0 == ANT1_2G)\n\t\t\tfat_tab->cck_ctrl_frame_cnt_main++;\n\t\telse\n\t\t\tfat_tab->cck_ctrl_frame_cnt_aux++;\n\n\t\todm_antsel_statistics_ctrl(dm, fat_tab->antsel_rx_keep_0,\n\t\t\t\t\t   rssi_cck);\n\t} else {\n\t\tfat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ?\n\t\t\t\t\t    ANT1_2G : ANT2_2G;\n\n\t\tif (fat_tab->antsel_rx_keep_0 == ANT1_2G)\n\t\t\tfat_tab->ofdm_ctrl_frame_cnt_main++;\n\t\telse\n\t\t\tfat_tab->ofdm_ctrl_frame_cnt_aux++;\n\n\t\todm_antsel_statistics_ctrl(dm, fat_tab->antsel_rx_keep_0,\n\t\t\t\t\t   phy_info->rx_pwdb_all);\n\t}\n}\n\n#endif /* @#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) */\n\nvoid odm_set_next_mac_addr_target(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tstruct cmn_sta_info *entry;\n\tu32 value32, i;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"%s ==>\\n\", __func__);\n\n\tif (dm->is_linked) {\n\t\tfor (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {\n\t\t\tif ((fat_tab->train_idx + 1) == ODM_ASSOCIATE_ENTRY_NUM)\n\t\t\t\tfat_tab->train_idx = 0;\n\t\t\telse\n\t\t\t\tfat_tab->train_idx++;\n\n\t\t\tentry = dm->phydm_sta_info[fat_tab->train_idx];\n\n\t\t\tif (is_sta_active(entry)) {\n\t\t\t\t/*@Match MAC ADDR*/\n\t\t\t\tvalue32 = (entry->mac_addr[5] << 8) | entry->mac_addr[4];\n\n\t\t\t\todm_set_mac_reg(dm, R_0x7b4, 0xFFFF, value32); /*@0x7b4~0x7b5*/\n\n\t\t\t\tvalue32 = (entry->mac_addr[3] << 24) | (entry->mac_addr[2] << 16) | (entry->mac_addr[1] << 8) | entry->mac_addr[0];\n\n\t\t\t\todm_set_mac_reg(dm, R_0x7b0, MASKDWORD, value32); /*@0x7b0~0x7b3*/\n\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"fat_tab->train_idx=%d\\n\",\n\t\t\t\t\t  fat_tab->train_idx);\n\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"Training MAC addr = %x:%x:%x:%x:%x:%x\\n\",\n\t\t\t\t\t  entry->mac_addr[5],\n\t\t\t\t\t  entry->mac_addr[4],\n\t\t\t\t\t  entry->mac_addr[3],\n\t\t\t\t\t  entry->mac_addr[2],\n\t\t\t\t\t  entry->mac_addr[1],\n\t\t\t\t\t  entry->mac_addr[0]);\n\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n}\n\n#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))\n\nvoid odm_fast_ant_training(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\tu32 max_rssi_path_a = 0, pckcnt_path_a = 0;\n\tu8 i, target_ant_path_a = 0;\n\tboolean is_pkt_filter_macth_path_a = false;\n#if (RTL8192E_SUPPORT == 1)\n\tu32 max_rssi_path_b = 0, pckcnt_path_b = 0;\n\tu8 target_ant_path_b = 0;\n\tboolean is_pkt_filter_macth_path_b = false;\n#endif\n\n\tif (!dm->is_linked) { /* @is_linked==False */\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[No Link!!!]\\n\");\n\n\t\tif (fat_tab->is_become_linked == true) {\n\t\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);\n\t\t\tphydm_fast_training_enable(dm, FAT_OFF);\n\t\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);\n\t\t\tfat_tab->is_become_linked = dm->is_linked;\n\t\t}\n\t\treturn;\n\t} else {\n\t\tif (fat_tab->is_become_linked == false) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[Linked!!!]\\n\");\n\t\t\tfat_tab->is_become_linked = dm->is_linked;\n\t\t}\n\t}\n\n\tif (!(*fat_tab->p_force_tx_by_desc)) {\n\t\tif (dm->is_one_entry_only == true)\n\t\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);\n\t\telse\n\t\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);\n\t}\n\n\tif (dm->support_ic_type == ODM_RTL8188E)\n\t\todm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1));\n#if (RTL8192E_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8192E) {\n\t\todm_set_bb_reg(dm, R_0xb38, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1)); /* path-A  */ /* ant combination=regB38[2:0]+1 */\n\t\todm_set_bb_reg(dm, R_0xb38, BIT(18) | BIT(17) | BIT(16), ((dm->fat_comb_b) - 1)); /* path-B  */ /* ant combination=regB38[18:16]+1 */\n\t}\n#endif\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"==>%s\\n\", __func__);\n\n\t/* @1 TRAINING STATE */\n\tif (fat_tab->fat_state == FAT_TRAINING_STATE) {\n\t\t/* @2 Caculate RSSI per Antenna */\n\n\t\t/* @3 [path-A]--------------------------- */\n\t\tfor (i = 0; i < (dm->fat_comb_a); i++) { /* @i : antenna index */\n\t\t\tif (fat_tab->ant_rssi_cnt[i] == 0)\n\t\t\t\tfat_tab->ant_ave_rssi[i] = 0;\n\t\t\telse {\n\t\t\t\tfat_tab->ant_ave_rssi[i] = fat_tab->ant_sum_rssi[i] / fat_tab->ant_rssi_cnt[i];\n\t\t\t\tis_pkt_filter_macth_path_a = true;\n\t\t\t}\n\n\t\t\tif (fat_tab->ant_ave_rssi[i] > max_rssi_path_a) {\n\t\t\t\tmax_rssi_path_a = fat_tab->ant_ave_rssi[i];\n\t\t\t\tpckcnt_path_a = fat_tab->ant_rssi_cnt[i];\n\t\t\t\ttarget_ant_path_a = i;\n\t\t\t} else if (fat_tab->ant_ave_rssi[i] == max_rssi_path_a) {\n\t\t\t\tif (fat_tab->ant_rssi_cnt[i] > pckcnt_path_a) {\n\t\t\t\t\tmax_rssi_path_a = fat_tab->ant_ave_rssi[i];\n\t\t\t\t\tpckcnt_path_a = fat_tab->ant_rssi_cnt[i];\n\t\t\t\t\ttarget_ant_path_a = i;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tPHYDM_DBG(\n\t\t\t\t  \"*** ant-index : [ %d ],      counter = (( %d )),     Avg RSSI = (( %d ))\\n\",\n\t\t\t\t  i, fat_tab->ant_rssi_cnt[i],\n\t\t\t\t  fat_tab->ant_ave_rssi[i]);\n\t\t}\n\n#if 0\n#if (RTL8192E_SUPPORT == 1)\n\t\t/* @3 [path-B]--------------------------- */\n\t\tfor (i = 0; i < (dm->fat_comb_b); i++) {\n\t\t\tif (fat_tab->antRSSIcnt_pathB[i] == 0)\n\t\t\t\tfat_tab->antAveRSSI_pathB[i] = 0;\n\t\t\telse { /*  @(ant_rssi_cnt[i] != 0) */\n\t\t\t\tfat_tab->antAveRSSI_pathB[i] = fat_tab->antSumRSSI_pathB[i] / fat_tab->antRSSIcnt_pathB[i];\n\t\t\t\tis_pkt_filter_macth_path_b = true;\n\t\t\t}\n\t\t\tif (fat_tab->antAveRSSI_pathB[i] > max_rssi_path_b) {\n\t\t\t\tmax_rssi_path_b = fat_tab->antAveRSSI_pathB[i];\n\t\t\t\tpckcnt_path_b = fat_tab->antRSSIcnt_pathB[i];\n\t\t\t\ttarget_ant_path_b = (u8)i;\n\t\t\t}\n\t\t\tif (fat_tab->antAveRSSI_pathB[i] == max_rssi_path_b) {\n\t\t\t\tif (fat_tab->antRSSIcnt_pathB > pckcnt_path_b) {\n\t\t\t\t\tmax_rssi_path_b = fat_tab->antAveRSSI_pathB[i];\n\t\t\t\t\ttarget_ant_path_b = (u8)i;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (dm->fat_print_rssi == 1) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"***{path-B}: Sum RSSI[%d] = (( %d )),      cnt RSSI [%d] = (( %d )),     Avg RSSI[%d] = (( %d ))\\n\",\n\t\t\t\t\t  i, fat_tab->antSumRSSI_pathB[i], i,\n\t\t\t\t\t  fat_tab->antRSSIcnt_pathB[i], i,\n\t\t\t\t\t  fat_tab->antAveRSSI_pathB[i]);\n\t\t\t}\n\t\t}\n#endif\n#endif\n\n\t\t/* @1 DECISION STATE */\n\n\t\t/* @2 Select TRX Antenna */\n\n\t\tphydm_fast_training_enable(dm, FAT_OFF);\n\n\t\t/* @3 [path-A]--------------------------- */\n\t\tif (is_pkt_filter_macth_path_a == false) {\n#if 0\n\t\t\t/* PHYDM_DBG(dm,DBG_ANT_DIV, \"{path-A}: None Packet is matched\\n\"); */\n#endif\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"{path-A}: None Packet is matched\\n\");\n\t\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);\n\t\t} else {\n\t\t\tPHYDM_DBG(\n\t\t\t\t  \"target_ant_path_a = (( %d )) , max_rssi_path_a = (( %d ))\\n\",\n\t\t\t\t  target_ant_path_a, max_rssi_path_a);\n\n\t\t\t/* @3 [ update RX-optional ant ]        Default RX is Omni, Optional RX is the best decision by FAT */\n\t\t\tif (dm->support_ic_type == ODM_RTL8188E)\n\t\t\t\todm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), target_ant_path_a);\n\t\t\telse if (dm->support_ic_type == ODM_RTL8192E)\n\t\t\t\todm_set_bb_reg(dm, R_0xb38, BIT(8) | BIT(7) | BIT(6), target_ant_path_a); /* Optional RX [pth-A] */\n\n\t\t\t/* @3 [ update TX ant ] */\n\t\t\todm_update_tx_ant(dm, target_ant_path_a, (fat_tab->train_idx));\n\n\t\t\tif (target_ant_path_a == 0)\n\t\t\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);\n\t\t}\n#if 0\n#if (RTL8192E_SUPPORT == 1)\n\t\t/* @3 [path-B]--------------------------- */\n\t\tif (is_pkt_filter_macth_path_b == false) {\n\t\t\tif (dm->fat_print_rssi == 1)\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"***[%d]{path-B}: None Packet is matched\\n\\n\\n\",\n\t\t\t\t\t  __LINE__);\n\t\t} else {\n\t\t\tif (dm->fat_print_rssi == 1) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \" ***target_ant_path_b = (( %d )) *** max_rssi = (( %d ))***\\n\\n\\n\",\n\t\t\t\t\t  target_ant_path_b, max_rssi_path_b);\n\t\t\t}\n\t\t\todm_set_bb_reg(dm, R_0xb38, BIT(21) | BIT20 | BIT19, target_ant_path_b);\t/* @Default RX is Omni, Optional RX is the best decision by FAT */\n\t\t\todm_set_bb_reg(dm, R_0x80c, BIT(21), 1); /* Reg80c[21]=1'b1\t\t//from TX Info */\n\n\t\t\tfat_tab->antsel_pathB[fat_tab->train_idx] = target_ant_path_b;\n\t\t}\n#endif\n#endif\n\n\t\t/* @2 Reset counter */\n\t\tfor (i = 0; i < (dm->fat_comb_a); i++) {\n\t\t\tfat_tab->ant_sum_rssi[i] = 0;\n\t\t\tfat_tab->ant_rssi_cnt[i] = 0;\n\t\t}\n\t\t/*@\n\t\t#if (RTL8192E_SUPPORT == 1)\n\t\tfor(i=0; i<=(dm->fat_comb_b); i++)\n\t\t{\n\t\t\tfat_tab->antSumRSSI_pathB[i] = 0;\n\t\t\tfat_tab->antRSSIcnt_pathB[i] = 0;\n\t\t}\n\t\t#endif\n\t\t*/\n\n\t\tfat_tab->fat_state = FAT_PREPARE_STATE;\n\t\treturn;\n\t}\n\n\t/* @1 NORMAL STATE */\n\tif (fat_tab->fat_state == FAT_PREPARE_STATE) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[ Start Prepare state ]\\n\");\n\n\t\todm_set_next_mac_addr_target(dm);\n\n\t\t/* @2 Prepare Training */\n\t\tfat_tab->fat_state = FAT_TRAINING_STATE;\n\t\tphydm_fast_training_enable(dm, FAT_ON);\n\t\todm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);\n\t\t/* @enable HW AntDiv */\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[Start Training state]\\n\");\n\n\t\todm_set_timer(dm, &dm->fast_ant_training_timer, dm->antdiv_intvl); /* @ms */\n\t}\n}\n\nvoid odm_fast_ant_training_callback(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tif (*(dm->is_net_closed) == true)\n\t\treturn;\n#endif\n\n#if USE_WORKITEM\n\todm_schedule_work_item(&dm->fast_ant_training_workitem);\n#else\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"******%s******\\n\", __func__);\n\todm_fast_ant_training(dm);\n#endif\n}\n\nvoid odm_fast_ant_training_work_item_callback(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"******%s******\\n\", __func__);\n\todm_fast_ant_training(dm);\n}\n\n#endif\n\nvoid odm_ant_div_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tstruct sw_antenna_switch *swat_tab = &dm->dm_swat_table;\n\n\tif (!(dm->support_ability & ODM_BB_ANT_DIV)) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[Return!!!]   Not Support Antenna Diversity Function\\n\");\n\t\treturn;\n\t}\n/* @--- */\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\tif (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\\n\");\n\t\tif (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC))\n\t\t\treturn;\n\t} else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\\n\");\n\t\tif (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC))\n\t\t\treturn;\n\t} else if (fat_tab->ant_div_2g_5g == (ODM_ANTDIV_2G | ODM_ANTDIV_5G))\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\\n\");\n\n#endif\n\t/* @--- */\n\n\t/* @2 [--General---] */\n\tdm->antdiv_period = 0;\n\n\tfat_tab->is_become_linked = false;\n\tfat_tab->ant_div_on_off = 0xff;\n\n/* @3       -   AP   - */\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\todm_bdc_init(dm);\n#endif\n#endif\n\n/* @3     -   WIN   - */\n#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tswat_tab->ant_5g = MAIN_ANT;\n\tswat_tab->ant_2g = MAIN_ANT;\n#endif\n\n\t/* @2 [---Set MAIN_ANT as default antenna if Auto-ant enable---] */\n\tif (fat_tab->div_path_type == ANT_PATH_A)\n\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);\n\telse if (fat_tab->div_path_type == ANT_PATH_B)\n\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);\n\telse if (fat_tab->div_path_type == ANT_PATH_AB)\n\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);\n\n\tdm->ant_type = ODM_AUTO_ANT;\n\n\tfat_tab->rx_idle_ant = 0xff;\n\t\t/*to make RX-idle-antenna will be updated absolutly*/\n\todm_update_rx_idle_ant(dm, MAIN_ANT);\n\tphydm_keep_rx_ack_ant_by_tx_ant_time(dm, 0);\n\t/* Timming issue: keep Rx ant after tx for ACK(5 x 3.2 mu = 16mu sec)*/\n\n\t/* @2 [---Set TX Antenna---] */\n\tif (!fat_tab->p_force_tx_by_desc) {\n\t\tfat_tab->force_tx_by_desc = 0;\n\t\tfat_tab->p_force_tx_by_desc = &fat_tab->force_tx_by_desc;\n\t}\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"p_force_tx_by_desc = %d\\n\",\n\t\t  *fat_tab->p_force_tx_by_desc);\n\n\tif (*fat_tab->p_force_tx_by_desc)\n\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);\n\telse\n\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);\n\n\t/* @2 [--88E---] */\n\tif (dm->support_ic_type == ODM_RTL8188E) {\n#if (RTL8188E_SUPPORT == 1)\n\t\t/* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */\n\t\t/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */\n\t\t/* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */\n\n\t\tif (dm->ant_div_type != CGCS_RX_HW_ANTDIV &&\n\t\t    dm->ant_div_type != CG_TRX_HW_ANTDIV &&\n\t\t    dm->ant_div_type != CG_TRX_SMART_ANTDIV) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[Return!!!]  88E Not Supprrt This AntDiv type\\n\");\n\t\t\tdm->support_ability &= ~(ODM_BB_ANT_DIV);\n\t\t\treturn;\n\t\t}\n\n\t\tif (dm->ant_div_type == CGCS_RX_HW_ANTDIV)\n\t\t\todm_rx_hw_ant_div_init_88e(dm);\n\t\telse if (dm->ant_div_type == CG_TRX_HW_ANTDIV)\n\t\t\todm_trx_hw_ant_div_init_88e(dm);\n#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))\n\t\telse if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)\n\t\t\todm_smart_hw_ant_div_init_88e(dm);\n#endif\n#endif\n\t}\n\n/* @2 [--92E---] */\n#if (RTL8192E_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8192E) {\n\t\t/* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */\n\t\t/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */\n\t\t/* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */\n\n\t\tif (dm->ant_div_type != CGCS_RX_HW_ANTDIV &&\n\t\t    dm->ant_div_type != CG_TRX_HW_ANTDIV &&\n\t\t    dm->ant_div_type != CG_TRX_SMART_ANTDIV) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[Return!!!]  8192E Not Supprrt This AntDiv type\\n\");\n\t\t\tdm->support_ability &= ~(ODM_BB_ANT_DIV);\n\t\t\treturn;\n\t\t}\n\n\t\tif (dm->ant_div_type == CGCS_RX_HW_ANTDIV)\n\t\t\todm_rx_hw_ant_div_init_92e(dm);\n\t\telse if (dm->ant_div_type == CG_TRX_HW_ANTDIV)\n\t\t\todm_trx_hw_ant_div_init_92e(dm);\n#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))\n\t\telse if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)\n\t\t\todm_smart_hw_ant_div_init_92e(dm);\n#endif\n\t}\n#endif\n\n\t/* @2 [--92F---] */\n#if (RTL8192F_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8192F) {\n\t/* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */\n\t/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */\n\t/* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */\n\n\tif (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {\n\t\tif (dm->ant_div_type != CG_TRX_HW_ANTDIV) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[Return!!!]  8192F Not Supprrt This AntDiv type\\n\");\n\t\t\tdm->support_ability &= ~(ODM_BB_ANT_DIV);\n\t\t\treturn;\n\t\t}\n\t}\n\tif (dm->ant_div_type == CGCS_RX_HW_ANTDIV)\n\t\todm_rx_hw_ant_div_init_92f(dm);\n\telse if (dm->ant_div_type == CG_TRX_HW_ANTDIV)\n\todm_trx_hw_ant_div_init_92f(dm);\n\t}\n#endif\n\n#if (RTL8197F_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8197F) {\n\t\tdm->ant_div_type = CGCS_RX_HW_ANTDIV;\n\n\t\tif (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[Return!!!]  8197F Not Supprrt This AntDiv type\\n\");\n\t\t\tdm->support_ability &= ~(ODM_BB_ANT_DIV);\n\t\t\treturn;\n\t\t}\n\t\tphydm_rx_hw_ant_div_init_97f(dm);\n\t}\n#endif\n/* @2 [--8723B---] */\n#if (RTL8723B_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8723B) {\n\t\tdm->ant_div_type = S0S1_SW_ANTDIV;\n\t\t/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */\n\n\t\tif (dm->ant_div_type != S0S1_SW_ANTDIV &&\n\t\t    dm->ant_div_type != CG_TRX_HW_ANTDIV) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[Return!!!] 8723B  Not Supprrt This AntDiv type\\n\");\n\t\t\tdm->support_ability &= ~(ODM_BB_ANT_DIV);\n\t\t\treturn;\n\t\t}\n\n\t\tif (dm->ant_div_type == S0S1_SW_ANTDIV)\n\t\t\todm_s0s1_sw_ant_div_init_8723b(dm);\n\t\telse if (dm->ant_div_type == CG_TRX_HW_ANTDIV)\n\t\t\todm_trx_hw_ant_div_init_8723b(dm);\n\t}\n#endif\n/*@2 [--8723D---]*/\n#if (RTL8723D_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8723D) {\n\t\tif (fat_tab->p_default_s0_s1 == NULL) {\n\t\t\tfat_tab->default_s0_s1 = 1;\n\t\t\tfat_tab->p_default_s0_s1 = &fat_tab->default_s0_s1;\n\t\t}\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"default_s0_s1 = %d\\n\",\n\t\t\t  *fat_tab->p_default_s0_s1);\n\n\t\tif (*fat_tab->p_default_s0_s1 == true)\n\t\t\todm_update_rx_idle_ant(dm, MAIN_ANT);\n\t\telse\n\t\t\todm_update_rx_idle_ant(dm, AUX_ANT);\n\n\t\tif (dm->ant_div_type == S0S1_TRX_HW_ANTDIV)\n\t\t\todm_trx_hw_ant_div_init_8723d(dm);\n\t\telse if (dm->ant_div_type == S0S1_SW_ANTDIV)\n\t\t\todm_s0s1_sw_ant_div_init_8723d(dm);\n\t\telse {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\"[Return!!!] 8723D  Not Supprrt This AntDiv type\\n\");\n\t\t\tdm->support_ability &= ~(ODM_BB_ANT_DIV);\n\t\t\treturn;\n\t\t}\n\t}\n#endif\n#if (RTL8721D_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8721D) {\n\t\t/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */\n\n\t\tif (dm->ant_div_type != CG_TRX_HW_ANTDIV) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[Return!!!]  8721D Not Supprrt This AntDiv type\\n\");\n\t\t\tdm->support_ability &= ~(ODM_BB_ANT_DIV);\n\t\t\treturn;\n\t\t}\n\t\tif (dm->ant_div_type == CG_TRX_HW_ANTDIV)\n\t\t\todm_trx_hw_ant_div_init_8721d(dm);\n\t}\n#endif\n/* @2 [--8811A 8821A---] */\n#if (RTL8821A_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8821) {\n#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1\n\t\tdm->ant_div_type = HL_SW_SMART_ANT_TYPE1;\n\n\t\tif (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {\n\t\t\todm_trx_hw_ant_div_init_8821a(dm);\n\t\t\tphydm_hl_smart_ant_type1_init_8821a(dm);\n\t\t} else\n#endif\n\t\t{\n#ifdef ODM_CONFIG_BT_COEXIST\n\t\t\tdm->ant_div_type = S0S1_SW_ANTDIV;\n#else\n\t\t\tdm->ant_div_type = CG_TRX_HW_ANTDIV;\n#endif\n\n\t\t\tif (dm->ant_div_type != CG_TRX_HW_ANTDIV &&\n\t\t\t    dm->ant_div_type != S0S1_SW_ANTDIV) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"[Return!!!] 8821A & 8811A  Not Supprrt This AntDiv type\\n\");\n\t\t\t\tdm->support_ability &= ~(ODM_BB_ANT_DIV);\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tif (dm->ant_div_type == CG_TRX_HW_ANTDIV)\n\t\t\t\todm_trx_hw_ant_div_init_8821a(dm);\n\t\t\telse if (dm->ant_div_type == S0S1_SW_ANTDIV)\n\t\t\t\todm_s0s1_sw_ant_div_init_8821a(dm);\n\t\t}\n\t}\n#endif\n\n/* @2 [--8821C---] */\n#if (RTL8821C_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8821C) {\n\t\tdm->ant_div_type = S0S1_SW_ANTDIV;\n\t\tif (dm->ant_div_type != S0S1_SW_ANTDIV) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[Return!!!] 8821C  Not Supprrt This AntDiv type\\n\");\n\t\t\tdm->support_ability &= ~(ODM_BB_ANT_DIV);\n\t\t\treturn;\n\t\t}\n\t\tphydm_s0s1_sw_ant_div_init_8821c(dm);\n\t\todm_trx_hw_ant_div_init_8821c(dm);\n\t}\n#endif\n\n/* @2 [--8881A---] */\n#if (RTL8881A_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8881A) {\n\t\t/* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */\n\t\t/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */\n\n\t\tif (dm->ant_div_type == CG_TRX_HW_ANTDIV) {\n\t\t\todm_trx_hw_ant_div_init_8881a(dm);\n\t\t} else {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[Return!!!] 8881A  Not Supprrt This AntDiv type\\n\");\n\t\t\tdm->support_ability &= ~(ODM_BB_ANT_DIV);\n\t\t\treturn;\n\t\t}\n\n\t\todm_trx_hw_ant_div_init_8881a(dm);\n\t}\n#endif\n\n/* @2 [--8812---] */\n#if (RTL8812A_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8812) {\n\t\t/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */\n\n\t\tif (dm->ant_div_type != CG_TRX_HW_ANTDIV) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[Return!!!] 8812A  Not Supprrt This AntDiv type\\n\");\n\t\t\tdm->support_ability &= ~(ODM_BB_ANT_DIV);\n\t\t\treturn;\n\t\t}\n\t\todm_trx_hw_ant_div_init_8812a(dm);\n\t}\n#endif\n\n/*@[--8188F---]*/\n#if (RTL8188F_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8188F) {\n\t\tdm->ant_div_type = S0S1_SW_ANTDIV;\n\t\todm_s0s1_sw_ant_div_init_8188f(dm);\n\t}\n#endif\n\n/*@[--8822B---]*/\n#if (RTL8822B_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8822B) {\n\t\tdm->ant_div_type = CG_TRX_HW_ANTDIV;\n\n\t\tif (dm->ant_div_type != CG_TRX_HW_ANTDIV) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[Return!!!]  8822B Not Supprrt This AntDiv type\\n\");\n\t\t\tdm->support_ability &= ~(ODM_BB_ANT_DIV);\n\t\t\treturn;\n\t\t}\n\t\tphydm_trx_hw_ant_div_init_22b(dm);\n#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2\n\t\tdm->ant_div_type = HL_SW_SMART_ANT_TYPE2;\n\n\t\tif (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2)\n\t\t\tphydm_hl_smart_ant_type2_init_8822b(dm);\n#endif\n\t}\n#endif\n\n/*@PHYDM_DBG(dm, DBG_ANT_DIV, \"*** support_ic_type=[%lu]\\n\",*/\n/*dm->support_ic_type);*/\n/*PHYDM_DBG(dm, DBG_ANT_DIV, \"*** AntDiv support_ability=[%lu]\\n\",*/\n/*\t  (dm->support_ability & ODM_BB_ANT_DIV)>>6);*/\n/*PHYDM_DBG(dm, DBG_ANT_DIV, \"*** AntDiv type=[%d]\\n\",dm->ant_div_type);*/\n}\n\nvoid odm_ant_div(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tvoid *adapter = dm->adapter;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n#if (defined(CONFIG_HL_SMART_ANTENNA))\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n#endif\n\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\tif (dm->is_linked) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"tp_active_occur=((%d)), evm_method_enable=((%d))\\n\",\n\t\t\t  dm->tp_active_occur, fat_tab->evm_method_enable);\n\n\t\tif (dm->tp_active_occur == 1 &&\n\t\t    fat_tab->evm_method_enable == 1) {\n\t\t\tfat_tab->idx_ant_div_counter_5g = dm->antdiv_period;\n\t\t\tfat_tab->idx_ant_div_counter_2g = dm->antdiv_period;\n\t\t}\n\t}\n#endif\n\n\tif (*dm->band_type == ODM_BAND_5G) {\n\t\tif (fat_tab->idx_ant_div_counter_5g < dm->antdiv_period) {\n\t\t\tfat_tab->idx_ant_div_counter_5g++;\n\t\t\treturn;\n\t\t} else\n\t\t\tfat_tab->idx_ant_div_counter_5g = 0;\n\t} else if (*dm->band_type == ODM_BAND_2_4G) {\n\t\tif (fat_tab->idx_ant_div_counter_2g < dm->antdiv_period) {\n\t\t\tfat_tab->idx_ant_div_counter_2g++;\n\t\t\treturn;\n\t\t} else\n\t\t\tfat_tab->idx_ant_div_counter_2g = 0;\n\t}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN || DM_ODM_SUPPORT_TYPE == ODM_CE)\n\n\tif (fat_tab->enable_ctrl_frame_antdiv) {\n\t\tif (dm->data_frame_num <= 10 && dm->is_linked)\n\t\t\tfat_tab->use_ctrl_frame_antdiv = 1;\n\t\telse\n\t\t\tfat_tab->use_ctrl_frame_antdiv = 0;\n\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\\n\",\n\t\t\t  fat_tab->use_ctrl_frame_antdiv, dm->data_frame_num);\n\t\tdm->data_frame_num = 0;\n\t}\n\n\t{\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\n\t\tenum beamforming_cap beamform_cap = phydm_get_beamform_cap(dm);\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"is_bt_continuous_turn = ((%d))\\n\",\n\t\t\t  dm->is_bt_continuous_turn);\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ AntDiv Beam Cap ]   cap= ((%d))\\n\", beamform_cap);\n\t\tif (!dm->is_bt_continuous_turn) {\n\t\t\tif ((beamform_cap & BEAMFORMEE_CAP) &&\n\t\t\t    (!(*fat_tab->is_no_csi_feedback))) {\n\t\t\t    /* @BFmee On  &&   Div On->Div Off */\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"[ AntDiv : OFF ]   BFmee ==1; cap= ((%d))\\n\",\n\t\t\t\t\t  beamform_cap);\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"[ AntDiv BF]   is_no_csi_feedback= ((%d))\\n\",\n\t\t\t\t\t  *(fat_tab->is_no_csi_feedback));\n\t\t\t\tif (fat_tab->fix_ant_bfee == 0) {\n\t\t\t\t\todm_ant_div_on_off(dm, ANTDIV_OFF,\n\t\t\t\t\t\t\t   ANT_PATH_A);\n\t\t\t\t\tfat_tab->fix_ant_bfee = 1;\n\t\t\t\t}\n\t\t\t\treturn;\n\t\t\t} else { /* @BFmee Off   &&   Div Off->Div On */\n\t\t\t\tif (fat_tab->fix_ant_bfee == 1 &&\n\t\t\t\t    dm->is_linked) {\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t\t  \"[ AntDiv : ON ]   BFmee ==0; cap=((%d))\\n\",\n\t\t\t\t\t\t  beamform_cap);\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t\t  \"[ AntDiv BF]   is_no_csi_feedback= ((%d))\\n\",\n\t\t\t\t\t\t  *fat_tab->is_no_csi_feedback);\n\t\t\t\t\tif (dm->ant_div_type != S0S1_SW_ANTDIV)\n\t\t\t\t\t\todm_ant_div_on_off(dm, ANTDIV_ON\n\t\t\t\t\t\t\t\t   , ANT_PATH_A)\n\t\t\t\t\t\t\t\t   ;\n\t\t\t\t\tfat_tab->fix_ant_bfee = 0;\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tif (fat_tab->div_path_type == ANT_PATH_A)\n\t\t\t\todm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);\n\t\t\telse if (fat_tab->div_path_type == ANT_PATH_B)\n\t\t\t\todm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);\n\t\t\telse if (fat_tab->div_path_type == ANT_PATH_AB)\n\t\t\t\todm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);\n\t\t}\n#endif\n\t}\n#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t/* @----------just for fool proof */\n\n\tif (dm->antdiv_rssi)\n\t\tdm->debug_components |= DBG_ANT_DIV;\n\telse\n\t\tdm->debug_components &= ~DBG_ANT_DIV;\n\n\tif (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) {\n\t\tif (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC))\n\t\t\treturn;\n\t} else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) {\n\t\tif (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC))\n\t\t\treturn;\n\t}\n#endif\n\n\t/* @---------- */\n\n\tif (dm->antdiv_select == 1)\n\t\tdm->ant_type = ODM_FIX_MAIN_ANT;\n\telse if (dm->antdiv_select == 2)\n\t\tdm->ant_type = ODM_FIX_AUX_ANT;\n\telse { /* @if (dm->antdiv_select==0) */\n\t\tdm->ant_type = ODM_AUTO_ANT;\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t\t/*Stop Antenna diversity for CMW500 testing case*/\n\t\tif (dm->consecutive_idlel_time >= 10) {\n\t\t\tdm->ant_type = ODM_FIX_MAIN_ANT;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"[AntDiv: OFF] No TP case, consecutive_idlel_time=((%d))\\n\",\n\t\t\t\t  dm->consecutive_idlel_time);\n\t\t}\n#endif\n\t}\n\n\t/*PHYDM_DBG(dm, DBG_ANT_DIV,\"ant_type= (%d), pre_ant_type= (%d)\\n\",*/\n\t/*dm->ant_type,dm->pre_ant_type); */\n\n\tif (dm->ant_type != ODM_AUTO_ANT) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Fix Antenna at (( %s ))\\n\",\n\t\t\t  (dm->ant_type == ODM_FIX_MAIN_ANT) ? \"MAIN\" : \"AUX\");\n\n\t\tif (dm->ant_type != dm->pre_ant_type) {\n\t\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);\n\t\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);\n\n\t\t\tif (dm->ant_type == ODM_FIX_MAIN_ANT)\n\t\t\t\todm_update_rx_idle_ant(dm, MAIN_ANT);\n\t\t\telse if (dm->ant_type == ODM_FIX_AUX_ANT)\n\t\t\t\todm_update_rx_idle_ant(dm, AUX_ANT);\n\t\t}\n\t\tdm->pre_ant_type = dm->ant_type;\n\t\treturn;\n\t} else {\n\t\tif (dm->ant_type != dm->pre_ant_type) {\n\t\t\todm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);\n\t\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);\n\t\t}\n\t\tdm->pre_ant_type = dm->ant_type;\n\t}\n#if (defined(CONFIG_2T4R_ANTENNA))\n\tif (dm->ant_type2 != ODM_AUTO_ANT) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"PathB Fix Ant at (( %s ))\\n\",\n\t\t\t  (dm->ant_type2 == ODM_FIX_MAIN_ANT) ? \"MAIN\" : \"AUX\");\n\n\t\tif (dm->ant_type2 != dm->pre_ant_type2) {\n\t\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);\n\t\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);\n\n\t\t\tif (dm->ant_type2 == ODM_FIX_MAIN_ANT)\n\t\t\t\tphydm_update_rx_idle_ant_pathb(dm, MAIN_ANT);\n\t\t\telse if (dm->ant_type2 == ODM_FIX_AUX_ANT)\n\t\t\t\tphydm_update_rx_idle_ant_pathb(dm, AUX_ANT);\n\t\t}\n\t\tdm->pre_ant_type2 = dm->ant_type2;\n\t\treturn;\n\t}\n\tif (dm->ant_type2 != dm->pre_ant_type2) {\n\t\todm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);\n\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);\n\t}\n\tdm->pre_ant_type2 = dm->ant_type2;\n\n#endif\n\n/*@ ----------------------------------------------- */\n/*@ [--8188E--] */\n\tif (dm->support_ic_type == ODM_RTL8188E) {\n#if (RTL8188E_SUPPORT == 1)\n\t\tif (dm->ant_div_type == CG_TRX_HW_ANTDIV ||\n\t\t    dm->ant_div_type == CGCS_RX_HW_ANTDIV)\n\t\t\todm_hw_ant_div(dm);\n\n#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\\\n\t(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))\n\t\telse if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)\n\t\t\todm_fast_ant_training(dm);\n#endif\n\n#endif\n\t}\n/*@ [--8192E--] */\n#if (RTL8192E_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8192E) {\n\t\tif (dm->ant_div_type == CGCS_RX_HW_ANTDIV ||\n\t\t    dm->ant_div_type == CG_TRX_HW_ANTDIV)\n\t\t\todm_hw_ant_div(dm);\n\n#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\\\n\t(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))\n\t\telse if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)\n\t\t\todm_fast_ant_training(dm);\n#endif\n\t}\n#endif\n/*@ [--8197F--] */\n#if (RTL8197F_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8197F) {\n\t\tif (dm->ant_div_type == CGCS_RX_HW_ANTDIV)\n\t\t\todm_hw_ant_div(dm);\n\t}\n#endif\n\n#if (RTL8723B_SUPPORT == 1)\n/*@ [--8723B---] */\n\telse if (dm->support_ic_type == ODM_RTL8723B) {\n\t\tif (phydm_is_bt_enable_8723b(dm)) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[BT is enable!!!]\\n\");\n\t\t\tif (fat_tab->is_become_linked == true) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"Set REG 948[9:6]=0x0\\n\");\n\t\t\t\tif (dm->support_ic_type == ODM_RTL8723B)\n\t\t\t\t\todm_set_bb_reg(dm, R_0x948, 0x3c0, 0x0)\n\t\t\t\t\t\t       ;\n\n\t\t\t\tfat_tab->is_become_linked = false;\n\t\t\t}\n\t\t} else {\n\t\t\tif (dm->ant_div_type == S0S1_SW_ANTDIV) {\n\t\t\t\t#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\t\t\t\todm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);\n\t\t\t\t#endif\n\t\t\t} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)\n\t\t\t\todm_hw_ant_div(dm);\n\t\t}\n\t}\n#endif\n/*@ [--8723D--]*/\n#if (RTL8723D_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8723D) {\n\t\tif (dm->ant_div_type == S0S1_SW_ANTDIV) {\n\t\t\t#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\t\t\tif (dm->antdiv_counter == CONFIG_ANTDIV_PERIOD) {\n\t\t\t\todm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);\n\t\t\t\tdm->antdiv_counter--;\n\t\t\t} else {\n\t\t\t\tdm->antdiv_counter--;\n\t\t\t}\n\t\t\tif (dm->antdiv_counter == 0)\n\t\t\t\tdm->antdiv_counter = CONFIG_ANTDIV_PERIOD;\n\t\t\t#endif\n\t\t} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {\n\t\t\todm_hw_ant_div(dm);\n\t\t}\n\t}\n#endif\n#if (RTL8721D_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8721D) {\n\t\tif (dm->ant_div_type == CG_TRX_HW_ANTDIV) {\n\t\t\todm_hw_ant_div(dm);\n\t\t}\n\t}\n#endif\n/*@ [--8821A--] */\n#if (RTL8821A_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8821) {\n\t\t#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1\n\t\tif (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {\n\t\t\tif (sat_tab->fix_beam_pattern_en != 0) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \" [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\\n\",\n\t\t\t\t\t  sat_tab->fix_beam_pattern_codeword);\n\t\t\t\t/*return;*/\n\t\t\t} else {\n\t\t\t\todm_fast_ant_training_hl_smart_antenna_type1(dm);\n\t\t\t}\n\n\t\t} else\n\t\t#endif\n\t\t{\n\t\t#ifdef ODM_CONFIG_BT_COEXIST\n\t\t\tif (!dm->bt_info_table.is_bt_enabled) { /*@BT disabled*/\n\t\t\t\tif (dm->ant_div_type == S0S1_SW_ANTDIV) {\n\t\t\t\t\tdm->ant_div_type = CG_TRX_HW_ANTDIV;\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t\t  \" [S0S1_SW_ANTDIV]  ->  [CG_TRX_HW_ANTDIV]\\n\");\n\t\t\t\t\t/*odm_set_bb_reg(dm, 0x8d4, BIT24, 1);*/\n\t\t\t\t\tif (fat_tab->is_become_linked == true)\n\t\t\t\t\t\todm_ant_div_on_off(dm,\n\t\t\t\t\t\t\t\t   ANTDIV_ON,\n\t\t\t\t\t\t\t\t   ANT_PATH_A);\n\t\t\t\t}\n\n\t\t\t} else { /*@BT enabled*/\n\n\t\t\t\tif (dm->ant_div_type == CG_TRX_HW_ANTDIV) {\n\t\t\t\t\tdm->ant_div_type = S0S1_SW_ANTDIV;\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t\t  \" [CG_TRX_HW_ANTDIV]  ->  [S0S1_SW_ANTDIV]\\n\");\n\t\t\t\t\t/*odm_set_bb_reg(dm, 0x8d4, BIT24, 0);*/\n\t\t\t\t\todm_ant_div_on_off(dm, ANTDIV_OFF,\n\t\t\t\t\t\t\t   ANT_PATH_A);\n\t\t\t\t}\n\t\t\t}\n\t\t#endif\n\n\t\t\tif (dm->ant_div_type == S0S1_SW_ANTDIV) {\n\t\t\t\t#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\t\t\t\todm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);\n\t\t\t\t#endif\n\t\t\t} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {\n\t\t\t\todm_hw_ant_div(dm);\n\t\t\t}\n\t\t}\n\t}\n#endif\n\n/*@ [--8821C--] */\n#if (RTL8821C_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8821C) {\n\t\tif (!dm->is_bt_continuous_turn) {\n\t\t\tdm->ant_div_type = S0S1_SW_ANTDIV;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"is_bt_continuous_turn = ((%d))   ==> SW AntDiv\\n\",\n\t\t\t\t  dm->is_bt_continuous_turn);\n\n\t\t} else {\n\t\t\tdm->ant_div_type = CG_TRX_HW_ANTDIV;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"is_bt_continuous_turn = ((%d))   ==> HW AntDiv\\n\",\n\t\t\t\t  dm->is_bt_continuous_turn);\n\t\t\todm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);\n\t\t}\n\n\t\tif (fat_tab->force_antdiv_type)\n\t\t\tdm->ant_div_type = fat_tab->antdiv_type_dbg;\n\n\t\tif (dm->ant_div_type == S0S1_SW_ANTDIV) {\n\t\t\t#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\t\t\todm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);\n\t\t\t#endif\n\t\t} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {\n\t\t\todm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);\n\t\t\todm_hw_ant_div(dm);\n\t\t}\n\t}\n#endif\n\n/* @ [--8881A--] */\n#if (RTL8881A_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8881A)\n\t\todm_hw_ant_div(dm);\n#endif\n\n/*@ [--8812A--] */\n#if (RTL8812A_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8812)\n\t\todm_hw_ant_div(dm);\n#endif\n\n#if (RTL8188F_SUPPORT == 1)\n/*@ [--8188F--]*/\n\telse if (dm->support_ic_type == ODM_RTL8188F) {\n\t\t#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\t\todm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);\n\t\t#endif\n\t}\n#endif\n\n/*@ [--8822B--]*/\n#if (RTL8822B_SUPPORT == 1)\n\telse if (dm->support_ic_type == ODM_RTL8822B) {\n\t\tif (dm->ant_div_type == CG_TRX_HW_ANTDIV)\n\t\t\todm_hw_ant_div(dm);\n\t\t#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2\n\t\tif (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) {\n\t\t\tif (sat_tab->fix_beam_pattern_en != 0)\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \" [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\\n\",\n\t\t\t\t\t  sat_tab->fix_beam_pattern_codeword);\n\t\t\telse\n\t\t\t\tphydm_fast_ant_training_hl_smart_antenna_type2(dm);\n\t\t}\n\t\t#endif\n\t}\n#endif\n}\n\nvoid odm_antsel_statistics(void *dm_void, void *phy_info_void,\n\t\t\t   u8 antsel_tr_mux, u32 mac_id, u32 utility, u8 method,\n\t\t\t   u8 is_cck_rate)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tstruct phydm_phyinfo_struct *phy_info = NULL;\n\n\tphy_info = (struct phydm_phyinfo_struct *)phy_info_void;\n\n\tif (method == RSSI_METHOD) {\n\t\tif (is_cck_rate) {\n\t\t\tif (antsel_tr_mux == ANT1_2G) {\n\t/*to prevent u16 overflow, max(RSSI)=100, 65435+100 = 65535 (u16)*/\n\t\t\t\tif (fat_tab->main_sum_cck[mac_id] > 65435)\n\t\t\t\t\treturn;\n\n\t\t\t\tfat_tab->main_sum_cck[mac_id] += (u16)utility;\n\t\t\t\tfat_tab->main_cnt_cck[mac_id]++;\n\t\t\t} else {\n\t\t\t\tif (fat_tab->aux_sum_cck[mac_id] > 65435)\n\t\t\t\t\treturn;\n\n\t\t\t\tfat_tab->aux_sum_cck[mac_id] += (u16)utility;\n\t\t\t\tfat_tab->aux_cnt_cck[mac_id]++;\n\t\t\t}\n\n\t\t} else { /*ofdm rate*/\n\n\t\t\tif (antsel_tr_mux == ANT1_2G) {\n\t\t\t\tif (fat_tab->main_sum[mac_id] > 65435)\n\t\t\t\t\treturn;\n\n\t\t\t\tfat_tab->main_sum[mac_id] += (u16)utility;\n\t\t\t\tfat_tab->main_cnt[mac_id]++;\n\t\t\t} else {\n\t\t\t\tif (fat_tab->aux_sum[mac_id] > 65435)\n\t\t\t\t\treturn;\n\n\t\t\t\tfat_tab->aux_sum[mac_id] += (u16)utility;\n\t\t\t\tfat_tab->aux_cnt[mac_id]++;\n\t\t\t}\n\t\t}\n\t}\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\telse if (method == EVM_METHOD) {\n\t\tif (!fat_tab->get_stats)\n\t\t\treturn;\n\n\t\tif (dm->rate_ss == 1) {\n\t\t\tphydm_statistics_evm_1ss(dm, phy_info, antsel_tr_mux,\n\t\t\t\t\t\t mac_id, utility);\n\t\t} else { /*@>= 2SS*/\n\t\t\tphydm_statistics_evm_2ss(dm, phy_info, antsel_tr_mux,\n\t\t\t\t\t\t mac_id, utility);\n\t\t}\n\n\t} else if (method == CRC32_METHOD) {\n\t\tif (antsel_tr_mux == ANT1_2G) {\n\t\t\tfat_tab->main_crc32_ok_cnt += utility;\n\t\t\tfat_tab->main_crc32_fail_cnt++;\n\t\t} else {\n\t\t\tfat_tab->aux_crc32_ok_cnt += utility;\n\t\t\tfat_tab->aux_crc32_fail_cnt++;\n\t\t}\n\n\t} else if (method == TP_METHOD) {\n\t\tif (!fat_tab->get_stats)\n\t\t\treturn;\n\t\tif (utility <= ODM_RATEMCS15 && utility >= ODM_RATEMCS0) {\n\t\t\tif (antsel_tr_mux == ANT1_2G) {\n\t\t\t\tfat_tab->main_tp += (phy_rate_table[utility])\n\t\t\t\t\t\t    << 5;\n\t\t\t\tfat_tab->main_tp_cnt++;\n\t\t\t} else {\n\t\t\t\tfat_tab->aux_tp += (phy_rate_table[utility])\n\t\t\t\t\t\t   << 5;\n\t\t\t\tfat_tab->aux_tp_cnt++;\n\t\t\t}\n\t\t}\n\t}\n#endif\n}\n\nvoid odm_process_rssi_smart(void *dm_void, void *phy_info_void,\n\t\t\t    void *pkt_info_void, u8 rx_power_ant0)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_phyinfo_struct *phy_info = NULL;\n\tstruct phydm_perpkt_info_struct *pktinfo = NULL;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\tphy_info = (struct phydm_phyinfo_struct *)phy_info_void;\n\tpktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;\n\n\tif ((dm->support_ic_type & ODM_SMART_ANT_SUPPORT) &&\n\t    pktinfo->is_packet_to_self &&\n\t    fat_tab->fat_state == FAT_TRAINING_STATE) {\n\t/* @(pktinfo->is_packet_match_bssid && (!pktinfo->is_packet_beacon)) */\n\t\tu8 antsel_tr_mux;\n\n\t\tantsel_tr_mux = (fat_tab->antsel_rx_keep_2 << 2) |\n\t\t\t\t(fat_tab->antsel_rx_keep_1 << 1) |\n\t\t\t\tfat_tab->antsel_rx_keep_0;\n\t\tfat_tab->ant_sum_rssi[antsel_tr_mux] += rx_power_ant0;\n\t\tfat_tab->ant_rssi_cnt[antsel_tr_mux]++;\n\t}\n}\n\nvoid odm_process_rssi_normal(void *dm_void, void *phy_info_void,\n\t\t\t     void *pkt_info_void, u8 rx_pwr0)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_phyinfo_struct *phy_info = NULL;\n\tstruct phydm_perpkt_info_struct *pktinfo = NULL;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tu8 rx_evm0, rx_evm1;\n\tboolean b_main;\n\n\tphy_info = (struct phydm_phyinfo_struct *)phy_info_void;\n\tpktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;\n\trx_evm0 = phy_info->rx_mimo_signal_quality[0];\n\trx_evm1 = phy_info->rx_mimo_signal_quality[1];\n\n\tif (!(pktinfo->is_packet_to_self || fat_tab->use_ctrl_frame_antdiv))\n\t\treturn;\n\n\tif (dm->ant_div_type == S0S1_SW_ANTDIV) {\n\t\tif (pktinfo->is_cck_rate ||\n\t\t    dm->support_ic_type == ODM_RTL8188F) {\n\n\t\t\tb_main = (fat_tab->rx_idle_ant == MAIN_ANT);\n\t\t\tfat_tab->antsel_rx_keep_0 = b_main ? ANT1_2G : ANT2_2G;\n\t\t}\n\n\t\todm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,\n\t\t\t\t      pktinfo->station_id, rx_pwr0, RSSI_METHOD,\n\t\t\t\t      pktinfo->is_cck_rate);\n\t} else {\n\t\todm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,\n\t\t\t\t      pktinfo->station_id, rx_pwr0, RSSI_METHOD,\n\t\t\t\t      pktinfo->is_cck_rate);\n\n\t\t#ifdef ODM_EVM_ENHANCE_ANTDIV\n\t\tif (!(dm->support_ic_type & ODM_EVM_ANTDIV_IC))\n\t\t\treturn;\n\t\tif (pktinfo->is_cck_rate)\n\t\t\treturn;\n\n\t\todm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,\n\t\t\t\t      pktinfo->station_id, rx_evm0, EVM_METHOD,\n\t\t\t\t      pktinfo->is_cck_rate);\n\t\todm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,\n\t\t\t\t      pktinfo->station_id, rx_evm0, TP_METHOD,\n\t\t\t\t      pktinfo->is_cck_rate);\n\t\t#endif\n\t}\n}\n\nvoid odm_process_rssi_for_ant_div(void *dm_void, void *phy_info_void,\n\t\t\t\t  void *pkt_info_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_phyinfo_struct *phy_info = NULL;\n\tstruct phydm_perpkt_info_struct *pktinfo = NULL;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n#if (defined(CONFIG_HL_SMART_ANTENNA))\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\tu32 beam_tmp;\n\tu8 next_ant;\n\tu8 train_pkt_number;\n#endif\n\tboolean b_main;\n\tu8 rx_power_ant0, rx_power_ant1;\n\tu8 rx_evm_ant0, rx_evm_ant1;\n\tu8 rssi_avg;\n\tu64 rssi_linear = 0;\n\n\tphy_info = (struct phydm_phyinfo_struct *)phy_info_void;\n\tpktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;\n\trx_power_ant0 = phy_info->rx_mimo_signal_strength[0];\n\trx_power_ant1 = phy_info->rx_mimo_signal_strength[1];\n\trx_evm_ant0 = phy_info->rx_mimo_signal_quality[0];\n\trx_evm_ant1 = phy_info->rx_mimo_signal_quality[1];\n\n\tif ((dm->support_ic_type & ODM_IC_2SS) && !pktinfo->is_cck_rate) {\n\t\tif (rx_power_ant1 < 100) {\n\t\t\trssi_linear = phydm_db_2_linear(rx_power_ant0) +\n\t\t\t\t      phydm_db_2_linear(rx_power_ant1);\n\t\t\t/* @Rounding and removing fractional bits */\n\t\t\trssi_linear = (rssi_linear +\n\t\t\t\t       (1 << (FRAC_BITS - 1))) >> FRAC_BITS;\n\t\t\t/* @Calculate average RSSI */\n\t\t\trssi_linear = DIVIDED_2(rssi_linear);\n\t\t\t/* @averaged PWDB */\n\t\t\trssi_avg = (u8)odm_convert_to_db(rssi_linear);\n\t\t}\n\n\t} else {\n\t\trx_power_ant0 = (u8)phy_info->rx_pwdb_all;\n\t\trssi_avg = rx_power_ant0;\n\t}\n\n#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2\n\tif ((dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) && (fat_tab->fat_state == FAT_TRAINING_STATE))\n\t\tphydm_process_rssi_for_hb_smtant_type2(dm, phy_info, pktinfo, rssi_avg); /*@for 8822B*/\n\telse\n#endif\n\n#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1\n#ifdef CONFIG_FAT_PATCH\n\t\tif (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1 && fat_tab->fat_state == FAT_TRAINING_STATE) {\n\t\t/*@[Beacon]*/\n\t\tif (pktinfo->is_packet_beacon) {\n\t\t\tsat_tab->beacon_counter++;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"MatchBSSID_beacon_counter = ((%d))\\n\",\n\t\t\t\t  sat_tab->beacon_counter);\n\n\t\t\tif (sat_tab->beacon_counter >= sat_tab->pre_beacon_counter + 2) {\n\t\t\t\tif (sat_tab->ant_num > 1) {\n\t\t\t\t\tnext_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;\n\t\t\t\t\todm_update_rx_idle_ant(dm, next_ant);\n\t\t\t\t}\n\n\t\t\t\tsat_tab->update_beam_idx++;\n\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\\n\",\n\t\t\t\t\t  sat_tab->pre_beacon_counter,\n\t\t\t\t\t  sat_tab->pkt_counter,\n\t\t\t\t\t  sat_tab->update_beam_idx);\n\n\t\t\t\tsat_tab->pre_beacon_counter = sat_tab->beacon_counter;\n\t\t\t\tsat_tab->pkt_counter = 0;\n\t\t\t}\n\t\t}\n\t\t/*@[data]*/\n\t\telse if (pktinfo->is_packet_to_self) {\n\t\t\tif (sat_tab->pkt_skip_statistic_en == 0) {\n\t\t\t\t/*@\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"StaID[%d]:  antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\\n\",\n\t\t\t\t\tpktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0);\n\t\t\t\t*/\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"ID[%d][pkt_cnt = %d]: {ANT, Beam} = {%d, %d}, RSSI = ((%d))\\n\",\n\t\t\t\t\t  pktinfo->station_id,\n\t\t\t\t\t  sat_tab->pkt_counter,\n\t\t\t\t\t  fat_tab->antsel_rx_keep_0,\n\t\t\t\t\t  sat_tab->fast_training_beam_num,\n\t\t\t\t\t  rx_power_ant0);\n\n\t\t\t\tsat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0;\n\t\t\t\tsat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++;\n\t\t\t\tsat_tab->pkt_counter++;\n\n#if 1\n\t\t\t\ttrain_pkt_number = sat_tab->beam_train_cnt[fat_tab->rx_idle_ant - 1][sat_tab->fast_training_beam_num];\n#else\n\t\t\t\ttrain_pkt_number = sat_tab->per_beam_training_pkt_num;\n#endif\n\n\t\t\t\t/*Swich Antenna erery N pkts*/\n\t\t\t\tif (sat_tab->pkt_counter == train_pkt_number) {\n\t\t\t\t\tif (sat_tab->ant_num > 1) {\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"packet enugh ((%d ))pkts ---> Switch antenna\\n\", train_pkt_number);\n\t\t\t\t\t\tnext_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;\n\t\t\t\t\t\todm_update_rx_idle_ant(dm, next_ant);\n\t\t\t\t\t}\n\n\t\t\t\t\tsat_tab->update_beam_idx++;\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"pre_beacon_counter = ((%d)), update_beam_idx_counter = ((%d))\\n\",\n\t\t\t\t\t\t  sat_tab->pre_beacon_counter, sat_tab->update_beam_idx);\n\n\t\t\t\t\tsat_tab->pre_beacon_counter = sat_tab->beacon_counter;\n\t\t\t\t\tsat_tab->pkt_counter = 0;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/*Swich Beam after switch \"sat_tab->ant_num\" antennas*/\n\t\tif (sat_tab->update_beam_idx == sat_tab->ant_num) {\n\t\t\tsat_tab->update_beam_idx = 0;\n\t\t\tsat_tab->pkt_counter = 0;\n\t\t\tbeam_tmp = sat_tab->fast_training_beam_num;\n\n\t\t\tif (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {\n\t\t\t\tfat_tab->fat_state = FAT_DECISION_STATE;\n\n#if DEV_BUS_TYPE == RT_PCI_INTERFACE\n\t\t\t\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\t\t\t\todm_fast_ant_training_hl_smart_antenna_type1(dm);\n#endif\n#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE\n\t\t\t\tif (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)\n\t\t\t\t\todm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);\n#endif\n\n\t\t\t} else {\n\t\t\t\tsat_tab->fast_training_beam_num++;\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"Update Beam_num (( %d )) -> (( %d ))\\n\",\n\t\t\t\t\t  beam_tmp,\n\t\t\t\t\t  sat_tab->fast_training_beam_num);\n\t\t\t\tphydm_set_all_ant_same_beam_num(dm);\n\n\t\t\t\tfat_tab->fat_state = FAT_TRAINING_STATE;\n\t\t\t}\n\t\t}\n\t}\n#else\n\n\t\tif (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {\n\t\tif ((dm->support_ic_type & ODM_HL_SMART_ANT_TYPE1_SUPPORT) &&\n\t\t    pktinfo->is_packet_to_self &&\n\t\t    fat_tab->fat_state == FAT_TRAINING_STATE) {\n\t\t\tif (sat_tab->pkt_skip_statistic_en == 0) {\n\t\t\t\t/*@\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"StaID[%d]:  antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\\n\",\n\t\t\t\t\tpktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0);\n\t\t\t\t*/\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"StaID[%d]:  antsel_pathA = ((%d)), is_packet_to_self = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\\n\",\n\t\t\t\t\t  pktinfo->station_id,\n\t\t\t\t\t  fat_tab->antsel_rx_keep_0,\n\t\t\t\t\t  pktinfo->is_packet_to_self,\n\t\t\t\t\t  sat_tab->fast_training_beam_num,\n\t\t\t\t\t  rx_power_ant0);\n\n\t\t\t\tsat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0;\n\t\t\t\tsat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++;\n\t\t\t\tsat_tab->pkt_counter++;\n\n\t\t\t\t/*swich beam every N pkt*/\n\t\t\t\tif (sat_tab->pkt_counter >= sat_tab->per_beam_training_pkt_num) {\n\t\t\t\t\tsat_tab->pkt_counter = 0;\n\t\t\t\t\tbeam_tmp = sat_tab->fast_training_beam_num;\n\n\t\t\t\t\tif (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {\n\t\t\t\t\t\tfat_tab->fat_state = FAT_DECISION_STATE;\n\n#if DEV_BUS_TYPE == RT_PCI_INTERFACE\n\t\t\t\t\t\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\t\t\t\t\t\todm_fast_ant_training_hl_smart_antenna_type1(dm);\n#endif\n#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE\n\t\t\t\t\t\tif (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)\n\t\t\t\t\t\t\todm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);\n#endif\n\n\t\t\t\t\t} else {\n\t\t\t\t\t\tsat_tab->fast_training_beam_num++;\n\t\t\t\t\t\tphydm_set_all_ant_same_beam_num(dm);\n\n\t\t\t\t\t\tfat_tab->fat_state = FAT_TRAINING_STATE;\n\t\t\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Update  Beam_num (( %d )) -> (( %d ))\\n\", beam_tmp, sat_tab->fast_training_beam_num);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n#endif\n\telse\n#endif\n\t\tif (dm->ant_div_type == CG_TRX_SMART_ANTDIV) {\n\t\t\todm_process_rssi_smart(dm, phy_info, pktinfo,\n\t\t\t\t\t       rx_power_ant0);\n\t\t} else { /* @ant_div_type != CG_TRX_SMART_ANTDIV */\n\t\t\todm_process_rssi_normal(dm, phy_info, pktinfo,\n\t\t\t\t\t\trx_power_ant0);\n\t\t}\n#if 0\n/* PHYDM_DBG(dm,DBG_ANT_DIV,\"is_cck_rate=%d, pwdb_all=%d\\n\",\n *\t     pktinfo->is_cck_rate, phy_info->rx_pwdb_all);\n * PHYDM_DBG(dm,DBG_ANT_DIV,\"antsel_tr_mux=3'b%d%d%d\\n\",\n *\t     fat_tab->antsel_rx_keep_2, fat_tab->antsel_rx_keep_1,\n *\t     fat_tab->antsel_rx_keep_0);\n */\n#endif\n}\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))\nvoid odm_set_tx_ant_by_tx_info(void *dm_void, u8 *desc, u8 mac_id)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\tif (!(dm->support_ability & ODM_BB_ANT_DIV))\n\t\treturn;\n\n\tif (dm->ant_div_type == CGCS_RX_HW_ANTDIV)\n\t\treturn;\n\n\tif (dm->support_ic_type == (ODM_RTL8723B | ODM_RTL8721D)) {\n#if (RTL8723B_SUPPORT == 1 || RTL8721D_SUPPORT == 1)\n\t\tSET_TX_DESC_ANTSEL_A_8723B(desc, fat_tab->antsel_a[mac_id]);\n/*PHYDM_DBG(dm,DBG_ANT_DIV,\n *\t   \"[8723B] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\\n\",\n *\t    mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],\n *\t    fat_tab->antsel_a[mac_id]);\n */\n#endif\n\t} else if (dm->support_ic_type == ODM_RTL8821) {\n#if (RTL8821A_SUPPORT == 1)\n\t\tSET_TX_DESC_ANTSEL_A_8812(desc, fat_tab->antsel_a[mac_id]);\n/*PHYDM_DBG(dm,DBG_ANT_DIV,\n *\t   \"[8821A] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\\n\",\n *\t    mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],\n *\t    fat_tab->antsel_a[mac_id]);\n */\n#endif\n\t} else if (dm->support_ic_type == ODM_RTL8188E) {\n#if (RTL8188E_SUPPORT == 1)\n\t\tSET_TX_DESC_ANTSEL_A_88E(desc, fat_tab->antsel_a[mac_id]);\n\t\tSET_TX_DESC_ANTSEL_B_88E(desc, fat_tab->antsel_b[mac_id]);\n\t\tSET_TX_DESC_ANTSEL_C_88E(desc, fat_tab->antsel_c[mac_id]);\n/*PHYDM_DBG(dm,DBG_ANT_DIV,\n *\t   \"[8188E] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\\n\",\n *\t    mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],\n *\t    fat_tab->antsel_a[mac_id]);\n */\n#endif\n\t} else if (dm->support_ic_type == ODM_RTL8821C) {\n#if (RTL8821C_SUPPORT == 1)\n\t\tSET_TX_DESC_ANTSEL_A_8821C(desc, fat_tab->antsel_a[mac_id]);\n/*PHYDM_DBG(dm,DBG_ANT_DIV,\n *\t   \"[8821C] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\\n\",\n *\t    mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],\n *\t    fat_tab->antsel_a[mac_id]);\n */\n#endif\n\t} else if (dm->support_ic_type == ODM_RTL8822B) {\n#if (RTL8822B_SUPPORT == 1)\n\t\tSET_TX_DESC_ANTSEL_A_8822B(desc, fat_tab->antsel_a[mac_id]);\n#endif\n\n\t}\n}\n#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\nvoid odm_set_tx_ant_by_tx_info(\n\tstruct rtl8192cd_priv *priv,\n\tstruct tx_desc *pdesc,\n\tunsigned short aid)\n{\n\tstruct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\n\tif (!(dm->support_ability & ODM_BB_ANT_DIV))\n\t\treturn;\n\n\tif (dm->ant_div_type == CGCS_RX_HW_ANTDIV)\n\t\treturn;\n\n\tif (dm->support_ic_type == ODM_RTL8881A) {\n#if 0\n\t\t/*panic_printk(\"[%s] [%d]   ******ODM_SetTxAntByTxInfo_8881E******\\n\",__FUNCTION__,__LINE__);\t*/\n#endif\n\t\tpdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16)));\n\t\tpdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);\n\t} else if (dm->support_ic_type == ODM_RTL8192E) {\n#if 0\n\t\t/*panic_printk(\"[%s] [%d]   ******ODM_SetTxAntByTxInfo_8192E******\\n\",__FUNCTION__,__LINE__);\t*/\n#endif\n\t\tpdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16)));\n\t\tpdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);\n\t} else if (dm->support_ic_type == ODM_RTL8197F) {\n#if 0\n\t\t/*panic_printk(\"[%s] [%d]   ******ODM_SetTxAntByTxInfo_8192E******\\n\",__FUNCTION__,__LINE__);\t*/\n#endif\n\t\tpdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16)));\n\t\tpdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);\n\t} else if (dm->support_ic_type == ODM_RTL8822B) {\n\t\tpdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16)));\n\t\tpdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);\n\t} else if (dm->support_ic_type == ODM_RTL8188E) {\n#if 0\n\t\t/*panic_printk(\"[%s] [%d]   ******ODM_SetTxAntByTxInfo_8188E******\\n\",__FUNCTION__,__LINE__);*/\n#endif\n\t\tpdesc->Dword2 &= set_desc(~BIT(24));\n\t\tpdesc->Dword2 &= set_desc(~BIT(25));\n\t\tpdesc->Dword7 &= set_desc(~BIT(29));\n\n\t\tpdesc->Dword2 |= set_desc(fat_tab->antsel_a[aid] << 24);\n\t\tpdesc->Dword2 |= set_desc(fat_tab->antsel_b[aid] << 25);\n\t\tpdesc->Dword7 |= set_desc(fat_tab->antsel_c[aid] << 29);\n\n\t} else if (dm->support_ic_type == ODM_RTL8812) {\n\t\t/*@[path-A]*/\n#if 0\n\t\t/*panic_printk(\"[%s] [%d]   ******ODM_SetTxAntByTxInfo_8881E******\\n\",__FUNCTION__,__LINE__);*/\n#endif\n\n\t\tpdesc->Dword6 &= set_desc(~BIT(16));\n\t\tpdesc->Dword6 &= set_desc(~BIT(17));\n\t\tpdesc->Dword6 &= set_desc(~BIT(18));\n\n\t\tpdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);\n\t\tpdesc->Dword6 |= set_desc(fat_tab->antsel_b[aid] << 17);\n\t\tpdesc->Dword6 |= set_desc(fat_tab->antsel_c[aid] << 18);\n\t}\n}\n\n#if 1 /*@def CONFIG_WLAN_HAL*/\nvoid odm_set_tx_ant_by_tx_info_hal(\n\tstruct rtl8192cd_priv *priv,\n\tvoid *pdesc_data,\n\tu16 aid)\n{\n\tstruct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tPTX_DESC_DATA_88XX pdescdata = (PTX_DESC_DATA_88XX)pdesc_data;\n\n\tif (!(dm->support_ability & ODM_BB_ANT_DIV))\n\t\treturn;\n\n\tif (dm->ant_div_type == CGCS_RX_HW_ANTDIV)\n\t\treturn;\n\n\tif (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8814A |\n\t    ODM_RTL8197F | ODM_RTL8822B)) {\n#if 0\n\t\t/*panic_printk(\"[%s] [%d] **odm_set_tx_ant_by_tx_info_hal**\\n\",\n\t\t *\t       __FUNCTION__,__LINE__);\n\t\t */\n#endif\n\t\tpdescdata->ant_sel = 1;\n\t\tpdescdata->ant_sel_a = fat_tab->antsel_a[aid];\n\t}\n}\n#endif /*@#ifdef CONFIG_WLAN_HAL*/\n\n#endif\n\nvoid odm_ant_div_config(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"WIN Config Antenna Diversity\\n\");\n\t/*@\n\tif(dm->support_ic_type==ODM_RTL8723B)\n\t{\n\t\tif((!dm->swat_tab.ANTA_ON || !dm->swat_tab.ANTB_ON))\n\t\t\tdm->support_ability &= ~(ODM_BB_ANT_DIV);\n\t}\n\t*/\n\t#if (defined(CONFIG_2T3R_ANTENNA))\n\t#if (RTL8822B_SUPPORT == 1)\n\t\tdm->rfe_type = ANT_2T3R_RFE_TYPE;\n\t#endif\n\t#endif\n\n\t#if (defined(CONFIG_2T4R_ANTENNA))\n\t#if (RTL8822B_SUPPORT == 1)\n\t\tdm->rfe_type = ANT_2T4R_RFE_TYPE;\n\t#endif\n\t#endif\n\n\tif (dm->support_ic_type == ODM_RTL8723D)\n\t\tdm->ant_div_type = S0S1_SW_ANTDIV;\n#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"CE Config Antenna Diversity\\n\");\n\n\tif (dm->support_ic_type == ODM_RTL8723B)\n\t\tdm->ant_div_type = S0S1_SW_ANTDIV;\n\n\tif (dm->support_ic_type == ODM_RTL8723D)\n\t\tdm->ant_div_type = S0S1_SW_ANTDIV;\n#elif (DM_ODM_SUPPORT_TYPE & (ODM_IOT))\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"IOT Config Antenna Diversity\\n\");\n\n\tif (dm->support_ic_type == ODM_RTL8721D)\n\t\tdm->ant_div_type = CG_TRX_HW_ANTDIV;\n\n#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"AP Config Antenna Diversity\\n\");\n\n\t/* @2 [ NOT_SUPPORT_ANTDIV ] */\n#if (defined(CONFIG_NOT_SUPPORT_ANTDIV))\n\tdm->support_ability &= ~(ODM_BB_ANT_DIV);\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\\n\");\n\n\t/* @2 [ 2G&5G_SUPPORT_ANTDIV ] */\n#elif (defined(CONFIG_2G5G_SUPPORT_ANTDIV))\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously\\n\");\n\tfat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G | ODM_ANTDIV_5G);\n\n\tif (dm->support_ic_type & ODM_ANTDIV_SUPPORT)\n\t\tdm->support_ability |= ODM_BB_ANT_DIV;\n\tif (*dm->band_type == ODM_BAND_5G) {\n#if (defined(CONFIG_5G_CGCS_RX_DIVERSITY))\n\t\tdm->ant_div_type = CGCS_RX_HW_ANTDIV;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\\n\");\n\t\tpanic_printk(\"[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\\n\");\n#elif (defined(CONFIG_5G_CG_TRX_DIVERSITY) ||\\\n\tdefined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))\n\t\tdm->ant_div_type = CG_TRX_HW_ANTDIV;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\\n\");\n\t\tpanic_printk(\"[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\\n\");\n#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))\n\t\tdm->ant_div_type = CG_TRX_SMART_ANTDIV;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ 5G] : AntDiv type = CG_SMART_ANTDIV\\n\");\n#elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY))\n\t\tdm->ant_div_type = S0S1_SW_ANTDIV;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ 5G] : AntDiv type = S0S1_SW_ANTDIV\\n\");\n#endif\n\t} else if (*dm->band_type == ODM_BAND_2_4G) {\n#if (defined(CONFIG_2G_CGCS_RX_DIVERSITY))\n\t\tdm->ant_div_type = CGCS_RX_HW_ANTDIV;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\\n\");\n#elif (defined(CONFIG_2G_CG_TRX_DIVERSITY) ||\\\n\tdefined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))\n\t\tdm->ant_div_type = CG_TRX_HW_ANTDIV;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\\n\");\n#elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))\n\t\tdm->ant_div_type = CG_TRX_SMART_ANTDIV;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\\n\");\n#elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY))\n\t\tdm->ant_div_type = S0S1_SW_ANTDIV;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\\n\");\n#endif\n\t}\n\n\t/* @2 [ 5G_SUPPORT_ANTDIV ] */\n#elif (defined(CONFIG_5G_SUPPORT_ANTDIV))\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[ Enable AntDiv function] : Only 5G Support Antenna Diversity\\n\");\n\tpanic_printk(\"[ Enable AntDiv function] : Only 5G Support Antenna Diversity\\n\");\n\tfat_tab->ant_div_2g_5g = (ODM_ANTDIV_5G);\n\tif (*dm->band_type == ODM_BAND_5G) {\n\t\tif (dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)\n\t\t\tdm->support_ability |= ODM_BB_ANT_DIV;\n#if (defined(CONFIG_5G_CGCS_RX_DIVERSITY))\n\t\tdm->ant_div_type = CGCS_RX_HW_ANTDIV;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\\n\");\n\t\tpanic_printk(\"[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\\n\");\n#elif (defined(CONFIG_5G_CG_TRX_DIVERSITY))\n\t\tdm->ant_div_type = CG_TRX_HW_ANTDIV;\n\t\tpanic_printk(\"[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\\n\");\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\\n\");\n#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))\n\t\tdm->ant_div_type = CG_TRX_SMART_ANTDIV;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ 5G] : AntDiv type = CG_SMART_ANTDIV\\n\");\n#elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY))\n\t\tdm->ant_div_type = S0S1_SW_ANTDIV;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ 5G] : AntDiv type = S0S1_SW_ANTDIV\\n\");\n#endif\n\t} else if (*dm->band_type == ODM_BAND_2_4G) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Not Support 2G ant_div_type\\n\");\n\t\tdm->support_ability &= ~(ODM_BB_ANT_DIV);\n\t}\n\n\t/* @2 [ 2G_SUPPORT_ANTDIV ] */\n#elif (defined(CONFIG_2G_SUPPORT_ANTDIV))\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\\n\");\n\tfat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G);\n\tif (*dm->band_type == ODM_BAND_2_4G) {\n\t\tif (dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)\n\t\t\tdm->support_ability |= ODM_BB_ANT_DIV;\n#if (defined(CONFIG_2G_CGCS_RX_DIVERSITY))\n\t\tdm->ant_div_type = CGCS_RX_HW_ANTDIV;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\\n\");\n#elif (defined(CONFIG_2G_CG_TRX_DIVERSITY))\n\t\tdm->ant_div_type = CG_TRX_HW_ANTDIV;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\\n\");\n#elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))\n\t\tdm->ant_div_type = CG_TRX_SMART_ANTDIV;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\\n\");\n#elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY))\n\t\tdm->ant_div_type = S0S1_SW_ANTDIV;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\\n\");\n#endif\n\t} else if (*dm->band_type == ODM_BAND_5G) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Not Support 5G ant_div_type\\n\");\n\t\tdm->support_ability &= ~(ODM_BB_ANT_DIV);\n\t}\n#endif\n#endif\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[AntDiv Config Info] AntDiv_SupportAbility = (( %x ))\\n\",\n\t\t  ((dm->support_ability & ODM_BB_ANT_DIV) ? 1 : 0));\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[AntDiv Config Info] be_fix_tx_ant = ((%d))\\n\",\n\t\t  dm->dm_fat_table.b_fix_tx_ant);\n}\n\nvoid odm_ant_div_timers(void *dm_void, u8 state)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tif (state == INIT_ANTDIV_TIMMER) {\n#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\t\todm_initialize_timer(dm,\n\t\t\t\t     &dm->dm_swat_table.sw_antdiv_timer,\n\t\t\t\t     (void *)odm_sw_antdiv_callback, NULL,\n\t\t\t\t     \"sw_antdiv_timer\");\n#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\\\n\t(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))\n\t\todm_initialize_timer(dm, &dm->fast_ant_training_timer,\n\t\t\t\t     (void *)odm_fast_ant_training_callback,\n\t\t\t\t     NULL, \"fast_ant_training_timer\");\n#endif\n\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\t\todm_initialize_timer(dm, &dm->evm_fast_ant_training_timer,\n\t\t\t\t     (void *)phydm_evm_antdiv_callback, NULL,\n\t\t\t\t     \"evm_fast_ant_training_timer\");\n#endif\n\t} else if (state == CANCEL_ANTDIV_TIMMER) {\n#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\t\todm_cancel_timer(dm,\n\t\t\t\t &dm->dm_swat_table.sw_antdiv_timer);\n#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\\\n\t(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))\n\t\todm_cancel_timer(dm, &dm->fast_ant_training_timer);\n#endif\n\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\t\todm_cancel_timer(dm, &dm->evm_fast_ant_training_timer);\n#endif\n\t} else if (state == RELEASE_ANTDIV_TIMMER) {\n#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\t\todm_release_timer(dm,\n\t\t\t\t  &dm->dm_swat_table.sw_antdiv_timer);\n#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\\\n\t(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))\n\t\todm_release_timer(dm, &dm->fast_ant_training_timer);\n#endif\n\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\t\todm_release_timer(dm, &dm->evm_fast_ant_training_timer);\n#endif\n\t}\n}\n\nvoid phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t\tchar *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct\t*fat_tab = &dm->dm_fat_table;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 dm_value[10] = {0};\n\tchar help[] = \"-h\";\n\tu8 i, input_idx = 0;\n\n\tfor (i = 0; i < 5; i++) {\n\t\tif (input[i + 1]) {\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);\n\t\t\tinput_idx++;\n\t\t}\n\t}\n\n\tif (input_idx == 0)\n\t\treturn;\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{1} {0:auto, 1:fix main, 2:fix auto}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{2} {antdiv_period}\\n\");\n\t\t#if (RTL8821C_SUPPORT == 1)\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{3} {en} {0:Default, 1:HW_Div, 2:SW_Div}\\n\");\n\t\t#endif\n\n\t} else if (dm_value[0] == 1) {\n\t/*@fixed or auto antenna*/\n\t\tif (dm_value[1] == 0) {\n\t\t\tdm->ant_type = ODM_AUTO_ANT;\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"AntDiv: Auto\\n\");\n\t\t} else if (dm_value[1] == 1) {\n\t\t\tdm->ant_type = ODM_FIX_MAIN_ANT;\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"AntDiv: Fix Main\\n\");\n\t\t} else if (dm_value[1] == 2) {\n\t\t\tdm->ant_type = ODM_FIX_AUX_ANT;\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"AntDiv: Fix Aux\\n\");\n\t\t}\n\n\t\tif (dm->ant_type != ODM_AUTO_ANT) {\n\t\t\todm_stop_antenna_switch_dm(dm);\n\t\t\tif (dm->ant_type == ODM_FIX_MAIN_ANT)\n\t\t\t\todm_update_rx_idle_ant(dm, MAIN_ANT);\n\t\t\telse if (dm->ant_type == ODM_FIX_AUX_ANT)\n\t\t\t\todm_update_rx_idle_ant(dm, AUX_ANT);\n\t\t} else {\n\t\t\tphydm_enable_antenna_diversity(dm);\n\t\t}\n\t\tdm->pre_ant_type = dm->ant_type;\n\t} else if (dm_value[0] == 2) {\n\t/*@dynamic period for AntDiv*/\n\t\tdm->antdiv_period = (u8)dm_value[1];\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"AntDiv_period=((%d))\\n\", dm->antdiv_period);\n\t}\n\t#if (RTL8821C_SUPPORT == 1)\n\telse if (dm_value[0] == 3 &&\n\t\t dm->support_ic_type == ODM_RTL8821C) {\n\t\t/*Only for 8821C*/\n\t\tif (dm_value[1] == 0) {\n\t\t\tfat_tab->force_antdiv_type = false;\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[8821C] AntDiv: Default\\n\");\n\t\t} else if (dm_value[1] == 1) {\n\t\t\tfat_tab->force_antdiv_type = true;\n\t\t\tfat_tab->antdiv_type_dbg = CG_TRX_HW_ANTDIV;\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[8821C] AntDiv: HW diversity\\n\");\n\t\t} else if (dm_value[1] == 2) {\n\t\t\tfat_tab->force_antdiv_type = true;\n\t\t\tfat_tab->antdiv_type_dbg = S0S1_SW_ANTDIV;\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[8821C] AntDiv: SW diversity\\n\");\n\t\t}\n\t}\n\t#endif\n\t#ifdef ODM_EVM_ENHANCE_ANTDIV\n\telse if (dm_value[0] == 4) {\n\t\tif (dm_value[1] == 0) {\n\t\t\t/*@init parameters for EVM AntDiv*/\n\t\t\tphydm_evm_sw_antdiv_init(dm);\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"init evm antdiv parameters\\n\");\n\t\t} else if (dm_value[1] == 1) {\n\t\t\t/*training number for EVM AntDiv*/\n\t\t\tdm->antdiv_train_num = (u8)dm_value[2];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"antdiv_train_num = ((%d))\\n\",\n\t\t\t\t dm->antdiv_train_num);\n\t\t} else if (dm_value[1] == 2) {\n\t\t\t/*training interval for EVM AntDiv*/\n\t\t\tdm->antdiv_intvl = (u8)dm_value[2];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"antdiv_intvl = ((%d))\\n\",\n\t\t\t\t dm->antdiv_intvl);\n\t\t} else if (dm_value[1] == 3) {\n\t\t\t/*@function period for EVM AntDiv*/\n\t\t\tdm->evm_antdiv_period = (u8)dm_value[2];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"evm_antdiv_period = ((%d))\\n\",\n\t\t\t\t dm->evm_antdiv_period);\n\t\t} else if (dm_value[1] == 100) {/*show parameters*/\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"ant_type = ((%d))\\n\", dm->ant_type);\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"antdiv_train_num = ((%d))\\n\",\n\t\t\t\t dm->antdiv_train_num);\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"antdiv_intvl = ((%d))\\n\",\n\t\t\t\t dm->antdiv_intvl);\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"evm_antdiv_period = ((%d))\\n\",\n\t\t\t\t dm->evm_antdiv_period);\n\t\t}\n\t}\n\t#ifdef CONFIG_2T4R_ANTENNA\n\telse if (dm_value[0] == 5) { /*Only for 8822B 2T4R case*/\n\n\t\tif (dm_value[1] == 0) {\n\t\t\tdm->ant_type2 = ODM_AUTO_ANT;\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"AntDiv: PathB Auto\\n\");\n\t\t} else if (dm_value[1] == 1) {\n\t\t\tdm->ant_type2 = ODM_FIX_MAIN_ANT;\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"AntDiv: PathB Fix Main\\n\");\n\t\t} else if (dm_value[1] == 2) {\n\t\t\tdm->ant_type2 = ODM_FIX_AUX_ANT;\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"AntDiv: PathB Fix Aux\\n\");\n\t\t}\n\n\t\tif (dm->ant_type2 != ODM_AUTO_ANT) {\n\t\t\todm_stop_antenna_switch_dm(dm);\n\t\t\tif (dm->ant_type2 == ODM_FIX_MAIN_ANT)\n\t\t\t\tphydm_update_rx_idle_ant_pathb(dm, MAIN_ANT);\n\t\t\telse if (dm->ant_type2 == ODM_FIX_AUX_ANT)\n\t\t\t\tphydm_update_rx_idle_ant_pathb(dm, AUX_ANT);\n\t\t} else {\n\t\t\tphydm_enable_antenna_diversity(dm);\n\t\t}\n\t\tdm->pre_ant_type2 = dm->ant_type2;\n\t}\n\t#endif\n\t#endif\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid odm_ant_div_reset(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\t#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\tif (dm->ant_div_type == S0S1_SW_ANTDIV)\n\t\todm_s0s1_sw_ant_div_reset(dm);\n\t#endif\n}\n\nvoid odm_antenna_diversity_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\todm_ant_div_config(dm);\n\todm_ant_div_init(dm);\n}\n\nvoid odm_antenna_diversity(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (*dm->mp_mode)\n\t\treturn;\n\n\tif (!(dm->support_ability & ODM_BB_ANT_DIV)) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[Return!!!]   Not Support Antenna Diversity Function\\n\");\n\t\treturn;\n\t}\n\n\tif (dm->pause_ability & ODM_BB_ANT_DIV) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Return: Pause AntDIv in LV=%d\\n\",\n\t\t\t  dm->pause_lv_table.lv_antdiv);\n\t\treturn;\n\t}\n\n\todm_ant_div(dm);\n}\n#endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/\n\n"
  },
  {
    "path": "hal/phydm/phydm_antdiv.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDMANTDIV_H__\n#define __PHYDMANTDIV_H__\n\n/*@#define ANTDIV_VERSION\t\"2.0\"  //2014.11.04*/\n/*@#define ANTDIV_VERSION\t\"2.1\"  //2015.01.13  Dino*/\n/*@#define ANTDIV_VERSION\t\"2.2\"  2015.01.16  Dino*/\n/*@#define ANTDIV_VERSION\t\"3.1\"  2015.07.29  YuChen,remove 92c 92d 8723a*/\n/*@#define ANTDIV_VERSION\t\"3.2\"  2015.08.11  Stanley, disable antenna*/\n\t\t\t\t/*@diversity when BT is enable for 8723B*/\n/*@#define ANTDIV_VERSION\t\"3.3\"  2015.08.12  Stanley. 8723B does not*/\n\t\t\t\t/*@need to check the antenna is control by BT,*/\n\t\t\t\t/*@because antenna diversity only works when */\n\t\t\t\t/*@BT is disable or radio off*/\n/*@#define ANTDIV_VERSION\t\"3.4\"  2015.08.28 Dino 1.Add 8821A Smart */\n\t\t\t\t/*@Antenna 2. Add 8188F SW S0S1 Antenna*/\n\t\t\t\t/*@Diversity*/\n/*@#define ANTDIV_VERSION\t\"3.5\"  2015.10.07 Stanley Always check antenna*/\n\t\t\t\t/*@detection result from BT-coex. for 8723B,*/\n\t\t\t\t/*@not from PHYDM*/\n/*@#define ANTDIV_VERSION\t\"3.6\"*/ /*@2015.11.16  Stanley  */\n/*@#define ANTDIV_VERSION\t\"3.7\"  2015.11.20 Dino Add SmartAnt FAT Patch */\n/*@#define ANTDIV_VERSION\t\"3.8\"  2015.12.21 Dino, Add SmartAnt dynamic*/\n\t\t\t\t/*@training packet num */\n/*@#define ANTDIV_VERSION\t\"3.9\"  2016.01.05 Dino, Add SmartAnt cmd for*/\n\t\t\t\t/*@converting single & two smtant, and add cmd*/\n\t\t\t\t/*@for adjust truth table */\n#define ANTDIV_VERSION \"4.0\"\t/*@2017.05.25  Mark, Add SW antenna diversity*/\n\t\t\t\t/*@for 8821c because HW transient issue */\n\n/* @1 ============================================================\n * 1  Definition\n * 1 ============================================================\n */\n\n#define\tANTDIV_INIT\t\t0xff\n#define\tMAIN_ANT\t1\t\t/*@ant A or ant Main   or S1*/\n#define\tAUX_ANT\t\t2\t\t/*@AntB or ant Aux   or S0*/\n#define\tMAX_ANT\t\t3\t\t/* @3 for AP using*/\n\n#define ANT1_2G 0\n/* @= ANT2_5G for 8723D  BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */\n#define ANT2_2G 1\n/* @= ANT1_5G for 8723D  BTG S0  RX S0S1 diversity for 8723D, TX fixed at S1 */\n/*smart antenna*/\n#define SUPPORT_RF_PATH_NUM 4\n#define SUPPORT_BEAM_PATTERN_NUM 4\n#define NUM_ANTENNA_8821A\t2\n\n#define SUPPORT_BEAM_SET_PATTERN_NUM\t\t16\n\n#define\tNO_FIX_TX_ANT\t\t0\n#define\tFIX_TX_AT_MAIN\t1\n#define\tFIX_AUX_AT_MAIN\t2\n\n/* @Antenna Diversty Control type */\n#define\tODM_AUTO_ANT\t\t0\n#define\tODM_FIX_MAIN_ANT\t1\n#define\tODM_FIX_AUX_ANT\t2\n\n#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\\\n\t\t\tODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A |\\\n\t\t\tODM_RTL8197F | ODM_RTL8721D)\n#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\\\n\t\t\tODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B)\n#define ODM_ANTDIV_SUPPORT\t(ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT)\n#define ODM_SMART_ANT_SUPPORT\t(ODM_RTL8188E | ODM_RTL8192E)\n#define ODM_HL_SMART_ANT_TYPE1_SUPPORT\t\t(ODM_RTL8821 | ODM_RTL8822B)\n\n#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\\\n\t\t\tODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D |\\\n\t\t\tODM_RTL8197F)\n#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\\\n\t\t\tODM_RTL8821C | ODM_RTL8822B)\n\n#define ODM_EVM_ANTDIV_IC (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8822B)\n\n#define ODM_ANTDIV_2G\tBIT(0)\n#define ODM_ANTDIV_5G\tBIT(1)\n\n#define ANTDIV_ON\t1\n#define ANTDIV_OFF\t0\n\n#define ANT_PATH_A\t0\n#define ANT_PATH_B\t1\n#define ANT_PATH_AB\t2\n\n#define FAT_ON\t1\n#define FAT_OFF\t0\n\n#define TX_BY_DESC\t1\n#define TX_BY_REG\t0\n\n#define RSSI_METHOD\t0\n#define EVM_METHOD\t\t1\n#define CRC32_METHOD\t2\n#define TP_METHOD\t\t3\n\n#define INIT_ANTDIV_TIMMER\t\t0\n#define CANCEL_ANTDIV_TIMMER\t1\n#define RELEASE_ANTDIV_TIMMER\t2\n\n#define CRC32_FAIL\t1\n#define CRC32_OK\t0\n\n#define evm_rssi_th_high\t25\n#define evm_rssi_th_low\t20\n\n#define NORMAL_STATE_MIAN\t1\n#define NORMAL_STATE_AUX\t2\n#define TRAINING_STATE\t\t3\n\n#define FORCE_RSSI_DIFF 10\n\n#define HT_IDX 16\n#define VHT_IDX 20\n\n#define CSI_ON\t1\n#define CSI_OFF\t0\n\n#define DIVON_CSIOFF 1\n#define DIVOFF_CSION 2\n\n#define BDC_DIV_TRAIN_STATE\t0\n#define bdc_bfer_train_state\t1\n#define BDC_DECISION_STATE\t\t2\n#define BDC_BF_HOLD_STATE\t\t3\n#define BDC_DIV_HOLD_STATE\t\t4\n\n#define BDC_MODE_1 1\n#define BDC_MODE_2 2\n#define BDC_MODE_3 3\n#define BDC_MODE_4 4\n#define BDC_MODE_NULL 0xff\n\n/*SW S0S1 antenna diversity*/\n#define SWAW_STEP_INIT\t\t\t0xff\n#define SWAW_STEP_PEEK\t\t0\n#define SWAW_STEP_DETERMINE\t1\n\n#define RSSI_CHECK_RESET_PERIOD\t10\n#define RSSI_CHECK_THRESHOLD\t\t50\n\n/*@Hong Lin Smart antenna*/\n#define HL_SMTANT_2WIRE_DATA_LEN 24\n\n#if (RTL8723D_SUPPORT == 1)\n\t#ifndef CONFIG_ANTDIV_PERIOD\n\t\t#define CONFIG_ANTDIV_PERIOD 1\n\t#endif\n#endif\n/* @1 ============================================================\n * 1  structure\n * 1 ============================================================\n */\n\n\nstruct sw_antenna_switch {\n\tu8\t\tdouble_chk_flag;\n\t/*@If current antenna RSSI > \"RSSI_CHECK_THRESHOLD\", than*/\n\t/*@check this antenna again*/\n\tu8\t\ttry_flag;\n\ts32\t\tpre_rssi;\n\tu8\t\tcur_antenna;\n\tu8\t\tpre_ant;\n\tu8\t\trssi_trying;\n\tu8\t\treset_idx;\n\tu8\t\ttrain_time;\n\tu8\t\ttrain_time_flag;\n\t/*@base on RSSI difference between two antennas*/\n\tstruct phydm_timer_list\tsw_antdiv_timer;\n\tu32\t\tpkt_cnt_sw_ant_div_by_ctrl_frame;\n\tboolean\t\tis_sw_ant_div_by_ctrl_frame;\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#if USE_WORKITEM\n\tRT_WORK_ITEM\tphydm_sw_antenna_switch_workitem;\n#endif\n#endif\n\n\t/* @AntDect (Before link Antenna Switch check) need to be moved*/\n\tu16\t\tsingle_ant_counter;\n\tu16\t\tdual_ant_counter;\n\tu16\t\taux_fail_detec_counter;\n\tu16\t\tretry_counter;\n\tu8\t\tswas_no_link_state;\n\tu32\t\tswas_no_link_bk_reg948;\n\tboolean\t\tANTA_ON;\t/*To indicate ant A is or not*/\n\tboolean\t\tANTB_ON;\t/*@To indicate ant B is on or not*/\n\tboolean\t\tpre_aux_fail_detec;\n\tboolean\t\trssi_ant_dect_result;\n\tu8\t\tant_5g;\n\tu8\t\tant_2g;\n};\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))\nstruct _BF_DIV_COEX_ {\n\tboolean w_bfer_client[ODM_ASSOCIATE_ENTRY_NUM];\n\tboolean w_bfee_client[ODM_ASSOCIATE_ENTRY_NUM];\n\tu32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM];\n\tu32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM];\n\n\tu8 bd_ccoex_type_wbfer;\n\tu8 num_txbfee_client;\n\tu8 num_txbfer_client;\n\tu8 bdc_try_counter;\n\tu8 bdc_hold_counter;\n\tu8 bdc_mode;\n\tu8 bdc_active_mode;\n\tu8 BDC_state;\n\tu8 bdc_rx_idle_update_counter;\n\tu8 num_client;\n\tu8 pre_num_client;\n\tu8 num_bf_tar;\n\tu8 num_div_tar;\n\n\tboolean is_all_div_sta_idle;\n\tboolean is_all_bf_sta_idle;\n\tboolean bdc_try_flag;\n\tboolean BF_pass;\n\tboolean DIV_pass;\n};\n#endif\n#endif\n\nstruct phydm_fat_struct {\n\tu8\tbssid[6];\n\tu8\tantsel_rx_keep_0;\n\tu8\tantsel_rx_keep_1;\n\tu8\tantsel_rx_keep_2;\n\tu8\tantsel_rx_keep_3;\n\tu32\tant_sum_rssi[7];\n\tu32\tant_rssi_cnt[7];\n\tu32\tant_ave_rssi[7];\n\tu8\tfat_state;\n\tu8\tfat_state_cnt;\n\tu32\ttrain_idx;\n\tu8\tantsel_a[ODM_ASSOCIATE_ENTRY_NUM];\n\tu8\tantsel_b[ODM_ASSOCIATE_ENTRY_NUM];\n\tu8\tantsel_c[ODM_ASSOCIATE_ENTRY_NUM];\n\tu16\tmain_ht_cnt[HT_IDX];\n\tu16\taux_ht_cnt[HT_IDX];\n\tu16\tmain_vht_cnt[VHT_IDX];\n\tu16\taux_vht_cnt[VHT_IDX];\n\tu16\tmain_sum[ODM_ASSOCIATE_ENTRY_NUM];\n\tu16\taux_sum[ODM_ASSOCIATE_ENTRY_NUM];\n\tu16\tmain_cnt[ODM_ASSOCIATE_ENTRY_NUM];\n\tu16\taux_cnt[ODM_ASSOCIATE_ENTRY_NUM];\n\tu16\tmain_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];\n\tu16\taux_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];\n\tu16\tmain_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];\n\tu16\taux_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];\n\tu8\trx_idle_ant;\n\tu8\trx_idle_ant2;\n\tu8\trvrt_val;\n\tu8\tant_div_on_off;\n\tu8\tdiv_path_type;\n\tboolean\tis_become_linked;\n\tboolean get_stats;\n\tu32\tmin_max_rssi;\n\tu8\tidx_ant_div_counter_2g;\n\tu8\tidx_ant_div_counter_5g;\n\tu8\tant_div_2g_5g;\n\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\t/*@For 1SS RX phy rate*/\n\tu32\tmain_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];\n\tu32\taux_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];\n\tu32\tmain_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];\n\tu32\taux_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];\n\n\t/*@For 2SS RX phy rate*/\n\tu32\tmain_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];/*@2SS with A1+B*/\n\tu32\taux_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];/*@2SS with A2+B*/\n\tu32\tmain_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];\n\tu32\taux_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];\n\n\tboolean\tevm_method_enable;\n\tu8\ttarget_ant_evm;\n\tu8\ttarget_ant_crc32;\n\tu8\ttarget_ant_tp;\n\tu8\ttarget_ant_enhance;\n\tu8\tpre_target_ant_enhance;\n\tu16\tmain_mpdu_ok_cnt;\n\tu16\taux_mpdu_ok_cnt;\n\n\tu32\tcrc32_ok_cnt;\n\tu32\tcrc32_fail_cnt;\n\tu32\tmain_crc32_ok_cnt;\n\tu32\taux_crc32_ok_cnt;\n\tu32\tmain_crc32_fail_cnt;\n\tu32\taux_crc32_fail_cnt;\n\n\tu32\tmain_tp;\n\tu32\taux_tp;\n\tu32\tmain_tp_cnt;\n\tu32\taux_tp_cnt;\n\n\tu8\tpre_antdiv_rssi;\n\tu8\tpre_antdiv_tp;\n#endif\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\tu32    cck_ctrl_frame_cnt_main;\n\tu32    cck_ctrl_frame_cnt_aux;\n\tu32    ofdm_ctrl_frame_cnt_main;\n\tu32    ofdm_ctrl_frame_cnt_aux;\n\tu32\tmain_ctrl_sum;\n\tu32\taux_ctrl_sum;\n\tu32\tmain_ctrl_cnt;\n\tu32\taux_ctrl_cnt;\n#endif\n\tu8\tb_fix_tx_ant;\n\tboolean\tfix_ant_bfee;\n\tboolean\tenable_ctrl_frame_antdiv;\n\tboolean\tuse_ctrl_frame_antdiv;\n\tboolean\t*is_no_csi_feedback;\n\tboolean\tforce_antdiv_type;\n\tu8\tantdiv_type_dbg;\n\tu8\thw_antsw_occur;\n\tu8\t*p_force_tx_by_desc;\n\tu8\tforce_tx_by_desc;\n\t/*@A temp value, will hook to driver team's outer parameter later*/\n\tu8\t*p_default_s0_s1;\n\tu8\tdefault_s0_s1;\n};\n\n/* @1 ============================================================\n * 1  enumeration\n * 1 ============================================================\n */\n\nenum fat_state /*@Fast antenna training*/\n{\n\tFAT_BEFORE_LINK_STATE\t= 0,\n\tFAT_PREPARE_STATE\t\t\t= 1,\n\tFAT_TRAINING_STATE\t\t= 2,\n\tFAT_DECISION_STATE\t\t= 3\n};\n\nenum ant_div_type {\n\tNO_ANTDIV\t\t\t= 0xFF,\n\tCG_TRX_HW_ANTDIV\t\t\t= 0x01,\n\tCGCS_RX_HW_ANTDIV\t\t= 0x02,\n\tFIXED_HW_ANTDIV\t\t= 0x03,\n\tCG_TRX_SMART_ANTDIV\t= 0x04,\n\tCGCS_RX_SW_ANTDIV\t= 0x05,\n\tS0S1_SW_ANTDIV\t= 0x06, /*@8723B intrnal switch S0 S1*/\n\tS0S1_TRX_HW_ANTDIV\t= 0x07, /*TRX S0S1 diversity for 8723D*/\n\tHL_SW_SMART_ANT_TYPE1\t= 0x10,\n\t/*@Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys,*/\n\t/*@and each ant. is equipped with 4 antenna patterns*/\n\tHL_SW_SMART_ANT_TYPE2\t= 0x11\n\t/*@Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/\n};\n\n/* @1 ============================================================\n * 1  function prototype\n * 1 ============================================================\n */\n\nvoid odm_stop_antenna_switch_dm(void *dm_void);\n\nvoid phydm_enable_antenna_diversity(void *dm_void);\n\nvoid odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C,....*/\n\t\t\t);\n\n#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link\n\nvoid odm_sw_ant_div_rest_after_link(void *dm_void);\n\nvoid odm_ant_div_on_off(void *dm_void, u8 swch, u8 path);\n\nvoid odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch);\n\n#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))\n\nvoid phydm_antdiv_reset_statistic(void *dm_void, u32 macid);\n\nvoid odm_update_rx_idle_ant(void *dm_void, u8 ant);\n\nvoid phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant);\n\nvoid phydm_set_antdiv_val(void *dm_void, u32 *val_buf,\tu8 val_len);\n\n#if (RTL8723B_SUPPORT == 1)\nvoid odm_update_rx_idle_ant_8723b(void *dm_void, u8 ant, u32 default_ant,\n\t\t\t\t  u32 optional_ant);\n#endif\n\n#if (RTL8188F_SUPPORT == 1)\nvoid phydm_update_rx_idle_antenna_8188F(void *dm_void,\tu32 default_ant);\n#endif\n\n#if (RTL8723D_SUPPORT == 1)\n\nvoid phydm_set_tx_ant_pwr_8723d(void *dm_void, u8 ant);\n\nvoid odm_update_rx_idle_ant_8723d(void *dm_void, u8 ant, u32 default_ant,\n\t\t\t\t  u32 optional_ant);\n\n#endif\n\n#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid odm_sw_antdiv_callback(struct phydm_timer_list *timer);\n\nvoid odm_sw_antdiv_workitem_callback(void *context);\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\nvoid odm_sw_antdiv_workitem_callback(void *context);\n\nvoid odm_sw_antdiv_callback(void *function_context);\n\n#endif\n\nvoid odm_s0s1_sw_ant_div_by_ctrl_frame(void *dm_void, u8 step);\n\nvoid odm_antsel_statistics_ctrl(void *dm_void,\tu8 antsel_tr_mux,\n\t\t\t\tu32 rx_pwdb_all);\n\nvoid odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void *dm_void,\n\t\t\t\t\t\t    void *phy_info_void,\n\t\t\t\t\t\t    void *pkt_info_void);\n\n#endif\n\n#ifdef ODM_EVM_ENHANCE_ANTDIV\nvoid phydm_evm_sw_antdiv_init(void *dm_void);\n\nvoid phydm_rx_rate_for_antdiv(void *dm_void, void *pkt_info_void);\n\nvoid phydm_antdiv_reset_rx_rate(void *dm_void);\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid phydm_evm_antdiv_callback(struct phydm_timer_list *timer);\n\nvoid phydm_evm_antdiv_workitem_callback(void *context);\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\nvoid phydm_evm_antdiv_callback(void *dm_void);\n\nvoid phydm_evm_antdiv_workitem_callback(void *context);\n\n#else\nvoid phydm_evm_antdiv_callback(void *dm_void);\n#endif\n\n#endif\n\nvoid odm_hw_ant_div(void *dm_void);\n\n#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\\\n\t(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))\nvoid odm_fast_ant_training(\n\tvoid *dm_void);\n\nvoid odm_fast_ant_training_callback(void *dm_void);\n\nvoid odm_fast_ant_training_work_item_callback(void *dm_void);\n#endif\n\nvoid odm_ant_div_init(void *dm_void);\n\nvoid odm_ant_div(void *dm_void);\n\nvoid odm_antsel_statistics(void *dm_void, void *phy_info_void,\n\t\t\t   u8 antsel_tr_mux, u32 mac_id, u32 utility, u8 method,\n\t\t\t   u8 is_cck_rate);\n\nvoid odm_process_rssi_for_ant_div(void *dm_void, void *phy_info_void,\n\t\t\t\t  void *pkt_info_void);\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\nvoid odm_set_tx_ant_by_tx_info(void *dm_void,\t u8 *desc, u8 mac_id);\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\nstruct tx_desc;\n/*@declared tx_desc here or compile error happened when enabled 8822B*/\n\nvoid odm_set_tx_ant_by_tx_info(struct rtl8192cd_priv *priv,\n\t\t\t       struct tx_desc *pdesc, unsigned short aid);\n\n#if 1 /*@def def CONFIG_WLAN_HAL*/\nvoid odm_set_tx_ant_by_tx_info_hal(struct rtl8192cd_priv *priv,\n\t\t\t\t   void *pdesc_data, u16 aid);\n#endif /*@#ifdef CONFIG_WLAN_HAL*/\n#endif\n\nvoid odm_ant_div_config(void *dm_void);\n\nvoid odm_ant_div_timers(void *dm_void, u8 state);\n\nvoid phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t\tchar *output, u32 *_out_len);\n\nvoid odm_ant_div_reset(void *dm_void);\n\nvoid odm_antenna_diversity_init(void *dm_void);\n\nvoid odm_antenna_diversity(void *dm_void);\n#endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/\n#endif /*@#ifndef\t__ODMANTDIV_H__*/\n"
  },
  {
    "path": "hal/phydm/phydm_api.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n * ************************************************************\n */\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\nvoid phydm_reset_bb_hw_cnt(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\t/*@ Reset all counter when 1 */\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\todm_set_bb_reg(dm, R_0x1eb4, BIT(25), 1);\n\t\todm_set_bb_reg(dm, R_0x1eb4, BIT(25), 0);\n\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\t/*@ Reset all counter when 1 (including PMAC and PHY)*/\n\t\t/* Reset Page F counter*/\n\t\todm_set_bb_reg(dm, R_0xb58, BIT(0), 1);\n\t\todm_set_bb_reg(dm, R_0xb58, BIT(0), 0);\n\t} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\todm_set_bb_reg(dm, R_0xf14, BIT(16), 0x1);\n\t\todm_set_bb_reg(dm, R_0xf14, BIT(16), 0x0);\n\t}\n}\n\nvoid phydm_dynamic_ant_weighting(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#ifdef DYN_ANT_WEIGHTING_SUPPORT\n\t#if (RTL8197F_SUPPORT)\n\tif (dm->support_ic_type & (ODM_RTL8197F))\n\t\tphydm_dynamic_ant_weighting_8197f(dm);\n\t#endif\n\n\t#if (RTL8812A_SUPPORT)\n\tif (dm->support_ic_type & (ODM_RTL8812)) {\n\t\tphydm_dynamic_ant_weighting_8812a(dm);\n\t}\n\t#endif\n\n\t#if (RTL8822B_SUPPORT)\n\tif (dm->support_ic_type & (ODM_RTL8822B))\n\t\tphydm_dynamic_ant_weighting_8822b(dm);\n\t#endif\n#endif\n}\n\n#ifdef DYN_ANT_WEIGHTING_SUPPORT\nvoid phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used,\n\t\t\t  char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tchar help[] = \"-h\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"echo dis_dym_ant_weighting {0/1}\\n\");\n\n\t} else {\n\t\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);\n\n\t\tif (var1[0] == 1) {\n\t\t\tdm->is_disable_dym_ant_weighting = 1;\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"Disable dyn-ant-weighting\\n\");\n\t\t} else {\n\t\t\tdm->is_disable_dym_ant_weighting = 0;\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"Enable dyn-ant-weighting\\n\");\n\t\t}\n\t}\n\t*_used = used;\n\t*_out_len = out_len;\n}\n#endif\n\nvoid phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 rx_ant = 0, tx_ant = 0;\n\tu8 path_bitmap = 1;\n\n\tpath_bitmap = (u8)phydm_gen_bitmask(num_rf_path);\n#if 0\n\t/*PHYDM_DBG(dm, ODM_COMP_INIT, \"path_bitmap=0x%x\\n\", path_bitmap);*/\n#endif\n\n\tdm->tx_ant_status = path_bitmap;\n\tdm->rx_ant_status = path_bitmap;\n\n\tif (num_rf_path == PDM_1SS)\n\t\treturn;\n\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tif (dm->support_ic_type &\n\t\t   (ODM_RTL8192F | ODM_RTL8192E | ODM_RTL8197F)) {\n\t\tdm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0xc04, 0x3);\n\t\tdm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x90c, 0x3);\n\t} else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8814A)) {\n\t\tdm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0x808, 0xf);\n\t\tdm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x80c, 0xf);\n\t}\n\t#endif\n\t#if (defined(PHYDM_IC_JGR3_SERIES_SUPPORT))\n\tif (dm->support_ic_type &\n\t    (ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8822C)) {\n\t\tdm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0x824, 0xf0000);\n\t\tdm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x820, 0xf);\n\t}\n\t#endif\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"[%s]ant_status{tx,rx}={0x%x, 0x%x}\\n\",\n\t\t  __func__, dm->tx_ant_status, dm->rx_ant_status);\n}\n\nvoid phydm_config_ofdm_tx_path(void *dm_void, u32 path)\n{\n#if (RTL8192E_SUPPORT || RTL8812A_SUPPORT)\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 ofdm_tx_path = 0x33;\n\n\tif (dm->num_rf_path == PDM_1SS)\n\t\treturn;\n\n\tswitch (dm->support_ic_type) {\n\t#if (RTL8192E_SUPPORT)\n\tcase ODM_RTL8192E:\n\t\tif (path == BB_PATH_A)\n\t\t\todm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121111);\n\t\telse if (path == BB_PATH_B)\n\t\t\todm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x82221222);\n\t\telse if (path == BB_PATH_AB)\n\t\t\todm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333);\n\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8812A_SUPPORT)\n\tcase ODM_RTL8812:\n\t\tif (path == BB_PATH_A)\n\t\t\tofdm_tx_path = 0x11;\n\t\telse if (path == BB_PATH_B)\n\t\t\tofdm_tx_path = 0x22;\n\t\telse if (path == BB_PATH_AB)\n\t\t\tofdm_tx_path = 0x33;\n\n\t\todm_set_bb_reg(dm, R_0x80c, 0xff00, ofdm_tx_path);\n\n\t\tbreak;\n\t#endif\n\n\tdefault:\n\t\tbreak;\n\t}\n#endif\n}\n\nvoid phydm_config_ofdm_rx_path(void *dm_void, u32 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 val = 0;\n\n\tif (dm->support_ic_type & (ODM_RTL8192E)) {\n#if (RTL8192E_SUPPORT)\n\t\tif (path == BB_PATH_A)\n\t\t\tval = 1;\n\t\telse if (path == BB_PATH_B)\n\t\t\tval = 2;\n\t\telse if (path == BB_PATH_AB)\n\t\t\tval = 3;\n\n\t\todm_set_bb_reg(dm, R_0xc04, 0xff, ((val << 4) | val));\n\t\todm_set_bb_reg(dm, R_0xd04, 0xf, val);\n#endif\n\t}\n#if (RTL8812A_SUPPORT || RTL8822B_SUPPORT)\n\telse if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) {\n\t\tif (path == BB_PATH_A)\n\t\t\tval = 1;\n\t\telse if (path == BB_PATH_B)\n\t\t\tval = 2;\n\t\telse if (path == BB_PATH_AB)\n\t\t\tval = 3;\n\n\t\todm_set_bb_reg(dm, R_0x808, MASKBYTE0, ((val << 4) | val));\n\t}\n#endif\n}\n\nvoid phydm_config_cck_rx_antenna_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tif (dm->support_ic_type & ODM_IC_1SS)\n\t\treturn;\n\n\t/*@CCK 2R CCA parameters*/\n\todm_set_bb_reg(dm, R_0xa00, BIT(15), 0x0); /*@Disable Ant diversity*/\n\todm_set_bb_reg(dm, R_0xa70, BIT(7), 0); /*@Concurrent CCA at LSB & USB*/\n\todm_set_bb_reg(dm, R_0xa74, BIT(8), 0); /*RX path diversity enable*/\n\todm_set_bb_reg(dm, R_0xa14, BIT(7), 0); /*r_en_mrc_antsel*/\n\todm_set_bb_reg(dm, R_0xa20, (BIT(5) | BIT(4)), 1); /*@MBC weighting*/\n\n\tif (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F))\n\t\todm_set_bb_reg(dm, R_0xa08, BIT(28), 1); /*r_cck_2nd_sel_eco*/\n\telse if (dm->support_ic_type & ODM_RTL8814A)\n\t\todm_set_bb_reg(dm, R_0xa84, BIT(28), 1); /*@2R CCA only*/\n#endif\n}\n\nvoid phydm_config_cck_rx_path(void *dm_void, enum bb_path path)\n{\n#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 path_div_select = 0;\n\tu8 cck_path[2] = {0};\n\tu8 en_2R_path = 0;\n\tu8 en_2R_mrc = 0;\n\tu8 i = 0, j = 0;\n\tu8 num_enable_path = 0;\n\tu8 cck_mrc_max_path = 2;\n\n\tif (dm->support_ic_type & ODM_IC_1SS)\n\t\treturn;\n\n\tfor (i = 0; i < 4; i++) {\n\t\tif (path & BIT(i)) { /*@ex: PHYDM_ABCD*/\n\t\t\tnum_enable_path++;\n\t\t\tcck_path[j] = i;\n\t\t\tj++;\n\t\t}\n\t\tif (num_enable_path >= cck_mrc_max_path)\n\t\t\tbreak;\n\t}\n\n\tif (num_enable_path > 1) {\n\t\tpath_div_select = 1;\n\t\ten_2R_path = 1;\n\t\ten_2R_mrc = 1;\n\t} else {\n\t\tpath_div_select = 0;\n\t\ten_2R_path = 0;\n\t\ten_2R_mrc = 0;\n\t}\n\t/*@CCK_1 input signal path*/\n\todm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), cck_path[0]);\n\t/*@CCK_2 input signal path*/\n\todm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), cck_path[1]);\n\t/*@enable Rx path diversity*/\n\todm_set_bb_reg(dm, R_0xa74, BIT(8), path_div_select);\n\t/*@enable 2R Rx path*/\n\todm_set_bb_reg(dm, R_0xa2c, BIT(18), en_2R_path);\n\t/*@enable 2R MRC*/\n\todm_set_bb_reg(dm, R_0xa2c, BIT(22), en_2R_mrc);\n\tif (dm->support_ic_type & ODM_RTL8192F) {\n\t\tif (path == BB_PATH_A) {\n\t\t\todm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);\n\t\t\todm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 0);\n\t\t\todm_set_bb_reg(dm, R_0xa74, BIT(8), 0);\n\t\t\todm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0);\n\t\t\todm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0);\n\t\t} else if (path == BB_PATH_B) {/*@for DC cancellation*/\n\t\t\todm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 1);\n\t\t\todm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);\n\t\t\todm_set_bb_reg(dm, R_0xa74, BIT(8), 0);\n\t\t\todm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0);\n\t\t\todm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0);\n\t\t} else if (path == BB_PATH_AB) {\n\t\t\todm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);\n\t\t\todm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);\n\t\t\todm_set_bb_reg(dm, R_0xa74, BIT(8), 1);\n\t\t\todm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 1);\n\t\t\todm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 1);\n\t\t}\n\t} else if (dm->support_ic_type & ODM_RTL8822B) {\n\t\tif (path == BB_PATH_A) {\n\t\t\todm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);\n\t\t\todm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 0);\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 1);\n\t\t\todm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);\n\t\t}\n\t}\n\n#endif\n}\n\nvoid phydm_config_cck_tx_path(void *dm_void, enum bb_path path)\n{\n#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (path == BB_PATH_A)\n\t\todm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x8);\n\telse if (path == BB_PATH_B)\n\t\todm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x4);\n\telse if (path == BB_PATH_AB)\n\t\todm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0xc);\n#endif\n}\n\nvoid phydm_config_trx_path_v2(void *dm_void, char input[][16], u32 *_used,\n\t\t\t      char *output, u32 *_out_len)\n{\n#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\\\n\tRTL8822C_SUPPORT || RTL8814B_SUPPORT)\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 val[10] = {0};\n\tchar help[] = \"-h\";\n\tu8 i = 0, input_idx = 0;\n\tenum bb_path tx_path, rx_path, tx_path_ctrl;\n\tboolean dbg_mode_en;\n\n\tif (!(dm->support_ic_type &\n\t    (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8822C |\n\t     ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8197G)))\n\t\treturn;\n\n\tfor (i = 0; i < 5; i++) {\n\t\tif (input[i + 1]) {\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);\n\t\t\tinput_idx++;\n\t\t}\n\t}\n\n\tif (input_idx == 0)\n\t\treturn;\n\n\tdbg_mode_en = (boolean)val[0];\n\ttx_path = (enum bb_path)val[1];\n\trx_path = (enum bb_path)val[2];\n\ttx_path_ctrl = (enum bb_path)val[3];\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tif (dm->support_ic_type & ODM_RTL8822C) {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"{en} {tx_path} {rx_path} {ff:auto, else:1ss_tx_path}\\n\"\n\t\t\t\t );\n\t\t} else {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"{en} {tx_path} {rx_path} {is_tx_2_path}\\n\");\n\t\t}\n\n\t} else if (dbg_mode_en) {\n\t\tdm->is_disable_phy_api = false;\n\t\tphydm_api_trx_mode(dm, tx_path, rx_path, tx_path_ctrl);\n\t\tdm->is_disable_phy_api = true;\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"T/RX path = 0x%x/0x%x, tx_path_ctrl=%d\\n\",\n\t\t\t tx_path, rx_path, tx_path_ctrl);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"T/RX path_en={0x%x, 0x%x}, tx_1ss=%d\\n\",\n\t\t\t dm->tx_ant_status, dm->rx_ant_status,\n\t\t\t dm->tx_1ss_status);\n\t} else {\n\t\tdm->is_disable_phy_api = false;\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Disable API debug mode\\n\");\n\t}\n#endif\n}\n\nvoid phydm_config_trx_path_v1(void *dm_void, char input[][16], u32 *_used,\n\t\t\t      char *output, u32 *_out_len)\n{\n#if (RTL8192E_SUPPORT || RTL8812A_SUPPORT)\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 val[10] = {0};\n\tchar help[] = \"-h\";\n\tu8 i = 0, input_idx = 0;\n\n\tif (!(dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)))\n\t\treturn;\n\n\tfor (i = 0; i < 5; i++) {\n\t\tif (input[i + 1]) {\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);\n\t\t\tinput_idx++;\n\t\t}\n\t}\n\n\tif (input_idx == 0)\n\t\treturn;\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{0:CCK, 1:OFDM} {1:TX, 2:RX} {1:path_A, 2:path_B, 3:path_AB}\\n\");\n\n\t\t*_used = used;\n\t\t*_out_len = out_len;\n\t\treturn;\n\n\t} else if (val[0] == 0) {\n\t/* @CCK */\n\t\tif (val[1] == 1) { /*TX*/\n\t\t\tif (val[2] == 1)\n\t\t\t\tphydm_config_cck_tx_path(dm, BB_PATH_A);\n\t\t\telse if (val[2] == 2)\n\t\t\t\tphydm_config_cck_tx_path(dm, BB_PATH_B);\n\t\t\telse if (val[2] == 3)\n\t\t\t\tphydm_config_cck_tx_path(dm, BB_PATH_AB);\n\t\t} else if (val[1] == 2) { /*RX*/\n\n\t\t\tphydm_config_cck_rx_antenna_init(dm);\n\n\t\t\tif (val[2] == 1)\n\t\t\t\tphydm_config_cck_rx_path(dm, BB_PATH_A);\n\t\t\telse if (val[2] == 2)\n\t\t\t\tphydm_config_cck_rx_path(dm, BB_PATH_B);\n\t\t\telse if (val[2] == 3)\n\t\t\t\tphydm_config_cck_rx_path(dm, BB_PATH_AB);\n\t\t\t}\n\t\t}\n\t/* OFDM */\n\telse if (val[0] == 1) {\n\t\tif (val[1] == 1) /*TX*/\n\t\t\tphydm_config_ofdm_tx_path(dm, val[2]);\n\t\telse if (val[1] == 2) /*RX*/\n\t\t\tphydm_config_ofdm_rx_path(dm, val[2]);\n\t}\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"PHYDM Set path [%s] [%s] = [%s%s%s%s]\\n\",\n\t\t (val[0] == 1) ? \"OFDM\" : \"CCK\",\n\t\t (val[1] == 1) ? \"TX\" : \"RX\",\n\t\t (val[2] & 0x1) ? \"A\" : \"\", (val[2] & 0x2) ? \"B\" : \"\",\n\t\t (val[2] & 0x4) ? \"C\" : \"\",\n\t\t (val[2] & 0x8) ? \"D\" : \"\");\n\n\t*_used = used;\n\t*_out_len = out_len;\n#endif\n}\n\nvoid phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used,\n\t\t\t   char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) {\n\t\t#if (RTL8192E_SUPPORT || RTL8812A_SUPPORT)\n\t\tphydm_config_trx_path_v1(dm, input, _used, output, _out_len);\n\t\t#endif\n\t} else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F |\n\t\t   ODM_RTL8192F | ODM_RTL8822C | ODM_RTL8812F |\n\t\t   ODM_RTL8197G | ODM_RTL8814B)) {\n\t\t#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT ||\\\n\t\t     RTL8192F_SUPPORT || RTL8822C_SUPPORT ||\\\n\t\t     RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\\\n\t\t     RTL8197G_SUPPORT)\n\t\tphydm_config_trx_path_v2(dm, input, _used, output, _out_len);\n\t\t#endif\n\t}\n}\n\nvoid phydm_tx_2path(void *dm_void)\n{\n#if (defined(PHYDM_COMPILE_IC_2SS))\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tenum bb_path rx_path = (enum bb_path)dm->rx_ant_status;\n\n\tPHYDM_DBG(dm, ODM_COMP_API, \"%s ======>\\n\", __func__);\n\n\n\tif (!(dm->support_ic_type & ODM_IC_2SS))\n\t\treturn;\n\n\t#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8197F_SUPPORT ||\\\n\t     RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)\n\tif (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F |\n\t    ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G))\n\t\tphydm_api_trx_mode(dm, BB_PATH_AB, rx_path, BB_PATH_AB);\n\t#endif\n\n\t#if (RTL8812A_SUPPORT || RTL8192E_SUPPORT)\n\tif (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) {\n\t\tphydm_config_cck_tx_path(dm, BB_PATH_AB);\n\t\tphydm_config_ofdm_tx_path(dm, BB_PATH_AB);\n\t}\n\t#endif\n#endif\n}\n\nvoid phydm_stop_3_wire(void *dm_void, u8 set_type)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (set_type == PHYDM_SET) {\n\t\t/*@[Stop 3-wires]*/\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t\todm_set_bb_reg(dm, R_0x180c, 0x3, 0x0);\n\t\t\todm_set_bb_reg(dm, R_0x180c, BIT(28), 0x1);\n\n\t\t\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\t\t\tif (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {\n\t\t\t\todm_set_bb_reg(dm, R_0x410c, 0x3, 0x0);\n\t\t\t\todm_set_bb_reg(dm, R_0x410c, BIT(28), 0x1);\n\t\t\t}\n\t\t\t#endif\n\n\t\t\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\t\t\tif (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {\n\t\t\t\todm_set_bb_reg(dm, R_0x520c, 0x3, 0x0);\n\t\t\t\todm_set_bb_reg(dm, R_0x520c, BIT(28), 0x1);\n\t\t\t\todm_set_bb_reg(dm, R_0x530c, 0x3, 0x0);\n\t\t\t\todm_set_bb_reg(dm, R_0x530c, BIT(28), 0x1);\n\t\t\t}\n\t\t\t#endif\n\t\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\t\todm_set_bb_reg(dm, R_0xc00, 0xf, 0x4);\n\t\t\todm_set_bb_reg(dm, R_0xe00, 0xf, 0x4);\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0x88c, 0xf00000, 0xf);\n\t\t}\n\n\t} else { /*@if (set_type == PHYDM_REVERT)*/\n\n\t\t/*@[Start 3-wires]*/\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t\todm_set_bb_reg(dm, R_0x180c, 0x3, 0x3);\n\t\t\todm_set_bb_reg(dm, R_0x180c, BIT(28), 0x1);\n\n\t\t\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\t\t\tif (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {\n\t\t\t\todm_set_bb_reg(dm, R_0x410c, 0x3, 0x3);\n\t\t\t\todm_set_bb_reg(dm, R_0x410c, BIT(28), 0x1);\n\t\t\t}\n\t\t\t#endif\n\n\t\t\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\t\t\tif (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {\n\t\t\t\todm_set_bb_reg(dm, R_0x520c, 0x3, 0x3);\n\t\t\t\todm_set_bb_reg(dm, R_0x520c, BIT(28), 0x1);\n\t\t\t\todm_set_bb_reg(dm, R_0x530c, 0x3, 0x3);\n\t\t\t\todm_set_bb_reg(dm, R_0x530c, BIT(28), 0x1);\n\t\t\t}\n\t\t\t#endif\n\t\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\t\todm_set_bb_reg(dm, R_0xc00, 0xf, 0x7);\n\t\t\todm_set_bb_reg(dm, R_0xe00, 0xf, 0x7);\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0x88c, 0xf00000, 0x0);\n\t\t}\n\t}\n}\n\nu8 phydm_stop_ic_trx(void *dm_void, u8 set_type)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_api_stuc *api = &dm->api_table;\n\tu32 i = 0;\n\tu8 trx_idle_success = false;\n\tu32 dbg_port_value = 0;\n\n\tif (set_type == PHYDM_SET) {\n\t/*@[Stop TRX]---------------------------------------------------------*/\n\t\t/*set debug port to 0x0*/\n\t\tif (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0x0))\n\t\t\treturn PHYDM_SET_FAIL;\n\n\t\tfor (i = 0; i < 100; i++) {\n\t\t\tdbg_port_value = phydm_get_bb_dbg_port_val(dm);\n\n\t\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t\t\t/* BB idle */\n\t\t\t\tif ((dbg_port_value & 0x1FFEFF3F) == 0 &&\n\t\t\t\t    (dbg_port_value & 0xC0010000) ==\n\t\t\t\t    0xC0010000) {\n\t\t\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t\t\t  \"Stop trx wait for (%d) times\\n\",\n\t\t\t\t\t\t  i);\n\n\t\t\t\t\ttrx_idle_success = true;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\t/* PHYTXON && CCA_all */\n\t\t\t\tif (dm->support_ic_type == ODM_RTL8721D) {\n\t\t\t\t\tif ((dbg_port_value &\n\t\t\t\t\t    (BIT(20) | BIT(15))) == 0) {\n\t\t\t\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t\t\t\t  \"Stop trx wait for (%d) times\\n\",\n\t\t\t\t\t\t\t  i);\n\n\t\t\t\t\t\ttrx_idle_success = true;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tif ((dbg_port_value &\n\t\t\t\t\t    (BIT(17) | BIT(3))) == 0) {\n\t\t\t\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t\t\t\t  \"Stop trx wait for (%d) times\\n\",\n\t\t\t\t\t\t\t  i);\n\n\t\t\t\t\t\ttrx_idle_success = true;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tODM_delay_ms(1);\n\t\t}\n\t\tphydm_release_bb_dbg_port(dm);\n\n\t\tif (trx_idle_success) {\n\t\t\tapi->tx_queue_bitmap = odm_read_1byte(dm, R_0x522);\n\n\t\t\t/*pause all TX queue*/\n\t\t\todm_set_mac_reg(dm, R_0x520, 0xff0000, 0xff);\n\n\t\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t\t\t/*@disable OFDM RX CCA*/\n\t\t\t\todm_set_bb_reg(dm, R_0x1c68, BIT(24), 1);\n\t\t\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\t\t\t/*@disable OFDM RX CCA*/\n\t\t\t\todm_set_bb_reg(dm, R_0x838, BIT(1), 1);\n\t\t\t} else {\n\t\t\t\tapi->rxiqc_reg1 = odm_read_4byte(dm, R_0xc14);\n\t\t\t\tapi->rxiqc_reg2 = odm_read_4byte(dm, R_0xc1c);\n\t\t\t\t/* @[ Set IQK Matrix = 0 ]\n\t\t\t\t * equivalent to [ Turn off CCA]\n\t\t\t\t */\n\t\t\t\todm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0);\n\t\t\t\todm_set_bb_reg(dm, R_0xc1c, MASKDWORD, 0x0);\n\t\t\t}\n\t\t\tphydm_dis_cck_trx(dm, PHYDM_SET);\n\t\t} else {\n\t\t\treturn PHYDM_SET_FAIL;\n\t\t}\n\n\t\treturn PHYDM_SET_SUCCESS;\n\n\t} else { /*@if (set_type == PHYDM_REVERT)*/\n\t\t/*Release all TX queue*/\n\t\todm_write_1byte(dm, R_0x522, api->tx_queue_bitmap);\n\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t\t/*@enable OFDM RX CCA*/\n\t\t\todm_set_bb_reg(dm, R_0x1c68, BIT(24), 0);\n\t\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\t\t/*@enable OFDM RX CCA*/\n\t\t\todm_set_bb_reg(dm, R_0x838, BIT(1), 0);\n\t\t} else {\n\t\t\t/* @[Set IQK Matrix = 0] equivalent to [ Turn off CCA]*/\n\t\t\todm_write_4byte(dm, R_0xc14, api->rxiqc_reg1);\n\t\t\todm_write_4byte(dm, R_0xc1c, api->rxiqc_reg2);\n\t\t}\n\t\tphydm_dis_cck_trx(dm, PHYDM_REVERT);\n\t\treturn PHYDM_SET_SUCCESS;\n\t}\n}\n\nvoid phydm_dis_cck_trx(void *dm_void, u8 set_type)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_api_stuc *api = &dm->api_table;\n\n\tif (set_type == PHYDM_SET) {\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t\tapi->ccktx_path = (u8)odm_get_bb_reg(dm, R_0x1a04,\n\t\t\t\t\t\t\t     0xf0000000);\n\t\t\t/* @CCK RxIQ weighting = [0,0] */\n\t\t\todm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);\n\t\t\t/* @disable CCK Tx */\n\t\t\todm_set_bb_reg(dm, R_0x1a04, 0xf0000000, 0x0);\n\t\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\t\tapi->ccktx_path = (u8)odm_get_bb_reg(dm, R_0xa04,\n\t\t\t\t\t\t\t     0xf0000000);\n\t\t\t/* @disable CCK block */\n\t\t\todm_set_bb_reg(dm, R_0x808, BIT(28), 0);\n\t\t\t/* @disable CCK Tx */\n\t\t\todm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x0);\n\t\t} else {\n\t\t\tapi->ccktx_path = (u8)odm_get_bb_reg(dm, R_0xa04,\n\t\t\t\t\t\t\t     0xf0000000);\n\t\t\t/* @disable whole CCK block */\n\t\t\todm_set_bb_reg(dm, R_0x800, BIT(24), 0);\n\t\t\t/* @disable CCK Tx */\n\t\t\todm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x0);\n\t\t}\n\t} else if (set_type == PHYDM_REVERT) {\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t\t/* @CCK RxIQ weighting = [1,1] */\n\t\t\todm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);\n\t\t\t/* @enable CCK Tx */\n\t\t\todm_set_bb_reg(dm, R_0x1a04, 0xf0000000,\n\t\t\t\t       api->ccktx_path);\n\t\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\t\t/* @enable CCK block */\n\t\t\todm_set_bb_reg(dm, R_0x808, BIT(28), 1);\n\t\t\t/* @enable CCK Tx */\n\t\t\todm_set_bb_reg(dm, R_0xa04, 0xf0000000,\n\t\t\t\t       api->ccktx_path);\n\t\t} else {\n\t\t\t/* @enable whole CCK block */\n\t\t\todm_set_bb_reg(dm, R_0x800, BIT(24), 1);\n\t\t\t/* @enable CCK Tx */\n\t\t\todm_set_bb_reg(dm, R_0xa04, 0xf0000000,\n\t\t\t\t       api->ccktx_path);\n\t\t}\n\t}\n}\nvoid phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch)\n{\n#if (RTL8821A_SUPPORT || RTL8881A_SUPPORT)\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (!(dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)))\n\t\treturn;\n\n\t/*Output Pin Settings*/\n\n\t/*select DPDT_P and DPDT_N as output pin*/\n\todm_set_mac_reg(dm, R_0x4c, BIT(23), 0);\n\n\t/*@by WLAN control*/\n\todm_set_mac_reg(dm, R_0x4c, BIT(24), 1);\n\n\t/*@DPDT_N = 1b'0*/ /*@DPDT_P = 1b'0*/\n\todm_set_bb_reg(dm, R_0xcb4, 0xFF, 77);\n\n\tif (ext_ant_switch == 1) { /*@2b'01*/\n\t\todm_set_bb_reg(dm, R_0xcb4, (BIT(29) | BIT(28)), 1);\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"8821A ant swh=2b'01\\n\");\n\t} else if (ext_ant_switch == 2) { /*@2b'10*/\n\t\todm_set_bb_reg(dm, R_0xcb4, BIT(29) | BIT(28), 2);\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"*8821A ant swh=2b'10\\n\");\n\t}\n#endif\n}\n\nvoid phydm_csi_mask_enable(void *dm_void, u32 enable)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tboolean en = false;\n\n\ten = (enable == FUNC_ENABLE) ? true : false;\n\n\tif (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\todm_set_bb_reg(dm, R_0xd2c, BIT(28), en);\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"Enable CSI Mask:  Reg 0xD2C[28] = ((0x%x))\\n\", en);\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\todm_set_bb_reg(dm, R_0xc0c, BIT(3), en);\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"Enable CSI Mask:  Reg 0xc0c[3] = ((0x%x))\\n\", en);\n\t#endif\n\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\todm_set_bb_reg(dm, R_0x874, BIT(0), en);\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"Enable CSI Mask:  Reg 0x874[0] = ((0x%x))\\n\", en);\n\t}\n}\n\nvoid phydm_clean_all_csi_mask(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\todm_set_bb_reg(dm, R_0xd40, MASKDWORD, 0);\n\t\todm_set_bb_reg(dm, R_0xd44, MASKDWORD, 0);\n\t\todm_set_bb_reg(dm, R_0xd48, MASKDWORD, 0);\n\t\todm_set_bb_reg(dm, R_0xd4c, MASKDWORD, 0);\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tu8 i = 0, idx_lmt = 0;\n\n\t\tif (dm->support_ic_type &\n\t\t   (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G))\n\t\t\tidx_lmt = 127;\n\t\telse /*@for IC supporting 80 + 80*/\n\t\t\tidx_lmt = 255;\n\n\t\todm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3);\n\t\todm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1);\n\t\tfor (i = 0; i < idx_lmt; i++) {\n\t\t\todm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, i);\n\t\t\todm_set_bb_reg(dm, R_0x1d94, MASKBYTE0, 0x0);\n\t\t}\n\t\todm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0);\n\t#endif\n\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\todm_set_bb_reg(dm, R_0x880, MASKDWORD, 0);\n\t\todm_set_bb_reg(dm, R_0x884, MASKDWORD, 0);\n\t\todm_set_bb_reg(dm, R_0x888, MASKDWORD, 0);\n\t\todm_set_bb_reg(dm, R_0x88c, MASKDWORD, 0);\n\t\todm_set_bb_reg(dm, R_0x890, MASKDWORD, 0);\n\t\todm_set_bb_reg(dm, R_0x894, MASKDWORD, 0);\n\t\todm_set_bb_reg(dm, R_0x898, MASKDWORD, 0);\n\t\todm_set_bb_reg(dm, R_0x89c, MASKDWORD, 0);\n\t}\n}\n\nvoid phydm_set_csi_mask(void *dm_void, u32 tone_idx_tmp, u8 tone_direction)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 byte_offset = 0, bit_offset = 0;\n\tu32 target_reg = 0;\n\tu8 reg_tmp_value = 0;\n\tu32 tone_num = 64;\n\tu32 tone_num_shift = 0;\n\tu32 csi_mask_reg_p = 0, csi_mask_reg_n = 0;\n\n\t/* @calculate real tone idx*/\n\tif ((tone_idx_tmp % 10) >= 5)\n\t\ttone_idx_tmp += 10;\n\n\ttone_idx_tmp = (tone_idx_tmp / 10);\n\n\tif (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\ttone_num = 64;\n\t\tcsi_mask_reg_p = 0xD40;\n\t\tcsi_mask_reg_n = 0xD48;\n\n\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\ttone_num = 128;\n\t\tcsi_mask_reg_p = 0x880;\n\t\tcsi_mask_reg_n = 0x890;\n\t}\n\n\tif (tone_direction == FREQ_POSITIVE) {\n\t\tif (tone_idx_tmp >= (tone_num - 1))\n\t\t\ttone_idx_tmp = (tone_num - 1);\n\n\t\tbyte_offset = (u8)(tone_idx_tmp >> 3);\n\t\tbit_offset = (u8)(tone_idx_tmp & 0x7);\n\t\ttarget_reg = csi_mask_reg_p + byte_offset;\n\n\t} else {\n\t\ttone_num_shift = tone_num;\n\n\t\tif (tone_idx_tmp >= tone_num)\n\t\t\ttone_idx_tmp = tone_num;\n\n\t\ttone_idx_tmp = tone_num - tone_idx_tmp;\n\n\t\tbyte_offset = (u8)(tone_idx_tmp >> 3);\n\t\tbit_offset = (u8)(tone_idx_tmp & 0x7);\n\t\ttarget_reg = csi_mask_reg_n + byte_offset;\n\t}\n\n\treg_tmp_value = odm_read_1byte(dm, target_reg);\n\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t  \"Pre Mask tone idx[%d]:  Reg0x%x = ((0x%x))\\n\",\n\t\t  (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value);\n\treg_tmp_value |= BIT(bit_offset);\n\todm_write_1byte(dm, target_reg, reg_tmp_value);\n\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t  \"New Mask tone idx[%d]:  Reg0x%x = ((0x%x))\\n\",\n\t\t  (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value);\n}\n\nvoid phydm_set_nbi_reg(void *dm_void, u32 tone_idx_tmp, u32 bw)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\t/*tone_idx X 10*/\n\tu32 nbi_128[NBI_128TONE] = {25, 55, 85, 115, 135,\n\t\t\t\t    155, 185, 205, 225, 245,\n\t\t\t\t    265, 285, 305, 335, 355,\n\t\t\t\t    375, 395, 415, 435, 455,\n\t\t\t\t    485, 505, 525, 555, 585, 615, 635};\n\t/*tone_idx X 10*/\n\tu32 nbi_256[NBI_256TONE] = {25, 55, 85, 115, 135,\n\t\t\t\t    155, 175, 195, 225, 245,\n\t\t\t\t    265, 285, 305, 325, 345,\n\t\t\t\t    365, 385, 405, 425, 445,\n\t\t\t\t    465, 485, 505, 525, 545,\n\t\t\t\t    565, 585, 605, 625, 645,\n\t\t\t\t    665, 695, 715, 735, 755,\n\t\t\t\t    775, 795, 815, 835, 855,\n\t\t\t\t    875, 895, 915, 935, 955,\n\t\t\t\t    975, 995, 1015, 1035, 1055,\n\t\t\t\t    1085, 1105, 1125, 1145, 1175,\n\t\t\t\t    1195, 1225, 1255, 1275};\n\tu32 reg_idx = 0;\n\tu32 i;\n\tu8 nbi_table_idx = FFT_128_TYPE;\n\n\tif (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\tnbi_table_idx = FFT_128_TYPE;\n\t} else if (dm->support_ic_type & ODM_IC_11AC_1_SERIES) {\n\t\tnbi_table_idx = FFT_256_TYPE;\n\t} else if (dm->support_ic_type & ODM_IC_11AC_2_SERIES) {\n\t\tif (bw == 80)\n\t\t\tnbi_table_idx = FFT_256_TYPE;\n\t\telse /*@20M, 40M*/\n\t\t\tnbi_table_idx = FFT_128_TYPE;\n\t}\n\n\tif (nbi_table_idx == FFT_128_TYPE) {\n\t\tfor (i = 0; i < NBI_128TONE; i++) {\n\t\t\tif (tone_idx_tmp < nbi_128[i]) {\n\t\t\t\treg_idx = i + 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t} else if (nbi_table_idx == FFT_256_TYPE) {\n\t\tfor (i = 0; i < NBI_256TONE; i++) {\n\t\t\tif (tone_idx_tmp < nbi_256[i]) {\n\t\t\t\treg_idx = i + 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\todm_set_bb_reg(dm, R_0xc40, 0x1f000000, reg_idx);\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"Set tone idx:  Reg0xC40[28:24] = ((0x%x))\\n\",\n\t\t\t  reg_idx);\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x87c, 0xfc000, reg_idx);\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"Set tone idx: Reg0x87C[19:14] = ((0x%x))\\n\",\n\t\t\t  reg_idx);\n\t}\n}\n\nvoid phydm_nbi_enable(void *dm_void, u32 enable)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 val = 0;\n\n\tval = (enable == FUNC_ENABLE) ? 1 : 0;\n\n\tPHYDM_DBG(dm, ODM_COMP_API, \"Enable NBI=%d\\n\", val);\n\n\tif (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\tif (dm->support_ic_type & (ODM_RTL8192F | ODM_RTL8197F)) {\n\t\t\tval = (enable == FUNC_ENABLE) ? 0xf : 0;\n\t\t\todm_set_bb_reg(dm, R_0xc50, 0xf000000, val);\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0xc40, BIT(9), val);\n\t\t}\n\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\tif (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {\n\t\t\todm_set_bb_reg(dm, R_0x87c, BIT(13), val);\n\t\t\todm_set_bb_reg(dm, R_0xc20, BIT(28), val);\n\t\t\tif (dm->rf_type > RF_1T1R)\n\t\t\t\todm_set_bb_reg(dm, R_0xe20, BIT(28), val);\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0x87c, BIT(13), val);\n\t\t}\n\t}\n}\n\nu8 phydm_find_fc(void *dm_void, u32 channel, u32 bw, u32 second_ch, u32 *fc_in)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 fc = *fc_in;\n\tu32 start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100,\n\t\t\t\t\t\t  108, 116, 124, 132, 140,\n\t\t\t\t\t\t  149, 157, 165, 173};\n\tu32 start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132,\n\t\t\t\t\t\t  149, 165};\n\tu32 *start_ch = &start_ch_per_40m[0];\n\tu32 num_start_channel = NUM_START_CH_40M;\n\tu32 channel_offset = 0;\n\tu32 i;\n\n\t/*@2.4G*/\n\tif (channel <= 14 && channel > 0) {\n\t\tif (bw == 80)\n\t\t\treturn PHYDM_SET_FAIL;\n\n\t\tfc = 2412 + (channel - 1) * 5;\n\n\t\tif (bw == 40 && second_ch == PHYDM_ABOVE) {\n\t\t\tif (channel >= 10) {\n\t\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t\t  \"CH = ((%d)), Scnd_CH = ((%d)) Error setting\\n\",\n\t\t\t\t\t  channel, second_ch);\n\t\t\t\treturn PHYDM_SET_FAIL;\n\t\t\t}\n\t\t\tfc += 10;\n\t\t} else if (bw == 40 && (second_ch == PHYDM_BELOW)) {\n\t\t\tif (channel <= 2) {\n\t\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t\t  \"CH = ((%d)), Scnd_CH = ((%d)) Error setting\\n\",\n\t\t\t\t\t  channel, second_ch);\n\t\t\t\treturn PHYDM_SET_FAIL;\n\t\t\t}\n\t\t\tfc -= 10;\n\t\t}\n\t}\n\t/*@5G*/\n\telse if (channel >= 36 && channel <= 177) {\n\t\tif (bw != 20) {\n\t\t\tif (bw == 40) {\n\t\t\t\tnum_start_channel = NUM_START_CH_40M;\n\t\t\t\tstart_ch = &start_ch_per_40m[0];\n\t\t\t\tchannel_offset = CH_OFFSET_40M;\n\t\t\t} else if (bw == 80) {\n\t\t\t\tnum_start_channel = NUM_START_CH_80M;\n\t\t\t\tstart_ch = &start_ch_per_80m[0];\n\t\t\t\tchannel_offset = CH_OFFSET_80M;\n\t\t\t}\n\n\t\t\tfor (i = 0; i < (num_start_channel - 1); i++) {\n\t\t\t\tif (channel < start_ch[i + 1]) {\n\t\t\t\t\tchannel = start_ch[i] + channel_offset;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\tPHYDM_DBG(dm, ODM_COMP_API, \"Mod_CH = ((%d))\\n\",\n\t\t\t\t  channel);\n\t\t}\n\n\t\tfc = 5180 + (channel - 36) * 5;\n\n\t} else {\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"CH = ((%d)) Error setting\\n\",\n\t\t\t  channel);\n\t\treturn PHYDM_SET_FAIL;\n\t}\n\n\t*fc_in = fc;\n\n\treturn PHYDM_SET_SUCCESS;\n}\n\nu8 phydm_find_intf_distance(void *dm_void, u32 bw, u32 fc, u32 f_interference,\n\t\t\t    u32 *tone_idx_tmp_in)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 bw_up = 0, bw_low = 0;\n\tu32 int_distance = 0;\n\tu32 tone_idx_tmp = 0;\n\tu8 set_result = PHYDM_SET_NO_NEED;\n\n\tbw_up = fc + bw / 2;\n\tbw_low = fc - bw / 2;\n\n\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t  \"[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\\n\", bw_low,\n\t\t  fc, bw_up, f_interference);\n\n\tif (f_interference >= bw_low && f_interference <= bw_up) {\n\t\tint_distance = DIFF_2(fc, f_interference);\n\t\t/*@10*(int_distance /0.3125)*/\n\t\ttone_idx_tmp = (int_distance << 5);\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\\n\",\n\t\t\t  int_distance, tone_idx_tmp / 10,\n\t\t\t  tone_idx_tmp % 10);\n\t\t*tone_idx_tmp_in = tone_idx_tmp;\n\t\tset_result = PHYDM_SET_SUCCESS;\n\t}\n\n\treturn set_result;\n}\n\nu8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw,\n\t\t\t  u32 f_intf, u32 sec_ch)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 fc = 2412;\n\tu8 direction = FREQ_POSITIVE;\n\tu32 tone_idx = 0;\n\tu8 set_result = PHYDM_SET_SUCCESS;\n\tu8 rpt = 0;\n\n\tif (enable == FUNC_DISABLE) {\n\t\tset_result = PHYDM_SET_SUCCESS;\n\t\tphydm_clean_all_csi_mask(dm);\n\n\t} else {\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\\n\",\n\t\t\t  ch, bw, f_intf,\n\t\t\t  (((bw == 20) || (ch > 14)) ? \"Don't care\" :\n\t\t\t  (sec_ch == PHYDM_ABOVE) ? \"H\" : \"L\"));\n\n\t\t/*@calculate fc*/\n\t\tif (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {\n\t\t\tset_result = PHYDM_SET_FAIL;\n\t\t} else {\n\t\t\t/*@calculate interference distance*/\n\t\t\trpt = phydm_find_intf_distance(dm, bw, fc, f_intf,\n\t\t\t\t\t\t       &tone_idx);\n\t\t\tif (rpt == PHYDM_SET_SUCCESS) {\n\t\t\t\tif (f_intf >= fc)\n\t\t\t\t\tdirection = FREQ_POSITIVE;\n\t\t\t\telse\n\t\t\t\t\tdirection = FREQ_NEGATIVE;\n\n\t\t\t\tphydm_set_csi_mask(dm, tone_idx, direction);\n\t\t\t\tset_result = PHYDM_SET_SUCCESS;\n\t\t\t} else {\n\t\t\t\tset_result = PHYDM_SET_NO_NEED;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (set_result == PHYDM_SET_SUCCESS)\n\t\tphydm_csi_mask_enable(dm, enable);\n\telse\n\t\tphydm_csi_mask_enable(dm, FUNC_DISABLE);\n\n\treturn set_result;\n}\n\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\nu8 phydm_find_intf_distance_jgr3(void *dm_void, u32 bw, u32 fc,\n\t\t\t\t u32 f_interference, u32 *tone_idx_tmp_in)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 bw_up = 0, bw_low = 0;\n\tu32 int_distance = 0;\n\tu32 tone_idx_tmp = 0;\n\tu8 set_result = PHYDM_SET_NO_NEED;\n\n\tbw_up = 1000 * (fc + bw / 2);\n\tbw_low = 1000 * (fc - bw / 2);\n\tfc = 1000 * fc;\n\n\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t  \"[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\\n\", bw_low,\n\t\t  fc, bw_up, f_interference);\n\n\tif (f_interference >= bw_low && f_interference <= bw_up) {\n\t\tint_distance = DIFF_2(fc, f_interference);\n\t\t/*@10*(int_distance /0.3125)*/\n\t\ttone_idx_tmp = (int_distance / 312);\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"int_distance = ((%d)) , tone_idx_tmp = ((%d))\\n\",\n\t\t\t  int_distance, tone_idx_tmp);\n\t\t*tone_idx_tmp_in = tone_idx_tmp;\n\t\tset_result = PHYDM_SET_SUCCESS;\n\t}\n\n\treturn set_result;\n}\nu8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw,\n\t\t\t       u32 f_intf, u32 sec_ch, u8 wgt)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 fc = 2412;\n\tu8 direction = FREQ_POSITIVE;\n\tu32 tone_idx = 0;\n\tu8 set_result = PHYDM_SET_SUCCESS;\n\tu8 rpt = 0;\n\n\tif (enable == FUNC_DISABLE) {\n\t\tphydm_csi_mask_enable(dm, FUNC_ENABLE);\n\t\tphydm_clean_all_csi_mask(dm);\n\t\tphydm_csi_mask_enable(dm, FUNC_DISABLE);\n\t\tset_result = PHYDM_SET_SUCCESS;\n\t} else {\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"[Set CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s)), wgt = ((%d))\\n\",\n\t\t\t  ch, bw, f_intf,\n\t\t\t  (((bw == 20) || (ch > 14)) ? \"Don't care\" :\n\t\t\t  (sec_ch == PHYDM_ABOVE) ? \"H\" : \"L\"), wgt);\n\n\t\t/*@calculate fc*/\n\t\tif (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {\n\t\t\tset_result = PHYDM_SET_FAIL;\n\t\t} else {\n\t\t\t/*@calculate interference distance*/\n\t\t\trpt = phydm_find_intf_distance_jgr3(dm, bw, fc, f_intf,\n\t\t\t\t\t\t\t    &tone_idx);\n\t\t\tif (rpt == PHYDM_SET_SUCCESS) {\n\t\t\t\tif (f_intf >= 1000 * fc)\n\t\t\t\t\tdirection = FREQ_POSITIVE;\n\t\t\t\telse\n\t\t\t\t\tdirection = FREQ_NEGATIVE;\n\n\t\t\t\tphydm_csi_mask_enable(dm, FUNC_ENABLE);\n\t\t\t\tphydm_set_csi_mask_jgr3(dm, tone_idx, direction,\n\t\t\t\t\t\t\twgt);\n\t\t\t\tset_result = PHYDM_SET_SUCCESS;\n\t\t\t} else {\n\t\t\t\tset_result = PHYDM_SET_NO_NEED;\n\t\t\t}\n\t\t}\n\t\tif (!(set_result == PHYDM_SET_SUCCESS))\n\t\t\tphydm_csi_mask_enable(dm, FUNC_DISABLE);\n\t}\n\n\treturn set_result;\n}\n\nvoid phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,\n\t\t\t     u8 wgt)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 reg_tmp_value = 0;\n\tu32 tone_num = 64;\n\tu32 table_addr = 0;\n\tu32 addr = 0;\n\tu8 rf_bw = 0;\n\tu8 value = 0;\n\n\trf_bw = odm_read_1byte(dm, R_0x9b0);\n\tif (((rf_bw & 0xc) >> 2) == 0x2)\n\t\ttone_num = 128; /* @RF80 : tone(-1) at tone_idx=255 */\n\telse\n\t\ttone_num = 64; /* @RF20/40 : tone(-1) at tone_idx=127 */\n\n\tif (tone_direction == FREQ_POSITIVE) {\n\t\tif (tone_idx_tmp >= (tone_num - 1))\n\t\t\ttone_idx_tmp = (tone_num - 1);\n\t} else {\n\t\tif (tone_idx_tmp >= tone_num)\n\t\t\ttone_idx_tmp = tone_num;\n\n\t\ttone_idx_tmp = (tone_num << 1) - tone_idx_tmp;\n\t}\n\ttable_addr = tone_idx_tmp >> 1;\n\n\treg_tmp_value = odm_read_4byte(dm, R_0x1d94);\n\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t  \"Pre Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\\n\",\n\t\t  tone_idx_tmp, reg_tmp_value);\n\todm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3);\n\todm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1);\n\todm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, (table_addr & 0xff));\n\tif (tone_idx_tmp % 2)\n\t\tvalue = (BIT(3) | (wgt & 0x7)) << 4;\n\telse\n\t\tvalue = BIT(3) | (wgt & 0x7);\n\n\todm_set_bb_reg(dm, R_0x1d94, 0xff, value);\n\treg_tmp_value = odm_read_4byte(dm, R_0x1d94);\n\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t  \"New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\\n\",\n\t\t  tone_idx_tmp, reg_tmp_value);\n\todm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0);\n}\n\nvoid phydm_nbi_reset_jgr3(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\todm_set_bb_reg(dm, R_0x818, BIT(3), 1);\n\todm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0);\n\todm_set_bb_reg(dm, R_0x818, BIT(3), 0);\n\todm_set_bb_reg(dm, R_0x818, BIT(11), 0);\n}\n\nu8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,\n\t\t\t  u32 sec_ch, u8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 fc = 2412;\n\tu8 direction = FREQ_POSITIVE;\n\tu32 tone_idx = 0;\n\tu8 set_result = PHYDM_SET_SUCCESS;\n\tu8 rpt = 0;\n\n\tif (enable == FUNC_DISABLE) {\n\t\tphydm_nbi_reset_jgr3(dm);\n\t\tset_result = PHYDM_SET_SUCCESS;\n\t} else {\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\\n\",\n\t\t\t  ch, bw, f_intf,\n\t\t\t  (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) ||\n\t\t\t  (ch > 14)) ? \"Don't care\" :\n\t\t\t  (sec_ch == PHYDM_ABOVE) ? \"H\" : \"L\"));\n\n\t\t/*@calculate fc*/\n\t\tif (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {\n\t\t\tset_result = PHYDM_SET_FAIL;\n\t\t} else {\n\t\t\t/*@calculate interference distance*/\n\t\t\trpt = phydm_find_intf_distance_jgr3(dm, bw, fc, f_intf,\n\t\t\t\t\t\t\t    &tone_idx);\n\t\t\tif (rpt == PHYDM_SET_SUCCESS) {\n\t\t\t\tif (f_intf >= 1000 * fc)\n\t\t\t\t\tdirection = FREQ_POSITIVE;\n\t\t\t\telse\n\t\t\t\t\tdirection = FREQ_NEGATIVE;\n\n\t\t\t\tphydm_set_nbi_reg_jgr3(dm, tone_idx, direction,\n\t\t\t\t\t\t       path);\n\t\t\t\tset_result = PHYDM_SET_SUCCESS;\n\t\t\t} else {\n\t\t\t\tset_result = PHYDM_SET_NO_NEED;\n\t\t}\n\t}\n\t}\n\n\tif (set_result == PHYDM_SET_SUCCESS)\n\t\tphydm_nbi_enable_jgr3(dm, enable, path);\n\telse\n\t\tphydm_nbi_enable_jgr3(dm, FUNC_DISABLE, path);\n\n\treturn set_result;\n}\n\nvoid phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,\n\t\t\t    u8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 reg_tmp_value = 0;\n\tu32 tone_num = 64;\n\tu32 addr = 0;\n\tu8 rf_bw = 0;\n\n\trf_bw = odm_read_1byte(dm, R_0x9b0);\n\tif (((rf_bw & 0xc) >> 2) == 0x2)\n\t\ttone_num = 128; /* RF80 : tone-1 at tone_idx=255 */\n\telse\n\t\ttone_num = 64; /* RF20/40 : tone-1 at tone_idx=127 */\n\n\tif (tone_direction == FREQ_POSITIVE) {\n\t\tif (tone_idx_tmp >= (tone_num - 1))\n\t\t\ttone_idx_tmp = (tone_num - 1);\n\t} else {\n\t\tif (tone_idx_tmp >= tone_num)\n\t\t\ttone_idx_tmp = tone_num;\n\n\t\ttone_idx_tmp = (tone_num << 1) - tone_idx_tmp;\n\t}\n\n\tswitch (path) {\n\tcase RF_PATH_A:\n\t\todm_set_bb_reg(dm, R_0x1944, 0x001FF000, tone_idx_tmp);\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"Set tone idx[%d]:PATH-A = ((0x%x))\\n\",\n\t\t\t  tone_idx_tmp, tone_idx_tmp);\n\t\tbreak;\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tcase RF_PATH_B:\n\t\todm_set_bb_reg(dm, R_0x4044, 0x001FF000, tone_idx_tmp);\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"Set tone idx[%d]:PATH-B = ((0x%x))\\n\",\n\t\t\t  tone_idx_tmp, tone_idx_tmp);\n\t\tbreak;\n\t#endif\n\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\tcase RF_PATH_C:\n\t\todm_set_bb_reg(dm, R_0x5044, 0x001FF000, tone_idx_tmp);\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"Set tone idx[%d]:PATH-C = ((0x%x))\\n\",\n\t\t\t  tone_idx_tmp, tone_idx_tmp);\n\t\tbreak;\n\t#endif\n\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\tcase RF_PATH_D:\n\t\todm_set_bb_reg(dm, R_0x5144, 0x001FF000, tone_idx_tmp);\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"Set tone idx[%d]:PATH-D = ((0x%x))\\n\",\n\t\t\t  tone_idx_tmp, tone_idx_tmp);\n\t\tbreak;\n\t#endif\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tboolean val = false;\n\n\tval = (enable == FUNC_ENABLE) ? true : false;\n\n\tPHYDM_DBG(dm, ODM_COMP_API, \"Enable NBI=%d\\n\", val);\n\n\tif (dm->support_ic_type & ODM_RTL8814B) {\n\t\todm_set_bb_reg(dm, R_0x1d3c, BIT(19), val);\n\t\todm_set_bb_reg(dm, R_0x818, BIT(3), val);\n\t} else if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {\n\t\todm_set_bb_reg(dm, R_0x818, BIT(3), !val);\n\t}\n\todm_set_bb_reg(dm, R_0x818, BIT(11), val);\n\todm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0xf);\n\n\tif (enable == FUNC_ENABLE) {\n\t\tswitch (path) {\n\t\tcase RF_PATH_A:\n\t\t\todm_set_bb_reg(dm, R_0x1940, BIT(31), val);\n\t\t\tbreak;\n\t\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\t\tcase RF_PATH_B:\n\t\t\todm_set_bb_reg(dm, R_0x4040, BIT(31), val);\n\t\t\tbreak;\n\t\t#endif\n\t\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\t\tcase RF_PATH_C:\n\t\t\todm_set_bb_reg(dm, R_0x5040, BIT(31), val);\n\t\t\tbreak;\n\t\t#endif\n\t\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\t\tcase RF_PATH_D:\n\t\t\todm_set_bb_reg(dm, R_0x5140, BIT(31), val);\n\t\t\tbreak;\n\t\t#endif\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x1940, BIT(31), val);\n\t\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\t\todm_set_bb_reg(dm, R_0x4040, BIT(31), val);\n\t\t#endif\n\t\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\t\todm_set_bb_reg(dm, R_0x5040, BIT(31), val);\n\t\t#endif\n\t\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\t\todm_set_bb_reg(dm, R_0x5140, BIT(31), val);\n\t\t#endif\n\t}\n}\n\nu8 phydm_phystat_rpt_jgr3(void *dm_void, enum phystat_rpt info,\n\t\t\t  enum rf_path ant_path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\ts8 evm_org, cfo_org, rxsnr_org;\n\tu8 i, return_info = 0, tmp_lsb = 0, tmp_msb = 0, tmp_info = 0;\n\n\t/* Update the status for each pkt */\n\todm_set_bb_reg(dm, R_0x8c4, 0xfff000, 0x448);\n\todm_set_bb_reg(dm, R_0x8c0, MASKLWORD, 0x4001);\n\t/* PHY status Page1 */\n\todm_set_bb_reg(dm, R_0x8c0, 0x3C00000, 0x1);\n\t/*choose debug port for phystatus */\n\todm_set_bb_reg(dm, R_0x1c3c, 0xFFF00, 0x380);\n\n\tif (info == PHY_PWDB) {\n\t\t/* Choose the report of the diff path */\n\t\tif (ant_path == RF_PATH_A)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1);\n\t\telse if (ant_path == RF_PATH_B)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x2);\n\t\telse if (ant_path == RF_PATH_C)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x3);\n\t\telse if (ant_path == RF_PATH_D)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x4);\n\t} else if (info == PHY_EVM) {\n\t\t/* Choose the report of the diff path */\n\t\tif (ant_path == RF_PATH_A)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x10);\n\t\telse if (ant_path == RF_PATH_B)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x11);\n\t\telse if (ant_path == RF_PATH_C)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x12);\n\t\telse if (ant_path == RF_PATH_D)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x13);\n\t\treturn_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);\n\t} else if (info == PHY_CFO) {\n\t\t/* Choose the report of the diff path */\n\t\tif (ant_path == RF_PATH_A)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x14);\n\t\telse if (ant_path == RF_PATH_B)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x15);\n\t\telse if (ant_path == RF_PATH_C)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x16);\n\t\telse if (ant_path == RF_PATH_D)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x17);\n\t\treturn_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);\n\t} else if (info == PHY_RXSNR) {\n\t\t/* Choose the report of the diff path */\n\t\tif (ant_path == RF_PATH_A)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x18);\n\t\telse if (ant_path == RF_PATH_B)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x19);\n\t\telse if (ant_path == RF_PATH_C)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1a);\n\t\telse if (ant_path == RF_PATH_D)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1b);\n\t\treturn_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);\n\t} else if (info == PHY_LGAIN) {\n\t\t/* choose page */\n\t\todm_set_bb_reg(dm, R_0x8c0, 0x3c00000, 0x2);\n\t\t/* Choose the report of the diff path */\n\t\tif (ant_path == RF_PATH_A) {\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xd);\n\t\t\ttmp_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3f);\n\t\t\treturn_info = tmp_info;\n\t\t} else if (ant_path == RF_PATH_B) {\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xd);\n\t\t\ttmp_lsb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xc0);\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xe);\n\t\t\ttmp_msb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xf);\n\t\t\ttmp_info |= (tmp_msb << 2) | tmp_lsb;\n\t\t\treturn_info = tmp_info;\n\t\t} else if (ant_path == RF_PATH_C) {\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xe);\n\t\t\ttmp_lsb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xf0);\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xf);\n\t\t\ttmp_msb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3);\n\t\t\ttmp_info |= (tmp_msb << 4) | tmp_lsb;\n\t\t\treturn_info = tmp_info;\n\t\t} else if (ant_path == RF_PATH_D) {\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x10);\n\t\t\ttmp_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3f);\n\t\t\treturn_info = tmp_info;\n\t\t}\n\t} else if (info == PHY_HT_AAGC_GAIN) {\n\t\t/* choose page */\n\t\todm_set_bb_reg(dm, R_0x8c0, 0x3c00000, 0x2);\n\t\t/* Choose the report of the diff path */\n\t\tif (ant_path == RF_PATH_A)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x12);\n\t\telse if (ant_path == RF_PATH_B)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x13);\n\t\telse if (ant_path == RF_PATH_C)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x14);\n\t\telse if (ant_path == RF_PATH_D)\n\t\t\todm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x15);\n\t\treturn_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);\n\t}\n\treturn return_info;\n}\n\nvoid phydm_ex_hal8814b_wifi_only_hw_config(void *dm_void)\n{\n\t/*BB control*/\n\t/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2);*/\n\t/*SW control*/\n\t/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0xff, 0x77);*/\n\t/*antenna mux switch */\n\t/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x974, 0x300, 0x3);*/\n\n\t/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1990, 0x300, 0x0);*/\n\n\t/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x80000, 0x0);*/\n\t/*switch to WL side controller and gnt_wl gnt_bt debug signal */\n\t/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x70, 0xff000000, 0x0e);*/\n\t/*gnt_wl=1 , gnt_bt=0*/\n\t/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff,\n\t *\t\t\t     0x7700);\n\t */\n\t/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff,\n\t *\t\t\t     0xc00f0038);\n\t */\n}\n\nvoid phydm_user_position_for_sniffer(void *dm_void, u8 user_position)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\t/* user position valid */\n\todm_set_bb_reg(dm, R_0xa68, BIT(17), 1);\n\t/* Select user seat from pmac */\n\todm_set_bb_reg(dm, R_0xa68, BIT(16), 1);\n\t/*user seat*/\n\todm_set_bb_reg(dm, R_0xa68, (BIT(19) | BIT(18)), user_position);\n}\n\n#endif\nu8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,\n\t\t     u32 sec_ch)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 fc = 2412;\n\tu8 direction = FREQ_POSITIVE;\n\tu32 tone_idx = 0;\n\tu8 set_result = PHYDM_SET_SUCCESS;\n\tu8 rpt = 0;\n\n\tif (enable == FUNC_DISABLE) {\n\t\tset_result = PHYDM_SET_SUCCESS;\n\t} else {\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\\n\",\n\t\t\t  ch, bw, f_intf,\n\t\t\t  (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) ||\n\t\t\t  (ch > 14)) ? \"Don't care\" :\n\t\t\t  (sec_ch == PHYDM_ABOVE) ? \"H\" : \"L\"));\n\n\t\t/*@calculate fc*/\n\t\tif (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {\n\t\t\tset_result = PHYDM_SET_FAIL;\n\t\t} else {\n\t\t\t/*@calculate interference distance*/\n\t\t\trpt = phydm_find_intf_distance(dm, bw, fc, f_intf,\n\t\t\t\t\t\t       &tone_idx);\n\t\t\tif (rpt == PHYDM_SET_SUCCESS) {\n\t\t\t\tif (f_intf >= fc)\n\t\t\t\t\tdirection = FREQ_POSITIVE;\n\t\t\t\telse\n\t\t\t\t\tdirection = FREQ_NEGATIVE;\n\n\t\t\t\tphydm_set_nbi_reg(dm, tone_idx, bw);\n\n\t\t\t\tset_result = PHYDM_SET_SUCCESS;\n\t\t\t} else {\n\t\t\t\tset_result = PHYDM_SET_NO_NEED;\n\t\t}\n\t}\n\t}\n\n\tif (set_result == PHYDM_SET_SUCCESS)\n\t\tphydm_nbi_enable(dm, enable);\n\telse\n\t\tphydm_nbi_enable(dm, FUNC_DISABLE);\n\n\treturn set_result;\n}\n\nvoid phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t     u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 val[10] = {0};\n\tchar help[] = \"-h\";\n\tu8 i = 0, input_idx = 0, idx_lmt = 0;\n\tu32 enable = 0; /*@function enable*/\n\tu32 ch = 0;\n\tu32 bw = 0;\n\tu32 f_int = 0; /*@interference frequency*/\n\tu32 sec_ch = 0; /*secondary channel*/\n\tu8 rpt = 0;\n\tu8 path = 0;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tidx_lmt = 6;\n\telse\n\t\tidx_lmt = 5;\n\tfor (i = 0; i < idx_lmt; i++) {\n\t\tif (input[i + 1]) {\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);\n\t\t\tinput_idx++;\n\t\t}\n\t}\n\n\tif (input_idx == 0)\n\t\treturn;\n\n\tenable = val[0];\n\tch = val[1];\n\tbw = val[2];\n\tf_int = val[3];\n\tsec_ch = val[4];\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\tpath = (u8)val[5];\n\t#endif\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(khz)} {Scnd_CH(L=1, H=2)} {Path:A~D(0~3)}\\n\");\n\t\telse\n\t\t#endif\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(khz)} {Scnd_CH(L=1, H=2)}\\n\");\n\t\t*_used = used;\n\t\t*_out_len = out_len;\n\t\treturn;\n\t} else if (val[0] == FUNC_ENABLE) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\\n\",\n\t\t\t ch, bw, f_int,\n\t\t\t ((sec_ch == PHYDM_DONT_CARE) ||\n\t\t\t (bw == 20) || (ch > 14)) ? \"Don't care\" :\n\t\t\t ((sec_ch == PHYDM_ABOVE) ? \"H\" : \"L\"));\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\t\trpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int,\n\t\t\t\t\t\t     sec_ch, path);\n\t\telse\n\t\t#endif\n\t\t\trpt = phydm_nbi_setting(dm, enable, ch, bw, f_int,\n\t\t\t\t\t\tsec_ch);\n\t} else if (val[0] == FUNC_DISABLE) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[Disable NBI]\\n\");\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\t\trpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int,\n\t\t\t\t\t\t     sec_ch, path);\n\t\telse\n\t\t#endif\n\t\t\trpt = phydm_nbi_setting(dm, enable, ch, bw, f_int,\n\t\t\t\t\t\tsec_ch);\n\t} else {\n\t\trpt = PHYDM_SET_FAIL;\n\t}\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"[NBI set result: %s]\\n\",\n\t\t (rpt == PHYDM_SET_SUCCESS) ? \"Success\" :\n\t\t ((rpt == PHYDM_SET_NO_NEED) ? \"No need\" : \"Error\"));\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_csi_debug(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t     u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 val[10] = {0};\n\tchar help[] = \"-h\";\n\tu8 i = 0, input_idx = 0, idx_lmt = 0;\n\tu32 enable = 0;  /*@function enable*/\n\tu32 ch = 0;\n\tu32 bw = 0;\n\tu32 f_int = 0; /*@interference frequency*/\n\tu32 sec_ch = 0;  /*secondary channel*/\n\tu8 rpt = 0;\n\tu8 wgt = 0;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tidx_lmt = 6;\n\telse\n\t\tidx_lmt = 5;\n\n\tfor (i = 0; i < idx_lmt; i++) {\n\t\tif (input[i + 1]) {\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);\n\t\t\tinput_idx++;\n\t\t}\n\t}\n\n\tif (input_idx == 0)\n\t\treturn;\n\n\tenable = val[0];\n\tch = val[1];\n\tbw = val[2];\n\tf_int = val[3];\n\tsec_ch = val[4];\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\twgt = (u8)val[5];\n\t#endif\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(KHz)} {Scnd_CH(L=1, H=2)}\\n{wgt:(7:3/4),(6~1: 1/2 ~ 1/64),(0:0)}\\n\");\n\t\telse\n\t\t#endif\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(Mhz)} {Scnd_CH(L=1, H=2)}\\n\");\n\n\t\t*_used = used;\n\t\t*_out_len = out_len;\n\t\treturn;\n\n\t} else if (val[0] == FUNC_ENABLE) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\\n\",\n\t\t\t ch, bw, f_int,\n\t\t\t (ch > 14) ? \"Don't care\" :\n\t\t\t (((sec_ch == PHYDM_DONT_CARE) ||\n\t\t\t (bw == 20) || (ch > 14)) ? \"H\" : \"L\"));\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\t\trpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw,\n\t\t\t\t\t\t\t  f_int, sec_ch, wgt);\n\t\telse\n\t\t#endif\n\t\t\trpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int,\n\t\t\t\t\t\t     sec_ch);\n\t} else if (val[0] == FUNC_DISABLE) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[Disable CSI MASK]\\n\");\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\t\trpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw,\n\t\t\t\t\t\t\t  f_int, sec_ch, wgt);\n\t\telse\n\t\t#endif\n\t\t\trpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int,\n\t\t\t\t\t\t     sec_ch);\n\t} else {\n\t\trpt = PHYDM_SET_FAIL;\n\t}\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"[CSI MASK set result: %s]\\n\",\n\t\t (rpt == PHYDM_SET_SUCCESS) ? \"Success\" :\n\t\t ((rpt == PHYDM_SET_NO_NEED) ? \"No need\" : \"Error\"));\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_stop_ck320(void *dm_void, u8 enable)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 val = enable ? 1 : 0;\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\todm_set_bb_reg(dm, R_0x8b4, BIT(6), val);\n\t} else {\n\t\tif (dm->support_ic_type & ODM_IC_N_2SS) /*N-2SS*/\n\t\t\todm_set_bb_reg(dm, R_0x87c, BIT(29), val);\n\t\telse /*N-1SS*/\n\t\t\todm_set_bb_reg(dm, R_0x87c, BIT(31), val);\n\t}\n}\n\nboolean\nphydm_set_bb_txagc_offset(void *dm_void, s8 power_offset, /*@(unit: dB)*/\n\t\t\t  u8 add_half_db /*@(+0.5 dB)*/)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\ts8 power_idx = power_offset * 2;\n\tboolean set_success = false;\n\n\tPHYDM_DBG(dm, ODM_COMP_API, \"power_offset=%d, add_half_db =%d\\n\",\n\t\t  power_offset, add_half_db);\n\n\t#if ODM_IC_11AC_SERIES_SUPPORT\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\tif (power_offset > -16 && power_offset < 15) {\n\t\t\tif (add_half_db)\n\t\t\t\tpower_idx += 1;\n\n\t\t\tpower_idx &= 0x3f;\n\n\t\t\tPHYDM_DBG(dm, ODM_COMP_API, \"Reg_idx =0x%x\\n\",\n\t\t\t\t  power_idx);\n\t\t\todm_set_bb_reg(dm, R_0x8b4, 0x3f, power_idx);\n\t\t\tset_success = true;\n\t\t} else {\n\t\t\tpr_debug(\"[Warning] TX AGC Offset Setting error!\");\n\t\t}\n\t}\n\t#endif\n\n\t#if ODM_IC_11N_SERIES_SUPPORT\n\tif (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\tif (power_offset > -8 || power_offset < 7) {\n\t\t\tif (add_half_db)\n\t\t\t\tpower_idx += 1;\n\n\t\t\tpower_idx &= 0x1f;\n\n\t\t\tPHYDM_DBG(dm, ODM_COMP_API, \"Reg_idx =0x%x\\n\",\n\t\t\t\t  power_idx);\n\t\t\t/*r_txagc_offset_a*/\n\t\t\todm_set_bb_reg(dm, R_0x80c, 0x1f00, power_idx);\n\t\t\t/*r_txagc_offset_b*/\n\t\t\todm_set_bb_reg(dm, R_0x80c, 0x3e000, power_idx);\n\t\t\tset_success = true;\n\t\t} else {\n\t\t\tpr_debug(\"[Warning] TX AGC Offset Setting error!\");\n\t\t}\n\t}\n\t#endif\n\n\treturn set_success;\n}\n\n#ifdef PHYDM_COMMON_API_SUPPORT\nboolean\nphydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path,\n\t\t      boolean is_positive) {\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tboolean ret = false;\n\tu32 txagc_cck = 0;\n\tu32 txagc_ofdm = 0;\n\tu32 r_txagc_ofdm[4] = {0x18e8, 0x41e8, 0x52e8, 0x53e8};\n\tu32 r_txagc_cck[4] = {0x18a0, 0x41a0, 0x52a0, 0x53a0};\n\n\t#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)\n\tif (dm->support_ic_type &\n\t   (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)) {\n\t\tif (path > RF_PATH_B) {\n\t\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Unsupported path (%d)\\n\",\n\t\t\t\t  path);\n\t\t\treturn false;\n\t\t}\n\t\ttxagc_cck = (u8)odm_get_bb_reg(dm, r_txagc_cck[path],\n\t\t\t\t\t\t   0x7F0000);\n\t\ttxagc_ofdm = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path],\n\t\t\t\t\t\t    0x1FC00);\n\t\tif (is_positive) {\n\t\t\tif (((txagc_cck + pwr_offset) > 127) ||\n\t\t\t    ((txagc_ofdm + pwr_offset) > 127))\n\t\t\t\treturn false;\n\n\t\t\ttxagc_cck += pwr_offset;\n\t\t\ttxagc_ofdm += pwr_offset;\n\t\t} else {\n\t\t\tif (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm)\n\t\t\t\treturn false;\n\n\t\t\ttxagc_cck -= pwr_offset;\n\t\t\ttxagc_ofdm -= pwr_offset;\n\t\t}\n\t\t#if (RTL8822C_SUPPORT)\n\t\tret = config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_cck,\n\t\t\t\t\t\t\t path, PDM_CCK);\n\t\tret &= config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_ofdm,\n\t\t\t\t\t\t\t path, PDM_OFDM);\n\t\t#endif\n\t\t#if (RTL8812F_SUPPORT)\n\t\tret = config_phydm_write_txagc_ref_8812f(dm, (u8)txagc_cck,\n\t\t\t\t\t\t\t path, PDM_CCK);\n\t\tret &= config_phydm_write_txagc_ref_8812f(dm, (u8)txagc_ofdm,\n\t\t\t\t\t\t\t path, PDM_OFDM);\n\t\t#endif\n\t\t#if (RTL8197G_SUPPORT)\n\t\tret = config_phydm_write_txagc_ref_8197g(dm, (u8)txagc_cck,\n\t\t\t\t\t\t\t path, PDM_CCK);\n\t\tret &= config_phydm_write_txagc_ref_8197g(dm, (u8)txagc_ofdm,\n\t\t\t\t\t\t\t path, PDM_OFDM);\n\t\t#endif\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t\t  \"%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\\n\",\n\t\t\t  __func__, path, txagc_cck, txagc_ofdm);\n\t}\n\t#endif\n\n\t#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)\n\tif (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) {\n\t\tif (path > RF_PATH_D) {\n\t\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Unsupported path (%d)\\n\",\n\t\t\t\t  path);\n\t\t\treturn false;\n\t\t}\n\t\ttxagc_cck = (u8)odm_get_bb_reg(dm, r_txagc_cck[path],\n\t\t\t\t\t\t   0x7F0000);\n\t\ttxagc_ofdm = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path],\n\t\t\t\t\t\t    0x1FC00);\n\t\tif (is_positive) {\n\t\t\tif (((txagc_cck + pwr_offset) > 127) ||\n\t\t\t    ((txagc_ofdm + pwr_offset) > 127))\n\t\t\t\treturn false;\n\n\t\t\ttxagc_cck += pwr_offset;\n\t\t\ttxagc_ofdm += pwr_offset;\n\t\t} else {\n\t\t\tif (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm)\n\t\t\t\treturn false;\n\n\t\t\ttxagc_cck -= pwr_offset;\n\t\t\ttxagc_ofdm -= pwr_offset;\n\t\t}\n\t\t#if (RTL8198F_SUPPORT)\n\t\tret = config_phydm_write_txagc_ref_8198f(dm, (u8)txagc_cck,\n\t\t\t\t\t\t\t path, PDM_CCK);\n\t\tret &= config_phydm_write_txagc_ref_8198f(dm, (u8)txagc_ofdm,\n\t\t\t\t\t\t\t path, PDM_OFDM);\n\t\t#endif\n\t\t#if (RTL8814B_SUPPORT)\n\t\tret = config_phydm_write_txagc_ref_8814b(dm, (u8)txagc_cck,\n\t\t\t\t\t\t\t path, PDM_CCK);\n\t\tret &= config_phydm_write_txagc_ref_8814b(dm, (u8)txagc_ofdm,\n\t\t\t\t\t\t\t path, PDM_OFDM);\n\t\t#endif\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t\t  \"%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\\n\",\n\t\t\t  __func__, path, txagc_cck, txagc_ofdm);\n\t}\n\t#endif\n\n\treturn ret;\n}\n\nboolean\nphydm_api_set_txagc(void *dm_void, u32 pwr_idx, enum rf_path path,\n\t\t    u8 rate, boolean is_single_rate)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tboolean ret = false;\n\t#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT ||\\\n\t     RTL8814B_SUPPORT || RTL8197G_SUPPORT)\n\tu8 base = 0;\n\tu8 txagc_tmp = 0;\n\ts8 pw_by_rate_tmp = 0;\n\ts8 pw_by_rate_new = 0;\n\t#endif\n\t#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\tu8 i = 0;\n\t#endif\n\n#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT)\n\tif (dm->support_ic_type &\n\t    (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)) {\n\t\tif (is_single_rate) {\n\t\t\t#if (RTL8822B_SUPPORT)\n\t\t\tif (dm->support_ic_type == ODM_RTL8822B)\n\t\t\t\tret = phydm_write_txagc_1byte_8822b(dm, pwr_idx,\n\t\t\t\t\t\t\t\t    path, rate);\n\t\t\t#endif\n\n\t\t\t#if (RTL8821C_SUPPORT)\n\t\t\tif (dm->support_ic_type == ODM_RTL8821C)\n\t\t\t\tret = phydm_write_txagc_1byte_8821c(dm, pwr_idx,\n\t\t\t\t\t\t\t\t    path, rate);\n\t\t\t#endif\n\n\t\t\t#if (RTL8195B_SUPPORT)\n\t\t\tif (dm->support_ic_type == ODM_RTL8195B)\n\t\t\t\tret = phydm_write_txagc_1byte_8195b(dm, pwr_idx,\n\t\t\t\t\t\t\t\t    path, rate);\n\t\t\t#endif\n\n\t\t\t#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\t\t\tset_current_tx_agc(dm->priv, path, rate, (u8)pwr_idx);\n\t\t\t#endif\n\n\t\t} else {\n\t\t\t#if (RTL8822B_SUPPORT)\n\t\t\tif (dm->support_ic_type == ODM_RTL8822B)\n\t\t\t\tret = config_phydm_write_txagc_8822b(dm,\n\t\t\t\t\t\t\t\t     pwr_idx,\n\t\t\t\t\t\t\t\t     path,\n\t\t\t\t\t\t\t\t     rate);\n\t\t\t#endif\n\n\t\t\t#if (RTL8821C_SUPPORT)\n\t\t\tif (dm->support_ic_type == ODM_RTL8821C)\n\t\t\t\tret = config_phydm_write_txagc_8821c(dm,\n\t\t\t\t\t\t\t\t     pwr_idx,\n\t\t\t\t\t\t\t\t     path,\n\t\t\t\t\t\t\t\t     rate);\n\t\t\t#endif\n\n\t\t\t#if (RTL8195B_SUPPORT)\n\t\t\tif (dm->support_ic_type == ODM_RTL8195B)\n\t\t\t\tret = config_phydm_write_txagc_8195b(dm,\n\t\t\t\t\t\t\t\t     pwr_idx,\n\t\t\t\t\t\t\t\t     path,\n\t\t\t\t\t\t\t\t     rate);\n\t\t\t#endif\n\n\t\t\t#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\t\t\tfor (i = 0; i < 4; i++)\n\t\t\t\tset_current_tx_agc(dm->priv, path, (rate + i),\n\t\t\t\t\t\t   (u8)pwr_idx);\n\t\t\t#endif\n\t\t}\n\t}\n#endif\n\n#if (RTL8198F_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8198F) {\n\t\tif (rate < 0x4)\n\t\t\ttxagc_tmp = config_phydm_read_txagc_8198f(dm, path,\n\t\t\t\t\t\t\t\t  rate,\n\t\t\t\t\t\t\t\t  PDM_CCK);\n\t\telse\n\t\t\ttxagc_tmp = config_phydm_read_txagc_8198f(dm, path,\n\t\t\t\t\t\t\t\t  rate,\n\t\t\t\t\t\t\t\t  PDM_OFDM);\n\n\t\tpw_by_rate_tmp = config_phydm_read_txagc_diff_8198f(dm, rate);\n\t\tbase = txagc_tmp -  pw_by_rate_tmp;\n\t\tbase = base & 0x7f;\n\t\tif (DIFF_2((pwr_idx & 0x7f), base) > 64 || pwr_idx > 127)\n\t\t\treturn false;\n\n\t\tpw_by_rate_new = (s8)(pwr_idx - base);\n\t\tret = phydm_write_txagc_1byte_8198f(dm, pw_by_rate_new, rate);\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t\t  \"%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\\n\",\n\t\t\t  __func__, path, rate, base, pw_by_rate_new);\n\t}\n#endif\n\n#if (RTL8822C_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8822C) {\n\t\tif (rate < 0x4)\n\t\t\ttxagc_tmp = config_phydm_read_txagc_8822c(dm, path,\n\t\t\t\t\t\t\t\t  rate,\n\t\t\t\t\t\t\t\t  PDM_CCK);\n\t\telse\n\t\t\ttxagc_tmp = config_phydm_read_txagc_8822c(dm, path,\n\t\t\t\t\t\t\t\t  rate,\n\t\t\t\t\t\t\t\t  PDM_OFDM);\n\n\t\tpw_by_rate_tmp = config_phydm_read_txagc_diff_8822c(dm, rate);\n\t\tbase = txagc_tmp - pw_by_rate_tmp;\n\t\tbase = base & 0x7f;\n\t\tif (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)\n\t\t\treturn false;\n\n\t\tpw_by_rate_new = (s8)(pwr_idx - base);\n\t\tret = phydm_write_txagc_1byte_8822c(dm, pw_by_rate_new, rate);\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t\t  \"%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\\n\",\n\t\t\t  __func__, path, rate, base, pw_by_rate_new);\n\t}\n#endif\n\n#if (RTL8814B_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8814B) {\n\t\tif (rate < 0x4)\n\t\t\ttxagc_tmp = config_phydm_read_txagc_8814b(dm, path,\n\t\t\t\t\t\t\t\t  rate,\n\t\t\t\t\t\t\t\t  PDM_CCK);\n\t\telse\n\t\t\ttxagc_tmp = config_phydm_read_txagc_8814b(dm, path,\n\t\t\t\t\t\t\t\t  rate,\n\t\t\t\t\t\t\t\t  PDM_OFDM);\n\n\t\tpw_by_rate_tmp = config_phydm_read_txagc_diff_8814b(dm, rate);\n\t\tbase = txagc_tmp -  pw_by_rate_tmp;\n\t\tbase = base & 0x7f;\n\t\tif (DIFF_2((pwr_idx & 0x7f), base) > 64)\n\t\t\treturn false;\n\n\t\tpw_by_rate_new = (s8)(pwr_idx - base);\n\t\tret = phydm_write_txagc_1byte_8814b(dm, pw_by_rate_new, rate);\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t\t  \"%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\\n\",\n\t\t\t  __func__, path, rate, base, pw_by_rate_new);\n\t}\n#endif\n\n#if (RTL8812F_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8812F) {\n\t\tif (rate < 0x4)\n\t\t\ttxagc_tmp = config_phydm_read_txagc_8812f(dm, path,\n\t\t\t\t\t\t\t\t  rate,\n\t\t\t\t\t\t\t\t  PDM_CCK);\n\t\telse\n\t\t\ttxagc_tmp = config_phydm_read_txagc_8812f(dm, path,\n\t\t\t\t\t\t\t\t  rate,\n\t\t\t\t\t\t\t\t  PDM_OFDM);\n\n\t\tpw_by_rate_tmp = config_phydm_read_txagc_diff_8812f(dm, rate);\n\t\tbase = txagc_tmp - pw_by_rate_tmp;\n\t\tbase = base & 0x7f;\n\t\tif (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)\n\t\t\treturn false;\n\n\t\tpw_by_rate_new = (s8)(pwr_idx - base);\n\t\tret = phydm_write_txagc_1byte_8812f(dm, pw_by_rate_new, rate);\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t\t  \"%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\\n\",\n\t\t\t  __func__, path, rate, base, pw_by_rate_new);\n\t}\n#endif\n\n#if (RTL8197G_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8197G) {\n\t\tif (rate < 0x4)\n\t\t\ttxagc_tmp = config_phydm_read_txagc_8197g(dm, path,\n\t\t\t\t\t\t\t\t  rate,\n\t\t\t\t\t\t\t\t  PDM_CCK);\n\t\telse\n\t\t\ttxagc_tmp = config_phydm_read_txagc_8197g(dm, path,\n\t\t\t\t\t\t\t\t  rate,\n\t\t\t\t\t\t\t\t  PDM_OFDM);\n\n\t\tpw_by_rate_tmp = config_phydm_read_txagc_diff_8197g(dm, rate);\n\t\tbase = txagc_tmp - pw_by_rate_tmp;\n\t\tbase = base & 0x7f;\n\t\tif (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)\n\t\t\treturn false;\n\n\t\tpw_by_rate_new = (s8)(pwr_idx - base);\n\t\tret = phydm_write_txagc_1byte_8197g(dm, pw_by_rate_new, rate);\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t\t  \"%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\\n\",\n\t\t\t  __func__, path, rate, base, pw_by_rate_new);\n\t}\n#endif\n\n#if (RTL8197F_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8197F)\n\t\tret = config_phydm_write_txagc_8197f(dm, pwr_idx, path, rate);\n#endif\n\n#if (RTL8192F_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8192F)\n\t\tret = config_phydm_write_txagc_8192f(dm, pwr_idx, path, rate);\n#endif\n\n#if (RTL8721D_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8721D)\n\t\tret = config_phydm_write_txagc_8721d(dm, pwr_idx, path, rate);\n#endif\n\treturn ret;\n}\n\nu8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 ret = 0;\n\n#if (RTL8822B_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8822B)\n\t\tret = config_phydm_read_txagc_8822b(dm, path, hw_rate);\n#endif\n\n#if (RTL8197F_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8197F)\n\t\tret = config_phydm_read_txagc_8197f(dm, path, hw_rate);\n#endif\n\n#if (RTL8821C_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8821C)\n\t\tret = config_phydm_read_txagc_8821c(dm, path, hw_rate);\n#endif\n\n#if (RTL8195B_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8195B)\n\t\tret = config_phydm_read_txagc_8195b(dm, path, hw_rate);\n#endif\n\n/*@jj add 20170822*/\n#if (RTL8192F_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8192F)\n\t\tret = config_phydm_read_txagc_8192f(dm, path, hw_rate);\n#endif\n\n#if (RTL8198F_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8198F) {\n\t\tif (hw_rate < 0x4) {\n\t\t\tret = config_phydm_read_txagc_8198f(dm, path, hw_rate,\n\t\t\t\t\t\t\t    PDM_CCK);\n\t\t} else {\n\t\t\tret = config_phydm_read_txagc_8198f(dm, path, hw_rate,\n\t\t\t\t\t\t\t    PDM_OFDM);\n\t\t}\n\t}\n#endif\n\n#if (RTL8822C_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8822C) {\n\t\tif (hw_rate < 0x4) {\n\t\t\tret = config_phydm_read_txagc_8822c(dm, path, hw_rate,\n\t\t\t\t\t\t\t    PDM_CCK);\n\t\t} else {\n\t\t\tret = config_phydm_read_txagc_8822c(dm, path, hw_rate,\n\t\t\t\t\t\t\t    PDM_OFDM);\n\t\t}\n\t}\n#endif\n\n#if (RTL8814B_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8814B) {\n\t\tif (hw_rate < 0x4) {\n\t\t\tret = config_phydm_read_txagc_8814b(dm, path, hw_rate,\n\t\t\t\t\t\t\t    PDM_CCK);\n\t\t} else {\n\t\t\tret = config_phydm_read_txagc_8814b(dm, path, hw_rate,\n\t\t\t\t\t\t\t    PDM_OFDM);\n\t\t}\n\t}\n#endif\n\n#if (RTL8812F_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8812F) {\n\t\tif (hw_rate < 0x4) {\n\t\t\tret = config_phydm_read_txagc_8812f(dm, path, hw_rate,\n\t\t\t\t\t\t\t    PDM_CCK);\n\t\t} else {\n\t\t\tret = config_phydm_read_txagc_8812f(dm, path, hw_rate,\n\t\t\t\t\t\t\t    PDM_OFDM);\n\t\t}\n\t}\n#endif\n\n#if (RTL8197G_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8197G) {\n\t\tif (hw_rate < 0x4) {\n\t\t\tret = config_phydm_read_txagc_8197g(dm, path, hw_rate,\n\t\t\t\t\t\t\t    PDM_CCK);\n\t\t} else {\n\t\t\tret = config_phydm_read_txagc_8197g(dm, path, hw_rate,\n\t\t\t\t\t\t\t    PDM_OFDM);\n\t\t}\n\t}\n#endif\n\n#if (RTL8721D_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8721D)\n\t\tret = config_phydm_read_txagc_8721d(dm, path, hw_rate);\n#endif\n\treturn ret;\n}\n\nboolean\nphydm_api_switch_bw_channel(void *dm_void, u8 ch, u8 pri_ch,\n\t\t\t    enum channel_width bw)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tboolean ret = false;\n\n\tswitch (dm->support_ic_type) {\n#if (RTL8822B_SUPPORT)\n\tcase ODM_RTL8822B:\n\t\tret = config_phydm_switch_channel_bw_8822b(dm, ch, pri_ch, bw);\n\tbreak;\n#endif\n\n#if (RTL8197F_SUPPORT)\n\tcase ODM_RTL8197F:\n\t\tret = config_phydm_switch_channel_bw_8197f(dm, ch, pri_ch, bw);\n\tbreak;\n#endif\n\n#if (RTL8821C_SUPPORT)\n\tcase ODM_RTL8821C:\n\t\tret = config_phydm_switch_channel_bw_8821c(dm, ch, pri_ch, bw);\n\tbreak;\n#endif\n\n#if (RTL8192F_SUPPORT)\n\tcase ODM_RTL8192F:\n\t\tret = config_phydm_switch_channel_bw_8192f(dm, ch, pri_ch, bw);\n\tbreak;\n#endif\n\n#if (RTL8198F_SUPPORT)\n\tcase ODM_RTL8198F:\n\t\tret = config_phydm_switch_channel_bw_8198f(dm, ch, pri_ch, bw);\n\tbreak;\n#endif\n\n#if (RTL8822C_SUPPORT)\n\tcase ODM_RTL8822C:\n\t\tret = config_phydm_switch_channel_bw_8822c(dm, ch, pri_ch, bw);\n\tbreak;\n#endif\n\n#if (RTL8814B_SUPPORT)\n\tcase ODM_RTL8814B:\n\t\tret = config_phydm_switch_channel_bw_8814b(dm, ch, pri_ch, bw);\n\tbreak;\n#endif\n\n#if (RTL8812F_SUPPORT)\n\tcase ODM_RTL8812F:\n\t\tret = config_phydm_switch_channel_bw_8812f(dm, ch, pri_ch, bw);\n\tbreak;\n#endif\n\n#if (RTL8197G_SUPPORT)\n\tcase ODM_RTL8197G:\n\t\tret = config_phydm_switch_channel_bw_8197g(dm, ch, pri_ch, bw);\n\tbreak;\n#endif\n\n#if (RTL8721D_SUPPORT)\n\tcase ODM_RTL8721D:\n\t\tret = config_phydm_switch_channel_bw_8721d(dm, ch, pri_ch, bw);\n#endif\n\n\tdefault:\n\t\tbreak;\n\t}\n\treturn ret;\n}\n\nboolean\nphydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path,\n\t\t   enum bb_path tx_path_ctrl)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tboolean ret = false;\n\tboolean is_2tx = false;\n\n\tif (tx_path_ctrl == BB_PATH_AB)\n\t\tis_2tx = true;\n\n\tswitch (dm->support_ic_type) {\n\t#if (RTL8822B_SUPPORT)\n\tcase ODM_RTL8822B:\n\t\tret = config_phydm_trx_mode_8822b(dm, tx_path, rx_path,\n\t\t\t\t\t\t  tx_path_ctrl);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8197F_SUPPORT)\n\tcase ODM_RTL8197F:\n\t\tret = config_phydm_trx_mode_8197f(dm, tx_path, rx_path, is_2tx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8192F_SUPPORT)\n\tcase ODM_RTL8192F:\n\t\tret = config_phydm_trx_mode_8192f(dm, tx_path, rx_path, is_2tx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8198F_SUPPORT)\n\tcase ODM_RTL8198F:\n\t\tret = config_phydm_trx_mode_8198f(dm, tx_path, rx_path, is_2tx);\n\t\tbreak;\n\t#endif\n\n\t#if 0/*(RTL8814B_SUPPORT)*/\n\tcase ODM_RTL8814B:\n\t\tret = config_phydm_trx_mode_8814b(dm, tx_path, rx_path, is_2tx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8822C_SUPPORT)\n\tcase ODM_RTL8822C:\n\t\tret = config_phydm_trx_mode_8822c(dm, tx_path, rx_path,\n\t\t\t\t\t\t  tx_path_ctrl);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8812F_SUPPORT)\n\tcase ODM_RTL8812F:\n\t\tret = config_phydm_trx_mode_8812f(dm, tx_path, rx_path, is_2tx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8197G_SUPPORT)\n\tcase ODM_RTL8197G:\n\t\tret = config_phydm_trx_mode_8197g(dm, tx_path, rx_path, is_2tx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8721D_SUPPORT)\n\tcase ODM_RTL8721D:\n\t\tret = config_phydm_trx_mode_8721d(dm, tx_path, rx_path, is_2tx);\n\t\tbreak;\n\t#endif\n\t}\n\treturn ret;\n}\n#else\nu8 config_phydm_read_txagc_n(void *dm_void, enum rf_path path, u8 hw_rate)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 read_back_data = INVALID_TXAGC_DATA;\n\tu32 reg_txagc;\n\tu32 reg_mask;\n\t/* This function is for 92E/88E etc... */\n\t/* @Input need to be HW rate index, not driver rate index!!!! */\n\n\t/* @Error handling */\n\tif (path > RF_PATH_B || hw_rate > ODM_RATEMCS15) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"%s: unsupported path (%d)\\n\",\n\t\t\t  __func__, path);\n\t\treturn INVALID_TXAGC_DATA;\n\t}\n\n\tif (path == RF_PATH_A) {\n\t\tswitch (hw_rate) {\n\t\tcase ODM_RATE1M:\n\t\t\treg_txagc = R_0xe08;\n\t\t\treg_mask = 0x00007f00;\n\t\t\tbreak;\n\t\tcase ODM_RATE2M:\n\t\t\treg_txagc = R_0x86c;\n\t\t\treg_mask = 0x00007f00;\n\t\t\tbreak;\n\t\tcase ODM_RATE5_5M:\n\t\t\treg_txagc = R_0x86c;\n\t\t\treg_mask = 0x007f0000;\n\t\t\tbreak;\n\t\tcase ODM_RATE11M:\n\t\t\treg_txagc = R_0x86c;\n\t\t\treg_mask = 0x7f000000;\n\t\t\tbreak;\n\n\t\tcase ODM_RATE6M:\n\t\t\treg_txagc = R_0xe00;\n\t\t\treg_mask = 0x0000007f;\n\t\t\tbreak;\n\t\tcase ODM_RATE9M:\n\t\t\treg_txagc = R_0xe00;\n\t\t\treg_mask = 0x00007f00;\n\t\t\tbreak;\n\t\tcase ODM_RATE12M:\n\t\t\treg_txagc = R_0xe00;\n\t\t\treg_mask = 0x007f0000;\n\t\t\tbreak;\n\t\tcase ODM_RATE18M:\n\t\t\treg_txagc = R_0xe00;\n\t\t\treg_mask = 0x7f000000;\n\t\t\tbreak;\n\t\tcase ODM_RATE24M:\n\t\t\treg_txagc = R_0xe04;\n\t\t\treg_mask = 0x0000007f;\n\t\t\tbreak;\n\t\tcase ODM_RATE36M:\n\t\t\treg_txagc = R_0xe04;\n\t\t\treg_mask = 0x00007f00;\n\t\t\tbreak;\n\t\tcase ODM_RATE48M:\n\t\t\treg_txagc = R_0xe04;\n\t\t\treg_mask = 0x007f0000;\n\t\t\tbreak;\n\t\tcase ODM_RATE54M:\n\t\t\treg_txagc = R_0xe04;\n\t\t\treg_mask = 0x7f000000;\n\t\t\tbreak;\n\n\t\tcase ODM_RATEMCS0:\n\t\t\treg_txagc = R_0xe10;\n\t\t\treg_mask = 0x0000007f;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS1:\n\t\t\treg_txagc = R_0xe10;\n\t\t\treg_mask = 0x00007f00;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS2:\n\t\t\treg_txagc = R_0xe10;\n\t\t\treg_mask = 0x007f0000;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS3:\n\t\t\treg_txagc = R_0xe10;\n\t\t\treg_mask = 0x7f000000;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS4:\n\t\t\treg_txagc = R_0xe14;\n\t\t\treg_mask = 0x0000007f;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS5:\n\t\t\treg_txagc = R_0xe14;\n\t\t\treg_mask = 0x00007f00;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS6:\n\t\t\treg_txagc = R_0xe14;\n\t\t\treg_mask = 0x007f0000;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS7:\n\t\t\treg_txagc = R_0xe14;\n\t\t\treg_mask = 0x7f000000;\n\t\t\tbreak;\n\n\t\tcase ODM_RATEMCS8:\n\t\t\treg_txagc = R_0xe18;\n\t\t\treg_mask = 0x0000007f;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS9:\n\t\t\treg_txagc = R_0xe18;\n\t\t\treg_mask = 0x00007f00;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS10:\n\t\t\treg_txagc = R_0xe18;\n\t\t\treg_mask = 0x007f0000;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS11:\n\t\t\treg_txagc = R_0xe18;\n\t\t\treg_mask = 0x7f000000;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS12:\n\t\t\treg_txagc = R_0xe1c;\n\t\t\treg_mask = 0x0000007f;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS13:\n\t\t\treg_txagc = R_0xe1c;\n\t\t\treg_mask = 0x00007f00;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS14:\n\t\t\treg_txagc = R_0xe1c;\n\t\t\treg_mask = 0x007f0000;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS15:\n\t\t\treg_txagc = R_0xe1c;\n\t\t\treg_mask = 0x7f000000;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Invalid HWrate!\\n\");\n\t\t\tbreak;\n\t\t}\n\t} else if (path == RF_PATH_B) {\n\t\tswitch (hw_rate) {\n\t\tcase ODM_RATE1M:\n\t\t\treg_txagc = R_0x838;\n\t\t\treg_mask = 0x00007f00;\n\t\t\tbreak;\n\t\tcase ODM_RATE2M:\n\t\t\treg_txagc = R_0x838;\n\t\t\treg_mask = 0x007f0000;\n\t\t\tbreak;\n\t\tcase ODM_RATE5_5M:\n\t\t\treg_txagc = R_0x838;\n\t\t\treg_mask = 0x7f000000;\n\t\t\tbreak;\n\t\tcase ODM_RATE11M:\n\t\t\treg_txagc = R_0x86c;\n\t\t\treg_mask = 0x0000007f;\n\t\t\tbreak;\n\n\t\tcase ODM_RATE6M:\n\t\t\treg_txagc = R_0x830;\n\t\t\treg_mask = 0x0000007f;\n\t\t\tbreak;\n\t\tcase ODM_RATE9M:\n\t\t\treg_txagc = R_0x830;\n\t\t\treg_mask = 0x00007f00;\n\t\t\tbreak;\n\t\tcase ODM_RATE12M:\n\t\t\treg_txagc = R_0x830;\n\t\t\treg_mask = 0x007f0000;\n\t\t\tbreak;\n\t\tcase ODM_RATE18M:\n\t\t\treg_txagc = R_0x830;\n\t\t\treg_mask = 0x7f000000;\n\t\t\tbreak;\n\t\tcase ODM_RATE24M:\n\t\t\treg_txagc = R_0x834;\n\t\t\treg_mask = 0x0000007f;\n\t\t\tbreak;\n\t\tcase ODM_RATE36M:\n\t\t\treg_txagc = R_0x834;\n\t\t\treg_mask = 0x00007f00;\n\t\t\tbreak;\n\t\tcase ODM_RATE48M:\n\t\t\treg_txagc = R_0x834;\n\t\t\treg_mask = 0x007f0000;\n\t\t\tbreak;\n\t\tcase ODM_RATE54M:\n\t\t\treg_txagc = R_0x834;\n\t\t\treg_mask = 0x7f000000;\n\t\t\tbreak;\n\n\t\tcase ODM_RATEMCS0:\n\t\t\treg_txagc = R_0x83c;\n\t\t\treg_mask = 0x0000007f;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS1:\n\t\t\treg_txagc = R_0x83c;\n\t\t\treg_mask = 0x00007f00;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS2:\n\t\t\treg_txagc = R_0x83c;\n\t\t\treg_mask = 0x007f0000;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS3:\n\t\t\treg_txagc = R_0x83c;\n\t\t\treg_mask = 0x7f000000;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS4:\n\t\t\treg_txagc = R_0x848;\n\t\t\treg_mask = 0x0000007f;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS5:\n\t\t\treg_txagc = R_0x848;\n\t\t\treg_mask = 0x00007f00;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS6:\n\t\t\treg_txagc = R_0x848;\n\t\t\treg_mask = 0x007f0000;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS7:\n\t\t\treg_txagc = R_0x848;\n\t\t\treg_mask = 0x7f000000;\n\t\t\tbreak;\n\n\t\tcase ODM_RATEMCS8:\n\t\t\treg_txagc = R_0x84c;\n\t\t\treg_mask = 0x0000007f;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS9:\n\t\t\treg_txagc = R_0x84c;\n\t\t\treg_mask = 0x00007f00;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS10:\n\t\t\treg_txagc = R_0x84c;\n\t\t\treg_mask = 0x007f0000;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS11:\n\t\t\treg_txagc = R_0x84c;\n\t\t\treg_mask = 0x7f000000;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS12:\n\t\t\treg_txagc = R_0x868;\n\t\t\treg_mask = 0x0000007f;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS13:\n\t\t\treg_txagc = R_0x868;\n\t\t\treg_mask = 0x00007f00;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS14:\n\t\t\treg_txagc = R_0x868;\n\t\t\treg_mask = 0x007f0000;\n\t\t\tbreak;\n\t\tcase ODM_RATEMCS15:\n\t\t\treg_txagc = R_0x868;\n\t\t\treg_mask = 0x7f000000;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Invalid HWrate!\\n\");\n\t\t\tbreak;\n\t\t}\n\t} else {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Invalid RF path!!\\n\");\n\t}\n\tread_back_data = (u8)odm_get_bb_reg(dm, reg_txagc, reg_mask);\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"%s: path-%d rate index 0x%x = 0x%x\\n\",\n\t\t  __func__, path, hw_rate, read_back_data);\n\treturn read_back_data;\n}\n#endif\n\n#ifdef CONFIG_MCC_DM\n#ifdef DYN_ANT_WEIGHTING_SUPPORT\nvoid phydm_set_weighting_cmn(struct dm_struct *dm)\n{\n\tPHYDM_DBG(dm, DBG_COMP_MCC, \"%s\\n\", __func__);\n\todm_set_bb_reg(dm, 0xc04, (BIT(18) | BIT(21)), 0x0);\n\todm_set_bb_reg(dm, 0xe04, (BIT(18) | BIT(21)), 0x0);\n}\n\nvoid phydm_set_weighting_mcc(u8 b_equal_weighting, void *dm_void, u8 port)\n{\n\t/*u8 reg_8;*/\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;\n\tu8\tval_0x98e, val_0x98f, val_0x81b;\n\tu32 temp_reg;\n\n\tPHYDM_DBG(dm, DBG_COMP_MCC, \"ant_weighting_mcc, port = %d\\n\", port);\n\tif (b_equal_weighting) {\n\t\ttemp_reg = odm_get_bb_reg(dm, 0x98c, 0x00ff0000);\n\t\tval_0x98e = (u8)(temp_reg >> 16) & 0xc0;\n\t\ttemp_reg = odm_get_bb_reg(dm, 0x98c, 0xff000000);\n\t\tval_0x98f = (u8)(temp_reg >> 24) & 0x7f;\n\t\ttemp_reg = odm_get_bb_reg(dm, 0x818, 0xff000000);\n\t\tval_0x81b = (u8)(temp_reg >> 24) & 0xfd;\n\t\tPHYDM_DBG(dm, DBG_COMP_MCC, \"Equal weighting ,rssi_min = %d\\n\",\n\t\t\t  dm->rssi_min);\n\t\t/*equal weighting*/\n\t} else {\n\t\tval_0x98e = 0x44;\n\t\tval_0x98f = 0x43;\n\t\ttemp_reg = odm_get_bb_reg(dm, 0x818, 0xff000000);\n\t\tval_0x81b = (u8)(temp_reg >> 24) | BIT(2);\n\t\tPHYDM_DBG(dm, DBG_COMP_MCC, \"AGC weighting ,rssi_min = %d\\n\",\n\t\t\t  dm->rssi_min);\n\t\t/*fix sec_min_wgt = 1/2*/\n\t}\n\tmcc_dm->mcc_reg_id[2] = 0x2;\n\tmcc_dm->mcc_dm_reg[2] = 0x98e;\n\tmcc_dm->mcc_dm_val[2][port] = val_0x98e;\n\n\tmcc_dm->mcc_reg_id[3] = 0x3;\n\tmcc_dm->mcc_dm_reg[3] = 0x98f;\n\tmcc_dm->mcc_dm_val[3][port] = val_0x98f;\n\n\tmcc_dm->mcc_reg_id[4] = 0x4;\n\tmcc_dm->mcc_dm_reg[4] = 0x81b;\n\tmcc_dm->mcc_dm_val[4][port] = val_0x81b;\n}\n\nvoid phydm_dyn_ant_dec_mcc(u8 port, u8 rssi_in, void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 rssi_l2h = 43, rssi_h2l = 37;\n\n\tif (rssi_in == 0xff)\n\t\tphydm_set_weighting_mcc(FALSE, dm, port);\n\telse if (rssi_in >= rssi_l2h)\n\t\tphydm_set_weighting_mcc(TRUE, dm, port);\n\telse if (rssi_in <= rssi_h2l)\n\t\tphydm_set_weighting_mcc(FALSE, dm, port);\n}\n\nvoid phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;\n\tu8\ti;\n\n\tphydm_set_weighting_cmn(dm);\n\tfor (i = 0; i <= 1; i++)\n\t\tphydm_dyn_ant_dec_mcc(i, mcc_dm->mcc_rssi[i], dm);\n}\n#endif /*#ifdef DYN_ANT_WEIGHTING_SUPPORT*/\n\nvoid phydm_mcc_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;\n\tu8\ti;\n\n\t/*PHYDM_DBG(dm, DBG_COMP_MCC, (\"MCC init\\n\"));*/\n\tPHYDM_DBG(dm, DBG_COMP_MCC, \"MCC init\\n\");\n\tfor (i = 0; i < MCC_DM_REG_NUM; i++) {\n\t\tmcc_dm->mcc_reg_id[i] = 0xff;\n\t\tmcc_dm->mcc_dm_reg[i] = 0;\n\t\tmcc_dm->mcc_dm_val[i][0] = 0;\n\t\tmcc_dm->mcc_dm_val[i][1] = 0;\n\t}\n\tfor (i = 0; i < NUM_STA; i++) {\n\t\tmcc_dm->sta_macid[0][i] = 0xff;\n\t\tmcc_dm->sta_macid[1][i] = 0xff;\n\t}\n\t/* Function init */\n\tdm->is_stop_dym_ant_weighting = 0;\n}\n\nu8 phydm_check(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;\n\tstruct cmn_sta_info\t\t\t*p_entry = NULL;\n\tu8\tshift = 0;\n\tu8\ti = 0;\n\tu8\tj = 0;\n\tu8\trssi_min[2] = {0xff, 0xff};\n\tu8\tsta_num = 8;\n\tu8 mcc_macid = 0;\n\n\tfor (i = 0; i <= 1; i++) {\n\t\tfor (j = 0; j < sta_num; j++) {\n\t\t\tif (mcc_dm->sta_macid[i][j] != 0xff) {\n\t\t\t\tmcc_macid = mcc_dm->sta_macid[i][j];\n\t\t\t\tp_entry = dm->phydm_sta_info[mcc_macid];\n\t\t\t\tif (!p_entry) {\n\t\t\t\t\tPHYDM_DBG(dm, DBG_COMP_MCC,\n\t\t\t\t\t\t  \"PEntry NULL(mac=%d)\\n\",\n\t\t\t\t\t\t  mcc_dm->sta_macid[i][j]);\n\t\t\t\t\treturn _FAIL;\n\t\t\t\t}\n\t\t\t\tPHYDM_DBG(dm, DBG_COMP_MCC,\n\t\t\t\t\t  \"undec_smoothed_pwdb=%d\\n\",\n\t\t\t\t\t  p_entry->rssi_stat.rssi);\n\t\t\t\tif (p_entry->rssi_stat.rssi < rssi_min[i])\n\t\t\t\t\trssi_min[i] = p_entry->rssi_stat.rssi;\n\t\t\t}\n\t\t}\n\t}\n\tmcc_dm->mcc_rssi[0] = (u8)rssi_min[0];\n\tmcc_dm->mcc_rssi[1] = (u8)rssi_min[1];\n\treturn _SUCCESS;\n}\n\nvoid phydm_mcc_h2ccmd_rst(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;\n\tu8 i;\n\tu8 regid;\n\tu8 h2c_mcc[H2C_MAX_LENGTH];\n\n\t/* RST MCC */\n\tfor (i = 0; i < H2C_MAX_LENGTH; i++)\n\t\th2c_mcc[i] = 0xff;\n\th2c_mcc[0] = 0x00;\n\todm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, h2c_mcc);\n\tPHYDM_DBG(dm, DBG_COMP_MCC, \"MCC H2C RST\\n\");\n}\n\nvoid phydm_mcc_h2ccmd(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;\n\tu8 i;\n\tu8 regid;\n\tu8 h2c_mcc[H2C_MAX_LENGTH];\n\n\tif (mcc_dm->mcc_rf_ch[0] == 0xff && mcc_dm->mcc_rf_ch[1] == 0xff) {\n\t\tPHYDM_DBG(dm, DBG_COMP_MCC, \"MCC channel Error\\n\");\n\t\treturn;\n\t}\n\t/* Set Channel number */\n\tfor (i = 0; i < H2C_MAX_LENGTH; i++)\n\t\th2c_mcc[i] = 0xff;\n\th2c_mcc[0] = 0xe0;\n\th2c_mcc[1] = (u8)(mcc_dm->mcc_rf_ch[0]);\n\th2c_mcc[2] = (u8)(mcc_dm->mcc_rf_ch[0] >> 8);\n\th2c_mcc[3] = (u8)(mcc_dm->mcc_rf_ch[1]);\n\th2c_mcc[4] = (u8)(mcc_dm->mcc_rf_ch[1] >> 8);\n\th2c_mcc[5] = 0xff;\n\th2c_mcc[6] = 0xff;\n\todm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, h2c_mcc);\n\tPHYDM_DBG(dm, DBG_COMP_MCC,\n\t\t  \"MCC H2C SetCH: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\\n\",\n\t\t  h2c_mcc[0], h2c_mcc[1], h2c_mcc[2], h2c_mcc[3],\n\t\t  h2c_mcc[4], h2c_mcc[5], h2c_mcc[6]);\n\n\t/* Set Reg and value*/\n\tfor (i = 0; i < H2C_MAX_LENGTH; i++)\n\t\th2c_mcc[i] = 0xff;\n\n\tfor (i = 0; i < MCC_DM_REG_NUM; i++) {\n\t\tregid = mcc_dm->mcc_reg_id[i];\n\t\tif (regid != 0xff) {\n\t\t\th2c_mcc[0] = 0xa0 | (regid & 0x1f);\n\t\t\th2c_mcc[1] = (u8)(mcc_dm->mcc_dm_reg[i]);\n\t\t\th2c_mcc[2] = (u8)(mcc_dm->mcc_dm_reg[i] >> 8);\n\t\t\th2c_mcc[3] = mcc_dm->mcc_dm_val[i][0];\n\t\t\th2c_mcc[4] = mcc_dm->mcc_dm_val[i][1];\n\t\t\th2c_mcc[5] = 0xff;\n\t\t\th2c_mcc[6] = 0xff;\n\t\t\todm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH,\n\t\t\t\t\t h2c_mcc);\n\t\t\tPHYDM_DBG(dm, DBG_COMP_MCC,\n\t\t\t\t  \"MCC H2C: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\\n\",\n\t\t\t\t  h2c_mcc[0], h2c_mcc[1], h2c_mcc[2],\n\t\t\t\t  h2c_mcc[3], h2c_mcc[4],\n\t\t\t\t  h2c_mcc[5], h2c_mcc[6]);\n\t\t}\n\t}\n}\n\nvoid phydm_mcc_ctrl(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\n\tPHYDM_DBG(dm, DBG_COMP_MCC, \"MCC status: %x\\n\", mcc_dm->mcc_status);\n\t/*MCC stage no change*/\n\tif (mcc_dm->mcc_status == mcc_dm->mcc_pre_status)\n\t\treturn;\n\t/*Not in MCC stage*/\n\tif (mcc_dm->mcc_status == 0) {\n\t\t/* Enable normal Ant-weighting */\n\t\tdm->is_stop_dym_ant_weighting = 0;\n\t\t/* Enable normal DIG */\n\t\todm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, 0x20);\n\t} else {\n\t\t/* Disable normal Ant-weighting */\n\t\tdm->is_stop_dym_ant_weighting = 1;\n\t\t/* Enable normal DIG */\n\t\todm_pause_dig(dm, PHYDM_PAUSE_NO_SET, PHYDM_PAUSE_LEVEL_1,\n\t\t\t      0x20);\n\t}\n\tif (mcc_dm->mcc_status == 0 && mcc_dm->mcc_pre_status != 0)\n\t\tphydm_mcc_init(dm);\n\tmcc_dm->mcc_pre_status = mcc_dm->mcc_status;\n\t}\n\nvoid phydm_fill_mcccmd(void *dm_void, u8 regid, u16 reg_add,\n\t\t       u8 val0, u8 val1)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;\n\n\tmcc_dm->mcc_reg_id[regid] = regid;\n\tmcc_dm->mcc_dm_reg[regid] = reg_add;\n\tmcc_dm->mcc_dm_val[regid][0] = val0;\n\tmcc_dm->mcc_dm_val[regid][1] = val1;\n}\n\nvoid phydm_mcc_switch(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;\n\ts8 ret;\n\n\tphydm_mcc_ctrl(dm);\n\tif (mcc_dm->mcc_status == 0) {/*Not in MCC stage*/\n\t\tphydm_mcc_h2ccmd_rst(dm);\n\t\treturn;\n\t}\n\tPHYDM_DBG(dm, DBG_COMP_MCC, \"MCC switch\\n\");\n\tret = phydm_check(dm);\n\tif (ret == _FAIL) {\n\t\tPHYDM_DBG(dm, DBG_COMP_MCC, \"MCC check fail\\n\");\n\t\treturn;\n\t}\n\t/* Set IGI*/\n\tphydm_mcc_igi_cal(dm);\n\n\t/* Set Antenna Gain*/\n#if (RTL8822B_SUPPORT == 1)\n\tphydm_dynamic_ant_weighting_mcc_8822b(dm);\n#endif\n\t/* Set H2C Cmd*/\n\tphydm_mcc_h2ccmd(dm);\n}\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid phydm_normal_driver_rx_sniffer(\n\tstruct dm_struct *dm,\n\tu8 *desc,\n\tPRT_RFD_STATUS rt_rfd_status,\n\tu8 *drv_info,\n\tu8 phy_status)\n{\n#if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING))\n\tu32 *msg;\n\tu16 seq_num;\n\n\tif (rt_rfd_status->packet_report_type != NORMAL_RX)\n\t\treturn;\n\n\tif (!dm->is_linked) {\n\t\tif (rt_rfd_status->is_hw_error)\n\t\t\treturn;\n\t}\n\n\tif (phy_status == true) {\n\t\tif (dm->rx_pkt_type == type_block_ack ||\n\t\t    dm->rx_pkt_type == type_rts || dm->rx_pkt_type == type_cts)\n\t\t\tseq_num = 0;\n\t\telse\n\t\t\tseq_num = rt_rfd_status->seq_num;\n\n\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER,\n\t\t\t    \"%04d , %01s, rate=0x%02x, L=%04d , %s , %s\",\n\t\t\t    seq_num,\n\t\t\t    /*rt_rfd_status->mac_id,*/\n\t\t\t    (rt_rfd_status->is_crc ? \"C\" :\n\t\t\t    rt_rfd_status->is_ampdu ? \"A\" : \"_\"),\n\t\t\t    rt_rfd_status->data_rate,\n\t\t\t    rt_rfd_status->length,\n\t\t\t    ((rt_rfd_status->band_width == 0) ? \"20M\" :\n\t\t\t    ((rt_rfd_status->band_width == 1) ? \"40M\" : \"80M\")),\n\t\t\t    (rt_rfd_status->is_ldpc ? \"LDP\" : \"BCC\"));\n\n\t\tif (dm->rx_pkt_type == type_asoc_req)\n\t\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER, \" , [%s]\", \"AS_REQ\");\n\t\telse if (dm->rx_pkt_type == type_asoc_rsp)\n\t\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER, \" , [%s]\", \"AS_RSP\");\n\t\telse if (dm->rx_pkt_type == type_probe_req)\n\t\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER, \" , [%s]\", \"PR_REQ\");\n\t\telse if (dm->rx_pkt_type == type_probe_rsp)\n\t\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER, \" , [%s]\", \"PR_RSP\");\n\t\telse if (dm->rx_pkt_type == type_deauth)\n\t\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER, \" , [%s]\", \"DEAUTH\");\n\t\telse if (dm->rx_pkt_type == type_beacon)\n\t\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER, \" , [%s]\", \"BEACON\");\n\t\telse if (dm->rx_pkt_type == type_block_ack_req)\n\t\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER, \" , [%s]\", \"BA_REQ\");\n\t\telse if (dm->rx_pkt_type == type_rts)\n\t\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER, \" , [%s]\", \"__RTS_\");\n\t\telse if (dm->rx_pkt_type == type_cts)\n\t\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER, \" , [%s]\", \"__CTS_\");\n\t\telse if (dm->rx_pkt_type == type_ack)\n\t\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER, \" , [%s]\", \"__ACK_\");\n\t\telse if (dm->rx_pkt_type == type_block_ack)\n\t\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER, \" , [%s]\", \"__BA__\");\n\t\telse if (dm->rx_pkt_type == type_data)\n\t\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER, \" , [%s]\", \"_DATA_\");\n\t\telse if (dm->rx_pkt_type == type_data_ack)\n\t\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER, \" , [%s]\", \"Data_Ack\");\n\t\telse if (dm->rx_pkt_type == type_qos_data)\n\t\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER, \" , [%s]\", \"QoS_Data\");\n\t\telse\n\t\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER, \" , [0x%x]\",\n\t\t\t\t    dm->rx_pkt_type);\n\n\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER, \" , [RSSI=%d,%d,%d,%d ]\",\n\t\t\t    dm->rssi_a,\n\t\t\t    dm->rssi_b,\n\t\t\t    dm->rssi_c,\n\t\t\t    dm->rssi_d);\n\n\t\tmsg = (u32 *)drv_info;\n\n\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER,\n\t\t\t    \" , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\\n\",\n\t\t\t    msg[6], msg[5], msg[4], msg[3],\n\t\t\t    msg[2], msg[1], msg[1]);\n\t} else {\n\t\tPHYDM_DBG_F(dm, ODM_COMP_SNIFFER,\n\t\t\t    \"%04d , %01s, rate=0x%02x, L=%04d , %s , %s\\n\",\n\t\t\t    rt_rfd_status->seq_num,\n\t\t\t    /*rt_rfd_status->mac_id,*/\n\t\t\t    (rt_rfd_status->is_crc ? \"C\" :\n\t\t\t    (rt_rfd_status->is_ampdu) ? \"A\" : \"_\"),\n\t\t\t    rt_rfd_status->data_rate,\n\t\t\t    rt_rfd_status->length,\n\t\t\t    ((rt_rfd_status->band_width == 0) ? \"20M\" :\n\t\t\t    ((rt_rfd_status->band_width == 1) ? \"40M\" : \"80M\")),\n\t\t\t    (rt_rfd_status->is_ldpc ? \"LDP\" : \"BCC\"));\n\t}\n\n#endif\n}\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_api.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDM_API_H__\n#define __PHYDM_API_H__\n\n#define PHYDM_API_VERSION \"1.0\" /* @2017.07.10  Dino, Add phydm_api.h*/\n\n/* @1 ============================================================\n * 1  Definition\n * 1 ============================================================\n */\n#define CN_CNT_MAX 10 /*@max condition number threshold*/\n\n#define FUNC_ENABLE 1\n#define FUNC_DISABLE 2\n\n/*@NBI API------------------------------------*/\n#define NBI_128TONE 27 /*register table size*/\n#define NBI_256TONE 59 /*register table size*/\n\n#define NUM_START_CH_80M 7\n#define NUM_START_CH_40M 14\n\n#define CH_OFFSET_40M 2\n#define CH_OFFSET_80M 6\n\n#define FFT_128_TYPE 1\n#define FFT_256_TYPE 2\n\n#define FREQ_POSITIVE 1\n#define FREQ_NEGATIVE 2\n/*@------------------------------------------------*/\n\nenum phystat_rpt {\n\tPHY_PWDB = 0,\n\tPHY_EVM = 1,\n\tPHY_CFO = 2,\n\tPHY_RXSNR = 3,\n\tPHY_LGAIN = 4,\n\tPHY_HT_AAGC_GAIN = 5,\n};\n\n#ifndef PHYDM_COMMON_API_SUPPORT\n#define INVALID_RF_DATA 0xffffffff\n#define INVALID_TXAGC_DATA 0xff\n#endif\n\n/* @1 ============================================================\n * 1  structure\n * 1 ============================================================\n */\n\nstruct phydm_api_stuc {\n\tu32 rxiqc_reg1; /*N-mode: for pathA REG0xc14*/\n\tu32 rxiqc_reg2; /*N-mode: for pathB REG0xc1c*/\n\tu8 tx_queue_bitmap; /*REG0x520[23:16]*/\n\tu8 ccktx_path;\n};\n\n/* @1 ============================================================\n * 1  enumeration\n * 1 ============================================================\n */\n\n/* @1 ============================================================\n * 1  function prototype\n * 1 ============================================================\n */\nvoid phydm_reset_bb_hw_cnt(void *dm_void);\n\nvoid phydm_dynamic_ant_weighting(void *dm_void);\n\n#ifdef DYN_ANT_WEIGHTING_SUPPORT\nvoid phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used,\n\t\t\t  char *output, u32 *_out_len);\n#endif\n\nvoid phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path);\n\nvoid phydm_config_ofdm_rx_path(void *dm_void, u32 path);\n\nvoid phydm_config_cck_rx_path(void *dm_void, enum bb_path path);\n\nvoid phydm_config_cck_rx_antenna_init(void *dm_void);\n\nvoid phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used,\n\t\t\t   char *output, u32 *_out_len);\n\nvoid phydm_tx_2path(void *dm_void);\n\nvoid phydm_stop_3_wire(void *dm_void, u8 set_type);\n\nu8 phydm_stop_ic_trx(void *dm_void, u8 set_type);\n\nvoid phydm_dis_cck_trx(void *dm_void, u8 set_type);\n\nvoid phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch);\n\nvoid phydm_nbi_enable(void *dm_void, u32 enable);\n\nu8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,\n\t\t\t  u32 sec_ch);\n\nu8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,\n\t\t     u32 sec_ch);\n\nvoid phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t     char *output, u32 *_out_len);\n\nvoid phydm_csi_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t     char *output, u32 *_out_len);\n\nvoid phydm_stop_ck320(void *dm_void, u8 enable);\n\nboolean\nphydm_set_bb_txagc_offset(void *dm_void, s8 power_offset, u8 add_half_db);\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\nu8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw,\n\t\t\t       u32 f_intf, u32 sec_ch, u8 wgt);\n\nvoid phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,\n\t\t\t     u8 wgt);\n\nu8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,\n\t\t\t  u32 sec_ch, u8 path);\n\nvoid phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,\n\t\t\t    u8 path);\n\nvoid phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path);\n\nu8 phydm_phystat_rpt_jgr3(void *dm_void, enum phystat_rpt info,\n\t\t\t  enum rf_path ant_path);\nvoid phydm_user_position_for_sniffer(void *dm_void, u8 user_position);\n\n#endif\n\n#ifdef PHYDM_COMMON_API_SUPPORT\nboolean\nphydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path,\n\t\t      boolean is_positive);\nboolean\nphydm_api_set_txagc(void *dm_void, u32 power_index, enum rf_path path,\n\t\t    u8 hw_rate, boolean is_single_rate);\n\nu8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate);\n\nboolean\nphydm_api_switch_bw_channel(void *dm_void, u8 central_ch, u8 primary_ch_idx,\n\t\t\t    enum channel_width bandwidth);\n\nboolean\nphydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path,\n\t\t   enum bb_path tx_path_ctrl);\n\n#endif\n\n#ifdef CONFIG_MCC_DM\n#ifdef DYN_ANT_WEIGHTING_SUPPORT\nvoid phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void);\n#endif /*#ifdef DYN_ANT_WEIGHTING_SUPPORT*/\nvoid phydm_fill_mcccmd(void *dm_void, u8 regid, u16 reg_add,\n\t\t       u8 val0,\tu8 val1);\nu8 phydm_check(void *dm_void);\nvoid phydm_mcc_init(void *dm_void);\nvoid phydm_mcc_switch(void *dm_void);\n#endif /*#ifdef CONFIG_MCC_DM*/\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_auto_dbg.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*************************************************************\n * include files\n ************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#ifdef PHYDM_AUTO_DEGBUG\n\nvoid phydm_check_hang_reset(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;\n\n\tatd_t->dbg_step = 0;\n\tatd_t->auto_dbg_type = AUTO_DBG_STOP;\n\tphydm_pause_dm_watchdog(dm, PHYDM_RESUME);\n\tdm->debug_components &= (~ODM_COMP_API);\n}\n\nvoid phydm_check_hang_init(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;\n\n\tatd_t->dbg_step = 0;\n\tatd_t->auto_dbg_type = AUTO_DBG_STOP;\n\tphydm_pause_dm_watchdog(dm, PHYDM_RESUME);\n}\n\n#if (ODM_IC_11N_SERIES_SUPPORT == 1)\nvoid phydm_auto_check_hang_engine_n(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;\n\tstruct n_dbgport_803 dbgport_803 = {0};\n\tu32 value32_tmp = 0, value32_tmp_2 = 0;\n\tu8 i;\n\tu32 curr_dbg_port_val[DBGPORT_CHK_NUM];\n\tu16 curr_ofdm_t_cnt;\n\tu16 curr_ofdm_r_cnt;\n\tu16 curr_cck_t_cnt;\n\tu16 curr_cck_r_cnt;\n\tu16 curr_ofdm_crc_error_cnt;\n\tu16 curr_cck_crc_error_cnt;\n\tu16 diff_ofdm_t_cnt;\n\tu16 diff_ofdm_r_cnt;\n\tu16 diff_cck_t_cnt;\n\tu16 diff_cck_r_cnt;\n\tu16 diff_ofdm_crc_error_cnt;\n\tu16 diff_cck_crc_error_cnt;\n\tu8 rf_mode;\n\n\tif (atd_t->auto_dbg_type == AUTO_DBG_STOP)\n\t\treturn;\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\tphydm_check_hang_reset(dm);\n\t\treturn;\n\t}\n\n\tif (atd_t->dbg_step == 0) {\n\t\tpr_debug(\"dbg_step=0\\n\\n\");\n\n\t\t/*Reset all packet counter*/\n\t\todm_set_bb_reg(dm, R_0xf14, BIT(16), 1);\n\t\todm_set_bb_reg(dm, R_0xf14, BIT(16), 0);\n\n\t} else if (atd_t->dbg_step == 1) {\n\t\tpr_debug(\"dbg_step=1\\n\\n\");\n\n\t\t/*Check packet counter Register*/\n\t\tatd_t->ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD);\n\t\tatd_t->ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD);\n\t\tatd_t->ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94,\n\t\t\t\t\t\t\t\tMASKHWORD);\n\n\t\tatd_t->cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD);\n\t\tatd_t->cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD);\n\t\tatd_t->cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84,\n\t\t\t\t\t\t\t       0x3fff);\n\n\t\t/*Check Debug Port*/\n\t\tfor (i = 0; i < DBGPORT_CHK_NUM; i++) {\n\t\t\tif (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3,\n\t\t\t\t\t\t  (u32)atd_t->dbg_port_table[i])\n\t\t\t\t\t\t  ) {\n\t\t\t\tatd_t->dbg_port_val[i] =\n\t\t\t\t\tphydm_get_bb_dbg_port_val(dm);\n\t\t\t\tphydm_release_bb_dbg_port(dm);\n\t\t\t}\n\t\t}\n\n\t} else if (atd_t->dbg_step == 2) {\n\t\tpr_debug(\"dbg_step=2\\n\\n\");\n\n\t\t/*Check packet counter Register*/\n\t\tcurr_ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD);\n\t\tcurr_ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD);\n\t\tcurr_ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94,\n\t\t\t\t\t\t\t      MASKHWORD);\n\n\t\tcurr_cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD);\n\t\tcurr_cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD);\n\t\tcurr_cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84,\n\t\t\t\t\t\t\t     0x3fff);\n\n\t\t/*Check Debug Port*/\n\t\tfor (i = 0; i < DBGPORT_CHK_NUM; i++) {\n\t\t\tif (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3,\n\t\t\t\t\t\t  (u32)atd_t->dbg_port_table[i])\n\t\t\t\t\t\t  ) {\n\t\t\t\tcurr_dbg_port_val[i] =\n\t\t\t\t\tphydm_get_bb_dbg_port_val(dm);\n\t\t\t\tphydm_release_bb_dbg_port(dm);\n\t\t\t}\n\t\t}\n\n\t\t/*=== Make check hang decision ===============================*/\n\t\tpr_debug(\"Check Hang Decision\\n\\n\");\n\n\t\t/* ----- Check RF Register -----------------------------------*/\n\t\tfor (i = 0; i < dm->num_rf_path; i++) {\n\t\t\trf_mode = (u8)odm_get_rf_reg(dm, i, RF_0x0, 0xf0000);\n\t\t\tpr_debug(\"RF0x0[%d] = 0x%x\\n\", i, rf_mode);\n\t\t\tif (rf_mode > 3) {\n\t\t\t\tpr_debug(\"Incorrect RF mode\\n\");\n\t\t\t\tpr_debug(\"ReasonCode:RHN-1\\n\");\n\t\t\t}\n\t\t}\n\t\tvalue32_tmp = odm_get_rf_reg(dm, 0, RF_0xb0, 0xf0000);\n\t\tif (dm->support_ic_type == ODM_RTL8188E) {\n\t\t\tif (value32_tmp != 0xff8c8) {\n\t\t\t\tpr_debug(\"ReasonCode:RHN-3\\n\");\n\t\t\t}\n\t\t}\n\t\t/* ----- Check BB Register ----------------------------------*/\n\t\t/*BB mode table*/\n\t\tvalue32_tmp = odm_get_bb_reg(dm, R_0x824, 0xe);\n\t\tvalue32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0xe);\n\t\tpr_debug(\"BB TX mode table {A, B}= {%d, %d}\\n\",\n\t\t\t value32_tmp, value32_tmp_2);\n\n\t\tif (value32_tmp > 3 || value32_tmp_2 > 3) {\n\t\t\tpr_debug(\"ReasonCode:RHN-2\\n\");\n\t\t}\n\n\t\tvalue32_tmp = odm_get_bb_reg(dm, R_0x824, 0x700000);\n\t\tvalue32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0x700000);\n\t\tpr_debug(\"BB RX mode table {A, B}= {%d, %d}\\n\", value32_tmp,\n\t\t\t value32_tmp_2);\n\n\t\tif (value32_tmp > 3 || value32_tmp_2 > 3) {\n\t\t\tpr_debug(\"ReasonCode:RHN-2\\n\");\n\t\t}\n\n\t\t/*BB HW Block*/\n\t\tvalue32_tmp = odm_get_bb_reg(dm, R_0x800, MASKDWORD);\n\n\t\tif (!(value32_tmp & BIT(24))) {\n\t\t\tpr_debug(\"Reg0x800[24] = 0, CCK BLK is disabled\\n\");\n\t\t\tpr_debug(\"ReasonCode: THN-3\\n\");\n\t\t}\n\n\t\tif (!(value32_tmp & BIT(25))) {\n\t\t\tpr_debug(\"Reg0x800[24] = 0, OFDM BLK is disabled\\n\");\n\t\t\tpr_debug(\"ReasonCode:THN-3\\n\");\n\t\t}\n\n\t\t/*BB Continue TX*/\n\t\tvalue32_tmp = odm_get_bb_reg(dm, R_0xd00, 0x70000000);\n\t\tpr_debug(\"Continue TX=%d\\n\", value32_tmp);\n\t\tif (value32_tmp != 0) {\n\t\t\tpr_debug(\"ReasonCode: THN-4\\n\");\n\t\t}\n\n\t\t/* ----- Check Packet Counter --------------------------------*/\n\t\tdiff_ofdm_t_cnt = curr_ofdm_t_cnt - atd_t->ofdm_t_cnt;\n\t\tdiff_ofdm_r_cnt = curr_ofdm_r_cnt - atd_t->ofdm_r_cnt;\n\t\tdiff_ofdm_crc_error_cnt = curr_ofdm_crc_error_cnt -\n\t\t\t\t\t  atd_t->ofdm_crc_error_cnt;\n\n\t\tdiff_cck_t_cnt = curr_cck_t_cnt - atd_t->cck_t_cnt;\n\t\tdiff_cck_r_cnt = curr_cck_r_cnt - atd_t->cck_r_cnt;\n\t\tdiff_cck_crc_error_cnt = curr_cck_crc_error_cnt -\n\t\t\t\t\t atd_t->cck_crc_error_cnt;\n\n\t\tpr_debug(\"OFDM[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\\n\",\n\t\t\t atd_t->ofdm_t_cnt, atd_t->ofdm_r_cnt,\n\t\t\t atd_t->ofdm_crc_error_cnt);\n\t\tpr_debug(\"OFDM[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\\n\",\n\t\t\t curr_ofdm_t_cnt, curr_ofdm_r_cnt,\n\t\t\t curr_ofdm_crc_error_cnt);\n\t\tpr_debug(\"OFDM_diff {TX, RX, CRC_error} = {%d, %d, %d}\\n\",\n\t\t\t diff_ofdm_t_cnt, diff_ofdm_r_cnt,\n\t\t\t diff_ofdm_crc_error_cnt);\n\n\t\tpr_debug(\"CCK[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\\n\",\n\t\t\t atd_t->cck_t_cnt, atd_t->cck_r_cnt,\n\t\t\t atd_t->cck_crc_error_cnt);\n\t\tpr_debug(\"CCK[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\\n\",\n\t\t\t curr_cck_t_cnt, curr_cck_r_cnt,\n\t\t\t curr_cck_crc_error_cnt);\n\t\tpr_debug(\"CCK_diff {TX, RX, CRC_error} = {%d, %d, %d}\\n\",\n\t\t\t diff_cck_t_cnt, diff_cck_r_cnt,\n\t\t\t diff_cck_crc_error_cnt);\n\n\t\t/* ----- Check Dbg Port --------------------------------*/\n\n\t\tfor (i = 0; i < DBGPORT_CHK_NUM; i++) {\n\t\t\tpr_debug(\"Dbg_port=((0x%x))\\n\",\n\t\t\t\t atd_t->dbg_port_table[i]);\n\t\t\tpr_debug(\"Val{pre, curr}={0x%x, 0x%x}\\n\",\n\t\t\t\t atd_t->dbg_port_val[i], curr_dbg_port_val[i]);\n\n\t\t\tif (atd_t->dbg_port_table[i] == 0) {\n\t\t\t\tif (atd_t->dbg_port_val[i] ==\n\t\t\t\t    curr_dbg_port_val[i]) {\n\t\t\t\t\tpr_debug(\"BB state hang\\n\");\n\t\t\t\t\tpr_debug(\"ReasonCode:\\n\");\n\t\t\t\t}\n\n\t\t\t} else if (atd_t->dbg_port_table[i] == 0x803) {\n\t\t\t\tif (atd_t->dbg_port_val[i] ==\n\t\t\t\t    curr_dbg_port_val[i]) {\n\t\t\t\t\t/* dbgport_803 =  */\n\t\t\t\t\t/* (struct n_dbgport_803 )   */\n\t\t\t\t\t/* (atd_t->dbg_port_val[i]); */\n\t\t\t\t\todm_move_memory(dm, &dbgport_803,\n\t\t\t\t\t\t\t&atd_t->dbg_port_val[i],\n\t\t\t\t\t\t\tsizeof(struct n_dbgport_803));\n\t\t\t\t\tpr_debug(\"RSTB{BB, GLB, OFDM}={%d, %d,%d}\\n\",\n\t\t\t\t\t\t dbgport_803.bb_rst_b,\n\t\t\t\t\t\t dbgport_803.glb_rst_b,\n\t\t\t\t\t\t dbgport_803.ofdm_rst_b);\n\t\t\t\t\tpr_debug(\"{ofdm_tx_en, cck_tx_en, phy_tx_on}={%d, %d, %d}\\n\",\n\t\t\t\t\t\t dbgport_803.ofdm_tx_en,\n\t\t\t\t\t\t dbgport_803.cck_tx_en,\n\t\t\t\t\t\t dbgport_803.phy_tx_on);\n\t\t\t\t\tpr_debug(\"CCA_PP{OFDM, CCK}={%d, %d}\\n\",\n\t\t\t\t\t\t dbgport_803.ofdm_cca_pp,\n\t\t\t\t\t\t dbgport_803.cck_cca_pp);\n\n\t\t\t\t\tif (dbgport_803.phy_tx_on)\n\t\t\t\t\t\tpr_debug(\"Maybe TX Hang\\n\");\n\t\t\t\t\telse if (dbgport_803.ofdm_cca_pp ||\n\t\t\t\t\t\t dbgport_803.cck_cca_pp)\n\t\t\t\t\t\tpr_debug(\"Maybe RX Hang\\n\");\n\t\t\t\t}\n\n\t\t\t} else if (atd_t->dbg_port_table[i] == 0x208) {\n\t\t\t\tif ((atd_t->dbg_port_val[i] & BIT(30)) &&\n\t\t\t\t    (curr_dbg_port_val[i] & BIT(30))) {\n\t\t\t\t\tpr_debug(\"EDCCA Pause TX\\n\");\n\t\t\t\t\tpr_debug(\"ReasonCode: THN-2\\n\");\n\t\t\t\t}\n\n\t\t\t} else if (atd_t->dbg_port_table[i] == 0xab0) {\n\t\t\t\t/* atd_t->dbg_port_val[i] & 0xffffff == 0 */\n\t\t\t\t/* curr_dbg_port_val[i] & 0xffffff == 0 */\n\t\t\t\tif (((atd_t->dbg_port_val[i] &\n\t\t\t\t      MASK24BITS) == 0) ||\n\t\t\t\t    ((curr_dbg_port_val[i] &\n\t\t\t\t      MASK24BITS) == 0)) {\n\t\t\t\t\tpr_debug(\"Wrong L-SIG formate\\n\");\n\t\t\t\t\tpr_debug(\"ReasonCode: THN-1\\n\");\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tphydm_check_hang_reset(dm);\n\t}\n\n\tatd_t->dbg_step++;\n}\n\nvoid phydm_bb_auto_check_hang_start_n(\n\tvoid *dm_void,\n\tu32 *_used,\n\tchar *output,\n\tu32 *_out_len)\n{\n\tu32 value32 = 0;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES)\n\t\treturn;\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"PHYDM auto check hang (N-series) is started, Please check the system log\\n\");\n\n\tdm->debug_components |= ODM_COMP_API;\n\tatd_t->auto_dbg_type = AUTO_DBG_CHECK_HANG;\n\tatd_t->dbg_step = 0;\n\n\tphydm_pause_dm_watchdog(dm, PHYDM_PAUSE);\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_dbg_port_dump_n(void *dm_void, u32 *_used, char *output,\n\t\t\t   u32 *_out_len)\n{\n\tu32 value32 = 0;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES)\n\t\treturn;\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"not support now\\n\");\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\n#endif\n\n#if (ODM_IC_11AC_SERIES_SUPPORT == 1)\nvoid phydm_dbg_port_dump_ac(void *dm_void, u32 *_used, char *output,\n\t\t\t    u32 *_out_len)\n{\n\tu32 value32 = 0;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\tif (dm->support_ic_type & ODM_IC_11N_SERIES)\n\t\treturn;\n\n\tvalue32 = odm_get_bb_reg(dm, R_0xf80, MASKDWORD);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = 0x%x\", \"rptreg of sc/bw/ht/...\", value32);\n\n\tif (dm->support_ic_type & ODM_RTL8822B)\n\t\todm_set_bb_reg(dm, R_0x198c, BIT(2) | BIT(1) | BIT(0), 7);\n\n\t/* dbg_port = basic state machine */\n\t{\n\t\todm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x000);\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"0x8fc\", value32);\n\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"basic state machine\", value32);\n\t}\n\n\t/* dbg_port = state machine */\n\t{\n\t\todm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x007);\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"0x8fc\", value32);\n\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"state machine\", value32);\n\t}\n\n\t/* dbg_port = CCA-related*/\n\t{\n\t\todm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x204);\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"0x8fc\", value32);\n\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"CCA-related\", value32);\n\t}\n\n\t/* dbg_port = edcca/rxd*/\n\t{\n\t\todm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x278);\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"0x8fc\", value32);\n\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"edcca/rxd\", value32);\n\t}\n\n\t/* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/\n\t{\n\t\todm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x290);\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"0x8fc\", value32);\n\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\",\n\t\t\t \"rx_state/mux_state/ADC_MASK_OFDM\", value32);\n\t}\n\n\t/* dbg_port = bf-related*/\n\t{\n\t\todm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B2);\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"0x8fc\", value32);\n\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"bf-related\", value32);\n\t}\n\n\t/* dbg_port = bf-related*/\n\t{\n\t\todm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B8);\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"0x8fc\", value32);\n\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"bf-related\", value32);\n\t}\n\n\t/* dbg_port = txon/rxd*/\n\t{\n\t\todm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA03);\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"0x8fc\", value32);\n\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"txon/rxd\", value32);\n\t}\n\n\t/* dbg_port = l_rate/l_length*/\n\t{\n\t\todm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0B);\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"0x8fc\", value32);\n\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"l_rate/l_length\", value32);\n\t}\n\n\t/* dbg_port = rxd/rxd_hit*/\n\t{\n\t\todm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0D);\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"0x8fc\", value32);\n\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"rxd/rxd_hit\", value32);\n\t}\n\n\t/* dbg_port = dis_cca*/\n\t{\n\t\todm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAA0);\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"0x8fc\", value32);\n\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"dis_cca\", value32);\n\t}\n\n\t/* dbg_port = tx*/\n\t{\n\t\todm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAB0);\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"0x8fc\", value32);\n\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"tx\", value32);\n\t}\n\n\t/* dbg_port = rx plcp*/\n\t{\n\t\todm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD0);\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"0x8fc\", value32);\n\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"rx plcp\", value32);\n\n\t\todm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD1);\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"0x8fc\", value32);\n\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"rx plcp\", value32);\n\n\t\todm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD2);\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"0x8fc\", value32);\n\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"rx plcp\", value32);\n\n\t\todm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD3);\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"0x8fc\", value32);\n\n\t\tvalue32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = 0x%x\", \"rx plcp\", value32);\n\t}\n\t*_used = used;\n\t*_out_len = out_len;\n}\n#endif\n\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\nvoid phydm_dbg_port_dump_jgr3(void *dm_void, u32 *_used, char *output,\n\t\t\t      u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\t/*u32 dbg_port_idx_all[3] = {0x000, 0x001, 0x002};*/\n\tu32 val = 0;\n\tu32 dbg_port_idx = 0;\n\tu32 i = 0;\n\n\tif (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))\n\t\treturn;\n\n\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t      \"%-17s = %s\\n\", \"DbgPort index\", \"Value\");\n\n#if 0\n\t/*0x000/0x001/0x002*/\n\tfor (i = 0; i < 3; i++) {\n\t\tdbg_port_idx = dbg_port_idx_all[i];\n\t\tif (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port_idx)) {\n\t\t\tval = phydm_get_bb_dbg_port_val(dm);\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"0x%-15x = 0x%x\\n\", dbg_port_idx, val);\n\t\t\tphydm_release_bb_dbg_port(dm);\n\t\t}\n\t}\n#endif\n\tfor (dbg_port_idx = 0x0; dbg_port_idx <= 0xfff; dbg_port_idx++) {\n\t\tif (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port_idx)) {\n\t\t\tval = phydm_get_bb_dbg_port_val(dm);\n\t\t\tPDM_VAST_SNPF(out_len, used, output + used,\n\t\t\t\t      out_len - used,\n\t\t\t\t      \"0x%-15x = 0x%x\\n\", dbg_port_idx, val);\n\t\t\tphydm_release_bb_dbg_port(dm);\n\t\t}\n\t}\n\t*_used = used;\n\t*_out_len = out_len;\n}\n#endif\n\nvoid phydm_dbg_port_dump(void *dm_void, u32 *_used, char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t      \"------ BB debug port start ------\\n\");\n\n\tswitch (dm->ic_ip_series) {\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\tcase PHYDM_IC_JGR3:\n\t\tphydm_dbg_port_dump_jgr3(dm, &used, output, &out_len);\n\t\tbreak;\n\t#endif\n\n\t#if (ODM_IC_11AC_SERIES_SUPPORT == 1)\n\tcase PHYDM_IC_AC:\n\t\tphydm_dbg_port_dump_ac(dm, &used, output, &out_len);\n\t\tbreak;\n\t#endif\n\n\t#if (ODM_IC_11N_SERIES_SUPPORT == 1)\n\tcase PHYDM_IC_N:\n\t\tphydm_dbg_port_dump_n(dm, &used, output, &out_len);\n\t\tbreak;\n\t#endif\n\n\tdefault:\n\t\tbreak;\n\t}\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_auto_dbg_console(\n\tvoid *dm_void,\n\tchar input[][16],\n\tu32 *_used,\n\tchar *output,\n\tu32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tchar help[] = \"-h\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"hang: {1} {1:Show DbgPort, 2:Auto check hang}\\n\");\n\t\treturn;\n\t} else if (var1[0] == 1) {\n\t\tPHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);\n\t\tif (var1[1] == 1) {\n\t\t\tphydm_dbg_port_dump(dm, &used, output, &out_len);\n\t\t} else if (var1[1] == 2) {\n\t\t\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t\t out_len - used, \"Not support\\n\");\n\t\t\t} else {\n\t\t\t\t#if (ODM_IC_11N_SERIES_SUPPORT == 1)\n\t\t\t\tphydm_bb_auto_check_hang_start_n(dm, &used,\n\t\t\t\t\t\t\t\t output,\n\t\t\t\t\t\t\t\t &out_len);\n\t\t\t\t#else\n\t\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t\t out_len - used, \"Not support\\n\");\n\t\t\t\t#endif\n\t\t\t}\n\t\t}\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_auto_dbg_engine(void *dm_void)\n{\n\tu32 value32 = 0;\n\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;\n\n\tif (atd_t->auto_dbg_type == AUTO_DBG_STOP)\n\t\treturn;\n\n\tpr_debug(\"%s ======>\\n\", __func__);\n\n\tif (atd_t->auto_dbg_type == AUTO_DBG_CHECK_HANG) {\n\t\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\t\tpr_debug(\"Not Support\\n\");\n\t\t} else {\n\t\t\t#if (ODM_IC_11N_SERIES_SUPPORT == 1)\n\t\t\tphydm_auto_check_hang_engine_n(dm);\n\t\t\t#else\n\t\t\tpr_debug(\"Not Support\\n\");\n\t\t\t#endif\n\t\t}\n\n\t} else if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_RA) {\n\t\tpr_debug(\"Not Support\\n\");\n\t}\n}\n\nvoid phydm_auto_dbg_engine_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;\n\tu16 dbg_port_table[DBGPORT_CHK_NUM] = {0x0, 0x803, 0x208, 0xab0,\n\t\t\t\t\t       0xab1, 0xab2};\n\n\tPHYDM_DBG(dm, ODM_COMP_API, \"%s ======>n\", __func__);\n\n\todm_move_memory(dm, &atd_t->dbg_port_table[0],\n\t\t\t&dbg_port_table[0], (DBGPORT_CHK_NUM * 2));\n\n\tphydm_check_hang_init(dm);\n}\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_auto_dbg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDM_AUTO_DBG_H__\n#define __PHYDM_AUTO_DBG_H__\n\n#define AUTO_DBG_VERSION \"1.0\" /* @2017.05.015  Dino, Add phydm_auto_dbg.h*/\n\n/* @1 ============================================================\n * 1  Definition\n * 1 ============================================================\n */\n\n#define AUTO_CHK_HANG_STEP_MAX 3\n#define DBGPORT_CHK_NUM 6\n\n#ifdef PHYDM_AUTO_DEGBUG\n\n/* @1 ============================================================\n * 1  enumeration\n * 1 ============================================================\n */\n\nenum auto_dbg_type_e {\n\tAUTO_DBG_STOP\t\t= 0,\n\tAUTO_DBG_CHECK_HANG\t= 1,\n\tAUTO_DBG_CHECK_RA\t= 2,\n\tAUTO_DBG_CHECK_DIG\t= 3\n};\n\n/* @1 ============================================================\n * 1  structure\n * 1 ============================================================\n */\n\nstruct n_dbgport_803 {\n\t/*@BYTE 3*/\n\tu8 bb_rst_b : 1;\n\tu8 glb_rst_b : 1;\n\tu8 zero_1bit_1 : 1;\n\tu8 ofdm_rst_b : 1;\n\tu8 cck_txpe : 1;\n\tu8 ofdm_txpe : 1;\n\tu8 phy_tx_on : 1;\n\tu8 tdrdy : 1;\n\t/*@BYTE 2*/\n\tu8 txd : 8;\n\t/*@BYTE 1*/\n\tu8 cck_cca_pp : 1;\n\tu8 ofdm_cca_pp : 1;\n\tu8 rx_rst : 1;\n\tu8 rdrdy : 1;\n\tu8 rxd_7_4 : 4;\n\t/*@BYTE 0*/\n\tu8 rxd_3_0 : 4;\n\tu8 ofdm_tx_en : 1;\n\tu8 cck_tx_en : 1;\n\tu8 zero_1bit_2 : 1;\n\tu8 clk_80m : 1;\n};\n\nstruct phydm_auto_dbg_struct {\n\tenum auto_dbg_type_e auto_dbg_type;\n\tu8 dbg_step;\n\tu16 dbg_port_table[DBGPORT_CHK_NUM];\n\tu32 dbg_port_val[DBGPORT_CHK_NUM];\n\tu16 ofdm_t_cnt;\n\tu16 ofdm_r_cnt;\n\tu16 cck_t_cnt;\n\tu16 cck_r_cnt;\n\tu16 ofdm_crc_error_cnt;\n\tu16 cck_crc_error_cnt;\n};\n\n/* @1 ============================================================\n * 1  function prototype\n * 1 ============================================================\n */\n\nvoid phydm_dbg_port_dump(void *dm_void, u32 *used, char *output, u32 *out_len);\n\nvoid phydm_auto_dbg_console(\n\tvoid *dm_void,\n\tchar input[][16],\n\tu32 *_used,\n\tchar *output,\n\tu32 *_out_len);\n\nvoid phydm_auto_dbg_engine(void *dm_void);\n\nvoid phydm_auto_dbg_engine_init(void *dm_void);\n#endif\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_beamforming.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t#if WPP_SOFTWARE_TRACE\n\t\t#include \"phydm_beamforming.tmh\"\n\t#endif\n#endif\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\nvoid phydm_get_txbf_device_num(\n\tvoid *dm_void,\n\tu8 macid)\n{\n#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*@For BDC*/\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct cmn_sta_info *sta = dm->phydm_sta_info[macid];\n\tstruct bf_cmn_info *bf = NULL;\n\tstruct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;\n\tu8 act_as_bfer = 0;\n\tu8 act_as_bfee = 0;\n\n\tif (is_sta_active(sta)) {\n\t\tbf = &(sta->bf_info);\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"[Warning] %s invalid sta_info\\n\",\n\t\t\t  __func__);\n\t\treturn;\n\t}\n\n\tif (sta->support_wireless_set & WIRELESS_VHT) {\n\t\tif (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMEE_ENABLE)\n\t\t\tact_as_bfer = 1;\n\n\t\tif (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMER_ENABLE)\n\t\t\tact_as_bfee = 1;\n\n\t} else if (sta->support_wireless_set & WIRELESS_HT) {\n\t\tif (bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMEE_ENABLE)\n\t\t\tact_as_bfer = 1;\n\n\t\tif (bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMER_ENABLE)\n\t\t\tact_as_bfee = 1;\n\t}\n\n\tif (act_as_bfer))\n\t\t{ /* Our Device act as BFer */\n\t\t\tdm_bdc_table->w_bfee_client[macid] = true;\n\t\t\tdm_bdc_table->num_txbfee_client++;\n\t\t}\n\telse\n\t\tdm_bdc_table->w_bfee_client[macid] = false;\n\n\tif (act_as_bfee))\n\t\t{ /* Our Device act as BFee */\n\t\t\tdm_bdc_table->w_bfer_client[macid] = true;\n\t\t\tdm_bdc_table->num_txbfer_client++;\n\t\t}\n\telse\n\t\tdm_bdc_table->w_bfer_client[macid] = false;\n\n#endif\n#endif\n}\n\nstruct _RT_BEAMFORM_STAINFO *\nphydm_sta_info_init(struct dm_struct *dm, u16 sta_idx, u8 *my_mac_addr)\n{\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORM_STAINFO *entry = &beam_info->beamform_sta_info;\n\tstruct cmn_sta_info *cmn_sta = dm->phydm_sta_info[sta_idx];\n\t//void\t\t\t\t\t*adapter = dm->adapter;\n\tADAPTER * adapter = dm->adapter;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tPMGNT_INFO p_MgntInfo = &((adapter)->MgntInfo);\n\tPRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_MgntInfo);\n\tPRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_MgntInfo);\n#endif\n\n\tif (!is_sta_active(cmn_sta)) {\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s => sta_info(mac_id:%d) failed\\n\",\n\t\t\t  __func__, sta_idx);\n\t\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\trtw_warn_on(1);\n\t\t#endif\n\n\t\treturn entry;\n\t}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t/*odm_move_memory(dm, (PVOID)(entry->my_mac_addr),*/\n\t/*(PVOID)(adapter->CurrentAddress), 6);*/\n\todm_move_memory(dm, entry->my_mac_addr, my_mac_addr, 6);\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t/*odm_move_memory(dm, entry->my_mac_addr,*/\n\t/*adapter_mac_addr(sta->padapter), 6);*/\n\todm_move_memory(dm, entry->my_mac_addr, my_mac_addr, 6);\n#endif\n\n\tentry->aid = cmn_sta->aid;\n\tentry->ra = cmn_sta->mac_addr;\n\tentry->mac_id = cmn_sta->mac_id;\n\tentry->bw = cmn_sta->bw_mode;\n\tentry->cur_beamform = cmn_sta->bf_info.ht_beamform_cap;\n\tentry->ht_beamform_cap = cmn_sta->bf_info.ht_beamform_cap;\n\n#if ODM_IC_11AC_SERIES_SUPPORT\n\tif (cmn_sta->support_wireless_set & WIRELESS_VHT) {\n\t\tentry->cur_beamform_vht = cmn_sta->bf_info.vht_beamform_cap;\n\t\tentry->vht_beamform_cap = cmn_sta->bf_info.vht_beamform_cap;\n\t}\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) /*To Be Removed */\n\tentry->ht_beamform_cap = p_ht_info->HtBeamformCap; /*To Be Removed*/\n\tentry->vht_beamform_cap = p_vht_info->VhtBeamformCap; /*To Be Removed*/\n\n\tif (sta_idx == 0) { /*@client mode*/\n\t\t#if ODM_IC_11AC_SERIES_SUPPORT\n\t\tif (cmn_sta->support_wireless_set & WIRELESS_VHT)\n\t\t\tentry->cur_beamform_vht = p_vht_info->VhtCurBeamform;\n\t\t#endif\n\t}\n#endif\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"wireless_set = 0x%x, staidx = %d\\n\",\n\t\t  cmn_sta->support_wireless_set, sta_idx);\n\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t  \"entry->cur_beamform = 0x%x, entry->cur_beamform_vht = 0x%x\\n\",\n\t\t  entry->cur_beamform, entry->cur_beamform_vht);\n\treturn entry;\n}\nvoid phydm_sta_info_update(\n\tstruct dm_struct *dm,\n\tu16 sta_idx,\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry)\n{\n\tstruct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];\n\n\tif (!is_sta_active(sta))\n\t\treturn;\n\n\tsta->bf_info.p_aid = beamform_entry->p_aid;\n\tsta->bf_info.g_id = beamform_entry->g_id;\n}\n\nstruct _RT_BEAMFORMEE_ENTRY *\nphydm_beamforming_get_bfee_entry_by_addr(\n\tvoid *dm_void,\n\tu8 *RA,\n\tu8 *idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i = 0;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\n\tfor (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {\n\t\tif (beam_info->beamformee_entry[i].is_used && (eq_mac_addr(RA, beam_info->beamformee_entry[i].mac_addr))) {\n\t\t\t*idx = i;\n\t\t\treturn &beam_info->beamformee_entry[i];\n\t\t}\n\t}\n\n\treturn NULL;\n}\n\nstruct _RT_BEAMFORMER_ENTRY *\nphydm_beamforming_get_bfer_entry_by_addr(\n\tvoid *dm_void,\n\tu8 *TA,\n\tu8 *idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i = 0;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\n\tfor (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) {\n\t\tif (beam_info->beamformer_entry[i].is_used && (eq_mac_addr(TA, beam_info->beamformer_entry[i].mac_addr))) {\n\t\t\t*idx = i;\n\t\t\treturn &beam_info->beamformer_entry[i];\n\t\t}\n\t}\n\n\treturn NULL;\n}\n\nstruct _RT_BEAMFORMEE_ENTRY *\nphydm_beamforming_get_entry_by_mac_id(\n\tvoid *dm_void,\n\tu8 mac_id,\n\tu8 *idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i = 0;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\n\tfor (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {\n\t\tif (beam_info->beamformee_entry[i].is_used && mac_id == beam_info->beamformee_entry[i].mac_id) {\n\t\t\t*idx = i;\n\t\t\treturn &beam_info->beamformee_entry[i];\n\t\t}\n\t}\n\n\treturn NULL;\n}\n\nenum beamforming_cap\nphydm_beamforming_get_entry_beam_cap_by_mac_id(\n\tvoid *dm_void,\n\tu8 mac_id)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i = 0;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tenum beamforming_cap beamform_entry_cap = BEAMFORMING_CAP_NONE;\n\n\tfor (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {\n\t\tif (beam_info->beamformee_entry[i].is_used && mac_id == beam_info->beamformee_entry[i].mac_id) {\n\t\t\tbeamform_entry_cap = beam_info->beamformee_entry[i].beamform_entry_cap;\n\t\t\ti = BEAMFORMEE_ENTRY_NUM;\n\t\t}\n\t}\n\n\treturn beamform_entry_cap;\n}\n\nstruct _RT_BEAMFORMEE_ENTRY *\nphydm_beamforming_get_free_bfee_entry(\n\tvoid *dm_void,\n\tu8 *idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i = 0;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\n\tfor (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {\n\t\tif (beam_info->beamformee_entry[i].is_used == false) {\n\t\t\t*idx = i;\n\t\t\treturn &beam_info->beamformee_entry[i];\n\t\t}\n\t}\n\treturn NULL;\n}\n\nstruct _RT_BEAMFORMER_ENTRY *\nphydm_beamforming_get_free_bfer_entry(\n\tvoid *dm_void,\n\tu8 *idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i = 0;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s ===>\\n\", __func__);\n\n\tfor (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) {\n\t\tif (beam_info->beamformer_entry[i].is_used == false) {\n\t\t\t*idx = i;\n\t\t\treturn &beam_info->beamformer_entry[i];\n\t\t}\n\t}\n\treturn NULL;\n}\n\n/*@\n * Description: Get the first entry index of MU Beamformee.\n *\n * Return value: index of the first MU sta.\n *\n * 2015.05.25. Created by tynli.\n *\n */\nu8 phydm_beamforming_get_first_mu_bfee_entry_idx(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 idx = 0xFF;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tboolean is_found = false;\n\n\tfor (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {\n\t\tif (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].is_mu_sta) {\n\t\t\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] idx=%d!\\n\", __func__,\n\t\t\t\t  idx);\n\t\t\tis_found = true;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!is_found)\n\t\tidx = 0xFF;\n\n\treturn idx;\n}\n\n/*@Add SU BFee and MU BFee*/\nstruct _RT_BEAMFORMEE_ENTRY *\nbeamforming_add_bfee_entry(\n\tvoid *dm_void,\n\tstruct _RT_BEAMFORM_STAINFO *sta,\n\tenum beamforming_cap beamform_cap,\n\tu8 num_of_sounding_dim,\n\tu8 comp_steering_num_of_bfer,\n\tu8 *idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMEE_ENTRY *entry = phydm_beamforming_get_free_bfee_entry(dm, idx);\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s Start!\\n\", __func__);\n\n\tif (entry != NULL) {\n\t\tentry->is_used = true;\n\t\tentry->aid = sta->aid;\n\t\tentry->mac_id = sta->mac_id;\n\t\tentry->sound_bw = sta->bw;\n\t\todm_move_memory(dm, entry->my_mac_addr, sta->my_mac_addr, 6);\n\n\t\tif (phydm_acting_determine(dm, phydm_acting_as_ap)) {\n\t\t\t/*@BSSID[44:47] xor BSSID[40:43]*/\n\t\t\tu16 bssid = ((sta->my_mac_addr[5] & 0xf0) >> 4) ^ (sta->my_mac_addr[5] & 0xf);\n\t\t\t/*@(dec(A) + dec(B)*32) mod 512*/\n\t\t\tentry->p_aid = (sta->aid + bssid * 32) & 0x1ff;\n\t\t\tentry->g_id = 63;\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"%s: BFee P_AID addressed to STA=%d\\n\",\n\t\t\t\t  __func__, entry->p_aid);\n\t\t} else if (phydm_acting_determine(dm, phydm_acting_as_ibss)) {\n\t\t\t/*@ad hoc mode*/\n\t\t\tentry->p_aid = 0;\n\t\t\tentry->g_id = 63;\n\t\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s: BFee P_AID as IBSS=%d\\n\",\n\t\t\t\t  __func__, entry->p_aid);\n\t\t} else {\n\t\t\t/*@client mode*/\n\t\t\tentry->p_aid = sta->ra[5];\n\t\t\t/*@BSSID[39:47]*/\n\t\t\tentry->p_aid = (entry->p_aid << 1) | (sta->ra[4] >> 7);\n\t\t\tentry->g_id = 0;\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"%s: BFee P_AID addressed to AP=0x%X\\n\",\n\t\t\t\t  __func__, entry->p_aid);\n\t\t}\n\t\tcp_mac_addr(entry->mac_addr, sta->ra);\n\t\tentry->is_txbf = false;\n\t\tentry->is_sound = false;\n\t\tentry->sound_period = 400;\n\t\tentry->beamform_entry_cap = beamform_cap;\n\t\tentry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;\n\n\t\t/*\t\t@entry->log_seq = 0xff;\t\t\t\tMove to beamforming_add_bfer_entry*/\n\t\t/*\t\t@entry->log_retry_cnt = 0;\t\t\tMove to beamforming_add_bfer_entry*/\n\t\t/*\t\t@entry->LogSuccessCnt = 0;\t\tMove to beamforming_add_bfer_entry*/\n\n\t\tentry->log_status_fail_cnt = 0;\n\n\t\tentry->num_of_sounding_dim = num_of_sounding_dim;\n\t\tentry->comp_steering_num_of_bfer = comp_steering_num_of_bfer;\n\n\t\tif (beamform_cap & BEAMFORMER_CAP_VHT_MU) {\n\t\t\tdm->beamforming_info.beamformee_mu_cnt += 1;\n\t\t\tentry->is_mu_sta = true;\n\t\t\tdm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(dm);\n\t\t} else if (beamform_cap & (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) {\n\t\t\tdm->beamforming_info.beamformee_su_cnt += 1;\n\t\t\tentry->is_mu_sta = false;\n\t\t}\n\n\t\treturn entry;\n\t} else\n\t\treturn NULL;\n}\n\n/*@Add SU BFee and MU BFer*/\nstruct _RT_BEAMFORMER_ENTRY *\nbeamforming_add_bfer_entry(\n\tvoid *dm_void,\n\tstruct _RT_BEAMFORM_STAINFO *sta,\n\tenum beamforming_cap beamform_cap,\n\tu8 num_of_sounding_dim,\n\tu8 *idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMER_ENTRY *entry = phydm_beamforming_get_free_bfer_entry(dm, idx);\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s Start!\\n\", __func__);\n\n\tif (entry != NULL) {\n\t\tentry->is_used = true;\n\t\todm_move_memory(dm, entry->my_mac_addr, sta->my_mac_addr, 6);\n\t\tif (phydm_acting_determine(dm, phydm_acting_as_ap)) {\n\t\t\t/*@BSSID[44:47] xor BSSID[40:43]*/\n\t\t\tu16 bssid = ((sta->my_mac_addr[5] & 0xf0) >> 4) ^ (sta->my_mac_addr[5] & 0xf);\n\n\t\t\tentry->p_aid = (sta->aid + bssid * 32) & 0x1ff;\n\t\t\tentry->g_id = 63;\n\t\t\t/*@(dec(A) + dec(B)*32) mod 512*/\n\t\t} else if (phydm_acting_determine(dm, phydm_acting_as_ibss)) {\n\t\t\tentry->p_aid = 0;\n\t\t\tentry->g_id = 63;\n\t\t} else {\n\t\t\tentry->p_aid = sta->ra[5];\n\t\t\t/*@BSSID[39:47]*/\n\t\t\tentry->p_aid = (entry->p_aid << 1) | (sta->ra[4] >> 7);\n\t\t\tentry->g_id = 0;\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"%s: P_AID addressed to AP=0x%X\\n\", __func__,\n\t\t\t\t  entry->p_aid);\n\t\t}\n\n\t\tcp_mac_addr(entry->mac_addr, sta->ra);\n\t\tentry->beamform_entry_cap = beamform_cap;\n\n\t\tentry->pre_log_seq = 0; /*@Modified by Jeffery @2015-04-13*/\n\t\tentry->log_seq = 0; /*@Modified by Jeffery @2014-10-29*/\n\t\tentry->log_retry_cnt = 0; /*@Modified by Jeffery @2014-10-29*/\n\t\tentry->log_success = 0; /*@log_success is NOT needed to be accumulated, so  LogSuccessCnt->log_success, 2015-04-13, Jeffery*/\n\t\tentry->clock_reset_times = 0; /*@Modified by Jeffery @2015-04-13*/\n\n\t\tentry->num_of_sounding_dim = num_of_sounding_dim;\n\n\t\tif (beamform_cap & BEAMFORMEE_CAP_VHT_MU) {\n\t\t\tdm->beamforming_info.beamformer_mu_cnt += 1;\n\t\t\tentry->is_mu_ap = true;\n\t\t\tentry->aid = sta->aid;\n\t\t} else if (beamform_cap & (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) {\n\t\t\tdm->beamforming_info.beamformer_su_cnt += 1;\n\t\t\tentry->is_mu_ap = false;\n\t\t}\n\n\t\treturn entry;\n\t} else\n\t\treturn NULL;\n}\n\n#if 0\nboolean\nbeamforming_remove_entry(\n\tvoid\t\t\t*adapter,\n\tu8\t\t*RA,\n\tu8\t\t*idx\n)\n{\n\tHAL_DATA_TYPE\t\t\t*hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct\t\t\t\t*dm = &hal_data->DM_OutSrc;\n\n\tstruct _RT_BEAMFORMER_ENTRY\t*bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, RA, idx);\n\tstruct _RT_BEAMFORMEE_ENTRY\t*entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, idx);\n\tboolean ret = false;\n\n\tRT_DISP(FBEAM, FBEAM_FUN, (\"[Beamforming]@%s Start!\\n\", __func__));\n\tRT_DISP(FBEAM, FBEAM_FUN, (\"[Beamforming]@%s, bfer_entry=0x%x\\n\", __func__, bfer_entry));\n\tRT_DISP(FBEAM, FBEAM_FUN, (\"[Beamforming]@%s, entry=0x%x\\n\", __func__, entry));\n\n\tif (entry != NULL) {\n\t\tentry->is_used = false;\n\t\tentry->beamform_entry_cap = BEAMFORMING_CAP_NONE;\n\t\t/*@entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;*/\n\t\tentry->is_beamforming_in_progress = false;\n\t\tret = true;\n\t}\n\tif (bfer_entry != NULL) {\n\t\tbfer_entry->is_used = false;\n\t\tbfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE;\n\t\tret = true;\n\t}\n\treturn ret;\n}\n#endif\n\n/* Used for beamforming_start_v1 */\nvoid phydm_beamforming_ndpa_rate(\n\tvoid *dm_void,\n\tenum channel_width BW,\n\tu8 rate)\n{\n\tu16 ndpa_rate = rate;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s Start!\\n\", __func__);\n\n\tif (ndpa_rate == 0) {\n\t\tif (dm->rssi_min > 30) /* @link RSSI > 30% */\n\t\t\tndpa_rate = ODM_RATE24M;\n\t\telse\n\t\t\tndpa_rate = ODM_RATE6M;\n\t}\n\n\tif (ndpa_rate < ODM_RATEMCS0)\n\t\tBW = (enum channel_width)CHANNEL_WIDTH_20;\n\n\tndpa_rate = (ndpa_rate << 8) | BW;\n\thal_com_txbf_set(dm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate);\n}\n\n/* Used for beamforming_start_sw and  beamforming_start_fw */\nvoid phydm_beamforming_dym_ndpa_rate(\n\tvoid *dm_void)\n{\n\tu16 ndpa_rate = ODM_RATE6M, BW;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tndpa_rate = ODM_RATE6M;\n\tBW = CHANNEL_WIDTH_20;\n\n\tndpa_rate = ndpa_rate << 8 | BW;\n\thal_com_txbf_set(dm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate);\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s End, NDPA rate = 0x%X\\n\", __func__,\n\t\t  ndpa_rate);\n}\n\n/*@\n*\tSW Sounding : SW Timer unit 1ms\n*\t\t\t\t HW Timer unit (1/32000) s  32k is clock.\n*\tFW Sounding : FW Timer unit 10ms\n*/\nvoid beamforming_dym_period(\n\tvoid *dm_void,\n\tu8 status)\n{\n\tu8 idx;\n\tboolean is_change_period = false;\n\tu16 sound_period_sw, sound_period_fw;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tstruct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;\n\n\tstruct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx];\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\t/* @3 TODO  per-client throughput caculation. */\n\n\tif ((*dm->current_tx_tp + *dm->current_rx_tp > 2) && (entry->log_status_fail_cnt <= 20 || status)) {\n\t\tsound_period_sw = 40; /* @40ms */\n\t\tsound_period_fw = 40; /* @From  H2C cmd, unit = 10ms */\n\t} else {\n\t\tsound_period_sw = 4000; /* @4s */\n\t\tsound_period_fw = 400;\n\t}\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s]sound_period_sw=%d, sound_period_fw=%d\\n\",\n\t\t  __func__, sound_period_sw, sound_period_fw);\n\n\tfor (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {\n\t\tbeamform_entry = beam_info->beamformee_entry + idx;\n\n\t\tif (beamform_entry->default_csi_cnt > 20) {\n\t\t\t/*@Modified by David*/\n\t\t\tsound_period_sw = 4000;\n\t\t\tsound_period_fw = 400;\n\t\t}\n\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] period = %d\\n\", __func__,\n\t\t\t  sound_period_sw);\n\t\tif ((beamform_entry->beamform_entry_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) == 0)\n\t\t\tcontinue;\n\n\t\tif (sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || sound_info->sound_mode == SOUNDING_FW_HT_TIMER) {\n\t\t\tif (beamform_entry->sound_period != sound_period_fw) {\n\t\t\t\tbeamform_entry->sound_period = sound_period_fw;\n\t\t\t\tis_change_period = true; /*Only FW sounding need to send H2C packet to change sound period. */\n\t\t\t}\n\t\t} else if (beamform_entry->sound_period != sound_period_sw)\n\t\t\tbeamform_entry->sound_period = sound_period_sw;\n\t}\n\n\tif (is_change_period)\n\t\thal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx);\n}\n\nboolean\nbeamforming_send_ht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tenum channel_width BW,\n\tu8 q_idx)\n{\n\tboolean ret = true;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (q_idx == BEACON_QUEUE)\n\t\tret = send_fw_ht_ndpa_packet(dm, RA, BW);\n\telse\n\t\tret = send_sw_ht_ndpa_packet(dm, RA, BW);\n\n\treturn ret;\n}\n\nboolean\nbeamforming_send_vht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tu16 AID,\n\tenum channel_width BW,\n\tu8 q_idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tboolean ret = true;\n\n\thal_com_txbf_set(dm, TXBF_SET_GET_TX_RATE, NULL);\n\n\tif (beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7 && beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9 && !beam_info->snding3ss)\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"@%s: 3SS VHT 789 don't sounding\\n\",\n\t\t\t  __func__);\n\n\telse {\n\t\tif (q_idx == BEACON_QUEUE) /* Send to reserved page => FW NDPA */\n\t\t\tret = send_fw_vht_ndpa_packet(dm, RA, AID, BW);\n\t\telse {\n#ifdef SUPPORT_MU_BF\n#if (SUPPORT_MU_BF == 1)\n\t\t\tbeam_info->is_mu_sounding = true;\n\t\t\tret = send_sw_vht_mu_ndpa_packet(dm, BW);\n#else\n\t\t\tbeam_info->is_mu_sounding = false;\n\t\t\tret = send_sw_vht_ndpa_packet(dm, RA, AID, BW);\n#endif\n#else\n\t\t\tbeam_info->is_mu_sounding = false;\n\t\t\tret = send_sw_vht_ndpa_packet(dm, RA, AID, BW);\n#endif\n\t\t}\n\t}\n\treturn ret;\n}\n\nenum beamforming_notify_state\nphydm_beamfomring_is_sounding(\n\tvoid *dm_void,\n\tstruct _RT_BEAMFORMING_INFO *beam_info,\n\tu8 *idx)\n{\n\tenum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE;\n\tstruct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s Start!\\n\", __func__);\n\n\t/*@if(( Beamforming_GetBeamCap(beam_info) & BEAMFORMER_CAP) == 0)*/\n\t/*@is_sounding = BEAMFORMING_NOTIFY_RESET;*/\n\tif (beam_oid_info.sound_oid_mode == sounding_stop_all_timer) {\n\t\tis_sounding = BEAMFORMING_NOTIFY_RESET;\n\t\tgoto out;\n\t}\n\n\tfor (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {\n\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t  \"@%s: BFee Entry %d is_used=%d, is_sound=%d\\n\",\n\t\t\t  __func__, i, beam_info->beamformee_entry[i].is_used,\n\t\t\t  beam_info->beamformee_entry[i].is_sound);\n\t\tif (beam_info->beamformee_entry[i].is_used && !beam_info->beamformee_entry[i].is_sound) {\n\t\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s: Add BFee entry %d\\n\",\n\t\t\t\t  __func__, i);\n\t\t\t*idx = i;\n\t\t\tif (beam_info->beamformee_entry[i].is_mu_sta)\n\t\t\t\tis_sounding = BEAMFORMEE_NOTIFY_ADD_MU;\n\t\t\telse\n\t\t\t\tis_sounding = BEAMFORMEE_NOTIFY_ADD_SU;\n\t\t}\n\n\t\tif (!beam_info->beamformee_entry[i].is_used && beam_info->beamformee_entry[i].is_sound) {\n\t\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s: Delete BFee entry %d\\n\",\n\t\t\t\t  __func__, i);\n\t\t\t*idx = i;\n\t\t\tif (beam_info->beamformee_entry[i].is_mu_sta)\n\t\t\t\tis_sounding = BEAMFORMEE_NOTIFY_DELETE_MU;\n\t\t\telse\n\t\t\t\tis_sounding = BEAMFORMEE_NOTIFY_DELETE_SU;\n\t\t}\n\t}\n\nout:\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s End, is_sounding = %d\\n\", __func__,\n\t\t  is_sounding);\n\treturn is_sounding;\n}\n\n/* This function is unused */\nu8 phydm_beamforming_sounding_idx(\n\tvoid *dm_void,\n\tstruct _RT_BEAMFORMING_INFO *beam_info)\n{\n\tu8 idx = 0;\n\tstruct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s Start!\\n\", __func__);\n\n\tif (beam_oid_info.sound_oid_mode == SOUNDING_SW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_SW_VHT_TIMER ||\n\t    beam_oid_info.sound_oid_mode == SOUNDING_HW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_VHT_TIMER)\n\t\tidx = beam_oid_info.sound_oid_idx;\n\telse {\n\t\tu8 i;\n\t\tfor (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {\n\t\t\tif (beam_info->beamformee_entry[i].is_used && !beam_info->beamformee_entry[i].is_sound) {\n\t\t\t\tidx = i;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn idx;\n}\n\nenum sounding_mode\nphydm_beamforming_sounding_mode(\n\tvoid *dm_void,\n\tstruct _RT_BEAMFORMING_INFO *beam_info,\n\tu8 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 support_interface = dm->support_interface;\n\n\tstruct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx];\n\tstruct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;\n\tenum sounding_mode mode = beam_oid_info.sound_oid_mode;\n\n\tif (beam_oid_info.sound_oid_mode == SOUNDING_SW_VHT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_VHT_TIMER) {\n\t\tif (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)\n\t\t\tmode = beam_oid_info.sound_oid_mode;\n\t\telse\n\t\t\tmode = sounding_stop_all_timer;\n\t} else if (beam_oid_info.sound_oid_mode == SOUNDING_SW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_HT_TIMER) {\n\t\tif (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)\n\t\t\tmode = beam_oid_info.sound_oid_mode;\n\t\telse\n\t\t\tmode = sounding_stop_all_timer;\n\t} else if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) {\n\t\tif (support_interface == ODM_ITRF_USB && !(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)))\n\t\t\tmode = SOUNDING_FW_VHT_TIMER;\n\t\telse\n\t\t\tmode = SOUNDING_SW_VHT_TIMER;\n\t} else if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) {\n\t\tif (support_interface == ODM_ITRF_USB && !(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)))\n\t\t\tmode = SOUNDING_FW_HT_TIMER;\n\t\telse\n\t\t\tmode = SOUNDING_SW_HT_TIMER;\n\t} else\n\t\tmode = sounding_stop_all_timer;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] support_interface=%d, mode=%d\\n\",\n\t\t  __func__, support_interface, mode);\n\n\treturn mode;\n}\n\nu16 phydm_beamforming_sounding_time(\n\tvoid *dm_void,\n\tstruct _RT_BEAMFORMING_INFO *beam_info,\n\tenum sounding_mode mode,\n\tu8 idx)\n{\n\tu16 sounding_time = 0xffff;\n\tstruct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx];\n\tstruct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s Start!\\n\", __func__);\n\n\tif (mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_HW_VHT_TIMER)\n\t\tsounding_time = beam_oid_info.sound_oid_period * 32;\n\telse if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_SW_VHT_TIMER)\n\t\t/*@Modified by David*/\n\t\tsounding_time = beam_entry.sound_period; /*@beam_oid_info.sound_oid_period;*/\n\telse\n\t\tsounding_time = beam_entry.sound_period;\n\n\treturn sounding_time;\n}\n\nenum channel_width\nphydm_beamforming_sounding_bw(\n\tvoid *dm_void,\n\tstruct _RT_BEAMFORMING_INFO *beam_info,\n\tenum sounding_mode mode,\n\tu8 idx)\n{\n\tenum channel_width sounding_bw = CHANNEL_WIDTH_20;\n\tstruct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx];\n\tstruct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_HW_VHT_TIMER)\n\t\tsounding_bw = beam_oid_info.sound_oid_bw;\n\telse if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_SW_VHT_TIMER)\n\t\t/*@Modified by David*/\n\t\tsounding_bw = beam_entry.sound_bw; /*@beam_oid_info.sound_oid_bw;*/\n\telse\n\t\tsounding_bw = beam_entry.sound_bw;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s, sounding_bw=0x%X\\n\", __func__,\n\t\t  sounding_bw);\n\n\treturn sounding_bw;\n}\n\nboolean\nphydm_beamforming_select_beam_entry(\n\tvoid *dm_void,\n\tstruct _RT_BEAMFORMING_INFO *beam_info)\n{\n\tstruct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\t/*@entry.is_sound is different between first and latter NDPA, and should not be used as BFee entry selection*/\n\t/*@BTW, latter modification should sync to the selection mechanism of AP/ADSL instead of the fixed sound_idx.*/\n\tsound_info->sound_idx = phydm_beamforming_sounding_idx(dm, beam_info);\n\t/*sound_info->sound_idx = 0;*/\n\n\tif (sound_info->sound_idx < BEAMFORMEE_ENTRY_NUM)\n\t\tsound_info->sound_mode = phydm_beamforming_sounding_mode(dm, beam_info, sound_info->sound_idx);\n\telse\n\t\tsound_info->sound_mode = sounding_stop_all_timer;\n\n\tif (sounding_stop_all_timer == sound_info->sound_mode) {\n\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t  \"[%s] Return because of sounding_stop_all_timer\\n\",\n\t\t\t  __func__);\n\t\treturn false;\n\t} else {\n\t\tsound_info->sound_bw = phydm_beamforming_sounding_bw(dm, beam_info, sound_info->sound_mode, sound_info->sound_idx);\n\t\tsound_info->sound_period = phydm_beamforming_sounding_time(dm, beam_info, sound_info->sound_mode, sound_info->sound_idx);\n\t\treturn true;\n\t}\n}\n\n/*SU BFee Entry Only*/\nboolean\nphydm_beamforming_start_period(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tboolean ret = true;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tstruct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;\n\n\tphydm_beamforming_dym_ndpa_rate(dm);\n\n\tphydm_beamforming_select_beam_entry(dm, beam_info); /* @Modified */\n\n\tif (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)\n\t\todm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period);\n\telse if (sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || sound_info->sound_mode == SOUNDING_HW_HT_TIMER ||\n\t\t sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER) {\n\t\tHAL_HW_TIMER_TYPE timer_type = HAL_TIMER_TXBF;\n\t\tu32 val = (sound_info->sound_period | (timer_type << 16));\n\n\t\t/* @HW timer stop: All IC has the same setting */\n\t\tphydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type));\n\t\t/* odm_write_1byte(dm, 0x15F, 0); */\n\t\t/* @HW timer init: All IC has the same setting, but 92E & 8812A only write 2 bytes */\n\t\tphydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_INIT, (u8 *)(&val));\n\t\t/* odm_write_1byte(dm, 0x164, 1); */\n\t\t/* odm_write_4byte(dm, 0x15C, val); */\n\t\t/* @HW timer start: All IC has the same setting */\n\t\tphydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_START, (u8 *)(&timer_type));\n\t\t/* odm_write_1byte(dm, 0x15F, 0x5); */\n\t} else if (sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || sound_info->sound_mode == SOUNDING_FW_HT_TIMER)\n\t\tret = beamforming_start_fw(dm, sound_info->sound_idx);\n\telse\n\t\tret = false;\n\n\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t  \"[%s] sound_idx=%d, sound_mode=%d, sound_bw=%d, sound_period=%d\\n\",\n\t\t  __func__, sound_info->sound_idx, sound_info->sound_mode,\n\t\t  sound_info->sound_bw, sound_info->sound_period);\n\n\treturn ret;\n}\n\n/* Used after beamforming_leave, and will clear the setting of the \"already deleted\" entry\n *SU BFee Entry Only*/\nvoid phydm_beamforming_end_period_sw(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\t/*void\t\t\t\t\t*adapter = dm->adapter;*/\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tstruct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;\n\n\tHAL_HW_TIMER_TYPE timer_type = HAL_TIMER_TXBF;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s Start!\\n\", __func__);\n\n\tif (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)\n\t\todm_cancel_timer(dm, &beam_info->beamforming_timer);\n\telse if (sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || sound_info->sound_mode == SOUNDING_HW_HT_TIMER ||\n\t\t sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER)\n\t\t/*@HW timer stop: All IC has the same setting*/\n\t\tphydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type));\n\t/*odm_write_1byte(dm, 0x15F, 0);*/\n}\n\nvoid phydm_beamforming_end_period_fw(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 idx = 0;\n\n\thal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx);\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s]\\n\", __func__);\n}\n\n/*SU BFee Entry Only*/\nvoid phydm_beamforming_clear_entry_sw(\n\tvoid *dm_void,\n\tboolean is_delete,\n\tu8 delete_idx)\n{\n\tu8 idx = 0;\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\n\tif (is_delete) {\n\t\tif (delete_idx < BEAMFORMEE_ENTRY_NUM) {\n\t\t\tbeamform_entry = beam_info->beamformee_entry + delete_idx;\n\t\t\tif (!(!beamform_entry->is_used && beamform_entry->is_sound)) {\n\t\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t\t  \"[%s] SW delete_idx is wrong!!!!!\\n\",\n\t\t\t\t\t  __func__);\n\t\t\t\treturn;\n\t\t\t}\n\t\t}\n\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] SW delete BFee entry %d\\n\",\n\t\t\t  __func__, delete_idx);\n\t\tif (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) {\n\t\t\tbeamform_entry->is_beamforming_in_progress = false;\n\t\t\tbeamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;\n\t\t} else if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {\n\t\t\tbeamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;\n\t\t\thal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&delete_idx);\n\t\t}\n\t\tbeamform_entry->is_sound = false;\n\t\treturn;\n\t}\n\n\tfor (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {\n\t\tbeamform_entry = beam_info->beamformee_entry + idx;\n\n\t\t/*Used after is_sounding=RESET, and will clear the setting of \"ever sounded\" entry, which is not necessarily be deleted.*/\n\t\t/*This function is mainly used in case \"beam_oid_info.sound_oid_mode == sounding_stop_all_timer\".*/\n\t\t/*@However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/\n\n\t\tif (!beamform_entry->is_sound)\n\t\t\tcontinue;\n\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] SW reset BFee entry %d\\n\",\n\t\t\t  __func__, idx);\n\t\t/*@\n\t\t*\tIf End procedure is\n\t\t*\t1. Between (Send NDPA, C2H packet return), reset state to initialized.\n\t\t*\tAfter C2H packet return , status bit will be set to zero.\n\t\t*\n\t\t*\t2. After C2H packet, then reset state to initialized and clear status bit.\n\t\t*/\n\n\t\tif (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)\n\t\t\tphydm_beamforming_end_sw(dm, 0);\n\t\telse if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {\n\t\t\tbeamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;\n\t\t\thal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx);\n\t\t}\n\n\t\tbeamform_entry->is_sound = false;\n\t}\n}\n\nvoid phydm_beamforming_clear_entry_fw(\n\tvoid *dm_void,\n\tboolean is_delete,\n\tu8 delete_idx)\n{\n\tu8 idx = 0;\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\n\tif (is_delete) {\n\t\tif (delete_idx < BEAMFORMEE_ENTRY_NUM) {\n\t\t\tbeamform_entry = beam_info->beamformee_entry + delete_idx;\n\n\t\t\tif (!(!beamform_entry->is_used && beamform_entry->is_sound)) {\n\t\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t\t  \"[%s] FW delete_idx is wrong!!!!!\\n\",\n\t\t\t\t\t  __func__);\n\t\t\t\treturn;\n\t\t\t}\n\t\t}\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s: FW delete BFee entry %d\\n\",\n\t\t\t  __func__, delete_idx);\n\t\tbeamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;\n\t\tbeamform_entry->is_sound = false;\n\t} else {\n\t\tfor (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {\n\t\t\tbeamform_entry = beam_info->beamformee_entry + idx;\n\n\t\t\t/*Used after is_sounding=RESET, and will clear the setting of \"ever sounded\" entry, which is not necessarily be deleted.*/\n\t\t\t/*This function is mainly used in case \"beam_oid_info.sound_oid_mode == sounding_stop_all_timer\".*/\n\t\t\t/*@However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/\n\n\t\t\tif (beamform_entry->is_sound) {\n\t\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t\t  \"[%s]FW reset BFee entry %d\\n\",\n\t\t\t\t\t  __func__, idx);\n\t\t\t\t/*@\n\t\t\t\t*\tIf End procedure is\n\t\t\t\t*\t1. Between (Send NDPA, C2H packet return), reset state to initialized.\n\t\t\t\t*\tAfter C2H packet return , status bit will be set to zero.\n\t\t\t\t*\n\t\t\t\t*\t2. After C2H packet, then reset state to initialized and clear status bit.\n\t\t\t\t*/\n\n\t\t\t\tbeamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;\n\t\t\t\tbeamform_entry->is_sound = false;\n\t\t\t}\n\t\t}\n\t}\n}\n\n/*@\n*\tCalled :\n*\t1. Add and delete entry : beamforming_enter/beamforming_leave\n*\t2. FW trigger :  Beamforming_SetTxBFen\n*\t3. Set OID_RT_BEAMFORMING_PERIOD : beamforming_control_v2\n*/\nvoid phydm_beamforming_notify(\n\tvoid *dm_void)\n{\n\tu8 idx = BEAMFORMEE_ENTRY_NUM;\n\tenum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tstruct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s Start!\\n\", __func__);\n\n\tis_sounding = phydm_beamfomring_is_sounding(dm, beam_info, &idx);\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s, Before notify, is_sounding=%d, idx=%d\\n\",\n\t\t  __func__, is_sounding, idx);\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s: beam_info->beamformee_su_cnt = %d\\n\",\n\t\t  __func__, beam_info->beamformee_su_cnt);\n\n\tswitch (is_sounding) {\n\tcase BEAMFORMEE_NOTIFY_ADD_SU:\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s: BEAMFORMEE_NOTIFY_ADD_SU\\n\",\n\t\t\t  __func__);\n\t\tphydm_beamforming_start_period(dm);\n\t\tbreak;\n\n\tcase BEAMFORMEE_NOTIFY_DELETE_SU:\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s: BEAMFORMEE_NOTIFY_DELETE_SU\\n\",\n\t\t\t  __func__);\n\t\tif (sound_info->sound_mode == SOUNDING_FW_HT_TIMER || sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) {\n\t\t\tphydm_beamforming_clear_entry_fw(dm, true, idx);\n\t\t\tif (beam_info->beamformee_su_cnt == 0) { /* @For 2->1 entry, we should not cancel SW timer */\n\t\t\t\tphydm_beamforming_end_period_fw(dm);\n\t\t\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s: No BFee left\\n\",\n\t\t\t\t\t  __func__);\n\t\t\t}\n\t\t} else {\n\t\t\tphydm_beamforming_clear_entry_sw(dm, true, idx);\n\t\t\tif (beam_info->beamformee_su_cnt == 0) { /* @For 2->1 entry, we should not cancel SW timer */\n\t\t\t\tphydm_beamforming_end_period_sw(dm);\n\t\t\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s: No BFee left\\n\",\n\t\t\t\t\t  __func__);\n\t\t\t}\n\t\t}\n\t\tbreak;\n\n\tcase BEAMFORMEE_NOTIFY_ADD_MU:\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s: BEAMFORMEE_NOTIFY_ADD_MU\\n\",\n\t\t\t  __func__);\n\t\tif (beam_info->beamformee_mu_cnt == 2) {\n\t\t\t/*@if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)\n\t\t\t\todm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period);*/\n\t\t\todm_set_timer(dm, &beam_info->beamforming_timer, 1000); /*@Do MU sounding every 1sec*/\n\t\t} else\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"%s: Less or larger than 2 MU STAs, not to set timer\\n\",\n\t\t\t\t  __func__);\n\t\tbreak;\n\n\tcase BEAMFORMEE_NOTIFY_DELETE_MU:\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s: BEAMFORMEE_NOTIFY_DELETE_MU\\n\",\n\t\t\t  __func__);\n\t\tif (beam_info->beamformee_mu_cnt == 1) {\n\t\t\t/*@if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)*/ {\n\t\t\t\todm_cancel_timer(dm, &beam_info->beamforming_timer);\n\t\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t\t  \"%s: Less than 2 MU STAs, stop sounding\\n\",\n\t\t\t\t\t  __func__);\n\t\t\t}\n\t\t}\n\t\tbreak;\n\n\tcase BEAMFORMING_NOTIFY_RESET:\n\t\tif (sound_info->sound_mode == SOUNDING_FW_HT_TIMER || sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) {\n\t\t\tphydm_beamforming_clear_entry_fw(dm, false, idx);\n\t\t\tphydm_beamforming_end_period_fw(dm);\n\t\t} else {\n\t\t\tphydm_beamforming_clear_entry_sw(dm, false, idx);\n\t\t\tphydm_beamforming_end_period_sw(dm);\n\t\t}\n\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nboolean\nbeamforming_init_entry(void *dm_void, u16 sta_idx, u8 *bfer_bfee_idx,\n\t\t       u8 *my_mac_addr)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct cmn_sta_info *cmn_sta = dm->phydm_sta_info[sta_idx];\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;\n\tstruct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL;\n\tstruct _RT_BEAMFORM_STAINFO *sta = NULL;\n\tenum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE;\n\tu8 bfer_idx = 0xF, bfee_idx = 0xF;\n\tu8 num_of_sounding_dim = 0, comp_steering_num_of_bfer = 0;\n\n\tif (!is_sta_active(cmn_sta)) {\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s => sta_info(mac_id:%d) failed\\n\",\n\t\t\t  __func__, sta_idx);\n\t\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\trtw_warn_on(1);\n\t\t#endif\n\t\treturn false;\n\t}\n\n\tsta = phydm_sta_info_init(dm, sta_idx, my_mac_addr);\n\t/*The current setting does not support Beaforming*/\n\tif (BEAMFORMING_CAP_NONE == sta->ht_beamform_cap && BEAMFORMING_CAP_NONE == sta->vht_beamform_cap) {\n\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t  \"The configuration disabled Beamforming! Skip...\\n\");\n\t\treturn false;\n\t}\n\n\tif (!(cmn_sta->support_wireless_set & (WIRELESS_VHT | WIRELESS_HT)))\n\t\treturn false;\n\telse {\n\t\tif (cmn_sta->support_wireless_set & WIRELESS_HT) { /*@HT*/\n\t\t\tif (TEST_FLAG(sta->cur_beamform, BEAMFORMING_HT_BEAMFORMER_ENABLE)) { /*We are Beamformee because the STA is Beamformer*/\n\t\t\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_HT_EXPLICIT);\n\t\t\t\tnum_of_sounding_dim = (sta->cur_beamform & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6;\n\t\t\t}\n\t\t\t/*We are Beamformer because the STA is Beamformee*/\n\t\t\tif (TEST_FLAG(sta->cur_beamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE) ||\n\t\t\t    TEST_FLAG(sta->ht_beamform_cap, BEAMFORMING_HT_BEAMFORMER_TEST)) {\n\t\t\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_HT_EXPLICIT);\n\t\t\t\tcomp_steering_num_of_bfer = (sta->cur_beamform & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4;\n\t\t\t}\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"[%s] HT cur_beamform=0x%X, beamform_cap=0x%X\\n\",\n\t\t\t\t  __func__, sta->cur_beamform, beamform_cap);\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"[%s] HT num_of_sounding_dim=%d, comp_steering_num_of_bfer=%d\\n\",\n\t\t\t\t  __func__, num_of_sounding_dim,\n\t\t\t\t  comp_steering_num_of_bfer);\n\t\t}\n#if (ODM_IC_11AC_SERIES_SUPPORT == 1)\n\t\tif (cmn_sta->support_wireless_set & WIRELESS_VHT) { /*VHT*/\n\n\t\t\t/* We are Beamformee because the STA is SU Beamformer*/\n\t\t\tif (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {\n\t\t\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_SU);\n\t\t\t\tnum_of_sounding_dim = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12;\n\t\t\t}\n\t\t\t/* We are Beamformer because the STA is SU Beamformee*/\n\t\t\tif (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) ||\n\t\t\t    TEST_FLAG(sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) {\n\t\t\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_SU);\n\t\t\t\tcomp_steering_num_of_bfer = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8;\n\t\t\t}\n\t\t\t/* We are Beamformee because the STA is MU Beamformer*/\n\t\t\tif (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) {\n\t\t\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_MU);\n\t\t\t\tnum_of_sounding_dim = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12;\n\t\t\t}\n\t\t\t/* We are Beamformer because the STA is MU Beamformee*/\n\t\t\tif (phydm_acting_determine(dm, phydm_acting_as_ap)) { /* Only AP mode supports to act an MU beamformer */\n\t\t\t\tif (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE) ||\n\t\t\t\t    TEST_FLAG(sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) {\n\t\t\t\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_MU);\n\t\t\t\t\tcomp_steering_num_of_bfer = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8;\n\t\t\t\t}\n\t\t\t}\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"[%s]VHT cur_beamform_vht=0x%X, beamform_cap=0x%X\\n\",\n\t\t\t\t  __func__, sta->cur_beamform_vht,\n\t\t\t\t  beamform_cap);\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"[%s]VHT num_of_sounding_dim=0x%X, comp_steering_num_of_bfer=0x%X\\n\",\n\t\t\t\t  __func__, num_of_sounding_dim,\n\t\t\t\t  comp_steering_num_of_bfer);\n\t\t}\n#endif\n\t}\n\n\tif (beamform_cap == BEAMFORMING_CAP_NONE)\n\t\treturn false;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Self BF Entry Cap = 0x%02X\\n\", __func__,\n\t\t  beamform_cap);\n\n\t/*We are BFee, so the entry is BFer*/\n\tif (beamform_cap & (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) {\n\t\tbeamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, sta->ra, &bfer_idx);\n\n\t\tif (beamformer_entry == NULL) {\n\t\t\tbeamformer_entry = beamforming_add_bfer_entry(dm, sta, beamform_cap, num_of_sounding_dim, &bfer_idx);\n\t\t\tif (beamformer_entry == NULL)\n\t\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t\t  \"[%s]Not enough BFer entry!!!!!\\n\",\n\t\t\t\t\t  __func__);\n\t\t}\n\t}\n\n\t/*We are BFer, so the entry is BFee*/\n\tif (beamform_cap & (BEAMFORMER_CAP_VHT_MU | BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) {\n\t\tbeamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, sta->ra, &bfee_idx);\n\n\t\t/*@if BFeeIdx = 0xF, that represent for no matched MACID among all linked entrys */\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Get BFee entry 0x%X by address\\n\",\n\t\t\t  __func__, bfee_idx);\n\t\tif (beamform_entry == NULL) {\n\t\t\tbeamform_entry = beamforming_add_bfee_entry(dm, sta, beamform_cap, num_of_sounding_dim, comp_steering_num_of_bfer, &bfee_idx);\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"[%s]: sta->AID=%d, sta->mac_id=%d\\n\",\n\t\t\t\t  __func__, sta->aid, sta->mac_id);\n\n\t\t\tPHYDM_DBG(dm, DBG_TXBF, \"[%s]: Add BFee entry %d\\n\",\n\t\t\t\t  __func__, bfee_idx);\n\n\t\t\tif (beamform_entry == NULL)\n\t\t\t\treturn false;\n\t\t\telse\n\t\t\t\tbeamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING;\n\t\t} else {\n\t\t\t/*@Entry has been created. If entry is initialing or progressing then errors occur.*/\n\t\t\tif (beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED &&\n\t\t\t    beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED)\n\t\t\t\treturn false;\n\t\t\telse\n\t\t\t\tbeamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING;\n\t\t}\n\t\tbeamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;\n\t\tphydm_sta_info_update(dm, sta_idx, beamform_entry);\n\t}\n\n\t*bfer_bfee_idx = (bfer_idx << 4) | bfee_idx;\n\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t  \"[%s] End: bfer_idx=0x%X, bfee_idx=0x%X, bfer_bfee_idx=0x%X\\n\",\n\t\t  __func__, bfer_idx, bfee_idx, *bfer_bfee_idx);\n\n\treturn true;\n}\n\nvoid beamforming_deinit_entry(\n\tvoid *dm_void,\n\tu8 *RA)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 idx = 0;\n\n\tstruct _RT_BEAMFORMER_ENTRY *bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, RA, &idx);\n\tstruct _RT_BEAMFORMEE_ENTRY *bfee_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);\n\tboolean ret = false;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s Start!\\n\", __func__);\n\n\tif (bfee_entry != NULL) {\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s, bfee_entry\\n\", __func__);\n\t\tbfee_entry->is_used = false;\n\t\tbfee_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE;\n\t\tbfee_entry->is_beamforming_in_progress = false;\n\t\tif (bfee_entry->is_mu_sta) {\n\t\t\tdm->beamforming_info.beamformee_mu_cnt -= 1;\n\t\t\tdm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(dm);\n\t\t} else\n\t\t\tdm->beamforming_info.beamformee_su_cnt -= 1;\n\t\tret = true;\n\t}\n\n\tif (bfer_entry != NULL) {\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s, bfer_entry\\n\", __func__);\n\t\tbfer_entry->is_used = false;\n\t\tbfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE;\n\t\tif (bfer_entry->is_mu_ap)\n\t\t\tdm->beamforming_info.beamformer_mu_cnt -= 1;\n\t\telse\n\t\t\tdm->beamforming_info.beamformer_su_cnt -= 1;\n\t\tret = true;\n\t}\n\n\tif (ret == true)\n\t\thal_com_txbf_set(dm, TXBF_SET_SOUNDING_LEAVE, (u8 *)&idx);\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s End, idx = 0x%X\\n\", __func__, idx);\n}\n\nboolean\nbeamforming_start_v1(\n\tvoid *dm_void,\n\tu8 *RA,\n\tboolean mode,\n\tenum channel_width BW,\n\tu8 rate)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 idx = 0;\n\tstruct _RT_BEAMFORMEE_ENTRY *entry;\n\tboolean ret = true;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\n\tentry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);\n\n\tif (entry->is_used == false) {\n\t\tentry->is_beamforming_in_progress = false;\n\t\treturn false;\n\t} else {\n\t\tif (entry->is_beamforming_in_progress)\n\t\t\treturn false;\n\n\t\tentry->is_beamforming_in_progress = true;\n\n\t\tif (mode == 1) {\n\t\t\tif (!(entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) {\n\t\t\t\tentry->is_beamforming_in_progress = false;\n\t\t\t\treturn false;\n\t\t\t}\n\t\t} else if (mode == 0) {\n\t\t\tif (!(entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) {\n\t\t\t\tentry->is_beamforming_in_progress = false;\n\t\t\t\treturn false;\n\t\t\t}\n\t\t}\n\n\t\tif (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) {\n\t\t\tentry->is_beamforming_in_progress = false;\n\t\t\treturn false;\n\t\t} else {\n\t\t\tentry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING;\n\t\t\tentry->is_sound = true;\n\t\t}\n\t}\n\n\tentry->sound_bw = BW;\n\tbeam_info->beamformee_cur_idx = idx;\n\tphydm_beamforming_ndpa_rate(dm, BW, rate);\n\thal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx);\n\n\tif (mode == 1)\n\t\tret = beamforming_send_ht_ndpa_packet(dm, RA, BW, NORMAL_QUEUE);\n\telse\n\t\tret = beamforming_send_vht_ndpa_packet(dm, RA, entry->aid, BW, NORMAL_QUEUE);\n\n\tif (ret == false) {\n\t\tbeamforming_leave(dm, RA);\n\t\tentry->is_beamforming_in_progress = false;\n\t\treturn false;\n\t}\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s  idx %d\\n\", __func__, idx);\n\treturn true;\n}\n\nboolean\nbeamforming_start_sw(\n\tvoid *dm_void,\n\tu8 idx,\n\tu8 mode,\n\tenum channel_width BW)\n{\n\tu8 *ra = NULL;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMEE_ENTRY *entry;\n\tboolean ret = true;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n#ifdef SUPPORT_MU_BF\n#if (SUPPORT_MU_BF == 1)\n\tu8 i, poll_sta_cnt = 0;\n\tboolean is_get_first_bfee = false;\n#endif\n#endif\n\n\tif (beam_info->is_mu_sounding) {\n\t\tbeam_info->is_mu_sounding_in_progress = true;\n\t\tentry = &beam_info->beamformee_entry[idx];\n\t\tra = entry->mac_addr;\n\n\t} else {\n\t\tentry = &beam_info->beamformee_entry[idx];\n\n\t\tif (entry->is_used == false) {\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"Skip Beamforming, no entry for idx =%d\\n\",\n\t\t\t\t  idx);\n\t\t\tentry->is_beamforming_in_progress = false;\n\t\t\treturn false;\n\t\t}\n\n\t\tif (entry->is_beamforming_in_progress) {\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"is_beamforming_in_progress, skip...\\n\");\n\t\t\treturn false;\n\t\t}\n\n\t\tentry->is_beamforming_in_progress = true;\n\t\tra = entry->mac_addr;\n\n\t\tif (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER) {\n\t\t\tif (!(entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) {\n\t\t\t\tentry->is_beamforming_in_progress = false;\n\t\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t\t  \"%s Return by not support BEAMFORMER_CAP_HT_EXPLICIT <==\\n\",\n\t\t\t\t\t  __func__);\n\t\t\t\treturn false;\n\t\t\t}\n\t\t} else if (mode == SOUNDING_SW_VHT_TIMER || mode == SOUNDING_HW_VHT_TIMER || mode == SOUNDING_AUTO_VHT_TIMER) {\n\t\t\tif (!(entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) {\n\t\t\t\tentry->is_beamforming_in_progress = false;\n\t\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t\t  \"%s Return by not support BEAMFORMER_CAP_VHT_SU <==\\n\",\n\t\t\t\t\t  __func__);\n\t\t\t\treturn false;\n\t\t\t}\n\t\t}\n\t\tif (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) {\n\t\t\tentry->is_beamforming_in_progress = false;\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"%s Return by incorrect beamform_entry_state(%d) <==\\n\",\n\t\t\t\t  __func__, entry->beamform_entry_state);\n\t\t\treturn false;\n\t\t} else {\n\t\t\tentry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING;\n\t\t\tentry->is_sound = true;\n\t\t}\n\n\t\tbeam_info->beamformee_cur_idx = idx;\n\t}\n\n\t/*@2014.12.22 Luke: Need to be checked*/\n\t/*@GET_TXBF_INFO(adapter)->fTxbfSet(adapter, TXBF_SET_SOUNDING_STATUS, (u8*)&idx);*/\n\n\tif (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER)\n\t\tret = beamforming_send_ht_ndpa_packet(dm, ra, BW, NORMAL_QUEUE);\n\telse\n\t\tret = beamforming_send_vht_ndpa_packet(dm, ra, entry->aid, BW, NORMAL_QUEUE);\n\n\tif (ret == false) {\n\t\tbeamforming_leave(dm, ra);\n\t\tentry->is_beamforming_in_progress = false;\n\t\treturn false;\n\t}\n\n/*@--------------------------\n\t * Send BF Report Poll for MU BF\n\t--------------------------*/\n#ifdef SUPPORT_MU_BF\n#if (SUPPORT_MU_BF == 1)\n\tif (beam_info->beamformee_mu_cnt <= 1)\n\t\tgoto out;\n\n\t/* @More than 1 MU STA*/\n\tfor (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {\n\t\tentry = &beam_info->beamformee_entry[i];\n\t\tif (!entry->is_mu_sta)\n\t\t\tcontinue;\n\n\t\tif (!is_get_first_bfee) {\n\t\t\tis_get_first_bfee = true;\n\t\t\tcontinue;\n\t\t}\n\n\t\tpoll_sta_cnt++;\n\t\tif (poll_sta_cnt == (beam_info->beamformee_mu_cnt - 1)) /* The last STA*/\n\t\t\tsend_sw_vht_bf_report_poll(dm, entry->mac_addr, true);\n\t\telse\n\t\t\tsend_sw_vht_bf_report_poll(dm, entry->mac_addr, false);\n\t}\nout:\n#endif\n#endif\n\treturn true;\n}\n\nboolean\nbeamforming_start_fw(\n\tvoid *dm_void,\n\tu8 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMEE_ENTRY *entry;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\n\tentry = &beam_info->beamformee_entry[idx];\n\tif (entry->is_used == false) {\n\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t  \"Skip Beamforming, no entry for idx =%d\\n\", idx);\n\t\treturn false;\n\t}\n\n\tentry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING;\n\tentry->is_sound = true;\n\thal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx);\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] End, idx=0x%X\\n\", __func__, idx);\n\treturn true;\n}\n\nvoid beamforming_check_sounding_success(\n\tvoid *dm_void,\n\tboolean status)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx];\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[David]@%s Start!\\n\", __func__);\n\n\tif (status == 1) {\n\t\tif (entry->log_status_fail_cnt == 21)\n\t\t\tbeamforming_dym_period(dm, status);\n\t\tentry->log_status_fail_cnt = 0;\n\t} else if (entry->log_status_fail_cnt <= 20) {\n\t\tentry->log_status_fail_cnt++;\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s log_status_fail_cnt %d\\n\", __func__,\n\t\t\t  entry->log_status_fail_cnt);\n\t}\n\tif (entry->log_status_fail_cnt > 20) {\n\t\tentry->log_status_fail_cnt = 21;\n\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t  \"%s log_status_fail_cnt > 20, Stop SOUNDING\\n\",\n\t\t\t  __func__);\n\t\tbeamforming_dym_period(dm, status);\n\t}\n}\n\nvoid phydm_beamforming_end_sw(\n\tvoid *dm_void,\n\tboolean status)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx];\n\n\tif (beam_info->is_mu_sounding) {\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s: MU sounding done\\n\", __func__);\n\t\tbeam_info->is_mu_sounding_in_progress = false;\n\t\thal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS,\n\t\t\t\t (u8 *)&beam_info->beamformee_cur_idx);\n\t} else {\n\t\tif (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSING) {\n\t\t\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] BeamformStatus %d\\n\",\n\t\t\t\t  __func__, entry->beamform_entry_state);\n\t\t\treturn;\n\t\t}\n\n\t\tif (beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7 && beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9 && !beam_info->snding3ss) {\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"[%s] VHT3SS 7,8,9, do not apply V matrix.\\n\",\n\t\t\t\t  __func__);\n\t\t\tentry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;\n\t\t\thal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS,\n\t\t\t\t\t (u8 *)&beam_info->beamformee_cur_idx);\n\t\t} else if (status == 1) {\n\t\t\tentry->log_status_fail_cnt = 0;\n\t\t\tentry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;\n\t\t\thal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS,\n\t\t\t\t\t (u8 *)&beam_info->beamformee_cur_idx);\n\t\t} else {\n\t\t\tentry->log_status_fail_cnt++;\n\t\t\tentry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;\n\t\t\thal_com_txbf_set(dm, TXBF_SET_TX_PATH_RESET,\n\t\t\t\t\t (u8 *)&beam_info->beamformee_cur_idx);\n\t\t\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] log_status_fail_cnt %d\\n\",\n\t\t\t\t  __func__, entry->log_status_fail_cnt);\n\t\t}\n\n\t\tif (entry->log_status_fail_cnt > 50) {\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"%s log_status_fail_cnt > 50, Stop SOUNDING\\n\",\n\t\t\t\t  __func__);\n\t\t\tentry->is_sound = false;\n\t\t\tbeamforming_deinit_entry(dm, entry->mac_addr);\n\n\t\t\t/*@Modified by David - Every action of deleting entry should follow by Notify*/\n\t\t\tphydm_beamforming_notify(dm);\n\t\t}\n\n\t\tentry->is_beamforming_in_progress = false;\n\t}\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s: status=%d\\n\", __func__, status);\n}\n\nvoid beamforming_timer_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *dm_void\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tvoid *context\n#endif\n\t)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tvoid *adapter = (void *)context;\n\tPHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->odmpriv;\n#endif\n\tboolean ret = false;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);\n\tstruct _RT_BEAMFORMEE_ENTRY *entry = &(beam_info->beamformee_entry[beam_info->beamformee_cur_idx]);\n\tstruct _RT_SOUNDING_INFO *sound_info = &(beam_info->sounding_info);\n\tboolean is_beamforming_in_progress;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s Start!\\n\", __func__);\n\n\tif (beam_info->is_mu_sounding)\n\t\tis_beamforming_in_progress = beam_info->is_mu_sounding_in_progress;\n\telse\n\t\tis_beamforming_in_progress = entry->is_beamforming_in_progress;\n\n\tif (is_beamforming_in_progress) {\n\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t  \"is_beamforming_in_progress, reset it\\n\");\n\t\tphydm_beamforming_end_sw(dm, 0);\n\t}\n\n\tret = phydm_beamforming_select_beam_entry(dm, beam_info);\n#if (SUPPORT_MU_BF == 1)\n\tif (ret && beam_info->beamformee_mu_cnt > 1)\n\t\tret = 1;\n\telse\n\t\tret = 0;\n#endif\n\tif (ret)\n\t\tret = beamforming_start_sw(dm, sound_info->sound_idx, sound_info->sound_mode, sound_info->sound_bw);\n\telse\n\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t  \"%s, Error value return from BeamformingStart_V2\\n\",\n\t\t\t  __func__);\n\n\tif (beam_info->beamformee_su_cnt != 0 || beam_info->beamformee_mu_cnt > 1) {\n\t\tif (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)\n\t\t\todm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period);\n\t\telse {\n\t\t\tu32 val = (sound_info->sound_period << 16) | HAL_TIMER_TXBF;\n\t\t\tphydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_RESTART, (u8 *)(&val));\n\t\t}\n\t}\n}\n\nvoid beamforming_sw_timer_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tstruct phydm_timer_list *timer\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tvoid *function_context\n#endif\n\t)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter = (void *)timer->Adapter;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\tbeamforming_timer_callback(dm);\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tstruct dm_struct *dm = (struct dm_struct *)function_context;\n\tvoid *adapter = dm->adapter;\n\n\tif (*dm->is_net_closed == true)\n\t\treturn;\n\tphydm_run_in_thread_cmd(dm, beamforming_timer_callback, adapter);\n#endif\n}\n\nvoid phydm_beamforming_init(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMING_OID_INFO *beam_oid_info = &beam_info->beamforming_oid_info;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\n#ifdef BEAMFORMING_VERSION_1\n\tif (hal_data->beamforming_version != BEAMFORMING_VERSION_1) {\n\t\treturn;\n\t}\n#endif\n#endif\n\n\tbeam_oid_info->sound_oid_mode = SOUNDING_STOP_OID_TIMER;\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s mode (%d)\\n\", __func__,\n\t\t  beam_oid_info->sound_oid_mode);\n\n\tbeam_info->beamformee_su_cnt = 0;\n\tbeam_info->beamformer_su_cnt = 0;\n\tbeam_info->beamformee_mu_cnt = 0;\n\tbeam_info->beamformer_mu_cnt = 0;\n\tbeam_info->beamformee_mu_reg_maping = 0;\n\tbeam_info->mu_ap_index = 0;\n\tbeam_info->is_mu_sounding = false;\n\tbeam_info->first_mu_bfee_index = 0xFF;\n\tbeam_info->apply_v_matrix = true;\n\tbeam_info->snding3ss = false;\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tbeam_info->source_adapter = dm->adapter;\n#endif\n\thal_com_txbf_beamform_init(dm);\n}\n\nboolean\nphydm_acting_determine(\n\tvoid *dm_void,\n\tenum phydm_acting_type type)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tboolean ret = false;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter = dm->beamforming_info.source_adapter;\n#else\n\tstruct _ADAPTER *adapter = dm->adapter;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tif (type == phydm_acting_as_ap)\n\t\tret = ACTING_AS_AP(adapter);\n\telse if (type == phydm_acting_as_ibss)\n\t\tret = ACTING_AS_IBSS(((PADAPTER)(adapter)));\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\n\tif (type == phydm_acting_as_ap)\n\t\tret = check_fwstate(pmlmepriv, WIFI_AP_STATE);\n\telse if (type == phydm_acting_as_ibss)\n\t\tret = check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);\n#endif\n\n\treturn ret;\n}\n\nvoid beamforming_enter(void *dm_void, u16 sta_idx, u8 *my_mac_addr)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 bfer_bfee_idx = 0xff;\n\n\tif (beamforming_init_entry(dm, sta_idx, &bfer_bfee_idx, my_mac_addr))\n\t\thal_com_txbf_set(dm, TXBF_SET_SOUNDING_ENTER, (u8 *)&bfer_bfee_idx);\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] End!\\n\", __func__);\n}\n\nvoid beamforming_leave(\n\tvoid *dm_void,\n\tu8 *RA)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (RA != NULL) {\n\t\tbeamforming_deinit_entry(dm, RA);\n\t\tphydm_beamforming_notify(dm);\n\t}\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] End!!\\n\", __func__);\n}\n\n#if 0\n/* Nobody calls this function */\nvoid\nphydm_beamforming_set_txbf_en(\n\tvoid\t\t*dm_void,\n\tu8\t\t\tmac_id,\n\tboolean\t\t\tis_txbf\n)\n{\n\tstruct dm_struct\t\t\t\t*dm = (struct dm_struct *)dm_void;\n\tu8\t\t\t\t\tidx = 0;\n\tstruct _RT_BEAMFORMEE_ENTRY\t*entry;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s Start!\\n\", __func__);\n\n\tentry = phydm_beamforming_get_entry_by_mac_id(dm, mac_id, &idx);\n\n\tif (entry == NULL)\n\t\treturn;\n\telse\n\t\tentry->is_txbf = is_txbf;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s mac_id %d TxBF %d\\n\", __func__,\n\t\t  entry->mac_id, entry->is_txbf);\n\n\tphydm_beamforming_notify(dm);\n}\n#endif\n\nenum beamforming_cap\nphydm_beamforming_get_beam_cap(\n\tvoid *dm_void,\n\tstruct _RT_BEAMFORMING_INFO *beam_info)\n{\n\tu8 i;\n\tboolean is_self_beamformer = false;\n\tboolean is_self_beamformee = false;\n\tstruct _RT_BEAMFORMEE_ENTRY beamformee_entry;\n\tstruct _RT_BEAMFORMER_ENTRY beamformer_entry;\n\tenum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tfor (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {\n\t\tbeamformee_entry = beam_info->beamformee_entry[i];\n\n\t\tif (beamformee_entry.is_used) {\n\t\t\tis_self_beamformer = true;\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"[%s] BFee entry %d is_used=true\\n\", __func__,\n\t\t\t\t  i);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tfor (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) {\n\t\tbeamformer_entry = beam_info->beamformer_entry[i];\n\n\t\tif (beamformer_entry.is_used) {\n\t\t\tis_self_beamformee = true;\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"[%s]: BFer entry %d is_used=true\\n\",\n\t\t\t\t  __func__, i);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (is_self_beamformer)\n\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP);\n\tif (is_self_beamformee)\n\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP);\n\n\treturn beamform_cap;\n}\n\nboolean\nbeamforming_control_v1(\n\tvoid *dm_void,\n\tu8 *RA,\n\tu8 AID,\n\tu8 mode,\n\tenum channel_width BW,\n\tu8 rate)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tboolean ret = true;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s Start!\\n\", __func__);\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"AID (%d), mode (%d), BW (%d)\\n\", AID, mode,\n\t\t  BW);\n\n\tswitch (mode) {\n\tcase 0:\n\t\tret = beamforming_start_v1(dm, RA, 0, BW, rate);\n\t\tbreak;\n\tcase 1:\n\t\tret = beamforming_start_v1(dm, RA, 1, BW, rate);\n\t\tbreak;\n\tcase 2:\n\t\tphydm_beamforming_ndpa_rate(dm, BW, rate);\n\t\tret = beamforming_send_vht_ndpa_packet(dm, RA, AID, BW, NORMAL_QUEUE);\n\t\tbreak;\n\tcase 3:\n\t\tphydm_beamforming_ndpa_rate(dm, BW, rate);\n\t\tret = beamforming_send_ht_ndpa_packet(dm, RA, BW, NORMAL_QUEUE);\n\t\tbreak;\n\t}\n\treturn ret;\n}\n\n/*Only OID uses this function*/\nboolean\nphydm_beamforming_control_v2(\n\tvoid *dm_void,\n\tu8 idx,\n\tu8 mode,\n\tenum channel_width BW,\n\tu16 period)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMING_OID_INFO *beam_oid_info = &beam_info->beamforming_oid_info;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s Start!\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_TXBF, \"idx (%d), mode (%d), BW (%d), period (%d)\\n\",\n\t\t  idx, mode, BW, period);\n\n\tbeam_oid_info->sound_oid_idx = idx;\n\tbeam_oid_info->sound_oid_mode = (enum sounding_mode)mode;\n\tbeam_oid_info->sound_oid_bw = BW;\n\tbeam_oid_info->sound_oid_period = period;\n\n\tphydm_beamforming_notify(dm);\n\n\treturn true;\n}\n\nvoid phydm_beamforming_watchdog(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s Start!\\n\", __func__);\n\n\tif (beam_info->beamformee_su_cnt == 0)\n\t\treturn;\n\n\tbeamforming_dym_period(dm, 0);\n}\nenum beamforming_cap\nphydm_get_beamform_cap(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct cmn_sta_info *sta = NULL;\n\tstruct bf_cmn_info *bf_info = NULL;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tvoid *adapter = dm->adapter;\n\tenum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE;\n\tu8 macid;\n\tu8 ht_curbeamformcap = 0;\n\tu16 vht_curbeamformcap = 0;\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tPMGNT_INFO p_MgntInfo = &(((PADAPTER)(adapter))->MgntInfo);\n\tPRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_MgntInfo);\n\tPRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_MgntInfo);\n\n\tht_curbeamformcap = p_ht_info->HtCurBeamform;\n\tvht_curbeamformcap = p_vht_info->VhtCurBeamform;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[%s] WIN ht_curcap = %d ; vht_curcap = %d\\n\", __func__,\n\t\t  ht_curbeamformcap, vht_curbeamformcap);\n\n\tif (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) /*We are Beamformee because the STA is Beamformer*/\n\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP));\n\n\t/*We are Beamformer because the STA is Beamformee*/\n\tif (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMEE_ENABLE))\n\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP));\n\n#if (ODM_IC_11AC_SERIES_SUPPORT == 1)\n\n\t/* We are Beamformee because the STA is SU Beamformer*/\n\tif (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMER_ENABLE))\n\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP));\n\n\t/* We are Beamformer because the STA is SU Beamformee*/\n\tif (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE))\n\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP));\n\n\t/* We are Beamformee because the STA is MU Beamformer*/\n\tif (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE))\n\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP));\n#endif\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\n\tfor (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {\n\t\tsta = dm->phydm_sta_info[macid];\n\n\t\tif (!is_sta_active(sta))\n\t\t\tcontinue;\n\n\t\tbf_info = &sta->bf_info;\n\t\tvht_curbeamformcap = bf_info->vht_beamform_cap;\n\t\tht_curbeamformcap = bf_info->ht_beamform_cap;\n\n\t\tif (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) /*We are Beamformee because the STA is Beamformer*/\n\t\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP));\n\n\t\t/*We are Beamformer because the STA is Beamformee*/\n\t\tif (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMEE_ENABLE))\n\t\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP));\n\n#if (ODM_IC_11AC_SERIES_SUPPORT == 1)\n\t\t/* We are Beamformee because the STA is SU Beamformer*/\n\t\tif (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMER_ENABLE))\n\t\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP));\n\n\t\t/* We are Beamformer because the STA is SU Beamformee*/\n\t\tif (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE))\n\t\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP));\n\n\t\t/* We are Beamformee because the STA is MU Beamformer*/\n\t\tif (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE))\n\t\t\tbeamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP));\n#endif\n\t}\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[%s] CE ht_curcap = %d ; vht_curcap = %d\\n\",\n\t\t  __func__, ht_curbeamformcap, vht_curbeamformcap);\n\n#endif\n\n\treturn beamform_cap;\n}\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_beamforming.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __INC_PHYDM_BEAMFORMING_H\n#define __INC_PHYDM_BEAMFORMING_H\n\n/*@Beamforming Related*/\n#include \"txbf/halcomtxbf.h\"\n#include \"txbf/haltxbfjaguar.h\"\n#include \"txbf/haltxbf8192e.h\"\n#include \"txbf/haltxbf8814a.h\"\n#include \"txbf/haltxbf8822b.h\"\n#include \"txbf/haltxbfinterface.h\"\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\n#define eq_mac_addr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0)\n#define cp_mac_addr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5])\n\n#endif\n\n#define MAX_BEAMFORMEE_SU 2\n#define MAX_BEAMFORMER_SU 2\n#if (RTL8822B_SUPPORT == 1)\n#define MAX_BEAMFORMEE_MU 6\n#define MAX_BEAMFORMER_MU 1\n#else\n#define MAX_BEAMFORMEE_MU 0\n#define MAX_BEAMFORMER_MU 0\n#endif\n\n#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU)\n#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU)\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n/*@for different naming between WIN and CE*/\n#define BEACON_QUEUE BCN_QUEUE_INX\n#define NORMAL_QUEUE MGT_QUEUE_INX\n#define RT_DISABLE_FUNC RTW_DISABLE_FUNC\n#define RT_ENABLE_FUNC RTW_ENABLE_FUNC\n#endif\n\nenum beamforming_entry_state {\n\tBEAMFORMING_ENTRY_STATE_UNINITIALIZE,\n\tBEAMFORMING_ENTRY_STATE_INITIALIZEING,\n\tBEAMFORMING_ENTRY_STATE_INITIALIZED,\n\tBEAMFORMING_ENTRY_STATE_PROGRESSING,\n\tBEAMFORMING_ENTRY_STATE_PROGRESSED\n};\n\nenum beamforming_notify_state {\n\tBEAMFORMING_NOTIFY_NONE,\n\tBEAMFORMING_NOTIFY_ADD,\n\tBEAMFORMING_NOTIFY_DELETE,\n\tBEAMFORMEE_NOTIFY_ADD_SU,\n\tBEAMFORMEE_NOTIFY_DELETE_SU,\n\tBEAMFORMEE_NOTIFY_ADD_MU,\n\tBEAMFORMEE_NOTIFY_DELETE_MU,\n\tBEAMFORMING_NOTIFY_RESET\n};\n\nenum beamforming_cap {\n\tBEAMFORMING_CAP_NONE = 0x0,\n\tBEAMFORMER_CAP_HT_EXPLICIT = BIT(1),\n\tBEAMFORMEE_CAP_HT_EXPLICIT = BIT(2),\n\tBEAMFORMER_CAP_VHT_SU = BIT(5), /* @Self has er Cap, because Reg er  & peer ee */\n\tBEAMFORMEE_CAP_VHT_SU = BIT(6), /* @Self has ee Cap, because Reg ee & peer er */\n\tBEAMFORMER_CAP_VHT_MU = BIT(7), /* @Self has er Cap, because Reg er  & peer ee */\n\tBEAMFORMEE_CAP_VHT_MU = BIT(8), /* @Self has ee Cap, because Reg ee & peer er */\n\tBEAMFORMER_CAP = BIT(9),\n\tBEAMFORMEE_CAP = BIT(10),\n};\n\nenum sounding_mode {\n\tSOUNDING_SW_VHT_TIMER = 0x0,\n\tSOUNDING_SW_HT_TIMER = 0x1,\n\tsounding_stop_all_timer = 0x2,\n\tSOUNDING_HW_VHT_TIMER = 0x3,\n\tSOUNDING_HW_HT_TIMER = 0x4,\n\tSOUNDING_STOP_OID_TIMER = 0x5,\n\tSOUNDING_AUTO_VHT_TIMER = 0x6,\n\tSOUNDING_AUTO_HT_TIMER = 0x7,\n\tSOUNDING_FW_VHT_TIMER = 0x8,\n\tSOUNDING_FW_HT_TIMER = 0x9,\n};\n\nstruct _RT_BEAMFORM_STAINFO {\n\tu8 *ra;\n\tu16 aid;\n\tu16 mac_id;\n\tu8 my_mac_addr[6];\n\t/*WIRELESS_MODE\t\t\t\twireless_mode;*/\n\tenum channel_width bw;\n\tenum beamforming_cap beamform_cap;\n\tu8 ht_beamform_cap;\n\tu16 vht_beamform_cap;\n\tu8 cur_beamform;\n\tu16 cur_beamform_vht;\n};\n\nstruct _RT_BEAMFORMEE_ENTRY {\n\tboolean is_used;\n\tboolean is_txbf;\n\tboolean is_sound;\n\tu16 aid; /*Used to construct AID field of NDPA packet.*/\n\tu16 mac_id; /*Used to Set Reg42C in IBSS mode. */\n\tu16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */\n\tu8 g_id; /*Used to fill Tx DESC*/\n\tu8 my_mac_addr[6];\n\tu8 mac_addr[6]; /*@Used to fill Reg6E4 to fill Mac address of CSI report frame.*/\n\tenum channel_width sound_bw; /*Sounding band_width*/\n\tu16 sound_period;\n\tenum beamforming_cap beamform_entry_cap;\n\tenum beamforming_entry_state beamform_entry_state;\n\tboolean is_beamforming_in_progress;\n\t/*@u8\tlog_seq;\t\t\t\t\t\t\t\t\t// Move to _RT_BEAMFORMER_ENTRY*/\n\t/*@u16\tlog_retry_cnt:3;\t\t// 0~4\t\t\t\t// Move to _RT_BEAMFORMER_ENTRY*/\n\t/*@u16\tLogSuccessCnt:2;\t\t// 0~2\t\t\t\t// Move to _RT_BEAMFORMER_ENTRY*/\n\tu16 log_status_fail_cnt : 5; /* @0~21 */\n\tu16 default_csi_cnt : 5; /* @0~21 */\n\tu8 csi_matrix[327];\n\tu16 csi_matrix_len;\n\tu8 num_of_sounding_dim;\n\tu8 comp_steering_num_of_bfer;\n\tu8 su_reg_index;\n\t/*@For MU-MIMO*/\n\tboolean is_mu_sta;\n\tu8 mu_reg_index;\n\tu8 gid_valid[8];\n\tu8 user_position[16];\n};\n\nstruct _RT_BEAMFORMER_ENTRY {\n\tboolean is_used;\n\t/*P_AID of BFer entry is probably not used*/\n\tu16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */\n\tu8 g_id;\n\tu8 my_mac_addr[6];\n\tu8 mac_addr[6];\n\tenum beamforming_cap beamform_entry_cap;\n\tu8 num_of_sounding_dim;\n\tu8 clock_reset_times; /*@Modified by Jeffery @2015-04-10*/\n\tu8 pre_log_seq; /*@Modified by Jeffery @2015-03-30*/\n\tu8 log_seq; /*@Modified by Jeffery @2014-10-29*/\n\tu16 log_retry_cnt : 3; /*@Modified by Jeffery @2014-10-29*/\n\tu16 log_success : 2; /*@Modified by Jeffery @2014-10-29*/\n\tu8 su_reg_index;\n\t/*@For MU-MIMO*/\n\tboolean is_mu_ap;\n\tu8 gid_valid[8];\n\tu8 user_position[16];\n\tu16 aid;\n};\n\nstruct _RT_SOUNDING_INFO {\n\tu8 sound_idx;\n\tenum channel_width sound_bw;\n\tenum sounding_mode sound_mode;\n\tu16 sound_period;\n};\n\nstruct _RT_BEAMFORMING_OID_INFO {\n\tu8 sound_oid_idx;\n\tenum channel_width sound_oid_bw;\n\tenum sounding_mode sound_oid_mode;\n\tu16 sound_oid_period;\n};\n\nstruct _RT_BEAMFORMING_INFO {\n\tenum beamforming_cap beamform_cap;\n\tstruct _RT_BEAMFORMEE_ENTRY beamformee_entry[BEAMFORMEE_ENTRY_NUM];\n\tstruct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM];\n\tstruct _RT_BEAMFORM_STAINFO beamform_sta_info;\n\tu8 beamformee_cur_idx;\n\tstruct phydm_timer_list beamforming_timer;\n\tstruct phydm_timer_list mu_timer;\n\tstruct _RT_SOUNDING_INFO sounding_info;\n\tstruct _RT_BEAMFORMING_OID_INFO beamforming_oid_info;\n\tstruct _HAL_TXBF_INFO txbf_info;\n\tu8 sounding_sequence;\n\tu8 beamformee_su_cnt;\n\tu8 beamformer_su_cnt;\n\tu32 beamformee_su_reg_maping;\n\tu32 beamformer_su_reg_maping;\n\t/*@For MU-MINO*/\n\tu8 beamformee_mu_cnt;\n\tu8 beamformer_mu_cnt;\n\tu32 beamformee_mu_reg_maping;\n\tu8 mu_ap_index;\n\tboolean is_mu_sounding;\n\tu8 first_mu_bfee_index;\n\tboolean is_mu_sounding_in_progress;\n\tboolean dbg_disable_mu_tx;\n\tboolean apply_v_matrix;\n\tboolean snding3ss;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *source_adapter;\n#endif\n\t/* @Control register */\n\tu32 reg_mu_tx_ctrl; /* @For USB/SDIO interfaces aync I/O */\n\tu8 tx_bf_data_rate;\n\tu8 last_usb_hub;\n};\n\nvoid phydm_get_txbf_device_num(\n\tvoid *dm_void,\n\tu8 macid);\n\nstruct _RT_NDPA_STA_INFO {\n\tu16 aid : 12;\n\tu16 feedback_type : 1;\n\tu16 nc_index : 3;\n};\n\nenum phydm_acting_type {\n\tphydm_acting_as_ibss = 0,\n\tphydm_acting_as_ap = 1\n};\n\nenum beamforming_cap\nphydm_beamforming_get_entry_beam_cap_by_mac_id(\n\tvoid *dm_void,\n\tu8 mac_id);\n\nstruct _RT_BEAMFORMEE_ENTRY *\nphydm_beamforming_get_bfee_entry_by_addr(\n\tvoid *dm_void,\n\tu8 *RA,\n\tu8 *idx);\n\nstruct _RT_BEAMFORMER_ENTRY *\nphydm_beamforming_get_bfer_entry_by_addr(\n\tvoid *dm_void,\n\tu8 *TA,\n\tu8 *idx);\n\nvoid phydm_beamforming_notify(\n\tvoid *dm_void);\n\nboolean\nphydm_acting_determine(\n\tvoid *dm_void,\n\tenum phydm_acting_type type);\n\nvoid beamforming_enter(void *dm_void, u16 sta_idx, u8 *my_mac_addr);\n\nvoid beamforming_leave(\n\tvoid *dm_void,\n\tu8 *RA);\n\nboolean\nbeamforming_start_fw(\n\tvoid *dm_void,\n\tu8 idx);\n\nvoid beamforming_check_sounding_success(\n\tvoid *dm_void,\n\tboolean status);\n\nvoid phydm_beamforming_end_sw(\n\tvoid *dm_void,\n\tboolean status);\n\nvoid beamforming_timer_callback(\n\tvoid *dm_void);\n\nvoid phydm_beamforming_init(\n\tvoid *dm_void);\n\nenum beamforming_cap\nphydm_beamforming_get_beam_cap(\n\tvoid *dm_void,\n\tstruct _RT_BEAMFORMING_INFO *beam_info);\n\nenum beamforming_cap\nphydm_get_beamform_cap(\n\tvoid *dm_void);\n\nboolean\nbeamforming_control_v1(\n\tvoid *dm_void,\n\tu8 *RA,\n\tu8 AID,\n\tu8 mode,\n\tenum channel_width BW,\n\tu8 rate);\n\nboolean\nphydm_beamforming_control_v2(\n\tvoid *dm_void,\n\tu8 idx,\n\tu8 mode,\n\tenum channel_width BW,\n\tu16 period);\n\nvoid phydm_beamforming_watchdog(\n\tvoid *dm_void);\n\nvoid beamforming_sw_timer_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tstruct phydm_timer_list *timer\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tvoid *function_context\n#endif\n\t);\n\nboolean\nbeamforming_send_ht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tenum channel_width BW,\n\tu8 q_idx);\n\nboolean\nbeamforming_send_vht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tu16 AID,\n\tenum channel_width BW,\n\tu8 q_idx);\n\n#else\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))\n#define beamforming_gid_paid(adapter, tcb)\n#define phydm_acting_determine(dm, type) false\n#define beamforming_enter(dm, sta_idx, my_mac_addr)\n#define beamforming_leave(dm, RA)\n#define beamforming_end_fw(dm)\n#define beamforming_control_v1(dm, RA, AID, mode, BW, rate) true\n#define beamforming_control_v2(dm, idx, mode, BW, period) true\n#define phydm_beamforming_end_sw(dm, _status)\n#define beamforming_timer_callback(dm)\n#define phydm_beamforming_init(dm)\n#define phydm_beamforming_control_v2(dm, _idx, _mode, _BW, _period) false\n#define beamforming_watchdog(dm)\n#define phydm_beamforming_watchdog(dm)\n#endif /*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/\n#endif /*@#ifdef PHYDM_BEAMFORMING_SUPPORT*/\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_cck_pd.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n ************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#ifdef PHYDM_SUPPORT_CCKPD\n#ifdef PHYDM_COMPILE_CCKPD_TYPE1\nvoid phydm_write_cck_pd_type1(void *dm_void, u8 cca_th)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\n\tPHYDM_DBG(dm, DBG_CCKPD, \"[%s] cck_cca_th=((0x%x))\\n\",\n\t\t  __func__, cca_th);\n\n\todm_write_1byte(dm, R_0xa0a, cca_th);\n\tcckpd_t->cur_cck_cca_thres = cca_th;\n}\n\nvoid phydm_set_cckpd_lv_type1(void *dm_void, enum cckpd_lv lv)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\tu8 pd_th = 0;\n\n\tPHYDM_DBG(dm, DBG_CCKPD, \"%s ======>\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_CCKPD, \"lv: (%d) -> (%d)\\n\", cckpd_t->cck_pd_lv, lv);\n\n\tif (cckpd_t->cck_pd_lv == lv) {\n\t\tPHYDM_DBG(dm, DBG_CCKPD, \"stay in lv=%d\\n\", lv);\n\t\treturn;\n\t}\n\n\tcckpd_t->cck_pd_lv = lv;\n\tcckpd_t->cck_fa_ma = CCK_FA_MA_RESET;\n\n\tif (lv == CCK_PD_LV_4)\n\t\tpd_th = 0xed;\n\telse if (lv == CCK_PD_LV_3)\n\t\tpd_th = 0xdd;\n\telse if (lv == CCK_PD_LV_2)\n\t\tpd_th = 0xcd;\n\telse if (lv == CCK_PD_LV_1)\n\t\tpd_th = 0x83;\n\telse if (lv == CCK_PD_LV_0)\n\t\tpd_th = 0x40;\n\n\tphydm_write_cck_pd_type1(dm, pd_th);\n}\n\nvoid phydm_cckpd_type1(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\tenum cckpd_lv lv = CCK_PD_LV_INIT;\n\tboolean is_update = true;\n\n\tif (dm->is_linked) {\n\t#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\t\tif (dm->rssi_min > 60) {\n\t\t\tlv = CCK_PD_LV_3;\n\t\t} else if (dm->rssi_min > 35) {\n\t\t\tlv = CCK_PD_LV_2;\n\t\t} else if (dm->rssi_min > 20) {\n\t\t\tif (cckpd_t->cck_fa_ma > 500)\n\t\t\t\tlv = CCK_PD_LV_2;\n\t\t\telse if (cckpd_t->cck_fa_ma < 250)\n\t\t\t\tlv = CCK_PD_LV_1;\n\t\t\telse\n\t\t\t\tis_update = false;\n\t\t} else { /*RSSI < 20*/\n\t\t\tlv = CCK_PD_LV_1;\n\t\t}\n\t#else /*ODM_AP*/\n\t\tif (dig_t->cur_ig_value > 0x32)\n\t\t\tlv = CCK_PD_LV_4;\n\t\telse if (dig_t->cur_ig_value > 0x2a)\n\t\t\tlv = CCK_PD_LV_3;\n\t\telse if (dig_t->cur_ig_value > 0x24)\n\t\t\tlv = CCK_PD_LV_2;\n\t\telse\n\t\t\tlv = CCK_PD_LV_1;\n\t#endif\n\t} else {\n\t\tif (cckpd_t->cck_fa_ma > 1000)\n\t\t\tlv = CCK_PD_LV_1;\n\t\telse if (cckpd_t->cck_fa_ma < 500)\n\t\t\tlv = CCK_PD_LV_0;\n\t\telse\n\t\t\tis_update = false;\n\t}\n\n\t/*[Abnormal case] =================================================*/\n\t#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t/*@HP 22B LPS power consumption issue & [PCIE-1596]*/\n\tif (dm->hp_hw_id && dm->traffic_load == TRAFFIC_ULTRA_LOW) {\n\t\tlv = CCK_PD_LV_0;\n\t\tPHYDM_DBG(dm, DBG_CCKPD, \"CCKPD Abnormal case1\\n\");\n\t} else if ((dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) &&\n\t    cckpd_t->cck_fa_ma > 200 && dm->rssi_min <= 20) {\n\t\tlv = CCK_PD_LV_1;\n\t\tcckpd_t->cck_pd_lv = lv;\n\t\tphydm_write_cck_pd_type1(dm, 0xc3); /*@for ASUS OTA test*/\n\t\tis_update = false;\n\t\tPHYDM_DBG(dm, DBG_CCKPD, \"CCKPD Abnormal case2\\n\");\n\t}\n\t#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\t\t#ifdef MCR_WIRELESS_EXTEND\n\t\tlv = CCK_PD_LV_2;\n\t\tcckpd_t->cck_pd_lv = lv;\n\t\tphydm_write_cck_pd_type1(dm, 0x43);\n\t\tis_update = false;\n\t\tPHYDM_DBG(dm, DBG_CCKPD, \"CCKPD Abnormal case3\\n\");\n\t\t#endif\n\t#endif\n\t/*=================================================================*/\n\n\tif (is_update)\n\t\tphydm_set_cckpd_lv_type1(dm, lv);\n\n\tPHYDM_DBG(dm, DBG_CCKPD, \"is_linked=%d, lv=%d, pd_th=0x%x\\n\\n\",\n\t\t  dm->is_linked, cckpd_t->cck_pd_lv,\n\t\t  cckpd_t->cur_cck_cca_thres);\n}\n#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE1*/\n\n#ifdef PHYDM_COMPILE_CCKPD_TYPE2\nvoid phydm_write_cck_pd_type2(void *dm_void, u8 cca_th, u8 cca_th_aaa)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\n\tPHYDM_DBG(dm, DBG_CCKPD, \"[%s] pd_th=0x%x, cs_ratio=0x%x\\n\",\n\t\t  __func__, cca_th, cca_th_aaa);\n\n\todm_set_bb_reg(dm, R_0xa08, 0x3f0000, cca_th);\n\todm_set_bb_reg(dm, R_0xaa8, 0x1f0000, cca_th_aaa);\n\tcckpd_t->cur_cck_cca_thres = cca_th;\n\tcckpd_t->cck_cca_th_aaa = cca_th_aaa;\n}\n\nvoid phydm_set_cckpd_lv_type2(void *dm_void, enum cckpd_lv lv)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\tu8 pd_th = 0, cs_ratio = 0, cs_2r_offset = 0;\n\tu8 cck_n_rx = 1;\n\n\tPHYDM_DBG(dm, DBG_CCKPD, \"%s ======>\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_CCKPD, \"lv: (%d) -> (%d)\\n\", cckpd_t->cck_pd_lv, lv);\n\n\t/*@r_mrx & r_cca_mrc*/\n\tcck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(18)) &&\n\t\t    odm_get_bb_reg(dm, R_0xa2c, BIT(22))) ? 2 : 1;\n\n\tif (cckpd_t->cck_pd_lv == lv && cckpd_t->cck_n_rx == cck_n_rx) {\n\t\tPHYDM_DBG(dm, DBG_CCKPD, \"stay in lv=%d\\n\", lv);\n\t\treturn;\n\t}\n\n\tcckpd_t->cck_n_rx = cck_n_rx;\n\tcckpd_t->cck_pd_lv = lv;\n\tcckpd_t->cck_fa_ma = CCK_FA_MA_RESET;\n\n\tif (lv == CCK_PD_LV_4) {\n\t\tcs_ratio = cckpd_t->aaa_default + 8;\n\t\tcs_2r_offset = 5;\n\t\tpd_th = 0xd;\n\t} else if (lv == CCK_PD_LV_3) {\n\t\tcs_ratio = cckpd_t->aaa_default + 6;\n\t\tcs_2r_offset = 4;\n\t\tpd_th = 0xd;\n\t} else if (lv == CCK_PD_LV_2) {\n\t\tcs_ratio = cckpd_t->aaa_default + 4;\n\t\tcs_2r_offset = 3;\n\t\tpd_th = 0xd;\n\t} else if (lv == CCK_PD_LV_1) {\n\t\tcs_ratio = cckpd_t->aaa_default + 2;\n\t\tcs_2r_offset = 1;\n\t\tpd_th = 0x7;\n\t} else if (lv == CCK_PD_LV_0) {\n\t\tcs_ratio = cckpd_t->aaa_default;\n\t\tcs_2r_offset = 0;\n\t\tpd_th = 0x3;\n\t}\n\n\tif (cckpd_t->cck_n_rx == 2) {\n\t\tif (cs_ratio >= cs_2r_offset)\n\t\t\tcs_ratio = cs_ratio - cs_2r_offset;\n\t\telse\n\t\t\tcs_ratio = 0;\n\t}\n\tphydm_write_cck_pd_type2(dm, pd_th, cs_ratio);\n}\n\nvoid phydm_cckpd_type2(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\tenum cckpd_lv lv = CCK_PD_LV_INIT;\n\tu8 igi = dig_t->cur_ig_value;\n\tu8 rssi_min = dm->rssi_min;\n\tboolean is_update = true;\n\n\tPHYDM_DBG(dm, DBG_CCKPD, \"%s ======>\\n\", __func__);\n\n\tif (dm->is_linked) {\n\t\tif (igi > 0x38 && rssi_min > 32) {\n\t\t\tlv = CCK_PD_LV_4;\n\t\t} else if (igi > 0x2a && rssi_min > 32) {\n\t\t\tlv = CCK_PD_LV_3;\n\t\t} else if (igi > 0x24 || (rssi_min > 24 && rssi_min <= 30)) {\n\t\t\tlv = CCK_PD_LV_2;\n\t\t} else if (igi <= 0x24 || rssi_min < 22) {\n\t\t\tif (cckpd_t->cck_fa_ma > 1000) {\n\t\t\t\tlv = CCK_PD_LV_1;\n\t\t\t} else if (cckpd_t->cck_fa_ma < 500) {\n\t\t\t\tlv = CCK_PD_LV_0;\n\t\t\t} else {\n\t\t\t\tis_update = false;\n\t\t\t}\n\t\t} else {\n\t\t\tis_update = false;\n\t\t}\n\t} else {\n\t\tif (cckpd_t->cck_fa_ma > 1000) {\n\t\t\tlv = CCK_PD_LV_1;\n\t\t} else if (cckpd_t->cck_fa_ma < 500) {\n\t\t\tlv = CCK_PD_LV_0;\n\t\t} else {\n\t\t\tis_update = false;\n\t\t}\n\t}\n\n\t/*[Abnormal case] =================================================*/\n\t#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t/*@21C Miracast lag issue & [PCIE-3298]*/\n\tif (dm->support_ic_type & ODM_RTL8821C && rssi_min > 60) {\n\t\tlv = CCK_PD_LV_4;\n\t\tcckpd_t->cck_pd_lv = lv;\n\t\tphydm_write_cck_pd_type2(dm, 0x1d, (cckpd_t->aaa_default + 8));\n\t\tis_update = false;\n\t\tPHYDM_DBG(dm, DBG_CCKPD, \"CCKPD Abnormal case1\\n\");\n\t}\n\t#endif\n\t/*=================================================================*/\n\n\tif (is_update) {\n\t\tphydm_set_cckpd_lv_type2(dm, lv);\n\t}\n\n\tPHYDM_DBG(dm, DBG_CCKPD,\n\t\t  \"is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x\\n\\n\",\n\t\t  dm->is_linked, cckpd_t->cck_pd_lv, cckpd_t->cck_n_rx,\n\t\t  cckpd_t->cck_cca_th_aaa, cckpd_t->cur_cck_cca_thres);\n}\n#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE2*/\n\n#ifdef PHYDM_COMPILE_CCKPD_TYPE3\nvoid phydm_write_cck_pd_type3(void *dm_void, u8 pd_th, u8 cs_ratio,\n\t\t\t      enum cckpd_mode mode)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\n\tPHYDM_DBG(dm, DBG_CCKPD,\n\t\t  \"[%s] mode=%d, pd_th=0x%x, cs_ratio=0x%x\\n\", __func__,\n\t\t  mode, pd_th, cs_ratio);\n\n\tswitch (mode) {\n\tcase CCK_BW20_1R: /*RFBW20_1R*/\n\t{\n\t\tcckpd_t->cur_cck_pd_20m_1r = pd_th;\n\t\tcckpd_t->cur_cck_cs_ratio_20m_1r = cs_ratio;\n\t\todm_set_bb_reg(dm, R_0xac8, 0xff, pd_th);\n\t\todm_set_bb_reg(dm, R_0xad0, 0x1f, cs_ratio);\n\t} break;\n\tcase CCK_BW20_2R: /*RFBW20_2R*/\n\t{\n\t\tcckpd_t->cur_cck_pd_20m_2r = pd_th;\n\t\tcckpd_t->cur_cck_cs_ratio_20m_2r = cs_ratio;\n\t\todm_set_bb_reg(dm, R_0xac8, 0xff00, pd_th);\n\t\todm_set_bb_reg(dm, R_0xad0, 0x3e0, cs_ratio);\n\t} break;\n\tcase CCK_BW40_1R: /*RFBW40_1R*/\n\t{\n\t\tcckpd_t->cur_cck_pd_40m_1r = pd_th;\n\t\tcckpd_t->cur_cck_cs_ratio_40m_1r = cs_ratio;\n\t\todm_set_bb_reg(dm, R_0xacc, 0xff, pd_th);\n\t\todm_set_bb_reg(dm, R_0xad0, 0x1f00000, cs_ratio);\n\t} break;\n\tcase CCK_BW40_2R: /*RFBW40_2R*/\n\t{\n\t\tcckpd_t->cur_cck_pd_40m_2r = pd_th;\n\t\tcckpd_t->cur_cck_cs_ratio_40m_2r = cs_ratio;\n\t\todm_set_bb_reg(dm, R_0xacc, 0xff00, pd_th);\n\t\todm_set_bb_reg(dm, R_0xad0, 0x3e000000, cs_ratio);\n\t} break;\n\n\tdefault:\n\t\t/*@pr_debug(\"[%s] warning!\\n\", __func__);*/\n\t\tbreak;\n\t}\n}\n\nvoid phydm_set_cckpd_lv_type3(void *dm_void, enum cckpd_lv lv)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\tenum cckpd_mode cck_mode = CCK_BW20_2R;\n\tenum channel_width cck_bw = CHANNEL_WIDTH_20;\n\tu8 cck_n_rx = 1;\n\tu8 pd_th;\n\tu8 cs_ratio;\n\n\tPHYDM_DBG(dm, DBG_CCKPD, \"%s ======>\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_CCKPD, \"lv: (%d) -> (%d)\\n\", cckpd_t->cck_pd_lv, lv);\n\n\t/*[Check Nrx]*/\n\tcck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(17))) ? 2 : 1;\n\n\t/*[Check BW]*/\n\tif (odm_get_bb_reg(dm, R_0x800, BIT(0)))\n\t\tcck_bw = CHANNEL_WIDTH_40;\n\telse\n\t\tcck_bw = CHANNEL_WIDTH_20;\n\n\t/*[Check LV]*/\n\tif (cckpd_t->cck_pd_lv == lv &&\n\t    cckpd_t->cck_n_rx == cck_n_rx &&\n\t    cckpd_t->cck_bw == cck_bw) {\n\t\tPHYDM_DBG(dm, DBG_CCKPD, \"stay in lv=%d\\n\", lv);\n\t\treturn;\n\t}\n\n\tcckpd_t->cck_bw = cck_bw;\n\tcckpd_t->cck_n_rx = cck_n_rx;\n\tcckpd_t->cck_pd_lv = lv;\n\tcckpd_t->cck_fa_ma = CCK_FA_MA_RESET;\n\n\tif (cck_n_rx == 2) {\n\t\tif (cck_bw == CHANNEL_WIDTH_20) {\n\t\t\tpd_th = cckpd_t->cck_pd_20m_2r;\n\t\t\tcs_ratio = cckpd_t->cck_cs_ratio_20m_2r;\n\t\t\tcck_mode = CCK_BW20_2R;\n\t\t} else {\n\t\t\tpd_th = cckpd_t->cck_pd_40m_2r;\n\t\t\tcs_ratio = cckpd_t->cck_cs_ratio_40m_2r;\n\t\t\tcck_mode = CCK_BW40_2R;\n\t\t}\n\t} else {\n\t\tif (cck_bw == CHANNEL_WIDTH_20) {\n\t\t\tpd_th = cckpd_t->cck_pd_20m_1r;\n\t\t\tcs_ratio = cckpd_t->cck_cs_ratio_20m_1r;\n\t\t\tcck_mode = CCK_BW20_1R;\n\t\t} else {\n\t\t\tpd_th = cckpd_t->cck_pd_40m_1r;\n\t\t\tcs_ratio = cckpd_t->cck_cs_ratio_40m_1r;\n\t\t\tcck_mode = CCK_BW40_1R;\n\t\t}\n\t}\n\n\tif (lv == CCK_PD_LV_4) {\n\t\tif (cck_n_rx == 2) {\n\t\t\tpd_th += 4;\n\t\t\tcs_ratio += 2;\n\t\t} else {\n\t\t\tpd_th += 4;\n\t\t\tcs_ratio += 3;\n\t\t}\n\t} else if (lv == CCK_PD_LV_3) {\n\t\tif (cck_n_rx == 2) {\n\t\t\tpd_th += 3;\n\t\t\tcs_ratio += 1;\n\t\t} else {\n\t\t\tpd_th += 3;\n\t\t\tcs_ratio += 2;\n\t\t}\n\t} else if (lv == CCK_PD_LV_2) {\n\t\tpd_th += 2;\n\t\tcs_ratio += 1;\n\t} else if (lv == CCK_PD_LV_1) {\n\t\tpd_th += 1;\n\t\tcs_ratio += 1;\n\t}\n\t#if 0\n\telse if (lv == CCK_PD_LV_0) {\n\t\tpd_th += 0;\n\t\tcs_ratio += 0;\n\t}\n\t#endif\n\n\tphydm_write_cck_pd_type3(dm, pd_th, cs_ratio, cck_mode);\n}\n\nvoid phydm_cckpd_type3(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\tenum cckpd_lv lv = CCK_PD_LV_INIT;\n\tu8 igi = dm->dm_dig_table.cur_ig_value;\n\tboolean is_update = true;\n\tu8 pd_th = 0;\n\tu8 cs_ratio = 0;\n\n\tPHYDM_DBG(dm, DBG_CCKPD, \"%s ======>\\n\", __func__);\n\n\tif (dm->is_linked) {\n\t\tif (igi > 0x38 && dm->rssi_min > 32) {\n\t\t\tlv = CCK_PD_LV_4;\n\t\t} else if ((igi > 0x2a) && (dm->rssi_min > 32)) {\n\t\t\tlv = CCK_PD_LV_3;\n\t\t} else if ((igi > 0x24) ||\n\t\t\t   (dm->rssi_min > 24 && dm->rssi_min <= 30)) {\n\t\t\tlv = CCK_PD_LV_2;\n\t\t} else if ((igi <= 0x24) || (dm->rssi_min < 22)) {\n\t\t\tif (cckpd_t->cck_fa_ma > 1000)\n\t\t\t\tlv = CCK_PD_LV_1;\n\t\t\telse if (cckpd_t->cck_fa_ma < 500)\n\t\t\t\tlv = CCK_PD_LV_0;\n\t\t\telse\n\t\t\t\tis_update = false;\n\t\t}\n\t} else {\n\t\tif (cckpd_t->cck_fa_ma > 1000)\n\t\t\tlv = CCK_PD_LV_1;\n\t\telse if (cckpd_t->cck_fa_ma < 500)\n\t\t\tlv = CCK_PD_LV_0;\n\t\telse\n\t\t\tis_update = false;\n\t}\n\n\tif (is_update)\n\t\tphydm_set_cckpd_lv_type3(dm, lv);\n\n\tif (cckpd_t->cck_n_rx == 2) {\n\t\tif (cckpd_t->cck_bw == CHANNEL_WIDTH_20) {\n\t\t\tpd_th = cckpd_t->cur_cck_pd_20m_2r;\n\t\t\tcs_ratio = cckpd_t->cur_cck_cs_ratio_20m_2r;\n\t\t} else {\n\t\t\tpd_th = cckpd_t->cur_cck_pd_40m_2r;\n\t\t\tcs_ratio = cckpd_t->cur_cck_cs_ratio_40m_2r;\n\t\t}\n\t} else {\n\t\tif (cckpd_t->cck_bw == CHANNEL_WIDTH_20) {\n\t\t\tpd_th = cckpd_t->cur_cck_pd_20m_1r;\n\t\t\tcs_ratio = cckpd_t->cur_cck_cs_ratio_20m_1r;\n\t\t} else {\n\t\t\tpd_th = cckpd_t->cur_cck_pd_40m_1r;\n\t\t\tcs_ratio = cckpd_t->cur_cck_cs_ratio_40m_1r;\n\t\t}\n\t}\n\tPHYDM_DBG(dm, DBG_CCKPD,\n\t\t  \"[%dR][%dM] is_linked=%d, lv=%d, cs_ratio=0x%x, pd_th=0x%x\\n\\n\",\n\t\t  cckpd_t->cck_n_rx, 20 << cckpd_t->cck_bw, dm->is_linked,\n\t\t  cckpd_t->cck_pd_lv, cs_ratio, pd_th);\n}\n\nvoid phydm_cck_pd_init_type3(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\tu32 reg_tmp = 0;\n\n\t/*Get Default value*/\n\tcckpd_t->cck_pd_20m_1r = (u8)odm_get_bb_reg(dm, R_0xac8, 0xff);\n\tcckpd_t->cck_pd_20m_2r = (u8)odm_get_bb_reg(dm, R_0xac8, 0xff00);\n\tcckpd_t->cck_pd_40m_1r = (u8)odm_get_bb_reg(dm, R_0xacc, 0xff);\n\tcckpd_t->cck_pd_40m_2r = (u8)odm_get_bb_reg(dm, R_0xacc, 0xff00);\n\n\treg_tmp = odm_get_bb_reg(dm, R_0xad0, MASKDWORD);\n\tcckpd_t->cck_cs_ratio_20m_1r = (u8)(reg_tmp & 0x1f);\n\tcckpd_t->cck_cs_ratio_20m_2r = (u8)((reg_tmp & 0x3e0) >> 5);\n\tcckpd_t->cck_cs_ratio_40m_1r = (u8)((reg_tmp & 0x1f00000) >> 20);\n\tcckpd_t->cck_cs_ratio_40m_2r = (u8)((reg_tmp & 0x3e000000) >> 25);\n\n\tphydm_set_cckpd_lv_type3(dm, CCK_PD_LV_0);\n}\n#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE3*/\n\n#ifdef PHYDM_COMPILE_CCKPD_TYPE4\nvoid phydm_write_cck_pd_type4(void *dm_void, enum cckpd_lv lv,\n\t\t\t      enum cckpd_mode mode)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\tu32 val = 0;\n\n\tPHYDM_DBG(dm, DBG_CCKPD, \"write CCK CCA parameters(CS_ratio & PD)\\n\");\n\tswitch (mode) {\n\tcase CCK_BW20_1R: /*RFBW20_1R*/\n\t{\n\t\tval = cckpd_t->cck_pd_table_jgr3[0][0][0][lv];\n\t\todm_set_bb_reg(dm, R_0x1ac8, 0xff, val);\n\t\tval = cckpd_t->cck_pd_table_jgr3[0][0][1][lv];\n\t\todm_set_bb_reg(dm, R_0x1ad0, 0x1f, val);\n\t} break;\n\tcase CCK_BW40_1R: /*RFBW40_1R*/\n\t{\n\t\tval = cckpd_t->cck_pd_table_jgr3[1][0][0][lv];\n\t\todm_set_bb_reg(dm, R_0x1acc, 0xff, val);\n\t\tval = cckpd_t->cck_pd_table_jgr3[1][0][1][lv];\n\t\todm_set_bb_reg(dm, R_0x1ad0, 0x01F00000, val);\n\t} break;\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tcase CCK_BW20_2R: /*RFBW20_2R*/\n\t{\n\t\tval = cckpd_t->cck_pd_table_jgr3[0][1][0][lv];\n\t\todm_set_bb_reg(dm, R_0x1ac8, 0xff00, val);\n\t\tval = cckpd_t->cck_pd_table_jgr3[0][1][1][lv];\n\t\todm_set_bb_reg(dm, R_0x1ad0, 0x3e0, val);\n\t} break;\n\tcase CCK_BW40_2R: /*RFBW40_2R*/\n\t{\n\t\tval = cckpd_t->cck_pd_table_jgr3[1][1][0][lv];\n\t\todm_set_bb_reg(dm, R_0x1acc, 0xff00, val);\n\t\tval = cckpd_t->cck_pd_table_jgr3[1][1][1][lv];\n\t\todm_set_bb_reg(dm, R_0x1ad0, 0x3E000000, val);\n\t} break;\n\t#endif\n\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\tcase CCK_BW20_3R: /*RFBW20_3R*/\n\t{\n\t\tval = cckpd_t->cck_pd_table_jgr3[0][2][0][lv];\n\t\todm_set_bb_reg(dm, R_0x1ac8, 0xff0000, val);\n\t\tval = cckpd_t->cck_pd_table_jgr3[0][2][1][lv];\n\t\todm_set_bb_reg(dm, R_0x1ad0, 0x7c00, val);\n\t} break;\n\tcase CCK_BW40_3R: /*RFBW40_3R*/\n\t{\n\t\tval = cckpd_t->cck_pd_table_jgr3[1][2][0][lv];\n\t\todm_set_bb_reg(dm, R_0x1acc, 0xff0000, val);\n\t\tval = cckpd_t->cck_pd_table_jgr3[1][2][1][lv] & 0x3;\n\t\todm_set_bb_reg(dm, R_0x1ad0, 0xC0000000, val);\n\t\tval = (cckpd_t->cck_pd_table_jgr3[1][2][1][lv] & 0x1c) >> 2;\n\t\todm_set_bb_reg(dm, R_0x1ad4, 0x7, val);\n\t} break;\n\t#endif\n\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\tcase CCK_BW20_4R: /*RFBW20_4R*/\n\t{\n\t\tval = cckpd_t->cck_pd_table_jgr3[0][3][0][lv];\n\t\todm_set_bb_reg(dm, R_0x1ac8, 0xff000000, val);\n\t\tval = cckpd_t->cck_pd_table_jgr3[0][3][1][lv];\n\t\todm_set_bb_reg(dm, R_0x1ad0, 0xF8000, val);\n\t} break;\n\tcase CCK_BW40_4R: /*RFBW40_4R*/\n\t{\n\t\tval = cckpd_t->cck_pd_table_jgr3[1][3][0][lv];\n\t\todm_set_bb_reg(dm, R_0x1acc, 0xff000000, val);\n\t\tval = cckpd_t->cck_pd_table_jgr3[1][3][1][lv];\n\t\todm_set_bb_reg(dm, R_0x1ad4, 0xf8, val);\n\t} break;\n\t#endif\n\tdefault:\n\t\t/*@pr_debug(\"[%s] warning!\\n\", __func__);*/\n\t\tbreak;\n\t}\n}\n\nvoid phydm_set_cck_pd_lv_type4(void *dm_void, enum cckpd_lv lv)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\tenum cckpd_mode cck_mode = CCK_BW20_2R;\n\tenum channel_width cck_bw = CHANNEL_WIDTH_20;\n\tu8 cck_n_rx = 0;\n\tu32 val = 0;\n\t/*u32 val_dbg = 0;*/\n\n\tPHYDM_DBG(dm, DBG_CCKPD, \"%s ======>\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_CCKPD, \"lv: (%d) -> (%d)\\n\", cckpd_t->cck_pd_lv, lv);\n\n\t/*[Check Nrx]*/\n\tcck_n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;\n\n\t/*[Check BW]*/\n\tval = odm_get_bb_reg(dm, R_0x9b0, 0xc);\n\tif (val == 0)\n\t\tcck_bw = CHANNEL_WIDTH_20;\n\telse if (val == 1)\n\t\tcck_bw = CHANNEL_WIDTH_40;\n\telse\n\t\tcck_bw = CHANNEL_WIDTH_80;\n\n\t/*[Check LV]*/\n\tif (cckpd_t->cck_pd_lv == lv &&\n\t    cckpd_t->cck_n_rx == cck_n_rx &&\n\t    cckpd_t->cck_bw == cck_bw) {\n\t\tPHYDM_DBG(dm, DBG_CCKPD, \"stay in lv=%d\\n\", lv);\n\t\treturn;\n\t}\n\n\tcckpd_t->cck_bw = cck_bw;\n\tcckpd_t->cck_n_rx = cck_n_rx;\n\tcckpd_t->cck_pd_lv = lv;\n\tcckpd_t->cck_fa_ma = CCK_FA_MA_RESET;\n\n\tswitch (cck_n_rx) {\n\tcase 1: /*1R*/\n\t{\n\t\tif (cck_bw == CHANNEL_WIDTH_20)\n\t\t\tcck_mode = CCK_BW20_1R;\n\t\telse if (cck_bw == CHANNEL_WIDTH_40)\n\t\t\tcck_mode = CCK_BW40_1R;\n\t} break;\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tcase 2: /*2R*/\n\t{\n\t\tif (cck_bw == CHANNEL_WIDTH_20)\n\t\t\tcck_mode = CCK_BW20_2R;\n\t\telse if (cck_bw == CHANNEL_WIDTH_40)\n\t\t\tcck_mode = CCK_BW40_2R;\n\t} break;\n\t#endif\n\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\tcase 3: /*3R*/\n\t{\n\t\tif (cck_bw == CHANNEL_WIDTH_20)\n\t\t\tcck_mode = CCK_BW20_3R;\n\t\telse if (cck_bw == CHANNEL_WIDTH_40)\n\t\t\tcck_mode = CCK_BW40_3R;\n\t} break;\n\t#endif\n\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\tcase 4: /*4R*/\n\t{\n\t\tif (cck_bw == CHANNEL_WIDTH_20)\n\t\t\tcck_mode = CCK_BW20_4R;\n\t\telse if (cck_bw == CHANNEL_WIDTH_40)\n\t\t\tcck_mode = CCK_BW40_4R;\n\t} break;\n\t#endif\n\tdefault:\n\t\t/*@pr_debug(\"[%s] warning!\\n\", __func__);*/\n\t\tbreak;\n\t}\nphydm_write_cck_pd_type4(dm, lv, cck_mode);\n}\n\nvoid phydm_read_cckpd_para_type4(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\tu8 bw = 0; /*r_RX_RF_BW*/\n\tu8 n_rx = 0;\n\tu8 curr_cck_pd_t[2][4][2];\n\tu32 reg0 = 0;\n\tu32 reg1 = 0;\n\tu32 reg2 = 0;\n\tu32 reg3 = 0;\n\n\tbw = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc);\n\tn_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;\n\n\treg0 = odm_get_bb_reg(dm, R_0x1ac8, MASKDWORD);\n\treg1 = odm_get_bb_reg(dm, R_0x1acc, MASKDWORD);\n\treg2 = odm_get_bb_reg(dm, R_0x1ad0, MASKDWORD);\n\treg3 = odm_get_bb_reg(dm, R_0x1ad4, MASKDWORD);\n\tcurr_cck_pd_t[0][0][0] = (u8)(reg0 & 0x000000ff);\n\tcurr_cck_pd_t[1][0][0] = (u8)(reg1 & 0x000000ff);\n\tcurr_cck_pd_t[0][0][1] = (u8)(reg2 & 0x0000001f);\n\tcurr_cck_pd_t[1][0][1] = (u8)((reg2 & 0x01f00000) >> 20);\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tif (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {\n\t\tcurr_cck_pd_t[0][1][0] = (u8)((reg0 & 0x0000ff00) >> 8);\n\t\tcurr_cck_pd_t[1][1][0] = (u8)((reg1 & 0x0000ff00) >> 8);\n\t\tcurr_cck_pd_t[0][1][1] = (u8)((reg2 & 0x000003E0) >> 5);\n\t\tcurr_cck_pd_t[1][1][1] = (u8)((reg2 & 0x3E000000) >> 25);\n\t}\n\t#endif\n\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\tif (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) {\n\t\tcurr_cck_pd_t[0][2][0] = (u8)((reg0 & 0x00ff0000) >> 16);\n\t\tcurr_cck_pd_t[1][2][0] = (u8)((reg1 & 0x00ff0000) >> 16);\n\t\tcurr_cck_pd_t[0][2][1] = (u8)((reg2 & 0x00007C00) >> 10);\n\t\tcurr_cck_pd_t[1][2][1] = (u8)((reg2 & 0xC0000000) >> 30) |\n\t\t\t\t\t (u8)((reg3 & 0x00000007) << 3);\n\t}\n\t#endif\n\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\tif (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {\n\t\tcurr_cck_pd_t[0][3][0] = (u8)((reg0 & 0xff000000) >> 24);\n\t\tcurr_cck_pd_t[1][3][0] = (u8)((reg1 & 0xff000000) >> 24);\n\t\tcurr_cck_pd_t[0][3][1] = (u8)((reg2 & 0x000F8000) >> 15);\n\t\tcurr_cck_pd_t[1][3][1] = (u8)((reg3 & 0x000000F8) >> 3);\n\t}\n\t#endif\n\n\tPHYDM_DBG(dm, DBG_CCKPD, \"bw=%dM, Nrx=%d\\n\", 20 << bw, n_rx);\n\tPHYDM_DBG(dm, DBG_CCKPD, \"lv=%d, readback CS_th=0x%x, PD th=0x%x\\n\",\n\t\t  cckpd_t->cck_pd_lv,\n\t\t  curr_cck_pd_t[bw][n_rx - 1][1],\n\t\t  curr_cck_pd_t[bw][n_rx - 1][0]);\n}\n\nvoid phydm_cckpd_type4(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\tu8 igi = dm->dm_dig_table.cur_ig_value;\n\tenum cckpd_lv lv = 0;\n\tboolean is_update = true;\n\n\tPHYDM_DBG(dm, DBG_CCKPD, \"%s ======>\\n\", __func__);\n\n\tif (dm->is_linked) {\n\t\tPHYDM_DBG(dm, DBG_CCKPD, \"Linked!!!\\n\");\n\t\tif (igi > 0x38 && dm->rssi_min > 32) {\n\t\t\tlv = CCK_PD_LV_4;\n\t\t\tPHYDM_DBG(dm, DBG_CCKPD, \"Order 1\\n\");\n\t\t} else if (igi > 0x2a && dm->rssi_min > 32) {\n\t\t\tlv = CCK_PD_LV_3;\n\t\t\tPHYDM_DBG(dm, DBG_CCKPD, \"Order 2\\n\");\n\t\t} else if (igi > 0x24 || dm->rssi_min > 24) {\n\t\t\tlv = CCK_PD_LV_2;\n\t\t\tPHYDM_DBG(dm, DBG_CCKPD, \"Order 3\\n\");\n\t\t} else {\n\t\t\tif (cckpd_t->cck_fa_ma > 1000) {\n\t\t\t\tlv = CCK_PD_LV_1;\n\t\t\t\tPHYDM_DBG(dm, DBG_CCKPD, \"Order 4-1\\n\");\n\t\t\t} else if (cckpd_t->cck_fa_ma < 500) {\n\t\t\t\tlv = CCK_PD_LV_0;\n\t\t\t\tPHYDM_DBG(dm, DBG_CCKPD, \"Order 4-2\\n\");\n\t\t\t} else {\n\t\t\t\tis_update = false;\n\t\t\t\tPHYDM_DBG(dm, DBG_CCKPD, \"Order 4-3\\n\");\n\t\t\t}\n\t\t}\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_CCKPD, \"UnLinked!!!\\n\");\n\t\tif (cckpd_t->cck_fa_ma > 1000) {\n\t\t\tlv = CCK_PD_LV_1;\n\t\t\tPHYDM_DBG(dm, DBG_CCKPD, \"Order 1\\n\");\n\t\t} else if (cckpd_t->cck_fa_ma < 500) {\n\t\t\tlv = CCK_PD_LV_0;\n\t\t\tPHYDM_DBG(dm, DBG_CCKPD, \"Order 2\\n\");\n\t\t} else {\n\t\t\tis_update = false;\n\t\t\tPHYDM_DBG(dm, DBG_CCKPD, \"Order 3\\n\");\n\t\t}\n\t}\n\n\tif (is_update) {\n\t\tphydm_set_cck_pd_lv_type4(dm, lv);\n\n\t\tPHYDM_DBG(dm, DBG_CCKPD, \"setting CS_th = 0x%x, PD th = 0x%x\\n\",\n\t\t\t  cckpd_t->cck_pd_table_jgr3[cckpd_t->cck_bw]\n\t\t\t  [cckpd_t->cck_n_rx - 1][1][lv],\n\t\t\t  cckpd_t->cck_pd_table_jgr3[cckpd_t->cck_bw]\n\t\t\t  [cckpd_t->cck_n_rx - 1][0][lv]);\n\t}\n\n\tphydm_read_cckpd_para_type4(dm);\n}\n\nvoid phydm_cck_pd_init_type4(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\tu32 reg0 = 0;\n\tu32 reg1 = 0;\n\tu32 reg2 = 0;\n\tu32 reg3 = 0;\n\tu8 pd_step = 0;\n\tu8 cck_bw = 0; /*r_RX_RF_BW*/\n\tu8 cck_n_rx = 0;\n\tu8 val = 0;\n\tu8 i = 0;\n\n\tPHYDM_DBG(dm, DBG_CCKPD, \"[%s]======>\\n\", __func__);\n\n\t#if 0\n\t/*@\n\t *cckpd_t[0][0][0][0] =  1ac8[7:0]\tr_PD_lim_RFBW20_1R\n\t *cckpd_t[0][1][0][0] =  1ac8[15:8]\tr_PD_lim_RFBW20_2R\n\t *cckpd_t[0][2][0][0] =  1ac8[23:16]\tr_PD_lim_RFBW20_3R\n\t *cckpd_t[0][3][0][0] =  1ac8[31:24]\tr_PD_lim_RFBW20_4R\n\t *cckpd_t[1][0][0][0] =  1acc[7:0]\tr_PD_lim_RFBW40_1R\n\t *cckpd_t[1][1][0][0] =  1acc[15:8]\tr_PD_lim_RFBW40_2R\n\t *cckpd_t[1][2][0][0] =  1acc[23:16]\tr_PD_lim_RFBW40_3R\n\t *cckpd_t[1][3][0][0] =  1acc[31:24]\tr_PD_lim_RFBW40_4R\n\t *\n\t *\n\t *cckpd_t[0][0][1][0] =  1ad0[4:0]\tr_CS_ratio_RFBW20_1R[4:0]\n\t *cckpd_t[0][1][1][0] =  1ad0[9:5]\tr_CS_ratio_RFBW20_2R[4:0]\n\t *cckpd_t[0][2][1][0] =  1ad0[14:10]\tr_CS_ratio_RFBW20_3R[4:0]\n\t *cckpd_t[0][3][1][0] =  1ad0[19:15]\tr_CS_ratio_RFBW20_4R[4:0]\n\t *cckpd_t[1][0][1][0] =  1ad0[24:20]\tr_CS_ratio_RFBW40_1R[4:0]\n\t *cckpd_t[1][1][1][0] =  1ad0[29:25]\tr_CS_ratio_RFBW40_2R[4:0]\n\t *cckpd_t[1][2][1][0] =  1ad0[31:30]\tr_CS_ratio_RFBW40_3R[1:0]\n\t *\t\t\t  1ad4[2:0]\tr_CS_ratio_RFBW40_3R[4:2]\n\t *cckpd_t[1][3][1][0] =  1ad4[7:3]\tr_CS_ratio_RFBW40_4R[4:0]\n\t */\n\t#endif\n\t/*[Check Nrx]*/\n\tcck_n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;\n\n\t/*[Check BW]*/\n\tval = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc);\n\tif (val == 0)\n\t\tcck_bw = CHANNEL_WIDTH_20;\n\telse if (val == 1)\n\t\tcck_bw = CHANNEL_WIDTH_40;\n\telse\n\t\tcck_bw = CHANNEL_WIDTH_80;\n\n\tcckpd_t->cck_bw = cck_bw;\n\tcckpd_t->cck_n_rx = cck_n_rx;\n\treg0 = odm_get_bb_reg(dm, R_0x1ac8, MASKDWORD);\n\treg1 = odm_get_bb_reg(dm, R_0x1acc, MASKDWORD);\n\treg2 = odm_get_bb_reg(dm, R_0x1ad0, MASKDWORD);\n\treg3 = odm_get_bb_reg(dm, R_0x1ad4, MASKDWORD);\n\n\tfor (i = 0 ; i < CCK_PD_LV_MAX ; i++) {\n\t\tpd_step = i * 2;\n\n\t\tval = (u8)(reg0 & 0x000000ff) + pd_step;\n\t\tPHYDM_DBG(dm, DBG_CCKPD, \"lvl %d val = %x\\n\\n\", i, val);\n\t\tcckpd_t->cck_pd_table_jgr3[0][0][0][i] = val;\n\n\t\tval = (u8)(reg1 & 0x000000ff) + pd_step;\n\t\tcckpd_t->cck_pd_table_jgr3[1][0][0][i] = val;\n\n\t\tval = (u8)(reg2 & 0x0000001F) + pd_step;\n\t\tcckpd_t->cck_pd_table_jgr3[0][0][1][i] = val;\n\n\t\tval = (u8)((reg2 & 0x01F00000) >> 20) + pd_step;\n\t\tcckpd_t->cck_pd_table_jgr3[1][0][1][i] = val;\n\n\t\t#ifdef PHYDM_COMPILE_ABOVE_2SS\n\t\tif (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {\n\t\t\tval = (u8)((reg0 & 0x0000ff00) >> 8) + pd_step;\n\t\t\tcckpd_t->cck_pd_table_jgr3[0][1][0][i] = val;\n\n\t\t\tval = (u8)((reg1 & 0x0000ff00) >> 8) + pd_step;\n\t\t\tcckpd_t->cck_pd_table_jgr3[1][1][0][i] = val;\n\n\t\t\tval = (u8)((reg2 & 0x000003E0) >> 5) + pd_step;\n\t\t\tcckpd_t->cck_pd_table_jgr3[0][1][1][i] = val;\n\n\t\t\tval = (u8)((reg2 & 0x3E000000) >> 25) + pd_step;\n\t\t\tcckpd_t->cck_pd_table_jgr3[1][1][1][i] = val;\n\t\t}\n\t\t#endif\n\n\t\t#ifdef PHYDM_COMPILE_ABOVE_3SS\n\t\tif (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) {\n\t\t\tval = (u8)((reg0 & 0x00ff0000) >> 16) + pd_step;\n\t\t\tcckpd_t->cck_pd_table_jgr3[0][2][0][i] = val;\n\n\t\t\tval = (u8)((reg1 & 0x00ff0000) >> 16) + pd_step;\n\t\t\tcckpd_t->cck_pd_table_jgr3[1][2][0][i] = val;\n\t\t\tval = (u8)((reg2 & 0x00007C00) >> 10) + pd_step;\n\t\t\tcckpd_t->cck_pd_table_jgr3[0][2][1][i] = val;\n\t\t\tval = (u8)(((reg2 & 0xC0000000) >> 30) |\n\t\t\t      ((reg3 & 0x7) << 3)) + pd_step;\n\t\t\tcckpd_t->cck_pd_table_jgr3[1][2][1][i] = val;\n\t\t}\n\t\t#endif\n\n\t\t#ifdef PHYDM_COMPILE_ABOVE_4SS\n\t\tif (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {\n\t\t\tval = (u8)((reg0 & 0xff000000) >> 24) + pd_step;\n\t\t\tcckpd_t->cck_pd_table_jgr3[0][3][0][i] = val;\n\n\t\t\tval = (u8)((reg1 & 0xff000000) >> 24) + pd_step;\n\t\t\tcckpd_t->cck_pd_table_jgr3[1][3][0][i] = val;\n\n\t\t\tval = (u8)((reg2 & 0x000F8000) >> 15) + pd_step;\n\t\t\tcckpd_t->cck_pd_table_jgr3[0][3][1][i] = val;\n\n\t\t\tval = (u8)((reg3 & 0x000000F8) >> 3) + pd_step;\n\t\t\tcckpd_t->cck_pd_table_jgr3[1][3][1][i] = val;\n\t\t}\n\t\t#endif\n\t}\n}\n#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE4*/\n\nvoid phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\tenum cckpd_lv lv;\n\n\tif (val_len != 1) {\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[Error][CCKPD]Need val_len=1\\n\");\n\t\treturn;\n\t}\n\n\tlv = (enum cckpd_lv)val_buf[0];\n\n\tif (lv > CCK_PD_LV_4) {\n\t\tpr_debug(\"[%s] warning! lv=%d\\n\", __func__, lv);\n\t\treturn;\n\t}\n\n\tswitch (cckpd_t->cckpd_hw_type) {\n\t#ifdef PHYDM_COMPILE_CCKPD_TYPE1\n\tcase 1:\n\t\tphydm_set_cckpd_lv_type1(dm, lv);\n\t\tbreak;\n\t#endif\n\t#ifdef PHYDM_COMPILE_CCKPD_TYPE2\n\tcase 2:\n\t\tphydm_set_cckpd_lv_type2(dm, lv);\n\t\tbreak;\n\t#endif\n\t#ifdef PHYDM_COMPILE_CCKPD_TYPE3\n\tcase 3:\n\t\tphydm_set_cckpd_lv_type3(dm, lv);\n\t\tbreak;\n\t#endif\n\t#ifdef PHYDM_COMPILE_CCKPD_TYPE4\n\tcase 4:\n\t\tphydm_set_cck_pd_lv_type4(dm, lv);\n\t\tbreak;\n\t#endif\n\tdefault:\n\t\tpr_debug(\"[%s]warning\\n\", __func__);\n\t\tbreak;\n\t}\n}\n\nboolean\nphydm_stop_cck_pd_th(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (!(dm->support_ability & (ODM_BB_CCK_PD | ODM_BB_FA_CNT))) {\n\t\tPHYDM_DBG(dm, DBG_CCKPD, \"Not Support\\n\");\n\t\treturn true;\n\t}\n\n\tif (dm->pause_ability & ODM_BB_CCK_PD) {\n\t\tPHYDM_DBG(dm, DBG_CCKPD, \"Return: Pause CCKPD in LV=%d\\n\",\n\t\t\t  dm->pause_lv_table.lv_cckpd);\n\t\treturn true;\n\t}\n\n\tif (dm->is_linked && (*dm->channel > 36)) {\n\t\tPHYDM_DBG(dm, DBG_CCKPD, \"Return: 5G CH=%d\\n\", *dm->channel);\n\t\treturn true;\n\t}\n\treturn false;\n}\n\nvoid phydm_cck_pd_th(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fa_struct *fa_t = &dm->false_alm_cnt;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\tu32 cck_fa = fa_t->cnt_cck_fail;\n\t#ifdef PHYDM_TDMA_DIG_SUPPORT\n\tstruct phydm_fa_acc_struct *fa_acc_t = &dm->false_alm_cnt_acc;\n\t#endif\n\n\tPHYDM_DBG(dm, DBG_CCKPD, \"[%s] ======>\\n\", __func__);\n\n\tif (phydm_stop_cck_pd_th(dm))\n\t\treturn;\n\n\t#ifdef PHYDM_TDMA_DIG_SUPPORT\n\tif (dm->original_dig_restore)\n\t\tcck_fa = fa_t->cnt_cck_fail;\n\telse\n\t\tcck_fa = fa_acc_t->cnt_cck_fail_1sec;\n\t#endif\n\n\tif (cckpd_t->cck_fa_ma == CCK_FA_MA_RESET)\n\t\tcckpd_t->cck_fa_ma = cck_fa;\n\telse\n\t\tcckpd_t->cck_fa_ma = (cckpd_t->cck_fa_ma * 3 + cck_fa) >> 2;\n\n\tPHYDM_DBG(dm, DBG_CCKPD,\n\t\t  \"IGI=0x%x, rssi_min=%d, cck_fa=%d, cck_fa_ma=%d\\n\",\n\t\t  dm->dm_dig_table.cur_ig_value, dm->rssi_min,\n\t\t  cck_fa, cckpd_t->cck_fa_ma);\n\n\tswitch (cckpd_t->cckpd_hw_type) {\n\t#ifdef PHYDM_COMPILE_CCKPD_TYPE1\n\tcase 1:\n\t\tphydm_cckpd_type1(dm);\n\t\tbreak;\n\t#endif\n\t#ifdef PHYDM_COMPILE_CCKPD_TYPE2\n\tcase 2:\n\t\tphydm_cckpd_type2(dm);\n\t\tbreak;\n\t#endif\n\t#ifdef PHYDM_COMPILE_CCKPD_TYPE3\n\tcase 3:\n\t\tphydm_cckpd_type3(dm);\n\t\tbreak;\n\t#endif\n\t#ifdef PHYDM_COMPILE_CCKPD_TYPE4\n\tcase 4:\n\t\tphydm_cckpd_type4(dm);\n\t\tbreak;\n\t#endif\n\tdefault:\n\t\tpr_debug(\"[%s]warning\\n\", __func__);\n\t\tbreak;\n\t}\n}\n\nvoid phydm_cck_pd_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;\n\n\tif (*dm->mp_mode)\n\t\treturn;\n\n\tif (dm->support_ic_type & CCK_PD_IC_TYPE1)\n\t\tcckpd_t->cckpd_hw_type = 1;\n\telse if (dm->support_ic_type & CCK_PD_IC_TYPE2)\n\t\tcckpd_t->cckpd_hw_type = 2;\n\telse if (dm->support_ic_type & CCK_PD_IC_TYPE3)\n\t\tcckpd_t->cckpd_hw_type = 3;\n\telse if (dm->support_ic_type & CCK_PD_IC_TYPE4)\n\t\tcckpd_t->cckpd_hw_type = 4;\n\n\tPHYDM_DBG(dm, DBG_CCKPD, \"[%s] cckpd_hw_type=%d\\n\",\n\t\t  __func__, cckpd_t->cckpd_hw_type);\n\n\tcckpd_t->cck_pd_lv = CCK_PD_LV_INIT;\n\tcckpd_t->cck_n_rx = 0xff;\n\tcckpd_t->cck_bw = CHANNEL_WIDTH_MAX;\n\n\tswitch (cckpd_t->cckpd_hw_type) {\n\t#ifdef PHYDM_COMPILE_CCKPD_TYPE1\n\tcase 1:\n\t\tphydm_set_cckpd_lv_type1(dm, CCK_PD_LV_0);\n\t\tbreak;\n\t#endif\n\t#ifdef PHYDM_COMPILE_CCKPD_TYPE2\n\tcase 2:\n\t\tcckpd_t->aaa_default = odm_read_1byte(dm, 0xaaa) & 0x1f;\n\t\tphydm_set_cckpd_lv_type2(dm, CCK_PD_LV_0);\n\t\tbreak;\n\t#endif\n\t#ifdef PHYDM_COMPILE_CCKPD_TYPE3\n\tcase 3:\n\t\tphydm_cck_pd_init_type3(dm);\n\t\tbreak;\n\t#endif\n\t#ifdef PHYDM_COMPILE_CCKPD_TYPE4\n\tcase 4:\n\t\tphydm_cck_pd_init_type4(dm);\n\t\tbreak;\n\t#endif\n\tdefault:\n\t\tpr_debug(\"[%s]warning\\n\", __func__);\n\t\tbreak;\n\t}\n}\n#endif /*#ifdef PHYDM_SUPPORT_CCKPD*/\n\n"
  },
  {
    "path": "hal/phydm/phydm_cck_pd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDM_CCK_PD_H__\n#define __PHYDM_CCK_PD_H__\n\n#define CCK_PD_VERSION \"3.1\"\n\n/*@\n * 1 ============================================================\n * 1  Definition\n * 1 ============================================================\n */\n#define CCK_FA_MA_RESET 0xffffffff\n\n/*@Run time flag of CCK_PD HW type*/\n#define CCK_PD_IC_TYPE1 (ODM_RTL8188E | ODM_RTL8812 | ODM_RTL8821 |\\\n\t\t\tODM_RTL8192E | ODM_RTL8723B | ODM_RTL8814A |\\\n\t\t\tODM_RTL8881A | ODM_RTL8822B | ODM_RTL8703B |\\\n\t\t\tODM_RTL8195A | ODM_RTL8188F)\n\n#define CCK_PD_IC_TYPE2 (ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8723D |\\\n\t\t\tODM_RTL8710B | ODM_RTL8195B) /*extend 0xaaa*/\n\n#define CCK_PD_IC_TYPE3 (ODM_RTL8192F | ODM_RTL8721D)\n/*@extend for different bw & path*/\n\n#define CCK_PD_IC_TYPE4 ODM_IC_JGR3_SERIES /*@extend for different bw & path*/\n\n/*@Compile time flag of CCK_PD HW type*/\n#if (RTL8188E_SUPPORT || RTL8812A_SUPPORT || RTL8821A_SUPPORT ||\\\n\tRTL8192E_SUPPORT || RTL8723B_SUPPORT || RTL8814A_SUPPORT ||\\\n\tRTL8881A_SUPPORT || RTL8822B_SUPPORT || RTL8703B_SUPPORT ||\\\n\tRTL8195A_SUPPORT || RTL8188F_SUPPORT)\n\t#define PHYDM_COMPILE_CCKPD_TYPE1 /*@only 0xa0a*/\n#endif\n\n#if (RTL8197F_SUPPORT || RTL8821C_SUPPORT || RTL8723D_SUPPORT ||\\\n\tRTL8710B_SUPPORT || RTL8195B_SUPPORT)\n\t#define PHYDM_COMPILE_CCKPD_TYPE2 /*@extend 0xaaa*/\n#endif\n\n#if (RTL8192F_SUPPORT || RTL8721D_SUPPORT)\n\t#define PHYDM_COMPILE_CCKPD_TYPE3 /*@extend for different & path*/\n#endif\n\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t#define PHYDM_COMPILE_CCKPD_TYPE4 /*@extend for different bw & path*/\n#endif\n/*@\n * 1 ============================================================\n * 1  enumeration\n * 1 ============================================================\n */\nenum cckpd_lv {\n\tCCK_PD_LV_INIT = 0xff,\n\tCCK_PD_LV_0 = 0,\n\tCCK_PD_LV_1 = 1,\n\tCCK_PD_LV_2 = 2,\n\tCCK_PD_LV_3 = 3,\n\tCCK_PD_LV_4 = 4,\n\tCCK_PD_LV_MAX = 5\n};\n\nenum cckpd_mode {\n\tCCK_BW20_1R = 0,\n\tCCK_BW20_2R = 1,\n\tCCK_BW20_3R = 2,\n\tCCK_BW20_4R = 3,\n\tCCK_BW40_1R = 4,\n\tCCK_BW40_2R = 5,\n\tCCK_BW40_3R = 6,\n\tCCK_BW40_4R = 7\n};\n\n/*@\n * 1 ============================================================\n * 1  structure\n * 1 ============================================================\n */\n\n#ifdef PHYDM_SUPPORT_CCKPD\nstruct phydm_cckpd_struct {\n\tu8\t\tcckpd_hw_type;\n\tu8\t\tcur_cck_cca_thres; /*@current cck_pd value 0xa0a*/\n\tu32\t\tcck_fa_ma;\n\tu8\t\trvrt_val;\n\tu8\t\tpause_lv;\n\tu8\t\tcck_n_rx;\n\tenum channel_width cck_bw;\n\tenum cckpd_lv\tcck_pd_lv;\n\t#ifdef PHYDM_COMPILE_CCKPD_TYPE2\n\tu8\t\tcck_cca_th_aaa; /*@current cs_ratio value 0xaaa*/\n\tu8\t\taaa_default;\t/*@Init cs_ratio value - 0xaaa*/\n\t#endif\n\t#ifdef PHYDM_COMPILE_CCKPD_TYPE3\n\t/*Default value*/\n\tu8\t\tcck_pd_20m_1r;\n\tu8\t\tcck_pd_20m_2r;\n\tu8\t\tcck_pd_40m_1r;\n\tu8\t\tcck_pd_40m_2r;\n\tu8\t\tcck_cs_ratio_20m_1r;\n\tu8\t\tcck_cs_ratio_20m_2r;\n\tu8\t\tcck_cs_ratio_40m_1r;\n\tu8\t\tcck_cs_ratio_40m_2r;\n\t/*Current value*/\n\tu8\t\tcur_cck_pd_20m_1r;\n\tu8\t\tcur_cck_pd_20m_2r;\n\tu8\t\tcur_cck_pd_40m_1r;\n\tu8\t\tcur_cck_pd_40m_2r;\n\tu8\t\tcur_cck_cs_ratio_20m_1r;\n\tu8\t\tcur_cck_cs_ratio_20m_2r;\n\tu8\t\tcur_cck_cs_ratio_40m_1r;\n\tu8\t\tcur_cck_cs_ratio_40m_2r;\n\t#endif\n\t#ifdef PHYDM_COMPILE_CCKPD_TYPE4\n\t/*@[bw][nrx][0:PD/1:CS][lv]*/\n\tu8\t\tcck_pd_table_jgr3[2][4][2][CCK_PD_LV_MAX];\n\t#endif\n};\n#endif\n\n/*@\n * 1 ============================================================\n * 1  function prototype\n * 1 ============================================================\n */\nvoid phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len);\n\nvoid phydm_cck_pd_th(void *dm_void);\n\nvoid phydm_cck_pd_init(void *dm_void);\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_ccx.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\nvoid phydm_ccx_hw_restart(void *dm_void)\n\t\t\t  /*@Will Restart NHM/CLM/FAHM simultaneously*/\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 reg1 = 0;\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES)\n\t\treg1 = R_0x994;\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\telse if (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\treg1 = R_0x1e60;\n\t#endif\n\telse\n\t\treg1 = R_0x890;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\t/*@disable NHM,CLM, FAHM*/\n\todm_set_bb_reg(dm, reg1, 0x7, 0x0);\n\todm_set_bb_reg(dm, reg1, BIT(8), 0x0);\n\todm_set_bb_reg(dm, reg1, BIT(8), 0x1);\n}\n\n#ifdef FAHM_SUPPORT\n\nu16 phydm_hw_divider(void *dm_void, u16 numerator, u16 denumerator)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu16 result = DEVIDER_ERROR;\n\tu32 tmp_u32 = ((numerator << 16) | denumerator);\n\tu32 reg_devider_input;\n\tu32 reg;\n\tu8 i;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\treg_devider_input = 0x1cbc;\n\t\treg = 0x1f98;\n\t} else {\n\t\treg_devider_input = 0x980;\n\t\treg = 0x9f0;\n\t}\n\n\todm_set_bb_reg(dm, reg_devider_input, MASKDWORD, tmp_u32);\n\n\tfor (i = 0; i < 10; i++) {\n\t\tODM_delay_ms(1);\n\t\tif (odm_get_bb_reg(dm, reg, BIT(24))) {\n\t\t/*@Chk HW rpt is ready*/\n\n\t\t\tresult = (u16)odm_get_bb_reg(dm, reg, MASKBYTE2);\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn result;\n}\n\nvoid phydm_fahm_trigger(void *dm_void, u16 tgr_period)\n{ /*@unit (4us)*/\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 fahm_reg1;\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\todm_set_bb_reg(dm, R_0x1cf8, 0xffff00, tgr_period);\n\n\t\tfahm_reg1 = 0x994;\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x978, 0xff000000, (tgr_period & 0xff));\n\t\todm_set_bb_reg(dm, R_0x97c, 0xff, (tgr_period & 0xff00) >> 8);\n\n\t\tfahm_reg1 = 0x890;\n\t}\n\n\todm_set_bb_reg(dm, fahm_reg1, BIT(2), 0);\n\todm_set_bb_reg(dm, fahm_reg1, BIT(2), 1);\n}\n\nvoid phydm_fahm_set_valid_cnt(void *dm_void, u8 numerator_sel,\n\t\t\t      u8 denominator_sel)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx_info = &dm->dm_ccx_info;\n\tu32 fahm_reg1;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\n\tif (ccx_info->fahm_nume_sel == numerator_sel &&\n\t    ccx_info->fahm_denom_sel == denominator_sel) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"no need to update\\n\");\n\t\treturn;\n\t}\n\n\tccx_info->fahm_nume_sel = numerator_sel;\n\tccx_info->fahm_denom_sel = denominator_sel;\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES)\n\t\tfahm_reg1 = 0x994;\n\telse\n\t\tfahm_reg1 = 0x890;\n\n\todm_set_bb_reg(dm, fahm_reg1, 0xe0, numerator_sel);\n\todm_set_bb_reg(dm, fahm_reg1, 0x7000, denominator_sel);\n}\n\nvoid phydm_fahm_get_result(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu16 fahm_cnt[12]; /*packet count*/\n\tu16 fahm_rpt[12]; /*percentage*/\n\tu16 denominator; /*@fahm_denominator packet count*/\n\tu32 reg_rpt, reg_rpt_2;\n\tu32 reg_tmp;\n\tboolean is_ready = false;\n\tu8 i;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\treg_rpt = 0x1f80;\n\t\treg_rpt_2 = 0x1f98;\n\t} else {\n\t\treg_rpt = 0x9d8;\n\t\treg_rpt_2 = 0x9f0;\n\t}\n\n\tfor (i = 0; i < 3; i++) {\n\t\tif (odm_get_bb_reg(dm, reg_rpt_2, BIT(31))) {\n\t\t/*@Chk HW rpt is ready*/\n\t\t\tis_ready = true;\n\t\t\tbreak;\n\t\t}\n\t\tODM_delay_ms(1);\n\t}\n\n\tif (!is_ready)\n\t\treturn;\n\n\t/*@Get FAHM Denominator*/\n\tdenominator = (u16)odm_get_bb_reg(dm, reg_rpt_2, MASKLWORD);\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"Reg[0x%x] fahm_denmrtr = %d\\n\", reg_rpt_2,\n\t\t  denominator);\n\n\t/*@Get FAHM nemerator*/\n\tfor (i = 0; i < 6; i++) {\n\t\treg_tmp = odm_get_bb_reg(dm, reg_rpt + (i << 2), MASKDWORD);\n\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"Reg[0x%x] fahm_denmrtr = %d\\n\",\n\t\t\t  reg_rpt + (i * 4), reg_tmp);\n\n\t\tfahm_cnt[i * 2] = (u16)(reg_tmp & MASKLWORD);\n\t\tfahm_cnt[i * 2 + 1] = (u16)((reg_tmp & MASKHWORD) >> 16);\n\t}\n\n\tfor (i = 0; i < 12; i++)\n\t\tfahm_rpt[i] = phydm_hw_divider(dm, fahm_cnt[i], denominator);\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t  \"FAHM_RPT_cnt[10:0]=[%d, %d, %d, %d, %d(IGI), %d, %d, %d, %d, %d, %d, %d]\\n\",\n\t\t  fahm_cnt[11], fahm_cnt[10], fahm_cnt[9],\n\t\t  fahm_cnt[8], fahm_cnt[7], fahm_cnt[6],\n\t\t  fahm_cnt[5], fahm_cnt[4], fahm_cnt[3],\n\t\t  fahm_cnt[2], fahm_cnt[1], fahm_cnt[0]);\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t  \"FAHM_RPT[10:0]=[%d, %d, %d, %d, %d(IGI), %d, %d, %d, %d, %d, %d, %d]\\n\",\n\t\t  fahm_rpt[11], fahm_rpt[10], fahm_rpt[9], fahm_rpt[8],\n\t\t  fahm_rpt[7], fahm_rpt[6], fahm_rpt[5], fahm_rpt[4],\n\t\t  fahm_rpt[3], fahm_rpt[2], fahm_rpt[1], fahm_rpt[0]);\n}\n\nvoid phydm_fahm_set_th_by_igi(void *dm_void, u8 igi)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx_info = &dm->dm_ccx_info;\n\tu32 val = 0;\n\tu8 f_th[11]; /*@FAHM Threshold*/\n\tu8 rssi_th[11]; /*@in RSSI scale*/\n\tu8 th_gap = 2 * IGI_TO_NHM_TH_MULTIPLIER; /*unit is 0.5dB for FAHM*/\n\tu8 i;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\n\tif (ccx_info->env_mntr_igi == igi) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t\t  \"No need to update FAHM_th, IGI=0x%x\\n\",\n\t\t\t  ccx_info->env_mntr_igi);\n\t\treturn;\n\t}\n\n\tccx_info->env_mntr_igi = igi; /*@bkp IGI*/\n\n\tif (igi >= CCA_CAP)\n\t\tf_th[0] = (igi - CCA_CAP) * IGI_TO_NHM_TH_MULTIPLIER;\n\telse\n\t\tf_th[0] = 0;\n\n\trssi_th[0] = igi - 10 - CCA_CAP;\n\n\tfor (i = 1; i <= 10; i++) {\n\t\tf_th[i] = f_th[0] + th_gap * i;\n\t\trssi_th[i] = rssi_th[0] + (i << 1);\n\t}\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t  \"FAHM_RSSI_th[10:0]=[%d, %d, %d, (IGI)%d, %d, %d, %d, %d, %d, %d, %d]\\n\",\n\t\t  rssi_th[10], rssi_th[9], rssi_th[8], rssi_th[7], rssi_th[6],\n\t\t  rssi_th[5], rssi_th[4], rssi_th[3], rssi_th[2], rssi_th[1],\n\t\t  rssi_th[0]);\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\tval = BYTE_2_DWORD(0, f_th[2], f_th[1], f_th[0]);\n\t\todm_set_bb_reg(dm, R_0x1c38, 0xffffff00, val);\n\t\tval = BYTE_2_DWORD(0, f_th[5], f_th[4], f_th[3]);\n\t\todm_set_bb_reg(dm, R_0x1c78, 0xffffff00, val);\n\t\tval = BYTE_2_DWORD(0, 0, f_th[7], f_th[6]);\n\t\todm_set_bb_reg(dm, R_0x1c7c, 0xffff0000, val);\n\t\tval = BYTE_2_DWORD(0, f_th[10], f_th[9], f_th[8]);\n\t\todm_set_bb_reg(dm, R_0x1cb8, 0xffffff00, val);\n\t} else {\n\t\tval = BYTE_2_DWORD(f_th[3], f_th[2], f_th[1], f_th[0]);\n\t\todm_set_bb_reg(dm, R_0x970, MASKDWORD, val);\n\t\tval = BYTE_2_DWORD(f_th[7], f_th[6], f_th[5], f_th[4]);\n\t\todm_set_bb_reg(dm, R_0x974, MASKDWORD, val);\n\t\tval = BYTE_2_DWORD(0, f_th[10], f_th[9], f_th[8]);\n\t\todm_set_bb_reg(dm, R_0x978, 0xffffff, val);\n\t}\n}\n\nvoid phydm_fahm_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx_info = &dm->dm_ccx_info;\n\tu32 fahm_reg1;\n\tu8 denumerator_sel = 0;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"IGI=0x%x\\n\",\n\t\t  dm->dm_dig_table.cur_ig_value);\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES)\n\t\tfahm_reg1 = 0x994;\n\telse\n\t\tfahm_reg1 = 0x890;\n\n\tccx_info->fahm_period = 65535;\n\n\todm_set_bb_reg(dm, fahm_reg1, 0x6, 3); /*@FAHM HW block enable*/\n\n\tdenumerator_sel = FAHM_INCLD_FA | FAHM_INCLD_CRC_OK | FAHM_INCLD_CRC_ER;\n\tphydm_fahm_set_valid_cnt(dm, FAHM_INCLD_FA, denumerator_sel);\n\tphydm_fahm_set_th_by_igi(dm, dm->dm_dig_table.cur_ig_value);\n}\n\nvoid phydm_fahm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t    u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx_info = &dm->dm_ccx_info;\n\tchar help[] = \"-h\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 i;\n\n\tfor (i = 0; i < 2; i++) {\n\t\tif (input[i + 1])\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);\n\t}\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{1: trigger, 2:get result}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{3: MNTR mode sel} {1: driver, 2. FW}\\n\");\n\t\treturn;\n\t} else if (var1[0] == 1) { /* Set & trigger CLM */\n\n\t\tphydm_fahm_set_th_by_igi(dm, dm->dm_dig_table.cur_ig_value);\n\t\tphydm_fahm_trigger(dm, ccx_info->fahm_period);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Monitor FAHM for %d * 4us\\n\", ccx_info->fahm_period);\n\n\t} else if (var1[0] == 2) { /* @Get CLM results */\n\n\t\tphydm_fahm_get_result(dm);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"FAHM_result=%d us\\n\", (ccx_info->clm_result << 2));\n\n\t} else {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Error\\n\");\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\n#endif /*@#ifdef FAHM_SUPPORT*/\n\n#ifdef NHM_SUPPORT\n\nvoid phydm_nhm_racing_release(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu32 value32 = 0;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"lv:(%d)->(0)\\n\", ccx->nhm_set_lv);\n\n\tccx->nhm_ongoing = false;\n\tccx->nhm_set_lv = NHM_RELEASE;\n\n\tif (!(ccx->nhm_app == NHM_BACKGROUND || ccx->nhm_app == NHM_ACS)) {\n\t\tphydm_pause_func(dm, F00_DIG, PHYDM_RESUME,\n\t\t\t\t PHYDM_PAUSE_LEVEL_1, 1, &value32);\n\t}\n\n\tccx->nhm_app = NHM_BACKGROUND;\n}\n\nu8 phydm_nhm_racing_ctrl(void *dm_void, enum phydm_nhm_level nhm_lv)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu8 set_result = PHYDM_SET_SUCCESS;\n\t/*@acquire to control NHM API*/\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"nhm_ongoing=%d, lv:(%d)->(%d)\\n\",\n\t\t  ccx->nhm_ongoing, ccx->nhm_set_lv, nhm_lv);\n\tif (ccx->nhm_ongoing) {\n\t\tif (nhm_lv <= ccx->nhm_set_lv) {\n\t\t\tset_result = PHYDM_SET_FAIL;\n\t\t} else {\n\t\t\tphydm_ccx_hw_restart(dm);\n\t\t\tccx->nhm_ongoing = false;\n\t\t}\n\t}\n\n\tif (set_result)\n\t\tccx->nhm_set_lv = nhm_lv;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"nhm racing success=%d\\n\", set_result);\n\treturn set_result;\n}\n\nvoid phydm_nhm_trigger(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu32 nhm_reg1 = 0;\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES)\n\t\tnhm_reg1 = R_0x994;\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\telse if (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tnhm_reg1 = R_0x1e60;\n\t#endif\n\telse\n\t\tnhm_reg1 = R_0x890;\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\n\t/* @Trigger NHM*/\n\tpdm_set_reg(dm, nhm_reg1, BIT(1), 0);\n\tpdm_set_reg(dm, nhm_reg1, BIT(1), 1);\n\tccx->nhm_trigger_time = dm->phydm_sys_up_time;\n\tccx->nhm_rpt_stamp++;\n\tccx->nhm_ongoing = true;\n}\n\nboolean\nphydm_nhm_check_rdy(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tboolean is_ready = false;\n\tu32 reg1 = 0, reg1_bit = 0;\n#if (ENV_MNTR_DBG || ENV_MNTR_DBG_1)\n\tu16 i = 0;\n\tu64 start_time = 0, progressing_time = 0;\n\tu32 reg_val_start = 0, reg_val = 0;\n\tu8 print_rpt = 0;\n#endif\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\treg1 = R_0xfb4;\n\t\treg1_bit = 16;\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\treg1 = R_0x2d4c;\n\t\treg1_bit = 16;\n\t#endif\n\t} else {\n\t\treg1 = R_0x8b4;\n\t\tif (dm->support_ic_type & (ODM_RTL8710B | ODM_RTL8721D)) {\n\t\t\treg1_bit = 25;\n\t\t} else {\n\t\t\treg1_bit = 17;\n\t\t}\n\t}\n\n#if (ENV_MNTR_DBG_1)\n\tstart_time = odm_get_current_time(dm);\n\n\tif (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"NHM_period = %d\\n\",\n\t\t\t  odm_get_bb_reg(dm, R_0x990, MASKDWORD));\n\n\t\t /*NHM trigger bit*/\n\t\treg_val_start = odm_get_bb_reg(dm, R_0x994, BIT(1));\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"reg_val_start = %d\\n\",\n\t\t\t  reg_val_start);\n\n\t\tfor (i = 0; i <= 400; i++) {\n\t\t\tif (print_rpt == 0) {\n\t\t\t\treg_val = odm_get_bb_reg(dm, R_0x994, BIT(1));\n\t\t\t\tif (reg_val != reg_val_start) {\n\t\t\t\t\tprint_rpt = 1;\n\t\t\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t\t\t\t\t  \"Trig[%d] (%d) -> (%d)\\n\",\n\t\t\t\t\t\t  i, reg_val_start, reg_val);\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) {\n\t\t\t\tis_ready = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tODM_delay_ms(1);\n\t\t}\n\t} else {\n\t\tif (odm_get_bb_reg(dm, reg1, BIT(reg1_bit)))\n\t\t\tis_ready = true;\n\t}\n\n\tprogressing_time = odm_get_progressing_time(dm, start_time);\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"NHM rdy=%d, i=%d, NHM_polling_time=%lld\\n\",\n\t\t  is_ready, i, progressing_time);\n\n#elif (ENV_MNTR_DBG)\n\tstart_time = odm_get_current_time(dm);\n\tfor (i = 0; i <= 400; i++) {\n\t\tif (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) {\n\t\t\tis_ready = true;\n\t\t\tbreak;\n\t\t}\n\t\tODM_delay_ms(1);\n\t}\n\tprogressing_time = odm_get_progressing_time(dm, start_time);\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"NHM rdy=%d, i=%d, NHM_polling_time=%lld\\n\",\n\t\t  is_ready, i, progressing_time);\n#else\n\tif (odm_get_bb_reg(dm, reg1, BIT(reg1_bit)))\n\t\tis_ready = true;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"NHM rdy=%d\\n\", is_ready);\n\n#endif\n\treturn is_ready;\n}\n\nvoid phydm_nhm_get_utility(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu8 nhm_rpt_non_0 = 0;\n\n\tif (ccx->nhm_rpt_sum >= ccx->nhm_result[0]) {\n\t\tnhm_rpt_non_0 = ccx->nhm_rpt_sum - ccx->nhm_result[0];\n\t\tccx->nhm_ratio = (nhm_rpt_non_0 * 100) >> 8;\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[warning] nhm_rpt_sum invalid\\n\");\n\t\tccx->nhm_ratio = 0;\n\t}\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"nhm_ratio=%d\\n\", ccx->nhm_ratio);\n}\n\nboolean\nphydm_nhm_get_result(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu32 value32 = 0;\n\tu8 i = 0;\n\tu32 nhm_reg1 = 0;\n\tu16 nhm_rpt_sum_tmp = 0;\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES)\n\t\tnhm_reg1 = R_0x994;\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\telse if (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tnhm_reg1 = R_0x1e60;\n\t#endif\n\telse\n\t\tnhm_reg1 = R_0x890;\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\n\tif (!(dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |\n\t\t\t\t     ODM_RTL8197G)))\n\t\tpdm_set_reg(dm, nhm_reg1, BIT(1), 0);\n\n#if (ENV_MNTR_DBG_2)\n\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t  \"[DBG][3] 0xc50=0x%x, 0x994=0x%x, 0x998=0x%x\\n\",\n\t\t  odm_get_bb_reg(dm, R_0xc50, MASKDWORD),\n\t\t  odm_get_bb_reg(dm, R_0x994, MASKDWORD),\n\t\t  odm_get_bb_reg(dm, R_0x998, MASKDWORD));\n#endif\n\n\tif (!(phydm_nhm_check_rdy(dm))) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"Get NHM report Fail\\n\");\n\t\tphydm_nhm_racing_release(dm);\n\t\treturn false;\n\t}\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\tvalue32 = odm_read_4byte(dm, R_0xfa8);\n\t\todm_move_memory(dm, &ccx->nhm_result[0], &value32, 4);\n\n\t\tvalue32 = odm_read_4byte(dm, R_0xfac);\n\t\todm_move_memory(dm, &ccx->nhm_result[4], &value32, 4);\n\n\t\tvalue32 = odm_read_4byte(dm, R_0xfb0);\n\t\todm_move_memory(dm, &ccx->nhm_result[8], &value32, 4);\n\n\t\t/*@Get NHM duration*/\n\t\tvalue32 = odm_read_4byte(dm, R_0xfb4);\n\t\tccx->nhm_duration = (u16)(value32 & MASKLWORD);\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tvalue32 = odm_read_4byte(dm, R_0x2d40);\n\t\todm_move_memory(dm, &ccx->nhm_result[0], &value32, 4);\n\n\t\tvalue32 = odm_read_4byte(dm, R_0x2d44);\n\t\todm_move_memory(dm, &ccx->nhm_result[4], &value32, 4);\n\n\t\tvalue32 = odm_read_4byte(dm, R_0x2d48);\n\t\todm_move_memory(dm, &ccx->nhm_result[8], &value32, 4);\n\n\t\t/*@Get NHM duration*/\n\t\tvalue32 = odm_read_4byte(dm, R_0x2d4c);\n\t\tccx->nhm_duration = (u16)(value32 & MASKLWORD);\n\t#endif\n\t} else {\n\t\tvalue32 = odm_read_4byte(dm, R_0x8d8);\n\t\todm_move_memory(dm, &ccx->nhm_result[0], &value32, 4);\n\n\t\tvalue32 = odm_read_4byte(dm, R_0x8dc);\n\t\todm_move_memory(dm, &ccx->nhm_result[4], &value32, 4);\n\n\t\tvalue32 = odm_get_bb_reg(dm, R_0x8d0, 0xffff0000);\n\t\todm_move_memory(dm, &ccx->nhm_result[8], &value32, 2);\n\n\t\tvalue32 = odm_read_4byte(dm, R_0x8d4);\n\n\t\tccx->nhm_result[10] = (u8)((value32 & MASKBYTE2) >> 16);\n\t\tccx->nhm_result[11] = (u8)((value32 & MASKBYTE3) >> 24);\n\n\t\t/*@Get NHM duration*/\n\t\tccx->nhm_duration = (u16)(value32 & MASKLWORD);\n\t}\n\n\t/* sum all nhm_result */\n\tif (ccx->nhm_period >= 65530) {\n\t\tvalue32 = (ccx->nhm_duration * 100) >> 16;\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t\t  \"NHM valid time = %d, valid: %d percent\\n\",\n\t\t\t  ccx->nhm_duration, value32);\n\t}\n\n\tfor (i = 0; i < NHM_RPT_NUM; i++)\n\t\tnhm_rpt_sum_tmp += (u16)ccx->nhm_result[i];\n\n\tccx->nhm_rpt_sum = (u8)nhm_rpt_sum_tmp;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t  \"NHM_Rpt[%d](H->L)[%d %d %d %d %d %d %d %d %d %d %d %d]\\n\",\n\t\t  ccx->nhm_rpt_stamp, ccx->nhm_result[11], ccx->nhm_result[10],\n\t\t  ccx->nhm_result[9], ccx->nhm_result[8], ccx->nhm_result[7],\n\t\t  ccx->nhm_result[6], ccx->nhm_result[5], ccx->nhm_result[4],\n\t\t  ccx->nhm_result[3], ccx->nhm_result[2], ccx->nhm_result[1],\n\t\t  ccx->nhm_result[0]);\n\n\tphydm_nhm_racing_release(dm);\n\n#if (ENV_MNTR_DBG_2)\n\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t  \"[DBG][4] 0xc50=0x%x, 0x994=0x%x, 0x998=0x%x\\n\",\n\t\t  odm_get_bb_reg(dm, R_0xc50, MASKDWORD),\n\t\t  odm_get_bb_reg(dm, R_0x994, MASKDWORD),\n\t\t  odm_get_bb_reg(dm, R_0x998, MASKDWORD));\n#endif\n\n\tif (nhm_rpt_sum_tmp > 255) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t\t  \"[Warning] Invalid NHM RPT, total=%d\\n\",\n\t\t\t  nhm_rpt_sum_tmp);\n\t\treturn false;\n\t}\n\n\treturn true;\n}\n\nvoid phydm_nhm_set_th_reg(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu32 reg1 = 0, reg2 = 0, reg3 = 0, reg4 = 0, reg4_bit = 0;\n\tu32 val = 0;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\treg1 = R_0x994;\n\t\treg2 = R_0x998;\n\t\treg3 = R_0x99c;\n\t\treg4 = R_0x9a0;\n\t\treg4_bit = MASKBYTE0;\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\treg1 = R_0x1e60;\n\t\treg2 = R_0x1e44;\n\t\treg3 = R_0x1e48;\n\t\treg4 = R_0x1e5c;\n\t\treg4_bit = MASKBYTE2;\n\t#endif\n\t} else {\n\t\treg1 = R_0x890;\n\t\treg2 = R_0x898;\n\t\treg3 = R_0x89c;\n\t\treg4 = R_0xe28;\n\t\treg4_bit = MASKBYTE0;\n\t}\n\n\t/*Set NHM threshold*/ /*Unit: PWdB U(8,1)*/\n\tval = BYTE_2_DWORD(ccx->nhm_th[3], ccx->nhm_th[2],\n\t\t\t   ccx->nhm_th[1], ccx->nhm_th[0]);\n\tpdm_set_reg(dm, reg2, MASKDWORD, val);\n\tval = BYTE_2_DWORD(ccx->nhm_th[7], ccx->nhm_th[6],\n\t\t\t   ccx->nhm_th[5], ccx->nhm_th[4]);\n\tpdm_set_reg(dm, reg3, MASKDWORD, val);\n\tpdm_set_reg(dm, reg4, reg4_bit, ccx->nhm_th[8]);\n\tval = BYTE_2_DWORD(0, 0, ccx->nhm_th[10], ccx->nhm_th[9]);\n\tpdm_set_reg(dm, reg1, 0xffff0000, val);\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t  \"Update NHM_th[H->L]=[%d %d %d %d %d %d %d %d %d %d %d]\\n\",\n\t\t  ccx->nhm_th[10], ccx->nhm_th[9], ccx->nhm_th[8],\n\t\t  ccx->nhm_th[7], ccx->nhm_th[6], ccx->nhm_th[5],\n\t\t  ccx->nhm_th[4], ccx->nhm_th[3], ccx->nhm_th[2],\n\t\t  ccx->nhm_th[1], ccx->nhm_th[0]);\n}\n\nboolean\nphydm_nhm_th_update_chk(void *dm_void, enum nhm_application nhm_app, u8 *nhm_th,\n\t\t\tu32 *igi_new)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tboolean is_update = false;\n\tu8 igi_curr = phydm_get_igi(dm, BB_PATH_A);\n\tu8 nhm_igi_th_11k_low[NHM_TH_NUM] = {0x12, 0x15, 0x18, 0x1b, 0x1e,\n\t\t\t\t\t     0x23, 0x28, 0x2c, 0x78,\n\t\t\t\t\t     0x78, 0x78};\n\tu8 nhm_igi_th_11k_high[NHM_TH_NUM] = {0x1e, 0x23, 0x28, 0x2d, 0x32,\n\t\t\t\t\t      0x37, 0x78, 0x78, 0x78, 0x78,\n\t\t\t\t\t      0x78};\n\tu8 nhm_igi_th_xbox[NHM_TH_NUM] = {0x1a, 0x2c, 0x2e, 0x30, 0x32, 0x34,\n\t\t\t\t\t  0x36, 0x38, 0x3a, 0x3c, 0x3d};\n\tu8 i = 0;\n\tu8 th_tmp = igi_curr - CCA_CAP;\n\tu8 th_step = 2;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"App=%d, nhm_igi=0x%x, igi_curr=0x%x\\n\",\n\t\t  nhm_app, ccx->nhm_igi, igi_curr);\n\n\tif (igi_curr < 0x10) /* Protect for invalid IGI*/\n\t\treturn false;\n\n\tswitch (nhm_app) {\n\tcase NHM_BACKGROUND: /* @Get IGI form driver parameter(cur_ig_value)*/\n\t\tif (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) {\n\t\t\tis_update = true;\n\t\t\t*igi_new = (u32)igi_curr;\n\n\t\t\t#ifdef NHM_DYM_PW_TH_SUPPORT\n\t\t\tif ((dm->support_ic_type & ODM_IC_JGR3_SERIES) &&\n\t\t\t    ccx->nhm_dym_pw_th_en) {\n\t\t\t\tth_tmp = MAX_2(igi_curr - DYM_PWTH_CCA_CAP, 0);\n\t\t\t\tth_step = 3;\n\t\t\t}\n\t\t\t#endif\n\n\t\t\tnhm_th[0] = (u8)IGI_2_NHM_TH(th_tmp);\n\n\t\t\tfor (i = 1; i <= 10; i++)\n\t\t\t\tnhm_th[i] = nhm_th[0] +\n\t\t\t\t\t    IGI_2_NHM_TH(th_step * i);\n\n\t\t}\n\t\tbreak;\n\n\tcase NHM_ACS:\n\t\tif (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) {\n\t\t\tis_update = true;\n\t\t\t*igi_new = (u32)igi_curr;\n\t\t\tnhm_th[0] = (u8)IGI_2_NHM_TH(igi_curr - CCA_CAP);\n\t\t\tfor (i = 1; i <= 10; i++)\n\t\t\t\tnhm_th[i] = nhm_th[0] + IGI_2_NHM_TH(2 * i);\n\t\t}\n\t\tbreak;\n\n\tcase IEEE_11K_HIGH:\n\t\tis_update = true;\n\t\t*igi_new = 0x2c;\n\t\tfor (i = 0; i < NHM_TH_NUM; i++)\n\t\t\tnhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_11k_high[i]);\n\t\tbreak;\n\n\tcase IEEE_11K_LOW:\n\t\tis_update = true;\n\t\t*igi_new = 0x20;\n\t\tfor (i = 0; i < NHM_TH_NUM; i++)\n\t\t\tnhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_11k_low[i]);\n\t\tbreak;\n\n\tcase INTEL_XBOX:\n\t\tis_update = true;\n\t\t*igi_new = 0x36;\n\t\tfor (i = 0; i < NHM_TH_NUM; i++)\n\t\t\tnhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_xbox[i]);\n\t\tbreak;\n\n\tcase NHM_DBG: /*@Get IGI form register*/\n\t\tigi_curr = phydm_get_igi(dm, BB_PATH_A);\n\t\tif (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) {\n\t\t\tis_update = true;\n\t\t\t*igi_new = (u32)igi_curr;\n\t\t\tnhm_th[0] = (u8)IGI_2_NHM_TH(igi_curr - CCA_CAP);\n\t\t\tfor (i = 1; i <= 10; i++)\n\t\t\t\tnhm_th[i] = nhm_th[0] + IGI_2_NHM_TH(2 * i);\n\t\t}\n\t\tbreak;\n\t}\n\n\tif (is_update) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[Update NHM_TH] igi_RSSI=%d\\n\",\n\t\t\t  IGI_2_RSSI(*igi_new));\n\n\t\tfor (i = 0; i < NHM_TH_NUM; i++) {\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"NHM_th[%d](RSSI) = %d\\n\",\n\t\t\t\t  i, NTH_TH_2_RSSI(nhm_th[i]));\n\t\t}\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"No need to update NHM_TH\\n\");\n\t}\n\treturn is_update;\n}\n\nvoid phydm_nhm_set(void *dm_void, enum nhm_option_txon_all include_tx,\n\t\t   enum nhm_option_cca_all include_cca,\n\t\t   enum nhm_divider_opt_all divi_opt,\n\t\t   enum nhm_application nhm_app, u16 period)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu8 nhm_th[NHM_TH_NUM] = {0};\n\tu32 igi = 0x20;\n\tu32 reg1 = 0, reg2 = 0;\n\tu32 val_tmp = 0;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t  \"incld{tx, cca}={%d, %d}, divi_opt=%d, period=%d\\n\",\n\t\t  include_tx, include_cca, divi_opt, period);\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\treg1 = R_0x994;\n\t\treg2 = R_0x990;\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\treg1 = R_0x1e60;\n\t\treg2 = R_0x1e40;\n\t#endif\n\t} else {\n\t\treg1 = R_0x890;\n\t\treg2 = R_0x894;\n\t}\n\n\t/*Set disable_ignore_cca, disable_ignore_txon, ccx_en*/\n\tif (include_tx != ccx->nhm_include_txon ||\n\t    include_cca != ccx->nhm_include_cca ||\n\t    divi_opt != ccx->nhm_divider_opt) {\n\t    /* some old ic is not supported on NHM divider option */\n\t\tif (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B |\n\t\t    ODM_RTL8195A | ODM_RTL8192E)) {\n\t\t\tval_tmp = (u32)((include_tx << 2) |\n\t\t\t\t  (include_cca << 1) | 1);\n\t\t\tpdm_set_reg(dm, reg1, 0x700, val_tmp);\n\t\t} else {\n\t\t\tval_tmp = (u32)BIT_2_BYTE(divi_opt, include_tx,\n\t\t\t\t  include_cca, 1);\n\t\t\tpdm_set_reg(dm, reg1, 0xf00, val_tmp);\n\t\t}\n\t\tccx->nhm_include_txon = include_tx;\n\t\tccx->nhm_include_cca = include_cca;\n\t\tccx->nhm_divider_opt = divi_opt;\n\t\t#if 0\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t\t  \"val_tmp=%d, incld{tx, cca}={%d, %d}, divi_opt=%d, period=%d\\n\",\n\t\t\t  val_tmp, include_tx, include_cca, divi_opt, period);\n\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"0x994=0x%x\\n\",\n\t\t\t  odm_get_bb_reg(dm, 0x994, 0xf00));\n\t\t#endif\n\t}\n\n\t/*Set NHM period*/\n\tif (period != ccx->nhm_period) {\n\t\tpdm_set_reg(dm, reg2, MASKHWORD, period);\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t\t  \"Update NHM period ((%d)) -> ((%d))\\n\",\n\t\t\t  ccx->nhm_period, period);\n\n\t\tccx->nhm_period = period;\n\t}\n\n\t/*Set NHM threshold*/\n\tif (phydm_nhm_th_update_chk(dm, nhm_app, &(nhm_th[0]), &igi)) {\n\t\t/*Pause IGI*/\n\t\tif (nhm_app == NHM_BACKGROUND || nhm_app == NHM_ACS) {\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"DIG Free Run\\n\");\n\t\t} else if (phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE,\n\t\t\t\t\t    PHYDM_PAUSE_LEVEL_1, 1, &igi)\n\t\t\t\t\t    == PAUSE_FAIL) {\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"pause DIG Fail\\n\");\n\t\t\treturn;\n\t\t} else {\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"pause DIG=0x%x\\n\", igi);\n\t\t}\n\t\tccx->nhm_app = nhm_app;\n\t\tccx->nhm_igi = (u8)igi;\n\t\todm_move_memory(dm, &ccx->nhm_th[0], &nhm_th, NHM_TH_NUM);\n\n\t\t/*Set NHM th*/\n\t\tphydm_nhm_set_th_reg(dm);\n\t}\n}\n\nu8 phydm_nhm_mntr_set(void *dm_void, struct nhm_para_info *nhm_para)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu16 nhm_time = 0; /*unit: 4us*/\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\n\tif (nhm_para->mntr_time == 0)\n\t\treturn PHYDM_SET_FAIL;\n\n\tif (nhm_para->nhm_lv >= NHM_MAX_NUM) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"Wrong LV=%d\\n\", nhm_para->nhm_lv);\n\t\treturn PHYDM_SET_FAIL;\n\t}\n\n\tif (phydm_nhm_racing_ctrl(dm, nhm_para->nhm_lv) == PHYDM_SET_FAIL)\n\t\treturn PHYDM_SET_FAIL;\n\n\tif (nhm_para->mntr_time >= 262)\n\t\tnhm_time = NHM_PERIOD_MAX;\n\telse\n\t\tnhm_time = nhm_para->mntr_time * MS_TO_4US_RATIO;\n\n\tphydm_nhm_set(dm, nhm_para->incld_txon, nhm_para->incld_cca,\n\t\t      nhm_para->div_opt, nhm_para->nhm_app, nhm_time);\n\n\treturn PHYDM_SET_SUCCESS;\n}\n\n#ifdef NHM_DYM_PW_TH_SUPPORT\nvoid\nphydm_nhm_restore_pw_th(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\n\todm_set_bb_reg(dm, R_0x82c, 0x3f, ccx->nhm_pw_th_rf20_dft);\n}\n\nvoid\nphydm_nhm_set_pw_th(void *dm_void, u8 noise, boolean chk_succ)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu8 pre_pw_th_rf20 = 0;\n\tu8 new_pw_th_rf20 = 0;\n\tu8 pw_th_u_bnd = 0;\n\ts8 noise_diff = 0;\n\tu8 point_mean = 15;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\n\tif (*dm->band_width != CHANNEL_WIDTH_20 ||\n\t    *dm->band_type == ODM_BAND_5G) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,  \"bandwidth=((%d)), band=((%d))\\n\",\n\t\t\t  *dm->band_width, *dm->band_type);\n\t\tphydm_nhm_restore_pw_th(dm);\n\t\treturn;\n\t}\n\n\tpre_pw_th_rf20 = (u8)odm_get_bb_reg(dm, R_0x82c, 0x3f);\n\n\t/* @pre_pw_th can not be lower than default value*/\n\tif (pre_pw_th_rf20 < ccx->nhm_pw_th_rf20_dft) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t\t  \"pre_pw_th=((%d)), new_pw_th=((%d))\\n\",\n\t\t\t  pre_pw_th_rf20, ccx->nhm_pw_th_rf20_dft);\n\n\t\tphydm_nhm_restore_pw_th(dm);\n\t\treturn;\n\t}\n\n\tif (chk_succ) {\n\t\tnoise_diff = noise - (ccx->nhm_igi - 10);\n\t\tpw_th_u_bnd = (u8)(noise_diff + 32 + point_mean);\n\n\t\tpw_th_u_bnd = MIN_2(pw_th_u_bnd, ccx->nhm_pw_th_max);\n\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t\t  \"noise_diff=((%d)), max=((%d)), pw_th_u_bnd=((%d))\\n\",\n\t\t\t  noise_diff, ccx->nhm_pw_th_max, pw_th_u_bnd);\n\n\t\tif (pw_th_u_bnd > pre_pw_th_rf20) {\n\t\t\tnew_pw_th_rf20 = pre_pw_th_rf20 + 1;\n\t\t} else if (pw_th_u_bnd == pre_pw_th_rf20) {\n\t\t\tnew_pw_th_rf20 = pre_pw_th_rf20;\n\t\t} else {\n\t\t\tif (pre_pw_th_rf20 > ccx->nhm_pw_th_rf20_dft)\n\t\t\t\tnew_pw_th_rf20 = pre_pw_th_rf20 - 1;\n\t\t\telse /* @pre_pw_th = ccx->nhm_pw_th_dft*/\n\t\t\t\tnew_pw_th_rf20 = pre_pw_th_rf20;\n\t\t}\n\t} else {\n\t\tif (pre_pw_th_rf20 > ccx->nhm_pw_th_rf20_dft)\n\t\t\tnew_pw_th_rf20 = pre_pw_th_rf20 - 1;\n\t\telse /* @pre_pw_th = ccx->nhm_pw_th_dft*/\n\t\t\tnew_pw_th_rf20 = pre_pw_th_rf20;\n\t}\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"pre_pw_th=((%d)), new_pw_th=((%d))\\n\",\n\t\t  pre_pw_th_rf20, new_pw_th_rf20);\n\n\tif (new_pw_th_rf20 != pre_pw_th_rf20)\n\t\todm_set_bb_reg(dm, R_0x82c, 0x3f, new_pw_th_rf20);\n}\n\nu8\nphydm_nhm_cal_noise(void *dm_void, u8 start_i, u8 end_i, u8 n_sum)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu8 i = 0;\n\tu32 noise_tmp = 0;\n\tu8 noise = 0;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\n\tfor (i = start_i; i <= end_i; i++)\n\t\tnoise_tmp += ccx->nhm_result[i] * (ccx->nhm_th[0] - 3 +\n\t\t\t     6 * i);\n\n\tnoise = (u8)(NTH_TH_2_RSSI(noise_tmp / n_sum));\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"noise(RSSI)=((%d))\\n\", noise);\n\n\treturn noise;\n}\n\nvoid\nphydm_nhm_dym_pw_th_1peak(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu8 i = 0;\n\tu8 max_i = 0;\n\tu8 m_dif_l1 = 0;\n\tu8 m_dif_r1 = 0;\n\tu8 patt_case = 0;\n\tu8 l1_dif_r2 = 0;\n\tu8 l2_dif_r1 = 0;\n\tu8 l1_dif_r1 = 0;\n\tu8 n_sum = 0;\n\tu8 r1_dif_r2 = 0;\n\tu8 l1_dif_l2 = 0;\n\tu8 noise = 0;\n\tboolean chk_succ = false;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\n\t/* @step1*/\n\tfor (i = 1; i < NHM_RPT_NUM; i++) {\n\t\tif (ccx->nhm_result[i] >= ccx->nhm_result[max_i])\n\t\t\tmax_i = i;\n\t}\n\n\tif (max_i == 0 || max_i == (NHM_RPT_NUM - 1)) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"max index can not be 0 or 11\\n\");\n\t\tphydm_nhm_set_pw_th(dm, 0, chk_succ);\n\t\treturn;\n\t}\n\n\t/* @step2*/\n\tm_dif_l1 = ccx->nhm_result[max_i] - ccx->nhm_result[max_i - 1];\n\tm_dif_r1 = ccx->nhm_result[max_i] - ccx->nhm_result[max_i + 1];\n\n\tif (m_dif_r1 <= NHM_TH1 && (max_i != NHM_RPT_NUM - 1))\n\t\tpatt_case = NHM_1PEAK_PS;\n\telse if ((m_dif_l1 <= NHM_TH1) && (max_i != 0))\n\t\tpatt_case = NHM_1PEAK_NS;\n\telse\n\t\tpatt_case = NHM_1PEAK_SYM;\n\n\tswitch (patt_case) {\n\tcase NHM_1PEAK_PS:\n\t\t/* @step3*/\n\t\tl1_dif_r2 = DIFF_2(ccx->nhm_result[max_i - 1],\n\t\t\t\t   ccx->nhm_result[max_i + 2]);\n\t\tif (l1_dif_r2 > NHM_TH2) {\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"S3 fail:c1((%d))\\n\",\n\t\t\t\t  l1_dif_r2);\n\t\t\tbreak;\n\t\t}\n\t\t/* @step4*/\n\t\tn_sum = ccx->nhm_result[max_i - 1] + ccx->nhm_result[max_i] +\n\t\t\tccx->nhm_result[max_i + 1] + ccx->nhm_result[max_i + 2];\n\t\tif (n_sum < NHM_TH4) {\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"S4 fail:((%d))\\n\", n_sum);\n\t\t\tbreak;\n\t\t}\n\t\t/* @step5*/\n\t\tr1_dif_r2 = DIFF_2(ccx->nhm_result[max_i + 1],\n\t\t\t\t   ccx->nhm_result[max_i + 2]);\n\t\tif (m_dif_l1 < NHM_TH5 || r1_dif_r2 < NHM_TH5) {\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"S5 fail:c1((%d, %d))\\n\",\n\t\t\t\t  m_dif_l1, r1_dif_r2);\n\t\t\tbreak;\n\t\t}\n\t\t/* @step6*/\n\t\tchk_succ = true;\n\t\tnoise = phydm_nhm_cal_noise(dm, max_i - 1, max_i + 2, n_sum);\n\t\tbreak;\n\tcase NHM_1PEAK_NS:\n\t\t/* @step3*/\n\t\tl2_dif_r1 = DIFF_2(ccx->nhm_result[max_i - 2],\n\t\t\t\t   ccx->nhm_result[max_i + 1]);\n\t\tif (l2_dif_r1 > NHM_TH2) {\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"S3 fail:c2((%d))\\n\",\n\t\t\t\t  l2_dif_r1);\n\t\t\tbreak;\n\t\t}\n\t\t/* @step4*/\n\t\tn_sum = ccx->nhm_result[max_i - 2] +\n\t\t\tccx->nhm_result[max_i - 1] +\n\t\t\tccx->nhm_result[max_i] + ccx->nhm_result[max_i + 1];\n\t\tif (n_sum < NHM_TH4) {\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"S4 fail:((%d))\\n\", n_sum);\n\t\t\tbreak;\n\t\t}\n\t\t/* @step5*/\n\t\tl1_dif_l2 = DIFF_2(ccx->nhm_result[max_i - 1],\n\t\t\t\t   ccx->nhm_result[max_i - 2]);\n\t\tif (m_dif_r1 < NHM_TH5 || l1_dif_l2 < NHM_TH5) {\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"S5 fail:c2((%d, %d))\\n\",\n\t\t\t\t  m_dif_r1, l1_dif_l2);\n\t\t\tbreak;\n\t\t}\n\t\t/* @step6*/\n\t\tchk_succ = true;\n\t\tnoise = phydm_nhm_cal_noise(dm, max_i - 2, max_i + 1, n_sum);\n\n\t\tbreak;\n\tcase NHM_1PEAK_SYM:\n\t\t/* @step3*/\n\t\tl1_dif_r1 = DIFF_2(ccx->nhm_result[max_i - 1],\n\t\t\t\t   ccx->nhm_result[max_i + 1]);\n\t\tif (l1_dif_r1 > NHM_TH3) {\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"S3 fail: c3((%d))\\n\",\n\t\t\t\t  l1_dif_r1);\n\t\t\tbreak;\n\t\t}\n\t\t/* @step4*/\n\t\tn_sum = ccx->nhm_result[max_i - 1] + ccx->nhm_result[max_i] +\n\t\t\tccx->nhm_result[max_i + 1];\n\t\tif (n_sum < NHM_TH4) {\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"S4 fail:((%d))\\n\", n_sum);\n\t\t\tbreak;\n\t\t}\n\t\t/* @step5*/\n\t\tif (m_dif_l1 < NHM_TH6 || m_dif_r1 < NHM_TH6) {\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"S5 fail:c3((%d, %d))\\n\",\n\t\t\t\t  m_dif_l1, m_dif_r1);\n\t\t\tbreak;\n\t\t}\n\t\t/* @step6*/\n\t\tchk_succ = true;\n\t\tnoise = phydm_nhm_cal_noise(dm, max_i - 1, max_i + 1, n_sum);\n\n\t\tbreak;\n\t}\n\tphydm_nhm_set_pw_th(dm, noise, chk_succ);\n}\n\nvoid\nphydm_nhm_dym_pw_th_sl(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu8 i = 0;\n\tu8 n_sum = 0;\n\tu8 noise = 0;\n\tboolean chk_succ = false;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\n\tfor (i = 0; i < NHM_RPT_NUM - 3; i++) {\n\t\tn_sum = ccx->nhm_result[i] + ccx->nhm_result[i + 1] +\n\t\t\tccx->nhm_result[i + 2] + ccx->nhm_result[i + 3];\n\t\tif (n_sum >= ccx->nhm_sl_pw_th) {\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"Do sl[%d:%d]\\n\", i, i + 3);\n\t\t\tchk_succ = true;\n\t\t\tnoise = phydm_nhm_cal_noise(dm, i, i + 3, n_sum);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!chk_succ)\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"SL method failed!\\n\");\n\n\tphydm_nhm_set_pw_th(dm, noise, chk_succ);\n}\n\nvoid\nphydm_nhm_dym_pw_th(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\n\tif (ccx->nhm_dym_1_peak_en)\n\t\tphydm_nhm_dym_pw_th_1peak(dm);\n\telse\n\t\tphydm_nhm_dym_pw_th_sl(dm);\n}\n\nvoid\nphydm_nhm_dym_pw_th_patch_id_chk(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\n\tif (dm->iot_table.phydm_patch_id == 0x100f0401) {\n\t\tccx->nhm_dym_pw_th_en = true;\n\t} else {\n\t\tif (ccx->nhm_dym_pw_th_en) {\n\t\t\tphydm_nhm_restore_pw_th(dm);\n\t\t\tccx->nhm_dym_pw_th_en = false;\n\t\t}\n\t}\n}\n#endif\n\n/*@Environment Monitor*/\nboolean\nphydm_nhm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tstruct nhm_para_info nhm_para = {0};\n\tboolean nhm_chk_result = false;\n\tu32 sys_return_time = 0;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\n\tif (ccx->nhm_manual_ctrl) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"NHM in manual ctrl\\n\");\n\t\treturn nhm_chk_result;\n\t}\n\tsys_return_time = ccx->nhm_trigger_time + MAX_ENV_MNTR_TIME;\n\tif (ccx->nhm_app != NHM_BACKGROUND &&\n\t    (sys_return_time > dm->phydm_sys_up_time)) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t\t  \"nhm_app=%d, trigger_time %d, sys_time=%d\\n\",\n\t\t\t  ccx->nhm_app, ccx->nhm_trigger_time,\n\t\t\t  dm->phydm_sys_up_time);\n\n\t\treturn nhm_chk_result;\n\t}\n\n\t/*@[NHM get result & calculate Utility----------------------------*/\n\t#ifdef NHM_DYM_PW_TH_SUPPORT\n\tphydm_nhm_dym_pw_th_patch_id_chk(dm);\n\t#endif\n\n\tif (phydm_nhm_get_result(dm)) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"Get NHM_rpt success\\n\");\n\t\tphydm_nhm_get_utility(dm);\n\n\t\t#ifdef NHM_DYM_PW_TH_SUPPORT\n\t\tif ((dm->support_ic_type & ODM_IC_JGR3_SERIES) &&\n\t\t    ccx->nhm_dym_pw_th_en)\n\t\t\tphydm_nhm_dym_pw_th(dm);\n\t\t#endif\n\t} else {\n\t\t#ifdef NHM_DYM_PW_TH_SUPPORT\n\t\tif ((dm->support_ic_type & ODM_IC_JGR3_SERIES) &&\n\t\t    ccx->nhm_dym_pw_th_en)\n\t\t\tphydm_nhm_set_pw_th(dm, 0, false);\n\t\t#endif\n\t}\n\n\t/*@[NHM trigger setting]------------------------------------------*/\n\tnhm_para.incld_txon = NHM_EXCLUDE_TXON;\n\tnhm_para.incld_cca = NHM_EXCLUDE_CCA;\n\t#ifdef NHM_DYM_PW_TH_SUPPORT\n\tif ((dm->support_ic_type & ODM_IC_JGR3_SERIES) &&\n\t    ccx->nhm_app == NHM_BACKGROUND && ccx->nhm_dym_pw_th_en)\n\t\tnhm_para.div_opt = NHM_VALID;\n\telse\n\t#endif\n\t\tnhm_para.div_opt = NHM_CNT_ALL;\n\n\tnhm_para.nhm_app = NHM_BACKGROUND;\n\tnhm_para.nhm_lv = NHM_LV_1;\n\t#ifdef NHM_DYM_PW_TH_SUPPORT\n\tif ((dm->support_ic_type & ODM_IC_JGR3_SERIES) &&\n\t    ccx->nhm_app == NHM_BACKGROUND && ccx->nhm_dym_pw_th_en)\n\t\tnhm_para.mntr_time = monitor_time >> ccx->nhm_period_decre;\n\telse\n\t#endif\n\t\tnhm_para.mntr_time = monitor_time;\n\n\tnhm_chk_result = phydm_nhm_mntr_set(dm, &nhm_para);\n\n\treturn nhm_chk_result;\n}\n\nvoid phydm_nhm_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"cur_igi=0x%x\\n\",\n\t\t  dm->dm_dig_table.cur_ig_value);\n\n\tccx->nhm_app = NHM_BACKGROUND;\n\tccx->nhm_igi = 0xff;\n\n\t/*Set NHM threshold*/\n\tccx->nhm_ongoing = false;\n\tccx->nhm_set_lv = NHM_RELEASE;\n\n\tif (phydm_nhm_th_update_chk(dm, ccx->nhm_app, &ccx->nhm_th[0],\n\t\t\t\t    (u32 *)&ccx->nhm_igi))\n\t\tphydm_nhm_set_th_reg(dm);\n\n\tccx->nhm_period = 0;\n\n\tccx->nhm_include_cca = NHM_CCA_INIT;\n\tccx->nhm_include_txon = NHM_TXON_INIT;\n\tccx->nhm_divider_opt = NHM_CNT_INIT;\n\n\tccx->nhm_manual_ctrl = 0;\n\tccx->nhm_rpt_stamp = 0;\n\n\t#ifdef NHM_DYM_PW_TH_SUPPORT\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tccx->nhm_dym_pw_th_en = false;\n\t\tccx->nhm_dym_1_peak_en = false;\n\t\tccx->nhm_pw_th_rf20_dft = (u8)odm_get_bb_reg(dm, R_0x82c, 0x3f);\n\t\tccx->nhm_pw_th_max = 63;\n\t\tccx->nhm_sl_pw_th = 100; /* @39%*/\n\t\tccx->nhm_period_decre = 1;\n\t}\n\t#endif\n}\n\nvoid phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t   u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tstruct nhm_para_info nhm_para;\n\tchar help[] = \"-h\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tboolean nhm_rpt_success = true;\n\tu8 result_tmp = 0;\n\tu8 i;\n\n\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"NHM Basic-Trigger 262ms: {1}\\n\");\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"NHM Adv-Trigger: {2} {Include TXON} {Include CCA}\\n{0:Cnt_all, 1:Cnt valid} {App} {LV} {0~262ms}\\n\");\n\t\t#ifdef NHM_DYM_PW_TH_SUPPORT\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"NHM dym_pw_th: {3} {en} {en_1-peak} {max} {period_decre} {sl_th}\\n\");\n\t\t}\n\t\t#endif\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"NHM Get Result: {100}\\n\");\n\t} else if (var1[0] == 100) { /*@Get NHM results*/\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"IGI=0x%x, rpt_stamp=%d\\n\", ccx->nhm_igi,\n\t\t\t ccx->nhm_rpt_stamp);\n\n\t\tnhm_rpt_success = phydm_nhm_get_result(dm);\n\n\t\tif (nhm_rpt_success) {\n\t\t\tfor (i = 0; i <= 11; i++) {\n\t\t\t\tresult_tmp = ccx->nhm_result[i];\n\t\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t\t out_len - used,\n\t\t\t\t\t \"nhm_rpt[%d] = %d (%d percent)\\n\",\n\t\t\t\t\t i, result_tmp,\n\t\t\t\t\t (((result_tmp * 100) + 128) >> 8));\n\t\t\t}\n\t\t} else {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"Get NHM_rpt Fail\\n\");\n\t\t}\n\t\tccx->nhm_manual_ctrl = 0;\n\t#ifdef NHM_DYM_PW_TH_SUPPORT\n\t} else if (var1[0] == 3) { /* @NMH dym_pw_th*/\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t\tfor (i = 1; i < 7; i++) {\n\t\t\t\tif (input[i + 1]) {\n\t\t\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,\n\t\t\t\t\t\t     &var1[i]);\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (var1[1] == 1) {\n\t\t\t\tccx->nhm_dym_pw_th_en = true;\n\t\t\t\tccx->nhm_dym_1_peak_en = (boolean)var1[2];\n\t\t\t\tccx->nhm_pw_th_max = (u8)var1[3];\n\t\t\t\tccx->nhm_period_decre = (u8)var1[4];\n\t\t\t\tccx->nhm_sl_pw_th = (u8)var1[5];\n\t\t\t} else if (var1[1] == 0) {\n\t\t\t\tccx->nhm_dym_pw_th_en = false;\n\t\t\t\tphydm_nhm_restore_pw_th(dm);\n\t\t\t} else if (var1[1] == 2) {\n\t\t\t\tccx->nhm_dym_pw_th_en = true;\n\t\t\t\tccx->nhm_dym_1_peak_en = false;\n\t\t\t\tccx->nhm_pw_th_max = 63;\n\t\t\t\tccx->nhm_period_decre = 1;\n\t\t\t\tccx->nhm_sl_pw_th = 100;\n\t\t\t}\n\t\t}\n\t#endif\n\t} else { /*NMH trigger*/\n\n\t\tccx->nhm_manual_ctrl = 1;\n\n\t\tfor (i = 1; i < 7; i++) {\n\t\t\tif (input[i + 1]) {\n\t\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,\n\t\t\t\t\t     &var1[i]);\n\t\t\t}\n\t\t}\n\n\t\tif (var1[0] == 1) {\n\t\t\tnhm_para.incld_txon = NHM_EXCLUDE_TXON;\n\t\t\tnhm_para.incld_cca = NHM_EXCLUDE_CCA;\n\t\t\tnhm_para.div_opt = NHM_CNT_ALL;\n\t\t\tnhm_para.nhm_app = NHM_DBG;\n\t\t\tnhm_para.nhm_lv = NHM_LV_4;\n\t\t\tnhm_para.mntr_time = 262;\n\t\t} else {\n\t\t\tnhm_para.incld_txon = (enum nhm_option_txon_all)var1[1];\n\t\t\tnhm_para.incld_cca = (enum nhm_option_cca_all)var1[2];\n\t\t\tnhm_para.div_opt = (enum nhm_divider_opt_all)var1[3];\n\t\t\tnhm_para.nhm_app = (enum nhm_application)var1[4];\n\t\t\tnhm_para.nhm_lv = (enum phydm_nhm_level)var1[5];\n\t\t\tnhm_para.mntr_time = (u16)var1[6];\n\n\t\t\t/* some old ic is not supported on NHM divider option */\n\t\t\tif (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B |\n\t\t\t    ODM_RTL8195A | ODM_RTL8192E)) {\n\t\t\t\tnhm_para.div_opt = NHM_CNT_ALL;\n\t\t\t}\n\t\t}\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"txon=%d, cca=%d, dev=%d, app=%d, lv=%d, time=%d ms\\n\",\n\t\t\t nhm_para.incld_txon, nhm_para.incld_cca,\n\t\t\t nhm_para.div_opt, nhm_para.nhm_app,\n\t\t\t nhm_para.nhm_lv, nhm_para.mntr_time);\n\n\t\tif (phydm_nhm_mntr_set(dm, &nhm_para) == PHYDM_SET_SUCCESS)\n\t\t\tphydm_nhm_trigger(dm);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"IGI=0x%x, rpt_stamp=%d\\n\", ccx->nhm_igi,\n\t\t\t ccx->nhm_rpt_stamp);\n\n\t\tfor (i = 0; i <= 10; i++) {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"NHM_th[%d] RSSI = %d\\n\", i,\n\t\t\t\t NTH_TH_2_RSSI(ccx->nhm_th[i]));\n\t\t}\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\n#endif /*@#ifdef NHM_SUPPORT*/\n\n#ifdef CLM_SUPPORT\n\nvoid phydm_clm_racing_release(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"lv:(%d)->(0)\\n\", ccx->clm_set_lv);\n\n\tccx->clm_ongoing = false;\n\tccx->clm_set_lv = CLM_RELEASE;\n\tccx->clm_app = CLM_BACKGROUND;\n}\n\nu8 phydm_clm_racing_ctrl(void *dm_void, enum phydm_clm_level clm_lv)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu8 set_result = PHYDM_SET_SUCCESS;\n\t/*@acquire to control CLM API*/\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"clm_ongoing=%d, lv:(%d)->(%d)\\n\",\n\t\t  ccx->clm_ongoing, ccx->clm_set_lv, clm_lv);\n\tif (ccx->clm_ongoing) {\n\t\tif (clm_lv <= ccx->clm_set_lv) {\n\t\t\tset_result = PHYDM_SET_FAIL;\n\t\t} else {\n\t\t\tphydm_ccx_hw_restart(dm);\n\t\t\tccx->clm_ongoing = false;\n\t\t}\n\t}\n\n\tif (set_result)\n\t\tccx->clm_set_lv = clm_lv;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"clm racing success=%d\\n\", set_result);\n\treturn set_result;\n}\n\nvoid phydm_clm_c2h_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx_info = &dm->dm_ccx_info;\n\tu8 clm_report = cmd_buf[0];\n\t/*@u8 clm_report_idx = cmd_buf[1];*/\n\n\tif (cmd_len >= 12)\n\t\treturn;\n\n\tccx_info->clm_fw_result_acc += clm_report;\n\tccx_info->clm_fw_result_cnt++;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%d] clm_report= %d\\n\",\n\t\t  ccx_info->clm_fw_result_cnt, clm_report);\n}\n\nvoid phydm_clm_h2c(void *dm_void, u16 obs_time, u8 fw_clm_en)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 h2c_val[H2C_MAX_LENGTH] = {0};\n\tu8 i = 0;\n\tu8 obs_time_idx = 0;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s] ======>\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"obs_time_index=%d *4 us\\n\", obs_time);\n\n\tfor (i = 1; i <= 16; i++) {\n\t\tif (obs_time & BIT(16 - i)) {\n\t\t\tobs_time_idx = 16 - i;\n\t\t\tbreak;\n\t\t}\n\t}\n#if 0\n\tobs_time = (2 ^ 16 - 1)~(2 ^ 15)  => obs_time_idx = 15  (65535 ~32768)\n\tobs_time = (2 ^ 15 - 1)~(2 ^ 14)  => obs_time_idx = 14\n\t...\n\t...\n\t...\n\tobs_time = (2 ^ 1 - 1)~(2 ^ 0)  => obs_time_idx = 0\n\n#endif\n\n\th2c_val[0] = obs_time_idx | (((fw_clm_en) ? 1 : 0) << 7);\n\th2c_val[1] = CLM_MAX_REPORT_TIME;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"PHYDM h2c[0x4d]=0x%x %x %x %x %x %x %x\\n\",\n\t\t  h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2],\n\t\t  h2c_val[1], h2c_val[0]);\n\n\todm_fill_h2c_cmd(dm, PHYDM_H2C_FW_CLM_MNTR, H2C_MAX_LENGTH, h2c_val);\n}\n\nvoid phydm_clm_setting(void *dm_void, u16 clm_period /*@4us sample 1 time*/)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\n\tif (ccx->clm_period != clm_period) {\n\t\tif (dm->support_ic_type & ODM_IC_11AC_SERIES)\n\t\t\todm_set_bb_reg(dm, R_0x990, MASKLWORD, clm_period);\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\telse if (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\t\todm_set_bb_reg(dm, R_0x1e40, MASKLWORD, clm_period);\n\t\t#endif\n\t\telse if (dm->support_ic_type & ODM_IC_11N_SERIES)\n\t\t\todm_set_bb_reg(dm, R_0x894, MASKLWORD, clm_period);\n\n\t\tccx->clm_period = clm_period;\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t\t  \"Update CLM period ((%d)) -> ((%d))\\n\",\n\t\t\t  ccx->clm_period, clm_period);\n\t}\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"Set CLM period=%d * 4us\\n\",\n\t\t  ccx->clm_period);\n}\n\nvoid phydm_clm_trigger(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu32 reg1 = 0;\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES)\n\t\treg1 = R_0x994;\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\telse if (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\treg1 = R_0x1e60;\n\t#endif\n\telse\n\t\treg1 = R_0x890;\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\n\todm_set_bb_reg(dm, reg1, BIT(0), 0x0);\n\todm_set_bb_reg(dm, reg1, BIT(0), 0x1);\n\n\tccx->clm_trigger_time = dm->phydm_sys_up_time;\n\tccx->clm_rpt_stamp++;\n\tccx->clm_ongoing = true;\n}\n\nboolean\nphydm_clm_check_rdy(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tboolean is_ready = false;\n\tu32 reg1 = 0, reg1_bit = 0;\n#if (ENV_MNTR_DBG)\n\tu16 i = 0;\n\tu64 start_time = 0, progressing_time = 0;\n#endif\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\treg1 = R_0xfa4;\n\t\treg1_bit = 16;\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\treg1 = R_0x2d88;\n\t\treg1_bit = 16;\n\t#endif\n\t} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\tif (dm->support_ic_type & (ODM_RTL8710B | ODM_RTL8721D)) {\n\t\t\treg1 = R_0x8b4;\n\t\t\treg1_bit = 24;\n\t\t} else {\n\t\t\treg1 = R_0x8b4;\n\t\t\treg1_bit = 16;\n\t\t}\n\t}\n#if (ENV_MNTR_DBG)\n\tstart_time = odm_get_current_time(dm);\n\tfor (i = 0; i <= 400; i++) {\n\t\tif (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) {\n\t\t\tis_ready = true;\n\t\t\tbreak;\n\t\t}\n\t\tODM_delay_ms(1);\n\t}\n\tprogressing_time = odm_get_progressing_time(dm, start_time);\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"CLM rdy=%d, i=%d, CLM_polling_time=%lld\\n\",\n\t\t  is_ready, i, progressing_time);\n#else\n\tif (odm_get_bb_reg(dm, reg1, BIT(reg1_bit)))\n\t\tis_ready = true;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"CLM rdy=%d\\n\", is_ready);\n#endif\n\treturn is_ready;\n}\n\nvoid phydm_clm_get_utility(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu32 clm_result_tmp;\n\n\tif (ccx->clm_period == 0) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[warning] clm_period = 0\\n\");\n\t\tccx->clm_ratio = 0;\n\t} else if (ccx->clm_period >= 65530) {\n\t\tclm_result_tmp = (u32)(ccx->clm_result * 100);\n\t\tccx->clm_ratio = (u8)((clm_result_tmp + (1 << 15)) >> 16);\n\t} else {\n\t\tclm_result_tmp = (u32)(ccx->clm_result * 100);\n\t\tccx->clm_ratio = (u8)(clm_result_tmp / (u32)ccx->clm_period);\n\t}\n}\n\nboolean\nphydm_clm_get_result(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx_info = &dm->dm_ccx_info;\n\tu32 reg1 = 0;\n\tu32 val = 0;\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES)\n\t\treg1 = R_0x994;\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\telse if (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\treg1 = R_0x1e60;\n\t#endif\n\telse\n\t\treg1 = R_0x890;\n\tif (!(dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |\n\t\t\t\t     ODM_RTL8197G)))\n\t\todm_set_bb_reg(dm, reg1, BIT(0), 0x0);\n\tif (!(phydm_clm_check_rdy(dm))) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"Get CLM report Fail\\n\");\n\t\tphydm_clm_racing_release(dm);\n\t\treturn false;\n\t}\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\tval = odm_get_bb_reg(dm, R_0xfa4, MASKLWORD);\n\t\tccx_info->clm_result = (u16)val;\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tval = odm_get_bb_reg(dm, R_0x2d88, MASKLWORD);\n\t\tccx_info->clm_result = (u16)val;\n\t#endif\n\t} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\tval = odm_get_bb_reg(dm, R_0x8d0, MASKLWORD);\n\t\tccx_info->clm_result = (u16)val;\n\t}\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"CLM result = %d *4 us\\n\",\n\t\t  ccx_info->clm_result);\n\tphydm_clm_racing_release(dm);\n\treturn true;\n}\n\nvoid phydm_clm_mntr_fw(void *dm_void, u16 monitor_time /*unit ms*/)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu32 val = 0;\n\n\t/*@[Get CLM report]*/\n\tif (ccx->clm_fw_result_cnt != 0) {\n\t\tval = ccx->clm_fw_result_acc / ccx->clm_fw_result_cnt;\n\t\tccx->clm_ratio = (u8)val;\n\t} else {\n\t\tccx->clm_ratio = 0;\n\t}\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t  \"clm_fw_result_acc=%d, clm_fw_result_cnt=%d\\n\",\n\t\t  ccx->clm_fw_result_acc, ccx->clm_fw_result_cnt);\n\n\tccx->clm_fw_result_acc = 0;\n\tccx->clm_fw_result_cnt = 0;\n\n\t/*@[CLM trigger]*/\n\tif (monitor_time >= 262)\n\t\tccx->clm_period = 65535;\n\telse\n\t\tccx->clm_period = monitor_time * MS_TO_4US_RATIO;\n\n\tphydm_clm_h2c(dm, ccx->clm_period, true);\n}\n\nu8 phydm_clm_mntr_set(void *dm_void, struct clm_para_info *clm_para)\n{\n\t/*@Driver Monitor CLM*/\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu16 clm_period = 0;\n\n\tif (clm_para->mntr_time == 0)\n\t\treturn PHYDM_SET_FAIL;\n\n\tif (clm_para->clm_lv >= CLM_MAX_NUM) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[WARNING] Wrong LV=%d\\n\",\n\t\t\t  clm_para->clm_lv);\n\t\treturn PHYDM_SET_FAIL;\n\t}\n\n\tif (phydm_clm_racing_ctrl(dm, clm_para->clm_lv) == PHYDM_SET_FAIL)\n\t\treturn PHYDM_SET_FAIL;\n\n\tif (clm_para->mntr_time >= 262)\n\t\tclm_period = CLM_PERIOD_MAX;\n\telse\n\t\tclm_period = clm_para->mntr_time * MS_TO_4US_RATIO;\n\n\tccx->clm_app = clm_para->clm_app;\n\tphydm_clm_setting(dm, clm_period);\n\n\treturn PHYDM_SET_SUCCESS;\n}\n\nboolean\nphydm_clm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tstruct clm_para_info clm_para = {0};\n\tboolean clm_chk_result = false;\n\tu32 sys_return_time = 0;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s] ======>\\n\", __func__);\n\tif (ccx->clm_manual_ctrl) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"CLM in manual ctrl\\n\");\n\t\treturn clm_chk_result;\n\t}\n\n\tsys_return_time = ccx->clm_trigger_time + MAX_ENV_MNTR_TIME;\n\n\tif (ccx->clm_app != CLM_BACKGROUND &&\n\t    sys_return_time > dm->phydm_sys_up_time) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"trigger_time %d, sys_time=%d\\n\",\n\t\t\t  ccx->clm_trigger_time, dm->phydm_sys_up_time);\n\n\t\treturn clm_chk_result;\n\t}\n\n\tclm_para.clm_app = CLM_BACKGROUND;\n\tclm_para.clm_lv = CLM_LV_1;\n\tclm_para.mntr_time = monitor_time;\n\tif (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) {\n\t\t/*@[Get CLM report]*/\n\t\tif (phydm_clm_get_result(dm)) {\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"Get CLM_rpt success\\n\");\n\t\t\tphydm_clm_get_utility(dm);\n\t\t}\n\n\t\t/*@[CLM trigger]----------------------------------------------*/\n\t\tif (phydm_clm_mntr_set(dm, &clm_para) == PHYDM_SET_SUCCESS)\n\t\t\tclm_chk_result = true;\n\t} else {\n\t\tphydm_clm_mntr_fw(dm, monitor_time);\n\t}\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"clm_ratio=%d\\n\", ccx->clm_ratio);\n\n\t/*@PHYDM_DBG(dm, DBG_ENV_MNTR, \"clm_chk_result=%d\\n\",clm_chk_result);*/\n\n\treturn clm_chk_result;\n}\n\nvoid phydm_set_clm_mntr_mode(void *dm_void, enum clm_monitor_mode mode)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx_info = &dm->dm_ccx_info;\n\n\tif (ccx_info->clm_mntr_mode != mode) {\n\t\tccx_info->clm_mntr_mode = mode;\n\t\tphydm_ccx_hw_restart(dm);\n\n\t\tif (mode == CLM_DRIVER_MNTR)\n\t\t\tphydm_clm_h2c(dm, 0, 0);\n\t}\n}\n\nvoid phydm_clm_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\tccx->clm_ongoing = false;\n\tccx->clm_manual_ctrl = 0;\n\tccx->clm_mntr_mode = CLM_DRIVER_MNTR;\n\tccx->clm_period = 0;\n\tccx->clm_rpt_stamp = 0;\n\tphydm_clm_setting(dm, 65535);\n}\n\nvoid phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t   u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tchar help[] = \"-h\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tstruct clm_para_info clm_para = {0};\n\tu32 i;\n\n\tfor (i = 0; i < 4; i++) {\n\t\tif (input[i + 1])\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);\n\t}\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"CLM Driver Basic-Trigger 262ms: {1}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"CLM Driver Adv-Trigger: {2} {app} {LV} {0~262ms}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"CLM FW Trigger: {3} {1:drv, 2:fw}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"CLM Get Result: {100}\\n\");\n\t} else if (var1[0] == 100) { /* @Get CLM results */\n\n\t\tif (phydm_clm_get_result(dm))\n\t\t\tphydm_clm_get_utility(dm);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"clm_rpt_stamp=%d\\n\", ccx->clm_rpt_stamp);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"clm_ratio:((%d percent)) = (%d us/ %d us)\\n\",\n\t\t\t ccx->clm_ratio, ccx->clm_result << 2,\n\t\t\t ccx->clm_period << 2);\n\n\t\tccx->clm_manual_ctrl = 0;\n\n\t} else if (var1[0] == 3) {\n\t\tphydm_set_clm_mntr_mode(dm, (enum clm_monitor_mode)var1[1]);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"CLM mode: %s mode\\n\",\n\t\t\t ((ccx->clm_mntr_mode == CLM_FW_MNTR) ? \"FW\" : \"Drv\"));\n\t} else { /* Set & trigger CLM */\n\t\tccx->clm_manual_ctrl = 1;\n\n\t\tif (var1[0] == 1) {\n\t\t\tclm_para.clm_app = CLM_BACKGROUND;\n\t\t\tclm_para.clm_lv = CLM_LV_4;\n\t\t\tclm_para.mntr_time = 262;\n\t\t\tccx->clm_mntr_mode = CLM_DRIVER_MNTR;\n\n\t\t} else if (var1[0] == 2) {\n\t\t\tclm_para.clm_app = (enum clm_application)var1[1];\n\t\t\tclm_para.clm_lv = (enum phydm_clm_level)var1[2];\n\t\t\tccx->clm_mntr_mode = CLM_DRIVER_MNTR;\n\t\t\tclm_para.mntr_time = (u16)var1[3];\n\n\t\t}\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"app=%d, lv=%d, mode=%s, time=%d ms\\n\",\n\t\t\t clm_para.clm_app, clm_para.clm_lv,\n\t\t\t ((ccx->clm_mntr_mode == CLM_FW_MNTR) ? \"FW\" :\n\t\t\t \"driver\"), clm_para.mntr_time);\n\n\t\tif (phydm_clm_mntr_set(dm, &clm_para) == PHYDM_SET_SUCCESS)\n\t\t\tphydm_clm_trigger(dm);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"clm_rpt_stamp=%d\\n\", ccx->clm_rpt_stamp);\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\n#endif /*@#ifdef CLM_SUPPORT*/\n\nu8 phydm_env_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para,\n\t\t\t  struct clm_para_info *clm_para,\n\t\t\t  struct env_trig_rpt *trig_rpt)\n{\n#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT))\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tboolean nhm_set_ok = false;\n\tboolean clm_set_ok = false;\n\tu8 trigger_result = 0;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s] ======>\\n\", __func__);\n\n#if (ENV_MNTR_DBG_2)\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t  \"[DBG][2] 0xc50=0x%x, 0x994=0x%x, 0x998=0x%x\\n\",\n\t\t  odm_get_bb_reg(dm, R_0xc50, MASKDWORD),\n\t\t  odm_get_bb_reg(dm, R_0x994, MASKDWORD),\n\t\t  odm_get_bb_reg(dm, R_0x998, MASKDWORD));\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t\t  \"[DBG][2] 0x1d70=0x%x, 0x1e60=0x%x, 0x1e44=0x%x\\n\",\n\t\t\t odm_get_bb_reg(dm, R_0x1d70, MASKDWORD),\n\t\t\t odm_get_bb_reg(dm, R_0x1e60, MASKDWORD),\n\t\t\t odm_get_bb_reg(dm, R_0x1e44, MASKDWORD));\n\t#endif\n\t}\n#endif\n\n\t/*@[NHM]*/\n\tnhm_set_ok = phydm_nhm_mntr_set(dm, nhm_para);\n\n\t/*@[CLM]*/\n\tif (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) {\n\t\tclm_set_ok = phydm_clm_mntr_set(dm, clm_para);\n\t} else if (ccx->clm_mntr_mode == CLM_FW_MNTR) {\n\t\tphydm_clm_h2c(dm, CLM_PERIOD_MAX, true);\n\t\ttrigger_result |= CLM_SUCCESS;\n\t}\n\n\tif (nhm_set_ok) {\n\t\tphydm_nhm_trigger(dm);\n\t\ttrigger_result |= NHM_SUCCESS;\n\t}\n\n\tif (clm_set_ok) {\n\t\tphydm_clm_trigger(dm);\n\t\ttrigger_result |= CLM_SUCCESS;\n\t}\n\n\t/*@monitor for the test duration*/\n\tccx->start_time = odm_get_current_time(dm);\n\n\ttrig_rpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp;\n\ttrig_rpt->clm_rpt_stamp = ccx->clm_rpt_stamp;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"nhm_rpt_stamp=%d, clm_rpt_stamp=%d,\\n\\n\",\n\t\t  trig_rpt->nhm_rpt_stamp, trig_rpt->clm_rpt_stamp);\n\n\treturn trigger_result;\n#endif\n}\n\nu8 phydm_env_mntr_result(void *dm_void, struct env_mntr_rpt *rpt)\n{\n#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT))\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu8 env_mntr_rpt = 0;\n\tu64 progressing_time = 0;\n\tu32 val_tmp = 0;\n\n\t/*@monitor for the test duration*/\n\tprogressing_time = odm_get_progressing_time(dm, ccx->start_time);\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s] ======>\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"env_time=%lld\\n\", progressing_time);\n\n#if (ENV_MNTR_DBG_2)\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t\t  \"[DBG][2] 0xc50=0x%x, 0x994=0x%x, 0x998=0x%x\\n\",\n\t\t\t  odm_get_bb_reg(dm, R_0xc50, MASKDWORD),\n\t\t\t  odm_get_bb_reg(dm, R_0x994, MASKDWORD),\n\t\t\t  odm_get_bb_reg(dm, R_0x998, MASKDWORD));\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t\t  \"[DBG][2] 0x1d70=0x%x, 0x1e60=0x%x, 0x1e44=0x%x\\n\",\n\t\t\t  odm_get_bb_reg(dm, R_0x1d70, MASKDWORD),\n\t\t\t  odm_get_bb_reg(dm, R_0x1e60, MASKDWORD),\n\t\t\t  odm_get_bb_reg(dm, R_0x1e44, MASKDWORD));\n\t#endif\n\t}\n#endif\n\n\t/*@Get NHM result*/\n\tif (phydm_nhm_get_result(dm)) {\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"Get NHM_rpt success\\n\");\n\t\tphydm_nhm_get_utility(dm);\n\t\trpt->nhm_ratio = ccx->nhm_ratio;\n\t\tenv_mntr_rpt |= NHM_SUCCESS;\n\n\t\todm_move_memory(dm, &rpt->nhm_result[0],\n\t\t\t\t&ccx->nhm_result[0], NHM_RPT_NUM);\n\t} else {\n\t\trpt->nhm_ratio = ENV_MNTR_FAIL;\n\t}\n\n\t/*@Get CLM result*/\n\tif (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) {\n\t\tif (phydm_clm_get_result(dm)) {\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"Get CLM_rpt success\\n\");\n\t\t\tphydm_clm_get_utility(dm);\n\t\t\tenv_mntr_rpt |= CLM_SUCCESS;\n\t\t\trpt->clm_ratio = ccx->clm_ratio;\n\t\t} else {\n\t\t\trpt->clm_ratio = ENV_MNTR_FAIL;\n\t\t}\n\n\t} else {\n\t\tif (ccx->clm_fw_result_cnt != 0) {\n\t\t\tval_tmp = ccx->clm_fw_result_acc\n\t\t\t/ ccx->clm_fw_result_cnt;\n\t\t\tccx->clm_ratio = (u8)val_tmp;\n\t\t} else {\n\t\t\tccx->clm_ratio = 0;\n\t\t}\n\n\t\trpt->clm_ratio = ccx->clm_ratio;\n\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t\t  \"clm_fw_result_acc=%d, clm_fw_result_cnt=%d\\n\",\n\t\t\t  ccx->clm_fw_result_acc, ccx->clm_fw_result_cnt);\n\n\t\tccx->clm_fw_result_acc = 0;\n\t\tccx->clm_fw_result_cnt = 0;\n\t\tenv_mntr_rpt |= CLM_SUCCESS;\n\t}\n\n\trpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp;\n\trpt->clm_rpt_stamp = ccx->clm_rpt_stamp;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t  \"IGI=0x%x, nhm_ratio=%d, clm_ratio=%d, nhm_rpt_stamp=%d, clm_rpt_stamp=%d\\n\\n\",\n\t\t  ccx->nhm_igi, rpt->nhm_ratio, rpt->clm_ratio,\n\t\t  rpt->nhm_rpt_stamp, rpt->clm_rpt_stamp);\n\n\treturn env_mntr_rpt;\n#endif\n}\n\n/*@Environment Monitor*/\nvoid phydm_env_mntr_watchdog(void *dm_void)\n{\n#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT))\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tboolean nhm_chk_ok = false;\n\tboolean clm_chk_ok = false;\n\n\tif (!(dm->support_ability & ODM_BB_ENV_MONITOR))\n\t\treturn;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\tnhm_chk_ok = phydm_nhm_mntr_chk(dm, 262); /*@monitor 262ms*/\n\tclm_chk_ok = phydm_clm_mntr_chk(dm, 262); /*@monitor 262ms*/\n\n\t/*@PHYDM_DBG(dm, DBG_ENV_MNTR, \"nhm_chk_ok %d\\n\\n\",nhm_chk_ok);*/\n\t/*@PHYDM_DBG(dm, DBG_ENV_MNTR, \"clm_chk_ok %d\\n\\n\",clm_chk_ok);*/\n\n\tif (nhm_chk_ok)\n\t\tphydm_nhm_trigger(dm);\n\n\tif (clm_chk_ok)\n\t\tphydm_clm_trigger(dm);\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t  \"Summary: nhm_ratio=((%d)) clm_ratio=((%d))\\n\\n\",\n\t\t  ccx->nhm_ratio, ccx->clm_ratio);\n#endif\n}\n\nvoid phydm_env_monitor_init(void *dm_void)\n{\n#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT))\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (!(dm->support_ability & ODM_BB_ENV_MONITOR))\n\t\treturn;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"[%s]===>\\n\", __func__);\n\tphydm_ccx_hw_restart(dm);\n\tphydm_nhm_init(dm);\n\tphydm_clm_init(dm);\n#endif\n}\n\nvoid phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used,\n\t\t\tchar *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tchar help[] = \"-h\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tstruct clm_para_info clm_para = {0};\n\tstruct nhm_para_info nhm_para = {0};\n\tstruct env_mntr_rpt rpt = {0};\n\tstruct env_trig_rpt trig_rpt = {0};\n\tu8 set_result;\n\tu8 i;\n\n\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Basic-Trigger 262ms: {1}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Get Result: {100}\\n\");\n\t} else if (var1[0] == 100) { /* @Get CLM results */\n\n\t\tset_result = phydm_env_mntr_result(dm, &rpt);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Set Result=%d\\n nhm_ratio=%d clm_ratio=%d\\n nhm_rpt_stamp=%d, clm_rpt_stamp=%d,\\n\",\n\t\t\t set_result, rpt.nhm_ratio, rpt.clm_ratio,\n\t\t\t rpt.nhm_rpt_stamp, rpt.clm_rpt_stamp);\n\n\t\tfor (i = 0; i <= 11; i++) {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"nhm_rpt[%d] = %d (%d percent)\\n\", i,\n\t\t\t\t rpt.nhm_result[i],\n\t\t\t\t (((rpt.nhm_result[i] * 100) + 128) >> 8));\n\t\t}\n\n\t} else { /* Set & trigger CLM */\n\t\t/*nhm para*/\n\t\tnhm_para.incld_txon = NHM_EXCLUDE_TXON;\n\t\tnhm_para.incld_cca = NHM_EXCLUDE_CCA;\n\t\tnhm_para.div_opt = NHM_CNT_ALL;\n\t\tnhm_para.nhm_app = NHM_ACS;\n\t\tnhm_para.nhm_lv = NHM_LV_2;\n\t\tnhm_para.mntr_time = 262;\n\n\t\t/*@clm para*/\n\t\tclm_para.clm_app = CLM_ACS;\n\t\tclm_para.clm_lv = CLM_LV_2;\n\t\tclm_para.mntr_time = 262;\n\n\t\tset_result = phydm_env_mntr_trigger(dm, &nhm_para,\n\t\t\t\t\t\t    &clm_para, &trig_rpt);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Set Result=%d, nhm_rpt_stamp=%d, clm_rpt_stamp=%d\\n\",\n\t\t\t set_result, trig_rpt.nhm_rpt_stamp,\n\t\t\t trig_rpt.clm_rpt_stamp);\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\n"
  },
  {
    "path": "hal/phydm/phydm_ccx.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDMCCX_H__\n#define __PHYDMCCX_H__\n\n#define CCX_VERSION \"1.4\" /* @ Remove r0 chk*/\n\n/* @1 ============================================================\n * 1  Definition\n * 1 ============================================================\n */\n#define\tENV_MNTR_DBG\t0\t/*@debug for the HW processing time from NHM/CLM trigger and get result*/\n#define\tENV_MNTR_DBG_1\t0\t/*@debug 8812A & 8821A P2P Fail to get result*/\n#define\tENV_MNTR_DBG_2\t0\t/*@debug for read reister*/\n\n#define CCX_EN 1\n\n#define\tMAX_ENV_MNTR_TIME\t8\t/*second*/\n#define\tIGI_TO_NHM_TH_MULTIPLIER 2\n#define\tMS_TO_4US_RATIO\t\t250\n#define\tCCA_CAP\t\t\t14\n#define\tCLM_MAX_REPORT_TIME\t10\n#define\tDEVIDER_ERROR\t\t0xffff\n#define CLM_PERIOD_MAX\t\t65535\n#define NHM_PERIOD_MAX\t\t65534\n#define\tNHM_TH_NUM\t\t11\t/*threshold number of NHM*/\n#define\tNHM_RPT_NUM\t\t12\n#ifdef NHM_DYM_PW_TH_SUPPORT\n#define\tDYM_PWTH_CCA_CAP\t25\n#define NHM_1PEAK_PS\t\t1\t/* @case1 : positive skew*/\n#define NHM_1PEAK_NS\t\t2\t/* @case2 : negative skew*/\n#define NHM_1PEAK_SYM\t\t3\t/* @case3 : symmetry*/\n#define NHM_TH1\t\t\t33\t/* @13%, for step2 decision*/\n#define NHM_TH2\t\t\t35\t/* @14%, for step3_c1_c2 decision*/\n#define NHM_TH3\t\t\t31\t/* @12%, for step3_c3 decision*/\n#define NHM_TH4\t\t\t178\t/* @70%, for step4 decision*/\n#define NHM_TH5\t\t\t25\t/* @10%, for step5_c1_c2 decision*/\n#define NHM_TH6\t\t\t39\t/* @15%, for step5_c3 decision*/\n#endif\n\n#define\tIGI_2_NHM_TH(igi)\t((igi) << 1)/*NHM_threshold = IGI * 2*/\n#define\tNTH_TH_2_RSSI(th)\t((th >> 1) - 10)\n\n/*@FAHM*/\n#define\tFAHM_INCLD_FA\t\tBIT(0)\n#define\tFAHM_INCLD_CRC_OK\tBIT(1)\n#define\tFAHM_INCLD_CRC_ER\tBIT(2)\n\n#define NHM_SUCCESS\t\tBIT(0)\n#define CLM_SUCCESS\t\tBIT(1)\n#define FAHM_SUCCESS\t\tBIT(2)\n#define\tENV_MNTR_FAIL\t\t0xff\n\n/* @1 ============================================================\n * 1 enumrate\n * 1 ============================================================\n */\nenum phydm_clm_level {\n\tCLM_RELEASE\t\t= 0,\n\tCLM_LV_1\t\t= 1,\t/* @Low Priority function */\n\tCLM_LV_2\t\t= 2,\t/* @Middle Priority function */\n\tCLM_LV_3\t\t= 3,\t/* @High priority function (ex: Check hang function) */\n\tCLM_LV_4\t\t= 4,\t/* @Debug function (the highest priority) */\n\tCLM_MAX_NUM\t\t= 5\n};\n\nenum phydm_nhm_level {\n\tNHM_RELEASE\t\t= 0,\n\tNHM_LV_1\t\t= 1,\t/* @Low Priority function */\n\tNHM_LV_2\t\t= 2,\t/* @Middle Priority function */\n\tNHM_LV_3\t\t= 3,\t/* @High priority function (ex: Check hang function) */\n\tNHM_LV_4\t\t= 4,\t/* @Debug function (the highest priority) */\n\tNHM_MAX_NUM\t\t= 5\n};\n\nenum nhm_divider_opt_all {\n\tNHM_CNT_ALL\t\t= 0,\t/*nhm SUM report <= 255*/\n\tNHM_VALID\t\t= 1,\t/*nhm SUM report = 255*/\n\tNHM_CNT_INIT\n};\n\nenum nhm_setting {\n\tSET_NHM_SETTING,\n\tSTORE_NHM_SETTING,\n\tRESTORE_NHM_SETTING\n};\n\nenum nhm_option_cca_all {\n\tNHM_EXCLUDE_CCA\t\t= 0,\n\tNHM_INCLUDE_CCA\t\t= 1,\n\tNHM_CCA_INIT\n};\n\nenum nhm_option_txon_all {\n\tNHM_EXCLUDE_TXON\t= 0,\n\tNHM_INCLUDE_TXON\t= 1,\n\tNHM_TXON_INIT\n};\n\nenum nhm_application {\n\tNHM_BACKGROUND\t\t= 0,/*@default*/\n\tNHM_ACS\t\t\t= 1,\n\tIEEE_11K_HIGH\t\t= 2,\n\tIEEE_11K_LOW\t\t= 3,\n\tINTEL_XBOX\t\t= 4,\n\tNHM_DBG\t\t\t= 5, /*@manual trigger*/\n};\n\nenum clm_application {\n\tCLM_BACKGROUND\t\t= 0,/*@default*/\n\tCLM_ACS\t\t\t= 1,\n};\n\nenum clm_monitor_mode {\n\tCLM_DRIVER_MNTR\t\t= 1,\n\tCLM_FW_MNTR\t\t= 2\n};\n\n/* @1 ============================================================\n * 1  structure\n * 1 ============================================================\n */\nstruct env_trig_rpt {\n\tu8\t\t\tnhm_rpt_stamp;\n\tu8\t\t\tclm_rpt_stamp;\n};\n\n\nstruct env_mntr_rpt {\n\tu8\t\t\tnhm_ratio;\n\tu8\t\t\tnhm_result[NHM_RPT_NUM];\n\tu8\t\t\tclm_ratio;\n\tu8\t\t\tnhm_rpt_stamp;\n\tu8\t\t\tclm_rpt_stamp;\n};\n\nstruct nhm_para_info {\n\tenum nhm_option_txon_all\tincld_txon;\t/*@Include TX on*/\n\tenum nhm_option_cca_all\t\tincld_cca;\t/*@Include CCA*/\n\tenum nhm_divider_opt_all\tdiv_opt;\t/*@divider option*/\n\tenum nhm_application\t\tnhm_app;\n\tenum phydm_nhm_level\t\tnhm_lv;\n\tu16\t\t\t\tmntr_time;\t/*@0~262 unit ms*/\n\n};\n\nstruct clm_para_info {\n\tenum clm_application\t\tclm_app;\n\tenum phydm_clm_level\t\tclm_lv;\n\tu16\t\t\t\tmntr_time;\t/*@0~262 unit ms*/\n};\n\nstruct ccx_info {\n\tu32\t\t\tnhm_trigger_time;\n\tu32\t\t\tclm_trigger_time;\n\tu64\t\t\tstart_time;\t/*@monitor for the test duration*/\n#ifdef NHM_SUPPORT\n\tenum nhm_application\t\tnhm_app;\n\tenum nhm_option_txon_all\tnhm_include_txon;\n\tenum nhm_option_cca_all\t\tnhm_include_cca;\n\tenum nhm_divider_opt_all \tnhm_divider_opt;\n\t/*Report*/\n\tu8\t\t\tnhm_th[NHM_TH_NUM];\n\tu8\t\t\tnhm_result[NHM_RPT_NUM];\n\tu16\t\t\tnhm_period;\t/* @4us per unit */\n\tu8\t\t\tnhm_igi;\n\tu8\t\t\tnhm_manual_ctrl;\n\tu8\t\t\tnhm_ratio;\t/*@1% per nuit, it means the interference igi can't overcome.*/\n\tu8\t\t\tnhm_rpt_sum;\n\tu16\t\t\tnhm_duration;\t/*@Real time of NHM_VALID */\n\tu8\t\t\tnhm_set_lv;\n\tboolean\t\t\tnhm_ongoing;\n\tu8\t\t\tnhm_rpt_stamp;\n#ifdef NHM_DYM_PW_TH_SUPPORT\n\tboolean\t\t\tnhm_dym_pw_th_en;\n\tboolean\t\t\tnhm_dym_1_peak_en;\n\tu8\t\t\tnhm_pw_th_rf20_dft;\n\tu8\t\t\tnhm_pw_th_max;\n\tu8\t\t\tnhm_period_decre;\n\tu8\t\t\tnhm_sl_pw_th;\n#endif\n#endif\n\n#ifdef CLM_SUPPORT\n\tenum clm_application\tclm_app;\n\tu8\t\t\tclm_manual_ctrl;\n\tu8\t\t\tclm_set_lv;\n\tboolean\t\t\tclm_ongoing;\n\tu16\t\t\tclm_period;\t/* @4us per unit */\n\tu16\t\t\tclm_result;\n\tu8\t\t\tclm_ratio;\n\tu32\t\t\tclm_fw_result_acc;\n\tu8\t\t\tclm_fw_result_cnt;\n\tenum clm_monitor_mode\tclm_mntr_mode;\n\tu8\t\t\tclm_rpt_stamp;\n#endif\n#ifdef FAHM_SUPPORT\n\tboolean\t\t\tfahm_ongoing;\n\tu8\t\t\tenv_mntr_igi;\n\tu8\t\t\tfahm_nume_sel;\t/*@fahm_numerator_sel: select {FA, CRCOK, CRC_fail} */\n\tu8\t\t\tfahm_denom_sel;\t/*@fahm_denominator_sel: select {FA, CRCOK, CRC_fail} */\n\tu16\t\t\tfahm_period;\t/*unit: 4us*/\n#endif\n};\n\n/* @1 ============================================================\n * 1 Function Prototype\n * 1 ============================================================\n */\n\n#ifdef FAHM_SUPPORT\n\nvoid phydm_fahm_init(void *dm_void);\n\nvoid phydm_fahm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t    u32 *_out_len);\n\n#endif\n\n/*@NHM*/\n#ifdef NHM_SUPPORT\nvoid phydm_nhm_trigger(void *dm_void);\n\nvoid phydm_nhm_init(void *dm_void);\n\nvoid phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t   u32 *_out_len);\nu8 phydm_get_igi(void *dm_void, enum bb_path path);\n#endif\n\n/*@CLM*/\n#ifdef CLM_SUPPORT\nvoid phydm_clm_c2h_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);\n\nvoid phydm_clm_h2c(void *dm_void, u16 obs_time, u8 fw_clm_en);\n\nvoid phydm_clm_setting(void *dm_void, u16 clm_period);\n\nvoid phydm_clm_trigger(void *dm_void);\n\nboolean phydm_clm_check_rdy(void *dm_void);\n\nvoid phydm_clm_get_utility(void *dm_void);\n\nboolean phydm_clm_get_result(void *dm_void);\n\nu8 phydm_clm_mntr_set(void *dm_void, struct clm_para_info *clm_para);\n\nvoid phydm_set_clm_mntr_mode(void *dm_void, enum clm_monitor_mode mode);\n\nvoid phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t   u32 *_out_len);\n#endif\n\nu8 phydm_env_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para,\n\t\t\t  struct clm_para_info *clm_para,\n\t\t\t  struct env_trig_rpt *rpt);\n\nu8 phydm_env_mntr_result(void *dm_void, struct env_mntr_rpt *rpt);\n\nvoid phydm_env_mntr_watchdog(void *dm_void);\n\nvoid phydm_env_monitor_init(void *dm_void);\n\nvoid phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used,\n\t\t\tchar *output, u32 *_out_len);\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_cfotracking.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\ns32 phydm_get_cfo_hz(void *dm_void, u32 val, u8 bit_num, u8 frac_num)\n{\n\ts32 val_s = 0;\n\n\tval_s = phydm_cnvrt_2_sign(val, bit_num);\n\n\tif (frac_num == 10) /*@ (X*312500)/1024 ~= X*305*/\n\t\tval_s *= 305;\n\telse if (frac_num == 11) /*@ (X*312500)/2048 ~= X*152*/\n\t\tval_s *= 152;\n\telse if (frac_num == 12) /*@ (X*312500)/4096 ~= X*76*/\n\t\tval_s *= 76;\n\n\treturn val_s;\n}\n\n#if (ODM_IC_11AC_SERIES_SUPPORT)\nvoid phydm_get_cfo_info_ac(void *dm_void, struct phydm_cfo_rpt *cfo)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i = 0;\n\tu32 val[4] = {0};\n\tu32 val_1[4] = {0};\n\tu32 val_2[4] = {0};\n\tu32 val_tmp = 0;\n\n\tval[0] = odm_read_4byte(dm, R_0xd0c);\n\tval_1[0] = odm_read_4byte(dm, R_0xd10);\n\tval_2[0] = odm_get_bb_reg(dm, R_0xd14, 0x1fff0000);\n\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tval[1] = odm_read_4byte(dm, R_0xd4c);\n\tval_1[1] = odm_read_4byte(dm, R_0xd50);\n\tval_2[1] = odm_get_bb_reg(dm, R_0xd54, 0x1fff0000);\n\t#endif\n\n\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\tval[2] = odm_read_4byte(dm, R_0xd8c);\n\tval_1[2] = odm_read_4byte(dm, R_0xd90);\n\tval_2[2] = odm_get_bb_reg(dm, R_0xd94, 0x1fff0000);\n\t#endif\n\n\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\tval[3] = odm_read_4byte(dm, R_0xdcc);\n\tval_1[3] = odm_read_4byte(dm, R_0xdd0);\n\tval_2[3] = odm_get_bb_reg(dm, R_0xdd4, 0x1fff0000);\n\t#endif\n\n\tfor (i = 0; i < dm->num_rf_path; i++) {\n\t\tval_tmp = val[i] & 0xfff;\t/*@ Short CFO, S(12,11)*/\n\t\tcfo->cfo_rpt_s[i] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);\n\n\t\tval_tmp = val[i] >> 16;\t\t/*@ Long CFO, S(13,12)*/\n\t\tcfo->cfo_rpt_l[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);\n\n\t\tval_tmp = val_1[i] & 0x7ff;\t/*@ SCFO, S(11,10)*/\n\t\tcfo->cfo_rpt_sec[i] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);\n\n\t\tval_tmp = val_1[i] >> 16;\t/*@ Acq CFO, S(13,12)*/\n\t\tcfo->cfo_rpt_acq[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);\n\n\t\tval_tmp = val_2[i];\t\t/*@ End CFO, S(13,12)*/\n\t\tcfo->cfo_rpt_end[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);\n\t}\n}\n#endif\n\n#if (ODM_IC_11N_SERIES_SUPPORT)\nvoid phydm_get_cfo_info_n(void *dm_void, struct phydm_cfo_rpt *cfo)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 val[5] = {0};\n\tu32 val_tmp = 0;\n\n\todm_set_bb_reg(dm, R_0xd00, BIT(26), 1);\n\n\tval[0] = odm_read_4byte(dm, R_0xdac); /*@ Short CFO*/\n\tval[1] = odm_read_4byte(dm, R_0xdb0); /*@ Long CFO*/\n\tval[2] = odm_read_4byte(dm, R_0xdb8); /*@ Sec CFO*/\n\tval[3] = odm_read_4byte(dm, R_0xde0); /*@ Acq CFO*/\n\tval[4] = odm_read_4byte(dm, R_0xdbc); /*@ End CFO*/\n\n\t/*@[path-A]*/\n\tif (dm->support_ic_type == ODM_RTL8721D) {\n\t\tval_tmp = (val[0] & 0x0fff0000) >> 16; /*@ Short CFO, S(12,11)*/\n\t\tcfo->cfo_rpt_s[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);\n\t\tval_tmp = (val[1] & 0x0fff0000) >> 16;\t/*@ Long CFO, S(12,11)*/\n\t\tcfo->cfo_rpt_l[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);\n\t\tval_tmp = (val[2] & 0x0fff0000) >> 16;\t/*@ Sec CFO, S(12,11)*/\n\t\tcfo->cfo_rpt_sec[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);\n\t\tval_tmp = (val[3] & 0x0fff0000) >> 16;\t/*@ Acq CFO, S(12,11)*/\n\t\tcfo->cfo_rpt_acq[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);\n\t\tval_tmp = (val[4] & 0x0fff0000) >> 16;\t/*@ Acq CFO, S(12,11)*/\n\t\tcfo->cfo_rpt_end[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);\n\t} else {\n\t\tval_tmp = (val[0] & 0x0fff0000) >> 16; /*@ Short CFO, S(12,11)*/\n\t\tcfo->cfo_rpt_s[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);\n\t\tval_tmp = (val[1] & 0x1fff0000) >> 16;\t/*@ Long CFO, S(13,12)*/\n\t\tcfo->cfo_rpt_l[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);\n\t\tval_tmp = (val[2] & 0x7ff0000) >> 16;\t/*@ Sec CFO, S(11,10)*/\n\t\tcfo->cfo_rpt_sec[0] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);\n\t\tval_tmp = (val[3] & 0x1fff0000) >> 16;\t/*@ Acq CFO, S(13,12)*/\n\t\tcfo->cfo_rpt_acq[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);\n\t\tval_tmp = (val[4] & 0x1fff0000) >> 16;\t/*@ Acq CFO, S(13,12)*/\n\t\tcfo->cfo_rpt_end[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);\n\t}\n\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\t/*@[path-B]*/\n\tval_tmp = val[0] & 0xfff;\t\t/*@ Short CFO, S(12,11)*/\n\tcfo->cfo_rpt_s[1] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);\n\tval_tmp = val[1] & 0x1fff;\t\t/*@ Long CFO, S(13,12)*/\n\tcfo->cfo_rpt_l[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);\n\tval_tmp = val[2] & 0x7ff;\t\t/*@ Sec CFO, S(11,10)*/\n\tcfo->cfo_rpt_sec[1] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);\n\tval_tmp = val[3] & 0x1fff;\t\t/*@ Acq CFO, S(13,12)*/\n\tcfo->cfo_rpt_acq[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);\n\tval_tmp = val[4] & 0x1fff;\t\t/*@ Acq CFO, S(13,12)*/\n\tcfo->cfo_rpt_end[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);\n\t#endif\n}\n\nvoid phydm_set_atc_status(void *dm_void, boolean atc_status)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;\n\tu32 reg_tmp = 0;\n\tu32 mask_tmp = 0;\n\n\tPHYDM_DBG(dm, DBG_CFO_TRK, \"[%s]ATC_en=%d\\n\", __func__, atc_status);\n\n\tif (cfo_track->is_atc_status == atc_status)\n\t\treturn;\n\n\treg_tmp = ODM_REG(BB_ATC, dm);\n\tmask_tmp = ODM_BIT(BB_ATC, dm);\n\todm_set_bb_reg(dm, reg_tmp, mask_tmp, atc_status);\n\tcfo_track->is_atc_status = atc_status;\n}\n\nboolean\nphydm_get_atc_status(void *dm_void)\n{\n\tboolean atc_status = false;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 reg_tmp = 0;\n\tu32 mask_tmp = 0;\n\n\treg_tmp = ODM_REG(BB_ATC, dm);\n\tmask_tmp = ODM_BIT(BB_ATC, dm);\n\n\tatc_status = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);\n\n\tPHYDM_DBG(dm, DBG_CFO_TRK, \"[%s]atc_status=%d\\n\", __func__, atc_status);\n\treturn atc_status;\n}\n#endif\n\nvoid phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tswitch (dm->ic_ip_series) {\n\t#if (ODM_IC_11N_SERIES_SUPPORT)\n\tcase PHYDM_IC_N:\n\t\tphydm_get_cfo_info_n(dm, cfo);\n\t\tbreak;\n\t#endif\n\t#if (ODM_IC_11AC_SERIES_SUPPORT)\n\tcase PHYDM_IC_AC:\n\t\tphydm_get_cfo_info_ac(dm, cfo);\n\t\tbreak;\n\t#endif\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nboolean\nphydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;\n\tu32 reg_val = 0;\n\n\tif (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |\n\t    ODM_RTL8195B | ODM_RTL8812F | ODM_RTL8197G | ODM_RTL8721D)) {\n\t\tcrystal_cap &= 0x7F;\n\t\treg_val = crystal_cap | (crystal_cap << 7);\n\t} else {\n\t\tcrystal_cap &= 0x3F;\n\t\treg_val = crystal_cap | (crystal_cap << 6);\n\t}\n\n\tcfo_track->crystal_cap = crystal_cap;\n\n\tif (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) {\n\t\t#if (RTL8188E_SUPPORT || RTL8188F_SUPPORT)\n\t\t/* write 0x24[22:17] = 0x24[16:11] = crystal_cap */\n\t\todm_set_mac_reg(dm, R_0x24, 0x7ff800, reg_val);\n\t\t#endif\n\t}\n\t#if (RTL8812A_SUPPORT)\n\telse if (dm->support_ic_type & ODM_RTL8812) {\n\t\t/* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */\n\t\todm_set_mac_reg(dm, R_0x2c, 0x7FF80000, reg_val);\n\t}\n\t#endif\n\t#if (RTL8703B_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\\\n\t     RTL8821A_SUPPORT || RTL8723D_SUPPORT)\n\telse if ((dm->support_ic_type &\n\t\t (ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8192E | ODM_RTL8821 |\n\t\t ODM_RTL8723D))) {\n\t\t/* @0x2C[23:18] = 0x2C[17:12] = crystal_cap */\n\t\todm_set_mac_reg(dm, R_0x2c, 0x00FFF000, reg_val);\n\t}\n\t#endif\n\t#if (RTL8814A_SUPPORT)\n\telse if (dm->support_ic_type & ODM_RTL8814A) {\n\t\t/* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */\n\t\todm_set_mac_reg(dm, R_0x2c, 0x07FF8000, reg_val);\n\t}\n\t#endif\n\t#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8197F_SUPPORT ||\\\n\t     RTL8192F_SUPPORT)\n\telse if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C |\n\t\t ODM_RTL8197F | ODM_RTL8192F)) {\n\t\t/* write 0x24[30:25] = 0x28[6:1] = crystal_cap */\n\t\todm_set_mac_reg(dm, R_0x24, 0x7e000000, crystal_cap);\n\t\todm_set_mac_reg(dm, R_0x28, 0x7e, crystal_cap);\n\t}\n\t#endif\n\t#if (RTL8710B_SUPPORT)\n\telse if (dm->support_ic_type & (ODM_RTL8710B)) {\n\t\t#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\t\t/* write 0x60[29:24] = 0x60[23:18] = crystal_cap */\n\t\tHAL_SetSYSOnReg(dm->adapter, R_0x60, 0x3FFC0000, reg_val);\n\t\t#endif\n\t}\n\t#endif\n\t#if (RTL8195B_SUPPORT)\n\telse if (dm->support_ic_type & ODM_RTL8195B) {\n\t\tphydm_set_crystalcap(dm, (u8)(reg_val & 0x7f));\n\t}\n\t#endif\n\t#if (RTL8721D_SUPPORT)\n\telse if (dm->support_ic_type & (ODM_RTL8721D)) {\n\t\t/* write 0x4800_0228[30:24] crystal_cap */\n\t\t/*HAL_SetSYSOnReg(dm->adapter, */\n\t\t/*REG_SYS_XTAL_8721d, 0x7F000000, crystal_cap);*/\n\t\tu32 temp_val = HAL_READ32(SYSTEM_CTRL_BASE_LP,\n\t\t\t\t\t   REG_SYS_EFUSE_SYSCFG2);\n\t\ttemp_val = ((crystal_cap << 24) & 0x7F000000)\n\t\t\t\t\t\t| (temp_val & (~0x7F000000));\n\t\tHAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_SYS_EFUSE_SYSCFG2,\n\t\t\t    temp_val);\n\t}\n\t#endif\n#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\\\n\tRTL8197G_SUPPORT)\n\telse if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |\n\t\t ODM_RTL8812F | ODM_RTL8197G)) {\n\t\t/* write 0x1040[23:17] = 0x1040[16:10] = crystal_cap */\n\t\todm_set_mac_reg(dm, R_0x1040, 0x00FFFC00, reg_val);\n\t} else {\n\t\treturn false;\n\t}\n#endif\n\treturn true;\n}\n\nvoid phydm_set_crystal_cap(void *dm_void, u8 crystal_cap)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;\n\n\tif (cfo_track->crystal_cap == crystal_cap)\n\t\treturn;\n\n\tif (phydm_set_crystal_cap_reg(dm, crystal_cap))\n\t\tPHYDM_DBG(dm, DBG_CFO_TRK, \"Set crystal_cap = 0x%x\\n\",\n\t\t\t  cfo_track->crystal_cap);\n\telse\n\t\tPHYDM_DBG(dm, DBG_CFO_TRK, \"Set fail\\n\");\n}\n\nvoid phydm_cfo_tracking_reset(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;\n\n\tPHYDM_DBG(dm, DBG_CFO_TRK, \"%s ======>\\n\", __func__);\n\n\tif (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8195B |\n\t    ODM_RTL8812F | ODM_RTL8197G))\n\t\tcfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x7f;\n\telse\n\t\tcfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x3f;\n\n\tcfo_track->is_adjust = true;\n\n\tif (cfo_track->crystal_cap > cfo_track->def_x_cap) {\n\t\tphydm_set_crystal_cap(dm, cfo_track->crystal_cap - 1);\n\t\tPHYDM_DBG(dm, DBG_CFO_TRK, \"approch to Init-val (0x%x)\\n\",\n\t\t\t  cfo_track->crystal_cap);\n\n\t} else if (cfo_track->crystal_cap < cfo_track->def_x_cap) {\n\t\tphydm_set_crystal_cap(dm, cfo_track->crystal_cap + 1);\n\t\tPHYDM_DBG(dm, DBG_CFO_TRK, \"approch to init-val 0x%x\\n\",\n\t\t\t  cfo_track->crystal_cap);\n\t}\n\n#if ODM_IC_11N_SERIES_SUPPORT\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\tif (dm->support_ic_type & ODM_IC_11N_SERIES)\n\t\tphydm_set_atc_status(dm, true);\n#endif\n#endif\n}\n\nvoid phydm_cfo_tracking_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;\n\n\tPHYDM_DBG(dm, DBG_CFO_TRK, \"[%s]=========>\\n\", __func__);\n\tif (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8195B |\n\t    ODM_RTL8812F | ODM_RTL8197G))\n\t\tcfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x7f;\n\telse\n\t\tcfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x3f;\n\n\tcfo_track->def_x_cap = cfo_track->crystal_cap;\n\tcfo_track->is_adjust = true;\n\tPHYDM_DBG(dm, DBG_CFO_TRK, \"crystal_cap=0x%x\\n\", cfo_track->def_x_cap);\n\n#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)\n\t/* @Crystal cap. control by WiFi */\n\tif (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C))\n\t\todm_set_mac_reg(dm, R_0x10, 0x40, 0x1);\n#endif\n}\n\nvoid phydm_cfo_tracking(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;\n\ts32 cfo_avg = 0, cfo_path_sum = 0, cfo_abs = 0;\n\tu32 cfo_rpt_sum = 0, cfo_khz_avg[4] = {0};\n\ts8 crystal_cap = cfo_track->crystal_cap;\n\tu8 i = 0, valid_path_cnt = 0;\n\n\tif (!(dm->support_ability & ODM_BB_CFO_TRACKING))\n\t\treturn;\n\n\tPHYDM_DBG(dm, DBG_CFO_TRK, \"%s ======>\\n\", __func__);\n\n\tif (!dm->is_linked || !dm->is_one_entry_only) {\n\t\tphydm_cfo_tracking_reset(dm);\n\t\tPHYDM_DBG(dm, DBG_CFO_TRK, \"is_linked=%d, one_entry_only=%d\\n\",\n\t\t\t  dm->is_linked, dm->is_one_entry_only);\n\n\t} else {\n\t\t/* No new packet */\n\t\tif (cfo_track->packet_count == cfo_track->packet_count_pre) {\n\t\t\tPHYDM_DBG(dm, DBG_CFO_TRK, \"Pkt cnt doesn't change\\n\");\n\t\t\treturn;\n\t\t}\n\t\tcfo_track->packet_count_pre = cfo_track->packet_count;\n\n\t\t/*@Calculate CFO */\n\t\tfor (i = 0; i < dm->num_rf_path; i++) {\n\t\t\tif (!(dm->rx_ant_status & BIT(i)))\n\t\t\t\tcontinue;\n\n\t\t\tvalid_path_cnt++;\n\n\t\t\tif (cfo_track->CFO_tail[i] < 0)\n\t\t\t\tcfo_abs = 0 - cfo_track->CFO_tail[i];\n\t\t\telse\n\t\t\t\tcfo_abs = cfo_track->CFO_tail[i];\n\n\t\t\tcfo_rpt_sum = (u32)CFO_HW_RPT_2_KHZ(cfo_abs);\n\t\t\tcfo_khz_avg[i] = PHYDM_DIV(cfo_rpt_sum,\n\t\t\t\t\t\t   cfo_track->CFO_cnt[i]);\n\n\t\t\tPHYDM_DBG(dm, DBG_CFO_TRK,\n\t\t\t\t  \"[Path-%d] CFO_sum=((%d)), cnt=((%d)), CFO_avg=((%s%d))kHz\\n\",\n\t\t\t\t  i, cfo_rpt_sum, cfo_track->CFO_cnt[i],\n\t\t\t\t  ((cfo_track->CFO_tail[i] < 0) ? \"-\" : \" \"),\n\t\t\t\t  cfo_khz_avg[i]);\n\n\t\t\tif (cfo_track->CFO_tail[i] < 0)\n\t\t\t\tcfo_path_sum += (0 - (s32)cfo_khz_avg[i]);\n\t\t\telse\n\t\t\t\tcfo_path_sum += (s32)cfo_khz_avg[i];\n\t\t}\n\n\t\tif (valid_path_cnt >= 2)\n\t\t\tcfo_avg = cfo_path_sum / valid_path_cnt;\n\t\telse\n\t\t\tcfo_avg = cfo_path_sum;\n\n\t\tcfo_track->CFO_ave_pre = cfo_avg;\n\n\t\tPHYDM_DBG(dm, DBG_CFO_TRK, \"path_cnt=%d, CFO_avg_path=%d kHz\\n\",\n\t\t\t  valid_path_cnt, cfo_avg);\n\n\t\t/*reset counter*/\n\t\tfor (i = 0; i < dm->num_rf_path; i++) {\n\t\t\tcfo_track->CFO_tail[i] = 0;\n\t\t\tcfo_track->CFO_cnt[i] = 0;\n\t\t}\n\n\t\t/* To adjust crystal cap or not */\n\t\tif (!cfo_track->is_adjust) {\n\t\t\tif (cfo_avg > CFO_TRK_ENABLE_TH ||\n\t\t\t    cfo_avg < (-CFO_TRK_ENABLE_TH))\n\t\t\t\tcfo_track->is_adjust = true;\n\t\t} else {\n\t\t\tif (cfo_avg < CFO_TRK_STOP_TH &&\n\t\t\t    cfo_avg > (-CFO_TRK_STOP_TH))\n\t\t\t\tcfo_track->is_adjust = false;\n\t\t}\n\n\t\t#ifdef ODM_CONFIG_BT_COEXIST\n\t\t/*@BT case: Disable CFO tracking */\n\t\tif (dm->bt_info_table.is_bt_enabled) {\n\t\t\tcfo_track->is_adjust = false;\n\t\t\tphydm_set_crystal_cap(dm, cfo_track->def_x_cap);\n\t\t\tPHYDM_DBG(dm, DBG_CFO_TRK, \"[BT]Disable CFO_track\\n\");\n\t\t}\n\t\t#endif\n\n\t\t/*@Adjust Crystal Cap. */\n\t\tif (cfo_track->is_adjust) {\n\t\t\tif (cfo_avg > CFO_TRK_STOP_TH)\n\t\t\t\tcrystal_cap += 1;\n\t\t\telse if (cfo_avg < (-CFO_TRK_STOP_TH))\n\t\t\t\tcrystal_cap -= 1;\n\n\t\t\tif (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |\n\t\t\t    ODM_RTL8195B | ODM_RTL8812F | ODM_RTL8197G)) {\n\t\t\t\tif (crystal_cap > 0x7F)\n\t\t\t\t\tcrystal_cap = 0x7F;\n\t\t\t} else {\n\t\t\t\tif (crystal_cap > 0x3F)\n\t\t\t\t\tcrystal_cap = 0x3F;\n\t\t\t}\n\t\t\tif (crystal_cap < 0)\n\t\t\t\tcrystal_cap = 0;\n\n\t\t\tphydm_set_crystal_cap(dm, (u8)crystal_cap);\n\t\t}\n\n\t\tPHYDM_DBG(dm, DBG_CFO_TRK, \"X_cap{Curr,Default}={0x%x,0x%x}\\n\",\n\t\t\t  cfo_track->crystal_cap, cfo_track->def_x_cap);\n\n\t\t/* @Dynamic ATC switch */\n\t\t#if ODM_IC_11N_SERIES_SUPPORT\n\t\t#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\t\tif (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\t\tif (cfo_avg < CFO_TH_ATC && cfo_avg > -CFO_TH_ATC)\n\t\t\t\tphydm_set_atc_status(dm, false);\n\t\t\telse\n\t\t\t\tphydm_set_atc_status(dm, true);\n\n\t\t}\n\t\t#endif\n\t\t#endif\n\t}\n}\n\nvoid phydm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail,\n\t\t       u8 num_ss)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_perpkt_info_struct *pktinfo = NULL;\n\tstruct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;\n\tboolean valid_info = false;\n\tu8 i = 0;\n\n\tif (!(dm->support_ability & ODM_BB_CFO_TRACKING))\n\t\treturn;\n\n\tpktinfo = (struct phydm_perpkt_info_struct *)pktinfo_void;\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))\n\tif (pktinfo->is_packet_match_bssid)\n\t\tvalid_info = true;\n#else\n\tif (dm->number_active_client == 1)\n\t\tvalid_info = true;\n#endif\n\tif (valid_info) {\n\t\tif (num_ss > dm->num_rf_path) /*@For fool proof*/\n\t\t\tnum_ss = dm->num_rf_path;\n\t\t#if 0\n\t\tPHYDM_DBG(dm, DBG_CFO_TRK, \"num_ss=%d, num_rf_path=%d\\n\",\n\t\t\t  num_ss, dm->num_rf_path);\n\t\t#endif\n\n\t\t/* @ Update CFO report for path-A & path-B */\n\t\t/* Only paht-A and path-B have CFO tail and short CFO */\n\t\tfor (i = 0; i < dm->num_rf_path; i++) {\n\t\t\tif (!(dm->rx_ant_status & BIT(i)))\n\t\t\t\tcontinue;\n\t\t\tcfo_track->CFO_tail[i] += pcfotail[i];\n\t\t\tcfo_track->CFO_cnt[i]++;\n\t\t\t#if 0\n\t\t\tPHYDM_DBG(dm, DBG_CFO_TRK,\n\t\t\t\t  \"[ID %d][path %d][rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\\n\",\n\t\t\t\t  pktinfo->station_id, i, pktinfo->data_rate,\n\t\t\t\t  pcfotail[i], cfo_track->CFO_tail[i],\n\t\t\t\t  cfo_track->CFO_cnt[i]);\n\t\t\t#endif\n\t\t}\n\n\t\t/* @ Update packet counter */\n\t\tif (cfo_track->packet_count == 0xffffffff)\n\t\t\tcfo_track->packet_count = 0;\n\t\telse\n\t\t\tcfo_track->packet_count++;\n\t}\n}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid phy_Init_crystal_capacity(void *dm_void, u8 crystal_cap)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (!phydm_set_crystal_cap_reg(dm, crystal_cap))\n\t\tRT_TRACE_F(COMP_INIT, DBG_SERIOUS,\n\t\t\t   (\"Crystal is not initialized!\\n\"));\n}\n#endif\n\nvoid phydm_cfo_tracking_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t\t      char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;\n\tchar help[] = \"-h\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"set Xcap: {1}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"show Xcap: {100}\\n\");\n\t} else {\n\t\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);\n\n\t\tif (var1[0] == 1) {\n\t\t\tPHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);\n\t\t\tphydm_set_crystal_cap(dm, (u8)var1[1]);\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"Set X_cap=0x%x\\n\", cfo_track->crystal_cap);\n\t\t} else if (var1[0] == 100) {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"X_cap=0x%x\\n\", cfo_track->crystal_cap);\n\t\t}\n\t}\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\n"
  },
  {
    "path": "hal/phydm/phydm_cfotracking.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDMCFOTRACK_H__\n#define __PHYDMCFOTRACK_H__\n\n#define CFO_TRACKING_VERSION \"2.3\"\n\n#define\t\tCFO_TRK_ENABLE_TH\t20 /* @kHz enable CFO_Track threshold*/\n#define\t\tCFO_TRK_STOP_TH\t\t10 /* @kHz disable CFO_Track threshold*/\n#define\t\tCFO_TH_ATC\t\t80 /* @kHz */\n\nstruct phydm_cfo_track_struct {\n\tboolean\t\tis_atc_status;\n\tboolean\t\tis_adjust;\t/*@already modify crystal cap*/\n\tu8\t\tcrystal_cap;\n\tu8\t\tcrystal_cap_default;\n\tu8\t\tdef_x_cap;\n\ts32\t\tCFO_tail[4];\n\tu32\t\tCFO_cnt[4];\n\ts32\t\tCFO_ave_pre;\n\tu32\t\tpacket_count;\n\tu32\t\tpacket_count_pre;\n};\n\nstruct phydm_cfo_rpt {\n\ts32 cfo_rpt_s[PHYDM_MAX_RF_PATH];\n\ts32 cfo_rpt_l[PHYDM_MAX_RF_PATH];\n\ts32 cfo_rpt_acq[PHYDM_MAX_RF_PATH];\n\ts32 cfo_rpt_sec[PHYDM_MAX_RF_PATH];\n\ts32 cfo_rpt_end[PHYDM_MAX_RF_PATH];\n};\n\nvoid phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo);\n\nboolean phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap);\n\nvoid phydm_set_crystal_cap(void *dm_void, u8 crystal_cap);\n\nvoid phydm_cfo_tracking_init(void *dm_void);\n\nvoid phydm_cfo_tracking(void *dm_void);\n\nvoid phydm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail,\n\t\t       u8 num_ss);\nvoid phydm_cfo_tracking_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t\t      char *output, u32 *_out_len);\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid phy_Init_crystal_capacity(void *dm_void, u8 crystal_cap);\n#endif\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_debug.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n ************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\nvoid phydm_init_debug_setting(struct dm_struct *dm)\n{\n\tdm->fw_debug_components = 0;\n\tdm->debug_components =\n\n#if DBG\n\t/*@BB Functions*/\n\t/*@DBG_DIG\t\t\t\t\t|*/\n\t/*@DBG_RA_MASK\t\t\t\t\t|*/\n\t/*@DBG_DYN_TXPWR\t\t\t\t|*/\n\t/*@DBG_FA_CNT\t\t\t\t\t|*/\n\t/*@DBG_RSSI_MNTR\t\t\t\t|*/\n\t/*@DBG_CCKPD\t\t\t\t\t|*/\n\t/*@DBG_ANT_DIV\t\t\t\t\t|*/\n\t/*@DBG_SMT_ANT\t\t\t\t\t|*/\n\t/*@DBG_PWR_TRAIN\t\t\t\t|*/\n\t/*@DBG_RA\t\t\t\t\t|*/\n\t/*@DBG_PATH_DIV\t\t\t\t\t|*/\n\t/*@DBG_DFS\t\t\t\t\t|*/\n\t/*@DBG_DYN_ARFR\t\t\t\t\t|*/\n\t/*@DBG_ADPTVTY\t\t\t\t\t|*/\n\t/*@DBG_CFO_TRK\t\t\t\t\t|*/\n\t/*@DBG_ENV_MNTR\t\t\t\t\t|*/\n\t/*@DBG_PRI_CCA\t\t\t\t\t|*/\n\t/*@DBG_ADPTV_SOML\t\t\t\t|*/\n\t/*@DBG_LNA_SAT_CHK\t\t\t\t|*/\n\t/*@DBG_PHY_STATUS\t\t\t\t|*/\n\t/*@DBG_TMP\t\t\t\t\t|*/\n\t/*@DBG_FW_TRACE\t\t\t\t\t|*/\n\t/*@DBG_TXBF\t\t\t\t\t|*/\n\t/*@DBG_COMMON_FLOW\t\t\t\t|*/\n\t/*@ODM_PHY_CONFIG\t\t\t\t|*/\n\t/*@ODM_COMP_INIT\t\t\t\t|*/\n\t/*@DBG_CMN\t\t\t\t\t|*/\n\t/*@ODM_COMP_API\t\t\t\t\t|*/\n#endif\n\t0;\n\n\tdm->fw_buff_is_enpty = true;\n\tdm->pre_c2h_seq = 0;\n\tdm->c2h_cmd_start = 0;\n\tdm->cmn_dbg_msg_cnt = PHYDM_WATCH_DOG_PERIOD;\n\tdm->cmn_dbg_msg_period = PHYDM_WATCH_DOG_PERIOD;\n\tphydm_reset_rx_rate_distribution(dm);\n}\n\nvoid phydm_bb_dbg_port_header_sel(void *dm_void, u32 header_idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\todm_set_bb_reg(dm, R_0x8f8, 0x3c00000, header_idx);\n\n\t\t/*@\n\t\t * header_idx:\n\t\t *\t(0:) '{ofdm_dbg[31:0]}'\n\t\t *\t(1:) '{cca,crc32_fail,dbg_ofdm[29:0]}'\n\t\t *\t(2:) '{vbon,crc32_fail,dbg_ofdm[29:0]}'\n\t\t *\t(3:) '{cca,crc32_ok,dbg_ofdm[29:0]}'\n\t\t *\t(4:) '{vbon,crc32_ok,dbg_ofdm[29:0]}'\n\t\t *\t(5:) '{dbg_iqk_anta}'\n\t\t *\t(6:) '{cca,ofdm_crc_ok,dbg_dp_anta[29:0]}'\n\t\t *\t(7:) '{dbg_iqk_antb}'\n\t\t *\t(8:) '{DBGOUT_RFC_b[31:0]}'\n\t\t *\t(9:) '{DBGOUT_RFC_a[31:0]}'\n\t\t *\t(a:) '{dbg_ofdm}'\n\t\t *\t(b:) '{dbg_cck}'\n\t\t */\n\t}\n}\n\nvoid phydm_bb_dbg_port_clock_en(void *dm_void, u8 enable)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 reg_value = 0;\n\n\tif (dm->support_ic_type &\n\t    (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814A | ODM_RTL8814B |\n\t    ODM_RTL8195B)) {\n\t\t/*@enable/disable debug port clock, for power saving*/\n\t\treg_value = enable ? 0x7 : 0;\n\t\todm_set_bb_reg(dm, R_0x198c, 0x7, reg_value);\n\t}\n}\n\nu32 phydm_get_bb_dbg_port_idx(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 val = 0;\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\tphydm_bb_dbg_port_clock_en(dm, true);\n\t\tval = odm_get_bb_reg(dm, R_0x8fc, MASKDWORD);\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tval = odm_get_bb_reg(dm, R_0x1c3c, 0xfff00);\n\t} else { /*@if (dm->support_ic_type & ODM_IC_11N_SERIES)*/\n\t\tval = odm_get_bb_reg(dm, R_0x908, MASKDWORD);\n\t}\n\treturn val;\n}\n\nu8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 dbg_port_result = false;\n\n\tif (curr_dbg_priority > dm->pre_dbg_priority) {\n\t\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\t\tphydm_bb_dbg_port_clock_en(dm, true);\n\n\t\t\todm_set_bb_reg(dm, R_0x8fc, MASKDWORD, debug_port);\n\t\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t\todm_set_bb_reg(dm, R_0x1c3c, 0xfff00, debug_port);\n\n\t\t} else { /*@if (dm->support_ic_type & ODM_IC_11N_SERIES)*/\n\t\t\todm_set_bb_reg(dm, R_0x908, MASKDWORD, debug_port);\n\t\t}\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"DbgPort ((0x%x)) set success, Cur_priority=((%d)), Pre_priority=((%d))\\n\",\n\t\t\t  debug_port, curr_dbg_priority, dm->pre_dbg_priority);\n\t\tdm->pre_dbg_priority = curr_dbg_priority;\n\t\tdbg_port_result = true;\n\t}\n\n\treturn dbg_port_result;\n}\n\nvoid phydm_release_bb_dbg_port(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tphydm_bb_dbg_port_clock_en(dm, false);\n\tphydm_bb_dbg_port_header_sel(dm, 0);\n\n\tdm->pre_dbg_priority = DBGPORT_RELEASE;\n\tPHYDM_DBG(dm, ODM_COMP_API, \"Release BB dbg_port\\n\");\n}\n\nu32 phydm_get_bb_dbg_port_val(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 dbg_port_value = 0;\n\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES)\n\t\tdbg_port_value = odm_get_bb_reg(dm, R_0xfa0, MASKDWORD);\n\telse if (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tdbg_port_value = odm_get_bb_reg(dm, R_0x2dbc, MASKDWORD);\n\telse /*@if (dm->support_ic_type & ODM_IC_11N_SERIES)*/\n\t\tdbg_port_value = odm_get_bb_reg(dm, R_0xdf4, MASKDWORD);\n\n\tPHYDM_DBG(dm, ODM_COMP_API, \"dbg_port_value = 0x%x\\n\", dbg_port_value);\n\treturn dbg_port_value;\n}\n\n#ifdef CONFIG_PHYDM_DEBUG_FUNCTION\n#if (ODM_IC_11N_SERIES_SUPPORT)\nvoid phydm_bb_hw_dbg_info_n(void *dm_void, u32 *_used, char *output,\n\t\t\t    u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 value32 = 0, value32_1 = 0;\n\tu8 rf_gain_a = 0, rf_gain_b = 0, rf_gain_c = 0, rf_gain_d = 0;\n\tu8 rx_snr_a = 0, rx_snr_b = 0, rx_snr_c = 0, rx_snr_d = 0;\n\ts8 rxevm_0 = 0, rxevm_1 = 0;\n\t#if 1\n\tstruct phydm_cfo_rpt cfo;\n\tu8 i = 0;\n\t#else\n\ts32 short_cfo_a = 0, short_cfo_b = 0, long_cfo_a = 0, long_cfo_b = 0;\n\ts32 scfo_a = 0, scfo_b = 0, avg_cfo_a = 0, avg_cfo_b = 0;\n\ts32 cfo_end_a = 0, cfo_end_b = 0, acq_cfo_a = 0, acq_cfo_b = 0;\n\t#endif\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"\\r\\n %-35s\\n\",\n\t\t \"BB Report Info\");\n\n\t/*@AGC result*/\n\tvalue32 = odm_get_bb_reg(dm, R_0xdd0, MASKDWORD);\n\trf_gain_a = (u8)(value32 & 0x3f);\n\trf_gain_a = rf_gain_a << 1;\n\n\trf_gain_b = (u8)((value32 >> 8) & 0x3f);\n\trf_gain_b = rf_gain_b << 1;\n\n\trf_gain_c = (u8)((value32 >> 16) & 0x3f);\n\trf_gain_c = rf_gain_c << 1;\n\n\trf_gain_d = (u8)((value32 >> 24) & 0x3f);\n\trf_gain_d = rf_gain_d << 1;\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d / %d / %d\", \"OFDM RX RF Gain(A/B/C/D)\",\n\t\t rf_gain_a, rf_gain_b, rf_gain_c, rf_gain_d);\n\n\t/*SNR report*/\n\tvalue32 = odm_get_bb_reg(dm, R_0xdd4, MASKDWORD);\n\trx_snr_a = (u8)(value32 & 0xff);\n\trx_snr_a = rx_snr_a >> 1;\n\n\trx_snr_b = (u8)((value32 >> 8) & 0xff);\n\trx_snr_b = rx_snr_b >> 1;\n\n\trx_snr_c = (u8)((value32 >> 16) & 0xff);\n\trx_snr_c = rx_snr_c >> 1;\n\n\trx_snr_d = (u8)((value32 >> 24) & 0xff);\n\trx_snr_d = rx_snr_d >> 1;\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d / %d / %d\", \"RXSNR(A/B/C/D, dB)\",\n\t\t rx_snr_a, rx_snr_b, rx_snr_c, rx_snr_d);\n\n\t/* PostFFT related info*/\n\tvalue32 = odm_get_bb_reg(dm, R_0xdd8, MASKDWORD);\n\n\trxevm_0 = (s8)((value32 & MASKBYTE2) >> 16);\n\trxevm_0 /= 2;\n\tif (rxevm_0 < -63)\n\t\trxevm_0 = 0;\n\n\trxevm_1 = (s8)((value32 & MASKBYTE3) >> 24);\n\trxevm_1 /= 2;\n\tif (rxevm_1 < -63)\n\t\trxevm_1 = 0;\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d\", \"RXEVM (1ss/2ss)\", rxevm_0, rxevm_1);\n\n#if 1\n\tphydm_get_cfo_info(dm, &cfo);\n\tfor (i = 0; i < dm->num_rf_path; i++) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %s[%d] %-28s = {%d, %d, %d, %d, %d}\",\n\t\t\t \"CFO\", i, \"{S, L, Sec, Acq, End}\",\n\t\t\t cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i], cfo.cfo_rpt_sec[i],\n\t\t\t cfo.cfo_rpt_acq[i], cfo.cfo_rpt_end[i]);\n\t}\n#else\n\t/*@CFO Report Info*/\n\todm_set_bb_reg(dm, R_0xd00, BIT(26), 1);\n\n\t/*Short CFO*/\n\tvalue32 = odm_get_bb_reg(dm, R_0xdac, MASKDWORD);\n\tvalue32_1 = odm_get_bb_reg(dm, R_0xdb0, MASKDWORD);\n\n\tshort_cfo_b = (s32)(value32 & 0xfff); /*S(12,11)*/\n\tshort_cfo_a = (s32)((value32 & 0x0fff0000) >> 16);\n\n\tlong_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/\n\tlong_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);\n\n\t/*SFO 2's to dec*/\n\tif (short_cfo_a > 2047)\n\t\tshort_cfo_a = short_cfo_a - 4096;\n\tif (short_cfo_b > 2047)\n\t\tshort_cfo_b = short_cfo_b - 4096;\n\n\tshort_cfo_a = (short_cfo_a * 312500) / 2048;\n\tshort_cfo_b = (short_cfo_b * 312500) / 2048;\n\n\t/*@LFO 2's to dec*/\n\n\tif (long_cfo_a > 4095)\n\t\tlong_cfo_a = long_cfo_a - 8192;\n\n\tif (long_cfo_b > 4095)\n\t\tlong_cfo_b = long_cfo_b - 8192;\n\n\tlong_cfo_a = long_cfo_a * 312500 / 4096;\n\tlong_cfo_b = long_cfo_b * 312500 / 4096;\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"\\r\\n %-35s\",\n\t\t \"CFO Report Info\");\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d\", \"Short CFO(Hz) <A/B>\", short_cfo_a,\n\t\t short_cfo_b);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d\", \"Long CFO(Hz) <A/B>\", long_cfo_a,\n\t\t long_cfo_b);\n\n\t/*SCFO*/\n\tvalue32 = odm_get_bb_reg(dm, R_0xdb8, MASKDWORD);\n\tvalue32_1 = odm_get_bb_reg(dm, R_0xdb4, MASKDWORD);\n\n\tscfo_b = (s32)(value32 & 0x7ff); /*S(11,10)*/\n\tscfo_a = (s32)((value32 & 0x07ff0000) >> 16);\n\n\tif (scfo_a > 1023)\n\t\tscfo_a = scfo_a - 2048;\n\n\tif (scfo_b > 1023)\n\t\tscfo_b = scfo_b - 2048;\n\n\tscfo_a = scfo_a * 312500 / 1024;\n\tscfo_b = scfo_b * 312500 / 1024;\n\n\tavg_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/\n\tavg_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);\n\n\tif (avg_cfo_a > 4095)\n\t\tavg_cfo_a = avg_cfo_a - 8192;\n\n\tif (avg_cfo_b > 4095)\n\t\tavg_cfo_b = avg_cfo_b - 8192;\n\n\tavg_cfo_a = avg_cfo_a * 312500 / 4096;\n\tavg_cfo_b = avg_cfo_b * 312500 / 4096;\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d\", \"value SCFO(Hz) <A/B>\", scfo_a,\n\t\t scfo_b);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d\", \"Avg CFO(Hz) <A/B>\", avg_cfo_a,\n\t\t avg_cfo_b);\n\n\tvalue32 = odm_get_bb_reg(dm, R_0xdbc, MASKDWORD);\n\tvalue32_1 = odm_get_bb_reg(dm, R_0xde0, MASKDWORD);\n\n\tcfo_end_b = (s32)(value32 & 0x1fff); /*S(13,12)*/\n\tcfo_end_a = (s32)((value32 & 0x1fff0000) >> 16);\n\n\tif (cfo_end_a > 4095)\n\t\tcfo_end_a = cfo_end_a - 8192;\n\n\tif (cfo_end_b > 4095)\n\t\tcfo_end_b = cfo_end_b - 8192;\n\n\tcfo_end_a = cfo_end_a * 312500 / 4096;\n\tcfo_end_b = cfo_end_b * 312500 / 4096;\n\n\tacq_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/\n\tacq_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);\n\n\tif (acq_cfo_a > 4095)\n\t\tacq_cfo_a = acq_cfo_a - 8192;\n\n\tif (acq_cfo_b > 4095)\n\t\tacq_cfo_b = acq_cfo_b - 8192;\n\n\tacq_cfo_a = acq_cfo_a * 312500 / 4096;\n\tacq_cfo_b = acq_cfo_b * 312500 / 4096;\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d\", \"End CFO(Hz) <A/B>\", cfo_end_a,\n\t\t cfo_end_b);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d\", \"ACQ CFO(Hz) <A/B>\", acq_cfo_a,\n\t\t acq_cfo_b);\n#endif\n}\n#endif\n\n#if (ODM_IC_11AC_SERIES_SUPPORT)\n#if (RTL8822B_SUPPORT)\nvoid phydm_bb_hw_dbg_info_8822b(void *dm_void, u32 *_used, char *output,\n\t\t\t\tu32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 condi_num = 0;\n\tu8 i = 0;\n\n\tif (!(dm->support_ic_type == ODM_RTL8822B))\n\t\treturn;\n\n\tcondi_num = phydm_get_condi_num_8822b(dm);\n\tphydm_get_condi_num_acc_8822b(dm);\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d.%.4d\", \"condi_num\",\n\t\t condi_num >> 4, phydm_show_fraction_num(condi_num & 0xf, 4));\n\n\tfor (i = 0; i < CN_CNT_MAX; i++) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n Tone_num[CN>%d]%-21s = %d\",\n\t\t\t i, \" \", dm->phy_dbg_info.condi_num_cdf[i]);\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n#endif\n\nvoid phydm_bb_hw_dbg_info_ac(void *dm_void, u32 *_used, char *output,\n\t\t\t     u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tchar *tmp_string = NULL;\n\tu8 rx_ht_bw, rx_vht_bw, rxsc, rx_ht, bw_idx = 0;\n\tstatic u8 v_rx_bw;\n\tu32 value32, value32_1, value32_2, value32_3;\n\tstruct phydm_cfo_rpt cfo;\n\tu8 i = 0;\n\tstatic u8 tail, parity, rsv, vrsv, smooth, htsound, agg;\n\tstatic u8 stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, v_nsts;\n\tstatic u8 vtxops, vrsv2, vbrsv, bf, vbcrc;\n\tstatic u16 h_length, htcrc8, length;\n\tstatic u16 vpaid;\n\tstatic u16 v_length, vhtcrc8, v_mcss, v_tail, vb_tail;\n\tstatic u8 hmcss, hrx_bw;\n\tu8 pwdb;\n\ts8 rxevm_0, rxevm_1, rxevm_2;\n\tu8 rf_gain[4];\n\tu8 rx_snr[4];\n\ts32 sig_power;\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"\\r\\n %-35s\\n\",\n\t\t \"BB Report Info\");\n\n\t/*@ [BW & Mode] =====================================================*/\n\n\tvalue32 = odm_get_bb_reg(dm, R_0xf80, MASKDWORD);\n\trx_ht = (u8)((value32 & 0x180) >> 7);\n\n\tif (rx_ht == AD_VHT_MODE) {\n\t\ttmp_string = \"VHT\";\n\t\tbw_idx = (u8)((value32 >> 1) & 0x3);\n\t} else if (rx_ht == AD_HT_MODE) {\n\t\ttmp_string = \"HT\";\n\t\tbw_idx = (u8)(value32 & 0x1);\n\t} else {\n\t\ttmp_string = \"Legacy\";\n\t\tbw_idx = 0;\n\t}\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s %s %dM\", \"mode\", tmp_string, (20 << bw_idx));\n\n\tif (rx_ht != AD_LEGACY_MODE) {\n\t\trxsc = (u8)(value32 & 0x78);\n\n\t\tif (rxsc == 0)\n\t\t\ttmp_string = \"duplicate/full bw\";\n\t\telse if (rxsc == 1)\n\t\t\ttmp_string = \"usc20-1\";\n\t\telse if (rxsc == 2)\n\t\t\ttmp_string = \"lsc20-1\";\n\t\telse if (rxsc == 3)\n\t\t\ttmp_string = \"usc20-2\";\n\t\telse if (rxsc == 4)\n\t\t\ttmp_string = \"lsc20-2\";\n\t\telse if (rxsc == 9)\n\t\t\ttmp_string = \"usc40\";\n\t\telse if (rxsc == 10)\n\t\t\ttmp_string = \"lsc40\";\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"  %-35s\", tmp_string);\n\t}\n\n\t/*@ [RX signal power and AGC related info] ==========================*/\n\n\tpwdb = (u8)odm_get_bb_reg(dm, R_0xf90, MASKBYTE1);\n\tsig_power = -110 + (pwdb >> 1);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d\", \"OFDM RX Signal Power(dB)\", sig_power);\n\n\tvalue32 = odm_get_bb_reg(dm, R_0xd14, MASKDWORD);\n\trx_snr[RF_PATH_A] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/\n\trf_gain[RF_PATH_A] = (s8)(((value32 & MASKBYTE1) >> 8) * 2);\n\n\tvalue32 = odm_get_bb_reg(dm, R_0xd54, MASKDWORD);\n\trx_snr[RF_PATH_B] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/\n\trf_gain[RF_PATH_B] = (s8)(((value32 & MASKBYTE1) >> 8) * 2);\n\n\tvalue32 = odm_get_bb_reg(dm, R_0xd94, MASKDWORD);\n\trx_snr[RF_PATH_C] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/\n\trf_gain[RF_PATH_C] = (s8)(((value32 & MASKBYTE1) >> 8) * 2);\n\n\tvalue32 = odm_get_bb_reg(dm, R_0xdd4, MASKDWORD);\n\trx_snr[RF_PATH_D] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/\n\trf_gain[RF_PATH_D] = (s8)(((value32 & MASKBYTE1) >> 8) * 2);\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d / %d / %d\", \"OFDM RX RF Gain(A/B/C/D)\",\n\t\t rf_gain[RF_PATH_A], rf_gain[RF_PATH_B],\n\t\t rf_gain[RF_PATH_C], rf_gain[RF_PATH_D]);\n\n\t/*@ [RX counter Info] ===============================================*/\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d\", \"OFDM CCA cnt\",\n\t\t odm_get_bb_reg(dm, R_0xf08, 0xFFFF0000));\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d\", \"OFDM SBD Fail cnt\",\n\t\t odm_get_bb_reg(dm, R_0xfd0, 0xFFFF));\n\n\tvalue32 = odm_get_bb_reg(dm, R_0xfc4, MASKDWORD);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d\", \"VHT SIGA/SIGB CRC8 Fail cnt\",\n\t\t value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16));\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d\", \"CCK CCA cnt\",\n\t\t odm_get_bb_reg(dm, R_0xfcc, 0xFFFF));\n\n\tvalue32 = odm_get_bb_reg(dm, R_0xfbc, MASKDWORD);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d\",\n\t\t \"LSIG (parity Fail/rate Illegal) cnt\", value32 & 0xFFFF,\n\t\t ((value32 & 0xFFFF0000) >> 16));\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d\", \"HT/VHT MCS NOT SUPPORT cnt\",\n\t\t odm_get_bb_reg(dm, R_0xfc0, (0xFFFF0000 >> 16)),\n\t\t odm_get_bb_reg(dm, R_0xfc8, 0xFFFF));\n\n\t/*@ [PostFFT Info] =================================================*/\n\tvalue32 = odm_get_bb_reg(dm, R_0xf8c, MASKDWORD);\n\trxevm_0 = (s8)((value32 & MASKBYTE2) >> 16);\n\trxevm_0 /= 2;\n\tif (rxevm_0 < -63)\n\t\trxevm_0 = 0;\n\n\trxevm_1 = (s8)((value32 & MASKBYTE3) >> 24);\n\trxevm_1 /= 2;\n\tvalue32 = odm_get_bb_reg(dm, R_0xf88, MASKDWORD);\n\trxevm_2 = (s8)((value32 & MASKBYTE2) >> 16);\n\trxevm_2 /= 2;\n\n\tif (rxevm_1 < -63)\n\t\trxevm_1 = 0;\n\tif (rxevm_2 < -63)\n\t\trxevm_2 = 0;\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d / %d\", \"RXEVM (1ss/2ss/3ss)\", rxevm_0,\n\t\t rxevm_1, rxevm_2);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d / %d / %d\", \"RXSNR(A/B/C/D dB)\",\n\t\t rx_snr[RF_PATH_A], rx_snr[RF_PATH_B],\n\t\t rx_snr[RF_PATH_C], rx_snr[RF_PATH_D]);\n\n\tvalue32 = odm_get_bb_reg(dm, R_0xf8c, MASKDWORD);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d\", \"CSI_1st /CSI_2nd\", value32 & 0xFFFF,\n\t\t ((value32 & 0xFFFF0000) >> 16));\n\n\t/*@ [CFO Report Info] ===============================================*/\n\tphydm_get_cfo_info(dm, &cfo);\n\tfor (i = 0; i < dm->num_rf_path; i++) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %s[%d] %-28s = {%d, %d, %d, %d, %d}\",\n\t\t\t \"CFO\", i, \"{S, L, Sec, Acq, End}\",\n\t\t\t cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i], cfo.cfo_rpt_sec[i],\n\t\t\t cfo.cfo_rpt_acq[i], cfo.cfo_rpt_end[i]);\n\t}\n\n\t/*@ [L-SIG Content] =================================================*/\n\tvalue32 = odm_get_bb_reg(dm, R_0xf20, MASKDWORD);\n\n\ttail = (u8)((value32 & 0xfc0000) >> 18);/*@[23:18]*/\n\tparity = (u8)((value32 & 0x20000) >> 17);/*@[17]*/\n\tlength = (u16)((value32 & 0x1ffe0) >> 5);/*@[16:5]*/\n\trsv = (u8)((value32 & 0x10) >> 4);/*@[4]*/\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"\\r\\n %-35s\",\n\t\t \"L-SIG\");\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d M\", \"rate\",\n\t\t phydm_get_l_sig_rate(dm, (u8)(value32 & 0x0f)));\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %x / %d / %d\", \"Rsv/length/parity\", rsv, length,\n\t\t parity);\n\n\tif (rx_ht == AD_HT_MODE) {\n\t/*@ [HT SIG 1] ======================================================*/\n\t\tvalue32 = odm_get_bb_reg(dm, R_0xf2c, MASKDWORD);\n\n\t\thmcss = (u8)(value32 & 0x7F);\n\t\thrx_bw = (u8)((value32 & 0x80) >> 7);\n\t\th_length = (u16)((value32 & 0x0fff00) >> 8);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s\", \"HT-SIG1\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = %d / %d / %d\", \"MCS/BW/length\",\n\t\t\t hmcss, hrx_bw, h_length);\n\t/*@ [HT SIG 2] ======================================================*/\n\t\tvalue32 = odm_get_bb_reg(dm, R_0xf30, MASKDWORD);\n\t\tsmooth = (u8)(value32 & 0x01);\n\t\thtsound = (u8)((value32 & 0x02) >> 1);\n\t\trsv = (u8)((value32 & 0x04) >> 2);\n\t\tagg = (u8)((value32 & 0x08) >> 3);\n\t\tstbc = (u8)((value32 & 0x30) >> 4);\n\t\tfec = (u8)((value32 & 0x40) >> 6);\n\t\tsgi = (u8)((value32 & 0x80) >> 7);\n\t\thtltf = (u8)((value32 & 0x300) >> 8);\n\t\thtcrc8 = (u16)((value32 & 0x3fc00) >> 10);\n\t\ttail = (u8)((value32 & 0xfc0000) >> 18);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s\",\n\t\t\t \"HT-SIG2\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = %x / %x / %x / %x / %x / %x\",\n\t\t\t \"Smooth/NoSound/Rsv/Aggregate/STBC/LDPC\",\n\t\t\t smooth, htsound, rsv, agg, stbc, fec);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = %x / %x / %x / %x\",\n\t\t\t \"SGI/E-HT-LTFs/CRC/tail\",\n\t\t\t sgi, htltf, htcrc8, tail);\n\t} else if (rx_ht == AD_VHT_MODE) {\n\t/*@ [VHT SIG A1] ====================================================*/\n\t\tvalue32 = odm_get_bb_reg(dm, R_0xf2c, MASKDWORD);\n\n\t\tv_rx_bw = (u8)(value32 & 0x03);\n\t\tvrsv = (u8)((value32 & 0x04) >> 2);\n\t\tvstbc = (u8)((value32 & 0x08) >> 3);\n\t\tvgid = (u8)((value32 & 0x3f0) >> 4);\n\t\tv_nsts = (u8)(((value32 & 0x1c00) >> 10) + 1);\n\t\tvpaid = (u16)((value32 & 0x3fe000) >> 13);\n\t\tvtxops = (u8)((value32 & 0x400000) >> 22);\n\t\tvrsv2 = (u8)((value32 & 0x800000) >> 23);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s\",\n\t\t\t \"VHT-SIG-A1\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x\",\n\t\t\t \"BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2\", v_rx_bw,\n\t\t\t vrsv, vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2);\n\n\t/*@ [VHT SIG A2] ====================================================*/\n\t\tvalue32 = odm_get_bb_reg(dm, R_0xf30, MASKDWORD);\n\n\t\t/* @sgi=(u8)(value32&0x01); */\n\t\tsgiext = (u8)(value32 & 0x03);\n\t\t/* @fec = (u8)(value32&0x04); */\n\t\tfecext = (u8)((value32 & 0x0C) >> 2);\n\n\t\tv_mcss = (u8)((value32 & 0xf0) >> 4);\n\t\tbf = (u8)((value32 & 0x100) >> 8);\n\t\tvrsv = (u8)((value32 & 0x200) >> 9);\n\t\tvhtcrc8 = (u16)((value32 & 0x3fc00) >> 10);\n\t\tv_tail = (u8)((value32 & 0xfc0000) >> 18);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s\", \"VHT-SIG-A2\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = %x / %x / %x / %x / %x / %x / %x\",\n\t\t\t \"SGI/FEC/MCS/BF/Rsv/CRC/tail\",\n\t\t\t sgiext, fecext, v_mcss, bf, vrsv, vhtcrc8, v_tail);\n\n\t/*@ [VHT SIG B] ====================================================*/\n\t\tvalue32 = odm_get_bb_reg(dm, R_0xf34, MASKDWORD);\n\n\t\t#if 0\n\t\tv_length = (u16)(value32 & 0x1fffff);\n\t\tvbrsv = (u8)((value32 & 0x600000) >> 21);\n\t\tvb_tail = (u16)((value32 & 0x1f800000) >> 23);\n\t\tvbcrc = (u8)((value32 & 0x80000000) >> 31);\n\t\t#endif\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s\", \"VHT-SIG-B\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = %x\",\n\t\t\t \"Codeword\", value32);\n\n\t\t#if 0\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = %x / %x / %x / %x\",\n\t\t\t \"length/Rsv/tail/CRC\",\n\t\t\t v_length, vbrsv, vb_tail, vbcrc);\n\t\t#endif\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n#endif\n\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\nvoid phydm_bb_hw_dbg_info_jgr3(void *dm_void, u32 *_used, char *output,\n\t\t\t       u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tchar *tmp_string = NULL;\n\tu8 rx_ht_bw = 0, rx_vht_bw = 0, rx_ht = 0;\n\tstatic u8 v_rx_bw;\n\tu32 value32 = 0;\n\tu8 i = 0;\n\tstatic u8 tail, parity, rsv, vrsv, smooth, htsound, agg;\n\tstatic u8 stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, v_nsts;\n\tstatic u8 vtxops, vrsv2, vbrsv, bf, vbcrc;\n\tstatic u16 h_length, htcrc8, length;\n\tstatic u16 vpaid;\n\tstatic u16 v_length, vhtcrc8, v_mcss, v_tail, vb_tail;\n\tstatic u8 hmcss, hrx_bw;\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"\\r\\n %-35s\\n\",\n\t\t \"BB Report Info\");\n\n\t/*@ [Mode] =====================================================*/\n\n\tvalue32 = odm_get_bb_reg(dm, R_0x2c20, MASKDWORD);\n\trx_ht = (u8)((value32 & 0xC0000) >> 18);\n\tif (rx_ht == AD_VHT_MODE)\n\t\ttmp_string = \"VHT\";\n\telse if (rx_ht == AD_HT_MODE)\n\t\ttmp_string = \"HT\";\n\telse\n\t\ttmp_string = \"Legacy\";\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s %s\", \"mode\", tmp_string);\n\t/*@ [RX counter Info] ===============================================*/\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d\", \"CCK CCA cnt\",\n\t\t odm_get_bb_reg(dm, R_0x2c08, 0xFFFF));\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d\", \"OFDM CCA cnt\",\n\t\t odm_get_bb_reg(dm, R_0x2c08, 0xFFFF0000));\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d\", \"OFDM SBD Fail cnt\",\n\t\t odm_get_bb_reg(dm, R_0x2d20, 0xFFFF0000));\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d\",\n\t\t \"LSIG (parity Fail/rate Illegal) cnt\",\n\t\t odm_get_bb_reg(dm, R_0x2d04, 0xFFFF0000),\n\t\t odm_get_bb_reg(dm, R_0x2d08, 0xFFFF));\n\n\tvalue32 = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d\", \"HT/VHT MCS NOT SUPPORT cnt\",\n\t\t value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16));\n\n\tvalue32 = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d / %d\", \"VHT SIGA/SIGB CRC8 Fail cnt\",\n\t\t value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16));\n\t/*@ [L-SIG Content] =================================================*/\n\tvalue32 = odm_get_bb_reg(dm, R_0x2c20, MASKDWORD);\n\n\tparity = (u8)((value32 & 0x20000) >> 17);/*@[17]*/\n\tlength = (u16)((value32 & 0x1ffe0) >> 5);/*@[16:5]*/\n\trsv = (u8)((value32 & 0x10) >> 4);/*@[4]*/\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"\\r\\n %-35s\",\n\t\t \"L-SIG\");\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %d M\", \"rate\",\n\t\t phydm_get_l_sig_rate(dm, (u8)(value32 & 0x0f)));\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\r\\n %-35s = %x / %d / %d\", \"Rsv/length/parity\", rsv, length,\n\t\t parity);\n\n\tif (rx_ht == AD_HT_MODE) {\n\t/*@ [HT SIG 1] ======================================================*/\n\t\tvalue32 = odm_get_bb_reg(dm, R_0x2c2c, MASKDWORD);\n\n\t\thmcss = (u8)(value32 & 0x7F);\n\t\thrx_bw = (u8)((value32 & 0x80) >> 7);\n\t\th_length = (u16)((value32 & 0x0fff00) >> 8);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s\", \"HT-SIG1\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = %d / %d / %d\", \"MCS/BW/length\",\n\t\t\t hmcss, hrx_bw, h_length);\n\t/*@ [HT SIG 2] ======================================================*/\n\t\tvalue32 = odm_get_bb_reg(dm, R_0x2c30, MASKDWORD);\n\t\tsmooth = (u8)(value32 & 0x01);\n\t\thtsound = (u8)((value32 & 0x02) >> 1);\n\t\trsv = (u8)((value32 & 0x04) >> 2);\n\t\tagg = (u8)((value32 & 0x08) >> 3);\n\t\tstbc = (u8)((value32 & 0x30) >> 4);\n\t\tfec = (u8)((value32 & 0x40) >> 6);\n\t\tsgi = (u8)((value32 & 0x80) >> 7);\n\t\thtltf = (u8)((value32 & 0x300) >> 8);\n\t\thtcrc8 = (u16)((value32 & 0x3fc00) >> 10);\n\t\ttail = (u8)((value32 & 0xfc0000) >> 18);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s\",\n\t\t\t \"HT-SIG2\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = %x / %x / %x / %x / %x / %x\",\n\t\t\t \"Smooth/NoSound/Rsv/Aggregate/STBC/LDPC\",\n\t\t\t smooth, htsound, rsv, agg, stbc, fec);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = %x / %x / %x / %x\",\n\t\t\t \"SGI/E-HT-LTFs/CRC/tail\",\n\t\t\t sgi, htltf, htcrc8, tail);\n\t} else if (rx_ht == AD_VHT_MODE) {\n\t/*@ [VHT SIG A1] ====================================================*/\n\t\tvalue32 = odm_get_bb_reg(dm, R_0x2c2c, MASKDWORD);\n\n\t\tv_rx_bw = (u8)(value32 & 0x03);\n\t\tvrsv = (u8)((value32 & 0x04) >> 2);\n\t\tvstbc = (u8)((value32 & 0x08) >> 3);\n\t\tvgid = (u8)((value32 & 0x3f0) >> 4);\n\t\tv_nsts = (u8)(((value32 & 0x1c00) >> 10) + 1);\n\t\tvpaid = (u16)((value32 & 0x3fe000) >> 13);\n\t\tvtxops = (u8)((value32 & 0x400000) >> 22);\n\t\tvrsv2 = (u8)((value32 & 0x800000) >> 23);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s\",\n\t\t\t \"VHT-SIG-A1\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x\",\n\t\t\t \"BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2\", v_rx_bw,\n\t\t\t vrsv, vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2);\n\n\t/*@ [VHT SIG A2] ====================================================*/\n\t\tvalue32 = odm_get_bb_reg(dm, R_0x2c30, MASKDWORD);\n\n\t\t/* @sgi=(u8)(value32&0x01); */\n\t\tsgiext = (u8)(value32 & 0x03);\n\t\t/* @fec = (u8)(value32&0x04); */\n\t\tfecext = (u8)((value32 & 0x0C) >> 2);\n\n\t\tv_mcss = (u8)((value32 & 0xf0) >> 4);\n\t\tbf = (u8)((value32 & 0x100) >> 8);\n\t\tvrsv = (u8)((value32 & 0x200) >> 9);\n\t\tvhtcrc8 = (u16)((value32 & 0x3fc00) >> 10);\n\t\tv_tail = (u8)((value32 & 0xfc0000) >> 18);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s\", \"VHT-SIG-A2\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = %x / %x / %x / %x / %x / %x / %x\",\n\t\t\t \"SGI/FEC/MCS/BF/Rsv/CRC/tail\",\n\t\t\t sgiext, fecext, v_mcss, bf, vrsv, vhtcrc8, v_tail);\n\n\t/*@ [VHT SIG B] ====================================================*/\n\t\tvalue32 = odm_get_bb_reg(dm, R_0x2c34, MASKDWORD);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s\", \"VHT-SIG-B\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = %x\",\n\t\t\t \"Codeword\", value32);\n\n\t\tif (v_rx_bw == 0) {\n\t\t\tv_length = (u16)(value32 & 0x1ffff);\n\t\t\tvbrsv = (u8)((value32 & 0xE0000) >> 17);\n\t\t\tvb_tail = (u16)((value32 & 0x03F00000) >> 20);\n\t\t} else if (v_rx_bw == 1) {\n\t\t\tv_length = (u16)(value32 & 0x7FFFF);\n\t\t\tvbrsv = (u8)((value32 & 0x180000) >> 19);\n\t\t\tvb_tail = (u16)((value32 & 0x07E00000) >> 21);\n\t\t} else if (v_rx_bw == 2) {\n\t\t\tv_length = (u16)(value32 & 0x1fffff);\n\t\t\tvbrsv = (u8)((value32 & 0x600000) >> 21);\n\t\t\tvb_tail = (u16)((value32 & 0x1f800000) >> 23);\n\t\t}\n\t\tvbcrc = (u8)((value32 & 0x80000000) >> 31);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"\\r\\n %-35s = %x / %x / %x / %x\",\n\t\t\t \"length/Rsv/tail/CRC\",\n\t\t\t v_length, vbrsv, vb_tail, vbcrc);\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n#endif\n\nu8 phydm_get_l_sig_rate(void *dm_void, u8 rate_idx_l_sig)\n{\n\tu8 rate_idx = 0xff;\n\n\tswitch (rate_idx_l_sig) {\n\tcase 0x0b:\n\t\trate_idx = 6;\n\t\tbreak;\n\tcase 0x0f:\n\t\trate_idx = 9;\n\t\tbreak;\n\tcase 0x0a:\n\t\trate_idx = 12;\n\t\tbreak;\n\tcase 0x0e:\n\t\trate_idx = 18;\n\t\tbreak;\n\tcase 0x09:\n\t\trate_idx = 24;\n\t\tbreak;\n\tcase 0x0d:\n\t\trate_idx = 36;\n\t\tbreak;\n\tcase 0x08:\n\t\trate_idx = 48;\n\t\tbreak;\n\tcase 0x0c:\n\t\trate_idx = 54;\n\t\tbreak;\n\tdefault:\n\t\trate_idx = 0xff;\n\t\tbreak;\n\t}\n\n\treturn rate_idx;\n}\n\nvoid phydm_bb_hw_dbg_info(void *dm_void, char input[][16], u32 *_used,\n\t\t\t  char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\tswitch (dm->ic_ip_series) {\n\t#if (ODM_IC_11N_SERIES_SUPPORT)\n\tcase PHYDM_IC_N:\n\t\tphydm_bb_hw_dbg_info_n(dm, &used, output, &out_len);\n\t\tbreak;\n\t#endif\n\n\t#if (ODM_IC_11AC_SERIES_SUPPORT)\n\tcase PHYDM_IC_AC:\n\t\tphydm_bb_hw_dbg_info_ac(dm, &used, output, &out_len);\n\t\tphydm_reset_bb_hw_cnt(dm);\n\t\t#if (RTL8822B_SUPPORT)\n\t\tphydm_bb_hw_dbg_info_8822b(dm, &used, output, &out_len);\n\t\t#endif\n\t\tbreak;\n\t#endif\n\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\tcase PHYDM_IC_JGR3:\n\t\tphydm_bb_hw_dbg_info_jgr3(dm, &used, output, &out_len);\n\t\tphydm_reset_bb_hw_cnt(dm);\n\t\tbreak;\n\t#endif\n\tdefault:\n\t\tbreak;\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\n#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\nvoid phydm_dm_summary_cli_win(void *dm_void, char *buf, u8 macid)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track;\n\tstruct cmn_sta_info *sta = NULL;\n\tstruct ra_sta_info *ra = NULL;\n\tstruct dtp_info *dtp = NULL;\n\tu64 comp = dm->support_ability;\n\tu64 pause_comp = dm->pause_ability;\n\n\tif (!dm->is_linked) {\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"[%s]No Link !!!\\n\", __func__);\n\t\tRT_PRINT(buf);\n\t\treturn;\n\t}\n\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"00.(%s) %-12s: IGI=0x%x, Dyn_Rng=0x%x~0x%x, FA_th={%d,%d,%d}\\n\",\n\t\t   ((comp & ODM_BB_DIG) ?\n\t\t   ((pause_comp & ODM_BB_DIG) ? \"P\" : \"V\") : \".\"),\n\t\t   \"DIG\",\n\t\t   dig_t->cur_ig_value,\n\t\t   dig_t->rx_gain_range_min, dig_t->rx_gain_range_max,\n\t\t   dig_t->fa_th[0], dig_t->fa_th[1], dig_t->fa_th[2]);\n        RT_PRINT(buf);\n\n\tsta = dm->phydm_sta_info[macid];\n\tif (is_sta_active(sta)) {\n\t\tRT_PRINT(buf);\n\n\t\tra = &sta->ra_info;\n\t\tdtp = &sta->dtp_stat;\n\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"01.(%s) %-12s: rssi_lv=%d, mask=0x%llx\\n\",\n\t\t\t   ((comp & ODM_BB_RA_MASK) ?\n\t\t\t   ((pause_comp & ODM_BB_RA_MASK) ? \"P\" : \"V\") : \".\"),\n\t\t\t   \"RaMask\",\n\t\t\t   ra->rssi_level, ra->ramask);\n\t\tRT_PRINT(buf);\n\n\t\t#ifdef CONFIG_DYNAMIC_TX_TWR\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"02.(%s) %-12s: pwr_lv=%d\\n\",\n\t\t\t   ((comp & ODM_BB_DYNAMIC_TXPWR) ?\n\t\t\t   ((pause_comp & ODM_BB_DYNAMIC_TXPWR) ? \"P\" : \"V\") : \".\"),\n\t\t\t   \"DynTxPwr\",\n\t\t\t   dtp->sta_tx_high_power_lvl);\n\t\tRT_PRINT(buf);\n\t\t#endif\n\t}\n\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"05.(%s) %-12s: cck_pd_lv=%d\\n\",\n\t\t   ((comp & ODM_BB_CCK_PD) ?\n\t\t   ((pause_comp & ODM_BB_CCK_PD) ? \"P\" : \"V\") : \".\"),\n\t\t   \"CCK_PD\", dm->dm_cckpd_table.cck_pd_lv);\n\tRT_PRINT(buf);\n\n#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"06.(%s) %-12s: div_type=%d, curr_ant=%s\\n\",\n\t\t   ((comp & ODM_BB_ANT_DIV) ?\n\t\t   ((pause_comp & ODM_BB_ANT_DIV) ? \"P\" : \"V\") : \".\"),\n\t\t   \"ANT_DIV\",\n\t\t   dm->ant_div_type,\n\t\t   (dm->dm_fat_table.rx_idle_ant == MAIN_ANT) ? \"MAIN\" : \"AUX\");\n\tRT_PRINT(buf);\n#endif\n\n#ifdef PHYDM_POWER_TRAINING_SUPPORT\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"08.(%s) %-12s: PT_score=%d, disable_PT=%d\\n\",\n\t\t   ((comp & ODM_BB_PWR_TRAIN) ?\n\t\t   ((pause_comp & ODM_BB_PWR_TRAIN) ? \"P\" : \"V\") : \".\"),\n\t\t   \"PwrTrain\",\n\t\t   dm->pow_train_table.pow_train_score,\n\t\t   dm->is_disable_power_training);\n\tRT_PRINT(buf);\n#endif\n\n#ifdef CONFIG_PHYDM_DFS_MASTER\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"11.(%s) %-12s: dbg_mode=%d, region_domain=%d\\n\",\n\t\t   ((comp & ODM_BB_DFS) ?\n\t\t   ((pause_comp & ODM_BB_DFS) ? \"P\" : \"V\") : \".\"),\n\t\t   \"DFS\",\n\t\t   dm->dfs.dbg_mode, dm->dfs_region_domain);\n\tRT_PRINT(buf);\n#endif\n#ifdef PHYDM_SUPPORT_ADAPTIVITY\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"13.(%s) %-12s: th{l2h, h2l}={%d, %d}, edcca_flag=%d\\n\",\n\t\t   ((comp & ODM_BB_ADAPTIVITY) ?\n\t\t   ((pause_comp & ODM_BB_ADAPTIVITY) ? \"P\" : \"V\") : \".\"),\n\t\t   \"Adaptivity\",\n\t\t   dm->adaptivity.th_l2h, dm->adaptivity.th_h2l,\n\t\t   dm->false_alm_cnt.edcca_flag);\n\tRT_PRINT(buf);\n#endif\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"14.(%s) %-12s: CFO_avg=%d kHz, CFO_traking=%s%d\\n\",\n\t\t   ((comp & ODM_BB_CFO_TRACKING) ?\n\t\t   ((pause_comp & ODM_BB_CFO_TRACKING) ? \"P\" : \"V\") : \".\"),\n\t\t   \"CfoTrack\",\n\t\t   cfo_t->CFO_ave_pre,\n\t\t   ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? \"+\" : \"-\"),\n\t\t   DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap));\n\tRT_PRINT(buf);\n\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"15.(%s) %-12s: ratio{nhm, clm}={%d, %d}\\n\",\n\t\t   ((comp & ODM_BB_ENV_MONITOR) ?\n\t\t   ((pause_comp & ODM_BB_ENV_MONITOR) ? \"P\" : \"V\") : \".\"),\n\t\t   \"EnvMntr\",\n\t\t   dm->dm_ccx_info.nhm_ratio, dm->dm_ccx_info.clm_ratio);\n\tRT_PRINT(buf);\n#ifdef PHYDM_PRIMARY_CCA\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"16.(%s) %-12s: CCA @ (%s SB)\\n\",\n\t\t   ((comp & ODM_BB_PRIMARY_CCA) ?\n\t\t   ((pause_comp & ODM_BB_PRIMARY_CCA) ? \"P\" : \"V\") : \".\"),\n\t\t   \"PriCCA\",\n\t\t   ((dm->dm_pri_cca.mf_state == MF_USC_LSC) ? \"D\" :\n\t\t   ((dm->dm_pri_cca.mf_state == MF_LSC) ? \"L\" : \"U\")));\n\tRT_PRINT(buf);\n#endif\n#ifdef CONFIG_ADAPTIVE_SOML\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"17.(%s) %-12s: soml_en = %s\\n\",\n\t\t   ((comp & ODM_BB_ADAPTIVE_SOML) ?\n\t\t   ((pause_comp & ODM_BB_ADAPTIVE_SOML) ? \"P\" : \"V\") : \".\"),\n\t\t   \"A-SOML\",\n\t\t   (dm->dm_soml_table.soml_last_state == SOML_ON) ?\n\t\t   \"ON\" : \"OFF\");\n\tRT_PRINT(buf);\n#endif\n#ifdef PHYDM_LNA_SAT_CHK_SUPPORT\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"18.(%s) %-12s:\\n\",\n\t\t   ((comp & ODM_BB_LNA_SAT_CHK) ?\n\t\t   ((pause_comp & ODM_BB_LNA_SAT_CHK) ? \"P\" : \"V\") : \".\"),\n\t\t   \"LNA_SAT_CHK\");\n\tRT_PRINT(buf);\n#endif\n}\n\nvoid phydm_basic_dbg_msg_cli_win(void *dm_void, char *buf)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fa_struct *fa_t = &dm->false_alm_cnt;\n\tstruct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track;\n\tstruct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;\n\tstruct phydm_phystatus_statistic *dbg_s = &dbg->physts_statistic_info;\n\tstruct phydm_phystatus_avg *dbg_avg = &dbg->phystatus_statistic_avg;\n\tchar *rate_type = NULL;\n\tu8 tmp_rssi_avg[4];\n\tu8 tmp_snr_avg[4];\n\tu8 tmp_evm_avg[4];\n\tu32 tmp_cnt = 0;\n\tu8 macid, target_macid = 0;\n\tu8 i = 0;\n\tu8 rate_num = dm->num_rf_path;\n\tu8 ss_ofst = 0;\n\tstruct cmn_sta_info *entry = NULL;\n\tchar dbg_buf[PHYDM_SNPRINT_SIZE] = {0};\n\n\tif (dm->debug_components & DBG_CMN)\n\t\treturn;\n\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n PHYDM Common Dbg Msg --------->\");\n\tRT_PRINT(buf);\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n System up time=%d\", dm->phydm_sys_up_time);\n\tRT_PRINT(buf);\n\n\tif (dm->is_linked) {\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n ID=((%d)), BW=((%d)), fc=((CH-%d))\",\n\t\t\t   dm->curr_station_id, 20 << *dm->band_width, *dm->channel);\n\t\tRT_PRINT(buf);\n\n\t\tif (((*dm->channel <= 14) && (*dm->band_width == CHANNEL_WIDTH_40)) &&\n\t\t    (dm->support_ic_type & ODM_IC_11N_SERIES)) {\n\t\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n Primary CCA at ((%s SB))\",\n\t\t\t\t   (*dm->sec_ch_offset == SECOND_CH_AT_LSB) ? \"U\" : \"L\");\n\t\t\tRT_PRINT(buf);\n\t\t}\n\n\t\tif ((dm->support_ic_type & PHYSTS_2ND_TYPE_IC) || dm->rx_rate > ODM_RATE11M) {\n\t\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n [AGC Idx] {0x%x, 0x%x, 0x%x, 0x%x}\",\n\t\t\t\t   dm->ofdm_agc_idx[0], dm->ofdm_agc_idx[1],\n\t\t\t\t   dm->ofdm_agc_idx[2], dm->ofdm_agc_idx[3]);\n\t\t\tRT_PRINT(buf);\n\t\t} else {\n\t\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n [CCK AGC Idx] {LNA,VGA}={0x%x, 0x%x}\",\n\t\t\t\t   dm->cck_lna_idx, dm->cck_vga_idx);\n\t\t\tRT_PRINT(buf);\n\t\t}\n\n\t\tphydm_print_rate_2_buff(dm, dm->rx_rate, dbg_buf, PHYDM_SNPRINT_SIZE);\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n RSSI:{%d, %d, %d, %d}, RxRate:%s (0x%x)\",\n\t\t\t   (dm->rssi_a == 0xff) ? 0 : dm->rssi_a,\n\t\t\t   (dm->rssi_b == 0xff) ? 0 : dm->rssi_b,\n\t\t\t   (dm->rssi_c == 0xff) ? 0 : dm->rssi_c,\n\t\t\t   (dm->rssi_d == 0xff) ? 0 : dm->rssi_d,\n\t\t\t  dbg_buf, dm->rx_rate);\n\t\tRT_PRINT(buf);\n\n\t\tphydm_print_rate_2_buff(dm, dm->phy_dbg_info.beacon_phy_rate, dbg_buf, PHYDM_SNPRINT_SIZE);\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n Beacon_cnt=%d, rate_idx:%s (0x%x)\",\n\t\t\t   dm->phy_dbg_info.beacon_cnt_in_period,\n\t\t\t   dbg_buf,\n\t\t\t   dm->phy_dbg_info.beacon_phy_rate);\n\t\tRT_PRINT(buf);\n\n\t\t/*Show phydm_rx_rate_distribution;*/\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n [RxRate Cnt] =============>\");\n\t\tRT_PRINT(buf);\n\n\t\t/*@======CCK=================================================*/\n\t\tif (*dm->channel <= 14) {\n\t\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n * CCK = {%d, %d, %d, %d}\",\n\t\t\t\t   dbg->num_qry_legacy_pkt[0], dbg->num_qry_legacy_pkt[1],\n\t\t\t\t   dbg->num_qry_legacy_pkt[2], dbg->num_qry_legacy_pkt[3]);\n\t\t\tRT_PRINT(buf);\n\t\t}\n\t\t/*@======OFDM================================================*/\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n * OFDM = {%d, %d, %d, %d, %d, %d, %d, %d}\",\n\t\t\t   dbg->num_qry_legacy_pkt[4], dbg->num_qry_legacy_pkt[5],\n\t\t\t   dbg->num_qry_legacy_pkt[6], dbg->num_qry_legacy_pkt[7],\n\t\t\t   dbg->num_qry_legacy_pkt[8], dbg->num_qry_legacy_pkt[9],\n\t\t\t   dbg->num_qry_legacy_pkt[10], dbg->num_qry_legacy_pkt[11]);\n\t\tRT_PRINT(buf);\n\n\t\t/*@======HT==================================================*/\n\t\tif (dbg->ht_pkt_not_zero) {\n\t\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\t\tss_ofst = (i << 3);\n\n\t\t\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n * HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\",\n\t\t\t\t\t   (ss_ofst), (ss_ofst + 7),\n\t\t\t\t\t   dbg->num_qry_ht_pkt[ss_ofst + 0], dbg->num_qry_ht_pkt[ss_ofst + 1],\n\t\t\t\t\t   dbg->num_qry_ht_pkt[ss_ofst + 2], dbg->num_qry_ht_pkt[ss_ofst + 3],\n\t\t\t\t\t   dbg->num_qry_ht_pkt[ss_ofst + 4], dbg->num_qry_ht_pkt[ss_ofst + 5],\n\t\t\t\t\t   dbg->num_qry_ht_pkt[ss_ofst + 6], dbg->num_qry_ht_pkt[ss_ofst + 7]);\n\t\t\t\tRT_PRINT(buf);\n\t\t\t}\n\n\t\t\tif (dbg->low_bw_20_occur) {\n\t\t\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\t\t\tss_ofst = (i << 3);\n\n\t\t\t\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n * [Low BW 20M] HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\",\n\t\t\t\t\t\t   (ss_ofst), (ss_ofst + 7),\n\t\t\t\t\t\t   dbg->num_qry_pkt_sc_20m[ss_ofst + 0], dbg->num_qry_pkt_sc_20m[ss_ofst + 1],\n\t\t\t\t\t\t   dbg->num_qry_pkt_sc_20m[ss_ofst + 2], dbg->num_qry_pkt_sc_20m[ss_ofst + 3],\n\t\t\t\t\t\t   dbg->num_qry_pkt_sc_20m[ss_ofst + 4], dbg->num_qry_pkt_sc_20m[ss_ofst + 5],\n\t\t\t\t\t\t   dbg->num_qry_pkt_sc_20m[ss_ofst + 6], dbg->num_qry_pkt_sc_20m[ss_ofst + 7]);\n\t\t\t\t\tRT_PRINT(buf);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))\n\t\t/*@======VHT=================================================*/\n\t\tif (dbg->vht_pkt_not_zero) {\n\t\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\t\tss_ofst = 10 * i;\n\n\t\t\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n * VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\",\n\t\t\t\t\t   (i + 1),\n\t\t\t\t\t   dbg->num_qry_vht_pkt[ss_ofst + 0], dbg->num_qry_vht_pkt[ss_ofst + 1],\n\t\t\t\t\t   dbg->num_qry_vht_pkt[ss_ofst + 2], dbg->num_qry_vht_pkt[ss_ofst + 3],\n\t\t\t\t\t   dbg->num_qry_vht_pkt[ss_ofst + 4], dbg->num_qry_vht_pkt[ss_ofst + 5],\n\t\t\t\t\t   dbg->num_qry_vht_pkt[ss_ofst + 6], dbg->num_qry_vht_pkt[ss_ofst + 7],\n\t\t\t\t\t   dbg->num_qry_vht_pkt[ss_ofst + 8], dbg->num_qry_vht_pkt[ss_ofst + 9]);\n\t\t\t\tRT_PRINT(buf);\n\t\t\t}\n\n\t\t\tif (dbg->low_bw_20_occur) {\n\t\t\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\t\t\tss_ofst = 10 * i;\n\n\t\t\t\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n *[Low BW 20M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\",\n\t\t\t\t\t\t   (i + 1),\n\t\t\t\t\t\t   dbg->num_qry_pkt_sc_20m[ss_ofst + 0], dbg->num_qry_pkt_sc_20m[ss_ofst + 1],\n\t\t\t\t\t\t   dbg->num_qry_pkt_sc_20m[ss_ofst + 2], dbg->num_qry_pkt_sc_20m[ss_ofst + 3],\n\t\t\t\t\t\t   dbg->num_qry_pkt_sc_20m[ss_ofst + 4], dbg->num_qry_pkt_sc_20m[ss_ofst + 5],\n\t\t\t\t\t\t   dbg->num_qry_pkt_sc_20m[ss_ofst + 6], dbg->num_qry_pkt_sc_20m[ss_ofst + 7],\n\t\t\t\t\t\t   dbg->num_qry_pkt_sc_20m[ss_ofst + 8], dbg->num_qry_pkt_sc_20m[ss_ofst + 9]);\n\t\t\t\t\tRT_PRINT(buf);\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (dbg->low_bw_40_occur) {\n\t\t\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\t\t\tss_ofst = 10 * i;\n\n\t\t\t\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n *[Low BW 40M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\",\n\t\t\t\t\t\t   (i + 1),\n\t\t\t\t\t\t   dbg->num_qry_pkt_sc_40m[ss_ofst + 0], dbg->num_qry_pkt_sc_40m[ss_ofst + 1],\n\t\t\t\t\t\t   dbg->num_qry_pkt_sc_40m[ss_ofst + 2], dbg->num_qry_pkt_sc_40m[ss_ofst + 3],\n\t\t\t\t\t\t   dbg->num_qry_pkt_sc_40m[ss_ofst + 4], dbg->num_qry_pkt_sc_40m[ss_ofst + 5],\n\t\t\t\t\t\t   dbg->num_qry_pkt_sc_40m[ss_ofst + 6], dbg->num_qry_pkt_sc_40m[ss_ofst + 7],\n\t\t\t\t\t\t   dbg->num_qry_pkt_sc_40m[ss_ofst + 8], dbg->num_qry_pkt_sc_40m[ss_ofst + 9]);\n\t\t\t\t\tRT_PRINT(buf);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n#endif\n\n\t\tphydm_reset_rx_rate_distribution(dm);\n\n\t\t//1 Show phydm_avg_phystatus_val\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n [Avg PHY Statistic] ==============>\");\n\t\tRT_PRINT(buf);\n#if 1\n\t\tphydm_get_avg_phystatus_val(dm);\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"* %-8s Cnt=((%.3d)) RSSI:{%.2d}\\n\",\n\t\t\t   \"[Beacon]\", dbg_s->rssi_beacon_cnt, dbg_avg->rssi_beacon_avg);\n\t\tRT_PRINT(buf);\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"* %-8s Cnt=((%.3d)) RSSI:{%.2d}\\n\",\n\t\t\t   \"[CCK]\", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg);\n\t\tRT_PRINT(buf);\n\n\t\tfor (i = 0; i <= 4; i++) {\n\t\t\tif (i > dm->num_rf_path)\n\t\t\t\tbreak;\n\n\t\t\todm_memory_set(dm, tmp_rssi_avg, 0, 4);\n\t\t\todm_memory_set(dm, tmp_snr_avg, 0, 4);\n\t\t\todm_memory_set(dm, tmp_evm_avg, 0, 4);\n\n\t\t\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\t\t\tif (i == 4) {\n\t\t\t\trate_type = \"[4-SS]\";\n\t\t\t\ttmp_cnt = dbg_s->rssi_4ss_cnt;\n\t\t\t\todm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_4ss_avg, dm->num_rf_path);\n\t\t\t\todm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_4ss_avg, dm->num_rf_path);\n\t\t\t\todm_move_memory(dm, tmp_evm_avg, dbg_avg->evm_4ss_avg, 4);\n\t\t\t} else\n\t\t\t#endif\n\t\t\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\t\t\tif (i == 3) {\n\t\t\t\trate_type = \"[3-SS]\";\n\t\t\t\ttmp_cnt = dbg_s->rssi_3ss_cnt;\n\t\t\t\todm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_3ss_avg, dm->num_rf_path);\n\t\t\t\todm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_3ss_avg, dm->num_rf_path);\n\t\t\t\todm_move_memory(dm, tmp_evm_avg, dbg_avg->evm_3ss_avg, 3);\n\t\t\t} else\n\t\t\t#endif\n\t\t\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\t\t\tif (i == 2) {\n\t\t\t\trate_type = \"[2-SS]\";\n\t\t\t\ttmp_cnt = dbg_s->rssi_2ss_cnt;\n\t\t\t\todm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_2ss_avg, dm->num_rf_path);\n\t\t\t\todm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_2ss_avg, dm->num_rf_path);\n\t\t\t\todm_move_memory(dm, tmp_evm_avg, dbg_avg->evm_2ss_avg, 2);\n\t\t\t} else\n\t\t\t#endif\n\t\t\tif (i == 1) {\n\t\t\t\trate_type = \"[1-SS]\";\n\t\t\t\ttmp_cnt = dbg_s->rssi_1ss_cnt;\n\t\t\t\todm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_1ss_avg, dm->num_rf_path);\n\t\t\t\todm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_1ss_avg, dm->num_rf_path);\n\t\t\t\todm_move_memory(dm, tmp_evm_avg, &dbg_avg->evm_1ss_avg, 1);\n\t\t\t} else {\n\t\t\t\trate_type = \"[L-OFDM]\";\n\t\t\t\ttmp_cnt = dbg_s->rssi_ofdm_cnt;\n\t\t\t\todm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_ofdm_avg, dm->num_rf_path);\n\t\t\t\todm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_ofdm_avg, dm->num_rf_path);\n\t\t\t\todm_move_memory(dm, tmp_evm_avg, &dbg_avg->evm_ofdm_avg, 1);\n\t\t\t}\n\n\t\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,\n\t\t\t\t   \"* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d} SNR:{%.2d, %.2d, %.2d, %.2d} EVM:{-%.2d, -%.2d, -%.2d, -%.2d}\\n\",\n\t\t\t\t    rate_type, tmp_cnt,\n\t\t\t\t    tmp_rssi_avg[0], tmp_rssi_avg[1], tmp_rssi_avg[2], tmp_rssi_avg[3],\n\t\t\t\t    tmp_snr_avg[0], tmp_snr_avg[1], tmp_snr_avg[2], tmp_snr_avg[3],\n\t\t\t\t    tmp_evm_avg[0], tmp_evm_avg[1], tmp_evm_avg[2], tmp_evm_avg[3]);\n\t\t\tRT_PRINT(buf);\n\t\t}\n#else\n\t\tphydm_reset_phystatus_avg(dm);\n\n\t\t/*@CCK*/\n\t\tdbg_avg->rssi_cck_avg = (u8)((dbg_s->rssi_cck_cnt != 0) ? (dbg_s->rssi_cck_sum / dbg_s->rssi_cck_cnt) : 0);\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n * cck Cnt= ((%d)) RSSI:{%d}\",\n\t\t\t   dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg);\n\t\tRT_PRINT(buf);\n\n\t\t/*OFDM*/\n\t\tif (dbg_s->rssi_ofdm_cnt != 0) {\n\t\t\tdbg_avg->rssi_ofdm_avg = (u8)(dbg_s->rssi_ofdm_sum / dbg_s->rssi_ofdm_cnt);\n\t\t\tdbg_avg->evm_ofdm_avg = (u8)(dbg_s->evm_ofdm_sum / dbg_s->rssi_ofdm_cnt);\n\t\t\tdbg_avg->snr_ofdm_avg = (u8)(dbg_s->snr_ofdm_sum / dbg_s->rssi_ofdm_cnt);\n\t\t}\n\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n * ofdm Cnt= ((%d)) RSSI:{%d} EVM:{%d} SNR:{%d}\",\n\t\t\t   dbg_s->rssi_ofdm_cnt, dbg_avg->rssi_ofdm_avg,\n\t\t\t   dbg_avg->evm_ofdm_avg, dbg_avg->snr_ofdm_avg);\n\t\tRT_PRINT(buf);\n\n\t\tif (dbg_s->rssi_1ss_cnt != 0) {\n\t\t\tdbg_avg->rssi_1ss_avg = (u8)(dbg_s->rssi_1ss_sum / dbg_s->rssi_1ss_cnt);\n\t\t\tdbg_avg->evm_1ss_avg = (u8)(dbg_s->evm_1ss_sum / dbg_s->rssi_1ss_cnt);\n\t\t\tdbg_avg->snr_1ss_avg = (u8)(dbg_s->snr_1ss_sum / dbg_s->rssi_1ss_cnt);\n\t\t}\n\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n * 1-ss Cnt= ((%d)) RSSI:{%d} EVM:{%d} SNR:{%d}\",\n\t\t\t   dbg_s->rssi_1ss_cnt, dbg_avg->rssi_1ss_avg,\n\t\t\t   dbg_avg->evm_1ss_avg, dbg_avg->snr_1ss_avg);\n\t\tRT_PRINT(buf);\n\n#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\t\tif (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) {\n\t\t\tif (dbg_s->rssi_2ss_cnt != 0) {\n\t\t\t\tdbg_avg->rssi_2ss_avg[0] = (u8)(dbg_s->rssi_2ss_sum[0] / dbg_s->rssi_2ss_cnt);\n\t\t\t\tdbg_avg->rssi_2ss_avg[1] = (u8)(dbg_s->rssi_2ss_sum[1] / dbg_s->rssi_2ss_cnt);\n\n\t\t\t\tdbg_avg->evm_2ss_avg[0] = (u8)(dbg_s->evm_2ss_sum[0] / dbg_s->rssi_2ss_cnt);\n\t\t\t\tdbg_avg->evm_2ss_avg[1] = (u8)(dbg_s->evm_2ss_sum[1] / dbg_s->rssi_2ss_cnt);\n\n\t\t\t\tdbg_avg->snr_2ss_avg[0] = (u8)(dbg_s->snr_2ss_sum[0] / dbg_s->rssi_2ss_cnt);\n\t\t\t\tdbg_avg->snr_2ss_avg[1] = (u8)(dbg_s->snr_2ss_sum[1] / dbg_s->rssi_2ss_cnt);\n\t\t\t}\n\n\t\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n * 2-ss Cnt= ((%d)) RSSI:{%d, %d}, EVM:{%d, %d}, SNR:{%d, %d}\",\n\t\t\t\t   dbg_s->rssi_2ss_cnt, dbg_avg->rssi_2ss_avg[0],\n\t\t\t\t   dbg_avg->rssi_2ss_avg[1], dbg_avg->evm_2ss_avg[0],\n\t\t\t\t   dbg_avg->evm_2ss_avg[1], dbg_avg->snr_2ss_avg[0],\n\t\t\t\t   dbg_avg->snr_2ss_avg[1]);\n\t\t\tRT_PRINT(buf);\n\t\t}\n#endif\n\n#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\t\tif (dm->support_ic_type & (PHYDM_IC_ABOVE_3SS)) {\n\t\t\tif (dbg_s->rssi_3ss_cnt != 0) {\n\t\t\t\tdbg_avg->rssi_3ss_avg[0] = (u8)(dbg_s->rssi_3ss_sum[0] / dbg_s->rssi_3ss_cnt);\n\t\t\t\tdbg_avg->rssi_3ss_avg[1] = (u8)(dbg_s->rssi_3ss_sum[1] / dbg_s->rssi_3ss_cnt);\n\t\t\t\tdbg_avg->rssi_3ss_avg[2] = (u8)(dbg_s->rssi_3ss_sum[2] / dbg_s->rssi_3ss_cnt);\n\n\t\t\t\tdbg_avg->evm_3ss_avg[0] = (u8)(dbg_s->evm_3ss_sum[0] / dbg_s->rssi_3ss_cnt);\n\t\t\t\tdbg_avg->evm_3ss_avg[1] = (u8)(dbg_s->evm_3ss_sum[1] / dbg_s->rssi_3ss_cnt);\n\t\t\t\tdbg_avg->evm_3ss_avg[2] = (u8)(dbg_s->evm_3ss_sum[2] / dbg_s->rssi_3ss_cnt);\n\n\t\t\t\tdbg_avg->snr_3ss_avg[0] = (u8)(dbg_s->snr_3ss_sum[0] / dbg_s->rssi_3ss_cnt);\n\t\t\t\tdbg_avg->snr_3ss_avg[1] = (u8)(dbg_s->snr_3ss_sum[1] / dbg_s->rssi_3ss_cnt);\n\t\t\t\tdbg_avg->snr_3ss_avg[2] = (u8)(dbg_s->snr_3ss_sum[2] / dbg_s->rssi_3ss_cnt);\n\t\t\t}\n\n\t\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n * 3-ss Cnt= ((%d)) RSSI:{%d, %d, %d} EVM:{%d, %d, %d} SNR:{%d, %d, %d}\",\n\t\t\t\t   dbg_s->rssi_3ss_cnt, dbg_avg->rssi_3ss_avg[0],\n\t\t\t\t   dbg_avg->rssi_3ss_avg[1], dbg_avg->rssi_3ss_avg[2],\n\t\t\t\t   dbg_avg->evm_3ss_avg[0], dbg_avg->evm_3ss_avg[1],\n\t\t\t\t   dbg_avg->evm_3ss_avg[2], dbg_avg->snr_3ss_avg[0],\n\t\t\t\t   dbg_avg->snr_3ss_avg[1], dbg_avg->snr_3ss_avg[2]);\n\t\t\tRT_PRINT(buf);\n\t\t}\n#endif\n\n#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\t\tif (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {\n\t\t\tif (dbg_s->rssi_4ss_cnt != 0) {\n\t\t\t\tdbg_avg->rssi_4ss_avg[0] = (u8)(dbg_s->rssi_4ss_sum[0] / dbg_s->rssi_4ss_cnt);\n\t\t\t\tdbg_avg->rssi_4ss_avg[1] = (u8)(dbg_s->rssi_4ss_sum[1] / dbg_s->rssi_4ss_cnt);\n\t\t\t\tdbg_avg->rssi_4ss_avg[2] = (u8)(dbg_s->rssi_4ss_sum[2] / dbg_s->rssi_4ss_cnt);\n\t\t\t\tdbg_avg->rssi_4ss_avg[3] = (u8)(dbg_s->rssi_4ss_sum[3] / dbg_s->rssi_4ss_cnt);\n\n\t\t\t\tdbg_avg->evm_4ss_avg[0] = (u8)(dbg_s->evm_4ss_sum[0] / dbg_s->rssi_4ss_cnt);\n\t\t\t\tdbg_avg->evm_4ss_avg[1] = (u8)(dbg_s->evm_4ss_sum[1] / dbg_s->rssi_4ss_cnt);\n\t\t\t\tdbg_avg->evm_4ss_avg[2] = (u8)(dbg_s->evm_4ss_sum[2] / dbg_s->rssi_4ss_cnt);\n\t\t\t\tdbg_avg->evm_4ss_avg[3] = (u8)(dbg_s->evm_4ss_sum[3] / dbg_s->rssi_4ss_cnt);\n\n\t\t\t\tdbg_avg->snr_4ss_avg[0] = (u8)(dbg_s->snr_4ss_sum[0] / dbg_s->rssi_4ss_cnt);\n\t\t\t\tdbg_avg->snr_4ss_avg[1] = (u8)(dbg_s->snr_4ss_sum[1] / dbg_s->rssi_4ss_cnt);\n\t\t\t\tdbg_avg->snr_4ss_avg[2] = (u8)(dbg_s->snr_4ss_sum[2] / dbg_s->rssi_4ss_cnt);\n\t\t\t\tdbg_avg->snr_4ss_avg[3] = (u8)(dbg_s->snr_4ss_sum[3] / dbg_s->rssi_4ss_cnt);\n\t\t\t}\n\n\t\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n * 4-ss Cnt= ((%d)) RSSI:{%d, %d, %d, %d} EVM:{%d, %d, %d, %d} SNR:{%d, %d, %d, %d}\",\n\t\t\t\t   dbg_s->rssi_4ss_cnt, dbg_avg->rssi_4ss_avg[0],\n\t\t\t\t   dbg_avg->rssi_4ss_avg[1], dbg_avg->rssi_4ss_avg[2],\n\t\t\t\t   dbg_avg->rssi_4ss_avg[3], dbg_avg->evm_4ss_avg[0],\n\t\t\t\t   dbg_avg->evm_4ss_avg[1], dbg_avg->evm_4ss_avg[2],\n\t\t\t\t   dbg_avg->evm_4ss_avg[3], dbg_avg->snr_4ss_avg[0],\n\t\t\t\t   dbg_avg->snr_4ss_avg[1], dbg_avg->snr_4ss_avg[2],\n\t\t\t\t   dbg_avg->snr_4ss_avg[3]);\n\t\t\tRT_PRINT(buf);\n\t\t}\n#endif\n#endif\n\t\tphydm_reset_phystatus_statistic(dm);\n\t\t/*@----------------------------------------------------------*/\n\n\t\t/*Print TX rate*/\n\t\tfor (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {\n\t\t\tentry = dm->phydm_sta_info[macid];\n\n\t\t\tif (is_sta_active(entry)) {\n\t\t\t\tphydm_print_rate_2_buff(dm, entry->ra_info.curr_tx_rate, dbg_buf, PHYDM_SNPRINT_SIZE);\n\t\t\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n TxRate[%d]=%s (0x%x)\", macid, dbg_buf, entry->ra_info.curr_tx_rate);\n\t\t\t\tRT_PRINT(buf);\n\t\t\t\ttarget_macid = macid;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,\n\t\t\t   \"\\r\\n TP {Tx, Rx, Total} = {%d, %d, %d}Mbps, Traffic_Load=(%d))\",\n\t\t\t   dm->tx_tp, dm->rx_tp, dm->total_tp, dm->traffic_load);\n\t\tRT_PRINT(buf);\n\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n CFO_avg=((%d kHz)), CFO_traking = ((%s%d))\",\n\t\t\t   cfo_t->CFO_ave_pre,\n\t\t\t   ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? \"+\" : \"-\"),\n\t\t\t   DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap));\n\t\tRT_PRINT(buf);\n\n\t\t/* @Condition number */\n\t\t#if (RTL8822B_SUPPORT)\n\t\tif (dm->support_ic_type == ODM_RTL8822B) {\n\t\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n Condi_Num=((%d.%.4d))\",\n\t\t\t\t   dm->phy_dbg_info.condi_num >> 4,\n\t\t\t\t   phydm_show_fraction_num(dm->phy_dbg_info.condi_num & 0xf, 4));\n\t\t\tRT_PRINT(buf);\n\t\t}\n\t\t#endif\n\n#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT))\n\t\t/*STBC or LDPC pkt*/\n\t\tif (dm->support_ic_type & (PHYSTS_2ND_TYPE_IC |\n\t\t\t\t\t   PHYSTS_3RD_TYPE_IC))\n\t\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n Coding: LDPC=((%s)), STBC=((%s))\",\n\t\t\t\t   (dm->phy_dbg_info.is_ldpc_pkt) ? \"Y\" : \"N\",\n\t\t\t\t   (dm->phy_dbg_info.is_stbc_pkt) ? \"Y\" : \"N\");\n\t\t\tRT_PRINT(buf);\n#endif\n\n\t} else {\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n No Link !!!\");\n\t\tRT_PRINT(buf);\n\t}\n\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n [CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\",\n\t\t   fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);\n\tRT_PRINT(buf);\n\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, \"\\r\\n [FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\",\n\t\t   fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all);\n\tRT_PRINT(buf);\n\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,\n\t\t   \"\\r\\n [CRC32 OK Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\",\n\t\t   fa_t->cnt_cck_crc32_ok,\n\t\t   fa_t->cnt_crc32_ok_all - fa_t->cnt_cck_crc32_ok,\n\t\t   fa_t->cnt_crc32_ok_all);\n\tRT_PRINT(buf);\n\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,\n\t\t   \"\\r\\n [CRC32 Err Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\",\n\t\t   fa_t->cnt_cck_crc32_error,\n\t\t   fa_t->cnt_crc32_error_all - fa_t->cnt_cck_crc32_error,\n\t\t   fa_t->cnt_crc32_error_all);\n\tRT_PRINT(buf);\n\n\t#if (ODM_IC_11N_SERIES_SUPPORT)\n\tif (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,\n\t\t\t   \"\\r\\n [OFDM FA Detail] Parity_Fail=%d, Rate_Illegal=%d, CRC8=%d, MCS_fail=%d, Fast_sync=%d, SB_Search_fail=%d\",\n\t\t\t   fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,\n\t\t\t   fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail,\n\t\t\t   fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail);\n\t\tRT_PRINT(buf);\n\t}\n\t#endif\n\tRT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,\n\t\t   \"\\r\\n is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x, bNoisy=%d\\n\",\n\t\t   dm->is_linked, dm->number_linked_client, dm->rssi_min,\n\t\t   dm->dm_dig_table.cur_ig_value, dm->noisy_decision);\n\tRT_PRINT(buf);\n\n\tphydm_dm_summary_cli_win(dm, buf, target_macid);\n}\n\n#ifdef CONFIG_PHYDM_DEBUG_FUNCTION\nvoid phydm_sbd_check(\n\tstruct dm_struct *dm)\n{\n\tstatic u32 pkt_cnt;\n\tstatic boolean sbd_state;\n\tu32 sym_count, count, value32;\n\n\tif (sbd_state == 0) {\n\t\tpkt_cnt++;\n\t\t/*read SBD conter once every 5 packets*/\n\t\tif (pkt_cnt % 5 == 0) {\n\t\t\todm_set_timer(dm, &dm->sbdcnt_timer, 0); /*@ms*/\n\t\t\tsbd_state = 1;\n\t\t}\n\t} else { /*read counter*/\n\t\tvalue32 = odm_get_bb_reg(dm, R_0xf98, MASKDWORD);\n\t\tsym_count = (value32 & 0x7C000000) >> 26;\n\t\tcount = (value32 & 0x3F00000) >> 20;\n\t\tpr_debug(\"#SBD# sym_count %d count %d\\n\", sym_count, count);\n\t\tsbd_state = 0;\n\t}\n}\n#endif\n\nvoid phydm_sbd_callback(\n\tstruct phydm_timer_list *timer)\n{\n#ifdef CONFIG_PHYDM_DEBUG_FUNCTION\n\tvoid *adapter = timer->Adapter;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\n#if USE_WORKITEM\n\todm_schedule_work_item(&dm->sbdcnt_workitem);\n#else\n\tphydm_sbd_check(dm);\n#endif\n#endif\n}\n\nvoid phydm_sbd_workitem_callback(\n\tvoid *context)\n{\n#ifdef CONFIG_PHYDM_DEBUG_FUNCTION\n\tvoid *adapter = (void *)context;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\n\tphydm_sbd_check(dm);\n#endif\n}\n#endif\n\nvoid phydm_reset_rx_rate_distribution(struct dm_struct *dm)\n{\n\tstruct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;\n\n\todm_memory_set(dm, &dbg->num_qry_legacy_pkt[0], 0,\n\t\t       (LEGACY_RATE_NUM * 2));\n\todm_memory_set(dm, &dbg->num_qry_ht_pkt[0], 0,\n\t\t       (HT_RATE_NUM * 2));\n\todm_memory_set(dm, &dbg->num_qry_pkt_sc_20m[0], 0,\n\t\t       (LOW_BW_RATE_NUM * 2));\n\n\tdbg->ht_pkt_not_zero = false;\n\tdbg->low_bw_20_occur = false;\n\n#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))\n\todm_memory_set(dm, &dbg->num_qry_vht_pkt[0], 0, VHT_RATE_NUM * 2);\n\todm_memory_set(dm, &dbg->num_qry_pkt_sc_40m[0], 0, LOW_BW_RATE_NUM * 2);\n\t#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) || (defined(PHYSTS_3RD_TYPE_SUPPORT))\n\todm_memory_set(dm, &dbg->num_mu_vht_pkt[0], 0, VHT_RATE_NUM * 2);\n\t#endif\n\tdbg->vht_pkt_not_zero = false;\n\tdbg->low_bw_40_occur = false;\n#endif\n}\n\nvoid phydm_rx_rate_distribution(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;\n\tu8 i = 0;\n\tu8 rate_num = dm->num_rf_path, ss_ofst = 0;\n\n\tPHYDM_DBG(dm, DBG_CMN, \"[RxRate Cnt] =============>\\n\");\n\n\t/*@======CCK=========================================================*/\n\tif (*dm->channel <= 14) {\n\t\tPHYDM_DBG(dm, DBG_CMN, \"* CCK = {%d, %d, %d, %d}\\n\",\n\t\t\t  dbg->num_qry_legacy_pkt[0],\n\t\t\t  dbg->num_qry_legacy_pkt[1],\n\t\t\t  dbg->num_qry_legacy_pkt[2],\n\t\t\t  dbg->num_qry_legacy_pkt[3]);\n\t}\n\t/*@======OFDM========================================================*/\n\tPHYDM_DBG(dm, DBG_CMN, \"* OFDM = {%d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t  dbg->num_qry_legacy_pkt[4], dbg->num_qry_legacy_pkt[5],\n\t\t  dbg->num_qry_legacy_pkt[6], dbg->num_qry_legacy_pkt[7],\n\t\t  dbg->num_qry_legacy_pkt[8], dbg->num_qry_legacy_pkt[9],\n\t\t  dbg->num_qry_legacy_pkt[10], dbg->num_qry_legacy_pkt[11]);\n\n\t/*@======HT==========================================================*/\n\tif (dbg->ht_pkt_not_zero) {\n\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\tss_ofst = (i << 3);\n\n\t\t\tPHYDM_DBG(dm, DBG_CMN,\n\t\t\t\t  \"* HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t\t\t  (ss_ofst), (ss_ofst + 7),\n\t\t\t\t  dbg->num_qry_ht_pkt[ss_ofst + 0],\n\t\t\t\t  dbg->num_qry_ht_pkt[ss_ofst + 1],\n\t\t\t\t  dbg->num_qry_ht_pkt[ss_ofst + 2],\n\t\t\t\t  dbg->num_qry_ht_pkt[ss_ofst + 3],\n\t\t\t\t  dbg->num_qry_ht_pkt[ss_ofst + 4],\n\t\t\t\t  dbg->num_qry_ht_pkt[ss_ofst + 5],\n\t\t\t\t  dbg->num_qry_ht_pkt[ss_ofst + 6],\n\t\t\t\t  dbg->num_qry_ht_pkt[ss_ofst + 7]);\n\t\t}\n\n\t\tif (dbg->low_bw_20_occur) {\n\t\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\t\tss_ofst = (i << 3);\n\n\t\t\t\tPHYDM_DBG(dm, DBG_CMN,\n\t\t\t\t\t  \"* [Low BW 20M] HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t\t\t\t  (ss_ofst), (ss_ofst + 7),\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 0],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 1],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 2],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 3],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 4],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 5],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 6],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 7]);\n\t\t\t}\n\t\t}\n\t}\n\n#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))\n\t/*@======VHT==========================================================*/\n\tif (dbg->vht_pkt_not_zero) {\n\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\tss_ofst = 10 * i;\n\n\t\t\tPHYDM_DBG(dm, DBG_CMN,\n\t\t\t\t  \"* VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t\t\t  (i + 1),\n\t\t\t\t  dbg->num_qry_vht_pkt[ss_ofst + 0],\n\t\t\t\t  dbg->num_qry_vht_pkt[ss_ofst + 1],\n\t\t\t\t  dbg->num_qry_vht_pkt[ss_ofst + 2],\n\t\t\t\t  dbg->num_qry_vht_pkt[ss_ofst + 3],\n\t\t\t\t  dbg->num_qry_vht_pkt[ss_ofst + 4],\n\t\t\t\t  dbg->num_qry_vht_pkt[ss_ofst + 5],\n\t\t\t\t  dbg->num_qry_vht_pkt[ss_ofst + 6],\n\t\t\t\t  dbg->num_qry_vht_pkt[ss_ofst + 7],\n\t\t\t\t  dbg->num_qry_vht_pkt[ss_ofst + 8],\n\t\t\t\t  dbg->num_qry_vht_pkt[ss_ofst + 9]);\n\t\t}\n\n\t\tif (dbg->low_bw_20_occur) {\n\t\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\t\tss_ofst = 10 * i;\n\n\t\t\t\tPHYDM_DBG(dm, DBG_CMN,\n\t\t\t\t\t  \"*[Low BW 20M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t\t\t\t  (i + 1),\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 0],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 1],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 2],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 3],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 4],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 5],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 6],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 7],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 8],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_20m[ss_ofst + 9]);\n\t\t\t}\n\t\t}\n\n\t\tif (dbg->low_bw_40_occur) {\n\t\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\t\tss_ofst = 10 * i;\n\n\t\t\t\tPHYDM_DBG(dm, DBG_CMN,\n\t\t\t\t\t  \"*[Low BW 40M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t\t\t\t  (i + 1),\n\t\t\t\t\t  dbg->num_qry_pkt_sc_40m[ss_ofst + 0],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_40m[ss_ofst + 1],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_40m[ss_ofst + 2],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_40m[ss_ofst + 3],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_40m[ss_ofst + 4],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_40m[ss_ofst + 5],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_40m[ss_ofst + 6],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_40m[ss_ofst + 7],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_40m[ss_ofst + 8],\n\t\t\t\t\t  dbg->num_qry_pkt_sc_40m[ss_ofst + 9]);\n\t\t\t}\n\t\t}\n\t}\n#endif\n}\n\nu16 phydm_rx_utility(void *dm_void, u16 avg_phy_rate, u8 rx_max_ss,\n\t\t     enum channel_width bw)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;\n\tu16 utility_primitive = 0, utility = 0;\n\n\tif (dbg->ht_pkt_not_zero) {\n\t/*@ MCS7 20M: tp = 65, 1000/65 = 15.38, 65*15.5 = 1007*/\n\t\tutility_primitive = avg_phy_rate * 15 + (avg_phy_rate >> 1);\n\t}\n#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))\n\telse if (dbg->vht_pkt_not_zero) {\n\t/*@ VHT 1SS MCS9(fake) 20M: tp = 90, 1000/90 = 11.11, 65*11.125 = 1001*/\n\t\tutility_primitive = avg_phy_rate * 11 + (avg_phy_rate >> 3);\n\t}\n#endif\n\telse {\n\t/*@ 54M, 1000/54 = 18.5, 54*18.5 = 999*/\n\t\tutility_primitive = avg_phy_rate * 18 + (avg_phy_rate >> 1);\n\t}\n\n\tutility = (utility_primitive / rx_max_ss) >> bw;\n\n\tif (utility > 1000)\n\t\tutility = 1000;\n\n\treturn utility;\n}\n\nu16 phydm_rx_avg_phy_rate(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;\n\tu8 i = 0, rate_num = 0, rate_base = 0;\n\tu16 rate = 0, avg_phy_rate = 0;\n\tu32 pkt_cnt = 0, phy_rate_sum = 0;\n\n\tif (dbg->ht_pkt_not_zero) {\n\t\trate_num = HT_RATE_NUM;\n\t\trate_base = ODM_RATEMCS0;\n\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\trate = phy_rate_table[i + rate_base] << *dm->band_width;\n\t\t\tphy_rate_sum += dbg->num_qry_ht_pkt[i] * rate;\n\t\t\tpkt_cnt += dbg->num_qry_ht_pkt[i];\n\t\t}\n\t}\n#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))\n\telse if (dbg->vht_pkt_not_zero) {\n\t\trate_num = VHT_RATE_NUM;\n\t\trate_base = ODM_RATEVHTSS1MCS0;\n\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\trate = phy_rate_table[i + rate_base] << *dm->band_width;\n\t\t\tphy_rate_sum += dbg->num_qry_vht_pkt[i] * rate;\n\t\t\tpkt_cnt += dbg->num_qry_vht_pkt[i];\n\t\t}\n\t}\n#endif\n\telse {\n\t\tfor (i = ODM_RATE1M; i <= ODM_RATE54M; i++) {\n\t\t\t/*SKIP 1M & 6M for beacon case*/\n\t\t\tif (*dm->channel < 36 && i == ODM_RATE1M)\n\t\t\t\tcontinue;\n\n\t\t\tif (*dm->channel >= 36 && i == ODM_RATE6M)\n\t\t\t\tcontinue;\n\n\t\t\trate = phy_rate_table[i];\n\t\t\tphy_rate_sum += dbg->num_qry_legacy_pkt[i] * rate;\n\t\t\tpkt_cnt += dbg->num_qry_legacy_pkt[i];\n\t\t}\n\t}\n\n#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))\n\tif (dbg->low_bw_40_occur) {\n\t\tfor (i = 0; i < LOW_BW_RATE_NUM; i++) {\n\t\t\trate = phy_rate_table[i + rate_base]\n\t\t\t       << CHANNEL_WIDTH_40;\n\t\t\tphy_rate_sum += dbg->num_qry_pkt_sc_40m[i] * rate;\n\t\t\tpkt_cnt += dbg->num_qry_pkt_sc_40m[i];\n\t\t}\n\t}\n#endif\n\n\tif (dbg->low_bw_20_occur) {\n\t\tfor (i = 0; i < LOW_BW_RATE_NUM; i++) {\n\t\t\trate = phy_rate_table[i + rate_base];\n\t\t\tphy_rate_sum += dbg->num_qry_pkt_sc_20m[i] * rate;\n\t\t\tpkt_cnt += dbg->num_qry_pkt_sc_20m[i];\n\t\t}\n\t}\n\n\tavg_phy_rate = (pkt_cnt == 0) ? 0 : (u16)(phy_rate_sum / pkt_cnt);\n\n\treturn avg_phy_rate;\n}\n\nvoid phydm_print_hist_2_buf(void *dm_void, u16 *val, u16 len, char *buf,\n\t\t\t    u16 buf_size)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (len == PHY_HIST_SIZE) {\n\t\tPHYDM_SNPRINTF(buf, buf_size,\n\t\t\t       \"[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]\",\n\t\t\t       val[0], val[1], val[2], val[3], val[4],\n\t\t\t       val[5], val[6], val[7], val[8], val[9],\n\t\t\t       val[10], val[11]);\n\t} else if (len == (PHY_HIST_SIZE - 1)) {\n\t\tPHYDM_SNPRINTF(buf, buf_size,\n\t\t\t       \"[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]\",\n\t\t\t       val[0], val[1], val[2], val[3], val[4],\n\t\t\t       val[5], val[6], val[7], val[8], val[9],\n\t\t\t       val[10]);\n\t}\n}\n\nvoid phydm_nss_hitogram(void *dm_void, enum PDM_RATE_TYPE rate_type)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;\n\tstruct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;\n\tchar buf[PHYDM_SNPRINT_SIZE] = {0};\n\tu16 buf_size = PHYDM_SNPRINT_SIZE;\n\tu16 h_size = PHY_HIST_SIZE;\n\tu16 *evm_hist = &dbg_s->evm_1ss_hist[0];\n\tu16 *snr_hist = &dbg_s->snr_1ss_hist[0];\n\tu8 i = 0;\n\tu8 ss = phydm_rate_type_2_num_ss(dm, rate_type);\n\n\tfor (i = 0; i < ss; i++) {\n\t\tif (rate_type == PDM_1SS) {\n\t\t\tevm_hist = &dbg_s->evm_1ss_hist[0];\n\t\t\tsnr_hist = &dbg_s->snr_1ss_hist[0];\n\t\t} else if (rate_type == PDM_2SS) {\n\t\t\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\t\t\tevm_hist = &dbg_s->evm_2ss_hist[i][0];\n\t\t\tsnr_hist = &dbg_s->snr_2ss_hist[i][0];\n\t\t\t#endif\n\t\t} else if (rate_type == PDM_3SS) {\n\t\t\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\t\t\tevm_hist = &dbg_s->evm_3ss_hist[i][0];\n\t\t\tsnr_hist = &dbg_s->snr_3ss_hist[i][0];\n\t\t\t#endif\n\t\t} else if (rate_type == PDM_4SS) {\n\t\t\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\t\t\tevm_hist = &dbg_s->evm_4ss_hist[i][0];\n\t\t\tsnr_hist = &dbg_s->snr_4ss_hist[i][0];\n\t\t\t#endif\n\t\t}\n\n\t\tphydm_print_hist_2_buf(dm, evm_hist, h_size, buf, buf_size);\n\t\tPHYDM_DBG(dm, DBG_CMN, \"[%d-SS][EVM][%d]=%s\\n\", ss, i, buf);\n\t\tphydm_print_hist_2_buf(dm, snr_hist, h_size, buf, buf_size);\n\t\tPHYDM_DBG(dm, DBG_CMN, \"[%d-SS][SNR][%d]=%s\\n\",  ss, i, buf);\n\t}\n}\n\nvoid phydm_show_phy_hitogram(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;\n\tstruct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;\n\tchar buf[PHYDM_SNPRINT_SIZE] = {0};\n\tu16 buf_size = PHYDM_SNPRINT_SIZE;\n\tu16 th_size = PHY_HIST_SIZE - 1;\n\tu8 i = 0;\n\n\tPHYDM_DBG(dm, DBG_CMN, \"[PHY Histogram] ==============>\\n\");\n/*@===[Threshold]=============================================================*/\n\tphydm_print_hist_2_buf(dm, dbg_i->evm_hist_th, th_size, buf, buf_size);\n\tPHYDM_DBG(dm, DBG_CMN, \"%-16s=%s\\n\", \"[EVM_TH]\", buf);\n\n\tphydm_print_hist_2_buf(dm, dbg_i->snr_hist_th, th_size, buf, buf_size);\n\tPHYDM_DBG(dm, DBG_CMN, \"%-16s=%s\\n\", \"[SNR_TH]\", buf);\n/*@===[OFDM]==================================================================*/\n\tif (dbg_s->rssi_ofdm_cnt) {\n\t\tphydm_print_hist_2_buf(dm, dbg_s->evm_ofdm_hist, PHY_HIST_SIZE,\n\t\t\t\t       buf, buf_size);\n\t\tPHYDM_DBG(dm, DBG_CMN, \"%-14s=%s\\n\", \"[OFDM][EVM]\", buf);\n\n\t\tphydm_print_hist_2_buf(dm, dbg_s->snr_ofdm_hist, PHY_HIST_SIZE,\n\t\t\t\t       buf, buf_size);\n\t\tPHYDM_DBG(dm, DBG_CMN, \"%-14s=%s\\n\", \"[OFDM][SNR]\", buf);\n\t}\n/*@===[1-SS]==================================================================*/\n\tif (dbg_s->rssi_1ss_cnt)\n\t\tphydm_nss_hitogram(dm, PDM_1SS);\n/*@===[2-SS]==================================================================*/\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tif ((dm->support_ic_type & PHYDM_IC_ABOVE_2SS) && dbg_s->rssi_2ss_cnt)\n\t\tphydm_nss_hitogram(dm, PDM_2SS);\n\t#endif\n/*@===[3-SS]==================================================================*/\n\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\tif ((dm->support_ic_type & PHYDM_IC_ABOVE_3SS) && dbg_s->rssi_3ss_cnt)\n\t\tphydm_nss_hitogram(dm, PDM_3SS);\n\t#endif\n/*@===[4-SS]==================================================================*/\n\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\tif (dm->support_ic_type & PHYDM_IC_ABOVE_4SS && dbg_s->rssi_4ss_cnt)\n\t\tphydm_nss_hitogram(dm, PDM_4SS);\n\t#endif\n}\n\nvoid phydm_avg_phy_val_nss(void *dm_void, u8 nss)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;\n\tstruct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;\n\tstruct phydm_phystatus_avg *dbg_avg = &dbg_i->phystatus_statistic_avg;\n\tchar *rate_type = NULL;\n\tu32 *tmp_cnt = NULL;\n\tu8 *tmp_rssi_avg = NULL;\n\tu32 *tmp_rssi_sum = NULL;\n\tu8 *tmp_snr_avg = NULL;\n\tu32 *tmp_snr_sum = NULL;\n\tu8 *tmp_evm_avg = NULL;\n\tu32 *tmp_evm_sum = NULL;\n\tu8 evm_rpt_show[RF_PATH_MEM_SIZE];\n\tu8 i = 0;\n\n\todm_memory_set(dm, &evm_rpt_show[0], 0, RF_PATH_MEM_SIZE);\n\n\tswitch (nss) {\n\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\tcase 4:\n\t\trate_type = \"[4-SS]\";\n\t\ttmp_cnt = &dbg_s->rssi_4ss_cnt;\n\t\ttmp_rssi_avg = &dbg_avg->rssi_4ss_avg[0];\n\t\ttmp_snr_avg = &dbg_avg->snr_4ss_avg[0];\n\t\ttmp_rssi_sum = &dbg_s->rssi_4ss_sum[0];\n\t\ttmp_snr_sum = &dbg_s->snr_4ss_sum[0];\n\t\ttmp_evm_avg = &dbg_avg->evm_4ss_avg[0];\n\t\ttmp_evm_sum = &dbg_s->evm_4ss_sum[0];\n\t\tbreak;\n\t#endif\n\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\tcase 3:\n\t\trate_type = \"[3-SS]\";\n\t\ttmp_cnt = &dbg_s->rssi_3ss_cnt;\n\t\ttmp_rssi_avg = &dbg_avg->rssi_3ss_avg[0];\n\t\ttmp_snr_avg = &dbg_avg->snr_3ss_avg[0];\n\t\ttmp_rssi_sum = &dbg_s->rssi_3ss_sum[0];\n\t\ttmp_snr_sum = &dbg_s->snr_3ss_sum[0];\n\t\ttmp_evm_avg = &dbg_avg->evm_3ss_avg[0];\n\t\ttmp_evm_sum = &dbg_s->evm_3ss_sum[0];\n\t\tbreak;\n\t#endif\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tcase 2:\n\t\trate_type = \"[2-SS]\";\n\t\ttmp_cnt = &dbg_s->rssi_2ss_cnt;\n\t\ttmp_rssi_avg = &dbg_avg->rssi_2ss_avg[0];\n\t\ttmp_snr_avg = &dbg_avg->snr_2ss_avg[0];\n\t\ttmp_rssi_sum = &dbg_s->rssi_2ss_sum[0];\n\t\ttmp_snr_sum = &dbg_s->snr_2ss_sum[0];\n\t\ttmp_evm_avg = &dbg_avg->evm_2ss_avg[0];\n\t\ttmp_evm_sum = &dbg_s->evm_2ss_sum[0];\n\t\tbreak;\n\t#endif\n\tcase 1:\n\t\trate_type = \"[1-SS]\";\n\t\ttmp_cnt = &dbg_s->rssi_1ss_cnt;\n\t\ttmp_rssi_avg = &dbg_avg->rssi_1ss_avg[0];\n\t\ttmp_snr_avg = &dbg_avg->snr_1ss_avg[0];\n\t\ttmp_rssi_sum = &dbg_s->rssi_1ss_sum[0];\n\t\ttmp_snr_sum = &dbg_s->snr_1ss_sum[0];\n\t\ttmp_evm_avg = &dbg_avg->evm_1ss_avg;\n\t\ttmp_evm_sum = &dbg_s->evm_1ss_sum;\n\t\tbreak;\n\tdefault:\n\t\trate_type = \"[L-OFDM]\";\n\t\ttmp_cnt = &dbg_s->rssi_ofdm_cnt;\n\t\ttmp_rssi_avg = &dbg_avg->rssi_ofdm_avg[0];\n\t\ttmp_snr_avg = &dbg_avg->snr_ofdm_avg[0];\n\t\ttmp_rssi_sum = &dbg_s->rssi_ofdm_sum[0];\n\t\ttmp_snr_sum = &dbg_s->snr_ofdm_sum[0];\n\t\ttmp_evm_avg = &dbg_avg->evm_ofdm_avg;\n\t\ttmp_evm_sum = &dbg_s->evm_ofdm_sum;\n\t\tbreak;\n\t}\n\n\tif (*tmp_cnt != 0) {\n\t\tfor (i = 0; i < dm->num_rf_path; i++) {\n\t\t\ttmp_rssi_avg[i] = (u8)(tmp_rssi_sum[i] / *tmp_cnt);\n\t\t\ttmp_snr_avg[i] = (u8)(tmp_snr_sum[i] / *tmp_cnt);\n\t\t}\n\n\t\tif (nss > 1) {\n\t\t\tfor (i = 0; i < nss; i++) {\n\t\t\t\ttmp_evm_avg[i] = (u8)(tmp_evm_sum[i] /\n\t\t\t\t\t\t      *tmp_cnt);\n\t\t\t\tevm_rpt_show[i] = tmp_evm_avg[i];\n\t\t\t}\n\t\t} else {\n\t\t\t*tmp_evm_avg = (u8)(*tmp_evm_sum / *tmp_cnt);\n\t\t\tevm_rpt_show[0] = *tmp_evm_avg;\n\t\t}\n\t}\n\n#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\tPHYDM_DBG(dm, DBG_CMN,\n\t\t  \"* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d} SNR:{%.2d, %.2d, %.2d, %.2d} EVM:{-%.2d, -%.2d, -%.2d, -%.2d}\\n\",\n\t\t  rate_type, *tmp_cnt,\n\t\t  tmp_rssi_avg[0], tmp_rssi_avg[1], tmp_rssi_avg[2],\n\t\t  tmp_rssi_avg[3], tmp_snr_avg[0], tmp_snr_avg[1],\n\t\t  tmp_snr_avg[2], tmp_snr_avg[3], evm_rpt_show[0],\n\t\t  evm_rpt_show[1], evm_rpt_show[2], evm_rpt_show[3]);\n#elif (defined(PHYDM_COMPILE_ABOVE_3SS))\n\tPHYDM_DBG(dm, DBG_CMN,\n\t\t  \"* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d} SNR:{%.2d, %.2d, %.2d} EVM:{-%.2d, -%.2d, -%.2d}\\n\",\n\t\t  rate_type, *tmp_cnt,\n\t\t  tmp_rssi_avg[0], tmp_rssi_avg[1], tmp_rssi_avg[2],\n\t\t  tmp_snr_avg[0], tmp_snr_avg[1], tmp_snr_avg[2],\n\t\t  evm_rpt_show[0], evm_rpt_show[1], evm_rpt_show[2]);\n#elif (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tPHYDM_DBG(dm, DBG_CMN,\n\t\t  \"* %-8s Cnt= ((%.3d)) RSSI:{%.2d, %.2d} SNR:{%.2d, %.2d} EVM:{-%.2d, -%.2d}\\n\",\n\t\t  rate_type, *tmp_cnt,\n\t\t  tmp_rssi_avg[0], tmp_rssi_avg[1],\n\t\t  tmp_snr_avg[0], tmp_snr_avg[1],\n\t\t  evm_rpt_show[0], evm_rpt_show[1]);\n#else\n\tPHYDM_DBG(dm, DBG_CMN,\n\t\t  \"* %-8s Cnt= ((%.3d)) RSSI:{%.2d} SNR:{%.2d} EVM:{-%.2d}\\n\",\n\t\t  rate_type, *tmp_cnt,\n\t\t  tmp_rssi_avg[0], tmp_snr_avg[0], evm_rpt_show[0]);\n#endif\n}\n\nvoid phydm_get_avg_phystatus_val(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;\n\tstruct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;\n\tstruct phydm_phystatus_avg *dbg_avg = &dbg_i->phystatus_statistic_avg;\n\tu8 i = 0;\n\n\tPHYDM_DBG(dm, DBG_CMN, \"[PHY Avg] ==============>\\n\");\n\tphydm_reset_phystatus_avg(dm);\n\n\t/*@===[Beacon]===*/\n\tif (dbg_s->rssi_beacon_cnt) {\n\t\tdbg_avg->rssi_beacon_avg = (u8)(dbg_s->rssi_beacon_sum /\n\t\t\t\t\t\tdbg_s->rssi_beacon_cnt);\n\t}\n\tPHYDM_DBG(dm, DBG_CMN, \"* %-8s Cnt=((%.3d)) RSSI:{%.2d}\\n\",\n\t\t  \"[Beacon]\", dbg_s->rssi_beacon_cnt, dbg_avg->rssi_beacon_avg);\n\n\t/*@===[CCK]===*/\n\tif (dbg_s->rssi_cck_cnt) {\n\t\tdbg_avg->rssi_cck_avg = (u8)(dbg_s->rssi_cck_sum /\n\t\t\t\t\t     dbg_s->rssi_cck_cnt);\n\t}\n\tPHYDM_DBG(dm, DBG_CMN, \"* %-8s Cnt=((%.3d)) RSSI:{%.2d}\\n\",\n\t\t  \"[CCK]\", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg);\n\n#if 1\n\tfor (i = 0; i <= 4; i++) {\n\t\tif (i > dm->num_rf_path)\n\t\t\tbreak;\n\n\t\tphydm_avg_phy_val_nss(dm, i);\n\t}\n#else\n\t/*@===[OFDM]===*/\n\tphydm_avg_phy_val_nss(dm, 0);\n\t/*@===[1-SS]===*/\n\tphydm_avg_phy_val_nss(dm, 1);\n\t/*@===[2-SS]===*/\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tif (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS))\n\t\tphydm_avg_phy_val_nss(dm, 2);\n\t#endif\n\t/*@===[3-SS]===*/\n\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\tif (dm->support_ic_type & (PHYDM_IC_ABOVE_3SS))\n\t\tphydm_avg_phy_val_nss(dm, 3);\n\t#endif\n\t/*@===[4-SS]===*/\n\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\tif (dm->support_ic_type & PHYDM_IC_ABOVE_4SS)\n\t\tphydm_avg_phy_val_nss(dm, 4);\n\t#endif\n#endif\n}\n\nvoid phydm_get_phy_statistic(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct cmn_sta_info *sta = dm->phydm_sta_info[dm->one_entry_macid];\n\tenum channel_width bw;\n\tu16 avg_phy_rate = 0;\n\tu16 utility = 0;\n\tu8 rx_ss = 1;\n\n\tavg_phy_rate = phydm_rx_avg_phy_rate(dm);\n\n\tif (dm->is_one_entry_only && is_sta_active(sta)) {\n\t\trx_ss = phydm_get_rx_stream_num(dm, sta->mimo_type);\n\t\tbw = sta->bw_mode;\n\t\tutility = phydm_rx_utility(dm, avg_phy_rate, rx_ss, bw);\n\t}\n\tPHYDM_DBG(dm, DBG_CMN, \"Avg_rx_rate = %d, rx_utility=( %d / 1000 )\\n\",\n\t\t  avg_phy_rate, utility);\n\n\tphydm_rx_rate_distribution(dm);\n\tphydm_reset_rx_rate_distribution(dm);\n\n\tphydm_show_phy_hitogram(dm);\n\tphydm_get_avg_phystatus_val(dm);\n\tphydm_reset_phystatus_statistic(dm);\n};\n\nvoid phydm_basic_dbg_msg_linked(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track;\n\tstruct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info;\n\tu16 macid, client_cnt = 0;\n\tu8 rate = 0;\n\tstruct cmn_sta_info *entry = NULL;\n\tchar dbg_buf[PHYDM_SNPRINT_SIZE] = {0};\n\tstruct phydm_cfo_rpt cfo;\n\tu8 i = 0;\n\n\tPHYDM_DBG(dm, DBG_CMN, \"ID=((%d)), BW=((%d)), fc=((CH-%d))\\n\",\n\t\t  dm->curr_station_id, 20 << *dm->band_width, *dm->channel);\n\n\t#ifdef ODM_IC_11N_SERIES_SUPPORT\n\t#ifdef PHYDM_PRIMARY_CCA\n\tif (((*dm->channel <= 14) && (*dm->band_width == CHANNEL_WIDTH_40)) &&\n\t    (dm->support_ic_type & ODM_IC_11N_SERIES)) {\n\t\tPHYDM_DBG(dm, DBG_CMN, \"Primary CCA at ((%s SB))\\n\",\n\t\t\t  ((*dm->sec_ch_offset == SECOND_CH_AT_LSB) ? \"U\" :\n\t\t\t  \"L\"));\n\t}\n\t#endif\n\t#endif\n\n\tif ((dm->support_ic_type & PHYSTS_2ND_TYPE_IC) ||\n\t    dm->rx_rate > ODM_RATE11M) {\n\t\tPHYDM_DBG(dm, DBG_CMN, \"[AGC Idx] {0x%x, 0x%x, 0x%x, 0x%x}\\n\",\n\t\t\t  dm->ofdm_agc_idx[0], dm->ofdm_agc_idx[1],\n\t\t\t  dm->ofdm_agc_idx[2], dm->ofdm_agc_idx[3]);\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_CMN, \"[CCK AGC Idx] {LNA,VGA}={0x%x, 0x%x}\\n\",\n\t\t\t  dm->cck_lna_idx, dm->cck_vga_idx);\n\t}\n\n\tphydm_print_rate_2_buff(dm, dm->rx_rate, dbg_buf, PHYDM_SNPRINT_SIZE);\n\tPHYDM_DBG(dm, DBG_CMN, \"RSSI:{%d, %d, %d, %d}, RxRate:%s (0x%x)\\n\",\n\t\t  (dm->rssi_a == 0xff) ? 0 : dm->rssi_a,\n\t\t  (dm->rssi_b == 0xff) ? 0 : dm->rssi_b,\n\t\t  (dm->rssi_c == 0xff) ? 0 : dm->rssi_c,\n\t\t  (dm->rssi_d == 0xff) ? 0 : dm->rssi_d,\n\t\t  dbg_buf, dm->rx_rate);\n\n\trate = dbg_t->beacon_phy_rate;\n\tphydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE);\n\n\tPHYDM_DBG(dm, DBG_CMN, \"Beacon_cnt=%d, rate_idx=%s (0x%x)\\n\",\n\t\t  dbg_t->num_qry_beacon_pkt, dbg_buf, dbg_t->beacon_phy_rate);\n\n\tphydm_get_phy_statistic(dm);\n\n\tPHYDM_DBG(dm, DBG_CMN,\n\t\t  \"rxsc_idx {Legacy, 20, 40, 80} = {%d, %d, %d, %d}\\n\",\n\t\t  dm->rxsc_l, dm->rxsc_20, dm->rxsc_40, dm->rxsc_80);\n\n\t/*Print TX rate*/\n\tfor (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {\n\t\tentry = dm->phydm_sta_info[macid];\n\n\t\tif (!is_sta_active(entry))\n\t\t\tcontinue;\n\n\t\trate = entry->ra_info.curr_tx_rate;\n\t\tphydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE);\n\t\tPHYDM_DBG(dm, DBG_CMN, \"TxRate[%d]=%s (0x%x)\\n\",\n\t\t\t  macid, dbg_buf, entry->ra_info.curr_tx_rate);\n\n\t\tclient_cnt++;\n\n\t\tif (client_cnt >= dm->number_linked_client)\n\t\t\tbreak;\n\t}\n\n\tPHYDM_DBG(dm, DBG_CMN,\n\t\t  \"TP {Tx, Rx, Total} = {%d, %d, %d}Mbps, Traffic_Load=(%d))\\n\",\n\t\t  dm->tx_tp, dm->rx_tp, dm->total_tp, dm->traffic_load);\n\n\tPHYDM_DBG(dm, DBG_CMN, \"CFO_avg=((%d kHz)), CFO_traking = ((%s%d))\\n\",\n\t\t  cfo_t->CFO_ave_pre,\n\t\t  ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? \"+\" : \"-\"),\n\t\t  DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap));\n\n\t/* @CFO report */\n\tswitch (dm->ic_ip_series) {\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\tcase PHYDM_IC_JGR3:\n\t\tPHYDM_DBG(dm, DBG_CMN, \"cfo_tail = {%d, %d, %d, %d}\\n\",\n\t\t\t  dbg_t->cfo_tail[0], dbg_t->cfo_tail[1],\n\t\t\t  dbg_t->cfo_tail[2], dbg_t->cfo_tail[3]);\n\t\tbreak;\n\t#endif\n\tdefault:\n\t\tphydm_get_cfo_info(dm, &cfo);\n\t\tfor (i = 0; i < dm->num_rf_path; i++) {\n\t\t\tPHYDM_DBG(dm, DBG_CMN,\n\t\t\t\t  \"CFO[%d] {S, L, Sec, Acq, End} = {%d, %d, %d, %d, %d}\\n\",\n\t\t\t\t  i, cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i],\n\t\t\t\t  cfo.cfo_rpt_sec[i], cfo.cfo_rpt_acq[i],\n\t\t\t\t  cfo.cfo_rpt_end[i]);\n\t\t}\n\t\tbreak;\n\t}\n\n/* @Condition number */\n#if (RTL8822B_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8822B) {\n\t\tPHYDM_DBG(dm, DBG_CMN, \"Condi_Num=((%d.%.4d)), %d\\n\",\n\t\t\t  dbg_t->condi_num >> 4,\n\t\t\t  phydm_show_fraction_num(dbg_t->condi_num & 0xf, 4),\n\t\t\t  dbg_t->condi_num);\n\t}\n#endif\n#ifdef PHYSTS_3RD_TYPE_SUPPORT\n\tif (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) {\n\t\tPHYDM_DBG(dm, DBG_CMN, \"Condi_Num=((%d.%4d dB))\\n\",\n\t\t\t  dbg_t->condi_num >> 1,\n\t\t\t  phydm_show_fraction_num(dbg_t->condi_num & 0x1, 1));\n\t}\n#endif\n\n#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT))\n\t/*STBC or LDPC pkt*/\n\tif (dm->support_ic_type & (PHYSTS_2ND_TYPE_IC | PHYSTS_3RD_TYPE_IC))\n\t\tPHYDM_DBG(dm, DBG_CMN, \"Coding: LDPC=((%s)), STBC=((%s))\\n\",\n\t\t\t  (dbg_t->is_ldpc_pkt) ? \"Y\" : \"N\",\n\t\t\t  (dbg_t->is_stbc_pkt) ? \"Y\" : \"N\");\n#endif\n\n#if (RTL8822C_SUPPORT)\n\t/*Beamformed pkt*/\n\tif (dm->support_ic_type == ODM_RTL8822C)\n\t\tPHYDM_DBG(dm, DBG_CMN, \"Beamformed=((%s))\\n\",\n\t\t\t  (dm->is_beamformed) ? \"Y\" : \"N\");\n#endif\n}\n\nvoid phydm_dm_summary(void *dm_void, u8 macid)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track;\n\tstruct cmn_sta_info *sta = NULL;\n\tstruct ra_sta_info *ra = NULL;\n\tstruct dtp_info *dtp = NULL;\n\tu64 comp = dm->support_ability;\n\tu64 pause_comp = dm->pause_ability;\n\n\tif (!(dm->debug_components & DBG_DM_SUMMARY))\n\t\treturn;\n\n\tif (!dm->is_linked) {\n\t\tpr_debug(\"[%s]No Link !!!\\n\", __func__);\n\t\treturn;\n\t}\n\n\tsta = dm->phydm_sta_info[macid];\n\n\tif (!is_sta_active(sta)) {\n\t\tpr_debug(\"[Warning] %s invalid STA, macid=%d\\n\",\n\t\t\t __func__, macid);\n\t\treturn;\n\t}\n\n\tra = &sta->ra_info;\n\tdtp = &sta->dtp_stat;\n\tpr_debug(\"[%s]===========>\\n\", __func__);\n\n\tpr_debug(\"00.(%s) %-12s: IGI=0x%x, Dyn_Rng=0x%x~0x%x, FA_th={%d,%d,%d}\\n\",\n\t\t ((comp & ODM_BB_DIG) ?\n\t\t ((pause_comp & ODM_BB_DIG) ? \"P\" : \"V\") : \".\"),\n\t\t \"DIG\",\n\t\t dig_t->cur_ig_value,\n\t\t dig_t->rx_gain_range_min, dig_t->rx_gain_range_max,\n\t\t dig_t->fa_th[0], dig_t->fa_th[1], dig_t->fa_th[2]);\n\n\tpr_debug(\"01.(%s) %-12s: rssi_lv=%d, mask=0x%llx\\n\",\n\t\t ((comp & ODM_BB_RA_MASK) ?\n\t\t ((pause_comp & ODM_BB_RA_MASK) ? \"P\" : \"V\") : \".\"),\n\t\t \"RaMask\",\n\t\t ra->rssi_level, ra->ramask);\n\n#ifdef CONFIG_DYNAMIC_TX_TWR\n\tpr_debug(\"02.(%s) %-12s: pwr_lv=%d\\n\",\n\t\t ((comp & ODM_BB_DYNAMIC_TXPWR) ?\n\t\t ((pause_comp & ODM_BB_DYNAMIC_TXPWR) ? \"P\" : \"V\") : \".\"),\n\t\t \"DynTxPwr\",\n\t\t dtp->sta_tx_high_power_lvl);\n#endif\n\n\tpr_debug(\"05.(%s) %-12s: cck_pd_lv=%d\\n\",\n\t\t ((comp & ODM_BB_CCK_PD) ?\n\t\t ((pause_comp & ODM_BB_CCK_PD) ? \"P\" : \"V\") : \".\"),\n\t\t \"CCK_PD\", dm->dm_cckpd_table.cck_pd_lv);\n\n#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\tpr_debug(\"06.(%s) %-12s: div_type=%d, curr_ant=%s\\n\",\n\t\t ((comp & ODM_BB_ANT_DIV) ?\n\t\t ((pause_comp & ODM_BB_ANT_DIV) ? \"P\" : \"V\") : \".\"),\n\t\t \"ANT_DIV\",\n\t\t dm->ant_div_type,\n\t\t (dm->dm_fat_table.rx_idle_ant == MAIN_ANT) ? \"MAIN\" : \"AUX\");\n#endif\n\n#ifdef PHYDM_POWER_TRAINING_SUPPORT\n\tpr_debug(\"08.(%s) %-12s: PT_score=%d, disable_PT=%d\\n\",\n\t\t ((comp & ODM_BB_PWR_TRAIN) ?\n\t\t ((pause_comp & ODM_BB_PWR_TRAIN) ? \"P\" : \"V\") : \".\"),\n\t\t \"PwrTrain\",\n\t\t dm->pow_train_table.pow_train_score,\n\t\t dm->is_disable_power_training);\n#endif\n\n#ifdef CONFIG_PHYDM_DFS_MASTER\n\tpr_debug(\"11.(%s) %-12s: dbg_mode=%d, region_domain=%d\\n\",\n\t\t ((comp & ODM_BB_DFS) ?\n\t\t ((pause_comp & ODM_BB_DFS) ? \"P\" : \"V\") : \".\"),\n\t\t \"DFS\",\n\t\t dm->dfs.dbg_mode, dm->dfs_region_domain);\n#endif\n#ifdef PHYDM_SUPPORT_ADAPTIVITY\n\tpr_debug(\"13.(%s) %-12s: th{l2h, h2l}={%d, %d}, edcca_flag=%d\\n\",\n\t\t ((comp & ODM_BB_ADAPTIVITY) ?\n\t\t ((pause_comp & ODM_BB_ADAPTIVITY) ? \"P\" : \"V\") : \".\"),\n\t\t \"Adaptivity\",\n\t\t dm->adaptivity.th_l2h, dm->adaptivity.th_h2l,\n\t\t dm->false_alm_cnt.edcca_flag);\n#endif\n\tpr_debug(\"14.(%s) %-12s: CFO_avg=%d kHz, CFO_traking=%s%d\\n\",\n\t\t ((comp & ODM_BB_CFO_TRACKING) ?\n\t\t ((pause_comp & ODM_BB_CFO_TRACKING) ? \"P\" : \"V\") : \".\"),\n\t\t \"CfoTrack\",\n\t\t cfo_t->CFO_ave_pre,\n\t\t ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? \"+\" : \"-\"),\n\t\t DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap));\n\n\tpr_debug(\"15.(%s) %-12s: ratio{nhm, clm}={%d, %d}\\n\",\n\t\t ((comp & ODM_BB_ENV_MONITOR) ?\n\t\t ((pause_comp & ODM_BB_ENV_MONITOR) ? \"P\" : \"V\") : \".\"),\n\t\t \"EnvMntr\",\n\t\t dm->dm_ccx_info.nhm_ratio, dm->dm_ccx_info.clm_ratio);\n\n#ifdef PHYDM_PRIMARY_CCA\n\tpr_debug(\"16.(%s) %-12s: CCA @ (%s SB)\\n\",\n\t\t ((comp & ODM_BB_PRIMARY_CCA) ?\n\t\t ((pause_comp & ODM_BB_PRIMARY_CCA) ? \"P\" : \"V\") : \".\"),\n\t\t \"PriCCA\",\n\t\t ((dm->dm_pri_cca.mf_state == MF_USC_LSC) ? \"D\" :\n\t\t ((dm->dm_pri_cca.mf_state == MF_LSC) ? \"L\" : \"U\")));\n#endif\n#ifdef CONFIG_ADAPTIVE_SOML\n\tpr_debug(\"17.(%s) %-12s: soml_en = %s\\n\",\n\t\t ((comp & ODM_BB_ADAPTIVE_SOML) ?\n\t\t ((pause_comp & ODM_BB_ADAPTIVE_SOML) ? \"P\" : \"V\") : \".\"),\n\t\t \"A-SOML\",\n\t\t (dm->dm_soml_table.soml_last_state == SOML_ON) ?\n\t\t \"ON\" : \"OFF\");\n#endif\n#ifdef PHYDM_LNA_SAT_CHK_SUPPORT\n\tpr_debug(\"18.(%s) %-12s:\\n\",\n\t\t ((comp & ODM_BB_LNA_SAT_CHK) ?\n\t\t ((pause_comp & ODM_BB_LNA_SAT_CHK) ? \"P\" : \"V\") : \".\"),\n\t\t \"LNA_SAT_CHK\");\n#endif\n}\n\nvoid phydm_basic_dbg_message(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fa_struct *fa_t = &dm->false_alm_cnt;\n\n\t#ifdef ROKU_PRIVATE\n\t/*if (!(dm->debug_components & DBG_CMN))*/\n\t/*\treturn;\t\t\t\t*/\n\t# else\n\tif (!(dm->debug_components & DBG_CMN))\n\t\treturn;\n\t#endif /*ROKU_PRIVATE*/\n\n\tif (dm->cmn_dbg_msg_cnt >= dm->cmn_dbg_msg_period) {\n\t\tdm->cmn_dbg_msg_cnt = PHYDM_WATCH_DOG_PERIOD;\n\t} else {\n\t\tdm->cmn_dbg_msg_cnt += PHYDM_WATCH_DOG_PERIOD;\n\t\treturn;\n\t}\n\n\tPHYDM_DBG(dm, DBG_CMN, \"[%s] System up time: ((%d sec))---->\\n\",\n\t\t  __func__, dm->phydm_sys_up_time);\n\n\tif (dm->is_linked)\n\t\tphydm_basic_dbg_msg_linked(dm);\n\telse\n\t\tPHYDM_DBG(dm, DBG_CMN, \"No Link !!!\\n\");\n\n\tPHYDM_DBG(dm, DBG_CMN, \"[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\\n\",\n\t\t  fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);\n\n\tPHYDM_DBG(dm, DBG_CMN, \"[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\\n\",\n\t\t  fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all);\n\n\tPHYDM_DBG(dm, DBG_CMN,\n\t\t  \"[CRC32 OK Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\",\n\t\t  fa_t->cnt_cck_crc32_ok,\n\t\t  fa_t->cnt_crc32_ok_all - fa_t->cnt_cck_crc32_ok,\n\t\t  fa_t->cnt_crc32_ok_all);\n\n\tPHYDM_DBG(dm, DBG_CMN,\n\t\t  \"[CRC32 Err Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\",\n\t\t  fa_t->cnt_cck_crc32_error,\n\t\t  fa_t->cnt_crc32_error_all - fa_t->cnt_cck_crc32_error,\n\t\t  fa_t->cnt_crc32_error_all);\n\n\tPHYDM_DBG(dm, DBG_CMN,\n\t\t  \"[OFDM FA Detail] Parity_Fail=%d, Rate_Illegal=%d, CRC8=%d, MCS_fail=%d, Fast_sync=%d, SB_Search_fail=%d\\n\",\n\t\t  fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,\n\t\t  fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail,\n\t\t  fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail);\n\n#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))\n\tif (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {\n\t\tPHYDM_DBG(dm, DBG_CMN,\n\t\t\t  \"[OFDM FA Detail VHT] CRC8_VHT=%d, MCS_Fail_VHT=%d\\n\",\n\t\t\t  fa_t->cnt_crc8_fail_vht, fa_t->cnt_mcs_fail_vht);\n\t}\n#endif\n\n\tPHYDM_DBG(dm, DBG_CMN,\n\t\t  \"is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x, bNoisy=%d\\n\\n\",\n\t\t  dm->is_linked, dm->number_linked_client, dm->rssi_min,\n\t\t  dm->dm_dig_table.cur_ig_value, dm->noisy_decision);\n}\n\nvoid phydm_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len)\n{\n#ifdef CONFIG_PHYDM_DEBUG_FUNCTION\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tchar *cut = NULL;\n\tchar *ic_type = NULL;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 date = 0;\n\tchar *commit_by = NULL;\n\tu32 release_ver = 0;\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"%-35s\\n\",\n\t\t \"% Basic Profile %\");\n\n\tif (dm->support_ic_type == ODM_RTL8188E) {\n#if (RTL8188E_SUPPORT)\n\t\tic_type = \"RTL8188E\";\n\t\tdate = RELEASE_DATE_8188E;\n\t\tcommit_by = COMMIT_BY_8188E;\n\t\trelease_ver = RELEASE_VERSION_8188E;\n#endif\n#if (RTL8812A_SUPPORT)\n\t} else if (dm->support_ic_type == ODM_RTL8812) {\n\t\tic_type = \"RTL8812A\";\n\t\tdate = RELEASE_DATE_8812A;\n\t\tcommit_by = COMMIT_BY_8812A;\n\t\trelease_ver = RELEASE_VERSION_8812A;\n#endif\n#if (RTL8821A_SUPPORT)\n\t} else if (dm->support_ic_type == ODM_RTL8821) {\n\t\tic_type = \"RTL8821A\";\n\t\tdate = RELEASE_DATE_8821A;\n\t\tcommit_by = COMMIT_BY_8821A;\n\t\trelease_ver = RELEASE_VERSION_8821A;\n#endif\n#if (RTL8192E_SUPPORT)\n\t} else if (dm->support_ic_type == ODM_RTL8192E) {\n\t\tic_type = \"RTL8192E\";\n\t\tdate = RELEASE_DATE_8192E;\n\t\tcommit_by = COMMIT_BY_8192E;\n\t\trelease_ver = RELEASE_VERSION_8192E;\n#endif\n#if (RTL8723B_SUPPORT)\n\t} else if (dm->support_ic_type == ODM_RTL8723B) {\n\t\tic_type = \"RTL8723B\";\n\t\tdate = RELEASE_DATE_8723B;\n\t\tcommit_by = COMMIT_BY_8723B;\n\t\trelease_ver = RELEASE_VERSION_8723B;\n#endif\n#if (RTL8814A_SUPPORT)\n\t} else if (dm->support_ic_type == ODM_RTL8814A) {\n\t\tic_type = \"RTL8814A\";\n\t\tdate = RELEASE_DATE_8814A;\n\t\tcommit_by = COMMIT_BY_8814A;\n\t\trelease_ver = RELEASE_VERSION_8814A;\n#endif\n#if (RTL8881A_SUPPORT)\n\t} else if (dm->support_ic_type == ODM_RTL8881A) {\n\t\tic_type = \"RTL8881A\";\n#endif\n#if (RTL8822B_SUPPORT)\n\t} else if (dm->support_ic_type == ODM_RTL8822B) {\n\t\tic_type = \"RTL8822B\";\n\t\tdate = RELEASE_DATE_8822B;\n\t\tcommit_by = COMMIT_BY_8822B;\n\t\trelease_ver = RELEASE_VERSION_8822B;\n#endif\n#if (RTL8197F_SUPPORT)\n\t} else if (dm->support_ic_type == ODM_RTL8197F) {\n\t\tic_type = \"RTL8197F\";\n\t\tdate = RELEASE_DATE_8197F;\n\t\tcommit_by = COMMIT_BY_8197F;\n\t\trelease_ver = RELEASE_VERSION_8197F;\n#endif\n#if (RTL8703B_SUPPORT)\n\t} else if (dm->support_ic_type == ODM_RTL8703B) {\n\t\tic_type = \"RTL8703B\";\n\t\tdate = RELEASE_DATE_8703B;\n\t\tcommit_by = COMMIT_BY_8703B;\n\t\trelease_ver = RELEASE_VERSION_8703B;\n#endif\n#if (RTL8195A_SUPPORT)\n\t} else if (dm->support_ic_type == ODM_RTL8195A) {\n\t\tic_type = \"RTL8195A\";\n#endif\n#if (RTL8188F_SUPPORT)\n\t} else if (dm->support_ic_type == ODM_RTL8188F) {\n\t\tic_type = \"RTL8188F\";\n\t\tdate = RELEASE_DATE_8188F;\n\t\tcommit_by = COMMIT_BY_8188F;\n\t\trelease_ver = RELEASE_VERSION_8188F;\n#endif\n#if (RTL8723D_SUPPORT)\n\t} else if (dm->support_ic_type == ODM_RTL8723D) {\n\t\tic_type = \"RTL8723D\";\n\t\tdate = RELEASE_DATE_8723D;\n\t\tcommit_by = COMMIT_BY_8723D;\n\t\trelease_ver = RELEASE_VERSION_8723D;\n#endif\n\t}\n\n/* @JJ ADD 20161014 */\n#if (RTL8710B_SUPPORT)\n\telse if (dm->support_ic_type == ODM_RTL8710B) {\n\t\tic_type = \"RTL8710B\";\n\t\tdate = RELEASE_DATE_8710B;\n\t\tcommit_by = COMMIT_BY_8710B;\n\t\trelease_ver = RELEASE_VERSION_8710B;\n\t}\n#endif\n\n#if (RTL8721D_SUPPORT)\n\telse if (dm->support_ic_type == ODM_RTL8721D) {\n\t\tic_type = \"RTL8721D\";\n\t\tdate = RELEASE_DATE_8721D;\n\t\tcommit_by = COMMIT_BY_8721D;\n\t\trelease_ver = RELEASE_VERSION_8721D;\n\t}\n#endif\n#if (RTL8821C_SUPPORT)\n\telse if (dm->support_ic_type == ODM_RTL8821C) {\n\t\tic_type = \"RTL8821C\";\n\t\tdate = RELEASE_DATE_8821C;\n\t\tcommit_by = COMMIT_BY_8821C;\n\t\trelease_ver = RELEASE_VERSION_8821C;\n\t}\n#endif\n\n/*@jj add 20170822*/\n#if (RTL8192F_SUPPORT)\n\telse if (dm->support_ic_type == ODM_RTL8192F) {\n\t\tic_type = \"RTL8192F\";\n\t\tdate = RELEASE_DATE_8192F;\n\t\tcommit_by = COMMIT_BY_8192F;\n\t\trelease_ver = RELEASE_VERSION_8192F;\n\t}\n#endif\n\n#if (RTL8198F_SUPPORT)\n\telse if (dm->support_ic_type == ODM_RTL8198F) {\n\t\tic_type = \"RTL8198F\";\n\t\tdate = RELEASE_DATE_8198F;\n\t\tcommit_by = COMMIT_BY_8198F;\n\t\trelease_ver = RELEASE_VERSION_8198F;\n\t}\n#endif\n\n#if (RTL8822C_SUPPORT)\n\telse if (dm->support_ic_type == ODM_RTL8822C) {\n\t\tic_type = \"RTL8822C\";\n\t\tdate = RELEASE_DATE_8822C;\n\t\tcommit_by = COMMIT_BY_8822C;\n\t\trelease_ver = RELEASE_VERSION_8822C;\n\t}\n#endif\n\n#if (RTL8812F_SUPPORT)\n\telse if (dm->support_ic_type == ODM_RTL8812F) {\n\t\tic_type = \"RTL8812F\";\n\t\tdate = RELEASE_DATE_8812F;\n\t\tcommit_by = COMMIT_BY_8812F;\n\t\trelease_ver = RELEASE_VERSION_8812F;\n\t}\n#endif\n\n#if (RTL8197G_SUPPORT)\n\telse if (dm->support_ic_type == ODM_RTL8197G) {\n\t\tic_type = \"RTL8197G\";\n\t\tdate = RELEASE_DATE_8197G;\n\t\tcommit_by = COMMIT_BY_8197G;\n\t\trelease_ver = RELEASE_VERSION_8197G;\n\t}\n#endif\n\n#if (RTL8814B_SUPPORT)\n\telse if (dm->support_ic_type == ODM_RTL8814B) {\n\t\tic_type = \"RTL8814B\";\n\t\tdate = RELEASE_DATE_8814B;\n\t\tcommit_by = COMMIT_BY_8814B;\n\t\trelease_ver = RELEASE_VERSION_8814B;\n\t}\n#endif\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"  %-35s: %s (MP Chip: %s)\\n\", \"IC type\", ic_type,\n\t\t dm->is_mp_chip ? \"Yes\" : \"No\");\n\n\tif (dm->cut_version == ODM_CUT_A)\n\t\tcut = \"A\";\n\telse if (dm->cut_version == ODM_CUT_B)\n\t\tcut = \"B\";\n\telse if (dm->cut_version == ODM_CUT_C)\n\t\tcut = \"C\";\n\telse if (dm->cut_version == ODM_CUT_D)\n\t\tcut = \"D\";\n\telse if (dm->cut_version == ODM_CUT_E)\n\t\tcut = \"E\";\n\telse if (dm->cut_version == ODM_CUT_F)\n\t\tcut = \"F\";\n\telse if (dm->cut_version == ODM_CUT_G)\n\t\tcut = \"G\";\n\telse if (dm->cut_version == ODM_CUT_H)\n\t\tcut = \"H\";\n\telse if (dm->cut_version == ODM_CUT_I)\n\t\tcut = \"I\";\n\telse if (dm->cut_version == ODM_CUT_J)\n\t\tcut = \"J\";\n\telse if (dm->cut_version == ODM_CUT_K)\n\t\tcut = \"K\";\n\telse if (dm->cut_version == ODM_CUT_L)\n\t\tcut = \"L\";\n\telse if (dm->cut_version == ODM_CUT_M)\n\t\tcut = \"M\";\n\telse if (dm->cut_version == ODM_CUT_N)\n\t\tcut = \"N\";\n\telse if (dm->cut_version == ODM_CUT_O)\n\t\tcut = \"O\";\n\telse if (dm->cut_version == ODM_CUT_TEST)\n\t\tcut = \"TEST\";\n\telse\n\t\tcut = \"UNKNOWN\";\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %d\\n\",\n\t\t \"RFE type\", dm->rfe_type);\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"Cut Ver\", cut);\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %d\\n\",\n\t\t \"PHY Para Ver\", odm_get_hw_img_version(dm));\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %d\\n\",\n\t\t \"PHY Para Commit date\", date);\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"PHY Para Commit by\", commit_by);\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %d\\n\",\n\t\t \"PHY Para Release Ver\", release_ver);\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"  %-35s: %d (Subversion: %d)\\n\", \"FW Ver\", dm->fw_version,\n\t\t dm->fw_sub_version);\n\n\t/* @1 PHY DM version List */\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"%-35s\\n\",\n\t\t \"% PHYDM version %\");\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"Code base\", PHYDM_CODE_BASE);\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"Release Date\", PHYDM_RELEASE_DATE);\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"Adaptivity\", ADAPTIVITY_VERSION);\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"DIG\", DIG_VERSION);\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"CFO Tracking\", CFO_TRACKING_VERSION);\n#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"AntDiv\", ANTDIV_VERSION);\n#endif\n#ifdef CONFIG_DYNAMIC_TX_TWR\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"Dynamic TxPower\", DYNAMIC_TXPWR_VERSION);\n#endif\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"RA Info\", RAINFO_VERSION);\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"AntDetect\", ANTDECT_VERSION);\n#endif\n#ifdef CONFIG_PATH_DIVERSITY\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"PathDiv\", PATHDIV_VERSION);\n#endif\n#ifdef CONFIG_ADAPTIVE_SOML\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"Adaptive SOML\", ADAPTIVE_SOML_VERSION);\n#endif\n#if (PHYDM_LA_MODE_SUPPORT)\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"LA mode\", DYNAMIC_LA_MODE);\n#endif\n#ifdef PHYDM_PRIMARY_CCA\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"Primary CCA\", PRIMARYCCA_VERSION);\n#endif\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"  %-35s: %s\\n\",\n\t\t \"DFS\", DFS_VERSION);\n\n#if (RTL8822B_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8822B)\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"  %-35s: %s\\n\", \"PHY config 8822B\",\n\t\t\t PHY_CONFIG_VERSION_8822B);\n\n#endif\n#if (RTL8197F_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8197F)\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"  %-35s: %s\\n\", \"PHY config 8197F\",\n\t\t\t PHY_CONFIG_VERSION_8197F);\n#endif\n\n/*@jj add 20170822*/\n#if (RTL8192F_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8192F)\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"  %-35s: %s\\n\", \"PHY config 8192F\",\n\t\t\t PHY_CONFIG_VERSION_8192F);\n#endif\n#if (RTL8721D_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8721D)\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"  %-35s: %s\\n\", \"PHY config 8721D\",\n\t\t\t PHY_CONFIG_VERSION_8721D);\n#endif\n\n\t*_used = used;\n\t*_out_len = out_len;\n\n#endif /*@#if CONFIG_PHYDM_DEBUG_FUNCTION*/\n}\n\n#ifdef CONFIG_PHYDM_DEBUG_FUNCTION\nvoid phydm_fw_trace_en_h2c(void *dm_void, boolean enable,\n\t\t\t   u32 fw_dbg_comp, u32 monitor_mode, u32 macid)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 h2c_parameter[7] = {0};\n\tu8 cmd_length;\n\n\tif (dm->support_ic_type & PHYDM_IC_3081_SERIES) {\n\t\th2c_parameter[0] = enable;\n\t\th2c_parameter[1] = (u8)(fw_dbg_comp & MASKBYTE0);\n\t\th2c_parameter[2] = (u8)((fw_dbg_comp & MASKBYTE1) >> 8);\n\t\th2c_parameter[3] = (u8)((fw_dbg_comp & MASKBYTE2) >> 16);\n\t\th2c_parameter[4] = (u8)((fw_dbg_comp & MASKBYTE3) >> 24);\n\t\th2c_parameter[5] = (u8)monitor_mode;\n\t\th2c_parameter[6] = (u8)macid;\n\t\tcmd_length = 7;\n\n\t} else {\n\t\th2c_parameter[0] = enable;\n\t\th2c_parameter[1] = (u8)monitor_mode;\n\t\th2c_parameter[2] = (u8)macid;\n\t\tcmd_length = 3;\n\t}\n\n\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t  \"[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\\n\",\n\t\t  enable, monitor_mode, macid);\n\n\todm_fill_h2c_cmd(dm, PHYDM_H2C_FW_TRACE_EN, cmd_length, h2c_parameter);\n}\n\nvoid phydm_get_per_path_txagc(void *dm_void, u8 path, u32 *_used, char *output,\n\t\t\t      u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 rate_idx = 0;\n\tu8 txagc = 0;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n#ifdef PHYDM_COMMON_API_SUPPORT\n\tif (!(dm->support_ic_type & CMN_API_SUPPORT_IC))\n\t\treturn;\n\n\tif (dm->num_rf_path == 1 && path > RF_PATH_A)\n\t\treturn;\n\telse if (dm->num_rf_path == 2 && path > RF_PATH_B)\n\t\treturn;\n\telse if (dm->num_rf_path == 3 && path > RF_PATH_C)\n\t\treturn;\n\telse if (dm->num_rf_path == 4 && path > RF_PATH_D)\n\t\treturn;\n\n\tfor (rate_idx = 0; rate_idx <= 0x53; rate_idx++) {\n\t\tif (!(dm->support_ic_type & PHYDM_IC_ABOVE_3SS) &&\n\t\t    ((rate_idx >= ODM_RATEMCS16 &&\n\t\t    rate_idx < ODM_RATEVHTSS1MCS0) ||\n\t\t    rate_idx >= ODM_RATEVHTSS3MCS0))\n\t\t\tcontinue;\n\n\t\tif (rate_idx == ODM_RATE1M)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"  %-35s\\n\", \"CCK====>\");\n\t\telse if (rate_idx == ODM_RATE6M)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"\\n  %-35s\\n\", \"OFDM====>\");\n\t\telse if (rate_idx == ODM_RATEMCS0)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"\\n  %-35s\\n\", \"HT 1ss====>\");\n\t\telse if (rate_idx == ODM_RATEMCS8)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"\\n  %-35s\\n\", \"HT 2ss====>\");\n\t\telse if (rate_idx == ODM_RATEMCS16)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"\\n  %-35s\\n\", \"HT 3ss====>\");\n\t\telse if (rate_idx == ODM_RATEMCS24)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"\\n  %-35s\\n\", \"HT 4ss====>\");\n\t\telse if (rate_idx == ODM_RATEVHTSS1MCS0)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"\\n  %-35s\\n\", \"VHT 1ss====>\");\n\t\telse if (rate_idx == ODM_RATEVHTSS2MCS0)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"\\n  %-35s\\n\", \"VHT 2ss====>\");\n\t\telse if (rate_idx == ODM_RATEVHTSS3MCS0)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"\\n  %-35s\\n\", \"VHT 3ss====>\");\n\t\telse if (rate_idx == ODM_RATEVHTSS4MCS0)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"\\n  %-35s\\n\", \"VHT 4ss====>\");\n\n\t\ttxagc = phydm_api_get_txagc(dm, (enum rf_path)path, rate_idx);\n\t\tif (config_phydm_read_txagc_check(txagc))\n\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t out_len - used, \"  0x%02x    \", txagc);\n\t\telse\n\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t out_len - used, \"  0x%s    \", \"xx\");\n\t}\n#endif\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_get_txagc(void *dm_void, u32 *_used, char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\t/* path-A */\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"%-35s\\n\",\n\t\t \"path-A====================\");\n\tphydm_get_per_path_txagc(dm, RF_PATH_A, &used, output, &out_len);\n\n\t/* path-B */\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"\\n%-35s\\n\",\n\t\t \"path-B====================\");\n\tphydm_get_per_path_txagc(dm, RF_PATH_B, &used, output, &out_len);\n\n\t/* path-C */\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"\\n%-35s\\n\",\n\t\t \"path-C====================\");\n\tphydm_get_per_path_txagc(dm, RF_PATH_C, &used, output, &out_len);\n\n\t/* path-D */\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"\\n%-35s\\n\",\n\t\t \"path-D====================\");\n\tphydm_get_per_path_txagc(dm, RF_PATH_D, &used, output, &out_len);\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_set_txagc(void *dm_void, u32 *const val, u32 *_used,\n\t\t     char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu8 i = 0;\n\tu32 pow = 0; /*power index*/\n\tu8 vht_start_rate = ODM_RATEVHTSS1MCS0;\n\tboolean rpt = true;\n\tenum rf_path path = RF_PATH_A;\n\n/*@val[1] = path*/\n/*@val[2] = hw_rate*/\n/*@val[3] = power_index*/\n\n#ifdef PHYDM_COMMON_API_SUPPORT\n\tif (!(dm->support_ic_type & CMN_API_SUPPORT_IC))\n\t\treturn;\n\n\tpath = (enum rf_path)val[1];\n\n\tif (val[1] >= dm->num_rf_path) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Write path-%d rate_idx-0x%x fail\\n\", val[1], val[2]);\n\t} else if ((u8)val[2] != 0xff) {\n\t\tif (phydm_api_set_txagc(dm, val[3], path, (u8)val[2], true))\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"Write path-%d rate_idx-0x%x = 0x%x\\n\",\n\t\t\t\t val[1], val[2], val[3]);\n\t\telse\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"Write path-%d rate index-0x%x fail\\n\",\n\t\t\t\t val[1], val[2]);\n\t} else {\n\n\t\tif (dm->support_ic_type &\n\t\t    (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)) {\n\t\t\tpow = (val[3] & 0x3f);\n\t\t\tpow = BYTE_DUPLICATE_2_DWORD(pow);\n\n\t\t\tfor (i = 0; i < ODM_RATEVHTSS2MCS9; i += 4)\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 0);\n\t\t} else if (dm->support_ic_type &\n\t\t\t   (ODM_RTL8197F | ODM_RTL8192F)) {\n\t\t\tpow = (val[3] & 0x3f);\n\t\t\tfor (i = 0; i <= ODM_RATEMCS15; i++)\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 0);\n\t\t} else if (dm->support_ic_type & ODM_RTL8198F) {\n\t\t\tpow = (val[3] & 0x7f);\n\t\t\tfor (i = 0; i <= ODM_RATEVHTSS4MCS9; i++)\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 0);\n\t\t} else if (dm->support_ic_type &\n\t\t\t   (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)) {\n\t\t\tpow = (val[3] & 0x7f);\n\t\t\tfor (i = 0; i <= ODM_RATEMCS15; i++)\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 0);\n\t\t\tfor (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++)\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 0);\n\t\t} else if (dm->support_ic_type &\n\t\t\t   (ODM_RTL8721D)) {\n\t\t\tpow = (val[3] & 0x3f);\n\t\t\tfor (i = 0; i <= ODM_RATEMCS7; i++)\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 0);\n\t\t}\n\n\t\tif (rpt)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"Write all TXAGC of path-%d = 0x%x\\n\",\n\t\t\t\t val[1], val[3]);\n\t\telse\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"Write all TXAGC of path-%d fail\\n\", val[1]);\n\t}\n\n#endif\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_shift_txagc(void *dm_void, u32 *const val, u32 *_used, char *output,\n\t\t       u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu8 i = 0;\n\tu32 pow = 0; /*Power index*/\n\tboolean rpt = true;\n\tu8 vht_start_rate = ODM_RATEVHTSS1MCS0;\n\tenum rf_path path = RF_PATH_A;\n\n#ifdef PHYDM_COMMON_API_SUPPORT\n\tif (!(dm->support_ic_type & CMN_API_SUPPORT_IC))\n\t\treturn;\n\n\tif (val[1] >= dm->num_rf_path) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Write path-%d fail\\n\", val[1]);\n\t\treturn;\n\t}\n\n\tpath = (enum rf_path)val[1];\n\n\tif ((u8)val[2] == 0) {\n\t/*@{0:-, 1:+} {Pwr Offset}*/\n\t\tif (dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)) {\n\t\t\tfor (i = 0; i <= ODM_RATEMCS7; i++) {\n\t\t\t\tpow = phydm_api_get_txagc(dm, path, i) - val[3];\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 1);\n\t\t\t}\n\t\t\tfor (i = vht_start_rate; i <= ODM_RATEVHTSS1MCS9; i++) {\n\t\t\t\tpow = phydm_api_get_txagc(dm, path, i) - val[3];\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 1);\n\t\t\t}\n\t\t} else if (dm->support_ic_type & (ODM_RTL8822B)) {\n\t\t\tfor (i = 0; i <= ODM_RATEMCS15; i++) {\n\t\t\t\tpow = phydm_api_get_txagc(dm, path, i) - val[3];\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 1);\n\t\t\t}\n\t\t\tfor (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++) {\n\t\t\t\tpow = phydm_api_get_txagc(dm, path, i) - val[3];\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 1);\n\t\t\t}\n\t\t} else if (dm->support_ic_type &\n\t\t\t   (ODM_RTL8197F | ODM_RTL8192F)) {\n\t\t\tfor (i = 0; i <= ODM_RATEMCS15; i++) {\n\t\t\t\tpow = phydm_api_get_txagc(dm, path, i) - val[3];\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 1);\n\t\t\t}\n\t\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t\trpt &= phydm_api_shift_txagc(dm, val[3], path, 0);\n\t\t} else if (dm->support_ic_type &\n\t\t\t   (ODM_RTL8721D)) {\n\t\t\tfor (i = 0; i <= ODM_RATEMCS7; i++) {\n\t\t\t\tpow = phydm_api_get_txagc(dm, path, i) - val[3];\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 1);\n\t\t\t}\n\t\t}\n\t} else if ((u8)val[2] == 1) {\n\t/*@{0:-, 1:+} {Pwr Offset}*/\n\t\tif (dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)) {\n\t\t\tfor (i = 0; i <= ODM_RATEMCS7; i++) {\n\t\t\t\tpow = phydm_api_get_txagc(dm, path, i) + val[3];\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 1);\n\t\t\t}\n\t\t\tfor (i = vht_start_rate; i <= ODM_RATEVHTSS1MCS9; i++) {\n\t\t\t\tpow = phydm_api_get_txagc(dm, path, i) + val[3];\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 1);\n\t\t\t}\n\t\t} else if (dm->support_ic_type & (ODM_RTL8822B)) {\n\t\t\tfor (i = 0; i <= ODM_RATEMCS15; i++) {\n\t\t\t\tpow = phydm_api_get_txagc(dm, path, i) + val[3];\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 1);\n\t\t\t}\n\t\t\tfor (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++) {\n\t\t\t\tpow = phydm_api_get_txagc(dm, path, i) + val[3];\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 1);\n\t\t\t}\n\t\t} else if (dm->support_ic_type &\n\t\t\t   (ODM_RTL8197F | ODM_RTL8192F)) {\n\t\t\tfor (i = 0; i <= ODM_RATEMCS15; i++) {\n\t\t\t\tpow = phydm_api_get_txagc(dm, path, i) + val[3];\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 1);\n\t\t\t}\n\t\t} else if (dm->support_ic_type & ODM_RTL8721D) {\n\t\t\tfor (i = 0; i <= ODM_RATEMCS7; i++) {\n\t\t\t\tpow = phydm_api_get_txagc(dm, path, i) + val[3];\n\t\t\t\trpt &= phydm_api_set_txagc(dm, pow, path, i, 1);\n\t\t\t}\n\t\t} else if (dm->support_ic_type &\n\t\t\t   (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)) {\n\t\t\trpt &= phydm_api_shift_txagc(dm, val[3], path, 1);\n\t\t}\n\t}\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[All rate] Set Path-%d Pow_idx: %s %d\\n\",\n\t\t\t val[1], (val[2] ? \"+\" : \"-\"), val[3]);\n\telse\n\t#endif\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[All rate] Set Path-%d Pow_idx: %s %d(%d.%s dB)\\n\",\n\t\t\t val[1], (val[2] ? \"+\" : \"-\"), val[3], val[3] >> 1,\n\t\t\t ((val[3] & 1) ? \"5\" : \"0\"));\n\n#endif\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_set_txagc_dbg(void *dm_void, char input[][16], u32 *_used,\n\t\t\t char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 var1[10] = {0};\n\tchar help[] = \"-h\";\n\tu8 i = 0, input_idx = 0;\n\n\tfor (i = 0; i < 5; i++) {\n\t\tif (input[i + 1]) {\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);\n\t\t\tinput_idx++;\n\t\t}\n\t}\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{Dis:0, En:1} {pathA~D(0~3)} {rate_idx(Hex), All_rate:0xff} {txagc_idx (Hex)}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{Pwr Shift(All rate):2} {pathA~D(0~3)} {0:-, 1:+} {Pwr Offset(Hex)}\\n\");\n\t} else if (var1[0] == 0) {\n\t\tdm->is_disable_phy_api = false;\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Disable API debug mode\\n\");\n\t} else if (var1[0] == 1) {\n\t\tdm->is_disable_phy_api = false;\n\t\t#ifdef CONFIG_TXAGC_DEBUG_8822C\n\t\tconfig_phydm_write_txagc_8822c(dm, var1[3],\n\t\t\t\t\t       (enum rf_path)var1[1],\n\t\t\t\t\t       (u8)var1[2]);\n\t\t#else\n\t\tphydm_set_txagc(dm, (u32 *)var1, &used, output, &out_len);\n\t\t#endif\n\t\tdm->is_disable_phy_api = true;\n\t} else if (var1[0] == 2) {\n\t\tPHYDM_SSCANF(input[4], DCMD_HEX, &var1[3]);\n\t\tdm->is_disable_phy_api = false;\n\t\tphydm_shift_txagc(dm, (u32 *)var1, &used, output, &out_len);\n\t\tdm->is_disable_phy_api = true;\n\t}\n\t#ifdef CONFIG_TXAGC_DEBUG_8822C\n\telse if (var1[0] == 3) {\n\t\tdm->is_disable_phy_api = false;\n\t\tphydm_txagc_tab_buff_show_8822c(dm);\n\t\tdm->is_disable_phy_api = true;\n\t} else if (var1[0] == 4) {\n\t\tdm->is_disable_phy_api = false;\n\t\tconfig_phydm_set_txagc_to_hw_8822c(dm);\n\t\tdm->is_disable_phy_api = true;\n\t}\n\t#endif\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_debug_trace(void *dm_void, char input[][16], u32 *_used,\n\t\t       char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu64 pre_debug_components, one = 1;\n\tu64 comp = 0;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 val[10] = {0};\n\tu8 i = 0;\n\n\tfor (i = 0; i < 5; i++) {\n\t\tif (input[i + 1])\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);\n\t}\n\tcomp = dm->debug_components;\n\tpre_debug_components = dm->debug_components;\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"\\n================================\\n\");\n\tif (val[0] == 100) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[DBG MSG] Component Selection\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"================================\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"00. (( %s ))DIG\\n\",\n\t\t\t ((comp & DBG_DIG) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"01. (( %s ))RA_MASK\\n\",\n\t\t\t ((comp & DBG_RA_MASK) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"02. (( %s ))DYN_TXPWR\\n\",\n\t\t\t ((comp & DBG_DYN_TXPWR) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"03. (( %s ))FA_CNT\\n\",\n\t\t\t ((comp & DBG_FA_CNT) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"04. (( %s ))RSSI_MNTR\\n\",\n\t\t\t ((comp & DBG_RSSI_MNTR) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"05. (( %s ))CCKPD\\n\",\n\t\t\t ((comp & DBG_CCKPD) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"06. (( %s ))ANT_DIV\\n\",\n\t\t\t ((comp & DBG_ANT_DIV) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"07. (( %s ))SMT_ANT\\n\",\n\t\t\t ((comp & DBG_SMT_ANT) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"08. (( %s ))PWR_TRAIN\\n\",\n\t\t\t ((comp & DBG_PWR_TRAIN) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"09. (( %s ))RA\\n\",\n\t\t\t ((comp & DBG_RA) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"10. (( %s ))PATH_DIV\\n\",\n\t\t\t ((comp & DBG_PATH_DIV) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"11. (( %s ))DFS\\n\",\n\t\t\t ((comp & DBG_DFS) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"12. (( %s ))DYN_ARFR\\n\",\n\t\t\t ((comp & DBG_DYN_ARFR) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"13. (( %s ))ADAPTIVITY\\n\",\n\t\t\t ((comp & DBG_ADPTVTY) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"14. (( %s ))CFO_TRK\\n\",\n\t\t\t ((comp & DBG_CFO_TRK) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"15. (( %s ))ENV_MNTR\\n\",\n\t\t\t ((comp & DBG_ENV_MNTR) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"16. (( %s ))PRI_CCA\\n\",\n\t\t\t ((comp & DBG_PRI_CCA) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"17. (( %s ))ADPTV_SOML\\n\",\n\t\t\t ((comp & DBG_ADPTV_SOML) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"18. (( %s ))LNA_SAT_CHK\\n\",\n\t\t\t ((comp & DBG_LNA_SAT_CHK) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"20. (( %s ))PHY_STATUS\\n\",\n\t\t\t ((comp & DBG_PHY_STATUS) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"21. (( %s ))TMP\\n\",\n\t\t\t ((comp & DBG_TMP) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"22. (( %s ))FW_DBG_TRACE\\n\",\n\t\t\t ((comp & DBG_FW_TRACE) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"23. (( %s ))TXBF\\n\",\n\t\t\t ((comp & DBG_TXBF) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"24. (( %s ))COMMON_FLOW\\n\",\n\t\t\t ((comp & DBG_COMMON_FLOW) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"28. (( %s ))PHY_CONFIG\\n\",\n\t\t\t ((comp & ODM_PHY_CONFIG) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"29. (( %s ))INIT\\n\",\n\t\t\t ((comp & ODM_COMP_INIT) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"30. (( %s ))COMMON\\n\",\n\t\t\t ((comp & DBG_CMN) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"31. (( %s ))API\\n\",\n\t\t\t ((comp & ODM_COMP_API) ? (\"V\") : (\".\")));\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"================================\\n\");\n\n\t} else if (val[0] == 101) {\n\t\tdm->debug_components = 0;\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Disable all debug components\\n\");\n\t} else {\n\t\tif (val[1] == 1) /*@enable*/\n\t\t\tdm->debug_components |= (one << val[0]);\n\t\telse if (val[1] == 2) /*@disable*/\n\t\t\tdm->debug_components &= ~(one << val[0]);\n\t\telse\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[Warning]  1:on,  2:off\\n\");\n\n\t\tif ((BIT(val[0]) == DBG_PHY_STATUS) && val[1] == 1) {\n\t\t\tdm->phy_dbg_info.show_phy_sts_all_pkt = (u8)val[2];\n\t\t\tdm->phy_dbg_info.show_phy_sts_max_cnt = (u16)val[3];\n\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"show_all_pkt=%d, show_max_num=%d\\n\\n\",\n\t\t\t\t dm->phy_dbg_info.show_phy_sts_all_pkt,\n\t\t\t\t dm->phy_dbg_info.show_phy_sts_max_cnt);\n\n\t\t} else if ((BIT(val[0]) == DBG_CMN) && (val[1] == 1)) {\n\t\t\tdm->cmn_dbg_msg_period = (u8)val[2];\n\n\t\t\tif (dm->cmn_dbg_msg_period < PHYDM_WATCH_DOG_PERIOD)\n\t\t\t\tdm->cmn_dbg_msg_period = PHYDM_WATCH_DOG_PERIOD;\n\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"cmn_dbg_msg_period=%d\\n\",\n\t\t\t\t dm->cmn_dbg_msg_period);\n\t\t}\n\t}\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"pre-DbgComponents = 0x%llx\\n\", pre_debug_components);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"Curr-DbgComponents = 0x%llx\\n\", dm->debug_components);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"================================\\n\");\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_fw_debug_trace(void *dm_void, char input[][16], u32 *_used,\n\t\t\t  char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 val[10] = {0};\n\tu8 i, input_idx = 0;\n\tchar help[] = \"-h\";\n\tu32 pre_fw_debug_components = 0, one = 1;\n\tu32 comp = 0;\n\n\tfor (i = 0; i < 5; i++) {\n\t\tif (input[i + 1]) {\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);\n\t\t\tinput_idx++;\n\t\t}\n\t}\n\n\tif (input_idx == 0)\n\t\treturn;\n\n\tpre_fw_debug_components = dm->fw_debug_components;\n\tcomp = dm->fw_debug_components;\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"{dbg_comp} {1:en, 2:dis} {mode} {macid}\\n\");\n\t} else {\n\t\tif (val[0] == 101) {\n\t\t\tdm->fw_debug_components = 0;\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"%s\\n\", \"Clear all fw debug components\");\n\t\t} else {\n\t\t\tif (val[1] == 1) /*@enable*/\n\t\t\t\tdm->fw_debug_components |= (one << val[0]);\n\t\t\telse if (val[1] == 2) /*@disable*/\n\t\t\t\tdm->fw_debug_components &= ~(one << val[0]);\n\t\t\telse\n\t\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t\t out_len - used, \"%s\\n\",\n\t\t\t\t\t \"[Warning!!!]  1:enable,  2:disable\");\n\t\t}\n\n\t\tcomp = dm->fw_debug_components;\n\n\t\tif (comp == 0) {\n\t\t\tdm->debug_components &= ~DBG_FW_TRACE;\n\t\t\t/*@H2C to enable C2H Msg*/\n\t\t\tphydm_fw_trace_en_h2c(dm, false, comp, val[2], val[3]);\n\t\t} else {\n\t\t\tdm->debug_components |= DBG_FW_TRACE;\n\t\t\t/*@H2C to enable C2H Msg*/\n\t\t\tphydm_fw_trace_en_h2c(dm, true, comp, val[2], val[3]);\n\t\t}\n\t}\n}\n\n#if (ODM_IC_11N_SERIES_SUPPORT)\nvoid phydm_dump_bb_reg_n(void *dm_void, u32 *_used, char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 addr = 0;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\t/*@For Nseries IC we only need to dump page8 to pageF using 3 digits*/\n\tfor (addr = 0x800; addr < 0xfff; addr += 4) {\n\t\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t      \"0x%03x 0x%08x\\n\",\n\t\t\t      addr, odm_get_bb_reg(dm, addr, MASKDWORD));\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n#endif\n\n#if (ODM_IC_11AC_SERIES_SUPPORT)\nvoid phydm_dump_bb_reg_ac(void *dm_void, u32 *_used, char *output,\n\t\t\t  u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 addr = 0;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\tfor (addr = 0x800; addr < 0xfff; addr += 4) {\n\t\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t      \"0x%04x 0x%08x\\n\",\n\t\t\t      addr, odm_get_bb_reg(dm, addr, MASKDWORD));\n\t}\n\n\tif (!(dm->support_ic_type &\n\t    (ODM_RTL8822B | ODM_RTL8814A | ODM_RTL8821C)))\n\t\tgoto rpt_reg;\n\n\tif (dm->rf_type > RF_2T2R) {\n\t\tfor (addr = 0x1800; addr < 0x18ff; addr += 4)\n\t\t\tPDM_VAST_SNPF(out_len, used, output + used,\n\t\t\t\t      out_len - used, \"0x%04x 0x%08x\\n\",\n\t\t\t\t      addr,\n\t\t\t\t      odm_get_bb_reg(dm, addr, MASKDWORD));\n\t}\n\n\tif (dm->rf_type > RF_3T3R) {\n\t\tfor (addr = 0x1a00; addr < 0x1aff; addr += 4)\n\t\t\tPDM_VAST_SNPF(out_len, used, output + used,\n\t\t\t\t      out_len - used, \"0x%04x 0x%08x\\n\",\n\t\t\t\t      addr,\n\t\t\t\t      odm_get_bb_reg(dm, addr, MASKDWORD));\n\t}\n\n\tfor (addr = 0x1900; addr < 0x19ff; addr += 4)\n\t\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t      \"0x%04x 0x%08x\\n\",\n\t\t\t      addr, odm_get_bb_reg(dm, addr, MASKDWORD));\n\n\tfor (addr = 0x1c00; addr < 0x1cff; addr += 4)\n\t\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t      \"0x%04x 0x%08x\\n\",\n\t\t\t      addr, odm_get_bb_reg(dm, addr, MASKDWORD));\n\n\tfor (addr = 0x1f00; addr < 0x1fff; addr += 4)\n\t\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t      \"0x%04x 0x%08x\\n\",\n\t\t\t      addr, odm_get_bb_reg(dm, addr, MASKDWORD));\n\nrpt_reg:\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\n#endif\n\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\nvoid phydm_dump_bb_reg_jgr3(void *dm_void, u32 *_used, char *output,\n\t\t\t    u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 addr = 0;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tfor (addr = 0x800; addr < 0xdff; addr += 4)\n\t\t\tPDM_VAST_SNPF(out_len, used, output + used,\n\t\t\t\t      out_len - used, \"0x%04x 0x%08x\\n\", addr,\n\t\t\t\t      odm_get_bb_reg(dm, addr, MASKDWORD));\n\n\t\tfor (addr = 0x1800; addr < 0x1aff; addr += 4)\n\t\t\tPDM_VAST_SNPF(out_len, used, output + used,\n\t\t\t\t      out_len - used, \"0x%04x 0x%08x\\n\", addr,\n\t\t\t\t      odm_get_bb_reg(dm, addr, MASKDWORD));\n\n\t\tfor (addr = 0x1c00; addr < 0x1eff; addr += 4)\n\t\t\tPDM_VAST_SNPF(out_len, used, output + used,\n\t\t\t\t      out_len - used, \"0x%04x 0x%08x\\n\", addr,\n\t\t\t\t      odm_get_bb_reg(dm, addr, MASKDWORD));\n\n\t\tfor (addr = 0x4000; addr < 0x41ff; addr += 4)\n\t\t\tPDM_VAST_SNPF(out_len, used, output + used,\n\t\t\t\t      out_len - used, \"0x%04x 0x%08x\\n\", addr,\n\t\t\t\t      odm_get_bb_reg(dm, addr, MASKDWORD));\n\t}\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_dump_bb_reg2_jgr3(void *dm_void, u32 *_used, char *output,\n\t\t\t     u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 addr = 0;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\tif (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))\n\t\treturn;\n\n\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\tif (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {\n\t\tfor (addr = 0x5000; addr < 0x53ff; addr += 4) {\n\t\t\tPDM_VAST_SNPF(out_len, used, output + used,\n\t\t\t\t      out_len - used, \"0x%04x 0x%08x\\n\",\n\t\t\t\t      addr,\n\t\t\t\t      odm_get_bb_reg(dm, addr, MASKDWORD));\n\t\t}\n\t}\n\t#endif\n\t/* @Do not change the order of page-2C/2D*/\n\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t      \"------ BB report-register start ------\\n\");\n\tfor (addr = 0x2c00; addr < 0x2dff; addr += 4) {\n\t\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t      \"0x%04x 0x%08x\\n\",\n\t\t\t      addr, odm_get_bb_reg(dm, addr, MASKDWORD));\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_get_per_path_anapar_jgr3(void *dm_void, u8 path, u32 *_used,\n\t\t\t\t    char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 state = 0;\n\tu8 state_bp = 0;\n\tu32 control_bb = 0;\n\tu32 control_pow = 0;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 reg_idx = 0;\n\tu32 dbgport_idx = 0;\n\tu32 dbgport_val = 0;\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"path-%d:\\n\",\n\t\t path);\n\n\tif (path == RF_PATH_A) {\n\t\treg_idx = R_0x1830;\n\t\tdbgport_idx = 0x9F0;\n\t} else if (path == RF_PATH_B) {\n\t\treg_idx = R_0x4130;\n\t\tdbgport_idx = 0xBF0;\n\t} else if (path == RF_PATH_C) {\n\t\treg_idx = R_0x5230;\n\t\tdbgport_idx = 0xDF0;\n\t} else if (path == RF_PATH_D) {\n\t\treg_idx = R_0x5330;\n\t\tdbgport_idx = 0xFF0;\n\t}\n\n\tstate_bp = (u8)odm_get_bb_reg(dm, reg_idx, 0xf00000);\n\todm_set_bb_reg(dm, reg_idx, 0x38000000, 0x5); /* @read en*/\n\n\tfor (state = 0; state <= 0xf; state++) {\n\t\todm_set_bb_reg(dm, reg_idx, 0xF00000, state);\n\t\tif (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbgport_idx)) {\n\t\t\tdbgport_val = phydm_get_bb_dbg_port_val(dm);\n\t\t\tphydm_release_bb_dbg_port(dm);\n\t\t} else {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"state:0x%x = read dbg_port error!\\n\", state);\n\t\t}\n\t\tcontrol_bb = (dbgport_val & 0xFFFF0) >> 4;\n\t\tcontrol_pow = dbgport_val & 0xF;\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"state:0x%x = control_bb:0x%x pow_bb:0x%x\\n\",\n\t\t\t state, control_bb, control_pow);\n\t}\n\todm_set_bb_reg(dm, reg_idx, 0xf00000, state_bp);\n\todm_set_bb_reg(dm, reg_idx, 0x38000000, 0x6); /* @write en*/\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\n#endif\n\nvoid phydm_dump_bb_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t      \"BB==========\\n\");\n\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t      \"------ BB control register start ------\\n\");\n\n\tswitch (dm->ic_ip_series) {\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\tcase PHYDM_IC_JGR3:\n\t\tphydm_dump_bb_reg_jgr3(dm, &used, output, &out_len);\n\t\tbreak;\n\t#endif\n\n\t#if (ODM_IC_11AC_SERIES_SUPPORT == 1)\n\tcase PHYDM_IC_AC:\n\t\tphydm_dump_bb_reg_ac(dm, &used, output, &out_len);\n\t\tbreak;\n\t#endif\n\n\t#if (ODM_IC_11N_SERIES_SUPPORT == 1)\n\tcase PHYDM_IC_N:\n\t\tphydm_dump_bb_reg_n(dm, &used, output, &out_len);\n\t\tbreak;\n\t#endif\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_dump_rf_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 addr = 0;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 reg = 0;\n\n\t/* @dump RF register */\n\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t      \"RF-A==========\\n\");\n\n\tfor (addr = 0; addr <= 0xFF; addr++) {\n\t\treg = odm_get_rf_reg(dm, RF_PATH_A, addr, RFREG_MASK);\n\t\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t      \"0x%02x 0x%05x\\n\", addr, reg);\n\t\t}\n\n#ifdef PHYDM_COMPILE_ABOVE_2SS\n\tif (dm->rf_type > RF_1T1R) {\n\t\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t      \"RF-B==========\\n\");\n\n\t\tfor (addr = 0; addr <= 0xFF; addr++) {\n\t\t\treg = odm_get_rf_reg(dm, RF_PATH_B, addr, RFREG_MASK);\n\t\t\tPDM_VAST_SNPF(out_len, used, output + used,\n\t\t\t\t      out_len - used, \"0x%02x 0x%05x\\n\",\n\t\t\t\t      addr, reg);\n\t\t}\n\t}\n#endif\n\n#ifdef PHYDM_COMPILE_ABOVE_3SS\n\tif (dm->rf_type > RF_2T2R) {\n\t\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t      \"RF-C==========\\n\");\n\n\t\tfor (addr = 0; addr <= 0xFF; addr++) {\n\t\t\treg = odm_get_rf_reg(dm, RF_PATH_C, addr, RFREG_MASK);\n\t\t\tPDM_VAST_SNPF(out_len, used, output + used,\n\t\t\t\t      out_len - used, \"0x%02x 0x%05x\\n\",\n\t\t\t\t      addr, reg);\n\t\t}\n\t}\n#endif\n\n#ifdef PHYDM_COMPILE_ABOVE_4SS\n\tif (dm->rf_type > RF_3T3R) {\n\t\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t      \"RF-D==========\\n\");\n\n\t\tfor (addr = 0; addr <= 0xFF; addr++) {\n\t\t\treg = odm_get_rf_reg(dm, RF_PATH_D, addr, RFREG_MASK);\n\t\t\tPDM_VAST_SNPF(out_len, used, output + used,\n\t\t\t\t      out_len - used, \"0x%02x 0x%05x\\n\",\n\t\t\t\t      addr, reg);\n\t\t}\n\t}\n#endif\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_dump_mac_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 addr = 0;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\t/* @dump MAC register */\n\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t      \"MAC==========\\n\");\n\n\tfor (addr = 0; addr < 0x7ff; addr += 4)\n\t\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t      \"0x%04x 0x%08x\\n\",\n\t\t\t      addr, odm_get_bb_reg(dm, addr, MASKDWORD));\n\n\tfor (addr = 0x1000; addr < 0x17ff; addr += 4)\n\t\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t      \"0x%04x 0x%08x\\n\",\n\t\t\t      addr, odm_get_bb_reg(dm, addr, MASKDWORD));\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_dump_reg(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t    u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tchar help[] = \"-h\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 addr = 0;\n\n\tif (input[1])\n\t\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"dumpreg {0:all, 1:BB, 2:RF, 3:MAC 4:BB2 for jgr3}\\n\");\n\t\telse\n\t\t#endif\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"dumpreg {0:all, 1:BB, 2:RF, 3:MAC}\\n\");\n\t} else if (var1[0] == 0) {\n\t\tphydm_dump_mac_reg(dm, &used, output, &out_len);\n\t\tphydm_dump_bb_reg(dm, &used, output, &out_len);\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\tif (dm->ic_ip_series == PHYDM_IC_JGR3)\n\t\t\tphydm_dump_bb_reg2_jgr3(dm, &used, output, &out_len);\n\t\t#endif\n\n\t\tphydm_dump_rf_reg(dm, &used, output, &out_len);\n\t} else if (var1[0] == 1) {\n\t\tphydm_dump_bb_reg(dm, &used, output, &out_len);\n\t} else if (var1[0] == 2) {\n\t\tphydm_dump_rf_reg(dm, &used, output, &out_len);\n\t} else if (var1[0] == 3) {\n\t\tphydm_dump_mac_reg(dm, &used, output, &out_len);\n\t} else if (var1[0] == 4) {\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\tif (dm->ic_ip_series == PHYDM_IC_JGR3)\n\t\t\tphydm_dump_bb_reg2_jgr3(dm, &used, output, &out_len);\n\t\t#endif\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_enable_big_jump(void *dm_void, char input[][16], u32 *_used,\n\t\t\t   char *output, u32 *_out_len)\n{\n#if (RTL8822B_SUPPORT)\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tu32 dm_value[10] = {0};\n\tu8 i, input_idx = 0;\n\tu32 val;\n\n\tif (!(dm->support_ic_type & ODM_RTL8822B))\n\t\treturn;\n\n\tfor (i = 0; i < 5; i++) {\n\t\tif (input[i + 1]) {\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);\n\t\t\tinput_idx++;\n\t\t}\n\t}\n\n\tif (input_idx == 0)\n\t\treturn;\n\n\tif (dm_value[0] == 0) {\n\t\tdm->dm_dig_table.enable_adjust_big_jump = false;\n\n\t\tval = (dig_t->big_jump_step3 << 5) |\n\t\t      (dig_t->big_jump_step2 << 3) |\n\t\t      dig_t->big_jump_step1;\n\n\t\todm_set_bb_reg(dm, R_0x8c8, 0xfe, val);\n\t} else {\n\t\tdm->dm_dig_table.enable_adjust_big_jump = true;\n\t}\n#endif\n}\n\nvoid phydm_show_rx_rate(void *dm_void, char input[][16], u32 *_used,\n\t\t\tchar *output, u32 *_out_len)\n{\n#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8814B_SUPPORT ||\\\n\tRTL8195B_SUPPORT || RTL8822C_SUPPORT)\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 var1[10] = {0};\n\tchar help[] = \"-h\";\n\tu8 i, input_idx = 0;\n\n\tfor (i = 0; i < 5; i++) {\n\t\tif (input[i + 1]) {\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);\n\t\t\tinput_idx++;\n\t\t}\n\t}\n\n\tif (input_idx == 0)\n\t\treturn;\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{1: show Rx rate, 0:reset counter}\\n\");\n\t\t*_used = used;\n\t\t*_out_len = out_len;\n\t\treturn;\n\n\t} else if (var1[0] == 0) {\n\t\tphydm_reset_rx_rate_distribution(dm);\n\t\t*_used = used;\n\t\t*_out_len = out_len;\n\t\treturn;\n\t}\n\n\t/* @==Show SU Rate====================================================*/\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"=====Rx SU rate Statistics=====\\n\");\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"[SU][1SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\\n\",\n\t\t dbg->num_qry_vht_pkt[0], dbg->num_qry_vht_pkt[1],\n\t\t dbg->num_qry_vht_pkt[2], dbg->num_qry_vht_pkt[3],\n\t\t dbg->num_qry_vht_pkt[4], dbg->num_qry_vht_pkt[5],\n\t\t dbg->num_qry_vht_pkt[6], dbg->num_qry_vht_pkt[7],\n\t\t dbg->num_qry_vht_pkt[8], dbg->num_qry_vht_pkt[9]);\n\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tif (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[SU][2SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\\n\",\n\t\t\t dbg->num_qry_vht_pkt[10], dbg->num_qry_vht_pkt[11],\n\t\t\t dbg->num_qry_vht_pkt[12], dbg->num_qry_vht_pkt[13],\n\t\t\t dbg->num_qry_vht_pkt[14], dbg->num_qry_vht_pkt[15],\n\t\t\t dbg->num_qry_vht_pkt[16], dbg->num_qry_vht_pkt[17],\n\t\t\t dbg->num_qry_vht_pkt[18], dbg->num_qry_vht_pkt[19]);\n\t}\n\t#endif\n\t/* @==Show MU Rate====================================================*/\n#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) || (defined(PHYSTS_3RD_TYPE_SUPPORT))\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"=====Rx MU rate Statistics=====\\n\");\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"[MU][1SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\\n\",\n\t\t dbg->num_mu_vht_pkt[0], dbg->num_mu_vht_pkt[1],\n\t\t dbg->num_mu_vht_pkt[2], dbg->num_mu_vht_pkt[3],\n\t\t dbg->num_mu_vht_pkt[4], dbg->num_mu_vht_pkt[5],\n\t\t dbg->num_mu_vht_pkt[6], dbg->num_mu_vht_pkt[7],\n\t\t dbg->num_mu_vht_pkt[8], dbg->num_mu_vht_pkt[9]);\n\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tif (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[MU][2SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\\n\",\n\t\t\t dbg->num_mu_vht_pkt[10], dbg->num_mu_vht_pkt[11],\n\t\t\t dbg->num_mu_vht_pkt[12], dbg->num_mu_vht_pkt[13],\n\t\t\t dbg->num_mu_vht_pkt[14], dbg->num_mu_vht_pkt[15],\n\t\t\t dbg->num_mu_vht_pkt[16], dbg->num_mu_vht_pkt[17],\n\t\t\t dbg->num_mu_vht_pkt[18], dbg->num_mu_vht_pkt[19]);\n\t}\n\t#endif\n#endif\n\t*_used = used;\n\t*_out_len = out_len;\n#endif\n}\n\nvoid phydm_per_tone_evm(void *dm_void, char input[][16], u32 *_used,\n\t\t\tchar *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i, j;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 var1[4] = {0};\n\tu32 val, tone_num, round;\n\ts8 rxevm_0, rxevm_1;\n\ts32 avg_num, evm_tone_0[256] = {0}, evm_tone_1[256] = {0};\n\ts32 rxevm_sum_0, rxevm_sum_1;\n\n\tif (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\tpr_debug(\"n series not support yet !\\n\");\n\t\treturn;\n\t}\n\n\tfor (i = 0; i < 4; i++) {\n\t\tif (input[i + 1])\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);\n\t}\n\n\tavg_num = var1[0];\n\tround = var1[1];\n\n\tif (!dm->is_linked) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"No Link !!\\n\");\n\n\t\t*_used = used;\n\t\t*_out_len = out_len;\n\n\t\treturn;\n\t}\n\n\tpr_debug(\"ID=((%d)), BW=((%d)), fc=((CH-%d))\\n\", dm->curr_station_id,\n\t\t 20 << *dm->band_width, *dm->channel);\n\tpr_debug(\"avg_num =((%d)), round =((%d))\\n\", avg_num, round);\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\twatchdog_stop(dm->priv);\n#endif\n\tfor (j = 0; j < round; j++) {\n\t\tpr_debug(\"\\nround((%d))\\n\", (j + 1));\n\t\tif (*dm->band_width == CHANNEL_WIDTH_20) {\n\t\t\tfor (tone_num = 228; tone_num <= 255; tone_num++) {\n\t\t\t\todm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);\n\t\t\t\trxevm_sum_0 = 0;\n\t\t\t\trxevm_sum_1 = 0;\n\t\t\t\tfor (i = 0; i < avg_num; i++) {\n\t\t\t\t\tval = odm_read_4byte(dm, R_0xf8c);\n\n\t\t\t\t\trxevm_0 = (s8)((val & MASKBYTE2) >> 16);\n\t\t\t\t\trxevm_0 = (rxevm_0 / 2);\n\t\t\t\t\tif (rxevm_0 < -63)\n\t\t\t\t\t\trxevm_0 = 0;\n\n\t\t\t\t\trxevm_1 = (s8)((val & MASKBYTE3) >> 24);\n\t\t\t\t\trxevm_1 = (rxevm_1 / 2);\n\t\t\t\t\tif (rxevm_1 < -63)\n\t\t\t\t\t\trxevm_1 = 0;\n\t\t\t\t\trxevm_sum_0 += rxevm_0;\n\t\t\t\t\trxevm_sum_1 += rxevm_1;\n\t\t\t\t\tODM_delay_ms(1);\n\t\t\t\t}\n\t\t\t\tevm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);\n\t\t\t\tevm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);\n\t\t\t\tpr_debug(\"Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\\n\",\n\t\t\t\t\t (256 - tone_num), evm_tone_0[tone_num],\n\t\t\t\t\t evm_tone_1[tone_num]);\n\t\t\t}\n\n\t\t\tfor (tone_num = 1; tone_num <= 28; tone_num++) {\n\t\t\t\todm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);\n\t\t\t\trxevm_sum_0 = 0;\n\t\t\t\trxevm_sum_1 = 0;\n\t\t\t\tfor (i = 0; i < avg_num; i++) {\n\t\t\t\t\tval = odm_read_4byte(dm, R_0xf8c);\n\n\t\t\t\t\trxevm_0 = (s8)((val & MASKBYTE2) >> 16);\n\t\t\t\t\trxevm_0 = (rxevm_0 / 2);\n\t\t\t\t\tif (rxevm_0 < -63)\n\t\t\t\t\t\trxevm_0 = 0;\n\n\t\t\t\t\trxevm_1 = (s8)((val & MASKBYTE3) >> 24);\n\t\t\t\t\trxevm_1 = (rxevm_1 / 2);\n\t\t\t\t\tif (rxevm_1 < -63)\n\t\t\t\t\t\trxevm_1 = 0;\n\t\t\t\t\trxevm_sum_0 += rxevm_0;\n\t\t\t\t\trxevm_sum_1 += rxevm_1;\n\t\t\t\t\tODM_delay_ms(1);\n\t\t\t\t}\n\t\t\t\tevm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);\n\t\t\t\tevm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);\n\t\t\t\tpr_debug(\"Tone(%-3d) RXEVM(1ss/2ss)=%d, %d\\n\",\n\t\t\t\t\t tone_num, evm_tone_0[tone_num],\n\t\t\t\t\t evm_tone_1[tone_num]);\n\t\t\t}\n\t\t} else if (*dm->band_width == CHANNEL_WIDTH_40) {\n\t\t\tfor (tone_num = 198; tone_num <= 254; tone_num++) {\n\t\t\t\todm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);\n\t\t\t\trxevm_sum_0 = 0;\n\t\t\t\trxevm_sum_1 = 0;\n\t\t\t\tfor (i = 0; i < avg_num; i++) {\n\t\t\t\t\tval = odm_read_4byte(dm, R_0xf8c);\n\n\t\t\t\t\trxevm_0 = (s8)((val & MASKBYTE2) >> 16);\n\t\t\t\t\trxevm_0 = (rxevm_0 / 2);\n\t\t\t\t\tif (rxevm_0 < -63)\n\t\t\t\t\t\trxevm_0 = 0;\n\n\t\t\t\t\trxevm_1 = (s8)((val & MASKBYTE3) >> 24);\n\t\t\t\t\trxevm_1 = (rxevm_1 / 2);\n\t\t\t\t\tif (rxevm_1 < -63)\n\t\t\t\t\t\trxevm_1 = 0;\n\n\t\t\t\t\trxevm_sum_0 += rxevm_0;\n\t\t\t\t\trxevm_sum_1 += rxevm_1;\n\t\t\t\t\tODM_delay_ms(1);\n\t\t\t\t}\n\t\t\t\tevm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);\n\t\t\t\tevm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);\n\t\t\t\tpr_debug(\"Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\\n\",\n\t\t\t\t\t (256 - tone_num), evm_tone_0[tone_num],\n\t\t\t\t\t evm_tone_1[tone_num]);\n\t\t\t}\n\n\t\t\tfor (tone_num = 2; tone_num <= 58; tone_num++) {\n\t\t\t\todm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);\n\t\t\t\trxevm_sum_0 = 0;\n\t\t\t\trxevm_sum_1 = 0;\n\t\t\t\tfor (i = 0; i < avg_num; i++) {\n\t\t\t\t\tval = odm_read_4byte(dm, R_0xf8c);\n\n\t\t\t\t\trxevm_0 = (s8)((val & MASKBYTE2) >> 16);\n\t\t\t\t\trxevm_0 = (rxevm_0 / 2);\n\t\t\t\t\tif (rxevm_0 < -63)\n\t\t\t\t\t\trxevm_0 = 0;\n\n\t\t\t\t\trxevm_1 = (s8)((val & MASKBYTE3) >> 24);\n\t\t\t\t\trxevm_1 = (rxevm_1 / 2);\n\t\t\t\t\tif (rxevm_1 < -63)\n\t\t\t\t\t\trxevm_1 = 0;\n\t\t\t\t\trxevm_sum_0 += rxevm_0;\n\t\t\t\t\trxevm_sum_1 += rxevm_1;\n\t\t\t\t\tODM_delay_ms(1);\n\t\t\t\t}\n\t\t\t\tevm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);\n\t\t\t\tevm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);\n\t\t\t\tpr_debug(\"Tone(%-3d) RXEVM(1ss/2ss)=%d, %d\\n\",\n\t\t\t\t\t tone_num, evm_tone_0[tone_num],\n\t\t\t\t\t evm_tone_1[tone_num]);\n\t\t\t}\n\t\t} else if (*dm->band_width == CHANNEL_WIDTH_80) {\n\t\t\tfor (tone_num = 134; tone_num <= 254; tone_num++) {\n\t\t\t\todm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);\n\t\t\t\trxevm_sum_0 = 0;\n\t\t\t\trxevm_sum_1 = 0;\n\t\t\t\tfor (i = 0; i < avg_num; i++) {\n\t\t\t\t\tval = odm_read_4byte(dm, R_0xf8c);\n\n\t\t\t\t\trxevm_0 = (s8)((val & MASKBYTE2) >> 16);\n\t\t\t\t\trxevm_0 = (rxevm_0 / 2);\n\t\t\t\t\tif (rxevm_0 < -63)\n\t\t\t\t\t\trxevm_0 = 0;\n\n\t\t\t\t\trxevm_1 = (s8)((val & MASKBYTE3) >> 24);\n\t\t\t\t\trxevm_1 = (rxevm_1 / 2);\n\t\t\t\t\tif (rxevm_1 < -63)\n\t\t\t\t\t\trxevm_1 = 0;\n\t\t\t\t\trxevm_sum_0 += rxevm_0;\n\t\t\t\t\trxevm_sum_1 += rxevm_1;\n\t\t\t\t\tODM_delay_ms(1);\n\t\t\t\t}\n\t\t\t\tevm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);\n\t\t\t\tevm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);\n\t\t\t\tpr_debug(\"Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\\n\",\n\t\t\t\t\t (256 - tone_num), evm_tone_0[tone_num],\n\t\t\t\t\t evm_tone_1[tone_num]);\n\t\t\t}\n\n\t\t\tfor (tone_num = 2; tone_num <= 122; tone_num++) {\n\t\t\t\todm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);\n\t\t\t\trxevm_sum_0 = 0;\n\t\t\t\trxevm_sum_1 = 0;\n\t\t\t\tfor (i = 0; i < avg_num; i++) {\n\t\t\t\t\tval = odm_read_4byte(dm, R_0xf8c);\n\n\t\t\t\t\trxevm_0 = (s8)((val & MASKBYTE2) >> 16);\n\t\t\t\t\trxevm_0 = (rxevm_0 / 2);\n\t\t\t\t\tif (rxevm_0 < -63)\n\t\t\t\t\t\trxevm_0 = 0;\n\n\t\t\t\t\trxevm_1 = (s8)((val & MASKBYTE3) >> 24);\n\t\t\t\t\trxevm_1 = (rxevm_1 / 2);\n\t\t\t\t\tif (rxevm_1 < -63)\n\t\t\t\t\t\trxevm_1 = 0;\n\t\t\t\t\trxevm_sum_0 += rxevm_0;\n\t\t\t\t\trxevm_sum_1 += rxevm_1;\n\t\t\t\t\tODM_delay_ms(1);\n\t\t\t\t}\n\t\t\t\tevm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);\n\t\t\t\tevm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);\n\t\t\t\tpr_debug(\"Tone(%-3d) RXEVM (1ss/2ss)=%d, %d\\n\",\n\t\t\t\t\t tone_num, evm_tone_0[tone_num],\n\t\t\t\t\t evm_tone_1[tone_num]);\n\t\t\t}\n\t\t}\n\t}\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_bw_ch_adjust(void *dm_void, char input[][16],\n\t\t\tu32 *_used, char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tchar help[] = \"-h\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu8 i;\n\tboolean is_enable_dbg_mode;\n\tu8 central_ch, primary_ch_idx;\n\tenum channel_width bw;\n\n#ifdef PHYDM_COMMON_API_SUPPORT\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{en} {CH} {pr_ch_idx 1/2/3/4/9/10} {0:20M,1:40M,2:80M}\\n\");\n\t\tgoto out;\n\t}\n\n\tif (!(dm->support_ic_type & CMN_API_SUPPORT_IC)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Not support this API\\n\");\n\t\tgoto out;\n\t}\n\n\tfor (i = 0; i < 4; i++) {\n\t\tif (input[i + 1])\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);\n\t}\n\n\tis_enable_dbg_mode = (boolean)var1[0];\n\tcentral_ch = (u8)var1[1];\n\tprimary_ch_idx = (u8)var1[2];\n\tbw = (enum channel_width)var1[3];\n\n\tif (is_enable_dbg_mode) {\n\t\tdm->is_disable_phy_api = false;\n\t\tphydm_api_switch_bw_channel(dm, central_ch, primary_ch_idx, bw);\n\t\tdm->is_disable_phy_api = true;\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"central_ch = %d, primary_ch_idx = %d, bw = %d\\n\",\n\t\t\t central_ch, primary_ch_idx, bw);\n\t}\nout:\n#endif\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_ext_rf_element_ctrl(void *dm_void, char input[][16], u32 *_used,\n\t\t\t       char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 val[10] = {0};\n\tu8 i = 0, input_idx = 0;\n\n\tfor (i = 0; i < 5; i++) {\n\t\tif (input[i + 1]) {\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);\n\t\t\tinput_idx++;\n\t\t}\n\t}\n\n\tif (input_idx == 0)\n\t\treturn;\n\n\tif (val[0] == 1) /*@ext switch*/ {\n\t\tphydm_set_ext_switch(dm, val[1]);\n\t}\n}\n\nvoid phydm_print_dbgport(void *dm_void, char input[][16], u32 *_used,\n\t\t\t char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tchar help[] = \"-h\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 dbg_port_value = 0;\n\tu8 val[32];\n\tu8 tmp = 0;\n\tu8 i;\n\n\tif (strcmp(input[1], help) == 0) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{dbg_port_idx}\\n\");\n\t\tgoto out;\n\t}\n\n\tPHYDM_SSCANF(input[1], DCMD_HEX, &var1[0]);\n\n\tdm->debug_components |= ODM_COMP_API;\n\tif (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, var1[0])) {\n\t\tdbg_port_value = phydm_get_bb_dbg_port_val(dm);\n\t\tphydm_release_bb_dbg_port(dm);\n\n\t\tfor (i = 0; i < 32; i++)\n\t\t\tval[i] = (u8)((dbg_port_value & BIT(i)) >> i);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Dbg Port[0x%x] = ((0x%x))\\n\", var1[0],\n\t\t\t dbg_port_value);\n\n\t\tfor (i = 4; i != 0; i--) {\n\t\t\ttmp = 8 * (i - 1);\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"val[%d:%d] = 8b'%d %d %d %d %d %d %d %d\\n\",\n\t\t\t\t tmp + 7, tmp, val[tmp + 7], val[tmp + 6],\n\t\t\t\t val[tmp + 5], val[tmp + 4], val[tmp + 3],\n\t\t\t\t val[tmp + 2], val[tmp + 1], val[tmp + 0]);\n\t\t}\n\t}\n\tdm->debug_components &= (~ODM_COMP_API);\nout:\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_get_anapar_table(void *dm_void, u32 *_used, char *output,\n\t\t\t    u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tenum rf_path i = RF_PATH_A;\n\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\tif (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))\n\t\treturn;\n\n\tPDM_VAST_SNPF(out_len, used, output + used, out_len - used,\n\t\t      \"------ Analog parameters start ------\\n\");\n\n\tfor (i = RF_PATH_A; i < (enum rf_path)dm->num_rf_path; i++)\n\t\tphydm_get_per_path_anapar_jgr3(dm, i, &used, output, &out_len);\n#endif\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_dd_dbg_dump(void *dm_void, char input[][16], u32 *_used,\n\t\t       char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tchar help[] = \"-h\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"dump: {1}\\n\");\n\t\treturn;\n\t} else if (var1[0] == 1) {\n\t\t/*[Reg]*/\n\t\tphydm_dump_mac_reg(dm, &used, output, &out_len);\n\t\tphydm_dump_bb_reg(dm, &used, output, &out_len);\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\tif (dm->ic_ip_series == PHYDM_IC_JGR3)\n\t\t\tphydm_dump_bb_reg2_jgr3(dm, &used, output, &out_len);\n\t\t#endif\n\n\t\tphydm_dump_rf_reg(dm, &used, output, &out_len);\n\t\t/*[Dbg Port]*/\n\t\t#ifdef PHYDM_AUTO_DEGBUG\n\t\tphydm_dbg_port_dump(dm, &used, output, &out_len);\n\t\t#endif\n\t\t/*[Analog Parameters]*/\n\t\tphydm_get_anapar_table(dm, &used, output, &out_len);\n\t}\n}\n\nvoid phydm_nss_hitogram_mp(void *dm_void, enum PDM_RATE_TYPE rate_type,\n\t\t\t   u32 *_used, char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;\n\tstruct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tchar buf[PHYDM_SNPRINT_SIZE] = {0};\n\tu16 buf_size = PHYDM_SNPRINT_SIZE;\n\tu16 h_size = PHY_HIST_SIZE;\n\tu16 *evm_hist = &dbg_s->evm_1ss_hist[0];\n\tu16 *snr_hist = &dbg_s->snr_1ss_hist[0];\n\tu8 i = 0;\n\tu8 ss = phydm_rate_type_2_num_ss(dm, rate_type);\n\n\tif (rate_type == PDM_OFDM) {\n\t\tphydm_print_hist_2_buf(dm, dbg_s->evm_ofdm_hist, PHY_HIST_SIZE,\n\t\t\t\t       buf, buf_size);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"%-14s=%s\\n\", \"[OFDM][EVM]\", buf);\n\n\t\tphydm_print_hist_2_buf(dm, dbg_s->snr_ofdm_hist, PHY_HIST_SIZE,\n\t\t\t\t       buf, buf_size);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"%-14s=%s\\n\", \"[OFDM][SNR]\", buf);\n\n\t\t*_used = used;\n\t\t*_out_len = out_len;\n\t\treturn;\n\t}\n\n\tfor (i = 0; i < ss; i++) {\n\t\tif (rate_type == PDM_1SS) {\n\t\t\tevm_hist = &dbg_s->evm_1ss_hist[0];\n\t\t\tsnr_hist = &dbg_s->snr_1ss_hist[0];\n\t\t} else if (rate_type == PDM_2SS) {\n\t\t\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\t\t\tevm_hist = &dbg_s->evm_2ss_hist[i][0];\n\t\t\tsnr_hist = &dbg_s->snr_2ss_hist[i][0];\n\t\t\t#endif\n\t\t} else if (rate_type == PDM_3SS) {\n\t\t\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\t\t\tevm_hist = &dbg_s->evm_3ss_hist[i][0];\n\t\t\tsnr_hist = &dbg_s->snr_3ss_hist[i][0];\n\t\t\t#endif\n\t\t} else if (rate_type == PDM_4SS) {\n\t\t\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\t\t\tevm_hist = &dbg_s->evm_4ss_hist[i][0];\n\t\t\tsnr_hist = &dbg_s->snr_4ss_hist[i][0];\n\t\t\t#endif\n\t\t}\n\n\t\tphydm_print_hist_2_buf(dm, evm_hist, h_size, buf, buf_size);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[%d-SS][EVM][%d]=%s\\n\", ss, i, buf);\n\t\tphydm_print_hist_2_buf(dm, snr_hist, h_size, buf, buf_size);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[%d-SS][SNR][%d]=%s\\n\",  ss, i, buf);\n\t}\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_mp_dbg(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t  u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;\n\tstruct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;\n\tstruct phydm_phystatus_avg *dbg_avg = &dbg_i->phystatus_statistic_avg;\n\tchar *rate_type = NULL;\n\tu8 tmp_rssi_avg[4];\n\tu8 tmp_snr_avg[4];\n\tu8 tmp_evm_avg[4];\n\tu32 tmp_cnt = 0;\n\tchar buf[PHYDM_SNPRINT_SIZE] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 var1[10] = {0};\n\tu16 buf_size = PHYDM_SNPRINT_SIZE;\n\tu16 th_size = PHY_HIST_SIZE - 1;\n\tu8 i = 0;\n\n\tif (!(*dm->mp_mode))\n\t\treturn;\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"BW=((%d)), fc=((CH-%d))\\n\",\n\t\t 20 << *dm->band_width, *dm->channel);\n\n\t/*@===[PHY Histogram]================================================*/\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"[PHY Histogram] ==============>\\n\");\n\t/*@===[Threshold]===*/\n\tphydm_print_hist_2_buf(dm, dbg_i->evm_hist_th, th_size, buf, buf_size);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"%-16s=%s\\n\", \"[EVM_TH]\", buf);\n\tphydm_print_hist_2_buf(dm, dbg_i->snr_hist_th, th_size, buf, buf_size);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"%-16s=%s\\n\", \"[SNR_TH]\", buf);\n\t/*@===[OFDM]===*/\n\tphydm_nss_hitogram_mp(dm, PDM_OFDM, &used, output, &out_len);\n\t/*@===[1-SS]===*/\n\tphydm_nss_hitogram_mp(dm, PDM_1SS, &used, output, &out_len);\n\t/*@===[2-SS]===*/\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tif (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)\n\t\tphydm_nss_hitogram_mp(dm, PDM_2SS, &used, output, &out_len);\n\t#endif\n\t/*@===[3-SS]===*/\n\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\tif (dm->support_ic_type & PHYDM_IC_ABOVE_3SS)\n\t\tphydm_nss_hitogram_mp(dm, PDM_3SS, &used, output, &out_len);\n\t#endif\n\t/*@===[4-SS]===*/\n\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\tif (dm->support_ic_type & PHYDM_IC_ABOVE_4SS)\n\t\tphydm_nss_hitogram_mp(dm, PDM_4SS, &used, output, &out_len);\n\t#endif\n\t/*@===[PHY Avg]======================================================*/\n\tphydm_get_avg_phystatus_val(dm);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"[PHY Avg] ==============>\\n\");\n\n\tphydm_get_avg_phystatus_val(dm);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"* %-8s Cnt=((%.3d)) RSSI:{%.2d}\\n\",\n\t\t \"[Beacon]\", dbg_s->rssi_beacon_cnt, dbg_avg->rssi_beacon_avg);\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"* %-8s Cnt=((%.3d)) RSSI:{%.2d}\\n\",\n\t\t \"[CCK]\", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg);\n\n\tfor (i = 0; i <= 4; i++) {\n\t\tif (i > dm->num_rf_path)\n\t\t\tbreak;\n\n\t\todm_memory_set(dm, tmp_rssi_avg, 0, 4);\n\t\todm_memory_set(dm, tmp_snr_avg, 0, 4);\n\t\todm_memory_set(dm, tmp_evm_avg, 0, 4);\n\n\t\tswitch (i) {\n\t\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\t\tcase 4:\n\t\t\trate_type = \"[4-SS]\";\n\t\t\ttmp_cnt = dbg_s->rssi_4ss_cnt;\n\t\t\todm_move_memory(dm, tmp_rssi_avg,\n\t\t\t\t\tdbg_avg->rssi_4ss_avg, dm->num_rf_path);\n\t\t\todm_move_memory(dm, tmp_snr_avg,\n\t\t\t\t\tdbg_avg->snr_4ss_avg, dm->num_rf_path);\n\t\t\todm_move_memory(dm, tmp_evm_avg, dbg_avg->evm_4ss_avg,\n\t\t\t\t\t4);\n\t\t\tbreak;\n\t\t#endif\n\t\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\t\tcase 3:\n\t\t\trate_type = \"[3-SS]\";\n\t\t\ttmp_cnt = dbg_s->rssi_3ss_cnt;\n\t\t\todm_move_memory(dm, tmp_rssi_avg,\n\t\t\t\t\tdbg_avg->rssi_3ss_avg, dm->num_rf_path);\n\t\t\todm_move_memory(dm, tmp_snr_avg,\n\t\t\t\t\tdbg_avg->snr_3ss_avg, dm->num_rf_path);\n\t\t\todm_move_memory(dm, tmp_evm_avg,\n\t\t\t\t\tdbg_avg->evm_3ss_avg, 3);\n\t\t\tbreak;\n\t\t#endif\n\t\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\t\tcase 2:\n\t\t\trate_type = \"[2-SS]\";\n\t\t\ttmp_cnt = dbg_s->rssi_2ss_cnt;\n\t\t\todm_move_memory(dm, tmp_rssi_avg,\n\t\t\t\t\tdbg_avg->rssi_2ss_avg, dm->num_rf_path);\n\t\t\todm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_2ss_avg,\n\t\t\t\t\tdm->num_rf_path);\n\t\t\todm_move_memory(dm, tmp_evm_avg,\n\t\t\t\t\tdbg_avg->evm_2ss_avg, 2);\n\t\t\tbreak;\n\t\t#endif\n\t\tcase 1:\n\t\t\trate_type = \"[1-SS]\";\n\t\t\ttmp_cnt = dbg_s->rssi_1ss_cnt;\n\t\t\todm_move_memory(dm, tmp_rssi_avg,\n\t\t\t\t\tdbg_avg->rssi_1ss_avg, dm->num_rf_path);\n\t\t\todm_move_memory(dm, tmp_snr_avg,\n\t\t\t\t\tdbg_avg->snr_1ss_avg, dm->num_rf_path);\n\t\t\todm_move_memory(dm, tmp_evm_avg,\n\t\t\t\t\t&dbg_avg->evm_1ss_avg, 1);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\trate_type = \"[L-OFDM]\";\n\t\t\ttmp_cnt = dbg_s->rssi_ofdm_cnt;\n\t\t\todm_move_memory(dm, tmp_rssi_avg,\n\t\t\t\t\tdbg_avg->rssi_ofdm_avg,\n\t\t\t\t\tdm->num_rf_path);\n\t\t\todm_move_memory(dm, tmp_snr_avg,\n\t\t\t\t\tdbg_avg->snr_ofdm_avg, dm->num_rf_path);\n\t\t\todm_move_memory(dm, tmp_evm_avg,\n\t\t\t\t\t&dbg_avg->evm_ofdm_avg, 1);\n\t\t\tbreak;\n\t\t}\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t   \"* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d} SNR:{%.2d, %.2d, %.2d, %.2d} EVM:{-%.2d, -%.2d, -%.2d, -%.2d}\\n\",\n\t\t\t    rate_type, tmp_cnt,\n\t\t\t    tmp_rssi_avg[0], tmp_rssi_avg[1],\n\t\t\t    tmp_rssi_avg[2], tmp_rssi_avg[3],\n\t\t\t    tmp_snr_avg[0], tmp_snr_avg[1],\n\t\t\t    tmp_snr_avg[2], tmp_snr_avg[3],\n\t\t\t    tmp_evm_avg[0], tmp_evm_avg[1],\n\t\t\t    tmp_evm_avg[2], tmp_evm_avg[3]);\n\t}\n\n\tphydm_reset_phystatus_statistic(dm);\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"rxsc_idx {Legacy, 20, 40, 80} = {%d, %d, %d, %d}\\n\",\n\t\t dm->rxsc_l, dm->rxsc_20, dm->rxsc_40, dm->rxsc_80);\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\n#if RTL8814B_SUPPORT\nvoid phydm_spur_detect_dbg(void *dm_void, char input[][16], u32 *_used,\n\t\t\t   char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tchar help[] = \"-h\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 i;\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{0: Auto spur detect(NBI+CSI), 1:NBI only,\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"2: CSI only, 3: Disable}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{NBI path(0~3) | CSI wgt (0~7)}\\n\");\n\t} else {\n\t\tfor (i = 0; i < 10; i++) {\n\t\t\tif (input[i + 1])\n\t\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);\n\t\t}\n\n\t\tif (var1[0] == 1)\n\t\t\tdm->dsde_sel = DET_NBI;\n\t\telse if (var1[0] == 2)\n\t\t\tdm->dsde_sel = DET_CSI;\n\t\telse if (var1[0] == 3)\n\t\t\tdm->dsde_sel = DET_DISABLE;\n\t\telse\n\t\t\tdm->dsde_sel = DET_AUTO;\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"spur detect mode = %d\\n\", dm->dsde_sel);\n\n\t\tif (dm->dsde_sel == DET_NBI) {\n\t\t\tif (var1[1] < 4) {\n\t\t\t\tdm->nbi_path_sel = (u8)var1[1];\n\t\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t\t out_len - used, \"NBI set path %d\\n\",\n\t\t\t\t\t dm->nbi_path_sel);\n\t\t\t} else {\n\t\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t\t out_len - used, \"path setting fail\\n\");\n\t\t\t}\n\t\t} else if (dm->dsde_sel == DET_CSI) {\n\t\t\tif (var1[1] < 8) {\n\t\t\t\tdm->csi_wgt = (u8)var1[1];\n\t\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t\t out_len - used, \"CSI wgt %d\\n\",\n\t\t\t\t\t dm->csi_wgt);\n\t\t\t} else {\n\t\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t\t out_len - used,\n\t\t\t\t\t \"CSI wgt setting fail\\n\");\n\t\t\t}\n\t\t}\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n#endif\n\nstruct phydm_command {\n\tchar name[16];\n\tu8 id;\n};\n\nenum PHYDM_CMD_ID {\n\tPHYDM_HELP,\n\tPHYDM_DEMO,\n\tPHYDM_RF_CMD,\n\tPHYDM_DIG,\n\tPHYDM_RA,\n\tPHYDM_PROFILE,\n\tPHYDM_ANTDIV,\n\tPHYDM_PATHDIV,\n\tPHYDM_DEBUG,\n\tPHYDM_MP_DEBUG,\n\tPHYDM_FW_DEBUG,\n\tPHYDM_SUPPORT_ABILITY,\n\tPHYDM_GET_TXAGC,\n\tPHYDM_SET_TXAGC,\n\tPHYDM_SMART_ANT,\n\tPHYDM_CH_BW,\n\tPHYDM_TRX_PATH,\n\tPHYDM_LA_MODE,\n\tPHYDM_DUMP_REG,\n\tPHYDM_AUTO_DBG,\n\tPHYDM_DD_DBG,\n\tPHYDM_BIG_JUMP,\n\tPHYDM_SHOW_RXRATE,\n\tPHYDM_NBI_EN,\n\tPHYDM_CSI_MASK_EN,\n\tPHYDM_DFS_DEBUG,\n\tPHYDM_DFS_HIST,\n\tPHYDM_NHM,\n\tPHYDM_CLM,\n\tPHYDM_FAHM,\n\tPHYDM_ENV_MNTR,\n\tPHYDM_BB_INFO,\n\t//PHYDM_TXBF,\n\tPHYDM_H2C,\n\tPHYDM_EXT_RF_E_CTRL,\n\tPHYDM_ADAPTIVE_SOML,\n\tPHYDM_PSD,\n\tPHYDM_DEBUG_PORT,\n\tPHYDM_DIS_HTSTF_CONTROL,\n\tPHYDM_CFO_TRK,\n\tPHYDM_ADAPTIVITY_DEBUG,\n\tPHYDM_DIS_DYM_ANT_WEIGHTING,\n\tPHYDM_FORECE_PT_STATE,\n\tPHYDM_STA_INFO,\n\tPHYDM_PAUSE_FUNC,\n\tPHYDM_PER_TONE_EVM,\n\tPHYDM_DYN_TXPWR,\n\tPHYDM_LNA_SAT,\n\tPHYDM_ANAPAR,\n\tPHYDM_BEAM_FORMING,\n#if RTL8814B_SUPPORT\n\tPHYDM_SPUR_DETECT\n#endif\n};\n\nstruct phydm_command phy_dm_ary[] = {\n\t{\"-h\", PHYDM_HELP}, /*@do not move this element to other position*/\n\t{\"demo\", PHYDM_DEMO}, /*@do not move this element to other position*/\n\t{\"rf\", PHYDM_RF_CMD},\n\t{\"dig\", PHYDM_DIG},\n\t{\"ra\", PHYDM_RA},\n\t{\"profile\", PHYDM_PROFILE},\n\t{\"antdiv\", PHYDM_ANTDIV},\n\t{\"pathdiv\", PHYDM_PATHDIV},\n\t{\"dbg\", PHYDM_DEBUG},\n\t{\"mp_dbg\", PHYDM_MP_DEBUG},\n\t{\"fw_dbg\", PHYDM_FW_DEBUG},\n\t{\"ability\", PHYDM_SUPPORT_ABILITY},\n\t{\"get_txagc\", PHYDM_GET_TXAGC},\n\t{\"set_txagc\", PHYDM_SET_TXAGC},\n\t{\"smtant\", PHYDM_SMART_ANT},\n\t{\"ch_bw\", PHYDM_CH_BW},\n\t{\"trxpath\", PHYDM_TRX_PATH},\n\t{\"lamode\", PHYDM_LA_MODE},\n\t{\"dumpreg\", PHYDM_DUMP_REG},\n\t{\"auto_dbg\", PHYDM_AUTO_DBG},\n\t{\"dd_dbg\", PHYDM_DD_DBG},\n\t{\"bigjump\", PHYDM_BIG_JUMP},\n\t{\"rxrate\", PHYDM_SHOW_RXRATE},\n\t{\"nbi\", PHYDM_NBI_EN},\n\t{\"csi_mask\", PHYDM_CSI_MASK_EN},\n\t{\"dfs\", PHYDM_DFS_DEBUG},\n\t{\"dfs_hist\", PHYDM_DFS_HIST},\n\t{\"nhm\", PHYDM_NHM},\n\t{\"clm\", PHYDM_CLM},\n\t{\"fahm\", PHYDM_FAHM},\n\t{\"env_mntr\", PHYDM_ENV_MNTR},\n\t{\"bbinfo\", PHYDM_BB_INFO},\n\t//{\"txbf\", PHYDM_TXBF},\n\t{\"h2c\", PHYDM_H2C},\n\t{\"ext_rfe\", PHYDM_EXT_RF_E_CTRL},\n\t{\"soml\", PHYDM_ADAPTIVE_SOML},\n\t{\"psd\", PHYDM_PSD},\n\t{\"dbgport\", PHYDM_DEBUG_PORT},\n\t{\"dis_htstf\", PHYDM_DIS_HTSTF_CONTROL},\n\t{\"cfo_trk\", PHYDM_CFO_TRK},\n\t{\"adapt_debug\", PHYDM_ADAPTIVITY_DEBUG},\n\t{\"dis_dym_ant_wgt\", PHYDM_DIS_DYM_ANT_WEIGHTING},\n\t{\"force_pt_state\", PHYDM_FORECE_PT_STATE},\n\t{\"sta_info\", PHYDM_STA_INFO},\n\t{\"pause\", PHYDM_PAUSE_FUNC},\n\t{\"evm\", PHYDM_PER_TONE_EVM},\n\t{\"dyn_txpwr\", PHYDM_DYN_TXPWR},\n\t{\"lna_sat\", PHYDM_LNA_SAT},\n\t{\"anapar\", PHYDM_ANAPAR},\n\t{\"bf\", PHYDM_BEAM_FORMING},\n#if RTL8814B_SUPPORT\n\t{\"spur_detect\", PHYDM_SPUR_DETECT}\n#endif\n\t};\n\n#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/\n\nvoid phydm_cmd_parser(struct dm_struct *dm, char input[][MAX_ARGV],\n\t\t      u32 input_num, u8 flag, char *output, u32 out_len)\n{\n#ifdef CONFIG_PHYDM_DEBUG_FUNCTION\n\tu32 used = 0;\n\tu8 id = 0;\n\tu32 var1[10] = {0};\n\tu32 i;\n\tu32 phydm_ary_size = sizeof(phy_dm_ary) / sizeof(struct phydm_command);\n\n\tif (flag == 0) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"GET, nothing to print\\n\");\n\t\treturn;\n\t}\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used, \"\\n\");\n\n\t/* Parsing Cmd ID */\n\tif (input_num) {\n\t\tfor (i = 0; i < phydm_ary_size; i++) {\n\t\t\tif (strcmp(phy_dm_ary[i].name, input[0]) == 0) {\n\t\t\t\tid = phy_dm_ary[i].id;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (i == phydm_ary_size) {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"PHYDM command not found!\\n\");\n\t\t\treturn;\n\t\t}\n\t}\n\n\tswitch (id) {\n\tcase PHYDM_HELP: {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"BB cmd ==>\\n\");\n\n\t\tfor (i = 0; i < phydm_ary_size - 2; i++)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"  %-5d: %s\\n\", i, phy_dm_ary[i + 2].name);\n\t} break;\n\n\tcase PHYDM_DEMO: { /*@echo demo 10 0x3a z abcde >cmd*/\n\t\tu32 directory = 0;\n\n\t\t#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))\n\t\tchar char_temp;\n\t\t#else\n\t\tu32 char_temp = ' ';\n\t\t#endif\n\n\t\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &directory);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Decimal value = %d\\n\", directory);\n\t\tPHYDM_SSCANF(input[2], DCMD_HEX, &directory);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Hex value = 0x%x\\n\", directory);\n\t\tPHYDM_SSCANF(input[3], DCMD_CHAR, &char_temp);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Char = %c\\n\", char_temp);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"String = %s\\n\", input[4]);\n\t} break;\n\tcase PHYDM_RF_CMD:\n\t\thalrf_cmd_parser(dm, input, &used, output, &out_len, input_num);\n\t\tbreak;\n\n\tcase PHYDM_DIG:\n\t\tphydm_dig_debug(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_RA:\n\t\tphydm_ra_debug(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_ANTDIV:\n\t\t#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))\n\t\tphydm_antdiv_debug(dm, input, &used, output, &out_len);\n\t\t#endif\n\t\tbreak;\n\n\tcase PHYDM_PATHDIV:\n\t\t#if (defined(CONFIG_PATH_DIVERSITY))\n\t\tphydm_pathdiv_debug(dm, input, &used, output, &out_len);\n\t\t#endif\n\t\tbreak;\n\n\tcase PHYDM_DEBUG:\n\t\tphydm_debug_trace(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_MP_DEBUG:\n\t\tphydm_mp_dbg(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_FW_DEBUG:\n\t\tphydm_fw_debug_trace(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_SUPPORT_ABILITY:\n\t\tphydm_supportability_en(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_SMART_ANT:\n\t\t#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))\n\n\t\t#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2\n\t\tphydm_hl_smt_ant_dbg_type2(dm, input, &used, output, &out_len);\n\t\t#elif (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))\n\t\tphydm_hl_smart_ant_debug(dm, input, &used, output, &out_len);\n\t\t#endif\n\n\t\t#elif (defined(CONFIG_CUMITEK_SMART_ANTENNA))\n\t\tphydm_cumitek_smt_ant_debug(dm, input, &used, output, &out_len);\n\t\t#endif\n\n\t\tbreak;\n\n\tcase PHYDM_CH_BW:\n\t\tphydm_bw_ch_adjust(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_PROFILE:\n\t\tphydm_basic_profile(dm, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_GET_TXAGC:\n\t\tphydm_get_txagc(dm, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_SET_TXAGC:\n\t\tphydm_set_txagc_dbg(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_TRX_PATH:\n\t\tphydm_config_trx_path(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_LA_MODE:\n\t\t#if (PHYDM_LA_MODE_SUPPORT)\n\t\tphydm_la_cmd(dm, input, &used, output, &out_len);\n\t\t#endif\n\t\tbreak;\n\n\tcase PHYDM_DUMP_REG:\n\t\tphydm_dump_reg(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_BIG_JUMP:\n\t\tphydm_enable_big_jump(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_AUTO_DBG:\n\t\t#ifdef PHYDM_AUTO_DEGBUG\n\t\tphydm_auto_dbg_console(dm, input, &used, output, &out_len);\n\t\t#endif\n\t\tbreak;\n\n\tcase PHYDM_DD_DBG:\n\t\tphydm_dd_dbg_dump(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_SHOW_RXRATE:\n\t\tphydm_show_rx_rate(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_NBI_EN:\n\t\tphydm_nbi_debug(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_CSI_MASK_EN:\n\t\tphydm_csi_debug(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\t#ifdef CONFIG_PHYDM_DFS_MASTER\n\tcase PHYDM_DFS_DEBUG:\n\t\tphydm_dfs_debug(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_DFS_HIST:\n\t\tphydm_dfs_hist_dbg(dm, input, &used, output, &out_len);\n\t\tbreak;\n\t#endif\n\n\tcase PHYDM_NHM:\n\t\t#ifdef NHM_SUPPORT\n\t\tphydm_nhm_dbg(dm, input, &used, output, &out_len);\n\t\t#endif\n\t\tbreak;\n\n\tcase PHYDM_CLM:\n\t\t#ifdef CLM_SUPPORT\n\t\tphydm_clm_dbg(dm, input, &used, output, &out_len);\n\t\t#endif\n\t\tbreak;\n\n\t#ifdef FAHM_SUPPORT\n\tcase PHYDM_FAHM:\n\t\tphydm_fahm_dbg(dm, input, &used, output, &out_len);\n\t\tbreak;\n\t#endif\n\n\tcase PHYDM_ENV_MNTR:\n\t\tphydm_env_mntr_dbg(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_BB_INFO:\n\t\tphydm_bb_hw_dbg_info(dm, input, &used, output, &out_len);\n\t\tbreak;\n\t/*\n\tcase PHYDM_TXBF: {\n\t#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\t#ifdef PHYDM_BEAMFORMING_SUPPORT\n\t\tstruct _RT_BEAMFORMING_INFO *beamforming_info = NULL;\n\n\t\tbeamforming_info = &dm->beamforming_info;\n\n\t\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);\n\t\tif (var1[0] == 0) {\n\t\t\tbeamforming_info->apply_v_matrix = false;\n\t\t\tbeamforming_info->snding3ss = true;\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"\\r\\n dont apply V matrix and 3SS 789 snding\\n\");\n\t\t} else if (var1[0] == 1) {\n\t\t\tbeamforming_info->apply_v_matrix = true;\n\t\t\tbeamforming_info->snding3ss = true;\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"\\r\\n apply V matrix and 3SS 789 snding\\n\");\n\t\t} else if (var1[0] == 2) {\n\t\t\tbeamforming_info->apply_v_matrix = true;\n\t\t\tbeamforming_info->snding3ss = false;\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"\\r\\n default txbf setting\\n\");\n\t\t} else\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"\\r\\n unknown cmd!!\\n\");\n\t#endif\n\t#endif\n\t} break;\n\t*/\n\tcase PHYDM_H2C:\n\t\tphydm_h2C_debug(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_EXT_RF_E_CTRL:\n\t\tphydm_ext_rf_element_ctrl(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_ADAPTIVE_SOML:\n\t\t#ifdef CONFIG_ADAPTIVE_SOML\n\t\tphydm_soml_debug(dm, input, &used, output, &out_len);\n\t\t#endif\n\t\tbreak;\n\n\tcase PHYDM_PSD:\n\n\t\t#ifdef CONFIG_PSD_TOOL\n\t\tphydm_psd_debug(dm, input, &used, output, &out_len);\n\t\t#endif\n\n\t\tbreak;\n\n\tcase PHYDM_DEBUG_PORT:\n\t\tphydm_print_dbgport(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_DIS_HTSTF_CONTROL: {\n\t\tif (input[1])\n\t\t\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);\n\n\t\tif (var1[0] == 1) {\n\t\t\t/* setting being false is for debug */\n\t\t\tdm->bhtstfdisabled = true;\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"Dynamic HT-STF Gain Control is Disable\\n\");\n\t\t} else {\n\t\t\t/* @default setting should be true,\n\t\t\t * always be dynamic control\n\t\t\t */\n\t\t\tdm->bhtstfdisabled = false;\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"Dynamic HT-STF Gain Control is Enable\\n\");\n\t\t}\n\t} break;\n\n\tcase PHYDM_CFO_TRK:\n\t\tphydm_cfo_tracking_debug(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_ADAPTIVITY_DEBUG:\n\t\t#ifdef PHYDM_SUPPORT_ADAPTIVITY\n\t\tphydm_adaptivity_debug(dm, input, &used, output, &out_len);\n\t\t#endif\n\t\tbreak;\n\n\tcase PHYDM_DIS_DYM_ANT_WEIGHTING:\n\t\t#ifdef DYN_ANT_WEIGHTING_SUPPORT\n\t\tphydm_ant_weight_dbg(dm, input, &used, output, &out_len);\n\t\t#endif\n\t\tbreak;\n\n\tcase PHYDM_FORECE_PT_STATE:\n\t\t#ifdef PHYDM_POWER_TRAINING_SUPPORT\n\t\tphydm_pow_train_debug(dm, input, &used, output, &out_len);\n\t\t#endif\n\t\tbreak;\n\n\tcase PHYDM_STA_INFO:\n\t\tphydm_show_sta_info(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_PAUSE_FUNC:\n\t\tphydm_pause_func_console(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\tcase PHYDM_PER_TONE_EVM:\n\t\tphydm_per_tone_evm(dm, input, &used, output, &out_len);\n\t\tbreak;\n\n\t#ifdef CONFIG_DYNAMIC_TX_TWR\n\tcase PHYDM_DYN_TXPWR:\n\t\tphydm_dtp_debug(dm, input, &used, output, &out_len);\n\t\tbreak;\n\t#endif\n\n\tcase PHYDM_LNA_SAT:\n\t\t#ifdef PHYDM_LNA_SAT_CHK_SUPPORT\n\t\tphydm_lna_sat_debug(dm, input, &used, output, &out_len);\n\t\t#endif\n\t\tbreak;\n\n\tcase PHYDM_ANAPAR:\n\t\tphydm_get_anapar_table(dm, &used, output, &out_len);\n\t\tbreak;\n\tcase PHYDM_BEAM_FORMING:\n\t\t#ifdef CONFIG_BB_TXBF_API\n\t\tphydm_bf_debug(dm, input, &used, output, &out_len);\n\t\t#endif\n\t\tbreak;\n\n#if RTL8814B_SUPPORT\n\tcase PHYDM_SPUR_DETECT:\n\t\tphydm_spur_detect_dbg(dm, input, &used, output, &out_len);\n\t\tbreak;\n#endif\n\tdefault:\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Do not support this command\\n\");\n\t\tbreak;\n\t}\n#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/\n}\n\n#if defined __ECOS || defined __ICCARM__\nchar *strsep(char **s, const char *ct)\n{\n\tchar *sbegin = *s;\n\tchar *end;\n\n\tif (!sbegin)\n\t\treturn NULL;\n\n\tend = strpbrk(sbegin, ct);\n\tif (end)\n\t\t*end++ = '\\0';\n\t*s = end;\n\treturn sbegin;\n}\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP | ODM_IOT))\ns32 phydm_cmd(struct dm_struct *dm, char *input, u32 in_len, u8 flag,\n\t      char *output, u32 out_len)\n{\n\tchar *token;\n\tu32 argc = 0;\n\tchar argv[MAX_ARGC][MAX_ARGV];\n\n\tdo {\n\t\ttoken = strsep(&input, \", \");\n\t\tif (token) {\n\t\t\tif (strlen(token) <= MAX_ARGV)\n\t\t\t\tstrcpy(argv[argc], token);\n\n\t\t\targc++;\n\t\t} else {\n\t\t\tbreak;\n\t\t}\n\t} while (argc < MAX_ARGC);\n\n\tif (argc == 1)\n\t\targv[0][strlen(argv[0]) - 1] = '\\0';\n\n\tphydm_cmd_parser(dm, argv, argc, flag, output, out_len);\n\n\treturn 0;\n}\n#endif\n\nvoid phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)\n{\n#ifdef CONFIG_PHYDM_DEBUG_FUNCTION\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\t/*@u8\tdebug_trace_11byte[60];*/\n\tu8 freg_num, c2h_seq, buf_0 = 0;\n\n\tif (!(dm->support_ic_type & PHYDM_IC_3081_SERIES))\n\t\treturn;\n\n\tif (cmd_len > 12 || cmd_len == 0) {\n\t\tpr_debug(\"[Warning] Error C2H cmd_len=%d\\n\", cmd_len);\n\t\treturn;\n\t}\n\n\tbuf_0 = cmd_buf[0];\n\tfreg_num = (buf_0 & 0xf);\n\tc2h_seq = (buf_0 & 0xf0) >> 4;\n\n\t#if 0\n\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t  \"[FW debug message] freg_num = (( %d )), c2h_seq=(( %d ))\\n\",\n\t\t  freg_num, c2h_seq);\n\n\tstrncpy(debug_trace_11byte, &cmd_buf[1], (cmd_len - 1));\n\tdebug_trace_11byte[cmd_len - 1] = '\\0';\n\tPHYDM_DBG(dm, DBG_FW_TRACE, \"[FW debug message] %s\\n\",\n\t\t  debug_trace_11byte);\n\tPHYDM_DBG(dm, DBG_FW_TRACE, \"[FW debug message] cmd_len = (( %d ))\\n\",\n\t\t  cmd_len);\n\tPHYDM_DBG(dm, DBG_FW_TRACE, \"[FW debug message] c2h_cmd_start=((%d))\\n\",\n\t\t  dm->c2h_cmd_start);\n\n\tPHYDM_DBG(dm, DBG_FW_TRACE, \"pre_seq = (( %d )), current_seq=((%d))\\n\",\n\t\t  dm->pre_c2h_seq, c2h_seq);\n\tPHYDM_DBG(dm, DBG_FW_TRACE, \"fw_buff_is_enpty = (( %d ))\\n\",\n\t\t  dm->fw_buff_is_enpty);\n\t#endif\n\n\tif (c2h_seq != dm->pre_c2h_seq && dm->fw_buff_is_enpty == false) {\n\t\tdm->fw_debug_trace[dm->c2h_cmd_start] = '\\0';\n\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"[FW Dbg Queue Overflow] %s\\n\",\n\t\t\t  dm->fw_debug_trace);\n\t\tdm->c2h_cmd_start = 0;\n\t}\n\n\tif ((cmd_len - 1) > (60 - dm->c2h_cmd_start)) {\n\t\tdm->fw_debug_trace[dm->c2h_cmd_start] = '\\0';\n\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t  \"[FW Dbg Queue error: wrong C2H length] %s\\n\",\n\t\t\t  dm->fw_debug_trace);\n\t\tdm->c2h_cmd_start = 0;\n\t\treturn;\n\t}\n\n\tstrncpy((char *)&dm->fw_debug_trace[dm->c2h_cmd_start],\n\t\t(char *)&cmd_buf[1], (cmd_len - 1));\n\tdm->c2h_cmd_start += (cmd_len - 1);\n\tdm->fw_buff_is_enpty = false;\n\n\tif (freg_num == 0 || dm->c2h_cmd_start >= 60) {\n\t\tif (dm->c2h_cmd_start < 60)\n\t\t\tdm->fw_debug_trace[dm->c2h_cmd_start] = '\\0';\n\t\telse\n\t\t\tdm->fw_debug_trace[59] = '\\0';\n\n\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"[FW DBG Msg] %s\\n\",\n\t\t\t  dm->fw_debug_trace);\n#if 0\n\t\t/*@dbg_print(\"[FW DBG Msg] %s\\n\", dm->fw_debug_trace);*/\n#endif\n\t\tdm->c2h_cmd_start = 0;\n\t\tdm->fw_buff_is_enpty = true;\n\t}\n\n\tdm->pre_c2h_seq = c2h_seq;\n#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/\n}\n\nvoid phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len)\n{\n#ifdef CONFIG_PHYDM_DEBUG_FUNCTION\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 function = buffer[0];\n\tu8 dbg_num = buffer[1];\n\tu16 content_0 = (((u16)buffer[3]) << 8) | ((u16)buffer[2]);\n\tu16 content_1 = (((u16)buffer[5]) << 8) | ((u16)buffer[4]);\n\tu16 content_2 = (((u16)buffer[7]) << 8) | ((u16)buffer[6]);\n\tu16 content_3 = (((u16)buffer[9]) << 8) | ((u16)buffer[8]);\n\tu16 content_4 = (((u16)buffer[11]) << 8) | ((u16)buffer[10]);\n\n\tif (cmd_len > 12)\n\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t  \"[FW Msg] Invalid cmd length (( %d )) >12\\n\",\n\t\t\t  cmd_len);\n/*@--------------------------------------------*/\n#ifdef CONFIG_RA_FW_DBG_CODE\n\tif (function == RATE_DECISION) {\n\t\tif (dbg_num == 0) {\n\t\t\tif (content_0 == 1)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] RA_CNT=((%d))  Max_device=((%d))--------------------------->\\n\",\n\t\t\t\t\t  content_1, content_2);\n\t\t\telse if (content_0 == 2)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] Check RA macid= ((%d)), MediaStatus=((%d)), Dis_RA=((%d)),  try_bit=((0x%x))\\n\",\n\t\t\t\t\t  content_1, content_2, content_3,\n\t\t\t\t\t  content_4);\n\t\t\telse if (content_0 == 3)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] Check RA  total=((%d)),  drop=((0x%x)), TXRPT_TRY_bit=((%x)), bNoisy=((%x))\\n\",\n\t\t\t\t\t  content_1, content_2, content_3,\n\t\t\t\t\t  content_4);\n\t\t} else if (dbg_num == 1) {\n\t\t\tif (content_0 == 1)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] RTY[0,1,2,3]=[ %d , %d , %d , %d ]\\n\",\n\t\t\t\t\t  content_1, content_2, content_3,\n\t\t\t\t\t  content_4);\n\t\t\telse if (content_0 == 2) {\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] RTY[4]=[ %d ], drop=(( %d )), total=(( %d )), current_rate=((0x %x ))\",\n\t\t\t\t\t  content_1, content_2, content_3,\n\t\t\t\t\t  content_4);\n\t\t\t\tphydm_print_rate(dm, (u8)content_4,\n\t\t\t\t\t\t DBG_FW_TRACE);\n\t\t\t} else if (content_0 == 3)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] penality_idx=(( %d ))\\n\",\n\t\t\t\t\t  content_1);\n\t\t\telse if (content_0 == 4)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] RSSI=(( %d )), ra_stage = (( %d ))\\n\",\n\t\t\t\t\t  content_1, content_2);\n\t\t} else if (dbg_num == 3) {\n\t\t\tif (content_0 == 1)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] Fast_RA (( DOWN ))  total=((%d)),  total>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\\n\",\n\t\t\t\t\t  content_1, content_2, content_3,\n\t\t\t\t\t  content_4);\n\t\t\telse if (content_0 == 2)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] Fast_RA (( UP ))  total_acc=((%d)),  total_acc>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\\n\",\n\t\t\t\t\t  content_1, content_2, content_3,\n\t\t\t\t\t  content_4);\n\t\t\telse if (content_0 == 3)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] Fast_RA (( UP )) ((rate Down Hold))  RA_CNT=((%d))\\n\",\n\t\t\t\t\t  content_1);\n\t\t\telse if (content_0 == 4)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] Fast_RA (( UP )) ((tota_accl<5 skip))  RA_CNT=((%d))\\n\",\n\t\t\t\t\t  content_1);\n\t\t\telse if (content_0 == 8)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] Fast_RA (( Reset Tx Rpt )) RA_CNT=((%d))\\n\",\n\t\t\t\t\t  content_1);\n\t\t} else if (dbg_num == 4) {\n\t\t\tif (content_0 == 3)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] RER_CNT   PCR_ori =(( %d )),  ratio_ori =(( %d )), pcr_updown_bitmap =(( 0x%x )), pcr_var_diff =(( %d ))\\n\",\n\t\t\t\t\t  content_1, content_2, content_3,\n\t\t\t\t\t  content_4);\n\t\t\telse if (content_0 == 4)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] pcr_shift_value =(( %s%d )), rate_down_threshold =(( %d )), rate_up_threshold =(( %d ))\\n\",\n\t\t\t\t\t  ((content_1) ? \"+\" : \"-\"), content_2,\n\t\t\t\t\t  content_3, content_4);\n\t\t\telse if (content_0 == 5)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] pcr_mean =(( %d )), PCR_VAR =(( %d )), offset =(( %d )), decision_offset_p =(( %d ))\\n\",\n\t\t\t\t\t  content_1, content_2, content_3,\n\t\t\t\t\t  content_4);\n\t\t} else if (dbg_num == 5) {\n\t\t\tif (content_0 == 1)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] (( UP))  Nsc=(( %d )), N_High=(( %d )), RateUp_Waiting=(( %d )), RateUp_Fail=(( %d ))\\n\",\n\t\t\t\t\t  content_1, content_2, content_3,\n\t\t\t\t\t  content_4);\n\t\t\telse if (content_0 == 2)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] ((DOWN))  Nsc=(( %d )), N_Low=(( %d ))\\n\",\n\t\t\t\t\t  content_1, content_2);\n\t\t\telse if (content_0 == 3)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] ((HOLD))  Nsc=((%d)), N_High=((%d)), N_Low=((%d)), Reset_CNT=((%d))\\n\",\n\t\t\t\t\t  content_1, content_2, content_3,\n\t\t\t\t\t  content_4);\n\t\t} else if (dbg_num == 0x60) {\n\t\t\tif (content_0 == 1)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] ((AP RPT))  macid=((%d)), BUPDATE[macid]=((%d))\\n\",\n\t\t\t\t\t  content_1, content_2);\n\t\t\telse if (content_0 == 4)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] ((AP RPT))  pass=((%d)), rty_num=((%d)), drop=((%d)), total=((%d))\\n\",\n\t\t\t\t\t  content_1, content_2, content_3,\n\t\t\t\t\t  content_4);\n\t\t\telse if (content_0 == 5)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW] ((AP RPT))  PASS=((%d)), RTY_NUM=((%d)), DROP=((%d)), TOTAL=((%d))\\n\",\n\t\t\t\t\t  content_1, content_2, content_3,\n\t\t\t\t\t  content_4);\n\t\t}\n\t} else if (function == INIT_RA_TABLE) {\n\t\tif (dbg_num == 3)\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t  \"[FW][INIT_RA_INFO] Ra_init, RA_SKIP_CNT = (( %d ))\\n\",\n\t\t\t\t  content_0);\n\t} else if (function == RATE_UP) {\n\t\tif (dbg_num == 2) {\n\t\t\tif (content_0 == 1)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW][RateUp]  ((Highest rate->return)), macid=((%d))  Nsc=((%d))\\n\",\n\t\t\t\t\t  content_1, content_2);\n\t\t} else if (dbg_num == 5) {\n\t\t\tif (content_0 == 0)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW][RateUp]  ((rate UP)), up_rate_tmp=((0x%x)), rate_idx=((0x%x)), SGI_en=((%d)),  SGI=((%d))\\n\",\n\t\t\t\t\t  content_1, content_2, content_3,\n\t\t\t\t\t  content_4);\n\t\t\telse if (content_0 == 1)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW][RateUp]  ((rate UP)), rate_1=((0x%x)), rate_2=((0x%x)), BW=((%d)), Try_Bit=((%d))\\n\",\n\t\t\t\t\t  content_1, content_2, content_3,\n\t\t\t\t\t  content_4);\n\t\t}\n\t} else if (function == RATE_DOWN) {\n\t\tif (dbg_num == 5) {\n\t\t\tif (content_0 == 1)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW][RateDownStep]  ((rate Down)), macid=((%d)), rate1=((0x%x)),  rate2=((0x%x)), BW=((%d))\\n\",\n\t\t\t\t\t  content_1, content_2, content_3,\n\t\t\t\t\t  content_4);\n\t\t}\n\t} else if (function == TRY_DONE) {\n\t\tif (dbg_num == 1) {\n\t\t\tif (content_0 == 1)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW][Try Done]  ((try succsess )) macid=((%d)), Try_Done_cnt=((%d))\\n\",\n\t\t\t\t\t  content_1, content_2);\n\t\t} else if (dbg_num == 2) {\n\t\t\tif (content_0 == 1)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW][Try Done]  ((try)) macid=((%d)), Try_Done_cnt=((%d)),  rate_2=((%d)),  try_succes=((%d))\\n\",\n\t\t\t\t\t  content_1, content_2, content_3,\n\t\t\t\t\t  content_4);\n\t\t}\n\t} else if (function == RA_H2C) {\n\t\tif (dbg_num == 1) {\n\t\t\tif (content_0 == 0)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW][H2C=0x49]  fw_trace_en=((%d)), mode =((%d)),  macid=((%d))\\n\",\n\t\t\t\t\t  content_1, content_2, content_3);\n\t\t}\n\t} else if (function == F_RATE_AP_RPT) {\n\t\tif (dbg_num == 1) {\n\t\t\tif (content_0 == 1)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW][AP RPT]  ((1)), SPE_STATIS=((0x%x))---------->\\n\",\n\t\t\t\t\t  content_3);\n\t\t} else if (dbg_num == 2) {\n\t\t\tif (content_0 == 1)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW][AP RPT]  RTY_all=((%d))\\n\",\n\t\t\t\t\t  content_1);\n\t\t} else if (dbg_num == 3) {\n\t\t\tif (content_0 == 1)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW][AP RPT]  MACID1[%d], TOTAL=((%d)),  RTY=((%d))\\n\",\n\t\t\t\t\t  content_3, content_1, content_2);\n\t\t} else if (dbg_num == 4) {\n\t\t\tif (content_0 == 1)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW][AP RPT]  MACID2[%d], TOTAL=((%d)),  RTY=((%d))\\n\",\n\t\t\t\t\t  content_3, content_1, content_2);\n\t\t} else if (dbg_num == 5) {\n\t\t\tif (content_0 == 1)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW][AP RPT]  MACID1[%d], PASS=((%d)),  DROP=((%d))\\n\",\n\t\t\t\t\t  content_3, content_1, content_2);\n\t\t} else if (dbg_num == 6) {\n\t\t\tif (content_0 == 1)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t\t  \"[FW][AP RPT]  MACID2[%d],, PASS=((%d)),  DROP=((%d))\\n\",\n\t\t\t\t\t  content_3, content_1, content_2);\n\t\t}\n\t} else if (function == DBC_FW_CLM) {\n\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t  \"[FW][CLM][%d, %d] = {%d, %d, %d, %d}\\n\", dbg_num,\n\t\t\t  content_0, content_1, content_2, content_3,\n\t\t\t  content_4);\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t  \"[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\\n\",\n\t\t\t  function, dbg_num, content_0, content_1, content_2,\n\t\t\t  content_3, content_4);\n\t}\n#else\n\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t  \"[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\\n\", function,\n\t\t  dbg_num, content_0, content_1, content_2, content_3,\n\t\t  content_4);\n#endif\n/*@--------------------------------------------*/\n\n#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/\n}\n\nvoid phydm_fw_trace_handler_8051(void *dm_void, u8 *buffer, u8 cmd_len)\n{\n#ifdef CONFIG_PHYDM_DEBUG_FUNCTION\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#if 0\n\tif (cmd_len >= 3)\n\t\tcmd_buf[cmd_len - 1] = '\\0';\n\tPHYDM_DBG(dm, DBG_FW_TRACE, \"[FW DBG Msg] %s\\n\", &cmd_buf[3]);\n#else\n\n\tint i = 0;\n\tu8 extend_c2h_sub_id = 0, extend_c2h_dbg_len = 0;\n\tu8 extend_c2h_dbg_seq = 0;\n\tu8 fw_debug_trace[128];\n\tu8 *extend_c2h_dbg_content = 0;\n\n\tif (cmd_len > 127)\n\t\treturn;\n\n\textend_c2h_sub_id = buffer[0];\n\textend_c2h_dbg_len = buffer[1];\n\textend_c2h_dbg_content = buffer + 2; /*@DbgSeq+DbgContent for show HEX*/\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tRT_DISP(FC2H, C2H_Summary, (\"[Extend C2H packet], Extend_c2hSubId=0x%x, extend_c2h_dbg_len=%d\\n\",\n\t\t\t\t    extend_c2h_sub_id, extend_c2h_dbg_len));\n\n\tRT_DISP_DATA(FC2H, C2H_Summary, \"[Extend C2H packet], Content Hex:\", extend_c2h_dbg_content, cmd_len - 2);\n#endif\n\ngo_backfor_aggre_dbg_pkt:\n\ti = 0;\n\textend_c2h_dbg_seq = buffer[2];\n\textend_c2h_dbg_content = buffer + 3;\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tRT_DISP(FC2H, C2H_Summary, (\"[RTKFW, SEQ= %d] :\", extend_c2h_dbg_seq));\n#endif\n\n\tfor (;; i++) {\n\t\tfw_debug_trace[i] = extend_c2h_dbg_content[i];\n\t\tif (extend_c2h_dbg_content[i + 1] == '\\0') {\n\t\t\tfw_debug_trace[i + 1] = '\\0';\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"[FW DBG Msg] %s\",\n\t\t\t\t  &fw_debug_trace[0]);\n\t\t\tbreak;\n\t\t} else if (extend_c2h_dbg_content[i] == '\\n') {\n\t\t\tfw_debug_trace[i + 1] = '\\0';\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"[FW DBG Msg] %s\",\n\t\t\t\t  &fw_debug_trace[0]);\n\t\t\tbuffer = extend_c2h_dbg_content + i + 3;\n\t\t\tgoto go_backfor_aggre_dbg_pkt;\n\t\t}\n\t}\n\n#endif\n#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/\n}\n"
  },
  {
    "path": "hal/phydm/phydm_debug.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __ODM_DBG_H__\n#define __ODM_DBG_H__\n\n/*@#define DEBUG_VERSION\t\"1.1\"*/ /*@2015.07.29 YuChen*/\n/*@#define DEBUG_VERSION\t\"1.2\"*/ /*@2015.08.28 Dino*/\n/*@#define DEBUG_VERSION\t\"1.3\"*/ /*@2016.04.28 YuChen*/\n/*@#define DEBUG_VERSION\t\"1.4\"*/ /*@2017.03.13 Dino*/\n#define DEBUG_VERSION \"2.0\" /*@2018.01.10 Dino*/\n\n/*@\n * ============================================================\n *  Definition\n * ============================================================\n */\n\n/*@FW DBG MSG*/\n#define\tRATE_DECISION\t\t1\n#define\tINIT_RA_TABLE\t\t2\n#define\tRATE_UP\t\t\t4\n#define\tRATE_DOWN\t\t8\n#define\tTRY_DONE\t\t16\n#define\tRA_H2C\t\t\t32\n#define\tF_RATE_AP_RPT\t\t64\n#define\tDBC_FW_CLM\t\t9\n\n#define PHYDM_SNPRINT_SIZE\t64\n/* @----------------------------------------------------------------------------\n * Define the tracing components\n *\n * -----------------------------------------------------------------------------\n * BB FW Functions\n */\n#define\tPHYDM_FW_COMP_RA\tBIT(0)\n#define\tPHYDM_FW_COMP_MU\tBIT(1)\n#define\tPHYDM_FW_COMP_PATH_DIV\tBIT(2)\n#define\tPHYDM_FW_COMP_PT\tBIT(3)\n\n/*@------------------------Export Marco Definition---------------------------*/\n\n#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA)\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t#if (DBG_CMD_SUPPORT == 1)\n\t\textern\tVOID DCMD_Printf(const char *pMsg);\n\t#else\n\t\t#define DCMD_Printf(_pMsg)\n\t#endif\n\n\t#if OS_WIN_FROM_WIN10(OS_VERSION)\n\t#define\tpr_debug(fmt, ...) DbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, fmt, ##__VA_ARGS__)\n\t#else\n\t#define\tpr_debug\t\tDbgPrint\n\t#endif\n\n\t#define\tdcmd_printf\t\tDCMD_Printf\n\t#define\tdcmd_scanf\t\tDCMD_Scanf\n\t#define\tRT_PRINTK\t\tpr_debug\n\t#define\tPRINT_MAX_SIZE\t\t512\n\t#define PHYDM_SNPRINTF\t\tRT_SPRINTF\n\t#define\tPHYDM_TRACE(_MSG_) \tEXhalPHYDMoutsrc_Print(_MSG_)\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\t#define PHYDM_SNPRINTF\t\tsnprintf\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t#undef\tpr_debug\n\t#define pr_debug\t\tprintk\n\t#define RT_PRINTK(fmt, args...)\tpr_debug(fmt, ## args)\n\t#define\tRT_DISP(dbgtype, dbgflag, printstr)\n\t#define RT_TRACE(adapter, comp, drv_level, fmt, args...)\t\\\n\t\tRTW_INFO(fmt, ## args)\n\t#define PHYDM_SNPRINTF\t\tsnprintf\n#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)\n\t#define pr_debug(fmt, args...)\t\tRTW_PRINT_MSG(fmt, ## args)\n\t#define RT_DEBUG(comp, drv_level, fmt, args...)\t\\\n\t\tRTW_PRINT_MSG(fmt, ## args)\n\t#define PHYDM_SNPRINTF\t\tsnprintf\n#else\n\t#define pr_debug\tpanic_printk\n\t/*@#define RT_PRINTK(fmt, args...)\tpr_debug(\"%s(): \" fmt, __FUNCTION__, ## args);*/\n\t#define RT_PRINTK(fmt, args...)\tpr_debug(fmt, ## args)\n\t#define PHYDM_SNPRINTF\t\tsnprintf\n#endif\n\n#ifndef ASSERT\n\t#define ASSERT(expr)\n#endif\n\n#if DBG\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n#define PHYDM_DBG(dm, comp, fmt, args...)\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\tif ((comp) & dm->debug_components) {          \\\n\t\t\tpr_debug(\"[PHYDM] \");\t\t\t\\\n\t\t\tRT_PRINTK(fmt, ## args);\t\t\\\n\t\t}\t\t\t\t\t\t\\\n\t} while (0)\n\n#define PHYDM_DBG_F(dm, comp, fmt, args...)\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\tif ((comp) & dm->debug_components) {\t\t\\\n\t\t\tRT_PRINTK(fmt, ## args);\t\t\\\n\t\t}\t\t\t\t\t\t\\\n\t} while (0)\n\n#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\tif ((comp) & dm->debug_components) {\t\t\\\n\t\t\tint __i;\t\t\t\t\\\n\t\t\tu8 *__ptr = (u8 *)addr;\t\t\t\\\n\t\t\tpr_debug(\"[PHYDM] \");\t\t\t\\\n\t\t\tpr_debug(title_str);\t\t\t\\\n\t\t\tpr_debug(\" \");\t\t\t\t\\\n\t\t\tfor (__i = 0; __i < 6; __i++)\t\t\\\n\t\t\t\tpr_debug(\"%02X%s\", __ptr[__i], (__i == 5) ? \"\" : \"-\");\\\n\t\t\tpr_debug(\"\\n\");\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\\\n\t} while (0)\n#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\nstatic __inline void PHYDM_DBG(PDM_ODM_T dm, int comp, char *fmt, ...)\n{\n\tRT_STATUS rt_status;\n\tva_list args;\n\tchar buf[PRINT_MAX_SIZE] = {0};\n\n\tif ((comp & dm->debug_components) == 0)\n\t\treturn;\n\n\tif (fmt == NULL)\n\t\treturn;\n\n\tva_start(args, fmt);\n\trt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);\n\tva_end(args);\n\n\tif (rt_status != RT_STATUS_SUCCESS) {\n\t\tDbgPrint(\"Failed (%d) to print message to buffer\\n\", rt_status);\n\t\treturn;\n\t}\n\n\t#if OS_WIN_FROM_WIN10(OS_VERSION)\n\tDbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, \"%s\", buf);\n\t#else\n\tDbgPrint(\"%s\", buf);\n\t#endif\n}\n\nstatic __inline void PHYDM_DBG_F(PDM_ODM_T dm, int comp, char *fmt, ...)\n{\n\tRT_STATUS rt_status;\n\tva_list args;\n\tchar buf[PRINT_MAX_SIZE] = {0};\n\n\tif ((comp & dm->debug_components) == 0)\n\t\treturn;\n\n\tif (fmt == NULL)\n\t\treturn;\n\n\tva_start(args, fmt);\n\trt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);\n\tva_end(args);\n\n\tif (rt_status != RT_STATUS_SUCCESS) {\n\t\t/*@DbgPrint(\"DM Print Fail\\n\");*/\n\t\treturn;\n\t}\n\n\t#if OS_WIN_FROM_WIN10(OS_VERSION)\n\tDbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, \"%s\", buf);\n\t#else\n\tDbgPrint(\"%s\", buf);\n\t#endif\n}\n\n#define PHYDM_PRINT_ADDR(p_dm, comp, title_str, ptr)\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\tif ((comp) & p_dm->debug_components) {\t\t\\\n\t\t\t\t\t\t\t\t\\\n\t\t\tint __i;\t\t\t\t\\\n\t\t\tu8 *__ptr = (u8 *)ptr;\t\t\t\\\n\t\t\tpr_debug(\"[PHYDM] \");\t\t\t\\\n\t\t\tpr_debug(title_str);\t\t\t\\\n\t\t\tpr_debug(\" \");\t\t\t\t\\\n\t\t\tfor (__i = 0; __i < 6; __i++)\t\t\\\n\t\t\t\tpr_debug(\"%02X%s\", __ptr[__i], (__i == 5) ? \"\" : \"-\");\t\\\n\t\t\tpr_debug(\"\\n\");\t\t\t\t\\\n\t\t}\t\\\n\t} while (0)\n#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)\n\n#define PHYDM_DBG(dm, comp, fmt, args...)\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\tif ((comp) & dm->debug_components) {\t\t\\\n\t\t\tRT_DEBUG(COMP_PHYDM, \\\n\t\t\t\t DBG_DMESG, \"[PHYDM] \" fmt, ##args);\t\\\n\t\t}\t\t\t\t\t\t\\\n\t} while (0)\n\n#define PHYDM_DBG_F(dm, comp, fmt, args...)\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\tif ((comp) & dm->debug_components) {\t\t\\\n\t\t\tRT_DEBUG(COMP_PHYDM, \\\n\t\t\t\t DBG_DMESG, fmt, ##args);\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\tif ((comp) & dm->debug_components) {\t\t\\\n\t\t\tRT_DEBUG(COMP_PHYDM, \\\n\t\t\t\t DBG_DMESG, \"[PHYDM] \" title_str \"%pM\\n\",\t\\\n\t\t\t\t addr);\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\\\n\t} while (0)\n\n#elif defined(DM_ODM_CE_MAC80211_V2)\n\n#define PHYDM_DBG(dm, comp, fmt, args...)\n#define PHYDM_DBG_F(dm, comp, fmt, args...)\n#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)\n\n#else\n\n#define PHYDM_DBG(dm, comp, fmt, args...)\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\tstruct dm_struct *__dm = (dm);\t\t\t\\\n\t\tif ((comp) & __dm->debug_components) {\t\t\\\n\t\t\tRT_TRACE(((struct rtl_priv *)__dm->adapter),\\\n\t\t\t\t COMP_PHYDM, DBG_DMESG,\t\t\\\n\t\t\t\t \"[PHYDM] \" fmt, ##args);\t\\\n\t\t}\t\t\t\t\t\t\\\n\t} while (0)\n\n#define PHYDM_DBG_F(dm, comp, fmt, args...)\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\tstruct dm_struct *__dm = (dm);\t\t\t\\\n\t\tif ((comp) & __dm->debug_components) {\t\t\\\n\t\t\tRT_TRACE(((struct rtl_priv *)__dm->adapter),\\\n\t\t\t\t COMP_PHYDM, DBG_DMESG, fmt, ##args);\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\tstruct dm_struct *__dm = (dm);\t\t\t\\\n\t\tif ((comp) & __dm->debug_components) {\t\t\\\n\t\t\tRT_TRACE(((struct rtl_priv *)__dm->adapter),\\\n\t\t\t\t COMP_PHYDM, DBG_DMESG,\t\t\\\n\t\t\t\t \"[PHYDM] \" title_str \"%pM\\n\", addr);\\\n\t\t}\t\t\t\t\t\t\\\n\t} while (0)\n#endif\n\n#else /*@#if DBG*/\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nstatic __inline void PHYDM_DBG(struct dm_struct *dm, int comp, char *fmt, ...)\n{\n\tRT_STATUS rt_status;\n\tva_list args;\n\tchar buf[PRINT_MAX_SIZE] = {0};\n\n\tif ((comp & dm->debug_components) == 0)\n\t\treturn;\n\n\tif (fmt == NULL)\n\t\treturn;\n\n\tva_start(args, fmt);\n\trt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);\n\tva_end(args);\n\n\tif (rt_status != RT_STATUS_SUCCESS) {\n\t\tDbgPrint(\"Failed (%d) to print message to buffer\\n\", rt_status);\n\t\treturn;\n\t}\n\n\tPHYDM_TRACE(buf);\n}\nstatic __inline void PHYDM_DBG_F(struct dm_struct *dm, int comp, char *fmt, ...)\n{\n}\n#else\n#define PHYDM_DBG(dm, comp, fmt, args...)\n#define PHYDM_DBG_F(dm, comp, fmt, args...)\n#endif\n#define PHYDM_PRINT_ADDR(dm, comp, title_str, ptr)\n\n#endif\n\n#define\tDBGPORT_PRI_3\t3\t/*@Debug function (the highest priority)*/\n#define\tDBGPORT_PRI_2\t2\t/*@Check hang function & Strong function*/\n#define\tDBGPORT_PRI_1\t1\t/*Watch dog function*/\n#define\tDBGPORT_RELEASE\t0\t/*@Init value (the lowest priority)*/\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#define\tPHYDM_DBGPRINT\t\t0\n#define\tPHYDM_SSCANF(x, y, z)\tdcmd_scanf(x, y, z)\n#define\tPDM_VAST_SNPF\t\tPDM_SNPF\n#if (PHYDM_DBGPRINT == 1)\n#define\tPDM_SNPF(msg)\t\\\n\tdo {\\\n\t\trsprintf msg;\\\n\t\tpr_debug(\"%s\", output);\\\n\t} while (0)\n#else\n\nstatic __inline void PDM_SNPF(u32 out_len, u32 used, char *buff, int len,\n\t\t\t      char *fmt, ...)\n{\n\tRT_STATUS rt_status;\n\tva_list args;\n\tchar buf[PRINT_MAX_SIZE] = {0};\n\n\tif (fmt == NULL)\n\t\treturn;\n\n\tva_start(args, fmt);\n\trt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);\n\tva_end(args);\n\n\tif (rt_status != RT_STATUS_SUCCESS) {\n\t\t/*@DbgPrint(\"DM Print Fail\\n\");*/\n\t\treturn;\n\t}\n\n\tDCMD_Printf(buf);\n}\n\n\n\n#endif\t/*@#if (PHYDM_DBGPRINT == 1)*/\n#else\t/*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__)\n\t#define\tPHYDM_DBGPRINT\t0\n\t#else\n\t#define\tPHYDM_DBGPRINT\t1\n\t#endif\n#define\tMAX_ARGC\t\t20\n#define\tMAX_ARGV\t\t16\n#define\tDCMD_DECIMAL\t\t\"%d\"\n#define\tDCMD_CHAR\t\t\"%c\"\n#define\tDCMD_HEX\t\t\"%x\"\n\n#define\tPHYDM_SSCANF(x, y, z)\tsscanf(x, y, z)\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) RT_PRINTK(fmt, ## args)\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n#define\tPDM_VAST_SNPF(out_len, used, buff, len, fmt, args...)\t\\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\tRT_DEBUG(COMP_PHYDM, DBG_DMESG, fmt, ##args);\t\t\\\n\t} while (0)\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n#define\tPDM_VAST_SNPF(out_len, used, buff, len, fmt, args...)\n#else\n#define\tPDM_VAST_SNPF(out_len, used, buff, len, fmt, args...)\t\\\n\t\tRT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \\\n\t\t\tDBG_DMESG, fmt, ##args)\n#endif\n\n#if (PHYDM_DBGPRINT == 1)\n#define\tPDM_SNPF(out_len, used, buff, len, fmt, args...)\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\tsnprintf(buff, len, fmt, ##args);\t\t\t\\\n\t\tpr_debug(\"%s\", output);\t\t\t\t\t\\\n\t} while (0)\n#else\n#define\tPDM_SNPF(out_len, used, buff, len, fmt, args...)\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\tu32 *__pdm_snpf_u = &(used);\t\t\t\t\\\n\t\tif (out_len > *__pdm_snpf_u)\t\t\t\t\\\n\t\t\t*__pdm_snpf_u += snprintf(buff, len, fmt, ##args);\\\n\t} while (0)\n#endif\n#endif\n/* @1 ============================================================\n * 1  enumeration\n * 1 ============================================================\n */\n\nenum auto_detection_state { /*@Fast antenna training*/\n\tAD_LEGACY_MODE\t= 0,\n\tAD_HT_MODE\t= 1,\n\tAD_VHT_MODE\t= 2\n};\n\n/*@\n * ============================================================\n * 1  structure\n * ============================================================\n */\n\n#ifdef CONFIG_PHYDM_DEBUG_FUNCTION\nu8 phydm_get_l_sig_rate(void *dm_void, u8 rate_idx_l_sig);\n#endif\n\nvoid phydm_init_debug_setting(struct dm_struct *dm);\n\nvoid phydm_bb_dbg_port_header_sel(void *dm_void, u32 header_idx);\n\nu32 phydm_get_bb_dbg_port_idx(void *dm_void);\n\nu8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port);\n\nvoid phydm_release_bb_dbg_port(void *dm_void);\n\nu32 phydm_get_bb_dbg_port_val(void *dm_void);\n\nvoid phydm_reset_rx_rate_distribution(struct dm_struct *dm);\n\nvoid phydm_rx_rate_distribution(void *dm_void);\n\nu16 phydm_rx_avg_phy_rate(void *dm_void);\n\nvoid phydm_show_phy_hitogram(void *dm_void);\n\nvoid phydm_get_avg_phystatus_val(void *dm_void);\n\nvoid phydm_get_phy_statistic(void *dm_void);\n\nvoid phydm_dm_summary(void *dm_void, u8 macid);\n\nvoid phydm_basic_dbg_message(void *dm_void);\n\nvoid phydm_basic_profile(void *dm_void, u32 *_used, char *output,\n\t\t\t u32 *_out_len);\n#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))\ns32 phydm_cmd(struct dm_struct *dm, char *input, u32 in_len, u8 flag,\n\t      char *output, u32 out_len);\n#endif\nvoid phydm_cmd_parser(struct dm_struct *dm, char input[][16], u32 input_num,\n\t\t      u8 flag, char *output, u32 out_len);\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid phydm_basic_dbg_msg_cli_win(void *dm_void, char *buf);\n\nvoid phydm_sbd_check(\n\tstruct dm_struct *dm);\n\nvoid phydm_sbd_callback(\n\tstruct phydm_timer_list *timer);\n\nvoid phydm_sbd_workitem_callback(\n\tvoid *context);\n#endif\n\nvoid phydm_fw_trace_en_h2c(void *dm_void, boolean enable,\n\t\t\t   u32 fw_debug_component, u32 monitor_mode, u32 macid);\n\nvoid phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);\n\nvoid phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len);\n\nvoid phydm_fw_trace_handler_8051(void *dm_void, u8 *cmd_buf, u8 cmd_len);\n\n#endif /* @__ODM_DBG_H__ */\n"
  },
  {
    "path": "hal/phydm/phydm_dfs.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@\n * ============================================================\n * include files\n * ============================================================\n */\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#if defined(CONFIG_PHYDM_DFS_MASTER)\n\nboolean phydm_dfs_is_meteorology_channel(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tu8 ch = *dm->channel;\n\tu8 bw = *dm->band_width;\n\n\treturn ((bw  == CHANNEL_WIDTH_80 && (ch) >= 116 && (ch) <= 128) ||\n\t\t(bw  == CHANNEL_WIDTH_40 && (ch) >= 116 && (ch) <= 128) ||\n\t\t(bw  == CHANNEL_WIDTH_20 && (ch) >= 120 && (ch) <= 128));\n}\n\nvoid phydm_dfs_segment_distinguish(void *dm_void, enum rf_syn syn_path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (!(dm->support_ic_type & (ODM_RTL8814B)))\n\t\treturn;\n\tif (syn_path == RF_SYN1)\n\t\tdm->seg1_dfs_flag = 1;\n\telse\n\t\tdm->seg1_dfs_flag = 0;\n}\n\nvoid phydm_dfs_segment_flag_reset(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (!(dm->support_ic_type & (ODM_RTL8814B)))\n\t\treturn;\n\tif (dm->seg1_dfs_flag)\n\t\tdm->seg1_dfs_flag = 0;\n}\n\nvoid phydm_radar_detect_reset(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |\n\t\t\t\t   ODM_RTL8197G)) {\n\t\todm_set_bb_reg(dm, R_0xa40, BIT(15), 0);\n\t\todm_set_bb_reg(dm, R_0xa40, BIT(15), 1);\n\t#if (RTL8721D_SUPPORT)\n\t} else if (dm->support_ic_type & (ODM_RTL8721D)) {\n\t\todm_set_bb_reg(dm, R_0xf58, BIT(29), 0);\n\t\todm_set_bb_reg(dm, R_0xf58, BIT(29), 1);\n\t#endif\n\t} else if (dm->support_ic_type & (ODM_RTL8814B)) {\n\t\tif (dm->seg1_dfs_flag == 1) {\n\t\t\todm_set_bb_reg(dm, R_0xa6c, BIT(0), 0);\n\t\t\todm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);\n\t\t\treturn;\n\t\t}\n\t\todm_set_bb_reg(dm, R_0xa40, BIT(15), 0);\n\t\todm_set_bb_reg(dm, R_0xa40, BIT(15), 1);\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x924, BIT(15), 0);\n\t\todm_set_bb_reg(dm, R_0x924, BIT(15), 1);\n\t}\n}\n\nvoid phydm_radar_detect_disable(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |\n\t\t\t\t   ODM_RTL8197G))\n\t\todm_set_bb_reg(dm, R_0xa40, BIT(15), 0);\n\telse if (dm->support_ic_type & (ODM_RTL8814B)) {\n\t\tif (dm->seg1_dfs_flag == 1) {\n\t\t\todm_set_bb_reg(dm, R_0xa6c, BIT(0), 0);\n\t\t\tdm->seg1_dfs_flag = 0;\n\t\t\treturn;\n\t\t}\n\t\todm_set_bb_reg(dm, R_0xa40, BIT(15), 0);\n\t}\n\t#if (RTL8721D_SUPPORT)\n\telse if (dm->support_ic_type & (ODM_RTL8721D))\n\t\todm_set_bb_reg(dm, R_0xf58, BIT(29), 0);\n\t#endif\n\telse\n\t\todm_set_bb_reg(dm, R_0x924, BIT(15), 0);\n\n\tPHYDM_DBG(dm, DBG_DFS, \"\\n\");\n}\n\nstatic void phydm_radar_detect_with_dbg_parm(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_RTL8721D) {\n\t\todm_set_bb_reg(dm, R_0xf54, MASKDWORD,\n\t\t\t       dm->radar_detect_reg_f54);\n\t\todm_set_bb_reg(dm, R_0xf58, MASKDWORD,\n\t\t\t       dm->radar_detect_reg_f58);\n\t\todm_set_bb_reg(dm, R_0xf5c, MASKDWORD,\n\t\t\t       dm->radar_detect_reg_f5c);\n\t\todm_set_bb_reg(dm, R_0xf70, MASKDWORD,\n\t\t\t       dm->radar_detect_reg_f70);\n\t\todm_set_bb_reg(dm, R_0xf74, MASKDWORD,\n\t\t\t       dm->radar_detect_reg_f74);\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\todm_set_bb_reg(dm, R_0xa40, MASKDWORD,\n\t\t\t       dm->radar_detect_reg_a40);\n\t\todm_set_bb_reg(dm, R_0xa44, MASKDWORD,\n\t\t\t       dm->radar_detect_reg_a44);\n\t\todm_set_bb_reg(dm, R_0xa48, MASKDWORD,\n\t\t\t       dm->radar_detect_reg_a48);\n\t\todm_set_bb_reg(dm, R_0xa4c, MASKDWORD,\n\t\t\t       dm->radar_detect_reg_a4c);\n\t\todm_set_bb_reg(dm, R_0xa50, MASKDWORD,\n\t\t\t       dm->radar_detect_reg_a50);\n\t\todm_set_bb_reg(dm, R_0xa54, MASKDWORD,\n\t\t\t       dm->radar_detect_reg_a54);\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x918, MASKDWORD,\n\t\t\t       dm->radar_detect_reg_918);\n\t\todm_set_bb_reg(dm, R_0x91c, MASKDWORD,\n\t\t\t       dm->radar_detect_reg_91c);\n\t\todm_set_bb_reg(dm, R_0x920, MASKDWORD,\n\t\t\t       dm->radar_detect_reg_920);\n\t\todm_set_bb_reg(dm, R_0x924, MASKDWORD,\n\t\t\t       dm->radar_detect_reg_924);\n\t}\n}\n\n/* @Init radar detection parameters, called after ch, bw is set */\n\nvoid phydm_radar_detect_enable(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _DFS_STATISTICS *dfs = &dm->dfs;\n\tu8 region_domain = dm->dfs_region_domain;\n\tu8 c_channel = *dm->channel;\n\tu8 band_width = *dm->band_width;\n\tu8 enable = 0, i;\n\tu8 short_pw_upperbound = 0;\n\n\tPHYDM_DBG(dm, DBG_DFS, \"test, region_domain = %d\\n\", region_domain);\n\tif (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) {\n\t\tPHYDM_DBG(dm, DBG_DFS, \"PHYDM_DFS_DOMAIN_UNKNOWN\\n\");\n\t\tgoto exit;\n\t}\n\n\tif (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) {\n\t\todm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);\n\t\todm_set_bb_reg(dm, R_0x834, MASKBYTE0, 0x06);\n\n\t\tif (dm->radar_detect_dbg_parm_en) {\n\t\t\tphydm_radar_detect_with_dbg_parm(dm);\n\t\t\tenable = 1;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (region_domain == PHYDM_DFS_DOMAIN_ETSI) {\n\t\t\todm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c17ecdf);\n\t\t\todm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);\n\t\t\todm_set_bb_reg(dm, R_0x91c, MASKDWORD, 0x0fa21a20);\n\t\t\todm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0f69204);\n\n\t\t} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {\n\t\t\todm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);\n\t\t\todm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67234);\n\n\t\t\tif (c_channel >= 52 && c_channel <= 64) {\n\t\t\t\todm_set_bb_reg(dm, R_0x918, MASKDWORD,\n\t\t\t\t\t       0x1c16ecdf);\n\t\t\t\todm_set_bb_reg(dm, R_0x91c, MASKDWORD,\n\t\t\t\t\t       0x0f141a20);\n\t\t\t} else {\n\t\t\t\todm_set_bb_reg(dm, R_0x918, MASKDWORD,\n\t\t\t\t\t       0x1c16acdf);\n\t\t\t\tif (band_width == CHANNEL_WIDTH_20)\n\t\t\t\t\todm_set_bb_reg(dm, R_0x91c, MASKDWORD,\n\t\t\t\t\t\t       0x64721a20);\n\t\t\t\telse\n\t\t\t\t\todm_set_bb_reg(dm, R_0x91c, MASKDWORD,\n\t\t\t\t\t\t       0x68721a20);\n\t\t\t}\n\n\t\t} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {\n\t\t\todm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c16acdf);\n\t\t\todm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);\n\t\t\todm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67231);\n\t\t\tif (band_width == CHANNEL_WIDTH_20)\n\t\t\t\todm_set_bb_reg(dm, R_0x91c, MASKDWORD,\n\t\t\t\t\t       0x64741a20);\n\t\t\telse\n\t\t\t\todm_set_bb_reg(dm, R_0x91c, MASKDWORD,\n\t\t\t\t\t       0x68741a20);\n\n\t\t} else {\n\t\t\t/* not supported */\n\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t  \"Unsupported dfs_region_domain:%d\\n\",\n\t\t\t\t  region_domain);\n\t\t\tgoto exit;\n\t\t}\n\n\t} else if (dm->support_ic_type &\n\t\t   (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {\n\n\t\todm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);\n\t\todm_set_bb_reg(dm, R_0x834, MASKBYTE0, 0x06);\n\n\t\t/* @8822B only, when BW = 20M, DFIR output is 40Mhz,\n\t\t * but DFS input is 80MMHz, so it need to upgrade to 80MHz\n\t\t */\n\t\tif (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {\n\t\t\tif (band_width == CHANNEL_WIDTH_20)\n\t\t\t\todm_set_bb_reg(dm, R_0x1984, BIT(26), 1);\n\t\t\telse\n\t\t\t\todm_set_bb_reg(dm, R_0x1984, BIT(26), 0);\n\t\t}\n\n\t\tif (dm->radar_detect_dbg_parm_en) {\n\t\t\tphydm_radar_detect_with_dbg_parm(dm);\n\t\t\tenable = 1;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (region_domain == PHYDM_DFS_DOMAIN_ETSI) {\n\t\t\todm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c16acdf);\n\t\t\todm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8500);\n\t\t\todm_set_bb_reg(dm, R_0x91c, MASKDWORD, 0x0fc01a1f);\n\t\t\todm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0f57204);\n\n\t\t} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {\n\t\t\todm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8500);\n\t\t\todm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67234);\n\n\t\t\tif (c_channel >= 52 && c_channel <= 64) {\n\t\t\t\todm_set_bb_reg(dm, R_0x918, MASKDWORD,\n\t\t\t\t\t       0x1c16ecdf);\n\t\t\t\todm_set_bb_reg(dm, R_0x91c, MASKDWORD,\n\t\t\t\t\t       0x0f141a1f);\n\t\t\t} else {\n\t\t\t\todm_set_bb_reg(dm, R_0x918, MASKDWORD,\n\t\t\t\t\t       0x1c166cdf);\n\t\t\t\tif (band_width == CHANNEL_WIDTH_20)\n\t\t\t\t\todm_set_bb_reg(dm, R_0x91c, MASKDWORD,\n\t\t\t\t\t\t       0x64721a1f);\n\t\t\t\telse\n\t\t\t\t\todm_set_bb_reg(dm, R_0x91c, MASKDWORD,\n\t\t\t\t\t\t       0x68721a1f);\n\t\t\t}\n\n\t\t} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {\n\t\t\todm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c176cdf);\n\t\t\todm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8400);\n\t\t\todm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe076d231);\n\t\t\tif (band_width == CHANNEL_WIDTH_20)\n\t\t\t\todm_set_bb_reg(dm, R_0x91c, MASKDWORD,\n\t\t\t\t\t       0x64901a1f);\n\t\t\telse\n\t\t\t\todm_set_bb_reg(dm, R_0x91c, MASKDWORD,\n\t\t\t\t\t       0x62901a1f);\n\n\t\t} else {\n\t\t\t/* not supported */\n\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t  \"Unsupported dfs_region_domain:%d\\n\",\n\t\t\t\t  region_domain);\n\t\t\tgoto exit;\n\t\t}\n\t\t/*RXHP low corner will extend the pulse width,\n\t\t *so we need to increase the upper bound.\n\t\t */\n\t\tif (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {\n\t\t\tif (odm_get_bb_reg(dm, 0x8d8,\n\t\t\t\t\t   BIT28 | BIT27 | BIT26) == 0) {\n\t\t\t\tshort_pw_upperbound =\n\t\t\t\t\t(u8)odm_get_bb_reg(dm, 0x91c,\n\t\t\t\t\t\t       BIT23 | BIT22 |\n\t\t\t\t\t\t       BIT21 | BIT20);\n\t\t\t\tif ((short_pw_upperbound + 4) > 15)\n\t\t\t\t\todm_set_bb_reg(dm, 0x91c,\n\t\t\t\t\t\t       BIT23 | BIT22 |\n\t\t\t\t\t\t       BIT21 | BIT20, 15);\n\t\t\t\telse\n\t\t\t\t\todm_set_bb_reg(dm, 0x91c,\n\t\t\t\t\t\t       BIT23 | BIT22 |\n\t\t\t\t\t\t       BIT21 | BIT20,\n\t\t\t\t\t\t       short_pw_upperbound + 4);\n\t\t\t}\n\t\t\t/*@if peak index -1~+1, use original NB method*/\n\t\t\todm_set_bb_reg(dm, 0x19e4, 0x003C0000, 13);\n\t\t\todm_set_bb_reg(dm, 0x924, 0x70000, 0);\n\t\t}\n\n\t\tif (dm->support_ic_type & (ODM_RTL8881A))\n\t\t\todm_set_bb_reg(dm, 0xb00, 0xc0000000, 3);\n\n\t\t/*@for 8814 new dfs mechanism setting*/\n\t\tif (dm->support_ic_type &\n\t\t    (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {\n\t\t\t/*Turn off dfs scaling factor*/\n\t\t\todm_set_bb_reg(dm, 0x19e4, 0x1fff, 0x0c00);\n\t\t\t/*NonDC peak_th = 2times DC peak_th*/\n\t\t\todm_set_bb_reg(dm, 0x19e4, 0x30000, 1);\n\t\t\t/*power for debug and auto test flow latch after ST*/\n\t\t\todm_set_bb_reg(dm, 0x9f8, 0xc0000000, 3);\n\n\t\t\t/*@low pulse width radar pattern will cause wrong drop*/\n\t\t\t/*@disable peak index should the same\n\t\t\t *during the same short pulse (new mechan)\n\t\t\t */\n\t\t\todm_set_bb_reg(dm, 0x9f4, 0x80000000, 0);\n\n\t\t\t/*@disable peak index should the same\n\t\t\t *during the same short pulse (old mechan)\n\t\t\t */\n\t\t\todm_set_bb_reg(dm, 0x924, 0x20000000, 0);\n\n\t\t\t/*@if peak index diff >=2, then drop the result*/\n\t\t\todm_set_bb_reg(dm, 0x19e4, 0xe000, 2);\n\t\t\tif (region_domain == 2) {\n\t\t\t\tif ((c_channel >= 52) && (c_channel <= 64)) {\n\t\t\t\t\t/*pulse width hist th setting*/\n\t\t\t\t\t/*th1=2*04us*/\n\t\t\t\t\todm_set_bb_reg(dm, 0x19e4,\n\t\t\t\t\t\t       0xff000000, 2);\n\t\t\t\t\t/*th2 = 3*0.4us, th3 = 4*0.4us\n\t\t\t\t\t *th4 = 7*0.4, th5 = 34*0.4\n\t\t\t\t\t */\n\t\t\t\t\todm_set_bb_reg(dm, 0x19e8,\n\t\t\t\t\t\t       MASKDWORD, 0x22070403);\n\n\t\t\t\t\t/*PRI hist th setting*/\n\t\t\t\t\t/*th1=42*32us*/\n\t\t\t\t\todm_set_bb_reg(dm, 0x19b8,\n\t\t\t\t\t\t       0x00007f80, 42);\n\t\t\t\t\t/*th2=47*32us, th3=115*32us,\n\t\t\t\t\t *th4=123*32us, th5=130*32us\n\t\t\t\t\t */\n\t\t\t\t\todm_set_bb_reg(dm, 0x19ec,\n\t\t\t\t\t\t       MASKDWORD, 0x827b732f);\n\t\t\t\t} else {\n\t\t\t\t\t/*pulse width hist th setting*/\n\t\t\t\t\t/*th1=2*04us*/\n\t\t\t\t\todm_set_bb_reg(dm, 0x19e4,\n\t\t\t\t\t\t       0xff000000, 1);\n\t\t\t\t\t/*th2 = 13*0.4us, th3 = 26*0.4us\n\t\t\t\t\t *th4 = 75*0.4us, th5 = 255*0.4us\n\t\t\t\t\t */\n\t\t\t\t\todm_set_bb_reg(dm, 0x19e8,\n\t\t\t\t\t\t       MASKDWORD, 0xff4b1a0d);\n\t\t\t\t\t/*PRI hist th setting*/\n\t\t\t\t\t/*th1=4*32us*/\n\n\t\t\t\t\todm_set_bb_reg(dm, 0x19b8,\n\t\t\t\t\t\t       0x00007f80, 4);\n\t\t\t\t\t/*th2=8*32us, th3=16*32us,\n\t\t\t\t\t *th4=32*32us, th5=128*32=4096us\n\t\t\t\t\t */\n\t\t\t\t\todm_set_bb_reg(dm, 0x19ec,\n\t\t\t\t\t\t       MASKDWORD, 0x80201008);\n\t\t\t\t}\n\t\t\t}\n\t\t\t/*@ETSI*/\n\t\t\telse if (region_domain == 3) {\n\t\t\t\t/*pulse width hist th setting*/\n\t\t\t\t/*th1=2*04us*/\n\t\t\t\todm_set_bb_reg(dm, 0x19e4, 0xff000000, 1);\n\t\t\t\todm_set_bb_reg(dm, 0x19e8,\n\t\t\t\t\t       MASKDWORD, 0x68260d06);\n\t\t\t\t/*PRI hist th setting*/\n\t\t\t\t/*th1=7*32us*/\n\t\t\t\todm_set_bb_reg(dm, 0x19b8, 0x00007f80, 7);\n\t\t\t\t/*th2=40*32us, th3=80*32us,\n\t\t\t\t *th4=110*32us, th5=157*32=5024\n\t\t\t\t */\n\t\t\t\todm_set_bb_reg(dm, 0x19ec,\n\t\t\t\t\t       MASKDWORD, 0xc06e2010);\n\t\t\t}\n\t\t\t/*@FCC*/\n\t\t\telse if (region_domain == 1) {\n\t\t\t\t/*pulse width hist th setting*/\n\t\t\t\t/*th1=2*04us*/\n\t\t\t\todm_set_bb_reg(dm, 0x19e4, 0xff000000, 2);\n\t\t\t\t/*th2 = 13*0.4us, th3 = 26*0.4us,\n\t\t\t\t *th4 = 75*0.4us, th5 = 255*0.4us\n\t\t\t\t */\n\t\t\t\todm_set_bb_reg(dm, 0x19e8,\n\t\t\t\t\t       MASKDWORD, 0xff4b1a0d);\n\n\t\t\t\t/*PRI hist th setting*/\n\t\t\t\t/*th1=4*32us*/\n\t\t\t\todm_set_bb_reg(dm, 0x19b8, 0x00007f80, 4);\n\t\t\t\t/*th2=8*32us, th3=21*32us,\n\t\t\t\t *th4=32*32us, th5=96*32=3072\n\t\t\t\t */\n\t\t\t\tif (band_width == CHANNEL_WIDTH_20)\n\t\t\t\t\todm_set_bb_reg(dm, 0x19ec,\n\t\t\t\t\t\t       MASKDWORD, 0x60282010);\n\t\t\t\telse\n\t\t\t\t\todm_set_bb_reg(dm, 0x19ec,\n\t\t\t\t\t\t       MASKDWORD, 0x60282420);\n\t\t\t} else {\n\t\t\t}\n\t\t}\n\t} else if (dm->support_ic_type &\n\t\t   ODM_IC_JGR3_SERIES) {\n\t\tif (dm->radar_detect_dbg_parm_en) {\n\t\t\tphydm_radar_detect_with_dbg_parm(dm);\n\t\t\tenable = 1;\n\t\t\tgoto exit;\n\t\t}\n\t\tif (region_domain == PHYDM_DFS_DOMAIN_ETSI) {\n\t\t\todm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd);\n\t\t\tif (dm->support_ic_type & (ODM_RTL8814B)) {\n\t\t\t\tif (dm->seg1_dfs_flag == 1)\n\t\t\t\t\todm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);\n\t\t\t}\n\t\t\todm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd);\n\t\t\todm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);\n\t\t\todm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345);\n\t\t\todm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003);\n\t\t\todm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8);\n\t\t} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {\n\t\t\todm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd);\n\t\t\tif (dm->support_ic_type & (ODM_RTL8814B)) {\n\t\t\t\tif (dm->seg1_dfs_flag == 1)\n\t\t\t\t\todm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);\n\t\t\t}\n\t\t\todm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd);\n\t\t\todm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);\n\t\t\todm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345);\n\t\t\todm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003);\n\t\t\todm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8);\n\t\t} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {\n\t\t\todm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd);\n\t\t\tif (dm->support_ic_type & (ODM_RTL8814B)) {\n\t\t\t\tif (dm->seg1_dfs_flag == 1)\n\t\t\t\t\todm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);\n\t\t\t}\n\t\t\todm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd);\n\t\t\todm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);\n\t\t\todm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345);\n\t\t\todm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003);\n\t\t\todm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8);\n\t\t} else {\n\t\t\t/* not supported */\n\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t  \"Unsupported dfs_region_domain:%d\\n\",\n\t\t\t\t  region_domain);\n\t\t\tgoto exit;\n\t\t}\n\t#if (RTL8721D_SUPPORT)\n\t} else if (dm->support_ic_type & ODM_RTL8721D) {\n\t\todm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);\n\t\t/*CCA MASK*/\n\t\todm_set_bb_reg(dm, R_0xc38, 0x07c00000, 0x06);\n\t\t/*CCA Threshold*/\n\t\todm_set_bb_reg(dm, R_0xc3c, 0x00000007, 0x0);\n\n\t\tif (dm->radar_detect_dbg_parm_en) {\n\t\t\tphydm_radar_detect_with_dbg_parm(dm);\n\t\t\tenable = 1;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (region_domain == PHYDM_DFS_DOMAIN_ETSI) {\n\t\t\todm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8);\n\t\t\todm_set_bb_reg(dm, R_0xf58, MASKDWORD, 0x354cd7dd);\n\t\t\todm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab25);\n\t\t\todm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fab98);\n\t\t\todm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc45029f);\n\n\t\t} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {\n\t\t\todm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8);\n\t\t\todm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab25);\n\t\t\todm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fb398);\n\t\t\todm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc450e9d);\n\n\t\t\tif (c_channel >= 52 && c_channel <= 64) {\n\t\t\t\todm_set_bb_reg(dm, R_0xf58, MASKDWORD,\n\t\t\t\t\t       0x354cd7fd);\n\t\t\t} else {\n\t\t\t\todm_set_bb_reg(dm, R_0xf58, MASKDWORD,\n\t\t\t\t\t       0x354cd7bd);\n\t\t\t}\n\t\t} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {\n\t\t\todm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8);\n\t\t\todm_set_bb_reg(dm, R_0xf58, MASKDWORD, 0x3558d7bd);\n\t\t\todm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab35);\n\t\t\todm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fb398);\n\t\t\todm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc444e9d);\n\t\t} else {\n\t\t\t/* not supported */\n\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t  \"Unsupported dfs_region_domain:%d\\n\",\n\t\t\t\t  region_domain);\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/*if peak index -1~+1, use original NB method*/\n\t\todm_set_bb_reg(dm, R_0xf70, 0x00070000, 0x7);\n\t\todm_set_bb_reg(dm, R_0xf74, 0x000c0000, 0);\n\n\t\t/*Turn off dfs scaling factor*/\n\t\todm_set_bb_reg(dm, R_0xf70, 0x00080000, 0x0);\n\t\t/*NonDC peak_th = 2times DC peak_th*/\n\t\todm_set_bb_reg(dm, R_0xf58, 0x00007800, 1);\n\n\t\t/*low pulse width radar pattern will cause wrong drop*/\n\t\t/*disable peak index should the same*/\n\t\t/*during the same short pulse (new mechan)*/\n\t\todm_set_bb_reg(dm, R_0xf70, 0x00100000, 0x0);\n\t\t/*if peak index diff >=2, then drop the result*/\n\t\todm_set_bb_reg(dm, R_0xf70, 0x30000000, 0x2);\n\t#endif\n\t} else {\n\t\t/*not supported IC type*/\n\t\tPHYDM_DBG(dm, DBG_DFS, \"Unsupported IC type:%d\\n\",\n\t\t\t  dm->support_ic_type);\n\t\tgoto exit;\n\t}\n\n\tenable = 1;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tdfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00007f00);\n\t\tdfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0xa50, 0x000000f0);\n\t\tdfs->peak_th = (u8)odm_get_bb_reg(dm, R_0xa48, 0x00c00000);\n\t\tdfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xa50,\n\t\t\t\t\t\t\t     0x00f00000);\n\t\tdfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xa4c,\n\t\t\t\t\t\t\t    0xf0000000);\n\t\tdfs->peak_window = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00030000);\n\t\tdfs->three_peak_opt = (u8)odm_get_bb_reg(dm, R_0xa40,\n\t\t\t\t\t\t\t 0x30000000);\n\t\tdfs->three_peak_th2 = (u8)odm_get_bb_reg(dm, R_0xa44,\n\t\t\t\t\t\t\t 0x00000007);\n\t#if (RTL8721D_SUPPORT)\n\t} else if (dm->support_ic_type & (ODM_RTL8721D)) {\n\t\tdfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xf54,\n\t\t\t\t\t\t     0x0000001f) << 2);\n\t\tdfs->st_l2h_cur += (u8)odm_get_bb_reg(dm, R_0xf58, 0xc0000000);\n\t\tdfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0xf70, 0x03c00000);\n\t\tdfs->peak_th = (u8)odm_get_bb_reg(dm, R_0xf5c, 0x00000030);\n\t\tdfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xf70,\n\t\t\t\t\t\t\t     0x00007800);\n\t\tdfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xf74,\n\t\t\t\t\t\t\t    0x0000000f);\n\t\tdfs->peak_window = (u8)odm_get_bb_reg(dm, R_0xf58, 0x18000000);\n\t\tdfs->three_peak_opt = (u8)odm_get_bb_reg(dm, R_0xf58,\n\t\t\t\t\t\t\t 0x00030000);\n\t\tdfs->three_peak_th2 = (u8)odm_get_bb_reg(dm,\n\t\t\t\t\t\t\t R_0xf58, 0x00007c00);\n\t#endif\n\t} else {\n\t\tdfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0x91c, 0x000000ff);\n\t\tdfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0x918, 0x00001f00);\n\t\tdfs->peak_th = (u8)odm_get_bb_reg(dm, R_0x918, 0x00030000);\n\t\tdfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0x920,\n\t\t\t\t\t\t\t     0x000f0000);\n\t\tdfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0x920,\n\t\t\t\t\t\t\t    0x00f00000);\n\t\tdfs->peak_window = (u8)odm_get_bb_reg(dm, R_0x920, 0x00000300);\n\t\tdfs->three_peak_opt = (u8)odm_get_bb_reg(dm, 0x924, 0x00000180);\n\t\tdfs->three_peak_th2 = (u8)odm_get_bb_reg(dm, 0x924, 0x00007000);\n\t}\n\n\t\tphydm_dfs_parameter_init(dm);\n\nexit:\n\tif (enable) {\n\t\tphydm_radar_detect_reset(dm);\n\t\tPHYDM_DBG(dm, DBG_DFS, \"on cch:%u, bw:%u\\n\", c_channel,\n\t\t\t  band_width);\n\t} else\n\t\tphydm_radar_detect_disable(dm);\n}\n\nvoid phydm_dfs_parameter_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _DFS_STATISTICS *dfs = &dm->dfs;\n\n\tu8 i;\n\tfor (i = 0; i < 5; i++) {\n\t\tdfs->pulse_flag_hist[i] = 0;\n\t\tdfs->pulse_type_hist[i] = 0;\n\t\tdfs->radar_det_mask_hist[i] = 0;\n\t\tdfs->fa_inc_hist[i] = 0;\n\t}\n\n\t/*@for dfs mode*/\n\tdfs->force_TP_mode = 0;\n\tdfs->sw_trigger_mode = 0;\n\tdfs->det_print = 0;\n\tdfs->det_print2 = 0;\n\tdfs->print_hist_rpt = 0;\n\tif (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))\n\t\tdfs->hist_cond_on = 1;\n\telse\n\t\tdfs->hist_cond_on = 0;\n\n\t/*@for dynamic dfs*/\n\tdfs->pwdb_th = 8;\n\tdfs->fa_mask_th = 30;\n\tdfs->st_l2h_min = 0x20;\n\tdfs->st_l2h_max = 0x4e;\n\tdfs->pwdb_scalar_factor = 12;\n\n\t/*@for dfs histogram*/\n\tdfs->pri_hist_th = 5;\n\tdfs->pri_sum_g1_th = 9;\n\tdfs->pri_sum_g5_th = 5;\n\tdfs->pri_sum_g1_fcc_th = 4;\t\t/*@FCC Type6*/\n\tdfs->pri_sum_g3_fcc_th = 6;\n\tdfs->pri_sum_safe_th = 50;\n\tdfs->pri_sum_safe_fcc_th = 110;\t\t/*@30 for AP*/\n\tdfs->pri_sum_type4_th = 16;\n\tdfs->pri_sum_type6_th = 12;\n\tdfs->pri_sum_g5_under_g1_th = 4;\n\tdfs->pri_pw_diff_th = 4;\n\tdfs->pri_pw_diff_fcc_th = 8;\n\tdfs->pri_pw_diff_fcc_idle_th = 2;\n\tdfs->pri_pw_diff_w53_th = 10;\n\tdfs->pw_std_th = 7;\t\t\t/*@FCC Type4*/\n\tdfs->pw_std_idle_th = 10;\n\tdfs->pri_std_th = 6;\t\t\t/*@FCC Type3,4,6*/\n\tdfs->pri_std_idle_th = 10;\n\tdfs->pri_type1_upp_fcc_th = 110;\n\tdfs->pri_type1_low_fcc_th = 50;\n\tdfs->pri_type1_cen_fcc_th = 70;\n\tdfs->pw_g0_th = 8;\n\tdfs->pw_long_lower_th = 6;\t\t/*@7->6*/\n\tdfs->pri_long_upper_th = 30;\n\tdfs->pw_long_lower_20m_th = 7;\t\t/*@7 for AP*/\n\tdfs->pw_long_sum_upper_th = 60;\n\tdfs->type4_pw_max_cnt = 7;\n\tdfs->type4_safe_pri_sum_th = 5;\n}\n\nvoid phydm_dfs_dynamic_setting(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _DFS_STATISTICS *dfs = &dm->dfs;\n\n\tu8 peak_th_cur = 0, short_pulse_cnt_th_cur = 0;\n\tu8 long_pulse_cnt_th_cur = 0, three_peak_opt_cur = 0;\n\tu8 three_peak_th2_cur = 0;\n\tu8 peak_window_cur = 0;\n\tu8 region_domain = dm->dfs_region_domain;\n\tu8 c_channel = *dm->channel;\n\n\tif (dm->rx_tp + dm->tx_tp <= 2) {\n\t\tdfs->idle_mode = 1;\n\t\tif (dfs->force_TP_mode)\n\t\t\tdfs->idle_mode = 0;\n\t} else {\n\t\tdfs->idle_mode = 0;\n\t}\n\n\tif (dfs->idle_mode == 1) { /*@idle (no traffic)*/\n\t\tpeak_th_cur = 3;\n\t\tshort_pulse_cnt_th_cur = 6;\n\t\tlong_pulse_cnt_th_cur = 9;\n\t\tpeak_window_cur = 2;\n\t\tthree_peak_opt_cur = 0;\n\t\tthree_peak_th2_cur = 2;\n\t\tif (region_domain == PHYDM_DFS_DOMAIN_MKK) {\n\t\t\tif (c_channel >= 52 && c_channel <= 64) {\n\t\t\t\tshort_pulse_cnt_th_cur = 14;\n\t\t\t\tlong_pulse_cnt_th_cur = 15;\n\t\t\t\tthree_peak_th2_cur = 0;\n\t\t\t} else {\n\t\t\t\tshort_pulse_cnt_th_cur = 6;\n\t\t\t\tthree_peak_th2_cur = 0;\n\t\t\t\tlong_pulse_cnt_th_cur = 10;\n\t\t\t}\n\t\t} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {\n\t\t\tthree_peak_th2_cur = 0;\n\t\t} else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {\n\t\t\tlong_pulse_cnt_th_cur = 15;\n\t\t\tif (phydm_dfs_is_meteorology_channel(dm)) {\n\t\t\t/*need to add check cac end condition*/\n\t\t\t\tpeak_th_cur = 2;\n\t\t\t\tthree_peak_opt_cur = 0;\n\t\t\t\tthree_peak_th2_cur = 0;\n\t\t\t\tshort_pulse_cnt_th_cur = 7;\n\t\t\t} else {\n\t\t\t\tthree_peak_opt_cur = 0;\n\t\t\t\tthree_peak_th2_cur = 0;\n\t\t\t\tshort_pulse_cnt_th_cur = 7;\n\t\t\t}\n\t\t} else /*@default: FCC*/\n\t\t\tthree_peak_th2_cur = 0;\n\n\t} else { /*@in service (with TP)*/\n\t\tpeak_th_cur = 2;\n\t\tshort_pulse_cnt_th_cur = 6;\n\t\tlong_pulse_cnt_th_cur = 7;\n\t\tpeak_window_cur = 2;\n\t\tthree_peak_opt_cur = 0;\n\t\tthree_peak_th2_cur = 2;\n\t\tif (region_domain == PHYDM_DFS_DOMAIN_MKK) {\n\t\t\tif (c_channel >= 52 && c_channel <= 64) {\n\t\t\t\tlong_pulse_cnt_th_cur = 15;\n\t\t\t\t/*@for high duty cycle*/\n\t\t\t\tshort_pulse_cnt_th_cur = 5;\n\t\t\t\tthree_peak_th2_cur = 0;\n\t\t\t} else {\n\t\t\t\tthree_peak_opt_cur = 0;\n\t\t\t\tthree_peak_th2_cur = 0;\n\t\t\t\tlong_pulse_cnt_th_cur = 8;\n\t\t\t}\n\t\t} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {\n\t\t\tlong_pulse_cnt_th_cur = 5;\t/*for 80M FCC*/\n\t\t\tshort_pulse_cnt_th_cur = 5;\t/*for 80M FCC*/\n\t\t} else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {\n\t\t\tlong_pulse_cnt_th_cur = 15;\n\t\t\tshort_pulse_cnt_th_cur = 5;\n\t\t\tthree_peak_opt_cur = 0;\n\t\t}\n\t}\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tif (dfs->peak_th != peak_th_cur)\n\t\t\todm_set_bb_reg(dm, R_0xa48, 0x00c00000, peak_th_cur);\n\t\tif (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur)\n\t\t\todm_set_bb_reg(dm, R_0xa50, 0x00f00000,\n\t\t\t\t       short_pulse_cnt_th_cur);\n\t\tif (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur)\n\t\t\todm_set_bb_reg(dm, R_0xa4c, 0xf0000000,\n\t\t\t\t       long_pulse_cnt_th_cur);\n\t\tif (dfs->peak_window != peak_window_cur)\n\t\t\todm_set_bb_reg(dm, R_0xa40, 0x00030000,\n\t\t\t\t       peak_window_cur);\n\t\tif (dfs->three_peak_opt != three_peak_opt_cur)\n\t\t\todm_set_bb_reg(dm, R_0xa40, 0x30000000,\n\t\t\t\t       three_peak_opt_cur);\n\t\tif (dfs->three_peak_th2 != three_peak_th2_cur)\n\t\t\todm_set_bb_reg(dm, R_0xa44, 0x00000007,\n\t\t\t\t       three_peak_th2_cur);\n\t#if (RTL8721D_SUPPORT)\n\t} else if (dm->support_ic_type & (ODM_RTL8721D)) {\n\t\tif (dfs->peak_th != peak_th_cur)\n\t\t\todm_set_bb_reg(dm, R_0xf5c, 0x00000030, peak_th_cur);\n\t\tif (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur)\n\t\t\todm_set_bb_reg(dm, R_0xf70, 0x00007800,\n\t\t\t\t       short_pulse_cnt_th_cur);\n\t\tif (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur)\n\t\t\todm_set_bb_reg(dm, R_0xf74, 0x0000000f,\n\t\t\t\t       long_pulse_cnt_th_cur);\n\t\tif (dfs->peak_window != peak_window_cur)\n\t\t\todm_set_bb_reg(dm, R_0xf58, 0x18000000,\n\t\t\t\t       peak_window_cur);\n\t\tif (dfs->three_peak_opt != three_peak_opt_cur)\n\t\t\todm_set_bb_reg(dm, R_0xf58, 0x00030000,\n\t\t\t\t       three_peak_opt_cur);\n\t\tif (dfs->three_peak_th2 != three_peak_th2_cur)\n\t\t\todm_set_bb_reg(dm, R_0xf58, 0x00007c00,\n\t\t\t\t       three_peak_th2_cur);\n\t#endif\n\t} else {\n\t\tif (dfs->peak_th != peak_th_cur)\n\t\t\todm_set_bb_reg(dm, R_0x918, 0x00030000, peak_th_cur);\n\t\tif (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur)\n\t\t\todm_set_bb_reg(dm, R_0x920, 0x000f0000,\n\t\t\t\t       short_pulse_cnt_th_cur);\n\t\tif (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur)\n\t\t\todm_set_bb_reg(dm, R_0x920, 0x00f00000,\n\t\t\t\t       long_pulse_cnt_th_cur);\n\t\tif (dfs->peak_window != peak_window_cur)\n\t\t\todm_set_bb_reg(dm, R_0x920, 0x00000300,\n\t\t\t\t       peak_window_cur);\n\t\tif (dfs->three_peak_opt != three_peak_opt_cur)\n\t\t\todm_set_bb_reg(dm, R_0x924, 0x00000180,\n\t\t\t\t       three_peak_opt_cur);\n\t\tif (dfs->three_peak_th2 != three_peak_th2_cur)\n\t\t\todm_set_bb_reg(dm, R_0x924, 0x00007000,\n\t\t\t\t       three_peak_th2_cur);\n\t}\n\n\tdfs->peak_th = peak_th_cur;\n\tdfs->short_pulse_cnt_th = short_pulse_cnt_th_cur;\n\tdfs->long_pulse_cnt_th = long_pulse_cnt_th_cur;\n\tdfs->peak_window = peak_window_cur;\n\tdfs->three_peak_opt = three_peak_opt_cur;\n\tdfs->three_peak_th2 = three_peak_th2_cur;\n}\n\nboolean\nphydm_radar_detect_dm_check(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _DFS_STATISTICS *dfs = &dm->dfs;\n\tu8 region_domain = dm->dfs_region_domain, index = 0;\n\n\tu16 i = 0, j = 0, k = 0, fa_count_cur = 0, fa_count_inc = 0;\n\tu16 total_fa_in_hist = 0, pre_post_now_acc_fa_in_hist = 0;\n\tu16 max_fa_in_hist = 0, vht_crc_ok_cnt_cur = 0;\n\tu16 vht_crc_ok_cnt_inc = 0, ht_crc_ok_cnt_cur = 0;\n\tu16 ht_crc_ok_cnt_inc = 0, leg_crc_ok_cnt_cur = 0;\n\tu16 leg_crc_ok_cnt_inc = 0;\n\tu16 total_crc_ok_cnt_inc = 0, short_pulse_cnt_cur = 0;\n\tu16 short_pulse_cnt_inc = 0, long_pulse_cnt_cur = 0;\n\tu16 long_pulse_cnt_inc = 0, total_pulse_count_inc = 0;\n\tu32 regf98_value = 0, reg918_value = 0, reg91c_value = 0;\n\tu32 reg920_value = 0, reg924_value = 0, radar_rpt_reg_value = 0;\n\tu32 regf54_value = 0, regf58_value = 0, regf5c_value = 0;\n\tu32 regdf4_value = 0, regf70_value = 0, regf74_value = 0;\n\tu32 rega40_value = 0, rega44_value = 0, rega48_value = 0;\n\tu32 rega4c_value = 0, rega50_value = 0, rega54_value = 0;\n\t#if (RTL8721D_SUPPORT)\n\tu32 reg908_value = 0, regdf4_value = 0;\n\tu32 regf54_value = 0, regf58_value = 0, regf5c_value = 0;\n\tu32 regf70_value = 0, regf74_value = 0;\n\t#endif\n\tboolean tri_short_pulse = 0, tri_long_pulse = 0, radar_type = 0;\n\tboolean fault_flag_det = 0, fault_flag_psd = 0, fa_flag = 0;\n\tboolean radar_detected = 0;\n\tu8 st_l2h_new = 0, fa_mask_th = 0, sum = 0;\n\tu8 c_channel = *dm->channel;\n\n\t/*@Get FA count during past 100ms, R_0xf48 for AC series*/\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tfa_count_cur = (u16)odm_get_bb_reg(dm, R_0x2d00, MASKLWORD);\n\t#if (RTL8721D_SUPPORT)\n\telse if (dm->support_ic_type & (ODM_RTL8721D)) {\n\t\tfa_count_cur = (u16)odm_get_bb_reg(dm,\n\t\t\t\t\t\t   ODM_REG_OFDM_FA_TYPE2_11N,\n\t\t\t\t\t\t   MASKHWORD);\n\t\tfa_count_cur += (u16)odm_get_bb_reg(dm,\n\t\t\t\t\t\t    ODM_REG_OFDM_FA_TYPE3_11N,\n\t\t\t\t\t\t    MASKLWORD);\n\t\tfa_count_cur += (u16)odm_get_bb_reg(dm,\n\t\t\t\t\t\t    ODM_REG_OFDM_FA_TYPE3_11N,\n\t\t\t\t\t\t    MASKHWORD);\n\t\tfa_count_cur += (u16)odm_get_bb_reg(dm,\n\t\t\t\t\t\t    ODM_REG_OFDM_FA_TYPE4_11N,\n\t\t\t\t\t\t    MASKLWORD);\n\t\tfa_count_cur += (u16)odm_get_bb_reg(dm,\n\t\t\t\t\t\t    ODM_REG_OFDM_FA_TYPE1_11N,\n\t\t\t\t\t\t    MASKLWORD);\n\t\tfa_count_cur += (u16)odm_get_bb_reg(dm,\n\t\t\t\t\t\t    ODM_REG_OFDM_FA_TYPE1_11N,\n\t\t\t\t\t\t    MASKHWORD);\n\t}\n\t#endif\n\telse\n\t\tfa_count_cur = (u16)odm_get_bb_reg(dm, R_0xf48, 0x0000ffff);\n\n\tif (dfs->fa_count_pre == 0)\n\t\tfa_count_inc = 0;\n\telse if (fa_count_cur >= dfs->fa_count_pre)\n\t\tfa_count_inc = fa_count_cur - dfs->fa_count_pre;\n\telse\n\t\tfa_count_inc = fa_count_cur;\n\tdfs->fa_count_pre = fa_count_cur;\n\n\tdfs->fa_inc_hist[dfs->mask_idx] = fa_count_inc;\n\n\tfor (i = 0; i < 5; i++) {\n\t\ttotal_fa_in_hist = total_fa_in_hist + dfs->fa_inc_hist[i];\n\t\tif (dfs->fa_inc_hist[i] > max_fa_in_hist)\n\t\t\tmax_fa_in_hist = dfs->fa_inc_hist[i];\n\t}\n\tif (dfs->mask_idx >= 2)\n\t\tindex = dfs->mask_idx - 2;\n\telse\n\t\tindex = 5 + dfs->mask_idx - 2;\n\tif (index == 0) {\n\t\tpre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] +\n\t\t\t\t\t      dfs->fa_inc_hist[index + 1] +\n\t\t\t\t\t      dfs->fa_inc_hist[4];\n\t} else if (index == 4) {\n\t\tpre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] +\n\t\t\t\t\t      dfs->fa_inc_hist[0] +\n\t\t\t\t\t      dfs->fa_inc_hist[index - 1];\n\t} else {\n\t\tpre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] +\n\t\t\t\t\t      dfs->fa_inc_hist[index + 1] +\n\t\t\t\t\t      dfs->fa_inc_hist[index - 1];\n\t}\n\n\t/*@Get VHT CRC32 ok count during past 100ms*/\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tvht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0x2c0c, 0xffff);\n\t#if (RTL8721D_SUPPORT)\n\telse if (dm->support_ic_type & ODM_RTL8721D)\n\t\tvht_crc_ok_cnt_cur = 0;\n\t#endif\n\telse\n\t\tvht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0xf0c,\n\t\t\t\t\t\t\t 0x00003fff);\n\n\tif (vht_crc_ok_cnt_cur >= dfs->vht_crc_ok_cnt_pre) {\n\t\tvht_crc_ok_cnt_inc = vht_crc_ok_cnt_cur -\n\t\t\t\t     dfs->vht_crc_ok_cnt_pre;\n\t} else {\n\t\tvht_crc_ok_cnt_inc = vht_crc_ok_cnt_cur;\n\t}\n\tdfs->vht_crc_ok_cnt_pre = vht_crc_ok_cnt_cur;\n\n\t/*@Get HT CRC32 ok count during past 100ms*/\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0x2c10, 0xffff);\n\t#if (RTL8721D_SUPPORT)\n\telse if (dm->support_ic_type & (ODM_RTL8721D))\n\t\tht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0xf90, MASKLWORD);\n\t#endif\n\telse\n\t\tht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0xf10,\n\t\t\t\t\t\t\t0x00003fff);\n\n\tif (ht_crc_ok_cnt_cur >= dfs->ht_crc_ok_cnt_pre)\n\t\tht_crc_ok_cnt_inc = ht_crc_ok_cnt_cur - dfs->ht_crc_ok_cnt_pre;\n\telse\n\t\tht_crc_ok_cnt_inc = ht_crc_ok_cnt_cur;\n\tdfs->ht_crc_ok_cnt_pre = ht_crc_ok_cnt_cur;\n\n\t/*@Get Legacy CRC32 ok count during past 100ms*/\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tleg_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0x2c14, 0xffff);\n\t#if (RTL8721D_SUPPORT)\n\telse if (dm->support_ic_type & ODM_RTL8721D)\n\t\tleg_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm,\n\t\t\t\t\t\t\t R_0xf94, MASKLWORD);\n\t#endif\n\telse\n\t\tleg_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0xf14,\n\t\t\t\t\t\t\t 0x00003fff);\n\n\tif (leg_crc_ok_cnt_cur >= dfs->leg_crc_ok_cnt_pre)\n\t\tleg_crc_ok_cnt_inc = leg_crc_ok_cnt_cur - dfs->leg_crc_ok_cnt_pre;\n\telse\n\t\tleg_crc_ok_cnt_inc = leg_crc_ok_cnt_cur;\n\tdfs->leg_crc_ok_cnt_pre = leg_crc_ok_cnt_cur;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tif (vht_crc_ok_cnt_cur == 0xffff ||\n\t\t\tht_crc_ok_cnt_cur == 0xffff ||\n\t\t\tleg_crc_ok_cnt_cur == 0xffff) {\n\t\t\tphydm_reset_bb_hw_cnt(dm);\n\t\t}\n\t#if (RTL8721D_SUPPORT)\n\t} else if (dm->support_ic_type & (ODM_RTL8721D)) {\n\t\tif (ht_crc_ok_cnt_cur == 0xffff ||\n\t\t    leg_crc_ok_cnt_cur == 0xffff) {\n\t\t\todm_set_bb_reg(dm, R_0xf14, BIT(16), 1);\n\t\t\todm_set_bb_reg(dm, R_0xf14, BIT(16), 0);\n\t\t}\n\t#endif\n\t} else {\n\t\tif (vht_crc_ok_cnt_cur == 0x3fff ||\n\t\t    ht_crc_ok_cnt_cur == 0x3fff ||\n\t\t    leg_crc_ok_cnt_cur == 0x3fff) {\n\t\t\tphydm_reset_bb_hw_cnt(dm);\n\t\t}\n\t}\n\n\ttotal_crc_ok_cnt_inc = vht_crc_ok_cnt_inc +\n\t\t\t       ht_crc_ok_cnt_inc +\n\t\t\t       leg_crc_ok_cnt_inc;\n\n\tif (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |\n\t\t\t\t   ODM_RTL8197G)) {\n\t\t/* if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x3b0)) {\n\t\t *\todm_set_bb_reg(dm, 0x1e28, 0x03c00000, 8);\n\t\t *\tdbgport2dbc_value = phydm_get_bb_dbg_port_val(dm);\n\t\t *\tphydm_release_bb_dbg_port(dm); }\n\t\t */\n\t\tradar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e00, 0xffffffff);\n\t\tshort_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x000ff800)\n\t\t\t\t\t    >> 11);\n\t\tlong_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x0fc00000)\n\t\t\t\t\t    >> 22);\n\t#if (RTL8721D_SUPPORT)\n\t} else if (dm->support_ic_type & (ODM_RTL8721D)) {\n\t\treg908_value = (u32)odm_get_bb_reg(dm, R_0x908, MASKDWORD);\n\t\todm_set_bb_reg(dm, R_0x908, MASKDWORD, 0x254);\n\t\tregdf4_value = odm_get_bb_reg(dm, R_0xdf4, MASKDWORD);\n\t\tshort_pulse_cnt_cur = (u16)((regdf4_value & 0x000ff000) >> 12);\n\t\tlong_pulse_cnt_cur = (u16)((regdf4_value & 0x0fc00000) >> 22);\n\n\t\ttri_short_pulse = (regdf4_value & BIT(20)) ? 1 : 0;\n\t\ttri_long_pulse = (regdf4_value & BIT(28)) ? 1 : 0;\n\t\tif (tri_short_pulse || tri_long_pulse) {\n\t\t\todm_set_bb_reg(dm, R_0xf58, BIT(29), 0);\n\t\t\todm_set_bb_reg(dm, R_0xf58, BIT(29), 1);\n\t\t}\n\t#endif\n\t} else if (dm->support_ic_type & (ODM_RTL8814B)) {\n\t\tif (dm->seg1_dfs_flag == 1)\n\t\t\tradar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e20,\n\t\t\t\t\t\t\t     0xffffffff);\n\t\telse\n\t\t\tradar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e00,\n\t\t\t\t\t\t\t     0xffffffff);\n\t\tshort_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x000ff800)\n\t\t\t\t\t    >> 11);\n\t\tlong_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x0fc00000)\n\t\t\t\t\t    >> 22);\n\t} else {\n\t\tregf98_value = odm_get_bb_reg(dm, R_0xf98, 0xffffffff);\n\t\tshort_pulse_cnt_cur = (u16)(regf98_value & 0x000000ff);\n\t\tlong_pulse_cnt_cur = (u16)((regf98_value & 0x0000ff00) >> 8);\n\t}\n\n\t/*@Get short pulse count, need carefully handle the counter overflow*/\n\n\tif (short_pulse_cnt_cur >= dfs->short_pulse_cnt_pre) {\n\t\tshort_pulse_cnt_inc = short_pulse_cnt_cur -\n\t\t\t\t      dfs->short_pulse_cnt_pre;\n\t} else {\n\t\tshort_pulse_cnt_inc = short_pulse_cnt_cur;\n\t}\n\tdfs->short_pulse_cnt_pre = short_pulse_cnt_cur;\n\n\t/*@Get long pulse count, need carefully handle the counter overflow*/\n\n\tif (long_pulse_cnt_cur >= dfs->long_pulse_cnt_pre) {\n\t\tlong_pulse_cnt_inc = long_pulse_cnt_cur -\n\t\t\t\t     dfs->long_pulse_cnt_pre;\n\t} else {\n\t\tlong_pulse_cnt_inc = long_pulse_cnt_cur;\n\t}\n\tdfs->long_pulse_cnt_pre = long_pulse_cnt_cur;\n\n\ttotal_pulse_count_inc = short_pulse_cnt_inc + long_pulse_cnt_inc;\n\n\tif (dfs->det_print) {\n\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t  \"===============================================\\n\");\n\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t  \"Total_CRC_OK_cnt_inc[%d] VHT_CRC_ok_cnt_inc[%d] HT_CRC_ok_cnt_inc[%d] LEG_CRC_ok_cnt_inc[%d] FA_count_inc[%d]\\n\",\n\t\t\t  total_crc_ok_cnt_inc, vht_crc_ok_cnt_inc,\n\t\t\t  ht_crc_ok_cnt_inc, leg_crc_ok_cnt_inc, fa_count_inc);\n\t\tif (dm->support_ic_type & (ODM_RTL8721D)) {\n\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t  \"Init_Gain[%x] st_l2h_cur[%x] 0xdf4[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\\n\",\n\t\t\t\t  dfs->igi_cur, dfs->st_l2h_cur, regdf4_value,\n\t\t\t\t  short_pulse_cnt_inc, long_pulse_cnt_inc);\n\t\t\tregf54_value = odm_get_bb_reg(dm, R_0xf54, MASKDWORD);\n\t\t\tregf58_value = odm_get_bb_reg(dm, R_0xf58, MASKDWORD);\n\t\t\tregf5c_value = odm_get_bb_reg(dm, R_0xf5c, MASKDWORD);\n\t\t\tregf70_value = odm_get_bb_reg(dm, R_0xf70, MASKDWORD);\n\t\t\tregf74_value = odm_get_bb_reg(dm, R_0xf74, MASKDWORD);\n\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t  \"0xf54[%08x] 0xf58[%08x] 0xf5c[%08x] 0xf70[%08x] 0xf74[%08x]\\n\",\n\t\t\t\t  regf54_value, regf58_value, regf5c_value,\n\t\t\t\t  regf70_value, regf74_value);\n\t\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t  \"Init_Gain[%x] st_l2h_cur[%x] 0x2dbc[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\\n\",\n\t\t\t\t  dfs->igi_cur, dfs->st_l2h_cur,\n\t\t\t\t  radar_rpt_reg_value, short_pulse_cnt_inc,\n\t\t\t\t  long_pulse_cnt_inc);\n\t\t\trega40_value = odm_get_bb_reg(dm, R_0xa40, MASKDWORD);\n\t\t\trega44_value = odm_get_bb_reg(dm, R_0xa44, MASKDWORD);\n\t\t\trega48_value = odm_get_bb_reg(dm, R_0xa48, MASKDWORD);\n\t\t\trega4c_value = odm_get_bb_reg(dm, R_0xa4c, MASKDWORD);\n\t\t\trega50_value = odm_get_bb_reg(dm, R_0xa50, MASKDWORD);\n\t\t\trega54_value = odm_get_bb_reg(dm, R_0xa54, MASKDWORD);\n\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t  \"0xa40[%08x] 0xa44[%08x] 0xa48[%08x] 0xa4c[%08x] 0xa50[%08x] 0xa54[%08x]\\n\",\n\t\t\t\t  rega40_value, rega44_value, rega48_value,\n\t\t\t\t  rega4c_value, rega50_value, rega54_value);\n\t\t} else {\n\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t  \"Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\\n\",\n\t\t\t\t  dfs->igi_cur, dfs->st_l2h_cur, regf98_value,\n\t\t\t\t  short_pulse_cnt_inc, long_pulse_cnt_inc);\n\t\t\treg918_value = odm_get_bb_reg(dm, R_0x918,\n\t\t\t\t\t\t      0xffffffff);\n\t\t\treg91c_value = odm_get_bb_reg(dm, R_0x91c,\n\t\t\t\t\t\t      0xffffffff);\n\t\t\treg920_value = odm_get_bb_reg(dm, R_0x920,\n\t\t\t\t\t\t      0xffffffff);\n\t\t\treg924_value = odm_get_bb_reg(dm, R_0x924,\n\t\t\t\t\t\t      0xffffffff);\n\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t  \"0x918[%08x] 0x91c[%08x] 0x920[%08x] 0x924[%08x]\\n\",\n\t\t\t\t  reg918_value, reg91c_value,\n\t\t\t\t  reg920_value, reg924_value);\n\t\t}\n\t\tPHYDM_DBG(dm, DBG_DFS, \"Throughput: %dMbps\\n\",\n\t\t\t  (dm->rx_tp + dm->tx_tp));\n\n\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t  \"dfs_regdomain = %d, dbg_mode = %d, idle_mode = %d, print_hist_rpt = %d, hist_cond_on = %d\\n\",\n\t\t\t  region_domain, dfs->dbg_mode,\n\t\t\t  dfs->idle_mode, dfs->print_hist_rpt,\n\t\t\t  dfs->hist_cond_on);\n\t}\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\ttri_short_pulse = (radar_rpt_reg_value & BIT(20)) ? 1 : 0;\n\t\ttri_long_pulse = (radar_rpt_reg_value & BIT(28)) ? 1 : 0;\n\t} else {\n\t\ttri_short_pulse = (regf98_value & BIT(17)) ? 1 : 0;\n\t\ttri_long_pulse = (regf98_value & BIT(19)) ? 1 : 0;\n\t}\n\n\tif (tri_short_pulse) {\n\t\tphydm_radar_detect_reset(dm);\n\t}\n\tif (tri_long_pulse) {\n\t\tphydm_radar_detect_reset(dm);\n\t\tif (region_domain == PHYDM_DFS_DOMAIN_MKK) {\n\t\t\tif (c_channel >= 52 && c_channel <= 64) {\n\t\t\t\ttri_long_pulse = 0;\n\t\t\t}\n\t\t}\n\t\tif (region_domain == PHYDM_DFS_DOMAIN_ETSI) {\n\t\t\ttri_long_pulse = 0;\n\t\t}\n\t}\n\n\tst_l2h_new = dfs->st_l2h_cur;\n\tdfs->pulse_flag_hist[dfs->mask_idx] = tri_short_pulse | tri_long_pulse;\n\tdfs->pulse_type_hist[dfs->mask_idx] = (tri_long_pulse) ? 1 : 0;\n\n\t/* PSD(not ready) */\n\n\tfault_flag_det = 0;\n\tfault_flag_psd = 0;\n\tfa_flag = 0;\n\tif (region_domain == PHYDM_DFS_DOMAIN_ETSI) {\n\t\tfa_mask_th = dfs->fa_mask_th + 20;\n\t} else {\n\t\tfa_mask_th = dfs->fa_mask_th;\n\t}\n\tif (max_fa_in_hist >= fa_mask_th ||\n\t    total_fa_in_hist >= fa_mask_th ||\n\t    pre_post_now_acc_fa_in_hist >= fa_mask_th ||\n\t    dfs->igi_cur >= 0x30) {\n\t\tst_l2h_new = dfs->st_l2h_max;\n\t\tdfs->radar_det_mask_hist[index] = 1;\n\t\tif (dfs->pulse_flag_hist[index] == 1) {\n\t\t\tdfs->pulse_flag_hist[index] = 0;\n\t\t\tif (dfs->det_print2) {\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t  \"Radar is masked : FA mask\\n\");\n\t\t\t}\n\t\t}\n\t\tfa_flag = 1;\n\t} else {\n\t\tdfs->radar_det_mask_hist[index] = 0;\n\t}\n\n\tif (dfs->det_print) {\n\t\tPHYDM_DBG(dm, DBG_DFS, \"mask_idx: %d\\n\", dfs->mask_idx);\n\t\tPHYDM_DBG(dm, DBG_DFS, \"radar_det_mask_hist: \");\n\t\tfor (i = 0; i < 5; i++)\n\t\t\tPHYDM_DBG(dm, DBG_DFS, \"%d \",\n\t\t\t\t  dfs->radar_det_mask_hist[i]);\n\t\tPHYDM_DBG(dm, DBG_DFS, \"pulse_flag_hist: \");\n\t\tfor (i = 0; i < 5; i++)\n\t\t\tPHYDM_DBG(dm, DBG_DFS, \"%d \", dfs->pulse_flag_hist[i]);\n\t\tPHYDM_DBG(dm, DBG_DFS, \"fa_inc_hist: \");\n\t\tfor (i = 0; i < 5; i++)\n\t\t\tPHYDM_DBG(dm, DBG_DFS, \"%d \", dfs->fa_inc_hist[i]);\n\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t  \"\\nfa_mask_th: %d max_fa_in_hist: %d total_fa_in_hist: %d pre_post_now_acc_fa_in_hist: %d \",\n\t\t\t  fa_mask_th, max_fa_in_hist, total_fa_in_hist,\n\t\t\t  pre_post_now_acc_fa_in_hist);\n\t}\n\n\tsum = 0;\n\tfor (k = 0; k < 5; k++) {\n\t\tif (dfs->radar_det_mask_hist[k] == 1)\n\t\t\tsum++;\n\t}\n\n\tif (dfs->mask_hist_checked <= 5)\n\t\tdfs->mask_hist_checked++;\n\n\tif (dfs->mask_hist_checked >= 5 && dfs->pulse_flag_hist[index]) {\n\t\tif (sum <= 2) {\n\t\t\tif (dfs->hist_cond_on) {\n\t\t\t\t/*return the value from hist_radar_detected*/\n\t\t\t\tradar_detected = phydm_dfs_hist_log(dm, index);\n\t\t\t} else {\n\t\t\t\tif (dfs->pulse_type_hist[index] == 0)\n\t\t\t\t\tdfs->radar_type = 0;\n\t\t\t\telse if (dfs->pulse_type_hist[index] == 1)\n\t\t\t\t\tdfs->radar_type = 1;\n\t\t\t\tradar_detected = 1;\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t  \"Detected type %d radar signal!\\n\",\n\t\t\t\t\t  dfs->radar_type);\n\t\t\t}\n\t\t} else {\n\t\t\tfault_flag_det = 1;\n\t\t\tif (dfs->det_print2) {\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t  \"Radar is masked : mask_hist large than thd\\n\");\n\t\t\t}\n\t\t}\n\t}\n\n\tdfs->mask_idx++;\n\tif (dfs->mask_idx == 5)\n\t\tdfs->mask_idx = 0;\n\n\tif (fault_flag_det == 0 && fault_flag_psd == 0 && fa_flag == 0) {\n\t\tif (dfs->igi_cur < 0x30) {\n\t\t\tst_l2h_new = dfs->st_l2h_min;\n\t\t}\n\t}\n\n\tif (st_l2h_new != dfs->st_l2h_cur) {\n\t\tif (st_l2h_new < dfs->st_l2h_min) {\n\t\t\tdfs->st_l2h_cur = dfs->st_l2h_min;\n\t\t} else if (st_l2h_new > dfs->st_l2h_max)\n\t\t\tdfs->st_l2h_cur = dfs->st_l2h_max;\n\t\telse\n\t\t\tdfs->st_l2h_cur = st_l2h_new;\n\t\t/*odm_set_bb_reg(dm, R_0x91c, 0xff, dfs->st_l2h_cur);*/\n\n\t\tdfs->pwdb_th_cur = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur)\n\t\t\t\t    / 2 + dfs->pwdb_scalar_factor;\n\n\t\t/*@limit the pwdb value to absolute lower bound 8*/\n\t\tdfs->pwdb_th_cur = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th);\n\n\t\t/*@limit the pwdb value to absolute upper bound 0x1f*/\n\t\tdfs->pwdb_th_cur = MIN_2(dfs->pwdb_th_cur, 0x1f);\n\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\t\todm_set_bb_reg(dm, R_0xa50, 0x000000f0,\n\t\t\t\t       dfs->pwdb_th_cur);\n\t\t#if (RTL8721D_SUPPORT)\n\t\telse if (dm->support_ic_type & ODM_RTL8721D) {\n\t\t\todm_set_bb_reg(dm, R_0xf54, 0x0000001f,\n\t\t\t\t       ((dfs->st_l2h_cur & 0x0000007c) >> 2));\n\t\t\todm_set_bb_reg(dm, R_0xf58, 0xc0000000,\n\t\t\t\t       (dfs->st_l2h_cur & 0x00000003));\n\t\t\todm_set_bb_reg(dm, R_0xf70, 0x03c00000,\n\t\t\t\t       dfs->pwdb_th_cur);\n\t\t}\n\t\t#endif\n\t\telse\n\t\t\todm_set_bb_reg(dm, R_0x918, 0x00001f00,\n\t\t\t\t       dfs->pwdb_th_cur);\n\t}\n\n\tif (dfs->det_print) {\n\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t  \"fault_flag_det[%d], fault_flag_psd[%d], DFS_detected [%d]\\n\",\n\t\t\t  fault_flag_det, fault_flag_psd, radar_detected);\n\t}\n\t#if (RTL8721D_SUPPORT)\n\tif (dm->support_ic_type & (ODM_RTL8721D))\n\t\todm_set_bb_reg(dm, R_0x908, MASKDWORD, reg908_value);\n\t#endif\n\n\treturn radar_detected;\n}\n\nvoid phydm_dfs_histogram_radar_distinguish(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _DFS_STATISTICS *dfs = &dm->dfs;\n\tu8 region_domain = dm->dfs_region_domain;\n\tu8 c_channel = *dm->channel;\n\tu8 band_width = *dm->band_width;\n\n\tu8 dfs_pw_thd1 = 0, dfs_pw_thd2 = 0, dfs_pw_thd3 = 0;\n\tu8 dfs_pw_thd4 = 0, dfs_pw_thd5 = 0;\n\tu8 dfs_pri_thd1 = 0, dfs_pri_thd2 = 0, dfs_pri_thd3 = 0;\n\tu8 dfs_pri_thd4 = 0, dfs_pri_thd5 = 0;\n\tu8 pri_th = 0, i = 0;\n\tu8 max_pri_idx = 0, max_pw_idx = 0, max_pri_cnt_th = 0;\n\tu8 max_pri_cnt_fcc_g1_th = 0, max_pri_cnt_fcc_g3_th = 0;\n\tu8 safe_pri_pw_diff_th = 0, safe_pri_pw_diff_fcc_th = 0;\n\tu8 safe_pri_pw_diff_w53_th = 0, safe_pri_pw_diff_fcc_idle_th = 0;\n\tu16 j = 0;\n\tu32 dfs_hist1_peak_index = 0, dfs_hist2_peak_index = 0;\n\tu32 dfs_hist1_pw = 0, dfs_hist2_pw = 0, g_pw[6] = {0};\n\tu32 g_peakindex[16] = {0}, g_mask_32 = 0, false_peak_hist1 = 0;\n\tu32 false_peak_hist2_above10 = 0, false_peak_hist2_above0 = 0;\n\tu32 dfs_hist1_pri = 0, dfs_hist2_pri = 0, g_pri[6] = {0};\n\tu32 pw_sum_g0g5 = 0, pw_sum_g1g2g3g4 = 0;\n\tu32 pri_sum_g0g5 = 0, pri_sum_g1g2g3g4 = 0;\n\tu32 pw_sum_ss_g1g2g3g4 = 0, pri_sum_ss_g1g2g3g4 = 0;\n\tu32 max_pri_cnt = 0, max_pw_cnt = 0;\n\t#if (RTL8721D_SUPPORT)\n\tif (dm->support_ic_type & (ODM_RTL8721D))\n\t\treturn;\n\t#endif\n\n\t/*read peak index hist report*/\n\todm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x0);\n\tdfs_hist1_peak_index = odm_get_bb_reg(dm, 0xf5c, 0xffffffff);\n\tdfs_hist2_peak_index = odm_get_bb_reg(dm, 0xf74, 0xffffffff);\n\n\tg_peakindex[15] = ((dfs_hist1_peak_index & 0x0000000f) >> 0);\n\tg_peakindex[14] = ((dfs_hist1_peak_index & 0x000000f0) >> 4);\n\tg_peakindex[13] = ((dfs_hist1_peak_index & 0x00000f00) >> 8);\n\tg_peakindex[12] = ((dfs_hist1_peak_index & 0x0000f000) >> 12);\n\tg_peakindex[11] = ((dfs_hist1_peak_index & 0x000f0000) >> 16);\n\tg_peakindex[10] = ((dfs_hist1_peak_index & 0x00f00000) >> 20);\n\tg_peakindex[9] = ((dfs_hist1_peak_index & 0x0f000000) >> 24);\n\tg_peakindex[8] = ((dfs_hist1_peak_index & 0xf0000000) >> 28);\n\tg_peakindex[7] = ((dfs_hist2_peak_index & 0x0000000f) >> 0);\n\tg_peakindex[6] = ((dfs_hist2_peak_index & 0x000000f0) >> 4);\n\tg_peakindex[5] = ((dfs_hist2_peak_index & 0x00000f00) >> 8);\n\tg_peakindex[4] = ((dfs_hist2_peak_index & 0x0000f000) >> 12);\n\tg_peakindex[3] = ((dfs_hist2_peak_index & 0x000f0000) >> 16);\n\tg_peakindex[2] = ((dfs_hist2_peak_index & 0x00f00000) >> 20);\n\tg_peakindex[1] = ((dfs_hist2_peak_index & 0x0f000000) >> 24);\n\tg_peakindex[0] = ((dfs_hist2_peak_index & 0xf0000000) >> 28);\n\n\t/*read pulse width hist report*/\n\todm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x1);\n\tdfs_hist1_pw = odm_get_bb_reg(dm, 0xf5c, 0xffffffff);\n\tdfs_hist2_pw = odm_get_bb_reg(dm, 0xf74, 0xffffffff);\n\n\tg_pw[0] = (unsigned int)((dfs_hist2_pw & 0xff000000) >> 24);\n\tg_pw[1] = (unsigned int)((dfs_hist2_pw & 0x00ff0000) >> 16);\n\tg_pw[2] = (unsigned int)((dfs_hist2_pw & 0x0000ff00) >> 8);\n\tg_pw[3] = (unsigned int)dfs_hist2_pw & 0x000000ff;\n\tg_pw[4] = (unsigned int)((dfs_hist1_pw & 0xff000000) >> 24);\n\tg_pw[5] = (unsigned int)((dfs_hist1_pw & 0x00ff0000) >> 16);\n\n\t/*read pulse repetition interval hist report*/\n\todm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x3);\n\tdfs_hist1_pri = odm_get_bb_reg(dm, 0xf5c, 0xffffffff);\n\tdfs_hist2_pri = odm_get_bb_reg(dm, 0xf74, 0xffffffff);\n\todm_set_bb_reg(dm, 0x19b4, 0x10000000, 1); /*reset histo report*/\n\todm_set_bb_reg(dm, 0x19b4, 0x10000000, 0); /*@continue histo report*/\n\n\tg_pri[0] = (unsigned int)((dfs_hist2_pri & 0xff000000) >> 24);\n\tg_pri[1] = (unsigned int)((dfs_hist2_pri & 0x00ff0000) >> 16);\n\tg_pri[2] = (unsigned int)((dfs_hist2_pri & 0x0000ff00) >> 8);\n\tg_pri[3] = (unsigned int)dfs_hist2_pri & 0x000000ff;\n\tg_pri[4] = (unsigned int)((dfs_hist1_pri & 0xff000000) >> 24);\n\tg_pri[5] = (unsigned int)((dfs_hist1_pri & 0x00ff0000) >> 16);\n\n\tdfs->pri_cond1 = 0;\n\tdfs->pri_cond2 = 0;\n\tdfs->pri_cond3 = 0;\n\tdfs->pri_cond4 = 0;\n\tdfs->pri_cond5 = 0;\n\tdfs->pw_cond1 = 0;\n\tdfs->pw_cond2 = 0;\n\tdfs->pw_cond3 = 0;\n\tdfs->pri_type3_4_cond1 = 0;\t/*@for ETSI*/\n\tdfs->pri_type3_4_cond2 = 0;\t/*@for ETSI*/\n\tdfs->pw_long_cond1 = 0;\t\t/*@for long radar*/\n\tdfs->pw_long_cond2 = 0;\t\t/*@for long radar*/\n\tdfs->pri_long_cond1 = 0;\t/*@for long radar*/\n\tdfs->pw_flag = 0;\n\tdfs->pri_flag = 0;\n\tdfs->pri_type3_4_flag = 0;\t/*@for ETSI*/\n\tdfs->long_radar_flag = 0;\n\tdfs->pw_std = 0;\t/*The std(var) of reasonable num of pw group*/\n\tdfs->pri_std = 0;\t/*The std(var) of reasonable num of pri group*/\n\n\tfor (i = 0; i < 6; i++) {\n\t\tdfs->pw_hold_sum[i] = 0;\n\t\tdfs->pri_hold_sum[i] = 0;\n\t\tdfs->pw_long_hold_sum[i] = 0;\n\t\tdfs->pri_long_hold_sum[i] = 0;\n\t}\n\n\tif (dfs->idle_mode == 1)\n\t\tpri_th = dfs->pri_hist_th;\n\telse\n\t\tpri_th = dfs->pri_hist_th - 1;\n\n\tfor (i = 0; i < 6; i++) {\n\t\tdfs->pw_hold[dfs->hist_idx][i] = (u8)g_pw[i];\n\t\tdfs->pri_hold[dfs->hist_idx][i] = (u8)g_pri[i];\n\t\t/*@collect whole histogram report may take some time\n\t\t *so we add the counter of 2 time slots in FCC and ETSI\n\t\t */\n\t\tif (region_domain == 1 || region_domain == 3) {\n\t\t\tdfs->pw_hold_sum[i] = dfs->pw_hold_sum[i] +\n\t\t\t\tdfs->pw_hold[(dfs->hist_idx + 1) % 3][i] +\n\t\t\t\tdfs->pw_hold[(dfs->hist_idx + 2) % 3][i];\n\t\t\tdfs->pri_hold_sum[i] = dfs->pri_hold_sum[i] +\n\t\t\t\tdfs->pri_hold[(dfs->hist_idx + 1) % 3][i] +\n\t\t\t\tdfs->pri_hold[(dfs->hist_idx + 2) % 3][i];\n\t\t} else{\n\t\t/*@collect whole histogram report may take some time,\n\t\t *so we add the counter of 3 time slots in MKK or else\n\t\t */\n\t\t\tdfs->pw_hold_sum[i] = dfs->pw_hold_sum[i] +\n\t\t\t\tdfs->pw_hold[(dfs->hist_idx + 1) % 4][i] +\n\t\t\t\tdfs->pw_hold[(dfs->hist_idx + 2) % 4][i] +\n\t\t\t\tdfs->pw_hold[(dfs->hist_idx + 3) % 4][i];\n\t\t\tdfs->pri_hold_sum[i] = dfs->pri_hold_sum[i] +\n\t\t\t\tdfs->pri_hold[(dfs->hist_idx + 1) % 4][i] +\n\t\t\t\tdfs->pri_hold[(dfs->hist_idx + 2) % 4][i] +\n\t\t\t\tdfs->pri_hold[(dfs->hist_idx + 3) % 4][i];\n\t\t}\n\t}\n\t/*@For long radar type*/\n\tfor (i = 0; i < 6; i++) {\n\t\tdfs->pw_long_hold[dfs->hist_long_idx][i] = (u8)g_pw[i];\n\t\tdfs->pri_long_hold[dfs->hist_long_idx][i] = (u8)g_pri[i];\n\t\t/*@collect whole histogram report may take some time,\n\t\t *so we add the counter of 299 time slots for long radar\n\t\t */\n\t\tfor (j = 1; j < 300; j++) {\n\t\tdfs->pw_long_hold_sum[i] = dfs->pw_long_hold_sum[i] +\n\t\t\tdfs->pw_long_hold[(dfs->hist_long_idx + j) % 300][i];\n\t\tdfs->pri_long_hold_sum[i] = dfs->pri_long_hold_sum[i] +\n\t\t\tdfs->pri_long_hold[(dfs->hist_long_idx + j) % 300][i];\n\t\t}\n\t}\n\tdfs->hist_idx++;\n\tdfs->hist_long_idx++;\n\tif (dfs->hist_long_idx == 300)\n\t\tdfs->hist_long_idx = 0;\n\tif (region_domain == 1 || region_domain == 3) {\n\t\tif (dfs->hist_idx == 3)\n\t\t\tdfs->hist_idx = 0;\n\t} else if (dfs->hist_idx == 4) {\n\t\tdfs->hist_idx = 0;\n\t}\n\n\tmax_pri_cnt = 0;\n\tmax_pri_idx = 0;\n\tmax_pw_cnt = 0;\n\tmax_pw_idx = 0;\n\tmax_pri_cnt_th = dfs->pri_sum_g1_th;\n\tmax_pri_cnt_fcc_g1_th = dfs->pri_sum_g1_fcc_th;\n\tmax_pri_cnt_fcc_g3_th = dfs->pri_sum_g3_fcc_th;\n\tsafe_pri_pw_diff_th = dfs->pri_pw_diff_th;\n\tsafe_pri_pw_diff_fcc_th = dfs->pri_pw_diff_fcc_th;\n\tsafe_pri_pw_diff_fcc_idle_th = dfs->pri_pw_diff_fcc_idle_th;\n\tsafe_pri_pw_diff_w53_th = dfs->pri_pw_diff_w53_th;\n\n\t/*@g1 to g4 is the reseasonable range of pri and pw*/\n\tfor (i = 1; i <= 4; i++) {\n\t\tif (dfs->pri_hold_sum[i] > max_pri_cnt) {\n\t\t\tmax_pri_cnt = dfs->pri_hold_sum[i];\n\t\t\tmax_pri_idx = i;\n\t\t}\n\t\tif (dfs->pw_hold_sum[i] > max_pw_cnt) {\n\t\t\tmax_pw_cnt = dfs->pw_hold_sum[i];\n\t\t\tmax_pw_idx = i;\n\t\t}\n\t\tif (dfs->pri_hold_sum[i] >= pri_th)\n\t\t\tdfs->pri_cond1 = 1;\n\t}\n\n\tpri_sum_g0g5 = dfs->pri_hold_sum[0];\n\tif (pri_sum_g0g5 == 0)\n\t\tpri_sum_g0g5 = 1;\n\tpri_sum_g1g2g3g4 = dfs->pri_hold_sum[1] + dfs->pri_hold_sum[2]\n\t\t\t + dfs->pri_hold_sum[3] + dfs->pri_hold_sum[4];\n\n\t/*pw will reduce because of dc, so we do not treat g0 as illegal group*/\n\tpw_sum_g0g5 = dfs->pw_hold_sum[5];\n\tif (pw_sum_g0g5 == 0)\n\t\tpw_sum_g0g5 = 1;\n\tpw_sum_g1g2g3g4 = dfs->pw_hold_sum[1] + dfs->pw_hold_sum[2] +\n\t\t\t\tdfs->pw_hold_sum[3] + dfs->pw_hold_sum[4];\n\n\t/*@Calculate the variation from g1 to g4*/\n\tfor (i = 1; i < 5; i++) {\n\t\t/*Sum of square*/\n\t\tpw_sum_ss_g1g2g3g4 = pw_sum_ss_g1g2g3g4 +\n\t\t(dfs->pw_hold_sum[i] - (pw_sum_g1g2g3g4 / 4)) *\n\t\t(dfs->pw_hold_sum[i] - (pw_sum_g1g2g3g4 / 4));\n\t\tpri_sum_ss_g1g2g3g4 = pri_sum_ss_g1g2g3g4 +\n\t\t(dfs->pri_hold_sum[i] - (pri_sum_g1g2g3g4 / 4)) *\n\t\t(dfs->pri_hold_sum[i] - (pri_sum_g1g2g3g4 / 4));\n\t}\n\t/*The value may less than the normal variance,\n\t *since the variable type is int (not float)\n\t */\n\t\tdfs->pw_std = (u16)(pw_sum_ss_g1g2g3g4 / 4);\n\t\tdfs->pri_std = (u16)(pri_sum_ss_g1g2g3g4 / 4);\n\n\tif (region_domain == 1) {\n\t\tdfs->pri_type3_4_flag = 1;\t/*@ETSI flag*/\n\n\t\t/*PRI judgment conditions for short radar type*/\n\t\t/*ratio of reasonable group and illegal group &&\n\t\t *pri variation of short radar should be large (=6)\n\t\t */\n\t\tif (max_pri_idx != 4 && dfs->pri_hold_sum[5] > 0)\n\t\t\tdfs->pri_cond2 = 0;\n\t\telse\n\t\t\tdfs->pri_cond2 = 1;\n\n\t\t/*reasonable group shouldn't large*/\n\t\tif ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2 &&\n\t\t    pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_fcc_th)\n\t\t\tdfs->pri_cond3 = 1;\n\n\t\t/*@Cancel the condition that the abs between pri and pw*/\n\t\tif (dfs->pri_std >= dfs->pri_std_th)\n\t\t\tdfs->pri_cond4 = 1;\n\t\telse if (max_pri_idx == 1 &&\n\t\t\t max_pri_cnt >= max_pri_cnt_fcc_g1_th)\n\t\t\tdfs->pri_cond4 = 1;\n\n\t\t/*we set threshold = 7 (>4) for distinguishing type 3,4 (g3)*/\n\t\tif (max_pri_idx == 1 && dfs->pri_hold_sum[3] +\n\t\t    dfs->pri_hold_sum[4] + dfs->pri_hold_sum[5] > 0)\n\t\t\tdfs->pri_cond5 = 0;\n\t\telse\n\t\t\tdfs->pri_cond5 = 1;\n\n\t\tif (dfs->pri_cond1 && dfs->pri_cond2 && dfs->pri_cond3 &&\n\t\t    dfs->pri_cond4 && dfs->pri_cond5)\n\t\t\tdfs->pri_flag = 1;\n\n\t\t/* PW judgment conditions for short radar type */\n\t\t/*ratio of reasonable and illegal group && g5 should be zero*/\n\t\tif (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) &&\n\t\t    (dfs->pw_hold_sum[5] <= 1))\n\t\t\tdfs->pw_cond1 = 1;\n\t\t/*unreasonable group*/\n\t\tif (dfs->pw_hold_sum[4] == 0 && dfs->pw_hold_sum[5] == 0)\n\t\t\tdfs->pw_cond2 = 1;\n\t\t/*pw's std (short radar) should be large(=7)*/\n\t\tif (dfs->pw_std >= dfs->pw_std_th)\n\t\t\tdfs->pw_cond3 = 1;\n\t\tif (dfs->pw_cond1 && dfs->pw_cond2 && dfs->pw_cond3)\n\t\t\tdfs->pw_flag = 1;\n\n\t\t/* @Judgment conditions of long radar type */\n\t\tif (band_width == CHANNEL_WIDTH_20) {\n\t\t\tif (dfs->pw_long_hold_sum[4] >=\n\t\t\t    dfs->pw_long_lower_20m_th)\n\t\t\t\tdfs->pw_long_cond1 = 1;\n\t\t} else{\n\t\t\tif (dfs->pw_long_hold_sum[4] >= dfs->pw_long_lower_th)\n\t\t\t\tdfs->pw_long_cond1 = 1;\n\t\t}\n\t\t/* @Disable the condition that dfs->pw_long_hold_sum[1] */\n\t\tif (dfs->pw_long_hold_sum[2] + dfs->pw_long_hold_sum[3] +\n\t\t    dfs->pw_long_hold_sum[4] <= dfs->pw_long_sum_upper_th &&\n\t\t    dfs->pw_long_hold_sum[2] <= dfs->pw_long_hold_sum[4] &&\n\t\t    dfs->pw_long_hold_sum[3] <= dfs->pw_long_hold_sum[4])\n\t\t\tdfs->pw_long_cond2 = 1;\n\t\t/*@g4 should be large for long radar*/\n\t\tif (dfs->pri_long_hold_sum[4] <= dfs->pri_long_upper_th)\n\t\t\tdfs->pri_long_cond1 = 1;\n\t\tif (dfs->pw_long_cond1 && dfs->pw_long_cond2 &&\n\t\t    dfs->pri_long_cond1)\n\t\t\tdfs->long_radar_flag = 1;\n\t} else if (region_domain == 2) {\n\t\tdfs->pri_type3_4_flag = 1;\t/*@ETSI flag*/\n\n\t\t/*PRI judgment conditions for short radar type*/\n\t\tif ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2)\n\t\t\tdfs->pri_cond2 = 1;\n\n\t\t/*reasonable group shouldn't too large*/\n\t\tif (pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_fcc_th)\n\t\t\tdfs->pri_cond3 = 1;\n\n\t\t/*Cancel the abs diff between pri and pw for idle mode (thr=2)*/\n\t\tdfs->pri_cond4 = 1;\n\n\t\tif (dfs->idle_mode == 1) {\n\t\t\tif (dfs->pri_std >= dfs->pri_std_idle_th) {\n\t\t\t\tif (max_pw_idx == 3 &&\n\t\t\t\t    pri_sum_g1g2g3g4 <= dfs->pri_sum_type4_th){\n\t\t/*To distinguish between type 4 radar and false detection*/\n\t\t\t\t\tdfs->pri_cond5 = 1;\n\t\t\t\t} else if (max_pw_idx == 1 &&\n\t\t\t\t\t   pri_sum_g1g2g3g4 >=\n\t\t\t\t\t   dfs->pri_sum_type6_th) {\n\t\t/*To distinguish between type 6 radar and false detection*/\n\t\t\t\t\tdfs->pri_cond5 = 1;\n\t\t\t\t} else {\n\t\t/*pri variation of short radar should be large (idle mode)*/\n\t\t\t\t\tdfs->pri_cond5 = 1;\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t/*pri variation of short radar should be large (TP mode)*/\n\t\t\tif (dfs->pri_std >= dfs->pri_std_th)\n\t\t\t\tdfs->pri_cond5 = 1;\n\t\t}\n\n\t\tif (dfs->pri_cond1 && dfs->pri_cond2 && dfs->pri_cond3 &&\n\t\t    dfs->pri_cond4 && dfs->pri_cond5)\n\t\t\tdfs->pri_flag = 1;\n\n\t\t/* PW judgment conditions for short radar type */\n\t\tif (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) &&\n\t\t    (dfs->pw_hold_sum[5] <= 1))\n\t\t/*ratio of reasonable and illegal group && g5 should be zero*/\n\t\t\tdfs->pw_cond1 = 1;\n\n\t\tif ((c_channel >= 52) && (c_channel <= 64))\n\t\t\tdfs->pw_cond2 = 1;\n\t\t/*unreasonable group shouldn't too large*/\n\t\telse if (dfs->pw_hold_sum[0] <= dfs->pw_g0_th)\n\t\t\tdfs->pw_cond2 = 1;\n\n\t\tif (dfs->idle_mode == 1) {\n\t\t/*pw variation of short radar should be large (idle mode)*/\n\t\t\tif (dfs->pw_std >= dfs->pw_std_idle_th)\n\t\t\t\tdfs->pw_cond3 = 1;\n\t\t} else {\n\t\t/*pw variation of short radar should be large (TP mode)*/\n\t\t\tif (dfs->pw_std >= dfs->pw_std_th)\n\t\t\t\tdfs->pw_cond3 = 1;\n\t\t}\n\t\tif (dfs->pw_cond1 && dfs->pw_cond2 && dfs->pw_cond3)\n\t\t\tdfs->pw_flag = 1;\n\n\t\t/* @Judgment conditions of long radar type */\n\t\tif (band_width == CHANNEL_WIDTH_20) {\n\t\t\tif (dfs->pw_long_hold_sum[4] >=\n\t\t\t    dfs->pw_long_lower_20m_th)\n\t\t\t\tdfs->pw_long_cond1 = 1;\n\t\t} else{\n\t\t\tif (dfs->pw_long_hold_sum[4] >= dfs->pw_long_lower_th)\n\t\t\t\tdfs->pw_long_cond1 = 1;\n\t\t}\n\t\tif (dfs->pw_long_hold_sum[1] + dfs->pw_long_hold_sum[2] +\n\t\t    dfs->pw_long_hold_sum[3] + dfs->pw_long_hold_sum[4]\n\t\t    <= dfs->pw_long_sum_upper_th)\n\t\t\tdfs->pw_long_cond2 = 1;\n\t\t/*@g4 should be large for long radar*/\n\t\tif (dfs->pri_long_hold_sum[4] <= dfs->pri_long_upper_th)\n\t\t\tdfs->pri_long_cond1 = 1;\n\t\tif (dfs->pw_long_cond1 &&\n\t\t    dfs->pw_long_cond2 && dfs->pri_long_cond1)\n\t\t\tdfs->long_radar_flag = 1;\n\t} else if (region_domain == 3) {\n\t\t/*ratio of reasonable group and illegal group */\n\t\tif ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2)\n\t\t\tdfs->pri_cond2 = 1;\n\n\t\tif (pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_th)\n\t\t\tdfs->pri_cond3 = 1;\n\n\t\t/*@Cancel the condition that the abs between pri and pw*/\n\t\t\tdfs->pri_cond4 = 1;\n\n\t\tif (dfs->pri_hold_sum[5] <= dfs->pri_sum_g5_th)\n\t\t\tdfs->pri_cond5 = 1;\n\n\t\tif (band_width == CHANNEL_WIDTH_40) {\n\t\t\tif (max_pw_idx == 4) {\n\t\t\t\tif (max_pw_cnt >= dfs->type4_pw_max_cnt &&\n\t\t\t\t    pri_sum_g1g2g3g4 >=\n\t\t\t\t    dfs->type4_safe_pri_sum_th) {\n\t\t\t\t\tdfs->pri_cond1 = 1;\n\t\t\t\t\tdfs->pri_cond4 = 1;\n\t\t\t\t\tdfs->pri_type3_4_cond1 = 1;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif (dfs->pri_cond1 && dfs->pri_cond2 &&\n\t\t    dfs->pri_cond3 && dfs->pri_cond4 && dfs->pri_cond5)\n\t\t\tdfs->pri_flag = 1;\n\n\t\tif (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2))\n\t\t\tdfs->pw_flag = 1;\n\n\t\t/*@max num pri group is g1 means radar type3 or type4*/\n\t\tif (max_pri_idx == 1) {\n\t\t\tif (max_pri_cnt >= max_pri_cnt_th)\n\t\t\t\tdfs->pri_type3_4_cond1 = 1;\n\t\t\tif (dfs->pri_hold_sum[4] <=\n\t\t\t    dfs->pri_sum_g5_under_g1_th &&\n\t\t\t    dfs->pri_hold_sum[5] <= dfs->pri_sum_g5_under_g1_th)\n\t\t\t\tdfs->pri_type3_4_cond2 = 1;\n\t\t} else {\n\t\t\tdfs->pri_type3_4_cond1 = 1;\n\t\t\tdfs->pri_type3_4_cond2 = 1;\n\t\t}\n\t\tif (dfs->pri_type3_4_cond1 && dfs->pri_type3_4_cond2)\n\t\t\tdfs->pri_type3_4_flag = 1;\n\t} else {\n\t}\n\n\tif (dfs->print_hist_rpt) {\n\t\tdfs_pw_thd1 = (u8)odm_get_bb_reg(dm, 0x19e4, 0xff000000);\n\t\tdfs_pw_thd2 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x000000ff);\n\t\tdfs_pw_thd3 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x0000ff00);\n\t\tdfs_pw_thd4 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x00ff0000);\n\t\tdfs_pw_thd5 = (u8)odm_get_bb_reg(dm, 0x19e8, 0xff000000);\n\n\t\tdfs_pri_thd1 = (u8)odm_get_bb_reg(dm, 0x19b8, 0x7F80);\n\t\tdfs_pri_thd2 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x000000ff);\n\t\tdfs_pri_thd3 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x0000ff00);\n\t\tdfs_pri_thd4 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x00ff0000);\n\t\tdfs_pri_thd5 = (u8)odm_get_bb_reg(dm, 0x19ec, 0xff000000);\n\n\t\tPHYDM_DBG(dm, DBG_DFS, \"peak index hist\\n\");\n\t\tPHYDM_DBG(dm, DBG_DFS, \"dfs_hist_peak_index=%x %x\\n\",\n\t\t\t  dfs_hist1_peak_index, dfs_hist2_peak_index);\n\t\tPHYDM_DBG(dm, DBG_DFS, \"g_peak_index_hist = \");\n\t\tfor (i = 0; i < 16; i++)\n\t\t\tPHYDM_DBG(dm, DBG_DFS, \" %x\", g_peakindex[i]);\n\t\tPHYDM_DBG(dm, DBG_DFS, \"\\ndfs_pw_thd=%d %d %d %d %d\\n\",\n\t\t\t  dfs_pw_thd1, dfs_pw_thd2, dfs_pw_thd3,\n\t\t\t  dfs_pw_thd4, dfs_pw_thd5);\n\t\tPHYDM_DBG(dm, DBG_DFS, \"-----pulse width hist-----\\n\");\n\t\tPHYDM_DBG(dm, DBG_DFS, \"dfs_hist_pw=%x %x\\n\",\n\t\t\t  dfs_hist1_pw, dfs_hist2_pw);\n\t\tPHYDM_DBG(dm, DBG_DFS, \"g_pw_hist = %x %x %x %x %x %x\\n\",\n\t\t\t  g_pw[0], g_pw[1], g_pw[2], g_pw[3],\n\t\t\t  g_pw[4], g_pw[5]);\n\t\tPHYDM_DBG(dm, DBG_DFS, \"dfs_pri_thd=%d %d %d %d %d\\n\",\n\t\t\t  dfs_pri_thd1, dfs_pri_thd2, dfs_pri_thd3,\n\t\t\t  dfs_pri_thd4, dfs_pri_thd5);\n\t\tPHYDM_DBG(dm, DBG_DFS, \"-----pulse interval hist-----\\n\");\n\t\tPHYDM_DBG(dm, DBG_DFS, \"dfs_hist_pri=%x %x\\n\",\n\t\t\t  dfs_hist1_pri, dfs_hist2_pri);\n\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t  \"g_pri_hist = %x %x %x %x %x %x, pw_flag = %d, pri_flag = %d\\n\",\n\t\t\t  g_pri[0], g_pri[1], g_pri[2], g_pri[3], g_pri[4],\n\t\t\t  g_pri[5], dfs->pw_flag, dfs->pri_flag);\n\t\tif (region_domain == 1 || region_domain == 3) {\n\t\t\tPHYDM_DBG(dm, DBG_DFS, \"hist_idx= %d\\n\",\n\t\t\t\t  (dfs->hist_idx + 2) % 3);\n\t\t} else {\n\t\t\tPHYDM_DBG(dm, DBG_DFS, \"hist_idx= %d\\n\",\n\t\t\t\t  (dfs->hist_idx + 3) % 4);\n\t\t}\n\t\tPHYDM_DBG(dm, DBG_DFS, \"hist_long_idx= %d\\n\",\n\t\t\t  (dfs->hist_long_idx + 299) % 300);\n\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t  \"pw_sum_g0g5 = %d, pw_sum_g1g2g3g4 = %d\\n\",\n\t\t\t  pw_sum_g0g5, pw_sum_g1g2g3g4);\n\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t  \"pri_sum_g0g5 = %d, pri_sum_g1g2g3g4 = %d\\n\",\n\t\t\t  pri_sum_g0g5, pri_sum_g1g2g3g4);\n\t\tPHYDM_DBG(dm, DBG_DFS, \"pw_hold_sum = %d %d %d %d %d %d\\n\",\n\t\t\t  dfs->pw_hold_sum[0], dfs->pw_hold_sum[1],\n\t\t\t  dfs->pw_hold_sum[2], dfs->pw_hold_sum[3],\n\t\t\t  dfs->pw_hold_sum[4], dfs->pw_hold_sum[5]);\n\t\tPHYDM_DBG(dm, DBG_DFS, \"pri_hold_sum = %d %d %d %d %d %d\\n\",\n\t\t\t  dfs->pri_hold_sum[0], dfs->pri_hold_sum[1],\n\t\t\t  dfs->pri_hold_sum[2], dfs->pri_hold_sum[3],\n\t\t\t  dfs->pri_hold_sum[4], dfs->pri_hold_sum[5]);\n\t\tPHYDM_DBG(dm, DBG_DFS, \"pw_long_hold_sum = %d %d %d %d %d %d\\n\",\n\t\t\t  dfs->pw_long_hold_sum[0], dfs->pw_long_hold_sum[1],\n\t\t\t  dfs->pw_long_hold_sum[2], dfs->pw_long_hold_sum[3],\n\t\t\t  dfs->pw_long_hold_sum[4], dfs->pw_long_hold_sum[5]);\n\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t  \"pri_long_hold_sum = %d %d %d %d %d %d\\n\",\n\t\t\t  dfs->pri_long_hold_sum[0], dfs->pri_long_hold_sum[1],\n\t\t\t  dfs->pri_long_hold_sum[2], dfs->pri_long_hold_sum[3],\n\t\t\t  dfs->pri_long_hold_sum[4], dfs->pri_long_hold_sum[5]);\n\t\tPHYDM_DBG(dm, DBG_DFS, \"idle_mode = %d\\n\", dfs->idle_mode);\n\t\tPHYDM_DBG(dm, DBG_DFS, \"pw_standard = %d\\n\", dfs->pw_std);\n\t\tPHYDM_DBG(dm, DBG_DFS, \"pri_standard = %d\\n\", dfs->pri_std);\n\t\tfor (j = 0; j < 4; j++) {\n\t\t\tfor (i = 0; i < 6; i++) {\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS, \"pri_hold = %d \",\n\t\t\t\t\t  dfs->pri_hold[j][i]);\n\t\t\t}\n\t\t\tPHYDM_DBG(dm, DBG_DFS, \"\\n\");\n\t\t}\n\t\tPHYDM_DBG(dm, DBG_DFS, \"\\n\");\n\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t  \"pri_cond1 = %d, pri_cond2 = %d, pri_cond3 = %d, pri_cond4 = %d, pri_cond5 = %d\\n\",\n\t\t\t  dfs->pri_cond1, dfs->pri_cond2, dfs->pri_cond3,\n\t\t\t  dfs->pri_cond4, dfs->pri_cond5);\n\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t  \"bandwidth = %d, pri_th = %d, max_pri_cnt_th = %d, safe_pri_pw_diff_th = %d\\n\",\n\t\t\t  band_width, pri_th, max_pri_cnt_th,\n\t\t\t  safe_pri_pw_diff_th);\n\t}\n}\n\nboolean phydm_dfs_hist_log(void *dm_void, u8 index)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _DFS_STATISTICS *dfs = &dm->dfs;\n\tu8 i = 0, j = 0;\n\tboolean hist_radar_detected = 0;\n\n\tif (dfs->pulse_type_hist[index] == 0) {\n\t\tdfs->radar_type = 0;\n\t\tif (dfs->pw_flag && dfs->pri_flag &&\n\t\t    dfs->pri_type3_4_flag) {\n\t\t\thist_radar_detected = 1;\n\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t  \"Detected type %d radar signal!\\n\",\n\t\t\t\t  dfs->radar_type);\n\t\t\tif (dfs->det_print2) {\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t  \"hist_idx= %d\\n\",\n\t\t\t\t\t  (dfs->hist_idx + 3) % 4);\n\t\t\t\tfor (j = 0; j < 4; j++) {\n\t\t\t\tfor (i = 0; i < 6; i++) {\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t\t  \"pri_hold = %d \",\n\t\t\t\t\t\t  dfs->pri_hold[j][i]);\n\t\t\t\t}\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS, \"\\n\");\n\t\t\t\t}\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS, \"\\n\");\n\t\t\t\tfor (j = 0; j < 4; j++) {\n\t\t\t\tfor (i = 0; i < 6; i++) {\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS, \"pw_hold = %d \",\n\t\t\t\t\t\t  dfs->pw_hold[j][i]);\n\t\t\t\t}\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS, \"\\n\");\n\t\t\t\t}\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS, \"\\n\");\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS, \"idle_mode = %d\\n\",\n\t\t\t\t\t  dfs->idle_mode);\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t  \"pw_hold_sum = %d %d %d %d %d %d\\n\",\n\t\t\t\t\t  dfs->pw_hold_sum[0],\n\t\t\t\t\t  dfs->pw_hold_sum[1],\n\t\t\t\t\t  dfs->pw_hold_sum[2],\n\t\t\t\t\t  dfs->pw_hold_sum[3],\n\t\t\t\t\t  dfs->pw_hold_sum[4],\n\t\t\t\t\t  dfs->pw_hold_sum[5]);\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t  \"pri_hold_sum = %d %d %d %d %d %d\\n\",\n\t\t\t\t\t  dfs->pri_hold_sum[0],\n\t\t\t\t\t  dfs->pri_hold_sum[1],\n\t\t\t\t\t  dfs->pri_hold_sum[2],\n\t\t\t\t\t  dfs->pri_hold_sum[3],\n\t\t\t\t\t  dfs->pri_hold_sum[4],\n\t\t\t\t\t  dfs->pri_hold_sum[5]);\n\t\t\t}\n\t\t} else {\n\t\tif (dfs->det_print2) {\n\t\t\tif (dfs->pulse_flag_hist[index] &&\n\t\t\t    dfs->pri_flag == 0) {\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS, \"pri_variation = %d\\n\",\n\t\t\t\t\t  dfs->pri_std);\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t  \"PRI criterion is not satisfied!\\n\");\n\t\t\t\tif (dfs->pri_cond1 == 0)\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t\t  \"pri_cond1 is not satisfied!\\n\");\n\t\t\t\tif (dfs->pri_cond2 == 0)\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t\t  \"pri_cond2 is not satisfied!\\n\");\n\t\t\t\tif (dfs->pri_cond3 == 0)\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t\t  \"pri_cond3 is not satisfied!\\n\");\n\t\t\t\tif (dfs->pri_cond4 == 0)\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t\t  \"pri_cond4 is not satisfied!\\n\");\n\t\t\t\tif (dfs->pri_cond5 == 0)\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t\t  \"pri_cond5 is not satisfied!\\n\");\n\t\t\t}\n\t\t\tif (dfs->pulse_flag_hist[index] &&\n\t\t\t    dfs->pw_flag == 0) {\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS, \"pw_variation = %d\\n\",\n\t\t\t\t\t  dfs->pw_std);\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t  \"PW criterion is not satisfied!\\n\");\n\t\t\t\tif (dfs->pw_cond1 == 0)\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t\t  \"pw_cond1 is not satisfied!\\n\");\n\t\t\t\tif (dfs->pw_cond2 == 0)\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t\t  \"pw_cond2 is not satisfied!\\n\");\n\t\t\t\tif (dfs->pw_cond3 == 0)\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t\t  \"pw_cond3 is not satisfied!\\n\");\n\t\t\t}\n\t\t\tif (dfs->pulse_flag_hist[index] &&\n\t\t\t    (dfs->pri_type3_4_flag == 0)) {\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t  \"pri_type3_4 criterion is not satisfied!\\n\");\n\t\t\t\tif (dfs->pri_type3_4_cond1 == 0)\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t\t  \"pri_type3_4_cond1 is not satisfied!\\n\");\n\t\t\t\tif (dfs->pri_type3_4_cond2 == 0)\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t\t  \"pri_type3_4_cond2 is not satisfied!\\n\");\n\t\t\t}\n\t\t\tPHYDM_DBG(dm, DBG_DFS, \"hist_idx= %d\\n\",\n\t\t\t\t  (dfs->hist_idx + 3) % 4);\n\t\t\tfor (j = 0; j < 4; j++) {\n\t\t\t\tfor (i = 0; i < 6; i++) {\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t\t  \"pri_hold = %d \",\n\t\t\t\t\t\t  dfs->pri_hold[j][i]);\n\t\t\t\t}\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS, \"\\n\");\n\t\t\t}\n\t\t\tPHYDM_DBG(dm, DBG_DFS, \"\\n\");\n\t\t\tfor (j = 0; j < 4; j++) {\n\t\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t\t  \"pw_hold = %d \",\n\t\t\t\t\t\t  dfs->pw_hold[j][i]);\n\t\t\t\tPHYDM_DBG(dm, DBG_DFS, \"\\n\");\n\t\t\t}\n\t\t\tPHYDM_DBG(dm, DBG_DFS, \"\\n\");\n\t\t\tPHYDM_DBG(dm, DBG_DFS, \"idle_mode = %d\\n\",\n\t\t\t\t  dfs->idle_mode);\n\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t  \"pw_hold_sum = %d %d %d %d %d %d\\n\",\n\t\t\t\t  dfs->pw_hold_sum[0], dfs->pw_hold_sum[1],\n\t\t\t\t  dfs->pw_hold_sum[2], dfs->pw_hold_sum[3],\n\t\t\t\t  dfs->pw_hold_sum[4], dfs->pw_hold_sum[5]);\n\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t  \"pri_hold_sum = %d %d %d %d %d %d\\n\",\n\t\t\t\t  dfs->pri_hold_sum[0], dfs->pri_hold_sum[1],\n\t\t\t\t  dfs->pri_hold_sum[2], dfs->pri_hold_sum[3],\n\t\t\t\t  dfs->pri_hold_sum[4], dfs->pri_hold_sum[5]);\n\t\t}\n\t\t}\n\t} else {\n\t\tdfs->radar_type = 1;\n\t\tif (dfs->det_print2) {\n\t\t\tPHYDM_DBG(dm, DBG_DFS, \"\\n\");\n\t\t\tPHYDM_DBG(dm, DBG_DFS, \"idle_mode = %d\\n\",\n\t\t\t\t  dfs->idle_mode);\n\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t  \"long_radar_pw_hold_sum = %d %d %d %d %d %d\\n\",\n\t\t\t\t  dfs->pw_long_hold_sum[0],\n\t\t\t\t  dfs->pw_long_hold_sum[1],\n\t\t\t\t  dfs->pw_long_hold_sum[2],\n\t\t\t\t  dfs->pw_long_hold_sum[3],\n\t\t\t\t  dfs->pw_long_hold_sum[4],\n\t\t\t\t  dfs->pw_long_hold_sum[5]);\n\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t  \"long_radar_pri_hold_sum = %d %d %d %d %d %d\\n\",\n\t\t\t\t  dfs->pri_long_hold_sum[0],\n\t\t\t\t  dfs->pri_long_hold_sum[1],\n\t\t\t\t  dfs->pri_long_hold_sum[2],\n\t\t\t\t  dfs->pri_long_hold_sum[3],\n\t\t\t\t  dfs->pri_long_hold_sum[4],\n\t\t\t\t  dfs->pri_long_hold_sum[5]);\n\t\t}\n\t\t/* @Long radar should satisfy three conditions */\n\t\tif (dfs->long_radar_flag == 1) {\n\t\t\thist_radar_detected = 1;\n\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t  \"Detected type %d radar signal!\\n\",\n\t\t\t\t  dfs->radar_type);\n\t\t} else {\n\t\t\tif (dfs->det_print2) {\n\t\t\t\tif (dfs->pw_long_cond1 == 0)\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t\t  \"--pw_long_cond1 is not satisfied!--\\n\");\n\t\t\t\tif (dfs->pw_long_cond2 == 0)\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t\t  \"--pw_long_cond2 is not satisfied!--\\n\");\n\t\t\t\tif (dfs->pri_long_cond1 == 0)\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t\t\t  \"--pri_long_cond1 is not satisfied!--\\n\");\n\t\t\t}\n\t\t}\n\t}\n\treturn hist_radar_detected;\n}\n\nboolean phydm_radar_detect(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _DFS_STATISTICS *dfs = &dm->dfs;\n\tboolean enable_DFS = false;\n\tboolean radar_detected = false;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tdfs->igi_cur = (u8)odm_get_bb_reg(dm, R_0x1d70, 0x0000007f);\n\t\tdfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00007f00);\n\t#if (RTL8721D_SUPPORT)\n\t} else if (dm->support_ic_type & (ODM_RTL8721D)) {\n\t\tdfs->st_l2h_cur = (u8)(odm_get_bb_reg(dm, R_0xf54,\n\t\t\t\t\t\t      0x0000001f) << 2);\n\t\tdfs->st_l2h_cur += (u8)odm_get_bb_reg(dm, R_0xf58, 0xc0000000);\n\t#endif\n\t} else {\n\t\tdfs->igi_cur = (u8)odm_get_bb_reg(dm, R_0xc50, 0x0000007f);\n\t\tdfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0x91c, 0x000000ff);\n\t}\n\n\t/* @dynamic pwdb calibration */\n\tif (dfs->igi_pre != dfs->igi_cur) {\n\t\tdfs->pwdb_th_cur = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur)\n\t\t\t\t    / 2 + dfs->pwdb_scalar_factor;\n\n\t\t/* @limit the pwdb value to absolute lower bound 0xa */\n\t\tdfs->pwdb_th_cur = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th);\n\t\t/* @limit the pwdb value to absolute upper bound 0x1f */\n\t\tdfs->pwdb_th_cur = MIN_2(dfs->pwdb_th_cur, 0x1f);\n\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\t\todm_set_bb_reg(dm, R_0xa50, 0x000000f0,\n\t\t\t\t       dfs->pwdb_th_cur);\n\t\t#if (RTL8721D_SUPPORT)\n\t\telse if (dm->support_ic_type & (ODM_RTL8721D))\n\t\t\todm_set_bb_reg(dm, R_0xf70, 0x03c00000,\n\t\t\t\t       dfs->pwdb_th_cur);\n\t\t#endif\n\t\telse\n\t\t\todm_set_bb_reg(dm, R_0x918, 0x00001f00,\n\t\t\t\t       dfs->pwdb_th_cur);\n\t}\n\n\tdfs->igi_pre = dfs->igi_cur;\n\n\tphydm_dfs_dynamic_setting(dm);\n\tif (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))\n\t\tphydm_dfs_histogram_radar_distinguish(dm);\n\tradar_detected = phydm_radar_detect_dm_check(dm);\n\n\tif (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |\n\t\t\t\t   ODM_RTL8197G)) {\n\t\tif (odm_get_bb_reg(dm, R_0xa40, BIT(15)))\n\t\t\tenable_DFS = true;\n\t#if (RTL8721D_SUPPORT)\n\t} else if (dm->support_ic_type & (ODM_RTL8721D)) {\n\t\tif (odm_get_bb_reg(dm, R_0xf58, BIT(29)))\n\t\t\tenable_DFS = true;\n\t#endif\n\t} else if (dm->support_ic_type & (ODM_RTL8814B)) {\n\t\tif (dm->seg1_dfs_flag == 1) {\n\t\t\tif (odm_get_bb_reg(dm, R_0xa6c, BIT(15)))\n\t\t\t\tenable_DFS = true;\n\t\t} else if (odm_get_bb_reg(dm, R_0xa40, BIT(15)))\n\t\t\tenable_DFS = true;\n\t} else {\n\t\tif (odm_get_bb_reg(dm, R_0x924, BIT(15)))\n\t\t\tenable_DFS = true;\n\t}\n\n\tif (enable_DFS && radar_detected) {\n\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t  \"Radar detect: enable_DFS:%d, radar_detected:%d\\n\",\n\t\t\t  enable_DFS, radar_detected);\n\t\tphydm_radar_detect_reset(dm);\n\t\tif (dfs->dbg_mode == 1) {\n\t\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t\t  \"Radar is detected in DFS dbg mode.\\n\");\n\t\t\tradar_detected = 0;\n\t\t}\n\t}\n\n\tif (enable_DFS && dfs->sw_trigger_mode == 1) {\n\t\tradar_detected = 1;\n\t\tPHYDM_DBG(dm, DBG_DFS,\n\t\t\t  \"Radar is detected in DFS SW trigger mode.\\n\");\n\t}\n\n\treturn enable_DFS && radar_detected;\n}\n\nvoid phydm_dfs_hist_dbg(void *dm_void, char input[][16], u32 *_used,\n\t\t\tchar *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _DFS_STATISTICS *dfs = &dm->dfs;\n\tchar help[] = \"-h\";\n\tu32 argv[30] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu8 i;\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{0} pri_hist_th = %d\\n\", dfs->pri_hist_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{1} pri_sum_g1_th = %d\\n\", dfs->pri_sum_g1_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{2} pri_sum_g5_th = %d\\n\", dfs->pri_sum_g5_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{3} pri_sum_g1_fcc_th = %d\\n\",\n\t\t\t dfs->pri_sum_g1_fcc_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{4} pri_sum_g3_fcc_th = %d\\n\",\n\t\t\t dfs->pri_sum_g3_fcc_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{5} pri_sum_safe_fcc_th = %d\\n\",\n\t\t\t dfs->pri_sum_safe_fcc_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{6} pri_sum_type4_th = %d\\n\", dfs->pri_sum_type4_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{7} pri_sum_type6_th = %d\\n\", dfs->pri_sum_type6_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{8} pri_sum_safe_th = %d\\n\", dfs->pri_sum_safe_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{9} pri_sum_g5_under_g1_th = %d\\n\",\n\t\t\t dfs->pri_sum_g5_under_g1_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{10} pri_pw_diff_th = %d\\n\", dfs->pri_pw_diff_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{11} pri_pw_diff_fcc_th = %d\\n\",\n\t\t\t dfs->pri_pw_diff_fcc_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{12} pri_pw_diff_fcc_idle_th = %d\\n\",\n\t\t\t dfs->pri_pw_diff_fcc_idle_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{13} pri_pw_diff_w53_th = %d\\n\",\n\t\t\t dfs->pri_pw_diff_w53_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{14} pri_type1_low_fcc_th = %d\\n\",\n\t\t\t dfs->pri_type1_low_fcc_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{15} pri_type1_upp_fcc_th = %d\\n\",\n\t\t\t dfs->pri_type1_upp_fcc_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{16} pri_type1_cen_fcc_th = %d\\n\",\n\t\t\t dfs->pri_type1_cen_fcc_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{17} pw_g0_th = %d\\n\", dfs->pw_g0_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{18} pw_long_lower_20m_th = %d\\n\",\n\t\t\t dfs->pw_long_lower_20m_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{19} pw_long_lower_th = %d\\n\",\n\t\t\t dfs->pw_long_lower_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{20} pri_long_upper_th = %d\\n\",\n\t\t\t dfs->pri_long_upper_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{21} pw_long_sum_upper_th = %d\\n\",\n\t\t\t dfs->pw_long_sum_upper_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{22} pw_std_th = %d\\n\", dfs->pw_std_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{23} pw_std_idle_th = %d\\n\", dfs->pw_std_idle_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{24} pri_std_th = %d\\n\", dfs->pri_std_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{25} pri_std_idle_th = %d\\n\", dfs->pri_std_idle_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{26} type4_pw_max_cnt = %d\\n\", dfs->type4_pw_max_cnt);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{27} type4_safe_pri_sum_th = %d\\n\",\n\t\t\t dfs->type4_safe_pri_sum_th);\n\t} else {\n\t\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &argv[0]);\n\n\t\tfor (i = 1; i < 30; i++) {\n\t\t\tif (input[i + 1])\n\t\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,\n\t\t\t\t\t     &argv[i]);\n\t\t}\n\t\tif (argv[0] == 0) {\n\t\t\tdfs->pri_hist_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_hist_th = %d\\n\",\n\t\t\t\t dfs->pri_hist_th);\n\t\t} else if (argv[0] == 1) {\n\t\t\tdfs->pri_sum_g1_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_sum_g1_th = %d\\n\",\n\t\t\t\t dfs->pri_sum_g1_th);\n\t\t} else if (argv[0] == 2) {\n\t\t\tdfs->pri_sum_g5_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_sum_g5_th = %d\\n\",\n\t\t\t\t dfs->pri_sum_g5_th);\n\t\t} else if (argv[0] == 3) {\n\t\t\tdfs->pri_sum_g1_fcc_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_sum_g1_fcc_th = %d\\n\",\n\t\t\t\t dfs->pri_sum_g1_fcc_th);\n\t\t} else if (argv[0] == 4) {\n\t\t\tdfs->pri_sum_g3_fcc_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_sum_g3_fcc_th = %d\\n\",\n\t\t\t\t dfs->pri_sum_g3_fcc_th);\n\t\t} else if (argv[0] == 5) {\n\t\t\tdfs->pri_sum_safe_fcc_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_sum_safe_fcc_th = %d\\n\",\n\t\t\t\t dfs->pri_sum_safe_fcc_th);\n\t\t} else if (argv[0] == 6) {\n\t\t\tdfs->pri_sum_type4_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_sum_type4_th = %d\\n\",\n\t\t\t\t dfs->pri_sum_type4_th);\n\t\t} else if (argv[0] == 7) {\n\t\t\tdfs->pri_sum_type6_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_sum_type6_th = %d\\n\",\n\t\t\t\t dfs->pri_sum_type6_th);\n\t\t} else if (argv[0] == 8) {\n\t\t\tdfs->pri_sum_safe_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_sum_safe_th = %d\\n\",\n\t\t\t\t dfs->pri_sum_safe_th);\n\t\t} else if (argv[0] == 9) {\n\t\t\tdfs->pri_sum_g5_under_g1_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_sum_g5_under_g1_th = %d\\n\",\n\t\t\t\t dfs->pri_sum_g5_under_g1_th);\n\t\t} else if (argv[0] == 10) {\n\t\t\tdfs->pri_pw_diff_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_pw_diff_th = %d\\n\",\n\t\t\t\t dfs->pri_pw_diff_th);\n\t\t} else if (argv[0] == 11) {\n\t\t\tdfs->pri_pw_diff_fcc_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_pw_diff_fcc_th = %d\\n\",\n\t\t\t\t dfs->pri_pw_diff_fcc_th);\n\t\t} else if (argv[0] == 12) {\n\t\t\tdfs->pri_pw_diff_fcc_idle_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_pw_diff_fcc_idle_th = %d\\n\",\n\t\t\t\t dfs->pri_pw_diff_fcc_idle_th);\n\t\t} else if (argv[0] == 13) {\n\t\t\tdfs->pri_pw_diff_w53_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_pw_diff_w53_th = %d\\n\",\n\t\t\t\t dfs->pri_pw_diff_w53_th);\n\t\t} else if (argv[0] == 14) {\n\t\t\tdfs->pri_type1_low_fcc_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_type1_low_fcc_th = %d\\n\",\n\t\t\t\t dfs->pri_type1_low_fcc_th);\n\t\t} else if (argv[0] == 15) {\n\t\t\tdfs->pri_type1_upp_fcc_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_type1_upp_fcc_th = %d\\n\",\n\t\t\t\t dfs->pri_type1_upp_fcc_th);\n\t\t} else if (argv[0] == 16) {\n\t\t\tdfs->pri_type1_cen_fcc_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_type1_cen_fcc_th = %d\\n\",\n\t\t\t\t dfs->pri_type1_cen_fcc_th);\n\t\t} else if (argv[0] == 17) {\n\t\t\tdfs->pw_g0_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pw_g0_th = %d\\n\",\n\t\t\t\t dfs->pw_g0_th);\n\t\t} else if (argv[0] == 18) {\n\t\t\tdfs->pw_long_lower_20m_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pw_long_lower_20m_th = %d\\n\",\n\t\t\t\t dfs->pw_long_lower_20m_th);\n\t\t} else if (argv[0] == 19) {\n\t\t\tdfs->pw_long_lower_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pw_long_lower_th = %d\\n\",\n\t\t\t\t dfs->pw_long_lower_th);\n\t\t} else if (argv[0] == 20) {\n\t\t\tdfs->pri_long_upper_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_long_upper_th = %d\\n\",\n\t\t\t\t dfs->pri_long_upper_th);\n\t\t} else if (argv[0] == 21) {\n\t\t\tdfs->pw_long_sum_upper_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pw_long_sum_upper_th = %d\\n\",\n\t\t\t\t dfs->pw_long_sum_upper_th);\n\t\t} else if (argv[0] == 22) {\n\t\t\tdfs->pw_std_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pw_std_th = %d\\n\",\n\t\t\t\t dfs->pw_std_th);\n\t\t} else if (argv[0] == 23) {\n\t\t\tdfs->pw_std_idle_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pw_std_idle_th = %d\\n\",\n\t\t\t\t dfs->pw_std_idle_th);\n\t\t} else if (argv[0] == 24) {\n\t\t\tdfs->pri_std_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_std_th = %d\\n\",\n\t\t\t\t dfs->pri_std_th);\n\t\t} else if (argv[0] == 25) {\n\t\t\tdfs->pri_std_idle_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"pri_std_idle_th = %d\\n\",\n\t\t\t\t dfs->pri_std_idle_th);\n\t\t} else if (argv[0] == 26) {\n\t\t\tdfs->type4_pw_max_cnt = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"type4_pw_max_cnt = %d\\n\",\n\t\t\t\t dfs->type4_pw_max_cnt);\n\t\t} else if (argv[0] == 27) {\n\t\t\tdfs->type4_safe_pri_sum_th = (u8)argv[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"type4_safe_pri_sum_th = %d\\n\",\n\t\t\t\t dfs->type4_safe_pri_sum_th);\n\t\t}\n\t}\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t     char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _DFS_STATISTICS *dfs = &dm->dfs;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 argv[10] = {0};\n\tu8 i, input_idx = 0;\n\n\tfor (i = 0; i < 7; i++) {\n\t\tif (input[i + 1]) {\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_HEX, &argv[i]);\n\t\t\tinput_idx++;\n\t\t}\n\t}\n\n\tif (input_idx == 0)\n\t\treturn;\n\n\tdfs->dbg_mode = (boolean)argv[0];\n\tdfs->sw_trigger_mode = (boolean)argv[1];\n\tdfs->force_TP_mode = (boolean)argv[2];\n\tdfs->det_print = (boolean)argv[3];\n\tdfs->det_print2 = (boolean)argv[4];\n\tdfs->print_hist_rpt = (boolean)argv[5];\n\tdfs->hist_cond_on = (boolean)argv[6];\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"dbg_mode: %d, sw_trigger_mode: %d, force_TP_mode: %d, det_print: %d,det_print2: %d, print_hist_rpt: %d, hist_cond_on: %d\\n\",\n\t\t dfs->dbg_mode, dfs->sw_trigger_mode, dfs->force_TP_mode,\n\t\t dfs->det_print, dfs->det_print2, dfs->print_hist_rpt,\n\t\t dfs->hist_cond_on);\n\n\t/*switch (argv[0]) {\n\tcase 1:\n#if defined(CONFIG_PHYDM_DFS_MASTER)\n\t\t set dbg parameters for radar detection instead of the default value\n\t\tif (argv[1] == 1) {\n\t\t\tdm->radar_detect_reg_918 = argv[2];\n\t\t\tdm->radar_detect_reg_91c = argv[3];\n\t\t\tdm->radar_detect_reg_920 = argv[4];\n\t\t\tdm->radar_detect_reg_924 = argv[5];\n\t\t\tdm->radar_detect_dbg_parm_en = 1;\n\n\t\t\tPDM_SNPF((output + used, out_len - used, \"Radar detection with dbg parameter\\n\"));\n\t\t\tPDM_SNPF((output + used, out_len - used, \"reg918:0x%08X\\n\", dm->radar_detect_reg_918));\n\t\t\tPDM_SNPF((output + used, out_len - used, \"reg91c:0x%08X\\n\", dm->radar_detect_reg_91c));\n\t\t\tPDM_SNPF((output + used, out_len - used, \"reg920:0x%08X\\n\", dm->radar_detect_reg_920));\n\t\t\tPDM_SNPF((output + used, out_len - used, \"reg924:0x%08X\\n\", dm->radar_detect_reg_924));\n\t\t} else {\n\t\t\tdm->radar_detect_dbg_parm_en = 0;\n\t\t\tPDM_SNPF((output + used, out_len - used, \"Radar detection with default parameter\\n\"));\n\t\t}\n\t\tphydm_radar_detect_enable(dm);\n#endif  defined(CONFIG_PHYDM_DFS_MASTER)\n\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}*/\n}\n\nu8 phydm_dfs_polling_time(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 dfs_polling_time = 0;\n\n\tif (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))\n\t\tdfs_polling_time = 40;\n\telse\n\t\tdfs_polling_time = 100;\n\n\treturn dfs_polling_time;\n}\n\n#endif /* @defined(CONFIG_PHYDM_DFS_MASTER) */\n\nboolean\nphydm_is_dfs_band(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (((*dm->channel >= 52) && (*dm->channel <= 64)) ||\n\t    ((*dm->channel >= 100) && (*dm->channel <= 144)))\n\t\treturn true;\n\telse\n\t\treturn false;\n}\n\nboolean\nphydm_dfs_master_enabled(void *dm_void)\n{\n#ifdef CONFIG_PHYDM_DFS_MASTER\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tboolean ret_val = false;\n\n\tif (dm->dfs_master_enabled) /*pointer protection*/\n\t\tret_val = *dm->dfs_master_enabled ? true : false;\n\n\treturn ret_val;\n#else\n\treturn false;\n#endif\n}\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\nvoid phydm_dfs_ap_reset_radar_detect_counter_and_flag(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\t/* @Clear Radar Counter and Radar flag */\n\todm_set_bb_reg(dm, R_0xa40, BIT(15), 0);\n\todm_set_bb_reg(dm, R_0xa40, BIT(15), 1);\n\n\t/* RT_TRACE(COMP_DFS, DBG_LOUD, (\"[DFS], After reset radar counter, 0xcf8 = 0x%x, 0xcf4 = 0x%x\\n\", */\n\t/* PHY_QueryBBReg(Adapter, 0xcf8, bMaskDWord), */\n\t/* PHY_QueryBBReg(Adapter, 0xcf4, bMaskDWord))); */\n}\n#endif\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_dfs.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDM_DFS_H__\n#define __PHYDM_DFS_H__\n\n#define DFS_VERSION \"1.1\"\n\n/*@\n * ============================================================\n *  Definition\n * ============================================================\n */\n\n/*@\n * ============================================================\n * 1  structure\n * ============================================================\n */\n\nstruct _DFS_STATISTICS {\n\tu8\t\tmask_idx;\n\tu8\t\tigi_cur;\n\tu8\t\tigi_pre;\n\tu8\t\tst_l2h_cur;\n\tu16\t\tfa_count_pre;\n\tu16\t\tfa_inc_hist[5];\n\tu16\t\tvht_crc_ok_cnt_pre;\n\tu16\t\tht_crc_ok_cnt_pre;\n\tu16\t\tleg_crc_ok_cnt_pre;\n\tu16\t\tshort_pulse_cnt_pre;\n\tu16\t\tlong_pulse_cnt_pre;\n\tu8\t\tpwdb_th;\n\tu8\t\tpwdb_th_cur;\n\tu8\t\tpwdb_scalar_factor;\n\tu8\t\tpeak_th;\n\tu8\t\tshort_pulse_cnt_th;\n\tu8\t\tlong_pulse_cnt_th;\n\tu8\t\tpeak_window;\n\tu8\t\tthree_peak_opt;\n\tu8\t\tthree_peak_th2;\n\tu8\t\tfa_mask_th;\n\tu8\t\tdet_flag_offset;\n\tu8\t\tst_l2h_max;\n\tu8\t\tst_l2h_min;\n\tu8\t\tmask_hist_checked;\n\tboolean\t\tpulse_flag_hist[5];\n\tboolean\t\tpulse_type_hist[5];\n\tboolean\t\tradar_det_mask_hist[5];\n\tboolean\t\tidle_mode;\n\tboolean\t\tforce_TP_mode;\n\tboolean\t\tdbg_mode;\n\tboolean\t\tsw_trigger_mode;\n\tboolean\t\tdet_print;\n\tboolean\t\tdet_print2;\n\tboolean\t\tradar_type;\n\t/*@dfs histogram*/\n\tboolean\t\tprint_hist_rpt;\n\tboolean\t\thist_cond_on;\n\tboolean\t\tpri_cond1;\n\tboolean\t\tpri_cond2;\n\tboolean\t\tpri_cond3;\n\tboolean\t\tpri_cond4;\n\tboolean\t\tpri_cond5;\n\tboolean\t\tpw_cond1;\n\tboolean\t\tpw_cond2;\n\tboolean\t\tpw_cond3;\n\tboolean\t\tpri_type3_4_cond1;\t/*@for ETSI*/\n\tboolean\t\tpri_type3_4_cond2;\t/*@for ETSI*/\n\tboolean\t\tpw_long_cond1;\t/*@for long radar*/\n\tboolean\t\tpw_long_cond2;\t/*@for long radar*/\n\tboolean\t\tpri_long_cond1;\t/*@for long radar*/\n\tboolean\t\tpw_flag;\n\tboolean\t\tpri_flag;\n\tboolean\t\tpri_type3_4_flag;\t/*@for ETSI*/\n\tboolean\t\tlong_radar_flag;\n\tu16\t\tpri_hold_sum[6];\n\tu16\t\tpw_hold_sum[6];\n\tu16\t\tpri_long_hold_sum[6];\n\tu16\t\tpw_long_hold_sum[6];\n\tu8\t\thist_idx;\n\tu8\t\thist_long_idx;\n\tu8\t\tpw_hold[4][6];\n\tu8\t\tpri_hold[4][6];\n\tu8\t\tpw_long_hold[300][6];\n\tu8\t\tpri_long_hold[300][6];\n\tu16\t\tpw_std;\t/*@The std(var) of reasonable num of pw group*/\n\tu16\t\tpri_std;/*@The std(var) of reasonable num of pri group*/\n\t/*@dfs histogram threshold*/\n\tu8\t\tpri_hist_th;\n\tu8\t\tpri_sum_g1_th;\n\tu8\t\tpri_sum_g5_th;\n\tu8\t\tpri_sum_g1_fcc_th;\n\tu8\t\tpri_sum_g3_fcc_th;\n\tu8\t\tpri_sum_safe_fcc_th;\n\tu8\t\tpri_sum_type4_th;\n\tu8\t\tpri_sum_type6_th;\n\tu8\t\tpri_sum_safe_th;\n\tu8\t\tpri_sum_g5_under_g1_th;\n\tu8\t\tpri_pw_diff_th;\n\tu8\t\tpri_pw_diff_fcc_th;\n\tu8\t\tpri_pw_diff_fcc_idle_th;\n\tu8\t\tpri_pw_diff_w53_th;\n\tu8\t\tpri_type1_low_fcc_th;\n\tu8\t\tpri_type1_upp_fcc_th;\n\tu8\t\tpri_type1_cen_fcc_th;\n\tu8\t\tpw_g0_th;\n\tu8\t\tpw_long_lower_20m_th;\n\tu8\t\tpw_long_lower_th;\n\tu8\t\tpri_long_upper_th;\n\tu8\t\tpw_long_sum_upper_th;\n\tu8\t\tpw_std_th;\n\tu8\t\tpw_std_idle_th;\n\tu8\t\tpri_std_th;\n\tu8\t\tpri_std_idle_th;\n\tu8\t\ttype4_pw_max_cnt;\n\tu8\t\ttype4_safe_pri_sum_th;\n};\n\n/*@\n * ============================================================\n * enumeration\n * ============================================================\n */\n\nenum phydm_dfs_region_domain {\n\tPHYDM_DFS_DOMAIN_UNKNOWN =\t0,\n\tPHYDM_DFS_DOMAIN_FCC =\t\t1,\n\tPHYDM_DFS_DOMAIN_MKK =\t\t2,\n\tPHYDM_DFS_DOMAIN_ETSI =\t\t3,\n};\n\n/*@\n * ============================================================\n * function prototype\n * ============================================================\n */\n#if defined(CONFIG_PHYDM_DFS_MASTER)\nvoid phydm_radar_detect_reset(void *dm_void);\nvoid phydm_radar_detect_disable(void *dm_void);\nvoid phydm_radar_detect_enable(void *dm_void);\nboolean phydm_radar_detect(void *dm_void);\nvoid phydm_dfs_histogram_radar_distinguish(void *dm_void);\nboolean phydm_dfs_hist_log(void *dm_void, u8 index);\nvoid phydm_dfs_parameter_init(void *dm_void);\nvoid phydm_dfs_hist_dbg(void *dm_void, char input[][16], u32 *_used,\n\t\t\tchar *output, u32 *_out_len);\nvoid phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t     char *output, u32 *_out_len);\nu8 phydm_dfs_polling_time(void *dm_void);\n#endif /* @defined(CONFIG_PHYDM_DFS_MASTER) */\n\nboolean\nphydm_dfs_is_meteorology_channel(void *dm_void);\n\nvoid\nphydm_dfs_segment_distinguish(void *dm_void, enum rf_syn syn_path);\n\nvoid\nphydm_dfs_segment_flag_reset(void *dm_void);\n\nboolean\nphydm_is_dfs_band(void *dm_void);\n\nboolean\nphydm_dfs_master_enabled(void *dm_void);\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\nvoid phydm_dfs_ap_reset_radar_detect_counter_and_flag(void *dm_void);\n#endif\n#endif\n\n#endif /*@#ifndef __PHYDM_DFS_H__ */\n"
  },
  {
    "path": "hal/phydm/phydm_dig.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n * ************************************************************\n */\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#ifdef CFG_DIG_DAMPING_CHK\nvoid phydm_dig_recorder_reset(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"%s ======>\\n\", __func__);\n\n\todm_memory_set(dm, &dig_rc->igi_bitmap, 0,\n\t\t       sizeof(struct phydm_dig_recorder_strcut));\n}\n\nvoid phydm_dig_recorder(void *dm_void, boolean first_connect, u8 igi_curr,\n\t\t\tu32 fa_cnt)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;\n\tu8 igi_pre = dig_rc->igi_history[0];\n\tu8 igi_up = 0;\n\n\tif (!dm->is_linked)\n\t\treturn;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"%s ======>\\n\", __func__);\n\n\tif (first_connect) {\n\t\tphydm_dig_recorder_reset(dm);\n\t\tdig_rc->igi_history[0] = igi_curr;\n\t\tdig_rc->fa_history[0] = fa_cnt;\n\t\treturn;\n\t}\n\n\tif (igi_curr % 2)\n\t\tigi_curr--;\n\n\tigi_pre = dig_rc->igi_history[0];\n\tigi_up = (igi_curr > igi_pre) ? 1 : 0;\n\tdig_rc->igi_bitmap = ((dig_rc->igi_bitmap << 1) & 0xfe) | igi_up;\n\n\tdig_rc->igi_history[3] = dig_rc->igi_history[2];\n\tdig_rc->igi_history[2] = dig_rc->igi_history[1];\n\tdig_rc->igi_history[1] = dig_rc->igi_history[0];\n\tdig_rc->igi_history[0] = igi_curr;\n\n\tdig_rc->fa_history[3] = dig_rc->fa_history[2];\n\tdig_rc->fa_history[2] = dig_rc->fa_history[1];\n\tdig_rc->fa_history[1] = dig_rc->fa_history[0];\n\tdig_rc->fa_history[0] = fa_cnt;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"igi_history[3:0] = {0x%x, 0x%x, 0x%x, 0x%x}\\n\",\n\t\t  dig_rc->igi_history[3], dig_rc->igi_history[2],\n\t\t  dig_rc->igi_history[1], dig_rc->igi_history[0]);\n\tPHYDM_DBG(dm, DBG_DIG, \"fa_history[3:0] = {%d, %d, %d, %d}\\n\",\n\t\t  dig_rc->fa_history[3], dig_rc->fa_history[2],\n\t\t  dig_rc->fa_history[1], dig_rc->fa_history[0]);\n\tPHYDM_DBG(dm, DBG_DIG, \"igi_bitmap = {%d, %d, %d, %d} = 0x%x\\n\",\n\t\t  (u8)((dig_rc->igi_bitmap & BIT(3)) >> 3),\n\t\t  (u8)((dig_rc->igi_bitmap & BIT(2)) >> 2),\n\t\t  (u8)((dig_rc->igi_bitmap & BIT(1)) >> 1),\n\t\t  (u8)(dig_rc->igi_bitmap & BIT(0)),\n\t\t  dig_rc->igi_bitmap);\n}\n\nvoid phydm_dig_damping_chk(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;\n\tu8 igi_bitmap_4bit = dig_rc->igi_bitmap & 0xf;\n\tu8 diff1 = 0, diff2 = 0;\n\tu32 fa_low_th = dig_t->fa_th[0];\n\tu32 fa_high_th = dig_t->fa_th[1];\n\tu32 fa_high_th2 = dig_t->fa_th[2];\n\tu8 fa_pattern_match = 0;\n\tu32 time_tmp = 0;\n\n\tif (!dm->is_linked)\n\t\treturn;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"%s ======>\\n\", __func__);\n\n\t/*@== Release Damping ================================================*/\n\tif (dig_rc->damping_limit_en) {\n\t\tPHYDM_DBG(dm, DBG_DIG,\n\t\t\t  \"[Damping Limit!] limit_time=%d, phydm_sys_up_time=%d\\n\",\n\t\t\t  dig_rc->limit_time, dm->phydm_sys_up_time);\n\n\t\ttime_tmp = dig_rc->limit_time + DIG_LIMIT_PERIOD;\n\n\t\tif (DIFF_2(dm->rssi_min, dig_rc->limit_rssi) > 3 ||\n\t\t    time_tmp < dm->phydm_sys_up_time) {\n\t\t\tdig_rc->damping_limit_en = 0;\n\t\t\tPHYDM_DBG(dm, DBG_DIG, \"rssi_min=%d, limit_rssi=%d\\n\",\n\t\t\t\t  dm->rssi_min, dig_rc->limit_rssi);\n\t\t}\n\t\treturn;\n\t}\n\n\t/*@== Damping Pattern Check===========================================*/\n\tPHYDM_DBG(dm, DBG_DIG, \"fa_th{H, L}= {%d,%d}\\n\", fa_high_th, fa_low_th);\n\n\tswitch (igi_bitmap_4bit) {\n\tcase 0x5:\n\t/*@ 4b'0101 \n\t* IGI:[3]down(0x24)->[2]up(0x26)->[1]down(0x24)->[0]up(0x26)->[new](Lock @ 0x26)\n\t* FA: [3] >high1   ->[2] <low   ->[1] >high1   ->[0] <low   ->[new]   <low\n\t*\n\t* IGI:[3]down(0x24)->[2]up(0x28)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28)\n\t* FA: [3] >high2   ->[2] <low   ->[1] >high2   ->[0] <low   ->[new]   <low\n\t*/\n\t\tif (dig_rc->igi_history[0] > dig_rc->igi_history[1])\n\t\t\tdiff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];\n\n\t\tif (dig_rc->igi_history[2] > dig_rc->igi_history[3])\n\t\t\tdiff2 = dig_rc->igi_history[2] - dig_rc->igi_history[3];\n\n\t\tif (dig_rc->fa_history[0] < fa_low_th &&\n\t\t    dig_rc->fa_history[1] > fa_high_th &&\n\t\t    dig_rc->fa_history[2] < fa_low_th &&\n\t\t    dig_rc->fa_history[3] > fa_high_th) {\n\t\t    /*@Check each fa element*/\n\t\t\tfa_pattern_match = 1;\n\t\t}\n\t\tbreak;\n\tcase 0x9:\n\t/*@ 4b'1001\n\t* IGI:[3]up(0x28)->[2]down(0x26)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28)\n\t* FA: [3]  <low  ->[2] <low     ->[1] >high2   ->[0] <low   ->[new]  <low\n\t*/\n\t\tif (dig_rc->igi_history[0] > dig_rc->igi_history[1])\n\t\t\tdiff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];\n\n\t\tif (dig_rc->igi_history[2] < dig_rc->igi_history[3])\n\t\t\tdiff2 = dig_rc->igi_history[3] - dig_rc->igi_history[2];\n\n\t\tif (dig_rc->fa_history[0] < fa_low_th &&\n\t\t    dig_rc->fa_history[1] > fa_high_th2 &&\n\t\t    dig_rc->fa_history[2] < fa_low_th &&\n\t\t    dig_rc->fa_history[3] < fa_low_th) {\n\t\t    /*@Check each fa element*/\n\t\t\tfa_pattern_match = 1;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (diff1 >= 2 && diff2 >= 2 && fa_pattern_match) {\n\t\tdig_rc->damping_limit_en = 1;\n\t\tdig_rc->damping_limit_val = dig_rc->igi_history[0];\n\t\tdig_rc->limit_time = dm->phydm_sys_up_time;\n\t\tdig_rc->limit_rssi = dm->rssi_min;\n\n\t\tPHYDM_DBG(dm, DBG_DIG,\n\t\t\t  \"[Start damping_limit!] IGI_dyn_min=0x%x, limit_time=%d, limit_rssi=%d\\n\",\n\t\t\t  dig_rc->damping_limit_val,\n\t\t\t  dig_rc->limit_time, dig_rc->limit_rssi);\n\t}\n\n\tPHYDM_DBG(dm, DBG_DIG, \"damping_limit=%d\\n\", dig_rc->damping_limit_en);\n}\n#endif\n\nboolean\nphydm_dig_go_up_check(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ccx_info *ccx_info = &dm->dm_ccx_info;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tu8 cur_ig_value = dig_t->cur_ig_value;\n\tu8 max_cover_bond = 0;\n\tu8 rx_gain_range_max = dig_t->rx_gain_range_max;\n\tu8 i = 0, j = 0;\n\tu8 total_nhm_cnt = ccx_info->nhm_rpt_sum;\n\tu32 dig_cnt = 0;\n\tu32 over_dig_cnt = 0;\n\tboolean ret = true;\n\n\tif (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE)\n\t\treturn ret;\n\n\tmax_cover_bond = DIG_MAX_BALANCE_MODE - dig_t->upcheck_init_val;\n\n\tif (cur_ig_value < max_cover_bond - 6)\n\t\tdig_t->go_up_chk_lv = DIG_GOUPCHECK_LEVEL_0;\n\telse if (cur_ig_value <= DIG_MAX_BALANCE_MODE)\n\t\tdig_t->go_up_chk_lv = DIG_GOUPCHECK_LEVEL_1;\n\telse /* @cur_ig_value > DM_DIG_MAX_AP, foolproof */\n\t\tdig_t->go_up_chk_lv = DIG_GOUPCHECK_LEVEL_2;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"check_lv = %d, max_cover_bond = 0x%x\\n\",\n\t\t  dig_t->go_up_chk_lv, max_cover_bond);\n\n\tif (total_nhm_cnt == 0)\n\t\treturn true;\n\n\tif (dig_t->go_up_chk_lv == DIG_GOUPCHECK_LEVEL_0) {\n\t\tfor (i = 3; i <= 11; i++)\n\t\t\tdig_cnt += ccx_info->nhm_result[i];\n\n\t\tif ((dig_t->lv0_ratio_reciprocal * dig_cnt) >= total_nhm_cnt)\n\t\t\tret = true;\n\t\telse\n\t\t\tret = false;\n\n\t} else if (dig_t->go_up_chk_lv == DIG_GOUPCHECK_LEVEL_1) {\n\t\t/* search index */\n\t\tfor (i = 0; i <= 10; i++) {\n\t\t\tif ((max_cover_bond * 2) == ccx_info->nhm_th[i]) {\n\t\t\t\tfor (j = (i + 1); j <= 11; j++)\n\t\t\t\t\tover_dig_cnt += ccx_info->nhm_result[j];\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tif (dig_t->lv1_ratio_reciprocal * over_dig_cnt < total_nhm_cnt)\n\t\t\tret = true;\n\t\telse\n\t\t\tret = false;\n\n\t\tif (!ret) {\n\t\t\t/* update dig_t->rx_gain_range_max */\n\t\t\tif (rx_gain_range_max + 6 >= max_cover_bond)\n\t\t\t\tdig_t->rx_gain_range_max =  max_cover_bond - 6;\n\t\t\telse\n\t\t\t\tdig_t->rx_gain_range_max =  rx_gain_range_max;\n\n\t\t\tPHYDM_DBG(dm, DBG_DIG,\n\t\t\t\t  \"Noise pwr over DIG can filter, lock rx_gain_range_max to 0x%x\\n\",\n\t\t\t\t  dig_t->rx_gain_range_max);\n\t\t}\n\t} else if (dig_t->go_up_chk_lv == DIG_GOUPCHECK_LEVEL_2) {\n\t\t/* @cur_ig_value > DM_DIG_MAX_AP, foolproof */\n\t\tret = true;\n\t}\n\n\treturn ret;\n}\n\nvoid phydm_fa_threshold_check(void *dm_void, boolean is_dfs_band)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\n\tif (dig_t->is_dbg_fa_th) {\n\t\tPHYDM_DBG(dm, DBG_DIG, \"Manual Fix FA_th\\n\");\n\t} else if (dm->is_linked) {\n\t\tif (dm->rssi_min < 20) { /*@[PHYDM-252]*/\n\t\t\tdig_t->fa_th[0] = 500;\n\t\t\tdig_t->fa_th[1] = 750;\n\t\t\tdig_t->fa_th[2] = 1000;\n\t\t} else if (((dm->rx_tp >> 2) > dm->tx_tp) && /*Test RX TP*/\n\t\t\t   (dm->rx_tp < 10) && (dm->rx_tp > 1)) { /*TP=1~10Mb*/\n\t\t\tdig_t->fa_th[0] = 125;\n\t\t\tdig_t->fa_th[1] = 250;\n\t\t\tdig_t->fa_th[2] = 500;\n\t\t} else {\n\t\t\tdig_t->fa_th[0] = 250;\n\t\t\tdig_t->fa_th[1] = 500;\n\t\t\tdig_t->fa_th[2] = 750;\n\t\t}\n\t} else {\n\t\tif (is_dfs_band) { /* @For DFS band and no link */\n\n\t\t\tdig_t->fa_th[0] = 250;\n\t\t\tdig_t->fa_th[1] = 1000;\n\t\t\tdig_t->fa_th[2] = 2000;\n\t\t} else {\n\t\t\tdig_t->fa_th[0] = 2000;\n\t\t\tdig_t->fa_th[1] = 4000;\n\t\t\tdig_t->fa_th[2] = 5000;\n\t\t}\n\t}\n\n\tPHYDM_DBG(dm, DBG_DIG, \"FA_th={%d,%d,%d}\\n\", dig_t->fa_th[0],\n\t\t  dig_t->fa_th[1], dig_t->fa_th[2]);\n}\n\nvoid phydm_set_big_jump_step(void *dm_void, u8 curr_igi)\n{\n#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tu8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90};\n\tu8 big_jump_lmt = dig_t->big_jump_lmt[dig_t->agc_table_idx];\n\tu8 i;\n\n\tif (dig_t->enable_adjust_big_jump == 0)\n\t\treturn;\n\n\tfor (i = 0; i <= dig_t->big_jump_step1; i++) {\n\t\tif ((curr_igi + step1[i]) > big_jump_lmt) {\n\t\t\tif (i != 0)\n\t\t\t\ti = i - 1;\n\t\t\tbreak;\n\t\t} else if (i == dig_t->big_jump_step1) {\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (dm->support_ic_type & ODM_RTL8822B)\n\t\todm_set_bb_reg(dm, R_0x8c8, 0xe, i);\n\telse if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))\n\t\todm_set_bb_reg(dm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i);\n\n\tPHYDM_DBG(dm, DBG_DIG, \"Bigjump = %d (ori = 0x%x), LMT=0x%x\\n\", i,\n\t\t  dig_t->big_jump_step1, big_jump_lmt);\n#endif\n}\n\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\nvoid phydm_write_dig_reg_jgr3(void *dm_void, u8 igi)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"%s===>\\n\", __func__);\n\n\t/* Set IGI value */\n\tif (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))\n\t\treturn;\n\n\todm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC, igi);\n\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tif (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)\n\t\todm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3, igi);\n\t#endif\n\n\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\tif (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {\n\t\todm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3, igi);\n\t\todm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3, igi);\n\t}\n\t#endif\n}\n\nu8 phydm_get_igi_reg_val_jgr3(void *dm_void, enum bb_path path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 val = 0;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"%s===>\\n\", __func__);\n\n\t/* Set IGI value */\n\tif (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))\n\t\treturn (u8)val;\n\n\tif (path == BB_PATH_A)\n\t\tval = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC);\n#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\telse if (path == BB_PATH_B)\n\t\tval = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3);\n#endif\n\n#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\telse if (path == BB_PATH_C)\n\t\tval = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3);\n#endif\n\n#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\telse if (path == BB_PATH_D)\n\t\tval = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3);\n#endif\n\treturn (u8)val;\n}\n\nvoid phydm_fa_cnt_statistics_jgr3(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fa_struct *fa_t = &dm->false_alm_cnt;\n\tu32 ret_value = 0;\n\tu32 cck_enable = 0;\n\tu16 ofdm_tx_counter = 0;\n\tu16 cck_tx_counter = 0;\n\n\tif (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))\n\t\treturn;\n\n\tofdm_tx_counter = (u16)odm_get_bb_reg(dm, R_0x2de0, MASKLWORD);\n\tcck_tx_counter = (u16)odm_get_bb_reg(dm, R_0x2de4, MASKLWORD);\n\n\tret_value = odm_get_bb_reg(dm, R_0x2d20, MASKDWORD);\n\tfa_t->cnt_fast_fsync = (ret_value & 0xffff);\n\tfa_t->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);\n\n\tret_value = odm_get_bb_reg(dm, R_0x2d04, MASKDWORD);\n\tfa_t->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);\n\n\tret_value = odm_get_bb_reg(dm, R_0x2d08, MASKDWORD);\n\tfa_t->cnt_rate_illegal = (ret_value & 0xffff);\n\tfa_t->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);\n\n\tret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);\n\tfa_t->cnt_mcs_fail = (ret_value & 0xffff);\n\n\t/* read CCK CRC32 counter */\n\tret_value = odm_get_bb_reg(dm, R_0x2c04, MASKDWORD);\n\tfa_t->cnt_cck_crc32_error = ((ret_value & 0xffff0000) >> 16);\n\tfa_t->cnt_cck_crc32_ok = ret_value & 0xffff;\n\n\t/* read OFDM CRC32 counter */\n\tret_value = odm_get_bb_reg(dm, R_0x2c14, MASKDWORD);\n\tfa_t->cnt_ofdm_crc32_error = ((ret_value & 0xffff0000) >> 16);\n\tfa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;\n\n\t/* read HT CRC32 counter */\n\tret_value = odm_get_bb_reg(dm, R_0x2c10, MASKDWORD);\n\tfa_t->cnt_ht_crc32_error = ((ret_value & 0xffff0000) >> 16);\n\tfa_t->cnt_ht_crc32_ok = ret_value & 0xffff;\n\n\t/* @for VHT part */\n\tif (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |\n\t    ODM_RTL8814B)) {\n\t\t/* read VHT CRC32 counter */\n\t\tret_value = odm_get_bb_reg(dm, R_0x2c0c, MASKDWORD);\n\t\tfa_t->cnt_vht_crc32_error = ((ret_value & 0xffff0000) >> 16);\n\t\tfa_t->cnt_vht_crc32_ok = ret_value & 0xffff;\n\n\t\tret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);\n\t\tfa_t->cnt_mcs_fail_vht = ((ret_value & 0xffff0000) >> 16);\n\n\t\tret_value = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD);\n\t\tfa_t->cnt_crc8_fail_vht = (ret_value & 0xffff) +\n\t\t\t\t\t  ((ret_value & 0xffff0000) >> 16);\n\t} else {\n\t\tfa_t->cnt_vht_crc32_error = 0;\n\t\tfa_t->cnt_vht_crc32_ok = 0;\n\t\tfa_t->cnt_mcs_fail_vht = 0;\n\t\tfa_t->cnt_crc8_fail_vht = 0;\n\t}\n\n\t/* @calculate OFDM FA counter instead of reading brk_cnt*/\n\tfa_t->cnt_ofdm_fail = fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal +\n\t\t\t      fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail +\n\t\t\t      fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail +\n\t\t\t      fa_t->cnt_mcs_fail_vht + fa_t->cnt_crc8_fail_vht;\n\n\t/* Read CCK FA counter */\n\tfa_t->cnt_cck_fail = odm_get_bb_reg(dm, R_0x1a5c, MASKLWORD);\n\n\t/* read CCK/OFDM CCA counter */\n\tret_value = odm_get_bb_reg(dm, R_0x2c08, MASKDWORD);\n\tfa_t->cnt_ofdm_cca = ((ret_value & 0xffff0000) >> 16);\n\tfa_t->cnt_cck_cca = ret_value & 0xffff;\n\n\t/* @CCK RxIQ weighting = 1 => 0x1a14[9:8]=0x0 */\n\tcck_enable = odm_get_bb_reg(dm, R_0x1a14, 0x300);\n\tif (cck_enable == 0x0) { /* @if(*dm->band_type == ODM_BAND_2_4G) */\n\t\tfa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail;\n\t\tfa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;\n\t\tPHYDM_DBG(dm, DBG_FA_CNT, \"ac3 OFDM FA = %d, CCK FA = %d\\n\",\n\t\t\t  fa_t->cnt_ofdm_fail, fa_t->cnt_cck_fail);\n\t} else {\n\t\tfa_t->cnt_all = fa_t->cnt_ofdm_fail;\n\t\tfa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;\n\t\tPHYDM_DBG(dm, DBG_FA_CNT, \"ac3 CCK disable OFDM FA = %d\\n\",\n\t\t\t  fa_t->cnt_ofdm_fail);\n\t}\n\n\tPHYDM_DBG(dm, DBG_FA_CNT,\n\t\t  \"ac3 [OFDM FA Detail] Parity_fail=((%d)), Rate_Illegal=((%d)), CRC8_fail=((%d)), Mcs_fail=((%d)), Fast_Fsync=((%d)), SBD_fail=((%d))\\n\",\n\t\t  fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,\n\t\t  fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail, fa_t->cnt_fast_fsync,\n\t\t  fa_t->cnt_sb_search_fail);\n}\n\n#endif\n\nvoid phydm_write_dig_reg_c50(void *dm_void, u8 igi)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"%s===>\\n\", __func__);\n\n\todm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), igi);\n\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tif (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)\n\t\todm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), igi);\n\t#endif\n\n\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\tif (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {\n\t\todm_set_bb_reg(dm, ODM_REG(IGI_C, dm), ODM_BIT(IGI, dm), igi);\n\t\todm_set_bb_reg(dm, ODM_REG(IGI_D, dm), ODM_BIT(IGI, dm), igi);\n\t}\n\t#endif\n}\n\nvoid phydm_write_dig_reg(void *dm_void, u8 igi)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"%s===>\\n\", __func__);\n\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tphydm_write_dig_reg_jgr3(dm, igi);\n\telse\n\t#endif\n\t\tphydm_write_dig_reg_c50(dm, igi);\n\n\tdig_t->cur_ig_value = igi;\n}\n\nvoid odm_write_dig(void *dm_void, u8 new_igi)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"%s===>\\n\", __func__);\n\n\t/* @1 Check IGI by upper bound */\n\tif (adaptivity->igi_lmt_en &&\n\t    new_igi > adaptivity->adapt_igi_up && dm->is_linked) {\n\t\tnew_igi = adaptivity->adapt_igi_up;\n\n\t\tPHYDM_DBG(dm, DBG_DIG, \"Force Adaptivity Up-bound=((0x%x))\\n\",\n\t\t\t  new_igi);\n\t}\n\n\t#if (RTL8192F_SUPPORT)\n\tif ((dm->support_ic_type & ODM_RTL8192F) &&\n\t    dm->cut_version == ODM_CUT_A &&\n\t    new_igi > 0x38) {\n\t\tnew_igi = 0x38;\n\t\tPHYDM_DBG(dm, DBG_DIG,\n\t\t\t  \"Force 92F Adaptivity Up-bound=((0x%x))\\n\", new_igi);\n\t}\n\t#endif\n\n\tif (dig_t->cur_ig_value != new_igi) {\n\t\t#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)\n\t\t/* @Modify big jump step for 8822B and 8197F */\n\t\tif (dm->support_ic_type &\n\t\t    (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F))\n\t\t\tphydm_set_big_jump_step(dm, new_igi);\n\t\t#endif\n\n\t\t#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)\n\t\t/* Set IGI value of CCK for new CCK AGC */\n\t\tif (dm->cck_new_agc &&\n\t\t    (dm->support_ic_type & PHYSTS_2ND_TYPE_IC))\n\t\t\todm_set_bb_reg(dm, R_0xa0c, 0x3f00, (new_igi >> 1));\n\t\t#endif\n\n\t\t/*@Add by YuChen for USB IO too slow issue*/\n\t\tif (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {\n\t\t\tif (dm->support_ability & ODM_BB_ADAPTIVITY &&\n\t\t\t    new_igi < dig_t->cur_ig_value) {\n\t\t\t\tdig_t->cur_ig_value = new_igi;\n\t\t\t\tphydm_adaptivity(dm);\n\t\t\t}\n\t\t} else {\n\t\t\tif (dm->support_ability & ODM_BB_ADAPTIVITY &&\n\t\t\t    new_igi > dig_t->cur_ig_value) {\n\t\t\t\tdig_t->cur_ig_value = new_igi;\n\t\t\t\tphydm_adaptivity(dm);\n\t\t\t}\n\t\t}\n\t\tphydm_write_dig_reg(dm, new_igi);\n\t}\n\n\tPHYDM_DBG(dm, DBG_DIG, \"New_igi=((0x%x))\\n\\n\", new_igi);\n}\n\nu8 phydm_get_igi_reg_val(void *dm_void, enum bb_path path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 val = 0;\n\tu32 bit_map = ODM_BIT(IGI, dm);\n\n\tswitch (path) {\n\tcase BB_PATH_A:\n\t\tval = odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), bit_map);\n\t\tbreak;\n\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\tcase BB_PATH_B:\n\t\tval = odm_get_bb_reg(dm, ODM_REG(IGI_B, dm), bit_map);\n\t\tbreak;\n\t#endif\n\n\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\tcase BB_PATH_C:\n\t\tval = odm_get_bb_reg(dm, ODM_REG(IGI_C, dm), bit_map);\n\t\tbreak;\n\t#endif\n\n\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\tcase BB_PATH_D:\n\t\tval = odm_get_bb_reg(dm, ODM_REG(IGI_D, dm), bit_map);\n\t\tbreak;\n\t#endif\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn (u8)val;\n}\n\nu8 phydm_get_igi(void *dm_void, enum bb_path path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 val = 0;\n\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tval = phydm_get_igi_reg_val_jgr3(dm, path);\n\telse\n\t#endif\n\t\tval = phydm_get_igi_reg_val(dm, path);\n\n\treturn val;\n}\n\nvoid phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (val_len != 1) {\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[Error][DIG]Need val_len=1\\n\");\n\t\treturn;\n\t}\n\n\todm_write_dig(dm, (u8)(*val_buf));\n}\n\nvoid odm_pause_dig(void *dm_void, enum phydm_pause_type type,\n\t\t   enum phydm_pause_level lv, u8 igi_input)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 rpt = false;\n\tu32 igi = (u32)igi_input;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"[%s]type=%d, LV=%d, igi=0x%x\\n\", __func__, type,\n\t\t  lv, igi);\n\n\tswitch (type) {\n\tcase PHYDM_PAUSE:\n\tcase PHYDM_PAUSE_NO_SET: {\n\t\trpt = phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, lv, 1, &igi);\n\t\tbreak;\n\t}\n\n\tcase PHYDM_RESUME: {\n\t\trpt = phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, lv, 1, &igi);\n\t\tbreak;\n\t}\n\tdefault:\n\t\tPHYDM_DBG(dm, DBG_DIG, \"Wrong type\\n\");\n\t\tbreak;\n\t}\n\n\tPHYDM_DBG(dm, DBG_DIG, \"pause_result=%d\\n\", rpt);\n}\n\nboolean\nphydm_dig_abort(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n#endif\n\n\t/* support_ability */\n\tif ((!(dm->support_ability & ODM_BB_FA_CNT)) ||\n\t    (!(dm->support_ability & ODM_BB_DIG)) ||\n\t    *dm->is_scan_in_process) {\n\t\tPHYDM_DBG(dm, DBG_DIG, \"Not Support\\n\");\n\t\treturn true;\n\t}\n\n\tif (dm->pause_ability & ODM_BB_DIG) {\n\t\tPHYDM_DBG(dm, DBG_DIG, \"Return: Pause DIG in LV=%d\\n\",\n\t\t\t  dm->pause_lv_table.lv_dig);\n\t\treturn true;\n\t}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#if OS_WIN_FROM_WIN7(OS_VERSION)\n\tif (IsAPModeExist(adapter) && ((PADAPTER)(adapter))->bInHctTest) {\n\t\tPHYDM_DBG(dm, DBG_DIG, \" Return: Is AP mode or In HCT Test\\n\");\n\t\treturn true;\n\t}\n#endif\n#endif\n\n\treturn false;\n}\n\nvoid phydm_dig_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tstruct phydm_fa_struct *false_alm_cnt = &dm->false_alm_cnt;\n#endif\n\tu32 ret_value = 0;\n\tu8 i;\n\n\tdig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;\n\tdig_t->dm_dig_min = DIG_MIN_PERFORMANCE;\n\tdig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;\n\n\tdig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);\n\n\tdig_t->is_media_connect = false;\n\n\tdig_t->fa_th[0] = 250;\n\tdig_t->fa_th[1] = 500;\n\tdig_t->fa_th[2] = 750;\n\tdig_t->is_dbg_fa_th = false;\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\t/* @For RTL8881A */\n\tfalse_alm_cnt->cnt_ofdm_fail_pre = 0;\n#endif\n\n\tdig_t->rx_gain_range_max = DIG_MAX_BALANCE_MODE;\n\tdig_t->rx_gain_range_min = dig_t->cur_ig_value;\n\n#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)\n\tdig_t->enable_adjust_big_jump = 1;\n\tif (dm->support_ic_type & ODM_RTL8822B)\n\t\tret_value = odm_get_bb_reg(dm, R_0x8c8, MASKLWORD);\n\telse if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))\n\t\tret_value = odm_get_bb_reg(dm, R_0xc74, MASKLWORD);\n\n\tdig_t->big_jump_step1 = (u8)(ret_value & 0xe) >> 1;\n\tdig_t->big_jump_step2 = (u8)(ret_value & 0x30) >> 4;\n\tdig_t->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6;\n\n\tif (dm->support_ic_type &\n\t    (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)) {\n\t\tfor (i = 0; i < sizeof(dig_t->big_jump_lmt); i++) {\n\t\t\tif (dig_t->big_jump_lmt[i] == 0)\n\t\t\t\tdig_t->big_jump_lmt[i] = 0x64;\n\t\t\t\t/* Set -10dBm as default value */\n\t\t}\n\t}\n#endif\n\n#ifdef PHYDM_TDMA_DIG_SUPPORT\n\t#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\t\tdm->original_dig_restore = true;\n\t\tdm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;\n\t\tdm->tdma_dig_timer_ms = DIG_TIMER_MS;\n\t#endif\n#endif\n#ifdef CFG_DIG_DAMPING_CHK\n\tphydm_dig_recorder_reset(dm);\n\tdig_t->dig_dl_en = 1;\n#endif\n}\nvoid phydm_dig_abs_boundary_decision(struct dm_struct *dm, boolean is_dfs_band)\n{\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct phydm_adaptivity_struct *adapt = &dm->adaptivity;\n\n\tif (!dm->is_linked) {\n\t\tdig_t->dm_dig_max = DIG_MAX_COVERAGR;\n\t\tdig_t->dm_dig_min = DIG_MIN_COVERAGE;\n\t} else if (is_dfs_band) {\n\t\tif (*dm->band_width == CHANNEL_WIDTH_20)\n\t\t\tdig_t->dm_dig_min = DIG_MIN_DFS + 2;\n\t\telse\n\t\t\tdig_t->dm_dig_min = DIG_MIN_DFS;\n\n\t\tdig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;\n\t\tdig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;\n\t} else {\n\t\tif (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {\n\t\t/*service > 2 devices*/\n\t\t\tdig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;\n\t\t\t#if (DIG_HW == 1)\n\t\t\tdig_t->dig_max_of_min = DIG_MIN_COVERAGE;\n\t\t\t#else\n\t\t\tdig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;\n\t\t\t#endif\n\t\t} else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {\n\t\t/*service 1 devices*/\n\t\t\tif (adapt->is_adapt_en && (dm->support_ic_type &\n\t\t\t    (ODM_RTL8197F | ODM_RTL8192F)))\n\t\t\t/*dig_max shouldn't be too high because of adaptivity*/\n\t\t\t\tdig_t->dm_dig_max =\n\t\t\t\t\tMIN_2((adapt->th_l2h + 40),\n\t\t\t\t\t      DIG_MAX_PERFORMANCE_MODE);\n\t\t\telse\n\t\t\t\tdig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;\n\n\t\t\tdig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;\n\t\t}\n\n\t\tif (dm->support_ic_type &\n\t\t    (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))\n\t\t\tdig_t->dm_dig_min = 0x1c;\n\t\telse if (dm->support_ic_type & ODM_RTL8197F)\n\t\t\tdig_t->dm_dig_min = 0x1e; /*@For HW setting*/\n\t\telse\n\t\t\tdig_t->dm_dig_min = DIG_MIN_PERFORMANCE;\n\t}\n\n\tPHYDM_DBG(dm, DBG_DIG, \"Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\\n\",\n\t\t  dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);\n}\n\nvoid phydm_dig_dym_boundary_decision(struct dm_struct *dm)\n{\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n#ifdef CFG_DIG_DAMPING_CHK\n\tstruct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;\n#endif\n\tu8 offset = 15, tmp_max = 0;\n\tu8 max_of_rssi_min = 0;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"%s ======>\\n\", __func__);\n\n\tif (!dm->is_linked) {\n\t\t/*@if no link, always stay at lower bound*/\n\t\tdig_t->rx_gain_range_max = dig_t->dig_max_of_min;\n\t\tdig_t->rx_gain_range_min = dig_t->dm_dig_min;\n\n\t\tPHYDM_DBG(dm, DBG_DIG, \"No-Link, Dyn{Max, Min}={0x%x, 0x%x}\\n\",\n\t\t\t  dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);\n\t\treturn;\n\t}\n\n\tPHYDM_DBG(dm, DBG_DIG, \"rssi_min=%d, ofst=%d\\n\", dm->rssi_min, offset);\n\n\t/* @DIG lower bound */\n\tif (dm->rssi_min > dig_t->dig_max_of_min)\n\t\tdig_t->rx_gain_range_min = dig_t->dig_max_of_min;\n\telse if (dm->rssi_min < dig_t->dm_dig_min)\n\t\tdig_t->rx_gain_range_min = dig_t->dm_dig_min;\n\telse\n\t\tdig_t->rx_gain_range_min = dm->rssi_min;\n\n#ifdef CFG_DIG_DAMPING_CHK\n\t/*@Limit Dyn min by damping*/\n\tif (dig_t->dig_dl_en &&\n\t    dig_rc->damping_limit_en &&\n\t    dig_t->rx_gain_range_min < dig_rc->damping_limit_val) {\n\t\tPHYDM_DBG(dm, DBG_DIG,\n\t\t\t  \"[Limit by Damping] Dig_dyn_min=0x%x -> 0x%x\\n\",\n\t\t\t  dig_t->rx_gain_range_min, dig_rc->damping_limit_val);\n\n\t\tdig_t->rx_gain_range_min = dig_rc->damping_limit_val;\n\t}\n#endif\n\n\t/* @DIG upper bound */\n\ttmp_max = dig_t->rx_gain_range_min + offset;\n\tif (dig_t->rx_gain_range_min != dm->rssi_min) {\n\t\tmax_of_rssi_min = dm->rssi_min + offset;\n\t\tif (tmp_max > max_of_rssi_min)\n\t\t\ttmp_max = max_of_rssi_min;\n\t}\n\n\tif (tmp_max > dig_t->dm_dig_max)\n\t\tdig_t->rx_gain_range_max = dig_t->dm_dig_max;\n\telse if (tmp_max < dig_t->dm_dig_min)\n\t\tdig_t->rx_gain_range_max = dig_t->dm_dig_min;\n\telse\n\t\tdig_t->rx_gain_range_max = tmp_max;\n\n\t#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\t/* @1 Force Lower Bound for AntDiv */\n\tif (!dm->is_one_entry_only &&\n\t    (dm->support_ability & ODM_BB_ANT_DIV) &&\n\t    (dm->ant_div_type == CG_TRX_HW_ANTDIV ||\n\t     dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {\n\t\tif (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)\n\t\t\tdig_t->rx_gain_range_min = dig_t->dig_max_of_min;\n\t\telse\n\t\t\tdig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;\n\n\t\tPHYDM_DBG(dm, DBG_DIG, \"Force Dyn-Min=0x%x, RSSI_max=0x%x\\n\",\n\t\t\t  dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);\n\t}\n\t#endif\n\n\tPHYDM_DBG(dm, DBG_DIG, \"Dyn{Max, Min}={0x%x, 0x%x}\\n\",\n\t\t  dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);\n}\n\nvoid phydm_dig_abnormal_case(struct dm_struct *dm)\n{\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\n\t/* @Abnormal lower bound case */\n\tif (dig_t->rx_gain_range_min > dig_t->rx_gain_range_max)\n\t\tdig_t->rx_gain_range_min = dig_t->rx_gain_range_max;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"Abnoraml checked {Max, Min}={0x%x, 0x%x}\\n\",\n\t\t  dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);\n}\n\nu8 phydm_new_igi_by_fa(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *step_size)\n{\n\tboolean dig_go_up_check = true;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\n#if 0\n\t/*@dig_go_up_check = phydm_dig_go_up_check(dm);*/\n#endif\n\n\tif (fa_cnt > dig_t->fa_th[2] && dig_go_up_check)\n\t\tigi = igi + step_size[0];\n\telse if ((fa_cnt > dig_t->fa_th[1]) && dig_go_up_check)\n\t\tigi = igi + step_size[1];\n\telse if (fa_cnt < dig_t->fa_th[0])\n\t\tigi = igi - step_size[2];\n\n\treturn igi;\n}\n\nu8 phydm_get_new_igi(struct dm_struct *dm, u8 igi, u32 fa_cnt,\n\t\t     boolean is_dfs_band)\n{\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tu8 step[3] = {0};\n\tboolean first_connect = false, first_dis_connect = false;\n\n\tfirst_connect = (dm->is_linked) && !dig_t->is_media_connect;\n\tfirst_dis_connect = (!dm->is_linked) && dig_t->is_media_connect;\n\n\tif (dm->is_linked) {\n\t\tif (dm->pre_rssi_min <= dm->rssi_min) {\n\t\t\tPHYDM_DBG(dm, DBG_DIG, \"pre_rssi_min <= rssi_min\\n\");\n\t\t\tstep[0] = 2;\n\t\t\tstep[1] = 1;\n\t\t\tstep[2] = 2;\n\t\t} else {\n\t\t\tstep[0] = 4;\n\t\t\tstep[1] = 2;\n\t\t\tstep[2] = 2;\n\t\t}\n\t} else {\n\t\tstep[0] = 2;\n\t\tstep[1] = 1;\n\t\tstep[2] = 2;\n\t}\n\n\tPHYDM_DBG(dm, DBG_DIG, \"step = {-%d, +%d, +%d}\\n\", step[2], step[1],\n\t\t  step[0]);\n\n\tif (first_connect) {\n\t\tif (is_dfs_band) {\n\t\t\tif (dm->rssi_min > DIG_MAX_DFS)\n\t\t\t\tigi = DIG_MAX_DFS;\n\t\t\telse\n\t\t\t\tigi = dm->rssi_min;\n\t\t\tPHYDM_DBG(dm, DBG_DIG, \"DFS band:IgiMax=0x%x\\n\",\n\t\t\t\t  dig_t->rx_gain_range_max);\n\t\t} else {\n\t\t\tigi = dig_t->rx_gain_range_min;\n\t\t}\n\n\t\t#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\t\t#if (RTL8812A_SUPPORT)\n\t\tif (dm->support_ic_type == ODM_RTL8812)\n\t\t\todm_config_bb_with_header_file(dm,\n\t\t\t\t\t\t       CONFIG_BB_AGC_TAB_DIFF);\n\t\t#endif\n\t\t#endif\n\t\tPHYDM_DBG(dm, DBG_DIG, \"First connect: foce IGI=0x%x\\n\", igi);\n\t} else if (dm->is_linked) {\n\t\tPHYDM_DBG(dm, DBG_DIG, \"Adjust IGI @ linked\\n\");\n\t\t/* @4 Abnormal # beacon case */\n\t\t#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\t\tif (dm->phy_dbg_info.num_qry_beacon_pkt < 5 &&\n\t\t    fa_cnt < DM_DIG_FA_TH1 && dm->bsta_state &&\n\t\t    dm->support_ic_type != ODM_RTL8723D) {\n\t\t\tdig_t->rx_gain_range_min = 0x1c;\n\t\t\tigi = dig_t->rx_gain_range_min;\n\t\t\tPHYDM_DBG(dm, DBG_DIG, \"Beacon_num=%d,force igi=0x%x\\n\",\n\t\t\t\t  dm->phy_dbg_info.num_qry_beacon_pkt, igi);\n\t\t} else {\n\t\t\tigi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);\n\t\t}\n\t\t#else\n\t\tigi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);\n\t\t#endif\n\t} else {\n\t\t/* @2 Before link */\n\t\tPHYDM_DBG(dm, DBG_DIG, \"Adjust IGI before link\\n\");\n\n\t\tif (first_dis_connect) {\n\t\t\tigi = dig_t->dm_dig_min;\n\t\t\tPHYDM_DBG(dm, DBG_DIG,\n\t\t\t\t  \"First disconnect:foce IGI to lower bound\\n\");\n\t\t} else {\n\t\t\tPHYDM_DBG(dm, DBG_DIG, \"Pre_IGI=((0x%x)), FA=((%d))\\n\",\n\t\t\t\t  igi, fa_cnt);\n\n\t\t\tigi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);\n\t\t}\n\t}\n\n\t/*@Check IGI by dyn-upper/lower bound */\n\tif (igi < dig_t->rx_gain_range_min)\n\t\tigi = dig_t->rx_gain_range_min;\n\n\tif (igi > dig_t->rx_gain_range_max)\n\t\tigi = dig_t->rx_gain_range_max;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"fa_cnt = %d, IGI: 0x%x -> 0x%x\\n\",\n\t\t  fa_cnt, dig_t->cur_ig_value, igi);\n\n\treturn igi;\n}\n\nboolean phydm_dig_dfs_mode_en(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tboolean dfs_mode_en = false;\n\n\t/* @Modify lower bound for DFS band */\n\tif (dm->is_dfs_band) {\n\t\t#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\t\tdfs_mode_en = true;\n\t\t#else\n\t\tif (phydm_dfs_master_enabled(dm))\n\t\t\tdfs_mode_en = true;\n\t\t#endif\n\t\tPHYDM_DBG(dm, DBG_DIG, \"In DFS band\\n\");\n\t}\n\treturn dfs_mode_en;\n}\n\nvoid phydm_dig(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;\n#ifdef PHYDM_TDMA_DIG_SUPPORT\n\tstruct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;\n#endif\n\tboolean first_connect, first_disconnect;\n\tu8 igi = dig_t->cur_ig_value;\n\tu8 new_igi = 0x20;\n\tu32 fa_cnt = falm_cnt->cnt_all;\n\tboolean dfs_mode_en = false;\n\n#ifdef PHYDM_TDMA_DIG_SUPPORT\n\tif (!(dm->original_dig_restore)) {\n\t\tif (dig_t->cur_ig_value_tdma == 0)\n\t\t\tdig_t->cur_ig_value_tdma = dig_t->cur_ig_value;\n\n\t\tigi = dig_t->cur_ig_value_tdma;\n\t\tfa_cnt = falm_cnt_acc->cnt_all_1sec;\n\t}\n#endif\n\n\tif (phydm_dig_abort(dm)) {\n\t\tdig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);\n\t\treturn;\n\t}\n\n\tPHYDM_DBG(dm, DBG_DIG, \"%s Start===>\\n\", __func__);\n\n\t/* @1 Update status */\n\tfirst_connect = (dm->is_linked) && !dig_t->is_media_connect;\n\tfirst_disconnect = (!dm->is_linked) && dig_t->is_media_connect;\n\n\tPHYDM_DBG(dm, DBG_DIG,\n\t\t  \"is_linked=%d, RSSI=%d, 1stConnect=%d, 1stDisconnect=%d\\n\",\n\t\t  dm->is_linked, dm->rssi_min, first_connect, first_disconnect);\n\n\tPHYDM_DBG(dm, DBG_DIG, \"DIG ((%s)) mode\\n\",\n\t\t  (*dm->bb_op_mode ? \"Balance\" : \"Performance\"));\n\n\t/*@DFS mode enable check*/\n\tdfs_mode_en = phydm_dig_dfs_mode_en(dm);\n\n#ifdef CFG_DIG_DAMPING_CHK\n\t/*Record IGI History*/\n\tphydm_dig_recorder(dm, first_connect, igi, fa_cnt);\n\n\t/*@DIG Damping Check*/\n\tphydm_dig_damping_chk(dm);\n#endif\n\n\t/*@Absolute Boundary Decision */\n\tphydm_dig_abs_boundary_decision(dm, dfs_mode_en);\n\n\t/*@Dynamic Boundary Decision*/\n\tphydm_dig_dym_boundary_decision(dm);\n\n\t/*@Abnormal case check*/\n\tphydm_dig_abnormal_case(dm);\n\n\t/*@FA threshold decision */\n\tphydm_fa_threshold_check(dm, dfs_mode_en);\n\n\t/*Select new IGI by FA */\n\tnew_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);\n\n\t/* @1 Update status */\n\t#ifdef PHYDM_TDMA_DIG_SUPPORT\n\tif (!(dm->original_dig_restore)) {\n\t\tdig_t->cur_ig_value_tdma = new_igi;\n\t\t/*@It is possible fa_acc_1sec_tsf >= */\n\t\t/*@1sec while tdma_dig_state == 0*/\n\t\tif (dig_t->tdma_dig_state != 0)\n\t\t\todm_write_dig(dm, dig_t->cur_ig_value_tdma);\n\t} else\n\t#endif\n\t\todm_write_dig(dm, new_igi);\n\n\tdig_t->is_media_connect = dm->is_linked;\n}\n\nvoid phydm_dig_lps_32k(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 current_igi = dm->rssi_min;\n\n\todm_write_dig(dm, current_igi);\n}\n\nvoid phydm_dig_by_rssi_lps(void *dm_void)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fa_struct *falm_cnt;\n\n\tu8 rssi_lower = DIG_MIN_LPS; /* @0x1E or 0x1C */\n\tu8 current_igi = dm->rssi_min;\n\n\tfalm_cnt = &dm->false_alm_cnt;\n\tif (phydm_dig_abort(dm))\n\t\treturn;\n\n\tcurrent_igi = current_igi + RSSI_OFFSET_DIG_LPS;\n\tPHYDM_DBG(dm, DBG_DIG, \"%s==>\\n\", __func__);\n\n\t/* Using FW PS mode to make IGI */\n\t/* @Adjust by  FA in LPS MODE */\n\tif (falm_cnt->cnt_all > DM_DIG_FA_TH2_LPS)\n\t\tcurrent_igi = current_igi + 4;\n\telse if (falm_cnt->cnt_all > DM_DIG_FA_TH1_LPS)\n\t\tcurrent_igi = current_igi + 2;\n\telse if (falm_cnt->cnt_all < DM_DIG_FA_TH0_LPS)\n\t\tcurrent_igi = current_igi - 2;\n\n\t/* @Lower bound checking */\n\n\t/* RSSI Lower bound check */\n\tif ((dm->rssi_min - 10) > DIG_MIN_LPS)\n\t\trssi_lower = (dm->rssi_min - 10);\n\telse\n\t\trssi_lower = DIG_MIN_LPS;\n\n\t/* Upper and Lower Bound checking */\n\tif (current_igi > DIG_MAX_LPS)\n\t\tcurrent_igi = DIG_MAX_LPS;\n\telse if (current_igi < rssi_lower)\n\t\tcurrent_igi = rssi_lower;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"fa_cnt_all=%d, rssi_min=%d, curr_igi=0x%x\\n\",\n\t\t  falm_cnt->cnt_all, dm->rssi_min, current_igi);\n\todm_write_dig(dm, current_igi);\n#endif\n}\n\n/* @3============================================================\n * 3 FASLE ALARM CHECK\n * 3============================================================\n */\nvoid phydm_false_alarm_counter_reg_reset(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;\n#ifdef PHYDM_TDMA_DIG_SUPPORT\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;\n#endif\n\tu32 false_alm_cnt = 0;\n\n#ifdef PHYDM_TDMA_DIG_SUPPORT\n\tif (!(dm->original_dig_restore)) {\n\t\tif (dig_t->cur_ig_value_tdma == 0)\n\t\t\tdig_t->cur_ig_value_tdma = dig_t->cur_ig_value;\n\n\t\tfalse_alm_cnt = falm_cnt_acc->cnt_all_1sec;\n\t} else\n#endif\n\t{\n\t\tfalse_alm_cnt = falm_cnt->cnt_all;\n\t}\n\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t/* @reset CCK FA counter */\n\t\todm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 0);\n\t\todm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 2);\n\n\t\t/* @reset CCK CCA counter */\n\t\todm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 0);\n\t\todm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 2);\n\n\t\t/* @Disable common rx clk gating => WLANBB-1106*/\n\t\todm_set_bb_reg(dm, R_0x1d2c, BIT(31), 0);\n\t\t/* @reset OFDM CCA counter, OFDM FA counter*/\n\t\tphydm_reset_bb_hw_cnt(dm);\n\t\t/* @Enable common rx clk gating => WLANBB-1106*/\n\t\todm_set_bb_reg(dm, R_0x1d2c, BIT(31), 1);\n\t}\n#endif\n#if (ODM_IC_11N_SERIES_SUPPORT)\n\tif (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\t/* @reset false alarm counter registers*/\n\t\todm_set_bb_reg(dm, R_0xc0c, BIT(31), 1);\n\t\todm_set_bb_reg(dm, R_0xc0c, BIT(31), 0);\n\t\todm_set_bb_reg(dm, R_0xd00, BIT(27), 1);\n\t\todm_set_bb_reg(dm, R_0xd00, BIT(27), 0);\n\n\t\t/* @update ofdm counter*/\n\t\t/* @update page C counter*/\n\t\todm_set_bb_reg(dm, R_0xc00, BIT(31), 0);\n\t\t/* @update page D counter*/\n\t\todm_set_bb_reg(dm, R_0xd00, BIT(31), 0);\n\n\t\t/* @reset CCK CCA counter*/\n\t\todm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 0);\n\t\todm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 2);\n\n\t\t/* @reset CCK FA counter*/\n\t\todm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 0);\n\t\todm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 2);\n\n\t\t/* @reset CRC32 counter*/\n\t\todm_set_bb_reg(dm, R_0xf14, BIT(16), 1);\n\t\todm_set_bb_reg(dm, R_0xf14, BIT(16), 0);\n\t}\n#endif /* @#if (ODM_IC_11N_SERIES_SUPPORT) */\n\n#if (ODM_IC_11AC_SERIES_SUPPORT)\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\t#if (RTL8881A_SUPPORT)\n\t\t/* @Reset FA counter by enable/disable OFDM */\n\t\tif ((dm->support_ic_type == ODM_RTL8881A) &&\n\t\t    false_alm_cnt->cnt_ofdm_fail_pre >= 0x7fff) {\n\t\t\t/* reset OFDM */\n\t\t\todm_set_bb_reg(dm, R_0x808, BIT(29), 0);\n\t\t\todm_set_bb_reg(dm, R_0x808, BIT(29), 1);\n\t\t\tfalse_alm_cnt->cnt_ofdm_fail_pre = 0;\n\t\t\tPHYDM_DBG(dm, DBG_FA_CNT, \"Reset FA_cnt\\n\");\n\t\t}\n\t\t#endif /* @#if (RTL8881A_SUPPORT) */\n\n\t\t/* @reset OFDM FA countner */\n\t\todm_set_bb_reg(dm, R_0x9a4, BIT(17), 1);\n\t\todm_set_bb_reg(dm, R_0x9a4, BIT(17), 0);\n\n\t\t/* @reset CCK FA counter */\n\t\todm_set_bb_reg(dm, R_0xa2c, BIT(15), 0);\n\t\todm_set_bb_reg(dm, R_0xa2c, BIT(15), 1);\n\n\t\t/* @reset CCA counter */\n\t\tphydm_reset_bb_hw_cnt(dm);\n\t}\n#endif /* @#if (ODM_IC_11AC_SERIES_SUPPORT) */\n}\n\nvoid phydm_false_alarm_counter_reg_hold(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t/* @hold cck counter */\n\t\todm_set_bb_reg(dm, R_0x1a2c, BIT(12), 1);\n\t\todm_set_bb_reg(dm, R_0x1a2c, BIT(14), 1);\n\t} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\t/*@hold ofdm counter*/\n\t\t/*@hold page C counter*/\n\t\todm_set_bb_reg(dm, R_0xc00, BIT(31), 1);\n\t\t/*@hold page D counter*/\n\t\todm_set_bb_reg(dm, R_0xd00, BIT(31), 1);\n\n\t\t/*@hold cck counter*/\n\t\todm_set_bb_reg(dm, R_0xa2c, BIT(12), 1);\n\t\todm_set_bb_reg(dm, R_0xa2c, BIT(14), 1);\n\t}\n}\n\n#if (ODM_IC_11N_SERIES_SUPPORT)\nvoid phydm_fa_cnt_statistics_n(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fa_struct *fa_t = &dm->false_alm_cnt;\n\tu32 reg = 0;\n\n\tif (!(dm->support_ic_type & ODM_IC_11N_SERIES))\n\t\treturn;\n\n\t/* @hold ofdm & cck counter */\n\tphydm_false_alarm_counter_reg_hold(dm);\n\n\treg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11N, MASKDWORD);\n\tfa_t->cnt_fast_fsync = (reg & 0xffff);\n\tfa_t->cnt_sb_search_fail = ((reg & 0xffff0000) >> 16);\n\n\treg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11N, MASKDWORD);\n\tfa_t->cnt_ofdm_cca = (reg & 0xffff);\n\tfa_t->cnt_parity_fail = ((reg & 0xffff0000) >> 16);\n\n\treg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11N, MASKDWORD);\n\tfa_t->cnt_rate_illegal = (reg & 0xffff);\n\tfa_t->cnt_crc8_fail = ((reg & 0xffff0000) >> 16);\n\n\treg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11N, MASKDWORD);\n\tfa_t->cnt_mcs_fail = (reg & 0xffff);\n\n\tfa_t->cnt_ofdm_fail =\n\t\tfa_t->cnt_parity_fail + fa_t->cnt_rate_illegal +\n\t\tfa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail +\n\t\tfa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail;\n\n\t/* read CCK CRC32 counter */\n\tfa_t->cnt_cck_crc32_error = odm_get_bb_reg(dm, R_0xf84, MASKDWORD);\n\tfa_t->cnt_cck_crc32_ok = odm_get_bb_reg(dm, R_0xf88, MASKDWORD);\n\n\t/* read OFDM CRC32 counter */\n\treg = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11N, MASKDWORD);\n\tfa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16;\n\tfa_t->cnt_ofdm_crc32_ok = reg & 0xffff;\n\n\t/* read HT CRC32 counter */\n\treg = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD);\n\tfa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16;\n\tfa_t->cnt_ht_crc32_ok = reg & 0xffff;\n\n\t/* read VHT CRC32 counter */\n\tfa_t->cnt_vht_crc32_error = 0;\n\tfa_t->cnt_vht_crc32_ok = 0;\n\n\t#if (RTL8723D_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8723D) {\n\t\t/* read HT CRC32 agg counter */\n\t\treg = odm_get_bb_reg(dm, R_0xfb8, MASKDWORD);\n\t\tfa_t->cnt_ht_crc32_error_agg = (reg & 0xffff0000) >> 16;\n\t\tfa_t->cnt_ht_crc32_ok_agg = reg & 0xffff;\n\t}\n\t#endif\n\n\t#if (RTL8188E_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8188E) {\n\t\treg = odm_get_bb_reg(dm, ODM_REG_SC_CNT_11N, MASKDWORD);\n\t\tfa_t->cnt_bw_lsc = (reg & 0xffff);\n\t\tfa_t->cnt_bw_usc = ((reg & 0xffff0000) >> 16);\n\t}\n\t#endif\n\n\treg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_LSB_11N, MASKBYTE0);\n\tfa_t->cnt_cck_fail = reg;\n\n\treg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_MSB_11N, MASKBYTE3);\n\tfa_t->cnt_cck_fail += (reg & 0xff) << 8;\n\n\treg = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11N, MASKDWORD);\n\tfa_t->cnt_cck_cca = ((reg & 0xFF) << 8) | ((reg & 0xFF00) >> 8);\n\n\tfa_t->cnt_all_pre = fa_t->cnt_all;\n\n\tfa_t->cnt_all = fa_t->cnt_fast_fsync +\n\t\t\tfa_t->cnt_sb_search_fail +\n\t\t\tfa_t->cnt_parity_fail +\n\t\t\tfa_t->cnt_rate_illegal +\n\t\t\tfa_t->cnt_crc8_fail +\n\t\t\tfa_t->cnt_mcs_fail +\n\t\t\tfa_t->cnt_cck_fail;\n\n\tfa_t->cnt_cca_all = fa_t->cnt_ofdm_cca + fa_t->cnt_cck_cca;\n\n\tPHYDM_DBG(dm, DBG_FA_CNT,\n\t\t  \"[OFDM FA Detail] Parity_Fail=((%d)), Rate_Illegal=((%d)), CRC8_fail=((%d)), Mcs_fail=((%d)), Fast_Fsync=(( %d )), SBD_fail=((%d))\\n\",\n\t\t  fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,\n\t\t  fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail, fa_t->cnt_fast_fsync,\n\t\t  fa_t->cnt_sb_search_fail);\n}\n#endif\n\n#if (ODM_IC_11AC_SERIES_SUPPORT)\nvoid phydm_fa_cnt_statistics_ac(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fa_struct *fa_t = &dm->false_alm_cnt;\n\tu32 ret_value = 0;\n\tu32 cck_enable = 0;\n\n\tif (!(dm->support_ic_type & ODM_IC_11AC_SERIES))\n\t\treturn;\n\n\tret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11AC, MASKDWORD);\n\tfa_t->cnt_fast_fsync = ((ret_value & 0xffff0000) >> 16);\n\n\tret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11AC, MASKDWORD);\n\tfa_t->cnt_sb_search_fail = (ret_value & 0xffff);\n\n\tret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11AC, MASKDWORD);\n\tfa_t->cnt_parity_fail = (ret_value & 0xffff);\n\tfa_t->cnt_rate_illegal = ((ret_value & 0xffff0000) >> 16);\n\n\tret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11AC, MASKDWORD);\n\tfa_t->cnt_crc8_fail = (ret_value & 0xffff);\n\tfa_t->cnt_mcs_fail = ((ret_value & 0xffff0000) >> 16);\n\n\tret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE5_11AC, MASKDWORD);\n\tfa_t->cnt_crc8_fail_vht = (ret_value & 0xffff) +\n\t\t\t\t  (ret_value & 0xffff0000 >> 16);\n\n\tret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE6_11AC, MASKDWORD);\n\tfa_t->cnt_mcs_fail_vht = (ret_value & 0xffff);\n\n\t/* read OFDM FA counter */\n\tfa_t->cnt_ofdm_fail = odm_get_bb_reg(dm, R_0xf48, MASKLWORD);\n\n\t/* Read CCK FA counter */\n\tfa_t->cnt_cck_fail = odm_get_bb_reg(dm, ODM_REG_CCK_FA_11AC, MASKLWORD);\n\n\t/* read CCK/OFDM CCA counter */\n\tret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD);\n\tfa_t->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16;\n\tfa_t->cnt_cck_cca = ret_value & 0xffff;\n\n\t/* read CCK CRC32 counter */\n\tret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CRC32_CNT_11AC, MASKDWORD);\n\tfa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16;\n\tfa_t->cnt_cck_crc32_ok = ret_value & 0xffff;\n\n\t/* read OFDM CRC32 counter */\n\tret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11AC, MASKDWORD);\n\tfa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;\n\tfa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;\n\n\t/* read HT CRC32 counter */\n\tret_value = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11AC, MASKDWORD);\n\tfa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;\n\tfa_t->cnt_ht_crc32_ok = ret_value & 0xffff;\n\n\t/* read VHT CRC32 counter */\n\tret_value = odm_get_bb_reg(dm, ODM_REG_VHT_CRC32_CNT_11AC, MASKDWORD);\n\tfa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16;\n\tfa_t->cnt_vht_crc32_ok = ret_value & 0xffff;\n\n\t#if (RTL8881A_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8881A) {\n\t\tu32 tmp = 0;\n\n\t\tif (fa_t->cnt_ofdm_fail >= fa_t->cnt_ofdm_fail_pre) {\n\t\t\ttmp = fa_t->cnt_ofdm_fail_pre;\n\t\t\tfa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;\n\t\t\tfa_t->cnt_ofdm_fail = fa_t->cnt_ofdm_fail - tmp;\n\t\t} else {\n\t\t\tfa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;\n\t\t}\n\n\t\tPHYDM_DBG(dm, DBG_FA_CNT,\n\t\t\t  \"[8881]cnt_ofdm_fail{curr,pre}={%d,%d}\\n\",\n\t\t\t  fa_t->cnt_ofdm_fail_pre, tmp);\n\t}\n\t#endif\n\n\tcck_enable = odm_get_bb_reg(dm, ODM_REG_BB_RX_PATH_11AC, BIT(28));\n\n\tif (cck_enable) { /* @if(*dm->band_type == ODM_BAND_2_4G) */\n\t\tfa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail;\n\t\tfa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;\n\t} else {\n\t\tfa_t->cnt_all = fa_t->cnt_ofdm_fail;\n\t\tfa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;\n\t}\n}\n#endif\n\nvoid phydm_get_dbg_port_info(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fa_struct *fa_t = &dm->false_alm_cnt;\n\tu32 dbg_port = dm->adaptivity.adaptivity_dbg_port;\n\tu32 val = 0;\n\n\t/*set debug port to 0x0*/\n\tif (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) {\n\t\tfa_t->dbg_port0 = phydm_get_bb_dbg_port_val(dm);\n\t\tphydm_release_bb_dbg_port(dm);\n\t}\n\n\tif (dm->support_ic_type & ODM_RTL8723D) {\n\t\tval = odm_get_bb_reg(dm, R_0x9a0, BIT(29));\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tval = odm_get_bb_reg(dm, R_0x2d38, BIT(24));\n\t} else if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, dbg_port)) {\n\t\tif (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E))\n\t\t\tval = (phydm_get_bb_dbg_port_val(dm) & BIT(30)) >> 30;\n\t\telse\n\t\t\tval = (phydm_get_bb_dbg_port_val(dm) & BIT(29)) >> 29;\n\t\tphydm_release_bb_dbg_port(dm);\n\t}\n\n\tfa_t->edcca_flag = (boolean)val;\n\n\tPHYDM_DBG(dm, DBG_FA_CNT, \"FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\\n\\n\",\n\t\t  fa_t->dbg_port0, fa_t->edcca_flag);\n}\n\nvoid phydm_false_alarm_counter_statistics(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fa_struct *fa_t = &dm->false_alm_cnt;\n\n\tif (!(dm->support_ability & ODM_BB_FA_CNT))\n\t\treturn;\n\n\tPHYDM_DBG(dm, DBG_FA_CNT, \"%s======>\\n\", __func__);\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\tphydm_fa_cnt_statistics_jgr3(dm);\n\t\t#endif\n\t} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\t#if (ODM_IC_11N_SERIES_SUPPORT)\n\t\tphydm_fa_cnt_statistics_n(dm);\n\t\t#endif\n\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\t#if (ODM_IC_11AC_SERIES_SUPPORT)\n\t\tphydm_fa_cnt_statistics_ac(dm);\n\t\t#endif\n\t}\n\n\tphydm_get_dbg_port_info(dm);\n\tphydm_false_alarm_counter_reg_reset(dm_void);\n\n\tfa_t->time_fa_all = fa_t->cnt_fast_fsync * 12 +\n\t\t\t    fa_t->cnt_sb_search_fail * 12 +\n\t\t\t    fa_t->cnt_parity_fail * 28 +\n\t\t\t    fa_t->cnt_rate_illegal * 28 +\n\t\t\t    fa_t->cnt_crc8_fail * 36 +\n\t\t\t    fa_t->cnt_crc8_fail_vht * 36 +\n\t\t\t    fa_t->cnt_mcs_fail_vht * 36 +\n\t\t\t    fa_t->cnt_mcs_fail * 32 +\n\t\t\t    fa_t->cnt_cck_fail * 80;\n\n\tfa_t->cnt_crc32_error_all = fa_t->cnt_vht_crc32_error +\n\t\t\t\t    fa_t->cnt_ht_crc32_error +\n\t\t\t\t    fa_t->cnt_ofdm_crc32_error +\n\t\t\t\t    fa_t->cnt_cck_crc32_error;\n\n\tfa_t->cnt_crc32_ok_all = fa_t->cnt_vht_crc32_ok +\n\t\t\t\t fa_t->cnt_ht_crc32_ok +\n\t\t\t\t fa_t->cnt_ofdm_crc32_ok +\n\t\t\t\t fa_t->cnt_cck_crc32_ok;\n\n\tPHYDM_DBG(dm, DBG_FA_CNT,\n\t\t  \"[OFDM FA Detail-1] Parity=((%d)), Rate_Illegal=((%d)), HT_CRC8=((%d)), HT_MCS=((%d))\\n\",\n\t\t  fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,\n\t\t  fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail);\n\tPHYDM_DBG(dm, DBG_FA_CNT,\n\t\t  \"[OFDM FA Detail-2] Fast_Fsync=((%d)), SBD=((%d)), VHT_CRC8=((%d)), VHT_MCS=((%d))\\n\",\n\t\t  fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail,\n\t\t  fa_t->cnt_crc8_fail_vht, fa_t->cnt_mcs_fail_vht);\n\tPHYDM_DBG(dm, DBG_FA_CNT,\n\t\t  \"[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\\n\",\n\t\t  fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);\n\tPHYDM_DBG(dm, DBG_FA_CNT,\n\t\t  \"[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\\n\",\n\t\t  fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all);\n\tPHYDM_DBG(dm, DBG_FA_CNT, \"[CCK]  CRC32 {error, ok}= {%d, %d}\\n\",\n\t\t  fa_t->cnt_cck_crc32_error, fa_t->cnt_cck_crc32_ok);\n\tPHYDM_DBG(dm, DBG_FA_CNT, \"[OFDM]CRC32 {error, ok}= {%d, %d}\\n\",\n\t\t  fa_t->cnt_ofdm_crc32_error, fa_t->cnt_ofdm_crc32_ok);\n\tPHYDM_DBG(dm, DBG_FA_CNT, \"[ HT ]  CRC32 {error, ok}= {%d, %d}\\n\",\n\t\t  fa_t->cnt_ht_crc32_error, fa_t->cnt_ht_crc32_ok);\n\tPHYDM_DBG(dm, DBG_FA_CNT, \"[VHT]  CRC32 {error, ok}= {%d, %d}\\n\",\n\t\t  fa_t->cnt_vht_crc32_error, fa_t->cnt_vht_crc32_ok);\n\tPHYDM_DBG(dm, DBG_FA_CNT, \"[TOTAL]  CRC32 {error, ok}= {%d, %d}\\n\",\n\t\t  fa_t->cnt_crc32_error_all, fa_t->cnt_crc32_ok_all);\n}\n\n#ifdef PHYDM_TDMA_DIG_SUPPORT\nvoid phydm_set_tdma_dig_timer(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 delta_time_us = dm->tdma_dig_timer_ms * 1000;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tu32 timeout = 0;\n\tu32 current_time_stamp, diff_time_stamp, regb0 = 0;\n\n\t/*some IC has no FREERUN_CUNT register, like 92E*/\n\tif (dm->support_ic_type & ODM_RTL8197F)\n\t\tcurrent_time_stamp = odm_get_bb_reg(dm, R_0x568, 0xffffffff);\n\telse\n\t\treturn;\n\n\ttimeout = current_time_stamp + delta_time_us;\n\n\tdiff_time_stamp = current_time_stamp - dig_t->cur_timestamp;\n\tdig_t->pre_timestamp = dig_t->cur_timestamp;\n\tdig_t->cur_timestamp = current_time_stamp;\n\n\t/*@HIMR0, it shows HW interrupt mask*/\n\tregb0 = odm_get_bb_reg(dm, R_0xb0, 0xffffffff);\n\n\tPHYDM_DBG(dm, DBG_DIG, \"Set next timer\\n\");\n\tPHYDM_DBG(dm, DBG_DIG,\n\t\t  \"curr_time_stamp=%d, delta_time_us=%d\\n\",\n\t\t  current_time_stamp, delta_time_us);\n\tPHYDM_DBG(dm, DBG_DIG,\n\t\t  \"timeout=%d, diff_time_stamp=%d, Reg0xb0 = 0x%x\\n\",\n\t\t  timeout, diff_time_stamp, regb0);\n\n\tif (dm->support_ic_type & ODM_RTL8197F) /*REG_PS_TIMER2*/\n\t\todm_set_bb_reg(dm, R_0x588, 0xffffffff, timeout);\n\telse {\n\t\tPHYDM_DBG(dm, DBG_DIG, \"NOT 97F, NOT start\\n\");\n\t\treturn;\n\t}\n}\n\nvoid phydm_tdma_dig_timer_check(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"tdma_dig_cnt=%d, pre_tdma_dig_cnt=%d\\n\",\n\t\t  dig_t->tdma_dig_cnt, dig_t->pre_tdma_dig_cnt);\n\n\tif (dig_t->tdma_dig_cnt == 0 ||\n\t    dig_t->tdma_dig_cnt == dig_t->pre_tdma_dig_cnt) {\n\t\tif (dm->support_ability & ODM_BB_DIG) {\n#ifdef IS_USE_NEW_TDMA\n\t\t\tif (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B |\n\t\t\t    ODM_RTL8812F | ODM_RTL8822B | ODM_RTL8192F |\n\t\t\t    ODM_RTL8821C | ODM_RTL8197G | ODM_RTL8822C |\n\t\t\t    ODM_RTL8723D)) {\n\t\t\t\tPHYDM_DBG(dm, DBG_DIG,\n\t\t\t\t\t  \"Check fail, Restart timer\\n\\n\");\n\t\t\t\tphydm_false_alarm_counter_reset(dm);\n\t\t\t\todm_set_timer(dm, &dm->tdma_dig_timer,\n\t\t\t\t\t      dm->tdma_dig_timer_ms);\n\t\t\t} else {\n\t\t\t\tPHYDM_DBG(dm, DBG_DIG,\n\t\t\t\t\t  \"Not support TDMADIG, no SW timer\\n\");\n\t\t\t}\n#else\n\t\t\t/*@if interrupt mask info is got.*/\n\t\t\t/*Reg0xb0 is no longer needed*/\n#if 0\n\t\t\t/*regb0 = odm_get_bb_reg(dm, R_0xb0, bMaskDWord);*/\n#endif\n\t\t\tPHYDM_DBG(dm, DBG_DIG,\n\t\t\t\t  \"Check fail, Mask[0]=0x%x, restart timer\\n\",\n\t\t\t\t  *dm->interrupt_mask);\n\n\t\t\tphydm_tdma_dig_add_interrupt_mask_handler(dm);\n\t\t\tphydm_enable_rx_related_interrupt_handler(dm);\n\t\t\tphydm_set_tdma_dig_timer(dm);\n#endif\n\t\t}\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_DIG, \"Check pass, update pre_tdma_dig_cnt\\n\");\n\t}\n\n\tdig_t->pre_tdma_dig_cnt = dig_t->tdma_dig_cnt;\n}\n\n/*@different IC/team may use different timer for tdma-dig*/\nvoid phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n#if (DM_ODM_SUPPORT_TYPE == (ODM_AP))\n\tif (dm->support_ic_type & ODM_RTL8197F) {\n\t\t/*@HAL_INT_TYPE_PSTIMEOUT2*/\n\t\tphydm_add_interrupt_mask_handler(dm, HAL_INT_TYPE_PSTIMEOUT2);\n\t}\n#elif (DM_ODM_SUPPORT_TYPE == (ODM_WIN))\n#elif (DM_ODM_SUPPORT_TYPE == (ODM_CE))\n#endif\n}\n\n/* will be triggered by HW timer*/\nvoid phydm_tdma_dig(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;\n\tu32 reg_c50 = 0;\n\n#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\\\n\tRTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8821C_SUPPORT)\n#ifdef IS_USE_NEW_TDMA\n\tif (dm->support_ic_type &\n\t    (ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8822B |\n\t     ODM_RTL8192F | ODM_RTL8821C)) {\n\t\tPHYDM_DBG(dm, DBG_DIG, \"98F/14B/12F/22B/92F/21C, new tdma\\n\");\n\t\treturn;\n\t}\n#endif\n#endif\n\treg_c50 = odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);\n\n\tdig_t->tdma_dig_state =\n\t\tdig_t->tdma_dig_cnt % dm->tdma_dig_state_number;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"tdma_dig_state=%d, regc50=0x%x\\n\",\n\t\t  dig_t->tdma_dig_state, reg_c50);\n\n\tdig_t->tdma_dig_cnt++;\n\n\tif (dig_t->tdma_dig_state == 1) {\n\t\t/* update IGI from tdma_dig_state == 0*/\n\t\tif (dig_t->cur_ig_value_tdma == 0)\n\t\t\tdig_t->cur_ig_value_tdma = dig_t->cur_ig_value;\n\n\t\todm_write_dig(dm, dig_t->cur_ig_value_tdma);\n\t\tphydm_tdma_false_alarm_counter_check(dm);\n\t\tPHYDM_DBG(dm, DBG_DIG, \"tdma_dig_state=%d, reset FA counter\\n\",\n\t\t\t  dig_t->tdma_dig_state);\n\n\t} else if (dig_t->tdma_dig_state == 0) {\n\t\t/* update dig_t->CurIGValue,*/\n\t\t/* @it may different from dig_t->cur_ig_value_tdma */\n\t\t/* TDMA IGI upperbond @ L-state = */\n\t\t/* rf_ft_var.tdma_dig_low_upper_bond = 0x26 */\n\n\t\tif (dig_t->cur_ig_value >= dm->tdma_dig_low_upper_bond)\n\t\t\tdig_t->low_ig_value = dm->tdma_dig_low_upper_bond;\n\t\telse\n\t\t\tdig_t->low_ig_value = dig_t->cur_ig_value;\n\n\t\todm_write_dig(dm, dig_t->low_ig_value);\n\t\tphydm_tdma_false_alarm_counter_check(dm);\n\t} else {\n\t\tphydm_tdma_false_alarm_counter_check(dm);\n\t}\n}\n\n/*@============================================================*/\n/*@FASLE ALARM CHECK*/\n/*@============================================================*/\nvoid phydm_tdma_false_alarm_counter_check(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;\n\tstruct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tboolean rssi_dump_en = 0;\n\tu32 timestamp = 0;\n\tu8 tdma_dig_state_number = 0;\n\tu32 start_th = 0;\n\n\tif (dig_t->tdma_dig_state == 1)\n\t\tphydm_false_alarm_counter_reset(dm);\n\t/* Reset FalseAlarmCounterStatistics */\n\t/* @fa_acc_1sec_tsf = fa_acc_1sec_tsf, keep */\n\t/* @fa_end_tsf = fa_start_tsf = TSF */\n\telse {\n\t\tphydm_false_alarm_counter_statistics(dm);\n\t\tif (dm->support_ic_type & ODM_RTL8197F) /*REG_FREERUN_CNT*/\n\t\t\ttimestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);\n\t\telse {\n\t\t\tPHYDM_DBG(dm, DBG_DIG, \"NOT 97F! NOT start\\n\");\n\t\t\treturn;\n\t\t}\n\t\tdig_t->fa_end_timestamp = timestamp;\n\t\tdig_t->fa_acc_1sec_timestamp +=\n\t\t\t(dig_t->fa_end_timestamp - dig_t->fa_start_timestamp);\n\n\t\t/*prevent dumb*/\n\t\tif (dm->tdma_dig_state_number == 1)\n\t\t\tdm->tdma_dig_state_number = 2;\n\n\t\ttdma_dig_state_number = dm->tdma_dig_state_number;\n\t\tdig_t->sec_factor =\n\t\t\ttdma_dig_state_number / (tdma_dig_state_number - 1);\n\n\t\t/*@1sec = 1000000us*/\n\t\tif (dig_t->sec_factor)\n\t\t\tstart_th = (u32)(1000000 / dig_t->sec_factor);\n\n\t\tif (dig_t->fa_acc_1sec_timestamp >= start_th) {\n\t\t\trssi_dump_en = 1;\n\t\t\tphydm_false_alarm_counter_acc(dm, rssi_dump_en);\n\t\t\tPHYDM_DBG(dm, DBG_DIG,\n\t\t\t\t  \"sec_factor=%d, total FA=%d, is_linked=%d\\n\",\n\t\t\t\t  dig_t->sec_factor, falm_cnt_acc->cnt_all,\n\t\t\t\t  dm->is_linked);\n\n\t\t\tphydm_noisy_detection(dm);\n\t\t\t#ifdef PHYDM_SUPPORT_CCKPD\n\t\t\tphydm_cck_pd_th(dm);\n\t\t\t#endif\n\t\t\tphydm_dig(dm);\n\t\t\tphydm_false_alarm_counter_acc_reset(dm);\n\n\t\t\t/* Reset FalseAlarmCounterStatistics */\n\t\t\t/* @fa_end_tsf = fa_start_tsf = TSF, keep */\n\t\t\t/* @fa_acc_1sec_tsf = 0 */\n\t\t\tphydm_false_alarm_counter_reset(dm);\n\t\t} else {\n\t\t\tphydm_false_alarm_counter_acc(dm, rssi_dump_en);\n\t\t}\n\t}\n}\n\nvoid phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;\n\tstruct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\n\tfalm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;\n\tfalm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;\n\tfalm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;\n\tfalm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;\n\tfalm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;\n\tfalm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;\n\tfalm_cnt_acc->cnt_all += falm_cnt->cnt_all;\n\tfalm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;\n\tfalm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;\n\tfalm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;\n\tfalm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;\n\tfalm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;\n\tfalm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;\n\tfalm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;\n\tfalm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;\n\tfalm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;\n\tfalm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;\n\tfalm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;\n\tfalm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;\n\tfalm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;\n\tfalm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;\n\tfalm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;\n\n\tif (rssi_dump_en == 1) {\n\t\tfalm_cnt_acc->cnt_all_1sec =\n\t\t\tfalm_cnt_acc->cnt_all * dig_t->sec_factor;\n\t\tfalm_cnt_acc->cnt_cca_all_1sec =\n\t\t\tfalm_cnt_acc->cnt_cca_all * dig_t->sec_factor;\n\t\tfalm_cnt_acc->cnt_cck_fail_1sec =\n\t\t\tfalm_cnt_acc->cnt_cck_fail * dig_t->sec_factor;\n\t}\n}\n\nvoid phydm_false_alarm_counter_acc_reset(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fa_acc_struct *falm_cnt_acc = NULL;\n\n#ifdef IS_USE_NEW_TDMA\n\tstruct phydm_fa_acc_struct *falm_cnt_acc_low = NULL;\n\tu32 tmp_cca_1sec = 0;\n\tu32 tmp_fa_1sec = 0;\n\n\t/*@clear L-fa_acc struct*/\n\tfalm_cnt_acc_low = &dm->false_alm_cnt_acc_low;\n\ttmp_cca_1sec = falm_cnt_acc_low->cnt_cca_all_1sec;\n\ttmp_fa_1sec = falm_cnt_acc_low->cnt_all_1sec;\n\todm_memory_set(dm, falm_cnt_acc_low, 0, sizeof(dm->false_alm_cnt_acc));\n\tfalm_cnt_acc_low->cnt_cca_all_1sec = tmp_cca_1sec;\n\tfalm_cnt_acc_low->cnt_all_1sec = tmp_fa_1sec;\n\n\t/*@clear H-fa_acc struct*/\n\tfalm_cnt_acc = &dm->false_alm_cnt_acc;\n\ttmp_cca_1sec = falm_cnt_acc->cnt_cca_all_1sec;\n\ttmp_fa_1sec = falm_cnt_acc->cnt_all_1sec;\n\todm_memory_set(dm, falm_cnt_acc, 0, sizeof(dm->false_alm_cnt_acc));\n\tfalm_cnt_acc->cnt_cca_all_1sec = tmp_cca_1sec;\n\tfalm_cnt_acc->cnt_all_1sec = tmp_fa_1sec;\n#else\n\tfalm_cnt_acc = &dm->false_alm_cnt_acc;\n\t/* @Cnt_all_for_rssi_dump & Cnt_CCA_all_for_rssi_dump */\n\t/* @do NOT need to be reset */\n\todm_memory_set(dm, falm_cnt_acc, 0, sizeof(falm_cnt_acc));\n#endif\n}\n\nvoid phydm_false_alarm_counter_reset(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fa_struct *falm_cnt;\n\tstruct phydm_dig_struct *dig_t;\n\tu32 timestamp;\n\n\tfalm_cnt = &dm->false_alm_cnt;\n\tdig_t = &dm->dm_dig_table;\n\n\tmemset(falm_cnt, 0, sizeof(dm->false_alm_cnt));\n\tphydm_false_alarm_counter_reg_reset(dm);\n\n#ifdef IS_USE_NEW_TDMA\n\treturn;\n#endif\n\tif (dig_t->tdma_dig_state != 1)\n\t\tdig_t->fa_acc_1sec_timestamp = 0;\n\telse\n\t\tdig_t->fa_acc_1sec_timestamp = dig_t->fa_acc_1sec_timestamp;\n\n\t/*REG_FREERUN_CNT*/\n\ttimestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);\n\tdig_t->fa_start_timestamp = timestamp;\n\tdig_t->fa_end_timestamp = timestamp;\n}\n\nvoid phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tswitch (type) {\n\tcase ENABLE_TDMA:\n\t\tdm->original_dig_restore = !((boolean)input);\n\t\tbreak;\n\tcase MODE_DECISION:\n\t\tif (input == MODE_PERFORMANCE)\n\t\t\tdm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES + 2;\n\t\telse if (input == MODE_COVERAGE)\n\t\t\tdm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;\n\t\telse\n\t\t\tdm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;\n\t\tbreak;\n\t}\n}\n\n#ifdef IS_USE_NEW_TDMA\nvoid phydm_tdma_dig_timers(void *dm_void, u8 state)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\n\tif (state == INIT_TDMA_DIG_TIMMER)\n\t\todm_initialize_timer(dm, &dm->tdma_dig_timer,\n\t\t\t\t     (void *)phydm_tdma_dig_cbk,\n\t\t\t\t     NULL, \"phydm_tdma_dig_timer\");\n\telse if (state == CANCEL_TDMA_DIG_TIMMER)\n\t\todm_cancel_timer(dm, &dm->tdma_dig_timer);\n\telse if (state == RELEASE_TDMA_DIG_TIMMER)\n\t\todm_release_timer(dm, &dm->tdma_dig_timer);\n}\n\nu8 get_new_igi_bound(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *rx_gain_max,\n\t\t     u8 *rx_gain_min, boolean is_dfs_band)\n{\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tu8 step[3] = {0};\n\tu8 cur_igi = igi;\n\tboolean first_connect = false, first_dis_connect = false;\n\n\tfirst_connect = (dm->is_linked) && !dig_t->is_media_connect;\n\tfirst_dis_connect = (!dm->is_linked) && dig_t->is_media_connect;\n\n\tif (dm->is_linked) {\n\t\tif (dm->pre_rssi_min <= dm->rssi_min) {\n\t\t\tPHYDM_DBG(dm, DBG_DIG, \"pre_rssi_min <= rssi_min\\n\");\n\t\t\tstep[0] = 2;\n\t\t\tstep[1] = 1;\n\t\t\tstep[2] = 2;\n\t\t} else {\n\t\t\tstep[0] = 4;\n\t\t\tstep[1] = 2;\n\t\t\tstep[2] = 2;\n\t\t}\n\t} else {\n\t\tstep[0] = 2;\n\t\tstep[1] = 1;\n\t\tstep[2] = 2;\n\t}\n\n\tPHYDM_DBG(dm, DBG_DIG, \"step = {-%d, +%d, +%d}\\n\", step[2], step[1],\n\t\t  step[0]);\n\n\tif (first_connect) {\n\t\tif (is_dfs_band) {\n\t\t\tif (dm->rssi_min > DIG_MAX_DFS)\n\t\t\t\tigi = DIG_MAX_DFS;\n\t\t\telse\n\t\t\t\tigi = dm->rssi_min;\n\t\t\tPHYDM_DBG(dm, DBG_DIG, \"DFS band:IgiMax=0x%x\\n\",\n\t\t\t\t  *rx_gain_max);\n\t\t} else {\n\t\t\tigi = *rx_gain_min;\n\t\t}\n\n\t\t#if 0\n\t\t#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\t\t#if (RTL8812A_SUPPORT)\n\t\tif (dm->support_ic_type == ODM_RTL8812)\n\t\t\todm_config_bb_with_header_file(dm,\n\t\t\t\t\t\t       CONFIG_BB_AGC_TAB_DIFF);\n\t\t#endif\n\t\t#endif\n\t\t#endif\n\t\tPHYDM_DBG(dm, DBG_DIG, \"First connect: foce IGI=0x%x\\n\", igi);\n\t} else {\n\t\t/* @2 Before link */\n\t\tPHYDM_DBG(dm, DBG_DIG, \"Adjust IGI before link\\n\");\n\n\t\tif (first_dis_connect) {\n\t\t\tigi = dig_t->dm_dig_min;\n\t\t\tPHYDM_DBG(dm, DBG_DIG,\n\t\t\t\t  \"First disconnect:foce IGI to lower bound\\n\");\n\t\t} else {\n\t\t\tPHYDM_DBG(dm, DBG_DIG, \"Pre_IGI=((0x%x)), FA=((%d))\\n\",\n\t\t\t\t  igi, fa_cnt);\n\n\t\t\tigi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);\n\t\t}\n\t}\n\t/*@Check IGI by dyn-upper/lower bound */\n\tif (igi < *rx_gain_min)\n\t\tigi = *rx_gain_min;\n\n\tif (igi > *rx_gain_max)\n\t\tigi = *rx_gain_max;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"fa_cnt = %d, IGI: 0x%x -> 0x%x\\n\",\n\t\t  fa_cnt, cur_igi, igi);\n\n\treturn igi;\n}\n\n/*@callback function triggered by SW timer*/\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid phydm_tdma_dig_cbk(struct phydm_timer_list *timer)\n{\n\tvoid *adapter = (void *)timer->Adapter;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\n\tif (phydm_dig_abort(dm) || dm->original_dig_restore)\n\t\treturn;\n\t/*@\n\t *PHYDM_DBG(dm, DBG_DIG, \"timer callback =======> tdma_dig_state=%d\\n\");\n\t *\t  dig_t->tdma_dig_state);\n\t *PHYDM_DBG(dm, DBG_DIG, \"tdma_h_igi=0x%x, tdma_l_igi=0x%x\\n\",\n\t *\t  dig_t->cur_ig_value_tdma,\n\t *\t  dig_t->low_ig_value);\n\t */\n\tphydm_tdma_fa_cnt_chk(dm);\n\n\t/*@prevent dumb*/\n\tif (dm->tdma_dig_state_number < 2)\n\t\tdm->tdma_dig_state_number = 2;\n\n\t/*@update state*/\n\tdig_t->tdma_dig_cnt++;\n\tdig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;\n\n\t/*@\n\t *PHYDM_DBG(dm, DBG_DIG, \"enter state %d, dig count %d\\n\",\n\t *\t  dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);\n\t */\n\n\tif (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)\n\t\todm_write_dig(dm, dig_t->low_ig_value);\n\telse if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)\n\t\todm_write_dig(dm, dig_t->cur_ig_value_tdma);\n\n\todm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);\n}\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\nvoid phydm_tdma_dig_cbk(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tvoid *padapter = dm->adapter;\n\n\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\tphydm_tdma_dig_workitem_callback(dm);\n\t/* @Can't do I/O in timer callback*/\n\telse\n\t\tphydm_run_in_thread_cmd(dm, phydm_tdma_dig_workitem_callback,\n\t\t\t\t\tdm);\n}\n\nvoid phydm_tdma_dig_workitem_callback(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\n\tif (phydm_dig_abort(dm) || (dm->original_dig_restore))\n\t\treturn;\n\t/*@\n\t *PHYDM_DBG(dm, DBG_DIG, \"timer callback =======> tdma_dig_state=%d\\n\");\n\t *\t  dig_t->tdma_dig_state);\n\t *PHYDM_DBG(dm, DBG_DIG, \"tdma_h_igi=0x%x, tdma_l_igi=0x%x\\n\",\n\t *\t  dig_t->cur_ig_value_tdma,\n\t *\t  dig_t->low_ig_value);\n\t */\n\tphydm_tdma_fa_cnt_chk(dm);\n\n\t/*@prevent dumb*/\n\tif (dm->tdma_dig_state_number < 2)\n\t\tdm->tdma_dig_state_number = 2;\n\n\t/*@update state*/\n\tdig_t->tdma_dig_cnt++;\n\tdig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;\n\n\t/*@\n\t *PHYDM_DBG(dm, DBG_DIG, \"enter state %d, dig count %d\\n\",\n\t *\t  dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);\n\t */\n\n\tif (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)\n\t\todm_write_dig(dm, dig_t->low_ig_value);\n\telse if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)\n\t\todm_write_dig(dm, dig_t->cur_ig_value_tdma);\n\n\todm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);\n}\n#else\nvoid phydm_tdma_dig_cbk(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\n\tif (phydm_dig_abort(dm) || dm->original_dig_restore)\n\t\treturn;\n\t/*@\n\t *PHYDM_DBG(dm, DBG_DIG, \"timer callback =======> tdma_dig_state=%d\\n\");\n\t *\t  dig_t->tdma_dig_state);\n\t *PHYDM_DBG(dm, DBG_DIG, \"tdma_h_igi=0x%x, tdma_l_igi=0x%x\\n\",\n\t *\t  dig_t->cur_ig_value_tdma,\n\t *\t  dig_t->low_ig_value);\n\t */\n\tphydm_tdma_fa_cnt_chk(dm);\n\n\t/*@prevent dumb*/\n\tif (dm->tdma_dig_state_number < 2)\n\t\tdm->tdma_dig_state_number = 2;\n\n\t/*@update state*/\n\tdig_t->tdma_dig_cnt++;\n\tdig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;\n\n\t/*@\n\t *PHYDM_DBG(dm, DBG_DIG, \"enter state %d, dig count %d\\n\",\n\t *\t  dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);\n\t */\n\n\tif (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)\n\t\todm_write_dig(dm, dig_t->low_ig_value);\n\telse if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)\n\t\todm_write_dig(dm, dig_t->cur_ig_value_tdma);\n\n\todm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);\n}\n#endif\n/*@============================================================*/\n/*@FASLE ALARM CHECK*/\n/*@============================================================*/\nvoid phydm_tdma_fa_cnt_chk(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;\n\tstruct phydm_fa_acc_struct *fa_t_acc = &dm->false_alm_cnt_acc;\n\tstruct phydm_fa_acc_struct *fa_t_acc_low = &dm->false_alm_cnt_acc_low;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tboolean rssi_dump_en = false;\n\tu32 timestamp = 0;\n\tu8 states_per_block = dm->tdma_dig_state_number;\n\tu8 cur_tdma_dig_state = 0;\n\tu32 start_th = 0;\n\tu8 state_diff = 0;\n\tu32 tdma_dig_block_period_ms = 0;\n\tu32 tdma_dig_block_cnt_thd = 0;\n\tu32 timestamp_diff = 0;\n\n\t/*@calculate duration of a tdma block*/\n\ttdma_dig_block_period_ms = dm->tdma_dig_timer_ms * states_per_block;\n\n\t/*@\n\t *caution!ONE_SEC_MS must be divisible by tdma_dig_block_period_ms,\n\t *or FA will be fewer.\n\t */\n\ttdma_dig_block_cnt_thd = ONE_SEC_MS / tdma_dig_block_period_ms;\n\n\t/*@tdma_dig_state == 0, collect H-state FA, else, collect L-state FA*/\n\tif (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)\n\t\tcur_tdma_dig_state = TDMA_DIG_LOW_STATE;\n\telse if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)\n\t\tcur_tdma_dig_state = TDMA_DIG_HIGH_STATE;\n\t/*@\n\t *PHYDM_DBG(dm, DBG_DIG, \"in state %d, dig count %d\\n\",\n\t *\t  cur_tdma_dig_state, dig_t->tdma_dig_cnt);\n\t */\n\tif (cur_tdma_dig_state == 0) {\n\t\t/*@L-state indicates next block*/\n\t\tdig_t->tdma_dig_block_cnt++;\n\n\t\t/*@1sec dump check*/\n\t\tif (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)\n\t\t\trssi_dump_en = true;\n\n\t\t/*@\n\t\t *PHYDM_DBG(dm, DBG_DIG,\"[L-state] tdma_dig_block_cnt=%d\\n\",\n\t\t *\t  dig_t->tdma_dig_block_cnt);\n\t\t */\n\n\t\t/*@collect FA till this block end*/\n\t\tphydm_false_alarm_counter_statistics(dm);\n\t\tphydm_fa_cnt_acc(dm, rssi_dump_en, cur_tdma_dig_state);\n\t\t/*@1s L-FA collect end*/\n\n\t\t/*@1sec dump reached*/\n\t\tif (rssi_dump_en) {\n\t\t\t/*@L-DIG*/\n\t\t\tphydm_noisy_detection(dm);\n\t\t\t#ifdef PHYDM_SUPPORT_CCKPD\n\t\t\tphydm_cck_pd_th(dm);\n\t\t\t#endif\n\t\t\tPHYDM_DBG(dm, DBG_DIG, \"run tdma L-state dig ====>\\n\");\n\t\t\tphydm_tdma_low_dig(dm);\n\t\t\tPHYDM_DBG(dm, DBG_DIG, \"\\n\\n\");\n\t\t}\n\t} else if (cur_tdma_dig_state == 1) {\n\t\t/*@1sec dump check*/\n\t\tif (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)\n\t\t\trssi_dump_en = true;\n\n\t\t/*@\n\t\t *PHYDM_DBG(dm, DBG_DIG,\"[H-state] tdma_dig_block_cnt=%d\\n\",\n\t\t *\t  dig_t->tdma_dig_block_cnt);\n\t\t */\n\n\t\t/*@collect FA till this block end*/\n\t\tphydm_false_alarm_counter_statistics(dm);\n\t\tphydm_fa_cnt_acc(dm, rssi_dump_en, cur_tdma_dig_state);\n\t\t/*@1s H-FA collect end*/\n\n\t\t/*@1sec dump reached*/\n\t\tstate_diff = dm->tdma_dig_state_number - dig_t->tdma_dig_state;\n\t\tif (rssi_dump_en && (state_diff == 1)) {\n\t\t\t/*@H-DIG*/\n\t\t\tphydm_noisy_detection(dm);\n\t\t\t#ifdef PHYDM_SUPPORT_CCKPD\n\t\t\tphydm_cck_pd_th(dm);\n\t\t\t#endif\n\t\t\tPHYDM_DBG(dm, DBG_DIG, \"run tdma H-state dig ====>\\n\");\n\t\t\tphydm_tdma_high_dig(dm);\n\t\t\tPHYDM_DBG(dm, DBG_DIG, \"\\n\\n\");\n\t\t\tPHYDM_DBG(dm, DBG_DIG, \"1 sec reached, is_linked=%d\\n\",\n\t\t\t\t  dm->is_linked);\n\t\t\tPHYDM_DBG(dm, DBG_DIG, \"1 sec L-CCA=%d, L-FA=%d\\n\",\n\t\t\t\t  fa_t_acc_low->cnt_cca_all_1sec,\n\t\t\t\t  fa_t_acc_low->cnt_all_1sec);\n\t\t\tPHYDM_DBG(dm, DBG_DIG, \"1 sec H-CCA=%d, H-FA=%d\\n\",\n\t\t\t\t  fa_t_acc->cnt_cca_all_1sec,\n\t\t\t\t  fa_t_acc->cnt_all_1sec);\n\t\t\tPHYDM_DBG(dm, DBG_DIG,\n\t\t\t\t  \"1 sec TOTAL-CCA=%d, TOTAL-FA=%d\\n\\n\",\n\t\t\t\t  fa_t_acc->cnt_cca_all +\n\t\t\t\t  fa_t_acc_low->cnt_cca_all,\n\t\t\t\t  fa_t_acc->cnt_all + fa_t_acc_low->cnt_all);\n\n\t\t\t/*@Reset AccFalseAlarmCounterStatistics */\n\t\t\tphydm_false_alarm_counter_acc_reset(dm);\n\t\t\tdig_t->tdma_dig_block_cnt = 0;\n\t\t}\n\t}\n\t/*@Reset FalseAlarmCounterStatistics */\n\tphydm_false_alarm_counter_reset(dm);\n}\n\nvoid phydm_tdma_low_dig(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;\n\tstruct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc_low;\n#ifdef CFG_DIG_DAMPING_CHK\n\tstruct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;\n#endif\n\tboolean first_connect, first_disconnect = false;\n\tu8 igi = dig_t->cur_ig_value;\n\tu8 new_igi = 0x20;\n\tu8 tdma_l_igi = dig_t->low_ig_value;\n\tu8 tdma_l_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE];\n\tu8 tdma_l_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE];\n\tu32 fa_cnt = falm_cnt->cnt_all;\n\tboolean dfs_mode_en = false, is_performance = true;\n\tu8 rssi_min = dm->rssi_min;\n\tu8 igi_upper_rssi_min = 0;\n\tu8 offset = 15;\n\n\tif (!(dm->original_dig_restore)) {\n\t\tif (tdma_l_igi == 0)\n\t\t\ttdma_l_igi = igi;\n\n\t\tfa_cnt = falm_cnt_acc->cnt_all_1sec;\n\t}\n\n\tif (phydm_dig_abort(dm)) {\n\t\tdig_t->low_ig_value = phydm_get_igi(dm, BB_PATH_A);\n\t\treturn;\n\t}\n\n\t/*@Mode Decision*/\n\tdfs_mode_en = false;\n\tis_performance = true;\n\n\t/* @Abs Boundary Decision*/\n\tdig_t->dm_dig_max = DIG_MAX_COVERAGR; //0x26\n\tdig_t->dm_dig_min = DIG_MIN_PERFORMANCE; //0x20\n\tdig_t->dig_max_of_min = DIG_MAX_OF_MIN_COVERAGE; //0x22\n\n\tif (dfs_mode_en) {\n\t\tif (*dm->band_width == CHANNEL_WIDTH_20)\n\t\t\tdig_t->dm_dig_min = DIG_MIN_DFS + 2;\n\t\telse\n\t\t\tdig_t->dm_dig_min = DIG_MIN_DFS;\n\n\t} else {\n\t\t#if 0\n\t\tif (dm->support_ic_type &\n\t\t    (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))\n\t\t\tdig_t->dm_dig_min = 0x1c;\n\t\telse if (dm->support_ic_type & ODM_RTL8197F)\n\t\t\tdig_t->dm_dig_min = 0x1e; /*@For HW setting*/\n\t\t#endif\n\t}\n\n\tPHYDM_DBG(dm, DBG_DIG, \"Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\\n\",\n\t\t  dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);\n\n\t/* @Dyn Boundary by RSSI*/\n\tif (!dm->is_linked) {\n\t\t/*@if no link, always stay at lower bound*/\n\t\ttdma_l_dym_max = 0x26;\n\t\ttdma_l_dym_min = dig_t->dm_dig_min;\n\n\t\tPHYDM_DBG(dm, DBG_DIG, \"No-Link, Dyn{Max, Min}={0x%x, 0x%x}\\n\",\n\t\t\t  tdma_l_dym_max, tdma_l_dym_min);\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_DIG, \"rssi_min=%d, ofst=%d\\n\",\n\t\t\t  dm->rssi_min, offset);\n\n\t\t/* @DIG lower bound in L-state*/\n\t\ttdma_l_dym_min = dig_t->dm_dig_min;\n\n#ifdef CFG_DIG_DAMPING_CHK\n\t\t/*@Limit Dyn min by damping*/\n\t\tif (dig_t->dig_dl_en &&\n\t\t    dig_rc->damping_limit_en &&\n\t\t    tdma_l_dym_min < dig_rc->damping_limit_val) {\n\t\t\tPHYDM_DBG(dm, DBG_DIG,\n\t\t\t\t  \"[Limit by Damping] dyn_min=0x%x -> 0x%x\\n\",\n\t\t\t\t  tdma_l_dym_min, dig_rc->damping_limit_val);\n\n\t\t\ttdma_l_dym_min = dig_rc->damping_limit_val;\n\t\t}\n#endif\n\n\t\t/*@DIG upper bound in L-state*/\n\t\tigi_upper_rssi_min = rssi_min + offset;\n\t\tif (igi_upper_rssi_min > dig_t->dm_dig_max)\n\t\t\ttdma_l_dym_max = dig_t->dm_dig_max;\n\t\telse if (igi_upper_rssi_min < dig_t->dm_dig_min)\n\t\t\ttdma_l_dym_max = dig_t->dm_dig_min;\n\t\telse\n\t\t\ttdma_l_dym_max = igi_upper_rssi_min;\n\n\t\t/* @1 Force Lower Bound for AntDiv */\n\t\t/*@\n\t\t *if (!dm->is_one_entry_only &&\n\t\t *(dm->support_ability & ODM_BB_ANT_DIV) &&\n\t\t *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||\n\t\t *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {\n\t\t *if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)\n\t\t *\tdig_t->rx_gain_range_min = dig_t->dig_max_of_min;\n\t\t *else\n\t\t *\tdig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;\n\t\t *\n\t\t *PHYDM_DBG(dm, DBG_DIG, \"Force Dyn-Min=0x%x, RSSI_max=0x%x\\n\",\n\t\t *\t  dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);\n\t\t *}\n\t\t */\n\n\t\tPHYDM_DBG(dm, DBG_DIG, \"Dyn{Max, Min}={0x%x, 0x%x}\\n\",\n\t\t\t  tdma_l_dym_max, tdma_l_dym_min);\n\t}\n\n\t/*@Abnormal Case Check*/\n\t/*@Abnormal lower bound case*/\n\tif (tdma_l_dym_min > tdma_l_dym_max)\n\t\ttdma_l_dym_min = tdma_l_dym_max;\n\n\tPHYDM_DBG(dm, DBG_DIG,\n\t\t  \"Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\\n\",\n\t\t  tdma_l_dym_max, tdma_l_dym_min);\n\n\t/*@False Alarm Threshold Decision*/\n\tphydm_fa_threshold_check(dm, dfs_mode_en);\n\n\t/*@Adjust Initial Gain by False Alarm*/\n\t/*Select new IGI by FA */\n\tif (!(dm->original_dig_restore)) {\n\t\ttdma_l_igi = get_new_igi_bound(dm, tdma_l_igi, fa_cnt,\n\t\t\t\t\t       &tdma_l_dym_max,\n\t\t\t\t\t       &tdma_l_dym_min,\n\t\t\t\t\t       dfs_mode_en);\n\t} else {\n\t\tnew_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);\n\t}\n\n\t/*Update status*/\n\tif (!(dm->original_dig_restore)) {\n\t\tdig_t->low_ig_value = tdma_l_igi;\n\t\tdig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] = tdma_l_dym_min;\n\t\tdig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = tdma_l_dym_max;\n#if 0\n\t\t/*odm_write_dig(dm, tdma_l_igi);*/\n#endif\n\t} else {\n\t\todm_write_dig(dm, new_igi);\n\t}\n\n\tdig_t->is_media_connect = dm->is_linked;\n}\n\nvoid phydm_tdma_high_dig(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;\n\tstruct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;\n#ifdef CFG_DIG_DAMPING_CHK\n\tstruct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;\n#endif\n\tboolean first_connect, first_disconnect = false;\n\tu8 igi = dig_t->cur_ig_value;\n\tu8 new_igi = 0x20;\n\tu8 tdma_h_igi = dig_t->cur_ig_value_tdma;\n\tu8 tdma_h_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE];\n\tu8 tdma_h_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE];\n\tu32 fa_cnt = falm_cnt->cnt_all;\n\tboolean dfs_mode_en = false, is_performance = true;\n\tu8 rssi_min = dm->rssi_min;\n\tu8 igi_upper_rssi_min = 0;\n\tu8 offset = 15;\n\n\tif (!(dm->original_dig_restore)) {\n\t\tif (tdma_h_igi == 0)\n\t\t\ttdma_h_igi = igi;\n\n\t\tfa_cnt = falm_cnt_acc->cnt_all_1sec;\n\t}\n\n\tif (phydm_dig_abort(dm)) {\n\t\tdig_t->cur_ig_value_tdma = phydm_get_igi(dm, BB_PATH_A);\n\t\treturn;\n\t}\n\n\t/*@Mode Decision*/\n\tdfs_mode_en = false;\n\tis_performance = true;\n\n\t/*@Abs Boundary Decision*/\n\tdig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; // 0x2a\n\n\tif (!dm->is_linked) {\n\t\tdig_t->dm_dig_max = DIG_MAX_COVERAGR;\n\t\tdig_t->dm_dig_min = DIG_MIN_PERFORMANCE; // 0x20\n\t} else if (dfs_mode_en) {\n\t\tif (*dm->band_width == CHANNEL_WIDTH_20)\n\t\t\tdig_t->dm_dig_min = DIG_MIN_DFS + 2;\n\t\telse\n\t\t\tdig_t->dm_dig_min = DIG_MIN_DFS;\n\n\t\tdig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;\n\t\tdig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;\n\t} else {\n\t\tif (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {\n\t\t/*service > 2 devices*/\n\t\t\tdig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;\n\t\t\t#if (DIG_HW == 1)\n\t\t\tdig_t->dig_max_of_min = DIG_MIN_COVERAGE;\n\t\t\t#else\n\t\t\tdig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;\n\t\t\t#endif\n\t\t} else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {\n\t\t/*service 1 devices*/\n\t\t\tdig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;\n\t\t\tdig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;\n\t\t}\n\n\t\t#if 0\n\t\tif (dm->support_ic_type &\n\t\t    (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))\n\t\t\tdig_t->dm_dig_min = 0x1c;\n\t\telse if (dm->support_ic_type & ODM_RTL8197F)\n\t\t\tdig_t->dm_dig_min = 0x1e; /*@For HW setting*/\n\t\telse\n\t\t#endif\n\t\t\tdig_t->dm_dig_min = DIG_MIN_PERFORMANCE;\n\t}\n\tPHYDM_DBG(dm, DBG_DIG, \"Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\\n\",\n\t\t  dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);\n\n\t/*@Dyn Boundary by RSSI*/\n\tif (!dm->is_linked) {\n\t\t/*@if no link, always stay at lower bound*/\n\t\ttdma_h_dym_max = dig_t->dig_max_of_min;\n\t\ttdma_h_dym_min = dig_t->dm_dig_min;\n\n\t\tPHYDM_DBG(dm, DBG_DIG, \"No-Link, Dyn{Max, Min}={0x%x, 0x%x}\\n\",\n\t\t\t  tdma_h_dym_max, tdma_h_dym_min);\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_DIG, \"rssi_min=%d, ofst=%d\\n\",\n\t\t\t  dm->rssi_min, offset);\n\n\t\t/* @DIG lower bound in H-state*/\n\t\tif (rssi_min < dig_t->dm_dig_min)\n\t\t\ttdma_h_dym_min = dig_t->dm_dig_min;\n\t\telse\n\t\t\ttdma_h_dym_min = rssi_min; // turbo not considered yet\n\n#ifdef CFG_DIG_DAMPING_CHK\n\t\t/*@Limit Dyn min by damping*/\n\t\tif (dig_t->dig_dl_en &&\n\t\t    dig_rc->damping_limit_en &&\n\t\t    tdma_h_dym_min < dig_rc->damping_limit_val) {\n\t\t\tPHYDM_DBG(dm, DBG_DIG,\n\t\t\t\t  \"[Limit by Damping] dyn_min=0x%x -> 0x%x\\n\",\n\t\t\t\t  tdma_h_dym_min, dig_rc->damping_limit_val);\n\n\t\t\ttdma_h_dym_min = dig_rc->damping_limit_val;\n\t\t}\n#endif\n\n\t\t/*@DIG upper bound in H-state*/\n\t\tigi_upper_rssi_min = rssi_min + offset;\n\t\tif (igi_upper_rssi_min > dig_t->dm_dig_max)\n\t\t\ttdma_h_dym_max = dig_t->dm_dig_max;\n\t\telse\n\t\t\ttdma_h_dym_max = igi_upper_rssi_min;\n\n\t\t/* @1 Force Lower Bound for AntDiv */\n\t\t/*@\n\t\t *if (!dm->is_one_entry_only &&\n\t\t *(dm->support_ability & ODM_BB_ANT_DIV) &&\n\t\t *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||\n\t\t *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {\n\t\t *\tif (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)\n\t\t *\tdig_t->rx_gain_range_min = dig_t->dig_max_of_min;\n\t\t *\telse\n\t\t *\tdig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;\n\t\t */\n\t\t/*@\n\t\t *PHYDM_DBG(dm, DBG_DIG, \"Force Dyn-Min=0x%x, RSSI_max=0x%x\\n\",\n\t\t *\t  dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);\n\t\t *}\n\t\t */\n\t\tPHYDM_DBG(dm, DBG_DIG, \"Dyn{Max, Min}={0x%x, 0x%x}\\n\",\n\t\t\t  tdma_h_dym_max, tdma_h_dym_min);\n\t}\n\n\t/*@Abnormal Case Check*/\n\t/*@Abnormal low higher bound case*/\n\tif (tdma_h_dym_max < dig_t->dm_dig_min)\n\t\ttdma_h_dym_max = dig_t->dm_dig_min;\n\t/*@Abnormal lower bound case*/\n\tif (tdma_h_dym_min > tdma_h_dym_max)\n\t\ttdma_h_dym_min = tdma_h_dym_max;\n\n\tPHYDM_DBG(dm, DBG_DIG, \"Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\\n\",\n\t\t  tdma_h_dym_max, tdma_h_dym_min);\n\n\t/*@False Alarm Threshold Decision*/\n\tphydm_fa_threshold_check(dm, dfs_mode_en);\n\n\t/*@Adjust Initial Gain by False Alarm*/\n\t/*Select new IGI by FA */\n\tif (!(dm->original_dig_restore)) {\n\t\ttdma_h_igi = get_new_igi_bound(dm, tdma_h_igi, fa_cnt,\n\t\t\t\t\t       &tdma_h_dym_max,\n\t\t\t\t\t       &tdma_h_dym_min,\n\t\t\t\t\t       dfs_mode_en);\n\t} else {\n\t\tnew_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);\n\t}\n\n\t/*Update status*/\n\tif (!(dm->original_dig_restore)) {\n\t\tdig_t->cur_ig_value_tdma = tdma_h_igi;\n\t\tdig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] = tdma_h_dym_min;\n\t\tdig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = tdma_h_dym_max;\n#if 0\n\t\t/*odm_write_dig(dm, tdma_h_igi);*/\n#endif\n\t} else {\n\t\todm_write_dig(dm, new_igi);\n\t}\n\n\tdig_t->is_media_connect = dm->is_linked;\n}\n\nvoid phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en,\n\t\t      u8 cur_tdma_dig_state)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;\n\tstruct phydm_fa_acc_struct *falm_cnt_acc = NULL;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tu8 factor_num = 0;\n\tu8 factor_denum = 1;\n\tu8 total_state_number = 0;\n\n\tif (cur_tdma_dig_state == TDMA_DIG_LOW_STATE)\n\t\tfalm_cnt_acc = &dm->false_alm_cnt_acc_low;\n\telse if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE)\n\n\t\tfalm_cnt_acc = &dm->false_alm_cnt_acc;\n\t/*@\n\t *PHYDM_DBG(dm, DBG_DIG,\n\t *\t  \"[%s] ==> dig_state=%d, one_sec=%d\\n\", __func__,\n\t *\t  cur_tdma_dig_state, rssi_dump_en);\n\t */\n\tfalm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;\n\tfalm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;\n\tfalm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;\n\tfalm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;\n\tfalm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;\n\tfalm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;\n\tfalm_cnt_acc->cnt_all += falm_cnt->cnt_all;\n\tfalm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;\n\tfalm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;\n\tfalm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;\n\tfalm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;\n\tfalm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;\n\tfalm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;\n\tfalm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;\n\tfalm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;\n\tfalm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;\n\tfalm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;\n\tfalm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;\n\tfalm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;\n\tfalm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;\n\tfalm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;\n\tfalm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;\n\n\t/*@\n\t *PHYDM_DBG(dm, DBG_DIG,\n\t *\t\"[CCA Cnt]     {CCK, OFDM, Total} = {%d, %d, %d}\\n\",\n\t *\tfalm_cnt->cnt_cck_cca,\n\t *\tfalm_cnt->cnt_ofdm_cca,\n\t *\tfalm_cnt->cnt_cca_all);\n\t *PHYDM_DBG(dm, DBG_DIG,\n\t *\t\"[FA Cnt]      {CCK, OFDM, Total} = {%d, %d, %d}\\n\",\n\t *\tfalm_cnt->cnt_cck_fail,\n\t *\tfalm_cnt->cnt_ofdm_fail,\n\t *\tfalm_cnt->cnt_all);\n\t */\n\tif (rssi_dump_en == 1) {\n\t\ttotal_state_number = dm->tdma_dig_state_number;\n\n\t\tif (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE) {\n\t\t\tfactor_num = total_state_number;\n\t\t\tfactor_denum = total_state_number - 1;\n\t\t} else if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE) {\n\t\t\tfactor_num = total_state_number;\n\t\t\tfactor_denum = 1;\n\t\t}\n\n\t\tfalm_cnt_acc->cnt_all_1sec =\n\t\t\tfalm_cnt_acc->cnt_all * factor_num / factor_denum;\n\t\tfalm_cnt_acc->cnt_cca_all_1sec =\n\t\t\tfalm_cnt_acc->cnt_cca_all * factor_num / factor_denum;\n\t\tfalm_cnt_acc->cnt_cck_fail_1sec =\n\t\t\tfalm_cnt_acc->cnt_cck_fail * factor_num / factor_denum;\n\n\t\tPHYDM_DBG(dm, DBG_DIG,\n\t\t\t  \"[ACC CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\\n\",\n\t\t\t  falm_cnt_acc->cnt_cck_cca,\n\t\t\t  falm_cnt_acc->cnt_ofdm_cca,\n\t\t\t  falm_cnt_acc->cnt_cca_all);\n\t\tPHYDM_DBG(dm, DBG_DIG,\n\t\t\t  \"[ACC FA Cnt]  {CCK, OFDM, Total} = {%d, %d, %d}\\n\\n\",\n\t\t\t  falm_cnt_acc->cnt_cck_fail,\n\t\t\t  falm_cnt_acc->cnt_ofdm_fail,\n\t\t\t  falm_cnt_acc->cnt_all);\n\n\t}\n}\n#endif /*@#ifdef IS_USE_NEW_TDMA*/\n#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/\n\nvoid phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t     u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tchar help[] = \"-h\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu8 i = 0;\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{0} {en} fa_th[0] fa_th[1] fa_th[2]\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{1} {Damping Limit en}\\n\");\n\t\t#ifdef PHYDM_TDMA_DIG_SUPPORT\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{2} {original_dig_restore = %d}\\n\",\n\t\t\t dm->original_dig_restore);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{3} {tdma_dig_timer_ms = %d}\\n\",\n\t\t\t dm->tdma_dig_timer_ms);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{4} {tdma_dig_state_number = %d}\\n\",\n\t\t\t dm->tdma_dig_state_number);\n\t\t#endif\n\t} else {\n\t\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);\n\n\t\tfor (i = 1; i < 10; i++)\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);\n\n\t\tif (var1[0] == 0) {\n\t\t\tif (var1[1] == 1) {\n\t\t\t\tdig_t->is_dbg_fa_th = true;\n\t\t\t\tdig_t->fa_th[0] = (u16)var1[2];\n\t\t\t\tdig_t->fa_th[1] = (u16)var1[3];\n\t\t\t\tdig_t->fa_th[2] = (u16)var1[4];\n\n\t\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t\t out_len - used,\n\t\t\t\t\t \"Set DIG fa_th[0:2]= {%d, %d, %d}\\n\",\n\t\t\t\t\t dig_t->fa_th[0], dig_t->fa_th[1],\n\t\t\t\t\t dig_t->fa_th[2]);\n\t\t\t} else {\n\t\t\t\tdig_t->is_dbg_fa_th = false;\n\t\t\t}\n\t\t#ifdef PHYDM_TDMA_DIG_SUPPORT\n\t\t} else if (var1[0] == 2) {\n\t\t\tdm->original_dig_restore = (u8)var1[1];\n\t\t\tif (dm->original_dig_restore == 1) {\n\t\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t\t out_len - used, \"Disable TDMA-DIG\\n\");\n\t\t\t} else {\n\t\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t\t out_len - used, \"Enable TDMA-DIG\\n\");\n\t\t\t}\n\t\t} else if (var1[0] == 3) {\n\t\t\tdm->tdma_dig_timer_ms = (u8)var1[1];\n\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t out_len - used, \"tdma_dig_timer_ms = %d\\n\",\n\t\t\t\t dm->tdma_dig_timer_ms);\n\t\t} else if (var1[0] == 4) {\n\t\t\tdm->tdma_dig_state_number = (u8)var1[1];\n\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t out_len - used, \"tdma_dig_state_number = %d\\n\",\n\t\t\t\t dm->tdma_dig_state_number);\n\t\t#endif\n\t\t}\n\n\t\t#ifdef CFG_DIG_DAMPING_CHK\n\t\telse if (var1[0] == 1) {\n\t\t\tdig_t->dig_dl_en = (u8)var1[1];\n\t\t\t/*@*/\n\t\t}\n\t\t#endif\n\t}\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\n#ifdef CONFIG_MCC_DM\n#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT)\nvoid phydm_mcc_igi_clr(void *dm_void, u8 clr_port)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;\n\n\tmcc_dm->mcc_rssi[clr_port] = 0xff;\n\tmcc_dm->mcc_dm_val[0][clr_port] = 0xff; /* 0xc50 clr */\n\tmcc_dm->mcc_dm_val[1][clr_port] = 0xff; /* 0xe50 clr */\n}\n\nvoid phydm_mcc_igi_chk(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;\n\n\tif (mcc_dm->mcc_dm_val[0][0] == 0xff &&\n\t    mcc_dm->mcc_dm_val[0][1] == 0xff) {\n\t\tmcc_dm->mcc_dm_reg[0] = 0xffff;\n\t\tmcc_dm->mcc_reg_id[0] = 0xff;\n\t}\n\tif (mcc_dm->mcc_dm_val[1][0] == 0xff &&\n\t    mcc_dm->mcc_dm_val[1][1] == 0xff) {\n\t\tmcc_dm->mcc_dm_reg[1] = 0xffff;\n\t\tmcc_dm->mcc_reg_id[1] = 0xff;\n\t}\n}\n\nvoid phydm_mcc_igi_cal(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tu8\tshift = 0;\n\tu8\tigi_val0, igi_val1;\n\n\tif (mcc_dm->mcc_rssi[0] == 0xff)\n\t\tphydm_mcc_igi_clr(dm, 0);\n\tif (mcc_dm->mcc_rssi[1] == 0xff)\n\t\tphydm_mcc_igi_clr(dm, 1);\n\tphydm_mcc_igi_chk(dm);\n\tigi_val0 = mcc_dm->mcc_rssi[0] - shift;\n\tigi_val1 = mcc_dm->mcc_rssi[1] - shift;\n\n\tif (igi_val0 < DIG_MIN_PERFORMANCE)\n\t\tigi_val0 = DIG_MIN_PERFORMANCE;\n\n\tif (igi_val1 < DIG_MIN_PERFORMANCE)\n\t\tigi_val1 = DIG_MIN_PERFORMANCE;\n\n\tswitch (dm->ic_ip_series) {\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\tcase PHYDM_IC_JGR3:\n\t\tphydm_fill_mcccmd(dm, 0, R_0x1d70, igi_val0, igi_val1);\n\t\tphydm_fill_mcccmd(dm, 1, R_0x1d70 + 1, igi_val0, igi_val1);\n\t\tbreak;\n\t#endif\n\tdefault:\n\t\tphydm_fill_mcccmd(dm, 0, R_0xc50, igi_val0, igi_val1);\n\t\tphydm_fill_mcccmd(dm, 1, R_0xe50, igi_val0, igi_val1);\n\t\tbreak;\n\t}\n\n\tPHYDM_DBG(dm, DBG_COMP_MCC, \"RSSI_min: %d %d, MCC_igi: %d %d\\n\",\n\t\t  mcc_dm->mcc_rssi[0], mcc_dm->mcc_rssi[1],\n\t\t  mcc_dm->mcc_dm_val[0][0], mcc_dm->mcc_dm_val[0][1]);\n}\n#endif /*#if (RTL8822B_SUPPORT)*/\n#endif /*#ifdef CONFIG_MCC_DM*/\n"
  },
  {
    "path": "hal/phydm/phydm_dig.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDMDIG_H__\n#define __PHYDMDIG_H__\n\n#define DIG_VERSION \"2.3\"\n\n#define\tDIG_HW\t\t0\n#define DIG_LIMIT_PERIOD 60 /*@60 sec*/\n\n/*@--------------------Define ---------------------------------------*/\n\n/*@=== [DIG Boundary] ========================================*/\n/*@DIG coverage mode*/\n#define\tDIG_MAX_COVERAGR\t\t0x26\n#define\tDIG_MIN_COVERAGE\t\t0x1c\n#define\tDIG_MAX_OF_MIN_COVERAGE\t\t0x22\n\n/*@[DIG Balance mode]*/\n#if (DIG_HW == 1)\n#define\tDIG_MAX_BALANCE_MODE\t\t0x32\n#else\n#define\tDIG_MAX_BALANCE_MODE\t\t0x3e\n#endif\n#define\tDIG_MAX_OF_MIN_BALANCE_MODE\t0x2a\n\n/*@[DIG Performance mode]*/\n#define\tDIG_MAX_PERFORMANCE_MODE\t0x5a\n#define\tDIG_MAX_OF_MIN_PERFORMANCE_MODE\t0x40\t/*@[WLANBB-871]*/\n#define\tDIG_MIN_PERFORMANCE\t\t0x20\n\n/*@DIG DFS function*/\n#define\tDIG_MAX_DFS\t\t\t0x28\n#define\tDIG_MIN_DFS\t\t\t0x20\n\n/*@DIG LPS function*/\n#define\tDIG_MAX_LPS\t\t\t0x3e\n#define\tDIG_MIN_LPS\t\t\t0x20\n\n#ifdef PHYDM_TDMA_DIG_SUPPORT\n#define DIG_NUM_OF_TDMA_STATES\t2 /*@L, H state*/\n#define DIG_TIMER_MS\t\t\t250\n#define\tONE_SEC_MS\t\t\t1000\n#endif\n\n/*@=== [DIG FA Threshold] ======================================*/\n\n/*Normal*/\n#define\tDM_DIG_FA_TH0\t\t\t500\n#define\tDM_DIG_FA_TH1\t\t\t750\n\n/*@LPS*/\n#define\tDM_DIG_FA_TH0_LPS\t\t4\t/* @-> 4 lps */\n#define\tDM_DIG_FA_TH1_LPS\t\t15\t/* @-> 15 lps */\n#define\tDM_DIG_FA_TH2_LPS\t\t30\t/* @-> 30 lps */\n\n#define\tRSSI_OFFSET_DIG_LPS\t\t5\n#define DIG_RECORD_NUM\t\t\t4\n\n/*@--------------------Enum-----------------------------------*/\nenum dig_goupcheck_level {\n\tDIG_GOUPCHECK_LEVEL_0,\n\tDIG_GOUPCHECK_LEVEL_1,\n\tDIG_GOUPCHECK_LEVEL_2\n};\n\nenum phydm_dig_mode {\n\tPHYDM_DIG_PERFORAMNCE_MODE\t= 0,\n\tPHYDM_DIG_COVERAGE_MODE\t\t= 1,\n};\n\n#ifdef PHYDM_TDMA_DIG_SUPPORT\nenum upd_type {\n\tENABLE_TDMA,\n\tMODE_DECISION\n};\n\nenum tdma_opmode {\n\tMODE_PERFORMANCE = 1,\n\tMODE_COVERAGE = 2\n};\n\n#ifdef IS_USE_NEW_TDMA\nenum tdma_dig_timer {\n\tINIT_TDMA_DIG_TIMMER,\n\tCANCEL_TDMA_DIG_TIMMER,\n\tRELEASE_TDMA_DIG_TIMMER\n};\n\nenum tdma_dig_state {\n\tTDMA_DIG_LOW_STATE = 0,\n\tTDMA_DIG_HIGH_STATE = 1,\n\tNORMAL_DIG = 2\n};\n#endif\n#endif\n\n/*@--------------------Define Struct-----------------------------------*/\n#ifdef CFG_DIG_DAMPING_CHK\nstruct phydm_dig_recorder_strcut {\n\tu8\t\tigi_bitmap; /*@Don't add any new parameter before this*/\n\tu8\t\tigi_history[DIG_RECORD_NUM];\n\tu32\t\tfa_history[DIG_RECORD_NUM];\n\tu8\t\tdamping_limit_en;\n\tu8\t\tdamping_limit_val; /*@Limit IGI_dyn_min*/\n\tu32\t\tlimit_time;\n\tu8\t\tlimit_rssi;\n};\n#endif\n\nstruct phydm_mcc_dig {\n\tu8\t\tmcc_rssi_A;\n\tu8\t\tmcc_rssi_B;\n};\n\nstruct phydm_dig_struct {\n#ifdef CFG_DIG_DAMPING_CHK\n\tstruct phydm_dig_recorder_strcut dig_recorder_t;\n\tu8\t\tdig_dl_en; /*@damping limit function enable*/\n#endif\n\tboolean\t\tis_dbg_fa_th;\n\tu8\t\tcur_ig_value;\n\tu8\t\trvrt_val;\n\tu8\t\tigi_backup;\n\tu8\t\trx_gain_range_max;\t/*@dig_dynamic_max*/\n\tu8\t\trx_gain_range_min;\t/*@dig_dynamic_min*/\n\tu8\t\tdm_dig_max;\t\t/*@Absolutly upper bound*/\n\tu8\t\tdm_dig_min;\t\t/*@Absolutly lower bound*/\n\tu8\t\tdig_max_of_min;\t\t/*@Absolutly max of min*/\n\tboolean\t\tis_media_connect;\n\tu32\t\tant_div_rssi_max;\n\tu8\t\t*is_p2p_in_process;\n\tenum dig_goupcheck_level\tgo_up_chk_lv;\n\tu16\t\tfa_th[3];\n#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\\\n\tRTL8198F_SUPPORT || RTL8192F_SUPPORT || RTL8195B_SUPPORT ||\\\n\tRTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8721D_SUPPORT ||\\\n\tRTL8812F_SUPPORT || RTL8197G_SUPPORT)\n\tu8\t\trf_gain_idx;\n\tu8\t\tagc_table_idx;\n\tu8\t\tbig_jump_lmt[16];\n\tu8\t\tenable_adjust_big_jump:1;\n\tu8\t\tbig_jump_step1:3;\n\tu8\t\tbig_jump_step2:2;\n\tu8\t\tbig_jump_step3:2;\n#endif\n\tu8\t\tupcheck_init_val;\n\tu8\t\tlv0_ratio_reciprocal;\n\tu8\t\tlv1_ratio_reciprocal;\n#ifdef PHYDM_TDMA_DIG_SUPPORT\n\tu8\t\tcur_ig_value_tdma;\n\tu8\t\tlow_ig_value;\n\tu8\t\ttdma_dig_state;\t/*@To distinguish which state is now.(L-sate or H-state)*/\n\tu8\t\ttdma_dig_cnt;\t/*@for phydm_tdma_dig_timer_check use*/\n\tu8\t\tpre_tdma_dig_cnt;\n\tu8\t\tsec_factor;\n\tu32\t\tcur_timestamp;\n\tu32\t\tpre_timestamp;\n\tu32\t\tfa_start_timestamp;\n\tu32\t\tfa_end_timestamp;\n\tu32\t\tfa_acc_1sec_timestamp;\n#ifdef IS_USE_NEW_TDMA\n\tu8\t\ttdma_dig_block_cnt;/*@for 1 second dump indicator use*/\n\t\t\t/*@dynamic upper bound for L/H state*/\n\tu8\t\ttdma_rx_gain_max[DIG_NUM_OF_TDMA_STATES];\n\t\t\t/*@dynamic lower bound for L/H state*/\n\tu8\t\ttdma_rx_gain_min[DIG_NUM_OF_TDMA_STATES];\n\t\t\t/*To distinguish current state(L-sate or H-state)*/\n#endif\n#endif\n};\n\nstruct phydm_fa_struct {\n\tu32\t\tcnt_parity_fail;\n\tu32\t\tcnt_rate_illegal;\n\tu32\t\tcnt_crc8_fail;\n\tu32\t\tcnt_crc8_fail_vht;\n\tu32\t\tcnt_mcs_fail;\n\tu32\t\tcnt_mcs_fail_vht;\n\tu32\t\tcnt_ofdm_fail;\n\tu32\t\tcnt_ofdm_fail_pre;\t/* @For RTL8881A */\n\tu32\t\tcnt_cck_fail;\n\tu32\t\tcnt_all;\n\tu32\t\tcnt_all_accumulated;\n\tu32\t\tcnt_all_pre;\n\tu32\t\tcnt_fast_fsync;\n\tu32\t\tcnt_sb_search_fail;\n\tu32\t\tcnt_ofdm_cca;\n\tu32\t\tcnt_cck_cca;\n\tu32\t\tcnt_cca_all;\n\tu32\t\tcnt_bw_usc;\n\tu32\t\tcnt_bw_lsc;\n\tu32\t\tcnt_cck_crc32_error;\n\tu32\t\tcnt_cck_crc32_ok;\n\tu32\t\tcnt_ofdm_crc32_error;\n\tu32\t\tcnt_ofdm_crc32_ok;\n\tu32\t\tcnt_ht_crc32_error;\n\tu32\t\tcnt_ht_crc32_ok;\n\tu32\t\tcnt_ht_crc32_error_agg;\n\tu32\t\tcnt_ht_crc32_ok_agg;\n\tu32\t\tcnt_vht_crc32_error;\n\tu32\t\tcnt_vht_crc32_ok;\n\tu32\t\tcnt_crc32_error_all;\n\tu32\t\tcnt_crc32_ok_all;\n\tu32\t\ttime_fa_all;\n\tboolean\t\tcck_block_enable;\n\tboolean\t\tofdm_block_enable;\n\tu32\t\tdbg_port0;\n\tboolean\t\tedcca_flag;\n};\n\n#ifdef PHYDM_TDMA_DIG_SUPPORT\nstruct phydm_fa_acc_struct {\n\tu32\t\tcnt_parity_fail;\n\tu32\t\tcnt_rate_illegal;\n\tu32\t\tcnt_crc8_fail;\n\tu32\t\tcnt_mcs_fail;\n\tu32\t\tcnt_ofdm_fail;\n\tu32\t\tcnt_ofdm_fail_pre;\t/*@For RTL8881A*/\n\tu32\t\tcnt_cck_fail;\n\tu32\t\tcnt_all;\n\tu32\t\tcnt_all_pre;\n\tu32\t\tcnt_fast_fsync;\n\tu32\t\tcnt_sb_search_fail;\n\tu32\t\tcnt_ofdm_cca;\n\tu32\t\tcnt_cck_cca;\n\tu32\t\tcnt_cca_all;\n\tu32\t\tcnt_cck_crc32_error;\n\tu32\t\tcnt_cck_crc32_ok;\n\tu32\t\tcnt_ofdm_crc32_error;\n\tu32\t\tcnt_ofdm_crc32_ok;\n\tu32\t\tcnt_ht_crc32_error;\n\tu32\t\tcnt_ht_crc32_ok;\n\tu32\t\tcnt_vht_crc32_error;\n\tu32\t\tcnt_vht_crc32_ok;\n\tu32\t\tcnt_crc32_error_all;\n\tu32\t\tcnt_crc32_ok_all;\n\tu32\t\tcnt_all_1sec;\n\tu32\t\tcnt_cca_all_1sec;\n\tu32\t\tcnt_cck_fail_1sec;\n};\n\n#endif\t/*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/\n\n/*@--------------------Function declaration-----------------------------*/\nvoid phydm_write_dig_reg(void *dm_void, u8 igi);\n\nvoid odm_write_dig(void *dm_void, u8 current_igi);\n\nu8 phydm_get_igi(void *dm_void, enum bb_path path);\n\nvoid phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len);\n\nvoid odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type,\n\t\t   enum phydm_pause_level pause_level, u8 igi_value);\n\nvoid phydm_dig_init(void *dm_void);\n\nvoid phydm_dig(void *dm_void);\n\nvoid phydm_dig_lps_32k(void *dm_void);\n\nvoid phydm_dig_by_rssi_lps(void *dm_void);\n\nvoid phydm_false_alarm_counter_statistics(void *dm_void);\n\n#ifdef PHYDM_TDMA_DIG_SUPPORT\nvoid phydm_set_tdma_dig_timer(void *dm_void);\n\nvoid phydm_tdma_dig_timer_check(void *dm_void);\n\nvoid phydm_tdma_dig(void *dm_void);\n\nvoid phydm_tdma_false_alarm_counter_check(void *dm_void);\n\nvoid phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void);\n\nvoid phydm_false_alarm_counter_reset(void *dm_void);\n\nvoid phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en);\n\nvoid phydm_false_alarm_counter_acc_reset(void *dm_void);\n\nvoid phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input);\n\n#ifdef IS_USE_NEW_TDMA\nvoid phydm_tdma_dig_timers(void *dm_void, u8 state);\n\nvoid phydm_tdma_dig_cbk(void *dm_void);\n\nvoid phydm_tdma_dig_workitem_callback(void *dm_void);\n\nvoid phydm_tdma_fa_cnt_chk(void *dm_void);\n\nvoid phydm_tdma_low_dig(void *dm_void);\n\nvoid phydm_tdma_high_dig(void *dm_void);\n\nvoid phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en,\n\t\t      u8 cur_tdma_dig_state);\n#endif /*@#ifdef IS_USE_NEW_TDMA*/\n#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/\n\nvoid phydm_set_ofdm_agc_tab(void *dm_void, u8 tab_sel);\n\nvoid phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t     u32 *_out_len);\n\n#ifdef CONFIG_MCC_DM\nvoid phydm_mcc_igi_cal(void *dm_void);\n#endif\n\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_direct_bf.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n ***************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n#ifdef CONFIG_DIRECTIONAL_BF\n#ifdef PHYDM_COMPILE_IC_2SS\nvoid phydm_iq_gen_en(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tenum rf_path i = RF_PATH_A;\n\tenum rf_path path = RF_PATH_A;\n\n\t#if (ODM_IC_11AC_SERIES_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8822B) {\n\t\tfor (i = RF_PATH_A; i <= RF_PATH_B; i++) {\n\t\t\t/*RF mode table write enable*/\n\t\t\todm_set_rf_reg(dm, path, RF_0xef, BIT(19), 0x1);\n\t\t\t/*Select RX mode*/\n\t\t\todm_set_rf_reg(dm, path, RF_0x33, 0xF, 3);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, path, RF_0x3e, 0xfffff, 0x00036);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, path, RF_0x3f, 0xfffff, 0x5AFCE);\n\t\t\t/*RF mode table write disable*/\n\t\t\todm_set_rf_reg(dm, path, RF_0xef, BIT(19), 0x0);\n\t\t}\n\t}\n\t#endif\n\n\t#if (ODM_IC_11N_SERIES_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8192F) {\n\t\t/*RF mode table write enable*/\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1);\n\t\t/* Path A */\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x08000);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0005f);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x01042);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0004f);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x71fc2);\n\t\t/* Path B */\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x08000);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x00050);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x01042);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x00040);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x71fc2);\n\t\t/*RF mode table write disable*/\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0);\n\t}\n\t#endif\n}\n\nvoid phydm_dis_cdd(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\t#if (ODM_IC_11AC_SERIES_SUPPORT)\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\todm_set_bb_reg(dm, R_0x808, 0x3ffff00, 0);\n\t\todm_set_bb_reg(dm, R_0x9ac, 0x1fff, 0);\n\t\todm_set_bb_reg(dm, R_0x9ac, BIT(13), 1);\n\t}\n\t#endif\n\t#if (ODM_IC_11N_SERIES_SUPPORT)\n\tif (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\todm_set_bb_reg(dm, R_0x90c, 0xffffffff, 0x83321333);\n\t\t/* Set Tx delay setting for CCK pathA,B*/\n\t\todm_set_bb_reg(dm, R_0xa2c, 0xf0000000, 0);\n\t\t/*Enable Tx CDD for HT part when spatial expansion is applied*/\n\t\todm_set_bb_reg(dm, R_0xd00, BIT(8), 0);\n\t\t/* Tx CDD for Legacy*/\n\t\todm_set_bb_reg(dm, R_0xd04, 0xf0000, 0);\n\t\t/* Tx CDD for non-HT*/\n\t\todm_set_bb_reg(dm, R_0xd0c, 0x3c0, 0);\n\t\t/* Tx CDD for HT SS1*/\n\t\todm_set_bb_reg(dm, R_0xd0c, 0xf8000, 0);\n\t}\n\t#endif\n}\n\nvoid phydm_pathb_q_matrix_rotate_en(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tphydm_iq_gen_en(dm);\n\n\t/*#ifdef PHYDM_COMMON_API_SUPPORT*/\n\t/*path selection is controlled by driver*/\n\t#if 0\n\tif (!phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, BB_PATH_AB))\n\t\treturn;\n\t#endif\n\n\tphydm_dis_cdd(dm);\n\tphydm_pathb_q_matrix_rotate(dm, 0);\n\n\t#if (ODM_IC_11AC_SERIES_SUPPORT)\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\t/*Set Q matrix r_v11 =1*/\n\t\todm_set_bb_reg(dm, R_0x195c, MASKDWORD, 0x40000);\n\t\t/*Set Q matrix enable*/\n\t\todm_set_bb_reg(dm, R_0x191c, BIT(7), 1);\n\t}\n\t#endif\n}\n\nvoid phydm_pathb_q_matrix_rotate(void *dm_void, u16 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\t#if (ODM_IC_11AC_SERIES_SUPPORT)\n\tu32 phase_table_0[ANGLE_NUM] = {0x40000, 0x376CF, 0x20000, 0x00000,\n\t\t\t\t\t0xFE0000, 0xFC8930, 0xFC0000,\n\t\t\t\t\t0xFC8930, 0xFDFFFF, 0x000000,\n\t\t\t\t\t0x020000, 0x0376CF};\n\tu32 phase_table_1[ANGLE_NUM] = {0x00000, 0x1FFFF, 0x376CF, 0x40000,\n\t\t\t\t\t0x0376CF, 0x01FFFF, 0x000000,\n\t\t\t\t\t0xFDFFFF, 0xFC8930, 0xFC0000,\n\t\t\t\t\t0xFC8930, 0xFDFFFF};\n\t#endif\n\t#if (ODM_IC_11N_SERIES_SUPPORT)\n\tu32 phase_table_n_0[ANGLE_NUM] = {0x00, 0x0B, 0x02, 0x00, 0x02, 0x02,\n\t\t\t\t\t  0x04, 0x02, 0x0D, 0x09, 0x04, 0x0B};\n\tu32 phase_table_n_1[ANGLE_NUM] = {0x40000100, 0x377F00DD, 0x201D8880,\n\t\t\t\t\t  0x00000000, 0xE01D8B80, 0xC8BF0322,\n\t\t\t\t\t  0xC000FF00, 0xC8BF0322, 0xDFE2777F,\n\t\t\t\t\t  0xFFC003FF, 0x20227480, 0x377F00DD};\n\tu32 phase_table_n_2[ANGLE_NUM] = {0x00, 0x1E, 0x3C, 0x4C, 0x3C, 0x1E,\n\t\t\t\t\t  0x0F, 0xD2, 0xC3, 0xC4, 0xC3, 0xD2};\n\t#endif\n\tif (idx >= ANGLE_NUM) {\n\t\tpr_debug(\"[%s]warning Phase Set Error: %d\\n\", __func__, idx);\n\t\treturn;\n\t}\n\n\tswitch (dm->ic_ip_series) {\n\t#if (ODM_IC_11AC_SERIES_SUPPORT == 1)\n\tcase PHYDM_IC_AC:\n\t\t/*Set Q matrix r_v21*/\n\t\todm_set_bb_reg(dm, R_0x1954, 0xffffff, phase_table_0[idx]);\n\t\todm_set_bb_reg(dm, R_0x1950, 0xffffff, phase_table_1[idx]);\n\t\tbreak;\n\t#endif\n\n\t#if (ODM_IC_11N_SERIES_SUPPORT == 1)\n\tcase PHYDM_IC_N:\n\t\t/*Set Q matrix r_v21*/\n\t\todm_set_bb_reg(dm, R_0xc4c, 0xff000000, phase_table_n_0[idx]);\n\t\todm_set_bb_reg(dm, R_0xc88, 0xffffffff, phase_table_n_1[idx]);\n\t\todm_set_bb_reg(dm, R_0xc9c, 0xff000000, phase_table_n_2[idx]);\n\t\tbreak;\n\t#endif\n\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n/*Before use this API, Fill correct Tx Des. and Disable STBC in advance*/\nvoid phydm_set_direct_bfer(void *dm_void, u16 phs_idx, u8 su_idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#if (RTL8822B_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8822B) {\n#if 0\n\t\tu8 phi[13] = {0x0, 0x5, 0xa, 0xf, 0x15, 0x1a, 0x1f, 0x25,\n\t\t\t      0x2a, 0x2f, 0x35, 0x3a, 0x0};\n\t\tu8 psi[13] = {0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,\n\t\t\t      0x7, 0x7, 0x7, 0x7};\n\t\tu16 psiphi[13] = {0x1c0, 0x1c5, 0x1ca, 0x1cf, 0x1d5, 0x1da,\n\t\t\t\t  0x1df, 0x1e5, 0x1ea, 0x1ef, 0x1f5, 0x1fa,\n\t\t\t\t  0x1c0}; //{Psi_4bit, Phi_6bit} of 0~360\n#endif\n\t\tu16 ns[3] = {52, 108, 234}; //20/40/80 MHz subcarrier number\n\t\tu16 psiphi[13] = {0x1c0, 0x1c5, 0x1ca, 0x1cf, 0x1d5, 0x1da,\n\t\t\t\t  0x1df, 0x1e5, 0x1ea, 0x1ef, 0x1f5, 0x1fa,\n\t\t\t\t  0x1c0}; //{Psi_4bit, Phi_6bit} of 0~360\n\t\tu16 psiphiR;\n\t\tu8 i;\n\t\tu8 snr = 0x12; // for 1SS BF\n\t\tu8 nc = 0x0; //bit 2-0\n\t\tu8 nr = 0x1; //bit 5-3\n\t\tu8 ng = 0x0; //bit 7-6\n\t\tu8 cb = 0x1; //bit 9-8; 1 => phi:6, psi:4;\n\t\tu32 bw = odm_get_bb_reg(dm, R_0x8ac, 0x3); //bit 11-10\n\t\tu8 userid = su_idx; //bit 12\n\t\tu32 csi_report = 0x0;\n\t\tu32 ndp_bw = odm_get_bb_reg(dm, R_0x8ac, 0x3); //bit 11-10\n\t\tu8 ndp_sc = 0; //bit 11-10\n\t\tu32 ndp_info = 0x0;\n\n\t\tu16 mem_num = 0;\n\t\tu8 mem_move = 0;\n\t\tu8 mem_sel = 0;\n\t\tu16 mem_addr = 0;\n\t\tu32 dw0, dw1;\n\t\tu64 vm_info = 0;\n\t\tu64 temp = 0;\n\t\tu8 vm_cnt = 0;\n\n\t\tmem_num = ((8 + (6 + 4) * ns[bw]) >> 6) + 1; // SU codebook 1\n\n\t\t/* setting NDP BW/SC info*/\n\t\tndp_info = (ndp_bw & 0x3)  | (ndp_bw & 0x3) << 6 |\n\t\t\t   (ndp_bw & 0x3) << 12 | (ndp_sc & 0xf) << 2 |\n\t\t\t   (ndp_sc & 0xf) << 8 | (ndp_sc & 0xf) << 14;\n\t\todm_set_bb_reg(dm, R_0xb58, 0x000FFFFC, ndp_info);\n\t\todm_set_bb_reg(dm, R_0x19f8, 0x00010000, 1);\n\t\tODM_delay_ms(1); // delay 1ms\n\t\todm_set_bb_reg(dm, R_0x19f8, 0x00010000, 0);\n\n\t\t/* setting CSI report info*/\n\t\tcsi_report = (userid & 0x1) << 12 | (bw & 0x3) << 10 |\n\t\t\t     (cb & 0x3) << 8 | (ng & 0x3) << 6 |\n\t\t\t     (nr & 0x7) << 3 | (nc & 0x7);\n\t\todm_set_bb_reg(dm, R_0x72c, 0x1FFF, csi_report);\n\t\todm_set_bb_reg(dm, R_0x71c, 0x80000000, 1);\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] direct BF csi report 0x%x\\n\",\n\t\t\t  __func__, csi_report);\n\t\t/*========================*/\n\n\t\todm_set_bb_reg(dm, R_0x19b8, 0x40, 1); //0x19b8[6]:1 to csi_rpt\n\t\todm_set_bb_reg(dm, R_0x19e0, 0x3FC0, 0xFF); //gated_clk off\n\t\todm_set_bb_reg(dm, R_0x9e8, 0x2000000, 1); //abnormal txbf\n\t\todm_set_bb_reg(dm, R_0x9e8, 0x1000000, 0); //read phi psi\n\t\todm_set_bb_reg(dm, R_0x9e8, 0x70000000, su_idx); //SU user 0\n\t\todm_set_bb_reg(dm, R_0x1910, 0x8000, 0); //BFer\n\n\t\tdw0 = 0; // for 0x9ec\n\t\tdw1 = 0; // for 0x1900\n\t\tmem_addr = 0;\n\t\tmem_sel = 0;\n\t\tmem_move = 0;\n\t\tvm_info = vm_info | (snr & 0xff); //V matrix info\n\t\tvm_cnt = 8; // V matrix length counter\n\t\tpsiphiR = (psiphi[phs_idx] & 0x3ff);\n\n\t\twhile (mem_addr < mem_num) {\n\t\t\twhile (vm_cnt <= 32) {\n\t\t\t\t// shift only max. 32 bit\n\t\t\t\tif (vm_cnt >= 20) {\n\t\t\t\t\ttemp = psiphiR << 20;\n\t\t\t\t\ttemp = temp << (vm_cnt - 20);\n\t\t\t\t} else {\n\t\t\t\t\ttemp = psiphiR << vm_cnt;\n\t\t\t\t}\n\t\t\t\tvm_info |= temp;\n\t\t\t\tvm_cnt += 10;\n\t\t\t}\n\t\t\tif (mem_sel == 0) {\n\t\t\t\tdw0 = vm_info & 0xffffffff;\n\t\t\t\tvm_info = vm_info >> 32;\n\t\t\t\tvm_cnt -= 32;\n\t\t\t\tmem_sel = 1;\n\t\t\t\tmem_move = 0;\n\t\t\t} else {\n\t\t\t\tdw1 = vm_info & 0xffffffff;\n\t\t\t\tvm_info = vm_info >> 32;\n\t\t\t\tvm_cnt -= 32;\n\t\t\t\tmem_sel = 0;\n\t\t\t\tmem_move = 1;\n\t\t\t}\n\t\t\tif (mem_move == 1) {\n\t\t\t\todm_set_bb_reg(dm, 0x9e8, 0x1000000, 0);\n\t\t\t\t\t       //read phi psi\n\t\t\t\todm_set_bb_reg(dm, 0x1910, 0x3FF0000,\n\t\t\t\t\t       mem_addr);\n\t\t\t\todm_set_bb_reg(dm, 0x09ec, 0xFFFFFFFF, dw0);\n\t\t\t\todm_set_bb_reg(dm, 0x1900, 0xFFFFFFFF, dw1);\n\t\t\t\todm_set_bb_reg(dm, 0x9e8, 0x1000000, 1);\n\t\t\t\t\t       //write phi psi\n\t\t\t\tmem_move = 0;\n\t\t\t\tmem_addr += 1;\n\t\t\t}\n\t\t}\n\t\todm_set_bb_reg(dm, 0x9e8, 0x2000000, 0); //normal txbf\n\t}\n#endif\n} //end function\n#endif\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_direct_bf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDM_DIR_BF_H__\n#define __PHYDM_DIR_BF_H__\n\n#ifdef CONFIG_DIRECTIONAL_BF\n#define ANGLE_NUM\t12\n\n/*@\n * ============================================================\n * function prototype\n * ============================================================\n */\nvoid phydm_iq_gen_en(void *dm_void);\nvoid phydm_dis_cdd(void *dm_void);\nvoid phydm_pathb_q_matrix_rotate_en(void *dm_void);\nvoid phydm_pathb_q_matrix_rotate(void *dm_void, u16 idx);\n#endif\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_dynamictxpower.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*************************************************************\n * include files\n ************************************************************/\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#ifdef CONFIG_DYNAMIC_TX_TWR\n\n#ifdef BB_RAM_SUPPORT\n\nvoid\nphdm_2ndtype_rd_ram_pwr(void *dm_void,\tu8\tmacid)\n{\n};\n\nvoid\nphdm_2ndtype_wt_ram_pwr(void *dm_void, u8\tmacid, boolean pwr_offset0_en,\n\t\t\t     boolean\tpwr_offset1_en, s8 pwr_offset0, s8 pwr_offset1)\n{\n\tu32 reg_io_0x1e84 = 0;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;\n\tdm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[macid];\n\tdm_ram_per_sta->tx_pwr_offset0_en = pwr_offset0_en;\n\tdm_ram_per_sta->tx_pwr_offset1_en = pwr_offset1_en;\n\tdm_ram_per_sta->tx_pwr_offset0 = pwr_offset0;\n\tdm_ram_per_sta->tx_pwr_offset1 = pwr_offset1;\n\treg_io_0x1e84 = (dm_ram_per_sta->hw_igi_en<<7) + dm_ram_per_sta->hw_igi;\n\treg_io_0x1e84 |= (pwr_offset0_en<<15) + ((pwr_offset0&0x7f)<<8);\n\treg_io_0x1e84 |= (pwr_offset1_en<<23) + ((pwr_offset1&0x7f)<<16);\n\treg_io_0x1e84 |= (macid&0x3f)<<24;\n\treg_io_0x1e84 |= BIT(30);\n\todm_set_bb_reg(dm, 0x1e84, 0xffffffff, reg_io_0x1e84);\n};\n\nu8 phydm_pwr_lv_mapping_2ndtype(u8 tx_pwr_lv)\n{\n\tif (tx_pwr_lv == tx_high_pwr_level_level3)\n\t\t/*PHYDM_2ND_OFFSET_MINUS_11DB;*/\n\t\treturn PHYDM_2ND_OFFSET_MINUS_7DB;\n\telse if (tx_pwr_lv == tx_high_pwr_level_level2)\n\t\treturn PHYDM_2ND_OFFSET_MINUS_7DB;\n\telse if (tx_pwr_lv == tx_high_pwr_level_level1)\n\t\treturn PHYDM_2ND_OFFSET_MINUS_3DB;\n\telse\n\t\treturn PHYDM_2ND_OFFSET_ZERO;\n}\n\n#if CONFIG_PHY_CTRL_PWR\nvoid phydm_pwr_lv_ctrl(void *dm_void, u8 macid, u8 tx_pwr_lv)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\ts8 pwr_offset;\n\n\tif (tx_pwr_lv == tx_high_pwr_level_level3)\n\t\tpwr_offset = PHYDM_BBRAM_OFFSET_MINUS_11DB;\n\telse if (tx_pwr_lv == tx_high_pwr_level_level2)\n\t\tpwr_offset = PHYDM_BBRAM_OFFSET_MINUS_7DB;\n\telse if (tx_pwr_lv == tx_high_pwr_level_level1)\n\t\tpwr_offset = PHYDM_BBRAM_OFFSET_MINUS_3DB;\n\telse\n\t\tpwr_offset = PHYDM_BBRAM_OFFSET_ZERO;\n\tphdm_2ndtype_wt_ram_pwr(dm, macid, false, true, 0, pwr_offset);\n\todm_set_mac_reg(dm, ODM_REG_RESP_TX_11AC, BIT(19) | BIT(18), 1);\n}\n#endif\n\nvoid phydm_dtp_fill_cmninfo_2ndtype(void *dm_void, u8 macid, u8 dtp_lvl)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dtp_info *dtp = NULL;\n\n\tdtp = &dm->phydm_sta_info[macid]->dtp_stat;\n\tif (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))\n\t\treturn;\n\t#if CONFIG_PHY_CTRL_PWR\n\tdtp->dyn_tx_power = 1;\n\t#else\n\tdtp->dyn_tx_power = phydm_pwr_lv_mapping_2ndtype(dtp_lvl);\n\t#endif\n\tPHYDM_DBG(dm, DBG_DYN_TXPWR,\n\t\t  \"Fill cmninfo TxPwr: macid=(%d), PwrLv (%d)\\n\", macid,\n\t\t  dtp->dyn_tx_power);\n\t/* dyn_tx_power is 2 bit at 8822C/14B/98F/12F*/\n}\n\nvoid\nphydm_2ndtype_dtp_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8\tpwr_offset_minus3, pwr_offset_minus7;\n\tu8\ti;\n\n\t#if 0\n\t/*@ 2's com, for offset 3dB and 7dB, which 1 step will be 1dB*/\n\tpwr_offset_minus3 = 0x0;\n\tpwr_offset_minus7 = 0x0;\n\todm_set_bb_reg(dm, 0x1e70, 0x00ff0000, pwr_offset_minus3);\n\todm_set_bb_reg(dm, 0x1e70, 0xff000000, pwr_offset_minus7);\n\tfor (i = 0; i <= 63; i++)\n\t\tphdm_2ndtype_wt_ram_pwr(dm, i, false, false, 0, 0);\n\t#endif\n};\n\n#endif\n\nboolean\nphydm_check_rates(void *dm_void, u8 rate_idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 check_rate_bitmap0 = 0x08080808; /* @check CCK11M, OFDM54M, MCS7, MCS15*/\n\tu32 check_rate_bitmap1 = 0x80200808; /* @check MCS23, MCS31, VHT1SS M9, VHT2SS M9*/\n\tu32 check_rate_bitmap2 = 0x00080200; /* @check VHT3SS M9, VHT4SS M9*/\n\tu32 bitmap_result;\n\n#if (RTL8822B_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8822B) {\n\t\tcheck_rate_bitmap2 &= 0;\n\t\tcheck_rate_bitmap1 &= 0xfffff000;\n\t\tcheck_rate_bitmap0 &= 0x0fffffff;\n\t}\n#endif\n\n#if (RTL8197F_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8197F) {\n\t\tcheck_rate_bitmap2 &= 0;\n\t\tcheck_rate_bitmap1 &= 0;\n\t\tcheck_rate_bitmap0 &= 0x0fffffff;\n\t}\n#endif\n\n#if (RTL8192E_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8192E) {\n\t\tcheck_rate_bitmap2 &= 0;\n\t\tcheck_rate_bitmap1 &= 0;\n\t\tcheck_rate_bitmap0 &= 0x0fffffff;\n\t}\n#endif\n\n/*@jj add 20170822*/\n#if (RTL8192F_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8192F) {\n\t\tcheck_rate_bitmap2 &= 0;\n\t\tcheck_rate_bitmap1 &= 0;\n\t\tcheck_rate_bitmap0 &= 0x0fffffff;\n\t}\n#endif\n#if (RTL8721D_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8721D) {\n\t\tcheck_rate_bitmap2 &= 0;\n\t\tcheck_rate_bitmap1 &= 0;\n\t\tcheck_rate_bitmap0 &= 0x000fffff;\n\t}\n#endif\n#if (RTL8821C_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8821C) {\n\t\tcheck_rate_bitmap2 &= 0;\n\t\tcheck_rate_bitmap1 &= 0x003ff000;\n\t\tcheck_rate_bitmap0 &= 0x000fffff;\n\t}\n#endif\n\n\tif (rate_idx >= 64)\n\t\tbitmap_result = BIT(rate_idx - 64) & check_rate_bitmap2;\n\telse if (rate_idx >= 32)\n\t\tbitmap_result = BIT(rate_idx - 32) & check_rate_bitmap1;\n\telse if (rate_idx <= 31)\n\t\tbitmap_result = BIT(rate_idx) & check_rate_bitmap0;\n\n\tif (bitmap_result != 0)\n\t\treturn true;\n\telse\n\t\treturn false;\n}\n\nenum rf_path\nphydm_check_paths(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tenum rf_path max_path = RF_PATH_A;\n\n\tif (dm->num_rf_path == 1)\n\t\tmax_path = RF_PATH_A;\n\tif (dm->num_rf_path == 2)\n\t\tmax_path = RF_PATH_B;\n\tif (dm->num_rf_path == 3)\n\t\tmax_path = RF_PATH_C;\n\tif (dm->num_rf_path == 4)\n\t\tmax_path = RF_PATH_D;\n\n\treturn max_path;\n}\n\n#ifndef PHYDM_COMMON_API_SUPPORT\nu8 phydm_dtp_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 ret = 0xff;\n\n#if (RTL8192E_SUPPORT == 1)\n\tret = config_phydm_read_txagc_n(dm, path, hw_rate);\n#endif\n\treturn ret;\n}\n#endif\n\nu8 phydm_search_min_power_index(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tenum rf_path path;\n\tenum rf_path max_path;\n\tu8 min_gain_index = 0x3f;\n\tu8 gain_index;\n\tu8 rate_idx;\n\n\tPHYDM_DBG(dm, DBG_DYN_TXPWR, \"%s\\n\", __func__);\n\tmax_path = phydm_check_paths(dm);\n\tfor (path = 0; path <= max_path; path++)\n\t\tfor (rate_idx = 0; rate_idx < 84; rate_idx++)\n\t\t\tif (phydm_check_rates(dm, rate_idx)) {\n#ifdef PHYDM_COMMON_API_SUPPORT\n\t\t\t\t/*This is for API support IC : 97F,8822B,92F,8821C*/\n\t\t\t\tgain_index = phydm_api_get_txagc(dm, path, rate_idx);\n#else\n\t\t\t\t/*This is for API non-support IC : 92E */\n\t\t\t\tgain_index = phydm_dtp_get_txagc(dm, path, rate_idx);\n#endif\n\t\t\t\tif (gain_index == 0xff) {\n\t\t\t\t\tmin_gain_index = 0x20;\n\t\t\t\t\tPHYDM_DBG(dm, DBG_DYN_TXPWR, \n\t\t\t\t\t\t\"Error Gain idx!! Rewite to: ((%d))\\n\", min_gain_index);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tPHYDM_DBG(dm, DBG_DYN_TXPWR,\n\t\t\t\t\t  \"Support Rate: ((%d)) -> Gain idx: ((%d))\\n\",\n\t\t\t\t\t  rate_idx, gain_index);\n\t\t\t\tif (gain_index < min_gain_index)\n\t\t\t\t\tmin_gain_index = gain_index;\n\t\t\t}\n\n\treturn min_gain_index;\n}\n\nvoid phydm_dynamic_tx_power_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i;\n\tdm->last_dtp_lvl = tx_high_pwr_level_normal;\n\tdm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;\n\tfor (i = 0; i < 3; i++) {\n\t\tdm->enhance_pwr_th[i] = 0xff;\n\t}\n\tdm->set_pwr_th[0] = TX_POWER_NEAR_FIELD_THRESH_LVL1;\n\tdm->set_pwr_th[1] = TX_POWER_NEAR_FIELD_THRESH_LVL2;\n\tdm->set_pwr_th[2] = 0xff;\n\tdm->min_power_index = phydm_search_min_power_index(dm);\n\tPHYDM_DBG(dm, DBG_DYN_TXPWR, \"DTP init: Min Gain idx: ((%d))\\n\",\n\t\t  dm->min_power_index);\n\t#ifdef BB_RAM_SUPPORT\n\tphydm_2ndtype_dtp_init(dm);\n\t#endif\n}\n\nvoid phydm_noisy_enhance_hp_th(void *dm_void, u8 noisy_state)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tif (noisy_state == 0) {\n\t\tdm->enhance_pwr_th[0] = dm->set_pwr_th[0];\n\t\tdm->enhance_pwr_th[1] = dm->set_pwr_th[1];\n\t\tdm->enhance_pwr_th[2] = dm->set_pwr_th[2];\n\t} else {\n\t\tdm->enhance_pwr_th[0] = dm->set_pwr_th[0] + 8;\n\t\tdm->enhance_pwr_th[1] = dm->set_pwr_th[1] + 5;\n\t\tdm->enhance_pwr_th[2] = dm->set_pwr_th[2];\n\t}\n\tPHYDM_DBG(dm, DBG_DYN_TXPWR,\n\t\t  \"DTP hp_th: Lv1_th =%d ,Lv2_th = %d ,Lv3_th = %d\\n\",\n\t\t  dm->enhance_pwr_th[0], dm->enhance_pwr_th[1],\n\t\t  dm->enhance_pwr_th[2]);\n}\n\nu8 phydm_pwr_lvl_check(void *dm_void, u8 input_rssi)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 th0,th1,th2;\n\tth2 = dm->enhance_pwr_th[2];\n\tth1 = dm->enhance_pwr_th[1];\n\tth0 = dm->enhance_pwr_th[0];\n\tif (input_rssi >= th2)\n\t\treturn tx_high_pwr_level_level3;\n\telse if (input_rssi < (th2 - 3) && input_rssi >= th1)\n\t\treturn tx_high_pwr_level_level2;\n\telse if (input_rssi < (th1 - 3) && input_rssi >= th0)\n\t\treturn tx_high_pwr_level_level1;\n\telse if (input_rssi < (th0 - 3))\n\t\treturn tx_high_pwr_level_normal;\n\telse\n\t\treturn tx_high_pwr_level_unchange;\n}\n\nu8 phydm_pwr_lv_mapping(u8 tx_pwr_lv)\n{\n\tif (tx_pwr_lv == tx_high_pwr_level_level3)\n\t\treturn PHYDM_OFFSET_MINUS_11DB;\n\telse if (tx_pwr_lv == tx_high_pwr_level_level2)\n\t\treturn PHYDM_OFFSET_MINUS_7DB;\n\telse if (tx_pwr_lv == tx_high_pwr_level_level1)\n\t\treturn PHYDM_OFFSET_MINUS_3DB;\n\telse\n\t\treturn PHYDM_OFFSET_ZERO;\n}\n\nvoid phydm_dynamic_response_power(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 rpwr;\n\n#if CONFIG_PHY_CTRL_PWR\n\treturn;\n#endif\n\tif (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))\n\t\treturn;\n\tif (dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_unchange) {\n\t\tdm->dynamic_tx_high_power_lvl = dm->last_dtp_lvl;\n\t\tPHYDM_DBG(dm, DBG_DYN_TXPWR, \"RespPwr not change\\n\");\n\t\treturn;\n\t}\n\tPHYDM_DBG(dm, DBG_DYN_TXPWR,\n\t\t  \"RespPwr update_DTP_lv: ((%d)) -> ((%d))\\n\", dm->last_dtp_lvl,\n\t\t  dm->dynamic_tx_high_power_lvl);\n\tdm->last_dtp_lvl = dm->dynamic_tx_high_power_lvl;\n\trpwr = phydm_pwr_lv_mapping(dm->dynamic_tx_high_power_lvl);\n\todm_set_mac_reg(dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT(19) | BIT(18), rpwr);\n\tPHYDM_DBG(dm, DBG_DYN_TXPWR, \"RespPwr Set TxPwr: Lv (%d)\\n\",\n\t\t  dm->dynamic_tx_high_power_lvl);\n}\n\nvoid phydm_dtp_fill_cmninfo(void *dm_void, u8 macid, u8 dtp_lvl)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dtp_info *dtp = NULL;\n\tdtp = &dm->phydm_sta_info[macid]->dtp_stat;\n\tif (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))\n\t\treturn;\n\tdtp->dyn_tx_power = phydm_pwr_lv_mapping(dtp_lvl);\n\tPHYDM_DBG(dm, DBG_DYN_TXPWR,\n\t\t  \"Fill cmninfo TxPwr: macid=(%d), PwrLv (%d)\\n\", macid,\n\t\t  dtp->dyn_tx_power);\n}\n\nvoid phydm_dtp_per_sta(void *dm_void, u8 macid)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct cmn_sta_info *sta = dm->phydm_sta_info[macid];\n\tstruct dtp_info *dtp = NULL;\n\tstruct rssi_info *rssi = NULL;\n\tif (is_sta_active(sta)) {\n\t\tdtp = &sta->dtp_stat;\n\t\trssi = &sta->rssi_stat;\n\t\tdtp->sta_tx_high_power_lvl = phydm_pwr_lvl_check(dm, rssi->rssi);\n\t\tPHYDM_DBG(dm, DBG_DYN_TXPWR,\n\t\t\t  \"STA=%d , RSSI: %d , GetPwrLv: %d\\n\", macid,\n\t\t\t  rssi->rssi, dtp->sta_tx_high_power_lvl);\n\t\tif (dtp->sta_tx_high_power_lvl == tx_high_pwr_level_unchange \n\t\t\t|| dtp->sta_tx_high_power_lvl == dtp->sta_last_dtp_lvl) {\n\t\t\tdtp->sta_tx_high_power_lvl = dtp->sta_last_dtp_lvl;\n\t\t\tPHYDM_DBG(dm, DBG_DYN_TXPWR,\n\t\t\t\t  \"DTP_lv not change: ((%d))\\n\",\n\t\t\t\t  dtp->sta_tx_high_power_lvl);\n\t\t\treturn;\n\t\t}\n\n\t\tPHYDM_DBG(dm, DBG_DYN_TXPWR,\n\t\t\t  \"DTP_lv update: ((%d)) -> ((%d))\\n\", dm->last_dtp_lvl,\n\t\t\t  dm->dynamic_tx_high_power_lvl);\n\t\tdtp->sta_last_dtp_lvl = dtp->sta_tx_high_power_lvl;\n#ifdef BB_RAM_SUPPORT\n\t\tphydm_dtp_fill_cmninfo_2ndtype(dm, macid, dtp->sta_tx_high_power_lvl);\n#else\n\t\tphydm_dtp_fill_cmninfo(dm, macid, dtp->sta_tx_high_power_lvl);\n#endif\n\t}\n}\n\n\nvoid odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 macid)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct dtp_info *dtp = NULL;\n\tdtp = &dm->phydm_sta_info[macid]->dtp_stat;\n\tif (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))\n\t\treturn;\n\tif (dm->fill_desc_dyntxpwr)\n\t\tdm->fill_desc_dyntxpwr(dm, desc, dtp->dyn_tx_power);\n\telse\n\t\tPHYDM_DBG(dm, DBG_DYN_TXPWR,\n\t\t\t  \"%s: fill_desc_dyntxpwr is null!\\n\", __func__);\n\tif (dtp->last_tx_power != dtp->dyn_tx_power) {\n\t\tPHYDM_DBG(dm, DBG_DYN_TXPWR,\n\t\t\t  \"%s: last_offset=%d, txpwr_offset=%d\\n\", __func__,\n\t\t\t  dtp->last_tx_power, dtp->dyn_tx_power);\n\t\tdtp->last_tx_power = dtp->dyn_tx_power;\n\t}\n}\n\nvoid phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t\t     u32 *_out_len)\n{\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tchar help[] = \"-h\";\n\tu32 var1[3] = {0};\n\tu8 set_pwr_th1, set_pwr_th2, set_pwr_th3;\n\tu8 i;\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Set DTP threhosld: {1} {TH[0]} {TH[1]} {TH[2]}\\n\");\n\t} else {\n\t\tfor (i = 0; i < 3; i++) {\n\t\t\tif (input[i + 1])\n\t\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);\n\t\t}\n\t\tif (var1[0] == 1) {\n\t\t\tfor (i = 0; i < 3; i++)\n\t\t\t\tif (var1[i] == 0 || var1[i] > 100)\n\t\t\t\t\tdm->set_pwr_th[i] = 0xff;\n\t\t\t\telse\n\t\t\t\t\tdm->set_pwr_th[i] = (u8)var1[1 + i];\n\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"DTP_TH[0:2] = {%d, %d, %d}\\n\",\n\t\t\t\t dm->set_pwr_th[0], dm->set_pwr_th[1],\n\t\t\t\t dm->set_pwr_th[2]);\n\t\t}\n\t}\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\n\nvoid phydm_dynamic_tx_power(void *dm_void)\n{\n\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct cmn_sta_info *sta = NULL;\n\tu8 i;\n\tu8 cnt = 0;\n\tu8 rssi_min = dm->rssi_min;\n\tu8 rssi_tmp = 0;\n\n\tif (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))\n\t\treturn;\n\n\tPHYDM_DBG(dm, DBG_DYN_TXPWR,\n\t\t  \"[%s] RSSI_min = %d, Noisy_dec = %d\\n\", __func__, rssi_min,\n\t\t  dm->noisy_decision);\n\tphydm_noisy_enhance_hp_th(dm, dm->noisy_decision);\n\t/* Response Power */\n\tdm->dynamic_tx_high_power_lvl = phydm_pwr_lvl_check(dm, rssi_min);\n\tphydm_dynamic_response_power(dm);\n\t/* Per STA Tx power */\n\tfor (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {\n\t\tphydm_dtp_per_sta(dm, i);\n\t\tcnt++;\n\t\tif (cnt >= dm->number_linked_client)\n\t\t\tbreak;\n\t}\n}\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\nvoid phydm_dynamic_tx_power_init_win(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tvoid *adapter = dm->adapter;\n\tPMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);\n\n\tmgnt_info->bDynamicTxPowerEnable = false;\n\n\t#if DEV_BUS_TYPE == RT_USB_INTERFACE\n\tif (RT_GetInterfaceSelection((PADAPTER)adapter) ==\n\t    INTF_SEL1_USB_High_Power) {\n\t\tmgnt_info->bDynamicTxPowerEnable = true;\n\t}\n\t#endif\n\n\thal_data->LastDTPLvl = tx_high_pwr_level_normal;\n\thal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;\n\n\tPHYDM_DBG(dm, DBG_DYN_TXPWR, \"[%s] DTP=%d\\n\", __func__,\n\t\t  mgnt_info->bDynamicTxPowerEnable);\n}\n\nvoid phydm_dynamic_tx_power_win(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))\n\t\treturn;\n\n\t#if (RTL8814A_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8814A)\n\t\todm_dynamic_tx_power_8814a(dm);\n\t#endif\n\n\t#if (RTL8821A_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8821) {\n\t\tvoid *adapter = dm->adapter;\n\t\tPMGNT_INFO mgnt_info = GetDefaultMgntInfo((PADAPTER)adapter);\n\n\t\tif (mgnt_info->RegRspPwr == 1) {\n\t\t\tif (dm->rssi_min > 60) {\n\t\t\t\t/*Resp TXAGC offset = -3dB*/\n\t\t\t\todm_set_mac_reg(dm, 0x6d8, 0x1C0000, 1);\n\t\t\t} else if (dm->rssi_min < 55) {\n\t\t\t\t/*Resp TXAGC offset = 0dB*/\n\t\t\t\todm_set_mac_reg(dm, 0x6d8, 0x1C0000, 0);\n\t\t\t}\n\t\t}\n\t}\n\t#endif\n}\n#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/\n#endif /* @#ifdef CONFIG_DYNAMIC_TX_TWR */\n"
  },
  {
    "path": "hal/phydm/phydm_dynamictxpower.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDMDYNAMICTXPOWER_H__\n#define __PHYDMDYNAMICTXPOWER_H__\n\n#ifdef CONFIG_DYNAMIC_TX_TWR\n/* @============================================================\n *  Definition\n * ============================================================\n */\n\n/*@#define DYNAMIC_TXPWR_VERSION\t\"1.0\"*/\n/*@#define DYNAMIC_TXPWR_VERSION\t\"1.3\" */ /*@2015.08.26, Add 8814 Dynamic TX power*/\n#define DYNAMIC_TXPWR_VERSION \"1.4\" /*@2015.11.06, Add CE 8821A Dynamic TX power*/\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74\n#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60\n#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F\n#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74\n#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74\n#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60\n#endif\n\n#define tx_high_pwr_level_normal 0\n#define tx_high_pwr_level_level1 1\n#define tx_high_pwr_level_level2 2\n#define tx_high_pwr_level_level3 3\n#define tx_high_pwr_level_unchange 4\n\n/* @============================================================\n * enumrate\n * ============================================================\n */\nenum phydm_dtp_power_offset {\n\tPHYDM_OFFSET_ZERO = 0,\n\tPHYDM_OFFSET_MINUS_3DB = 1,\n\tPHYDM_OFFSET_MINUS_7DB = 2,\n\tPHYDM_OFFSET_MINUS_11DB = 3,\n\tPHYDM_OFFSET_ADD_3DB = 4,\n\tPHYDM_OFFSET_ADD_6DB = 5\n};\n\nenum phydm_dtp_power_offset_2ndtype {\n\tPHYDM_2ND_OFFSET_ZERO = 0,\n\tPHYDM_2ND_OFFSET_MINUS_3DB = 2,\n\tPHYDM_2ND_OFFSET_MINUS_7DB = 3,\n\tPHYDM_2ND_OFFSET_MINUS_11DB = 1\n};\n\nenum phydm_dtp_power_offset_bbram {\n\t/*@ HW min use 0.25*/\n\tPHYDM_BBRAM_OFFSET_ZERO = 0,\n\tPHYDM_BBRAM_OFFSET_MINUS_3DB = -3,\n\tPHYDM_BBRAM_OFFSET_MINUS_7DB = -7,\n\tPHYDM_BBRAM_OFFSET_MINUS_11DB = -11\n};\n\n/* @============================================================\n *  structure\n * ============================================================\n */\n\n/* @============================================================\n *  Function Prototype\n * ============================================================\n */\n\nextern void\nodm_set_dyntxpwr(void *dm_void, u8 *desc, u8 mac_id);\n\nvoid phydm_dynamic_tx_power(void *dm_void);\n\nvoid phydm_dynamic_tx_power_init(void *dm_void);\n\nvoid phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t\t     u32 *_out_len);\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid odm_dynamic_tx_power_win(void *dm_void);\n#endif\n\n#endif\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_features.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDM_FEATURES_H__\n#define __PHYDM_FEATURES_H__\n\n#define CONFIG_RUN_IN_DRV\n#define ODM_DC_CANCELLATION_SUPPORT\t\t(ODM_RTL8188F | \\\n\t\t\t\t\t\t ODM_RTL8710B | \\\n\t\t\t\t\t\t ODM_RTL8723D | \\\n\t\t\t\t\t\t ODM_RTL8192F | \\\n\t\t\t\t\t\t ODM_RTL8821C | \\\n\t\t\t\t\t\t ODM_RTL8721D)\n#define ODM_RECEIVER_BLOCKING_SUPPORT\t(ODM_RTL8188E | ODM_RTL8192E)\n\n/*@20170103 YuChen add for FW API*/\n#define PHYDM_FW_API_ENABLE_8822B\t\t1\n#define PHYDM_FW_API_FUNC_ENABLE_8822B\t\t1\n#define PHYDM_FW_API_ENABLE_8821C\t\t1\n#define PHYDM_FW_API_FUNC_ENABLE_8821C\t\t1\n#define PHYDM_FW_API_ENABLE_8195B\t\t1\n#define PHYDM_FW_API_FUNC_ENABLE_8195B\t\t1\n#define PHYDM_FW_API_ENABLE_8198F\t\t1\n#define PHYDM_FW_API_FUNC_ENABLE_8198F\t\t1\n#define PHYDM_FW_API_ENABLE_8822C 1\n#define PHYDM_FW_API_FUNC_ENABLE_8822C 1\n#define PHYDM_FW_API_ENABLE_8814B 1\n#define PHYDM_FW_API_FUNC_ENABLE_8814B 1\n#define PHYDM_FW_API_ENABLE_8812F 1\n#define PHYDM_FW_API_FUNC_ENABLE_8812F 1\n\n#define CONFIG_POWERSAVING 0\n\n#ifdef BEAMFORMING_SUPPORT\n#if (BEAMFORMING_SUPPORT)\n\t#define PHYDM_BEAMFORMING_SUPPORT\n#endif\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t#include\t\"phydm_features_win.h\"\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t#include\t\"phydm_features_ce.h\"\n\t/*@#include\t\"phydm_features_ce2_kernel.h\"*/\n#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t#include\t\"phydm_features_ap.h\"\n#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)\n\t#include\t\"phydm_features_iot.h\"\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_features_ap.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef\t__PHYDM_FEATURES_AP_H__\n#define __PHYDM_FEATURES_AP_H__\n\n#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\\\n\tRTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\\\n\tRTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT)\n\t#define PHYDM_LA_MODE_SUPPORT\t\t\t1\n#else\n\t#define PHYDM_LA_MODE_SUPPORT\t\t\t0\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\\\n\tRTL8192F_SUPPORT)\n\t#define DYN_ANT_WEIGHTING_SUPPORT\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)\n\t#define FAHM_SUPPORT\n#endif\n\t#define NHM_SUPPORT\n\t#define CLM_SUPPORT\n\n#if (RTL8822B_SUPPORT)\n\t/*#define PHYDM_PHYSTAUS_SMP_MODE*/\n#endif\n\n#if (RTL8197F_SUPPORT)\n\t/*#define PHYDM_TDMA_DIG_SUPPORT*/\n#endif\n\n#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)\n\t#define PHYDM_TDMA_DIG_SUPPORT 1\n\t#ifdef PHYDM_TDMA_DIG_SUPPORT\n\t#define IS_USE_NEW_TDMA /*new tdma dig test*/\n\t#endif\n#endif\n\n#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT ||\\\n\tRTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)\n\t#define PHYDM_LNA_SAT_CHK_SUPPORT\n\t#ifdef PHYDM_LNA_SAT_CHK_SUPPORT\n\n\t\t#if (RTL8197F_SUPPORT)\n\t\t/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/\n\t\t#endif\n\n\t\t#if (RTL8822B_SUPPORT)\n\t\t/*#define PHYDM_LNA_SAT_CHK_TYPE2*/\n\t\t#endif\n\n\t\t#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)\n\t\t#define PHYDM_LNA_SAT_CHK_TYPE1\n\t\t#endif\n\t#endif\n#endif\n\n#if (RTL8822B_SUPPORT)\n\t/*#define PHYDM_POWER_TRAINING_SUPPORT*/\n#endif\n\n#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\\\n\tRTL8812F_SUPPORT)\n\t#define PHYDM_PMAC_TX_SETTING_SUPPORT\n#endif\n\n#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\\\n\tRTL8812F_SUPPORT)\n\t#define PHYDM_MP_SUPPORT\n#endif\n\n#if (RTL8822B_SUPPORT)\n\t#define PHYDM_TXA_CALIBRATION\n#endif\n\n#if (RTL8188E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)\n\t#define\tPHYDM_PRIMARY_CCA\n#endif\n\n#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\\\n\tRTL8822B_SUPPORT || RTL8192F_SUPPORT)\n\t#define\tPHYDM_DC_CANCELLATION\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)\n\t#define\tCONFIG_ADAPTIVE_SOML\n#endif\n\n#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\\\n\tRTL8192E_SUPPORT || RTL8723B_SUPPORT)\n\t/*#define\tCONFIG_RA_FW_DBG_CODE*/\n#endif\n\n#if (RTL8192F_SUPPORT == 1)\n\t/*#define\tCONFIG_8912F_SPUR_CALIBRATION*/\n#endif\n\n#if (RTL8822B_SUPPORT == 1)\n\t/* #define\tCONFIG_8822B_SPUR_CALIBRATION */\n#endif\n\n#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR\n#define CONFIG_DYNAMIC_TX_TWR\n#endif\n/*#define\tCONFIG_PSD_TOOL*/\n#define PHYDM_SUPPORT_CCKPD\n#define PHYDM_SUPPORT_ADAPTIVITY\n/*#define\tCONFIG_PATH_DIVERSITY*/\n/*#define\tCONFIG_RA_DYNAMIC_RTY_LIMIT*/\n/*#define\tCONFIG_RA_DYNAMIC_RATE_ID*/\n#define\tCONFIG_BB_TXBF_API\n/*#define\tODM_CONFIG_BT_COEXIST*/\n#define\tPHYDM_SUPPORT_RSSI_MONITOR\n#if !defined(CONFIG_DISABLE_PHYDM_DEBUG_FUNCTION)\n\t#define CONFIG_PHYDM_DEBUG_FUNCTION\n#endif\n\n/* [ Configure Antenna Diversity ] */\n#if (RTL8188F_SUPPORT)\n\t#ifdef CONFIG_ANTENNA_DIVERSITY\n\t\t#define CONFIG_PHYDM_ANTENNA_DIVERSITY\n\t\t#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\t#endif\n#endif\n\n#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) || defined(CONFIG_RTL_8197F_ANT_SWITCH)\n\t#define CONFIG_PHYDM_ANTENNA_DIVERSITY\n\t#define ODM_EVM_ENHANCE_ANTDIV\n\t/*#define SKIP_EVM_ANTDIV_TRAINING_PATCH*/\n\n\t/*----------*/\n\t#ifdef CONFIG_NO_2G_DIVERSITY_8197F\n\t\t#define CONFIG_NO_2G_DIVERSITY\n\t#elif defined(CONFIG_2G_CGCS_RX_DIVERSITY_8197F)\n\t\t#define CONFIG_2G_CGCS_RX_DIVERSITY\n\t#elif defined(CONFIG_2G_CG_TRX_DIVERSITY_8197F)\n\t\t#define CONFIG_2G_CG_TRX_DIVERSITY\n\t#endif\n\n\t#if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))\n\t\t#define CONFIG_NO_2G_DIVERSITY\n\t#endif\n\n\t#ifdef CONFIG_NO_5G_DIVERSITY_8881A\n\t\t#define CONFIG_NO_5G_DIVERSITY\n\t#elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A)\n\t\t#define CONFIG_5G_CGCS_RX_DIVERSITY\n\t#elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A)\n\t\t#define CONFIG_5G_CG_TRX_DIVERSITY\n\t#elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)\n\t\t#define CONFIG_2G5G_CG_TRX_DIVERSITY\n\t#endif\n\t#if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))\n\t\t#define CONFIG_NO_5G_DIVERSITY\n\t#endif\n\t/*----------*/\n\t#if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))\n\t\t#define CONFIG_NOT_SUPPORT_ANTDIV\n\t#elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))\n\t\t#define CONFIG_2G_SUPPORT_ANTDIV\n\t#elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY))\n\t\t#define CONFIG_5G_SUPPORT_ANTDIV\n\t#elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY))\n\t\t\t#define CONFIG_2G5G_SUPPORT_ANTDIV\n\t#endif\n\t\t/*----------*/\n#endif /*Antenna Diveristy*/\n\n/*[SmartAntenna]*/\n/*#define\tCONFIG_SMART_ANTENNA*/\n#ifdef CONFIG_SMART_ANTENNA\n\t/*#define\tCONFIG_CUMITEK_SMART_ANTENNA*/\n#endif\n#define CFG_DIG_DAMPING_CHK\n/* --------------------------------------------------*/\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\t#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\\\n\t     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\\\n\t     RTL8814B_SUPPORT || RTL8812F_SUPPORT)\n\t\t#define\tDRIVER_BEAMFORMING_VERSION2\n\t#endif\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_features_ce.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDM_FEATURES_CE_H__\n#define __PHYDM_FEATURES_CE_H__\n\n#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\\\n\tRTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\\\n\tRTL8822C_SUPPORT)\n\t#define PHYDM_LA_MODE_SUPPORT\t\t\t1\n#else\n\t#define PHYDM_LA_MODE_SUPPORT\t\t\t0\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\\\n\tRTL8192F_SUPPORT)\n\t#define DYN_ANT_WEIGHTING_SUPPORT\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)\n\t#define FAHM_SUPPORT\n#endif\n\t#define NHM_SUPPORT\n\t#define CLM_SUPPORT\n\n#if (RTL8822C_SUPPORT)\n\t#define NHM_DYM_PW_TH_SUPPORT\n#endif\n\n#if (RTL8822B_SUPPORT)\n\t/*@#define PHYDM_PHYSTAUS_SMP_MODE*/\n#endif\n\n/*@#define PHYDM_TDMA_DIG_SUPPORT*/\n\n#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8821C_SUPPORT ||\\\n\tRTL8822C_SUPPORT || RTL8723D_SUPPORT)\n\t#ifdef CONFIG_TDMADIG\n\t#define PHYDM_TDMA_DIG_SUPPORT\n\t#ifdef PHYDM_TDMA_DIG_SUPPORT\n\t#define IS_USE_NEW_TDMA /*new tdma dig test*/\n\t#endif\n\t#endif\n#endif\n\n#if (RTL8814B_SUPPORT)\n\t/*@#define PHYDM_TDMA_DIG_SUPPORT*/\n\t#ifdef PHYDM_TDMA_DIG_SUPPORT\n\t/*@#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/\n\t#endif\n#endif\n\n#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8814B_SUPPORT)\n\t/*@#define PHYDM_LNA_SAT_CHK_SUPPORT*/\n\t#ifdef PHYDM_LNA_SAT_CHK_SUPPORT\n\n\t\t#if (RTL8197F_SUPPORT)\n\t\t/*@#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/\n\t\t#endif\n\n\t\t#if (RTL8822B_SUPPORT)\n\t\t/*@#define PHYDM_LNA_SAT_CHK_TYPE2*/\n\t\t#endif\n\n\t\t#if (RTL8814B_SUPPORT)\n\t\t/*@#define PHYDM_LNA_SAT_CHK_TYPE1*/\n\t\t#endif\n\t#endif\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT)\n\t#define PHYDM_POWER_TRAINING_SUPPORT\n#endif\n\n#if (RTL8822C_SUPPORT)\n\t#define PHYDM_PMAC_TX_SETTING_SUPPORT\n#endif\n\n#if (RTL8822C_SUPPORT)\n\t#define PHYDM_MP_SUPPORT\n#endif\n\n#if (RTL8822B_SUPPORT)\n\t#define PHYDM_TXA_CALIBRATION\n#endif\n\n#if (RTL8188E_SUPPORT)\n\t#define\tPHYDM_PRIMARY_CCA\n#endif\n\n#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\\\n\tRTL8822B_SUPPORT || RTL8192F_SUPPORT)\n\t#define\tPHYDM_DC_CANCELLATION\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)\n\t#define\tCONFIG_ADAPTIVE_SOML\n#endif\n\n#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)\n\t#define\tCONFIG_RECEIVER_BLOCKING\n#endif\n\n#if (RTL8192F_SUPPORT == 1)\n\t/*#define\tCONFIG_8912F_SPUR_CALIBRATION*/\n#endif\n\n#if (RTL8822B_SUPPORT == 1)\n\t#define\tCONFIG_8822B_SPUR_CALIBRATION\n#endif\n\n#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR\n#define CONFIG_DYNAMIC_TX_TWR\n#endif\n#define PHYDM_SUPPORT_CCKPD\n#define PHYDM_SUPPORT_ADAPTIVITY\n\n/*@Antenna Diversity*/\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\t#define CONFIG_PHYDM_ANTENNA_DIVERSITY\n\n\t#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\n\t\t#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\\\n\t\t     RTL8188F_SUPPORT || RTL8821C_SUPPORT ||\\\n\t\t     RTL8723D_SUPPORT)\n\t\t\t#define\tCONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\t\t#endif\n\n\t\t#if (RTL8821A_SUPPORT)\n\t\t\t/*@#define CONFIG_HL_SMART_ANTENNA_TYPE1*/\n\t\t#endif\n\n\t\t#if (RTL8822B_SUPPORT)\n\t\t\t/*@#define CONFIG_HL_SMART_ANTENNA_TYPE2*/\n\t\t#endif\n\n\t#endif\n#endif\n\n#if (RTL8822C_SUPPORT)\n\t#define CONFIG_PATH_DIVERSITY\n#endif\n\n/*@[SmartAntenna]*/\n/*@#define\tCONFIG_SMART_ANTENNA*/\n#ifdef CONFIG_SMART_ANTENNA\n\t/*@#define\tCONFIG_CUMITEK_SMART_ANTENNA*/\n#endif\n/* @--------------------------------------------------*/\n\n#ifdef CONFIG_DFS_MASTER\n\t#define CONFIG_PHYDM_DFS_MASTER\n#endif\n\n#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\\\n\tRTL8192E_SUPPORT || RTL8723B_SUPPORT)\n\t/*@#define\tCONFIG_RA_FW_DBG_CODE*/\n#endif\n\n#define\tCONFIG_PSD_TOOL\n/*@#define\tCONFIG_ANT_DETECTION*/\n/*@#define\tCONFIG_RA_DYNAMIC_RTY_LIMIT*/\n#define\tCONFIG_BB_TXBF_API\n#define\tCONFIG_PHYDM_DEBUG_FUNCTION\n\n#ifdef CONFIG_BT_COEXIST\n\t#define\tODM_CONFIG_BT_COEXIST\n#endif\n#define\tPHYDM_SUPPORT_RSSI_MONITOR\n#define\tPHYDM_AUTO_DEGBUG\n#define CFG_DIG_DAMPING_CHK\n\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\t#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8192E_SUPPORT ||\\\n\t     RTL8814A_SUPPORT || RTL8881A_SUPPORT)\n\t\t#define\tPHYDM_BEAMFORMING_VERSION1\n\t#endif\n\t#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\\\n\t     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\\\n\t     RTL8822C_SUPPORT || RTL8814B_SUPPORT)\n\t\t#define\tDRIVER_BEAMFORMING_VERSION2\n\t#endif\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT)\n\t#ifdef CONFIG_MCC_MODE\n\t#define\tCONFIG_MCC_DM\n\t#endif\n#endif\n\n#if (RTL8822B_SUPPORT)\n\t#ifdef CONFIG_DYNAMIC_BYPASS_MODE\n\t#define\tCONFIG_DYNAMIC_BYPASS\n\t#endif\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT)\n\t#define CONFIG_DIRECTIONAL_BF\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_features_ce2_kernel.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDM_FEATURES_CE_H__\n#define __PHYDM_FEATURES_CE_H__\n\n#define PHYDM_LA_MODE_SUPPORT\t\t\t0\n\n#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\\\n\tRTL8192F_SUPPORT)\n\t#define DYN_ANT_WEIGHTING_SUPPORT\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)\n\t#define FAHM_SUPPORT\n#endif\n\t#define NHM_SUPPORT\n\t#define CLM_SUPPORT\n\n#if (RTL8822B_SUPPORT)\n\t#define PHYDM_TXA_CALIBRATION\n#endif\n\n#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\\\n\tRTL8822B_SUPPORT || RTL8192F_SUPPORT)\n\t#define\tPHYDM_DC_CANCELLATION\n#endif\n\n#if (RTL8192F_SUPPORT == 1)\n\t/*#define\tCONFIG_8912F_SPUR_CALIBRATION*/\n#endif\n\n#if (RTL8822B_SUPPORT == 1)\n\t/* #define\tCONFIG_8822B_SPUR_CALIBRATION */\n#endif\n\n#define PHYDM_SUPPORT_CCKPD\n#define PHYDM_SUPPORT_ADAPTIVITY\n\n#ifdef CONFIG_DFS_MASTER\n\t#define CONFIG_PHYDM_DFS_MASTER\n#endif\n\n#define\tCONFIG_BB_TXBF_API\n#define\tCONFIG_PHYDM_DEBUG_FUNCTION\n\n#ifdef CONFIG_BT_COEXIST\n\t#define\tODM_CONFIG_BT_COEXIST\n#endif\n#define\tPHYDM_SUPPORT_RSSI_MONITOR\n#define CFG_DIG_DAMPING_CHK\n\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\t#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\\\n\t     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\\\n\t     RTL8822C_SUPPORT || RTL8814B_SUPPORT)\n\t\t#define\tDRIVER_BEAMFORMING_VERSION2\n\t#endif\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_features_iot.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef\t__PHYDM_FEATURES_IOT_H__\n#define __PHYDM_FEATURES_IOT_H__\n\n#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\\\n\tRTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\\\n\tRTL8822C_SUPPORT || RTL8195B_SUPPORT)\n\t#define PHYDM_LA_MODE_SUPPORT\t\t\t1\n#else\n\t#define PHYDM_LA_MODE_SUPPORT\t\t\t0\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\\\n\tRTL8192F_SUPPORT)\n\t#define DYN_ANT_WEIGHTING_SUPPORT\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)\n\t#define FAHM_SUPPORT\n#endif\n\t#define NHM_SUPPORT\n\t#define CLM_SUPPORT\n\n#if (RTL8822B_SUPPORT)\n\t/*#define PHYDM_PHYSTAUS_SMP_MODE*/\n#endif\n\n/*#define PHYDM_TDMA_DIG_SUPPORT*/\n\n#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT)\n\t/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/\n\t#ifdef PHYDM_LNA_SAT_CHK_SUPPORT\n\t\t#if (RTL8197F_SUPPORT)\n\t\t/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/\n\t\t#endif\n\n\t\t#if (RTL8822B_SUPPORT)\n\t\t/*#define PHYDM_LNA_SAT_CHK_TYPE2*/\n\t\t#endif\n\t#endif\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8721D_SUPPORT)\n\t#define PHYDM_POWER_TRAINING_SUPPORT\n#endif\n\n#if (RTL8822C_SUPPORT)\n\t/* #define PHYDM_PMAC_TX_SETTING_SUPPORT */\n#endif\n\n#if (RTL8822C_SUPPORT)\n\t/* #define PHYDM_MP_SUPPORT */\n#endif\n\n#if (RTL8822B_SUPPORT)\n\t#define PHYDM_TXA_CALIBRATION\n#endif\n\n#if (RTL8188E_SUPPORT)\n\t#define\tPHYDM_PRIMARY_CCA\n#endif\n\n#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\\\n\tRTL8822B_SUPPORT || RTL8721D_SUPPORT)\n\t#define\tPHYDM_DC_CANCELLATION\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)\n\t#define\tCONFIG_ADAPTIVE_SOML\n#endif\n\n#if (RTL8822B_SUPPORT)\n\t/*#define\tCONFIG_DYNAMIC_RX_PATH*/\n#endif\n\n#if (RTL8822B_SUPPORT == 1)\n\t/* #define\tCONFIG_8822B_SPUR_CALIBRATION */\n#endif\n\n#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)\n\t#define\tCONFIG_RECEIVER_BLOCKING\n#endif\n\n#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR\n#define CONFIG_DYNAMIC_TX_TWR\n#endif\n#define PHYDM_SUPPORT_CCKPD\n#define PHYDM_SUPPORT_ADAPTIVITY\n\n/*Antenna Diversity*/\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\t#define CONFIG_PHYDM_ANTENNA_DIVERSITY\n\n\t#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\n\t\t#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\\\n\t\t     RTL8188F_SUPPORT || RTL8821C_SUPPORT)\n\t\t\t#define\tCONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\t\t#endif\n\n\t\t#if (RTL8821A_SUPPORT)\n\t\t\t/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/\n\t\t#endif\n\n\t\t#if (RTL8822B_SUPPORT)\n\t\t\t/*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/\n\t\t#endif\n\t#endif\n#endif\n\n/*[SmartAntenna]*/\n/*#define\tCONFIG_SMART_ANTENNA*/\n#ifdef CONFIG_SMART_ANTENNA\n\t/*#define\tCONFIG_CUMITEK_SMART_ANTENNA*/\n#endif\n/* --------------------------------------------------*/\n\n#ifdef CONFIG_DFS_MASTER\n\t#define CONFIG_PHYDM_DFS_MASTER\n#endif\n\n#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\\\n\tRTL8192E_SUPPORT || RTL8723B_SUPPORT)\n\t/*#define\tCONFIG_RA_FW_DBG_CODE*/\n#endif\n\n#define\tCONFIG_PSD_TOOL\n/*#define\tCONFIG_RA_DBG_CMD*/\n/*#define\tCONFIG_ANT_DETECTION*/\n/*#define\tCONFIG_PATH_DIVERSITY*/\n/*#define\tCONFIG_RA_DYNAMIC_RTY_LIMIT*/\n#define\tCONFIG_BB_TXBF_API\n#define\tCONFIG_PHYDM_DEBUG_FUNCTION\n\n#ifdef CONFIG_BT_COEXIST\n\t#define\tODM_CONFIG_BT_COEXIST\n#endif\n#define\tPHYDM_SUPPORT_RSSI_MONITOR\n/*#define\tPHYDM_AUTO_DEGBUG*/\n#define CFG_DIG_DAMPING_CHK\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\t#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\\\n\t     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\\\n\t     RTL8822C_SUPPORT || RTL8814B_SUPPORT)\n\t\t#define\tDRIVER_BEAMFORMING_VERSION2\n\t#endif\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_features_win.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef\t__PHYDM_FEATURES_WIN_H__\n#define __PHYDM_FEATURES_WIN_H__\n\n#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\\\n\tRTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\\\n\tRTL8822C_SUPPORT || RTL8814B_SUPPORT)\n\t#define PHYDM_LA_MODE_SUPPORT\t\t\t1\n#else\n\t#define PHYDM_LA_MODE_SUPPORT\t\t\t0\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\\\n\tRTL8192F_SUPPORT)\n\t#define DYN_ANT_WEIGHTING_SUPPORT\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)\n\t#define FAHM_SUPPORT\n#endif\n\t#define NHM_SUPPORT\n\t#define CLM_SUPPORT\n\n#if (RTL8822C_SUPPORT)\n\t#define NHM_DYM_PW_TH_SUPPORT\n#endif\n\n#if (RTL8822B_SUPPORT)\n\t/*#define PHYDM_PHYSTAUS_SMP_MODE*/\n#endif\n\n/*#define PHYDM_TDMA_DIG_SUPPORT*/\n\n#if (RTL8814B_SUPPORT)\n\t/*#define PHYDM_TDMA_DIG_SUPPORT*/\n\t#ifdef PHYDM_TDMA_DIG_SUPPORT\n\t/*#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/\n\t#endif\n#endif\n\n#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8814B_SUPPORT)\n\t/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/\n\t#ifdef PHYDM_LNA_SAT_CHK_SUPPORT\n\n\t\t#if (RTL8197F_SUPPORT)\n\t\t/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/\n\t\t#endif\n\n\t\t#if (RTL8822B_SUPPORT)\n\t\t/*#define PHYDM_LNA_SAT_CHK_TYPE2*/\n\t\t#endif\n\n\t\t#if (RTL8814B_SUPPORT)\n\t\t/*#define PHYDM_LNA_SAT_CHK_TYPE1*/\n\t\t#endif\n\t#endif\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8710B_SUPPORT || RTL8723D_SUPPORT ||\\\n\tRTL8192F_SUPPORT)\n\t#define\tPHYDM_POWER_TRAINING_SUPPORT\n#endif\n\n#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT)\n\t#define\tPHYDM_PMAC_TX_SETTING_SUPPORT\n#endif\n\n#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT)\n\t#define\tPHYDM_MP_SUPPORT\n#endif\n\n#if (RTL8822B_SUPPORT)\n\t#define\tPHYDM_TXA_CALIBRATION\n#endif\n\n#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)\n\t#define\tPHYDM_PRIMARY_CCA\n#endif\n\n#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\\\n\tRTL8822B_SUPPORT || RTL8192F_SUPPORT)\n\t#define\tPHYDM_DC_CANCELLATION\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)\n\t#define\tCONFIG_ADAPTIVE_SOML\n#endif\n\n#if (RTL8192F_SUPPORT == 1)\n\t#define\tCONFIG_8912F_SPUR_CALIBRATION\n#endif\n\n/*Antenna Diversity*/\n#define\tCONFIG_PHYDM_ANTENNA_DIVERSITY\n#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\n\t#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT || RTL8188F_SUPPORT ||\\\n\t     RTL8821C_SUPPORT || RTL8723D_SUPPORT)\n\t\t#define\tCONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\t#endif\n\n\t#if (RTL8822B_SUPPORT)\n\t\t/*#define\tODM_EVM_ENHANCE_ANTDIV*/\n\t\t/*#define\tCONFIG_2T3R_ANTENNA*/\n\t\t/*#define\tCONFIG_2T4R_ANTENNA*/\n\t#endif\n\n\t/* --[SmtAnt]-----------------------------------------*/\n\t#if (RTL8821A_SUPPORT)\n\t\t/*#define\tCONFIG_HL_SMART_ANTENNA_TYPE1*/\n\t\t#define\tCONFIG_FAT_PATCH\n\t#endif\n\t\n\t#if (RTL8822B_SUPPORT)\n\t\t/*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/\n\t#endif\n\t\n\t#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1) || defined(CONFIG_HL_SMART_ANTENNA_TYPE2))\n\t\t#define\tCONFIG_HL_SMART_ANTENNA\n\t#endif\n\n\t/* --------------------------------------------------*/\n\n#endif\n\n#if (RTL8822C_SUPPORT)\n\t#define CONFIG_PATH_DIVERSITY\n#endif\n\n/*[SmartAntenna]*/\n#define\tCONFIG_SMART_ANTENNA\n#ifdef CONFIG_SMART_ANTENNA\n\t/*#define\tCONFIG_CUMITEK_SMART_ANTENNA*/\n#endif\n\t/* --------------------------------------------------*/\n\n#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)\n\t#define\tCONFIG_RECEIVER_BLOCKING\n#endif\n\n#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\\\n\tRTL8192E_SUPPORT || RTL8723B_SUPPORT)\n\t#define\tCONFIG_RA_FW_DBG_CODE\n#endif\n\n/* #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR */\n#define CONFIG_DYNAMIC_TX_TWR\n/* #endif */\n#define\tCONFIG_PSD_TOOL\n#define PHYDM_SUPPORT_ADAPTIVITY\n#define\tPHYDM_SUPPORT_CCKPD\n/*#define\tCONFIG_RA_DYNAMIC_RTY_LIMIT*/\n#define CONFIG_ANT_DETECTION\n#define\tCONFIG_BB_TXBF_API\n#define\tODM_CONFIG_BT_COEXIST\n#define\tCONFIG_PHYDM_DFS_MASTER\n#define\tPHYDM_SUPPORT_RSSI_MONITOR\n#define\tPHYDM_AUTO_DEGBUG\n#define CONFIG_PHYDM_DEBUG_FUNCTION\n#define CFG_DIG_DAMPING_CHK\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\t#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT ||  RTL8192E_SUPPORT ||\\\n\t     RTL8814A_SUPPORT || RTL8881A_SUPPORT)\n\t\t#define\tPHYDM_BEAMFORMING_VERSION1\n\t#endif\n\t#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\\\n\t     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\\\n\t     RTL8822C_SUPPORT || RTL8814B_SUPPORT)\n\t\t#define\tDRIVER_BEAMFORMING_VERSION2\n\t#endif\n#endif\n\n#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT)\n\t/*#define CONFIG_DIRECTIONAL_BF*/\n#endif\n\n#if (RTL8822C_SUPPORT)\n\t#define CONFIG_MU_RSOML\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_hwconfig.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n ************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#define READ_AND_CONFIG_MP(ic, txt) (odm_read_and_config_mp_##ic##txt(dm))\n#define READ_AND_CONFIG_TC(ic, txt) (odm_read_and_config_tc_##ic##txt(dm))\n\n#if (PHYDM_TESTCHIP_SUPPORT == 1)\n#define READ_AND_CONFIG(ic, txt)                     \\\n\tdo {                                         \\\n\t\tif (dm->is_mp_chip)                  \\\n\t\t\tREAD_AND_CONFIG_MP(ic, txt); \\\n\t\telse                                 \\\n\t\t\tREAD_AND_CONFIG_TC(ic, txt); \\\n\t} while (0)\n#else\n#define READ_AND_CONFIG READ_AND_CONFIG_MP\n#endif\n\n#define GET_VERSION_MP(ic, txt) (odm_get_version_mp_##ic##txt())\n#define GET_VERSION_TC(ic, txt) (odm_get_version_tc_##ic##txt())\n\n#if (PHYDM_TESTCHIP_SUPPORT == 1)\n#define GET_VERSION(ic, txt) (dm->is_mp_chip ? GET_VERSION_MP(ic, txt) : GET_VERSION_TC(ic, txt))\n#else\n#define GET_VERSION(ic, txt) GET_VERSION_MP(ic, txt)\n#endif\n\nenum hal_status\nodm_config_rf_with_header_file(struct dm_struct *dm,\n\t\t\t       enum odm_rf_config_type config_type,\n\t\t\t       u8 e_rf_path)\n{\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tPMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;\n#endif\n\tenum hal_status result = HAL_STATUS_SUCCESS;\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"===>%s (%s)\\n\", __func__,\n\t\t  (dm->is_mp_chip) ? \"MPChip\" : \"TestChip\");\n\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t  \"support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\\n\",\n\t\t  dm->support_platform, dm->support_interface, dm->board_type);\n\n/* @1 AP doesn't use PHYDM power tracking table in these ICs */\n#if (DM_ODM_SUPPORT_TYPE != ODM_AP)\n#if (RTL8812A_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8812) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8812a, _radioa);\n\t\t\telse if (e_rf_path == RF_PATH_B)\n\t\t\t\tREAD_AND_CONFIG_MP(8812a, _radiob);\n\t\t} else if (config_type == CONFIG_RF_TXPWR_LMT) {\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE)\n\t\t\tHAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\t\t\tif ((hal_data->EEPROMSVID == 0x17AA && hal_data->EEPROMSMID == 0xA811) ||\n\t\t\t    (hal_data->EEPROMSVID == 0x10EC && hal_data->EEPROMSMID == 0xA812) ||\n\t\t\t    (hal_data->EEPROMSVID == 0x10EC && hal_data->EEPROMSMID == 0x8812))\n\t\t\t\tREAD_AND_CONFIG_MP(8812a, _txpwr_lmt_hm812a03);\n\t\t\telse\n#endif\n\t\t\t\tREAD_AND_CONFIG_MP(8812a, _txpwr_lmt);\n\t\t}\n\t}\n#endif\n#if (RTL8821A_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8821) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8821a, _radioa);\n\t\t} else if (config_type == CONFIG_RF_TXPWR_LMT) {\n\t\t\tif (dm->support_interface == ODM_ITRF_USB) {\n\t\t\t\tif (dm->ext_pa_5g || dm->ext_lna_5g)\n\t\t\t\t\tREAD_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_fem);\n\t\t\t\telse\n\t\t\t\t\tREAD_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_ipa);\n\t\t\t} else {\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t\t\t\tif (mgnt_info->CustomerID == RT_CID_8821AE_ASUS_MB)\n\t\t\t\t\tREAD_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_8mm);\n\t\t\t\telse if (mgnt_info->CustomerID == RT_CID_ASUS_NB)\n\t\t\t\t\tREAD_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_5mm);\n\t\t\t\telse\n#endif\n\t\t\t\t\tREAD_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a);\n\t\t\t}\n\t\t}\n\t}\n#endif\n#if (RTL8192E_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8192E) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8192e, _radioa);\n\t\t\telse if (e_rf_path == RF_PATH_B)\n\t\t\t\tREAD_AND_CONFIG_MP(8192e, _radiob);\n\t\t} else if (config_type == CONFIG_RF_TXPWR_LMT) {\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) /*Refine by Vincent Lan for 5mm SAR pwr limit*/\n\t\t\tHAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\n\t\t\tif ((hal_data->EEPROMSVID == 0x11AD && hal_data->EEPROMSMID == 0x8192) ||\n\t\t\t    (hal_data->EEPROMSVID == 0x11AD && hal_data->EEPROMSMID == 0x8193))\n\t\t\t\tREAD_AND_CONFIG_MP(8192e, _txpwr_lmt_8192e_sar_5mm);\n\t\t\telse\n#endif\n\t\t\t\tREAD_AND_CONFIG_MP(8192e, _txpwr_lmt);\n\t\t}\n\t}\n#endif\n#if (RTL8723D_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8723D) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8723d, _radioa);\n\t\t} else if (config_type == CONFIG_RF_TXPWR_LMT) {\n\t\t\tREAD_AND_CONFIG_MP(8723d, _txpwr_lmt);\n\t\t}\n\t}\n#endif\n/* @JJ ADD 20161014 */\n#if (RTL8710B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8710B) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8710b, _radioa);\n\t\t} else if (config_type == CONFIG_RF_TXPWR_LMT)\n\t\t\tREAD_AND_CONFIG_MP(8710b, _txpwr_lmt);\n\t}\n#endif\n\n#endif /* @(DM_ODM_SUPPORT_TYPE !=  ODM_AP) */\n/* @1 All platforms support */\n#if (RTL8188E_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8188E) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8188e, _radioa);\n\t\t} else if (config_type == CONFIG_RF_TXPWR_LMT)\n\t\t\tREAD_AND_CONFIG_MP(8188e, _txpwr_lmt);\n\t}\n#endif\n#if (RTL8723B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8723B) {\n\t\tif (config_type == CONFIG_RF_RADIO)\n\t\t\tREAD_AND_CONFIG_MP(8723b, _radioa);\n\t\telse if (config_type == CONFIG_RF_TXPWR_LMT)\n\t\t\tREAD_AND_CONFIG_MP(8723b, _txpwr_lmt);\n\t}\n#endif\n#if (RTL8814A_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8814A) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _radioa);\n\t\t\telse if (e_rf_path == RF_PATH_B)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _radiob);\n\t\t\telse if (e_rf_path == RF_PATH_C)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _radioc);\n\t\t\telse if (e_rf_path == RF_PATH_D)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _radiod);\n\t\t} else if (config_type == CONFIG_RF_TXPWR_LMT) {\n\t\t\tif (dm->rfe_type == 0)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _txpwr_lmt_type0);\n\t\t\telse if (dm->rfe_type == 1)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _txpwr_lmt_type1);\n\t\t\telse if (dm->rfe_type == 2)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _txpwr_lmt_type2);\n\t\t\telse if (dm->rfe_type == 3)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _txpwr_lmt_type3);\n\t\t\telse if (dm->rfe_type == 5)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _txpwr_lmt_type5);\n\t\t\telse if (dm->rfe_type == 7)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _txpwr_lmt_type7);\n\t\t\telse if (dm->rfe_type == 8)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _txpwr_lmt_type8);\n\t\t\telse\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _txpwr_lmt);\n\t\t}\n\t}\n#endif\n#if (RTL8703B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8703B) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8703b, _radioa);\n\t\t}\n\t}\n#endif\n#if (RTL8188F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8188F) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8188f, _radioa);\n\t\t} else if (config_type == CONFIG_RF_TXPWR_LMT)\n\t\t\tREAD_AND_CONFIG_MP(8188f, _txpwr_lmt);\n\t}\n#endif\n#if (RTL8822B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8822B) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _radioa);\n\t\t\telse if (e_rf_path == RF_PATH_B)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _radiob);\n\t\t} else if (config_type == CONFIG_RF_TXPWR_LMT) {\n\t\t\tif (dm->rfe_type == 5)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _txpwr_lmt_type5);\n\t\t\telse if (dm->rfe_type == 2)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _txpwr_lmt_type2);\n\t\t\telse if (dm->rfe_type == 3)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _txpwr_lmt_type3);\n\t\t\telse if (dm->rfe_type == 4)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _txpwr_lmt_type4);\n\t\t\telse if (dm->rfe_type == 12)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _txpwr_lmt_type12);\n\t\t\telse if (dm->rfe_type == 15)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _txpwr_lmt_type15);\n\t\t\telse if (dm->rfe_type == 16)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _txpwr_lmt_type16);\n\t\t\telse if (dm->rfe_type == 17)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _txpwr_lmt_type17);\n\t\t\telse if (dm->rfe_type == 18)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _txpwr_lmt_type18);\n\t\t\telse\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _txpwr_lmt);\n\t\t}\n\t}\n#endif\n\n#if (RTL8197F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8197F) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8197f, _radioa);\n\t\t\telse if (e_rf_path == RF_PATH_B)\n\t\t\t\tREAD_AND_CONFIG_MP(8197f, _radiob);\n\t\t}\n\t}\n#endif\n/*@jj add 20170822*/\n#if (RTL8192F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8192F) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _radioa);\n\t\t\telse if (e_rf_path == RF_PATH_B)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _radiob);\n\t\t} else if (config_type == CONFIG_RF_TXPWR_LMT) {\n\t\t\tif (dm->rfe_type == 0)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type0);\n\t\t\telse if (dm->rfe_type == 1)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type1);\n\t\t\telse if (dm->rfe_type == 2)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type2);\n\t\t\telse if (dm->rfe_type == 3)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type3);\n\t\t\telse if (dm->rfe_type == 4)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type4);\n\t\t\telse if (dm->rfe_type == 5)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type5);\n\t\t\telse if (dm->rfe_type == 6)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type6);\n\t\t\telse if (dm->rfe_type == 7)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type7);\n\t\t\telse if (dm->rfe_type == 8)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type8);\n\t\t\telse if (dm->rfe_type == 9)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type9);\n\t\t\telse if (dm->rfe_type == 10)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type10);\n\t\t\telse if (dm->rfe_type == 11)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type11);\n\t\t\telse if (dm->rfe_type == 12)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type12);\n\t\t\telse if (dm->rfe_type == 13)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type13);\n\t\t\telse if (dm->rfe_type == 14)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type14);\n\t\t\telse if (dm->rfe_type == 15)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type15);\n\t\t\telse if (dm->rfe_type == 16)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type16);\n\t\t\telse if (dm->rfe_type == 17)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type17);\n\t\t\telse if (dm->rfe_type == 18)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type18);\n\t\t\telse if (dm->rfe_type == 19)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type19);\n\t\t\telse if (dm->rfe_type == 20)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type20);\n\t\t\telse if (dm->rfe_type == 21)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type21);\n\t\t\telse if (dm->rfe_type == 22)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type22);\n\t\t\telse if (dm->rfe_type == 23)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type23);\n\t\t\telse if (dm->rfe_type == 24)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type24);\n\t\t\telse if (dm->rfe_type == 25)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type25);\n\t\t\telse if (dm->rfe_type == 26)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type26);\n\t\t\telse if (dm->rfe_type == 27)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type27);\n\t\t\telse if (dm->rfe_type == 28)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type28);\n\t\t\telse if (dm->rfe_type == 29)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type29);\n\t\t\telse if (dm->rfe_type == 30)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type30);\n\t\t\telse if (dm->rfe_type == 31)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt_type31);\n\t\t\telse\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _txpwr_lmt);\n\t\t}\n\t}\n#endif\n#if (RTL8721D_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8721D) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8721d, _radioa);\n\t\t} else if (config_type == CONFIG_RF_TXPWR_LMT)\n\t\t\tREAD_AND_CONFIG_MP(8721d, _txpwr_lmt);\n\t}\n#endif\n#if (RTL8821C_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8821C) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG(8821c, _radioa);\n\t\t} else if (config_type == CONFIG_RF_TXPWR_LMT) {\n\t\t\tREAD_AND_CONFIG(8821c, _txpwr_lmt);\n\t\t}\n\t}\n#endif\n#if (RTL8195B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8195B) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG(8195b, _radioa);\n\t\t}\n\t\t#if 0\n\t\telse if (config_type == CONFIG_RF_TXPWR_LMT) {\n\t\t\tREAD_AND_CONFIG(8821c, _txpwr_lmt);\n\t\t\t/*@*/\n\t\t}\n\t\t#endif\n\t}\n#endif\n#if (RTL8198F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8198F) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8198f, _radioa);\n\t\t\telse if (e_rf_path == RF_PATH_B)\n\t\t\t\tREAD_AND_CONFIG_MP(8198f, _radiob);\n\t\t\telse if (e_rf_path == RF_PATH_C)\n\t\t\t\tREAD_AND_CONFIG_MP(8198f, _radioc);\n\t\t\telse if (e_rf_path == RF_PATH_D)\n\t\t\t\tREAD_AND_CONFIG_MP(8198f, _radiod);\n\t\t}\n\t}\n#endif\n/*#if (RTL8814B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8814B) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8814b, _radioa);\n\t\t\telse if (e_rf_path == RF_PATH_B)\n\t\t\t\tREAD_AND_CONFIG_MP(8814b, _radiob);\n\t\t\telse if (e_rf_path == RF_PATH_C)\n\t\t\t\tREAD_AND_CONFIG_MP(8814b, _radioc);\n\t\t\telse if (e_rf_path == RF_PATH_D)\n\t\t\t\tREAD_AND_CONFIG_MP(8814b, _radiod);\n\t\t}\n\t}\n#endif\n*/\n#if (RTL8822C_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8822C) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8822c, _radioa);\n\t\t\telse if (e_rf_path == RF_PATH_B)\n\t\t\t\tREAD_AND_CONFIG_MP(8822c, _radiob);\n\t\t} else if (config_type == CONFIG_RF_TXPWR_LMT) {\n\t\t\tREAD_AND_CONFIG_MP(8822c, _txpwr_lmt);\n\t\t}\n\t}\n#endif\n#if (RTL8812F_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8812F) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8812f, _radioa);\n\t\t\telse if (e_rf_path == RF_PATH_B)\n\t\t\t\tREAD_AND_CONFIG_MP(8812f, _radiob);\n\t\t}\n\t}\n#endif\n\n /*8814B need review, when phydm has related files*/\n #if (RTL8814B_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8814B) {\n\t\tif (config_type == CONFIG_RF_RADIO) {\n\t\t\tif (e_rf_path == RF_PATH_A)\n\t\t\t\tREAD_AND_CONFIG_MP(8814b, _radioa);\n\t\t\telse if (e_rf_path == RF_PATH_B)\n\t\t\t\tREAD_AND_CONFIG_MP(8814b, _radiob);\n\t\t\telse if (e_rf_path == RF_PATH_C)\n\t\t\t\tREAD_AND_CONFIG_MP(8814b, _radioc);\n\t\t\telse if (e_rf_path == RF_PATH_D)\n\t\t\t\tREAD_AND_CONFIG_MP(8814b, _radiod);\n\t\t}\n\t\tif (config_type == CONFIG_RF_SYN_RADIO) {\n\t\t\tif (e_rf_path == RF_SYN0)\n\t\t\t\tREAD_AND_CONFIG_MP(8814b, _radiosyn0);\n\t\t\telse if (e_rf_path == RF_SYN1)\n\t\t\t\tREAD_AND_CONFIG_MP(8814b, _radiosyn1);\n\t\t}\n\t}\n  #endif\n\n\tif (config_type == CONFIG_RF_RADIO) {\n\t\tif (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {\n\t\t\tresult = phydm_set_reg_by_fw(dm,\n\t\t\t\t\t\t     PHYDM_HALMAC_CMD_END,\n\t\t\t\t\t\t     0,\n\t\t\t\t\t\t     0,\n\t\t\t\t\t\t     0,\n\t\t\t\t\t\t     (enum rf_path)0,\n\t\t\t\t\t\t     0);\n\t\t\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t\t\t  \"rf param offload end!result = %d\", result);\n\t\t}\n\t}\n\n\treturn result;\n}\n\nenum hal_status\nodm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm)\n{\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"===>%s (%s)\\n\", __func__,\n\t\t  (dm->is_mp_chip) ? \"MPChip\" : \"TestChip\");\n\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t  \"support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\\n\",\n\t\t  dm->support_platform, dm->support_interface, dm->board_type);\n\n/* @1 AP doesn't use PHYDM power tracking table in these ICs */\n#if (DM_ODM_SUPPORT_TYPE != ODM_AP)\n#if RTL8821A_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8821) {\n\t\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\t\tREAD_AND_CONFIG_MP(8821a, _txpowertrack_pcie);\n\t\telse if (dm->support_interface == ODM_ITRF_USB)\n\t\t\tREAD_AND_CONFIG_MP(8821a, _txpowertrack_usb);\n\t\telse if (dm->support_interface == ODM_ITRF_SDIO)\n\t\t\tREAD_AND_CONFIG_MP(8821a, _txpowertrack_sdio);\n\t}\n#endif\n#if RTL8812A_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8812) {\n\t\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\t\tREAD_AND_CONFIG_MP(8812a, _txpowertrack_pcie);\n\t\telse if (dm->support_interface == ODM_ITRF_USB) {\n\t\t\tif (dm->rfe_type == 3 && dm->is_mp_chip)\n\t\t\t\tREAD_AND_CONFIG_MP(8812a, _txpowertrack_rfe3);\n\t\t\telse\n\t\t\t\tREAD_AND_CONFIG_MP(8812a, _txpowertrack_usb);\n\t\t}\n\t}\n#endif\n#if RTL8192E_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8192E) {\n\t\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\t\tREAD_AND_CONFIG_MP(8192e, _txpowertrack_pcie);\n\t\telse if (dm->support_interface == ODM_ITRF_USB)\n\t\t\tREAD_AND_CONFIG_MP(8192e, _txpowertrack_usb);\n\t\telse if (dm->support_interface == ODM_ITRF_SDIO)\n\t\t\tREAD_AND_CONFIG_MP(8192e, _txpowertrack_sdio);\n\t}\n#endif\n#if RTL8723D_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8723D) {\n\t\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\t\tREAD_AND_CONFIG_MP(8723d, _txpowertrack_pcie);\n\t\telse if (dm->support_interface == ODM_ITRF_USB)\n\t\t\tREAD_AND_CONFIG_MP(8723d, _txpowertrack_usb);\n\t\telse if (dm->support_interface == ODM_ITRF_SDIO)\n\t\t\tREAD_AND_CONFIG_MP(8723d, _txpowertrack_sdio);\n\n\t\tREAD_AND_CONFIG_MP(8723d, _txxtaltrack);\n\t}\n#endif\n/* @JJ ADD 20161014 */\n#if RTL8710B_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8710B) {\n\t\tif (dm->package_type == 1)\n\t\t\tREAD_AND_CONFIG_MP(8710b, _txpowertrack_qfn48m_smic);\n\t\telse if (dm->package_type == 5)\n\t\t\tREAD_AND_CONFIG_MP(8710b, _txpowertrack_qfn48m_umc);\n\n\t\tREAD_AND_CONFIG_MP(8710b, _txxtaltrack);\n\t}\n#endif\n#if RTL8188E_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8188E) {\n\t\tif (odm_get_mac_reg(dm, R_0xf0, 0xF000) >= 8) { /*@if 0xF0[15:12] >= 8, SMIC*/\n\t\t\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\t\t\tREAD_AND_CONFIG_MP(8188e, _txpowertrack_pcie_icut);\n\t\t\telse if (dm->support_interface == ODM_ITRF_USB)\n\t\t\t\tREAD_AND_CONFIG_MP(8188e, _txpowertrack_usb_icut);\n\t\t\telse if (dm->support_interface == ODM_ITRF_SDIO)\n\t\t\t\tREAD_AND_CONFIG_MP(8188e, _txpowertrack_sdio_icut);\n\t\t} else { /*@else 0xF0[15:12] < 8, TSMC*/\n\t\t\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\t\t\tREAD_AND_CONFIG_MP(8188e, _txpowertrack_pcie);\n\t\t\telse if (dm->support_interface == ODM_ITRF_USB)\n\t\t\t\tREAD_AND_CONFIG_MP(8188e, _txpowertrack_usb);\n\t\t\telse if (dm->support_interface == ODM_ITRF_SDIO)\n\t\t\t\tREAD_AND_CONFIG_MP(8188e, _txpowertrack_sdio);\n\t\t}\n\t}\n#endif\n#endif /* @(DM_ODM_SUPPORT_TYPE !=  ODM_AP) */\n/* @1 All platforms support */\n#if RTL8723B_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8723B) {\n\t\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\t\tREAD_AND_CONFIG_MP(8723b, _txpowertrack_pcie);\n\t\telse if (dm->support_interface == ODM_ITRF_USB)\n\t\t\tREAD_AND_CONFIG_MP(8723b, _txpowertrack_usb);\n\t\telse if (dm->support_interface == ODM_ITRF_SDIO)\n\t\t\tREAD_AND_CONFIG_MP(8723b, _txpowertrack_sdio);\n\t}\n#endif\n#if RTL8814A_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8814A) {\n\t\tif (dm->rfe_type == 0)\n\t\t\tREAD_AND_CONFIG_MP(8814a, _txpowertrack_type0);\n\t\telse if (dm->rfe_type == 2)\n\t\t\tREAD_AND_CONFIG_MP(8814a, _txpowertrack_type2);\n\t\telse if (dm->rfe_type == 5)\n\t\t\tREAD_AND_CONFIG_MP(8814a, _txpowertrack_type5);\n\t\telse if (dm->rfe_type == 7)\n\t\t\tREAD_AND_CONFIG_MP(8814a, _txpowertrack_type7);\n\t\telse if (dm->rfe_type == 8)\n\t\t\tREAD_AND_CONFIG_MP(8814a, _txpowertrack_type8);\n\t\telse\n\t\t\tREAD_AND_CONFIG_MP(8814a, _txpowertrack);\n\n\t\tREAD_AND_CONFIG_MP(8814a, _txpowertssi);\n\t}\n#endif\n#if RTL8703B_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8703B) {\n\t\tif (dm->support_interface == ODM_ITRF_USB)\n\t\t\tREAD_AND_CONFIG_MP(8703b, _txpowertrack_usb);\n\t\telse if (dm->support_interface == ODM_ITRF_SDIO)\n\t\t\tREAD_AND_CONFIG_MP(8703b, _txpowertrack_sdio);\n\n\t\tREAD_AND_CONFIG_MP(8703b, _txxtaltrack);\n\t}\n#endif\n#if RTL8188F_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8188F) {\n\t\tif (dm->support_interface == ODM_ITRF_USB)\n\t\t\tREAD_AND_CONFIG_MP(8188f, _txpowertrack_usb);\n\t\telse if (dm->support_interface == ODM_ITRF_SDIO)\n\t\t\tREAD_AND_CONFIG_MP(8188f, _txpowertrack_sdio);\n\t}\n#endif\n#if RTL8822B_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8822B) {\n\t\tif (dm->rfe_type == 0)\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type0);\n\t\telse if (dm->rfe_type == 1)\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type1);\n\t\telse if (dm->rfe_type == 2)\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type2);\n\t\telse if ((dm->rfe_type == 3) || (dm->rfe_type == 5))\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type3_type5);\n\t\telse if (dm->rfe_type == 4)\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type4);\n\t\telse if (dm->rfe_type == 6)\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type6);\n\t\telse if (dm->rfe_type == 7)\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type7);\n\t\telse if (dm->rfe_type == 8)\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type8);\n\t\telse if (dm->rfe_type == 9)\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type9);\n\t\telse if (dm->rfe_type == 10)\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type10);\n\t\telse if (dm->rfe_type == 11)\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type11);\n\t\telse if (dm->rfe_type == 12)\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type12);\n\t\telse if (dm->rfe_type == 13)\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type13);\n\t\telse if (dm->rfe_type == 14)\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type14);\n\t\telse if (dm->rfe_type == 15)\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type15);\n\t\telse if (dm->rfe_type == 16)\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type16);\n\t\telse if (dm->rfe_type == 17)\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type17);\n\t\telse if (dm->rfe_type == 18)\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack_type18);\n\t\telse\n\t\t\tREAD_AND_CONFIG_MP(8822b, _txpowertrack);\n\t}\n#endif\n#if RTL8197F_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8197F) {\n\t\tif (dm->rfe_type == 0)\n\t\t\tREAD_AND_CONFIG_MP(8197f, _txpowertrack_type0);\n\t\telse if (dm->rfe_type == 1)\n\t\t\tREAD_AND_CONFIG_MP(8197f, _txpowertrack_type1);\n\t\telse\n\t\t\tREAD_AND_CONFIG_MP(8197f, _txpowertrack);\n\t}\n#endif\n/*@jj add 20170822*/\n#if RTL8192F_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8192F) {\n\t\tif (dm->rfe_type == 0)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type0);\n\t\telse if (dm->rfe_type == 1)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type1);\n\t\telse if (dm->rfe_type == 2)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type2);\n\t\telse if (dm->rfe_type == 3)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type3);\n\t\telse if (dm->rfe_type == 4)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type4);\n\t\telse if (dm->rfe_type == 5)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type5);\n\t\telse if (dm->rfe_type == 6)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type6);\n\t\telse if (dm->rfe_type == 7)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type7);\n\t\telse if (dm->rfe_type == 8)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type8);\n\t\telse if (dm->rfe_type == 9)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type9);\n\t\telse if (dm->rfe_type == 10)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type10);\n\t\telse if (dm->rfe_type == 11)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type11);\n\t\telse if (dm->rfe_type == 12)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type12);\n\t\telse if (dm->rfe_type == 13)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type13);\n\t\telse if (dm->rfe_type == 14)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type14);\n\t\telse if (dm->rfe_type == 15)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type15);\n\t\telse if (dm->rfe_type == 16)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type16);\n\t\telse if (dm->rfe_type == 17)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type17);\n\t\telse if (dm->rfe_type == 18)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type18);\n\t\telse if (dm->rfe_type == 19)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type19);\n\t\telse if (dm->rfe_type == 20)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type20);\n\t\telse if (dm->rfe_type == 21)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type21);\n\t\telse if (dm->rfe_type == 22)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type22);\n\t\telse if (dm->rfe_type == 23)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type23);\n\t\telse if (dm->rfe_type == 24)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type24);\n\t\telse if (dm->rfe_type == 25)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type25);\n\t\telse if (dm->rfe_type == 26)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type26);\n\t\telse if (dm->rfe_type == 27)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type27);\n\t\telse if (dm->rfe_type == 28)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type28);\n\t\telse if (dm->rfe_type == 29)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type29);\n\t\telse if (dm->rfe_type == 30)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type30);\n\t\telse if (dm->rfe_type == 31)\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack_type31);\n\t\telse\n\t\t\tREAD_AND_CONFIG_MP(8192f, _txpowertrack);\n\n\t\tREAD_AND_CONFIG_MP(8192f, _txxtaltrack);\n\t}\n#endif\n\n#if RTL8721D_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8721D) {\n\t\t#if 0\n\t\tif (dm->package_type == 1)\n\t\t\tREAD_AND_CONFIG_MP(8721d, _txpowertrack_qfn48m_smic);\n\t\telse if (dm->package_type == 5)\n\t\t\tREAD_AND_CONFIG_MP(8721d, _txpowertrack_qfn48m_umc);\n\t\t#endif\n\t\tREAD_AND_CONFIG_MP(8721d, _txpowertrack);\n\t\tREAD_AND_CONFIG_MP(8721d, _txxtaltrack);\n\t}\n#endif\n#if RTL8821C_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8821C) {\n\t\tif (dm->rfe_type == 0x5)\n\t\t\tREAD_AND_CONFIG(8821c, _txpowertrack_type0x28);\n\t\telse if (dm->rfe_type == 0x4)\n\t\t\tREAD_AND_CONFIG(8821c, _txpowertrack_type0x20);\n\t\telse\n\t\t\tREAD_AND_CONFIG(8821c, _txpowertrack);\n\t}\n#endif\n\n#if RTL8198F_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8198F) {\n\t\tif (dm->rfe_type == 0)\n\t\t\tREAD_AND_CONFIG_MP(8198f, _txpowertrack_type0);\n\t\telse if (dm->rfe_type == 1)\n\t\t\tREAD_AND_CONFIG_MP(8198f, _txpowertrack_type1);\n\t\telse\n\t\t\tREAD_AND_CONFIG_MP(8198f, _txpowertrack);\n\t\t}\n#endif\n\n#if RTL8195B_SUPPORT\n\tif (dm->support_ic_type == ODM_RTL8195B) {\n\t\tREAD_AND_CONFIG_MP(8195b, _txpowertrack);\n\t\tREAD_AND_CONFIG_MP(8195b, _txxtaltrack);\n\t}\n#endif\n\n#if (RTL8822C_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8822C)\n\t\tREAD_AND_CONFIG_MP(8822c, _txpowertrack);\n#endif\n\n#if (RTL8812F_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8812F)\n\t\tREAD_AND_CONFIG_MP(8812f, _txpowertrack);\n#endif\n\n#if RTL8814B_SUPPORT\n\t\tif (dm->support_ic_type == ODM_RTL8814B)\n\t\t\tREAD_AND_CONFIG_MP(8814b, _txpowertrack);\n#endif\n\n\treturn HAL_STATUS_SUCCESS;\n}\n\nenum hal_status\nodm_config_bb_with_header_file(struct dm_struct *dm,\n\t\t\t       enum odm_bb_config_type config_type)\n{\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tPMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;\n#endif\n\tenum hal_status result = HAL_STATUS_SUCCESS;\n\n/* @1 AP doesn't use PHYDM initialization in these ICs */\n#if (DM_ODM_SUPPORT_TYPE != ODM_AP)\n#if (RTL8812A_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8812) {\n\t\tif (config_type == CONFIG_BB_PHY_REG)\n\t\t\tREAD_AND_CONFIG_MP(8812a, _phy_reg);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG_MP(8812a, _agc_tab);\n\t\telse if (config_type == CONFIG_BB_PHY_REG_PG) {\n\t\t\tif (dm->rfe_type == 3 && dm->is_mp_chip)\n\t\t\t\tREAD_AND_CONFIG_MP(8812a, _phy_reg_pg_asus);\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t\t\telse if (mgnt_info->CustomerID == RT_CID_WNC_NEC && dm->is_mp_chip)\n\t\t\t\tREAD_AND_CONFIG_MP(8812a, _phy_reg_pg_nec);\n#if RT_PLATFORM == PLATFORM_MACOSX\n\t\t\t/*@{1827}{1024} for BUFFALO power by rate table. Isaiah 2013-11-29*/\n\t\t\telse if (mgnt_info->CustomerID == RT_CID_DNI_BUFFALO)\n\t\t\t\tREAD_AND_CONFIG_MP(8812a, _phy_reg_pg_dni);\n\t\t\t/* TP-Link T4UH, Isaiah 2015-03-16*/\n\t\t\telse if (mgnt_info->CustomerID == RT_CID_TPLINK_HPWR) {\n\t\t\t\tpr_debug(\"RT_CID_TPLINK_HPWR:: _PHY_REG_PG_TPLINK\\n\");\n\t\t\t\tREAD_AND_CONFIG_MP(8812a, _phy_reg_pg_tplink);\n\t\t\t}\n#endif\n#endif\n\t\t\telse\n\t\t\t\tREAD_AND_CONFIG_MP(8812a, _phy_reg_pg);\n\t\t} else if (config_type == CONFIG_BB_PHY_REG_MP)\n\t\t\tREAD_AND_CONFIG_MP(8812a, _phy_reg_mp);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB_DIFF) {\n\t\t\tdm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD;\n\t\t\t/*@AGC_TAB DIFF dont support FW offload*/\n\t\t\tif ((*dm->channel >= 36) && (*dm->channel <= 64))\n\t\t\t\tAGC_DIFF_CONFIG_MP(8812a, lb);\n\t\t\telse if (*dm->channel >= 100)\n\t\t\t\tAGC_DIFF_CONFIG_MP(8812a, hb);\n\t\t}\n\t}\n#endif\n#if (RTL8821A_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8821) {\n\t\tif (config_type == CONFIG_BB_PHY_REG)\n\t\t\tREAD_AND_CONFIG_MP(8821a, _phy_reg);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG_MP(8821a, _agc_tab);\n\t\telse if (config_type == CONFIG_BB_PHY_REG_PG) {\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)\n\t\t\tHAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\n\t\t\tif ((hal_data->EEPROMSVID == 0x1043 && hal_data->EEPROMSMID == 0x207F))\n\t\t\t\tREAD_AND_CONFIG_MP(8821a, _phy_reg_pg_e202_sa);\n\t\t\telse\n#endif\n#if (RT_PLATFORM == PLATFORM_MACOSX)\n\t\t\t\t/*@  for BUFFALO pwr by rate table */\n\t\t\t\tif (mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) {\n\t\t\t\t/*@  for BUFFALO pwr by rate table (JP/US)*/\n\t\t\t\tif (mgnt_info->ChannelPlan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G)\n\t\t\t\t\tREAD_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_us);\n\t\t\t\telse\n\t\t\t\t\tREAD_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_jp);\n\t\t\t} else\n#endif\n#endif\n\t\t\t\tREAD_AND_CONFIG_MP(8821a, _phy_reg_pg);\n\t\t}\n\t}\n#endif\n#if (RTL8192E_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8192E) {\n\t\tif (config_type == CONFIG_BB_PHY_REG)\n\t\t\tREAD_AND_CONFIG_MP(8192e, _phy_reg);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG_MP(8192e, _agc_tab);\n\t\telse if (config_type == CONFIG_BB_PHY_REG_PG)\n\t\t\tREAD_AND_CONFIG_MP(8192e, _phy_reg_pg);\n\t}\n#endif\n#if (RTL8723D_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8723D) {\n\t\tif (config_type == CONFIG_BB_PHY_REG)\n\t\t\tREAD_AND_CONFIG_MP(8723d, _phy_reg);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG_MP(8723d, _agc_tab);\n\t\telse if (config_type == CONFIG_BB_PHY_REG_PG)\n\t\t\tREAD_AND_CONFIG_MP(8723d, _phy_reg_pg);\n\t}\n#endif\n/* @JJ ADD 20161014 */\n#if (RTL8710B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8710B) {\n\t\tif (config_type == CONFIG_BB_PHY_REG)\n\t\t\tREAD_AND_CONFIG_MP(8710b, _phy_reg);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG_MP(8710b, _agc_tab);\n\t\telse if (config_type == CONFIG_BB_PHY_REG_PG)\n\t\t\tREAD_AND_CONFIG_MP(8710b, _phy_reg_pg);\n\t}\n#endif\n\n#endif /* @(DM_ODM_SUPPORT_TYPE !=  ODM_AP) */\n/* @1 All platforms support */\n#if (RTL8188E_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8188E) {\n\t\tif (config_type == CONFIG_BB_PHY_REG)\n\t\t\tREAD_AND_CONFIG_MP(8188e, _phy_reg);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG_MP(8188e, _agc_tab);\n\t\telse if (config_type == CONFIG_BB_PHY_REG_PG)\n\t\t\tREAD_AND_CONFIG_MP(8188e, _phy_reg_pg);\n\t}\n#endif\n#if (RTL8723B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8723B) {\n\t\tif (config_type == CONFIG_BB_PHY_REG)\n\t\t\tREAD_AND_CONFIG_MP(8723b, _phy_reg);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG_MP(8723b, _agc_tab);\n\t\telse if (config_type == CONFIG_BB_PHY_REG_PG)\n\t\t\tREAD_AND_CONFIG_MP(8723b, _phy_reg_pg);\n\t}\n#endif\n#if (RTL8814A_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8814A) {\n\t\tif (config_type == CONFIG_BB_PHY_REG)\n\t\t\tREAD_AND_CONFIG_MP(8814a, _phy_reg);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG_MP(8814a, _agc_tab);\n\t\telse if (config_type == CONFIG_BB_PHY_REG_PG) {\n\t\t\tif (dm->rfe_type == 0)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _phy_reg_pg_type0);\n\t\t\telse if (dm->rfe_type == 2)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _phy_reg_pg_type2);\n\t\t\telse if (dm->rfe_type == 3)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _phy_reg_pg_type3);\n\t\t\telse if (dm->rfe_type == 4)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _phy_reg_pg_type4);\n\t\t\telse if (dm->rfe_type == 5)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _phy_reg_pg_type5);\n\t\t\telse if (dm->rfe_type == 7)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _phy_reg_pg_type7);\n\t\t\telse if (dm->rfe_type == 8)\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _phy_reg_pg_type8);\n\t\t\telse\n\t\t\t\tREAD_AND_CONFIG_MP(8814a, _phy_reg_pg);\n\t\t} else if (config_type == CONFIG_BB_PHY_REG_MP)\n\t\t\tREAD_AND_CONFIG_MP(8814a, _phy_reg_mp);\n\t}\n#endif\n#if (RTL8703B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8703B) {\n\t\tif (config_type == CONFIG_BB_PHY_REG)\n\t\t\tREAD_AND_CONFIG_MP(8703b, _phy_reg);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG_MP(8703b, _agc_tab);\n\t\telse if (config_type == CONFIG_BB_PHY_REG_PG)\n\t\t\tREAD_AND_CONFIG_MP(8703b, _phy_reg_pg);\n\t}\n#endif\n#if (RTL8188F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8188F) {\n\t\tif (config_type == CONFIG_BB_PHY_REG)\n\t\t\tREAD_AND_CONFIG_MP(8188f, _phy_reg);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG_MP(8188f, _agc_tab);\n\t\telse if (config_type == CONFIG_BB_PHY_REG_PG)\n\t\t\tREAD_AND_CONFIG_MP(8188f, _phy_reg_pg);\n\t}\n#endif\n#if (RTL8822B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8822B) {\n\t\tif (config_type == CONFIG_BB_PHY_REG) {\n\t\t\tREAD_AND_CONFIG_MP(8822b, _phy_reg);\n\t\t} else if (config_type == CONFIG_BB_AGC_TAB) {\n\t\t\tREAD_AND_CONFIG_MP(8822b, _agc_tab);\n\t\t} else if (config_type == CONFIG_BB_PHY_REG_PG) {\n\t\t\tif (dm->rfe_type == 2)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _phy_reg_pg_type2);\n\t\t\telse if (dm->rfe_type == 3)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _phy_reg_pg_type3);\n\t\t\telse if (dm->rfe_type == 4)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _phy_reg_pg_type4);\n\t\t\telse if (dm->rfe_type == 5)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _phy_reg_pg_type5);\n\t\t\telse if (dm->rfe_type == 12)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _phy_reg_pg_type12);\n\t\t\telse if (dm->rfe_type == 15)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _phy_reg_pg_type15);\n\t\t\telse if (dm->rfe_type == 16)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _phy_reg_pg_type16);\n\t\t\telse if (dm->rfe_type == 17)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _phy_reg_pg_type17);\n\t\t\telse if (dm->rfe_type == 18)\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _phy_reg_pg_type18);\n\t\t\telse\n\t\t\t\tREAD_AND_CONFIG_MP(8822b, _phy_reg_pg);\n\t\t}\n\t}\n#endif\n\n#if (RTL8197F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8197F) {\n\t\tif (config_type == CONFIG_BB_PHY_REG) {\n\t\t\tREAD_AND_CONFIG_MP(8197f, _phy_reg);\n\t\t\tif (dm->cut_version == ODM_CUT_A)\n\t\t\t\tphydm_phypara_a_cut(dm);\n\t\t} else if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG_MP(8197f, _agc_tab);\n\t}\n#endif\n/*@jj add 20170822*/\n#if (RTL8192F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8192F) {\n\t\tif (config_type == CONFIG_BB_PHY_REG) {\n\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg);\n\t\t} else if (config_type == CONFIG_BB_AGC_TAB) {\n\t\t\tREAD_AND_CONFIG_MP(8192f, _agc_tab);\n\t\t} else if (config_type == CONFIG_BB_PHY_REG_PG) {\n\t\t\tif (dm->rfe_type == 0)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type0);\n\t\t\telse if (dm->rfe_type == 1)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type1);\n\t\t\telse if (dm->rfe_type == 2)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type2);\n\t\t\telse if (dm->rfe_type == 3)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type3);\n\t\t\telse if (dm->rfe_type == 4)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type4);\n\t\t\telse if (dm->rfe_type == 5)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type5);\n\t\t\telse if (dm->rfe_type == 6)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type6);\n\t\t\telse if (dm->rfe_type == 7)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type7);\n\t\t\telse if (dm->rfe_type == 8)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type8);\n\t\t\telse if (dm->rfe_type == 9)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type9);\n\t\t\telse if (dm->rfe_type == 10)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type10);\n\t\t\telse if (dm->rfe_type == 11)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type11);\n\t\t\telse if (dm->rfe_type == 12)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type12);\n\t\t\telse if (dm->rfe_type == 13)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type13);\n\t\t\telse if (dm->rfe_type == 14)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type14);\n\t\t\telse if (dm->rfe_type == 15)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type15);\n\t\t\telse if (dm->rfe_type == 16)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type16);\n\t\t\telse if (dm->rfe_type == 17)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type17);\n\t\t\telse if (dm->rfe_type == 18)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type18);\n\t\t\telse if (dm->rfe_type == 19)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type19);\n\t\t\telse if (dm->rfe_type == 20)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type20);\n\t\t\telse if (dm->rfe_type == 21)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type21);\n\t\t\telse if (dm->rfe_type == 22)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type22);\n\t\t\telse if (dm->rfe_type == 23)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type23);\n\t\t\telse if (dm->rfe_type == 24)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type24);\n\t\t\telse if (dm->rfe_type == 25)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type25);\n\t\t\telse if (dm->rfe_type == 26)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type26);\n\t\t\telse if (dm->rfe_type == 27)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type27);\n\t\t\telse if (dm->rfe_type == 28)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type28);\n\t\t\telse if (dm->rfe_type == 29)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type29);\n\t\t\telse if (dm->rfe_type == 30)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type30);\n\t\t\telse if (dm->rfe_type == 31)\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg_type31);\n\t\t\telse\n\t\t\t\tREAD_AND_CONFIG_MP(8192f, _phy_reg_pg);\n\t\t}\n\t}\n#endif\n#if (RTL8721D_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8721D) {\n\t\tif (config_type == CONFIG_BB_PHY_REG)\n\t\t\tREAD_AND_CONFIG_MP(8721d, _phy_reg);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG_MP(8721d, _agc_tab);\n\t\telse if (config_type == CONFIG_BB_PHY_REG_PG)\n\t\t\tREAD_AND_CONFIG_MP(8721d, _phy_reg_pg);\n\t}\n#endif\n#if (RTL8821C_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8821C) {\n\t\tif (config_type == CONFIG_BB_PHY_REG) {\n\t\t\tREAD_AND_CONFIG(8821c, _phy_reg);\n\t\t} else if (config_type == CONFIG_BB_AGC_TAB) {\n\t\t\tREAD_AND_CONFIG(8821c, _agc_tab);\n\t\t\t/* @According to RFEtype, choosing correct AGC table*/\n\t\t\tif (dm->default_rf_set_8821c == SWITCH_TO_BTG)\n\t\t\t\tAGC_DIFF_CONFIG_MP(8821c, btg);\n\t\t} else if (config_type == CONFIG_BB_PHY_REG_PG) {\n\t\t\tif (dm->rfe_type == 0x5)\n\t\t\t\tREAD_AND_CONFIG(8821c, _phy_reg_pg_type0x28);\n\t\t\telse\n\t\t\t\tREAD_AND_CONFIG(8821c, _phy_reg_pg);\n\t\t} else if (config_type == CONFIG_BB_AGC_TAB_DIFF) {\n\t\t\tdm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD;\n\t\t\t/*@AGC_TAB DIFF dont support FW offload*/\n\t\t\tif (dm->current_rf_set_8821c == SWITCH_TO_BTG)\n\t\t\t\tAGC_DIFF_CONFIG_MP(8821c, btg);\n\t\t\telse if (dm->current_rf_set_8821c == SWITCH_TO_WLG)\n\t\t\t\tAGC_DIFF_CONFIG_MP(8821c, wlg);\n\t\t} else if (config_type == CONFIG_BB_PHY_REG_MP) {\n\t\t\tREAD_AND_CONFIG(8821c, _phy_reg_mp);\n\t\t}\n\t}\n#endif\n\n#if (RTL8195A_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8195A) {\n\t\tif (config_type == CONFIG_BB_PHY_REG)\n\t\t\tREAD_AND_CONFIG(8195a, _phy_reg);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG(8195a, _agc_tab);\n\t\telse if (config_type == CONFIG_BB_PHY_REG_PG)\n\t\t\tREAD_AND_CONFIG(8195a, _phy_reg_pg);\n\t}\n#endif\n#if (RTL8195B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8195B) {\n\t\tif (config_type == CONFIG_BB_PHY_REG)\n\t\t\tREAD_AND_CONFIG(8195b, _phy_reg);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG(8195b, _agc_tab);\n\t\telse if (config_type == CONFIG_BB_PHY_REG_PG)\n\t\t\tREAD_AND_CONFIG(8195b, _phy_reg_pg);\n\t}\n#endif\n#if (RTL8198F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8198F) {\n\t\tif (config_type == CONFIG_BB_PHY_REG)\n\t\t\tREAD_AND_CONFIG_MP(8198f, _phy_reg);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG_MP(8198f, _agc_tab);\n\t}\n#endif\n#if (RTL8814B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8814B) {\n\t\tif (config_type == CONFIG_BB_PHY_REG)\n\t\t\tREAD_AND_CONFIG_MP(8814b, _phy_reg);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG_MP(8814b, _agc_tab);\n\t\telse if (config_type == CONFIG_BB_PHY_REG_PG)\n\t\t\tREAD_AND_CONFIG(8814b, _phy_reg_pg);\n\t}\n#endif\n#if (RTL8822C_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8822C) {\n\t\tif (config_type == CONFIG_BB_PHY_REG)\n\t\t\tREAD_AND_CONFIG_MP(8822c, _phy_reg);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG_MP(8822c, _agc_tab);\n\t\telse if (config_type == CONFIG_BB_PHY_REG_PG)\n\t\t\tREAD_AND_CONFIG(8822c, _phy_reg_pg);\n\t}\n#endif\n#if (RTL8812F_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8812F) {\n\t\tif (config_type == CONFIG_BB_PHY_REG)\n\t\t\tREAD_AND_CONFIG_MP(8812f, _phy_reg);\n\t\telse if (config_type == CONFIG_BB_AGC_TAB)\n\t\t\tREAD_AND_CONFIG_MP(8812f, _agc_tab);\n\t\telse if (config_type == CONFIG_BB_PHY_REG_PG)\n\t\t\tREAD_AND_CONFIG(8812f, _phy_reg_pg);\n\t}\n#endif\n\n\tif (config_type == CONFIG_BB_PHY_REG ||\n\t    config_type == CONFIG_BB_AGC_TAB)\n\t\tif (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {\n\t\t\tresult = phydm_set_reg_by_fw(dm,\n\t\t\t\t\t\t     PHYDM_HALMAC_CMD_END,\n\t\t\t\t\t\t     0,\n\t\t\t\t\t\t     0,\n\t\t\t\t\t\t     0,\n\t\t\t\t\t\t     (enum rf_path)0,\n\t\t\t\t\t\t     0);\n\t\t\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t\t\t  \"phy param offload end!result = %d\", result);\n\t\t}\n\n\treturn result;\n}\n\nenum hal_status\nodm_config_mac_with_header_file(struct dm_struct *dm)\n{\n\tenum hal_status result = HAL_STATUS_SUCCESS;\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"===>%s (%s)\\n\", __func__,\n\t\t  (dm->is_mp_chip) ? \"MPChip\" : \"TestChip\");\n\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t  \"support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\\n\",\n\t\t  dm->support_platform, dm->support_interface, dm->board_type);\n\n#if (RTL8822C_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8822C) {\n\t\tPHYDM_DBG(dm, ODM_COMP_INIT, \"MAC para-package in HALMAC\\n\");\n\t\treturn result;\n\t}\n#endif\n/* @1 AP doesn't use PHYDM initialization in these ICs */\n#if (DM_ODM_SUPPORT_TYPE != ODM_AP)\n#if (RTL8812A_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8812)\n\t\tREAD_AND_CONFIG_MP(8812a, _mac_reg);\n#endif\n#if (RTL8821A_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8821)\n\t\tREAD_AND_CONFIG_MP(8821a, _mac_reg);\n#endif\n#if (RTL8192E_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8192E)\n\t\tREAD_AND_CONFIG_MP(8192e, _mac_reg);\n#endif\n#if (RTL8723D_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8723D)\n\t\tREAD_AND_CONFIG_MP(8723d, _mac_reg);\n#endif\n/* @JJ ADD 20161014 */\n#if (RTL8710B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8710B)\n\t\tREAD_AND_CONFIG_MP(8710b, _mac_reg);\n#endif\n#endif /* @(DM_ODM_SUPPORT_TYPE !=  ODM_AP) */\n/* @1 All platforms support */\n#if (RTL8188E_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8188E)\n\t\tREAD_AND_CONFIG_MP(8188e, _mac_reg);\n#endif\n#if (RTL8723B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8723B)\n\t\tREAD_AND_CONFIG_MP(8723b, _mac_reg);\n#endif\n#if (RTL8814A_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8814A)\n\t\tREAD_AND_CONFIG_MP(8814a, _mac_reg);\n#endif\n#if (RTL8703B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8703B)\n\t\tREAD_AND_CONFIG_MP(8703b, _mac_reg);\n#endif\n#if (RTL8188F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8188F)\n\t\tREAD_AND_CONFIG_MP(8188f, _mac_reg);\n#endif\n#if (RTL8822B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8822B)\n\t\tREAD_AND_CONFIG_MP(8822b, _mac_reg);\n#endif\n#if (RTL8197F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8197F)\n\t\tREAD_AND_CONFIG_MP(8197f, _mac_reg);\n#endif\n\n/*@jj add 20170822*/\n#if (RTL8192F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8192F)\n\t\tREAD_AND_CONFIG_MP(8192f, _mac_reg);\n#endif\n\n#if (RTL8721D_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8721D)\n\t\tREAD_AND_CONFIG_MP(8721d, _mac_reg);\n#endif\n#if (RTL8821C_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8821C)\n\t\tREAD_AND_CONFIG(8821c, _mac_reg);\n#endif\n#if (RTL8195A_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8195A)\n\t\tREAD_AND_CONFIG_MP(8195a, _mac_reg);\n#endif\n#if (RTL8195B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8195B)\n\t\tREAD_AND_CONFIG_MP(8195b, _mac_reg);\n#endif\n#if (RTL8198F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8198F)\n\t\tREAD_AND_CONFIG_MP(8198f, _mac_reg);\n#endif\n#if (RTL8814B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8814B)\n\t\tREAD_AND_CONFIG_MP(8814b, _mac_reg);\n#endif\n#if (RTL8812F_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8812F)\n\t\tREAD_AND_CONFIG_MP(8812f, _mac_reg);\n#endif\n\n\tif (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {\n\t\tresult = phydm_set_reg_by_fw(dm,\n\t\t\t\t\t     PHYDM_HALMAC_CMD_END,\n\t\t\t\t\t     0,\n\t\t\t\t\t     0,\n\t\t\t\t\t     0,\n\t\t\t\t\t     (enum rf_path)0,\n\t\t\t\t\t     0);\n\t\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t\t  \"mac param offload end!result = %d\", result);\n\t}\n\n\treturn result;\n}\n\nu32 odm_get_hw_img_version(struct dm_struct *dm)\n{\n\tu32 version = 0;\n\n/* @1 AP doesn't use PHYDM initialization in these ICs */\n#if (DM_ODM_SUPPORT_TYPE != ODM_AP)\n#if (RTL8821A_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8821)\n\t\tversion = GET_VERSION_MP(8821a, _mac_reg);\n#endif\n#if (RTL8192E_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8192E)\n\t\tversion = GET_VERSION_MP(8192e, _mac_reg);\n#endif\n#if (RTL8812A_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8812)\n\t\tversion = GET_VERSION_MP(8812a, _mac_reg);\n#endif\n#if (RTL8723D_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8723D)\n\t\tversion = GET_VERSION_MP(8723d, _mac_reg);\n#endif\n/* @JJ ADD 20161014 */\n#if (RTL8710B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8710B)\n\t\tversion = GET_VERSION_MP(8710b, _mac_reg);\n#endif\n#endif /* @(DM_ODM_SUPPORT_TYPE != ODM_AP) */\n\n/*@1 All platforms support*/\n#if (RTL8188E_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8188E)\n\t\tversion = GET_VERSION_MP(8188e, _mac_reg);\n#endif\n#if (RTL8723B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8723B)\n\t\tversion = GET_VERSION_MP(8723b, _mac_reg);\n#endif\n#if (RTL8814A_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8814A)\n\t\tversion = GET_VERSION_MP(8814a, _mac_reg);\n#endif\n#if (RTL8703B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8703B)\n\t\tversion = GET_VERSION_MP(8703b, _mac_reg);\n#endif\n#if (RTL8188F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8188F)\n\t\tversion = GET_VERSION_MP(8188f, _mac_reg);\n#endif\n#if (RTL8822B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8822B)\n\t\tversion = GET_VERSION_MP(8822b, _mac_reg);\n#endif\n#if (RTL8197F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8197F)\n\t\tversion = GET_VERSION_MP(8197f, _mac_reg);\n#endif\n\n/*@jj add 20170822*/\n#if (RTL8192F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8192F)\n\t\tversion = GET_VERSION_MP(8192f, _mac_reg);\n#endif\n#if (RTL8721D_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8721D)\n\t\tversion = GET_VERSION_MP(8721d, _mac_reg);\n#endif\n#if (RTL8821C_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8821C)\n\t\tversion = GET_VERSION(8821c, _mac_reg);\n#endif\n#if (RTL8195B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8195B)\n\t\tversion = GET_VERSION(8195b, _mac_reg);\n#endif\n#if (RTL8198F_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8198F)\n\t\tversion = GET_VERSION_MP(8198f, _mac_reg);\n#endif\n#if 0 /*(RTL8822C_SUPPORT)*/\n\tif (dm->support_ic_type == ODM_RTL8822C)\n\t\tversion = GET_VERSION_MP(8822c, _mac_reg);\n#endif\n#if (RTL8812F_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8812F)\n\t\tversion = GET_VERSION_MP(8812f, _mac_reg);\n#endif\n#if (RTL8814B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8814B)\n\t\tversion = GET_VERSION_MP(8814b, _mac_reg);\n#endif\n\n\treturn version;\n}\n\nu32 query_phydm_trx_capability(struct dm_struct *dm)\n{\n\tu32 value32 = 0xFFFFFFFF;\n\n#if (RTL8821C_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8821C)\n\t\tvalue32 = query_phydm_trx_capability_8821c(dm);\n#endif\n#if (RTL8195B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8195B)\n\t\tvalue32 = query_phydm_trx_capability_8195b(dm);\n#endif\n\treturn value32;\n}\n\nu32 query_phydm_stbc_capability(struct dm_struct *dm)\n{\n\tu32 value32 = 0xFFFFFFFF;\n\n#if (RTL8821C_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8821C)\n\t\tvalue32 = query_phydm_stbc_capability_8821c(dm);\n#endif\n#if (RTL8195B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8195B)\n\t\tvalue32 = query_phydm_stbc_capability_8195b(dm);\n#endif\n\n\treturn value32;\n}\n\nu32 query_phydm_ldpc_capability(struct dm_struct *dm)\n{\n\tu32 value32 = 0xFFFFFFFF;\n\n#if (RTL8821C_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8821C)\n\t\tvalue32 = query_phydm_ldpc_capability_8821c(dm);\n#endif\n#if (RTL8195B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8195B)\n\t\tvalue32 = query_phydm_ldpc_capability_8195b(dm);\n#endif\n\treturn value32;\n}\n\nu32 query_phydm_txbf_parameters(struct dm_struct *dm)\n{\n\tu32 value32 = 0xFFFFFFFF;\n\n#if (RTL8821C_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8821C)\n\t\tvalue32 = query_phydm_txbf_parameters_8821c(dm);\n#endif\n#if (RTL8195B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8195B)\n\t\tvalue32 = query_phydm_txbf_parameters_8195b(dm);\n#endif\n\treturn value32;\n}\n\nu32 query_phydm_txbf_capability(struct dm_struct *dm)\n{\n\tu32 value32 = 0xFFFFFFFF;\n\n#if (RTL8821C_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8821C)\n\t\tvalue32 = query_phydm_txbf_capability_8821c(dm);\n#endif\n#if (RTL8195B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8195B)\n\t\tvalue32 = query_phydm_txbf_capability_8195b(dm);\n#endif\n\treturn value32;\n}\n"
  },
  {
    "path": "hal/phydm/phydm_hwconfig.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __HALHWOUTSRC_H__\n#define __HALHWOUTSRC_H__\n\n/*@--------------------------Define -------------------------------------------*/\n#define AGC_DIFF_CONFIG_MP(ic, band)\t\t\t\t\\\n\t(odm_read_and_config_mp_##ic##_agc_tab_diff(dm,\t\t\\\n\tarray_mp_##ic##_agc_tab_diff_##band,\t\t\t\\\n\tsizeof(array_mp_##ic##_agc_tab_diff_##band) / sizeof(u32)))\n#define AGC_DIFF_CONFIG_TC(ic, band)\t\t\t\t\\\n\t(odm_read_and_config_tc_##ic##_agc_tab_diff(dm,\t\t\\\n\tarray_tc_##ic##_agc_tab_diff_##band,\t\t\t\\\n\tsizeof(array_tc_##ic##_agc_tab_diff_##band) / sizeof(u32)))\n#if defined(DM_ODM_CE_MAC80211)\n#else\n#define AGC_DIFF_CONFIG(ic, band)                     \\\n\tdo {                                          \\\n\t\tif (dm->is_mp_chip)                   \\\n\t\t\tAGC_DIFF_CONFIG_MP(ic, band); \\\n\t\telse                                  \\\n\t\t\tAGC_DIFF_CONFIG_TC(ic, band); \\\n\t} while (0)\n#endif\n/*@************************************************************\n * structure and define\n ************************************************************/\n\nenum hal_status\nodm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm);\n\nenum hal_status\nodm_config_rf_with_header_file(struct dm_struct *dm,\n\t\t\t       enum odm_rf_config_type config_type,\n\t\t\t       u8 e_rf_path);\n\nenum hal_status\nodm_config_bb_with_header_file(struct dm_struct *dm,\n\t\t\t       enum odm_bb_config_type config_type);\n\nenum hal_status\nodm_config_mac_with_header_file(struct dm_struct *dm);\n\nu32 odm_get_hw_img_version(struct dm_struct *dm);\n\nu32 query_phydm_trx_capability(struct dm_struct *dm);\n\nu32 query_phydm_stbc_capability(struct dm_struct *dm);\n\nu32 query_phydm_ldpc_capability(struct dm_struct *dm);\n\nu32 query_phydm_txbf_parameters(struct dm_struct *dm);\n\nu32 query_phydm_txbf_capability(struct dm_struct *dm);\n\n#endif /*@#ifndef\t__HALHWOUTSRC_H__*/\n"
  },
  {
    "path": "hal/phydm/phydm_interface.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n ************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n/*@\n * ODM IO Relative API.\n */\n\nu8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tstruct rtl8192cd_priv *priv = dm->priv;\n\treturn RTL_R8(reg_addr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tstruct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;\n\n\treturn rtl_read_byte(rtlpriv, reg_addr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tstruct rtw_dev *rtwdev = dm->adapter;\n\n\treturn rtw_read8(rtwdev, reg_addr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\tvoid *adapter = dm->adapter;\n\treturn rtw_read8(adapter, reg_addr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\treturn PlatformEFIORead1Byte(adapter, reg_addr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tvoid *adapter = dm->adapter;\n\n\treturn rtw_read8(adapter, reg_addr);\n#endif\n}\n\nu16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tstruct rtl8192cd_priv *priv = dm->priv;\n\treturn RTL_R16(reg_addr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tstruct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;\n\n\treturn rtl_read_word(rtlpriv, reg_addr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tstruct rtw_dev *rtwdev = dm->adapter;\n\n\treturn rtw_read16(rtwdev, reg_addr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\tvoid *adapter = dm->adapter;\n\treturn rtw_read16(adapter, reg_addr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\treturn PlatformEFIORead2Byte(adapter, reg_addr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tvoid *adapter = dm->adapter;\n\n\treturn rtw_read16(adapter, reg_addr);\n#endif\n}\n\nu32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tstruct rtl8192cd_priv *priv = dm->priv;\n\treturn RTL_R32(reg_addr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tstruct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;\n\n\treturn rtl_read_dword(rtlpriv, reg_addr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tstruct rtw_dev *rtwdev = dm->adapter;\n\n\treturn rtw_read32(rtwdev, reg_addr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\tvoid *adapter = dm->adapter;\n\treturn rtw_read32(adapter, reg_addr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\treturn PlatformEFIORead4Byte(adapter, reg_addr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tvoid *adapter = dm->adapter;\n\n\treturn rtw_read32(adapter, reg_addr);\n#endif\n}\n\nvoid odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tstruct rtl8192cd_priv *priv = dm->priv;\n\tRTL_W8(reg_addr, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tstruct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;\n\n\trtl_write_byte(rtlpriv, reg_addr, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tstruct rtw_dev *rtwdev = dm->adapter;\n\n\trtw_write8(rtwdev, reg_addr, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\tvoid *adapter = dm->adapter;\n\trtw_write8(adapter, reg_addr, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tPlatformEFIOWrite1Byte(adapter, reg_addr, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tvoid *adapter = dm->adapter;\n\n\trtw_write8(adapter, reg_addr, data);\n#endif\n}\n\nvoid odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tstruct rtl8192cd_priv *priv = dm->priv;\n\tRTL_W16(reg_addr, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tstruct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;\n\n\trtl_write_word(rtlpriv, reg_addr, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tstruct rtw_dev *rtwdev = dm->adapter;\n\n\trtw_write16(rtwdev, reg_addr, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\tvoid *adapter = dm->adapter;\n\trtw_write16(adapter, reg_addr, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tPlatformEFIOWrite2Byte(adapter, reg_addr, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tvoid *adapter = dm->adapter;\n\n\trtw_write16(adapter, reg_addr, data);\n#endif\n}\n\nvoid odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tstruct rtl8192cd_priv *priv = dm->priv;\n\tRTL_W32(reg_addr, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tstruct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;\n\n\trtl_write_dword(rtlpriv, reg_addr, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tstruct rtw_dev *rtwdev = dm->adapter;\n\n\trtw_write32(rtwdev, reg_addr, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\tvoid *adapter = dm->adapter;\n\trtw_write32(adapter, reg_addr, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tPlatformEFIOWrite4Byte(adapter, reg_addr, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tvoid *adapter = dm->adapter;\n\n\trtw_write32(adapter, reg_addr, data);\n#endif\n}\n\nvoid odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tphy_set_bb_reg(dm->priv, reg_addr, bit_mask, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tPHY_SetBBReg(adapter, reg_addr, bit_mask, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tstruct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;\n\n\trtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tstruct rtw_dev *rtwdev = dm->adapter;\n\n\trtw_set_reg_with_mask(rtwdev, reg_addr, bit_mask, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tphy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);\n#else\n\tphy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);\n#endif\n}\n\nu32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\treturn phy_query_bb_reg(dm->priv, reg_addr, bit_mask);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\treturn PHY_QueryMacReg(dm->adapter, reg_addr, bit_mask);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tstruct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;\n\n\treturn rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tstruct rtw_dev *rtwdev = dm->adapter;\n\n\treturn rtw_get_reg_with_mask(rtwdev, reg_addr, bit_mask);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\treturn phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);\n#else\n\treturn phy_query_mac_reg(dm->adapter, reg_addr, bit_mask);\n#endif\n}\n\nvoid odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tphy_set_bb_reg(dm->priv, reg_addr, bit_mask, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tPHY_SetBBReg(adapter, reg_addr, bit_mask, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tstruct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;\n\n\trtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tstruct rtw_dev *rtwdev = dm->adapter;\n\n\trtw_set_reg_with_mask(rtwdev, reg_addr, bit_mask, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tphy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);\n#else\n\tphy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);\n#endif\n}\n\nu32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\treturn phy_query_bb_reg(dm->priv, reg_addr, bit_mask);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\treturn PHY_QueryBBReg(adapter, reg_addr, bit_mask);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tstruct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;\n\n\treturn rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tstruct rtw_dev *rtwdev = dm->adapter;\n\n\treturn rtw_get_reg_with_mask(rtwdev, reg_addr, bit_mask);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\treturn phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);\n#else\n\treturn phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);\n#endif\n}\n\nvoid odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,\n\t\t    u32 bit_mask, u32 data)\n{\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\tphy_set_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tPHY_SetRFReg(adapter, e_rf_path, reg_addr, bit_mask, data);\n\tODM_delay_us(2);\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tstruct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;\n\n\trtl_set_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tstruct rtw_dev *rtwdev = dm->adapter;\n\n\trtw_write_rf(rtwdev, e_rf_path, reg_addr, bit_mask, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\tphy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tphy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data);\n\tODM_delay_us(2);\n#endif\n}\n\nu32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,\n\t\t   u32 bit_mask)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\treturn phy_query_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, 1);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\treturn PHY_QueryRFReg(adapter, e_rf_path, reg_addr, bit_mask);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tstruct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;\n\n\treturn rtl_get_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tstruct rtw_dev *rtwdev = dm->adapter;\n\n\treturn rtw_read_rf(rtwdev, e_rf_path, reg_addr, bit_mask);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\treturn phy_query_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask);\n#else\n\treturn phy_query_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask);\n#endif\n}\n\nenum hal_status\nphydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type,\n\t\t    u32 offset, u32 data, u32 mask, enum rf_path e_rf_path,\n\t\t    u32 delay_time)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\n\treturn HAL_MAC_Config_PHY_WriteNByte(dm,\n\t\t\t\t\t     config_type,\n\t\t\t\t\t     offset,\n\t\t\t\t\t     data,\n\t\t\t\t\t     mask,\n\t\t\t\t\t     e_rf_path,\n\t\t\t\t\t     delay_time);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tPHYDM_DBG(dm, DBG_CMN, \"Not support for CE MAC80211 driver!\\n\");\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\treturn -ENOTSUPP;\n#else\n\treturn rtw_phydm_cfg_phy_para(dm,\n\t\t\t\t      config_type,\n\t\t\t\t      offset,\n\t\t\t\t      data,\n\t\t\t\t      mask,\n\t\t\t\t      e_rf_path,\n\t\t\t\t      delay_time);\n#endif\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tPHYDM_DBG(dm, DBG_CMN, \"Not support for CE MAC80211 driver!\\n\");\n#endif\n}\n\n/*@\n * ODM Memory relative API.\n */\nvoid odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\t*ptr = kmalloc(length, GFP_ATOMIC);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\t*ptr = kmalloc(length, GFP_ATOMIC);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\t*ptr = kmalloc(length, GFP_ATOMIC);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\t*ptr = rtw_zvmalloc(length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tPlatformAllocateMemory(adapter, ptr, length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\t*ptr = rtw_zvmalloc(length);\n#endif\n}\n\n/* @length could be ignored, used to detect memory leakage. */\nvoid odm_free_memory(struct dm_struct *dm, void *ptr, u32 length)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tkfree(ptr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tkfree(ptr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tkfree(ptr);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\trtw_vmfree(ptr, length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t/* struct void*    adapter = dm->adapter; */\n\tPlatformFreeMemory(ptr, length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\trtw_vmfree(ptr, length);\n#endif\n}\n\nvoid odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length)\n{\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\tmemcpy(dest, src, length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tmemcpy(dest, src, length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tmemcpy(dest, src, length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\t_rtw_memcpy(dest, src, length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tPlatformMoveMemory(dest, src, length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\trtw_memcpy(dest, src, length);\n#endif\n}\n\nvoid odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length)\n{\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\tmemset(pbuf, value, length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tmemset(pbuf, value, length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tmemset(pbuf, value, length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\t_rtw_memset(pbuf, value, length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tPlatformFillMemory(pbuf, length, value);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\trtw_memset(pbuf, value, length);\n#endif\n}\n\ns32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2, u32 length)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\treturn memcmp(buf1, buf2, length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\treturn memcmp(buf1, buf2, length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\treturn memcmp(buf1, buf2, length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\treturn _rtw_memcmp(buf1, buf2, length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\treturn PlatformCompareMemory(buf1, buf2, length);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\treturn rtw_memcmp(buf1, buf2, length);\n#endif\n}\n\n/*@\n * ODM MISC relative API.\n */\nvoid odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tstruct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;\n\n\trtl_odm_acquirespinlock(rtlpriv, type);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tstruct rtw_dev *rtwdev = dm->adapter;\n\n\tspin_lock(&rtwdev->hal.dm_lock);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\tvoid *adapter = dm->adapter;\n\trtw_odm_acquirespinlock(adapter, type);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tPlatformAcquireSpinLock(adapter, type);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tvoid *adapter = dm->adapter;\n\n\trtw_odm_acquirespinlock(adapter, type);\n#endif\n}\n\nvoid odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tstruct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;\n\n\trtl_odm_releasespinlock(rtlpriv, type);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tstruct rtw_dev *rtwdev = dm->adapter;\n\n\tspin_unlock(&rtwdev->hal.dm_lock);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\tvoid *adapter = dm->adapter;\n\trtw_odm_releasespinlock(adapter, type);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tPlatformReleaseSpinLock(adapter, type);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tvoid *adapter = dm->adapter;\n\n\trtw_odm_releasespinlock(adapter, type);\n#endif\n}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n/*@\n * Work item relative API. FOr MP driver only~!\n *   */\nvoid odm_initialize_work_item(\n\tstruct dm_struct *dm,\n\tPRT_WORK_ITEM work_item,\n\tRT_WORKITEM_CALL_BACK callback,\n\tvoid *context,\n\tconst char *id)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tPlatformInitializeWorkItem(adapter, work_item, callback, context, id);\n#endif\n}\n\nvoid odm_start_work_item(\n\tPRT_WORK_ITEM p_rt_work_item)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tPlatformStartWorkItem(p_rt_work_item);\n#endif\n}\n\nvoid odm_stop_work_item(\n\tPRT_WORK_ITEM p_rt_work_item)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tPlatformStopWorkItem(p_rt_work_item);\n#endif\n}\n\nvoid odm_free_work_item(\n\tPRT_WORK_ITEM p_rt_work_item)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tPlatformFreeWorkItem(p_rt_work_item);\n#endif\n}\n\nvoid odm_schedule_work_item(\n\tPRT_WORK_ITEM p_rt_work_item)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tPlatformScheduleWorkItem(p_rt_work_item);\n#endif\n}\n\nboolean\nodm_is_work_item_scheduled(\n\tPRT_WORK_ITEM p_rt_work_item)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\treturn PlatformIsWorkItemScheduled(p_rt_work_item);\n#endif\n}\n#endif\n\n/*@\n * ODM Timer relative API.\n */\n\nvoid ODM_delay_ms(u32 ms)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tdelay_ms(ms);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tmdelay(ms);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tmdelay(ms);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\trtw_mdelay_os(ms);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tdelay_ms(ms);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\trtw_mdelay_os(ms);\n#endif\n}\n\nvoid ODM_delay_us(u32 us)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tdelay_us(us);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tudelay(us);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tudelay(us);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\trtw_udelay_os(us);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tPlatformStallExecution(us);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\trtw_udelay_os(us);\n#endif\n}\n\nvoid ODM_sleep_ms(u32 ms)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tdelay_ms(ms);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tmsleep(ms);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tmsleep(ms);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\trtw_msleep_os(ms);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tdelay_ms(ms);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\trtw_msleep_os(ms);\n#endif\n}\n\nvoid ODM_sleep_us(u32 us)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tdelay_us(us);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tusleep_range(us, us + 1);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tusleep_range(us, us + 1);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\trtw_usleep_os(us);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tPlatformStallExecution(us);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\trtw_usleep_os(us);\n#endif\n}\n\nvoid odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer,\n\t\t   u32 ms_delay)\n{\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\tmod_timer(timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(ms_delay));\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tmod_timer(timer, jiffies + msecs_to_jiffies(ms_delay));\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tmod_timer(&timer->timer, jiffies + msecs_to_jiffies(ms_delay));\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\t_set_timer(timer, ms_delay); /* @ms */\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tPlatformSetTimer(adapter, timer, ms_delay);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\trtw_set_timer(timer, ms_delay); /* @ms */\n#endif\n}\n\nvoid odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer,\n\t\t\t  void *call_back_func, void *context,\n\t\t\t  const char *sz_id)\n{\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\tinit_timer(timer);\n\ttimer->function = call_back_func;\n\ttimer->data = (unsigned long)dm;\n#if 0\n\t/*@mod_timer(timer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10));\t*/\n#endif\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\ttimer_setup(timer, call_back_func, 0);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\tstruct _ADAPTER *adapter = dm->adapter;\n\n\t_init_timer(timer, adapter->pnetdev, call_back_func, dm);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\n\tPlatformInitializeTimer(adapter, timer, (RT_TIMER_CALL_BACK)call_back_func, context, sz_id);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tstruct _ADAPTER *adapter = dm->adapter;\n\n\trtw_init_timer(timer, adapter->pnetdev, (TIMER_FUN)call_back_func, dm, NULL);\n#endif\n}\n\nvoid odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer)\n{\n#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\tdel_timer(timer);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tdel_timer(timer);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tdel_timer(&timer->timer);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\t_cancel_timer_ex(timer);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tPlatformCancelTimer(adapter, timer);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\trtw_cancel_timer(timer);\n#endif\n}\n\nvoid odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\n\tvoid *adapter = dm->adapter;\n\n\t/* @<20120301, Kordan> If the initilization fails,\n\t * InitializeAdapterXxx will return regardless of InitHalDm.\n\t * Hence, uninitialized timers cause BSOD when the driver\n\t * releases resources since the init fail.\n\t */\n\tif (timer == 0) {\n\t\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t\t  \"[%s] Timer is NULL! Please check!\\n\", __func__);\n\t\treturn;\n\t}\n\n\tPlatformReleaseTimer(adapter, timer);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\trtw_del_timer(timer);\n#endif\n}\n\nu8 phydm_trans_h2c_id(struct dm_struct *dm, u8 phydm_h2c_id)\n{\n\tu8 platform_h2c_id = phydm_h2c_id;\n\n\tswitch (phydm_h2c_id) {\n\t/* @1 [0] */\n\tcase ODM_H2C_RSSI_REPORT:\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t\t#if (RTL8188E_SUPPORT == 1)\n\t\tif (dm->support_ic_type == ODM_RTL8188E)\n\t\t\tplatform_h2c_id = H2C_88E_RSSI_REPORT;\n\t\telse\n\t\t#endif\n\t\t\tplatform_h2c_id = H2C_RSSI_REPORT;\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\t\tplatform_h2c_id = H2C_RSSI_SETTING;\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)\n#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/\n\t\tif (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES)\n\t\t\tplatform_h2c_id = H2C_88XX_RSSI_REPORT;\n\t\telse\n#endif\n#if (RTL8812A_SUPPORT == 1)\n\t\t\tif (dm->support_ic_type == ODM_RTL8812)\n\t\t\tplatform_h2c_id = H2C_8812_RSSI_REPORT;\n\t\telse\n#endif\n\t\t{\n\t\t}\n#endif\n\n\t\tbreak;\n\n\t/* @1 [3] */\n\tcase ODM_H2C_WIFI_CALIBRATION:\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t\tplatform_h2c_id = H2C_WIFI_CALIBRATION;\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n#if (RTL8723B_SUPPORT == 1)\n\t\tplatform_h2c_id = H2C_8723B_BT_WLAN_CALIBRATION;\n#endif\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)\n#endif\n\t\tbreak;\n\n\t/* @1 [4] */\n\tcase ODM_H2C_IQ_CALIBRATION:\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t\tplatform_h2c_id = H2C_IQ_CALIBRATION;\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))\n\t\tplatform_h2c_id = H2C_8812_IQ_CALIBRATION;\n#endif\n#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)\n#endif\n\n\t\tbreak;\n\t/* @1 [5] */\n\tcase ODM_H2C_RA_PARA_ADJUST:\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t\tplatform_h2c_id = H2C_RA_PARA_ADJUST;\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))\n\t\tplatform_h2c_id = H2C_8812_RA_PARA_ADJUST;\n#elif ((RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1))\n\t\tplatform_h2c_id = H2C_RA_PARA_ADJUST;\n#elif (RTL8192E_SUPPORT == 1)\n\t\tplatform_h2c_id = H2C_8192E_RA_PARA_ADJUST;\n#elif (RTL8723B_SUPPORT == 1)\n\t\tplatform_h2c_id = H2C_8723B_RA_PARA_ADJUST;\n#endif\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)\n#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/\n\t\tif (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES)\n\t\t\tplatform_h2c_id = H2C_88XX_RA_PARA_ADJUST;\n\t\telse\n#endif\n#if (RTL8812A_SUPPORT == 1)\n\t\t\tif (dm->support_ic_type == ODM_RTL8812)\n\t\t\tplatform_h2c_id = H2C_8812_RA_PARA_ADJUST;\n\t\telse\n#endif\n\t\t{\n\t\t}\n#endif\n\n\t\tbreak;\n\n\t/* @1 [6] */\n\tcase PHYDM_H2C_DYNAMIC_TX_PATH:\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t#if (RTL8814A_SUPPORT == 1)\n\t\tif (dm->support_ic_type == ODM_RTL8814A)\n\t\t\tplatform_h2c_id = H2C_8814A_DYNAMIC_TX_PATH;\n\t#endif\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n#if (RTL8814A_SUPPORT == 1)\n\t\tif (dm->support_ic_type == ODM_RTL8814A)\n\t\t\tplatform_h2c_id = H2C_DYNAMIC_TX_PATH;\n#endif\n#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)\n#if (RTL8814A_SUPPORT == 1)\n\t\tif (dm->support_ic_type == ODM_RTL8814A)\n\t\t\tplatform_h2c_id = H2C_88XX_DYNAMIC_TX_PATH;\n#endif\n\n#endif\n\n\t\tbreak;\n\n\t/* @[7]*/\n\tcase PHYDM_H2C_FW_TRACE_EN:\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\n\t\tplatform_h2c_id = H2C_FW_TRACE_EN;\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\n\t\tplatform_h2c_id = 0x49;\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)\n#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/\n\t\tif (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES)\n\t\t\tplatform_h2c_id = H2C_88XX_FW_TRACE_EN;\n\t\telse\n#endif\n#if (RTL8812A_SUPPORT == 1)\n\t\tif (dm->support_ic_type == ODM_RTL8812)\n\t\t\tplatform_h2c_id = H2C_8812_FW_TRACE_EN;\n\t\telse\n#endif\n\t\t{\n\t\t}\n\n#endif\n\n\t\tbreak;\n\n\tcase PHYDM_H2C_TXBF:\n#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1))\n\t\tplatform_h2c_id = 0x41; /*@H2C_TxBF*/\n#endif\n\t\tbreak;\n\n\tcase PHYDM_H2C_MU:\n#if (RTL8822B_SUPPORT == 1)\n\t\tplatform_h2c_id = 0x4a; /*@H2C_MU*/\n#endif\n\t\tbreak;\n\n\tdefault:\n\t\tplatform_h2c_id = phydm_h2c_id;\n\t\tbreak;\n\t}\n\n\treturn platform_h2c_id;\n}\n\n/*@ODM FW relative API.*/\n\nvoid odm_fill_h2c_cmd(struct dm_struct *dm, u8 phydm_h2c_id, u32 cmd_len,\n\t\t      u8 *cmd_buf)\n{\n#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tstruct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tstruct rtw_dev *rtwdev = dm->adapter;\n\tu8 cmd_id, cmd_class;\n\tu8 h2c_pkt[8];\n#else\n\tvoid *adapter = dm->adapter;\n#endif\n\tu8 h2c_id = phydm_trans_h2c_id(dm, phydm_h2c_id);\n\n\tPHYDM_DBG(dm, DBG_RA, \"[H2C]  h2c_id=((0x%x))\\n\", h2c_id);\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tif (dm->support_ic_type == ODM_RTL8188E) {\n\t\tif (!dm->ra_support88e)\n\t\t\tFillH2CCmd88E(adapter, h2c_id, cmd_len, cmd_buf);\n\t} else if (dm->support_ic_type == ODM_RTL8814A)\n\t\tFillH2CCmd8814A(adapter, h2c_id, cmd_len, cmd_buf);\n\telse if (dm->support_ic_type == ODM_RTL8822B)\n\t\tFillH2CCmd8822B(adapter, h2c_id, cmd_len, cmd_buf);\n\telse\n\t\tFillH2CCmd(adapter, h2c_id, cmd_len, cmd_buf);\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\n\t#ifdef DM_ODM_CE_MAC80211\n\trtlpriv->cfg->ops->fill_h2c_cmd(rtlpriv->hw, h2c_id, cmd_len, cmd_buf);\n\t#elif defined(DM_ODM_CE_MAC80211_V2)\n\tcmd_id = phydm_h2c_id & 0x1f;\n\tcmd_class = (phydm_h2c_id >> RTW_H2C_CLASS_OFFSET) & 0x7;\n\tmemcpy(h2c_pkt + 1, cmd_buf, 7);\n\th2c_pkt[0] = phydm_h2c_id;\n\trtw_fw_send_h2c_packet(rtwdev, h2c_pkt, cmd_id, cmd_class);\n\t/* TODO: implement fill h2c command for rtwlan */\n\t#else\n\trtw_hal_fill_h2c_cmd(adapter, h2c_id, cmd_len, cmd_buf);\n\t#endif\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\n\t#if (RTL8812A_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8812) {\n\t\tfill_h2c_cmd8812(dm->priv, h2c_id, cmd_len, cmd_buf);\n\t} else\n\t#endif\n\t{\n\t\tGET_HAL_INTERFACE(dm->priv)->fill_h2c_cmd_handler(dm->priv, h2c_id, cmd_len, cmd_buf);\n\t}\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\trtw_hal_fill_h2c_cmd(adapter, h2c_id, cmd_len, cmd_buf);\n\n#endif\n}\n\nu8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,\n\t\t\t     u8 *tmp_buf)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter = dm->adapter;\n#endif\n\tu8 extend_c2h_sub_id = 0;\n\tu8 find_c2h_cmd = true;\n\n\tif (c2h_cmd_len > 12 || c2h_cmd_len == 0) {\n\t\tpr_debug(\"[Warning] Error C2H ID=%d, len=%d\\n\",\n\t\t\t c2h_cmd_id, c2h_cmd_len);\n\n\t\tfind_c2h_cmd = false;\n\t\treturn find_c2h_cmd;\n\t}\n\n\tswitch (c2h_cmd_id) {\n\tcase PHYDM_C2H_DBG:\n\t\tphydm_fw_trace_handler(dm, tmp_buf, c2h_cmd_len);\n\t\tbreak;\n\n\tcase PHYDM_C2H_RA_RPT:\n\t\tphydm_c2h_ra_report_handler(dm, tmp_buf, c2h_cmd_len);\n\t\tbreak;\n\n\tcase PHYDM_C2H_RA_PARA_RPT:\n\t\todm_c2h_ra_para_report_handler(dm, tmp_buf, c2h_cmd_len);\n\t\tbreak;\n#ifdef CONFIG_PATH_DIVERSITY\n\tcase PHYDM_C2H_DYNAMIC_TX_PATH_RPT:\n\t\tif (dm->support_ic_type & (ODM_RTL8814A))\n\t\t\tphydm_c2h_dtp_handler(dm, tmp_buf, c2h_cmd_len);\n\t\tbreak;\n#endif\n\n\tcase PHYDM_C2H_IQK_FINISH:\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\n\t\tif (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) {\n\t\t\tRT_TRACE(COMP_MP, DBG_LOUD, (\"== FW IQK Finish ==\\n\"));\n\t\t\todm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);\n\t\t\tdm->rf_calibrate_info.is_iqk_in_progress = false;\n\t\t\todm_release_spin_lock(dm, RT_IQK_SPINLOCK);\n\t\t\tdm->rf_calibrate_info.iqk_progressing_time = 0;\n\t\t\tdm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time);\n\t\t}\n\n#endif\n\t\tbreak;\n\n\tcase PHYDM_C2H_CLM_MONITOR:\n\t\tphydm_clm_c2h_report_handler(dm, tmp_buf, c2h_cmd_len);\n\t\tbreak;\n\n\tcase PHYDM_C2H_DBG_CODE:\n\t\tphydm_fw_trace_handler_code(dm, tmp_buf, c2h_cmd_len);\n\t\tbreak;\n\n\tcase PHYDM_C2H_EXTEND:\n\t\textend_c2h_sub_id = tmp_buf[0];\n\t\tif (extend_c2h_sub_id == PHYDM_EXTEND_C2H_DBG_PRINT)\n\t\t\tphydm_fw_trace_handler_8051(dm, tmp_buf, c2h_cmd_len);\n\n\t\tbreak;\n\n\tdefault:\n\t\tfind_c2h_cmd = false;\n\t\tbreak;\n\t}\n\n\treturn find_c2h_cmd;\n}\n\nu64 odm_get_current_time(struct dm_struct *dm)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\treturn (u64)rtw_get_current_time();\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\treturn jiffies;\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\treturn jiffies;\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\treturn rtw_get_current_time();\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\treturn PlatformGetCurrentTime();\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\treturn rtw_get_current_time();\n#endif\n}\n\nu64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\treturn rtw_get_passing_time_ms((u32)start_time);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\treturn jiffies_to_msecs(jiffies - start_time);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\treturn jiffies_to_msecs(jiffies - start_time);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\treturn rtw_get_passing_time_ms((systime)start_time);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\treturn ((PlatformGetCurrentTime() - start_time) >> 10);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\treturn rtw_get_passing_time_ms(start_time);\n#endif\n}\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \\\n\t(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))\n\nvoid phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 RegName,\n\t\t\t\t\tu8 *val)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\tstruct _ADAPTER *adapter = dm->adapter;\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t((PADAPTER)adapter)->HalFunc.SetHwRegHandler(adapter, RegName, val);\n#else\n\tadapter->hal_func.set_hw_reg_handler(adapter, RegName, val);\n#endif\n\n#endif\n}\n\nvoid phydm_get_hal_def_var_handler_interface(struct dm_struct *dm,\n\t\t\t\t\t     enum _HAL_DEF_VARIABLE e_variable,\n\t\t\t\t\t     void *value)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\tstruct _ADAPTER *adapter = dm->adapter;\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t((PADAPTER)adapter)->HalFunc.GetHalDefVarHandler(adapter, e_variable, value);\n#else\n\tadapter->hal_func.get_hal_def_var_handler(adapter, e_variable, value);\n#endif\n\n#endif\n}\n\n#endif\n\nvoid odm_set_tx_power_index_by_rate_section(struct dm_struct *dm,\n\t\t\t\t\t    enum rf_path path, u8 ch,\n\t\t\t\t\t    u8 section)\n{\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\tPHY_SetTxPowerIndexByRateSection(adapter, path, ch, section);\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tvoid *adapter = dm->adapter;\n\n\tphy_set_tx_power_index_by_rs(adapter, ch, path, section);\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\tphy_set_tx_power_index_by_rate_section(dm->adapter, path, ch, section);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tvoid *adapter = dm->adapter;\n\n\tPHY_SetTxPowerIndexByRateSection(adapter, path, ch, section);\n#endif\n}\n\nu8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 rate,\n\t\t\t  u8 bw, u8 ch)\n{\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\n\treturn PHY_GetTxPowerIndex(dm->adapter, path, rate, (CHANNEL_WIDTH)bw, ch);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tvoid *adapter = dm->adapter;\n\n\treturn phy_get_tx_power_index(adapter, path, rate, bw, ch);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\tvoid *adapter = dm->adapter;\n\n\treturn phy_get_tx_power_index(adapter, path, rate, bw, ch);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\treturn phy_get_tx_power_index(dm->adapter, path, rate, bw, ch);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tvoid *adapter = dm->adapter;\n\n\treturn PHY_GetTxPowerIndex(dm->adapter, path, rate, bw, ch);\n#endif\n}\n\nu8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data,\n\t\t\t   boolean b_pseu_do_test)\n{\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\n\treturn (u8)EFUSE_OneByteRead(adapter, addr, data, b_pseu_do_test);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tvoid *adapter = dm->adapter;\n\n\treturn rtl_efuse_onebyte_read(adapter, addr, data, b_pseu_do_test);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\treturn -1;\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\treturn efuse_onebyte_read(dm->adapter, addr, data, b_pseu_do_test);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\treturn Efuse_OneByteRead(dm, addr, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tvoid *adapter = dm->adapter;\n\n\treturn (u8)efuse_OneByteRead(adapter, addr, data, b_pseu_do_test);\n#endif\n}\n\nvoid odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset,\n\t\t\t\tu32 *data)\n{\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tvoid *adapter = dm->adapter;\n\n\tEFUSE_ShadowRead(adapter, type, offset, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tvoid *adapter = dm->adapter;\n\n\trtl_efuse_logical_map_read(adapter, type, offset, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\tefuse_logical_map_read(dm->adapter, type, offset, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tvoid *adapter = dm->adapter;\n\n\tEFUSE_ShadowRead(adapter, type, offset, data);\n#endif\n}\n\nenum hal_status\nodm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment)\n{\n\tenum hal_status iqk_result = HAL_STATUS_FAILURE;\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tstruct _ADAPTER *adapter = dm->adapter;\n\n\tif (HAL_MAC_FWIQK_Trigger(&GET_HAL_MAC_INFO(adapter), clear, segment) == 0)\n\t\tiqk_result = HAL_STATUS_SUCCESS;\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tvoid *adapter = dm->adapter;\n\n\tiqk_result = rtl_phydm_fw_iqk(adapter, clear, segment);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n#else\n\tiqk_result = rtw_phydm_fw_iqk(dm, clear, segment);\n#endif\n#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)\n\tiqk_result = rtw_phydm_fw_iqk(dm, clear, segment);\n#endif\n\treturn iqk_result;\n}\n\nvoid odm_cmn_info_ptr_array_hook(struct dm_struct *dm,\n\t\t\t\t enum odm_cmninfo cmn_info, u16 index,\n\t\t\t\t void *value)\n{\n\t/*ODM_CMNINFO_STA_STATUS*/\n}\n\nvoid phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 mac_id,\n\t\t\t     struct cmn_sta_info *pcmn_sta_info)\n{\n\tdm->phydm_sta_info[mac_id] = pcmn_sta_info;\n\n\tif (is_sta_active(pcmn_sta_info))\n\t\tdm->phydm_macid_table[pcmn_sta_info->mac_id] = mac_id;\n}\n\nvoid phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx,\n\t\t\t       struct cmn_sta_info *pcmn_sta_info)\n{\n\tif (is_sta_active(pcmn_sta_info))\n\t\tdm->phydm_macid_table[pcmn_sta_info->mac_id] = entry_idx;\n}\n\nvoid phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\n\tstruct rtl8192cd_priv *priv = dm->priv;\n\n\t#if IS_EXIST_PCI || IS_EXIST_EMBEDDED\n\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\tGET_HAL_INTERFACE(priv)->AddInterruptMaskHandler(priv,\n\t\t\t\t\t\t\t\t interrupt_type)\n\t\t\t\t\t\t\t\t ;\n\t#endif\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n#endif\n}\n\nvoid phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\n\tstruct rtl8192cd_priv *priv = dm->priv;\n\n\t#if IS_EXIST_PCI || IS_EXIST_EMBEDDED\n\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\tGET_HAL_INTERFACE(priv)->EnableRxRelatedInterruptHandler(priv);\n\t#endif\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n#endif\n}\n\n#if 0\nboolean\nphydm_get_txbf_en(\n\tstruct dm_struct\t\t*dm,\n\tu16\t\t\t\t\t\t\tmac_id,\n\tu8\t\t\t\t\t\t\ti\n)\n{\n\tboolean txbf_en = false;\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && !defined(DM_ODM_CE_MAC80211)\n\n#ifdef CONFIG_BEAMFORMING\n\tenum beamforming_cap beamform_cap;\n\tvoid *adapter = dm->adapter;\n\t#ifdef PHYDM_BEAMFORMING_SUPPORT\n\tbeamform_cap =\n\tphydm_beamforming_get_entry_beam_cap_by_mac_id(dm, mac_id);\n\t#else/*@for drv beamforming*/\n\tbeamform_cap =\n\tbeamforming_get_entry_beam_cap_by_mac_id(&adapter->mlmepriv, mac_id);\n\t#endif\n\tif (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU))\n\t\ttxbf_en = true;\n\telse\n\t\ttxbf_en = false;\n#endif /*@#ifdef CONFIG_BEAMFORMING*/\n\n#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\tu8 idx = 0xff;\n\tboolean act_bfer = false;\n\tBEAMFORMING_CAP beamform_cap = BEAMFORMING_CAP_NONE;\n\tPRT_BEAMFORMING_ENTRY\tentry = NULL;\n\tstruct rtl8192cd_priv *priv\t\t\t= dm->priv;\n\t#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))\n\tstruct _BF_DIV_COEX_\t*dm_bdc_table = &dm->dm_bdc_table;\n\n\tdm_bdc_table->num_txbfee_client = 0;\n\tdm_bdc_table->num_txbfer_client = 0;\n\t#endif\n#endif\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\tbeamform_cap = Beamforming_GetEntryBeamCapByMacId(priv, mac_id);\n\tentry = Beamforming_GetEntryByMacId(priv, mac_id, &idx);\n\tif (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) {\n\t\tif (entry->Sounding_En)\n\t\t\ttxbf_en = true;\n\t\telse\n\t\t\ttxbf_en = false;\n\t\tact_bfer = true;\n\t}\n\t#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*@BDC*/\n\tif (act_bfer == true) {\n\t\tdm_bdc_table->w_bfee_client[i] = true; /* @AP act as BFer */\n\t\tdm_bdc_table->num_txbfee_client++;\n\t} else\n\t\tdm_bdc_table->w_bfee_client[i] = false; /* @AP act as BFer */\n\n\tif (beamform_cap & (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP_VHT_SU)) {\n\t\tdm_bdc_table->w_bfer_client[i] = true; /* @AP act as BFee */\n\t\tdm_bdc_table->num_txbfer_client++;\n\t} else\n\t\tdm_bdc_table->w_bfer_client[i] = false; /* @AP act as BFer */\n\n\t#endif\n#endif\n\n#endif\n\treturn txbf_en;\n}\n#endif\n\nvoid phydm_iqk_wait(struct dm_struct *dm, u32 timeout)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tPHYDM_DBG(dm, DBG_CMN, \"Not support for CE MAC80211 driver!\\n\");\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n#else\n\tvoid *adapter = dm->adapter;\n\n\trtl8812_iqk_wait(adapter, timeout);\n#endif\n#endif\n}\n\nu8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)\n\treturn HwRateToMRate(rate);\n#endif\n\treturn 0;\n}\n\nvoid phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)\n\tROM_odm_SetCrystalCap(dm, crystal_cap);\n#endif\n}\n\nvoid phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *),\n\t\t\t     void *context)\n{\n#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\tPHYDM_DBG(dm, DBG_CMN, \"Not support for CE MAC80211 driver!\\n\");\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\tvoid *adapter = dm->adapter;\n\n\trtw_run_in_thread_cmd(adapter, func, context);\n#endif\n}\n\nu8 phydm_get_tx_rate(struct dm_struct *dm)\n{\n\tstruct _hal_rf_ *rf = &dm->rf_table;\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tstruct _ADAPTER *adapter = dm->adapter;\n#endif\n\tu8 tx_rate = 0xff;\n\tu8 mpt_rate_index = 0;\n\n\tif (*dm->mp_mode == 1) {\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n#if (MP_DRIVER == 1)\n\t\tPMPT_CONTEXT p_mpt_ctx = &adapter->MptCtx;\n\n\t\ttx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);\n#endif\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n#ifdef CONFIG_MP_INCLUDED\n\t\tif (rf->mp_rate_index)\n\t\t\tmpt_rate_index = *rf->mp_rate_index;\n\n\t\ttx_rate = mpt_to_mgnt_rate(mpt_rate_index);\n#endif\n#endif\n#endif\n\t} else {\n\t\tu16 rate = *dm->forced_data_rate;\n\n\t\tif (!rate) { /*auto rate*/\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t\t\tstruct _ADAPTER *adapter = dm->adapter;\n\n\t\t\ttx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\t\t\ttx_rate = dm->tx_rate;\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\t\t\tif (dm->number_linked_client != 0)\n\t\t\t\ttx_rate = hw_rate_to_m_rate(dm->tx_rate);\n\t\t\telse\n\t\t\t\ttx_rate = rf->p_rate_index;\n#endif\n\t\t} else { /*force rate*/\n\t\t\ttx_rate = (u8)rate;\n\t\t}\n\t}\n\n\treturn tx_rate;\n}\n\nu8 phydm_get_tx_power_dbm(struct dm_struct *dm, u8 rf_path,\n\t\t\t\t\tu8 rate, u8 bandwidth, u8 channel)\n{\n\tu8 tx_power_dbm = 0;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tstruct _ADAPTER *adapter = dm->adapter;\n\ttx_power_dbm = PHY_GetTxPowerFinalAbsoluteValue(adapter, rf_path, rate, bandwidth, channel);\n#endif\n\treturn tx_power_dbm;\n}\n\nu64 phydm_division64(u64 x, u64 y)\n{\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tdo_div(x, y); \n\treturn x;\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\treturn x / y;\n#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\treturn rtw_division64(x, y);\n#endif\n}\n"
  },
  {
    "path": "hal/phydm/phydm_interface.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __ODM_INTERFACE_H__\n#define __ODM_INTERFACE_H__\n\n#define INTERFACE_VERSION \"1.2\"\n\n#define pdm_set_reg odm_set_bb_reg\n\n/*@=========== Constant/Structure/Enum/... Define*/\n\nenum phydm_h2c_cmd {\n\tPHYDM_H2C_RA_MASK\t\t= 0x40,\n\tPHYDM_H2C_TXBF\t\t\t= 0x41,\n\tODM_H2C_RSSI_REPORT\t\t= 0x42,\n\tODM_H2C_IQ_CALIBRATION\t\t= 0x45,\n\tPHYDM_RA_MASK_ABOVE_3SS\t\t= 0x46,\n\tODM_H2C_RA_PARA_ADJUST\t\t= 0x47,\n\tPHYDM_H2C_DYNAMIC_TX_PATH\t= 0x48,\n\tPHYDM_H2C_FW_TRACE_EN\t\t= 0x49,\n\tODM_H2C_WIFI_CALIBRATION\t= 0x6d,\n\tPHYDM_H2C_MU\t\t\t= 0x4a,\n\tPHYDM_H2C_FW_GENERAL_INIT\t= 0x4c,\n\tPHYDM_H2C_FW_CLM_MNTR\t\t= 0x4d,\n\tPHYDM_H2C_MCC\t\t\t= 0x4f,\n\tPHYDM_H2C_RESP_TX_PATH_CTRL\t= 0x50,\n\tPHYDM_H2C_RESP_TX_ANT_CTRL\t= 0x51,\n\tODM_MAX_H2CCMD\n};\n\nenum phydm_c2h_evt {\n\tPHYDM_C2H_DBG =\t\t0,\n\tPHYDM_C2H_LB =\t\t1,\n\tPHYDM_C2H_XBF =\t\t2,\n\tPHYDM_C2H_TX_REPORT =\t3,\n\tPHYDM_C2H_INFO =\t9,\n\tPHYDM_C2H_BT_MP =\t11,\n\tPHYDM_C2H_RA_RPT =\t12,\n\tPHYDM_C2H_RA_PARA_RPT = 14,\n\tPHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15,\n\tPHYDM_C2H_IQK_FINISH =\t17, /*@0x11*/\n\tPHYDM_C2H_CLM_MONITOR =\t0x2a,\n\tPHYDM_C2H_DBG_CODE =\t0xFE,\n\tPHYDM_C2H_EXTEND =\t0xFF,\n};\n\nenum phydm_extend_c2h_evt {\n\tPHYDM_EXTEND_C2H_DBG_PRINT = 0\n\n};\n\nenum phydm_halmac_param {\n\tPHYDM_HALMAC_CMD_MAC_W8 = 0,\n\tPHYDM_HALMAC_CMD_MAC_W16 = 1,\n\tPHYDM_HALMAC_CMD_MAC_W32 = 2,\n\tPHYDM_HALMAC_CMD_BB_W8,\n\tPHYDM_HALMAC_CMD_BB_W16,\n\tPHYDM_HALMAC_CMD_BB_W32,\n\tPHYDM_HALMAC_CMD_RF_W,\n\tPHYDM_HALMAC_CMD_DELAY_US,\n\tPHYDM_HALMAC_CMD_DELAY_MS,\n\tPHYDM_HALMAC_CMD_END = 0XFF,\n};\n\n/*@=========== Macro Define*/\n\n#define _reg_all(_name)\t\t\tODM_##_name\n#define _reg_ic(_name, _ic)\t\tODM_##_name##_ic\n#define _bit_all(_name)\t\t\tBIT_##_name\n#define _bit_ic(_name, _ic)\t\tBIT_##_name##_ic\n\n/* @_cat: implemented by Token-Pasting Operator. */\n#if 0\n#define _cat(_name, _ic_type, _func) \\\n\t(                            \\\n\t\t_func##_all(_name))\n#endif\n\n#if 0\n\n#define ODM_REG_DIG_11N\t\t0xC50\n#define ODM_REG_DIG_11AC\t0xDDD\n\nODM_REG(DIG,_pdm_odm)\n#endif\n\n#if defined(DM_ODM_CE_MAC80211)\n#define ODM_BIT(name, dm)\t\t\t\t\\\n\t((dm->support_ic_type & ODM_IC_11N_SERIES) ?\t\\\n\t ODM_BIT_##name##_11N : ODM_BIT_##name##_11AC)\n\n#define ODM_REG(name, dm)\t\t\t\t\\\n\t((dm->support_ic_type & ODM_IC_11N_SERIES) ?\t\\\n\t ODM_REG_##name##_11N : ODM_REG_##name##_11AC)\n#else\n#define _reg_11N(_name)\t\t\tODM_REG_##_name##_11N\n#define _reg_11AC(_name)\t\tODM_REG_##_name##_11AC\n#define _bit_11N(_name)\t\t\tODM_BIT_##_name##_11N\n#define _bit_11AC(_name)\t\tODM_BIT_##_name##_11AC\n\n#ifdef __ECOS\n#define _rtk_cat(_name, _ic_type, _func)                                \\\n\t(                                                               \\\n\t\t((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \\\n\t\t\t\t\t\t   _func##_11AC(_name))\n#else\n\n#define _cat(_name, _ic_type, _func)                                    \\\n\t(                                                               \\\n\t\t((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \\\n\t\t\t\t\t\t   _func##_11AC(_name))\n#endif\n/*@\n * only sample code\n *#define _cat(_name, _ic_type, _func)\t\t\t\t\t\\\n *\t(\t\t\t\t\t\t\t\t\\\n *\t\t((_ic_type) & ODM_RTL8188E) ? _func##_ic(_name, _8188E) :\\\n *\t\t_func##_ic(_name, _8195)\t\t\t\t\\\n *\t)\n */\n\n/* @_name: name of register or bit.\n * Example: \"ODM_REG(R_A_AGC_CORE1, dm)\"\n * gets \"ODM_R_A_AGC_CORE1\" or \"ODM_R_A_AGC_CORE1_8192C\",\n * depends on support_ic_type.\n */\n#ifdef __ECOS\n\t#define ODM_REG(_name, _pdm_odm)\t\\\n\t\t_rtk_cat(_name, _pdm_odm->support_ic_type, _reg)\n\t#define ODM_BIT(_name, _pdm_odm)\t\\\n\t\t_rtk_cat(_name, _pdm_odm->support_ic_type, _bit)\n#else\n\t#define ODM_REG(_name, _pdm_odm)\t\\\n\t\t_cat(_name, _pdm_odm->support_ic_type, _reg)\n\t#define ODM_BIT(_name, _pdm_odm)\t\\\n\t\t_cat(_name, _pdm_odm->support_ic_type, _bit)\n#endif\n\n#endif\n/*@\n * =========== Extern Variable ??? It should be forbidden.\n */\n\n/*@\n * =========== EXtern Function Prototype\n */\n\nu8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr);\n\nu16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr);\n\nu32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr);\n\nvoid odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data);\n\nvoid odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data);\n\nvoid odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data);\n\nvoid odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask,\n\t\t     u32 data);\n\nu32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask);\n\nvoid odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data);\n\nu32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask);\n\nvoid odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,\n\t\t    u32 bit_mask, u32 data);\n\nu32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,\n\t\t   u32 bit_mask);\n\n/*@\n * Memory Relative Function.\n */\nvoid odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length);\nvoid odm_free_memory(struct dm_struct *dm, void *ptr, u32 length);\n\nvoid odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length);\n\ns32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2,\n\t\t       u32 length);\n\nvoid odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length);\n\n/*@\n * ODM MISC-spin lock relative API.\n */\nvoid odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type);\n\nvoid odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type);\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n/*@\n * ODM MISC-workitem relative API.\n */\nvoid odm_initialize_work_item(\n\tstruct dm_struct *dm,\n\tPRT_WORK_ITEM p_rt_work_item,\n\tRT_WORKITEM_CALL_BACK rt_work_item_callback,\n\tvoid *context,\n\tconst char *sz_id);\n\nvoid odm_start_work_item(\n\tPRT_WORK_ITEM p_rt_work_item);\n\nvoid odm_stop_work_item(\n\tPRT_WORK_ITEM p_rt_work_item);\n\nvoid odm_free_work_item(\n\tPRT_WORK_ITEM p_rt_work_item);\n\nvoid odm_schedule_work_item(\n\tPRT_WORK_ITEM p_rt_work_item);\n\nboolean\nodm_is_work_item_scheduled(\n\tPRT_WORK_ITEM p_rt_work_item);\n#endif\n\n/*@\n * ODM Timer relative API.\n */\nvoid ODM_delay_ms(u32 ms);\n\nvoid ODM_delay_us(u32 us);\n\nvoid ODM_sleep_ms(u32 ms);\n\nvoid ODM_sleep_us(u32 us);\n\nvoid odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer,\n\t\t   u32 ms_delay);\n\nvoid odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer,\n\t\t\t  void *call_back_func, void *context,\n\t\t\t  const char *sz_id);\n\nvoid odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer);\n\nvoid odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer);\n\n/*ODM FW relative API.*/\n\nenum hal_status\nphydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type,\n\t\t    u32 offset, u32 data, u32 mask, enum rf_path e_rf_path,\n\t\t    u32 delay_time);\n\nvoid odm_fill_h2c_cmd(struct dm_struct *dm, u8 element_id, u32 cmd_len,\n\t\t      u8 *cmd_buffer);\n\nu8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,\n\t\t\t     u8 *tmp_buf);\n\nu64 odm_get_current_time(struct dm_struct *dm);\nu64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time);\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \\\n\t(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))\n\nvoid phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 reg_Name,\n\t\t\t\t\tu8 *val);\n\nvoid phydm_get_hal_def_var_handler_interface(struct dm_struct *dm,\n\t\t\t\t\t     enum _HAL_DEF_VARIABLE e_variable,\n\t\t\t\t\t     void *value);\n\n#endif\n\nvoid odm_set_tx_power_index_by_rate_section(struct dm_struct *dm,\n\t\t\t\t\t    enum rf_path path, u8 channel,\n\t\t\t\t\t    u8 rate_section);\n\nu8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 tx_rate,\n\t\t\t  u8 band_width, u8 channel);\n\nu8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data,\n\t\t\t   boolean b_pseu_do_test);\n\nvoid odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset,\n\t\t\t\tu32 *data);\n\nenum hal_status\nodm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment);\n\nvoid odm_cmn_info_ptr_array_hook(struct dm_struct *dm,\n\t\t\t\t enum odm_cmninfo cmn_info, u16 index,\n\t\t\t\t void *value);\n\nvoid phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 index,\n\t\t\t     struct cmn_sta_info *pcmn_sta_info);\n\nvoid phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx,\n\t\t\t       struct cmn_sta_info *pcmn_sta_info);\n\nvoid phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type);\n\nvoid phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm);\n\n#if 0\nboolean\nphydm_get_txbf_en(\n\tstruct dm_struct\t\t*dm,\n\tu16\t\tmac_id,\n\tu8\t\ti\n);\n#endif\n\nvoid phydm_iqk_wait(struct dm_struct *dm, u32 timeout);\nu8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate);\n\nvoid phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap);\nvoid phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *),\n\t\t\t     void *context);\nu8 phydm_get_tx_rate(struct dm_struct *dm);\nu8 phydm_get_tx_power_dbm(struct dm_struct *dm, u8 rf_path,\n\t\t\t\t\tu8 rate, u8 bandwidth, u8 channel);\nu64 phydm_division64(u64 x, u64 y);\n\n#endif /* @__ODM_INTERFACE_H__ */\n"
  },
  {
    "path": "hal/phydm/phydm_lna_sat.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*************************************************************\n * include files\n * *************************************************************/\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#ifdef PHYDM_LNA_SAT_CHK_SUPPORT\n\n#ifdef PHYDM_LNA_SAT_CHK_TYPE1\nvoid phydm_lna_sat_chk_init(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"%s ==>\\n\", __func__);\n\n\tlna_info->check_time = 0;\n\tlna_info->sat_cnt_acc_patha = 0;\n\tlna_info->sat_cnt_acc_pathb = 0;\n\t#ifdef PHYDM_IC_ABOVE_3SS\n\tlna_info->sat_cnt_acc_pathc = 0;\n\t#endif\n\t#ifdef PHYDM_IC_ABOVE_4SS\n\tlna_info->sat_cnt_acc_pathd = 0;\n\t#endif\n\tlna_info->cur_sat_status = 0;\n\tlna_info->pre_sat_status = 0;\n\tlna_info->cur_timer_check_cnt = 0;\n\tlna_info->pre_timer_check_cnt = 0;\n\n\t#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)\n\tif (dm->support_ic_type &\n\t    (ODM_RTL8198F | ODM_RTL8814B))\n\t\tphydm_lna_sat_chk_bb_init(dm);\n\t#endif\n}\n\n#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)\nvoid phydm_lna_sat_chk_bb_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;\n\n\tboolean disable_bb_switch_tab = false;\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"%s ==>\\n\", __func__);\n\n\t/*@set table switch mux r_6table_sel_anten*/\n\todm_set_bb_reg(dm, 0x18ac, BIT(8), 0);\n\n\t/*@tab decision when idle*/\n\todm_set_bb_reg(dm, 0x18ac, BIT(16), disable_bb_switch_tab);\n\todm_set_bb_reg(dm, 0x41ac, BIT(16), disable_bb_switch_tab);\n\todm_set_bb_reg(dm, 0x52ac, BIT(16), disable_bb_switch_tab);\n\todm_set_bb_reg(dm, 0x53ac, BIT(16), disable_bb_switch_tab);\n\t/*@tab decision when ofdmcca*/\n\todm_set_bb_reg(dm, 0x18ac, BIT(17), disable_bb_switch_tab);\n\todm_set_bb_reg(dm, 0x41ac, BIT(17), disable_bb_switch_tab);\n\todm_set_bb_reg(dm, 0x52ac, BIT(17), disable_bb_switch_tab);\n\todm_set_bb_reg(dm, 0x53ac, BIT(17), disable_bb_switch_tab);\n}\n\nvoid phydm_set_ofdm_agc_tab_path(\n\tvoid *dm_void,\n\tu8 tab_sel,\n\tenum rf_path path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"%s ==>\\n\", __func__);\n\tif (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) {\n\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"set AGC Tab%d\\n\", tab_sel);\n\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"r_6table_sel_anten = 0x%x\\n\",\n\t\t\t  odm_get_bb_reg(dm, 0x18ac, BIT(8)));\n\t}\n\n\tif (dm->support_ic_type & ODM_RTL8198F) {\n\t\t/*@table sel:0/2, mapping 2 to 1 */\n\t\tif (tab_sel == OFDM_AGC_TAB_0) {\n\t\t\todm_set_bb_reg(dm, 0x18ac, BIT(4), 0);\n\t\t\todm_set_bb_reg(dm, 0x41ac, BIT(4), 0);\n\t\t\todm_set_bb_reg(dm, 0x52ac, BIT(4), 0);\n\t\t\todm_set_bb_reg(dm, 0x53ac, BIT(4), 0);\n\t\t} else if (tab_sel == OFDM_AGC_TAB_2) {\n\t\t\todm_set_bb_reg(dm, 0x18ac, BIT(4), 1);\n\t\t\todm_set_bb_reg(dm, 0x41ac, BIT(4), 1);\n\t\t\todm_set_bb_reg(dm, 0x52ac, BIT(4), 1);\n\t\t\todm_set_bb_reg(dm, 0x53ac, BIT(4), 1);\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, 0x18ac, BIT(4), 0);\n\t\t\todm_set_bb_reg(dm, 0x41ac, BIT(4), 0);\n\t\t\todm_set_bb_reg(dm, 0x52ac, BIT(4), 0);\n\t\t\todm_set_bb_reg(dm, 0x53ac, BIT(4), 0);\n\t\t}\n\t} else if (dm->support_ic_type & ODM_RTL8814B) {\n\t\tif (tab_sel == OFDM_AGC_TAB_0) {\n\t\t\todm_set_bb_reg(dm, 0x18ac, 0xf0, 0);\n\t\t\todm_set_bb_reg(dm, 0x41ac, 0xf0, 0);\n\t\t\todm_set_bb_reg(dm, 0x52ac, 0xf0, 0);\n\t\t\todm_set_bb_reg(dm, 0x53ac, 0xf0, 0);\n\t\t} else if (tab_sel == OFDM_AGC_TAB_2) {\n\t\t\todm_set_bb_reg(dm, 0x18ac, 0xf0, 2);\n\t\t\todm_set_bb_reg(dm, 0x41ac, 0xf0, 2);\n\t\t\todm_set_bb_reg(dm, 0x52ac, 0xf0, 2);\n\t\t\todm_set_bb_reg(dm, 0x53ac, 0xf0, 2);\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, 0x18ac, 0xf0, 0);\n\t\t\todm_set_bb_reg(dm, 0x41ac, 0xf0, 0);\n\t\t\todm_set_bb_reg(dm, 0x52ac, 0xf0, 0);\n\t\t\todm_set_bb_reg(dm, 0x53ac, 0xf0, 0);\n\t\t}\n\t}\n}\n\nu8 phydm_get_ofdm_agc_tab_path(\n\tvoid *dm_void,\n\tenum rf_path path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 tab_sel = 0;\n\n\tif (dm->support_ic_type & ODM_RTL8198F) {\n\t\ttab_sel = (u8)odm_get_bb_reg(dm, R_0x18ac, BIT(4));\n\t\tif (tab_sel == 0)\n\t\t\ttab_sel = OFDM_AGC_TAB_0;\n\t\telse if (tab_sel == 1)\n\t\t\ttab_sel = OFDM_AGC_TAB_2;\n\t} else if (dm->support_ic_type & ODM_RTL8814B) {\n\t\ttab_sel = (u8)odm_get_bb_reg(dm, R_0x18ac, 0xf0);\n\t\tif (tab_sel == 0)\n\t\t\ttab_sel = OFDM_AGC_TAB_0;\n\t\telse if (tab_sel == 2)\n\t\t\ttab_sel = OFDM_AGC_TAB_2;\n\t}\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"get path %d AGC Tab %d\\n\",\n\t\t  path, tab_sel);\n\treturn tab_sel;\n}\n#endif /*@#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)*/\n\nvoid phydm_set_ofdm_agc_tab(\n\tvoid *dm_void,\n\tu8 tab_sel)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\t/*@table sel:0/2, 1 is used for CCK */\n\tif (tab_sel == OFDM_AGC_TAB_0)\n\t\todm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_0);\n\telse if (tab_sel == OFDM_AGC_TAB_2)\n\t\todm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_2);\n\telse\n\t\todm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_0);\n}\n\nu8 phydm_get_ofdm_agc_tab(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\treturn (u8)odm_get_bb_reg(dm, R_0xc70, 0x1e00);\n}\n\nvoid phydm_lna_sat_chk(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_dig_struct *dig_t = &dm->dm_dig_table;\n\tstruct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;\n\tu8 igi_rssi_min;\n\tu8 rssi_min = dm->rssi_min;\n\tu32 sat_status_a, sat_status_b;\n\t#ifdef PHYDM_IC_ABOVE_3SS\n\tu32 sat_status_c;\n\t#endif\n\t#ifdef PHYDM_IC_ABOVE_4SS\n\tu32 sat_status_d;\n\t#endif\n\tu8 igi_restore = dig_t->cur_ig_value;\n\tu8 i, chk_cnt = lna_info->chk_cnt;\n\tu32 lna_sat_cnt_thd = 0;\n\tu8 agc_tab;\n\tu32 max_check_time = 0;\n\t/*@use rssi_max if rssi_min is not stable;*/\n\t/*@rssi_min = dm->rssi_max;*/\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"\\n%s ==>\\n\", __func__);\n\n\tif (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) {\n\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"Func disable\\n\");\n\t\treturn;\n\t}\n\n\tif (lna_info->is_disable_lna_sat_chk) {\n\t\tphydm_lna_sat_chk_init(dm);\n\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"disable_lna_sat_chk\\n\");\n\t\treturn;\n\t}\n\n\t/*@move igi to target pin of rssi_min */\n\tif (rssi_min == 0 || rssi_min == 0xff) {\n\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t\t  \"rssi_min=%d, set AGC Tab0\\n\", rssi_min);\n\t\t/*@adapt agc table 0*/\n\t\tphydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);\n\t\tphydm_lna_sat_chk_init(dm);\n\t\treturn;\n\t} else if (rssi_min % 2 != 0) {\n\t\tigi_rssi_min = rssi_min + DIFF_RSSI_TO_IGI - 1;\n\t} else {\n\t\tigi_rssi_min = rssi_min + DIFF_RSSI_TO_IGI;\n\t}\n\n\tif ((lna_info->chk_period > 0) && (lna_info->chk_period <= ONE_SEC_MS))\n\t\tmax_check_time = chk_cnt * (ONE_SEC_MS / (lna_info->chk_period)) * 5;\n\telse\n\t\tmax_check_time = chk_cnt * 5;\n\n\tlna_sat_cnt_thd = (max_check_time * lna_info->chk_duty_cycle) / 100;\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t  \"check_time=%d, rssi_min=%d, igi_rssi_min=0x%x\\nchk_cnt=%d, chk_period=%d, max_check_time=%d, lna_sat_cnt_thd=%d\\n\",\n\t\t  lna_info->check_time,\n\t\t  rssi_min,\n\t\t  igi_rssi_min,\n\t\t  chk_cnt,\n\t\t  lna_info->chk_period,\n\t\t  max_check_time,\n\t\t  lna_sat_cnt_thd);\n\n\todm_write_dig(dm, igi_rssi_min);\n\n\t/*@adapt agc table 0 check saturation status*/\n\t#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)\n\tif (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))\n\t\tphydm_set_ofdm_agc_tab_path(dm, OFDM_AGC_TAB_0, RF_PATH_A);\n\telse\n\t#endif\n\t\tphydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);\n\t/*@open rf power detection ckt & set detection range */\n#if (RTL8198F_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8198F) {\n\t\t/*@set rf detection range (threshold)*/\n\t\tconfig_phydm_write_rf_reg_8198f(dm, RF_PATH_A, 0x85,\n\t\t\t\t\t\t0x3f, 0x3f);\n\t\tconfig_phydm_write_rf_reg_8198f(dm, RF_PATH_B, 0x85,\n\t\t\t\t\t\t0x3f, 0x3f);\n\t\tconfig_phydm_write_rf_reg_8198f(dm, RF_PATH_C, 0x85,\n\t\t\t\t\t\t0x3f, 0x3f);\n\t\tconfig_phydm_write_rf_reg_8198f(dm, RF_PATH_D, 0x85,\n\t\t\t\t\t\t0x3f, 0x3f);\n\t\t/*@open rf power detection ckt*/\n\t\tconfig_phydm_write_rf_reg_8198f(dm, RF_PATH_A, 0x86, 0x10, 1);\n\t\tconfig_phydm_write_rf_reg_8198f(dm, RF_PATH_B, 0x86, 0x10, 1);\n\t\tconfig_phydm_write_rf_reg_8198f(dm, RF_PATH_C, 0x86, 0x10, 1);\n\t\tconfig_phydm_write_rf_reg_8198f(dm, RF_PATH_D, 0x86, 0x10, 1);\n\t}\n#elif (RTL8814B_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8814B) {\n\t\t/*@set rf detection range (threshold)*/\n\t\tconfig_phydm_write_rf_reg_8814b(dm, RF_PATH_A, 0x8B, 0x3, 0x3);\n\t\tconfig_phydm_write_rf_reg_8814b(dm, RF_PATH_B, 0x8B, 0x3, 0x3);\n\t\tconfig_phydm_write_rf_reg_8814b(dm, RF_PATH_C, 0x8B, 0x3, 0x3);\n\t\tconfig_phydm_write_rf_reg_8814b(dm, RF_PATH_D, 0x8B, 0x3, 0x3);\n\t\t/*@open rf power detection ckt*/\n\t\tconfig_phydm_write_rf_reg_8814b(dm, RF_PATH_A, 0x8B, 0x4, 1);\n\t\tconfig_phydm_write_rf_reg_8814b(dm, RF_PATH_B, 0x8B, 0x4, 1);\n\t\tconfig_phydm_write_rf_reg_8814b(dm, RF_PATH_C, 0x8B, 0x4, 1);\n\t\tconfig_phydm_write_rf_reg_8814b(dm, RF_PATH_D, 0x8B, 0x4, 1);\n\t}\n#else\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x86, 0x1f, 0x10);\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0x86, 0x1f, 0x10);\n\t#ifdef PHYDM_IC_ABOVE_3SS\n\todm_set_rf_reg(dm, RF_PATH_C, RF_0x86, 0x1f, 0x10);\n\t#endif\n\t#ifdef PHYDM_IC_ABOVE_4SS\n\todm_set_rf_reg(dm, RF_PATH_D, RF_0x86, 0x1f, 0x10);\n\t#endif\n#endif\n\n\t/*@check saturation status*/\n\tfor (i = 0; i < chk_cnt; i++) {\n#if (RTL8198F_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8198F) {\n\t\tsat_status_a = config_phydm_read_rf_reg_8198f(dm, RF_PATH_A,\n\t\t\t\t\t\t\t      RF_0xae,\n\t\t\t\t\t\t\t      0xe0000);\n\t\tsat_status_b = config_phydm_read_rf_reg_8198f(dm, RF_PATH_B,\n\t\t\t\t\t\t\t      RF_0xae,\n\t\t\t\t\t\t\t      0xe0000);\n\t\tsat_status_c = config_phydm_read_rf_reg_8198f(dm, RF_PATH_C,\n\t\t\t\t\t\t\t      RF_0xae,\n\t\t\t\t\t\t\t      0xe0000);\n\t\tsat_status_d = config_phydm_read_rf_reg_8198f(dm, RF_PATH_D,\n\t\t\t\t\t\t\t      RF_0xae,\n\t\t\t\t\t\t\t      0xe0000);\n\t}\n#elif (RTL8814B_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8814B) {\n\t/*@read peak detector info from 8814B rf reg*/\n\t\tsat_status_a = config_phydm_read_rf_reg_8814b(dm, RF_PATH_A,\n\t\t\t\t\t\t\t      RF_0xae,\n\t\t\t\t\t\t\t      0xc0000);\n\t\tsat_status_b = config_phydm_read_rf_reg_8814b(dm, RF_PATH_B,\n\t\t\t\t\t\t\t      RF_0xae,\n\t\t\t\t\t\t\t      0xc0000);\n\t\tsat_status_c = config_phydm_read_rf_reg_8814b(dm, RF_PATH_C,\n\t\t\t\t\t\t\t      RF_0xae,\n\t\t\t\t\t\t\t      0xc0000);\n\t\tsat_status_d = config_phydm_read_rf_reg_8814b(dm, RF_PATH_D,\n\t\t\t\t\t\t\t      RF_0xae,\n\t\t\t\t\t\t\t      0xc0000);\n\t}\n#else\n\t\tsat_status_a = odm_get_rf_reg(dm, RF_PATH_A, RF_0xae, 0xc0000);\n\t\tsat_status_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0xae, 0xc0000);\n\t\t#ifdef PHYDM_IC_ABOVE_3SS\n\t\tsat_status_c = odm_get_rf_reg(dm, RF_PATH_C, RF_0xae, 0xc0000);\n\t\t#endif\n\t\t#ifdef PHYDM_IC_ABOVE_4SS\n\t\tsat_status_d = odm_get_rf_reg(dm, RF_PATH_D, RF_0xae, 0xc0000);\n\t\t#endif\n#endif\n\n\t\tif (sat_status_a != 0)\n\t\t\tlna_info->sat_cnt_acc_patha++;\n\t\tif (sat_status_b != 0)\n\t\t\tlna_info->sat_cnt_acc_pathb++;\n\t\t#ifdef PHYDM_IC_ABOVE_3SS\n\t\tif (sat_status_c != 0)\n\t\t\tlna_info->sat_cnt_acc_pathc++;\n\t\t#endif\n\t\t#ifdef PHYDM_IC_ABOVE_4SS\n\t\tif (sat_status_d != 0)\n\t\t\tlna_info->sat_cnt_acc_pathd++;\n\t\t#endif\n\n\t\tif (lna_info->sat_cnt_acc_patha >= lna_sat_cnt_thd ||\n\t\t    lna_info->sat_cnt_acc_pathb >= lna_sat_cnt_thd ||\n\t\t    #ifdef PHYDM_IC_ABOVE_3SS\n\t\t    lna_info->sat_cnt_acc_pathc >= lna_sat_cnt_thd ||\n\t\t    #endif\n\t\t    #ifdef PHYDM_IC_ABOVE_4SS\n\t\t    lna_info->sat_cnt_acc_pathd >= lna_sat_cnt_thd ||\n\t\t    #endif\n\t\t    0) {\n\t\t\tlna_info->cur_sat_status = 1;\n\t\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t\t\t  \"cur_sat_status=%d, check_time=%d\\n\",\n\t\t\t\t  lna_info->cur_sat_status,\n\t\t\t\t  lna_info->check_time);\n\t\t\tbreak;\n\t\t}\n\t\tlna_info->cur_sat_status = 0;\n\t}\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t  \"cur_sat_status=%d, pre_sat_status=%d, sat_cnt_acc_patha=%d, sat_cnt_acc_pathb=%d\\n\",\n\t\t  lna_info->cur_sat_status,\n\t\t  lna_info->pre_sat_status,\n\t\t  lna_info->sat_cnt_acc_patha,\n\t\t  lna_info->sat_cnt_acc_pathb);\n\n\t#ifdef PHYDM_IC_ABOVE_4SS\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t  \"cur_sat_status=%d, pre_sat_status=%d, sat_cnt_acc_pathc=%d, sat_cnt_acc_pathd=%d\\n\",\n\t\t  lna_info->cur_sat_status,\n\t\t  lna_info->pre_sat_status,\n\t\t  lna_info->sat_cnt_acc_pathc,\n\t\t  lna_info->sat_cnt_acc_pathd);\n\t#endif\n\t/*@agc table decision*/\n\tif (lna_info->cur_sat_status) {\n\t\tif (!lna_info->dis_agc_table_swh)\n\t\t\t#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)\n\t\t\tif (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))\n\t\t\t\tphydm_set_ofdm_agc_tab_path(dm,\n\t\t\t\t\t\t\t    OFDM_AGC_TAB_2,\n\t\t\t\t\t\t\t    RF_PATH_A);\n\t\t\telse\n\t\t\t#endif\n\t\t\t\tphydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_2);\n\t\telse\n\t\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t\t\t  \"disable set to AGC Tab%d\\n\", OFDM_AGC_TAB_2);\n\t\tlna_info->check_time = 0;\n\t\tlna_info->sat_cnt_acc_patha = 0;\n\t\tlna_info->sat_cnt_acc_pathb = 0;\n\t\t#ifdef PHYDM_IC_ABOVE_3SS\n\t\tlna_info->sat_cnt_acc_pathc = 0;\n\t\t#endif\n\t\t#ifdef PHYDM_IC_ABOVE_4SS\n\t\tlna_info->sat_cnt_acc_pathd = 0;\n\t\t#endif\n\t\tlna_info->pre_sat_status = lna_info->cur_sat_status;\n\n\t} else if (lna_info->check_time <= (max_check_time - 1)) {\n\t\tif (lna_info->pre_sat_status && !lna_info->dis_agc_table_swh)\n\t\t\t#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)\n\t\t\tif (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))\n\t\t\t\tphydm_set_ofdm_agc_tab_path(dm,\n\t\t\t\t\t\t\t    OFDM_AGC_TAB_2,\n\t\t\t\t\t\t\t    RF_PATH_A);\n\t\t\telse\n\t\t\t#endif\n\t\t\t\tphydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_2);\n\n\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"ckeck time not reached\\n\");\n\t\tif (lna_info->dis_agc_table_swh)\n\t\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t\t\t  \"disable set to AGC Tab%d\\n\", OFDM_AGC_TAB_2);\n\t\tlna_info->check_time++;\n\n\t} else if (lna_info->check_time >= max_check_time) {\n\t\tif (!lna_info->dis_agc_table_swh)\n\t\t\t#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)\n\t\t\tif (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))\n\t\t\t\tphydm_set_ofdm_agc_tab_path(dm,\n\t\t\t\t\t\t\t    OFDM_AGC_TAB_0,\n\t\t\t\t\t\t\t    RF_PATH_A);\n\t\t\telse\n\t\t\t#endif\n\t\t\t\tphydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);\n\n\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"ckeck time reached\\n\");\n\t\tif (lna_info->dis_agc_table_swh)\n\t\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t\t\t  \"disable set to AGC Tab%d\\n\", OFDM_AGC_TAB_0);\n\t\tlna_info->check_time = 0;\n\t\tlna_info->sat_cnt_acc_patha = 0;\n\t\tlna_info->sat_cnt_acc_pathb = 0;\n\t\t#ifdef PHYDM_IC_ABOVE_3SS\n\t\tlna_info->sat_cnt_acc_pathc = 0;\n\t\t#endif\n\t\t#ifdef PHYDM_IC_ABOVE_4SS\n\t\tlna_info->sat_cnt_acc_pathd = 0;\n\t\t#endif\n\t\tlna_info->pre_sat_status = lna_info->cur_sat_status;\n\t}\n\n\t#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)\n\tif (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))\n\t\tagc_tab = phydm_get_ofdm_agc_tab_path(dm, RF_PATH_A);\n\telse\n\t#endif\n\t\tagc_tab = phydm_get_ofdm_agc_tab(dm);\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"use AGC tab %d\\n\", agc_tab);\n\n\t/*@restore previous igi*/\n\todm_write_dig(dm, igi_restore);\n\tlna_info->cur_timer_check_cnt++;\n\todm_set_timer(dm, &lna_info->phydm_lna_sat_chk_timer,\n\t\t      lna_info->chk_period);\n}\n\nvoid phydm_lna_sat_chk_callback(\n\tvoid *dm_void\n\n\t)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"\\n%s ==>\\n\", __func__);\n\tphydm_lna_sat_chk(dm);\n}\n\nvoid phydm_lna_sat_chk_timers(\n\tvoid *dm_void,\n\tu8 state)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;\n\n\tif (state == INIT_LNA_SAT_CHK_TIMMER) {\n\t\todm_initialize_timer(dm,\n\t\t\t\t     &lna_info->phydm_lna_sat_chk_timer,\n\t\t\t\t     (void *)phydm_lna_sat_chk_callback, NULL,\n\t\t\t\t     \"phydm_lna_sat_chk_timer\");\n\t} else if (state == CANCEL_LNA_SAT_CHK_TIMMER) {\n\t\todm_cancel_timer(dm, &lna_info->phydm_lna_sat_chk_timer);\n\t} else if (state == RELEASE_LNA_SAT_CHK_TIMMER) {\n\t\todm_release_timer(dm, &lna_info->phydm_lna_sat_chk_timer);\n\t}\n}\n\nvoid phydm_lna_sat_chk_watchdog_type1(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;\n\n\tu8 rssi_min = dm->rssi_min;\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"\\n%s ==>\\n\", __func__);\n\n\tif (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) {\n\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t\t  \"func disable\\n\");\n\t\treturn;\n\t}\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t  \"pre_timer_check_cnt=%d, cur_timer_check_cnt=%d\\n\",\n\t\t  lna_info->pre_timer_check_cnt,\n\t\t  lna_info->cur_timer_check_cnt);\n\n\tif (lna_info->is_disable_lna_sat_chk) {\n\t\tphydm_lna_sat_chk_init(dm);\n\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t\t  \"is_disable_lna_sat_chk=%d, return\\n\",\n\t\t\t  lna_info->is_disable_lna_sat_chk);\n\t\treturn;\n\t}\n\n\tif (!(dm->support_ic_type &\n\t    (ODM_RTL8197F | ODM_RTL8198F | ODM_RTL8814B))) {\n\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t\t  \"support_ic_type not 97F/98F/14B, return\\n\");\n\t\treturn;\n\t}\n\n\tif (rssi_min == 0 || rssi_min == 0xff) {\n\t\t/*@adapt agc table 0 */\n\t\tphydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);\n\t\tphydm_lna_sat_chk_init(dm);\n\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t\t  \"rssi_min=%d, return\\n\", rssi_min);\n\t\treturn;\n\t}\n\n\tif (lna_info->cur_timer_check_cnt == lna_info->pre_timer_check_cnt) {\n\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"fail, restart timer\\n\");\n\t\todm_set_timer(dm, &lna_info->phydm_lna_sat_chk_timer,\n\t\t\t      lna_info->chk_period);\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"Timer check pass\\n\");\n\t}\n\tlna_info->pre_timer_check_cnt = lna_info->cur_timer_check_cnt;\n}\n\n#endif /*@#ifdef PHYDM_LNA_SAT_CHK_TYPE1*/\n\n#ifdef PHYDM_LNA_SAT_CHK_TYPE2\n\nvoid phydm_bubble_sort(\n\tvoid *dm_void,\n\tu8 *array,\n\tu16 array_length)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu16 i, j;\n\tu8 temp;\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"%s ==>\\n\", __func__);\n\tfor (i = 0; i < (array_length - 1); i++) {\n\t\tfor (j = (i + 1); j < (array_length); j++) {\n\t\t\tif (array[i] > array[j]) {\n\t\t\t\ttemp = array[i];\n\t\t\t\tarray[i] = array[j];\n\t\t\t\tarray[j] = temp;\n\t\t\t}\n\t\t}\n\t}\n}\n\nvoid phydm_lna_sat_chk_type2_init(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*pinfo = &dm->dm_lna_sat_info;\n\tu8 real_shift = pinfo->total_bit_shift;\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"%s ==>\\n\", __func__);\n\n\tpinfo->total_cnt_snr = 1 << real_shift;\n\tpinfo->is_sm_done = TRUE;\n\tpinfo->is_snr_done = FALSE;\n\tpinfo->cur_snr_mean = 0;\n\tpinfo->cur_snr_var = 0;\n\tpinfo->cur_lower_snr_mean = 0;\n\tpinfo->pre_snr_mean = 0;\n\tpinfo->pre_snr_var = 0;\n\tpinfo->pre_lower_snr_mean = 0;\n\tpinfo->nxt_state = ORI_TABLE_MONITOR;\n\tpinfo->pre_state = ORI_TABLE_MONITOR;\n}\n\nvoid phydm_snr_collect(\n\tvoid *dm_void,\n\tu8 rx_snr)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*pinfo = &dm->dm_lna_sat_info;\n\n\tif (pinfo->is_sm_done) {\n#if 0\n\t\t/*PHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"%s ==>\\n\", __func__);*/\n#endif\n\n\t\t/* @adapt only path-A for calculation */\n\t\tpinfo->snr_statistic[pinfo->cnt_snr_statistic] = rx_snr;\n\n\t\tif (pinfo->cnt_snr_statistic == (pinfo->total_cnt_snr - 1)) {\n\t\t\tpinfo->is_snr_done = TRUE;\n\t\t\tpinfo->cnt_snr_statistic = 0;\n\t\t} else {\n\t\t\tpinfo->cnt_snr_statistic++;\n\t\t}\n\t} else {\n\t\treturn;\n\t}\n}\n\nvoid phydm_parsing_snr(void *dm_void, void *pktinfo_void, s8 *rx_snr)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*lna_t = &dm->dm_lna_sat_info;\n\tstruct phydm_perpkt_info_struct *pktinfo = NULL;\n\tu8 target_macid = dm->rssi_min_macid;\n\n\tif (!(dm->support_ability & ODM_BB_LNA_SAT_CHK))\n\t\treturn;\n\n\tpktinfo = (struct phydm_perpkt_info_struct *)pktinfo_void;\n\n\tif (!pktinfo->is_packet_match_bssid)\n\t\treturn;\n\n\tif (lna_t->force_traget_macid != 0)\n\t\ttarget_macid = lna_t->force_traget_macid;\n\n\tif (target_macid != pktinfo->station_id)\n\t\treturn;\n\n\tphydm_snr_collect(dm, rx_snr[0]); /*path-A B C D???*/\n}\n\nvoid phydm_snr_data_processing(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*pinfo = &dm->dm_lna_sat_info;\n\tu8 real_shift = pinfo->total_bit_shift;\n\tu16 total_snr_cnt = pinfo->total_cnt_snr;\n\tu16 total_loop_cnt = (total_snr_cnt - 1), i;\n\tu32 temp;\n\tu32 sum_snr_statistic = 0;\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"%s ==>\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t  \"total_loop_cnt=%d\\n\", total_loop_cnt);\n\n\tfor (i = 0; (i <= total_loop_cnt); i++) {\n\t\tif (pinfo->is_snr_detail_en) {\n\t\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t\t\t  \"snr[%d]=%d\\n\", i, pinfo->snr_statistic[i]);\n\t\t}\n\n\t\tsum_snr_statistic += (u32)(pinfo->snr_statistic[i]);\n\n\t\tpinfo->snr_statistic_sqr[i] = (u16)(pinfo->snr_statistic[i] * pinfo->snr_statistic[i]);\n\t}\n\n\tphydm_bubble_sort(dm, pinfo->snr_statistic, pinfo->total_cnt_snr);\n\n\t/*update SNR's cur mean*/\n\tpinfo->cur_snr_mean = (sum_snr_statistic >> real_shift);\n\n\tfor (i = 0; (i <= total_loop_cnt); i++) {\n\t\tif (pinfo->snr_statistic[i] >= pinfo->cur_snr_mean)\n\t\t\ttemp = pinfo->snr_statistic[i] - pinfo->cur_snr_mean;\n\t\telse\n\t\t\ttemp = pinfo->cur_snr_mean - pinfo->snr_statistic[i];\n\n\t\tpinfo->cur_snr_var += (temp * temp);\n\t}\n\n\t/*update SNR's VAR*/\n\tpinfo->cur_snr_var = (pinfo->cur_snr_var >> real_shift);\n\n\t/*@acquire lower SNR's statistics*/\n\ttemp = 0;\n\tpinfo->cnt_lower_snr_statistic = (total_snr_cnt >> pinfo->lwr_snr_ratio_bit_shift);\n\tpinfo->cnt_lower_snr_statistic = MAX_2(pinfo->cnt_lower_snr_statistic, SNR_RPT_MAX);\n\n\tfor (i = 0; i < pinfo->cnt_lower_snr_statistic; i++)\n\t\ttemp += pinfo->snr_statistic[i];\n\n\tpinfo->cur_lower_snr_mean = temp >> (real_shift - pinfo->lwr_snr_ratio_bit_shift);\n}\n\nboolean phydm_is_snr_improve(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*pinfo = &dm->dm_lna_sat_info;\n\tboolean is_snr_improve;\n\tu8 cur_state = pinfo->nxt_state;\n\tu32 cur_mean = pinfo->cur_snr_mean;\n\tu32 pre_mean = pinfo->pre_snr_mean;\n\tu32 cur_lower_mean = pinfo->cur_lower_snr_mean;\n\tu32 pre_lower_mean = pinfo->pre_lower_snr_mean;\n\tu32 cur_var = pinfo->cur_snr_var;\n\n\t/*special case, zero VAR, interference is gone*/\n\t /*@make sure pre_var is larger enough*/\n\tif (cur_state == SAT_TABLE_MONITOR ||\n\t    cur_state == ORI_TABLE_TRAINING) {\n\t\tif (cur_mean >= pre_mean) {\n\t\t\tif (cur_var == 0)\n\t\t\t\treturn true;\n\t\t}\n\t}\n#if 0\n\t/*special case, mean degrade less than VAR improvement*/\n\t/*@make sure pre_var is larger enough*/\n\tif (cur_state == ORI_TABLE_MONITOR &&\n\t    cur_mean < pre_mean &&\n\t    cur_var < pre_var) {\n\t\tdiff_mean = pre_mean - cur_mean;\n\t\tdiff_var = pre_var - cur_var;\n\t\treturn (diff_var > (2 * diff_mean * diff_mean)) ? true : false;\n\t}\n\n#endif\n\tif (cur_lower_mean >= (pre_lower_mean + pinfo->delta_snr_mean))\n\t\tis_snr_improve = true;\n\telse\n\t\tis_snr_improve = false;\n#if 0\n/* @condition refine, mean is bigger enough or VAR is smaller enough*/\n/* @1. from mean's view, mean improve delta_snr_mean(2), VAR not degrade lot*/\n\tif (cur_mean > (pre_mean + pinfo->delta_snr_mean)) {\n\t\tis_mean_improve = TRUE;\n\t\tis_var_improve = (cur_var <= pre_var + dm->delta_snr_var)\n\t\t\t\t ? TRUE : FALSE;\n\n\t} else if (cur_var + dm->delta_snr_var <= pre_var) {\n\t\tis_var_improve = TRUE;\n\t\tis_mean_improve = ((cur_mean + 1) >= pre_mean) ? TRUE : FALSE;\n\t} else {\n\t\treturn false;\n\t}\n#endif\n\treturn is_snr_improve;\n}\n\nboolean phydm_is_snr_degrade(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*pinfo = &dm->dm_lna_sat_info;\n\tu32 cur_lower_mean = pinfo->cur_lower_snr_mean;\n\tu32 pre_lower_mean = pinfo->pre_lower_snr_mean;\n\tboolean is_degrade;\n\n\tif (cur_lower_mean <= (pre_lower_mean - pinfo->delta_snr_mean))\n\t\tis_degrade = TRUE;\n\telse\n\t\tis_degrade = FALSE;\n#if 0\n\tis_mean_dgrade = (pinfo->cur_snr_mean + pinfo->delta_snr_mean <= pinfo->pre_snr_mean) ? TRUE : FALSE;\n\tis_var_degrade = (pinfo->cur_snr_var > (pinfo->pre_snr_var + pinfo->delta_snr_mean)) ? TRUE : FALSE;\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d\\n\",\n\t\t  __func__,\n\t\t  pinfo->cur_snr_mean,\n\t\t  pinfo->pre_snr_mean,\n\t\t  pinfo->cur_snr_var,\n\t\t  pinfo->pre_snr_var);\n\n\treturn (is_mean_dgrade & is_var_degrade);\n#endif\n\treturn is_degrade;\n}\n\nboolean phydm_is_large_var(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*pinfo = &dm->dm_lna_sat_info;\n\tboolean is_large_var = (pinfo->cur_snr_var >= pinfo->snr_var_thd) ? TRUE : FALSE;\n\n\treturn is_large_var;\n}\n\nvoid phydm_update_pre_status(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*pinfo = &dm->dm_lna_sat_info;\n\n\tpinfo->pre_lower_snr_mean = pinfo->cur_lower_snr_mean;\n\tpinfo->pre_snr_mean = pinfo->cur_snr_mean;\n\tpinfo->pre_snr_var = pinfo->cur_snr_var;\n}\n\nvoid phydm_ori_table_monitor(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*pinfo = &dm->dm_lna_sat_info;\n\n\tif (phydm_is_large_var(dm)) {\n\t\tpinfo->nxt_state = SAT_TABLE_TRAINING;\n\t\tconfig_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);\n\t} else {\n\t\tpinfo->nxt_state = ORI_TABLE_MONITOR;\n\t\t/*switch to anti-sat table*/\n\t\tconfig_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);\n\t}\n\tphydm_update_pre_status(dm);\n\tpinfo->pre_state = ORI_TABLE_MONITOR;\n}\n\nvoid phydm_sat_table_training(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*pinfo = &dm->dm_lna_sat_info;\n\n\t#if 0\n\tif pre_state = ORI_TABLE_MONITOR || SAT_TABLE_TRY_FAIL,\n\t/*@\"pre\" adapt ori-table, \"cur\" adapt sat-table*/\n\t/*@adapt ori table*/\n\tif (pinfo->pre_state == ORI_TABLE_MONITOR) {\n\t\tpinfo->nxt_state = SAT_TABLE_TRAINING;\n\t\tconfig_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);\n\t} else {\n\t#endif\n\tif (phydm_is_snr_improve(dm)) {\n\t\tpinfo->nxt_state = SAT_TABLE_MONITOR;\n\t} else {\n\t\tpinfo->nxt_state = SAT_TABLE_TRY_FAIL;\n\t\tconfig_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);\n\t}\n\t/*@}*/\n\n\tphydm_update_pre_status(dm);\n\tpinfo->pre_state = SAT_TABLE_TRAINING;\n}\n\nvoid phydm_sat_table_try_fail(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*pinfo = &dm->dm_lna_sat_info;\n\n\t/* @if pre_state = SAT_TABLE_TRAINING, \"pre\" adapt sat-table, \"cur\" adapt ori-table */\n\t/* @if pre_state = SAT_TABLE_TRY_FAIL, \"pre\" adapt ori-table, \"cur\" adapt ori-table */\n\n\tif (phydm_is_large_var(dm)) {\n\t\tif (phydm_is_snr_degrade(dm)) {\n\t\t\tpinfo->nxt_state = SAT_TABLE_TRAINING;\n\t\t\tconfig_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);\n\t\t} else {\n\t\t\tpinfo->nxt_state = SAT_TABLE_TRY_FAIL;\n\t\t}\n\t} else {\n\t\tpinfo->nxt_state = ORI_TABLE_MONITOR;\n\t}\n\tphydm_update_pre_status(dm);\n\tpinfo->pre_state = SAT_TABLE_TRY_FAIL;\n}\n\nvoid phydm_sat_table_monitor(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*pinfo = &dm->dm_lna_sat_info;\n\n\tif (phydm_is_snr_improve(dm)) {\n\t\tpinfo->sat_table_monitor_times = 0;\n\n\t\t/* @if pre_state = SAT_TABLE_MONITOR, \"pre\" adapt sat-table, \"cur\" adapt sat-table */\n\t\tif (pinfo->pre_state == SAT_TABLE_MONITOR) {\n\t\t\tpinfo->nxt_state = ORI_TABLE_TRAINING;\n\t\t\tconfig_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);\n\t\t\t//phydm_update_pre_status(dm);\n\t\t} else {\n\t\t\tpinfo->nxt_state = SAT_TABLE_MONITOR;\n\t\t}\n\n\t\t/* @if pre_state = SAT_TABLE_TRAINING, \"pre\" adapt sat-table, \"cur\" adapt sat-table */\n\t\t/* @if pre_state = ORI_TABLE_TRAINING, \"pre\" adapt ori-table, \"cur\" adapt sat-table */\n\t\t/*pre_state above is no need to update*/\n\t} else {\n\t\tif (pinfo->sat_table_monitor_times == pinfo->force_change_period) {\n\t\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"%s: sat_table_monitor_times=%d\\n\",\n\t\t\t\t  __func__, pinfo->sat_table_monitor_times);\n\n\t\t\tpinfo->nxt_state = ORI_TABLE_TRAINING;\n\t\t\tpinfo->sat_table_monitor_times = 0;\n\t\t\tconfig_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);\n\t\t} else {\n\t\t\tpinfo->nxt_state = SAT_TABLE_MONITOR;\n\t\t\tpinfo->sat_table_monitor_times++;\n\t\t}\n\t}\n\tphydm_update_pre_status(dm);\n\tpinfo->pre_state = SAT_TABLE_MONITOR;\n}\n\nvoid phydm_ori_table_training(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*pinfo = &dm->dm_lna_sat_info;\n\n\t/* pre_state = SAT_TABLE_MONITOR, \"pre\" adapt sat-table, \"cur\" adapt ori-table */\n\n\tif (phydm_is_snr_degrade(dm) == FALSE) {\n\t\tpinfo->nxt_state = ORI_TABLE_MONITOR;\n\t} else {\n\t\tif (pinfo->pre_snr_var == 0)\n\t\t\tpinfo->nxt_state = ORI_TABLE_TRY_FAIL;\n\t\telse\n\t\t\tpinfo->nxt_state = SAT_TABLE_MONITOR;\n\n\t\tconfig_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);\n\t}\n\tphydm_update_pre_status(dm);\n\tpinfo->pre_state = ORI_TABLE_TRAINING;\n}\n\nvoid phydm_ori_table_try_fail(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*pinfo = &dm->dm_lna_sat_info;\n\n\tif (pinfo->pre_state == ORI_TABLE_TRY_FAIL) {\n\t\tif (phydm_is_snr_improve(dm)) {\n\t\t\tpinfo->nxt_state = ORI_TABLE_TRAINING;\n\t\t\tpinfo->ori_table_try_fail_times = 0;\n\t\t\tconfig_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);\n\t\t} else {\n\t\t\tif (pinfo->ori_table_try_fail_times == pinfo->force_change_period) {\n\t\t\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t\t\t\t  \"%s: ori_table_try_fail_times=%d\\n\", __func__, pinfo->ori_table_try_fail_times);\n\n\t\t\t\tpinfo->nxt_state = ORI_TABLE_TRY_FAIL;\n\t\t\t\tpinfo->ori_table_try_fail_times = 0;\n\t\t\t\tphydm_update_pre_status(dm);\n\t\t\t} else {\n\t\t\t\tpinfo->nxt_state = ORI_TABLE_TRY_FAIL;\n\t\t\t\tpinfo->ori_table_try_fail_times++;\n\t\t\t\tphydm_update_pre_status(dm);\n\t\t\t\t//config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);\n\t\t\t}\n\t\t}\n\t} else {\n\t\tpinfo->nxt_state = ORI_TABLE_TRY_FAIL;\n\t\tpinfo->ori_table_try_fail_times = 0;\n\t\tphydm_update_pre_status(dm);\n\t\t//config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);\n\t}\n\n#if 0\n\tif (phydm_is_large_var(dm)) {\n\t\tif (phydm_is_snr_degrade(dm)) {\n\t\t\tpinfo->nxt_state = SAT_TABLE_TRAINING;\n\t\t\tconfig_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);\n\t\t} else {\n\t\t\tpinfo->nxt_state = SAT_TABLE_TRY_FAIL;\n\t\t}\n\t} else {\n\t\tpinfo->nxt_state = ORI_TABLE_MONITOR;\n\t}\n\n\tphydm_update_pre_status(dm);\n#endif\n\tpinfo->pre_state = ORI_TABLE_TRY_FAIL;\n}\n\nchar *phydm_lna_sat_state_msg(\n\tvoid *dm_void,\n\tIN u8 state)\n{\n\tchar *dbg_message;\n\n\tswitch (state) {\n\tcase ORI_TABLE_MONITOR:\n\t\tdbg_message = \"ORI_TABLE_MONITOR\";\n\t\tbreak;\n\n\tcase SAT_TABLE_TRAINING:\n\t\tdbg_message = \"SAT_TABLE_TRAINING\";\n\t\tbreak;\n\n\tcase SAT_TABLE_TRY_FAIL:\n\t\tdbg_message = \"SAT_TABLE_TRY_FAIL\";\n\t\tbreak;\n\n\tcase SAT_TABLE_MONITOR:\n\t\tdbg_message = \"SAT_TABLE_MONITOR\";\n\t\tbreak;\n\n\tcase ORI_TABLE_TRAINING:\n\t\tdbg_message = \"ORI_TABLE_TRAINING\";\n\t\tbreak;\n\n\tcase ORI_TABLE_TRY_FAIL:\n\t\tdbg_message = \"ORI_TABLE_TRY_FAIL\";\n\t\tbreak;\n\n\tdefault:\n\t\tdbg_message = \"ORI_TABLE_MONITOR\";\n\t\tbreak;\n\t}\n\n\treturn dbg_message;\n}\n\nvoid phydm_lna_sat_type2_sm(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*pinfo = &dm->dm_lna_sat_info;\n\tu8 state = pinfo->nxt_state;\n\tu8 agc_tab = (u8)odm_get_bb_reg(dm, 0x958, 0x1f);\n\tchar *dbg_message, *nxt_dbg_message;\n\tu8 real_shift = pinfo->total_bit_shift;\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"\\n\\n%s ==>\\n\", __func__);\n\n\tif ((dm->support_ic_type & ODM_RTL8822B) == FALSE) {\n\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"ODM_BB_LNA_SAT_CHK_TYPE2 only support 22B.\\n\");\n\t\treturn;\n\t}\n\n\tif ((dm->support_ability & ODM_BB_LNA_SAT_CHK) == FALSE) {\n\t\tphydm_lna_sat_chk_type2_init(dm);\n\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"ODM_BB_LNA_SAT_CHK_TYPE2 is NOT supported, cur table=%d\\n\", agc_tab);\n\t\treturn;\n\t}\n\n\tif (pinfo->is_snr_done)\n\t\tphydm_snr_data_processing(dm);\n\telse\n\t\treturn;\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"cur agc table %d\\n\", agc_tab);\n\n\tif (pinfo->is_force_lna_sat_table != AUTO_AGC_TABLE) {\n\t\t/*reset state machine*/\n\t\tpinfo->nxt_state = ORI_TABLE_MONITOR;\n\t\tif (pinfo->is_snr_done) {\n\t\t\tif (pinfo->is_force_lna_sat_table == DEFAULT_AGC_TABLE)\n\t\t\t\tconfig_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);\n\t\t\telse if (pinfo->is_force_lna_sat_table == LNA_SAT_AGC_TABLE)\n\t\t\t\tconfig_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);\n\t\t\telse\n\t\t\t\tconfig_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);\n\n\t\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t\t\t  \"%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d,cur_lower_mean=%d, pre_lower_mean=%d, cnt_lower_snr=%d\\n\",\n\t\t\t\t  __func__,\n\t\t\t\t  pinfo->cur_snr_mean,\n\t\t\t\t  pinfo->pre_snr_mean,\n\t\t\t\t  pinfo->cur_snr_var,\n\t\t\t\t  pinfo->pre_snr_var,\n\t\t\t\t  pinfo->cur_lower_snr_mean,\n\t\t\t\t  pinfo->pre_lower_snr_mean,\n\t\t\t\t  pinfo->cnt_lower_snr_statistic);\n\n\t\t\tpinfo->is_snr_done = FALSE;\n\t\t\tpinfo->is_sm_done = TRUE;\n\t\t\tphydm_update_pre_status(dm);\n\t\t} else {\n\t\t\treturn;\n\t\t}\n\t} else if (pinfo->is_snr_done) {\n\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK,\n\t\t\t  \"%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d,cur_lower_mean=%d, pre_lower_mean=%d, cnt_lower_snr=%d\\n\",\n\t\t\t  __func__,\n\t\t\t  pinfo->cur_snr_mean,\n\t\t\t  pinfo->pre_snr_mean,\n\t\t\t  pinfo->cur_snr_var,\n\t\t\t  pinfo->pre_snr_var,\n\t\t\t  pinfo->cur_lower_snr_mean,\n\t\t\t  pinfo->pre_lower_snr_mean,\n\t\t\t  pinfo->cnt_lower_snr_statistic);\n\n\t\tswitch (state) {\n\t\tcase ORI_TABLE_MONITOR:\n\t\t\tdbg_message = \"ORI_TABLE_MONITOR\";\n\t\t\tphydm_ori_table_monitor(dm);\n\t\t\tbreak;\n\n\t\tcase SAT_TABLE_TRAINING:\n\t\t\tdbg_message = \"SAT_TABLE_TRAINING\";\n\t\t\tphydm_sat_table_training(dm);\n\t\t\tbreak;\n\n\t\tcase SAT_TABLE_TRY_FAIL:\n\t\t\tdbg_message = \"SAT_TABLE_TRY_FAIL\";\n\t\t\tphydm_sat_table_try_fail(dm);\n\t\t\tbreak;\n\n\t\tcase SAT_TABLE_MONITOR:\n\t\t\tdbg_message = \"SAT_TABLE_MONITOR\";\n\t\t\tphydm_sat_table_monitor(dm);\n\t\t\tbreak;\n\n\t\tcase ORI_TABLE_TRAINING:\n\t\t\tdbg_message = \"ORI_TABLE_TRAINING\";\n\t\t\tphydm_ori_table_training(dm);\n\t\t\tbreak;\n\n\t\tcase ORI_TABLE_TRY_FAIL:\n\t\t\tdbg_message = \"ORI_TABLE_TRAINING\";\n\t\t\tphydm_ori_table_try_fail(dm);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tdbg_message = \"ORI_TABLE_MONITOR\";\n\t\t\tphydm_ori_table_monitor(dm);\n\t\t\tbreak;\n\t\t}\n\n\t\tdbg_message = phydm_lna_sat_state_msg(dm, state);\n\t\tnxt_dbg_message = phydm_lna_sat_state_msg(dm, pinfo->nxt_state);\n\t\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"state: [%s]->[%s]\\n\",\n\t\t\t  dbg_message, nxt_dbg_message);\n\n\t\tpinfo->is_snr_done = FALSE;\n\t\tpinfo->is_sm_done = TRUE;\n\t\tpinfo->total_cnt_snr = 1 << real_shift;\n\n\t} else {\n\t\treturn;\n\t}\n}\n\n\n#endif /*@#ifdef PHYDM_LNA_SAT_CHK_TYPE2*/\n\nvoid phydm_lna_sat_debug(\n\tvoid *dm_void,\n\tchar input[][16],\n\tu32 *_used,\n\tchar *output,\n\tu32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*lna_t = &dm->dm_lna_sat_info;\n\tchar help[] = \"-h\";\n\tchar monitor[] = \"-m\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu8 i;\n\tu8 agc_tab = 0;\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"monitor: -m\\n\");\n\t\t#ifdef PHYDM_LNA_SAT_CHK_TYPE1\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{0} {lna_sat_chk_en}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{1} {agc_table_switch_en}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{2} {chk_cnt per callback}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{3} {chk_period(ms)}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{4} {chk_duty_cycle(%)}\\n\");\n\t\t#endif\n\t} else if ((strcmp(input[1], monitor) == 0)) {\n#ifdef PHYDM_LNA_SAT_CHK_TYPE1\n\t\t#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)\n\t\tif (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))\n\t\t\tagc_tab = phydm_get_ofdm_agc_tab_path(dm, RF_PATH_A);\n\t\telse\n\t\t#endif\n\t\t\tagc_tab = phydm_get_ofdm_agc_tab(dm);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"%s%d, %s%d, %s%d, %s%d\\n\",\n\t\t\t \"check_time = \", lna_t->check_time,\n\t\t\t \"pre_sat_status = \", lna_t->pre_sat_status,\n\t\t\t \"cur_sat_status = \", lna_t->cur_sat_status,\n\t\t\t \"current AGC tab = \", agc_tab);\n#endif\n\t} else {\n\t\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);\n\n\t\tfor (i = 1; i < 10; i++) {\n\t\t\tif (input[i + 1])\n\t\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,\n\t\t\t\t\t     &var1[i]);\n\t\t}\n\t\t#ifdef PHYDM_LNA_SAT_CHK_TYPE1\n\t\tif (var1[0] == 0) {\n\t\t\tif (var1[1] == 1)\n\t\t\t\tlna_t->is_disable_lna_sat_chk = false;\n\t\t\telse if (var1[1] == 0)\n\t\t\t\tlna_t->is_disable_lna_sat_chk = true;\n\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"dis_lna_sat_chk=%d\\n\",\n\t\t\t\t lna_t->is_disable_lna_sat_chk);\n\t\t} else if (var1[0] == 1) {\n\t\t\tif (var1[1] == 1)\n\t\t\t\tlna_t->dis_agc_table_swh = false;\n\t\t\telse if (var1[1] == 0)\n\t\t\t\tlna_t->dis_agc_table_swh = true;\n\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"dis_agc_table_swh=%d\\n\",\n\t\t\t\t lna_t->dis_agc_table_swh);\n\n\t\t} else if (var1[0] == 2) {\n\t\t\tlna_t->chk_cnt = (u8)var1[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"chk_cnt=%d\\n\", lna_t->chk_cnt);\n\t\t} else if (var1[0] == 3) {\n\t\t\tlna_t->chk_period = var1[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"chk_period=%d\\n\", lna_t->chk_period);\n\t\t} else if (var1[0] == 4) {\n\t\t\tlna_t->chk_duty_cycle = (u8)var1[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"chk_duty_cycle=%d\\n\",\n\t\t\t\t lna_t->chk_duty_cycle);\n\t\t}\n\t\t#endif\n\t\t#ifdef PHYDM_LNA_SAT_CHK_TYPE2\n\t\tif (var1[0] == 1)\n\t\t\tlna_t->force_traget_macid = var1[1];\n\t\t#endif\n\t}\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_lna_sat_chk_watchdog(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t *lna_sat = &dm->dm_lna_sat_info;\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"%s ==>\\n\", __func__);\n\n\tif (lna_sat->lna_sat_type == LNA_SAT_WITH_PEAK_DET) {\n\t\t#ifdef PHYDM_LNA_SAT_CHK_TYPE1\n\t\tphydm_lna_sat_chk_watchdog_type1(dm);\n\t\t#endif\n\t} else if (lna_sat->lna_sat_type == LNA_SAT_WITH_TRAIN) {\n\t\t#ifdef PHYDM_LNA_SAT_CHK_TYPE2\n\n\t\t#endif\n\t}\n\n}\n\nvoid phydm_lna_sat_config(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*lna_sat = &dm->dm_lna_sat_info;\n\n\t#if (RTL8822B_SUPPORT == 1)\n\tif (dm->support_ic_type & (ODM_RTL8822B))\n\t\tlna_sat->lna_sat_type = LNA_SAT_WITH_TRAIN;\n\t#endif\n\n\t#if (RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\\\n\t     RTL8198F_SUPPORT || RTL8814B_SUPPORT)\n\tif (dm->support_ic_type &\n\t    (ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8198F | ODM_RTL8814B))\n\t\tlna_sat->lna_sat_type = LNA_SAT_WITH_PEAK_DET;\n\t#endif\n\n\tPHYDM_DBG(dm, DBG_LNA_SAT_CHK, \"[%s] lna_sat_type=%d\\n\",\n\t\t  __func__, lna_sat->lna_sat_type);\n}\n\nvoid phydm_lna_sat_check_init(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_lna_sat_t\t*lna_sat = &dm->dm_lna_sat_info;\n\n\tif ((dm->support_ability & ODM_BB_LNA_SAT_CHK))\n\t\treturn;\n\n\t/*@2018.04.17 Johnson*/\n\tphydm_lna_sat_config(dm);\n\t#ifdef PHYDM_LNA_SAT_CHK_TYPE1\n\tlna_sat->chk_period = LNA_CHK_PERIOD;\n\tlna_sat->chk_cnt = LNA_CHK_CNT;\n\tlna_sat->chk_duty_cycle = LNA_CHK_DUTY_CYCLE;\n\tlna_sat->dis_agc_table_swh = false;\n\t#endif\n\t/*@2018.04.17 Johnson end*/\n\n\tif (lna_sat->lna_sat_type == LNA_SAT_WITH_PEAK_DET) {\n\t\t#ifdef PHYDM_LNA_SAT_CHK_TYPE1\n\t\tphydm_lna_sat_chk_init(dm);\n\t\t#endif\n\t} else if (lna_sat->lna_sat_type == LNA_SAT_WITH_TRAIN) {\n\t\t#ifdef PHYDM_LNA_SAT_CHK_TYPE2\n\t\tphydm_lna_sat_chk_type2_init(dm);\n\t\t#endif\n\t}\n}\n\n#endif /*@#ifdef PHYDM_LNA_SAT_CHK_SUPPORT*/\n"
  },
  {
    "path": "hal/phydm/phydm_lna_sat.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDM_LNA_SAT_H__\n#define __PHYDM_LNA_SAT_H__\n#ifdef PHYDM_LNA_SAT_CHK_SUPPORT\n/* @1 ============================================================\n * 1  Definition\n * 1 ============================================================\n */\n\n#define LNA_SAT_VERSION \"1.0\"\n\n/*@LNA saturation check*/\n#define\tOFDM_AGC_TAB_0\t\t\t0\n#define\tOFDM_AGC_TAB_2\t\t\t2\n\n#define\tDIFF_RSSI_TO_IGI\t\t10\n#define\tONE_SEC_MS\t\t\t1000\n\n#define LNA_CHK_PERIOD\t\t\t100 /*@ms*/\n#define LNA_CHK_CNT\t\t\t10 /*@checks per callback*/\n#define LNA_CHK_DUTY_CYCLE\t\t5 /*@percentage*/\n\n#define\tDELTA_STD\t2\n#define\tDELTA_MEAN\t2\n#define\tSNR_STATISTIC_SHIFT\t8\n#define\tSNR_RPT_MAX\t256\n\n/* @1 ============================================================\n * 1 enumrate\n * 1 ============================================================\n */\n\nenum lna_sat_timer_state {\n\tINIT_LNA_SAT_CHK_TIMMER,\n\tCANCEL_LNA_SAT_CHK_TIMMER,\n\tRELEASE_LNA_SAT_CHK_TIMMER\n};\n\n#ifdef PHYDM_LNA_SAT_CHK_TYPE2\nenum lna_sat_chk_type2_status {\n\tORI_TABLE_MONITOR,\n\tORI_TABLE_TRAINING,\n\tSAT_TABLE_MONITOR,\n\tSAT_TABLE_TRAINING,\n\tSAT_TABLE_TRY_FAIL,\n\tORI_TABLE_TRY_FAIL\n};\n\n#endif\n\nenum lna_sat_type {\n\tLNA_SAT_WITH_PEAK_DET\t= 1,\t/*type1*/\n\tLNA_SAT_WITH_TRAIN\t= 2,\t/*type2*/\n};\n\n/* @1 ============================================================\n * 1  structure\n * 1 ============================================================\n */\n\nstruct phydm_lna_sat_t {\n#ifdef PHYDM_LNA_SAT_CHK_TYPE1\n\tu8\t\t\tchk_cnt;\n\tu8\t\t\tchk_duty_cycle;\n\tu32\t\t\tchk_period;/*@ms*/\n\tboolean\t\t\tis_disable_lna_sat_chk;\n\tboolean\t\t\tdis_agc_table_swh;\n#endif\n#ifdef PHYDM_LNA_SAT_CHK_TYPE2\n\tu8\t\t\tforce_traget_macid;\n\tu32\t\t\tsnr_var_thd;\n\tu32\t\t\tdelta_snr_mean;\n\tu16\t\t\tori_table_try_fail_times;\n\tu16\t\t\tcnt_lower_snr_statistic;\n\tu16\t\t\tsat_table_monitor_times;\n\tu16\t\t\tforce_change_period;\n\tu8\t\t\tis_snr_detail_en;\n\tu8\t\t\tis_force_lna_sat_table;\n\tu8\t\t\tlwr_snr_ratio_bit_shift;\n\tu8\t\t\tcnt_snr_statistic;\n\tu16\t\t\tsnr_statistic_sqr[SNR_RPT_MAX];\n\tu8\t\t\tsnr_statistic[SNR_RPT_MAX];\n\tu8\t\t\tis_sm_done;\n\tu8\t\t\tis_snr_done;\n\tu32\t\t\tcur_snr_var;\n\tu8\t\t\ttotal_bit_shift;\n\tu8\t\t\ttotal_cnt_snr;\n\tu32\t\t\tcur_snr_mean;\n\tu8\t\t\tcur_snr_var0;\n\tu32\t\t\tcur_lower_snr_mean;\n\tu32\t\t\tpre_snr_mean;\n\tu32\t\t\tpre_snr_var;\n\tu32\t\t\tpre_lower_snr_mean;\n\tu8\t\t\tnxt_state;\n\tu8\t\t\tpre_state;\n#endif\n\tenum lna_sat_type\tlna_sat_type;\n\tu32\t\t\tsat_cnt_acc_patha;\n\tu32\t\t\tsat_cnt_acc_pathb;\n#ifdef PHYDM_IC_ABOVE_3SS\n\tu32\t\t\tsat_cnt_acc_pathc;\n#endif\n#ifdef PHYDM_IC_ABOVE_4SS\n\tu32\t\t\tsat_cnt_acc_pathd;\n#endif\n\tu32\t\t\tcheck_time;\n\tboolean\t\t\tpre_sat_status;\n\tboolean\t\t\tcur_sat_status;\n\tstruct phydm_timer_list\tphydm_lna_sat_chk_timer;\n\tu32\t\t\tcur_timer_check_cnt;\n\tu32\t\t\tpre_timer_check_cnt;\n};\n\n/* @1 ============================================================\n * 1 function prototype\n * 1 ============================================================\n */\nvoid phydm_lna_sat_chk_init(void *dm_void);\n\nu8 phydm_get_ofdm_agc_tab(void *dm_void);\n\nvoid phydm_lna_sat_chk(void *dm_void);\n\nvoid phydm_lna_sat_chk_timers(void *dm_void, u8 state);\n\n#ifdef PHYDM_LNA_SAT_CHK_TYPE1\n#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)\nvoid phydm_lna_sat_chk_bb_init(void *dm_void);\n\nvoid phydm_set_ofdm_agc_tab_path(void *dm_void,\n\t\t\t\t u8 tab_sel, enum rf_path path);\n\nu8 phydm_get_ofdm_agc_tab_path(void *dm_void, enum rf_path path);\n#endif /*@#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)*/\n#endif\n\n#ifdef PHYDM_LNA_SAT_CHK_TYPE2\nvoid phydm_parsing_snr(void *dm_void, void *pktinfo_void, s8 *rx_snr);\n#endif\n\nvoid phydm_lna_sat_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t\t char *output, u32 *_out_len);\n\nvoid phydm_lna_sat_chk_watchdog(void *dm_void);\n\nvoid phydm_lna_sat_check_init(void *dm_void);\n\n#endif /*@#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_math_lib.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n ************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\nconst u32 db_invert_table[12][8] = {\n\t{10, 13, 16, 20, 25, 32, 40, 50}, /* @U(32,3) */\n\t{64, 80, 101, 128, 160, 201, 256, 318}, /* @U(32,3) */\n\t{401, 505, 635, 800, 1007, 1268, 1596, 2010}, /* @U(32,3) */\n\t{316, 398, 501, 631, 794, 1000, 1259, 1585}, /* @U(32,0) */\n\t{1995, 2512, 3162, 3981, 5012, 6310, 7943, 10000}, /* @U(32,0) */\n\t{12589, 15849, 19953, 25119, 31623, 39811, 50119, 63098}, /* @U(32,0) */\n\t{79433, 100000, 125893, 158489, 199526, 251189, 316228,\n\t 398107}, /* @U(32,0) */\n\t{501187, 630957, 794328, 1000000, 1258925, 1584893, 1995262,\n\t 2511886}, /* @U(32,0) */\n\t{3162278, 3981072, 5011872, 6309573, 7943282, 1000000, 12589254,\n\t 15848932}, /* @U(32,0) */\n\t{19952623, 25118864, 31622777, 39810717, 50118723, 63095734,\n\t 79432823, 100000000}, /* @U(32,0) */\n\t{125892541, 158489319, 199526232, 251188643, 316227766, 398107171,\n\t 501187234, 630957345}, /* @U(32,0) */\n\t{794328235, 1000000000, 1258925412, 1584893192, 1995262315,\n\t 2511886432U, 3162277660U, 3981071706U} }; /* @U(32,0) */\n\n/*Y = 10*log(X)*/\ns32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit)\n{\n\ts32 Y, integer = 0, decimal = 0;\n\tu32 i;\n\n\tif (X == 0)\n\t\tX = 1; /* @log2(x), x can't be 0 */\n\n\tfor (i = (total_bit - 1); i > 0; i--) {\n\t\tif (X & BIT(i)) {\n\t\t\tinteger = i;\n\t\t\tif (i > 0) {\n\t\t\t\t/*decimal is 0.5dB*3=1.5dB~=2dB */\n\t\t\t\tdecimal = (X & BIT(i - 1)) ? 2 : 0;\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tY = 3 * (integer - decimal_bit) + decimal; /* @10*log(x)=3*log2(x), */\n\n\treturn Y;\n}\n\ns32 odm_sign_conversion(s32 value, u32 total_bit)\n{\n\tif (value & BIT(total_bit - 1))\n\t\tvalue -= BIT(total_bit);\n\n\treturn value;\n}\n\n/*threshold must form low to high*/\nu16 phydm_find_intrvl(void *dm_void, u16 val, u16 *threshold, u16 th_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu16 i = 0;\n\tu16 ret_val = 0;\n\tu16 max_th = threshold[th_len - 1];\n\n\tfor (i = 0; i < th_len; i++) {\n\t\tif (val < threshold[i]) {\n\t\t\tret_val = i;\n\t\t\tbreak;\n\t\t} else if (val >= max_th) {\n\t\t\tret_val = th_len;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn ret_val;\n}\n\nvoid phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,\n\t\t       u8 seq_length)\n{\n\tu8 i = 0, j = 0;\n\tu32 tmp_a, tmp_b;\n\tu32 tmp_idx_a, tmp_idx_b;\n\n\tfor (i = 0; i < seq_length; i++)\n\t\trank_idx[i] = i;\n\n\tfor (i = 0; i < (seq_length - 1); i++) {\n\t\tfor (j = 0; j < (seq_length - 1 - i); j++) {\n\t\t\ttmp_a = value[j];\n\t\t\ttmp_b = value[j + 1];\n\n\t\t\ttmp_idx_a = rank_idx[j];\n\t\t\ttmp_idx_b = rank_idx[j + 1];\n\n\t\t\tif (tmp_a < tmp_b) {\n\t\t\t\tvalue[j] = tmp_b;\n\t\t\t\tvalue[j + 1] = tmp_a;\n\n\t\t\t\trank_idx[j] = tmp_idx_b;\n\t\t\t\trank_idx[j + 1] = tmp_idx_a;\n\t\t\t}\n\t\t}\n\t}\n\n\tfor (i = 0; i < seq_length; i++)\n\t\tidx_out[rank_idx[i]] = i + 1;\n}\n\nu32 odm_convert_to_db(u64 value)\n{\n\tu8 i;\n\tu8 j;\n\tu32 dB;\n\n\tif (value >= db_invert_table[11][7])\n\t\treturn 96; /* @maximum 96 dB */\n\n\tfor (i = 0; i < 12; i++) {\n\t\tif (i <= 2 && (value << FRAC_BITS) <= db_invert_table[i][7])\n\t\t\tbreak;\n\t\telse if (i > 2 && value <= db_invert_table[i][7])\n\t\t\tbreak;\n\t}\n\n\tfor (j = 0; j < 8; j++) {\n\t\tif (i <= 2 && (value << FRAC_BITS) <= db_invert_table[i][j])\n\t\t\tbreak;\n\t\telse if (i > 2 && i < 12 && value <= db_invert_table[i][j])\n\t\t\tbreak;\n\t}\n\n\tif (j == 0 && i == 0)\n\t\tgoto end;\n\n\tif (j == 0) {\n\t\tif (i != 3) {\n\t\t\tif (db_invert_table[i][0] - value >\n\t\t\t    value - db_invert_table[i - 1][7]) {\n\t\t\t\ti = i - 1;\n\t\t\t\tj = 7;\n\t\t\t}\n\t\t} else {\n\t\t\tif (db_invert_table[3][0] - value >\n\t\t\t    value - db_invert_table[2][7]) {\n\t\t\t\ti = 2;\n\t\t\t\tj = 7;\n\t\t\t}\n\t\t}\n\t} else {\n\t\tif (db_invert_table[i][j] - value >\n\t\t    value - db_invert_table[i][j - 1]) {\n\t\t\ti = i;\n\t\t\tj = j - 1;\n\t\t}\n\t}\nend:\n\tdB = (i << 3) + j + 1;\n\n\treturn dB;\n}\n\nu64 phydm_db_2_linear(u32 value)\n{\n\tu8 i = 0;\n\tu8 j = 0;\n\tu64 linear = 0;\n\n\tvalue = value & 0xFF;\n\n\t/* @1dB~96dB */\n\tif (value > 96) {\n\t\tvalue = 96;\n\t} else if (value < 1) {\n\t\tlinear = 1;\n\t\treturn linear;\n\t}\n\n\ti = (u8)((value - 1) >> 3);\n\tj = (u8)(value - 1) - (i << 3);\n\n\tlinear = db_invert_table[i][j];\n\n\tif (i > 2)\n\t\tlinear = linear << FRAC_BITS;\n\n\treturn linear;\n}\n\nu16 phydm_show_fraction_num(u32 frac_val, u8 bit_num)\n{\n\tu8 i = 0;\n\tu16 val = 0;\n\tu16 base = 5000;\n\n\tfor (i = bit_num; i > 0; i--) {\n\t\tif (frac_val & BIT(i - 1))\n\t\t\tval += (base >> (bit_num - i));\n\t}\n\treturn val;\n}\n\nu64 phydm_gen_bitmask(u8 mask_num)\n{\n\tu8 i = 0;\n\tu64 bitmask = 0;\n\n\tif (mask_num > 64)\n\t\treturn 1;\n\n\tfor (i = 0; i < mask_num; i++)\n\t\tbitmask = (bitmask << 1) | BIT(0);\n\n\treturn bitmask;\n}\n\ns32 phydm_cnvrt_2_sign(u32 val, u8 bit_num)\n{\n\tif (bit_num >= 32)\n\t\treturn (s32)val;\n\n\tif (val & BIT(bit_num - 1)) /*Sign BIT*/\n\t\tval -= (1 << bit_num); /*@2's*/\n\n\treturn val;\n}\n\ns64 phydm_cnvrt_2_sign_64(u64 val, u8 bit_num)\n{\n\tu64 one = 1;\n\ts64 val_sign = (s64)val;\n\n\tif (bit_num >= 64)\n\t\treturn (s64)val;\n\n\tif (val & (one << (bit_num - 1))) /*Sign BIT*/\n\t\tval_sign = val - (one << bit_num); /*@2's*/\n\n\treturn val_sign;\n}\n\n"
  },
  {
    "path": "hal/phydm/phydm_math_lib.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDM_MATH_LIB_H__\n#define __PHYDM_MATH_LIB_H__\n\n/* @2019.01.24 remove linear2db debug log*/\n#define AUTO_MATH_LIB_VERSION \"1.2\"\n\n/*@\n * 1 ============================================================\n * 1  Definition\n * 1 ============================================================\n */\n\n#define PHYDM_DIV(a, b) ((b) ? (a / b) : 0)\n#define DIVIDED_2(X) ((X) >> 1)\n/*@1/3 ~ 11/32*/\n#if defined(DM_ODM_CE_MAC80211)\n#define DIVIDED_3(X) ({\t\\\n\tu32 div_3_tmp = (X);\t\\\n\t(((div_3_tmp) + ((div_3_tmp) << 1) + ((div_3_tmp) << 3)) >> 5); })\n#else\n#define DIVIDED_3(X) (((X) + ((X) << 1) + ((X) << 3)) >> 5)\n#endif\n#define DIVIDED_4(X) ((X) >> 2)\n\n/*Store Ori Value*/\n#if defined(DM_ODM_CE_MAC80211)\n#define WEIGHTING_AVG(v1, w1, v2, w2)\t\\\n\t__WEIGHTING_AVG(v1, w1, v2, w2, typeof(v1), typeof(w1), typeof(v2), \\\n\t\t\ttypeof(w2))\n#define __WEIGHTING_AVG(v1, w1, v2, w2, t1, t2, t3, t4)\t({\t\\\n\tt1 __w_a_v1 = (v1);\t\\\n\tt2 __w_a_w1 = (w1);\t\\\n\tt3 __w_a_v2 = (v2);\t\\\n\tt4 __w_a_w2 = (w2);\t\\\n\t((__w_a_v1) * (__w_a_w1) + (__w_a_v2) * (__w_a_w2))\t\\\n\t/ ((__w_a_w2) + (__w_a_w1)); })\n#else\n#define WEIGHTING_AVG(v1, w1, v2, w2) \\\n\t(((v1) * (w1) + (v2) * (w2)) / ((w2) + (w1)))\n#endif\n\n/*Store 2^ma x Value*/\n#if defined(DM_ODM_CE_MAC80211)\n#define MA_ACC(old, new_val, ma) ({\t\\\n\ts16 __ma_acc_o = (old);\t\t\\\n\t(__ma_acc_o) - ((__ma_acc_o) >> (ma)) + (new_val); })\n#define GET_MA_VAL(val, ma) ({\t\\\n\ts16 __get_ma_tmp = (ma);\\\n\t((val) + (1 << ((__get_ma_tmp) - 1))) >> (__get_ma_tmp); })\n#else\n#define MA_ACC(old, new_val, ma) ((old) - ((old) >> (ma)) + (new_val))\n#define GET_MA_VAL(val, ma) (((val) + (1 << ((ma) - 1))) >> (ma))\n#endif\n#define FRAC_BITS 3\n/*@\n * 1 ============================================================\n * 1  enumeration\n * 1 ============================================================\n */\n\n/*@\n * 1 ============================================================\n * 1  structure\n * 1 ============================================================\n */\n\n/*@\n * 1 ============================================================\n * 1  function prototype\n * 1 ============================================================\n */\n\ns32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit);\n\ns32 odm_sign_conversion(s32 value, u32 total_bit);\n\nu16 phydm_find_intrvl(void *dm_void, u16 val, u16 *threshold, u16 th_len);\n\nvoid phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,\n\t\t       u8 seq_length);\n\nu32 odm_convert_to_db(u64 value);\n\nu64 phydm_db_2_linear(u32 value);\n\nu16 phydm_show_fraction_num(u32 frac_val, u8 bit_num);\n\nu64 phydm_gen_bitmask(u8 mask_num);\n\ns32 phydm_cnvrt_2_sign(u32 val, u8 bit_num);\n\ns64 phydm_cnvrt_2_sign_64(u64 val, u8 bit_num);\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_mp.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n ************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#ifdef PHYDM_MP_SUPPORT\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\nvoid phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,\n\t\t\t\t   u8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_mp *mp = &dm->dm_mp_table;\n\tu8 start = RF_PATH_A, end = RF_PATH_A;\n\tu8 i = 0;\n\n\tswitch (path) {\n\tcase RF_PATH_A:\n\tcase RF_PATH_B:\n\tcase RF_PATH_C:\n\tcase RF_PATH_D:\n\t\tstart = path;\n\t\tend = path;\n\t\tbreak;\n\tcase RF_PATH_AB:\n\t\tstart = RF_PATH_A;\n\t\tend = RF_PATH_B;\n\t\tbreak;\n#if (RTL8814B_SUPPORT == 1 || RTL8198F_SUPPORT == 1)\n\tcase RF_PATH_AC:\n\t\tstart = RF_PATH_A;\n\t\tend = RF_PATH_C;\n\t\tbreak;\n\tcase RF_PATH_AD:\n\t\tstart = RF_PATH_A;\n\t\tend = RF_PATH_D;\n\t\tbreak;\n\tcase RF_PATH_BC:\n\t\tstart = RF_PATH_B;\n\t\tend = RF_PATH_C;\n\t\tbreak;\n\tcase RF_PATH_BD:\n\t\tstart = RF_PATH_B;\n\t\tend = RF_PATH_D;\n\t\tbreak;\n\tcase RF_PATH_CD:\n\t\tstart = RF_PATH_C;\n\t\tend = RF_PATH_D;\n\t\tbreak;\n\tcase RF_PATH_ABC:\n\t\tstart = RF_PATH_A;\n\t\tend = RF_PATH_C;\n\t\tbreak;\n\tcase RF_PATH_ABD:\n\t\tstart = RF_PATH_A;\n\t\tend = RF_PATH_D;\n\t\tbreak;\n\tcase RF_PATH_ACD:\n\t\tstart = RF_PATH_A;\n\t\tend = RF_PATH_D;\n\t\tbreak;\n\tcase RF_PATH_BCD:\n\t\tstart = RF_PATH_B;\n\t\tend = RF_PATH_D;\n\t\tbreak;\n\tcase RF_PATH_ABCD:\n\t\tstart = RF_PATH_A;\n\t\tend = RF_PATH_D;\n\t\tbreak;\n#endif\n\t}\n\tif (is_single_tone) {\n\t\tmp->rf_reg0 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, 0xfffff);\n#if 0\n\t\tmp->rfe_sel_a_0 = odm_get_bb_reg(dm, R_0x1840, MASKDWORD);\n\t\tmp->rfe_sel_b_0 = odm_get_bb_reg(dm, R_0x4140, MASKDWORD);\n\t\tmp->rfe_sel_c_0 = odm_get_bb_reg(dm, R_0x5240, MASKDWORD);\n\t\tmp->rfe_sel_d_0 = odm_get_bb_reg(dm, R_0x5340, MASKDWORD);\n\t\tmp->rfe_sel_a_1 = odm_get_bb_reg(dm, R_0x1844, MASKDWORD);\n\t\tmp->rfe_sel_b_1 = odm_get_bb_reg(dm, R_0x4144, MASKDWORD);\n\t\tmp->rfe_sel_c_1 = odm_get_bb_reg(dm, R_0x5244, MASKDWORD);\n\t\tmp->rfe_sel_d_1 = odm_get_bb_reg(dm, R_0x5344, MASKDWORD);\n#endif\n\t\t/* Disable CCK and OFDM */\n\t\todm_set_bb_reg(dm, R_0x1c3c, 0x3, 0x0);\n\t\tfor (i = start; i <= end; i++) {\n\t\t\t/* @Tx mode: RF0x00[19:16]=4'b0010 */\n\t\t\todm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);\n\t\t\t/* @Lowest RF gain index: RF_0x0[4:0] = 0*/\n\t\t\todm_set_rf_reg(dm, i, RF_0x0, 0x1F, 0x0);\n\t\t\t/* @RF LO enabled */\n\t\t\todm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);\n\t\t}\n\t\t#if (RTL8814B_SUPPORT)\n\t\tif (dm->support_ic_type & ODM_RTL8814B) {\n\t\t\t/* @Tx mode: RF0x00[19:16]=4'b0010 */\n\t\t\tconfig_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,\n\t\t\t\t\t\t\t0xF0000, 0x2);\n\t\t\t/* @Lowest RF gain index: RF_0x0[4:0] = 0*/\n\t\t\tconfig_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,\n\t\t\t\t\t\t\t0x1F, 0x0);\n\t\t\t/* @RF LO enabled */\n\t\t\tconfig_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,\n\t\t\t\t\t\t\tBIT(1), 0x1);\n\t\t}\n\t\t#endif\n\t} else {\n\t\t/* Eable CCK and OFDM */\n\t\todm_set_bb_reg(dm, R_0x1c3c, 0x3, 0x3);\n\t\tif (!(dm->support_ic_type & ODM_RTL8814B)) {\n\t\t\tfor (i = start; i <= end; i++) {\n\t\t\t\todm_set_rf_reg(dm, i, RF_0x00, 0xfffff,\n\t\t\t\t\t       mp->rf_reg0);\n\t\t\t\t/* RF LO disabled */\n\t\t\t\todm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);\n\t\t\t}\n\t\t}\n#if 0\n\t\todm_set_bb_reg(dm, R_0x1840, MASKDWORD, mp->rfe_sel_a_0);\n\t\todm_set_bb_reg(dm, R_0x4140, MASKDWORD, mp->rfe_sel_b_0);\n\t\todm_set_bb_reg(dm, R_0x5240, MASKDWORD, mp->rfe_sel_c_0);\n\t\todm_set_bb_reg(dm, R_0x5340, MASKDWORD, mp->rfe_sel_d_0);\n\t\todm_set_bb_reg(dm, R_0x1844, MASKDWORD, mp->rfe_sel_a_1);\n\t\todm_set_bb_reg(dm, R_0x4144, MASKDWORD, mp->rfe_sel_b_1);\n\t\todm_set_bb_reg(dm, R_0x5244, MASKDWORD, mp->rfe_sel_c_1);\n\t\todm_set_bb_reg(dm, R_0x5344, MASKDWORD, mp->rfe_sel_d_1);\n#endif\n\t}\n}\n\nvoid phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp,\n\t\t\t\t    u32 rate_index)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_mp *mp = &dm->dm_mp_table;\n\n\tif (is_carrier_supp) {\n\t\tif (phydm_is_cck_rate(dm, (u8)rate_index)) {\n\t\t\t/* @if CCK block on? */\n\t\t\tif (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))\n\t\t\t\todm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1);\n\n\t\t\t/* @Turn Off All Test mode */\n\t\t\todm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);\n\n\t\t\t/* @transmit mode */\n\t\t\todm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2);\n\t\t\t/* @turn off scramble setting */\n\t\t\todm_set_bb_reg(dm, R_0x1a00, 0x8, 0x0);\n\t\t\t/* @Set CCK Tx Test Rate, set FTxRate to 1Mbps */\n\t\t\todm_set_bb_reg(dm, R_0x1a00, 0x3000, 0x0);\n\t\t}\n\t} else { /* @Stop Carrier Suppression. */\n\t\tif (phydm_is_cck_rate(dm, (u8)rate_index)) {\n\t\t\t/* @normal mode */\n\t\t\todm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);\n\t\t\t/* @turn on scramble setting */\n\t\t\todm_set_bb_reg(dm, R_0x1a00, 0x8, 0x1);\n\t\t\t/* @BB Reset */\n\t\t\todm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0);\n\t\t\todm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1);\n\t\t}\n\t}\n}\n#endif\n\nvoid phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tphydm_set_crystal_cap(dm, crystal_cap);\n}\n\nvoid phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tphydm_mp_set_single_tone_jgr3(dm, is_single_tone, path);\n}\n\nvoid phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,\n\t\t\t       u32 rate_index)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tphydm_mp_set_carrier_supp_jgr3(dm, is_carrier_supp, rate_index);\n}\n\nvoid phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_mp *mp = &dm->dm_mp_table;\n\n\tif (is_single_carrier) {\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t\t/* @1. if OFDM block on? */\n\t\t\tif (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))\n\t\t\t\todm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1);\n\n\t\t\t/* @2. set CCK test mode off, set to CCK normal mode */\n\t\t\todm_set_bb_reg(dm, R_0x1a00, 0x3, 0);\n\n\t\t\t/* @3. turn on scramble setting */\n\t\t\todm_set_bb_reg(dm, R_0x1a00, 0x8, 1);\n\n\t\t\t/* @4. Turn On single carrier. */\n\t\t\todm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);\n\t\t} else {\n\t\t\t/* @1. if OFDM block on? */\n\t\t\tif (!odm_get_bb_reg(dm, R_0x800, 0x2000000))\n\t\t\t\todm_set_bb_reg(dm, R_0x800, 0x2000000, 1);\n\n\t\t\t/* @2. set CCK test mode off, set to CCK normal mode */\n\t\t\todm_set_bb_reg(dm, R_0xa00, 0x3, 0);\n\n\t\t\t/* @3. turn on scramble setting */\n\t\t\todm_set_bb_reg(dm, R_0xa00, 0x8, 1);\n\n\t\t\t/* @4. Turn On single carrier. */\n\t\t\tif (dm->support_ic_type & ODM_IC_11AC_SERIES)\n\t\t\t\todm_set_bb_reg(dm, R_0x914, 0x70000,\n\t\t\t\t\t       OFDM_SINGLE_CARRIER);\n\t\t\telse if (dm->support_ic_type & ODM_IC_11N_SERIES)\n\t\t\t\todm_set_bb_reg(dm, R_0xd00, 0x70000000,\n\t\t\t\t\t       OFDM_SINGLE_CARRIER);\n\t\t}\n\t} else { /* @Stop Single Carrier. */\n\t    /* @Turn off all test modes. */\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\t\todm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_OFF);\n\t\telse if (dm->support_ic_type & ODM_IC_11AC_SERIES)\n\t\t\todm_set_bb_reg(dm, R_0x914, 0x70000, OFDM_OFF);\n\t\telse if (dm->support_ic_type & ODM_IC_11N_SERIES)\n\t\t\todm_set_bb_reg(dm, R_0xd00, 0x70000000, OFDM_OFF);\n\t\t/* @Delay 10 ms */\n\t\tODM_delay_ms(10);\n\n\t\t/* @BB Reset */\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t\todm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0);\n\t\t\todm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1);\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0x100, 0x100, 0x0);\n\t\t\todm_set_bb_reg(dm, R_0x100, 0x100, 0x1);\n\t\t}\n\t} \n}\nvoid phydm_mp_reset_rx_counters_phy(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tphydm_reset_bb_hw_cnt(dm);\n}\n\nvoid phydm_mp_get_tx_ok(void *dm_void, u32 rate_index)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_mp *mp = &dm->dm_mp_table;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tif (phydm_is_cck_rate(dm, (u8)rate_index))\n\t\t\tmp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de4,\n\t\t\t\t\t\t\t   0xffff);\n\t\telse\n\t\t\tmp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de0,\n\t\t\t\t\t\t\t   0xffff);\n\t} else {\n\t\tif (phydm_is_cck_rate(dm, (u8)rate_index))\n\t\t\tmp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0xf50,\n\t\t\t\t\t\t\t   0xffff);\n\t\telse\n\t\t\tmp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0xf50,\n\t\t\t\t\t\t\t   0xffff0000);\n\t}\n}\n\nvoid phydm_mp_get_rx_ok(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_mp *mp = &dm->dm_mp_table;\t\n\n\tu32 cck_ok = 0, ofdm_ok = 0, ht_ok = 0, vht_ok = 0;\t\n\tu32 cck_err = 0, ofdm_err = 0, ht_err = 0, vht_err = 0;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tcck_ok = odm_get_bb_reg(dm, R_0x2c04, 0xffff);\n\t\tofdm_ok = odm_get_bb_reg(dm, R_0x2c14, 0xffff);\n\t\tht_ok = odm_get_bb_reg(dm, R_0x2c10, 0xffff);\n\t\tvht_ok = odm_get_bb_reg(dm, R_0x2c0c, 0xffff);\n  \n\t\tcck_err = odm_get_bb_reg(dm, R_0x2c04, 0xffff0000);\n\t\tofdm_err = odm_get_bb_reg(dm, R_0x2c14, 0xffff0000);\n\t\tht_err = odm_get_bb_reg(dm, R_0x2c10, 0xffff0000);\n\t\tvht_err = odm_get_bb_reg(dm, R_0x2c0c, 0xffff0000);\n\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\tcck_ok = odm_get_bb_reg(dm, R_0xf04, 0x3FFF);\n\t\tofdm_ok = odm_get_bb_reg(dm, R_0xf14, 0x3FFF);\n\t\tht_ok = odm_get_bb_reg(dm, R_0xf10, 0x3FFF);\n\t\tvht_ok = odm_get_bb_reg(dm, R_0xf0c, 0x3FFF);\n  \n\t\tcck_err = odm_get_bb_reg(dm, R_0xf04, 0x3FFF0000);\n\t\tofdm_err = odm_get_bb_reg(dm, R_0xf14, 0x3FFF0000);\n\t\tht_err = odm_get_bb_reg(dm, R_0xf10, 0x3FFF0000);\n\t\tvht_err = odm_get_bb_reg(dm, R_0xf0c, 0x3FFF0000);\n\t} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\tcck_ok = odm_get_bb_reg(dm, R_0xf88, MASKDWORD);\n\t\tofdm_ok = odm_get_bb_reg(dm, R_0xf94, 0xffff);\n\t\tht_ok = odm_get_bb_reg(dm, R_0xf90, 0xffff);\n\t    \n\t\tcck_err = odm_get_bb_reg(dm, R_0xf84, MASKDWORD);\n\t\tofdm_err = odm_get_bb_reg(dm, R_0xf94, 0xffff0000);\n\t\tht_err = odm_get_bb_reg(dm, R_0xf90, 0xffff0000);\n\t}\n\n\tmp->rx_phy_ok_cnt = cck_ok + ofdm_ok + ht_ok + vht_ok;\n\tmp->rx_phy_crc_err_cnt = cck_err + ofdm_err + ht_err + vht_err;\n\tmp->io_value = (u32)mp->rx_phy_ok_cnt;\n}\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_mp.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDM_MP_H__\n#define __PHYDM_MP_H__\n\n#define MP_VERSION \"1.3\"\n\n/* @1 ============================================================\n * 1  Definition\n * 1 ============================================================\n */\n/* @1 ============================================================\n * 1  structure\n * 1 ============================================================\n */\nstruct phydm_mp {\n\t/* @Rx OK count, statistics used in Mass Production Test.*/\n\tu64 tx_phy_ok_cnt;\n\tu64 rx_phy_ok_cnt;\n\t/* @Rx CRC32 error count, statistics used in Mass Production Test.*/\n\tu64 rx_phy_crc_err_cnt;\n\t/* @The Value of IO operation is depend of MptActType.*/\n\tu32 io_value;\n\tu32 rf_reg0;\n\t/* @u32 rfe_sel_a_0;*/\n\t/* @u32 rfe_sel_b_0;*/\n\t/* @u32 rfe_sel_c_0;*/\n\t/* @u32 rfe_sel_d_0;*/\n\t/* @u32 rfe_sel_a_1;*/\n\t/* @u32 rfe_sel_b_1;*/\n\t/* @u32 rfe_sel_c_1;*/\n\t/* @u32 rfe_sel_d_1;*/\n};\n\n/* @1 ============================================================\n * 1  enumeration\n * 1 ============================================================\n */\nenum TX_MODE_OFDM {\n\tOFDM_OFF = 0,\t\n\tOFDM_CONT_TX = 1,\n\tOFDM_SINGLE_CARRIER = 2,\n\tOFDM_SINGLE_TONE = 4,\n};\n/* @1 ============================================================\n * 1  function prototype\n * 1 ============================================================\n */\nvoid phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap);\n\nvoid phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path);\n\nvoid phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,\n\t\t\t       u32 rate_index);\n\nvoid phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier);\n\nvoid phydm_mp_reset_rx_counters_phy(void *dm_void);\n\nvoid phydm_mp_get_tx_ok(void *dm_void, u32 rate_index);\n\nvoid phydm_mp_get_rx_ok(void *dm_void);\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_noisemonitor.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*************************************************************\n * include files\n ************************************************************/\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n/**************************************************\n * This function is for inband noise test utility only\n * To obtain the inband noise level(dbm), do the following.\n * 1. disable DIG and Power Saving\n * 2. Set initial gain = 0x1a\n * 3. Stop updating idle time pwer report (for driver read)\n *\t- 0x80c[25]\n *\n *************************************************/\n\nvoid phydm_set_noise_data_sum(struct noise_level *noise_data, u8 max_rf_path)\n{\n\tu8 i = 0;\n\n\tfor (i = RF_PATH_A; i < max_rf_path; i++) {\n\t\tif (noise_data->valid_cnt[i])\n\t\t\tnoise_data->sum[i] /= noise_data->valid_cnt[i];\n\t\telse\n\t\t\tnoise_data->sum[i] = 0;\n\t}\n}\n\n#if (ODM_IC_11N_SERIES_SUPPORT)\ns16 odm_inband_noise_monitor_n(struct dm_struct *dm, u8 is_pause_dig, u8 igi,\n\t\t\t       u32 max_time)\n{\n\tu32 tmp4b;\n\tu8 max_rf_path = 0, i = 0;\n\tu8 reg_c50, reg_c58, valid_done = 0;\n\tstruct noise_level noise_data;\n\tu64 start = 0, func_start = 0, func_end = 0;\n\ts8 val_s8 = 0;\n\n\tfunc_start = odm_get_current_time(dm);\n\tdm->noise_level.noise_all = 0;\n\n\tif (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R)\n\t\tmax_rf_path = 2;\n\telse\n\t\tmax_rf_path = 1;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t  \"odm_DebugControlInbandNoise_Nseries() ==>\\n\");\n\n\todm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));\n\t/* step 1. Disable DIG && Set initial gain. */\n\n\tif (is_pause_dig)\n\t\todm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);\n\n\t/* step 3. Get noise power level */\n\tstart = odm_get_current_time(dm);\n\twhile (1) {\n\t\t/* Stop updating idle time pwer report (for driver read) */\n\t\todm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1);\n\n\t\t/* Read Noise Floor Report */\n\t\ttmp4b = odm_get_bb_reg(dm, R_0x8f8, MASKDWORD);\n\n\t\t/* update idle time pwer report per 5us */\n\t\todm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0);\n\n\t\tODM_delay_us(5);\n\n\t\tnoise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff);\n\t\tnoise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);\n\n\t\tfor (i = RF_PATH_A; i < max_rf_path; i++) {\n\t\t\tnoise_data.sval[i] = (s8)noise_data.value[i];\n\t\t\tnoise_data.sval[i] /= 2;\n\t\t}\n\n\t\tfor (i = RF_PATH_A; i < max_rf_path; i++) {\n\t\t\tif (noise_data.valid_cnt[i] >= VALID_CNT)\n\t\t\t\tcontinue;\n\n\t\t\tnoise_data.valid_cnt[i]++;\n\t\t\tnoise_data.sum[i] += noise_data.sval[i];\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t\t\t  \"rf_path:%d Valid sval=%d\\n\", i,\n\t\t\t\t  noise_data.sval[i]);\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"Sum of sval = %d,\\n\",\n\t\t\t\t  noise_data.sum[i]);\n\t\t\tif (noise_data.valid_cnt[i] == VALID_CNT)\n\t\t\t\tvalid_done++;\n\t\t}\n\t\tif (valid_done == max_rf_path ||\n\t\t    (odm_get_progressing_time(dm, start) > max_time)) {\n\t\t\tphydm_set_noise_data_sum(&noise_data, max_rf_path);\n\t\t\tbreak;\n\t\t}\n\t}\n\treg_c50 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0);\n\treg_c50 &= ~BIT(7);\n\tval_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);\n\tdm->noise_level.noise[RF_PATH_A] = val_s8;\n\tdm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A];\n\n\tif (max_rf_path == 2) {\n\t\treg_c58 = (u8)odm_get_bb_reg(dm, R_0xc58, MASKBYTE0);\n\t\treg_c58 &= ~BIT(7);\n\t\tval_s8 = (s8)(-110 + reg_c58 + noise_data.sum[RF_PATH_B]);\n\t\tdm->noise_level.noise[RF_PATH_B] = val_s8;\n\t\tdm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B];\n\t}\n\tdm->noise_level.noise_all /= max_rf_path;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t  \"noise_a = %d, noise_b = %d, noise_all = %d\\n\",\n\t\t  dm->noise_level.noise[RF_PATH_A],\n\t\t  dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all);\n\n\t/* step 4. Recover the Dig */\n\tif (is_pause_dig)\n\t\todm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);\n\tfunc_end = odm_get_progressing_time(dm, func_start);\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"end\\n\");\n\treturn dm->noise_level.noise_all;\n}\n#endif\n\n#if (ODM_IC_11AC_SERIES_SUPPORT)\ns16 phydm_idle_noise_measure_ac(struct dm_struct *dm, u8 pause_dig,\n\t\t\t\tu8 igi, u32 max_time)\n{\n\tu32 tmp4b;\n\tu8 max_rf_path = 0, i = 0;\n\tu8 reg_c50, reg_e50, valid_done = 0;\n\tu64 start = 0, func_start = 0, func_end = 0;\n\tstruct noise_level noise_data;\n\ts8 val_s8 = 0;\n\n\tfunc_start = odm_get_current_time(dm);\n\tdm->noise_level.noise_all = 0;\n\n\tif (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R)\n\t\tmax_rf_path = 2;\n\telse\n\t\tmax_rf_path = 1;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"%s==>\\n\", __func__);\n\n\todm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));\n\n\t/*Step 1. Disable DIG && Set initial gain.*/\n\n\tif (pause_dig)\n\t\todm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);\n\n\t/*Step 2. Get noise power level*/\n\tstart = odm_get_current_time(dm);\n\n\twhile (1) {\n\t\t/*Stop updating idle time pwer report (for driver read)*/\n\t\todm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x1);\n\n\t\t/*Read Noise Floor Report*/\n\t\ttmp4b = odm_get_bb_reg(dm, R_0xff0, MASKDWORD);\n\n\t\t/*update idle time pwer report per 5us*/\n\t\todm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x0);\n\n\t\tODM_delay_us(5);\n\n\t\tnoise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff);\n\t\tnoise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);\n\n\t\tfor (i = RF_PATH_A; i < max_rf_path; i++) {\n\t\t\tnoise_data.sval[i] = (s8)noise_data.value[i];\n\t\t\tnoise_data.sval[i] = noise_data.sval[i] >> 1;\n\t\t}\n\n\t\tfor (i = RF_PATH_A; i < max_rf_path; i++) {\n\t\t\tif (noise_data.valid_cnt[i] >= VALID_CNT)\n\t\t\t\tcontinue;\n\n\t\t\tnoise_data.valid_cnt[i]++;\n\t\t\tnoise_data.sum[i] += noise_data.sval[i];\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"Path:%d Valid sval = %d\\n\",\n\t\t\t\t  i, noise_data.sval[i]);\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"Sum of sval = %d\\n\",\n\t\t\t\t  noise_data.sum[i]);\n\t\t\tif (noise_data.valid_cnt[i] == VALID_CNT)\n\t\t\t\tvalid_done++;\n\t\t}\n\n\t\tif (valid_done == max_rf_path ||\n\t\t    (odm_get_progressing_time(dm, start) > max_time)) {\n\t\t\tphydm_set_noise_data_sum(&noise_data, max_rf_path);\n\t\t\tbreak;\n\t\t}\n\t}\n\treg_c50 = (u8)odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);\n\treg_c50 &= ~BIT(7);\n\tval_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);\n\tdm->noise_level.noise[RF_PATH_A] = val_s8;\n\tdm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A];\n\n\tif (max_rf_path == 2) {\n\t\treg_e50 = (u8)odm_get_bb_reg(dm, R_0xe50, MASKBYTE0);\n\t\treg_e50 &= ~BIT(7);\n\t\tval_s8 = (s8)(-110 + reg_e50 + noise_data.sum[RF_PATH_B]);\n\t\tdm->noise_level.noise[RF_PATH_B] = val_s8;\n\t\tdm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B];\n\t}\n\tdm->noise_level.noise_all /= max_rf_path;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t  \"noise_a = %d, noise_b = %d, noise_all = %d\\n\",\n\t\t  dm->noise_level.noise[RF_PATH_A],\n\t\t  dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all);\n\n\t/*Step 3. Recover the Dig*/\n\tif (pause_dig)\n\t\todm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);\n\tfunc_end = odm_get_progressing_time(dm, func_start);\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"end\\n\");\n\treturn dm->noise_level.noise_all;\n}\n\ns16 odm_inband_noise_monitor_ac(struct dm_struct *dm, u8 pause_dig, u8 igi,\n\t\t\t\tu32 max_time)\n{\n\ts32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/\n\ts32 value32, pwdb_A = 0, sval, noise, sum = 0;\n\tboolean pd_flag;\n\tu8 valid_cnt = 0;\n\tu64 start = 0, func_start = 0, func_end = 0;\n\ts32 val_s32 = 0;\n\ts16 rpt = 0;\n\tu8 val_u8 = 0;\n\n\tif (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {\n\t\trpt = phydm_idle_noise_measure_ac(dm, pause_dig, igi, max_time);\n\t\treturn rpt;\n\t}\n\n\tif (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A)))\n\t\treturn 0;\n\n\tfunc_start = odm_get_current_time(dm);\n\tdm->noise_level.noise_all = 0;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"%s ==>\\n\", __func__);\n\n\t/* step 1. Disable DIG && Set initial gain. */\n\tif (pause_dig)\n\t\todm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);\n\n\t/* step 3. Get noise power level */\n\tstart = odm_get_current_time(dm);\n\n\t/* step 3. Get noise power level */\n\twhile (1) {\n\t\t/*Set IGI=0x1C */\n\t\todm_write_dig(dm, 0x1C);\n\t\t/*stop CK320&CK88 */\n\t\todm_set_bb_reg(dm, R_0x8b4, BIT(6), 1);\n\t\t/*Read path-A */\n\t\t/*set debug port*/\n\t\todm_set_bb_reg(dm, R_0x8fc, MASKDWORD, 0x200);\n\t\t/*read debug port*/\n\t\tvalue32 = odm_get_bb_reg(dm, R_0xfa0, MASKDWORD);\n\t\t/*rxi_buf_anta=RegFA0[19:10]*/\n\t\trxi_buf_anta = (value32 & 0xFFC00) >> 10;\n\t\trxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/\n\n\t\tpd_flag = (boolean)((value32 & BIT(31)) >> 31);\n\n\t\t/*Not in packet detection period or Tx state */\n\t\tif (!pd_flag || rxi_buf_anta != 0x200) {\n\t\t\t/*sign conversion*/\n\t\t\trxi_buf_anta = odm_sign_conversion(rxi_buf_anta, 10);\n\t\t\trxq_buf_anta = odm_sign_conversion(rxq_buf_anta, 10);\n\n\t\t\tval_s32 = rxi_buf_anta * rxi_buf_anta +\n\t\t\t\t  rxq_buf_anta * rxq_buf_anta;\n\t\t\t/*S(10,9)*S(10,9)=S(20,18)*/\n\t\t\tpwdb_A = odm_pwdb_conversion(val_s32, 20, 18);\n\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t\t\t  \"pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\\n\",\n\t\t\t\t  pwdb_A, rxi_buf_anta & 0x3FF,\n\t\t\t\t  rxq_buf_anta & 0x3FF);\n\t\t}\n\t\t/*Start CK320&CK88*/\n\t\todm_set_bb_reg(dm, R_0x8b4, BIT(6), 0);\n\t\t/*@BB Reset*/\n\t\tval_u8 = odm_read_1byte(dm, 0x02) & (~BIT(0));\n\t\todm_write_1byte(dm, 0x02, val_u8);\n\t\tval_u8 = odm_read_1byte(dm, 0x02) | BIT(0);\n\t\todm_write_1byte(dm, 0x02, val_u8);\n\t\t/*PMAC Reset*/\n\t\tval_u8 = odm_read_1byte(dm, 0xB03) & (~BIT(0));\n\t\todm_write_1byte(dm, 0xB03, val_u8);\n\t\tval_u8 = odm_read_1byte(dm, 0xB03) | BIT(0);\n\t\todm_write_1byte(dm, 0xB03, val_u8);\n\t\t/*@CCK Reset*/\n\t\tif (odm_read_1byte(dm, 0x80B) & BIT(4)) {\n\t\t\tval_u8 = odm_read_1byte(dm, 0x80B) & (~BIT(4));\n\t\t\todm_write_1byte(dm, 0x80B, val_u8);\n\t\t\tval_u8 = odm_read_1byte(dm, 0x80B) | BIT(4);\n\t\t\todm_write_1byte(dm, 0x80B, val_u8);\n\t\t}\n\n\t\tsval = pwdb_A;\n\n\t\tif ((sval < 0 && sval >= -27) && valid_cnt < VALID_CNT) {\n\t\t\tvalid_cnt++;\n\t\t\tsum += sval;\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"Valid sval = %d\\n\", sval);\n\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"Sum of sval = %d,\\n\", sum);\n\t\t\tif (valid_cnt >= VALID_CNT ||\n\t\t\t    (odm_get_progressing_time(dm, start) > max_time)) {\n\t\t\t\tsum /= VALID_CNT;\n\t\t\t\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t\t\t\t  \"After divided, sum = %d\\n\", sum);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\t/*@ADC backoff is 12dB,*/\n\t/*Ptarget=0x1C-110=-82dBm*/\n\tnoise = sum + 12 + 0x1C - 110;\n\n\t/*Offset*/\n\tnoise = noise - 3;\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"noise = %d\\n\", noise);\n\tdm->noise_level.noise_all = (s16)noise;\n\n\t/* step 4. Recover the Dig*/\n\tif (pause_dig)\n\t\todm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);\n\n\tfunc_end = odm_get_progressing_time(dm, func_start);\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR, \"%s <==\\n\", __func__);\n\n\treturn dm->noise_level.noise_all;\n}\n#endif\n\ns16 odm_inband_noise_monitor(void *dm_void, u8 pause_dig, u8 igi,\n\t\t\t     u32 max_time)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\ts16 val = 0;\n\n\tigi = 0x32;\n\n\t/* since HW ability is about +15~-35,\n\t * we fix IGI = -60 for maximum coverage\n\t */\n\t#if (ODM_IC_11AC_SERIES_SUPPORT)\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES)\n\t\tval = odm_inband_noise_monitor_ac(dm, pause_dig, igi, max_time);\n\t#endif\n\n\t#if (ODM_IC_11N_SERIES_SUPPORT)\n\tif (dm->support_ic_type & ODM_IC_11N_SERIES)\n\t\tval = odm_inband_noise_monitor_n(dm, pause_dig, igi, max_time);\n\t#endif\n\n\treturn val;\n}\n\nvoid phydm_noisy_detection(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 total_fa_cnt, total_cca_cnt;\n\tu32 score = 0, i, score_smooth;\n\n\ttotal_cca_cnt = dm->false_alm_cnt.cnt_cca_all;\n\ttotal_fa_cnt = dm->false_alm_cnt.cnt_all;\n\n#if 0\n\tif (total_fa_cnt * 16 >= total_cca_cnt * 14)    /*  @87.5 */\n\t\t;\n\telse if (total_fa_cnt * 16 >= total_cca_cnt * 12) /*  @75 */\n\t\t;\n\telse if (total_fa_cnt * 16 >= total_cca_cnt * 10) /*  @56.25 */\n\t\t;\n\telse if (total_fa_cnt * 16 >= total_cca_cnt * 8) /*  @50 */\n\t\t;\n\telse if (total_fa_cnt * 16 >= total_cca_cnt * 7) /*  @43.75 */\n\t\t;\n\telse if (total_fa_cnt * 16 >= total_cca_cnt * 6) /*  @37.5 */\n\t\t;\n\telse if (total_fa_cnt * 16 >= total_cca_cnt * 5) /*  @31.25% */\n\t\t;\n\telse if (total_fa_cnt * 16 >= total_cca_cnt * 4) /*  @25% */\n\t\t;\n\telse if (total_fa_cnt * 16 >= total_cca_cnt * 3) /*  @18.75% */\n\t\t;\n\telse if (total_fa_cnt * 16 >= total_cca_cnt * 2) /*  @12.5% */\n\t\t;\n\telse if (total_fa_cnt * 16 >= total_cca_cnt * 1) /*  @6.25% */\n\t\t;\n#endif\n\tfor (i = 0; i <= 16; i++) {\n\t\tif (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) {\n\t\t\tscore = 16 - i;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */\n\tdm->noisy_decision_smooth = (dm->noisy_decision_smooth >> 1) +\n\t\t\t\t    (score << 2);\n\n\t/* Round the noisy_decision_smooth: +\"3\" comes from (2^3)/2-1 */\n\tif (total_cca_cnt >= 300)\n\t\tscore_smooth = (dm->noisy_decision_smooth + 3) >> 3;\n\telse\n\t\tscore_smooth = 0;\n\n\tdm->noisy_decision = (score_smooth >= 3) ? 1 : 0;\n\n\tPHYDM_DBG(dm, DBG_ENV_MNTR,\n\t\t  \"[NoisyDetection] CCA_cnt=%d,FA_cnt=%d, noisy_dec_smooth=%d, score=%d, score_smooth=%d, noisy_dec=%d\\n\",\n\t\t  total_cca_cnt, total_fa_cnt, dm->noisy_decision_smooth, score,\n\t\t  score_smooth, dm->noisy_decision);\n}\n"
  },
  {
    "path": "hal/phydm/phydm_noisemonitor.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#ifndef __ODMNOISEMONITOR_H__\n#define __ODMNOISEMONITOR_H__\n\n#define VALID_CNT 5\n\nstruct noise_level {\n\tu8 value[PHYDM_MAX_RF_PATH];\n\ts8 sval[PHYDM_MAX_RF_PATH];\n\ts32 sum[PHYDM_MAX_RF_PATH];\n\tu8 valid[PHYDM_MAX_RF_PATH];\n\tu8 valid_cnt[PHYDM_MAX_RF_PATH];\n};\n\nstruct odm_noise_monitor {\n\ts8 noise[PHYDM_MAX_RF_PATH];\n\ts16 noise_all;\n};\n\ns16 odm_inband_noise_monitor(void *dm_void, u8 is_pause_dig, u8 igi_value,\n\t\t\t     u32 max_time);\n\nvoid phydm_noisy_detection(void *dm_void);\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_pathdiv.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*************************************************************\n * include files\n ************************************************************/\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#ifdef CONFIG_PATH_DIVERSITY\n#if RTL8814A_SUPPORT\nvoid phydm_dtp_fix_tx_path(\n\tvoid *dm_void,\n\tu8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\tu8 i, num_enable_path = 0;\n\n\tif (path == p_div->pre_tx_path)\n\t\treturn;\n\telse\n\t\tp_div->pre_tx_path = path;\n\n\todm_set_bb_reg(dm, R_0x93c, BIT(18) | BIT(19), 3);\n\n\tfor (i = 0; i < 4; i++) {\n\t\tif (path & BIT(i))\n\t\t\tnum_enable_path++;\n\t}\n\tPHYDM_DBG(dm, DBG_PATH_DIV, \" number of turn-on path : (( %d ))\\n\",\n\t\t  num_enable_path);\n\n\tif (num_enable_path == 1) {\n\t\todm_set_bb_reg(dm, R_0x93c, 0xf00000, path);\n\n\t\tif (path == BB_PATH_A) { /* @1-1 */\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV, \" Turn on path (( A ))\\n\");\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);\n\t\t} else if (path == BB_PATH_B) { /* @1-2 */\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV, \" Turn on path (( B ))\\n\");\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0);\n\t\t} else if (path == BB_PATH_C) { /* @1-3 */\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV, \" Turn on path (( C ))\\n\");\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 0);\n\n\t\t} else if (path == BB_PATH_D) { /* @1-4 */\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV, \" Turn on path (( D ))\\n\");\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 0);\n\t\t}\n\n\t} else if (num_enable_path == 2) {\n\t\todm_set_bb_reg(dm, R_0x93c, 0xf00000, path);\n\t\todm_set_bb_reg(dm, R_0x940, 0xf0, path);\n\n\t\tif (path == (BB_PATH_AB)) { /* @2-1 */\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV,\n\t\t\t\t  \" Turn on path (( A B ))\\n\");\n\t\t\t/* set for 1ss */\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1);\n\t\t\t/* set for 2ss */\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1);\n\t\t} else if (path == BB_PATH_AC) { /* @2-2 */\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV,\n\t\t\t\t  \" Turn on path (( A C ))\\n\");\n\t\t\t/* set for 1ss */\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1);\n\t\t\t/* set for 2ss */\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1);\n\t\t} else if (path == BB_PATH_AD) { /* @2-3 */\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV,\n\t\t\t\t  \" Turn on path (( A D ))\\n\");\n\t\t\t/* set for 1ss */\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1);\n\t\t\t/* set for 2ss */\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1);\n\t\t} else if (path == BB_PATH_BC) { /* @2-4 */\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV,\n\t\t\t\t  \" Turn on path (( B C ))\\n\");\n\t\t\t/* set for 1ss */\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0);\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1);\n\t\t\t/* set for 2ss */\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1);\n\t\t} else if (path == BB_PATH_BD) { /* @2-5 */\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV,\n\t\t\t\t  \" Turn on path (( B D ))\\n\");\n\t\t\t/* set for 1ss */\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0);\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1);\n\t\t\t/* set for 2ss */\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1);\n\t\t} else if (path == BB_PATH_CD) { /* @2-6 */\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV,\n\t\t\t\t  \" Turn on path (( C D ))\\n\");\n\t\t\t/* set for 1ss */\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 0);\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1);\n\t\t\t/* set for 2ss */\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 0);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1);\n\t\t}\n\n\t} else if (num_enable_path == 3) {\n\t\todm_set_bb_reg(dm, R_0x93c, 0xf00000, path);\n\t\todm_set_bb_reg(dm, R_0x940, 0xf0, path);\n\t\todm_set_bb_reg(dm, R_0x940, 0xf0000, path);\n\n\t\tif (path == BB_PATH_ABC) { /* @3-1 */\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV,\n\t\t\t\t  \" Turn on path (( A B C))\\n\");\n\t\t\t/* set for 1ss */\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1);\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 2);\n\t\t\t/* set for 2ss */\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 2);\n\t\t\t/* set for 3ss */\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 1);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 2);\n\t\t} else if (path == BB_PATH_ABD) { /* @3-2 */\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV,\n\t\t\t\t  \" Turn on path (( A B D ))\\n\");\n\t\t\t/* set for 1ss */\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1);\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2);\n\t\t\t/* set for 2ss */\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2);\n\t\t\t/* set for 3ss */\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 1);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2);\n\n\t\t} else if (path == BB_PATH_ACD) { /* @3-3 */\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV,\n\t\t\t\t  \" Turn on path (( A C D ))\\n\");\n\t\t\t/* set for 1ss */\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1);\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2);\n\t\t\t/* set for 2ss */\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2);\n\t\t\t/* set for 3ss */\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 1);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2);\n\t\t} else if (path == BB_PATH_BCD) { /* @3-4 */\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV,\n\t\t\t\t  \" Turn on path (( B C D))\\n\");\n\t\t\t/* set for 1ss */\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0);\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1);\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2);\n\t\t\t/* set for 2ss */\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2);\n\t\t\t/* set for 3ss */\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 0);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 1);\n\t\t\todm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2);\n\t\t}\n\t} else if (num_enable_path == 4)\n\t\tPHYDM_DBG(dm, DBG_PATH_DIV, \" Turn on path ((A  B C D))\\n\");\n}\n\nvoid phydm_find_default_path(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\tu32 rssi_a = 0, rssi_b = 0, rssi_c = 0, rssi_d = 0, rssi_bcd = 0;\n\tu32 rssi_total_a = 0, rssi_total_b = 0;\n\tu32 rssi_total_c = 0, rssi_total_d = 0;\n\n\t/* @2 Default path Selection By RSSI */\n\n\trssi_a = (p_div->path_a_cnt_all > 0) ?\n\t\t (p_div->path_a_sum_all / p_div->path_a_cnt_all) : 0;\n\trssi_b = (p_div->path_b_cnt_all > 0) ?\n\t\t (p_div->path_b_sum_all / p_div->path_b_cnt_all) : 0;\n\trssi_c = (p_div->path_c_cnt_all > 0) ?\n\t\t (p_div->path_c_sum_all / p_div->path_c_cnt_all) : 0;\n\trssi_d = (p_div->path_d_cnt_all > 0) ?\n\t\t (p_div->path_d_sum_all / p_div->path_d_cnt_all) : 0;\n\n\tp_div->path_a_sum_all = 0;\n\tp_div->path_a_cnt_all = 0;\n\tp_div->path_b_sum_all = 0;\n\tp_div->path_b_cnt_all = 0;\n\tp_div->path_c_sum_all = 0;\n\tp_div->path_c_cnt_all = 0;\n\tp_div->path_d_sum_all = 0;\n\tp_div->path_d_cnt_all = 0;\n\n\tif (p_div->use_path_a_as_default_ant == 1) {\n\t\trssi_bcd = (rssi_b + rssi_c + rssi_d) / 3;\n\n\t\tif ((rssi_a + ANT_DECT_RSSI_TH) > rssi_bcd) {\n\t\t\tp_div->is_path_a_exist = true;\n\t\t\tp_div->default_path = PATH_A;\n\t\t} else {\n\t\t\tp_div->is_path_a_exist = false;\n\t\t}\n\t} else {\n\t\tif (rssi_a >= rssi_b &&\n\t\t    rssi_a >= rssi_c &&\n\t\t    rssi_a >= rssi_d)\n\t\t\tp_div->default_path = PATH_A;\n\t\telse if ((rssi_b >= rssi_c) && (rssi_b >= rssi_d))\n\t\t\tp_div->default_path = PATH_B;\n\t\telse if (rssi_c >= rssi_d)\n\t\t\tp_div->default_path = PATH_C;\n\t\telse\n\t\t\tp_div->default_path = PATH_D;\n\t}\n}\n\nvoid phydm_candidate_dtp_update(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\n\tp_div->num_candidate = 3;\n\n\tif (p_div->use_path_a_as_default_ant == 1) {\n\t\tif (p_div->num_tx_path == 3) {\n\t\t\tif (p_div->is_path_a_exist) {\n\t\t\t\tp_div->ant_candidate_1 = BB_PATH_ABC;\n\t\t\t\tp_div->ant_candidate_2 = BB_PATH_ABD;\n\t\t\t\tp_div->ant_candidate_3 = BB_PATH_ACD;\n\t\t\t} else { /* use path BCD */\n\t\t\t\tp_div->num_candidate = 1;\n\t\t\t\tphydm_dtp_fix_tx_path(dm, BB_PATH_BCD);\n\t\t\t\treturn;\n\t\t\t}\n\t\t} else if (p_div->num_tx_path == 2) {\n\t\t\tif (p_div->is_path_a_exist) {\n\t\t\t\tp_div->ant_candidate_1 = BB_PATH_AB;\n\t\t\t\tp_div->ant_candidate_2 = BB_PATH_AC;\n\t\t\t\tp_div->ant_candidate_3 = BB_PATH_AD;\n\t\t\t} else {\n\t\t\t\tp_div->ant_candidate_1 = BB_PATH_BC;\n\t\t\t\tp_div->ant_candidate_2 = BB_PATH_BD;\n\t\t\t\tp_div->ant_candidate_3 = BB_PATH_CD;\n\t\t\t}\n\t\t}\n\t} else {\n\t\t/* @2 3 TX mode */\n\t\tif (p_div->num_tx_path == 3) { /* @choose 3 ant form 4 */\n\t\t\tif (p_div->default_path == PATH_A) {\n\t\t\t/* @choose 2 ant form 3 */\n\t\t\t\tp_div->ant_candidate_1 = BB_PATH_ABC;\n\t\t\t\tp_div->ant_candidate_2 = BB_PATH_ABD;\n\t\t\t\tp_div->ant_candidate_3 = BB_PATH_ACD;\n\t\t\t} else if (p_div->default_path == PATH_B) {\n\t\t\t\tp_div->ant_candidate_1 = BB_PATH_ABC;\n\t\t\t\tp_div->ant_candidate_2 = BB_PATH_ABD;\n\t\t\t\tp_div->ant_candidate_3 = BB_PATH_BCD;\n\t\t\t} else if (p_div->default_path == PATH_C) {\n\t\t\t\tp_div->ant_candidate_1 = BB_PATH_ABC;\n\t\t\t\tp_div->ant_candidate_2 = BB_PATH_ACD;\n\t\t\t\tp_div->ant_candidate_3 = BB_PATH_BCD;\n\t\t\t} else if (p_div->default_path == PATH_D) {\n\t\t\t\tp_div->ant_candidate_1 = BB_PATH_ABD;\n\t\t\t\tp_div->ant_candidate_2 = BB_PATH_ACD;\n\t\t\t\tp_div->ant_candidate_3 = BB_PATH_BCD;\n\t\t\t}\n\t\t}\n\n\t\t/* @2 2 TX mode */\n\t\telse if (p_div->num_tx_path == 2) { /* @choose 2 ant form 4 */\n\t\t\tif (p_div->default_path == PATH_A) {\n\t\t\t/* @choose 2 ant form 3 */\n\t\t\t\tp_div->ant_candidate_1 = BB_PATH_AB;\n\t\t\t\tp_div->ant_candidate_2 = BB_PATH_AC;\n\t\t\t\tp_div->ant_candidate_3 = BB_PATH_AD;\n\t\t\t} else if (p_div->default_path == PATH_B) {\n\t\t\t\tp_div->ant_candidate_1 = BB_PATH_AB;\n\t\t\t\tp_div->ant_candidate_2 = BB_PATH_BC;\n\t\t\t\tp_div->ant_candidate_3 = BB_PATH_BD;\n\t\t\t} else if (p_div->default_path == PATH_C) {\n\t\t\t\tp_div->ant_candidate_1 = BB_PATH_AC;\n\t\t\t\tp_div->ant_candidate_2 = BB_PATH_BC;\n\t\t\t\tp_div->ant_candidate_3 = BB_PATH_CD;\n\t\t\t} else if (p_div->default_path == PATH_D) {\n\t\t\t\tp_div->ant_candidate_1 = BB_PATH_AD;\n\t\t\t\tp_div->ant_candidate_2 = BB_PATH_BD;\n\t\t\t\tp_div->ant_candidate_3 = BB_PATH_CD;\n\t\t\t}\n\t\t}\n\t}\n}\n\nvoid phydm_dynamic_tx_path(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\n\tstruct sta_info *entry;\n\tu32 i;\n\tu8 num_client = 0;\n\tu8 h2c_parameter[6] = {0};\n\n\tif (!dm->is_linked) { /* @is_linked==False */\n\t\tPHYDM_DBG(dm, DBG_PATH_DIV, \"DTP_8814 [No Link!!!]\\n\");\n\n\t\tif (p_div->is_become_linked) {\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV, \"[Be disconnected]---->\\n\");\n\t\t\tp_div->is_become_linked = dm->is_linked;\n\t\t}\n\t\treturn;\n\t} else {\n\t\tif (!p_div->is_become_linked) {\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV, \" [Be Linked !!!]----->\\n\");\n\t\t\tp_div->is_become_linked = dm->is_linked;\n\t\t}\n\t}\n\n\t/* @2 [period CTRL] */\n\tif (p_div->dtp_period >= 2) {\n\t\tp_div->dtp_period = 0;\n\t} else {\n\t\tp_div->dtp_period++;\n\t\treturn;\n\t}\n\n\t/* @2 [Fix path] */\n\tif (dm->path_select != PHYDM_AUTO_PATH)\n\t\treturn;\n\n/* @2 [Check Bfer] */\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\t{\n\t\tenum beamforming_cap beamform_cap = (dm->beamforming_info.beamform_cap);\n\n\t\tif (beamform_cap & BEAMFORMER_CAP) { /* @BFmer On  &&   Div On->Div Off */\n\t\t\tif (p_div->fix_path_bfer == 0) {\n\t\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV,\n\t\t\t\t\t  \"[ PathDiv : OFF ]   BFmer ==1\\n\");\n\t\t\t\tp_div->fix_path_bfer = 1;\n\t\t\t}\n\t\t\treturn;\n\t\t} else { /* @BFmer Off   &&   Div Off->Div On */\n\t\t\tif (p_div->fix_path_bfer == 1) {\n\t\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV,\n\t\t\t\t\t  \"[ PathDiv : ON ]   BFmer ==0\\n\");\n\t\t\t\tp_div->fix_path_bfer = 0;\n\t\t\t}\n\t\t}\n\t}\n#endif\n#endif\n\n\tif (p_div->use_path_a_as_default_ant == 1) {\n\t\tphydm_find_default_path(dm);\n\t\tphydm_candidate_dtp_update(dm);\n\t} else {\n\t\tif (p_div->phydm_dtp_state == PHYDM_DTP_INIT) {\n\t\t\tphydm_find_default_path(dm);\n\t\t\tphydm_candidate_dtp_update(dm);\n\t\t\tp_div->phydm_dtp_state = PHYDM_DTP_RUNNING_1;\n\t\t}\n\n\t\telse if (p_div->phydm_dtp_state == PHYDM_DTP_RUNNING_1) {\n\t\t\tp_div->dtp_check_patha_counter++;\n\n\t\t\tif (p_div->dtp_check_patha_counter >=\n\t\t\t    NUM_RESET_DTP_PERIOD) {\n\t\t\t\tp_div->dtp_check_patha_counter = 0;\n\t\t\t\tp_div->phydm_dtp_state = PHYDM_DTP_INIT;\n\t\t\t}\n#if 0\n\t\t\t/* @2 Search space update */\n\t\t\telse {\n\t\t\t\t/* @1.  find the worst candidate */\n\n\n\t\t\t\t/* @2. repalce the worst candidate */\n\t\t\t}\n#endif\n\t\t}\n\t}\n\n\t/* @2 Dynamic path Selection H2C */\n\n\tif (p_div->num_candidate == 1) {\n\t\treturn;\n\t} else {\n\t\th2c_parameter[0] = p_div->num_candidate;\n\t\th2c_parameter[1] = p_div->num_tx_path;\n\t\th2c_parameter[2] = p_div->ant_candidate_1;\n\t\th2c_parameter[3] = p_div->ant_candidate_2;\n\t\th2c_parameter[4] = p_div->ant_candidate_3;\n\n\t\todm_fill_h2c_cmd(dm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, h2c_parameter);\n\t}\n}\n\nvoid phydm_dynamic_tx_path_init(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\tvoid *adapter = dm->adapter;\n\tu8 search_space_2[NUM_CHOOSE2_FROM4] = {BB_PATH_AB, BB_PATH_AC, BB_PATH_AD, BB_PATH_BC, BB_PATH_BD, BB_PATH_CD};\n\tu8 search_space_3[NUM_CHOOSE3_FROM4] = {BB_PATH_BCD, BB_PATH_ACD, BB_PATH_ABD, BB_PATH_ABC};\n\n#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT)\n\tp_div->is_u3_mode = (*dm->hub_usb_mode == 2) ? 1 : 0;\n\tPHYDM_DBG(dm, DBG_PATH_DIV, \"[WIN USB] is_u3_mode = (( %d ))\\n\",\n\t\t  p_div->is_u3_mode);\n#else\n\tp_div->is_u3_mode = 1;\n#endif\n\tPHYDM_DBG(dm, DBG_PATH_DIV, \"Dynamic TX path Init 8814\\n\");\n\n\tmemcpy(&p_div->search_space_2[0], &search_space_2[0],\n\t       NUM_CHOOSE2_FROM4);\n\tmemcpy(&p_div->search_space_3[0], &search_space_3[0],\n\t       NUM_CHOOSE3_FROM4);\n\n\tp_div->use_path_a_as_default_ant = 1;\n\tp_div->phydm_dtp_state = PHYDM_DTP_INIT;\n\tdm->path_select = PHYDM_AUTO_PATH;\n\tp_div->phydm_path_div_type = PHYDM_4R_PATH_DIV;\n\n\tif (p_div->is_u3_mode) {\n\t\tp_div->num_tx_path = 3;\n\t\tphydm_dtp_fix_tx_path(dm, BB_PATH_BCD); /* @3TX  Set Init TX path*/\n\n\t} else {\n\t\tp_div->num_tx_path = 2;\n\t\tphydm_dtp_fix_tx_path(dm, BB_PATH_BC); /* @2TX // Set Init TX path*/\n\t}\n}\n\nvoid phydm_process_rssi_for_path_div_8814a(void *dm_void, void *phy_info_void,\n\t\t\t\t\t   void *pkt_info_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_phyinfo_struct *phy_info = NULL;\n\tstruct phydm_perpkt_info_struct *pktinfo = NULL;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\n\tphy_info = (struct phydm_phyinfo_struct *)phy_info_void;\n\tpktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;\n\n\tif (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid))\n\t\treturn;\n\n\tif (pktinfo->data_rate <= ODM_RATE11M)\n\t\treturn;\n\n\tif (p_div->phydm_path_div_type == PHYDM_4R_PATH_DIV) {\n\t\tp_div->path_a_sum_all += phy_info->rx_mimo_signal_strength[0];\n\t\tp_div->path_a_cnt_all++;\n\n\t\tp_div->path_b_sum_all += phy_info->rx_mimo_signal_strength[1];\n\t\tp_div->path_b_cnt_all++;\n\n\t\tp_div->path_c_sum_all += phy_info->rx_mimo_signal_strength[2];\n\t\tp_div->path_c_cnt_all++;\n\n\t\tp_div->path_d_sum_all += phy_info->rx_mimo_signal_strength[3];\n\t\tp_div->path_d_cnt_all++;\n\t}\n}\n\nvoid phydm_pathdiv_debug_8814a(void *dm_void, char input[][16], u32 *_used,\n\t\t\t       char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 dm_value[10] = {0};\n\tu8 i, input_idx = 0;\n\n\tfor (i = 0; i < 5; i++) {\n\t\tif (input[i + 1]) {\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);\n\t\t\tinput_idx++;\n\t\t}\n\t}\n\n\tif (input_idx == 0)\n\t\treturn;\n\n\tdm->path_select = (u8)(dm_value[0] & 0xf);\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"Path_select = (( 0x%x ))\\n\", dm->path_select);\n\n\t/* @2 [Fix path] */\n\tif (dm->path_select != PHYDM_AUTO_PATH) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Turn on path  [%s%s%s%s]\\n\",\n\t\t\t ((dm->path_select) & 0x1) ? \"A\" : \"\",\n\t\t\t ((dm->path_select) & 0x2) ? \"B\" : \"\",\n\t\t\t ((dm->path_select) & 0x4) ? \"C\" : \"\",\n\t\t\t ((dm->path_select) & 0x8) ? \"D\" : \"\");\n\n\t\tphydm_dtp_fix_tx_path(dm, dm->path_select);\n\t} else {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used, \"%s\\n\",\n\t\t\t \"Auto path\");\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\n#endif /* @#if RTL8814A_SUPPORT */\n\n#if RTL8812A_SUPPORT\nvoid phydm_update_tx_path_8812a(void *dm_void, enum bb_path path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\n\tif (p_div->default_tx_path != path) {\n\t\tPHYDM_DBG(dm, DBG_PATH_DIV, \"Need to Update Tx path\\n\");\n\n\t\tif (path == BB_PATH_A) {\n\t\t\t/*Tx by Reg*/\n\t\t\todm_set_bb_reg(dm, R_0x80c, 0xFFF0, 0x111);\n\t\t\t/*Resp Tx by Txinfo*/\n\t\t\todm_set_bb_reg(dm, R_0x6d8, 0xc0, 1);\n\t\t} else {\n\t\t\t/*Tx by Reg*/\n\t\t\todm_set_bb_reg(dm, R_0x80c, 0xFFF0, 0x222);\n\t\t\t /*Resp Tx by Txinfo*/\n\t\t\todm_set_bb_reg(dm, R_0x6d8, 0xc0, 2);\n\t\t}\n\t}\n\tp_div->default_tx_path = path;\n\n\tPHYDM_DBG(dm, DBG_PATH_DIV, \"path=%s\\n\",\n\t\t  (path == BB_PATH_A) ? \"A\" : \"B\");\n}\n\nvoid phydm_path_diversity_init_8812a(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\tu32 i;\n\n\todm_set_bb_reg(dm, R_0x80c, BIT(29), 1); /* Tx path from Reg */\n\todm_set_bb_reg(dm, R_0x80c, 0xFFF0, 0x111); /* Tx by Reg */\n\todm_set_bb_reg(dm, R_0x6d8, BIT(7) | BIT6, 1); /* Resp Tx by Txinfo */\n\tphydm_set_tx_path_by_bb_reg(dm, RF_PATH_A);\n\n\tfor (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)\n\t\tp_div->path_sel[i] = 1; /* TxInfo default at path-A */\n}\n#endif\n\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\nvoid phydm_set_resp_tx_path_by_fw_jgr3(void *dm_void, u8 macid,\n\t\t\t\t       enum bb_path path, boolean enable)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\tu8 h2c_para[7] = {0};\n\tu8 path_map[4] = {0}; /* tx logic map*/\n\tu8 num_enable_path = 0;\n\tu8 n_tx_path_ctrl_map = 0;\n\tu8 i = 0, n_sts = 0;\n\n\t/*Response TX is controlled in FW ctrl info*/\n\n\tPHYDM_DBG(dm, DBG_PATH_DIV, \"[%s] =====>\\n\", __func__);\n\n\tif (enable) {\n\t\tn_tx_path_ctrl_map = path;\n\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\tpath_map[i] = 0;\n\t\t\tif (path & BIT(i))\n\t\t\t\tnum_enable_path++;\n\t\t}\n\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\tif (path & BIT(i)) {\n\t\t\t\tpath_map[i] = n_sts;\n\t\t\t\tn_sts++;\n\n\t\t\t\tif (n_sts == num_enable_path)\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tPHYDM_DBG(dm, DBG_PATH_DIV, \"ctrl_map=0x%x Map[D:A]={%d, %d, %d, %d}\\n\",\n\t\t  n_tx_path_ctrl_map,\n\t\t  path_map[3], path_map[2], path_map[1], path_map[0]);\n\n\th2c_para[0] = macid;\n\th2c_para[1] = n_tx_path_ctrl_map;\n\th2c_para[2] = (path_map[3] << 6) | (path_map[2] << 4) |\n\t\t      (path_map[1] << 2) | path_map[0];\n\n\todm_fill_h2c_cmd(dm, PHYDM_H2C_DYNAMIC_TX_PATH, 7, h2c_para);\n}\n\nvoid phydm_get_tx_path_txdesc_jgr3(void *dm_void, u8 macid,\n\t\t\t\t   struct path_txdesc_ctrl *desc)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\tu8 ant_map_a = 0, ant_map_b = 0;\n\tu8 ntx_map = 0;\n\n\tif (p_div->path_sel[macid] == BB_PATH_A) {\n\t\tdesc->ant_map_a = 0; /*offest24[23:22]*/\n\t\tdesc->ant_map_b = 0; /*offest24[25:24]*/\n\t\tdesc->ntx_map = BB_PATH_A; /*offest28[23:20]*/\n\t} else if (p_div->path_sel[macid] == BB_PATH_B) {\n\t\tdesc->ant_map_a = 0; /*offest24[23:22]*/\n\t\tdesc->ant_map_b = 0; /*offest24[25:24]*/\n\t\tdesc->ntx_map = BB_PATH_B; /*offest28[23:20]*/\n\t} else {\n\t\tdesc->ant_map_a = 0; /*offest24[23:22]*/\n\t\tdesc->ant_map_b = 1; /*offest24[25:24]*/\n\t\tdesc->ntx_map = BB_PATH_AB; /*offest28[23:20]*/\n\t}\n}\n#endif\n\nvoid phydm_tx_path_by_mac_or_reg(void *dm_void, enum phydm_path_ctrl ctrl)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\n\tPHYDM_DBG(dm, DBG_PATH_DIV, \"[%s] ctrl=%s\\n\",\n\t\t  __func__, (ctrl == TX_PATH_BY_REG) ? \"REG\" : \"DESC\");\n\n\tif (ctrl == p_div->tx_path_ctrl)\n\t\treturn;\n\n\tp_div->tx_path_ctrl = ctrl;\n\n\tswitch (dm->support_ic_type) {\n\t#if (RTL8822C_SUPPORT)\n\tcase ODM_RTL8822C:\n\t\tif (ctrl == TX_PATH_BY_REG) {\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(16), 0); /*OFDM*/\n\t\t\todm_set_bb_reg(dm, R_0x1a84, 0xe0, 0); /*CCK*/\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(16), 1); /*OFDM*/\n\t\t\todm_set_bb_reg(dm, R_0x1a84, 0xe0, 7); /*CCK*/\n\t\t}\n\n\t\tbreak;\n\t#endif\n\t#if 0 /*(RTL8822B_SUPPORT)*/ /*@ HW Bug*/\n\tcase ODM_RTL8822B:\n\t\tif (ctrl == TX_PATH_BY_REG) {\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(18), 0);\n\t\t\todm_set_bb_reg(dm, R_0xa84, 0xe0, 0); /*CCK*/\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0x93c, BIT(18), 1);\n\t\t\todm_set_bb_reg(dm, R_0xa84, 0xe0, 7); /*CCK*/\n\t\t}\n\n\t\tbreak;\n\t#endif\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid phydm_fix_1ss_tx_path_by_bb_reg(void *dm_void,\n\t\t\t\t     enum bb_path tx_path_sel_1ss,\n\t\t\t\t     enum bb_path tx_path_sel_cck)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\n\tif (tx_path_sel_1ss != BB_PATH_AUTO) {\n\t\tp_div->ofdm_fix_path_en = true;\n\t\tp_div->ofdm_fix_path_sel = tx_path_sel_1ss;\n\t} else {\n\t\tp_div->ofdm_fix_path_en = false;\n\t\tp_div->ofdm_fix_path_sel = dm->tx_1ss_status;\n\t}\n\n\tif (tx_path_sel_cck != BB_PATH_AUTO) {\n\t\tp_div->cck_fix_path_en = true;\n\t\tp_div->cck_fix_path_sel = tx_path_sel_cck;\n\t} else {\n\t\tp_div->cck_fix_path_en = false;\n\t\tp_div->cck_fix_path_sel = dm->tx_1ss_status;\n\t}\n\n\tp_div->force_update = true;\n\n\tPHYDM_DBG(dm, DBG_PATH_DIV,\n\t\t  \"{OFDM_fix_en=%d, path=%d} {CCK_fix_en=%d, path=%d}\\n\",\n\t\t  p_div->ofdm_fix_path_en, p_div->ofdm_fix_path_sel,\n\t\t  p_div->cck_fix_path_en, p_div->cck_fix_path_sel);\n}\n\nvoid phydm_set_tx_path_by_bb_reg(void *dm_void, enum bb_path tx_path_sel_1ss)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\tenum bb_path tx_path_sel_cck = tx_path_sel_1ss;\n\n\tif (!p_div->force_update) {\n\t\tif (tx_path_sel_1ss == p_div->default_tx_path) {\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV, \"Stay in TX path=%s\\n\",\n\t\t\t\t  (tx_path_sel_1ss == BB_PATH_A) ? \"A\" : \"B\");\n\t\t\treturn;\n\t\t}\n\t}\n\tp_div->force_update = false;\n\n\tp_div->default_tx_path = tx_path_sel_1ss;\n\n\tPHYDM_DBG(dm, DBG_PATH_DIV, \"Switch TX path=%s\\n\",\n\t\t  (tx_path_sel_1ss == BB_PATH_A) ? \"A\" : \"B\");\n\n\t/*Adv-ctrl mode*/\n\tif (p_div->cck_fix_path_en) {\n\t\tPHYDM_DBG(dm, DBG_PATH_DIV, \"Fix CCK TX path=%d\\n\",\n\t\t\t  p_div->cck_fix_path_sel);\n\t\ttx_path_sel_cck = p_div->cck_fix_path_sel;\n\t}\n\n\tif (p_div->ofdm_fix_path_en) {\n\t\tPHYDM_DBG(dm, DBG_PATH_DIV, \"Fix OFDM TX path=%d\\n\",\n\t\t\t  p_div->ofdm_fix_path_sel);\n\t\ttx_path_sel_1ss = p_div->ofdm_fix_path_sel;\n\t}\n\n\tswitch (dm->support_ic_type) {\n\t#if RTL8822C_SUPPORT\n\tcase ODM_RTL8822C:\n\t\tphydm_config_tx_path_8822c(dm, dm->tx_2ss_status,\n\t\t\t\t\t   tx_path_sel_1ss, tx_path_sel_cck);\n\t\tbreak;\n\t#endif\n\n\t#if 0 /*RTL8822B_SUPPORT*/\n\tcase ODM_RTL8822B:\n\t\tif (dm->tx_ant_status != BB_PATH_AB)\n\t\t\treturn;\n\n\t\tphydm_config_tx_path_8822b(dm, BB_PATH_AB,\n\t\t\t\t\t   tx_path_sel_1ss, tx_path_sel_cck);\n\t\tbreak;\n\t#endif\n\n\t#if RTL8812A_SUPPORT\n\tcase ODM_RTL8812:\n\t\tphydm_update_tx_path_8812a(dm, tx_path_sel_1ss);\n\t\tbreak;\n\t#endif\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid phydm_tx_path_diversity_2ss(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\tstruct cmn_sta_info *sta;\n\tenum bb_path default_tx_path = BB_PATH_A, path = BB_PATH_A;\n\tu32 rssi_a = 0, rssi_b = 0;\n\tu32 local_max_rssi, glb_min_rssi = 0xff;\n\tu8 i = 0;\n\n\tPHYDM_DBG(dm, DBG_PATH_DIV, \"[%s] =======>\\n\", __func__);\n\n\tif (!dm->is_linked) {\n\t\tif (dm->first_disconnect)\n\t\t\tphydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_REG);\n\n\t\tPHYDM_DBG(dm, DBG_PATH_DIV, \"No Link\\n\");\n\t\treturn;\n\t}\n\n\t#if 0/*def PHYDM_IC_JGR3_SERIES_SUPPORT*/\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tif (dm->is_one_entry_only || p_div->cck_fix_path_en ||\n\t\t    p_div->ofdm_fix_path_en)\n\t\t\tphydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_REG);\n\t\telse\n\t\t\tphydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_DESC);\n\t}\n\t#endif\n\n\tfor (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {\n\t\tsta = dm->phydm_sta_info[i];\n\t\tif (!is_sta_active(sta))\n\t\t\tcontinue;\n\n\t\t/* 2 Caculate RSSI per path */\n\t\trssi_a = PHYDM_DIV(p_div->path_a_sum[i], p_div->path_a_cnt[i]);\n\t\trssi_b = PHYDM_DIV(p_div->path_b_sum[i], p_div->path_b_cnt[i]);\n\n\t\tif (rssi_a == rssi_b)\n\t\t\tpath =  p_div->default_tx_path;\n\t\telse\n\t\t\tpath = (rssi_a > rssi_b) ? BB_PATH_A : BB_PATH_B;\n\n\t\tlocal_max_rssi = (rssi_a > rssi_b) ? rssi_a : rssi_b;\n\n\t\tPHYDM_DBG(dm, DBG_PATH_DIV,\n\t\t\t  \"[%d]PathA sum=%d, cnt=%d, avg_rssi=%d\\n\",\n\t\t\t  i, p_div->path_a_sum[i],\n\t\t\t  p_div->path_a_cnt[i], rssi_a);\n\t\tPHYDM_DBG(dm, DBG_PATH_DIV,\n\t\t\t  \"[%d]PathB sum=%d, cnt=%d, avg_rssi=%d\\n\",\n\t\t\t  i, p_div->path_b_sum[i],\n\t\t\t  p_div->path_b_cnt[i], rssi_b);\n\n\t\t/*Select default Tx path */\n\t\tif (local_max_rssi < glb_min_rssi) {\n\t\t\tglb_min_rssi = local_max_rssi;\n\t\t\tdefault_tx_path = path;\n\t\t}\n\n\t\tif (p_div->path_sel[i] != path) {\n\t\t\tp_div->path_sel[i] = path;\n\t\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\t\t\tphydm_set_resp_tx_path_by_fw_jgr3(dm, i,\n\t\t\t\t\t\t\t\t  path, true);\n\t\t\t#endif\n\t\t}\n\n\t\tp_div->path_a_cnt[i] = 0;\n\t\tp_div->path_a_sum[i] = 0;\n\t\tp_div->path_b_cnt[i] = 0;\n\t\tp_div->path_b_sum[i] = 0;\n\t}\n\n\t/* 2 Update default Tx path */\n\tphydm_set_tx_path_by_bb_reg(dm, default_tx_path);\n\tPHYDM_DBG(dm, DBG_PATH_DIV, \"[%s] end\\n\\n\", __func__);\n}\n\nvoid phydm_tx_path_diversity(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\n\tp_div->path_div_in_progress = false;\n\n\tif (!(dm->support_ability & ODM_BB_PATH_DIV))\n\t\treturn;\n\n\tif (p_div->stop_path_div) {\n\t\tPHYDM_DBG(dm, DBG_PATH_DIV,\n\t\t\t  \"stop_path_div=1, tx_1ss_status=%d\\n\",\n\t\t\t  dm->tx_1ss_status);\n\t\treturn;\n\t}\n\n\tswitch (dm->support_ic_type) {\n\t#if (RTL8822C_SUPPORT || RTL8822B_SUPPORT || RTL8812A_SUPPORT)\n\tcase ODM_RTL8812:\n\tcase ODM_RTL8822B:\n\tcase ODM_RTL8822C:\n\t\tif (dm->rx_ant_status != BB_PATH_AB) {\n\t\t\tPHYDM_DBG(dm, DBG_PATH_DIV,\n\t\t\t\t  \"[Return] tx_Path_en=%d, rx_Path_en=%d\\n\",\n\t\t\t\t  dm->tx_ant_status, dm->rx_ant_status);\n\t\t\treturn;\n\t\t}\n\n\t\tp_div->path_div_in_progress = true;\n\t\tphydm_tx_path_diversity_2ss(dm);\n\t\tbreak;\n\t#endif\n\n\t#if RTL8814A_SUPPORT\n\tcase ODM_RTL8814A:\n\t\tphydm_dynamic_tx_path(dm);\n\t\tbreak;\n\t#endif\n\t}\n}\n\nvoid phydm_tx_path_diversity_init_v2(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\tu32 i = 0;\n\n\tPHYDM_DBG(dm, DBG_PATH_DIV, \"[%s] ====>\\n\", __func__);\n\n\t/*BB_PATH_AB is a invalid value used for init state*/\n\tp_div->default_tx_path = BB_PATH_A;\n\tp_div->tx_path_ctrl = TX_PATH_CTRL_INIT;\n\tp_div->path_div_in_progress = false;\n\n\tp_div->cck_fix_path_en = false;\n\tp_div->ofdm_fix_path_en = false;\n\tp_div->force_update = false;\n\n\tfor (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)\n\t\tp_div->path_sel[i] = BB_PATH_A; /* TxInfo default at path-A */\n\n\tphydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_REG);\n}\n\nvoid phydm_tx_path_diversity_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (!(dm->support_ability & ODM_BB_PATH_DIV))\n\t\treturn;\n\n\tswitch (dm->support_ic_type) {\n\t#if (RTL8822C_SUPPORT || RTL8822B_SUPPORT)\n\tcase ODM_RTL8822C:\n\tcase ODM_RTL8822B:\n\tphydm_tx_path_diversity_init_v2(dm); /*@ After 8822B*/\n\tbreak;\n\t#endif\n\n\t#if RTL8812A_SUPPORT\n\tcase ODM_RTL8812:\n\tphydm_path_diversity_init_8812a(dm);\n\tbreak;\n\t#endif\n\n\t#if RTL8814A_SUPPORT\n\tcase ODM_RTL8814A:\n\tphydm_dynamic_tx_path_init(dm);\n\tbreak;\n\t#endif\n\t}\n}\n\nvoid phydm_process_rssi_for_path_div(void *dm_void, void *phy_info_void,\n\t\t\t\t     void *pkt_info_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_phyinfo_struct *phy_info = NULL;\n\tstruct phydm_perpkt_info_struct *pktinfo = NULL;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\tu8 id = 0;\n\n\tphy_info = (struct phydm_phyinfo_struct *)phy_info_void;\n\tpktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;\n\n\tif (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid))\n\t\treturn;\n\n\tif (pktinfo->is_cck_rate)\n\t\treturn;\n\n\tid = pktinfo->station_id;\n\tp_div->path_a_sum[id] += phy_info->rx_mimo_signal_strength[0];\n\tp_div->path_a_cnt[id]++;\n\n\tp_div->path_b_sum[id] += phy_info->rx_mimo_signal_strength[1];\n\tp_div->path_b_cnt[id]++;\n}\n\nvoid phydm_pathdiv_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t\t char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\tchar help[] = \"-h\";\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 val[10] = {0};\n\tu8 i, input_idx = 0;\n\n\tfor (i = 0; i < 5; i++) {\n\t\tif (input[i + 1]) {\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);\n\t\t\tinput_idx++;\n\t\t}\n\t}\n\n\tif (input_idx == 0)\n\t\treturn;\n\n\tPHYDM_SSCANF(input[1], DCMD_HEX, &val[0]);\n\tPHYDM_SSCANF(input[2], DCMD_HEX, &val[1]);\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{1:TX Ctrl Sig} {0:BB, 1:MAC}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{2:BB Default TX REG} {path}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{3:MAC DESC TX} {path} {macid}\\n\");\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{4:MAC Resp TX} {path} {macid}\\n\");\n\t\t#endif\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{5:Fix 1ss path} {ofdm path} {cck path}\\n\");\n\t} else if (val[0] == 1) {\n\t\tphydm_tx_path_by_mac_or_reg(dm, (enum phydm_path_ctrl)val[1]);\n\t} else if (val[0] == 2) {\n\t\tphydm_set_tx_path_by_bb_reg(dm, (enum bb_path)val[1]);\n\t} else if (val[0] == 3) {\n\t\tp_div->path_sel[val[2]] = (enum bb_path)val[1];\n\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t} else if (val[0] == 4) {\n\t\tphydm_set_resp_tx_path_by_fw_jgr3(dm, (u8)val[2],\n\t\t\t\t\t\t  (enum bb_path)val[1], true);\n\t#endif\n\t} else if (val[0] == 5) {\n\t\tphydm_fix_1ss_tx_path_by_bb_reg(dm, (enum bb_path)val[1],\n\t\t\t\t\t\t(enum bb_path)val[2]);\n\t}\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_c2h_dtp_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n\n\tu8 macid = cmd_buf[0];\n\tu8 target = cmd_buf[1];\n\tu8 nsc_1 = cmd_buf[2];\n\tu8 nsc_2 = cmd_buf[3];\n\tu8 nsc_3 = cmd_buf[4];\n\n\tPHYDM_DBG(dm, DBG_PATH_DIV, \"Target_candidate = (( %d ))\\n\", target);\n/*@\n\tif( (nsc_1 >= nsc_2) &&  (nsc_1 >= nsc_3))\n\t{\n\t\tphydm_dtp_fix_tx_path(dm, p_div->ant_candidate_1);\n\t}\n\telse\tif( nsc_2 >= nsc_3)\n\t{\n\t\tphydm_dtp_fix_tx_path(dm, p_div->ant_candidate_2);\n\t}\n\telse\n\t{\n\t\tphydm_dtp_fix_tx_path(dm, p_div->ant_candidate_3);\n\t}\n\t*/\n}\n\n#endif /*  @#ifdef CONFIG_PATH_DIVERSITY */\n"
  },
  {
    "path": "hal/phydm/phydm_pathdiv.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDMPATHDIV_H__\n#define __PHYDMPATHDIV_H__\n\n#ifdef CONFIG_PATH_DIVERSITY\n#define PATHDIV_VERSION \"4.1\" /* @ modify the condition of by reg*/\n\n#define USE_PATH_A_AS_DEFAULT_ANT /* @for 8814 dynamic TX path selection */\n\n#define NUM_RESET_DTP_PERIOD 5\n#define ANT_DECT_RSSI_TH 3\n\n#define PATH_A 1\n#define PATH_B 2\n#define PATH_C 3\n#define PATH_D 4\n\n#define PHYDM_AUTO_PATH 0\n#define PHYDM_FIX_PATH 1\n\n#define NUM_CHOOSE2_FROM4 6\n#define NUM_CHOOSE3_FROM4 4\n\nenum phydm_dtp_state {\n\tPHYDM_DTP_INIT = 1,\n\tPHYDM_DTP_RUNNING_1\n};\n\nenum phydm_path_div_type {\n\tPHYDM_2R_PATH_DIV = 1,\n\tPHYDM_4R_PATH_DIV = 2\n};\n\nenum phydm_path_ctrl {\n\tTX_PATH_BY_REG = 0,\n\tTX_PATH_BY_DESC = 1,\n\tTX_PATH_CTRL_INIT\n};\n\nstruct path_txdesc_ctrl {\n\tu8 ant_map_a : 2;\n\tu8 ant_map_b : 2;\n\tu8 ntx_map : 4;\n};\n\nstruct _ODM_PATH_DIVERSITY_ {\n\tboolean stop_path_div; /*@Limit by enabled path number*/\n\tboolean path_div_in_progress;\n\tboolean\tcck_fix_path_en; /*@ BB Reg for Adv-Ctrl (or debug mode)*/\n\tboolean\tofdm_fix_path_en; /*@ BB Reg for Adv-Ctrl (or debug mode)*/\n\tenum bb_path cck_fix_path_sel; /*@ BB Reg for Adv-Ctrl (or debug mode)*/\n\tenum bb_path ofdm_fix_path_sel;/*@ BB Reg for Adv-Ctrl (or debug mode)*/\n\tenum phydm_path_ctrl tx_path_ctrl;\n\tenum bb_path default_tx_path;\n\tenum bb_path path_sel[ODM_ASSOCIATE_ENTRY_NUM];\n\tu32\tpath_a_sum[ODM_ASSOCIATE_ENTRY_NUM];\n\tu32\tpath_b_sum[ODM_ASSOCIATE_ENTRY_NUM];\n\tu16\tpath_a_cnt[ODM_ASSOCIATE_ENTRY_NUM];\n\tu16\tpath_b_cnt[ODM_ASSOCIATE_ENTRY_NUM];\n\tu8\tphydm_path_div_type;\n\tboolean force_update;\n#if RTL8814A_SUPPORT\n\n\tu32\tpath_a_sum_all;\n\tu32\tpath_b_sum_all;\n\tu32\tpath_c_sum_all;\n\tu32\tpath_d_sum_all;\n\n\tu32\tpath_a_cnt_all;\n\tu32\tpath_b_cnt_all;\n\tu32\tpath_c_cnt_all;\n\tu32\tpath_d_cnt_all;\n\n\tu8\tdtp_period;\n\tboolean\tis_become_linked;\n\tboolean\tis_u3_mode;\n\tu8\tnum_tx_path;\n\tu8\tdefault_path;\n\tu8\tnum_candidate;\n\tu8\tant_candidate_1;\n\tu8\tant_candidate_2;\n\tu8\tant_candidate_3;\n\tu8     phydm_dtp_state;\n\tu8\tdtp_check_patha_counter;\n\tboolean\tfix_path_bfer;\n\tu8\tsearch_space_2[NUM_CHOOSE2_FROM4];\n\tu8\tsearch_space_3[NUM_CHOOSE3_FROM4];\n\n\tu8\tpre_tx_path;\n\tu8\tuse_path_a_as_default_ant;\n\tboolean\tis_path_a_exist;\n\n#endif\n};\n\nvoid phydm_set_tx_path_by_bb_reg(void *dm_void, enum bb_path tx_path_sel_1ss);\n\nvoid phydm_get_tx_path_txdesc_jgr3(void *dm_void, u8 macid,\n\t\t\t\t   struct path_txdesc_ctrl *desc);\n\nvoid phydm_c2h_dtp_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);\n\nvoid phydm_tx_path_diversity_init(void *dm_void);\n\nvoid phydm_tx_path_diversity(void *dm_void);\n\nvoid phydm_process_rssi_for_path_div(void *dm_void, void *phy_info_void,\n\t\t\t\t     void *pkt_info_void);\n\nvoid phydm_pathdiv_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t\t char *output, u32 *_out_len);\n\n#endif /* @#ifdef CONFIG_PATH_DIVERSITY */\n#endif /* @#ifndef  __PHYDMPATHDIV_H__ */\n\n"
  },
  {
    "path": "hal/phydm/phydm_phystatus.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n ************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#ifdef PHYDM_COMPILE_MU\nu8 phydm_get_gid(struct dm_struct *dm, u8 *phy_status_inf)\n{\n#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)\n\tstruct phy_sts_rpt_jgr2_type1 *rpt_jgr2 = NULL;\n#endif\n#ifdef PHYSTS_3RD_TYPE_SUPPORT\n\tstruct phy_sts_rpt_jgr3_type1 *rpt_jgr3 = NULL;\n#endif\n\tu8 gid = 0;\n\n\tif (dm->ic_phy_sts_type == PHYDM_PHYSTS_TYPE_1)\n\t\treturn 0;\n\n\tif ((*phy_status_inf & 0xf) != 1)\n\t\treturn 0;\n\n\tswitch (dm->ic_phy_sts_type) {\n\t#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)\n\tcase PHYDM_PHYSTS_TYPE_2:\n\t\trpt_jgr2 = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf;\n\t\tgid = rpt_jgr2->gid;\n\t\tbreak;\n\t#endif\n\t#ifdef PHYSTS_3RD_TYPE_SUPPORT\n\tcase PHYDM_PHYSTS_TYPE_3:\n\t\trpt_jgr3 = (struct phy_sts_rpt_jgr3_type1 *)phy_status_inf;\n\t\tgid = rpt_jgr3->gid;\n\t\tbreak;\n\t#endif\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn gid;\n}\n#endif\n\nvoid phydm_rx_statistic_cal(struct dm_struct *dm,\n\t\t\t    struct phydm_phyinfo_struct *phy_info,\n\t\t\t    u8 *phy_status_inf,\n\t\t\t    struct phydm_perpkt_info_struct *pktinfo)\n{\n\tstruct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;\n\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\tstruct phydm_bf_rate_info_jgr3 *bfrateinfo = &dm->bf_rate_info_jgr3;\n#endif\n\n\tu8 rate = (pktinfo->data_rate & 0x7f);\n\tu8 bw_idx = phy_info->band_width;\n\tu8 offset = 0;\n\tu8 gid = 0;\n#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT))\n\tu8 val = 0;\n#endif\n\t#ifdef PHYDM_COMPILE_MU\n\tu8 is_mu_pkt = 0;\n\t#endif\n\n\tif (rate <= ODM_RATE54M) {\n\t\tdbg_i->num_qry_legacy_pkt[rate]++;\n\t} else if (rate <= ODM_RATEMCS31) {\n\t\tdbg_i->ht_pkt_not_zero = true;\n\t\toffset = rate - ODM_RATEMCS0;\n\n\t\tif (offset > (HT_RATE_NUM - 1))\n\t\t\toffset = HT_RATE_NUM - 1;\n\n\t\tif (dm->support_ic_type &\n\t\t    (PHYSTS_2ND_TYPE_IC | PHYSTS_3RD_TYPE_IC)) {\n\t\t\tif (bw_idx == *dm->band_width) {\n\t\t\t\tdbg_i->num_qry_ht_pkt[offset]++;\n\n\t\t\t} else if (bw_idx == CHANNEL_WIDTH_20) {\n\t\t\t\tdbg_i->num_qry_pkt_sc_20m[offset]++;\n\t\t\t\tdbg_i->low_bw_20_occur = true;\n\t\t\t}\n\t\t} else {\n\t\t\tdbg_i->num_qry_ht_pkt[offset]++;\n\t\t}\n\t}\n#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT))\n\telse if (rate <= ODM_RATEVHTSS4MCS9) {\n\t\toffset = rate - ODM_RATEVHTSS1MCS0;\n\n\t\tif (offset > (VHT_RATE_NUM - 1))\n\t\t\toffset = VHT_RATE_NUM - 1;\n\n\t\t#ifdef PHYDM_COMPILE_MU\n\t\tgid = phydm_get_gid(dm, phy_status_inf);\n\n\t\tif (gid != 0 && gid != 63)\n\t\t\tis_mu_pkt = true;\n\n\t\tif (is_mu_pkt) {\n\t\t#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT ||\\\n\t\t     (defined(PHYSTS_3RD_TYPE_SUPPORT)))\n\t\t\tdbg_i->num_mu_vht_pkt[offset]++;\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\t\tbfrateinfo->num_mu_vht_pkt[offset]++;\n\t\t#endif\n\t\t#else\n\t\t\tdbg_i->num_qry_vht_pkt[offset]++; /*@for debug*/\n\t\t#endif\n\t\t} else\n\t\t#endif\n\t\t{\n\t\t\tdbg_i->vht_pkt_not_zero = true;\n\n\t\t\tif (dm->support_ic_type &\n\t\t\t    (PHYSTS_2ND_TYPE_IC | PHYSTS_3RD_TYPE_IC)) {\n\t\t\t\tif (bw_idx == *dm->band_width) {\n\t\t\t\t\tdbg_i->num_qry_vht_pkt[offset]++;\n\t\t\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\t\t\t\tbfrateinfo->num_qry_vht_pkt[offset]++;\n\t\t\t\t#endif\n\n\t\t\t\t} else if (bw_idx == CHANNEL_WIDTH_20) {\n\t\t\t\t\tdbg_i->num_qry_pkt_sc_20m[offset]++;\n\t\t\t\t\tdbg_i->low_bw_20_occur = true;\n\t\t\t\t} else {/*@if (bw_idx == CHANNEL_WIDTH_40)*/\n\t\t\t\t\tdbg_i->num_qry_pkt_sc_40m[offset]++;\n\t\t\t\t\tdbg_i->low_bw_40_occur = true;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tdbg_i->num_qry_vht_pkt[offset]++;\n\t\t\t}\n\t\t}\n\n\t\t#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT ||\\\n\t\t     (defined(PHYSTS_3RD_TYPE_SUPPORT)))\n\t\tif (pktinfo->ppdu_cnt < 4) {\n\t\t\tval = rate;\n\n\t\t\t#ifdef PHYDM_COMPILE_MU\n\t\t\tif (is_mu_pkt)\n\t\t\t\tval |= BIT(7);\n\t\t\t#endif\n\n\t\t\tdbg_i->num_of_ppdu[pktinfo->ppdu_cnt] = val;\n\t\t\tdbg_i->gid_num[pktinfo->ppdu_cnt] = gid;\n\t\t}\n\t\t#endif\n\t}\n#endif\n}\n\nvoid phydm_reset_phystatus_avg(struct dm_struct *dm)\n{\n\tstruct phydm_phystatus_avg *dbg_avg = NULL;\n\n\tdbg_avg = &dm->phy_dbg_info.phystatus_statistic_avg;\n\todm_memory_set(dm, &dbg_avg->rssi_cck_avg, 0,\n\t\t       sizeof(struct phydm_phystatus_avg));\n}\n\nvoid phydm_reset_phystatus_statistic(struct dm_struct *dm)\n{\n\tstruct phydm_phystatus_statistic *dbg_s = NULL;\n\n\tdbg_s = &dm->phy_dbg_info.physts_statistic_info;\n\n\todm_memory_set(dm, &dbg_s->rssi_cck_sum, 0,\n\t\t       sizeof(struct phydm_phystatus_statistic));\n}\n\nvoid phydm_avg_phystatus_index(void *dm_void,\n\t\t\t       struct phydm_phyinfo_struct *phy_info,\n\t\t\t       struct phydm_perpkt_info_struct *pktinfo)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;\n\tstruct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;\n\tu8 rssi[PHYSTS_PATH_NUM] = {0};\n\tu8 evm[PHYSTS_PATH_NUM] = {0};\n\ts8 snr[PHYSTS_PATH_NUM] = {0};\n\tu32 size = PHYSTS_PATH_NUM; /*size of path=4*/\n\tu16 size_th = PHY_HIST_SIZE - 1; /*size of threshold*/\n\tu16 val = 0, intvl = 0;\n\tu8 i = 0;\n\n\todm_move_memory(dm, rssi, phy_info->rx_mimo_signal_strength, size);\n\todm_move_memory(dm, evm, phy_info->rx_mimo_evm_dbm, size);\n\todm_move_memory(dm, snr, phy_info->rx_snr, size);\n\n\tif (pktinfo->is_packet_beacon) {\n\t\tdbg_s->rssi_beacon_sum += rssi[0];\n\t\tdbg_s->rssi_beacon_cnt++;\n\t}\n\n\tif (pktinfo->data_rate <= ODM_RATE11M) {\n\t\t/*RSSI*/\n\t\tdbg_s->rssi_cck_sum += rssi[0];\n\t\tdbg_s->rssi_cck_cnt++;\n\t} else if (pktinfo->data_rate <= ODM_RATE54M) {\n\t\tfor (i = 0; i < dm->num_rf_path; i++) {\n\t\t\t/*SNR & RSSI*/\n\t\t\tdbg_s->snr_ofdm_sum[i] += snr[i];\n\t\t\tdbg_s->rssi_ofdm_sum[i] += rssi[i];\n\t\t}\n\t\t/*@evm*/\n\t\tdbg_s->evm_ofdm_sum += evm[0];\n\t\tdbg_s->rssi_ofdm_cnt++;\n\n\t\tval = (u16)evm[0];\n\t\tintvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, size_th);\n\t\tdbg_s->evm_ofdm_hist[intvl]++;\n\n\t\tval = (u16)snr[0];\n\t\tintvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, size_th);\n\t\tdbg_s->snr_ofdm_hist[intvl]++;\n\n\t} else if (pktinfo->rate_ss == 1) {\n/*@===[1-SS]==================================================================*/\n\t\tfor (i = 0; i < dm->num_rf_path; i++) {\n\t\t\t/*SNR & RSSI*/\n\t\t\tdbg_s->snr_1ss_sum[i] += snr[i];\n\t\t\tdbg_s->rssi_1ss_sum[i] += rssi[i];\n\t\t}\n\n\t\t/*@evm*/\n\t\tdbg_s->evm_1ss_sum += evm[0];\n\t\t/*@EVM Histogram*/\n\t\tval = (u16)evm[0];\n\t\tintvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, size_th);\n\t\tdbg_s->evm_1ss_hist[intvl]++;\n\n\t\t/*SNR Histogram*/\n\t\tval = (u16)snr[0];\n\t\tintvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, size_th);\n\t\tdbg_s->snr_1ss_hist[intvl]++;\n\n\t\tdbg_s->rssi_1ss_cnt++;\n\t} else if (pktinfo->rate_ss == 2) {\n/*@===[2-SS]==================================================================*/\n\t\t#if (defined(PHYDM_COMPILE_ABOVE_2SS))\n\t\tfor (i = 0; i < dm->num_rf_path; i++) {\n\t\t\t/*SNR & RSSI*/\n\t\t\tdbg_s->snr_2ss_sum[i] += snr[i];\n\t\t\tdbg_s->rssi_2ss_sum[i] += rssi[i];\n\t\t}\n\n\t\tfor (i = 0; i < pktinfo->rate_ss; i++) {\n\t\t\t/*@evm*/\n\t\t\tdbg_s->evm_2ss_sum[i] += evm[i];\n\t\t\t/*@EVM Histogram*/\n\t\t\tval = (u16)evm[i];\n\t\t\tintvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,\n\t\t\t\t\t\t  size_th);\n\t\t\tdbg_s->evm_2ss_hist[i][intvl]++;\n\n\t\t\t/*SNR Histogram*/\n\t\t\tval = (u16)snr[i];\n\t\t\tintvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,\n\t\t\t\t\t\t  size_th);\n\t\t\tdbg_s->snr_2ss_hist[i][intvl]++;\n\t\t}\n\t\tdbg_s->rssi_2ss_cnt++;\n\t\t#endif\n\t} else if (pktinfo->rate_ss == 3) {\n/*@===[3-SS]==================================================================*/\n\t\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\t\tfor (i = 0; i < dm->num_rf_path; i++) {\n\t\t\t/*SNR & RSSI*/\n\t\t\tdbg_s->snr_3ss_sum[i] += snr[i];\n\t\t\tdbg_s->rssi_3ss_sum[i] += rssi[i];\n\t\t}\n\n\t\tfor (i = 0; i < pktinfo->rate_ss; i++) {\n\t\t\t/*@evm*/\n\t\t\tdbg_s->evm_3ss_sum[i] += evm[i];\n\t\t\t/*@EVM Histogram*/\n\t\t\tval = (u16)evm[i];\n\t\t\tintvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,\n\t\t\t\t\t\t  size_th);\n\t\t\tdbg_s->evm_3ss_hist[i][intvl]++;\n\n\t\t\t/*SNR Histogram*/\n\t\t\tval = (u16)snr[i];\n\t\t\tintvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,\n\t\t\t\t\t\t  size_th);\n\t\t\tdbg_s->snr_3ss_hist[i][intvl]++;\n\t\t}\n\t\tdbg_s->rssi_3ss_cnt++;\n\t\t#endif\n\t} else if (pktinfo->rate_ss == 4) {\n/*@===[4-SS]==================================================================*/\n\t\t#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\t\tfor (i = 0; i < dm->num_rf_path; i++) {\n\t\t\t/*SNR & RSSI*/\n\t\t\tdbg_s->snr_4ss_sum[i] += snr[i];\n\t\t\tdbg_s->rssi_4ss_sum[i] += rssi[i];\n\t\t}\n\n\t\tfor (i = 0; i < pktinfo->rate_ss; i++) {\n\t\t\t/*@evm*/\n\t\t\tdbg_s->evm_4ss_sum[i] += evm[i];\n\n\t\t\t/*@EVM Histogram*/\n\t\t\tval = (u16)evm[i];\n\t\t\tintvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,\n\t\t\t\t\t\t  size_th);\n\t\t\tdbg_s->evm_4ss_hist[i][intvl]++;\n\n\t\t\t/*SNR Histogram*/\n\t\t\tval = (u16)snr[i];\n\t\t\tintvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,\n\t\t\t\t\t\t  size_th);\n\t\t\tdbg_s->snr_4ss_hist[i][intvl]++;\n\t\t}\n\t\tdbg_s->rssi_4ss_cnt++;\n\t\t#endif\n\t}\n}\n\nvoid phydm_avg_phystatus_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;\n\tu16 snr_hist_th[PHY_HIST_SIZE - 1] = {5, 8, 11, 14, 17, 20, 23, 26,\n\t\t\t\t\t      29, 32, 35};\n\tu16 evm_hist_th[PHY_HIST_SIZE - 1] = {5, 8, 11, 14, 17, 20, 23, 26,\n\t\t\t\t\t      29, 32, 35};\n\tu32 size = (PHY_HIST_SIZE - 1) * 2;\n\n\todm_move_memory(dm, dbg_i->snr_hist_th, snr_hist_th, size);\n\todm_move_memory(dm, dbg_i->evm_hist_th, evm_hist_th, size);\n}\n\nu8 phydm_get_signal_quality(struct phydm_phyinfo_struct *phy_info,\n\t\t\t    struct dm_struct *dm,\n\t\t\t    struct phy_status_rpt_8192cd *phy_sts)\n{\n\tu8 sq_rpt;\n\tu8 result = 0;\n\n\tif (phy_info->rx_pwdb_all > 40 && !dm->is_in_hct_test) {\n\t\tresult = 100;\n\t} else {\n\t\tsq_rpt = phy_sts->cck_sig_qual_ofdm_pwdb_all;\n\n\t\tif (sq_rpt > 64)\n\t\t\tresult = 0;\n\t\telse if (sq_rpt < 20)\n\t\t\tresult = 100;\n\t\telse\n\t\t\tresult = ((64 - sq_rpt) * 100) / 44;\n\t}\n\n\treturn result;\n}\n\nu8 phydm_pwr_2_percent(s8 ant_power)\n{\n\tif ((ant_power <= -100) || ant_power >= 20)\n\t\treturn 0;\n\telse if (ant_power >= 0)\n\t\treturn 100;\n\telse\n\t\treturn 100 + ant_power;\n}\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\n#if 0 /*(DM_ODM_SUPPORT_TYPE == ODM_CE)*/\ns32 phydm_signal_scale_mapping_92c_series(struct dm_struct *dm, s32 curr_sig)\n{\n\ts32 ret_sig = 0;\n\n#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)\n\tif (dm->support_interface == ODM_ITRF_PCIE) {\n\t\t/* step 1. Scale mapping. */\n\t\tif (curr_sig >= 61 && curr_sig <= 100)\n\t\t\tret_sig = 90 + ((curr_sig - 60) / 4);\n\t\telse if (curr_sig >= 41 && curr_sig <= 60)\n\t\t\tret_sig = 78 + ((curr_sig - 40) / 2);\n\t\telse if (curr_sig >= 31 && curr_sig <= 40)\n\t\t\tret_sig = 66 + (curr_sig - 30);\n\t\telse if (curr_sig >= 21 && curr_sig <= 30)\n\t\t\tret_sig = 54 + (curr_sig - 20);\n\t\telse if (curr_sig >= 5 && curr_sig <= 20)\n\t\t\tret_sig = 42 + (((curr_sig - 5) * 2) / 3);\n\t\telse if (curr_sig == 4)\n\t\t\tret_sig = 36;\n\t\telse if (curr_sig == 3)\n\t\t\tret_sig = 27;\n\t\telse if (curr_sig == 2)\n\t\t\tret_sig = 18;\n\t\telse if (curr_sig == 1)\n\t\t\tret_sig = 9;\n\t\telse\n\t\t\tret_sig = curr_sig;\n\t}\n#endif\n\n#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))\n\tif (dm->support_interface == ODM_ITRF_USB ||\n\t    dm->support_interface == ODM_ITRF_SDIO) {\n\t\tif (curr_sig >= 51 && curr_sig <= 100)\n\t\t\tret_sig = 100;\n\t\telse if (curr_sig >= 41 && curr_sig <= 50)\n\t\t\tret_sig = 80 + ((curr_sig - 40) * 2);\n\t\telse if (curr_sig >= 31 && curr_sig <= 40)\n\t\t\tret_sig = 66 + (curr_sig - 30);\n\t\telse if (curr_sig >= 21 && curr_sig <= 30)\n\t\t\tret_sig = 54 + (curr_sig - 20);\n\t\telse if (curr_sig >= 10 && curr_sig <= 20)\n\t\t\tret_sig = 42 + (((curr_sig - 10) * 2) / 3);\n\t\telse if (curr_sig >= 5 && curr_sig <= 9)\n\t\t\tret_sig = 22 + (((curr_sig - 5) * 3) / 2);\n\t\telse if (curr_sig >= 1 && curr_sig <= 4)\n\t\t\tret_sig = 6 + (((curr_sig - 1) * 3) / 2);\n\t\telse\n\t\t\tret_sig = curr_sig;\n\t}\n\n#endif\n\treturn ret_sig;\n}\n\ns32 phydm_signal_scale_mapping(struct dm_struct *dm, s32 curr_sig)\n{\n#ifdef CONFIG_SIGNAL_SCALE_MAPPING\n\treturn phydm_signal_scale_mapping_92c_series(dm, curr_sig);\n#else\n\treturn curr_sig;\n#endif\n}\n#endif\n\nvoid phydm_process_signal_strength(struct dm_struct *dm,\n\t\t\t\t   struct phydm_phyinfo_struct *phy_info,\n\t\t\t\t   struct phydm_perpkt_info_struct *pktinfo)\n{\n\tu8 avg_rssi = 0, tmp_rssi = 0, best_rssi = 0, second_rssi = 0;\n\tu8 ss = 0; /*signal strenth after scale mapping*/\n\tu8 pwdb = phy_info->rx_pwdb_all;\n\tu8 i;\n\n\t/*use the best two RSSI only*/\n\tfor (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {\n\t\ttmp_rssi = phy_info->rx_mimo_signal_strength[i];\n\n\t\t/*@Get the best two RSSI*/\n\t\tif (tmp_rssi > best_rssi && tmp_rssi > second_rssi) {\n\t\t\tsecond_rssi = best_rssi;\n\t\t\tbest_rssi = tmp_rssi;\n\t\t} else if (tmp_rssi > second_rssi && tmp_rssi <= best_rssi) {\n\t\t\tsecond_rssi = tmp_rssi;\n\t\t}\n\t}\n\n\tif (best_rssi == 0)\n\t\treturn;\n\n\tif (pktinfo->rate_ss == 1)\n\t\tavg_rssi = best_rssi;\n\telse\n\t\tavg_rssi = (best_rssi + second_rssi) >> 1;\n\n\tif (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) {\n\t#ifdef PHYSTS_3RD_TYPE_SUPPORT\n\t\t/* Update signal strength to UI,\n\t\t * and phy_info->rx_pwdb_all is the maximum RSSI of all path\n\t\t */\n\t\t#if 1 /*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/\n\t\tss = SignalScaleProc(dm->adapter, pwdb, false, false);\n\t\t#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\tss = (u8)phydm_signal_scale_mapping(dm, pwdb);\n\t\t#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)\n\t\tss = (u8)phydm_signal_scale_mapping(dm, pwdb);\n\t\t#endif\n\n\t#endif\n\t} else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) {\n\t#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)\n\t\t/* Update signal strength to UI,\n\t\t * and phy_info->rx_pwdb_all is the maximum RSSI of all path\n\t\t */\n\t\t#if 1 /*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/\n\t\tss = SignalScaleProc(dm->adapter, pwdb, false, false);\n\t\t#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\tss = (u8)phydm_signal_scale_mapping(dm, pwdb);\n\t\t#endif\n\n\t#endif\n\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t#if ODM_IC_11AC_SERIES_SUPPORT\n\t\tif (pktinfo->is_cck_rate)\n\t\t\t#if 1/*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/\n\t\t\tss = SignalScaleProc(dm->adapter, pwdb, 0, 1);\n\t\t\t#else\n\t\t\tss = (u8)phydm_signal_scale_mapping(dm, pwdb);\n\t\t\t#endif\n\t\telse\n\t\t\t#if 1 /*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/\n\t\t\tss = SignalScaleProc(dm->adapter, avg_rssi, 0, 1);\n\t\t\t#else\n\t\t\tss = (u8)phydm_signal_scale_mapping(dm, avg_rssi);\n\t\t\t#endif\n\t#endif\n\t} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t#if ODM_IC_11N_SERIES_SUPPORT\n\t\tif (pktinfo->is_cck_rate)\n\t\t\t#if 1/*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/\n\t\t\tss = SignalScaleProc(dm->adapter, pwdb, 1, 1);\n\t\t\t#else\n\t\t\tss = (u8)phydm_signal_scale_mapping(dm, pwdb);\n\t\t\t#endif\n\t\telse\n\t\t\t#if 1 /*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/\n\t\t\tss = SignalScaleProc(dm->adapter, avg_rssi, 1, 0);\n\t\t\t#else\n\t\t\tss = (u8)phydm_signal_scale_mapping(dm, avg_rssi);\n\t\t\t#endif\n\t#endif\n\t}\n\tphy_info->signal_strength = ss;\n}\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\nstatic u8 phydm_sq_patch_lenovo(\n\tstruct dm_struct *dm,\n\tu8 is_cck_rate,\n\tu8 pwdb_all,\n\tu8 path,\n\tu8 RSSI)\n{\n\tu8 sq = 0;\n\n\tif (is_cck_rate) {\n\t\tif (dm->support_ic_type & ODM_RTL8192E) {\n/*@\n * <Roger_Notes>\n * Expected signal strength and bars indication at Lenovo lab. 2013.04.11\n * 802.11n, 802.11b, 802.11g only at channel 6\n *\n *\tAttenuation (dB)\tOS Signal Bars\tRSSI by Xirrus (dBm)\n *\t\t50\t\t\t\t5\t\t\t-49\n *\t\t55\t\t\t\t5\t\t\t-49\n *\t\t60\t\t\t\t5\t\t\t-50\n *\t\t65\t\t\t\t5\t\t\t-51\n *\t\t70\t\t\t\t5\t\t\t-52\n *\t\t75\t\t\t\t5\t\t\t-54\n *\t\t80\t\t\t\t5\t\t\t-55\n *\t\t85\t\t\t\t4\t\t\t-60\n *\t\t90\t\t\t\t3\t\t\t-63\n *\t\t95\t\t\t\t3\t\t\t-65\n *\t\t100\t\t\t\t2\t\t\t-67\n *\t\t102\t\t\t\t2\t\t\t-67\n *\t\t104\t\t\t\t1\t\t\t-70\n */\n\t\t\tif (pwdb_all >= 50)\n\t\t\t\tsq = 100;\n\t\t\telse if (pwdb_all >= 35 && pwdb_all < 50)\n\t\t\t\tsq = 80;\n\t\t\telse if (pwdb_all >= 31 && pwdb_all < 35)\n\t\t\t\tsq = 60;\n\t\t\telse if (pwdb_all >= 22 && pwdb_all < 31)\n\t\t\t\tsq = 40;\n\t\t\telse if (pwdb_all >= 18 && pwdb_all < 22)\n\t\t\t\tsq = 20;\n\t\t\telse\n\t\t\t\tsq = 10;\n\t\t} else {\n\t\t\tif (pwdb_all >= 50)\n\t\t\t\tsq = 100;\n\t\t\telse if (pwdb_all >= 35 && pwdb_all < 50)\n\t\t\t\tsq = 80;\n\t\t\telse if (pwdb_all >= 22 && pwdb_all < 35)\n\t\t\t\tsq = 60;\n\t\t\telse if (pwdb_all >= 18 && pwdb_all < 22)\n\t\t\t\tsq = 40;\n\t\t\telse\n\t\t\t\tsq = 10;\n\t\t}\n\n\t} else {\n\t\t/* OFDM rate */\n\n\t\tif (dm->support_ic_type & ODM_RTL8192E) {\n\t\t\tif (RSSI >= 45)\n\t\t\t\tsq = 100;\n\t\t\telse if (RSSI >= 22 && RSSI < 45)\n\t\t\t\tsq = 80;\n\t\t\telse if (RSSI >= 18 && RSSI < 22)\n\t\t\t\tsq = 40;\n\t\t\telse\n\t\t\t\tsq = 20;\n\t\t} else {\n\t\t\tif (RSSI >= 45)\n\t\t\t\tsq = 100;\n\t\t\telse if (RSSI >= 22 && RSSI < 45)\n\t\t\t\tsq = 80;\n\t\t\telse if (RSSI >= 18 && RSSI < 22)\n\t\t\t\tsq = 40;\n\t\t\telse\n\t\t\t\tsq = 20;\n\t\t}\n\t}\n\treturn sq;\n}\n\nstatic u8 phydm_sq_patch_rt_cid_819x_acer(\n\tstruct dm_struct *dm,\n\tu8 is_cck_rate,\n\tu8 pwdb_all,\n\tu8 path,\n\tu8 RSSI)\n{\n\tu8 sq = 0;\n\n\tif (is_cck_rate) {\n#if OS_WIN_FROM_WIN8(OS_VERSION)\n\t\tif (pwdb_all >= 50)\n\t\t\tsq = 100;\n\t\telse if (pwdb_all >= 35 && pwdb_all < 50)\n\t\t\tsq = 80;\n\t\telse if (pwdb_all >= 30 && pwdb_all < 35)\n\t\t\tsq = 60;\n\t\telse if (pwdb_all >= 25 && pwdb_all < 30)\n\t\t\tsq = 40;\n\t\telse if (pwdb_all >= 20 && pwdb_all < 25)\n\t\t\tsq = 20;\n\t\telse\n\t\t\tsq = 10;\n#else\n\t\tif (pwdb_all >= 50)\n\t\t\tsq = 100;\n\t\telse if (pwdb_all >= 35 && pwdb_all < 50)\n\t\t\tsq = 80;\n\t\telse if (pwdb_all >= 30 && pwdb_all < 35)\n\t\t\tsq = 60;\n\t\telse if (pwdb_all >= 25 && pwdb_all < 30)\n\t\t\tsq = 40;\n\t\telse if (pwdb_all >= 20 && pwdb_all < 25)\n\t\t\tsq = 20;\n\t\telse\n\t\t\tsq = 10;\n\n\t\t/* @Abnormal case, do not indicate the value above 20 on Win7 */\n\t\tif (pwdb_all == 0)\n\t\t\tsq = 20;\n#endif\n\n\t} else {\n\t\t/* OFDM rate */\n\t\tif (dm->support_ic_type & ODM_RTL8192E) {\n\t\t\tif (RSSI >= 45)\n\t\t\t\tsq = 100;\n\t\t\telse if (RSSI >= 22 && RSSI < 45)\n\t\t\t\tsq = 80;\n\t\t\telse if (RSSI >= 18 && RSSI < 22)\n\t\t\t\tsq = 40;\n\t\t\telse\n\t\t\t\tsq = 20;\n\t\t} else {\n\t\t\tif (RSSI >= 35)\n\t\t\t\tsq = 100;\n\t\t\telse if (RSSI >= 30 && RSSI < 35)\n\t\t\t\tsq = 80;\n\t\t\telse if (RSSI >= 25 && RSSI < 30)\n\t\t\t\tsq = 40;\n\t\t\telse\n\t\t\t\tsq = 20;\n\t\t}\n\t}\n\treturn sq;\n}\n#endif\n\nstatic u8\nphydm_evm_2_percent(s8 value)\n{\n\t/* @-33dB~0dB to 0%~99% */\n\ts8 ret_val;\n\n\tret_val = value;\n\tret_val /= 2;\n\n/*@dbg_print(\"value=%d\\n\", value);*/\n#ifdef ODM_EVM_ENHANCE_ANTDIV\n\tif (ret_val >= 0)\n\t\tret_val = 0;\n\n\tif (ret_val <= -40)\n\t\tret_val = -40;\n\n\tret_val = 0 - ret_val;\n\tret_val *= 3;\n#else\n\tif (ret_val >= 0)\n\t\tret_val = 0;\n\n\tif (ret_val <= -33)\n\t\tret_val = -33;\n\n\tret_val = 0 - ret_val;\n\tret_val *= 3;\n\n\tif (ret_val == 99)\n\t\tret_val = 100;\n#endif\n\n\treturn (u8)ret_val;\n}\n\ns8 phydm_cck_rssi_convert(struct dm_struct *dm, u16 lna_idx, u8 vga_idx)\n{\n\t/*@phydm_get_cck_rssi_table_from_reg*/\n\treturn (dm->cck_lna_gain_table[lna_idx] - (vga_idx << 1));\n}\n\nvoid phydm_get_cck_rssi_table_from_reg(struct dm_struct *dm)\n{\n\tu8 used_lna_idx_tmp;\n\tu32 reg_0xa80 = 0x7431, reg_0xabc = 0xcbe5edfd;\n\tu32 val = 0;\n\tu8 i;\n\n\t/*@example: {-53, -43, -33, -27, -19, -13, -3, 1}*/\n\t/*@{0xCB, 0xD5, 0xDF, 0xE5, 0xED, 0xF3, 0xFD, 0x2}*/\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"CCK LNA Gain table init\\n\");\n\n\tif (!(dm->support_ic_type & ODM_RTL8197F))\n\t\treturn;\n\n\treg_0xa80 = odm_get_bb_reg(dm, R_0xa80, 0xFFFF);\n\treg_0xabc = odm_get_bb_reg(dm, R_0xabc, MASKDWORD);\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"reg_0xa80 = 0x%x\\n\", reg_0xa80);\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"reg_0xabc = 0x%x\\n\", reg_0xabc);\n\n\tfor (i = 0; i <= 3; i++) {\n\t\tused_lna_idx_tmp = (u8)((reg_0xa80 >> (4 * i)) & 0x7);\n\t\tval = (reg_0xabc >> (8 * i)) & 0xff;\n\t\tdm->cck_lna_gain_table[used_lna_idx_tmp] = (s8)val;\n\t}\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t  \"cck_lna_gain_table = {%d,%d,%d,%d,%d,%d,%d,%d}\\n\",\n\t\t  dm->cck_lna_gain_table[0], dm->cck_lna_gain_table[1],\n\t\t  dm->cck_lna_gain_table[2], dm->cck_lna_gain_table[3],\n\t\t  dm->cck_lna_gain_table[4], dm->cck_lna_gain_table[5],\n\t\t  dm->cck_lna_gain_table[6], dm->cck_lna_gain_table[7]);\n}\n\ns8 phydm_get_cck_rssi(void *dm_void, u8 lna_idx, u8 vga_idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\ts8 rx_pow = 0;\n\n\tswitch (dm->support_ic_type) {\n\t#if (RTL8197F_SUPPORT)\n\tcase ODM_RTL8197F:\n\t\trx_pow = phydm_cck_rssi_convert(dm, lna_idx, vga_idx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8723D_SUPPORT)\n\tcase ODM_RTL8723D:\n\t\trx_pow = phydm_cckrssi_8723d(dm, lna_idx, vga_idx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8710B_SUPPORT)\n\tcase ODM_RTL8710B:\n\t\trx_pow = phydm_cckrssi_8710b(dm, lna_idx, vga_idx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8721D_SUPPORT)\n\tcase ODM_RTL8721D:\n\t\trx_pow = phydm_cckrssi_8721d(dm, lna_idx, vga_idx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8192F_SUPPORT)\n\tcase ODM_RTL8192F:\n\t\trx_pow = phydm_cckrssi_8192f(dm, lna_idx, vga_idx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8821C_SUPPORT)\n\tcase ODM_RTL8821C:\n\t\trx_pow = phydm_cck_rssi_8821c(dm, lna_idx, vga_idx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8195B_SUPPORT)\n\tcase ODM_RTL8195B:\n\t\trx_pow = phydm_cck_rssi_8195B(dm, lna_idx, vga_idx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8188E_SUPPORT)\n\tcase ODM_RTL8188E:\n\t\trx_pow = phydm_cck_rssi_8188e(dm, lna_idx, vga_idx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8192E_SUPPORT)\n\tcase ODM_RTL8192E:\n\t\trx_pow = phydm_cck_rssi_8192e(dm, lna_idx, vga_idx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8723B_SUPPORT)\n\tcase ODM_RTL8723B:\n\t\trx_pow = phydm_cck_rssi_8723b(dm, lna_idx, vga_idx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8703B_SUPPORT)\n\tcase ODM_RTL8703B:\n\t\trx_pow = phydm_cck_rssi_8703b(dm, lna_idx, vga_idx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8188F_SUPPORT)\n\tcase ODM_RTL8188F:\n\t\trx_pow = phydm_cck_rssi_8188f(dm, lna_idx, vga_idx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8195A_SUPPORT)\n\tcase ODM_RTL8195A:\n\t\trx_pow = phydm_cck_rssi_8195a(dm, lna_idx, vga_idx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8812A_SUPPORT)\n\tcase ODM_RTL8812:\n\t\trx_pow = phydm_cck_rssi_8812a(dm, lna_idx, vga_idx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8821A_SUPPORT || RTL8881A_SUPPORT)\n\tcase ODM_RTL8821:\n\tcase ODM_RTL8881A:\n\t\trx_pow = phydm_cck_rssi_8821a(dm, lna_idx, vga_idx);\n\t\tbreak;\n\t#endif\n\n\t#if (RTL8814A_SUPPORT)\n\tcase ODM_RTL8814A:\n\t\trx_pow = phydm_cck_rssi_8814a(dm, lna_idx, vga_idx);\n\t\tbreak;\n\t#endif\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn rx_pow;\n}\n\n#if (ODM_IC_11N_SERIES_SUPPORT)\nvoid phydm_phy_sts_n_parsing(struct dm_struct *dm,\n\t\t\t     struct phydm_phyinfo_struct *phy_info,\n\t\t\t     u8 *phy_status_inf,\n\t\t\t     struct phydm_perpkt_info_struct *pktinfo)\n{\n\tu8 i = 0;\n\ts8 rx_pwr[4], rx_pwr_all = 0;\n\tu8 EVM, pwdb_all = 0, pwdb_all_bt = 0;\n\tu8 RSSI, total_rssi = 0;\n\tu8 rf_rx_num = 0;\n\tu8 lna_idx = 0;\n\tu8 vga_idx = 0;\n\tu8 cck_agc_rpt;\n\ts8 evm_tmp = 0;\n\tu8 sq = 0;\n\tu8 val_tmp = 0;\n\ts8 val_s8 = 0;\n\tstruct phy_status_rpt_8192cd *phy_sts = NULL;\n\n\tphy_sts = (struct phy_status_rpt_8192cd *)phy_status_inf;\n\n\tif (pktinfo->is_cck_rate) {\n\t\tcck_agc_rpt = phy_sts->cck_agc_rpt_ofdm_cfosho_a;\n\n\t\t/*@3 bit LNA*/\n\t\tlna_idx = ((cck_agc_rpt & 0xE0) >> 5);\n\t\tvga_idx = (cck_agc_rpt & 0x1F);\n\n\t\t#if (RTL8703B_SUPPORT)\n\t\tif (dm->support_ic_type & (ODM_RTL8703B) &&\n\t\t    dm->cck_agc_report_type == 1) {\n\t\t\t/*@4 bit LNA*/\n\t\t\tif (phy_sts->cck_rpt_b_ofdm_cfosho_b & BIT(7))\n\t\t\t\tval_tmp = 1;\n\t\t\telse\n\t\t\t\tval_tmp = 0;\n\t\t\tlna_idx = (val_tmp << 3) | lna_idx;\n\t\t}\n\t\t#endif\n\n\t\trx_pwr_all = phydm_get_cck_rssi(dm, lna_idx, vga_idx);\n\n\t\tPHYDM_DBG(dm, DBG_RSSI_MNTR,\n\t\t\t  \"ext_lna_gain (( %d )), lna_idx: (( 0x%x )), vga_idx: (( 0x%x )), rx_pwr_all: (( %d ))\\n\",\n\t\t\t  dm->ext_lna_gain, lna_idx, vga_idx, rx_pwr_all);\n\n\t\tif (dm->board_type & ODM_BOARD_EXT_LNA)\n\t\t\trx_pwr_all -= dm->ext_lna_gain;\n\n\t\tpwdb_all = phydm_pwr_2_percent(rx_pwr_all);\n\n\t\tif (pktinfo->is_to_self) {\n\t\t\tdm->cck_lna_idx = lna_idx;\n\t\t\tdm->cck_vga_idx = vga_idx;\n\t\t}\n\n\t\tphy_info->rx_pwdb_all = pwdb_all;\n\t\tphy_info->bt_rx_rssi_percentage = pwdb_all;\n\t\tphy_info->recv_signal_power = rx_pwr_all;\n\n\t\t/* @(3) Get Signal Quality (EVM) */\n\t\t#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t\tif (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO)\n\t\t\tsq = phydm_sq_patch_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0);\n\t\telse if (dm->iot_table.win_patch_id == RT_CID_819X_ACER)\n\t\t\tsq = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0);\n\t\telse\n\t\t#endif\n\t\t\tsq = phydm_get_signal_quality(phy_info, dm, phy_sts);\n\n#if 0\n\t\t/* @dbg_print(\"cck sq = %d\\n\", sq); */\n#endif\n\t\tphy_info->signal_quality = sq;\n\t\tphy_info->rx_mimo_signal_quality[RF_PATH_A] = sq;\n\t\tphy_info->rx_mimo_signal_quality[RF_PATH_B] = -1;\n\n\t\tfor (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {\n\t\t\tif (i == 0)\n\t\t\t\tphy_info->rx_mimo_signal_strength[0] = pwdb_all;\n\t\t\telse\n\t\t\t\tphy_info->rx_mimo_signal_strength[i] = 0;\n\t\t}\n\t} else { /* @2 is OFDM rate */\n\n\t\t/* @(1)Get RSSI for HT rate */\n\n\t\tfor (i = RF_PATH_A; i < dm->num_rf_path; i++) {\n\t\t\tif (dm->rf_path_rx_enable & BIT(i))\n\t\t\t\trf_rx_num++;\n\n\t\t\tval_s8 = phy_sts->path_agc[i].gain & 0x3F;\n\t\t\trx_pwr[i] = (val_s8 * 2) - 110;\n\n\t\t\tif (pktinfo->is_to_self)\n\t\t\t\tdm->ofdm_agc_idx[i] = val_s8;\n\n\t\t\tphy_info->rx_pwr[i] = rx_pwr[i];\n\t\t\tRSSI = phydm_pwr_2_percent(rx_pwr[i]);\n\t\t\ttotal_rssi += RSSI;\n\n\t\t\tphy_info->rx_mimo_signal_strength[i] = (u8)RSSI;\n\n\t\t\t/* @Get Rx snr value in DB */\n\t\t\tval_s8 = (s8)(phy_sts->path_rxsnr[i] / 2);\n\t\t\tphy_info->rx_snr[i] = val_s8;\n\n\t\t\t/* Record Signal Strength for next packet */\n\n\t\t\t#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t\t\tif (i == RF_PATH_A) {\n\t\t\t\tif (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) {\n\t\t\t\t\tphy_info->signal_quality = phydm_sq_patch_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, i, RSSI);\n\t\t\t\t} else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER)\n\t\t\t\t\tphy_info->signal_quality = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, RSSI);\n\t\t\t}\n\t\t\t#endif\n\t\t}\n\n\t\t/* @(2)PWDB, Average PWDB calculated by hardware (for RA) */\n\t\tval_s8 = phy_sts->cck_sig_qual_ofdm_pwdb_all >> 1;\n\t\trx_pwr_all = (val_s8  & 0x7f) - 110;\n\n\t\tpwdb_all = phydm_pwr_2_percent(rx_pwr_all);\n\t\tpwdb_all_bt = pwdb_all;\n\n\t\tphy_info->rx_pwdb_all = pwdb_all;\n\t\tphy_info->bt_rx_rssi_percentage = pwdb_all_bt;\n\t\tphy_info->rx_power = rx_pwr_all;\n\t\tphy_info->recv_signal_power = rx_pwr_all;\n\n\t\t/* @(3)EVM of HT rate */\n\t\tfor (i = 0; i < pktinfo->rate_ss; i++) {\n\t\t/* @Do not use shift operation like \"rx_evmX >>= 1\"\n\t\t * because the compilor of free build environment\n\t\t * fill most significant bit to \"zero\" when doing shifting\n\t\t * operation which may change a negative\n\t\t * value to positive one, then the dbm value\n\t\t * (which is supposed to be negative) is not correct anymore.\n\t\t */\n\t\t\tEVM = phydm_evm_2_percent(phy_sts->stream_rxevm[i]);\n\n\t\t\t/*@Fill value in RFD, Get the 1st spatial stream only*/\n\t\t\tif (i == RF_PATH_A)\n\t\t\t\tphy_info->signal_quality = (u8)(EVM & 0xff);\n\n\t\t\tphy_info->rx_mimo_signal_quality[i] = (u8)(EVM & 0xff);\n\n\t\t\tif (phy_sts->stream_rxevm[i] < 0)\n\t\t\t\tevm_tmp = 0 - phy_sts->stream_rxevm[i];\n\n\t\t\tif (evm_tmp == 64)\n\t\t\t\tevm_tmp = 0;\n\n\t\t\tphy_info->rx_mimo_evm_dbm[i] = (u8)evm_tmp;\n\t\t}\n\t\tphydm_parsing_cfo(dm, pktinfo,\n\t\t\t\t  phy_sts->path_cfotail, pktinfo->rate_ss);\n\t}\n\n\t#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\tdm->dm_fat_table.antsel_rx_keep_0 = phy_sts->ant_sel;\n\tdm->dm_fat_table.antsel_rx_keep_1 = phy_sts->ant_sel_b;\n\tdm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antsel_rx_keep_2;\n\t#endif\n}\n#endif\n\n#if ODM_IC_11AC_SERIES_SUPPORT\nstatic s16\nphydm_cfo(s8 value)\n{\n\ts16 ret_val;\n\n\tif (value < 0) {\n\t\tret_val = 0 - value;\n\t\tret_val = (ret_val << 1) + (ret_val >> 1); /*@2.5~=312.5/2^7 */\n\t\tret_val = ret_val | BIT(12); /*set bit12 as 1 for negative cfo*/\n\t} else {\n\t\tret_val = value;\n\t\tret_val = (ret_val << 1) + (ret_val >> 1); /* @*2.5~=312.5/2^7*/\n\t}\n\treturn ret_val;\n}\n\nstatic u8\nphydm_evm_dbm(s8 value)\n{\n\ts8 ret_val = value;\n\n\t/* @-33dB~0dB to 33dB ~ 0dB */\n\tif (ret_val == -128)\n\t\tret_val = 127;\n\telse if (ret_val < 0)\n\t\tret_val = 0 - ret_val;\n\n\tret_val = ret_val >> 1;\n\treturn (u8)ret_val;\n}\n\nvoid phydm_rx_physts_bw_parsing(struct phydm_phyinfo_struct *phy_info,\n\t\t\t\tstruct phydm_perpkt_info_struct *\n\t\t\t\tpktinfo,\n\t\t\t\tstruct phy_status_rpt_8812 *\n\t\t\t\tphy_sts)\n{\n\tif (pktinfo->data_rate > ODM_RATE54M) {\n\t\tswitch (phy_sts->r_RFMOD) {\n\t\tcase 1:\n\t\t\tif (phy_sts->sub_chnl == 0)\n\t\t\t\tphy_info->band_width = 1;\n\t\t\telse\n\t\t\t\tphy_info->band_width = 0;\n\t\t\tbreak;\n\n\t\tcase 2:\n\t\t\tif (phy_sts->sub_chnl == 0)\n\t\t\t\tphy_info->band_width = 2;\n\t\t\telse if (phy_sts->sub_chnl == 9 ||\n\t\t\t\t phy_sts->sub_chnl == 10)\n\t\t\t\tphy_info->band_width = 1;\n\t\t\telse\n\t\t\t\tphy_info->band_width = 0;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\tcase 0:\n\t\t\tphy_info->band_width = 0;\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\nvoid phydm_get_sq(struct dm_struct *dm, struct phydm_phyinfo_struct *phy_info,\n\t\t  u8 is_cck_rate)\n{\n\tu8 sq = 0;\n\tu8 pwdb_all = phy_info->rx_pwdb_all; /*precentage*/\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tu8 rssi = phy_info->rx_mimo_signal_strength[0];\n\t#endif\n\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tif (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) {\n\t\tif (is_cck_rate)\n\t\t\tsq = phydm_sq_patch_lenovo(dm, 1, pwdb_all, 0, 0);\n\t\telse\n\t\t\tsq = phydm_sq_patch_lenovo(dm, 0, pwdb_all, 0, rssi);\n\t} else\n\t#endif\n\t{\n\t\tif (is_cck_rate) {\n\t\t\tif (pwdb_all > 40 && !dm->is_in_hct_test) {\n\t\t\t\tsq = 100;\n\t\t\t} else {\n\t\t\t\tif (pwdb_all > 64)\n\t\t\t\t\tsq = 0;\n\t\t\t\telse if (pwdb_all < 20)\n\t\t\t\t\tsq = 100;\n\t\t\t\telse\n\t\t\t\t\tsq = ((64 - pwdb_all) * 100) / 44;\n\t\t\t}\n\t\t} else {\n\t\t\tsq = phy_info->rx_mimo_signal_quality[0];\n\t\t}\n\t}\n\n#if 0\n\t/* @dbg_print(\"cck sq = %d\\n\", sq); */\n#endif\n\tphy_info->signal_quality = sq;\n}\n\nvoid phydm_rx_physts_1st_type(struct dm_struct *dm,\n\t\t\t      struct phydm_phyinfo_struct *phy_info,\n\t\t\t      u8 *phy_status_inf,\n\t\t\t      struct phydm_perpkt_info_struct *pktinfo)\n{\n\tu8 i = 0;\n\ts8 rx_pwr_db = 0;\n\tu8 val = 0; /*tmp value*/\n\ts8 val_s8 = 0; /*tmp value*/\n\tu8 rssi = 0; /*pre path RSSI*/\n\tu8 rf_rx_num = 0;\n\tu8 lna_idx = 0, vga_idx = 0;\n\tu8 cck_agc_rpt = 0;\n\tstruct phy_status_rpt_8812 *phy_sts = NULL;\n\t#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\t#endif\n\n\tphy_sts = (struct phy_status_rpt_8812 *)phy_status_inf;\n\tphydm_rx_physts_bw_parsing(phy_info, pktinfo, phy_sts);\n\n\t/* @== [CCK rate] ====================================================*/\n\tif (pktinfo->is_cck_rate) {\n\t\tcck_agc_rpt = phy_sts->cfosho[0];\n\t\tlna_idx = (cck_agc_rpt & 0xE0) >> 5;\n\t\tvga_idx = cck_agc_rpt & 0x1F;\n\n\t\trx_pwr_db = phydm_get_cck_rssi(dm, lna_idx, vga_idx);\n\t\trssi = phydm_pwr_2_percent(rx_pwr_db);\n\n\t\tif (dm->support_ic_type == ODM_RTL8812 &&\n\t\t    !dm->is_cck_high_power) {\n\t\t\tif (rssi >= 80) {\n\t\t\t\trssi = ((rssi - 80) << 1) +\n\t\t\t\t\t   ((rssi - 80) >> 1) + 80;\n\t\t\t} else if ((rssi <= 78) && (rssi >= 20)) {\n\t\t\t\trssi += 3;\n\t\t\t}\n\t\t}\n\t\tdm->cck_lna_idx = lna_idx;\n\t\tdm->cck_vga_idx = vga_idx;\n\n\t\tphy_info->rx_pwdb_all = rssi;\n\t\tphy_info->rx_mimo_signal_strength[0] = rssi;\n\t} else {\n\t/* @== [OFDM rate] ===================================================*/\n\t\tfor (i = RF_PATH_A; i < dm->num_rf_path; i++) {\n\t\t\t/*@[RSSI]*/\n\t\t\tif (dm->rf_path_rx_enable & BIT(i))\n\t\t\t\trf_rx_num++;\n\n\t\t\tif (i < RF_PATH_C)\n\t\t\t\tval = phy_sts->gain_trsw[i];\n\t\t\telse\n\t\t\t\tval = phy_sts->gain_trsw_cd[i - 2];\n\n\t\t\tphy_info->rx_pwr[i] = (val & 0x7F) - 110;\n\t\t\trssi = phydm_pwr_2_percent(phy_info->rx_pwr[i]);\n\t\t\tphy_info->rx_mimo_signal_strength[i] = rssi;\n\n\t\t\t/*@[SNR]*/\n\t\t\tif (i < RF_PATH_C)\n\t\t\t\tval_s8 = phy_sts->rxsnr[i];\n\t\t\telse if (dm->support_ic_type & (ODM_RTL8814A))\n\t\t\t\tval_s8 = (s8)phy_sts->csi_current[i - 2];\n\n\t\t\tphy_info->rx_snr[i] = val_s8 >> 1;\n\n\t\t\t/*@[CFO_short  & CFO_tail]*/\n\t\t\tif (i < RF_PATH_C) {\n\t\t\t\tval_s8 = phy_sts->cfosho[i];\n\t\t\t\tphy_info->cfo_short[i] = phydm_cfo(val_s8);\n\t\t\t\tval_s8 = phy_sts->cfotail[i];\n\t\t\t\tphy_info->cfo_tail[i] = phydm_cfo(val_s8);\n\t\t\t}\n\n\t\t\tif (i < RF_PATH_C && pktinfo->is_to_self)\n\t\t\t\tdm->ofdm_agc_idx[i] = phy_sts->gain_trsw[i];\n\t\t}\n\n\t/* @== [PWDB] ========================================================*/\n\n\t\t/*@(Avg PWDB calculated by hardware*/\n\t\tif (!dm->is_mp_chip) /*@8812, 8821*/\n\t\t\tval = phy_sts->pwdb_all;\n\t\telse\n\t\t\tval = phy_sts->pwdb_all >> 1; /*old fomula*/\n\n\t\trx_pwr_db = (val & 0x7f) - 110;\n\t\tphy_info->rx_pwdb_all = phydm_pwr_2_percent(rx_pwr_db);\n\n\t\t/*@(4)EVM of OFDM rate*/\n\t\tfor (i = 0; i < pktinfo->rate_ss; i++) {\n\t\t\tif (!pktinfo->is_cck_rate &&\n\t\t\t    pktinfo->data_rate <= ODM_RATE54M) {\n\t\t\t\tval_s8 = phy_sts->sigevm;\n\t\t\t} else if (i < RF_PATH_C) {\n\t\t\t\tif (phy_sts->rxevm[i] == -128)\n\t\t\t\t\tphy_sts->rxevm[i] = -25;\n\n\t\t\t\tval_s8 = phy_sts->rxevm[i];\n\t\t\t} else {\n\t\t\t\tif (phy_sts->rxevm_cd[i - 2] == -128)\n\t\t\t\t\tphy_sts->rxevm_cd[i - 2] = -25;\n\n\t\t\t\tval_s8 = phy_sts->rxevm_cd[i - 2];\n\t\t\t}\n\t\t\t/*@[EVM to 0~100%]*/\n\t\t\tval = phydm_evm_2_percent(val_s8);\n\t\t\tphy_info->rx_mimo_signal_quality[i] = val;\n\t\t\t/*@[EVM dBm]*/\n\t\t\tphy_info->rx_mimo_evm_dbm[i] = phydm_evm_dbm(val_s8);\n\t\t}\n\t\tphydm_parsing_cfo(dm, pktinfo,\n\t\t\t\t  phy_sts->cfotail, pktinfo->rate_ss);\n\t}\n\n\t/* @== [General Info] ================================================*/\n\n\tphy_info->rx_power = rx_pwr_db;\n\tphy_info->bt_rx_rssi_percentage = phy_info->rx_pwdb_all;\n\tphy_info->recv_signal_power = phy_info->rx_power;\n\tphydm_get_sq(dm, phy_info, pktinfo->is_cck_rate);\n\n\tdm->rx_pwdb_ave = dm->rx_pwdb_ave + phy_info->rx_pwdb_all;\n\n\t#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\tfat_tab->hw_antsw_occur = phy_sts->hw_antsw_occur;\n\tdm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_anta;\n\tdm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_antb;\n\tdm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_antc;\n\tdm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_antd;\n\t#endif\n}\n\n#endif\n\nvoid phydm_reset_rssi_for_dm(struct dm_struct *dm, u8 station_id)\n{\n\tstruct cmn_sta_info *sta;\n\n\tsta = dm->phydm_sta_info[station_id];\n\n\tif (!is_sta_active(sta))\n\t\treturn;\n\tPHYDM_DBG(dm, DBG_RSSI_MNTR, \"Reset RSSI for macid = (( %d ))\\n\",\n\t\t  station_id);\n\n\tsta->rssi_stat.rssi_cck = -1;\n\tsta->rssi_stat.rssi_ofdm = -1;\n\tsta->rssi_stat.rssi = -1;\n\tsta->rssi_stat.ofdm_pkt_cnt = 0;\n\tsta->rssi_stat.cck_pkt_cnt = 0;\n\tsta->rssi_stat.cck_sum_power = 0;\n\tsta->rssi_stat.is_send_rssi = RA_RSSI_STATE_INIT;\n\tsta->rssi_stat.packet_map = 0;\n\tsta->rssi_stat.valid_bit = 0;\n}\n\n#if (ODM_IC_11N_SERIES_SUPPORT || ODM_IC_11AC_SERIES_SUPPORT)\n\ns32 phydm_get_rssi_8814_ofdm(struct dm_struct *dm, u8 *rssi_in)\n{\n\ts32 rssi_avg;\n\tu8 rx_count = 0;\n\tu64 rssi_linear = 0;\n\n\tif (dm->rx_ant_status & BB_PATH_A) {\n\t\trx_count++;\n\t\trssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_A]);\n\t}\n\n\tif (dm->rx_ant_status & BB_PATH_B) {\n\t\trx_count++;\n\t\trssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_B]);\n\t}\n\n\tif (dm->rx_ant_status & BB_PATH_C) {\n\t\trx_count++;\n\t\trssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_C]);\n\t}\n\n\tif (dm->rx_ant_status & BB_PATH_D) {\n\t\trx_count++;\n\t\trssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_D]);\n\t}\n\n\t/* @Rounding and removing fractional bits */\n\trssi_linear = (rssi_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;\n\n\t/* @Calculate average RSSI */\n\tswitch (rx_count) {\n\tcase 2:\n\t\trssi_linear = DIVIDED_2(rssi_linear);\n\t\tbreak;\n\tcase 3:\n\t\trssi_linear = DIVIDED_3(rssi_linear);\n\t\tbreak;\n\tcase 4:\n\t\trssi_linear = DIVIDED_4(rssi_linear);\n\t\tbreak;\n\t}\n\trssi_avg = odm_convert_to_db(rssi_linear);\n\n\treturn rssi_avg;\n}\n\nvoid phydm_process_rssi_for_dm(struct dm_struct *dm,\n\t\t\t       struct phydm_phyinfo_struct *phy_info,\n\t\t\t       struct phydm_perpkt_info_struct *pktinfo)\n{\n\ts32 rssi_ave = 0; /*@average among all paths*/\n\ts8 rssi_all = 0; /*@average value of CCK & OFDM*/\n\ts8 rssi_cck_tmp = 0, rssi_ofdm_tmp = 0;\n\tu8 i = 0;\n\tu8 rssi_max = 0, rssi_min = 0;\n\tu32 w1 = 0, w2 = 0; /*weighting*/\n\tu8 send_rssi_2_fw = 0;\n\tu8 *rssi_tmp = NULL;\n\tstruct cmn_sta_info *sta = NULL;\n\tstruct rssi_info *rssi_t = NULL;\n\t#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\t#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\t#endif\n\t#endif\n\n\tif (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)\n\t\treturn;\n\n\t#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY\n\todm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(dm, phy_info, pktinfo);\n\t#endif\n\t#ifdef ODM_EVM_ENHANCE_ANTDIV\n\tphydm_rx_rate_for_antdiv(dm, pktinfo);\n\t#endif\n\n\tsta = dm->phydm_sta_info[pktinfo->station_id];\n\n\tif (!is_sta_active(sta))\n\t\treturn;\n\n\trssi_t = &sta->rssi_stat;\n\n\t#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\t#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\n\tif ((dm->support_ability & ODM_BB_ANT_DIV) &&\n\t    fat_tab->enable_ctrl_frame_antdiv) {\n\t\tif (pktinfo->is_packet_match_bssid)\n\t\t\tdm->data_frame_num++;\n\n\t\tif (fat_tab->use_ctrl_frame_antdiv) {\n\t\t\tif (!pktinfo->is_to_self) /*@data frame + CTRL frame*/\n\t\t\t\treturn;\n\t\t} else {\n\t\t\t/*@data frame only*/\n\t\t\tif (!pktinfo->is_packet_match_bssid)\n\t\t\t\treturn;\n\t\t}\n\t} else\n\t#endif\n\t#endif\n\t{\n\t\tif (!pktinfo->is_packet_match_bssid) /*@data frame only*/\n\t\t\treturn;\n\t}\n\n\tif (pktinfo->is_packet_beacon) {\n\t\tdm->phy_dbg_info.num_qry_beacon_pkt++;\n\t\tdm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;\n\t}\n\n\t/* @--------------Statistic for antenna/path diversity--------------- */\n\t#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))\n\tif (dm->support_ability & ODM_BB_ANT_DIV)\n\t\todm_process_rssi_for_ant_div(dm, phy_info, pktinfo);\n\t#endif\n\n\t#if (defined(CONFIG_PATH_DIVERSITY))\n\tif (dm->support_ability & ODM_BB_PATH_DIV)\n\t\tphydm_process_rssi_for_path_div(dm, phy_info, pktinfo);\n\t#endif\n\t/* @----------------------------------------------------------------- */\n\n\trssi_cck_tmp = rssi_t->rssi_cck;\n\trssi_ofdm_tmp = rssi_t->rssi_ofdm;\n\trssi_all = rssi_t->rssi;\n\n\tif (!(pktinfo->is_packet_to_self || pktinfo->is_packet_beacon))\n\t\treturn;\n\n\tif (!pktinfo->is_cck_rate) {\n/* @=== [ofdm RSSI] ======================================================== */\n\t\trssi_tmp = phy_info->rx_mimo_signal_strength;\n\n\t\t#if (RTL8814A_SUPPORT == 1)\n\t\tif (dm->support_ic_type & (ODM_RTL8814A)) {\n\t\t\trssi_ave = phydm_get_rssi_8814_ofdm(dm, rssi_tmp);\n\t\t} else\n\t\t#endif\n\t\t{\n\t\t\tif (rssi_tmp[RF_PATH_B] == 0) {\n\t\t\t\trssi_ave = rssi_tmp[RF_PATH_A];\n\t\t\t} else {\n\t\t\t\tif (rssi_tmp[RF_PATH_A] > rssi_tmp[RF_PATH_B]) {\n\t\t\t\t\trssi_max = rssi_tmp[RF_PATH_A];\n\t\t\t\t\trssi_min = rssi_tmp[RF_PATH_B];\n\t\t\t\t} else {\n\t\t\t\t\trssi_max = rssi_tmp[RF_PATH_B];\n\t\t\t\t\trssi_min = rssi_tmp[RF_PATH_A];\n\t\t\t\t}\n\t\t\t\tif ((rssi_max - rssi_min) < 3)\n\t\t\t\t\trssi_ave = rssi_max;\n\t\t\t\telse if ((rssi_max - rssi_min) < 6)\n\t\t\t\t\trssi_ave = rssi_max - 1;\n\t\t\t\telse if ((rssi_max - rssi_min) < 10)\n\t\t\t\t\trssi_ave = rssi_max - 2;\n\t\t\t\telse\n\t\t\t\t\trssi_ave = rssi_max - 3;\n\t\t\t}\n\t\t}\n\n\t\t/* OFDM MA RSSI */\n\t\tif (rssi_ofdm_tmp <= 0) { /* @initialize */\n\t\t\trssi_ofdm_tmp = (s8)phy_info->rx_pwdb_all;\n\t\t} else {\n\t\t\trssi_ofdm_tmp = (s8)WEIGHTING_AVG(rssi_ofdm_tmp,\n\t\t\t\t\t\t\t  (1 << RSSI_MA) - 1,\n\t\t\t\t\t\t\t  rssi_ave, 1);\n\t\t\tif (phy_info->rx_pwdb_all > (u32)rssi_ofdm_tmp)\n\t\t\t\trssi_ofdm_tmp++;\n\t\t}\n\n\t\tPHYDM_DBG(dm, DBG_RSSI_MNTR, \"rssi_ofdm=%d\\n\", rssi_ofdm_tmp);\n\t} else {\n/* @=== [cck RSSI] ========================================================= */\n\t\trssi_ave = phy_info->rx_pwdb_all;\n\n\t\tif (rssi_t->cck_pkt_cnt <= 63)\n\t\t\trssi_t->cck_pkt_cnt++;\n\n\t\t/* @1 Process CCK RSSI */\n\t\tif (rssi_cck_tmp <= 0) { /* @initialize */\n\t\t\trssi_cck_tmp = (s8)phy_info->rx_pwdb_all;\n\t\t\trssi_t->cck_sum_power = (u16)phy_info->rx_pwdb_all;\n\t\t\trssi_t->cck_pkt_cnt = 1; /*reset*/\n\t\t\tPHYDM_DBG(dm, DBG_RSSI_MNTR, \"[1]CCK_INIT\\n\");\n\t\t} else if (rssi_t->cck_pkt_cnt <= CCK_RSSI_INIT_COUNT) {\n\t\t\trssi_t->cck_sum_power = rssi_t->cck_sum_power +\n\t\t\t\t\t\t(u16)phy_info->rx_pwdb_all;\n\n\t\t\trssi_cck_tmp = rssi_t->cck_sum_power /\n\t\t\t\t       rssi_t->cck_pkt_cnt;\n\n\t\t\tPHYDM_DBG(dm, DBG_RSSI_MNTR,\n\t\t\t\t  \"[2]SumPow=%d, cck_pkt=%d\\n\",\n\t\t\t\t  rssi_t->cck_sum_power, rssi_t->cck_pkt_cnt);\n\t\t} else {\n\t\t\trssi_cck_tmp = (s8)WEIGHTING_AVG(rssi_cck_tmp,\n\t\t\t\t\t\t\t (1 << RSSI_MA) - 1,\n\t\t\t\t\t\t\t phy_info->rx_pwdb_all,\n\t\t\t\t\t\t\t 1);\n\t\t\tif (phy_info->rx_pwdb_all > (u32)rssi_cck_tmp)\n\t\t\t\trssi_cck_tmp++;\n\t\t}\n\t\tPHYDM_DBG(dm, DBG_RSSI_MNTR, \"rssi_cck=%d\\n\", rssi_cck_tmp);\n\t}\n\n/* @=== [ofdm + cck weighting RSSI] ========================================= */\n\tif (!pktinfo->is_cck_rate) {\n\t\tif (rssi_t->ofdm_pkt_cnt < 8 && !(rssi_t->packet_map & BIT(7)))\n\t\t\trssi_t->ofdm_pkt_cnt++; /*OFDM packet cnt in bitmap*/\n\n\t\trssi_t->packet_map = (rssi_t->packet_map << 1) | BIT(0);\n\t} else {\n\t\tif (rssi_t->ofdm_pkt_cnt > 0 && rssi_t->packet_map & BIT(7))\n\t\t\trssi_t->ofdm_pkt_cnt--;\n\n\t\trssi_t->packet_map = rssi_t->packet_map << 1;\n\t}\n\n\tif (rssi_t->ofdm_pkt_cnt == 8) {\n\t\trssi_all = rssi_ofdm_tmp;\n\t} else {\n\t\tif (rssi_t->valid_bit < 8)\n\t\t\trssi_t->valid_bit++;\n\n\t\tif (rssi_t->valid_bit == 8) {\n\t\t\tif (rssi_t->ofdm_pkt_cnt > 4)\n\t\t\t\tw1 = 64;\n\t\t\telse\n\t\t\t\tw1 = (u32)(rssi_t->ofdm_pkt_cnt << 4);\n\n\t\t\tw2 = 64 - w1;\n\n\t\t\trssi_all = (s8)((w1 * (u32)rssi_ofdm_tmp +\n\t\t\t\t\t w2 * (u32)rssi_cck_tmp) >> 6);\n\t\t} else if (rssi_t->valid_bit != 0) { /*@(valid_bit > 8)*/\n\t\t\tw1 = (u32)rssi_t->ofdm_pkt_cnt;\n\t\t\tw2 = (u32)(rssi_t->valid_bit - rssi_t->ofdm_pkt_cnt);\n\t\t\trssi_all = (s8)WEIGHTING_AVG((u32)rssi_ofdm_tmp, w1,\n\t\t\t\t\t\t     (u32)rssi_cck_tmp, w2);\n\t\t} else {\n\t\t\trssi_all = 0;\n\t\t}\n\t}\n\tPHYDM_DBG(dm, DBG_RSSI_MNTR, \"rssi=%d,w1=%d,w2=%d\\n\", rssi_all, w1, w2);\n\n\tif ((rssi_t->ofdm_pkt_cnt >= 1 || rssi_t->cck_pkt_cnt >= 5) &&\n\t    rssi_t->is_send_rssi == RA_RSSI_STATE_INIT) {\n\t\tsend_rssi_2_fw = 1;\n\t\trssi_t->is_send_rssi = RA_RSSI_STATE_SEND;\n\t}\n\n\trssi_t->rssi_cck = rssi_cck_tmp;\n\trssi_t->rssi_ofdm = rssi_ofdm_tmp;\n\trssi_t->rssi = rssi_all;\n\n\tif (send_rssi_2_fw) { /* Trigger init rate by RSSI */\n\t\tif (rssi_t->ofdm_pkt_cnt != 0)\n\t\t\trssi_t->rssi = rssi_ofdm_tmp;\n\n\t\tPHYDM_DBG(dm, DBG_RSSI_MNTR,\n\t\t\t  \"[Send to FW] PWDB=%d, ofdm_pkt=%d, cck_pkt=%d\\n\",\n\t\t\t  rssi_all, rssi_t->ofdm_pkt_cnt, rssi_t->cck_pkt_cnt);\n\t}\n\n#if 0\n\t/* @dbg_print(\"ofdm_pkt=%d, weighting=%d\\n\", ofdm_pkt_cnt, weighting);*/\n\t/* @dbg_print(\"rssi_ofdm_tmp=%d, rssi_all=%d, rssi_cck_tmp=%d\\n\", */\n\t/*\trssi_ofdm_tmp, rssi_all, rssi_cck_tmp); */\n#endif\n}\n#endif\n\n#ifdef PHYSTS_3RD_TYPE_SUPPORT\nvoid phydm_print_phystat_jaguar3(struct dm_struct *dm, u8 *phy_sts,\n\t\t\t\t struct phydm_perpkt_info_struct *pktinfo,\n\t\t\t\t struct phydm_phyinfo_struct *phy_info)\n{\n\tstruct phy_sts_rpt_jgr3_type0 *rpt0 = NULL;\n\tstruct phy_sts_rpt_jgr3_type1 *rpt1 = NULL;\n\tstruct phy_sts_rpt_jgr3_type2_3 *rpt2 = NULL;\n\tstruct phy_sts_rpt_jgr3_type4 *rpt3 = NULL;\n\tstruct phy_sts_rpt_jgr3_type5 *rpt4 = NULL;\n\tstruct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;\n\tu8 phy_status_page_num = (*phy_sts & 0xf);\n\tu32 phy_status_tmp[PHY_STATUS_JRGUAR3_DW_LEN] = {0};\n\tu8 i = 0;\n\tu32 size = PHY_STATUS_JRGUAR3_DW_LEN << 2;\n\n\trpt0 = (struct phy_sts_rpt_jgr3_type0 *)phy_sts;\n\trpt1 = (struct phy_sts_rpt_jgr3_type1 *)phy_sts;\n\trpt2 = (struct phy_sts_rpt_jgr3_type2_3 *)phy_sts;\n\trpt3 = (struct phy_sts_rpt_jgr3_type4 *)phy_sts;\n\trpt4 = (struct phy_sts_rpt_jgr3_type5 *)phy_sts;\n\n\todm_move_memory(dm, phy_status_tmp, phy_sts, size);\n\tif (!(dm->debug_components & DBG_PHY_STATUS))\n\t\treturn;\n\n\tif (dbg->show_phy_sts_all_pkt == 0) {\n\t\tif (!pktinfo->is_packet_match_bssid)\n\t\t\treturn;\n\t}\n\n\tdbg->show_phy_sts_cnt++;\n\n\tif (dbg->show_phy_sts_max_cnt != SHOW_PHY_STATUS_UNLIMITED) {\n\t\tif (dbg->show_phy_sts_cnt > dbg->show_phy_sts_max_cnt)\n\t\t\treturn;\n\t}\n\n\tif (phy_status_page_num == 0)\n\t\tpr_debug(\"Phy Status Rpt: CCK\\n\");\n\telse\n\t\tpr_debug(\"Phy Status Rpt: OFDM_%d\\n\", phy_status_page_num);\n\n\tpr_debug(\"StaID=%d, RxRate = 0x%x match_bssid=%d\\n\",\n\t\t pktinfo->station_id, pktinfo->data_rate,\n\t\t pktinfo->is_packet_match_bssid);\n\n\tfor (i = 0; i < PHY_STATUS_JRGUAR3_DW_LEN; i++)\n\t\tpr_debug(\"Offset[%d:%d] = 0x%x\\n\",\n\t\t\t ((4 * i) + 3), (4 * i), phy_status_tmp[i]);\n\n\tif (phy_status_page_num == 0) { /* @CCK(default) */\n\t\tpr_debug(\"[0] Pkt_cnt=%d, Channel_msb=%d, Pwdb_a=%d, Gain_a=%d, TRSW=%d, AGC_table_b=%d, AGC_table_c=%d,\\n\",\n\t\t\t rpt0->pkt_cnt, rpt0->channel_msb, rpt0->pwdb_a,\n\t\t\t rpt0->gain_a, rpt0->trsw, rpt0->agc_table_b,\n\t\t\t rpt0->agc_table_c);\n\t\tpr_debug(\"[4] Path_Sel_o=%d, Gnt_BT_keep_cnt=%d, HW_AntSW_occur_keep_cck=%d,\\n Band=%d, Channel=%d, AGC_table_a=%d, l_RXSC=%d, AGC_table_d=%d\\n\",\n\t\t\t rpt0->path_sel_o, rpt0->gnt_bt_keep_cck,\n\t\t\t rpt0->hw_antsw_occur_keep_cck, rpt0->band,\n\t\t\t rpt0->channel, rpt0->agc_table_a, rpt0->l_rxsc,\n\t\t\t rpt0->agc_table_d);\n\t\tpr_debug(\"[8] AntIdx={%d, %d, %d, %d}, Length=%d\\n\",\n\t\t\t rpt0->antidx_d, rpt0->antidx_c, rpt0->antidx_b,\n\t\t\t rpt0->antidx_a, rpt0->length);\n\t\tpr_debug(\"[12] MF_off=%d, SQloss=%d, lockbit=%d, raterr=%d, rxrate=%d, lna_h_a=%d, CCK_BB_power_a=%d, lna_l_a=%d, vga_a=%d, sq=%d\\n\",\n\t\t\t rpt0->mf_off, rpt0->sqloss, rpt0->lockbit,\n\t\t\t rpt0->raterr, rpt0->rxrate, rpt0->lna_h_a,\n\t\t\t rpt0->bb_power_a, rpt0->lna_l_a, rpt0->vga_a,\n\t\t\t rpt0->signal_quality);\n\t\tpr_debug(\"[16] Gain_b=%d, lna_h_b=%d, CCK_BB_power_b=%d, lna_l_b=%d, vga_b=%d, Pwdb_b=%d\\n\",\n\t\t\t rpt0->gain_b, rpt0->lna_h_b, rpt0->bb_power_b,\n\t\t\t rpt0->lna_l_b, rpt0->vga_b, rpt0->pwdb_b);\n\t\tpr_debug(\"[20] Gain_c=%d, lna_h_c=%d, CCK_BB_power_c=%d, lna_l_c=%d, vga_c=%d, Pwdb_c=%d\\n\",\n\t\t\t rpt0->gain_c, rpt0->lna_h_c, rpt0->bb_power_c,\n\t\t\t rpt0->lna_l_c, rpt0->vga_c, rpt0->pwdb_c);\n\t\tpr_debug(\"[24] Gain_d=%d, lna_h_d=%d, CCK_BB_power_d=%d, lna_l_d=%d, vga_d=%d, Pwdb_d=%d\\n\",\n\t\t\t rpt0->gain_c, rpt0->lna_h_c, rpt0->bb_power_c,\n\t\t\t rpt0->lna_l_c, rpt0->vga_c, rpt0->pwdb_c);\n\t} else if (phy_status_page_num == 1) {\n\t\tpr_debug(\"[0] pwdb[C:A]={%d, %d, %d}, Channel_pri_msb=%d, Pkt_cnt=%d,\\n\",\n\t\t\t rpt1->pwdb_c, rpt1->pwdb_b, rpt1->pwdb_a,\n\t\t\t rpt1->channel_pri_msb, rpt1->pkt_cnt);\n\t\tpr_debug(\"[4] BF: %d, stbc=%d, ldpc=%d, gnt_bt=%d, band=%d, Ch_pri_lsb=%d, rxsc[ht, l]={%d, %d}, pwdb[D]=%d\\n\",\n\t\t\t rpt1->beamformed, rpt1->stbc, rpt1->ldpc, rpt1->gnt_bt,\n\t\t\t rpt1->band, rpt1->channel_pri_lsb, rpt1->ht_rxsc,\n\t\t\t rpt1->l_rxsc, rpt1->pwdb_d);\n\t\tpr_debug(\"[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}, Channel_sec[msb,lsb]={%d, %d}\\n\",\n\t\t\t rpt1->antidx_d, rpt1->antidx_c,\n\t\t\t rpt1->antidx_b, rpt1->antidx_a,\n\t\t\t rpt1->hw_antsw_occur_d, rpt1->hw_antsw_occur_c,\n\t\t\t rpt1->hw_antsw_occur_b, rpt1->hw_antsw_occur_a,\n\t\t\t rpt1->channel_sec_msb, rpt1->channel_sec_lsb);\n\t\tpr_debug(\"[12] GID=%d, PAID[msb,lsb]={%d,%d}\\n\",\n\t\t\t rpt1->gid, rpt1->paid_msb, rpt1->paid);\n\t\tpr_debug(\"[16] RX_EVM[D:A]={%d, %d, %d, %d}\\n\",\n\t\t\t rpt1->rxevm[3], rpt1->rxevm[2],\n\t\t\t rpt1->rxevm[1], rpt1->rxevm[0]);\n\t\tpr_debug(\"[20] CFO_tail[D:A]={%d, %d, %d, %d}\\n\",\n\t\t\t rpt1->cfo_tail[3], rpt1->cfo_tail[2],\n\t\t\t rpt1->cfo_tail[1], rpt1->cfo_tail[0]);\n\t\tpr_debug(\"[24] RX_SNR[D:A]={%d, %d, %d, %d}\\n\\n\",\n\t\t\t rpt1->rxsnr[3], rpt1->rxsnr[2],\n\t\t\t rpt1->rxsnr[1], rpt1->rxsnr[0]);\n\t} else if (phy_status_page_num == 2 || phy_status_page_num == 3) {\n\t\tpr_debug(\"[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\\n\",\n\t\t\t rpt2->pwdb[2], rpt2->pwdb[1], rpt2->pwdb[0],\n\t\t\t rpt2->channel_msb, rpt2->pkt_cnt);\n\t\tpr_debug(\"[4] BF=%d, STBC=%d, LDPC=%d, Gnt_BT=%d, band=%d, CH_lsb=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\\n\",\n\t\t\t rpt2->beamformed, rpt2->stbc, rpt2->ldpc, rpt2->gnt_bt,\n\t\t\t rpt2->band, rpt2->channel_lsb,\n\t\t\t rpt2->ht_rxsc, rpt2->l_rxsc, rpt2->pwdb[3]);\n\t\tpr_debug(\"[8] AgcTab[D:A]={%d, %d, %d, %d}, pwed_th=%d, shift_l_map=%d\\n\",\n\t\t\t rpt2->agc_table_d, rpt2->agc_table_c,\n\t\t\t rpt2->agc_table_b, rpt2->agc_table_a,\n\t\t\t rpt2->pwed_th, rpt2->shift_l_map);\n\t\tpr_debug(\"[12] AvgNoisePowerdB=%d, mp_gain_c[msb, lsb]={%d, %d}, mp_gain_b[msb, lsb]={%d, %d}, mp_gain_a=%d, cnt_cca2agc_rdy=%d\\n\",\n\t\t\t rpt2->avg_noise_pwr_lsb, rpt2->mp_gain_c_msb,\n\t\t\t rpt2->mp_gain_c_lsb, rpt2->mp_gain_b_msb,\n\t\t\t rpt2->mp_gain_b_lsb, rpt2->mp_gain_a,\n\t\t\t rpt2->cnt_cca2agc_rdy);\n\t\tpr_debug(\"[16] HT AAGC gain[B:A]={%d, %d}, AAGC step[D:A]={%d, %d, %d, %d}, IsFreqSelectFadimg=%d, mp_gain_d=%d\\n\",\n\t\t\t rpt2->ht_aagc_gain[1], rpt2->ht_aagc_gain[0],\n\t\t\t rpt2->aagc_step_d, rpt2->aagc_step_c,\n\t\t\t rpt2->aagc_step_b, rpt2->aagc_step_a,\n\t\t\t rpt2->is_freq_select_fading, rpt2->mp_gain_d);\n\t\tpr_debug(\"[20] DAGC gain ant[B:A]={%d, %d}, HT AAGC gain[D:C]={%d, %d}\\n\",\n\t\t\t rpt2->dagc_gain[1], rpt2->dagc_gain[0],\n\t\t\t rpt2->ht_aagc_gain[3], rpt2->ht_aagc_gain[2]);\n\t\tpr_debug(\"[24] AvgNoisePwerdB=%d, syn_count[msb, lsb]={%d, %d}, counter=%d, DAGC gain ant[D:C]={%d, %d}\\n\",\n\t\t\t rpt2->avg_noise_pwr_msb, rpt2->syn_count_msb,\n\t\t\t rpt2->syn_count_lsb, rpt2->counter,\n\t\t\t rpt2->dagc_gain[3], rpt2->dagc_gain[2]);\n\t} else if (phy_status_page_num == 4) { /*type 4*/\n\t\tpr_debug(\"[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\\n\",\n\t\t\t rpt3->pwdb[2], rpt3->pwdb[1], rpt3->pwdb[0],\n\t\t\t rpt3->channel_msb, rpt3->pkt_cnt);\n\t\tpr_debug(\"[4] BF=%d, STBC=%d, LDPC=%d, GNT_BT=%d, band=%d, CH_pri=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\\n\",\n\t\t\t rpt3->beamformed, rpt3->stbc, rpt3->ldpc, rpt3->gnt_bt,\n\t\t\t rpt3->band, rpt3->channel_lsb, rpt3->ht_rxsc,\n\t\t\t rpt3->l_rxsc, rpt3->pwdb[3]);\n\t\tpr_debug(\"[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}, Training_done[D:A]={%d, %d, %d, %d},\\n    BadToneCnt_CN_excess_0=%d, BadToneCnt_min_eign_0=%d\\n\",\n\t\t\t rpt3->antidx_d, rpt3->antidx_c,\n\t\t\t rpt3->antidx_b, rpt3->antidx_a,\n\t\t\t rpt3->hw_antsw_occur_d, rpt3->hw_antsw_occur_c,\n\t\t\t rpt3->hw_antsw_occur_b, rpt3->hw_antsw_occur_a,\n\t\t\t rpt3->training_done_d, rpt3->training_done_c,\n\t\t\t rpt3->training_done_b, rpt3->training_done_a,\n\t\t\t rpt3->bad_tone_cnt_cn_excess_0,\n\t\t\t rpt3->bad_tone_cnt_min_eign_0);\n\t\tpr_debug(\"[12] avg_cond_num_1_msb=%d, avg_cond_num_1_lsb=%d, avg_cond_num_0=%d, bad_tone_cnt_cn_excess_1=%d,\\n     bad_tone_cnt_min_eign_1=%d, Tx_pkt_cnt=%d\\n\",\n\t\t\t rpt3->avg_cond_num_1_msb, rpt3->avg_cond_num_1_lsb,\n\t\t\t rpt3->avg_cond_num_0, rpt3->bad_tone_cnt_cn_excess_1,\n\t\t\t rpt3->bad_tone_cnt_min_eign_1, rpt3->tx_pkt_cnt);\n\t\tpr_debug(\"[16] Stream RXEVM[D:A]={%d, %d, %d, %d}\\n\",\n\t\t\t rpt3->rxevm[3], rpt3->rxevm[2],\n\t\t\t rpt3->rxevm[1], rpt3->rxevm[0]);\n\t\tpr_debug(\"[20] Eigenvalue[D:A]={%d, %d, %d, %d}\\n\",\n\t\t\t rpt3->eigenvalue[3], rpt3->eigenvalue[2],\n\t\t\t rpt3->eigenvalue[1], rpt3->eigenvalue[0]);\n\t\tpr_debug(\"[24] RX SNR[D:A]={%d, %d, %d, %d}\\n\",\n\t\t\t rpt3->rxsnr[3], rpt3->rxsnr[2],\n\t\t\t rpt3->rxsnr[1], rpt3->rxsnr[0]);\n\t} else if (phy_status_page_num == 5) { /*type 5*/\n\t\tpr_debug(\"[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\\n\",\n\t\t\t rpt4->pwdb[2], rpt4->pwdb[1], rpt4->pwdb[0],\n\t\t\t rpt4->channel_msb, rpt4->pkt_cnt);\n\t\tpr_debug(\"[4] BF=%d, STBC=%d, LDPC=%d, GNT_BT=%d, band=%d, CH_pri=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\\n\",\n\t\t\t rpt4->beamformed, rpt4->stbc, rpt4->ldpc, rpt4->gnt_bt,\n\t\t\t rpt4->band, rpt4->channel_lsb, rpt4->ht_rxsc,\n\t\t\t rpt4->l_rxsc, rpt4->pwdb[3]);\n\t\tpr_debug(\"[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}\\n\",\n\t\t\t rpt4->antidx_d, rpt4->antidx_c,\n\t\t\t rpt4->antidx_b, rpt4->antidx_a,\n\t\t\t rpt4->hw_antsw_occur_d, rpt4->hw_antsw_occur_c,\n\t\t\t rpt4->hw_antsw_occur_b, rpt4->hw_antsw_occur_a);\n\t\tpr_debug(\"[12] Inf_posD[1,0]={%d, %d}, Inf_posC[1,0]={%d, %d}, Inf_posB[1,0]={%d, %d}, Inf_posA[1,0]={%d, %d}, Tx_pkt_cnt=%d\\n\",\n\t\t\t rpt4->inf_pos_1_D_flg, rpt4->inf_pos_0_D_flg,\n\t\t\t rpt4->inf_pos_1_C_flg, rpt4->inf_pos_0_C_flg,\n\t\t\t rpt4->inf_pos_1_B_flg, rpt4->inf_pos_0_B_flg,\n\t\t\t rpt4->inf_pos_1_A_flg, rpt4->inf_pos_0_A_flg,\n\t\t\t rpt4->tx_pkt_cnt);\n\t\tpr_debug(\"[16] Inf_pos_B[1,0]={%d, %d}, Inf_pos_A[1,0]={%d, %d}\\n\",\n\t\t\t rpt4->inf_pos_1_b, rpt4->inf_pos_0_b,\n\t\t\t rpt4->inf_pos_1_a, rpt4->inf_pos_0_a);\n\t\tpr_debug(\"[20] Inf_pos_D[1,0]={%d, %d}, Inf_pos_C[1,0]={%d, %d}\\n\",\n\t\t\t rpt4->inf_pos_1_d, rpt4->inf_pos_0_d,\n\t\t\t rpt4->inf_pos_1_c, rpt4->inf_pos_0_c);\n\t}\n}\n\nvoid phydm_reset_phy_info_3rd(struct dm_struct *phydm,\n\t\t\t      struct phydm_phyinfo_struct *phy_info)\n{\n\tphy_info->rx_pwdb_all = 0;\n\tphy_info->signal_quality = 0;\n\tphy_info->band_width = 0;\n\tphy_info->rx_count = 0;\n\todm_memory_set(phydm, phy_info->rx_mimo_signal_quality, 0, 4);\n\todm_memory_set(phydm, phy_info->rx_mimo_signal_strength, 0, 4);\n\todm_memory_set(phydm, phy_info->rx_snr, 0, 4);\n\n\tphy_info->rx_power = -110;\n\tphy_info->recv_signal_power = -110;\n\tphy_info->bt_rx_rssi_percentage = 0;\n\tphy_info->signal_strength = 0;\n\tphy_info->channel = 0;\n\tphy_info->is_mu_packet = 0;\n\tphy_info->is_beamformed = 0;\n\tphy_info->rxsc = 0;\n\todm_memory_set(phydm, phy_info->rx_pwr, -110, 4);\n\todm_memory_set(phydm, phy_info->cfo_short, 0, 8);\n\todm_memory_set(phydm, phy_info->cfo_tail, 0, 8);\n\n\todm_memory_set(phydm, phy_info->rx_mimo_evm_dbm, 0, 4);\n}\n\nvoid phydm_per_path_info_3rd(u8 rx_path, s8 pwr, s8 rx_evm, s8 cfo_tail,\n\t\t\t     s8 rx_snr, struct phydm_phyinfo_struct *phy_info)\n{\n\tu8 evm_dbm = 0;\n\tu8 evm_percentage = 0;\n\n\t/* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */\n\n\tif (rx_evm < 0) {\n\t\t/* @Calculate EVM in dBm */\n\t\tevm_dbm = ((u8)(0 - rx_evm) >> 1);\n\n\t\tif (evm_dbm == 64)\n\t\t\tevm_dbm = 0; /*@if 1SS rate, evm_dbm [2nd stream] =64*/\n\n\t\tif (evm_dbm != 0) {\n\t\t\t/* @Convert EVM to 0%~100% percentage */\n\t\t\tif (evm_dbm >= 34)\n\t\t\t\tevm_percentage = 100;\n\t\t\telse\n\t\t\t\tevm_percentage = (evm_dbm << 1) + (evm_dbm);\n\t\t}\n\t}\n\n\tphy_info->rx_pwr[rx_path] = pwr;\n\n\t/*@CFO(kHz) = CFO_tail * 312.5(kHz) / 2^7 ~= CFO tail * 5/2 (kHz)*/\n\tphy_info->cfo_tail[rx_path] = (cfo_tail * 5) >> 1;\n\tphy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;\n\tphy_info->rx_mimo_signal_strength[rx_path] = phydm_pwr_2_percent(pwr);\n\tphy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;\n\tphy_info->rx_snr[rx_path] = rx_snr >> 1;\n}\n\nvoid phydm_common_phy_info_3rd(s8 rx_power, u8 channel, boolean is_beamformed,\n\t\t\t       boolean is_mu_packet, u8 bandwidth,\n\t\t\t       u8 signal_quality, u8 rxsc,\n\t\t\t       struct phydm_phyinfo_struct *phy_info)\n{\n\tphy_info->rx_power = rx_power; /* RSSI in dB */\n\tphy_info->recv_signal_power = rx_power; /* RSSI in dB */\n\tphy_info->channel = channel; /* @channel number */\n\tphy_info->is_beamformed = is_beamformed; /* @apply BF */\n\tphy_info->is_mu_packet = is_mu_packet; /* @MU packet */\n\tphy_info->rxsc = rxsc;\n\n\tphy_info->rx_pwdb_all = phydm_pwr_2_percent(rx_power); /*percentage */\n\tphy_info->signal_quality = signal_quality; /* signal quality */\n\tphy_info->band_width = bandwidth; /* @bandwidth */\n\n#if 0\n\t/* @if (pktinfo->is_packet_match_bssid) */\n\t{\n\t\tdbg_print(\"rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\\n\", phy_info->rx_pwdb_all, phy_info->rx_power, phy_info->recv_signal_power);\n\t\tdbg_print(\"signal_quality = %d\\n\", phy_info->signal_quality);\n\t\tdbg_print(\"is_beamformed = %d, is_mu_packet = %d, rx_count = %d\\n\", phy_info->is_beamformed, phy_info->is_mu_packet, phy_info->rx_count + 1);\n\t\tdbg_print(\"channel = %d, rxsc = %d, band_width = %d\\n\", channel, rxsc, bandwidth);\n\t}\n#endif\n}\n\nvoid phydm_get_physts_jarguar3_0(struct dm_struct *dm, u8 *phy_status_inf,\n\t\t\t\t struct phydm_perpkt_info_struct *pktinfo,\n\t\t\t\t struct phydm_phyinfo_struct *phy_info)\n{\n\t/* type 0 is used for cck packet */\n\tstruct phy_sts_rpt_jgr3_type0 *phy_sts = NULL;\n\tstruct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;\n\tu8 sq = 0, i;\n\ts8 rx_power[4];\n\ts8 rx_pwr_db_max = -120;\n\n\tphy_sts = (struct phy_sts_rpt_jgr3_type0 *)phy_status_inf;\n\n\trx_power[0] = phy_sts->pwdb_a;\n\trx_power[1] = phy_sts->pwdb_b;\n\trx_power[2] = phy_sts->pwdb_c;\n\trx_power[3] = phy_sts->pwdb_d;\n\n\t#if (RTL8822C_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8822C) {\n\t\tstruct phydm_physts *physts_table = &dm->dm_physts_table;\n\t\tif (phy_sts->gain_a < physts_table->cck_gi_l_bnd)\n\t\t\trx_power[0] += ((physts_table->cck_gi_l_bnd -\n\t\t\t\t\tphy_sts->gain_a) << 1);\n\t\telse if (phy_sts->gain_a > physts_table->cck_gi_u_bnd)\n\t\t\trx_power[0] -= ((phy_sts->gain_a -\n\t\t\t\t\tphysts_table->cck_gi_u_bnd) << 1);\n\n\t\tif (phy_sts->gain_b < physts_table->cck_gi_l_bnd)\n\t\t\trx_power[1] += ((physts_table->cck_gi_l_bnd -\n\t\t\t\t\tphy_sts->gain_b) << 1);\n\t\telse if (phy_sts->gain_b > physts_table->cck_gi_u_bnd)\n\t\t\trx_power[1] -= ((phy_sts->gain_b -\n\t\t\t\t\tphysts_table->cck_gi_u_bnd) << 1);\n\t}\n\t#endif\n\n\t/* @Setting the RX power: agc_idx -110 dBm*/\n\trx_power[0] -= 110;\n\trx_power[1] -= 110;\n\trx_power[2] -= 110;\n\trx_power[3] -= 110;\n\n\tfor (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {\n\t\tif (rx_power[i] > rx_pwr_db_max)\n\t\t\trx_pwr_db_max = rx_power[i];\n\t}\n\tif (pktinfo->is_to_self) {\n\t\tdm->ofdm_agc_idx[0] = phy_sts->pwdb_a;\n\t\tdm->ofdm_agc_idx[1] = phy_sts->pwdb_b;\n\t\tdm->ofdm_agc_idx[2] = phy_sts->pwdb_c;\n\t\tdm->ofdm_agc_idx[3] = phy_sts->pwdb_d;\n\t}\n\n\t/* @Calculate Signal Quality*/\n\tif (phy_sts->signal_quality >= 64) {\n\t\tsq = 0;\n\t} else if (phy_sts->signal_quality <= 20) {\n\t\tsq = 100;\n\t} else {\n\t\t/* @mapping to 2~99% */\n\t\tsq = 64 - phy_sts->signal_quality;\n\t\tsq = ((sq << 3) + sq) >> 2;\n\t}\n\n\t/* @Modify CCK PWDB if old AGC */\n\tif (!dm->cck_new_agc) {\n\t\tu8 lna_idx[4], vga_idx[4];\n\n\t\tlna_idx[0] = ((phy_sts->lna_h_a << 3) | phy_sts->lna_l_a);\n\t\tvga_idx[0] = phy_sts->vga_a;\n\t\tlna_idx[1] = ((phy_sts->lna_h_b << 3) | phy_sts->lna_l_b);\n\t\tvga_idx[1] = phy_sts->vga_b;\n\t\tlna_idx[2] = ((phy_sts->lna_h_c << 3) | phy_sts->lna_l_c);\n\t\tvga_idx[2] = phy_sts->vga_c;\n\t\tlna_idx[3] = ((phy_sts->lna_h_d << 3) | phy_sts->lna_l_d);\n\t\tvga_idx[3] = phy_sts->vga_d;\n\t\t#if (RTL8198F_SUPPORT)\n\t\t\t/*phydm_cck_rssi_8198f*/\n\t\t#endif\n\t}\n\n\t/*@CCK no STBC and LDPC*/\n\tdbg_i->is_ldpc_pkt = false;\n\tdbg_i->is_stbc_pkt = false;\n\n\t/* Update Common information */\n\tphydm_common_phy_info_3rd(rx_pwr_db_max, phy_sts->channel, false,\n\t\t\t\t  false, CHANNEL_WIDTH_20, sq,\n\t\t\t\t  phy_sts->l_rxsc, phy_info);\n\n\t/* Update CCK pwdb */\n\t/* Update per-path information */\n\tfor (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++)\n\t\tphydm_per_path_info_3rd(i, rx_power[i], 0, 0, 0, phy_info);\n\n\t#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\tdm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;\n\tdm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;\n\tdm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;\n\tdm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;\n\t#endif\n}\n\nvoid phydm_get_physts_jarguar3_1(struct dm_struct *dm, u8 *phy_status_inf,\n\t\t\t\t struct phydm_perpkt_info_struct *pktinfo,\n\t\t\t\t struct phydm_phyinfo_struct *phy_info)\n{\n\t/* type 1 is used for ofdm packet */\n\tstruct phy_sts_rpt_jgr3_type1 *phy_sts = NULL;\n\tstruct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;\n\ts8 rx_pwr_db = -120;\n\ts8 rx_path_pwr_db;\n\tu8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_cnt = 0;\n\tu8 pwdb[4];\n\tboolean is_mu;\n\n\tphy_sts = (struct phy_sts_rpt_jgr3_type1 *)phy_status_inf;\n\n\tpwdb[0] = phy_sts->pwdb_a;\n\tpwdb[1] = phy_sts->pwdb_b;\n\tpwdb[2] = phy_sts->pwdb_c;\n\tpwdb[3] = phy_sts->pwdb_d;\n\n\t/* Update per-path information */\n\tfor (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {\n\t\tif (dm->rx_ant_status & BIT(i)) {\n\t\t\trx_cnt++; /* @check the number of the ant */\n\n\t\t\tif (rx_cnt > dm->num_rf_path)\n\t\t\t\tbreak;\n\n\t\t\t/* Update per-path information\n\t\t\t * (RSSI_dB RSSI_percentage EVM SNR CFO sq)\n\t\t\t */\n\t\t\t/* @EVM report is reported by stream, not path */\n\t\t\t/* @per-path pw (dB)*/\n\t\t\trx_path_pwr_db = (s8)pwdb[i] - 110;\n\n\t\t\tif (pktinfo->is_to_self)\n\t\t\t\tdm->ofdm_agc_idx[i] = pwdb[i];\n\n\t\t\tphydm_per_path_info_3rd(i, rx_path_pwr_db,\n\t\t\t\t\t\tphy_sts->rxevm[rx_cnt - 1],\n\t\t\t\t\t\tphy_sts->cfo_tail[i],\n\t\t\t\t\t\tphy_sts->rxsnr[i], phy_info);\n\n\t\t\t/*@CFO(kHz) = CFO_tail*312.5/2^7 ~= CFO tail*5/2*/\n\t\t\tdbg_i->cfo_tail[i] = (phy_sts->cfo_tail[i] * 5) >> 1;\n\t\t\t/* search maximum pwdb */\n\t\t\tif (rx_path_pwr_db > rx_pwr_db)\n\t\t\t\trx_pwr_db = rx_path_pwr_db;\n\t\t}\n\t}\n\n\t/* @mapping RX counter from 1~4 to 0~3 */\n\tif (rx_cnt > 0)\n\t\tphy_info->rx_count = rx_cnt - 1;\n\n\t/* @Check if MU packet or not */\n\tif (phy_sts->gid != 0 && phy_sts->gid != 63) {\n\t\tis_mu = true;\n\t\tdbg_i->num_qry_mu_pkt++;\n\t} else {\n\t\tis_mu = false;\n\t}\n\n\t/* @count BF packet */\n\tdbg_i->num_qry_bf_pkt = dbg_i->num_qry_bf_pkt + phy_sts->beamformed;\n\n\t/*STBC or LDPC pkt*/\n\tdbg_i->is_ldpc_pkt = phy_sts->ldpc;\n\tdbg_i->is_stbc_pkt = phy_sts->stbc;\n\n\t/* @Check sub-channel */\n\tif (pktinfo->data_rate > ODM_RATE11M &&\n\t    pktinfo->data_rate < ODM_RATEMCS0)\n\t\trxsc = phy_sts->l_rxsc; /*@Legacy*/\n\telse\n\t\trxsc = phy_sts->ht_rxsc; /* @HT and VHT */\n\n\t/* @Check RX bandwidth */\n\tif (rxsc >= 1 && rxsc <= 8)\n\t\tbw = CHANNEL_WIDTH_20;\n\telse if ((rxsc >= 9) && (rxsc <= 12))\n\t\tbw = CHANNEL_WIDTH_40;\n\telse if (rxsc >= 13)\n\t\tbw = CHANNEL_WIDTH_80;\n\telse\n\t\tbw = *dm->band_width;\n\n\t/* Update packet information */\n\t/* RX power choose the path with the maximum power */\n\tphydm_common_phy_info_3rd(rx_pwr_db, phy_sts->channel_pri_lsb,\n\t\t\t\t  (boolean)phy_sts->beamformed, is_mu,\n\t\t\t\t  bw, phy_info->rx_mimo_signal_quality[0],\n\t\t\t\t  rxsc, phy_info);\n\n\tphydm_parsing_cfo(dm, pktinfo, phy_sts->cfo_tail, pktinfo->rate_ss);\n\n#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))\n\tdm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;\n\tdm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;\n\tdm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;\n\tdm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;\n#endif\n}\n\nvoid phydm_get_physts_jarguar3_2_3(struct dm_struct *dm, u8 *phy_status_inf,\n\t\t\t\t   struct phydm_perpkt_info_struct *pktinfo,\n\t\t\t\t   struct phydm_phyinfo_struct *phy_info)\n{\n\t/* type 2 & 3 is used for ofdm packet */\n\tstruct phy_sts_rpt_jgr3_type2_3 *phy_sts = NULL;\n\tstruct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;\n\ts8 rx_pwr_db_max = -120;\n\ts8 rx_path_pwr_db = 0;\n\tu8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;\n\n\tphy_sts = (struct phy_sts_rpt_jgr3_type2_3 *)phy_status_inf;\n\n\t/* Update per-path information */\n\tfor (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {\n\t\tif (dm->rx_ant_status & BIT(i)) {\n\t\t\trx_count++; /* @check the number of the ant */\n\n\t\t\tif (rx_count > dm->num_rf_path)\n\t\t\t\tbreak;\n\n\t\t\t/* Update per-path information\n\t\t\t * (RSSI_dB RSSI_percentage EVM SNR CFO sq)\n\t\t\t */\n\t\t\t/* @EVM report is reported by stream, not path */\n\t\t\trx_path_pwr_db = (s8)phy_sts->pwdb[i] - 110; /*@dB*/\n\n\t\t\tif (pktinfo->is_to_self)\n\t\t\t\tdm->ofdm_agc_idx[i] = phy_sts->pwdb[i];\n\n\t\t\tphydm_per_path_info_3rd(i, rx_path_pwr_db, 0,\n\t\t\t\t\t\t0, 0, phy_info);\n\n\t\t\t/* search maximum pwdb */\n\t\t\tif (rx_path_pwr_db > rx_pwr_db_max)\n\t\t\t\trx_pwr_db_max = rx_path_pwr_db;\n\t\t}\n\t}\n\n\t/* @mapping RX counter from 1~4 to 0~3 */\n\tif (rx_count > 0)\n\t\tphy_info->rx_count = rx_count - 1;\n\n\t/* @count BF packet */\n\tdbg_i->num_qry_bf_pkt = dm->phy_dbg_info.num_qry_bf_pkt +\n\t\t\t\t\t  phy_sts->beamformed;\n\n\t/*STBC or LDPC pkt*/\n\tdbg_i->is_ldpc_pkt = phy_sts->ldpc;\n\tdbg_i->is_stbc_pkt = phy_sts->stbc;\n\n\t/* @Check sub-channel */\n\tif (pktinfo->data_rate > ODM_RATE11M &&\n\t    pktinfo->data_rate < ODM_RATEMCS0)\n\t\trxsc = phy_sts->l_rxsc; /*@Legacy*/\n\telse\n\t\trxsc = phy_sts->ht_rxsc; /* @HT and VHT */\n\n\t/* @Check RX bandwidth */\n\tif (rxsc >= 1 && rxsc <= 8)\n\t\tbw = CHANNEL_WIDTH_20;\n\telse if ((rxsc >= 9) && (rxsc <= 12))\n\t\tbw = CHANNEL_WIDTH_40;\n\telse if (rxsc >= 13)\n\t\tbw = CHANNEL_WIDTH_80;\n\telse\n\t\tbw = *dm->band_width;\n\n\t/* Update packet information */\n\t/* RX power choose the path with the maximum power */\n\tphydm_common_phy_info_3rd(rx_pwr_db_max, phy_sts->channel_lsb,\n\t\t\t\t  (boolean)phy_sts->beamformed,\n\t\t\t\t  false, bw, 0, rxsc, phy_info);\n}\n\nvoid phydm_get_physts_jarguar3_4(struct dm_struct *dm, u8 *phy_status_inf,\n\t\t\t\t struct phydm_perpkt_info_struct *pktinfo,\n\t\t\t\t struct phydm_phyinfo_struct *phy_info)\n{\n\t/* type 4 is used for ofdm packet */\n\tstruct phy_sts_rpt_jgr3_type4 *phy_sts = NULL;\n\tstruct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;\n\ts8 rx_pwr_db_max = -120;\n\ts8 rx_path_pwr_db = 0;\n\tu8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_cnt = 0;\n\n\tphy_sts = (struct phy_sts_rpt_jgr3_type4 *)phy_status_inf;\n\n\t/* Update per-path information */\n\tfor (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {\n\t\tif (dm->rx_ant_status & BIT(i)) {\n\t\t\trx_cnt++; /* @check the number of the ant */\n\n\t\t\tif (rx_cnt > dm->num_rf_path)\n\t\t\t\tbreak;\n\n\t\t\t/* Update per-path information\n\t\t\t * (RSSI_dB RSSI_percentage EVM SNR CFO sq)\n\t\t\t */\n\t\t\t/* @EVM report is reported by stream, not path */\n\t\t\trx_path_pwr_db = (s8)phy_sts->pwdb[i] - 110; /*@dB*/\n\n\t\t\tif (pktinfo->is_to_self)\n\t\t\t\tdm->ofdm_agc_idx[i] = phy_sts->pwdb[i];\n\n\t\t\tphydm_per_path_info_3rd(i, rx_path_pwr_db,\n\t\t\t\t\t\tphy_sts->rxevm[rx_cnt - 1],\n\t\t\t\t\t\t0, phy_sts->rxsnr[i],\n\t\t\t\t\t\tphy_info);\n\n\t\t\t/* search maximum pwdb */\n\t\t\tif (rx_path_pwr_db > rx_pwr_db_max)\n\t\t\t\trx_pwr_db_max = rx_path_pwr_db;\n\t\t}\n\t}\n\n\t/* @mapping RX counter from 1~4 to 0~3 */\n\tif (rx_cnt > 0)\n\t\tphy_info->rx_count = rx_cnt - 1;\n\n\t/* @count BF packet */\n\tdbg_i->num_qry_bf_pkt = dm->phy_dbg_info.num_qry_bf_pkt +\n\t\t\t\t\t  phy_sts->beamformed;\n\n\t/* @STBC or LDPC pkt*/\n\tdbg_i->is_ldpc_pkt = phy_sts->ldpc;\n\tdbg_i->is_stbc_pkt = phy_sts->stbc;\n\n\t/* @Check sub-channel */\n\tif (pktinfo->data_rate > ODM_RATE11M &&\n\t    pktinfo->data_rate < ODM_RATEMCS0)\n\t\trxsc = phy_sts->l_rxsc; /*@Legacy*/\n\telse\n\t\trxsc = phy_sts->ht_rxsc; /* @HT and VHT */\n\n\t/* @Check RX bandwidth */\n\tif (rxsc >= 1 && rxsc <= 8)\n\t\tbw = CHANNEL_WIDTH_20;\n\telse if ((rxsc >= 9) && (rxsc <= 12))\n\t\tbw = CHANNEL_WIDTH_40;\n\telse if (rxsc >= 13)\n\t\tbw = CHANNEL_WIDTH_80;\n\telse\n\t\tbw = *dm->band_width;\n\n\t/* @Conditional number */\n\tdbg_i->condi_num = (u32)phy_sts->avg_cond_num_0;\n\n\t/* Update packet information */\n\t/* RX power choose the path with the maximum power */\n\tphydm_common_phy_info_3rd(rx_pwr_db_max, phy_sts->channel_lsb,\n\t\t\t\t  (boolean)phy_sts->beamformed,\n\t\t\t\t  false, bw, 0, rxsc, phy_info);\n}\n\nvoid phydm_get_physts_jarguar3_5(struct dm_struct *dm, u8 *phy_status_inf,\n\t\t\t\t struct phydm_perpkt_info_struct *pktinfo,\n\t\t\t\t struct phydm_phyinfo_struct *phy_info)\n{\n\t/* type 5 is used for ofdm packet */\n\tstruct phy_sts_rpt_jgr3_type5 *phy_sts = NULL;\n\tstruct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;\n\ts8 rx_pwr_db_max = -120;\n\ts8 rx_path_pwr_db = 0;\n\tu8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;\n\n\tphy_sts = (struct phy_sts_rpt_jgr3_type5 *)phy_status_inf;\n\n\t/* Update per-path information */\n\tfor (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {\n\t\tif (dm->rx_ant_status & BIT(i)) {\n\t\t\trx_count++; /* @check the number of the ant */\n\n\t\t\tif (rx_count > dm->num_rf_path)\n\t\t\t\tbreak;\n\n\t\t\t/* Update per-path information\n\t\t\t * (RSSI_dB RSSI_percentage EVM SNR CFO sq)\n\t\t\t */\n\t\t\t/* @EVM report is reported by stream, not path */\n\t\t\trx_path_pwr_db = (s8)phy_sts->pwdb[i] - 110; /*@dB*/\n\n\t\t\tif (pktinfo->is_to_self)\n\t\t\t\tdm->ofdm_agc_idx[i] = phy_sts->pwdb[i];\n\n\t\t\tphydm_per_path_info_3rd(i, rx_path_pwr_db,\n\t\t\t\t\t\t0, 0, 0, phy_info);\n\n\t\t\t/* search maximum pwdb */\n\t\t\tif (rx_path_pwr_db > rx_pwr_db_max)\n\t\t\t\trx_pwr_db_max = rx_path_pwr_db;\n\t\t}\n\t}\n\n\t/* @mapping RX counter from 1~4 to 0~3 */\n\tif (rx_count > 0)\n\t\tphy_info->rx_count = rx_count - 1;\n\n\t/* @count BF packet */\n\tdbg_i->num_qry_bf_pkt = dm->phy_dbg_info.num_qry_bf_pkt +\n\t\t\t\t\t  phy_sts->beamformed;\n\n\t/*STBC or LDPC pkt*/\n\tdbg_i->is_ldpc_pkt = phy_sts->ldpc;\n\tdbg_i->is_stbc_pkt = phy_sts->stbc;\n\n\t/* @Check sub-channel */\n\tif (pktinfo->data_rate > ODM_RATE11M &&\n\t    pktinfo->data_rate < ODM_RATEMCS0)\n\t\trxsc = phy_sts->l_rxsc; /*@Legacy*/\n\telse\n\t\trxsc = phy_sts->ht_rxsc; /* @HT and VHT */\n\n\t/* @Check RX bandwidth */\n\tif (rxsc >= 1 && rxsc <= 8)\n\t\tbw = CHANNEL_WIDTH_20;\n\telse if ((rxsc >= 9) && (rxsc <= 12))\n\t\tbw = CHANNEL_WIDTH_40;\n\telse if (rxsc >= 13)\n\t\tbw = CHANNEL_WIDTH_80;\n\telse\n\t\tbw = *dm->band_width;\n\n\t/* Update packet information */\n\t/* RX power choose the path with the maximum power */\n\tphydm_common_phy_info_3rd(rx_pwr_db_max, phy_sts->channel_lsb,\n\t\t\t\t  (boolean)phy_sts->beamformed,\n\t\t\t\t  false, bw, 0, rxsc, phy_info);\n}\n\nvoid phydm_process_dm_rssi_3rd_type(struct dm_struct *dm,\n\t\t\t\t    struct phydm_phyinfo_struct *phy_info,\n\t\t\t\t    struct phydm_perpkt_info_struct *pktinfo)\n{\n\tstruct cmn_sta_info *sta = NULL;\n\tstruct rssi_info *rssi_t = NULL;\n\tu8 rssi_tmp = 0;\n\tu64 rssi_linear = 0;\n\ts16 rssi_db = 0;\n\tu8 i = 0;\n\n\t/*@[Step4]*/\n\n\tif (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)\n\t\treturn;\n\n\tsta = dm->phydm_sta_info[pktinfo->station_id];\n\n\tif (!is_sta_active(sta))\n\t\treturn;\n\n\tif (!pktinfo->is_packet_match_bssid) /*@data frame only*/\n\t\treturn;\n\n\tif (!(pktinfo->is_packet_to_self) && !(pktinfo->is_packet_beacon))\n\t\treturn;\n\n\tif (pktinfo->is_packet_beacon) {\n\t\tdm->phy_dbg_info.num_qry_beacon_pkt++;\n\t\tdm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;\n\t}\n\n\t#if (defined(CONFIG_PATH_DIVERSITY))\n\tif (dm->support_ability & ODM_BB_PATH_DIV)\n\t\tphydm_process_rssi_for_path_div(dm, phy_info, pktinfo);\n\t#endif\n\n\trssi_t = &sta->rssi_stat;\n\n\tif (pktinfo->is_cck_rate) {\n\t\trssi_db = phy_info->rx_mimo_signal_strength[0]; /*Path-A*/\n\t\tif (rssi_t->rssi_acc == 0) {\n\t\t\trssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA);\n\t\t\trssi_t->rssi = (s8)(rssi_db);\n\t\t} else {\n\t\t\trssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc,\n\t\t\t\t\t\t  rssi_db, RSSI_MA);\n\t\t\trssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc,\n\t\t\t\t\t\t      RSSI_MA);\n\t\t}\n\t\trssi_t->rssi_cck = (s8)rssi_db;\n\t} else {\n\t\tfor (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {\n\t\t\trssi_tmp = phy_info->rx_mimo_signal_strength[i];\n\t\t\tif (rssi_tmp != 0)\n\t\t\t\trssi_linear += phydm_db_2_linear(rssi_tmp);\n\t\t}\n\t\t/* @Rounding and removing fractional bits */\n\t\trssi_linear = (rssi_linear +\n\t\t\t       (1 << (FRAC_BITS - 1))) >> FRAC_BITS;\n\n\t\tswitch (phy_info->rx_count + 1) {\n\t\tcase 2:\n\t\t\trssi_linear = DIVIDED_2(rssi_linear);\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\trssi_linear = DIVIDED_3(rssi_linear);\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\trssi_linear = DIVIDED_4(rssi_linear);\n\t\t\tbreak;\n\t\t}\n\t\trssi_db = (s16)odm_convert_to_db(rssi_linear);\n\n\t\tif (rssi_t->rssi_acc == 0) {\n\t\t\trssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA);\n\t\t\trssi_t->rssi = (s8)(rssi_db);\n\t\t} else {\n\t\t\trssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc,\n\t\t\t\t\t\t  rssi_db, RSSI_MA);\n\t\t\trssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc,\n\t\t\t\t\t\t      RSSI_MA);\n\t\t}\n\t\trssi_t->rssi_ofdm = (s8)rssi_db;\n\t}\n}\n\nvoid phydm_rx_physts_3rd_type(void *dm_void, u8 *phy_sts,\n\t\t\t      struct phydm_perpkt_info_struct *pktinfo,\n\t\t\t      struct phydm_phyinfo_struct *phy_info)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#ifdef PHYDM_PHYSTAUS_SMP_MODE\n\tstruct pkt_process_info *pkt_process = &dm->pkt_proc_struct;\n#endif\n\tu8 phy_status_type = (*phy_sts & 0xf);\n\n#ifdef PHYDM_PHYSTAUS_SMP_MODE\n\tif (pkt_process->phystatus_smp_mode_en && phy_status_type != 0) {\n\t\tif (pkt_process->pre_ppdu_cnt == pktinfo->ppdu_cnt)\n\t\t\treturn;\n\t\tpkt_process->pre_ppdu_cnt = pktinfo->ppdu_cnt;\n\t}\n#endif\n\n\t/*@[Step 2]*/\n\tphydm_reset_phy_info_3rd(dm, phy_info); /* @Memory reset */\n\n\t/* Phy status parsing */\n\tswitch (phy_status_type) {\n\tcase 0: /*@CCK*/\n\t\tphydm_get_physts_jarguar3_0(dm, phy_sts, pktinfo, phy_info);\n\t\tbreak;\n\tcase 1:\n\t\tphydm_get_physts_jarguar3_1(dm, phy_sts, pktinfo, phy_info);\n\t\tbreak;\n\tcase 2:\n\tcase 3:\n\t\tphydm_get_physts_jarguar3_2_3(dm, phy_sts, pktinfo, phy_info);\n\t\tbreak;\n\tcase 4:\n\t\tphydm_get_physts_jarguar3_4(dm, phy_sts, pktinfo, phy_info);\n\t\tbreak;\n\tcase 5:\n\t\tphydm_get_physts_jarguar3_5(dm, phy_sts, pktinfo, phy_info);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\n\t/*@[Step 1]*/\n\tphydm_print_phystat_jaguar3(dm, phy_sts, pktinfo, phy_info);\n}\n\n#endif\n\n#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)\n/* @For 8822B only!! need to move to FW finally */\n/*@==============================================*/\n\nboolean\nphydm_query_is_mu_api(struct dm_struct *phydm, u8 ppdu_idx, u8 *p_data_rate,\n\t\t      u8 *p_gid)\n{\n\tu8 data_rate = 0, gid = 0;\n\tboolean is_mu = false;\n\n\tdata_rate = phydm->phy_dbg_info.num_of_ppdu[ppdu_idx];\n\tgid = phydm->phy_dbg_info.gid_num[ppdu_idx];\n\n\tif (data_rate & BIT(7)) {\n\t\tis_mu = true;\n\t\tdata_rate = data_rate & ~(BIT(7));\n\t} else {\n\t\tis_mu = false;\n\t}\n\n\t*p_data_rate = data_rate;\n\t*p_gid = gid;\n\n\treturn is_mu;\n}\n\nvoid phydm_reset_phy_info(struct dm_struct *phydm,\n\t\t\t  struct phydm_phyinfo_struct *phy_info)\n{\n\tphy_info->rx_pwdb_all = 0;\n\tphy_info->signal_quality = 0;\n\tphy_info->band_width = 0;\n\tphy_info->rx_count = 0;\n\todm_memory_set(phydm, phy_info->rx_mimo_signal_quality, 0, 4);\n\todm_memory_set(phydm, phy_info->rx_mimo_signal_strength, 0, 4);\n\todm_memory_set(phydm, phy_info->rx_snr, 0, 4);\n\n\tphy_info->rx_power = -110;\n\tphy_info->recv_signal_power = -110;\n\tphy_info->bt_rx_rssi_percentage = 0;\n\tphy_info->signal_strength = 0;\n\tphy_info->channel = 0;\n\tphy_info->is_mu_packet = 0;\n\tphy_info->is_beamformed = 0;\n\tphy_info->rxsc = 0;\n\todm_memory_set(phydm, phy_info->rx_pwr, -110, 4);\n\todm_memory_set(phydm, phy_info->cfo_short, 0, 8);\n\todm_memory_set(phydm, phy_info->cfo_tail, 0, 8);\n\todm_memory_set(phydm, phy_info->ant_idx, 0, 4);\n\n\todm_memory_set(phydm, phy_info->rx_mimo_evm_dbm, 0, 4);\n}\n\nvoid phydm_print_phy_sts_jgr2(struct dm_struct *dm, u8 *phy_status_inf,\n\t\t\t      struct phydm_perpkt_info_struct *pktinfo,\n\t\t\t      struct phydm_phyinfo_struct *phy_info)\n{\n\tstruct phy_sts_rpt_jgr2_type0 *rpt0 = NULL;\n\tstruct phy_sts_rpt_jgr2_type1 *rpt = NULL;\n\tstruct phy_sts_rpt_jgr2_type2 *rpt2 = NULL;\n\tstruct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;\n\tu8 phy_status_page_num = (*phy_status_inf & 0xf);\n\tu32 phy_status[PHY_STATUS_JRGUAR2_DW_LEN] = {0};\n\tu8 i;\n\tu32 size = PHY_STATUS_JRGUAR2_DW_LEN << 2;\n\n\trpt0 = (struct phy_sts_rpt_jgr2_type0 *)phy_status_inf;\n\trpt = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf;\n\trpt2 = (struct phy_sts_rpt_jgr2_type2 *)phy_status_inf;\n\n\todm_move_memory(dm, phy_status, phy_status_inf, size);\n\n\tif (!(dm->debug_components & DBG_PHY_STATUS))\n\t\treturn;\n\n\tif (dbg->show_phy_sts_all_pkt == 0) {\n\t\tif (!pktinfo->is_packet_match_bssid)\n\t\t\treturn;\n\t}\n\n\tdbg->show_phy_sts_cnt++;\n\t#if 0\n\tdbg_print(\"cnt=%d, max=%d\\n\",\n\t\t  dbg->show_phy_sts_cnt, dbg->show_phy_sts_max_cnt);\n\t#endif\n\n\tif (dbg->show_phy_sts_max_cnt != SHOW_PHY_STATUS_UNLIMITED) {\n\t\tif (dbg->show_phy_sts_cnt > dbg->show_phy_sts_max_cnt)\n\t\t\treturn;\n\t}\n\n\tpr_debug(\"Phy Status Rpt: OFDM_%d\\n\", phy_status_page_num);\n\tpr_debug(\"StaID=%d, RxRate = 0x%x match_bssid=%d\\n\",\n\t\t pktinfo->station_id, pktinfo->data_rate,\n\t\t pktinfo->is_packet_match_bssid);\n\n\tfor (i = 0; i < PHY_STATUS_JRGUAR2_DW_LEN; i++)\n\t\tpr_debug(\"Offset[%d:%d] = 0x%x\\n\",\n\t\t\t ((4 * i) + 3), (4 * i), phy_status[i]);\n\n\tif (phy_status_page_num == 0) {\n\t\tpr_debug(\"[0] TRSW=%d, MP_gain_idx=%d, pwdb=%d\\n\",\n\t\t\t rpt0->trsw, rpt0->gain, rpt0->pwdb);\n\t\tpr_debug(\"[4] band=%d, CH=%d, agc_table = %d, rxsc = %d\\n\",\n\t\t\t rpt0->band, rpt0->channel,\n\t\t\t rpt0->agc_table, rpt0->rxsc);\n\t\tpr_debug(\"[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\\n\",\n\t\t\t rpt0->antidx_d, rpt0->antidx_c, rpt0->antidx_b,\n\t\t\t rpt0->antidx_a, rpt0->length);\n\t\tpr_debug(\"[12] lna_h=%d, bb_pwr=%d, lna_l=%d, vga=%d, sq=%d\\n\",\n\t\t\t rpt0->lna_h, rpt0->bb_power, rpt0->lna_l,\n\t\t\t rpt0->vga, rpt0->signal_quality);\n\n\t} else if (phy_status_page_num == 1) {\n\t\tpr_debug(\"[0] pwdb[D:A]={%d, %d, %d, %d}\\n\",\n\t\t\t rpt->pwdb[3], rpt->pwdb[2],\n\t\t\t rpt->pwdb[1], rpt->pwdb[0]);\n\t\tpr_debug(\"[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht, l]={%d, %d}\\n\",\n\t\t\t rpt->beamformed, rpt->ldpc, rpt->stbc, rpt->gnt_bt,\n\t\t\t rpt->hw_antsw_occu, rpt->band, rpt->channel,\n\t\t\t rpt->ht_rxsc, rpt->l_rxsc);\n\t\tpr_debug(\"[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\\n\",\n\t\t\t rpt->antidx_d, rpt->antidx_c, rpt->antidx_b,\n\t\t\t rpt->antidx_a, rpt->lsig_length);\n\t\tpr_debug(\"[12] rf_mode=%d, NBI=%d, Intf_pos=%d, GID=%d, PAID=%d\\n\",\n\t\t\t rpt->rf_mode, rpt->nb_intf_flag,\n\t\t\t (rpt->intf_pos + (rpt->intf_pos_msb << 8)), rpt->gid,\n\t\t\t (rpt->paid + (rpt->paid_msb << 8)));\n\t\tpr_debug(\"[16] EVM[D:A]={%d, %d, %d, %d}\\n\",\n\t\t\t rpt->rxevm[3], rpt->rxevm[2],\n\t\t\t rpt->rxevm[1], rpt->rxevm[0]);\n\t\tpr_debug(\"[20] CFO[D:A]={%d, %d, %d, %d}\\n\",\n\t\t\t rpt->cfo_tail[3], rpt->cfo_tail[2], rpt->cfo_tail[1],\n\t\t\t rpt->cfo_tail[0]);\n\t\tpr_debug(\"[24] SNR[D:A]={%d, %d, %d, %d}\\n\\n\",\n\t\t\t rpt->rxsnr[3], rpt->rxsnr[2], rpt->rxsnr[1],\n\t\t\t rpt->rxsnr[0]);\n\n\t} else if (phy_status_page_num == 2) {\n\t\tpr_debug(\"[0] pwdb[D:A]={%d, %d, %d, %d}\\n\",\n\t\t\t rpt2->pwdb[3], rpt2->pwdb[2], rpt2->pwdb[1],\n\t\t\t rpt2->pwdb[0]);\n\t\tpr_debug(\"[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht,l]={%d, %d}\\n\",\n\t\t\t rpt2->beamformed, rpt2->ldpc, rpt2->stbc, rpt2->gnt_bt,\n\t\t\t rpt2->hw_antsw_occu, rpt2->band, rpt2->channel,\n\t\t\t rpt2->ht_rxsc, rpt2->l_rxsc);\n\t\tpr_debug(\"[8] AgcTab[D:A]={%d, %d, %d, %d}, cnt_pw2cca=%d, shift_l_map=%d\\n\",\n\t\t\t rpt2->agc_table_d, rpt2->agc_table_c,\n\t\t\t rpt2->agc_table_b, rpt2->agc_table_a,\n\t\t\t rpt2->cnt_pw2cca, rpt2->shift_l_map);\n\t\tpr_debug(\"[12] (TRSW|Gain)[D:A]={%d %d, %d %d, %d %d, %d %d}, cnt_cca2agc_rdy=%d\\n\",\n\t\t\t rpt2->trsw_d, rpt2->gain_d, rpt2->trsw_c, rpt2->gain_c,\n\t\t\t rpt2->trsw_b, rpt2->gain_b, rpt2->trsw_a,\n\t\t\t rpt2->gain_a, rpt2->cnt_cca2agc_rdy);\n\t\tpr_debug(\"[16] AAGC step[D:A]={%d, %d, %d, %d} HT AAGC gain[D:A]={%d, %d, %d, %d}\\n\",\n\t\t\t rpt2->aagc_step_d, rpt2->aagc_step_c,\n\t\t\t rpt2->aagc_step_b, rpt2->aagc_step_a,\n\t\t\t rpt2->ht_aagc_gain[3], rpt2->ht_aagc_gain[2],\n\t\t\t rpt2->ht_aagc_gain[1], rpt2->ht_aagc_gain[0]);\n\t\tpr_debug(\"[20] DAGC gain[D:A]={%d, %d, %d, %d}\\n\",\n\t\t\t rpt2->dagc_gain[3],\n\t\t\t rpt2->dagc_gain[2], rpt2->dagc_gain[1],\n\t\t\t rpt2->dagc_gain[0]);\n\t\tpr_debug(\"[24] syn_cnt: %d, Cnt=%d\\n\\n\",\n\t\t\t rpt2->syn_count, rpt2->counter);\n\t}\n}\n\nvoid phydm_set_per_path_phy_info(u8 rx_path, s8 pwr, s8 rx_evm, s8 cfo_tail,\n\t\t\t\t s8 rx_snr, u8 ant_idx,\n\t\t\t\t struct phydm_phyinfo_struct *phy_info)\n{\n\tu8 evm_dbm = 0;\n\tu8 evm_percentage = 0;\n\n\t/* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */\n\n\tif (rx_evm < 0) {\n\t\t/* @Calculate EVM in dBm */\n\t\tevm_dbm = ((u8)(0 - rx_evm) >> 1);\n\n\t\tif (evm_dbm == 64)\n\t\t\tevm_dbm = 0; /*@if 1SS rate, evm_dbm [2nd stream] =64*/\n\n\t\tif (evm_dbm != 0) {\n\t\t\t/* @Convert EVM to 0%~100% percentage */\n\t\t\tif (evm_dbm >= 34)\n\t\t\t\tevm_percentage = 100;\n\t\t\telse\n\t\t\t\tevm_percentage = (evm_dbm << 1) + (evm_dbm);\n\t\t}\n\t}\n\n\tphy_info->rx_pwr[rx_path] = pwr;\n\n\t/*@CFO(kHz) = CFO_tail * 312.5(kHz) / 2^7 ~= CFO tail * 5/2 (kHz)*/\n\tphy_info->cfo_tail[rx_path] = (cfo_tail * 5) >> 1;\n\tphy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;\n\tphy_info->rx_mimo_signal_strength[rx_path] = phydm_pwr_2_percent(pwr);\n\tphy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;\n\tphy_info->rx_snr[rx_path] = rx_snr >> 1;\n\tphy_info->ant_idx[rx_path] = ant_idx;\n\n#if 0\n\tif (!pktinfo->is_packet_match_bssid)\n\t\treturn;\n\n\tdbg_print(\"path (%d)--------\\n\", rx_path);\n\tdbg_print(\"rx_pwr = %d, Signal strength = %d\\n\",\n\t\t  phy_info->rx_pwr[rx_path],\n\t\t  phy_info->rx_mimo_signal_strength[rx_path]);\n\tdbg_print(\"evm_dbm = %d, Signal quality = %d\\n\",\n\t\t  phy_info->rx_mimo_evm_dbm[rx_path],\n\t\t  phy_info->rx_mimo_signal_quality[rx_path]);\n\tdbg_print(\"CFO = %d, SNR = %d\\n\",\n\t\t  phy_info->cfo_tail[rx_path], phy_info->rx_snr[rx_path]);\n\n#endif\n}\n\nvoid phydm_set_common_phy_info(s8 rx_power, u8 channel, boolean is_beamformed,\n\t\t\t       boolean is_mu_packet, u8 bandwidth,\n\t\t\t       u8 signal_quality, u8 rxsc,\n\t\t\t       struct phydm_phyinfo_struct *phy_info)\n{\n\tphy_info->rx_power = rx_power; /* RSSI in dB */\n\tphy_info->recv_signal_power = rx_power; /* RSSI in dB */\n\tphy_info->channel = channel; /* @channel number */\n\tphy_info->is_beamformed = is_beamformed; /* @apply BF */\n\tphy_info->is_mu_packet = is_mu_packet; /* @MU packet */\n\tphy_info->rxsc = rxsc;\n\n\t/* RSSI in percentage */\n\tphy_info->rx_pwdb_all = phydm_pwr_2_percent(rx_power);\n\tphy_info->signal_quality = signal_quality; /* signal quality */\n\tphy_info->band_width = bandwidth; /* @bandwidth */\n\n#if 0\n\tif (!pktinfo->is_packet_match_bssid)\n\t\treturn;\n\n\tdbg_print(\"rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\\n\",\n\t\t  phy_info->rx_pwdb_all, phy_info->rx_power,\n\t\t  phy_info->recv_signal_power);\n\tdbg_print(\"signal_quality = %d\\n\", phy_info->signal_quality);\n\tdbg_print(\"is_beamformed = %d, is_mu_packet = %d, rx_count = %d\\n\",\n\t\t  phy_info->is_beamformed, phy_info->is_mu_packet,\n\t\t  phy_info->rx_count + 1);\n\tdbg_print(\"channel = %d, rxsc = %d, band_width = %d\\n\", channel,\n\t\t  rxsc, bandwidth);\n\n#endif\n}\n\nvoid phydm_get_phy_sts_type0(struct dm_struct *dm, u8 *phy_status_inf,\n\t\t\t     struct phydm_perpkt_info_struct *pktinfo,\n\t\t\t     struct phydm_phyinfo_struct *phy_info)\n{\n\t/* type 0 is used for cck packet */\n\tstruct phy_sts_rpt_jgr2_type0 *phy_sts = NULL;\n\tu8 sq = 0;\n\ts8 rx_pow = 0;\n\tu8 lna_idx = 0, vga_idx = 0;\n\tu8 ant_idx;\n\n\tphy_sts = (struct phy_sts_rpt_jgr2_type0 *)phy_status_inf;\n\trx_pow = phy_sts->pwdb - 110;\n\n\t/* Fill in per-path antenna index */\n\tant_idx = phy_sts->antidx_a;\n\n\tif (dm->support_ic_type & ODM_RTL8723D) {\n\t\t#if (RTL8723D_SUPPORT)\n\t\trx_pow = phy_sts->pwdb - 97;\n\t\t#endif\n\t}\n\t#if (RTL8821C_SUPPORT)\n\telse if (dm->support_ic_type & ODM_RTL8821C) {\n\t\tif (phy_sts->pwdb >= -57)\n\t\t\trx_pow = phy_sts->pwdb - 100;\n\t\telse\n\t\t\trx_pow = phy_sts->pwdb - 102;\n\t}\n\t#endif\n\n\tif (pktinfo->is_to_self) {\n\t\tdm->ofdm_agc_idx[0] = phy_sts->pwdb;\n\t\tdm->ofdm_agc_idx[1] = 0;\n\t\tdm->ofdm_agc_idx[2] = 0;\n\t\tdm->ofdm_agc_idx[3] = 0;\n\t}\n\n\t/* @Calculate Signal Quality*/\n\tif (phy_sts->signal_quality >= 64) {\n\t\tsq = 0;\n\t} else if (phy_sts->signal_quality <= 20) {\n\t\tsq = 100;\n\t} else {\n\t\t/* @mapping to 2~99% */\n\t\tsq = 64 - phy_sts->signal_quality;\n\t\tsq = ((sq << 3) + sq) >> 2;\n\t}\n\n\t/* @Get RSSI for old CCK AGC */\n\tif (!dm->cck_new_agc) {\n\t\tvga_idx = phy_sts->vga;\n\n\t\tif (dm->support_ic_type & ODM_RTL8197F) {\n\t\t\t/*@3bit LNA*/\n\t\t\tlna_idx = phy_sts->lna_l;\n\t\t} else {\n\t\t\t/*@4bit LNA*/\n\t\t\tlna_idx = (phy_sts->lna_h << 3) | phy_sts->lna_l;\n\t\t}\n\t\trx_pow = phydm_get_cck_rssi(dm, lna_idx, vga_idx);\n\t}\n\n\t/* @Confirm CCK RSSI */\n\t#if (RTL8197F_SUPPORT)\n\tif (dm->support_ic_type & ODM_RTL8197F) {\n\t\tu8 bb_pwr_th_l = 5; /* round( 31*0.15 ) */\n\t\tu8 bb_pwr_th_h = 27; /* round( 31*0.85 ) */\n\n\t\tif (phy_sts->bb_power < bb_pwr_th_l ||\n\t\t    phy_sts->bb_power > bb_pwr_th_h)\n\t\t\trx_pow = 0; /* @Error RSSI for CCK ; set 100*/\n\t}\n\t#endif\n\n\t/*@CCK no STBC and LDPC*/\n\tdm->phy_dbg_info.is_ldpc_pkt = false;\n\tdm->phy_dbg_info.is_stbc_pkt = false;\n\n\t/* Update Common information */\n\tphydm_set_common_phy_info(rx_pow, phy_sts->channel, false,\n\t\t\t\t  false, CHANNEL_WIDTH_20, sq,\n\t\t\t\t  phy_sts->rxsc, phy_info);\n\t/* Update CCK pwdb */\n\tphydm_set_per_path_phy_info(RF_PATH_A, rx_pow, 0, 0, 0, ant_idx,\n\t\t\t\t    phy_info);\n\n\t#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY\n\tdm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;\n\tdm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;\n\tdm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;\n\tdm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;\n\t#endif\n}\n\nvoid phydm_get_phy_sts_type1(struct dm_struct *dm, u8 *phy_status_inf,\n\t\t\t     struct phydm_perpkt_info_struct *pktinfo,\n\t\t\t     struct phydm_phyinfo_struct *phy_info)\n{\n\t/* type 1 is used for ofdm packet */\n\tstruct phy_sts_rpt_jgr2_type1 *phy_sts = NULL;\n\tstruct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;\n\ts8 rx_pwr_db = -120;\n\ts8 rx_pwr = 0;\n\tu8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;\n\tboolean is_mu;\n\tu8 ant_idx[4];\n\n\tphy_sts = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf;\n\n\t/* Fill in per-path antenna index */\n\tant_idx[0] = phy_sts->antidx_a;\n\tant_idx[1] = phy_sts->antidx_b;\n\tant_idx[2] = phy_sts->antidx_c;\n\tant_idx[3] = phy_sts->antidx_d;\n\n\t/* Update per-path information */\n\tfor (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {\n\t\tif (!(dm->rx_ant_status & BIT(i)))\n\t\t\tcontinue;\n\t\trx_count++;\n\n\t\tif (rx_count > dm->num_rf_path)\n\t\t\tbreak;\n\n\t\t/* Update per-path information\n\t\t * (RSSI_dB RSSI_percentage EVM SNR CFO sq)\n\t\t */\n\t\t/* @EVM report is reported by stream, not path */\n\t\trx_pwr = phy_sts->pwdb[i] - 110; /* per-path pwdb(dB)*/\n\n\t\tif (pktinfo->is_to_self)\n\t\t\tdm->ofdm_agc_idx[i] = phy_sts->pwdb[i];\n\n\t\tphydm_set_per_path_phy_info(i, rx_pwr,\n\t\t\t\t\t    phy_sts->rxevm[rx_count - 1],\n\t\t\t\t\t    phy_sts->cfo_tail[i],\n\t\t\t\t\t    phy_sts->rxsnr[i],\n\t\t\t\t\t    ant_idx[i], phy_info);\n\t\t/* search maximum pwdb */\n\t\tif (rx_pwr > rx_pwr_db)\n\t\t\trx_pwr_db = rx_pwr;\n\t}\n\n\t/* @mapping RX counter from 1~4 to 0~3 */\n\tif (rx_count > 0)\n\t\tphy_info->rx_count = rx_count - 1;\n\n\t/* @Check if MU packet or not */\n\tif (phy_sts->gid != 0 && phy_sts->gid != 63) {\n\t\tis_mu = true;\n\t\tdbg_i->num_qry_mu_pkt++;\n\t} else {\n\t\tis_mu = false;\n\t}\n\n\t/* @count BF packet */\n\tdbg_i->num_qry_bf_pkt = dbg_i->num_qry_bf_pkt + phy_sts->beamformed;\n\n\t/*STBC or LDPC pkt*/\n\tdbg_i->is_ldpc_pkt = phy_sts->ldpc;\n\tdbg_i->is_stbc_pkt = phy_sts->stbc;\n\n\t/* @Check sub-channel */\n\tif (pktinfo->data_rate > ODM_RATE11M &&\n\t    pktinfo->data_rate < ODM_RATEMCS0)\n\t\trxsc = phy_sts->l_rxsc;\n\telse\n\t\trxsc = phy_sts->ht_rxsc;\n\n\t/* @Check RX bandwidth */\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\tif (rxsc >= 1 && rxsc <= 8)\n\t\t\tbw = CHANNEL_WIDTH_20;\n\t\telse if ((rxsc >= 9) && (rxsc <= 12))\n\t\t\tbw = CHANNEL_WIDTH_40;\n\t\telse if (rxsc >= 13)\n\t\t\tbw = CHANNEL_WIDTH_80;\n\t\telse\n\t\t\tbw = phy_sts->rf_mode;\n\n\t} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\tif (phy_sts->rf_mode == 0)\n\t\t\tbw = CHANNEL_WIDTH_20;\n\t\telse if ((rxsc == 1) || (rxsc == 2))\n\t\t\tbw = CHANNEL_WIDTH_20;\n\t\telse\n\t\t\tbw = CHANNEL_WIDTH_40;\n\t}\n\n\t/* Update packet information */\n\tphydm_set_common_phy_info(rx_pwr_db, phy_sts->channel,\n\t\t\t\t  (boolean)phy_sts->beamformed, is_mu, bw,\n\t\t\t\t  phy_info->rx_mimo_signal_quality[0],\n\t\t\t\t  rxsc, phy_info);\n\n\tphydm_parsing_cfo(dm, pktinfo, phy_sts->cfo_tail, pktinfo->rate_ss);\n\t#ifdef PHYDM_LNA_SAT_CHK_TYPE2\n\tphydm_parsing_snr(dm, pktinfo, phy_sts->rxsnr);\n\t#endif\n\n\t#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))\n\tdm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;\n\tdm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;\n\tdm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;\n\tdm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;\n\t#endif\n}\n\nvoid phydm_get_phy_sts_type2(struct dm_struct *dm, u8 *phy_status_inf,\n\t\t\t     struct phydm_perpkt_info_struct *pktinfo,\n\t\t\t     struct phydm_phyinfo_struct *phy_info)\n{\n\tstruct phy_sts_rpt_jgr2_type2 *phy_sts = NULL;\n\ts8 rx_pwr_db_max = -120;\n\ts8 rx_pwr = 0;\n\tu8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;\n\n\tphy_sts = (struct phy_sts_rpt_jgr2_type2 *)phy_status_inf;\n\n\tfor (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {\n\t\tif (!(dm->rx_ant_status & BIT(i)))\n\t\t\tcontinue;\n\t\trx_count++;\n\n\t\tif (rx_count > dm->num_rf_path)\n\t\t\tbreak;\n\n\t\t/* Update per-path information*/\n\t\t/* RSSI_dB, RSSI_percentage, EVM, SNR, CFO, sq */\n\t\t#if (RTL8197F_SUPPORT)\n\t\tif ((dm->support_ic_type & ODM_RTL8197F) &&\n\t\t    phy_sts->pwdb[i] == 0x7f) { /*@97f workaround*/\n\n\t\t\tif (i == RF_PATH_A) {\n\t\t\t\trx_pwr = (phy_sts->gain_a) << 1;\n\t\t\t\trx_pwr = rx_pwr - 110;\n\t\t\t} else if (i == RF_PATH_B) {\n\t\t\t\trx_pwr = (phy_sts->gain_b) << 1;\n\t\t\t\trx_pwr = rx_pwr - 110;\n\t\t\t} else {\n\t\t\t\trx_pwr = 0;\n\t\t\t}\n\t\t} else\n\t\t#endif\n\t\t\trx_pwr = phy_sts->pwdb[i] - 110; /*@dBm*/\n\n\t\tphydm_set_per_path_phy_info(i, rx_pwr, 0, 0, 0, 0, phy_info);\n\n\t\tif (rx_pwr > rx_pwr_db_max) /* search max pwdb */\n\t\t\trx_pwr_db_max = rx_pwr;\n\t}\n\n\t/* @mapping RX counter from 1~4 to 0~3 */\n\tif (rx_count > 0)\n\t\tphy_info->rx_count = rx_count - 1;\n\n\t/* @Check RX sub-channel */\n\tif (pktinfo->data_rate > ODM_RATE11M &&\n\t    pktinfo->data_rate < ODM_RATEMCS0)\n\t\trxsc = phy_sts->l_rxsc;\n\telse\n\t\trxsc = phy_sts->ht_rxsc;\n\n\t/*STBC or LDPC pkt*/\n\tdm->phy_dbg_info.is_ldpc_pkt = phy_sts->ldpc;\n\tdm->phy_dbg_info.is_stbc_pkt = phy_sts->stbc;\n\n\t/* @Check RX bandwidth */\n\t/* @BW information of sc=0 is useless,\n\t *because there is no information of RF mode\n\t */\n\tif (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\tif (rxsc >= 1 && rxsc <= 8)\n\t\t\tbw = CHANNEL_WIDTH_20;\n\t\telse if ((rxsc >= 9) && (rxsc <= 12))\n\t\t\tbw = CHANNEL_WIDTH_40;\n\t\telse if (rxsc >= 13)\n\t\t\tbw = CHANNEL_WIDTH_80;\n\n\t} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\tif (rxsc == 3)\n\t\t\tbw = CHANNEL_WIDTH_40;\n\t\telse if ((rxsc == 1) || (rxsc == 2))\n\t\t\tbw = CHANNEL_WIDTH_20;\n\t}\n\n\t/* Update packet information */\n\tphydm_set_common_phy_info(rx_pwr_db_max, phy_sts->channel,\n\t\t\t\t  (boolean)phy_sts->beamformed,\n\t\t\t\t  false, bw, 0, rxsc, phy_info);\n}\n\nvoid phydm_process_rssi_for_dm_2nd_type(struct dm_struct *dm,\n\t\t\t\t\tstruct phydm_phyinfo_struct *phy_info,\n\t\t\t\t\tstruct phydm_perpkt_info_struct *pktinfo\n\t\t\t\t\t)\n{\n\tstruct cmn_sta_info *sta = NULL;\n\tstruct rssi_info *rssi_t = NULL;\n\tu8 rssi_tmp = 0;\n\tu64 rssi_linear = 0;\n\ts16 rssi_db = 0;\n\tu8 i = 0;\n\n\tif (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)\n\t\treturn;\n\n\tsta = dm->phydm_sta_info[pktinfo->station_id];\n\n\tif (!is_sta_active(sta))\n\t\treturn;\n\n\tif (!pktinfo->is_packet_match_bssid) /*@data frame only*/\n\t\treturn;\n\n#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))\n\tif (dm->support_ability & ODM_BB_ANT_DIV)\n\t\todm_process_rssi_for_ant_div(dm, phy_info, pktinfo);\n#endif\n\n#ifdef CONFIG_ADAPTIVE_SOML\n\tphydm_rx_qam_for_soml(dm, pktinfo);\n\tphydm_rx_rate_for_soml(dm, pktinfo);\n#endif\n\n\tif (!(pktinfo->is_packet_to_self) && !(pktinfo->is_packet_beacon))\n\t\treturn;\n\n\tif (pktinfo->is_packet_beacon) {\n\t\tdm->phy_dbg_info.num_qry_beacon_pkt++;\n\t\tdm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;\n\t}\n\n\trssi_t = &sta->rssi_stat;\n\n\tfor (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {\n\t\trssi_tmp = phy_info->rx_mimo_signal_strength[i];\n\t\tif (rssi_tmp != 0)\n\t\t\trssi_linear += phydm_db_2_linear(rssi_tmp);\n\t}\n\t/* @Rounding and removing fractional bits */\n\trssi_linear = (rssi_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;\n\n\tswitch (phy_info->rx_count + 1) {\n\tcase 2:\n\t\trssi_linear = DIVIDED_2(rssi_linear);\n\t\tbreak;\n\tcase 3:\n\t\trssi_linear = DIVIDED_3(rssi_linear);\n\t\tbreak;\n\tcase 4:\n\t\trssi_linear = DIVIDED_4(rssi_linear);\n\t\tbreak;\n\t}\n\n\trssi_db = (s16)odm_convert_to_db(rssi_linear);\n\n\tif (rssi_t->rssi_acc == 0) {\n\t\trssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA);\n\t\trssi_t->rssi = (s8)(rssi_db);\n\t} else {\n\t\trssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc, rssi_db, RSSI_MA);\n\t\trssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc, RSSI_MA);\n\t}\n\n\t#if 0\n\tPHYDM_DBG(dm, DBG_TMP, \"RSSI[%d]{A,B,C,D}={%d, %d, %d, %d} AVG=%d\\n\",\n\t\t  pktinfo->station_id,\n\t\t  phy_info->rx_mimo_signal_strength[0],\n\t\t  phy_info->rx_mimo_signal_strength[1],\n\t\t  phy_info->rx_mimo_signal_strength[2],\n\t\t  phy_info->rx_mimo_signal_strength[3], rssi_db);\n\tPHYDM_DBG(dm, DBG_TMP, \"rssi_acc = %d, rssi=%d\\n\",\n\t\t  rssi_t->rssi_acc, rssi_t->rssi);\n\t#endif\n\n\tif (pktinfo->is_cck_rate)\n\t\trssi_t->rssi_cck = (s8)rssi_db;\n\telse\n\t\trssi_t->rssi_ofdm = (s8)rssi_db;\n}\n\nvoid phydm_rx_physts_2nd_type(void *dm_void, u8 *phy_sts,\n\t\t\t      struct phydm_perpkt_info_struct *pktinfo,\n\t\t\t      struct phydm_phyinfo_struct *phy_info)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#ifdef PHYDM_PHYSTAUS_SMP_MODE\n\tstruct pkt_process_info *pkt_process = &dm->pkt_proc_struct;\n#endif\n\tu8 page = (*phy_sts & 0xf);\n\n#ifdef PHYDM_PHYSTAUS_SMP_MODE\n\tif (pkt_process->phystatus_smp_mode_en && page != 0) {\n\t\tif (pkt_process->pre_ppdu_cnt == pktinfo->ppdu_cnt)\n\t\t\treturn;\n\n\t\tpkt_process->pre_ppdu_cnt = pktinfo->ppdu_cnt;\n\t}\n#endif\n\n\tphydm_reset_phy_info(dm, phy_info); /* @Memory reset */\n\n\t/* Phy status parsing */\n\tswitch (page) {\n\tcase 0: /*@CCK*/\n\t\tphydm_get_phy_sts_type0(dm, phy_sts, pktinfo, phy_info);\n\t\tbreak;\n\tcase 1:\n\t\tphydm_get_phy_sts_type1(dm, phy_sts, pktinfo, phy_info);\n\t\tbreak;\n\tcase 2:\n\t\tphydm_get_phy_sts_type2(dm, phy_sts, pktinfo, phy_info);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT)\n\tif (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B))\n\t\tphydm_print_phy_sts_jgr2(dm, phy_sts, pktinfo, phy_info);\n#endif\n}\n\n/*@==============================================*/\n#endif\n\nvoid odm_phy_status_query(struct dm_struct *dm,\n\t\t\t  struct phydm_phyinfo_struct *phy_info,\n\t\t\t  u8 *phy_status_inf,\n\t\t\t  struct phydm_perpkt_info_struct *pktinfo)\n{\n\tu8 rate = pktinfo->data_rate;\n\n\tpktinfo->is_cck_rate = (rate <= ODM_RATE11M) ? true : false;\n\tpktinfo->rate_ss = phydm_rate_to_num_ss(dm, rate);\n\tdm->rate_ss = pktinfo->rate_ss; /*@For AP EVM SW antenna diversity use*/\n\n\tif (pktinfo->is_cck_rate)\n\t\tdm->phy_dbg_info.num_qry_phy_status_cck++;\n\telse\n\t\tdm->phy_dbg_info.num_qry_phy_status_ofdm++;\n\n\t/*Reset phy_info*/\n\todm_memory_set(dm, phy_info->rx_mimo_signal_strength, 0, 4);\n\todm_memory_set(dm, phy_info->rx_mimo_signal_quality, 0, 4);\n\tif (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) {\n\t\t#ifdef PHYSTS_3RD_TYPE_SUPPORT\n\t\tphydm_rx_physts_3rd_type(dm, phy_status_inf, pktinfo, phy_info);\n\t\tphydm_process_dm_rssi_3rd_type(dm, phy_info, pktinfo);\n\t\t#endif\n\t} else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) {\n\t\t#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)\n\t\tphydm_rx_physts_2nd_type(dm, phy_status_inf, pktinfo, phy_info);\n\t\tphydm_process_rssi_for_dm_2nd_type(dm, phy_info, pktinfo);\n\t\t#endif\n\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\t#if ODM_IC_11AC_SERIES_SUPPORT\n\t\tphydm_rx_physts_1st_type(dm, phy_info, phy_status_inf, pktinfo);\n\t\tphydm_process_rssi_for_dm(dm, phy_info, pktinfo);\n\t\t#endif\n\t} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\t#if ODM_IC_11N_SERIES_SUPPORT\n\t\tphydm_phy_sts_n_parsing(dm, phy_info, phy_status_inf, pktinfo);\n\t\tphydm_process_rssi_for_dm(dm, phy_info, pktinfo);\n\t\t#endif\n\t}\n\tphy_info->signal_strength = phy_info->rx_pwdb_all;\n\t#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tphydm_process_signal_strength(dm, phy_info, pktinfo);\n\t#endif\n\n\t/*For basic debug message*/\n\tif (pktinfo->is_packet_match_bssid || pktinfo->is_packet_beacon ||\n\t    *dm->mp_mode) {\n\t\tdm->curr_station_id = pktinfo->station_id;\n\t\tdm->rx_rate = rate;\n\t\tdm->rssi_a = phy_info->rx_mimo_signal_strength[RF_PATH_A];\n\t\tdm->rssi_b = phy_info->rx_mimo_signal_strength[RF_PATH_B];\n\t\tdm->rssi_c = phy_info->rx_mimo_signal_strength[RF_PATH_C];\n\t\tdm->rssi_d = phy_info->rx_mimo_signal_strength[RF_PATH_D];\n\n\t\tif (rate >= ODM_RATE6M && rate <= ODM_RATE54M)\n\t\t\tdm->rxsc_l = (s8)phy_info->rxsc;\n\t\telse if (phy_info->band_width == CHANNEL_WIDTH_20)\n\t\t\tdm->rxsc_20 = (s8)phy_info->rxsc;\n\t\telse if (phy_info->band_width == CHANNEL_WIDTH_40)\n\t\t\tdm->rxsc_40 = (s8)phy_info->rxsc;\n\t\telse if (phy_info->band_width == CHANNEL_WIDTH_80)\n\t\t\tdm->rxsc_80 = (s8)phy_info->rxsc;\n\n\t\tphydm_avg_phystatus_index(dm, phy_info, pktinfo);\n\t\tphydm_rx_statistic_cal(dm, phy_info, phy_status_inf, pktinfo);\n\t}\n}\n\nvoid phydm_rx_phy_status_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;\n#ifdef PHYDM_PHYSTAUS_SMP_MODE\n\tstruct pkt_process_info *pkt_process = &dm->pkt_proc_struct;\n\n\tif (dm->support_ic_type & ODM_RTL8822B) {\n\t\tpkt_process->phystatus_smp_mode_en = 1;\n\t\tpkt_process->pre_ppdu_cnt = 0xff;\n\t\t/*phystatus sampling mode enable*/\n\t\todm_set_mac_reg(dm, R_0x60f, BIT(7), 1);\n\t\t/*@First update timming*/\n\t\todm_set_bb_reg(dm, R_0x9e4, 0x3ff, 0x0);\n\t\t/*Update Sampling time*/\n\t\todm_set_bb_reg(dm, R_0x9e4, 0xfc00, 0x0);\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\t/*@First update timming*/\n\t\todm_set_bb_reg(dm, R_0x8c0, 0x3ff0, 0x0);\n\t\t/*Update Sampling time*/\n\t\todm_set_bb_reg(dm, R_0x8c0, 0xfc000, 0x0);\n\t}\n#endif\n\n\tdbg->show_phy_sts_all_pkt = 0;\n\tdbg->show_phy_sts_max_cnt = 1;\n\tdbg->show_phy_sts_cnt = 0;\n\n\tphydm_avg_phystatus_init(dm);\n}\n"
  },
  {
    "path": "hal/phydm/phydm_phystatus.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDM_PHYSTATUS_H__\n#define __PHYDM_PHYSTATUS_H__\n\n/*@--------------------------Define ------------------------------------------*/\n#define CCK_RSSI_INIT_COUNT 5\n\n#define RA_RSSI_STATE_INIT 0\n#define RA_RSSI_STATE_SEND 1\n#define RA_RSSI_STATE_HOLD 2\n\n#if defined(DM_ODM_CE_MAC80211)\n#define CFO_HW_RPT_2_KHZ(val) ({\t\t\\\n\ts32 cfo_hw_rpt_2_khz_tmp = (val);\t\\\n\t(cfo_hw_rpt_2_khz_tmp << 1) + (cfo_hw_rpt_2_khz_tmp >> 1);\t\\\n\t})\n#else\n#define CFO_HW_RPT_2_KHZ(val) ((val << 1) + (val >> 1))\n#endif\n\n/* @(X* 312.5 Khz)>>7 ~=  X*2.5 Khz= (X<<1 + X>>1)Khz  */\n\n#define IGI_2_RSSI(igi) (igi - 10)\n\n#define PHY_STATUS_JRGUAR2_DW_LEN 7 /* @7*4 = 28 Byte */\n#define PHY_STATUS_JRGUAR3_DW_LEN 7 /* @7*4 = 28 Byte */\n#define SHOW_PHY_STATUS_UNLIMITED 0\n#define RSSI_MA 4 /*moving average factor for RSSI: 2^4=16 */\n\n#define PHYSTS_PATH_NUM 4\n\n/*@************************************************************\n * structure and define\n ************************************************************/\n\n__PACK struct phy_rx_agc_info {\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 gain : 7, trsw : 1;\n#else\n\tu8 trsw : 1, gain : 7;\n#endif\n};\n\n__PACK struct phy_status_rpt_8192cd {\n\tstruct phy_rx_agc_info path_agc[2];\n\tu8\tch_corr[2];\n\tu8\tcck_sig_qual_ofdm_pwdb_all;\n\tu8\tcck_agc_rpt_ofdm_cfosho_a;\n\tu8\tcck_rpt_b_ofdm_cfosho_b;\n\tu8\trsvd_1;/*@ch_corr_msb;*/\n\tu8\tnoise_power_db_msb;\n\ts8\tpath_cfotail[2];\n\tu8\tpcts_mask[2];\n\ts8\tstream_rxevm[2];\n\tu8\tpath_rxsnr[2];\n\tu8\tnoise_power_db_lsb;\n\tu8\trsvd_2[3];\n\tu8\tstream_csi[2];\n\tu8\tstream_target_csi[2];\n\ts8\tsig_evm;\n\tu8\trsvd_3;\n\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8\tantsel_rx_keep_2: 1;\t/*@ex_intf_flg:1;*/\n\tu8\tsgi_en: 1;\n\tu8\trxsc: 2;\n\tu8\tidle_long: 1;\n\tu8\tr_ant_train_en: 1;\n\tu8\tant_sel_b: 1;\n\tu8\tant_sel: 1;\n#else\t/*@_BIG_ENDIAN_\t*/\n\tu8\tant_sel: 1;\n\tu8\tant_sel_b: 1;\n\tu8\tr_ant_train_en: 1;\n\tu8\tidle_long: 1;\n\tu8\trxsc: 2;\n\tu8\tsgi_en: 1;\n\tu8\tantsel_rx_keep_2: 1;/*@ex_intf_flg:1;*/\n#endif\n};\n\nstruct phy_status_rpt_8812 {\n\t/*\t@DWORD 0*/\n\tu8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/\n\tu8 chl_num_LSB; /*@channel number[7:0]*/\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 chl_num_MSB : 2; /*@channel number[9:8]*/\n\tu8 sub_chnl : 4; /*sub-channel location[3:0]*/\n\tu8 r_RFMOD : 2; /*RF mode[1:0]*/\n#else /*@_BIG_ENDIAN_\t*/\n\tu8 r_RFMOD : 2;\n\tu8 sub_chnl : 4;\n\tu8 chl_num_MSB : 2;\n#endif\n\n\t/*\t@DWORD 1*/\n\tu8 pwdb_all; /*@CCK signal quality / OFDM pwdb all*/\n\ts8 cfosho[2]; /*@CCK AGC report and CCK_BB_Power*/\n\t\t      /*OFDM path-A and path-B short CFO*/\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 resvd_0 : 6;\n\tu8 bt_RF_ch_MSB : 2; /*@8812A:2'b0  8814A: bt rf channel keep[7:6]*/\n#else /*@_BIG_ENDIAN_*/\n\tu8 bt_RF_ch_MSB : 2;\n\tu8 resvd_0 : 6;\n#endif\n\n/*\t@DWORD 2*/\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 ant_div_sw_a : 1; /*@8812A: ant_div_sw_a    8814A: 1'b0*/\n\tu8 ant_div_sw_b : 1; /*@8812A: ant_div_sw_b    8814A: 1'b0*/\n\tu8 bt_RF_ch_LSB : 6; /*@8812A: 6'b0     8814A: bt rf channel keep[5:0]*/\n#else /*@_BIG_ENDIAN_\t*/\n\tu8 bt_RF_ch_LSB : 6;\n\tu8 ant_div_sw_b : 1;\n\tu8 ant_div_sw_a : 1;\n#endif\n\ts8 cfotail[2]; /*@DW2 byte 1 DW2 byte 2\tpath-A and path-B CFO tail*/\n\tu8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/\n\tu8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/\n\n\t/*\t@DWORD 3*/\n\ts8 rxevm[2]; /*@DW3 byte 1 DW3 byte 2\tstream 1 and stream 2 RX EVM*/\n\ts8 rxsnr[2]; /*@DW3 byte 3 DW4 byte 0\tpath-A and path-B RX SNR*/\n\n\t/*\t@DWORD 4*/\n\tu8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 PCTS_MSK_RPT_3 : 6; /*PCTS mask report[29:24]*/\n\tu8 pcts_rpt_valid : 1; /*pcts_rpt_valid*/\n\tu8 resvd_1 : 1; /*@1'b0*/\n#else /*@_BIG_ENDIAN_*/\n\tu8 resvd_1 : 1;\n\tu8 pcts_rpt_valid : 1;\n\tu8 PCTS_MSK_RPT_3 : 6;\n#endif\n\ts8 rxevm_cd[2]; /*@8812A: 16'b0*/\n\t\t\t/*@8814A: stream 3 and stream 4 RX EVM*/\n\t/*\t@DWORD 5*/\n\tu8 csi_current[2]; /*@8812A: stream 1 and 2 CSI*/\n\t\t\t   /*@8814A:  path-C and path-D RX SNR*/\n\tu8 gain_trsw_cd[2]; /*path-C and path-D {TRSW, gain[6:0] }*/\n\n\t/*\t@DWORD 6*/\n\ts8 sigevm; /*signal field EVM*/\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 antidx_antc : 3;\t/*@8812A: 3'b0\t8814A: antidx_antc[2:0]*/\n\tu8 antidx_antd : 3;\t/*@8812A: 3'b0\t8814A: antidx_antd[2:0]*/\n\tu8 dpdt_ctrl_keep : 1;\t/*@8812A: 1'b0\t8814A: dpdt_ctrl_keep*/\n\tu8 GNT_BT_keep : 1;\t/*@8812A: 1'b0\t8814A: GNT_BT_keep*/\n#else /*@_BIG_ENDIAN_*/\n\tu8 GNT_BT_keep : 1;\n\tu8 dpdt_ctrl_keep : 1;\n\tu8 antidx_antd : 3;\n\tu8 antidx_antc : 3;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 antidx_anta : 3; /*@antidx_anta[2:0]*/\n\tu8 antidx_antb : 3; /*@antidx_antb[2:0]*/\n\tu8 hw_antsw_occur : 2; /*@1'b0*/\n#else /*@_BIG_ENDIAN_*/\n\tu8 hw_antsw_occur : 2;\n\tu8 antidx_antb : 3;\n\tu8 antidx_anta : 3;\n#endif\n};\n\n#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)\n\n__PACK struct phy_sts_rpt_jgr2_type0 {\n\t/* @DW0 */\n\tu8 page_num;\n\tu8 pwdb;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 gain : 6;\n\tu8 rsvd_0 : 1;\n\tu8 trsw : 1;\n#else\n\tu8 trsw : 1;\n\tu8 rsvd_0 : 1;\n\tu8 gain : 6;\n#endif\n\tu8 rsvd_1;\n\n\t/* @DW1 */\n\tu8 rsvd_2;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 rxsc : 4;\n\tu8 agc_table : 4;\n#else\n\tu8 agc_table : 4;\n\tu8 rxsc : 4;\n#endif\n\tu8 channel;\n\tu8 band;\n\n\t/* @DW2 */\n\tu16 length;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 antidx_a : 3;\n\tu8 antidx_b : 3;\n\tu8 rsvd_3 : 2;\n\tu8 antidx_c : 3;\n\tu8 antidx_d : 3;\n\tu8 rsvd_4 : 2;\n#else\n\tu8 rsvd_3 : 2;\n\tu8 antidx_b : 3;\n\tu8 antidx_a : 3;\n\tu8 rsvd_4 : 2;\n\tu8 antidx_d : 3;\n\tu8 antidx_c : 3;\n#endif\n\n\t/* @DW3 */\n\tu8 signal_quality;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 vga : 5;\n\tu8 lna_l : 3;\n\tu8 bb_power : 6;\n\tu8 rsvd_9 : 1;\n\tu8 lna_h : 1;\n#else\n\tu8 lna_l : 3;\n\tu8 vga : 5;\n\tu8 lna_h : 1;\n\tu8 rsvd_9 : 1;\n\tu8 bb_power : 6;\n#endif\n\tu8 rsvd_5;\n\n\t/* @DW4 */\n\tu32 rsvd_6;\n\n\t/* @DW5 */\n\tu32 rsvd_7;\n\n\t/* @DW6 */\n\tu32 rsvd_8;\n};\n\n__PACK struct phy_sts_rpt_jgr2_type1 {\n\t/* @DW0 and DW1 */\n\tu8 page_num;\n\tu8 pwdb[4];\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 l_rxsc : 4;\n\tu8 ht_rxsc : 4;\n#else\n\tu8 ht_rxsc : 4;\n\tu8 l_rxsc : 4;\n#endif\n\tu8 channel;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 band : 2;\n\tu8 rsvd_0 : 1;\n\tu8 hw_antsw_occu : 1;\n\tu8 gnt_bt : 1;\n\tu8 ldpc : 1;\n\tu8 stbc : 1;\n\tu8 beamformed : 1;\n#else\n\tu8 beamformed : 1;\n\tu8 stbc : 1;\n\tu8 ldpc : 1;\n\tu8 gnt_bt : 1;\n\tu8 hw_antsw_occu : 1;\n\tu8 rsvd_0 : 1;\n\tu8 band : 2;\n#endif\n\n\t/* @DW2 */\n\tu16 lsig_length;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 antidx_a : 3;\n\tu8 antidx_b : 3;\n\tu8 rsvd_1 : 2;\n\tu8 antidx_c : 3;\n\tu8 antidx_d : 3;\n\tu8 rsvd_2 : 2;\n#else\n\tu8 rsvd_1 : 2;\n\tu8 antidx_b : 3;\n\tu8 antidx_a : 3;\n\tu8 rsvd_2 : 2;\n\tu8 antidx_d : 3;\n\tu8 antidx_c : 3;\n#endif\n\n\t/* @DW3 */\n\tu8 paid;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 paid_msb : 1;\n\tu8 gid : 6;\n\tu8 rsvd_3 : 1;\n#else\n\tu8 rsvd_3 : 1;\n\tu8 gid : 6;\n\tu8 paid_msb : 1;\n#endif\n\tu8 intf_pos;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 intf_pos_msb : 1;\n\tu8 rsvd_4 : 2;\n\tu8 nb_intf_flag : 1;\n\tu8 rf_mode : 2;\n\tu8 rsvd_5 : 2;\n#else\n\tu8 rsvd_5 : 2;\n\tu8 rf_mode : 2;\n\tu8 nb_intf_flag : 1;\n\tu8 rsvd_4 : 2;\n\tu8 intf_pos_msb : 1;\n#endif\n\n\t/* @DW4 */\n\ts8 rxevm[4]; /* s(8,1) */\n\n\t/* @DW5 */\n\ts8 cfo_tail[4]; /* s(8,7) */\n\n\t/* @DW6 */\n\ts8 rxsnr[4]; /* s(8,1) */\n};\n\n__PACK struct phy_sts_rpt_jgr2_type2 {\n\t/* @DW0 ane DW1 */\n\tu8 page_num;\n\tu8 pwdb[4];\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 l_rxsc : 4;\n\tu8 ht_rxsc : 4;\n#else\n\tu8 ht_rxsc : 4;\n\tu8 l_rxsc : 4;\n#endif\n\tu8 channel;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 band : 2;\n\tu8 rsvd_0 : 1;\n\tu8 hw_antsw_occu : 1;\n\tu8 gnt_bt : 1;\n\tu8 ldpc : 1;\n\tu8 stbc : 1;\n\tu8 beamformed : 1;\n#else\n\tu8 beamformed : 1;\n\tu8 stbc : 1;\n\tu8 ldpc : 1;\n\tu8 gnt_bt : 1;\n\tu8 hw_antsw_occu : 1;\n\tu8 rsvd_0 : 1;\n\tu8 band : 2;\n#endif\n\n/* @DW2 */\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 shift_l_map : 6;\n\tu8 rsvd_1 : 2;\n#else\n\tu8 rsvd_1 : 2;\n\tu8 shift_l_map : 6;\n#endif\n\tu8 cnt_pw2cca;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 agc_table_a : 4;\n\tu8 agc_table_b : 4;\n\tu8 agc_table_c : 4;\n\tu8 agc_table_d : 4;\n#else\n\tu8 agc_table_b : 4;\n\tu8 agc_table_a : 4;\n\tu8 agc_table_d : 4;\n\tu8 agc_table_c : 4;\n#endif\n\n\t/* @DW3 ~ DW6*/\n\tu8 cnt_cca2agc_rdy;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 gain_a : 6;\n\tu8 rsvd_2 : 1;\n\tu8 trsw_a : 1;\n\tu8 gain_b : 6;\n\tu8 rsvd_3 : 1;\n\tu8 trsw_b : 1;\n\tu8 gain_c : 6;\n\tu8 rsvd_4 : 1;\n\tu8 trsw_c : 1;\n\tu8 gain_d : 6;\n\tu8 rsvd_5 : 1;\n\tu8 trsw_d : 1;\n\tu8 aagc_step_a : 2;\n\tu8 aagc_step_b : 2;\n\tu8 aagc_step_c : 2;\n\tu8 aagc_step_d : 2;\n#else\n\tu8 trsw_a : 1;\n\tu8 rsvd_2 : 1;\n\tu8 gain_a : 6;\n\tu8 trsw_b : 1;\n\tu8 rsvd_3 : 1;\n\tu8 gain_b : 6;\n\tu8 trsw_c : 1;\n\tu8 rsvd_4 : 1;\n\tu8 gain_c : 6;\n\tu8 trsw_d : 1;\n\tu8 rsvd_5 : 1;\n\tu8 gain_d : 6;\n\tu8 aagc_step_d : 2;\n\tu8 aagc_step_c : 2;\n\tu8 aagc_step_b : 2;\n\tu8 aagc_step_a : 2;\n#endif\n\tu8 ht_aagc_gain[4];\n\tu8 dagc_gain[4];\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 counter : 6;\n\tu8 rsvd_6 : 2;\n\tu8 syn_count : 5;\n\tu8 rsvd_7 : 3;\n#else\n\tu8 rsvd_6 : 2;\n\tu8 counter : 6;\n\tu8 rsvd_7 : 3;\n\tu8 syn_count : 5;\n#endif\n};\n#endif\n\n/*@==============================================*/\n#ifdef PHYSTS_3RD_TYPE_SUPPORT\n__PACK struct phy_sts_rpt_jgr3_type0 {\n/* @DW0 : Offset 0 */\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 page_num : 4;\n\tu8 pkt_cnt : 2;\n\tu8 channel_msb : 2;\n#else\n\tu8 channel_msb : 2;\n\tu8 pkt_cnt : 2;\n\tu8 page_num : 4;\n#endif\n\tu8 pwdb_a;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 gain_a : 6;\n\tu8 rsvd_0 : 1;\n\tu8 trsw : 1;\n#else\n\tu8 trsw : 1;\n\tu8 rsvd_0 : 1;\n\tu8 gain_a : 6;\n#endif\n\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 agc_table_b : 4;\n\tu8 agc_table_c : 4;\n#else\n\tu8 agc_table_c : 4;\n\tu8 agc_table_b : 4;\n#endif\n\n/* @DW1 : Offset 4 */\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 rsvd_1 : 4;\n\tu8 agc_table_d : 4;\n#else\n\tu8 agc_table_d : 4;\n\tu8 rsvd_1 : 4;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 l_rxsc : 4;\n\tu8 agc_table_a : 4;\n#else\n\tu8 agc_table_a : 4;\n\tu8 l_rxsc : 4;\n#endif\n\tu8 channel;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 band : 2;\n\tu8 rsvd_2_1 : 1;\n\tu8 hw_antsw_occur_keep_cck : 1;\n\tu8 gnt_bt_keep_cck : 1;\n\tu8 rsvd_2_2 : 1;\n\tu8 path_sel_o : 2;\n#else\n\tu8 path_sel_o : 2;\n\tu8 rsvd_2_2 : 1;\n\tu8 gnt_bt_keep_cck : 1;\n\tu8 hw_antsw_occur_keep_cck : 1;\n\tu8 rsvd_2_1 : 1;\n\tu8 band : 2;\n#endif\n\n\t/* @DW2 : Offset 8 */\n\tu16 length;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 antidx_a : 4;\n\tu8 antidx_b : 4;\n#else\n\tu8 antidx_b : 4;\n\tu8 antidx_a : 4;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 antidx_c : 4;\n\tu8 antidx_d : 4;\n#else\n\tu8 antidx_d : 4;\n\tu8 antidx_c : 4;\n#endif\n\n\t/* @DW3 : Offset 12 */\n\tu8 signal_quality;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 vga_a : 5;\n\tu8 lna_l_a : 3;\n#else\n\tu8 lna_l_a : 3;\n\tu8 vga_a : 5;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 bb_power_a : 6;\n\tu8 rsvd_3_1 : 1;\n\tu8 lna_h_a : 1;\n#else\n\n\tu8 lna_h_a : 1;\n\tu8 rsvd_3_1 : 1;\n\tu8 bb_power_a : 6;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 rxrate : 2;\n\tu8 raterr : 1;\n\tu8 lockbit : 1;\n\tu8 sqloss : 1;\n\tu8 mf_off : 1;\n\tu8 rsvd_3_2 : 2;\n#else\n\tu8 rsvd_3_2 : 2;\n\tu8 mf_off : 1;\n\tu8 sqloss : 1;\n\tu8 lockbit : 1;\n\tu8 raterr : 1;\n\tu8 rxrate : 2;\n#endif\n\n\t/* @DW4 : Offset 16 */\n\tu8 pwdb_b;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 vga_b : 5;\n\tu8 lna_l_b : 3;\n#else\n\tu8 lna_l_b : 3;\n\tu8 vga_b : 5;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 bb_power_b : 6;\n\tu8 rsvd_4_1 : 1;\n\tu8 lna_h_b : 1;\n#else\n\tu8 lna_h_b : 1;\n\tu8 rsvd_4_1 : 1;\n\tu8 bb_power_b : 6;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 gain_b : 6;\n\tu8 rsvd_4_2 : 2;\n#else\n\tu8 rsvd_4_2 : 2;\n\tu8 gain_b : 6;\n#endif\n\n\t/* @DW5 : Offset 20 */\n\tu8 pwdb_c;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 vga_c : 5;\n\tu8 lna_l_c : 3;\n#else\n\tu8 lna_l_c : 3;\n\tu8 vga_c : 5;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 bb_power_c : 6;\n\tu8 rsvd_5_1 : 1;\n\tu8 lna_h_c : 1;\n#else\n\tu8 lna_h_c : 1;\n\tu8 rsvd_5_1 : 1;\n\tu8 bb_power_c : 6;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 gain_c : 6;\n\tu8 rsvd_5_2 : 2;\n#else\n\tu8 rsvd_5_2 : 2;\n\tu8 gain_c : 6;\n#endif\n\n\t/* @DW6 : Offset 24 */\n\tu8 pwdb_d;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 vga_d : 5;\n\tu8 lna_l_d : 3;\n#else\n\tu8 lna_l_d : 3;\n\tu8 vga_d : 5;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 bb_power_d : 6;\n\tu8 rsvd_6_1 : 1;\n\tu8 lna_h_d : 1;\n#else\n\tu8 lna_h_d : 1;\n\tu8 rsvd_6_1 : 1;\n\tu8 bb_power_d : 6;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 gain_d : 6;\n\tu8 rsvd_6_2 : 2;\n#else\n\tu8 rsvd_6_2 : 2;\n\tu8 gain_d : 6;\n#endif\n};\n\n__PACK struct phy_sts_rpt_jgr3_type1 {\n/* @DW0 : Offset 0 */\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 page_num : 4;\n\tu8 pkt_cnt : 2;\n\tu8 channel_pri_msb : 2;\n#else\n\tu8 channel_pri_msb : 2;\n\tu8 pkt_cnt : 2;\n\tu8 page_num : 4;\n#endif\n\tu8 pwdb_a;\n\tu8 pwdb_b;\n\tu8 pwdb_c;\n\n\t/* @DW1 : Offset 4 */\n\tu8 pwdb_d;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 l_rxsc : 4;\n\tu8 ht_rxsc : 4;\n#else\n\tu8 ht_rxsc : 4;\n\tu8 l_rxsc : 4;\n#endif\n\tu8 channel_pri_lsb;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 band : 2;\n\tu8 rsvd_0 : 2;\n\tu8 gnt_bt : 1;\n\tu8 ldpc : 1;\n\tu8 stbc : 1;\n\tu8 beamformed : 1;\n#else\n\tu8 beamformed : 1;\n\tu8 stbc : 1;\n\tu8 ldpc : 1;\n\tu8 gnt_bt : 1;\n\tu8 rsvd_0 : 2;\n\tu8 band : 2;\n#endif\n\n\t/* @DW2 : Offset 8 */\n\tu8 channel_sec_lsb;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 channel_sec_msb : 2;\n\tu8 rsvd_1 : 2;\n\tu8 hw_antsw_occur_a : 1;\n\tu8 hw_antsw_occur_b : 1;\n\tu8 hw_antsw_occur_c : 1;\n\tu8 hw_antsw_occur_d : 1;\n#else\n\tu8 hw_antsw_occur_d : 1;\n\tu8 hw_antsw_occur_c : 1;\n\tu8 hw_antsw_occur_b : 1;\n\tu8 hw_antsw_occur_a : 1;\n\tu8 rsvd_1 : 2;\n\tu8 channel_sec_msb : 2;\n\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 antidx_a : 4;\n\tu8 antidx_b : 4;\n#else\n\tu8 antidx_b : 4;\n\tu8 antidx_a : 4;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 antidx_c : 4;\n\tu8 antidx_d : 4;\n#else\n\tu8 antidx_d : 4;\n\tu8 antidx_c : 4;\n#endif\n\n\t/* @DW3 : Offset 12 */\n\tu8 paid;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 paid_msb : 1;\n\tu8 gid : 6;\n\tu8 rsvd_3 : 1;\n#else\n\tu8 rsvd_3 : 1;\n\tu8 gid : 6;\n\tu8 paid_msb : 1;\n#endif\n\tu16 rsvd_4;\n#if 0\n\t/*@\n\tu8\t\trsvd_4;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8\t\trsvd_5: 6;\n\tu8\t\trf_mode: 2;\n#else\n\tu8\t\trf_mode: 2;\n\tu8\t\trsvd_5: 6;\n#endif\n*/\n#endif\n\t/* @DW4 : Offset 16 */\n\ts8 rxevm[4]; /* s(8,1) */\n\n\t/* @DW5 : Offset 20 */\n\ts8 cfo_tail[4]; /* s(8,7) */\n\n\t/* @DW6 : Offset 24 */\n\ts8 rxsnr[4]; /* s(8,1) */\n};\n\n__PACK struct phy_sts_rpt_jgr3_type2_3 {\n/* Type2 is primary channel & type3 is secondary channel */\n/* @DW0 and DW1: Offest 0 and Offset 4 */\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 page_num : 4;\n\tu8 pkt_cnt : 2;\n\tu8 channel_msb : 2;\n#else\n\tu8 channel_msb : 2;\n\tu8 pkt_cnt : 2;\n\tu8 page_num : 4;\n#endif\n\tu8 pwdb[4];\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 l_rxsc : 4;\n\tu8 ht_rxsc : 4;\n#else\n\tu8 ht_rxsc : 4;\n\tu8 l_rxsc : 4;\n#endif\n\tu8 channel_lsb;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 band : 2;\n\tu8 rsvd_0 : 2;\n\tu8 gnt_bt : 1;\n\tu8 ldpc : 1;\n\tu8 stbc : 1;\n\tu8 beamformed : 1;\n#else\n\tu8 beamformed : 1;\n\tu8 stbc : 1;\n\tu8 ldpc : 1;\n\tu8 gnt_bt : 1;\n\tu8 rsvd_0 : 2;\n\tu8 band : 2;\n#endif\n\n/* @DW2 : Offset 8 */\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 shift_l_map : 6;\n\tu8 rsvd_1 : 2;\n#else\n\tu8 rsvd_1 : 2;\n\tu8 shift_l_map : 6;\n#endif\n\ts8 pwed_th; /* @dynamic energy threshold S(8,2) */\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 agc_table_a : 4;\n\tu8 agc_table_b : 4;\n#else\n\tu8 agc_table_b : 4;\n\tu8 agc_table_a : 4;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 agc_table_c : 4;\n\tu8 agc_table_d : 4;\n#else\n\tu8 agc_table_d : 4;\n\tu8 agc_table_c : 4;\n#endif\n\n\t/* @DW3 : Offset 12 */\n\tu8 cnt_cca2agc_rdy; /* Time(ns) = cnt_cca2agc_ready*25 */\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 mp_gain_a : 6;\n\tu8 mp_gain_b_lsb : 2;\n#else\n\tu8 mp_gain_b_lsb : 2;\n\tu8 mp_gain_a : 6;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 mp_gain_b_msb : 4;\n\tu8 mp_gain_c_lsb : 4;\n#else\n\tu8 mp_gain_c_lsb : 4;\n\tu8 mp_gain_b_msb : 4;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 mp_gain_c_msb : 2;\n\tu8 avg_noise_pwr_lsb : 4;\n\tu8 rsvd_3 : 2;\n\t/* u8\t\tr_rfmod:2; */\n#else\n\t/* u8\t\tr_rfmod:2; */\n\tu8 rsvd_3 : 2;\n\tu8 avg_noise_pwr_lsb : 4;\n\tu8 mp_gain_c_msb : 2;\n#endif\n\t/* @DW4 ~ 5: offset 16 ~20 */\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 mp_gain_d : 6;\n\tu8 is_freq_select_fading : 1;\n\tu8 rsvd_2 : 1;\n#else\n\tu8 rsvd_2 : 1;\n\tu8 is_freq_select_fading : 1;\n\tu8 mp_gain_d : 6;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 aagc_step_a : 2;\n\tu8 aagc_step_b : 2;\n\tu8 aagc_step_c : 2;\n\tu8 aagc_step_d : 2;\n#else\n\tu8 aagc_step_d : 2;\n\tu8 aagc_step_c : 2;\n\tu8 aagc_step_b : 2;\n\tu8 aagc_step_a : 2;\n#endif\n\tu8 ht_aagc_gain[4];\n\tu8 dagc_gain[4];\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 counter : 6;\n\tu8 syn_count_lsb : 2;\n#else\n\tu8 syn_count_lsb : 2;\n\tu8 counter : 6;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 syn_count_msb : 3;\n\tu8 avg_noise_pwr_msb : 5;\n#else\n\tu8 avg_noise_pwr_msb : 5;\n\tu8 syn_count_msb : 3;\n#endif\n};\n\n__PACK struct phy_sts_rpt_jgr3_type4 {\n/* smart antenna */\n/* @DW0 and DW1 : offset 0 and 4  */\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 page_num : 4;\n\tu8 pkt_cnt : 2;\n\tu8 channel_msb : 2;\n#else\n\tu8 channel_msb : 2;\n\tu8 pkt_cnt : 2;\n\tu8 page_num : 4;\n#endif\n\tu8 pwdb[4];\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 l_rxsc : 4;\n\tu8 ht_rxsc : 4;\n#else\n\tu8 ht_rxsc : 4;\n\tu8 l_rxsc : 4;\n#endif\n\tu8 channel_lsb;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 band : 2;\n\tu8 rsvd_0 : 2;\n\tu8 gnt_bt : 1;\n\tu8 ldpc : 1;\n\tu8 stbc : 1;\n\tu8 beamformed : 1;\n#else\n\tu8 beamformed : 1;\n\tu8 stbc : 1;\n\tu8 ldpc : 1;\n\tu8 gnt_bt : 1;\n\tu8 rsvd_0 : 1;\n\tu8 band : 2;\n#endif\n\n/* @DW2 : offset 8 */\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 bad_tone_cnt_min_eign_0 : 4;\n\tu8 bad_tone_cnt_cn_excess_0 : 4;\n#else\n\tu8 bad_tone_cnt_cn_excess_0 : 4;\n\tu8 bad_tone_cnt_min_eign_0 : 4;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 training_done_a : 1;\n\tu8 training_done_b : 1;\n\tu8 training_done_c : 1;\n\tu8 training_done_d : 1;\n\tu8 hw_antsw_occur_a : 1;\n\tu8 hw_antsw_occur_b : 1;\n\tu8 hw_antsw_occur_c : 1;\n\tu8 hw_antsw_occur_d : 1;\n#else\n\tu8 hw_antsw_occur_d : 1;\n\tu8 hw_antsw_occur_c : 1;\n\tu8 hw_antsw_occur_b : 1;\n\tu8 hw_antsw_occur_a : 1;\n\tu8 training_done_d : 1;\n\tu8 training_done_c : 1;\n\tu8 training_done_b : 1;\n\tu8 training_done_a : 1;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 antidx_a : 4;\n\tu8 antidx_b : 4;\n#else\n\tu8 antidx_b : 4;\n\tu8 antidx_a : 4;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 antidx_c : 4;\n\tu8 antidx_d : 4;\n#else\n\tu8 antidx_d : 4;\n\tu8 antidx_c : 4;\n#endif\n/* @DW3 : offset 12 */\n\tu8 tx_pkt_cnt;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 bad_tone_cnt_min_eign_1 : 4;\n\tu8 bad_tone_cnt_cn_excess_1 : 4;\n#else\n\tu8 bad_tone_cnt_cn_excess_1 : 4;\n\tu8 bad_tone_cnt_min_eign_1 : 4;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 avg_cond_num_0 : 7;\n\tu8 avg_cond_num_1_lsb : 1;\n#else\n\tu8 avg_cond_num_1_lsb : 1;\n\tu8 avg_cond_num_0 : 7;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 avg_cond_num_1_msb : 6;\n\tu8 rsvd_1 : 2;\n#else\n\tu8 rsvd_1 : 2;\n\tu8 avg_cond_num_1_msb : 6;\n#endif\n\n\t/* @DW4 : offset 16 */\n\ts8 rxevm[4]; /* s(8,1) */\n\n\t/* @DW5 : offset 20 */\n\tu8 eigenvalue[4]; /* @eigenvalue or eigenvalue of seg0 (in dB) */\n\n\t/* @DW6 : ofset 24 */\n\ts8 rxsnr[4]; /* s(8,1) */\n};\n\n__PACK struct phy_sts_rpt_jgr3_type5 {\n/* @Debug */\n/* @DW0 ane DW1 : offset 0 and 4 */\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 page_num : 4;\n\tu8 pkt_cnt : 2;\n\tu8 channel_msb : 2;\n#else\n\tu8 channel_msb : 2;\n\tu8 pkt_cnt : 2;\n\tu8 page_num : 4;\n#endif\n\tu8 pwdb[4];\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 l_rxsc : 4;\n\tu8 ht_rxsc : 4;\n#else\n\tu8 ht_rxsc : 4;\n\tu8 l_rxsc : 4;\n#endif\n\tu8 channel_lsb;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 band : 2;\n\tu8 rsvd_0 : 2;\n\tu8 gnt_bt : 1;\n\tu8 ldpc : 1;\n\tu8 stbc : 1;\n\tu8 beamformed : 1;\n#else\n\tu8 beamformed : 1;\n\tu8 stbc : 1;\n\tu8 ldpc : 1;\n\tu8 gnt_bt : 1;\n\tu8 rsvd_0 : 2;\n\tu8 band : 2;\n#endif\n\t/* @DW2 : offset 8 */\n\tu8 rsvd_1;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 rsvd_2 : 4;\n\tu8 hw_antsw_occur_a : 1;\n\tu8 hw_antsw_occur_b : 1;\n\tu8 hw_antsw_occur_c : 1;\n\tu8 hw_antsw_occur_d : 1;\n#else\n\tu8 hw_antsw_occur_d : 1;\n\tu8 hw_antsw_occur_c : 1;\n\tu8 hw_antsw_occur_b : 1;\n\tu8 hw_antsw_occur_a : 1;\n\tu8 rsvd_2 : 4;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 antidx_a : 4;\n\tu8 antidx_b : 4;\n#else\n\tu8 antidx_b : 4;\n\tu8 antidx_a : 4;\n#endif\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 antidx_c : 4;\n\tu8 antidx_d : 4;\n#else\n\tu8 antidx_d : 4;\n\tu8 antidx_c : 4;\n#endif\n\t/* @DW3 : offset 12 */\n\tu8 tx_pkt_cnt;\n#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)\n\tu8 inf_pos_0_A_flg : 1;\n\tu8 inf_pos_1_A_flg : 1;\n\tu8 inf_pos_0_B_flg : 1;\n\tu8 inf_pos_1_B_flg : 1;\n\tu8 inf_pos_0_C_flg : 1;\n\tu8 inf_pos_1_C_flg : 1;\n\tu8 inf_pos_0_D_flg : 1;\n\tu8 inf_pos_1_D_flg : 1;\n#else\n\tu8 inf_pos_1_D_flg : 1;\n\tu8 inf_pos_0_D_flg : 1;\n\tu8 inf_pos_1_C_flg : 1;\n\tu8 inf_pos_0_C_flg : 1;\n\tu8 inf_pos_1_B_flg : 1;\n\tu8 inf_pos_0_B_flg : 1;\n\tu8 inf_pos_1_A_flg : 1;\n\tu8 inf_pos_0_A_flg : 1;\n#endif\n\tu8 rsvd_3;\n\tu8 rsvd_4;\n\t/* @DW4 : offset 16 */\n\tu8 inf_pos_0_a;\n\tu8 inf_pos_1_a;\n\tu8 inf_pos_0_b;\n\tu8 inf_pos_1_b;\n\t/* @DW5 : offset 20 */\n\tu8 inf_pos_0_c;\n\tu8 inf_pos_1_c;\n\tu8 inf_pos_0_d;\n\tu8 inf_pos_1_d;\n};\n#endif /*@#ifdef PHYSTS_3RD_TYPE_SUPPORT*/\n\n#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)\nboolean\nphydm_query_is_mu_api(struct dm_struct *phydm, u8 ppdu_idx, u8 *p_data_rate,\n\t\t      u8 *p_gid);\n#endif\n\n#ifdef PHYSTS_3RD_TYPE_SUPPORT\nvoid phydm_rx_physts_3rd_type(void *dm_void, u8 *phy_sts,\n\t\t\t      struct phydm_perpkt_info_struct *pktinfo,\n\t\t\t      struct phydm_phyinfo_struct *phy_info);\n#endif\n\nvoid phydm_reset_phystatus_avg(struct dm_struct *dm);\n\nvoid phydm_reset_phystatus_statistic(struct dm_struct *dm);\n\nvoid phydm_reset_rssi_for_dm(struct dm_struct *dm, u8 station_id);\n\nvoid phydm_get_cck_rssi_table_from_reg(struct dm_struct *dm);\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid phydm_normal_driver_rx_sniffer(\n\tstruct dm_struct *dm,\n\tu8 *desc,\n\tPRT_RFD_STATUS rt_rfd_status,\n\tu8 *drv_info,\n\tu8 phy_status);\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\ns32 phydm_signal_scale_mapping(struct dm_struct *dm, s32 curr_sig);\n#endif\n\nvoid odm_phy_status_query(struct dm_struct *dm,\n\t\t\t  struct phydm_phyinfo_struct *phy_info,\n\t\t\t  u8 *phy_status_inf,\n\t\t\t  struct phydm_perpkt_info_struct *pktinfo);\n\nvoid phydm_rx_phy_status_init(void *dm_void);\n\n#endif /*@#ifndef\t__HALHWOUTSRC_H__*/\n"
  },
  {
    "path": "hal/phydm/phydm_pmac_tx_setting.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n ************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\nvoid phydm_start_cck_cont_tx_jgr3(void *dm_void,\n\t\t\t\t  struct phydm_pmac_info *tx_info)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;\n\tu8 rate = tx_info->tx_rate; /* @HW rate */\n\n\t/* @if CCK block on? */\n\tif (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))\n\t\todm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1);\n\n\t/* @Turn Off All Test mode */\n\todm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);\n\n\todm_set_bb_reg(dm, R_0x1a00, 0x3000, rate);\n\todm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2); /* @transmit mode */\n\todm_set_bb_reg(dm, R_0x1a00, 0x8, 0x1); /* @turn on scramble setting */\n\n\t/* @Fix rate selection issue */\n\todm_set_bb_reg(dm, R_0x1a70, 0x4000, 0x1);\n\t/* @set RX weighting for path I & Q to 0 */\n\todm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);\n\t/* @set loopback mode */\n\todm_set_bb_reg(dm, R_0x1c3c, 0x10, 0x1);\n\n\tpmac_tx->cck_cont_tx = true;\n\tpmac_tx->ofdm_cont_tx = false;\n}\n\nvoid phydm_stop_cck_cont_tx_jgr3(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;\n\n\tpmac_tx->cck_cont_tx = false;\n\tpmac_tx->ofdm_cont_tx = false;\n\n\todm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0); /* @normal mode */\n\todm_set_bb_reg(dm, R_0x1a00, 0x8, 0x1); /* @turn on scramble setting */\n\n\t/* @back to default */\n\todm_set_bb_reg(dm, R_0x1a70, 0x4000, 0x0);\n\todm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);\n\todm_set_bb_reg(dm, R_0x1c3c, 0x10, 0x0);\n\t/* @BB Reset */\n\todm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0);\n\todm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1);\n}\n\nvoid phydm_start_ofdm_cont_tx_jgr3(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;\n\n\t/* @1. if OFDM block on */\n\tif (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))\n\t\todm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1);\n\n\t/* @2. set CCK test mode off, set to CCK normal mode */\n\todm_set_bb_reg(dm, R_0x1a00, 0x3, 0);\n\n\t/* @3. turn on scramble setting */\n\todm_set_bb_reg(dm, R_0x1a00, 0x8, 1);\n\n\t/* @4. Turn On Continue Tx and turn off the other test modes. */\n\todm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x1);\n\n\tpmac_tx->cck_cont_tx = false;\n\tpmac_tx->ofdm_cont_tx = true;\n}\n\nvoid phydm_stop_ofdm_cont_tx_jgr3(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;\n\n\tpmac_tx->cck_cont_tx = false;\n\tpmac_tx->ofdm_cont_tx = false;\n\n\t/* @Turn Off All Test mode */\n\todm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);\n\n\t/* @Delay 10 ms */\n\tODM_delay_ms(10);\n\n\t/* @BB Reset */\n\todm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0);\n\todm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1);\n}\n\nvoid phydm_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,\n\t\t\t\tboolean en_pmac_tx, u8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;\n\tu8 start = RF_PATH_A, end = RF_PATH_A;\n\tu8 i = 0;\n\n\tswitch (path) {\n\tcase RF_PATH_A:\n\tcase RF_PATH_B:\n\tcase RF_PATH_C:\n\tcase RF_PATH_D:\n\t\tstart = path;\n\t\tend = path;\n\t\tbreak;\n\tcase RF_PATH_AB:\n\t\tstart = RF_PATH_A;\n\t\tend = RF_PATH_B;\n\t\tbreak;\n#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT)\n\tcase RF_PATH_AC:\n\t\tstart = RF_PATH_A;\n\t\tend = RF_PATH_C;\n\t\tbreak;\n\tcase RF_PATH_AD:\n\t\tstart = RF_PATH_A;\n\t\tend = RF_PATH_D;\n\t\tbreak;\n\tcase RF_PATH_BC:\n\t\tstart = RF_PATH_B;\n\t\tend = RF_PATH_C;\n\t\tbreak;\n\tcase RF_PATH_BD:\n\t\tstart = RF_PATH_B;\n\t\tend = RF_PATH_D;\n\t\tbreak;\n\tcase RF_PATH_CD:\n\t\tstart = RF_PATH_C;\n\t\tend = RF_PATH_D;\n\t\tbreak;\n\tcase RF_PATH_ABC:\n\t\tstart = RF_PATH_A;\n\t\tend = RF_PATH_C;\n\t\tbreak;\n\tcase RF_PATH_ABD:\n\t\tstart = RF_PATH_A;\n\t\tend = RF_PATH_D;\n\t\tbreak;\n\tcase RF_PATH_ACD:\n\t\tstart = RF_PATH_A;\n\t\tend = RF_PATH_D;\n\t\tbreak;\n\tcase RF_PATH_BCD:\n\t\tstart = RF_PATH_B;\n\t\tend = RF_PATH_D;\n\t\tbreak;\n\tcase RF_PATH_ABCD:\n\t\tstart = RF_PATH_A;\n\t\tend = RF_PATH_D;\n\t\tbreak;\n#endif\n\t}\n\n\tif (is_single_tone) {\n\t\tpmac_tx->tx_scailing = odm_get_bb_reg(dm, R_0x81c, MASKDWORD);\n\n\t\tif (!en_pmac_tx) {\n\t\t\tphydm_start_ofdm_cont_tx_jgr3(dm);\n\t\t\t/*SendPSPoll(pAdapter);*/\n\t\t}\n\n\t\todm_set_bb_reg(dm, R_0x1c68, BIT(24), 0x1); /* @Disable CCA */\n\n\t\tfor (i = start; i <= end; i++) {\n\t\t\t/* @Tx mode: RF0x00[19:16]=4'b0010 */\n\t\t\t/* @odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2); */\n\t\t\t/* @Lowest RF gain index: RF_0x0[4:0] = 0*/\n\t\t\todm_set_rf_reg(dm, i, RF_0x0, 0x1F, 0x0);\n\t\t\t/* @RF LO enabled */\n\t\t\todm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);\n\t\t}\n\t\t#if (RTL8814B_SUPPORT == 1)\n\t\tif (dm->support_ic_type & ODM_RTL8814B) {\n\t\t\t/* @Tx mode: RF0x00[19:16]=4'b0010 */\n\t\t\t/* config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,\n\t\t\t *\t\t\t\t0xF0000, 0x2);\n\t\t\t */\n\t\t\t/* @Lowest RF gain index: RF_0x0[4:0] = 0*/\n\t\t\tconfig_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,\n\t\t\t\t\t\t\t0x1F, 0x0);\n\t\t\t/* @RF LO enabled */\n\t\t\tconfig_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,\n\t\t\t\t\t\t\tBIT(1), 0x1);\n\t\t}\n\t\t#endif\n\t\todm_set_bb_reg(dm, R_0x81c, 0x001FC000, 0);\n\t} else {\n\t\tfor (i = start; i <= end; i++) {\n\t\t\t/* @RF LO disabled */\n\t\t\todm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);\n\t\t}\n\t\todm_set_bb_reg(dm, R_0x1c68, BIT(24), 0x0); /* @Enable CCA */\n\n\t\tif (!en_pmac_tx)\n\t\t\tphydm_stop_ofdm_cont_tx_jgr3(dm);\n\n\t\todm_set_bb_reg(dm, R_0x81c, MASKDWORD, pmac_tx->tx_scailing);\n\t}\n}\n\nvoid phydm_stop_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;\n\tu32 tmp = 0;\n\n\tif (tx_info->mode == CONT_TX) {\n\t\todm_set_bb_reg(dm, R_0x1e70, 0xf, 2); /* TX Stop */\n\t\tif (pmac_tx->is_cck_rate)\n\t\t\tphydm_stop_cck_cont_tx_jgr3(dm);\n\t\telse\n\t\t\tphydm_stop_ofdm_cont_tx_jgr3(dm);\n\t} else {\n\t\tif (pmac_tx->is_cck_rate) {\n\t\t\ttmp = odm_get_bb_reg(dm, R_0x2de4, MASKLWORD);\n\t\t\todm_set_bb_reg(dm, R_0x1e64, MASKLWORD, tmp + 50);\n\t\t}\n\t\todm_set_bb_reg(dm, R_0x1e70, 0xf, 2); /* TX Stop */\n\t}\n\n\tif (tx_info->mode == OFDM_SINGLE_TONE_TX) {\n\t\t/* Stop HW TX -> Stop Continuous TX -> Stop RF Setting */\n\t\tif (pmac_tx->is_cck_rate)\n\t\t\tphydm_stop_cck_cont_tx_jgr3(dm);\n\t\telse\n\t\t\tphydm_stop_ofdm_cont_tx_jgr3(dm);\n\n\t\tphydm_set_single_tone_jgr3(dm, false, true, pmac_tx->path);\n\t}\n}\n\nvoid phydm_set_mac_phy_txinfo_jgr3(void *dm_void,\n\t\t\t\t   struct phydm_pmac_info *tx_info)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;\n\tu32 tmp = 0;\n\n\todm_set_bb_reg(dm, R_0xa58, 0x003F8000, tx_info->tx_rate);\n\n\t/* @0x900[1] ndp_sound */\n\todm_set_bb_reg(dm, R_0x900, 0x2, tx_info->ndp_sound);\n\n\t/* @0x900[27:24] txsc [29:28] bw [31:30] m_stbc */\n\tif (dm->support_ic_type & ODM_RTL8812F) {\n\t\ttmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) |\n\t\t\t((tx_info->m_stbc) << 6);\n\t} else {\n\t\ttmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) |\n\t\t\t((tx_info->m_stbc - 1) << 6);\n\t}\n\todm_set_bb_reg(dm, R_0x900, 0xFF000000, tmp);\n\n\tif (pmac_tx->is_ofdm_rate) {\n\t\todm_set_bb_reg(dm, R_0x900, 0x1, 0);\n\t\todm_set_bb_reg(dm, R_0x900, 0x4, 0);\n\t} else if (pmac_tx->is_ht_rate) {\n\t\todm_set_bb_reg(dm, R_0x900, 0x1, 1);\n\t\todm_set_bb_reg(dm, R_0x900, 0x4, 0);\n\t} else if (pmac_tx->is_vht_rate) {\n\t\todm_set_bb_reg(dm, R_0x900, 0x1, 0);\n\t\todm_set_bb_reg(dm, R_0x900, 0x4, 1);\n\t}\n\n\ttmp = tx_info->packet_period; /* @for TX interval */\n\todm_set_bb_reg(dm, R_0x9b8, 0xffff0000, tmp);\n}\n\nvoid phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;\n\tu32 tmp = 0;\n\n\tif (pmac_tx->is_cck_rate)\n\t\treturn;\n\n\t/* @L-SIG */\n\todm_set_bb_reg(dm, R_0x1eb4, 0xfffff, tx_info->packet_count);\n\n\ttmp = BYTE_2_DWORD(0, tx_info->lsig[2], tx_info->lsig[1],\n\t\t\t   tx_info->lsig[0]);\n\todm_set_bb_reg(dm, R_0x908, 0xffffff, tmp);\n#if 0\n\t/* @0x924[7:0] = Data init octet */\n\ttmp = tx_info->packet_pattern;\n\todm_set_bb_reg(dm, R_0x924, 0xff, tmp);\n\n\tif (tx_info->packet_pattern == RANDOM_BY_PN32)\n\t\ttmp = 0x3;\n\telse\n\t\ttmp = 0x0;\n\n\todm_set_bb_reg(dm, R_0x914, 0x60000000, tmp);\n#endif\n\tif (pmac_tx->is_ht_rate) {\n\t/* @HT SIG */\n\t\ttmp = BYTE_2_DWORD(0, tx_info->ht_sig[2], tx_info->ht_sig[1],\n\t\t\t\t   tx_info->ht_sig[0]);\n\t\todm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp);\n\t\ttmp = BYTE_2_DWORD(0, tx_info->ht_sig[5], tx_info->ht_sig[4],\n\t\t\t\t   tx_info->ht_sig[3]);\n\t\todm_set_bb_reg(dm, R_0x910, 0xffffff, tmp);\n\t} else if (pmac_tx->is_vht_rate) {\n\t/* @VHT SIG A/B/serv_field/delimiter */\n\t\ttmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[2],\n\t\t\t\t   tx_info->vht_sig_a[1],\n\t\t\t\t   tx_info->vht_sig_a[0]);\n\t\todm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp);\n\t\ttmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[5],\n\t\t\t\t   tx_info->vht_sig_a[4],\n\t\t\t\t   tx_info->vht_sig_a[3]);\n\t\todm_set_bb_reg(dm, R_0x910, 0xffffff, tmp);\n\t\ttmp = BYTE_2_DWORD(tx_info->vht_sig_b[3], tx_info->vht_sig_b[2],\n\t\t\t\t   tx_info->vht_sig_b[1],\n\t\t\t\t   tx_info->vht_sig_b[0]);\n\t\todm_set_bb_reg(dm, R_0x914, 0x1FFFFFFF, tmp);\n\n\t\ttmp = tx_info->vht_sig_b_crc;\n\t\todm_set_bb_reg(dm, R_0x938, 0xff00, tmp);\n\n\t\ttmp = BYTE_2_DWORD(tx_info->vht_delimiter[3],\n\t\t\t\t   tx_info->vht_delimiter[2],\n\t\t\t\t   tx_info->vht_delimiter[1],\n\t\t\t\t   tx_info->vht_delimiter[0]);\n\t\todm_set_bb_reg(dm, R_0x940, MASKDWORD, tmp);\n\t}\n}\n\nvoid phydm_set_cck_preamble_hdr_jgr3(void *dm_void,\n\t\t\t\t     struct phydm_pmac_info *tx_info)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;\n\tu32 tmp = 0;\n\n\tif (!pmac_tx->is_cck_rate)\n\t\treturn;\n\n\ttmp = tx_info->packet_count | (tx_info->sfd << 16);\n\todm_set_bb_reg(dm, R_0x1e64, MASKDWORD, tmp);\n\ttmp = tx_info->signal_field | (tx_info->service_field << 8) |\n\t      (tx_info->length << 16);\n\todm_set_bb_reg(dm, R_0x1e68, MASKDWORD, tmp);\n\ttmp = BYTE_2_DWORD(0, 0, tx_info->crc16[1], tx_info->crc16[0]);\n\todm_set_bb_reg(dm, R_0x1e6c, 0xffff, tmp);\n\n\tif (tx_info->is_short_preamble)\n\t\todm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0);\n\telse\n\t\todm_set_bb_reg(dm, R_0x1e6c, BIT(16), 1);\n}\n\nvoid phydm_set_mode_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,\n\t\t\t enum phydm_pmac_mode mode)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;\n\n\tif (mode == CONT_TX) {\n\t\ttx_info->packet_count = 1;\n\n\t\tif (pmac_tx->is_cck_rate)\n\t\t\tphydm_start_cck_cont_tx_jgr3(dm, tx_info);\n\t\telse\n\t\t\tphydm_start_ofdm_cont_tx_jgr3(dm);\n\t} else if (mode == OFDM_SINGLE_TONE_TX) {\n\t\t/* Continuous TX -> HW TX -> RF Setting */\n\t\ttx_info->packet_count = 1;\n\n\t\tif (pmac_tx->is_cck_rate)\n\t\t\tphydm_start_cck_cont_tx_jgr3(dm, tx_info);\n\t\telse\n\t\t\tphydm_start_ofdm_cont_tx_jgr3(dm);\n\t} else if (mode == PKTS_TX) {\n\t\tif (pmac_tx->is_cck_rate && tx_info->packet_count == 0)\n\t\t\ttx_info->packet_count = 0xffff;\n\t}\n}\n\nvoid phydm_set_pmac_txon_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;\n\n\todm_set_bb_reg(dm, R_0x1d08, BIT(0), 1); /* Turn on PMAC */\n\n\t/* mac scramble seed setting, only in 8198F */\n\t#if (RTL8198F_SUPPORT)\n\t\tif (dm->support_ic_type & ODM_RTL8198F)\n\t\t\tif (!odm_get_bb_reg(dm, R_0x1d10, BIT(16)))\n\t\t\t\todm_set_bb_reg(dm, R_0x1d10, BIT(16), 1);\n\t#endif\n\n\tif (pmac_tx->is_cck_rate) {\n\t\todm_set_bb_reg(dm, R_0x1e70, 0xf, 8); /* TX CCK ON */\n\t\todm_set_bb_reg(dm, R_0x1a84, BIT(31), 0);\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x1e70, 0xf, 4); /* TX Ofdm ON */\n\t}\n\n\tif (tx_info->mode == OFDM_SINGLE_TONE_TX)\n\t\tphydm_set_single_tone_jgr3(dm, true, true, pmac_tx->path);\n}\n\nvoid phydm_set_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,\n\t\t\t    enum rf_path mpt_rf_path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;\n\n\tpmac_tx->is_cck_rate = phydm_is_cck_rate(dm, tx_info->tx_rate);\n\tpmac_tx->is_ofdm_rate = phydm_is_ofdm_rate(dm, tx_info->tx_rate);\n\tpmac_tx->is_ht_rate = phydm_is_ht_rate(dm, tx_info->tx_rate);\n\tpmac_tx->is_vht_rate = phydm_is_vht_rate(dm, tx_info->tx_rate);\n\tpmac_tx->path = mpt_rf_path;\n\n\tif (!tx_info->en_pmac_tx) {\n\t\tphydm_stop_pmac_tx_jgr3(dm, tx_info);\n\t\treturn;\n\t}\n\n\tphydm_set_mode_jgr3(dm, tx_info, tx_info->mode);\n\n\tif (pmac_tx->is_cck_rate)\n\t\tphydm_set_cck_preamble_hdr_jgr3(dm, tx_info);\n\telse\n\t\tphydm_set_sig_jgr3(dm, tx_info);\n\n\tphydm_set_mac_phy_txinfo_jgr3(dm, tx_info);\n\tphydm_set_pmac_txon_jgr3(dm, tx_info);\n}\n\nvoid phydm_set_tmac_tx_jgr3(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\t/* Turn on TMAC */\n\tif (odm_get_bb_reg(dm, R_0x1d08, BIT(0)))\n\t\todm_set_bb_reg(dm, R_0x1d08, BIT(0), 0);\n\n\t/* mac scramble seed setting, only in 8198F */\n\t#if (RTL8198F_SUPPORT == 1)\n\t\tif (dm->support_ic_type & ODM_RTL8198F)\n\t\t\tif (odm_get_bb_reg(dm, R_0x1d10, BIT(16)))\n\t\t\t\todm_set_bb_reg(dm, R_0x1d10, BIT(16), 0);\n\t#endif\n\n\t/* Turn on TMAC CCK */\n\tif ((odm_get_bb_reg(dm, R_0x1a84, BIT(31))) == 0)\n\t\todm_set_bb_reg(dm, R_0x1a84, BIT(31), 1);\n}\n#endif\n\nvoid phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tphydm_start_cck_cont_tx_jgr3(dm, tx_info);\n}\n\nvoid phydm_stop_cck_cont_tx(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tphydm_stop_cck_cont_tx_jgr3(dm);\n}\n\nvoid phydm_start_ofdm_cont_tx(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tphydm_start_ofdm_cont_tx_jgr3(dm);\n}\n\nvoid phydm_stop_ofdm_cont_tx(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tphydm_stop_ofdm_cont_tx_jgr3(dm);\n}\n\nvoid phydm_set_single_tone(void *dm_void, boolean is_single_tone,\n\t\t\t   boolean en_pmac_tx, u8 path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tphydm_set_single_tone_jgr3(dm, is_single_tone,\n\t\t\t\t\t   en_pmac_tx, path);\n}\n\nvoid phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,\n\t\t       enum rf_path mpt_rf_path)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tphydm_set_pmac_tx_jgr3(dm, tx_info, mpt_rf_path);\n}\n\nvoid phydm_set_tmac_tx(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tphydm_set_tmac_tx_jgr3(dm);\n}\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_pmac_tx_setting.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDM_PMAC_TX_SETTING_H__\n#define __PHYDM_PMAC_TX_SETTING_H__\n\n#define PMAC_TX_SETTING_VERSION \"1.3\"\n\n/* @1 ============================================================\n * 1  Definition\n * 1 ============================================================\n */\n#define RANDOM_BY_PN32 0x12\n/* @1 ============================================================\n * 1  structure\n * 1 ============================================================\n */\nstruct phydm_pmac_info {\n\tu8 en_pmac_tx:1; /*@ disable pmac 1: enable pmac */\n\tu8 mode:3; /*@ 0: Packet TX 3:Continuous TX */\n\t/* @u8 Ntx:4; */\n\tu8 tx_rate; /* @should be HW rate*/\n\t/* @u8 TX_RATE_HEX; */\n\tu8 tx_sc;\n\t/* @u8 bSGI:1; */\n\tu8 is_short_preamble:1;\n\t/* @u8 bSTBC:1; */\n\t/* @u8 bLDPC:1; */\n\tu8 ndp_sound:1;\n\tu8 bw:3; /* @0:20 1:40 2:80Mhz */\n\tu8 m_stbc; /* @bSTBC + 1 */\n\tu16 packet_period;\n\tu32 packet_count;\n\t/* @u32 PacketLength; */\n\tu8 packet_pattern;\n\tu16 sfd;\n\tu8 signal_field;\n\tu8 service_field;\n\tu16 length;\n\tu8 crc16[2];\n\tu8 lsig[3];\n\tu8 ht_sig[6];\n\tu8 vht_sig_a[6];\n\tu8 vht_sig_b[4];\n\tu8 vht_sig_b_crc;\n\tu8 vht_delimiter[4];\n\t/* @u8 mac_addr[6]; */\n};\n\nstruct phydm_pmac_tx {\n\tboolean is_cck_rate;\n\tboolean is_ofdm_rate;\n\tboolean is_ht_rate;\n\tboolean is_vht_rate;\n\tboolean cck_cont_tx;\n\tboolean ofdm_cont_tx;\n\tu8 path;\n\tu32 tx_scailing;\n};\n\n/* @1 ============================================================\n * 1  enumeration\n * 1 ============================================================\n */\n\nenum phydm_pmac_mode {\n\tNONE_TEST,\n\tPKTS_TX,\n\tPKTS_RX,\n\tCONT_TX,\n\tOFDM_SINGLE_TONE_TX,\n\tCCK_CARRIER_SIPPRESSION_TX\n};\n\n/* @1 ============================================================\n * 1  function prototype\n * 1 ============================================================\n */\nvoid phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info);\n\nvoid phydm_stop_cck_cont_tx(void *dm_void);\n\nvoid phydm_start_ofdm_cont_tx(void *dm_void);\n\nvoid phydm_stop_ofdm_cont_tx(void *dm_void);\n\nvoid phydm_set_single_tone(void *dm_void, boolean is_single_tone,\n\t\t\t   boolean en_pmac_tx, u8 path);\n\nvoid phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,\n\t\t       enum rf_path mpt_rf_path);\n\nvoid phydm_set_tmac_tx(void *dm_void);\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_pow_train.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*************************************************************\n * include files\n ************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#ifdef PHYDM_POWER_TRAINING_SUPPORT\nvoid phydm_reset_pt_para(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;\n\n\tpt_t->pow_train_score = 0;\n}\n\nvoid phydm_update_power_training_state(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;\n\tstruct phydm_fa_struct *fa_cnt = &dm->false_alm_cnt;\n\tstruct ccx_info *ccx = &dm->dm_ccx_info;\n\tu32 pt_score_tmp = ENABLE_PT_SCORE;\n\tu32 crc_ok_cnt = 0;\n\tu32 cca_cnt = 0;\n\n\t/*@is_disable_power_training is the key to H2C to disable/enable PT*/\n\t/*@if is_disable_power_training == 1, it will use largest power*/\n\tif (!(dm->support_ability & ODM_BB_PWR_TRAIN) || !dm->is_linked) {\n\t\tdm->is_disable_power_training = true;\n\t\tphydm_reset_pt_para(dm);\n\t\treturn;\n\t}\n\n\tPHYDM_DBG(dm, DBG_PWR_TRAIN, \"%s ======>\\n\", __func__);\n\n\tif (pt_t->pt_state == DISABLE_POW_TRAIN) {\n\t\tdm->is_disable_power_training = true;\n\t\tphydm_reset_pt_para(dm);\n\t\tPHYDM_DBG(dm, DBG_PWR_TRAIN, \"Disable PT\\n\");\n\t\treturn;\n\n\t} else if (pt_t->pt_state == ENABLE_POW_TRAIN) {\n\t\tdm->is_disable_power_training = false;\n\t\tphydm_reset_pt_para(dm);\n\t\tPHYDM_DBG(dm, DBG_PWR_TRAIN, \"Enable PT\\n\");\n\t\treturn;\n\n\t} else if (pt_t->pt_state == DYNAMIC_POW_TRAIN) {\n\t\tPHYDM_DBG(dm, DBG_PWR_TRAIN, \"Dynamic PT\\n\");\n\n\t\t/* @Compute score */\n\t\tcrc_ok_cnt = dm->phy_dbg_info.num_qry_phy_status_ofdm +\n\t\t\t     dm->phy_dbg_info.num_qry_phy_status_cck;\n\t\tcca_cnt = fa_cnt->cnt_cca_all;\n#if 0\n\t\tif (crc_ok_cnt > cca_cnt) { /*invalid situation*/\n\t\t\tpt_score_tmp = KEEP_PRE_PT_SCORE;\n\t\t\treturn;\n\t\t} else if ((crc_ok_cnt + (crc_ok_cnt >> 1)) <= cca_cnt) {\n\t\t/* @???crc_ok <= (2/3)*cca */\n\t\t\tpt_score_tmp = DISABLE_PT_SCORE;\n\t\t\tdm->is_disable_power_training = true;\n\t\t} else if ((crc_ok_cnt + (crc_ok_cnt >> 2)) <= cca_cnt) {\n\t\t/* @???crc_ok <= (4/5)*cca */\n\t\t\tpt_score_tmp = KEEP_PRE_PT_SCORE;\n\t\t} else {\n\t\t/* @???crc_ok > (4/5)*cca */\n\t\t\tpt_score_tmp = ENABLE_PT_SCORE;\n\t\t\tdm->is_disable_power_training = false;\n\t\t}\n#endif\n\t\tif (ccx->nhm_ratio > 10) {\n\t\t\tpt_score_tmp = DISABLE_PT_SCORE;\n\t\t\tdm->is_disable_power_training = true;\n\t\t} else if (ccx->nhm_ratio < 5) {\n\t\t\tpt_score_tmp = ENABLE_PT_SCORE;\n\t\t\tdm->is_disable_power_training = false;\n\t\t} else {\n\t\t\tpt_score_tmp = KEEP_PRE_PT_SCORE;\n\t\t}\n\n\t\tPHYDM_DBG(dm, DBG_PWR_TRAIN,\n\t\t\t  \"pkt_cnt{ofdm,cck,all} = {%d, %d, %d}, cnt_cca_all=%d\\n\",\n\t\t\t  dm->phy_dbg_info.num_qry_phy_status_ofdm,\n\t\t\t  dm->phy_dbg_info.num_qry_phy_status_cck,\n\t\t\t  crc_ok_cnt, cca_cnt);\n\n\t\tPHYDM_DBG(dm, DBG_PWR_TRAIN, \"pt_score_tmp=%d\\n\", pt_score_tmp);\n\n\t\t/* smoothing */\n\t\tpt_t->pow_train_score = (pt_score_tmp << 4) +\n\t\t\t\t\t(pt_t->pow_train_score >> 1) +\n\t\t\t\t\t(pt_t->pow_train_score >> 2);\n\n\t\tpt_score_tmp = (pt_t->pow_train_score + 32) >> 6;\n\n\t\tPHYDM_DBG(dm, DBG_PWR_TRAIN,\n\t\t\t  \"pow_train_score = %d, score after smoothing = %d, is_disable_PT = %d\\n\",\n\t\t\t  pt_t->pow_train_score, pt_score_tmp,\n\t\t\t  dm->is_disable_power_training);\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_PWR_TRAIN, \"[%s]warning\\n\", __func__);\n\t}\n}\n\nvoid phydm_pow_train_debug(\n\tvoid *dm_void,\n\tchar input[][16],\n\tu32 *_used,\n\tchar *output,\n\tu32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;\n\tchar help[] = \"-h\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 i;\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{0: Auto PT, 1:enable, 2: disable}\\n\");\n\t} else {\n\t\tfor (i = 0; i < 10; i++) {\n\t\t\tif (input[i + 1])\n\t\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);\n\t\t}\n\n\t\tif (var1[0] == 0)\n\t\t\tpt_t->pt_state = DYNAMIC_POW_TRAIN;\n\t\telse if (var1[0] == 1)\n\t\t\tpt_t->pt_state = ENABLE_POW_TRAIN;\n\t\telse if (var1[0] == 2)\n\t\t\tpt_t->pt_state = DISABLE_POW_TRAIN;\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"PT state = %d\\n\", pt_t->pt_state);\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_pow_train.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDM_POW_TRAIN_H__\n#define __PHYDM_POW_TRAIN_H__\n\n#define POW_TRAIN_VERSION \"1.0\" /* @2017.07.0141  Dino, Add phydm_pow_train.h*/\n\n/****************************************************************\n * 1 ============================================================\n * 1  Definition\n * 1 ============================================================\n ***************************************************************/\n\n#ifdef PHYDM_POWER_TRAINING_SUPPORT\n/****************************************************************\n * 1 ============================================================\n * 1  structure\n * 1 ============================================================\n ***************************************************************/\n\nstruct phydm_pow_train_stuc {\n\tu8 pt_state;\n\tu32 pow_train_score;\n};\n\n/****************************************************************\n * 1 ============================================================\n * 1  enumeration\n * 1 ============================================================\n ***************************************************************/\n\nenum pow_train_state {\n\tDYNAMIC_POW_TRAIN = 0,\n\tENABLE_POW_TRAIN = 1,\n\tDISABLE_POW_TRAIN = 2\n};\n\nenum power_training_score {\n\tDISABLE_PT_SCORE = 0,\n\tKEEP_PRE_PT_SCORE = 1,\n\tENABLE_PT_SCORE = 2\n};\n\n/****************************************************************\n * 1 ============================================================\n * 1  function prototype\n * 1 ============================================================\n ***************************************************************/\n\nvoid phydm_update_power_training_state(\n\tvoid *dm_void);\n\nvoid phydm_pow_train_debug(\n\tvoid *dm_void,\n\tchar input[][16],\n\tu32 *_used,\n\tchar *output,\n\tu32 *_out_len);\n\n#endif\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_pre_define.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDMPREDEFINE_H__\n#define __PHYDMPREDEFINE_H__\n\n/****************************************************************\n * 1 ============================================================\n * 1  Definition\n * 1 ============================================================\n ***************************************************************/\n\n#define PHYDM_CODE_BASE\t\t\t\"PHYDM_V35\"\n#define PHYDM_RELEASE_DATE\t\t\"20181109.0\"\n\n/*PHYDM API status*/\n#define\tPHYDM_SET_FAIL\t\t\t0\n#define\tPHYDM_SET_SUCCESS\t\t1\n#define\tPHYDM_SET_NO_NEED\t\t3\n\n/*PHYDM Set/Revert*/\n#define\tPHYDM_SET\t\t\t1\n#define\tPHYDM_REVERT\t\t\t2\n\n/* @Max path of IC */\n/*N-IC*/\n#define MAX_PATH_NUM_8188E\t\t1\n#define MAX_PATH_NUM_8188F\t\t1\n#define MAX_PATH_NUM_8710B\t\t1\n#define MAX_PATH_NUM_8723B\t\t1\n#define MAX_PATH_NUM_8723D\t\t1\n#define MAX_PATH_NUM_8703B\t\t1\n#define MAX_PATH_NUM_8192E\t\t2\n#define MAX_PATH_NUM_8192F\t\t2\n#define MAX_PATH_NUM_8197F\t\t2\n#define MAX_PATH_NUM_8198F\t\t4\n#define MAX_PATH_NUM_8197G\t\t2\n#define MAX_PATH_NUM_8721D\t\t1\n/*@AC-IC*/\n#define MAX_PATH_NUM_8821A\t\t1\n#define MAX_PATH_NUM_8881A\t\t1\n#define MAX_PATH_NUM_8821C\t\t1\n#define MAX_PATH_NUM_8195B\t\t1\n#define MAX_PATH_NUM_8812A\t\t2\n#define MAX_PATH_NUM_8822B\t\t2\n#define MAX_PATH_NUM_8822C\t\t2\n#define MAX_PATH_NUM_8814A\t\t4\n#define MAX_PATH_NUM_8814B\t\t4\n#define MAX_PATH_NUM_8814C\t\t4\n#define MAX_PATH_NUM_8195B\t\t1\n#define MAX_PATH_NUM_8812F\t\t2\n\n/* @Max RF path */\n#define PHYDM_MAX_RF_PATH_N\t\t2\t/*@For old N-series IC*/\n#define PHYDM_MAX_RF_PATH\t\t4\n\n/* number of entry */\n#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))\n\t#ifdef DM_ODM_CE_MAC80211\n\t\t/* @defined in wifi.h (32+1) */\n\t#else\n\t\t#define\tASSOCIATE_ENTRY_NUM\tMACID_NUM_SW_LIMIT  /* @Max size of asoc_entry[].*/\n\t#endif\n\t#define\tODM_ASSOCIATE_ENTRY_NUM\tASSOCIATE_ENTRY_NUM\n#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\t#define ASSOCIATE_ENTRY_NUM\tNUM_STAT\n\t#define\tODM_ASSOCIATE_ENTRY_NUM\t(ASSOCIATE_ENTRY_NUM + 1)\n#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))\n\t#ifdef CONFIG_CONCURRENT_MODE\n\t\t#define ASSOCIATE_ENTRY_NUM\tNUM_STA + 2 /*@2 is for station mod*/\n\t#else\n\t\t#define ASSOCIATE_ENTRY_NUM\tNUM_STA /*@8 is for max size of asoc_entry[].*/\n\t#endif\n\t#define\tODM_ASSOCIATE_ENTRY_NUM\tASSOCIATE_ENTRY_NUM\n#else\n\t#define ODM_ASSOCIATE_ENTRY_NUM\t(((ASSOCIATE_ENTRY_NUM + 1) * 3) + 1)\n#endif\n\n/* @-----MGN rate--------------------------------- */\n\nenum PDM_RATE_TYPE {\n\tPDM_1SS\t\t\t= 1,\t/*VHT/HT 1SS*/\n\tPDM_2SS\t\t\t= 2,\t/*VHT/HT 2SS*/\n\tPDM_3SS\t\t\t= 3,\t/*VHT/HT 3SS*/\n\tPDM_4SS\t\t\t= 4,\t/*VHT/HT 4SS*/\n\tPDM_CCK\t\t\t= 11,\t/*@B*/\n\tPDM_OFDM\t\t= 12\t/*@G*/\n};\n\nenum ODM_MGN_RATE {\n\tODM_MGN_1M\t\t= 0x02,\n\tODM_MGN_2M\t\t= 0x04,\n\tODM_MGN_5_5M\t\t= 0x0B,\n\tODM_MGN_6M\t\t= 0x0C,\n\tODM_MGN_9M\t\t= 0x12,\n\tODM_MGN_11M\t\t= 0x16,\n\tODM_MGN_12M\t\t= 0x18,\n\tODM_MGN_18M\t\t= 0x24,\n\tODM_MGN_24M\t\t= 0x30,\n\tODM_MGN_36M\t\t= 0x48,\n\tODM_MGN_48M\t\t= 0x60,\n\tODM_MGN_54M\t\t= 0x6C,\n\tODM_MGN_MCS32\t\t= 0x7F,\n\tODM_MGN_MCS0\t\t= 0x80,\n\tODM_MGN_MCS1,\n\tODM_MGN_MCS2,\n\tODM_MGN_MCS3,\n\tODM_MGN_MCS4,\n\tODM_MGN_MCS5,\n\tODM_MGN_MCS6,\n\tODM_MGN_MCS7\t\t= 0x87,\n\tODM_MGN_MCS8,\n\tODM_MGN_MCS9,\n\tODM_MGN_MCS10,\n\tODM_MGN_MCS11,\n\tODM_MGN_MCS12,\n\tODM_MGN_MCS13,\n\tODM_MGN_MCS14,\n\tODM_MGN_MCS15,\n\tODM_MGN_MCS16\t\t= 0x90,\n\tODM_MGN_MCS17,\n\tODM_MGN_MCS18,\n\tODM_MGN_MCS19,\n\tODM_MGN_MCS20,\n\tODM_MGN_MCS21,\n\tODM_MGN_MCS22,\n\tODM_MGN_MCS23,\n\tODM_MGN_MCS24\t\t= 0x98,\n\tODM_MGN_MCS25,\n\tODM_MGN_MCS26,\n\tODM_MGN_MCS27,\n\tODM_MGN_MCS28,\n\tODM_MGN_MCS29,\n\tODM_MGN_MCS30,\n\tODM_MGN_MCS31,\n\tODM_MGN_VHT1SS_MCS0\t= 0xa0,\n\tODM_MGN_VHT1SS_MCS1,\n\tODM_MGN_VHT1SS_MCS2,\n\tODM_MGN_VHT1SS_MCS3,\n\tODM_MGN_VHT1SS_MCS4,\n\tODM_MGN_VHT1SS_MCS5,\n\tODM_MGN_VHT1SS_MCS6,\n\tODM_MGN_VHT1SS_MCS7,\n\tODM_MGN_VHT1SS_MCS8,\n\tODM_MGN_VHT1SS_MCS9,\n\tODM_MGN_VHT2SS_MCS0\t= 0xaa,\n\tODM_MGN_VHT2SS_MCS1\t= 0xab,\n\tODM_MGN_VHT2SS_MCS2,\n\tODM_MGN_VHT2SS_MCS3,\n\tODM_MGN_VHT2SS_MCS4,\n\tODM_MGN_VHT2SS_MCS5\t= 0xaf,\n\tODM_MGN_VHT2SS_MCS6\t= 0xb0,\n\tODM_MGN_VHT2SS_MCS7,\n\tODM_MGN_VHT2SS_MCS8,\n\tODM_MGN_VHT2SS_MCS9\t= 0xb3,\n\tODM_MGN_VHT3SS_MCS0\t= 0xb4,\n\tODM_MGN_VHT3SS_MCS1,\n\tODM_MGN_VHT3SS_MCS2,\n\tODM_MGN_VHT3SS_MCS3,\n\tODM_MGN_VHT3SS_MCS4,\n\tODM_MGN_VHT3SS_MCS5,\n\tODM_MGN_VHT3SS_MCS6,\n\tODM_MGN_VHT3SS_MCS7\t= 0xbb,\n\tODM_MGN_VHT3SS_MCS8\t= 0xbc,\n\tODM_MGN_VHT3SS_MCS9\t= 0xbd,\n\tODM_MGN_VHT4SS_MCS0\t= 0xbe,\n\tODM_MGN_VHT4SS_MCS1,\n\tODM_MGN_VHT4SS_MCS2,\n\tODM_MGN_VHT4SS_MCS3,\n\tODM_MGN_VHT4SS_MCS4,\n\tODM_MGN_VHT4SS_MCS5,\n\tODM_MGN_VHT4SS_MCS6,\n\tODM_MGN_VHT4SS_MCS7,\n\tODM_MGN_VHT4SS_MCS8,\n\tODM_MGN_VHT4SS_MCS9\t= 0xc7,\n\tODM_MGN_UNKNOWN\n};\n\n#define\tODM_MGN_MCS0_SG\t\t0xc0\n#define\tODM_MGN_MCS1_SG\t\t0xc1\n#define\tODM_MGN_MCS2_SG\t\t0xc2\n#define\tODM_MGN_MCS3_SG\t\t0xc3\n#define\tODM_MGN_MCS4_SG\t\t0xc4\n#define\tODM_MGN_MCS5_SG\t\t0xc5\n#define\tODM_MGN_MCS6_SG\t\t0xc6\n#define\tODM_MGN_MCS7_SG\t\t0xc7\n#define\tODM_MGN_MCS8_SG\t\t0xc8\n#define\tODM_MGN_MCS9_SG\t\t0xc9\n#define\tODM_MGN_MCS10_SG\t0xca\n#define\tODM_MGN_MCS11_SG\t0xcb\n#define\tODM_MGN_MCS12_SG\t0xcc\n#define\tODM_MGN_MCS13_SG\t0xcd\n#define\tODM_MGN_MCS14_SG\t0xce\n#define\tODM_MGN_MCS15_SG\t0xcf\n\n/* @-----DESC rate--------------------------------- */\n\n#define ODM_RATEMCS15_SG\t0x1c\n#define ODM_RATEMCS32\t\t0x20\n\nenum phydm_ctrl_info_rate {\n\tODM_RATE1M\t\t= 0x00,\n\tODM_RATE2M\t\t= 0x01,\n\tODM_RATE5_5M\t\t= 0x02,\n\tODM_RATE11M\t\t= 0x03,\n/* OFDM Rates, TxHT = 0 */\n\tODM_RATE6M\t\t= 0x04,\n\tODM_RATE9M\t\t= 0x05,\n\tODM_RATE12M\t\t= 0x06,\n\tODM_RATE18M\t\t= 0x07,\n\tODM_RATE24M\t\t= 0x08,\n\tODM_RATE36M\t\t= 0x09,\n\tODM_RATE48M\t\t= 0x0A,\n\tODM_RATE54M\t\t= 0x0B,\n/* @MCS Rates, TxHT = 1 */\n\tODM_RATEMCS0\t\t= 0x0C,\n\tODM_RATEMCS1\t\t= 0x0D,\n\tODM_RATEMCS2\t\t= 0x0E,\n\tODM_RATEMCS3\t\t= 0x0F,\n\tODM_RATEMCS4\t\t= 0x10,\n\tODM_RATEMCS5\t\t= 0x11,\n\tODM_RATEMCS6\t\t= 0x12,\n\tODM_RATEMCS7\t\t= 0x13,\n\tODM_RATEMCS8\t\t= 0x14,\n\tODM_RATEMCS9\t\t= 0x15,\n\tODM_RATEMCS10\t\t= 0x16,\n\tODM_RATEMCS11\t\t= 0x17,\n\tODM_RATEMCS12\t\t= 0x18,\n\tODM_RATEMCS13\t\t= 0x19,\n\tODM_RATEMCS14\t\t= 0x1A,\n\tODM_RATEMCS15\t\t= 0x1B,\n\tODM_RATEMCS16\t\t= 0x1C,\n\tODM_RATEMCS17\t\t= 0x1D,\n\tODM_RATEMCS18\t\t= 0x1E,\n\tODM_RATEMCS19\t\t= 0x1F,\n\tODM_RATEMCS20\t\t= 0x20,\n\tODM_RATEMCS21\t\t= 0x21,\n\tODM_RATEMCS22\t\t= 0x22,\n\tODM_RATEMCS23\t\t= 0x23,\n\tODM_RATEMCS24\t\t= 0x24,\n\tODM_RATEMCS25\t\t= 0x25,\n\tODM_RATEMCS26\t\t= 0x26,\n\tODM_RATEMCS27\t\t= 0x27,\n\tODM_RATEMCS28\t\t= 0x28,\n\tODM_RATEMCS29\t\t= 0x29,\n\tODM_RATEMCS30\t\t= 0x2A,\n\tODM_RATEMCS31\t\t= 0x2B,\n\tODM_RATEVHTSS1MCS0\t= 0x2C,\n\tODM_RATEVHTSS1MCS1\t= 0x2D,\n\tODM_RATEVHTSS1MCS2\t= 0x2E,\n\tODM_RATEVHTSS1MCS3\t= 0x2F,\n\tODM_RATEVHTSS1MCS4\t= 0x30,\n\tODM_RATEVHTSS1MCS5\t= 0x31,\n\tODM_RATEVHTSS1MCS6\t= 0x32,\n\tODM_RATEVHTSS1MCS7\t= 0x33,\n\tODM_RATEVHTSS1MCS8\t= 0x34,\n\tODM_RATEVHTSS1MCS9\t= 0x35,\n\tODM_RATEVHTSS2MCS0\t= 0x36,\n\tODM_RATEVHTSS2MCS1\t= 0x37,\n\tODM_RATEVHTSS2MCS2\t= 0x38,\n\tODM_RATEVHTSS2MCS3\t= 0x39,\n\tODM_RATEVHTSS2MCS4\t= 0x3A,\n\tODM_RATEVHTSS2MCS5\t= 0x3B,\n\tODM_RATEVHTSS2MCS6\t= 0x3C,\n\tODM_RATEVHTSS2MCS7\t= 0x3D,\n\tODM_RATEVHTSS2MCS8\t= 0x3E,\n\tODM_RATEVHTSS2MCS9\t= 0x3F,\n\tODM_RATEVHTSS3MCS0\t= 0x40,\n\tODM_RATEVHTSS3MCS1\t= 0x41,\n\tODM_RATEVHTSS3MCS2\t= 0x42,\n\tODM_RATEVHTSS3MCS3\t= 0x43,\n\tODM_RATEVHTSS3MCS4\t= 0x44,\n\tODM_RATEVHTSS3MCS5\t= 0x45,\n\tODM_RATEVHTSS3MCS6\t= 0x46,\n\tODM_RATEVHTSS3MCS7\t= 0x47,\n\tODM_RATEVHTSS3MCS8\t= 0x48,\n\tODM_RATEVHTSS3MCS9\t= 0x49,\n\tODM_RATEVHTSS4MCS0\t= 0x4A,\n\tODM_RATEVHTSS4MCS1\t= 0x4B,\n\tODM_RATEVHTSS4MCS2\t= 0x4C,\n\tODM_RATEVHTSS4MCS3\t= 0x4D,\n\tODM_RATEVHTSS4MCS4\t= 0x4E,\n\tODM_RATEVHTSS4MCS5\t= 0x4F,\n\tODM_RATEVHTSS4MCS6\t= 0x50,\n\tODM_RATEVHTSS4MCS7\t= 0x51,\n\tODM_RATEVHTSS4MCS8\t= 0x52,\n\tODM_RATEVHTSS4MCS9\t= 0x53,\n};\n\n#define NUM_RATE_AC_4SS (ODM_RATEVHTSS4MCS9 + 1)\n#define NUM_RATE_AC_3SS (ODM_RATEVHTSS3MCS9 + 1)\n#define NUM_RATE_AC_2SS (ODM_RATEVHTSS2MCS9 + 1)\n#define NUM_RATE_AC_1SS (ODM_RATEVHTSS1MCS9 + 1)\n#define NUM_RATE_N_4SS (ODM_RATEMCS31 + 1)\n#define NUM_RATE_N_3SS (ODM_RATEMCS23 + 1)\n#define NUM_RATE_N_2SS (ODM_RATEMCS15 + 1)\n#define NUM_RATE_N_1SS (ODM_RATEMCS7 + 1)\n\n/*Define from larger rate size to small rate size, DO NOT change the position*/\n/*[AC-4SS]*/\n#if (RTL8814B_SUPPORT)\n\t#define PHY_NUM_RATE_IDX NUM_RATE_AC_4SS\n/*[AC-3SS]*/\n#elif (RTL8814A_SUPPORT)\n\t#define PHY_NUM_RATE_IDX NUM_RATE_AC_3SS\n/*[AC-2SS]*/\n#elif (RTL8812A_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\\\n\tRTL8812F_SUPPORT)\n\t#define PHY_NUM_RATE_IDX NUM_RATE_AC_2SS\n/*[AC-1SS]*/\n#elif (RTL8881A_SUPPORT || RTL8821A_SUPPORT || RTL8821C_SUPPORT ||\\\n\tRTL8195B_SUPPORT)\n\t#define PHY_NUM_RATE_IDX NUM_RATE_AC_1SS\n/*[N-4SS]*/\n#elif (RTL8198F_SUPPORT)\n\t#define PHY_NUM_RATE_IDX NUM_RATE_N_4SS\n/*[N-2SS]*/\n#elif (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\\\n\tRTL8197G_SUPPORT)\n\t#define PHY_NUM_RATE_IDX NUM_RATE_N_2SS\n/*[N-1SS]*/\n#elif (RTL8723B_SUPPORT || RTL8703B_SUPPORT || RTL8188E_SUPPORT || \\\n\tRTL8188F_SUPPORT || RTL8723D_SUPPORT || RTL8195A_SUPPORT ||\\\n\tRTL8710B_SUPPORT || RTL8721D_SUPPORT)\n\t#define PHY_NUM_RATE_IDX NUM_RATE_N_1SS\n#else\n\t#define PHY_NUM_RATE_IDX NUM_RATE_AC_4SS\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t#define CONFIG_SFW_SUPPORTED\n#endif\n\n/****************************************************************\n * 1 ============================================================\n * 1  enumeration\n * 1 ============================================================\n ***************************************************************/\n\n/*\tODM_CMNINFO_INTERFACE */\nenum odm_interface {\n\tODM_ITRF_PCIE\t=\t0x1,\n\tODM_ITRF_USB\t=\t0x2,\n\tODM_ITRF_SDIO\t=\t0x4,\n\tODM_ITRF_ALL\t=\t0x7,\n};\n\nenum phydm_api_host {\n\tRUN_IN_FW\t\t= 0,\n\tRUN_IN_DRIVER\t\t= 1,\n};\n\n/*@========[Run time IC flag] ===================================*/\n\nenum phydm_ic {\n\tODM_RTL8188E\t=\tBIT(0),\n\tODM_RTL8812\t=\tBIT(1),\n\tODM_RTL8821\t=\tBIT(2),\n\tODM_RTL8192E\t=\tBIT(3),\n\tODM_RTL8723B\t=\tBIT(4),\n\tODM_RTL8814A\t=\tBIT(5),\n\tODM_RTL8881A\t=\tBIT(6),\n\tODM_RTL8822B\t=\tBIT(7),\n\tODM_RTL8703B\t=\tBIT(8),\n\tODM_RTL8195A\t=\tBIT(9),\n\tODM_RTL8188F\t=\tBIT(10),\n\tODM_RTL8723D\t=\tBIT(11),\n\tODM_RTL8197F\t=\tBIT(12),\n\tODM_RTL8821C\t=\tBIT(13),\n\tODM_RTL8814B\t=\tBIT(14),\n\tODM_RTL8198F\t=\tBIT(15),\n\tODM_RTL8710B\t=\tBIT(16),\n\tODM_RTL8192F\t=\tBIT(17),\n\tODM_RTL8822C\t=\tBIT(18),\n\tODM_RTL8195B\t=\tBIT(19),\n\tODM_RTL8812F\t=\tBIT(20),\n\tODM_RTL8197G\t=\tBIT(21),\n\tODM_RTL8721D\t=\tBIT(22)\n};\n\n#define ODM_IC_N_1SS\t\t(ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B |\\\n\t\t\t\t ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8195A |\\\n\t\t\t\t ODM_RTL8710B | ODM_RTL8721D)\n#define ODM_IC_N_2SS\t\t(ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F)\n#define ODM_IC_N_3SS\t\t0\n#define ODM_IC_N_4SS\t\t0\n\n#define ODM_IC_AC_1SS\t\t(ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C |\\\n\t\t\t\t ODM_RTL8195B)\n#define ODM_IC_AC_2SS\t\t(ODM_RTL8812 | ODM_RTL8822B)\n#define ODM_IC_AC_3SS\t\t0\n#define ODM_IC_AC_4SS\t\t(ODM_RTL8814A)\n\n#define ODM_IC_JGR3_1SS\t\t0\n#define ODM_IC_JGR3_2SS\t\t(ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)\n#define ODM_IC_JGR3_3SS\t\t0\n#define ODM_IC_JGR3_4SS\t\t(ODM_RTL8198F | ODM_RTL8814B)\n\n/*@====the following macro DO NOT need to update when adding a new IC======= */\n#define ODM_IC_1SS\t\t(ODM_IC_N_1SS | ODM_IC_AC_1SS | ODM_IC_JGR3_1SS)\n#define ODM_IC_2SS\t\t(ODM_IC_N_2SS | ODM_IC_AC_2SS | ODM_IC_JGR3_2SS)\n#define ODM_IC_3SS\t\t(ODM_IC_N_3SS | ODM_IC_AC_3SS | ODM_IC_JGR3_3SS)\n#define ODM_IC_4SS\t\t(ODM_IC_N_4SS | ODM_IC_AC_4SS | ODM_IC_JGR3_4SS)\n\n#define PHYDM_IC_ABOVE_1SS\t(ODM_IC_1SS | ODM_IC_2SS | ODM_IC_3SS |\\\n\t\t\t\t ODM_IC_4SS)\n#define PHYDM_IC_ABOVE_2SS\t(ODM_IC_2SS | ODM_IC_3SS | ODM_IC_4SS)\n#define PHYDM_IC_ABOVE_3SS\t(ODM_IC_3SS | ODM_IC_4SS)\n#define PHYDM_IC_ABOVE_4SS\tODM_IC_4SS\n\n#define ODM_IC_11N_SERIES\t(ODM_IC_N_1SS | ODM_IC_N_2SS | ODM_IC_N_3SS |\\\n\t\t\t\t ODM_IC_N_4SS)\n#define ODM_IC_11AC_SERIES\t(ODM_IC_AC_1SS | ODM_IC_AC_2SS |\\\n\t\t\t\t ODM_IC_AC_3SS | ODM_IC_AC_4SS)\n#define ODM_IC_JGR3_SERIES\t(ODM_IC_JGR3_1SS | ODM_IC_JGR3_2SS |\\\n\t\t\t\t ODM_IC_JGR3_3SS | ODM_IC_JGR3_4SS)\n/*@====================================================*/\n\n#define ODM_IC_11AC_1_SERIES\t(ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)\n#define ODM_IC_11AC_2_SERIES\t(ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C |\\\n\t\t\t\t ODM_RTL8195B)\n\n/*@[Phy status type]*/\n#define PHYSTS_2ND_TYPE_IC\t(ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D |\\\n\t\t\t\t ODM_RTL8821C | ODM_RTL8710B | ODM_RTL8195B |\\\n\t\t\t\t ODM_RTL8192F | ODM_RTL8721D)\n#define PHYSTS_3RD_TYPE_IC\t(ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8822C |\\\n\t\t\t\t ODM_RTL8812F | ODM_RTL8197G)\n/*@[FW Type]*/\n#define PHYDM_IC_8051_SERIES\t(ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 |\\\n\t\t\t\t ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B |\\\n\t\t\t\t ODM_RTL8188F | ODM_RTL8192F | ODM_RTL8721D)\n#define PHYDM_IC_3081_SERIES\t(ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\\\n\t\t\t\t ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\\\n\t\t\t\t ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8814B |\\\n\t\t\t\t ODM_RTL8197G)\n/*@[LA mode]*/\n#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\\\n\t\t\t\t  ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\\\n\t\t\t\t  ODM_RTL8192F | ODM_RTL8822C | ODM_RTL8812F |\\\n\t\t\t\t  ODM_RTL8195B | ODM_RTL8814B | ODM_RTL8197G)\n/*@[BF]*/\n#define ODM_IC_TXBF_SUPPORT\t(ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 |\\\n\t\t\t\t ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B |\\\n\t\t\t\t ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8195B |\\\n\t\t\t\t ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |\\\n\t\t\t\t ODM_RTL8814B | ODM_RTL8197G)\n#define PHYDM_IC_SUPPORT_MU_BFEE (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814B |\\\n\t\t\t\t  ODM_RTL8195B | ODM_RTL8198F | ODM_RTL8822C |\\\n\t\t\t\t  ODM_RTL8812F)\n#define PHYDM_IC_SUPPORT_MU_BFER (ODM_RTL8822B | ODM_RTL8814B | ODM_RTL8198F |\\\n\t\t\t\t  ODM_RTL8822C | ODM_RTL8812F)\n\n#define PHYDM_IC_SUPPORT_MU (PHYDM_IC_SUPPORT_MU_BFEE |\\\n\t\t\t\tPHYDM_IC_SUPPORT_MU_BFER)\n/*@[PHYDM API]*/\n#define CMN_API_SUPPORT_IC (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F |\\\n\t\t\t    ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\\\n\t\t\t    ODM_RTL8198F | ODM_RTL8812F | ODM_RTL8814B |\\\n\t\t\t    ODM_RTL8197G | ODM_RTL8721D)\n\n/* fw offload ability*/\n#define PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD (ODM_RTL8814A | ODM_RTL8822B |\\\n\t\t\t\t\t   ODM_RTL8821C | ODM_RTL8822C)\n\n/*@========[Compile time IC flag] ========================*/\n/*@========[AC-3/AC/N Support] ===========================*/\n\n#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\\\n\tRTL8812F_SUPPORT || RTL8197G_SUPPORT)\n\t#define PHYDM_IC_JGR3_SERIES_SUPPORT\n\t#if (RTL8814B_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT)\n\t\t#define PHYDM_IC_JGR3_80M_SUPPORT\n\t#endif\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\n\t#ifdef RTK_AC_SUPPORT\n\t#define ODM_IC_11AC_SERIES_SUPPORT\t1\n\t#else\n\t#define ODM_IC_11AC_SERIES_SUPPORT\t0\n\t#endif\n\n\t#define ODM_IC_11N_SERIES_SUPPORT\t1\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\n\t#define ODM_IC_11AC_SERIES_SUPPORT\t1\n\t#define ODM_IC_11N_SERIES_SUPPORT\t1\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\n\t#define ODM_IC_11AC_SERIES_SUPPORT\t1\n\t#define ODM_IC_11N_SERIES_SUPPORT\t1\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n\n\t#define ODM_IC_11AC_SERIES_SUPPORT\t\t1\n\t#define ODM_IC_11N_SERIES_SUPPORT\t\t\t1\n\n#else /*ODM_CE*/\n\n\t#if (RTL8188E_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\\\n\t     RTL8195A_SUPPORT || RTL8703B_SUPPORT || RTL8188F_SUPPORT ||\\\n\t     RTL8723D_SUPPORT || RTL8197F_SUPPORT || RTL8710B_SUPPORT ||\\\n\t     RTL8192F_SUPPORT || RTL8721D_SUPPORT)\n\t\t#define ODM_IC_11N_SERIES_SUPPORT\t1\n\t\t#define ODM_IC_11AC_SERIES_SUPPORT\t0\n\t#else\n\t\t#define ODM_IC_11N_SERIES_SUPPORT\t0\n\t\t#define ODM_IC_11AC_SERIES_SUPPORT\t1\n\t#endif\n#endif\n\n/*@===IC SS Compile Flag, prepare for code size reduction==============*/\n#if (RTL8188E_SUPPORT || RTL8188F_SUPPORT || RTL8723B_SUPPORT ||\\\n\tRTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8881A_SUPPORT ||\\\n\tRTL8821A_SUPPORT || RTL8821C_SUPPORT || RTL8195A_SUPPORT ||\\\n\tRTL8710B_SUPPORT || RTL8195B_SUPPORT || RTL8721D_SUPPORT)\n\n\t#define PHYDM_COMPILE_IC_1SS\n#endif\n\n#if (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8812A_SUPPORT ||\\\n\tRTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8822C_SUPPORT ||\\\n\tRTL8812F_SUPPORT || RTL8197G_SUPPORT)\n\t#define PHYDM_COMPILE_IC_2SS\n#endif\n\n/*@#define PHYDM_COMPILE_IC_3SS*/\n\n#if ((RTL8814B_SUPPORT) || (RTL8814A_SUPPORT) || (RTL8198F_SUPPORT))\n\t#define PHYDM_COMPILE_IC_4SS\n#endif\n\n/*@==[ABOVE N-SS COMPILE FLAG]=================================================*/\n#if (defined(PHYDM_COMPILE_IC_1SS) || defined(PHYDM_COMPILE_IC_2SS) ||\\\n\tdefined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS))\n\t#define PHYDM_COMPILE_ABOVE_1SS\n#endif\n\n#if (defined(PHYDM_COMPILE_IC_2SS) || defined(PHYDM_COMPILE_IC_3SS) ||\\\n\tdefined(PHYDM_COMPILE_IC_4SS))\n\t#define PHYDM_COMPILE_ABOVE_2SS\n#endif\n\n#if (defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS))\n\t#define PHYDM_COMPILE_ABOVE_3SS\n#endif\n\n#if (defined(PHYDM_COMPILE_IC_4SS))\n\t#define PHYDM_COMPILE_ABOVE_4SS\n#endif\n\n/*@==[Max RF path number among all compiled ICs]==============================*/\n/*@ ex: support 8814B & 8821C => size=4 */\n/*@ ex: support 8822C & 8821C => size=2 */\n#if (defined(PHYDM_COMPILE_IC_4SS))\n\t#define RF_PATH_MEM_SIZE 4\n#elif (defined(PHYDM_COMPILE_IC_3SS))\n\t#define RF_PATH_MEM_SIZE 3\n#elif (defined(PHYDM_COMPILE_IC_2SS))\n\t#define RF_PATH_MEM_SIZE 2\n#else\n\t#define RF_PATH_MEM_SIZE 1\n#endif\n\n/*@========[New Phy-Status Support] ========================*/\n#if (RTL8197F_SUPPORT || RTL8723D_SUPPORT || RTL8822B_SUPPORT ||\\\n\tRTL8821C_SUPPORT || RTL8710B_SUPPORT || RTL8195B_SUPPORT ||\\\n\tRTL8192F_SUPPORT || RTL8721D_SUPPORT)\n\t#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT\t\t\t1\n#else\n\t#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT\t\t\t0\n#endif\n\n#if (RTL8198F_SUPPORT) || (RTL8814B_SUPPORT) || (RTL8822C_SUPPORT) ||\\\n\t(RTL8812F_SUPPORT) || (RTL8197G_SUPPORT)\n\t#define PHYSTS_3RD_TYPE_SUPPORT\n#endif\n\n#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8822C_SUPPORT ||\\\n\tRTL8812F_SUPPORT || RTL8197G_SUPPORT)\n\t#define BB_RAM_SUPPORT\n#endif\n\n#if (RTL8821C_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\\\n\tRTL8812F_SUPPORT || RTL8814B_SUPPORT || RTL8195B_SUPPORT ||\\\n\tRTL8198F_SUPPORT)\n\t#define PHYDM_COMPILE_MU\n#endif\n\n#if (RTL8822B_SUPPORT)\n\t#define CONFIG_MU_JAGUAR_2\n#endif\n\n#if (RTL8814B_SUPPORT || RTL8822C_SUPPORT)\n\t#define CONFIG_MU_JAGUAR_3\n#endif\n\n#if (defined(CONFIG_MU_JAGUAR_2) || defined(CONFIG_MU_JAGUAR_3))\n#if (RTL8814B_SUPPORT)\n\t#define MU_EX_MACID\t\t\t76\n\t#elif (RTL8822B_SUPPORT || RTL8822C_SUPPORT)\n\t\t#define MU_EX_MACID\t\t30\n\t#endif\n#endif\n/*@============================================================================*/\n\n#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\\\n\tRTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8822C_SUPPORT ||\\\n\tRTL8198F_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\\\n\tRTL8197G_SUPPORT || RTL8721D_SUPPORT)\n#define PHYDM_COMMON_API_SUPPORT\n#endif\n\n\n#define\tCCK_RATE_NUM\t\t4\n#define\tOFDM_RATE_NUM\t\t8\n\n#define\tLEGACY_RATE_NUM\t\t12\n\n#define\tHT_RATE_NUM_4SS\t\t32\n#define\tVHT_RATE_NUM_4SS\t40\n\n#define\tHT_RATE_NUM_3SS\t\t24\n#define\tVHT_RATE_NUM_3SS\t30\n\n#define\tHT_RATE_NUM_2SS\t\t16\n#define\tVHT_RATE_NUM_2SS\t20\n\n#define\tHT_RATE_NUM_1SS\t\t8\n#define\tVHT_RATE_NUM_1SS\t10\n#if (defined(PHYDM_COMPILE_ABOVE_4SS))\n\t#define\tHT_RATE_NUM\tHT_RATE_NUM_4SS\n\t#define\tVHT_RATE_NUM\tVHT_RATE_NUM_4SS\n#elif (defined(PHYDM_COMPILE_ABOVE_3SS))\n\t#define\tHT_RATE_NUM\tHT_RATE_NUM_3SS\n\t#define\tVHT_RATE_NUM\tVHT_RATE_NUM_3SS\n#elif (defined(PHYDM_COMPILE_ABOVE_2SS))\n\t#define\tHT_RATE_NUM\tHT_RATE_NUM_2SS\n\t#define\tVHT_RATE_NUM\tVHT_RATE_NUM_2SS\n#else\n\t#define\tHT_RATE_NUM\tHT_RATE_NUM_1SS\n\t#define\tVHT_RATE_NUM\tVHT_RATE_NUM_1SS\n#endif\n\n#define\tLOW_BW_RATE_NUM\t\tVHT_RATE_NUM\n\nenum phydm_ic_ip {\n\tPHYDM_IC_N\t\t= 0,\n\tPHYDM_IC_AC\t\t= 1,\n\tPHYDM_IC_JGR3\t\t= 2\n};\n\nenum phydm_phy_sts_type {\n\tPHYDM_PHYSTS_TYPE_1\t= 1,\n\tPHYDM_PHYSTS_TYPE_2\t= 2,\n\tPHYDM_PHYSTS_TYPE_3\t= 3\n};\n\n/* ODM_CMNINFO_CUT_VER */\nenum odm_cut_version {\n\tODM_CUT_A\t\t= 0,\n\tODM_CUT_B\t\t= 1,\n\tODM_CUT_C\t\t= 2,\n\tODM_CUT_D\t\t= 3,\n\tODM_CUT_E\t\t= 4,\n\tODM_CUT_F\t\t= 5,\n\tODM_CUT_G\t\t= 6,\n\tODM_CUT_H\t\t= 7,\n\tODM_CUT_I\t\t= 8,\n\tODM_CUT_J\t\t= 9,\n\tODM_CUT_K\t\t= 10,\n\tODM_CUT_L\t\t= 11,\n\tODM_CUT_M\t\t= 12,\n\tODM_CUT_N\t\t= 13,\n\tODM_CUT_O\t\t= 14,\n\tODM_CUT_TEST\t\t= 15,\n};\n\n/* ODM_CMNINFO_FAB_VER */\nenum odm_fab {\n\tODM_TSMC\t\t= 0,\n\tODM_UMC\t\t\t= 1,\n};\n\n/* ODM_CMNINFO_OP_MODE */\nenum odm_operation_mode {\n\tODM_NO_LINK\t\t= BIT(0),\n\tODM_LINK\t\t= BIT(1),\n\tODM_SCAN\t\t= BIT(2),\n\tODM_POWERSAVE\t\t= BIT(3),\n\tODM_AP_MODE\t\t= BIT(4),\n\tODM_CLIENT_MODE\t\t= BIT(5),\n\tODM_AD_HOC\t\t= BIT(6),\n\tODM_WIFI_DIRECT\t\t= BIT(7),\n\tODM_WIFI_DISPLAY\t= BIT(8),\n};\n\n/* ODM_CMNINFO_WM_MODE */\n#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))\nenum odm_wireless_mode {\n\tODM_WM_UNKNOW\t\t= 0x0,\n\tODM_WM_B\t\t= BIT(0),\n\tODM_WM_G\t\t= BIT(1),\n\tODM_WM_A\t\t= BIT(2),\n\tODM_WM_N24G\t\t= BIT(3),\n\tODM_WM_N5G\t\t= BIT(4),\n\tODM_WM_AUTO\t\t= BIT(5),\n\tODM_WM_AC\t\t= BIT(6),\n};\n#else\nenum odm_wireless_mode {\n\tODM_WM_UNKNOWN\t\t= 0x00,/*@0x0*/\n\tODM_WM_A\t\t= BIT(0), /* @0x1*/\n\tODM_WM_B\t\t= BIT(1), /* @0x2*/\n\tODM_WM_G\t\t= BIT(2),/* @0x4*/\n\tODM_WM_AUTO\t\t= BIT(3),/* @0x8*/\n\tODM_WM_N24G\t\t= BIT(4),/* @0x10*/\n\tODM_WM_N5G\t\t= BIT(5),/* @0x20*/\n\tODM_WM_AC_5G\t\t= BIT(6),/* @0x40*/\n\tODM_WM_AC_24G\t\t= BIT(7),/* @0x80*/\n\tODM_WM_AC_ONLY\t\t= BIT(8),/* @0x100*/\n\tODM_WM_MAX\t\t= BIT(11)/* @0x800*/\n\n};\n#endif\n\n/* ODM_CMNINFO_BAND */\nenum odm_band_type {\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\tODM_BAND_2_4G\t\t= BIT(0),\n\tODM_BAND_5G\t\t= BIT(1),\n#else\n\tODM_BAND_2_4G\t\t= 0,\n\tODM_BAND_5G,\n\tODM_BAND_ON_BOTH,\n\tODM_BANDMAX\n#endif\n};\n\n/* ODM_CMNINFO_SEC_CHNL_OFFSET */\nenum phydm_sec_chnl_offset {\n\tPHYDM_DONT_CARE\t\t= 0,\n\tPHYDM_BELOW\t\t= 1,\n\tPHYDM_ABOVE\t\t= 2\n};\n\n/* ODM_CMNINFO_SEC_MODE */\nenum odm_security {\n\tODM_SEC_OPEN\t\t= 0,\n\tODM_SEC_WEP40\t\t= 1,\n\tODM_SEC_TKIP\t\t= 2,\n\tODM_SEC_RESERVE\t\t= 3,\n\tODM_SEC_AESCCMP\t\t= 4,\n\tODM_SEC_WEP104\t\t= 5,\n\tODM_WEP_WPA_MIXED\t= 6, /* WEP + WPA */\n\tODM_SEC_SMS4\t\t= 7,\n};\n\n/* ODM_CMNINFO_CHNL */\n\n/* ODM_CMNINFO_BOARD_TYPE */\nenum odm_board_type {\n\tODM_BOARD_DEFAULT\t= 0,\t  /* The DEFAULT case. */\n\tODM_BOARD_MINICARD\t= BIT(0), /* @0 = non-mini card, 1= mini card. */\n\tODM_BOARD_SLIM\t\t= BIT(1), /* @0 = non-slim card, 1 = slim card */\n\tODM_BOARD_BT\t\t= BIT(2), /* @0 = without BT card, 1 = with BT */\n\tODM_BOARD_EXT_PA\t= BIT(3), /* @0 = no 2G ext-PA, 1 = existing 2G ext-PA */\n\tODM_BOARD_EXT_LNA\t= BIT(4), /* @0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */\n\tODM_BOARD_EXT_TRSW\t= BIT(5), /* @0 = no ext-TRSW, 1 = existing ext-TRSW */\n\tODM_BOARD_EXT_PA_5G\t= BIT(6), /* @0 = no 5G ext-PA, 1 = existing 5G ext-PA */\n\tODM_BOARD_EXT_LNA_5G\t= BIT(7), /* @0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */\n};\n\nenum odm_package_type {\n\tODM_PACKAGE_DEFAULT\t= 0,\n\tODM_PACKAGE_QFN68\t= BIT(0),\n\tODM_PACKAGE_TFBGA90\t= BIT(1),\n\tODM_PACKAGE_TFBGA79\t= BIT(2),\n};\n\nenum odm_type_gpa {\n\tTYPE_GPA0\t\t= 0x0000,\n\tTYPE_GPA1\t\t= 0x0055,\n\tTYPE_GPA2\t\t= 0x00AA,\n\tTYPE_GPA3\t\t= 0x00FF,\n\tTYPE_GPA4\t\t= 0x5500,\n\tTYPE_GPA5\t\t= 0x5555,\n\tTYPE_GPA6\t\t= 0x55AA,\n\tTYPE_GPA7\t\t= 0x55FF,\n\tTYPE_GPA8\t\t= 0xAA00,\n\tTYPE_GPA9\t\t= 0xAA55,\n\tTYPE_GPA10\t\t= 0xAAAA,\n\tTYPE_GPA11\t\t= 0xAAFF,\n\tTYPE_GPA12\t\t= 0xFF00,\n\tTYPE_GPA13\t\t= 0xFF55,\n\tTYPE_GPA14\t\t= 0xFFAA,\n\tTYPE_GPA15\t\t= 0xFFFF,\n};\n\nenum odm_type_apa {\n\tTYPE_APA0\t\t= 0x0000,\n\tTYPE_APA1\t\t= 0x0055,\n\tTYPE_APA2\t\t= 0x00AA,\n\tTYPE_APA3\t\t= 0x00FF,\n\tTYPE_APA4\t\t= 0x5500,\n\tTYPE_APA5\t\t= 0x5555,\n\tTYPE_APA6\t\t= 0x55AA,\n\tTYPE_APA7\t\t= 0x55FF,\n\tTYPE_APA8\t\t= 0xAA00,\n\tTYPE_APA9\t\t= 0xAA55,\n\tTYPE_APA10\t\t= 0xAAAA,\n\tTYPE_APA11\t\t= 0xAAFF,\n\tTYPE_APA12\t\t= 0xFF00,\n\tTYPE_APA13\t\t= 0xFF55,\n\tTYPE_APA14\t\t= 0xFFAA,\n\tTYPE_APA15\t\t= 0xFFFF,\n};\n\nenum odm_type_glna {\n\tTYPE_GLNA0\t\t= 0x0000,\n\tTYPE_GLNA1\t\t= 0x0055,\n\tTYPE_GLNA2\t\t= 0x00AA,\n\tTYPE_GLNA3\t\t= 0x00FF,\n\tTYPE_GLNA4\t\t= 0x5500,\n\tTYPE_GLNA5\t\t= 0x5555,\n\tTYPE_GLNA6\t\t= 0x55AA,\n\tTYPE_GLNA7\t\t= 0x55FF,\n\tTYPE_GLNA8\t\t= 0xAA00,\n\tTYPE_GLNA9\t\t= 0xAA55,\n\tTYPE_GLNA10\t\t= 0xAAAA,\n\tTYPE_GLNA11\t\t= 0xAAFF,\n\tTYPE_GLNA12\t\t= 0xFF00,\n\tTYPE_GLNA13\t\t= 0xFF55,\n\tTYPE_GLNA14\t\t= 0xFFAA,\n\tTYPE_GLNA15\t\t= 0xFFFF,\n};\n\nenum odm_type_alna {\n\tTYPE_ALNA0\t\t= 0x0000,\n\tTYPE_ALNA1\t\t= 0x0055,\n\tTYPE_ALNA2\t\t= 0x00AA,\n\tTYPE_ALNA3\t\t= 0x00FF,\n\tTYPE_ALNA4\t\t= 0x5500,\n\tTYPE_ALNA5\t\t= 0x5555,\n\tTYPE_ALNA6\t\t= 0x55AA,\n\tTYPE_ALNA7\t\t= 0x55FF,\n\tTYPE_ALNA8\t\t= 0xAA00,\n\tTYPE_ALNA9\t\t= 0xAA55,\n\tTYPE_ALNA10\t\t= 0xAAAA,\n\tTYPE_ALNA11\t\t= 0xAAFF,\n\tTYPE_ALNA12\t\t= 0xFF00,\n\tTYPE_ALNA13\t\t= 0xFF55,\n\tTYPE_ALNA14\t\t= 0xFFAA,\n\tTYPE_ALNA15\t\t= 0xFFFF,\n};\n\n#define\tPAUSE_FAIL\t\t0\n#define\tPAUSE_SUCCESS\t\t1\n\nenum odm_parameter_init {\n\tODM_PRE_SETTING\t\t= 0,\n\tODM_POST_SETTING\t= 1,\n\tODM_INIT_FW_SETTING\n};\n\nenum phydm_pause_type {\n\tPHYDM_PAUSE\t\t= 1,\t/*Pause & Set new value*/\n\tPHYDM_PAUSE_NO_SET\t= 2,\t/*Pause & Stay in current value*/\n\tPHYDM_RESUME\t\t= 3\n};\n\nenum phydm_pause_level {\n\tPHYDM_PAUSE_RELEASE\t= -1,\n\tPHYDM_PAUSE_LEVEL_0\t= 0,\t/* @Low Priority function */\n\tPHYDM_PAUSE_LEVEL_1\t= 1,\t/* @Middle Priority function */\n\tPHYDM_PAUSE_LEVEL_2\t= 2,\t/* @High priority function (ex: Check hang function) */\n\tPHYDM_PAUSE_LEVEL_3\t= 3,\t/* @Debug function (the highest priority) */\n\tPHYDM_PAUSE_MAX_NUM\t= 4\n};\n\nenum phydm_dis_hw_fun {\n\tHW_FUN_DIS\t\t= 0,\t/*@Disable a cetain HW function & backup the original value*/\n\tHW_FUN_RESUME\t\t= 1\t/*Revert */\n};\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_precomp.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __ODM_PRECOMP_H__\n#define __ODM_PRECOMP_H__\n\n#include \"phydm_types.h\"\n#include \"halrf/halrf_features.h\"\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t#include \"Precomp.h\"\t\t/* @We need to include mp_precomp.h due to batch file setting. */\n#else\n\t#define\t\tTEST_FALG___\t\t1\n#endif\n\n/* @2 Config Flags and Structs - defined by each ODM type */\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t#include \"../8192cd_cfg.h\"\n\t#include \"../odm_inc.h\"\n\n\t#include \"../8192cd.h\"\n\t#include \"../8192cd_util.h\"\n\t#include \"../8192cd_hw.h\"\n\t#ifdef _BIG_ENDIAN_\n\t\t#define\tODM_ENDIAN_TYPE\t\t\t\tODM_ENDIAN_BIG\n\t#else\n\t\t#define\tODM_ENDIAN_TYPE\t\t\t\tODM_ENDIAN_LITTLE\n\t#endif\n\n\t#include \"../8192cd_headers.h\"\n\t#include \"../8192cd_debug.h\"\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t#ifdef DM_ODM_CE_MAC80211\n\t\t#include \"../wifi.h\"\n\t\t#include \"rtl_phydm.h\"\n\t#elif defined(DM_ODM_CE_MAC80211_V2)\n\t\t#include \"../main.h\"\n\t\t#include \"../hw.h\"\n\t\t#include \"../fw.h\"\n\t#endif\n\t#define __PACK\n\t#define __WLAN_ATTRIB_PACK__\n#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t#include \"mp_precomp.h\"\n\t#define\tODM_ENDIAN_TYPE\t\t\t\tODM_ENDIAN_LITTLE\n\t#define __PACK\n\t#define __WLAN_ATTRIB_PACK__\n#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)\n\t#include <drv_types.h>\n\t#include <wifi.h>\n\t#define\tODM_ENDIAN_TYPE\t\t\t\tODM_ENDIAN_LITTLE\n\t#define __PACK\n#endif\n\n/* @2 OutSrc Header Files */\n\n#include \"phydm.h\"\n#include \"phydm_hwconfig.h\"\n#include \"phydm_phystatus.h\"\n#include \"phydm_debug.h\"\n#include \"phydm_regdefine11ac.h\"\n#include \"phydm_regdefine11n.h\"\n#include \"phydm_interface.h\"\n#include \"phydm_reg.h\"\n#include \"halrf/halrf_debug.h\"\n\n#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && \\\n\t(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))\n\nvoid phy_set_tx_power_limit(\n\tstruct dm_struct *dm,\n\tu8 *regulation,\n\tu8 *band,\n\tu8 *bandwidth,\n\tu8 *rate_section,\n\tu8 *rf_path,\n\tu8 *channel,\n\tu8 *power_limit);\n\nenum hal_status\nrtw_phydm_fw_iqk(\n\tstruct dm_struct *dm,\n\tu8 clear,\n\tu8 segment);\n\nenum hal_status\nrtw_phydm_cfg_phy_para(\n\tstruct dm_struct *dm,\n\tenum phydm_halmac_param config_type,\n\tu32 offset,\n\tu32 data,\n\tu32 mask,\n\tenum rf_path e_rf_path,\n\tu32 delay_time);\n\n#endif\n\n/* @Judy ADD 20180125 */\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_IOT))\n#define RTL8710B_SUPPORT\t\t0\n#endif\n\n#if RTL8188E_SUPPORT == 1\n\t#define RTL8188E_T_SUPPORT 1\n\t#ifdef CONFIG_SFW_SUPPORTED\n\t\t#define RTL8188E_S_SUPPORT 1\n\t#else\n\t\t#define RTL8188E_S_SUPPORT 0\n\t#endif\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n#define RTL8197F_SUPPORT 0\t/*@Just for PHYDM API development*/\n#define\tRTL8195B_SUPPORT 0\t/*@Just for PHYDM API development*/\n#define\tRTL8198F_SUPPORT 0\t/*@Just for PHYDM API development*/\n#define\tRTL8812F_SUPPORT 0\t/*@Just for PHYDM API development*/\n#define\tRTL8197G_SUPPORT 0\t/*@Just for PHYDM API development*/\n#endif\n\n#if (RTL8188E_SUPPORT == 1)\n\t#include \"rtl8188e/hal8188erateadaptive.h\" /* @for  RA,Power training */\n\t#include \"rtl8188e/halhwimg8188e_mac.h\"\n\t#include \"rtl8188e/halhwimg8188e_rf.h\"\n\t#include \"rtl8188e/halhwimg8188e_bb.h\"\n\t#include \"rtl8188e/phydm_regconfig8188e.h\"\n\t#include \"rtl8188e/phydm_rtl8188e.h\"\n\t#include \"rtl8188e/hal8188ereg.h\"\n\t#include \"rtl8188e/version_rtl8188e.h\"\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#include \"rtl8188e_hal.h\"\n\t\t#include \"halrf/rtl8188e/halrf_8188e_ce.h\"\n\t#endif\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t\t#include \"halrf/rtl8188e/halrf_8188e_win.h\"\n\t#endif\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t\t#include \"halrf/rtl8188e/halrf_8188e_ap.h\"\n\t#endif\n#endif /* @88E END */\n\n#if (RTL8192E_SUPPORT == 1)\n\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t\t#include \"halrf/rtl8192e/halrf_8192e_win.h\" /*@FOR_8192E_IQK*/\n\t#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t\t#include \"halrf/rtl8192e/halrf_8192e_ap.h\" /*@FOR_8192E_IQK*/\n\t#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#include \"halrf/rtl8192e/halrf_8192e_ce.h\" /*@FOR_8192E_IQK*/\n\t#endif\n\n\t#include \"rtl8192e/phydm_rtl8192e.h\" /* @FOR_8192E_IQK */\n\t#include \"rtl8192e/version_rtl8192e.h\"\n\t#if (DM_ODM_SUPPORT_TYPE != ODM_AP)\n\t\t#include \"rtl8192e/halhwimg8192e_bb.h\"\n\t\t#include \"rtl8192e/halhwimg8192e_mac.h\"\n\t\t#include \"rtl8192e/halhwimg8192e_rf.h\"\n\t\t#include \"rtl8192e/phydm_regconfig8192e.h\"\n\t\t#include \"rtl8192e/hal8192ereg.h\"\n\t#endif\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#include \"rtl8192e_hal.h\"\n\t#endif\n#endif /* @92E END */\n\n#if (RTL8812A_SUPPORT == 1)\n\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t\t#include \"halrf/rtl8812a/halrf_8812a_win.h\"\n\t#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t\t#include \"halrf/rtl8812a/halrf_8812a_ap.h\"\n\t#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#include \"halrf/rtl8812a/halrf_8812a_ce.h\"\n\t#endif\n\n\t/* @#include \"halrf/rtl8812a/halrf_8812a.h\"  */ /* @FOR_8812_IQK */\n\t#if (DM_ODM_SUPPORT_TYPE != ODM_AP)\n\t\t#include \"rtl8812a/halhwimg8812a_bb.h\"\n\t\t#include \"rtl8812a/halhwimg8812a_mac.h\"\n\t\t#include \"rtl8812a/halhwimg8812a_rf.h\"\n\t\t#include \"rtl8812a/phydm_regconfig8812a.h\"\n\t#endif\n\t#include \"rtl8812a/phydm_rtl8812a.h\"\n\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#include \"rtl8812a_hal.h\"\n\t#endif\n\t#include \"rtl8812a/version_rtl8812a.h\"\n\n#endif /* @8812 END */\n\n#if (RTL8814A_SUPPORT == 1)\n\n\t#include \"rtl8814a/halhwimg8814a_mac.h\"\n\t#include \"rtl8814a/halhwimg8814a_rf.h\"\n\t#include \"rtl8814a/halhwimg8814a_bb.h\"\n\t#include \"rtl8814a/version_rtl8814a.h\"\n\t#include \"rtl8814a/phydm_rtl8814a.h\"\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t\t#include \"halrf/rtl8814a/halrf_8814a_win.h\"\n\t#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#include \"halrf/rtl8814a/halrf_8814a_ce.h\"\n\t#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t\t#include \"halrf/rtl8814a/halrf_8814a_ap.h\"\n\t#endif\n\t#include \"rtl8814a/phydm_regconfig8814a.h\"\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#include \"rtl8814a_hal.h\"\n\t\t#include \"halrf/rtl8814a/halrf_iqk_8814a.h\"\n\t#endif\n#endif /* @8814 END */\n\n#if (RTL8881A_SUPPORT == 1)/* @FOR_8881_IQK */\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t\t#include \"halrf/rtl8821a/halrf_iqk_8821a_win.h\"\n\t#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#include \"halrf/rtl8821a/halrf_iqk_8821a_ce.h\"\n\t#else\n\t\t#include \"halrf/rtl8821a/halrf_iqk_8821a_ap.h\"\n\t#endif\n\t/* @#include \"rtl8881a/HalHWImg8881A_BB.h\" */\n\t/* @#include \"rtl8881a/HalHWImg8881A_MAC.h\" */\n\t/* @#include \"rtl8881a/HalHWImg8881A_RF.h\" */\n\t/* @#include \"rtl8881a/odm_RegConfig8881A.h\" */\n#endif\n\n#if (RTL8723B_SUPPORT == 1)\n\t#include \"rtl8723b/halhwimg8723b_mac.h\"\n\t#include \"rtl8723b/halhwimg8723b_rf.h\"\n\t#include \"rtl8723b/halhwimg8723b_bb.h\"\n\t#include \"rtl8723b/phydm_regconfig8723b.h\"\n\t#include \"rtl8723b/phydm_rtl8723b.h\"\n\t#include \"rtl8723b/hal8723breg.h\"\n\t#include \"rtl8723b/version_rtl8723b.h\"\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t\t#include \"halrf/rtl8723b/halrf_8723b_win.h\"\n\t#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#include \"halrf/rtl8723b/halrf_8723b_ce.h\"\n\t\t#include \"rtl8723b/halhwimg8723b_mp.h\"\n\t\t#include \"rtl8723b_hal.h\"\n\t#else\n\t\t#include \"halrf/rtl8723b/halrf_8723b_ap.h\"\n\t#endif\n#endif\n\n#if (RTL8821A_SUPPORT == 1)\n\t#include \"rtl8821a/halhwimg8821a_mac.h\"\n\t#include \"rtl8821a/halhwimg8821a_rf.h\"\n\t#include \"rtl8821a/halhwimg8821a_bb.h\"\n\t#include \"rtl8821a/phydm_regconfig8821a.h\"\n\t#include \"rtl8821a/phydm_rtl8821a.h\"\n\t#include \"rtl8821a/version_rtl8821a.h\"\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t\t#include \"halrf/rtl8821a/halrf_8821a_win.h\"\n\t#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#include \"halrf/rtl8821a/halrf_8821a_ce.h\"\n\t\t#include \"halrf/rtl8821a/halrf_iqk_8821a_ce.h\"/*@for IQK*/\n\t\t#include \"halrf/rtl8812a/halrf_8812a_ce.h\"/*@for IQK,LCK,Power-tracking*/\n\t\t#include \"rtl8812a_hal.h\"\n\t#else\n\t#endif\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)\n#include \"../halmac/halmac_reg2.h\"\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)\n#include \"../halmac/halmac_reg2.h\"\n#endif\n\n\n#if (RTL8822B_SUPPORT == 1)\n\t#include \"rtl8822b/halhwimg8822b_mac.h\"\n\t#include \"rtl8822b/halhwimg8822b_bb.h\"\n\t#include \"rtl8822b/phydm_regconfig8822b.h\"\n\t#include \"halrf/rtl8822b/halrf_8822b.h\"\n\t#include \"halrf/rtl8822b/halhwimg8822b_rf.h\"\n\t#include \"rtl8822b/phydm_rtl8822b.h\"\n\t#include \"rtl8822b/phydm_hal_api8822b.h\"\n\t#include \"rtl8822b/version_rtl8822b.h\"\n\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#ifdef DM_ODM_CE_MAC80211\n\t\t\t#include \"../halmac/halmac_reg_8822b.h\"\n\t\t#elif defined(DM_ODM_CE_MAC80211_V2)\n\t\t\t#include \"../halmac/halmac_reg_8822b.h\"\n\t\t#else\n\t\t\t#include <hal_data.h>\t\t/* @struct HAL_DATA_TYPE */\n\t\t\t#include <rtl8822b_hal.h>\t/* @RX_SMOOTH_FACTOR, reg definition and etc.*/\n\t\t#endif\n\t#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t#endif\n\n#endif\n\n#if (RTL8703B_SUPPORT == 1)\n\t#include \"rtl8703b/phydm_rtl8703b.h\"\n\t#include \"rtl8703b/phydm_regconfig8703b.h\"\n\t#include \"rtl8703b/halhwimg8703b_mac.h\"\n\t#include \"rtl8703b/halhwimg8703b_rf.h\"\n\t#include \"rtl8703b/halhwimg8703b_bb.h\"\n\t#include \"halrf/rtl8703b/halrf_8703b.h\"\n\t#include \"rtl8703b/version_rtl8703b.h\"\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#include \"rtl8703b_hal.h\"\n\t#endif\n#endif\n\n#if (RTL8188F_SUPPORT == 1)\n\t#include \"rtl8188f/halhwimg8188f_mac.h\"\n\t#include \"rtl8188f/halhwimg8188f_rf.h\"\n\t#include \"rtl8188f/halhwimg8188f_bb.h\"\n\t#include \"rtl8188f/hal8188freg.h\"\n\t#include \"rtl8188f/phydm_rtl8188f.h\"\n\t#include \"rtl8188f/phydm_regconfig8188f.h\"\n\t#include \"halrf/rtl8188f/halrf_8188f.h\" /*@for IQK,LCK,Power-tracking*/\n\t#include \"rtl8188f/version_rtl8188f.h\"\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#include \"rtl8188f_hal.h\"\n\t#endif\n#endif\n\n#if (RTL8723D_SUPPORT == 1)\n\t#if (DM_ODM_SUPPORT_TYPE != ODM_AP)\n\n\t\t#include \"rtl8723d/halhwimg8723d_bb.h\"\n\t\t#include \"rtl8723d/halhwimg8723d_mac.h\"\n\t\t#include \"rtl8723d/halhwimg8723d_rf.h\"\n\t\t#include \"rtl8723d/phydm_regconfig8723d.h\"\n\t\t#include \"rtl8723d/hal8723dreg.h\"\n\t\t#include \"rtl8723d/phydm_rtl8723d.h\"\n\t\t#include \"halrf/rtl8723d/halrf_8723d.h\"\n\t\t#include \"rtl8723d/version_rtl8723d.h\"\n\t#endif\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#ifdef DM_ODM_CE_MAC80211\n\t\t#else\n\t\t#include \"rtl8723d_hal.h\"\n\t\t#endif\n\t#endif\n#endif /* @8723D End */\n\n#if (RTL8710B_SUPPORT == 1)\n\t#if (DM_ODM_SUPPORT_TYPE != ODM_AP)\n\n\t\t#include \"rtl8710b/halhwimg8710b_bb.h\"\n\t\t#include \"rtl8710b/halhwimg8710b_mac.h\"\n\t\t#include \"rtl8710b/phydm_regconfig8710b.h\"\n\t\t#include \"rtl8710b/hal8710breg.h\"\n\t\t#include \"rtl8710b/phydm_rtl8710b.h\"\n\t\t#include \"halrf/rtl8710b/halrf_8710b.h\"\n\t\t#include \"halrf/rtl8710b/halhwimg8710b_rf.h\"\n\t\t#include \"rtl8710b/version_rtl8710b.h\"\n\t#endif\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#include \"rtl8710b_hal.h\"\n\t#endif\n#endif /* @8710B End */\n\n#if (RTL8197F_SUPPORT == 1)\n\t#include \"rtl8197f/halhwimg8197f_mac.h\"\n\t#include \"rtl8197f/halhwimg8197f_bb.h\"\n\t#include \"rtl8197f/phydm_hal_api8197f.h\"\n\t#include \"rtl8197f/version_rtl8197f.h\"\n\t#include \"rtl8197f/phydm_rtl8197f.h\"\n\t#include \"rtl8197f/phydm_regconfig8197f.h\"\n\t#include \"halrf/rtl8197f/halrf_8197f.h\"\n\t#include \"halrf/rtl8197f/halrf_iqk_8197f.h\"\n\t#include \"halrf/rtl8197f/halrf_dpk_8197f.h\"\n\t#include \"halrf/rtl8197f/halhwimg8197f_rf.h\"\n#endif\n\n#if (RTL8821C_SUPPORT == 1)\n\t#include \"rtl8821c/phydm_hal_api8821c.h\"\n\t#include \"rtl8821c/halhwimg8821c_mac.h\"\n\t#include \"rtl8821c/halhwimg8821c_bb.h\"\n\t#include \"rtl8821c/phydm_regconfig8821c.h\"\n\t#include \"halrf/rtl8821c/halrf_8821c.h\"\n\t#include \"halrf/rtl8821c/halhwimg8821c_rf.h\"\n\t#include \"rtl8821c/version_rtl8821c.h\"\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#ifdef DM_ODM_CE_MAC80211\n\t\t#include \"../halmac/halmac_reg_8821c.h\"\n\t\t#else\n\t\t#include \"rtl8821c_hal.h\"\n\t\t#endif\n\t#endif\n#endif\n\n#if (RTL8192F_SUPPORT == 1)\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#include \"rtl8192f_hal.h\"/*need to before rf.h*/\n\t#endif\n\t#include \"rtl8192f/halhwimg8192f_mac.h\"\n\t#include \"rtl8192f/halhwimg8192f_bb.h\"\n\t#include \"rtl8192f/phydm_hal_api8192f.h\"\n\t#include \"rtl8192f/version_rtl8192f.h\"\n\t#include \"rtl8192f/phydm_rtl8192f.h\"\n\t#include \"rtl8192f/phydm_regconfig8192f.h\"\n\t#include \"halrf/rtl8192f/halrf_8192f.h\"\n\t#include \"halrf/rtl8192f/halhwimg8192f_rf.h\"\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t\t#include \"halrf/rtl8192f/halrf_dpk_8192f.h\"\n\t#endif\n#endif\n\n#if (RTL8721D_SUPPORT == 1)\n\t#include \"halrf/rtl8721d/halrf_8721d.h\"\n\t#include \"halrf/rtl8721d/halhwimg8721d_rf.h\"\n\n\t#include \"rtl8721d/phydm_hal_api8721d.h\"\n\t#include \"rtl8721d/phydm_regconfig8721d.h\"\n\t#include \"rtl8721d/halhwimg8721d_mac.h\"\n\t#include \"rtl8721d/halhwimg8721d_bb.h\"\n\t#include \"rtl8721d/version_rtl8721d.h\"\n\t#include \"rtl8721d/phydm_rtl8721d.h\"\n\t#include \"rtl8721d/hal8721dreg.h\"\n\t#include <hal_data.h>\n\t#if 0\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t\t#include \"halrf/rtl8721d/halrf_dpk_8721d.h\"\n\t#endif\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#include \"rtl8721d_hal.h\"\n\t#endif\n\t#endif\n#endif\n#if (RTL8195B_SUPPORT == 1)\n\t#include \"halrf/rtl8195b/halrf_8195b.h\"\n\t#include \"halrf/rtl8195b/halhwimg8195b_rf.h\"\n\n\t#include \"rtl8195b/phydm_hal_api8195b.h\"\n\t#include \"rtl8195b/phydm_regconfig8195b.h\"\n\t#include \"rtl8195b/halhwimg8195b_mac.h\"\n\t#include \"rtl8195b/halhwimg8195b_bb.h\"\n\t#include \"rtl8195b/version_rtl8195b.h\"\n\t#include <hal_data.h> /*@HAL_DATA_TYPE*/\n#endif\n\n#if (RTL8198F_SUPPORT == 1)\n\t#include \"rtl8198f/phydm_regconfig8198f.h\"\n\t#include \"rtl8198f/phydm_hal_api8198f.h\"\n\t#include \"rtl8198f/halhwimg8198f_mac.h\"\n\t#include \"rtl8198f/halhwimg8198f_bb.h\"\n\t#include \"rtl8198f/version_rtl8198f.h\"\n\t#include \"halrf/rtl8198f/halrf_8198f.h\"\n\t#include \"halrf/rtl8198f/halrf_iqk_8198f.h\"\n\t#include \"halrf/rtl8198f/halhwimg8198f_rf.h\"\n#endif\n\n#if (RTL8822C_SUPPORT)\n\t#include \"rtl8822c/halhwimg8822c_bb.h\"\n\t#include \"rtl8822c/phydm_regconfig8822c.h\"\n\t#include \"rtl8822c/phydm_hal_api8822c.h\"\n\t#include \"rtl8822c/version_rtl8822c.h\"\n\t#include \"rtl8822c/phydm_rtl8822c.h\"\n\t#include \"halrf/rtl8822c/halrf_8822c.h\"\n\t#include \"halrf/rtl8822c/halhwimg8822c_rf.h\"\n\t#include \"halrf/rtl8822c/version_rtl8822c_rf.h\"\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t/* @struct HAL_DATA_TYPE */\n\t#include <hal_data.h>\n\t/* @RX_SMOOTH_FACTOR, reg definition and etc.*/\n\t#include <rtl8822c_hal.h>\n\t#endif\n#endif\n#if (RTL8814B_SUPPORT == 1)\n\t#include \"rtl8814b/halhwimg8814b_mac.h\"\n\t#include \"rtl8814b/halhwimg8814b_bb.h\"\n\t#include \"rtl8814b/phydm_regconfig8814b.h\"\n\t#include \"halrf/rtl8814b/halrf_8814b.h\"\n\t#include \"halrf/rtl8814b/halhwimg8814b_rf.h\"\n\t#include \"rtl8814b/phydm_hal_api8814b.h\"\n\t#include \"rtl8814b/version_rtl8814b.h\"\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t#include <hal_data.h>\t\t/* @struct HAL_DATA_TYPE */\n\t\t#include <rtl8814b_hal.h>\t/* @RX_SMOOTH_FACTOR, reg definition and etc.*/\n\t#endif\n#endif\n#if (RTL8812F_SUPPORT)\n\t#include \"rtl8812f/halhwimg8812f_mac.h\"\n\t#include \"rtl8812f/halhwimg8812f_bb.h\"\n\t#include \"rtl8812f/phydm_regconfig8812f.h\"\n\t#include \"halrf/rtl8812f/halrf_8812f.h\"\n\t#include \"halrf/rtl8812f/halhwimg8812f_rf.h\"\n\t#include \"rtl8812f/phydm_hal_api8812f.h\"\n\t#include \"rtl8812f/version_rtl8812f.h\"\n#endif\n#if (RTL8197G_SUPPORT)\n\t#include \"rtl8197g/halhwimg8197g_mac.h\"\n\t#include \"rtl8197g/halhwimg8197g_bb.h\"\n\t#include \"rtl8197g/phydm_regconfig8197g.h\"\n\t#include \"halrf/rtl8197g/halrf_8197g.h\"\n\t#include \"halrf/rtl8197g/halhwimg8197g_rf.h\"\n\t#include \"rtl8197g/phydm_hal_api8197g.h\"\n\t#include \"rtl8197g/version_rtl8197g.h\"\n#endif\n#endif /* @__ODM_PRECOMP_H__ */\n"
  },
  {
    "path": "hal/phydm/phydm_primary_cca.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*************************************************************\n * include files\n ************************************************************/\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n#ifdef PHYDM_PRIMARY_CCA\n\nvoid phydm_write_dynamic_cca(\n\tvoid *dm_void,\n\tu8 curr_mf_state\n\n\t)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;\n\n\tif (pri_cca->mf_state == curr_mf_state)\n\t\treturn;\n\n\tif (dm->support_ic_type & ODM_IC_11N_SERIES) {\n\t\tif (curr_mf_state == MF_USC_LSC) {\n\t\t\todm_set_bb_reg(dm, R_0xc6c, 0x180, MF_USC_LSC);\n\t\t\t/*@40M OFDM MF CCA threshold*/\n\t\t\todm_set_bb_reg(dm, R_0xc84, 0xf0000000,\n\t\t\t\t       pri_cca->cca_th_40m_bkp);\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0xc6c, 0x180, curr_mf_state);\n\t\t\t/*@40M OFDM MF CCA threshold*/\n\t\t\todm_set_bb_reg(dm, R_0xc84, 0xf0000000, 0);\n\t\t}\n\t}\n\n\tpri_cca->mf_state = curr_mf_state;\n\tPHYDM_DBG(dm, DBG_PRI_CCA, \"Set CCA at ((%s SB)), 0xc6c[8:7]=((%d))\\n\",\n\t\t  ((curr_mf_state == MF_USC_LSC) ? \"D\" :\n\t\t  ((curr_mf_state == MF_LSC) ? \"L\" : \"U\")), curr_mf_state);\n}\n\nvoid phydm_primary_cca_reset(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;\n\n\tPHYDM_DBG(dm, DBG_PRI_CCA, \"[PriCCA] Reset\\n\");\n\tpri_cca->mf_state = 0xff;\n\tpri_cca->pre_bw = (enum channel_width)0xff;\n\tphydm_write_dynamic_cca(dm, MF_USC_LSC);\n}\n\nvoid phydm_primary_cca_11n(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;\n\tenum channel_width curr_bw = (enum channel_width)*dm->band_width;\n\n\tif (!(dm->support_ability & ODM_BB_PRIMARY_CCA))\n\t\treturn;\n\n\tif (!dm->is_linked) {\n\t\tPHYDM_DBG(dm, DBG_PRI_CCA, \"[PriCCA][No Link!!!]\\n\");\n\n\t\tif (pri_cca->pri_cca_is_become_linked) {\n\t\t\tphydm_primary_cca_reset(dm);\n\t\t\tpri_cca->pri_cca_is_become_linked = dm->is_linked;\n\t\t}\n\t\treturn;\n\t} else {\n\t\tif (!pri_cca->pri_cca_is_become_linked) {\n\t\t\tPHYDM_DBG(dm, DBG_PRI_CCA, \"[PriCCA][Linked !!!]\\n\");\n\t\t\tpri_cca->pri_cca_is_become_linked = dm->is_linked;\n\t\t}\n\t}\n\n\tif (curr_bw != pri_cca->pre_bw) {\n\t\tPHYDM_DBG(dm, DBG_PRI_CCA, \"[Primary CCA] start ==>\\n\");\n\t\tpri_cca->pre_bw = curr_bw;\n\n\t\tif (curr_bw == CHANNEL_WIDTH_40) {\n\t\t\tif (*dm->sec_ch_offset == SECOND_CH_AT_LSB) {\n\t\t\t/* Primary CH @ upper sideband*/\n\t\t\t\tPHYDM_DBG(dm, DBG_PRI_CCA,\n\t\t\t\t\t  \"BW40M, Primary CH at USB\\n\");\n\t\t\t\tphydm_write_dynamic_cca(dm, MF_USC);\n\t\t\t} else {\n\t\t\t/*Primary CH @ lower sideband*/\n\t\t\t\tPHYDM_DBG(dm, DBG_PRI_CCA,\n\t\t\t\t\t  \"BW40M, Primary CH at LSB\\n\");\n\t\t\t\tphydm_write_dynamic_cca(dm, MF_LSC);\n\t\t\t}\n\t\t} else {\n\t\t\tPHYDM_DBG(dm, DBG_PRI_CCA, \"Not BW40M, USB + LSB\\n\");\n\t\t\tphydm_primary_cca_reset(dm);\n\t\t}\n\t}\n}\n\nboolean\nodm_dynamic_primary_cca_dup_rts(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;\n\n\treturn pri_cca->dup_rts_flag;\n}\n\nvoid phydm_primary_cca_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;\n\n\tif (!(dm->support_ability & ODM_BB_PRIMARY_CCA))\n\t\treturn;\n\n\tif (!(dm->support_ic_type & ODM_IC_11N_SERIES))\n\t\treturn;\n\n\tPHYDM_DBG(dm, DBG_PRI_CCA, \"[PriCCA] Init ==>\\n\");\n#if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1)\n\tpri_cca->dup_rts_flag = 0;\n\tpri_cca->intf_flag = 0;\n\tpri_cca->intf_type = 0;\n\tpri_cca->monitor_flag = 0;\n\tpri_cca->pri_cca_flag = 0;\n\tpri_cca->ch_offset = 0;\n#endif\n\tpri_cca->mf_state = 0xff;\n\tpri_cca->pre_bw = (enum channel_width)0xff;\n\tpri_cca->cca_th_40m_bkp = (u8)odm_get_bb_reg(dm, R_0xc84, 0xf0000000);\n}\n\nvoid phydm_primary_cca(void *dm_void)\n{\n#ifdef PHYDM_PRIMARY_CCA\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (!(dm->support_ic_type & ODM_IC_11N_SERIES))\n\t\treturn;\n\n\tif (!(dm->support_ability & ODM_BB_PRIMARY_CCA))\n\t\treturn;\n\n\tphydm_primary_cca_11n(dm);\n\n#endif\n}\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_primary_cca.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDM_PRIMARYCCA_H__\n#define __PHYDM_PRIMARYCCA_H__\n\n#ifdef PHYDM_PRIMARY_CCA\n#define PRIMARYCCA_VERSION \"2.0\"\n\n/*@============================================================*/\n/*@Definition */\n/*@============================================================*/\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n#define\tSECOND_CH_AT_LSB\t2\t/*@primary CH @ MSB,  SD4: HAL_PRIME_CHNL_OFFSET_UPPER*/\n#define\tSECOND_CH_AT_USB\t1\t/*@primary CH @ LSB,   SD4: HAL_PRIME_CHNL_OFFSET_LOWER*/\n#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#define\tSECOND_CH_AT_LSB\t2\t/*@primary CH @ MSB,  SD7: HAL_PRIME_CHNL_OFFSET_UPPER*/\n#define\tSECOND_CH_AT_USB\t1\t/*@primary CH @ LSB,   SD7: HAL_PRIME_CHNL_OFFSET_LOWER*/\n#else /*if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/\n#define\tSECOND_CH_AT_LSB\t1\t/*@primary CH @ MSB,  SD8: HT_2NDCH_OFFSET_BELOW*/\n#define\tSECOND_CH_AT_USB\t2\t/*@primary CH @ LSB,   SD8: HT_2NDCH_OFFSET_ABOVE*/\n#endif\n\n#define\tOFDMCCA_TH\t\t500\n#define\tbw_ind_bias\t\t500\n#define\tPRI_CCA_MONITOR_TIME\t30\n\n/*@============================================================*/\n/*structure and define*/\n/*@============================================================*/\nenum primary_cca_ch_position { /*N-series REG0xc6c[8:7]*/\n\tMF_USC_LSC\t= 0,\n\tMF_LSC\t\t= 1,\n\tMF_USC\t\t= 2\n};\n\nstruct phydm_pricca_struct {\n\t#if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1)\n\tu8\tpri_cca_flag;\n\tu8\tintf_flag;\n\tu8\tintf_type;\n\tu8\tmonitor_flag;\n\tu8\tch_offset;\n\t#endif\n\tu8\tdup_rts_flag;\n\tu8\tcca_th_40m_bkp; /*@c84[31:28]*/\n\tenum channel_width\tpre_bw;\n\tu8\tpri_cca_is_become_linked;\n\tu8\tmf_state;\n};\n\n/*@============================================================*/\n/*@function prototype*/\n/*@============================================================*/\nvoid phydm_write_dynamic_cca(void *dm_void, u8 curr_mf_state);\n\nboolean odm_dynamic_primary_cca_dup_rts(void *dm_void);\n\nvoid phydm_primary_cca_init(void *dm_void);\n\nvoid phydm_primary_cca(void *dm_void);\n#endif /*@#ifdef PHYDM_PRIMARY_CCA*/\n#endif /*@#ifndef\t__PHYDM_PRIMARYCCA_H__*/\n\n"
  },
  {
    "path": "hal/phydm/phydm_psd.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/******************************************************************************\n * include files\n *****************************************************************************/\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#ifdef CONFIG_PSD_TOOL\nu32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct psd_info *dm_psd_table = &dm->dm_psd_table;\n\tu32 psd_report = 0;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\todm_set_bb_reg(dm, R_0x1e8c, 0x3ff, psd_tone_idx & 0x3ff);\n\t\todm_set_bb_reg(dm, R_0x1e88, BIT(27) | BIT(26),\n\t\t\t       psd_tone_idx >> 10);\n\t\t/*PSD trigger start*/\n\t\todm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 1);\n\t\tODM_delay_us(10);\n\t\t/*PSD trigger stop*/\n\t\todm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 0);\n\t} else if (dm->support_ic_type == ODM_RTL8721D) {\n\t\todm_set_bb_reg(dm, dm_psd_table->psd_reg, 0xfff, psd_tone_idx);\n\t\todm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 1);\n\t\t/*PSD trigger start*/\n\t\tODM_delay_us(10);\n\t\todm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 0);\n\t\t/*PSD trigger stop*/\n\t} else {\n\t\todm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff, psd_tone_idx);\n\t\t/*PSD trigger start*/\n\t\todm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 1);\n\t\tODM_delay_us(10);\n\t\t/*PSD trigger stop*/\n\t\todm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 0);\n\t}\n\n\t/*Get PSD Report*/\n\tif (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D)) {\n\t\tpsd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,\n\t\t\t\t\t    0xffffff);\n\t\tpsd_report = psd_report >> 5;\n\t} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tpsd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,\n\t\t\t\t\t    0xffffff);\n\t} else {\n\t\tpsd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,\n\t\t\t\t\t    0xffff);\n\t}\n\tpsd_report = odm_convert_to_db((u64)psd_report) + igi;\n\n\treturn psd_report;\n}\n\nu8 psd_result_cali_tone_8821[7] = {21, 28, 33, 93, 98, 105, 127};\nu8 psd_result_cali_val_8821[7] = {67, 69, 71, 72, 71, 69, 67};\n\nu8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct psd_info *dm_psd_table = &dm->dm_psd_table;\n\tu32 i = 0, mod_tone_idx = 0;\n\tu32 t = 0;\n\tu16 fft_max_half_bw = 0;\n\tu16 psd_fc_channel = dm_psd_table->psd_fc_channel;\n\tu8 ag_rf_mode_reg = 0;\n\tu8 is_5G = 0;\n\tu32 psd_result_tmp = 0;\n\tu8 psd_result = 0;\n\tu8 psd_result_cali_tone[7] = {0};\n\tu8 psd_result_cali_val[7] = {0};\n\tu8 noise_idx = 0;\n\tu8 set_result = 0;\n\tu32 igi_tmp = 0x6e;\n\n\tif (dm->support_ic_type == ODM_RTL8821) {\n\t\todm_move_memory(dm, psd_result_cali_tone,\n\t\t\t\tpsd_result_cali_tone_8821, 7);\n\t\todm_move_memory(dm, psd_result_cali_val,\n\t\t\t\tpsd_result_cali_val_8821, 7);\n\t}\n\n\tdm_psd_table->psd_in_progress = 1;\n\n\tPHYDM_DBG(dm, ODM_COMP_API, \"PSD Start =>\\n\");\n\n\t/* @[Stop DIG]*/\n\t/* @IGI target at 0dBm & make it can't CCA*/\n\tif (phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_3, 1,\n\t\t\t     &igi_tmp) == PAUSE_FAIL) {\n\t\treturn PHYDM_SET_FAIL;\n\t}\n\n\tODM_delay_us(10);\n\n\tif (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {\n\t\tphydm_pause_func(dm, F00_DIG, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_3,\n\t\t\t\t 1, &igi_tmp);\n\t\treturn PHYDM_SET_FAIL;\n\t}\n\n\t/* @[Set IGI]*/\n\tphydm_write_dig_reg(dm, (u8)igi);\n\n\t/* @[Backup RF Reg]*/\n\tdm_psd_table->rf_0x18_bkp = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18,\n\t\t\t\t\t\t   RFREG_MASK);\n\tdm_psd_table->rf_0x18_bkp_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0x18,\n\t\t\t\t\t\t     RFREG_MASK);\n\n\tif (psd_fc_channel > 14) {\n\t\tis_5G = 1;\n\t\tif (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |\n\t\t\t\t\t   ODM_RTL8197G)) {\n\t\t\tif (psd_fc_channel < 80)\n\t\t\t\tag_rf_mode_reg = 0x1;\n\t\t\telse if (psd_fc_channel >= 80 && psd_fc_channel <= 140)\n\t\t\t\tag_rf_mode_reg = 0x3;\n\t\t\telse if (psd_fc_channel > 140)\n\t\t\t\tag_rf_mode_reg = 0x5;\n\t\t} else if (dm->support_ic_type == ODM_RTL8721D) {\n\t\t\tif (psd_fc_channel >= 36 && psd_fc_channel <= 64)\n\t\t\t\tag_rf_mode_reg = 0x1;\n\t\t\telse if (psd_fc_channel >= 100 && psd_fc_channel <= 140)\n\t\t\t\tag_rf_mode_reg = 0x5;\n\t\t\telse if (psd_fc_channel > 140)\n\t\t\t\tag_rf_mode_reg = 0x9;\n\t\t} else {\n\t\t\tif (psd_fc_channel >= 36 && psd_fc_channel <= 64)\n\t\t\t\tag_rf_mode_reg = 0x1;\n\t\t\telse if (psd_fc_channel >= 100 && psd_fc_channel <= 140)\n\t\t\t\tag_rf_mode_reg = 0x3;\n\t\t\telse if (psd_fc_channel > 140)\n\t\t\t\tag_rf_mode_reg = 0x5;\n\t\t}\n\t}\n\n\t/* Set RF fc*/\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff, psd_fc_channel);\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xff, psd_fc_channel);\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x300, is_5G);\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x300, is_5G);\n\tif (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |\n\t\t\t\t   ODM_RTL8197G)) {\n\t\t/* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x3000,\n\t\t\t       dm_psd_table->psd_bw_rf_reg);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x3000,\n\t\t\t       dm_psd_table->psd_bw_rf_reg);\n\t\t/* Set RF ag fc mode*/\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x70000,\n\t\t\t       ag_rf_mode_reg);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x70000,\n\t\t\t       ag_rf_mode_reg);\n\t} else {\n\t\t/* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */\n\t\tif (dm->support_ic_type == ODM_RTL8721D) {\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x1c00,\n\t\t\t\t       dm_psd_table->psd_bw_rf_reg);\n\t\t} else {\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xc00,\n\t\t\t\t       dm_psd_table->psd_bw_rf_reg);\n\t\t}\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xc00,\n\t\t\t\t       dm_psd_table->psd_bw_rf_reg);\n\t\t\t/* Set RF ag fc mode*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xf0000,\n\t\t\t\t       ag_rf_mode_reg);\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xf0000,\n\t\t\t\t       ag_rf_mode_reg);\n\t}\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"0x1d70=((0x%x))\\n\",\n\t\t\t  odm_get_bb_reg(dm, R_0x1d70, MASKDWORD));\n\telse\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"0xc50=((0x%x))\\n\",\n\t\t\t  odm_get_bb_reg(dm, R_0xc50, MASKDWORD));\n\n\tPHYDM_DBG(dm, ODM_COMP_API, \"RF0x18=((0x%x))\\n\",\n\t\t  odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK));\n\n\t/* @[Stop 3-wires]*/\n\tphydm_stop_3_wire(dm, PHYDM_SET);\n\n\tODM_delay_us(10);\n\n\tif (stop_point > (dm_psd_table->fft_smp_point - 1))\n\t\tstop_point = (dm_psd_table->fft_smp_point - 1);\n\n\tif (start_point > (dm_psd_table->fft_smp_point - 1))\n\t\tstart_point = (dm_psd_table->fft_smp_point - 1);\n\n\tif (start_point > stop_point)\n\t\tstop_point = start_point;\n\n\tfor (i = start_point; i <= stop_point; i++) {\n\t\tfft_max_half_bw = (dm_psd_table->fft_smp_point) >> 1;\n\n\t\tif (i < fft_max_half_bw)\n\t\t\tmod_tone_idx = i + fft_max_half_bw;\n\t\telse\n\t\t\tmod_tone_idx = i - fft_max_half_bw;\n\n\t\tpsd_result_tmp = 0;\n\t\tfor (t = 0; t < dm_psd_table->sw_avg_time; t++)\n\t\t\tpsd_result_tmp += phydm_get_psd_data(dm, mod_tone_idx,\n\t\t\t\t\t\t\t     igi);\n\t\tpsd_result =\n\t\t\t(u8)((psd_result_tmp / dm_psd_table->sw_avg_time)) -\n\t\t\tdm_psd_table->psd_pwr_common_offset;\n\n\t\tif (dm_psd_table->fft_smp_point == 128 &&\n\t\t    dm_psd_table->noise_k_en) {\n\t\t\tif (i > psd_result_cali_tone[noise_idx])\n\t\t\t\tnoise_idx++;\n\n\t\t\tif (noise_idx > 6)\n\t\t\t\tnoise_idx = 6;\n\n\t\t\tif (psd_result >= psd_result_cali_val[noise_idx])\n\t\t\t\tpsd_result = psd_result -\n\t\t\t\t\t     psd_result_cali_val[noise_idx];\n\t\t\telse\n\t\t\t\tpsd_result = 0;\n\n\t\t\tdm_psd_table->psd_result[i] = psd_result;\n\t\t}\n\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[%d] N_cali = %d, PSD = %d\\n\",\n\t\t\t  mod_tone_idx, psd_result_cali_val[noise_idx],\n\t\t\t  psd_result);\n\t}\n\n\t/*@[Start 3-wires]*/\n\tphydm_stop_3_wire(dm, PHYDM_REVERT);\n\n\tODM_delay_us(10);\n\n\t/*@[Revert Reg]*/\n\tset_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);\n\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK,\n\t\t       dm_psd_table->rf_0x18_bkp);\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0x18, RFREG_MASK,\n\t\t       dm_psd_table->rf_0x18_bkp_b);\n\n\tPHYDM_DBG(dm, ODM_COMP_API, \"PSD finished\\n\\n\");\n\n\tphydm_pause_func(dm, F00_DIG, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_3, 1,\n\t\t\t &igi_tmp);\n\tdm_psd_table->psd_in_progress = 0;\n\n\treturn PHYDM_SET_SUCCESS;\n}\n\nvoid phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,\n\t\t\t    u8 i_q_setting, u16 fft_smp_point, u8 ant_sel,\n\t\t\t    u8 psd_input, u8 channel, u8 noise_k_en)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct psd_info *dm_psd_table = &dm->dm_psd_table;\n\tu8 fft_smp_point_idx = 0;\n\n\tdm_psd_table->fft_smp_point = fft_smp_point;\n\n\tif (sw_avg_time == 0)\n\t\tsw_avg_time = 1;\n\n\tdm_psd_table->sw_avg_time = sw_avg_time;\n\tdm_psd_table->psd_fc_channel = channel;\n\tdm_psd_table->noise_k_en = noise_k_en;\n\n\tif (fft_smp_point == 128)\n\t\tfft_smp_point_idx = 0;\n\telse if (fft_smp_point == 256)\n\t\tfft_smp_point_idx = 1;\n\telse if (fft_smp_point == 512)\n\t\tfft_smp_point_idx = 2;\n\telse if (fft_smp_point == 1024)\n\t\tfft_smp_point_idx = 3;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\todm_set_bb_reg(dm, R_0x1e8c, BIT(11) | BIT(10), i_q_setting);\n\t\todm_set_bb_reg(dm, R_0x1e8c, BIT(13) | BIT(12), hw_avg_time);\n\n\t\tif (fft_smp_point == 4096) {\n\t\t\todm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x2);\n\t\t} else if (fft_smp_point == 2048) {\n\t\t\todm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x1);\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x0);\n\t\t\todm_set_bb_reg(dm, R_0x1e8c, BIT(15) | BIT(14),\n\t\t\t\t       fft_smp_point_idx);\n\t\t}\n\t\todm_set_bb_reg(dm, R_0x1e8c, BIT(17) | BIT(16), ant_sel);\n\t\todm_set_bb_reg(dm, R_0x1e8c, BIT(23) | BIT(22), psd_input);\n\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\todm_set_bb_reg(dm, R_0x910, BIT(11) | BIT(10), i_q_setting);\n\t\todm_set_bb_reg(dm, R_0x910, BIT(13) | BIT(12), hw_avg_time);\n\t\todm_set_bb_reg(dm, R_0x910, BIT(15) | BIT(14),\n\t\t\t       fft_smp_point_idx);\n\t\todm_set_bb_reg(dm, R_0x910, BIT(17) | BIT(16), ant_sel);\n\t\todm_set_bb_reg(dm, R_0x910, BIT(23), psd_input);\n\t} else if (dm->support_ic_type == ODM_RTL8721D) {\n\t\todm_set_bb_reg(dm, 0x808, BIT(19) | BIT(18), i_q_setting);\n\t\todm_set_bb_reg(dm, 0x808, BIT(21) | BIT(20), hw_avg_time);\n\t\todm_set_bb_reg(dm, 0x808, BIT(23) | BIT(22), fft_smp_point_idx);\n\t\todm_set_bb_reg(dm, 0x804, BIT(5) | BIT(4), ant_sel);\n\t\todm_set_bb_reg(dm, 0x80C, BIT(23), psd_input);\n\n#if 0\n\t} else {\t/*ODM_IC_11N_SERIES*/\n#endif\n\t}\n\t/*@bw = (*dm->band_width); //ODM_BW20M */\n\t/*@channel = *(dm->channel);*/\n}\n\nvoid phydm_psd_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct psd_info *dm_psd_table = &dm->dm_psd_table;\n\n\tPHYDM_DBG(dm, ODM_COMP_API, \"PSD para init\\n\");\n\n\tdm_psd_table->psd_in_progress = false;\n\n\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES) {\n\t\tdm_psd_table->psd_reg = R_0x1e8c;\n\t\tdm_psd_table->psd_report_reg = R_0x2d90;\n\n\t\t/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */\n\t\tdm_psd_table->psd_bw_rf_reg = 1;\n\t} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {\n\t\tdm_psd_table->psd_reg = R_0x910;\n\t\tdm_psd_table->psd_report_reg = R_0xf44;\n\n\t\t/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */\n\t\tif (ODM_IC_11AC_2_SERIES)\n\t\t\tdm_psd_table->psd_bw_rf_reg = 1;\n\t\telse\n\t\t\tdm_psd_table->psd_bw_rf_reg = 2;\n\t} else {\n\t\tdm_psd_table->psd_reg = R_0x808;\n\t\tdm_psd_table->psd_report_reg = R_0x8b4;\n\t\t/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */\n\t\tdm_psd_table->psd_bw_rf_reg = 2;\n\t}\n\n\tdm_psd_table->psd_pwr_common_offset = 0;\n\n\tphydm_psd_para_setting(dm, 1, 2, 3, 128, 0, 0, 7, 0);\n#if 0\n\t/*phydm_psd(dm, 0x3c, 0, 127);*/ /* target at -50dBm */\n#endif\n}\n\nvoid phydm_psd_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t     char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tchar help[] = \"-h\";\n\tu32 var1[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu8 i = 0;\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\tif (dm->support_ic_type & ODM_IC_JGR3_SERIES)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4) 2048 4096}\\n{path_sel 0~3} {0:ADC, 1:rxdata_fir_in, 2:rx_nbi_nf_stage2} {CH} {noise_k}\\n\\n\");\n\t\telse\n\t\t#endif\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\\n\");\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{1} {IGI(hex)} {start_point} {stop_point}\\n\");\n\t\tgoto out;\n\t}\n\n\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);\n\n\tif (var1[0] == 0) {\n\t\tfor (i = 1; i < 10; i++) {\n\t\t\tif (input[i + 1])\n\t\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,\n\t\t\t\t\t     &var1[i]);\n\t\t}\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\\n\",\n\t\t\t var1[1], var1[2], var1[3], var1[4], var1[5],\n\t\t\t var1[6], (u8)var1[7], (u8)var1[8]);\n\t\tphydm_psd_para_setting(dm, (u8)var1[1], (u8)var1[2],\n\t\t\t\t       (u8)var1[3], (u16)var1[4],\n\t\t\t\t       (u8)var1[5], (u8)var1[6],\n\t\t\t\t       (u8)var1[7], (u8)var1[8]);\n\n\t} else if (var1[0] == 1) {\n\t\tPHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);\n\t\tPHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);\n\t\tPHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\\n\",\n\t\t\t var1[1], var1[2], var1[3]);\n\t\tdm->debug_components |= ODM_COMP_API;\n\t\tif (phydm_psd(dm, var1[1], (u16)var1[2], (u16)var1[3]) ==\n\t\t    PHYDM_SET_FAIL)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"PSD_SET_FAIL\\n\");\n\t\tdm->debug_components &= ~(ODM_COMP_API);\n\t}\n\nout:\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nu8 phydm_get_psd_result_table(void *dm_void, int index)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct psd_info *dm_psd_table = &dm->dm_psd_table;\n\tu8 result = 0;\n\n\tif (index < 128)\n\t\tresult = dm_psd_table->psd_result[index];\n\n\treturn result;\n}\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_psd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDMPSD_H__\n#define __PHYDMPSD_H__\n\n/*@#define PSD_VERSION\t\"1.0\"*/ /*@2016.09.22  Dino*/\n#define PSD_VERSION \"1.1\" /*@2016.10.07  Dino, Add Option for PSD Tone index Selection */\n\n#ifdef CONFIG_PSD_TOOL\n\n\nstruct psd_info {\n\tu8\tpsd_in_progress;\n\tu32\tpsd_reg;\n\tu32\tpsd_report_reg;\n\tu8\tpsd_pwr_common_offset;\n\tu16\tsw_avg_time;\n\tu16\tfft_smp_point;\n\tu32\trf_0x18_bkp;\n\tu32\trf_0x18_bkp_b;\n\tu16\tpsd_fc_channel;\n\tu32\tpsd_bw_rf_reg;\n\tu8\tpsd_result[128];\n\tu8\tnoise_k_en;\n};\n\nu32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi);\n\nvoid phydm_psd_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t     char *output, u32 *_out_len);\n\nu8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point);\n\nvoid phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,\n\t\t\t    u8 i_q_setting, u16 fft_smp_point, u8 ant_sel,\n\t\t\t    u8 psd_input, u8 channel, u8 noise_k_en);\n\nvoid phydm_psd_init(void *dm_void);\n\nu8 phydm_get_psd_result_table(void *dm_void, int index);\n\n#endif\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_rainfo.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n ************************************************************/\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\nboolean phydm_is_vht_rate(void *dm_void, u8 rate)\n{\n\treturn ((rate & 0x7f) >= ODM_RATEVHTSS1MCS0) ? true : false;\n}\n\nboolean phydm_is_ht_rate(void *dm_void, u8 rate)\n{\n\treturn (((rate & 0x7f) >= ODM_RATEMCS0) &&\n\t\t((rate & 0x7f) <= ODM_RATEMCS31)) ? true : false;\n}\n\nboolean phydm_is_ofdm_rate(void *dm_void, u8 rate)\n{\n\treturn (((rate & 0x7f) >= ODM_RATE6M) &&\n\t\t((rate & 0x7f) <= ODM_RATE54M)) ? true : false;\n}\n\nboolean phydm_is_cck_rate(void *dm_void, u8 rate)\n{\n\treturn ((rate & 0x7f) <= ODM_RATE11M) ? true : false;\n}\n\nu8 phydm_rate_2_rate_digit(void *dm_void, u8 rate)\n{\n\tu8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54};\n\tu8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/\n\tu8 rate_digit = 0;\n\n\tif (rate_idx >= ODM_RATEVHTSS1MCS0)\n\t\trate_digit = (rate_idx - ODM_RATEVHTSS1MCS0) % 10;\n\telse if (rate_idx >= ODM_RATEMCS0)\n\t\trate_digit = (rate_idx - ODM_RATEMCS0);\n\telse if (rate_idx <= ODM_RATE54M)\n\t\trate_digit = legacy_table[rate_idx];\n\n\treturn rate_digit;\n}\n\nu8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type)\n{\n\tu8 num_ss = 1;\n\n\tswitch (type) {\n\tcase PDM_CCK:\n\tcase PDM_OFDM:\n\tcase PDM_1SS:\n\t\tnum_ss = 1;\n\t\tbreak;\n\tcase PDM_2SS:\n\t\tnum_ss = 2;\n\t\tbreak;\n\tcase PDM_3SS:\n\t\tnum_ss = 3;\n\t\tbreak;\n\tcase PDM_4SS:\n\t\tnum_ss = 4;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn num_ss;\n}\n\nu8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate)\n{\n\tu8 num_ss = 1;\n\n\tif (data_rate <= ODM_RATE54M)\n\t\tnum_ss = 1;\n\telse if (data_rate <= ODM_RATEMCS31)\n\t\tnum_ss = ((data_rate - ODM_RATEMCS0) >> 3) + 1;\n\telse if (data_rate <= ODM_RATEVHTSS1MCS9)\n\t\tnum_ss = 1;\n\telse if (data_rate <= ODM_RATEVHTSS2MCS9)\n\t\tnum_ss = 2;\n\telse if (data_rate <= ODM_RATEVHTSS3MCS9)\n\t\tnum_ss = 3;\n\telse if (data_rate <= ODM_RATEVHTSS4MCS9)\n\t\tnum_ss = 4;\n\n\treturn num_ss;\n}\n\nvoid phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t     char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 dm_value[10] = {0};\n\tu8 i = 0, input_idx = 0;\n\tu8 h2c_parameter[H2C_MAX_LENGTH] = {0};\n\tu8 phydm_h2c_id = 0;\n\n\tfor (i = 0; i < 8; i++) {\n\t\tif (input[i + 1]) {\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);\n\t\t\tinput_idx++;\n\t\t}\n\t}\n\n\tif (input_idx == 0)\n\t\treturn;\n\n\tphydm_h2c_id = (u8)dm_value[0];\n\n\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t \"Phydm Send H2C_ID (( 0x%x))\\n\", phydm_h2c_id);\n\n\tfor (i = 0; i < H2C_MAX_LENGTH; i++) {\n\t\th2c_parameter[i] = (u8)dm_value[i + 1];\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"H2C: Byte[%d] = ((0x%x))\\n\", i, h2c_parameter[i]);\n\t}\n\n\todm_fill_h2c_cmd(dm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter);\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_fw_fix_rate(void *dm_void, u8 en, u8 macid, u8 bw, u8 rate)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 reg_u32_tmp;\n\n\tif (dm->support_ic_type & PHYDM_IC_8051_SERIES) {\n\t\treg_u32_tmp = (bw << 24) | (rate << 16) | (macid << 8) | en;\n\t\todm_set_bb_reg(dm, R_0x4a0, MASKDWORD, reg_u32_tmp);\n\n\t} else {\n\t\tif (en == 1)\n\t\t\treg_u32_tmp = BYTE_2_DWORD(0x60, macid, bw, rate);\n\t\telse\n\t\t\treg_u32_tmp = 0x40000000;\n\t\tif (dm->support_ic_type & ODM_RTL8814B)\n\t\t\todm_set_bb_reg(dm, R_0x448, MASKDWORD, reg_u32_tmp);\n\t\telse\n\t\t\todm_set_bb_reg(dm, R_0x450, MASKDWORD, reg_u32_tmp);\n\t}\n\tif (en == 1) {\n\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t  \"FW fix TX rate[id =%d], %dM, Rate(%d)=\", macid,\n\t\t\t  (20 << bw), rate);\n\t\tphydm_print_rate(dm, rate, ODM_COMP_API);\n\t} else {\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"Auto Rate\\n\");\n\t}\n}\n\nvoid phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t    u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra_tab = &dm->dm_ra_table;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tchar help[] = \"-h\";\n\tu32 var[5] = {0};\n\tu8 macid = 0, bw = 0, rate = 0;\n\tu8 i = 0;\n\n\tfor (i = 0; i < 5; i++) {\n\t\tif (input[i + 1])\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]);\n\t}\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{1} {0:-,1:+} {ofst}: set offset\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{1} {100}: show offset\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{2} {en} {macid} {bw} {rate}: fw fix rate\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{3} {en}: Dynamic RRSR\\n\");\n\n\t} else if (var[0] == 1) { /*@Adjust PCR offset*/\n\n\t\tif (var[1] == 100) {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[Get] RA_ofst=((%s%d))\\n\",\n\t\t\t\t ((ra_tab->ra_ofst_direc) ? \"+\" : \"-\"),\n\t\t\t\t ra_tab->ra_th_ofst);\n\n\t\t} else if (var[1] == 0) {\n\t\t\tra_tab->ra_ofst_direc = 0;\n\t\t\tra_tab->ra_th_ofst = (u8)var[2];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[Set] RA_ofst=((-%d))\\n\", ra_tab->ra_th_ofst);\n\t\t} else if (var[1] == 1) {\n\t\t\tra_tab->ra_ofst_direc = 1;\n\t\t\tra_tab->ra_th_ofst = (u8)var[2];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[Set] RA_ofst=((+%d))\\n\", ra_tab->ra_th_ofst);\n\t\t}\n\n\t} else if (var[0] == 2) { /*@FW fix rate*/\n\t\tmacid = (u8)var[2];\n\t\tbw = (u8)var[3];\n\t\trate = (u8)var[4];\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[FW fix TX Rate] {en, macid,bw,rate}={%d, %d, %d, 0x%x}\",\n\t\t\t var[1], macid, bw, rate);\n\n\t\tphydm_fw_fix_rate(dm, (u8)var[1], macid, bw, rate);\n\t} else if (var[0] == 3) { /*@FW fix rate*/\n\t\tra_tab->dynamic_rrsr_en = (boolean)var[1];\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[Dynamic RRSR] enable=%d\", ra_tab->dynamic_rrsr_en);\n\t} else {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[Set] Error\\n\");\n\t}\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 mode = cmd_buf[0]; /*Retry Penalty, NH, NL*/\n\tu8 i;\n\n\tPHYDM_DBG(dm, DBG_FW_TRACE, \"[%s] [mode: %d]----------------------->\\n\",\n\t\t  __func__, mode);\n\n\tif (mode == RADBG_DEBUG_MONITOR1) {\n\t\tif (dm->support_ic_type & PHYDM_IC_3081_SERIES) {\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  %d\\n\", \"RSSI =\",\n\t\t\t\t  cmd_buf[1]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  0x%x\\n\", \"rate =\",\n\t\t\t\t  cmd_buf[2] & 0x7f);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  %d\\n\", \"SGI =\",\n\t\t\t\t  (cmd_buf[2] & 0x80) >> 7);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  %d\\n\", \"BW =\",\n\t\t\t\t  cmd_buf[3]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  %d\\n\", \"BW_max =\",\n\t\t\t\t  cmd_buf[4]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  0x%x\\n\",\n\t\t\t\t  \"multi_rate0 =\", cmd_buf[5]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  0x%x\\n\",\n\t\t\t\t  \"multi_rate1 =\", cmd_buf[6]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  %d\\n\", \"DISRA =\",\n\t\t\t\t  cmd_buf[7]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  %d\\n\", \"VHT_EN =\",\n\t\t\t\t  cmd_buf[8]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  %d\\n\",\n\t\t\t\t  \"SGI_support =\", cmd_buf[9]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  %d\\n\", \"try_ness =\",\n\t\t\t\t  cmd_buf[10]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  0x%x\\n\", \"pre_rate =\",\n\t\t\t\t  cmd_buf[11]);\n\t\t} else {\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  %d\\n\", \"RSSI =\",\n\t\t\t\t  cmd_buf[1]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  %x\\n\", \"BW =\",\n\t\t\t\t  cmd_buf[2]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  %d\\n\", \"DISRA =\",\n\t\t\t\t  cmd_buf[3]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  %d\\n\", \"VHT_EN =\",\n\t\t\t\t  cmd_buf[4]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  %d\\n\",\n\t\t\t\t  \"Hightest rate =\", cmd_buf[5]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  0x%x\\n\",\n\t\t\t\t  \"Lowest rate =\", cmd_buf[6]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  0x%x\\n\",\n\t\t\t\t  \"SGI_support =\", cmd_buf[7]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  %d\\n\", \"Rate_ID =\",\n\t\t\t\t  cmd_buf[8]);\n\t\t}\n\t} else if (mode == RADBG_DEBUG_MONITOR2) {\n\t\tif (dm->support_ic_type & PHYDM_IC_3081_SERIES) {\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  %d\\n\", \"rate_id =\",\n\t\t\t\t  cmd_buf[1]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  0x%x\\n\",\n\t\t\t\t  \"highest_rate =\", cmd_buf[2]);\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  0x%x\\n\",\n\t\t\t\t  \"lowest_rate =\", cmd_buf[3]);\n\n\t\t\tfor (i = 4; i <= 11; i++)\n\t\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"RAMASK =  0x%x\\n\",\n\t\t\t\t\t  cmd_buf[i]);\n\t\t} else {\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE,\n\t\t\t\t  \"%5s  %x%x  %x%x  %x%x  %x%x\\n\", \"RA Mask:\",\n\t\t\t\t  cmd_buf[8], cmd_buf[7], cmd_buf[6],\n\t\t\t\t  cmd_buf[5], cmd_buf[4], cmd_buf[3],\n\t\t\t\t  cmd_buf[2], cmd_buf[1]);\n\t\t}\n\t} else if (mode == RADBG_DEBUG_MONITOR3) {\n\t\tfor (i = 0; i < (cmd_len - 1); i++)\n\t\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"content[%d] = %d\\n\", i,\n\t\t\t\t  cmd_buf[1 + i]);\n\t} else if (mode == RADBG_DEBUG_MONITOR4)\n\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  {%d.%d}\\n\", \"RA version =\",\n\t\t\t  cmd_buf[1], cmd_buf[2]);\n\telse if (mode == RADBG_DEBUG_MONITOR5) {\n\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  0x%x\\n\", \"Current rate =\",\n\t\t\t  cmd_buf[1]);\n\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  %d\\n\", \"Retry ratio =\",\n\t\t\t  cmd_buf[2]);\n\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  %d\\n\", \"rate down ratio =\",\n\t\t\t  cmd_buf[3]);\n\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  0x%x\\n\", \"highest rate =\",\n\t\t\t  cmd_buf[4]);\n\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  {0x%x 0x%x}\\n\", \"Muti-try =\",\n\t\t\t  cmd_buf[5], cmd_buf[6]);\n\t\tPHYDM_DBG(dm, DBG_FW_TRACE, \"%5s  0x%x%x%x%x%x\\n\", \"RA mask =\",\n\t\t\t  cmd_buf[11], cmd_buf[10], cmd_buf[9], cmd_buf[8],\n\t\t\t  cmd_buf[7]);\n\t}\n\tPHYDM_DBG(dm, DBG_FW_TRACE, \"-------------------------------\\n\");\n}\n\nvoid phydm_ra_dynamic_retry_count(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (!(dm->support_ability & ODM_BB_DYNAMIC_ARFR))\n\t\treturn;\n\n#if 0\n\t/*PHYDM_DBG(dm, DBG_RA, \"dm->pre_b_noisy = %d\\n\", dm->pre_b_noisy );*/\n#endif\n\tif (dm->pre_b_noisy != dm->noisy_decision) {\n\t\tif (dm->noisy_decision) {\n\t\t\tPHYDM_DBG(dm, DBG_DYN_ARFR, \"Noisy Env. RA fallback\\n\");\n\t\t\todm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x0);\n\t\t\todm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x04030201);\n\t\t} else {\n\t\t\tPHYDM_DBG(dm, DBG_DYN_ARFR, \"Clean Env. RA fallback\\n\");\n\t\t\todm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x01000000);\n\t\t\todm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x06050402);\n\t\t}\n\t\tdm->pre_b_noisy = dm->noisy_decision;\n\t}\n}\n\nvoid phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/\n\tboolean vht_en = phydm_is_vht_rate(dm, rate_idx);\n\tu8 b_sgi = (rate & 0x80) >> 7;\n\tu8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx);\n\tu8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx);\n\n\tPHYDM_DBG_F(dm, dbg_component, \"( %s%s%s%s%s%d%s%s)\\n\",\n\t\t    (vht_en && (rate_ss == 1)) ? \"VHT 1ss \" : \"\",\n\t\t    (vht_en && (rate_ss == 2)) ? \"VHT 2ss \" : \"\",\n\t\t    (vht_en && (rate_ss == 3)) ? \"VHT 3ss \" : \"\",\n\t\t    (vht_en && (rate_ss == 4)) ? \"VHT 4ss \" : \"\",\n\t\t    (rate_idx >= ODM_RATEMCS0) ? \"MCS \" : \"\",\n\t\t    rate_digit,\n\t\t    (b_sgi) ? \"-S\" : \" \",\n\t\t    (rate_idx >= ODM_RATEMCS0) ? \"\" : \"M\");\n}\n\nvoid phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/\n\tboolean vht_en = phydm_is_vht_rate(dm, rate_idx);\n\tu8 b_sgi = (rate & 0x80) >> 7;\n\tu8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx);\n\tu8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx);\n\n\tPHYDM_SNPRINTF(buf, buf_size, \"( %s%s%s%s%d%s%s)\",\n\t\t       (vht_en && (rate_ss == 1)) ? \"VHT 1ss \" : \"\",\n\t\t       (vht_en && (rate_ss == 2)) ? \"VHT 2ss \" : \"\",\n\t\t       (vht_en && (rate_ss == 3)) ? \"VHT 3ss \" : \"\",\n\t\t       (rate_idx >= ODM_RATEMCS0) ? \"MCS \" : \"\",\n\t\t       rate_digit,\n\t\t       (b_sgi) ? \"-S\" : \" \",\n\t\t       (rate_idx >= ODM_RATEMCS0) ? \"\" : \"M\");\n}\n\nvoid phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra_tab = &dm->dm_ra_table;\n\tstruct cmn_sta_info *sta = NULL;\n\tu8 macid = cmd_buf[1];\n\tu8 rate = cmd_buf[0];\n\tu8 ra_ratio = 0xff;\n\tu8 curr_bw = 0xff;\n\tu8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/\n\tu8 rate_order;\n\tu8 gid_index = 0;\n\tchar dbg_buf[PHYDM_SNPRINT_SIZE] = {0};\n\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tsta = dm->phydm_sta_info[dm->phydm_macid_table[macid]];\n\t#else\n\tsta = dm->phydm_sta_info[macid];\n\t#endif\n\n\tif (cmd_len >= 7) {\n\t\tra_ratio = cmd_buf[5];\n\t\tcurr_bw = cmd_buf[6];\n\t\tPHYDM_DBG(dm, DBG_RA, \"[%d] PER=%d\\n\", macid, ra_ratio);\n\t}\n\n\tif (cmd_buf[3] != 0) {\n\t\tif (cmd_buf[3] == 0xff)\n\t\t\tPHYDM_DBG(dm, DBG_RA, \"FW Fix Rate\\n\");\n\t\telse if (cmd_buf[3] == 1)\n\t\t\tPHYDM_DBG(dm, DBG_RA, \"Try Success\\n\");\n\t\telse if (cmd_buf[3] == 2)\n\t\t\tPHYDM_DBG(dm, DBG_RA, \"Try Fail & Again\\n\");\n\t\telse if (cmd_buf[3] == 3)\n\t\t\tPHYDM_DBG(dm, DBG_RA, \"Rate Back\\n\");\n\t\telse if (cmd_buf[3] == 4)\n\t\t\tPHYDM_DBG(dm, DBG_RA, \"Start rate by RSSI\\n\");\n\t\telse if (cmd_buf[3] == 5)\n\t\t\tPHYDM_DBG(dm, DBG_RA, \"Try rate\\n\");\n\t}\n\tphydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE);\n\tPHYDM_DBG(dm, DBG_RA, \"Tx Rate=%s (%d)\", dbg_buf, rate);\n\n#ifdef MU_EX_MACID\n\tif (macid >= 128 && macid < (128 + MU_EX_MACID)) {\n\t\tgid_index = macid - 128;\n\t\tra_tab->mu1_rate[gid_index] = rate;\n\t}\n#endif\n\n\t/*@ra_tab->link_tx_rate[macid] = rate;*/\n\n\tif (is_sta_active(sta)) {\n\t\tsta->ra_info.curr_tx_rate = rate;\n\t\tsta->ra_info.curr_tx_bw = (enum channel_width)curr_bw;\n\t\tsta->ra_info.curr_retry_ratio = ra_ratio;\n\t}\n\n\t/*trigger power training*/\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\n\trate_order = phydm_rate_order_compute(dm, rate_idx);\n\n\tif (dm->is_one_entry_only ||\n\t    (rate_order > ra_tab->highest_client_tx_order &&\n\t    ra_tab->power_tracking_flag == 1)) {\n\t\thalrf_update_pwr_track(dm, rate_idx);\n\t\tra_tab->power_tracking_flag = 0;\n\t}\n\n#endif\n\n#if 0\n\t/*trigger dynamic rate ID*/\n\tif (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E))\n\t\tphydm_update_rate_id(dm, rate, macid);\n#endif\n}\n\nvoid odm_ra_post_action_on_assoc(void *dm_void)\n{\n#if 0\n\tstruct dm_struct\t*dm = (struct dm_struct *)dm_void;\n\n\tdm->h2c_rarpt_connect = 1;\n\tphydm_rssi_monitor_check(dm);\n\tdm->h2c_rarpt_connect = 0;\n#endif\n}\n\nvoid phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc,\n\t\t\t\t   u8 ra_th_ofst)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra_tab = &dm->dm_ra_table;\n\n\tra_tab->ra_ofst_direc = ra_ofst_direc;\n\tra_tab->ra_th_ofst = ra_th_ofst;\n\tPHYDM_DBG(dm, DBG_RA_MASK, \"Set ra_th_offset=(( %s%d ))\\n\",\n\t\t  ((ra_ofst_direc) ? \"+\" : \"-\"), ra_th_ofst);\n}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\nvoid phydm_gen_ramask_h2c_AP(\n\tvoid *dm_void,\n\tstruct rtl8192cd_priv *priv,\n\tstruct sta_info *entry,\n\tu8 rssi_level)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type == ODM_RTL8812) {\n\t\t#if (RTL8812A_SUPPORT == 1)\n\t\tUpdateHalRAMask8812(priv, entry, rssi_level);\n\t\t#endif\n\t} else if (dm->support_ic_type == ODM_RTL8188E) {\n\t\t#if (RTL8188E_SUPPORT == 1)\n\t\t#ifdef TXREPORT\n\t\tadd_RATid(priv, entry);\n\t\t#endif\n\t\t#endif\n\t} else {\n\t\t#ifdef CONFIG_WLAN_HAL\n\t\tGET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, entry, rssi_level);\n\t\t#endif\n\t}\n}\n\nvoid phydm_update_hal_ra_mask(\n\tvoid *dm_void,\n\tu32 wireless_mode,\n\tu8 rf_type,\n\tu8 bw,\n\tu8 mimo_ps_enable,\n\tu8 disable_cck_rate,\n\tu32 *ratr_bitmap_msb_in,\n\tu32 *ratr_bitmap_lsb_in,\n\tu8 tx_rate_level)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 ratr_bitmap = *ratr_bitmap_lsb_in;\n\tu32 ratr_bitmap_msb = *ratr_bitmap_msb_in;\n\n#if 0\n\t/*PHYDM_DBG(dm, DBG_RA_MASK, \"phydm_rf_type = (( %x )), rf_type = (( %x ))\\n\", phydm_rf_type, rf_type);*/\n#endif\n\tPHYDM_DBG(dm, DBG_RA_MASK,\n\t\t  \"Platfoem original RA Mask = (( 0x %x | %x ))\\n\",\n\t\t  ratr_bitmap_msb, ratr_bitmap);\n\n\tswitch (wireless_mode) {\n\tcase PHYDM_WIRELESS_MODE_B: {\n\t\tratr_bitmap &= 0x0000000f;\n\t} break;\n\n\tcase PHYDM_WIRELESS_MODE_G: {\n\t\tratr_bitmap &= 0x00000ff5;\n\t} break;\n\n\tcase PHYDM_WIRELESS_MODE_A: {\n\t\tratr_bitmap &= 0x00000ff0;\n\t} break;\n\n\tcase PHYDM_WIRELESS_MODE_N_24G:\n\tcase PHYDM_WIRELESS_MODE_N_5G: {\n\t\tif (mimo_ps_enable)\n\t\t\trf_type = RF_1T1R;\n\n\t\tif (rf_type == RF_1T1R) {\n\t\t\tif (bw == CHANNEL_WIDTH_40)\n\t\t\t\tratr_bitmap &= 0x000ff015;\n\t\t\telse\n\t\t\t\tratr_bitmap &= 0x000ff005;\n\t\t} else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {\n\t\t\tif (bw == CHANNEL_WIDTH_40)\n\t\t\t\tratr_bitmap &= 0x0ffff015;\n\t\t\telse\n\t\t\t\tratr_bitmap &= 0x0ffff005;\n\t\t} else { /*@3T*/\n\n\t\t\tratr_bitmap &= 0xfffff015;\n\t\t\tratr_bitmap_msb &= 0xf;\n\t\t}\n\t} break;\n\n\tcase PHYDM_WIRELESS_MODE_AC_24G: {\n\t\tif (rf_type == RF_1T1R) {\n\t\t\tratr_bitmap &= 0x003ff015;\n\t\t} else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {\n\t\t\tratr_bitmap &= 0xfffff015;\n\t\t} else { /*@3T*/\n\n\t\t\tratr_bitmap &= 0xfffff010;\n\t\t\tratr_bitmap_msb &= 0x3ff;\n\t\t}\n\n\t\tif (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/\n\t\t\tratr_bitmap &= 0x7fdfffff;\n\t\t\tratr_bitmap_msb &= 0x1ff;\n\t\t}\n\t} break;\n\n\tcase PHYDM_WIRELESS_MODE_AC_5G: {\n\t\tif (rf_type == RF_1T1R) {\n\t\t\tratr_bitmap &= 0x003ff010;\n\t\t} else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {\n\t\t\tratr_bitmap &= 0xfffff010;\n\t\t} else { /*@3T*/\n\n\t\t\tratr_bitmap &= 0xfffff010;\n\t\t\tratr_bitmap_msb &= 0x3ff;\n\t\t}\n\n\t\tif (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/\n\t\t\tratr_bitmap &= 0x7fdfffff;\n\t\t\tratr_bitmap_msb &= 0x1ff;\n\t\t}\n\t} break;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (wireless_mode != PHYDM_WIRELESS_MODE_B) {\n\t\tif (tx_rate_level == 0)\n\t\t\tratr_bitmap &= 0xffffffff;\n\t\telse if (tx_rate_level == 1)\n\t\t\tratr_bitmap &= 0xfffffff0;\n\t\telse if (tx_rate_level == 2)\n\t\t\tratr_bitmap &= 0xffffefe0;\n\t\telse if (tx_rate_level == 3)\n\t\t\tratr_bitmap &= 0xffffcfc0;\n\t\telse if (tx_rate_level == 4)\n\t\t\tratr_bitmap &= 0xffff8f80;\n\t\telse if (tx_rate_level >= 5)\n\t\t\tratr_bitmap &= 0xffff0f00;\n\t}\n\n\tif (disable_cck_rate)\n\t\tratr_bitmap &= 0xfffffff0;\n\n\tPHYDM_DBG(dm, DBG_RA_MASK,\n\t\t  \"wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\\n\",\n\t\t  wireless_mode, rf_type, bw, mimo_ps_enable, tx_rate_level);\n\n#if 0\n\t/*PHYDM_DBG(dm, DBG_RA_MASK, \"111 Phydm modified RA Mask = (( 0x %x | %x ))\\n\", ratr_bitmap_msb, ratr_bitmap);*/\n#endif\n\n\t*ratr_bitmap_lsb_in = ratr_bitmap;\n\t*ratr_bitmap_msb_in = ratr_bitmap_msb;\n\tPHYDM_DBG(dm, DBG_RA_MASK,\n\t\t  \"Phydm modified RA Mask = (( 0x %x | %x ))\\n\",\n\t\t  *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in);\n}\n\n#endif\n\nvoid phydm_rate_adaptive_mask_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra_t = &dm->dm_ra_table;\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tPADAPTER adapter = dm->adapter;\n\tPMGNT_INFO mgnt_info = &(adapter->MgntInfo);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)dm->adapter));\n\n\tif (mgnt_info->DM_Type == dm_type_by_driver)\n\t\thal_data->bUseRAMask = true;\n\telse\n\t\thal_data->bUseRAMask = false;\n\n#endif\n\n\tra_t->ldpc_thres = 35;\n\tra_t->up_ramask_cnt = 0;\n\tra_t->up_ramask_cnt_tmp = 0;\n}\n\nvoid phydm_refresh_rate_adaptive_mask(void *dm_void)\n{\n/*@Will be removed*/\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tphydm_ra_mask_watchdog(dm);\n}\n\nvoid phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used,\n\t\t\t char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct cmn_sta_info *sta = NULL;\n\tstruct ra_sta_info *ra = NULL;\n#ifdef CONFIG_BEAMFORMING\n\tstruct bf_cmn_info *bf = NULL;\n#endif\n\tchar help[] = \"-h\";\n\tu32 var[10] = {0};\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 i, sta_idx_start, sta_idx_end;\n\tu8 tatal_sta_num = 0;\n\n\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &var[0]);\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"All STA: {1}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"STA[macid]: {2} {macid}\\n\");\n\t\treturn;\n\t} else if (var[0] == 1) {\n\t\tsta_idx_start = 0;\n\t\tsta_idx_end = ODM_ASSOCIATE_ENTRY_NUM;\n\t} else if (var[0] == 2) {\n\t\tsta_idx_start = var[1];\n\t\tsta_idx_end = var[1];\n\t} else {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Warning input value!\\n\");\n\t\treturn;\n\t}\n\n\tfor (i = sta_idx_start; i < sta_idx_end; i++) {\n\t\tsta = dm->phydm_sta_info[i];\n\n\t\tif (!is_sta_active(sta))\n\t\t\tcontinue;\n\n\t\tra = &sta->ra_info;\n\t\t#ifdef CONFIG_BEAMFORMING\n\t\tbf = &sta->bf_info;\n\t\t#endif\n\n\t\ttatal_sta_num++;\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"==[sta_idx: %d][MACID: %d]============>\\n\", i,\n\t\t\t sta->mac_id);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"AID:%d\\n\", sta->aid);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"ADDR:%x-%x-%x-%x-%x-%x\\n\", sta->mac_addr[5],\n\t\t\t sta->mac_addr[4], sta->mac_addr[3], sta->mac_addr[2],\n\t\t\t sta->mac_addr[1], sta->mac_addr[0]);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"DM_ctrl:0x%x\\n\", sta->dm_ctrl);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"BW:%d, MIMO_Type:0x%x\\n\", sta->bw_mode,\n\t\t\t sta->mimo_type);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"STBC_en:%d, LDPC_en=%d\\n\", sta->stbc_en,\n\t\t\t sta->ldpc_en);\n\n\t\t/*@[RSSI Info]*/\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"RSSI{All, OFDM, CCK}={%d, %d, %d}\\n\",\n\t\t\t sta->rssi_stat.rssi, sta->rssi_stat.rssi_ofdm,\n\t\t\t sta->rssi_stat.rssi_cck);\n\n\t\t/*@[RA Info]*/\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Rate_ID:%d, RSSI_LV:%d, ra_bw:%d, SGI_en:%d\\n\",\n\t\t\t ra->rate_id, ra->rssi_level, ra->ra_bw_mode,\n\t\t\t ra->is_support_sgi);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"VHT_en:%d, Wireless_set=0x%x, sm_ps=%d\\n\",\n\t\t\t ra->is_vht_enable, sta->support_wireless_set,\n\t\t\t sta->sm_ps);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Dis{RA, PT}={%d, %d}, TxRx:%d, Noisy:%d\\n\",\n\t\t\t ra->disable_ra, ra->disable_pt, ra->txrx_state,\n\t\t\t ra->is_noisy);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"TX{Rate, BW}={0x%x, %d}, RTY:%d\\n\", ra->curr_tx_rate,\n\t\t\t ra->curr_tx_bw, ra->curr_retry_ratio);\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"RA_Mask:0x%llx\\n\", ra->ramask);\n\n\t\t/*@[TP]*/\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"TP{TX,RX}={%d, %d}\\n\", sta->tx_moving_average_tp,\n\t\t\t sta->rx_moving_average_tp);\n\n#ifdef CONFIG_BEAMFORMING\n\t\t/*@[Beamforming]*/\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"BF CAP{HT,VHT}={0x%x, 0x%x}\\n\", bf->ht_beamform_cap,\n\t\t\t bf->vht_beamform_cap);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"BF {p_aid,g_id}={0x%x, 0x%x}\\n\\n\", bf->p_aid,\n\t\t\t bf->g_id);\n#endif\n\t}\n\n\tif (tatal_sta_num == 0) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"No Linked STA\\n\");\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nu8 phydm_get_rx_stream_num(void *dm_void, enum rf_type type)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 rx_num = 1;\n\n\tif (type == RF_1T1R)\n\t\trx_num = 1;\n\telse if (type == RF_2T2R || type == RF_1T2R)\n\t\trx_num = 2;\n\telse if (type == RF_3T3R || type == RF_2T3R)\n\t\trx_num = 3;\n\telse if (type == RF_4T4R || type == RF_3T4R || type == RF_2T4R)\n\t\trx_num = 4;\n\telse\n\t\tpr_debug(\"[Warrning] %s\\n\", __func__);\n\n\treturn rx_num;\n}\n\nu8 phydm_get_tx_stream_num(void *dm_void, enum rf_type type)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 tx_num = 1;\n\n\tif (type == RF_1T1R || type == RF_1T2R)\n\t\ttx_num = 1;\n\telse if (type == RF_2T2R || type == RF_2T3R || type == RF_2T4R)\n\t\ttx_num = 2;\n\telse if (type == RF_3T3R || type == RF_3T4R)\n\t\ttx_num = 3;\n\telse if (type == RF_4T4R)\n\t\ttx_num = 4;\n\telse\n\t\tPHYDM_DBG(dm, DBG_RA, \"[Warrning] no mimo_type is found\\n\");\n\n\treturn tx_num;\n}\n\nu64 phydm_get_bb_mod_ra_mask(void *dm_void, u8 sta_idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];\n\tstruct ra_sta_info *ra = NULL;\n\tenum channel_width bw = 0;\n\tenum wireless_set wrls_mode = 0;\n\tu8 tx_stream_num = 1;\n\tu8 rssi_lv = 0;\n\tu64 ra_mask_bitmap = 0;\n\n\tif (is_sta_active(sta)) {\n\t\tra = &sta->ra_info;\n\t\tbw = ra->ra_bw_mode;\n\t\twrls_mode = sta->support_wireless_set;\n\t\ttx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type);\n\t\trssi_lv = ra->rssi_level;\n\t\tra_mask_bitmap = ra->ramask;\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_RA, \"[Warning] %s invalid STA\\n\", __func__);\n\t\treturn 0;\n\t}\n\n\tPHYDM_DBG(dm, DBG_RA, \"macid=%d ori_RA_Mask= 0x%llx\\n\", sta->mac_id,\n\t\t  ra_mask_bitmap);\n\tPHYDM_DBG(dm, DBG_RA,\n\t\t  \"wireless_mode=0x%x, tx_ss=%d, BW=%d, MimoPs=%d, rssi_lv=%d\\n\",\n\t\t  wrls_mode, tx_stream_num, bw, sta->sm_ps, rssi_lv);\n\n\tif (sta->sm_ps == SM_PS_STATIC) /*@mimo_ps_enable*/\n\t\ttx_stream_num = 1;\n\n\t/*@[Modify RA Mask by Wireless Mode]*/\n\n\tif (wrls_mode == WIRELESS_CCK) { /*@B mode*/\n\t\tra_mask_bitmap &= 0x0000000f;\n\t} else if (wrls_mode == WIRELESS_OFDM) { /*@G mode*/\n\t\tra_mask_bitmap &= 0x00000ff0;\n\t} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) { /*@BG mode*/\n\t\tra_mask_bitmap &= 0x00000ff5;\n\t} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) {\n\t\t/*N_2G*/\n\t\tif (tx_stream_num == 1) {\n\t\t\tif (bw == CHANNEL_WIDTH_40)\n\t\t\t\tra_mask_bitmap &= 0x000ff015;\n\t\t\telse\n\t\t\t\tra_mask_bitmap &= 0x000ff005;\n\t\t} else if (tx_stream_num == 2) {\n\t\t\tif (bw == CHANNEL_WIDTH_40)\n\t\t\t\tra_mask_bitmap &= 0x0ffff015;\n\t\t\telse\n\t\t\t\tra_mask_bitmap &= 0x0ffff005;\n\t\t} else if (tx_stream_num == 3) {\n\t\t\tra_mask_bitmap &= 0xffffff015;\n\t\t} else {\n\t\t\tra_mask_bitmap &= 0xffffffff015;\n\t\t}\n\t} else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) { /*N_5G*/\n\n\t\tif (tx_stream_num == 1) {\n\t\t\tif (bw == CHANNEL_WIDTH_40)\n\t\t\t\tra_mask_bitmap &= 0x000ff030;\n\t\t\telse\n\t\t\t\tra_mask_bitmap &= 0x000ff010;\n\t\t} else if (tx_stream_num == 2) {\n\t\t\tif (bw == CHANNEL_WIDTH_40)\n\t\t\t\tra_mask_bitmap &= 0x0ffff030;\n\t\t\telse\n\t\t\t\tra_mask_bitmap &= 0x0ffff010;\n\t\t} else if (tx_stream_num == 3) {\n\t\t\tra_mask_bitmap &= 0xffffff010;\n\t\t} else {\n\t\t\tra_mask_bitmap &= 0xffffffff010;\n\t\t}\n\t} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) {\n\t\t/*@AC_2G*/\n\t\tif (tx_stream_num == 1)\n\t\t\tra_mask_bitmap &= 0x003ff015;\n\t\telse if (tx_stream_num == 2)\n\t\t\tra_mask_bitmap &= 0xfffff015;\n\t\telse if (tx_stream_num == 3)\n\t\t\tra_mask_bitmap &= 0x3fffffff015;\n\t\telse /*@AC_4SS 2G*/\n\t\t\tra_mask_bitmap &= 0x000ffffffffff015;\n\t\tif (bw == CHANNEL_WIDTH_20) {\n\t\t/* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/\n\t\t\tra_mask_bitmap &= 0x0007ffff7fdff015;\n\t\t} else if (bw == CHANNEL_WIDTH_80) {\n\t\t/* @AC 80MHz doesn't support 3SS MCS6*/\n\t\t\tra_mask_bitmap &= 0x000fffbffffff015;\n\t\t}\n\t} else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) { /*@AC_5G*/\n\n\t\tif (tx_stream_num == 1)\n\t\t\tra_mask_bitmap &= 0x003ff010;\n\t\telse if (tx_stream_num == 2)\n\t\t\tra_mask_bitmap &= 0xfffff010;\n\t\telse if (tx_stream_num == 3)\n\t\t\tra_mask_bitmap &= 0x3fffffff010;\n\t\telse /*@AC_4SS 5G*/\n\t\t\tra_mask_bitmap &= 0x000ffffffffff010;\n\n\t\tif (bw == CHANNEL_WIDTH_20) {\n\t\t/* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/\n\t\t\tra_mask_bitmap &= 0x0007ffff7fdff010;\n\t\t} else if (bw == CHANNEL_WIDTH_80) {\n\t\t/* @AC 80MHz doesn't support 3SS MCS6*/\n\t\t\tra_mask_bitmap &= 0x000fffbffffff010;\n\t\t}\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_RA, \"[Warrning] RA mask is Not found\\n\");\n\t}\n\n\tPHYDM_DBG(dm, DBG_RA, \"Mod by mode=0x%llx\\n\", ra_mask_bitmap);\n\n\t/*@[Modify RA Mask by RSSI level]*/\n\tif (wrls_mode != WIRELESS_CCK) {\n\t\tif (rssi_lv == 0)\n\t\t\tra_mask_bitmap &= 0xffffffffffffffff;\n\t\telse if (rssi_lv == 1)\n\t\t\tra_mask_bitmap &= 0xfffffffffffffff0;\n\t\telse if (rssi_lv == 2)\n\t\t\tra_mask_bitmap &= 0xffffffffffffefe0;\n\t\telse if (rssi_lv == 3)\n\t\t\tra_mask_bitmap &= 0xffffffffffffcfc0;\n\t\telse if (rssi_lv == 4)\n\t\t\tra_mask_bitmap &= 0xffffffffffff8f80;\n\t\telse if (rssi_lv >= 5)\n\t\t\tra_mask_bitmap &= 0xffffffffffff0f00;\n\t}\n\tPHYDM_DBG(dm, DBG_RA, \"Mod by RSSI=0x%llx\\n\", ra_mask_bitmap);\n\n\treturn ra_mask_bitmap;\n}\n\nu8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];\n\tstruct ra_sta_info *ra = NULL;\n\tenum wireless_set wrls_set = 0;\n\tu8 rssi_lv = 0;\n\tu8 rate_idx = 0;\n\tu8 rate_ofst = 0;\n\n\tif (is_sta_active(sta)) {\n\t\tra = &sta->ra_info;\n\t\twrls_set = sta->support_wireless_set;\n\t\trssi_lv = ra->rssi_level;\n\t} else {\n\t\tpr_debug(\"[Warning] %s: invalid STA\\n\", __func__);\n\t\treturn 0;\n\t}\n\n\tPHYDM_DBG(dm, DBG_RA, \"[%s]macid=%d, wireless_set=0x%x, rssi_lv=%d\\n\",\n\t\t  __func__, sta->mac_id, wrls_set, rssi_lv);\n\n\trate_ofst = (rssi_lv <= 1) ? 0 : (rssi_lv - 1);\n\n\tif (wrls_set & WIRELESS_VHT) {\n\t\trate_idx = ODM_RATEVHTSS1MCS0 + rate_ofst;\n\t} else if (wrls_set & WIRELESS_HT) {\n\t\trate_idx = ODM_RATEMCS0 + rate_ofst;\n\t} else if (wrls_set & WIRELESS_OFDM) {\n\t\trate_idx = ODM_RATE6M + rate_ofst;\n\t} else {\n\t\trate_idx = ODM_RATE1M + rate_ofst;\n\n\t\tif (rate_idx > ODM_RATE11M)\n\t\t\trate_idx = ODM_RATE11M;\n\t}\n\treturn rate_idx;\n}\n\nu8 phydm_get_rate_id(void *dm_void, u8 sta_idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];\n\tstruct ra_sta_info *ra = NULL;\n\tenum channel_width bw = 0;\n\tenum wireless_set wrls_mode = 0;\n\tu8 tx_stream_num = 1;\n\tu8 rate_id_idx = PHYDM_BGN_20M_1SS;\n\n\tif (is_sta_active(sta)) {\n\t\tra = &sta->ra_info;\n\t\tbw = ra->ra_bw_mode;\n\t\twrls_mode = sta->support_wireless_set;\n\t\ttx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type);\n\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_RA, \"[Warning] %s: invalid STA\\n\", __func__);\n\t\treturn 0;\n\t}\n\n\tPHYDM_DBG(dm, DBG_RA, \"macid=%d,wireless_set=0x%x,tx_SS_num=%d,BW=%d\\n\",\n\t\t  sta->mac_id, wrls_mode, tx_stream_num, bw);\n\n\tif (wrls_mode == WIRELESS_CCK) {\n\t/*@B mode*/\n\t\trate_id_idx = PHYDM_B_20M;\n\t} else if (wrls_mode == WIRELESS_OFDM) {\n\t/*@G mode*/\n\t\trate_id_idx = PHYDM_G;\n\t} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) {\n\t/*@BG mode*/\n\t\trate_id_idx = PHYDM_BG;\n\t} else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) {\n\t/*@GN mode*/\n\t\tif (tx_stream_num == 1)\n\t\t\trate_id_idx = PHYDM_GN_N1SS;\n\t\telse if (tx_stream_num == 2)\n\t\t\trate_id_idx = PHYDM_GN_N2SS;\n\t\telse if (tx_stream_num == 3)\n\t\t\trate_id_idx = PHYDM_ARFR5_N_3SS;\n\t} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) {\n\t /*@BGN mode*/\n\t\tif (bw == CHANNEL_WIDTH_40) {\n\t\t\tif (tx_stream_num == 1)\n\t\t\t\trate_id_idx = PHYDM_BGN_40M_1SS;\n\t\t\telse if (tx_stream_num == 2)\n\t\t\t\trate_id_idx = PHYDM_BGN_40M_2SS;\n\t\t\telse if (tx_stream_num == 3)\n\t\t\t\trate_id_idx = PHYDM_ARFR5_N_3SS;\n\t\t\telse if (tx_stream_num == 4)\n\t\t\t\trate_id_idx = PHYDM_ARFR7_N_4SS;\n\n\t\t} else {\n\t\t\tif (tx_stream_num == 1)\n\t\t\t\trate_id_idx = PHYDM_BGN_20M_1SS;\n\t\t\telse if (tx_stream_num == 2)\n\t\t\t\trate_id_idx = PHYDM_BGN_20M_2SS;\n\t\t\telse if (tx_stream_num == 3)\n\t\t\t\trate_id_idx = PHYDM_ARFR5_N_3SS;\n\t\t\telse if (tx_stream_num == 4)\n\t\t\t\trate_id_idx = PHYDM_ARFR7_N_4SS;\n\t\t}\n\t} else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) {\n\t/*@AC mode*/\n\t\tif (tx_stream_num == 1)\n\t\t\trate_id_idx = PHYDM_ARFR1_AC_1SS;\n\t\telse if (tx_stream_num == 2)\n\t\t\trate_id_idx = PHYDM_ARFR0_AC_2SS;\n\t\telse if (tx_stream_num == 3)\n\t\t\trate_id_idx = PHYDM_ARFR4_AC_3SS;\n\t\telse if (tx_stream_num == 4)\n\t\t\trate_id_idx = PHYDM_ARFR6_AC_4SS;\n\t} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) {\n\t/*@AC 2.4G mode*/\n\t\tif (bw >= CHANNEL_WIDTH_80) {\n\t\t\tif (tx_stream_num == 1)\n\t\t\t\trate_id_idx = PHYDM_ARFR1_AC_1SS;\n\t\t\telse if (tx_stream_num == 2)\n\t\t\t\trate_id_idx = PHYDM_ARFR0_AC_2SS;\n\t\t\telse if (tx_stream_num == 3)\n\t\t\t\trate_id_idx = PHYDM_ARFR4_AC_3SS;\n\t\t\telse if (tx_stream_num == 4)\n\t\t\t\trate_id_idx = PHYDM_ARFR6_AC_4SS;\n\t\t} else {\n\t\t\tif (tx_stream_num == 1)\n\t\t\t\trate_id_idx = PHYDM_ARFR2_AC_2G_1SS;\n\t\t\telse if (tx_stream_num == 2)\n\t\t\t\trate_id_idx = PHYDM_ARFR3_AC_2G_2SS;\n\t\t\telse if (tx_stream_num == 3)\n\t\t\t\trate_id_idx = PHYDM_ARFR4_AC_3SS;\n\t\t\telse if (tx_stream_num == 4)\n\t\t\t\trate_id_idx = PHYDM_ARFR6_AC_4SS;\n\t\t}\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_RA, \"[Warrning] No rate_id is found\\n\");\n\t\trate_id_idx = 0;\n\t}\n\n\tPHYDM_DBG(dm, DBG_RA, \"Rate_ID=((0x%x))\\n\", rate_id_idx);\n\n\treturn rate_id_idx;\n}\n\nvoid phydm_ra_h2c(void *dm_void, u8 sta_idx, u8 dis_ra, u8 dis_pt,\n\t\t  u8 no_update_bw, u8 init_ra_lv, u64 ra_mask)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];\n\tstruct ra_sta_info *ra = NULL;\n\tu8 h2c_val[H2C_MAX_LENGTH] = {0};\n\n\tif (is_sta_active(sta)) {\n\t\tra = &sta->ra_info;\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_RA, \"[Warning] %s invalid sta_info\\n\",\n\t\t\t  __func__);\n\t\treturn;\n\t}\n\n\tPHYDM_DBG(dm, DBG_RA, \"%s ======>\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_RA, \"MACID=%d\\n\", sta->mac_id);\n\n\tif (dm->is_disable_power_training)\n\t\tdis_pt = true;\n\telse if (!dm->is_disable_power_training)\n\t\tdis_pt = false;\n\n\th2c_val[0] = sta->mac_id;\n\th2c_val[1] = (ra->rate_id & 0x1f) | ((init_ra_lv & 0x3) << 5) |\n\t\t     (ra->is_support_sgi << 7);\n\th2c_val[2] = (u8)((ra->ra_bw_mode) | (((sta->ldpc_en) ? 1 : 0) << 2) |\n\t\t\t  ((no_update_bw & 0x1) << 3) |\n\t\t\t  (ra->is_vht_enable << 4) |\n\t\t\t  ((dis_pt & 0x1) << 6) | ((dis_ra & 0x1) << 7));\n\n\th2c_val[3] = (u8)(ra_mask & 0xff);\n\th2c_val[4] = (u8)((ra_mask & 0xff00) >> 8);\n\th2c_val[5] = (u8)((ra_mask & 0xff0000) >> 16);\n\th2c_val[6] = (u8)((ra_mask & 0xff000000) >> 24);\n\n\tPHYDM_DBG(dm, DBG_RA, \"PHYDM h2c[0x40]=0x%x %x %x %x %x %x %x\\n\",\n\t\t  h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2],\n\t\t  h2c_val[1], h2c_val[0]);\n\n\todm_fill_h2c_cmd(dm, PHYDM_H2C_RA_MASK, H2C_MAX_LENGTH, h2c_val);\n\n\t#if (defined(PHYDM_COMPILE_ABOVE_3SS))\n\tif (dm->support_ic_type & (PHYDM_IC_ABOVE_3SS)) {\n\t\th2c_val[3] = (u8)((ra_mask >> 32) & 0x000000ff);\n\t\th2c_val[4] = (u8)(((ra_mask >> 32) & 0x0000ff00) >> 8);\n\t\th2c_val[5] = (u8)(((ra_mask >> 32) & 0x00ff0000) >> 16);\n\t\th2c_val[6] = (u8)(((ra_mask >> 32) & 0xff000000) >> 24);\n\n\t\tPHYDM_DBG(dm, DBG_RA, \"h2c[0x46]=0x%x %x %x %x %x %x %x\\n\",\n\t\t\t  h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3],\n\t\t\t  h2c_val[2], h2c_val[1], h2c_val[0]);\n\n\t\todm_fill_h2c_cmd(dm, PHYDM_RA_MASK_ABOVE_3SS,\n\t\t\t\t H2C_MAX_LENGTH, h2c_val);\n\t}\n\t#endif\n}\n\nvoid phydm_ra_registed(void *dm_void, u8 sta_idx,\n\t\t       /*@index of sta_info array, not MACID*/\n\t\t       u8 rssi_from_assoc)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra_t = &dm->dm_ra_table;\n\tstruct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];\n\tstruct ra_sta_info *ra = NULL;\n\tu8 init_ra_lv = 0;\n\tu64 ra_mask = 0;\n\t/*@SD7 STA_idx != macid*/\n\t/*@SD4,8 STA_idx == macid, */\n\n\tPHYDM_DBG(dm, DBG_RA_MASK, \"%s ======>\\n\", __func__);\n\n\tif (is_sta_active(sta)) {\n\t\tra = &sta->ra_info;\n\t\tPHYDM_DBG(dm, DBG_RA_MASK, \"sta_idx=%d, macid=%d\\n\", sta_idx,\n\t\t\t  sta->mac_id);\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_RA_MASK, \"[Warning] %s invalid STA\\n\",\n\t\t\t  __func__);\n\t\tPHYDM_DBG(dm, DBG_RA_MASK, \"sta_idx=%d\\n\", sta_idx);\n\t\treturn;\n\t}\n\n\t#if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8188E)\n\t\tra->rate_id = phydm_get_rate_id_88e(dm, sta_idx);\n\telse\n\t#endif\n\t{\n\t\tra->rate_id = phydm_get_rate_id(dm, sta_idx);\n\t}\n\n\tra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx);\n\n\tPHYDM_DBG(dm, DBG_RA_MASK, \"rssi_assoc=%d\\n\", rssi_from_assoc);\n\n\tif (rssi_from_assoc > 40)\n\t\tinit_ra_lv = 1;\n\telse if (rssi_from_assoc > 20)\n\t\tinit_ra_lv = 2;\n\telse if (rssi_from_assoc > 1)\n\t\tinit_ra_lv = 3;\n\telse\n\t\tinit_ra_lv = 0;\n\n\tif (ra_t->record_ra_info)\n\t\tra_t->record_ra_info(dm, sta_idx, sta, ra_mask);\n\n\t#if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8188E)\n\t\t/*@Driver RA*/\n\t\tphydm_ra_update_8188e(dm, sta_idx, ra->rate_id,\n\t\t\t\t      (u32)ra_mask, ra->is_support_sgi);\n\telse\n\t#endif\n\t{\n\t\t/*@FW RA*/\n\t\tphydm_ra_h2c(dm, sta_idx, ra->disable_ra, ra->disable_pt, 0,\n\t\t\t     init_ra_lv, ra_mask);\n\t}\n}\n\nvoid phydm_ra_offline(void *dm_void, u8 sta_idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra_t = &dm->dm_ra_table;\n\tstruct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];\n\tstruct ra_sta_info *ra = NULL;\n\n\tif (is_sta_active(sta)) {\n\t\tra = &sta->ra_info;\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_RA, \"[Warning] %s invalid STA\\n\", __func__);\n\t\treturn;\n\t}\n\n\tPHYDM_DBG(dm, DBG_RA, \"%s ======>\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_RA, \"MACID=%d\\n\", sta->mac_id);\n\n\todm_memory_set(dm, &ra->rate_id, 0, sizeof(struct ra_sta_info));\n\tra->disable_ra = 1;\n\tra->disable_pt = 1;\n\n\tif (ra_t->record_ra_info)\n\t\tra_t->record_ra_info(dm, sta->mac_id, sta, 0);\n\n\tif (dm->support_ic_type != ODM_RTL8188E)\n\t\tphydm_ra_h2c(dm, sta->mac_id, 1, 1, 0, 0, 0);\n}\n\nvoid phydm_ra_mask_watchdog(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra_t = &dm->dm_ra_table;\n\tstruct cmn_sta_info *sta = NULL;\n\tstruct ra_sta_info *ra = NULL;\n\tboolean force_ra_mask_en = false;\n\tu8 sta_idx;\n\tu64 ra_mask;\n\tu8 rssi_lv_new;\n\tu8 rssi = 0;\n\n\tif (!(dm->support_ability & ODM_BB_RA_MASK))\n\t\treturn;\n\n\tif (!dm->is_linked || (dm->phydm_sys_up_time % 2) == 1)\n\t\treturn;\n\n\tPHYDM_DBG(dm, DBG_RA_MASK, \"%s ======>\\n\", __func__);\n\n\tra_t->up_ramask_cnt++;\n\n\tif (ra_t->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD) {\n\t\tra_t->up_ramask_cnt = 0;\n\t\tforce_ra_mask_en = true;\n\t}\n\n\tfor (sta_idx = 0; sta_idx < ODM_ASSOCIATE_ENTRY_NUM; sta_idx++) {\n\t\tsta = dm->phydm_sta_info[sta_idx];\n\n\t\tif (!is_sta_active(sta))\n\t\t\tcontinue;\n\n\t\tra = &sta->ra_info;\n\n\t\tif (ra->disable_ra)\n\t\t\tcontinue;\n\n\t\tPHYDM_DBG(dm, DBG_RA_MASK, \"sta_idx=%d, macid=%d\\n\", sta_idx,\n\t\t\t  sta->mac_id);\n\n\t\trssi = (u8)(sta->rssi_stat.rssi);\n\n\t\t/*@to be modified*/\n\t\t#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))\n\t\tif (dm->support_ic_type == ODM_RTL8812 ||\n\t\t\t(dm->support_ic_type == ODM_RTL8821 &&\n\t\t\t dm->cut_version == ODM_CUT_A)\n\t\t\t) {\n\t\t\tif (rssi < ra_t->ldpc_thres) {\n\t\t\t\t/*@LDPC TX enable*/\n\t\t\t\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t\t\tset_ra_ldpc_8812(sta, true);\n\t\t\t\t#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t\t\t\tMgntSet_TX_LDPC(dm->adapter, sta->mac_id, true);\n\t\t\t\t#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t\t\t\t/*to be added*/\n\t\t\t\t#endif\n\t\t\t\tPHYDM_DBG(dm, DBG_RA_MASK,\n\t\t\t\t\t  \"RSSI=%d, ldpc_en =TRUE\\n\", rssi);\n\n\t\t\t} else if (rssi > (ra_t->ldpc_thres + 3)) {\n\t\t\t\t/*@LDPC TX disable*/\n\t\t\t\t#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t\t\t\tset_ra_ldpc_8812(sta, false);\n\t\t\t\t#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t\t\t\tMgntSet_TX_LDPC(dm->adapter, sta->mac_id, false);\n\t\t\t\t#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t\t\t\t/*to be added*/\n\t\t\t\t#endif\n\t\t\t\tPHYDM_DBG(dm, DBG_RA_MASK,\n\t\t\t\t\t  \"RSSI=%d, ldpc_en =FALSE\\n\", rssi);\n\t\t\t}\n\t\t}\n\t\t#endif\n\n\t\trssi_lv_new = phydm_rssi_lv_dec(dm, (u32)rssi, ra->rssi_level);\n\n\t\tif (ra->rssi_level != rssi_lv_new || force_ra_mask_en) {\n\t\t\tPHYDM_DBG(dm, DBG_RA_MASK, \"RSSI LV:((%d))->((%d))\\n\",\n\t\t\t\t  ra->rssi_level, rssi_lv_new);\n\n\t\t\tra->rssi_level = rssi_lv_new;\n\n\t\t\tra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx);\n\n\t\t\tif (ra_t->record_ra_info)\n\t\t\t\tra_t->record_ra_info(dm, sta_idx, sta, ra_mask);\n\n\t\t\t#if (RTL8188E_SUPPORT) && (RATE_ADAPTIVE_SUPPORT)\n\t\t\tif (dm->support_ic_type == ODM_RTL8188E)\n\t\t\t\t/*@Driver RA*/\n\t\t\t\tphydm_ra_update_8188e(dm, sta_idx, ra->rate_id,\n\t\t\t\t\t\t      (u32)ra_mask,\n\t\t\t\t\t\t      ra->is_support_sgi);\n\t\t\telse\n\t\t\t#endif\n\t\t\t{\n\t\t\t\t/*@FW RA*/\n\t\t\t\tphydm_ra_h2c(dm, sta_idx, ra->disable_ra,\n\t\t\t\t\t     ra->disable_pt, 1, 0, ra_mask);\n\t\t\t}\n\t\t}\n\t}\n}\n\nu8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 vht_en_out = 0;\n\n\tif (wireless_mode == PHYDM_WIRELESS_MODE_AC_5G ||\n\t    wireless_mode == PHYDM_WIRELESS_MODE_AC_24G ||\n\t    wireless_mode == PHYDM_WIRELESS_MODE_AC_ONLY)\n\t\tvht_en_out = 1;\n\n\tPHYDM_DBG(dm, DBG_RA, \"wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\\n\",\n\t\t  wireless_mode, vht_en_out);\n\treturn vht_en_out;\n}\n\nu8 phydm_rftype2rateid_2g_n20(void *dm_void, u8 rf_type)\n{\n\tu8 rate_id_idx = 0;\n\n\tif (rf_type == RF_1T1R)\n\t\trate_id_idx = PHYDM_BGN_20M_1SS;\n\telse if (rf_type == RF_2T2R)\n\t\trate_id_idx = PHYDM_BGN_20M_2SS;\n\telse if (rf_type == RF_3T3R)\n\t\trate_id_idx = PHYDM_ARFR5_N_3SS;\n\telse\n\t\trate_id_idx = PHYDM_ARFR7_N_4SS;\n\treturn rate_id_idx;\n}\n\nu8 phydm_rftype2rateid_2g_n40(void *dm_void, u8 rf_type)\n{\n\tu8 rate_id_idx = 0;\n\n\tif (rf_type == RF_1T1R)\n\t\trate_id_idx = PHYDM_BGN_40M_1SS;\n\telse if (rf_type == RF_2T2R)\n\t\trate_id_idx = PHYDM_BGN_40M_2SS;\n\telse if (rf_type == RF_3T3R)\n\t\trate_id_idx = PHYDM_ARFR5_N_3SS;\n\telse\n\t\trate_id_idx = PHYDM_ARFR7_N_4SS;\n\treturn rate_id_idx;\n}\n\nu8 phydm_rftype2rateid_5g_n(void *dm_void, u8 rf_type)\n{\n\tu8 rate_id_idx = 0;\n\n\tif (rf_type == RF_1T1R)\n\t\trate_id_idx = PHYDM_GN_N1SS;\n\telse if (rf_type == RF_2T2R)\n\t\trate_id_idx = PHYDM_GN_N2SS;\n\telse if (rf_type == RF_3T3R)\n\t\trate_id_idx = PHYDM_ARFR5_N_3SS;\n\telse\n\t\trate_id_idx = PHYDM_ARFR7_N_4SS;\n\treturn rate_id_idx;\n}\n\nu8 phydm_rftype2rateid_ac80(void *dm_void, u8 rf_type)\n{\n\tu8 rate_id_idx = 0;\n\n\tif (rf_type == RF_1T1R)\n\t\trate_id_idx = PHYDM_ARFR1_AC_1SS;\n\telse if (rf_type == RF_2T2R)\n\t\trate_id_idx = PHYDM_ARFR0_AC_2SS;\n\telse if (rf_type == RF_3T3R)\n\t\trate_id_idx = PHYDM_ARFR4_AC_3SS;\n\telse\n\t\trate_id_idx = PHYDM_ARFR6_AC_4SS;\n\treturn rate_id_idx;\n}\n\nu8 phydm_rftype2rateid_ac40(void *dm_void, u8 rf_type)\n{\n\tu8 rate_id_idx = 0;\n\n\tif (rf_type == RF_1T1R)\n\t\trate_id_idx = PHYDM_ARFR2_AC_2G_1SS;\n\telse if (rf_type == RF_2T2R)\n\t\trate_id_idx = PHYDM_ARFR3_AC_2G_2SS;\n\telse if (rf_type == RF_3T3R)\n\t\trate_id_idx = PHYDM_ARFR4_AC_3SS;\n\telse\n\t\trate_id_idx = PHYDM_ARFR6_AC_4SS;\n\treturn rate_id_idx;\n}\n\nu8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 rate_id_idx = 0;\n\n\tPHYDM_DBG(dm, DBG_RA,\n\t\t  \"wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\\n\",\n\t\t  wireless_mode, rf_type, bw);\n\n\tswitch (wireless_mode) {\n\tcase PHYDM_WIRELESS_MODE_N_24G:\n\t\tif (bw == CHANNEL_WIDTH_40)\n\t\t\trate_id_idx = phydm_rftype2rateid_2g_n40(dm, rf_type);\n\t\telse\n\t\t\trate_id_idx = phydm_rftype2rateid_2g_n20(dm, rf_type);\n\t\tbreak;\n\n\tcase PHYDM_WIRELESS_MODE_N_5G:\n\t\trate_id_idx = phydm_rftype2rateid_5g_n(dm, rf_type);\n\t\tbreak;\n\n\tcase PHYDM_WIRELESS_MODE_G:\n\t\trate_id_idx = PHYDM_BG;\n\t\tbreak;\n\n\tcase PHYDM_WIRELESS_MODE_A:\n\t\trate_id_idx = PHYDM_G;\n\t\tbreak;\n\n\tcase PHYDM_WIRELESS_MODE_B:\n\t\trate_id_idx = PHYDM_B_20M;\n\t\tbreak;\n\n\tcase PHYDM_WIRELESS_MODE_AC_5G:\n\tcase PHYDM_WIRELESS_MODE_AC_ONLY:\n\t\trate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type);\n\t\tbreak;\n\n\tcase PHYDM_WIRELESS_MODE_AC_24G:\n/*@Becareful to set \"Lowest rate\" while using PHYDM_ARFR4_AC_3SS in 2.4G/5G*/\n\t\tif (bw >= CHANNEL_WIDTH_80)\n\t\t\trate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type);\n\t\telse\n\t\t\trate_id_idx = phydm_rftype2rateid_ac40(dm, rf_type);\n\t\tbreak;\n\n\tdefault:\n\t\trate_id_idx = 0;\n\t\tbreak;\n\t}\n\n\tPHYDM_DBG(dm, DBG_RA, \"RA rate ID = (( 0x%x ))\\n\", rate_id_idx);\n\n\treturn rate_id_idx;\n}\n\nu8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\t/*@MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/\n\tu8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100};\n\tu8 new_rssi_lv = 0;\n\tu8 i;\n\n\tPHYDM_DBG(dm, DBG_RA_MASK,\n\t\t  \"curr RA level=(%d), Table_ori=[%d, %d, %d, %d, %d, %d]\\n\",\n\t\t  ratr_state, rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2],\n\t\t  rssi_lv_t[3], rssi_lv_t[4], rssi_lv_t[5]);\n\n\tfor (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {\n\t\tif (i >= (ratr_state))\n\t\t\trssi_lv_t[i] += RA_FLOOR_UP_GAP;\n\t}\n\n\tPHYDM_DBG(dm, DBG_RA_MASK,\n\t\t  \"RSSI=(%d), Table_mod=[%d, %d, %d, %d, %d, %d]\\n\", rssi,\n\t\t  rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2], rssi_lv_t[3],\n\t\t  rssi_lv_t[4], rssi_lv_t[5]);\n\n\tfor (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {\n\t\tif (rssi < rssi_lv_t[i]) {\n\t\t\tnew_rssi_lv = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn new_rssi_lv;\n}\n\nenum phydm_qam_order phydm_get_ofdm_qam_order(void *dm_void, u8 rate_idx)\n{\n\tu8 tmp_idx = 0;\n\tenum phydm_qam_order qam_order = PHYDM_QAM_BPSK;\n\tenum phydm_qam_order qam[10] = {PHYDM_QAM_BPSK, PHYDM_QAM_QPSK,\n\t\t\t\t\tPHYDM_QAM_QPSK, PHYDM_QAM_16QAM,\n\t\t\t\t\tPHYDM_QAM_16QAM, PHYDM_QAM_64QAM,\n\t\t\t\t\tPHYDM_QAM_64QAM, PHYDM_QAM_64QAM,\n\t\t\t\t\tPHYDM_QAM_256QAM, PHYDM_QAM_256QAM};\n\n\tif (rate_idx <= ODM_RATE11M)\n\t\treturn PHYDM_QAM_CCK;\n\n\tif (rate_idx >= ODM_RATEVHTSS1MCS0) {\n\t\tif (rate_idx >= ODM_RATEVHTSS4MCS0)\n\t\t\ttmp_idx -= ODM_RATEVHTSS4MCS0;\n\t\telse if (rate_idx >= ODM_RATEVHTSS3MCS0)\n\t\t\ttmp_idx -= ODM_RATEVHTSS3MCS0;\n\t\telse if (rate_idx >= ODM_RATEVHTSS2MCS0)\n\t\t\ttmp_idx -= ODM_RATEVHTSS2MCS0;\n\t\telse\n\t\t\ttmp_idx -= ODM_RATEVHTSS1MCS0;\n\n\t\tqam_order = qam[tmp_idx];\n\t} else if (rate_idx >= ODM_RATEMCS0) {\n\t\tif (rate_idx >= ODM_RATEMCS24)\n\t\t\ttmp_idx -= ODM_RATEMCS24;\n\t\telse if (rate_idx >= ODM_RATEMCS16)\n\t\t\ttmp_idx -= ODM_RATEMCS16;\n\t\telse if (rate_idx >= ODM_RATEMCS8)\n\t\t\ttmp_idx -= ODM_RATEMCS8;\n\t\telse\n\t\t\ttmp_idx -= ODM_RATEMCS0;\n\n\t\tqam_order = qam[tmp_idx];\n\t} else {\n\t\tif (rate_idx > ODM_RATE6M) {\n\t\t\ttmp_idx -= ODM_RATE6M;\n\t\t\tqam_order = qam[tmp_idx - 1];\n\t\t} else {\n\t\t\tqam_order = PHYDM_QAM_BPSK;\n\t\t}\n\t}\n\n\treturn qam_order;\n}\n\nu8 phydm_rate_order_compute(void *dm_void, u8 rate_idx)\n{\n\tu8 rate_order = rate_idx & 0x7f;\n\n\trate_idx &= 0x7f;\n\n\tif (rate_idx >= ODM_RATEVHTSS4MCS0)\n\t\trate_order -= ODM_RATEVHTSS4MCS0;\n\telse if (rate_idx >= ODM_RATEVHTSS3MCS0)\n\t\trate_order -= ODM_RATEVHTSS3MCS0;\n\telse if (rate_idx >= ODM_RATEVHTSS2MCS0)\n\t\trate_order -= ODM_RATEVHTSS2MCS0;\n\telse if (rate_idx >= ODM_RATEVHTSS1MCS0)\n\t\trate_order -= ODM_RATEVHTSS1MCS0;\n\telse if (rate_idx >= ODM_RATEMCS24)\n\t\trate_order -= ODM_RATEMCS24;\n\telse if (rate_idx >= ODM_RATEMCS16)\n\t\trate_order -= ODM_RATEMCS16;\n\telse if (rate_idx >= ODM_RATEMCS8)\n\t\trate_order -= ODM_RATEMCS8;\n\telse if (rate_idx >= ODM_RATEMCS0)\n\t\trate_order -= ODM_RATEMCS0;\n\telse if (rate_idx >= ODM_RATE6M)\n\t\trate_order -= ODM_RATE6M;\n\telse\n\t\trate_order -= ODM_RATE1M;\n\n\tif (rate_idx >= ODM_RATEMCS0)\n\t\trate_order++;\n\n\treturn rate_order;\n}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\nu8 phydm_rate2ss(void *dm_void, u8 rate_idx)\n{\n\tu8 ret = 0xff;\n\tu8 i, j;\n\tu8 search_idx;\n\tu32 ss_mapping_tab[4][3] = {{0x00000000, 0x003ff000, 0x000ff000},\n\t\t\t\t    {0x00000000, 0xffc00000, 0x0ff00000},\n\t\t\t\t    {0x000003ff, 0x0000000f, 0xf0000000},\n\t\t\t\t    {0x000ffc00, 0x00000ff0, 0x00000000} };\n\tif (rate_idx < 32) {\n\t\tsearch_idx = rate_idx;\n\t\tj = 0;\n\t} else if (rate_idx < 64) {\n\t\tsearch_idx = rate_idx - 32;\n\t\tj = 1;\n\t} else {\n\t\tsearch_idx = rate_idx - 64;\n\t\tj = 2;\n\t}\n\tfor (i = 0; i < 4; i++)\n\t\tif (ss_mapping_tab[i][j] & BIT(search_idx))\n\t\t\tret = i;\n\treturn ret;\n}\n\nu8 phydm_rate2plcp(void *dm_void, u8 rate_idx)\n{\n\tu8 rate2ss = 0;\n\tu8 ltftime = 0;\n\tu8 plcptime = 0xff;\n\n\tif (rate_idx < ODM_RATE6M) {\n\t\tplcptime = 192;\n\t\t/* @CCK PLCP = 192us (long preamble) */\n\t} else if (rate_idx < ODM_RATEMCS0) {\n\t\tplcptime = 20;\n\t\t/* @LegOFDM PLCP = 20us */\n\t} else {\n\t\tif (rate_idx < ODM_RATEVHTSS1MCS0)\n\t\t\tplcptime = 32;\n\t\t/* @HT mode PLCP = 20us + 12us + 4us x Nss */\n\t\telse\n\t\t\tplcptime = 36;\n\t\t/* VHT mode PLCP = 20us + 16us + 4us x Nss */\n\t\trate2ss = phydm_rate2ss(dm_void, rate_idx);\n\t\tif (rate2ss != 0xff)\n\t\t\tltftime = (rate2ss + 1) * 4;\n\t\telse\n\t\t\treturn 0xff;\n\n\t\tplcptime += ltftime;\n\t}\n\treturn plcptime;\n}\n\nu8 phydm_get_plcp(void *dm_void, u16 macid)\n{\n\tu8 plcp_time = 0;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct cmn_sta_info *sta = NULL;\n\tstruct ra_sta_info *ra = NULL;\n\n\tsta = dm->phydm_sta_info[macid];\n\tra = &sta->ra_info;\n\tplcp_time = phydm_rate2plcp(dm, ra->curr_tx_rate);\n\treturn plcp_time;\n}\n#endif\n\nvoid phydm_ra_common_info_update(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra_tab = &dm->dm_ra_table;\n\tstruct cmn_sta_info *sta = NULL;\n\tu16 macid;\n\tu8 rate_order_tmp;\n\tu8 rate_idx = 0;\n\tu8 cnt = 0;\n\n\tra_tab->highest_client_tx_order = 0;\n\tra_tab->power_tracking_flag = 1;\n\n\tif (!dm->number_linked_client)\n\t\treturn;\n\n\tfor (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {\n\t\tsta = dm->phydm_sta_info[macid];\n\n\t\tif (!is_sta_active(sta))\n\t\t\tcontinue;\n\n\t\trate_idx = sta->ra_info.curr_tx_rate & 0x7f;\n\t\trate_order_tmp = phydm_rate_order_compute(dm, rate_idx);\n\n\t\tif (rate_order_tmp >= ra_tab->highest_client_tx_order) {\n\t\t\tra_tab->highest_client_tx_order = rate_order_tmp;\n\t\t\tra_tab->highest_client_tx_rate_order = macid;\n\t\t}\n\n\t\tcnt++;\n\n\t\tif (cnt == dm->number_linked_client)\n\t\t\tbreak;\n\t}\n\tPHYDM_DBG(dm, DBG_RA,\n\t\t  \"MACID[%d], Highest Tx order Update for power traking: %d\\n\",\n\t\t  ra_tab->highest_client_tx_rate_order,\n\t\t  ra_tab->highest_client_tx_order);\n}\n\nvoid phydm_rrsr_set_register(void *dm_void, u32 rrsr_val)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\todm_set_mac_reg(dm, R_0x440, 0xfffff, rrsr_val);\n}\n\nvoid phydm_masked_rrsr_set_register(void *dm_void, u32 rrsr_val)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra_tab = &dm->dm_ra_table;\n\n\tif (ra_tab->rrsr_val_curr == rrsr_val)\n\t\treturn;\n\n\tra_tab->rrsr_val_curr = rrsr_val;\n\todm_set_mac_reg(dm, R_0x440, 0xfffff, rrsr_val);\n}\n\nvoid phydm_rrsr_mask(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra = &dm->dm_ra_table;\n\tstruct cmn_sta_info *sta = NULL;\n\tu8 rate_order = 0;\n\tu8 rate_order_min = 0xff;\n\tu32 rrsr_mask = 0, rrsr_mask_ofdm = 0;\n\tu8 tx_rate_idx = 0;\n\tu8 i = 0, sta_cnt = 0;\n\n\tif (!ra->dynamic_rrsr_en)\n\t\treturn;\n\n\tif (!dm->is_linked) {\n\t\tphydm_masked_rrsr_set_register(dm, ra->rrsr_val_init);\n\t\treturn;\n\t}\n\n#if 1\n\tfor (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {\n\t\tsta = dm->phydm_sta_info[i];\n\t\tif (!is_sta_active(sta))\n\t\t\tcontinue;\n\n\t\tsta_cnt++;\n\t\ttx_rate_idx = sta->ra_info.curr_tx_rate & 0x7f;\n\t\trate_order = phydm_rate_order_compute(dm, tx_rate_idx);\n\t\tif (rate_order < rate_order_min)\n\t\t\trate_order_min = rate_order;\n\n\t\tif (sta_cnt == dm->number_linked_client)\n\t\t\tbreak;\n\t}\n#else\n\tsta = dm->phydm_sta_info[dm->rssi_min_macid];\n\n\tif (!is_sta_active(sta)) {\n\t\tPHYDM_DBG(dm, DBG_DYN_ARFR, \"[Warning] %s invalid STA\\n\",\n\t\t\t  __func__);\n\t\treturn;\n\t}\n\n\trate_order = phydm_rate_order_compute(dm, sta->ra_info.curr_tx_rate);\n#endif\n\tif (rate_order_min == 0) {\n\t\trrsr_mask = 0x1f;\n\t} else {\n\t\trrsr_mask_ofdm = (u32)phydm_gen_bitmask(rate_order_min);\n\t\trrsr_mask = (rrsr_mask_ofdm << 4) | 0xf;\n\t}\n\n\t/*ra->rrsr_val_init = 0x15d;*/\n\n\tphydm_masked_rrsr_set_register(dm, ra->rrsr_val_init & rrsr_mask);\n\n\tPHYDM_DBG(dm, DBG_DYN_ARFR,\n\t\t  \"tx{rate, rate_order_min}={0x%x, %d}, rrsr_init=0x%x, ofdm_rrsr_mask=0x%x, rrsr_val=0x%x\\n\",\n\t\t  tx_rate_idx, rate_order_min, ra->rrsr_val_init,\n\t\t  rrsr_mask, ra->rrsr_val_curr);\n}\n\nvoid phydm_ra_info_watchdog(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tphydm_ra_common_info_update(dm);\n\tphydm_ra_dynamic_retry_count(dm);\n\tphydm_rrsr_mask(dm);\n\tphydm_ra_mask_watchdog(dm);\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\todm_refresh_basic_rate_mask(dm);\n#endif\n}\n\nvoid phydm_rrsr_en(void *dm_void, boolean en_rrsr)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra_tab = &dm->dm_ra_table;\n\n\tra_tab->dynamic_rrsr_en = en_rrsr;\n}\n\nvoid phydm_ra_info_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra_tab = &dm->dm_ra_table;\n\n\tra_tab->highest_client_tx_rate_order = 0;\n\tra_tab->highest_client_tx_order = 0;\n\tra_tab->ra_th_ofst = 0;\n\tra_tab->ra_ofst_direc = 0;\n\tra_tab->rrsr_val_init = odm_get_mac_reg(dm, R_0x440, MASKDWORD);\n\tra_tab->dynamic_rrsr_en = true;\n\n#if (RTL8822B_SUPPORT == 1)\n\tif (dm->support_ic_type == ODM_RTL8822B) {\n\t\tu32 ret_value;\n\n\t\tret_value = odm_get_bb_reg(dm, R_0x4c8, MASKBYTE2);\n\t\todm_set_bb_reg(dm, R_0x4cc, MASKBYTE3, (ret_value - 1));\n\t}\n#endif\n\n\t#if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/\n\tphydm_ra_dynamic_retry_limit_init(dm);\n\t#endif\n\n\t#if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/\n\tphydm_ra_dynamic_rate_id_init(dm);\n\t#endif\n\n\tphydm_rate_adaptive_mask_init(dm);\n}\n\nu8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 rts_ini_rate = ODM_RATE6M;\n\n\tif (is_erp_protect) { /* use CCK rate as RTS*/\n\t\trts_ini_rate = ODM_RATE1M;\n\t} else {\n\t\tswitch (tx_rate) {\n\t\tcase ODM_RATEVHTSS4MCS9:\n\t\tcase ODM_RATEVHTSS4MCS8:\n\t\tcase ODM_RATEVHTSS4MCS7:\n\t\tcase ODM_RATEVHTSS4MCS6:\n\t\tcase ODM_RATEVHTSS4MCS5:\n\t\tcase ODM_RATEVHTSS4MCS4:\n\t\tcase ODM_RATEVHTSS4MCS3:\n\t\tcase ODM_RATEVHTSS3MCS9:\n\t\tcase ODM_RATEVHTSS3MCS8:\n\t\tcase ODM_RATEVHTSS3MCS7:\n\t\tcase ODM_RATEVHTSS3MCS6:\n\t\tcase ODM_RATEVHTSS3MCS5:\n\t\tcase ODM_RATEVHTSS3MCS4:\n\t\tcase ODM_RATEVHTSS3MCS3:\n\t\tcase ODM_RATEVHTSS2MCS9:\n\t\tcase ODM_RATEVHTSS2MCS8:\n\t\tcase ODM_RATEVHTSS2MCS7:\n\t\tcase ODM_RATEVHTSS2MCS6:\n\t\tcase ODM_RATEVHTSS2MCS5:\n\t\tcase ODM_RATEVHTSS2MCS4:\n\t\tcase ODM_RATEVHTSS2MCS3:\n\t\tcase ODM_RATEVHTSS1MCS9:\n\t\tcase ODM_RATEVHTSS1MCS8:\n\t\tcase ODM_RATEVHTSS1MCS7:\n\t\tcase ODM_RATEVHTSS1MCS6:\n\t\tcase ODM_RATEVHTSS1MCS5:\n\t\tcase ODM_RATEVHTSS1MCS4:\n\t\tcase ODM_RATEVHTSS1MCS3:\n\t\tcase ODM_RATEMCS31:\n\t\tcase ODM_RATEMCS30:\n\t\tcase ODM_RATEMCS29:\n\t\tcase ODM_RATEMCS28:\n\t\tcase ODM_RATEMCS27:\n\t\tcase ODM_RATEMCS23:\n\t\tcase ODM_RATEMCS22:\n\t\tcase ODM_RATEMCS21:\n\t\tcase ODM_RATEMCS20:\n\t\tcase ODM_RATEMCS19:\n\t\tcase ODM_RATEMCS15:\n\t\tcase ODM_RATEMCS14:\n\t\tcase ODM_RATEMCS13:\n\t\tcase ODM_RATEMCS12:\n\t\tcase ODM_RATEMCS11:\n\t\tcase ODM_RATEMCS7:\n\t\tcase ODM_RATEMCS6:\n\t\tcase ODM_RATEMCS5:\n\t\tcase ODM_RATEMCS4:\n\t\tcase ODM_RATEMCS3:\n\t\tcase ODM_RATE54M:\n\t\tcase ODM_RATE48M:\n\t\tcase ODM_RATE36M:\n\t\tcase ODM_RATE24M:\n\t\t\trts_ini_rate = ODM_RATE24M;\n\t\t\tbreak;\n\t\tcase ODM_RATEVHTSS4MCS2:\n\t\tcase ODM_RATEVHTSS4MCS1:\n\t\tcase ODM_RATEVHTSS3MCS2:\n\t\tcase ODM_RATEVHTSS3MCS1:\n\t\tcase ODM_RATEVHTSS2MCS2:\n\t\tcase ODM_RATEVHTSS2MCS1:\n\t\tcase ODM_RATEVHTSS1MCS2:\n\t\tcase ODM_RATEVHTSS1MCS1:\n\t\tcase ODM_RATEMCS26:\n\t\tcase ODM_RATEMCS25:\n\t\tcase ODM_RATEMCS18:\n\t\tcase ODM_RATEMCS17:\n\t\tcase ODM_RATEMCS10:\n\t\tcase ODM_RATEMCS9:\n\t\tcase ODM_RATEMCS2:\n\t\tcase ODM_RATEMCS1:\n\t\tcase ODM_RATE18M:\n\t\tcase ODM_RATE12M:\n\t\t\trts_ini_rate = ODM_RATE12M;\n\t\t\tbreak;\n\t\tcase ODM_RATEVHTSS4MCS0:\n\t\tcase ODM_RATEVHTSS3MCS0:\n\t\tcase ODM_RATEVHTSS2MCS0:\n\t\tcase ODM_RATEVHTSS1MCS0:\n\t\tcase ODM_RATEMCS24:\n\t\tcase ODM_RATEMCS16:\n\t\tcase ODM_RATEMCS8:\n\t\tcase ODM_RATEMCS0:\n\t\tcase ODM_RATE9M:\n\t\tcase ODM_RATE6M:\n\t\t\trts_ini_rate = ODM_RATE6M;\n\t\t\tbreak;\n\t\tcase ODM_RATE11M:\n\t\tcase ODM_RATE5_5M:\n\t\tcase ODM_RATE2M:\n\t\tcase ODM_RATE1M:\n\t\t\trts_ini_rate = ODM_RATE1M;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\trts_ini_rate = ODM_RATE6M;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (*dm->band_type == ODM_BAND_5G) {\n\t\tif (rts_ini_rate < ODM_RATE6M)\n\t\t\trts_ini_rate = ODM_RATE6M;\n\t}\n\treturn rts_ini_rate;\n}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\nvoid odm_refresh_basic_rate_mask(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tvoid *adapter = dm->adapter;\n\tstatic u8 stage = 0;\n\tu8 cur_stage = 0;\n\tOCTET_STRING os_rate_set;\n\tPMGNT_INFO mgnt_info = GetDefaultMgntInfo(((PADAPTER)adapter));\n\tu8 rate_set[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M};\n\n\tif (dm->support_ic_type != ODM_RTL8812 && dm->support_ic_type != ODM_RTL8821)\n\t\treturn;\n\n\tif (dm->is_linked == false) /* unlink Default port information */\n\t\tcur_stage = 0;\n\telse if (dm->rssi_min < 40) /* @link RSSI  < 40% */\n\t\tcur_stage = 1;\n\telse if (dm->rssi_min > 45) /* @link RSSI > 45% */\n\t\tcur_stage = 3;\n\telse\n\t\tcur_stage = 2; /* @link  25% <= RSSI <= 30% */\n\n\tif (cur_stage != stage) {\n\t\tif (cur_stage == 1) {\n\t\t\tFillOctetString(os_rate_set, rate_set, 5);\n\t\t\tFilterSupportRate(mgnt_info->mBrates, &os_rate_set, false);\n\t\t\tphydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)&os_rate_set);\n\t\t} else if (cur_stage == 3 && (stage == 1 || stage == 2))\n\t\t\tphydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)(&mgnt_info->mBrates));\n\t}\n\n\tstage = cur_stage;\n}\n\n#endif\n\n#if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/\n\nvoid phydm_retry_limit_table_bound(\n\tvoid *dm_void,\n\tu8 *retry_limit,\n\tu8 offset)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra_tab = &dm->dm_ra_table;\n\n\tif (*retry_limit > offset) {\n\t\t*retry_limit -= offset;\n\n\t\tif (*retry_limit < ra_tab->retrylimit_low)\n\t\t\t*retry_limit = ra_tab->retrylimit_low;\n\t\telse if (*retry_limit > ra_tab->retrylimit_high)\n\t\t\t*retry_limit = ra_tab->retrylimit_high;\n\t} else\n\t\t*retry_limit = ra_tab->retrylimit_low;\n}\n\nvoid phydm_reset_retry_limit_table(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra_t = &dm->dm_ra_table;\n\tu8 i;\n\n\tu8 per_rate_retrylimit_table_20M[ODM_RATEMCS15 + 1] = {\n\t\t1, 1, 2, 4, /*@CCK*/\n\t\t2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/\n\t\t2, 4, 6, 8, 12, 18, 20, 22, /*@20M HT-1SS*/\n\t\t2, 4, 6, 8, 12, 18, 20, 22 /*@20M HT-2SS*/\n\t};\n\tu8 per_rate_retrylimit_table_40M[ODM_RATEMCS15 + 1] = {\n\t\t1, 1, 2, 4, /*@CCK*/\n\t\t2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/\n\t\t4, 8, 12, 16, 24, 32, 32, 32, /*@40M HT-1SS*/\n\t\t4, 8, 12, 16, 24, 32, 32, 32 /*@40M HT-2SS*/\n\t};\n\n\tmemcpy(&ra_t->per_rate_retrylimit_20M[0],\n\t       &per_rate_retrylimit_table_20M[0], PHY_NUM_RATE_IDX);\n\tmemcpy(&ra_t->per_rate_retrylimit_40M[0],\n\t       &per_rate_retrylimit_table_40M[0], PHY_NUM_RATE_IDX);\n\n\tfor (i = 0; i < PHY_NUM_RATE_IDX; i++) {\n\t\tphydm_retry_limit_table_bound(dm,\n\t\t\t\t\t      &ra_t->per_rate_retrylimit_20M[i],\n\t\t\t\t\t      0);\n\t\tphydm_retry_limit_table_bound(dm,\n\t\t\t\t\t      &ra_t->per_rate_retrylimit_40M[i],\n\t\t\t\t\t      0);\n\t}\n}\n\nvoid phydm_ra_dynamic_retry_limit_init(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra_tab = &dm->dm_ra_table;\n\n\tra_tab->retry_descend_num = RA_RETRY_DESCEND_NUM;\n\tra_tab->retrylimit_low = RA_RETRY_LIMIT_LOW;\n\tra_tab->retrylimit_high = RA_RETRY_LIMIT_HIGH;\n\n\tphydm_reset_retry_limit_table(dm);\n}\n\nvoid phydm_ra_dynamic_retry_limit(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra_tab = &dm->dm_ra_table;\n\tu8 i, retry_offset;\n\tu32 ma_rx_tp;\n\n\tif (dm->pre_number_active_client == dm->number_active_client) {\n\t\tPHYDM_DBG(dm, DBG_RA,\n\t\t\t  \"pre_number_active_client ==  number_active_client\\n\");\n\t\treturn;\n\n\t} else {\n\t\tif (dm->number_active_client == 1) {\n\t\t\tphydm_reset_retry_limit_table(dm);\n\t\t\tPHYDM_DBG(dm, DBG_RA,\n\t\t\t\t  \"one client only->reset to default value\\n\");\n\t\t} else {\n\t\t\tretry_offset = dm->number_active_client * ra_tab->retry_descend_num;\n\n\t\t\tfor (i = 0; i < PHY_NUM_RATE_IDX; i++) {\n\t\t\t\tphydm_retry_limit_table_bound(dm,\n\t\t\t\t\t\t\t      &ra_tab->per_rate_retrylimit_20M[i],\n\t\t\t\t\t\t\t      retry_offset);\n\t\t\t\tphydm_retry_limit_table_bound(dm,\n\t\t\t\t\t\t\t      &ra_tab->per_rate_retrylimit_40M[i],\n\t\t\t\t\t\t\t      retry_offset);\n\t\t\t}\n\t\t}\n\t}\n}\n#endif\n\n#if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/\nvoid phydm_ra_dynamic_rate_id_on_assoc(\n\tvoid *dm_void,\n\tu8 wireless_mode,\n\tu8 init_rate_id)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_RA,\n\t\t  \"[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\\n\",\n\t\t  dm->rf_type, wireless_mode, init_rate_id);\n\n\tif (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) {\n\t\tif ((dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) &&\n\t\t    (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G))) {\n\t\t\tPHYDM_DBG(dm, DBG_RA,\n\t\t\t\t  \"[ON ASSOC] set N-2SS ARFR5 table\\n\");\n\t\t\todm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/\n\t\t\todm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/\n\t\t} else if ((dm->support_ic_type & (ODM_RTL8812)) &&\n\t\t\t   (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY))) {\n\t\t\tPHYDM_DBG(dm, DBG_RA,\n\t\t\t\t  \"[ON ASSOC] set AC-2SS ARFR0 table\\n\");\n\t\t\todm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/\n\t\t\todm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/\n\t\t}\n\t}\n}\n\nvoid phydm_ra_dynamic_rate_id_init(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) {\n\t\todm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/\n\t\todm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/\n\n\t\todm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/\n\t\todm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/\n\t}\n}\n\nvoid phydm_update_rate_id(\n\tvoid *dm_void,\n\tu8 rate,\n\tu8 platform_macid)\n{\n#if 0\n\n\tstruct dm_struct\t*dm = (struct dm_struct *)dm_void;\n\tstruct ra_table\t\t*ra_tab = &dm->dm_ra_table;\n\tu8\t\tcurrent_tx_ss;\n\tu8\t\trate_idx = rate & 0x7f; /*remove bit7 SGI*/\n\tenum wireless_set wireless_set;\n\tu8\t\tphydm_macid;\n\tstruct cmn_sta_info\t*sta;\n\n#if 0\n\tif (rate_idx >= ODM_RATEVHTSS2MCS0) {\n\t\tPHYDM_DBG(dm, DBG_RA, \"rate[%d]: (( VHT2SS-MCS%d ))\\n\",\n\t\t\t  platform_macid, (rate_idx - ODM_RATEVHTSS2MCS0));\n\t\t/*@dummy for SD4 check patch*/\n\t} else if (rate_idx >= ODM_RATEVHTSS1MCS0) {\n\t\tPHYDM_DBG(dm, DBG_RA, \"rate[%d]: (( VHT1SS-MCS%d ))\\n\",\n\t\t\t  platform_macid, (rate_idx - ODM_RATEVHTSS1MCS0));\n\t\t/*@dummy for SD4 check patch*/\n\t} else if (rate_idx >= ODM_RATEMCS0) {\n\t\tPHYDM_DBG(dm, DBG_RA, \"rate[%d]: (( HT-MCS%d ))\\n\",\n\t\t\t  platform_macid, (rate_idx - ODM_RATEMCS0));\n\t\t/*@dummy for SD4 check patch*/\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_RA, \"rate[%d]: (( HT-MCS%d ))\\n\",\n\t\t\t  platform_macid, rate_idx);\n\t\t/*@dummy for SD4 check patch*/\n\t}\n#endif\n\n\tphydm_macid = dm->phydm_macid_table[platform_macid];\n\tsta = dm->phydm_sta_info[phydm_macid];\n\n\tif (is_sta_active(sta)) {\n\t\twireless_set = sta->support_wireless_set;\n\n\t\tif (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) {\n\t\t\tif (wireless_set & WIRELESS_HT) { /*N mode*/\n\t\t\t\tif (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*@2SS mode*/\n\n\t\t\t\t\tsta->ra_info.rate_id  = ARFR_5_RATE_ID;\n\t\t\t\t\tPHYDM_DBG(dm, DBG_RA, \"ARFR_5\\n\");\n\t\t\t\t}\n\t\t\t} else if (wireless_set & WIRELESS_VHT) {/*@AC mode*/\n\t\t\t\tif (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*@2SS mode*/\n\n\t\t\t\t\tsta->ra_info.rate_id  = ARFR_0_RATE_ID;\n\t\t\t\t\tPHYDM_DBG(dm, DBG_RA, \"ARFR_0\\n\");\n\t\t\t\t}\n\t\t\t} else\n\t\t\t\tsta->ra_info.rate_id  = ARFR_0_RATE_ID;\n\n\t\t\tPHYDM_DBG(dm, DBG_RA, \"UPdate_RateID[%d]: (( 0x%x ))\\n\",\n\t\t\t\t  platform_macid, sta->ra_info.rate_id);\n\t\t}\n\t}\n#endif\n}\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_rainfo.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDMRAINFO_H__\n#define __PHYDMRAINFO_H__\n\n#define RAINFO_VERSION \"8.0\"\n\n#define\tFORCED_UPDATE_RAMASK_PERIOD\t5\n\n#define\tH2C_MAX_LENGTH\t\t7\n\n#define\tRA_FLOOR_UP_GAP\t\t3\n#define\tRA_FLOOR_TABLE_SIZE\t7\n\n#define\tACTIVE_TP_THRESHOLD\t1\n#define\tRA_RETRY_DESCEND_NUM\t2\n#define\tRA_RETRY_LIMIT_LOW\t4\n#define\tRA_RETRY_LIMIT_HIGH\t32\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t#define\tFIRST_MACID\t1\n#else\n\t#define\tFIRST_MACID\t0\n#endif\n\n/* @1 ============================================================\n * 1 enumrate\n * 1 ============================================================\n */\n\nenum phydm_ra_dbg_para {\n\tRADBG_PCR_TH_OFFSET\t= 0,\n\tRADBG_RTY_PENALTY\t= 1,\n\tRADBG_N_HIGH\t\t= 2,\n\tRADBG_N_LOW\t\t= 3,\n\tRADBG_TRATE_UP_TABLE\t= 4,\n\tRADBG_TRATE_DOWN_TABLE\t= 5,\n\tRADBG_TRYING_NECESSARY\t= 6,\n\tRADBG_TDROPING_NECESSARY = 7,\n\tRADBG_RATE_UP_RTY_RATIO\t= 8,\n\tRADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */\n\n\tRADBG_DEBUG_MONITOR1\t= 0xc,\n\tRADBG_DEBUG_MONITOR2\t= 0xd,\n\tRADBG_DEBUG_MONITOR3\t= 0xe,\n\tRADBG_DEBUG_MONITOR4\t= 0xf,\n\tRADBG_DEBUG_MONITOR5\t= 0x10,\n\tNUM_RA_PARA\n};\n\nenum phydm_wireless_mode {\n\tPHYDM_WIRELESS_MODE_UNKNOWN\t= 0x00,\n\tPHYDM_WIRELESS_MODE_A\t\t= 0x01,\n\tPHYDM_WIRELESS_MODE_B\t\t= 0x02,\n\tPHYDM_WIRELESS_MODE_G\t\t= 0x04,\n\tPHYDM_WIRELESS_MODE_AUTO\t= 0x08,\n\tPHYDM_WIRELESS_MODE_N_24G\t= 0x10,\n\tPHYDM_WIRELESS_MODE_N_5G\t= 0x20,\n\tPHYDM_WIRELESS_MODE_AC_5G\t= 0x40,\n\tPHYDM_WIRELESS_MODE_AC_24G\t= 0x80,\n\tPHYDM_WIRELESS_MODE_AC_ONLY\t= 0x100,\n\tPHYDM_WIRELESS_MODE_MAX\t\t= 0x800,\n\tPHYDM_WIRELESS_MODE_ALL\t\t= 0xFFFF\n};\n\nenum phydm_rateid_idx {\n\tPHYDM_BGN_40M_2SS\t= 0,\n\tPHYDM_BGN_40M_1SS\t= 1,\n\tPHYDM_BGN_20M_2SS\t= 2,\n\tPHYDM_BGN_20M_1SS\t= 3,\n\tPHYDM_GN_N2SS\t\t= 4,\n\tPHYDM_GN_N1SS\t\t= 5,\n\tPHYDM_BG\t\t= 6,\n\tPHYDM_G\t\t\t= 7,\n\tPHYDM_B_20M\t\t= 8,\n\tPHYDM_ARFR0_AC_2SS\t= 9,\n\tPHYDM_ARFR1_AC_1SS\t= 10,\n\tPHYDM_ARFR2_AC_2G_1SS\t= 11,\n\tPHYDM_ARFR3_AC_2G_2SS\t= 12,\n\tPHYDM_ARFR4_AC_3SS\t= 13,\n\tPHYDM_ARFR5_N_3SS\t= 14,\n\tPHYDM_ARFR7_N_4SS\t= 15,\n\tPHYDM_ARFR6_AC_4SS\t= 16\n};\n\nenum phydm_qam_order {\n\tPHYDM_QAM_CCK\t= 0,\n\tPHYDM_QAM_BPSK\t= 1,\n\tPHYDM_QAM_QPSK\t= 2,\n\tPHYDM_QAM_16QAM\t= 3,\n\tPHYDM_QAM_64QAM\t= 4,\n\tPHYDM_QAM_256QAM = 5\n};\n\n#if (RATE_ADAPTIVE_SUPPORT == 1)/* @88E RA */\n\nstruct _phydm_txstatistic_ {\n\tu32\thw_total_tx;\n\tu32\thw_tx_success;\n\tu32\thw_tx_rty;\n\tu32\thw_tx_drop;\n};\n\n/* @1 ============================================================\n * 1  structure\n * 1 ============================================================\n */\nstruct _odm_ra_info_ {\n\tu8\trate_id;\n\tu32\trate_mask;\n\tu32\tra_use_rate;\n\tu8\trate_sgi;\n\tu8\trssi_sta_ra;\n\tu8\tpre_rssi_sta_ra;\n\tu8\tsgi_enable;\n\tu8\tdecision_rate;\n\tu8\tpre_rate;\n\tu8\thighest_rate;\n\tu8\tlowest_rate;\n\tu32\tnsc_up;\n\tu32\tnsc_down;\n\tu16\tRTY[5];\n\tu32\tTOTAL;\n\tu16\tDROP;\n\tu8\tactive;\n\tu16\trpt_time;\n\tu8\tra_waiting_counter;\n\tu8\tra_pending_counter;\n\tu8\tra_drop_after_down;\n#if 1 /* POWER_TRAINING_ACTIVE == 1 */ /* For compile  pass only~! */\n\tu8\tpt_active;\t/* on or off */\n\tu8\tpt_try_state;\t/* @0 trying state, 1 for decision state */\n\tu8\tpt_stage;\t/* @0~6 */\n\tu8\tpt_stop_count;\t/* Stop PT counter */\n\tu8\tpt_pre_rate;\t/* @if rate change do PT */\n\tu8\tpt_pre_rssi;\t/* @if RSSI change 5% do PT */\n\tu8\tpt_mode_ss;\t/* @decide whitch rate should do PT */\n\tu8\tra_stage;\t/* @StageRA, decide how many times RA will be done between PT */\n\tu8\tpt_smooth_factor;\n#endif\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP) &&\t((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))\n\tu8\trate_down_counter;\n\tu8\trate_up_counter;\n\tu8\trate_direction;\n\tu8\tbounding_type;\n\tu8\tbounding_counter;\n\tu8\tbounding_learning_time;\n\tu8\trate_down_start_time;\n#endif\n};\n#endif\n\n\nstruct ra_table {\n\tu8\tfirstconnect;\n\t/*@u8\tlink_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];*/\n\t#ifdef MU_EX_MACID\n\tu8\tmu1_rate[MU_EX_MACID];\n\t#endif\n\tu8\thighest_client_tx_order;\n\tu16\thighest_client_tx_rate_order;\n\tu8\tpower_tracking_flag;\n\tu8\tra_th_ofst; /*RA_threshold_offset*/\n\tu8\tra_ofst_direc; /*RA_offset_direction*/\n\tu8\tup_ramask_cnt; /*@force update_ra_mask counter*/\n\tu8\tup_ramask_cnt_tmp; /*@Just for debug, should be removed latter*/\n\tu32\trrsr_val_init; /*0x440*/\n\tu32\trrsr_val_curr; /*0x440*/\n\tboolean dynamic_rrsr_en;\n#if 0\t/*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/\n\tu8\tper_rate_retrylimit_20M[PHY_NUM_RATE_IDX];\n\tu8\tper_rate_retrylimit_40M[PHY_NUM_RATE_IDX];\n\tu8\tretry_descend_num;\n\tu8\tretrylimit_low;\n\tu8\tretrylimit_high;\n#endif\n\tu8\tldpc_thres; /* @if RSSI > ldpc_th => switch from LPDC to BCC */\n\tvoid (*record_ra_info)(void *dm_void, u8 macid,\n\t\t\t       struct cmn_sta_info *sta, u64 ra_mask);\n};\n\n/* @1 ============================================================\n * 1  Function Prototype\n * 1 ============================================================\n */\nboolean phydm_is_cck_rate(void *dm_void, u8 rate);\n\nboolean phydm_is_ofdm_rate(void *dm_void, u8 rate);\n\nboolean phydm_is_ht_rate(void *dm_void, u8 rate);\n\nboolean phydm_is_vht_rate(void *dm_void, u8 rate);\n\nu8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type);\n\nu8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate);\n\nvoid phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t     char *output, u32 *_out_len);\n\nvoid phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t    u32 *_out_len);\n\nvoid odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);\n\nvoid phydm_ra_dynamic_retry_count(void *dm_void);\n\n\nvoid phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component);\n\nvoid phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size);\n\nvoid phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);\n\nu8 phydm_rate_order_compute(void *dm_void, u8 rate_idx);\n\nvoid phydm_rrsr_set_register(void *dm_void, u32 rrsr_val);\n\nvoid phydm_ra_info_watchdog(void *dm_void);\n\nvoid phydm_rrsr_en(void *dm_void, boolean en_rrsr);\n\nvoid phydm_ra_info_init(void *dm_void);\n\nvoid phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc,\n\t\t\t\t   u8 ra_th_ofst);\n\nu8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode);\n\nu8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw);\n#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\nvoid phydm_update_hal_ra_mask(\n\tvoid *dm_void,\n\tu32 wireless_mode,\n\tu8 rf_type,\n\tu8 BW,\n\tu8 mimo_ps_enable,\n\tu8 disable_cck_rate,\n\tu32 *ratr_bitmap_msb_in,\n\tu32 *ratr_bitmap_in,\n\tu8 tx_rate_level);\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\nu8 phydm_get_plcp(void *dm_void, u16 macid);\n#endif\n\nvoid phydm_refresh_rate_adaptive_mask(void *dm_void);\n\nu8 phydm_get_rx_stream_num(void *dm_void, enum rf_type type);\n\nu8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state);\n\nvoid odm_ra_post_action_on_assoc(void *dm);\n\nu8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect);\n\nvoid phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used,\n\t\t\t char *output, u32 *_out_len);\n\nu8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx);\n\nvoid phydm_ra_registed(void *dm_void, u8 macid, u8 rssi_from_assoc);\n\nvoid phydm_ra_offline(void *dm_void, u8 macid);\n\nvoid phydm_ra_mask_watchdog(void *dm_void);\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid odm_refresh_basic_rate_mask(\n\tvoid *dm_void);\n#endif\n#endif /*@#ifndef __PHYDMRAINFO_H__*/\n"
  },
  {
    "path": "hal/phydm/phydm_reg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n/*************************************************************\n * File Name: odm_reg.h\n *\n * Description:\n *\n * This file is for general register definition.\n *\n *\n ************************************************************/\n#ifndef __HAL_ODM_REG_H__\n#define __HAL_ODM_REG_H__\n\n/*@\n * Register Definition\n *\n */\n\n/* @MAC REG */\n#define\tODM_BB_RESET\t\t\t\t0x002\n#define\tODM_DUMMY\t\t\t\t0x4fe\n#define\tRF_T_METER_OLD\t\t\t\t0x24\n#define\tRF_T_METER_NEW\t\t\t\t0x42\n\n#define\tODM_EDCA_VO_PARAM\t\t\t0x500\n#define\tODM_EDCA_VI_PARAM\t\t\t0x504\n#define\tODM_EDCA_BE_PARAM\t\t\t0x508\n#define\tODM_EDCA_BK_PARAM\t\t\t0x50C\n#define\tODM_TXPAUSE\t\t\t\t0x522\n\n/* @LTE_COEX */\n#define REG_LTECOEX_CTRL\t\t\t0x07C0\n#define REG_LTECOEX_WRITE_DATA\t\t\t0x07C4\n#define REG_LTECOEX_READ_DATA\t\t\t0x07C8\n#define REG_LTECOEX_PATH_CONTROL\t\t0x70\n\n/* @BB REG */\n#define\tODM_FPGA_PHY0_PAGE8\t\t\t0x800\n#define\tODM_PSD_SETTING\t\t\t\t0x808\n#define\tODM_AFE_SETTING\t\t\t\t0x818\n#define\tODM_TXAGC_B_6_18\t\t\t0x830\n#define\tODM_TXAGC_B_24_54\t\t\t0x834\n#define\tODM_TXAGC_B_MCS32_5\t\t\t0x838\n#define\tODM_TXAGC_B_MCS0_MCS3\t\t\t0x83c\n#define\tODM_TXAGC_B_MCS4_MCS7\t\t\t0x848\n#define\tODM_TXAGC_B_MCS8_MCS11\t\t\t0x84c\n#define\tODM_ANALOG_REGISTER\t\t\t0x85c\n#define\tODM_RF_INTERFACE_OUTPUT\t\t\t0x860\n#define\tODM_TXAGC_B_MCS12_MCS15\t\t\t0x868\n#define\tODM_TXAGC_B_11_A_2_11\t\t\t0x86c\n#define\tODM_AD_DA_LSB_MASK\t\t\t0x874\n#define\tODM_ENABLE_3_WIRE\t\t\t0x88c\n#define\tODM_PSD_REPORT\t\t\t\t0x8b4\n#define\tODM_R_ANT_SELECT\t\t\t0x90c\n#define\tODM_CCK_ANT_SELECT\t\t\t0xa07\n#define\tODM_CCK_PD_THRESH\t\t\t0xa0a\n#define\tODM_CCK_RF_REG1\t\t\t\t0xa11\n#define\tODM_CCK_MATCH_FILTER\t\t\t0xa20\n#define\tODM_CCK_RAKE_MAC\t\t\t0xa2e\n#define\tODM_CCK_CNT_RESET\t\t\t0xa2d\n#define\tODM_CCK_TX_DIVERSITY\t\t\t0xa2f\n#define\tODM_CCK_FA_CNT_MSB\t\t\t0xa5b\n#define\tODM_CCK_FA_CNT_LSB\t\t\t0xa5c\n#define\tODM_CCK_NEW_FUNCTION\t\t\t0xa75\n#define\tODM_OFDM_PHY0_PAGE_C\t\t\t0xc00\n#define\tODM_OFDM_RX_ANT\t\t\t\t0xc04\n#define\tODM_R_A_RXIQI\t\t\t\t0xc14\n#define\tODM_R_A_AGC_CORE1\t\t\t0xc50\n#define\tODM_R_A_AGC_CORE2\t\t\t0xc54\n#define\tODM_R_B_AGC_CORE1\t\t\t0xc58\n#define\tODM_R_AGC_PAR\t\t\t\t0xc70\n#define\tODM_R_HTSTF_AGC_PAR\t\t\t0xc7c\n#define\tODM_TX_PWR_TRAINING_A\t\t\t0xc90\n#define\tODM_TX_PWR_TRAINING_B\t\t\t0xc98\n#define\tODM_OFDM_FA_CNT1\t\t\t0xcf0\n#define\tODM_OFDM_PHY0_PAGE_D\t\t\t0xd00\n#define\tODM_OFDM_FA_CNT2\t\t\t0xda0\n#define\tODM_OFDM_FA_CNT3\t\t\t0xda4\n#define\tODM_OFDM_FA_CNT4\t\t\t0xda8\n#define\tODM_TXAGC_A_6_18\t\t\t0xe00\n#define\tODM_TXAGC_A_24_54\t\t\t0xe04\n#define\tODM_TXAGC_A_1_MCS32\t\t\t0xe08\n#define\tODM_TXAGC_A_MCS0_MCS3\t\t\t0xe10\n#define\tODM_TXAGC_A_MCS4_MCS7\t\t\t0xe14\n#define\tODM_TXAGC_A_MCS8_MCS11\t\t\t0xe18\n#define\tODM_TXAGC_A_MCS12_MCS15\t\t\t0xe1c\n\n/* RF REG */\n#define\tODM_GAIN_SETTING\t\t\t0x00\n#define\tODM_CHANNEL\t\t\t\t0x18\n#define\tODM_RF_T_METER\t\t\t\t0x24\n#define\tODM_RF_T_METER_92D\t\t\t0x42\n#define\tODM_RF_T_METER_88E\t\t\t0x42\n#define\tODM_RF_T_METER_92E\t\t\t0x42\n#define\tODM_RF_T_METER_8812\t\t\t0x42\n#define\tREG_RF_TX_GAIN_OFFSET\t\t\t0x55\n\n/* @ant Detect Reg */\n#define\tODM_DPDT\t\t\t\t0x300\n\n/* PSD Init */\n#define\tODM_PSDREG\t\t\t\t0x808\n\n/* @92D path Div */\n#define\tPATHDIV_REG\t\t\t\t0xB30\n#define\tPATHDIV_TRI\t\t\t\t0xBA0\n\n\n/*@\n * Bitmap Definition\n */\n#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\n\t/* TX AGC */\n\t#define\t\tREG_TX_AGC_A_CCK_11_CCK_1_JAGUAR\t\t0xc20\n\t#define\t\tREG_TX_AGC_A_OFDM18_OFDM6_JAGUAR\t\t0xc24\n\t#define\t\tREG_TX_AGC_A_OFDM54_OFDM24_JAGUAR\t\t0xc28\n\t#define\t\tREG_TX_AGC_A_MCS3_MCS0_JAGUAR\t\t\t0xc2c\n\t#define\t\tREG_TX_AGC_A_MCS7_MCS4_JAGUAR\t\t\t0xc30\n\t#define\t\tREG_TX_AGC_A_MCS11_MCS8_JAGUAR\t\t\t0xc34\n\t#define\t\tREG_TX_AGC_A_MCS15_MCS12_JAGUAR\t\t\t0xc38\n\t#define\t\tREG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR\t0xc3c\n\t#define\t\tREG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR\t0xc40\n\t#define\t\tREG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR\t0xc44\n\t#define\t\tREG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR\t0xc48\n\t#define\t\tREG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR\t0xc4c\n\t#if defined(CONFIG_WLAN_HAL_8814AE)\n\t\t#define\t\tREG_TX_AGC_A_MCS19_MCS16_JAGUAR\t\t0xcd8\n\t\t#define\t\tREG_TX_AGC_A_MCS23_MCS20_JAGUAR\t\t0xcdc\n\t\t#define\t\tREG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR\t0xce0\n\t\t#define\t\tREG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR\t0xce4\n\t\t#define\t\tREG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR\t0xce8\n\t#endif\n\t#define\t\tREG_TX_AGC_B_CCK_11_CCK_1_JAGUAR\t\t0xe20\n\t#define\t\tREG_TX_AGC_B_OFDM18_OFDM6_JAGUAR\t\t0xe24\n\t#define\t\tREG_TX_AGC_B_OFDM54_OFDM24_JAGUAR\t\t0xe28\n\t#define\t\tREG_TX_AGC_B_MCS3_MCS0_JAGUAR\t\t\t0xe2c\n\t#define\t\tREG_TX_AGC_B_MCS7_MCS4_JAGUAR\t\t\t0xe30\n\t#define\t\tREG_TX_AGC_B_MCS11_MCS8_JAGUAR\t\t\t0xe34\n\t#define\t\tREG_TX_AGC_B_MCS15_MCS12_JAGUAR\t\t\t0xe38\n\t#define\t\tREG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR\t0xe3c\n\t#define\t\tREG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR\t0xe40\n\t#define\t\tREG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR\t0xe44\n\t#define\t\tREG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR\t0xe48\n\t#define\t\tREG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR\t0xe4c\n\t#if defined(CONFIG_WLAN_HAL_8814AE)\n\t\t#define\t\tREG_TX_AGC_B_MCS19_MCS16_JAGUAR\t\t0xed8\n\t\t#define\t\tREG_TX_AGC_B_MCS23_MCS20_JAGUAR\t\t0xedc\n\t\t#define\t\tREG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR\t0xee0\n\t\t#define\t\tREG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR\t0xee4\n\t\t#define\t\tREG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR\t0xee8\n\t\t#define\t\tREG_TX_AGC_C_CCK_11_CCK_1_JAGUAR\t0x1820\n\t\t#define\t\tREG_TX_AGC_C_OFDM18_OFDM6_JAGUAR\t0x1824\n\t\t#define\t\tREG_TX_AGC_C_OFDM54_OFDM24_JAGUAR\t0x1828\n\t\t#define\t\tREG_TX_AGC_C_MCS3_MCS0_JAGUAR\t\t0x182c\n\t\t#define\t\tREG_TX_AGC_C_MCS7_MCS4_JAGUAR\t\t0x1830\n\t\t#define\t\tREG_TX_AGC_C_MCS11_MCS8_JAGUAR\t\t0x1834\n\t\t#define\t\tREG_TX_AGC_C_MCS15_MCS12_JAGUAR\t\t0x1838\n\t\t#define\t\tREG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR\t0x183c\n\t\t#define\t\tREG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR\t0x1840\n\t\t#define\t\tREG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR\t0x1844\n\t\t#define\t\tREG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR\t0x1848\n\t\t#define\t\tREG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR\t0x184c\n\t\t#define\t\tREG_TX_AGC_C_MCS19_MCS16_JAGUAR\t\t0x18d8\n\t\t#define\t\tREG_TX_AGC_C_MCS23_MCS20_JAGUAR\t\t0x18dc\n\t\t#define\t\tREG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR\t0x18e0\n\t\t#define\t\tREG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR\t0x18e4\n\t\t#define\t\tREG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR\t0x18e8\n\t\t#define\t\tREG_TX_AGC_D_CCK_11_CCK_1_JAGUAR\t0x1a20\n\t\t#define\t\tREG_TX_AGC_D_OFDM18_OFDM6_JAGUAR\t0x1a24\n\t\t#define\t\tREG_TX_AGC_D_OFDM54_OFDM24_JAGUAR\t0x1a28\n\t\t#define\t\tREG_TX_AGC_D_MCS3_MCS0_JAGUAR\t\t0x1a2c\n\t\t#define\t\tREG_TX_AGC_D_MCS7_MCS4_JAGUAR\t\t0x1a30\n\t\t#define\t\tREG_TX_AGC_D_MCS11_MCS8_JAGUAR\t\t0x1a34\n\t\t#define\t\tREG_TX_AGC_D_MCS15_MCS12_JAGUAR\t\t0x1a38\n\t\t#define\t\tREG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR\t0x1a3c\n\t\t#define\t\tREG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR\t0x1a40\n\t\t#define\t\tREG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR\t0x1a44\n\t\t#define\t\tREG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR\t0x1a48\n\t\t#define\t\tREG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR\t0x1a4c\n\t\t#define\t\tREG_TX_AGC_D_MCS19_MCS16_JAGUAR\t\t0x1ad8\n\t\t#define\t\tREG_TX_AGC_D_MCS23_MCS20_JAGUAR\t\t0x1adc\n\t\t#define\t\tREG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR\t0x1ae0\n\t\t#define\t\tREG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR\t0x1ae4\n\t\t#define\t\tREG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR\t0x1ae8\n\t#endif\n\n\t#define\t\tis_tx_agc_byte0_jaguar\t0xff\n\t#define\t\tis_tx_agc_byte1_jaguar\t0xff00\n\t#define\t\tis_tx_agc_byte2_jaguar\t0xff0000\n\t#define\t\tis_tx_agc_byte3_jaguar\t0xff000000\n#if defined(CONFIG_WLAN_HAL_8198F) || defined(CONFIG_WLAN_HAL_8822CE) ||\\\ndefined(CONFIG_WLAN_HAL_8814BE) || defined(CONFIG_WLAN_HAL_8812FE)\n\t\t#define REG_TX_AGC_CCK_11_CCK_1_JAGUAR3\t\t0x3a00\n\t\t#define REG_TX_AGC_OFDM_18_CCK_6_JAGUAR3\t0x3a04\n\t\t#define\tREG_TX_AGC_OFDM_54_CCK_24_JAGUAR3\t0x3a08\n\t\t#define\tREG_TX_AGC_MCS3_0_JAGUAR3\t\t0x3a0c\n\t\t#define\tREG_TX_AGC_MCS7_4_JAGUAR3\t\t0x3a10\n\t\t#define\tREG_TX_AGC_MCS11_8_JAGUAR3\t\t0x3a14\n\t\t#define\tREG_TX_AGC_MCS15_12_JAGUAR3\t\t0x3a18\n\t\t#define\tREG_TX_AGC_MCS19_16_JAGUAR3\t\t0x3a1c\n\t\t#define\tREG_TX_AGC_MCS23_20_JAGUAR3\t\t0x3a20\n\t\t#define\tREG_TX_AGC_MCS27_24_JAGUAR3\t\t0x3a24\n\t\t#define\tREG_TX_AGC_MCS31_28_JAGUAR3\t\t0x3a28\n\t\t#define\tREG_TX_AGC_VHT_Nss1_MCS3_0_JAGUAR3\t0x3a2c\n\t\t#define\tREG_TX_AGC_VHT_Nss1_MCS7_4_JAGUAR3\t0x3a30\n\t\t#define\tREG_TX_AGC_VHT_NSS2_MCS1_NSS1_MCS8_JAGUAR3\t0x3a34\n\t\t#define\tREG_TX_AGC_VHT_Nss2_MCS5_2_JAGUAR3\t0x3a38\n\t\t#define\tREG_TX_AGC_VHT_Nss2_MCS9_6_JAGUAR3\t0x3a3c\n\t\t#define\tREG_TX_AGC_VHT_Nss3_MCS3_0_JAGUAR3\t0x3a40\n\t\t#define\tREG_TX_AGC_VHT_Nss3_MCS7_4_JAGUAR3\t0x3a44\n\t\t#define\tREG_TX_AGC_VHT_Nss4_MCS1_Nss3_MCS8_JAGUAR3\t0x3a48\n\t\t#define\tREG_TX_AGC_VHT_Nss4_MCS5_2_JAGUAR3\t0x3a4c\n\t\t#define\tREG_TX_AGC_VHT_Nss4_MCS9_6_JAGUAR3\t0x3a50\n#endif\n#endif\n\n#define\tBIT_FA_RESET\t\t\t\t\tBIT(0)\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_regdefine11ac.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __ODM_REGDEFINE11AC_H__\n#define __ODM_REGDEFINE11AC_H__\n\n/* @2 RF REG LIST */\n\n\n\n/* @2 BB REG LIST */\n/* PAGE 8 */\n#define\tODM_REG_CCK_RPT_FORMAT_11AC\t\t0x804\n#define\tODM_REG_BB_RX_PATH_11AC\t\t\t0x808\n#define\tODM_REG_BB_TX_PATH_11AC\t\t\t0x80c\n#define\tODM_REG_BB_ATC_11AC\t\t\t0x860\n#define\tODM_REG_EDCCA_POWER_CAL\t\t\t0x8dc\n#define\tODM_REG_DBG_RPT_11AC\t\t\t0x8fc\n/* PAGE 9 */\n#define\tODM_REG_EDCCA_DOWN_OPT\t\t\t0x900\n#define\tODM_REG_ACBB_EDCCA_ENHANCE\t\t0x944\n#define\todm_adc_trigger_jaguar2\t\t\t0x95C\t/*@ADC sample mode*/\n#define\tODM_REG_OFDM_FA_RST_11AC\t\t0x9A4\n#define\tODM_REG_CCX_PERIOD_11AC\t\t\t0x990\n#define\tODM_REG_NHM_TH9_TH10_11AC\t\t0x994\n#define\tODM_REG_CLM_11AC\t\t\t0x994\n#define\tODM_REG_NHM_TH3_TO_TH0_11AC\t\t0x998\n#define\tODM_REG_NHM_TH7_TO_TH4_11AC\t\t0x99c\n#define\tODM_REG_NHM_TH8_11AC\t\t\t0x9a0\n#define\tODM_REG_NHM_9E8_11AC\t\t\t0x9e8\n#define\tODM_REG_CSI_CONTENT_VALUE\t\t0x9b4\n/* PAGE A */\n#define\tODM_REG_CCK_CCA_11AC\t\t\t0xA0A\n#define\tODM_REG_CCK_FA_RST_11AC\t\t\t0xA2C\n#define\tODM_REG_CCK_FA_11AC\t\t\t0xA5C\n/* PAGE B */\n#define\tODM_REG_RST_RPT_11AC\t\t\t0xB58\n/* PAGE C */\n#define\tODM_REG_TRMUX_11AC\t\t\t0xC08\n#define\tODM_REG_IGI_A_11AC\t\t\t0xC50\n/* PAGE E */\n#define\tODM_REG_IGI_B_11AC\t\t\t0xE50\n#define\tODM_REG_ANT_11AC_B\t\t\t0xE08\n/* PAGE F */\n#define\tODM_REG_CCK_CRC32_CNT_11AC\t\t0xF04\n#define\tODM_REG_CCK_CCA_CNT_11AC\t\t0xF08\n#define\tODM_REG_VHT_CRC32_CNT_11AC\t\t0xF0c\n#define\tODM_REG_HT_CRC32_CNT_11AC\t\t0xF10\n#define\tODM_REG_OFDM_CRC32_CNT_11AC\t\t0xF14\n#define\tODM_REG_OFDM_FA_11AC\t\t\t0xF48\n#define\tODM_REG_OFDM_FA_TYPE1_11AC\t\t0xFCC\n#define\tODM_REG_OFDM_FA_TYPE2_11AC\t\t0xFD0\n#define\tODM_REG_OFDM_FA_TYPE3_11AC\t\t0xFBC\n#define\tODM_REG_OFDM_FA_TYPE4_11AC\t\t0xFC0\n#define\tODM_REG_OFDM_FA_TYPE5_11AC\t\t0xFC4\n#define\tODM_REG_OFDM_FA_TYPE6_11AC\t\t0xFC8\n#define\tODM_REG_RPT_11AC\t\t\t0xfa0\n#define\tODM_REG_CLM_RESULT_11AC\t\t\t0xfa4\n#define\tODM_REG_NHM_CNT_11AC\t\t\t0xfa8\n#define ODM_REG_NHM_DUR_READY_11AC\t\t0xfb4\n\n#define\tODM_REG_NHM_CNT7_TO_CNT4_11AC\t\t0xfac\n#define\tODM_REG_NHM_CNT11_TO_CNT8_11AC\t\t0xfb0\n/* PAGE 18 */\n#define\tODM_REG_IGI_C_11AC\t\t\t0x1850\n/* PAGE 1A */\n#define\tODM_REG_IGI_D_11AC\t\t\t0x1A50\n\n/* PAGE 1D */\n#define\tODM_REG_IGI_11AC3\t\t\t0x1D70\n\n/* @2 MAC REG LIST */\n#define\tODM_REG_RESP_TX_11AC\t\t\t0x6D8\n\n\n\n/* @DIG Related */\n#define\tODM_BIT_IGI_11AC\t\t\t0x0000007F\n#define\tODM_BIT_IGI_B_11AC3\t\t\t0x00007F00\n#define\tODM_BIT_IGI_C_11AC3\t\t\t0x007F0000\n#define\tODM_BIT_IGI_D_11AC3\t\t\t0x7F000000\n#define\tODM_BIT_CCK_RPT_FORMAT_11AC\t\tBIT(16)\n#define\tODM_BIT_BB_RX_PATH_11AC\t\t\t0xF\n#define\tODM_BIT_BB_TX_PATH_11AC\t\t\t0xF\n#define\tODM_BIT_BB_ATC_11AC\t\t\tBIT(14)\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_regdefine11n.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __ODM_REGDEFINE11N_H__\n#define __ODM_REGDEFINE11N_H__\n\n/* @2 RF REG LIST */\n#define\tODM_REG_RF_MODE_11N\t\t\t0x00\n#define\tODM_REG_RF_0B_11N\t\t\t0x0B\n#define\tODM_REG_CHNBW_11N\t\t\t0x18\n#define\tODM_REG_T_METER_11N\t\t\t0x24\n#define\tODM_REG_RF_25_11N\t\t\t0x25\n#define\tODM_REG_RF_26_11N\t\t\t0x26\n#define\tODM_REG_RF_27_11N\t\t\t0x27\n#define\tODM_REG_RF_2B_11N\t\t\t0x2B\n#define\tODM_REG_RF_2C_11N\t\t\t0x2C\n#define\tODM_REG_RXRF_A3_11N\t\t\t0x3C\n#define\tODM_REG_T_METER_92D_11N\t\t\t0x42\n#define\tODM_REG_T_METER_88E_11N\t\t\t0x42\n\n\n\n/* @2 BB REG LIST\n * PAGE 8\n */\n#define\tODM_REG_BB_CTRL_11N\t\t\t0x800\n#define\tODM_REG_RF_PIN_11N\t\t\t0x804\n#define\tODM_REG_PSD_CTRL_11N\t\t\t0x808\n#define\tODM_REG_TX_ANT_CTRL_11N\t\t\t0x80C\n#define\tODM_REG_BB_PWR_SAV5_11N\t\t\t0x818\n#define\tODM_REG_CCK_RPT_FORMAT_11N\t\t0x824\n#define\tODM_REG_CCK_RPT_FORMAT_11N_B\t\t0x82C\n#define\tODM_REG_RX_DEFAULT_A_11N\t\t0x858\n#define\tODM_REG_RX_DEFAULT_B_11N\t\t0x85A\n#define\tODM_REG_BB_PWR_SAV3_11N\t\t\t0x85C\n#define\tODM_REG_ANTSEL_CTRL_11N\t\t\t0x860\n#define\tODM_REG_RX_ANT_CTRL_11N\t\t\t0x864\n#define\tODM_REG_PIN_CTRL_11N\t\t\t0x870\n#define\tODM_REG_BB_PWR_SAV1_11N\t\t\t0x874\n#define\tODM_REG_ANTSEL_PATH_11N\t\t\t0x878\n#define\tODM_REG_BB_3WIRE_11N\t\t\t0x88C\n#define\tODM_REG_SC_CNT_11N\t\t\t0x8C4\n#define\tODM_REG_PSD_DATA_11N\t\t\t0x8B4\n#define\tODM_REG_CCX_PERIOD_11N\t\t\t0x894\n#define\tODM_REG_NHM_TH9_TH10_11N\t\t0x890\n#define\tODM_REG_CLM_11N\t\t\t\t0x890\n#define\tODM_REG_NHM_TH3_TO_TH0_11N\t\t0x898\n#define\tODM_REG_NHM_TH7_TO_TH4_11N\t\t0x89c\n#define ODM_REG_NHM_TH8_11N\t\t\t0xe28\n#define\tODM_REG_CLM_READY_11N\t\t\t0x8b4\n#define\tODM_REG_CLM_RESULT_11N\t\t\t0x8d0\n#define\tODM_REG_NHM_CNT_11N\t\t\t0x8d8\n\n/* @For struct acs_info, Jeffery, 2014-12-26 */\n#define\tODM_REG_NHM_CNT7_TO_CNT4_11N\t\t0x8dc\n#define\tODM_REG_NHM_CNT9_TO_CNT8_11N\t\t0x8d0\n#define\tODM_REG_NHM_CNT10_TO_CNT11_11N\t\t0x8d4\n\n/* PAGE 9 */\n#define\tODM_REG_BB_CTRL_PAGE9_11N\t\t0x900\n#define\tODM_REG_DBG_RPT_11N\t\t\t0x908\n#define\tODM_REG_BB_TX_PATH_11N\t\t\t0x90c\n#define\tODM_REG_ANT_MAPPING1_11N\t\t0x914\n#define\tODM_REG_ANT_MAPPING2_11N\t\t0x918\n#define\tODM_REG_EDCCA_DOWN_OPT_11N\t\t0x948\n#define\tODM_REG_RX_DFIR_MOD_97F\t\t\t0x948\n#define\tODM_REG_SOML_97F\t\t\t0x998\n\n/* PAGE A */\n#define\tODM_REG_CCK_ANTDIV_PARA1_11N\t\t0xA00\n#define\tODM_REG_CCK_ANT_SEL_11N\t\t\t0xA04\n#define\tODM_REG_CCK_CCA_11N\t\t\t0xA0A\n#define\tODM_REG_CCK_ANTDIV_PARA2_11N\t\t0xA0C\n#define\tODM_REG_CCK_ANTDIV_PARA3_11N\t\t0xA10\n#define\tODM_REG_CCK_ANTDIV_PARA4_11N\t\t0xA14\n#define\tODM_REG_CCK_FILTER_PARA1_11N\t\t0xA22\n#define\tODM_REG_CCK_FILTER_PARA2_11N\t\t0xA23\n#define\tODM_REG_CCK_FILTER_PARA3_11N\t\t0xA24\n#define\tODM_REG_CCK_FILTER_PARA4_11N\t\t0xA25\n#define\tODM_REG_CCK_FILTER_PARA5_11N\t\t0xA26\n#define\tODM_REG_CCK_FILTER_PARA6_11N\t\t0xA27\n#define\tODM_REG_CCK_FILTER_PARA7_11N\t\t0xA28\n#define\tODM_REG_CCK_FILTER_PARA8_11N\t\t0xA29\n#define\tODM_REG_CCK_FA_RST_11N\t\t\t0xA2C\n#define\tODM_REG_CCK_FA_MSB_11N\t\t\t0xA58\n#define\tODM_REG_CCK_FA_LSB_11N\t\t\t0xA5C\n#define\tODM_REG_CCK_CCA_CNT_11N\t\t\t0xA60\n#define\tODM_REG_BB_PWR_SAV4_11N\t\t\t0xA74\n/* PAGE B */\n#define\tODM_REG_LNA_SWITCH_11N\t\t\t0xB2C\n#define\tODM_REG_PATH_SWITCH_11N\t\t\t0xB30\n#define\tODM_REG_RSSI_CTRL_11N\t\t\t0xB38\n#define\tODM_REG_CONFIG_ANTA_11N\t\t\t0xB68\n#define\tODM_REG_RSSI_BT_11N\t\t\t0xB9C\n#define\tODM_REG_RXCK_RFMOD\t\t\t0xBB0\n#define\tODM_REG_EDCCA_DCNF_97F\t\t\t0xBC0\n\n/* PAGE C */\n#define\tODM_REG_OFDM_FA_HOLDC_11N\t\t0xC00\n#define\tODM_REG_BB_RX_PATH_11N\t\t\t0xC04\n#define\tODM_REG_TRMUX_11N\t\t\t0xC08\n#define\tODM_REG_OFDM_FA_RSTC_11N\t\t0xC0C\n#define\tODM_REG_DOWNSAM_FACTOR_11N\t\t0xC10\n#define\tODM_REG_RXIQI_MATRIX_11N\t\t0xC14\n#define\tODM_REG_TXIQK_MATRIX_LSB1_11N\t\t0xC4C\n#define\tODM_REG_IGI_A_11N\t\t\t0xC50\n#define\tODM_REG_ANTDIV_PARA2_11N\t\t0xC54\n#define\tODM_REG_IGI_B_11N\t\t\t0xC58\n#define\tODM_REG_ANTDIV_PARA3_11N\t\t0xC5C\n#define   ODM_REG_L1SBD_PD_CH_11N\t\t0XC6C\n#define\tODM_REG_BB_PWR_SAV2_11N\t\t\t0xC70\n#define\tODM_REG_BB_AGC_SET_2_11N\t\t0xc74\n#define\tODM_REG_RX_OFF_11N\t\t\t0xC7C\n#define\tODM_REG_TXIQK_MATRIXA_11N\t\t0xC80\n#define\tODM_REG_TXIQK_MATRIXB_11N\t\t0xC88\n#define\tODM_REG_TXIQK_MATRIXA_LSB2_11N\t\t0xC94\n#define\tODM_REG_TXIQK_MATRIXB_LSB2_11N\t\t0xC9C\n#define\tODM_REG_RXIQK_MATRIX_LSB_11N\t\t0xCA0\n#define\tODM_REG_ANTDIV_PARA1_11N\t\t0xCA4\n#define\tODM_REG_SMALL_BANDWIDTH_11N\t\t0xCE4\n#define\tODM_REG_OFDM_FA_TYPE1_11N\t\t0xCF0\n/* PAGE D */\n#define\tODM_REG_OFDM_FA_RSTD_11N\t\t0xD00\n#define\tODM_REG_BB_RX_ANT_11N\t\t\t0xD04\n#define\tODM_REG_BB_ATC_11N\t\t\t0xD2C\n#define\tODM_REG_OFDM_FA_TYPE2_11N\t\t0xDA0\n#define\tODM_REG_OFDM_FA_TYPE3_11N\t\t0xDA4\n#define\tODM_REG_OFDM_FA_TYPE4_11N\t\t0xDA8\n#define\tODM_REG_RPT_11N\t\t\t\t0xDF4\n/* PAGE E */\n#define\tODM_REG_TXAGC_A_6_18_11N\t\t0xE00\n#define\tODM_REG_TXAGC_A_24_54_11N\t\t0xE04\n#define\tODM_REG_TXAGC_A_1_MCS32_11N\t\t0xE08\n#define\tODM_REG_TXAGC_A_MCS0_3_11N\t\t0xE10\n#define\tODM_REG_TXAGC_A_MCS4_7_11N\t\t0xE14\n#define\tODM_REG_TXAGC_A_MCS8_11_11N\t\t0xE18\n#define\tODM_REG_TXAGC_A_MCS12_15_11N\t\t0xE1C\n#define\tODM_REG_EDCCA_DCNF_11N\t\t\t0xE24\n#define\tODM_REG_TAP_UPD_97F\t\t\t0xE24\n#define\tODM_REG_FPGA0_IQK_11N\t\t\t0xE28\n#define\tODM_REG_PAGE_B1_97F\t\t\t0xE28\n#define\tODM_REG_TXIQK_TONE_A_11N\t\t0xE30\n#define\tODM_REG_RXIQK_TONE_A_11N\t\t0xE34\n#define\tODM_REG_TXIQK_PI_A_11N\t\t\t0xE38\n#define\tODM_REG_RXIQK_PI_A_11N\t\t\t0xE3C\n#define\tODM_REG_TXIQK_11N\t\t\t0xE40\n#define\tODM_REG_RXIQK_11N\t\t\t0xE44\n#define\tODM_REG_IQK_AGC_PTS_11N\t\t\t0xE48\n#define\tODM_REG_IQK_AGC_RSP_11N\t\t\t0xE4C\n#define\tODM_REG_BLUETOOTH_11N\t\t\t0xE6C\n#define\tODM_REG_RX_WAIT_CCA_11N\t\t\t0xE70\n#define\tODM_REG_TX_CCK_RFON_11N\t\t\t0xE74\n#define\tODM_REG_TX_CCK_BBON_11N\t\t\t0xE78\n#define\tODM_REG_OFDM_RFON_11N\t\t\t0xE7C\n#define\tODM_REG_OFDM_BBON_11N\t\t\t0xE80\n#define\tODM_REG_TX2RX_11N\t\t\t0xE84\n#define\tODM_REG_TX2TX_11N\t\t\t0xE88\n#define\tODM_REG_RX_CCK_11N\t\t\t0xE8C\n#define\tODM_REG_RX_OFDM_11N\t\t\t0xED0\n#define\tODM_REG_RX_WAIT_RIFS_11N\t\t0xED4\n#define\tODM_REG_RX2RX_11N\t\t\t0xED8\n#define\tODM_REG_STANDBY_11N\t\t\t0xEDC\n#define\tODM_REG_SLEEP_11N\t\t\t0xEE0\n#define\tODM_REG_PMPD_ANAEN_11N\t\t\t0xEEC\n/* PAGE F */\n#define\tODM_REG_PAGE_F_RST_11N\t\t\t0xF14\n#define\tODM_REG_IGI_C_11N\t\t\t0xF84\n#define\tODM_REG_IGI_D_11N\t\t\t0xF88\n#define\tODM_REG_CCK_CRC32_ERROR_CNT_11N\t\t0xF84\n#define\tODM_REG_CCK_CRC32_OK_CNT_11N\t\t0xF88\n#define\tODM_REG_HT_CRC32_CNT_11N\t\t0xF90\n#define\tODM_REG_OFDM_CRC32_CNT_11N\t\t0xF94\n#define\tODM_REG_HT_CRC32_CNT_11N_AGG\t\t0xFB8\n\n/* @2 MAC REG LIST */\n#define\tODM_REG_BB_RST_11N\t\t\t0x02\n#define\tODM_REG_ANTSEL_PIN_11N\t\t\t0x4C\n#define\tODM_REG_EARLY_MODE_11N\t\t\t0x4D0\n#define\tODM_REG_RSSI_MONITOR_11N\t\t0x4FE\n#define\tODM_REG_EDCA_VO_11N\t\t\t0x500\n#define\tODM_REG_EDCA_VI_11N\t\t\t0x504\n#define\tODM_REG_EDCA_BE_11N\t\t\t0x508\n#define\tODM_REG_EDCA_BK_11N\t\t\t0x50C\n#define\tODM_REG_TXPAUSE_11N\t\t\t0x522\n#define\tODM_REG_RESP_TX_11N\t\t\t0x6D8\n#define\tODM_REG_ANT_TRAIN_PARA1_11N\t\t0x7b0\n#define\tODM_REG_ANT_TRAIN_PARA2_11N\t\t0x7b4\n\n\n/* @DIG Related */\n#define\tODM_BIT_IGI_11N\t\t\t\t0x0000007F\n#define\tODM_BIT_CCK_RPT_FORMAT_11N\t\tBIT(9)\n#define\tODM_BIT_BB_RX_PATH_11N\t\t\t0xF\n#define\tODM_BIT_BB_TX_PATH_11N\t\t\t0xF\n#define\tODM_BIT_BB_ATC_11N\t\t\tBIT(11)\n#endif\n\n"
  },
  {
    "path": "hal/phydm/phydm_regtable.h",
    "content": "#define R_0x0 0x0\n#define R_0x00 0x00\n#define R_0x0106 0x0106\n#define R_0x0140 0x0140\n#define R_0x0144 0x0144\n#define R_0x0148 0x0148\n#define R_0x040 0x040\n#define R_0x10 0x10\n#define R_0x100 0x100\n#define R_0x1038 0x1038\n#define R_0x103c 0x103c\n#define R_0x1040 0x1040\n#define R_0x1048 0x1048\n#define R_0x1080 0x1080\n#define R_0x14c0 0x14c0\n#define R_0x14c4 0x14c4\n#define R_0x14c8 0x14c8\n#define R_0x14cc 0x14cc\n#define R_0x1518 0x1518\n#define R_0x1684 0x1684\n#define R_0x1688 0x1688\n#define R_0x168c 0x168c\n#define R_0x1700 0x1700\n#define R_0x1704 0x1704\n#define R_0x1800 0x1800\n#define R_0x1804 0x1804\n#define R_0x1808 0x1808\n#define R_0x180c 0x180c\n#define R_0x1810 0x1810\n#define R_0x1814 0x1814\n#define R_0x1818 0x1818\n#define R_0x181c 0x181c\n#define R_0x1830 0x1830\n#define R_0x1834 0x1834\n#define R_0x1838 0x1838\n#define R_0x183c 0x183c\n#define R_0x1840 0x1840\n#define R_0x1844 0x1844\n#define R_0x1848 0x1848\n#define R_0x1860 0x1860\n#define R_0x1864 0x1864\n#define R_0x186c 0x186c\n#define R_0x1870 0x1870\n#define R_0x1880 0x1880\n#define R_0x1884 0x1884\n#define R_0x188c 0x188c\n#define R_0x1894 0x1894\n#define R_0x189c 0x189c\n#define R_0x18a0 0x18a0\n#define R_0x18a4 0x18a4\n#define R_0x18a8 0x18a8\n#define R_0x18ac 0x18ac\n#define R_0x18e0 0x18e0\n#define R_0x18e8 0x18e8\n#define R_0x18ec 0x18ec\n#define R_0x18f0 0x18f0\n#define R_0x18f8 0x18f8\n#define R_0x18fc 0x18fc\n#define R_0x1900 0x1900\n#define R_0x1904 0x1904\n#define R_0x1908 0x1908\n#define R_0x1910 0x1910\n#define R_0x1918 0x1918\n#define R_0x191c 0x191c\n#define R_0x1928 0x1928\n#define R_0x1940 0x1940\n#define R_0x1944 0x1944\n#define R_0x1950 0x1950\n#define R_0x1954 0x1954\n#define R_0x195c 0x195c\n#define R_0x1970 0x1970\n#define R_0x1984 0x1984\n#define R_0x1988 0x1988\n#define R_0x198c 0x198c\n#define R_0x1990 0x1990\n#define R_0x1991 0x1991\n#define R_0x1998 0x1998\n#define R_0x19a8 0x19a8\n#define R_0x19b8 0x19b8\n#define R_0x19d4 0x19d4\n#define R_0x19d8 0x19d8\n#define R_0x19e0 0x19e0\n#define R_0x19f0 0x19f0\n#define R_0x19f8 0x19f8\n#define R_0x1a00 0x1a00\n#define R_0x1a04 0x1a04\n#define R_0x1a14 0x1a14\n#define R_0x1a20 0x1a20\n#define R_0x1a24 0x1a24\n#define R_0x1a28 0x1a28\n#define R_0x1a2c 0x1a2c\n#define R_0x1a5c 0x1a5c\n#define R_0x1a70 0x1a70\n#define R_0x1a74 0x1a74\n#define R_0x1a80 0x1a80\n#define R_0x1a84 0x1a84\n#define R_0x1a8c 0x1a8c\n#define R_0x1a94 0x1a94\n#define R_0x1a98 0x1a98\n#define R_0x1a9c 0x1a9c\n#define R_0x1aa0 0x1aa0\n#define R_0x1aa8 0x1aa8\n#define R_0x1aac 0x1aac\n#define R_0x1ab0 0x1ab0\n#define R_0x1abc 0x1abc\n#define R_0x1ac0 0x1ac0\n#define R_0x1ac8 0x1ac8\n#define R_0x1acc 0x1acc\n#define R_0x1ad0 0x1ad0\n#define R_0x1ad4 0x1ad4\n#define R_0x1ae8 0x1ae8\n#define R_0x1aec 0x1aec\n#define R_0x1b00 0x1b00\n#define R_0x1b04 0x1b04\n#define R_0x1b08 0x1b08\n#define R_0x1b0c 0x1b0c\n#define R_0x1b10 0x1b10\n#define R_0x1b14 0x1b14\n#define R_0x1b18 0x1b18\n#define R_0x1b1c 0x1b1c\n#define R_0x1b20 0x1b20\n#define R_0x1b23 0x1b23\n#define R_0x1b24 0x1b24\n#define R_0x1b28 0x1b28\n#define R_0x1b2c 0x1b2c\n#define R_0x1b30 0x1b30\n#define R_0x1b34 0x1b34\n#define R_0x1b38 0x1b38\n#define R_0x1b3c 0x1b3c\n#define R_0x1b40 0x1b40\n#define R_0x1b44 0x1b44\n#define R_0x1b48 0x1b48\n#define R_0x1b4c 0x1b4c\n#define R_0x1b50 0x1b50\n#define R_0x1b54 0x1b54\n#define R_0x1b58 0x1b58\n#define R_0x1b5c 0x1b5c\n#define R_0x1b60 0x1b60\n#define R_0x1b64 0x1b64\n#define R_0x1b67 0x1b67\n#define R_0x1b68 0x1b68\n#define R_0x1b6c 0x1b6c\n#define R_0x1b70 0x1b70\n#define R_0x1b74 0x1b74\n#define R_0x1b78 0x1b78\n#define R_0x1b7c 0x1b7c\n#define R_0x1b80 0x1b80\n#define R_0x1b83 0x1b83\n#define R_0x1b84 0x1b84\n#define R_0x1b88 0x1b88\n#define R_0x1b8c 0x1b8c\n#define R_0x1b90 0x1b90\n#define R_0x1b92 0x1b92\n#define R_0x1b94 0x1b94\n#define R_0x1b97 0x1b97\n#define R_0x1b98 0x1b98\n#define R_0x1b9c 0x1b9c\n#define R_0x1ba0 0x1ba0\n#define R_0x1ba4 0x1ba4\n#define R_0x1ba8 0x1ba8\n#define R_0x1bac 0x1bac\n#define R_0x1bb0 0x1bb0\n#define R_0x1bb4 0x1bb4\n#define R_0x1bb8 0x1bb8\n#define R_0x1bbc 0x1bbc\n#define R_0x1bc0 0x1bc0\n#define R_0x1bc8 0x1bc8\n#define R_0x1bca 0x1bca\n#define R_0x1bcb 0x1bcb\n#define R_0x1bcc 0x1bcc\n#define R_0x1bce 0x1bce\n#define R_0x1bd0 0x1bd0\n#define R_0x1bd4 0x1bd4\n#define R_0x1bd6 0x1bd6\n#define R_0x1bd8 0x1bd8\n#define R_0x1bdc 0x1bdc\n#define R_0x1be4 0x1be4\n#define R_0x1be8 0x1be8\n#define R_0x1beb 0x1beb\n#define R_0x1bec 0x1bec\n#define R_0x1bef 0x1bef\n#define R_0x1bf0 0x1bf0\n#define R_0x1bf4 0x1bf4\n#define R_0x1bf8 0x1bf8\n#define R_0x1bfc 0x1bfc\n#define R_0x1c 0x1c\n#define R_0x1c20 0x1c20\n#define R_0x1c24 0x1c24\n#define R_0x1c28 0x1c28\n#define R_0x1c2c 0x1c2c\n#define R_0x1c30 0x1c30\n#define R_0x1c34 0x1c34\n#define R_0x1c38 0x1c38\n#define R_0x1c3c 0x1c3c\n#define R_0x1c64 0x1c64\n#define R_0x1c68 0x1c68\n#define R_0x1c74 0x1c74\n#define R_0x1c78 0x1c78\n#define R_0x1c7c 0x1c7c\n#define R_0x1c80 0x1c80\n#define R_0x1c90 0x1c90\n#define R_0x1c94 0x1c94\n#define R_0x1c98 0x1c98\n#define R_0x1c9c 0x1c9c\n#define R_0x1ca0 0x1ca0\n#define R_0x1ca4 0x1ca4\n#define R_0x1cb0 0x1cb0\n#define R_0x1cb8 0x1cb8\n#define R_0x1cc0 0x1cc0\n#define R_0x1cd0 0x1cd0\n#define R_0x1ce4 0x1ce4\n#define R_0x1ce8 0x1ce8\n#define R_0x1cec 0x1cec\n#define R_0x1cf0 0x1cf0\n#define R_0x1cf4 0x1cf4\n#define R_0x1cf8 0x1cf8\n#define R_0x1d04 0x1d04\n#define R_0x1d08 0x1d08\n#define R_0x1d0c 0x1d0c\n#define R_0x1d10 0x1d10\n#define R_0x1d2c 0x1d2c\n#define R_0x1d30 0x1d30\n#define R_0x1d3c 0x1d3c\n#define R_0x1d44 0x1d44\n#define R_0x1d48 0x1d48\n#define R_0x1d58 0x1d58\n#define R_0x1d60 0x1d60\n#define R_0x1d6c 0x1d6c\n#define R_0x1d70 0x1d70\n#define R_0x1d90 0x1d90\n#define R_0x1d94 0x1d94\n#define R_0x1d9c 0x1d9c\n#define R_0x1da4 0x1da4\n#define R_0x1da8 0x1da8\n#define R_0x1e14 0x1e14\n#define R_0x1e18 0x1e18\n#define R_0x1e1c 0x1e1c\n#define R_0x1e24 0x1e24\n#define R_0x1e28 0x1e28\n#define R_0x1e2c 0x1e2c\n#define R_0x1e28 0x1e28\n#define R_0x1e30 0x1e30\n#define R_0x1e40 0x1e40\n#define R_0x1e44 0x1e44\n#define R_0x1e48 0x1e48\n#define R_0x1e5c 0x1e5c\n#define R_0x1e60 0x1e60\n#define R_0x1e64 0x1e64\n#define R_0x1e68 0x1e68\n#define R_0x1e6c 0x1e6c\n#define R_0x1e70 0x1e70\n#define R_0x1e7c 0x1e7c\n#define R_0x1e84 0x1e84\n#define R_0x1e88 0x1e88\n#define R_0x1e8c 0x1e8c\n#define R_0x1ea4 0x1ea4\n#define R_0x1eb4 0x1eb4\n#define R_0x1ee8 0x1ee8\n#define R_0x1eec 0x1eec\n#define R_0x1ef0 0x1ef0\n#define R_0x1ef4 0x1ef4\n#define R_0x1efc 0x1efc\n#define R_0x24 0x24\n#define R_0x28 0x28\n#define R_0x2c 0x2c\n#define R_0x28a4 0x28a4\n#define R_0x2c04 0x2c04\n#define R_0x2c08 0x2c08\n#define R_0x2c0c 0x2c0c\n#define R_0x2c10 0x2c10\n#define R_0x2c14 0x2c14\n#define R_0x2c20 0x2c20\n#define R_0x2c2c 0x2c2c\n#define R_0x2c30 0x2c30\n#define R_0x2c34 0x2c34\n#define R_0x2d00 0x2d00\n#define R_0x2d04 0x2d04\n#define R_0x2d08 0x2d08\n#define R_0x2d0c 0x2d0c\n#define R_0x2d10 0x2d10\n#define R_0x2d20 0x2d20\n#define R_0x2d38 0x2d38\n#define R_0x2d40 0x2d40\n#define R_0x2d44 0x2d44\n#define R_0x2d48 0x2d48\n#define R_0x2d4c 0x2d4c\n#define R_0x2d88 0x2d88\n#define R_0x2d90 0x2d90\n#define R_0x2d9c 0x2d9c\n#define R_0x2db4 0x2db4\n#define R_0x2db8 0x2db8\n#define R_0x2dbc 0x2dbc\n#define R_0x2de0 0x2de0\n#define R_0x2de4 0x2de4\n#define R_0x2de8 0x2de8\n#define R_0x2e00 0x2e00\n#define R_0x2e20 0x2e20\n#define R_0x300 0x300\n#define R_0x38 0x38\n#define R_0x3a00 0x3a00\n#define R_0x3a04 0x3a04\n#define R_0x3a08 0x3a08\n#define R_0x3a0c 0x3a0c\n#define R_0x3a10 0x3a10\n#define R_0x3a14 0x3a14\n#define R_0x3a18 0x3a18\n#define R_0x3a1c 0x3a1c\n#define R_0x3a20 0x3a20\n#define R_0x3a24 0x3a24\n#define R_0x3a28 0x3a28\n#define R_0x3a2c 0x3a2c\n#define R_0x3a30 0x3a30\n#define R_0x3a34 0x3a34\n#define R_0x3a38 0x3a38\n#define R_0x3a3c 0x3a3c\n#define R_0x3a40 0x3a40\n#define R_0x3a44 0x3a44\n#define R_0x3a48 0x3a48\n#define R_0x3a4c 0x3a4c\n#define R_0x3a50 0x3a50               \n#define R_0x3a54 0x3a54\n#define R_0x3a58 0x3a58\n#define R_0x3a5c 0x3a5c\n#define R_0x3a60 0x3a60\n#define R_0x3a64 0x3a64\n#define R_0x3a68 0x3a68\n#define R_0x3a6c 0x3a6c\n#define R_0x3a70 0x3a70\n#define R_0x3a74 0x3a74\n#define R_0x3a78 0x3a78\n#define R_0x3a7c 0x3a7c\n#define R_0x3a80 0x3a80\n#define R_0x3a84 0x3a84\n#define R_0x3a88 0x3a88\n#define R_0x3a8c 0x3a8c\n#define R_0x3a90 0x3a90\n#define R_0x3a94 0x3a94\n#define R_0x3a98 0x3a98\n#define R_0x3a9c 0x3a9c\n#define R_0x3aa0 0x3aa0\n#define R_0x3aa4 0x3aa4\n#define R_0x3c00 0x3c00\n#define R_0x40 0x40\n#define R_0x4000 0x4000\n#define R_0x4008 0x4008\n#define R_0x4018 0x4018\n#define R_0x401c 0x401c\n#define R_0x4028 0x4028\n#define R_0x4040 0x4040\n#define R_0x4044 0x4044\n#define R_0x4100 0x4100\n#define R_0x4104 0x4104\n#define R_0x4108 0x4108\n#define R_0x410c 0x410c\n#define R_0x4110 0x4110\n#define R_0x4114 0x4114\n#define R_0x4118 0x4118\n#define R_0x411c 0x411c\n#define R_0x4130 0x4130\n#define R_0x4134 0x4134\n#define R_0x4138 0x4138\n#define R_0x413c 0x413c\n#define R_0x4140 0x4140\n#define R_0x4144 0x4144\n#define R_0x4148 0x4148\n#define R_0x4160 0x4160\n#define R_0x4164 0x4164\n#define R_0x416c 0x416c\n#define R_0x4180 0x4180\n#define R_0x419c 0x419c\n#define R_0x41a0 0x41a0\n#define R_0x41a4 0x41a4\n#define R_0x41a8 0x41a8\n#define R_0x41ac 0x41ac\n#define R_0x41e0 0x41e0\n#define R_0x41e8 0x41e8\n#define R_0x41ec 0x41ec\n#define R_0x41f0 0x41f0\n#define R_0x41f8 0x41f8\n#define R_0x41fc 0x41fc\n#define R_0x42 0x42\n#define R_0x430 0x430\n#define R_0x434 0x434\n#define R_0x44 0x44\n#define R_0x440 0x440\n#define R_0x444 0x444\n#define R_0x448 0x448\n#define R_0x450 0x450\n#define R_0x454 0x454\n#define R_0x49c 0x49c\n#define R_0x4a0 0x4a0\n#define R_0x4a4 0x4a4\n#define R_0x4a8 0x4a8\n#define R_0x4c 0x4c\n#define R_0x4c8 0x4c8\n#define R_0x4cc 0x4cc\n#define R_0x45a4 0x45a4\n#define R_0x4c00 0x4c00\n#define R_0x5000 0x5000\n#define R_0x5008 0x5008\n#define R_0x5018 0x5018\n#define R_0x501c 0x501c\n#define R_0x5028 0x5028\n#define R_0x5040 0x5040\n#define R_0x5044 0x5044\n#define R_0x5100 0x5100\n#define R_0x5108 0x5108\n#define R_0x5118 0x5118\n#define R_0x511c 0x511c\n#define R_0x5128 0x5128\n#define R_0x5140 0x5140\n#define R_0x5144 0x5144\n#define R_0x520 0x520\n#define R_0x5200 0x5200\n#define R_0x520c 0x520c\n#define R_0x522 0x522\n#define R_0x524 0x524\n#define R_0x5230 0x5230\n#define R_0x5234 0x5234\n#define R_0x5238 0x5238\n#define R_0x523c 0x523c\n#define R_0x5240 0x5240\n#define R_0x5244 0x5244\n#define R_0x5248 0x5248\n#define R_0x526c 0x526c\n#define R_0x52a0 0x52a0\n#define R_0x52a4 0x52a4\n#define R_0x52ac 0x52ac\n#define R_0x5300 0x5300\n#define R_0x530c 0x530c\n#define R_0x5330 0x5330\n#define R_0x5334 0x5334\n#define R_0x5338 0x5338\n#define R_0x533c 0x533c\n#define R_0x5340 0x5340\n#define R_0x5344 0x5344\n#define R_0x5348 0x5348\n#define R_0x536c 0x536c\n#define R_0x53a0 0x53a0\n#define R_0x53a4 0x53a4\n#define R_0x53ac 0x53ac\n#define R_0x550 0x550\n#define R_0x551 0x551\n#define R_0x568 0x568\n#define R_0x588 0x588\n#define R_0x60 0x60\n#define R_0x604 0x604\n#define R_0x608 0x608\n#define R_0x60f 0x60f\n#define R_0x64 0x64\n#define R_0x66 0x66\n#define R_0x660 0x660\n#define R_0x668 0x668\n#define R_0x688 0x688\n#define R_0x6a0 0x6a0\n#define R_0x6d8 0x6d8\n#define R_0x6dc 0x6dc\n#define R_0x70 0x70\n#define R_0x74 0x74\n#define R_0x700 0x700\n#define R_0x71c 0x71c\n#define R_0x72c 0x72c\n#define R_0x764 0x764\n#define R_0x7b0 0x7b0\n#define R_0x7b4 0x7b4\n#define R_0x7c0 0x7c0\n#define R_0x7c4 0x7c4\n#define R_0x7c8 0x7c8\n#define R_0x7cc 0x7cc\n#define R_0x7f0 0x7f0\n#define R_0x7f4 0x7f4\n#define R_0x7f8 0x7f8\n#define R_0x7fc 0x7fc\n#define R_0x800 0x800\n#define R_0x8000 0x8000\n#define R_0x804 0x804\n#define R_0x808 0x808\n#define R_0x80c 0x80c\n#define R_0x810 0x810\n#define R_0x814 0x814\n#define R_0x818 0x818\n#define R_0x81c 0x81c\n#define R_0x820 0x820\n#define R_0x824 0x824\n#define R_0x828 0x828\n#define R_0x82c 0x82c\n#define R_0x830 0x830\n#define R_0x834 0x834\n#define R_0x838 0x838\n#define R_0x83c 0x83c\n#define R_0x840 0x840\n#define R_0x844 0x840\n#define R_0x848 0x848\n#define R_0x84c 0x84c\n#define R_0x850 0x850\n#define R_0x854 0x854\n#define R_0x858 0x858\n#define R_0x85c 0x85c\n#define R_0x860 0x860\n#define R_0x864 0x864\n#define R_0x868 0x868\n#define R_0x86c 0x86c\n#define R_0x870 0x870\n#define R_0x874 0x874\n#define R_0x878 0x878\n#define R_0x87c 0x87c\n#define R_0x880 0x880\n#define R_0x884 0x884\n#define R_0x888 0x888\n#define R_0x88c 0x88c\n#define R_0x890 0x890\n#define R_0x894 0x894\n#define R_0x898 0x898\n#define R_0x89c 0x89c\n#define R_0x8a0 0x8a0\n#define R_0x8a4 0x8a4\n#define R_0x8ac 0x8ac\n#define R_0x8b4 0x8b4\n#define R_0x8b8 0x8b8\n#define R_0x8c0 0x8c0\n#define R_0x8c4 0x8c4\n#define R_0x8c8 0x8c8\n#define R_0x8cc 0x8cc\n#define R_0x8d0 0x8d0\n#define R_0x8d4 0x8d4\n#define R_0x8d8 0x8d8\n#define R_0x8dc 0x8dc\n#define R_0x8f0 0x8f0\n#define R_0x8f8 0x8f8\n#define R_0x8fc 0x8fc\n#define R_0x900 0x900\n#define R_0x908 0x908\n#define R_0x90c 0x90c\n#define R_0x910 0x910\n#define R_0x914 0x914\n#define R_0x918 0x918\n#define R_0x91c 0x91c\n#define R_0x920 0x920\n#define R_0x924 0x924\n#define R_0x92c 0x92c\n#define R_0x930 0x930\n#define R_0x934 0x934\n#define R_0x938 0x938\n#define R_0x93c 0x93c\n#define R_0x940 0x940\n#define R_0x944 0x944\n#define R_0x948 0x948\n#define R_0x94c 0x94c\n#define R_0x950 0x950\n#define R_0x954 0x954\n#define R_0x958 0x958\n#define R_0x95c 0x95c\n#define R_0x960 0x960\n#define R_0x964 0x964\n#define R_0x968 0x968\n#define R_0x970 0x970\n#define R_0x974 0x974\n#define R_0x978 0x978\n#define R_0x97c 0x97c\n#define R_0x98c 0x98c\n#define R_0x990 0x990\n#define R_0x994 0x994\n#define R_0x998 0x998\n#define R_0x99c 0x99c\n#define R_0x9a0 0x9a0\n#define R_0x9a4 0x9a4\n#define R_0x9ac 0x9ac\n#define R_0x9b0 0x9b0\n#define R_0x9b4 0x9b4\n#define R_0x9b8 0x9b8\n#define R_0x9cc 0x9cc\n#define R_0x9d0 0x9d0\n#define R_0x9e4 0x9e4\n#define R_0x9e8 0x9e8\n#define R_0x9f0 0x9f0\n#define R_0xa0 0xa0\n#define R_0xa00 0xa00\n#define R_0xa04 0xa04\n#define R_0xa08 0xa08\n#define R_0xa0a 0xa0a\n#define R_0xa0c 0xa0c\n#define R_0xa10 0xa10\n#define R_0xa14 0xa14\n#define R_0xa20 0xa20\n#define R_0xa24 0xa24\n#define R_0xa28 0xa28\n#define R_0xa2c 0xa2c\n#define R_0xa40 0xa40\n#define R_0xa44 0xa44\n#define R_0xa48 0xa48\n#define R_0xa4c 0xa4c\n#define R_0xa50 0xa50\n#define R_0xa54 0xa54\n#define R_0xa58 0xa58\n#define R_0xa68 0xa68\n#define R_0xa6c 0xa6c\n#define R_0xa70 0xa70\n#define R_0xa74 0xa74\n#define R_0xa78 0xa78\n#define R_0xa8 0xa8\n#define R_0xa80 0xa80\n#define R_0xa84 0xa84\n#define R_0xa98 0xa98\n#define R_0xa9c 0xa9c\n#define R_0xaa8 0xaa8\n#define R_0xaac 0xaac\n#define R_0xab4 0xab4\n#define R_0xabc 0xabc\n#define R_0xac8 0xac8\n#define R_0xacc 0xacc\n#define R_0xad0 0xad0\n#define R_0xb0 0xb0\n#define R_0xb00 0xb00\n#define R_0xb04 0xb04\n#define R_0xb07 0xb07\n#define R_0xb08 0xb08\n#define R_0xb0c 0xb0c\n#define R_0xb10 0xb10\n#define R_0xb14 0xb14\n#define R_0xb18 0xb18\n#define R_0xb1c 0xb1c\n#define R_0xb20 0xb20\n#define R_0xb24 0xb24\n#define R_0xb28 0xb28\n#define R_0xb2b 0xb2b\n#define R_0xb2c 0xb2c\n#define R_0xb30 0xb30\n#define R_0xb34 0xb34\n#define R_0xb38 0xb38\n#define R_0xb3c 0xb3c\n#define R_0xb40 0xb40\n#define R_0xb44 0xb44\n#define R_0xb48 0xb48\n#define R_0xb54 0xb54\n#define R_0xb58 0xb58\n#define R_0xb60 0xb60\n#define R_0xb64 0xb64\n#define R_0xb68 0xb68\n#define R_0xb6a 0xb6a\n#define R_0xb6c 0xb6c\n#define R_0xb6e 0xb6e\n#define R_0xb70 0xb70\n#define R_0xb74 0xb74\n#define R_0xb77 0xb77\n#define R_0xb78 0xb78\n#define R_0xb7c 0xb7c\n#define R_0xb80 0xb80\n#define R_0xb84 0xb84\n#define R_0xb88 0xb88\n#define R_0xb8c 0xb8c\n#define R_0xb90 0xb90\n#define R_0xb94 0xb94\n#define R_0xb98 0xb98\n#define R_0xb9b 0xb9b\n#define R_0xb9c 0xb9c\n#define R_0xba0 0xba0\n#define R_0xba4 0xba4\n#define R_0xba8 0xba8\n#define R_0xbac 0xbac\n#define R_0xbad 0xbad\n#define R_0xbc0 0xbc0\n#define R_0xbc4 0xbc4\n#define R_0xbc8 0xbc8\n#define R_0xbcc 0xbcc\n#define R_0xbd8 0xbd8\n#define R_0xbdc 0xbdc\n#define R_0xbe0 0xbe0\n#define R_0xbe4 0xbe4\n#define R_0xbe8 0xbe8\n#define R_0xbec 0xbec\n#define R_0xbf0 0xbf0\n#define R_0xbf4 0xbf4\n#define R_0xbf8 0xbf8\n#define R_0xc00 0xc00\n#define R_0xc04 0xc04\n#define R_0xc08 0xc08\n#define R_0xc0c 0xc0c\n#define R_0xc10 0xc10\n#define R_0xc14 0xc14\n#define R_0xc18 0xc18\n#define R_0xc1c 0xc1c\n#define R_0xc20 0xc20\n#define R_0xc24 0xc24\n#define R_0xc30 0xc30\n#define R_0xc38 0xc38\n#define R_0xc3c 0xc3c\n#define R_0xc40 0xc40\n#define R_0xc44 0xc44\n#define R_0xc4c 0xc4c\n#define R_0xc50 0xc50\n#define R_0xc54 0xc54\n#define R_0xc58 0xc58\n#define R_0xc5c 0xc5c\n#define R_0xc6c 0xc6c\n#define R_0xc70 0xc70\n#define R_0xc74 0xc74\n#define R_0xc78 0xc78\n#define R_0xc7c 0xc7c\n#define R_0xc80 0xc80\n#define R_0xc84 0xc84\n#define R_0xc88 0xc88\n#define R_0xc8c 0xc8c\n#define R_0xc90 0xc90\n#define R_0xc94 0xc94\n#define R_0xc9c 0xc9c\n#define R_0xca0 0xca0\n#define R_0xca4 0xca4\n#define R_0xca8 0xca8\n#define R_0xcac 0xcac\n#define R_0xcb0 0xcb0\n#define R_0xcb4 0xcb4\n#define R_0xcb8 0xcb8\n#define R_0xcbc 0xcbc\n#define R_0xcbd 0xcbd\n#define R_0xcbe 0xcbe\n#define R_0xcc0 0xcc0\n#define R_0xcc4 0xcc4\n#define R_0xcc8 0xcc8\n#define R_0xccc 0xccc\n#define R_0xcd0 0xcd0\n#define R_0xcd4 0xcd4\n#define R_0xcd8 0xcd8\n#define R_0xce0 0xce0\n#define R_0xce4 0xce4\n#define R_0xce8 0xce8\n#define R_0xd00 0xd00\n#define R_0xd04 0xd04\n#define R_0xd08 0xd08\n#define R_0xd0c 0xd0c\n#define R_0xd10 0xd10\n#define R_0xd14 0xd14\n#define R_0xd2c 0xd2c\n#define R_0xd30 0xd30\n#define R_0xd40 0xd40\n#define R_0xd44 0xd44\n#define R_0xd48 0xd48\n#define R_0xd4c 0xd4c\n#define R_0xd50 0xd50\n#define R_0xd54 0xd54\n#define R_0xd5c 0xd5c\n#define R_0xd6c 0xd6c\n#define R_0xd7c 0xd7c\n#define R_0xd80 0xd80\n#define R_0xd84 0xd84\n#define R_0xd8c 0xd8c\n#define R_0xd90 0xd90\n#define R_0xd94 0xd94\n#define R_0xdac 0xdac\n#define R_0xdb0 0xdb0\n#define R_0xdb4 0xdb4\n#define R_0xdb8 0xdb8\n#define R_0xdbc 0xdbc\n#define R_0xdcc 0xdcc\n#define R_0xdd0 0xdd0\n#define R_0xdd4 0xdd4\n#define R_0xdd8 0xdd8\n#define R_0xde0 0xde0\n#define R_0xdec 0xdec\n#define R_0xdf4 0xdf4\n#define R_0xe00 0xe00\n#define R_0xe04 0xe04\n#define R_0xe08 0xe08\n#define R_0xe10 0xe10\n#define R_0xe14 0xe14\n#define R_0xe18 0xe18\n#define R_0xe1c 0xe1c\n#define R_0xe20 0xe20\n#define R_0xe24 0xe24\n#define R_0xe28 0xe28\n#define R_0xe30 0xe30\n#define R_0xe34 0xe34\n#define R_0xe38 0xe38\n#define R_0xe3c 0xe3c\n#define R_0xe40 0xe40\n#define R_0xe44 0xe44\n#define R_0xe48 0xe48\n#define R_0xe4c 0xe4c\n#define R_0xe50 0xe50\n#define R_0xe54 0xe54\n#define R_0xe5c 0xe5c\n#define R_0xe64 0xe64\n#define R_0xe6c 0xe6c\n#define R_0xe70 0xe70\n#define R_0xe74 0xe74\n#define R_0xe78 0xe78\n#define R_0xe7c 0xe7c\n#define R_0xe80 0xe80\n#define R_0xe84 0xe84\n#define R_0xe88 0xe88\n#define R_0xe8c 0xe8c\n#define R_0xe90 0xe90\n#define R_0xe94 0xe94\n#define R_0xe98 0xe98\n#define R_0xe9c 0xe9c\n#define R_0xea0 0xea0\n#define R_0xea4 0xea4\n#define R_0xea8 0xea8\n#define R_0xeac 0xeac\n#define R_0xeb0 0xeb0\n#define R_0xeb4 0xeb4\n#define R_0xeb8 0xeb8\n#define R_0xebc 0xebc\n#define R_0xec 0xec\n#define R_0xec0 0xec0\n#define R_0xec4 0xec4\n#define R_0xec8 0xec8\n#define R_0xecc 0xecc\n#define R_0xed0 0xed0\n#define R_0xed4 0xed4\n#define R_0xed8 0xed8\n#define R_0xedc 0xedc\n#define R_0xee0 0xee0\n#define R_0xee8 0xee8\n#define R_0xeec 0xeec\n#define R_0xf0 0xf0\n#define R_0xf00 0xf00\n#define R_0xf04 0xf04\n#define R_0xf08 0xf08\n#define R_0xf0c 0xf0c\n#define R_0xf10 0xf10\n#define R_0xf14 0xf14\n#define R_0xf20 0xf20\n#define R_0xf2c 0xf2c\n#define R_0xf30 0xf30\n#define R_0xf34 0xf34\n#define R_0xf4 0xf4\n#define R_0xf44 0xf44\n#define R_0xf48 0xf48\n#define R_0xf4c 0xf4c\n#define R_0xf50 0xf50\n#define R_0xf54 0xf54\n#define R_0xf58 0xf58\n#define R_0xf5c 0xf5c\n#define R_0xf70 0xf70\n#define R_0xf74 0xf74\n#define R_0xf80 0xf80\n#define R_0xf84 0xf84\n#define R_0xf87 0xf87\n#define R_0xf88 0xf88\n#define R_0xf8c 0xf8c\n#define R_0xf90 0xf90\n#define R_0xf94 0xf94\n#define R_0xf98 0xf98\n#define R_0xfa0 0xfa0\n#define R_0xfa4 0xfa4\n#define R_0xfa8 0xfa8\n#define R_0xfac 0xfac\n#define R_0xfb0 0xfb0\n#define R_0xfb4 0xfb4\n#define R_0xfb8 0xfb8\n#define R_0xfbc 0xfbc\n#define R_0xfc0 0xfc0\n#define R_0xfc4 0xfc4\n#define R_0xfc8 0xfc8\n#define R_0xfcc 0xfcc\n#define R_0xfd0 0xfd0\n#define R_0xff0 0xff0\n#define RF_0x0 0x0\n#define RF_0x00 0x00\n#define RF_0x08 0x08\n#define RF_0x0c 0x0c\n#define RF_0x0d 0x0d\n#define RF_0x1 0x1\n#define RF_0x18 0x18\n#define RF_0x19 0x19\n#define RF_0x1a 0x1a\n#define RF_0x1bf0 0x1bf0\n#define RF_0x2 0x2\n#define RF_0x3 0x3\n#define RF_0x30 0x30\n#define RF_0x31 0x31\n#define RF_0x32 0x32\n#define RF_0x33 0x33\n#define RF_0x35 0x35\n#define RF_0x3e 0x3e\n#define RF_0x3f 0x3f\n#define RF_0x4 0x4\n#define RF_0x42 0x42\n#define RF_0x43 0x43\n#define RF_0x51 0x51\n#define RF_0x52 0x52\n#define RF_0x54 0x54\n#define RF_0x55 0x55\n#define RF_0x56 0x56\n#define RF_0x58 0x58\n#define RF_0x5c 0x5c\n#define RF_0x61 0x61\n#define RF_0x63 0x63\n#define RF_0x64 0x64\n#define RF_0x65 0x65\n#define RF_0x66 0x66\n#define RF_0x67 0x67\n#define RF_0x6e 0x6e\n#define RF_0x6f 0x6f\n#define RF_0x75 0x75\n#define RF_0x76 0x76\n#define RF_0x78 0x78\n#define RF_0x7f 0x7f\n#define RF_0x8 0x8\n#define RF_0x80 0x80\n#define RF_0x81 0x81\n#define RF_0x82 0x82\n#define RF_0x83 0x83\n#define RF_0x85 0x85\n#define RF_0x86 0x86\n#define RF_0x87 0x87\n#define RF_0x8a 0x8a\n#define RF_0x8d 0x8d\n#define RF_0x8f 0x8f\n#define RF_0x93 0x93\n#define RF_0xa9 0xa9\n#define RF_0xae 0xae\n#define RF_0xb0 0xb0\n#define RF_0xb3 0xb3\n#define RF_0xb4 0xb4\n#define RF_0xb8 0xb8\n#define RF_0xbc 0xbc\n#define RF_0xbe 0xbe\n#define RF_0xc4 0xc4\n#define RF_0xc9 0xc9\n#define RF_0xca 0xca\n#define RF_0xcc 0xcc\n#define RF_0xd 0xd\n#define RF_0xdd 0xdd\n#define RF_0xde 0xde\n#define RF_0xdf 0xdf\n#define RF_0xed 0xed\n#define RF_0xee 0xee\n#define RF_0xef 0xef\n#define RF_0xf5 0xf5\n"
  },
  {
    "path": "hal/phydm/phydm_rssi_monitor.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*@************************************************************\n * include files\n ************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#ifdef PHYDM_SUPPORT_RSSI_MONITOR\n\nvoid phydm_rssi_monitor_h2c(void *dm_void, u8 macid)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra_t = &dm->dm_ra_table;\n\tstruct cmn_sta_info *sta = dm->phydm_sta_info[macid];\n\tstruct ra_sta_info *ra = NULL;\n\t#ifdef CONFIG_BEAMFORMING\n\tstruct bf_cmn_info *bf = NULL;\n\t#endif\n\tu8 h2c[H2C_MAX_LENGTH] = {0};\n\tu8 stbc_en, ldpc_en;\n\tu8 bf_en = 0;\n\tu8 is_rx, is_tx;\n\n\tif (is_sta_active(sta)) {\n\t\tra = &sta->ra_info;\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_RSSI_MNTR, \"[Warning] %s\\n\", __func__);\n\t\treturn;\n\t}\n\n\tPHYDM_DBG(dm, DBG_RSSI_MNTR, \"%s ======>\\n\", __func__);\n\tPHYDM_DBG(dm, DBG_RSSI_MNTR, \"MACID=%d\\n\", sta->mac_id);\n\n\tis_rx = (ra->txrx_state == RX_STATE) ? 1 : 0;\n\tis_tx = (ra->txrx_state == TX_STATE) ? 1 : 0;\n\tstbc_en = (sta->stbc_en) ? 1 : 0;\n\tldpc_en = (sta->ldpc_en) ? 1 : 0;\n\n\t#ifdef CONFIG_BEAMFORMING\n\tbf = &sta->bf_info;\n\n\tif ((bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMEE_ENABLE) ||\n\t    (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMEE_ENABLE))\n\t\tbf_en = 1;\n\t#endif\n\n\tPHYDM_DBG(dm, DBG_RSSI_MNTR, \"RA_th_ofst=(( %s%d ))\\n\",\n\t\t  ((ra_t->ra_ofst_direc) ? \"+\" : \"-\"), ra_t->ra_th_ofst);\n\n\th2c[0] = sta->mac_id;\n\th2c[1] = 0;\n\th2c[2] = sta->rssi_stat.rssi;\n\th2c[3] = is_rx | (stbc_en << 1) |\n\t\t     ((dm->noisy_decision & 0x1) << 2) | (bf_en << 6);\n\th2c[4] = (ra_t->ra_th_ofst & 0x7f) |\n\t\t     ((ra_t->ra_ofst_direc & 0x1) << 7);\n\th2c[5] = 0;\n\th2c[6] = 0;\n\n\tPHYDM_DBG(dm, DBG_RSSI_MNTR, \"PHYDM h2c[0x42]=0x%x %x %x %x %x %x %x\\n\",\n\t\t  h2c[6], h2c[5], h2c[4], h2c[3], h2c[2], h2c[1], h2c[0]);\n\n\t#if (RTL8188E_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8188E)\n\t\todm_ra_set_rssi_8188e(dm, sta->mac_id, sta->rssi_stat.rssi);\n\telse\n\t#endif\n\t{\n\t\todm_fill_h2c_cmd(dm, ODM_H2C_RSSI_REPORT, H2C_MAX_LENGTH, h2c);\n\t}\n}\n\nvoid phydm_calculate_rssi_min_max(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct cmn_sta_info *sta;\n\ts8 rssi_max_tmp = 0, rssi_min_tmp = 100;\n\tu8 i;\n\tu8 sta_cnt = 0;\n\n\tif (!dm->is_linked)\n\t\treturn;\n\n\tPHYDM_DBG(dm, DBG_RSSI_MNTR, \"%s ======>\\n\", __func__);\n\n\tfor (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {\n\t\tsta = dm->phydm_sta_info[i];\n\t\tif (is_sta_active(sta)) {\n\t\t\tsta_cnt++;\n\n\t\t\tif (sta->rssi_stat.rssi < rssi_min_tmp) {\n\t\t\t\trssi_min_tmp = sta->rssi_stat.rssi;\n\t\t\t\tdm->rssi_min_macid = i;\n\t\t\t}\n\n\t\t\tif (sta->rssi_stat.rssi > rssi_max_tmp) {\n\t\t\t\trssi_max_tmp = sta->rssi_stat.rssi;\n\t\t\t\tdm->rssi_max_macid = i;\n\t\t\t}\n\n\t\t\t/*@[Send RSSI to FW]*/\n\t\t\tif (!sta->ra_info.disable_ra)\n\t\t\t\tphydm_rssi_monitor_h2c(dm, i);\n\n\t\t\tif (sta_cnt == dm->number_linked_client)\n\t\t\t\tbreak;\n\t\t}\n\t}\n\tdm->pre_rssi_min = dm->rssi_min;\n\n\tdm->rssi_max = (u8)rssi_max_tmp;\n\tdm->rssi_min = (u8)rssi_min_tmp;\n}\n\nvoid phydm_rssi_monitor_check(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (!(dm->support_ability & ODM_BB_RSSI_MONITOR))\n\t\treturn;\n\n\t/*@for AP watchdog period = 1 sec*/\n\tif ((dm->phydm_sys_up_time % 2) == 1)\n\t\treturn;\n\n\tPHYDM_DBG(dm, DBG_RSSI_MNTR, \"%s ======>\\n\", __func__);\n\n\tphydm_calculate_rssi_min_max(dm);\n\n\tPHYDM_DBG(dm, DBG_RSSI_MNTR, \"RSSI {max, min} = {%d, %d}\\n\",\n\t\t  dm->rssi_max, dm->rssi_min);\n}\n\nvoid phydm_rssi_monitor_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct ra_table *ra_tab = &dm->dm_ra_table;\n\n\tra_tab->firstconnect = false;\n\tdm->pre_rssi_min = 0;\n\tdm->rssi_max = 0;\n\tdm->rssi_min = 0;\n}\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_rssi_monitor.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDM_RSSI_MONITOR_H__\n#define __PHYDM_RSSI_MONITOR_H__\n\n#define RSSI_MONITOR_VERSION \"2.0\"\n\n/* @1 ============================================================\n * 1  Definition\n * 1 ============================================================\n */\n\n/* @1 ============================================================\n * 1  structure\n * 1 ============================================================\n */\n\n/* @1 ============================================================\n * 1  enumeration\n * 1 ============================================================\n */\n\n/* @1 ============================================================\n * 1  function prototype\n * 1 ============================================================\n */\n\nvoid phydm_rssi_monitor_check(void *dm_void);\n\nvoid phydm_rssi_monitor_init(void *dm_void);\n\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_smt_ant.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/* ************************************************************\n * include files\n * ************************************************************ */\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n/*******************************************************\n * when antenna test utility is on or some testing need to disable antenna diversity\n * call this function to disable all ODM related mechanisms which will switch antenna.\n ******************************************************/\n#if (defined(CONFIG_SMART_ANTENNA))\n\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n#if (RTL8198F_SUPPORT == 1)\nvoid phydm_smt_ant_init_98f(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 val = 0;\n\n\t#if 0\n\todm_set_bb_reg(dm, R_0x1da4, 0x3c, 4); /*6.25*4 = 25ms*/\n\todm_set_bb_reg(dm, R_0x1da4, BIT(6), 1);\n\todm_set_bb_reg(dm, R_0x1da4, BIT(7), 1);\n\t#endif\n}\n#endif\n#endif\n\n#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))\nvoid phydm_cumitek_smt_ant_mapping_table_8822b(\n\tvoid *dm_void,\n\tu8 *table_path_a,\n\tu8 *table_path_b)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 path_a_0to3_idx = 0;\n\tu32 path_b_0to3_idx = 0;\n\tu32 path_a_4to7_idx = 0;\n\tu32 path_b_4to7_idx = 0;\n\n\tpath_a_0to3_idx = ((table_path_a[3] & 0xf) << 24) | ((table_path_a[2] & 0xf) << 16) | ((table_path_a[1] & 0xf) << 8) | (table_path_a[0] & 0xf);\n\n\tpath_b_0to3_idx = ((table_path_b[3] & 0xf) << 28) | ((table_path_b[2] & 0xf) << 20) | ((table_path_b[1] & 0xf) << 12) | ((table_path_b[0] & 0xf) << 4);\n\n\tpath_a_4to7_idx = ((table_path_a[7] & 0xf) << 24) | ((table_path_a[6] & 0xf) << 16) | ((table_path_a[5] & 0xf) << 8) | (table_path_a[4] & 0xf);\n\n\tpath_b_4to7_idx = ((table_path_b[7] & 0xf) << 28) | ((table_path_b[6] & 0xf) << 20) | ((table_path_b[5] & 0xf) << 12) | ((table_path_b[4] & 0xf) << 4);\n\n#if 0\n\t/*PHYDM_DBG(dm, DBG_SMT_ANT, \"mapping table{A, B} = {0x%x, 0x%x}\\n\", path_a_0to3_idx, path_b_0to3_idx);*/\n#endif\n\n\t/*pathA*/\n\todm_set_bb_reg(dm, R_0xca4, MASKDWORD, path_a_0to3_idx); /*@ant map 1*/\n\todm_set_bb_reg(dm, R_0xca8, MASKDWORD, path_a_4to7_idx); /*@ant map 2*/\n\n\t/*pathB*/\n\todm_set_bb_reg(dm, R_0xea4, MASKDWORD, path_b_0to3_idx); /*@ant map 1*/\n\todm_set_bb_reg(dm, R_0xea8, MASKDWORD, path_b_4to7_idx); /*@ant map 2*/\n}\n\nvoid phydm_cumitek_smt_ant_init_8822b(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant *smtant_table = &dm->smtant_table;\n\tstruct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;\n\tu32 value32;\n\n\tPHYDM_DBG(dm, DBG_SMT_ANT, \"[8822B Cumitek SmtAnt Int]\\n\");\n\n\t/*@========= MAC GPIO setting =================================*/\n\n\t/* Pin, pin_name, RFE_CTRL_NUM*/\n\n\t/* @A0, 55, 5G_TRSW, 3*/\n\t/* @A1, 52, 5G_TRSW, 0*/\n\t/* @A2, 25, 5G_TRSW, 8*/\n\n\t/* @B0, 16, 5G_TRSW, 4*/\n\t/* @B1, 13, 5G_TRSW, 11*/\n\t/* @B2, 24, 5G_TRSW, 9*/\n\n\t/*@for RFE_CTRL 8 & 9*/\n\todm_set_mac_reg(dm, R_0x4c, BIT(24) | BIT(23), 2);\n\todm_set_mac_reg(dm, R_0x44, BIT(27) | BIT(26), 0);\n\n\t/*@for RFE_CTRL 0*/\n\todm_set_mac_reg(dm, R_0x4c, BIT(25), 0);\n\todm_set_mac_reg(dm, R_0x64, BIT(29), 1);\n\n\t/*@for RFE_CTRL 2 & 3*/\n\todm_set_mac_reg(dm, R_0x4c, BIT(26), 0);\n\todm_set_mac_reg(dm, R_0x64, BIT(28), 1);\n\n\t/*@for RFE_CTRL 11*/\n\todm_set_mac_reg(dm, R_0x40, BIT(3), 1);\n\n\t/*@0x604[25]=1 : 2bit mode for pathA&B&C&D*/\n\t/*@0x604[25]=0 : 3bit mode for pathA&B*/\n\tsmtant_table->tx_desc_mode = 0;\n\todm_set_mac_reg(dm, R_0x604, BIT(25), (u32)smtant_table->tx_desc_mode);\n\n\t/*@========= BB RFE setting =================================*/\n#if 0\n\t/*path A*/\n\todm_set_bb_reg(dm, R_0x1990, BIT(3), 0);\t\t/*RFE_CTRL_3*/ /*A_0*/\n\todm_set_bb_reg(dm, R_0xcbc, BIT(3), 0);\t\t/*@inv*/\n\todm_set_bb_reg(dm, R_0xcb0, 0xf000, 8);\n\n\todm_set_bb_reg(dm, R_0x1990, BIT(0), 0);\t\t/*RFE_CTRL_0*/ /*A_1*/\n\todm_set_bb_reg(dm, R_0xcbc, BIT(0), 0);\t\t/*@inv*/\n\todm_set_bb_reg(dm, R_0xcb0, 0xf, 0x9);\n\n\todm_set_bb_reg(dm, R_0x1990, BIT(8), 0);\t\t/*RFE_CTRL_8*/ /*A_2*/\n\todm_set_bb_reg(dm, R_0xcbc, BIT(8), 0);\t\t/*@inv*/\n\todm_set_bb_reg(dm, R_0xcb4, 0xf, 0xa);\n\n\n\t/*path B*/\n\todm_set_bb_reg(dm, R_0x1990, BIT(4), 1);\t\t/*RFE_CTRL_4*/\t/*B_0*/\n\todm_set_bb_reg(dm, R_0xdbc, BIT(4), 0);\t\t/*@inv*/\n\todm_set_bb_reg(dm, R_0xdb0, 0xf0000, 0xb);\n\n\todm_set_bb_reg(dm, R_0x1990, BIT(11), 1);\t/*RFE_CTRL_11*/\t/*B_1*/\n\todm_set_bb_reg(dm, R_0xdbc, BIT(11), 0);\t\t/*@inv*/\n\todm_set_bb_reg(dm, R_0xdb4, 0xf000, 0xc);\n\n\todm_set_bb_reg(dm, R_0x1990, BIT(9), 1);\t\t/*RFE_CTRL_9*/\t/*B_2*/\n\todm_set_bb_reg(dm, R_0xdbc, BIT(9), 0);\t\t/*@inv*/\n\todm_set_bb_reg(dm, R_0xdb4, 0xf0, 0xd);\n#endif\n\t/*@========= BB SmtAnt setting =================================*/\n\todm_set_mac_reg(dm, R_0x6d8, BIT(22) | BIT(21), 2); /*resp tx by register*/\n\todm_set_mac_reg(dm, R_0x668, BIT(3), 1);\n\todm_set_bb_reg(dm, R_0x804, BIT(4), 0); /*@lathch antsel*/\n\todm_set_bb_reg(dm, R_0x818, 0xf00000, 0); /*@keep tx by rx*/\n\todm_set_bb_reg(dm, R_0x900, BIT(19), 0); /*@fast train*/\n\todm_set_bb_reg(dm, R_0x900, BIT(18), 1); /*@1: by TXDESC*/\n\n\t/*pathA*/\n\todm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x03020100); /*@ant map 1*/\n\todm_set_bb_reg(dm, R_0xca8, MASKDWORD, 0x07060504); /*@ant map 2*/\n\todm_set_bb_reg(dm, R_0xcac, BIT(9), 0); /*@keep antsel map by GNT_BT*/\n\n\t/*pathB*/\n\todm_set_bb_reg(dm, R_0xea4, MASKDWORD, 0x30201000); /*@ant map 1*/\n\todm_set_bb_reg(dm, R_0xea8, MASKDWORD, 0x70605040); /*@ant map 2*/\n\todm_set_bb_reg(dm, R_0xeac, BIT(9), 0); /*@keep antsel map by GNT_BT*/\n}\n\nvoid phydm_cumitek_smt_ant_init_8197f(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant *smtant_table = &dm->smtant_table;\n\tstruct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;\n\tu32 value32;\n\n\tPHYDM_DBG(dm, DBG_SMT_ANT, \"[8197F Cumitek SmtAnt Int]\\n\");\n\n\t/*@GPIO setting*/\n}\n\nvoid phydm_cumitek_smt_ant_init_8192f(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant *smtant_table = &dm->smtant_table;\n\tstruct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;\n\tu32 value32;\n\tPHYDM_DBG(dm, DBG_SMT_ANT, \"[8192F Cumitek SmtAnt Int]\\n\");\n\n\t/*@GPIO setting*/\n}\n\nvoid phydm_cumitek_smt_tx_ant_update(\n\tvoid *dm_void,\n\tu8 tx_ant_idx_path_a,\n\tu8 tx_ant_idx_path_b,\n\tu32 mac_id)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant *smtant_table = &dm->smtant_table;\n\tstruct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[Cumitek] Set TX-ANT[%d] = (( A:0x%x ,  B:0x%x ))\\n\", mac_id,\n\t\t  tx_ant_idx_path_a, tx_ant_idx_path_b);\n\n\t/*path-A*/\n\tcumi_smtant_table->tx_ant_idx[0][mac_id] = tx_ant_idx_path_a; /*@fill this value into TXDESC*/\n\n\t/*path-B*/\n\tcumi_smtant_table->tx_ant_idx[1][mac_id] = tx_ant_idx_path_b; /*@fill this value into TXDESC*/\n}\n\nvoid phydm_cumitek_smt_rx_default_ant_update(\n\tvoid *dm_void,\n\tu8 rx_ant_idx_path_a,\n\tu8 rx_ant_idx_path_b)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant *smtant_table = &dm->smtant_table;\n\tstruct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[Cumitek] Set RX-ANT = (( A:0x%x, B:0x%x ))\\n\",\n\t\t  rx_ant_idx_path_a, rx_ant_idx_path_b);\n\n\t/*path-A*/\n\tif (cumi_smtant_table->rx_default_ant_idx[0] != rx_ant_idx_path_a) {\n\t\t#if (RTL8822B_SUPPORT == 1)\n\t\tif (dm->support_ic_type == ODM_RTL8822B) {\n\t\t\todm_set_bb_reg(dm, R_0xc08, BIT(21) | BIT(20) | BIT(19), rx_ant_idx_path_a); /*@default RX antenna*/\n\t\t\todm_set_mac_reg(dm, R_0x6d8, BIT(2) | BIT(1) | BIT(0), rx_ant_idx_path_a); /*@default response TX antenna*/\n\t\t}\n\t\t#endif\n\n\t\t#if (RTL8197F_SUPPORT == 1)\n\t\tif (dm->support_ic_type == ODM_RTL8197F) {\n\t\t}\n\t\t#endif\n\n\t\t/*@jj add 20170822*/\n\t\t#if (RTL8192F_SUPPORT == 1)\n\t\tif (dm->support_ic_type == ODM_RTL8192F) {\n\t\t}\n\t\t#endif\n\t\tcumi_smtant_table->rx_default_ant_idx[0] = rx_ant_idx_path_a;\n\t}\n\n\t/*path-B*/\n\tif (cumi_smtant_table->rx_default_ant_idx[1] != rx_ant_idx_path_b) {\n\t\t#if (RTL8822B_SUPPORT == 1)\n\t\tif (dm->support_ic_type == ODM_RTL8822B) {\n\t\t\todm_set_bb_reg(dm, R_0xe08, BIT(21) | BIT(20) | BIT(19), rx_ant_idx_path_b); /*@default antenna*/\n\t\t\todm_set_mac_reg(dm, R_0x6d8, BIT(5) | BIT(4) | BIT(3), rx_ant_idx_path_b); /*@default response TX antenna*/\n\t\t}\n\t\t#endif\n\n\t\t#if (RTL8197F_SUPPORT == 1)\n\t\tif (dm->support_ic_type == ODM_RTL8197F) {\n\t\t}\n\t\t#endif\n\n\t\t/*@jj add 20170822*/\n\t\t#if (RTL8192F_SUPPORT == 1)\n\t\tif (dm->support_ic_type == ODM_RTL8192F) {\n\t\t}\n\t\t#endif\n\t\tcumi_smtant_table->rx_default_ant_idx[1] = rx_ant_idx_path_b;\n\t}\n}\n\nvoid phydm_cumitek_smt_ant_debug(\n\tvoid *dm_void,\n\tchar input[][16],\n\tu32 *_used,\n\tchar *output,\n\tu32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant *smtant_table = &dm->smtant_table;\n\tstruct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tchar help[] = \"-h\";\n\tu32 dm_value[10] = {0};\n\tu8 i;\n\n\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &dm_value[0]);\n\n\tif (strcmp(input[1], help) == 0) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{1} {PathA rx_ant_idx} {pathB rx_ant_idx}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{2} {PathA tx_ant_idx} {pathB tx_ant_idx} {macid}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{3} {PathA mapping table} {PathB mapping table}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"{4} {txdesc_mode 0:3bit, 1:2bit}\\n\");\n\n\t} else if (dm_value[0] == 1) { /*@fix rx_idle pattern*/\n\n\t\tPHYDM_SSCANF(input[2], DCMD_DECIMAL, &dm_value[1]);\n\t\tPHYDM_SSCANF(input[3], DCMD_DECIMAL, &dm_value[2]);\n\n\t\tphydm_cumitek_smt_rx_default_ant_update(dm, (u8)dm_value[1], (u8)dm_value[2]);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"RX Ant{A, B}={%d, %d}\\n\", dm_value[1], dm_value[2]);\n\n\t} else if (dm_value[0] == 2) { /*@fix tx pattern*/\n\n\t\tfor (i = 1; i < 4; i++) {\n\t\t\tif (input[i + 1])\n\t\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);\n\t\t}\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"STA[%d] TX Ant{A, B}={%d, %d}\\n\", dm_value[3],\n\t\t\t dm_value[1], dm_value[2]);\n\t\tphydm_cumitek_smt_tx_ant_update(dm, (u8)dm_value[1], (u8)dm_value[2], (u8)dm_value[3]);\n\n\t} else if (dm_value[0] == 3) {\n\t\tu8 table_path_a[8] = {0};\n\t\tu8 table_path_b[8] = {0};\n\n\t\tfor (i = 1; i < 4; i++) {\n\t\t\tif (input[i + 1])\n\t\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);\n\t\t}\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Set Path-AB mapping table={%d, %d}\\n\", dm_value[1],\n\t\t\t dm_value[2]);\n\n\t\tfor (i = 0; i < 8; i++) {\n\t\t\ttable_path_a[i] = (u8)((dm_value[1] >> (4 * i)) & 0xf);\n\t\t\ttable_path_b[i] = (u8)((dm_value[2] >> (4 * i)) & 0xf);\n\t\t}\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Ant_Table_A[7:0]={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x}\\n\",\n\t\t\t table_path_a[7], table_path_a[6], table_path_a[5],\n\t\t\t table_path_a[4], table_path_a[3], table_path_a[2],\n\t\t\t table_path_a[1], table_path_a[0]);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"Ant_Table_B[7:0]={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x}\\n\",\n\t\t\t table_path_b[7], table_path_b[6], table_path_b[5],\n\t\t\t table_path_b[4], table_path_b[3], table_path_b[2],\n\t\t\t table_path_b[1], table_path_b[0]);\n\n\t\tphydm_cumitek_smt_ant_mapping_table_8822b(dm, &table_path_a[0], &table_path_b[0]);\n\n\t} else if (dm_value[0] == 4) {\n\t\tsmtant_table->tx_desc_mode = (u8)dm_value[1];\n\t\todm_set_mac_reg(dm, R_0x604, BIT(25), (u32)smtant_table->tx_desc_mode);\n\t}\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\n#endif\n\n#if (defined(CONFIG_HL_SMART_ANTENNA))\n#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2\n\n#if (RTL8822B_SUPPORT == 1)\nvoid phydm_hl_smart_ant_type2_init_8822b(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tu8 j;\n\tu8 rfu_codeword_table_init_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] = {\n\t\t{1, 1}, /*@0*/\n\t\t{1, 2},\n\t\t{2, 1},\n\t\t{2, 2},\n\t\t{4, 0},\n\t\t{5, 0},\n\t\t{6, 0},\n\t\t{7, 0},\n\t\t{8, 0}, /*@8*/\n\t\t{9, 0},\n\t\t{0xa, 0},\n\t\t{0xb, 0},\n\t\t{0xc, 0},\n\t\t{0xd, 0},\n\t\t{0xe, 0},\n\t\t{0xf, 0}};\n\tu8 rfu_codeword_table_init_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] = {\n#if 1\n\t\t{9, 1}, /*@0*/\n\t\t{9, 9},\n\t\t{1, 9},\n\t\t{9, 6},\n\t\t{2, 1},\n\t\t{2, 9},\n\t\t{9, 2},\n\t\t{2, 2}, /*@8*/\n\t\t{6, 1},\n\t\t{6, 9},\n\t\t{2, 9},\n\t\t{2, 2},\n\t\t{6, 2},\n\t\t{6, 6},\n\t\t{2, 6},\n\t\t{1, 1}\n#else\n\t\t{1, 1}, /*@0*/\n\t\t{9, 1},\n\t\t{9, 9},\n\t\t{1, 9},\n\t\t{1, 2},\n\t\t{9, 2},\n\t\t{9, 6},\n\t\t{1, 6},\n\t\t{2, 1}, /*@8*/\n\t\t{6, 1},\n\t\t{6, 9},\n\t\t{2, 9},\n\t\t{2, 2},\n\t\t{6, 2},\n\t\t{6, 6},\n\t\t{2, 6}\n#endif\n\t};\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"***RTK 8822B SmartAnt_Init: Hong-Bo SmrtAnt Type2]\\n\");\n\n\t/* @---------------------------------------- */\n\t/* @GPIO 0-1 for Beam control */\n\t/* reg0x66[2:0]=0 */\n\t/* reg0x44[25:24] = 0 */\n\t/* reg0x44[23:16]  enable_output for P_GPIO[7:0] */\n\t/* reg0x44[15:8]  output_value for P_GPIO[7:0] */\n\t/* reg0x40[1:0] = 0  GPIO function */\n\t/* @------------------------------------------ */\n\n\todm_move_memory(dm, sat_tab->rfu_codeword_table_2g, rfu_codeword_table_init_2g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B));\n\todm_move_memory(dm, sat_tab->rfu_codeword_table_5g, rfu_codeword_table_init_5g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B));\n\n\t/*@GPIO setting*/\n\todm_set_mac_reg(dm, R_0x64, (BIT(18) | BIT(17) | BIT(16)), 0);\n\todm_set_mac_reg(dm, R_0x44, BIT(25) | BIT(24), 0); /*@config P_GPIO[3:2] to data port*/\n\todm_set_mac_reg(dm, R_0x44, BIT(17) | BIT(16), 0x3); /*@enable_output for P_GPIO[3:2]*/\n#if 0\n\t/*odm_set_mac_reg(dm, R_0x44, BIT(9)|BIT(8), 0);*/ /*P_GPIO[3:2] output value*/\n#endif\n\todm_set_mac_reg(dm, R_0x40, BIT(1) | BIT(0), 0); /*@GPIO function*/\n\n\t/*@Hong_lin smart antenna HW setting*/\n\tsat_tab->rfu_protocol_type = 2;\n\tsat_tab->rfu_protocol_delay_time = 45;\n\n\tsat_tab->rfu_codeword_total_bit_num = 16; /*@max=32bit*/\n\tsat_tab->rfu_each_ant_bit_num = 4;\n\n\tsat_tab->total_beam_set_num = 4;\n\tsat_tab->total_beam_set_num_2g = 4;\n\tsat_tab->total_beam_set_num_5g = 8;\n\n#if DEV_BUS_TYPE == RT_SDIO_INTERFACE\n\tif (dm->support_interface == ODM_ITRF_SDIO)\n\t\tsat_tab->latch_time = 100; /*@mu sec*/\n#endif\n#if DEV_BUS_TYPE == RT_USB_INTERFACE\n\tif (dm->support_interface == ODM_ITRF_USB)\n\t\tsat_tab->latch_time = 100; /*@mu sec*/\n#endif\n\tsat_tab->pkt_skip_statistic_en = 0;\n\n\tsat_tab->ant_num = 2;\n\tsat_tab->ant_num_total = MAX_PATH_NUM_8822B;\n\tsat_tab->first_train_ant = MAIN_ANT;\n\n\tsat_tab->fix_beam_pattern_en = 0;\n\tsat_tab->decision_holding_period = 0;\n\n\t/*@beam training setting*/\n\tsat_tab->pkt_counter = 0;\n\tsat_tab->per_beam_training_pkt_num = 10;\n\n\t/*set default beam*/\n\tsat_tab->fast_training_beam_num = 0;\n\tsat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;\n\n\tfor (j = 0; j < SUPPORT_BEAM_SET_PATTERN_NUM; j++) {\n\t\tsat_tab->beam_set_avg_rssi_pre[j] = 0;\n\t\tsat_tab->beam_set_train_val_diff[j] = 0;\n\t\tsat_tab->beam_set_train_cnt[j] = 0;\n\t}\n\tphydm_set_rfu_beam_pattern_type2(dm);\n\tfat_tab->fat_state = FAT_BEFORE_LINK_STATE;\n}\n#endif\n\nu32 phydm_construct_hb_rfu_codeword_type2(\n\tvoid *dm_void,\n\tu32 beam_set_idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\tu32 sync_codeword = 0x7f;\n\tu32 codeword = 0;\n\tu32 data_tmp = 0;\n\tu32 i;\n\n\tfor (i = 0; i < sat_tab->ant_num_total; i++) {\n\t\tif (*dm->band_type == ODM_BAND_5G)\n\t\t\tdata_tmp = sat_tab->rfu_codeword_table_5g[beam_set_idx][i];\n\t\telse\n\t\t\tdata_tmp = sat_tab->rfu_codeword_table_2g[beam_set_idx][i];\n\n\t\tcodeword |= (data_tmp << (i * sat_tab->rfu_each_ant_bit_num));\n\t}\n\n\tcodeword = (codeword << 8) | sync_codeword;\n\n\treturn codeword;\n}\n\nvoid phydm_update_beam_pattern_type2(\n\tvoid *dm_void,\n\tu32 codeword,\n\tu32 codeword_length)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\tu8 i;\n\tboolean beam_ctrl_signal;\n\tu32 one = 0x1;\n\tu32 reg44_tmp_p, reg44_tmp_n, reg44_ori;\n\tu8 devide_num = 4;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Set codeword = ((0x%x))\\n\", codeword);\n\n\treg44_ori = odm_get_mac_reg(dm, R_0x44, MASKDWORD);\n\treg44_tmp_p = reg44_ori;\n#if 0\n\t/*PHYDM_DBG(dm, DBG_ANT_DIV, \"reg44_ori =0x%x\\n\", reg44_ori);*/\n#endif\n\n\t/*@devide_num = (sat_tab->rfu_protocol_type == 2) ? 8 : 4;*/\n\n\tfor (i = 0; i <= (codeword_length - 1); i++) {\n\t\tbeam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i);\n\n\t\t#if 1\n\t\tif (dm->debug_components & DBG_ANT_DIV) {\n\t\t\tif (i == (codeword_length - 1))\n\t\t\t\tpr_debug(\"%d ]\\n\", beam_ctrl_signal);\n\t\t\telse if (i == 0)\n\t\t\t\tpr_debug(\"Start sending codeword[1:%d] ---> [ %d \", codeword_length, beam_ctrl_signal);\n\t\t\telse if ((i % devide_num) == (devide_num - 1))\n\t\t\t\tpr_debug(\"%d  |  \", beam_ctrl_signal);\n\t\t\telse\n\t\t\t\tpr_debug(\"%d \", beam_ctrl_signal);\n\t\t}\n\t\t#endif\n\n\t\tif (dm->support_ic_type == ODM_RTL8821) {\n\t\t\t#if (RTL8821A_SUPPORT == 1)\n\t\t\treg44_tmp_p = reg44_ori & (~(BIT(11) | BIT(10))); /*@clean bit 10 & 11*/\n\t\t\treg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10));\n\t\t\treg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10)));\n\n#if 0\n\t\t\t/*PHYDM_DBG(dm, DBG_ANT_DIV, \"reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\\n\", reg44_tmp_p, reg44_tmp_n);*/\n#endif\n\t\t\todm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);\n\t\t\todm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n);\n\t\t\t#endif\n\t\t}\n\t\t#if (RTL8822B_SUPPORT == 1)\n\t\telse if (dm->support_ic_type == ODM_RTL8822B) {\n\t\t\tif (sat_tab->rfu_protocol_type == 2) {\n\t\t\t\treg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*@clean bit 8*/\n\t\t\t\treg44_tmp_p = reg44_tmp_p ^ BIT(9); /*@get new clk high/low, exclusive-or*/\n\n\t\t\t\treg44_tmp_p |= (beam_ctrl_signal << 8);\n\n\t\t\t\todm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);\n\t\t\t\tODM_delay_us(sat_tab->rfu_protocol_delay_time);\n#if 0\n\t\t\t\t/*PHYDM_DBG(dm, DBG_ANT_DIV, \"reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\\n\", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal);*/\n#endif\n\n\t\t\t} else {\n\t\t\t\treg44_tmp_p = reg44_ori & (~(BIT(9) | BIT(8))); /*@clean bit 9 & 8*/\n\t\t\t\treg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8));\n\t\t\t\treg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8)));\n\n#if 0\n\t\t\t\t/*PHYDM_DBG(dm, DBG_ANT_DIV, \"reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\\n\", reg44_tmp_p, reg44_tmp_n); */\n#endif\n\t\t\t\todm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);\n\t\t\t\tODM_delay_us(10);\n\t\t\t\todm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n);\n\t\t\t\tODM_delay_us(10);\n\t\t\t}\n\t\t}\n\t\t#endif\n\t}\n}\n\nvoid phydm_update_rx_idle_beam_type2(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\tu32 i;\n\n\tsat_tab->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(dm, sat_tab->rx_idle_beam_set_idx);\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[ Update Rx-Idle-Beam ] BeamSet idx = ((%d))\\n\",\n\t\t  sat_tab->rx_idle_beam_set_idx);\n\n#if DEV_BUS_TYPE == RT_PCI_INTERFACE\n\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\tphydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);\n#endif\n#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE\n\tif (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)\n\t\todm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);\n#if 0\n\t/*odm_stall_execution(1);*/\n#endif\n#endif\n\n\tsat_tab->pre_codeword = sat_tab->update_beam_codeword;\n}\n\nvoid phydm_hl_smt_ant_dbg_type2(\n\tvoid *dm_void,\n\tchar input[][16],\n\tu32 *_used,\n\tchar *output,\n\tu32 *_out_len\n)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 one = 0x1;\n\tu32 codeword_length = sat_tab->rfu_codeword_total_bit_num;\n\tu32 beam_ctrl_signal, i;\n\tu8 devide_num = 4;\n\tchar help[] = \"-h\";\n\tu32 dm_value[10] = {0};\n\n\tPHYDM_SSCANF(input[1], DCMD_DECIMAL, &dm_value[0]);\n\tPHYDM_SSCANF(input[2], DCMD_DECIMAL, &dm_value[1]);\n\tPHYDM_SSCANF(input[3], DCMD_DECIMAL, &dm_value[2]);\n\tPHYDM_SSCANF(input[4], DCMD_DECIMAL, &dm_value[3]);\n\tPHYDM_SSCANF(input[5], DCMD_DECIMAL, &dm_value[4]);\n\n\tif (strcmp(input[1], help) == 0) {\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \" 1 {fix_en} {codeword(Hex)}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \" 3 {Fix_training_num_en} {Per_beam_training_pkt_num} {Decision_holding_period}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \" 5 {0:show, 1:2G, 2:5G} {beam_num} {idxA(Hex)} {idxB(Hex)}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \" 7 {0:show, 1:2G, 2:5G} {total_beam_set_num}\\n\");\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \" 8 {0:show, 1:set} {RFU delay time(us)}\\n\");\n\n\t} else if (dm_value[0] == 1) { /*@fix beam pattern*/\n\n\t\tsat_tab->fix_beam_pattern_en = dm_value[1];\n\n\t\tif (sat_tab->fix_beam_pattern_en == 1) {\n\t\t\tPHYDM_SSCANF(input[3], DCMD_HEX, &dm_value[2]);\n\t\t\tsat_tab->fix_beam_pattern_codeword = dm_value[2];\n\n\t\t\tif (sat_tab->fix_beam_pattern_codeword > (one << codeword_length)) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\\n\",\n\t\t\t\t\t  sat_tab->fix_beam_pattern_codeword,\n\t\t\t\t\t  codeword_length);\n\n\t\t\t\t(sat_tab->fix_beam_pattern_codeword) &= 0xffffff;\n\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"[ SmartAnt ] Auto modify to (0x%x)\\n\",\n\t\t\t\t\t  sat_tab->fix_beam_pattern_codeword);\n\t\t\t}\n\n\t\t\tsat_tab->update_beam_codeword = sat_tab->fix_beam_pattern_codeword;\n\n\t\t\t/*@---------------------------------------------------------*/\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"Fix Beam Pattern\\n\");\n\n\t\t\t/*@devide_num = (sat_tab->rfu_protocol_type == 2) ? 8 : 4;*/\n\n\t\t\tfor (i = 0; i <= (codeword_length - 1); i++) {\n\t\t\t\tbeam_ctrl_signal = (boolean)((sat_tab->update_beam_codeword & BIT(i)) >> i);\n\n\t\t\t\tif (i == (codeword_length - 1))\n\t\t\t\t\tPDM_SNPF(out_len, used,\n\t\t\t\t\t\t output + used,\n\t\t\t\t\t\t out_len - used,\n\t\t\t\t\t\t \"%d]\\n\",\n\t\t\t\t\t\t beam_ctrl_signal);\n\t\t\t\telse if (i == 0)\n\t\t\t\t\tPDM_SNPF(out_len, used,\n\t\t\t\t\t\t output + used,\n\t\t\t\t\t\t out_len - used,\n\t\t\t\t\t\t \"Send Codeword[1:%d] to RFU -> [%d\",\n\t\t\t\t\t\t sat_tab->rfu_codeword_total_bit_num,\n\t\t\t\t\t\t beam_ctrl_signal);\n\t\t\t\telse if ((i % devide_num) == (devide_num - 1))\n\t\t\t\t\tPDM_SNPF(out_len, used,\n\t\t\t\t\t\t output + used,\n\t\t\t\t\t\t out_len - used, \"%d|\",\n\t\t\t\t\t\t beam_ctrl_signal);\n\t\t\t\telse\n\t\t\t\t\tPDM_SNPF(out_len, used,\n\t\t\t\t\t\t output + used,\n\t\t\t\t\t\t out_len - used, \"%d\",\n\t\t\t\t\t\t beam_ctrl_signal);\n\t\t\t}\n/*@---------------------------------------------------------*/\n\n#if DEV_BUS_TYPE == RT_PCI_INTERFACE\n\t\t\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\t\t\tphydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);\n#endif\n#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE\n\t\t\tif (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)\n\t\t\todm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);\n#if 0\n\t\t\t/*odm_stall_execution(1);*/\n#endif\n#endif\n\t\t} else if (sat_tab->fix_beam_pattern_en == 0)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[ SmartAnt ] Smart Antenna: Enable\\n\");\n\n\t} else if (dm_value[0] == 2) { /*set latch time*/\n\n\t\tsat_tab->latch_time = dm_value[1];\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[ SmartAnt ]  latch_time =0x%x\\n\",\n\t\t\t  sat_tab->latch_time);\n\t} else if (dm_value[0] == 3) {\n\t\tsat_tab->fix_training_num_en = dm_value[1];\n\n\t\tif (sat_tab->fix_training_num_en == 1) {\n\t\t\tsat_tab->per_beam_training_pkt_num = (u8)dm_value[2];\n\t\t\tsat_tab->decision_holding_period = (u8)dm_value[3];\n\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[SmtAnt] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\\n\",\n\t\t\t\t sat_tab->fix_training_num_en,\n\t\t\t\t sat_tab->per_beam_training_pkt_num,\n\t\t\t\t sat_tab->decision_holding_period);\n\n\t\t} else if (sat_tab->fix_training_num_en == 0) {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[ SmartAnt ]  AUTO per_beam_training_pkt_num\\n\");\n\t\t}\n\t} else if (dm_value[0] == 4) {\n\t\t#if 0\n\t\tif (dm_value[1] == 1) {\n\t\t\tsat_tab->ant_num = 1;\n\t\t\tsat_tab->first_train_ant = MAIN_ANT;\n\n\t\t} else if (dm_value[1] == 2) {\n\t\t\tsat_tab->ant_num = 1;\n\t\t\tsat_tab->first_train_ant = AUX_ANT;\n\n\t\t} else if (dm_value[1] == 3) {\n\t\t\tsat_tab->ant_num = 2;\n\t\t\tsat_tab->first_train_ant = MAIN_ANT;\n\t\t}\n\n\t\tPDM_SNPF((output + used, out_len - used,\n\t\t\t \"[ SmartAnt ]  Set ant Num = (( %d )), first_train_ant = (( %d ))\\n\",\n\t\t\t sat_tab->ant_num, (sat_tab->first_train_ant - 1)));\n\t\t#endif\n\t} else if (dm_value[0] == 5) { /*set beam set table*/\n\n\t\tPHYDM_SSCANF(input[4], DCMD_HEX, &dm_value[3]);\n\t\tPHYDM_SSCANF(input[5], DCMD_HEX, &dm_value[4]);\n\n\t\tif (dm_value[1] == 1) { /*@2G*/\n\t\t\tif (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) {\n\t\t\t\tsat_tab->rfu_codeword_table_2g[dm_value[2]][0] = (u8)dm_value[3];\n\t\t\t\tsat_tab->rfu_codeword_table_2g[dm_value[2]][1] = (u8)dm_value[4];\n\t\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t\t out_len - used,\n\t\t\t\t\t \"[SmtAnt] Set 2G Table[%d] = [A:0x%x, B:0x%x]\\n\",\n\t\t\t\t\t dm_value[2], dm_value[3], dm_value[4]);\n\t\t\t}\n\n\t\t} else if (dm_value[1] == 2) { /*@5G*/\n\t\t\tif (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) {\n\t\t\t\tsat_tab->rfu_codeword_table_5g[dm_value[2]][0] = (u8)dm_value[3];\n\t\t\t\tsat_tab->rfu_codeword_table_5g[dm_value[2]][1] = (u8)dm_value[4];\n\t\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t\t out_len - used,\n\t\t\t\t\t \"[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\\n\",\n\t\t\t\t\t dm_value[2], dm_value[3], dm_value[4]);\n\t\t\t}\n\t\t} else if (dm_value[1] == 0) {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[SmtAnt] 2G Beam Table==============>\\n\");\n\t\t\tfor (i = 0; i < sat_tab->total_beam_set_num_2g; i++) {\n\t\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t\t out_len - used,\n\t\t\t\t\t \"2G Table[%d] = [A:0x%x, B:0x%x]\\n\", i,\n\t\t\t\t\t sat_tab->rfu_codeword_table_2g[i][0],\n\t\t\t\t\t sat_tab->rfu_codeword_table_2g[i][1]);\n\t\t\t}\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[SmtAnt] 5G Beam Table==============>\\n\");\n\t\t\tfor (i = 0; i < sat_tab->total_beam_set_num_5g; i++) {\n\t\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t\t out_len - used,\n\t\t\t\t\t \"5G Table[%d] = [A:0x%x, B:0x%x]\\n\", i,\n\t\t\t\t\t sat_tab->rfu_codeword_table_5g[i][0],\n\t\t\t\t\t sat_tab->rfu_codeword_table_5g[i][1]);\n\t\t\t}\n\t\t}\n\n\t} else if (dm_value[0] == 6) {\n#if 0\n\t\tif (dm_value[1] == 0) {\n\t\t\tif (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) {\n\t\t\t\tsat_tab->rfu_codeword_table_5g[dm_value[2] ][0] = (u8)dm_value[3];\n\t\t\t\tsat_tab->rfu_codeword_table_5g[dm_value[2] ][1] = (u8)dm_value[4];\n\t\t\t\tPDM_SNPF((output + used, out_len - used,\n\t\t\t\t\t \"[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\\n\",\n\t\t\t\t\t dm_value[2], dm_value[3],\n\t\t\t\t\t dm_value[4]));\n\t\t\t}\n\t\t} else {\n\t\t\tfor (i = 0; i < sat_tab->total_beam_set_num_5g; i++) {\n\t\t\t\tPDM_SNPF((output + used, out_len - used,\n\t\t\t\t\t \"[SmtAnt] Read 5G Table[%d] = [A:0x%x, B:0x%x]\\n\",\n\t\t\t\t\t i,\n\t\t\t\t\t sat_tab->rfu_codeword_table_5g[i][0],\n\t\t\t\t\t sat_tab->rfu_codeword_table_5g[i][1]));\n\t\t\t}\n\t\t}\n#endif\n\t} else if (dm_value[0] == 7) {\n\t\tif (dm_value[1] == 1) {\n\t\t\tsat_tab->total_beam_set_num_2g = (u8)(dm_value[2]);\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[ SmartAnt ] total_beam_set_num_2g = ((%d))\\n\",\n\t\t\t\t sat_tab->total_beam_set_num_2g);\n\n\t\t} else if (dm_value[1] == 2) {\n\t\t\tsat_tab->total_beam_set_num_5g = (u8)(dm_value[2]);\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[ SmartAnt ] total_beam_set_num_5g = ((%d))\\n\",\n\t\t\t\t sat_tab->total_beam_set_num_5g);\n\t\t} else if (dm_value[1] == 0) {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[ SmartAnt ] Show total_beam_set_num{2g,5g} = {%d,%d}\\n\",\n\t\t\t\t sat_tab->total_beam_set_num_2g,\n\t\t\t\t sat_tab->total_beam_set_num_5g);\n\t\t}\n\n\t} else if (dm_value[0] == 8) {\n\t\tif (dm_value[1] == 1) {\n\t\t\tsat_tab->rfu_protocol_delay_time = (u16)(dm_value[2]);\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[SmtAnt] Set rfu_protocol_delay_time = ((%d))\\n\",\n\t\t\t\t sat_tab->rfu_protocol_delay_time);\n\t\t} else if (dm_value[1] == 0) {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[SmtAnt] Read rfu_protocol_delay_time = ((%d))\\n\",\n\t\t\t\t sat_tab->rfu_protocol_delay_time);\n\t\t}\n\t}\n\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_set_rfu_beam_pattern_type2(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\n\tif (dm->ant_div_type != HL_SW_SMART_ANT_TYPE2)\n\t\treturn;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Training beam_set index = (( 0x%x ))\\n\",\n\t\t  sat_tab->fast_training_beam_num);\n\tsat_tab->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(dm, sat_tab->fast_training_beam_num);\n\n\t#if DEV_BUS_TYPE == RT_PCI_INTERFACE\n\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\tphydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);\n\t#endif\n\t#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE\n\tif (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)\n\t\todm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);\n#if 0\n\t/*odm_stall_execution(1);*/\n#endif\n\t#endif\n}\n\nvoid phydm_fast_ant_training_hl_smart_antenna_type2(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tstruct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;\n\tu32 codeword = 0;\n\tu8 i = 0, j = 0;\n\tu8 avg_rssi_tmp;\n\tu8 avg_rssi_tmp_ma;\n\tu8 max_beam_ant_rssi = 0;\n\tu8 rssi_target_beam = 0, target_beam_max_rssi = 0;\n\tu8 evm1ss_target_beam = 0, evm2ss_target_beam = 0;\n\tu32 target_beam_max_evm1ss = 0, target_beam_max_evm2ss = 0;\n\tu32 beam_tmp;\n\tu8 per_beam_val_diff_tmp = 0, training_pkt_num_offset;\n\tu32 avg_evm2ss[2] = {0}, avg_evm2ss_sum = 0;\n\tu32 avg_evm1ss = 0;\n\tu32 beam_path_evm_2ss_cnt_all = 0; /*sum of all 2SS-pattern cnt*/\n\tu32 beam_path_evm_1ss_cnt_all = 0; /*sum of all 1SS-pattern cnt*/\n\tu8 decision_type;\n\n\tif (!dm->is_linked) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[No Link!!!]\\n\");\n\n\t\tif (fat_tab->is_become_linked == true) {\n\t\t\tsat_tab->decision_holding_period = 0;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Link->no Link\\n\");\n\t\t\tfat_tab->fat_state = FAT_BEFORE_LINK_STATE;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"change to (( %d )) FAT_state\\n\",\n\t\t\t\t  fat_tab->fat_state);\n\t\t\tfat_tab->is_become_linked = dm->is_linked;\n\t\t}\n\t\treturn;\n\n\t} else {\n\t\tif (fat_tab->is_become_linked == false) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[Linked !!!]\\n\");\n\n\t\t\tfat_tab->fat_state = FAT_PREPARE_STATE;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"change to (( %d )) FAT_state\\n\",\n\t\t\t\t  fat_tab->fat_state);\n\n\t\t\t/*sat_tab->fast_training_beam_num = 0;*/\n\t\t\t/*phydm_set_rfu_beam_pattern_type2(dm);*/\n\n\t\t\tfat_tab->is_become_linked = dm->is_linked;\n\t\t}\n\t}\n\n#if 0\n\t/*PHYDM_DBG(dm, DBG_ANT_DIV, \"HL Smart ant Training: state (( %d ))\\n\", fat_tab->fat_state);*/\n#endif\n\n\t/* @[DECISION STATE] */\n\t/*@=======================================================================================*/\n\tif (fat_tab->fat_state == FAT_DECISION_STATE) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[ 3. In Decision state]\\n\");\n\n\t\t/*@compute target beam in each antenna*/\n\n\t\tfor (j = 0; j < (sat_tab->total_beam_set_num); j++) {\n\t\t\t/*@[Decision1: RSSI]-------------------------------------------------------------------*/\n\t\t\tif (sat_tab->statistic_pkt_cnt[j] == 0) { /*@if new RSSI = 0 -> MA_RSSI-=2*/\n\t\t\t\tavg_rssi_tmp = sat_tab->beam_set_avg_rssi_pre[j];\n\t\t\t\tavg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp;\n\t\t\t\tavg_rssi_tmp_ma = avg_rssi_tmp;\n\t\t\t} else {\n\t\t\t\tavg_rssi_tmp = (u8)((sat_tab->beam_set_rssi_avg_sum[j]) / (sat_tab->statistic_pkt_cnt[j]));\n\t\t\t\tavg_rssi_tmp_ma = (avg_rssi_tmp + sat_tab->beam_set_avg_rssi_pre[j]) >> 1;\n\t\t\t}\n\n\t\t\tsat_tab->beam_set_avg_rssi_pre[j] = avg_rssi_tmp;\n\n\t\t\tif (avg_rssi_tmp > target_beam_max_rssi) {\n\t\t\t\trssi_target_beam = j;\n\t\t\t\ttarget_beam_max_rssi = avg_rssi_tmp;\n\t\t\t}\n\n\t\t\t/*@[Decision2: EVM 2ss]-------------------------------------------------------------------*/\n\t\t\tif (sat_tab->beam_path_evm_2ss_cnt[j] != 0) {\n\t\t\t\tavg_evm2ss[0] = sat_tab->beam_path_evm_2ss_sum[j][0] / sat_tab->beam_path_evm_2ss_cnt[j];\n\t\t\t\tavg_evm2ss[1] = sat_tab->beam_path_evm_2ss_sum[j][1] / sat_tab->beam_path_evm_2ss_cnt[j];\n\t\t\t\tavg_evm2ss_sum = avg_evm2ss[0] + avg_evm2ss[1];\n\t\t\t\tbeam_path_evm_2ss_cnt_all += sat_tab->beam_path_evm_2ss_cnt[j];\n\n\t\t\t\tsat_tab->beam_set_avg_evm_2ss_pre[j] = (u8)avg_evm2ss_sum;\n\t\t\t}\n\n\t\t\tif (avg_evm2ss_sum > target_beam_max_evm2ss) {\n\t\t\t\tevm2ss_target_beam = j;\n\t\t\t\ttarget_beam_max_evm2ss = avg_evm2ss_sum;\n\t\t\t}\n\n\t\t\t/*@[Decision3: EVM 1ss]-------------------------------------------------------------------*/\n\t\t\tif (sat_tab->beam_path_evm_1ss_cnt[j] != 0) {\n\t\t\t\tavg_evm1ss = sat_tab->beam_path_evm_1ss_sum[j] / sat_tab->beam_path_evm_1ss_cnt[j];\n\t\t\t\tbeam_path_evm_1ss_cnt_all += sat_tab->beam_path_evm_1ss_cnt[j];\n\n\t\t\t\tsat_tab->beam_set_avg_evm_1ss_pre[j] = (u8)avg_evm1ss;\n\t\t\t}\n\n\t\t\tif (avg_evm1ss > target_beam_max_evm1ss) {\n\t\t\t\tevm1ss_target_beam = j;\n\t\t\t\ttarget_beam_max_evm1ss = avg_evm1ss;\n\t\t\t}\n\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"Beam[%d] Pkt_cnt=(( %d )), avg{MA,rssi}={%d, %d}, EVM1={%d}, EVM2={%d, %d, %d}\\n\",\n\t\t\t\t  j, sat_tab->statistic_pkt_cnt[j],\n\t\t\t\t  avg_rssi_tmp_ma, avg_rssi_tmp, avg_evm1ss,\n\t\t\t\t  avg_evm2ss[0], avg_evm2ss[1], avg_evm2ss_sum);\n\n\t\t\t/*reset counter value*/\n\t\t\tsat_tab->beam_set_rssi_avg_sum[j] = 0;\n\t\t\tsat_tab->beam_path_rssi_sum[j][0] = 0;\n\t\t\tsat_tab->beam_path_rssi_sum[j][1] = 0;\n\t\t\tsat_tab->statistic_pkt_cnt[j] = 0;\n\n\t\t\tsat_tab->beam_path_evm_2ss_sum[j][0] = 0;\n\t\t\tsat_tab->beam_path_evm_2ss_sum[j][1] = 0;\n\t\t\tsat_tab->beam_path_evm_2ss_cnt[j] = 0;\n\n\t\t\tsat_tab->beam_path_evm_1ss_sum[j] = 0;\n\t\t\tsat_tab->beam_path_evm_1ss_cnt[j] = 0;\n\t\t}\n\n\t\t/*@[Joint Decision]-------------------------------------------------------------------*/\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"--->1.[RSSI]      Target Beam(( %d )) RSSI_max=((%d))\\n\",\n\t\t\t  rssi_target_beam, target_beam_max_rssi);\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"--->2.[Evm2SS] Target Beam(( %d )) EVM2SS_max=((%d))\\n\",\n\t\t\t  evm2ss_target_beam, target_beam_max_evm2ss);\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"--->3.[Evm1SS] Target Beam(( %d )) EVM1SS_max=((%d))\\n\",\n\t\t\t  evm1ss_target_beam, target_beam_max_evm1ss);\n\n\t\tif (target_beam_max_rssi <= 10) {\n\t\t\tsat_tab->rx_idle_beam_set_idx = rssi_target_beam;\n\t\t\tdecision_type = 1;\n\t\t} else {\n\t\t\tif (beam_path_evm_2ss_cnt_all != 0) {\n\t\t\t\tsat_tab->rx_idle_beam_set_idx = evm2ss_target_beam;\n\t\t\t\tdecision_type = 2;\n\t\t\t} else if (beam_path_evm_1ss_cnt_all != 0) {\n\t\t\t\tsat_tab->rx_idle_beam_set_idx = evm1ss_target_beam;\n\t\t\t\tdecision_type = 3;\n\t\t\t} else {\n\t\t\t\tsat_tab->rx_idle_beam_set_idx = rssi_target_beam;\n\t\t\t\tdecision_type = 1;\n\t\t\t}\n\t\t}\n\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"---> Decision_type=((%d)), Final Target Beam(( %d ))\\n\",\n\t\t\t  decision_type, sat_tab->rx_idle_beam_set_idx);\n\n\t\t/*@Calculate packet counter offset*/\n\t\tfor (j = 0; j < (sat_tab->total_beam_set_num); j++) {\n\t\t\tif (decision_type == 1) {\n\t\t\t\tper_beam_val_diff_tmp = target_beam_max_rssi - sat_tab->beam_set_avg_rssi_pre[j];\n\n\t\t\t} else if (decision_type == 2) {\n\t\t\t\tper_beam_val_diff_tmp = ((u8)target_beam_max_evm2ss - sat_tab->beam_set_avg_evm_2ss_pre[j]) >> 1;\n\t\t\t} else if (decision_type == 3) {\n\t\t\t\tper_beam_val_diff_tmp = (u8)target_beam_max_evm1ss - sat_tab->beam_set_avg_evm_1ss_pre[j];\n\t\t\t}\n\t\t\tsat_tab->beam_set_train_val_diff[j] = per_beam_val_diff_tmp;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"Beam_Set[%d]: diff= ((%d))\\n\", j,\n\t\t\t\t  per_beam_val_diff_tmp);\n\t\t}\n\n\t\t/*set beam in each antenna*/\n\t\tphydm_update_rx_idle_beam_type2(dm);\n\t\tfat_tab->fat_state = FAT_PREPARE_STATE;\n\t}\n\t/* @[TRAINING STATE] */\n\telse if (fat_tab->fat_state == FAT_TRAINING_STATE) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[ 2. In Training state]\\n\");\n\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"curr_beam_idx = (( %d )), pre_beam_idx = (( %d ))\\n\",\n\t\t\t  sat_tab->fast_training_beam_num,\n\t\t\t  sat_tab->pre_fast_training_beam_num);\n\n\t\tif (sat_tab->fast_training_beam_num > sat_tab->pre_fast_training_beam_num)\n\n\t\t\tsat_tab->force_update_beam_en = 0;\n\n\t\telse {\n\t\t\tsat_tab->force_update_beam_en = 1;\n\n\t\t\tsat_tab->pkt_counter = 0;\n\t\t\tbeam_tmp = sat_tab->fast_training_beam_num;\n\t\t\tif (sat_tab->fast_training_beam_num >= ((u32)sat_tab->total_beam_set_num - 1)) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"[Timeout Update]  Beam_num (( %d )) -> (( decision ))\\n\",\n\t\t\t\t\t  sat_tab->fast_training_beam_num);\n\t\t\t\tfat_tab->fat_state = FAT_DECISION_STATE;\n\t\t\t\tphydm_fast_ant_training_hl_smart_antenna_type2(dm);\n\n\t\t\t} else {\n\t\t\t\tsat_tab->fast_training_beam_num++;\n\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"[Timeout Update]  Beam_num (( %d )) -> (( %d ))\\n\",\n\t\t\t\t\t  beam_tmp,\n\t\t\t\t\t  sat_tab->fast_training_beam_num);\n\t\t\t\tphydm_set_rfu_beam_pattern_type2(dm);\n\t\t\t\tfat_tab->fat_state = FAT_TRAINING_STATE;\n\t\t\t}\n\t\t}\n\t\tsat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Update Pre_Beam =(( %d ))\\n\",\n\t\t\t  sat_tab->pre_fast_training_beam_num);\n\t}\n\t/*  @[Prepare state] */\n\t/*@=======================================================================================*/\n\telse if (fat_tab->fat_state == FAT_PREPARE_STATE) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"\\n\\n[ 1. In Prepare state]\\n\");\n\n\t\tif (dm->pre_traffic_load == dm->traffic_load) {\n\t\t\tif (sat_tab->decision_holding_period != 0) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"Holding_period = (( %d )), return!!!\\n\",\n\t\t\t\t\t  sat_tab->decision_holding_period);\n\t\t\t\tsat_tab->decision_holding_period--;\n\t\t\t\treturn;\n\t\t\t}\n\t\t}\n\n\t\t/* Set training packet number*/\n\t\tif (sat_tab->fix_training_num_en == 0) {\n\t\t\tswitch (dm->traffic_load) {\n\t\t\tcase TRAFFIC_HIGH:\n\t\t\t\tsat_tab->per_beam_training_pkt_num = 8;\n\t\t\t\tsat_tab->decision_holding_period = 2;\n\t\t\t\tbreak;\n\t\t\tcase TRAFFIC_MID:\n\t\t\t\tsat_tab->per_beam_training_pkt_num = 6;\n\t\t\t\tsat_tab->decision_holding_period = 3;\n\t\t\t\tbreak;\n\t\t\tcase TRAFFIC_LOW:\n\t\t\t\tsat_tab->per_beam_training_pkt_num = 3; /*ping 60000*/\n\t\t\t\tsat_tab->decision_holding_period = 4;\n\t\t\t\tbreak;\n\t\t\tcase TRAFFIC_ULTRA_LOW:\n\t\t\t\tsat_tab->per_beam_training_pkt_num = 1;\n\t\t\t\tsat_tab->decision_holding_period = 6;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"TrafficLoad = (( %d )), Fix_beam = (( %d )), per_beam_training_pkt_num = (( %d )), decision_holding_period = ((%d))\\n\",\n\t\t\t  dm->traffic_load, sat_tab->fix_training_num_en,\n\t\t\t  sat_tab->per_beam_training_pkt_num,\n\t\t\t  sat_tab->decision_holding_period);\n\n\t\t/*@Beam_set number*/\n\t\tif (*dm->band_type == ODM_BAND_5G) {\n\t\t\tsat_tab->total_beam_set_num = sat_tab->total_beam_set_num_5g;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"5G beam_set num = ((%d))\\n\",\n\t\t\t\t  sat_tab->total_beam_set_num);\n\t\t} else {\n\t\t\tsat_tab->total_beam_set_num = sat_tab->total_beam_set_num_2g;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"2G beam_set num = ((%d))\\n\",\n\t\t\t\t  sat_tab->total_beam_set_num);\n\t\t}\n\n\t\tfor (j = 0; j < (sat_tab->total_beam_set_num); j++) {\n\t\t\ttraining_pkt_num_offset = sat_tab->beam_set_train_val_diff[j];\n\n\t\t\tif (sat_tab->per_beam_training_pkt_num > training_pkt_num_offset)\n\t\t\t\tsat_tab->beam_set_train_cnt[j] = sat_tab->per_beam_training_pkt_num - training_pkt_num_offset;\n\t\t\telse\n\t\t\t\tsat_tab->beam_set_train_cnt[j] = 1;\n\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"Beam_Set[ %d ] training_pkt_offset = ((%d)), training_pkt_num = ((%d))\\n\",\n\t\t\t\t  j, sat_tab->beam_set_train_val_diff[j],\n\t\t\t\t  sat_tab->beam_set_train_cnt[j]);\n\t\t}\n\n\t\tsat_tab->pre_beacon_counter = sat_tab->beacon_counter;\n\t\tsat_tab->update_beam_idx = 0;\n\t\tsat_tab->pkt_counter = 0;\n\n\t\tsat_tab->fast_training_beam_num = 0;\n\t\tphydm_set_rfu_beam_pattern_type2(dm);\n\t\tsat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;\n\t\tfat_tab->fat_state = FAT_TRAINING_STATE;\n\t}\n}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\nvoid phydm_beam_switch_workitem_callback(\n\tvoid *context)\n{\n\tvoid *adapter = (void *)context;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\n#if DEV_BUS_TYPE != RT_PCI_INTERFACE\n\tsat_tab->pkt_skip_statistic_en = 1;\n#endif\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\\n\",\n\t\t  sat_tab->pkt_skip_statistic_en);\n\n\tphydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);\n\n#if DEV_BUS_TYPE != RT_PCI_INTERFACE\n#if 0\n\t/*odm_stall_execution(sat_tab->latch_time);*/\n#endif\n\tsat_tab->pkt_skip_statistic_en = 0;\n#endif\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\\n\",\n\t\t  sat_tab->pkt_skip_statistic_en, sat_tab->latch_time);\n}\n\nvoid phydm_beam_decision_workitem_callback(\n\tvoid *context)\n{\n\tvoid *adapter = (void *)context;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[ SmartAnt ] Beam decision Workitem Callback\\n\");\n\tphydm_fast_ant_training_hl_smart_antenna_type2(dm);\n}\n#endif\n\nvoid phydm_process_rssi_for_hb_smtant_type2(\n\tvoid *dm_void,\n\tvoid *phy_info_void,\n\tvoid *pkt_info_void,\n\tu8 rssi_avg)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void;\n\tstruct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\tu8 train_pkt_number;\n\tu32 beam_tmp;\n\tu8 rx_power_ant0 = phy_info->rx_mimo_signal_strength[0];\n\tu8 rx_power_ant1 = phy_info->rx_mimo_signal_strength[1];\n\tu8 rx_evm_ant0 = phy_info->rx_mimo_evm_dbm[0];\n\tu8 rx_evm_ant1 = phy_info->rx_mimo_evm_dbm[1];\n\n\t/*@[Beacon]*/\n\tif (pktinfo->is_packet_beacon) {\n\t\tsat_tab->beacon_counter++;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"MatchBSSID_beacon_counter = ((%d))\\n\",\n\t\t\t  sat_tab->beacon_counter);\n\n\t\tif (sat_tab->beacon_counter >= sat_tab->pre_beacon_counter + 2) {\n\t\t\tsat_tab->update_beam_idx++;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\\n\",\n\t\t\t\t  sat_tab->pre_beacon_counter,\n\t\t\t\t  sat_tab->pkt_counter,\n\t\t\t\t  sat_tab->update_beam_idx);\n\n\t\t\tsat_tab->pre_beacon_counter = sat_tab->beacon_counter;\n\t\t\tsat_tab->pkt_counter = 0;\n\t\t}\n\t}\n\t/*@[data]*/\n\telse if (pktinfo->is_packet_to_self) {\n\t\tif (sat_tab->pkt_skip_statistic_en == 0) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"ID[%d] pkt_cnt=((%d)): Beam_set = ((%d)), RSSI{A,B,avg} = {%d, %d, %d}\\n\",\n\t\t\t\t  pktinfo->station_id, sat_tab->pkt_counter,\n\t\t\t\t  sat_tab->fast_training_beam_num,\n\t\t\t\t  rx_power_ant0, rx_power_ant1, rssi_avg);\n\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"Rate_ss = ((%d)), EVM{A,B} = {%d, %d}, RX Rate =\",\n\t\t\t\t  pktinfo->rate_ss, rx_evm_ant0, rx_evm_ant1);\n\t\t\tphydm_print_rate(dm, dm->rx_rate, DBG_ANT_DIV);\n\n\t\t\tif (sat_tab->pkt_counter >= 1) /*packet skip count*/\n\t\t\t{\n\t\t\t\tsat_tab->beam_set_rssi_avg_sum[sat_tab->fast_training_beam_num] += rssi_avg;\n\t\t\t\tsat_tab->statistic_pkt_cnt[sat_tab->fast_training_beam_num]++;\n\n\t\t\t\tsat_tab->beam_path_rssi_sum[sat_tab->fast_training_beam_num][0] += rx_power_ant0;\n\t\t\t\tsat_tab->beam_path_rssi_sum[sat_tab->fast_training_beam_num][1] += rx_power_ant1;\n\n\t\t\t\tif (pktinfo->rate_ss == 2) {\n\t\t\t\t\tsat_tab->beam_path_evm_2ss_sum[sat_tab->fast_training_beam_num][0] += rx_evm_ant0;\n\t\t\t\t\tsat_tab->beam_path_evm_2ss_sum[sat_tab->fast_training_beam_num][1] += rx_evm_ant1;\n\t\t\t\t\tsat_tab->beam_path_evm_2ss_cnt[sat_tab->fast_training_beam_num]++;\n\t\t\t\t} else {\n\t\t\t\t\tsat_tab->beam_path_evm_1ss_sum[sat_tab->fast_training_beam_num] += rx_evm_ant0;\n\t\t\t\t\tsat_tab->beam_path_evm_1ss_cnt[sat_tab->fast_training_beam_num]++;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tsat_tab->pkt_counter++;\n\n\t\t\ttrain_pkt_number = sat_tab->beam_set_train_cnt[sat_tab->fast_training_beam_num];\n\n\t\t\tif (sat_tab->pkt_counter >= train_pkt_number) {\n\t\t\t\tsat_tab->update_beam_idx++;\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"pre_beacon_counter = ((%d)), Update_new_beam = ((%d))\\n\",\n\t\t\t\t\t  sat_tab->pre_beacon_counter,\n\t\t\t\t\t  sat_tab->update_beam_idx);\n\n\t\t\t\tsat_tab->pre_beacon_counter = sat_tab->beacon_counter;\n\t\t\t\tsat_tab->pkt_counter = 0;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (sat_tab->update_beam_idx > 0) {\n\t\tsat_tab->update_beam_idx = 0;\n\n\t\tif (sat_tab->fast_training_beam_num >= ((u32)sat_tab->total_beam_set_num - 1)) {\n\t\t\tfat_tab->fat_state = FAT_DECISION_STATE;\n\n\t\t\t#if DEV_BUS_TYPE == RT_PCI_INTERFACE\n\t\t\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\t\t\tphydm_fast_ant_training_hl_smart_antenna_type2(dm); /*@go to make decision*/\n\t\t\t#endif\n\t\t\t#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE\n\t\t\tif (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)\n\t\t\t\todm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);\n\t\t\t#endif\n\n\t\t} else {\n\t\t\tbeam_tmp = sat_tab->fast_training_beam_num;\n\t\t\tsat_tab->fast_training_beam_num++;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"Update Beam_num (( %d )) -> (( %d ))\\n\",\n\t\t\t\t  beam_tmp, sat_tab->fast_training_beam_num);\n\t\t\tphydm_set_rfu_beam_pattern_type2(dm);\n\t\t\tsat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;\n\n\t\t\tfat_tab->fat_state = FAT_TRAINING_STATE;\n\t\t}\n\t}\n}\n#endif\n\n#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))\n\nvoid phydm_hl_smart_ant_type1_init_8821a(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tu32 value32;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"***8821A SmartAnt_Init => ant_div_type=[Hong-Lin Smart ant Type1]\\n\");\n\n#if 0\n\t/* @---------------------------------------- */\n\t/* @GPIO 2-3 for Beam control */\n\t/* reg0x66[2]=0 */\n\t/* reg0x44[27:26] = 0 */\n\t/* reg0x44[23:16]  enable_output for P_GPIO[7:0] */\n\t/* reg0x44[15:8]  output_value for P_GPIO[7:0] */\n\t/* reg0x40[1:0] = 0  GPIO function */\n\t/* @------------------------------------------ */\n#endif\n\n\t/*@GPIO setting*/\n\todm_set_mac_reg(dm, R_0x64, BIT(18), 0);\n\todm_set_mac_reg(dm, R_0x44, BIT(27) | BIT(26), 0);\n\todm_set_mac_reg(dm, R_0x44, BIT(19) | BIT(18), 0x3); /*@enable_output for P_GPIO[3:2]*/\n#if 0\n\t/*odm_set_mac_reg(dm, R_0x44, BIT(11)|BIT(10), 0);*/ /*output value*/\n#endif\n\todm_set_mac_reg(dm, R_0x40, BIT(1) | BIT(0), 0); /*@GPIO function*/\n\n\t/*@Hong_lin smart antenna HW setting*/\n\tsat_tab->rfu_codeword_total_bit_num = 24; /*@max=32*/\n\tsat_tab->rfu_each_ant_bit_num = 4;\n\tsat_tab->beam_patten_num_each_ant = 4;\n\n#if DEV_BUS_TYPE == RT_SDIO_INTERFACE\n\tsat_tab->latch_time = 100; /*@mu sec*/\n#elif DEV_BUS_TYPE == RT_USB_INTERFACE\n\tsat_tab->latch_time = 100; /*@mu sec*/\n#endif\n\tsat_tab->pkt_skip_statistic_en = 0;\n\n\tsat_tab->ant_num = 1; /*@max=8*/\n\tsat_tab->ant_num_total = NUM_ANTENNA_8821A;\n\tsat_tab->first_train_ant = MAIN_ANT;\n\n\tsat_tab->rfu_codeword_table[0] = 0x0;\n\tsat_tab->rfu_codeword_table[1] = 0x4;\n\tsat_tab->rfu_codeword_table[2] = 0x8;\n\tsat_tab->rfu_codeword_table[3] = 0xc;\n\n\tsat_tab->rfu_codeword_table_5g[0] = 0x1;\n\tsat_tab->rfu_codeword_table_5g[1] = 0x2;\n\tsat_tab->rfu_codeword_table_5g[2] = 0x4;\n\tsat_tab->rfu_codeword_table_5g[3] = 0x8;\n\n\tsat_tab->fix_beam_pattern_en = 0;\n\tsat_tab->decision_holding_period = 0;\n\n\t/*@beam training setting*/\n\tsat_tab->pkt_counter = 0;\n\tsat_tab->per_beam_training_pkt_num = 10;\n\n\t/*set default beam*/\n\tsat_tab->fast_training_beam_num = 0;\n\tsat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;\n\tphydm_set_all_ant_same_beam_num(dm);\n\n\tfat_tab->fat_state = FAT_BEFORE_LINK_STATE;\n\n\todm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x01000100);\n\todm_set_bb_reg(dm, R_0xca8, MASKDWORD, 0x01000100);\n\n\t/*@[BB] FAT setting*/\n\todm_set_bb_reg(dm, R_0xc08, BIT(18) | BIT(17) | BIT(16), sat_tab->ant_num);\n\todm_set_bb_reg(dm, R_0xc08, BIT(31), 0); /*@increase ant num every FAT period 0:+1, 1+2*/\n\todm_set_bb_reg(dm, R_0x8c4, BIT(2) | BIT(1), 1); /*@change cca antenna timming threshold if no CCA occurred: 0:200ms / 1:100ms / 2:no use / 3: 300*/\n\todm_set_bb_reg(dm, R_0x8c4, BIT(0), 1); /*@FAT_watchdog_en*/\n\n\tvalue32 = odm_get_mac_reg(dm, R_0x7b4, MASKDWORD);\n\todm_set_mac_reg(dm, R_0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /*Reg7B4[16]=1 enable antenna training */\n\t/*Reg7B4[17]=1 enable  match MAC addr*/\n\todm_set_mac_reg(dm, R_0x7b4, 0xFFFF, 0); /*@Match MAC ADDR*/\n\todm_set_mac_reg(dm, R_0x7b0, MASKDWORD, 0);\n}\n\nu32 phydm_construct_hl_beam_codeword(\n\tvoid *dm_void,\n\tu32 *beam_pattern_idx,\n\tu32 ant_num)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\tu32 codeword = 0;\n\tu32 data_tmp;\n\tu32 i;\n\tu32 break_counter = 0;\n\n\tif (ant_num < 8) {\n\t\tfor (i = 0; i < (sat_tab->ant_num_total); i++) {\n#if 0\n\t\t\t/*PHYDM_DBG(dm,DBG_ANT_DIV, \"beam_pattern_num[%x] = %x\\n\",i,beam_pattern_num[i] );*/\n#endif\n\t\t\tif ((i < (sat_tab->first_train_ant - 1)) || break_counter >= sat_tab->ant_num) {\n\t\t\t\tdata_tmp = 0;\n\t\t\t} else {\n\t\t\t\tbreak_counter++;\n\n\t\t\t\tif (beam_pattern_idx[i] == 0) {\n\t\t\t\t\tif (*dm->band_type == ODM_BAND_5G)\n\t\t\t\t\t\tdata_tmp = sat_tab->rfu_codeword_table_5g[0];\n\t\t\t\t\telse\n\t\t\t\t\t\tdata_tmp = sat_tab->rfu_codeword_table[0];\n\n\t\t\t\t} else if (beam_pattern_idx[i] == 1) {\n\t\t\t\t\tif (*dm->band_type == ODM_BAND_5G)\n\t\t\t\t\t\tdata_tmp = sat_tab->rfu_codeword_table_5g[1];\n\t\t\t\t\telse\n\t\t\t\t\t\tdata_tmp = sat_tab->rfu_codeword_table[1];\n\n\t\t\t\t} else if (beam_pattern_idx[i] == 2) {\n\t\t\t\t\tif (*dm->band_type == ODM_BAND_5G)\n\t\t\t\t\t\tdata_tmp = sat_tab->rfu_codeword_table_5g[2];\n\t\t\t\t\telse\n\t\t\t\t\t\tdata_tmp = sat_tab->rfu_codeword_table[2];\n\n\t\t\t\t} else if (beam_pattern_idx[i] == 3) {\n\t\t\t\t\tif (*dm->band_type == ODM_BAND_5G)\n\t\t\t\t\t\tdata_tmp = sat_tab->rfu_codeword_table_5g[3];\n\t\t\t\t\telse\n\t\t\t\t\t\tdata_tmp = sat_tab->rfu_codeword_table[3];\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tcodeword |= (data_tmp << (i * 4));\n\t\t}\n\t}\n\n\treturn codeword;\n}\n\nvoid phydm_update_beam_pattern(\n\tvoid *dm_void,\n\tu32 codeword,\n\tu32 codeword_length)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\tu8 i;\n\tboolean beam_ctrl_signal;\n\tu32 one = 0x1;\n\tu32 reg44_tmp_p, reg44_tmp_n, reg44_ori;\n\tu8 devide_num = 4;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[ SmartAnt ] Set Beam Pattern =0x%x\\n\",\n\t\t  codeword);\n\n\treg44_ori = odm_get_mac_reg(dm, R_0x44, MASKDWORD);\n\treg44_tmp_p = reg44_ori;\n#if 0\n\t/*PHYDM_DBG(dm, DBG_ANT_DIV, \"reg44_ori =0x%x\\n\", reg44_ori);*/\n#endif\n\n\tdevide_num = (sat_tab->rfu_protocol_type == 2) ? 6 : 4;\n\n\tfor (i = 0; i <= (codeword_length - 1); i++) {\n\t\tbeam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i);\n\n\t\tif (dm->debug_components & DBG_ANT_DIV) {\n\t\t\tif (i == (codeword_length - 1))\n\t\t\t\tpr_debug(\"%d ]\\n\", beam_ctrl_signal);\n\t\t\telse if (i == 0)\n\t\t\t\tpr_debug(\"Send codeword[1:%d] ---> [ %d \", codeword_length, beam_ctrl_signal);\n\t\t\telse if ((i % devide_num) == (devide_num - 1))\n\t\t\t\tpr_debug(\"%d  |  \", beam_ctrl_signal);\n\t\t\telse\n\t\t\t\tpr_debug(\"%d \", beam_ctrl_signal);\n\t\t}\n\n\t\tif (dm->support_ic_type == ODM_RTL8821) {\n\t\t\t#if (RTL8821A_SUPPORT == 1)\n\t\t\treg44_tmp_p = reg44_ori & (~(BIT(11) | BIT(10))); /*@clean bit 10 & 11*/\n\t\t\treg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10));\n\t\t\treg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10)));\n\n#if 0\n\t\t\t/*PHYDM_DBG(dm, DBG_ANT_DIV, \"reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\\n\", reg44_tmp_p, reg44_tmp_n);*/\n#endif\n\t\t\todm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);\n\t\t\todm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n);\n\t\t\t#endif\n\t\t}\n\t\t#if (RTL8822B_SUPPORT == 1)\n\t\telse if (dm->support_ic_type == ODM_RTL8822B) {\n\t\t\tif (sat_tab->rfu_protocol_type == 2) {\n\t\t\t\treg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*@clean bit 8*/\n\t\t\t\treg44_tmp_p = reg44_tmp_p ^ BIT(9); /*@get new clk high/low, exclusive-or*/\n\n\t\t\t\treg44_tmp_p |= (beam_ctrl_signal << 8);\n\n\t\t\t\todm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);\n\t\t\t\tODM_delay_us(10);\n#if 0\n\t\t\t\t/*PHYDM_DBG(dm, DBG_ANT_DIV, \"reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\\n\", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal);*/\n#endif\n\n\t\t\t} else {\n\t\t\t\treg44_tmp_p = reg44_ori & (~(BIT(9) | BIT(8))); /*@clean bit 9 & 8*/\n\t\t\t\treg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8));\n\t\t\t\treg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8)));\n\n#if 0\n\t\t\t\t/*PHYDM_DBG(dm, DBG_ANT_DIV, \"reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\\n\", reg44_tmp_p, reg44_tmp_n); */\n#endif\n\t\t\t\todm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);\n\t\t\t\tODM_delay_us(10);\n\t\t\t\todm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n);\n\t\t\t\tODM_delay_us(10);\n\t\t\t}\n\t\t}\n\t\t#endif\n\t}\n}\n\nvoid phydm_update_rx_idle_beam(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\tu32 i;\n\n\tsat_tab->update_beam_codeword = phydm_construct_hl_beam_codeword(dm,\n\t\t\t\t\t\t\t\t\t &sat_tab->rx_idle_beam[0],\n\t\t\t\t\t\t\t\t\t sat_tab->ant_num);\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"Set target beam_pattern codeword = (( 0x%x ))\\n\",\n\t\t  sat_tab->update_beam_codeword);\n\n\tfor (i = 0; i < (sat_tab->ant_num); i++)\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[ Update Rx-Idle-Beam ] RxIdleBeam[%d] =%d\\n\", i,\n\t\t\t  sat_tab->rx_idle_beam[i]);\n\n#if DEV_BUS_TYPE == RT_PCI_INTERFACE\n\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\tphydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);\n#endif\n#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE\n\tif (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)\n\t\todm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);\n#if 0\n\t/*odm_stall_execution(1);*/\n#endif\n#endif\n\n\tsat_tab->pre_codeword = sat_tab->update_beam_codeword;\n}\n\nvoid phydm_hl_smart_ant_debug(\n\tvoid *dm_void,\n\tchar input[][16],\n\tu32 *_used,\n\tchar *output,\n\tu32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 one = 0x1;\n\tu32 codeword_length = sat_tab->rfu_codeword_total_bit_num;\n\tu32 beam_ctrl_signal, i;\n\tu8 devide_num = 4;\n\n\tif (dm_value[0] == 1) { /*@fix beam pattern*/\n\n\t\tsat_tab->fix_beam_pattern_en = dm_value[1];\n\n\t\tif (sat_tab->fix_beam_pattern_en == 1) {\n\t\t\tsat_tab->fix_beam_pattern_codeword = dm_value[2];\n\n\t\t\tif (sat_tab->fix_beam_pattern_codeword > (one << codeword_length)) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\\n\",\n\t\t\t\t\t  sat_tab->fix_beam_pattern_codeword,\n\t\t\t\t\t  codeword_length);\n\n\t\t\t\t(sat_tab->fix_beam_pattern_codeword) &= 0xffffff;\n\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"[ SmartAnt ] Auto modify to (0x%x)\\n\",\n\t\t\t\t\t  sat_tab->fix_beam_pattern_codeword);\n\t\t\t}\n\n\t\t\tsat_tab->update_beam_codeword = sat_tab->fix_beam_pattern_codeword;\n\n\t\t\t/*@---------------------------------------------------------*/\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"Fix Beam Pattern\\n\");\n\n\t\t\tdevide_num = (sat_tab->rfu_protocol_type == 2) ? 6 : 4;\n\n\t\t\tfor (i = 0; i <= (codeword_length - 1); i++) {\n\t\t\t\tbeam_ctrl_signal = (boolean)((sat_tab->update_beam_codeword & BIT(i)) >> i);\n\n\t\t\t\tif (i == (codeword_length - 1))\n\t\t\t\t\tPDM_SNPF(out_len, used,\n\t\t\t\t\t\t output + used,\n\t\t\t\t\t\t out_len - used,\n\t\t\t\t\t\t \"%d]\\n\",\n\t\t\t\t\t\t beam_ctrl_signal);\n\t\t\t\telse if (i == 0)\n\t\t\t\t\tPDM_SNPF(out_len, used,\n\t\t\t\t\t\t output + used,\n\t\t\t\t\t\t out_len - used,\n\t\t\t\t\t\t \"Send Codeword[1:24] to RFU -> [%d\",\n\t\t\t\t\t\t beam_ctrl_signal);\n\t\t\t\telse if ((i % devide_num) == (devide_num - 1))\n\t\t\t\t\tPDM_SNPF(out_len, used,\n\t\t\t\t\t\t output + used,\n\t\t\t\t\t\t out_len - used, \"%d|\",\n\t\t\t\t\t\t beam_ctrl_signal);\n\t\t\t\telse\n\t\t\t\t\tPDM_SNPF(out_len, used,\n\t\t\t\t\t\t output + used,\n\t\t\t\t\t\t out_len - used, \"%d\",\n\t\t\t\t\t\t beam_ctrl_signal);\n\t\t\t}\n/*@---------------------------------------------------------*/\n\n\t\t\t#if DEV_BUS_TYPE == RT_PCI_INTERFACE\n\t\t\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\t\t\tphydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);\n\t\t\t#endif\n\t\t\t#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE\n\t\t\tif (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)\n\t\t\t\todm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);\n#if 0\n\t\t\t/*odm_stall_execution(1);*/\n#endif\n\t\t\t#endif\n\t\t} else if (sat_tab->fix_beam_pattern_en == 0)\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[ SmartAnt ] Smart Antenna: Enable\\n\");\n\n\t} else if (dm_value[0] == 2) { /*set latch time*/\n\n\t\tsat_tab->latch_time = dm_value[1];\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[ SmartAnt ]  latch_time =0x%x\\n\",\n\t\t\t  sat_tab->latch_time);\n\t} else if (dm_value[0] == 3) {\n\t\tsat_tab->fix_training_num_en = dm_value[1];\n\n\t\tif (sat_tab->fix_training_num_en == 1) {\n\t\t\tsat_tab->per_beam_training_pkt_num = (u8)dm_value[2];\n\t\t\tsat_tab->decision_holding_period = (u8)dm_value[3];\n\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[SmartAnt][Dbg] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\\n\",\n\t\t\t\t sat_tab->fix_training_num_en,\n\t\t\t\t sat_tab->per_beam_training_pkt_num,\n\t\t\t\t sat_tab->decision_holding_period);\n\n\t\t} else if (sat_tab->fix_training_num_en == 0) {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[ SmartAnt ]  AUTO per_beam_training_pkt_num\\n\");\n\t\t}\n\t} else if (dm_value[0] == 4) {\n\t\tif (dm_value[1] == 1) {\n\t\t\tsat_tab->ant_num = 1;\n\t\t\tsat_tab->first_train_ant = MAIN_ANT;\n\n\t\t} else if (dm_value[1] == 2) {\n\t\t\tsat_tab->ant_num = 1;\n\t\t\tsat_tab->first_train_ant = AUX_ANT;\n\n\t\t} else if (dm_value[1] == 3) {\n\t\t\tsat_tab->ant_num = 2;\n\t\t\tsat_tab->first_train_ant = MAIN_ANT;\n\t\t}\n\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"[ SmartAnt ]  Set ant Num = (( %d )), first_train_ant = (( %d ))\\n\",\n\t\t\t sat_tab->ant_num, (sat_tab->first_train_ant - 1));\n\t} else if (dm_value[0] == 5) {\n\t\tif (dm_value[1] <= 3) {\n\t\t\tsat_tab->rfu_codeword_table[dm_value[1]] = dm_value[2];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[ SmartAnt ] Set Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\\n\",\n\t\t\t\t dm_value[1], dm_value[2]);\n\t\t} else {\n\t\t\tfor (i = 0; i < 4; i++) {\n\t\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t\t out_len - used,\n\t\t\t\t\t \"[ SmartAnt ] Show Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\\n\",\n\t\t\t\t\t i, sat_tab->rfu_codeword_table[i]);\n\t\t\t}\n\t\t}\n\t} else if (dm_value[0] == 6) {\n\t\tif (dm_value[1] <= 3) {\n\t\t\tsat_tab->rfu_codeword_table_5g[dm_value[1]] = dm_value[2];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[ SmartAnt ] Set Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\\n\",\n\t\t\t\t dm_value[1], dm_value[2]);\n\t\t} else {\n\t\t\tfor (i = 0; i < 4; i++) {\n\t\t\t\tPDM_SNPF(out_len, used, output + used,\n\t\t\t\t\t out_len - used,\n\t\t\t\t\t \"[ SmartAnt ] Show Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\\n\",\n\t\t\t\t\t i, sat_tab->rfu_codeword_table_5g[i]);\n\t\t\t}\n\t\t}\n\t} else if (dm_value[0] == 7) {\n\t\tif (dm_value[1] <= 4) {\n\t\t\tsat_tab->beam_patten_num_each_ant = dm_value[1];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[ SmartAnt ] Set Beam number = (( %d ))\\n\",\n\t\t\t\t sat_tab->beam_patten_num_each_ant);\n\t\t} else {\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"[ SmartAnt ] Show Beam number = (( %d ))\\n\",\n\t\t\t\t sat_tab->beam_patten_num_each_ant);\n\t\t}\n\t}\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_set_all_ant_same_beam_num(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\n\tif (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { /*@2ant for 8821A*/\n\n\t\tsat_tab->rx_idle_beam[0] = sat_tab->fast_training_beam_num;\n\t\tsat_tab->rx_idle_beam[1] = sat_tab->fast_training_beam_num;\n\t}\n\n\tsat_tab->update_beam_codeword = phydm_construct_hl_beam_codeword(dm,\n\t\t\t\t\t\t\t\t\t &sat_tab->rx_idle_beam[0],\n\t\t\t\t\t\t\t\t\t sat_tab->ant_num);\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[ SmartAnt ] Set all ant beam_pattern: codeword = (( 0x%x ))\\n\",\n\t\t  sat_tab->update_beam_codeword);\n\n#if DEV_BUS_TYPE == RT_PCI_INTERFACE\n\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\tphydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);\n#endif\n#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE\n\tif (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)\n\t\todm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);\n/*odm_stall_execution(1);*/\n#endif\n}\n\nvoid odm_fast_ant_training_hl_smart_antenna_type1(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\tstruct phydm_fat_struct *fat_tab = &dm->dm_fat_table;\n\tstruct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;\n\tu32 codeword = 0, i, j;\n\tu32 target_ant;\n\tu32 avg_rssi_tmp, avg_rssi_tmp_ma;\n\tu32 target_ant_beam_max_rssi[SUPPORT_RF_PATH_NUM] = {0};\n\tu32 max_beam_ant_rssi = 0;\n\tu32 target_ant_beam[SUPPORT_RF_PATH_NUM] = {0};\n\tu32 beam_tmp;\n\tu8 next_ant;\n\tu32 rssi_sorting_seq[SUPPORT_BEAM_PATTERN_NUM] = {0};\n\tu32 rank_idx_seq[SUPPORT_BEAM_PATTERN_NUM] = {0};\n\tu32 rank_idx_out[SUPPORT_BEAM_PATTERN_NUM] = {0};\n\tu8 per_beam_rssi_diff_tmp = 0, training_pkt_num_offset;\n\tu32 break_counter = 0;\n\tu32 used_ant;\n\n\tif (!dm->is_linked) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[No Link!!!]\\n\");\n\n\t\tif (fat_tab->is_become_linked == true) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Link->no Link\\n\");\n\t\t\tfat_tab->fat_state = FAT_BEFORE_LINK_STATE;\n\t\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);\n\t\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"change to (( %d )) FAT_state\\n\",\n\t\t\t\t  fat_tab->fat_state);\n\n\t\t\tfat_tab->is_become_linked = dm->is_linked;\n\t\t}\n\t\treturn;\n\n\t} else {\n\t\tif (fat_tab->is_become_linked == false) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[Linked !!!]\\n\");\n\n\t\t\tfat_tab->fat_state = FAT_PREPARE_STATE;\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"change to (( %d )) FAT_state\\n\",\n\t\t\t\t  fat_tab->fat_state);\n\n#if 0\n\t\t\t/*sat_tab->fast_training_beam_num = 0;*/\n\t\t\t/*phydm_set_all_ant_same_beam_num(dm);*/\n#endif\n\n\t\t\tfat_tab->is_become_linked = dm->is_linked;\n\t\t}\n\t}\n\n\tif (!(*fat_tab->p_force_tx_by_desc)) {\n\t\tif (dm->is_one_entry_only == true)\n\t\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);\n\t\telse\n\t\t\todm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);\n\t}\n\n#if 0\n\t/*PHYDM_DBG(dm, DBG_ANT_DIV, \"HL Smart ant Training: state (( %d ))\\n\", fat_tab->fat_state);*/\n#endif\n\n\t/* @[DECISION STATE] */\n\t/*@=======================================================================================*/\n\tif (fat_tab->fat_state == FAT_DECISION_STATE) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[ 3. In Decision state]\\n\");\n\t\tphydm_fast_training_enable(dm, FAT_OFF);\n\n\t\tbreak_counter = 0;\n\t\t/*@compute target beam in each antenna*/\n\t\tfor (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) {\n\t\t\tfor (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) {\n\t\t\t\tif (sat_tab->pkt_rssi_cnt[i][j] == 0) {\n\t\t\t\t\tavg_rssi_tmp = sat_tab->pkt_rssi_pre[i][j];\n\t\t\t\t\tavg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp;\n\t\t\t\t\tavg_rssi_tmp_ma = avg_rssi_tmp;\n\t\t\t\t} else {\n\t\t\t\t\tavg_rssi_tmp = (sat_tab->pkt_rssi_sum[i][j]) / (sat_tab->pkt_rssi_cnt[i][j]);\n\t\t\t\t\tavg_rssi_tmp_ma = (avg_rssi_tmp + sat_tab->pkt_rssi_pre[i][j]) >> 1;\n\t\t\t\t}\n\n\t\t\t\trssi_sorting_seq[j] = avg_rssi_tmp;\n\t\t\t\tsat_tab->pkt_rssi_pre[i][j] = avg_rssi_tmp;\n\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"ant[%d], Beam[%d]: pkt_cnt=(( %d )), avg_rssi_MA=(( %d )), avg_rssi=(( %d ))\\n\",\n\t\t\t\t\t  i, j, sat_tab->pkt_rssi_cnt[i][j],\n\t\t\t\t\t  avg_rssi_tmp_ma, avg_rssi_tmp);\n\n\t\t\t\tif (avg_rssi_tmp > target_ant_beam_max_rssi[i]) {\n\t\t\t\t\ttarget_ant_beam[i] = j;\n\t\t\t\t\ttarget_ant_beam_max_rssi[i] = avg_rssi_tmp;\n\t\t\t\t}\n\n\t\t\t\t/*reset counter value*/\n\t\t\t\tsat_tab->pkt_rssi_sum[i][j] = 0;\n\t\t\t\tsat_tab->pkt_rssi_cnt[i][j] = 0;\n\t\t\t}\n\t\t\tsat_tab->rx_idle_beam[i] = target_ant_beam[i];\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t  \"---------> Target of ant[%d]: Beam_num-(( %d )) RSSI= ((%d))\\n\",\n\t\t\t\t  i, target_ant_beam[i],\n\t\t\t\t  target_ant_beam_max_rssi[i]);\n\n#if 0\n\t\t\t/*sorting*/\n\t\t\t/*@\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[Pre]rssi_sorting_seq = [%d, %d, %d, %d]\\n\", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3]);\n\t\t\t*/\n\n\t\t\t/*phydm_seq_sorting(dm, &rssi_sorting_seq[0], &rank_idx_seq[0], &rank_idx_out[0], SUPPORT_BEAM_PATTERN_NUM);*/\n\n\t\t\t/*@\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[Post]rssi_sorting_seq = [%d, %d, %d, %d]\\n\", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3]);\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[Post]rank_idx_seq = [%d, %d, %d, %d]\\n\", rank_idx_seq[0], rank_idx_seq[1], rank_idx_seq[2], rank_idx_seq[3]);\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[Post]rank_idx_out = [%d, %d, %d, %d]\\n\", rank_idx_out[0], rank_idx_out[1], rank_idx_out[2], rank_idx_out[3]);\n\t\t\t*/\n#endif\n\n\t\t\tif (target_ant_beam_max_rssi[i] > max_beam_ant_rssi) {\n\t\t\t\ttarget_ant = i;\n\t\t\t\tmax_beam_ant_rssi = target_ant_beam_max_rssi[i];\n#if\n\t\t\t\t/*PHYDM_DBG(dm, DBG_ANT_DIV, \"Target of ant = (( %d )) max_beam_ant_rssi = (( %d ))\\n\",\n\t\t\t\t\ttarget_ant,  max_beam_ant_rssi);*/\n#endif\n\t\t\t}\n\t\t\tbreak_counter++;\n\t\t\tif (break_counter >= sat_tab->ant_num)\n\t\t\t\tbreak;\n\t\t}\n\n#ifdef CONFIG_FAT_PATCH\n\t\tbreak_counter = 0;\n\t\tfor (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) {\n\t\t\tfor (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) {\n\t\t\t\tper_beam_rssi_diff_tmp = (u8)(max_beam_ant_rssi - sat_tab->pkt_rssi_pre[i][j]);\n\t\t\t\tsat_tab->beam_train_rssi_diff[i][j] = per_beam_rssi_diff_tmp;\n\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"ant[%d], Beam[%d]: RSSI_diff= ((%d))\\n\",\n\t\t\t\t\t  i, j, per_beam_rssi_diff_tmp);\n\t\t\t}\n\t\t\tbreak_counter++;\n\t\t\tif (break_counter >= sat_tab->ant_num)\n\t\t\t\tbreak;\n\t\t}\n#endif\n\n\t\tif (target_ant == 0)\n\t\t\ttarget_ant = MAIN_ANT;\n\t\telse if (target_ant == 1)\n\t\t\ttarget_ant = AUX_ANT;\n\n\t\tif (sat_tab->ant_num > 1) {\n\t\t\t/* @[ update RX ant ]*/\n\t\t\todm_update_rx_idle_ant(dm, (u8)target_ant);\n\n\t\t\t/* @[ update TX ant ]*/\n\t\t\todm_update_tx_ant(dm, (u8)target_ant, (fat_tab->train_idx));\n\t\t}\n\n\t\t/*set beam in each antenna*/\n\t\tphydm_update_rx_idle_beam(dm);\n\n\t\todm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);\n\t\tfat_tab->fat_state = FAT_PREPARE_STATE;\n\t\treturn;\n\t}\n\t/* @[TRAINING STATE] */\n\telse if (fat_tab->fat_state == FAT_TRAINING_STATE) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"[ 2. In Training state]\\n\");\n\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"fat_beam_n = (( %d )), pre_fat_beam_n = (( %d ))\\n\",\n\t\t\t  sat_tab->fast_training_beam_num,\n\t\t\t  sat_tab->pre_fast_training_beam_num);\n\n\t\tif (sat_tab->fast_training_beam_num > sat_tab->pre_fast_training_beam_num)\n\n\t\t\tsat_tab->force_update_beam_en = 0;\n\n\t\telse {\n\t\t\tsat_tab->force_update_beam_en = 1;\n\n\t\t\tsat_tab->pkt_counter = 0;\n\t\t\tbeam_tmp = sat_tab->fast_training_beam_num;\n\t\t\tif (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"[Timeout Update]  Beam_num (( %d )) -> (( decision ))\\n\",\n\t\t\t\t\t  sat_tab->fast_training_beam_num);\n\t\t\t\tfat_tab->fat_state = FAT_DECISION_STATE;\n\t\t\t\todm_fast_ant_training_hl_smart_antenna_type1(dm);\n\n\t\t\t} else {\n\t\t\t\tsat_tab->fast_training_beam_num++;\n\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"[Timeout Update]  Beam_num (( %d )) -> (( %d ))\\n\",\n\t\t\t\t\t  beam_tmp,\n\t\t\t\t\t  sat_tab->fast_training_beam_num);\n\t\t\t\tphydm_set_all_ant_same_beam_num(dm);\n\t\t\t\tfat_tab->fat_state = FAT_TRAINING_STATE;\n\t\t\t}\n\t\t}\n\t\tsat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"[prepare state] Update Pre_Beam =(( %d ))\\n\",\n\t\t\t  sat_tab->pre_fast_training_beam_num);\n\t}\n\t/*  @[Prepare state] */\n\t/*@=======================================================================================*/\n\telse if (fat_tab->fat_state == FAT_PREPARE_STATE) {\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"\\n\\n[ 1. In Prepare state]\\n\");\n\n\t\tif (dm->pre_traffic_load == dm->traffic_load) {\n\t\t\tif (sat_tab->decision_holding_period != 0) {\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"Holding_period = (( %d )), return!!!\\n\",\n\t\t\t\t\t  sat_tab->decision_holding_period);\n\t\t\t\tsat_tab->decision_holding_period--;\n\t\t\t\treturn;\n\t\t\t}\n\t\t}\n\n\t\t/* Set training packet number*/\n\t\tif (sat_tab->fix_training_num_en == 0) {\n\t\t\tswitch (dm->traffic_load) {\n\t\t\tcase TRAFFIC_HIGH:\n\t\t\t\tsat_tab->per_beam_training_pkt_num = 8;\n\t\t\t\tsat_tab->decision_holding_period = 2;\n\t\t\t\tbreak;\n\t\t\tcase TRAFFIC_MID:\n\t\t\t\tsat_tab->per_beam_training_pkt_num = 6;\n\t\t\t\tsat_tab->decision_holding_period = 3;\n\t\t\t\tbreak;\n\t\t\tcase TRAFFIC_LOW:\n\t\t\t\tsat_tab->per_beam_training_pkt_num = 3; /*ping 60000*/\n\t\t\t\tsat_tab->decision_holding_period = 4;\n\t\t\t\tbreak;\n\t\t\tcase TRAFFIC_ULTRA_LOW:\n\t\t\t\tsat_tab->per_beam_training_pkt_num = 1;\n\t\t\t\tsat_tab->decision_holding_period = 6;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t  \"Fix_training_en = (( %d )), training_pkt_num_base = (( %d )), holding_period = ((%d))\\n\",\n\t\t\t  sat_tab->fix_training_num_en,\n\t\t\t  sat_tab->per_beam_training_pkt_num,\n\t\t\t  sat_tab->decision_holding_period);\n\n#ifdef CONFIG_FAT_PATCH\n\t\tbreak_counter = 0;\n\t\tfor (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) {\n\t\t\tfor (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) {\n\t\t\t\tper_beam_rssi_diff_tmp = sat_tab->beam_train_rssi_diff[i][j];\n\t\t\t\ttraining_pkt_num_offset = per_beam_rssi_diff_tmp;\n\n\t\t\t\tif (sat_tab->per_beam_training_pkt_num > training_pkt_num_offset)\n\t\t\t\t\tsat_tab->beam_train_cnt[i][j] = sat_tab->per_beam_training_pkt_num - training_pkt_num_offset;\n\t\t\t\telse\n\t\t\t\t\tsat_tab->beam_train_cnt[i][j] = 1;\n\n\t\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t\t\t\t  \"ant[%d]: Beam_num-(( %d ))  training_pkt_num = ((%d))\\n\",\n\t\t\t\t\t  i, j, sat_tab->beam_train_cnt[i][j]);\n\t\t\t}\n\t\t\tbreak_counter++;\n\t\t\tif (break_counter >= sat_tab->ant_num)\n\t\t\t\tbreak;\n\t\t}\n\n\t\tphydm_fast_training_enable(dm, FAT_OFF);\n\t\tsat_tab->pre_beacon_counter = sat_tab->beacon_counter;\n\t\tsat_tab->update_beam_idx = 0;\n\n\t\tif (*dm->band_type == ODM_BAND_5G) {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Set 5G ant\\n\");\n\t\t\t/*used_ant = (sat_tab->first_train_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;*/\n\t\t\tused_ant = sat_tab->first_train_ant;\n\t\t} else {\n\t\t\tPHYDM_DBG(dm, DBG_ANT_DIV, \"Set 2.4G ant\\n\");\n\t\t\tused_ant = sat_tab->first_train_ant;\n\t\t}\n\n\t\todm_update_rx_idle_ant(dm, (u8)used_ant);\n\n#else\n\t\t/* Set training MAC addr. of target */\n\t\todm_set_next_mac_addr_target(dm);\n\t\tphydm_fast_training_enable(dm, FAT_ON);\n#endif\n\n\t\todm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);\n\t\tsat_tab->pkt_counter = 0;\n\t\tsat_tab->fast_training_beam_num = 0;\n\t\tphydm_set_all_ant_same_beam_num(dm);\n\t\tsat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;\n\t\tfat_tab->fat_state = FAT_TRAINING_STATE;\n\t}\n}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\nvoid phydm_beam_switch_workitem_callback(\n\tvoid *context)\n{\n\tvoid *adapter = (void *)context;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\tstruct smt_ant_honbo *sat_tab = &dm->dm_sat_table;\n\n#if DEV_BUS_TYPE != RT_PCI_INTERFACE\n\tsat_tab->pkt_skip_statistic_en = 1;\n#endif\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\\n\",\n\t\t  sat_tab->pkt_skip_statistic_en);\n\n\tphydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);\n\n#if DEV_BUS_TYPE != RT_PCI_INTERFACE\n#if 0\n\t/*odm_stall_execution(sat_tab->latch_time);*/\n#endif\n\tsat_tab->pkt_skip_statistic_en = 0;\n#endif\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\\n\",\n\t\t  sat_tab->pkt_skip_statistic_en, sat_tab->latch_time);\n}\n\nvoid phydm_beam_decision_workitem_callback(\n\tvoid *context)\n{\n\tvoid *adapter = (void *)context;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\n\tPHYDM_DBG(dm, DBG_ANT_DIV,\n\t\t  \"[ SmartAnt ] Beam decision Workitem Callback\\n\");\n\todm_fast_ant_training_hl_smart_antenna_type1(dm);\n}\n#endif\n\n#endif /*@#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/\n\n#endif /*@#ifdef CONFIG_HL_SMART_ANTENNA*/\n\nvoid phydm_smt_ant_config(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant *smtant_table = &dm->smtant_table;\n\n#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))\n\n\tdm->support_ability |= ODM_BB_SMT_ANT;\n\tsmtant_table->smt_ant_vendor = SMTANT_CUMITEK;\n\tsmtant_table->smt_ant_type = 1;\n#if (RTL8822B_SUPPORT == 1)\n\tdm->rfe_type = SMTANT_TMP_RFE_TYPE;\n#endif\n#elif (defined(CONFIG_HL_SMART_ANTENNA))\n\n\tdm->support_ability |= ODM_BB_SMT_ANT;\n\tsmtant_table->smt_ant_vendor = SMTANT_HON_BO;\n\n#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1\n\tsmtant_table->smt_ant_type = 1;\n#endif\n\n#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2\n\tsmtant_table->smt_ant_type = 2;\n#endif\n#endif\n\n\tPHYDM_DBG(dm, DBG_SMT_ANT,\n\t\t  \"[SmtAnt Config] Vendor=((%d)), Smt_ant_type =((%d))\\n\",\n\t\t  smtant_table->smt_ant_vendor, smtant_table->smt_ant_type);\n}\n\nvoid phydm_smt_ant_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct smt_ant *smtant_table = &dm->smtant_table;\n\n\tphydm_smt_ant_config(dm);\n\n\tif (smtant_table->smt_ant_vendor == SMTANT_CUMITEK) {\n#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))\n#if (RTL8822B_SUPPORT == 1)\n\t\tif (dm->support_ic_type == ODM_RTL8822B)\n\t\t\tphydm_cumitek_smt_ant_init_8822b(dm);\n#endif\n\n#if (RTL8197F_SUPPORT == 1)\n\t\tif (dm->support_ic_type == ODM_RTL8197F)\n\t\t\tphydm_cumitek_smt_ant_init_8197f(dm);\n#endif\n/*@jj add 20170822*/\n#if (RTL8192F_SUPPORT == 1)\n\t\tif (dm->support_ic_type == ODM_RTL8192F)\n\t\t\tphydm_cumitek_smt_ant_init_8192f(dm);\n#endif\n#endif /*@#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))*/\n\n\t} else if (smtant_table->smt_ant_vendor == SMTANT_HON_BO) {\n#if (defined(CONFIG_HL_SMART_ANTENNA))\n#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1\n\t\tif (dm->support_ic_type == ODM_RTL8821)\n\t\t\tphydm_hl_smart_ant_type1_init_8821a(dm);\n#endif\n\n#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2\n\t\tif (dm->support_ic_type == ODM_RTL8822B)\n\t\t\tphydm_hl_smart_ant_type2_init_8822b(dm);\n#endif\n#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/\n\t}\n}\n#endif\n"
  },
  {
    "path": "hal/phydm/phydm_smt_ant.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#ifndef __PHYDMSMTANT_H__\n#define __PHYDMSMTANT_H__\n\n/*@#define SMT_ANT_VERSION\t\"1.1\"*/ /*@2017.03.13*/\n/*@#define SMT_ANT_VERSION\t\"1.2\"*/ /*@2017.03.28*/\n#define SMT_ANT_VERSION \"2.0\" /* @Add Cumitek SmtAnt 2017.05.25*/\n\n#define\tSMTANT_RTK\t\t1\n#define\tSMTANT_HON_BO\t2\n#define\tSMTANT_CUMITEK\t3\n\n#if (defined(CONFIG_SMART_ANTENNA))\n\n#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))\nstruct smt_ant_cumitek {\n\tu8\ttx_ant_idx[2][ODM_ASSOCIATE_ENTRY_NUM]; /*@[pathA~B] [MACID 0~128]*/\n\tu8\trx_default_ant_idx[2]; /*@[pathA~B]*/\n};\n#endif\n\n#if (defined(CONFIG_HL_SMART_ANTENNA))\nstruct smt_ant_honbo {\n\tu32\tlatch_time;\n\tboolean\tpkt_skip_statistic_en;\n\tu32\tfix_beam_pattern_en;\n\tu32\tfix_training_num_en;\n\tu32\tfix_beam_pattern_codeword;\n\tu32\tupdate_beam_codeword;\n\tu32\tant_num; /*number of \"used\" smart beam antenna*/\n\tu32\tant_num_total;/*number of \"total\" smart beam antenna*/\n\tu32\tfirst_train_ant; /*@decide witch antenna to train first*/\n\n\t#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1\n\tu32\tpkt_rssi_pre[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];/*@rssi of each path with a certain beam pattern*/\n\tu8\tbeam_train_rssi_diff[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];\n\tu8\tbeam_train_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];\n\tu32\trfu_codeword_table[4]; /*@2G beam truth table*/\n\tu32\trfu_codeword_table_5g[4]; /*@5G beam truth table*/\n\tu32\tbeam_patten_num_each_ant;/*@number of  beam can be switched in each antenna*/\n\tu32\trx_idle_beam[SUPPORT_RF_PATH_NUM];\n\tu32\tpkt_rssi_sum[8][SUPPORT_BEAM_PATTERN_NUM];\n\tu32\tpkt_rssi_cnt[8][SUPPORT_BEAM_PATTERN_NUM];\n\t#endif\n\n\tu32\tfast_training_beam_num;/*@current training beam_set index*/\n\tu32\tpre_fast_training_beam_num;/*pre training beam_set index*/\n\tu32\trfu_codeword_total_bit_num; /* @total bit number of RFU protocol*/\n\tu32\trfu_each_ant_bit_num; /* @bit number of RFU protocol for each ant*/\n\tu8\tper_beam_training_pkt_num;\n\tu8\tdecision_holding_period;\n\n\n\tu32\tpre_codeword;\n\tboolean\tforce_update_beam_en;\n\tu32\tbeacon_counter;\n\tu32\tpre_beacon_counter;\n\tu8\tpkt_counter;\t\t/*@packet number that each beam-set should be colected in training state*/\n\tu8\tupdate_beam_idx;\t/*@the index announce that the beam can be updated*/\n\tu8\trfu_protocol_type;\n\tu16\trfu_protocol_delay_time;\n\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tRT_WORK_ITEM\thl_smart_antenna_workitem;\n\tRT_WORK_ITEM\thl_smart_antenna_decision_workitem;\n\t#endif\n\n\n\t#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2\n\tu8\tbeam_set_avg_rssi_pre[SUPPORT_BEAM_SET_PATTERN_NUM];\t\t/*@avg pre_rssi of each beam set*/\n\tu8\tbeam_set_train_val_diff[SUPPORT_BEAM_SET_PATTERN_NUM];\t/*@rssi of a beam pattern set, ex: a set = {ant1_beam=1, ant2_beam=3}*/\n\tu8\tbeam_set_train_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];\t\t\t/*@training pkt num of each beam set*/\n\tu32\tbeam_set_rssi_avg_sum[SUPPORT_BEAM_SET_PATTERN_NUM];\t\t\t/*@RSSI_sum of avg(pathA,pathB) for each beam-set)*/\n\tu32\tbeam_path_rssi_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*@RSSI_sum of each path for each beam-set)*/\n\n\tu8\tbeam_set_avg_evm_2ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM];\n\tu32\tbeam_path_evm_2ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*@2SS evm_sum of each path for each beam-set)*/\n\tu32\tbeam_path_evm_2ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];\n\n\tu8\tbeam_set_avg_evm_1ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM];\n\tu32\tbeam_path_evm_1ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM];/*@1SS evm_sum of each path for each beam-set)*/\n\tu32\tbeam_path_evm_1ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];\n\n\tu32\tstatistic_pkt_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];\t\t\t\t/*@statistic_pkt_cnt for SmtAnt make decision*/\n\n\tu8\ttotal_beam_set_num;\t/*@number of  beam set can be switched*/\n\tu8\ttotal_beam_set_num_2g;/*@number of  beam set can be switched in 2G*/\n\tu8\ttotal_beam_set_num_5g;/*@number of  beam set can be switched in 5G*/\n\n\tu8\trfu_codeword_table_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*@2G beam truth table*/\n\tu8\trfu_codeword_table_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*@5G beam truth table*/\n\tu8\trx_idle_beam_set_idx;\t/*the filanl decsion result*/\n\t#endif\n\n\n};\n#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/\n\nstruct smt_ant {\n\tu8\tsmt_ant_vendor;\n\tu8\tsmt_ant_type;\n\tu8\ttx_desc_mode; /*@0:3 bit mode, 1:2 bit mode*/\n\t#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))\n\tstruct\tsmt_ant_cumitek\tcumi_smtant_table;\n\t#endif\n};\n\n#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))\nvoid phydm_cumitek_smt_tx_ant_update(\n\tvoid *dm_void,\n\tu8 tx_ant_idx_path_a,\n\tu8 tx_ant_idx_path_b,\n\tu32 mac_id);\n\nvoid phydm_cumitek_smt_rx_default_ant_update(\n\tvoid *dm_void,\n\tu8 rx_ant_idx_path_a,\n\tu8 rx_ant_idx_path_b);\n\nvoid phydm_cumitek_smt_ant_debug(\n\tvoid *dm_void,\n\tchar input[][16],\n\tu32 *_used,\n\tchar *output,\n\tu32 *_out_len);\n\n#endif\n\n#if (defined(CONFIG_HL_SMART_ANTENNA))\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid phydm_beam_switch_workitem_callback(\n\tvoid *context);\n\nvoid phydm_beam_decision_workitem_callback(\n\tvoid *context);\n#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/\n\n#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2\nvoid phydm_hl_smart_ant_type2_init_8822b(\n\tvoid *dm_void);\n\nvoid phydm_update_beam_pattern_type2(\n\tvoid *dm_void,\n\tu32 codeword,\n\tu32 codeword_length);\n\nvoid phydm_set_rfu_beam_pattern_type2(\n\tvoid *dm_void);\n\nvoid phydm_hl_smt_ant_dbg_type2(\n\tvoid *dm_void,\n\tchar input[][16],\n\tu32 *_used,\n\tchar *output,\n\tu32 *_out_len);\n\nvoid phydm_process_rssi_for_hb_smtant_type2(\n\tvoid *dm_void,\n\tvoid *phy_info_void,\n\tvoid *pkt_info_void,\n\tu8 rssi_avg);\n\n#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE2))*/\n\n#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))\n\nvoid phydm_update_beam_pattern(\n\tvoid *dm_void,\n\tu32 codeword,\n\tu32 codeword_length);\n\nvoid phydm_set_all_ant_same_beam_num(\n\tvoid *dm_void);\n\nvoid phydm_hl_smart_ant_debug(\n\tvoid *dm_void,\n\tchar input[][16],\n\tu32 *_used,\n\tchar *output,\n\tu32 *_out_len);\n\n#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))*/\n#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/\nvoid phydm_smt_ant_init(void *dm_void);\n#endif /*@#if (defined(CONFIG_SMART_ANTENNA))*/\n#endif"
  },
  {
    "path": "hal/phydm/phydm_soml.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*************************************************************\n * include files\n ************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#ifdef CONFIG_ADAPTIVE_SOML\n\nvoid phydm_dynamicsoftmletting(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 ret_val;\n\n#if (RTL8822B_SUPPORT == 1)\n\tif (!*dm->mp_mode) {\n\t\tif (dm->support_ic_type & ODM_RTL8822B) {\n\t\t\tif (!dm->is_linked | dm->iot_table.is_linked_cmw500)\n\t\t\t\treturn;\n\n\t\t\tif (dm->bsomlenabled) {\n\t\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t\t  \"PHYDM_DynamicSoftMLSetting(): SoML has been enable, skip dynamic SoML switch\\n\");\n\t\t\t\treturn;\n\t\t\t}\n\n\t\t\tret_val = odm_get_bb_reg(dm, R_0xf8c, MASKBYTE0);\n\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t  \"PHYDM_DynamicSoftMLSetting(): Read 0xF8C = 0x%08X\\n\",\n\t\t\t\t  ret_val);\n\n\t\t\tif (ret_val < 0x16) {\n\t\t\t\tPHYDM_DBG(dm, ODM_COMP_API,\n\t\t\t\t\t  \"PHYDM_DynamicSoftMLSetting(): 0xF8C(== 0x%08X) < 0x16, enable SoML\\n\",\n\t\t\t\t\t  ret_val);\n\t\t\t\tphydm_somlrxhp_setting(dm, true);\n#if 0\n\t\t\t/*odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0xc10a0000);*/\n#endif\n\t\t\t\tdm->bsomlenabled = true;\n\t\t\t}\n\t\t}\n\t}\n#endif\n}\n\nvoid phydm_soml_on_off(void *dm_void, u8 swch)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\n\tif (swch == SOML_ON) {\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML, \"(( Turn on )) SOML\\n\");\n\n\t\tif (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))\n\t\t\todm_set_bb_reg(dm, R_0x998, BIT(6), swch);\n#if (RTL8822B_SUPPORT == 1)\n\t\telse if (dm->support_ic_type == ODM_RTL8822B)\n\t\t\tphydm_somlrxhp_setting(dm, true);\n#endif\n\n\t} else if (swch == SOML_OFF) {\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML, \"(( Turn off )) SOML\\n\");\n\n\t\tif (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))\n\t\t\todm_set_bb_reg(dm, R_0x998, BIT(6), swch);\n#if (RTL8822B_SUPPORT == 1)\n\t\telse if (dm->support_ic_type == ODM_RTL8822B)\n\t\t\tphydm_somlrxhp_setting(dm, false);\n#endif\n\t}\n\tsoml_tab->soml_on_off = swch;\n}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid phydm_adaptive_soml_callback(struct phydm_timer_list *timer)\n{\n\tvoid *adapter = (void *)timer->Adapter;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\n\t#if DEV_BUS_TYPE == RT_PCI_INTERFACE\n\t#if USE_WORKITEM\n\todm_schedule_work_item(&soml_tab->phydm_adaptive_soml_workitem);\n\t#else\n\t{\n#if 0\n\t\t/*@dbg_print(\"%s\\n\",__func__);*/\n#endif\n\t\tphydm_adsl(dm);\n\t}\n\t#endif\n\t#else\n\todm_schedule_work_item(&soml_tab->phydm_adaptive_soml_workitem);\n\t#endif\n}\n\nvoid phydm_adaptive_soml_workitem_callback(void *context)\n{\n#ifdef CONFIG_ADAPTIVE_SOML\n\tvoid *adapter = (void *)context;\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\n#if 0\n\t/*@dbg_print(\"%s\\n\",__func__);*/\n#endif\n\tphydm_adsl(dm);\n#endif\n}\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\nvoid phydm_adaptive_soml_callback(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tvoid *padapter = dm->adapter;\n\n\tif (*dm->is_net_closed == true)\n\t\treturn;\n\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\tphydm_adsl(dm);\n\telse {\n\t\t/* @Can't do I/O in timer callback*/\n\t\tphydm_run_in_thread_cmd(dm,\n\t\t\t\t\tphydm_adaptive_soml_workitem_callback,\n\t\t\t\t\tdm);\n\t}\n}\n\nvoid phydm_adaptive_soml_workitem_callback(void *context)\n{\n\tstruct dm_struct *dm = (void *)context;\n\n#if 0\n\t/*@dbg_print(\"%s\\n\",__func__);*/\n#endif\n\tphydm_adsl(dm);\n}\n\n#else\nvoid phydm_adaptive_soml_callback(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_ADPTV_SOML, \"******SOML_Callback******\\n\");\n\tphydm_adsl(dm);\n}\n#endif\n\nvoid phydm_rx_rate_for_soml(void *dm_void, void *pkt_info_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\tstruct phydm_perpkt_info_struct *pktinfo = NULL;\n\tu8 data_rate;\n\n\tpktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;\n\tdata_rate = (pktinfo->data_rate & 0x7f);\n\n\tif (pktinfo->data_rate >= ODM_RATEMCS0 &&\n\t    pktinfo->data_rate <= ODM_RATEMCS31)\n\t\tsoml_tab->ht_cnt[data_rate - ODM_RATEMCS0]++;\n\telse if ((pktinfo->data_rate >= ODM_RATEVHTSS1MCS0) &&\n\t\t (pktinfo->data_rate <= ODM_RATEVHTSS4MCS9))\n\t\tsoml_tab->vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++;\n}\n\nvoid phydm_rx_qam_for_soml(void *dm_void, void *pkt_info_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\tstruct phydm_perpkt_info_struct *pktinfo = NULL;\n\tu8 date_rate;\n\n\tpktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;\n\tdate_rate = (pktinfo->data_rate & 0x7f);\n\tif (soml_tab->soml_state_cnt < (soml_tab->soml_train_num << 1)) {\n\t\tif (soml_tab->soml_on_off == SOML_ON) {\n\t\t\treturn;\n\t\t} else if (soml_tab->soml_on_off == SOML_OFF) {\n\t\t\tif (date_rate >= ODM_RATEMCS8 &&\n\t\t\t    date_rate <= ODM_RATEMCS10)\n\t\t\t\tsoml_tab->num_ht_qam[BPSK_QPSK]++;\n\n\t\t\telse if ((date_rate >= ODM_RATEMCS11) &&\n\t\t\t\t (date_rate <= ODM_RATEMCS12))\n\t\t\t\tsoml_tab->num_ht_qam[QAM16]++;\n\n\t\t\telse if ((date_rate >= ODM_RATEMCS13) &&\n\t\t\t\t (date_rate <= ODM_RATEMCS15))\n\t\t\t\tsoml_tab->num_ht_qam[QAM64]++;\n\n\t\t\telse if ((date_rate >= ODM_RATEVHTSS2MCS0) &&\n\t\t\t\t (date_rate <= ODM_RATEVHTSS2MCS2))\n\t\t\t\tsoml_tab->num_vht_qam[BPSK_QPSK]++;\n\n\t\t\telse if ((date_rate >= ODM_RATEVHTSS2MCS3) &&\n\t\t\t\t (date_rate <= ODM_RATEVHTSS2MCS4))\n\t\t\t\tsoml_tab->num_vht_qam[QAM16]++;\n\n\t\t\telse if ((date_rate >= ODM_RATEVHTSS2MCS5) &&\n\t\t\t\t (date_rate <= ODM_RATEVHTSS2MCS5))\n\t\t\t\tsoml_tab->num_vht_qam[QAM64]++;\n\n\t\t\telse if ((date_rate >= ODM_RATEVHTSS2MCS8) &&\n\t\t\t\t (date_rate <= ODM_RATEVHTSS2MCS9))\n\t\t\t\tsoml_tab->num_vht_qam[QAM256]++;\n\t\t}\n\t}\n}\n\nvoid phydm_soml_reset_rx_rate(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\tu8 order;\n\n\tfor (order = 0; order < HT_RATE_IDX; order++) {\n\t\tsoml_tab->ht_cnt[order] = 0;\n\t\tsoml_tab->pre_ht_cnt[order] = 0;\n\t\tsoml_tab->ht_cnt_on[order] = 0;\n\t\tsoml_tab->ht_cnt_off[order] = 0;\n\t\tsoml_tab->ht_crc_ok_cnt_on[order] = 0;\n\t\tsoml_tab->ht_crc_fail_cnt_on[order] = 0;\n\t\tsoml_tab->ht_crc_ok_cnt_off[order] = 0;\n\t\tsoml_tab->ht_crc_fail_cnt_off[order] = 0;\n\t}\n\n\tfor (order = 0; order < VHT_RATE_IDX; order++) {\n\t\tsoml_tab->vht_cnt[order] = 0;\n\t\tsoml_tab->pre_vht_cnt[order] = 0;\n\t\tsoml_tab->vht_cnt_on[order] = 0;\n\t\tsoml_tab->vht_cnt_off[order] = 0;\n\t\tsoml_tab->vht_crc_ok_cnt_on[order] = 0;\n\t\tsoml_tab->vht_crc_fail_cnt_on[order] = 0;\n\t\tsoml_tab->vht_crc_ok_cnt_off[order] = 0;\n\t\tsoml_tab->vht_crc_fail_cnt_off[order] = 0;\n\t}\n}\n\nvoid phydm_soml_reset_qam(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\tu8 order;\n\n\tfor (order = 0; order < HT_ORDER_TYPE; order++)\n\t\tsoml_tab->num_ht_qam[order] = 0;\n\n\tfor (order = 0; order < VHT_ORDER_TYPE; order++)\n\t\tsoml_tab->num_vht_qam[order] = 0;\n}\n\nvoid phydm_soml_cfo_process(void *dm_void, s32 *diff_a, s32 *diff_b)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 value32, value32_1, value32_2, value32_3;\n\ts32 cfo_acq_a, cfo_acq_b, cfo_end_a, cfo_end_b;\n\n\tvalue32 = odm_get_bb_reg(dm, R_0xd10, MASKDWORD);\n\tvalue32_1 = odm_get_bb_reg(dm, R_0xd14, MASKDWORD);\n\tvalue32_2 = odm_get_bb_reg(dm, R_0xd50, MASKDWORD);\n\tvalue32_3 = odm_get_bb_reg(dm, R_0xd54, MASKDWORD);\n\n\tcfo_acq_a = (s32)((value32 & 0x1fff0000) >> 16);\n\tcfo_end_a = (s32)((value32_1 & 0x1fff0000) >> 16);\n\tcfo_acq_b = (s32)((value32_2 & 0x1fff0000) >> 16);\n\tcfo_end_b = (s32)((value32_3 & 0x1fff0000) >> 16);\n\n\t*diff_a = ((cfo_acq_a >= cfo_end_a) ? (cfo_acq_a - cfo_end_a) :\n\t\t  (cfo_end_a - cfo_acq_a));\n\t*diff_b = ((cfo_acq_b >= cfo_end_b) ? (cfo_acq_b - cfo_end_b) :\n\t\t  (cfo_end_b - cfo_acq_b));\n\n\t*diff_a = ((*diff_a * 312) + (*diff_a >> 1)) >> 12; /* @312.5/2^12 */\n\t*diff_b = ((*diff_b * 312) + (*diff_b >> 1)) >> 12; /* @312.5/2^12 */\n}\n\nvoid phydm_soml_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t      char *output, u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\tu32 used = *_used;\n\tu32 out_len = *_out_len;\n\tu32 dm_value[10] = {0};\n\tu8 i = 0, input_idx = 0;\n\n\tfor (i = 0; i < 5; i++) {\n\t\tif (input[i + 1]) {\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);\n\t\t\tinput_idx++;\n\t\t}\n\t}\n\n\tif (input_idx == 0)\n\t\treturn;\n\n\tif (dm_value[0] == 1) { /*Turn on/off SOML*/\n\t\tsoml_tab->soml_select = (u8)dm_value[1];\n\n\t} else if (dm_value[0] == 2) { /*training number for SOML*/\n\n\t\tsoml_tab->soml_train_num = (u8)dm_value[1];\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"soml_train_num = ((%d))\\n\",\n\t\t\t soml_tab->soml_train_num);\n\t} else if (dm_value[0] == 3) { /*training interval for SOML*/\n\n\t\tsoml_tab->soml_intvl = (u8)dm_value[1];\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"soml_intvl = ((%d))\\n\", soml_tab->soml_intvl);\n\t} else if (dm_value[0] == 4) { /*@function period for SOML*/\n\n\t\tsoml_tab->soml_period = (u8)dm_value[1];\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"soml_period = ((%d))\\n\", soml_tab->soml_period);\n\t} else if (dm_value[0] == 5) { /*@delay_time for SOML*/\n\n\t\tsoml_tab->soml_delay_time = (u8)dm_value[1];\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"soml_delay_time = ((%d))\\n\",\n\t\t\t soml_tab->soml_delay_time);\n\t} else if (dm_value[0] == 6) { /* @for SOML Rx QAM distribution th*/\n\t\tif (dm_value[1] == 256) {\n\t\t\tsoml_tab->qam256_dist_th = (u8)dm_value[2];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"qam256_dist_th = ((%d))\\n\",\n\t\t\t\t soml_tab->qam256_dist_th);\n\t\t} else if (dm_value[1] == 64) {\n\t\t\tsoml_tab->qam64_dist_th = (u8)dm_value[2];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"qam64_dist_th = ((%d))\\n\",\n\t\t\t\t soml_tab->qam64_dist_th);\n\t\t} else if (dm_value[1] == 16) {\n\t\t\tsoml_tab->qam16_dist_th = (u8)dm_value[2];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"qam16_dist_th = ((%d))\\n\",\n\t\t\t\t soml_tab->qam16_dist_th);\n\t\t} else if (dm_value[1] == 4) {\n\t\t\tsoml_tab->bpsk_qpsk_dist_th = (u8)dm_value[2];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"bpsk_qpsk_dist_th = ((%d))\\n\",\n\t\t\t\t soml_tab->bpsk_qpsk_dist_th);\n\t\t}\n\t} else if (dm_value[0] == 7) { /* @for SOML cfo th*/\n\t\tif (dm_value[1] == 256) {\n\t\t\tsoml_tab->cfo_qam256_th = (u8)dm_value[2];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"cfo_qam256_th = ((%d KHz))\\n\",\n\t\t\t\t soml_tab->cfo_qam256_th);\n\t\t} else if (dm_value[1] == 64) {\n\t\t\tsoml_tab->cfo_qam64_th = (u8)dm_value[2];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"cfo_qam64_th = ((%d KHz))\\n\",\n\t\t\t\t soml_tab->cfo_qam64_th);\n\t\t} else if (dm_value[1] == 16) {\n\t\t\tsoml_tab->cfo_qam16_th = (u8)dm_value[2];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"cfo_qam16_th = ((%d KHz))\\n\",\n\t\t\t\t soml_tab->cfo_qam16_th);\n\t\t} else if (dm_value[1] == 4) {\n\t\t\tsoml_tab->cfo_qpsk_th = (u8)dm_value[2];\n\t\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t\t \"cfo_qpsk_th = ((%d KHz))\\n\",\n\t\t\t\t soml_tab->cfo_qpsk_th);\n\t\t}\n\t} else if (dm_value[0] == 100) {\n\t\t/*show parameters*/\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"soml_select = ((%d))\\n\", soml_tab->soml_select);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"soml_train_num = ((%d))\\n\",\n\t\t\t soml_tab->soml_train_num);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"soml_intvl = ((%d))\\n\", soml_tab->soml_intvl);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"soml_period = ((%d))\\n\", soml_tab->soml_period);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"soml_delay_time = ((%d))\\n\\n\",\n\t\t\t soml_tab->soml_delay_time);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"qam256_dist_th = ((%d)),  qam64_dist_th = ((%d)), \",\n\t\t\t soml_tab->qam256_dist_th,\n\t\t\t soml_tab->qam64_dist_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"qam16_dist_th = ((%d)),  bpsk_qpsk_dist_th = ((%d))\\n\",\n\t\t\t soml_tab->qam16_dist_th,\n\t\t\t soml_tab->bpsk_qpsk_dist_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"cfo_qam256_th = ((%d KHz)),  cfo_qam64_th = ((%d KHz)), \",\n\t\t\t soml_tab->cfo_qam256_th,\n\t\t\t soml_tab->cfo_qam64_th);\n\t\tPDM_SNPF(out_len, used, output + used, out_len - used,\n\t\t\t \"cfo_qam16_th = ((%d KHz)),  cfo_qpsk_th  = ((%d KHz))\\n\",\n\t\t\t soml_tab->cfo_qam16_th,\n\t\t\t soml_tab->cfo_qpsk_th);\n\t}\n\t*_used = used;\n\t*_out_len = out_len;\n}\n\nvoid phydm_soml_stats_ht_on(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\tu8 i, mcs0;\n\tu16 num_bytes_diff, num_rate_diff;\n\n\tmcs0 = ODM_RATEMCS0;\n\tfor (i = mcs0; i <= ODM_RATEMCS15; i++) {\n\t\tnum_rate_diff = soml_tab->ht_cnt[i - mcs0] -\n\t\t\t\tsoml_tab->pre_ht_cnt[i - mcs0];\n\t\tsoml_tab->ht_cnt_on[i - mcs0] += num_rate_diff;\n\t\tsoml_tab->pre_ht_cnt[i - mcs0] = soml_tab->ht_cnt[i - mcs0];\n\t\tnum_bytes_diff = soml_tab->ht_byte[i - mcs0] -\n\t\t\t\t soml_tab->pre_ht_byte[i - mcs0];\n\t\tsoml_tab->ht_byte_on[i - mcs0] += num_bytes_diff;\n\t\tsoml_tab->pre_ht_byte[i - mcs0] = soml_tab->ht_byte[i - mcs0];\n\t}\n}\n\nvoid phydm_soml_stats_ht_off(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\tu8 i, mcs0;\n\tu16 num_bytes_diff, num_rate_diff;\n\n\tmcs0 = ODM_RATEMCS0;\n\tfor (i = mcs0; i <= ODM_RATEMCS15; i++) {\n\t\tnum_rate_diff = soml_tab->ht_cnt[i - mcs0] -\n\t\t\t\tsoml_tab->pre_ht_cnt[i - mcs0];\n\t\tsoml_tab->ht_cnt_off[i - mcs0] += num_rate_diff;\n\t\tsoml_tab->pre_ht_cnt[i - mcs0] = soml_tab->ht_cnt[i - mcs0];\n\t\tnum_bytes_diff = soml_tab->ht_byte[i - mcs0] -\n\t\t\t\t soml_tab->pre_ht_byte[i - mcs0];\n\t\tsoml_tab->ht_byte_off[i - mcs0] += num_bytes_diff;\n\t\tsoml_tab->pre_ht_byte[i - mcs0] = soml_tab->ht_byte[i - mcs0];\n\t}\n}\n\nvoid phydm_soml_stats_vht_on(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\tu8 j, vht0;\n\tu16 num_bytes_diff, num_rate_diff;\n\n\tvht0 = ODM_RATEVHTSS1MCS0;\n\tfor (j = vht0; j <= ODM_RATEVHTSS2MCS9; j++) {\n\t\tnum_rate_diff = soml_tab->vht_cnt[j - vht0] -\n\t\t\t\tsoml_tab->pre_vht_cnt[j - vht0];\n\t\tsoml_tab->vht_cnt_on[j - vht0] += num_rate_diff;\n\t\tsoml_tab->pre_vht_cnt[j - vht0] = soml_tab->vht_cnt[j - vht0];\n\t\tnum_bytes_diff = soml_tab->vht_byte[j - vht0] -\n\t\t\t\t soml_tab->pre_vht_byte[j - vht0];\n\t\tsoml_tab->vht_byte_on[j - vht0] += num_bytes_diff;\n\t\tsoml_tab->pre_vht_byte[j - vht0] = soml_tab->vht_byte[j - vht0];\n\t}\n}\n\nvoid phydm_soml_stats_vht_off(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\tu8 j, vht0;\n\tu16 num_bytes_diff, num_rate_diff;\n\n\tvht0 = ODM_RATEVHTSS1MCS0;\n\tfor (j = vht0; j <= ODM_RATEVHTSS2MCS9; j++) {\n\t\tnum_rate_diff = soml_tab->vht_cnt[j - vht0] -\n\t\t\t\tsoml_tab->pre_vht_cnt[j - vht0];\n\t\tsoml_tab->vht_cnt_off[j - vht0] += num_rate_diff;\n\t\tsoml_tab->pre_vht_cnt[j - vht0] = soml_tab->vht_cnt[j - vht0];\n\t\tnum_bytes_diff = soml_tab->vht_byte[j - vht0] -\n\t\t\t\t soml_tab->pre_vht_byte[j - vht0];\n\t\tsoml_tab->vht_byte_off[j - vht0] += num_bytes_diff;\n\t\tsoml_tab->pre_vht_byte[j - vht0] = soml_tab->vht_byte[j - vht0];\n\t}\n}\n\nvoid phydm_soml_statistics(void *dm_void, u8 on_off_state)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\n\tif (on_off_state == SOML_ON) {\n\t\tif (*dm->channel <= 14)\n\t\t\tphydm_soml_stats_ht_on(dm);\n\t\tif (dm->support_ic_type == ODM_RTL8822B)\n\t\t\tphydm_soml_stats_vht_on(dm);\n\t} else if (on_off_state == SOML_OFF) {\n\t\tif (*dm->channel <= 14)\n\t\t\tphydm_soml_stats_ht_off(dm);\n\t\tif (dm->support_ic_type == ODM_RTL8822B)\n\t\t\tphydm_soml_stats_vht_off(dm);\n\t}\n}\n\nvoid phydm_adsl_init_state(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\n\tu8 next_on_off;\n\tu16 ht_reset[HT_RATE_IDX] = {0}, vht_reset[VHT_RATE_IDX] = {0};\n\tu8 size = sizeof(ht_reset[0]);\n\n\tphydm_soml_reset_rx_rate(dm);\n\todm_move_memory(dm, soml_tab->ht_byte, ht_reset,\n\t\t\tHT_RATE_IDX * size);\n\todm_move_memory(dm, soml_tab->ht_byte_on, ht_reset,\n\t\t\tHT_RATE_IDX * size);\n\todm_move_memory(dm, soml_tab->ht_byte_off, ht_reset,\n\t\t\tHT_RATE_IDX * size);\n\todm_move_memory(dm, soml_tab->vht_byte, vht_reset,\n\t\t\tVHT_RATE_IDX * size);\n\todm_move_memory(dm, soml_tab->vht_byte_on, vht_reset,\n\t\t\tVHT_RATE_IDX * size);\n\todm_move_memory(dm, soml_tab->vht_byte_off, vht_reset,\n\t\t\tVHT_RATE_IDX * size);\n\tif (dm->support_ic_type == ODM_RTL8822B) {\n\t\tsoml_tab->cfo_cnt++;\n\t\tphydm_soml_cfo_process(dm,\n\t\t\t\t       &soml_tab->cfo_diff_a,\n\t\t\t\t       &soml_tab->cfo_diff_b);\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t  \"[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\\n\",\n\t\t\t  soml_tab->cfo_cnt, soml_tab->cfo_diff_a,\n\t\t\t  soml_tab->cfo_diff_b);\n\t\tsoml_tab->cfo_diff_sum_a += soml_tab->cfo_diff_a;\n\t\tsoml_tab->cfo_diff_sum_b += soml_tab->cfo_diff_b;\n\t}\n\n\tsoml_tab->is_soml_method_enable = 1;\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\todm_set_mac_reg(dm, R_0x608, BIT(8), 1);\n\t/*RCR accepts CRC32-Error packets*/\n\t#endif\n\tsoml_tab->get_stats = false;\n\tsoml_tab->soml_state_cnt++;\n\tnext_on_off = (soml_tab->soml_on_off == SOML_ON) ? SOML_ON : SOML_OFF;\n\tphydm_soml_on_off(dm, next_on_off);\n\todm_set_timer(dm, &soml_tab->phydm_adaptive_soml_timer,\n\t\t      soml_tab->soml_delay_time); /*@ms*/\n}\n\nvoid phydm_adsl_odd_state(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\tu16 ht_reset[HT_RATE_IDX] = {0}, vht_reset[VHT_RATE_IDX] = {0};\n\tu8 size = sizeof(ht_reset[0]);\n\n\tsoml_tab->get_stats = true;\n\tsoml_tab->soml_state_cnt++;\n\todm_move_memory(dm, soml_tab->pre_ht_cnt, soml_tab->ht_cnt,\n\t\t\tHT_RATE_IDX * size);\n\todm_move_memory(dm, soml_tab->pre_vht_cnt, soml_tab->vht_cnt,\n\t\t\tVHT_RATE_IDX * size);\n\todm_move_memory(dm, soml_tab->pre_ht_byte, soml_tab->ht_byte,\n\t\t\tHT_RATE_IDX * size);\n\todm_move_memory(dm, soml_tab->pre_vht_byte, soml_tab->vht_byte,\n\t\t\tVHT_RATE_IDX * size);\n\n\tif (dm->support_ic_type == ODM_RTL8822B) {\n\t\tsoml_tab->cfo_cnt++;\n\t\tphydm_soml_cfo_process(dm,\n\t\t\t\t       &soml_tab->cfo_diff_a,\n\t\t\t\t       &soml_tab->cfo_diff_b);\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t  \"[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\\n\",\n\t\t\t  soml_tab->cfo_cnt, soml_tab->cfo_diff_a,\n\t\t\t  soml_tab->cfo_diff_b);\n\t\tsoml_tab->cfo_diff_sum_a += soml_tab->cfo_diff_a;\n\t\tsoml_tab->cfo_diff_sum_b += soml_tab->cfo_diff_b;\n\t}\n\todm_set_timer(dm, &soml_tab->phydm_adaptive_soml_timer,\n\t\t      soml_tab->soml_intvl); /*@ms*/\n}\n\nvoid phydm_adsl_even_state(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\tu8 next_on_off;\n\n\tsoml_tab->get_stats = false;\n\tif (dm->support_ic_type == ODM_RTL8822B) {\n\t\tsoml_tab->cfo_cnt++;\n\t\tphydm_soml_cfo_process(dm,\n\t\t\t\t       &soml_tab->cfo_diff_a,\n\t\t\t\t       &soml_tab->cfo_diff_b);\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t  \"[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\\n\",\n\t\t\t  soml_tab->cfo_cnt, soml_tab->cfo_diff_a,\n\t\t\t  soml_tab->cfo_diff_b);\n\t\tsoml_tab->cfo_diff_sum_a += soml_tab->cfo_diff_a;\n\t\tsoml_tab->cfo_diff_sum_b += soml_tab->cfo_diff_b;\n\t}\n\tsoml_tab->soml_state_cnt++;\n\tphydm_soml_statistics(dm, soml_tab->soml_on_off);\n\tnext_on_off = (soml_tab->soml_on_off == SOML_ON) ? SOML_OFF : SOML_ON;\n\tphydm_soml_on_off(dm, next_on_off);\n\todm_set_timer(dm, &soml_tab->phydm_adaptive_soml_timer,\n\t\t      soml_tab->soml_delay_time); /*@ms*/\n}\n\nvoid phydm_adsl_decision_state(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\tboolean on_above = false, off_above = false;\n\tu8 i, max_idx_on = 0, max_idx_off = 0;\n\tu8 next_on_off = soml_tab->soml_last_state;\n\tu8 mcs0 = ODM_RATEMCS0, vht0 = ODM_RATEVHTSS1MCS0;\n\tu8 crc_taget = soml_tab->soml_last_state;\n\tu8 rate_num = 1, ss_shift = 0;\n\tu16 ht_ok_max_on = 0, ht_fail_max_on = 0, utility_on = 0;\n\tu16 ht_ok_max_off = 0, ht_fail_max_off = 0, utility_off = 0;\n\tu16 vht_ok_max_on = 0, vht_fail_max_on = 0;\n\tu16 vht_ok_max_off = 0, vht_fail_max_off = 0;\n\tu16 num_total_qam = 0;\n\tu16 cnt_max_on = 0, cnt_max_off = 0;\n\tu32 ht_total_cnt_on = 0, ht_total_cnt_off = 0;\n\tu32 total_ht_rate_on = 0, total_ht_rate_off = 0;\n\tu32 vht_total_cnt_on = 0, vht_total_cnt_off = 0;\n\tu32 total_vht_rate_on = 0, total_vht_rate_off = 0;\n\tu32 rate_per_pkt_on = 0, rate_per_pkt_off = 0;\n\ts32 cfo_diff_avg_a, cfo_diff_avg_b;\n\tu16 vht_phy_rate_table[] = {\n\t\t/*@20M*/\n\t\t6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1SS MCS0~9*/\n\t\t13, 26, 39, 52, 78, 104, 117, 130, 156, 180 /*@2SSMCS0~9*/\n\t};\n\n\tif (dm->support_ic_type & ODM_IC_1SS)\n\t\trate_num = 1;\n\t#ifdef PHYDM_COMPILE_ABOVE_2SS\n\telse if (dm->support_ic_type & ODM_IC_2SS)\n\t\trate_num = 2;\n\t#endif\n\t#ifdef PHYDM_COMPILE_ABOVE_3SS\n\telse if (dm->support_ic_type & ODM_IC_3SS)\n\t\trate_num = 3;\n\t#endif\n\t#ifdef PHYDM_COMPILE_ABOVE_4SS\n\telse if (dm->support_ic_type & ODM_IC_4SS)\n\t\trate_num = 4;\n\t#endif\n\telse\n\t\tpr_debug(\"%s: mismatch IC type %x\\n\", __func__,\n\t\t\t dm->support_ic_type);\n\tsoml_tab->get_stats = false;\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\todm_set_mac_reg(dm, R_0x608, BIT(8), 0);\n\t/* NOT Accept CRC32 Error packets. */\n\t#endif\n\tPHYDM_DBG(dm, DBG_ADPTV_SOML, \"[Decisoin state ]\\n\");\n\tphydm_soml_statistics(dm, soml_tab->soml_on_off);\n\tif (*dm->channel <= 14) {\n\t\t/* @[Search 1st and 2nd rate by counter] */\n\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\tss_shift = (i << 3);\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t\t  \"*ht_cnt_on  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t\t\t  (ss_shift), (ss_shift + 7),\n\t\t\t\t  soml_tab->ht_cnt_on[ss_shift + 0],\n\t\t\t\t  soml_tab->ht_cnt_on[ss_shift + 1],\n\t\t\t\t  soml_tab->ht_cnt_on[ss_shift + 2],\n\t\t\t\t  soml_tab->ht_cnt_on[ss_shift + 3],\n\t\t\t\t  soml_tab->ht_cnt_on[ss_shift + 4],\n\t\t\t\t  soml_tab->ht_cnt_on[ss_shift + 5],\n\t\t\t\t  soml_tab->ht_cnt_on[ss_shift + 6],\n\t\t\t\t  soml_tab->ht_cnt_on[ss_shift + 7]);\n\t\t}\n\n\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\tss_shift = (i << 3);\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t\t  \"*ht_cnt_off  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t\t\t  (ss_shift), (ss_shift + 7),\n\t\t\t\t  soml_tab->ht_cnt_off[ss_shift + 0],\n\t\t\t\t  soml_tab->ht_cnt_off[ss_shift + 1],\n\t\t\t\t  soml_tab->ht_cnt_off[ss_shift + 2],\n\t\t\t\t  soml_tab->ht_cnt_off[ss_shift + 3],\n\t\t\t\t  soml_tab->ht_cnt_off[ss_shift + 4],\n\t\t\t\t  soml_tab->ht_cnt_off[ss_shift + 5],\n\t\t\t\t  soml_tab->ht_cnt_off[ss_shift + 6],\n\t\t\t\t  soml_tab->ht_cnt_off[ss_shift + 7]);\n\t\t}\n\n\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\tss_shift = (i << 3);\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t\t  \"*ht_crc_ok_cnt_on  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t\t\t  (ss_shift), (ss_shift + 7),\n\t\t\t\t  soml_tab->ht_crc_ok_cnt_on[ss_shift + 0],\n\t\t\t\t  soml_tab->ht_crc_ok_cnt_on[ss_shift + 1],\n\t\t\t\t  soml_tab->ht_crc_ok_cnt_on[ss_shift + 2],\n\t\t\t\t  soml_tab->ht_crc_ok_cnt_on[ss_shift + 3],\n\t\t\t\t  soml_tab->ht_crc_ok_cnt_on[ss_shift + 4],\n\t\t\t\t  soml_tab->ht_crc_ok_cnt_on[ss_shift + 5],\n\t\t\t\t  soml_tab->ht_crc_ok_cnt_on[ss_shift + 6],\n\t\t\t\t  soml_tab->ht_crc_ok_cnt_on[ss_shift + 7]);\n\t\t}\n\n\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\tss_shift = (i << 3);\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t\t  \"*ht_crc_fail_cnt_on  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t\t\t  (ss_shift), (ss_shift + 7),\n\t\t\t\t  soml_tab->ht_crc_fail_cnt_on[ss_shift + 0],\n\t\t\t\t  soml_tab->ht_crc_fail_cnt_on[ss_shift + 1],\n\t\t\t\t  soml_tab->ht_crc_fail_cnt_on[ss_shift + 2],\n\t\t\t\t  soml_tab->ht_crc_fail_cnt_on[ss_shift + 3],\n\t\t\t\t  soml_tab->ht_crc_fail_cnt_on[ss_shift + 4],\n\t\t\t\t  soml_tab->ht_crc_fail_cnt_on[ss_shift + 5],\n\t\t\t\t  soml_tab->ht_crc_fail_cnt_on[ss_shift + 6],\n\t\t\t\t  soml_tab->ht_crc_fail_cnt_on[ss_shift + 7]);\n\t\t}\n\n\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\tss_shift = (i << 3);\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t\t  \"*ht_crc_ok_cnt_off  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t\t\t  (ss_shift), (ss_shift + 7),\n\t\t\t\t  soml_tab->ht_crc_ok_cnt_off[ss_shift + 0],\n\t\t\t\t  soml_tab->ht_crc_ok_cnt_off[ss_shift + 1],\n\t\t\t\t  soml_tab->ht_crc_ok_cnt_off[ss_shift + 2],\n\t\t\t\t  soml_tab->ht_crc_ok_cnt_off[ss_shift + 3],\n\t\t\t\t  soml_tab->ht_crc_ok_cnt_off[ss_shift + 4],\n\t\t\t\t  soml_tab->ht_crc_ok_cnt_off[ss_shift + 5],\n\t\t\t\t  soml_tab->ht_crc_ok_cnt_off[ss_shift + 6],\n\t\t\t\t  soml_tab->ht_crc_ok_cnt_off[ss_shift + 7]);\n\t\t}\n\n\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\tss_shift = (i << 3);\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t\t  \"*ht_crc_fail_cnt_off  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t\t\t  (ss_shift), (ss_shift + 7),\n\t\t\t\t  soml_tab->ht_crc_fail_cnt_off[ss_shift + 0],\n\t\t\t\t  soml_tab->ht_crc_fail_cnt_off[ss_shift + 1],\n\t\t\t\t  soml_tab->ht_crc_fail_cnt_off[ss_shift + 2],\n\t\t\t\t  soml_tab->ht_crc_fail_cnt_off[ss_shift + 3],\n\t\t\t\t  soml_tab->ht_crc_fail_cnt_off[ss_shift + 4],\n\t\t\t\t  soml_tab->ht_crc_fail_cnt_off[ss_shift + 5],\n\t\t\t\t  soml_tab->ht_crc_fail_cnt_off[ss_shift + 6],\n\t\t\t\t  soml_tab->ht_crc_fail_cnt_off[ss_shift + 7]);\n\t\t}\n\t\tfor (i = ODM_RATEMCS0; i <= ODM_RATEMCS15; i++) {\n\t\t\tht_total_cnt_on += soml_tab->ht_cnt_on[i - mcs0];\n\t\t\tht_total_cnt_off += soml_tab->ht_cnt_off[i - mcs0];\n\t\t\ttotal_ht_rate_on += (soml_tab->ht_cnt_on[i - mcs0] *\n\t\t\t\t\t    phy_rate_table[i]);\n\t\t\ttotal_ht_rate_off += (soml_tab->ht_cnt_off[i - mcs0] *\n\t\t\t\t\t     phy_rate_table[i]);\n\t\t\tif (soml_tab->ht_cnt_on[i - mcs0] > cnt_max_on) {\n\t\t\t\tcnt_max_on = soml_tab->ht_cnt_on[i - mcs0];\n\t\t\t\tmax_idx_on = i - mcs0;\n\t\t\t}\n\n\t\t\tif (soml_tab->ht_cnt_off[i - mcs0] > cnt_max_off) {\n\t\t\t\tcnt_max_off = soml_tab->ht_cnt_off[i - mcs0];\n\t\t\t\tmax_idx_off = i - mcs0;\n\t\t\t}\n\t\t}\n\t\ttotal_ht_rate_on = total_ht_rate_on << 3;\n\t\ttotal_ht_rate_off = total_ht_rate_off << 3;\n\t\trate_per_pkt_on = (ht_total_cnt_on != 0) ?\n\t\t\t\t  (total_ht_rate_on / ht_total_cnt_on) : 0;\n\t\trate_per_pkt_off = (ht_total_cnt_off != 0) ?\n\t\t\t\t   (total_ht_rate_off / ht_total_cnt_off) : 0;\n\t\t#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t\tht_ok_max_on = soml_tab->ht_crc_ok_cnt_on[max_idx_on];\n\t\tht_fail_max_on = soml_tab->ht_crc_fail_cnt_on[max_idx_on];\n\t\tht_ok_max_off = soml_tab->ht_crc_ok_cnt_off[max_idx_off];\n\t\tht_fail_max_off = soml_tab->ht_crc_fail_cnt_off[max_idx_off];\n\n\t\tif (ht_fail_max_on == 0)\n\t\t\tht_fail_max_on = 1;\n\n\t\tif (ht_fail_max_off == 0)\n\t\t\tht_fail_max_off = 1;\n\n\t\tif (ht_ok_max_on > ht_fail_max_on)\n\t\t\ton_above = true;\n\n\t\tif (ht_ok_max_off > ht_fail_max_off)\n\t\t\toff_above = true;\n\n\t\tif (on_above && !off_above) {\n\t\t\tcrc_taget = SOML_ON;\n\t\t} else if (!on_above && off_above) {\n\t\t\tcrc_taget = SOML_OFF;\n\t\t} else if (on_above && off_above) {\n\t\t\tutility_on = (ht_ok_max_on << 7) / ht_fail_max_on;\n\t\t\tutility_off = (ht_ok_max_off << 7) / ht_fail_max_off;\n\t\t\tcrc_taget = (utility_on == utility_off) ?\n\t\t\t\t    (soml_tab->soml_last_state) :\n\t\t\t\t    ((utility_on > utility_off) ? SOML_ON :\n\t\t\t\t    SOML_OFF);\n\n\t\t} else if (!on_above && !off_above) {\n\t\t\tif (ht_ok_max_on == 0)\n\t\t\t\tht_ok_max_on = 1;\n\t\t\tif (ht_ok_max_off == 0)\n\t\t\t\tht_ok_max_off = 1;\n\t\t\tutility_on = (ht_fail_max_on << 7) / ht_ok_max_on;\n\t\t\tutility_off = (ht_fail_max_off << 7) / ht_ok_max_off;\n\t\t\tcrc_taget = (utility_on == utility_off) ?\n\t\t\t\t    (soml_tab->soml_last_state) :\n\t\t\t\t    ((utility_on < utility_off) ? SOML_ON :\n\t\t\t\t    SOML_OFF);\n\t\t}\n\t\t#endif\n\t} else if (dm->support_ic_type == ODM_RTL8822B) {\n\t\tcfo_diff_avg_a = soml_tab->cfo_diff_sum_a / soml_tab->cfo_cnt;\n\t\tcfo_diff_avg_b = soml_tab->cfo_diff_sum_b / soml_tab->cfo_cnt;\n\t\tsoml_tab->cfo_diff_avg_a = (soml_tab->cfo_cnt != 0) ?\n\t\t\t\t\t   cfo_diff_avg_a : 0;\n\t\tsoml_tab->cfo_diff_avg_b = (soml_tab->cfo_cnt != 0) ?\n\t\t\t\t\t   cfo_diff_avg_b : 0;\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t  \"[ cfo_diff_avg_a = %d KHz; cfo_diff_avg_b = %d KHz]\\n\",\n\t\t\t  soml_tab->cfo_diff_avg_a,\n\t\t\t  soml_tab->cfo_diff_avg_b);\n\t\tfor (i = 0; i < VHT_ORDER_TYPE; i++)\n\t\t\tnum_total_qam += soml_tab->num_vht_qam[i];\n\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t  \"[ ((2SS)) BPSK_QPSK_count = %d ; 16QAM_count = %d ; 64QAM_count = %d ; 256QAM_count = %d ; num_total_qam = %d]\\n\",\n\t\t\t  soml_tab->num_vht_qam[BPSK_QPSK],\n\t\t\t  soml_tab->num_vht_qam[QAM16],\n\t\t\t  soml_tab->num_vht_qam[QAM64],\n\t\t\t  soml_tab->num_vht_qam[QAM256],\n\t\t\t  num_total_qam);\n\t\tif (((soml_tab->num_vht_qam[QAM256] * 100) >\n\t\t    (num_total_qam * soml_tab->qam256_dist_th)) &&\n\t\t    cfo_diff_avg_a > soml_tab->cfo_qam256_th &&\n\t\t    cfo_diff_avg_b > soml_tab->cfo_qam256_th) {\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t\t  \"[  QAM256_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\\n\",\n\t\t\t\t  soml_tab->qam256_dist_th,\n\t\t\t\t  soml_tab->cfo_qam256_th);\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML, \"[ Final decisoin ] : \");\n\t\t\tphydm_soml_on_off(dm, SOML_OFF);\n\t\t\treturn;\n\t\t} else if (((soml_tab->num_vht_qam[QAM64] * 100) >\n\t\t\t   (num_total_qam * soml_tab->qam64_dist_th)) &&\n\t\t\t   (cfo_diff_avg_a > soml_tab->cfo_qam64_th) &&\n\t\t\t   (cfo_diff_avg_b > soml_tab->cfo_qam64_th)) {\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t\t  \"[  QAM64_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\\n\",\n\t\t\t\t  soml_tab->qam64_dist_th,\n\t\t\t\t  soml_tab->cfo_qam64_th);\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML, \"[ Final decisoin ] : \");\n\t\t\tphydm_soml_on_off(dm, SOML_OFF);\n\t\t\treturn;\n\t\t} else if (((soml_tab->num_vht_qam[QAM16] * 100) >\n\t\t\t   (num_total_qam * soml_tab->qam16_dist_th)) &&\n\t\t\t   (cfo_diff_avg_a > soml_tab->cfo_qam16_th) &&\n\t\t\t   (cfo_diff_avg_b > soml_tab->cfo_qam16_th)) {\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t\t  \"[  QAM16_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\\n\",\n\t\t\t\t  soml_tab->qam16_dist_th,\n\t\t\t\t  soml_tab->cfo_qam16_th);\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML, \"[ Final decisoin ] : \");\n\t\t\tphydm_soml_on_off(dm, SOML_OFF);\n\t\t\treturn;\n\t\t} else if (((soml_tab->num_vht_qam[BPSK_QPSK] * 100) >\n\t\t\t   (num_total_qam * soml_tab->bpsk_qpsk_dist_th)) &&\n\t\t\t   (cfo_diff_avg_a > soml_tab->cfo_qpsk_th) &&\n\t\t\t   (cfo_diff_avg_b > soml_tab->cfo_qpsk_th)) {\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t\t  \"[  BPSK_QPSK_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\\n\",\n\t\t\t\t  soml_tab->bpsk_qpsk_dist_th,\n\t\t\t\t  soml_tab->cfo_qpsk_th);\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML, \"[ Final decisoin ] : \");\n\t\t\tphydm_soml_on_off(dm, SOML_OFF);\n\t\t\treturn;\n\t\t}\n\n\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\tss_shift = 10 * i;\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t\t  \"[  vht_cnt_on  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\\n\",\n\t\t\t\t  (i + 1),\n\t\t\t\t  soml_tab->vht_cnt_on[ss_shift + 0],\n\t\t\t\t  soml_tab->vht_cnt_on[ss_shift + 1],\n\t\t\t\t  soml_tab->vht_cnt_on[ss_shift + 2],\n\t\t\t\t  soml_tab->vht_cnt_on[ss_shift + 3],\n\t\t\t\t  soml_tab->vht_cnt_on[ss_shift + 4],\n\t\t\t\t  soml_tab->vht_cnt_on[ss_shift + 5],\n\t\t\t\t  soml_tab->vht_cnt_on[ss_shift + 6],\n\t\t\t\t  soml_tab->vht_cnt_on[ss_shift + 7],\n\t\t\t\t  soml_tab->vht_cnt_on[ss_shift + 8],\n\t\t\t\t  soml_tab->vht_cnt_on[ss_shift + 9]);\n\t\t}\n\n\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\tss_shift = 10 * i;\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t\t  \"[  vht_cnt_off  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\\n\",\n\t\t\t\t  (i + 1),\n\t\t\t\t  soml_tab->vht_cnt_off[ss_shift + 0],\n\t\t\t\t  soml_tab->vht_cnt_off[ss_shift + 1],\n\t\t\t\t  soml_tab->vht_cnt_off[ss_shift + 2],\n\t\t\t\t  soml_tab->vht_cnt_off[ss_shift + 3],\n\t\t\t\t  soml_tab->vht_cnt_off[ss_shift + 4],\n\t\t\t\t  soml_tab->vht_cnt_off[ss_shift + 5],\n\t\t\t\t  soml_tab->vht_cnt_off[ss_shift + 6],\n\t\t\t\t  soml_tab->vht_cnt_off[ss_shift + 7],\n\t\t\t\t  soml_tab->vht_cnt_off[ss_shift + 8],\n\t\t\t\t  soml_tab->vht_cnt_off[ss_shift + 9]);\n\t\t}\n\n\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\tss_shift = 10 * i;\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t\t  \"*vht_crc_ok_cnt_on  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t\t\t  (i + 1),\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_on[ss_shift + 0],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_on[ss_shift + 1],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_on[ss_shift + 2],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_on[ss_shift + 3],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_on[ss_shift + 4],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_on[ss_shift + 5],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_on[ss_shift + 6],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_on[ss_shift + 7],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_on[ss_shift + 8],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_on[ss_shift + 9]);\n\t\t}\n\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\tss_shift = 10 * i;\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t\t  \"*vht_crc_fail_cnt_on  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t\t\t  (i + 1),\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_on[ss_shift + 0],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_on[ss_shift + 1],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_on[ss_shift + 2],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_on[ss_shift + 3],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_on[ss_shift + 4],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_on[ss_shift + 5],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_on[ss_shift + 6],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_on[ss_shift + 7],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_on[ss_shift + 8],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_on[ss_shift + 9]);\n\t\t}\n\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\tss_shift = 10 * i;\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t\t  \"*vht_crc_ok_cnt_off  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t\t\t  (i + 1),\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_off[ss_shift + 0],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_off[ss_shift + 1],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_off[ss_shift + 2],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_off[ss_shift + 3],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_off[ss_shift + 4],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_off[ss_shift + 5],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_off[ss_shift + 6],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_off[ss_shift + 7],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_off[ss_shift + 8],\n\t\t\t\t  soml_tab->vht_crc_ok_cnt_off[ss_shift + 9]);\n\t\t}\n\t\tfor (i = 0; i < rate_num; i++) {\n\t\t\tss_shift = 10 * i;\n\t\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t\t  \"*vht_crc_fail_cnt_off  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\\n\",\n\t\t\t\t  (i + 1),\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_off[ss_shift + 0],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_off[ss_shift + 1],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_off[ss_shift + 2],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_off[ss_shift + 3],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_off[ss_shift + 4],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_off[ss_shift + 5],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_off[ss_shift + 6],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_off[ss_shift + 7],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_off[ss_shift + 8],\n\t\t\t\t  soml_tab->vht_crc_fail_cnt_off[ss_shift + 9]);\n\t\t}\n\n\t\tfor (i = ODM_RATEVHTSS2MCS0; i <= ODM_RATEVHTSS2MCS9; i++) {\n\t\t\tvht_total_cnt_on += soml_tab->vht_cnt_on[i - vht0];\n\t\t\tvht_total_cnt_off += soml_tab->vht_cnt_off[i - vht0];\n\t\t\ttotal_vht_rate_on += (soml_tab->vht_cnt_on[i - vht0] *\n\t\t\t\t\t     vht_phy_rate_table[i - vht0]);\n\t\t\ttotal_vht_rate_off += (soml_tab->vht_cnt_off[i - vht0] *\n\t\t\t\t\t      vht_phy_rate_table[i - vht0]);\n\n\t\t\tif (soml_tab->vht_cnt_on[i - vht0] > cnt_max_on) {\n\t\t\t\tcnt_max_on = soml_tab->vht_cnt_on[i - vht0];\n\t\t\t\tmax_idx_on = i - vht0;\n\t\t\t}\n\n\t\t\tif (soml_tab->vht_cnt_off[i - vht0] > cnt_max_off) {\n\t\t\t\tcnt_max_off = soml_tab->vht_cnt_off[i - vht0];\n\t\t\t\tmax_idx_off = i - vht0;\n\t\t\t}\n\t\t}\n\t\ttotal_vht_rate_on = total_vht_rate_on << 3;\n\t\ttotal_vht_rate_off = total_vht_rate_off << 3;\n\t\trate_per_pkt_on = (vht_total_cnt_on != 0) ?\n\t\t\t\t  (total_vht_rate_on / vht_total_cnt_on) : 0;\n\t\trate_per_pkt_off = (vht_total_cnt_off != 0) ?\n\t\t\t\t   (total_vht_rate_off / vht_total_cnt_off) : 0;\n\t\t#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t\tvht_ok_max_on = soml_tab->vht_crc_ok_cnt_on[max_idx_on];\n\t\tvht_fail_max_on = soml_tab->vht_crc_fail_cnt_on[max_idx_on];\n\t\tvht_ok_max_off = soml_tab->vht_crc_ok_cnt_off[max_idx_off];\n\t\tvht_fail_max_off = soml_tab->vht_crc_fail_cnt_off[max_idx_off];\n\n\t\tif (vht_fail_max_on == 0)\n\t\t\tvht_fail_max_on = 1;\n\n\t\tif (vht_fail_max_off == 0)\n\t\t\tvht_fail_max_off = 1;\n\n\t\tif (vht_ok_max_on > vht_fail_max_on)\n\t\t\ton_above = true;\n\n\t\tif (vht_ok_max_off > vht_fail_max_off)\n\t\t\toff_above = true;\n\n\t\tif (on_above && !off_above) {\n\t\t\tcrc_taget = SOML_ON;\n\t\t} else if (!on_above && off_above) {\n\t\t\tcrc_taget = SOML_OFF;\n\t\t} else if (on_above && off_above) {\n\t\t\tutility_on = (vht_ok_max_on << 7) / vht_fail_max_on;\n\t\t\tutility_off = (vht_ok_max_off << 7) / vht_fail_max_off;\n\t\t\tcrc_taget = (utility_on == utility_off) ?\n\t\t\t\t    (soml_tab->soml_last_state) :\n\t\t\t\t    ((utility_on > utility_off) ? SOML_ON :\n\t\t\t\t    SOML_OFF);\n\n\t\t} else if (!on_above && !off_above) {\n\t\t\tif (vht_ok_max_on == 0)\n\t\t\t\tvht_ok_max_on = 1;\n\t\t\tif (vht_ok_max_off == 0)\n\t\t\t\tvht_ok_max_off = 1;\n\t\t\tutility_on = (vht_fail_max_on << 7) / vht_ok_max_on;\n\t\t\tutility_off = (vht_fail_max_off << 7) / vht_ok_max_off;\n\t\t\tcrc_taget = (utility_on == utility_off) ?\n\t\t\t\t    (soml_tab->soml_last_state) :\n\t\t\t\t    ((utility_on < utility_off) ? SOML_ON :\n\t\t\t\t    SOML_OFF);\n\t\t}\n\t\t#endif\n\n\t}\n\n\t/* @[Decision] */\n\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t  \"[  rate_per_pkt_on = %d ; rate_per_pkt_off = %d ]\\n\",\n\t\t  rate_per_pkt_on, rate_per_pkt_off);\n\t#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\tif (max_idx_on == max_idx_off && max_idx_on != 0) {\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t  \"[ max_idx_on == max_idx_off ]\\n\");\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t  \"[ max_idx = %d, crc_utility_on = %d, crc_utility_off = %d, crc_target = %d]\\n\",\n\t\t\t  max_idx_on, utility_on, utility_off,\n\t\t\t  crc_taget);\n\t\tnext_on_off = crc_taget;\n\t} else\n\t#endif\n\tif (rate_per_pkt_on > rate_per_pkt_off) {\n\t\tnext_on_off = SOML_ON;\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t  \"[ rate_per_pkt_on > rate_per_pkt_off ==> SOML_ON ]\\n\");\n\t} else if (rate_per_pkt_on < rate_per_pkt_off) {\n\t\tnext_on_off = SOML_OFF;\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t  \"[ rate_per_pkt_on < rate_per_pkt_off ==> SOML_OFF ]\\n\");\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t  \"[ stay at soml_last_state ]\\n\");\n\t\tnext_on_off = soml_tab->soml_last_state;\n\t}\n\n\tPHYDM_DBG(dm, DBG_ADPTV_SOML, \"[ Final decisoin ] : \");\n\tphydm_soml_on_off(dm, next_on_off);\n\tsoml_tab->soml_last_state = next_on_off;\n}\n\nvoid phydm_adsl(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\n\tif (dm->support_ic_type & PHYDM_ADAPTIVE_SOML_IC) {\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML, \"soml_state_cnt =((%d))\\n\",\n\t\t\t  soml_tab->soml_state_cnt);\n\t\t/*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)===============*/\n\t\tif (soml_tab->soml_state_cnt <\n\t\t    (soml_tab->soml_train_num << 1)) {\n\t\t\tif (soml_tab->soml_state_cnt == 0)\n\t\t\t\tphydm_adsl_init_state(dm);\n\t\t\telse if ((soml_tab->soml_state_cnt % 2) != 0)\n\t\t\t\tphydm_adsl_odd_state(dm);\n\t\t\telse if ((soml_tab->soml_state_cnt % 2) == 0)\n\t\t\t\tphydm_adsl_even_state(dm);\n\t\t} else {\n\t\t\tphydm_adsl_decision_state(dm);\n\t\t}\n\t}\n}\n\nvoid phydm_adaptive_soml_reset(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\n\tsoml_tab->soml_state_cnt = 0;\n\tsoml_tab->is_soml_method_enable = 0;\n\tsoml_tab->soml_counter = 0;\n}\n\nvoid phydm_set_adsl_val(void *dm_void, u32 *val_buf, u8 val_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (val_len != 1) {\n\t\tPHYDM_DBG(dm, ODM_COMP_API, \"[Error][ADSL]Need val_len=1\\n\");\n\t\treturn;\n\t}\n\n\tphydm_soml_on_off(dm, (u8)val_buf[1]);\n}\n\nvoid phydm_soml_crc_acq(void *dm_void, u8 rate_id, boolean crc32, u32 length)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\tu8 offset = 0;\n\n\tif (!soml_tab->get_stats)\n\t\treturn;\n\tif (length < 1400)\n\t\treturn;\n\n\tif (soml_tab->soml_on_off == SOML_ON) {\n\t\tif (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS15) {\n\t\t\toffset = rate_id - ODM_RATEMCS0;\n\t\t\tif (crc32 == CRC_OK)\n\t\t\t\tsoml_tab->ht_crc_ok_cnt_on[offset]++;\n\t\t\telse if (crc32 == CRC_FAIL)\n\t\t\t\tsoml_tab->ht_crc_fail_cnt_on[offset]++;\n\t\t} else if (rate_id >= ODM_RATEVHTSS1MCS0 &&\n\t\t\t   rate_id <= ODM_RATEVHTSS2MCS9) {\n\t\t\toffset = rate_id - ODM_RATEVHTSS1MCS0;\n\t\t\tif (crc32 == CRC_OK)\n\t\t\t\tsoml_tab->vht_crc_ok_cnt_on[offset]++;\n\t\t\telse if (crc32 == CRC_FAIL)\n\t\t\t\tsoml_tab->vht_crc_fail_cnt_on[offset]++;\n\t\t}\n\t} else if (soml_tab->soml_on_off == SOML_OFF) {\n\t\tif (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS15) {\n\t\t\toffset = rate_id - ODM_RATEMCS0;\n\t\t\tif (crc32 == CRC_OK)\n\t\t\t\tsoml_tab->ht_crc_ok_cnt_off[offset]++;\n\t\t\telse if (crc32 == CRC_FAIL)\n\t\t\t\tsoml_tab->ht_crc_fail_cnt_off[offset]++;\n\t\t} else if (rate_id >= ODM_RATEVHTSS1MCS0 &&\n\t\t\t   rate_id <= ODM_RATEVHTSS2MCS9) {\n\t\t\toffset = rate_id - ODM_RATEVHTSS1MCS0;\n\t\t\tif (crc32 == CRC_OK)\n\t\t\t\tsoml_tab->vht_crc_ok_cnt_off[offset]++;\n\t\t\telse if (crc32 == CRC_FAIL)\n\t\t\t\tsoml_tab->vht_crc_fail_cnt_off[offset]++;\n\t\t}\n\t}\n}\n\nvoid phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\tu8 offset = 0;\n\n\n\tif (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS31) {\n\t\toffset = rate_id - ODM_RATEMCS0;\n\t\tif (offset > (HT_RATE_IDX - 1))\n\t\t\toffset = HT_RATE_IDX - 1;\n\n\t\tsoml_tab->ht_byte[offset] += (u16)length;\n\t} else if (rate_id >= ODM_RATEVHTSS1MCS0 &&\n\t\t   rate_id <= ODM_RATEVHTSS4MCS9) {\n\t\toffset = rate_id - ODM_RATEVHTSS1MCS0;\n\t\tif (offset > (VHT_RATE_IDX - 1))\n\t\t\toffset = VHT_RATE_IDX - 1;\n\n\t\tsoml_tab->vht_byte[offset] += (u16)length;\n\t}\n}\n\n#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)\n#define INIT_TIMER_EVENT_ENTRY(_entry, _func, _data) \\\n\tdo { \\\n\t\t_rtw_init_listhead(&(_entry)->list); \\\n\t\t(_entry)->data = (_data); \\\n\t\t(_entry)->function = (_func); \\\n\t} while (0)\n\nstatic void pre_phydm_adaptive_soml_callback(unsigned long task_dm)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)task_dm;\n\tstruct rtl8192cd_priv *priv = dm->priv;\n\tstruct priv_shared_info *pshare = priv->pshare;\n\n\tif (pshare->bDriverStopped || pshare->bSurpriseRemoved) {\n\t\tprintk(\"[%s] bDriverStopped(%d) OR bSurpriseRemoved(%d)\\n\",\n\t\t       __FUNCTION__, pshare->bDriverStopped,\n\t\t       pshare->bSurpriseRemoved);\n\t\treturn;\n\t}\n\n\trtw_enqueue_timer_event(priv, &pshare->adaptive_soml_event,\n\t\t\t\tENQUEUE_TO_TAIL);\n}\n\nvoid phydm_adaptive_soml_timers_usb(void *dm_void, u8 state)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\tstruct rtl8192cd_priv *priv = dm->priv;\n\n\tif (state == INIT_SOML_TIMMER) {\n\t\tinit_timer(&soml_tab->phydm_adaptive_soml_timer);\n\t\tsoml_tab->phydm_adaptive_soml_timer.data = (unsigned long)dm;\n\t\tsoml_tab->phydm_adaptive_soml_timer.function = pre_phydm_adaptive_soml_callback;\n\t\tINIT_TIMER_EVENT_ENTRY(&priv->pshare->adaptive_soml_event,\n\t\t\t\t       phydm_adaptive_soml_callback,\n\t\t\t\t       (unsigned long)dm);\n\t} else if (state == CANCEL_SOML_TIMMER) {\n\t\todm_cancel_timer(dm, &soml_tab->phydm_adaptive_soml_timer);\n\t} else if (state == RELEASE_SOML_TIMMER) {\n\t\todm_release_timer(dm, &soml_tab->phydm_adaptive_soml_timer);\n\t}\n}\n#endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */\n\nvoid phydm_adaptive_soml_timers(void *dm_void, u8 state)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\n#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)\n\tstruct rtl8192cd_priv *priv = dm->priv;\n\n\tif (priv->hci_type == RTL_HCI_USB) {\n\t\tphydm_adaptive_soml_timers_usb(dm_void, state);\n\t} else\n#endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */\n\t{\n\tif (state == INIT_SOML_TIMMER) {\n\t\todm_initialize_timer(dm, &soml_tab->phydm_adaptive_soml_timer,\n\t\t\t\t     (void *)phydm_adaptive_soml_callback, NULL,\n\t\t\t\t     \"phydm_adaptive_soml_timer\");\n\t} else if (state == CANCEL_SOML_TIMMER) {\n\t\todm_cancel_timer(dm, &soml_tab->phydm_adaptive_soml_timer);\n\t} else if (state == RELEASE_SOML_TIMMER) {\n\t\todm_release_timer(dm, &soml_tab->phydm_adaptive_soml_timer);\n\t}\n\t}\n}\n\nvoid phydm_adaptive_soml_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n#if 0\n\tif (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) {\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t  \"[Return]   Not Support Adaptive SOML\\n\");\n\t\treturn;\n\t}\n#endif\n\tPHYDM_DBG(dm, DBG_ADPTV_SOML, \"%s\\n\", __func__);\n\n\tsoml_tab->soml_state_cnt = 0;\n\tsoml_tab->soml_delay_time = 40;\n\tsoml_tab->soml_intvl = 150;\n\tsoml_tab->soml_train_num = 4;\n\tsoml_tab->is_soml_method_enable = 0;\n\tsoml_tab->soml_counter = 0;\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\tsoml_tab->soml_period = 1;\n#else\n\tsoml_tab->soml_period = 4;\n#endif\n\tsoml_tab->soml_select = 0;\n\tsoml_tab->cfo_cnt = 0;\n\tsoml_tab->cfo_diff_sum_a = 0;\n\tsoml_tab->cfo_diff_sum_b = 0;\n\n\tsoml_tab->cfo_qpsk_th = 94;\n\tsoml_tab->cfo_qam16_th = 38;\n\tsoml_tab->cfo_qam64_th = 17;\n\tsoml_tab->cfo_qam256_th = 7;\n\n\tsoml_tab->bpsk_qpsk_dist_th = 20;\n\tsoml_tab->qam16_dist_th = 20;\n\tsoml_tab->qam64_dist_th = 20;\n\tsoml_tab->qam256_dist_th = 20;\n\n\tif (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))\n\t\todm_set_bb_reg(dm, 0x988, BIT(25), 1);\n}\n\nvoid phydm_adaptive_soml(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\n\tif (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) {\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t  \"[Return!!!] Not Support Adaptive SOML Function\\n\");\n\t\treturn;\n\t}\n\n\tif (dm->pause_ability & ODM_BB_ADAPTIVE_SOML) {\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML, \"Return: Pause ADSL in LV=%d\\n\",\n\t\t\t  dm->pause_lv_table.lv_adsl);\n\t\treturn;\n\t}\n\n\tif (soml_tab->soml_counter < soml_tab->soml_period) {\n\t\tsoml_tab->soml_counter++;\n\t\treturn;\n\t}\n\tsoml_tab->soml_counter = 0;\n\tsoml_tab->soml_state_cnt = 0;\n\tsoml_tab->cfo_cnt = 0;\n\tsoml_tab->cfo_diff_sum_a = 0;\n\tsoml_tab->cfo_diff_sum_b = 0;\n\n\tphydm_soml_reset_qam(dm);\n\n\tif (soml_tab->soml_select == 0) {\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML,\n\t\t\t  \"[ Adaptive SOML Training !!!]\\n\");\n\t} else if (soml_tab->soml_select == 1) {\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML, \"[ Stop Adaptive SOML !!!]\\n\");\n\t\tphydm_soml_on_off(dm, SOML_ON);\n\t\treturn;\n\t} else if (soml_tab->soml_select == 2) {\n\t\tPHYDM_DBG(dm, DBG_ADPTV_SOML, \"[ Stop Adaptive SOML !!!]\\n\");\n\t\tphydm_soml_on_off(dm, SOML_OFF);\n\t\treturn;\n\t}\n\n\tif (dm->support_ic_type & PHYDM_ADAPTIVE_SOML_IC)\n\t\tphydm_adsl(dm);\n}\n\nvoid phydm_enable_adaptive_soml(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_ADPTV_SOML, \"[%s]\\n\", __func__);\n\tdm->support_ability |= ODM_BB_ADAPTIVE_SOML;\n\tphydm_soml_on_off(dm, SOML_ON);\n}\n\nvoid phydm_stop_adaptive_soml(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_ADPTV_SOML, \"[%s]\\n\", __func__);\n\tdm->support_ability &= ~ODM_BB_ADAPTIVE_SOML;\n\tphydm_soml_on_off(dm, SOML_ON);\n}\n\nvoid phydm_adaptive_soml_para_set(void *dm_void, u8 train_num, u8 intvl,\n\t\t\t\t  u8 period, u8 delay_time)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct adaptive_soml *soml_tab = &dm->dm_soml_table;\n\n\tsoml_tab->soml_train_num = train_num;\n\tsoml_tab->soml_intvl = intvl;\n\tsoml_tab->soml_period = period;\n\tsoml_tab->soml_delay_time = delay_time;\n}\n#endif /* @end of CONFIG_ADAPTIVE_SOML*/\n\nvoid phydm_init_soft_ml_setting(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 soml_mask = BIT(31) | BIT(30) | BIT(29) | BIT(28);\n\n#if (RTL8822B_SUPPORT == 1)\n\tif (!*dm->mp_mode) {\n\t\tif (dm->support_ic_type & ODM_RTL8822B) {\n#if 0\n\t\t\t/*odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0xd10a0000);*/\n#endif\n\t\t\tphydm_somlrxhp_setting(dm, true);\n\t\t\tdm->bsomlenabled = true;\n\t\t}\n\t}\n#endif\n#if (RTL8821C_SUPPORT == 1)\n\tif (!*dm->mp_mode) {\n\t\tif (dm->support_ic_type & ODM_RTL8821C)\n\t\t\todm_set_bb_reg(dm, R_0x19a8, soml_mask, 0xd);\n\t}\n#endif\n#if (RTL8195B_SUPPORT == 1)\n\tif (!*dm->mp_mode) {\n\t\tif (dm->support_ic_type & ODM_RTL8195B)\n\t\t\todm_set_bb_reg(dm, R_0x19a8, soml_mask, 0xd);\n\t}\n#endif\n}\n"
  },
  {
    "path": "hal/phydm/phydm_soml.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#ifndef __PHYDMSOML_H__\n#define __PHYDMSOML_H__\n\n/*@#define ADAPTIVE_SOML_VERSION\t\"1.0\" Byte counter version*/\n#define ADAPTIVE_SOML_VERSION \"2.0\" /*@add avg. phy rate decision 20180126*/\n\n#define PHYDM_ADAPTIVE_SOML_IC\t(ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)\n/*@jj add 20170822*/\n\n#define INIT_SOML_TIMMER\t\t\t0\n#define CANCEL_SOML_TIMMER\t\t\t1\n#define RELEASE_SOML_TIMMER\t\t2\n\n#define SOML_RSSI_TH_HIGH\t25\n#define SOML_RSSI_TH_LOW\t20\n\n#define HT_RATE_IDX\t\t\t16\n#define VHT_RATE_IDX\t\t20\n\n#define HT_ORDER_TYPE\t\t3\n#define VHT_ORDER_TYPE\t\t4\n\n#define CRC_FAIL\t1\n#define CRC_OK\t\t0\n\n#if 0\n#define CFO_QPSK_TH\t\t\t20\n#define CFO_QAM16_TH\t\t20\n#define CFO_QAM64_TH\t\t20\n#define CFO_QAM256_TH\t\t20\n\n#define BPSK_QPSK_DIST\t\t20\n#define QAM16_DIST\t\t\t30\n#define QAM64_DIST\t\t\t30\n#define QAM256_DIST\t\t\t20\n#endif\n#define HT_TYPE\t\t1\n#define VHT_TYPE\t\t2\n\n#define SOML_ON\t\t1\n#define SOML_OFF\t\t0\n\n#ifdef CONFIG_ADAPTIVE_SOML\n\nstruct adaptive_soml {\n\tu8\t\t\trvrt_val;\n\tboolean\t\t\tis_soml_method_enable;\n\tboolean\t\t\tget_stats;\n\tu8\t\t\tsoml_on_off;\n\tu8\t\t\tsoml_state_cnt;\n\tu8\t\t\tsoml_delay_time;\n\tu8\t\t\tsoml_intvl;\n\tu8\t\t\tsoml_train_num;\n\tu8\t\t\tsoml_counter;\n\tu8\t\t\tsoml_period;\n\tu8\t\t\tsoml_select;\n\tu8\t\t\tsoml_last_state;\n\tu8\t\t\tcfo_qpsk_th;\n\tu8\t\t\tcfo_qam16_th;\n\tu8\t\t\tcfo_qam64_th;\n\tu8\t\t\tcfo_qam256_th;\n\tu8\t\t\tbpsk_qpsk_dist_th;\n\tu8\t\t\tqam16_dist_th;\n\tu8\t\t\tqam64_dist_th;\n\tu8\t\t\tqam256_dist_th;\n\tu8\t\t\tcfo_cnt;\n\ts32\t\t\tcfo_diff_a;\n\ts32\t\t\tcfo_diff_b;\n\ts32\t\t\tcfo_diff_sum_a;\n\ts32\t\t\tcfo_diff_sum_b;\n\ts32\t\t\tcfo_diff_avg_a;\n\ts32\t\t\tcfo_diff_avg_b;\n\tu16\t\t\tht_cnt[HT_RATE_IDX];\n\tu16\t\t\tpre_ht_cnt[HT_RATE_IDX];\n\tu16\t\t\tht_cnt_on[HT_RATE_IDX];\n\tu16\t\t\tht_cnt_off[HT_RATE_IDX];\n\tu16\t\t\tht_crc_ok_cnt_on[HT_RATE_IDX];\n\tu16\t\t\tht_crc_fail_cnt_on[HT_RATE_IDX];\n\tu16\t\t\tht_crc_ok_cnt_off[HT_RATE_IDX];\n\tu16\t\t\tht_crc_fail_cnt_off[HT_RATE_IDX];\n\tu16\t\t\tvht_crc_ok_cnt_on[VHT_RATE_IDX];\n\tu16\t\t\tvht_crc_fail_cnt_on[VHT_RATE_IDX];\n\tu16\t\t\tvht_crc_ok_cnt_off[VHT_RATE_IDX];\n\tu16\t\t\tvht_crc_fail_cnt_off[VHT_RATE_IDX];\n\n\tu16\t\t\tvht_cnt[VHT_RATE_IDX];\n\tu16\t\t\tpre_vht_cnt[VHT_RATE_IDX];\n\tu16\t\t\tvht_cnt_on[VHT_RATE_IDX];\n\tu16\t\t\tvht_cnt_off[VHT_RATE_IDX];\n\n\tu16\t\t\tnum_ht_qam[HT_ORDER_TYPE];\n\tu16\t\t\tht_byte[HT_RATE_IDX];\n\tu16\t\t\tpre_ht_byte[HT_RATE_IDX];\n\tu16\t\t\tht_byte_on[HT_RATE_IDX];\n\tu16\t\t\tht_byte_off[HT_RATE_IDX];\n\tu16\t\t\tnum_vht_qam[VHT_ORDER_TYPE];\n\tu16\t\t\tvht_byte[VHT_RATE_IDX];\n\tu16\t\t\tpre_vht_byte[VHT_RATE_IDX];\n\tu16\t\t\tvht_byte_on[VHT_RATE_IDX];\n\tu16\t\t\tvht_byte_off[VHT_RATE_IDX];\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#if USE_WORKITEM\n\tRT_WORK_ITEM\tphydm_adaptive_soml_workitem;\n#endif\n#endif\n\tstruct phydm_timer_list\t\tphydm_adaptive_soml_timer;\n\n};\n\nenum qam_order {\n\tBPSK_QPSK\t= 0,\n\tQAM16\t\t= 1,\n\tQAM64\t\t= 2,\n\tQAM256\t\t= 3\n};\n\nvoid phydm_dynamicsoftmletting(void *dm_void);\n\nvoid phydm_soml_on_off(void *dm_void, u8 swch);\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid phydm_adaptive_soml_callback(struct phydm_timer_list *timer);\n\nvoid phydm_adaptive_soml_workitem_callback(void *context);\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\nvoid phydm_adaptive_soml_callback(void *dm_void);\n\nvoid phydm_adaptive_soml_workitem_callback(void *context);\n\n#else\nvoid phydm_adaptive_soml_callback(void *dm_void);\n#endif\n\nvoid phydm_rx_rate_for_soml(void *dm_void, void *pkt_info_void);\n\nvoid phydm_rx_qam_for_soml(void *dm_void, void *pkt_info_void);\n\nvoid phydm_soml_reset_rx_rate(void *dm_void);\n\nvoid phydm_soml_reset_qam(void *dm_void);\n\nvoid phydm_soml_cfo_process(void *dm_void, s32 *diff_a, s32 *diff_b);\n\nvoid phydm_soml_debug(void *dm_void, char input[][16], u32 *_used,\n\t\t      char *output, u32 *_out_len);\n\nvoid phydm_soml_statistics(void *dm_void, u8 on_off_state);\n\nvoid phydm_adsl(void *dm_void);\n\nvoid phydm_adaptive_soml_reset(void *dm_void);\n\nvoid phydm_set_adsl_val(void *dm_void, u32 *val_buf, u8 val_len);\n\nvoid phydm_soml_crc_acq(void *dm_void, u8 rate_id, boolean crc32, u32 length);\n\nvoid phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length);\n\nvoid phydm_adaptive_soml_timers(void *dm_void, u8 state);\n\nvoid phydm_adaptive_soml_init(void *dm_void);\n\nvoid phydm_adaptive_soml(void *dm_void);\n\nvoid phydm_enable_adaptive_soml(void *dm_void);\n\nvoid phydm_stop_adaptive_soml(void *dm_void);\n\nvoid phydm_adaptive_soml_para_set(void *dm_void, u8 train_num, u8 intvl,\n\t\t\t\t  u8 period, u8 delay_time);\n#endif\nvoid phydm_init_soft_ml_setting(void *dm_void);\n#endif /*@#ifndef\t__PHYDMSOML_H__*/\n"
  },
  {
    "path": "hal/phydm/phydm_types.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#ifndef __ODM_TYPES_H__\n#define __ODM_TYPES_H__\n\n/*Define Different SW team support*/\n#define\tODM_AP\t\t\t0x01\t/*BIT(0)*/\n#define\tODM_CE\t\t\t0x04\t/*BIT(2)*/\n#define\tODM_WIN\t\t0x08\t/*BIT(3)*/\n#define\tODM_ADSL\t\t0x10\n/*BIT(4)*/\t\t/*already combine with ODM_AP, and is nouse now*/\n#define\tODM_IOT\t\t0x20\t/*BIT(5)*/\n\n/*For FW API*/\n#define\t__iram_odm_func__\n#define\t__odm_func__\n#define\t__odm_func_aon__\n\n/*Deifne HW endian support*/\n#define\tODM_ENDIAN_BIG\t0\n#define\tODM_ENDIAN_LITTLE\t1\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t#define GET_PDM_ODM(__padapter)\t((struct dm_struct*)(&(GET_HAL_DATA(__padapter))->DM_OutSrc))\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t#define GET_PDM_ODM(__padapter)\t((struct dm_struct *)(&(GET_HAL_DATA(__padapter))->odmpriv))\n#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t#define GET_PDM_ODM(__padapter)\t((struct dm_struct*)(&__padapter->pshare->_dmODM))\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)\n\t#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)\n\t/* enable PCI & USB HCI at the same time */\n  \t#define RT_PCI_USB_INTERFACE\t\t\t1\n  \t#define\tRT_PCI_INTERFACE\t\t\tRT_PCI_USB_INTERFACE\n\t#define RT_USB_INTERFACE\t\t\tRT_PCI_USB_INTERFACE\n\t#define\tRT_SDIO_INTERFACE\t\t\t3\n  \t#else\n\t#define\tRT_PCI_INTERFACE\t\t\t1\n\t#define\tRT_USB_INTERFACE\t\t\t2\n\t#define\tRT_SDIO_INTERFACE\t\t\t3\n\t#endif\n#endif\n\nenum hal_status {\n\tHAL_STATUS_SUCCESS,\n\tHAL_STATUS_FAILURE,\n#if 0\n\tRT_STATUS_PENDING,\n\tRT_STATUS_RESOURCE,\n\tRT_STATUS_INVALID_CONTEXT,\n\tRT_STATUS_INVALID_PARAMETER,\n\tRT_STATUS_NOT_SUPPORT,\n\tRT_STATUS_OS_API_FAILED,\n#endif\n};\n\n#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)\n\n#define\t\tVISTA_USB_RX_REVISE\t\t\t0\n\n/*\n * Declare for ODM spin lock definition temporarily fro compile pass.\n */\nenum rt_spinlock_type {\n\tRT_TX_SPINLOCK = 1,\n\tRT_RX_SPINLOCK = 2,\n\tRT_RM_SPINLOCK = 3,\n\tRT_CAM_SPINLOCK = 4,\n\tRT_SCAN_SPINLOCK = 5,\n\tRT_LOG_SPINLOCK = 7,\n\tRT_BW_SPINLOCK = 8,\n\tRT_CHNLOP_SPINLOCK = 9,\n\tRT_RF_OPERATE_SPINLOCK = 10,\n\tRT_INITIAL_SPINLOCK = 11,\n\tRT_RF_STATE_SPINLOCK = 12,\n\t/* For RF state. Added by Bruce, 2007-10-30. */\n#if VISTA_USB_RX_REVISE\n\tRT_USBRX_CONTEXT_SPINLOCK = 13,\n\tRT_USBRX_POSTPROC_SPINLOCK = 14,\n\t/* protect data of adapter->IndicateW/ IndicateR */\n#endif\n\t/* Shall we define Ndis 6.2 SpinLock Here ? */\n\tRT_PORT_SPINLOCK = 16,\n\tRT_VNIC_SPINLOCK = 17,\n\tRT_HVL_SPINLOCK = 18,\n\tRT_H2C_SPINLOCK = 20,\n\t/* For H2C cmd. Added by tynli. 2009.11.09. */\n\n\trt_bt_data_spinlock = 25,\n\n\tRT_WAPI_OPTION_SPINLOCK = 26,\n\tRT_WAPI_RX_SPINLOCK = 27,\n\n\t/* add for 92D CCK control issue */\n\tRT_CCK_PAGEA_SPINLOCK = 28,\n\tRT_BUFFER_SPINLOCK = 29,\n\tRT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,\n\tRT_GEN_TEMP_BUF_SPINLOCK = 31,\n\tRT_AWB_SPINLOCK = 32,\n\tRT_FW_PS_SPINLOCK = 33,\n\tRT_HW_TIMER_SPIN_LOCK = 34,\n\tRT_MPT_WI_SPINLOCK = 35,\n\tRT_P2P_SPIN_LOCK = 36,\t/* Protect P2P context */\n\tRT_DBG_SPIN_LOCK = 37,\n\tRT_IQK_SPINLOCK = 38,\n\tRT_PENDED_OID_SPINLOCK = 39,\n\tRT_CHNLLIST_SPINLOCK = 40,\n\tRT_INDIC_SPINLOCK = 41,\t/* protect indication */\n\tRT_RFD_SPINLOCK = 42,\n\tRT_SYNC_IO_CNT_SPINLOCK = 43,\n\tRT_LAST_SPINLOCK,\n};\n\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t#define sta_info \t_RT_WLAN_STA\n\t#define\t__func__\t\t__FUNCTION__\n\t#define\tPHYDM_TESTCHIP_SUPPORT\tTESTCHIP_SUPPORT\n\t#define MASKH3BYTES\t\t\t0xffffff00\n\t#define SUCCESS\t0\n\t#define FAIL\t(-1)\n\n\t#define\tu8 \t\tu1Byte\n\t#define\ts8 \t\ts1Byte\n\n\t#define\tu16\t\tu2Byte\n\t#define\ts16\t\ts2Byte\n\n\t#define\tu32 \tu4Byte\n\t#define\ts32 \t\ts4Byte\n\n\t#define\tu64\t\tu8Byte\n\t#define\ts64\t\ts8Byte\n\n\t#define\tphydm_timer_list\t_RT_TIMER\n\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)\n\t#include \"../typedef.h\"\n\n\t#ifdef CONFIG_PCI_HCI\n\t#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)\n\t\t#define DEV_BUS_TYPE\t\tRT_PCI_USB_INTERFACE\n\t#else\n\t\t#define DEV_BUS_TYPE\t\tRT_PCI_INTERFACE\n\t#endif\n\t#endif\n\n\t#if (defined(TESTCHIP_SUPPORT))\n\t\t#define\tPHYDM_TESTCHIP_SUPPORT 1\n\t#else\n\t\t#define\tPHYDM_TESTCHIP_SUPPORT 0\n\t#endif\n\n\t#define\tsta_info stat_info\n\t#define\tboolean\tbool\n\n\t#define\tphydm_timer_list\ttimer_list\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)\n\n\t#include <asm/byteorder.h>\n\n\t#define DEV_BUS_TYPE\tRT_PCI_INTERFACE\n\n\t#if defined(__LITTLE_ENDIAN)\n\t\t#define\tODM_ENDIAN_TYPE\t\t\tODM_ENDIAN_LITTLE\n\t#elif defined(__BIG_ENDIAN)\n\t\t#define\tODM_ENDIAN_TYPE\t\t\tODM_ENDIAN_BIG\n\t#else\n\t\t#error\n\t#endif\n\n\t/* define useless flag to avoid compile warning */\n\t#define\tUSE_WORKITEM 0\n\t#define\tFOR_BRAZIL_PRETEST 0\n\t#define\tFPGA_TWO_MAC_VERIFICATION\t0\n\t#define\tRTL8881A_SUPPORT\t0\n\t#define\tPHYDM_TESTCHIP_SUPPORT 0\n\n\n\t#define RATE_ADAPTIVE_SUPPORT\t\t\t0\n\t#define POWER_TRAINING_ACTIVE\t\t\t0\n\n\t#define sta_info\trtl_sta_info\n\t#define\tboolean\t\tbool\n\n\t#define\tphydm_timer_list\ttimer_list\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\t#include <drv_types.h>\n\n\t#ifdef CONFIG_USB_HCI\n\t\t#define DEV_BUS_TYPE\tRT_USB_INTERFACE\n\t#elif defined(CONFIG_PCI_HCI)\n\t\t#define DEV_BUS_TYPE\tRT_PCI_INTERFACE\n\t#elif defined(CONFIG_SDIO_HCI)\n\t\t#define DEV_BUS_TYPE\tRT_SDIO_INTERFACE\n\t#elif defined(CONFIG_GSPI_HCI)\n\t\t#define DEV_BUS_TYPE\tRT_SDIO_INTERFACE\n\t#endif\n\n\n\t#if defined(CONFIG_LITTLE_ENDIAN)\n\t\t#define\tODM_ENDIAN_TYPE\t\t\tODM_ENDIAN_LITTLE\n\t#elif defined(CONFIG_BIG_ENDIAN)\n\t\t#define\tODM_ENDIAN_TYPE\t\t\tODM_ENDIAN_BIG\n\t#endif\n\n\t#define\tboolean\tbool\n\n\t#define SET_TX_DESC_ANTSEL_A_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 8, 24, 1, __value)\n\t#define SET_TX_DESC_ANTSEL_B_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 8, 25, 1, __value)\n\t#define SET_TX_DESC_ANTSEL_C_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 28, 29, 1, __value)\n\n\t/* define useless flag to avoid compile warning */\n\t#define\tUSE_WORKITEM 0\n\t#define\tFOR_BRAZIL_PRETEST 0\n\t#define\tFPGA_TWO_MAC_VERIFICATION\t0\n\t#define\tRTL8881A_SUPPORT\t0\n\n\t#if (defined(TESTCHIP_SUPPORT))\n\t\t#define\tPHYDM_TESTCHIP_SUPPORT 1\n\t#else\n\t\t#define\tPHYDM_TESTCHIP_SUPPORT 0\n\t#endif\n\n\t#define\tphydm_timer_list\trtw_timer_list\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)\n\t#define\tboolean\tbool\n\t#define true\t_TRUE\n\t#define false\t_FALSE\n\n\t// for power limit table\n\tenum odm_pw_lmt_regulation_type {\n\t\tPW_LMT_REGU_NULL = 0,\n\t\tPW_LMT_REGU_FCC = 1,\n\t\tPW_LMT_REGU_ETSI = 2,\n\t\tPW_LMT_REGU_MKK = 3,\n\t\tPW_LMT_REGU_WW13 = 4\n\t};\n\n\tenum odm_pw_lmt_band_type {\n\t\tPW_LMT_BAND_NULL = 0,\n\t\tPW_LMT_BAND_2_4G = 1,\n\t\tPW_LMT_BAND_5G = 2\n\t};\n\n\tenum odm_pw_lmt_bandwidth_type {\n\t\tPW_LMT_BW_NULL = 0,\n\t\tPW_LMT_BW_20M = 1,\n\t\tPW_LMT_BW_40M = 2,\n\t\tPW_LMT_BW_80M = 3\n\t};\n\n\tenum odm_pw_lmt_ratesection_type {\n\t\tPW_LMT_RS_NULL = 0,\n\t\tPW_LMT_RS_CCK = 1,\n\t\tPW_LMT_RS_OFDM = 2,\n\t\tPW_LMT_RS_HT = 3,\n\t\tPW_LMT_RS_VHT = 4\n\t};\n\n\tenum odm_pw_lmt_rfpath_type {\n\t\tPW_LMT_PH_NULL = 0,\n\t\tPW_LMT_PH_1T = 1,\n\t\tPW_LMT_PH_2T = 2,\n\t\tPW_LMT_PH_3T = 3,\n\t\tPW_LMT_PH_4T = 4\n\t};\n\n\t#define\tphydm_timer_list\ttimer_list\n\n#endif\n\n#define READ_NEXT_PAIR(v1, v2, i) do { if (i + 2 >= array_len) break; i += 2; v1 = array[i]; v2 = array[i + 1]; } while (0)\n#define COND_ELSE  2\n#define COND_ENDIF 3\n\n#define\tMASKBYTE0\t\t0xff\n#define\tMASKBYTE1\t\t0xff00\n#define\tMASKBYTE2\t\t0xff0000\n#define\tMASKBYTE3\t\t0xff000000\n#define\tMASKHWORD\t\t0xffff0000\n#define\tMASKLWORD\t\t0x0000ffff\n#define\tMASKDWORD\t\t0xffffffff\n\n#define\tMASK7BITS\t\t0x7f\n#define\tMASK12BITS\t\t0xfff\n#define\tMASKH4BITS\t\t0xf0000000\n#define\tMASK20BITS\t\t0xfffff\n#define\tMASK24BITS\t\t0xffffff\n#define\tMASKOFDM_D\t\t0xffc00000\n#define\tMASKCCK\t\t\t0x3f3f3f3f\n\n#define RFREGOFFSETMASK\t\t0xfffff\n#define RFREG_MASK\t\t0xfffff\n\n#define MASKH3BYTES\t\t0xffffff00\n#define MASKL3BYTES\t\t0x00ffffff\n#define MASKBYTE2HIGHNIBBLE\t0x00f00000\n#define MASKBYTE3LOWNIBBLE\t0x0f000000\n#define\tMASKL3BYTES\t\t0x00ffffff\n\n#endif /* __ODM_TYPES_H__ */\n"
  },
  {
    "path": "hal/phydm/rtl8822c/halhwimg8822c_bb.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*Image2HeaderVersion: R3 1.5.8*/\n#include \"mp_precomp.h\"\n#include \"../phydm_precomp.h\"\n\n#if (RTL8822C_SUPPORT == 1)\nstatic boolean\ncheck_positive(struct dm_struct *dm,\n\t       const u32\tcondition1,\n\t       const u32\tcondition2,\n\t       const u32\tcondition3,\n\t       const u32\tcondition4\n)\n{\n\tu32\tcond1 = condition1, cond2 = condition2,\n\t\tcond3 = condition3, cond4 = condition4;\n\n\tu8\tcut_version_for_para =\n\t\t(dm->cut_version ==  ODM_CUT_A) ? 15 : dm->cut_version;\n\n\tu8\tpkg_type_for_para =\n\t\t(dm->package_type == 0) ? 15 : dm->package_type;\n\n\tu32\tdriver1 = cut_version_for_para << 24 |\n\t\t\t(dm->support_interface & 0xF0) << 16 |\n\t\t\tdm->support_platform << 16 |\n\t\t\tpkg_type_for_para << 12 |\n\t\t\t(dm->support_interface & 0x0F) << 8  |\n\t\t\tdm->rfe_type;\n\n\tu32\tdriver2 = (dm->type_glna & 0xFF) <<  0 |\n\t\t\t(dm->type_gpa & 0xFF)  <<  8 |\n\t\t\t(dm->type_alna & 0xFF) << 16 |\n\t\t\t(dm->type_apa & 0xFF)  << 24;\n\n\tu32\tdriver3 = 0;\n\n\tu32\tdriver4 = (dm->type_glna & 0xFF00) >>  8 |\n\t\t\t(dm->type_gpa & 0xFF00) |\n\t\t\t(dm->type_alna & 0xFF00) << 8 |\n\t\t\t(dm->type_apa & 0xFF00)  << 16;\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t  \"===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\\n\",\n\t\t  __func__, cond1, cond2, cond3, cond4);\n\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t  \"===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\\n\",\n\t\t  __func__, driver1, driver2, driver3, driver4);\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t  \"\t(Platform, Interface) = (0x%X, 0x%X)\\n\",\n\t\t  dm->support_platform, dm->support_interface);\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"\t(RFE, Package) = (0x%X, 0x%X)\\n\",\n\t\t  dm->rfe_type, dm->package_type);\n\n\t/*============== value Defined Check ===============*/\n\t/*cut version [27:24] need to do value check*/\n\tif (((cond1 & 0x0F000000) != 0) &&\n\t    ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))\n\t\treturn false;\n\n\t/*pkg type [15:12] need to do value check*/\n\tif (((cond1 & 0x0000F000) != 0) &&\n\t    ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))\n\t\treturn false;\n\n\t/*interface [11:8] need to do value check*/\n\tif (((cond1 & 0x00000F00) != 0) &&\n\t    ((cond1 & 0x00000F00) != (driver1 & 0x00000F00)))\n\t\treturn false;\n\t/*=============== Bit Defined Check ================*/\n\t/* We don't care [31:28] */\n\n\tcond1 &= 0x000000FF;\n\tdriver1 &= 0x000000FF;\n\n\tif (cond1 == driver1)\n\t\treturn true;\n\telse\n\t\treturn false;\n}\n\n\n/******************************************************************************\n *                           agc_tab.TXT\n ******************************************************************************/\n\nconst u32 array_mp_8822c_agc_tab[] = {\n\t\t0x1D90, 0x300001FF,\n\t\t0x1D90, 0x300101FE,\n\t\t0x1D90, 0x300201FD,\n\t\t0x1D90, 0x300301FC,\n\t\t0x1D90, 0x300401FB,\n\t\t0x1D90, 0x300501FA,\n\t\t0x1D90, 0x300601F9,\n\t\t0x1D90, 0x300701F8,\n\t\t0x1D90, 0x300801F7,\n\t\t0x1D90, 0x300901F6,\n\t\t0x1D90, 0x300A01F5,\n\t\t0x1D90, 0x300B01F4,\n\t\t0x1D90, 0x300C01F3,\n\t\t0x1D90, 0x300D01F2,\n\t\t0x1D90, 0x300E01F1,\n\t\t0x1D90, 0x300F01F0,\n\t\t0x1D90, 0x301001EF,\n\t\t0x1D90, 0x301101EE,\n\t\t0x1D90, 0x301201ED,\n\t\t0x1D90, 0x301301EC,\n\t\t0x1D90, 0x301401EB,\n\t\t0x1D90, 0x301501EA,\n\t\t0x1D90, 0x301601E9,\n\t\t0x1D90, 0x301701E8,\n\t\t0x1D90, 0x301801E7,\n\t\t0x1D90, 0x301901E5,\n\t\t0x1D90, 0x301A01E4,\n\t\t0x1D90, 0x301B01C5,\n\t\t0x1D90, 0x301C01C4,\n\t\t0x1D90, 0x301D01C3,\n\t\t0x1D90, 0x301E01C2,\n\t\t0x1D90, 0x301F0188,\n\t\t0x1D90, 0x30200187,\n\t\t0x1D90, 0x30210186,\n\t\t0x1D90, 0x30220184,\n\t\t0x1D90, 0x30230183,\n\t\t0x1D90, 0x30240182,\n\t\t0x1D90, 0x30250181,\n\t\t0x1D90, 0x30260148,\n\t\t0x1D90, 0x30270147,\n\t\t0x1D90, 0x30280146,\n\t\t0x1D90, 0x30290144,\n\t\t0x1D90, 0x302A0143,\n\t\t0x1D90, 0x302B0142,\n\t\t0x1D90, 0x302C0141,\n\t\t0x1D90, 0x302D00C8,\n\t\t0x1D90, 0x302E00C7,\n\t\t0x1D90, 0x302F00C6,\n\t\t0x1D90, 0x303000C5,\n\t\t0x1D90, 0x303100C4,\n\t\t0x1D90, 0x303200C3,\n\t\t0x1D90, 0x30330048,\n\t\t0x1D90, 0x30340047,\n\t\t0x1D90, 0x30350046,\n\t\t0x1D90, 0x30360045,\n\t\t0x1D90, 0x30370025,\n\t\t0x1D90, 0x30380024,\n\t\t0x1D90, 0x30390023,\n\t\t0x1D90, 0x303A0022,\n\t\t0x1D90, 0x303B0021,\n\t\t0x1D90, 0x303C0020,\n\t\t0x1D90, 0x303D0003,\n\t\t0x1D90, 0x303E0002,\n\t\t0x1D90, 0x303F0001,\n\t\t0x1D90, 0x3040011F,\n\t\t0x1D90, 0x3041011F,\n\t\t0x1D90, 0x3042011F,\n\t\t0x1D90, 0x3043011F,\n\t\t0x1D90, 0x3044011F,\n\t\t0x1D90, 0x3045011F,\n\t\t0x1D90, 0x3046011F,\n\t\t0x1D90, 0x3047011F,\n\t\t0x1D90, 0x3048011F,\n\t\t0x1D90, 0x3049011F,\n\t\t0x1D90, 0x304A011F,\n\t\t0x1D90, 0x304B011F,\n\t\t0x1D90, 0x304C011F,\n\t\t0x1D90, 0x304D011F,\n\t\t0x1D90, 0x304E011F,\n\t\t0x1D90, 0x304F00F4,\n\t\t0x1D90, 0x305000F3,\n\t\t0x1D90, 0x305100F2,\n\t\t0x1D90, 0x305200F1,\n\t\t0x1D90, 0x305300F0,\n\t\t0x1D90, 0x305400EF,\n\t\t0x1D90, 0x305500EE,\n\t\t0x1D90, 0x305600ED,\n\t\t0x1D90, 0x305700EC,\n\t\t0x1D90, 0x305800EB,\n\t\t0x1D90, 0x305900EA,\n\t\t0x1D90, 0x305A00E9,\n\t\t0x1D90, 0x305B00E8,\n\t\t0x1D90, 0x305C00E7,\n\t\t0x1D90, 0x305D00E6,\n\t\t0x1D90, 0x305E00E4,\n\t\t0x1D90, 0x305F00E3,\n\t\t0x1D90, 0x306000E2,\n\t\t0x1D90, 0x306100C4,\n\t\t0x1D90, 0x306200C3,\n\t\t0x1D90, 0x306300C2,\n\t\t0x1D90, 0x306400A4,\n\t\t0x1D90, 0x306500A3,\n\t\t0x1D90, 0x306600A2,\n\t\t0x1D90, 0x306700A1,\n\t\t0x1D90, 0x30680084,\n\t\t0x1D90, 0x30690083,\n\t\t0x1D90, 0x306A0082,\n\t\t0x1D90, 0x306B0081,\n\t\t0x1D90, 0x306C0080,\n\t\t0x1D90, 0x306D0067,\n\t\t0x1D90, 0x306E0066,\n\t\t0x1D90, 0x306F0065,\n\t\t0x1D90, 0x30700064,\n\t\t0x1D90, 0x30710063,\n\t\t0x1D90, 0x30720044,\n\t\t0x1D90, 0x30730043,\n\t\t0x1D90, 0x30740042,\n\t\t0x1D90, 0x30750041,\n\t\t0x1D90, 0x30760024,\n\t\t0x1D90, 0x30770023,\n\t\t0x1D90, 0x30780022,\n\t\t0x1D90, 0x30790021,\n\t\t0x1D90, 0x307A0020,\n\t\t0x1D90, 0x307B0004,\n\t\t0x1D90, 0x307C0003,\n\t\t0x1D90, 0x307D0002,\n\t\t0x1D90, 0x307E0001,\n\t\t0x1D90, 0x307F0000,\n\t\t0x1D90, 0x308000FF,\n\t\t0x1D90, 0x308100FF,\n\t\t0x1D90, 0x308200FF,\n\t\t0x1D90, 0x308300FF,\n\t\t0x1D90, 0x308400FF,\n\t\t0x1D90, 0x308500FF,\n\t\t0x1D90, 0x308600FE,\n\t\t0x1D90, 0x308700FD,\n\t\t0x1D90, 0x308800FC,\n\t\t0x1D90, 0x308900FB,\n\t\t0x1D90, 0x308A00FA,\n\t\t0x1D90, 0x308B00F9,\n\t\t0x1D90, 0x308C00F8,\n\t\t0x1D90, 0x308D00F7,\n\t\t0x1D90, 0x308E00F6,\n\t\t0x1D90, 0x308F00F5,\n\t\t0x1D90, 0x309000F4,\n\t\t0x1D90, 0x309100F3,\n\t\t0x1D90, 0x309200F2,\n\t\t0x1D90, 0x309300F1,\n\t\t0x1D90, 0x309400F0,\n\t\t0x1D90, 0x309500EF,\n\t\t0x1D90, 0x309600EE,\n\t\t0x1D90, 0x309700ED,\n\t\t0x1D90, 0x309800EC,\n\t\t0x1D90, 0x309900EB,\n\t\t0x1D90, 0x309A00EA,\n\t\t0x1D90, 0x309B00E8,\n\t\t0x1D90, 0x309C00E7,\n\t\t0x1D90, 0x309D00E6,\n\t\t0x1D90, 0x309E00E5,\n\t\t0x1D90, 0x309F00E4,\n\t\t0x1D90, 0x30A000C4,\n\t\t0x1D90, 0x30A100C3,\n\t\t0x1D90, 0x30A200C2,\n\t\t0x1D90, 0x30A300C1,\n\t\t0x1D90, 0x30A400A3,\n\t\t0x1D90, 0x30A500A2,\n\t\t0x1D90, 0x30A600A1,\n\t\t0x1D90, 0x30A70085,\n\t\t0x1D90, 0x30A80084,\n\t\t0x1D90, 0x30A90083,\n\t\t0x1D90, 0x30AA0082,\n\t\t0x1D90, 0x30AB0081,\n\t\t0x1D90, 0x30AC0067,\n\t\t0x1D90, 0x30AD0066,\n\t\t0x1D90, 0x30AE0065,\n\t\t0x1D90, 0x30AF0064,\n\t\t0x1D90, 0x30B00063,\n\t\t0x1D90, 0x30B10044,\n\t\t0x1D90, 0x30B20043,\n\t\t0x1D90, 0x30B30042,\n\t\t0x1D90, 0x30B40026,\n\t\t0x1D90, 0x30B50025,\n\t\t0x1D90, 0x30B60024,\n\t\t0x1D90, 0x30B70023,\n\t\t0x1D90, 0x30B80022,\n\t\t0x1D90, 0x30B90021,\n\t\t0x1D90, 0x30BA0005,\n\t\t0x1D90, 0x30BB0004,\n\t\t0x1D90, 0x30BC0003,\n\t\t0x1D90, 0x30BD0002,\n\t\t0x1D90, 0x30BE0001,\n\t\t0x1D90, 0x30BF0000,\n\t\t0x1D90, 0x30C000FF,\n\t\t0x1D90, 0x30C100FF,\n\t\t0x1D90, 0x30C200FF,\n\t\t0x1D90, 0x30C300FF,\n\t\t0x1D90, 0x30C400FF,\n\t\t0x1D90, 0x30C500FF,\n\t\t0x1D90, 0x30C600FE,\n\t\t0x1D90, 0x30C700FD,\n\t\t0x1D90, 0x30C800FC,\n\t\t0x1D90, 0x30C900FB,\n\t\t0x1D90, 0x30CA00FA,\n\t\t0x1D90, 0x30CB00F9,\n\t\t0x1D90, 0x30CC00F8,\n\t\t0x1D90, 0x30CD00F7,\n\t\t0x1D90, 0x30CE00F6,\n\t\t0x1D90, 0x30CF00F5,\n\t\t0x1D90, 0x30D000F4,\n\t\t0x1D90, 0x30D100F3,\n\t\t0x1D90, 0x30D200F2,\n\t\t0x1D90, 0x30D300F1,\n\t\t0x1D90, 0x30D400F0,\n\t\t0x1D90, 0x30D500EF,\n\t\t0x1D90, 0x30D600EE,\n\t\t0x1D90, 0x30D700ED,\n\t\t0x1D90, 0x30D800EC,\n\t\t0x1D90, 0x30D900EB,\n\t\t0x1D90, 0x30DA00EA,\n\t\t0x1D90, 0x30DB00E8,\n\t\t0x1D90, 0x30DC00E7,\n\t\t0x1D90, 0x30DD00E6,\n\t\t0x1D90, 0x30DE00E5,\n\t\t0x1D90, 0x30DF00E4,\n\t\t0x1D90, 0x30E000E3,\n\t\t0x1D90, 0x30E100E2,\n\t\t0x1D90, 0x30E200A6,\n\t\t0x1D90, 0x30E300A5,\n\t\t0x1D90, 0x30E400A4,\n\t\t0x1D90, 0x30E500A3,\n\t\t0x1D90, 0x30E600A2,\n\t\t0x1D90, 0x30E70086,\n\t\t0x1D90, 0x30E80085,\n\t\t0x1D90, 0x30E90084,\n\t\t0x1D90, 0x30EA0083,\n\t\t0x1D90, 0x30EB0082,\n\t\t0x1D90, 0x30EC0067,\n\t\t0x1D90, 0x30ED0066,\n\t\t0x1D90, 0x30EE0065,\n\t\t0x1D90, 0x30EF0064,\n\t\t0x1D90, 0x30F00063,\n\t\t0x1D90, 0x30F10045,\n\t\t0x1D90, 0x30F20044,\n\t\t0x1D90, 0x30F30043,\n\t\t0x1D90, 0x30F40042,\n\t\t0x1D90, 0x30F50025,\n\t\t0x1D90, 0x30F60024,\n\t\t0x1D90, 0x30F70023,\n\t\t0x1D90, 0x30F80022,\n\t\t0x1D90, 0x30F90021,\n\t\t0x1D90, 0x30FA0005,\n\t\t0x1D90, 0x30FB0004,\n\t\t0x1D90, 0x30FC0003,\n\t\t0x1D90, 0x30FD0002,\n\t\t0x1D90, 0x30FE0001,\n\t\t0x1D90, 0x30FF0000,\n\t\t0x1D90, 0x310001FF,\n\t\t0x1D90, 0x310101FF,\n\t\t0x1D90, 0x310201FF,\n\t\t0x1D90, 0x310301FF,\n\t\t0x1D90, 0x310401FF,\n\t\t0x1D90, 0x310501FF,\n\t\t0x1D90, 0x310601FF,\n\t\t0x1D90, 0x310701FF,\n\t\t0x1D90, 0x310801FF,\n\t\t0x1D90, 0x310901FE,\n\t\t0x1D90, 0x310A01FD,\n\t\t0x1D90, 0x310B01FC,\n\t\t0x1D90, 0x310C01FB,\n\t\t0x1D90, 0x310D01FA,\n\t\t0x1D90, 0x310E01F9,\n\t\t0x1D90, 0x310F01F8,\n\t\t0x1D90, 0x311001F7,\n\t\t0x1D90, 0x311101F6,\n\t\t0x1D90, 0x311201F5,\n\t\t0x1D90, 0x311301F4,\n\t\t0x1D90, 0x311401F3,\n\t\t0x1D90, 0x311501F2,\n\t\t0x1D90, 0x311601F1,\n\t\t0x1D90, 0x311701F0,\n\t\t0x1D90, 0x311801EF,\n\t\t0x1D90, 0x311901EE,\n\t\t0x1D90, 0x311A01ED,\n\t\t0x1D90, 0x311B01EC,\n\t\t0x1D90, 0x311C01EB,\n\t\t0x1D90, 0x311D0192,\n\t\t0x1D90, 0x311E0191,\n\t\t0x1D90, 0x311F0190,\n\t\t0x1D90, 0x3120018F,\n\t\t0x1D90, 0x3121018E,\n\t\t0x1D90, 0x3122018D,\n\t\t0x1D90, 0x3123018C,\n\t\t0x1D90, 0x3124018B,\n\t\t0x1D90, 0x3125018A,\n\t\t0x1D90, 0x31260189,\n\t\t0x1D90, 0x31270188,\n\t\t0x1D90, 0x31280187,\n\t\t0x1D90, 0x31290186,\n\t\t0x1D90, 0x312A0185,\n\t\t0x1D90, 0x312B0149,\n\t\t0x1D90, 0x312C0148,\n\t\t0x1D90, 0x312D0147,\n\t\t0x1D90, 0x312E0146,\n\t\t0x1D90, 0x312F0145,\n\t\t0x1D90, 0x31300144,\n\t\t0x1D90, 0x31310143,\n\t\t0x1D90, 0x31320142,\n\t\t0x1D90, 0x31330141,\n\t\t0x1D90, 0x31340140,\n\t\t0x1D90, 0x313500C7,\n\t\t0x1D90, 0x313600C6,\n\t\t0x1D90, 0x313700C5,\n\t\t0x1D90, 0x313800C4,\n\t\t0x1D90, 0x313900C3,\n\t\t0x1D90, 0x313A0088,\n\t\t0x1D90, 0x313B0087,\n\t\t0x1D90, 0x313C0086,\n\t\t0x1D90, 0x313D0045,\n\t\t0x1D90, 0x313E0044,\n\t\t0x1D90, 0x313F0043,\n\t\t0x1D90, 0x314001FF,\n\t\t0x1D90, 0x314101FF,\n\t\t0x1D90, 0x314201FF,\n\t\t0x1D90, 0x314301FF,\n\t\t0x1D90, 0x314401FF,\n\t\t0x1D90, 0x314501FF,\n\t\t0x1D90, 0x314601FF,\n\t\t0x1D90, 0x314701FE,\n\t\t0x1D90, 0x314801FD,\n\t\t0x1D90, 0x314901FC,\n\t\t0x1D90, 0x314A01FB,\n\t\t0x1D90, 0x314B01FA,\n\t\t0x1D90, 0x314C01F9,\n\t\t0x1D90, 0x314D01F8,\n\t\t0x1D90, 0x314E01F7,\n\t\t0x1D90, 0x314F01F6,\n\t\t0x1D90, 0x315001F5,\n\t\t0x1D90, 0x315101F4,\n\t\t0x1D90, 0x315201F3,\n\t\t0x1D90, 0x315301F2,\n\t\t0x1D90, 0x315401F1,\n\t\t0x1D90, 0x315501F0,\n\t\t0x1D90, 0x315601EF,\n\t\t0x1D90, 0x315701EE,\n\t\t0x1D90, 0x315801ED,\n\t\t0x1D90, 0x315901EC,\n\t\t0x1D90, 0x315A01EB,\n\t\t0x1D90, 0x315B01EA,\n\t\t0x1D90, 0x315C01E9,\n\t\t0x1D90, 0x315D018F,\n\t\t0x1D90, 0x315E018E,\n\t\t0x1D90, 0x315F018D,\n\t\t0x1D90, 0x3160018C,\n\t\t0x1D90, 0x3161018B,\n\t\t0x1D90, 0x3162018A,\n\t\t0x1D90, 0x31630189,\n\t\t0x1D90, 0x31640188,\n\t\t0x1D90, 0x31650187,\n\t\t0x1D90, 0x31660186,\n\t\t0x1D90, 0x31670185,\n\t\t0x1D90, 0x31680184,\n\t\t0x1D90, 0x31690183,\n\t\t0x1D90, 0x316A0182,\n\t\t0x1D90, 0x316B0149,\n\t\t0x1D90, 0x316C0148,\n\t\t0x1D90, 0x316D0147,\n\t\t0x1D90, 0x316E0146,\n\t\t0x1D90, 0x316F0145,\n\t\t0x1D90, 0x31700144,\n\t\t0x1D90, 0x31710143,\n\t\t0x1D90, 0x31720142,\n\t\t0x1D90, 0x31730141,\n\t\t0x1D90, 0x31740140,\n\t\t0x1D90, 0x317500C7,\n\t\t0x1D90, 0x317600C6,\n\t\t0x1D90, 0x317700C5,\n\t\t0x1D90, 0x317800C4,\n\t\t0x1D90, 0x317900C3,\n\t\t0x1D90, 0x317A0088,\n\t\t0x1D90, 0x317B0087,\n\t\t0x1D90, 0x317C0086,\n\t\t0x1D90, 0x317D0045,\n\t\t0x1D90, 0x317E0044,\n\t\t0x1D90, 0x317F0043,\n\t\t0x1D90, 0x318001FE,\n\t\t0x1D90, 0x318101FD,\n\t\t0x1D90, 0x318201FC,\n\t\t0x1D90, 0x318301FB,\n\t\t0x1D90, 0x318401FA,\n\t\t0x1D90, 0x318501F9,\n\t\t0x1D90, 0x318601F8,\n\t\t0x1D90, 0x318701F7,\n\t\t0x1D90, 0x318801F6,\n\t\t0x1D90, 0x318901F5,\n\t\t0x1D90, 0x318A01F4,\n\t\t0x1D90, 0x318B01F3,\n\t\t0x1D90, 0x318C01F2,\n\t\t0x1D90, 0x318D01F1,\n\t\t0x1D90, 0x318E01F0,\n\t\t0x1D90, 0x318F01EF,\n\t\t0x1D90, 0x319001EE,\n\t\t0x1D90, 0x319101ED,\n\t\t0x1D90, 0x319201EC,\n\t\t0x1D90, 0x319301EB,\n\t\t0x1D90, 0x319401EA,\n\t\t0x1D90, 0x319501E9,\n\t\t0x1D90, 0x319601E7,\n\t\t0x1D90, 0x319701E6,\n\t\t0x1D90, 0x319801E5,\n\t\t0x1D90, 0x319901E4,\n\t\t0x1D90, 0x319A01A8,\n\t\t0x1D90, 0x319B01A7,\n\t\t0x1D90, 0x319C01A6,\n\t\t0x1D90, 0x319D01A5,\n\t\t0x1D90, 0x319E0185,\n\t\t0x1D90, 0x319F0184,\n\t\t0x1D90, 0x31A00183,\n\t\t0x1D90, 0x31A10182,\n\t\t0x1D90, 0x31A20149,\n\t\t0x1D90, 0x31A30148,\n\t\t0x1D90, 0x31A40147,\n\t\t0x1D90, 0x31A50145,\n\t\t0x1D90, 0x31A60144,\n\t\t0x1D90, 0x31A70143,\n\t\t0x1D90, 0x31A80142,\n\t\t0x1D90, 0x31A900E6,\n\t\t0x1D90, 0x31AA00E5,\n\t\t0x1D90, 0x31AB00C9,\n\t\t0x1D90, 0x31AC00C8,\n\t\t0x1D90, 0x31AD00C7,\n\t\t0x1D90, 0x31AE00C6,\n\t\t0x1D90, 0x31AF00C5,\n\t\t0x1D90, 0x31B000C4,\n\t\t0x1D90, 0x31B100C3,\n\t\t0x1D90, 0x31B20088,\n\t\t0x1D90, 0x31B30087,\n\t\t0x1D90, 0x31B40086,\n\t\t0x1D90, 0x31B50085,\n\t\t0x1D90, 0x31B60026,\n\t\t0x1D90, 0x31B70025,\n\t\t0x1D90, 0x31B80024,\n\t\t0x1D90, 0x31B90023,\n\t\t0x1D90, 0x31BA0022,\n\t\t0x1D90, 0x31BB0021,\n\t\t0x1D90, 0x31BC0020,\n\t\t0x1D90, 0x31BD0003,\n\t\t0x1D90, 0x31BE0002,\n\t\t0x1D90, 0x31BF0001,\n\t\t0x1D70, 0x22222222,\n\t\t0x1D70, 0x20202020,\n\n};\n\nvoid\nodm_read_and_config_mp_8822c_agc_tab(struct dm_struct *dm)\n{\n\tu32\ti = 0;\n\tu8\tc_cond;\n\tboolean\tis_matched = true, is_skipped = false;\n\tu32\tarray_len =\n\t\t\tsizeof(array_mp_8822c_agc_tab) / sizeof(u32);\n\tu32\t*array = (u32 *)array_mp_8822c_agc_tab;\n\n\tu32\tv1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;\n\tu32\ta1 = 0, a2 = 0, a3 = 0, a4 = 0;\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"===> %s\\n\", __func__);\n\n\twhile ((i + 1) < array_len) {\n\t\tv1 = array[i];\n\t\tv2 = array[i + 1];\n\n\t\tif (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/\n\t\t\tif (v1 & BIT(31)) {/* positive condition*/\n\t\t\t\tc_cond  =\n\t\t\t\t\t(u8)((v1 & (BIT(29) | BIT(28))) >> 28);\n\t\t\t\tif (c_cond == COND_ENDIF) {/*end*/\n\t\t\t\t\tis_matched = true;\n\t\t\t\t\tis_skipped = false;\n\t\t\t\t\tPHYDM_DBG(dm, ODM_COMP_INIT, \"ENDIF\\n\");\n\t\t\t\t} else if (c_cond == COND_ELSE) { /*else*/\n\t\t\t\t\tis_matched = is_skipped ? false : true;\n\t\t\t\t\tPHYDM_DBG(dm, ODM_COMP_INIT, \"ELSE\\n\");\n\t\t\t\t} else {/*if , else if*/\n\t\t\t\t\tpre_v1 = v1;\n\t\t\t\t\tpre_v2 = v2;\n\t\t\t\t\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t\t\t\t\t  \"IF or ELSE IF\\n\");\n\t\t\t\t}\n\t\t\t} else if (v1 & BIT(30)) { /*negative condition*/\n\t\t\t\tif (!is_skipped) {\n\t\t\t\t\ta1 = pre_v1; a2 = pre_v2;\n\t\t\t\t\ta3 = v1; a4 = v2;\n\t\t\t\t\tif (check_positive(dm,\n\t\t\t\t\t\t\t   a1, a2, a3, a4)) {\n\t\t\t\t\t\tis_matched = true;\n\t\t\t\t\t\tis_skipped = true;\n\t\t\t\t\t} else {\n\t\t\t\t\t\tis_matched = false;\n\t\t\t\t\t\tis_skipped = false;\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tis_matched = false;\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tif (is_matched)\n\t\t\t\todm_config_bb_agc_8822c(dm, v1, MASKDWORD, v2);\n\t\t}\n\t\ti = i + 2;\n\t}\n}\n\nu32\nodm_get_version_mp_8822c_agc_tab(void)\n{\n\t\treturn 41;\n}\n\n/******************************************************************************\n *                           phy_reg.TXT\n ******************************************************************************/\n\nconst u32 array_mp_8822c_phy_reg[] = {\n\t\t0x1D0C, 0x00410000,\n\t\t0x1C3C, 0x01038040,\n\t\t0x1C90, 0x00E49708,\n\t\t0x800, 0x00000000,\n\t\t0x804, 0xD6300000,\n\t\t0x808, 0x60956093,\n\t\t0x80C, 0x00000025,\n\t\t0x810, 0x11B019B0,\n\t\t0x814, 0x00904080,\n\t\t0x818, 0xC30056F1,\n\t\t0x81C, 0x00050000,\n\t\t0x820, 0x11111111,\n\t\t0x824, 0xC3C3CCC4,\n\t\t0x828, 0x30FB186C,\n\t\t0x82C, 0x185D6556,\n\t\t0x830, 0x1751145B,\n\t\t0x834, 0x776995D7,\n\t\t0x838, 0x74777A7D,\n\t\t0x83C, 0xF9AA9982,\n\t\t0x840, 0x89AA9ABB,\n\t\t0x844, 0x0DEEDDC1,\n\t\t0x848, 0xCDEEDEFF,\n\t\t0x84C, 0xFFFF5555,\n\t\t0x850, 0x6F7A727D,\n\t\t0x854, 0x6C776F7A,\n\t\t0x858, 0x6F7A6C77,\n\t\t0x85C, 0x69746974,\n\t\t0x860, 0x6F7A6C77,\n\t\t0x864, 0x6C776C77,\n\t\t0x868, 0x727D6F7A,\n\t\t0x86C, 0x69D7B196,\n\t\t0x870, 0x1A6D769B,\n\t\t0x874, 0x55823917,\n\t\t0x878, 0x00C025BD,\n\t\t0x87C, 0x4140557D,\n\t\t0x880, 0x9A1D9D47,\n\t\t0x884, 0x1DE7134F,\n\t\t0x888, 0x2857A857,\n\t\t0x88C, 0x520E8A24,\n\t\t0x890, 0x8F628C44,\n\t\t0x894, 0x72745F43,\n\t\t0x898, 0x03F02F0D,\n\t\t0x89C, 0x5DB6886F,\n\t\t0x8A0, 0x07DC309F,\n\t\t0x8A4, 0x09412495,\n\t\t0x8A8, 0x222222A9,\n\t\t0x8AC, 0x89628C44,\n\t\t0x8B0, 0x72745F43,\n\t\t0x8B4, 0x03F02F0D,\n\t\t0x8B8, 0x55B6886F,\n\t\t0x8BC, 0x07D0309F,\n\t\t0x8C0, 0x70404023,\n\t\t0x8C4, 0x00440001,\n\t\t0x8C8, 0x7A7A2E26,\n\t\t0x8CC, 0x25297777,\n\t\t0x8D0, 0x6CEB6DCE,\n\t\t0x8D4, 0x0005A632,\n\t\t0x8D8, 0x00000000,\n\t\t0x8DC, 0x00000000,\n\t\t0x8E0, 0x00000000,\n\t\t0x8E4, 0x00000000,\n\t\t0x8E8, 0x00000000,\n\t\t0x8EC, 0x00000000,\n\t\t0x8F0, 0x00000000,\n\t\t0x8F4, 0x00000000,\n\t\t0x8F8, 0x25239843,\n\t\t0x900, 0x00000000,\n\t\t0x904, 0x00000000,\n\t\t0x908, 0x000008CB,\n\t\t0x90C, 0x00000000,\n\t\t0x910, 0x00000000,\n\t\t0x914, 0x20000000,\n\t\t0x918, 0x20000000,\n\t\t0x91C, 0x20000000,\n\t\t0x920, 0x20000000,\n\t\t0x924, 0x00000000,\n\t\t0x928, 0x0000003A,\n\t\t0x92C, 0x0000003A,\n\t\t0x930, 0x0000003A,\n\t\t0x934, 0x0000003A,\n\t\t0x938, 0x0000000F,\n\t\t0x93C, 0x00000000,\n\t\t0x940, 0x4E1F3E81,\n\t\t0x944, 0x4E1F3E81,\n\t\t0x948, 0x4E1F3E81,\n\t\t0x94C, 0x4E1F3E81,\n\t\t0x950, 0x03020100,\n\t\t0x954, 0x07060504,\n\t\t0x958, 0x0B0A0908,\n\t\t0x95C, 0x0F0E0D0C,\n\t\t0x960, 0x13121110,\n\t\t0x964, 0x17161514,\n\t\t0x968, 0x03020100,\n\t\t0x96C, 0x07060504,\n\t\t0x970, 0x0B0A0908,\n\t\t0x974, 0x0F0E0D0C,\n\t\t0x978, 0x13121110,\n\t\t0x97C, 0x17161514,\n\t\t0x980, 0x03020100,\n\t\t0x984, 0x07060504,\n\t\t0x988, 0x0B0A0908,\n\t\t0x98C, 0x0F0E0D0C,\n\t\t0x990, 0x13121110,\n\t\t0x994, 0x17161514,\n\t\t0x998, 0x03020100,\n\t\t0x99C, 0x07060504,\n\t\t0x9A0, 0x0B0A0908,\n\t\t0x9A4, 0x0F0E0D0C,\n\t\t0x9A8, 0x13121110,\n\t\t0x9AC, 0x17161514,\n\t\t0x9B0, 0x00002200,\n\t\t0x9B4, 0xDB6FFF00,\n\t\t0x9B8, 0x00400064,\n\t\t0x9BC, 0x00000000,\n\t\t0x9C0, 0x01010101,\n\t\t0x9C4, 0x00640064,\n\t\t0x9C8, 0x00640064,\n\t\t0x9CC, 0x00007777,\n\t\t0x9D0, 0x00000000,\n\t\t0x9D4, 0x00000000,\n\t\t0x9D8, 0x00000000,\n\t\t0x9DC, 0x00000000,\n\t\t0x9E0, 0x00000000,\n\t\t0x9E4, 0x00000000,\n\t\t0x9E8, 0x00000000,\n\t\t0x9EC, 0x00000000,\n\t\t0x9F0, 0x100024E0,\n\t\t0x9F4, 0x00000000,\n\t\t0x9F8, 0x00000000,\n\t\t0xA00, 0x02001208,\n\t\t0xA04, 0x00000000,\n\t\t0xA08, 0x00000000,\n\t\t0xA0C, 0x00000000,\n\t\t0xA10, 0x00000000,\n\t\t0xA14, 0x00000000,\n\t\t0xA18, 0x00000000,\n\t\t0xA1C, 0x00000000,\n\t\t0xA20, 0xCB31B333,\n\t\t0xA24, 0x00275485,\n\t\t0xA28, 0x00166366,\n\t\t0xA2C, 0x00275485,\n\t\t0xA30, 0x00166366,\n\t\t0xA34, 0x00275485,\n\t\t0xA38, 0x00200400,\n\t\t0xA3C, 0x00200400,\n\t\t0xA40, 0xB35DC5BD,\n\t\t0xA44, 0x3033BEBD,\n\t\t0xA48, 0x2A521254,\n\t\t0xA4C, 0xA2733345,\n\t\t0xA50, 0x617BE003,\n\t\t0xA54, 0x50000968,\n\t\t0xA58, 0x00020000,\n\t\t0xA5C, 0x01000000,\n\t\t0xA60, 0x02000000,\n\t\t0xA64, 0x03000000,\n\t\t0xA68, 0x00020000,\n\t\t0xA6C, 0x00000000,\n\t\t0xA70, 0x00000000,\n\t\t0xA74, 0x00000000,\n\t\t0xA78, 0x00000000,\n\t\t0xA7C, 0x00000000,\n\t\t0xA80, 0x00000000,\n\t\t0xA84, 0x00000000,\n\t\t0xA88, 0x00000000,\n\t\t0xA8C, 0x00000000,\n\t\t0xA90, 0x00000000,\n\t\t0xA94, 0x00000000,\n\t\t0xA98, 0x00000000,\n\t\t0xA9C, 0x00000000,\n\t\t0xAA0, 0x00000000,\n\t\t0xAA4, 0x00000000,\n\t\t0xAA8, 0x00000000,\n\t\t0xAAC, 0x00000000,\n\t\t0xAB0, 0x00000000,\n\t\t0xAB4, 0x00000000,\n\t\t0xAB8, 0x00000000,\n\t\t0xABC, 0x00000000,\n\t\t0xAC0, 0x00000000,\n\t\t0xAC4, 0x00000000,\n\t\t0xAC8, 0x00000000,\n\t\t0xACC, 0x00000000,\n\t\t0xAD0, 0x00000000,\n\t\t0xAD4, 0x00000000,\n\t\t0xAD8, 0x00000000,\n\t\t0xADC, 0x00000000,\n\t\t0xAE0, 0x00000000,\n\t\t0xAE4, 0x00000000,\n\t\t0xAE8, 0x00000000,\n\t\t0xAEC, 0x00000000,\n\t\t0xAF0, 0x00000000,\n\t\t0xAF4, 0x00000000,\n\t\t0xAF8, 0x00000000,\n\t\t0xB00, 0x00000000,\n\t\t0xB04, 0x00000000,\n\t\t0xB08, 0x00000000,\n\t\t0xB0C, 0x00000000,\n\t\t0xB10, 0x00000000,\n\t\t0xB14, 0x00000000,\n\t\t0xB18, 0x00000000,\n\t\t0xB1C, 0x00000000,\n\t\t0xB20, 0x00000000,\n\t\t0xB24, 0x00000000,\n\t\t0xB28, 0x00000000,\n\t\t0xB2C, 0x00000000,\n\t\t0xB30, 0x00000000,\n\t\t0xB34, 0x00000000,\n\t\t0xB38, 0x00000000,\n\t\t0xB3C, 0x00000000,\n\t\t0xB40, 0x00000000,\n\t\t0xB44, 0x00000000,\n\t\t0xB48, 0x00000000,\n\t\t0xB4C, 0x00000000,\n\t\t0xB50, 0x00000000,\n\t\t0xB54, 0x00000000,\n\t\t0xB58, 0x00060100,\n\t\t0xB5C, 0x00000000,\n\t\t0xB60, 0x00000000,\n\t\t0xB64, 0x00000000,\n\t\t0xB68, 0x00000000,\n\t\t0xB6C, 0x00000000,\n\t\t0xB70, 0x00000000,\n\t\t0xB74, 0x00000000,\n\t\t0xB78, 0x00000000,\n\t\t0xB7C, 0x00000000,\n\t\t0xB80, 0x00000000,\n\t\t0xB84, 0x00000000,\n\t\t0xB88, 0x00000000,\n\t\t0xB8C, 0x00000000,\n\t\t0xB90, 0x00000000,\n\t\t0xB94, 0x00000000,\n\t\t0xB98, 0x00000000,\n\t\t0xB9C, 0x00000000,\n\t\t0xBA0, 0x00000000,\n\t\t0xBA4, 0x00000000,\n\t\t0xBA8, 0x00000000,\n\t\t0xBAC, 0x00000000,\n\t\t0xBB0, 0x00000000,\n\t\t0xBB4, 0x00000000,\n\t\t0xBB8, 0x00000000,\n\t\t0xBBC, 0x00000000,\n\t\t0xBC0, 0x00000000,\n\t\t0xBC4, 0x00000000,\n\t\t0xBC8, 0x00000000,\n\t\t0xBCC, 0x00000000,\n\t\t0xBD0, 0x00000000,\n\t\t0xBD4, 0x00000000,\n\t\t0xBD8, 0x00000000,\n\t\t0xBDC, 0x00000000,\n\t\t0xBE0, 0x00000000,\n\t\t0xBE4, 0x00000000,\n\t\t0xBE8, 0x00000000,\n\t\t0xBEC, 0x00000000,\n\t\t0xBF0, 0x00000000,\n\t\t0xBF4, 0x00000000,\n\t\t0xBF8, 0x00000000,\n\t\t0xC00, 0x0C8BA0D6,\n\t\t0xC04, 0x00000001,\n\t\t0xC08, 0x00000000,\n\t\t0xC0C, 0x02F1D8B7,\n\t\t0xC10, 0x000000B0,\n\t\t0xC14, 0x0000D891,\n\t\t0xC18, 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0x62F508C4,\n\t\t0x1814, 0x506AA5B4,\n\t\t0x1818, 0x000014FF,\n\t\t0x181C, 0x00000000,\n\t\t0x1820, 0x02D508CC,\n\t\t0x1824, 0x506AA5B4,\n\t\t0x1828, 0x000004FD,\n\t\t0x182C, 0x00000000,\n\t\t0x1834, 0x00000000,\n\t\t0x1838, 0x20000000,\n\t\t0x183C, 0x00000000,\n\t\t0x1840, 0x00000000,\n\t\t0x1844, 0x00000000,\n\t\t0x1848, 0x00000000,\n\t\t0x184C, 0x00000000,\n\t\t0x1850, 0x00000000,\n\t\t0x1854, 0x00000000,\n\t\t0x1858, 0x00000000,\n\t\t0x185C, 0x00000000,\n\t\t0x1860, 0xF0040FF8,\n\t\t0x1864, 0x7F000000,\n\t\t0x1868, 0x00000000,\n\t\t0x186C, 0x0000FF00,\n\t\t0x1870, 0x00000000,\n\t\t0x1874, 0x00000000,\n\t\t0x1878, 0x00000000,\n\t\t0x187C, 0x00000000,\n\t\t0x1880, 0x00000000,\n\t\t0x1884, 0x02B00000,\n\t\t0x1888, 0x00000000,\n\t\t0x188C, 0x00000000,\n\t\t0x1890, 0x00000000,\n\t\t0x1894, 0x00000000,\n\t\t0x1898, 0x00000000,\n\t\t0x18A0, 0x00510000,\n\t\t0x18A4, 0x183C1F7F,\n\t\t0x18A8, 0x0A02C99A,\n\t\t0x18AC, 0x00004200,\n\t\t0x18B0, 0x0809FB08,\n\t\t0x18B0, 0x0809FB09,\n\t\t0x18B4, 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0x00000000,\n\t\t0x1AF8, 0x00000000,\n\t\t0x1AFC, 0x00000000,\n\t\t0x1D0C, 0x00400000,\n\t\t0x1D0C, 0x00410000,\n\t\t0x1EE8, 0x00000003,\n\t\t0xC0C, 0x02F1D8BF,\n\t\t0x1D94, 0x40000000,\n\t\t0x1D94, 0x40010000,\n\t\t0x1D94, 0x40020000,\n\t\t0x1D94, 0x40030000,\n\t\t0x1D94, 0x40040000,\n\t\t0x1D94, 0x40050000,\n\t\t0x1D94, 0x40060000,\n\t\t0x1D94, 0x40070000,\n\t\t0x1D94, 0x40080000,\n\t\t0x1D94, 0x40090000,\n\t\t0x1D94, 0x400A0000,\n\t\t0x1D94, 0x400B0000,\n\t\t0x1D94, 0x400C0000,\n\t\t0x1D94, 0x400D0000,\n\t\t0x1D94, 0x400E0000,\n\t\t0x1D94, 0x400F0000,\n\t\t0x1D94, 0x40100000,\n\t\t0x1D94, 0x40110000,\n\t\t0x1D94, 0x40120000,\n\t\t0x1D94, 0x40130000,\n\t\t0x1D94, 0x40140000,\n\t\t0x1D94, 0x40150000,\n\t\t0x1D94, 0x40160000,\n\t\t0x1D94, 0x40170000,\n\t\t0x1D94, 0x40180000,\n\t\t0x1D94, 0x40190000,\n\t\t0x1D94, 0x401A0000,\n\t\t0x1D94, 0x401B0000,\n\t\t0x1D94, 0x401C0000,\n\t\t0x1D94, 0x401D0000,\n\t\t0x1D94, 0x401E0000,\n\t\t0x1D94, 0x401F0000,\n\t\t0x1D94, 0x40200000,\n\t\t0x1D94, 0x40210000,\n\t\t0x1D94, 0x40220000,\n\t\t0x1D94, 0x40230000,\n\t\t0x1D94, 0x40240000,\n\t\t0x1D94, 0x40250000,\n\t\t0x1D94, 0x40260000,\n\t\t0x1D94, 0x40270000,\n\t\t0x1D94, 0x40280000,\n\t\t0x1D94, 0x40290000,\n\t\t0x1D94, 0x402A0000,\n\t\t0x1D94, 0x402B0000,\n\t\t0x1D94, 0x402C0000,\n\t\t0x1D94, 0x402D0000,\n\t\t0x1D94, 0x402E0000,\n\t\t0x1D94, 0x402F0000,\n\t\t0x1D94, 0x40300000,\n\t\t0x1D94, 0x40310000,\n\t\t0x1D94, 0x40320000,\n\t\t0x1D94, 0x40330000,\n\t\t0x1D94, 0x40340000,\n\t\t0x1D94, 0x40350000,\n\t\t0x1D94, 0x40360000,\n\t\t0x1D94, 0x40370000,\n\t\t0x1D94, 0x40380000,\n\t\t0x1D94, 0x40390000,\n\t\t0x1D94, 0x403A0000,\n\t\t0x1D94, 0x403B0000,\n\t\t0x1D94, 0x403C0000,\n\t\t0x1D94, 0x403D0000,\n\t\t0x1D94, 0x403E0000,\n\t\t0x1D94, 0x403F0000,\n\t\t0x1D94, 0x40400000,\n\t\t0x1D94, 0x40410000,\n\t\t0x1D94, 0x40420000,\n\t\t0x1D94, 0x40430000,\n\t\t0x1D94, 0x40440000,\n\t\t0x1D94, 0x40450000,\n\t\t0x1D94, 0x40460000,\n\t\t0x1D94, 0x40470000,\n\t\t0x1D94, 0x40480000,\n\t\t0x1D94, 0x40490000,\n\t\t0x1D94, 0x404A0000,\n\t\t0x1D94, 0x404B0000,\n\t\t0x1D94, 0x404C0000,\n\t\t0x1D94, 0x404D0000,\n\t\t0x1D94, 0x404E0000,\n\t\t0x1D94, 0x404F0000,\n\t\t0x1D94, 0x40500000,\n\t\t0x1D94, 0x40510000,\n\t\t0x1D94, 0x40520000,\n\t\t0x1D94, 0x40530000,\n\t\t0x1D94, 0x40540000,\n\t\t0x1D94, 0x40550000,\n\t\t0x1D94, 0x40560000,\n\t\t0x1D94, 0x40570000,\n\t\t0x1D94, 0x40580000,\n\t\t0x1D94, 0x40590000,\n\t\t0x1D94, 0x405A0000,\n\t\t0x1D94, 0x405B0000,\n\t\t0x1D94, 0x405C0000,\n\t\t0x1D94, 0x405D0000,\n\t\t0x1D94, 0x405E0000,\n\t\t0x1D94, 0x405F0000,\n\t\t0x1D94, 0x40600000,\n\t\t0x1D94, 0x40610000,\n\t\t0x1D94, 0x40620000,\n\t\t0x1D94, 0x40630000,\n\t\t0x1D94, 0x40640000,\n\t\t0x1D94, 0x40650000,\n\t\t0x1D94, 0x40660000,\n\t\t0x1D94, 0x40670000,\n\t\t0x1D94, 0x40680000,\n\t\t0x1D94, 0x40690000,\n\t\t0x1D94, 0x406A0000,\n\t\t0x1D94, 0x406B0000,\n\t\t0x1D94, 0x406C0000,\n\t\t0x1D94, 0x406D0000,\n\t\t0x1D94, 0x406E0000,\n\t\t0x1D94, 0x406F0000,\n\t\t0x1D94, 0x40700000,\n\t\t0x1D94, 0x40710000,\n\t\t0x1D94, 0x40720000,\n\t\t0x1D94, 0x40730000,\n\t\t0x1D94, 0x40740000,\n\t\t0x1D94, 0x40750000,\n\t\t0x1D94, 0x40760000,\n\t\t0x1D94, 0x40770000,\n\t\t0x1D94, 0x40780000,\n\t\t0x1D94, 0x40790000,\n\t\t0x1D94, 0x407A0000,\n\t\t0x1D94, 0x407B0000,\n\t\t0x1D94, 0x407C0000,\n\t\t0x1D94, 0x407D0000,\n\t\t0x1D94, 0x407E0000,\n\t\t0x1D94, 0x407F0000,\n\t\t0x1D94, 0x40800000,\n\t\t0x1D94, 0x40810000,\n\t\t0x1D94, 0x40820000,\n\t\t0x1D94, 0x40830000,\n\t\t0x1D94, 0x40840000,\n\t\t0x1D94, 0x40850000,\n\t\t0x1D94, 0x40860000,\n\t\t0x1D94, 0x40870000,\n\t\t0x1D94, 0x40880000,\n\t\t0x1D94, 0x40890000,\n\t\t0x1D94, 0x408A0000,\n\t\t0x1D94, 0x408B0000,\n\t\t0x1D94, 0x408C0000,\n\t\t0x1D94, 0x408D0000,\n\t\t0x1D94, 0x408E0000,\n\t\t0x1D94, 0x408F0000,\n\t\t0x1D94, 0x40900000,\n\t\t0x1D94, 0x40910000,\n\t\t0x1D94, 0x40920000,\n\t\t0x1D94, 0x40930000,\n\t\t0x1D94, 0x40940000,\n\t\t0x1D94, 0x40950000,\n\t\t0x1D94, 0x40960000,\n\t\t0x1D94, 0x40970000,\n\t\t0x1D94, 0x40980000,\n\t\t0x1D94, 0x40990000,\n\t\t0x1D94, 0x409A0000,\n\t\t0x1D94, 0x409B0000,\n\t\t0x1D94, 0x409C0000,\n\t\t0x1D94, 0x409D0000,\n\t\t0x1D94, 0x409E0000,\n\t\t0x1D94, 0x409F0000,\n\t\t0x1D94, 0x40A00000,\n\t\t0x1D94, 0x40A10000,\n\t\t0x1D94, 0x40A20000,\n\t\t0x1D94, 0x40A30000,\n\t\t0x1D94, 0x40A40000,\n\t\t0x1D94, 0x40A50000,\n\t\t0x1D94, 0x40A60000,\n\t\t0x1D94, 0x40A70000,\n\t\t0x1D94, 0x40A80000,\n\t\t0x1D94, 0x40A90000,\n\t\t0x1D94, 0x40AA0000,\n\t\t0x1D94, 0x40AB0000,\n\t\t0x1D94, 0x40AC0000,\n\t\t0x1D94, 0x40AD0000,\n\t\t0x1D94, 0x40AE0000,\n\t\t0x1D94, 0x40AF0000,\n\t\t0x1D94, 0x40B00000,\n\t\t0x1D94, 0x40B10000,\n\t\t0x1D94, 0x40B20000,\n\t\t0x1D94, 0x40B30000,\n\t\t0x1D94, 0x40B40000,\n\t\t0x1D94, 0x40B50000,\n\t\t0x1D94, 0x40B60000,\n\t\t0x1D94, 0x40B70000,\n\t\t0x1D94, 0x40B80000,\n\t\t0x1D94, 0x40B90000,\n\t\t0x1D94, 0x40BA0000,\n\t\t0x1D94, 0x40BB0000,\n\t\t0x1D94, 0x40BC0000,\n\t\t0x1D94, 0x40BD0000,\n\t\t0x1D94, 0x40BE0000,\n\t\t0x1D94, 0x40BF0000,\n\t\t0x1D94, 0x40C00000,\n\t\t0x1D94, 0x40C10000,\n\t\t0x1D94, 0x40C20000,\n\t\t0x1D94, 0x40C30000,\n\t\t0x1D94, 0x40C40000,\n\t\t0x1D94, 0x40C50000,\n\t\t0x1D94, 0x40C60000,\n\t\t0x1D94, 0x40C70000,\n\t\t0x1D94, 0x40C80000,\n\t\t0x1D94, 0x40C90000,\n\t\t0x1D94, 0x40CA0000,\n\t\t0x1D94, 0x40CB0000,\n\t\t0x1D94, 0x40CC0000,\n\t\t0x1D94, 0x40CD0000,\n\t\t0x1D94, 0x40CE0000,\n\t\t0x1D94, 0x40CF0000,\n\t\t0x1D94, 0x40D00000,\n\t\t0x1D94, 0x40D10000,\n\t\t0x1D94, 0x40D20000,\n\t\t0x1D94, 0x40D30000,\n\t\t0x1D94, 0x40D40000,\n\t\t0x1D94, 0x40D50000,\n\t\t0x1D94, 0x40D60000,\n\t\t0x1D94, 0x40D70000,\n\t\t0x1D94, 0x40D80000,\n\t\t0x1D94, 0x40D90000,\n\t\t0x1D94, 0x40DA0000,\n\t\t0x1D94, 0x40DB0000,\n\t\t0x1D94, 0x40DC0000,\n\t\t0x1D94, 0x40DD0000,\n\t\t0x1D94, 0x40DE0000,\n\t\t0x1D94, 0x40DF0000,\n\t\t0x1D94, 0x40E00000,\n\t\t0x1D94, 0x40E10000,\n\t\t0x1D94, 0x40E20000,\n\t\t0x1D94, 0x40E30000,\n\t\t0x1D94, 0x40E40000,\n\t\t0x1D94, 0x40E50000,\n\t\t0x1D94, 0x40E60000,\n\t\t0x1D94, 0x40E70000,\n\t\t0x1D94, 0x40E80000,\n\t\t0x1D94, 0x40E90000,\n\t\t0x1D94, 0x40EA0000,\n\t\t0x1D94, 0x40EB0000,\n\t\t0x1D94, 0x40EC0000,\n\t\t0x1D94, 0x40ED0000,\n\t\t0x1D94, 0x40EE0000,\n\t\t0x1D94, 0x40EF0000,\n\t\t0x1D94, 0x40F00000,\n\t\t0x1D94, 0x40F10000,\n\t\t0x1D94, 0x40F20000,\n\t\t0x1D94, 0x40F30000,\n\t\t0x1D94, 0x40F40000,\n\t\t0x1D94, 0x40F50000,\n\t\t0x1D94, 0x40F60000,\n\t\t0x1D94, 0x40F70000,\n\t\t0x1D94, 0x40F80000,\n\t\t0x1D94, 0x40F90000,\n\t\t0x1D94, 0x40FA0000,\n\t\t0x1D94, 0x40FB0000,\n\t\t0x1D94, 0x40FC0000,\n\t\t0x1D94, 0x40FD0000,\n\t\t0x1D94, 0x40FE0000,\n\t\t0x1D94, 0x40FF0000,\n\t\t0xC0C, 0x02F1D8B7,\n\t\t0x1EE8, 0x00000000,\n\n};\n\nvoid\nodm_read_and_config_mp_8822c_phy_reg(struct dm_struct *dm)\n{\n\tu32\ti = 0;\n\tu8\tc_cond;\n\tboolean\tis_matched = true, is_skipped = false;\n\tu32\tarray_len =\n\t\t\tsizeof(array_mp_8822c_phy_reg) / sizeof(u32);\n\tu32\t*array = (u32 *)array_mp_8822c_phy_reg;\n\n\tu32\tv1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;\n\tu32\ta1 = 0, a2 = 0, a3 = 0, a4 = 0;\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"===> %s\\n\", __func__);\n\n\twhile ((i + 1) < array_len) {\n\t\tv1 = array[i];\n\t\tv2 = array[i + 1];\n\n\t\tif (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/\n\t\t\tif (v1 & BIT(31)) {/* positive condition*/\n\t\t\t\tc_cond  =\n\t\t\t\t\t(u8)((v1 & (BIT(29) | BIT(28))) >> 28);\n\t\t\t\tif (c_cond == COND_ENDIF) {/*end*/\n\t\t\t\t\tis_matched = true;\n\t\t\t\t\tis_skipped = false;\n\t\t\t\t\tPHYDM_DBG(dm, ODM_COMP_INIT, \"ENDIF\\n\");\n\t\t\t\t} else if (c_cond == COND_ELSE) { /*else*/\n\t\t\t\t\tis_matched = is_skipped ? false : true;\n\t\t\t\t\tPHYDM_DBG(dm, ODM_COMP_INIT, \"ELSE\\n\");\n\t\t\t\t} else {/*if , else if*/\n\t\t\t\t\tpre_v1 = v1;\n\t\t\t\t\tpre_v2 = v2;\n\t\t\t\t\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t\t\t\t\t  \"IF or ELSE IF\\n\");\n\t\t\t\t}\n\t\t\t} else if (v1 & BIT(30)) { /*negative condition*/\n\t\t\t\tif (!is_skipped) {\n\t\t\t\t\ta1 = pre_v1; a2 = pre_v2;\n\t\t\t\t\ta3 = v1; a4 = v2;\n\t\t\t\t\tif (check_positive(dm,\n\t\t\t\t\t\t\t   a1, a2, a3, a4)) {\n\t\t\t\t\t\tis_matched = true;\n\t\t\t\t\t\tis_skipped = true;\n\t\t\t\t\t} else {\n\t\t\t\t\t\tis_matched = false;\n\t\t\t\t\t\tis_skipped = false;\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tis_matched = false;\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tif (is_matched)\n\t\t\t\todm_config_bb_phy_8822c(dm, v1, MASKDWORD, v2);\n\t\t}\n\t\ti = i + 2;\n\t}\n}\n\nu32\nodm_get_version_mp_8822c_phy_reg(void)\n{\n\t\treturn 41;\n}\n\n/******************************************************************************\n *                           phy_reg_pg.TXT\n ******************************************************************************/\n\n#ifdef CONFIG_8822C\nconst u32 array_mp_8822c_phy_reg_pg[] = {\n\t0, 0, 0, 0x00000c20, 0xffffffff, 0x484c5054,\n\t0, 0, 0, 0x00000c24, 0xffffffff, 0x54585858,\n\t0, 0, 0, 0x00000c28, 0xffffffff, 0x44484c50,\n\t0, 0, 0, 0x00000c2c, 0xffffffff, 0x50545858,\n\t0, 0, 0, 0x00000c30, 0xffffffff, 0x4044484c,\n\t0, 0, 1, 0x00000c34, 0xffffffff, 0x50545858,\n\t0, 0, 1, 0x00000c38, 0xffffffff, 0x4044484c,\n\t0, 0, 0, 0x00000c3c, 0xffffffff, 0x50545858,\n\t0, 0, 0, 0x00000c40, 0xffffffff, 0x4044484c,\n\t0, 0, 0, 0x00000c44, 0xffffffff, 0x5858383c,\n\t0, 0, 1, 0x00000c48, 0xffffffff, 0x484c5054,\n\t0, 0, 1, 0x00000c4c, 0xffffffff, 0x383c4044,\n\t0, 1, 0, 0x00000e20, 0xffffffff, 0x484c5054,\n\t0, 1, 0, 0x00000e24, 0xffffffff, 0x54585858,\n\t0, 1, 0, 0x00000e28, 0xffffffff, 0x44484c50,\n\t0, 1, 0, 0x00000e2c, 0xffffffff, 0x50545858,\n\t0, 1, 0, 0x00000e30, 0xffffffff, 0x4044484c,\n\t0, 1, 1, 0x00000e34, 0xffffffff, 0x50545858,\n\t0, 1, 1, 0x00000e38, 0xffffffff, 0x4044484c,\n\t0, 1, 0, 0x00000e3c, 0xffffffff, 0x50545858,\n\t0, 1, 0, 0x00000e40, 0xffffffff, 0x4044484c,\n\t0, 1, 0, 0x00000e44, 0xffffffff, 0x5858383c,\n\t0, 1, 1, 0x00000e48, 0xffffffff, 0x484c5054,\n\t0, 1, 1, 0x00000e4c, 0xffffffff, 0x383c4044,\n\t1, 0, 0, 0x00000c24, 0xffffffff, 0x54585858,\n\t1, 0, 0, 0x00000c28, 0xffffffff, 0x44484c50,\n\t1, 0, 0, 0x00000c2c, 0xffffffff, 0x50545858,\n\t1, 0, 0, 0x00000c30, 0xffffffff, 0x4044484c,\n\t1, 0, 1, 0x00000c34, 0xffffffff, 0x50545858,\n\t1, 0, 1, 0x00000c38, 0xffffffff, 0x4044484c,\n\t1, 0, 0, 0x00000c3c, 0xffffffff, 0x50545858,\n\t1, 0, 0, 0x00000c40, 0xffffffff, 0x4044484c,\n\t1, 0, 0, 0x00000c44, 0xffffffff, 0x5858383c,\n\t1, 0, 1, 0x00000c48, 0xffffffff, 0x484c5054,\n\t1, 0, 1, 0x00000c4c, 0xffffffff, 0x383c4044,\n\t1, 1, 0, 0x00000e24, 0xffffffff, 0x54585858,\n\t1, 1, 0, 0x00000e28, 0xffffffff, 0x44484c50,\n\t1, 1, 0, 0x00000e2c, 0xffffffff, 0x50545858,\n\t1, 1, 0, 0x00000e30, 0xffffffff, 0x4044484c,\n\t1, 1, 1, 0x00000e34, 0xffffffff, 0x50545858,\n\t1, 1, 1, 0x00000e38, 0xffffffff, 0x4044484c,\n\t1, 1, 0, 0x00000e3c, 0xffffffff, 0x50545858,\n\t1, 1, 0, 0x00000e40, 0xffffffff, 0x4044484c,\n\t1, 1, 0, 0x00000e44, 0xffffffff, 0x5858383c,\n\t1, 1, 1, 0x00000e48, 0xffffffff, 0x484c5054,\n\t1, 1, 1, 0x00000e4c, 0xffffffff, 0x383c4044\n};\n\n#endif\n\nvoid\nodm_read_and_config_mp_8822c_phy_reg_pg(struct dm_struct *dm)\n{\n#ifdef CONFIG_8822C\n\n\tu32 i = 0;\n\tu32 array_len =\n\t\t sizeof(array_mp_8822c_phy_reg_pg) / sizeof(u32);\n\tu32 *array = (u32 *)array_mp_8822c_phy_reg_pg;\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid\t*adapter = dm->adapter;\n\tHAL_DATA_TYPE\t*hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\n\todm_memory_set(dm, hal_data->BufOfLinesPwrByRate, 0,\n\t\t       MAX_LINES_HWCONFIG_TXT *\n\t\t       MAX_BYTES_LINE_HWCONFIG_TXT);\n\thal_data->nLinesReadPwrByRate = array_len / 6;\n#endif\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"===> %s\\n\", __func__);\n\n\tdm->phy_reg_pg_version = 2;\n\tdm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;\n\n\tfor (i = 0; i < array_len; i += 6) {\n\t\tu32\tv1 = array[i];\n\t\tu32\tv2 = array[i + 1];\n\t\tu32\tv3 = array[i + 2];\n\t\tu32\tv4 = array[i + 3];\n\t\tu32\tv5 = array[i + 4];\n\t\tu32\tv6 = array[i + 5];\n\n\t\todm_config_bb_phy_reg_pg_8822c(dm, v1, v2, v3, v4, v5, v6);\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\trsprintf((char *)hal_data->BufOfLinesPwrByRate[i / 6], 100,\n\t\t \"%s, %s, %s, 0x%X, 0x%08X, 0x%08X,\",\n\t\t (v1 == 0 ? \"2.4G\" : \"  5G\"), (v2 == 0 ? \"A\" : \"B\"),\n\t\t (v3 == 0 ? \"1Tx\" : \"2Tx\"), v4, v5, v6);\n#endif\n\t}\n#endif\n}\n\n#endif /* end of HWIMG_SUPPORT*/\n\n"
  },
  {
    "path": "hal/phydm/rtl8822c/halhwimg8822c_bb.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n/*Image2HeaderVersion: R3 1.5.8*/\n#if (RTL8822C_SUPPORT == 1)\n#ifndef __INC_MP_BB_HW_IMG_8822C_H\n#define __INC_MP_BB_HW_IMG_8822C_H\n\n/******************************************************************************\n *                           agc_tab.TXT\n ******************************************************************************/\n\n/* tc: Test Chip, mp: mp Chip*/\nvoid\nodm_read_and_config_mp_8822c_agc_tab(struct dm_struct *dm);\nu32 odm_get_version_mp_8822c_agc_tab(void);\n\n/******************************************************************************\n *                           phy_reg.TXT\n ******************************************************************************/\n\n/* tc: Test Chip, mp: mp Chip*/\nvoid\nodm_read_and_config_mp_8822c_phy_reg(struct dm_struct *dm);\nu32 odm_get_version_mp_8822c_phy_reg(void);\n\n/******************************************************************************\n *                           phy_reg_pg.TXT\n ******************************************************************************/\n\n/* tc: Test Chip, mp: mp Chip*/\nvoid\nodm_read_and_config_mp_8822c_phy_reg_pg(struct dm_struct *dm);\nu32 odm_get_version_mp_8822c_phy_reg_pg(void);\n\n#endif\n#endif /* end of HWIMG_SUPPORT*/\n\n"
  },
  {
    "path": "hal/phydm/rtl8822c/mp_precomp.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n"
  },
  {
    "path": "hal/phydm/rtl8822c/phydm_hal_api8822c.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#include \"mp_precomp.h\"\n#include \"../phydm_precomp.h\"\n\n#if (RTL8822C_SUPPORT)\n#if (PHYDM_FW_API_ENABLE_8822C)\n/* ======================================================================== */\n/* These following functions can be used for PHY DM only*/\n\nenum channel_width bw_8822c;\n\n#ifdef CONFIG_TXAGC_DEBUG_8822C\n__odm_func__\nboolean phydm_set_pw_by_rate_8822c(struct dm_struct *dm, s8 *pw_idx,\n\t\t\t\t   u8 rate_idx)\n{\n\tu32 pw_all = 0;\n\tu8 j = 0;\n\n\tif (rate_idx % 4 != 0) {\n\t\tpr_debug(\"[Warning] %s\\n\", __func__);\n\t\treturn false;\n\t}\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"pow = {%d, %d, %d, %d}\\n\",\n\t\t  *pw_idx, *(pw_idx - 1), *(pw_idx - 2), *(pw_idx - 3));\n\n\t/* @bbrstb TX AGC report - default disable */\n\t/* @Enable for writing the TX AGC table when bb_reset=0 */\n\todm_set_bb_reg(dm, R_0x1c90, BIT(15), 0x0);\n\n\t/* @According the rate to write in the ofdm or the cck */\n\t/* @driver need to construct a 4-byte power index */\n\todm_set_bb_reg(dm, 0x3a00 + rate_idx, MASKDWORD, pw_all);\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"rate_idx=0x%x (REG0x%x) = 0x%x\\n\",\n\t\t  rate_idx, 0x3a00 + rate_idx, pw_all);\n\n\tfor (j = 0; j < 4; j++)\n\t\tconfig_phydm_read_txagc_diff_8822c(dm, rate_idx + j);\n\n\treturn true;\n}\n\n__odm_func__\nvoid phydm_txagc_tab_buff_init_8822c(struct dm_struct *dm)\n{\n\tu8 i;\n\n\tfor (i = 0; i < NUM_RATE_AC_2SS; i++) {\n\t\tdm->txagc_buff[RF_PATH_A][i] = i >> 2;\n\t\tdm->txagc_buff[RF_PATH_B][i] = i >> 2;\n\t}\n}\n\n__odm_func__\nvoid phydm_txagc_tab_buff_show_8822c(struct dm_struct *dm)\n{\n\tu8 i;\n\n\tpr_debug(\"path A\\n\");\n\tfor (i = 0; i < NUM_RATE_AC_2SS; i++)\n\t\tpr_debug(\"[A][rate:%d] = %d\\n\", i,\n\t\t\t dm->txagc_buff[RF_PATH_A][i]);\n\tpr_debug(\"path B\\n\");\n\tfor (i = 0; i < NUM_RATE_AC_2SS; i++)\n\t\tpr_debug(\"[B][rate:%d] = %d\\n\", i,\n\t\t\t dm->txagc_buff[RF_PATH_B][i]);\n}\n#endif\n\n__odm_func__\nvoid phydm_bb_reset_8822c(struct dm_struct *dm)\n{\n\tif (*dm->mp_mode) \n\t\treturn;\n\n\todm_set_mac_reg(dm, R_0x0, BIT(16), 1);\n\todm_set_mac_reg(dm, R_0x0, BIT(16), 0);\n\todm_set_mac_reg(dm, R_0x0, BIT(16), 1);\n}\n\n__odm_func__\nvoid phydm_igi_toggle_8822c(struct dm_struct *dm)\n{\n\tu32 igi = 0x20;\n\n\t/* @Do not use PHYDM API to read/write because FW can not access */\n\tigi = odm_get_bb_reg(dm, R_0x1d70, 0x7f);\n\todm_set_bb_reg(dm, R_0x1d70, 0x7f, igi - 2);\n\todm_set_bb_reg(dm, R_0x1d70, 0x7f00, igi - 2);\n\todm_set_bb_reg(dm, R_0x1d70, 0x7f, igi);\n\todm_set_bb_reg(dm, R_0x1d70, 0x7f00, igi);\n}\n\n__odm_func__\nu32 phydm_check_bit_mask_8822c(u32 bit_mask, u32 data_original, u32 data)\n{\n\tu8 bit_shift = 0;\n\n\tif (bit_mask != 0xfffff) {\n\t\tfor (bit_shift = 0; bit_shift <= 19; bit_shift++) {\n\t\t\tif ((bit_mask >> bit_shift) & 0x1)\n\t\t\t\tbreak;\n\t\t}\n\t\treturn (data_original & (~bit_mask)) | (data << bit_shift);\n\t}\n\n\treturn data;\n}\n\n__odm_func__\nu32 config_phydm_read_rf_reg_8822c(struct dm_struct *dm, enum rf_path path,\n\t\t\t\t   u32 reg_addr, u32 bit_mask)\n{\n\tu32 readback_value = 0, direct_addr = 0;\n\tu32 offset_read_rf[2] = {0x3c00, 0x4c00};\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"%s ======>\\n\", __func__);\n\n\t/* @Error handling.*/\n\tif (path > RF_PATH_B) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Unsupported path (%d)\\n\", path);\n\t\treturn INVALID_RF_DATA;\n\t}\n\n\t/* @Calculate offset */\n\treg_addr &= 0xff;\n\tdirect_addr = offset_read_rf[path] + (reg_addr << 2);\n\n\t/* @RF register only has 20bits */\n\tbit_mask &= RFREG_MASK;\n\n\t/* @Read RF register directly */\n\treadback_value = odm_get_bb_reg(dm, direct_addr, bit_mask);\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t  \"RF-%d 0x%x = 0x%x, bit mask = 0x%x\\n\", path, reg_addr,\n\t\t  readback_value, bit_mask);\n\treturn readback_value;\n}\n\n__odm_func__\nboolean\nconfig_phydm_direct_write_rf_reg_8822c(struct dm_struct *dm, enum rf_path path,\n\t\t\t\t       u32 reg_addr, u32 bit_mask, u32 data)\n{\n\tu32 direct_addr = 0;\n\tu32 offset_write_rf[2] = {0x3c00, 0x4c00};\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"%s ======>\\n\", __func__);\n\n\t/* @Calculate offset */\n\treg_addr &= 0xff;\n\tdirect_addr = offset_write_rf[path] + (reg_addr << 2);\n\n\t/* @RF register only has 20bits */\n\tbit_mask &= RFREG_MASK;\n\n\t/* direct write only*/\n\tif (reg_addr == RF_0x18) {\n\t\todm_set_mac_reg(dm, R_0x1c, BIT(31) | BIT(30), 0x3);\n\t\todm_set_mac_reg(dm, R_0xec, BIT(31) | BIT(30), 0x3);\n\t}\n\n\t/* @write RF register directly*/\n\todm_set_bb_reg(dm, direct_addr, bit_mask, data);\n\n\tODM_delay_us(1);\n\n\t/* default setting: RF-0x0 is PI, others are direct*/\n\tif (reg_addr == RF_0x18) {\n\t\todm_set_mac_reg(dm, R_0x1c, BIT(31) | BIT(30), 0x2);\n\t\todm_set_mac_reg(dm, R_0xec, BIT(31) | BIT(30), 0x2);\n\t}\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"RF-%d 0x%x = 0x%x , bit mask = 0x%x\\n\",\n\t\t  path, reg_addr, data, bit_mask);\n\n\treturn true;\n}\n\n__odm_func__\nboolean\nconfig_phydm_write_rf_reg_8822c(struct dm_struct *dm, enum rf_path path,\n\t\t\t\tu32 reg_addr, u32 bit_mask, u32 data)\n{\n\tu32 data_and_addr = 0, data_original = 0;\n\tu32 offset_write_rf[2] = {0x1808, 0x4108};\n\tboolean result = false;\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"%s ======>\\n\", __func__);\n\n\t/* @Error handling.*/\n\tif (path > RF_PATH_B) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Invalid path=%d\\n\", path);\n\t\treturn false;\n\t}\n\n\tif (!(reg_addr == RF_0x0)) {\n\t\tresult = config_phydm_direct_write_rf_reg_8822c(dm, path,\n\t\t\t\t\t\t\t\treg_addr,\n\t\t\t\t\t\t\t\tbit_mask, data);\n\t\treturn result;\n\t}\n\n\t/* @Read RF register content first */\n\treg_addr &= 0xff;\n\tbit_mask &= RFREG_MASK;\n\n\tif (bit_mask != RFREG_MASK) {\n\t\tdata_original = config_phydm_read_rf_reg_8822c(dm, path,\n\t\t\t\t\t\t\t       reg_addr,\n\t\t\t\t\t\t\t       RFREG_MASK);\n\n\t\t/* @Error handling. RF is disabled */\n\t\tif (!(data_original != INVALID_RF_DATA)) {\n\t\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t\t\t  \"Write fail, RF is disable\\n\");\n\t\t\treturn false;\n\t\t}\n\n\t\t/* @check bit mask */\n\t\tdata = phydm_check_bit_mask_8822c(bit_mask, data_original,\n\t\t\t\t\t\t  data);\n\t}\n\n\t/* @Put write addr in [27:20] and write data in [19:00] */\n\tdata_and_addr = ((reg_addr << 20) | (data & 0x000fffff)) & 0x0fffffff;\n\n\t/* @Write operation */\n\todm_set_bb_reg(dm, offset_write_rf[path], MASKDWORD, data_and_addr);\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t  \"RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\\n\",\n\t\t  path, reg_addr, data, data_original, bit_mask);\n#if (defined(CONFIG_RUN_IN_DRV))\n\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\tODM_delay_us(13);\n#elif (defined(CONFIG_RUN_IN_FW))\n\tODM_delay_us(13);\n#endif\n\n\treturn true;\n}\n\n__odm_func__\nboolean\nphydm_write_txagc_1byte_8822c(struct dm_struct *dm, u32 pw_idx, u8 hw_rate)\n{\n#if (PHYDM_FW_API_FUNC_ENABLE_8822C)\n\n\tu32 offset_txagc = 0x3a00;\n\tu8 rate_idx = (hw_rate & 0xfc), i = 0;\n\tu8 rate_offset = (hw_rate & 0x3);\n\tu8 ret = 0;\n\tu32 txagc_idx = 0x0;\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"%s ======>\\n\", __func__);\n\t/* @For debug command only!!!! */\n\n\t/* @bbrstb TX AGC report - default disable */\n\t/* @Enable for writing the TX AGC table when bb_reset=0 */\n\todm_set_bb_reg(dm, R_0x1c90, BIT(15), 0x0);\n\n\t/* @Error handling */\n\tif (hw_rate > 0x53) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Unsupported rate\\n\");\n\t\treturn false;\n\t}\n\n\t/* @For HW limitation, We can't write TXAGC once a byte. */\n\tfor (i = 0; i < 4; i++) {\n\t\tif (i != rate_offset) {\n\t\t\tret = config_phydm_read_txagc_diff_8822c(dm,\n\t\t\t\t\t\t\t\t rate_idx + i);\n\t\t\ttxagc_idx |= ret << (i << 3);\n\t\t} else {\n\t\t\ttxagc_idx |= (pw_idx & 0x7f) << (i << 3);\n\t\t}\n\t}\n\todm_set_bb_reg(dm, (offset_txagc + rate_idx), MASKDWORD, txagc_idx);\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"rate_idx 0x%x (0x%x) = 0x%x\\n\",\n\t\t  hw_rate, (offset_txagc + hw_rate), txagc_idx);\n\treturn true;\n#else\n\treturn false;\n#endif\n}\n\n__odm_func__\nboolean\nconfig_phydm_write_txagc_ref_8822c(struct dm_struct *dm, u8 power_index,\n\t\t\t\t   enum rf_path path,\n\t\t\t\t   enum PDM_RATE_TYPE rate_type)\n{\n\t/* @2-path power reference */\n\tu32 txagc_ofdm_ref[2] = {0x18e8, 0x41e8};\n\tu32 txagc_cck_ref[2] = {0x18a0, 0x41a0};\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"%s ======>\\n\", __func__);\n\n\t/* @Input need to be HW rate index, not driver rate index!!!! */\n\tif (dm->is_disable_phy_api) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Disable PHY API for debug\\n\");\n\t\treturn true;\n\t}\n\n\t/* @Error handling */\n\tif (path > RF_PATH_B) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Unsupported path (%d)\\n\",\n\t\t\t  path);\n\t\treturn false;\n\t}\n\n\t/* @bbrstb TX AGC report - default disable */\n\t/* @Enable for writing the TX AGC table when bb_reset=0 */\n\todm_set_bb_reg(dm, R_0x1c90, BIT(15), 0x0);\n\n\t/* @According the rate to write in the ofdm or the cck */\n\t/* @CCK reference setting */\n\tif (rate_type == PDM_CCK) {\n\t\todm_set_bb_reg(dm, txagc_cck_ref[path], 0x007f0000,\n\t\t\t       power_index);\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t\t  \"path-%d rate type %d (0x%x) = 0x%x\\n\",\n\t\t\t  path, rate_type, txagc_cck_ref[path], power_index);\n\n\t/* @OFDM reference setting */\n\t} else {\n\t\todm_set_bb_reg(dm, txagc_ofdm_ref[path], 0x0001fc00,\n\t\t\t       power_index);\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t\t  \"path-%d rate type %d (0x%x) = 0x%x\\n\",\n\t\t\t  path, rate_type, txagc_ofdm_ref[path], power_index);\n\t}\n\n\treturn true;\n}\n\n__odm_func__\nboolean\nconfig_phydm_write_txagc_diff_8822c(struct dm_struct *dm, s8 power_index1,\n\t\t\t\t    s8 power_index2, s8 power_index3,\n\t\t\t\t    s8 power_index4, u8 hw_rate)\n{\n\tu32 offset_txagc = 0x3a00;\n\tu8 rate_idx = hw_rate & 0xfc; /* @Extract the 0xfc */\n\tu8 power_idx1 = 0;\n\tu8 power_idx2 = 0;\n\tu8 power_idx3 = 0;\n\tu8 power_idx4 = 0;\n\tu32 pw_all = 0;\n\n\tpower_idx1 = power_index1 & 0x7f;\n\tpower_idx2 = power_index2 & 0x7f;\n\tpower_idx3 = power_index3 & 0x7f;\n\tpower_idx4 = power_index4 & 0x7f;\n\tpw_all = (power_idx4 << 24) | (power_idx3 << 16) | (power_idx2 << 8) |\n\t\t power_idx1;\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"%s ======>\\n\", __func__);\n\n\t/* @Input need to be HW rate index, not driver rate index!!!! */\n\tif (dm->is_disable_phy_api) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Disable PHY API for debug\\n\");\n\t\treturn true;\n\t}\n\n\t/* @Error handling */\n\tif (hw_rate > ODM_RATEVHTSS2MCS9) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Unsupported rate\\n\");\n\t\treturn false;\n\t}\n\n\t/* @bbrstb TX AGC report - default disable */\n\t/* @Enable for writing the TX AGC table when bb_reset=0 */\n\todm_set_bb_reg(dm, R_0x1c90, BIT(15), 0x0);\n\n\t/* @According the rate to write in the ofdm or the cck */\n\t/* @driver need to construct a 4-byte power index */\n\todm_set_bb_reg(dm, (offset_txagc + rate_idx), MASKDWORD, pw_all);\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"rate index 0x%x (0x%x) = 0x%x\\n\",\n\t\t  hw_rate, (offset_txagc + hw_rate), pw_all);\n\treturn true;\n}\n\n#if 1 /*Will remove when FW fill TXAGC funciton well verified*/\n__odm_func__\nvoid config_phydm_set_txagc_to_hw_8822c(struct dm_struct *dm)\n{\n#if (defined(CONFIG_RUN_IN_DRV))\n\ts8 diff_tab[2][NUM_RATE_AC_2SS]; /*power diff table of 2 paths*/\n\ts8 diff_tab_min[NUM_RATE_AC_2SS];\n\tu8 ref_pow_cck[2] = {dm->txagc_buff[RF_PATH_A][ODM_RATE11M],\n\t\t\t     dm->txagc_buff[RF_PATH_B][ODM_RATE11M]};\n\tu8 ref_pow_ofdm[2] = {dm->txagc_buff[RF_PATH_A][ODM_RATEMCS7],\n\t\t\t      dm->txagc_buff[RF_PATH_B][ODM_RATEMCS7]};\n\tu8 ref_pow_tmp = 0;\n\tenum rf_path path = 0;\n\tu8 i, j = 0;\n\n\tif (*dm->is_fcs_mode_enable)\n\t\treturn;\n\n\t/* === [Reference base] =============================================*/\n#ifdef CONFIG_TXAGC_DEBUG_8822C\n\tpr_debug(\"ref_pow_cck={%d, %d}, ref_pow_ofdm={%d, %d}\\n\",\n\t\t ref_pow_cck[0], ref_pow_cck[1], ref_pow_ofdm[0],\n\t\t ref_pow_ofdm[1]);\n#endif\n\t/*Set OFDM/CCK Ref. power index*/\n\tconfig_phydm_write_txagc_ref_8822c(dm, ref_pow_cck[0], RF_PATH_A,\n\t\t\t\t\t   PDM_CCK);\n\tconfig_phydm_write_txagc_ref_8822c(dm, ref_pow_cck[1], RF_PATH_B,\n\t\t\t\t\t   PDM_CCK);\n\tconfig_phydm_write_txagc_ref_8822c(dm, ref_pow_ofdm[0], RF_PATH_A,\n\t\t\t\t\t   PDM_OFDM);\n\tconfig_phydm_write_txagc_ref_8822c(dm, ref_pow_ofdm[1], RF_PATH_B,\n\t\t\t\t\t   PDM_OFDM);\n\n\t/* === [Power By Rate] ==============================================*/\n\tfor (path = RF_PATH_A; path <= RF_PATH_B; path++)\n\t\todm_move_memory(dm, diff_tab[path], dm->txagc_buff[path],\n\t\t\t\tNUM_RATE_AC_2SS);\n\n#ifdef CONFIG_TXAGC_DEBUG_8822C\n\tpr_debug(\"1. diff_tab path A\\n\");\n\tfor (i = 0; i <= ODM_RATEVHTSS2MCS9; i++)\n\t\tpr_debug(\"[A][rate:%d] = %d\\n\", i, diff_tab[RF_PATH_A][i]);\n\tpr_debug(\"2. diff_tab path B\\n\");\n\tfor (i = 0; i <= ODM_RATEVHTSS2MCS9; i++)\n\t\tpr_debug(\"[B][rate:%d] = %d\\n\", i, diff_tab[RF_PATH_B][i]);\n#endif\n\n\tfor (path = RF_PATH_A; path <= RF_PATH_B; path++) {\n\t\t/*CCK*/\n\t\tref_pow_tmp = ref_pow_cck[path];\n\t\tfor (j = ODM_RATE1M; j <= ODM_RATE11M; j++) {\n\t\t\tdiff_tab[path][j] -= (s8)ref_pow_tmp;\n\t\t\t/**/\n\t\t}\n\t\t/*OFDM*/\n\t\tref_pow_tmp = ref_pow_ofdm[path];\n\t\tfor (j = ODM_RATE6M; j <= ODM_RATEMCS15; j++) {\n\t\t\tdiff_tab[path][j] -= (s8)ref_pow_tmp;\n\t\t\t/**/\n\t\t}\n\t\tfor (j = ODM_RATEVHTSS1MCS0; j <= ODM_RATEVHTSS2MCS9; j++) {\n\t\t\tdiff_tab[path][j] -= (s8)ref_pow_tmp;\n\t\t\t/**/\n\t\t}\n\t}\n\n#ifdef CONFIG_TXAGC_DEBUG_8822C\n\tpr_debug(\"3. diff_tab path A\\n\");\n\tfor (i = 0; i <= ODM_RATEVHTSS2MCS9; i++)\n\t\tpr_debug(\"[A][rate:%d] = %d\\n\", i, diff_tab[RF_PATH_A][i]);\n\tpr_debug(\"4. diff_tab path B\\n\");\n\tfor (i = 0; i <= ODM_RATEVHTSS2MCS9; i++)\n\t\tpr_debug(\"[B][rate:%d] = %d\\n\", i, diff_tab[RF_PATH_B][i]);\n#endif\n\n\tfor (i = ODM_RATE1M; i <= ODM_RATEMCS15; i++) {\n\t\tdiff_tab_min[i] = MIN_2(diff_tab[RF_PATH_A][i],\n\t\t\t\t\tdiff_tab[RF_PATH_B][i]);\n\t\t#ifdef CONFIG_TXAGC_DEBUG_8822C\n\t\tpr_debug(\"diff_tab_min[rate:%d]= %d\\n\", i, diff_tab_min[i]);\n\t\t#endif\n\t\tif  (i % 4 == 3) {\n\t\t\tconfig_phydm_write_txagc_diff_8822c(dm,\n\t\t\t\t\t\t\t    diff_tab_min[i - 3],\n\t\t\t\t\t\t\t    diff_tab_min[i - 2],\n\t\t\t\t\t\t\t    diff_tab_min[i - 1],\n\t\t\t\t\t\t\t    diff_tab_min[i],\n\t\t\t\t\t\t\t    i - 3);\n\t\t}\n\t}\n\n\tfor (i = ODM_RATEVHTSS1MCS0; i <= ODM_RATEVHTSS2MCS9; i++) {\n\t\tdiff_tab_min[i] = MIN_2(diff_tab[RF_PATH_A][i],\n\t\t\t\t\tdiff_tab[RF_PATH_B][i]);\n\t\t#ifdef CONFIG_TXAGC_DEBUG_8822C\n\t\tpr_debug(\"diff_tab_min[rate:%d]= %d\\n\", i, diff_tab_min[i]);\n\t\t#endif\n\t\tif  (i % 4 == 3) {\n\t\t\tconfig_phydm_write_txagc_diff_8822c(dm,\n\t\t\t\t\t\t\t    diff_tab_min[i - 3],\n\t\t\t\t\t\t\t    diff_tab_min[i - 2],\n\t\t\t\t\t\t\t    diff_tab_min[i - 1],\n\t\t\t\t\t\t\t    diff_tab_min[i],\n\t\t\t\t\t\t\t    i - 3);\n\t\t}\n\t}\n#endif\n}\n\n__odm_func__\nboolean config_phydm_write_txagc_8822c(struct dm_struct *dm, u32 pw_idx,\n\t\t\t\t       enum rf_path path, u8 hw_rate)\n{\n#if (defined(CONFIG_RUN_IN_DRV))\n\tu8 ref_rate = ODM_RATEMCS15;\n\tu8 rate;\n\tu8 fill_valid_cnt = 0;\n\tu8 i = 0;\n\n\tif (*dm->is_fcs_mode_enable)\n\t\treturn false;\n\n\tif (dm->is_disable_phy_api) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Disable PHY API for debug\\n\");\n\t\treturn true;\n\t}\n\n\tif (path > RF_PATH_B) {\n\t\tpr_debug(\"[Warning 1] %s\\n\", __func__);\n\t\treturn false;\n\t}\n\n\tif ((hw_rate > ODM_RATEMCS15 && hw_rate <= ODM_RATEMCS31) ||\n\t    hw_rate > ODM_RATEVHTSS2MCS9) {\n\t\tpr_debug(\"[Warning 2] %s\\n\", __func__);\n\t\treturn false;\n\t}\n\n\tif (hw_rate <= ODM_RATEMCS15)\n\t\tref_rate = ODM_RATEMCS15;\n\telse\n\t\tref_rate = ODM_RATEVHTSS2MCS9;\n\n\tfill_valid_cnt = ref_rate - hw_rate + 1;\n\tif (fill_valid_cnt > 4)\n\t\tfill_valid_cnt = 4;\n\n\tfor (i = 0; i < fill_valid_cnt; i++) {\n\t\trate = hw_rate + i;\n\t\tif (rate > (PHY_NUM_RATE_IDX - 1)) /*Just for protection*/\n\t\t\tbreak;\n\n\t\tdm->txagc_buff[path][rate] = (u8)((pw_idx >> (8 * i)) & 0xff);\n\t}\n#endif\n\treturn true;\n}\n#endif\n\n#if 1 /*API for FW fill txagc*/\n__odm_func__\nvoid phydm_set_txagc_by_table_8822c(struct dm_struct *dm,\n\t\t\t\t    struct txagc_table_8822c *tab)\n{\n#if (defined(CONFIG_RUN_IN_FW))\n\tu8 i = 0;\n\n\t/* === [Reference base] =============================================*/\n\t/*Set OFDM/CCK Ref. power index*/\n\tconfig_phydm_write_txagc_ref_8822c(dm, tab->ref_pow_cck[0], RF_PATH_A,\n\t\t\t\t\t   PDM_CCK);\n\tconfig_phydm_write_txagc_ref_8822c(dm, tab->ref_pow_cck[1], RF_PATH_B,\n\t\t\t\t\t   PDM_CCK);\n\tconfig_phydm_write_txagc_ref_8822c(dm, tab->ref_pow_ofdm[0], RF_PATH_A,\n\t\t\t\t\t   PDM_OFDM);\n\tconfig_phydm_write_txagc_ref_8822c(dm, tab->ref_pow_ofdm[1], RF_PATH_B,\n\t\t\t\t\t   PDM_OFDM);\n\n\tfor (i = ODM_RATE1M; i <= ODM_RATEMCS15; i++) {\n\t\tif  (i % 4 == 3) {\n\t\t\tconfig_phydm_write_txagc_diff_8822c(dm,\n\t\t\t\t\t\t\t    tab->diff_t[i - 3],\n\t\t\t\t\t\t\t    tab->diff_t[i - 2],\n\t\t\t\t\t\t\t    tab->diff_t[i - 1],\n\t\t\t\t\t\t\t    tab->diff_t[i],\n\t\t\t\t\t\t\t    i - 3);\n\t\t}\n\t}\n\n\tfor (i = ODM_RATEVHTSS1MCS0; i <= ODM_RATEVHTSS2MCS9; i++) {\n\t\tif  (i % 4 == 3) {\n\t\t\tconfig_phydm_write_txagc_diff_8822c(dm,\n\t\t\t\t\t\t\t    tab->diff_t[i - 3],\n\t\t\t\t\t\t\t    tab->diff_t[i - 2],\n\t\t\t\t\t\t\t    tab->diff_t[i - 1],\n\t\t\t\t\t\t\t    tab->diff_t[i],\n\t\t\t\t\t\t\t    i - 3);\n\t\t}\n\t}\n#endif\n}\n\n__odm_func__\nvoid phydm_get_txagc_ref_and_diff_8822c(struct dm_struct *dm,\n\t\t\t\t\tu8 txagc_buff[2][NUM_RATE_AC_2SS],\n\t\t\t\t\tu16 length,\n\t\t\t\t\tstruct txagc_table_8822c *tab)\n{\n#if (defined(CONFIG_RUN_IN_DRV))\n\ts8 diff_tab[2][NUM_RATE_AC_2SS]; /*power diff table of 2 paths*/\n\ts8 diff_tab_min[NUM_RATE_AC_2SS];\n\tu8 ref_pow_cck[2];\n\tu8 ref_pow_ofdm[2];\n\tu8 ref_pow_tmp = 0;\n\tenum rf_path path = 0;\n\tu8 i, j = 0;\n\n\tif (*dm->mp_mode || !dm->is_download_fw)\n\t\treturn;\n\n\tif (length != NUM_RATE_AC_2SS) {\n\t\tpr_debug(\"[warning] %s\\n\", __func__);\n\t\treturn;\n\t}\n\n\t/* === [Reference base] =============================================*/\n#ifdef CONFIG_TXAGC_DEBUG_8822C\n\tpr_debug(\"ref_pow_cck={%d, %d}, ref_pow_ofdm={%d, %d}\\n\",\n\t\t ref_pow_cck[0], ref_pow_cck[1], ref_pow_ofdm[0],\n\t\t ref_pow_ofdm[1]);\n#endif\n\n\t/* === [Power By Rate] ==============================================*/\n\tfor (path = RF_PATH_A; path <= RF_PATH_B; path++)\n\t\todm_move_memory(dm, diff_tab[path], txagc_buff[path],\n\t\t\t\tNUM_RATE_AC_2SS);\n\n\tref_pow_cck[0] = diff_tab[RF_PATH_A][ODM_RATE11M];\n\tref_pow_cck[1] = diff_tab[RF_PATH_B][ODM_RATE11M];\n\n\tref_pow_ofdm[0] = diff_tab[RF_PATH_A][ODM_RATEMCS7];\n\tref_pow_ofdm[1] = diff_tab[RF_PATH_B][ODM_RATEMCS7];\n\n#ifdef CONFIG_TXAGC_DEBUG_8822C\n\tpr_debug(\"1. diff_tab path A\\n\");\n\tfor (i = 0; i <= ODM_RATEVHTSS2MCS9; i++)\n\t\tpr_debug(\"[A][rate:%d] = %d\\n\", i, diff_tab[RF_PATH_A][i]);\n\tpr_debug(\"2. diff_tab path B\\n\");\n\tfor (i = 0; i <= ODM_RATEVHTSS2MCS9; i++)\n\t\tpr_debug(\"[B][rate:%d] = %d\\n\", i, diff_tab[RF_PATH_B][i]);\n#endif\n\n\tfor (path = RF_PATH_A; path <= RF_PATH_B; path++) {\n\t\t/*CCK*/\n\t\tref_pow_tmp = ref_pow_cck[path];\n\t\tfor (j = ODM_RATE1M; j <= ODM_RATE11M; j++) {\n\t\t\tdiff_tab[path][j] -= (s8)ref_pow_tmp;\n\t\t\t/**/\n\t\t}\n\t\t/*OFDM*/\n\t\tref_pow_tmp = ref_pow_ofdm[path];\n\t\tfor (j = ODM_RATE6M; j <= ODM_RATEMCS15; j++) {\n\t\t\tdiff_tab[path][j] -= (s8)ref_pow_tmp;\n\t\t\t/**/\n\t\t}\n\t\tfor (j = ODM_RATEVHTSS1MCS0; j <= ODM_RATEVHTSS2MCS9; j++) {\n\t\t\tdiff_tab[path][j] -= (s8)ref_pow_tmp;\n\t\t\t/**/\n\t\t}\n\t}\n\n#ifdef CONFIG_TXAGC_DEBUG_8822C\n\tpr_debug(\"3. diff_tab path A\\n\");\n\tfor (i = 0; i <= ODM_RATEVHTSS2MCS9; i++)\n\t\tpr_debug(\"[A][rate:%d] = %d\\n\", i, diff_tab[RF_PATH_A][i]);\n\tpr_debug(\"4. diff_tab path B\\n\");\n\tfor (i = 0; i <= ODM_RATEVHTSS2MCS9; i++)\n\t\tpr_debug(\"[B][rate:%d] = %d\\n\", i, diff_tab[RF_PATH_B][i]);\n#endif\n\n\tfor (i = ODM_RATE1M; i <= ODM_RATEMCS15; i++) {\n\t\tdiff_tab_min[i] = MIN_2(diff_tab[RF_PATH_A][i],\n\t\t\t\t\tdiff_tab[RF_PATH_B][i]);\n\t\t#ifdef CONFIG_TXAGC_DEBUG_8822C\n\t\tpr_debug(\"diff_tab_min[rate:%d]= %d\\n\", i, diff_tab_min[i]);\n\t\t#endif\n\t}\n\n\tfor (i = ODM_RATEVHTSS1MCS0; i <= ODM_RATEVHTSS2MCS9; i++) {\n\t\tdiff_tab_min[i] = MIN_2(diff_tab[RF_PATH_A][i],\n\t\t\t\t\tdiff_tab[RF_PATH_B][i]);\n\t\t#ifdef CONFIG_TXAGC_DEBUG_8822C\n\t\tpr_debug(\"diff_tab_min[rate:%d]= %d\\n\", i, diff_tab_min[i]);\n\t\t#endif\n\t}\n\n\todm_move_memory(dm, tab->ref_pow_cck, ref_pow_cck, 2);\n\todm_move_memory(dm, tab->ref_pow_ofdm, ref_pow_ofdm, 2);\n\todm_move_memory(dm, tab->diff_t, diff_tab_min, NUM_RATE_AC_2SS);\n#endif\n}\n#endif\n\n__odm_func__\ns8 config_phydm_read_txagc_diff_8822c(struct dm_struct *dm, u8 hw_rate)\n{\n#if (PHYDM_FW_API_FUNC_ENABLE_8822C)\n\ts8 read_back_data = 0;\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"%s ======>\\n\", __func__);\n\n\t/* @Input need to be HW rate index, not driver rate index!!!! */\n\n\t/* @Error handling */\n\tif (hw_rate > 0x53) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Unsupported rate\\n\");\n\t\treturn INVALID_TXAGC_DATA;\n\t}\n\n\t/* @Disable TX AGC report */\n\todm_set_bb_reg(dm, R_0x1c7c, BIT(23), 0x0); /* need to check */\n\n\t/* @Set data rate index (bit30~24) */\n\todm_set_bb_reg(dm, R_0x1c7c, 0x7F000000, hw_rate);\n\n\t/* @Enable TXAGC report */\n\todm_set_bb_reg(dm, R_0x1c7c, BIT(23), 0x1);\n\n\t/* @Read TX AGC report */\n\tread_back_data = (s8)odm_get_bb_reg(dm, R_0x2de8, 0xff);\n\tif (read_back_data & BIT(6))\n\t\tread_back_data |= BIT(7);\n\n\t/* @Driver have to disable TXAGC report after reading TXAGC */\n\todm_set_bb_reg(dm, R_0x1c7c, BIT(23), 0x0);\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"rate index 0x%x = 0x%x\\n\", hw_rate,\n\t\t  read_back_data);\n\treturn read_back_data;\n#else\n\treturn 0;\n#endif\n}\n\n__odm_func__\nu8 config_phydm_read_txagc_8822c(struct dm_struct *dm, enum rf_path path,\n\t\t\t\t u8 hw_rate, enum PDM_RATE_TYPE rate_type)\n{\n\ts8 read_back_data = 0;\n\tu8 ref_data = 0;\n\tu8 result_data = 0;\n\t/* @2-path power reference */\n\tu32 r_txagc_ofdm[2] = {0x18e8, 0x41e8};\n\tu32 r_txagc_cck[2] = {0x18a0, 0x41a0};\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"%s ======>\\n\", __func__);\n\n\t/* @Input need to be HW rate index, not driver rate index!!!! */\n\n\t/* @Error handling */\n\tif (path > RF_PATH_B || hw_rate > 0x53) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Unsupported path (%d)\\n\", path);\n\t\treturn INVALID_TXAGC_DATA;\n\t}\n\n\t/* @Disable TX AGC report */\n\todm_set_bb_reg(dm, R_0x1c7c, BIT(23), 0x0); /* need to check */\n\n\t/* @Set data rate index (bit30~24) */\n\todm_set_bb_reg(dm, R_0x1c7c, 0x7F000000, hw_rate);\n\n\t/* @Enable TXAGC report */\n\todm_set_bb_reg(dm, R_0x1c7c, BIT(23), 0x1);\n\n\t/* @Read power difference report */\n\tread_back_data = (s8)odm_get_bb_reg(dm, R_0x2de8, 0xff);\n\tif (read_back_data & BIT(6))\n\t\tread_back_data |= BIT(7);\n\n\t/* @Read power reference value report */\n\tif (rate_type == PDM_CCK) /* @Bit=22:16 */\n\t\tref_data = (u8)odm_get_bb_reg(dm, r_txagc_cck[path], 0x7F0000);\n\telse if (rate_type == PDM_OFDM) /* @Bit=16:10 */\n\t\tref_data = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path], 0x1FC00);\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"diff=%d ref=%d\\n\", read_back_data,\n\t\t  ref_data);\n\n\tif (read_back_data + ref_data < 0)\n\t\tresult_data = 0;\n\telse\n\t\tresult_data = read_back_data + ref_data;\n\n\t/* @Driver have to disable TXAGC report after reading TXAGC */\n\todm_set_bb_reg(dm, R_0x1c7c, BIT(23), 0x0);\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"path-%d rate index 0x%x = 0x%x\\n\",\n\t\t  path, hw_rate, result_data);\n\treturn result_data;\n}\n\n__odm_func__\nvoid\nphydm_get_tx_path_en_setting_8822c(struct dm_struct *dm,\n\t\t\t\t   struct tx_path_en_8822c *path)\n{\n\tu32 val = 0;\n\n\t/*@OFDM*/\n\tval = odm_get_bb_reg(dm, R_0x820, MASKDWORD);\n\tpath->tx_path_en_ofdm_2sts = (u8)((val & 0xf0) >> 4);\n\tpath->tx_path_en_ofdm_1sts = (u8)(val & 0xf);\n\n\t/*@CCK*/\n\tval = odm_get_bb_reg(dm, R_0x1a04, 0xf0000000);\n\n\tif (val == 0xc)\n\t\tpath->tx_path_en_cck = 3; /*AB*/\n\telse if (val == 0x8)\n\t\tpath->tx_path_en_cck = 1; /*A*/\n\telse if (val == 0x4)\n\t\tpath->tx_path_en_cck = 2; /*B*/\n\telse if (val == 0x0)\n\t\tpath->tx_path_en_cck = 0; /*disable cck tx in 5G*/\n\n\t/*@Path CTRL source*/\n\tval = odm_get_bb_reg(dm, R_0x1e24, BIT(16));\n\tpath->is_path_ctrl_by_bb_reg = (boolean)(~val);\n}\n\n__odm_func__\nvoid\nphydm_get_rx_path_en_setting_8822c(struct dm_struct *dm,\n\t\t\t\t   struct rx_path_en_8822c *path)\n{\n\tu32 val = 0;\n\n\t/*@OFDM*/\n\tpath->rx_path_en_ofdm = (u8)odm_get_bb_reg(dm, R_0x824, 0xf0000);\n\n\t/*@CCK*/\n\tval = odm_get_bb_reg(dm, R_0x1a04, 0x0f000000);\n\n\tif (val == 0x1)\n\t\tpath->rx_path_en_cck = 3; /*AB*/\n\telse if (val == 0x0)\n\t\tpath->rx_path_en_cck = 1; /*A*/\n\telse if (val == 0x5)\n\t\tpath->rx_path_en_cck = 2; /*B*/\n}\n\n__odm_func__\nvoid\nphydm_config_cck_tx_path_8822c(struct dm_struct *dm, enum bb_path tx_path)\n{\n\tif (tx_path == BB_PATH_A)\n\t\todm_set_bb_reg(dm, R_0x1a04, 0xf0000000, 0x8);\n\telse if (tx_path == BB_PATH_B)\n\t\todm_set_bb_reg(dm, R_0x1a04, 0xf0000000, 0x4);\n\telse /* @if (tx_path == BB_PATH_AB)*/\n\t\todm_set_bb_reg(dm, R_0x1a04, 0xf0000000, 0xc);\n\n#ifdef CONFIG_PATH_DIVERSITY\n\tif (!dm->dm_path_div.path_div_in_progress)\n\t\tphydm_bb_reset_8822c(dm);\n#else\n\tphydm_bb_reset_8822c(dm);\n#endif\n}\n\n__odm_func__\nboolean\nphydm_config_cck_rx_path_8822c(struct dm_struct *dm, enum bb_path rx_path)\n{\n\tboolean set_result = PHYDM_SET_FAIL;\n\n\tif (rx_path == BB_PATH_A) {\n\t\t/* @Select ant_A to receive CCK_1 and CCK_2*/\n\t\todm_set_bb_reg(dm, R_0x1a04, 0x0f000000, 0x0);\n\t\t/* @Enable Rx clk gated */\n\t\todm_set_bb_reg(dm, R_0x1a2c, BIT(5), 0x0);\n\t\t/* @Disable MRC for CCK barker */\n\t\todm_set_bb_reg(dm, R_0x1a2c, 0x00060000, 0x0);\n\t\t/* @Disable MRC for CCK CCA */\n\t\todm_set_bb_reg(dm, R_0x1a2c, 0x00600000, 0x0);\n\t\t/* @2R CS ratio setting*/\n\t\todm_set_bb_reg(dm, R_0x1ad0, 0x3e0, 0xd);\n\t} else if (rx_path == BB_PATH_B) {\n\t\t/* @Select ant_B to receive CCK_1 and CCK_2*/\n\t\todm_set_bb_reg(dm, R_0x1a04, 0x0f000000, 0x5);\n\t\t/* @Disable Rx clk gated */\n\t\todm_set_bb_reg(dm, R_0x1a2c, BIT(5), 0x1);\n\t\t/* @replace path-B with path-AB: [PHYDM-336]*/\n\t\t/* @Disable MRC for CCK barker */\n\t\todm_set_bb_reg(dm, R_0x1a2c, 0x00060000, 0x0);\n\t\t/* @Eable MRC for CCK CCA */\n\t\todm_set_bb_reg(dm, R_0x1a2c, 0x00600000, 0x1);\n\t\t/* @2R CS ratio setting*/\n\t\todm_set_bb_reg(dm, R_0x1ad0, 0x3e0, 0xf);\n\t} else if (rx_path == BB_PATH_AB) {\n\t\t/* @Select ant_A to receive CCK_1 and ant_B to receive CCK_2*/\n\t\todm_set_bb_reg(dm, R_0x1a04, 0x0f000000, 0x1);\n\t\t/* @Enable Rx clk gated */\n\t\todm_set_bb_reg(dm, R_0x1a2c, BIT(5), 0x0);\n\t\t/* @Disable MRC for CCK barker */\n\t\todm_set_bb_reg(dm, R_0x1a2c, 0x00060000, 0x1);\n\t\t/* @Eable MRC for CCK CCA */\n\t\todm_set_bb_reg(dm, R_0x1a2c, 0x00600000, 0x1);\n\t\t/* @2R CS ratio setting*/\n\t\todm_set_bb_reg(dm, R_0x1ad0, 0x3e0, 0xd);\n\t}\n\n\tset_result = PHYDM_SET_SUCCESS;\n\n#ifdef CONFIG_PATH_DIVERSITY\n\tif (!dm->dm_path_div.path_div_in_progress)\n\t\tphydm_bb_reset_8822c(dm);\n#else\n\tphydm_bb_reset_8822c(dm);\n#endif\n\treturn set_result;\n}\n\n__odm_func__\nvoid\nphydm_config_ofdm_tx_path_8822c(struct dm_struct *dm, enum bb_path tx_path_2ss,\n\t\t\t\tenum bb_path tx_path_sel_1ss)\n{\n\tu8 tx_path_2ss_en = false;\n\n\tif (tx_path_2ss == BB_PATH_AB)\n\t\ttx_path_2ss_en = true;\n\n\tif (!tx_path_2ss_en) {/* 1ss1T, do not config this with STBC*/\n\t\tif (tx_path_sel_1ss == BB_PATH_A) {\n\t\t\todm_set_bb_reg(dm, R_0x820, 0xff, 0x1);\n\t\t\todm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x0);\n\t\t} else { /*if (tx_path_sel_1ss == BB_PATH_B)*/\n\t\t\todm_set_bb_reg(dm, R_0x820, 0xff, 0x2);\n\t\t\todm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x0);\n\t\t}\n\t} else {\n\t\tif (tx_path_sel_1ss == BB_PATH_A) {\n\t\t\todm_set_bb_reg(dm, R_0x820, 0xff, 0x31);\n\t\t\todm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x0400);\n\t\t} else if (tx_path_sel_1ss == BB_PATH_B) {\n\t\t\todm_set_bb_reg(dm, R_0x820, 0xff, 0x32);\n\t\t\todm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x0400);\n\t\t} else { /*BB_PATH_AB*/\n\t\t\todm_set_bb_reg(dm, R_0x820, 0xff, 0x33);\n\t\t\todm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x0404);\n\t\t}\n\t}\n\n#ifdef CONFIG_PATH_DIVERSITY\n\tif (!dm->dm_path_div.path_div_in_progress)\n\t\tphydm_bb_reset_8822c(dm);\n#else\n\tphydm_bb_reset_8822c(dm);\n#endif\n}\n\n__odm_func__\nvoid\nphydm_config_ofdm_rx_path_8822c(struct dm_struct *dm, enum bb_path rx_path)\n{\n\tu32 ofdm_rx = 0x0;\n\n\tofdm_rx = (u32)rx_path;\n\tif (!(*dm->mp_mode)) {\n\t\tif (ofdm_rx == BB_PATH_B) {\n\t\t\tofdm_rx = BB_PATH_AB;\n\t\t\todm_set_bb_reg(dm, R_0xcc0, 0x7ff, 0x0);\n\t\t\todm_set_bb_reg(dm, R_0xcc0, BIT(22), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0xcc8, 0x7ff, 0x0);\n\t\t\todm_set_bb_reg(dm, R_0xcc8, BIT(22), 0x1);\n\t\t} else { /* ofdm_rx == BB_PATH_A || ofdm_rx == BB_PATH_AB*/\n\t\t\todm_set_bb_reg(dm, R_0xcc0, 0x7ff, 0x400);\n\t\t\todm_set_bb_reg(dm, R_0xcc0, BIT(22), 0x0);\n\t\t\todm_set_bb_reg(dm, R_0xcc8, 0x7ff, 0x400);\n\t\t\todm_set_bb_reg(dm, R_0xcc8, BIT(22), 0x0);\n\t\t}\n\t}\n\n\tif (ofdm_rx == BB_PATH_A || ofdm_rx == BB_PATH_B) {\n\t\t/*@ ht_mcs_limit*/\n\t\todm_set_bb_reg(dm, R_0x1d30, 0x300, 0x0);\n\t\t/*@ vht_nss_limit*/\n\t\todm_set_bb_reg(dm, R_0x1d30, 0x600000, 0x0);\n\t\t/* @Disable Antenna weighting */\n\t\todm_set_bb_reg(dm, R_0xc44, BIT(17), 0x0);\n\t\t/* @htstf ant-wgt enable = 0*/\n\t\todm_set_bb_reg(dm, R_0xc54, BIT(20), 0x0);\n\t\t/* @MRC_mode = 'original ZF eqz'*/\n\t\todm_set_bb_reg(dm, R_0xc38, BIT(24), 0x0);\n\t\t/* @Rx_ant */\n\t\todm_set_bb_reg(dm, R_0x824, 0x000f0000, rx_path);\n\t\t/* @Rx_CCA*/\n\t\todm_set_bb_reg(dm, R_0x824, 0x0f000000, rx_path);\n\t} else if (ofdm_rx == BB_PATH_AB) {\n\t\t/*@ ht_mcs_limit*/\n\t\todm_set_bb_reg(dm, R_0x1d30, 0x300, 0x1);\n\t\t/*@ vht_nss_limit*/\n\t\todm_set_bb_reg(dm, R_0x1d30, 0x600000, 0x1);\n\t\t/* @Enable Antenna weighting */\n\t\todm_set_bb_reg(dm, R_0xc44, BIT(17), 0x1);\n\t\t/* @htstf ant-wgt enable = 1*/\n\t\todm_set_bb_reg(dm, R_0xc54, BIT(20), 0x1);\n\t\t/* @MRC_mode = 'modified ZF eqz'*/\n\t\todm_set_bb_reg(dm, R_0xc38, BIT(24), 0x1);\n\t\t/* @Rx_ant */\n\t\todm_set_bb_reg(dm, R_0x824, 0x000f0000, BB_PATH_AB);\n\t\t/* @Rx_CCA*/\n\t\todm_set_bb_reg(dm, R_0x824, 0x0f000000, BB_PATH_AB);\n\t}\n\n#ifdef CONFIG_PATH_DIVERSITY\n\tif (!dm->dm_path_div.path_div_in_progress)\n\t\tphydm_bb_reset_8822c(dm);\n#else\n\tphydm_bb_reset_8822c(dm);\n#endif\n}\n\n__odm_func__\nvoid phydm_config_tx_path_8822c(struct dm_struct *dm, enum bb_path tx_path_2ss,\n\t\t\t\tenum bb_path tx_path_sel_1ss,\n\t\t\t\tenum bb_path tx_path_sel_cck)\n{\n\tdm->tx_2ss_status = tx_path_2ss;\n\tdm->tx_1ss_status = tx_path_sel_1ss;\n\n\tdm->tx_ant_status = dm->tx_2ss_status | dm->tx_1ss_status;\n\n\t/* @CCK TX antenna mapping */\n\tphydm_config_cck_tx_path_8822c(dm, tx_path_sel_cck);\n\n\t/* @OFDM TX antenna mapping*/\n\tphydm_config_ofdm_tx_path_8822c(dm, tx_path_2ss, tx_path_sel_1ss);\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"path_sel_2ss/1ss/cck={%d, %d, %d}\\n\",\n\t\t  tx_path_2ss, tx_path_sel_1ss, tx_path_sel_cck);\n\n#ifdef CONFIG_PATH_DIVERSITY\n\tif (!dm->dm_path_div.path_div_in_progress)\n\t\tphydm_bb_reset_8822c(dm);\n#else\n\tphydm_bb_reset_8822c(dm);\n#endif\n}\n\n__odm_func__\nvoid phydm_config_rx_path_8822c(struct dm_struct *dm, enum bb_path rx_path)\n{\n\t/* @CCK RX antenna mapping */\n\tphydm_config_cck_rx_path_8822c(dm, rx_path);\n\n\t/* @OFDM RX antenna mapping*/\n\tphydm_config_ofdm_rx_path_8822c(dm, rx_path);\n\n\tdm->rx_ant_status = rx_path;\n\n#ifdef CONFIG_PATH_DIVERSITY\n\tif (!dm->dm_path_div.path_div_in_progress)\n\t\tphydm_bb_reset_8822c(dm);\n#else\n\tphydm_bb_reset_8822c(dm);\n#endif\n}\n\n__odm_func__\nvoid\nphydm_set_rf_mode_table_8822c(struct dm_struct *dm,\n\t\t\t      enum bb_path tx_path_mode_table,\n\t\t\t      enum bb_path rx_path)\n{\n\t /* @Cannot shut down path-A, beacause synthesizer will shut down\n\t  * @when path-A is in shut down mode\n\t  */\n\n\t/* @[3-wire setting]  0: shutdown, 1: standby, 2: TX, 3: RX*/\n\tif (tx_path_mode_table == BB_PATH_A) {\n\t\tif (rx_path == BB_PATH_A) {\n\t\t\todm_set_bb_reg(dm, R_0x1800, 0xfffff, 0x33312);\n\t\t\todm_set_bb_reg(dm, R_0x4100, 0xfffff, 0x0);\n\t\t} else { /* @BB_PATH_AB*/\n\t\t\todm_set_bb_reg(dm, R_0x1800, 0xfffff, 0x33312);\n\t\t\todm_set_bb_reg(dm, R_0x4100, 0xfffff, 0x33311);\n\t\t}\n\t} else if (tx_path_mode_table == BB_PATH_B) {\n\t\tif (rx_path == BB_PATH_A) {\n\t\t\todm_set_bb_reg(dm, R_0x1800, 0xfffff, 0x33311);\n\t\t\todm_set_bb_reg(dm, R_0x4100, 0xfffff, 0x11112);\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0x1800, 0xfffff, 0x33311);\n\t\t\todm_set_bb_reg(dm, R_0x4100, 0xfffff, 0x33312);\n\t\t}\n\t} else if (tx_path_mode_table == BB_PATH_AB) {\n\t\tif (rx_path == BB_PATH_A) {\n\t\t\todm_set_bb_reg(dm, R_0x1800, 0xfffff, 0x33312);\n\t\t\todm_set_bb_reg(dm, R_0x4100, 0xfffff, 0x11112);\n\t\t} else {\n\t\t\todm_set_bb_reg(dm, R_0x1800, 0xfffff, 0x33312);\n\t\t\todm_set_bb_reg(dm, R_0x4100, 0xfffff, 0x33312);\n\t\t}\n\t}\n}\n\n__odm_func__\nboolean\nconfig_phydm_trx_mode_8822c(struct dm_struct *dm, enum bb_path tx_path_en,\n\t\t\t    enum bb_path rx_path, enum bb_path tx_path_sel_1ss)\n{\n#ifdef CONFIG_PATH_DIVERSITY\n\tstruct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;\n#endif\n\tboolean disable_2sts_div_mode = false;\n\tenum bb_path tx_path_mode_table = tx_path_en;\n\tenum bb_path tx_path_2ss = BB_PATH_AB;\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"%s ======>\\n\", __func__);\n\n\tif (dm->is_disable_phy_api) {\n\t\tpr_debug(\"[%s] Disable PHY API\\n\", __func__);\n\t\treturn true;\n\t}\n\n\t/*RX Check*/\n\tif (rx_path & ~BB_PATH_AB) {\n\t\tpr_debug(\"[Warning][%s] RX:0x%x\\n\", __func__, rx_path);\n\t\treturn false;\n\t}\n\n\t/*TX Check*/\n\tif (tx_path_en == BB_PATH_AUTO && tx_path_sel_1ss == BB_PATH_AUTO) {\n\t\t/*@ Shutting down 2sts rate, but 1sts PathDiv is enabled*/\n\t\tdisable_2sts_div_mode = true;\n\t\ttx_path_mode_table = BB_PATH_AB;\n\t} else if (tx_path_en & ~BB_PATH_AB) {\n\t\tpr_debug(\"[Warning][%s] TX:0x%x\\n\", __func__, tx_path_en);\n\t\treturn false;\n\t}\n\n\t/* @==== [RF Mode Table] ========================================*/\n\tphydm_set_rf_mode_table_8822c(dm, tx_path_mode_table, rx_path);\n\n\t/* @==== [RX Path] ==============================================*/\n\tphydm_config_rx_path_8822c(dm, rx_path);\n\n\t/* @==== [TX Path] ==============================================*/\n#ifdef CONFIG_PATH_DIVERSITY\n\t/*@ [PHYDM-312]*/\n\tif (p_div->default_tx_path != BB_PATH_A &&\n\t    p_div->default_tx_path != BB_PATH_B)\n\t\tp_div->default_tx_path = BB_PATH_A;\n\n\tif (tx_path_en == BB_PATH_A || tx_path_en == BB_PATH_B) {\n\t\tp_div->stop_path_div = true;\n\t\ttx_path_sel_1ss = tx_path_en;\n\t\ttx_path_2ss = BB_PATH_NON;\n\t} else if (tx_path_en == BB_PATH_AB) {\n\t\tif (tx_path_sel_1ss == BB_PATH_AUTO) {\n\t\t\tp_div->stop_path_div = false;\n\t\t\ttx_path_sel_1ss = p_div->default_tx_path;\n\t\t} else { /* @BB_PATH_AB, BB_PATH_A, BB_PATH_B*/\n\t\t\tp_div->stop_path_div = true;\n\t\t}\n\t\ttx_path_2ss = BB_PATH_AB;\n\t} else if (disable_2sts_div_mode) {\n\t\tp_div->stop_path_div = false;\n\t\ttx_path_sel_1ss = p_div->default_tx_path;\n\t\ttx_path_2ss = BB_PATH_NON;\n\t}\n#else\n\tif (dm->tx_1ss_status == BB_PATH_NON)\n\t\tdm->tx_1ss_status = BB_PATH_A;\n\n\tif (tx_path_en == BB_PATH_A || tx_path_en == BB_PATH_B) {\n\t\ttx_path_2ss = BB_PATH_NON;\n\t\ttx_path_sel_1ss = tx_path_en;\n\t} else if (tx_path_en == BB_PATH_AB) {\n\t\ttx_path_2ss = BB_PATH_AB;\n\t\tif (tx_path_sel_1ss == BB_PATH_AUTO)\n\t\t\ttx_path_sel_1ss = dm->tx_1ss_status;\n\t} else if (disable_2sts_div_mode) {\n\t\ttx_path_2ss = BB_PATH_NON;\n\t\ttx_path_sel_1ss = dm->tx_1ss_status;\n\t}\n#endif\n\tphydm_config_tx_path_8822c(dm, tx_path_2ss, tx_path_sel_1ss,\n\t\t\t\t   tx_path_sel_1ss);\n\n\tphydm_igi_toggle_8822c(dm);\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"RX_en=%x, tx_en/2ss/1ss={%x,%x,%x}\\n\",\n\t\t  rx_path, tx_path_en, tx_path_2ss, tx_path_sel_1ss);\n\n#ifdef CONFIG_PATH_DIVERSITY\n\tif (!p_div->path_div_in_progress)\n\t\tphydm_bb_reset_8822c(dm);\n#else\n\tphydm_bb_reset_8822c(dm);\n#endif\n\n\treturn true;\n}\n\nvoid phydm_dis_cck_trx_8822c(struct dm_struct *dm, u8 set_type)\n{\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Disable CCK TRX\\n\");\n\n\tif (set_type == PHYDM_SET) {\n\t\t/* @ CCK source 1*/\n\t\todm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x0);\n\t\t/* @ CCK RxIQ weighting = [0,0] */\n\t\todm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);\n\t\t/* @ Disable CCK Tx */\n\t\todm_set_bb_reg(dm, R_0x1a04, 0xf0000000, 0x0);\n\t} else if (set_type == PHYDM_REVERT) {\n\t\t/* @ CCK source 5*/\n\t\todm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x1);\n\t\t/* @ CCK RxIQ weighting = [1,1] */\n\t\todm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);\n\n\t\tif (dm->tx_1ss_status == BB_PATH_NON) {\n\t\t\tdm->tx_1ss_status = BB_PATH_A;\n\t\t\tpr_debug(\"[%s]tx_1ss is non !\\n\", __func__);\n\t\t}\n\t\tphydm_config_cck_tx_path_8822c(dm, dm->tx_1ss_status);\n\t}\n\tphydm_bb_reset_8822c(dm);\n}\n\n__odm_func__\nboolean\nconfig_phydm_switch_band_8822c(struct dm_struct *dm, u8 central_ch)\n{\n\tu32 rf_reg18 = 0;\n\tboolean rf_reg_status = true;\n#if 0\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"%s ======>\\n\", __func__);\n\n\tif (dm->is_disable_phy_api) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Disable PHY API for dbg\\n\");\n\t\treturn true;\n\t}\n\n\trf_reg18 = config_phydm_read_rf_reg_8822c(dm, RF_PATH_A, 0x18,\n\t\t\t\t\t\t  RFREG_MASK);\n\tif (rf_reg18 != INVALID_RF_DATA)\n\t\trf_reg_status = true;\n\telse\n\t\trf_reg_status = false;\n\n\trf_reg18 &= ~(BIT(16) | BIT(9) | BIT(8) | MASKBYTE0);\n\n\tif (central_ch <= 14) {\n\t\t/* @2.4G */\n\n\t\t/* @Enable CCK TRx */\n\t\tphydm_dis_cck_trx_8822c(dm, PHYDM_REVERT);\n\n\t\t/* @Disable MAC CCK check */\n\t\todm_set_mac_reg(dm, R_0x454, BIT(7), 0x0);\n\n\t\t/* @Disable BB CCK check */\n\t\todm_set_bb_reg(dm, R_0x1a80, BIT(18), 0x0);\n\n\t\t/* @CCA Mask, default = 0xf */\n\t\todm_set_bb_reg(dm, R_0x1c80, 0x3F000000, 0xF);\n\n\t\t/* @RF 2.4G default ch-1 */\n\t\trf_reg18 |= 0x1;\n\n\t} else if (central_ch > 35) {\n\t\t/* 5G */\n\n\t\t/* @Enable BB CCK check */\n\t\todm_set_bb_reg(dm, R_0x1a80, BIT(18), 0x1);\n\n\t\t/* @Enable CCK check */\n\t\todm_set_mac_reg(dm, R_0x454, BIT(7), 0x1);\n\n\t\t/* @Disable CCK TRx */\n\t\tphydm_dis_cck_trx_8822c(dm, PHYDM_SET);\n\n\t\t/* @CCA Mask */\n\t\todm_set_bb_reg(dm, R_0x1c80, 0x3F000000, 0x22);\n\n\t\t/* @RF band, 5G default ch-36 */\n\t\trf_reg18 |= (BIT(16) | BIT(8) | 0x24);\n\t} else {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Fail to switch band (ch: %d)\\n\",\n\t\t\t  central_ch);\n\t\treturn false;\n\t}\n\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK, rf_reg18);\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0x18, RFREG_MASK, rf_reg18);\n\n\tif (!rf_reg_status) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t\t  \"Fail to switch band (ch: %d), write RF_reg fail\\n\",\n\t\t\t  central_ch);\n\t\treturn false;\n\t}\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Success to switch band (ch: %d)\\n\",\n\t\t  central_ch);\n\n\tphydm_bb_reset_8822c(dm);\n#endif\n\treturn true;\n}\n\n__odm_func__\nvoid\nphydm_cck_tx_shaping_filter_8822c(struct dm_struct *dm, u8 central_ch)\n{\n\t/* @CCK TX filter parameters */\n\tif (central_ch == 14) {\n\t\t/* @TX Shaping Filter C0~1 */\n\t\todm_set_bb_reg(dm, R_0x1a20, MASKHWORD, 0x3da0);\n\t\t/* @TX Shaping Filter C2~5 */\n\t\todm_set_bb_reg(dm, R_0x1a24, MASKDWORD, 0x4962c931);\n\t\t/* @TX Shaping Filter C6~7 */\n\t\todm_set_bb_reg(dm, R_0x1a28, MASKLWORD, 0x6aa3);\n\t\t/* @TX Shaping Filter C8~9 */\n\t\todm_set_bb_reg(dm, R_0x1a98, MASKHWORD, 0xaa7b);\n\t\t/* @TX Shaping Filter C10~11 */\n\t\todm_set_bb_reg(dm, R_0x1a9c, MASKLWORD, 0xf3d7);\n\t\t/* @TX Shaping Filter C12~15 */\n\t\todm_set_bb_reg(dm, R_0x1aa0, MASKDWORD, 0x00000000);\n\t\t/* @TX Shaping Filter_MSB C0~7 */\n\t\todm_set_bb_reg(dm, R_0x1aac, MASKDWORD, 0xff012455);\n\t\t/* @TX Shaping Filter_MSB C8~15 */\n\t\todm_set_bb_reg(dm, R_0x1ab0, MASKDWORD, 0x0000ffff);\n\t} else {\n\t\t/* @TX Shaping Filter C0~1 */\n\t\todm_set_bb_reg(dm, R_0x1a20, MASKHWORD, 0x5284);\n\t\t/* @TX Shaping Filter C2~5 */\n\t\todm_set_bb_reg(dm, R_0x1a24, MASKDWORD, 0x3e18fec8);\n\t\t/* @TX Shaping Filter C6~7 */\n\t\todm_set_bb_reg(dm, R_0x1a28, MASKLWORD, 0x0a88);\n\t\t/* @TX Shaping Filter C8~9 */\n\t\todm_set_bb_reg(dm, R_0x1a98, MASKHWORD, 0xacc4);\n\t\t/* @TX Shaping Filter C10~11 */\n\t\todm_set_bb_reg(dm, R_0x1a9c, MASKLWORD, 0xc8b2);\n\t\t/* @TX Shaping Filter C12~15 */\n\t\todm_set_bb_reg(dm, R_0x1aa0, MASKDWORD, 0x00faf0de);\n\t\t/* @TX Shaping Filter_MSB C0~7 */\n\t\todm_set_bb_reg(dm, R_0x1aac, MASKDWORD, 0x00122344);\n\t\t/* @TX Shaping Filter_MSB C8~15 */\n\t\todm_set_bb_reg(dm, R_0x1ab0, MASKDWORD, 0x0fffffff);\n\t}\n}\n\n__odm_func__\nvoid\nphydm_agc_tab_sel_8822c(struct dm_struct *dm, u8 central_ch)\n{\n\tstruct phydm_dig_struct *dig_tab = &dm->dm_dig_table;\n\n\tif (central_ch <= 14) {\n\t\tif (*dm->band_width == CHANNEL_WIDTH_20) {\n\t\t\t/* @CCK*/\n\t\t\todm_set_bb_reg(dm, R_0x18ac, 0xf000, 0x5);\n\t\t\todm_set_bb_reg(dm, R_0x41ac, 0xf000, 0x5);\n\t\t\t/* @OFDM*/\n\t\t\todm_set_bb_reg(dm, R_0x18ac, 0x1f0, 0x6);\n\t\t\todm_set_bb_reg(dm, R_0x41ac, 0x1f0, 0x6);\n\t\t\tdig_tab->agc_table_idx = 0x6;\n\t\t} else {\n\t\t\t/* @CCK*/\n\t\t\todm_set_bb_reg(dm, R_0x18ac, 0xf000, 0x4);\n\t\t\todm_set_bb_reg(dm, R_0x41ac, 0xf000, 0x4);\n\t\t\t/* @OFDM*/\n\t\t\todm_set_bb_reg(dm, R_0x18ac, 0x1f0, 0x0);\n\t\t\todm_set_bb_reg(dm, R_0x41ac, 0x1f0, 0x0);\n\t\t\tdig_tab->agc_table_idx = 0x0;\n\t\t}\n\t} else if (central_ch >= 36 && central_ch <= 64) {\n\t\todm_set_bb_reg(dm, R_0x18ac, 0x1f0, 0x1);\n\t\todm_set_bb_reg(dm, R_0x41ac, 0x1f0, 0x1);\n\t\tdig_tab->agc_table_idx = 0x1;\n\t} else if ((central_ch >= 100) && (central_ch <= 144)) {\n\t\todm_set_bb_reg(dm, R_0x18ac, 0x1f0, 0x2);\n\t\todm_set_bb_reg(dm, R_0x41ac, 0x1f0, 0x2);\n\t\tdig_tab->agc_table_idx = 0x2;\n\t} else { /*if (central_ch >= 149)*/\n\t\todm_set_bb_reg(dm, R_0x18ac, 0x1f0, 0x3);\n\t\todm_set_bb_reg(dm, R_0x41ac, 0x1f0, 0x3);\n\t\tdig_tab->agc_table_idx = 0x3;\n\t}\n}\n\n__odm_func__\nvoid\nphydm_sco_trk_fc_setting_8822c(struct dm_struct *dm, u8 central_ch)\n{\n\tif (central_ch == 13 || central_ch == 14) {\n\t\t/* @n:41, s:37 */\n\t\todm_set_bb_reg(dm, R_0xc30, 0xfff, 0x969);\n\t} else if (central_ch == 11 || central_ch == 12) {\n\t\t/* @n:42, s:37 */\n\t\todm_set_bb_reg(dm, R_0xc30, 0xfff, 0x96a);\n\t} else if (central_ch >= 1 && central_ch <= 10) {\n\t\t/* @n:42, s:38 */\n\t\todm_set_bb_reg(dm, R_0xc30, 0xfff, 0x9aa);\n\t} else if (central_ch >= 36 && central_ch <= 51) {\n\t\t/* @n:20, s:18 */\n\t\todm_set_bb_reg(dm, R_0xc30, 0xfff, 0x494);\n\t} else if (central_ch >= 52 && central_ch <= 55) {\n\t\t/* @n:19, s:18 */\n\t\todm_set_bb_reg(dm, R_0xc30, 0xfff, 0x493);\n\t} else if ((central_ch >= 56) && (central_ch <= 111)) {\n\t\t/* @n:19, s:17 */\n\t\todm_set_bb_reg(dm, R_0xc30, 0xfff, 0x453);\n\t} else if ((central_ch >= 112) && (central_ch <= 119)) {\n\t\t/* @n:18, s:17 */\n\t\todm_set_bb_reg(dm, R_0xc30, 0xfff, 0x452);\n\t} else if ((central_ch >= 120) && (central_ch <= 172)) {\n\t\t/* @n:18, s:16 */\n\t\todm_set_bb_reg(dm, R_0xc30, 0xfff, 0x412);\n\t} else { /* if ((central_ch >= 173) && (central_ch <= 177)) */\n\t\t/* n:17, s:16 */\n\t\todm_set_bb_reg(dm, R_0xc30, 0xfff, 0x411);\n\t}\n}\n\n__odm_func__\nvoid\nphydm_tx_dfir_setting_8822c(struct dm_struct *dm, u8 central_ch)\n{\n\tif (central_ch <= 14) {\n\t\tif (central_ch == 13)\n\t\t\todm_set_bb_reg(dm, R_0x808, 0x70, 0x3);\n\t\telse\n\t\t\todm_set_bb_reg(dm, R_0x808, 0x70, 0x1);\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x808, 0x70, 0x3);\n\t}\n}\n\n__odm_func__\nboolean\nconfig_phydm_switch_channel_8822c(struct dm_struct *dm, u8 central_ch)\n{\n\tu32 rf_reg18 = 0;\n\tboolean is_2g_ch = true;\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"%s ======>\\n\", __func__);\n\n\tif (dm->is_disable_phy_api) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Disable PHY API\\n\");\n\t\treturn true;\n\t}\n\n\tif ((central_ch > 14 && central_ch < 36) ||\n\t    (central_ch > 64 && central_ch < 100) ||\n\t    (central_ch > 144 && central_ch < 149) ||\n\t    central_ch > 177) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Error CH:%d\\n\", central_ch);\n\t\treturn false;\n\t}\n\n\trf_reg18 = config_phydm_read_rf_reg_8822c(dm, RF_PATH_A, RF_0x18,\n\t\t\t\t\t\t  RFREG_MASK);\n\tif (rf_reg18 == INVALID_RF_DATA) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Invalid RF_0x18\\n\");\n\t\treturn false;\n\t}\n\n\tis_2g_ch = (central_ch <= 14) ? true : false;\n\n\t/* ==== [Set BB Reg] =================================================*/\n\n\t/* @1. AGC table selection */\n\tphydm_agc_tab_sel_8822c(dm, central_ch);\n\t/* @2. Set fc for clock offset tracking */\n\tphydm_sco_trk_fc_setting_8822c(dm, central_ch);\n\t/* @3. TX DFIR*/\n\tphydm_tx_dfir_setting_8822c(dm, central_ch);\n\t/* @4. Other BB Settings*/\n\tif (is_2g_ch) {\n\t\tphydm_cck_tx_shaping_filter_8822c(dm, central_ch);\n\t\t/* @Enable CCK TRx */\n\t\tphydm_dis_cck_trx_8822c(dm, PHYDM_REVERT);\n\t\t/* @Disable MAC CCK check */\n\t\todm_set_mac_reg(dm, R_0x454, BIT(7), 0x0);\n\t\t/* @Disable BB CCK check */\n\t\todm_set_bb_reg(dm, R_0x1a80, BIT(18), 0x0);\n\t\t/* @CCA Mask, default = 0xf */\n\t\todm_set_bb_reg(dm, R_0x1c80, 0x3F000000, 0xF);\n\t} else {\n\t\t/* @Enable BB CCK check */\n\t\todm_set_bb_reg(dm, R_0x1a80, BIT(18), 0x1);\n\t\t/* @Enable CCK check */\n\t\todm_set_mac_reg(dm, R_0x454, BIT(7), 0x1);\n\t\t/* @Disable CCK TRx */\n\t\tphydm_dis_cck_trx_8822c(dm, PHYDM_SET);\n\t\t/* @CCA Mask */\n\t\todm_set_bb_reg(dm, R_0x1c80, 0x3F000000, 0x22);\n\t}\n\n\t/* ==== [Set RF Reg 0x18] ===========================================*/\n\trf_reg18 &= ~0x703ff; /*[18:17],[16],[9:8],[7:0]*/\n\trf_reg18 |= central_ch; /* @Channel*/\n\n\tif (!is_2g_ch) { /*5G*/\n\t\trf_reg18 |= (BIT(16) | BIT(8));\n\n\t\t/* @5G Sub-Band, 01: 5400<f<=5720, 10: f>5720*/\n\t\tif (central_ch > 144)\n\t\t\trf_reg18 |= BIT(18);\n\t\telse if (central_ch >= 80)\n\t\t\trf_reg18 |= BIT(17);\n\t}\n\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK, rf_reg18);\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0x18, RFREG_MASK, rf_reg18);\n\t/*====================================================================*/\n\n\tphydm_igi_toggle_8822c(dm);\n\tphydm_bb_reset_8822c(dm);\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Switch CH:%d success\\n\", central_ch);\n\treturn true;\n}\n\n__odm_func__\nboolean\nconfig_phydm_switch_bandwidth_8822c(struct dm_struct *dm, u8 pri_ch,\n\t\t\t\t    enum channel_width bw)\n{\n\tstruct phydm_dig_struct *dig_tab = &dm->dm_dig_table;\n\tu32 rf_reg18 = 0;\n\tboolean rf_reg_status = true;\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"%s ======>\\n\", __func__);\n\n\tif (dm->is_disable_phy_api) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Disable PHY API for debug!!\\n\");\n\t\treturn true;\n\t}\n\n\t/* @Error handling */\n\tif (bw >= CHANNEL_WIDTH_MAX || (bw == CHANNEL_WIDTH_40 && pri_ch > 2) ||\n\t    (bw == CHANNEL_WIDTH_80 && pri_ch > 4)) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t\t  \"Fail to switch bw(bw:%d, pri ch:%d)\\n\", bw, pri_ch);\n\t\treturn false;\n\t}\n\n\tbw_8822c = bw;\n\trf_reg18 = config_phydm_read_rf_reg_8822c(dm, RF_PATH_A, RF_0x18,\n\t\t\t\t\t\t  RFREG_MASK);\n\tif (rf_reg18 != INVALID_RF_DATA)\n\t\trf_reg_status = true;\n\telse\n\t\trf_reg_status = false;\n\n\trf_reg18 &= ~(BIT(13) | BIT(12));\n\n\t/* @Switch bandwidth */\n\tswitch (bw) {\n\tcase CHANNEL_WIDTH_5:\n\tcase CHANNEL_WIDTH_10:\n\tcase CHANNEL_WIDTH_20:\n\t\tif (bw == CHANNEL_WIDTH_5) {\n\t\t\t/* @RX DFIR*/\n\t\t\todm_set_bb_reg(dm, R_0x810, 0x3ff0, 0x2ab);\n\n\t\t\t/* @small BW:[7:6]=0x1 */\n\t\t\t/* @TX pri ch:[11:8]=0x0, RX pri ch:[15:12]=0x0 */\n\t\t\todm_set_bb_reg(dm, R_0x9b0, 0xffc0, 0x1);\n\n\t\t\t/* @DAC clock = 120M clock for BW5 */\n\t\t\todm_set_bb_reg(dm, R_0x9b4, 0x00000700, 0x4);\n\n\t\t\t/* @ADC clock = 40M clock for BW5 */\n\t\t\todm_set_bb_reg(dm, R_0x9b4, 0x00700000, 0x4);\n\t\t} else if (bw == CHANNEL_WIDTH_10) {\n\t\t\t/* @RX DFIR*/\n\t\t\todm_set_bb_reg(dm, R_0x810, 0x3ff0, 0x2ab);\n\n\t\t\t/* @small BW:[7:6]=0x2 */\n\t\t\t/* @TX pri ch:[11:8]=0x0, RX pri ch:[15:12]=0x0 */\n\t\t\todm_set_bb_reg(dm, R_0x9b0, 0xffc0, 0x2);\n\n\t\t\t/* @DAC clock = 240M clock for BW10 */\n\t\t\todm_set_bb_reg(dm, R_0x9b4, 0x00000700, 0x6);\n\n\t\t\t/* @ADC clock = 80M clock for BW10 */\n\t\t\todm_set_bb_reg(dm, R_0x9b4, 0x00700000, 0x5);\n\t\t} else if (bw == CHANNEL_WIDTH_20) {\n\t\t\t/* @RX DFIR*/\n\t\t\todm_set_bb_reg(dm, R_0x810, 0x3ff0, 0x19b);\n\n\t\t\t/* @small BW:[7:6]=0x0 */\n\t\t\t/* @TX pri ch:[11:8]=0x0, RX pri ch:[15:12]=0x0 */\n\t\t\todm_set_bb_reg(dm, R_0x9b0, 0xffc0, 0x0);\n\n\t\t\t/* @DAC clock = 480M clock for BW20 */\n\t\t\todm_set_bb_reg(dm, R_0x9b4, 0x00000700, 0x7);\n\n\t\t\t/* @ADC clock = 160M clock for BW20 */\n\t\t\todm_set_bb_reg(dm, R_0x9b4, 0x00700000, 0x6);\n\t\t}\n\n\t\t/* @TX_RF_BW:[1:0]=0x0, RX_RF_BW:[3:2]=0x0 */\n\t\todm_set_bb_reg(dm, R_0x9b0, 0xf, 0x0);\n\n\t\t/* @RF bandwidth */\n\t\trf_reg18 |= (BIT(13) | BIT(12));\n\n\t\t/* @RF RXBB setting, modify 0x3f for WLANBB-1081*/\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0xee, 0x4, 0x1);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x33, 0x1F, 0x12);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREG_MASK, 0x18);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0xee, 0x4, 0x0);\n\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0xee, 0x4, 0x1);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0x1F, 0x12);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, RFREG_MASK, 0x18);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0xee, 0x4, 0x0);\n\n\t\t/* @pilot smoothing on */\n\t\todm_set_bb_reg(dm, R_0xcbc, BIT(21), 0x0);\n\n\t\t/* @CCK source 4 */\n\t\todm_set_bb_reg(dm, R_0x1abc, BIT(30), 0x0);\n\n\t\t/* dynamic CCK PD th*/\n\t\todm_set_bb_reg(dm, R_0x1ae8, BIT(31), 0x1);\n\t\todm_set_bb_reg(dm, R_0x1aec, 0xf, 0x6);\n\n\t\t/* subtune*/\n\t\todm_set_bb_reg(dm, R_0x88c, 0xf000, 0x1);\n\n\t\tif (*dm->band_type == ODM_BAND_2_4G) {\n\t\t\t/* @CCK*/\n\t\t\todm_set_bb_reg(dm, R_0x18ac, 0xf000, 0x5);\n\t\t\todm_set_bb_reg(dm, R_0x41ac, 0xf000, 0x5);\n\n\t\t\t/* @OFDM*/\n\t\t\todm_set_bb_reg(dm, R_0x18ac, 0x1f0, 0x6);\n\t\t\todm_set_bb_reg(dm, R_0x41ac, 0x1f0, 0x6);\n\t\t\tdig_tab->agc_table_idx = 0x6;\n\t\t}\n\t\tbreak;\n\tcase CHANNEL_WIDTH_40:\n\t\t/* @CCK primary channel */\n\t\tif (pri_ch == 1)\n\t\t\todm_set_bb_reg(dm, R_0x1a00, BIT(4), pri_ch);\n\t\telse\n\t\t\todm_set_bb_reg(dm, R_0x1a00, BIT(4), 0);\n\n\t\t/* @TX_RF_BW:[1:0]=0x1, RX_RF_BW:[3:2]=0x1 */\n\t\todm_set_bb_reg(dm, R_0x9b0, 0xf, 0x5);\n\n\t\t/* @small BW */\n\t\todm_set_bb_reg(dm, R_0x9b0, 0xc0, 0x0);\n\n\t\t/* @TX pri ch:[11:8], RX pri ch:[15:12] */\n\t\todm_set_bb_reg(dm, R_0x9b0, 0xff00, (pri_ch | (pri_ch << 4)));\n\n\t\t/* @RF bandwidth */\n\t\trf_reg18 |= BIT(13);\n\n\t\t/* @RF RXBB setting, modify 0x3f for WLANBB-1081 */\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0xee, 0x4, 0x1);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x33, 0x1F, 0x12);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREG_MASK, 0x10);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0xee, 0x4, 0x0);\n\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0xee, 0x4, 0x1);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0x1F, 0x12);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, RFREG_MASK, 0x10);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0xee, 0x4, 0x0);\n\n\t\t/* @pilot smoothing off */\n\t\todm_set_bb_reg(dm, R_0xcbc, BIT(21), 0x1);\n\n\t\t/* @CCK source 5 */\n\t\todm_set_bb_reg(dm, R_0x1abc, BIT(30), 0x1);\n\n\t\t/* dynamic CCK PD th*/\n\t\todm_set_bb_reg(dm, R_0x1ae8, BIT(31), 0x0);\n\t\todm_set_bb_reg(dm, R_0x1aec, 0xf, 0x8);\n\n\t\t/* subtune*/\n\t\todm_set_bb_reg(dm, R_0x88c, 0xf000, 0x1);\n\n\t\tif (*dm->band_type == ODM_BAND_2_4G) {\n\t\t\t/* @CCK*/\n\t\t\todm_set_bb_reg(dm, R_0x18ac, 0xf000, 0x4);\n\t\t\todm_set_bb_reg(dm, R_0x41ac, 0xf000, 0x4);\n\n\t\t\t/* @OFDM*/\n\t\t\todm_set_bb_reg(dm, R_0x18ac, 0x1f0, 0x0);\n\t\t\todm_set_bb_reg(dm, R_0x41ac, 0x1f0, 0x0);\n\t\t\tdig_tab->agc_table_idx = 0x0;\n\t\t}\n\t\tbreak;\n\tcase CHANNEL_WIDTH_80:\n\t\t/* @TX_RF_BW:[1:0]=0x2, RX_RF_BW:[3:2]=0x2 */\n\t\todm_set_bb_reg(dm, R_0x9b0, 0xf, 0xa);\n\n\t\t/* @small BW */\n\t\todm_set_bb_reg(dm, R_0x9b0, 0xc0, 0x0);\n\n\t\t/* @TX pri ch:[11:8], RX pri ch:[15:12] */\n\t\todm_set_bb_reg(dm, R_0x9b0, 0xff00, (pri_ch | (pri_ch << 4)));\n\n\t\t/* @RF bandwidth */\n\t\trf_reg18 |= BIT(12);\n\n\t\t/* @RF RXBB setting, modify 0x3f for WLANBB-1081 */\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0xee, 0x4, 0x1);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x33, 0x1F, 0x12);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREG_MASK, 0x8);\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0xee, 0x4, 0x0);\n\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0xee, 0x4, 0x1);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0x1F, 0x12);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, RFREG_MASK, 0x8);\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0xee, 0x4, 0x0);\n\n\t\t/* @pilot smoothing off */\n\t\todm_set_bb_reg(dm, R_0xcbc, BIT(21), 0x1);\n\n\t\t/* subtune*/\n\t\todm_set_bb_reg(dm, R_0x88c, 0xf000, 0x6);\n\t\tbreak;\n\tdefault:\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t\t  \"Fail to switch bw (bw:%d, pri ch:%d)\\n\", bw, pri_ch);\n\t}\n\n\t/* @Write RF register */\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK, rf_reg18);\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0x18, RFREG_MASK, rf_reg18);\n\n\tif (!rf_reg_status) {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t\t  \"Fail to switch bw (bw:%d, primary ch:%d), because writing RF register is fail\\n\",\n\t\t\t  bw, pri_ch);\n\t\treturn false;\n\t}\n\n\t/* @Toggle IGI to let RF enter RX mode */\n\tphydm_igi_toggle_8822c(dm);\n\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t  \"Success to switch bw (bw:%d, pri ch:%d)\\n\", bw, pri_ch);\n\n\tphydm_bb_reset_8822c(dm);\n\treturn true;\n}\n\n__odm_func__\nboolean\nconfig_phydm_switch_channel_bw_8822c(struct dm_struct *dm, u8 central_ch,\n\t\t\t\t     u8 primary_ch_idx,\n\t\t\t\t     enum channel_width bandwidth)\n{\n\t/* @Switch channel */\n\tif (!config_phydm_switch_channel_8822c(dm, central_ch))\n\t\treturn false;\n\n\t/* @Switch bandwidth */\n\tif (!config_phydm_switch_bandwidth_8822c(dm, primary_ch_idx, bandwidth))\n\t\treturn false;\n\n\treturn true;\n}\n\n__odm_func__\nvoid phydm_i_only_setting_8822c(struct dm_struct *dm, boolean en_i_only,\n\t\t\t\tboolean en_before_cca)\n{\n\tif (en_i_only) { /*@ Set path-a*/\n\t\tif (en_before_cca) {\n\t\t\todm_set_bb_reg(dm, R_0x1800, 0xfff00, 0x833);\n\t\t\todm_set_bb_reg(dm, R_0x1c68, 0xc000, 0x2);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70038001);\n\t\t} else {\n\t\t\tif (!(*dm->band_width == CHANNEL_WIDTH_40))\n\t\t\t\treturn;\n\n\t\t\tdm->bp_0x9b0 = odm_get_bb_reg(dm, R_0x9b0, MASKDWORD);\n\t\t\todm_set_bb_reg(dm, R_0x1800, 0xfff00, 0x888);\n\t\t\todm_set_bb_reg(dm, R_0x898, BIT(30), 0x1);\n\t\t\todm_set_bb_reg(dm, R_0x1c68, 0xc000, 0x1);\n\t\t\todm_set_bb_reg(dm, R_0x9b0, MASKDWORD, 0x2200);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70038001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70038001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70538001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70738001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70838001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70938001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70a38001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70b38001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70c38001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70d38001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70e38001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70f38001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70f38001);\n\t\t}\n\t} else {\n\t\tif (en_before_cca) {\n\t\t\todm_set_bb_reg(dm, R_0x1800, 0xfff00, 0x333);\n\t\t\todm_set_bb_reg(dm, R_0x1c68, 0xc000, 0x0);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8001);\n\t\t} else {\n\t\t\tif (!(*dm->band_width == CHANNEL_WIDTH_40))\n\t\t\t\treturn;\n\n\t\t\todm_set_bb_reg(dm, R_0x1800, 0xfff00, 0x333);\n\t\t\todm_set_bb_reg(dm, R_0x898, BIT(30), 0x0);\n\t\t\todm_set_bb_reg(dm, R_0x1c68, 0xc000, 0x0);\n\t\t\todm_set_bb_reg(dm, R_0x9b0, MASKDWORD, dm->bp_0x9b0);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x700b8001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x705b8001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x707b8001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x708b8001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x709b8001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70ab8001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70bb8001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70cb8001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70db8001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70eb8001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70fb8001);\n\t\t\todm_set_bb_reg(dm, R_0x1830, MASKDWORD, 0x70fb8001);\n\t\t}\n\t}\n}\n\n__odm_func__\nvoid phydm_1rcca_setting_8822c(struct dm_struct *dm, boolean en_1rcca)\n{\n\tif (en_1rcca) { /*@ Set path-a*/\n\t\todm_set_bb_reg(dm, R_0x83c, 0x4, 0x1);\n\t\todm_set_bb_reg(dm, R_0x824, 0x0f000000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x4100, 0xf0000, 0x1);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x70008001);\n\t\tphydm_config_cck_rx_path_8822c(dm, BB_PATH_A);\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x83c, 0x4, 0x0);\n\t\todm_set_bb_reg(dm, R_0x824, 0x0f000000, 0x3);\n\t\todm_set_bb_reg(dm, R_0x4100, 0xf0000, 0x3);\n\t\todm_set_bb_reg(dm, R_0x4130, MASKDWORD, 0x700b8001);\n\t\tphydm_config_cck_rx_path_8822c(dm, BB_PATH_AB);\n\t}\n\tphydm_bb_reset_8822c(dm);\n}\n\n__odm_func__\nvoid phydm_cck_gi_bound_8822c(struct dm_struct *dm)\n{\n\tstruct phydm_physts *physts_table = &dm->dm_physts_table;\n\tu8 cck_gi_u_bnd_msb = 0;\n\tu8 cck_gi_u_bnd_lsb = 0;\n\tu8 cck_gi_l_bnd_msb = 0;\n\tu8 cck_gi_l_bnd_lsb = 0;\n\n\tcck_gi_u_bnd_msb = (u8)odm_get_bb_reg(dm, R_0x1a98, 0xc000);\n\tcck_gi_u_bnd_lsb = (u8)odm_get_bb_reg(dm, R_0x1aa8, 0xf0000);\n\tcck_gi_l_bnd_msb = (u8)odm_get_bb_reg(dm, R_0x1a98, 0xc0);\n\tcck_gi_l_bnd_lsb = (u8)odm_get_bb_reg(dm, R_0x1a70, 0x0f000000);\n\n\tphysts_table->cck_gi_u_bnd = (u8)((cck_gi_u_bnd_msb << 4) |\n\t\t\t\t     (cck_gi_u_bnd_lsb));\n\tphysts_table->cck_gi_l_bnd = (u8)((cck_gi_l_bnd_msb << 4) |\n\t\t\t\t     (cck_gi_l_bnd_lsb));\n}\n\n__odm_func__\nvoid phydm_ch_smooth_setting_8822c(struct dm_struct *dm, boolean en_ch_smooth)\n{\n\tif (en_ch_smooth)\n\t\t/* @enable force channel smoothing*/\n\t\todm_set_bb_reg(dm, R_0xc54, BIT(7), 0x1);\n\telse\n\t\todm_set_bb_reg(dm, R_0xc54, BIT(7), 0x0);\n}\n\n__odm_func__\nu16 phydm_get_dis_dpd_by_rate_8822c(struct dm_struct *dm)\n{\n\tu16 dis_dpd_rate = 0;\n\n\tdis_dpd_rate = dm->dis_dpd_rate;\n\n\treturn dis_dpd_rate;\n}\n\n__odm_func__\nvoid phydm_set_dis_dpd_by_rate_8822c(struct dm_struct *dm, u16 bitmask)\n{\n\t/* bit(0) : ofdm 6m*/\n\t/* bit(1) : ofdm 9m*/\n\t/* bit(2) : ht mcs0*/\n\t/* bit(3) : ht mcs1*/\n\t/* bit(4) : ht mcs8*/\n\t/* bit(5) : ht mcs9*/\n\t/* bit(6) : vht 1ss mcs0*/\n\t/* bit(7) : vht 1ss mcs1*/\n\t/* bit(8) : vht 2ss mcs0*/\n\t/* bit(9) : vht 2ss mcs1*/\n\n\todm_set_bb_reg(dm, R_0xa70, 0x3ff, bitmask);\n\tdm->dis_dpd_rate = bitmask;\n}\n\n__odm_func__\nvoid phydm_cck_pd_init_8822c(struct dm_struct *dm)\n{\n\tstruct phydm_iot_center\t*iot_table = &dm->iot_table;\n\n\tif (*dm->mp_mode && iot_table->patch_id_021f0800)\n\t\t/*CS ratio:BW20/1R*/\n\t\todm_set_bb_reg(dm, R_0x1ad0, 0x1f, 0x12);\n}\n\n__odm_func__\nboolean\nconfig_phydm_parameter_init_8822c(struct dm_struct *dm,\n\t\t\t\t  enum odm_parameter_init type)\n{\n\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"%s ======>\\n\", __func__);\n\n\tphydm_cck_gi_bound_8822c(dm);\n\tphydm_cck_pd_init_8822c(dm);\n\n\t/* Disable low rate DPD*/\n\tif (dm->en_dis_dpd)\n\t\tphydm_set_dis_dpd_by_rate_8822c(dm, 0x3ff);\n\telse\n\t\tphydm_set_dis_dpd_by_rate_8822c(dm, 0x0);\n\n\t/* @Do not use PHYDM API to read/write because FW can not access */\n\t/* @Turn on 3-wire*/\n\todm_set_bb_reg(dm, R_0x180c, 0x3, 0x3);\n\todm_set_bb_reg(dm, R_0x180c, BIT(28), 0x1);\n\todm_set_bb_reg(dm, R_0x410c, 0x3, 0x3);\n\todm_set_bb_reg(dm, R_0x410c, BIT(28), 0x1);\n\n\tif (type == ODM_PRE_SETTING) {\n\t\todm_set_bb_reg(dm, R_0x1c3c, (BIT(0) | BIT(1)), 0x0);\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t\t  \"Pre setting: disable OFDM and CCK block\\n\");\n\t} else if (type == ODM_POST_SETTING) {\n\t\todm_set_bb_reg(dm, R_0x1c3c, (BIT(0) | BIT(1)), 0x3);\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG,\n\t\t\t  \"Post setting: enable OFDM and CCK block\\n\");\n\t} else {\n\t\tPHYDM_DBG(dm, ODM_PHY_CONFIG, \"Wrong type!!\\n\");\n\t\treturn false;\n\t}\n\n\tphydm_bb_reset_8822c(dm);\n\t#ifdef CONFIG_TXAGC_DEBUG_8822C\n\t/*phydm_txagc_tab_buff_init_8822c(dm);*/\n\t#endif\n\n\treturn true;\n}\n\n#if CONFIG_POWERSAVING\n__odm_func_aon__\nboolean\nphydm_rfe_8822c_lps(struct dm_struct *dm, boolean enable_sw_rfe)\n{\n#if 0\n\t//u8 rfe_type = dm->rfe_type;\n\tu32 rf_reg18_ch = 0;\n\n\trf_reg18_ch = config_phydm_read_rf_reg_8822c(dm, RF_PATH_A, RF_0x18,\n\t\t\t\t\t\t     0xff);\n\n\t/* HW Setting for each RFE type */\n\tif (rfe_type == 4) {\n\t\tif (rf_reg18_ch <= 14) {\n\t\t\t/* signal source */\n\t\t\tif (!enable_sw_rfe) {\n\t\t\t\todm_set_bb_reg(dm, R_0x1840, 0xffffff,\n\t\t\t\t\t       0x745774);\n\t\t\t\todm_set_bb_reg(dm, R_0x4140, 0xffffff,\n\t\t\t\t\t       0x745774);\n\t\t\t\todm_set_bb_reg(dm, R_0x1844, MASKBYTE1, 0x57);\n\t\t\t\todm_set_bb_reg(dm, R_0x4144, MASKBYTE1, 0x57);\n\t\t\t} else {\n\t\t\t\todm_set_bb_reg(dm, R_0x1840, 0xffffff,\n\t\t\t\t\t       0x777777);\n\t\t\t\todm_set_bb_reg(dm, R_0x4140, 0xffffff,\n\t\t\t\t\t       0x777777);\n\t\t\t\todm_set_bb_reg(dm, R_0x1844, MASKBYTE1, 0x77);\n\t\t\t\todm_set_bb_reg(dm, R_0x4144, MASKBYTE1, 0x77);\n\t\t\t}\n\t\t} else if (rf_reg18_ch > 35) {\n\t\t\t/* signal source */\n\t\t\tif (!enable_sw_rfe) {\n\t\t\t\todm_set_bb_reg(dm, R_0x1840, 0xffffff,\n\t\t\t\t\t       0x477547);\n\t\t\t\todm_set_bb_reg(dm, R_0x4140, 0xffffff,\n\t\t\t\t\t       0x477547);\n\t\t\t\todm_set_bb_reg(dm, R_0x1844, MASKBYTE1, 0x75);\n\t\t\t\todm_set_bb_reg(dm, R_0x4144, MASKBYTE1, 0x75);\n\t\t\t} else {\n\t\t\t\todm_set_bb_reg(dm, R_0x1840, 0xffffff,\n\t\t\t\t\t       0x777777);\n\t\t\t\todm_set_bb_reg(dm, R_0x4140, 0xffffff,\n\t\t\t\t\t       0x777777);\n\t\t\t\todm_set_bb_reg(dm, R_0x1844, MASKBYTE1, 0x77);\n\t\t\t\todm_set_bb_reg(dm, R_0x4144, MASKBYTE1, 0x77);\n\t\t\t}\n\t\t} else {\n\t\t\treturn false;\n\t\t}\n\t} else if ((rfe_type == 1) || (rfe_type == 2) || (rfe_type == 6) ||\n\t\t   (rfe_type == 7) || (rfe_type == 9) || (rfe_type == 11)) {\n\t\t/* eFem */\n\t\tif (rf_reg18_ch <= 14) {\n\t\t\t/* signal source */\n\t\t\tif (!enable_sw_rfe) {\n\t\t\t\todm_set_bb_reg(dm, R_0x1840, 0xffffff,\n\t\t\t\t\t       0x705770);\n\t\t\t\todm_set_bb_reg(dm, R_0x4140, 0xffffff,\n\t\t\t\t\t       0x705770);\n\t\t\t\todm_set_bb_reg(dm, R_0x1844, MASKBYTE1, 0x57);\n\t\t\t\todm_set_bb_reg(dm, R_0x4144, MASKBYTE1, 0x57);\n\t\t\t} else {\n\t\t\t\todm_set_bb_reg(dm, R_0x1840, 0xffffff,\n\t\t\t\t\t       0x777777);\n\t\t\t\todm_set_bb_reg(dm, R_0x4140, 0xffffff,\n\t\t\t\t\t       0x777777);\n\t\t\t\todm_set_bb_reg(dm, R_0x1844, MASKBYTE1, 0x77);\n\t\t\t\todm_set_bb_reg(dm, R_0x4144, MASKBYTE1, 0x77);\n\t\t\t}\n\t\t} else if (rf_reg18_ch > 35) {\n\t\t\t/* signal source */\n\t\t\tif (!enable_sw_rfe) {\n\t\t\t\todm_set_bb_reg(dm, R_0x1840, 0xffffff,\n\t\t\t\t\t       0x177517);\n\t\t\t\todm_set_bb_reg(dm, R_0x4140, 0xffffff,\n\t\t\t\t\t       0x177517);\n\t\t\t\todm_set_bb_reg(dm, R_0x1844, MASKBYTE1, 0x75);\n\t\t\t\todm_set_bb_reg(dm, R_0x4144, MASKBYTE1, 0x75);\n\t\t\t} else {\n\t\t\t\todm_set_bb_reg(dm, R_0x1840, 0xffffff,\n\t\t\t\t\t       0x777777);\n\t\t\t\todm_set_bb_reg(dm, R_0x4140, 0xffffff,\n\t\t\t\t\t       0x777777);\n\t\t\t\todm_set_bb_reg(dm, R_0x1844, MASKBYTE1, 0x77);\n\t\t\t\todm_set_bb_reg(dm, R_0x4144, MASKBYTE1, 0x77);\n\t\t\t}\n\t\t} else {\n\t\t\treturn false;\n\t\t}\n\t} else {\n\t\treturn true;\n\t}\n\t#endif\n\treturn true;\n}\n\n__odm_func_aon__\nboolean\nphydm_8822c_lps(struct dm_struct *dm, boolean enable_lps)\n{\n\tu16 poll_cnt = 0;\n\tu32 bbtemp = 0;\n\n\tif (enable_lps == _TRUE) {\n\t\t/* backup RF reg0x0 */\n\t\tSysMib.Wlan.PS.PSParm.RxGainPathA = (u16)(config_phydm_read_rf_reg_8822c(dm, RF_PATH_A, RF_0x00, RFREG_MASK));\n\t\tSysMib.Wlan.PS.PSParm.RxGainPathB = (u16)(config_phydm_read_rf_reg_8822c(dm, RF_PATH_B, RF_0x00, RFREG_MASK));\n\n\t\t/* turn off TRx HSSI: 0x180c[1:0]=2'b00, 0x410c[1:0]=2'b00 */\n\t\tbbtemp = odm_get_bb_reg(dm, R_0x180c, MASKDWORD) & 0xfffffffc;\n\t\todm_set_bb_reg(dm, R_0x180c, MASKDWORD, bbtemp);\n\t\tbbtemp = odm_get_bb_reg(dm, R_0x410c, MASKDWORD) & 0xfffffffc;\n\t\todm_set_bb_reg(dm, R_0x410c, MASKDWORD, bbtemp);\n\n\t\t/* Set RF enter shutdown mode */\n\t\tconfig_phydm_write_rf_reg_8822c(dm, RF_PATH_A, RF_0x0,\n\t\t\t\t\t\tRFREG_MASK, 0);\n\t\tconfig_phydm_write_rf_reg_8822c(dm, RF_PATH_B, RF_0x0,\n\t\t\t\t\t\tRFREG_MASK, 0);\n\n\t\t/* if eFEM, RFE control for signal source = 0 */\n\t\tphydm_rfe_8822c_lps(dm, _TRUE);\n\n\t\t/* Check BB state is idle, do not check GNT_WL only for LPS */\n\t\twhile (1) {\n\t\t\todm_set_bb_reg(dm, R_0x1c3c, 0x00f00000, 0x0);\n\t\t\tbbtemp = odm_get_bb_reg(dm, R_0x2db4, MASKDWORD);\n\t\t\tif ((bbtemp & 0x1FFEFF3F) == 0 &&\n\t\t\t    (bbtemp & 0xC0000000) == 0xC0000000)\n\t\t\t\tbreak;\n\n\t\t\tif (poll_cnt > WAIT_TXSM_STABLE_CNT) {\n\t\t\t\tWriteMACRegDWord(REG_DBG_DW_FW_ERR, ReadMACRegDWord(REG_DBG_DW_FW_ERR) | FES_BBSTATE_IDLE);\n\t\t\t/* SysMib.Wlan.DbgPort.DbgInfoParm.u4ErrFlag[0] |= FES_BBSTATE_IDLE; */\n\t\t\t\treturn _FALSE;\n\t\t\t}\n\n\t\t\tDelayUS(WAIT_TXSM_STABLE_ONCE_TIME);\n\t\t\tpoll_cnt++;\n\t\t}\n\n\t\t/* disable CCK and OFDM module */\n\t\tWriteMACRegByte(REG_SYS_FUNC_EN, ReadMACRegByte(REG_SYS_FUNC_EN)\n\t\t\t\t& ~BIT_FEN_BBRSTB);\n\n\t\tif (poll_cnt < WAIT_TXSM_STABLE_CNT) {\n\t\t\t/* Gated BBclk 0x1c24[0] = 1 */\n\t\t\tbbtemp = odm_get_bb_reg(dm, R_0x1c24, MASKDWORD) |\n\t\t\t\t 0x00000001;\n\t\t\todm_set_bb_reg(dm, R_0x1c24, MASKDWORD, bbtemp);\n\t\t}\n\n\t\treturn _TRUE;\n\t} else {\n\t\t/* release BB clk 0x1c24[0] = 0 */\n\t\tbbtemp = odm_get_bb_reg(dm, R_0x1c24, MASKDWORD) &\n\t\t\t (~0x00000001);\n\t\todm_set_bb_reg(dm, R_0x1c24, MASKDWORD, bbtemp);\n\n\t\t/* Enable CCK and OFDM module, */\n\t\t/* should be a delay large than 200ns before RF access */\n\t\tWriteMACRegByte(REG_SYS_FUNC_EN, ReadMACRegByte(REG_SYS_FUNC_EN)\n\t\t\t\t| BIT_FEN_BBRSTB);\n\t\tDelayUS(1);\n\n\t\t/* if eFEM, restore RFE control signal */\n\t\tphydm_rfe_8822c_lps(dm, _FALSE);\n\n\t\t/* Set RF enter active mode */\n\t\tconfig_phydm_write_rf_reg_8822c(dm, RF_PATH_A, R_0x00, RFREG_MASK, (0x30000 | SysMib.Wlan.PS.PSParm.RxGainPathA));\n\t\tconfig_phydm_write_rf_reg_8822c(dm, RF_PATH_B, R_0x00, RFREG_MASK, (0x30000 | SysMib.Wlan.PS.PSParm.RxGainPathB));\n\n\t\t/* turn on TRx HSSI: 0x180c[1:0]=2'b11, 0x410c[1:0]=2'b11 */\n\t\tbbtemp = odm_get_bb_reg(dm, R_0x180c, MASKDWORD) | 0x00000003;\n\t\todm_set_bb_reg(dm, R_0x180c, MASKDWORD, bbtemp);\n\t\tbbtemp = odm_get_bb_reg(dm, R_0x410c, MASKDWORD) | 0x00000003;\n\t\todm_set_bb_reg(dm, R_0x410c, MASKDWORD, bbtemp);\n\n\t\treturn _TRUE;\n\t}\n}\n#endif /* #if CONFIG_POWERSAVING */\n\n/* ======================================================================== */\n#endif /* PHYDM_FW_API_ENABLE_8822C */\n#endif /* RTL8822C_SUPPORT */\n"
  },
  {
    "path": "hal/phydm/rtl8822c/phydm_hal_api8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#ifndef __INC_PHYDM_API_H_8822C__\n#define __INC_PHYDM_API_H_8822C__\n\n#if (RTL8822C_SUPPORT)\n\n/* @2018.12.18 Modify OFDM Rx setting and add ch_smooth API*/\n#define PHY_CONFIG_VERSION_8822C \"1.2.1\"\n/*#define CONFIG_TXAGC_DEBUG_8822C*/\n\n#define SMTANT_TMP_RFE_TYPE 100\n\n#define INVALID_RF_DATA 0xffffffff\n#define INVALID_TXAGC_DATA 0xff\n\n#define number_channel_interferecne 4\n\n#define config_phydm_read_rf_check_8822c(data) ((data) != INVALID_RF_DATA)\n#define config_phydm_read_txagc_check_8822c(data) ((data) != INVALID_TXAGC_DATA)\n\nstruct txagc_table_8822c {\n\tu8 ref_pow_cck[2];\n\tu8 ref_pow_ofdm[2];\n\ts8 diff_t[NUM_RATE_AC_2SS]; /*by rate differential table*/\n};\n\nstruct tx_path_en_8822c {\n\tu8 tx_path_en_ofdm_1sts;\n\tu8 tx_path_en_ofdm_2sts;\n\tu8 tx_path_en_cck;\n\tboolean is_path_ctrl_by_bb_reg;\n};\n\nstruct rx_path_en_8822c {\n\tu8 rx_path_en_ofdm;\n\tu8 rx_path_en_cck;\n};\n\nu32 config_phydm_read_rf_reg_8822c(struct dm_struct *dm, enum rf_path path,\n\t\t\t\t   u32 reg_addr, u32 bit_mask);\n\nboolean config_phydm_write_rf_reg_8822c(struct dm_struct *dm, enum rf_path path,\n\t\t\t\t\tu32 reg_addr, u32 bit_mask, u32 data);\n\nboolean phydm_write_txagc_1byte_8822c(struct dm_struct *dm, u32 pw_idx,\n\t\t\t\t      u8 hw_rate);\n\nboolean config_phydm_write_txagc_ref_8822c(struct dm_struct *dm, u8 power_index,\n\t\t\t\t\t   enum rf_path path,\n\t\t\t\t\t   enum PDM_RATE_TYPE rate_type);\n\nboolean config_phydm_write_txagc_diff_8822c(struct dm_struct *dm,\n\t\t\t\t\t    s8 power_index1, s8 power_index2,\n\t\t\t\t\t    s8 power_index3, s8 power_index4,\n\t\t\t\t\t    u8 hw_rate);\n\n#ifdef CONFIG_TXAGC_DEBUG_8822C\nvoid phydm_txagc_tab_buff_show_8822c(struct dm_struct *dm);\n#endif\n\ns8 config_phydm_read_txagc_diff_8822c(struct dm_struct *dm, u8 hw_rate);\n\nu8 config_phydm_read_txagc_8822c(struct dm_struct *dm, enum rf_path path,\n\t\t\t\t u8 hw_rate, enum PDM_RATE_TYPE rate_type);\n\nvoid phydm_get_tx_path_en_setting_8822c(struct dm_struct *dm,\n\t\t\t\t\tstruct tx_path_en_8822c *path);\n\nvoid phydm_get_rx_path_en_setting_8822c(struct dm_struct *dm,\n\t\t\t\t\tstruct rx_path_en_8822c *path);\n\nvoid phydm_config_tx_path_8822c(struct dm_struct *dm, enum bb_path tx_path_2ss,\n\t\t\t\tenum bb_path tx_path_sel_1ss,\n\t\t\t\tenum bb_path tx_path_sel_cck);\n\nboolean config_phydm_trx_mode_8822c(struct dm_struct *dm,\n\t\t\t\t    enum bb_path tx_path_en,\n\t\t\t\t    enum bb_path rx_path,\n\t\t\t\t    enum bb_path tx_path_sel_1ss);\n\nboolean config_phydm_switch_band_8822c(struct dm_struct *dm, u8 central_ch);\n\nboolean config_phydm_switch_channel_8822c(struct dm_struct *dm, u8 central_ch);\n\nboolean config_phydm_switch_bandwidth_8822c(struct dm_struct *dm, u8 pri_ch,\n\t\t\t\t\t    enum channel_width bw);\n\nboolean config_phydm_switch_channel_bw_8822c(struct dm_struct *dm,\n\t\t\t\t\t     u8 central_ch, u8 primary_ch_idx,\n\t\t\t\t\t     enum channel_width bandwidth);\n\nvoid phydm_i_only_setting_8822c(struct dm_struct *dm, boolean en_i_only,\n\t\t\t\tboolean en_before_cca);\n\nvoid phydm_1rcca_setting_8822c(struct dm_struct *dm, boolean en_1rcca);\n\nvoid phydm_ch_smooth_setting_8822c(struct dm_struct *dm, boolean en_ch_smooth);\n\nu16 phydm_get_dis_dpd_by_rate_8822c(struct dm_struct *dm);\n\nboolean config_phydm_parameter_init_8822c(struct dm_struct *dm,\n\t\t\t\t\t  enum odm_parameter_init type);\n\n#if CONFIG_POWERSAVING\nboolean phydm_rfe_8822c_lps(struct dm_struct *dm, boolean enable_sw_rfe);\n\nboolean phydm_8822c_lps(struct dm_struct *dm, boolean enable_lps);\n#endif /* #if CONFIG_POWERSAVING */\n\nvoid config_phydm_set_txagc_to_hw_8822c(struct dm_struct *dm);\n\nboolean config_phydm_write_txagc_8822c(struct dm_struct *dm, u32 power_index,\n\t\t\t\t       enum rf_path path, u8 hw_rate);\n\nvoid phydm_set_txagc_by_table_8822c(struct dm_struct *dm,\n\t\t\t\t    struct txagc_table_8822c *tab);\n\nvoid phydm_get_txagc_ref_and_diff_8822c(struct dm_struct *dm,\n\t\t\t\t\tu8 txagc_buff[2][NUM_RATE_AC_2SS],\n\t\t\t\t\tu16 length,\n\t\t\t\t\tstruct txagc_table_8822c *tab);\n#endif /* RTL8822C_SUPPORT */\n#endif /*  __INC_PHYDM_API_H_8822C__ */\n"
  },
  {
    "path": "hal/phydm/rtl8822c/phydm_regconfig8822c.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"../phydm_precomp.h\"\n\n#if (RTL8822C_SUPPORT)\n\nvoid odm_config_rf_reg_8822c(struct dm_struct *dm, u32 addr, u32 data,\n\t\t\t     enum rf_path rf_path, u32 reg_addr)\n{\n\tif (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {\n\t\tif (addr == 0xffe)\n\t\t\tphydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_DELAY_MS,\n\t\t\t\t\t    reg_addr, data, RFREG_MASK, rf_path,\n\t\t\t\t\t    50);\n\t\telse if (addr == 0xfe)\n\t\t\tphydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_DELAY_US,\n\t\t\t\t\t    reg_addr, data, RFREG_MASK, rf_path,\n\t\t\t\t\t    100);\n\t\telse {\n\t\t\tphydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_RF_W, reg_addr,\n\t\t\t\t\t    data, RFREG_MASK, rf_path, 0);\n\t\t\tphydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_DELAY_US,\n\t\t\t\t\t    reg_addr, data, RFREG_MASK, rf_path,\n\t\t\t\t\t    1);\n\t\t}\n\t} else {\n\t\tif (addr == 0xffe) {\n#ifdef CONFIG_LONG_DELAY_ISSUE\n\t\t\tODM_sleep_ms(50);\n#else\n\t\t\tODM_delay_ms(50);\n#endif\n\t\t} else if (addr == 0xfe) {\n#ifdef CONFIG_LONG_DELAY_ISSUE\n\t\t\tODM_sleep_us(100);\n#else\n\t\t\tODM_delay_us(100);\n#endif\n\t\t} else if (addr == 0xffff) {\n\t\t\tODM_delay_us(1);\n\t\t} else {\n\t\t\todm_set_rf_reg(dm, rf_path, reg_addr, RFREG_MASK, data);\n\n\t\t\t/*Add 1us delay between BB/RF register setting.*/\n\t\t\tODM_delay_us(1);\n\t\t}\n\t}\n}\n\nvoid odm_config_rf_radio_a_8822c(struct dm_struct *dm, u32 addr, u32 data)\n{\n\tu32 content = 0x1000; /* RF_Content: radioa_txt */\n\tu32 maskfor_phy_set = (u32)(content & 0xE000);\n\n\todm_config_rf_reg_8822c(dm, addr, data, RF_PATH_A, addr |\n\t\t\t\tmaskfor_phy_set);\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"===> config_rf: [RadioA] %08X %08X\\n\",\n\t\t  addr, data);\n}\n\nvoid odm_config_rf_radio_b_8822c(struct dm_struct *dm, u32 addr, u32 data)\n{\n\tu32 content = 0x1001; /* RF_Content: radiob_txt */\n\tu32 maskfor_phy_set = (u32)(content & 0xE000);\n\n\todm_config_rf_reg_8822c(dm, addr, data, RF_PATH_B, addr |\n\t\t\t\tmaskfor_phy_set);\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"===> config_rf: [RadioB] %08X %08X\\n\",\n\t\t  addr, data);\n}\n\nvoid odm_config_mac_8822c(struct dm_struct *dm,\tu32 addr, u8 data)\n{\n\tif (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD)\n\t\tphydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_MAC_W8, addr, data, 0,\n\t\t\t\t    (enum rf_path)0, 0);\n\telse\n\t\todm_write_1byte(dm, addr, data);\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"===> config_mac: [MAC_REG] %08X %08X\\n\",\n\t\t  addr, data);\n}\n\nvoid odm_update_agc_big_jump_lmt_8822c(struct dm_struct *dm, u32 addr, u32 data)\n{\n#if 0\n\tstruct phydm_dig_struct *dig_tab = &dm->dm_dig_table;\n\tu8 rf_gain_idx = (u8)((data & 0xFF000000) >> 24);\n\tu8 bb_gain_idx = (u8)((data & 0x00ff0000) >> 16);\n\tu8 agc_table_idx = (u8)((data & 0x00000f00) >> 8);\n\n\tstatic boolean is_limit;\n\n\tif (addr != 0x81c)\n\t\treturn;\n\n\tdbg_print(\"data = 0x%x, bb_gain_idx = 0x%x, agc_table_idx = 0x%x\\n\",\n\t\t  data, bb_gain_idx, agc_table_idx);\n\tdbg_print(\"rf_gain_idx = 0x%x, dig_tab->rf_gain_idx = 0x%x\\n\",\n\t\t  rf_gain_idx, dig_tab->rf_gain_idx);\n\n\tif (bb_gain_idx > 0x3c) {\n\t\tif (rf_gain_idx == dig_tab->rf_gain_idx && !is_limit) {\n\t\t\tis_limit = true;\n\t\t\tdig_tab->big_jump_lmt[agc_table_idx] = bb_gain_idx - 2;\n\t\t\tPHYDM_DBG(dm, DBG_DIG,\n\t\t\t\t  \"===> [AGC_TAB] big_jump_lmt [%d] = 0x%x\\n\",\n\t\t\t\t  agc_table_idx,\n\t\t\t\t  dig_tab->big_jump_lmt[agc_table_idx]);\n\t\t}\n\t} else {\n\t\tis_limit = false;\n\t}\n\tdig_tab->rf_gain_idx = rf_gain_idx;\n#endif\n}\n\nvoid odm_config_bb_agc_8822c(struct dm_struct *dm, u32 addr, u32 bitmask,\n\t\t\t     u32 data)\n{\n\t/* odm_update_agc_big_jump_lmt_8822c(dm, addr, data); */\n\n\tif (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD)\n\t\tphydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_BB_W32, addr, data,\n\t\t\t\t    bitmask, (enum rf_path)0, 0);\n\telse\n\t\todm_set_bb_reg(dm, addr, bitmask, data);\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"===> config_bb: [AGC_TAB] %08X %08X\\n\",\n\t\t  addr, data);\n}\n\nvoid odm_config_bb_phy_reg_pg_8822c(struct dm_struct *dm, u32 band, u32 rf_path,\n\t\t\t\t    u32 tx_num, u32 addr, u32 bitmask, u32 data)\n{\n\tif (addr == 0xfe || addr == 0xffe) {\n#ifdef CONFIG_LONG_DELAY_ISSUE\n\t\tODM_sleep_ms(50);\n#else\n\t\tODM_delay_ms(50);\n#endif\n\t} else {\n#if (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\t\tphy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num,\n\t\t\t\t\t   addr, bitmask, data);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\t\tPHY_StoreTxPowerByRate(dm->adapter, band, rf_path, tx_num, addr,\n\t\t\t\t       bitmask, data);\n#endif\n\t}\n\tPHYDM_DBG(dm, ODM_COMP_INIT,\n\t\t  \"===> config_bb: [PHY_REG] %08X %08X %08X\\n\", addr, bitmask,\n\t\t  data);\n}\n\nvoid odm_config_bb_phy_8822c(struct dm_struct *dm, u32 addr, u32 bitmask,\n\t\t\t     u32 data)\n{\n\tif (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {\n\t\tu32 delay_time = 0;\n\n\t\tif (addr >= 0xf9 && addr <= 0xfe) {\n\t\t\tif (addr == 0xfe || addr == 0xfb)\n\t\t\t\tdelay_time = 50;\n\t\t\telse if (addr == 0xfd || addr == 0xfa)\n\t\t\t\tdelay_time = 5;\n\t\t\telse\n\t\t\t\tdelay_time = 1;\n\n\t\t\tif (addr >= 0xfc && addr <= 0xfe)\n\t\t\t\tphydm_set_reg_by_fw(dm,\n\t\t\t\t\t\t    PHYDM_HALMAC_CMD_DELAY_MS,\n\t\t\t\t\t\t    addr, data, bitmask,\n\t\t\t\t\t\t    (enum rf_path)0,\n\t\t\t\t\t\t    delay_time);\n\t\t\telse\n\t\t\t\tphydm_set_reg_by_fw(dm,\n\t\t\t\t\t\t    PHYDM_HALMAC_CMD_DELAY_US,\n\t\t\t\t\t\t    addr, data, bitmask,\n\t\t\t\t\t\t    (enum rf_path)0,\n\t\t\t\t\t\t    delay_time);\n\t\t} else\n\t\t\tphydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_BB_W32,\n\t\t\t\t\t    addr, data, bitmask,\n\t\t\t\t\t    (enum rf_path)0, 0);\n\t} else {\n\t\tif (addr == 0xfe)\n#ifdef CONFIG_LONG_DELAY_ISSUE\n\t\t\tODM_sleep_ms(50);\n#else\n\t\t\tODM_delay_ms(50);\n#endif\n\t\telse if (addr == 0xfd)\n\t\t\tODM_delay_ms(5);\n\t\telse if (addr == 0xfc)\n\t\t\tODM_delay_ms(1);\n\t\telse if (addr == 0xfb)\n\t\t\tODM_delay_us(50);\n\t\telse if (addr == 0xfa)\n\t\t\tODM_delay_us(5);\n\t\telse if (addr == 0xf9)\n\t\t\tODM_delay_us(1);\n\t\telse\n\t\t\todm_set_bb_reg(dm, addr, bitmask, data);\n\t}\n\n\tPHYDM_DBG(dm, ODM_COMP_INIT, \"===> config_bb: [PHY_REG] %08X %08X\\n\",\n\t\t  addr, data);\n}\n\nvoid odm_config_bb_txpwr_lmt_8822c(struct dm_struct *dm, u8 *regulation,\n\t\t\t\t   u8 *band, u8 *bandwidth, u8 *rate_section,\n\t\t\t\t   u8 *rf_path, u8 *channel, u8 *power_limit)\n{\n#if (DM_ODM_SUPPORT_TYPE & ODM_CE)\n\tphy_set_tx_power_limit(dm, regulation, band, bandwidth, rate_section,\n\t\t\t       rf_path, channel, power_limit);\n#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\n\tPHY_SetTxPowerLimit(dm, regulation, band, bandwidth, rate_section,\n\t\t\t    rf_path, channel, power_limit);\n#endif\n}\n\n#endif\n"
  },
  {
    "path": "hal/phydm/rtl8822c/phydm_regconfig8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#ifndef __INC_ODM_REGCONFIG_H_8822C\n#define __INC_ODM_REGCONFIG_H_8822C\n\n#if (RTL8822C_SUPPORT)\n\nvoid odm_config_rf_reg_8822c(struct dm_struct *dm, u32 addr, u32 data,\n\t\t\t     enum rf_path rf_path, u32 reg_addr);\n\nvoid odm_config_rf_radio_a_8822c(struct dm_struct *dm, u32 addr, u32 data);\n\nvoid odm_config_rf_radio_b_8822c(struct dm_struct *dm, u32 addr, u32 data);\n\nvoid odm_config_mac_8822c(struct dm_struct *dm, u32 addr, u8 data);\n\nvoid odm_update_agc_big_jump_lmt_8822c(struct dm_struct *dm, u32 addr,\n\t\t\t\t       u32 data);\n\nvoid odm_config_bb_agc_8822c(struct dm_struct *dm, u32 addr, u32 bitmask,\n\t\t\t     u32 data);\n\nvoid odm_config_bb_phy_reg_pg_8822c(struct dm_struct *dm, u32 band, u32 rf_path,\n\t\t\t\t    u32 tx_num, u32 addr, u32 bitmask,\n\t\t\t\t    u32 data);\n\nvoid odm_config_bb_phy_8822c(struct dm_struct *dm, u32 addr, u32 bitmask,\n\t\t\t     u32 data);\n\nvoid odm_config_bb_txpwr_lmt_8822c(struct dm_struct *dm, u8 *regulation,\n\t\t\t\t   u8 *band, u8 *bandwidth, u8 *rate_section,\n\t\t\t\t   u8 *rf_path, u8 *channel, u8 *power_limit);\n\n#endif\n#endif /* RTL8822C_SUPPORT*/\n"
  },
  {
    "path": "hal/phydm/rtl8822c/phydm_rtl8822c.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#include \"mp_precomp.h\"\n#include \"../phydm_precomp.h\"\n\n#if (RTL8822C_SUPPORT)\nvoid phydm_dynamic_switch_htstf_agc_8822c(struct dm_struct *dm)\n{\n\tu8 ndp_valid_cnt = 0;\n\tu8 ndp_valid_cnt_diff = 0;\n\n\tif (dm->bhtstfdisabled)\n\t\treturn;\n\n\t/*set debug port to 0x51f*/\n\tif (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x51f)) {\n\t\tndp_valid_cnt = (u8)(phydm_get_bb_dbg_port_val(dm) & 0xff);\n\t\tphydm_release_bb_dbg_port(dm);\n\n\t\tndp_valid_cnt_diff = DIFF_2(dm->ndp_cnt_pre, ndp_valid_cnt);\n\t\tdm->ndp_cnt_pre = ndp_valid_cnt;\n\n\t\tif (ndp_valid_cnt_diff)\n\t\t\tdm->is_beamformed = true;\n\t\telse\n\t\t\tdm->is_beamformed = false;\n\n\t\tif (dm->total_tp == 0 || dm->is_beamformed) {\n\t\t\todm_set_bb_reg(dm, R_0x8a0, BIT(2), 0x1);\n\t\t\tdm->no_ndp_cnts = 0;\n\t\t} else {\n\t\t\tif (dm->no_ndp_cnts == 3)\n\t\t\t\todm_set_bb_reg(dm, R_0x8a0, BIT(2), 0x0);\n\t\t\telse if (dm->no_ndp_cnts < 3)\n\t\t\t\tdm->no_ndp_cnts++;\n\t\t}\n\t}\n}\n\nvoid phydm_hwsetting_8822c(struct dm_struct *dm)\n{\n\tphydm_dynamic_switch_htstf_agc_8822c(dm);\n}\n#endif\n"
  },
  {
    "path": "hal/phydm/rtl8822c/phydm_rtl8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#if (RTL8822C_SUPPORT)\n#ifndef __ODM_RTL8822C_H__\n#define __ODM_RTL8822C_H__\n\n/* 2019.08.20: modify code structure*/\n#define HW_SETTING_VERSION_8822C \"1.1\"\n\nenum phydm_bf_linked {\n\tPHYDM_IS_BF_LINKED\t= 1,\n\tPHYDM_NO_BF_LINKED\t= 2,\n};\n\nvoid phydm_hwsetting_8822c(struct dm_struct *dm);\n#endif\n#endif\n"
  },
  {
    "path": "hal/phydm/rtl8822c/version_rtl8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n/*RTL8822C PHY Parameters*/\n/* \n[Caution] \n  Since 01/Aug/2015, the commit rules will be simplified. You do not need to fill up the version.h anymore, \n  only the maintenance supervisor fills it before formal release.\n*/\n#define\tRELEASE_DATE_8822C\t\t20190605\n#define\tCOMMIT_BY_8822C\t\t\t\"BB_Allen\"\n#define\tRELEASE_VERSION_8822C\t41\n"
  },
  {
    "path": "hal/phydm/sd4_phydm_2_kernel.mk",
    "content": "EXTRA_CFLAGS += -I$(src)/hal/phydm\n\n_PHYDM_FILES := hal/phydm/phydm_debug.o\t\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_interface.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_phystatus.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_hwconfig.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_dig.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_rainfo.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_adaptivity.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_cfotracking.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_noisemonitor.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_beamforming.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_dfs.o\\\n\t\t\t\t\t\t\t\thal/phydm/txbf/halcomtxbf.o\\\n\t\t\t\t\t\t\t\thal/phydm/txbf/haltxbfinterface.o\\\n\t\t\t\t\t\t\t\thal/phydm/txbf/phydm_hal_txbf_api.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_ccx.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_cck_pd.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_rssi_monitor.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_math_lib.o\\\n\t\t\t\t\t\t\t\thal/phydm/phydm_api.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/halrf.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/halrf_debug.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/halphyrf_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/halrf_powertracking_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/halrf_powertracking.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/halrf_kfree.o\n\nifeq ($(CONFIG_RTL8188E), y)\nRTL871X = rtl8188e\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8188e_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8188e_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8188e.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/hal8188erateadaptive.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8188e.o\nendif\n\nifeq ($(CONFIG_RTL8192E), y)\nRTL871X = rtl8192e\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8192e_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8192e_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8192e.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8192e.o\nendif\n\n\nifeq ($(CONFIG_RTL8812A), y)\nRTL871X = rtl8812a\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8812a_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8812a_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8812a.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8812a.o\\\n\t\t\t\t\t\t\t\thal/phydm/txbf/haltxbfjaguar.o\nendif\n\nifeq ($(CONFIG_RTL8821A), y)\nRTL871X = rtl8821a\n_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/rtl8821a/halhwimg8821a_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/rtl8821a/halhwimg8821a_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/rtl8821a/phydm_regconfig8821a.o\\\n\t\t\t\t\t\t\t\thal/phydm/rtl8821a/phydm_rtl8821a.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/txbf/haltxbfjaguar.o\nendif\n\n\nifeq ($(CONFIG_RTL8723B), y)\nRTL871X = rtl8723b\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8723b_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8723b_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8723b_mp.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8723b.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8723b.o\nendif\n\n\nifeq ($(CONFIG_RTL8814A), y)\nRTL871X = rtl8814a\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8814a_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8814a_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8814a.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8814a.o\\\n\t\t\t\t\t\t\t\thal/phydm/txbf/haltxbf8814a.o\nendif\n\n\nifeq ($(CONFIG_RTL8723C), y)\nRTL871X = rtl8703b\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8703b_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8703b_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8703b.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8703b.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8703b.o\nendif\n\nifeq ($(CONFIG_RTL8723D), y)\nRTL871X = rtl8723d\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8723d_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8723d_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8723d.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8723d.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8723d.o\nendif\n\n\nifeq ($(CONFIG_RTL8710B), y)\nRTL871X = rtl8710b\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8710b_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8710b_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8710b.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8710b.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8710b.o\nendif\n\n\nifeq ($(CONFIG_RTL8188F), y)\nRTL871X = rtl8188f\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8188f_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8188f_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8188f.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8188f.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8188f.o\nendif\n\nifeq ($(CONFIG_RTL8822B), y)\nRTL871X = rtl8822b\n_PHYDM_FILES +=\thal/phydm/$(RTL871X)/halhwimg8822b_bb.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8822b_mac.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8822b_rf.o \\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8822b.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_hal_api8822b.o \\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8822b.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8822b.o\n\n_PHYDM_FILES +=\thal/phydm/txbf/haltxbf8822b.o\nendif\n\n\nifeq ($(CONFIG_RTL8821C), y)\nRTL871X = rtl8821c\n_PHYDM_FILES +=\thal/phydm/$(RTL871X)/halhwimg8821c_bb.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8821c_mac.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8821c_rf.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_hal_api8821c.o \\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8821c.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8821c.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o\nendif\nifeq ($(CONFIG_RTL8192F), y)\nRTL871X = rtl8192f\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8192f_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8192f_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_hal_api8192f.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8192f.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_rtl8192f.o\\\n\t\t\t\t\t\t\t\thal/phydm/halrf/$(RTL871X)/halrf_8192f.o\nendif\n\nifeq ($(CONFIG_RTL8198F), y)\nRTL871X = rtl8198f\n_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8198f_mac.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/halhwimg8198f_rf.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_hal_api8198f.o\\\n\t\t\t\t\t\t\t\thal/phydm/$(RTL871X)/phydm_regconfig8198f.o\nendif\n"
  },
  {
    "path": "hal/phydm/txbf/halcomtxbf.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n/*@************************************************************\n * Description:\n *\n * This file is for TXBF mechanism\n *\n ************************************************************/\n#include \"mp_precomp.h\"\n#include \"../phydm_precomp.h\"\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n/*@Beamforming halcomtxbf API create by YuChen 2015/05*/\n\nvoid hal_com_txbf_beamform_init(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tboolean is_iqgen_setting_ok = false;\n\n\tif (dm->support_ic_type & ODM_RTL8814A) {\n\t\tis_iqgen_setting_ok = phydm_beamforming_set_iqgen_8814A(dm);\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] is_iqgen_setting_ok = %d\\n\",\n\t\t\t  __func__, is_iqgen_setting_ok);\n\t}\n}\n\n/*Only used for MU BFer Entry when get GID management frame (self as MU STA)*/\nvoid hal_com_txbf_config_gtab(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->support_ic_type & ODM_RTL8822B)\n\t\thal_txbf_8822b_config_gtab(dm);\n}\n\nvoid phydm_beamform_set_sounding_enter(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tstruct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;\n\n\tif (!odm_is_work_item_scheduled(&p_txbf_info->txbf_enter_work_item))\n\t\todm_schedule_work_item(&p_txbf_info->txbf_enter_work_item);\n#else\n\thal_com_txbf_enter_work_item_callback(dm);\n#endif\n}\n\nvoid phydm_beamform_set_sounding_leave(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tstruct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;\n\n\tif (!odm_is_work_item_scheduled(&p_txbf_info->txbf_leave_work_item))\n\t\todm_schedule_work_item(&p_txbf_info->txbf_leave_work_item);\n#else\n\thal_com_txbf_leave_work_item_callback(dm);\n#endif\n}\n\nvoid phydm_beamform_set_sounding_rate(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tstruct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;\n\n\tif (!odm_is_work_item_scheduled(&p_txbf_info->txbf_rate_work_item))\n\t\todm_schedule_work_item(&p_txbf_info->txbf_rate_work_item);\n#else\n\thal_com_txbf_rate_work_item_callback(dm);\n#endif\n}\n\nvoid phydm_beamform_set_sounding_status(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tstruct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;\n\n\tif (!odm_is_work_item_scheduled(&p_txbf_info->txbf_status_work_item))\n\t\todm_schedule_work_item(&p_txbf_info->txbf_status_work_item);\n#else\n\thal_com_txbf_status_work_item_callback(dm);\n#endif\n}\n\nvoid phydm_beamform_set_sounding_fw_ndpa(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tstruct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;\n\n\tif (*dm->is_fw_dw_rsvd_page_in_progress)\n\t\todm_set_timer(dm, &p_txbf_info->txbf_fw_ndpa_timer, 5);\n\telse\n\t\todm_schedule_work_item(&p_txbf_info->txbf_fw_ndpa_work_item);\n#else\n\thal_com_txbf_fw_ndpa_work_item_callback(dm);\n#endif\n}\n\nvoid phydm_beamform_set_sounding_clk(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tstruct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;\n\n\tif (!odm_is_work_item_scheduled(&p_txbf_info->txbf_clk_work_item))\n\t\todm_schedule_work_item(&p_txbf_info->txbf_clk_work_item);\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tphydm_run_in_thread_cmd(dm, hal_com_txbf_clk_work_item_callback, dm);\n#else\n\thal_com_txbf_clk_work_item_callback(dm);\n#endif\n}\n\nvoid phydm_beamform_set_reset_tx_path(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tstruct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;\n\tstruct _RT_WORK_ITEM *pwi = &p_txbf_info->txbf_reset_tx_path_work_item;\n\n\tif (!odm_is_work_item_scheduled(pwi))\n\t\todm_schedule_work_item(pwi);\n#else\n\thal_com_txbf_reset_tx_path_work_item_callback(dm);\n#endif\n}\n\nvoid phydm_beamform_set_get_tx_rate(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tstruct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;\n\tstruct _RT_WORK_ITEM *pwi = &p_txbf_info->txbf_get_tx_rate_work_item;\n\n\tif (!odm_is_work_item_scheduled(pwi))\n\t\todm_schedule_work_item(pwi);\n#else\n\thal_com_txbf_get_tx_rate_work_item_callback(dm);\n#endif\n}\n\nvoid hal_com_txbf_enter_work_item_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter\n#else\n\tvoid *dm_void\n#endif\n\t)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tPHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n#else\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#endif\n\tstruct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;\n\tu8 idx = p_txbf_info->txbf_idx;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tif (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))\n\t\thal_txbf_jaguar_enter(dm, idx);\n\telse if (dm->support_ic_type & ODM_RTL8192E)\n\t\thal_txbf_8192e_enter(dm, idx);\n\telse if (dm->support_ic_type & ODM_RTL8814A)\n\t\thal_txbf_8814a_enter(dm, idx);\n\telse if (dm->support_ic_type & ODM_RTL8822B)\n\t\thal_txbf_8822b_enter(dm, idx);\n}\n\nvoid hal_com_txbf_leave_work_item_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter\n#else\n\tvoid *dm_void\n#endif\n\t)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tPHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n#else\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#endif\n\tstruct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;\n\n\tu8 idx = p_txbf_info->txbf_idx;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tif (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))\n\t\thal_txbf_jaguar_leave(dm, idx);\n\telse if (dm->support_ic_type & ODM_RTL8192E)\n\t\thal_txbf_8192e_leave(dm, idx);\n\telse if (dm->support_ic_type & ODM_RTL8814A)\n\t\thal_txbf_8814a_leave(dm, idx);\n\telse if (dm->support_ic_type & ODM_RTL8822B)\n\t\thal_txbf_8822b_leave(dm, idx);\n}\n\nvoid hal_com_txbf_fw_ndpa_work_item_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter\n#else\n\tvoid *dm_void\n#endif\n\t)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tPHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n#else\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#endif\n\tstruct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;\n\tu8 idx = p_txbf_info->ndpa_idx;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tif (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))\n\t\thal_txbf_jaguar_fw_txbf(dm, idx);\n\telse if (dm->support_ic_type & ODM_RTL8192E)\n\t\thal_txbf_8192e_fw_tx_bf(dm, idx);\n\telse if (dm->support_ic_type & ODM_RTL8814A)\n\t\thal_txbf_8814a_fw_txbf(dm, idx);\n\telse if (dm->support_ic_type & ODM_RTL8822B)\n\t\thal_txbf_8822b_fw_txbf(dm, idx);\n}\n\nvoid hal_com_txbf_clk_work_item_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter\n#else\n\tvoid *dm_void\n#endif\n\t)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tPHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n#else\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#endif\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tif (dm->support_ic_type & ODM_RTL8812)\n\t\thal_txbf_jaguar_clk_8812a(dm);\n}\n\nvoid hal_com_txbf_rate_work_item_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter\n#else\n\tvoid *dm_void\n#endif\n\t)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tPHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n#else\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#endif\n\tstruct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;\n\tu8 BW = p_txbf_info->BW;\n\tu8 rate = p_txbf_info->rate;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tif (dm->support_ic_type & ODM_RTL8812)\n\t\thal_txbf_8812a_set_ndpa_rate(dm, BW, rate);\n\telse if (dm->support_ic_type & ODM_RTL8192E)\n\t\thal_txbf_8192e_set_ndpa_rate(dm, BW, rate);\n\telse if (dm->support_ic_type & ODM_RTL8814A)\n\t\thal_txbf_8814a_set_ndpa_rate(dm, BW, rate);\n}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid hal_com_txbf_fw_ndpa_timer_callback(\n\tstruct phydm_timer_list *timer)\n{\n\tvoid *adapter = (void *)timer->Adapter;\n\tPHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\n\tstruct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tif (*dm->is_fw_dw_rsvd_page_in_progress)\n\t\todm_set_timer(dm, &(p_txbf_info->txbf_fw_ndpa_timer), 5);\n\telse\n\t\todm_schedule_work_item(&(p_txbf_info->txbf_fw_ndpa_work_item));\n}\n#endif\n\nvoid hal_com_txbf_status_work_item_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter\n#else\n\tvoid *dm_void\n#endif\n\t)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tPHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n#else\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#endif\n\tstruct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;\n\n\tu8 idx = p_txbf_info->txbf_idx;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tif (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))\n\t\thal_txbf_jaguar_status(dm, idx);\n\telse if (dm->support_ic_type & ODM_RTL8192E)\n\t\thal_txbf_8192e_status(dm, idx);\n\telse if (dm->support_ic_type & ODM_RTL8814A)\n\t\thal_txbf_8814a_status(dm, idx);\n\telse if (dm->support_ic_type & ODM_RTL8822B)\n\t\thal_txbf_8822b_status(dm, idx);\n}\n\nvoid hal_com_txbf_reset_tx_path_work_item_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter\n#else\n\tvoid *dm_void\n#endif\n\t)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tPHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n#else\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#endif\n\tstruct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;\n\n\tu8 idx = p_txbf_info->txbf_idx;\n\n\tif (dm->support_ic_type & ODM_RTL8814A)\n\t\thal_txbf_8814a_reset_tx_path(dm, idx);\n}\n\nvoid hal_com_txbf_get_tx_rate_work_item_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter\n#else\n\tvoid *dm_void\n#endif\n\t)\n{\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tPHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n#else\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#endif\n\n\tif (dm->support_ic_type & ODM_RTL8814A)\n\t\thal_txbf_8814a_get_tx_rate(dm);\n}\n\nboolean\nhal_com_txbf_set(\n\tvoid *dm_void,\n\tu8 set_type,\n\tvoid *p_in_buf)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 *p_u1_tmp = (u8 *)p_in_buf;\n\tstruct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] set_type = 0x%X\\n\", __func__, set_type);\n\n\tswitch (set_type) {\n\tcase TXBF_SET_SOUNDING_ENTER:\n\t\tp_txbf_info->txbf_idx = *p_u1_tmp;\n\t\tphydm_beamform_set_sounding_enter(dm);\n\t\tbreak;\n\n\tcase TXBF_SET_SOUNDING_LEAVE:\n\t\tp_txbf_info->txbf_idx = *p_u1_tmp;\n\t\tphydm_beamform_set_sounding_leave(dm);\n\t\tbreak;\n\n\tcase TXBF_SET_SOUNDING_RATE:\n\t\tp_txbf_info->BW = p_u1_tmp[0];\n\t\tp_txbf_info->rate = p_u1_tmp[1];\n\t\tphydm_beamform_set_sounding_rate(dm);\n\t\tbreak;\n\n\tcase TXBF_SET_SOUNDING_STATUS:\n\t\tp_txbf_info->txbf_idx = *p_u1_tmp;\n\t\tphydm_beamform_set_sounding_status(dm);\n\t\tbreak;\n\n\tcase TXBF_SET_SOUNDING_FW_NDPA:\n\t\tp_txbf_info->ndpa_idx = *p_u1_tmp;\n\t\tphydm_beamform_set_sounding_fw_ndpa(dm);\n\t\tbreak;\n\n\tcase TXBF_SET_SOUNDING_CLK:\n\t\tphydm_beamform_set_sounding_clk(dm);\n\t\tbreak;\n\n\tcase TXBF_SET_TX_PATH_RESET:\n\t\tp_txbf_info->txbf_idx = *p_u1_tmp;\n\t\tphydm_beamform_set_reset_tx_path(dm);\n\t\tbreak;\n\n\tcase TXBF_SET_GET_TX_RATE:\n\t\tphydm_beamform_set_get_tx_rate(dm);\n\t\tbreak;\n\t}\n\n\treturn true;\n}\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nboolean\nhal_com_txbf_get(\n\tvoid *adapter,\n\tu8 get_type,\n\tvoid *p_out_buf)\n{\n\tPHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\tboolean *p_boolean = (boolean *)p_out_buf;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tif (get_type == TXBF_GET_EXPLICIT_BEAMFORMEE) {\n\t\tif (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter))\n\t\t\t*p_boolean = false;\n\t\telse if (/*@IS_HARDWARE_TYPE_8822B(adapter)\t||*/\n\t\t\t IS_HARDWARE_TYPE_8821B(adapter) ||\n\t\t\t IS_HARDWARE_TYPE_8192E(adapter) ||\n\t\t\t IS_HARDWARE_TYPE_8192F(adapter) ||\n\t\t\t IS_HARDWARE_TYPE_JAGUAR(adapter) ||\n\t\t\t IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter) ||\n\t\t\t IS_HARDWARE_TYPE_JAGUAR3(adapter))\n\t\t\t*p_boolean = true;\n\t\telse\n\t\t\t*p_boolean = false;\n\t} else if (get_type == TXBF_GET_EXPLICIT_BEAMFORMER) {\n\t\tif (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter))\n\t\t\t*p_boolean = false;\n\t\telse if (/*@IS_HARDWARE_TYPE_8822B(adapter)\t||*/\n\t\t\t IS_HARDWARE_TYPE_8821B(adapter) ||\n\t\t\t IS_HARDWARE_TYPE_8192E(adapter) ||\n\t\t\t IS_HARDWARE_TYPE_8192F(adapter) ||\n\t\t\t IS_HARDWARE_TYPE_JAGUAR(adapter) ||\n\t\t\t IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter) ||\n\t\t\t IS_HARDWARE_TYPE_JAGUAR3(adapter)) {\n\t\t\tif (hal_data->RF_Type == RF_2T2R ||\n\t\t\t    hal_data->RF_Type == RF_3T3R ||\n\t\t\t    hal_data->RF_Type == RF_4T4R)\n\t\t\t\t*p_boolean = true;\n\t\t\telse\n\t\t\t\t*p_boolean = false;\n\t\t} else\n\t\t\t*p_boolean = false;\n\t} else if (get_type == TXBF_GET_MU_MIMO_STA) {\n#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) ||\\\n\t(RTL8822C_SUPPORT == 1))\n\t\tif (IS_HARDWARE_TYPE_8822B(adapter) ||\n\t\t    IS_HARDWARE_TYPE_8821C(adapter) ||\n\t\t    IS_HARDWARE_TYPE_JAGUAR3(adapter))\n\t\t\t*p_boolean = true;\n\t\telse\n#endif\n\t\t\t*p_boolean = false;\n\n\t} else if (get_type == TXBF_GET_MU_MIMO_AP) {\n#if ((RTL8822B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))\n\t\tif (IS_HARDWARE_TYPE_8822B(adapter) ||\n\t\t    IS_HARDWARE_TYPE_JAGUAR3(adapter))\n\t\t\t*p_boolean = true;\n\t\telse\n#endif\n\t\t\t*p_boolean = false;\n\t}\n\n\treturn true;\n}\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/phydm/txbf/halcomtxbf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#ifndef __HAL_COM_TXBF_H__\n#define __HAL_COM_TXBF_H__\n\n#if 0\ntypedef\tbool\n(*TXBF_GET)(\n\tvoid*\t\t\tadapter,\n\tu8\t\t\tget_type,\n\tvoid*\t\t\tp_out_buf\n\t);\n\ntypedef\tbool\n(*TXBF_SET)(\n\tvoid*\t\t\tadapter,\n\tu8\t\t\tset_type,\n\tvoid*\t\t\tp_in_buf\n\t);\n#endif\n\nenum txbf_set_type {\n\tTXBF_SET_SOUNDING_ENTER,\n\tTXBF_SET_SOUNDING_LEAVE,\n\tTXBF_SET_SOUNDING_RATE,\n\tTXBF_SET_SOUNDING_STATUS,\n\tTXBF_SET_SOUNDING_FW_NDPA,\n\tTXBF_SET_SOUNDING_CLK,\n\tTXBF_SET_TX_PATH_RESET,\n\tTXBF_SET_GET_TX_RATE\n};\n\nenum txbf_get_type {\n\tTXBF_GET_EXPLICIT_BEAMFORMEE,\n\tTXBF_GET_EXPLICIT_BEAMFORMER,\n\tTXBF_GET_MU_MIMO_STA,\n\tTXBF_GET_MU_MIMO_AP\n};\n\n/* @2 HAL TXBF related */\nstruct _HAL_TXBF_INFO {\n\tu8 txbf_idx;\n\tu8 ndpa_idx;\n\tu8 BW;\n\tu8 rate;\n\n\tstruct phydm_timer_list txbf_fw_ndpa_timer;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tRT_WORK_ITEM txbf_enter_work_item;\n\tRT_WORK_ITEM txbf_leave_work_item;\n\tRT_WORK_ITEM txbf_fw_ndpa_work_item;\n\tRT_WORK_ITEM txbf_clk_work_item;\n\tRT_WORK_ITEM txbf_status_work_item;\n\tRT_WORK_ITEM txbf_rate_work_item;\n\tRT_WORK_ITEM txbf_reset_tx_path_work_item;\n\tRT_WORK_ITEM txbf_get_tx_rate_work_item;\n#endif\n};\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\nvoid hal_com_txbf_beamform_init(\n\tvoid *dm_void);\n\nvoid hal_com_txbf_config_gtab(\n\tvoid *dm_void);\n\nvoid hal_com_txbf_enter_work_item_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter\n#else\n\tvoid *dm_void\n#endif\n\t);\n\nvoid hal_com_txbf_leave_work_item_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter\n#else\n\tvoid *dm_void\n#endif\n\t);\n\nvoid hal_com_txbf_fw_ndpa_work_item_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter\n#else\n\tvoid *dm_void\n#endif\n\t);\n\nvoid hal_com_txbf_clk_work_item_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter\n#else\n\tvoid *dm_void\n#endif\n\t);\n\nvoid hal_com_txbf_reset_tx_path_work_item_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter\n#else\n\tvoid *dm_void\n#endif\n\t);\n\nvoid hal_com_txbf_get_tx_rate_work_item_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter\n#else\n\tvoid *dm_void\n#endif\n\t);\n\nvoid hal_com_txbf_rate_work_item_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter\n#else\n\tvoid *dm_void\n#endif\n\t);\n\nvoid hal_com_txbf_fw_ndpa_timer_callback(\n\tstruct phydm_timer_list *timer);\n\nvoid hal_com_txbf_status_work_item_callback(\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tvoid *adapter\n#else\n\tvoid *dm_void\n#endif\n\t);\n\nboolean\nhal_com_txbf_set(\n\tvoid *dm_void,\n\tu8 set_type,\n\tvoid *p_in_buf);\n\nboolean\nhal_com_txbf_get(\n\tvoid *adapter,\n\tu8 get_type,\n\tvoid *p_out_buf);\n\n#else\n#define hal_com_txbf_beamform_init(dm_void) NULL\n#define hal_com_txbf_config_gtab(dm_void) NULL\n#define hal_com_txbf_enter_work_item_callback(_adapter) NULL\n#define hal_com_txbf_leave_work_item_callback(_adapter) NULL\n#define hal_com_txbf_fw_ndpa_work_item_callback(_adapter) NULL\n#define hal_com_txbf_clk_work_item_callback(_adapter) NULL\n#define hal_com_txbf_rate_work_item_callback(_adapter) NULL\n#define hal_com_txbf_fw_ndpa_timer_callback(_adapter) NULL\n#define hal_com_txbf_status_work_item_callback(_adapter) NULL\n#define hal_com_txbf_get(_adapter, _get_type, _pout_buf)\n\n#endif\n\n#endif /*  @#ifndef __HAL_COM_TXBF_H__ */\n"
  },
  {
    "path": "hal/phydm/txbf/haltxbf8192e.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n/*************************************************************\n * Description:\n *\n * This file is for 8192E TXBF mechanism\n *\n ************************************************************/\n#include \"mp_precomp.h\"\n#include \"../phydm_precomp.h\"\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n#if (RTL8192E_SUPPORT == 1)\n\nvoid hal_txbf_8192e_set_ndpa_rate(\n\tvoid *dm_void,\n\tu8 BW,\n\tu8 rate)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\todm_write_1byte(dm, REG_NDPA_OPT_CTRL_8192E, (rate << 2 | BW));\n}\n\nvoid hal_txbf_8192e_rf_mode(\n\tvoid *dm_void,\n\tstruct _RT_BEAMFORMING_INFO *beam_info)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tif (dm->rf_type == RF_1T1R)\n\t\treturn;\n\n\todm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/\n\todm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/\n\n\tif (beam_info->beamformee_su_cnt > 0) {\n\t\t/*Path_A*/\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode  0x30=0x18000*/\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/\n\t\t/*Path_B*/\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/\n\t} else {\n\t\t/*Path_A*/\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/\n\t\t/*Path_B*/\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/\n\t}\n\n\todm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/\n\todm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/\n\n\tif (beam_info->beamformee_su_cnt > 0) {\n\t\todm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333);\n\t\todm_set_bb_reg(dm, R_0xa04, MASKBYTE3, 0xc1);\n\t} else\n\t\todm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121313);\n}\n\nvoid hal_txbf_8192e_fw_txbf_cmd(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 idx, period0 = 0, period1 = 0;\n\tu8 PageNum0 = 0xFF, PageNum1 = 0xFF;\n\tu8 u1_tx_bf_parm[3] = {0};\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\n\tfor (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {\n\t\tif (beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {\n\t\t\tif (idx == 0) {\n\t\t\t\tif (beam_info->beamformee_entry[idx].is_sound)\n\t\t\t\t\tPageNum0 = 0xFE;\n\t\t\t\telse\n\t\t\t\t\tPageNum0 = 0xFF; /* stop sounding */\n\t\t\t\tperiod0 = (u8)(beam_info->beamformee_entry[idx].sound_period);\n\t\t\t} else if (idx == 1) {\n\t\t\t\tif (beam_info->beamformee_entry[idx].is_sound)\n\t\t\t\t\tPageNum1 = 0xFE;\n\t\t\t\telse\n\t\t\t\t\tPageNum1 = 0xFF; /* stop sounding */\n\t\t\t\tperiod1 = (u8)(beam_info->beamformee_entry[idx].sound_period);\n\t\t\t}\n\t\t}\n\t}\n\n\tu1_tx_bf_parm[0] = PageNum0;\n\tu1_tx_bf_parm[1] = PageNum1;\n\tu1_tx_bf_parm[2] = (period1 << 4) | period0;\n\todm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);\n\n\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t  \"[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\\n\",\n\t\t  __func__, PageNum0, period0, PageNum1, period1);\n}\n\nvoid hal_txbf_8192e_download_ndpa(\n\tvoid *dm_void,\n\tu8 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 u1b_tmp = 0, tmp_reg422 = 0, head_page;\n\tu8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;\n\tboolean is_send_beacon = false;\n\tu8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812;\n\t/*@default reseved 1 page for the IC type which is undefined.*/\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t*dm->is_fw_dw_rsvd_page_in_progress = true;\n#endif\n\tif (idx == 0)\n\t\thead_page = 0xFE;\n\telse\n\t\thead_page = 0xFE;\n\n\tphydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy);\n\n\t/*Set REG_CR bit 8. DMA beacon by SW.*/\n\tu1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1);\n\todm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp | BIT(0)));\n\n\t/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/\n\ttmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2);\n\todm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422 & (~BIT(6)));\n\n\tif (tmp_reg422 & BIT(6)) {\n\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t  \"%s There is an adapter is sending beacon.\\n\",\n\t\t\t  __func__);\n\t\tis_send_beacon = true;\n\t}\n\n\t/*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD\tNDPA Head for TXDMA*/\n\todm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, head_page);\n\n\tdo {\n\t\t/*@Clear beacon valid check bit.*/\n\t\tbcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);\n\t\todm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 2, (bcn_valid_reg | BIT(0)));\n\n\t\t/* @download NDPA rsvd page. */\n\t\tbeamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);\n\n#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)\n\t\tif (dm->support_interface == ODM_ITRF_PCIE) {\n\t\t\tu1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3);\n\t\t\tcount = 0;\n\t\t\twhile ((count < 20) && (u1b_tmp & BIT(4))) {\n\t\t\t\tcount++;\n\t\t\t\tODM_delay_us(10);\n\t\t\t\tu1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3);\n\t\t\t}\n\t\t\todm_write_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3, u1b_tmp | BIT(4));\n\t\t}\n#endif\n\n\t\t/*@check rsvd page download OK.*/\n\t\tbcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);\n\t\tcount = 0;\n\t\twhile (!(bcn_valid_reg & BIT(0)) && count < 20) {\n\t\t\tcount++;\n\t\t\tODM_delay_us(10);\n\t\t\tbcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);\n\t\t}\n\t\tdl_bcn_count++;\n\t} while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5);\n\n\tif (!(bcn_valid_reg & BIT(0)))\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s Download RSVD page failed!\\n\",\n\t\t\t  __func__);\n\n\t/*TDECTRL[15:8] 0x209[7:0] = 0xF9\tBeacon Head for TXDMA*/\n\todm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, tx_page_bndy);\n\n\t/*To make sure that if there exists an adapter which would like to send beacon.*/\n\t/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/\n\t/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/\n\t/*the beacon cannot be sent by HW.*/\n\t/*@2010.06.23. Added by tynli.*/\n\tif (is_send_beacon)\n\t\todm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422);\n\n\t/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/\n\t/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/\n\tu1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1);\n\todm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp & (~BIT(0))));\n\n\tp_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t*dm->is_fw_dw_rsvd_page_in_progress = false;\n#endif\n}\n\nvoid hal_txbf_8192e_enter(\n\tvoid *dm_void,\n\tu8 bfer_bfee_idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i = 0;\n\tu8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;\n\tu8 bfee_idx = (bfer_bfee_idx & 0xF);\n\tu32 csi_param;\n\tstruct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY beamformee_entry;\n\tstruct _RT_BEAMFORMER_ENTRY beamformer_entry;\n\tu16 sta_id = 0;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\thal_txbf_8192e_rf_mode(dm, beamforming_info);\n\n\tif (dm->rf_type == RF_2T2R)\n\t\todm_write_4byte(dm, 0xd80, 0x00000000); /*nc =2*/\n\n\tif (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {\n\t\tbeamformer_entry = beamforming_info->beamformer_entry[bfer_idx];\n\n\t\t/*Sounding protocol control*/\n\t\todm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xCB);\n\n\t\t/*@MAC address/Partial AID of Beamformer*/\n\t\tif (bfer_idx == 0) {\n\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\todm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8192E + i), beamformer_entry.mac_addr[i]);\n\t\t} else {\n\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\todm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8192E + i), beamformer_entry.mac_addr[i]);\n\t\t}\n\n\t\t/*@CSI report parameters of Beamformer Default use nc = 2*/\n\t\tcsi_param = 0x03090309;\n\n\t\todm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8192E, csi_param);\n\t\todm_write_4byte(dm, REG_CSI_RPT_PARAM_BW40_8192E, csi_param);\n\t\todm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8192E, csi_param);\n\n\t\t/*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us,  MP chip)*/\n\t\todm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E + 3, 0x50);\n\t}\n\n\tif (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {\n\t\tbeamformee_entry = beamforming_info->beamformee_entry[bfee_idx];\n\n\t\tif (phydm_acting_determine(dm, phydm_acting_as_ibss))\n\t\t\tsta_id = beamformee_entry.mac_id;\n\t\telse\n\t\t\tsta_id = beamformee_entry.p_aid;\n\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"[%s], sta_id=0x%X\\n\", __func__,\n\t\t\t  sta_id);\n\n\t\t/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/\n\t\tif (bfee_idx == 0) {\n\t\t\todm_write_2byte(dm, REG_TXBF_CTRL_8192E, sta_id);\n\t\t\todm_write_1byte(dm, REG_TXBF_CTRL_8192E + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 3) | BIT(4) | BIT(6) | BIT(7));\n\t\t} else\n\t\t\todm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, sta_id | BIT(12) | BIT(14) | BIT(15));\n\n\t\t/*@CSI report parameters of Beamformee*/\n\t\tif (bfee_idx == 0) {\n\t\t\t/*@Get BIT24 & BIT25*/\n\t\t\tu8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3) & 0x3;\n\n\t\t\todm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3, tmp | 0x60);\n\t\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, sta_id | BIT(9));\n\t\t} else {\n\t\t\t/*Set BIT25*/\n\t\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, sta_id | 0xE200);\n\t\t}\n\t\tphydm_beamforming_notify(dm);\n\t}\n}\n\nvoid hal_txbf_8192e_leave(\n\tvoid *dm_void,\n\tu8 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\n\thal_txbf_8192e_rf_mode(dm, beam_info);\n\n\t/*\t@Clear P_AID of Beamformee\n\t*\tClear MAC addresss of Beamformer\n\t*\tClear Associated Bfmee Sel\n\t*/\n\tif (beam_info->beamform_cap == BEAMFORMING_CAP_NONE)\n\t\todm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xC8);\n\n\tif (idx == 0) {\n\t\todm_write_2byte(dm, REG_TXBF_CTRL_8192E, 0);\n\t\todm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0);\n\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E + 4, 0);\n\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0);\n\t} else {\n\t\todm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 2) & 0xF000);\n\t\todm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0);\n\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E + 4, 0);\n\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2) & 0x60);\n\t}\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] idx %d\\n\", __func__, idx);\n}\n\nvoid hal_txbf_8192e_status(\n\tvoid *dm_void,\n\tu8 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu16 beam_ctrl_val;\n\tu32 beam_ctrl_reg;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx];\n\n\tif (phydm_acting_determine(dm, phydm_acting_as_ibss))\n\t\tbeam_ctrl_val = beamform_entry.mac_id;\n\telse\n\t\tbeam_ctrl_val = beamform_entry.p_aid;\n\n\tif (idx == 0)\n\t\tbeam_ctrl_reg = REG_TXBF_CTRL_8192E;\n\telse {\n\t\tbeam_ctrl_reg = REG_TXBF_CTRL_8192E + 2;\n\t\tbeam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);\n\t}\n\n\tif (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beam_info->apply_v_matrix == true) {\n\t\tif (beamform_entry.sound_bw == CHANNEL_WIDTH_20)\n\t\t\tbeam_ctrl_val |= BIT(9);\n\t\telse if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)\n\t\t\tbeam_ctrl_val |= BIT(10);\n\t} else\n\t\tbeam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));\n\n\todm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);\n\n\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t  \"[%s] idx %d beam_ctrl_reg %x beam_ctrl_val %x\\n\", __func__,\n\t\t  idx, beam_ctrl_reg, beam_ctrl_val);\n}\n\nvoid hal_txbf_8192e_fw_tx_bf(\n\tvoid *dm_void,\n\tu8 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tif (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)\n\t\thal_txbf_8192e_download_ndpa(dm, idx);\n\n\thal_txbf_8192e_fw_txbf_cmd(dm);\n}\n\n#endif /* @#if (RTL8192E_SUPPORT == 1)*/\n\n#endif\n"
  },
  {
    "path": "hal/phydm/txbf/haltxbf8192e.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#ifndef __HAL_TXBF_8192E_H__\n#define __HAL_TXBF_8192E_H__\n\n#if (RTL8192E_SUPPORT == 1)\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\nvoid hal_txbf_8192e_set_ndpa_rate(\n\tvoid *dm_void,\n\tu8 BW,\n\tu8 rate);\n\nvoid hal_txbf_8192e_enter(\n\tvoid *dm_void,\n\tu8 idx);\n\nvoid hal_txbf_8192e_leave(\n\tvoid *dm_void,\n\tu8 idx);\n\nvoid hal_txbf_8192e_status(\n\tvoid *dm_void,\n\tu8 idx);\n\nvoid hal_txbf_8192e_fw_tx_bf(\n\tvoid *dm_void,\n\tu8 idx);\n#else\n\n#define hal_txbf_8192e_set_ndpa_rate(dm_void, BW, rate)\n#define hal_txbf_8192e_enter(dm_void, idx)\n#define hal_txbf_8192e_leave(dm_void, idx)\n#define hal_txbf_8192e_status(dm_void, idx)\n#define hal_txbf_8192e_fw_tx_bf(dm_void, idx)\n\n#endif\n\n#else\n\n#define hal_txbf_8192e_set_ndpa_rate(dm_void, BW, rate)\n#define hal_txbf_8192e_enter(dm_void, idx)\n#define hal_txbf_8192e_leave(dm_void, idx)\n#define hal_txbf_8192e_status(dm_void, idx)\n#define hal_txbf_8192e_fw_tx_bf(dm_void, idx)\n\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/phydm/txbf/haltxbf8814a.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n/* ************************************************************\n * Description:\n *\n * This file is for 8814A TXBF mechanism\n *\n * ************************************************************ */\n\n#include \"mp_precomp.h\"\n#include \"../phydm_precomp.h\"\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n#if (RTL8814A_SUPPORT == 1)\n\nboolean\nphydm_beamforming_set_iqgen_8814A(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i = 0;\n\tu16 counter = 0;\n\tu32 rf_mode[4];\n\n\tfor (i = RF_PATH_A; i < MAX_RF_PATH; i++)\n\t\todm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/\n\n\twhile (1) {\n\t\tcounter++;\n\t\tfor (i = RF_PATH_A; i < MAX_RF_PATH; i++)\n\t\t\todm_set_rf_reg(dm, i, RF_RCK_OS, 0xfffff, 0x18000); /*Select Rx mode*/\n\n\t\tODM_delay_us(2);\n\n\t\tfor (i = RF_PATH_A; i < MAX_RF_PATH; i++)\n\t\t\trf_mode[i] = odm_get_rf_reg(dm, i, RF_RCK_OS, 0xfffff);\n\n\t\tif (rf_mode[0] == 0x18000 && rf_mode[1] == 0x18000 && rf_mode[2] == 0x18000 && rf_mode[3] == 0x18000)\n\t\t\tbreak;\n\t\telse if (counter == 100) {\n\t\t\tPHYDM_DBG(dm, DBG_TXBF, \"iqgen setting fail:8814A\\n\");\n\t\t\treturn false;\n\t\t}\n\t}\n\n\tfor (i = RF_PATH_A; i < MAX_RF_PATH; i++) {\n\t\todm_set_rf_reg(dm, i, RF_TXPA_G1, 0xfffff, 0xBE77F); /*Set Table data*/\n\t\todm_set_rf_reg(dm, i, RF_TXPA_G2, 0xfffff, 0x226BF); /*@Enable TXIQGEN in Rx mode*/\n\t}\n\todm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in Rx mode*/\n\n\tfor (i = RF_PATH_A; i < MAX_RF_PATH; i++)\n\t\todm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/\n\n\treturn true;\n}\n\nvoid hal_txbf_8814a_set_ndpa_rate(void *dm_void, u8 BW, u8 rate)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\todm_write_1byte(dm, REG_NDPA_OPT_CTRL_8814A, BW);\n\todm_write_1byte(dm, REG_NDPA_RATE_8814A, (u8)rate);\n}\n#if 0\n#define PHYDM_MEMORY_MAP_BUF_READ 0x8000\n#define PHYDM_CTRL_INFO_PAGE 0x660\n\nvoid\nphydm_data_rate_8814a(\n\tstruct dm_struct\t\t\t*dm,\n\tu8\t\t\t\tmac_id,\n\tu32\t\t\t\t*data,\n\tu8\t\t\t\tdata_len\n)\n{\n\tu8\ti = 0;\n\tu16\tx_read_data_addr = 0;\n\n\todm_write_2byte(dm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE);\n\tx_read_data_addr = PHYDM_MEMORY_MAP_BUF_READ + mac_id * 32; /*@Ctrl Info: 32Bytes for each macid(n)*/\n\n\tif (x_read_data_addr < PHYDM_MEMORY_MAP_BUF_READ || x_read_data_addr > 0x8FFF) {\n\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t  \"x_read_data_addr(0x%x) is not correct!\\n\",\n\t\t\t  x_read_data_addr);\n\t\treturn;\n\t}\n\n\t/* Read data */\n\tfor (i = 0; i < data_len; i++)\n\t\t*(data + i) = odm_read_2byte(dm, x_read_data_addr + i);\n}\n#endif\n\nvoid hal_txbf_8814a_get_tx_rate(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY *entry;\n\tstruct ra_table *ra_tab = &dm->dm_ra_table;\n\tstruct cmn_sta_info *sta = NULL;\n\tu8 data_rate = 0xFF;\n\tu8 macid = 0;\n\n\tentry = &(beam_info->beamformee_entry[beam_info->beamformee_cur_idx]);\n\tmacid = (u8)entry->mac_id;\n\n\tsta = dm->phydm_sta_info[macid];\n\n\tif (is_sta_active(sta)) {\n\t\tdata_rate = (sta->ra_info.curr_tx_rate) & 0x7f; /*@Bit7 indicates SGI*/\n\t\tbeam_info->tx_bf_data_rate = data_rate;\n\t}\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] dm->tx_bf_data_rate = 0x%x\\n\", __func__,\n\t\t  beam_info->tx_bf_data_rate);\n}\n\nvoid hal_txbf_8814a_reset_tx_path(void *dm_void, u8 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n#if DEV_BUS_TYPE == RT_USB_INTERFACE\n\tstruct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY beamformee_entry;\n\tu8 nr_index = 0, tx_ss = 0;\n\n\tif (idx < BEAMFORMEE_ENTRY_NUM)\n\t\tbeamformee_entry = beamforming_info->beamformee_entry[idx];\n\telse\n\t\treturn;\n\n\tif (beamforming_info->last_usb_hub != (*dm->hub_usb_mode)) {\n\t\tnr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer);\n\n\t\tif (*dm->hub_usb_mode == 2) {\n\t\t\tif (dm->rf_type == RF_4T4R)\n\t\t\t\ttx_ss = 0xf;\n\t\t\telse if (dm->rf_type == RF_3T3R)\n\t\t\t\ttx_ss = 0xe;\n\t\t\telse\n\t\t\t\ttx_ss = 0x6;\n\t\t} else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/\n\t\t\ttx_ss = 0x6;\n\t\telse\n\t\t\ttx_ss = 0x6;\n\n\t\tif (tx_ss == 0xf) {\n\t\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f);\n\t\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0);\n\t\t} else if (tx_ss == 0xe) {\n\t\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e);\n\t\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0);\n\t\t} else if (tx_ss == 0x6) {\n\t\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936);\n\t\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360);\n\t\t}\n\n\t\tif (idx == 0) {\n\t\t\tswitch (nr_index) {\n\t\t\tcase 0:\n\t\t\t\tbreak;\n\n\t\t\tcase 1: /*Nsts = 2\tBC*/\n\t\t\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/\n\t\t\t\tbreak;\n\n\t\t\tcase 2: /*Nsts = 3\tBCD*/\n\t\t\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/\n\t\t\t\tbreak;\n\n\t\t\tdefault: /*nr>3, same as Case 3*/\n\t\t\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} else {\n\t\t\tswitch (nr_index) {\n\t\t\tcase 0:\n\t\t\t\tbreak;\n\n\t\t\tcase 1: /*Nsts = 2\tBC*/\n\t\t\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/\n\t\t\t\tbreak;\n\n\t\t\tcase 2: /*Nsts = 3\tBCD*/\n\t\t\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/\n\t\t\t\tbreak;\n\n\t\t\tdefault: /*nr>3, same as Case 3*/\n\t\t\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tbeamforming_info->last_usb_hub = *dm->hub_usb_mode;\n\t} else\n\t\treturn;\n#endif\n}\n\nu8 hal_txbf_8814a_get_ntx(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 ntx = 0, tx_ss = 3;\n\n#if DEV_BUS_TYPE == RT_USB_INTERFACE\n\ttx_ss = *dm->hub_usb_mode;\n#endif\n\tif (tx_ss == 3 || tx_ss == 2) {\n\t\tif (dm->rf_type == RF_4T4R)\n\t\t\tntx = 3;\n\t\telse if (dm->rf_type == RF_3T3R)\n\t\t\tntx = 2;\n\t\telse\n\t\t\tntx = 1;\n\t} else if (tx_ss == 1) /*USB 2.0 always 2Tx*/\n\t\tntx = 1;\n\telse\n\t\tntx = 1;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] ntx = %d\\n\", __func__, ntx);\n\treturn ntx;\n}\n\nu8 hal_txbf_8814a_get_nrx(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 nrx = 0;\n\n\tif (dm->rf_type == RF_4T4R)\n\t\tnrx = 3;\n\telse if (dm->rf_type == RF_3T3R)\n\t\tnrx = 2;\n\telse if (dm->rf_type == RF_2T2R)\n\t\tnrx = 1;\n\telse if (dm->rf_type == RF_2T3R)\n\t\tnrx = 2;\n\telse if (dm->rf_type == RF_2T4R)\n\t\tnrx = 3;\n\telse if (dm->rf_type == RF_1T1R)\n\t\tnrx = 0;\n\telse if (dm->rf_type == RF_1T2R)\n\t\tnrx = 1;\n\telse\n\t\tnrx = 0;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] nrx = %d\\n\", __func__, nrx);\n\treturn nrx;\n}\n\nvoid hal_txbf_8814a_rf_mode(void *dm_void,\n\t\t\t    struct _RT_BEAMFORMING_INFO *beamforming_info,\n\t\t\t    u8 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 nr_index = 0;\n\tu8 tx_ss = 3; /*@default use 3 Tx*/\n\tstruct _RT_BEAMFORMEE_ENTRY beamformee_entry;\n\n\tif (idx < BEAMFORMEE_ENTRY_NUM)\n\t\tbeamformee_entry = beamforming_info->beamformee_entry[idx];\n\telse\n\t\treturn;\n\n\tnr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer);\n\n\tif (dm->rf_type == RF_1T1R)\n\t\treturn;\n\n\tif (beamforming_info->beamformee_su_cnt > 0) {\n#if DEV_BUS_TYPE == RT_USB_INTERFACE\n\t\tbeamforming_info->last_usb_hub = *dm->hub_usb_mode;\n\t\ttx_ss = *dm->hub_usb_mode;\n#endif\n\t\tif (tx_ss == 3 || tx_ss == 2) {\n\t\t\tif (dm->rf_type == RF_4T4R)\n\t\t\t\ttx_ss = 0xf;\n\t\t\telse if (dm->rf_type == RF_3T3R)\n\t\t\t\ttx_ss = 0xe;\n\t\t\telse\n\t\t\t\ttx_ss = 0x6;\n\t\t} else if (tx_ss == 1) /*USB 2.0 always 2Tx*/\n\t\t\ttx_ss = 0x6;\n\t\telse\n\t\t\ttx_ss = 0x6;\n\n\t\tif (tx_ss == 0xf) {\n\t\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f);\n\t\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0);\n\t\t} else if (tx_ss == 0xe) {\n\t\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e);\n\t\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0);\n\t\t} else if (tx_ss == 0x6) {\n\t\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936);\n\t\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360);\n\t\t}\n\n\t\t/*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/\n\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/\n\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT30, 0x1); /*@if Nsts > Nc don't apply V matrix*/\n\n\t\tif (idx == 0) {\n\t\t\tswitch (nr_index) {\n\t\t\tcase 0:\n\t\t\t\tbreak;\n\n\t\t\tcase 1: /*Nsts = 2\tBC*/\n\t\t\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/\n\t\t\t\tbreak;\n\n\t\t\tcase 2: /*Nsts = 3\tBCD*/\n\t\t\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/\n\t\t\t\tbreak;\n\n\t\t\tdefault: /*nr>3, same as Case 3*/\n\t\t\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/\n\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} else {\n\t\t\tswitch (nr_index) {\n\t\t\tcase 0:\n\t\t\t\tbreak;\n\n\t\t\tcase 1: /*Nsts = 2\tBC*/\n\t\t\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/\n\t\t\t\tbreak;\n\n\t\t\tcase 2: /*Nsts = 3\tBCD*/\n\t\t\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/\n\t\t\t\tbreak;\n\n\t\t\tdefault: /*nr>3, same as Case 3*/\n\t\t\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (beamforming_info->beamformee_su_cnt == 0 && beamforming_info->beamformer_su_cnt == 0) {\n\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x932); /*set tx_path selection for 8814a BFer bug refine*/\n\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e9360);\n\t}\n}\n#if 0\nvoid\nhal_txbf_8814a_download_ndpa(\n\tvoid\t\t\t*dm_void,\n\tu8\t\t\t\tidx\n)\n{\n\tstruct dm_struct\t*dm = (struct dm_struct *)dm_void;\n\tu8\t\t\tu1b_tmp = 0, tmp_reg422 = 0;\n\tu8\t\t\tbcn_valid_reg = 0, count = 0, dl_bcn_count = 0;\n\tu16\t\t\thead_page = 0x7FE;\n\tboolean\t\t\tis_send_beacon = false;\n\tu16\t\t\ttx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*@default reseved 1 page for the IC type which is undefined.*/\n\tstruct _RT_BEAMFORMING_INFO\t*beam_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY\t*p_beam_entry = beam_info->beamformee_entry + idx;\n\tvoid\t\t*adapter = dm->adapter;\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t*dm->is_fw_dw_rsvd_page_in_progress = true;\n#endif\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tphydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy);\n\n\t/*Set REG_CR bit 8. DMA beacon by SW.*/\n\tu1b_tmp = odm_read_1byte(dm, REG_CR_8814A + 1);\n\todm_write_1byte(dm,  REG_CR_8814A + 1, (u1b_tmp | BIT(0)));\n\n\n\t/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/\n\ttmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2);\n\todm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2,  tmp_reg422 & (~BIT(6)));\n\n\tif (tmp_reg422 & BIT(6)) {\n\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t  \"%s: There is an adapter is sending beacon.\\n\",\n\t\t\t  __func__);\n\t\tis_send_beacon = true;\n\t}\n\n\t/*@0x204[11:0]\tBeacon Head for TXDMA*/\n\todm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, head_page);\n\n\tdo {\n\t\t/*@Clear beacon valid check bit.*/\n\t\tbcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1);\n\t\todm_write_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7)));\n\n\t\t/*@download NDPA rsvd page.*/\n\t\tif (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)\n\t\t\tbeamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE);\n\t\telse\n\t\t\tbeamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);\n\n\t\t/*@check rsvd page download OK.*/\n\t\tbcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1);\n\t\tcount = 0;\n\t\twhile (!(bcn_valid_reg & BIT(7)) && count < 20) {\n\t\t\tcount++;\n\t\t\tODM_delay_ms(10);\n\t\t\tbcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 2);\n\t\t}\n\t\tdl_bcn_count++;\n\t} while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5);\n\n\tif (!(bcn_valid_reg & BIT(7)))\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s Download RSVD page failed!\\n\",\n\t\t\t  __func__);\n\n\t/*@0x204[11:0]\tBeacon Head for TXDMA*/\n\todm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy);\n\n\t/*To make sure that if there exists an adapter which would like to send beacon.*/\n\t/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/\n\t/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */\n\t/*the beacon cannot be sent by HW.*/\n\t/*@2010.06.23. Added by tynli.*/\n\tif (is_send_beacon)\n\t\todm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422);\n\n\t/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/\n\t/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/\n\tu1b_tmp = odm_read_1byte(dm, REG_CR_8814A + 1);\n\todm_write_1byte(dm, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0))));\n\n\tp_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t*dm->is_fw_dw_rsvd_page_in_progress = false;\n#endif\n}\n\nvoid\nhal_txbf_8814a_fw_txbf_cmd(\n\tvoid\t\t\t*dm_void\n)\n{\n\tstruct dm_struct\t*dm = (struct dm_struct *)dm_void;\n\tu8\tidx, period = 0;\n\tu8\tPageNum0 = 0xFF, PageNum1 = 0xFF;\n\tu8\tu1_tx_bf_parm[3] = {0};\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\n\tfor (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {\n\t\tif (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {\n\t\t\tif (beam_info->beamformee_entry[idx].is_sound) {\n\t\t\t\tPageNum0 = 0xFE;\n\t\t\t\tPageNum1 = 0x07;\n\t\t\t\tperiod = (u8)(beam_info->beamformee_entry[idx].sound_period);\n\t\t\t} else if (PageNum0 == 0xFF) {\n\t\t\t\tPageNum0 = 0xFF; /*stop sounding*/\n\t\t\t\tPageNum1 = 0x0F;\n\t\t\t}\n\t\t}\n\t}\n\n\tu1_tx_bf_parm[0] = PageNum0;\n\tu1_tx_bf_parm[1] = PageNum1;\n\tu1_tx_bf_parm[2] = period;\n\todm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);\n\n\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t  \"[%s] PageNum0 = %d, PageNum1 = %d period = %d\\n\", __func__,\n\t\t  PageNum0, PageNum1, period);\n}\n#endif\nvoid hal_txbf_8814a_enter(void *dm_void, u8 bfer_bfee_idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i = 0;\n\tu8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;\n\tu8 bfee_idx = (bfer_bfee_idx & 0xF);\n\tstruct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY beamformee_entry;\n\tstruct _RT_BEAMFORMER_ENTRY beamformer_entry;\n\tu16 sta_id = 0, csi_param = 0;\n\tu8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] bfer_idx=%d, bfee_idx=%d\\n\", __func__,\n\t\t  bfer_idx, bfee_idx);\n\todm_set_mac_reg(dm, REG_SND_PTCL_CTRL_8814A, MASKBYTE1 | MASKBYTE2, 0x0202);\n\n\tif (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {\n\t\tbeamformer_entry = beamforming_info->beamformer_entry[bfer_idx];\n\t\t/*Sounding protocol control*/\n\t\todm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xDB);\n\n\t\t/*@MAC address/Partial AID of Beamformer*/\n\t\tif (bfer_idx == 0) {\n\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\todm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), beamformer_entry.mac_addr[i]);\n\t\t} else {\n\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\todm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), beamformer_entry.mac_addr[i]);\n\t\t}\n\n\t\t/*@CSI report parameters of Beamformer*/\n\t\tnc_index = hal_txbf_8814a_get_nrx(dm); /*@for 8814A nrx = 3(4 ant), min=0(1 ant)*/\n\t\tnr_index = beamformer_entry.num_of_sounding_dim; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/\n\n\t\tgrouping = 0;\n\n\t\t/*@for ac = 1, for n = 3*/\n\t\tif (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)\n\t\t\tcodebookinfo = 1;\n\t\telse if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT)\n\t\t\tcodebookinfo = 3;\n\n\t\tcoefficientsize = 3;\n\n\t\tcsi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index));\n\n\t\tif (bfer_idx == 0)\n\t\t\todm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, csi_param);\n\t\telse\n\t\t\todm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, csi_param);\n\t\t/*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/\n\t\todm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A + 3, 0x40);\n\t}\n\n\tif (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {\n\t\tbeamformee_entry = beamforming_info->beamformee_entry[bfee_idx];\n\n\t\thal_txbf_8814a_rf_mode(dm, beamforming_info, bfee_idx);\n\n\t\tif (phydm_acting_determine(dm, phydm_acting_as_ibss))\n\t\t\tsta_id = beamformee_entry.mac_id;\n\t\telse\n\t\t\tsta_id = beamformee_entry.p_aid;\n\n\t\t/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/\n\t\tif (bfee_idx == 0) {\n\t\t\todm_write_2byte(dm, REG_TXBF_CTRL_8814A, sta_id);\n\t\t\todm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7));\n\t\t} else\n\t\t\todm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, sta_id | BIT(14) | BIT(15) | BIT(12));\n\n\t\t/*@CSI report parameters of Beamformee*/\n\t\tif (bfee_idx == 0) {\n\t\t\t/*@Get BIT24 & BIT25*/\n\t\t\tu8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3;\n\n\t\t\todm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60);\n\t\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, sta_id | BIT(9));\n\t\t} else\n\t\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT25*/\n\n\t\tphydm_beamforming_notify(dm);\n\t}\n}\n\nvoid hal_txbf_8814a_leave(void *dm_void, u8 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMER_ENTRY beamformer_entry;\n\tstruct _RT_BEAMFORMEE_ENTRY beamformee_entry;\n\n\tif (idx < BEAMFORMER_ENTRY_NUM) {\n\t\tbeamformer_entry = beamforming_info->beamformer_entry[idx];\n\t\tbeamformee_entry = beamforming_info->beamformee_entry[idx];\n\t} else\n\t\treturn;\n\n\t/*@Clear P_AID of Beamformee*/\n\t/*@Clear MAC address of Beamformer*/\n\t/*@Clear Associated Bfmee Sel*/\n\n\tif (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {\n\t\todm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xD8);\n\t\tif (idx == 0) {\n\t\t\todm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0);\n\t\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0);\n\t\t\todm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, 0);\n\t\t} else {\n\t\t\todm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0);\n\t\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0);\n\t\t\todm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0);\n\t\t}\n\t}\n\n\tif (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {\n\t\thal_txbf_8814a_rf_mode(dm, beamforming_info, idx);\n\t\tif (idx == 0) {\n\t\t\todm_write_2byte(dm, REG_TXBF_CTRL_8814A, 0x0);\n\t\t\todm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7));\n\t\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0);\n\t\t} else {\n\t\t\todm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT(14) | BIT(15) | BIT(12));\n\n\t\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60);\n\t\t}\n\t}\n}\n\nvoid hal_txbf_8814a_status(void *dm_void, u8 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu16 beam_ctrl_val, tmp_val;\n\tu32 beam_ctrl_reg;\n\tstruct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY beamform_entry;\n\n\tif (idx < BEAMFORMEE_ENTRY_NUM)\n\t\tbeamform_entry = beamforming_info->beamformee_entry[idx];\n\telse\n\t\treturn;\n\n\tif (phydm_acting_determine(dm, phydm_acting_as_ibss))\n\t\tbeam_ctrl_val = beamform_entry.mac_id;\n\telse\n\t\tbeam_ctrl_val = beamform_entry.p_aid;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"@%s, beamform_entry.beamform_entry_state = %d\",\n\t\t  __func__, beamform_entry.beamform_entry_state);\n\n\tif (idx == 0)\n\t\tbeam_ctrl_reg = REG_TXBF_CTRL_8814A;\n\telse {\n\t\tbeam_ctrl_reg = REG_TXBF_CTRL_8814A + 2;\n\t\tbeam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);\n\t}\n\n\tif (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beamforming_info->apply_v_matrix == true) {\n\t\tif (beamform_entry.sound_bw == CHANNEL_WIDTH_20)\n\t\t\tbeam_ctrl_val |= BIT(9);\n\t\telse if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)\n\t\t\tbeam_ctrl_val |= (BIT(9) | BIT(10));\n\t\telse if (beamform_entry.sound_bw == CHANNEL_WIDTH_80)\n\t\t\tbeam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"@%s, Don't apply Vmatrix\", __func__);\n\t\tbeam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));\n\t}\n\n\todm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);\n\t/*@disable NDP packet use beamforming */\n\ttmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8814A);\n\todm_write_2byte(dm, REG_TXBF_CTRL_8814A, tmp_val | BIT(15));\n}\n\nvoid hal_txbf_8814a_fw_txbf(void *dm_void, u8 idx)\n{\n#if 0\n\tstruct dm_struct\t*dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO\t*beam_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY\t*p_beam_entry = beam_info->beamformee_entry + idx;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tif (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)\n\t\thal_txbf_8814a_download_ndpa(dm, idx);\n\n\thal_txbf_8814a_fw_txbf_cmd(dm);\n#endif\n}\n\n#endif /* @(RTL8814A_SUPPORT == 1)*/\n\n#endif\n"
  },
  {
    "path": "hal/phydm/txbf/haltxbf8814a.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#ifndef __HAL_TXBF_8814A_H__\n#define __HAL_TXBF_8814A_H__\n\n#if (RTL8814A_SUPPORT == 1)\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\nboolean\nphydm_beamforming_set_iqgen_8814A(void *dm_void);\n\nvoid hal_txbf_8814a_set_ndpa_rate(void *dm_void, u8 BW, u8 rate);\n\nu8 hal_txbf_8814a_get_ntx(void *dm_void);\n\nvoid hal_txbf_8814a_enter(void *dm_void, u8 idx);\n\nvoid hal_txbf_8814a_leave(void *dm_void, u8 idx);\n\nvoid hal_txbf_8814a_status(void *dm_void, u8 idx);\n\nvoid hal_txbf_8814a_reset_tx_path(void *dm_void, u8 idx);\n\nvoid hal_txbf_8814a_get_tx_rate(void *dm_void);\n\nvoid hal_txbf_8814a_fw_txbf(void *dm_void, u8 idx);\n\n#else\n\n#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate)\n#define hal_txbf_8814a_get_ntx(dm_void) 0\n#define hal_txbf_8814a_enter(dm_void, idx)\n#define hal_txbf_8814a_leave(dm_void, idx)\n#define hal_txbf_8814a_status(dm_void, idx)\n#define hal_txbf_8814a_reset_tx_path(dm_void, idx)\n#define hal_txbf_8814a_get_tx_rate(dm_void)\n#define hal_txbf_8814a_fw_txbf(dm_void, idx)\n#define phydm_beamforming_set_iqgen_8814A(dm_void) 0\n\n#endif\n\n#else\n\n#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate)\n#define hal_txbf_8814a_get_ntx(dm_void) 0\n#define hal_txbf_8814a_enter(dm_void, idx)\n#define hal_txbf_8814a_leave(dm_void, idx)\n#define hal_txbf_8814a_status(dm_void, idx)\n#define hal_txbf_8814a_reset_tx_path(dm_void, idx)\n#define hal_txbf_8814a_get_tx_rate(dm_void)\n#define hal_txbf_8814a_fw_txbf(dm_void, idx)\n#define phydm_beamforming_set_iqgen_8814A(dm_void) 0\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/phydm/txbf/haltxbf8822b.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n/*@============================================================*/\n/* @Description:                                              */\n/*                                                           @*/\n/* This file is for 8814A TXBF mechanism                     */\n/*                                                           @*/\n/*@============================================================*/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#if (RTL8822B_SUPPORT == 1)\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\nu8 hal_txbf_8822b_get_ntx(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 ntx = 0;\n\n#if DEV_BUS_TYPE == RT_USB_INTERFACE\n\tif (dm->support_interface == ODM_ITRF_USB) {\n\t\tif (*dm->hub_usb_mode == 2) { /*USB3.0*/\n\t\t\tif (dm->rf_type == RF_4T4R)\n\t\t\t\tntx = 3;\n\t\t\telse if (dm->rf_type == RF_3T3R)\n\t\t\t\tntx = 2;\n\t\t\telse\n\t\t\t\tntx = 1;\n\t\t} else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/\n\t\t\tntx = 1;\n\t\telse\n\t\t\tntx = 1;\n\t} else\n#endif\n\t{\n\t\tif (dm->rf_type == RF_4T4R)\n\t\t\tntx = 3;\n\t\telse if (dm->rf_type == RF_3T3R)\n\t\t\tntx = 2;\n\t\telse\n\t\t\tntx = 1;\n\t}\n\n\treturn ntx;\n}\n\nu8 hal_txbf_8822b_get_nrx(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 nrx = 0;\n\n\tif (dm->rf_type == RF_4T4R)\n\t\tnrx = 3;\n\telse if (dm->rf_type == RF_3T3R)\n\t\tnrx = 2;\n\telse if (dm->rf_type == RF_2T2R)\n\t\tnrx = 1;\n\telse if (dm->rf_type == RF_2T3R)\n\t\tnrx = 2;\n\telse if (dm->rf_type == RF_2T4R)\n\t\tnrx = 3;\n\telse if (dm->rf_type == RF_1T1R)\n\t\tnrx = 0;\n\telse if (dm->rf_type == RF_1T2R)\n\t\tnrx = 1;\n\telse\n\t\tnrx = 0;\n\n\treturn nrx;\n}\n\n/***************SU & MU BFee Entry********************/\nvoid hal_txbf_8822b_rf_mode(\n\tvoid *dm_void,\n\tstruct _RT_BEAMFORMING_INFO *beamforming_info,\n\tu8 idx)\n{\n#if 0\n\tstruct dm_struct\t*dm = (struct dm_struct *)dm_void;\n\tu8\t\t\t\ti, nr_index = 0;\n\tboolean\t\t\t\tis_self_beamformer = false;\n\tboolean\t\t\t\tis_self_beamformee = false;\n\tstruct _RT_BEAMFORMEE_ENTRY\tbeamformee_entry;\n\n\tif (idx < BEAMFORMEE_ENTRY_NUM)\n\t\tbeamformee_entry = beamforming_info->beamformee_entry[idx];\n\telse\n\t\treturn;\n\n\tif (dm->rf_type == RF_1T1R)\n\t\treturn;\n\n\tfor (i = RF_PATH_A; i < RF_PATH_B; i++) {\n\t\todm_set_rf_reg(dm, (enum rf_path)i, rf_welut_jaguar, 0x80000, 0x1);\n\t\t/*RF mode table write enable*/\n\t}\n\n\tif (beamforming_info->beamformee_su_cnt > 0 || beamforming_info->beamformee_mu_cnt > 0) {\n\t\tfor (i = RF_PATH_A; i < RF_PATH_B; i++) {\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_addr, 0xfffff, 0x18000);\n\t\t\t/*Select RX mode*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_data0, 0xfffff, 0xBE77F);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_data1, 0xfffff, 0x226BF);\n\t\t\t/*@Enable TXIQGEN in RX mode*/\n\t\t}\n\t\todm_set_rf_reg(dm, RF_PATH_A, rf_mode_table_data1, 0xfffff, 0xE26BF);\n\t\t/*@Enable TXIQGEN in RX mode*/\n\t}\n\n\tfor (i = RF_PATH_A; i < RF_PATH_B; i++) {\n\t\todm_set_rf_reg(dm, (enum rf_path)i, rf_welut_jaguar, 0x80000, 0x0);\n\t\t/*RF mode table write disable*/\n\t}\n\n\tif (beamforming_info->beamformee_su_cnt > 0) {\n\t\t/*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/\n\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2);\t\t\t/*@enable BB TxBF ant mapping register*/\n\n\t\tif (idx == 0) {\n\t\t\t/*Nsts = 2\tAB*/\n\t\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8822B, 0xffff, 0x0433);\n\t\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);\n\t\t\t/*odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430);*/\n\n\t\t} else {/*@IDX =1*/\n\t\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433);\n\t\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);\n\t\t\t/*odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430;*/\n\t\t}\n\t} else {\n\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*@1SS by path-A*/\n\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*@2SS by path-A,B*/\n\t}\n\n\tif (beamforming_info->beamformee_mu_cnt > 0) {\n\t\t/*@MU STAs share the common setting*/\n\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1);\n\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433);\n\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);\n\t}\n#endif\n}\n#if 0\nvoid\nhal_txbf_8822b_download_ndpa(\n\tvoid\t\t\t*adapter,\n\tu8\t\t\t\tidx\n)\n{\n\tu8\t\t\tu1b_tmp = 0, tmp_reg422 = 0;\n\tu8\t\t\tbcn_valid_reg = 0, count = 0, dl_bcn_count = 0;\n\tu16\t\t\thead_page = 0x7FE;\n\tboolean\t\t\tis_send_beacon = false;\n\tHAL_DATA_TYPE\t*hal_data = GET_HAL_DATA(adapter);\n\tu16\t\t\ttx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*@default reseved 1 page for the IC type which is undefined.*/\n\tstruct _RT_BEAMFORMING_INFO\t*beam_info = GET_BEAMFORM_INFO(adapter);\n\tstruct _RT_BEAMFORMEE_ENTRY\t*p_beam_entry = beam_info->beamformee_entry + idx;\n\n\thal_data->is_fw_dw_rsvd_page_in_progress = true;\n\tphydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy);\n\n\t/*Set REG_CR bit 8. DMA beacon by SW.*/\n\tu1b_tmp = platform_efio_read_1byte(adapter, REG_CR_8814A + 1);\n\tplatform_efio_write_1byte(adapter,  REG_CR_8814A + 1, (u1b_tmp | BIT(0)));\n\n\n\t/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/\n\ttmp_reg422 = platform_efio_read_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2);\n\tplatform_efio_write_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2,  tmp_reg422 & (~BIT(6)));\n\n\tif (tmp_reg422 & BIT(6)) {\n\t\tRT_TRACE(COMP_INIT, DBG_LOUD, (\"SetBeamformDownloadNDPA_8814A(): There is an adapter is sending beacon.\\n\"));\n\t\tis_send_beacon = true;\n\t}\n\n\t/*@0x204[11:0]\tBeacon Head for TXDMA*/\n\tplatform_efio_write_2byte(adapter, REG_FIFOPAGE_CTRL_2_8814A, head_page);\n\n\tdo {\n\t\t/*@Clear beacon valid check bit.*/\n\t\tbcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1);\n\t\tplatform_efio_write_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7)));\n\n\t\t/*@download NDPA rsvd page.*/\n\t\tif (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)\n\t\t\tbeamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE);\n\t\telse\n\t\t\tbeamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);\n\n\t\t/*@check rsvd page download OK.*/\n\t\tbcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1);\n\t\tcount = 0;\n\t\twhile (!(bcn_valid_reg & BIT(7)) && count < 20) {\n\t\t\tcount++;\n\t\t\tdelay_us(10);\n\t\t\tbcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 2);\n\t\t}\n\t\tdl_bcn_count++;\n\t} while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5);\n\n\tif (!(bcn_valid_reg & BIT(0)))\n\t\tRT_DISP(FBEAM, FBEAM_ERROR, (\"%s Download RSVD page failed!\\n\", __func__));\n\n\t/*@0x204[11:0]\tBeacon Head for TXDMA*/\n\tplatform_efio_write_2byte(adapter, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy);\n\n\t/*To make sure that if there exists an adapter which would like to send beacon.*/\n\t/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/\n\t/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */\n\t/*the beacon cannot be sent by HW.*/\n\t/*@2010.06.23. Added by tynli.*/\n\tif (is_send_beacon)\n\t\tplatform_efio_write_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422);\n\n\t/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/\n\t/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/\n\tu1b_tmp = platform_efio_read_1byte(adapter, REG_CR_8814A + 1);\n\tplatform_efio_write_1byte(adapter, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0))));\n\n\tp_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;\n\n\thal_data->is_fw_dw_rsvd_page_in_progress = false;\n}\n\nvoid\nhal_txbf_8822b_fw_txbf_cmd(\n\tvoid\t*adapter\n)\n{\n\tu8\tidx, period = 0;\n\tu8\tPageNum0 = 0xFF, PageNum1 = 0xFF;\n\tu8\tu1_tx_bf_parm[3] = {0};\n\n\tPMGNT_INFO\t\t\t\tmgnt_info = &(adapter->MgntInfo);\n\tstruct _RT_BEAMFORMING_INFO\t*beam_info = GET_BEAMFORM_INFO(adapter);\n\n\tfor (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {\n\t\tif (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {\n\t\t\tif (beam_info->beamformee_entry[idx].is_sound) {\n\t\t\t\tPageNum0 = 0xFE;\n\t\t\t\tPageNum1 = 0x07;\n\t\t\t\tperiod = (u8)(beam_info->beamformee_entry[idx].sound_period);\n\t\t\t} else if (PageNum0 == 0xFF) {\n\t\t\t\tPageNum0 = 0xFF; /*stop sounding*/\n\t\t\t\tPageNum1 = 0x0F;\n\t\t\t}\n\t\t}\n\t}\n\n\tu1_tx_bf_parm[0] = PageNum0;\n\tu1_tx_bf_parm[1] = PageNum1;\n\tu1_tx_bf_parm[2] = period;\n\tfill_h2c_cmd(adapter, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);\n\n\tRT_DISP(FBEAM, FBEAM_FUN, (\"@%s End, PageNum0 = 0x%x, PageNum1 = 0x%x period = %d\", __func__, PageNum0, PageNum1, period));\n}\n#endif\n\n#if 0\nvoid\nhal_txbf_8822b_init(\n\tvoid\t\t\t*dm_void\n)\n{\n\tstruct dm_struct\t*dm = (struct dm_struct *)dm_void;\n\tu8\t\tu1b_tmp;\n\tstruct _RT_BEAMFORMING_INFO\t\t*beamforming_info = &dm->beamforming_info;\n\tvoid\t\t\t\t*adapter = dm->adapter;\n\n\todm_set_bb_reg(dm, R_0x14c0, BIT(16), 1); /*@Enable P1 aggr new packet according to P0 transfer time*/\n\todm_set_bb_reg(dm, R_0x14c0, BIT(15) | BIT14 | BIT13 | BIT12, 10); /*@MU Retry Limit*/\n\todm_set_bb_reg(dm, R_0x14c0, BIT(7), 0); /*@Disable Tx MU-MIMO until sounding done*/\n\todm_set_bb_reg(dm, R_0x14c0, 0x3F, 0); /* @Clear validity of MU STAs */\n\todm_write_1byte(dm, 0x167c, 0x70); /*@MU-MIMO Option as default value*/\n\todm_write_2byte(dm, 0x1680, 0); /*@MU-MIMO Control as default value*/\n\n\t/* Set MU NDPA rate & BW source */\n\t/* @0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */\n\tu1b_tmp = odm_read_1byte(dm, 0x42C);\n\todm_write_1byte(dm, REG_TXBF_CTRL_8822B, (u1b_tmp | BIT(6)));\n\t/* @0x45F[7:0] = 0x10 (rate=OFDM_6M, BW20) */\n\todm_write_1byte(dm, REG_NDPA_OPT_CTRL_8822B, 0x10);\n\n\t/*Temp Settings*/\n\todm_set_bb_reg(dm, R_0x6dc, 0x3F000000, 4); /*STA2's CSI rate is fixed at 6M*/\n\todm_set_bb_reg(dm, R_0x1c94, MASKDWORD, 0xAFFFAFFF); /*@Grouping bitmap parameters*/\n\n\t/* @Init HW variable */\n\tbeamforming_info->reg_mu_tx_ctrl = odm_read_4byte(dm, 0x14c0);\n\n\tif (dm->rf_type == RF_2T2R) { /*@2T2R*/\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s: rf_type is 2T2R\\n\", __func__);\n\t\tconfig_phydm_trx_mode_8822b(dm, (enum bb_path)3, (enum bb_path)3, true);/*Tx2path*/\n\t}\n\n#if (OMNIPEEK_SNIFFER_ENABLED == 1)\n\t/* @Config HW to receive packet on the user position from registry for sniffer mode. */\n\t/* odm_set_bb_reg(dm, R_0xb00, BIT(9), 1);*/ /* For A-cut only. RegB00[9] = 1 (enable PMAC Rx) */\n\todm_set_bb_reg(dm, R_0xb54, BIT(30), 1); /* RegB54[30] = 1 (force user position) */\n\todm_set_bb_reg(dm, R_0xb54, (BIT(29) | BIT28), adapter->MgntInfo.sniff_user_position); /* RegB54[29:28] = user position (0~3) */\n\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t  \"Set adapter->MgntInfo.sniff_user_position=%#X\\n\",\n\t\t  adapter->MgntInfo.sniff_user_position);\n#endif\n}\n#endif\n\nvoid hal_txbf_8822b_enter(\n\tvoid *dm_void,\n\tu8 bfer_bfee_idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i = 0;\n\tu8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;\n\tu8 bfee_idx = (bfer_bfee_idx & 0xF);\n\tu16 csi_param = 0;\n\tstruct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry;\n\tstruct _RT_BEAMFORMER_ENTRY *beamformer_entry;\n\tu16 value16, sta_id = 0;\n\tu8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;\n\tu32 gid_valid, user_position_l, user_position_h;\n\tu32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e};\n\tu8 u1b_tmp;\n\tu32 u4b_tmp;\n\n\tRT_DISP(FBEAM, FBEAM_FUN, (\"%s: bfer_bfee_idx=%d, bfer_idx=%d, bfee_idx=%d\\n\", __func__, bfer_bfee_idx, bfer_idx, bfee_idx));\n\n\t/*************SU BFer Entry Init*************/\n\tif (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {\n\t\tbeamformer_entry = &beamforming_info->beamformer_entry[bfer_idx];\n\t\tbeamformer_entry->is_mu_ap = false;\n\t\t/*Sounding protocol control*/\n\t\todm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB);\n\n\t\tfor (i = 0; i < MAX_BEAMFORMER_SU; i++) {\n\t\t\tif ((beamforming_info->beamformer_su_reg_maping & BIT(i)) == 0) {\n\t\t\t\tbeamforming_info->beamformer_su_reg_maping |= BIT(i);\n\t\t\t\tbeamformer_entry->su_reg_index = i;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\t/*@MAC address/Partial AID of Beamformer*/\n\t\tif (beamformer_entry->su_reg_index == 0) {\n\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\todm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), beamformer_entry->mac_addr[i]);\n\t\t} else {\n\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\todm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8822B + i), beamformer_entry->mac_addr[i]);\n\t\t}\n\n\t\t/*@CSI report parameters of Beamformer*/\n\t\tnc_index = hal_txbf_8822b_get_nrx(dm); /*@for 8814A nrx = 3(4 ant), min=0(1 ant)*/\n\t\tnr_index = beamformer_entry->num_of_sounding_dim; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/\n\n\t\tgrouping = 0;\n\n\t\t/*@for ac = 1, for n = 3*/\n\t\tif (beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)\n\t\t\tcodebookinfo = 1;\n\t\telse if (beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT)\n\t\t\tcodebookinfo = 3;\n\n\t\tcoefficientsize = 3;\n\n\t\tcsi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index));\n\n\t\tif (bfer_idx == 0)\n\t\t\todm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B, csi_param);\n\t\telse\n\t\t\todm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, csi_param);\n\t\t/*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/\n\t\todm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B + 3, 0x70);\n\t}\n\n\t/*************SU BFee Entry Init*************/\n\tif (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {\n\t\tp_beamformee_entry = &beamforming_info->beamformee_entry[bfee_idx];\n\t\tp_beamformee_entry->is_mu_sta = false;\n\t\thal_txbf_8822b_rf_mode(dm, beamforming_info, bfee_idx);\n\n\t\tif (phydm_acting_determine(dm, phydm_acting_as_ibss))\n\t\t\tsta_id = p_beamformee_entry->mac_id;\n\t\telse\n\t\t\tsta_id = p_beamformee_entry->p_aid;\n\n\t\tfor (i = 0; i < MAX_BEAMFORMEE_SU; i++) {\n\t\t\tif ((beamforming_info->beamformee_su_reg_maping & BIT(i)) == 0) {\n\t\t\t\tbeamforming_info->beamformee_su_reg_maping |= BIT(i);\n\t\t\t\tp_beamformee_entry->su_reg_index = i;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\t/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/\n\t\tif (p_beamformee_entry->su_reg_index == 0) {\n\t\t\todm_write_2byte(dm, REG_TXBF_CTRL_8822B, sta_id);\n\t\t\todm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7));\n\t\t} else\n\t\t\todm_write_2byte(dm, REG_TXBF_CTRL_8822B + 2, sta_id | BIT(14) | BIT(15) | BIT(12));\n\n\t\t/*@CSI report parameters of Beamformee*/\n\t\tif (p_beamformee_entry->su_reg_index == 0) {\n\t\t\t/*@Get BIT24 & BIT25*/\n\t\t\tu8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3) & 0x3;\n\n\t\t\todm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3, tmp | 0x60);\n\t\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B, sta_id | BIT(9));\n\t\t} else\n\t\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, sta_id | 0xE200); /*Set BIT25*/\n\n\t\tphydm_beamforming_notify(dm);\n\t}\n\n\t/*************MU BFer Entry Init*************/\n\tif (beamforming_info->beamformer_mu_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {\n\t\tbeamformer_entry = &beamforming_info->beamformer_entry[bfer_idx];\n\t\tbeamforming_info->mu_ap_index = bfer_idx;\n\t\tbeamformer_entry->is_mu_ap = true;\n\t\tfor (i = 0; i < 8; i++)\n\t\t\tbeamformer_entry->gid_valid[i] = 0;\n\t\tfor (i = 0; i < 16; i++)\n\t\t\tbeamformer_entry->user_position[i] = 0;\n\n\t\t/*Sounding protocol control*/\n\t\todm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB);\n\n\t\t/* @MAC address */\n\t\tfor (i = 0; i < 6; i++)\n\t\t\todm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), beamformer_entry->mac_addr[i]);\n\n\t\t/* Set partial AID */\n\t\todm_write_2byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + 6), beamformer_entry->p_aid);\n\n\t\t/* @Fill our AID to 0x1680[11:0] and [13:12] = 2b'00, BF report segment select to 3895 bytes*/\n\t\tu1b_tmp = odm_read_1byte(dm, 0x1680);\n\t\tu1b_tmp = (beamformer_entry->p_aid) & 0xFFF;\n\t\todm_write_1byte(dm, 0x1680, u1b_tmp);\n\n\t\t/* Set 80us for leaving ndp_rx_standby_state */\n\t\todm_write_1byte(dm, 0x71B, 0x50);\n\n\t\t/* Set 0x6A0[14] = 1 to accept action_no_ack */\n\t\tu1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP0_8822B + 1);\n\t\tu1b_tmp |= 0x40;\n\t\todm_write_1byte(dm, REG_RXFLTMAP0_8822B + 1, u1b_tmp);\n\t\t/* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */\n\t\tu1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP1_8822B);\n\t\tu1b_tmp |= 0x30;\n\t\todm_write_1byte(dm, REG_RXFLTMAP1_8822B, u1b_tmp);\n\n\t\t/*@CSI report parameters of Beamformer*/\n\t\tnc_index = hal_txbf_8822b_get_nrx(dm); /* @Depend on RF type */\n\t\tnr_index = 1; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/\n\t\tgrouping = 0; /*no grouping*/\n\t\tcodebookinfo = 1; /*@7 bit for psi, 9 bit for phi*/\n\t\tcoefficientsize = 0; /*This is nothing really matter*/\n\t\tcsi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index));\n\t\todm_write_2byte(dm, 0x6F4, csi_param);\n\n\t\t/*@for B-cut*/\n\t\todm_set_bb_reg(dm, R_0x6a0, BIT(20), 0);\n\t\todm_set_bb_reg(dm, R_0x688, BIT(20), 0);\n\t}\n\n\t/*************MU BFee Entry Init*************/\n\tif (beamforming_info->beamformee_mu_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {\n\t\tp_beamformee_entry = &beamforming_info->beamformee_entry[bfee_idx];\n\t\tp_beamformee_entry->is_mu_sta = true;\n\t\tfor (i = 0; i < MAX_BEAMFORMEE_MU; i++) {\n\t\t\tif ((beamforming_info->beamformee_mu_reg_maping & BIT(i)) == 0) {\n\t\t\t\tbeamforming_info->beamformee_mu_reg_maping |= BIT(i);\n\t\t\t\tp_beamformee_entry->mu_reg_index = i;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tif (p_beamformee_entry->mu_reg_index == 0xFF) {\n\t\t\t/* There is no valid bit in beamformee_mu_reg_maping */\n\t\t\tRT_DISP(FBEAM, FBEAM_FUN, (\"%s: ERROR! There is no valid bit in beamformee_mu_reg_maping!\\n\", __func__));\n\t\t\treturn;\n\t\t}\n\n\t\t/*User position table*/\n\t\tswitch (p_beamformee_entry->mu_reg_index) {\n\t\tcase 0:\n\t\t\tgid_valid = 0x7fe;\n\t\t\tuser_position_l = 0x111110;\n\t\t\tuser_position_h = 0x0;\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tgid_valid = 0x7f806;\n\t\t\tuser_position_l = 0x11000004;\n\t\t\tuser_position_h = 0x11;\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tgid_valid = 0x1f81818;\n\t\t\tuser_position_l = 0x400040;\n\t\t\tuser_position_h = 0x11100;\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\tgid_valid = 0x1e186060;\n\t\t\tuser_position_l = 0x4000400;\n\t\t\tuser_position_h = 0x1100040;\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\tgid_valid = 0x66618180;\n\t\t\tuser_position_l = 0x40004000;\n\t\t\tuser_position_h = 0x10040400;\n\t\t\tbreak;\n\t\tcase 5:\n\t\t\tgid_valid = 0x79860600;\n\t\t\tuser_position_l = 0x40000;\n\t\t\tuser_position_h = 0x4404004;\n\t\t\tbreak;\n\t\t}\n\n\t\tfor (i = 0; i < 8; i++) {\n\t\t\tif (i < 4) {\n\t\t\t\tp_beamformee_entry->gid_valid[i] = (u8)(gid_valid & 0xFF);\n\t\t\t\tgid_valid = (gid_valid >> 8);\n\t\t\t} else\n\t\t\t\tp_beamformee_entry->gid_valid[i] = 0;\n\t\t}\n\t\tfor (i = 0; i < 16; i++) {\n\t\t\tif (i < 4)\n\t\t\t\tp_beamformee_entry->user_position[i] = (u8)((user_position_l >> (i * 8)) & 0xFF);\n\t\t\telse if (i < 8)\n\t\t\t\tp_beamformee_entry->user_position[i] = (u8)((user_position_h >> ((i - 4) * 8)) & 0xFF);\n\t\t\telse\n\t\t\t\tp_beamformee_entry->user_position[i] = 0;\n\t\t}\n\n\t\t/*Sounding protocol control*/\n\t\todm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB);\n\n\t\t/*select MU STA table*/\n\t\tbeamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));\n\t\tbeamforming_info->reg_mu_tx_ctrl |= (p_beamformee_entry->mu_reg_index << 8) & (BIT(8) | BIT(9) | BIT(10));\n\t\todm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);\n\n\t\todm_set_bb_reg(dm, R_0x14c4, MASKDWORD, 0); /*Reset gid_valid table*/\n\t\todm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l);\n\t\todm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h);\n\n\t\t/*set validity of MU STAs*/\n\t\tbeamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0;\n\t\tbeamforming_info->reg_mu_tx_ctrl |= beamforming_info->beamformee_mu_reg_maping & 0x3F;\n\t\todm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);\n\n\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t  \"@%s, reg_mu_tx_ctrl = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\\n\",\n\t\t\t  __func__, beamforming_info->reg_mu_tx_ctrl,\n\t\t\t  user_position_l, user_position_h);\n\n\t\tvalue16 = odm_read_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index]);\n\t\tvalue16 &= 0xFE00; /*@Clear PAID*/\n\t\tvalue16 |= BIT(9); /*@Enable MU BFee*/\n\t\tvalue16 |= p_beamformee_entry->p_aid;\n\t\todm_write_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index], value16);\n\n\t\t/* @0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */\n\t\tu1b_tmp = odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3);\n\t\tu1b_tmp |= 0xD0; /* Set bit 28, 30, 31 to 3b'111*/\n\t\todm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, u1b_tmp);\n\t\t/* Set NDPA to 6M*/\n\t\todm_write_1byte(dm, REG_NDPA_RATE_8822B, 0x4);\n\n\t\tu1b_tmp = odm_read_1byte(dm, REG_NDPA_OPT_CTRL_8822B);\n\t\tu1b_tmp &= 0xFC; /* @Clear bit 0, 1*/\n\t\todm_write_1byte(dm, REG_NDPA_OPT_CTRL_8822B, u1b_tmp);\n\n\t\tu4b_tmp = odm_read_4byte(dm, REG_SND_PTCL_CTRL_8822B);\n\t\tu4b_tmp = ((u4b_tmp & 0xFF0000FF) | 0x020200); /* Set [23:8] to 0x0202*/\n\t\todm_write_4byte(dm, REG_SND_PTCL_CTRL_8822B, u4b_tmp);\n\n\t\t/* Set 0x6A0[14] = 1 to accept action_no_ack */\n\t\tu1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP0_8822B + 1);\n\t\tu1b_tmp |= 0x40;\n\t\todm_write_1byte(dm, REG_RXFLTMAP0_8822B + 1, u1b_tmp);\n\t\t/* @End of MAC registers setting */\n\n\t\thal_txbf_8822b_rf_mode(dm, beamforming_info, bfee_idx);\n#if (SUPPORT_MU_BF == 1)\n\t\t/*Special for plugfest*/\n\t\tdelay_ms(50); /* wait for 4-way handshake ending*/\n\t\tsend_sw_vht_gid_mgnt_frame(dm, p_beamformee_entry->mac_addr, bfee_idx);\n#endif\n\n\t\tphydm_beamforming_notify(dm);\n#if 1\n\t\t{\n\t\t\tu32 ctrl_info_offset, index;\n\t\t\t/*Set Ctrl Info*/\n\t\t\todm_write_2byte(dm, 0x140, 0x660);\n\t\t\tctrl_info_offset = 0x8000 + 32 * p_beamformee_entry->mac_id;\n\t\t\t/*Reset Ctrl Info*/\n\t\t\tfor (index = 0; index < 8; index++)\n\t\t\t\todm_write_4byte(dm, ctrl_info_offset + index * 4, 0);\n\n\t\t\todm_write_4byte(dm, ctrl_info_offset, (p_beamformee_entry->mu_reg_index + 1) << 16);\n\t\t\todm_write_1byte(dm, 0x81, 0x80); /*RPTBUF ready*/\n\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"@%s, mac_id = %d, ctrl_info_offset = 0x%x, mu_reg_index = %x\\n\",\n\t\t\t\t  __func__, p_beamformee_entry->mac_id,\n\t\t\t\t  ctrl_info_offset,\n\t\t\t\t  p_beamformee_entry->mu_reg_index);\n\t\t}\n#endif\n\t}\n}\n\nvoid hal_txbf_8822b_leave(\n\tvoid *dm_void,\n\tu8 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMER_ENTRY *beamformer_entry;\n\tstruct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry;\n\tu32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e};\n\n\tif (idx < BEAMFORMER_ENTRY_NUM) {\n\t\tbeamformer_entry = &beamforming_info->beamformer_entry[idx];\n\t\tp_beamformee_entry = &beamforming_info->beamformee_entry[idx];\n\t} else\n\t\treturn;\n\n\t/*@Clear P_AID of Beamformee*/\n\t/*@Clear MAC address of Beamformer*/\n\t/*@Clear Associated Bfmee Sel*/\n\n\tif (beamformer_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) {\n\t\todm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xD8);\n\t\tif (beamformer_entry->is_mu_ap == 0) { /*SU BFer */\n\t\t\tif (beamformer_entry->su_reg_index == 0) {\n\t\t\t\todm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8822B, 0);\n\t\t\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8822B + 4, 0);\n\t\t\t\todm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B, 0);\n\t\t\t} else {\n\t\t\t\todm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8822B, 0);\n\t\t\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8822B + 4, 0);\n\t\t\t\todm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, 0);\n\t\t\t}\n\t\t\tbeamforming_info->beamformer_su_reg_maping &= ~(BIT(beamformer_entry->su_reg_index));\n\t\t\tbeamformer_entry->su_reg_index = 0xFF;\n\t\t} else { /*@MU BFer */\n\t\t\t/*set validity of MU STA0 and MU STA1*/\n\t\t\tbeamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0;\n\t\t\todm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);\n\n\t\t\todm_memory_set(dm, beamformer_entry->gid_valid, 0, 8);\n\t\t\todm_memory_set(dm, beamformer_entry->user_position, 0, 16);\n\t\t\tbeamformer_entry->is_mu_ap = false;\n\t\t}\n\t}\n\n\tif (p_beamformee_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) {\n\t\thal_txbf_8822b_rf_mode(dm, beamforming_info, idx);\n\t\tif (p_beamformee_entry->is_mu_sta == 0) { /*SU BFee*/\n\t\t\tif (p_beamformee_entry->su_reg_index == 0) {\n\t\t\t\todm_write_2byte(dm, REG_TXBF_CTRL_8822B, 0x0);\n\t\t\t\todm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7));\n\t\t\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B, 0);\n\t\t\t} else {\n\t\t\t\todm_write_2byte(dm, REG_TXBF_CTRL_8822B + 2, 0x0 | BIT(14) | BIT(15) | BIT(12));\n\n\t\t\t\todm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2,\n\t\t\t\t\t\todm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2) & 0x60);\n\t\t\t}\n\t\t\tbeamforming_info->beamformee_su_reg_maping &= ~(BIT(p_beamformee_entry->su_reg_index));\n\t\t\tp_beamformee_entry->su_reg_index = 0xFF;\n\t\t} else { /*@MU BFee */\n\t\t\t/*@Disable sending NDPA & BF-rpt-poll to this BFee*/\n\t\t\todm_write_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index], 0);\n\t\t\t/*set validity of MU STA*/\n\t\t\tbeamforming_info->reg_mu_tx_ctrl &= ~(BIT(p_beamformee_entry->mu_reg_index));\n\t\t\todm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);\n\n\t\t\tp_beamformee_entry->is_mu_sta = false;\n\t\t\tbeamforming_info->beamformee_mu_reg_maping &= ~(BIT(p_beamformee_entry->mu_reg_index));\n\t\t\tp_beamformee_entry->mu_reg_index = 0xFF;\n\t\t}\n\t}\n}\n\n/***********SU & MU BFee Entry Only when souding done****************/\nvoid hal_txbf_8822b_status(\n\tvoid *dm_void,\n\tu8 beamform_idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu16 beam_ctrl_val, tmp_val;\n\tu32 beam_ctrl_reg;\n\tstruct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry;\n\tboolean is_mu_sounding = beamforming_info->is_mu_sounding, is_bitmap_ready = false;\n\tu16 bitmap;\n\tu8 idx, gid, i;\n\tu8 id1, id0;\n\tu32 gid_valid[6] = {0};\n\tu32 value32;\n\tboolean is_sounding_success[6] = {false};\n\n\tif (beamform_idx < BEAMFORMEE_ENTRY_NUM)\n\t\tbeamform_entry = &beamforming_info->beamformee_entry[beamform_idx];\n\telse\n\t\treturn;\n\n\t/*SU sounding done */\n\tif (is_mu_sounding == false) {\n\t\tif (phydm_acting_determine(dm, phydm_acting_as_ibss))\n\t\t\tbeam_ctrl_val = beamform_entry->mac_id;\n\t\telse\n\t\t\tbeam_ctrl_val = beamform_entry->p_aid;\n\n\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t  \"@%s, beamform_entry.beamform_entry_state = %d\",\n\t\t\t  __func__, beamform_entry->beamform_entry_state);\n\n\t\tif (beamform_entry->su_reg_index == 0)\n\t\t\tbeam_ctrl_reg = REG_TXBF_CTRL_8822B;\n\t\telse {\n\t\t\tbeam_ctrl_reg = REG_TXBF_CTRL_8822B + 2;\n\t\t\tbeam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);\n\t\t}\n\n\t\tif (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {\n\t\t\tif (beamform_entry->sound_bw == CHANNEL_WIDTH_20)\n\t\t\t\tbeam_ctrl_val |= BIT(9);\n\t\t\telse if (beamform_entry->sound_bw == CHANNEL_WIDTH_40)\n\t\t\t\tbeam_ctrl_val |= (BIT(9) | BIT(10));\n\t\t\telse if (beamform_entry->sound_bw == CHANNEL_WIDTH_80)\n\t\t\t\tbeam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));\n\t\t} else {\n\t\t\tPHYDM_DBG(dm, DBG_TXBF, \"@%s, Don't apply Vmatrix\",\n\t\t\t\t  __func__);\n\t\t\tbeam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));\n\t\t}\n\n\t\todm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);\n\t\t/*@disable NDP packet use beamforming */\n\t\ttmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8822B);\n\t\todm_write_2byte(dm, REG_TXBF_CTRL_8822B, tmp_val | BIT(15));\n\t} else {\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"@%s, MU Sounding Done\\n\", __func__);\n\t\t/*@MU sounding done */\n\t\tif (1) { /* @(beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { */\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"@%s, BEAMFORMING_ENTRY_STATE_PROGRESSED\\n\",\n\t\t\t\t  __func__);\n\n\t\t\tvalue32 = odm_get_bb_reg(dm, R_0x1684, MASKDWORD);\n\t\t\tis_sounding_success[0] = (value32 & BIT(10)) ? 1 : 0;\n\t\t\tis_sounding_success[1] = (value32 & BIT(26)) ? 1 : 0;\n\t\t\tvalue32 = odm_get_bb_reg(dm, R_0x1688, MASKDWORD);\n\t\t\tis_sounding_success[2] = (value32 & BIT(10)) ? 1 : 0;\n\t\t\tis_sounding_success[3] = (value32 & BIT(26)) ? 1 : 0;\n\t\t\tvalue32 = odm_get_bb_reg(dm, R_0x168c, MASKDWORD);\n\t\t\tis_sounding_success[4] = (value32 & BIT(10)) ? 1 : 0;\n\t\t\tis_sounding_success[5] = (value32 & BIT(26)) ? 1 : 0;\n\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"@%s, is_sounding_success STA1:%d,  STA2:%d, STA3:%d, STA4:%d, STA5:%d, STA6:%d\\n\",\n\t\t\t\t  __func__, is_sounding_success[0],\n\t\t\t\t  is_sounding_success[1],\n\t\t\t\t  is_sounding_success[2],\n\t\t\t\t  is_sounding_success[3],\n\t\t\t\t  is_sounding_success[4],\n\t\t\t\t  is_sounding_success[5]);\n\n\t\t\tvalue32 = odm_get_bb_reg(dm, R_0xf4c, 0xFFFF0000);\n\t\t\t/* odm_set_bb_reg(dm, R_0x19e0, MASKHWORD, 0xFFFF);Let MAC ignore bitmap */\n\n\t\t\tis_bitmap_ready = (boolean)((value32 & BIT(15)) >> 15);\n\t\t\tbitmap = (u16)(value32 & 0x3FFF);\n\n\t\t\tfor (idx = 0; idx < 15; idx++) {\n\t\t\t\tif (idx < 5) { /*@bit0~4*/\n\t\t\t\t\tid0 = 0;\n\t\t\t\t\tid1 = (u8)(idx + 1);\n\t\t\t\t} else if (idx < 9) { /*@bit5~8*/\n\t\t\t\t\tid0 = 1;\n\t\t\t\t\tid1 = (u8)(idx - 3);\n\t\t\t\t} else if (idx < 12) { /*@bit9~11*/\n\t\t\t\t\tid0 = 2;\n\t\t\t\t\tid1 = (u8)(idx - 6);\n\t\t\t\t} else if (idx < 14) { /*@bit12~13*/\n\t\t\t\t\tid0 = 3;\n\t\t\t\t\tid1 = (u8)(idx - 8);\n\t\t\t\t} else { /*@bit14*/\n\t\t\t\t\tid0 = 4;\n\t\t\t\t\tid1 = (u8)(idx - 9);\n\t\t\t\t}\n\t\t\t\tif (bitmap & BIT(idx)) {\n\t\t\t\t\t/*Pair 1*/\n\t\t\t\t\tgid = (idx << 1) + 1;\n\t\t\t\t\tgid_valid[id0] |= (BIT(gid));\n\t\t\t\t\tgid_valid[id1] |= (BIT(gid));\n\t\t\t\t\t/*Pair 2*/\n\t\t\t\t\tgid += 1;\n\t\t\t\t\tgid_valid[id0] |= (BIT(gid));\n\t\t\t\t\tgid_valid[id1] |= (BIT(gid));\n\t\t\t\t} else {\n\t\t\t\t\t/*Pair 1*/\n\t\t\t\t\tgid = (idx << 1) + 1;\n\t\t\t\t\tgid_valid[id0] &= ~(BIT(gid));\n\t\t\t\t\tgid_valid[id1] &= ~(BIT(gid));\n\t\t\t\t\t/*Pair 2*/\n\t\t\t\t\tgid += 1;\n\t\t\t\t\tgid_valid[id0] &= ~(BIT(gid));\n\t\t\t\t\tgid_valid[id1] &= ~(BIT(gid));\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tfor (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {\n\t\t\t\tbeamform_entry = &beamforming_info->beamformee_entry[i];\n\t\t\t\tif (beamform_entry->is_mu_sta && beamform_entry->mu_reg_index < 6) {\n\t\t\t\t\tvalue32 = gid_valid[beamform_entry->mu_reg_index];\n\t\t\t\t\tfor (idx = 0; idx < 4; idx++) {\n\t\t\t\t\t\tbeamform_entry->gid_valid[idx] = (u8)(value32 & 0xFF);\n\t\t\t\t\t\tvalue32 = (value32 >> 8);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tfor (idx = 0; idx < 6; idx++) {\n\t\t\t\tbeamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));\n\t\t\t\tbeamforming_info->reg_mu_tx_ctrl |= ((idx << 8) & (BIT(8) | BIT(9) | BIT(10)));\n\t\t\t\todm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);\n\t\t\t\todm_set_mac_reg(dm, R_0x14c4, MASKDWORD, gid_valid[idx]); /*set MU STA gid valid table*/\n\t\t\t}\n\n\t\t\t/*@Enable TxMU PPDU*/\n\t\t\tif (beamforming_info->dbg_disable_mu_tx == false)\n\t\t\t\tbeamforming_info->reg_mu_tx_ctrl |= BIT(7);\n\t\t\telse\n\t\t\t\tbeamforming_info->reg_mu_tx_ctrl &= ~BIT(7);\n\t\t\todm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);\n\t\t}\n\t}\n}\n\n/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/\nvoid hal_txbf_8822b_config_gtab(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL;\n\tu32 gid_valid = 0, user_position_l = 0, user_position_h = 0, i;\n\n\tif (beamforming_info->mu_ap_index < BEAMFORMER_ENTRY_NUM)\n\t\tbeamformer_entry = &beamforming_info->beamformer_entry[beamforming_info->mu_ap_index];\n\telse\n\t\treturn;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"%s==>\\n\", __func__);\n\n\t/*@For GID 0~31*/\n\tfor (i = 0; i < 4; i++)\n\t\tgid_valid |= (beamformer_entry->gid_valid[i] << (i << 3));\n\tfor (i = 0; i < 8; i++) {\n\t\tif (i < 4)\n\t\t\tuser_position_l |= (beamformer_entry->user_position[i] << (i << 3));\n\t\telse\n\t\t\tuser_position_h |= (beamformer_entry->user_position[i] << ((i - 4) << 3));\n\t}\n\t/*select MU STA0 table*/\n\tbeamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));\n\todm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);\n\todm_set_bb_reg(dm, R_0x14c4, MASKDWORD, gid_valid);\n\todm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l);\n\todm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h);\n\n\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t  \"%s: STA0: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\\n\",\n\t\t  __func__, gid_valid, user_position_l, user_position_h);\n\n\tgid_valid = 0;\n\tuser_position_l = 0;\n\tuser_position_h = 0;\n\n\t/*@For GID 32~64*/\n\tfor (i = 4; i < 8; i++)\n\t\tgid_valid |= (beamformer_entry->gid_valid[i] << ((i - 4) << 3));\n\tfor (i = 8; i < 16; i++) {\n\t\tif (i < 4)\n\t\t\tuser_position_l |= (beamformer_entry->user_position[i] << ((i - 8) << 3));\n\t\telse\n\t\t\tuser_position_h |= (beamformer_entry->user_position[i] << ((i - 12) << 3));\n\t}\n\t/*select MU STA1 table*/\n\tbeamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));\n\tbeamforming_info->reg_mu_tx_ctrl |= BIT(8);\n\todm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);\n\todm_set_bb_reg(dm, R_0x14c4, MASKDWORD, gid_valid);\n\todm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l);\n\todm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h);\n\n\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t  \"%s: STA1: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\\n\",\n\t\t  __func__, gid_valid, user_position_l, user_position_h);\n\n\t/* Set validity of MU STA0 and MU STA1*/\n\tbeamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0;\n\tbeamforming_info->reg_mu_tx_ctrl |= 0x3; /* STA0, STA1*/\n\todm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);\n}\n\n#if 0\n/*This function translate the bitmap to GTAB*/\nvoid\nhaltxbf8822b_gtab_translation(\n\tstruct dm_struct\t\t\t*dm\n)\n{\n\tu8 idx, gid;\n\tu8 id1, id0;\n\tu32 gid_valid[6] = {0};\n\tu32 user_position_lsb[6] = {0};\n\tu32 user_position_msb[6] = {0};\n\n\tfor (idx = 0; idx < 15; idx++) {\n\t\tif (idx < 5) {/*@bit0~4*/\n\t\t\tid0 = 0;\n\t\t\tid1 = (u8)(idx + 1);\n\t\t} else if (idx < 9) { /*@bit5~8*/\n\t\t\tid0 = 1;\n\t\t\tid1 = (u8)(idx - 3);\n\t\t} else if (idx < 12) { /*@bit9~11*/\n\t\t\tid0 = 2;\n\t\t\tid1 = (u8)(idx - 6);\n\t\t} else if (idx < 14) { /*@bit12~13*/\n\t\t\tid0 = 3;\n\t\t\tid1 = (u8)(idx - 8);\n\t\t} else { /*@bit14*/\n\t\t\tid0 = 4;\n\t\t\tid1 = (u8)(idx - 9);\n\t\t}\n\n\t\t/*Pair 1*/\n\t\tgid = (idx << 1) + 1;\n\t\tgid_valid[id0] |= (1 << gid);\n\t\tgid_valid[id1] |= (1 << gid);\n\t\tif (gid < 16) {\n\t\t\t/*user_position_lsb[id0] |= (0 << (gid << 1));*/\n\t\t\tuser_position_lsb[id1] |= (1 << (gid << 1));\n\t\t} else {\n\t\t\t/*user_position_msb[id0] |= (0 << ((gid - 16) << 1));*/\n\t\t\tuser_position_msb[id1] |= (1 << ((gid - 16) << 1));\n\t\t}\n\n\t\t/*Pair 2*/\n\t\tgid += 1;\n\t\tgid_valid[id0] |= (1 << gid);\n\t\tgid_valid[id1] |= (1 << gid);\n\t\tif (gid < 16) {\n\t\t\tuser_position_lsb[id0] |= (1 << (gid << 1));\n\t\t\t/*user_position_lsb[id1] |= (0 << (gid << 1));*/\n\t\t} else {\n\t\t\tuser_position_msb[id0] |= (1 << ((gid - 16) << 1));\n\t\t\t/*user_position_msb[id1] |= (0 << ((gid - 16) << 1));*/\n\t\t}\n\t}\n\n\n\tfor (idx = 0; idx < 6; idx++) {\n\t\t/*@dbg_print(\"gid_valid[%d] = 0x%x\\n\", idx, gid_valid[idx]);\n\t\tdbg_print(\"user_position[%d] = 0x%x   %x\\n\", idx, user_position_msb[idx], user_position_lsb[idx]);*/\n\t}\n}\n#endif\n\nvoid hal_txbf_8822b_fw_txbf(\n\tvoid *dm_void,\n\tu8 idx)\n{\n#if 0\n\tstruct _RT_BEAMFORMING_INFO\t*beam_info = GET_BEAMFORM_INFO(adapter);\n\tstruct _RT_BEAMFORMEE_ENTRY\t*p_beam_entry = beam_info->beamformee_entry + idx;\n\n\tif (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)\n\t\thal_txbf_8822b_download_ndpa(adapter, idx);\n\n\thal_txbf_8822b_fw_txbf_cmd(adapter);\n#endif\n}\n\n#endif\n\n#if (defined(CONFIG_BB_TXBF_API))\n/*this function is only used for BFer*/\nvoid phydm_8822btxbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i;\n\n\tif (dm->rf_type == RF_1T1R)\n\t\treturn;\n\n\tif (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {\n\t\tfor (i = RF_PATH_A; i <= RF_PATH_B; i++) {\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), 0x1); /*RF mode table write enable*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3); /*Select RX mode*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff, 0x00036); /*Set Table data*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff, 0x5AFCE); /*Set Table data*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), 0x0); /*RF mode table write disable*/\n\t\t}\n\t}\n\n\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(30), 1); /*@if Nsts > Nc, don't apply V matrix*/\n\n\tif (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {\n\t\t/*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/\n\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/\n\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); /*@ignore user since 8822B only 2Tx*/\n\n\t\t/*Nsts = 2\tAB*/\n\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433);\n\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);\n\n\t} else {\n\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x0); /*@enable BB TxBF ant mapping register*/\n\t\todm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 0); /*@ignore user since 8822B only 2Tx*/\n\n\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*@1SS by path-A*/\n\t\todm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*@2SS by path-A,B*/\n\t}\n}\n\n/*this function is for BFer bug workaround*/\nvoid phydm_8822b_sutxbfer_workaroud(void *dm_void, boolean enable_su_bfer,\n\t\t\t\t    u8 nc, u8 nr, u8 ng, u8 CB, u8 BW,\n\t\t\t\t    boolean is_vht)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (enable_su_bfer) {\n\t\todm_set_bb_reg(dm, R_0x19f8, BIT(22) | BIT(21) | BIT(20), 0x1);\n\t\todm_set_bb_reg(dm, R_0x19f8, BIT(25) | BIT(24) | BIT(23), 0x0);\n\t\todm_set_bb_reg(dm, R_0x19f8, BIT(16), 0x1);\n\n\t\tif (is_vht)\n\t\t\todm_set_bb_reg(dm, R_0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x1f);\n\t\telse\n\t\t\todm_set_bb_reg(dm, R_0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x22);\n\n\t\todm_set_bb_reg(dm, R_0x19f0, BIT(7) | BIT(6), nc);\n\t\todm_set_bb_reg(dm, R_0x19f0, BIT(9) | BIT(8), nr);\n\t\todm_set_bb_reg(dm, R_0x19f0, BIT(11) | BIT(10), ng);\n\t\todm_set_bb_reg(dm, R_0x19f0, BIT(13) | BIT(12), CB);\n\n\t\todm_set_bb_reg(dm, R_0xb58, BIT(3) | BIT(2), BW);\n\t\todm_set_bb_reg(dm, R_0xb58, BIT(7) | BIT(6) | BIT(5) | BIT(4), 0x0);\n\t\todm_set_bb_reg(dm, R_0xb58, BIT(9) | BIT(8), BW);\n\t\todm_set_bb_reg(dm, R_0xb58, BIT(13) | BIT(12) | BIT(11) | BIT(10), 0x0);\n\t} else {\n\t\todm_set_bb_reg(dm, R_0x19f8, BIT(16), 0x0);\n\t}\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] enable_su_bfer = %d, is_vht = %d\\n\",\n\t\t  __func__, enable_su_bfer, is_vht);\n\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t  \"[%s] nc = %d, nr = %d, ng = %d, CB = %d, BW = %d\\n\",\n\t\t  __func__, nc, nr, ng, CB, BW);\n}\n#endif\n#endif /* @(RTL8822B_SUPPORT == 1)*/\n"
  },
  {
    "path": "hal/phydm/txbf/haltxbf8822b.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#ifndef __HAL_TXBF_8822B_H__\n#define __HAL_TXBF_8822B_H__\n\n#if (RTL8822B_SUPPORT == 1)\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\nvoid hal_txbf_8822b_enter(\n\tvoid *dm_void,\n\tu8 idx);\n\nvoid hal_txbf_8822b_leave(\n\tvoid *dm_void,\n\tu8 idx);\n\nvoid hal_txbf_8822b_status(\n\tvoid *dm_void,\n\tu8 beamform_idx);\n\nvoid hal_txbf_8822b_config_gtab(\n\tvoid *dm_void);\n\nvoid hal_txbf_8822b_fw_txbf(\n\tvoid *dm_void,\n\tu8 idx);\n#else\n#define hal_txbf_8822b_enter(dm_void, idx)\n#define hal_txbf_8822b_leave(dm_void, idx)\n#define hal_txbf_8822b_status(dm_void, idx)\n#define hal_txbf_8822b_fw_txbf(dm_void, idx)\n#define hal_txbf_8822b_config_gtab(dm_void)\n\n#endif\n\n#if (defined(CONFIG_BB_TXBF_API))\nvoid phydm_8822btxbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt);\n\nvoid phydm_8822b_sutxbfer_workaroud(void *dm_void, boolean enable_su_bfer,\n\t\t\t\t    u8 nc, u8 nr, u8 ng, u8 CB, u8 BW,\n\t\t\t\t    boolean is_vht);\n\n#else\n#define phydm_8822btxbf_rfmode(dm_void, su_bfee_cnt, mu_bfee_cnt)\n#define phydm_8822b_sutxbfer_workaroud(dm_void, enable_su_bfer, nc, nr, ng, CB, BW, is_vht)\n#endif\n\n#else\n#define hal_txbf_8822b_enter(dm_void, idx)\n#define hal_txbf_8822b_leave(dm_void, idx)\n#define hal_txbf_8822b_status(dm_void, idx)\n#define hal_txbf_8822b_fw_txbf(dm_void, idx)\n#define hal_txbf_8822b_config_gtab(dm_void)\n\n#endif\n#endif\n"
  },
  {
    "path": "hal/phydm/txbf/haltxbfinterface.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n/*************************************************************\n * Description:\n *\n * This file is for TXBF interface mechanism\n *\n ************************************************************/\n#include \"mp_precomp.h\"\n#include \"../phydm_precomp.h\"\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\nvoid beamforming_gid_paid(\n\tvoid *adapter,\n\tPRT_TCB tcb)\n{\n\tu8 RA[6] = {0};\n\tu8 *p_header = GET_FRAME_OF_FIRST_FRAG(adapter, tcb);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);\n\n\tif (((PADAPTER)adapter)->HardwareType < HARDWARE_TYPE_RTL8192EE)\n\t\treturn;\n\telse if (IS_WIRELESS_MODE_N((PADAPTER)adapter) == false)\n\t\treturn;\n\n#if (SUPPORT_MU_BF == 1)\n\tif (tcb->tx_bf_pkt_type == RT_BF_PKT_TYPE_BROADCAST_NDPA) { /* @MU NDPA */\n#else\n\tif (0) {\n#endif\n\t\t/* @Fill G_ID and P_AID */\n\t\ttcb->G_ID = 63;\n\t\tif (beam_info->first_mu_bfee_index < BEAMFORMEE_ENTRY_NUM) {\n\t\t\ttcb->P_AID = beam_info->beamformee_entry[beam_info->first_mu_bfee_index].p_aid;\n\t\t\tRT_DISP(FBEAM, FBEAM_FUN, (\"[David]@%s End, G_ID=0x%X, P_AID=0x%X\\n\", __func__, tcb->G_ID, tcb->P_AID));\n\t\t}\n\t} else {\n\t\tGET_80211_HDR_ADDRESS1(p_header, &RA);\n\n\t\t/* VHT SU PPDU carrying one or more group addressed MPDUs or */\n\t\t/* Transmitting a VHT NDP intended for multiple recipients */\n\t\tif (MacAddr_isBcst(RA) || MacAddr_isMulticast(RA) || tcb->macId == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) {\n\t\t\ttcb->G_ID = 63;\n\t\t\ttcb->P_AID = 0;\n\t\t} else if (ACTING_AS_AP(adapter)) {\n\t\t\tu16 AID = (u16)(MacIdGetOwnerAssociatedClientAID(adapter, tcb->macId) & 0x1ff); /*@AID[0:8]*/\n\n\t\t\t/*RT_DISP(FBEAM, FBEAM_FUN, (\"@%s  tcb->mac_id=0x%X, AID=0x%X\\n\", __func__, tcb->mac_id, AID));*/\n\t\t\ttcb->G_ID = 63;\n\n\t\t\tif (AID == 0) /*@A PPDU sent by an AP to a non associated STA*/\n\t\t\t\ttcb->P_AID = 0;\n\t\t\telse { /*Sent by an AP and addressed to a STA associated with that AP*/\n\t\t\t\tu16 BSSID = 0;\n\t\t\t\tGET_80211_HDR_ADDRESS2(p_header, &RA);\n\t\t\t\tBSSID = ((RA[5] & 0xf0) >> 4) ^ (RA[5] & 0xf); /*@BSSID[44:47] xor BSSID[40:43]*/\n\t\t\t\ttcb->P_AID = (AID + BSSID * 32) & 0x1ff; /*@(dec(A) + dec(B)*32) mod 512*/\n\t\t\t}\n\t\t} else if (ACTING_AS_IBSS(((PADAPTER)adapter))) {\n\t\t\ttcb->G_ID = 63;\n\t\t\t/*P_AID for infrasturcture mode; MACID for ad-hoc mode. */\n\t\t\ttcb->P_AID = tcb->macId;\n\t\t} else if (MgntLinkStatusQuery(adapter)) { /*@Addressed to AP*/\n\t\t\ttcb->G_ID = 0;\n\t\t\tGET_80211_HDR_ADDRESS1(p_header, &RA);\n\t\t\ttcb->P_AID = RA[5]; /*RA[39:47]*/\n\t\t\ttcb->P_AID = (tcb->P_AID << 1) | (RA[4] >> 7);\n\t\t} else {\n\t\t\ttcb->G_ID = 63;\n\t\t\ttcb->P_AID = 0;\n\t\t}\n\t\t/*RT_DISP(FBEAM, FBEAM_FUN, (\"[David]@%s End, G_ID=0x%X, P_AID=0x%X\\n\", __func__, tcb->G_ID, tcb->P_AID));*/\n\t}\n}\n\nenum rt_status\nbeamforming_get_report_frame(\n\tvoid *adapter,\n\tPRT_RFD rfd,\n\tPOCTET_STRING p_pdu_os)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;\n\tu8 *p_mimo_ctrl_field, p_csi_matrix;\n\tu8 idx, nc, nr, CH_W;\n\tu16 csi_matrix_len = 0;\n\n\tACT_PKT_TYPE pkt_type = ACT_PKT_TYPE_UNKNOWN;\n\n\t/* @Memory comparison to see if CSI report is the same with previous one */\n\tbeamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, Frame_Addr2(*p_pdu_os), &idx);\n\n\tif (beamform_entry == NULL) {\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s: Cannot find entry by addr\\n\",\n\t\t\t  __func__);\n\t\treturn RT_STATUS_FAILURE;\n\t}\n\n\tpkt_type = PacketGetActionFrameType(p_pdu_os);\n\n\t/* @-@ Modified by David */\n\tif (pkt_type == ACT_PKT_VHT_COMPRESSED_BEAMFORMING) {\n\t\tp_mimo_ctrl_field = p_pdu_os->Octet + 26;\n\t\tnc = ((*p_mimo_ctrl_field) & 0x7) + 1;\n\t\tnr = (((*p_mimo_ctrl_field) & 0x38) >> 3) + 1;\n\t\tCH_W = (((*p_mimo_ctrl_field) & 0xC0) >> 6);\n\t\t/*p_csi_matrix = p_mimo_ctrl_field + 3 + nc;*/ /* 24+(1+1+3)+2  MAC header+(Category+ActionCode+MIMOControlField) +SNR(nc=2) */\n\t\tcsi_matrix_len = p_pdu_os->Length - 26 - 3 - nc;\n\t} else if (pkt_type == ACT_PKT_HT_COMPRESSED_BEAMFORMING) {\n\t\tp_mimo_ctrl_field = p_pdu_os->Octet + 26;\n\t\tnc = ((*p_mimo_ctrl_field) & 0x3) + 1;\n\t\tnr = (((*p_mimo_ctrl_field) & 0xC) >> 2) + 1;\n\t\tCH_W = (((*p_mimo_ctrl_field) & 0x10) >> 4);\n\t\t/*p_csi_matrix = p_mimo_ctrl_field + 6 + nr;*/ /* 24+(1+1+6)+2  MAC header+(Category+ActionCode+MIMOControlField) +SNR(nc=2) */\n\t\tcsi_matrix_len = p_pdu_os->Length - 26 - 6 - nr;\n\t} else\n\t\treturn RT_STATUS_SUCCESS;\n\n\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t  \"[%s] idx=%d, pkt type=%d, nc=%d, nr=%d, CH_W=%d\\n\", __func__,\n\t\t  idx, pkt_type, nc, nr, CH_W);\n\n\treturn RT_STATUS_SUCCESS;\n}\n\nvoid construct_ht_ndpa_packet(\n\t// 2017/11 MH PHYDM compile. But why need to use windows maco?\n\t// For all linux code, it should be useless?\n\t//void\t\t\t\t*adapter = dm->adapter;\n\tADAPTER * adapter,\n\t//void\t\t*adapter,\n\tu8 *RA,\n\tu8 *buffer,\n\tu32 *p_length,\n\tenum channel_width BW)\n{\n\tu16 duration = 0;\n\tPMGNT_INFO mgnt_info = &(((PADAPTER)adapter)->MgntInfo);\n\t//PMGNT_INFO\t\t\t\tmgnt_info = &((MGNT_INFO)(((PADAPTER)adapter)->MgntInfo));\n\tOCTET_STRING p_ndpa_frame, action_content;\n\tu8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c};\n\n\tPlatformZeroMemory(buffer, 32);\n\n\tSET_80211_HDR_FRAME_CONTROL(buffer, 0);\n\n\tSET_80211_HDR_ORDER(buffer, 1);\n\tSET_80211_HDR_TYPE_AND_SUBTYPE(buffer, Type_Action_No_Ack);\n\n\tSET_80211_HDR_ADDRESS1(buffer, RA);\n\tSET_80211_HDR_ADDRESS2(buffer, ((PADAPTER)adapter)->CurrentAddress);\n\tSET_80211_HDR_ADDRESS3(buffer, ((PMGNT_INFO)mgnt_info)->Bssid);\n\n\tduration = 2 * a_SifsTime + 40;\n\n\tif (BW == CHANNEL_WIDTH_40)\n\t\tduration += 87;\n\telse\n\t\tduration += 180;\n\n\tSET_80211_HDR_DURATION(buffer, duration);\n\n\t/* @HT control field */\n\tSET_HT_CTRL_CSI_STEERING(buffer + sMacHdrLng, 3);\n\tSET_HT_CTRL_NDP_ANNOUNCEMENT(buffer + sMacHdrLng, 1);\n\n\tFillOctetString(p_ndpa_frame, buffer, sMacHdrLng + sHTCLng);\n\n\tFillOctetString(action_content, action_hdr, 4);\n\tPacketAppendData(&p_ndpa_frame, action_content);\n\n\t*p_length = 32;\n}\n\nboolean\nsend_fw_ht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tenum channel_width BW)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tvoid *adapter = dm->adapter;\n\tPRT_TCB tcb;\n\tPRT_TX_LOCAL_BUFFER p_buf;\n\tboolean ret = true;\n\tu32 buf_len;\n\tu8 *buf_addr;\n\tu8 desc_len = 0, idx = 0, ndp_tx_rate;\n\tvoid *p_def_adapter = GetDefaultAdapter(((PADAPTER)adapter));\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tif (beamform_entry == NULL)\n\t\treturn false;\n\n\tndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] ndp_tx_rate =%d\\n\", __func__,\n\t\t  ndp_tx_rate);\n\tPlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);\n\n\tif (MgntGetFWBuffer(p_def_adapter, &tcb, &p_buf)) {\n#if (DEV_BUS_TYPE != RT_PCI_INTERFACE)\n\t\tdesc_len = ((PADAPTER)adapter)->HWDescHeadLength - hal_data->USBALLDummyLength;\n#endif\n\t\tbuf_addr = p_buf->Buffer.VirtualAddress + desc_len;\n\n\t\tconstruct_ht_ndpa_packet(\n\t\t\tadapter,\n\t\t\tRA,\n\t\t\tbuf_addr,\n\t\t\t&buf_len,\n\t\t\tBW);\n\n\t\ttcb->PacketLength = buf_len + desc_len;\n\n\t\ttcb->bTxEnableSwCalcDur = true;\n\n\t\ttcb->BWOfPacket = BW;\n\n\t\tif (ACTING_AS_IBSS(((PADAPTER)adapter)) || ACTING_AS_AP(((PADAPTER)adapter)))\n\t\t\ttcb->G_ID = 63;\n\n\t\ttcb->P_AID = beamform_entry->p_aid;\n\t\ttcb->DataRate = ndp_tx_rate; /*rate of NDP decide by nr*/\n\n\t\t((PADAPTER)adapter)->HalFunc.CmdSendPacketHandler(((PADAPTER)adapter), tcb, p_buf, tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false);\n\t} else\n\t\tret = false;\n\n\tPlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);\n\n\tif (ret)\n\t\tRT_DISP_DATA(FBEAM, FBEAM_DATA, \"\", p_buf->Buffer.VirtualAddress, tcb->PacketLength);\n\n\treturn ret;\n}\n\nboolean\nsend_sw_ht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tenum channel_width BW)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tvoid *adapter = dm->adapter;\n\tPRT_TCB tcb;\n\tPRT_TX_LOCAL_BUFFER p_buf;\n\tboolean ret = true;\n\tu8 idx = 0, ndp_tx_rate = 0;\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] ndp_tx_rate =%d\\n\", __func__,\n\t\t  ndp_tx_rate);\n\n\tPlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);\n\n\tif (MgntGetBuffer(adapter, &tcb, &p_buf)) {\n\t\tconstruct_ht_ndpa_packet(\n\t\t\tadapter,\n\t\t\tRA,\n\t\t\tp_buf->Buffer.VirtualAddress,\n\t\t\t&tcb->PacketLength,\n\t\t\tBW);\n\n\t\ttcb->bTxEnableSwCalcDur = true;\n\n\t\ttcb->BWOfPacket = BW;\n\n\t\tMgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate);\n\t} else\n\t\tret = false;\n\n\tPlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);\n\n\tif (ret)\n\t\tRT_DISP_DATA(FBEAM, FBEAM_DATA, \"\", p_buf->Buffer.VirtualAddress, tcb->PacketLength);\n\n\treturn ret;\n}\n\nvoid construct_vht_ndpa_packet(\n\tstruct dm_struct *dm,\n\tu8 *RA,\n\tu16 AID,\n\tu8 *buffer,\n\tu32 *p_length,\n\tenum channel_width BW)\n{\n\tu16 duration = 0;\n\tu8 sequence = 0;\n\tu8 *p_ndpa_frame = buffer;\n\tstruct _RT_NDPA_STA_INFO sta_info;\n\t// 2017/11 MH PHYDM compile. But why need to use windows maco?\n\t// For all linux code, it should be useless?\n\t//void\t\t\t\t*adapter = dm->adapter;\n\tADAPTER * adapter = (PADAPTER)(dm->adapter);\n\tu8 idx = 0;\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);\n\t/* @Frame control. */\n\tSET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0);\n\tSET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA);\n\n\tSET_80211_HDR_ADDRESS1(p_ndpa_frame, RA);\n\tSET_80211_HDR_ADDRESS2(p_ndpa_frame, beamform_entry->my_mac_addr);\n\n\t// 2017/11 MH PHYDM compile. But why need to use windows maco?\n\t// For all linux code, it should be useless?\n\tduration = 2 * a_SifsTime + 44;\n\n\tif (BW == CHANNEL_WIDTH_80)\n\t\tduration += 40;\n\telse if (BW == CHANNEL_WIDTH_40)\n\t\tduration += 87;\n\telse\n\t\tduration += 180;\n\n\tSET_80211_HDR_DURATION(p_ndpa_frame, duration);\n\n\tsequence = *(dm->sounding_seq) << 2;\n\todm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1);\n\n\tif (phydm_acting_determine(dm, phydm_acting_as_ibss) || phydm_acting_determine(dm, phydm_acting_as_ap) == false)\n\t\tAID = 0;\n\n\tsta_info.aid = AID;\n\tsta_info.feedback_type = 0;\n\tsta_info.nc_index = 0;\n\n\todm_move_memory(dm, p_ndpa_frame + 17, (u8 *)&sta_info, 2);\n\n\t*p_length = 19;\n}\n\nboolean\nsend_fw_vht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tu16 AID,\n\tenum channel_width BW)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tvoid *adapter = dm->adapter;\n\tPRT_TCB tcb;\n\tPRT_TX_LOCAL_BUFFER p_buf;\n\tboolean ret = true;\n\tu32 buf_len;\n\tu8 *buf_addr;\n\tu8 desc_len = 0, idx = 0, ndp_tx_rate = 0;\n\tvoid *p_def_adapter = GetDefaultAdapter(((PADAPTER)adapter));\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tif (beamform_entry == NULL)\n\t\treturn false;\n\n\tndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] ndp_tx_rate =%d\\n\", __func__,\n\t\t  ndp_tx_rate);\n\n\tPlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);\n\n\tif (MgntGetFWBuffer(p_def_adapter, &tcb, &p_buf)) {\n#if (DEV_BUS_TYPE != RT_PCI_INTERFACE)\n\t\tdesc_len = ((PADAPTER)adapter)->HWDescHeadLength - hal_data->USBALLDummyLength;\n#endif\n\t\tbuf_addr = p_buf->Buffer.VirtualAddress + desc_len;\n\n\t\tconstruct_vht_ndpa_packet(\n\t\t\tdm,\n\t\t\tRA,\n\t\t\tAID,\n\t\t\tbuf_addr,\n\t\t\t&buf_len,\n\t\t\tBW);\n\n\t\ttcb->PacketLength = buf_len + desc_len;\n\n\t\ttcb->bTxEnableSwCalcDur = true;\n\n\t\ttcb->BWOfPacket = BW;\n\n\t\tif (phydm_acting_determine(dm, phydm_acting_as_ibss) || phydm_acting_determine(dm, phydm_acting_as_ap))\n\t\t\ttcb->G_ID = 63;\n\n\t\ttcb->P_AID = beamform_entry->p_aid;\n\t\ttcb->DataRate = ndp_tx_rate; /*@decide by nr*/\n\n\t\t((PADAPTER)adapter)->HalFunc.CmdSendPacketHandler(adapter, tcb, p_buf, tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false);\n\t} else\n\t\tret = false;\n\n\tPlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] End, ret=%d\\n\", __func__, ret);\n\n\tif (ret)\n\t\tRT_DISP_DATA(FBEAM, FBEAM_DATA, \"\", p_buf->Buffer.VirtualAddress, tcb->PacketLength);\n\n\treturn ret;\n}\n\nboolean\nsend_sw_vht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tu16 AID,\n\tenum channel_width BW)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tvoid *adapter = dm->adapter;\n\tPRT_TCB tcb;\n\tPRT_TX_LOCAL_BUFFER p_buf;\n\tboolean ret = true;\n\tu8 idx = 0, ndp_tx_rate = 0;\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);\n\n\tndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] ndp_tx_rate =%d\\n\", __func__,\n\t\t  ndp_tx_rate);\n\n\tPlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);\n\n\tif (MgntGetBuffer(adapter, &tcb, &p_buf)) {\n\t\tconstruct_vht_ndpa_packet(\n\t\t\tdm,\n\t\t\tRA,\n\t\t\tAID,\n\t\t\tp_buf->Buffer.VirtualAddress,\n\t\t\t&tcb->PacketLength,\n\t\t\tBW);\n\n\t\ttcb->bTxEnableSwCalcDur = true;\n\t\ttcb->BWOfPacket = BW;\n\n\t\t/*rate of NDP decide by nr*/\n\t\tMgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate);\n\t} else\n\t\tret = false;\n\n\tPlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);\n\n\tif (ret)\n\t\tRT_DISP_DATA(FBEAM, FBEAM_DATA, \"\", p_buf->Buffer.VirtualAddress, tcb->PacketLength);\n\n\treturn ret;\n}\n\n#ifdef SUPPORT_MU_BF\n#if (SUPPORT_MU_BF == 1)\n/*@\n * Description: On VHT GID management frame by an MU beamformee.\n *\n * 2015.05.20. Created by tynli.\n */\nenum rt_status\nbeamforming_get_vht_gid_mgnt_frame(\n\tvoid *adapter,\n\tPRT_RFD rfd,\n\tPOCTET_STRING p_pdu_os)\n{\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));\n\tstruct dm_struct *dm = &hal_data->DM_OutSrc;\n\tenum rt_status rt_status = RT_STATUS_SUCCESS;\n\tu8 *p_buffer = NULL;\n\tu8 *p_raddr = NULL;\n\tu8 mem_status[8] = {0}, user_pos[16] = {0};\n\tu8 idx;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);\n\tstruct _RT_BEAMFORMER_ENTRY *beamform_entry = &beam_info->beamformer_entry[beam_info->mu_ap_index];\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] On VHT GID mgnt frame!\\n\", __func__);\n\n\t/* @Check length*/\n\tif (p_pdu_os->length < (FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY + 16)) {\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s: Invalid length (%d)\\n\", __func__,\n\t\t\t  p_pdu_os->length);\n\t\treturn RT_STATUS_INVALID_LENGTH;\n\t}\n\n\t/* @Check RA*/\n\tp_raddr = (u8 *)(p_pdu_os->Octet) + 4;\n\tif (!eq_mac_addr(p_raddr, adapter->CurrentAddress)) {\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s: Drop because of RA error.\\n\",\n\t\t\t  __func__);\n\t\treturn RT_STATUS_PKT_DROP;\n\t}\n\n\tRT_DISP_DATA(FBEAM, FBEAM_DATA, \"On VHT GID Mgnt Frame ==>:\\n\", p_pdu_os->Octet, p_pdu_os->length);\n\n\t/*Parsing Membership status array*/\n\tp_buffer = p_pdu_os->Octet + FRAME_OFFSET_VHT_GID_MGNT_MEMBERSHIP_STATUS_ARRAY;\n\tfor (idx = 0; idx < 8; idx++) {\n\t\tmem_status[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx);\n\t\tbeamform_entry->gid_valid[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx);\n\t}\n\n\tRT_DISP_DATA(FBEAM, FBEAM_DATA, \"mem_status: \", mem_status, 8);\n\n\t/* Parsing User Position array*/\n\tp_buffer = p_pdu_os->Octet + FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY;\n\tfor (idx = 0; idx < 16; idx++) {\n\t\tuser_pos[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx);\n\t\tbeamform_entry->user_position[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx);\n\t}\n\n\tRT_DISP_DATA(FBEAM, FBEAM_DATA, \"user_pos: \", user_pos, 16);\n\n\t/* @Group ID detail printed*/\n\t{\n\t\tu8 i, j;\n\t\tu8 tmp_val;\n\t\tu16 tmp_val2;\n\n\t\tfor (i = 0; i < 8; i++) {\n\t\t\ttmp_val = mem_status[i];\n\t\t\ttmp_val2 = ((user_pos[i * 2 + 1] << 8) & 0xFF00) + (user_pos[i * 2] & 0xFF);\n\t\t\tfor (j = 0; j < 8; j++) {\n\t\t\t\tif ((tmp_val >> j) & BIT(0)) {\n\t\t\t\t\tPHYDM_DBG(dm, DBG_TXBF, \"Use Group ID (%d), User Position (%d)\\n\",\n\t\t\t\t\t\t  (i * 8 + j), (tmp_val2 >> 2 * j) & 0x3);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t/* @Indicate GID frame to IHV service. */\n\t{\n\t\tu8 indibuffer[24] = {0};\n\t\tu8 indioffset = 0;\n\n\t\tPlatformMoveMemory(indibuffer + indioffset, beamform_entry->gid_valid, 8);\n\t\tindioffset += 8;\n\t\tPlatformMoveMemory(indibuffer + indioffset, beamform_entry->user_position, 16);\n\t\tindioffset += 16;\n\n\t\tPlatformIndicateCustomStatus(\n\t\t\tadapter,\n\t\t\tRT_CUSTOM_EVENT_VHT_RECV_GID_MGNT_FRAME,\n\t\t\tRT_CUSTOM_INDI_TARGET_IHV,\n\t\t\tindibuffer,\n\t\t\tindioffset);\n\t}\n\n\t/* @Config HW GID table */\n\thal_com_txbf_config_gtab(dm);\n\n\treturn rt_status;\n}\n\n/*@\n * Description: Construct VHT Group ID (GID) management frame.\n *\n * 2015.05.20. Created by tynli.\n */\nvoid construct_vht_gid_mgnt_frame(\n\tstruct dm_struct *dm,\n\tu8 *RA,\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry,\n\tu8 *buffer,\n\tu32 *p_length\n\n\t)\n{\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);\n\tvoid *adapter = beam_info->source_adapter;\n\tOCTET_STRING os_ftm_frame, tmp;\n\n\tFillOctetString(os_ftm_frame, buffer, 0);\n\t*p_length = 0;\n\n\tConstructMaFrameHdr(\n\t\tadapter,\n\t\tRA,\n\t\tACT_CAT_VHT,\n\t\tACT_VHT_GROUPID_MANAGEMENT,\n\t\t&os_ftm_frame);\n\n\t/* @Membership status array*/\n\tFillOctetString(tmp, beamform_entry->gid_valid, 8);\n\tPacketAppendData(&os_ftm_frame, tmp);\n\n\t/* User Position array*/\n\tFillOctetString(tmp, beamform_entry->user_position, 16);\n\tPacketAppendData(&os_ftm_frame, tmp);\n\n\t*p_length = os_ftm_frame.length;\n\n\tRT_DISP_DATA(FBEAM, FBEAM_DATA, \"construct_vht_gid_mgnt_frame():\\n\", buffer, *p_length);\n}\n\nboolean\nsend_sw_vht_gid_mgnt_frame(\n\tvoid *dm_void,\n\tu8 *RA,\n\tu8 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tPRT_TCB tcb;\n\tPRT_TX_LOCAL_BUFFER p_buf;\n\tboolean ret = true;\n\tu8 data_rate = 0;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry = &beam_info->beamformee_entry[idx];\n\tvoid *adapter = beam_info->source_adapter;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tPlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);\n\n\tif (MgntGetBuffer(adapter, &tcb, &p_buf)) {\n\t\tconstruct_vht_gid_mgnt_frame(\n\t\t\tdm,\n\t\t\tRA,\n\t\t\tbeamform_entry,\n\t\t\tp_buf->Buffer.VirtualAddress,\n\t\t\t&tcb->PacketLength);\n\n\t\ttcb->bw_of_packet = CHANNEL_WIDTH_20;\n\t\tdata_rate = MGN_6M;\n\t\tMgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, data_rate);\n\t} else\n\t\tret = false;\n\n\tPlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);\n\n\tif (ret)\n\t\tRT_DISP_DATA(FBEAM, FBEAM_DATA, \"\", p_buf->Buffer.VirtualAddress, tcb->PacketLength);\n\n\treturn ret;\n}\n\n/*@\n * Description: Construct VHT beamforming report poll.\n *\n * 2015.05.20. Created by tynli.\n */\nvoid construct_vht_bf_report_poll(\n\tstruct dm_struct *dm,\n\tu8 *RA,\n\tu8 *buffer,\n\tu32 *p_length)\n{\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);\n\tvoid *adapter = beam_info->source_adapter;\n\tu8 *p_bf_rpt_poll = buffer;\n\n\t/* @Frame control*/\n\tSET_80211_HDR_FRAME_CONTROL(p_bf_rpt_poll, 0);\n\tSET_80211_HDR_TYPE_AND_SUBTYPE(p_bf_rpt_poll, Type_Beamforming_Report_Poll);\n\n\t/* @duration*/\n\tSET_80211_HDR_DURATION(p_bf_rpt_poll, 100);\n\n\t/* RA*/\n\tSET_VHT_BF_REPORT_POLL_RA(p_bf_rpt_poll, RA);\n\n\t/* TA*/\n\tSET_VHT_BF_REPORT_POLL_TA(p_bf_rpt_poll, adapter->CurrentAddress);\n\n\t/* @Feedback Segment Retransmission Bitmap*/\n\tSET_VHT_BF_REPORT_POLL_FEEDBACK_SEG_RETRAN_BITMAP(p_bf_rpt_poll, 0xFF);\n\n\t*p_length = 17;\n\n\tRT_DISP_DATA(FBEAM, FBEAM_DATA, \"construct_vht_bf_report_poll():\\n\", buffer, *p_length);\n}\n\nboolean\nsend_sw_vht_bf_report_poll(\n\tvoid *dm_void,\n\tu8 *RA,\n\tboolean is_final_poll)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tPRT_TCB tcb;\n\tPRT_TX_LOCAL_BUFFER p_buf;\n\tboolean ret = true;\n\tu8 idx = 0, data_rate = 0;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);\n\tvoid *adapter = beam_info->source_adapter;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tPlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);\n\n\tif (MgntGetBuffer(adapter, &tcb, &p_buf)) {\n\t\tconstruct_vht_bf_report_poll(\n\t\t\tdm,\n\t\t\tRA,\n\t\t\tp_buf->Buffer.VirtualAddress,\n\t\t\t&tcb->PacketLength);\n\n\t\ttcb->bTxEnableSwCalcDur = true; /* @<tynli_note> need?*/\n\t\ttcb->BWOfPacket = CHANNEL_WIDTH_20;\n\n\t\tif (is_final_poll)\n\t\t\ttcb->TxBFPktType = RT_BF_PKT_TYPE_FINAL_BF_REPORT_POLL;\n\t\telse\n\t\t\ttcb->TxBFPktType = RT_BF_PKT_TYPE_BF_REPORT_POLL;\n\n\t\tdata_rate = MGN_6M; /* @Legacy OFDM rate*/\n\t\tMgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, data_rate);\n\t} else\n\t\tret = false;\n\n\tPlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);\n\n\tif (ret)\n\t\tRT_DISP_DATA(FBEAM, FBEAM_DATA, \"send_sw_vht_bf_report_poll:\\n\",\n\t\tp_buf->Buffer.VirtualAddress, tcb->PacketLength);\n\n\treturn ret;\n}\n\n/*@\n * Description: Construct VHT MU NDPA packet.\n *\t<Note> We should combine this function with construct_vht_ndpa_packet() in the future.\n *\n * 2015.05.21. Created by tynli.\n */\nvoid construct_vht_mu_ndpa_packet(\n\tstruct dm_struct *dm,\n\tenum channel_width BW,\n\tu8 *buffer,\n\tu32 *p_length)\n{\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);\n\tvoid *adapter = beam_info->source_adapter;\n\tu16 duration = 0;\n\tu8 sequence = 0;\n\tu8 *p_ndpa_frame = buffer;\n\tstruct _RT_NDPA_STA_INFO sta_info;\n\tu8 idx;\n\tu8 dest_addr[6] = {0};\n\tstruct _RT_BEAMFORMEE_ENTRY *entry = NULL;\n\n\t/* @Fill the first MU BFee entry (STA1) MAC addr to destination address then\n\t     HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */\n\tfor (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {\n\t\tentry = &(beam_info->beamformee_entry[idx]);\n\t\tif (entry->is_mu_sta) {\n\t\t\tcp_mac_addr(dest_addr, entry->mac_addr);\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (entry == NULL)\n\t\treturn;\n\n\t/* @Frame control.*/\n\tSET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0);\n\tSET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA);\n\n\tSET_80211_HDR_ADDRESS1(p_ndpa_frame, dest_addr);\n\tSET_80211_HDR_ADDRESS2(p_ndpa_frame, entry->my_mac_addr);\n\n\t/*@--------------------------------------------*/\n\t/* @<Note> Need to modify \"duration\" to MU consideration. */\n\tduration = 2 * a_SifsTime + 44;\n\n\tif (BW == CHANNEL_WIDTH_80)\n\t\tduration += 40;\n\telse if (BW == CHANNEL_WIDTH_40)\n\t\tduration += 87;\n\telse\n\t\tduration += 180;\n\t/*@--------------------------------------------*/\n\n\tSET_80211_HDR_DURATION(p_ndpa_frame, duration);\n\n\tsequence = *(dm->sounding_seq) << 2;\n\todm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1);\n\n\t*p_length = 17;\n\n\t/* @Construct STA info. for multiple STAs*/\n\tfor (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {\n\t\tentry = &(beam_info->beamformee_entry[idx]);\n\t\tif (entry->is_mu_sta) {\n\t\t\tsta_info.aid = entry->AID;\n\t\t\tsta_info.feedback_type = 1; /* @1'b1: MU*/\n\t\t\tsta_info.nc_index = 0;\n\n\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t  \"[%s] Get beamformee_entry idx(%d), AID =%d\\n\",\n\t\t\t\t  __func__, idx, entry->AID);\n\n\t\t\todm_move_memory(dm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2);\n\t\t\t*p_length += 2;\n\t\t}\n\t}\n}\n\nboolean\nsend_sw_vht_mu_ndpa_packet(\n\tvoid *dm_void,\n\tenum channel_width BW)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tPRT_TCB tcb;\n\tPRT_TX_LOCAL_BUFFER p_buf;\n\tboolean ret = true;\n\tu8 ndp_tx_rate = 0;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);\n\tvoid *adapter = beam_info->source_adapter;\n\n\tndp_tx_rate = MGN_VHT2SS_MCS0;\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] ndp_tx_rate =%d\\n\", __func__,\n\t\t  ndp_tx_rate);\n\n\tPlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);\n\n\tif (MgntGetBuffer(adapter, &tcb, &p_buf)) {\n\t\tconstruct_vht_mu_ndpa_packet(\n\t\t\tdm,\n\t\t\tBW,\n\t\t\tp_buf->Buffer.VirtualAddress,\n\t\t\t&tcb->PacketLength);\n\n\t\ttcb->bTxEnableSwCalcDur = true;\n\t\ttcb->BWOfPacket = BW;\n\t\ttcb->TxBFPktType = RT_BF_PKT_TYPE_BROADCAST_NDPA;\n\n\t\t/*rate of NDP decide by nr*/\n\t\tMgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate);\n\t} else\n\t\tret = false;\n\n\tPlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);\n\n\tif (ret)\n\t\tRT_DISP_DATA(FBEAM, FBEAM_DATA, \"\", p_buf->Buffer.VirtualAddress, tcb->PacketLength);\n\n\treturn ret;\n}\n\nvoid dbg_construct_vht_mundpa_packet(\n\tstruct dm_struct *dm,\n\tenum channel_width BW,\n\tu8 *buffer,\n\tu32 *p_length)\n{\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);\n\tvoid *adapter = beam_info->source_adapter;\n\tu16 duration = 0;\n\tu8 sequence = 0;\n\tu8 *p_ndpa_frame = buffer;\n\tstruct _RT_NDPA_STA_INFO sta_info;\n\tu8 idx;\n\tu8 dest_addr[6] = {0};\n\tstruct _RT_BEAMFORMEE_ENTRY *entry = NULL;\n\n\tboolean is_STA1 = false;\n\n\t/* @Fill the first MU BFee entry (STA1) MAC addr to destination address then\n\t     HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */\n\tfor (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {\n\t\tentry = &(beam_info->beamformee_entry[idx]);\n\t\tif (entry->is_mu_sta) {\n\t\t\tif (is_STA1 == false) {\n\t\t\t\tis_STA1 = true;\n\t\t\t\tcontinue;\n\t\t\t} else {\n\t\t\t\tcp_mac_addr(dest_addr, entry->mac_addr);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* @Frame control.*/\n\tSET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0);\n\tSET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA);\n\n\tSET_80211_HDR_ADDRESS1(p_ndpa_frame, dest_addr);\n\tSET_80211_HDR_ADDRESS2(p_ndpa_frame, dm->CurrentAddress);\n\n\t/*@--------------------------------------------*/\n\t/* @<Note> Need to modify \"duration\" to MU consideration. */\n\tduration = 2 * a_SifsTime + 44;\n\n\tif (BW == CHANNEL_WIDTH_80)\n\t\tduration += 40;\n\telse if (BW == CHANNEL_WIDTH_40)\n\t\tduration += 87;\n\telse\n\t\tduration += 180;\n\t/*@--------------------------------------------*/\n\n\tSET_80211_HDR_DURATION(p_ndpa_frame, duration);\n\n\tsequence = *(dm->sounding_seq) << 2;\n\todm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1);\n\n\t*p_length = 17;\n\n\t/*STA2's STA Info*/\n\tsta_info.aid = entry->aid;\n\tsta_info.feedback_type = 1; /* @1'b1: MU */\n\tsta_info.nc_index = 0;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Get beamformee_entry idx(%d), AID =%d\\n\",\n\t\t  __func__, idx, entry->aid);\n\n\todm_move_memory(dm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2);\n\t*p_length += 2;\n}\n\nboolean\ndbg_send_sw_vht_mundpa_packet(\n\tvoid *dm_void,\n\tenum channel_width BW)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tPRT_TCB tcb;\n\tPRT_TX_LOCAL_BUFFER p_buf;\n\tboolean ret = true;\n\tu8 ndp_tx_rate = 0;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);\n\tvoid *adapter = beam_info->source_adapter;\n\n\tndp_tx_rate = MGN_VHT2SS_MCS0;\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] ndp_tx_rate =%d\\n\", __func__,\n\t\t  ndp_tx_rate);\n\n\tPlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);\n\n\tif (MgntGetBuffer(adapter, &tcb, &p_buf)) {\n\t\tdbg_construct_vht_mundpa_packet(\n\t\t\tdm,\n\t\t\tBW,\n\t\t\tp_buf->Buffer.VirtualAddress,\n\t\t\t&tcb->PacketLength);\n\n\t\ttcb->bTxEnableSwCalcDur = true;\n\t\ttcb->BWOfPacket = BW;\n\t\ttcb->TxBFPktType = RT_BF_PKT_TYPE_UNICAST_NDPA;\n\n\t\t/*rate of NDP decide by nr*/\n\t\tMgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate);\n\t} else\n\t\tret = false;\n\n\tPlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);\n\n\tif (ret)\n\t\tRT_DISP_DATA(FBEAM, FBEAM_DATA, \"\", p_buf->Buffer.VirtualAddress, tcb->PacketLength);\n\n\treturn ret;\n}\n\n#endif /*@#if (SUPPORT_MU_BF == 1)*/\n#endif /*@#ifdef SUPPORT_MU_BF*/\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\nu32 beamforming_get_report_frame(\n\tvoid *dm_void,\n\tunion recv_frame *precv_frame)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu32 ret = _SUCCESS;\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;\n\tu8 *pframe = precv_frame->u.hdr.rx_data;\n\tu32 frame_len = precv_frame->u.hdr.len;\n\tu8 *TA;\n\tu8 idx, offset;\n\n\t/*@Memory comparison to see if CSI report is the same with previous one*/\n\tTA = get_addr2_ptr(pframe);\n\tbeamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, TA, &idx);\n\tif (beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)\n\t\toffset = 31; /*@24+(1+1+3)+2  MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/\n\telse if (beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)\n\t\toffset = 34; /*@24+(1+1+6)+2  MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/\n\telse\n\t\treturn ret;\n\n\treturn ret;\n}\n\nboolean\nsend_fw_ht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tenum channel_width BW)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ADAPTER *adapter = dm->adapter;\n\tstruct xmit_frame *pmgntframe;\n\tstruct pkt_attrib *pattrib;\n\tstruct rtw_ieee80211_hdr *pwlanhdr;\n\tstruct xmit_priv *pxmitpriv = &(adapter->xmitpriv);\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c};\n\tu8 *pframe;\n\tu16 *fctrl;\n\tu16 duration = 0;\n\tu8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\n\tif (pmgntframe == NULL) {\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s, alloc mgnt frame fail\\n\",\n\t\t\t  __func__);\n\t\treturn false;\n\t}\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(adapter, pattrib);\n\n\tpattrib->qsel = QSLT_BEACON;\n\tndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] ndp_tx_rate =%d\\n\", __func__,\n\t\t  ndp_tx_rate);\n\tpattrib->rate = ndp_tx_rate;\n\tpattrib->bwmode = BW;\n\tpattrib->order = 1;\n\tpattrib->subtype = WIFI_ACTION_NOACK;\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &pwlanhdr->frame_ctl;\n\t*(fctrl) = 0;\n\n\tset_order_bit(pframe);\n\tset_frame_sub_type(pframe, WIFI_ACTION_NOACK);\n\n\t_rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\n\tif (pmlmeext->cur_wireless_mode == WIRELESS_11B)\n\t\ta_sifs_time = 10;\n\telse\n\t\ta_sifs_time = 16;\n\n\tduration = 2 * a_sifs_time + 40;\n\n\tif (BW == CHANNEL_WIDTH_40)\n\t\tduration += 87;\n\telse\n\t\tduration += 180;\n\n\tset_duration(pframe, duration);\n\n\t/* @HT control field */\n\tSET_HT_CTRL_CSI_STEERING(pframe + 24, 3);\n\tSET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1);\n\n\t_rtw_memcpy(pframe + 28, action_hdr, 4);\n\n\tpattrib->pktlen = 32;\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(adapter, pmgntframe);\n\n\treturn true;\n}\n\nboolean\nsend_sw_ht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tenum channel_width BW)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ADAPTER *adapter = dm->adapter;\n\tstruct xmit_frame *pmgntframe;\n\tstruct pkt_attrib *pattrib;\n\tstruct rtw_ieee80211_hdr *pwlanhdr;\n\tstruct xmit_priv *pxmitpriv = &(adapter->xmitpriv);\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c};\n\tu8 *pframe;\n\tu16 *fctrl;\n\tu16 duration = 0;\n\tu8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);\n\n\tndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\n\tif (pmgntframe == NULL) {\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s, alloc mgnt frame fail\\n\",\n\t\t\t  __func__);\n\t\treturn false;\n\t}\n\n\t/*update attribute*/\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(adapter, pattrib);\n\tpattrib->qsel = QSLT_MGNT;\n\tpattrib->rate = ndp_tx_rate;\n\tpattrib->bwmode = BW;\n\tpattrib->order = 1;\n\tpattrib->subtype = WIFI_ACTION_NOACK;\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &pwlanhdr->frame_ctl;\n\t*(fctrl) = 0;\n\n\tset_order_bit(pframe);\n\tset_frame_sub_type(pframe, WIFI_ACTION_NOACK);\n\n\t_rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\n\tif (pmlmeext->cur_wireless_mode == WIRELESS_11B)\n\t\ta_sifs_time = 10;\n\telse\n\t\ta_sifs_time = 16;\n\n\tduration = 2 * a_sifs_time + 40;\n\n\tif (BW == CHANNEL_WIDTH_40)\n\t\tduration += 87;\n\telse\n\t\tduration += 180;\n\n\tset_duration(pframe, duration);\n\n\t/*@HT control field*/\n\tSET_HT_CTRL_CSI_STEERING(pframe + 24, 3);\n\tSET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1);\n\n\t_rtw_memcpy(pframe + 28, action_hdr, 4);\n\n\tpattrib->pktlen = 32;\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(adapter, pmgntframe);\n\n\treturn true;\n}\n\nboolean\nsend_fw_vht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tu16 AID,\n\tenum channel_width BW)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ADAPTER *adapter = dm->adapter;\n\tstruct xmit_frame *pmgntframe;\n\tstruct pkt_attrib *pattrib;\n\tstruct rtw_ieee80211_hdr *pwlanhdr;\n\tstruct xmit_priv *pxmitpriv = &(adapter->xmitpriv);\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct mlme_priv *pmlmepriv = &(adapter->mlmepriv);\n\tu8 *pframe;\n\tu16 *fctrl;\n\tu16 duration = 0;\n\tu8 sequence = 0, a_sifs_time = 0, ndp_tx_rate = 0, idx = 0;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);\n\tstruct _RT_NDPA_STA_INFO sta_info;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\n\tif (pmgntframe == NULL) {\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s, alloc mgnt frame fail\\n\",\n\t\t\t  __func__);\n\t\treturn false;\n\t}\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\t_rtw_memcpy(pattrib->ra, RA, ETH_ALEN);\n\tupdate_mgntframe_attrib(adapter, pattrib);\n\n\tpattrib->qsel = QSLT_BEACON;\n\tndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] ndp_tx_rate =%d\\n\", __func__,\n\t\t  ndp_tx_rate);\n\tpattrib->rate = ndp_tx_rate;\n\tpattrib->bwmode = BW;\n\tpattrib->subtype = WIFI_NDPA;\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &pwlanhdr->frame_ctl;\n\t*(fctrl) = 0;\n\n\tset_frame_sub_type(pframe, WIFI_NDPA);\n\n\t_rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN);\n\n\tif (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))\n\t\ta_sifs_time = 16;\n\telse\n\t\ta_sifs_time = 10;\n\n\tduration = 2 * a_sifs_time + 44;\n\n\tif (BW == CHANNEL_WIDTH_80)\n\t\tduration += 40;\n\telse if (BW == CHANNEL_WIDTH_40)\n\t\tduration += 87;\n\telse\n\t\tduration += 180;\n\n\tset_duration(pframe, duration);\n\n\tsequence = beam_info->sounding_sequence << 2;\n\tif (beam_info->sounding_sequence >= 0x3f)\n\t\tbeam_info->sounding_sequence = 0;\n\telse\n\t\tbeam_info->sounding_sequence++;\n\n\t_rtw_memcpy(pframe + 16, &sequence, 1);\n\n\tif (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))\n\t\tAID = 0;\n\n\tsta_info.aid = AID;\n\tsta_info.feedback_type = 0;\n\tsta_info.nc_index = 0;\n\n\t_rtw_memcpy(pframe + 17, (u8 *)&sta_info, 2);\n\n\tpattrib->pktlen = 19;\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(adapter, pmgntframe);\n\n\treturn true;\n}\n\nboolean\nsend_sw_vht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tu16 AID,\n\tenum channel_width BW)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _ADAPTER *adapter = dm->adapter;\n\tstruct xmit_frame *pmgntframe;\n\tstruct pkt_attrib *pattrib;\n\tstruct rtw_ieee80211_hdr *pwlanhdr;\n\tstruct xmit_priv *pxmitpriv = &(adapter->xmitpriv);\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct mlme_priv *pmlmepriv = &(adapter->mlmepriv);\n\tstruct _RT_NDPA_STA_INFO ndpa_sta_info;\n\tu8 ndp_tx_rate = 0, sequence = 0, a_sifs_time = 0, idx = 0;\n\tu8 *pframe;\n\tu16 *fctrl;\n\tu16 duration = 0;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);\n\tstruct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);\n\n\tndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] ndp_tx_rate =%d\\n\", __func__,\n\t\t  ndp_tx_rate);\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\n\tif (pmgntframe == NULL) {\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s, alloc mgnt frame fail\\n\",\n\t\t\t  __func__);\n\t\treturn false;\n\t}\n\n\t/*update attribute*/\n\tpattrib = &pmgntframe->attrib;\n\t_rtw_memcpy(pattrib->ra, RA, ETH_ALEN);\n\tupdate_mgntframe_attrib(adapter, pattrib);\n\tpattrib->qsel = QSLT_MGNT;\n\tpattrib->rate = ndp_tx_rate;\n\tpattrib->bwmode = BW;\n\tpattrib->subtype = WIFI_NDPA;\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &pwlanhdr->frame_ctl;\n\t*(fctrl) = 0;\n\n\tset_frame_sub_type(pframe, WIFI_NDPA);\n\n\t_rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN);\n\n\tif (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))\n\t\ta_sifs_time = 16;\n\telse\n\t\ta_sifs_time = 10;\n\n\tduration = 2 * a_sifs_time + 44;\n\n\tif (BW == CHANNEL_WIDTH_80)\n\t\tduration += 40;\n\telse if (BW == CHANNEL_WIDTH_40)\n\t\tduration += 87;\n\telse\n\t\tduration += 180;\n\n\tset_duration(pframe, duration);\n\n\tsequence = beam_info->sounding_sequence << 2;\n\tif (beam_info->sounding_sequence >= 0x3f)\n\t\tbeam_info->sounding_sequence = 0;\n\telse\n\t\tbeam_info->sounding_sequence++;\n\n\t_rtw_memcpy(pframe + 16, &sequence, 1);\n\tif (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))\n\t\tAID = 0;\n\n\tndpa_sta_info.aid = AID;\n\tndpa_sta_info.feedback_type = 0;\n\tndpa_sta_info.nc_index = 0;\n\n\t_rtw_memcpy(pframe + 17, (u8 *)&ndpa_sta_info, 2);\n\n\tpattrib->pktlen = 19;\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(adapter, pmgntframe);\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] [%d]\\n\", __func__, __LINE__);\n\n\treturn true;\n}\n\n#endif\n\nvoid beamforming_get_ndpa_frame(\n\tvoid *dm_void,\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tOCTET_STRING pdu_os\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tunion recv_frame *precv_frame\n#endif\n\t)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 *TA;\n\tu8 idx, sequence;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tu8 *p_ndpa_frame = pdu_os.Octet;\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tu8 *p_ndpa_frame = precv_frame->u.hdr.rx_data;\n#endif\n\tstruct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL; /*@Modified By Jeffery @2014-10-29*/\n\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tRT_DISP_DATA(FBEAM, FBEAM_DATA, \"beamforming_get_ndpa_frame\\n\",\n\tpdu_os.Octet, pdu_os.Length);\n\tif (IsCtrlNDPA(p_ndpa_frame) == false)\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tif (get_frame_sub_type(p_ndpa_frame) != WIFI_NDPA)\n#endif\n\t\treturn;\n\telse if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))) {\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] not 8812 or 8821A, return\\n\",\n\t\t\t  __func__);\n\t\treturn;\n\t}\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tTA = Frame_Addr2(pdu_os);\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tTA = get_addr2_ptr(p_ndpa_frame);\n#endif\n\t/*Remove signaling TA. */\n\tTA[0] = TA[0] & 0xFE;\n\n\tbeamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, TA, &idx); /* @Modified By Jeffery @2014-10-29 */\n\n\t/*@Break options for Clock Reset*/\n\tif (beamformer_entry == NULL)\n\t\treturn;\n\telse if (!(beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU))\n\t\treturn;\n\t/*@log_success: As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is NO LONGER needed !2015-04-10, Jeffery*/\n\t/*@clock_reset_times: While BFer entry always doesn't receive our CSI, clock will reset again and again.So clock_reset_times is limited to 5 times.2015-04-13, Jeffery*/\n\telse if ((beamformer_entry->log_success == 1) || (beamformer_entry->clock_reset_times == 5)) {\n\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t  \"[%s] log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, log_success=%d, clock_reset_times=%d, clock reset is no longer needed.\\n\",\n\t\t\t  __func__, beamformer_entry->log_seq,\n\t\t\t  beamformer_entry->pre_log_seq,\n\t\t\t  beamformer_entry->log_retry_cnt,\n\t\t\t  beamformer_entry->log_success,\n\t\t\t  beamformer_entry->clock_reset_times);\n\n\t\treturn;\n\t}\n\n\tsequence = (p_ndpa_frame[16]) >> 2;\n\n\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t  \"[%s] Start, sequence=%d, log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, clock_reset_times=%d, log_success=%d\\n\",\n\t\t  __func__, sequence, beamformer_entry->log_seq,\n\t\t  beamformer_entry->pre_log_seq,\n\t\t  beamformer_entry->log_retry_cnt,\n\t\t  beamformer_entry->clock_reset_times,\n\t\t  beamformer_entry->log_success);\n\n\tif (beamformer_entry->log_seq != 0 && beamformer_entry->pre_log_seq != 0) {\n\t\t/*Success condition*/\n\t\tif (beamformer_entry->log_seq != sequence && beamformer_entry->pre_log_seq != beamformer_entry->log_seq) {\n\t\t\t/* @break option for clcok reset, 2015-03-30, Jeffery */\n\t\t\tbeamformer_entry->log_retry_cnt = 0;\n\t\t\t/*@As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is no longer needed.*/\n\t\t\t/*That is, log_success is NOT needed to be reset to zero, 2015-04-13, Jeffery*/\n\t\t\tbeamformer_entry->log_success = 1;\n\n\t\t} else { /*@Fail condition*/\n\n\t\t\tif (beamformer_entry->log_retry_cnt == 5) {\n\t\t\t\tbeamformer_entry->clock_reset_times++;\n\t\t\t\tbeamformer_entry->log_retry_cnt = 0;\n\n\t\t\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t\t\t  \"[%s] Clock Reset!!! clock_reset_times=%d\\n\",\n\t\t\t\t\t  __func__,\n\t\t\t\t\t  beamformer_entry->clock_reset_times);\n\t\t\t\thal_com_txbf_set(dm, TXBF_SET_SOUNDING_CLK, NULL);\n\n\t\t\t} else\n\t\t\t\tbeamformer_entry->log_retry_cnt++;\n\t\t}\n\t}\n\n\t/*Update log_seq & pre_log_seq*/\n\tbeamformer_entry->pre_log_seq = beamformer_entry->log_seq;\n\tbeamformer_entry->log_seq = sequence;\n}\n\n#endif\n"
  },
  {
    "path": "hal/phydm/txbf/haltxbfinterface.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#ifndef __HAL_TXBF_INTERFACE_H__\n#define __HAL_TXBF_INTERFACE_H__\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\n#define a_SifsTime ((IS_WIRELESS_MODE_5G(adapter) || IS_WIRELESS_MODE_N_24G(adapter)) ? 16 : 10)\n\nvoid beamforming_gid_paid(\n\tvoid *adapter,\n\tPRT_TCB tcb);\n\nenum rt_status\nbeamforming_get_report_frame(\n\tvoid *adapter,\n\tPRT_RFD rfd,\n\tPOCTET_STRING p_pdu_os);\n\nvoid beamforming_get_ndpa_frame(\n\tvoid *dm_void,\n\tOCTET_STRING pdu_os);\n\nboolean\nsend_fw_ht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tenum channel_width BW);\n\nboolean\nsend_fw_vht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tu16 AID,\n\tenum channel_width BW);\n\nboolean\nsend_sw_vht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tu16 AID,\n\tenum channel_width BW);\n\nboolean\nsend_sw_ht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tenum channel_width BW);\n\n#if (SUPPORT_MU_BF == 1)\nenum rt_status\nbeamforming_get_vht_gid_mgnt_frame(\n\tvoid *adapter,\n\tPRT_RFD rfd,\n\tPOCTET_STRING p_pdu_os);\n\nboolean\nsend_sw_vht_gid_mgnt_frame(\n\tvoid *dm_void,\n\tu8 *RA,\n\tu8 idx);\n\nboolean\nsend_sw_vht_bf_report_poll(\n\tvoid *dm_void,\n\tu8 *RA,\n\tboolean is_final_poll);\n\nboolean\nsend_sw_vht_mu_ndpa_packet(\n\tvoid *dm_void,\n\tenum channel_width BW);\n#else\n#define beamforming_get_vht_gid_mgnt_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE\n#define send_sw_vht_gid_mgnt_frame(dm_void, RA)\n#define send_sw_vht_bf_report_poll(dm_void, RA, is_final_poll)\n#define send_sw_vht_mu_ndpa_packet(dm_void, BW)\n#endif\n\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\nu32 beamforming_get_report_frame(\n\tvoid *dm_void,\n\tunion recv_frame *precv_frame);\n\nboolean\nsend_fw_ht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tenum channel_width BW);\n\nboolean\nsend_sw_ht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tenum channel_width BW);\n\nboolean\nsend_fw_vht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tu16 AID,\n\tenum channel_width BW);\n\nboolean\nsend_sw_vht_ndpa_packet(\n\tvoid *dm_void,\n\tu8 *RA,\n\tu16 AID,\n\tenum channel_width BW);\n#endif\n\nvoid beamforming_get_ndpa_frame(\n\tvoid *dm_void,\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tOCTET_STRING pdu_os\n#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\n\tunion recv_frame *precv_frame\n#endif\n\t);\n\nboolean\ndbg_send_sw_vht_mundpa_packet(\n\tvoid *dm_void,\n\tenum channel_width BW);\n\n#else\n#define beamforming_get_ndpa_frame(dm, _pdu_os)\n#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\n#define beamforming_get_report_frame(adapter, precv_frame) RT_STATUS_FAILURE\n#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n#define beamforming_get_report_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE\n#define beamforming_get_vht_gid_mgnt_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE\n#endif\n#define send_fw_ht_ndpa_packet(dm_void, RA, BW)\n#define send_sw_ht_ndpa_packet(dm_void, RA, BW)\n#define send_fw_vht_ndpa_packet(dm_void, RA, AID, BW)\n#define send_sw_vht_ndpa_packet(dm_void, RA, AID, BW)\n#define send_sw_vht_gid_mgnt_frame(dm_void, RA, idx)\n#define send_sw_vht_bf_report_poll(dm_void, RA, is_final_poll)\n#define send_sw_vht_mu_ndpa_packet(dm_void, BW)\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/phydm/txbf/haltxbfjaguar.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n/*************************************************************\n * Description:\n *\n * This file is for 8812/8821/8811 TXBF mechanism\n *\n ************************************************************/\n#include \"mp_precomp.h\"\n#include \"../phydm_precomp.h\"\n\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))\nvoid hal_txbf_8812a_set_ndpa_rate(\n\tvoid *dm_void,\n\tu8 BW,\n\tu8 rate)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\todm_write_1byte(dm, REG_NDPA_OPT_CTRL_8812A, (rate << 2 | BW));\n}\n\nvoid hal_txbf_jaguar_rf_mode(\n\tvoid *dm_void,\n\tstruct _RT_BEAMFORMING_INFO *beam_info)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tif (dm->rf_type == RF_1T1R)\n\t\treturn;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] set TxIQGen\\n\", __func__);\n\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1); /*RF mode table write enable*/\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1); /*RF mode table write enable*/\n\n\tif (beam_info->beamformee_su_cnt > 0) {\n\t\t/* Paath_A */\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0x78000, 0x3); /*Select RX mode*/\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in RX mode*/\n\t\t/* Path_B */\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0x78000, 0x3); /*Select RX mode*/\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in RX mode*/\n\t} else {\n\t\t/* Paath_A */\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0x78000, 0x3); /*Select RX mode*/\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/\n\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0xC26BF); /*@Disable TXIQGEN in RX mode*/\n\t\t/* Path_B */\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0x78000, 0x3); /*Select RX mode*/\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/\n\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0xC26BF); /*@Disable TXIQGEN in RX mode*/\n\t}\n\n\todm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0); /*RF mode table write disable*/\n\todm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0); /*RF mode table write disable*/\n\n\tif (beam_info->beamformee_su_cnt > 0)\n\t\todm_set_bb_reg(dm, R_0x80c, MASKBYTE1, 0x33);\n\telse\n\t\todm_set_bb_reg(dm, R_0x80c, MASKBYTE1, 0x11);\n}\n\nvoid hal_txbf_jaguar_download_ndpa(\n\tvoid *dm_void,\n\tu8 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 u1b_tmp = 0, tmp_reg422 = 0, head_page;\n\tu8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;\n\tboolean is_send_beacon = false;\n\tu8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*@default reseved 1 page for the IC type which is undefined.*/\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;\n\tvoid *adapter = dm->adapter;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t*dm->is_fw_dw_rsvd_page_in_progress = true;\n#endif\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tif (idx == 0)\n\t\thead_page = 0xFE;\n\telse\n\t\thead_page = 0xFE;\n\n\tphydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy);\n\n\t/*Set REG_CR bit 8. DMA beacon by SW.*/\n\tu1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1);\n\todm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp | BIT(0)));\n\n\t/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/\n\ttmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2);\n\todm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422 & (~BIT(6)));\n\n\tif (tmp_reg422 & BIT(6)) {\n\t\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t\t  \"SetBeamformDownloadNDPA_8812(): There is an adapter is sending beacon.\\n\");\n\t\tis_send_beacon = true;\n\t}\n\n\t/*TDECTRL[15:8] 0x209[7:0] = 0xF6\tBeacon Head for TXDMA*/\n\todm_write_1byte(dm, REG_TDECTRL_8812A + 1, head_page);\n\n\tdo {\n\t\t/*@Clear beacon valid check bit.*/\n\t\tbcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2);\n\t\todm_write_1byte(dm, REG_TDECTRL_8812A + 2, (bcn_valid_reg | BIT(0)));\n\n\t\t/*@download NDPA rsvd page.*/\n\t\tif (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)\n\t\t\tbeamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->aid, p_beam_entry->sound_bw, BEACON_QUEUE);\n\t\telse\n\t\t\tbeamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);\n\n\t\t/*@check rsvd page download OK.*/\n\t\tbcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2);\n\t\tcount = 0;\n\t\twhile (!(bcn_valid_reg & BIT(0)) && count < 20) {\n\t\t\tcount++;\n\t\t\tODM_delay_ms(10);\n\t\t\tbcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2);\n\t\t}\n\t\tdl_bcn_count++;\n\t} while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5);\n\n\tif (!(bcn_valid_reg & BIT(0)))\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"%s Download RSVD page failed!\\n\",\n\t\t\t  __func__);\n\n\t/*TDECTRL[15:8] 0x209[7:0] = 0xF6\tBeacon Head for TXDMA*/\n\todm_write_1byte(dm, REG_TDECTRL_8812A + 1, tx_page_bndy);\n\n\t/*To make sure that if there exists an adapter which would like to send beacon.*/\n\t/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/\n\t/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/\n\t/*the beacon cannot be sent by HW.*/\n\t/*@2010.06.23. Added by tynli.*/\n\tif (is_send_beacon)\n\t\todm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422);\n\n\t/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/\n\t/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/\n\tu1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1);\n\todm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp & (~BIT(0))));\n\n\tp_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\t*dm->is_fw_dw_rsvd_page_in_progress = false;\n#endif\n}\n\nvoid hal_txbf_jaguar_fw_txbf_cmd(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 idx, period0 = 0, period1 = 0;\n\tu8 PageNum0 = 0xFF, PageNum1 = 0xFF;\n\tu8 u1_tx_bf_parm[3] = {0};\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\n\tfor (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {\n\t\t/*@Modified by David*/\n\t\tif (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {\n\t\t\tif (idx == 0) {\n\t\t\t\tif (beam_info->beamformee_entry[idx].is_sound)\n\t\t\t\t\tPageNum0 = 0xFE;\n\t\t\t\telse\n\t\t\t\t\tPageNum0 = 0xFF; /*stop sounding*/\n\t\t\t\tperiod0 = (u8)(beam_info->beamformee_entry[idx].sound_period);\n\t\t\t} else if (idx == 1) {\n\t\t\t\tif (beam_info->beamformee_entry[idx].is_sound)\n\t\t\t\t\tPageNum1 = 0xFE;\n\t\t\t\telse\n\t\t\t\t\tPageNum1 = 0xFF; /*stop sounding*/\n\t\t\t\tperiod1 = (u8)(beam_info->beamformee_entry[idx].sound_period);\n\t\t\t}\n\t\t}\n\t}\n\n\tu1_tx_bf_parm[0] = PageNum0;\n\tu1_tx_bf_parm[1] = PageNum1;\n\tu1_tx_bf_parm[2] = (period1 << 4) | period0;\n\todm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);\n\n\tPHYDM_DBG(dm, DBG_TXBF,\n\t\t  \"[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\\n\",\n\t\t  __func__, PageNum0, period0, PageNum1, period1);\n}\n\nvoid hal_txbf_jaguar_enter(\n\tvoid *dm_void,\n\tu8 bfer_bfee_idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i = 0;\n\tu8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;\n\tu8 bfee_idx = (bfer_bfee_idx & 0xF);\n\tu32 csi_param;\n\tstruct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY beamformee_entry;\n\tstruct _RT_BEAMFORMER_ENTRY beamformer_entry;\n\tu16 sta_id = 0;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s]Start!\\n\", __func__);\n\n\thal_txbf_jaguar_rf_mode(dm, beamforming_info);\n\n\tif (dm->rf_type == RF_2T2R)\n\t\todm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x00000000); /*nc =2*/\n\telse\n\t\todm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x01081008); /*nc =1*/\n\n\tif (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {\n\t\tbeamformer_entry = beamforming_info->beamformer_entry[bfer_idx];\n\n\t\t/*Sounding protocol control*/\n\t\todm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xCB);\n\n\t\t/*@MAC address/Partial AID of Beamformer*/\n\t\tif (bfer_idx == 0) {\n\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\todm_write_1byte(dm, (REG_BFMER0_INFO_8812A + i), beamformer_entry.mac_addr[i]);\n\t\t\t/*@CSI report use legacy ofdm so don't need to fill P_AID. */\n\t\t\t/*platform_efio_write_2byte(adapter, REG_BFMER0_INFO_8812A+6, beamform_entry.P_AID); */\n\t\t} else {\n\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\todm_write_1byte(dm, (REG_BFMER1_INFO_8812A + i), beamformer_entry.mac_addr[i]);\n\t\t\t/*@CSI report use legacy ofdm so don't need to fill P_AID.*/\n\t\t\t/*platform_efio_write_2byte(adapter, REG_BFMER1_INFO_8812A+6, beamform_entry.P_AID);*/\n\t\t}\n\n\t\t/*@CSI report parameters of Beamformee*/\n\t\tif (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) {\n\t\t\tif (dm->rf_type == RF_2T2R)\n\t\t\t\tcsi_param = 0x01090109;\n\t\t\telse\n\t\t\t\tcsi_param = 0x01080108;\n\t\t} else {\n\t\t\tif (dm->rf_type == RF_2T2R)\n\t\t\t\tcsi_param = 0x03090309;\n\t\t\telse\n\t\t\t\tcsi_param = 0x03080308;\n\t\t}\n\n\t\todm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, csi_param);\n\t\todm_write_4byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, csi_param);\n\t\todm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, csi_param);\n\n\t\t/*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us,  MP chip)*/\n\t\todm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A + 3, 0x50);\n\t}\n\n\tif (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {\n\t\tbeamformee_entry = beamforming_info->beamformee_entry[bfee_idx];\n\n\t\tif (phydm_acting_determine(dm, phydm_acting_as_ibss))\n\t\t\tsta_id = beamformee_entry.mac_id;\n\t\telse\n\t\t\tsta_id = beamformee_entry.p_aid;\n\n\t\t/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/\n\t\tif (bfee_idx == 0) {\n\t\t\todm_write_2byte(dm, REG_TXBF_CTRL_8812A, sta_id);\n\t\t\todm_write_1byte(dm, REG_TXBF_CTRL_8812A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8812A + 3) | BIT(4) | BIT(6) | BIT(7));\n\t\t} else\n\t\t\todm_write_2byte(dm, REG_TXBF_CTRL_8812A + 2, sta_id | BIT(12) | BIT(14) | BIT(15));\n\n\t\t/*@CSI report parameters of Beamformee*/\n\t\tif (bfee_idx == 0) {\n\t\t\t/*@Get BIT24 & BIT25*/\n\t\t\tu8 tmp = odm_read_1byte(dm, REG_BFMEE_SEL_8812A + 3) & 0x3;\n\n\t\t\todm_write_1byte(dm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60);\n\t\t\todm_write_2byte(dm, REG_BFMEE_SEL_8812A, sta_id | BIT(9));\n\t\t} else {\n\t\t\t/*Set BIT25*/\n\t\t\todm_write_2byte(dm, REG_BFMEE_SEL_8812A + 2, sta_id | 0xE200);\n\t\t}\n\t\tphydm_beamforming_notify(dm);\n\t}\n}\n\nvoid hal_txbf_jaguar_leave(\n\tvoid *dm_void,\n\tu8 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMER_ENTRY beamformer_entry;\n\tstruct _RT_BEAMFORMEE_ENTRY beamformee_entry;\n\n\tif (idx < BEAMFORMER_ENTRY_NUM) {\n\t\tbeamformer_entry = beamforming_info->beamformer_entry[idx];\n\t\tbeamformee_entry = beamforming_info->beamformee_entry[idx];\n\t} else\n\t\treturn;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s]Start!, IDx = %d\\n\", __func__, idx);\n\n\t/*@Clear P_AID of Beamformee*/\n\t/*@Clear MAC address of Beamformer*/\n\t/*@Clear Associated Bfmee Sel*/\n\n\tif (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {\n\t\todm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xC8);\n\t\tif (idx == 0) {\n\t\t\todm_write_4byte(dm, REG_BFMER0_INFO_8812A, 0);\n\t\t\todm_write_2byte(dm, REG_BFMER0_INFO_8812A + 4, 0);\n\t\t\todm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, 0);\n\t\t\todm_write_2byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, 0);\n\t\t\todm_write_2byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, 0);\n\t\t} else {\n\t\t\todm_write_4byte(dm, REG_BFMER1_INFO_8812A, 0);\n\t\t\todm_write_2byte(dm, REG_BFMER1_INFO_8812A + 4, 0);\n\t\t\todm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, 0);\n\t\t\todm_write_2byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, 0);\n\t\t\todm_write_2byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, 0);\n\t\t}\n\t}\n\n\tif (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {\n\t\thal_txbf_jaguar_rf_mode(dm, beamforming_info);\n\t\tif (idx == 0) {\n\t\t\todm_write_2byte(dm, REG_TXBF_CTRL_8812A, 0x0);\n\t\t\todm_write_2byte(dm, REG_BFMEE_SEL_8812A, 0);\n\t\t} else {\n\t\t\todm_write_2byte(dm, REG_TXBF_CTRL_8812A + 2, odm_read_2byte(dm, REG_TXBF_CTRL_8812A + 2) & 0xF000);\n\t\t\todm_write_2byte(dm, REG_BFMEE_SEL_8812A + 2, odm_read_2byte(dm, REG_BFMEE_SEL_8812A + 2) & 0x60);\n\t\t}\n\t}\n}\n\nvoid hal_txbf_jaguar_status(\n\tvoid *dm_void,\n\tu8 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu16 beam_ctrl_val;\n\tu32 beam_ctrl_reg;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx];\n\n\tif (phydm_acting_determine(dm, phydm_acting_as_ibss))\n\t\tbeam_ctrl_val = beamform_entry.mac_id;\n\telse\n\t\tbeam_ctrl_val = beamform_entry.p_aid;\n\n\tif (idx == 0)\n\t\tbeam_ctrl_reg = REG_TXBF_CTRL_8812A;\n\telse {\n\t\tbeam_ctrl_reg = REG_TXBF_CTRL_8812A + 2;\n\t\tbeam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);\n\t}\n\n\tif (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beam_info->apply_v_matrix == true) {\n\t\tif (beamform_entry.sound_bw == CHANNEL_WIDTH_20)\n\t\t\tbeam_ctrl_val |= BIT(9);\n\t\telse if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)\n\t\t\tbeam_ctrl_val |= (BIT(9) | BIT(10));\n\t\telse if (beamform_entry.sound_bw == CHANNEL_WIDTH_80)\n\t\t\tbeam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));\n\t} else\n\t\tbeam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] beam_ctrl_val = 0x%x!\\n\", __func__,\n\t\t  beam_ctrl_val);\n\n\todm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);\n}\n\nvoid hal_txbf_jaguar_fw_txbf(\n\tvoid *dm_void,\n\tu8 idx)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\tstruct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tif (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)\n\t\thal_txbf_jaguar_download_ndpa(dm, idx);\n\n\thal_txbf_jaguar_fw_txbf_cmd(dm);\n}\n\nvoid hal_txbf_jaguar_patch(\n\tvoid *dm_void,\n\tu8 operation)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tif (beam_info->beamform_cap == BEAMFORMING_CAP_NONE)\n\t\treturn;\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tif (operation == SCAN_OPT_BACKUP_BAND0)\n\t\todm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xC8);\n\telse if (operation == SCAN_OPT_RESTORE)\n\t\todm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xCB);\n#endif\n}\n\nvoid hal_txbf_jaguar_clk_8812a(\n\tvoid *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu16 u2btmp;\n\tu8 count = 0, u1btmp;\n\tvoid *adapter = dm->adapter;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] Start!\\n\", __func__);\n\n\tif (*dm->is_scan_in_process) {\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] return by Scan\\n\", __func__);\n\t\treturn;\n\t}\n#if DEV_BUS_TYPE == RT_PCI_INTERFACE\n\t/*Stop PCIe TxDMA*/\n\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\todm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE);\n#endif\n\n/*Stop Usb TxDMA*/\n#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\n\tRT_DISABLE_FUNC((PADAPTER)adapter, DF_TX_BIT);\n\tPlatformReturnAllPendingTxPackets(adapter);\n#else\n\trtw_write_port_cancel(adapter);\n#endif\n\n\t/*Wait TXFF empty*/\n\tfor (count = 0; count < 100; count++) {\n\t\tu2btmp = odm_read_2byte(dm, REG_TXPKT_EMPTY_8812A);\n\t\tu2btmp = u2btmp & 0xfff;\n\t\tif (u2btmp != 0xfff) {\n\t\t\tODM_delay_ms(10);\n\t\t\tcontinue;\n\t\t} else\n\t\t\tbreak;\n\t}\n\n\t/*TX pause*/\n\todm_write_1byte(dm, REG_TXPAUSE_8812A, 0xFF);\n\n\t/*Wait TX state Machine OK*/\n\tfor (count = 0; count < 100; count++) {\n\t\tif (odm_read_4byte(dm, REG_SCH_TXCMD_8812A) != 0)\n\t\t\tcontinue;\n\t\telse\n\t\t\tbreak;\n\t}\n\n\t/*Stop RX DMA path*/\n\tu1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A);\n\todm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT(2));\n\n\tfor (count = 0; count < 100; count++) {\n\t\tu1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A);\n\t\tif (u1btmp & BIT(1))\n\t\t\tbreak;\n\t\telse\n\t\t\tODM_delay_ms(10);\n\t}\n\n\t/*@Disable clock*/\n\todm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xf0);\n\t/*@Disable 320M*/\n\todm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0x8);\n\t/*@Enable 320M*/\n\todm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0xa);\n\t/*@Enable clock*/\n\todm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xfc);\n\n\t/*Release Tx pause*/\n\todm_write_1byte(dm, REG_TXPAUSE_8812A, 0);\n\n\t/*@Enable RX DMA path*/\n\tu1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A);\n\todm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT(2)));\n#if DEV_BUS_TYPE == RT_PCI_INTERFACE\n\t/*@Enable PCIe TxDMA*/\n\tif (dm->support_interface == ODM_ITRF_PCIE)\n\t\todm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0);\n#endif\n\t/*Start Usb TxDMA*/\n\tRT_ENABLE_FUNC((PADAPTER)adapter, DF_TX_BIT);\n}\n\n#endif\n\n#endif\n"
  },
  {
    "path": "hal/phydm/txbf/haltxbfjaguar.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#ifndef __HAL_TXBF_JAGUAR_H__\n#define __HAL_TXBF_JAGUAR_H__\n#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))\n#ifdef PHYDM_BEAMFORMING_SUPPORT\n\nvoid hal_txbf_8812a_set_ndpa_rate(\n\tvoid *dm_void,\n\tu8 BW,\n\tu8 rate);\n\nvoid hal_txbf_jaguar_enter(\n\tvoid *dm_void,\n\tu8 idx);\n\nvoid hal_txbf_jaguar_leave(\n\tvoid *dm_void,\n\tu8 idx);\n\nvoid hal_txbf_jaguar_status(\n\tvoid *dm_void,\n\tu8 idx);\n\nvoid hal_txbf_jaguar_fw_txbf(\n\tvoid *dm_void,\n\tu8 idx);\n\nvoid hal_txbf_jaguar_patch(\n\tvoid *dm_void,\n\tu8 operation);\n\nvoid hal_txbf_jaguar_clk_8812a(\n\tvoid *dm_void);\n#else\n\n#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate)\n#define hal_txbf_jaguar_enter(dm_void, idx)\n#define hal_txbf_jaguar_leave(dm_void, idx)\n#define hal_txbf_jaguar_status(dm_void, idx)\n#define hal_txbf_jaguar_fw_txbf(dm_void, idx)\n#define hal_txbf_jaguar_patch(dm_void, operation)\n#define hal_txbf_jaguar_clk_8812a(dm_void)\n#endif\n#else\n\n#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate)\n#define hal_txbf_jaguar_enter(dm_void, idx)\n#define hal_txbf_jaguar_leave(dm_void, idx)\n#define hal_txbf_jaguar_status(dm_void, idx)\n#define hal_txbf_jaguar_fw_txbf(dm_void, idx)\n#define hal_txbf_jaguar_patch(dm_void, operation)\n#define hal_txbf_jaguar_clk_8812a(dm_void)\n#endif\n\n#endif /*  @#ifndef __HAL_TXBF_JAGUAR_H__ */\n"
  },
  {
    "path": "hal/phydm/txbf/phydm_hal_txbf_api.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include \"mp_precomp.h\"\n#include \"phydm_precomp.h\"\n\n#if (defined(CONFIG_BB_TXBF_API))\n#if (RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1 ||\\\n\tRTL8822C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 || RTL8814B_SUPPORT == 1)\n/*@Add by YuChen for 8822B MU-MIMO API*/\n\n/*this function is only used for BFer*/\nu8 phydm_get_ndpa_rate(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 ndpa_rate = ODM_RATE6M;\n\n\tif (dm->rssi_min >= 30) /*@link RSSI > 30%*/\n\t\tndpa_rate = ODM_RATE24M;\n\telse if (dm->rssi_min <= 25)\n\t\tndpa_rate = ODM_RATE6M;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] ndpa_rate = 0x%x\\n\", __func__, ndpa_rate);\n\n\treturn ndpa_rate;\n}\n\n/*this function is only used for BFer*/\nu8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput,\n\t\t\t\t       u8 total_bfee_num, u8 *tx_rate)\n{\n\tu8 idx = 0;\n\tu8 snddecision = 0xff;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\tfor (idx = 0; idx < total_bfee_num; idx++) {\n\t\tif (dm->support_ic_type & (ODM_RTL8814A)) {\n\t\t\tif ((tx_rate[idx] >= ODM_RATEVHTSS3MCS7 &&\n\t\t\t     tx_rate[idx] <= ODM_RATEVHTSS3MCS9))\n\t\t\t\tsnddecision = snddecision & ~(1 << idx);\n\t\t} else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8822C |\n\t\t\t   ODM_RTL8812 | ODM_RTL8192F)) {\n\t\t\tif ((tx_rate[idx] >= ODM_RATEVHTSS2MCS7 &&\n\t\t\t     tx_rate[idx] <= ODM_RATEVHTSS2MCS9))\n\t\t\t\tsnddecision = snddecision & ~(1 << idx);\n\t\t} else if (dm->support_ic_type & (ODM_RTL8814B)) {\n\t\t\tif ((tx_rate[idx] >= ODM_RATEVHTSS4MCS7 &&\n\t\t\t     tx_rate[idx] <= ODM_RATEVHTSS4MCS9))\n\t\t\t\tsnddecision = snddecision & ~(1 << idx);\n\t\t}\n\t}\n\n\tfor (idx = 0; idx < total_bfee_num; idx++) {\n\t\tif (throughput[idx] <= 10)\n\t\t\tsnddecision = snddecision & ~(1 << idx);\n\t}\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] soundingdecision = 0x%x\\n\", __func__,\n\t\t  snddecision);\n\n\treturn snddecision;\n}\n\n/*this function is only used for BFer*/\nu8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput)\n{\n\tu8 snding_score = 0;\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\t/*throughput unit is Mbps*/\n\tif (throughput >= 500)\n\t\tsnding_score = 100;\n\telse if (throughput >= 450)\n\t\tsnding_score = 90;\n\telse if (throughput >= 400)\n\t\tsnding_score = 80;\n\telse if (throughput >= 350)\n\t\tsnding_score = 70;\n\telse if (throughput >= 300)\n\t\tsnding_score = 60;\n\telse if (throughput >= 250)\n\t\tsnding_score = 50;\n\telse if (throughput >= 200)\n\t\tsnding_score = 40;\n\telse if (throughput >= 150)\n\t\tsnding_score = 30;\n\telse if (throughput >= 100)\n\t\tsnding_score = 20;\n\telse if (throughput >= 50)\n\t\tsnding_score = 10;\n\telse\n\t\tsnding_score = 0;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[%s] snding_score = 0x%x\\n\", __func__,\n\t\t  snding_score);\n\n\treturn snding_score;\n}\n\n#endif\n#if (DM_ODM_SUPPORT_TYPE != ODM_AP)\nu8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 nr_index = 0;\n\tu8 ndp_tx_rate;\n/*@Find nr*/\n#if (RTL8814A_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8814A)\n\t\tnr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num);\n\telse\n#endif\n\t\tnr_index = tx_bf_nr(1, bfer_str_num);\n\n\tswitch (nr_index) {\n\tcase 1:\n\t\tndp_tx_rate = ODM_MGN_MCS8;\n\t\tbreak;\n\n\tcase 2:\n\t\tndp_tx_rate = ODM_MGN_MCS16;\n\t\tbreak;\n\n\tcase 3:\n\t\tndp_tx_rate = ODM_MGN_MCS24;\n\t\tbreak;\n\n\tdefault:\n\t\tndp_tx_rate = ODM_MGN_MCS8;\n\t\tbreak;\n\t}\n\n\treturn ndp_tx_rate;\n}\n\nu8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 nr_index = 0;\n\tu8 ndp_tx_rate;\n/*@Find nr*/\n#if (RTL8814A_SUPPORT == 1)\n\tif (dm->support_ic_type & ODM_RTL8814A)\n\t\tnr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num);\n\telse\n#endif\n\t\tnr_index = tx_bf_nr(1, bfer_str_num);\n\n\tswitch (nr_index) {\n\tcase 1:\n\t\tndp_tx_rate = ODM_MGN_VHT2SS_MCS0;\n\t\tbreak;\n\n\tcase 2:\n\t\tndp_tx_rate = ODM_MGN_VHT3SS_MCS0;\n\t\tbreak;\n\n\tcase 3:\n\t\tndp_tx_rate = ODM_MGN_VHT4SS_MCS0;\n\t\tbreak;\n\n\tdefault:\n\t\tndp_tx_rate = ODM_MGN_VHT2SS_MCS0;\n\t\tbreak;\n\t}\n\n\treturn ndp_tx_rate;\n}\n#endif\n\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n/*this function is only used for BFer*/\nvoid phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i;\n\n\tif (dm->rf_type == RF_1T1R)\n\t\treturn;\n#if (RTL8822C_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8822C) {\n\t\tif (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {\n\t\t\t/*Path A ==================*/\n\t\t\t/*RF mode table write enable*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x1);\n\t\t\t/*Select RX mode*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x33, 0xF, 3);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, 0x3, 0x2);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0xfffff,\n\t\t\t\t       0x65AFF);\n\t\t\t/*RF mode table write disable*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x0);\n\n\t\t\t/*Path B ==================*/\n\t\t\t/*RF mode table write enable*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x1);\n\t\t\t/*Select RX mode*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0xF, 3);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, 0xfffff,\n\t\t\t\t       0x996BF);\n\t\t\t/*Select Standby mode*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0xF, 1);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, 0xfffff,\n\t\t\t\t       0x99230);\n\t\t\t/*RF mode table write disable*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x0);\n\t\t}\n\n\t\t/*@if Nsts > Nc, don't apply V matrix*/\n\t\todm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);\n\n\t\tif (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {\n\t\t\t/*@enable BB TxBF ant mapping register*/\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);\n\n\t\t\t/* logic mapping */\n\t\t\t/* TX BF logic map and TX path en for Nsts = 1~2 */\n\t\t\todm_set_bb_reg(dm, R_0x820, 0xff, 0x33);\n\t\t\todm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x404);\n\t\t\todm_set_bb_reg(dm, R_0x820, 0xffff0000, 0x33);\n\t\t\todm_set_bb_reg(dm, R_0x1e30, 0xffff, 0x404);\n\t\t} else {\n\t\t\t/*@Disable BB TxBF ant mapping register*/\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);\n\t\t\t/*@1SS~2ss A, AB*/\n\t\t\todm_set_bb_reg(dm, R_0x820, 0xff, 0x31);\n\t\t\todm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x400);\n\t\t}\n\t}\n#endif\n#if (RTL8812F_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8812F) {\n\t\tif (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {\n\t\t\t/*Path A ==================*/\n\t\t\t/*RF mode table write enable*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x1);\n\t\t\t/*Select RX mode*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x33, 0xF, 3);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, 0x3, 0x3);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0xfffff,\n\t\t\t\t       0x61AFE);\n\t\t\t/*RF mode table write disable*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x0);\n\n\t\t\t/*Path B ==================*/\n\t\t\t/*RF mode table write enable*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x1);\n\t\t\t/*Select RX mode*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0xF, 3);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, 0xfffff,\n\t\t\t\t       0xD86BF);\n\t\t\t/*RF mode table write disable*/\n\t\t\todm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x0);\n\t\t}\n\n\t\t/*@if Nsts > Nc, don't apply V matrix*/\n\t\todm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);\n\n\t\tif (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {\n\t\t\t/*@enable BB TxBF ant mapping register*/\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);\n\n\t\t\t/* logic mapping */\n\t\t\t/* TX BF logic map and TX path en for Nsts = 1~2 */\n\t\t\todm_set_bb_reg(dm, R_0x820, 0xff, 0x33);\n\t\t\todm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x404);\n\t\t\todm_set_bb_reg(dm, R_0x820, 0xffff0000, 0x33);\n\t\t\todm_set_bb_reg(dm, R_0x1e30, 0xffff, 0x404);\n\t\t} else {\n\t\t\t/*@Disable BB TxBF ant mapping register*/\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);\n\t\t\t/*@1SS~2ss A, AB*/\n\t\t\todm_set_bb_reg(dm, R_0x820, 0xff, 0x31);\n\t\t\todm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x400);\n\t\t}\n\t}\n#endif\n#if (RTL8814B_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8814B) {\n\t\tif (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {\n\t\t\tfor (i = RF_PATH_A; i <= RF_PATH_D; i++) {\n\t\t\t\t/*RF mode table write enable*/\n\t\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,\n\t\t\t\t\t       BIT(19), 0x1);\n\t\t\t\t/*Select RX mode*/\n\t\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x33,\n\t\t\t\t\t       0xF, 2);\n\t\t\t\t/*Set Table data*/\n\t\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e,\n\t\t\t\t\t       0xfffff, 0x3fc);\n\t\t\t\t/*Set Table data*/\n\t\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f,\n\t\t\t\t\t       0xfffff, 0x280f7);\n\t\t\t\t/*Select RX mode*/\n\t\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x33,\n\t\t\t\t\t       0xF, 3);\n\t\t\t\t/*Set Table data*/\n\t\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e,\n\t\t\t\t\t       0xfffff, 0x365);\n\t\t\t\t/*Set Table data*/\n\t\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f,\n\t\t\t\t\t       0xfffff, 0xafcf7);\n\t\t\t\t/*RF mode table write disable*/\n\t\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,\n\t\t\t\t\t       BIT(19), 0x0);\n\t\t\t}\n\t\t}\n\t\t/*@if Nsts > Nc, don't apply V matrix*/\n\t\todm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);\n\n\t\tif (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {\n\t\t\t/*@enable BB TxBF ant mapping register*/\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);\n\n\t\t\t/* logic mapping */\n\t\t\t/* TX BF logic map and TX path en for Nsts = 1~4 */\n\t\t\todm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xffff);\n\t\t\t/*verification path-AC*/\n\t\t\todm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e4e4e4);\n\t\t} else {\n\t\t\t/*@Disable BB TxBF ant mapping register*/\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);\n\t\t\t/*@1SS~4ss A, AB, ABC, ABCD*/\n\t\t\todm_set_bb_reg(dm, R_0x820, 0xffff, 0xf731);\n\t\t\todm_set_bb_reg(dm, R_0x1e2c, 0xffffffff, 0xe4240400);\n\t\t}\n\t}\n#endif\n#if (RTL8198F_SUPPORT)\n\tif (dm->support_ic_type == ODM_RTL8198F) {\n\t\tif (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {\n\t\t\tfor (i = RF_PATH_A; i <= RF_PATH_D; i++) {\n\t\t\t\t/*RF mode table write enable*/\n\t\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,\n\t\t\t\t\t       BIT(19), 0x1);\n\t\t\t\t/*Select RX mode*/\n\t\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x30,\n\t\t\t\t\t       0xfffff, 0x18000);\n\t\t\t\t/*Set Table data*/\n\t\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x31,\n\t\t\t\t\t       0xfffff, 0x4f);\n\t\t\t\t/*Select RX mode*/\n\t\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x32,\n\t\t\t\t\t       0xfffff, 0x71fc0);\n\t\t\t\t/*RF mode table write disable*/\n\t\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,\n\t\t\t\t\t       BIT(19), 0x0);\n\t\t\t}\n\t\t}\n\t\t/*@if Nsts > Nc, don't apply V matrix*/\n\t\todm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);\n\n\t\tif (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {\n\t\t\t/*@enable BB TxBF ant mapping register*/\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);\n\n\t\t\t/* logic mapping */\n\t\t\t/* TX BF logic map and TX path en for Nsts = 1~4 */\n\t\t\todm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xffff);\n\t\t\todm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e4e4e4);\n\t\t} else {\n\t\t\t/*@Disable BB TxBF ant mapping register*/\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);\n\t\t\todm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);\n\t\t\t/*@1SS~4ss A, AB, ABC, ABCD*/\n\t\t\todm_set_bb_reg(dm, R_0x820, 0xffff, 0xf731);\n\t\t\todm_set_bb_reg(dm, R_0x1e2c, 0xffffffff, 0xe4240400);\n\t\t}\n\t}\n#endif\n}\n\nvoid phydm_mu_rsoml_reset(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[MU RSOML] %s cnt reset\\n\", __func__);\n\n\todm_memory_set(dm, &rateinfo->num_mu_vht_pkt[0], 0, VHT_RATE_NUM * 2);\n\todm_memory_set(dm, &rateinfo->num_qry_vht_pkt[0], 0, VHT_RATE_NUM * 2);\n}\n\nvoid phydm_mu_rsoml_init(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[MU RSOML] %s - cnt init\\n\", __func__);\n\n\trateinfo->enable = 1;\n\trateinfo->mu_ratio_th = 30;\n\trateinfo->pre_mu_ratio = 0;\n\tphydm_mu_rsoml_reset(dm);\n}\n\nvoid phydm_mu_rsoml_decision(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tstruct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3;\n\tu8 offset = 0;\n\tu32 mu_ratio = 0;\n\tu32 su_pkt = 0;\n\tu32 mu_pkt = 0;\n\tu32 total_pkt = 0;\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[MU RSOML] RSOML Decision eanble: %d\\n\",\n\t\t  rateinfo->enable);\n\n\tif (!rateinfo->enable)\n\t\treturn;\n\n\tfor (offset = 0; offset < VHT_RATE_NUM; offset++) {\n\t\tmu_pkt +=  rateinfo->num_mu_vht_pkt[offset];\n\t\tsu_pkt +=  rateinfo->num_qry_vht_pkt[offset];\n\t}\n\ttotal_pkt = su_pkt + mu_pkt;\n\n\tif (total_pkt == 0)\n\t\tmu_ratio = 0;\n\telse\n\t\tmu_ratio = (mu_pkt * 100) / total_pkt; // unit:%\n\n\tPHYDM_DBG(dm, DBG_TXBF, \"[MU RSOML] MU rx ratio: %d, total pkt: %d\\n\",\n\t\t  mu_ratio, total_pkt);\n\n\tif (mu_ratio > rateinfo->mu_ratio_th &&\n\t    rateinfo->pre_mu_ratio > rateinfo->mu_ratio_th)\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"[MU RSOML] RSOML status remain\\n\");\n\telse if (mu_ratio <= rateinfo->mu_ratio_th &&\n\t\t rateinfo->pre_mu_ratio <= rateinfo->mu_ratio_th)\n\t\tPHYDM_DBG(dm, DBG_TXBF, \"[MU RSOML] RSOML status remain\\n\");\n\telse if (mu_ratio > rateinfo->mu_ratio_th)\n\t\todm_set_bb_reg(dm, R_0xc00, BIT(26), 0);\n\telse\n\t\todm_set_bb_reg(dm, R_0xc00, BIT(26), 1);\n\n\trateinfo->pre_mu_ratio = mu_ratio;\n\n\tphydm_mu_rsoml_reset(dm);\n}\n\nvoid phydm_txbf_avoid_hang(void *dm_void)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\n\t/* avoid CCK CCA hang when the BF mode */\n\todm_set_bb_reg(dm, R_0x1e6c, 0x100000, 0x1);\n}\n\n#if (RTL8814B_SUPPORT == 1)\nvoid phydm_txbf_80p80_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tu8 i;\n\n\tif (dm->rf_type == RF_1T1R)\n\t\treturn;\n\n\tif (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {\n\t\tfor (i = RF_PATH_A; i <= RF_PATH_D; i += 3) {\n\t\t\t/*RF mode table write enable*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),\n\t\t\t\t       0x1);\n\t\t\t/*Select RX mode*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 2);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff,\n\t\t\t\t       0x3fc);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,\n\t\t\t\t       0x280f7);\n\t\t\t/*Select RX mode*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff,\n\t\t\t\t       0x365);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,\n\t\t\t\t       0xafcf7);\n\t\t\t/*RF mode table write disable*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),\n\t\t\t\t       0x0);\n\t\t}\n\t\tfor (i = RF_PATH_B; i <= RF_PATH_C; i++) {\n\t\t\t/*RF mode table write enable*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),\n\t\t\t\t       0x1);\n\t\t\t/*Select RX mode*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 2);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,\n\t\t\t\t       0x280c7);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,\n\t\t\t\t       0x280c7);\n\t\t\t/*Select RX mode*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff,\n\t\t\t\t       0x365);\n\t\t\t/*Set Table data*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,\n\t\t\t\t       0xafcc7);\n\t\t\t/*RF mode table write disable*/\n\t\t\todm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),\n\t\t\t\t       0x0);\n\t\t}\n\t}\n\t/*@if Nsts > Nc, don't apply V matrix*/\n\todm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);\n\n\tif (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {\n\t\t/*@enable BB TxBF ant mapping register*/\n\t\todm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);\n\t\todm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);\n\n\t\t/* logic mapping */\n\t\t/* TX BF logic map and TX path en for Nsts = 1~2 */\n\t\todm_set_bb_reg(dm, R_0x820, 0xff0000, 0x33); /*seg0*/\n\t\todm_set_bb_reg(dm, R_0x824, 0xff00, 0xcc); /*seg1*/\n\t\todm_set_bb_reg(dm, R_0x1e30, 0xffff, 0xe4e4);\n\n\t} else {\n\t\t/*@Disable BB TxBF ant mapping register*/\n\t\todm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);\n\t\todm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);\n\t\t/*@1SS~2ss A, AB*/\n\t\todm_set_bb_reg(dm, R_0x820, 0xff, 0x31); /*seg0*/\n\t\todm_set_bb_reg(dm, R_0x824, 0xff, 0xc8); /*seg1*/\n\t\todm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0xe420);\n\t}\n}\n#endif\n#endif /*PHYSTS_3RD_TYPE_IC*/\n\nvoid phydm_bf_debug(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t    u32 *_out_len)\n{\n\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\tchar help[] = \"-h\";\n\tu32 var1[3] = {0};\n\tu32 i;\n\n\tif ((strcmp(input[1], help) == 0)) {\n\t\tPDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,\n\t\t\t \"{BF ver1 :0}, {NO applyV:0; applyV:1; default:2}\\n\");\n\t\tPDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,\n\t\t\t \"{MU RSOML:1}, {MU enable:1/0}, {MU Ratio:40}\\n\");\n\t\treturn;\n\t}\n\tfor (i = 0; i < 3; i++) {\n\t\tif (input[i + 1])\n\t\t\tPHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);\n\t}\n\tif (var1[0] == 0) {\n\t\t#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))\n\t\t#ifdef PHYDM_BEAMFORMING_SUPPORT\n\t\tstruct _RT_BEAMFORMING_INFO *beamforming_info = NULL;\n\n\t\tbeamforming_info = &dm->beamforming_info;\n\n\t\tif (var1[1] == 0) {\n\t\t\tbeamforming_info->apply_v_matrix = false;\n\t\t\tbeamforming_info->snding3ss = true;\n\t\t\tPDM_SNPF(*_out_len, *_used, output + *_used,\n\t\t\t\t *_out_len - *_used,\n\t\t\t\t\"\\r\\n dont apply V matrix and 3SS 789 snding\\n\");\n\t\t} else if (var1[1] == 1) {\n\t\t\tbeamforming_info->apply_v_matrix = true;\n\t\t\tbeamforming_info->snding3ss = true;\n\t\t\tPDM_SNPF(*_out_len, *_used, output + *_used,\n\t\t\t\t *_out_len - *_used,\n\t\t\t\t \"\\r\\n apply V matrix and 3SS 789 snding\\n\");\n\t\t} else if (var1[1] == 2) {\n\t\t\tbeamforming_info->apply_v_matrix = true;\n\t\t\tbeamforming_info->snding3ss = false;\n\t\t\tPDM_SNPF(*_out_len, *_used, output + *_used,\n\t\t\t\t *_out_len - *_used,\n\t\t\t\t \"\\r\\n default txbf setting\\n\");\n\t\t} else {\n\t\t\tPDM_SNPF(*_out_len, *_used, output + *_used,\n\t\t\t\t *_out_len - *_used,\n\t\t\t\t \"\\r\\n unknown cmd!!\\n\");\n\t\t}\n\t\t#endif\n\t\t#endif\n\t} else if (var1[0] == 1) {\n\t\t#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\n\t\tstruct dm_struct *dm = (struct dm_struct *)dm_void;\n\t\tstruct phydm_bf_rate_info_jgr3 *bfinfo = &dm->bf_rate_info_jgr3;\n\n\t\tbfinfo->enable = (u8)var1[1];\n\t\tbfinfo->mu_ratio_th = (u8)var1[2];\n\t\tPDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,\n\t\t\t \"[MU RSOML] enable= %d, MU ratio TH= %d\\n\",\n\t\t\t bfinfo->enable, bfinfo->mu_ratio_th);\n\t\t#endif\n\t}\n}\n\n#endif /*CONFIG_BB_TXBF_API*/\n"
  },
  {
    "path": "hal/phydm/txbf/phydm_hal_txbf_api.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017  Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * The full GNU General Public License is included in this distribution in the\n * file called LICENSE.\n *\n * Contact Information:\n * wlanfae <wlanfae@realtek.com>\n * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,\n * Hsinchu 300, Taiwan.\n *\n * Larry Finger <Larry.Finger@lwfinger.net>\n *\n *****************************************************************************/\n#ifndef __PHYDM_HAL_TXBF_API_H__\n#define __PHYDM_HAL_TXBF_API_H__\n\n#if (defined(CONFIG_BB_TXBF_API))\n\n#if (DM_ODM_SUPPORT_TYPE != ODM_AP)\n#if defined(DM_ODM_CE_MAC80211)\n#define tx_bf_nr(a, b) ({\t\\\n\tu8 __tx_bf_nr_a = (a);\t\\\n\tu8 __tx_bf_nr_b = (b);\t\\\n\t((__tx_bf_nr_a > __tx_bf_nr_b) ? (__tx_bf_nr_b) : (__tx_bf_nr_a)); })\n#else\n#define tx_bf_nr(a, b) ((a > b) ? (b) : (a))\n#endif\n\nu8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num);\n\nu8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num);\n\n#endif\n\n#if (RTL8822B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8192F_SUPPORT == 1 ||\\\n\tRTL8814B_SUPPORT == 1 || RTL8198F_SUPPORT == 1)\n\nu8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput,\n\t\t\t\t       u8 total_bfee_num, u8 *tx_rate);\nu8 phydm_get_ndpa_rate(void *dm_void);\n\nu8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput);\n\n#else\n#define phydm_get_beamforming_sounding_info(dm, tp, bfee_num, rate) 0\n#define phydm_get_ndpa_rate(dm)\n#define phydm_get_mu_bfee_snding_decision(dm, tp)\n\n#endif\n\n#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT\nstruct phydm_bf_rate_info_jgr3 {\n\tu8\t\t\tenable;\n\tu8\t\t\tmu_ratio_th;\n\tu32\t\t\tpre_mu_ratio;\n\tu16\t\t\tnum_mu_vht_pkt[VHT_RATE_NUM];\n\tu16\t\t\tnum_qry_vht_pkt[VHT_RATE_NUM];\n};\n\n/*this function is only used for BFer*/\nvoid phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt);\nvoid phydm_txbf_avoid_hang(void *dm_void);\nvoid phydm_mu_rsoml_init(void *dm_void);\nvoid phydm_mu_rsoml_decision(void *dm_void);\n\n#if (RTL8814B_SUPPORT == 1)\nvoid phydm_txbf_80p80_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt);\n#endif\n\n#endif /*#PHYDM_IC_JGR3_SERIES_SUPPORT*/\nvoid phydm_bf_debug(void *dm_void, char input[][16], u32 *_used, char *output,\n\t\t    u32 *_out_len);\n#endif\n#endif\n"
  },
  {
    "path": "hal/rtl8822c/hal8822c_fw.c",
    "content": "/******************************************************************************\n*\n* Copyright(c) 2012 - 2017 Realtek Corporation.\n*\n* This program is free software; you can redistribute it and/or modify it\n* under the terms of version 2 of the GNU General Public License as\n* published by the Free Software Foundation.\n*\n* This program is distributed in the hope that it will be useful, but WITHOUT\n* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n* more details.\n*\n******************************************************************************/\n\n#ifdef CONFIG_RTL8822C\n\n#include \"drv_types.h\"\n\n#ifdef LOAD_FW_HEADER_FROM_DRIVER\n\n#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))\n\nu8 array_mp_8822c_fw_ap[] = {\n0x22, 0x88, 0x00, 0x00, 0x07, 0x00, 0x0D, 0x00,\n0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,\n0x09, 0x12, 0x0E, 0x18, 0xE3, 0x07, 0x00, 0x00,\n0x18, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x20, 0x80, 0xB0, 0x2B, 0x00, 0x00,\n0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x80, 0x49, 0x00, 0x00, 0x80, 0x81, 0x01, 0x00,\n0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80,\n0x00, 0x00, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08,\n0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,\n0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\n0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 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0x8C, 0xEA, 0x63, 0xEA, 0x46, 0x60,\n0x30, 0xF0, 0x20, 0x6C, 0x48, 0x35, 0x25, 0xF1,\n0x10, 0x4C, 0x91, 0xE5, 0xA0, 0xAC, 0xFF, 0x6C,\n0xC5, 0x67, 0x8C, 0xEE, 0x2E, 0xEE, 0x05, 0x2E,\n0xA2, 0x35, 0x8C, 0xED, 0x04, 0x94, 0x8E, 0xED,\n0xB0, 0x25, 0x30, 0xF0, 0x20, 0x6C, 0x48, 0x35,\n0x25, 0xF1, 0x10, 0x4C, 0xB1, 0xE4, 0xA1, 0xAC,\n0xFF, 0x6C, 0xC5, 0x67, 0x8C, 0xEE, 0x2E, 0xEE,\n0xDE, 0x2E, 0x04, 0x96, 0xA2, 0x35, 0x8C, 0xED,\n0xCE, 0xED, 0xD9, 0x2D, 0x9E, 0x17, 0x62, 0xEA,\n0x00, 0x68, 0x09, 0x61, 0x3D, 0x67, 0x47, 0x41,\n0x09, 0x4A, 0x40, 0xA2, 0x0D, 0x91, 0x01, 0x68,\n0x40, 0xC1, 0x0E, 0x94, 0x60, 0xC4, 0x30, 0xF0,\n0x20, 0x6B, 0xE9, 0xF1, 0x68, 0x9B, 0xFF, 0x6A,\n0x01, 0x4A, 0x6C, 0xEA, 0x09, 0x22, 0x30, 0xF0,\n0x20, 0x6C, 0xE3, 0xF6, 0x04, 0x4C, 0xB0, 0x67,\n0x80, 0x18, 0x10, 0x42, 0x01, 0x10, 0x00, 0x68,\n0x50, 0x67, 0x0B, 0x97, 0x0A, 0x91, 0x09, 0x90,\n0x06, 0x63, 0x00, 0xEF, 0x00, 0x68, 0xF0, 0x67,\n0xD0, 0x67, 0xE5, 0x17, 0xFB, 0x63, 0x09, 0x62,\n0x08, 0xD1, 0x07, 0xD0, 0xFF, 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0x69,\n0x38, 0xEC, 0x30, 0xF0, 0x20, 0x6A, 0x29, 0xF6,\n0x00, 0x4A, 0x30, 0xF0, 0x20, 0x68, 0xFF, 0x6D,\n0x02, 0x6E, 0x12, 0xE9, 0x25, 0xE2, 0x80, 0xF2,\n0x48, 0x98, 0x87, 0x41, 0x1A, 0x4C, 0x40, 0xEA,\n0x80, 0xF2, 0x48, 0x98, 0x87, 0x41, 0x1C, 0x4C,\n0x00, 0x6D, 0x02, 0x6E, 0x40, 0xEA, 0x30, 0xF0,\n0x20, 0x6B, 0xE9, 0xF1, 0x68, 0x9B, 0x01, 0xF0,\n0x00, 0x6A, 0x6C, 0xEA, 0x13, 0x22, 0x30, 0xF0,\n0x20, 0x6C, 0x03, 0xF7, 0x0C, 0x4C, 0x0C, 0x10,\n0x30, 0xF0, 0x20, 0x6B, 0xE9, 0xF1, 0x68, 0x9B,\n0x01, 0xF0, 0x00, 0x6A, 0x6C, 0xEA, 0x06, 0x22,\n0x30, 0xF0, 0x20, 0x6C, 0x03, 0xF7, 0x18, 0x4C,\n0x80, 0x18, 0x10, 0x42, 0x07, 0x97, 0x06, 0x91,\n0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0x00, 0x65,\n0xFC, 0x63, 0x07, 0x62, 0xFF, 0x6A, 0x8C, 0xEA,\n0x2E, 0x6B, 0x78, 0xEA, 0x30, 0xF0, 0x20, 0x6C,\n0x29, 0xF6, 0x00, 0x4C, 0x12, 0xEB, 0x6D, 0xE4,\n0x20, 0xF0, 0x81, 0xA3, 0xFF, 0x74, 0x0F, 0x60,\n0x20, 0xF0, 0x83, 0xA3, 0x32, 0x5C, 0x04, 0x60,\n0x01, 0x4C, 0x20, 0xF0, 0x83, 0xC3, 0x07, 0x10,\n0x00, 0x6C, 0x20, 0xF0, 0x83, 0xC3, 0x01, 0x6C,\n0x8B, 0xEC, 0x20, 0xF0, 0x81, 0xC3, 0x20, 0xF0,\n0x82, 0xA3, 0xFF, 0x74, 0x0F, 0x60, 0x20, 0xF0,\n0x84, 0xA3, 0x32, 0x5C, 0x08, 0x61, 0x00, 0x6C,\n0x20, 0xF0, 0x84, 0xC3, 0x01, 0x6C, 0x8B, 0xEC,\n0x20, 0xF0, 0x82, 0xC3, 0x03, 0x10, 0x01, 0x4C,\n0x20, 0xF0, 0x84, 0xC3, 0x01, 0x72, 0x17, 0x61,\n0x30, 0xF0, 0x20, 0x6C, 0xE9, 0xF1, 0x88, 0x9C,\n0x01, 0xF0, 0x00, 0x6A, 0x8C, 0xEA, 0x0F, 0x22,\n0x20, 0xF0, 0xA1, 0xA3, 0x20, 0xF0, 0xC3, 0xA3,\n0x20, 0xF0, 0xE2, 0xA3, 0x20, 0xF0, 0x44, 0xA3,\n0x30, 0xF0, 0x20, 0x6C, 0x23, 0xF7, 0x04, 0x4C,\n0x04, 0xD2, 0x80, 0x18, 0x10, 0x42, 0x07, 0x97,\n0x04, 0x63, 0x00, 0xEF, 0xFC, 0x63, 0x07, 0x62,\n0xFF, 0x6E, 0x44, 0x67, 0x20, 0xF4, 0x0D, 0x6B,\n0x9D, 0x67, 0x68, 0xCC, 0xCC, 0xEA, 0x20, 0xF4,\n0x0F, 0x6B, 0x69, 0xCC, 0x44, 0x33, 0x6D, 0xE4,\n0x68, 0xAB, 0x1F, 0xF7, 0x00, 0x6C, 0xAC, 0xEE,\n0x6C, 0xEC, 0x02, 0xF0, 0x00, 0x74, 0x01, 0x60,\n0x05, 0x2C, 0x30, 0xF0, 0x20, 0x6C, 0xE2, 0xF4,\n0x98, 0x9C, 0x04, 0x10, 0x30, 0xF0, 0x20, 0x6C,\n0xE2, 0xF4, 0x9C, 0x9C, 0x91, 0xE3, 0xA0, 0xA4,\n0xF1, 0x6C, 0xAC, 0xEC, 0xC4, 0x35, 0x8D, 0xED,\n0x00, 0xF6, 0xA0, 0x34, 0x00, 0xF6, 0x83, 0x34,\n0xFF, 0x6D, 0xAC, 0xEC, 0x1F, 0xF7, 0x00, 0x6D,\n0x6C, 0xED, 0x02, 0xF0, 0x00, 0x75, 0x01, 0x60,\n0x05, 0x2D, 0x30, 0xF0, 0x20, 0x6D, 0xE2, 0xF4,\n0xB8, 0x9D, 0x04, 0x10, 0x30, 0xF0, 0x20, 0x6D,\n0xE2, 0xF4, 0xBC, 0x9D, 0xAD, 0xE3, 0x80, 0xC3,\n0x30, 0xF0, 0x20, 0x6B, 0xE9, 0xF1, 0x68, 0x9B,\n0x10, 0x6C, 0x8C, 0xEB, 0x07, 0x23, 0x30, 0xF0,\n0x20, 0x6C, 0x43, 0xF7, 0x00, 0x4C, 0xA2, 0x67,\n0x80, 0x18, 0x10, 0x42, 0x07, 0x97, 0x04, 0x63,\n0x00, 0xEF, 0x00, 0x65, 0xFB, 0x63, 0x09, 0x62,\n0x08, 0xD1, 0x07, 0xD0, 0x30, 0xF0, 0x20, 0x68,\n0x25, 0xF5, 0x00, 0x48, 0xE4, 0xF0, 0x59, 0xA0,\n0xFF, 0x69, 0x8C, 0xE9, 0x16, 0x22, 0x09, 0xE1,\n0xE4, 0xF0, 0xB4, 0xA2, 0x91, 0x67, 0x04, 0xD2,\n0x80, 0x18, 0x0B, 0x4B, 0xC3, 0xF4, 0x48, 0x98,\n0x10, 0x6B, 0x6C, 0xEA, 0x0A, 0x22, 0x04, 0x92,\n0x30, 0xF0, 0x20, 0x6C, 0x43, 0xF7, 0x18, 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0x30, 0xF0, 0x20, 0x6B, 0x63, 0xF2,\n0x88, 0x9B, 0x40, 0x6D, 0xAB, 0xED, 0x60, 0xA4,\n0x2C, 0xEA, 0x0C, 0xEB, 0xAC, 0xEB, 0x05, 0x95,\n0xAD, 0xEB, 0x0C, 0xEB, 0x60, 0xC4, 0x30, 0xF0,\n0x20, 0x6B, 0x63, 0xF2, 0x8C, 0x9B, 0x30, 0xF0,\n0x20, 0x6D, 0xE2, 0xF7, 0xA0, 0x9D, 0x60, 0x9C,\n0x06, 0x96, 0xAC, 0xEB, 0x30, 0xF0, 0x20, 0x6D,\n0xE2, 0xF5, 0xAC, 0x9D, 0xC4, 0xEA, 0x46, 0x67,\n0xAD, 0xEB, 0x04, 0x95, 0x07, 0x96, 0xAC, 0xEA,\n0xAF, 0xED, 0xCC, 0xED, 0xAD, 0xEA, 0x2C, 0xEA,\n0x4D, 0xEB, 0x60, 0xDC, 0x30, 0xF0, 0x20, 0x6A,\n0x80, 0xF3, 0x4C, 0x9A, 0x0A, 0x6C, 0x40, 0xEA,\n0x0B, 0x97, 0x0A, 0x91, 0x09, 0x90, 0x06, 0x63,\n0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62,\n0x00, 0x6C, 0x10, 0xF0, 0x00, 0x6D, 0x80, 0x18,\n0xB1, 0x5F, 0x05, 0x97, 0x01, 0x5A, 0x58, 0x67,\n0x03, 0x63, 0x00, 0xEF, 0xFD, 0x63, 0x05, 0x62,\n0x04, 0xD0, 0x30, 0xF0, 0x20, 0x6B, 0xC2, 0xF4,\n0x64, 0x9B, 0x10, 0xF0, 0x32, 0x6A, 0x30, 0xF0,\n0x05, 0x4A, 0x40, 0xDB, 0x00, 0x68, 0x31, 0x10,\n0x82, 0xF3, 0x08, 0x70, 0x1A, 0x61, 0x30, 0xF0,\n0x20, 0x6A, 0xA2, 0xF5, 0x64, 0x9A, 0x02, 0xF0,\n0x00, 0x6C, 0x40, 0x9B, 0x8D, 0xEA, 0x40, 0xDB,\n0x30, 0xF0, 0x20, 0x6A, 0x25, 0xF5, 0x00, 0x4A,\n0x63, 0xF3, 0x60, 0x9A, 0x8D, 0xEB, 0x63, 0xF3,\n0x60, 0xDA, 0x30, 0xF0, 0x20, 0x6A, 0x62, 0xF5,\n0x4C, 0x9A, 0x03, 0x6B, 0x6B, 0xEB, 0x60, 0xC2,\n0x18, 0x10, 0xFF, 0xF7, 0x1F, 0x6A, 0x01, 0x48,\n0x4C, 0xE8, 0x30, 0xF0, 0x20, 0x6A, 0x80, 0xF3,\n0x4C, 0x9A, 0x14, 0x6C, 0x40, 0xEA, 0x33, 0x58,\n0x08, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0x23, 0xF1,\n0x48, 0x9A, 0x60, 0xA2, 0x08, 0x6A, 0x6C, 0xEA,\n0x04, 0x2A, 0x80, 0x18, 0x03, 0x60, 0x01, 0x72,\n0xCB, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0x62, 0xF5,\n0x4C, 0x9A, 0x02, 0x6B, 0x6B, 0xEB, 0x60, 0xC2,\n0x30, 0xF0, 0x20, 0x6B, 0xC2, 0xF4, 0x64, 0x9B,\n0x10, 0xF0, 0x32, 0x6A, 0x30, 0xF0, 0x06, 0x4A,\n0x40, 0xDB, 0x05, 0x97, 0x04, 0x90, 0x03, 0x63,\n0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62,\n0x04, 0xD0, 0x30, 0xF0, 0x20, 0x6A, 0x63, 0xF2,\n0x70, 0x9A, 0x02, 0x6C, 0xFF, 0xF7, 0x1F, 0x6D,\n0x40, 0x9B, 0xFF, 0x6E, 0x41, 0x4E, 0x8D, 0xEA,\n0x40, 0xDB, 0x30, 0xF0, 0x20, 0x6A, 0x02, 0xF5,\n0x70, 0x9A, 0xE0, 0xF3, 0x1E, 0x4C, 0x30, 0xF0,\n0x20, 0x68, 0x40, 0xAB, 0xAC, 0xEA, 0x8D, 0xEA,\n0xAC, 0xEA, 0x40, 0xCB, 0x02, 0x6C, 0x80, 0x18,\n0xCC, 0x5F, 0x80, 0xF3, 0x4C, 0x98, 0x0A, 0x6C,\n0x40, 0xEA, 0x00, 0x6C, 0xC0, 0x6D, 0x02, 0x6E,\n0x80, 0x18, 0xCC, 0x5F, 0x00, 0x6C, 0xC4, 0x67,\n0x02, 0xF0, 0x00, 0x6D, 0x80, 0x18, 0xCC, 0x5F,\n0x00, 0x6C, 0xC4, 0x67, 0x0C, 0xF0, 0x00, 0x6D,\n0x80, 0x18, 0xCC, 0x5F, 0x00, 0x6C, 0x01, 0xF0,\n0x00, 0x6D, 0x01, 0x6E, 0x80, 0x18, 0xCC, 0x5F,\n0x10, 0xF0, 0x00, 0x6D, 0x01, 0x6E, 0x00, 0x6C,\n0x80, 0x18, 0xCC, 0x5F, 0x80, 0xF3, 0x4C, 0x98,\n0x0A, 0x6C, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6A,\n0x63, 0xF2, 0x74, 0x9A, 0xFF, 0x6C, 0x04, 0x6D,\n0x40, 0xA3, 0x8C, 0xEA, 0xAD, 0xEA, 0x8C, 0xEA,\n0x40, 0xC3, 0x05, 0x97, 0x04, 0x90, 0x03, 0x63,\n0x00, 0xEF, 0x00, 0x65, 0x00, 0x00, 0x00, 0x00,\n0xC8, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\n};\n\nu32 array_length_mp_8822c_fw_ap = 128776;\n\n#endif /*defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))*/\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE))\n\nu8 array_mp_8822c_fw_hybrid[] = {\n0x22, 0x88, 0x00, 0x00, 0x07, 0x00, 0x0D, 0x00,\n0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,\n0x09, 0x12, 0x0E, 0x1A, 0xE3, 0x07, 0x00, 0x00,\n0x18, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x20, 0x80, 0xC0, 0x40, 0x00, 0x00,\n0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x98, 0x95, 0x00, 0x00, 0xC0, 0xBE, 0x01, 0x00,\n0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80,\n0x00, 0x00, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08,\n0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,\n0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\n0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x03, 0x00, 0x01, 0xFE, 0x03, 0x01, 0x01, 0xFE,\n0x03, 0x02, 0x01, 0xFE, 0x03, 0x03, 0x01, 0xFE,\n0x03, 0x04, 0x01, 0xFE, 0x03, 0x05, 0x01, 0xFE,\n0x03, 0x06, 0x01, 0xFE, 0x03, 0x07, 0x01, 0xFE,\n0x48, 0x0A, 0x20, 0x80, 0x06, 0x00, 0x00, 0x00,\n0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,\n0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00,\n0x01, 0x00, 0x03, 0x80, 0xA9, 0x01, 0x03, 0x80,\n0xA9, 0x01, 0x03, 0x80, 0x08, 0x00, 0x00, 0x00,\n0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0xE0,\n0x4C, 0x81, 0x92, 0x01, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x8D,\n0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x07, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x66, 0xB8, 0x00, 0xFF, 0xFF, 0x00,\n0xCD, 0x9B, 0x78, 0x56, 0x04, 0x1C, 0x66, 0xB8,\n0x08, 0x1C, 0x66, 0xB8, 0xFF, 0xFF, 0xFF, 0x3F,\n0x1F, 0x00, 0x60, 0xB8, 0x05, 0xEA, 0xEF, 0xFD,\n0x06, 0xEA, 0xEF, 0xFD, 0x00, 0x1C, 0x66, 0xB8,\n0xFF, 0xFF, 0x3F, 0x00, 0x04, 0xEA, 0xEF, 0xFD,\n0x07, 0xEA, 0xEF, 0xFD, 0x08, 0xEA, 0xEF, 0xFD,\n0x09, 0xEA, 0xEF, 0xFD, 0x0A, 0xEA, 0xEF, 0xFD,\n0x00, 0x10, 0x66, 0xB8, 0x23, 0x04, 0x64, 0xB8,\n0x30, 0x04, 0x64, 0xB8, 0x34, 0x04, 0x64, 0xB8,\n0x04, 0x05, 0x07, 0x08, 0x00, 0x01, 0x01, 0x02,\n0x2D, 0x04, 0x64, 0xB8, 0x06, 0x00, 0x66, 0xB8,\n0x52, 0x04, 0x64, 0xB8, 0x53, 0x04, 0x64, 0xB8,\n0x50, 0x04, 0x64, 0xB8, 0x51, 0x04, 0x64, 0xB8,\n0x01, 0x1C, 0x66, 0xB8, 0x02, 0x1C, 0x66, 0xB8,\n0x03, 0x1C, 0x66, 0xB8, 0x05, 0x1C, 0x66, 0xB8,\n0x06, 0x1C, 0x66, 0xB8, 0x07, 0x1C, 0x66, 0xB8,\n0x44, 0x00, 0x78, 0xB8, 0x01, 0x00, 0x00, 0xC0,\n0x01, 0x00, 0x00, 0x60, 0x01, 0x00, 0x0F, 0x70,\n0x01, 0x00, 0x1F, 0x70, 0x01, 0x00, 0x2F, 0x70,\n0x01, 0x00, 0x3F, 0x70, 0x01, 0x00, 0x4F, 0x70,\n0x01, 0x00, 0x5F, 0x70, 0x01, 0x00, 0x6F, 0x70,\n0x01, 0x00, 0x7F, 0x70, 0x01, 0x00, 0x8F, 0x70,\n0x01, 0x00, 0x9F, 0x70, 0x01, 0x00, 0xAF, 0x70,\n0x01, 0x00, 0xBF, 0x70, 0x01, 0x00, 0xCF, 0x70,\n0x01, 0x00, 0xDF, 0x70, 0x01, 0x00, 0xEF, 0x70,\n0x01, 0x00, 0xFF, 0x70, 0x41, 0x80, 0x0B, 0x70,\n0x41, 0x40, 0x14, 0x70, 0x41, 0x40, 0x24, 0x70,\n0x41, 0x40, 0x34, 0x70, 0x41, 0x40, 0x44, 0x70,\n0x41, 0x80, 0x5B, 0x70, 0x41, 0x40, 0x64, 0x70,\n0x41, 0x80, 0x7B, 0x70, 0x41, 0x80, 0x8B, 0x70,\n0x41, 0x80, 0x9B, 0x70, 0x41, 0x80, 0xAB, 0x70,\n0x41, 0x80, 0xBB, 0x70, 0x41, 0x80, 0xCB, 0x70,\n0x41, 0x80, 0xDB, 0x70, 0x41, 0x80, 0xEB, 0x70,\n0x41, 0x80, 0xFB, 0x70, 0x00, 0x00, 0x10, 0x00,\n0x50, 0x50, 0x50, 0x50, 0x00, 0x00, 0x00, 0x70,\n0x00, 0x00, 0x03, 0x00, 0xEF, 0x00, 0x60, 0xB8,\n0x03, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x60,\n0x08, 0x18, 0x07, 0x00, 0x08, 0x0C, 0x07, 0x00,\n0x08, 0x00, 0x04, 0x00, 0xFF, 0x60, 0x0F, 0x00,\n0x3F, 0xD8, 0x0F, 0x00, 0xFF, 0x60, 0x07, 0x00,\n0x3F, 0xD8, 0x0D, 0x00, 0xFF, 0xDE, 0x07, 0x00,\n0xBF, 0xF7, 0x0D, 0x00, 0x00, 0xC0, 0x0F, 0x00,\n0x00, 0x00, 0x7C, 0x00, 0x00, 0xF0, 0x01, 0x00,\n0x5E, 0x00, 0xD5, 0xF7, 0x40, 0x00, 0x1F, 0x70,\n0x40, 0x00, 0x2F, 0x70, 0x40, 0x00, 0x3F, 0x70,\n0x40, 0x00, 0x4F, 0x70, 0x40, 0x00, 0x6F, 0x70,\n0x5E, 0x00, 0xA1, 0xFF, 0x00, 0x00, 0xFF, 0x1F,\n0xFF, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFF,\n0x00, 0x00, 0xFF, 0xFF, 0x80, 0x00, 0x00, 0x30,\n0xF0, 0x00, 0x04, 0x00, 0xF0, 0x00, 0x04, 0x04,\n0xF0, 0x00, 0x04, 0x08, 0xF0, 0x00, 0x04, 0x01,\n0xF0, 0x00, 0x04, 0x05, 0xF0, 0x00, 0x04, 0x09,\n0xF0, 0x00, 0x04, 0x02, 0xF0, 0x00, 0x04, 0x06,\n0xF0, 0x00, 0x04, 0x0A, 0xF0, 0x00, 0x04, 0x03,\n0xF0, 0x00, 0x04, 0x07, 0xF0, 0x00, 0x04, 0x0B,\n0xF0, 0x00, 0x04, 0x0C, 0xF0, 0x00, 0x04, 0x10,\n0xF0, 0x00, 0x04, 0x0D, 0xF0, 0x00, 0x04, 0x11,\n0xF0, 0x00, 0x04, 0x0E, 0xF0, 0x00, 0x04, 0x12,\n0xF0, 0x00, 0x04, 0x0F, 0xF0, 0x00, 0x04, 0x13,\n0x00, 0x00, 0x06, 0x00, 0x01, 0x00, 0x06, 0x00,\n0xF0, 0x00, 0x09, 0x00, 0x17, 0x00, 0x05, 0x00,\n0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x10, 0x1F,\n0x00, 0x00, 0x0D, 0x1F, 0x0B, 0x17, 0x23, 0x3B,\n0x47, 0x53, 0x5F, 0x77, 0x00, 0x48, 0x08, 0x00,\n0x01, 0x48, 0x08, 0x00, 0x00, 0x00, 0x0F, 0x80,\n0x00, 0x00, 0x0F, 0xC0, 0x3F, 0x00, 0x00, 0xC0,\n0x80, 0x66, 0x06, 0x01, 0x10, 0x13, 0x00, 0x80,\n0xDB, 0x00, 0x00, 0x81, 0xDB, 0x00, 0x00, 0x01,\n0x00, 0x00, 0x02, 0x05, 0x0C, 0x19, 0x00, 0x82,\n0x0C, 0x19, 0x00, 0x02, 0x14, 0xEE, 0x01, 0x83,\n0x14, 0xEE, 0x01, 0x03, 0x08, 0x00, 0x02, 0x05,\n0x14, 0x00, 0x03, 0x00, 0xFF, 0xFF, 0xFF, 0x03,\n0x12, 0x33, 0x03, 0x00, 0x11, 0x33, 0x03, 0x00,\n0x12, 0x11, 0x01, 0x00, 0x31, 0xC9, 0x62, 0x49,\n0x55, 0x24, 0x01, 0xFF, 0xC8, 0xFE, 0x18, 0x3E,\n0xDE, 0xF0, 0xFA, 0x00, 0x44, 0x23, 0x12, 0x00,\n0x01, 0xC0, 0xE0, 0x70, 0x01, 0x80, 0xEB, 0x70,\n0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00,\n0x3F, 0xFF, 0xFE, 0xDF, 0x00, 0xFF, 0x0F, 0x00,\n0x01, 0x80, 0x03, 0x70, 0x01, 0x80, 0x53, 0x70,\n0x01, 0x80, 0x73, 0x70, 0x01, 0x80, 0x83, 0x70,\n0x01, 0x80, 0x93, 0x70, 0x01, 0x80, 0xA3, 0x70,\n0x01, 0x80, 0xB3, 0x70, 0x01, 0x80, 0xC3, 0x70,\n0x01, 0x80, 0xD3, 0x70, 0x01, 0x80, 0xE3, 0x70,\n0x01, 0x80, 0xF3, 0x70, 0x01, 0x80, 0x0B, 0x70,\n0x01, 0x80, 0x5B, 0x70, 0x01, 0x80, 0x7B, 0x70,\n0x01, 0x80, 0x8B, 0x70, 0x01, 0x80, 0x9B, 0x70,\n0x01, 0x80, 0xAB, 0x70, 0x01, 0x80, 0xBB, 0x70,\n0x01, 0x80, 0xCB, 0x70, 0x01, 0x80, 0xDB, 0x70,\n0x01, 0x80, 0xFB, 0x70, 0x00, 0x00, 0x60, 0x00,\n0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x7F, 0x00,\n0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x40, 0x00,\n0x00, 0x00, 0x70, 0x00, 0x00, 0xFC, 0xF8, 0xFF,\n0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x3F,\n0xC4, 0x06, 0x64, 0xB8, 0x70, 0x07, 0x64, 0xB8,\n0x74, 0x07, 0x64, 0xB8, 0xCC, 0x06, 0x64, 0xB8,\n0xAA, 0x00, 0x60, 0xB8, 0x00, 0x04, 0x00, 0x04,\n0xA8, 0x06, 0x64, 0xB8, 0x10, 0x07, 0x64, 0xB8,\n0x00, 0x16, 0x64, 0xB8, 0x04, 0x16, 0x64, 0xB8,\n0x08, 0x16, 0x64, 0xB8, 0x65, 0x07, 0x64, 0xB8,\n0x40, 0x00, 0x60, 0xB8, 0x68, 0x00, 0x60, 0xB8,\n0x6E, 0x07, 0x64, 0xB8, 0x64, 0x07, 0x64, 0xB8,\n0x23, 0x05, 0x64, 0xB8, 0x64, 0x00, 0x60, 0xB8,\n0xFF, 0xFF, 0x40, 0xFF, 0x20, 0x34, 0x00, 0xB8,\n0x00, 0x00, 0x70, 0xB8, 0x18, 0x00, 0x70, 0xB8,\n0x0B, 0x00, 0x70, 0xB8, 0x02, 0x00, 0x70, 0xB8,\n0x1C, 0x01, 0x64, 0xB8, 0x94, 0x02, 0x64, 0xB8,\n0x97, 0x02, 0x64, 0xB8, 0x84, 0x02, 0x64, 0xB8,\n0x50, 0x02, 0x64, 0xB8, 0x48, 0x02, 0x64, 0xB8,\n0x74, 0x00, 0x18, 0x2E, 0x74, 0x00, 0x19, 0x2E,\n0x01, 0x00, 0x60, 0xB8, 0x01, 0x00, 0x64, 0xB8,\n0xCF, 0x01, 0x64, 0xB8, 0x34, 0x01, 0x64, 0xB8,\n0x64, 0x05, 0x64, 0xB8, 0x60, 0x05, 0x64, 0xB8,\n0x27, 0x05, 0x64, 0xB8, 0xB5, 0x05, 0x64, 0xB8,\n0x1D, 0x05, 0x64, 0xB8, 0x1C, 0x05, 0x64, 0xB8,\n0xB7, 0x05, 0x64, 0xB8, 0x31, 0x05, 0x64, 0xB8,\n0x3C, 0x11, 0x64, 0xB8, 0x50, 0x05, 0x64, 0xB8,\n0x40, 0x05, 0x64, 0xB8, 0xC8, 0x01, 0x64, 0xB8,\n0xC9, 0x01, 0x64, 0xB8, 0x0C, 0xEA, 0xEF, 0xFD,\n0xA0, 0x01, 0x64, 0xB8, 0x48, 0x00, 0x60, 0xB8,\n0x47, 0x00, 0x60, 0xB8, 0x46, 0x00, 0x60, 0xB8,\n0x63, 0x00, 0x60, 0xB8, 0x62, 0x00, 0x60, 0xB8,\n0x45, 0x00, 0x60, 0xB8, 0x61, 0x00, 0x60, 0xB8,\n0xC6, 0x01, 0x64, 0xB8, 0xFF, 0xFF, 0xFF, 0x00,\n0x00, 0x00, 0x00, 0x05, 0x64, 0x01, 0x64, 0xB8,\n0x53, 0x05, 0x64, 0xB8, 0x94, 0x01, 0x64, 0xB8,\n0x54, 0x00, 0x60, 0xB8, 0x24, 0x11, 0x64, 0xB8,\n0x2C, 0x11, 0x64, 0xB8, 0x34, 0x11, 0x64, 0xB8,\n0xE4, 0x11, 0x64, 0xB8, 0x00, 0x40, 0xE0, 0x03,\n0x01, 0x70, 0x00, 0x03, 0xE0, 0x12, 0x64, 0xB8,\n0x67, 0x05, 0x64, 0xB8, 0x66, 0x05, 0x64, 0xB8,\n0x65, 0x05, 0x64, 0xB8, 0x63, 0x05, 0x64, 0xB8,\n0x62, 0x05, 0x64, 0xB8, 0x61, 0x05, 0x64, 0xB8,\n0xB4, 0x00, 0x60, 0xB8, 0x2F, 0x01, 0x64, 0xB8,\n0xE8, 0x10, 0x60, 0xB8, 0x00, 0x3C, 0x64, 0xB8,\n0x00, 0x4C, 0x64, 0xB8, 0x00, 0x58, 0x64, 0xB8,\n0x00, 0x5C, 0x64, 0xB8, 0xF8, 0x05, 0x64, 0xB8,\n0x83, 0x00, 0x60, 0xB8, 0x08, 0x01, 0x64, 0xB8,\n0x90, 0x00, 0x60, 0xB8, 0x92, 0x00, 0x60, 0xB8,\n0x92, 0x06, 0x64, 0xB8, 0x2C, 0x04, 0x64, 0xB8,\n0x1F, 0x04, 0x64, 0xB8, 0x5F, 0x01, 0x64, 0xB8,\n0x1F, 0x07, 0x64, 0xB8, 0x1C, 0x07, 0x64, 0xB8,\n0xB8, 0x05, 0x64, 0xB8, 0xBC, 0x05, 0x64, 0xB8,\n0x5F, 0x11, 0x64, 0xB8, 0xFE, 0xFF, 0xFF, 0x7F,\n0x30, 0x00, 0x78, 0x18, 0xA0, 0x34, 0x00, 0xB8,\n0x00, 0x52, 0x00, 0xB8, 0x04, 0x52, 0x00, 0xB8,\n0x08, 0x52, 0x00, 0xB8, 0x0C, 0x52, 0x00, 0xB8,\n0x10, 0x52, 0x00, 0xB8, 0x30, 0x52, 0x00, 0xB8,\n0x3C, 0x50, 0x00, 0xB8, 0x4C, 0x04, 0x64, 0xB8,\n0xB8, 0x01, 0x64, 0xB8, 0x7E, 0x04, 0x64, 0xB8,\n0x20, 0x04, 0x64, 0xB8, 0xAC, 0x04, 0x64, 0xB8,\n0x08, 0x10, 0x66, 0xB8, 0x04, 0x10, 0x66, 0xB8,\n0x0C, 0x10, 0x66, 0xB8, 0x7C, 0x04, 0x64, 0xB8,\n0xF4, 0x00, 0x60, 0xB8, 0x71, 0x00, 0x60, 0xB8,\n0xE4, 0x00, 0x60, 0xB8, 0xE6, 0x00, 0x60, 0xB8,\n0xE8, 0x00, 0x60, 0xB8, 0xE9, 0x00, 0x60, 0xB8,\n0xEA, 0x00, 0x60, 0xB8, 0xEB, 0x00, 0x60, 0xB8,\n0xE5, 0x00, 0x60, 0xB8, 0x44, 0x00, 0x02, 0x00,\n0xA0, 0x07, 0x64, 0xB8, 0x00, 0x00, 0x60, 0x83,\n0x00, 0x00, 0x60, 0x06, 0x00, 0x00, 0x60, 0x02,\n0xFF, 0xFF, 0xBF, 0xFD, 0x00, 0x00, 0x40, 0x02,\n0xFF, 0xFF, 0xDF, 0xFF, 0xBC, 0x01, 0x64, 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0x7C, 0x9A, 0x30, 0xF0, 0x20, 0x6A,\n0x03, 0xF0, 0x5C, 0x9A, 0x60, 0xDA, 0xF0, 0x17,\n0x47, 0xA0, 0x03, 0x6B, 0x4A, 0x32, 0x6C, 0xEA,\n0x30, 0xF0, 0x21, 0x6B, 0x90, 0xF3, 0x68, 0xA3,\n0x05, 0x73, 0x11, 0x61, 0x38, 0x22, 0x30, 0xF0,\n0x20, 0x6A, 0xA3, 0xF3, 0x48, 0x9A, 0x00, 0x6B,\n0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xC3, 0xF3,\n0x60, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0x03, 0xF0,\n0x5C, 0x9A, 0x60, 0xDA, 0xF0, 0x17, 0x06, 0x73,\n0x12, 0x61, 0x02, 0x5A, 0x24, 0x61, 0x30, 0xF0,\n0x20, 0x6A, 0xA3, 0xF3, 0x48, 0x9A, 0x00, 0x6B,\n0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xC3, 0xF3,\n0x64, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0x03, 0xF0,\n0x5C, 0x9A, 0x60, 0xDA, 0xF0, 0x17, 0x07, 0x73,\n0x12, 0x61, 0x03, 0x72, 0x10, 0x61, 0x30, 0xF0,\n0x20, 0x6A, 0xA3, 0xF3, 0x48, 0x9A, 0x00, 0x6B,\n0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xC3, 0xF3,\n0x68, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0x03, 0xF0,\n0x5C, 0x9A, 0x60, 0xDA, 0xF0, 0x17, 0x30, 0xF0,\n0x21, 0x6A, 0x90, 0xF3, 0x4A, 0xA2, 0x02, 0x72,\n0x14, 0x61, 0x6C, 0xA0, 0x03, 0x6A, 0x6C, 0xEA,\n0x10, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3,\n0x48, 0x9A, 0x00, 0x6B, 0x60, 0xC2, 0x30, 0xF0,\n0x20, 0x6A, 0xC3, 0xF3, 0x6C, 0x9A, 0x30, 0xF0,\n0x20, 0x6A, 0x03, 0xF0, 0x5C, 0x9A, 0x60, 0xDA,\n0xF0, 0x17, 0x91, 0x67, 0x80, 0x18, 0x14, 0x4D,\n0x06, 0x92, 0x0D, 0x22, 0x04, 0x6B, 0xC7, 0xA0,\n0x4F, 0xE3, 0x09, 0x6A, 0x44, 0xEB, 0xFF, 0x6D,\n0xCA, 0x36, 0x4C, 0xED, 0x03, 0x6A, 0x91, 0x67,\n0x4C, 0xEE, 0x80, 0x18, 0x63, 0x51, 0x0B, 0x97,\n0x0A, 0x91, 0x09, 0x90, 0x06, 0x63, 0x00, 0xEF,\n0xFD, 0x63, 0x05, 0x62, 0xFF, 0x6A, 0x4C, 0xEC,\n0xC0, 0x4C, 0x4C, 0xEC, 0x13, 0x5C, 0x33, 0x60,\n0x30, 0xF0, 0x20, 0x6A, 0x88, 0x34, 0x82, 0xF2,\n0x00, 0x4A, 0x89, 0xE2, 0x40, 0x9A, 0x00, 0xEA,\n0x85, 0x67, 0x80, 0x18, 0xA5, 0x45, 0x27, 0x10,\n0x85, 0x67, 0x80, 0x18, 0x01, 0x45, 0x23, 0x10,\n0x85, 0x67, 0x80, 0x18, 0x68, 0x45, 0x1F, 0x10,\n0x85, 0x67, 0x80, 0x18, 0x5C, 0x44, 0x1B, 0x10,\n0x85, 0x67, 0x80, 0x18, 0x40, 0x43, 0x17, 0x10,\n0x85, 0x67, 0x80, 0x18, 0x53, 0x45, 0x13, 0x10,\n0x85, 0x67, 0x80, 0x18, 0xB7, 0x43, 0x0F, 0x10,\n0x85, 0x67, 0x80, 0x18, 0xC4, 0x44, 0x0B, 0x10,\n0x85, 0x67, 0x80, 0x18, 0x57, 0x42, 0x07, 0x10,\n0x85, 0x67, 0x80, 0x18, 0x0B, 0x42, 0x03, 0x10,\n0x85, 0x67, 0x80, 0x18, 0x36, 0x42, 0x05, 0x97,\n0x03, 0x63, 0x00, 0xEF, 0x30, 0xF0, 0x20, 0x6A,\n0xA8, 0xF4, 0x08, 0x4A, 0x05, 0x6B, 0x07, 0xF7,\n0x64, 0xDA, 0x09, 0x6B, 0x07, 0xF7, 0x60, 0xDA,\n0x20, 0xE8, 0x00, 0x65, 0x30, 0xF0, 0x21, 0x6A,\n0x52, 0xF1, 0x10, 0x4A, 0x30, 0xF0, 0x21, 0x6C,\n0xC8, 0x42, 0xE7, 0x42, 0x31, 0xF7, 0x10, 0x4C,\n0xE8, 0x4E, 0x39, 0x4F, 0x00, 0x6B, 0xFF, 0xF4,\n0x60, 0xCA, 0x3F, 0xF5, 0x60, 0xCA, 0x40, 0xF0,\n0x60, 0xCA, 0x80, 0xF0, 0x60, 0xCA, 0x60, 0xCA,\n0xC0, 0xF0, 0x60, 0xCA, 0x40, 0xF1, 0x60, 0xCA,\n0x00, 0xF1, 0x60, 0xCA, 0x80, 0xF1, 0x64, 0xCA,\n0xC0, 0xF1, 0x64, 0xCA, 0x00, 0xF2, 0x64, 0xCA,\n0x02, 0x4A, 0x00, 0x6D, 0xEA, 0xEA, 0xA0, 0xDC,\n0x80, 0xF0, 0xA0, 0xDC, 0x00, 0xF1, 0xA0, 0xDC,\n0x80, 0xF1, 0xA0, 0xDC, 0x60, 0xC6, 0x04, 0x4C,\n0x01, 0x4E, 0xDC, 0x61, 0x30, 0xF0, 0x21, 0x6A,\n0x78, 0x67, 0xD2, 0xF2, 0x70, 0xDA, 0x20, 0xE8,\n0xFF, 0x6A, 0x8C, 0xEA, 0xF4, 0xF6, 0xA4, 0x42,\n0x30, 0xF0, 0x20, 0x6B, 0xA8, 0xF4, 0x08, 0x4B,\n0xA4, 0x35, 0x00, 0x6C, 0x75, 0xE5, 0x80, 0xCD,\n0xD4, 0xF6, 0xA4, 0x42, 0xA4, 0x35, 0x75, 0xE5,\n0x80, 0xCD, 0x14, 0xF7, 0xA4, 0x42, 0xA4, 0x35,\n0x75, 0xE5, 0x82, 0xCD, 0x34, 0xF7, 0xA4, 0x42,\n0x44, 0xF7, 0x14, 0x4A, 0xA4, 0x35, 0x44, 0x32,\n0x75, 0xE5, 0x6D, 0xE2, 0x82, 0xCD, 0x82, 0xCB,\n0x20, 0xE8, 0x00, 0x65, 0xFF, 0x6A, 0x8C, 0xEA,\n0x54, 0xF6, 0xA4, 0x42, 0x30, 0xF0, 0x20, 0x6B,\n0xA8, 0xF4, 0x08, 0x4B, 0xA4, 0x35, 0x00, 0x6C,\n0x75, 0xE5, 0x80, 0xCD, 0xB4, 0xF6, 0xA4, 0x42,\n0xA4, 0x35, 0x75, 0xE5, 0x80, 0xCD, 0x74, 0xF6,\n0xA4, 0x42, 0xA4, 0x35, 0x75, 0xE5, 0x80, 0xCD,\n0x94, 0xF6, 0xA4, 0x42, 0xA4, 0x35, 0x75, 0xE5,\n0x80, 0xCD, 0x2E, 0x6C, 0x98, 0xEA, 0xB2, 0x4C,\n0x12, 0xEA, 0x6D, 0xE2, 0xC8, 0xF1, 0x57, 0xA3,\n0x4C, 0xEC, 0xC8, 0xF1, 0x97, 0xC3, 0x20, 0xE8,\n0xFC, 0x63, 0x07, 0xD1, 0x06, 0xD0, 0x0D, 0x92,\n0xFF, 0xF7, 0x1F, 0x6B, 0x1B, 0x65, 0x02, 0xD2,\n0xCC, 0xEB, 0x00, 0xD3, 0x0C, 0x90, 0x02, 0x93,\n0xD8, 0x67, 0xFF, 0x69, 0x2C, 0xEC, 0xCC, 0xEF,\n0xCC, 0xEB, 0xCC, 0xE8, 0x2E, 0x6E, 0xD8, 0xEC,\n0x0E, 0x92, 0x30, 0xF0, 0x21, 0x6E, 0x70, 0xF6,\n0x00, 0x4E, 0x2C, 0xEA, 0x02, 0xD3, 0x03, 0xE7,\n0x78, 0x67, 0x6C, 0xE8, 0x12, 0xE9, 0x39, 0xE6,\n0x00, 0x91, 0x01, 0xD6, 0x3B, 0xE5, 0xFB, 0xE6,\n0x03, 0xD6, 0xF4, 0xF6, 0x24, 0x44, 0x30, 0xF0,\n0x20, 0x6E, 0x24, 0x31, 0xA8, 0xF4, 0x08, 0x4E,\n0xD9, 0xE1, 0x00, 0x91, 0x04, 0xD6, 0xC0, 0xAE,\n0x2F, 0xE3, 0xC2, 0xEB, 0x03, 0x61, 0x04, 0x93,\n0xD9, 0xE1, 0xC0, 0xCB, 0x30, 0xF0, 0x20, 0x6B,\n0xD4, 0xF6, 0xC4, 0x44, 0xA8, 0xF4, 0x08, 0x4B,\n0xC4, 0x36, 0x79, 0xE6, 0x60, 0xAE, 0xFF, 0xF7,\n0x1F, 0x69, 0xE7, 0xE1, 0x62, 0xE9, 0x02, 0x61,\n0x6D, 0xE7, 0x60, 0xCE, 0x30, 0xF0, 0x20, 0x6B,\n0xA8, 0xF4, 0x08, 0x4B, 0x29, 0xF6, 0xC8, 0x9B,\n0x0F, 0xE9, 0xC3, 0xE9, 0x03, 0x61, 0xC1, 0xE0,\n0x29, 0xF6, 0x08, 0xDB, 0x30, 0xF0, 0x20, 0x6E,\n0x14, 0xF7, 0x64, 0x44, 0xA8, 0xF4, 0x08, 0x4E,\n0x64, 0x33, 0xCD, 0xE3, 0x03, 0x91, 0xC2, 0xAB,\n0xFF, 0xF7, 0x1F, 0x68, 0x23, 0xE0, 0xC3, 0xE8,\n0x02, 0x61, 0xD9, 0xE1, 0xC2, 0xCB, 0x30, 0xF0,\n0x20, 0x6E, 0x54, 0xF7, 0x64, 0x44, 0xA8, 0xF4,\n0x08, 0x4E, 0x64, 0x33, 0xCD, 0xE3, 0x02, 0x91,\n0xC2, 0xAB, 0xFF, 0xF7, 0x1F, 0x68, 0x23, 0xE0,\n0xC2, 0xE8, 0x02, 0x61, 0xD9, 0xE1, 0xC2, 0xCB,\n0x30, 0xF0, 0x20, 0x6E, 0x34, 0xF7, 0x64, 0x44,\n0xA8, 0xF4, 0x08, 0x4E, 0x64, 0x33, 0xCD, 0xE3,\n0xC2, 0xAB, 0xFF, 0xF7, 0x1F, 0x68, 0xA3, 0xE0,\n0xC3, 0xE8, 0x02, 0x61, 0xD9, 0xE5, 0xC2, 0xCB,\n0x01, 0x96, 0x75, 0xAE, 0xFF, 0xF7, 0x1F, 0x6E,\n0xBB, 0xE6, 0xC3, 0xEB, 0x03, 0x60, 0x01, 0x90,\n0x6D, 0xE5, 0x75, 0xC8, 0x01, 0x91, 0xFF, 0xF7,\n0x1F, 0x6E, 0xBB, 0xE6, 0x76, 0xA9, 0xC3, 0xEB,\n0x02, 0x60, 0x75, 0xE5, 0xB6, 0xC9, 0x6A, 0x42,\n0xFF, 0x6D, 0xAC, 0xEB, 0x02, 0x5B, 0x00, 0x6B,\n0x0A, 0x61, 0x6C, 0x42, 0xAC, 0xEB, 0x02, 0x5B,\n0x01, 0x6B, 0x05, 0x61, 0x03, 0x22, 0x03, 0x72,\n0x03, 0x6B, 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0x05, 0x97, 0x04, 0x90, 0x03, 0x63,\n0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62,\n0x04, 0xD0, 0x30, 0xF0, 0x20, 0x6A, 0xE3, 0xF7,\n0x68, 0x9A, 0x02, 0x6C, 0xFF, 0xF7, 0x1F, 0x6D,\n0x40, 0x9B, 0xFF, 0x6E, 0x41, 0x4E, 0x8D, 0xEA,\n0x40, 0xDB, 0x30, 0xF0, 0x20, 0x6A, 0x23, 0xF1,\n0x60, 0x9A, 0xE0, 0xF3, 0x1E, 0x4C, 0x30, 0xF0,\n0x20, 0x68, 0x40, 0xAB, 0xAC, 0xEA, 0x8D, 0xEA,\n0xAC, 0xEA, 0x40, 0xCB, 0x02, 0x6C, 0x80, 0x18,\n0x1C, 0x6F, 0x80, 0xF3, 0x4C, 0x98, 0x0A, 0x6C,\n0x40, 0xEA, 0x00, 0x6C, 0xC0, 0x6D, 0x02, 0x6E,\n0x80, 0x18, 0x1C, 0x6F, 0x00, 0x6C, 0xC4, 0x67,\n0x02, 0xF0, 0x00, 0x6D, 0x80, 0x18, 0x1C, 0x6F,\n0x00, 0x6C, 0xC4, 0x67, 0x0C, 0xF0, 0x00, 0x6D,\n0x80, 0x18, 0x1C, 0x6F, 0x00, 0x6C, 0x01, 0xF0,\n0x00, 0x6D, 0x01, 0x6E, 0x80, 0x18, 0x1C, 0x6F,\n0x10, 0xF0, 0x00, 0x6D, 0x01, 0x6E, 0x00, 0x6C,\n0x80, 0x18, 0x1C, 0x6F, 0x80, 0xF3, 0x4C, 0x98,\n0x0A, 0x6C, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6A,\n0xA4, 0xF0, 0x70, 0x9A, 0xFF, 0x6C, 0x04, 0x6D,\n0x40, 0xA3, 0x8C, 0xEA, 0xAD, 0xEA, 0x8C, 0xEA,\n0x40, 0xC3, 0x05, 0x97, 0x04, 0x90, 0x03, 0x63,\n0x00, 0xEF, 0x00, 0x65, 0x00, 0x00, 0x00, 0x00,\n0x65, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\n};\n\nu32 array_length_mp_8822c_fw_hybrid = 169328;\n\nu8 array_mp_8822c_fw_nic[] = {\n0x22, 0x88, 0x00, 0x00, 0x07, 0x00, 0x0D, 0x00,\n0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,\n0x09, 0x12, 0x0E, 0x18, 0xE3, 0x07, 0x00, 0x00,\n0x18, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x20, 0x80, 0x48, 0x42, 0x00, 0x00,\n0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x60, 0xAA, 0x00, 0x00, 0xA0, 0xE6, 0x01, 0x00,\n0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80,\n0x00, 0x00, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08,\n0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,\n0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\n0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x03, 0x00, 0x01, 0xFE, 0x03, 0x01, 0x01, 0xFE,\n0x03, 0x02, 0x01, 0xFE, 0x03, 0x03, 0x01, 0xFE,\n0x03, 0x04, 0x01, 0xFE, 0x03, 0x05, 0x01, 0xFE,\n0x03, 0x06, 0x01, 0xFE, 0x03, 0x07, 0x01, 0xFE,\n0x48, 0x0A, 0x20, 0x80, 0x06, 0x00, 0x00, 0x00,\n0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,\n0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00,\n0x01, 0x00, 0x03, 0x80, 0x99, 0x01, 0x03, 0x80,\n0x99, 0x01, 0x03, 0x80, 0x08, 0x00, 0x00, 0x00,\n0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0xE0,\n0x4C, 0x81, 0x92, 0x01, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x8D,\n0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x07, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 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0xDC, 0x30, 0xF0,\n0x20, 0x6B, 0x29, 0xF1, 0x0B, 0x4B, 0x30, 0xF0,\n0x20, 0x6C, 0xE0, 0xF6, 0x60, 0xDC, 0x30, 0xF0,\n0x20, 0x6B, 0x29, 0xF1, 0x12, 0x4B, 0x30, 0xF0,\n0x20, 0x6C, 0xE0, 0xF6, 0x64, 0xDC, 0x30, 0xF0,\n0x20, 0x6B, 0xC0, 0xF6, 0x40, 0xDB, 0x20, 0xE8,\n0x30, 0xF0, 0x20, 0x6A, 0x30, 0xF0, 0x20, 0x6B,\n0x21, 0xF0, 0x00, 0x4B, 0x80, 0xF2, 0x08, 0x4A,\n0x13, 0x10, 0x80, 0x9A, 0x10, 0x2C, 0x30, 0xF0,\n0x20, 0x6C, 0xC3, 0xF1, 0xA4, 0x9C, 0x30, 0xF0,\n0x20, 0x6E, 0x43, 0xF1, 0xCC, 0x9E, 0x80, 0x9D,\n0xCD, 0xEC, 0x80, 0xDD, 0x30, 0xF0, 0x20, 0x6C,\n0xA4, 0xF0, 0x9C, 0x9C, 0x40, 0xDC, 0x04, 0x4A,\n0x43, 0xEB, 0xEB, 0x60, 0x20, 0xE8, 0x00, 0x65,\n0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF7, 0x54, 0x9A,\n0xE5, 0xF6, 0x1F, 0x6B, 0xFF, 0x6C, 0x60, 0xDA,\n0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF7, 0x58, 0x9A,\n0x10, 0x6B, 0x40, 0x6D, 0x60, 0xC2, 0x30, 0xF0,\n0x20, 0x6A, 0xA3, 0xF7, 0x5C, 0x9A, 0x01, 0x6B,\n0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF1,\n0x54, 0x9A, 0x60, 0xA2, 0x8C, 0xEB, 0xAD, 0xEB,\n0x8C, 0xEB, 0x60, 0xC2, 0x60, 0xA2, 0x07, 0x6D,\n0x8C, 0xEB, 0xAD, 0xEB, 0x8C, 0xEB, 0x60, 0xC2,\n0x80, 0xA2, 0xEF, 0x6B, 0x8C, 0xEB, 0x60, 0xC2,\n0x30, 0xF0, 0x20, 0x6A, 0xC3, 0xF7, 0x40, 0x9A,\n0x00, 0xF2, 0x01, 0x6C, 0x8B, 0xEC, 0x60, 0x9A,\n0x8C, 0xEB, 0x60, 0xDA, 0x60, 0x9A, 0x00, 0xF1,\n0x00, 0x4C, 0x8C, 0xEB, 0x60, 0xDA, 0x30, 0xF0,\n0x20, 0x6A, 0xC3, 0xF7, 0x64, 0x9A, 0x30, 0xF0,\n0x20, 0x6C, 0x63, 0xF1, 0x88, 0x9C, 0x40, 0x9B,\n0x8D, 0xEA, 0x40, 0xDB, 0x30, 0xF0, 0x20, 0x6A,\n0xC3, 0xF7, 0x48, 0x9A, 0x60, 0xA2, 0x04, 0x5B,\n0x02, 0x60, 0x04, 0x6B, 0x60, 0xC2, 0x30, 0xF0,\n0x20, 0x6A, 0xA3, 0xF1, 0x54, 0x9A, 0x7F, 0x6B,\n0x80, 0xA2, 0x8C, 0xEB, 0x60, 0xC2, 0x80, 0xA2,\n0xF7, 0x6B, 0x8C, 0xEB, 0x60, 0xC2, 0x20, 0xE8,\n0xFB, 0x63, 0x09, 0x62, 0x08, 0xD1, 0x07, 0xD0,\n0xFF, 0xF7, 0x1F, 0x69, 0x2C, 0xED, 0x30, 0xF0,\n0x20, 0x6B, 0x04, 0xD5, 0xC4, 0xF0, 0xA0, 0x9B,\n0xFF, 0x6A, 0x40, 0x6E, 0x60, 0xA5, 0xCB, 0xEE,\n0x4C, 0xEC, 0x4C, 0xEB, 0xCC, 0xEB, 0x6D, 0xEC,\n0x4C, 0xEC, 0x80, 0xC5, 0x30, 0xF0, 0x20, 0x6A,\n0x80, 0xF3, 0x4C, 0x9A, 0x0A, 0x6C, 0x40, 0xEA,\n0x30, 0xF0, 0x20, 0x6A, 0xC4, 0xF0, 0x44, 0x9A,\n0x00, 0xAA, 0x04, 0x92, 0x2C, 0xE8, 0x2A, 0xEA,\n0x0B, 0x60, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF3,\n0x44, 0x9A, 0x04, 0x94, 0x40, 0xEA, 0x04, 0x93,\n0x2C, 0xEA, 0x6C, 0xE8, 0x07, 0xEA, 0x2C, 0xE8,\n0x50, 0x67, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90,\n0x05, 0x63, 0x00, 0xEF, 0xFA, 0x63, 0x0B, 0x62,\n0x0A, 0xD1, 0x09, 0xD0, 0xFF, 0xF7, 0x1F, 0x69,\n0x2C, 0xED, 0xFF, 0x68, 0x0C, 0xEC, 0x2C, 0xEE,\n0x2A, 0xED, 0x05, 0xD4, 0x04, 0xD5, 0x06, 0xD6,\n0x1F, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0xC4, 0xF0,\n0x60, 0x9A, 0x40, 0x6C, 0x8B, 0xEC, 0x40, 0xA3,\n0x0C, 0xEA, 0x8C, 0xEA, 0x05, 0x94, 0x8D, 0xEA,\n0x0C, 0xEA, 0x40, 0xC3, 0x30, 0xF0, 0x20, 0x6A,\n0xC4, 0xF0, 0x64, 0x9A, 0x30, 0xF0, 0x20, 0x6C,\n0xA3, 0xF4, 0x8C, 0x9C, 0x40, 0x9B, 0x8C, 0xEA,\n0x30, 0xF0, 0x20, 0x6C, 0xA3, 0xF0, 0x8C, 0x9C,\n0x8D, 0xEA, 0xCD, 0xEA, 0x40, 0xDB, 0x34, 0x10,\n0x05, 0x94, 0xB1, 0x67, 0x80, 0x18, 0xFA, 0x78,\n0x07, 0xD2, 0x30, 0xF0, 0x20, 0x6A, 0x04, 0x94,\n0xA0, 0xF3, 0x44, 0x9A, 0x40, 0xEA, 0x30, 0xF0,\n0x20, 0x6B, 0xC4, 0xF0, 0x80, 0x9B, 0x40, 0x6D,\n0xAB, 0xED, 0x60, 0xA4, 0x2C, 0xEA, 0x0C, 0xEB,\n0xAC, 0xEB, 0x05, 0x95, 0xAD, 0xEB, 0x0C, 0xEB,\n0x60, 0xC4, 0x30, 0xF0, 0x20, 0x6B, 0xC4, 0xF0,\n0x84, 0x9B, 0x30, 0xF0, 0x20, 0x6D, 0xA3, 0xF4,\n0xAC, 0x9D, 0x60, 0x9C, 0x06, 0x96, 0xAC, 0xEB,\n0x30, 0xF0, 0x20, 0x6D, 0xA3, 0xF0, 0xAC, 0x9D,\n0xC4, 0xEA, 0x46, 0x67, 0xAD, 0xEB, 0x04, 0x95,\n0x07, 0x96, 0xAC, 0xEA, 0xAF, 0xED, 0xCC, 0xED,\n0xAD, 0xEA, 0x2C, 0xEA, 0x4D, 0xEB, 0x60, 0xDC,\n0x30, 0xF0, 0x20, 0x6A, 0x80, 0xF3, 0x4C, 0x9A,\n0x0A, 0x6C, 0x40, 0xEA, 0x0B, 0x97, 0x0A, 0x91,\n0x09, 0x90, 0x06, 0x63, 0x00, 0xEF, 0x00, 0x65,\n0xFD, 0x63, 0x05, 0x62, 0x00, 0x6C, 0x10, 0xF0,\n0x00, 0x6D, 0x80, 0x18, 0xFA, 0x78, 0x05, 0x97,\n0x01, 0x5A, 0x58, 0x67, 0x03, 0x63, 0x00, 0xEF,\n0xFD, 0x63, 0x05, 0x62, 0x04, 0xD0, 0x30, 0xF0,\n0x20, 0x6B, 0x63, 0xF0, 0x7C, 0x9B, 0x10, 0xF0,\n0x32, 0x6A, 0x5C, 0xF5, 0x09, 0x4A, 0x40, 0xDB,\n0x00, 0x68, 0x31, 0x10, 0x82, 0xF3, 0x08, 0x70,\n0x1A, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0xC3, 0xF1,\n0x64, 0x9A, 0x02, 0xF0, 0x00, 0x6C, 0x40, 0x9B,\n0x8D, 0xEA, 0x40, 0xDB, 0x30, 0xF0, 0x20, 0x6A,\n0x29, 0xF0, 0x08, 0x4A, 0x83, 0xF3, 0x78, 0x9A,\n0x8D, 0xEB, 0x83, 0xF3, 0x78, 0xDA, 0x30, 0xF0,\n0x20, 0x6A, 0xA3, 0xF1, 0x40, 0x9A, 0x03, 0x6B,\n0x6B, 0xEB, 0x60, 0xC2, 0x18, 0x10, 0xFF, 0xF7,\n0x1F, 0x6A, 0x01, 0x48, 0x4C, 0xE8, 0x30, 0xF0,\n0x20, 0x6A, 0x80, 0xF3, 0x4C, 0x9A, 0x14, 0x6C,\n0x40, 0xEA, 0x33, 0x58, 0x08, 0x61, 0x30, 0xF0,\n0x20, 0x6A, 0x03, 0xF7, 0x5C, 0x9A, 0x60, 0xA2,\n0x08, 0x6A, 0x6C, 0xEA, 0x04, 0x2A, 0x80, 0x18,\n0x4C, 0x79, 0x01, 0x72, 0xCB, 0x61, 0x30, 0xF0,\n0x20, 0x6A, 0xA3, 0xF1, 0x40, 0x9A, 0x02, 0x6B,\n0x6B, 0xEB, 0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6B,\n0x63, 0xF0, 0x7C, 0x9B, 0x10, 0xF0, 0x32, 0x6A,\n0x5C, 0xF5, 0x0A, 0x4A, 0x40, 0xDB, 0x05, 0x97,\n0x04, 0x90, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65,\n0xFD, 0x63, 0x05, 0x62, 0x04, 0xD0, 0x30, 0xF0,\n0x20, 0x6A, 0xA3, 0xF7, 0x60, 0x9A, 0x02, 0x6C,\n0xFF, 0xF7, 0x1F, 0x6D, 0x40, 0x9B, 0xFF, 0x6E,\n0x41, 0x4E, 0x8D, 0xEA, 0x40, 0xDB, 0x30, 0xF0,\n0x20, 0x6A, 0x83, 0xF1, 0x60, 0x9A, 0xE0, 0xF3,\n0x1E, 0x4C, 0x30, 0xF0, 0x20, 0x68, 0x40, 0xAB,\n0xAC, 0xEA, 0x8D, 0xEA, 0xAC, 0xEA, 0x40, 0xCB,\n0x02, 0x6C, 0x80, 0x18, 0x15, 0x79, 0x80, 0xF3,\n0x4C, 0x98, 0x0A, 0x6C, 0x40, 0xEA, 0x00, 0x6C,\n0xC0, 0x6D, 0x02, 0x6E, 0x80, 0x18, 0x15, 0x79,\n0x00, 0x6C, 0xC4, 0x67, 0x02, 0xF0, 0x00, 0x6D,\n0x80, 0x18, 0x15, 0x79, 0x00, 0x6C, 0xC4, 0x67,\n0x0C, 0xF0, 0x00, 0x6D, 0x80, 0x18, 0x15, 0x79,\n0x00, 0x6C, 0x01, 0xF0, 0x00, 0x6D, 0x01, 0x6E,\n0x80, 0x18, 0x15, 0x79, 0x10, 0xF0, 0x00, 0x6D,\n0x01, 0x6E, 0x00, 0x6C, 0x80, 0x18, 0x15, 0x79,\n0x80, 0xF3, 0x4C, 0x98, 0x0A, 0x6C, 0x40, 0xEA,\n0x30, 0xF0, 0x20, 0x6A, 0xC4, 0xF0, 0x68, 0x9A,\n0xFF, 0x6C, 0x04, 0x6D, 0x40, 0xA3, 0x8C, 0xEA,\n0xAD, 0xEA, 0x8C, 0xEA, 0x40, 0xC3, 0x05, 0x97,\n0x04, 0x90, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65,\n0x2B, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\n};\n\nu32 array_length_mp_8822c_fw_nic = 185248;\n\nu8 array_mp_8822c_fw_spic[] = {\n0x22, 0x88, 0x00, 0x00, 0x07, 0x00, 0x0D, 0x00,\n0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,\n0x09, 0x12, 0x0E, 0x1B, 0xE3, 0x07, 0x00, 0x00,\n0x18, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x20, 0x80, 0x68, 0x1B, 0x00, 0x00,\n0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n0xC8, 0x62, 0x00, 0x00, 0xF0, 0x40, 0x01, 0x00,\n0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80,\n0x00, 0x00, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08,\n0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,\n0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\n0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x03, 0x00, 0x01, 0xFE, 0x03, 0x01, 0x01, 0xFE,\n0x03, 0x02, 0x01, 0xFE, 0x03, 0x03, 0x01, 0xFE,\n0x03, 0x04, 0x01, 0xFE, 0x03, 0x05, 0x01, 0xFE,\n0x03, 0x06, 0x01, 0xFE, 0x03, 0x07, 0x01, 0xFE,\n0x48, 0x0A, 0x20, 0x80, 0x06, 0x00, 0x00, 0x00,\n0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,\n0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00,\n0x01, 0x00, 0x03, 0x80, 0xBD, 0x01, 0x03, 0x80,\n0xBD, 0x01, 0x03, 0x80, 0x08, 0x00, 0x00, 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0x01, 0x64, 0xB8,\n0x3C, 0x11, 0x64, 0xB8, 0x38, 0x11, 0x64, 0xB8,\n0xE4, 0x11, 0x64, 0xB8, 0xE0, 0x11, 0x64, 0xB8,\n0xE0, 0x12, 0x64, 0xB8, 0xE8, 0x10, 0x60, 0xB8,\n0x00, 0x3C, 0x64, 0xB8, 0x00, 0x4C, 0x64, 0xB8,\n0x00, 0x58, 0x64, 0xB8, 0x00, 0x5C, 0x64, 0xB8,\n0xF8, 0x05, 0x64, 0xB8, 0x92, 0x06, 0x64, 0xB8,\n0xC0, 0x01, 0x64, 0xB8, 0x1F, 0x07, 0x64, 0xB8,\n0x1C, 0x07, 0x64, 0xB8, 0xB8, 0x05, 0x64, 0xB8,\n0xBC, 0x05, 0x64, 0xB8, 0x5F, 0x11, 0x64, 0xB8,\n0xFE, 0xFF, 0xFF, 0x7F, 0x30, 0x00, 0x78, 0x18,\n0x70, 0x00, 0x60, 0xB8, 0x1C, 0x00, 0x60, 0xB8,\n0x00, 0x08, 0x70, 0xB8, 0xA0, 0x34, 0x00, 0xB8,\n0x00, 0x52, 0x00, 0xB8, 0x04, 0x52, 0x00, 0xB8,\n0x08, 0x52, 0x00, 0xB8, 0x0C, 0x52, 0x00, 0xB8,\n0x10, 0x52, 0x00, 0xB8, 0x30, 0x52, 0x00, 0xB8,\n0x3C, 0x50, 0x00, 0xB8, 0x4C, 0x04, 0x64, 0xB8,\n0x50, 0x04, 0x64, 0xB8, 0xA4, 0x04, 0x64, 0xB8,\n0xA8, 0x04, 0x64, 0xB8, 0xB8, 0x01, 0x64, 0xB8,\n0x7E, 0x04, 0x64, 0xB8, 0x20, 0x04, 0x64, 0xB8,\n0xAC, 0x04, 0x64, 0xB8, 0x08, 0x10, 0x66, 0xB8,\n0x00, 0x10, 0x66, 0xB8, 0x04, 0x10, 0x66, 0xB8,\n0x0C, 0x10, 0x66, 0xB8, 0x7D, 0x04, 0x64, 0xB8,\n0x7C, 0x04, 0x64, 0xB8, 0xF4, 0x00, 0x60, 0xB8,\n0x71, 0x00, 0x60, 0xB8, 0xE4, 0x00, 0x60, 0xB8,\n0xE6, 0x00, 0x60, 0xB8, 0xE8, 0x00, 0x60, 0xB8,\n0xE9, 0x00, 0x60, 0xB8, 0xEA, 0x00, 0x60, 0xB8,\n0xEB, 0x00, 0x60, 0xB8, 0xE5, 0x00, 0x60, 0xB8,\n0x44, 0x00, 0x02, 0x00, 0xA0, 0x07, 0x64, 0xB8,\n0xFF, 0xFF, 0xFF, 0x7F, 0xBC, 0x01, 0x64, 0xB8,\n0x9A, 0x01, 0x64, 0xB8, 0x98, 0x01, 0x64, 0xB8,\n0xC7, 0x01, 0x64, 0xB8, 0x90, 0x00, 0x60, 0xB8,\n0x00, 0x01, 0x64, 0xB8, 0xD0, 0x05, 0x64, 0xB8,\n0x08, 0x06, 0x64, 0xB8, 0xA0, 0x06, 0x64, 0xB8,\n0xFF, 0xFF, 0xFB, 0xFF, 0xC2, 0x01, 0x64, 0xB8,\n0x08, 0x90, 0x00, 0xB8, 0x00, 0x90, 0x00, 0xB8,\n0x10, 0x90, 0x00, 0xB8, 0x04, 0x90, 0x00, 0xB8,\n0x18, 0x91, 0x00, 0xB8, 0x1C, 0x91, 0x00, 0xB8,\n0x60, 0x90, 0x00, 0xB8, 0x28, 0x90, 0x00, 0xB8,\n0x40, 0x00, 0x60, 0xB8, 0x20, 0x91, 0x00, 0xB8,\n0x2C, 0x90, 0x00, 0xB8, 0x04, 0x06, 0x64, 0xB8,\n0xFF, 0xFF, 0xFF, 0xFE, 0x60, 0x16, 0x64, 0xB8,\n0x7A, 0x04, 0x64, 0xB8, 0x20, 0x00, 0x78, 0xB8,\n0x10, 0x00, 0x78, 0xB8, 0x03, 0x00, 0x78, 0xB8,\n0xFF, 0xFF, 0x01, 0xFF, 0x05, 0x00, 0x78, 0xB8,\n0x12, 0x05, 0x64, 0xB8, 0x10, 0x05, 0x64, 0xB8,\n0x09, 0x00, 0x78, 0xB8, 0x14, 0x00, 0x78, 0xB8,\n0x00, 0x00, 0x00, 0x00, 0x15, 0xF0, 0xFF, 0x0F,\n0x00, 0x00, 0x00, 0x00, 0x15, 0xF0, 0x0F, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x05, 0xF0, 0xFF, 0x0F,\n0x00, 0x00, 0x00, 0x00, 0x05, 0xF0, 0x0F, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x10, 0xF0, 0xFF, 0x0F,\n0x00, 0x00, 0x00, 0x00, 0x10, 0xF0, 0x0F, 0x00,\n0x00, 0x00, 0x00, 0x00, 0xF5, 0x0F, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0xFF,\n0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x3F, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x15, 0xF0, 0x3F, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x15, 0xF0, 0xFF, 0xFF,\n0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0xFF,\n0xFF, 0x03, 0x00, 0x00, 0x15, 0xF0, 0xFF, 0xFF,\n0x0F, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x06,\n0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF,\n0xFF, 0x00, 0x01, 0x02, 0x02, 0x04, 0x05, 0x06,\n0x07, 0x08, 0x09, 0x0A, 0x28, 0x28, 0x32, 0x28,\n0x1E, 0x19, 0x19, 0x19, 0x18, 0x18, 0x12, 0x0F,\n0x1E, 0x1E, 0x19, 0x1E, 0x18, 0x16, 0x0C, 0x0C,\n0x1E, 0x1E, 0x19, 0x1E, 0x18, 0x16, 0x0C, 0x0C,\n0x1E, 0x1E, 0x19, 0x1C, 0x18, 0x14, 0x0C, 0x0A,\n0x1E, 0x1E, 0x19, 0x1E, 0x19, 0x18, 0x0F, 0x0E,\n0x1E, 0x1E, 0x1E, 0x1E, 0x1C, 0x16, 0x14, 0x12,\n0x0C, 0x0A, 0x1E, 0x1E, 0x1E, 0x1E, 0x1A, 0x16,\n0x12, 0x10, 0x0C, 0x0A, 0x1E, 0x1E, 0x1E, 0x1E,\n0x18, 0x16, 0x0D, 0x0E, 0x0C, 0x0A, 0x0A, 0x0A,\n0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,\n0x12, 0x12, 0x14, 0x12, 0x0F, 0x0F, 0x0C, 0x0C,\n0x09, 0x08, 0x08, 0x07, 0x0A, 0x0A, 0x09, 0x07,\n0x07, 0x06, 0x05, 0x04, 0x0C, 0x0C, 0x0A, 0x0A,\n0x09, 0x07, 0x07, 0x06, 0x0C, 0x0C, 0x0A, 0x0A,\n0x09, 0x07, 0x07, 0x06, 0x0C, 0x0C, 0x0A, 0x0A,\n0x09, 0x07, 0x07, 0x06, 0x0A, 0x0A, 0x08, 0x08,\n0x08, 0x07, 0x07, 0x06, 0x04, 0x04, 0x0C, 0x0C,\n0x0A, 0x0A, 0x09, 0x07, 0x07, 0x06, 0x05, 0x04,\n0x0C, 0x0C, 0x0A, 0x0A, 0x09, 0x07, 0x07, 0x06,\n0x05, 0x04, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,\n0x0A, 0x0A, 0x0A, 0x0A, 0x02, 0x02, 0x02, 0x04,\n0x02, 0x04, 0x06, 0x06, 0x08, 0x08, 0x09, 0x09,\n0x03, 0x06, 0x08, 0x08, 0x0A, 0x0E, 0x10, 0x18,\n0x05, 0x08, 0x08, 0x08, 0x0A, 0x0E, 0x10, 0x18,\n0x05, 0x08, 0x08, 0x09, 0x10, 0x14, 0x1C, 0x20,\n0x04, 0x06, 0x08, 0x0A, 0x10, 0x18, 0x18, 0x20,\n0x03, 0x06, 0x08, 0x09, 0x10, 0x14, 0x1C, 0x24,\n0x34, 0x3A, 0x05, 0x07, 0x09, 0x0A, 0x10, 0x14,\n0x1C, 0x28, 0x34, 0x3C, 0x06, 0x08, 0x0A, 0x0C,\n0x12, 0x18, 0x1E, 0x2E, 0x36, 0x40, 0x0A, 0x0C,\n0x0C, 0x12, 0x16, 0x1C, 0x20, 0x2E, 0x36, 0x40,\n0x2C, 0x00, 0x04, 0x00, 0x2D, 0x00, 0x2C, 0x01,\n0x2D, 0x01, 0x2C, 0x02, 0x2E, 0x01, 0xFF, 0x00,\n0x2D, 0x02, 0xFF, 0x00, 0x36, 0x2D, 0xFF, 0x36,\n0x2E, 0xFF, 0x37, 0x2F, 0xFF, 0x38, 0x30, 0xFF,\n0x39, 0x31, 0xFF, 0x3A, 0x32, 0xFF, 0x3A, 0x33,\n0xFF, 0x3A, 0x34, 0xFF, 0x3A, 0x35, 0xFF, 0x3B,\n0xFF, 0xFF, 0x37, 0x2E, 0xFF, 0x38, 0x30, 0xFF,\n0x39, 0x31, 0xFF, 0x3A, 0x32, 0xFF, 0x3B, 0x35,\n0xFF, 0x3C, 0xFF, 0xFF, 0x3D, 0xFF, 0xFF, 0x3E,\n0xFF, 0xFF, 0x3F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n0x37, 0xFF, 0x2F, 0x39, 0xFF, 0x31, 0xFF, 0x3A,\n0x33, 0xFF, 0x3B, 0x35, 0xFF, 0x3D, 0xFF, 0xFF,\n0xFF, 0x3E, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00,\n0x0D, 0x14, 0xFF, 0x15, 0x0E, 0xFF, 0x15, 0x0F,\n0xFF, 0x16, 0x10, 0xFF, 0x17, 0x11, 0xFF, 0x18,\n0x12, 0xFF, 0x18, 0x13, 0xFF, 0x18, 0xFF, 0xFF,\n0x15, 0x0E, 0xFF, 0x16, 0x10, 0xFF, 0x17, 0x10,\n0xFF, 0x18, 0x11, 0xFF, 0x19, 0xFF, 0xFF, 0x1A,\n0xFF, 0xFF, 0x1B, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n0x15, 0x13, 0x0F, 0x17, 0x1E, 0x11, 0x18, 0x1F,\n0x13, 0x20, 0x19, 0xFF, 0x21, 0x1B, 0xFF, 0x22,\n0xFF, 0xFF, 0x23, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n0x04, 0x04, 0x04, 0x36, 0x2C, 0xFF, 0x2D, 0xFF,\n0xFF, 0x2E, 0x37, 0xFF, 0x38, 0x2F, 0xFF, 0x39,\n0x30, 0xFF, 0x39, 0x31, 0xFF, 0x39, 0x32, 0xFF,\n0x3A, 0x33, 0xFF, 0x3A, 0x34, 0xFF, 0x2D, 0x2C,\n0xFF, 0x36, 0x2E, 0xFF, 0x37, 0x2F, 0xFF, 0x38,\n0x30, 0xFF, 0x33, 0x39, 0xFF, 0x35, 0x3A, 0xFF,\n0x3B, 0x34, 0xFF, 0x3C, 0x3B, 0xFF, 0x3D, 0x3C,\n0xFF, 0x3E, 0x3D, 0xFF, 0x37, 0x2E, 0xFF, 0x38,\n0x2F, 0xFF, 0x39, 0x31, 0xFF, 0x3A, 0xFF, 0xFF,\n0xFF, 0x3B, 0xFF, 0xFF, 0x3C, 0xFF, 0xFF, 0x3D,\n0x3C, 0xFF, 0x3F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n0xFF, 0xFF, 0x00, 0x00, 0x04, 0xFF, 0xFF, 0x0C,\n0xFF, 0xFF, 0x0D, 0x14, 0xFF, 0x0E, 0x15, 0xFF,\n0x16, 0x0F, 0xFF, 0x17, 0x10, 0xFF, 0x17, 0x11,\n0xFF, 0x17, 0x12, 0xFF, 0x0D, 0x0C, 0xFF, 0x14,\n0x0E, 0xFF, 0x15, 0x0F, 0xFF, 0x16, 0x10, 0xFF,\n0x17, 0x12, 0xFF, 0x18, 0x13, 0xFF, 0x19, 0x13,\n0xFF, 0x1A, 0x13, 0xFF, 0x14, 0x0E, 0xFF, 0x15,\n0x1C, 0xFF, 0x17, 0x1D, 0x11, 0x18, 0x1E, 0x13,\n0x19, 0x1F, 0x1E, 0x20, 0x1A, 0x1F, 0x21, 0x1B,\n0x20, 0x22, 0x21, 0x1B, 0x01, 0x00, 0x02, 0x00,\n0x05, 0x00, 0x0B, 0x00, 0x06, 0x00, 0x09, 0x00,\n0x0C, 0x00, 0x12, 0x00, 0x18, 0x00, 0x24, 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0x63,\n0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62,\n0x00, 0x6C, 0x10, 0xF0, 0x00, 0x6D, 0x80, 0x18,\n0x8D, 0x4F, 0x05, 0x97, 0x01, 0x5A, 0x58, 0x67,\n0x03, 0x63, 0x00, 0xEF, 0xFD, 0x63, 0x05, 0x62,\n0x04, 0xD0, 0x30, 0xF0, 0x20, 0x6B, 0xE2, 0xF1,\n0x78, 0x9B, 0x10, 0xF0, 0x31, 0x6A, 0x87, 0xF7,\n0x15, 0x4A, 0x40, 0xDB, 0x00, 0x68, 0x31, 0x10,\n0x82, 0xF3, 0x08, 0x70, 0x1A, 0x61, 0x30, 0xF0,\n0x20, 0x6A, 0x42, 0xF2, 0x78, 0x9A, 0x02, 0xF0,\n0x00, 0x6C, 0x40, 0x9B, 0x8D, 0xEA, 0x40, 0xDB,\n0x30, 0xF0, 0x20, 0x6A, 0xC3, 0xF3, 0x18, 0x4A,\n0x23, 0xF3, 0x6C, 0x9A, 0x8D, 0xEB, 0x23, 0xF3,\n0x6C, 0xDA, 0x30, 0xF0, 0x20, 0x6A, 0xC2, 0xF6,\n0x58, 0x9A, 0x03, 0x6B, 0x6B, 0xEB, 0x60, 0xC2,\n0x18, 0x10, 0xFF, 0xF7, 0x1F, 0x6A, 0x01, 0x48,\n0x4C, 0xE8, 0x30, 0xF0, 0x20, 0x6A, 0x80, 0xF3,\n0x4C, 0x9A, 0x14, 0x6C, 0x40, 0xEA, 0x33, 0x58,\n0x08, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0x82, 0xF5,\n0x54, 0x9A, 0x60, 0xA2, 0x08, 0x6A, 0x6C, 0xEA,\n0x04, 0x2A, 0x80, 0x18, 0xDF, 0x4F, 0x01, 0x72,\n0xCB, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0xC2, 0xF6,\n0x58, 0x9A, 0x02, 0x6B, 0x6B, 0xEB, 0x60, 0xC2,\n0x30, 0xF0, 0x20, 0x6B, 0xE2, 0xF1, 0x78, 0x9B,\n0x10, 0xF0, 0x31, 0x6A, 0x87, 0xF7, 0x16, 0x4A,\n0x40, 0xDB, 0x05, 0x97, 0x04, 0x90, 0x03, 0x63,\n0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62,\n0x04, 0xD0, 0x30, 0xF0, 0x20, 0x6A, 0xC2, 0xF6,\n0x7C, 0x9A, 0x02, 0x6C, 0xFF, 0xF7, 0x1F, 0x6D,\n0x40, 0x9B, 0xFF, 0x6E, 0x41, 0x4E, 0x8D, 0xEA,\n0x40, 0xDB, 0x30, 0xF0, 0x20, 0x6A, 0xE2, 0xF6,\n0x60, 0x9A, 0xE0, 0xF3, 0x1E, 0x4C, 0x30, 0xF0,\n0x20, 0x68, 0x40, 0xAB, 0xAC, 0xEA, 0x8D, 0xEA,\n0xAC, 0xEA, 0x40, 0xCB, 0x02, 0x6C, 0x80, 0x18,\n0xA8, 0x4F, 0x80, 0xF3, 0x4C, 0x98, 0x0A, 0x6C,\n0x40, 0xEA, 0x00, 0x6C, 0xC0, 0x6D, 0x02, 0x6E,\n0x80, 0x18, 0xA8, 0x4F, 0x00, 0x6C, 0xC4, 0x67,\n0x02, 0xF0, 0x00, 0x6D, 0x80, 0x18, 0xA8, 0x4F,\n0x00, 0x6C, 0xC4, 0x67, 0x0C, 0xF0, 0x00, 0x6D,\n0x80, 0x18, 0xA8, 0x4F, 0x00, 0x6C, 0x01, 0xF0,\n0x00, 0x6D, 0x01, 0x6E, 0x80, 0x18, 0xA8, 0x4F,\n0x10, 0xF0, 0x00, 0x6D, 0x01, 0x6E, 0x00, 0x6C,\n0x80, 0x18, 0xA8, 0x4F, 0x80, 0xF3, 0x4C, 0x98,\n0x0A, 0x6C, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6A,\n0xE2, 0xF6, 0x64, 0x9A, 0xFF, 0x6C, 0x04, 0x6D,\n0x40, 0xA3, 0x8C, 0xEA, 0xAD, 0xEA, 0x8C, 0xEA,\n0x40, 0xC3, 0x05, 0x97, 0x04, 0x90, 0x03, 0x63,\n0x00, 0xEF, 0x00, 0x65, 0x00, 0x00, 0x00, 0x00,\n0x28, 0x95, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\n};\n\nu32 array_length_mp_8822c_fw_spic = 114552;\n\n#ifdef CONFIG_WOWLAN\n\nu8 array_mp_8822c_fw_wowlan[] = {\n0x22, 0x88, 0x00, 0x00, 0x07, 0x00, 0x0D, 0x00,\n0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,\n0x09, 0x12, 0x0E, 0x19, 0xE3, 0x07, 0x00, 0x00,\n0x18, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x20, 0x80, 0x68, 0x2F, 0x00, 0x00,\n0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x20, 0x8D, 0x00, 0x00, 0x28, 0x48, 0x01, 0x00,\n0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80,\n0x00, 0x00, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08,\n0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,\n0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\n0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x03, 0x00, 0x01, 0xFE, 0x03, 0x01, 0x01, 0xFE,\n0x03, 0x02, 0x01, 0xFE, 0x03, 0x03, 0x01, 0xFE,\n0x03, 0x04, 0x01, 0xFE, 0x03, 0x05, 0x01, 0xFE,\n0x03, 0x06, 0x01, 0xFE, 0x03, 0x07, 0x01, 0xFE,\n0x48, 0x0A, 0x20, 0x80, 0x06, 0x00, 0x00, 0x00,\n0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,\n0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00,\n0x01, 0x00, 0x03, 0x80, 0x95, 0x01, 0x03, 0x80,\n0x95, 0x01, 0x03, 0x80, 0x08, 0x00, 0x00, 0x00,\n0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0xE0,\n0x4C, 0x81, 0x92, 0x01, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x8D,\n0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x07, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 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0xB8,\n0x78, 0x06, 0x64, 0xB8, 0x00, 0x00, 0x01, 0x80,\n0x74, 0x06, 0x64, 0xB8, 0x98, 0x06, 0x64, 0xB8,\n0x9C, 0x06, 0x64, 0xB8, 0x54, 0x06, 0x64, 0xB8,\n0x58, 0x06, 0x64, 0xB8, 0x5C, 0x06, 0x64, 0xB8,\n0xFF, 0xFF, 0xFF, 0x8F, 0x00, 0x00, 0x60, 0xB8,\n0x00, 0x00, 0x64, 0xB8, 0xBF, 0x01, 0x64, 0xB8,\n0x89, 0x00, 0x60, 0xB8, 0x8A, 0x00, 0x60, 0xB8,\n0x1A, 0x04, 0x64, 0xB8, 0x1B, 0x04, 0x64, 0xB8,\n0x8C, 0x00, 0x60, 0xB8, 0x01, 0x00, 0xFF, 0x00,\n0xF4, 0x11, 0x64, 0xB8, 0x58, 0x05, 0x64, 0xB8,\n0xE2, 0x10, 0x60, 0xB8, 0x30, 0x01, 0x64, 0xB8,\n0x20, 0x01, 0x64, 0xB8, 0x20, 0x11, 0x64, 0xB8,\n0x01, 0x8F, 0x00, 0xF0, 0x28, 0x11, 0x64, 0xB8,\n0x30, 0x11, 0x64, 0xB8, 0x38, 0x11, 0x64, 0xB8,\n0xE0, 0x11, 0x64, 0xB8, 0x50, 0x00, 0x60, 0xB8,\n0x38, 0x01, 0x64, 0xB8, 0x18, 0x34, 0x00, 0xB8,\n0x88, 0x10, 0x60, 0xB8, 0xFB, 0x11, 0x64, 0xB8,\n0xFA, 0x11, 0x64, 0xB8, 0xF8, 0x11, 0x64, 0xB8,\n0xC6, 0x04, 0x64, 0xB8, 0x00, 0x00, 0x66, 0xB8,\n0x02, 0x00, 0x60, 0xB8, 0xBF, 0xD8, 0xF1, 0x02,\n0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x01, 0x00,\n0x00, 0x00, 0x00, 0x41, 0xB7, 0xD8, 0xF1, 0x02,\n0x28, 0x06, 0x64, 0xB8, 0x00, 0x00, 0x80, 0xC0,\n0x2C, 0x06, 0x64, 0xB8, 0x00, 0x00, 0x00, 0x10,\n0x00, 0x00, 0x00, 0x20, 0x62, 0x06, 0x64, 0xB8,\n0x00, 0x00, 0x0F, 0x00, 0x00, 0x01, 0x64, 0xB8,\n0x2C, 0x02, 0x64, 0xB8, 0x44, 0x02, 0x64, 0xB8,\n0x4C, 0x02, 0x64, 0xB8, 0x54, 0x02, 0x64, 0xB8,\n0xD8, 0x04, 0x64, 0xB8, 0xDC, 0x04, 0x64, 0xB8,\n0x7D, 0x04, 0x64, 0xB8, 0xC7, 0x01, 0x64, 0xB8,\n0x90, 0x06, 0x64, 0xB8, 0x80, 0x00, 0x60, 0xB8,\n0x00, 0x00, 0x80, 0x00, 0xFF, 0xFF, 0x7F, 0xFF,\n0x00, 0x00, 0x78, 0xB8, 0xA0, 0x00, 0x78, 0xB8,\n0x30, 0x00, 0x78, 0xB8, 0xA4, 0x04, 0x64, 0xB8,\n0xA8, 0x04, 0x64, 0xB8, 0xF8, 0x10, 0x60, 0xB8,\n0x00, 0x00, 0x20, 0x00, 0x10, 0x02, 0x64, 0xB8,\n0x88, 0x02, 0x64, 0xB8, 0xE2, 0x04, 0x64, 0xB8,\n0xFF, 0x00, 0xFF, 0x00, 0x96, 0x02, 0x64, 0xB8,\n0x86, 0x02, 0x64, 0xB8, 0xA2, 0x02, 0x64, 0xB8,\n0xCC, 0x01, 0x64, 0xB8, 0x0A, 0x06, 0x64, 0xB8,\n0xB1, 0x05, 0x64, 0xB8, 0xCA, 0x01, 0x64, 0xB8,\n0x5B, 0x01, 0x64, 0xB8, 0x3C, 0x01, 0x64, 0xB8,\n0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x02, 0x00,\n0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00,\n0x22, 0x05, 0x64, 0xB8, 0xFE, 0x11, 0x64, 0xB8,\n0x7F, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x01,\n0xFC, 0x11, 0x64, 0xB8, 0xE0, 0x10, 0x60, 0xB8,\n0x57, 0x01, 0x64, 0xB8, 0x31, 0x00, 0x78, 0xB8,\n0x1D, 0x04, 0x64, 0xB8, 0x7A, 0x04, 0x64, 0xB8,\n0x80, 0x01, 0x64, 0xB8, 0x84, 0x01, 0x64, 0xB8,\n0x72, 0x06, 0x64, 0xB8, 0xA9, 0x00, 0x78, 0xB8,\n0x61, 0x00, 0x78, 0xB8, 0x01, 0x00, 0x78, 0xB8,\n0xB9, 0x00, 0x78, 0xB8, 0xC1, 0x01, 0x64, 0xB8,\n0xB9, 0x01, 0x64, 0xB8, 0xC3, 0x01, 0x64, 0xB8,\n0x00, 0x00, 0xFF, 0x00, 0x24, 0x01, 0x64, 0xB8,\n0xB8, 0x01, 0x64, 0xB8, 0x60, 0x00, 0x60, 0xB8,\n0x44, 0x00, 0x60, 0xB8, 0x4D, 0x01, 0x64, 0xB8,\n0x18, 0x00, 0x78, 0xB8, 0x28, 0x00, 0x78, 0xB8,\n0x10, 0x00, 0x78, 0xB8, 0x08, 0x00, 0x78, 0xB8,\n0x09, 0x00, 0x78, 0xB8, 0x0A, 0x00, 0x78, 0xB8,\n0x46, 0x00, 0x78, 0xB8, 0x50, 0x00, 0x78, 0xB8,\n0x40, 0x00, 0x78, 0xB8, 0x4A, 0x00, 0x78, 0xB8,\n0x34, 0x00, 0x78, 0xB8, 0x09, 0x06, 0x64, 0xB8,\n0x08, 0x06, 0x64, 0xB8, 0xFF, 0xFF, 0xFF, 0x7F,\n0x05, 0x00, 0x60, 0xB8, 0x04, 0x00, 0x78, 0xB8,\n0x38, 0x00, 0x78, 0xB8, 0x7A, 0x00, 0x78, 0xB8,\n0x60, 0x00, 0x78, 0xB8, 0x54, 0x00, 0x78, 0xB8,\n0xC0, 0x01, 0x64, 0xB8, 0x20, 0x00, 0x78, 0xB8,\n0xC4, 0x01, 0x64, 0xB8, 0xA5, 0xA5, 0xA5, 0xA5,\n0x48, 0x00, 0x78, 0xB8, 0xC2, 0x01, 0x64, 0xB8,\n0x05, 0x00, 0x78, 0xB8, 0x02, 0x00, 0x78, 0xB8,\n0x06, 0x00, 0x78, 0xB8, 0x0C, 0x00, 0x78, 0xB8,\n0x0D, 0x00, 0x78, 0xB8, 0x0E, 0x00, 0x78, 0xB8,\n0x0F, 0x00, 0x78, 0xB8, 0x14, 0x00, 0x78, 0xB8,\n0x02, 0x00, 0x64, 0xB8, 0x86, 0x00, 0x60, 0xB8,\n0x87, 0x00, 0x60, 0xB8, 0x88, 0x00, 0x60, 0xB8,\n0x84, 0x00, 0x60, 0xB8, 0x00, 0x00, 0x00, 0x02,\n0xCB, 0x01, 0x64, 0xB8, 0x00, 0x00, 0x68, 0xB8,\n0x04, 0x00, 0x68, 0xB8, 0x08, 0x00, 0x68, 0xB8,\n0x0C, 0x00, 0x68, 0xB8, 0x00, 0x00, 0x00, 0x03,\n0x00, 0x00, 0x00, 0x42, 0xE0, 0x00, 0x60, 0xB8,\n0xFF, 0xFF, 0xFF, 0xFD, 0xE3, 0x00, 0x60, 0xB8,\n0x00, 0x00, 0x00, 0x01, 0xE1, 0x00, 0x60, 0xB8,\n0x00, 0x00, 0x00, 0x60, 0xCC, 0x00, 0x60, 0xB8,\n0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x04,\n0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xDF,\n0xFF, 0xFF, 0xFF, 0x1F, 0x04, 0x00, 0x60, 0xB8,\n0x04, 0x00, 0x64, 0xB8, 0x08, 0x00, 0x60, 0xB8,\n0x08, 0x00, 0x64, 0xB8, 0xE8, 0x12, 0x64, 0xB8,\n0x24, 0x00, 0x60, 0xB8, 0xFF, 0xFF, 0xFE, 0xFF,\n0xFF, 0xFF, 0xFF, 0xEF, 0xFF, 0xFF, 0xFD, 0xFF,\n0x24, 0x04, 0x64, 0xB8, 0xB0, 0x02, 0x64, 0xB8,\n0x1C, 0x04, 0x64, 0xB8, 0x00, 0x0C, 0x01, 0x00,\n0x00, 0x80, 0xFF, 0x01, 0x08, 0x00, 0x00, 0xF8,\n0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x1F, 0x00,\n0x01, 0x00, 0x00, 0xE0, 0x00, 0x00, 0xFF, 0x0F,\n0x21, 0x00, 0x00, 0xE0, 0x00, 0xDB, 0x66, 0xDB,\n0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0xFC,\n0x00, 0x00, 0x00, 0x06, 0x80, 0xFF, 0x7F, 0x00,\n0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0xFC, 0x07,\n0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0xF0, 0x0F,\n0x00, 0x00, 0x00, 0x0F, 0xB4, 0x06, 0x64, 0xB8,\n0x06, 0x00, 0x00, 0x89, 0x00, 0x0A, 0x08, 0x00,\n0x01, 0x00, 0x66, 0xB8, 0x44, 0x00, 0x78, 0xB8,\n0x01, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0x60,\n0x01, 0x00, 0x0F, 0x70, 0x01, 0x00, 0x1F, 0x70,\n0x01, 0x00, 0x2F, 0x70, 0x01, 0x00, 0x3F, 0x70,\n0x01, 0x00, 0x4F, 0x70, 0x01, 0x00, 0x5F, 0x70,\n0x01, 0x00, 0x6F, 0x70, 0x01, 0x00, 0x7F, 0x70,\n0x01, 0x00, 0x8F, 0x70, 0x01, 0x00, 0x9F, 0x70,\n0x01, 0x00, 0xAF, 0x70, 0x01, 0x00, 0xBF, 0x70,\n0x01, 0x00, 0xCF, 0x70, 0x01, 0x00, 0xDF, 0x70,\n0x01, 0x00, 0xEF, 0x70, 0x01, 0x00, 0xFF, 0x70,\n0x41, 0x80, 0x0B, 0x70, 0x41, 0x40, 0x14, 0x70,\n0x41, 0x40, 0x24, 0x70, 0x41, 0x40, 0x34, 0x70,\n0x41, 0x40, 0x44, 0x70, 0x41, 0x80, 0x5B, 0x70,\n0x41, 0x40, 0x64, 0x70, 0x41, 0x80, 0x7B, 0x70,\n0x41, 0x80, 0x8B, 0x70, 0x41, 0x80, 0x9B, 0x70,\n0x41, 0x80, 0xAB, 0x70, 0x41, 0x80, 0xBB, 0x70,\n0x41, 0x80, 0xCB, 0x70, 0x41, 0x80, 0xDB, 0x70,\n0x41, 0x80, 0xEB, 0x70, 0x41, 0x80, 0xFB, 0x70,\n0x00, 0x00, 0x10, 0x00, 0x50, 0x50, 0x50, 0x50,\n0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x03, 0x00,\n0x1F, 0x00, 0x60, 0xB8, 0xEF, 0x00, 0x60, 0xB8,\n0x03, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x60,\n0x08, 0x18, 0x07, 0x00, 0x08, 0x0C, 0x07, 0x00,\n0x08, 0x00, 0x04, 0x00, 0xFF, 0x60, 0x0F, 0x00,\n0x3F, 0xD8, 0x0F, 0x00, 0xFF, 0x60, 0x07, 0x00,\n0x3F, 0xD8, 0x0D, 0x00, 0xFF, 0xDE, 0x07, 0x00,\n0xBF, 0xF7, 0x0D, 0x00, 0x00, 0xC0, 0x0F, 0x00,\n0x00, 0x00, 0x7C, 0x00, 0x00, 0xF0, 0x01, 0x00,\n0x5E, 0x00, 0xD5, 0xF7, 0x40, 0x00, 0x1F, 0x70,\n0x40, 0x00, 0x2F, 0x70, 0x40, 0x00, 0x3F, 0x70,\n0x40, 0x00, 0x4F, 0x70, 0x40, 0x00, 0x6F, 0x70,\n0x5E, 0x00, 0xA1, 0xFF, 0x00, 0x00, 0xFF, 0x1F,\n0xFF, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFF,\n0x00, 0x00, 0xFF, 0xFF, 0x80, 0x00, 0x00, 0x30,\n0xF0, 0x00, 0x04, 0x00, 0xF0, 0x00, 0x04, 0x04,\n0xF0, 0x00, 0x04, 0x08, 0xF0, 0x00, 0x04, 0x01,\n0xF0, 0x00, 0x04, 0x05, 0xF0, 0x00, 0x04, 0x09,\n0xF0, 0x00, 0x04, 0x02, 0xF0, 0x00, 0x04, 0x06,\n0xF0, 0x00, 0x04, 0x0A, 0xF0, 0x00, 0x04, 0x03,\n0xF0, 0x00, 0x04, 0x07, 0xF0, 0x00, 0x04, 0x0B,\n0xF0, 0x00, 0x04, 0x0C, 0xF0, 0x00, 0x04, 0x10,\n0xF0, 0x00, 0x04, 0x0D, 0xF0, 0x00, 0x04, 0x11,\n0xF0, 0x00, 0x04, 0x0E, 0xF0, 0x00, 0x04, 0x12,\n0xF0, 0x00, 0x04, 0x0F, 0xF0, 0x00, 0x04, 0x13,\n0x00, 0x00, 0x06, 0x00, 0x01, 0x00, 0x06, 0x00,\n0xF0, 0x00, 0x09, 0x00, 0x17, 0x00, 0x05, 0x00,\n0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x10, 0x1F,\n0x00, 0x00, 0x0D, 0x1F, 0x0B, 0x17, 0x23, 0x3B,\n0x47, 0x53, 0x5F, 0x77, 0x00, 0x48, 0x08, 0x00,\n0x01, 0x48, 0x08, 0x00, 0x00, 0x00, 0x0F, 0x80,\n0x00, 0x00, 0x0F, 0xC0, 0x3F, 0x00, 0x00, 0xC0,\n0x80, 0x66, 0x06, 0x01, 0x10, 0x13, 0x00, 0x80,\n0xDB, 0x00, 0x00, 0x81, 0xDB, 0x00, 0x00, 0x01,\n0x00, 0x00, 0x02, 0x05, 0x0C, 0x19, 0x00, 0x82,\n0x0C, 0x19, 0x00, 0x02, 0x14, 0xEE, 0x01, 0x83,\n0x14, 0xEE, 0x01, 0x03, 0x08, 0x00, 0x02, 0x05,\n0x14, 0x00, 0x03, 0x00, 0xFF, 0xFF, 0xFF, 0x03,\n0x00, 0x00, 0x7F, 0x00, 0x00, 0xFC, 0x01, 0x00,\n0x12, 0x33, 0x03, 0x00, 0x11, 0x33, 0x03, 0x00,\n0x12, 0x11, 0x01, 0x00, 0x31, 0xC9, 0x62, 0x49,\n0x55, 0x24, 0x01, 0xFF, 0xC8, 0xFE, 0x18, 0x3E,\n0xDE, 0xF0, 0xFA, 0x00, 0x44, 0x23, 0x12, 0x00,\n0x01, 0xC0, 0xE0, 0x70, 0x01, 0x80, 0xEB, 0x70,\n0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00,\n0x3F, 0xFF, 0xFE, 0xDF, 0x00, 0x00, 0x60, 0x00,\n0x00, 0xFF, 0x0F, 0x00, 0x01, 0x80, 0x03, 0x70,\n0x01, 0x80, 0x53, 0x70, 0x01, 0x80, 0x73, 0x70,\n0x01, 0x80, 0x83, 0x70, 0x01, 0x80, 0x93, 0x70,\n0x01, 0x80, 0xA3, 0x70, 0x01, 0x80, 0xB3, 0x70,\n0x01, 0x80, 0xC3, 0x70, 0x01, 0x80, 0xD3, 0x70,\n0x01, 0x80, 0xE3, 0x70, 0x01, 0x80, 0xF3, 0x70,\n0x01, 0x80, 0x0B, 0x70, 0x01, 0x80, 0x5B, 0x70,\n0x01, 0x80, 0x7B, 0x70, 0x01, 0x80, 0x8B, 0x70,\n0x01, 0x80, 0x9B, 0x70, 0x01, 0x80, 0xAB, 0x70,\n0x01, 0x80, 0xBB, 0x70, 0x01, 0x80, 0xCB, 0x70,\n0x01, 0x80, 0xDB, 0x70, 0x01, 0x80, 0xFB, 0x70,\n0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x40, 0x00,\n0x00, 0x00, 0x70, 0x00, 0x00, 0xFC, 0xF8, 0xFF,\n0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x3F,\n0x00, 0x00, 0x70, 0xB8, 0x18, 0x00, 0x70, 0xB8,\n0x0B, 0x00, 0x70, 0xB8, 0x02, 0x00, 0x70, 0xB8,\n0x1C, 0x01, 0x64, 0xB8, 0x94, 0x02, 0x64, 0xB8,\n0x97, 0x02, 0x64, 0xB8, 0x84, 0x02, 0x64, 0xB8,\n0x06, 0x00, 0x66, 0xB8, 0x50, 0x02, 0x64, 0xB8,\n0x48, 0x02, 0x64, 0xB8, 0x74, 0x00, 0x18, 0x2E,\n0x74, 0x00, 0x19, 0x2E, 0x01, 0x00, 0x60, 0xB8,\n0x01, 0x00, 0x64, 0xB8, 0xCF, 0x01, 0x64, 0xB8,\n0x34, 0x01, 0x64, 0xB8, 0x64, 0x05, 0x64, 0xB8,\n0x60, 0x05, 0x64, 0xB8, 0xC8, 0x01, 0x64, 0xB8,\n0xC9, 0x01, 0x64, 0xB8, 0x0C, 0xEA, 0xEF, 0xFD,\n0xA0, 0x01, 0x64, 0xB8, 0x48, 0x00, 0x60, 0xB8,\n0x47, 0x00, 0x60, 0xB8, 0x46, 0x00, 0x60, 0xB8,\n0x63, 0x00, 0x60, 0xB8, 0x62, 0x00, 0x60, 0xB8,\n0x45, 0x00, 0x60, 0xB8, 0x61, 0x00, 0x60, 0xB8,\n0xC6, 0x01, 0x64, 0xB8, 0xFF, 0xFF, 0xFF, 0x00,\n0x00, 0x00, 0x00, 0x05, 0x64, 0x01, 0x64, 0xB8,\n0x53, 0x05, 0x64, 0xB8, 0x94, 0x01, 0x64, 0xB8,\n0x00, 0x1C, 0x66, 0xB8, 0x54, 0x00, 0x60, 0xB8,\n0x24, 0x11, 0x64, 0xB8, 0x2C, 0x11, 0x64, 0xB8,\n0x34, 0x11, 0x64, 0xB8, 0x3C, 0x11, 0x64, 0xB8,\n0xE4, 0x11, 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0x4A,\n0x30, 0xF0, 0x20, 0x6B, 0x20, 0xF6, 0x50, 0xDB,\n0x30, 0xF0, 0x20, 0x6A, 0xCB, 0xF2, 0x00, 0x4A,\n0x30, 0xF0, 0x20, 0x6B, 0x20, 0xF6, 0x54, 0xDB,\n0x30, 0xF0, 0x20, 0x6B, 0x20, 0xF6, 0x58, 0xDB,\n0x30, 0xF0, 0x20, 0x6A, 0xCD, 0xF2, 0x14, 0x4A,\n0x30, 0xF0, 0x20, 0x6B, 0x20, 0xF6, 0x5C, 0xDB,\n0x30, 0xF0, 0x20, 0x6A, 0xCD, 0xF5, 0x17, 0x4A,\n0x30, 0xF0, 0x20, 0x6B, 0x40, 0xF6, 0x40, 0xDB,\n0x30, 0xF0, 0x20, 0x6A, 0xCD, 0xF5, 0x1C, 0x4A,\n0x30, 0xF0, 0x20, 0x6B, 0x40, 0xF6, 0x44, 0xDB,\n0x30, 0xF0, 0x20, 0x6A, 0xED, 0xF5, 0x04, 0x4A,\n0x30, 0xF0, 0x20, 0x6B, 0x40, 0xF6, 0x48, 0xDB,\n0x30, 0xF0, 0x20, 0x6A, 0xAB, 0xF2, 0x00, 0x4A,\n0x30, 0xF0, 0x20, 0x6B, 0x40, 0xF6, 0x4C, 0xDB,\n0x30, 0xF0, 0x20, 0x6A, 0xAB, 0xF2, 0x08, 0x4A,\n0x30, 0xF0, 0x20, 0x6B, 0x40, 0xF6, 0x50, 0xDB,\n0x30, 0xF0, 0x20, 0x6A, 0xAB, 0xF2, 0x09, 0x4A,\n0x30, 0xF0, 0x20, 0x6B, 0x40, 0xF6, 0x54, 0xDB,\n0x30, 0xF0, 0x20, 0x6A, 0xAB, 0xF2, 0x0A, 0x4A,\n0x30, 0xF0, 0x20, 0x6B, 0x40, 0xF6, 0x58, 0xDB,\n0x30, 0xF0, 0x20, 0x6A, 0xAB, 0xF2, 0x10, 0x4A,\n0x30, 0xF0, 0x20, 0x6B, 0x40, 0xF6, 0x5C, 0xDB,\n0x30, 0xF0, 0x20, 0x6A, 0xAB, 0xF2, 0x1A, 0x4A,\n0x30, 0xF0, 0x20, 0x6B, 0x60, 0xF6, 0x40, 0xDB,\n0x30, 0xF0, 0x20, 0x6A, 0x06, 0xF2, 0x1D, 0x4A,\n0x30, 0xF0, 0x20, 0x6B, 0xA0, 0xF6, 0x58, 0xDB,\n0x30, 0xF0, 0x20, 0x6A, 0x8D, 0xF7, 0x18, 0x4A,\n0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF6, 0x40, 0xDB,\n0x20, 0xE8, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x6A,\n0x30, 0xF0, 0x20, 0x6B, 0x21, 0xF0, 0x00, 0x4B,\n0x80, 0xF2, 0x08, 0x4A, 0x13, 0x10, 0x80, 0x9A,\n0x10, 0x2C, 0x30, 0xF0, 0x20, 0x6C, 0x22, 0xF6,\n0xA4, 0x9C, 0x30, 0xF0, 0x20, 0x6E, 0xA2, 0xF5,\n0xD0, 0x9E, 0x80, 0x9D, 0xCD, 0xEC, 0x80, 0xDD,\n0x30, 0xF0, 0x20, 0x6C, 0x43, 0xF4, 0x9C, 0x9C,\n0x40, 0xDC, 0x04, 0x4A, 0x43, 0xEB, 0xEB, 0x60,\n0x20, 0xE8, 0x00, 0x65, 0xFB, 0x63, 0x09, 0x62,\n0x08, 0xD1, 0x07, 0xD0, 0xFF, 0xF7, 0x1F, 0x69,\n0x2C, 0xED, 0x30, 0xF0, 0x20, 0x6B, 0x04, 0xD5,\n0x63, 0xF4, 0xA0, 0x9B, 0xFF, 0x6A, 0x40, 0x6E,\n0x60, 0xA5, 0xCB, 0xEE, 0x4C, 0xEC, 0x4C, 0xEB,\n0xCC, 0xEB, 0x6D, 0xEC, 0x4C, 0xEC, 0x80, 0xC5,\n0x30, 0xF0, 0x20, 0x6A, 0x80, 0xF3, 0x4C, 0x9A,\n0x0A, 0x6C, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6A,\n0x63, 0xF4, 0x44, 0x9A, 0x00, 0xAA, 0x04, 0x92,\n0x2C, 0xE8, 0x2A, 0xEA, 0x0B, 0x60, 0x30, 0xF0,\n0x20, 0x6A, 0xA0, 0xF3, 0x44, 0x9A, 0x04, 0x94,\n0x40, 0xEA, 0x04, 0x93, 0x2C, 0xEA, 0x6C, 0xE8,\n0x07, 0xEA, 0x2C, 0xE8, 0x50, 0x67, 0x09, 0x97,\n0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF,\n0xFA, 0x63, 0x0B, 0x62, 0x0A, 0xD1, 0x09, 0xD0,\n0xFF, 0xF7, 0x1F, 0x69, 0x2C, 0xED, 0xFF, 0x68,\n0x0C, 0xEC, 0x2C, 0xEE, 0x2A, 0xED, 0x05, 0xD4,\n0x04, 0xD5, 0x06, 0xD6, 0x1F, 0x61, 0x30, 0xF0,\n0x20, 0x6A, 0x63, 0xF4, 0x60, 0x9A, 0x40, 0x6C,\n0x8B, 0xEC, 0x40, 0xA3, 0x0C, 0xEA, 0x8C, 0xEA,\n0x05, 0x94, 0x8D, 0xEA, 0x0C, 0xEA, 0x40, 0xC3,\n0x30, 0xF0, 0x20, 0x6A, 0x63, 0xF4, 0x64, 0x9A,\n0x30, 0xF0, 0x20, 0x6C, 0x43, 0xF1, 0x90, 0x9C,\n0x40, 0x9B, 0x8C, 0xEA, 0x30, 0xF0, 0x20, 0x6C,\n0x02, 0xF5, 0x88, 0x9C, 0x8D, 0xEA, 0xCD, 0xEA,\n0x40, 0xDB, 0x34, 0x10, 0x05, 0x94, 0xB1, 0x67,\n0x80, 0x18, 0x5B, 0x51, 0x07, 0xD2, 0x30, 0xF0,\n0x20, 0x6A, 0x04, 0x94, 0xA0, 0xF3, 0x44, 0x9A,\n0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6B, 0x63, 0xF4,\n0x80, 0x9B, 0x40, 0x6D, 0xAB, 0xED, 0x60, 0xA4,\n0x2C, 0xEA, 0x0C, 0xEB, 0xAC, 0xEB, 0x05, 0x95,\n0xAD, 0xEB, 0x0C, 0xEB, 0x60, 0xC4, 0x30, 0xF0,\n0x20, 0x6B, 0x63, 0xF4, 0x84, 0x9B, 0x30, 0xF0,\n0x20, 0x6D, 0x43, 0xF1, 0xB0, 0x9D, 0x60, 0x9C,\n0x06, 0x96, 0xAC, 0xEB, 0x30, 0xF0, 0x20, 0x6D,\n0x02, 0xF5, 0xA8, 0x9D, 0xC4, 0xEA, 0x46, 0x67,\n0xAD, 0xEB, 0x04, 0x95, 0x07, 0x96, 0xAC, 0xEA,\n0xAF, 0xED, 0xCC, 0xED, 0xAD, 0xEA, 0x2C, 0xEA,\n0x4D, 0xEB, 0x60, 0xDC, 0x30, 0xF0, 0x20, 0x6A,\n0x80, 0xF3, 0x4C, 0x9A, 0x0A, 0x6C, 0x40, 0xEA,\n0x0B, 0x97, 0x0A, 0x91, 0x09, 0x90, 0x06, 0x63,\n0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62,\n0x00, 0x6C, 0x10, 0xF0, 0x00, 0x6D, 0x80, 0x18,\n0x5B, 0x51, 0x05, 0x97, 0x01, 0x5A, 0x58, 0x67,\n0x03, 0x63, 0x00, 0xEF, 0xFD, 0x63, 0x05, 0x62,\n0x04, 0xD0, 0x30, 0xF0, 0x20, 0x6B, 0xC2, 0xF4,\n0x78, 0x9B, 0x10, 0xF0, 0x31, 0x6A, 0xC8, 0xF6,\n0x0D, 0x4A, 0x40, 0xDB, 0x00, 0x68, 0x31, 0x10,\n0x82, 0xF3, 0x08, 0x70, 0x1A, 0x61, 0x30, 0xF0,\n0x20, 0x6A, 0x22, 0xF6, 0x64, 0x9A, 0x02, 0xF0,\n0x00, 0x6C, 0x40, 0x9B, 0x8D, 0xEA, 0x40, 0xDB,\n0x30, 0xF0, 0x20, 0x6A, 0x26, 0xF1, 0x08, 0x4A,\n0xA3, 0xF3, 0x64, 0x9A, 0x8D, 0xEB, 0xA3, 0xF3,\n0x64, 0xDA, 0x30, 0xF0, 0x20, 0x6A, 0xE2, 0xF5,\n0x5C, 0x9A, 0x03, 0x6B, 0x6B, 0xEB, 0x60, 0xC2,\n0x18, 0x10, 0xFF, 0xF7, 0x1F, 0x6A, 0x01, 0x48,\n0x4C, 0xE8, 0x30, 0xF0, 0x20, 0x6A, 0x80, 0xF3,\n0x4C, 0x9A, 0x14, 0x6C, 0x40, 0xEA, 0x33, 0x58,\n0x08, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0x23, 0xF3,\n0x58, 0x9A, 0x60, 0xA2, 0x08, 0x6A, 0x6C, 0xEA,\n0x04, 0x2A, 0x80, 0x18, 0xAD, 0x51, 0x01, 0x72,\n0xCB, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0xE2, 0xF5,\n0x5C, 0x9A, 0x02, 0x6B, 0x6B, 0xEB, 0x60, 0xC2,\n0x30, 0xF0, 0x20, 0x6B, 0xC2, 0xF4, 0x78, 0x9B,\n0x10, 0xF0, 0x31, 0x6A, 0xC8, 0xF6, 0x0E, 0x4A,\n0x40, 0xDB, 0x05, 0x97, 0x04, 0x90, 0x03, 0x63,\n0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62,\n0x04, 0xD0, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3,\n0x60, 0x9A, 0x02, 0x6C, 0xFF, 0xF7, 0x1F, 0x6D,\n0x40, 0x9B, 0xFF, 0x6E, 0x41, 0x4E, 0x8D, 0xEA,\n0x40, 0xDB, 0x30, 0xF0, 0x20, 0x6A, 0xC2, 0xF5,\n0x7C, 0x9A, 0xE0, 0xF3, 0x1E, 0x4C, 0x30, 0xF0,\n0x20, 0x68, 0x40, 0xAB, 0xAC, 0xEA, 0x8D, 0xEA,\n0xAC, 0xEA, 0x40, 0xCB, 0x02, 0x6C, 0x80, 0x18,\n0x76, 0x51, 0x80, 0xF3, 0x4C, 0x98, 0x0A, 0x6C,\n0x40, 0xEA, 0x00, 0x6C, 0xC0, 0x6D, 0x02, 0x6E,\n0x80, 0x18, 0x76, 0x51, 0x00, 0x6C, 0xC4, 0x67,\n0x02, 0xF0, 0x00, 0x6D, 0x80, 0x18, 0x76, 0x51,\n0x00, 0x6C, 0xC4, 0x67, 0x0C, 0xF0, 0x00, 0x6D,\n0x80, 0x18, 0x76, 0x51, 0x00, 0x6C, 0x01, 0xF0,\n0x00, 0x6D, 0x01, 0x6E, 0x80, 0x18, 0x76, 0x51,\n0x10, 0xF0, 0x00, 0x6D, 0x01, 0x6E, 0x00, 0x6C,\n0x80, 0x18, 0x76, 0x51, 0x80, 0xF3, 0x4C, 0x98,\n0x0A, 0x6C, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6A,\n0x63, 0xF4, 0x68, 0x9A, 0xFF, 0x6C, 0x04, 0x6D,\n0x40, 0xA3, 0x8C, 0xEA, 0xAD, 0xEA, 0x8C, 0xEA,\n0x40, 0xC3, 0x05, 0x97, 0x04, 0x90, 0x03, 0x63,\n0x00, 0xEF, 0x00, 0x65, 0x00, 0x00, 0x00, 0x00,\n0xF2, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\n};\n\nu32 array_length_mp_8822c_fw_wowlan = 132360;\n\n#endif /*CONFIG_WOWLAN*/\n\n#endif\n\n#endif /* end of LOAD_FW_HEADER_FROM_DRIVER */\n\n#endif\n"
  },
  {
    "path": "hal/rtl8822c/hal8822c_fw.h",
    "content": "/******************************************************************************\n*\n* Copyright(c) 2012 - 2017 Realtek Corporation.\n*\n* This program is free software; you can redistribute it and/or modify it\n* under the terms of version 2 of the GNU General Public License as\n* published by the Free Software Foundation.\n*\n* This program is distributed in the hope that it will be useful, but WITHOUT\n* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n* more details.\n*\n******************************************************************************/\n\n#ifdef CONFIG_RTL8822C\n\n#ifndef _FW_HEADER_8822C_H\n#define _FW_HEADER_8822C_H\n\n#ifdef LOAD_FW_HEADER_FROM_DRIVER\n#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))\nextern u8 array_mp_8822c_fw_ap[128776];\nextern u32 array_length_mp_8822c_fw_ap;\n#endif\n\n#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE))\nextern u8 array_mp_8822c_fw_hybrid[169328];\nextern u32 array_length_mp_8822c_fw_hybrid;\nextern u8 array_mp_8822c_fw_nic[185248];\nextern u32 array_length_mp_8822c_fw_nic;\nextern u8 array_mp_8822c_fw_spic[114552];\nextern u32 array_length_mp_8822c_fw_spic;\n#ifdef CONFIG_WOWLAN\nextern u8 array_mp_8822c_fw_wowlan[132360];\nextern u32 array_length_mp_8822c_fw_wowlan;\n#endif /*CONFIG_WOWLAN*/\n#endif\n#endif /* end of LOAD_FW_HEADER_FROM_DRIVER */\n\n#endif\n\n#endif\n\n"
  },
  {
    "path": "hal/rtl8822c/pci/rtl8822ce.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8822CE_H_\n#define _RTL8822CE_H_\n\n#include <drv_types.h>\t\t/* PADAPTER */\n\n#if defined (CONFIG_PCI_TX_POLLING) && !defined (CONFIG_PCI_TX_POLLING_V2)\n#define TX_BD_NUM_8822CE\t256\n#else\n#define TX_BD_NUM_8822CE\t128\n#endif\n#define RX_BD_NUM_8822CE\tPCI_MAX_RX_COUNT /* TODO */\n\n#ifdef CONFIG_CONCURRENT_MODE\n#define TX_BD_NUM_BEQ_8822CE\t(TX_BD_NUM_8822CE << 1)\n#else\n#define TX_BD_NUM_BEQ_8822CE\tTX_BD_NUM_8822CE\n#endif /* CONFIG_CONCURRENT_MODE */\n\n#define TX_BD_NUM_8822CE_BCN\t2\n#define TX_BD_NUM_8822CE_CMD\t128\n\n#define RTL8822CE_SEG_NUM       1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */\n\n#ifndef MAX_RECVBUF_SZ\n\t#ifndef CONFIG_MINIMAL_MEMORY_USAGE\n\t\t#define MAX_RECVBUF_SZ (32768)\n\t#else\n\t\t#define MAX_RECVBUF_SZ (4000)\n\t#endif\n#endif /* !MAX_RECVBUF_SZ */\n\n#define TX_BUFFER_SEG_NUM\t1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */\n\n#define MAX_RECVBUF_SZ_8822C\t24576\t/* 24k */\n\n/* TX BD */\n#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)\n#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)\n#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)\n\n/* RX BD */\n#define SET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pRxBd + 0x04, 0, 32, __Value)\n#define SET_RX_BD_RXBUFFSIZE(__pRxBd, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pRxBd + 0x00, 0, 14, __Value)\n#define SET_RX_BD_LS(__pRxBd, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pRxBd + 0x00, 14, 1, __Value)\n#define SET_RX_BD_FS(__pRxBd, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pRxBd + 0x00, 15, 1, __Value)\n#define SET_RX_BD_TOTALRXPKTSIZE(__pRxBd, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pRxBd + 0x00, 16, 13, __Value)\n\n/* rtl8822ce_halinit.c */\nu32 rtl8822ce_init(PADAPTER);\nu32 rtl8822ce_deinit(PADAPTER padapter);\nvoid rtl8822ce_init_default_value(PADAPTER);\n\n/* rtl8822ce_halmac.c */\nint rtl8822ce_halmac_init_adapter(PADAPTER);\n\n/* rtl8822ce_io.c */\n\n/* rtl8822ce_led.c */\nvoid rtl8822ce_initswleds(PADAPTER);\nvoid rtl8822ce_deinitswleds(PADAPTER);\n\n/* rtl8822cs_xmit.c */\n#define OFFSET_SZ 0\n\ns32 rtl8822ce_init_xmit_priv(PADAPTER);\nvoid rtl8822ce_free_xmit_priv(PADAPTER);\nstruct xmit_buf *rtl8822ce_dequeue_xmitbuf(struct rtw_tx_ring *);\nvoid rtl8822ce_fill_fake_txdesc(PADAPTER, u8 *pDesc, u32 BufferLen,\n\t\t\t\tu8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);\nint rtl8822ce_init_txbd_ring(PADAPTER, unsigned int q_idx,\n\t\t\t     unsigned int entries);\nvoid rtl8822ce_free_txbd_ring(PADAPTER, unsigned int prio);\n\nvoid rtl8822ce_tx_isr(PADAPTER, int prio);\n#ifdef CONFIG_PCI_TX_POLLING_V2\nvoid rtl8822ce_tx_isr_polling(PADAPTER, int prio);\n#endif\n\n#ifdef CONFIG_PCI_TX_POLLING\nvoid rtl8822ce_tx_ring_poll(PADAPTER Adapter, int prio);\n#endif\n\ns32 rtl8822ce_mgnt_xmit(PADAPTER, struct xmit_frame *);\ns32 rtl8822ce_hal_xmit(PADAPTER, struct xmit_frame *);\ns32 rtl8822ce_hal_xmitframe_enqueue(PADAPTER, struct xmit_frame *);\n\n#ifdef CONFIG_XMIT_THREAD_MODE\n\ts32 rtl8822ce_xmit_buf_handler(PADAPTER);\n#endif\nu32 InitMAC_TRXBD_8822CE(PADAPTER adapter);\nvoid rtl8822ce_reset_bd(_adapter *padapter);\n\nvoid rtl8822ce_xmitframe_resume(PADAPTER);\n\n/* rtl8822cs_recv.c */\ns32 rtl8822ce_init_recv_priv(PADAPTER);\nvoid rtl8822ce_free_recv_priv(PADAPTER);\nint rtl8822ce_init_rxbd_ring(PADAPTER);\nvoid rtl8822ce_free_rxbd_ring(PADAPTER);\n\n/* rtl8822cs_ops.c */\n\n#endif /* _RTL8822CE_H_ */\n"
  },
  {
    "path": "hal/rtl8822c/pci/rtl8822ce_halinit.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#define _RTL8822CE_HALINIT_C_\n#include <drv_types.h>          /* PADAPTER, basic_types.h and etc. */\n#include <hal_data.h>\t\t/* HAL_DATA_TYPE */\n#include \"../../hal_halmac.h\"\t/* HALMAC API */\n#include \"../rtl8822c.h\"\n#include \"rtl8822ce.h\"\n\n#ifdef CONFIG_FWLPS_IN_IPS\nu8 rtl8822ce_fw_ips_init(_adapter *padapter)\n{\n\tstruct sreset_priv *psrtpriv = &GET_HAL_DATA(padapter)->srestpriv;\n\tstruct debug_priv *pdbgpriv = &adapter_to_dvobj(padapter)->drv_dbg;\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);\n\tsystime start_time;\n\tu8 cpwm_orig, cpwm_now, rpwm;\n\tu8 bMacPwrCtrlOn = _TRUE;\n\n\tif ((pwrctl->bips_processing == _FALSE)\n\t    || (psrtpriv->silent_reset_inprogress == _TRUE)\n\t    || (GET_HAL_DATA(padapter)->bFWReady == _FALSE)\n\t    || (pwrctl->pre_ips_type != 0))\n\t\treturn _FAIL;\n\n\tRTW_INFO(\"%s: Leaving FW_IPS\\n\", __func__);\n\n#ifdef CONFIG_LPS_LCLK\n\t/* for polling cpwm */\n\tcpwm_orig = 0;\n\trtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);\n\n\t/* set rpwm */\n\trtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &rpwm);\n\trpwm += 0x80;\n\trpwm |= PS_ACK;\n\trtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));\n\n\n\tRTW_INFO(\"%s: write rpwm=%02x\\n\", __func__, rpwm);\n\n\tpwrctl->tog = (rpwm + 0x80) & 0x80;\n\n\t/* do polling cpwm */\n\tstart_time = rtw_get_current_time();\n\tdo {\n\t\trtw_mdelay_os(1);\n\n\t\trtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);\n\t\tif ((cpwm_orig ^ cpwm_now) & 0x80) {\n#ifdef DBG_CHECK_FW_PS_STATE\n\t\t\tRTW_INFO(\"%s: polling cpwm ok when leaving IPS in FWLPS state,\"\n\t\t\t\t \" cost %d ms,\"\n\t\t\t\t \" cpwm_orig=0x%02x, cpwm_now=0x%02x, 0x100=0x%x\\n\",\n\t\t\t\t __FUNCTION__,\n\t\t\t\t rtw_get_passing_time_ms(start_time),\n\t\t\t\t cpwm_orig, cpwm_now, rtw_read8(padapter, REG_CR_8822C));\n#endif /* DBG_CHECK_FW_PS_STATE */\n\t\t\tbreak;\n\t\t}\n\n\t\tif (rtw_get_passing_time_ms(start_time) > 100) {\n\t\t\tRTW_ERR(\"%s: polling cpwm timeout when leaving IPS in FWLPS state\\n\", __FUNCTION__);\n\t\t\tbreak;\n\t\t}\n\t} while (1);\n#endif /* CONFIG_LPS_LCLK */\n\n\trtl8822c_set_FwPwrModeInIPS_cmd(padapter, 0);\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);\n\n#ifdef CONFIG_LPS_LCLK\n#ifdef DBG_CHECK_FW_PS_STATE\n\tif (rtw_fw_ps_state(padapter) == _FAIL) {\n\t\tRTW_INFO(\"after hal init, fw ps state in 32k\\n\");\n\t\tpdbgpriv->dbg_ips_drvopen_fail_cnt++;\n\t}\n#endif /* DBG_CHECK_FW_PS_STATE */\n#endif /* CONFIG_LPS_LCLK */\n\n\treturn _SUCCESS;\n}\n\nu8 rtl8822ce_fw_ips_deinit(_adapter *padapter)\n{\n\tstruct sreset_priv *psrtpriv =  &GET_HAL_DATA(padapter)->srestpriv;\n\tstruct debug_priv *pdbgpriv = &adapter_to_dvobj(padapter)->drv_dbg;\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);\n\tsystime start_time;\n\tint cnt = 0;\n\tu8 val8 = 0, rpwm;\n\n\tif ((pwrctl->bips_processing == _FALSE)\n\t    || (psrtpriv->silent_reset_inprogress == _TRUE)\n\t    || (GET_HAL_DATA(padapter)->bFWReady == _FALSE)\n\t    || (padapter->netif_up == _FALSE)) {\n\t\tpdbgpriv->dbg_carddisable_cnt++;\n\t\tpwrctl->pre_ips_type = 1;\n\n\t\treturn _FAIL;\n\t}\n\n\tRTW_INFO(\"%s: issue H2C to FW when entering IPS\\n\", __func__);\n\trtl8822c_set_FwPwrModeInIPS_cmd(padapter, 0x1);\n\n#ifdef CONFIG_LPS_LCLK\n\t/*\n\t * poll 0x1cc to make sure H2C command already finished by FW;\n\t * MAC_0x1cc=0 means H2C done by FW.\n\t */\n\tstart_time = rtw_get_current_time();\n\tdo {\n\t\trtw_mdelay_os(10);\n\t\tval8 = rtw_read8(padapter, REG_HMETFR_8822C);\n\t\tcnt++;\n\t\tif (!val8)\n\t\t\tbreak;\n\n\t\tif (rtw_get_passing_time_ms(start_time) > 100) {\n\t\t\tRTW_ERR(\"%s: fail to wait H2C, REG_HMETFR=0x%x, cnt=%d\\n\",\n\t\t\t\t__FUNCTION__, val8, cnt);\n#ifdef DBG_CHECK_FW_PS_STATE\n\t\t\tRTW_WARN(\"MAC_1C0=0x%08x, MAC_1C4=0x%08x, MAC_1C8=0x%08x, MAC_1CC=0x%08x\\n\",\n\t\t\t\t rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4),\n\t\t\t\t rtw_read32(padapter, 0x1c8), rtw_read32(padapter, REG_HMETFR_8822C));\n#endif /* DBG_CHECK_FW_PS_STATE */\n\t\t\tgoto exit;\n\t\t}\n\t} while (1);\n\n\t/* H2C done, enter 32k */\n\t/* set rpwm to enter 32k */\n\trtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &rpwm);\n\trpwm += 0x80;\n\trpwm |= PS_STATE_S0;\n\trtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));\n\tRTW_INFO(\"%s: write rpwm=%02x\\n\", __func__, rpwm);\n\tpwrctl->tog = (val8 + 0x80) & 0x80;\n\n\tcnt = val8 = 0;\n\tstart_time = rtw_get_current_time();\n\tdo {\n\t\tval8 = rtw_read8(padapter, REG_CR_8822C);\n\t\tcnt++;\n\t\tRTW_INFO(\"%s: polling 0x100=0x%x, cnt=%d\\n\",\n\t\t\t __FUNCTION__, val8, cnt);\n\t\tif (val8 == 0xEA) {\n\t\t\tRTW_INFO(\"%s: polling 0x100=0xEA, cnt=%d, cost %d ms\\n\",\n\t\t\t\t __FUNCTION__, cnt,\n\t\t\t\t rtw_get_passing_time_ms(start_time));\n\t\t\tbreak;\n\t\t}\n\n\t\tif (rtw_get_passing_time_ms(start_time) > 100) {\n\t\t\tRTW_ERR(\"%s: polling polling 0x100=0xEA timeout! cnt=%d\\n\",\n\t\t\t\t__FUNCTION__, cnt);\n#ifdef DBG_CHECK_FW_PS_STATE\n\t\t\tRTW_WARN(\"MAC_1C0=0x%08x, MAC_1C4=0x%08x, MAC_1C8=0x%08x, MAC_1CC=0x%08x\\n\",\n\t\t\t\t rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4),\n\t\t\t\t rtw_read32(padapter, 0x1c8), rtw_read32(padapter, REG_HMETFR_8822C));\n#endif /* DBG_CHECK_FW_PS_STATE */\n\t\t\tbreak;\n\t\t}\n\n\t\trtw_mdelay_os(10);\n\t} while (1);\n\nexit:\n\tRTW_INFO(\"polling done when entering IPS, check result: 0x100=0x%02x, cnt=%d, MAC_1cc=0x%02x\\n\",\n\t\t rtw_read8(padapter, REG_CR_8822C), cnt, rtw_read8(padapter, REG_HMETFR_8822C));\n#endif /* CONFIG_LPS_LCLK */\n\n\tpwrctl->pre_ips_type = 0;\n\n\treturn _SUCCESS;\n\n}\n\n#endif /* CONFIG_FWLPS_IN_IPS */\n\nu32 InitMAC_TRXBD_8822CE(PADAPTER Adapter)\n{\n\tu8 tmpU1b;\n\tu16 tmpU2b;\n\tu32 tmpU4b;\n\tint q_idx;\n\tstruct recv_priv *precvpriv = &Adapter->recvpriv;\n\tstruct xmit_priv *pxmitpriv = &Adapter->xmitpriv;\n\tHAL_DATA_TYPE\t*pHalData\t= GET_HAL_DATA(Adapter);\n\n\tRTW_INFO(\"=======>InitMAC_TXBD_8822CE()\\n\");\n\n\t/*\n\t * Set CMD TX BD (buffer descriptor) physical address(from OS API).\n\t */\n\trtw_write32(Adapter, REG_H2CQ_TXBD_DESA_8822C,\n\t\t    (u64)pxmitpriv->tx_ring[TXCMD_QUEUE_INX].dma &\n\t\t    DMA_BIT_MASK(32));\n\trtw_write32(Adapter, REG_H2CQ_TXBD_NUM_8822C,\n\t\t    TX_BD_NUM_8822CE_CMD | ((RTL8822CE_SEG_NUM << 12) &\n\t\t\t\t\t 0x3000));\n\n#ifdef CONFIG_64BIT_DMA\n\trtw_write32(Adapter, REG_H2CQ_TXBD_DESA_8822C + 4,\n\t\t    ((u64)pxmitpriv->tx_ring[TXCMD_QUEUE_INX].dma) >> 32);\n#endif\n\t/*\n\t * Set TX/RX BD (buffer descriptor) physical address(from OS API).\n\t */\n\trtw_write32(Adapter, REG_BCNQ_TXBD_DESA_8822C,\n\t\t    (u64)pxmitpriv->tx_ring[BCN_QUEUE_INX].dma &\n\t\t    DMA_BIT_MASK(32));\n\trtw_write32(Adapter, REG_MGQ_TXBD_DESA_8822C,\n\t\t    (u64)pxmitpriv->tx_ring[MGT_QUEUE_INX].dma &\n\t\t    DMA_BIT_MASK(32));\n\trtw_write32(Adapter, REG_VOQ_TXBD_DESA_8822C,\n\t\t    (u64)pxmitpriv->tx_ring[VO_QUEUE_INX].dma &\n\t\t    DMA_BIT_MASK(32));\n\trtw_write32(Adapter, REG_VIQ_TXBD_DESA_8822C,\n\t\t    (u64)pxmitpriv->tx_ring[VI_QUEUE_INX].dma &\n\t\t    DMA_BIT_MASK(32));\n\trtw_write32(Adapter, REG_BEQ_TXBD_DESA_8822C,\n\t\t    (u64)pxmitpriv->tx_ring[BE_QUEUE_INX].dma &\n\t\t    DMA_BIT_MASK(32));\n\n\t/* vincent sync windows */\n\ttmpU4b = rtw_read32(Adapter, REG_BEQ_TXBD_DESA_8822C);\n\n\trtw_write32(Adapter, REG_BKQ_TXBD_DESA_8822C,\n\t\t    (u64)pxmitpriv->tx_ring[BK_QUEUE_INX].dma &\n\t\t    DMA_BIT_MASK(32));\n\trtw_write32(Adapter, REG_HI0Q_TXBD_DESA_8822C,\n\t\t    (u64)pxmitpriv->tx_ring[HIGH_QUEUE_INX].dma &\n\t\t    DMA_BIT_MASK(32));\n\trtw_write32(Adapter, REG_RXQ_RXBD_DESA_8822C,\n\t\t    (u64)precvpriv->rx_ring[RX_MPDU_QUEUE].dma &\n\t\t    DMA_BIT_MASK(32));\n\n#ifdef CONFIG_64BIT_DMA\n\t/*\n\t * 2009/10/28 MH For DMA 64 bits. We need to assign the high\n\t * 32 bit address for NIC HW to transmit data to correct path.\n\t */\n\trtw_write32(Adapter, REG_BCNQ_TXBD_DESA_8822C + 4,\n\t\t    ((u64)pxmitpriv->tx_ring[BCN_QUEUE_INX].dma) >> 32);\n\trtw_write32(Adapter, REG_MGQ_TXBD_DESA_8822C + 4,\n\t\t    ((u64)pxmitpriv->tx_ring[MGT_QUEUE_INX].dma) >> 32);\n\trtw_write32(Adapter, REG_VOQ_TXBD_DESA_8822C + 4,\n\t\t    ((u64)pxmitpriv->tx_ring[VO_QUEUE_INX].dma) >> 32);\n\trtw_write32(Adapter, REG_VIQ_TXBD_DESA_8822C + 4,\n\t\t    ((u64)pxmitpriv->tx_ring[VI_QUEUE_INX].dma) >> 32);\n\trtw_write32(Adapter, REG_BEQ_TXBD_DESA_8822C + 4,\n\t\t    ((u64)pxmitpriv->tx_ring[BE_QUEUE_INX].dma) >> 32);\n\trtw_write32(Adapter, REG_BKQ_TXBD_DESA_8822C + 4,\n\t\t    ((u64)pxmitpriv->tx_ring[BK_QUEUE_INX].dma) >> 32);\n\trtw_write32(Adapter, REG_HI0Q_TXBD_DESA_8822C + 4,\n\t\t    ((u64)pxmitpriv->tx_ring[HIGH_QUEUE_INX].dma) >> 32);\n\trtw_write32(Adapter, REG_RXQ_RXBD_DESA_8822C + 4,\n\t\t    ((u64)precvpriv->rx_ring[RX_MPDU_QUEUE].dma) >> 32);\n\n\n\t/* 2009/10/28 MH If RX descriptor address is not equal to zero.\n\t* We will enable DMA 64 bit functuion.\n\t* Note: We never saw thd consition which the descripto address are\n\t*\tdivided into 4G down and 4G upper separate area.\n\t*/\n\tif (((u64)precvpriv->rx_ring[RX_MPDU_QUEUE].dma) >> 32 != 0) {\n\t\tRTW_INFO(\"Enable DMA64 bit\\n\");\n\n\t\t/* Check if other descriptor address is zero and\n\t\t * abnormally be in 4G lower area. */\n\t\tif (((u64)pxmitpriv->tx_ring[MGT_QUEUE_INX].dma) >> 32)\n\t\t\tRTW_INFO(\"MGNT_QUEUE HA=0\\n\");\n\n\t\tPlatformEnableDMA64(Adapter);\n\t} else\n\t\tRTW_INFO(\"Enable DMA32 bit\\n\");\n#endif\n\n\t/* pci buffer descriptor mode: Reset the Read/Write point to 0 */\n\tPlatformEFIOWrite4Byte(Adapter, REG_TSFTIMER_HCI_8822C, 0x3fffffff);\n\n\t/* Reset the H2CQ R/W point index to 0 */\n\ttmpU4b = rtw_read32(Adapter, REG_H2CQ_CSR_8822C);\n\trtw_write32(Adapter, REG_H2CQ_CSR_8822C, (tmpU4b | BIT8 | BIT16));\n\n\ttmpU1b = rtw_read8(Adapter, REG_PCIE_CTRL + 3);\n\trtw_write8(Adapter, REG_PCIE_CTRL + 3, (tmpU1b | 0xF7));\n\n\t/* 20100318 Joseph: Reset interrupt migration setting\n\t * when initialization. Suggested by SD1. */\n\trtw_write32(Adapter, REG_INT_MIG, 0);\n\tpHalData->bInterruptMigration = _FALSE;\n\n\t/* 2009.10.19. Reset H2C protection register. by tynli. */\n\trtw_write32(Adapter, REG_MCUTST_I_8822C, 0x0);\n\n#if MP_DRIVER == 1\n\tif (Adapter->registrypriv.mp_mode == 1) {\n\t\trtw_write32(Adapter, REG_MACID, 0x87654321);\n\t\trtw_write32(Adapter, 0x0700, 0x87654321);\n\t}\n#endif\n\n\t/* pic buffer descriptor mode: */\n\t/* ---- tx */\n\trtw_write16(Adapter, REG_MGQ_TXBD_NUM_8822C,\n\t\t    TX_BD_NUM_8822CE | ((RTL8822CE_SEG_NUM << 12) & 0x3000));\n\trtw_write16(Adapter, REG_VOQ_TXBD_NUM_8822C,\n\t\t    TX_BD_NUM_8822CE | ((RTL8822CE_SEG_NUM << 12) & 0x3000));\n\trtw_write16(Adapter, REG_VIQ_TXBD_NUM_8822C,\n\t\t    TX_BD_NUM_8822CE | ((RTL8822CE_SEG_NUM << 12) & 0x3000));\n\trtw_write16(Adapter, REG_BEQ_TXBD_NUM_8822C,\n\t\t    TX_BD_NUM_BEQ_8822CE | ((RTL8822CE_SEG_NUM << 12) & 0x3000));\n\trtw_write16(Adapter, REG_BKQ_TXBD_NUM_8822C,\n\t\t    TX_BD_NUM_8822CE | ((RTL8822CE_SEG_NUM << 12) & 0x3000));\n\trtw_write16(Adapter, REG_HI0Q_TXBD_NUM_8822C,\n\t\t    TX_BD_NUM_8822CE | ((RTL8822CE_SEG_NUM << 12) & 0x3000));\n\trtw_write16(Adapter, REG_HI1Q_TXBD_NUM_8822C,\n\t\t    TX_BD_NUM_8822CE | ((RTL8822CE_SEG_NUM << 12) & 0x3000));\n\trtw_write16(Adapter, REG_HI2Q_TXBD_NUM_8822C,\n\t\t    TX_BD_NUM_8822CE | ((RTL8822CE_SEG_NUM << 12) & 0x3000));\n\trtw_write16(Adapter, REG_HI3Q_TXBD_NUM_8822C,\n\t\t    TX_BD_NUM_8822CE | ((RTL8822CE_SEG_NUM << 12) & 0x3000));\n\trtw_write16(Adapter, REG_HI4Q_TXBD_NUM_8822C,\n\t\t    TX_BD_NUM_8822CE | ((RTL8822CE_SEG_NUM << 12) & 0x3000));\n\trtw_write16(Adapter, REG_HI5Q_TXBD_NUM_8822C,\n\t\t    TX_BD_NUM_8822CE | ((RTL8822CE_SEG_NUM << 12) & 0x3000));\n\trtw_write16(Adapter, REG_HI6Q_TXBD_NUM_8822C,\n\t\t    TX_BD_NUM_8822CE | ((RTL8822CE_SEG_NUM << 12) & 0x3000));\n\trtw_write16(Adapter, REG_HI7Q_TXBD_NUM_8822C,\n\t\t    TX_BD_NUM_8822CE | ((RTL8822CE_SEG_NUM << 12) & 0x3000));\n\n\n\t/* rx. support 32 bits in linux */\n\n\n\t/* using 64bit\n\trtw_write16(Adapter, REG_RX_RXBD_NUM_8822C,\n\t\tRX_BD_NUM_8822CE |((RTL8822CE_SEG_NUM<<13 ) & 0x6000) |0x8000);\n\t*/\n\n\n\t/* using 32bit */\n\trtw_write16(Adapter, REG_RX_RXBD_NUM_8822C,\n\t\t    RX_BD_NUM_8822CE | ((RTL8822CE_SEG_NUM << 13) & 0x6000));\n\n\t/* reset read/write point */\n\trtw_write32(Adapter, REG_TSFTIMER_HCI_8822C, 0XFFFFFFFF);\n\n#if 1 /* vincent windows */\n\t/* Start debug mode */\n\t{\n\t\tu8 reg0x3f3 = 0;\n\n\t\treg0x3f3 = rtw_read8(Adapter, 0x3f3);\n\t\trtw_write8(Adapter, 0x3f3, reg0x3f3 | BIT2);\n\t}\n\n\t{\n\t\t/* Need to disable BT coex to let MP tool Tx, this would be done in FW\n\t\t * in the future, suggest by ChunChu, 2015.05.19\n\t\t */\n\n\t\tu8 tmp1Byte;\n\t\tu16 tmp2Byte;\n\t\tu32 tmp4Byte;\n\n\t\ttmp2Byte = rtw_read16(Adapter, REG_SYS_FUNC_EN_8822C);\n\t\trtw_write16(Adapter, REG_SYS_FUNC_EN_8822C, tmp2Byte | BIT10);\n\t\ttmp1Byte = rtw_read8(Adapter, REG_DIS_TXREQ_CLR_8822C);\n\t\trtw_write8(Adapter, REG_DIS_TXREQ_CLR_8822C, tmp1Byte | BIT7);\n\t\ttmp4Byte = rtw_read32(Adapter, 0x1080);\n\t\trtw_write32(Adapter, 0x1080, tmp4Byte | BIT16);\n\t}\n#endif\n\n\tRTW_INFO(\"InitMAC_TXBD_8822CE() <====\\n\");\n\n\treturn _SUCCESS;\n}\n\n#ifdef CONFIG_RTW_LED\nstatic void init_hwled(PADAPTER adapter, u8 enable)\n{\n\tu8 mode = 0;\n\tstruct led_priv *ledpriv = adapter_to_led(adapter);\n\n\tif (ledpriv->LedStrategy != HW_LED)\n\t\treturn;\n\n\trtw_halmac_led_cfg(adapter_to_dvobj(adapter), enable, mode);\n}\n#endif /* CONFIG_RTW_LED */\n\nstatic void hal_init_misc(PADAPTER adapter)\n{\n#ifdef CONFIG_RTW_LED\n\tstruct led_priv *ledpriv = adapter_to_led(adapter);\n#ifdef CONFIG_SW_LED\n\tpledpriv->bRegUseLed = _TRUE;\n\tledpriv->LedStrategy = SW_LED_MODE1;\n#else /* HW LED */\n\tledpriv->LedStrategy = HW_LED;\n#endif /* CONFIG_SW_LED */\n\tinit_hwled(adapter, 1);\n#endif\n}\n\nu32 rtl8822ce_init(PADAPTER padapter)\n{\n\tu8 ok = _TRUE;\n\tu8 val8;\n\tPHAL_DATA_TYPE hal;\n\tstruct registry_priv  *registry_par = &padapter->registrypriv;\n\n\thal = GET_HAL_DATA(padapter);\n\n#if 0\n\t/*Only reset HW Ring*/\n\tInitMAC_TRXBD_8822CE(padapter);\n#else\n\t/*Both reset HW and SW Ring.\n\t *For FW IPS, only HW Ring is resetted. It cause Tx DMA errors.\n\t *Both reset HW/SW Ring here can fix errors.\n\t */\n\trtl8822ce_reset_bd(padapter);\n#endif\n\n#ifdef CONFIG_FWLPS_IN_IPS\n\tif (_SUCCESS == rtl8822ce_fw_ips_init(padapter)) {\n\t\tRTW_INFO(\"%s(%d) ooo fw_ips_init init success\\n\",__func__,__LINE__);\n\t\treturn _SUCCESS;\n\t}\n#endif\n\n\tok = rtl8822c_hal_init(padapter);\n\tif (_FALSE == ok)\n\t\treturn _FAIL;\n\n#if defined(USING_RX_TAG)\n\t/* have to init after halmac init */\n\tval8 = rtw_read8(padapter, REG_PCIE_CTRL_8822C + 2);\n\trtw_write8(padapter, REG_PCIE_CTRL_8822C + 2, (val8 | BIT4));\n\trtw_write16(padapter, REG_PCIE_CTRL_8822C, 0x8000);\n#else\n\trtw_write16(padapter, REG_PCIE_CTRL_8822C, 0x0000);\n#endif\n\n\trtw_write8(padapter, REG_RX_DRVINFO_SZ_8822C, 0x4);\n\n\trtl8822c_phy_init_haldm(padapter);\n#ifdef CONFIG_BEAMFORMING\n\trtl8822c_phy_bf_init(padapter);\n#endif\n\n#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\t/*HW /FW init*/\n\trtw_hal_set_default_port_id_cmd(padapter, 0);\n#endif\n\n#ifdef CONFIG_BT_COEXIST\n\t/* Init BT hw config. */\n\tif (hal->EEPROMBluetoothCoexist == _TRUE) {\n\t\trtw_btcoex_HAL_Initialize(padapter, _FALSE);\n\t\t#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\t\trtw_hal_set_wifi_btc_port_id_cmd(padapter);\n\t\t#endif\n\t} else\n#endif /* CONFIG_BT_COEXIST */\n\t\trtw_btcoex_wifionly_hw_config(padapter);\n\n\thal->pci_backdoor_ctrl = registry_par->pci_aspm_config;\n\n\trtw_pci_aspm_config(padapter);\n\n\trtl8822c_init_misc(padapter);\n\thal_init_misc(padapter);\n\n#ifdef CONFIG_8822CE_INT_MIGRATION \n\t/* TX interrupt migration - 3pkts or 7*64=448us */\n\trtw_write32(padapter, REG_INT_MIG_8822C, 0x03070000);\n#endif\n\treturn _SUCCESS;\n}\n\nvoid rtl8822ce_init_default_value(PADAPTER padapter)\n{\n\tPHAL_DATA_TYPE pHalData;\n\n\n\tpHalData = GET_HAL_DATA(padapter);\n\n\trtl8822c_init_default_value(padapter);\n\n\t/* interface related variable */\n\tpHalData->CurrentWirelessMode = WIRELESS_MODE_AUTO;\n\tpHalData->bDefaultAntenna = 1;\n\tpHalData->TransmitConfig = BIT_CFEND_FORMAT | BIT_WMAC_TCR_ERRSTEN_3;\n\n\t/* Set RCR-Receive Control Register .\n\t * The value is set in InitializeAdapter8190Pci().\n\t */\n\tpHalData->ReceiveConfig = (\n#ifdef CONFIG_RX_PACKET_APPEND_FCS\n\t\t\t\t\t  BIT_APP_FCS\t\t|\n#endif\n\t\t\t\t\t  BIT_APP_MIC\t\t|\n\t\t\t\t\t  BIT_APP_ICV\t\t|\n\t\t\t\t\t  BIT_APP_PHYSTS\t\t|\n\t\t\t\t\t  BIT_VHT_DACK\t\t|\n\t\t\t\t\t  BIT_HTC_LOC_CTRL\t|\n\t\t\t\t\t  /* BIT_AMF\t\t| */\n\t\t\t\t\t  BIT_CBSSID_DATA\t\t|\n\t\t\t\t\t  BIT_CBSSID_BCN\t\t|\n\t\t\t\t\t  /* BIT_ACF\t\t| */\n\t\t\t\t\t  /* BIT_ADF\t\t| */ /* PS-Poll filter */\n\t\t\t\t\t  BIT_AB\t\t\t|\n\t\t\t\t\t  BIT_AB\t\t\t|\n\t\t\t\t\t  BIT_APM\t\t\t|\n\t\t\t\t\t  0);\n\n\t/*\n\t * Set default value of Interrupt Mask Register0\n\t */\n\tpHalData->IntrMaskDefault[0] = (u32)(\n\t\t\t\t\t       BIT(29)\t\t\t| /* BIT_PSTIMEOUT */\n\t\t\t\t\t       BIT(27)\t\t\t| /* BIT_GTINT3 */\n\t\t\t\t\t       BIT_TXBCN0ERR_MSK\t|\n\t\t\t\t\t       BIT_TXBCN0OK_MSK\t|\n\t\t\t\t\t       BIT_BCNDMAINT0_MSK\t|\n\t\t\t\t\t       BIT_HSISR_IND_ON_INT_MSK |\n\t\t\t\t\t       BIT_C2HCMD_MSK\t\t|\n\t\t\t#ifdef CONFIG_LPS_LCLK\n\t\t\t\t\t\tBIT_CPWM_MSK\t\t|\n\t\t\t#endif\n\t\t\t#if (!(defined (CONFIG_PCI_TX_POLLING) || defined (CONFIG_PCI_TX_POLLING_V2)))\n\t\t\t\t\t       BIT_HIGHDOK_MSK\t\t|\n\t\t\t\t\t       BIT_MGTDOK_MSK\t\t|\n\t\t\t\t\t       BIT_BKDOK_MSK\t\t|\n\t\t\t\t\t       BIT_BEDOK_MSK\t\t|\n\t\t\t\t\t       BIT_VIDOK_MSK\t\t|\n\t\t\t\t\t       BIT_VODOK_MSK\t\t|\n\t\t\t#endif\n\t\t\t\t\t       BIT_RDU_MSK\t\t|\n\t\t\t\t\t       BIT_RXOK_MSK\t\t|\n\t\t\t\t\t       0);\n\n\t/*\n\t * Set default value of Interrupt Mask Register1\n\t */\n\tpHalData->IntrMaskDefault[1] = (u32)(\n\t\t\t\t\t       BIT(9)\t\t| /* TXFOVW */\n\t\t\t\t\t       BIT_FOVW_MSK\t|\n\t\t\t\t\t       0);\n\n\t/*\n\t * Set default value of Interrupt Mask Register3\n\t */\n\tpHalData->IntrMaskDefault[3] = (u32)(\n\t\t\t\t\t       BIT(2)| /*PCIE TX DMA Stuck mask*/\n\t\t\t\t\t       BIT(3)| /*PCIE RX DMA Stuck mask*/\n\t\t\t\t       BIT_SETH2CDOK_MASK\t| /* H2C_TX_OK */\n\t\t\t\t\t       0);\n\n\t/* 2012/03/27 hpfan Add for win8 DTM DPC ISR test */\n\tpHalData->IntrMaskReg[0] = (u32)(\n\t\t\t\t\t   BIT_RDU_MSK\t|\n\t\t\t\t\t   BIT(29)\t\t| /* BIT_PSTIMEOUT */\n\t\t\t\t\t   0);\n\n\tpHalData->IntrMaskReg[1] = (u32)(\n\t\t\t\t\t   BIT_C2HCMD_MSK\t|\n\t\t\t\t\t   0);\n\n\tpHalData->IntrMask[0] = pHalData->IntrMaskDefault[0];\n\tpHalData->IntrMask[1] = pHalData->IntrMaskDefault[1];\n\tpHalData->IntrMask[3] = pHalData->IntrMaskDefault[3];\n\n}\n\nstatic void hal_deinit_misc(PADAPTER adapter)\n{\n#ifdef CONFIG_RTW_LED\n\tstruct led_priv *ledpriv = adapter_to_led(adapter);\n\n\tinit_hwled(adapter, 0);\n#ifdef CONFIG_RTW_SW_LED\n\tif (ledpriv->bRegUseLed == _TRUE)\n\t\trtw_halmac_led_cfg(adapter_to_dvobj(adapter), _FALSE, 3);\n#endif\n#endif /* CONFIG_RTW_LED */\n}\n\nu32 rtl8822ce_deinit(PADAPTER padapter)\n{\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct dvobj_priv *pobj_priv = adapter_to_dvobj(padapter);\n\tu8 status = _TRUE;\n\n\tRTW_INFO(\"==> %s\\n\", __func__);\n\n#ifdef CONFIG_FWLPS_IN_IPS\n\tif (_SUCCESS == rtl8822ce_fw_ips_deinit(padapter))\n\t\tgoto exit;\n#endif\n\n\thal_deinit_misc(padapter);\n\tstatus = rtl8822c_deinit(padapter);\n\tif (status == _FALSE) {\n\t\tRTW_INFO(\"%s: rtl8822c_hal_deinit fail\\n\", __func__);\n\t\treturn _FAIL;\n\t}\n\n#ifdef CONFIG_FWLPS_IN_IPS\nexit:\n#endif\n\tRTW_INFO(\"%s <==\\n\", __func__);\n\treturn _SUCCESS;\n}\n\n\n"
  },
  {
    "path": "hal/rtl8822c/pci/rtl8822ce_halmac.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2018 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTL8822CE_HALMAC_C_\n#include <drv_types.h>\t\t/* struct dvobj_priv and etc. */\n#include \"../../hal_halmac.h\"\n#include \"../rtl8822c.h\"\t/* rtl8822c_get_tx_desc_size() */\n#include \"rtl8822ce.h\"\n\nstatic u8 pci_write_port_not_xmitframe(void *d,  u32 size, u8 *pBuf,  u8 qsel)\n{\n\tstruct dvobj_priv *pobj = (struct dvobj_priv *)d;\n\tstruct pci_dev *pdev = pobj->ppcidev;\n\tPADAPTER padapter = dvobj_get_primary_adapter(pobj);\n\tu8 *txbd;\n\tdma_addr_t txbd_dma;\n\tu8 ret = _SUCCESS;\n\tdma_addr_t mapping;\n\tu16 tx_page_size = 128;\n\tu16 tx_page_used = 0;\n\tint i;\n\n\n\t/* map TX DESC buf_addr (including TX DESC + tx data) */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\tmapping = dma_map_single(&pdev->dev, pBuf,\n\t\t size + TX_WIFI_INFO_SIZE, DMA_TO_DEVICE);\n#else\n\tmapping = pci_map_single(pdev, pBuf,\n\t\t size + TX_WIFI_INFO_SIZE, PCI_DMA_TODEVICE);\n#endif\n\n\t/* Calculate page size.\n\t * Total buffer length including TX_WIFI_INFO and PacketLen */\n\tif (tx_page_size > 0) {\n\t\ttx_page_used = (size + TX_WIFI_INFO_SIZE) / tx_page_size;\n\t\tif (((size + TX_WIFI_INFO_SIZE) % tx_page_size) > 0)\n\t\t\ttx_page_used++;\n\t}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\ttxbd = dma_alloc_coherent(&pdev->dev, sizeof(struct tx_buf_desc), &txbd_dma, GFP_KERNEL);\n#else\n\ttxbd = pci_alloc_consistent(pdev, sizeof(struct tx_buf_desc), &txbd_dma);\n#endif\n\n\tif (!txbd) {\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\t\tdma_unmap_single(&pdev->dev, mapping,\n\t\t\tsize + TX_WIFI_INFO_SIZE, DMA_FROM_DEVICE);\n#else\n\t\tpci_unmap_single(pdev, mapping,\n\t\t\tsize + TX_WIFI_INFO_SIZE, PCI_DMA_FROMDEVICE);\n#endif\n\n\t\treturn _FALSE;\n\t}\n\t/* BD init */\n\tif (qsel == HALMAC_TXDESC_QSEL_H2C_CMD) {\n\t\trtw_write32(padapter, REG_H2CQ_TXBD_DESA_8822C,\n\t\t    txbd_dma & DMA_BIT_MASK(32));\n\n#ifdef CONFIG_64BIT_DMA\n\t\trtw_write32(padapter, REG_H2CQ_TXBD_DESA_8822C + 4,\n\t\t    ((u64)txbd_dma) >> 32);\n#endif\n\t\trtw_write32(padapter, REG_H2CQ_TXBD_NUM_8822C,\n\t\t\t2 | ((RTL8822CE_SEG_NUM << 12) & 0x3000));\n\t} else {\n\t\trtw_write32(padapter, REG_BCNQ_TXBD_DESA_8822C,\n\t\t\ttxbd_dma & DMA_BIT_MASK(32));\n\t#ifdef CONFIG_64BIT_DMA\n\t\trtw_write32(padapter, REG_BCNQ_TXBD_DESA_8822C + 4,\n\t\t\t((u64)txbd_dma) >> 32);\n\t#endif\n\t}\n\t/*\n\t * Reset all tx buffer desciprtor content\n\t * -- Reset first element\n\t */\n\t_rtw_memset(txbd, 0, sizeof(struct tx_buf_desc));\n\n\t/*\n\t * Fill buffer length of the first buffer,\n\t * For 8821ce, it is required that TX_WIFI_INFO is put in first segment,\n\t * and the size of the first segment cannot be larger than\n\t * TX_WIFI_INFO_SIZE.\n\t */\n\tSET_TX_BD_TX_BUFF_SIZE0(txbd, TX_WIFI_INFO_SIZE);\n\tSET_TX_BD_PSB(txbd, tx_page_used);\n\t/* starting addr of TXDESC */\n\tSET_TX_BD_PHYSICAL_ADDR0_LOW(txbd, mapping);\n\n\t/*\n\t * It is assumed that in linux implementation, packet is coalesced\n\t * in only one buffer. Extension mode is not supported here\n\t */\n\tSET_TXBUFFER_DESC_LEN_WITH_OFFSET(txbd, 1, size);\n\t/* don't using extendsion mode. */\n\tSET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(txbd, 1, 0);\n\tSET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(txbd, 1,\n\t\tmapping + TX_WIFI_INFO_SIZE); /* pkt */\n\n\twmb();\n\n\tif (qsel == HALMAC_TXDESC_QSEL_H2C_CMD)\n\t\trtw_write16(padapter, REG_H2CQ_TXBD_IDX, 1);\n\telse {\n\t\tSET_TX_BD_OWN(txbd, 1);\n\t/* kick start */\n\trtw_write8(padapter, REG_RX_RXBD_NUM + 1,\n\t\trtw_read8(padapter, REG_RX_RXBD_NUM + 1) | BIT(4));\n\t}\n\n\tudelay(100);\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\tdma_free_coherent(&pdev->dev, sizeof(struct tx_buf_desc), txbd, txbd_dma);\n#else\n\tpci_free_consistent(pdev, sizeof(struct tx_buf_desc), txbd, txbd_dma);\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\tdma_unmap_single(&pdev->dev, mapping, size + TX_WIFI_INFO_SIZE,\n\t\tDMA_FROM_DEVICE);\n#else\n\tpci_unmap_single(pdev, mapping, size + TX_WIFI_INFO_SIZE,\n\t\tPCI_DMA_FROMDEVICE);\n#endif\n\n\treturn ret;\n}\n\nstatic u8 pci_write_data_not_xmitframe(void *d, u8 *pBuf, u32 size, u8 qsel)\n{\n\tstruct dvobj_priv *pobj = (struct dvobj_priv *)d;\n\tPADAPTER padapter = dvobj_get_primary_adapter(pobj);\n\tstruct halmac_adapter *halmac = dvobj_to_halmac((struct dvobj_priv *)d);\n\tstruct halmac_api *api = HALMAC_GET_API(halmac);\n\tu32 desclen = 0;\n\tu32 len = 0;\n\tu8 *buf = NULL;\n\tu8 ret = _FALSE;\n\n\tif (size + TXDESC_OFFSET > MAX_CMDBUF_SZ) {\n\t\tRTW_INFO(\"%s: total buffer size(%d) > MAX_CMDBUF_SZ(%d)\\n\",\n\t\t\t__func__, size + TXDESC_OFFSET, MAX_CMDBUF_SZ);\n\t\treturn _FALSE;\n\t}\n\n\tdesclen = rtl8822c_get_tx_desc_size(padapter);\n\tlen = desclen + size;\n\n\tbuf = rtw_zmalloc(len);\n\n\tif (!buf) {\n\t\tRTW_ERR(\"%s: alloc buffer fail!\\n\", __func__);\n\t\treturn _FALSE;\n\t}\n\n\t/* copy data */\n\t_rtw_memcpy(buf + desclen, pBuf, size);\n\n\tSET_TX_DESC_TXPKTSIZE_8822C(buf, size);\n\n\t/* TX_DESC is not included in the data,\n\t * driver needs to fill in the TX_DESC with qsel=h2c\n\t * Offset in TX_DESC should be set to 0.\n\t */\n\tif (qsel == HALMAC_TXDESC_QSEL_H2C_CMD)\n\t\tSET_TX_DESC_OFFSET_8822C(buf, 0);\n\telse\n\t\tSET_TX_DESC_OFFSET_8822C(buf, desclen);\n\n\tSET_TX_DESC_QSEL_8822C(buf, qsel);\n\n\tapi->halmac_fill_txdesc_checksum(halmac, buf);\n\n\tret = pci_write_port_not_xmitframe(d, size, buf, qsel);\n\n\tif (ret == _SUCCESS)\n\t\tret = _TRUE;\n\telse\n\t\tret = _FALSE;\n\n\trtw_mfree(buf, len);\n\n\treturn _TRUE;\n}\n\nstatic u8 pci_write_data_rsvd_page_xmitframe(void *d, u8 *pBuf, u32 size)\n{\n\tstruct dvobj_priv *pobj = (struct dvobj_priv *)d;\n\tPADAPTER padapter = dvobj_get_primary_adapter(pobj);\n\tstruct xmit_priv        *pxmitpriv = &padapter->xmitpriv;\n\tstruct rtw_tx_ring *ring = &pxmitpriv->tx_ring[BCN_QUEUE_INX];\n\tstruct pci_dev *pdev = pobj->ppcidev;\n\tstruct xmit_frame       *pcmdframe = NULL;\n\tstruct xmit_buf       \t*pxmitbuf = NULL;\n\tstruct pkt_attrib       *pattrib = NULL;\n\tu32 desclen = 0;\n\tu8 *txdesc = NULL;\n\tu8 DLBcnCount = 0;\n\tu32 poll = 0;\n\tu8 *txbd;\n\tBOOLEAN bcn_valid = _FALSE;\n\n\tif (size + TXDESC_OFFSET > MAX_CMDBUF_SZ) {\n\t\tRTW_INFO(\"%s: total buffer size(%d) > MAX_CMDBUF_SZ(%d)\\n\"\n\t\t\t, __func__, size + TXDESC_OFFSET, MAX_CMDBUF_SZ);\n\t\treturn _FALSE;\n\t}\n\n\tpcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv);\n\n\tif (pcmdframe == NULL) {\n\t\tRTW_INFO(\"%s: alloc ReservedPagePacket fail!\\n\", __func__);\n\t\treturn _FALSE;\n\t}\n\n\tpxmitbuf = pcmdframe->pxmitbuf;\n\tdesclen = rtl8822c_get_tx_desc_size(padapter);\n\ttxdesc = pcmdframe->buf_addr;\n\n\t_rtw_memcpy((txdesc + desclen), pBuf, size); /* shift desclen */\n\n\t/* update attribute */\n\tpattrib = &pcmdframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\tpattrib->qsel = QSLT_BEACON;\n\tpattrib->pktlen = size;\n\tpattrib->last_txcmdsz = size;\n\n\t/* Clear beacon valid check bit. */\n\trtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);\n\trtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);\n\n\tdump_mgntframe(padapter, pcmdframe);\n\n\tDLBcnCount = 0;\n\tpoll = 0;\n\tdo {\n\t\tDLBcnCount++;\n\t\tdo {\n\t\t\trtw_yield_os();\n\t\t\t/* does rsvd page download OK. */\n\t\t\trtw_hal_get_hwreg(padapter,\n\t\t\t\tHW_VAR_BCN_VALID,(u8 *)(&bcn_valid));\n\t\t\tpoll++;\n\t\t} while (!bcn_valid && (poll % 10) != 0 && !RTW_CANNOT_RUN(padapter));\n\t} while (!bcn_valid && DLBcnCount <= 100 && !RTW_CANNOT_RUN(padapter));\n\n\ttxbd = (u8 *)(&ring->buf_desc[0]);\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\tdma_unmap_single(&pdev->dev, GET_TX_BD_PHYSICAL_ADDR0_LOW(txbd),\n\t\tpxmitbuf->len, DMA_TO_DEVICE);\n#else\n\tpci_unmap_single(pdev, GET_TX_BD_PHYSICAL_ADDR0_LOW(txbd),\n\t\tpxmitbuf->len, PCI_DMA_TODEVICE);\n#endif\n\n\treturn _TRUE;\n}\n\nstatic u8 pci_write_data_h2c_normal(void *d, u8 *pBuf, u32 size)\n{\n\tstruct dvobj_priv *pobj = (struct dvobj_priv *)d;\n\tPADAPTER padapter = dvobj_get_primary_adapter(pobj);\n\tstruct halmac_adapter *halmac = dvobj_to_halmac((struct dvobj_priv *)d);\n\tstruct xmit_priv        *pxmitpriv = &padapter->xmitpriv;\n\tstruct xmit_frame       *pcmdframe = NULL;\n\tstruct pkt_attrib       *pattrib = NULL;\n\tstruct halmac_api *api;\n\tu32 desclen;\n\tu8 *buf;\n\n        if (size + TXDESC_OFFSET > MAX_XMIT_EXTBUF_SZ) {\n                RTW_INFO(\"%s: total buffer size(%d) > MAX_XMIT_EXTBUF_SZ(%d)\\n\"\n                         , __func__, size + TXDESC_OFFSET, MAX_XMIT_EXTBUF_SZ);\n                return _FALSE;\n        }\n\n\tpcmdframe = alloc_mgtxmitframe(pxmitpriv);\n\n\tif (pcmdframe == NULL) {\n\t\tRTW_INFO(\"%s: alloc ReservedPagePacket fail!\\n\", __func__);\n\t\treturn _FALSE;\n\t}\n\n\tapi = HALMAC_GET_API(halmac);\n\n\tdesclen = rtl8822c_get_tx_desc_size(padapter);\n\tbuf = pcmdframe->buf_addr;\n\t_rtw_memcpy(buf + desclen, pBuf, size); /* shift desclen */\n\n\tSET_TX_DESC_TXPKTSIZE_8822C(buf, size);\n\tSET_TX_DESC_OFFSET_8822C(buf, 0);\n\tSET_TX_DESC_QSEL_8822C(buf, HALMAC_TXDESC_QSEL_H2C_CMD);\n\tSET_TX_DESC_TXDESC_CHECKSUM_8822C(buf, 0);\n\tapi->halmac_fill_txdesc_checksum(halmac, buf);\n\n\t/* update attribute */\n\tpattrib = &pcmdframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\tpattrib->qsel = QSLT_CMD;\n\tpattrib->pktlen = size;\n\tpattrib->last_txcmdsz = size;\n\n\t/* fill tx desc in dump_mgntframe */\n\tdump_mgntframe(padapter, pcmdframe);\n\n\treturn _TRUE;\n}\n\nstatic u8 pci_write_data_rsvd_page(void *d, u8 *pBuf, u32 size)\n{\n\tstruct dvobj_priv *pobj = (struct dvobj_priv *)d;\n\tPADAPTER padapter = dvobj_get_primary_adapter(pobj);\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tu8 ret;\n\n\tif (pHalData->not_xmitframe_fw_dl)\n\t\tret = pci_write_data_not_xmitframe(d, pBuf, size, HALMAC_TXDESC_QSEL_BEACON);\n\telse\n\t\tret = pci_write_data_rsvd_page_xmitframe(d, pBuf, size);\n\n\tif (ret == _TRUE)\n\t\treturn 1;\n\treturn 0;\n}\n\nstatic u8 pci_write_data_h2c(void *d, u8 *pBuf, u32 size)\n{\n\tstruct dvobj_priv *pobj = (struct dvobj_priv *)d;\n\tPADAPTER padapter = dvobj_get_primary_adapter(pobj);\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tu8 ret;\n\n\tif (pHalData->not_xmitframe_fw_dl)\n\t\tret = pci_write_data_not_xmitframe(d, pBuf, size, HALMAC_TXDESC_QSEL_H2C_CMD);\n\telse\n\t\tret = pci_write_data_h2c_normal(d, pBuf, size);\n\n\tif (ret == _TRUE)\n\t\treturn 1;\n\treturn 0;\n}\n\nint rtl8822ce_halmac_init_adapter(PADAPTER padapter)\n{\n\tstruct dvobj_priv *d;\n\tstruct halmac_platform_api *api;\n\tint err;\n\n\td = adapter_to_dvobj(padapter);\n\tapi = &rtw_halmac_platform_api;\n\tapi->SEND_RSVD_PAGE = pci_write_data_rsvd_page;\n\tapi->SEND_H2C_PKT = pci_write_data_h2c;\n\n\terr = rtw_halmac_init_adapter(d, api);\n\n\treturn err;\n}\n"
  },
  {
    "path": "hal/rtl8822c/pci/rtl8822ce_io.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTL8822CE_IO_C_\n\n#include <drv_types.h>\t\t/* PADAPTER and etc. */\n\n#ifdef RTK_129X_PLATFORM\n#include <soc/realtek/rtd129x_lockapi.h>\n\n#define IO_2K_MASK 0xFFFFF800\n#define IO_4K_MASK 0xFFFFF000\n#define MAX_RETRY 5\n\nstatic u32 pci_io_read_129x(struct dvobj_priv *pdvobjpriv, u32 addr, u8 size)\n{\n\tunsigned long mask_addr = pdvobjpriv->mask_addr;\n\tunsigned long tran_addr = pdvobjpriv->tran_addr;\n\tu8 busnumber = pdvobjpriv->pcipriv.busnumber;\n\tu32 rval = 0;\n\tu32 mask;\n\tu32 translate_val = 0;\n\tu32 tmp_addr = addr & 0xFFF;\n\t_irqL irqL;\n\tu32 pci_error_status = 0;\n\tint retry_cnt = 0;\n\tunsigned long flags;\n\n\t_enter_critical(&pdvobjpriv->io_reg_lock, &irqL);\n\n\t/* PCIE1.1 0x9804FCEC, PCIE2.0 0x9803CCEC & 0x9803CC68\n\t * can't be used because of 1295 hardware issue.\n\t */\n\tif ((tmp_addr == 0xCEC) || ((busnumber == 0x01) &&\n\t    (tmp_addr == 0xC68))) {\n\t\tmask = IO_2K_MASK;\n\t\twritel(0xFFFFF800, (u8 *)mask_addr);\n\t\ttranslate_val = readl((u8 *)tran_addr);\n\t\twritel(translate_val|(addr&mask), (u8 *)tran_addr);\n\t} else if (addr >= 0x1000) {\n\t\tmask = IO_4K_MASK;\n\t\ttranslate_val = readl((u8 *)tran_addr);\n\t\twritel(translate_val|(addr&mask), (u8 *)tran_addr);\n\t} else\n\t\tmask = 0x0;\n\npci_read_129x_retry:\n\n\t/* All RBUS1 driver need to have a workaround for emmc hardware error */\n\t/* Need to protect 0xXXXX_X8XX~ 0xXXXX_X9XX */\n\tif ((tmp_addr > 0x7FF) && (tmp_addr < 0xA00))\n\t\trtk_lockapi_lock(flags, __func__);\n\n\tswitch (size) {\n\tcase 1:\n\t\trval = readb((u8 *)pdvobjpriv->pci_mem_start + (addr&~mask));\n\t\tbreak;\n\tcase 2:\n\t\trval = readw((u8 *)pdvobjpriv->pci_mem_start + (addr&~mask));\n\t\tbreak;\n\tcase 4:\n\t\trval = readl((u8 *)pdvobjpriv->pci_mem_start + (addr&~mask));\n\t\tbreak;\n\tdefault:\n\t\tRTW_WARN(\"RTD129X: %s: wrong size %d\\n\", __func__, size);\n\t\tbreak;\n\t}\n\n\tif ((tmp_addr > 0x7FF) && (tmp_addr < 0xA00))\n\t\trtk_lockapi_unlock(flags, __func__);\n\n\t//DLLP error patch\n\tpci_error_status = readl( (u8 *)(pdvobjpriv->ctrl_start + 0x7C));\n\tif(pci_error_status & 0x1F) {\n\t\twritel(pci_error_status, (u8 *)(pdvobjpriv->ctrl_start + 0x7C));\n\t\tRTW_WARN(\"RTD129X: %s: DLLP(#%d) 0x%x reg=0x%x val=0x%x\\n\", __func__, retry_cnt, pci_error_status, addr, rval);\n\n\t\tif(retry_cnt < MAX_RETRY) {\n\t\t\tretry_cnt++;\n\t\t\tgoto pci_read_129x_retry;\n\t\t}\n\t}\n\n\t/* PCIE1.1 0x9804FCEC, PCIE2.0 0x9803CCEC & 0x9803CC68\n\t * can't be used because of 1295 hardware issue.\n\t */\n\tif ((tmp_addr == 0xCEC) || ((busnumber == 0x01) &&\n\t    (tmp_addr == 0xC68))) {\n\t\twritel(translate_val, (u8 *)tran_addr);\n\t\twritel(0xFFFFF000, (u8 *)mask_addr);\n\t} else if (addr >= 0x1000) {\n\t\twritel(translate_val, (u8 *)tran_addr);\n\t}\n\n\t_exit_critical(&pdvobjpriv->io_reg_lock, &irqL);\n\n\treturn rval;\n}\n\nstatic void pci_io_write_129x(struct dvobj_priv *pdvobjpriv,\n\t\t\t      u32 addr, u8 size, u32 wval)\n{\n\tunsigned long mask_addr = pdvobjpriv->mask_addr;\n\tunsigned long tran_addr = pdvobjpriv->tran_addr;\n\tu8 busnumber = pdvobjpriv->pcipriv.busnumber;\n\tu32 mask;\n\tu32 translate_val = 0;\n\tu32 tmp_addr = addr & 0xFFF;\n\t_irqL irqL;\n\tunsigned long flags;\n\n\t_enter_critical(&pdvobjpriv->io_reg_lock, &irqL);\n\n\t/* PCIE1.1 0x9804FCEC, PCIE2.0 0x9803CCEC & 0x9803CC68\n\t * can't be used because of 1295 hardware issue.\n\t */\n\tif ((tmp_addr == 0xCEC) || ((busnumber == 0x01) &&\n\t    (tmp_addr == 0xC68))) {\n\t\tmask = IO_2K_MASK;\n\t\twritel(0xFFFFF800, (u8 *)mask_addr);\n\t\ttranslate_val = readl((u8 *)tran_addr);\n\t\twritel(translate_val|(addr&mask), (u8 *)tran_addr);\n\t} else if (addr >= 0x1000) {\n\t\tmask = IO_4K_MASK;\n\t\ttranslate_val = readl((u8 *)tran_addr);\n\t\twritel(translate_val|(addr&mask), (u8 *)tran_addr);\n\t} else\n\t\tmask = 0x0;\n\n\t/* All RBUS1 driver need to have a workaround for emmc hardware error */\n\t/* Need to protect 0xXXXX_X8XX~ 0xXXXX_X9XX */\n\tif ((tmp_addr > 0x7FF) && (tmp_addr < 0xA00))\n\t\trtk_lockapi_lock(flags, __func__);\n\n\tswitch (size) {\n\tcase 1:\n\t\twriteb((u8)wval,\n\t\t       (u8 *)pdvobjpriv->pci_mem_start + (addr&~mask));\n\t\tbreak;\n\tcase 2:\n\t\twritew((u16)wval,\n\t\t       (u8 *)pdvobjpriv->pci_mem_start + (addr&~mask));\n\t\tbreak;\n\tcase 4:\n\t\twritel((u32)wval,\n\t\t       (u8 *)pdvobjpriv->pci_mem_start + (addr&~mask));\n\t\tbreak;\n\tdefault:\n\t\tRTW_WARN(\"RTD129X: %s: wrong size %d\\n\", __func__, size);\n\t\tbreak;\n\t}\n\n\tif ((tmp_addr > 0x7FF) && (tmp_addr < 0xA00))\n\t\trtk_lockapi_unlock(flags, __func__);\n\n\t/* PCIE1.1 0x9804FCEC, PCIE2.0 0x9803CCEC & 0x9803CC68\n\t * can't be used because of 1295 hardware issue.\n\t */\n\tif ((tmp_addr == 0xCEC) || ((busnumber == 0x01) &&\n\t    (tmp_addr == 0xC68))) {\n\t\twritel(translate_val, (u8 *)tran_addr);\n\t\twritel(0xFFFFF000, (u8 *)mask_addr);\n\t} else if (addr >= 0x1000) {\n\t\twritel(translate_val, (u8 *)tran_addr);\n\t}\n\n\t_exit_critical(&pdvobjpriv->io_reg_lock, &irqL);\n}\n\nstatic u8 pci_read8_129x(struct intf_hdl *phdl, u32 addr)\n{\n\tstruct dvobj_priv  *pdvobjpriv = (struct dvobj_priv  *)phdl->pintf_dev;\n\n\treturn (u8)pci_io_read_129x(pdvobjpriv, addr, 1);\n}\n\nstatic u16 pci_read16_129x(struct intf_hdl *phdl, u32 addr)\n{\n\tstruct dvobj_priv  *pdvobjpriv = (struct dvobj_priv  *)phdl->pintf_dev;\n\n\treturn (u16)pci_io_read_129x(pdvobjpriv, addr, 2);\n}\n\nstatic u32 pci_read32_129x(struct intf_hdl *phdl, u32 addr)\n{\n\tstruct dvobj_priv  *pdvobjpriv = (struct dvobj_priv  *)phdl->pintf_dev;\n\n\treturn (u32)pci_io_read_129x(pdvobjpriv, addr, 4);\n}\n\n/*\n * 2009.12.23. by tynli. Suggested by SD1 victorh.\n * For ASPM hang on AMD and Nvidia.\n * 20100212 Tynli: Do read IO operation after write for\n * all PCI bridge suggested by SD1. Origianally this is only for INTEL.\n */\nstatic int pci_write8_129x(struct intf_hdl *phdl, u32 addr, u8 val)\n{\n\tstruct dvobj_priv  *pdvobjpriv = (struct dvobj_priv  *)phdl->pintf_dev;\n\n\tpci_io_write_129x(pdvobjpriv, addr, 1, val);\n\treturn 1;\n}\n\nstatic int pci_write16_129x(struct intf_hdl *phdl, u32 addr, u16 val)\n{\n\tstruct dvobj_priv  *pdvobjpriv = (struct dvobj_priv  *)phdl->pintf_dev;\n\n\tpci_io_write_129x(pdvobjpriv, addr, 2, val);\n\treturn 2;\n}\n\nstatic int pci_write32_129x(struct intf_hdl *phdl, u32 addr, u32 val)\n{\n\tstruct dvobj_priv  *pdvobjpriv = (struct dvobj_priv  *)phdl->pintf_dev;\n\n\tpci_io_write_129x(pdvobjpriv, addr, 4, val);\n\treturn 4;\n}\n\n#else /* original*/\n\nstatic u8 pci_read8(struct intf_hdl *phdl, u32 addr)\n{\n\tstruct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev;\n\n\treturn 0xff & readb((u8 *)pdvobjpriv->pci_mem_start + addr);\n}\n\nstatic u16 pci_read16(struct intf_hdl *phdl, u32 addr)\n{\n\tstruct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev;\n\n\treturn readw((u8 *)pdvobjpriv->pci_mem_start + addr);\n}\n\nstatic u32 pci_read32(struct intf_hdl *phdl, u32 addr)\n{\n\tstruct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev;\n\n\treturn readl((u8 *)pdvobjpriv->pci_mem_start + addr);\n}\n\n/*\n * 2009.12.23. by tynli. Suggested by SD1 victorh.\n * For ASPM hang on AMD and Nvidia.\n * 20100212 Tynli: Do read IO operation after write for\n * all PCI bridge suggested by SD1. Origianally this is only for INTEL.\n */\nstatic int pci_write8(struct intf_hdl *phdl, u32 addr, u8 val)\n{\n\tstruct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev;\n\n\twriteb(val, (u8 *)pdvobjpriv->pci_mem_start + addr);\n\treturn 1;\n}\n\nstatic int pci_write16(struct intf_hdl *phdl, u32 addr, u16 val)\n{\n\tstruct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev;\n\n\twritew(val, (u8 *)pdvobjpriv->pci_mem_start + addr);\n\treturn 2;\n}\n\nstatic int pci_write32(struct intf_hdl *phdl, u32 addr, u32 val)\n{\n\tstruct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev;\n\n\twritel(val, (u8 *)pdvobjpriv->pci_mem_start + addr);\n\treturn 4;\n}\n#endif /* RTK_129X_PLATFORM */\n\nstatic void pci_read_mem(struct intf_hdl *phdl, u32 addr, u32 cnt, u8 *rmem)\n{\n\tRTW_INFO(\"%s(%d)fake function\\n\", __func__, __LINE__);\n}\n\nstatic void pci_write_mem(struct intf_hdl *phdl, u32 addr, u32 cnt, u8 *wmem)\n{\n\tRTW_INFO(\"%s(%d)fake function\\n\", __func__, __LINE__);\n}\n\nstatic u32 pci_read_port(struct intf_hdl *phdl, u32 addr, u32 cnt, u8 *rmem)\n{\n\treturn 0;\n}\n\nstatic u32 pci_write_port(struct intf_hdl *phdl, u32 addr, u32 cnt, u8 *wmem)\n{\n\t_adapter *padapter = (_adapter *)phdl->padapter;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))\n\tnetif_trans_update(padapter->pnetdev);\n#else\n\tpadapter->pnetdev->trans_start = jiffies;\n#endif\n\n\treturn 0;\n}\n\nvoid rtl8822ce_set_intf_ops(struct _io_ops *pops)\n{\n\n\t_rtw_memset((u8 *)pops, 0, sizeof(struct _io_ops));\n\n#ifdef RTK_129X_PLATFORM\n\tpops->_read8 = &pci_read8_129x;\n\tpops->_read16 = &pci_read16_129x;\n\tpops->_read32 = &pci_read32_129x;\n#else\n\tpops->_read8 = &pci_read8;\n\tpops->_read16 = &pci_read16;\n\tpops->_read32 = &pci_read32;\n#endif /* RTK_129X_PLATFORM */\n\n\tpops->_read_mem = &pci_read_mem;\n\tpops->_read_port = &pci_read_port;\n\n#ifdef RTK_129X_PLATFORM\n\tpops->_write8 = &pci_write8_129x;\n\tpops->_write16 = &pci_write16_129x;\n\tpops->_write32 = &pci_write32_129x;\n#else\n\tpops->_write8 = &pci_write8;\n\tpops->_write16 = &pci_write16;\n\tpops->_write32 = &pci_write32;\n#endif /* RTK_129X_PLATFORM */\n\n\tpops->_write_mem = &pci_write_mem;\n\tpops->_write_port = &pci_write_port;\n\n\n}\n"
  },
  {
    "path": "hal/rtl8822c/pci/rtl8822ce_led.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include <drv_types.h>\t\t/* PADAPTER */\n#include <hal_data.h>\t\t/* PHAL_DATA_TYPE */\n#include <hal_com_led.h>\t/* PLED_PCIE */\n\n#ifdef CONFIG_RTW_SW_LED\n\n/*\n *==============================================================================\n *\tPrototype of protected function.\n *==============================================================================\n */\n\n/*\n *==============================================================================\n * LED_819xUsb routines.\n *==============================================================================\n */\n\n/*\n * Description:\n *\tTurn on LED according to LedPin specified.\n */\nstatic void SwLedOn_8822ce(PADAPTER adapter, PLED_PCIE pLed)\n{\n#if 0\n\tu16 LedReg = REG_LEDCFG0;\n\tu8 LedCfg = 0;\n\tstruct led_priv\t*ledpriv = adapter_to_led(adapter);\n\n\tif (RTW_CANNOT_RUN(adapter))\n\t\treturn;\n\n\tswitch (pLed->LedPin) {\n\tcase LED_PIN_LED0:\n\t\tif (ledpriv->LedStrategy == SW_LED_MODE10)\n\t\t\tLedReg = REG_LEDCFG0;\n\t\telse\n\t\t\tLedReg = REG_LEDCFG1;\n\t\tbreak;\n\n\tcase LED_PIN_LED1:\n\t\tLedReg = REG_LEDCFG2;\n\t\tbreak;\n\n\tcase LED_PIN_GPIO0:\n\tdefault:\n\t\tbreak;\n\t}\n\n\tLedCfg = rtw_read8(adapter, LedReg);\n\tLedCfg |= BIT5; /* Set 0x4c[21] */\n\n\t/* Clear 0x4c[23:22] and 0x4c[19:16] */\n\tLedCfg &= ~(BIT7 | BIT6 | BIT3 | BIT2 | BIT1 | BIT0);\n\n\t/* SW control led0 on. */\n\trtw_write8(adapter, LedReg, LedCfg);\n\tpLed->bLedOn = _TRUE;\n#else\n\tRTW_INFO(\"%s(%d)TODO LED\\n\", __func__, __LINE__);\n#endif\n}\n\n\n/*\n * Description:\n *\tTurn off LED according to LedPin specified.\n */\nstatic void SwLedOff_8822ce(PADAPTER adapter, PLED_PCIE pLed)\n{\n#if 0\n\tu16 LedReg = REG_LEDCFG0;\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tstruct led_priv\t*ledpriv = adapter_to_led(adapter);\n\n\tif (RTW_CANNOT_RUN(adapter))\n\t\treturn;\n\n\tswitch (pLed->LedPin) {\n\tcase LED_PIN_LED0:\n\t\tif (ledpriv->LedStrategy == SW_LED_MODE10)\n\t\t\tLedReg = REG_LEDCFG0;\n\t\telse\n\t\t\tLedReg = REG_LEDCFG1;\n\t\tbreak;\n\n\tcase LED_PIN_LED1:\n\t\tLedReg = REG_LEDCFG2;\n\t\tbreak;\n\n\tcase LED_PIN_GPIO0:\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* Open-drain arrangement for controlling the LED */\n\tif (hal->bLedOpenDrain == _TRUE) {\n\t\tu8 LedCfg = rtw_read8(adapter, LedReg);\n\n\t\tLedCfg &= 0xd0; /* Set to software control. */\n\t\trtw_write8(adapter, LedReg, (LedCfg | BIT3));\n\n\t\t/* Open-drain arrangement */\n\t\tLedCfg = rtw_read8(adapter, REG_MAC_PINMUX_CFG);\n\t\tLedCfg &= 0xFE;/* Set GPIO[8] to input mode */\n\t\trtw_write8(adapter, REG_MAC_PINMUX_CFG, LedCfg);\n\n\t} else\n\t\trtw_write8(adapter, LedReg, 0x28);\n\n\tpLed->bLedOn = _FALSE;\n#else\n\tRTW_INFO(\"%s(%d)TODO LED\\n\", __func__, __LINE__);\n#endif\n}\n\n/*\n * Description:\n *\tInitialize all LED_871x objects.\n */\nvoid rtl8822ce_InitSwLeds(PADAPTER adapter)\n{\n\tstruct led_priv *pledpriv = adapter_to_led(adapter);\n\n\tpledpriv->LedControlHandler = LedControlPCIE;\n\n\tpledpriv->SwLedOn = SwLedOn_8822ce;\n\tpledpriv->SwLedOff = SwLedOff_8822ce;\n\n\tInitLed(adapter, &pledpriv->SwLed0, LED_PIN_LED0);\n\tInitLed(adapter, &pledpriv->SwLed1, LED_PIN_LED1);\n}\n\n\n/*\n * Description:\n *\tDeInitialize all LED_819xUsb objects.\n */\nvoid rtl8822ce_DeInitSwLeds(PADAPTER adapter)\n{\n\tstruct led_priv\t*ledpriv = adapter_to_led(adapter);\n\n\tDeInitLed(&ledpriv->SwLed0);\n\tDeInitLed(&ledpriv->SwLed1);\n}\n#endif\n"
  },
  {
    "path": "hal/rtl8822c/pci/rtl8822ce_ops.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#define _HCI_OPS_OS_C_\n\n#include <drv_types.h>\t\t/* PADAPTER, basic_types.h and etc. */\n#include <hal_data.h>\t\t/* HAL_DATA_TYPE, GET_HAL_DATA() and etc. */\n#include <hal_intf.h>\t\t/* struct hal_ops */\n#include \"../rtl8822c.h\"\n#include \"rtl8822ce.h\"\n\nstatic void init_bd_ring_var(_adapter *padapter)\n{\n\tstruct recv_priv *r_priv = &padapter->recvpriv;\n\tstruct xmit_priv *t_priv = &padapter->xmitpriv;\n\tu8 i = 0;\n\n\tfor (i = 0; i < HW_QUEUE_ENTRY; i++)\n\t\tt_priv->txringcount[i] = TX_BD_NUM_8822CE;\n\n\t/*\n\t * we just alloc 2 desc for beacon queue,\n\t * because we just need first desc in hw beacon.\n\t */\n\tt_priv->txringcount[BCN_QUEUE_INX] = TX_BD_NUM_8822CE_BCN;\n\n\tt_priv->txringcount[TXCMD_QUEUE_INX] = TX_BD_NUM_8822CE_CMD;\n\tt_priv->txringcount[BE_QUEUE_INX] = TX_BD_NUM_BEQ_8822CE;\n\n\t/*\n\t * BE queue need more descriptor for performance consideration\n\t * or, No more tx desc will happen, and may cause mac80211 mem leakage.\n\t */\n\tr_priv->rxbuffersize = MAX_RECVBUF_SZ;\n\tr_priv->rxringcount = RX_BD_NUM_8822CE;\n}\n\nvoid rtl8822ce_reset_bd(_adapter *padapter)\n{\n\t_irqL\tirqL;\n\tstruct xmit_priv *t_priv = &padapter->xmitpriv;\n\tstruct recv_priv *r_priv = &padapter->recvpriv;\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct xmit_buf\t*pxmitbuf = NULL;\n\tu8 *tx_bd, *rx_bd;\n\tint i, rx_queue_idx;\n\n\tInitMAC_TRXBD_8822CE(padapter);\n\n\tfor (rx_queue_idx = 0; rx_queue_idx < 1; rx_queue_idx++) {\n\t\tif (r_priv->rx_ring[rx_queue_idx].buf_desc) {\n\t\t\trx_bd = NULL;\n\t\t\tfor (i = 0; i < r_priv->rxringcount; i++) {\n\t\t\t\trx_bd = (u8 *)\n\t\t\t\t\t&r_priv->rx_ring[rx_queue_idx].buf_desc[i];\n\t\t\t}\n\t\t\tr_priv->rx_ring[rx_queue_idx].idx = 0;\n\t\t}\n\t}\n\n\t_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);\n\tfor (i = 0; i < PCI_MAX_TX_QUEUE_COUNT; i++) {\n\t\tif (t_priv->tx_ring[i].buf_desc) {\n\t\t\tstruct rtw_tx_ring *ring = &t_priv->tx_ring[i];\n\n\t\t\twhile (ring->qlen) {\n\t\t\t\ttx_bd = (u8 *)(&ring->buf_desc[ring->idx]);\n\t\t\t\tSET_TX_BD_OWN(tx_bd, 0);\n\n\t\t\t\tif (i != BCN_QUEUE_INX)\n\t\t\t\t\tring->idx =\n\t\t\t\t\t\t(ring->idx + 1) % ring->entries;\n\n\t\t\t\tpxmitbuf = rtl8822ce_dequeue_xmitbuf(ring);\n\t\t\t\tif (pxmitbuf) {\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\t\t\t\t\tdma_unmap_single(&pdvobjpriv->ppcidev->dev,\n\t\t\t\t\t\tGET_TX_BD_PHYSICAL_ADDR0_LOW(tx_bd),\n\t\t\t\t\t\tpxmitbuf->len, DMA_TO_DEVICE);\n#else\n\t\t\t\t\tpci_unmap_single(pdvobjpriv->ppcidev,\n\t\t\t\t\t\tGET_TX_BD_PHYSICAL_ADDR0_LOW(tx_bd),\n\t\t\t\t\t\tpxmitbuf->len, PCI_DMA_TODEVICE);\n#endif\n\t\t\t\t\trtw_free_xmitbuf(t_priv, pxmitbuf);\n\t\t\t\t} else {\n\t\t\t\t\tRTW_INFO(\"%s(): qlen(%d) is not zero, but have xmitbuf in pending queue\\n\",\n\t\t\t\t\t\t __func__, ring->qlen);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\tring->idx = 0;\n\t\t}\n\t}\n\t_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);\n}\n\nstatic void intf_chip_configure(PADAPTER padapter)\n{\n\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(pdvobjpriv);\n\n\t/* close ASPM for AMD defaultly */\n\tpdvobjpriv->const_amdpci_aspm = 0;\n\n\t/* ASPM PS mode. */\n\t/* 0 - Disable ASPM, 1 - Enable ASPM without Clock Req, */\n\t/* 2 - Enable ASPM with Clock Req, 3- Alwyas Enable ASPM with Clock Req, */\n\t/* 4-  Always Enable ASPM without Clock Req. */\n\t/* set default to rtl8188ee:3 RTL8192E:2 */\n\tpdvobjpriv->const_pci_aspm = 0;\n\n\t/* Setting for PCI-E device */\n\tpdvobjpriv->const_devicepci_aspm_setting = 0x03;\n\n\t/* Setting for PCI-E bridge */\n\tpdvobjpriv->const_hostpci_aspm_setting = 0x03;\n\n\t/* In Hw/Sw Radio Off situation. */\n\t/* 0 - Default, 1 - From ASPM setting without low Mac Pwr, */\n\t/* 2 - From ASPM setting with low Mac Pwr, 3 - Bus D3 */\n\t/* set default to RTL8192CE:0 RTL8192SE:2 */\n\tpdvobjpriv->const_hwsw_rfoff_d3 = 0;\n\n\t/* This setting works for those device with backdoor ASPM setting such as EPHY setting. */\n\t/* 0: Not support ASPM, 1: Support ASPM, 2: According to chipset. */\n\tpdvobjpriv->const_support_pciaspm = 1;\n\n\tpwrpriv->reg_rfoff = 0;\n\tpwrpriv->rfoff_reason = 0;\n\n\tpHalData->bL1OffSupport = _FALSE;\n}\n\n/*\n * Description:\n *\tCollect all hardware information, fill \"HAL_DATA_TYPE\".\n *\tSometimes this would be used to read MAC address.\n *\tThis function will do\n *\t1. Read Efuse/EEPROM to initialize\n *\t2. Read registers to initialize\n *\t3. Other vaiables initialization\n */\nstatic u8 read_adapter_info(PADAPTER adapter)\n{\n\tu8 ret = _FAIL;\n\n\t/*\n\t * 1. Read Efuse/EEPROM to initialize\n\t */\n\tif (rtl8822c_read_efuse(adapter) != _SUCCESS)\n\t\tgoto exit;\n\n\t/*\n\t * 2. Read registers to initialize\n\t */\n\n\t/*\n\t * 3. Other Initialization\n\t */\n\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n\nstatic BOOLEAN rtl8822ce_InterruptRecognized(PADAPTER Adapter)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\n\tBOOLEAN bRecognized = _FALSE;\n\n\t/* 2013.11.18 Glayrainx suggests that turn off IMR and\n\t * restore after cleaning ISR.\n\t */\n\trtw_write32(Adapter, REG_HIMR0, 0);\n\trtw_write32(Adapter, REG_HIMR1, 0);\n\trtw_write32(Adapter, REG_HIMR3, 0);\n\n\tpHalData->IntArray[0] = rtw_read32(Adapter, REG_HISR0);\n\tpHalData->IntArray[0] &= pHalData->IntrMask[0];\n\trtw_write32(Adapter, REG_HISR0, pHalData->IntArray[0]);\n\n\t/* For HISR extension. Added by tynli. 2009.10.07. */\n\tpHalData->IntArray[1] = rtw_read32(Adapter, REG_HISR1);\n\tpHalData->IntArray[1] &= pHalData->IntrMask[1];\n\trtw_write32(Adapter, REG_HISR1, pHalData->IntArray[1]);\n\n\t/* for H2C cmd queue */\n\tpHalData->IntArray[3] = rtw_read32(Adapter, REG_HISR3);\n\tpHalData->IntArray[3] &= pHalData->IntrMask[3];\n\trtw_write32(Adapter, REG_HISR3, pHalData->IntArray[3]);\n\n\tif (((pHalData->IntArray[0]) & pHalData->IntrMask[0]) != 0 ||\n\t    ((pHalData->IntArray[1]) & pHalData->IntrMask[1]) != 0 ||\n\t    ((pHalData->IntArray[3]) & pHalData->IntrMask[3]) != 0)\n\t\tbRecognized = _TRUE;\n\n\t/* restore IMR */\n\trtw_write32(Adapter, REG_HIMR0, pHalData->IntrMask[0] & 0xFFFFFFFF);\n\trtw_write32(Adapter, REG_HIMR1, pHalData->IntrMask[1] & 0xFFFFFFFF);\n\trtw_write32(Adapter, REG_HIMR3, pHalData->IntrMask[3] & 0xFFFFFFFF);\n\n\treturn bRecognized;\n}\n\nstatic void DisableInterrupt8822ce(PADAPTER Adapter)\n{\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);\n\n\trtw_write32(Adapter, REG_HIMR0, 0x0);\n\trtw_write32(Adapter, REG_HIMR1, 0x0);\n\trtw_write32(Adapter, REG_HIMR3, 0x0);\n\tpdvobjpriv->irq_enabled = 0;\n}\n\nstatic void rtl8822ce_enable_interrupt(PADAPTER Adapter)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);\n\n\tpdvobjpriv->irq_enabled = 1;\n\n\trtw_write32(Adapter, REG_HIMR0, pHalData->IntrMask[0] & 0xFFFFFFFF);\n\trtw_write32(Adapter, REG_HIMR1, pHalData->IntrMask[1] & 0xFFFFFFFF);\n\trtw_write32(Adapter, REG_HIMR3, pHalData->IntrMask[3] & 0xFFFFFFFF);\n\n}\n\nstatic void rtl8822ce_clear_interrupt(PADAPTER Adapter)\n{\n\tu32 u32b;\n\tHAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\n\n\tu32b = rtw_read32(Adapter, REG_HISR0_8822C);\n\trtw_write32(Adapter, REG_HISR0_8822C, u32b);\n\tpHalData->IntArray[0] = 0;\n\n\tu32b = rtw_read32(Adapter, REG_HISR1_8822C);\n\trtw_write32(Adapter, REG_HISR1_8822C, u32b);\n\tpHalData->IntArray[1] = 0;\n\n\tu32b = rtw_read32(Adapter, REG_HISR3_8822C);\n\trtw_write32(Adapter, REG_HISR1_8822C, u32b);\n\tpHalData->IntArray[3] = 0;\n}\n\nstatic void rtl8822ce_disable_interrupt(PADAPTER Adapter)\n{\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(Adapter);\n\n\trtw_write32(Adapter, REG_HIMR0, 0x0);\n\trtw_write32(Adapter, REG_HIMR1, 0x0);\t/* by tynli */\n\trtw_write32(Adapter, REG_HIMR3, 0x0);\n\tpdvobjpriv->irq_enabled = 0;\n}\n\nvoid UpdateInterruptMask8822CE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1,\n\t\t\t       u32 RemoveMSR, u32 RemoveMSR1)\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);\n\n\tDisableInterrupt8822ce(Adapter);\n\n\tif (AddMSR)\n\t\tpHalData->IntrMask[0] |= AddMSR;\n\n\tif (AddMSR1)\n\t\tpHalData->IntrMask[1] |= AddMSR1;\n\n\tif (RemoveMSR)\n\t\tpHalData->IntrMask[0] &= (~RemoveMSR);\n\n\tif (RemoveMSR1)\n\t\tpHalData->IntrMask[1] &= (~RemoveMSR1);\n\n#if 0 /* TODO */\n\tif (RemoveMSR3)\n\t\tpHalData->IntrMask[3] &= (~RemoveMSR3);\n#endif\n\n\trtl8822ce_enable_interrupt(Adapter);\n}\n\nstatic void rtl8822ce_bcn_handler(PADAPTER Adapter, u32 handled[])\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);\n\n\tif (pHalData->IntArray[0] & BIT_TXBCN0OK_MSK) {\n#ifndef CONFIG_PCI_BCN_POLLING\n#ifdef CONFIG_BCN_ICF\n\t\t/* do nothing */\n\t\tDBG_COUNTER(Adapter->int_logs.tbdok);\n#else\n\t\t/* Modify for MI temporary,\n\t\t * this processor cannot apply to multi-ap */\n\t\tPADAPTER bcn_adapter = rtw_mi_get_ap_adapter(Adapter);\n\n\t\tif (bcn_adapter->xmitpriv.beaconDMAing) {\n\t\t\tbcn_adapter->xmitpriv.beaconDMAing = _FAIL;\n\t\t\trtl8822ce_tx_isr(Adapter, BCN_QUEUE_INX);\n\t\t}\n#endif /* CONFIG_BCN_ICF */\n#endif\n\t\thandled[0] |= BIT_TXBCN0OK_MSK;\n\t}\n\n\tif (pHalData->IntArray[0] & BIT_TXBCN0ERR_MSK) {\n#ifndef CONFIG_PCI_BCN_POLLING\n#ifdef CONFIG_BCN_ICF\n\t\tRTW_INFO(\"IMR_TXBCN0ERR isr!\\n\");\n\t\tDBG_COUNTER(Adapter->int_logs.tbder);\n#else /* !CONFIG_BCN_ICF */\n\t\t/* Modify for MI temporary,\n\t\t * this processor cannot apply to multi-ap */\n\t\tPADAPTER bcn_adapter = rtw_mi_get_ap_adapter(Adapter);\n\n\t\tif (bcn_adapter->xmitpriv.beaconDMAing) {\n\t\t\tbcn_adapter->xmitpriv.beaconDMAing = _FAIL;\n\t\t\trtl8822ce_tx_isr(Adapter, BCN_QUEUE_INX);\n\t\t}\n#endif /* CONFIG_BCN_ICF */\n#endif\n\t\thandled[0] |= BIT_TXBCN0ERR_MSK;\n\t}\n\tif (pHalData->IntArray[0] & BIT_BCNDERR0_MSK) {\n#ifndef CONFIG_PCI_BCN_POLLING\n#ifdef CONFIG_BCN_ICF\n\t\tRTW_INFO(\"BIT_BCNDERR0_MSK isr!\\n\");\n\t\tDBG_COUNTER(Adapter->int_logs.bcnderr);\n#else /* !CONFIG_BCN_ICF */\n\t\t/* Release resource and re-transmit beacon to HW */\n\t\t_tasklet *bcn_tasklet;\n\t\t/* Modify for MI temporary,\n\t\t * this processor cannot apply to multi-ap */\n\t\tPADAPTER bcn_adapter = rtw_mi_get_ap_adapter(Adapter);\n\n\t\trtl8822ce_tx_isr(Adapter, BCN_QUEUE_INX);\n\t\tbcn_adapter->mlmepriv.update_bcn = _TRUE;\n\t\tbcn_tasklet = &bcn_adapter->recvpriv.irq_prepare_beacon_tasklet;\n\t\ttasklet_hi_schedule(bcn_tasklet);\n#endif /* CONFIG_BCN_ICF */\n#endif\n\t\thandled[0] |= BIT_BCNDERR0_MSK;\n\t}\n\n\tif (pHalData->IntArray[0] & BIT_BCNDMAINT0_MSK) {\n#ifndef CONFIG_PCI_BCN_POLLING\n\t\t_tasklet *bcn_tasklet;\n\t\t/* Modify for MI temporary,\n\t\t  this processor cannot apply to multi-ap */\n\t\tPADAPTER bcn_adapter = rtw_mi_get_ap_adapter(Adapter);\n\n\t\tDBG_COUNTER(Adapter->int_logs.bcndma);\n\t\tbcn_tasklet = &bcn_adapter->recvpriv.irq_prepare_beacon_tasklet;\n\t\ttasklet_hi_schedule(bcn_tasklet);\n#endif\n\t\thandled[0] |= BIT_BCNDMAINT0_MSK;\n\t}\n}\n\nstatic void rtl8822ce_rx_handler(PADAPTER Adapter, u32 handled[])\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);\n\n\tif ((pHalData->IntArray[0] & (BIT_RXOK | BIT_RDU)) ||\n\t    (pHalData->IntArray[1] & (BIT_FOVW | BIT_RXERR_INT))) {\n\t    \tDBG_COUNTER(Adapter->int_logs.rx);\n\n\t\tif (pHalData->IntArray[0] & BIT_RDU)\n\t\t\tDBG_COUNTER(Adapter->int_logs.rx_rdu);\n\n\t\tif (pHalData->IntArray[1] & BIT_FOVW)\n\t\t\tDBG_COUNTER(Adapter->int_logs.rx_fovw);\n\n\t\tpHalData->IntrMask[0] &= (~(BIT_RXOK_MSK | BIT_RDU_MSK));\n\t\tpHalData->IntrMask[1] &= (~(BIT_FOVW_MSK | BIT_RXERR_MSK));\n\t\trtw_write32(Adapter, REG_HIMR0, pHalData->IntrMask[0]);\n\t\trtw_write32(Adapter, REG_HIMR1, pHalData->IntrMask[1]);\n\t\ttasklet_hi_schedule(&Adapter->recvpriv.recv_tasklet);\n\t\thandled[0] |= pHalData->IntArray[0] & (BIT_RXOK | BIT_RDU);\n\t\thandled[1] |= pHalData->IntArray[1] & (BIT_FOVW | BIT_RXERR_INT);\n\t}\n}\n\n#if (!(defined (CONFIG_PCI_TX_POLLING) || defined (CONFIG_PCI_TX_POLLING_V2)))\nstatic void rtl8822ce_tx_handler(PADAPTER Adapter, u32 events[], u32 handled[])\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);\n\n\tif (events[0] & BIT_MGTDOK_MSK) {\n\t\tDBG_COUNTER(Adapter->int_logs.mgntok);\n\t\trtl8822ce_tx_isr(Adapter, MGT_QUEUE_INX);\n\t\thandled[0] |= BIT_MGTDOK_MSK;\n\t}\n\n\tif (events[0] & BIT_HIGHDOK_MSK) {\n\t\tDBG_COUNTER(Adapter->int_logs.highdok);\n\t\trtl8822ce_tx_isr(Adapter, HIGH_QUEUE_INX);\n\t\thandled[0] |= BIT_HIGHDOK_MSK;\n\t}\n\n\tif (events[0] & BIT_BKDOK_MSK) {\n\t\tDBG_COUNTER(Adapter->int_logs.bkdok);\n\t\trtl8822ce_tx_isr(Adapter, BK_QUEUE_INX);\n\t\thandled[0] |= BIT_BKDOK_MSK;\n\t}\n\n\tif (events[0] & BIT_BEDOK_MSK) {\n\t\tDBG_COUNTER(Adapter->int_logs.bedok);\n\t\trtl8822ce_tx_isr(Adapter, BE_QUEUE_INX);\n\t\thandled[0] |= BIT_BEDOK_MSK;\n\t}\n\n\tif (events[0] & BIT_VIDOK_MSK) {\n\t\tDBG_COUNTER(Adapter->int_logs.vidok);\n\t\trtl8822ce_tx_isr(Adapter, VI_QUEUE_INX);\n\t\thandled[0] |= BIT_VIDOK_MSK;\n\t}\n\n\tif (events[0] & BIT_VODOK_MSK) {\n\t\tDBG_COUNTER(Adapter->int_logs.vodok);\n\t\trtl8822ce_tx_isr(Adapter, VO_QUEUE_INX);\n\t\thandled[0] |= BIT_VODOK_MSK;\n\t}\n}\n#endif\n\nstatic void rtl8822ce_cmd_handler(PADAPTER Adapter, u32 handled[])\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);\n\n\tif (pHalData->IntArray[3] & BIT_SETH2CDOK_MASK) {\n\t\trtl8822ce_tx_isr(Adapter, TXCMD_QUEUE_INX);\n\t\thandled[3] |= BIT_SETH2CDOK_MASK;\n\t}\n}\n\nstatic void rtl8822ce_pci_handler(PADAPTER Adapter, u32 handled[])\n{\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);\n\n\tif (pHalData->IntArray[3] & BIT(2)) {\n\t\thandled[3] |= pHalData->IntArray[3] & (BIT(2));\n\t\tRTW_WARN(\"PCI Tx DMA Stuck!\\n\");\n\t}\n\n\tif (pHalData->IntArray[3] & BIT(3)) {\n\t\thandled[3] |= pHalData->IntArray[3] & (BIT(3));\n\t\tRTW_WARN(\"PCI Rx DMA Stuck!\\n\");\n\t}\n}\n\nstatic s32 rtl8822ce_interrupt(PADAPTER Adapter)\n{\n\t_irqL irqL;\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);\n\tstruct xmit_priv *t_priv = &Adapter->xmitpriv;\n\tint ret = _SUCCESS;\n\tu32 handled[4] = {0};\n\n\t_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);\n\n\tDBG_COUNTER(Adapter->int_logs.all);\n\n\t/* read ISR: 4/8bytes */\n\tif (rtl8822ce_InterruptRecognized(Adapter) == _FALSE) {\n\t\tret = _FAIL;\n\t\tgoto done;\n\t}\n\n\t/* <1> beacon related */\n\trtl8822ce_bcn_handler(Adapter, handled);\n\n\t/* <2> Rx related */\n\trtl8822ce_rx_handler(Adapter, handled);\n\n\t/* <3> Tx related */\n#if (!(defined (CONFIG_PCI_TX_POLLING) || defined (CONFIG_PCI_TX_POLLING_V2)))\n\trtl8822ce_tx_handler(Adapter, pHalData->IntArray, handled);\n#endif\n\n\tif (pHalData->IntArray[1] & BIT_TXFOVW) {\n\t\tDBG_COUNTER(Adapter->int_logs.txfovw);\n#if 0\n\t\tif (printk_ratelimit())\n\t\t\tRTW_WARN(\"[TXFOVW]\\n\");\n#endif\n\t\thandled[1] |= BIT_TXFOVW;\n\t}\n\n\t/* <4> Cmd related */\n\trtl8822ce_cmd_handler(Adapter, handled);\n\n\t/* <5> PCI related */\n\trtl8822ce_pci_handler(Adapter, handled);\n\n#ifdef CONFIG_LPS_LCLK\n\tif (pHalData->IntArray[0] & BIT_CPWM) {\n\t\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter);\n\n\t\t_set_workitem(&(pwrpriv->cpwm_event));\n\t\thandled[0] |= BIT_CPWM;\n\t}\n#endif\n\n\tif ((pHalData->IntArray[0] & (~handled[0])) ||\n\t\t(pHalData->IntArray[1] & (~handled[1])) ||\n\t\t(pHalData->IntArray[3] & (~handled[3]))) {\n\n\t\tif (printk_ratelimit()) {\n\t\t\tRTW_WARN(\"Unhandled ISR = %x, %x, %x\\n\",\n\t\t\t\t(pHalData->IntArray[0] & (~handled[0])),\n\t\t\t\t(pHalData->IntArray[1] & (~handled[1])),\n\t\t\t\t(pHalData->IntArray[3] & (~handled[3])));\n\t}\n\t}\ndone:\n\t_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);\n\treturn ret;\n}\n\nstatic void rtl8822ce_unmap_beacon_icf(PADAPTER Adapter)\n{\n\t_adapter *pri_adapter = GET_PRIMARY_ADAPTER(Adapter);\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(pri_adapter);\n\tstruct xmit_priv\t*pxmitpriv = &Adapter->xmitpriv;\n\tstruct xmit_buf\t*pxmitbuf;\n\tstruct rtw_tx_ring\t*ring = &pri_adapter->xmitpriv.tx_ring[BCN_QUEUE_INX];\n\tu8\t*tx_bufdesc;\n\n\ttx_bufdesc = (u8 *)&ring->buf_desc[0];\n\tpxmitbuf = &pxmitpriv->pcmd_xmitbuf[CMDBUF_BEACON];\n\tif (!pxmitbuf) {\n\t\tRTW_INFO(\"%s, fail to get xmit_buf\\n\", __func__);\n\t\treturn;\n\t}\n//\tRTW_INFO(\"FREE pxmitbuf: %p, buf_desc: %p, sz: %d\\n\", pxmitbuf, tx_bufdesc, pxmitbuf->len);\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\tdma_unmap_single(&pdvobjpriv->ppcidev->dev,\n\t\t\t GET_TX_BD_PHYSICAL_ADDR0_LOW(tx_bufdesc),\n\t\t\t pxmitbuf->len,\n\t\t\t DMA_TO_DEVICE);\n#else\n\tpci_unmap_single(pdvobjpriv->ppcidev,\n\t\t\t GET_TX_BD_PHYSICAL_ADDR0_LOW(tx_bufdesc),\n\t\t\t pxmitbuf->len,\n\t\t\t PCI_DMA_TODEVICE);\n#endif\n}\n\nu32 rtl8822ce_init_bd(_adapter *padapter)\n{\n\tstruct xmit_priv *t_priv = &padapter->xmitpriv;\n\tint\ti, ret = _SUCCESS;\n\n\tinit_bd_ring_var(padapter);\n\tret = rtl8822ce_init_rxbd_ring(padapter);\n\n\tif (ret == _FAIL)\n\t\treturn ret;\n\n\t/* general process for other queue */\n\tfor (i = 0; i < PCI_MAX_TX_QUEUE_COUNT; i++) {\n\t\tret = rtl8822ce_init_txbd_ring(padapter, i,\n\t\t\t\t\t       t_priv->txringcount[i]);\n\t\tif (ret == _FAIL)\n\t\t\tgoto err_free_rings;\n\t}\n\n\treturn ret;\n\nerr_free_rings:\n\n\trtl8822ce_free_rxbd_ring(padapter);\n\n\tfor (i = 0; i < PCI_MAX_TX_QUEUE_COUNT; i++)\n\t\tif (t_priv->tx_ring[i].buf_desc)\n\t\t\trtl8822ce_free_txbd_ring(padapter, i);\n\n\n\treturn ret;\n}\n\nu32 rtl8822ce_free_bd(_adapter *padapter)\n{\n\tstruct xmit_priv\t*t_priv = &padapter->xmitpriv;\n\tu32 i;\n\n\n\t/* free rxbd rings */\n\trtl8822ce_free_rxbd_ring(padapter);\n\n\t/* free txbd rings */\n\tfor (i = 0; i < HW_QUEUE_ENTRY; i++)\n\t\trtl8822ce_free_txbd_ring(padapter, i);\n\n\n\treturn _SUCCESS;\n}\n\nstatic u16\nhal_mdio_read_8822ce(PADAPTER Adapter, u8 Addr)\n{\n\tu16 ret = 0;\n\tu8 tmpU1b = 0, count = 0;\n\n\trtw_write8(Adapter, REG_PCIE_MIX_CFG_8822C, Addr | BIT6);\n\ttmpU1b = rtw_read8(Adapter, REG_PCIE_MIX_CFG_8822C) & BIT6;\n\tcount = 0;\n\twhile (tmpU1b && count < 20) {\n\t\trtw_udelay_os(10);\n\t\ttmpU1b = rtw_read8(Adapter, REG_PCIE_MIX_CFG_8822C) & BIT6;\n\t\tcount++;\n\t}\n\tif (tmpU1b == 0)\n\t\tret = rtw_read16(Adapter, REG_MDIO_V1_8822C);\n\n\treturn ret;\n}\n\n\nstatic void\nhal_mdio_write_8822ce(PADAPTER Adapter, u8 Addr, u16 Data)\n{\n\tu8 tmpU1b = 0, count = 0;\n\n\trtw_write16(Adapter, REG_MDIO_V1_8822C, Data);\n\trtw_write8(Adapter, REG_PCIE_MIX_CFG_8822C, Addr | BIT5);\n\ttmpU1b = rtw_read8(Adapter, REG_PCIE_MIX_CFG_8822C) & BIT5;\n\tcount = 0;\n\twhile (tmpU1b && count < 20) {\n\t\trtw_udelay_os(10);\n\t\ttmpU1b = rtw_read8(Adapter, REG_PCIE_MIX_CFG_8822C) & BIT5;\n\t\tcount++;\n\t}\n}\n\n\nstatic void hal_dbi_write_8822ce(PADAPTER Adapter, u16 Addr, u8 Data)\n{\n\tu8 tmpU1b = 0, count = 0;\n\tu16 WriteAddr = 0, Remainder = Addr % 4;\n\n\n\t/* Write DBI 1Byte Data */\n\tWriteAddr = REG_DBI_WDATA_V1_8822C + Remainder;\n\trtw_write8(Adapter, WriteAddr, Data);\n\n\t/* Write DBI 2Byte Address & Write Enable */\n\tWriteAddr = (Addr & 0xfffc) | (BIT0 << (Remainder + 12));\n\trtw_write16(Adapter, REG_DBI_FLAG_V1_8822C, WriteAddr);\n\n\t/* Write DBI Write Flag */\n\trtw_write8(Adapter, REG_DBI_FLAG_V1_8822C + 2, 0x1);\n\n\ttmpU1b = rtw_read8(Adapter, REG_DBI_FLAG_V1_8822C + 2);\n\tcount = 0;\n\twhile (tmpU1b && count < 20) {\n\t\trtw_udelay_os(10);\n\t\ttmpU1b = rtw_read8(Adapter, REG_DBI_FLAG_V1_8822C + 2);\n\t\tcount++;\n\t}\n}\n\nstatic u8 hal_dbi_read_8822ce(PADAPTER Adapter, u16 Addr)\n{\n\tu16 ReadAddr = Addr & 0xfffc;\n\tu8 ret = 0, tmpU1b = 0, count = 0;\n\n\trtw_write16(Adapter, REG_DBI_FLAG_V1_8822C, ReadAddr);\n\trtw_write8(Adapter, REG_DBI_FLAG_V1_8822C + 2, 0x2);\n\ttmpU1b = rtw_read8(Adapter, REG_DBI_FLAG_V1_8822C + 2);\n\tcount = 0;\n\twhile (tmpU1b && count < 20) {\n\t\trtw_udelay_os(10);\n\t\ttmpU1b = rtw_read8(Adapter, REG_DBI_FLAG_V1_8822C + 2);\n\t\tcount++;\n\t}\n\tif (tmpU1b == 0) {\n\t\tReadAddr = REG_DBI_RDATA_V1_8822C + Addr % 4;\n\t\tret = rtw_read8(Adapter, ReadAddr);\n\t}\n\n\treturn ret;\n}\n\nvoid rtl8822ce_aspm_config_l1off(PADAPTER padapter, u8 enable)\n{\n\tu8 tmp8;\n\n\ttmp8 = hal_dbi_read_8822ce(padapter, 0x718);\n\n\tif (enable)\n\t\thal_dbi_write_8822ce(padapter, 0x718, (tmp8 | BIT5));\n\telse\n\t\thal_dbi_write_8822ce(padapter, 0x718, (tmp8 & (~BIT5)));\n}\n\nstatic u8 sethwreg(PADAPTER padapter, u8 variable, u8 *val)\n{\n\tu8 ret = _SUCCESS;\n\n\tswitch (variable) {\n\tcase HW_VAR_DBI:\n\t{\n\t\tu16 *pCmd;\n\n\t\tpCmd = (u16 *)val;\n\t\thal_dbi_write_8822ce(padapter, pCmd[0], (u8)pCmd[1]);\n\t\tbreak;\n\t}\n\tcase HW_VAR_MDIO:\n\t{\n\t\tu16 *pCmd;\n\n\t\tpCmd = (u16 *)val;\n\t\thal_mdio_write_8822ce(padapter, (u8)pCmd[0], pCmd[1]);\n\t\tbreak;\n\t}\n#ifdef CONFIG_LPS_LCLK\n\tcase HW_VAR_SET_RPWM:\n\t{\n\t\tu8 ps_state = *((u8 *)val);\n\t\t/* rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) for 88e. */\n\t\t/* BIT0 value - 1: 32k, 0:40MHz. */\n\t\t/* BIT4 value - Power Gated. */\n\t\t/* BIT6 value - 1: report cpwm value after success set, 0:do not report. */\n\t\t/* BIT7 value - Toggle bit change. */\n\t\t/* modify by Thomas. 2012/4/2. */\n#ifdef CONFIG_LPS_PG\n\t\tif ((ps_state & BIT(0)) && (adapter_to_pwrctl(padapter)->lps_level == LPS_PG))\n\t\t\tps_state |= BIT(4);\n#endif\n\t\tps_state = ps_state & 0xD1;\n\t\t/* RTW_INFO(\"##### Change RPWM value to = %x for switch clk #####\\n\",ps_state); */\n\t\trtw_write8(padapter, REG_PCIE_HRPWM1_V1_8822C, ps_state);\n\t\tbreak;\n\t}\n#endif\n\tdefault:\n\t\tret = rtl8822c_sethwreg(padapter, variable, val);\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstatic void gethwreg(PADAPTER padapter, u8 variable, u8 *val)\n{\n\tswitch (variable) {\n\tcase HW_VAR_DBI:\n\t\t*val = hal_dbi_read_8822ce(padapter, *((u16 *)(val)));\n\t\tbreak;\n\n\tcase HW_VAR_MDIO:\n\t\t*((u16 *)(val)) = hal_mdio_read_8822ce(padapter, *val);\n\t\tbreak;\n\n\tcase HW_VAR_L1OFF_NIC_SUPPORT:\n\t\t{\n\t\tu8 l1off;\n\n\t\tl1off = hal_dbi_read_8822ce(padapter, 0x168);\n\t\tif (l1off & (BIT2|BIT3))\n\t\t\t*val = _TRUE;\n\t\telse\n\t\t\t*val = _FALSE;\n\t\t}\n\t\tbreak;\n\n\tcase HW_VAR_L1OFF_CAPABILITY:\n\t\t{\n\t\tu8 l1off;\n\n\t\tl1off = hal_dbi_read_8822ce(padapter, 0x164);\n\t\tif (l1off & (BIT2|BIT3))\n\t\t\t*val = _TRUE;\n\t\telse\n\t\t\t*val = _FALSE;\n\t\t}\n\t\tbreak;\n#ifdef CONFIG_LPS_LCLK\n\tcase HW_VAR_CPWM:\n\t\t*val = rtw_read8(padapter, REG_PCIE_HCPWM1_V1_8822C);\n\t\tbreak;\n#endif\n\tcase HW_VAR_RPWM_TOG:\n\t\t*val = rtw_read8(padapter, REG_PCIE_HRPWM1_V1_8822C);\n\t\t*val &= BIT_TOGGLE_8822C;\n\t\tbreak;\n\tdefault:\n\t\trtl8822c_gethwreg(padapter, variable, val);\n\t\tbreak;\n\t}\n\n}\n\n/*\n\tDescription:\n\t\tQuery setting of specified variable.\n*/\nstatic u8 gethaldefvar(PADAPTER\tpadapter, HAL_DEF_VARIABLE eVariable, void *pValue)\n{\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\tu8 bResult = _SUCCESS;\n\n\tswitch (eVariable) {\n\n\tcase HAL_DEF_MAX_RECVBUF_SZ:\n\t\t*((u32 *)pValue) = MAX_RECVBUF_SZ;\n\t\tbreak;\n\n\tcase HW_VAR_MAX_RX_AMPDU_FACTOR:\n\t\t*(HT_CAP_AMPDU_FACTOR *)pValue = MAX_AMPDU_FACTOR_64K;\n\t\tbreak;\n\tdefault:\n\t\tbResult = rtl8822c_gethaldefvar(padapter, eVariable, pValue);\n\t\tbreak;\n\t}\n\n\treturn bResult;\n}\n\n#ifdef CONFIG_RFKILL_POLL\nstatic bool rtl8822ce_gpio_radio_on_off_check(_adapter *adapter, u8 *valid)\n{\n\tu8 tmp8;\n\tbool ret;\n\n\ttmp8  = rtw_read32(adapter, REG_GPIO_EXT_CTRL);\n\tret = (tmp8 & BIT(1)) ? _FALSE : _TRUE;\t/* Power down pin output value, low active */\n\t*valid = 1;\n\n\treturn ret;\n}\n#endif\n\n#ifdef CONFIG_PCI_TX_POLLING\nstatic void rtl8822ce_tx_poll_handler(PADAPTER Adapter)\n{\n\t_irqL irqL;\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);\n\n\t_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);\n\trtl8822ce_tx_isr(Adapter, MGT_QUEUE_INX);\n\trtl8822ce_tx_isr(Adapter, HIGH_QUEUE_INX);\n\trtl8822ce_tx_isr(Adapter, BK_QUEUE_INX);\n#ifndef CONFIG_PCI_TX_POLLING_V2\n\trtl8822ce_tx_isr(Adapter, BE_QUEUE_INX);\n#endif\n\trtl8822ce_tx_isr(Adapter, VI_QUEUE_INX);\n\trtl8822ce_tx_isr(Adapter, VO_QUEUE_INX);\n\t_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);\n}\n#endif\n\nvoid rtl8822ce_set_hal_ops(PADAPTER padapter)\n{\n\tstruct hal_ops *ops;\n\tint err;\n\n\terr = rtl8822ce_halmac_init_adapter(padapter);\n\tif (err) {\n\t\tRTW_INFO(\"%s: [ERROR]HALMAC initialize FAIL!\\n\", __func__);\n\t\treturn;\n\t}\n\n\trtl8822c_set_hal_ops(padapter);\n\n\tops = &padapter->hal_func;\n\n\tops->hal_init = rtl8822ce_init;\n\tops->hal_deinit = rtl8822ce_deinit;\n\tops->inirp_init = rtl8822ce_init_bd;\n\tops->inirp_deinit = rtl8822ce_free_bd;\n\tops->irp_reset = rtl8822ce_reset_bd;\n\tops->init_xmit_priv = rtl8822ce_init_xmit_priv;\n\tops->free_xmit_priv = rtl8822ce_free_xmit_priv;\n\tops->init_recv_priv = rtl8822ce_init_recv_priv;\n\tops->free_recv_priv = rtl8822ce_free_recv_priv;\n\n#ifdef CONFIG_RTW_SW_LED\n\tops->InitSwLeds = rtl8822ce_InitSwLeds;\n\tops->DeInitSwLeds = rtl8822ce_DeInitSwLeds;\n#endif\n\n\tops->init_default_value = rtl8822ce_init_default_value;\n\tops->intf_chip_configure = intf_chip_configure;\n\tops->read_adapter_info = read_adapter_info;\n\n\tops->enable_interrupt = rtl8822ce_enable_interrupt;\n\tops->disable_interrupt = rtl8822ce_disable_interrupt;\n\tops->interrupt_handler = rtl8822ce_interrupt;\n\t/*\n\t\tops->check_ips_status = check_ips_status;\n\t*/\n\tops->clear_interrupt = rtl8822ce_clear_interrupt;\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) ||\\\n\tdefined(CONFIG_PCI_HCI)\n\t/*\n\t\tops->clear_interrupt = clear_interrupt_all;\n\t*/\n#endif\n\tops->get_hal_def_var_handler = gethaldefvar;\n\n\tops->set_hw_reg_handler = sethwreg;\n\tops->GetHwRegHandler = gethwreg;\n\n\tops->hal_xmit = rtl8822ce_hal_xmit;\n\tops->mgnt_xmit = rtl8822ce_mgnt_xmit;\n\tops->hal_xmitframe_enqueue = rtl8822ce_hal_xmitframe_enqueue;\n#ifdef CONFIG_HOSTAPD_MLME\n\tops->hostap_mgnt_xmit_entry = rtl8822ce_hostap_mgnt_xmit_entry;\n#endif\n\n#ifdef CONFIG_XMIT_THREAD_MODE\n\t/* vincent TODO */\n\tops->xmit_thread_handler = rtl8822ce_xmit_buf_handler;\n#endif\n\n\tops->hal_set_l1ssbackdoor_handler = rtl8822ce_aspm_config_l1off;\n#ifdef CONFIG_RFKILL_POLL\n\tops->hal_radio_onoff_check = rtl8822ce_gpio_radio_on_off_check;\n#endif\n#ifdef CONFIG_PCI_TX_POLLING\n\tops->tx_poll_handler = rtl8822ce_tx_poll_handler;\n#endif\n\tops->unmap_beacon_icf = rtl8822ce_unmap_beacon_icf;\n}\n"
  },
  {
    "path": "hal/rtl8822c/pci/rtl8822ce_recv.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTL8822CE_RECV_C_\n\n#include <drv_types.h>\t\t/* PADAPTER and etc. */\n#include <hal_data.h>\t\t/* HAL_DATA_TYPE */\n#include \"../rtl8822c.h\"\n#include \"rtl8822ce.h\"\n\n/* Debug Buffer Descriptor Ring */\n\n/*#define BUF_DESC_DEBUG*/\n#ifdef BUF_DESC_DEBUG\n#define buf_desc_debug(...) do {\\\n\t\tRTW_INFO(\"BUF_DESC:\" __VA_ARGS__);\\\n\t} while (0)\n#else\n#define buf_desc_debug(...)  do {} while (0)\n#endif\n\n/*\n * Wait until rx data is ready\n *\treturn value: _SUCCESS if Rx packet is ready, _FAIL if not ready\n */\n\nstatic u32 rtl8822ce_wait_rxrdy(_adapter *padapter,\n\t\t\t\tu8 *rx_bd, u16 rx_q_idx)\n{\n\tstruct recv_priv *r_priv = &padapter->recvpriv;\n\tu8 first_seg = 0, last_seg = 0;\n\tu16 total_len = 0, read_cnt = 0;\n\n\tstatic BOOLEAN start_rx = _FALSE;\n\tu16 status = _SUCCESS;\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\n\tif (rx_bd == NULL)\n\t\treturn _FAIL;\n\n\ttotal_len = (u16)GET_RX_BD_TOTALRXPKTSIZE(rx_bd);\n\tfirst_seg = (u8)GET_RX_BD_FS(rx_bd);\n\tlast_seg = (u8)GET_RX_BD_LS(rx_bd);\n\n\tbuf_desc_debug(\"RX:%s enter: rx_bd addr = %p, total_len=%d, first_seg=%d, last_seg=%d, read_cnt %d, index %d, address %p\\n\",\n\t\t       __func__,\n\t\t(u8 *)&r_priv->rx_ring[rx_q_idx].desc[r_priv->rx_ring[rx_q_idx].idx],\n\t\t       total_len, first_seg, last_seg, read_cnt,\n\t\t       r_priv->rx_ring[rx_q_idx].idx, rx_bd);\n\n#if defined(USING_RX_TAG)\n\t/* Rx Tag not ported */\n\tif (!start_rx) {\n\t\tstart_rx = _TRUE;\n\t\tpHalData->RxTag = 1;\n\t} else {\n\t\twhile (total_len != (pHalData->RxTag + 1)) {\n\n\t\t\tread_cnt++;\n\n\t\t\ttotal_len = (u16)GET_RX_BD_TOTALRXPKTSIZE(rx_bd);\n\t\t\tfirst_seg = (u8)GET_RX_BD_FS(rx_bd);\n\t\t\tlast_seg = (u8)GET_RX_BD_LS(rx_bd);\n\n\t\t\tif (read_cnt > 10000) {\n\t\t\t\tpHalData->RxTag = total_len;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif (total_len == 0 && pHalData->RxTag == 0x1fff)\n\t\t\t\tbreak;\n\t\t}\n\t\tpHalData->RxTag = total_len;\n\t}\n#else\n\twhile (total_len == 0) {\n\t\tread_cnt++;\n\n\t\ttotal_len = (u16) GET_RX_BD_TOTALRXPKTSIZE(rx_bd);\n\t\tfirst_seg = (u8) GET_RX_BD_FS(rx_bd);\n\t\tlast_seg = (u8) GET_RX_BD_LS(rx_bd);\n\n\t\tif (read_cnt > 20) {\n\t\t\tstatus = _FAIL;\n\t\t\tbreak;\n\t\t}\n\t}\n#endif\n\n\tbuf_desc_debug(\"RX:%s exit total_len=%d, rx_tag = %d, first_seg=%d, last_seg=%d, read_cnt %d\\n\",\n\t\t       __func__, total_len, pHalData->RxTag,\n\t\t       first_seg, last_seg, read_cnt);\n\n\treturn status;\n}\n\n/*\n * Check the number of rxdec to be handled between\n *   \"index of RX queue descriptor maintained by host (write pointer)\" and\n *   \"index of RX queue descriptor maintained by hardware (read pointer)\"\n */\nstatic u16 rtl8822ce_check_rxdesc_remain(_adapter *padapter, int rx_queue_idx)\n{\n\tstruct recv_priv *r_priv = &padapter->recvpriv;\n\tu16 desc_idx_hw = 0, desc_idx_host = 0, num_rxdesc_to_handle = 0;\n\tu32 tmp_4bytes = 0;\n\tstatic BOOLEAN\tstart_rx = FALSE;\n\n\n\ttmp_4bytes = rtw_read32(padapter, REG_RXQ_RXBD_IDX_8822C);\n\tdesc_idx_hw = (u16)((tmp_4bytes >> 16) & 0x7ff);\n\tdesc_idx_host = (u16)(tmp_4bytes & 0x7ff);\n\n\t/*\n\t * make sure driver does not handle packet if hardware pointer\n\t * keeps in zero in initial state\n\t */\n\tbuf_desc_debug(\"RX:%s(%d) reg_value %x\\n\", __func__, __LINE__,\n\t\t       tmp_4bytes);\n\n\tif (desc_idx_hw > 0)\n\t\tstart_rx = TRUE;\n\n\tif (!start_rx)\n\t\treturn 0;\n\n\tif (desc_idx_hw < desc_idx_host)\n\t\t/* hw idx is turn around */\n\t\tnum_rxdesc_to_handle = RX_BD_NUM_8822CE - desc_idx_host + desc_idx_hw;\n\telse\n\t\tnum_rxdesc_to_handle = desc_idx_hw - desc_idx_host;\n\n\tif (num_rxdesc_to_handle == 0)\n\t\treturn 0;\n\n\tr_priv->rx_ring[rx_queue_idx].idx = desc_idx_host;\n\n\tbuf_desc_debug(\"RX:%s reg_val %x, hw_idx %x, host_idx %x, desc to handle = %d\\n\",\n\t\t__func__, tmp_4bytes, desc_idx_hw, desc_idx_host, num_rxdesc_to_handle);\n\n\treturn num_rxdesc_to_handle;\n}\n\nstatic void rtl8822ce_rx_mpdu(_adapter *padapter)\n{\n\tstruct recv_priv *r_priv = &padapter->recvpriv;\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\t_queue *pfree_recv_queue = &r_priv->free_recv_queue;\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\tunion recv_frame *precvframe = NULL;\n\tstruct rx_pkt_attrib *pattrib = NULL;\n\tint rx_q_idx = RX_MPDU_QUEUE;\n\tu32 count = r_priv->rxringcount;\n\tu16 remaing_rxdesc = 0;\n\tu8 *rx_bd;\n\tstruct sk_buff *skb;\n\tu32 desc_size;\n\n\n\tdesc_size = rtl8822c_get_rx_desc_size(padapter);\n\n\t/* RX NORMAL PKT */\n\n\tremaing_rxdesc = rtl8822ce_check_rxdesc_remain(padapter, rx_q_idx);\n\twhile (remaing_rxdesc) {\n\n\t\t/* rx descriptor */\n\t\trx_bd = (u8 *)&r_priv->rx_ring[rx_q_idx].buf_desc[r_priv->rx_ring[rx_q_idx].idx];\n\n\t\t/* rx packet */\n\t\tskb = r_priv->rx_ring[rx_q_idx].rx_buf[r_priv->rx_ring[rx_q_idx].idx];\n\n\t\tbuf_desc_debug(\"RX:%s(%d), rx_bd addr = %x, total_len = %d, ring idx = %d\\n\",\n\t\t\t       __func__, __LINE__, (u32)rx_bd,\n\t\t\t       GET_RX_BD_TOTALRXPKTSIZE(rx_bd),\n\t\t\t       r_priv->rx_ring[rx_q_idx].idx);\n\n\t\tbuf_desc_debug(\"RX:%s(%d), skb(rx_buf)=%x, buf addr(virtual = %x, phisycal = %x)\\n\",\n\t\t\t       __func__, __LINE__, (u32)skb,\n\t\t\t       (u32)(skb_tail_pointer(skb)),\n\t\t\t       GET_RX_BD_PHYSICAL_ADDR_LOW(rx_bd));\n\n\t\t/* wait until packet is ready. this operation is similar to\n\t\t * check own bit and should be called before pci_unmap_single\n\t\t * which release memory mapping\n\t\t */\n\n\t\tif (rtl8822ce_wait_rxrdy(padapter, rx_bd, rx_q_idx) !=\n\t\t    _SUCCESS)\n\t\t\tbuf_desc_debug(\"RX:%s(%d) packet not ready\\n\",\n\t\t\t\t       __func__, __LINE__);\n\n\t\t{\n\t\t\tprecvframe = rtw_alloc_recvframe(pfree_recv_queue);\n\n\t\t\tif (precvframe == NULL) {\n\t\t\t\tgoto done;\n\t\t\t}\n\n\t\t\t_rtw_init_listhead(&precvframe->u.hdr.list);\n\t\t\tprecvframe->u.hdr.len = 0;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\t\t\tdma_unmap_single(&pdvobjpriv->ppcidev->dev,\n\t\t\t\t\t *((dma_addr_t *)skb->cb),\n\t\t\t\t\t r_priv->rxbuffersize,\n\t\t\t\t\t DMA_FROM_DEVICE);\n#else\n\t\t\tpci_unmap_single(pdvobjpriv->ppcidev,\n\t\t\t\t\t *((dma_addr_t *)skb->cb),\n\t\t\t\t\t r_priv->rxbuffersize,\n\t\t\t\t\t PCI_DMA_FROMDEVICE);\n#endif\n\n\t\t\trtl8822c_query_rx_desc(precvframe, skb->data);\n\t\t\tpattrib = &precvframe->u.hdr.attrib;\n\n#ifdef CONFIG_RX_PACKET_APPEND_FCS\n\t\t\t{\n\t\t\t\tstruct mlme_priv *mlmepriv =\n\t\t\t\t\t\t&padapter->mlmepriv;\n\n\t\t\t\tif (check_fwstate(mlmepriv,\n\t\t\t\t\t\t  WIFI_MONITOR_STATE) == _FALSE)\n\t\t\t\t\tif (pattrib->pkt_rpt_type == NORMAL_RX)\n\t\t\t\t\t\tpattrib->pkt_len -=\n\t\t\t\t\t\t\tIEEE80211_FCS_LEN;\n\t\t\t}\n#endif\n\n\t\t\tbuf_desc_debug(\"RX:%s(%d), pkt_len = %d, pattrib->drvinfo_sz = %d, pattrib->qos = %d, pattrib->shift_sz = %d\\n\",\n\t\t\t\t       __func__, __LINE__, pattrib->pkt_len,\n\t\t\t\t       pattrib->drvinfo_sz, pattrib->qos,\n\t\t\t\t       pattrib->shift_sz);\n\n\t\t\tif (rtw_os_alloc_recvframe(padapter, precvframe,\n\t\t\t\t   (skb->data + desc_size +\n\t\t\t\t    pattrib->drvinfo_sz + pattrib->shift_sz),\n\t\t\t\t\t\t   skb) == _FAIL) {\n\n\t\t\t\trtw_free_recvframe(precvframe,\n\t\t\t\t\t\t   &r_priv->free_recv_queue);\n\n\t\t\t\tRTW_INFO(\"rtl8822ce_rx_mpdu:can't allocate memory for skb copy\\n\");\n\t\t\t\t*((dma_addr_t *) skb->cb) =\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\t\t\t\t\tdma_map_single(&pdvobjpriv->ppcidev->dev,\n\t\t\t\t\t\t       skb_tail_pointer(skb),\n\t\t\t\t\t\t       r_priv->rxbuffersize,\n\t\t\t\t\t\t       DMA_FROM_DEVICE);\n#else\n\t\t\t\t\tpci_map_single(pdvobjpriv->ppcidev,\n\t\t\t\t\t\t       skb_tail_pointer(skb),\n\t\t\t\t\t\t       r_priv->rxbuffersize,\n\t\t\t\t\t\t       PCI_DMA_FROMDEVICE);\n#endif\n\t\t\t\tgoto done;\n\t\t\t}\n\n\t\t\trecvframe_put(precvframe, pattrib->pkt_len);\n\n\t\t\tif (pattrib->pkt_rpt_type == NORMAL_RX) {\n\t\t\t\t/* Normal rx packet */\n\t\t\t\tpre_recv_entry(precvframe, pattrib->physt ? ((u8 *)(skb->data) + desc_size) : NULL);\n\t\t\t} else {\n\t\t\t\tif (pattrib->pkt_rpt_type == C2H_PACKET)\n\t\t\t\t\trtl8822c_c2h_handler_no_io(padapter,\n\t\t\t\t\t\t\t     skb->data,\n\t\t\t\t\t\t\t     desc_size +\n\t\t\t\t\t\t\t     pattrib->pkt_len);\n\n\t\t\t\trtw_free_recvframe(precvframe,\n\t\t\t\t\t\t   pfree_recv_queue);\n\t\t\t}\n\t\t\t*((dma_addr_t *) skb->cb) =\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\t\t\t\tdma_map_single(&pdvobjpriv->ppcidev->dev,\n\t\t\t\t\t       skb_tail_pointer(skb),\n\t\t\t\t\t       r_priv->rxbuffersize,\n\t\t\t\t\t       DMA_FROM_DEVICE);\n#else\n\t\t\t\tpci_map_single(pdvobjpriv->ppcidev,\n\t\t\t\t\t       skb_tail_pointer(skb),\n\t\t\t\t\t       r_priv->rxbuffersize,\n\t\t\t\t\t       PCI_DMA_FROMDEVICE);\n#endif\n\t\t}\ndone:\n\n\n\t\tSET_RX_BD_PHYSICAL_ADDR_LOW(rx_bd, *((dma_addr_t *)skb->cb));\n\t\t/*Max. MPDU size is 11454 bytes, fix Rx buffer size to 12K is safe.*/\n\t\t/*Even most Rx frame size is smaller than 4K, 12K Rx buffer size will not affect Rx efficiency.*/\n\t\tSET_RX_BD_RXBUFFSIZE(rx_bd, 12*1024);\n\n\t\tr_priv->rx_ring[rx_q_idx].idx =\n\t\t\t(r_priv->rx_ring[rx_q_idx].idx + 1) %\n\t\t\tr_priv->rxringcount;\n\n\t\trtw_write16(padapter, REG_RXQ_RXBD_IDX,\n\t\t\t    r_priv->rx_ring[rx_q_idx].idx);\n\n\t\tbuf_desc_debug(\"RX:%s(%d) reg_value %x\\n\", __func__, __LINE__,\n\t\t\t       rtw_read32(padapter, REG_RXQ_RXBD_IDX));\n\n\t\tremaing_rxdesc--;\n\t}\n}\n\nstatic void rtl8822ce_recv_tasklet(void *priv)\n{\n\t_irqL\tirqL;\n\t_adapter\t*padapter = (_adapter *)priv;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\n\trtl8822ce_rx_mpdu(padapter);\n\t_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);\n\tpHalData->IntrMask[0] |= (BIT_RXOK_MSK_8822C | BIT_RDU_MSK_8822C);\n\tpHalData->IntrMask[1] |= BIT_FOVW_MSK_8822C;\n\trtw_write32(padapter, REG_HIMR0_8822C, pHalData->IntrMask[0]);\n\trtw_write32(padapter, REG_HIMR1_8822C, pHalData->IntrMask[1]);\n\t_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);\n}\n\nstatic void rtl8822ce_xmit_beacon(PADAPTER Adapter)\n{\n#if defined(CONFIG_AP_MODE) && defined(CONFIG_NATIVEAP_MLME)\n\tstruct mlme_priv *pmlmepriv = &Adapter->mlmepriv;\n\n\tif (MLME_IS_AP(Adapter) || MLME_IS_MESH(Adapter)) {\n\t\t/* send_beacon(Adapter); */\n\t\tif (pmlmepriv->update_bcn == _TRUE)\n\t\t\ttx_beacon_hdl(Adapter, NULL);\n\t}\n#endif\n}\n\nstatic void rtl8822ce_prepare_bcn_tasklet(void *priv)\n{\n\t_adapter *padapter = (_adapter *)priv;\n\n\trtl8822ce_xmit_beacon(padapter);\n}\n\ns32 rtl8822ce_init_recv_priv(_adapter *padapter)\n{\n\tstruct recv_priv\t*precvpriv = &padapter->recvpriv;\n\ts32\tret = _SUCCESS;\n\n\n#ifdef PLATFORM_LINUX\n\ttasklet_init(&precvpriv->recv_tasklet,\n\t\t     (void(*)(unsigned long))rtl8822ce_recv_tasklet,\n\t\t     (unsigned long)padapter);\n\n\ttasklet_init(&precvpriv->irq_prepare_beacon_tasklet,\n\t\t     (void(*)(unsigned long))rtl8822ce_prepare_bcn_tasklet,\n\t\t     (unsigned long)padapter);\n#endif\n\n\n\treturn ret;\n}\n\nvoid rtl8822ce_free_recv_priv(_adapter *padapter)\n{\n\n}\n\nint rtl8822ce_init_rxbd_ring(_adapter *padapter)\n{\n\tstruct recv_priv\t*r_priv = &padapter->recvpriv;\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct pci_dev\t*pdev = pdvobjpriv->ppcidev;\n\tstruct net_device\t*dev = padapter->pnetdev;\n\tdma_addr_t *mapping = NULL;\n\tstruct sk_buff *skb = NULL;\n\tu8\t*rx_desc = NULL;\n\tint\ti, rx_queue_idx;\n\n\n\t/* rx_queue_idx 0:RX_MPDU_QUEUE */\n\t/* rx_queue_idx 1:RX_CMD_QUEUE */\n\tfor (rx_queue_idx = 0; rx_queue_idx < 1; rx_queue_idx++) {\n\t\tr_priv->rx_ring[rx_queue_idx].buf_desc =\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\t\t\tdma_alloc_coherent(&pdev->dev,\n\t\t\t     sizeof(*r_priv->rx_ring[rx_queue_idx].buf_desc) *\n\t\t\t\t\t     r_priv->rxringcount,\n\t\t\t\t     &r_priv->rx_ring[rx_queue_idx].dma, GFP_KERNEL);\n#else\n\t\t\tpci_alloc_consistent(pdev,\n\t\t\t     sizeof(*r_priv->rx_ring[rx_queue_idx].buf_desc) *\n\t\t\t\t\t     r_priv->rxringcount,\n\t\t\t\t     &r_priv->rx_ring[rx_queue_idx].dma);\n#endif\n\n\t\tif (!r_priv->rx_ring[rx_queue_idx].buf_desc ||\n\t\t    (unsigned long)r_priv->rx_ring[rx_queue_idx].buf_desc &\n\t\t    0xFF) {\n\t\t\tRTW_INFO(\"Cannot allocate RX ring\\n\");\n\t\t\treturn _FAIL;\n\t\t}\n\n\t\t_rtw_memset(r_priv->rx_ring[rx_queue_idx].buf_desc, 0,\n\t\t\t    sizeof(*r_priv->rx_ring[rx_queue_idx].buf_desc) *\n\t\t\t    r_priv->rxringcount);\n\t\tr_priv->rx_ring[rx_queue_idx].idx = 0;\n\n\t\tfor (i = 0; i < r_priv->rxringcount; i++) {\n\t\t\tskb = dev_alloc_skb(r_priv->rxbuffersize);\n\t\t\tif (!skb) {\n\t\t\t\tRTW_INFO(\"Cannot allocate skb for RX ring\\n\");\n\t\t\t\treturn _FAIL;\n\t\t\t}\n\n\t\t\trx_desc =\n\t\t\t\t(u8 *)(&r_priv->rx_ring[rx_queue_idx].buf_desc[i]);\n\t\t\tr_priv->rx_ring[rx_queue_idx].rx_buf[i] = skb;\n\t\t\tmapping = (dma_addr_t *)skb->cb;\n\n\t\t\t/* just set skb->cb to mapping addr\n\t\t\t * for pci_unmap_single use */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\t\t\t*mapping = dma_map_single(&pdev->dev, skb_tail_pointer(skb),\n\t\t\t\t\t\t  r_priv->rxbuffersize,\n\t\t\t\t\t\t  DMA_FROM_DEVICE);\n#else\n\t\t\t*mapping = pci_map_single(pdev, skb_tail_pointer(skb),\n\t\t\t\t\t\t  r_priv->rxbuffersize,\n\t\t\t\t\t\t  PCI_DMA_FROMDEVICE);\n#endif\n\n\t\t\t/* Reset FS, LS, Total len */\n\t\t\tSET_RX_BD_LS(rx_desc, 0);\n\t\t\tSET_RX_BD_FS(rx_desc, 0);\n\t\t\tSET_RX_BD_TOTALRXPKTSIZE(rx_desc, 0);\n\t\t\t/*Max. MPDU size is 11454 bytes, fix Rx buffer size to 12K is safe.*/\n\t\t\t/*Even most Rx frame size is smaller than 4K, 12K Rx buffer size will not affect Rx efficiency.*/\n\t\t\tSET_RX_BD_RXBUFFSIZE(rx_desc, 12*1024);\n\t\t\tSET_RX_BD_PHYSICAL_ADDR_LOW(rx_desc, *mapping);\n\n\t\t\tbuf_desc_debug(\"RX:rx buffer desc addr[%d] = %x, skb(rx_buf) = %x, buffer addr (virtual = %x, physical = %x)\\n\",\n\t\t\t\ti, (u32)&r_priv->rx_ring[rx_queue_idx].buf_desc[i],\n\t\t\t\t(u32)r_priv->rx_ring[rx_queue_idx].rx_buf[i],\n\t\t\t\t(u32)(skb_tail_pointer(skb)), (u32)(*mapping));\n\t\t}\n\t}\n\n\n\treturn _SUCCESS;\n}\n\nvoid rtl8822ce_free_rxbd_ring(_adapter *padapter)\n{\n\tstruct recv_priv *r_priv = &padapter->recvpriv;\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct pci_dev *pdev = pdvobjpriv->ppcidev;\n\tint i, rx_queue_idx;\n\n\n\t/* rx_queue_idx 0:RX_MPDU_QUEUE */\n\t/* rx_queue_idx 1:RX_CMD_QUEUE */\n\tfor (rx_queue_idx = 0; rx_queue_idx < 1; rx_queue_idx++) {\n\t\tfor (i = 0; i < r_priv->rxringcount; i++) {\n\t\t\tstruct sk_buff *skb;\n\n\t\t\tskb = r_priv->rx_ring[rx_queue_idx].rx_buf[i];\n\n\t\t\tif (!skb)\n\t\t\t\tcontinue;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\t\t\tdma_unmap_single(&pdev->dev,\n\t\t\t\t\t *((dma_addr_t *) skb->cb),\n\t\t\t\t\t r_priv->rxbuffersize,\n\t\t\t\t\t DMA_FROM_DEVICE);\n#else\n\t\t\tpci_unmap_single(pdev,\n\t\t\t\t\t *((dma_addr_t *) skb->cb),\n\t\t\t\t\t r_priv->rxbuffersize,\n\t\t\t\t\t PCI_DMA_FROMDEVICE);\n#endif\n\t\t\tkfree_skb(skb);\n\t\t}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\t\tdma_free_coherent(&pdev->dev,\n#else\n\t\tpci_free_consistent(pdev,\n#endif\n\t\t\t    sizeof(*r_priv->rx_ring[rx_queue_idx].buf_desc) *\n\t\t\t\t    r_priv->rxringcount,\n\t\t\t\t    r_priv->rx_ring[rx_queue_idx].buf_desc,\n\t\t\t\t    r_priv->rx_ring[rx_queue_idx].dma);\n\t\tr_priv->rx_ring[rx_queue_idx].buf_desc = NULL;\n\t}\n\n}\n"
  },
  {
    "path": "hal/rtl8822c/pci/rtl8822ce_xmit.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTL8822CE_XMIT_C_\n\n#include <drv_types.h>\t\t/* PADAPTER, rtw_xmit.h and etc. */\n#include <hal_data.h>\t\t/* HAL_DATA_TYPE */\n#include \"../halmac/halmac_api.h\"\n#include \"../rtl8822c.h\"\n#include \"rtl8822ce.h\"\n\n/* Debug Buffer Descriptor Ring */\n/*#define BUF_DESC_DEBUG*/\n#ifdef BUF_DESC_DEBUG\n#define buf_desc_debug(...) do {\\\n\t\tRTW_INFO(\"BUF_DESC:\" __VA_ARGS__);\\\n\t} while (0)\n#else\n#define buf_desc_debug(...)  do {} while (0)\n#endif\n\nstatic void rtl8822ce_xmit_tasklet(void *priv)\n{\n\t_irqL irqL;\n\t_adapter *padapter = (_adapter *)priv;\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\n\t/* try to deal with the pending packets */\n\trtl8822ce_xmitframe_resume(padapter);\n\n}\n\ns32 rtl8822ce_init_xmit_priv(_adapter *padapter)\n{\n\ts32 ret = _SUCCESS;\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\n\t_rtw_spinlock_init(&pdvobjpriv->irq_th_lock);\n\n#ifdef PLATFORM_LINUX\n\ttasklet_init(&pxmitpriv->xmit_tasklet,\n\t\t     (void(*)(unsigned long))rtl8822ce_xmit_tasklet,\n\t\t     (unsigned long)padapter);\n#endif\n\trtl8822c_init_xmit_priv(padapter);\n\n\treturn ret;\n}\n\nvoid rtl8822ce_free_xmit_priv(_adapter *padapter)\n{\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\n\t_rtw_spinlock_free(&pdvobjpriv->irq_th_lock);\n}\n\nstatic s32 rtl8822ce_enqueue_xmitbuf(struct rtw_tx_ring\t*ring,\n\t\t\t\t     struct xmit_buf *pxmitbuf)\n{\n\t_irqL irqL;\n\t_queue *ppending_queue = &ring->queue;\n\n\n\tif (pxmitbuf == NULL)\n\t\treturn _FAIL;\n\n\trtw_list_delete(&pxmitbuf->list);\n\trtw_list_insert_tail(&(pxmitbuf->list), get_list_head(ppending_queue));\n\tring->qlen++;\n\n\n\treturn _SUCCESS;\n}\n\nstruct xmit_buf *rtl8822ce_dequeue_xmitbuf(struct rtw_tx_ring\t*ring)\n{\n\t_irqL irqL;\n\t_list *plist, *phead;\n\tstruct xmit_buf *pxmitbuf =  NULL;\n\t_queue *ppending_queue = &ring->queue;\n\n\n\tif (_rtw_queue_empty(ppending_queue) == _TRUE)\n\t\tpxmitbuf = NULL;\n\telse {\n\n\t\tphead = get_list_head(ppending_queue);\n\t\tplist = get_next(phead);\n\t\tpxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);\n\t\trtw_list_delete(&(pxmitbuf->list));\n\t\tring->qlen--;\n\t}\n\n\n\treturn pxmitbuf;\n}\n\nstatic u8 *get_txbd(_adapter *padapter, u8 q_idx)\n{\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tstruct rtw_tx_ring *ring;\n\tu8 *ptxbd = NULL;\n\tint idx = 0;\n\n\tring = &pxmitpriv->tx_ring[q_idx];\n\n\t/* DO NOT use last entry. */\n\t/* (len -1) to avoid wrap around overlap problem in cycler queue. */\n\tif (ring->qlen == (ring->entries - 1)) {\n\t\tRTW_INFO(\"No more TX desc@%d, ring->idx = %d,idx = %d\\n\",\n\t\t\t q_idx, ring->idx, idx);\n\t\treturn NULL;\n\t}\n\n\tif (q_idx == BCN_QUEUE_INX)\n\t\tidx = 0;\n\telse\n\t\tidx = (ring->idx + ring->qlen) % ring->entries;\n\n\tptxbd = (u8 *)&ring->buf_desc[idx];\n\n\treturn ptxbd;\n}\n\n/*\n * Get txbd reg addr according to q_sel\n */\nu16 get_txbd_rw_reg(u16 q_idx)\n{\n\tu16 txbd_reg_addr = REG_BEQ_TXBD_IDX;\n\n\tswitch (q_idx) {\n\n\tcase BK_QUEUE_INX:\n\t\ttxbd_reg_addr = REG_BKQ_TXBD_IDX;\n\t\tbreak;\n\n\tcase BE_QUEUE_INX:\n\t\ttxbd_reg_addr = REG_BEQ_TXBD_IDX;\n\t\tbreak;\n\n\tcase VI_QUEUE_INX:\n\t\ttxbd_reg_addr = REG_VIQ_TXBD_IDX;\n\t\tbreak;\n\n\tcase VO_QUEUE_INX:\n\t\ttxbd_reg_addr = REG_VOQ_TXBD_IDX;\n\t\tbreak;\n\n\tcase BCN_QUEUE_INX:\n\t\ttxbd_reg_addr = REG_BEQ_TXBD_IDX;\t/* need check */\n\t\tbreak;\n\n\tcase TXCMD_QUEUE_INX:\n\t\ttxbd_reg_addr = REG_H2CQ_TXBD_IDX;\n\t\tbreak;\n\n\tcase MGT_QUEUE_INX:\n\t\ttxbd_reg_addr = REG_MGQ_TXBD_IDX;\n\t\tbreak;\n\n\tcase HIGH_QUEUE_INX:\n\t\ttxbd_reg_addr = REG_HI0Q_TXBD_IDX;   /* need check */\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn txbd_reg_addr;\n}\n\nstruct xmit_frame *__rtw_alloc_cmdxmitframe_8822ce(struct xmit_priv *pxmitpriv,\n\t\tenum cmdbuf_type buf_type)\n{\n\t_adapter *padapter;\n\tu16\tqueue_idx = BCN_QUEUE_INX;\n\tu8 *ptxdesc = NULL;\n\n\tpadapter = GET_PRIMARY_ADAPTER(pxmitpriv->adapter);\n\n\tptxdesc = get_txbd(padapter, BCN_QUEUE_INX);\n\n\t/* set OWN bit in Beacon tx descriptor */\n#if 1 /* vincent TODO */\n\tif (ptxdesc != NULL)\n\t\tSET_TX_BD_OWN(ptxdesc, 0);\n\telse\n\t\treturn NULL;\n#endif\n\n\treturn __rtw_alloc_cmdxmitframe(pxmitpriv, CMDBUF_BEACON);\n}\n\n/*\n * Update Read/Write pointer\n *\tRead pointer is h/w descriptor index\n *\tWrite pointer is host desciptor index:\n *\tFor tx side, if own bit is set in packet index n,\n *\thost pointer (write pointer) point to index n + 1.)\n */\nvoid fill_txbd_own(_adapter *padapter, u8 *txbd, u16 queue_idx,\n\tstruct rtw_tx_ring *ptxring)\n{\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tstruct rtw_tx_ring *ring;\n\tu16 host_wp = 0;\n\n\tif (queue_idx == BCN_QUEUE_INX) {\n\n\t\tSET_TX_BD_OWN(txbd, 1);\n\n\t\t/* kick start */\n\t\trtw_write8(padapter, REG_RX_RXBD_NUM + 1,\n\t\trtw_read8(padapter, REG_RX_RXBD_NUM + 1) | BIT(4));\n\n\t\treturn;\n\t}\n\n\t/*\n\t * update h/w index\n\t * for tx side, if own bit is set in packet index n,\n\t * host pointer (write pointer) point to index n + 1.\n\t */\n\n        /* for current tx packet, enqueue has been ring->qlen++ before.\n         * so, host_wp = ring->idx + ring->qlen.\n         */\n        host_wp = (ptxring->idx + ptxring->qlen) % ptxring->entries;\n        rtw_write16(padapter, get_txbd_rw_reg(queue_idx), host_wp);\n}\n/*\nstatic u16 ffaddr2dma(u32 addr)\n{\n\tu16\tdma_ctrl;\n\n\tswitch (addr) {\n\tcase VO_QUEUE_INX:\n\t\tdma_ctrl = BIT3;\n\t\tbreak;\n\tcase VI_QUEUE_INX:\n\t\tdma_ctrl = BIT2;\n\t\tbreak;\n\tcase BE_QUEUE_INX:\n\t\tdma_ctrl = BIT1;\n\t\tbreak;\n\tcase BK_QUEUE_INX:\n\t\tdma_ctrl = BIT0;\n\t\tbreak;\n\tcase BCN_QUEUE_INX:\n\t\tdma_ctrl = BIT4;\n\t\tbreak;\n\tcase MGT_QUEUE_INX:\n\t\tdma_ctrl = BIT6;\n\t\tbreak;\n\tcase HIGH_QUEUE_INX:\n\t\tdma_ctrl = BIT7;\n\t\tbreak;\n\tdefault:\n\t\tdma_ctrl = 0;\n\t\tbreak;\n\t}\n\n\treturn dma_ctrl;\n}\n*/\n\n/*\n * Fill tx buffer desciptor. Map each buffer address in tx buffer descriptor\n * segment. Designed for tx buffer descriptor architecture\n * Input *pmem: pointer to the Tx Buffer Descriptor\n */\nstatic void rtl8822ce_update_txbd(struct xmit_frame *pxmitframe,\n\t\t\t\t  u8 *txbd, s32 sz)\n{\n\t_adapter *padapter = pxmitframe->padapter;\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\tdma_addr_t mapping;\n\tu32 i = 0;\n\tu16 seg_num =\n\t\t((TX_BUFFER_SEG_NUM == 0) ? 2 : ((TX_BUFFER_SEG_NUM == 1) ? 4 : 8));\n\tu16 tx_page_size_reg = 1;\n\tu16 page_size_length = 0;\n\n\t/* map TX DESC buf_addr (including TX DESC + tx data) */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\tmapping = dma_map_single(&pdvobjpriv->ppcidev->dev, pxmitframe->buf_addr ,\n\t\t\t\t sz + TX_WIFI_INFO_SIZE, DMA_TO_DEVICE);\n#else\n\tmapping = pci_map_single(pdvobjpriv->ppcidev, pxmitframe->buf_addr ,\n\t\t\t\t sz + TX_WIFI_INFO_SIZE, PCI_DMA_TODEVICE);\n#endif\n\n\t/* Calculate page size.\n\t * Total buffer length including TX_WIFI_INFO and PacketLen */\n\tif (tx_page_size_reg > 0) {\n\t\tpage_size_length = (sz + TX_WIFI_INFO_SIZE) /\n\t\t\t\t   (tx_page_size_reg * 128);\n\t\tif (((sz + TX_WIFI_INFO_SIZE) % (tx_page_size_reg * 128)) > 0)\n\t\t\tpage_size_length++;\n\t}\n\n#if 1\n\t/*\n\t * Reset all tx buffer desciprtor content\n\t * -- Reset first element\n\t */\n\tSET_TX_BD_TX_BUFF_SIZE0(txbd, 0);\n\tSET_TX_BD_PSB(txbd, 0);\n\tSET_TX_BD_OWN(txbd, 0);\n\n\t/* -- Reset second and other element */\n\tfor (i = 1 ; i < seg_num ; i++) {\n\t\tSET_TXBUFFER_DESC_LEN_WITH_OFFSET(txbd, i, 0);\n\t\tSET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(txbd, i, 0);\n\t\tSET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(txbd, i, 0);\n\t}\n\n\t/*\n\t * Fill buffer length of the first buffer,\n\t * For 8822ce, it is required that TX_WIFI_INFO is put in first segment,\n\t * and the size of the first segment cannot be larger than\n\t * TX_WIFI_INFO_SIZE.\n\t */\n\tSET_TX_BD_TX_BUFF_SIZE0(txbd, TX_WIFI_INFO_SIZE);\n\tSET_TX_BD_PSB(txbd, page_size_length);\n\t/* starting addr of TXDESC */\n\tSET_TX_BD_PHYSICAL_ADDR0_LOW(txbd, mapping);\n\n\t/*\n\t * It is assumed that in linux implementation, packet is coalesced\n\t * in only one buffer. Extension mode is not supported here\n\t */\n\tSET_TXBUFFER_DESC_LEN_WITH_OFFSET(txbd, 1, sz);\n\t/* don't using extendsion mode. */\n\tSET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(txbd, 1, 0);\n\tSET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(txbd, 1,\n\t\t\t\t      mapping + TX_WIFI_INFO_SIZE); /* pkt */\n#endif\n\n\t/*buf_desc_debug(\"TX:%s, txbd = 0x%p\\n\", __FUNCTION__, txbd);*/\n\tbuf_desc_debug(\"%s, txbd = 0x%08x\\n\", __func__, txbd);\n\tbuf_desc_debug(\"TXBD:, 00h(0x%08x)\\n\", *((u32 *)(txbd)));\n\tbuf_desc_debug(\"TXBD:, 04h(0x%08x)\\n\", *((u32 *)(txbd + 4)));\n\tbuf_desc_debug(\"TXBD:, 08h(0x%08x)\\n\", *((u32 *)(txbd + 8)));\n\tbuf_desc_debug(\"TXBD:, 12h(0x%08x)\\n\", *((u32 *)(txbd + 12)));\n\n}\n\nstatic s32 update_txdesc(struct xmit_frame *pxmitframe, s32 sz)\n{\n\tuint qsel;\n\tu8 data_rate, pwr_status;\n\t_adapter *padapter = pxmitframe->padapter;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct pkt_attrib *pattrib = &pxmitframe->attrib;\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8 *ptxdesc;\n\tsint bmcst = IS_MCAST(pattrib->ra);\n\tu16 SWDefineContent = 0x0;\n\tu8 DriverFixedRate = 0x0;\n\tu8 hw_port = rtw_hal_get_port(padapter);\n\n\tptxdesc = pxmitframe->buf_addr;\n\t_rtw_memset(ptxdesc, 0, TXDESC_SIZE);\n\n\t/* offset 0 */\n\t/*SET_TX_DESC_FIRST_SEG_8812(ptxdesc, 1);*/\n\tSET_TX_DESC_LS_8822C(ptxdesc, 1);\n\t/*SET_TX_DESC_OWN_8812(ptxdesc, 1);*/\n\n\tSET_TX_DESC_TXPKTSIZE_8822C(ptxdesc, sz);\n\n\t/* TX_DESC is not included in the data,\n\t * driver needs to fill in the TX_DESC with qsel=h2c\n\t * Offset in TX_DESC should be set to 0.\n\t */\n#ifdef CONFIG_TX_EARLY_MODE\n\tSET_TX_DESC_PKT_OFFSET_8812(ptxdesc, 1);\n\tif (pattrib->qsel == HALMAC_TXDESC_QSEL_H2C_CMD)\n\t\tSET_TX_DESC_OFFSET_8822C(ptxdesc, 0);\n\telse\n\t\tSET_TX_DESC_OFFSET_8822C(ptxdesc,\n\t\t\tTXDESC_SIZE + EARLY_MODE_INFO_SIZE);\n#else\n\tif (pattrib->qsel == HALMAC_TXDESC_QSEL_H2C_CMD)\n\t\tSET_TX_DESC_OFFSET_8822C(ptxdesc, 0);\n\telse\n\t\tSET_TX_DESC_OFFSET_8822C(ptxdesc, TXDESC_SIZE);\n#endif\n\n\tif (bmcst)\n\t\tSET_TX_DESC_BMC_8822C(ptxdesc, 1);\n\n\tSET_TX_DESC_MACID_8822C(ptxdesc, pattrib->mac_id);\n\tSET_TX_DESC_RATE_ID_8822C(ptxdesc, pattrib->raid);\n\n\tSET_TX_DESC_QSEL_8822C(ptxdesc,  pattrib->qsel);\n\n\tif (!pattrib->qos_en) {\n\t\t/* Hw set sequence number */\n\t\tSET_TX_DESC_DISQSELSEQ_8822C(ptxdesc, 1);\n\t\tSET_TX_DESC_EN_HWSEQ_8822C(ptxdesc, 1);\n\t\tSET_TX_DESC_HW_SSN_SEL_8822C(ptxdesc, pattrib->hw_ssn_sel);\n\t\tSET_TX_DESC_EN_HWEXSEQ_8822C(ptxdesc, 0);\n\t} else\n\t\tSET_TX_DESC_SW_SEQ_8822C(ptxdesc, pattrib->seqnum);\n\n\tif ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) {\n\t\trtl8822c_fill_txdesc_sectype(pattrib, ptxdesc);\n\t\trtl8822c_fill_txdesc_vcs(padapter, pattrib, ptxdesc);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (bmcst)\n\t\t\trtl8822c_fill_txdesc_force_bmc_camid(pattrib, ptxdesc);\n#endif\n\n\t\tif ((pattrib->ether_type != 0x888e) &&\n\t\t    (pattrib->ether_type != 0x0806) &&\n\t\t    (pattrib->ether_type != 0x88b4) &&\n\t\t    (pattrib->dhcp_pkt != 1)\n#ifdef CONFIG_AUTO_AP_MODE\n\t\t    && (pattrib->pctrl != _TRUE)\n#endif\n\t\t   ) {\n\t\t\t/* Non EAP & ARP & DHCP type data packet */\n\n\t\t\tif (pattrib->ampdu_en == _TRUE) {\n\t\t\t\t/* 8822c does NOT support AGG broadcast pkt */\n\t\t\t\tif (!bmcst)\n\t\t\t\t\tSET_TX_DESC_AGG_EN_8822C(ptxdesc, 1);\n\n\t\t\t\tSET_TX_DESC_MAX_AGG_NUM_8822C(ptxdesc, 0x1f);\n\t\t\t\t/* Set A-MPDU aggregation. */\n\t\t\t\tSET_TX_DESC_AMPDU_DENSITY_8822C(ptxdesc,\n\t\t\t\t\t\t\tpattrib->ampdu_spacing);\n\t\t\t} else\n\t\t\t\tSET_TX_DESC_BK_8822C(ptxdesc, 1);\n\n\t\t\trtl8822c_fill_txdesc_phy(padapter, pattrib, ptxdesc);\n\n\t\t\t/* DATA  Rate FB LMT */\n\t\t\t/* compatibility for MCC consideration, use pmlmeext->cur_channel */\n\t\t\tif (!bmcst) {\n\t\t\t\tif (pmlmeext->cur_channel > 14)\n\t\t\t\t\t/* for 5G. OFMD 6M */\n\t\t\t\t\tSET_TX_DESC_DATA_RTY_LOWEST_RATE_8822C(\n\t\t\t\t\t\tptxdesc, 4);\n\t\t\t\telse\n\t\t\t\t\t/* for 2.4G. CCK 1M */\n\t\t\t\t\tSET_TX_DESC_DATA_RTY_LOWEST_RATE_8822C(\n\t\t\t\t\t\tptxdesc, 0);\n\t\t\t}\n\n\t\t\tif (pHalData->fw_ractrl == _FALSE) {\n\t\t\t\tSET_TX_DESC_USE_RATE_8822C(ptxdesc, 1);\n\t\t\t\tDriverFixedRate = 0x01;\n\n\t\t\t\tif (pHalData->INIDATA_RATE[pattrib->mac_id] &\n\t\t\t\t    BIT(7))\n\t\t\t\t\tSET_TX_DESC_DATA_SHORT_8822C(\n\t\t\t\t\t\tptxdesc, 1);\n\n\t\t\t\tSET_TX_DESC_DATARATE_8822C(ptxdesc,\n\t\t\t\t\tpHalData->INIDATA_RATE[pattrib->mac_id]\n\t\t\t\t\t\t\t   & 0x7F);\n\t\t\t}\n\t\t\tif (bmcst) {\n\t\t\t\tDriverFixedRate = 0x01;\n\t\t\t\trtl8822c_fill_txdesc_bmc_tx_rate(pattrib, ptxdesc);\n\t\t\t}\n\t\t\tif (padapter->fix_rate != 0xFF) {\n\t\t\t\t/* modify data rate by iwpriv */\n\t\t\t\tSET_TX_DESC_USE_RATE_8822C(ptxdesc, 1);\n\n\t\t\t\tDriverFixedRate = 0x01;\n\t\t\t\tif (padapter->fix_rate & BIT(7))\n\t\t\t\t\tSET_TX_DESC_DATA_SHORT_8822C(\n\t\t\t\t\t\tptxdesc, 1);\n\n\t\t\t\tSET_TX_DESC_DATARATE_8822C(ptxdesc,\n\t\t\t\t\t\t   (padapter->fix_rate & 0x7F));\n\t\t\t\tif (!padapter->data_fb)\n\t\t\t\t\tSET_TX_DESC_DISDATAFB_8822C(ptxdesc, 1);\n\t\t\t}\n\n\t\t\tif (pattrib->ldpc)\n\t\t\t\tSET_TX_DESC_DATA_LDPC_8822C(ptxdesc, 1);\n\t\t\tif (pattrib->stbc)\n\t\t\t\tSET_TX_DESC_DATA_STBC_8822C(ptxdesc, 1);\n\n#ifdef CONFIG_WMMPS_STA\n\t\t\tif (pattrib->trigger_frame)\n\t\t\t\tSET_TX_DESC_TRI_FRAME_8822C (ptxdesc, 1);\n#endif /* CONFIG_WMMPS_STA */\n\n\t\t} else {\n\t\t\t/*\n\t\t\t * EAP data packet and ARP packet and DHCP.\n\t\t\t * Use the 1M data rate to send the EAP/ARP packet.\n\t\t\t * This will maybe make the handshake smooth.\n\t\t\t */\n\n\t\t\tSET_TX_DESC_USE_RATE_8822C(ptxdesc, 1);\n\t\t\tDriverFixedRate = 0x01;\n\t\t\tSET_TX_DESC_BK_8822C(ptxdesc, 1);\n\n\t\t\t/* HW will ignore this setting if the transmission rate\n\t\t\t * is legacy OFDM. */\n\t\t\tif (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)\n\t\t\t\tSET_TX_DESC_DATA_SHORT_8822C(ptxdesc, 1);\n#ifdef CONFIG_IP_R_MONITOR\n\t\t\tif((pattrib->ether_type == ETH_P_ARP) &&\n\t\t\t\t(IsSupportedTxOFDM(padapter->registrypriv.wireless_mode))) {\n\t\t\t\tSET_TX_DESC_DATARATE_8822C(ptxdesc,\n\t\t\t\t\t   MRateToHwRate(IEEE80211_OFDM_RATE_6MB));\n\t\t\t\t#ifdef DBG_IP_R_MONITOR\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT \": SP Packet(0x%04X) rate=0x%x SeqNum = %d\\n\",\n\t\t\t\t\tFUNC_ADPT_ARG(padapter), pattrib->ether_type, MRateToHwRate(pmlmeext->tx_rate), pattrib->seqnum);\n\t\t\t\t#endif/*DBG_IP_R_MONITOR*/\n\t\t\t } else\n#endif/*CONFIG_IP_R_MONITOR*/\n\t\t\tSET_TX_DESC_DATARATE_8822C(ptxdesc,\n\t\t\t\t\t   MRateToHwRate(pmlmeext->tx_rate));\n\t\t}\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_XMIT_ACK\n\t\t/* CCX-TXRPT ack for xmit mgmt frames. */\n\t\tif (pxmitframe->ack_report) {\n\t\t\tSET_TX_DESC_SPE_RPT_8822C(ptxdesc, 1);\n#ifdef DBG_CCX\n\t\t\tRTW_INFO(\"%s set tx report\\n\", __func__);\n#endif\n\t\t}\n#endif /* CONFIG_XMIT_ACK */\n#endif\n\t} else if ((pxmitframe->frame_tag & 0x0f) == MGNT_FRAMETAG) {\n\t\tSET_TX_DESC_MBSSID_8822C(ptxdesc, pattrib->mbssid & 0xF);\n\t\tSET_TX_DESC_USE_RATE_8822C(ptxdesc, 1);\n\t\tDriverFixedRate = 0x01;\n\n\t\tSET_TX_DESC_DATARATE_8822C(ptxdesc, MRateToHwRate(pattrib->rate));\n\n\t\tSET_TX_DESC_RTY_LMT_EN_8822C(ptxdesc, 1);\n\t\tif (pattrib->retry_ctrl == _TRUE)\n\t\t\tSET_TX_DESC_RTS_DATA_RTY_LMT_8822C(ptxdesc, 6);\n\t\telse\n\t\t\tSET_TX_DESC_RTS_DATA_RTY_LMT_8822C(ptxdesc, 12);\n\n\t\trtl8822c_fill_txdesc_mgnt_bf(pxmitframe, ptxdesc);\n\n#ifdef CONFIG_XMIT_ACK\n\t\t/* CCX-TXRPT ack for xmit mgmt frames. */\n\t\tif (pxmitframe->ack_report) {\n\t\t\tSET_TX_DESC_SPE_RPT_8822C(ptxdesc, 1);\n#ifdef DBG_CCX\n\t\t\tRTW_INFO(\"%s set tx report\\n\", __func__);\n#endif\n\t\t}\n#endif /* CONFIG_XMIT_ACK */\n\t} else if ((pxmitframe->frame_tag & 0x0f) == TXAGG_FRAMETAG)\n\t\tRTW_INFO(\"pxmitframe->frame_tag == TXAGG_FRAMETAG\\n\");\n#ifdef CONFIG_MP_INCLUDED\n\telse if (((pxmitframe->frame_tag & 0x0f) == MP_FRAMETAG) &&\n\t\t (padapter->registrypriv.mp_mode == 1))\n\t\tfill_txdesc_for_mp(padapter, ptxdesc);\n#endif\n\telse {\n\t\tRTW_INFO(\"pxmitframe->frame_tag = %d\\n\",\n\t\t\t pxmitframe->frame_tag);\n\n\t\tSET_TX_DESC_USE_RATE_8822C(ptxdesc, 1);\n\t\tDriverFixedRate = 0x01;\n\t\tSET_TX_DESC_DATARATE_8822C(ptxdesc,\n\t\t\t\t\t   MRateToHwRate(pmlmeext->tx_rate));\n\t}\n\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\tif (!bmcst && pattrib->psta)\n\t\todm_set_tx_ant_by_tx_info(adapter_to_phydm(padapter), ptxdesc, pattrib->psta->cmn.mac_id);\n#endif\n\n\trtl8822c_fill_txdesc_bf(pxmitframe, ptxdesc);\n\n\t/*SET_TX_DESC_TX_BUFFER_SIZE_8812(ptxdesc, sz);*/\n\n\tif (DriverFixedRate)\n\t\tSWDefineContent |= 0x01;\n\n\tSET_TX_DESC_SW_DEFINE_8822C(ptxdesc, SWDefineContent);\n\n\tSET_TX_DESC_PORT_ID_8822C(ptxdesc, hw_port);\n\tSET_TX_DESC_MULTIPLE_PORT_8822C(ptxdesc, hw_port);\n\n\trtl8822c_cal_txdesc_chksum(padapter, ptxdesc);\n\trtl8822c_dbg_dump_tx_desc(padapter, pxmitframe->frame_tag, ptxdesc);\n\treturn 0;\n}\n\ns32 rtl8822ce_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe)\n{\n\ts32 ret = _SUCCESS;\n\ts32 inner_ret = _SUCCESS;\n\t_irqL irqL;\n\tint t, sz, w_sz, pull = 0;\n\tu32 ff_hwaddr;\n\tstruct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf;\n\tstruct pkt_attrib *pattrib = &pxmitframe->attrib;\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tu8 *txbd;\n\tstruct rtw_tx_ring *ptx_ring;\n\n\n#ifdef CONFIG_80211N_HT\n\tif ((pxmitframe->frame_tag == DATA_FRAMETAG) &&\n\t    (pxmitframe->attrib.ether_type != 0x0806) &&\n\t    (pxmitframe->attrib.ether_type != 0x888e) &&\n\t    (pxmitframe->attrib.dhcp_pkt != 1))\n\t\trtw_issue_addbareq_cmd(padapter, pxmitframe, _FALSE);\n#endif /* CONFIG_80211N_HT */\n\tfor (t = 0; t < pattrib->nr_frags; t++) {\n\n\t\tif (inner_ret != _SUCCESS && ret == _SUCCESS)\n\t\t\tret = _FAIL;\n\n\t\tif (t != (pattrib->nr_frags - 1)) {\n\n\t\t\tsz = pxmitpriv->frag_len - 4;\n\n\t\t\tif (!psecuritypriv->sw_encrypt)\n\t\t\t\tsz -= pattrib->icv_len;\n\t\t} else {\n\t\t\t/* no frag */\n\t\t\tsz = pattrib->last_txcmdsz;\n\t\t}\n\n\t\tff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);\n\n\t\t_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);\n\t\ttxbd = get_txbd(GET_PRIMARY_ADAPTER(padapter), ff_hwaddr);\n\n\t\tptx_ring = &(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.tx_ring[ff_hwaddr]);\n\n#ifndef CONFIG_BCN_ICF\n\t\tif (BCN_QUEUE_INX == ff_hwaddr)\n\t\t\tpadapter->xmitpriv.beaconDMAing = _TRUE;\n#endif\n\n\t\tif (txbd == NULL) {\n\t\t\t_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);\n\t\t\trtw_sctx_done_err(&pxmitbuf->sctx,\n\t\t\t\t\t  RTW_SCTX_DONE_TX_DESC_NA);\n\t\t\trtw_free_xmitbuf(pxmitpriv, pxmitbuf);\n\t\t\tRTW_INFO(\"##### Tx desc unavailable !#####\\n\");\n\t\t\tbreak;\n\t\t}\n\n\t\tif (pattrib->qsel != HALMAC_TXDESC_QSEL_H2C_CMD)\n\t\t\tupdate_txdesc(pxmitframe, sz);\n\n\t\t/* rtl8822ce_update_txbd() must be called after update_txdesc().\n\t\t * It rely on rtl8822ce_update_txbd() to map it into non cache\n\t\t * memory */\n\n\t\trtl8822ce_update_txbd(pxmitframe, txbd, sz);\n\n\t\tif (pxmitbuf->buf_tag != XMITBUF_CMD)\n\t\t\trtl8822ce_enqueue_xmitbuf(ptx_ring, pxmitbuf);\n\n\t\tpxmitbuf->len = sz + TX_WIFI_INFO_SIZE;\n\t\tw_sz = sz;\n\n\t\t/* Please comment here */\n\t\twmb();\n\t\tfill_txbd_own(padapter, txbd, ff_hwaddr, ptx_ring);\n\n#ifdef DBG_TXBD_DESC_DUMP\n\t\tif (pxmitpriv->dump_txbd_desc)\n\t\t\trtw_tx_desc_backup(padapter, pxmitframe, TX_WIFI_INFO_SIZE, ff_hwaddr);\n#endif\n\n\n#ifdef CONFIG_PCI_TX_POLLING_V2\n\t\tif (BE_QUEUE_INX == ff_hwaddr) { \n\t\t\t/*while (ptx_ring->qlen > (29*(NR_XMITBUFF>>5))) { *//*90.6%*/\n\t\t\t/*while (ptx_ring->qlen > (14*(NR_XMITBUFF>>4))) { *//*87.5%*/\n\t\t\twhile (ptx_ring->qlen > (6*(NR_XMITBUFF>>3))) { /*75%*/\n\t\t\t/*while (ptx_ring->qlen > (NR_XMITBUFF>>1)) { *//*50%*/\n\t\t\t\trtl8822ce_tx_isr_polling(padapter, BE_QUEUE_INX);\n\t\t\t}\n\t\t}\n#ifndef CONFIG_PCI_TX_POLLING\n\t\telse if (MGT_QUEUE_INX == ff_hwaddr){\n\t\t\twhile (ptx_ring->qlen > 2) {\t/* mini. qlen=2 */\n\t\t\t\trtl8822ce_tx_isr_polling(padapter, MGT_QUEUE_INX); /*mgnt frame use xmit_buf_ext, only 32 buf.*/\n\t\t\t}\n\t\t} else if ((HIGH_QUEUE_INX == ff_hwaddr) ||(BK_QUEUE_INX == ff_hwaddr) ||\n\t\t\t (VI_QUEUE_INX == ff_hwaddr) ||(VO_QUEUE_INX == ff_hwaddr)){\n\t\t\twhile (ptx_ring->qlen > (6*(TX_BD_NUM_8822CE>>3))) { /*75%*/\n\t\t\t/*while (ptx_ring->qlen > (TX_BD_NUM_8822CE>>1)) { *//*50%*/\n\t\t\t\trtl8822ce_tx_isr_polling(padapter, ff_hwaddr);\n\t\t\t}\n\t\t}\n#endif\n#endif\n\n\t\t_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);\n\n\t\tinner_ret = rtw_write_port(padapter, ff_hwaddr, w_sz,\n\t\t\t\t\t   (unsigned char *)pxmitbuf);\n\n\t\trtw_count_tx_stats(padapter, pxmitframe, sz);\n\t}\n\n\trtw_free_xmitframe(pxmitpriv, pxmitframe);\n\n\tif (ret != _SUCCESS)\n\t\trtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN);\n\n\treturn ret;\n}\n\n/*\n * Packet should not be dequeued if there is no available descriptor\n * return: _SUCCESS if there is available descriptor\n */\nstatic u8 check_tx_desc_resource(_adapter *padapter, int prio)\n{\n\tstruct xmit_priv\t*pxmitpriv = &padapter->xmitpriv;\n\tstruct rtw_tx_ring\t*ring;\n\n\tring = &pxmitpriv->tx_ring[prio];\n\n\t/*\n\t * for now we reserve two free descriptor as a safety boundary\n\t * between the tail and the head\n\t */\n\n\tif ((ring->entries - ring->qlen) >= 2)\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\n\nstatic u8 check_nic_enough_desc_all(_adapter *padapter)\n{\n\tu8 status = (check_tx_desc_resource(padapter, VI_QUEUE_INX) &&\n\t\t     check_tx_desc_resource(padapter, VO_QUEUE_INX) &&\n\t\t     check_tx_desc_resource(padapter, BE_QUEUE_INX) &&\n\t\t     check_tx_desc_resource(padapter, BK_QUEUE_INX) &&\n\t\t     check_tx_desc_resource(padapter, MGT_QUEUE_INX) &&\n\t\t     check_tx_desc_resource(padapter, TXCMD_QUEUE_INX) &&\n\t\t     check_tx_desc_resource(padapter, HIGH_QUEUE_INX));\n\treturn status;\n}\n\nstatic u8 check_nic_enough_desc(_adapter *padapter, struct pkt_attrib *pattrib)\n{\n\tu32 prio;\n\tstruct xmit_priv\t*pxmitpriv = &padapter->xmitpriv;\n\tstruct rtw_tx_ring\t*ring;\n\n\tswitch (pattrib->qsel) {\n\tcase 0:\n\tcase 3:\n\t\tprio = BE_QUEUE_INX;\n\t\tbreak;\n\tcase 1:\n\tcase 2:\n\t\tprio = BK_QUEUE_INX;\n\t\tbreak;\n\tcase 4:\n\tcase 5:\n\t\tprio = VI_QUEUE_INX;\n\t\tbreak;\n\tcase 6:\n\tcase 7:\n\t\tprio = VO_QUEUE_INX;\n\t\tbreak;\n\tdefault:\n\t\tprio = BE_QUEUE_INX;\n\t\tbreak;\n\t}\n\n\tring = &pxmitpriv->tx_ring[prio];\n\n\t/*\n\t * for now we reserve two free descriptor as a safety boundary\n\t * between the tail and the head\n\t */\n\tif ((ring->entries - ring->qlen) >= 2)\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\n\n#ifdef CONFIG_XMIT_THREAD_MODE\n/*\n * Description\n *\tTransmit xmitbuf to hardware tx fifo\n *\n * Return\n *\t_SUCCESS\tok\n *\t_FAIL\t\tsomething error\n */\ns32 rtl8822ce_xmit_buf_handler(_adapter *padapter)\n{\n\tPHAL_DATA_TYPE phal;\n\tstruct xmit_priv *pxmitpriv;\n\tstruct xmit_buf *pxmitbuf;\n\tstruct xmit_frame *pxmitframe;\n\ts32 ret;\n\n\tphal = GET_HAL_DATA(padapter);\n\tpxmitpriv = &padapter->xmitpriv;\n\n\tret = _rtw_down_sema(&pxmitpriv->xmit_sema);\n\n\tif (ret == _FAIL) {\n\t\tRTW_ERR(\"%s: down XmitBufSema fail!\\n\", __FUNCTION__);\n\t\treturn _FAIL;\n\t}\n\n\tif (RTW_CANNOT_RUN(padapter)) {\n\t\tRTW_INFO(\"%s: bDriverStopped(%s) bSurpriseRemoved(%s)!\\n\"\n\t\t\t, __func__\n\t\t\t, rtw_is_drv_stopped(padapter)?\"True\":\"False\"\n\t\t\t, rtw_is_surprise_removed(padapter)?\"True\":\"False\");\n\t\treturn _FAIL;\n\t}\n\n\tif (check_pending_xmitbuf(pxmitpriv) == _FALSE)\n\t\treturn _SUCCESS;\n\n#ifdef CONFIG_LPS_LCLK\n\tret = rtw_register_tx_alive(padapter);\n\tif (ret != _SUCCESS) {\n\t\tRTW_INFO(\"%s: wait to leave LPS_LCLK\\n\", __FUNCTION__);\n\t\treturn _SUCCESS;\n\t}\n#endif\n\n\tdo {\n\t\tpxmitbuf = select_and_dequeue_pending_xmitbuf(padapter);\n\n\t\tif (pxmitbuf == NULL)\n\t\t\tbreak;\n\t\tpxmitframe = (struct xmit_frame *)pxmitbuf->priv_data;\n\n\t\tif (check_nic_enough_desc(padapter, &pxmitframe->attrib) == _FALSE) {\n\t\t\tenqueue_pending_xmitbuf_to_head(pxmitpriv, pxmitbuf);\n\t\t\tbreak;\n\t\t}\n\t\trtl8822ce_dump_xframe(padapter, pxmitframe);\n\t} while (1);\n\n\n\treturn _SUCCESS;\n}\n#endif\n\nstatic s32 xmitframe_direct(_adapter *padapter, struct xmit_frame *pxmitframe)\n{\n#ifdef CONFIG_XMIT_THREAD_MODE\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n#endif\n\ts32 res = _SUCCESS;\n\n\tres = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);\n\tif (res == _SUCCESS) {\n\t#ifdef CONFIG_XMIT_THREAD_MODE\n\t\tenqueue_pending_xmitbuf(pxmitpriv, pxmitframe->pxmitbuf);\n\t#else\n\t\trtl8822ce_dump_xframe(padapter, pxmitframe);\n\t#endif\n\t}\n\treturn res;\n}\n\n#ifdef CONFIG_TX_AMSDU\nstatic s32 xmitframe_amsdu_direct(_adapter *padapter, struct xmit_frame *pxmitframe)\n{\n\tstruct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf;\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\ts32 res = _SUCCESS;\n\n\tres = rtw_xmitframe_coalesce_amsdu(padapter, pxmitframe, NULL);\n\n\tif (res == _SUCCESS) {\n\t#ifdef CONFIG_XMIT_THREAD_MODE\n\t\tenqueue_pending_xmitbuf(pxmitpriv, pxmitframe->pxmitbuf);\n\t#else\n\t\tres = rtl8822ce_dump_xframe(padapter, pxmitframe);\n\t#endif\n\t} else {\n\t\trtw_free_xmitbuf(pxmitpriv, pxmitbuf);\n\t\trtw_free_xmitframe(pxmitpriv, pxmitframe);\n\t}\n\treturn res;\n}\n#endif\n\n\nvoid rtl8822ce_xmitframe_resume(_adapter *padapter)\n{\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tstruct xmit_frame *pxmitframe = NULL;\n\tstruct xmit_buf\t*pxmitbuf = NULL;\n\tint res = _SUCCESS, xcnt = 0;\n\n#ifdef CONFIG_TX_AMSDU\n\tstruct mlme_priv *pmlmepriv =  &padapter->mlmepriv;\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\n\tint tx_amsdu = padapter->tx_amsdu;\n\tint tx_amsdu_rate = padapter->tx_amsdu_rate;\n\tint current_tx_rate = pdvobjpriv->traffic_stat.cur_tx_tp;\n\n\tstruct pkt_attrib *pattrib = NULL;\n\n\tstruct xmit_frame *pxmitframe_next = NULL;\n\tstruct xmit_buf *pxmitbuf_next = NULL;\n\tstruct pkt_attrib *pattrib_next = NULL;\n\tint num_frame = 0;\n\n\tu8 amsdu_timeout = 0;\n#endif\n\n\twhile (1) {\n\t\tif (RTW_CANNOT_RUN(padapter)) {\n\t\t\tRTW_INFO(\"%s => bDriverStopped or bSurpriseRemoved\\n\",\n\t\t\t\t __func__);\n\t\t\tbreak;\n\t\t}\n\n\t#ifndef CONFIG_XMIT_THREAD_MODE\n\t\tif (!check_nic_enough_desc_all(padapter))\n\t\t\tbreak;\n\t#endif\n\n\t\tpxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);\n\t\tif (!pxmitbuf)\n\t\t\tbreak;\n\n#ifdef CONFIG_TX_AMSDU\n\t\tif(tx_amsdu == 0)\n\t\t\tgoto dump_pkt;\n\n\t\tif (!check_fwstate(pmlmepriv, WIFI_STATION_STATE))\n\t\t\tgoto dump_pkt;\n\n\t\tpxmitframe = rtw_get_xframe(pxmitpriv, &num_frame);\n\n\t\tif(num_frame == 0 || pxmitframe == NULL || !check_amsdu(pxmitframe))\n\t\t\tgoto dump_pkt;\n\n\t\tpattrib = &pxmitframe->attrib;\n\n\t\tif(tx_amsdu == 1)\n\t\t{\n\t\t\tpxmitframe =  rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits,\n\t\t\t\t\t\tpxmitpriv->hwxmit_entry);\n\t\t\tif (pxmitframe)\n\t\t\t{\n\t\t\t\tpxmitframe->pxmitbuf = pxmitbuf;\n\t\t\t\tpxmitframe->buf_addr = pxmitbuf->pbuf;\n\t\t\t\tpxmitbuf->priv_data = pxmitframe;\n\t\t\t\txmitframe_amsdu_direct(padapter, pxmitframe);\n\t\t\t\tpxmitpriv->amsdu_debug_coalesce_one++;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\trtw_free_xmitbuf(pxmitpriv, pxmitbuf);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\telse if(tx_amsdu == 2 && ((tx_amsdu_rate == 0) || (current_tx_rate > tx_amsdu_rate)))\n\t\t{\n\t\t\tif(num_frame == 1)\n\t\t\t{\n\t\t\t\tamsdu_timeout = rtw_amsdu_get_timer_status(padapter,\n\t\t\t\t\t\t\tpattrib->priority); \n\n\t\t\t\tif(amsdu_timeout == RTW_AMSDU_TIMER_UNSET)\n\t\t\t\t{\n\t\t\t\t\trtw_free_xmitbuf(pxmitpriv, pxmitbuf);\n\t\t\t\t\trtw_amsdu_set_timer_status(padapter,\n\t\t\t\t\t\tpattrib->priority, RTW_AMSDU_TIMER_SETTING);\n\t\t\t\t\trtw_amsdu_set_timer(padapter, pattrib->priority);\n\t\t\t\t\tpxmitpriv->amsdu_debug_set_timer++;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\telse if(amsdu_timeout == RTW_AMSDU_TIMER_SETTING)\n\t\t\t\t{\n\t\t\t\t\trtw_free_xmitbuf(pxmitpriv, pxmitbuf);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\telse if(amsdu_timeout == RTW_AMSDU_TIMER_TIMEOUT)\n\t\t\t\t{\n\t\t\t\t\trtw_amsdu_set_timer_status(padapter,\n\t\t\t\t\t\tpattrib->priority, RTW_AMSDU_TIMER_UNSET);\n\t\t\t\t\tpxmitpriv->amsdu_debug_timeout++;\n\t\t\t\t\tpxmitframe = rtw_dequeue_xframe(pxmitpriv,\n\t\t\t\t\t\tpxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);\n\t\t\t\t\tif (pxmitframe)\n\t\t\t\t\t{\n\t\t\t\t\t\tpxmitframe->pxmitbuf = pxmitbuf;\n\t\t\t\t\t\tpxmitframe->buf_addr = pxmitbuf->pbuf;\n\t\t\t\t\t\tpxmitbuf->priv_data = pxmitframe;\n\t\t\t\t\t\txmitframe_amsdu_direct(padapter, pxmitframe);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\trtw_free_xmitbuf(pxmitpriv, pxmitbuf);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\n\t\t\t\t}\n\t\t\t}\n\t\t\telse/* num_frame > 1*/\n\t\t\t{\n\t\t\t\tpxmitframe = rtw_dequeue_xframe(pxmitpriv,\n\t\t\t\t\tpxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);\n\n\t\t\t\tif(!pxmitframe)\n\t\t\t\t{\n\t\t\t\t\trtw_free_xmitbuf(pxmitpriv, pxmitbuf);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\tpxmitframe->pxmitbuf = pxmitbuf;\n\t\t\t\tpxmitframe->buf_addr = pxmitbuf->pbuf;\n\t\t\t\tpxmitbuf->priv_data = pxmitframe;\n\n\t\t\t\tpxmitframe_next = rtw_get_xframe(pxmitpriv, &num_frame);\n\n\t\t\t\tif(num_frame == 0)\n\t\t\t\t{\n\t\t\t\t\txmitframe_amsdu_direct(padapter, pxmitframe);\n\t\t\t\t\tpxmitpriv->amsdu_debug_coalesce_one++;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\tif(!check_amsdu(pxmitframe_next))\n\t\t\t\t{\n\t\t\t\t\txmitframe_amsdu_direct(padapter, pxmitframe);\n\t\t\t\t\tpxmitpriv->amsdu_debug_coalesce_one++;\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tpxmitbuf_next = rtw_alloc_xmitbuf(pxmitpriv);\n\t\t\t\t\tif (!pxmitbuf_next)\n\t\t\t\t\t{\n\t\t\t\t\t\txmitframe_amsdu_direct(padapter, pxmitframe);\n\t\t\t\t\t\tpxmitpriv->amsdu_debug_coalesce_one++;\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\n\n\t\t\t\t\tpxmitframe_next = rtw_dequeue_xframe(pxmitpriv,\n\t\t\t\t\t\tpxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);\n\t\t\t\t\tif(!pxmitframe_next)\n\t\t\t\t\t{\n\t\t\t\t\t\trtw_free_xmitbuf(pxmitpriv, pxmitbuf_next);\n\t\t\t\t\t\txmitframe_amsdu_direct(padapter, pxmitframe);\n\t\t\t\t\t\tpxmitpriv->amsdu_debug_coalesce_one++;\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\n\n\t\t\t\t\tpxmitframe_next->pxmitbuf = pxmitbuf_next;\n\t\t\t\t\tpxmitframe_next->buf_addr = pxmitbuf_next->pbuf;\n\t\t\t\t\tpxmitbuf_next->priv_data = pxmitframe_next;\n\n\t\t\t\t\trtw_xmitframe_coalesce_amsdu(padapter,\n\t\t\t\t\t\tpxmitframe_next , pxmitframe);\n\t\t\t\t\trtw_free_xmitframe(pxmitpriv, pxmitframe);\n\t\t\t\t\trtw_free_xmitbuf(pxmitpriv, pxmitbuf);\n\n#ifdef CONFIG_XMIT_THREAD_MODE\n\t\t\t\t\tenqueue_pending_xmitbuf(pxmitpriv, pxmitframe_next->pxmitbuf);\n#else\n\t\t\t\t\trtl8822ce_dump_xframe(padapter, pxmitframe_next);\n#endif\n\t\t\t\t\tpxmitpriv->amsdu_debug_coalesce_two++;\n\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t}\n\n\t\t}\ndump_pkt:\n#endif /* CONFIG_TX_AMSDU */\n\n\t\tpxmitframe =  rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits,\n\t\t\t\t\t\t pxmitpriv->hwxmit_entry);\n\n\t\tif (pxmitframe) {\n\t\t\tpxmitframe->pxmitbuf = pxmitbuf;\n\t\t\tpxmitframe->buf_addr = pxmitbuf->pbuf;\n\t\t\tpxmitbuf->priv_data = pxmitframe;\n\n\t\t\tif ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) {\n\t\t\t\tif (pxmitframe->attrib.priority <= 15) {\n\t\t\t\t\t/* TID0~15 */\n\t\t\t\t\tres = rtw_xmitframe_coalesce(padapter,\n\t\t\t\t\t\tpxmitframe->pkt, pxmitframe);\n\t\t\t\t}\n\n\t\t\t\t/* always return ndis_packet after\n\t\t\t\t * rtw_xmitframe_coalesce */\n\t\t\t\trtw_os_xmit_complete(padapter, pxmitframe);\n\t\t\t}\n\n\n\t\t\tif (res == _SUCCESS) {\n\t\t\t#ifdef CONFIG_XMIT_THREAD_MODE\n\t\t\t\tenqueue_pending_xmitbuf(pxmitpriv, pxmitframe->pxmitbuf);\n\t\t\t#else\n\t\t\t\trtl8822ce_dump_xframe(padapter, pxmitframe);\n\t\t\t#endif\n\t\t\t} else {\n\t\t\t\trtw_free_xmitbuf(pxmitpriv, pxmitbuf);\n\t\t\t\trtw_free_xmitframe(pxmitpriv, pxmitframe);\n\t\t\t}\n\n\t\t\txcnt++;\n\t\t} else {\n\t\t\trtw_free_xmitbuf(pxmitpriv, pxmitbuf);\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\n\n/*\n * Return\n *\t_TRUE\tdump packet directly\n *\t_FALSE\tenqueue packet\n */\nstatic s32 pre_xmitframe(_adapter *padapter, struct xmit_frame *pxmitframe)\n{\n\t_irqL irqL;\n\ts32 res;\n\tstruct xmit_buf *pxmitbuf = NULL;\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tstruct pkt_attrib *pattrib = &pxmitframe->attrib;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n#ifdef CONFIG_TX_AMSDU\n\tint tx_amsdu = padapter->tx_amsdu;\n\tu8 amsdu_timeout = 0;\n#endif\n\n\t_enter_critical_bh(&pxmitpriv->lock, &irqL);\n\n\tif (rtw_txframes_sta_ac_pending(padapter, pattrib) > 0)\n\t\tgoto enqueue;\n\n#ifndef CONFIG_XMIT_THREAD_MODE\n\tif (check_nic_enough_desc(padapter, pattrib) == _FALSE)\n\t\tgoto enqueue;\n\n\tif (rtw_xmit_ac_blocked(padapter) == _TRUE)\n\t\tgoto enqueue;\n#endif\n\n\tif (DEV_STA_LG_NUM(padapter->dvobj))\n\t\tgoto enqueue;\n\n#ifdef CONFIG_TX_AMSDU\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) &&\n\t\tcheck_amsdu_tx_support(padapter)) {\n\n\t\tif (IS_AMSDU_AMPDU_VALID(pattrib))\n\t\t\tgoto enqueue;\n\t}\n#endif\n\n\tpxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);\n\tif (pxmitbuf == NULL)\n\t\tgoto enqueue;\n\n\t_exit_critical_bh(&pxmitpriv->lock, &irqL);\n\n\tpxmitframe->pxmitbuf = pxmitbuf;\n\tpxmitframe->buf_addr = pxmitbuf->pbuf;\n\tpxmitbuf->priv_data = pxmitframe;\n\n\tif (xmitframe_direct(padapter, pxmitframe) != _SUCCESS) {\n\t\trtw_free_xmitbuf(pxmitpriv, pxmitbuf);\n\t\trtw_free_xmitframe(pxmitpriv, pxmitframe);\n\t}\n\n\treturn _TRUE;\n\nenqueue:\n\tres = rtw_xmitframe_enqueue(padapter, pxmitframe);\n\n#ifdef CONFIG_TX_AMSDU\n\tif(res == _SUCCESS && tx_amsdu == 2)\n\t{\n\t\tamsdu_timeout = rtw_amsdu_get_timer_status(padapter, pattrib->priority);\n\t\tif(amsdu_timeout == RTW_AMSDU_TIMER_SETTING)\n\t\t{\n\t\t\trtw_amsdu_cancel_timer(padapter, pattrib->priority);\n\t\t\trtw_amsdu_set_timer_status(padapter, pattrib->priority,\n\t\t\t\tRTW_AMSDU_TIMER_UNSET);\n\t\t}\n\t}\n#endif\n\n\t_exit_critical_bh(&pxmitpriv->lock, &irqL);\n\n\tif (res != _SUCCESS) {\n\t\trtw_free_xmitframe(pxmitpriv, pxmitframe);\n\n\t\tpxmitpriv->tx_drop++;\n\t\treturn _TRUE;\n\t}\n\n#ifdef CONFIG_TX_AMSDU\n\ttasklet_hi_schedule(&pxmitpriv->xmit_tasklet);\n#endif\n\treturn _FALSE;\n}\n\ns32 rtl8822ce_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)\n{\n\n#ifdef CONFIG_XMIT_THREAD_MODE\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\tstruct pkt_attrib\t*pattrib = &pmgntframe->attrib;\n\ts32 ret = _SUCCESS;\n\n\t/* For FW download rsvd page and H2C pkt */\n\tif ((pattrib->qsel == QSLT_CMD) || (pattrib->qsel == QSLT_BEACON))\n\t\tret = rtl8822ce_dump_xframe(padapter, pmgntframe);\n\telse\n\t\tenqueue_pending_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);\n\treturn ret;\n\n#else\n\treturn rtl8822ce_dump_xframe(padapter, pmgntframe);\n#endif\n}\n\n/*\n * Return\n *\t_TRUE\tdump packet directly ok\n *\t_FALSE\ttemporary can't transmit packets to hardware\n */\ns32 rtl8822ce_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)\n{\n\treturn pre_xmitframe(padapter, pxmitframe);\n}\n\ns32 rtl8822ce_hal_xmitframe_enqueue(_adapter *padapter,\n\t\t\t\t    struct xmit_frame *pxmitframe)\n{\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\ts32 err;\n\n\terr = rtw_xmitframe_enqueue(padapter, pxmitframe);\n\tif (err != _SUCCESS) {\n\t\trtw_free_xmitframe(pxmitpriv, pxmitframe);\n\t\tpxmitpriv->tx_drop++;\n\t} else {\n#ifdef PLATFORM_LINUX\n\t\tif (check_nic_enough_desc(padapter,\n\t\t\t\t\t  &pxmitframe->attrib) == _TRUE)\n\t\t\ttasklet_hi_schedule(&pxmitpriv->xmit_tasklet);\n#endif\n\t}\n\n\treturn err;\n}\n\nint rtl8822ce_init_txbd_ring(_adapter *padapter, unsigned int q_idx,\n\t\t\t     unsigned int entries)\n{\n\tstruct xmit_priv *t_priv = &padapter->xmitpriv;\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct pci_dev *pdev = pdvobjpriv->ppcidev;\n\tstruct tx_buf_desc *txbd;\n\tu8 *tx_desc;\n\tdma_addr_t dma;\n\tint i;\n\n\n\tRTW_INFO(\"%s entries num:%d\\n\", __func__, entries);\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\ttxbd = dma_alloc_coherent(&pdev->dev, sizeof(*txbd) * entries, &dma, GFP_KERNEL);\n#else\n\ttxbd = pci_alloc_consistent(pdev, sizeof(*txbd) * entries, &dma);\n#endif\n\n\tif (!txbd || (unsigned long)txbd & 0xFF) {\n\t\tRTW_INFO(\"Cannot allocate TXBD (q_idx = %d)\\n\", q_idx);\n\t\treturn _FAIL;\n\t}\n\n\t_rtw_memset(txbd, 0, sizeof(*txbd) * entries);\n\tt_priv->tx_ring[q_idx].buf_desc = txbd;\n\tt_priv->tx_ring[q_idx].dma = dma;\n\tt_priv->tx_ring[q_idx].idx = 0;\n\tt_priv->tx_ring[q_idx].entries = entries;\n\t_rtw_init_queue(&t_priv->tx_ring[q_idx].queue);\n\tt_priv->tx_ring[q_idx].qlen = 0;\n\n\tRTW_INFO(\"%s queue:%d, ring_addr:%p\\n\", __func__, q_idx, txbd);\n\n\n\treturn _SUCCESS;\n}\n\nvoid rtl8822ce_free_txbd_ring(_adapter *padapter, unsigned int prio)\n{\n\tstruct xmit_priv *t_priv = &padapter->xmitpriv;\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct pci_dev *pdev = pdvobjpriv->ppcidev;\n\tstruct rtw_tx_ring *ring = &t_priv->tx_ring[prio];\n\tu8 *txbd;\n\tstruct xmit_buf\t*pxmitbuf;\n\n\n\twhile (ring->qlen) {\n\t\ttxbd = (u8 *)(&ring->buf_desc[ring->idx]);\n\t\tSET_TX_BD_OWN(txbd, 0);\n\n\t\tif (prio != BCN_QUEUE_INX)\n\t\t\tring->idx = (ring->idx + 1) % ring->entries;\n\n\t\tpxmitbuf = rtl8822ce_dequeue_xmitbuf(ring);\n\n\t\tif (pxmitbuf) {\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\t\t\tdma_unmap_single(&pdev->dev,\n\t\t\t\tGET_TX_BD_PHYSICAL_ADDR0_LOW(txbd),\n\t\t\t\tpxmitbuf->len, DMA_TO_DEVICE);\n#else\n\t\t\tpci_unmap_single(pdev,\n\t\t\t\tGET_TX_BD_PHYSICAL_ADDR0_LOW(txbd),\n\t\t\t\tpxmitbuf->len, PCI_DMA_TODEVICE);\n#endif\n\n\t\t\trtw_free_xmitbuf(t_priv, pxmitbuf);\n\n\t\t} else {\n\t\t\tRTW_INFO(\"%s qlen=%d!=0,but have xmitbuf in pendingQ\\n\",\n\t\t\t\t __func__, ring->qlen);\n\t\t\tbreak;\n\t\t}\n\t}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\tdma_free_coherent(&pdev->dev, sizeof(*ring->buf_desc) * ring->entries,\n#else\n\tpci_free_consistent(pdev, sizeof(*ring->buf_desc) * ring->entries,\n#endif\n\t\t\t    ring->buf_desc, ring->dma);\n\tring->buf_desc = NULL;\n\n}\n\n/*\n * Draw a line to show queue status. For debug\n * i: queue index / W:HW index / h:host index / .: enpty entry / *:ready to DMA\n * Example:  R- 3- 4- 8 ..iW***h..... (i=3,W=4,h=8,\n * *** means 3 tx_desc is reaady to dma)\n */\n#ifdef BUF_DESC_DEBUG\nstatic void _draw_queue(PADAPTER Adapter, int prio)\n{\n\tint i;\n\tu8 line[TX_BD_NUM_8822CE + 1];\n\tu16 hw, host;\n\tu32\tindex, tmp_4bytes = 0;\n\n\tstruct xmit_priv\t*t_priv = &Adapter->xmitpriv;\n\tstruct rtw_tx_ring\t*ring = &t_priv->tx_ring[prio];\n\n\ttmp_4bytes = rtw_read32(Adapter, get_txbd_rw_reg(prio));\n\thw   = (u16)((tmp_4bytes >> 16) & 0x7ff);\n\thost = (u16)(tmp_4bytes & 0x7ff);\n\n\tindex = ring->idx;\n\t_rtw_memset(line, '.', TX_BD_NUM_8822CE);\n\n\t/* ready to return to driver */\n\tif (index <= hw) {\n\t\tfor (i = index; i < hw; i++)\n\t\t\tline[i] = ':';\n\t} else { /* wrap */\n\t\tfor (i = index; i < TX_BD_NUM_8822CE; i++)\n\t\t\tline[i] = ':';\n\t\tfor (i = 0; i < hw; i++)\n\t\t\tline[i] = ':';\n\t}\n\n\t/* ready to dma */\n\tif (hw <= host) {\n\t\tfor (i = hw; i < host; i++)\n\t\t\tline[i] = '*';\n\t} else { /* wrap */\n\t\tfor (i = hw; i < TX_BD_NUM_8822CE; i++)\n\t\t\tline[i] = '*';\n\t\tfor (i = 0; i < host; i++)\n\t\t\tline[i] = '*';\n\t}\n\n\tline[index] = 'i'; /* software queue index */\n\tline[host] = 'h';  /* host index */\n\tline[hw] = 'W';\t   /* hardware index */\n\tline[TX_BD_NUM_8822CE] = 0x0;\n\n\t/* Q2:10-20-30: */\n\tbuf_desc_debug(\"Q%d:%02d-%02d-%02d %s\\n\", prio, index, hw, host, line);\n}\n#endif\n\n/*\n * Read pointer is h/w descriptor index\n * Write pointer is host desciptor index: For tx side, if own bit is set in\n * packet index n, host pointer (write pointer) point to index n + 1.\n */\nstatic u32 rtl8822ce_check_txdesc_closed(PADAPTER Adapter, u32 queue_idx,\n\t\tstruct rtw_tx_ring *ring)\n{\n\t/*\n\t * hw_rp_cache is used to reduce REG access.\n\t */\n\tu32\ttmp32;\n\n\t/* bcn queue should not enter this function */\n\tif (queue_idx == BCN_QUEUE_INX)\n\t\treturn _TRUE;\n\n\t/* qlen == 0 --> don't need to process */\n\tif (ring->qlen == 0)\n\t\treturn _FALSE;\n\n\t/* sw_rp == hw_rp_cache --> sync hw_rp */\n\tif (ring->idx == ring->hw_rp_cache) {\n\n\t\ttmp32 = rtw_read32(Adapter, get_txbd_rw_reg(queue_idx));\n\n\t\tring->hw_rp_cache = (tmp32 >> 16) & 0x0FFF;\n\t}\n\n\t/* check if need to handle TXOK */\n\tif (ring->idx == ring->hw_rp_cache)\n\t\treturn _FALSE;\n\n\treturn _TRUE;\n}\n\n#ifdef CONFIG_BCN_ICF\nvoid rtl8822ce_tx_isr(PADAPTER Adapter, int prio)\n{\n\tstruct xmit_priv *t_priv = &Adapter->xmitpriv;\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);\n\tstruct rtw_tx_ring *ring = &t_priv->tx_ring[prio];\n\tstruct xmit_buf\t*pxmitbuf;\n\tu8 *tx_desc;\n\tu16 tmp_4bytes;\n\tu16 desc_idx_hw = 0, desc_idx_host = 0;\n\n#ifdef CONFIG_LPS_LCLK\n\tint index;\n\ts32 enter32k = _SUCCESS;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter);\n#endif\n\n\twhile (ring->qlen) {\n\t\ttx_desc = (u8 *)&ring->buf_desc[ring->idx];\n\n\t\t/*  beacon use cmd buf Never run into here */\n\t\tif (!rtl8822ce_check_txdesc_closed(Adapter, prio, ring))\n\t\t\treturn;\n\n\t\tbuf_desc_debug(\"TX: %s, q_idx = %d, tx_bd = %04x, close [%04x] r_idx [%04x]\\n\",\n\t\t\t       __func__, prio, (u32)tx_desc, ring->idx,\n\t\t\t       (ring->idx + 1) % ring->entries);\n\n\t\tring->idx = (ring->idx + 1) % ring->entries;\n\t\tpxmitbuf = rtl8822ce_dequeue_xmitbuf(ring);\n\n\t\tif (pxmitbuf) {\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\t\t\tdma_unmap_single(&pdvobjpriv->ppcidev->dev,\n\t\t\t\tGET_TX_BD_PHYSICAL_ADDR0_LOW(tx_desc),\n\t\t\t\tpxmitbuf->len, DMA_TO_DEVICE);\n#else\n\t\t\tpci_unmap_single(pdvobjpriv->ppcidev,\n\t\t\t\tGET_TX_BD_PHYSICAL_ADDR0_LOW(tx_desc),\n\t\t\t\tpxmitbuf->len, PCI_DMA_TODEVICE);\n#endif\n\t\t\trtw_sctx_done(&pxmitbuf->sctx);\n\t\t\trtw_free_xmitbuf(&(pxmitbuf->padapter->xmitpriv),\n\t\t\t\t\t pxmitbuf);\n\t\t} else {\n\t\t\tRTW_INFO(\"%s qlen=%d!=0,but have xmitbuf in pendingQ\\n\",\n\t\t\t\t __func__, ring->qlen);\n\t\t\tbreak;\n\t\t}\n\t}\n\n#ifdef CONFIG_LPS_LCLK\n\tfor (index = 0; index < HW_QUEUE_ENTRY; index++) {\n\t\tif (index != BCN_QUEUE_INX) {\n\t\t\tif (_rtw_queue_empty(&(Adapter->xmitpriv.tx_ring[index].queue)) == _FALSE) {\n\t\t\t\tenter32k = _FAIL;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\tif (enter32k)\n\t\t_set_workitem(&(pwrpriv->dma_event));\n#endif\n\n\tif (check_tx_desc_resource(Adapter, prio)\n\t    && rtw_xmit_ac_blocked(Adapter) != _TRUE)\n\t\trtw_mi_xmit_tasklet_schedule(Adapter);\n}\n\n#ifdef CONFIG_PCI_TX_POLLING_V2\nvoid rtl8822ce_tx_isr_polling(PADAPTER Adapter, int prio)\n{\n\tstruct xmit_priv *t_priv = &Adapter->xmitpriv;\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);\n\tstruct rtw_tx_ring *ring = &t_priv->tx_ring[prio];\n\tstruct xmit_buf\t*pxmitbuf;\n\tu8 *tx_desc;\n\tu16 tmp_4bytes;\n\tu16 desc_idx_hw = 0, desc_idx_host = 0;\n\tu32 qlen_ths;\n\n#ifdef CONFIG_LPS_LCLK\n\tint index;\n\ts32 enter32k = _SUCCESS;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter);\n#endif\n\tqlen_ths = ring->qlen >>3; /*10% ~ 6% */\n\t/*qlen_ths = 1;*/\n\n\twhile (ring->qlen >= qlen_ths) {\n\t\ttx_desc = (u8 *)&ring->buf_desc[ring->idx];\n\n\t\t/*  beacon use cmd buf Never run into here */\n\t\tif (!rtl8822ce_check_txdesc_closed(Adapter, prio, ring)){\n\t\t\treturn;\n\t\t}\n\n\t\tbuf_desc_debug(\"TX: %s, q_idx = %d, tx_bd = %04x, close [%04x] r_idx [%04x]\\n\",\n\t\t\t       __func__, prio, (u32)tx_desc, ring->idx,\n\t\t\t       (ring->idx + 1) % ring->entries);\n\n\t\tring->idx = (ring->idx + 1) % ring->entries;\n\t\tpxmitbuf = rtl8822ce_dequeue_xmitbuf(ring);\n\n\t\tif (pxmitbuf) {\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\t\t\tdma_unmap_single(&pdvobjpriv->ppcidev->dev,\n\t\t\t\tGET_TX_BD_PHYSICAL_ADDR0_LOW(tx_desc),\n\t\t\t\tpxmitbuf->len, DMA_TO_DEVICE);\n#else\n\t\t\tpci_unmap_single(pdvobjpriv->ppcidev,\n\t\t\t\tGET_TX_BD_PHYSICAL_ADDR0_LOW(tx_desc),\n\t\t\t\tpxmitbuf->len, PCI_DMA_TODEVICE);\n#endif\n\t\t\trtw_sctx_done(&pxmitbuf->sctx);\n\t\t\trtw_free_xmitbuf(&(pxmitbuf->padapter->xmitpriv),\n\t\t\t\t\t pxmitbuf);\n\n\t\t} else {\n\t\t\tRTW_INFO(\"%s qlen=%d!=0,but have xmitbuf in pendingQ\\n\",\n\t\t\t\t __func__, ring->qlen);\n\t\t\tbreak;\n\t\t}\n\t}\n\n#ifdef CONFIG_LPS_LCLK\n\tfor (index = 0; index < HW_QUEUE_ENTRY; index++) {\n\t\tif (index != BCN_QUEUE_INX) {\n\t\t\tif (_rtw_queue_empty(&(Adapter->xmitpriv.tx_ring[index].queue)) == _FALSE) {\n\t\t\t\tenter32k = _FAIL;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\tif (enter32k)\n\t\t_set_workitem(&(pwrpriv->dma_event));\n#endif\n\n\tif (check_tx_desc_resource(Adapter, prio)\n\t    && rtw_xmit_ac_blocked(Adapter) != _TRUE)\n\t\trtw_mi_xmit_tasklet_schedule(Adapter);\n}\n#endif\n\n#else /* !CONFIG_BCN_ICF */\nvoid rtl8822ce_tx_isr(PADAPTER Adapter, int prio)\n{\n\tstruct xmit_priv *t_priv = &Adapter->xmitpriv;\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);\n\tstruct rtw_tx_ring *ring = &t_priv->tx_ring[prio];\n\tstruct xmit_buf\t*pxmitbuf;\n\tu8 *tx_desc;\n\tu16 tmp_4bytes;\n\tu16 desc_idx_hw = 0, desc_idx_host = 0;\n\n#ifdef CONFIG_LPS_LCLK\n\tint index;\n\ts32 enter32k = _SUCCESS;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter);\n#endif\n\n\n\twhile (ring->qlen) {\n\t\ttx_desc = (u8 *)&ring->buf_desc[ring->idx];\n\n\t\t/*\n\t\t * beacon packet will only use the first descriptor defautly,\n\t\t * check register to see whether h/w has consumed buffer\n\t\t * descriptor\n\t\t */\n\t\tif (prio != BCN_QUEUE_INX) {\n\t\t\tif (!rtl8822ce_check_txdesc_closed(Adapter,\n\t\t\t\t\t\t\t   prio, ring->idx))\n\t\t\t\treturn;\n\n\t\t\tbuf_desc_debug(\"TX: %s, queue_idx = %d, tx_desc = %04x, close desc [%04x] and update ring->idx to [%04x]\\n\",\n\t\t\t\t       __func__, prio, (u32)tx_desc, ring->idx,\n\t\t\t\t       (ring->idx + 1) % ring->entries);\n\t\t\tring->idx = (ring->idx + 1) % ring->entries;\n\t\t}\n\t\t#if 0 /* 8822c change 00[31] to DISQSELSEQ */\n\t\telse if (prio == BCN_QUEUE_INX)\n\t\t\tSET_TX_DESC_OWN_92E(tx_desc, 0);\n\t\t#endif\n\n\t\tpxmitbuf = rtl8822ce_dequeue_xmitbuf(ring);\n\t\tif (pxmitbuf) {\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\t\t\tdma_unmap_single(&pdvobjpriv->ppcidev->dev,\n\t\t\t\t GET_TX_BD_PHYSICAL_ADDR0_LOW(tx_desc),\n\t\t\t\t\t pxmitbuf->len, DMA_TO_DEVICE);\n#else\n\t\t\tpci_unmap_single(pdvobjpriv->ppcidev,\n\t\t\t\t GET_TX_BD_PHYSICAL_ADDR0_LOW(tx_desc),\n\t\t\t\t\t pxmitbuf->len, PCI_DMA_TODEVICE);\n#endif\n\t\t\trtw_sctx_done(&pxmitbuf->sctx);\n\t\t\trtw_free_xmitbuf(&(pxmitbuf->padapter->xmitpriv),\n\t\t\t\t\t pxmitbuf);\n\t\t} else {\n\t\t\tRTW_INFO(\"%s qlen=%d!=0,but have xmitbuf in pendingQ\\n\",\n\t\t\t\t __func__, ring->qlen);\n\t\t}\n\t}\n\n#ifdef CONFIG_LPS_LCLK\n\tfor (index = 0; index < HW_QUEUE_ENTRY; index++) {\n\t\tif (index != BCN_QUEUE_INX) {\n\t\t\tif (_rtw_queue_empty(&(Adapter->xmitpriv.tx_ring[index].queue)) == _FALSE) {\n\t\t\t\tenter32k = _FAIL;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\tif (enter32k)\n\t\t_set_workitem(&(pwrpriv->dma_event));\n#endif\n\n\tif ((prio != BCN_QUEUE_INX) && check_tx_desc_resource(Adapter, prio)\n\t    && rtw_xmit_ac_blocked(Adapter) != _TRUE)\n\t\trtw_mi_xmit_tasklet_schedule(Adapter);\n}\n#endif /* CONFIG_BCN_ICF */\n\n#ifdef CONFIG_HOSTAPD_MLME\nstatic void rtl8812ae_hostap_mgnt_xmit_cb(struct urb *urb)\n{\n#ifdef PLATFORM_LINUX\n\tstruct sk_buff *skb = (struct sk_buff *)urb->context;\n\n\tdev_kfree_skb_any(skb);\n#endif\n}\n\ns32 rtl8822ce_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)\n{\n#ifdef PLATFORM_LINUX\n\tu16 fc;\n\tint rc, len, pipe;\n\tunsigned int bmcst, tid, qsel;\n\tstruct sk_buff *skb, *pxmit_skb;\n\tstruct urb *urb;\n\tunsigned char *pxmitbuf;\n\tstruct tx_desc *ptxdesc;\n\tstruct rtw_ieee80211_hdr *tx_hdr;\n\tstruct hostapd_priv *phostapdpriv = padapter->phostapdpriv;\n\tstruct net_device *pnetdev = padapter->pnetdev;\n\tHAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);\n\tstruct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);\n\n\n\tskb = pkt;\n\tlen = skb->len;\n\ttx_hdr = (struct rtw_ieee80211_hdr *)(skb->data);\n\tfc = le16_to_cpu(tx_hdr->frame_ctl);\n\tbmcst = IS_MCAST(tx_hdr->addr1);\n\n\tif ((fc & RTW_IEEE80211_FCTL_FTYPE) != RTW_IEEE80211_FTYPE_MGMT)\n\t\tgoto _exit;\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))\n\t/* http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html */\n\tpxmit_skb = dev_alloc_skb(len + TXDESC_SIZE);\n#else\n\tpxmit_skb = netdev_alloc_skb(pnetdev, len + TXDESC_SIZE);\n#endif\n\n\tif (!pxmit_skb)\n\t\tgoto _exit;\n\n\tpxmitbuf = pxmit_skb->data;\n\n\turb = usb_alloc_urb(0, GFP_ATOMIC);\n\tif (!urb)\n\t\tgoto _exit;\n\n\t/* ----- fill tx desc ----- */\n\tptxdesc = (struct tx_desc *)pxmitbuf;\n\t_rtw_memset(ptxdesc, 0, sizeof(*ptxdesc));\n\n\t/* offset 0 */\n\tptxdesc->txdw0 |= cpu_to_le32(len & 0x0000ffff);\n\t/* default = 32 bytes for TX Desc */\n\tptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) &\n\t\t\t\t      0x00ff0000);\n\tptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);\n\n\tif (bmcst)\n\t\tptxdesc->txdw0 |= cpu_to_le32(BIT(24));\n\n\t/* offset 4 */\n\tptxdesc->txdw1 |= cpu_to_le32(0x00);/* MAC_ID */\n\n\tptxdesc->txdw1 |= cpu_to_le32((0x12 << QSEL_SHT) & 0x00001f00);\n\n\tptxdesc->txdw1 |= cpu_to_le32((0x06 << 16) & 0x000f0000);/* b mode */\n\n\t/* offset 8 */\n\n\t/* offset 12 */\n\tptxdesc->txdw3 |= cpu_to_le32((le16_to_cpu(tx_hdr->seq_ctl) << 16) &\n\t\t\t\t      0xffff0000);\n\n\t/* offset 16 */\n\tptxdesc->txdw4 |= cpu_to_le32(BIT(8));/* driver uses rate */\n\n\t/* offset 20 */\n\n\trtl8188e_cal_txdesc_chksum(ptxdesc);\n\t/* ----- end of fill tx desc ----- */\n\n\tskb_put(pxmit_skb, len + TXDESC_SIZE);\n\tpxmitbuf = pxmitbuf + TXDESC_SIZE;\n\t_rtw_memcpy(pxmitbuf, skb->data, len);\n\n\t/* ----- prepare urb for submit ----- */\n\n\t/* translate DMA FIFO addr to pipehandle */\n\t/*pipe = ffaddr2pipehdl(pdvobj, MGT_QUEUE_INX);*/\n\tpipe = usb_sndbulkpipe(pdvobj->pusbdev,\n\t\t\t       pHalData->Queue2EPNum[(u8)MGT_QUEUE_INX] & 0x0f);\n\n\tusb_fill_bulk_urb(urb, pdvobj->pusbdev, pipe, pxmit_skb->data,\n\t\t  pxmit_skb->len, rtl8188ee_hostap_mgnt_xmit_cb, pxmit_skb);\n\n\turb->transfer_flags |= URB_ZERO_PACKET;\n\tusb_anchor_urb(urb, &phostapdpriv->anchored);\n\trc = usb_submit_urb(urb, GFP_ATOMIC);\n\tif (rc < 0) {\n\t\tusb_unanchor_urb(urb);\n\t\tkfree_skb(skb);\n\t}\n\tusb_free_urb(urb);\n\n\n_exit:\n\n\tdev_kfree_skb_any(skb);\n#endif\n\treturn 0;\n\n}\n#endif\n"
  },
  {
    "path": "hal/rtl8822c/rtl8822c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8822C_H_\n#define _RTL8822C_H_\n\n#include <drv_types.h>\t\t/* PADAPTER */\n#include <rtw_rf.h>\t\t/* CHANNEL_WIDTH */\n#include <rtw_xmit.h>\t\t/* struct pkt_attrib, struct xmit_frame */\n#include <rtw_recv.h>\t\t/* struct recv_frame */\n#include <hal_intf.h>\t\t/* HAL_DEF_VARIABLE */\n#include \"hal8822c_fw.h\"\t/* FW array */\n\n#define DRIVER_EARLY_INT_TIME_8822C\t0x05\n#define BCN_DMA_ATIME_INT_TIME_8822C\t0x02\n\n/* rtl8822c_ops.c */\nstruct hw_port_reg {\n\tu32 net_type;\t/*reg_offset*/\n\tu8 net_type_shift;\n\tu32 macaddr;\t/*reg_offset*/\n\tu32 bssid;\t/*reg_offset*/\n\tu32 bcn_ctl;\t\t\t/*reg_offset*/\n\tu32 tsf_rst;\t\t\t/*reg_offset*/\n\tu8 tsf_rst_bit;\n\tu32 bcn_space;\t\t/*reg_offset*/\n\tu8 bcn_space_shift;\n\tu16 bcn_space_mask;\n\tu32\tps_aid;\t\t\t/*reg_offset*/\n\tu32\tta;\t\t\t/*reg_offset*/\n};\n\n/* rtl8822c_halinit.c */\nvoid rtl8822c_init_hal_spec(PADAPTER);\nu32 rtl8822c_power_on(PADAPTER);\nvoid rtl8822c_power_off(PADAPTER);\nu8 rtl8822c_hal_init(PADAPTER);\nu8 rtl8822c_mac_verify(PADAPTER);\nvoid rtl8822c_init_misc(PADAPTER padapter);\nu32 rtl8822c_init(PADAPTER);\nu32 rtl8822c_deinit(PADAPTER);\nvoid rtl8822c_init_default_value(PADAPTER);\n\n/* rtl8822c_mac.c */\nu8 rtl8822c_rcr_config(PADAPTER, u32 rcr);\nu8 rtl8822c_rx_ba_ssn_appended(PADAPTER);\nu8 rtl8822c_rx_fcs_append_switch(PADAPTER, u8 enable);\nu8 rtl8822c_rx_fcs_appended(PADAPTER);\nu8 rtl8822c_rx_tsf_addr_filter_config(PADAPTER, u8 config);\ns32 rtl8822c_fw_dl(PADAPTER, u8 wowlan);\nu8 rtl8822c_get_rx_drv_info_size(struct _ADAPTER *a);\nu32 rtl8822c_get_tx_desc_size(struct _ADAPTER *a);\nu32 rtl8822c_get_rx_desc_size(struct _ADAPTER *a);\n\n/* rtl8822c_ops.c */\nu8 rtl8822c_read_efuse(PADAPTER);\nvoid rtl8822c_run_thread(PADAPTER);\nvoid rtl8822c_cancel_thread(PADAPTER);\nu8 rtl8822c_sethwreg(PADAPTER, u8 variable, u8 *pval);\nvoid rtl8822c_gethwreg(PADAPTER, u8 variable, u8 *pval);\nu8 rtl8822c_sethaldefvar(PADAPTER, HAL_DEF_VARIABLE, void *pval);\nu8 rtl8822c_gethaldefvar(PADAPTER, HAL_DEF_VARIABLE, void *pval);\nvoid rtl8822c_set_hal_ops(PADAPTER);\n\n/* tx */\nvoid rtl8822c_init_xmit_priv(_adapter *adapter);\nvoid rtl8822c_fill_txdesc_sectype(struct pkt_attrib *, u8 *ptxdesc);\nvoid rtl8822c_fill_txdesc_vcs(PADAPTER, struct pkt_attrib *, u8 *ptxdesc);\nvoid rtl8822c_fill_txdesc_phy(PADAPTER, struct pkt_attrib *, u8 *ptxdesc);\nvoid rtl8822c_fill_txdesc_force_bmc_camid(struct pkt_attrib *, u8 *ptxdesc);\nvoid rtl8822c_fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);\nu8 rtl8822c_bw_mapping(PADAPTER, struct pkt_attrib *);\nu8 rtl8822c_sc_mapping(PADAPTER, struct pkt_attrib *);\nvoid rtl8822c_fill_txdesc_bf(struct xmit_frame *, u8 *desc);\nvoid rtl8822c_fill_txdesc_mgnt_bf(struct xmit_frame *, u8 *desc);\nvoid rtl8822c_cal_txdesc_chksum(PADAPTER, u8 *ptxdesc);\nvoid rtl8822c_update_txdesc(struct xmit_frame *, u8 *pbuf);\nvoid rtl8822c_dbg_dump_tx_desc(PADAPTER, int frame_tag, u8 *ptxdesc);\n\n/* rx */\nvoid rtl8822c_rxdesc2attribute(struct rx_pkt_attrib *a, u8 *desc);\nvoid rtl8822c_query_rx_desc(union recv_frame *, u8 *pdesc);\n\n/* rtl8822c_cmd.c */\ns32 rtl8822c_fillh2ccmd(PADAPTER, u8 id, u32 buf_len, u8 *pbuf);\nvoid rtl8822c_set_FwPwrMode_cmd(PADAPTER, u8 psmode);\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\nvoid rtl8822c_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);\n#endif\n#endif\n\nvoid rtl8822c_set_FwPwrModeInIPS_cmd(PADAPTER adapter, u8 cmd_param);\nvoid rtl8822c_req_txrpt_cmd(PADAPTER, u8 macid);\nvoid rtl8822c_c2h_handler(PADAPTER, u8 *pbuf, u16 length);\n#ifdef CONFIG_WOWLAN\nvoid rtl8822c_set_fw_pwrmode_inips_cmd_wowlan(PADAPTER padapter, u8 ps_mode);\n#endif\nvoid rtl8822c_c2h_handler_no_io(PADAPTER, u8 *pbuf, u16 length);\n\n#ifdef CONFIG_BT_COEXIST\nvoid rtl8822c_download_BTCoex_AP_mode_rsvd_page(PADAPTER);\n#endif /* CONFIG_BT_COEXIST */\n\n/* rtl8822c_phy.c */\nu8 rtl8822c_phy_init_mac_register(PADAPTER);\nu8 rtl8822c_phy_init(PADAPTER);\nvoid rtl8822c_phy_init_dm_priv(PADAPTER);\nvoid rtl8822c_phy_deinit_dm_priv(PADAPTER);\nvoid rtl8822c_phy_init_haldm(PADAPTER);\nvoid rtl8822c_phy_haldm_watchdog(PADAPTER);\nu32 rtl8822c_read_bb_reg(PADAPTER, u32 addr, u32 mask);\nvoid rtl8822c_write_bb_reg(PADAPTER, u32 addr, u32 mask, u32 val);\nu32 rtl8822c_read_rf_reg(PADAPTER adapter, enum rf_path path, u32 addr, u32 mask);\nvoid rtl8822c_write_rf_reg(PADAPTER adapter, enum rf_path path, u32 addr, u32 mask, u32 val);\nvoid rtl8822c_set_channel_bw(PADAPTER adapter, u8 center_ch, enum channel_width, u8 offset40, u8 offset80);\nvoid rtl8822c_set_tx_power_level(PADAPTER, u8 channel);\nvoid rtl8822c_set_txpwr_done(_adapter *adapter);\nvoid rtl8822c_set_tx_power_index(PADAPTER adapter, u32 powerindex, enum rf_path rfpath, u8 rate);\nu8 rtl8822c_get_tx_power_index(PADAPTER adapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic);\nvoid rtl8822c_notch_filter_switch(PADAPTER, bool enable);\n#ifdef CONFIG_BEAMFORMING\nvoid rtl8822c_phy_bf_init(PADAPTER);\nvoid rtl8822c_phy_bf_enter(PADAPTER, struct sta_info*);\nvoid rtl8822c_phy_bf_leave(PADAPTER, u8 *addr);\nvoid rtl8822c_phy_bf_set_gid_table(PADAPTER, struct beamformer_entry*);\nvoid rtl8822c_phy_bf_sounding_status(PADAPTER, u8 status);\n#endif /* CONFIG_BEAMFORMING */\n\n#endif /* _RTL8822C_H_ */\n"
  },
  {
    "path": "hal/rtl8822c/rtl8822c_cmd.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTL8822C_CMD_C_\n\n#include <hal_data.h>\t\t/* HAL_DATA_TYPE */\n#include \"../hal_halmac.h\"\t/* HRTW_HALMAC_H2C_MAX_SIZE, CMD_ID_RSVD_PAGE and etc. */\n#include \"rtl8822c.h\"\n\n/*\n * Below functions are for C2H\n */\n/*****************************************\n * H2C Msg format :\n *| 31 - 8\t\t|7-5\t| 4 - 0\t|\n *| h2c_msg\t\t|Class\t|CMD_ID\t|\n *| 31-0\t\t\t\t|\n *| Ext msg\t\t\t\t|\n *\n ******************************************/\ns32 rtl8822c_fillh2ccmd(PADAPTER adapter, u8 id, u32 buf_len, u8 *pbuf)\n{\n\tu8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0};\n#ifdef CONFIG_RTW_DEBUG\n\tu8 msg[(RTW_HALMAC_H2C_MAX_SIZE - 1) * 5 + 1] = {0};\n\tu8 *msg_p;\n\tu32 msg_size, i, n;\n#endif /* CONFIG_RTW_DEBUG */\n\tint err;\n\ts32 ret = _FAIL;\n\n\n\tif (!pbuf)\n\t\tgoto exit;\n\n\tif (buf_len > (RTW_HALMAC_H2C_MAX_SIZE - 1))\n\t\tgoto exit;\n\n\tif (rtw_is_surprise_removed(adapter))\n\t\tgoto exit;\n\n#ifdef CONFIG_RTW_DEBUG\n\tmsg_p = msg;\n\tmsg_size = (RTW_HALMAC_H2C_MAX_SIZE - 1) * 5 + 1;\n\tfor (i = 0; i < buf_len; i++) {\n\t\tn = rtw_sprintf(msg_p, msg_size, \" 0x%02x\", pbuf[i]);\n\t\tmsg_p += n;\n\t\tmsg_size -= n;\n\t\tif (msg_size == 0)\n\t\t\tbreak;\n\t}\n\tRTW_DBG(FUNC_ADPT_FMT \": id=0x%02x buf=%s\\n\",\n\t\t FUNC_ADPT_ARG(adapter), id, msg);\n#endif /* CONFIG_RTW_DEBUG */\n\n\th2c[0] = id;\n\t_rtw_memcpy(h2c + 1, pbuf, buf_len);\n\n\terr = rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c);\n\tif (!err)\n\t\tret = _SUCCESS;\n\nexit:\n\n\treturn ret;\n}\n\nvoid rtl8822c_req_txrpt_cmd(PADAPTER adapter, u8 macid)\n{\n\tu8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0};\n\n\tAP_REQ_TXRPT_SET_CMD_ID(h2c, CMD_ID_AP_REQ_TXRPT);\n\tAP_REQ_TXRPT_SET_CLASS(h2c, CLASS_AP_REQ_TXRPT);\n\n\tAP_REQ_TXRPT_SET_STA1_MACID(h2c, macid);\n\tAP_REQ_TXRPT_SET_STA2_MACID(h2c, 0xff);\n\tAP_REQ_TXRPT_SET_RTY_OK_TOTAL(h2c, 0x00);\n\tAP_REQ_TXRPT_SET_RTY_CNT_MACID(h2c, 0x00);\n\trtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c);\n\n\tAP_REQ_TXRPT_SET_RTY_CNT_MACID(h2c, 0x01);\n\trtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c);\n}\n\n#define SET_PWR_MODE_SET_BCN_RECEIVING_TIME(h2c_pkt, value)                    \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 5, value)\n#define SET_PWR_MODE_SET_ADOPT_BCN_RECEIVING_TIME(h2c_pkt, value)              \\\n\tSET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 31, 1, value)\n\nvoid rtl8822c_set_FwPwrMode_cmd(PADAPTER adapter, u8 psmode)\n{\n\tint i;\n\tu8 smart_ps = 0, mode = 0;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n#ifdef CONFIG_BCN_RECV_TIME\n\tu8 bcn_recv_time;\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n#endif\n#ifdef CONFIG_WMMPS_STA\n\tstruct mlme_priv\t*pmlmepriv = &(adapter->mlmepriv);\n\tstruct qos_priv\t*pqospriv = &pmlmepriv->qospriv;\n#endif /* CONFIG_WMMPS_STA */\t\n\tu8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0};\n\tu8 PowerState = 0, awake_intvl = 1, rlbm = 0;\n\tu8 allQueueUAPSD = 0;\n\tchar *fw_psmode_str = \"\";\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *wdinfo = &adapter->wdinfo;\n#endif /* CONFIG_P2P */\n\tu8 hw_port = rtw_hal_get_port(adapter);\n\n\tif (pwrpriv->dtim > 0)\n\t\tRTW_INFO(FUNC_ADPT_FMT \": dtim=%d, HW port id=%d\\n\", FUNC_ADPT_ARG(adapter),\n\t\t\tpwrpriv->dtim, psmode == PS_MODE_ACTIVE ? pwrpriv->current_lps_hw_port_id : hw_port);\n\telse\n\t\tRTW_INFO(FUNC_ADPT_FMT \": HW port id=%d\\n\", FUNC_ADPT_ARG(adapter),\n\t\t\tpsmode == PS_MODE_ACTIVE ? pwrpriv->current_lps_hw_port_id : hw_port);\n\n\tif (psmode == PS_MODE_MIN || psmode == PS_MODE_MAX) {\n#ifdef CONFIG_WMMPS_STA\t\n\t\tif (rtw_is_wmmps_mode(adapter)) {\n\t\t\tmode = 2;\n\n\t\t\tsmart_ps = pwrpriv->wmm_smart_ps;\n\n\t\t\t/* (WMMPS) allQueueUAPSD: 0: PSPoll, 1: QosNullData (if wmm_smart_ps=1) or do nothing (if wmm_smart_ps=2) */\n\t\t\tif ((pqospriv->uapsd_tid & BIT_MASK_TID_TC) == ALL_TID_TC_SUPPORTED_UAPSD)\n\t\t\t\tallQueueUAPSD = 1;\n\t\t} else\n#endif /* CONFIG_WMMPS_STA */\n\t\t{\n\t\t\tmode = 1;\n#ifdef CONFIG_WMMPS_STA\t\n\t\t\t/* For WMMPS test case, the station must retain sleep mode to capture buffered data on LPS mechanism */ \n\t\t\tif ((pqospriv->uapsd_tid & BIT_MASK_TID_TC)  != 0)\n\t\t\t\tsmart_ps = 0;\n\t\t\telse\n#endif /* CONFIG_WMMPS_STA */\n\t\t\t{\n\t\t\t\tsmart_ps = pwrpriv->smart_ps;\n\t\t\t}\n\t\t}\n\n\t\tif (psmode == PS_MODE_MIN)\n\t\t\trlbm = 0;\n\t\telse\n\t\t\trlbm = 1;\n\t} else if (psmode == PS_MODE_DTIM) {\n\t\tmode = 1;\n\t\t/* For WOWLAN LPS, DTIM = (awake_intvl - 1) */\n\t\tif (pwrpriv->dtim > 0 && pwrpriv->dtim < 16)\n\t\t\t/* DTIM = (awake_intvl - 1) */\n\t\t\tawake_intvl = pwrpriv->dtim + 1;\n\t\telse\n\t\t\t/* DTIM = 3 */\n\t\t\tawake_intvl = 4;\n\n\t\trlbm = 2;\n\t\tsmart_ps = pwrpriv->smart_ps;\n\t} else if (psmode == PS_MODE_ACTIVE) {\n\t\tmode = 0;\n\t} else {\n\t\trlbm = 2;\n\t\tawake_intvl = 4;\n\t\tsmart_ps = pwrpriv->smart_ps;\n\t}\n\n#ifdef CONFIG_P2P\n\tif (!rtw_p2p_chk_state(wdinfo, P2P_STATE_NONE)) {\n\t\tawake_intvl = 2;\n\t\trlbm = 1;\n\t}\n#endif /* CONFIG_P2P */\n\n\tif (adapter->registrypriv.wifi_spec == 1) {\n\t\tawake_intvl = 2;\n\t\trlbm = 1;\n\t}\n\n\tif (psmode > 0) {\n#ifdef CONFIG_BT_COEXIST\n\t\tif (rtw_btcoex_IsBtControlLps(adapter) == _TRUE)\n\t\t\tPowerState = rtw_btcoex_RpwmVal(adapter);\n\t\telse\n#endif /* CONFIG_BT_COEXIST */\n\t\t\tPowerState = 0x00; /* AllON(0x0C), RFON(0x04), RFOFF(0x00) */\n\t} else\n\t\tPowerState = 0x0C; /* AllON(0x0C), RFON(0x04), RFOFF(0x00) */\n\n\tif (mode == 0)\n\t\tfw_psmode_str = \"ACTIVE\";\n\telse if (mode == 1)\n\t\tfw_psmode_str = \"LPS\";\n\telse if (mode == 2)\n\t\tfw_psmode_str = \"WMMPS\";\n\telse\n\t\tfw_psmode_str = \"UNSPECIFIED\";\n\n\tRTW_INFO(FUNC_ADPT_FMT\": fw ps mode = %s, drv ps mode = %d, rlbm = %d , smart_ps = %d, allQueueUAPSD = %d\\n\", \n\t\t\t\tFUNC_ADPT_ARG(adapter), fw_psmode_str, psmode, rlbm, smart_ps, allQueueUAPSD);\n\n#ifdef CONFIG_LPS_1T1R\n\tif (psmode > PS_MODE_ACTIVE) {\n\t\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\n\t\tif (hal_data->lps_1t1r != pwrpriv->lps_1t1r\n\t\t\t/* if rf_type already 1T1R, no need to enable LPS-1T1R */\n\t\t\t&& hal_data->NumTotalRFPath > 1\n\t\t\t#if 0 /* this branch always have pathA on both TX and RX */\n\t\t\t/* for now, FW LPS 1T1R operates on TX:A, RX:A */\n\t\t\t&& GET_HAL_TX_PATH_BMP(adapter) & 0x01\n\t\t\t&& GET_HAL_RX_PATH_BMP(adapter) & 0x01\n\t\t\t#endif\n\t\t) {\n\t\t\t/* TODO: cmd macro defined by halmac */\n\t\t\t#define SET_PWR_MODE_EXT_SET_1T1R_EN(h2c_pkt, value) SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)\n\t\t\tu8 h2c_ext[RTW_HALMAC_H2C_MAX_SIZE] = {0};\n\n\t\t\tSET_PWR_MODE_SET_CMD_ID(h2c_ext, 0x11); /* TODO: CMD_ID defined by halmac */\n\t\t\tSET_PWR_MODE_SET_CLASS(h2c_ext, CLASS_SET_PWR_MODE);\n\t\t\tSET_PWR_MODE_EXT_SET_1T1R_EN(h2c_ext, pwrpriv->lps_1t1r);\n\t\t\tRTW_DBG_DUMP(\"H2C-PwrModeExt Parm:\", h2c_ext, RTW_HALMAC_H2C_MAX_SIZE);\n\t\t\tif (rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c_ext) == 0)\n\t\t\t\thal_data->lps_1t1r = pwrpriv->lps_1t1r;\n\t\t}\n\t}\n#endif\n\n\tSET_PWR_MODE_SET_CMD_ID(h2c, CMD_ID_SET_PWR_MODE);\n\tSET_PWR_MODE_SET_CLASS(h2c, CLASS_SET_PWR_MODE);\n\tSET_PWR_MODE_SET_MODE(h2c, mode);\n\tSET_PWR_MODE_SET_SMART_PS(h2c, smart_ps);\n\tSET_PWR_MODE_SET_RLBM(h2c, rlbm);\n\tSET_PWR_MODE_SET_AWAKE_INTERVAL(h2c, awake_intvl);\n\tSET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c, allQueueUAPSD);\n\tSET_PWR_MODE_SET_PWR_STATE(h2c, PowerState);\n\tif (psmode == PS_MODE_ACTIVE) {\n\t\t/* Leave LPS, set the same HW port ID */\n\t\tSET_PWR_MODE_SET_PORT_ID(h2c, pwrpriv->current_lps_hw_port_id);\n\t} else {\n\t\t/* Enter LPS, record HW port ID */\n\t\tSET_PWR_MODE_SET_PORT_ID(h2c, hw_port);\n\t\tpwrpriv->current_lps_hw_port_id = hw_port;\n\t}\n#ifdef CONFIG_BCN_RECV_TIME\n\tif (pmlmeext->bcn_rx_time) {\n\t\tbcn_recv_time = pmlmeext->bcn_rx_time / 128; /*unit : 128 us*/\n\t\tif (pmlmeext->bcn_rx_time % 128)\n\t\t\tbcn_recv_time += 1;\n\n\t\tif (bcn_recv_time > 31)\n\t\t\tbcn_recv_time = 31;\n\t\tSET_PWR_MODE_SET_ADOPT_BCN_RECEIVING_TIME(h2c, 1);\n\t\tSET_PWR_MODE_SET_BCN_RECEIVING_TIME(h2c, bcn_recv_time);\n\t}\n#endif\n\n#ifdef CONFIG_BT_COEXIST\n\trtw_btcoex_RecordPwrMode(adapter, h2c + 1, RTW_HALMAC_H2C_MAX_SIZE - 1);\n#endif /* CONFIG_BT_COEXIST */\n\n\tRTW_DBG_DUMP(\"H2C-PwrMode Parm:\", h2c, RTW_HALMAC_H2C_MAX_SIZE);\n\trtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c);\n}\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\nvoid rtl8822c_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable)\n{\n\tu8\tu1H2CSetPwrMode[RTW_HALMAC_H2C_MAX_SIZE] = {0};\n\n\tSET_PWR_MODE_SET_CMD_ID(u1H2CSetPwrMode, CMD_ID_SET_PWR_MODE);\n\tSET_PWR_MODE_SET_CLASS(u1H2CSetPwrMode, CLASS_SET_PWR_MODE);\n\tSET_PWR_MODE_SET_MODE(u1H2CSetPwrMode, 1);\n\tSET_PWR_MODE_SET_RLBM(u1H2CSetPwrMode, 1);\n\tSET_PWR_MODE_SET_BCN_EARLY_RPT(u1H2CSetPwrMode, enable);\n\tSET_PWR_MODE_SET_PWR_STATE(u1H2CSetPwrMode, 0x0C);\n\t\n\trtw_halmac_send_h2c(adapter_to_dvobj(padapter), u1H2CSetPwrMode);\n}\n#endif\n#endif\n\nvoid rtl8822c_set_FwPwrModeInIPS_cmd(PADAPTER adapter, u8 cmd_param)\n{\n\n\tu8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0};\n\n\tINACTIVE_PS_SET_CMD_ID(h2c, CMD_ID_INACTIVE_PS);\n\tINACTIVE_PS_SET_CLASS(h2c, CLASS_INACTIVE_PS);\n\n\tif (cmd_param & BIT0)\n\t\tINACTIVE_PS_SET_ENABLE(h2c, 1);\n\n\tif (cmd_param & BIT1)\n\t\tINACTIVE_PS_SET_IGNORE_PS_CONDITION(h2c, 1);\n\n\tRTW_DBG_DUMP(\"H2C-FwPwrModeInIPS Parm:\", h2c, RTW_HALMAC_H2C_MAX_SIZE);\n\trtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c);\n}\n\n#ifdef CONFIG_WOWLAN\n\nvoid rtl8822c_set_fw_pwrmode_inips_cmd_wowlan(PADAPTER padapter, u8 ps_mode)\n{\n\tstruct registry_priv  *registry_par = &padapter->registrypriv;\n\tu8 param[H2C_INACTIVE_PS_LEN] = {0};\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n\tRTW_INFO(\"%s, ps_mode: %d\\n\", __func__, ps_mode);\n\tif (ps_mode == PS_MODE_ACTIVE) {\n\t\tSET_H2CCMD_INACTIVE_PS_EN(param, 0);\n\t}\n\telse {\n\t\tSET_H2CCMD_INACTIVE_PS_EN(param, 1);\n\t\tif(registry_par->suspend_type == FW_IPS_DISABLE_BBRF && !check_fwstate(pmlmepriv, _FW_LINKED))\n\t\t\tSET_H2CCMD_INACTIVE_DISBBRF(param, 1);\n\t\tif(registry_par->suspend_type == FW_IPS_WRC) {\n\t\t\tSET_H2CCMD_INACTIVE_PERIOD_SCAN_EN(param, 1);\n\t\t\tSET_H2CCMD_INACTIVE_PS_FREQ(param, 3);\n\t\t\tSET_H2CCMD_INACTIVE_PS_DURATION(param, 1);\n\t\t\tSET_H2CCMD_INACTIVE_PS_PERIOD_SCAN_TIME(param, 3);\n\t\t}\n\t}\n\n\trtl8822c_fillh2ccmd(padapter, H2C_INACTIVE_PS_, sizeof(param), param);\n}\n\n#endif /* CONFIG_WOWLAN */\n\n\n#ifdef CONFIG_BT_COEXIST\nvoid rtl8822c_download_BTCoex_AP_mode_rsvd_page(PADAPTER adapter)\n{\n\thw_var_set_dl_rsvd_page(adapter, RT_MEDIA_CONNECT);\n}\n#endif /* CONFIG_BT_COEXIST */\n\n\n/*\n * Below functions are for C2H\n */\nstatic void c2h_ccx_rpt(PADAPTER adapter, u8 *pdata)\n{\n#ifdef CONFIG_XMIT_ACK\n\tu8 tx_state;\n\n\n\ttx_state = CCX_RPT_GET_TX_STATE(pdata);\n\n\t/* 0 means success, 1 means retry drop */\n\tif (tx_state == 0)\n\t\trtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_SUCCESS);\n\telse\n\t\trtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);\n#endif /* CONFIG_XMIT_ACK */\n}\n\nstatic void\nC2HTxRPTHandler_8822c(\n\t\tPADAPTER\tAdapter,\n\t\tu8\t\t\t*CmdBuf,\n\t\tu8\t\t\tCmdLen\n)\n{\n\t_irqL\t irqL;\n\tu8 macid = 0, IniRate = 0;\n\tu16 TxOK = 0, TxFail = 0;\n\tstruct sta_priv\t*pstapriv = &(GET_PRIMARY_ADAPTER(Adapter))->stapriv, *pstapriv_original = NULL;\n\tu8 TxOK0 = 0, TxOK1 = 0;\n\tu8 TxFail0 = 0, TxFail1 = 0;\n\tstruct sta_info *psta = NULL;\n\tPADAPTER\tadapter_ognl = NULL;\n\n\tif(!pstapriv->gotc2h) {\n\t\tRTW_WARN(\"%s,%d: No gotc2h!\\n\", __FUNCTION__, __LINE__);\n\t\treturn;\n\t}\n\t\n\tadapter_ognl = rtw_get_iface_by_id(GET_PRIMARY_ADAPTER(Adapter), pstapriv->c2h_adapter_id);\n\tif(!adapter_ognl) {\n\t\tRTW_WARN(\"%s: No adapter!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tpsta = rtw_get_stainfo(&adapter_ognl->stapriv, pstapriv->c2h_sta_mac);\n\tif (!psta) {\n\t\tRTW_WARN(\"%s: No corresponding sta_info!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tmacid = C2H_AP_REQ_TXRPT_GET_STA1_MACID(CmdBuf);\n\tTxOK0 = C2H_AP_REQ_TXRPT_GET_TX_OK1_0(CmdBuf);\n\tTxOK1 = C2H_AP_REQ_TXRPT_GET_TX_OK1_1(CmdBuf);\n\tTxOK = (TxOK1 << 8) | TxOK0;\n\tTxFail0 = C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(CmdBuf);\n\tTxFail1 = C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(CmdBuf);\n\tTxFail = (TxFail1 << 8) | TxFail0;\n\tIniRate = C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(CmdBuf);\n\n\tpsta->sta_stats.tx_ok_cnt = TxOK;\n\tpsta->sta_stats.tx_fail_cnt = TxFail;\n\n}\n\nstatic void\nC2HSPC_STAT_8822c(\n\t\tPADAPTER\tAdapter,\n\t\tu8\t\t\t*CmdBuf,\n\t\tu8\t\t\tCmdLen\n)\n{\n\t_irqL\t irqL;\n\tstruct sta_priv *pstapriv = &(GET_PRIMARY_ADAPTER(Adapter))->stapriv;\n\tstruct sta_info *psta = NULL;\n\tstruct sta_info *pbcmc_stainfo = rtw_get_bcmc_stainfo(Adapter);\n\t_list\t*plist, *phead;\n\tu8 idx = C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(CmdBuf);\n\tPADAPTER\tadapter_ognl = NULL;\n\n\tif(!pstapriv->gotc2h) {\n\t\tRTW_WARN(\"%s, %d: No gotc2h!\\n\", __FUNCTION__, __LINE__);\n\t\treturn;\n\t}\n\t\n\tadapter_ognl = rtw_get_iface_by_id(GET_PRIMARY_ADAPTER(Adapter), pstapriv->c2h_adapter_id);\n\tif(!adapter_ognl) {\n\t\tRTW_WARN(\"%s: No adapter!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tpsta = rtw_get_stainfo(&adapter_ognl->stapriv, pstapriv->c2h_sta_mac);\n\tif (!psta) {\n\t\tRTW_WARN(\"%s: No corresponding sta_info!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\tpsta->sta_stats.tx_retry_cnt = (C2H_SPECIAL_STATISTICS_GET_DATA3(CmdBuf) << 8) | C2H_SPECIAL_STATISTICS_GET_DATA2(CmdBuf);\n\trtw_sctx_done(&pstapriv->gotc2h);\n}\n#ifdef CONFIG_FW_HANDLE_TXBCN\n#define C2H_SUB_CMD_ID_FW_TBTT_RPT  0X23\n#define TBTT_RPT_GET_SN(c2h_pkt)\tLE_BITS_TO_4BYTE(c2h_pkt + 0X01, 0, 8)\n#define TBTT_RPT_GET_PORT_ID(c2h_pkt)\tLE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)\n\n#define TBTT_ROOT\t0x00\n#define TBTT_VAP1\t0x10\n#define TBTT_VAP2\t0x20\n#define TBTT_VAP3\t0x30\n\nstatic void c2h_tbtt_rpt(PADAPTER adapter, u8 *pdata)\n{\n\tu8 ap_id, c2h_sn;\n\n\tap_id = TBTT_RPT_GET_PORT_ID(pdata);\n\tc2h_sn = TBTT_RPT_GET_SN(pdata);\n#ifdef DBG_FW_TBTT_RPT\n\tif (ap_id == TBTT_ROOT)\n\t\tRTW_INFO(\"== TBTT ROOT SN:%d==\\n\", c2h_sn);\n\telse if (ap_id == TBTT_VAP1)\n\t\tRTW_INFO(\"== TBTT_VAP1 SN:%d==\\n\", c2h_sn);\n\telse if (ap_id == TBTT_VAP2)\n\t\tRTW_INFO(\"== TBTT_VAP2 SN:%d==\\n\", c2h_sn);\n\telse if (ap_id == TBTT_VAP3)\n\t\tRTW_INFO(\"== TBTT_VAP3 SN:%d==\\n\", c2h_sn);\n\telse\n\t\tRTW_ERR(\"TBTT RPT INFO ERROR\\n\");\n#endif\n}\n#endif\n\n/**\n * c2h = RXDESC + c2h packet\n * size = RXDESC_SIZE + c2h packet size\n * c2h payload = c2h packet revmoe id & seq\n */\nstatic void process_c2h_event(PADAPTER adapter, u8 *c2h, u32 size)\n{\n\tstruct mlme_ext_priv *pmlmeext;\n\tstruct mlme_ext_info *pmlmeinfo;\n\tu32 desc_size;\n\tu8 id, seq;\n\tu8 c2h_len, c2h_payload_len;\n\tu8 *pc2h_data, *pc2h_payload;\n\n\n\tif (!c2h) {\n\t\tRTW_INFO(\"%s: c2h buffer is NULL!!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\tdesc_size = rtl8822c_get_rx_desc_size(adapter);\n\n\tif (size < desc_size) {\n\t\tRTW_INFO(\"%s: c2h length(%d) is smaller than RXDESC_SIZE(%d)!!\\n\",\n\t\t\t __FUNCTION__, size, desc_size);\n\t\treturn;\n\t}\n\n\tpmlmeext = &adapter->mlmeextpriv;\n\tpmlmeinfo = &pmlmeext->mlmext_info;\n\n\t/* shift rx desc len */\n\tpc2h_data = c2h + desc_size;\n\tc2h_len = size - desc_size;\n\n\tid = C2H_GET_CMD_ID(pc2h_data);\n\tseq = C2H_GET_SEQ(pc2h_data);\n\n\t/* shift 2 byte to remove cmd id & seq */\n\tpc2h_payload = pc2h_data + 2;\n\tc2h_payload_len = c2h_len - 2;\n\n\tswitch (id) {\n#ifdef CONFIG_BEAMFORMING\n\tcase CMD_ID_C2H_SND_TXBF:\n\t\tRTW_INFO(\"%s: [CMD_ID_C2H_SND_TXBF] len=%d\\n\", __FUNCTION__, c2h_payload_len);\n\t\trtw_bf_c2h_handler(adapter, id, pc2h_data, c2h_len);\n\t\tbreak;\n#endif /* CONFIG_BEAMFORMING */\n\n\tcase CMD_ID_C2H_AP_REQ_TXRPT:\n\t\t/*RTW_INFO(\"[C2H], C2H_AP_REQ_TXRPT!!\\n\");*/\n\t\tC2HTxRPTHandler_8822c(adapter, pc2h_data, c2h_len);\n\t\tbreak;\n\n\tcase CMD_ID_C2H_SPECIAL_STATISTICS:\n\t\t/*RTW_INFO(\"[C2H], C2H_SPC_STAT!!\\n\");*/\n\t\tC2HSPC_STAT_8822c(adapter, pc2h_data, c2h_len);\n\t\tbreak;\n\n\tcase CMD_ID_C2H_CUR_CHANNEL:\n\t{\n\t\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\t\tstruct submit_ctx *chsw_sctx = &hal->chsw_sctx;\n\n\t\t/* RTW_INFO(\"[C2H], CMD_ID_C2H_CUR_CHANNEL!!\\n\"); */\n\t\trtw_sctx_done(&chsw_sctx);\n\t\tbreak;\n\t}\n\n\tcase C2H_EXTEND:\n\t\tif (C2H_HDR_GET_C2H_SUB_CMD_ID(pc2h_data) == C2H_SUB_CMD_ID_CCX_RPT) {\n\t\t\t/* Shift C2H HDR 4 bytes */\n\t\t\tc2h_ccx_rpt(adapter, pc2h_data);\n\t\t\tbreak;\n\t\t}\n#ifdef CONFIG_FW_HANDLE_TXBCN\n\t\telse if (C2H_HDR_GET_C2H_SUB_CMD_ID(pc2h_data) == C2H_SUB_CMD_ID_FW_TBTT_RPT) {\n\t\t\tc2h_tbtt_rpt(adapter, pc2h_data);\n\t\t\tbreak;\n\t\t}\n#endif\n\t\telse if (C2H_HDR_GET_C2H_SUB_CMD_ID(pc2h_data) == 0x1B) {\n\t\t\t/* C2H_SUB_CMD_ID_C2H_PKT_FW_STATUS_NOTIFY */\n\t\t\tbreak;\n\t\t}\n\n\n\t\t/* indicate c2h pkt + rx desc to halmac */\n\t\trtw_halmac_c2h_handle(adapter_to_dvobj(adapter), c2h, size);\n\t\tbreak;\n\n\t/* others for c2h common code */\n\tdefault:\n\t\tc2h_handler(adapter, id, seq, c2h_payload_len, pc2h_payload);\n\t\tbreak;\n\t}\n}\n\nvoid rtl8822c_c2h_handler(PADAPTER adapter, u8 *pbuf, u16 length)\n{\n#ifdef CONFIG_WOWLAN\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\n\n\tif (pwrpriv->wowlan_mode == _TRUE) {\n#ifdef CONFIG_RTW_DEBUG\n\t\tu32 desc_size;\n\n\t\tdesc_size = rtl8822c_get_rx_desc_size(adapter);\n\t\tRTW_INFO(\"%s: return because wowolan_mode==TRUE! CMDID=%d\\n\",\n\t\t\t __FUNCTION__, C2H_GET_CMD_ID(pbuf + desc_size));\n#endif /* CONFIG_RTW_DEBUG */\n\t\treturn;\n\t}\n#endif /* CONFIG_WOWLAN*/\n\n\tprocess_c2h_event(adapter, pbuf, length);\n}\n\n/**\n * pbuf = RXDESC + c2h packet\n * length = RXDESC_SIZE + c2h packet size\n */\nvoid rtl8822c_c2h_handler_no_io(PADAPTER adapter, u8 *pbuf, u16 length)\n{\n\tu32 desc_size;\n\tu8 id, seq;\n\tu8 *pc2h_content;\n\tu8 res;\n\n\n\tif ((length == 0) || (!pbuf))\n\t\treturn;\n\n\tdesc_size = rtl8822c_get_rx_desc_size(adapter);\n\n\t/* shift rx desc len to get c2h packet content */\n\tpc2h_content = pbuf + desc_size;\n\tid = C2H_GET_CMD_ID(pc2h_content);\n\tseq = C2H_GET_SEQ(pc2h_content);\n\n\tRTW_DBG(\"%s: C2H, ID=%d seq=%d len=%d\\n\",\n\t\t __FUNCTION__, id, seq, length);\n\n\tswitch (id) {\n\tcase CMD_ID_C2H_SND_TXBF:\n\tcase CMD_ID_C2H_CCX_RPT:\n\tcase C2H_BT_MP_INFO:\n\tcase C2H_FW_CHNL_SWITCH_COMPLETE:\n\tcase C2H_IQK_FINISH:\n\tcase C2H_MCC:\n\tcase C2H_BCN_EARLY_RPT:\n\tcase C2H_EXTEND:\n\t\t/* no I/O, process directly */\n\t\tprocess_c2h_event(adapter, pbuf, length);\n\t\tbreak;\n\n\tdefault:\n\t\t/* Others may need I/O, run in command thread */\n\t\tres = rtw_c2h_packet_wk_cmd(adapter, pbuf, length);\n\t\tif (res == _FAIL)\n\t\t\tRTW_ERR(\"%s: C2H(%d) enqueue FAIL!\\n\", __FUNCTION__, id);\n\t\tbreak;\n\t}\n}\n"
  },
  {
    "path": "hal/rtl8822c/rtl8822c_halinit.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTL8822C_HALINIT_C_\n\n#include <drv_types.h>\t\t/* PADAPTER, basic_types.h and etc. */\n#include <hal_data.h>\t\t/* GET_HAL_SPEC(), HAL_DATA_TYPE */\n#include \"../hal_halmac.h\"\t/* HALMAC API */\n#include \"rtl8822c.h\"\n\n\nvoid rtl8822c_init_hal_spec(PADAPTER adapter)\n{\n\tstruct hal_spec_t *hal_spec;\n\n\n\thal_spec = GET_HAL_SPEC(adapter);\n\trtw_halmac_fill_hal_spec(adapter_to_dvobj(adapter), hal_spec);\n\n\thal_spec->ic_name = \"rtl8822c\";\n\thal_spec->macid_num = 128;\n\t/* hal_spec->sec_cam_ent_num follow halmac setting */\n\thal_spec->sec_cap = SEC_CAP_CHK_BMC;\n\thal_spec->rfpath_num_2g = 2;\n\thal_spec->rfpath_num_5g = 2;\n\thal_spec->txgi_max = 127;\n\thal_spec->txgi_pdbm = 4;\n\thal_spec->max_tx_cnt = 2;\n\thal_spec->tx_nss_num = 2;\n\thal_spec->rx_nss_num = 2;\n\thal_spec->band_cap = BAND_CAP_2G | BAND_CAP_5G;\n\thal_spec->bw_cap = BW_CAP_20M | BW_CAP_40M | BW_CAP_80M;\n\thal_spec->port_num = 5;\n\thal_spec->proto_cap = PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N | PROTO_CAP_11AC;\n\n\thal_spec->wl_func = 0\n\t\t\t    | WL_FUNC_P2P\n\t\t\t    | WL_FUNC_MIRACAST\n\t\t\t    | WL_FUNC_TDLS\n\t\t\t    ;\n\n#if CONFIG_TX_AC_LIFETIME\n\thal_spec->tx_aclt_unit_factor = 8;\n#endif\n\n\thal_spec->rx_tsf_filter = 1;\n\n\thal_spec->pg_txpwr_saddr = 0x10;\n\thal_spec->pg_txgi_diff_factor = 2;\n\n\thal_spec->hci_type = 0;\n\n\trtw_macid_ctl_init_sleep_reg(adapter_to_macidctl(adapter)\n\t\t, REG_MACID_SLEEP_8822C\n\t\t, REG_MACID_SLEEP1_8822C\n\t\t, REG_MACID_SLEEP2_8822C\n\t\t, REG_MACID_SLEEP3_8822C);\n}\n\nu32 rtl8822c_power_on(PADAPTER adapter)\n{\n\tstruct dvobj_priv *d;\n\tPHAL_DATA_TYPE hal;\n\tu8 bMacPwrCtrlOn;\n\tint err = 0;\n\tu8 ret = _SUCCESS;\n\n\n\td = adapter_to_dvobj(adapter);\n\n\tbMacPwrCtrlOn = _FALSE;\n\trtw_hal_get_hwreg(adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);\n\tif (bMacPwrCtrlOn == _TRUE)\n\t\tgoto out;\n\n\terr = rtw_halmac_poweron(d);\n\tif (err) {\n\t\tRTW_ERR(\"%s: Power ON Fail!!\\n\", __FUNCTION__);\n\t\tret = _FAIL;\n\t\tgoto out;\n\t}\n\n\tbMacPwrCtrlOn = _TRUE;\n\trtw_hal_set_hwreg(adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);\n\n#ifdef CONFIG_RTW_DISABLE_HW_PDN\n\trtw_write8(adapter, REG_SYS_PW_CTRL + 1, (rtw_read8(adapter, REG_SYS_PW_CTRL + 1) & (~BIT(7))));\n#endif\n\nout:\n\treturn ret;\n}\n\nvoid rtl8822c_power_off(PADAPTER adapter)\n{\n\tstruct dvobj_priv *d;\n\tu8 bMacPwrCtrlOn;\n\tint err = 0;\n\n\n\td = adapter_to_dvobj(adapter);\n\n\tbMacPwrCtrlOn = _FALSE;\n\trtw_hal_get_hwreg(adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);\n\tif (bMacPwrCtrlOn == _FALSE)\n\t\tgoto out;\n\n\tbMacPwrCtrlOn = _FALSE;\n\trtw_hal_set_hwreg(adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);\n\n\tGET_HAL_DATA(adapter)->bFWReady = _FALSE;\n\n\terr = rtw_halmac_poweroff(d);\n\tif (err) {\n\t\tRTW_ERR(\"%s: Power OFF Fail!!\\n\", __FUNCTION__);\n\t\tgoto out;\n\t}\n\nout:\n\treturn;\n}\n\nu8 rtl8822c_hal_init(PADAPTER adapter)\n{\n\tstruct dvobj_priv *d;\n\tPHAL_DATA_TYPE hal;\n\tint err;\n\tu8 fw_bin = _TRUE;\n\n\td = adapter_to_dvobj(adapter);\n\thal = GET_HAL_DATA(adapter);\n\n\thal->bFWReady = _FALSE;\n\thal->fw_ractrl = _FALSE;\n\n#ifdef CONFIG_NO_FW\n\terr = rtw_halmac_init_hal(d);\n\tif(!err) {\n\t\tRTW_INFO(\"%s@%d: no fw test successful\\n\", __func__, __LINE__);\n\t\treturn _TRUE;\n\t}\n#endif\n\n#ifdef CONFIG_FILE_FWIMG\n\trtw_get_phy_file_path(adapter, MAC_FILE_FW_NIC);\n\tif (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {\n\t\tRTW_INFO(\"%s acquire FW from file:%s\\n\", __FUNCTION__, rtw_phy_para_file_path);\n\t\tfw_bin = _TRUE;\n\t} else\n#endif /* CONFIG_FILE_FWIMG */\n\t{\n\t\tRTW_INFO(\"%s fw source from array\\n\", __FUNCTION__);\n\t\tfw_bin = _FALSE;\n\t}\n\n#ifdef CONFIG_FILE_FWIMG\n\tif (_TRUE == fw_bin)\n\t\terr = rtw_halmac_init_hal_fw_file(d, rtw_phy_para_file_path);\n\telse\n#endif /* CONFIG_FILE_FWIMG */\n\t\terr = rtw_halmac_init_hal_fw(d, array_mp_8822c_fw_nic, array_length_mp_8822c_fw_nic);\n\n\tif (err) {\n\t\tRTW_ERR(\"%s Download Firmware from %s failed\\n\", __FUNCTION__, (fw_bin) ? \"file\" : \"array\");\n\t\treturn _FALSE;\n\t}\n\n\t\n\n\tRTW_INFO(\"%s Download Firmware from %s success\\n\", __FUNCTION__, (fw_bin) ? \"file\" : \"array\");\n\tRTW_INFO(\"%s FW Version:%d SubVersion:%d FW size:%d\\n\", \"NIC\",\n\t\thal->firmware_version, hal->firmware_sub_version, hal->firmware_size);\n\n\t/* Sync driver status with hardware setting */\n\trtw_hal_get_hwreg(adapter, HW_VAR_RCR, NULL);\n\thal->bFWReady = _TRUE;\n\thal->fw_ractrl = _TRUE;\n\n\treturn _TRUE;\n}\n\nu8 rtl8822c_mac_verify(PADAPTER adapter)\n{\n\tstruct dvobj_priv *d;\n\tint err;\n\n\n\td = adapter_to_dvobj(adapter);\n\n\terr = rtw_halmac_self_verify(d);\n\tif (err) {\n\t\tRTW_INFO(\"%s fail\\n\", __FUNCTION__);\n\t\treturn _FALSE;\n\t}\n\n\tRTW_INFO(\"%s successful\\n\", __FUNCTION__);\n\treturn _TRUE;\n}\n\nvoid rtl8822c_init_misc(PADAPTER adapter)\n{\n\tPHAL_DATA_TYPE hal;\n\tu8 v8 = 0;\n\tu32 v32 = 0;\n\n\n\thal = GET_HAL_DATA(adapter);\n\n\n\t/* initial security setting */\n\tinvalidate_cam_all(adapter);\n\n\t/* check RCR/ICV bit */\n\trtw_hal_rcr_clear(adapter, BIT_ACRC32_8822C | BIT_AICV_8822C);\n\n\t/* clear rx ctrl frame */\n\trtw_write16(adapter, REG_RXFLTMAP1_8822C, 0);\n\n\t/*Enable MAC security engine*/\n\trtw_write16(adapter, REG_CR, (rtw_read16(adapter, REG_CR) | BIT_MAC_SEC_EN));\n\n#ifdef CONFIG_XMIT_ACK\n\t/* ack for xmit mgmt frames. */\n\trtw_write32(adapter, REG_FWHW_TXQ_CTRL_8822C,\n\t\trtw_read32(adapter, REG_FWHW_TXQ_CTRL_8822C) | BIT_EN_QUEUE_RPT_8822C(BIT(4)));\n#endif /* CONFIG_XMIT_ACK */\n\n#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX\n\trtw_hal_rcr_add(adapter, BIT_TCPOFLD_EN_8822C);\n#endif /* CONFIG_TCP_CSUM_OFFLOAD_RX*/\n}\n\nu32 rtl8822c_init(PADAPTER adapter)\n{\n\tu8 ok = _TRUE;\n\tPHAL_DATA_TYPE hal;\n\n\thal = GET_HAL_DATA(adapter);\n\n\tok = rtl8822c_hal_init(adapter);\n\tif (_FALSE == ok)\n\t\treturn _FAIL;\n\n\trtl8822c_phy_init_haldm(adapter);\n#ifdef CONFIG_BEAMFORMING\n\trtl8822c_phy_bf_init(adapter);\n#endif\n\n#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\t/*HW / FW init*/\n\trtw_hal_set_default_port_id_cmd(adapter, 0);\n#endif\n\n#ifdef CONFIG_BT_COEXIST\n\t/* Init BT hw config. */\n\tif (_TRUE == hal->EEPROMBluetoothCoexist) {\n\t\trtw_btcoex_HAL_Initialize(adapter, _FALSE);\n\t\t#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\t\trtw_hal_set_wifi_btc_port_id_cmd(adapter);\n\t\t#endif\n\t} else\n#endif /* CONFIG_BT_COEXIST */\n\t\trtw_btcoex_wifionly_hw_config(adapter);\n\n\trtl8822c_init_misc(adapter);\n\n\treturn _SUCCESS;\n}\n\nu32 rtl8822c_deinit(PADAPTER adapter)\n{\n\tstruct dvobj_priv *d;\n\tPHAL_DATA_TYPE hal;\n\tint err;\n\n\n\td = adapter_to_dvobj(adapter);\n\thal = GET_HAL_DATA(adapter);\n\n\thal->bFWReady = _FALSE;\n\thal->fw_ractrl = _FALSE;\n\n\terr = rtw_halmac_deinit_hal(d);\n\tif (err)\n\t\treturn _FAIL;\n\n\treturn _SUCCESS;\n}\n\nvoid rtl8822c_init_default_value(PADAPTER adapter)\n{\n\tPHAL_DATA_TYPE hal;\n\tu8 i;\n\n\n\thal = GET_HAL_DATA(adapter);\n\n\t/* init default value */\n\thal->fw_ractrl = _FALSE;\n\n\tif (!adapter_to_pwrctl(adapter)->bkeepfwalive)\n\t\thal->LastHMEBoxNum = 0;\n\n\t/* init phydm default value */\n\thal->bIQKInitialized = _FALSE;\n\n\t/* init Efuse variables */\n\thal->EfuseUsedBytes = 0;\n\thal->EfuseUsedPercentage = 0;\n\n\thal->EfuseHal.fakeEfuseBank = 0;\n\thal->EfuseHal.fakeEfuseUsedBytes = 0;\n\t_rtw_memset(hal->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE);\n\t_rtw_memset(hal->EfuseHal.fakeEfuseInitMap, 0xFF, EFUSE_MAX_MAP_LEN);\n\t_rtw_memset(hal->EfuseHal.fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);\n\thal->EfuseHal.BTEfuseUsedBytes = 0;\n\thal->EfuseHal.BTEfuseUsedPercentage = 0;\n\t_rtw_memset(hal->EfuseHal.BTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK * EFUSE_MAX_HW_SIZE);\n\t_rtw_memset(hal->EfuseHal.BTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);\n\t_rtw_memset(hal->EfuseHal.BTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);\n\thal->EfuseHal.fakeBTEfuseUsedBytes = 0;\n\t_rtw_memset(hal->EfuseHal.fakeBTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK * EFUSE_MAX_HW_SIZE);\n\t_rtw_memset(hal->EfuseHal.fakeBTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);\n\t_rtw_memset(hal->EfuseHal.fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);\n\n}\n"
  },
  {
    "path": "hal/rtl8822c/rtl8822c_mac.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTL8822C_MAC_C_\n\n#include <drv_types.h>\t\t/* PADAPTER, basic_types.h and etc. */\n#include <hal_data.h>\t\t/* HAL_DATA_TYPE */\n#include \"../hal_halmac.h\"\t/* Register Definition and etc. */\n#include \"rtl8822c.h\"\t\t/* FW array */\n\n\ninline u8 rtl8822c_rcr_config(PADAPTER p, u32 rcr)\n{\n\tu32 v32;\n\tint err;\n\n\n\tv32 = GET_HAL_DATA(p)->ReceiveConfig;\n\tv32 ^= rcr;\n\tv32 &= BIT_APP_PHYSTS_8822C;\n\tif (v32) {\n\t\tv32 = rcr & BIT_APP_PHYSTS_8822C;\n\t\tRTW_INFO(\"%s: runtime %s rx phy status!\\n\",\n\t\t\t __FUNCTION__, v32 ? \"ENABLE\" : \"DISABLE\");\n\t\tif (v32) {\n\t\t\terr = rtw_halmac_config_rx_info(adapter_to_dvobj(p), HALMAC_DRV_INFO_PHY_STATUS);\n\t\t\tif (err) {\n\t\t\t\tRTW_INFO(\"%s: Enable rx phy status FAIL!!\", __FUNCTION__);\n\t\t\t\trcr &= ~BIT_APP_PHYSTS_8822C;\n\t\t\t}\n\t\t} else {\n\t\t\terr = rtw_halmac_config_rx_info(adapter_to_dvobj(p), HALMAC_DRV_INFO_NONE);\n\t\t\tif (err) {\n\t\t\t\tRTW_INFO(\"%s: Disable rx phy status FAIL!!\", __FUNCTION__);\n\t\t\t\trcr |= BIT_APP_PHYSTS_8822C;\n\t\t\t}\n\t\t}\n\t}\n\n\terr = rtw_write32(p, REG_RCR_8822C, rcr);\n\tif (_FAIL == err)\n\t\treturn _FALSE;\n\n\tGET_HAL_DATA(p)->ReceiveConfig = rcr;\n\treturn _TRUE;\n}\n\ninline u8 rtl8822c_rx_ba_ssn_appended(PADAPTER p)\n{\n\treturn rtw_hal_rcr_check(p, BIT_APP_BASSN_8822C);\n}\n\ninline u8 rtl8822c_rx_fcs_append_switch(PADAPTER p, u8 enable)\n{\n\tu32 rcr_bit;\n\tu8 ret = _TRUE;\n\n\trcr_bit = BIT_APP_FCS_8822C;\n\tif (_TRUE == enable)\n\t\tret = rtw_hal_rcr_add(p, rcr_bit);\n\telse\n\t\tret = rtw_hal_rcr_clear(p, rcr_bit);\n\n\treturn ret;\n}\n\ninline u8 rtl8822c_rx_fcs_appended(PADAPTER p)\n{\n\treturn rtw_hal_rcr_check(p, BIT_APP_FCS_8822C);\n}\n\ninline u8 rtl8822c_rx_tsf_addr_filter_config(PADAPTER p, u8 config)\n{\n\tu8 v8;\n\tint err;\n\n\tv8 = GET_HAL_DATA(p)->rx_tsf_addr_filter_config;\n\n\tif (v8 != config) {\n\n\t\terr = rtw_write8(p, REG_NAN_RX_TSF_FILTER_8822C, config);\n\t\tif (_FAIL == err)\n\t\t\treturn _FALSE;\n\t}\n\n\tGET_HAL_DATA(p)->rx_tsf_addr_filter_config = config;\n\treturn _TRUE;\n}\n\n/*\n * Return:\n *\t_SUCCESS\tDownload Firmware OK.\n *\t_FAIL\t\tDownload Firmware FAIL!\n */\ns32 rtl8822c_fw_dl(PADAPTER adapter, u8 wowlan)\n{\n\tstruct dvobj_priv *d = adapter_to_dvobj(adapter);\n\tHAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\tint err;\n\tu8 fw_bin = _TRUE;\n\n#ifdef CONFIG_FILE_FWIMG\n#ifdef CONFIG_WOWLAN\n\tif (wowlan)\n\t\trtw_get_phy_file_path(adapter, MAC_FILE_FW_WW_IMG);\n\telse\n#endif /* CONFIG_WOWLAN */\n\t\trtw_get_phy_file_path(adapter, MAC_FILE_FW_NIC);\n\n\tif (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {\n\t\tRTW_INFO(\"%s acquire FW from file:%s\\n\", __FUNCTION__, rtw_phy_para_file_path);\n\t\tfw_bin = _TRUE;\n\t} else\n#endif /* CONFIG_FILE_FWIMG */\n\t{\n\t\tRTW_INFO(\"%s fw source from array\\n\", __FUNCTION__);\n\t\tfw_bin = _FALSE;\n\t}\n\n#ifdef CONFIG_FILE_FWIMG\n\tif (_TRUE == fw_bin) {\n\t\terr = rtw_halmac_dlfw_from_file(d, rtw_phy_para_file_path);\n\t} else\n#endif /* CONFIG_FILE_FWIMG */\n\t{\n\t\t#ifdef CONFIG_WOWLAN\n\t\tif (_TRUE == wowlan)\n\t\t\terr = rtw_halmac_dlfw(d, array_mp_8822c_fw_wowlan, array_length_mp_8822c_fw_wowlan);\n\t\telse\n\t\t#endif /* CONFIG_WOWLAN */\n\t\t\terr = rtw_halmac_dlfw(d, array_mp_8822c_fw_nic, array_length_mp_8822c_fw_nic);\n\t}\n\n\tif (!err) {\n\t\thal->bFWReady = _TRUE;\n\t\thal->fw_ractrl = _TRUE;\n\t\tRTW_INFO(\"%s Download Firmware from %s success\\n\", __FUNCTION__, (fw_bin) ? \"file\" : \"array\");\n\t\tRTW_INFO(\"%s FW Version:%d SubVersion:%d FW size:%d\\n\", (wowlan) ? \"WOW\" : \"NIC\",\n\t\t\thal->firmware_version, hal->firmware_sub_version, hal->firmware_size);\n\t\treturn _SUCCESS;\n\t} else {\n\t\thal->bFWReady = _FALSE;\n\t\thal->fw_ractrl = _FALSE;\n\t\tRTW_ERR(\"%s Download Firmware from %s failed\\n\", __FUNCTION__, (fw_bin) ? \"file\" : \"array\");\n\t\treturn _FAIL;\n\t}\n}\n\nu8 rtl8822c_get_rx_drv_info_size(struct _ADAPTER *a)\n{\n\tstruct dvobj_priv *d;\n\tu8 size = 80;\t/* HALMAC_RX_DESC_DUMMY_SIZE_MAX_88XX */\n\tint err = 0;\n\n\n\td = adapter_to_dvobj(a);\n\n\terr = rtw_halmac_get_rx_drv_info_sz(d, &size);\n\tif (err) {\n\t\tRTW_WARN(FUNC_ADPT_FMT \": Fail to get DRV INFO size!!(err=%d)\\n\",\n\t\t\t FUNC_ADPT_ARG(a), err);\n\t\tsize = 80;\n\t}\n\n\treturn size;\n}\n\nu32 rtl8822c_get_tx_desc_size(struct _ADAPTER *a)\n{\n\tstruct dvobj_priv *d;\n\tu32 size = 48;\t/* HALMAC_TX_DESC_SIZE_8822C */\n\tint err = 0;\n\n\n\td = adapter_to_dvobj(a);\n\n\terr = rtw_halmac_get_tx_desc_size(d, &size);\n\tif (err) {\n\t\tRTW_WARN(FUNC_ADPT_FMT \": Fail to get TX Descriptor size!!(err=%d)\\n\",\n\t\t\t FUNC_ADPT_ARG(a), err);\n\t\tsize = 48;\n\t}\n\n\treturn size;\n}\n\nu32 rtl8822c_get_rx_desc_size(struct _ADAPTER *a)\n{\n\tstruct dvobj_priv *d;\n\tu32 size = 24;\t/* HALMAC_RX_DESC_SIZE_8822C */\n\tint err = 0;\n\n\n\td = adapter_to_dvobj(a);\n\n\terr = rtw_halmac_get_rx_desc_size(d, &size);\n\tif (err) {\n\t\tRTW_WARN(FUNC_ADPT_FMT \": Fail to get RX Descriptor size!!(err=%d)\\n\",\n\t\t\t FUNC_ADPT_ARG(a), err);\n\t\tsize = 24;\n\t}\n\n\treturn size;\n}\n"
  },
  {
    "path": "hal/rtl8822c/rtl8822c_ops.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTL8822C_OPS_C_\n\n#include <drv_types.h>\t\t/* basic_types.h, rtw_io.h and etc. */\n#include <rtw_xmit.h>\t\t/* struct xmit_priv */\n#ifdef DBG_CONFIG_ERROR_DETECT\n#include <rtw_sreset.h>\n#endif /* DBG_CONFIG_ERROR_DETECT */\n#include <hal_data.h>\t\t/* PHAL_DATA_TYPE, GET_HAL_DATA() */\n#include <hal_com.h>\t\t/* rtw_hal_config_rftype(), dump_chip_info() and etc. */\n#include \"../hal_halmac.h\"\t/* GET_RX_DESC_XXX_8822C() */\n#include \"rtl8822c.h\"\n#include \"rtl8822c_hal.h\"\n\n\nstatic const struct hw_port_reg port_cfg[] = {\n\t/*port 0*/\n\t{\n\t.net_type = (REG_CR_8822C + 2),\n\t.net_type_shift = 0,\n\t.macaddr = REG_MACID_8822C,\n\t.bssid = REG_BSSID_8822C,\n\t.bcn_ctl = REG_BCN_CTRL_8822C,\n\t.tsf_rst = REG_DUAL_TSF_RST,\n\t.tsf_rst_bit = BIT_TSFTR_RST_8822C,\n\t.bcn_space = REG_MBSSID_BCN_SPACE_8822C,\n\t.bcn_space_shift = 0,\n\t.bcn_space_mask = 0xffff,\n\t.ps_aid = REG_BCN_PSR_RPT_8822C,\n\t.ta = REG_TRANSMIT_ADDRSS_0_8822C,\n\t},\n\t/*port 1*/\n\t{\n\t.net_type = (REG_CR_8822C + 2),\n\t.net_type_shift = 2,\n\t.macaddr = REG_MACID1_8822C,\n\t.bssid = REG_BSSID1_8822C,\n\t.bcn_ctl = REG_BCN_CTRL_CLINT0_8822C,\n\t.tsf_rst = REG_DUAL_TSF_RST,\n\t.tsf_rst_bit = BIT_TSFTR_CLI0_RST_8822C,\n\t.bcn_space = REG_MBSSID_BCN_SPACE_8822C,\n\t.bcn_space_shift = 16,\n\t.bcn_space_mask = 0xfff,\n\t.ps_aid = REG_BCN_PSR_RPT1_8822C,\n\t.ta = REG_TRANSMIT_ADDRSS_1_8822C,\n\t},\n\t/*port 2*/\n\t{\n\t.net_type =  REG_CR_EXT_8822C,\n\t.net_type_shift = 0,\n\t.macaddr = REG_MACID2_8822C,\n\t.bssid = REG_BSSID2_8822C,\n\t.bcn_ctl = REG_BCN_CTRL_CLINT1_8822C,\n\t.tsf_rst = REG_DUAL_TSF_RST,\n\t.tsf_rst_bit = BIT_TSFTR_CLI1_RST_8822C,\n\t.bcn_space = REG_MBSSID_BCN_SPACE2_8822C,\n\t.bcn_space_shift = 0,\n\t.bcn_space_mask = 0xfff,\n\t.ps_aid = REG_BCN_PSR_RPT2_8822C,\n\t.ta = REG_TRANSMIT_ADDRSS_2_8822C,\n\t},\n\t/*port 3*/\n\t{\n\t.net_type =  REG_CR_EXT_8822C,\n\t.net_type_shift = 2,\n\t.macaddr = REG_MACID3_8822C,\n\t.bssid = REG_BSSID3_8822C,\n\t.bcn_ctl = REG_BCN_CTRL_CLINT2_8822C,\n\t.tsf_rst = REG_DUAL_TSF_RST,\n\t.tsf_rst_bit = BIT_TSFTR_CLI2_RST_8822C,\n\t.bcn_space = REG_MBSSID_BCN_SPACE2_8822C,\n\t.bcn_space_shift = 16,\n\t.bcn_space_mask = 0xfff,\n\t.ps_aid = REG_BCN_PSR_RPT3_8822C,\n\t.ta = REG_TRANSMIT_ADDRSS_3_8822C,\n\t},\n\t/*port 4*/\n\t{\n\t.net_type =  REG_CR_EXT_8822C,\n\t.net_type_shift = 4,\n\t.macaddr = REG_MACID4_8822C,\n\t.bssid = REG_BSSID4_8822C,\n\t.bcn_ctl = REG_BCN_CTRL_CLINT3_8822C,\n\t.tsf_rst = REG_DUAL_TSF_RST,\n\t.tsf_rst_bit = BIT_TSFTR_CLI3_RST_8822C,\n\t.bcn_space = REG_MBSSID_BCN_SPACE3_8822C,\n\t.bcn_space_shift = 0,\n\t.bcn_space_mask = 0xfff,\n\t.ps_aid = REG_BCN_PSR_RPT4_8822C,\n\t.ta = REG_TRANSMIT_ADDRSS_4_8822C,\n\t},\n};\n\nstatic u32 hw_bcn_ctrl_addr(_adapter *adapter, u8 hw_port)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tu32 addr = 0;\n\n\tif (hw_port >= hal_spec->port_num) {\n\t\tRTW_ERR(FUNC_ADPT_FMT\" HW Port(%d) invalid\\n\", FUNC_ADPT_ARG(adapter), hw_port);\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\taddr = port_cfg[hw_port].bcn_ctl;\n\nexit:\n\treturn addr;\n}\n#ifdef CONFIG_CLIENT_PORT_CFG\nstatic void hw_bcn_ctrl_set(_adapter *adapter, u8 hw_port, u8 bcn_ctl_val)\n{\n\tu32 bcn_ctl_addr = 0;\n\n\tif (hw_port >= MAX_HW_PORT) {\n\t\tRTW_ERR(FUNC_ADPT_FMT\" HW Port(%d) invalid\\n\", FUNC_ADPT_ARG(adapter), hw_port);\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tbcn_ctl_addr = port_cfg[hw_port].bcn_ctl;\n\trtw_write8(adapter, bcn_ctl_addr, bcn_ctl_val);\n}\n#endif\nstatic void hw_bcn_ctrl_add(_adapter *adapter, u8 hw_port, u8 bcn_ctl_val)\n{\n\tu32 bcn_ctl_addr = 0;\n\tu8 val8 = 0;\n\n\tif (hw_port >= MAX_HW_PORT) {\n\t\tRTW_ERR(FUNC_ADPT_FMT\" HW Port(%d) invalid\\n\", FUNC_ADPT_ARG(adapter), hw_port);\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tbcn_ctl_addr = port_cfg[hw_port].bcn_ctl;\n\tval8 = rtw_read8(adapter, bcn_ctl_addr) | bcn_ctl_val;\n\trtw_write8(adapter, bcn_ctl_addr, val8);\n}\n\nstatic void hw_bcn_ctrl_clr(_adapter *adapter, u8 hw_port, u8 bcn_ctl_val)\n{\n\tu32 bcn_ctl_addr = 0;\n\tu8 val8 = 0;\n\n\tif (hw_port >= MAX_HW_PORT) {\n\t\tRTW_ERR(FUNC_ADPT_FMT\" HW Port(%d) invalid\\n\", FUNC_ADPT_ARG(adapter), hw_port);\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tbcn_ctl_addr = port_cfg[hw_port].bcn_ctl;\n\tval8 = rtw_read8(adapter, bcn_ctl_addr);\n\tval8 &= ~bcn_ctl_val;\n\trtw_write8(adapter, bcn_ctl_addr, val8);\n}\n\nstatic void read_chip_version(PADAPTER adapter)\n{\n\tPHAL_DATA_TYPE hal;\n\tu32 value32;\n\n\n\thal = GET_HAL_DATA(adapter);\n\n\tvalue32 = rtw_read32(adapter, REG_SYS_CFG1_8822C);\n\thal->version_id.ICType = CHIP_8822C;\n\thal->version_id.ChipType = ((value32 & BIT_RTL_ID_8822C) ? TEST_CHIP : NORMAL_CHIP);\n\thal->version_id.CUTVersion = BIT_GET_CHIP_VER_8822C(value32);\n\thal->version_id.VendorType = BIT_GET_VENDOR_ID_8822C(value32);\n\thal->version_id.VendorType >>= 2;\n\tswitch (hal->version_id.VendorType) {\n\tcase 0:\n\t\thal->version_id.VendorType = CHIP_VENDOR_TSMC;\n\t\tbreak;\n\tcase 1:\n\t\thal->version_id.VendorType = CHIP_VENDOR_SMIC;\n\t\tbreak;\n\tcase 2:\n\t\thal->version_id.VendorType = CHIP_VENDOR_UMC;\n\t\tbreak;\n\t}\n\n\thal->version_id.RFType = ((value32 & BIT_RF_TYPE_ID_8822C) ? RF_TYPE_2T2R : RF_TYPE_1T1R);\n\tif (adapter->registrypriv.special_rf_path == 1)\n\t\thal->version_id.RFType = RF_TYPE_1T1R;\t/* RF_1T1R; */\n\n\t/* refer to sd7 code base*/\n\thal->RegulatorMode = ((value32 & BIT_INTERNAL_EXTERNAL_SWR_8822C) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);\n\n\tvalue32 = rtw_read32(adapter, REG_SYS_STATUS1_8822C);\n\thal->version_id.ROMVer = BIT_GET_RF_RL_ID_8822C(value32);\n\n\t/* For multi-function consideration. */\n\thal->MultiFunc = RT_MULTI_FUNC_NONE;\n\tvalue32 = rtw_read32(adapter, REG_WL_BT_PWR_CTRL_8822C);\n\thal->MultiFunc |= ((value32 & BIT_WL_FUNC_EN_8822C) ? RT_MULTI_FUNC_WIFI : 0);\n\thal->MultiFunc |= ((value32 & BIT_BT_FUNC_EN_8822C) ? RT_MULTI_FUNC_BT : 0);\n\thal->PolarityCtl = ((value32 & BIT_WL_HWPDN_SL_8822C) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT);\n\n\trtw_hal_config_rftype(adapter);\n\n\tdump_chip_info(hal->version_id);\n}\n\n/*\n * Return:\n *\t_TRUE\tvalid ID\n *\t_FALSE\tinvalid ID\n */\nstatic u8 Hal_EfuseParseIDCode(PADAPTER adapter, u8 *map)\n{\n\tu16 EEPROMId;\n\n\n\t/* Check 0x8129 again for making sure autoload status!! */\n\tEEPROMId = le16_to_cpu(*(u16 *)map);\n\tRTW_INFO(\"EEPROM ID = 0x%04x\\n\", EEPROMId);\n\tif (EEPROMId == RTL_EEPROM_ID)\n\t\treturn _TRUE;\n\n\tRTW_WARN(\"EEPROM ID is invalid!!\\n\");\n\treturn _FALSE;\n}\n\nstatic void Hal_EfuseParseEEPROMVer(PADAPTER adapter, u8 *map, u8 mapvalid)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\n\n\tif (_TRUE == mapvalid)\n\t\thal->EEPROMVersion = map[EEPROM_VERSION_8822C];\n\telse\n\t\thal->EEPROMVersion = 1;\n\n\tRTW_INFO(\"EEPROM Version = %d\\n\", hal->EEPROMVersion);\n}\n\nstatic int Hal_EfuseParseTxPowerInfo(PADAPTER adapter, u8 *map, u8 mapvalid)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tu8 tpt_mode = (map[EEPROM_TX_PWR_CALIBRATE_RATE_8822C] & 0xF0) >> 4;\n\tTxPowerInfo24G tbl2G4;\n\tTxPowerInfo5G tbl5g;\n\tint ret = _FAIL;\n\n\tif (tpt_mode >= 4 && tpt_mode < 7) { /* 4~7: TSSI, TODO */\n\t\tRTW_ERR(\"%s tpt_mode=%u, TSSI is not supported\\n\", __func__, tpt_mode);\n\t\tgoto exit;\n\t}\n\n\thal_load_txpwr_info(adapter, &tbl2G4, &tbl5g, map);\n\n\tif ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8822C] != 0xFF))\n\t\thal->EEPROMRegulatory = map[EEPROM_RF_BOARD_OPTION_8822C] & 0x7; /* bit0~2 */\n\telse\n\t\thal->EEPROMRegulatory = EEPROM_DEFAULT_BOARD_OPTION & 0x7; /* bit0~2 */\n\tRTW_INFO(\"EEPROM Regulatory=0x%02x\\n\", hal->EEPROMRegulatory);\n\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n\nstatic void Hal_EfuseParseBoardType(PADAPTER adapter, u8 *map, u8 mapvalid)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\n\n\tif ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8822C] != 0xFF))\n\t\thal->InterfaceSel = (map[EEPROM_RF_BOARD_OPTION_8822C] & 0xE0) >> 5;\n\telse\n\t\thal->InterfaceSel = (EEPROM_DEFAULT_BOARD_OPTION & 0xE0) >> 5;\n\n\tRTW_INFO(\"EEPROM Board Type=0x%02x\\n\", hal->InterfaceSel);\n}\n\nstatic void Hal_EfuseParseBTCoexistInfo(PADAPTER adapter, u8 *map, u8 mapvalid)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tu8 setting;\n\tu32 tmpu4;\n\n\tif ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8822C] != 0xFF)) {\n\t\t/* 0xc1[7:5] = 0x01 */\n\t\tif (((map[EEPROM_RF_BOARD_OPTION_8822C] & 0xe0) >> 5) == 0x01)\n\t\t\thal->EEPROMBluetoothCoexist = _TRUE;\n\t\telse\n\t\t\thal->EEPROMBluetoothCoexist = _FALSE;\n\t} else\n\t\thal->EEPROMBluetoothCoexist = _FALSE;\n\n\thal->EEPROMBluetoothType = BT_RTL8822C;\n\n\tsetting = map[EEPROM_RF_BT_SETTING_8822C];\n\tif ((_TRUE == mapvalid) && (setting != 0xFF)) {\n\t\thal->EEPROMBluetoothAntNum = setting & BIT(0);\n\t\t/*\n\t\t * EFUSE_0xC3[6] == 0, S1(Main)-RF_PATH_A;\n\t\t * EFUSE_0xC3[6] == 1, S0(Aux)-RF_PATH_B\n\t\t */\n\t\thal->ant_path = (setting & BIT(6)) ? RF_PATH_B : RF_PATH_A;\n\t} else {\n\t\thal->EEPROMBluetoothAntNum = Ant_x2;\n\t\thal->ant_path = RF_PATH_A;\n\t}\n\n#ifdef CONFIG_RTW_8822C_BETA_DEV\n\t\thal->EEPROMBluetoothCoexist = _FALSE;\n\t\thal->EEPROMBluetoothAntNum = Ant_x1;\n\t\thal->ant_path = RF_PATH_A;\n#endif\n\n\tRTW_INFO(\"EEPROM %s BT-coex, ant_num=%d\\n\",\n\t\t hal->EEPROMBluetoothCoexist == _TRUE ? \"Enable\" : \"Disable\",\n\t\t hal->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1);\n}\n\nstatic void Hal_EfuseParseChnlPlan(PADAPTER adapter, u8 *map, u8 autoloadfail)\n{\n\thal_com_config_channel_plan(\n\t\tadapter,\n\t\tmap ? &map[EEPROM_COUNTRY_CODE_8822C] : NULL,\n\t\tmap ? map[EEPROM_ChannelPlan_8822C] : 0xFF,\n\t\tadapter->registrypriv.alpha2,\n\t\tadapter->registrypriv.channel_plan,\n\t\tRTW_CHPLAN_REALTEK_DEFINE,\n\t\tautoloadfail\n\t);\n}\n\nstatic void Hal_EfuseParseXtal(PADAPTER adapter, u8 *map, u8 mapvalid)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\n\n\tif ((_TRUE == mapvalid) && map[EEPROM_XTAL_B9_8822C] != 0xFF)\n\t\thal->crystal_cap = map[EEPROM_XTAL_B9_8822C];\n\telse\n\t\thal->crystal_cap = EEPROM_Default_CrystalCap_B9_8822C;\n\n\tRTW_INFO(\"EEPROM crystal_cap=0x%02x\\n\", hal->crystal_cap);\n}\n\nstatic void Hal_EfuseParseThermalMeter(PADAPTER adapter, u8 *map, u8 mapvalid)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\n\n\t/* ThermalMeter from EEPROM */\n\tif ((_TRUE == mapvalid) && (map[EEPROM_THERMAL_METER_A_8822C] != 0xFF) \\\n\t\t&& (map[EEPROM_THERMAL_METER_B_8822C] != 0xFF)) {\n\t\t/* suggested by James@RF */\n\t\tu8 eeprom_thermal_meter_a = map[EEPROM_THERMAL_METER_A_8822C];\n\t\tu8 eeprom_thermal_meter_b = map[EEPROM_THERMAL_METER_B_8822C];\t\t\n\t\thal->eeprom_thermal_meter = (eeprom_thermal_meter_a + eeprom_thermal_meter_b)/2;\n\t} else {\n\t\thal->eeprom_thermal_meter = EEPROM_Default_ThermalMeter;\n\t\thal->odmpriv.rf_calibrate_info.is_apk_thermal_meter_ignore = _TRUE;\n\t}\n\n\tRTW_INFO(\"EEPROM ThermalMeter=0x%02x\\n\", hal->eeprom_thermal_meter);\n}\n\nstatic void Hal_EfuseParseAntennaDiversity(PADAPTER adapter, u8 *map, u8 mapvalid)\n{\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tstruct registry_priv *registry_par = &adapter->registrypriv;\n\n\n\tif (hal->EEPROMBluetoothAntNum == Ant_x1)\n\t\thal->AntDivCfg = 0;\n\telse {\n\t\tif (registry_par->antdiv_cfg == 2)/* 0:OFF , 1:ON, 2:By EFUSE */\n\t\t\thal->AntDivCfg = 1;\n\t\telse\n\t\t\thal->AntDivCfg = registry_par->antdiv_cfg;\n\t}\n\n\t/* If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead. */\n\tif (registry_par->antdiv_type == 0) {\n\t\thal->TRxAntDivType = map[EEPROM_RFE_OPTION_8822C];\n\t\tif (hal->TRxAntDivType == 0xFF)\n\t\t\thal->TRxAntDivType = S0S1_SW_ANTDIV; /* internal switch S0S1 */\n\t\telse if (hal->TRxAntDivType == 0x10)\n\t\t\thal->TRxAntDivType = S0S1_SW_ANTDIV; /* internal switch S0S1 */\n\t\telse if (hal->TRxAntDivType == 0x11)\n\t\t\thal->TRxAntDivType = S0S1_SW_ANTDIV; /* internal switch S0S1 */\n\t\telse\n\t\t\tRTW_INFO(\"EEPROM efuse[0x%x]=0x%02x is unknown type\\n\",\n\t\t\t\t EEPROM_RFE_OPTION_8723B, hal->TRxAntDivType);\n\t} else\n\t\thal->TRxAntDivType = registry_par->antdiv_type;\n\n\tRTW_INFO(\"EEPROM AntDivCfg=%d, AntDivType=%d\\n\",\n\t\t hal->AntDivCfg, hal->TRxAntDivType);\n#endif /* CONFIG_ANTENNA_DIVERSITY */\n}\n\nstatic void Hal_EfuseParseCustomerID(PADAPTER adapter, u8 *map, u8 mapvalid)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\n\n\tif (_TRUE == mapvalid)\n\t\thal->EEPROMCustomerID = map[EEPROM_CustomID_8822C];\n\telse\n\t\thal->EEPROMCustomerID = 0;\n\tRTW_INFO(\"EEPROM Customer ID=0x%02x\\n\", hal->EEPROMCustomerID);\n}\n\nstatic void Hal_DetectWoWMode(PADAPTER adapter)\n{\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\n\tadapter_to_pwrctl(adapter)->bSupportRemoteWakeup = _TRUE;\n#else /* !(CONFIG_WOWLAN || CONFIG_AP_WOWLAN) */\n\tadapter_to_pwrctl(adapter)->bSupportRemoteWakeup = _FALSE;\n#endif /* !(CONFIG_WOWLAN || CONFIG_AP_WOWLAN) */\n\n\tRTW_INFO(\"EEPROM SupportRemoteWakeup=%d\\n\", adapter_to_pwrctl(adapter)->bSupportRemoteWakeup);\n}\n\nstatic void hal_ReadPAType(PADAPTER adapter, u8 *map, u8 mapvalid)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\n\tif (mapvalid) {\n\t\t/* AUTO */\n\t\tif (GetRegAmplifierType2G(adapter) == 0) {\n\t\t\thal->PAType_2G = ReadLE1Byte(&map[EEPROM_2G_5G_PA_TYPE_8822C]);\n\t\t\thal->LNAType_2G = ReadLE1Byte(&map[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822C]);\n\n\t\t\tif (hal->PAType_2G == 0xFF)\n\t\t\t\thal->PAType_2G = 0;\n\n\t\t\tif (hal->LNAType_2G == 0xFF)\n\t\t\t\thal->LNAType_2G = 0;\n\n\t\t\thal->ExternalPA_2G = (hal->PAType_2G & BIT4) ? 1 : 0;\n\t\t\thal->ExternalLNA_2G = (hal->LNAType_2G & BIT3) ? 1 : 0;\n\t\t} else {\n\t\t\thal->ExternalPA_2G  = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_PA)  ? 1 : 0;\n\t\t\thal->ExternalLNA_2G = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_LNA) ? 1 : 0;\n\t\t}\n\n\t\t/* AUTO */\n\t\tif (GetRegAmplifierType5G(adapter) == 0) {\n\t\t\thal->PAType_5G = ReadLE1Byte(&map[EEPROM_2G_5G_PA_TYPE_8822C]);\n\t\t\thal->LNAType_5G = ReadLE1Byte(&map[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822C]);\n\t\t\tif (hal->PAType_5G == 0xFF)\n\t\t\t\thal->PAType_5G = 0;\n\t\t\tif (hal->LNAType_5G == 0xFF)\n\t\t\t\thal->LNAType_5G = 0;\n\n\t\t\thal->external_pa_5g = (hal->PAType_5G & BIT0) ? 1 : 0;\n\t\t\thal->external_lna_5g = (hal->LNAType_5G & BIT3) ? 1 : 0;\n\t\t} else {\n\t\t\thal->external_pa_5g  = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_PA_5G)  ? 1 : 0;\n\t\t\thal->external_lna_5g = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_LNA_5G) ? 1 : 0;\n\t\t}\n\t} else {\n\t\thal->ExternalPA_2G  = EEPROM_Default_PAType;\n\t\thal->external_pa_5g  = 0xFF;\n\t\thal->ExternalLNA_2G = EEPROM_Default_LNAType;\n\t\thal->external_lna_5g = 0xFF;\n\n\t\t/* AUTO */\n\t\tif (GetRegAmplifierType2G(adapter) == 0) {\n\t\t\thal->ExternalPA_2G  = 0;\n\t\t\thal->ExternalLNA_2G = 0;\n\t\t} else {\n\t\t\thal->ExternalPA_2G  = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_PA)  ? 1 : 0;\n\t\t\thal->ExternalLNA_2G = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_LNA) ? 1 : 0;\n\t\t}\n\n\t\t/* AUTO */\n\t\tif (GetRegAmplifierType5G(adapter) == 0) {\n\t\t\thal->external_pa_5g  = 0;\n\t\t\thal->external_lna_5g = 0;\n\t\t} else {\n\t\t\thal->external_pa_5g  = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_PA_5G)  ? 1 : 0;\n\t\t\thal->external_lna_5g = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_LNA_5G) ? 1 : 0;\n\t\t}\n\t}\n\n\tRTW_INFO(\"EEPROM PAType_2G is 0x%x, ExternalPA_2G = %d\\n\", hal->PAType_2G, hal->ExternalPA_2G);\n\tRTW_INFO(\"EEPROM PAType_5G is 0x%x, external_pa_5g = %d\\n\", hal->PAType_5G, hal->external_pa_5g);\n\tRTW_INFO(\"EEPROM LNAType_2G is 0x%x, ExternalLNA_2G = %d\\n\", hal->LNAType_2G, hal->ExternalLNA_2G);\n\tRTW_INFO(\"EEPROM LNAType_5G is 0x%x, external_lna_5g = %d\\n\", hal->LNAType_5G, hal->external_lna_5g);\n}\n\nstatic void Hal_ReadAmplifierType(PADAPTER adapter, u8 *map, u8 mapvalid)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tu8 extTypePA_2G_A = (map[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822C] & BIT2) >> 2;\n\tu8 extTypePA_2G_B = (map[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822C] & BIT6) >> 6;\n\tu8 extTypePA_5G_A = (map[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822C] & BIT2) >> 2;\n\tu8 extTypePA_5G_B = (map[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822C] & BIT6) >> 6;\n\tu8 extTypeLNA_2G_A = (map[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822C] & (BIT1 | BIT0)) >> 0;\n\tu8 extTypeLNA_2G_B = (map[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822C] & (BIT5 | BIT4)) >> 4;\n\tu8 extTypeLNA_5G_A = (map[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822C] & (BIT1 | BIT0)) >> 0;\n\tu8 extTypeLNA_5G_B = (map[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822C] & (BIT5 | BIT4)) >> 4;\n\n\thal_ReadPAType(adapter, map, mapvalid);\n\n\t/* [2.4G] Path A and B are both extPA */\n\tif ((hal->PAType_2G & (BIT5 | BIT4)) == (BIT5 | BIT4))\n\t\thal->TypeGPA  = extTypePA_2G_B  << 2 | extTypePA_2G_A;\n\n\t/* [5G] Path A and B are both extPA */\n\tif ((hal->PAType_5G & (BIT1 | BIT0)) == (BIT1 | BIT0))\n\t\thal->TypeAPA  = extTypePA_5G_B  << 2 | extTypePA_5G_A;\n\n\t/* [2.4G] Path A and B are both extLNA */\n\tif ((hal->LNAType_2G & (BIT7 | BIT3)) == (BIT7 | BIT3))\n\t\thal->TypeGLNA = extTypeLNA_2G_B << 2 | extTypeLNA_2G_A;\n\n\t/* [5G] Path A and B are both extLNA */\n\tif ((hal->LNAType_5G & (BIT7 | BIT3)) == (BIT7 | BIT3))\n\t\thal->TypeALNA = extTypeLNA_5G_B << 2 | extTypeLNA_5G_A;\n\n\tRTW_INFO(\"EEPROM TypeGPA = 0x%X\\n\", hal->TypeGPA);\n\tRTW_INFO(\"EEPROM TypeAPA = 0x%X\\n\", hal->TypeAPA);\n\tRTW_INFO(\"EEPROM TypeGLNA = 0x%X\\n\", hal->TypeGLNA);\n\tRTW_INFO(\"EEPROM TypeALNA = 0x%X\\n\", hal->TypeALNA);\n}\n\nstatic u8 Hal_ReadRFEType(PADAPTER adapter, u8 *map, u8 mapvalid)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\n\n\t/* check registry value */\n\tif (GetRegRFEType(adapter) != CONFIG_RTW_RFE_TYPE) {\n\t\thal->rfe_type = GetRegRFEType(adapter);\n\t\tgoto exit;\n\t}\n\n\tif (mapvalid) {\n\t\t/* check efuse map */\n\t\thal->rfe_type = ReadLE1Byte(&map[EEPROM_RFE_OPTION_8822C]);\n\t\tif (0xFF != hal->rfe_type)\n\t\t\tgoto exit;\n\t}\n\n\t/* error handle */\n\thal->rfe_type = 0;\n\n\t/* If ignore incorrect rfe_type may cause card drop. */\n\t/* it's DIFFICULT do debug especially on COB project */\n\tRTW_ERR(\"\\n\\nEmpty EFUSE with unknown REF type!!\\n\\n\");\n\tRTW_ERR(\"please program efuse or specify correct RFE type.\\n\");\n\tRTW_ERR(\"cmd: insmod rtl8822cx.ko rtw_RFE_type=<rfe_type>\\n\\n\");\n\n\treturn _FAIL;\n\nexit:\n\tRTW_INFO(\"EEPROM rfe_type=0x%x\\n\", hal->rfe_type);\n\treturn _SUCCESS;\n}\n\nstatic void Hal_EfuseParsePackageType(PADAPTER adapter, u8 *map, u8 mapvalid)\n{\n}\n\nstatic void Hal_EfuseParsePABias(PADAPTER adapter)\n{\n\tstruct hal_com_data *hal;\n\tu8 data[2] = {0xFF, 0xFF};\n\tu8 ret;\n\n\n\tret = rtw_efuse_access(adapter, 0, 0x3D7, 2, data);\n\tif (_FAIL == ret) {\n\t\tRTW_ERR(\"%s: Fail to read PA Bias from eFuse!\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\thal = GET_HAL_DATA(adapter);\n\thal->efuse0x3d7 = data[0];\t/* efuse[0x3D7] */\n\thal->efuse0x3d8 = data[1];\t/* efuse[0x3D8] */\n\n\tRTW_INFO(\"EEPROM efuse[0x3D7]=0x%x\\n\", hal->efuse0x3d7);\n\tRTW_INFO(\"EEPROM efuse[0x3D8]=0x%x\\n\", hal->efuse0x3d8);\n}\n\n\n#ifdef CONFIG_USB_HCI\nstatic void Hal_ReadUsbModeSwitch(PADAPTER adapter, u8 *map, u8 mapvalid)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\n\tif (_TRUE == mapvalid)\n\t\t/* check efuse 0x06 bit7 */\n\t\thal->EEPROMUsbSwitch = (map[EEPROM_USB_MODE_8822CU] & BIT7) >> 7;\n\telse\n\t\thal->EEPROMUsbSwitch = _FALSE;\n\n\tRTW_INFO(\"EEPROM USB Switch=%d\\n\", hal->EEPROMUsbSwitch);\n}\n\nstatic void hal_read_usb_pid_vid(PADAPTER adapter, u8 *map, u8 mapvalid)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\n\tif (_TRUE == mapvalid) {\n\t\t/* VID, PID */\n\t\thal->EEPROMVID = ReadLE2Byte(&map[EEPROM_VID_8822CU]);\n\t\thal->EEPROMPID = ReadLE2Byte(&map[EEPROM_PID_8822CU]);\n\t} else {\n\t\thal->EEPROMVID = EEPROM_Default_VID;\n\t\thal->EEPROMPID = EEPROM_Default_PID;\n\t}\n\n\tRTW_INFO(\"EEPROM VID = 0x%04X, PID = 0x%04X\\n\", hal->EEPROMVID, hal->EEPROMPID);\n}\n\n#endif /* CONFIG_USB_HCI */\n\n#ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY\n#define GET_XCAP_VALUE_B9_8822C(x) (x & 0x7F)\n#define GET_XCAP_VALUE_110_8822C(x) (x & 0x7F)\n#define GET_XCAP_VALUE_111_8822C(x) ((x & 0x7F00) >> 8)\n#define EFUSE_XCAP_VALID_CHK_B9_8822C(x) \\\n\t(!(GET_XCAP_VALUE_B9_8822C(x) == 0x7F))\n#define EFUSE_XCAP_VALID_CHK_110_8822C(x) \\\n\t(!((GET_XCAP_VALUE_110_8822C(x) == EEPROM_Default_CrystalCap_110_8822C) || (GET_XCAP_VALUE_110_8822C(x) == 0x7F)))\n#define EFUSE_XCAP_VALID_CHK_111_8822C(x) \\\n\t(!((GET_XCAP_VALUE_111_8822C(x) == EEPROM_Default_CrystalCap_111_8822C) || (GET_XCAP_VALUE_111_8822C(x) == 0x7F)))\nstatic s16 hal_efuse_search_xtal_cap(PADAPTER adapter, u8 h_xcap_b9, u16 f_xcap_110_111, u8 f_xcap_b9)\n{\n\tenum {\n\t\tXCAP_SRC_H_EFUSE_B9_8822C = 0,\n\t\tXCAP_SRC_F_EFUSE_110_8822C,\n\t\tXCAP_SRC_F_EFUSE_B9_8822C,\n\t\tXCAP_SRC_8822C_MAX\n\t};\n\n\tconst char *const xcap_src_8822c_str[XCAP_SRC_8822C_MAX] = {\n\t\t\"XCAP_SRC_H_EFUSE_B9\",\n\t\t\"XCAP_SRC_F_EFUSE_110\",\n\t\t\"XCAP_SRC_F_EFUSE_B9\"\n\t};\n\n\t/* this declaration also controls the priority while searching xcap value from the candidates, \n\t\tthe prior element in the array implies the higher priority, fill -1 to bypass the element */\n\ts8 xcap_src_8822c[XCAP_SRC_8822C_MAX] = \n\t\t{XCAP_SRC_F_EFUSE_B9_8822C, XCAP_SRC_F_EFUSE_110_8822C, XCAP_SRC_H_EFUSE_B9_8822C};\n\n\tint i = 0;\n\ts8 xcap_found = -1;\n\ts16 xcap_value = -1;\n\n\t/* search for the valid xcap value from candidates */\n\tfor (i = 0; i < XCAP_SRC_8822C_MAX; i++) {\n\t\tswitch (xcap_src_8822c[i]) {\n\t\tcase XCAP_SRC_H_EFUSE_B9_8822C:\n\t\t\tif (EFUSE_XCAP_VALID_CHK_B9_8822C(h_xcap_b9)) {\n\t\t\t\txcap_value = ((GET_XCAP_VALUE_B9_8822C(h_xcap_b9) << 8) | GET_XCAP_VALUE_B9_8822C(h_xcap_b9));\n\t\t\t\txcap_found = XCAP_SRC_H_EFUSE_B9_8822C;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase XCAP_SRC_F_EFUSE_110_8822C:\n\t\t\tif ((EFUSE_XCAP_VALID_CHK_110_8822C(f_xcap_110_111 )) && (EFUSE_XCAP_VALID_CHK_111_8822C(f_xcap_110_111 ))) {\n\t\t\t\txcap_value = (f_xcap_110_111 & 0x7F7F);\n\t\t\t\txcap_found = XCAP_SRC_F_EFUSE_110_8822C;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase XCAP_SRC_F_EFUSE_B9_8822C:\n\t\t\tif (EFUSE_XCAP_VALID_CHK_B9_8822C(f_xcap_b9)) {\n\t\t\t\txcap_value = ((GET_XCAP_VALUE_B9_8822C(f_xcap_b9) << 8) | GET_XCAP_VALUE_B9_8822C(f_xcap_b9));\n\t\t\t\txcap_found = XCAP_SRC_F_EFUSE_B9_8822C;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase -1:\n\t\t\tbreak;\n\t\t}\n\n\t\tif (xcap_found >= 0)\n\t\t\tbreak;\n\t}\n\n\tif (xcap_found == -1)\n\t\tRTW_INFO(\"valid crystall_cap value is not found in all sources!\\n\");\n\telse\n\t\tRTW_INFO(\"valid crystal_cap value 0x%04X is found in %s!\\n\", xcap_value, xcap_src_8822c_str[xcap_found]);\n\n\treturn xcap_value;\n}\n\nstatic void hal_efuse_parse_xtal_cap_new(PADAPTER adapter, u16 h_xcap_110_111, u8 h_xcap_b9, \n\tu16 f_xcap_110_111, u8 f_xcap_b9, u8 mapvalid)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\ts16 xcap_value = -1;\n\tu16 xcap_value_to_h_efuse = 0;\n\n\tif (mapvalid == _FALSE) {\n\t\thal->crystal_cap = EEPROM_Default_CrystalCap_110_8822C;\n\t\tgoto exit;\n\t}\n\n\tif (adapter->registrypriv.rtw_8822c_xcap_overwrite == 1) {\n\t\txcap_value = hal_efuse_search_xtal_cap(adapter, h_xcap_b9, f_xcap_110_111, f_xcap_b9);\n\t\tif (xcap_value != -1) {\n\t\t\tif (xcap_value != (h_xcap_110_111 & 0x7F7F)) {\n\t\t\t\txcap_value_to_h_efuse = ((h_xcap_110_111 & 0x8080) | xcap_value);\n\t\t\t\trtw_efuse_map_write(adapter, EEPROM_XTAL_110_8822C, 2, (u8*)&xcap_value_to_h_efuse);\n\t\t\t\tRTW_INFO(\"update crystal_cap = 0x%02X into hw efuse!\\n\", xcap_value);\n\t\t\t}\n\n\t\t\thal->crystal_cap = GET_XCAP_VALUE_110_8822C(xcap_value);\n\t\t}\n\t\telse {\n\t\t\tif ((EFUSE_XCAP_VALID_CHK_110_8822C(h_xcap_110_111)) && (EFUSE_XCAP_VALID_CHK_111_8822C(h_xcap_110_111)))\n\t\t\t\thal->crystal_cap = GET_XCAP_VALUE_110_8822C(h_xcap_110_111);\n\t\t\telse\n\t\t\t\thal->crystal_cap = EEPROM_Default_CrystalCap_110_8822C;\n\t\t}\n\t}\n\telse {\n\t\t\tif ((EFUSE_XCAP_VALID_CHK_110_8822C(h_xcap_110_111)) && (EFUSE_XCAP_VALID_CHK_111_8822C(h_xcap_110_111)))\n\t\t\t\thal->crystal_cap = GET_XCAP_VALUE_110_8822C(h_xcap_110_111);\n\t\t\telse {\n\t\t\t\txcap_value = hal_efuse_search_xtal_cap(adapter, h_xcap_b9, f_xcap_110_111, f_xcap_b9);\n\t\t\t\tif (xcap_value != -1) {\n\t\t\t\t\txcap_value_to_h_efuse = ((h_xcap_110_111 & 0x8080) | xcap_value);\n\t\t\t\t\trtw_efuse_map_write(adapter, EEPROM_XTAL_110_8822C, 2, (u8*)&xcap_value_to_h_efuse);\n\t\t\t\t\tRTW_INFO(\"update crystal_cap = 0x%02X into hw efuse!\\n\", xcap_value);\n\t\t\t\t\thal->crystal_cap = GET_XCAP_VALUE_110_8822C(xcap_value);\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t\thal->crystal_cap = EEPROM_Default_CrystalCap_110_8822C;\n\t\t\t}\n\t}\n\nexit:\n\tRTW_INFO(\"EEPROM crystal_cap=0x%02x\\n\", hal->crystal_cap);\n\n}\n#endif\n\n/*\n * Description:\n *\tCollect all information from efuse or files.\n *\tThis function will do\n *\t1. Read registers to check hardware efuse available or not\n *\t2. Read Efuse/EEPROM\n *\t3. Read file if necessary\n *\t4. Parsing Efuse data\n */\nu8 rtl8822c_read_efuse(PADAPTER adapter)\n{\n\tPHAL_DATA_TYPE hal;\n\tu8 val8;\n\tu8 *efuse_map = NULL;\n\tu8 valid;\n#ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY\n\tu8 h_efuse_xcap_b9 = 0xFF;\n\tu16 h_efuse_xcap_110_111 = 0xFFFF;\n\tu8 f_efuse_xcap_b9 = 0xFF;\n\tu16 f_efuse_xcap_110_111 = 0xFFFF;\n#endif\n\tu8 ret = _FAIL;\n\n\thal = GET_HAL_DATA(adapter);\n\tefuse_map = hal->efuse_eeprom_data;\n\n\t/* 1. Read registers to check hardware eFuse available or not */\n\tval8 = rtw_read8(adapter, REG_SYS_EEPROM_CTRL_8822C);\n\thal->EepromOrEfuse = (val8 & BIT_EERPOMSEL_8822C) ? _TRUE : _FALSE;\n\thal->bautoload_fail_flag = (val8 & BIT_AUTOLOAD_SUS_8822C) ? _FALSE : _TRUE;\n\t/*\n\t * In 8822C, bautoload_fail_flag is used to present eFuse map is valid\n\t * or not, no matter the map comes from hardware or files.\n\t */\n\n\t/* 2. Read eFuse */\n\tEFUSE_ShadowMapUpdate(adapter, EFUSE_WIFI, 0);\n\n#ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY\n\th_efuse_xcap_b9 = efuse_map[EEPROM_XTAL_B9_8822C];\n\th_efuse_xcap_110_111 = ((efuse_map[EEPROM_XTAL_111_8822C] << 8) | efuse_map[EEPROM_XTAL_110_8822C]);\n#endif\n\n\t/* 3. Read Efuse file if necessary */\n#ifdef CONFIG_EFUSE_CONFIG_FILE\n\tif (check_phy_efuse_tx_power_info_valid(adapter) == _FALSE) {\n\t\tif (Hal_readPGDataFromConfigFile(adapter) != _SUCCESS)\n\t\t\tRTW_WARN(\"%s: invalid phy efuse and read from file fail, will use driver default!!\\n\", __FUNCTION__);\n#ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY\n\t\telse {\n\t\t\tf_efuse_xcap_b9 = efuse_map[EEPROM_XTAL_B9_8822C];\n\t\t\tf_efuse_xcap_110_111 = ((efuse_map[EEPROM_XTAL_111_8822C] << 8) | efuse_map[EEPROM_XTAL_110_8822C]);\n\t\t}\n#endif\n\t}\n#endif /* CONFIG_EFUSE_CONFIG_FILE */\n\n\t/* 4. Parse Efuse data */\n\tvalid = Hal_EfuseParseIDCode(adapter, efuse_map);\n\tif (_TRUE == valid)\n\t\thal->bautoload_fail_flag = _FALSE;\n\telse\n\t\thal->bautoload_fail_flag = _TRUE;\n\n\tHal_EfuseParseEEPROMVer(adapter, efuse_map, valid);\n\thal_config_macaddr(adapter, hal->bautoload_fail_flag);\n\tif (Hal_EfuseParseTxPowerInfo(adapter, efuse_map, valid) != _SUCCESS)\n\t\tgoto exit;\n\tHal_EfuseParseBoardType(adapter, efuse_map, valid);\n\tHal_EfuseParseBTCoexistInfo(adapter, efuse_map, valid);\n\tHal_EfuseParseChnlPlan(adapter, efuse_map, hal->bautoload_fail_flag);\n#ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY\n\tif ((adapter->registrypriv.mp_mode == 0) && (hal->EEPROMBluetoothCoexist == _TRUE))\n\t\thal_efuse_parse_xtal_cap_new(adapter, h_efuse_xcap_110_111, h_efuse_xcap_b9, f_efuse_xcap_110_111, f_efuse_xcap_b9, valid);\n\telse\n#else\n\tHal_EfuseParseXtal(adapter, efuse_map, valid);\n#endif\n\tHal_EfuseParseThermalMeter(adapter, efuse_map, valid);\n\tHal_EfuseParseAntennaDiversity(adapter, efuse_map, valid);\n\tHal_EfuseParseCustomerID(adapter, efuse_map, valid);\n\tHal_DetectWoWMode(adapter);\n\tHal_ReadAmplifierType(adapter, efuse_map, valid);\n\tif (Hal_ReadRFEType(adapter, efuse_map, valid) != _SUCCESS)\n\t\tgoto exit;\n\n\t/* Data out of Efuse Map */\n\tHal_EfuseParsePackageType(adapter, efuse_map, valid);\n\t/* Hal_EfuseParsePABias(adapter); */\n\n#ifdef CONFIG_USB_HCI\n\tHal_ReadUsbModeSwitch(adapter, efuse_map, valid);\n\thal_read_usb_pid_vid(adapter, efuse_map, valid);\n#endif /* CONFIG_USB_HCI */\n\n\t/* set coex. ant info once efuse parsing is done */\n\trtw_btcoex_set_ant_info(adapter);\n\n\thal_read_mac_hidden_rpt(adapter);\n\t{\n\t\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\n\t\tif (hal_spec->hci_type <= 3 && hal_spec->hci_type >= 1) {\n\t\t\thal->EEPROMBluetoothCoexist = _FALSE;\n\t\t\tRTW_INFO(\"EEPROM Disable BT-coex by hal_spec\\n\");\n\t\t\trtw_btcoex_wifionly_AntInfoSetting(adapter);\n\t\t}\n\t}\n\n\trtw_phydm_read_efuse(adapter);\n\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n\nvoid rtl8822c_run_thread(PADAPTER adapter)\n{\n}\n\nvoid rtl8822c_cancel_thread(PADAPTER adapter)\n{\n}\n\n/*\n * Description:\n *\tUsing 0x100 to check the power status of FW.\n */\nstatic u8 check_ips_status(PADAPTER adapter)\n{\n\tu8 val8;\n\n\n\tRTW_INFO(FUNC_ADPT_FMT \": Read 0x100=0x%02x 0x86=0x%02x\\n\",\n\t\t FUNC_ADPT_ARG(adapter),\n\t\t rtw_read8(adapter, 0x100), rtw_read8(adapter, 0x86));\n\n\tval8 = rtw_read8(adapter, 0x100);\n\tif (val8 == 0xEA)\n\t\treturn _TRUE;\n\n\treturn _FALSE;\n}\n\nstatic void InitBeaconParameters(PADAPTER adapter)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tu16 val16;\n\tu8 val8;\n\n\n\tval8 = BIT_DIS_TSF_UDT_8822C;\n\tval16 = val8 | (val8 << 8); /* port0 and port1 */\n#ifdef CONFIG_BT_COEXIST\n\tif (hal->EEPROMBluetoothCoexist)\n\t\t/* Enable port0 beacon function for PSTDMA under BTCOEX */\n\t\tval16 |= EN_BCN_FUNCTION;\n#endif\n\trtw_write16(adapter, REG_BCN_CTRL_8822C, val16);\n\n\t/* TBTT setup time */\n\trtw_write8(adapter, REG_TBTT_PROHIBIT_8822C, TBTT_PROHIBIT_SETUP_TIME);\n\n\t/* TBTT hold time: 0x540[19:8] */\n\trtw_write8(adapter, REG_TBTT_PROHIBIT_8822C + 1, TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);\n\trtw_write8(adapter, REG_TBTT_PROHIBIT_8822C + 2,\n\t\t(rtw_read8(adapter, REG_TBTT_PROHIBIT_8822C + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8));\n\n\trtw_write8(adapter, REG_DRVERLYINT_8822C, DRIVER_EARLY_INT_TIME_8822C); /* 5ms */\n\trtw_write8(adapter, REG_BCNDMATIM_8822C, BCN_DMA_ATIME_INT_TIME_8822C); /* 2ms */\n\n\t/*\n\t * Suggested by designer timchen. Change beacon AIFS to the largest number\n\t * beacause test chip does not contension before sending beacon.\n\t */\n\trtw_write16(adapter, REG_BCNTCFG_8822C, 0x4413);\n}\n\nstatic void beacon_function_enable(PADAPTER adapter, u8 Enable, u8 Linked)\n{\n\tu8 val8;\n\tu32 bcn_ctrl_reg;\n\n\t/* port0 */\n\tbcn_ctrl_reg = REG_BCN_CTRL_8822C;\n\tval8  = BIT_DIS_TSF_UDT_8822C | BIT_EN_BCN_FUNCTION_8822C;\n#ifdef CONFIG_CONCURRENT_MODE\n\t/* port1 */\n\tif (adapter->hw_port == HW_PORT1) {\n\t\tbcn_ctrl_reg = REG_BCN_CTRL_CLINT0_8822C;\n\t\tval8 = BIT_CLI0_DIS_TSF_UDT_8822C | BIT_CLI0_EN_BCN_FUNCTION_8822C;\n\t}\n#endif\n\n\trtw_write8(adapter, bcn_ctrl_reg, val8);\n\trtw_write8(adapter, REG_RD_CTRL_8822C + 1, 0x6F);\n}\n\nstatic void set_beacon_related_registers(PADAPTER adapter)\n{\n\tu8 val8;\n\tu32 value32;\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;\n\tu32 bcn_ctrl_reg, bcn_interval_reg;\n\n\n\t/* reset TSF, enable update TSF, correcting TSF On Beacon */\n\t/*\n\t * REG_MBSSID_BCN_SPACE\n\t * REG_BCNDMATIM\n\t * REG_ATIMWND\n\t * REG_TBTT_PROHIBIT\n\t * REG_DRVERLYINT\n\t * REG_BCN_MAX_ERR\n\t * REG_BCNTCFG (0x510)\n\t * REG_DUAL_TSF_RST\n\t * REG_BCN_CTRL (0x550)\n\t */\n\n\tbcn_ctrl_reg = REG_BCN_CTRL_8822C;\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (adapter->hw_port == HW_PORT1)\n\t\tbcn_ctrl_reg = REG_BCN_CTRL_CLINT0_8822C;\n#endif\n\n\t/*\n\t * ATIM window\n\t */\n\trtw_write16(adapter, REG_ATIMWND_8822C, 2);\n\n\t/*\n\t * Beacon interval (in unit of TU).\n\t */\n\trtw_hal_set_hwreg(adapter, HW_VAR_BEACON_INTERVAL, (u8 *)&pmlmeinfo->bcn_interval);\n\n\tInitBeaconParameters(adapter);\n\n\trtw_write8(adapter, REG_SLOT_8822C, 0x09);\n\n\t/* Reset TSF Timer to zero */\n\tval8 = BIT_TSFTR_RST_8822C;\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (adapter->hw_port == HW_PORT1)\n\t\tval8 = BIT_TSFTR_CLI0_RST_8822C;\n#endif\n\trtw_write8(adapter, REG_DUAL_TSF_RST_8822C, val8);\n\tval8 = BIT_TSFTR_RST_8822C;\n\trtw_write8(adapter, REG_DUAL_TSF_RST_8822C, val8);\n\n\trtw_write8(adapter, REG_RXTSF_OFFSET_CCK_8822C, 0x50);\n\trtw_write8(adapter, REG_RXTSF_OFFSET_OFDM_8822C, 0x50);\n\n\tbeacon_function_enable(adapter, _TRUE, _TRUE);\n\n\tResumeTxBeacon(adapter);\n}\n\n#ifdef DBG_CONFIG_ERROR_DETECT\nstatic void xmit_status_check(PADAPTER p)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(p);\n\tstruct sreset_priv *psrtpriv = &hal->srestpriv;\n\tstruct xmit_priv *pxmitpriv = &p->xmitpriv;\n\tsystime current_time = 0;\n\tunsigned int diff_time = 0;\n\tu32 txdma_status = 0;\n\n\ttxdma_status = rtw_read32(p, REG_TXDMA_STATUS_8822C);\n\tif (txdma_status != 0x00) {\n\t\tRTW_INFO(\"%s REG_TXDMA_STATUS:0x%08x\\n\", __FUNCTION__, txdma_status);\n\t\tpsrtpriv->tx_dma_status_cnt++;\n\t\tpsrtpriv->self_dect_case = 4;\n\t\trtw_hal_sreset_reset(p);\n\t}\n#ifdef CONFIG_USB_HCI\n\tcurrent_time = rtw_get_current_time();\n\n\tif (0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {\n\t\tdiff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time);\n\n\t\tif (diff_time > 2000) {\n\t\t\tif (psrtpriv->last_tx_complete_time == 0)\n\t\t\t\tpsrtpriv->last_tx_complete_time = current_time;\n\t\t\telse {\n\t\t\t\tdiff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time);\n\t\t\t\tif (diff_time > 4000) {\n\t\t\t\t\tu32 ability = 0;\n\n\t\t\t\t\tability = rtw_phydm_ability_get(p);\n\n\t\t\t\t\tRTW_INFO(\"%s tx hang %s\\n\", __FUNCTION__,\n\t\t\t\t\t\t(ability & ODM_BB_ADAPTIVITY) ? \"ODM_BB_ADAPTIVITY\" : \"\");\n\n\t\t\t\t\tif (!(ability & ODM_BB_ADAPTIVITY)) {\n\t\t\t\t\t\tpsrtpriv->self_dect_tx_cnt++;\n\t\t\t\t\t\tpsrtpriv->self_dect_case = 1;\n\t\t\t\t\t\trtw_hal_sreset_reset(p);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\t}\n#endif /* CONFIG_USB_HCI */\n\n\tif (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) {\n\t\tpsrtpriv->dbg_trigger_point = SRESET_TGP_NULL;\n\t\trtw_hal_sreset_reset(p);\n\t\treturn;\n\t}\n}\n\n#ifdef CONFIG_USB_HCI\nstatic void check_rx_count(PADAPTER p)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(p);\n\tstruct sreset_priv *psrtpriv = &hal->srestpriv;\n\tu16 cur_mac_rxff_ptr;\n\n\tcur_mac_rxff_ptr = rtw_read16(p, REG_RXFF_PTR_V1_8822C);\n\n#if 0\n\tRTW_INFO(\"%s,psrtpriv->last_mac_rxff_ptr = %d , cur_mac_rxff_ptr = %d\\n\", __func__, psrtpriv->last_mac_rxff_ptr, cur_mac_rxff_ptr);\n#endif\n\n\tif (psrtpriv->last_mac_rxff_ptr == cur_mac_rxff_ptr) {\n\t\tpsrtpriv->rx_cnt++;\n#if 0\n\t\tRTW_INFO(\"%s,MAC case rx_cnt=%d\\n\", __func__, psrtpriv->rx_cnt);\n#endif\n\t\tgoto exit;\n\t}\n\n\tpsrtpriv->rx_cnt = 0;\n\nexit:\n\n\tpsrtpriv->last_mac_rxff_ptr = cur_mac_rxff_ptr;\n\n\tif (psrtpriv->rx_cnt > 3) {\n\t\tpsrtpriv->self_dect_case = 2;\n\t\tpsrtpriv->self_dect_rx_cnt++;\n\t\trtw_hal_sreset_reset(p);\n\t}\n}\n#endif/*#ifdef CONFIG_USB_HCI*/\n\nstatic void linked_status_check(PADAPTER p)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(p);\n\tstruct sreset_priv *psrtpriv = &hal->srestpriv;\n\tstruct\tpwrctrl_priv *pwrpriv = adapter_to_pwrctl(p);\n\tu32 rx_dma_status = 0;\n\n\trx_dma_status = rtw_read32(p, REG_RXDMA_STATUS_8822C);\n\tif (rx_dma_status != 0x00) {\n\t\tRTW_INFO(\"%s REG_RXDMA_STATUS:0x%08x\\n\", __FUNCTION__, rx_dma_status);\n\t\tpsrtpriv->rx_dma_status_cnt++;\n\t\tpsrtpriv->self_dect_case = 5;\n#ifdef CONFIG_USB_HCI\n\t\trtw_hal_sreset_reset(p);\n#endif /* CONFIG_USB_HCI */\n\t}\n\n\tif (psrtpriv->self_dect_fw) {\n\t\tpsrtpriv->self_dect_case = 3;\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)\n\t\trtw_hal_sreset_reset(p);\n#endif /* CONFIG_USB_HCI || CONFIG_PCI_HCI */\n\t}\n\n#ifdef CONFIG_USB_HCI\n\tcheck_rx_count(p);\n#endif /* CONFIG_USB_HCI */\n\n\tif (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {\n\t\tpsrtpriv->dbg_trigger_point = SRESET_TGP_NULL;\n\t\trtw_hal_sreset_reset(p);\n\t\treturn;\n\t}\n}\n#endif /* DBG_CONFIG_ERROR_DETECT */\n\nstatic void set_opmode_monitor(PADAPTER adapter)\n{\n\tu32 rcr_bits;\n\tu16 value_rxfltmap2;\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\n\n\t/* Receive all type */\n\trcr_bits = BIT_AAP_8822C | BIT_APM_8822C | BIT_AM_8822C\n\t\t   | BIT_AB_8822C | BIT_APWRMGT_8822C\n\t\t   | BIT_APP_PHYSTS_8822C;\n\n#ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL\n\t/* Append FCS */\n\trcr_bits |= BIT_APP_FCS_8822C;\n#endif\n\n\trtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&GET_HAL_DATA(adapter)->rcr_backup);\n\trtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr_bits);\n\n\t/* Receive all data frames */\n\tvalue_rxfltmap2 = 0xFFFF;\n\trtw_write16(adapter, REG_RXFLTMAP2_8822C, value_rxfltmap2);\n}\n\nstatic void set_opmode_port0(PADAPTER adapter, u8 mode)\n{\n\tu8 is_tx_bcn;\n\tu8 val8;\n\tu16 val16;\n\tu32 val32;\n\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tis_tx_bcn = rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter);\n#else /* !CONFIG_CONCURRENT_MODE */\n\tis_tx_bcn = 0;\n#endif /* !CONFIG_CONCURRENT_MODE */\n\n\t/* disable Port0 TSF update */\n\trtw_iface_disable_tsf_update(adapter);\n\n\tSet_MSR(adapter, mode);\n\n\tRTW_INFO(FUNC_ADPT_FMT \": hw_port(%d) mode=%d\\n\",\n\t\t FUNC_ADPT_ARG(adapter), adapter->hw_port, mode);\n\n\tswitch (mode) {\n\tcase _HW_STATE_NOLINK_:\n\tcase _HW_STATE_STATION_:\n\t\tif (!is_tx_bcn) {\n\t\t\tStopTxBeacon(adapter);\n#ifdef CONFIG_PCI_HCI\n\t\t\tUpdateInterruptMask8822CE(adapter, 0, 0, RT_BCN_INT_MASKS, 0);\n#endif /* CONFIG_PCI_HCI */\n\t\t}\n\n\t\t/* disable beacon function */\n\t\tval8 = BIT_DIS_TSF_UDT_8822C | BIT_EN_BCN_FUNCTION_8822C;\n\t\trtw_write8(adapter, REG_BCN_CTRL_8822C, val8);\n\n\t\t/* disable atim wnd(only for Port0) */\n\t\tval8 = rtw_read8(adapter, REG_DIS_ATIM_8822C);\n\t\tval8 |= BIT_DIS_ATIM_ROOT_8822C;\n\t\trtw_write8(adapter, REG_DIS_ATIM_8822C, val8);\n\t\tbreak;\n\n\tcase _HW_STATE_ADHOC_:\n\t\tResumeTxBeacon(adapter);\n\t\tval8 = BIT_DIS_TSF_UDT_8822C | BIT_EN_BCN_FUNCTION_8822C;\n\t\trtw_write8(adapter, REG_BCN_CTRL_8822C, val8);\n\t\tbreak;\n\n\tcase _HW_STATE_AP_:\n#ifdef CONFIG_PCI_HCI\n\t\tUpdateInterruptMask8822CE(adapter, RT_BCN_INT_MASKS, 0, 0, 0);\n#endif /* CONFIG_PCI_HCI */\n\n\t\t/*\n\t\t * enable BCN0 Function for if1\n\t\t * disable update TSF0 for if1\n\t\t * enable TX BCN report:\n\t\t * Reg REG_FWHW_TXQ_CTRL_8822C [2] = 1\n\t\t * Reg REG_BCN_CTRL_8822C[3][5] = 1\n\t\t * Enable ATIM\n\t\t * Enable HW seq for BCN\n\t\t */\n\t\t/* enable TX BCN report */\n\t\t/* disable RX BCN report */\n\t\tval8 = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8822C);\n\t\tval8 |= BIT_EN_BCN_TRXRPT_V1_8822C;\n\t\trtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822C, val8);\n\n\t\t/* enable BCN0 Function */\n\t\tval8 = rtw_read8(adapter, REG_BCN_CTRL_8822C);\n\t\tval8 |= BIT_EN_BCN_FUNCTION_8822C | BIT_DIS_TSF_UDT_8822C | BIT_P0_EN_TXBCN_RPT_8822C;\n\t\tval8 &= (~BIT_P0_EN_RXBCN_RPT_8822C);\n\t\trtw_write8(adapter, REG_BCN_CTRL_8822C, val8);\n\n\t\t/* Enable ATIM */\n\t\tval8 = rtw_read8(adapter, REG_DIS_ATIM_8822C);\n\t\tval8 &= ~BIT_DIS_ATIM_ROOT_8822C;\n\t\trtw_write8(adapter, REG_DIS_ATIM_8822C, val8);\n\n\t\t/* Enable HW seq for BCN\n\t\t\t0x4FC[0]: EN_HWSEQ\n=\t\t\t0x4FC[1]: EN_HWSEQEXT\n\t\t\tAccording TX desc\n\t\t*/\n\t\trtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822C, 0x01);\n\n\t\t/* enable to rx data frame */\n\t\trtw_write16(adapter, REG_RXFLTMAP2_8822C, 0xFFFF);\n\t\t/* enable to rx ps-poll */\n\t\tval16 = rtw_read16(adapter, REG_RXFLTMAP1_8822C);\n\t\tval16 |= BIT_CTRLFLT10EN_8822C;\n\t\trtw_write16(adapter, REG_RXFLTMAP1_8822C, val16);\n\n\t\t/* Beacon Control related register for first time */\n\t\trtw_write8(adapter, REG_BCNDMATIM_8822C, 0x02); /* 2ms */\n\n\t\trtw_write8(adapter, REG_ATIMWND_8822C, 0x0c); /* 12ms */\n\n\n\t\trtw_write16(adapter, REG_TSFTR_SYN_OFFSET_8822C, 0x7fff); /* +32767 (~32ms) */\n\n\t\t/* reset TSF */\n\t\trtw_write8(adapter, REG_DUAL_TSF_RST_8822C, BIT_TSFTR_RST_8822C);\n\n\t\t/* SW_BCN_SEL - Port0 */\n\t\trtw_hal_set_hwreg(adapter, HW_VAR_DL_BCN_SEL, NULL);\n\n\t\t/* select BCN on port 0 */\n\t\tval8 = rtw_read8(adapter, REG_CCK_CHECK_8822C);\n\t\tval8 &= ~BIT_BCN_PORT_SEL_8822C;\n\t\trtw_write8(adapter, REG_CCK_CHECK_8822C, val8);\n\t\tbreak;\n\t}\n}\n\nstatic void set_opmode_port1(PADAPTER adapter, u8 mode)\n{\n#ifdef CONFIG_CONCURRENT_MODE\n\tu8 is_tx_bcn;\n\tu8 val8;\n\n\tis_tx_bcn = rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter);\n\n\t/* disable Port1 TSF update */\n\trtw_iface_disable_tsf_update(adapter);\n\n\tSet_MSR(adapter, mode);\n\n\tRTW_INFO(FUNC_ADPT_FMT \": hw_port(%d) mode=%d\\n\",\n\t\t FUNC_ADPT_ARG(adapter), adapter->hw_port, mode);\n\n\tswitch (mode) {\n\tcase _HW_STATE_NOLINK_:\n\tcase _HW_STATE_STATION_:\n\t\tif (!is_tx_bcn) {\n\t\t\tStopTxBeacon(adapter);\n#ifdef CONFIG_PCI_HCI\n\t\t\tUpdateInterruptMask8822CE(adapter, 0, 0, RT_BCN_INT_MASKS, 0);\n#endif /* CONFIG_PCI_HCI */\n\t\t}\n\n\t\t/* disable beacon function */\n\t\tval8 = BIT_CLI0_DIS_TSF_UDT_8822C | BIT_CLI0_EN_BCN_FUNCTION_8822C;\n\t\trtw_write8(adapter, REG_BCN_CTRL_CLINT0_8822C, val8);\n\t\tbreak;\n\n\tcase _HW_STATE_ADHOC_:\n\t\tResumeTxBeacon(adapter);\n\t\tval8 = BIT_CLI0_DIS_TSF_UDT_8822C | BIT_CLI0_EN_BCN_FUNCTION_8822C;\n\t\trtw_write8(adapter, REG_BCN_CTRL_CLINT0_8822C, val8);\n\t\tbreak;\n\n\tcase _HW_STATE_AP_:\n#ifdef CONFIG_PCI_HCI\n\t\tUpdateInterruptMask8822CE(adapter, RT_BCN_INT_MASKS, 0, 0, 0);\n#endif /* CONFIG_PCI_HCI */\n\n\t\t/* ToDo */\n\t\tbreak;\n\t}\n#endif /* CONFIG_CONCURRENT_MODE */\n}\nvoid hw_tsf_reset(_adapter *adapter)\n{\n\tu8 hw_port = rtw_hal_get_port(adapter);\n\tu32 tsf_rst_addr = 0;\n\tu8 tsf_rst_bit = 0;\n\n\tif (hw_port >= MAX_HW_PORT) {\n\t\tRTW_ERR(FUNC_ADPT_FMT\" HW Port(%d) invalid\\n\", FUNC_ADPT_ARG(adapter), hw_port);\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\ttsf_rst_addr = port_cfg[hw_port].tsf_rst;\n\ttsf_rst_bit = port_cfg[hw_port].tsf_rst_bit;\n\trtw_write8(adapter, tsf_rst_addr, tsf_rst_bit);\n}\nvoid hw_set_ta(_adapter *adapter, u8 hw_port, u8 *val)\n{\n\tu8 idx = 0;\n\tu32 reg = port_cfg[hw_port].ta;\n\n\tfor (idx = 0 ; idx < ETH_ALEN; idx++)\n\t\trtw_write8(adapter, (reg + idx), val[idx]);\n\n\tRTW_INFO(\"%s(\"ADPT_FMT\") hw port -%d TA: \"MAC_FMT\"\\n\",\n\t\t__func__, ADPT_ARG(adapter), hw_port, MAC_ARG(val));\n}\nvoid hw_set_aid(_adapter *adapter, u8 hw_port, u8 aid)\n{\n\trtw_write16(adapter, port_cfg[hw_port].ps_aid, (0xF800 | aid));\n\tRTW_INFO(\"%s(\"ADPT_FMT\") hw port -%d AID: %d\\n\",\n\t\t\t__func__, ADPT_ARG(adapter), hw_port, aid);\n}\n#ifdef CONFIG_CLIENT_PORT_CFG\nvoid rtw_hw_client_port_cfg(_adapter *adapter)\n{\n\tstruct mlme_ext_priv\t*pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8 clt_port = get_clt_port(adapter);\n\n\tif (clt_port == CLT_PORT_INVALID)\n\t\treturn;\n\tRTW_INFO(\"%s (\"ADPT_FMT\")\\n\", __func__, ADPT_ARG(adapter));\n\n\t/*Network type*/\n\trtw_halmac_set_network_type(adapter_to_dvobj(adapter), clt_port, _HW_STATE_STATION_);\n\t/*A1*/\n\trtw_halmac_set_mac_address(adapter_to_dvobj(adapter), clt_port, adapter_mac_addr(adapter));\n\t/*A2*/\n\thw_set_ta(adapter, clt_port, pmlmeinfo->network.MacAddress);\n\t/*A3*/\n\trtw_halmac_set_bssid(adapter_to_dvobj(adapter), clt_port, pmlmeinfo->network.MacAddress);\n\t/*Beacon space*/\n\trtw_halmac_set_bcn_interval(adapter_to_dvobj(adapter), clt_port, pmlmeinfo->bcn_interval);\n\t/*AID*/\n\thw_set_aid(adapter, clt_port, pmlmeinfo->aid);\n\t/*Beacon control*/\n\thw_bcn_ctrl_set(adapter, clt_port, (BIT_P0_EN_RXBCN_RPT | BIT_EN_BCN_FUNCTION));\n\n\tRTW_INFO(\"%s (\"ADPT_FMT\") clt_port:%d\\n\", __func__, ADPT_ARG(adapter), clt_port);\n}\n\n/*#define DBG_TSF_MONITOR*/\nvoid rtw_hw_client_port_clr(_adapter *adapter)\n{\n\tu8 null_addr[ETH_ALEN] = {0};\n\tu8 clt_port = get_clt_port(adapter);\n\n\tif (clt_port == CLT_PORT_INVALID)\n\t\treturn;\n\tRTW_INFO(\"%s (\"ADPT_FMT\") ==> \\n\", __func__, ADPT_ARG(adapter));\n\n\t#ifdef DBG_TSF_MONITOR\n\t/*Beacon control*/\n\thw_bcn_ctrl_clr(adapter, clt_port, BIT_EN_BCN_FUNCTION);\n\thw_tsf_reset(adapter);\n\t#endif\n\n\t/*Network type*/\n\trtw_halmac_set_network_type(adapter_to_dvobj(adapter), clt_port, _HW_STATE_NOLINK_);\n\t/*A1*/\n\trtw_halmac_set_mac_address(adapter_to_dvobj(adapter), clt_port, null_addr);\n\t/*A2*/\n\thw_set_ta(adapter, clt_port, null_addr);\n\t/*A3*/\n\trtw_halmac_set_bssid(adapter_to_dvobj(adapter), clt_port, null_addr);\n\n\t#ifdef DBG_TSF_MONITOR\n\tif (0)\n\t#endif\n\t/*Beacon control*/\n\thw_bcn_ctrl_set(adapter, clt_port, (BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION));\n\n\t/*AID*/\n\thw_set_aid(adapter, clt_port, 0);\n\tRTW_INFO(\"%s(\"ADPT_FMT\") clt_port:%d\\n\", __func__, ADPT_ARG(adapter), clt_port);\n}\n#endif\n\nstatic void hw_var_set_opmode(PADAPTER adapter, u8 mode)\n{\n\tu8 val8;\n\tstatic u8 isMonitor = _FALSE;\n\n\n\tif (isMonitor == _TRUE) {\n\t\t/* reset RCR from backup */\n\t\trtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&GET_HAL_DATA(adapter)->rcr_backup);\n\t\trtw_hal_rcr_set_chk_bssid(adapter, MLME_ACTION_NONE);\n\t\tisMonitor = _FALSE;\n\t}\n\n\tif (mode == _HW_STATE_MONITOR_) {\n\t\tisMonitor = _TRUE;\n\n\t\tSet_MSR(adapter, _HW_STATE_NOLINK_);\n\t\tset_opmode_monitor(adapter);\n\t\treturn;\n\t}\n\n\t/* clear crc bit */\n\tif (rtw_hal_rcr_check(adapter, BIT_ACRC32_8822C))\n\t\trtw_hal_rcr_clear(adapter, BIT_ACRC32_8822C);\n\n#ifdef CONFIG_MI_WITH_MBSSID_CAM /*For Port0 - MBSS CAM*/\n\tif (adapter->hw_port != HW_PORT0) {\n\t\tRTW_ERR(ADPT_FMT \": Configure MBSSID cam on HW_PORT%d\\n\", ADPT_ARG(adapter), adapter->hw_port);\n\t\trtw_warn_on(1);\n\t} else\n\t\thw_var_set_opmode_mbid(adapter, mode);\n#else\n\n\tswitch (adapter->hw_port) {\n\tcase HW_PORT0:\n\t\tset_opmode_port0(adapter, mode);\n\t\tbreak;\n\n\tcase HW_PORT1:\n\t\tset_opmode_port1(adapter, mode);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n#endif\n}\n\nstatic void hw_var_hw_port_cfg(_adapter *adapter, u8 enable)\n{\n\tif (enable)\n\t\thw_bcn_ctrl_add(adapter, get_hw_port(adapter), (BIT_P0_EN_RXBCN_RPT | BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION));\n\telse\n\t\thw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_EN_BCN_FUNCTION);\n}\n\nstatic void hw_var_set_bcn_func(PADAPTER adapter, u8 enable)\n{\n\tu8 val8 = 0;\n\n\tif (enable) {\n\t\t/* enable TX BCN report\n\t\t *  Reg REG_FWHW_TXQ_CTRL_8822C[2] = 1\n\t\t *  Reg REG_BCN_CTRL_8822C[3][5] = 1\n\t\t */\n\t\tval8 = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8822C);\n\t\tval8 |= BIT_EN_BCN_TRXRPT_V1_8822C;\n\t\trtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822C, val8);\n\n\t\t\n\t\tswitch (adapter->hw_port) {\n\t\tcase HW_PORT0:\n\t\t\tval8 =  BIT_EN_BCN_FUNCTION_8822C | BIT_P0_EN_TXBCN_RPT_8822C;\n\t\t\thw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_P0_EN_RXBCN_RPT_8822C);\n\t\t\tbreak;\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tcase HW_PORT1:\n\t\t\tval8 =  BIT_CLI0_EN_BCN_FUNCTION_8822C;\n\t\t\thw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_CLI0_EN_RXBCN_RPT_8822C);\n\t\t\tbreak;\n\t\tcase HW_PORT2:\n\t\t\tval8 =  BIT_CLI1_EN_BCN_FUNCTION_8822C;\n\t\t\thw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_CLI1_EN_RXBCN_RPT_8822C);\n\t\t\tbreak;\n\t\tcase HW_PORT3:\n\t\t\tval8 =  BIT_CLI2_EN_BCN_FUNCTION_8822C;\n\t\t\thw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_CLI2_EN_RXBCN_RPT_8822C);\n\t\t\tbreak;\n\t\tcase HW_PORT4:\n\t\t\tval8 =  BIT_CLI3_EN_BCN_FUNCTION_8822C;\n\t\t\thw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_CLI3_EN_RXBCN_RPT_8822C);\n\t\t\tbreak;\n#endif /* CONFIG_CONCURRENT_MODE */\n\t\tdefault:\n\t\t\tRTW_ERR(FUNC_ADPT_FMT\" Unknow hw port(%d) \\n\", FUNC_ADPT_ARG(adapter), adapter->hw_port);\n\t\t\trtw_warn_on(1);\n\t\t\tbreak;\n\n\t\t}\n\t\thw_bcn_ctrl_add(adapter, get_hw_port(adapter), val8);\n\t} else {\n\n\t\tswitch (adapter->hw_port) {\n\t\tcase HW_PORT0:\n\t\t\tval8 =  BIT_EN_BCN_FUNCTION_8822C | BIT_P0_EN_TXBCN_RPT_8822C;\n#ifdef CONFIG_BT_COEXIST\n\t\t\t/* Always enable port0 beacon function for PSTDMA */\n\t\t\tif (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist)\n\t\t\t\tval8 = BIT_P0_EN_TXBCN_RPT_8822C;\n#endif /* CONFIG_BT_COEXIST */\n\t\t\tbreak;\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tcase HW_PORT1:\n\t\t\tval8 =  BIT_CLI0_EN_BCN_FUNCTION_8822C;\n\t\t\tbreak;\n\t\tcase HW_PORT2:\n\t\t\tval8 =  BIT_CLI1_EN_BCN_FUNCTION_8822C;\n\t\t\tbreak;\n\t\tcase HW_PORT3:\n\t\t\tval8 =  BIT_CLI2_EN_BCN_FUNCTION_8822C;\n\t\t\tbreak;\n\t\tcase HW_PORT4:\n\t\t\tval8 =  BIT_CLI3_EN_BCN_FUNCTION_8822C;\n\t\t\tbreak;\n#endif /* CONFIG_CONCURRENT_MODE */\n\t\tdefault:\n\t\t\tRTW_ERR(FUNC_ADPT_FMT\" Unknow hw port(%d) \\n\", FUNC_ADPT_ARG(adapter), adapter->hw_port);\n\t\t\trtw_warn_on(1);\n\t\t\tbreak;\n\t\t}\n\n\t\thw_bcn_ctrl_clr(adapter, get_hw_port(adapter), val8);\n\t}\n}\n\nstatic void hw_var_set_mlme_disconnect(PADAPTER adapter)\n{\n\tu8 val8;\n\tstruct mi_state mstate;\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE)\n#endif\n\t\t/* reject all data frames under not link state */\n\t\trtw_write16(adapter, REG_RXFLTMAP2_8822C, 0);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (adapter->hw_port == HW_PORT1) {\n\t\t/* reset TSF1(CLINT0) */\n\t\trtw_write8(adapter, REG_DUAL_TSF_RST_8822C, BIT_TSFTR_CLI0_RST_8822C);\n\n\t\t/* disable update TSF1(CLINT0) */\n\t\trtw_iface_disable_tsf_update(adapter);\n\n\t\t/* disable Port1's beacon function */\n\t\tval8 = rtw_read8(adapter, REG_BCN_CTRL_CLINT0_8822C);\n\t\tval8 &= ~BIT_CLI0_EN_BCN_FUNCTION_8822C;\n\t\trtw_write8(adapter, REG_BCN_CTRL_CLINT0_8822C, val8);\n\t} else\n#endif\n\t{\n\t\t/* reset TSF */\n\t\trtw_write8(adapter, REG_DUAL_TSF_RST_8822C, BIT_TSFTR_RST_8822C);\n\n\t\t/* disable update TSF */\n\t\trtw_iface_disable_tsf_update(adapter);\n\t}\n\n\trtw_mi_status_no_self(adapter, &mstate);\n\n\t/* clear update TSF only BSSID match for no linked station */\n\tif (MSTATE_STA_LD_NUM(&mstate) == 0 && MSTATE_STA_LG_NUM(&mstate) == 0)\n\t\trtl8822c_rx_tsf_addr_filter_config(adapter, 0);\n\n#ifdef CONFIG_CLIENT_PORT_CFG\n\tif (MLME_IS_STA(adapter))\n\t\trtw_hw_client_port_clr(adapter);\n#endif\n\n}\n\nstatic void hw_var_set_mlme_sitesurvey(PADAPTER adapter, u8 enable)\n{\n\tstruct dvobj_priv *dvobj;\n\tPHAL_DATA_TYPE hal;\n\tstruct mlme_priv *pmlmepriv;\n\tPADAPTER iface;\n\tu32 reg_bcn_ctl;\n\tu16 value_rxfltmap2;\n\tu8 val8, i;\n\n\n\tdvobj = adapter_to_dvobj(adapter);\n\thal = GET_HAL_DATA(adapter);\n\tpmlmepriv = &adapter->mlmepriv;\n\n#ifdef CONFIG_FIND_BEST_CHANNEL\n\t/* Receive all data frames */\n\tvalue_rxfltmap2 = 0xFFFF;\n#else\n\t/* not to receive data frame */\n\tvalue_rxfltmap2 = 0;\n#endif\n\n\tif (enable) {\n\t\t/*\n\t\t * 1. configure REG_RXFLTMAP2\n\t\t * 2. config RCR to receive different BSSID BCN or probe rsp\n\t\t */\n\n\t\trtw_write16(adapter, REG_RXFLTMAP2_8822C, value_rxfltmap2);\n\n\t\trtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_ENTER);\n\n\t\tif (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))\n\t\t\tStopTxBeacon(adapter);\n\t} else {\n\t\t/* sitesurvey done\n\t\t * 1. enable rx data frame\n\t\t * 2. config RCR not to receive different BSSID BCN or probe rsp\n\t\t */\n\n\t\tif (rtw_mi_check_fwstate(adapter, _FW_LINKED | WIFI_AP_STATE | WIFI_MESH_STATE))\n\t\t\t/* enable to rx data frame */\n\t\t\trtw_write16(adapter, REG_RXFLTMAP2_8822C, 0xFFFF);\n\n\t\trtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_DONE);\n\n\t\tif (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {\n\t\t\tResumeTxBeacon(adapter);\n\t\t\trtw_mi_tx_beacon_hdl(adapter);\n\t\t}\n\t}\n}\n\nstatic void hw_var_set_mlme_join(PADAPTER adapter, u8 type)\n{\n\tu8 val8;\n\tu16 val16;\n\tu32 val32;\n\tu8 RetryLimit;\n\tPHAL_DATA_TYPE hal;\n\tstruct mlme_priv *pmlmepriv;\n\n\tRetryLimit = RL_VAL_STA;\n\thal = GET_HAL_DATA(adapter);\n\tpmlmepriv = &adapter->mlmepriv;\n\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (type == 0) {\n\t\t/* prepare to join */\n\t\tif (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))\n\t\t\tStopTxBeacon(adapter);\n\n\t\t/* enable to rx data frame.Accept all data frame */\n\t\trtw_write16(adapter, REG_RXFLTMAP2_8822C, 0xFFFF);\n\n\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)\n\t\t\tRetryLimit = (hal->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA;\n\t\telse /* Ad-hoc Mode */\n\t\t\tRetryLimit = RL_VAL_AP;\n\n\t\t/*\n\t\t * for 8822C, must enable BCN function if BIT_CBSSID_BCN_8822C(bit 7) of REG_RCR(0x608) is enable to recv BSSID bcn\n\t\t */\n\t\thw_var_set_bcn_func(adapter, _TRUE);\n\n\t\t/* update TSF only BSSID match for station mode */\n\t\trtl8822c_rx_tsf_addr_filter_config(adapter, BIT_CHK_TSF_EN_8822C | BIT_CHK_TSF_CBSSID_8822C);\n\t\t#ifdef CONFIG_CLIENT_PORT_CFG\n\t\trtw_hw_client_port_cfg(adapter);\n\t\t#endif\n\n\t\trtw_iface_enable_tsf_update(adapter);\n\n\t} else if (type == 1) {\n\t\t/* joinbss_event call back when join res < 0 */\n\t\tif (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE)\n\t\t\trtw_write16(adapter, REG_RXFLTMAP2_8822C, 0x00);\n\n\t\trtw_iface_disable_tsf_update(adapter);\n\n\t\tif (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {\n\t\t\tResumeTxBeacon(adapter);\n\n\t\t\t/* reset TSF 1/2 after resume_tx_beacon */\n\t\t\tval8 = BIT_TSFTR_RST_8822C | BIT_TSFTR_CLI0_RST_8822C;\n\t\t\trtw_write8(adapter, REG_DUAL_TSF_RST_8822C, val8);\n\t\t}\n\t\t#ifdef CONFIG_CLIENT_PORT_CFG\n\t\tif (MLME_IS_STA(adapter))\n\t\t\trtw_hw_client_port_clr(adapter);\n\t\t#endif\n\n\t} else if (type == 2) {\n\t\t/* sta add event callback */\n\t\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {\n\t\t\trtw_write8(adapter, 0x542, 0x02);\n\t\t\tRetryLimit = RL_VAL_AP;\n\t\t}\n\n\t\tif (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {\n\t\t\tResumeTxBeacon(adapter);\n\n\t\t\t/* reset TSF 1/2 after resume_tx_beacon */\n\t\t\trtw_write8(adapter, REG_DUAL_TSF_RST_8822C, BIT_TSFTR_RST_8822C | BIT_TSFTR_CLI0_RST_8822C);\n\t\t}\n\t}\n\n\tval16 = BIT_LRL_8822C(RetryLimit) | BIT_SRL_8822C(RetryLimit);\n\trtw_write16(adapter, REG_RETRY_LIMIT_8822C, val16);\n#else /* !CONFIG_CONCURRENT_MODE */\n\tif (type == 0) {\n\t\t/* prepare to join */\n\n\t\t/* enable to rx data frame. Accept all data frame */\n\t\trtw_write16(adapter, REG_RXFLTMAP2_8822C, 0xFFFF);\n\n\t\t/*\n\t\t * for 8822C, must enable BCN function if BIT_CBSSID_BCN_8822C(bit 7) of REG_RCR(0x608) is enabled to recv BSSID bcn\n\t\t */\n\t\thw_var_set_bcn_func(adapter, _TRUE);\n\n\t\t/* update TSF only BSSID match for station mode */\n\t\trtl8822c_rx_tsf_addr_filter_config(adapter, BIT_CHK_TSF_EN_8822C | BIT_CHK_TSF_CBSSID_8822C);\n\n\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)\n\t\t\tRetryLimit = (hal->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA;\n\t\telse /* Ad-hoc Mode */\n\t\t\tRetryLimit = RL_VAL_AP;\n\n\t\trtw_iface_enable_tsf_update(adapter);\n\n\t} else if (type == 1) {\n\t\t/* joinbss_event call back when join res < 0 */\n\t\trtw_write16(adapter, REG_RXFLTMAP2_8822C, 0x00);\n\n\t\trtw_iface_disable_tsf_update(adapter);\n\n\t} else if (type == 2) {\n\t\t/* sta add event callback */\n\t\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE))\n\t\t\tRetryLimit = RL_VAL_AP;\n\t}\n\n\tval16 = BIT_LRL_8822C(RetryLimit) | BIT_SRL_8822C(RetryLimit);\n\trtw_write16(adapter, REG_RETRY_LIMIT_8822C, val16);\n#endif /* !CONFIG_CONCURRENT_MODE */\n}\n\nstatic void hw_var_set_acm_ctrl(PADAPTER adapter, u8 ctrl)\n{\n\tu8 hwctrl = 0;\n\n\tif (ctrl) {\n\t\thwctrl |= BIT_ACMHWEN_8822C;\n\n\t\tif (ctrl & BIT(1)) /* BE */\n\t\t\thwctrl |= BIT_BEQ_ACM_EN_8822C;\n\t\telse\n\t\t\thwctrl &= (~BIT_BEQ_ACM_EN_8822C);\n\n\t\tif (ctrl & BIT(2)) /* VI */\n\t\t\thwctrl |= BIT_VIQ_ACM_EN_8822C;\n\t\telse\n\t\t\thwctrl &= (~BIT_VIQ_ACM_EN_8822C);\n\n\t\tif (ctrl & BIT(3)) /* VO */\n\t\t\thwctrl |= BIT_VOQ_ACM_EN_8822C;\n\t\telse\n\t\t\thwctrl &= (~BIT_VOQ_ACM_EN_8822C);\n\t}\n\n\tRTW_INFO(\"[HW_VAR_ACM_CTRL] Write 0x%02X\\n\", hwctrl);\n\trtw_write8(adapter, REG_ACMHWCTRL_8822C, hwctrl);\n}\n\nstatic void hw_var_set_sec_dk_cfg(PADAPTER adapter, u8 enable)\n{\n\tstruct security_priv *sec = &adapter->securitypriv;\n\tu8 reg_scr = rtw_read8(adapter, REG_SECCFG_8822C);\n\n\tif (enable) {\n\t\t/* Enable default key related setting */\n\t\treg_scr |= BIT_TXBCUSEDK_8822C;\n\t\tif (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)\n\t\t\treg_scr |= BIT_RXUHUSEDK_8822C | BIT_TXUHUSEDK_8822C;\n\t} else {\n\t\t/* Disable default key related setting */\n\t\treg_scr &= ~(BIT_RXBCUSEDK_8822C | BIT_TXBCUSEDK_8822C | BIT_RXUHUSEDK_8822C | BIT_TXUHUSEDK_8822C);\n\t}\n\n\trtw_write8(adapter, REG_SECCFG_8822C, reg_scr);\n\n\tRTW_INFO(\"%s: [HW_VAR_SEC_DK_CFG] 0x%x=0x%08x\\n\", __FUNCTION__,\n\t\t REG_SECCFG_8822C, rtw_read32(adapter, REG_SECCFG_8822C));\n}\n\nstatic void hw_var_set_bcn_valid(PADAPTER adapter)\n{\n\tu8 val8 = 0;\n\n\t/* only port 0 can TX BCN */\n\tval8 = rtw_read8(adapter, REG_FIFOPAGE_CTRL_2_8822C + 1);\n\tval8 = val8 | BIT(7);\n\trtw_write8(adapter, REG_FIFOPAGE_CTRL_2_8822C + 1, val8);\n}\n\nstatic void hw_var_set_ack_preamble(PADAPTER adapter, u8 bShortPreamble)\n{\n\tu8 val8 = 0;\n\n\n\tval8 = rtw_read8(adapter, REG_WMAC_TRXPTCL_CTL_8822C + 2);\n\tval8 |= BIT(4) | BIT(5);\n\n\tif (bShortPreamble)\n\t\tval8 |= BIT1;\n\telse\n\t\tval8 &= (~BIT1);\n\n\trtw_write8(adapter, REG_WMAC_TRXPTCL_CTL_8822C + 2, val8);\n}\n\nvoid hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\tu8 bcn_valid = _FALSE;\n\tu8 DLBcnCount = 0;\n\tu32 poll = 0;\n\tu8 val8;\n\tu8 restore[2];\n\tu8 hw_port = rtw_hal_get_port(adapter);\n\n\tRTW_INFO(FUNC_ADPT_FMT \":+ hw_port=%d mstatus(%x)\\n\",\n\t\t FUNC_ADPT_ARG(adapter), hw_port, mstatus);\n\n\tif (mstatus == RT_MEDIA_CONNECT) {\n#if 0\n\t\tu8 bRecover = _FALSE;\n#endif\n\t\tu8 v8;\n\n\t\t/* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 8822C. */\n\t\trtw_write16(adapter, port_cfg[hw_port].ps_aid, (0xF800 | pmlmeinfo->aid));\n\n\t\t/* Enable SW TX beacon */\n\t\tv8 = rtw_read8(adapter, REG_CR_8822C + 1);\n\t\trestore[0] = v8;\n\t\tv8 |= (BIT_ENSWBCN_8822C >> 8);\n\t\trtw_write8(adapter, REG_CR_8822C + 1, v8);\n\n\t\t/*\n\t\t * Disable Hw protection for a time which revserd for Hw sending beacon.\n\t\t * Fix download reserved page packet fail that access collision with the protection time.\n\t\t */\n\t\tval8 = rtw_read8(adapter, REG_BCN_CTRL_8822C);\n\t\trestore[1] = val8;\n\t\tval8 &= ~BIT_EN_BCN_FUNCTION_8822C;\n\t\tval8 |= BIT_DIS_TSF_UDT_8822C;\n\t\trtw_write8(adapter, REG_BCN_CTRL_8822C, val8);\n\n#if 0\n\t\t/* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */\n\t\tRegFwHwTxQCtrl = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8822C + 2);\n\n\t\tif (RegFwHwTxQCtrl & BIT(6))\n\t\t\tbRecover = _TRUE;\n\n\t\t/* To tell Hw the packet is not a real beacon frame. */\n\t\tRegFwHwTxQCtrl &= ~BIT(6);\n\t\trtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822C + 2, RegFwHwTxQCtrl);\n#endif\n\n\t\t/* Clear beacon valid check bit. */\n\t\trtw_hal_set_hwreg(adapter, HW_VAR_BCN_VALID, NULL);\n\t\trtw_hal_set_hwreg(adapter, HW_VAR_DL_BCN_SEL, NULL);\n\n\t\tDLBcnCount = 0;\n\t\tpoll = 0;\n\t\tdo {\n\t\t\t/* download rsvd page. */\n\t\t\trtw_hal_set_fw_rsvd_page(adapter, _FALSE);\n\t\t\tDLBcnCount++;\n\t\t\tdo {\n\t\t\t\trtw_yield_os();\n\n\t\t\t\t/* check rsvd page download OK. */\n\t\t\t\trtw_hal_get_hwreg(adapter, HW_VAR_BCN_VALID, (u8 *)&bcn_valid);\n\t\t\t\tpoll++;\n\t\t\t} while (!bcn_valid && (poll % 10) != 0 && !RTW_CANNOT_RUN(adapter));\n\n\t\t} while (!bcn_valid && DLBcnCount <= 100 && !RTW_CANNOT_RUN(adapter));\n\n\t\tif (RTW_CANNOT_RUN(adapter))\n\t\t\t;\n\t\telse if (!bcn_valid)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": DL RSVD page failed! DLBcnCount:%u, poll:%u\\n\",\n\t\t\t\t FUNC_ADPT_ARG(adapter), DLBcnCount, poll);\n\t\telse {\n\t\t\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);\n\n\t\t\tpwrctl->fw_psmode_iface_id = adapter->iface_id;\n\t\t\trtw_hal_set_fw_rsvd_page(adapter, _TRUE);\n\t\t\tRTW_INFO(ADPT_FMT \": DL RSVD page success! DLBcnCount:%u, poll:%u\\n\",\n\t\t\t\t ADPT_ARG(adapter), DLBcnCount, poll);\n\t\t}\n\n\t\trtw_write8(adapter, REG_BCN_CTRL, restore[1]);\n\t\trtw_write8(adapter,  REG_CR + 1, restore[0]);\n#if 0\n\t\t/*\n\t\t * To make sure that if there exists an adapter which would like to send beacon.\n\t\t * If exists, the origianl value of 0x422[6] will be 1, we should check this to\n\t\t * prevent from setting 0x422[6] to 0 after download reserved page, or it will cause\n\t\t * the beacon cannot be sent by HW.\n\t\t */\n\t\tif (bRecover) {\n\t\t\tRegFwHwTxQCtrl |= BIT(6);\n\t\t\trtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822C + 2, RegFwHwTxQCtrl);\n\t\t}\n#endif\n#ifndef CONFIG_PCI_HCI\n\t\t/* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */\n\t\tv8 = rtw_read8(adapter, REG_CR_8822C + 1);\n\t\tv8 &= ~BIT(0); /* ~ENSWBCN */\n\t\trtw_write8(adapter, REG_CR_8822C + 1, v8);\n#endif /* !CONFIG_PCI_HCI */\n\t}\n}\n\nstatic void hw_var_set_h2c_fw_joinbssrpt(PADAPTER adapter, u8 mstatus)\n{\n\tif (mstatus == RT_MEDIA_CONNECT)\n\t\thw_var_set_dl_rsvd_page(adapter, RT_MEDIA_CONNECT);\n}\n\n/*\n * Parameters:\n *\tadapter\n *\tenable\t\t_TRUE: enable; _FALSE: disable\n */\nstatic u8 rx_agg_switch(PADAPTER adapter, u8 enable)\n{\n\tint err;\n\n\terr = rtw_halmac_rx_agg_switch(adapter_to_dvobj(adapter), enable);\n\tif (err)\n\t\treturn _FAIL;\n\n\treturn _SUCCESS;\n}\n\n\n#ifdef CONFIG_AP_PORT_SWAP\n/*\n * Parameters:\n *\tif_ap\t\tap interface\n *\tif_port0\t\tport0 interface\n */\n\nstatic void hw_port_reconfig(_adapter * if_ap, _adapter *if_port0)\n{\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(if_port0);\n\tstruct mlme_ext_priv *pmlmeext = &if_port0->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu32 bssid_offset = 0;\n\tu8 bssid[6] = {0};\n\tu8 vnet_type = 0;\n\tu8 vbcn_ctrl = 0;\n\tu8 i;\n\tu8 port = if_ap->hw_port;\n\n\tif (port > (hal_spec->port_num - 1)) {\n\t\tRTW_INFO(\"[WARN] \"ADPT_FMT\"- hw_port : %d,will switch to invalid port-%d\\n\",\n\t\t\t ADPT_ARG(if_port0), if_port0->hw_port, port);\n\t\trtw_warn_on(1);\n\t}\n\n\tRTW_PRINT(ADPT_FMT\" - hw_port : %d,will switch to port-%d\\n\",\n\t\t  ADPT_ARG(if_port0), if_port0->hw_port, port);\n\n\t/*backup*/\n\tGetHwReg(if_port0, HW_VAR_MEDIA_STATUS, &vnet_type);\n\tvbcn_ctrl = rtw_read8(if_port0, port_cfg[if_port0->hw_port].bcn_ctl);\n\n\tif (is_client_associated_to_ap(if_port0)) {\n\t\tRTW_INFO(\"port0-iface(\"ADPT_FMT\") is STA mode and linked\\n\", ADPT_ARG(if_port0));\n\t\tbssid_offset = port_cfg[if_port0->hw_port].bssid;\n\t\tfor (i = 0; i < 6; i++)\n\t\t\tbssid[i] = rtw_read8(if_port0, bssid_offset + i);\n\t}\n\n\t/*reconfigure*/\n\tif_port0->hw_port = port;\n\t/* adapter mac addr switch to port mac addr */\n\trtw_hal_set_hwreg(if_port0, HW_VAR_MAC_ADDR, adapter_mac_addr(if_port0));\n\tSet_MSR(if_port0, vnet_type);\n\trtw_write8(if_port0, port_cfg[if_port0->hw_port].bcn_ctl, vbcn_ctrl);\n\n\tif (is_client_associated_to_ap(if_port0)) {\n\t\trtw_hal_set_hwreg(if_port0, HW_VAR_BSSID, bssid);\n\t\t#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\t\trtw_set_default_port_id(if_port0);\n\t\t#endif\n\t}\n\n#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)\n\tif (GET_HAL_DATA(if_port0)->EEPROMBluetoothCoexist == _TRUE)\n\t\trtw_hal_set_wifi_btc_port_id_cmd(if_port0);\n#endif\n\n\tif_ap->hw_port =HW_PORT0;\n\t/* port mac addr switch to adapter mac addr */\n\trtw_hal_set_hwreg(if_ap, HW_VAR_MAC_ADDR, adapter_mac_addr(if_ap));\n}\n\nstatic void hw_var_ap_port_switch(_adapter *adapter, u8 mode)\n{\n\tu8 hw_port = get_hw_port(adapter);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tu8 ap_nums = 0;\n\t_adapter *if_port0 = NULL;\n\tint i;\n\n\tRTW_INFO(ADPT_FMT \": hw_port(%d) will set mode to %d\\n\", ADPT_ARG(adapter), hw_port, mode);\n#if 0\n\t#ifdef CONFIG_P2P\n\tif (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) {\n\t\tRTW_INFO(\"%s, role=%d, p2p_state=%d, pre_p2p_state=%d\\n\", __func__,\n\t\t\trtw_p2p_role(&adapter->wdinfo), rtw_p2p_state(&adapter->wdinfo), rtw_p2p_pre_state(&adapter->wdinfo));\n\t}\n\t#endif\n#endif\n\n\tif (mode != _HW_STATE_AP_)\n\t\treturn;\n\n\tif (hw_port == HW_PORT0)\n\t\treturn;\n\n\t/*check and prepare switch port to port0 for AP mode's BCN function*/\n\tap_nums = rtw_mi_get_ap_num(adapter);\n\tif (ap_nums > 0) {\n\t\tRTW_ERR(\"SortAP mode numbers:%d, must move setting to MBSSID CAM, not support yet\\n\", ap_nums);\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\t/*Get iface of port-0*/\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tif (get_hw_port(dvobj->padapters[i]) == HW_PORT0) {\n\t\t\tif_port0 = dvobj->padapters[i];\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (if_port0 == NULL) {\n\t\tRTW_ERR(\"%s if_port0 == NULL\\n\", __func__);\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\t/* if_port0 switch to hw_port */\n\thw_port_reconfig(adapter, if_port0);\n\tRTW_INFO(ADPT_FMT \": Cfg SoftAP mode to hw_port(%d) done\\n\", ADPT_ARG(adapter), adapter->hw_port);\n\n}\n#endif\n\nu8 rtl8822c_sethwreg(PADAPTER adapter, u8 variable, u8 *val)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tu8 ret = _SUCCESS;\n\tu8 val8;\n\tu16 val16;\n\tu32 val32;\n\n\n\tswitch (variable) {\n\tcase HW_VAR_SET_OPMODE:\n\t\thw_var_set_opmode(adapter, *val);\n\t\tbreak;\n/*\n\tcase HW_VAR_INIT_RTS_RATE:\n\t\tbreak;\n*/\n\tcase HW_VAR_BASIC_RATE:\n\t\trtw_var_set_basic_rate(adapter, val);\n\t\tbreak;\n\n\tcase HW_VAR_TXPAUSE:\n\t\trtw_write8(adapter, REG_TXPAUSE_8822C, *val);\n\t\tbreak;\n\n\tcase HW_VAR_BCN_FUNC:\n\t\thw_var_set_bcn_func(adapter, *val);\n\t\tbreak;\n\n\tcase HW_VAR_PORT_CFG:\n\t\thw_var_hw_port_cfg(adapter, *val);\n\t\tbreak;\n\n\tcase HW_VAR_MLME_DISCONNECT:\n\t\thw_var_set_mlme_disconnect(adapter);\n\t\tbreak;\n\n\tcase HW_VAR_MLME_SITESURVEY:\n\t\thw_var_set_mlme_sitesurvey(adapter, *val);\n#ifdef CONFIG_BT_COEXIST\n\t\tif (hal->EEPROMBluetoothCoexist)\n\t\t\trtw_btcoex_ScanNotify(adapter, *val ? _TRUE : _FALSE);\n\t\telse\n#endif /* CONFIG_BT_COEXIST */\n\t\t\trtw_btcoex_wifionly_scan_notify(adapter);\n\t\tbreak;\n\n\tcase HW_VAR_MLME_JOIN:\n\t\thw_var_set_mlme_join(adapter, *val);\n#ifdef CONFIG_BT_COEXIST\n\t\tif (hal->EEPROMBluetoothCoexist)\n\t\t\trtw_btcoex_ConnectNotify(adapter, *val ? _FALSE : _TRUE);\n\t\telse\n#endif /* CONFIG_BT_COEXIST */\n\t\trtw_btcoex_wifionly_connect_notify(adapter);\n\t\tbreak;\n\n\tcase HW_VAR_RCR:\n\t\tret = rtl8822c_rcr_config(adapter, *((u32 *)val));\n\t\tbreak;\n\n\tcase HW_VAR_SLOT_TIME:\n\t\trtw_write8(adapter, REG_SLOT_8822C, *val);\n\t\tbreak;\n\n\tcase HW_VAR_RESP_SIFS:\n\t\t/* RESP_SIFS for CCK */\n\t\trtw_write8(adapter, REG_RESP_SIFS_CCK_8822C, val[0]);\n\t\trtw_write8(adapter, REG_RESP_SIFS_CCK_8822C + 1, val[1]);\n\t\t/* RESP_SIFS for OFDM */\n\t\trtw_write8(adapter, REG_RESP_SIFS_OFDM_8822C, val[2]);\n\t\trtw_write8(adapter, REG_RESP_SIFS_OFDM_8822C + 1, val[3]);\n\t\tbreak;\n\n\tcase HW_VAR_ACK_PREAMBLE:\n\t\thw_var_set_ack_preamble(adapter, *val);\n\t\tbreak;\n\n/*\n\tcase HW_VAR_SEC_CFG:\n\t\tfollow hal_com.c\n\t\tbreak;\n*/\n\n\tcase HW_VAR_SEC_DK_CFG:\n\t\tif (val)\n\t\t\thw_var_set_sec_dk_cfg(adapter, _TRUE);\n\t\telse\n\t\t\thw_var_set_sec_dk_cfg(adapter, _FALSE);\n\t\tbreak;\n\n\tcase HW_VAR_BCN_VALID:\n\t\thw_var_set_bcn_valid(adapter);\n\t\tbreak;\n/*\n\tcase HW_VAR_RF_TYPE:\n\t\tbreak;\n*/\n\n\tcase HW_VAR_CAM_INVALID_ALL:\n\t\tval32 = BIT_SECCAM_POLLING_8822C | BIT_SECCAM_CLR_8822C;\n\t\trtw_write32(adapter, REG_CAMCMD_8822C, val32);\n\t\tbreak;\n\n\tcase HW_VAR_AC_PARAM_VO:\n\t\trtw_write32(adapter, REG_EDCA_VO_PARAM_8822C, *(u32 *)val);\n\t\tbreak;\n\n\tcase HW_VAR_AC_PARAM_VI:\n\t\trtw_write32(adapter, REG_EDCA_VI_PARAM_8822C, *(u32 *)val);\n\t\tbreak;\n\n\tcase HW_VAR_AC_PARAM_BE:\n\t\thal->ac_param_be = *(u32 *)val;\n\t\trtw_write32(adapter, REG_EDCA_BE_PARAM_8822C, *(u32 *)val);\n\t\tbreak;\n\n\tcase HW_VAR_AC_PARAM_BK:\n\t\trtw_write32(adapter, REG_EDCA_BK_PARAM_8822C, *(u32 *)val);\n\t\tbreak;\n\n\tcase HW_VAR_ACM_CTRL:\n\t\thw_var_set_acm_ctrl(adapter, *val);\n\t\tbreak;\n/*\n\tcase HW_VAR_AMPDU_MIN_SPACE:\n\t\tbreak;\n*/\n#ifdef CONFIG_80211N_HT\n\tcase HW_VAR_AMPDU_FACTOR: {\n\t\tu32 AMPDULen = *val; /* enum AGGRE_SIZE */\n\n\t\tAMPDULen = (0x2000 << AMPDULen) - 1;\n\t\trtw_write32(adapter, REG_AMPDU_MAX_LENGTH_HT_8822C, AMPDULen);\n\t}\n\tbreak;\n#endif /* CONFIG_80211N_HT */\n\tcase HW_VAR_RXDMA_AGG_PG_TH:\n\t\t/*\n\t\t * TH=1 => invalidate RX DMA aggregation\n\t\t * TH=0 => validate RX DMA aggregation, use init value.\n\t\t */\n\t\tif (*val == 0)\n\t\t\t/* enable RXDMA aggregation */\n\t\t\trx_agg_switch(adapter, _TRUE);\n\t\telse\n\t\t\t/* disable RXDMA aggregation */\n\t\t\trx_agg_switch(adapter, _FALSE);\n\t\tbreak;\n/*\n\tcase HW_VAR_SET_RPWM:\n\tcase HW_VAR_CPWM:\n\t\tbreak;\n*/\n\tcase HW_VAR_H2C_FW_PWRMODE:\n\t\trtl8822c_set_FwPwrMode_cmd(adapter, *val);\n\t\tbreak;\n/*\n\tcase HW_VAR_H2C_PS_TUNE_PARAM:\n\t\tbreak;\n*/\n\tcase HW_VAR_H2C_INACTIVE_IPS:\n#ifdef CONFIG_WOWLAN\n\t\trtl8822c_set_fw_pwrmode_inips_cmd_wowlan(adapter, *val);\n#endif /* CONFIG_WOWLAN */\n\t\tbreak;\n\tcase HW_VAR_H2C_FW_JOINBSSRPT:\n\t\thw_var_set_h2c_fw_joinbssrpt(adapter, *val);\n\t\tbreak;\n\tcase HW_VAR_DL_RSVD_PAGE:\n#ifdef CONFIG_BT_COEXIST\n\t\tif (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE)\n\t\t\trtl8822c_download_BTCoex_AP_mode_rsvd_page(adapter);\n#endif\n\t\tbreak;\n#ifdef CONFIG_P2P_PS\n\tcase HW_VAR_H2C_FW_P2P_PS_OFFLOAD:\n\t\t#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\t\tif (*val == P2P_PS_ENABLE)\n\t\t\trtw_set_default_port_id(adapter);\n\t\t#endif\n\t\trtw_set_p2p_ps_offload_cmd(adapter, *val);\n\t\tbreak;\n#endif /* CONFIG_P2P_PS */\n/*\n\tcase HW_VAR_TRIGGER_GPIO_0:\n\tcase HW_VAR_BT_SET_COEXIST:\n\tcase HW_VAR_BT_ISSUE_DELBA:\n\tcase HW_VAR_SWITCH_EPHY_WoWLAN:\n\tcase HW_VAR_EFUSE_USAGE:\n\tcase HW_VAR_EFUSE_BYTES:\n\tcase HW_VAR_EFUSE_BT_USAGE:\n\tcase HW_VAR_EFUSE_BT_BYTES:\n\t\tbreak;\n*/\n\tcase HW_VAR_FIFO_CLEARN_UP: {\n\t\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\t\tu8 trycnt = 100;\n\t\tu32 reg_hw_ssn;\n\n\t\t/* pause tx */\n\t\trtw_write8(adapter, REG_TXPAUSE_8822C, 0xff);\n\n\t\t/* keep hw sn */\n\t\tif (adapter->xmitpriv.hw_ssn_seq_no == 1)\n\t\t\treg_hw_ssn = REG_HW_SEQ1_8822C;\n\t\telse if (adapter->xmitpriv.hw_ssn_seq_no == 2)\n\t\t\treg_hw_ssn = REG_HW_SEQ2_8822C;\n\t\telse if (adapter->xmitpriv.hw_ssn_seq_no == 3)\n\t\t\treg_hw_ssn = REG_HW_SEQ3_8822C;\n\t\telse\n\t\t\treg_hw_ssn = REG_HW_SEQ0_8822C;\n\n\t\tadapter->xmitpriv.nqos_ssn = rtw_read16(adapter, reg_hw_ssn);\n\n\t\tif (pwrpriv->bkeepfwalive != _TRUE) {\n\t\t\t/* RX DMA stop */\n\t\t\tval32 = rtw_read32(adapter, REG_RXPKT_NUM_8822C);\n\t\t\tval32 |= BIT_RW_RELEASE_EN;\n\t\t\trtw_write32(adapter, REG_RXPKT_NUM_8822C, val32);\n\t\t\tdo {\n\t\t\t\tval32 = rtw_read32(adapter, REG_RXPKT_NUM_8822C);\n\t\t\t\tval32 &= BIT_RXDMA_IDLE_8822C;\n\t\t\t\tif (val32)\n\t\t\t\t\tbreak;\n\n\t\t\t\tRTW_INFO(\"[HW_VAR_FIFO_CLEARN_UP] val=%x times:%d\\n\", val32, trycnt);\n\t\t\t} while (--trycnt);\n\t\t\tif (trycnt == 0)\n\t\t\t\tRTW_INFO(\"[HW_VAR_FIFO_CLEARN_UP] Stop RX DMA failed!\\n\");\n#if 0\n\t\t\t/* RQPN Load 0 */\n\t\t\trtw_write16(adapter, REG_RQPN_NPQ, 0);\n\t\t\trtw_write32(adapter, REG_RQPN, 0x80000000);\n\t\t\trtw_mdelay_os(2);\n#endif\n\t\t}\n\t}\n\tbreak;\n\n\tcase HW_VAR_RESTORE_HW_SEQ:\n\t\t{\n\t\t/* restore Sequence No. */\n\t\t\tu32 reg_hw_ssn;\n\n\t\t\tif (adapter->xmitpriv.hw_ssn_seq_no == 1)\n\t\t\t\treg_hw_ssn = REG_HW_SEQ1_8822C;\n\t\t\telse if (adapter->xmitpriv.hw_ssn_seq_no == 2)\n\t\t\t\treg_hw_ssn = REG_HW_SEQ2_8822C;\n\t\t\telse if (adapter->xmitpriv.hw_ssn_seq_no == 3)\n\t\t\t\treg_hw_ssn = REG_HW_SEQ3_8822C;\n\t\t\telse\n\t\t\t\treg_hw_ssn = REG_HW_SEQ0_8822C;\n\n\t\t\trtw_write8(adapter, reg_hw_ssn, adapter->xmitpriv.nqos_ssn);\n\t\t}\n\t\tbreak;\n\n\tcase HW_VAR_CHECK_TXBUF: {\n\t\tu16 rtylmtorg;\n\t\tu8 RetryLimit = 0x01;\n\t\tsystime start;\n\t\tu32 passtime;\n\t\tu32 timelmt = 2000;\t/* ms */\n\t\tint err;\n\t\tu8 empty;\n\n\n\t\trtylmtorg = rtw_read16(adapter, REG_RETRY_LIMIT_8822C);\n\n\t\tval16 = BIT_LRL_8822C(RetryLimit) | BIT_SRL_8822C(RetryLimit);\n\t\trtw_write16(adapter, REG_RETRY_LIMIT_8822C, val16);\n\n\t\t/* Check TX FIFO empty or not */\n\t\tempty = _FALSE;\n\t\tstart = rtw_get_current_time();\n\t\terr = rtw_halmac_txfifo_wait_empty(adapter_to_dvobj(adapter), timelmt);\n\t\tif (!err)\n\t\t\tempty = _TRUE;\n\t\tpasstime = rtw_get_passing_time_ms(start);\n\n\t\tif (_TRUE == empty)\n\t\t\tRTW_INFO(\"[HW_VAR_CHECK_TXBUF] Empty in %d ms\\n\", passtime);\n\t\telse if (RTW_CANNOT_RUN(adapter))\n\t\t\tRTW_WARN(\"[HW_VAR_CHECK_TXBUF] bDriverStopped or bSurpriseRemoved\\n\");\n\t\telse {\n\t\t\tRTW_ERR(\"[HW_VAR_CHECK_TXBUF] NOT empty in %d ms\\n\", passtime);\n\n\t\t}\n\t\trtw_write16(adapter, REG_RETRY_LIMIT_8822C, rtylmtorg);\n\t}\n\tbreak;\n/*\n\tcase HW_VAR_PCIE_STOP_TX_DMA:\n\tcase HW_VAR_APFM_ON_MAC\n\tcase HW_VAR_HCI_SUS_STATE:\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\n\tcase HW_VAR_WOWLAN:\n\tcase HW_VAR_WAKEUP_REASON:\n#endif\n\tcase HW_VAR_RPWM_TOG:\n\t\tbreak;\n*/\n#ifdef CONFIG_GPIO_WAKEUP\n\tcase HW_SET_GPIO_WL_CTRL: {\n\t\tu8 enable = *val;\n\t\tu8 value = 0;\n\t\tu8 addr = REG_PAD_CTRL1_8822C + 3;\n\n\t\tif (WAKEUP_GPIO_IDX == 6) {\n\t\t\tvalue = rtw_read8(adapter, addr);\n\n\t\t\tif (enable == _TRUE && (value & BIT(1)))\n\t\t\t\t/* set 0x64[25] = 0 to control GPIO 6 */\n\t\t\t\trtw_write8(adapter, addr, value & (~BIT(1)));\n\t\t\telse if (enable == _FALSE)\n\t\t\t\trtw_write8(adapter, addr, value | BIT(1));\n\n\t\t\tRTW_INFO(\"[HW_SET_GPIO_WL_CTRL] 0x%02X=0x%02X\\n\",\n\t\t\t\t addr, rtw_read8(adapter, addr));\n\t\t}\n\t}\n\tbreak;\n#endif\n/*\n\tcase HW_VAR_SYS_CLKR:\n\t\tbreak;\n*/\n\tcase HW_VAR_NAV_UPPER: {\n#define HAL_NAV_UPPER_UNIT\t128\t/* micro-second */\n\t\tu32 usNavUpper = *(u32 *)val;\n\n\t\tif (usNavUpper > HAL_NAV_UPPER_UNIT * 0xFF) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": [HW_VAR_NAV_UPPER] value(0x%08X us) is larger than (%d * 0xFF)!!!\\n\",\n\t\t\t\tFUNC_ADPT_ARG(adapter), usNavUpper, HAL_NAV_UPPER_UNIT);\n\t\t\tbreak;\n\t\t}\n\n\t\tusNavUpper = (usNavUpper + HAL_NAV_UPPER_UNIT - 1) / HAL_NAV_UPPER_UNIT;\n\t\trtw_write8(adapter, REG_NAV_CTRL_8822C + 2, (u8)usNavUpper);\n\t}\n\tbreak;\n\n/*\n\tcase HW_VAR_RPT_TIMER_SETTING:\n\tcase HW_VAR_TX_RPT_MAX_MACID:\n\tcase HW_VAR_CHK_HI_QUEUE_EMPTY:\n\tcase HW_VAR_AMPDU_MAX_TIME:\n\tcase HW_VAR_WIRELESS_MODE:\n\tcase HW_VAR_USB_MODE:\n\t\tbreak;\n*/\n#ifdef CONFIG_AP_PORT_SWAP\n\tcase HW_VAR_PORT_SWITCH:\n\t\t{\n\t\t\tu8 mode = *((u8 *)val);\n\n\t\t\thw_var_ap_port_switch(adapter, mode);\n\t\t}\n\t\tbreak;\n#endif\n\n#ifdef CONFIG_BEAMFORMING\n\tcase HW_VAR_SOUNDING_ENTER:\n\t\trtl8822c_phy_bf_enter(adapter, (struct sta_info*)val);\n\t\tbreak;\n\n\tcase HW_VAR_SOUNDING_LEAVE:\n\t\trtl8822c_phy_bf_leave(adapter, val);\n\t\tbreak;\n/*\n\tcase HW_VAR_SOUNDING_RATE:\n\t\tbreak;\n*/\n\tcase HW_VAR_SOUNDING_STATUS:\n\t\trtl8822c_phy_bf_sounding_status(adapter, *val);\n\t\tbreak;\n/*\n\tcase HW_VAR_SOUNDING_FW_NDPA:\n\tcase HW_VAR_SOUNDING_CLK:\n\t\tbreak;\n*/\n\tcase HW_VAR_SOUNDING_SET_GID_TABLE:\n\t\trtl8822c_phy_bf_set_gid_table(adapter, (struct beamformer_entry*)val);\n\t\tbreak;\n#endif /* CONFIG_BEAMFORMING */\n/*\n\tcase HW_VAR_HW_REG_TIMER_INIT:\n\tcase HW_VAR_HW_REG_TIMER_RESTART:\n\tcase HW_VAR_HW_REG_TIMER_START:\n\tcase HW_VAR_HW_REG_TIMER_STOP:\n\t\tbreak;\n*/\n\n/*\n\tcase HW_VAR_MACID_LINK:\n\tcase HW_VAR_MACID_NOLINK:\n\tcase HW_VAR_DUMP_MAC_QUEUE_INFO:\n\tcase HW_VAR_ASIX_IOT:\n\tcase HW_VAR_EN_HW_UPDATE_TSF:\n\tcase HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO:\n\tcase HW_VAR_CH_SW_IQK_INFO_BACKUP:\n\tcase HW_VAR_CH_SW_IQK_INFO_RESTORE:\n\t\tbreak;\n*/\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\n\tcase HW_VAR_TDLS_BCN_EARLY_C2H_RPT:\n\t\trtl8822c_set_BcnEarly_C2H_Rpt_cmd(adapter, *val);\n\t\tbreak;\n#endif\n#endif\n\n\tcase HW_VAR_FREECNT:\n\n\t\tval8 = (u8)*val;\n\n\t\tif (val8==0) {\n\t\t\t/* disable free run counter set 0x577[3]=0 */\n\t\t\trtw_write8(adapter, REG_MISC_CTRL,\n\t\t\t\trtw_read8(adapter, REG_MISC_CTRL)&(~BIT_EN_FREECNT));\n\n\t\t\t/* reset FREE_RUN_COUNTER set 0x553[5]=1 */\n\t\t\tval8 = rtw_read8(adapter, REG_DUAL_TSF_RST);\n\t\t\tval8 |=  BIT_FREECNT_RST;\n\t\t\trtw_write8(adapter, REG_DUAL_TSF_RST, val8);\n\n\t\t} else if (val8==1){\n\n\t\t\t/* enable free run counter */\n\n\t\t\t/* disable first set 0x577[3]=0 */\n\t\t\trtw_write8(adapter, REG_MISC_CTRL,\n\t\t\t\trtw_read8(adapter, REG_MISC_CTRL)&(~BIT_EN_FREECNT));\n\n\t\t\t/* reset FREE_RUN_COUNTER set 0x553[5]=1 */\n\t\t\tval8 = rtw_read8(adapter, REG_DUAL_TSF_RST);\n\t\t\tval8 |=  BIT_FREECNT_RST;\n\t\t\trtw_write8(adapter, REG_DUAL_TSF_RST, val8);\n\n\t\t\t/* enable free run counter 0x577[3]=1 */\n\t\t\trtw_write8(adapter, REG_MISC_CTRL,\n\t\t\t\trtw_read8(adapter, REG_MISC_CTRL)|BIT_EN_FREECNT);\n\t\t}\n\t\tbreak;\n\n\tcase HW_VAR_SET_SOML_PARAM:\n#ifdef CONFIG_DYNAMIC_SOML\n\t\trtw_dyn_soml_para_set(adapter, 4, 20, 1, 0);\n#endif\n\t\tbreak;\n\n\tdefault:\n\t\tret = SetHwReg(adapter, variable, val);\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstruct qinfo {\n\tu32 head:11;\n\tu32 tail:11;\n\tu32 empty:1;\n\tu32 ac:2;\n\tu32 macid:7;\n};\n\nstruct bcn_qinfo {\n\tu16 head:12;\n\tu16 rsvd:4;\n};\n\nstatic void dump_qinfo(void *sel, struct qinfo *info, u32 pkt_num, const char *tag)\n{\n\tRTW_PRINT_SEL(sel, \"%shead:0x%02x, tail:0x%02x, pkt_num:%u, macid:%u, ac:%u\\n\",\n\t\ttag ? tag : \"\", info->head, info->tail, pkt_num, info->macid, info->ac);\n}\n\nstatic void dump_bcn_qinfo(void *sel, struct bcn_qinfo *info, u32 pkt_num, const char *tag)\n{\n\tRTW_PRINT_SEL(sel, \"%shead:0x%02x, pkt_num:%u\\n\",\n\t\t      tag ? tag : \"\", info->head, pkt_num);\n}\n\nstatic void dump_mac_qinfo(void *sel, _adapter *adapter)\n{\n\tu32 q0_info;\n\tu32 q1_info;\n\tu32 q2_info;\n\tu32 q3_info;\n\tu32 q4_info;\n\tu32 q5_info;\n\tu32 q6_info;\n\tu32 q7_info;\n\tu32 mg_q_info;\n\tu32 hi_q_info;\n\tu16 bcn_q_info;\n\tu32 q0_q1_info;\n\tu32 q2_q3_info;\n\tu32 q4_q5_info;\n\tu32 q6_q7_info;\n\tu32 mg_hi_q_info;\n\tu32 cmd_bcn_q_info;\n\n\tq0_info = rtw_read32(adapter, REG_Q0_INFO_8822C);\n\tq1_info = rtw_read32(adapter, REG_Q1_INFO_8822C);\n\tq2_info = rtw_read32(adapter, REG_Q2_INFO_8822C);\n\tq3_info = rtw_read32(adapter, REG_Q3_INFO_8822C);\n\tq4_info = rtw_read32(adapter, REG_Q4_INFO_8822C);\n\tq5_info = rtw_read32(adapter, REG_Q5_INFO_8822C);\n\tq6_info = rtw_read32(adapter, REG_Q6_INFO_8822C);\n\tq7_info = rtw_read32(adapter, REG_Q7_INFO_8822C);\n\tmg_q_info = rtw_read32(adapter, REG_MGQ_INFO_8822C);\n\thi_q_info = rtw_read32(adapter, REG_HIQ_INFO_8822C);\n\tbcn_q_info = rtw_read16(adapter, REG_BCNQ_INFO_8822C);\n\n\tq0_q1_info = rtw_read32(adapter, REG_Q0_Q1_INFO_8822C);\n\tq2_q3_info = rtw_read32(adapter, REG_Q2_Q3_INFO_8822C);\n\tq4_q5_info = rtw_read32(adapter, REG_Q4_Q5_INFO_8822C);\n\tq6_q7_info = rtw_read32(adapter, REG_Q6_Q7_INFO_8822C);\n\tmg_hi_q_info = rtw_read32(adapter, REG_MGQ_HIQ_INFO_8822C);\n\tcmd_bcn_q_info = rtw_read32(adapter, REG_CMDQ_BCNQ_INFO_8822C);\n\n\tdump_qinfo(sel, (struct qinfo *)&q0_info, q0_q1_info&0xFFF, \"Q0 \");\n\tdump_qinfo(sel, (struct qinfo *)&q1_info, (q0_q1_info>>15)&0xFFF, \"Q1 \");\n\tdump_qinfo(sel, (struct qinfo *)&q2_info, q2_q3_info&0xFFF, \"Q2 \");\n\tdump_qinfo(sel, (struct qinfo *)&q3_info, (q2_q3_info>>15)&0xFFF, \"Q3 \");\n\tdump_qinfo(sel, (struct qinfo *)&q4_info, q4_q5_info&0xFFF, \"Q4 \");\n\tdump_qinfo(sel, (struct qinfo *)&q5_info, (q4_q5_info>>15)&0xFFF, \"Q5 \");\n\tdump_qinfo(sel, (struct qinfo *)&q6_info, q6_q7_info&0xFFF, \"Q6 \");\n\tdump_qinfo(sel, (struct qinfo *)&q7_info, (q6_q7_info>>15)&0xFFF, \"Q7 \");\n\tdump_qinfo(sel, (struct qinfo *)&mg_q_info, mg_hi_q_info&0xFFF, \"MG \");\n\tdump_qinfo(sel, (struct qinfo *)&hi_q_info, (mg_hi_q_info>>15)&0xFFF, \"HI \");\n\tdump_bcn_qinfo(sel, (struct bcn_qinfo *)&bcn_q_info, cmd_bcn_q_info&0xFFF, \"BCN \");\n\n}\n\nstatic void dump_mac_txfifo(void *sel, _adapter *adapter)\n{\n\tu32 hpq, lpq, npq, epq, pubq;\n\n\thpq = rtw_read32(adapter, REG_FIFOPAGE_INFO_1_8822C);\n\tlpq = rtw_read32(adapter, REG_FIFOPAGE_INFO_2_8822C);\n\tnpq = rtw_read32(adapter, REG_FIFOPAGE_INFO_3_8822C);\n\tepq = rtw_read32(adapter, REG_FIFOPAGE_INFO_4_8822C);\n\tpubq = rtw_read32(adapter, REG_FIFOPAGE_INFO_5_8822C);\n\n\thpq = (hpq & 0xFFF0000)>>16;\n\tlpq = (lpq & 0xFFF0000)>>16;\n\tnpq = (npq & 0xFFF0000)>>16;\n\tepq = (epq & 0xFFF0000)>>16;\n\tpubq = (pubq & 0xFFF0000)>>16;\n\n\tRTW_PRINT_SEL(sel, \"Tx: available page num: \");\n\tif ((hpq == 0xAEA) && (hpq == lpq) && (hpq == pubq))\n\t\tRTW_PRINT_SEL(sel, \"N/A (reg val = 0xea)\\n\");\n\telse\n\t\tRTW_PRINT_SEL(sel, \"HPQ: %d, LPQ: %d, NPQ: %d, EPQ: %d, PUBQ: %d\\n\"\n\t\t\t, hpq, lpq, npq, epq, pubq);\n}\n\nstatic u8 hw_var_get_bcn_valid(PADAPTER adapter)\n{\n\tu8 val8 = 0;\n\tu8 ret = _FALSE;\n\n\t/* only port 0 can TX BCN */\n\tval8 = rtw_read8(adapter, REG_FIFOPAGE_CTRL_2_8822C + 1);\n\tret = (BIT(7) & val8) ? _TRUE : _FALSE;\n\n\treturn ret;\n}\n\nvoid rtl8822c_read_wmmedca_reg(PADAPTER adapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params)\n{\n\tu8 vo_reg_params[4];\n\tu8 vi_reg_params[4];\n\tu8 be_reg_params[4];\n\tu8 bk_reg_params[4];\n\n\trtl8822c_gethwreg(adapter, HW_VAR_AC_PARAM_VO, vo_reg_params);\n\trtl8822c_gethwreg(adapter, HW_VAR_AC_PARAM_VI, vi_reg_params);\n\trtl8822c_gethwreg(adapter, HW_VAR_AC_PARAM_BE, be_reg_params);\n\trtl8822c_gethwreg(adapter, HW_VAR_AC_PARAM_BK, bk_reg_params);\n\n\tvo_params[0] = vo_reg_params[0];\n\tvo_params[1] = vo_reg_params[1] & 0x0F;\n\tvo_params[2] = (vo_reg_params[1] & 0xF0) >> 4;\n\tvo_params[3] = ((vo_reg_params[3] << 8) | (vo_reg_params[2])) * 32;\n\n\tvi_params[0] = vi_reg_params[0];\n\tvi_params[1] = vi_reg_params[1] & 0x0F;\n\tvi_params[2] = (vi_reg_params[1] & 0xF0) >> 4;\n\tvi_params[3] = ((vi_reg_params[3] << 8) | (vi_reg_params[2])) * 32;\n\n\tbe_params[0] = be_reg_params[0];\n\tbe_params[1] = be_reg_params[1] & 0x0F;\n\tbe_params[2] = (be_reg_params[1] & 0xF0) >> 4;\n\tbe_params[3] = ((be_reg_params[3] << 8) | (be_reg_params[2])) * 32;\n\n\tbk_params[0] = bk_reg_params[0];\n\tbk_params[1] = bk_reg_params[1] & 0x0F;\n\tbk_params[2] = (bk_reg_params[1] & 0xF0) >> 4;\n\tbk_params[3] = ((bk_reg_params[3] << 8) | (bk_reg_params[2])) * 32;\n\n\tvo_params[1] = (1 << vo_params[1]) - 1;\n\tvo_params[2] = (1 << vo_params[2]) - 1;\n\tvi_params[1] = (1 << vi_params[1]) - 1;\n\tvi_params[2] = (1 << vi_params[2]) - 1;\n\tbe_params[1] = (1 << be_params[1]) - 1;\n\tbe_params[2] = (1 << be_params[2]) - 1;\n\tbk_params[1] = (1 << bk_params[1]) - 1;\n\tbk_params[2] = (1 << bk_params[2]) - 1;\n}\n\nvoid rtl8822c_gethwreg(PADAPTER adapter, u8 variable, u8 *val)\n{\n\tPHAL_DATA_TYPE hal;\n\tu8 val8;\n\tu16 val16;\n\tu32 val32;\n\tu64 val64;\n\n\n\thal = GET_HAL_DATA(adapter);\n\n\tswitch (variable) {\n/*\n\tcase HW_VAR_INIT_RTS_RATE:\n\tcase HW_VAR_BASIC_RATE:\n\t\tbreak;\n*/\n\tcase HW_VAR_TXPAUSE:\n\t\t*val = rtw_read8(adapter, REG_TXPAUSE_8822C);\n\t\tbreak;\n/*\n\tcase HW_VAR_BCN_FUNC:\n\tcase HW_VAR_MLME_DISCONNECT:\n\tcase HW_VAR_MLME_SITESURVEY:\n\tcase HW_VAR_MLME_JOIN:\n\tcase HW_VAR_BEACON_INTERVAL:\n\tcase HW_VAR_SLOT_TIME:\n\tcase HW_VAR_RESP_SIFS:\n\tcase HW_VAR_ACK_PREAMBLE:\n\tcase HW_VAR_SEC_CFG:\n\tcase HW_VAR_SEC_DK_CFG:\n\t\tbreak;\n*/\n\tcase HW_VAR_BCN_VALID:\n\t\t*val = hw_var_get_bcn_valid(adapter);\n\t\tbreak;\n/*\n\tcase HW_VAR_RF_TYPE:\n\tcase HW_VAR_FREECNT:\n\tcase HW_VAR_CAM_INVALID_ALL:\n*/\n\tcase HW_VAR_AC_PARAM_VO:\n\t\tval32 = rtw_read32(adapter, REG_EDCA_VO_PARAM);\n\t\tval[0] = val32 & 0xFF;\n\t\tval[1] = (val32 >> 8) & 0xFF;\n\t\tval[2] = (val32 >> 16) & 0xFF;\n\t\tval[3] = (val32 >> 24) & 0x07;\n\t\tbreak;\n\n\tcase HW_VAR_AC_PARAM_VI:\n\t\tval32 = rtw_read32(adapter, REG_EDCA_VI_PARAM);\n\t\tval[0] = val32 & 0xFF;\n\t\tval[1] = (val32 >> 8) & 0xFF;\n\t\tval[2] = (val32 >> 16) & 0xFF;\n\t\tval[3] = (val32 >> 24) & 0x07;\n\t\tbreak;\n\n\tcase HW_VAR_AC_PARAM_BE:\n\t\tval32 = rtw_read32(adapter, REG_EDCA_BE_PARAM);\n\t\tval[0] = val32 & 0xFF;\n\t\tval[1] = (val32 >> 8) & 0xFF;\n\t\tval[2] = (val32 >> 16) & 0xFF;\n\t\tval[3] = (val32 >> 24) & 0x07;\n\t\tbreak;\n\n\tcase HW_VAR_AC_PARAM_BK:\n\t\tval32 = rtw_read32(adapter, REG_EDCA_BK_PARAM);\n\t\tval[0] = val32 & 0xFF;\n\t\tval[1] = (val32 >> 8) & 0xFF;\n\t\tval[2] = (val32 >> 16) & 0xFF;\n\t\tval[3] = (val32 >> 24) & 0x07;\n\t\tbreak;\n/*\n\tcase HW_VAR_ACM_CTRL:\n\tcase HW_VAR_AMPDU_MIN_SPACE:\n\tcase HW_VAR_AMPDU_FACTOR:\n\tcase HW_VAR_RXDMA_AGG_PG_TH:\n\tcase HW_VAR_SET_RPWM:\n\tcase HW_VAR_CPWM:\n\tcase HW_VAR_H2C_FW_PWRMODE:\n\tcase HW_VAR_H2C_PS_TUNE_PARAM:\n\tcase HW_VAR_H2C_FW_JOINBSSRPT:\n\t\tbreak;\n*/\n\tcase HW_VAR_FWLPS_RF_ON:\n\t\t/* When we halt NIC, we should check if FW LPS is leave. */\n\t\tif (rtw_is_surprise_removed(adapter) ||\n\t\t    (adapter_to_pwrctl(adapter)->rf_pwrstate == rf_off)) {\n\t\t\t/*\n\t\t\t * If it is in HW/SW Radio OFF or IPS state,\n\t\t\t * we do not check Fw LPS Leave,\n\t\t\t * because Fw is unload.\n\t\t\t */\n\t\t\t*val = _TRUE;\n\t\t} else {\n\t\t\trtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&val32);\n\n\t\t\tif (adapter_to_pwrctl(adapter)->wowlan_mode == _TRUE)\n\t\t\t\tval32 &= (BIT_UC_MD_EN_8822C | BIT_BC_MD_EN_8822C);\n\t\t\telse\n\t\t\t\tval32 &= (BIT_UC_MD_EN_8822C | BIT_BC_MD_EN_8822C | BIT_TIM_PARSER_EN_8822C);\n\n\t\t\tif (val32)\n\t\t\t\t*val = _FALSE;\n\t\t\telse\n\t\t\t\t*val = _TRUE;\n\t\t}\n\t\tbreak;\n/*\n\tcase HW_VAR_H2C_FW_P2P_PS_OFFLOAD:\n\tcase HW_VAR_TRIGGER_GPIO_0:\n\tcase HW_VAR_BT_SET_COEXIST:\n\tcase HW_VAR_BT_ISSUE_DELBA:\n\tcase HW_VAR_SWITCH_EPHY_WoWLAN:\n\tcase HW_VAR_EFUSE_USAGE:\n\tcase HW_VAR_EFUSE_BYTES:\n\tcase HW_VAR_EFUSE_BT_USAGE:\n\tcase HW_VAR_EFUSE_BT_BYTES:\n\tcase HW_VAR_FIFO_CLEARN_UP:\n\tcase HW_VAR_RESTORE_HW_SEQ:\n\tcase HW_VAR_CHECK_TXBUF:\n\tcase HW_VAR_PCIE_STOP_TX_DMA:\n\t\tbreak;\n*/\n\n/*\n\tcase HW_VAR_HCI_SUS_STATE:\n\t\tbreak;\n*/\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\n/*\n\tcase HW_VAR_WOWLAN:\n\t\tbreak;\n\n\tcase HW_VAR_WAKEUP_REASON:\n\t\trtw_halmac_get_wow_reason(adapter_to_dvobj(adapter), val);\n\t\tbreak;\n\n\tcase HW_VAR_RPWM_TOG:\n\t\tbreak;\n*/\n#endif\n/*\n#ifdef CONFIG_GPIO_WAKEUP\n\tcase HW_SET_GPIO_WL_CTRL:\n\t\tbreak;\n#endif\n*/\n\tcase HW_VAR_SYS_CLKR:\n\t\t*val = rtw_read8(adapter, REG_SYS_CLK_CTRL_8822C);\n\t\tbreak;\n/*\n\tcase HW_VAR_NAV_UPPER:\n\tcase HW_VAR_RPT_TIMER_SETTING:\n\tcase HW_VAR_TX_RPT_MAX_MACID:\n\t\tbreak;\n*/\n\tcase HW_VAR_CHK_HI_QUEUE_EMPTY:\n\t\tval16 = rtw_read16(adapter, REG_TXPKT_EMPTY_8822C);\n\t\t*val = (val16 & BIT_HQQ_EMPTY_8822C) ? _TRUE : _FALSE;\n\t\tbreak;\n\tcase HW_VAR_CHK_MGQ_CPU_EMPTY:\n\t\tval16 = rtw_read16(adapter, REG_TXPKT_EMPTY_8822C);\n\t\t*val = (val16 & BIT_MGQ_CPU_EMPTY_8822C) ? _TRUE : _FALSE;\n\t\tbreak;\n/*\n\tcase HW_VAR_DL_BCN_SEL:\n\tcase HW_VAR_AMPDU_MAX_TIME:\n\tcase HW_VAR_WIRELESS_MODE:\n\tcase HW_VAR_USB_MODE:\n\tcase HW_VAR_PORT_SWITCH:\n\tcase HW_VAR_DO_IQK:\n\tcase HW_VAR_SOUNDING_ENTER:\n\tcase HW_VAR_SOUNDING_LEAVE:\n\tcase HW_VAR_SOUNDING_RATE:\n\tcase HW_VAR_SOUNDING_STATUS:\n\tcase HW_VAR_SOUNDING_FW_NDPA:\n\tcase HW_VAR_SOUNDING_CLK:\n\tcase HW_VAR_HW_REG_TIMER_INIT:\n\tcase HW_VAR_HW_REG_TIMER_RESTART:\n\tcase HW_VAR_HW_REG_TIMER_START:\n\tcase HW_VAR_HW_REG_TIMER_STOP:\n\tcase HW_VAR_MACID_LINK:\n\tcase HW_VAR_MACID_NOLINK:\n\t\tbreak;\n*/\n\tcase HW_VAR_FW_PS_STATE:\n\t\t/* driver read REG_SYS_CFG5 - BIT_LPS_STATUS REG_1070[3] to get hw ps state */\n\t\t*((u16 *)val) = rtw_read8(adapter, REG_SYS_CFG5);\n\t\tbreak;\n\n\tcase HW_VAR_DUMP_MAC_QUEUE_INFO:\n\t\tdump_mac_qinfo(val, adapter);\n\t\tbreak;\n\n\tcase HW_VAR_DUMP_MAC_TXFIFO:\n\t\tdump_mac_txfifo(val, adapter);\n\t\tbreak;\n/*\n\tcase HW_VAR_ASIX_IOT:\n\tcase HW_VAR_EN_HW_UPDATE_TSF:\n\tcase HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO:\n\tcase HW_VAR_CH_SW_IQK_INFO_BACKUP:\n\tcase HW_VAR_CH_SW_IQK_INFO_RESTORE:\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\n\tcase HW_VAR_TDLS_BCN_EARLY_C2H_RPT:\n#endif\n#endif\n\t\tbreak;\n*/\n\n\tcase HW_VAR_BCN_CTRL_ADDR:\n\t\t*((u32 *)val) = hw_bcn_ctrl_addr(adapter, adapter->hw_port);\n\t\tbreak;\n\n\tdefault:\n\t\tGetHwReg(adapter, variable, val);\n\t\tbreak;\n\t}\n}\n\n/*\n * Description:\n *\tChange default setting of specified variable.\n */\nu8 rtl8822c_sethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval)\n{\n\tPHAL_DATA_TYPE hal;\n\tu8 bResult;\n\n\n\thal = GET_HAL_DATA(adapter);\n\tbResult = _SUCCESS;\n\n\tswitch (variable) {\n/*\n\tcase HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:\n\tcase HAL_DEF_IS_SUPPORT_ANT_DIV:\n\tcase HAL_DEF_DRVINFO_SZ:\n\tcase HAL_DEF_MAX_RECVBUF_SZ:\n\tcase HAL_DEF_RX_PACKET_OFFSET:\n\tcase HAL_DEF_RX_DMA_SZ_WOW:\n\tcase HAL_DEF_RX_DMA_SZ:\n\tcase HAL_DEF_RX_PAGE_SIZE:\n\tcase HAL_DEF_DBG_DUMP_RXPKT:\n\tcase HAL_DEF_RA_DECISION_RATE:\n\tcase HAL_DEF_RA_SGI:\n\tcase HAL_DEF_PT_PWR_STATUS:\n\tcase HAL_DEF_TX_LDPC:\n\tcase HAL_DEF_RX_LDPC:\n\tcase HAL_DEF_TX_STBC:\n\tcase HAL_DEF_RX_STBC:\n\tcase HAL_DEF_EXPLICIT_BEAMFORMER:\n\tcase HAL_DEF_EXPLICIT_BEAMFORMEE:\n\tcase HAL_DEF_VHT_MU_BEAMFORMER:\n\tcase HAL_DEF_VHT_MU_BEAMFORMEE:\n\tcase HAL_DEF_BEAMFORMER_CAP:\n\tcase HAL_DEF_BEAMFORMEE_CAP:\n\tcase HW_VAR_MAX_RX_AMPDU_FACTOR:\n\tcase HAL_DEF_DBG_DUMP_TXPKT:\n\tcase HAL_DEF_TX_PAGE_SIZE:\n\tcase HAL_DEF_TX_PAGE_BOUNDARY:\n\tcase HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN:\n\tcase HAL_DEF_ANT_DETECT:\n\tcase HAL_DEF_PCI_SUUPORT_L1_BACKDOOR:\n\tcase HAL_DEF_PCI_AMD_L1_SUPPORT:\n\tcase HAL_DEF_PCI_ASPM_OSC:\n\tcase HAL_DEF_EFUSE_USAGE:\n\tcase HAL_DEF_EFUSE_BYTES:\n\tcase HW_VAR_BEST_AMPDU_DENSITY:\n\t\tbreak;\n*/\n\tdefault:\n\t\tbResult = SetHalDefVar(adapter, variable, pval);\n\t\tbreak;\n\t}\n\n\treturn bResult;\n}\nvoid rtl8822c_ra_info_dump(_adapter *padapter, void *sel)\n{\n\tu8 mac_id;\n\tstruct sta_info *psta;\n\tu32 rate_mask1, rate_mask2;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\n\tfor (mac_id = 0; mac_id < macid_ctl->num; mac_id++) {\n\t\tif (rtw_macid_is_used(macid_ctl, mac_id) && !rtw_macid_is_bmc(macid_ctl, mac_id)) {\n\t\t\tpsta = macid_ctl->sta[mac_id];\n\t\t\tif (!psta)\n\t\t\t\tcontinue;\n\n\t\t\tdump_sta_info(sel, psta);\n\t\t\trate_mask1 = macid_ctl->rate_bmp0[mac_id];\n\t\t\trate_mask2 = macid_ctl->rate_bmp1[mac_id];\n\t\t\t_RTW_PRINT_SEL(sel, \"rate_mask2:0x%08x, rate_mask1:0x%08x\\n\", rate_mask2, rate_mask1);\n\t\t}\n\t}\n}\n/*\n * Description:\n *\tQuery setting of specified variable.\n */\nu8 rtl8822c_gethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval)\n{\n\tPHAL_DATA_TYPE hal;\n\tstruct dvobj_priv *d;\n\tu8 bResult;\n\tu8 val8 = 0;\n\tu32 val32 = 0;\n\n\n\td = adapter_to_dvobj(adapter);\n\thal = GET_HAL_DATA(adapter);\n\tbResult = _SUCCESS;\n\n\tswitch (variable) {\n/*\n\tcase HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:\n\t\tbreak;\n*/\n\tcase HAL_DEF_IS_SUPPORT_ANT_DIV:\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\t\t*(u8 *)pval = _TRUE;\n#else\n\t\t*(u8 *)pval = _FALSE;\n#endif\n\t\tbreak;\n\n/*\n\tcase HAL_DEF_DRVINFO_SZ:\n\t\tbreak;\n*/\n\tcase HAL_DEF_MAX_RECVBUF_SZ:\n\t\t*((u32 *)pval) = MAX_RECVBUF_SZ;\n\t\tbreak;\n\n\tcase HAL_DEF_RX_PACKET_OFFSET:\n\t\tval32 = rtl8822c_get_rx_desc_size(adapter);\n\t\tval8 = rtl8822c_get_rx_drv_info_size(adapter);\n\t\t*((u32 *)pval) = val32 + val8;\n\t\tbreak;\n/*\n\tcase HAL_DEF_RX_DMA_SZ_WOW:\n\tcase HAL_DEF_RX_DMA_SZ:\n\tcase HAL_DEF_RX_PAGE_SIZE:\n\tcase HAL_DEF_DBG_DUMP_RXPKT:\n\tcase HAL_DEF_RA_DECISION_RATE:\n\tcase HAL_DEF_RA_SGI:\n\t\tbreak;\n*/\n\t/* only for 8188E */\n\tcase HAL_DEF_PT_PWR_STATUS:\n\t\tbreak;\n\n\tcase HAL_DEF_TX_LDPC:\n\tcase HAL_DEF_RX_LDPC:\n\t\t*(u8 *)pval = _TRUE;\n\t\tbreak;\n\n\t/* support 1T STBC under 2TX */\n\tcase HAL_DEF_TX_STBC:\n#ifdef CONFIG_ALPHA_SMART_ANTENNA \n\t\t*(u8 *)pval = 0;\n#else\n\t\tif (hal->rf_type == RF_1T2R || hal->rf_type == RF_1T1R)\n\t\t\t*(u8 *)pval = 0;\n\t\telse\n\t\t\t*(u8 *)pval = 1;\n#endif\n\t\tbreak;\n\n\t/* support 1RX for STBC */\n\tcase HAL_DEF_RX_STBC:\n\t\t*(u8 *)pval = 1;\n\t\tbreak;\n\n\t/* support Explicit TxBF for HT/VHT */\n\tcase HAL_DEF_EXPLICIT_BEAMFORMER:\n\tcase HAL_DEF_EXPLICIT_BEAMFORMEE:\n\tcase HAL_DEF_VHT_MU_BEAMFORMER:\n\tcase HAL_DEF_VHT_MU_BEAMFORMEE:\n\t\t*(u8 *)pval = _TRUE;\n\t\tbreak;\n\n\tcase HAL_DEF_BEAMFORMER_CAP:\n\t\tval8 = 0;\n\t\trtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, &val8);\n\t\tswitch (val8) {\n\t\tcase RF_1T1R:\n\t\tcase RF_1T2R:\n\t\t\t*(u8 *)pval = 0;\n\t\t\tbreak;\n\t\tdefault:\n\t\tcase RF_2T2R:\n\t\t\t*(u8 *)pval = 1;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\n\tcase HAL_DEF_BEAMFORMEE_CAP:\n\t\t*(u8 *)pval = 3;\n\t\tbreak;\n\n\tcase HW_VAR_MAX_RX_AMPDU_FACTOR:\n\t\t/* 8822C RX FIFO is 24KB */\n\t\t*(HT_CAP_AMPDU_FACTOR *)pval = MAX_AMPDU_FACTOR_16K;\n\t\tbreak;\n\n\tcase HW_DEF_RA_INFO_DUMP:\n\t\trtl8822c_ra_info_dump(adapter, pval);\n\t\tbreak;\n/*\n\tcase HAL_DEF_DBG_DUMP_TXPKT:\n\tcase HAL_DEF_TX_PAGE_SIZE:\n\tcase HAL_DEF_TX_PAGE_BOUNDARY:\n\tcase HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN:\n\tcase HAL_DEF_ANT_DETECT:\n\tcase HAL_DEF_PCI_SUUPORT_L1_BACKDOOR:\n\tcase HAL_DEF_PCI_AMD_L1_SUPPORT:\n\tcase HAL_DEF_PCI_ASPM_OSC:\n\tcase HAL_DEF_EFUSE_USAGE:\n\tcase HAL_DEF_EFUSE_BYTES:\n\t\tbreak;\n*/\n\tcase HW_VAR_BEST_AMPDU_DENSITY:\n\t\t*((u32 *)pval) = AMPDU_DENSITY_VALUE_4;\n\t\tbreak;\n\n\tdefault:\n\t\tbResult = GetHalDefVar(adapter, variable, pval);\n\t\tbreak;\n\t}\n\n\treturn bResult;\n}\n\nvoid rtl8822c_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc)\n{\n\tif ((pattrib->encrypt > 0) && !pattrib->bswenc) {\n\t\t/* SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES */\n\t\tswitch (pattrib->encrypt) {\n\t\tcase _WEP40_:\n\t\tcase _WEP104_:\n\t\tcase _TKIP_:\n\t\tcase _TKIP_WTMIC_:\n\t\t\tSET_TX_DESC_SEC_TYPE_8822C(ptxdesc, 0x1);\n\t\t\tbreak;\n#ifdef CONFIG_WAPI_SUPPORT\n\t\tcase _SMS4_:\n\t\t\tSET_TX_DESC_SEC_TYPE_8822C(ptxdesc, 0x2);\n\t\t\tbreak;\n#endif\n\t\tcase _AES_:\n\t\t\tSET_TX_DESC_SEC_TYPE_8822C(ptxdesc, 0x3);\n\t\t\tbreak;\n\t\tcase _NO_PRIVACY_:\n\t\tdefault:\n\t\t\tSET_TX_DESC_SEC_TYPE_8822C(ptxdesc, 0x0);\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\nvoid rtl8822c_fill_txdesc_vcs(PADAPTER adapter, struct pkt_attrib *pattrib, u8 *ptxdesc)\n{\n\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\n\tif (pattrib->vcs_mode) {\n\t\tswitch (pattrib->vcs_mode) {\n\t\tcase RTS_CTS:\n\t\t\tSET_TX_DESC_RTSEN_8822C(ptxdesc, 1);\n\t\t\tbreak;\n\t\tcase CTS_TO_SELF:\n\t\t\tSET_TX_DESC_CTS2SELF_8822C(ptxdesc, 1);\n\t\t\tbreak;\n\t\tcase NONE_VCS:\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tif (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)\n\t\t\tSET_TX_DESC_RTS_SHORT_8822C(ptxdesc, 1);\n\n\t\t/* RTS Rate=24M */\n\t\tSET_TX_DESC_RTSRATE_8822C(ptxdesc, 0x8);\n\n\t\t/* compatibility for MCC consideration, use pmlmeext->cur_channel */\n\t\tif (pmlmeext->cur_channel > 14)\n\t\t\t/* RTS retry to rate OFDM 6M for 5G */\n\t\t\tSET_TX_DESC_RTS_RTY_LOWEST_RATE_8822C(ptxdesc, 4);\n\t\telse\n\t\t\t/* RTS retry to rate CCK 1M for 2.4G */\n\t\t\tSET_TX_DESC_RTS_RTY_LOWEST_RATE_8822C(ptxdesc, 0);\n\t}\n}\n\nu8 rtl8822c_bw_mapping(PADAPTER adapter, struct pkt_attrib *pattrib)\n{\n\tu8 BWSettingOfDesc = 0;\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\n\n\tif (hal->current_channel_bw == CHANNEL_WIDTH_80) {\n\t\tif (pattrib->bwmode == CHANNEL_WIDTH_80)\n\t\t\tBWSettingOfDesc = 2;\n\t\telse if (pattrib->bwmode == CHANNEL_WIDTH_40)\n\t\t\tBWSettingOfDesc = 1;\n\t\telse\n\t\t\tBWSettingOfDesc = 0;\n\t} else if (hal->current_channel_bw == CHANNEL_WIDTH_40) {\n\t\tif ((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80))\n\t\t\tBWSettingOfDesc = 1;\n\t\telse\n\t\t\tBWSettingOfDesc = 0;\n\t} else\n\t\tBWSettingOfDesc = 0;\n\n\treturn BWSettingOfDesc;\n}\n\nu8 rtl8822c_sc_mapping(PADAPTER adapter, struct pkt_attrib *pattrib)\n{\n\tu8 SCSettingOfDesc = 0;\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\n\n\tif (hal->current_channel_bw == CHANNEL_WIDTH_80) {\n\t\tif (pattrib->bwmode == CHANNEL_WIDTH_80)\n\t\t\tSCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;\n\t\telse if (pattrib->bwmode == CHANNEL_WIDTH_40) {\n\t\t\tif (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)\n\t\t\t\tSCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ;\n\t\t\telse if (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)\n\t\t\t\tSCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ;\n\t\t\telse\n\t\t\t\tRTW_INFO(\"SCMapping: DONOT CARE Mode Setting\\n\");\n\t\t} else {\n\t\t\tif ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))\n\t\t\t\tSCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ;\n\t\t\telse if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))\n\t\t\t\tSCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;\n\t\t\telse if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))\n\t\t\t\tSCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;\n\t\t\telse if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))\n\t\t\t\tSCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ;\n\t\t\telse\n\t\t\t\tRTW_INFO(\"SCMapping: DONOT CARE Mode Setting\\n\");\n\t\t}\n\t} else if (hal->current_channel_bw == CHANNEL_WIDTH_40) {\n\t\tif (pattrib->bwmode == CHANNEL_WIDTH_40)\n\t\t\tSCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;\n\t\telse if (pattrib->bwmode == CHANNEL_WIDTH_20) {\n\t\t\tif (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)\n\t\t\t\tSCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;\n\t\t\telse if (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)\n\t\t\t\tSCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;\n\t\t\telse\n\t\t\t\tSCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;\n\t\t}\n\t} else\n\t\tSCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;\n\n\treturn SCSettingOfDesc;\n}\n\nvoid rtl8822c_fill_txdesc_phy(PADAPTER adapter, struct pkt_attrib *pattrib, u8 *ptxdesc)\n{\n\tif (pattrib->ht_en) {\n\t\t/* Set Bandwidth and sub-channel settings. */\n\t\tSET_TX_DESC_DATA_BW_8822C(ptxdesc, rtl8822c_bw_mapping(adapter, pattrib));\n\t\tSET_TX_DESC_DATA_SC_8822C(ptxdesc, rtl8822c_sc_mapping(adapter, pattrib));\n\t}\n}\n\n/**\n * rtl8822c_fill_txdesc_tx_rate() - Set rate in tx description\n * @adapter\tstruct _ADAPTER*\n * @attrib\tpacket attribute\n * @rate\tDESC_RATE*\n * @shrt\t1/0 means short/long PLCP for CCK, short/long GI for HT/VHT\n * @fallback\tenable rate fallback or not\n * @desc\tbuffer of tx description\n *\n * Fill rate related fields of tx description when driver want to use specific\n * data rate to send this packet.\n */\nstatic void rtl8822c_fill_txdesc_tx_rate(struct _ADAPTER *adapter,\n\t\t\t\tstruct pkt_attrib *attrib,\n\t\t\t\tu8 rate, u8 shrt, u8 fallback, u8 *desc)\n{\n\tu8 disfb;\n\tu8 bw;\n\n\n\trate = rate & 0x7F;\n\tshrt = shrt ? 1 : 0;\n\tdisfb = fallback ? 0 : 1;\n\n\tSET_TX_DESC_USE_RATE_8822C(desc, 1);\n\tSET_TX_DESC_DATARATE_8822C(desc, rate);\n\tSET_TX_DESC_DATA_SHORT_8822C(desc, shrt);\n\tSET_TX_DESC_DISDATAFB_8822C(desc, disfb);\n\n\t/* HT MCS rate can't support bandwidth higher than 40MHz */\n\tbw = GET_TX_DESC_DATA_BW_8822C(desc);\n\tif (((rate >= DESC_RATEMCS0) && (rate <= DESC_RATEMCS31)) && (bw > 1)) {\n\t\tRTW_WARN(FUNC_ADPT_FMT \": Use HT rate(%s) on bandwidth \"\n\t\t\t \"higher than 40MHz(%u>%u) is illegal, \"\n\t\t\t \"switch bandwidth to 40MHz!\\n\",\n\t\t\t FUNC_ADPT_ARG(adapter),\n\t\t\t HDATA_RATE(rate), attrib->bwmode,\n\t\t\t CHANNEL_WIDTH_40);\n\n\t\tif (attrib->bwmode > CHANNEL_WIDTH_40)\n\t\t\tattrib->bwmode = CHANNEL_WIDTH_40;\n\t\trtl8822c_fill_txdesc_phy(adapter, attrib, desc);\n\t}\n}\n\n#ifdef CONFIG_CONCURRENT_MODE\nvoid rtl8822c_fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc)\n{\n\tif ((pattrib->encrypt > 0) && (!pattrib->bswenc)\n\t    && (pattrib->bmc_camid != INVALID_SEC_MAC_CAM_ID)) {\n\t\tSET_TX_DESC_EN_DESC_ID_8822C(ptxdesc, 1);\n\t\tSET_TX_DESC_MACID_8822C(ptxdesc, pattrib->bmc_camid);\n\t}\n}\n#endif\n\nvoid rtl8822c_fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc)\n{\n\tSET_TX_DESC_USE_RATE_8822C(ptxdesc, 1);\n\tSET_TX_DESC_DATARATE_8822C(ptxdesc, MRateToHwRate(pattrib->rate));\n\tSET_TX_DESC_DISDATAFB_8822C(ptxdesc, 1);\n}\n\n/*\n * Description:\n *\tFill tx description for beamforming packets\n */\nvoid rtl8822c_fill_txdesc_bf(struct xmit_frame *frame, u8 *desc)\n{\n#ifndef CONFIG_BEAMFORMING\n\treturn;\n#else /* CONFIG_BEAMFORMING */\n\tstruct pkt_attrib *attrib;\n\n\n\tattrib = &frame->attrib;\n\n\tSET_TX_DESC_G_ID_8822C(desc, attrib->txbf_g_id);\n\tSET_TX_DESC_P_AID_8822C(desc, attrib->txbf_p_aid);\n\n\tSET_TX_DESC_MU_DATARATE_8822C(desc, MRateToHwRate(attrib->rate));\n\t/*SET_TX_DESC_MU_RC_8822C(desc, 0);*/\n\n\t/* Force to disable STBC when txbf is enabled */\n\tif (attrib->txbf_p_aid && attrib->stbc)\n\t\tSET_TX_DESC_DATA_STBC_8822C(desc, 0);\n#endif /* CONFIG_BEAMFORMING */\n}\n\n/*\n * Description:\n *\tFill tx description for beamformer,\n *\tinclude following management packets:\n *\t1. VHT NDPA\n *\t2. HT NDPA\n *\t3. Beamforming Report Poll\n */\nvoid rtl8822c_fill_txdesc_mgnt_bf(struct xmit_frame *frame, u8 *desc)\n{\n#ifndef CONFIG_BEAMFORMING\n\treturn;\n#else /* CONFIG_BEAMFORMING */\n\tPADAPTER adapter;\n\tstruct pkt_attrib *attrib;\n\tu8 ndpa = 0;\n\tu8 ht_ndpa = 0;\n\tu8 report_poll = 0;\n\n\n\tadapter = frame->padapter;\n\tattrib = &frame->attrib;\n\n\tif (attrib->subtype == WIFI_NDPA)\n\t\tndpa = 1;\n\tif ((attrib->subtype == WIFI_ACTION_NOACK) && (attrib->order == 1))\n\t\tht_ndpa = 1;\n\tif (attrib->subtype == WIFI_BF_REPORT_POLL)\n\t\treport_poll = 1;\n\n\tif ((!ndpa) && (!ht_ndpa) && (!report_poll))\n\t\treturn;\n\n\t/*SET_TX_DESC_TXPKTSIZE_8822C(desc, pattrib->last_txcmdsz);*/\n\t/*SET_TX_DESC_OFFSET_8822C(desc, HALMAC_TX_DESC_SIZE_8822C);*/\n\tSET_TX_DESC_DISRTSFB_8822C(desc, 1);\n\tSET_TX_DESC_DISDATAFB(desc, 1);\n\t/*SET_TX_DESC_SW_SEQ_8822C(desc, pattrib->seqnum);*/\n\tSET_TX_DESC_DATA_BW_8822C(desc, rtl8822c_bw_mapping(adapter, attrib));\n\tSET_TX_DESC_SIGNALING_TA_PKT_SC_8822C(desc,\n\t\t\t\t\trtl8822c_sc_mapping(adapter, attrib));\n\t/*SET_TX_DESC_RTY_LMT_EN_8822C(ptxdesc, 1);*/\n\tSET_TX_DESC_RTS_DATA_RTY_LMT_8822C(desc, 5);\n\tSET_TX_DESC_NDPA_8822C(desc, 1);\n\tSET_TX_DESC_NAVUSEHDR_8822C(desc, 1);\n\t/*SET_TX_DESC_QSEL_8822C(desc, QSLT_MGNT);*/\n\t/*\n\t * NSS2MCS0 for VHT\n\t * MCS8 for HT\n\t */\n\tSET_TX_DESC_DATARATE_8822C(desc, MRateToHwRate(attrib->rate));\n\t/*SET_TX_DESC_USE_RATE_8822C(desc, 1);*/\n\t/*SET_TX_DESC_MACID_8822C(desc, pattrib->mac_id);*/ /* ad-hoc mode */\n\t/*SET_TX_DESC_G_ID_8822C(desc, 63);*/\n\t/*\n\t * partial AID of 1st STA, at infrastructure mode, either SU or MU; \n\t * MACID, at ad-hoc mode\n\t *\n\t * For WMAC to restore the received CSI report of STA1.\n\t * WMAC would set p_aid field to 0 in PLCP header for MU.\n\t */\n\t/*SET_TX_DESC_P_AID_8822C(desc, pattrib->txbf_p_aid);*/\n\tSET_TX_DESC_SND_PKT_SEL_8822C(desc, attrib->bf_pkt_type);\n#endif /* CONFIG_BEAMFORMING */\n}\n\nvoid rtl8822c_cal_txdesc_chksum(PADAPTER adapter, u8 *ptxdesc)\n{\n\tstruct halmac_adapter *halmac;\n\tstruct halmac_api *api;\n\n\n\thalmac = adapter_to_halmac(adapter);\n\tapi = HALMAC_GET_API(halmac);\n\n\tapi->halmac_fill_txdesc_checksum(halmac, ptxdesc);\n}\n\n\n#ifdef CONFIG_MP_INCLUDED\nvoid rtl8822c_prepare_mp_txdesc(PADAPTER adapter, struct mp_priv *pmp_priv)\n{\n\tu8 *desc;\n\tstruct pkt_attrib *attrib;\n\tu32 pkt_size;\n\ts32 bmcast;\n\tu32 desc_size;\n\tu8 data_rate, pwr_status, offset;\n\n\n\tdesc = pmp_priv->tx.desc;\n\tattrib = &pmp_priv->tx.attrib;\n\tpkt_size = attrib->last_txcmdsz;\n\tbmcast = IS_MCAST(attrib->ra);\n\tdesc_size = rtl8822c_get_tx_desc_size(adapter);\n\n\tSET_TX_DESC_LS_8822C(desc, 1);\n\tSET_TX_DESC_TXPKTSIZE_8822C(desc, pkt_size);\n\n\toffset = desc_size;\n\tSET_TX_DESC_OFFSET_8822C(desc, offset);\n#if defined(CONFIG_PCI_HCI)\n\tSET_TX_DESC_PKT_OFFSET_8822C(desc, 0); /* 8822CE pkt_offset is 0 */\n#else\n\tSET_TX_DESC_PKT_OFFSET_8822C(desc, 1);\n#endif\n\n\tif (bmcast)\n\t\tSET_TX_DESC_BMC_8822C(desc, 1);\n\n\tSET_TX_DESC_MACID_8822C(desc, attrib->mac_id);\n\tSET_TX_DESC_RATE_ID_8822C(desc, attrib->raid);\n\tSET_TX_DESC_QSEL_8822C(desc, attrib->qsel);\n\n\tif (pmp_priv->preamble)\n\t\tSET_TX_DESC_DATA_SHORT_8822C(desc, 1);\n\n\tif (!attrib->qos_en)\n\t\tSET_TX_DESC_EN_HWSEQ_8822C(desc, 1);\n\telse\n\t\tSET_TX_DESC_SW_SEQ_8822C(desc, attrib->seqnum);\n\n\tif (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)\n\t\tSET_TX_DESC_DATA_BW_8822C(desc, pmp_priv->bandwidth);\n\telse {\n\t\tRTW_ERR(\"%s: unknown bandwidth %d, use 20M\\n\",\n\t\t\t __FUNCTION__, pmp_priv->bandwidth);\n\t\tSET_TX_DESC_DATA_BW_8822C(desc, CHANNEL_WIDTH_20);\n\t}\n\n\tSET_TX_DESC_DISDATAFB_8822C(desc, 1);\n\tSET_TX_DESC_USE_RATE_8822C(desc, 1);\n\tSET_TX_DESC_DATARATE_8822C(desc, pmp_priv->rateidx);\n}\n#endif /* CONFIG_MP_INCLUDED */\n\nstatic void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)\n{\n\tPADAPTER adapter;\n\tPHAL_DATA_TYPE hal;\n\tstruct mlme_ext_priv *pmlmeext;\n\tstruct mlme_ext_info *pmlmeinfo;\n\tstruct pkt_attrib *pattrib;\n\ts32 bmcst;\n\tu32 desc_size;\n\tu8 hw_port;\n\n\tadapter = pxmitframe->padapter;\n\thal = GET_HAL_DATA(adapter);\n\tpmlmeext = &adapter->mlmeextpriv;\n\tpmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tpattrib = &pxmitframe->attrib;\n\tbmcst = IS_MCAST(pattrib->ra);\n\thw_port = rtw_hal_get_port(adapter);\n\n\tdesc_size = rtl8822c_get_tx_desc_size(adapter);\n\t_rtw_memset(pbuf, 0, desc_size);\n\n\tif (pxmitframe->frame_tag == DATA_FRAMETAG) {\n\t\tu8 drv_userate = 0;\n\n\t\tSET_TX_DESC_MACID_8822C(pbuf, pattrib->mac_id);\n\t\tSET_TX_DESC_RATE_ID_8822C(pbuf, pattrib->raid);\n\t\tSET_TX_DESC_QSEL_8822C(pbuf, pattrib->qsel);\n\t\tSET_TX_DESC_SW_SEQ_8822C(pbuf, pattrib->seqnum);\n\n\t\trtl8822c_fill_txdesc_sectype(pattrib, pbuf);\n\t\trtl8822c_fill_txdesc_vcs(adapter, pattrib, pbuf);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (bmcst)\n\t\t\trtl8822c_fill_txdesc_force_bmc_camid(pattrib, pbuf);\n#endif\n\n#ifdef CONFIG_P2P\n\t\tif (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) {\n\t\t\tif (pattrib->icmp_pkt == 1 && adapter->registrypriv.wifi_spec == 1)\n\t\t\t\tdrv_userate = 1;\n\t\t}\n#endif\n\n\t\tif ((pattrib->ether_type != 0x888e) &&\n\t\t    (pattrib->ether_type != 0x0806) &&\n\t\t    (pattrib->ether_type != 0x88B4) &&\n\t\t    (pattrib->dhcp_pkt != 1) &&\n\t\t    (drv_userate != 1)\n#ifdef CONFIG_AUTO_AP_MODE\n\t\t    && (pattrib->pctrl != _TRUE)\n#endif\n\t\t   ) {\n\t\t\t/* Non EAP & ARP & DHCP type data packet */\n\n\t\t\tif (pattrib->ampdu_en == _TRUE) {\n\t\t\t\tSET_TX_DESC_AGG_EN_8822C(pbuf, 1);\n\t\t\t\tSET_TX_DESC_MAX_AGG_NUM_8822C(pbuf, 0x1F);\n\t\t\t\tSET_TX_DESC_AMPDU_DENSITY_8822C(pbuf, pattrib->ampdu_spacing);\n\t\t\t} else\n\t\t\t\tSET_TX_DESC_BK_8822C(pbuf, 1);\n\n\t\t\trtl8822c_fill_txdesc_phy(adapter, pattrib, pbuf);\n\n\t\t\t/* compatibility for MCC consideration, use pmlmeext->cur_channel */\n\t\t\tif (!bmcst) {\n\t\t\t\tif (pmlmeext->cur_channel > 14)\n\t\t\t\t\t/* for 5G, OFDM 6M */\n\t\t\t\t\tSET_TX_DESC_DATA_RTY_LOWEST_RATE_8822C(pbuf, 4);\n\t\t\t\telse\n\t\t\t\t\t/* for 2.4G, CCK 1M */\n\t\t\t\t\tSET_TX_DESC_DATA_RTY_LOWEST_RATE_8822C(pbuf, 0);\n\t\t\t}\n\n\t\t\tif (hal->fw_ractrl == _FALSE)\n\t\t\t\trtl8822c_fill_txdesc_tx_rate(adapter, pattrib,\n\t\t\t\t\thal->INIDATA_RATE[pattrib->mac_id] & 0x7F,\n\t\t\t\t\thal->INIDATA_RATE[pattrib->mac_id] & BIT(7) ? 1 : 0,\n\t\t\t\t\t1, pbuf);\n\n\t\t\tif (bmcst) {\n\t\t\t\tSET_TX_DESC_SW_DEFINE_8822C(pbuf, 0x01);\n\t\t\t\trtl8822c_fill_txdesc_bmc_tx_rate(pattrib, pbuf);\n\t\t\t}\n\n\t\t\t/* modify data rate by iwpriv */\n\t\t\tif (adapter->fix_rate != 0xFF)\n\t\t\t\trtl8822c_fill_txdesc_tx_rate(adapter, pattrib,\n\t\t\t\t\tadapter->fix_rate & 0x7F,\n\t\t\t\t\tadapter->fix_rate & BIT(7) ? 1 : 0,\n\t\t\t\t\tadapter->data_fb, pbuf);\n\n\t\t\tif (pattrib->ldpc)\n\t\t\t\tSET_TX_DESC_DATA_LDPC_8822C(pbuf, 1);\n\t\t\tif (pattrib->stbc)\n\t\t\t\tSET_TX_DESC_DATA_STBC_8822C(pbuf, 1);\n\n#ifdef CONFIG_CMCC_TEST\n\t\t\tSET_TX_DESC_DATA_SHORT_8822C(pbuf, 1); /* use cck short premble */\n#endif\n\n#ifdef CONFIG_WMMPS_STA\n\t\t\tif (pattrib->trigger_frame)\n\t\t\t\tSET_TX_DESC_TRI_FRAME_8822C (pbuf, 1);\n#endif /* CONFIG_WMMPS_STA */\n\n\t\t} else {\n\t\t\t/*\n\t\t\t * EAP data packet and ARP packet.\n\t\t\t * Use the 1M data rate to send the EAP/ARP packet.\n\t\t\t * This will maybe make the handshake smooth.\n\t\t\t */\n\n\t\t\tSET_TX_DESC_BK_8822C(pbuf, 1);\n\t\t\tSET_TX_DESC_USE_RATE_8822C(pbuf, 1);\n\t\t\tif (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)\n\t\t\t\tSET_TX_DESC_DATA_SHORT_8822C(pbuf, 1);\n#ifdef CONFIG_IP_R_MONITOR\n\t\t\tif((pattrib->ether_type == ETH_P_ARP) &&\n\t\t\t\t(IsSupportedTxOFDM(adapter->registrypriv.wireless_mode))) \n\t\t\t\tSET_TX_DESC_DATARATE_8822C(pbuf, MRateToHwRate(IEEE80211_OFDM_RATE_6MB));\n\t\t\t else\n#endif/*CONFIG_IP_R_MONITOR*/\n\t\t\t\tSET_TX_DESC_DATARATE_8822C(pbuf, MRateToHwRate(pmlmeext->tx_rate));\n\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": SP Packet(0x%04X) rate=0x%x SeqNum = %d\\n\",\n\t\t\t\tFUNC_ADPT_ARG(adapter), pattrib->ether_type, MRateToHwRate(pmlmeext->tx_rate), pattrib->seqnum);\t\t\t\n\t\t}\n\n#if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t\tSET_TX_DESC_DMA_TXAGG_NUM_8822C(pbuf, pxmitframe->agg_num);\n#endif\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_XMIT_ACK\n\t\t/* CCX-TXRPT ack for xmit mgmt frames. */\n\t\tif (pxmitframe->ack_report) {\n#ifdef DBG_CCX\n\t\t\tRTW_INFO(\"%s set spe_rpt\\n\", __func__);\n#endif\n\t\t\tSET_TX_DESC_SPE_RPT_8822C(pbuf, 1);\n\t\t\tSET_TX_DESC_SW_DEFINE_8822C(pbuf, (u8)(GET_PRIMARY_ADAPTER(adapter)->xmitpriv.seq_no));\n\t\t}\n#endif /* CONFIG_XMIT_ACK */\n#endif\n\t} else if (pxmitframe->frame_tag == MGNT_FRAMETAG) {\n\t\tSET_TX_DESC_MACID_8822C(pbuf, pattrib->mac_id);\n\t\tSET_TX_DESC_QSEL_8822C(pbuf, pattrib->qsel);\n\t\tSET_TX_DESC_RATE_ID_8822C(pbuf, pattrib->raid);\n\t\tSET_TX_DESC_SW_SEQ_8822C(pbuf, pattrib->seqnum);\n\t\tSET_TX_DESC_USE_RATE_8822C(pbuf, 1);\n\n\t\tSET_TX_DESC_MBSSID_8822C(pbuf, pattrib->mbssid & 0xF);\n\n\t\tSET_TX_DESC_DATARATE_8822C(pbuf, MRateToHwRate(pattrib->rate));\n\n\t\tSET_TX_DESC_RTY_LMT_EN_8822C(pbuf, 1);\n\t\tif (pattrib->retry_ctrl == _TRUE)\n\t\t\tSET_TX_DESC_RTS_DATA_RTY_LMT_8822C(pbuf, 6);\n\t\telse\n\t\t\tSET_TX_DESC_RTS_DATA_RTY_LMT_8822C(pbuf, 12);\n\n\t\trtl8822c_fill_txdesc_mgnt_bf(pxmitframe, pbuf);\n\n#ifdef CONFIG_XMIT_ACK\n\t\t/* CCX-TXRPT ack for xmit mgmt frames. */\n\t\tif (pxmitframe->ack_report) {\n#ifdef DBG_CCX\n\t\t\tRTW_INFO(\"%s set spe_rpt\\n\", __FUNCTION__);\n#endif\n\t\t\tSET_TX_DESC_SPE_RPT_8822C(pbuf, 1);\n\t\t\tSET_TX_DESC_SW_DEFINE_8822C(pbuf, (u8)(GET_PRIMARY_ADAPTER(adapter)->xmitpriv.seq_no));\n\t\t}\n#endif /* CONFIG_XMIT_ACK */\n\t} else if (pxmitframe->frame_tag == TXAGG_FRAMETAG)\n\t\tRTW_INFO(\"%s: TXAGG_FRAMETAG\\n\", __FUNCTION__);\n#ifdef CONFIG_MP_INCLUDED\n\telse if (pxmitframe->frame_tag == MP_FRAMETAG) {\n\t\tRTW_DBG(\"%s: MP_FRAMETAG\\n\", __FUNCTION__);\n\t\tfill_txdesc_for_mp(adapter, pbuf);\n\t}\n#endif\n\telse {\n\t\tRTW_INFO(\"%s: frame_tag=0x%x\\n\", __FUNCTION__, pxmitframe->frame_tag);\n\n\t\tSET_TX_DESC_MACID_8822C(pbuf, pattrib->mac_id);\n\t\tSET_TX_DESC_RATE_ID_8822C(pbuf, pattrib->raid);\n\t\tSET_TX_DESC_QSEL_8822C(pbuf, pattrib->qsel);\n\t\tSET_TX_DESC_SW_SEQ_8822C(pbuf, pattrib->seqnum);\n\t\tSET_TX_DESC_USE_RATE_8822C(pbuf, 1);\n\t\tSET_TX_DESC_DATARATE_8822C(pbuf, MRateToHwRate(pmlmeext->tx_rate));\n\t}\n\n\tSET_TX_DESC_TXPKTSIZE_8822C(pbuf, pattrib->last_txcmdsz);\n\n\t{\n\t\tu8 pkt_offset, offset;\n\n\t\tpkt_offset = 0;\n\t\toffset = desc_size;\n#ifdef CONFIG_USB_HCI\n\t\tpkt_offset = pxmitframe->pkt_offset;\n\t\toffset += (pxmitframe->pkt_offset >> 3);\n#endif /* CONFIG_USB_HCI */\n\n#ifdef CONFIG_TX_EARLY_MODE\n\t\tif (pxmitframe->frame_tag == DATA_FRAMETAG) {\n\t\t\tpkt_offset = 1;\n\t\t\toffset += EARLY_MODE_INFO_SIZE;\n\t\t}\n#endif /* CONFIG_TX_EARLY_MODE */\n\n\t\tSET_TX_DESC_PKT_OFFSET_8822C(pbuf, pkt_offset);\n\t\tSET_TX_DESC_OFFSET_8822C(pbuf, offset);\n#ifdef CONFIG_TX_CSUM_OFFLOAD\n\tif (pattrib->hw_csum == 1) {\n\t\tint offset = 48 + pkt_offset*8 + 24;\n\n\t\tSET_TX_DESC_OFFSET_8822C(pbuf, offset);\n\t\tSET_TX_DESC_CHK_EN_8822C(pbuf, 1);\n\t\tSET_TX_DESC_WHEADER_LEN_8822C(pbuf, (pattrib->hdrlen + pattrib->iv_len)>>1);\n\t}\n#endif\n\t}\n\n\tif (bmcst)\n\t\tSET_TX_DESC_BMC_8822C(pbuf, 1);\n\n\t/*\n\t * 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS.\n\t * (1) The sequence number of each non-Qos frame / broadcast / multicast /\n\t * mgnt frame should be controlled by Hw because Fw will also send null data\n\t * which we cannot control when Fw LPS enable.\n\t * --> default enable non-Qos data sequense number. 2010.06.23. by tynli.\n\t * (2) Enable HW SEQ control for beacon packet, because we use Hw beacon.\n\t * (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets.\n\t * 2010.06.23. Added by tynli.\n\t */\n\tif (!pattrib->qos_en) {\n\t\tSET_TX_DESC_DISQSELSEQ_8822C(pbuf, 1);\n\t\tSET_TX_DESC_EN_HWSEQ_8822C(pbuf, 1);\n\t\tSET_TX_DESC_HW_SSN_SEL_8822C(pbuf, pattrib->hw_ssn_sel);\n\t}\n\n\tSET_TX_DESC_PORT_ID_8822C(pbuf, hw_port);\n\tSET_TX_DESC_MULTIPLE_PORT_8822C(pbuf, hw_port);\n\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\tif (!bmcst && pattrib->psta)\n\t\todm_set_tx_ant_by_tx_info(adapter_to_phydm(adapter), pbuf, pattrib->psta->cmn.mac_id);\n#endif\n\n\trtl8822c_fill_txdesc_bf(pxmitframe, pbuf);\n}\n\n/*\n * Description:\n *\n * Parameters:\n *\tpxmitframe\txmitframe\n *\tpbuf\t\twhere to fill tx desc\n */\nvoid rtl8822c_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)\n{\n\tfill_default_txdesc(pxmitframe, pbuf);\n\trtl8822c_cal_txdesc_chksum(pxmitframe->padapter, pbuf);\n}\n\n/*\n * Description:\n *\tIn normal chip, we should send some packet to HW which will be used by FW\n *\tin FW LPS mode.\n *\tThe function is to fill the Tx descriptor of this packets,\n *\tthen FW can tell HW to send these packet directly.\n */\nstatic void fill_fake_txdesc(PADAPTER adapter, u8 *pDesc, u32 BufferLen,\n\t\t\t     u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame)\n{\n\t/* Clear all status */\n\tstruct mlme_ext_priv\t*pmlmeext = &adapter->mlmeextpriv;\n\tstruct xmit_priv\t\t*pxmitpriv = &adapter->xmitpriv;\n\tu32 desc_size;\n\tu8 hw_port = rtw_hal_get_port(adapter);\n\n\n\tdesc_size = rtl8822c_get_tx_desc_size(adapter);\n\t_rtw_memset(pDesc, 0, desc_size);\n\n\tSET_TX_DESC_LS_8822C(pDesc, 1);\n\n\tSET_TX_DESC_OFFSET_8822C(pDesc, desc_size);\n\n\tSET_TX_DESC_TXPKTSIZE_8822C(pDesc, BufferLen);\n\tSET_TX_DESC_QSEL_8822C(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */\n\n\tif (pmlmeext->cur_wireless_mode & WIRELESS_11B)\n\t\tSET_TX_DESC_RATE_ID_8822C(pDesc, RATEID_IDX_B);\n\telse\n\t\tSET_TX_DESC_RATE_ID_8822C(pDesc, RATEID_IDX_G);\n\n\t/* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by HW */\n\tif (_TRUE == IsPsPoll)\n\t\tSET_TX_DESC_NAVUSEHDR_8822C(pDesc, 1);\n\telse {\n\t\tSET_TX_DESC_DISQSELSEQ_8822C(pDesc, 1);\n\t\tSET_TX_DESC_EN_HWSEQ_8822C(pDesc, 1);\n\t\tSET_TX_DESC_HW_SSN_SEL_8822C(pDesc, pxmitpriv->hw_ssn_seq_no);/*pattrib->hw_ssn_sel*/\n\t\tSET_TX_DESC_EN_HWEXSEQ_8822C(pDesc, 0);\n\t}\n\n\tif (_TRUE == IsBTQosNull)\n\t\tSET_TX_DESC_BT_NULL_8822C(pDesc, 1);\n\n\tSET_TX_DESC_USE_RATE_8822C(pDesc, 1);\n\tSET_TX_DESC_DATARATE_8822C(pDesc, MRateToHwRate(pmlmeext->tx_rate));\n\n#ifdef CONFIG_MCC_MODE\n\t/* config Null data retry number */\n\tif (IsPsPoll == _FALSE && IsBTQosNull == _FALSE && bDataFrame == _FALSE) {\n\t\tif (rtw_hal_check_mcc_status(adapter, MCC_STATUS_PROCESS_MCC_START_SETTING)) {\n\t\t\tu8 rty_num = adapter->mcc_adapterpriv.null_rty_num;\n\t\t\tif (rty_num != 0) {\n\t\t\t\tSET_TX_DESC_RTY_LMT_EN_8822C(pDesc, 1);\n\t\t\t\tSET_TX_DESC_RTS_DATA_RTY_LMT_8822C(pDesc, rty_num);\n\t\t\t}\n\t\t}\n\t}\n#endif\n\n\n\t/*\n\t * Encrypt the data frame if under security mode excepct null data.\n\t */\n\tif (_TRUE == bDataFrame) {\n\t\tu32 EncAlg;\n\n\t\tEncAlg = adapter->securitypriv.dot11PrivacyAlgrthm;\n\t\tswitch (EncAlg) {\n\t\tcase _NO_PRIVACY_:\n\t\t\tSET_TX_DESC_SEC_TYPE_8822C(pDesc, 0x0);\n\t\t\tbreak;\n\t\tcase _WEP40_:\n\t\tcase _WEP104_:\n\t\tcase _TKIP_:\n\t\t\tSET_TX_DESC_SEC_TYPE_8822C(pDesc, 0x1);\n\t\t\tbreak;\n\t\tcase _SMS4_:\n\t\t\tSET_TX_DESC_SEC_TYPE_8822C(pDesc, 0x2);\n\t\t\tbreak;\n\t\tcase _AES_:\n\t\t\tSET_TX_DESC_SEC_TYPE_8822C(pDesc, 0x3);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tSET_TX_DESC_SEC_TYPE_8822C(pDesc, 0x0);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tSET_TX_DESC_PORT_ID_8822C(pDesc, hw_port);\n\tSET_TX_DESC_MULTIPLE_PORT_8822C(pDesc, hw_port);\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t/*\n\t * USB interface drop packet if the checksum of descriptor isn't correct.\n\t * Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.).\n\t */\n\trtl8822c_cal_txdesc_chksum(adapter, pDesc);\n#endif\n}\n\nvoid rtl8822c_dbg_dump_tx_desc(PADAPTER adapter, int frame_tag, u8 *ptxdesc)\n{\n\tu8 bDumpTxPkt;\n\tu8 bDumpTxDesc = _FALSE;\n\n\n\trtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_TXPKT, &bDumpTxPkt);\n\n\t/* 1 for data frame, 2 for mgnt frame */\n\tif (bDumpTxPkt == 1) {\n\t\tRTW_INFO(\"dump tx_desc for data frame\\n\");\n\t\tif ((frame_tag & 0x0f) == DATA_FRAMETAG)\n\t\t\tbDumpTxDesc = _TRUE;\n\t} else if (bDumpTxPkt == 2) {\n\t\tRTW_INFO(\"dump tx_desc for mgnt frame\\n\");\n\t\tif ((frame_tag & 0x0f) == MGNT_FRAMETAG)\n\t\t\tbDumpTxDesc = _TRUE;\n\t}\n\n\t/* 8822C TX SIZE = 48(HALMAC_TX_DESC_SIZE_8822C) */\n\tif (_TRUE == bDumpTxDesc) {\n\t\tRTW_INFO(\"=====================================\\n\");\n\t\tRTW_INFO(\"Offset00(0x%08x)\\n\", *((u32 *)(ptxdesc)));\n\t\tRTW_INFO(\"Offset04(0x%08x)\\n\", *((u32 *)(ptxdesc + 4)));\n\t\tRTW_INFO(\"Offset08(0x%08x)\\n\", *((u32 *)(ptxdesc + 8)));\n\t\tRTW_INFO(\"Offset12(0x%08x)\\n\", *((u32 *)(ptxdesc + 12)));\n\t\tRTW_INFO(\"Offset16(0x%08x)\\n\", *((u32 *)(ptxdesc + 16)));\n\t\tRTW_INFO(\"Offset20(0x%08x)\\n\", *((u32 *)(ptxdesc + 20)));\n\t\tRTW_INFO(\"Offset24(0x%08x)\\n\", *((u32 *)(ptxdesc + 24)));\n\t\tRTW_INFO(\"Offset28(0x%08x)\\n\", *((u32 *)(ptxdesc + 28)));\n\t\tRTW_INFO(\"Offset32(0x%08x)\\n\", *((u32 *)(ptxdesc + 32)));\n\t\tRTW_INFO(\"Offset36(0x%08x)\\n\", *((u32 *)(ptxdesc + 36)));\n\t\tRTW_INFO(\"Offset40(0x%08x)\\n\", *((u32 *)(ptxdesc + 40)));\n\t\tRTW_INFO(\"Offset44(0x%08x)\\n\", *((u32 *)(ptxdesc + 44)));\n\t\tRTW_INFO(\"=====================================\\n\");\n\t}\n}\n/* xmit section */\nvoid rtl8822c_init_xmit_priv(_adapter *adapter)\n{\n\tstruct xmit_priv *pxmitpriv = &adapter->xmitpriv;\n\n\tpxmitpriv->hw_ssn_seq_no = rtw_get_hwseq_no(adapter);\n\tpxmitpriv->nqos_ssn = 0;\n}\n\nvoid rtl8822c_rxdesc2attribute(struct rx_pkt_attrib *a, u8 *desc)\n{\n\t/* initial value */\n\t_rtw_memset(a, 0, sizeof(struct rx_pkt_attrib));\n\ta->bw = CHANNEL_WIDTH_MAX;\n\n\t/* Get from RX DESC */\n\ta->pkt_len = (u16)GET_RX_DESC_PKT_LEN_8822C(desc);\n\ta->pkt_rpt_type = GET_RX_DESC_C2H_8822C(desc) ? C2H_PACKET : NORMAL_RX;\n\n\tif (a->pkt_rpt_type == NORMAL_RX) {\n\t\ta->crc_err = (u8)GET_RX_DESC_CRC32_8822C(desc);\n\t\ta->icv_err = (u8)GET_RX_DESC_ICV_ERR_8822C(desc);\n\t\ta->drvinfo_sz = (u8)GET_RX_DESC_DRV_INFO_SIZE_8822C(desc) << 3;\n\t\ta->encrypt = (u8)GET_RX_DESC_SECURITY_8822C(desc);\n\t\ta->qos = (u8)GET_RX_DESC_QOS_8822C(desc);\n\t\ta->shift_sz = (u8)GET_RX_DESC_SHIFT_8822C(desc);\n\t\ta->physt = (u8)GET_RX_DESC_PHYST_8822C(desc);\n\t\ta->bdecrypted = (u8)GET_RX_DESC_SWDEC_8822C(desc) ? 0 : 1;\n\n\t\ta->priority = (u8)GET_RX_DESC_TID_8822C(desc);\n\t\ta->amsdu = (u8)GET_RX_DESC_AMSDU_8822C(desc);\n\t\ta->mdata = (u8)GET_RX_DESC_MD_8822C(desc);\n\t\ta->mfrag = (u8)GET_RX_DESC_MF_8822C(desc);\n\n\t\ta->seq_num = (u16)GET_RX_DESC_SEQ_8822C(desc);\n\t\ta->frag_num = (u8)GET_RX_DESC_FRAG_8822C(desc);\n\n\t\ta->data_rate = (u8)GET_RX_DESC_RX_RATE_8822C(desc);\n\t\ta->ppdu_cnt = (u8)GET_RX_DESC_PPDU_CNT_8822C(desc);\n\t\ta->free_cnt = (u32)GET_RX_DESC_TSFL_8822C(desc);\n\n#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX\n\t\t/* RX TCP checksum offload related variables */\n\t\ta->csum_valid = (u8)GET_RX_DESC_CHK_VLD_8822C(desc);\n\t\ta->csum_err = (u8)GET_RX_DESC_CHKERR_8822C(desc);\n#endif /* CONFIG_TCP_CSUM_OFFLOAD_RX */\n\t}\n}\n\nvoid rtl8822c_query_rx_desc(union recv_frame *precvframe, u8 *pdesc)\n{\n\trtl8822c_rxdesc2attribute(&precvframe->u.hdr.attrib, pdesc);\n}\n\nvoid rtl8822c_set_hal_ops(PADAPTER adapter)\n{\n\tstruct hal_com_data *hal;\n\tstruct hal_ops *ops;\n\n\n\thal = GET_HAL_DATA(adapter);\n\tops = &adapter->hal_func;\n\n\t/*\n\t * Initialize hal_com_data variables\n\t */\n\thal->efuse0x3d7 = 0xFF;\n\thal->efuse0x3d8 = 0xFF;\n\n\t/*\n\t * Initialize operation callback functions\n\t */\n\t/*** initialize section ***/\n\tops->read_chip_version = read_chip_version;\n/*\n\tops->init_default_value = NULL;\n\tops->intf_chip_configure = NULL;\n*/\n\tops->read_adapter_info = rtl8822c_read_efuse;\n\tops->hal_power_on = rtl8822c_power_on;\n\tops->hal_power_off = rtl8822c_power_off;\n\tops->hal_init = rtl8822c_init;\n\tops->hal_deinit = rtl8822c_deinit;\n\tops->dm_init = rtl8822c_phy_init_dm_priv;\n\tops->dm_deinit = rtl8822c_phy_deinit_dm_priv;\n\n\t/*** xmit section ***/\n/*\n\tops->init_xmit_priv = NULL;\n\tops->free_xmit_priv = NULL;\n\tops->hal_xmit = NULL;\n\tops->mgnt_xmit = NULL;\n\tops->hal_xmitframe_enqueue = NULL;\n#ifdef CONFIG_XMIT_THREAD_MODE\n\tops->xmit_thread_handler = NULL;\n#endif\n*/\n\tops->run_thread = rtl8822c_run_thread;\n\tops->cancel_thread = rtl8822c_cancel_thread;\n\n\t/*** recv section ***/\n/*\n\tops->init_recv_priv = NULL;\n\tops->free_recv_priv = NULL;\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)\n\tops->inirp_init = NULL;\n\tops->inirp_deinit = NULL;\n#endif\n*/\n\t/*** interrupt hdl section ***/\n/*\n\tops->enable_interrupt = NULL;\n\tops->disable_interrupt = NULL;\n*/\n\tops->check_ips_status = check_ips_status;\n/*\n#if defined(CONFIG_PCI_HCI)\n\tops->interrupt_handler = NULL;\n#endif\n#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)\n\tops->interrupt_handler = NULL;\n#endif\n#if defined(CONFIG_PCI_HCI)\n\tops->irp_reset = NULL;\n#endif\n*/\n\n\t/*** DM section ***/\n\tops->set_chnl_bw_handler = rtl8822c_set_channel_bw;\n\n\tops->set_tx_power_level_handler = rtl8822c_set_tx_power_level;\n\tops->set_txpwr_done = rtl8822c_set_txpwr_done;\n\tops->set_tx_power_index_handler = rtl8822c_set_tx_power_index;\n\tops->get_tx_power_index_handler = rtl8822c_get_tx_power_index;\n\n\tops->hal_dm_watchdog = rtl8822c_phy_haldm_watchdog;\n\n\tops->set_hw_reg_handler = rtl8822c_sethwreg;\n\tops->GetHwRegHandler = rtl8822c_gethwreg;\n\tops->get_hal_def_var_handler = rtl8822c_gethaldefvar;\n\tops->SetHalDefVarHandler = rtl8822c_sethaldefvar;\n\n\tops->GetHalODMVarHandler = GetHalODMVar;\n\tops->SetHalODMVarHandler = SetHalODMVar;\n\n\tops->SetBeaconRelatedRegistersHandler = set_beacon_related_registers;\n\n/*\n\tops->interface_ps_func = NULL;\n*/\n\tops->read_bbreg = rtl8822c_read_bb_reg;\n\tops->write_bbreg = rtl8822c_write_bb_reg;\n\tops->read_rfreg = rtl8822c_read_rf_reg;\n\tops->write_rfreg = rtl8822c_write_rf_reg;\n\tops->read_wmmedca_reg = rtl8822c_read_wmmedca_reg;\n\n#ifdef CONFIG_HOSTAPD_MLME\n/*\n\tops->hostap_mgnt_xmit_entry = NULL;\n*/\n#endif\n/*\n\tops->EfusePowerSwitch = NULL;\n\tops->BTEfusePowerSwitch = NULL;\n\tops->ReadEFuse = NULL;\n\tops->EFUSEGetEfuseDefinition = NULL;\n\tops->EfuseGetCurrentSize = NULL;\n\tops->Efuse_PgPacketRead = NULL;\n\tops->Efuse_PgPacketWrite = NULL;\n\tops->Efuse_WordEnableDataWrite = NULL;\n\tops->Efuse_PgPacketWrite_BT = NULL;\n*/\n#ifdef DBG_CONFIG_ERROR_DETECT\n\tops->sreset_init_value = sreset_init_value;\n\tops->sreset_reset_value = sreset_reset_value;\n\tops->silentreset = sreset_reset;\n\tops->sreset_xmit_status_check = xmit_status_check;\n\tops->sreset_linked_status_check = linked_status_check;\n\tops->sreset_get_wifi_status = sreset_get_wifi_status;\n\tops->sreset_inprogress = sreset_inprogress;\n#endif /* DBG_CONFIG_ERROR_DETECT */\n\n#ifdef CONFIG_IOL\n/*\n\tops->IOL_exec_cmds_sync = NULL;\n*/\n#endif\n\n\tops->hal_notch_filter = rtl8822c_notch_filter_switch;\n\tops->hal_mac_c2h_handler = rtl8822c_c2h_handler;\n\tops->fill_h2c_cmd = rtl8822c_fillh2ccmd;\n\tops->fill_fake_txdesc = fill_fake_txdesc;\n\tops->fw_dl = rtl8822c_fw_dl;\n\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_PCI_HCI)\n/*\n\tops->clear_interrupt = NULL;\n*/\n#endif\n/*\n\tops->hal_get_tx_buff_rsvd_page_num = NULL;\n*/\n#ifdef CONFIG_GPIO_API\n/*\n\tops->update_hisr_hsisr_ind = NULL;\n*/\n#endif\n\n\t/* HALMAC related functions */\n\tops->init_mac_register = rtl8822c_phy_init_mac_register;\n\tops->init_phy = rtl8822c_phy_init;\n\tops->reqtxrpt = rtl8822c_req_txrpt_cmd;\n}\n\n"
  },
  {
    "path": "hal/rtl8822c/rtl8822c_phy.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RTL8822C_PHY_C_\n\n#include <hal_data.h>\t\t/* HAL_DATA_TYPE */\n#include \"../hal_halmac.h\"\t/* rtw_halmac_phy_power_switch() */\n#include \"rtl8822c.h\"\n\n\n/*\n * Description:\n *\tInitialize Register definition offset for Radio Path A/B/C/D\n *\tThe initialization value is constant and it should never be changes\n */\nstatic void bb_rf_register_definition(PADAPTER adapter)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\n\n\t/* RF Interface Sowrtware Control */\n\thal->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;\n\thal->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;\n\n\t/* RF Interface Output (and Enable) */\n\thal->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;\n\thal->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;\n\n\t/* RF Interface (Output and) Enable */\n\thal->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;\n\thal->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;\n\n\thal->PHYRegDef[RF_PATH_A].rf3wireOffset = rA_LSSIWrite_Jaguar;\n\thal->PHYRegDef[RF_PATH_B].rf3wireOffset = rB_LSSIWrite_Jaguar;\n\n\thal->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rHSSIRead_Jaguar;\n\thal->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rHSSIRead_Jaguar;\n\n\t/* Tranceiver Readback LSSI/HSPI mode */\n\thal->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rA_SIRead_Jaguar;\n\thal->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rB_SIRead_Jaguar;\n\thal->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = rA_PIRead_Jaguar;\n\thal->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = rB_PIRead_Jaguar;\n}\n\n/*\n * Description:\n *\tInitialize MAC registers\n *\n * Return:\n *\t_TRUE\tSuccess\n *\t_FALSE\tFail\n */\nu8 rtl8822c_phy_init_mac_register(PADAPTER adapter)\n{\n\tPHAL_DATA_TYPE hal;\n\tu8 ret = _TRUE;\n\tint res;\n\tenum hal_status status;\n\n\n\thal = GET_HAL_DATA(adapter);\n\n\tret = _FALSE;\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\tres = phy_ConfigMACWithParaFile(adapter, PHY_FILE_MAC_REG);\n\tif (_SUCCESS == res)\n\t\tret = _TRUE;\n#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */\n\tif (_FALSE == ret) {\n\t\tstatus = odm_config_mac_with_header_file(&hal->odmpriv);\n\t\tif (HAL_STATUS_SUCCESS == status)\n\t\t\tret = _TRUE;\n\t}\n\tif (_FALSE == ret)\n\t\tRTW_INFO(\"%s: Write MAC Reg Fail!!\", __FUNCTION__);\n\n\treturn ret;\n}\n\nstatic u8 _init_bb_reg(PADAPTER Adapter)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(Adapter);\n\tu8 ret = _TRUE;\n\tint res;\n\tenum hal_status status;\n\n\t/*\n\t * 1. Read PHY_REG.TXT BB INIT!!\n\t */\n\tret = _FALSE;\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\tres = phy_ConfigBBWithParaFile(Adapter, PHY_FILE_PHY_REG, CONFIG_BB_PHY_REG);\n\tif (_SUCCESS == res)\n\t\tret = _TRUE;\n#endif\n\tif (_FALSE == ret) {\n\t\tstatus = odm_config_bb_with_header_file(&hal->odmpriv, CONFIG_BB_PHY_REG);\n\t\tif (HAL_STATUS_SUCCESS == status)\n\t\t\tret = _TRUE;\n\t}\n\tif (_FALSE == ret) {\n\t\tRTW_INFO(\"%s: Write BB Reg Fail!!\", __FUNCTION__);\n\t\tgoto exit;\n\t}\n\n#if 0 /* No parameter with MP using currently by BB@Stanley. */\n/*#ifdef CONFIG_MP_INCLUDED*/\n\tif (Adapter->registrypriv.mp_mode == 1) {\n\t\t/*\n\t\t * 1.1 Read PHY_REG_MP.TXT BB INIT!!\n\t\t */\n\t\tret = _FALSE;\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\t\tres = phy_ConfigBBWithMpParaFile(Adapter, PHY_FILE_PHY_REG_MP);\n\t\tif (_SUCCESS == res)\n\t\t\tret = _TRUE;\n#endif\n\t\tif (_FALSE == ret) {\n\t\t\tstatus = odm_config_bb_with_header_file(&hal->odmpriv, CONFIG_BB_PHY_REG_MP);\n\t\t\tif (HAL_STATUS_SUCCESS == status)\n\t\t\t\tret = _TRUE;\n\t\t}\n\t\tif (_FALSE == ret) {\n\t\t\tRTW_INFO(\"%s: Write BB Reg MP Fail!!\", __FUNCTION__);\n\t\t\tgoto exit;\n\t\t}\n\t}\n#endif /* CONFIG_MP_INCLUDED */\n\n\t/*\n\t * 2. Read BB AGC table Initialization\n\t */\n\tret = _FALSE;\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\tres = phy_ConfigBBWithParaFile(Adapter, PHY_FILE_AGC_TAB, CONFIG_BB_AGC_TAB);\n\tif (_SUCCESS == res)\n\t\tret = _TRUE;\n#endif\n\tif (_FALSE == ret) {\n\t\tstatus = odm_config_bb_with_header_file(&hal->odmpriv, CONFIG_BB_AGC_TAB);\n\t\tif (HAL_STATUS_SUCCESS == status)\n\t\t\tret = _TRUE;\n\t}\n\tif (_FALSE == ret) {\n\t\tRTW_INFO(\"%s: Write AGC Table Fail!\\n\", __FUNCTION__);\n\t\tgoto exit;\n\t}\n\nexit:\n\treturn ret;\n}\n\nstatic u8 init_bb_reg(PADAPTER adapter)\n{\n\tu8 ret = _TRUE;\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\n\n\t/*\n\t * Config BB and AGC\n\t */\n\tret = _init_bb_reg(adapter);\n\n\tif (rtw_phydm_set_crystal_cap(adapter, hal->crystal_cap) == _FALSE) {\n\t\tRTW_ERR(\"Init crystal_cap failed\\n\");\n\t\trtw_warn_on(1);\n\t\tret = _FALSE;\n\t}\n\n\treturn ret;\n}\n\nstatic u8 _init_rf_reg(PADAPTER adapter)\n{\n\tu8 path;\n\tenum rf_path phydm_path;\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\tu8 *regfile;\n#endif\n\tenum hal_status status;\n\tint res;\n\tu8 ret = _TRUE;\n\n\n\t/*\n\t * Initialize IQK\n\t */\n\n\tstatus = halrf_config_rfk_with_header_file(&hal->odmpriv, CONFIG_BB_RF_CAL_INIT);\n\tif (HAL_STATUS_SUCCESS == status)\n\t\tret = _TRUE;\n\n\tif (_FALSE == ret) {\n\t\tRTW_INFO(\"%s: Init IQK Fail!\\n\", __FUNCTION__);\n\t\tgoto exit;\n\t}\n\n\t/*\n\t * Initialize RF\n\t */\n\tfor (path = 0; path < hal->NumTotalRFPath; path++) {\n\t\t/* Initialize RF from configuration file */\n\t\tswitch (path) {\n\t\tcase 0:\n\t\t\tphydm_path = RF_PATH_A;\n\t\t\t#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\t\t\tregfile = PHY_FILE_RADIO_A;\n\t\t\t#endif\n\t\t\tbreak;\n\n\t\tcase 1:\n\t\t\tphydm_path = RF_PATH_B;\n\t\t\t#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\t\t\tregfile = PHY_FILE_RADIO_B;\n\t\t\t#endif\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tRTW_INFO(\"%s: [WARN] Unknown path=%d, skip!\\n\", __FUNCTION__, path);\n\t\t\tcontinue;\n\t\t}\n\n\t\tret = _FALSE;\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\t\tres = PHY_ConfigRFWithParaFile(adapter, regfile, phydm_path);\n\t\tif (_SUCCESS == res)\n\t\t\tret = _TRUE;\n#endif\n\t\tif (_FALSE == ret) {\n\t\t\tstatus = odm_config_rf_with_header_file(&hal->odmpriv, CONFIG_RF_RADIO, phydm_path);\n\t\t\tif (HAL_STATUS_SUCCESS != status)\n\t\t\t\tgoto exit;\n\t\t\tret = _TRUE;\n\t\t}\n\t}\n\n\t/*\n\t * Configuration of Tx Power Tracking\n\t */\n\tret = _FALSE;\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\tres = PHY_ConfigRFWithTxPwrTrackParaFile(adapter, PHY_FILE_TXPWR_TRACK);\n\tif (_SUCCESS == res)\n\t\tret = _TRUE;\n#endif\n\tif (_FALSE == ret) {\n\t\tstatus = odm_config_rf_with_tx_pwr_track_header_file(&hal->odmpriv);\n\t\tif (HAL_STATUS_SUCCESS != status) {\n\t\t\tRTW_INFO(\"%s: Write PwrTrack Table Fail!\\n\", __FUNCTION__);\n\t\t\tgoto exit;\n\t\t}\n\t\tret = _TRUE;\n\t}\n\nexit:\n\treturn ret;\n}\n\nstatic u8 init_rf_reg(PADAPTER adapter)\n{\n\tu8 ret = _TRUE;\n\n\n\tret = _init_rf_reg(adapter);\n\n\treturn ret;\n}\n\n/*\n * Description:\n *\tInitialize PHY(BB/RF) related functions\n *\n * Return:\n *\t_TRUE\tSuccess\n *\t_FALSE\tFail\n */\nu8 rtl8822c_phy_init(PADAPTER adapter)\n{\n\tstruct dvobj_priv *d;\n\tstruct dm_struct *phydm;\n\tenum bb_path txpath = BB_PATH_A | BB_PATH_B;\n\tenum bb_path rxpath = BB_PATH_A | BB_PATH_B;\n\tint err;\n\tu8 ok = _TRUE;\n\tBOOLEAN ret;\n\n\n\td = adapter_to_dvobj(adapter);\n\tphydm = adapter_to_phydm(adapter);\n\n\tbb_rf_register_definition(adapter);\n\n\terr = rtw_halmac_phy_power_switch(d, _TRUE);\n\tif (err)\n\t\treturn _FALSE;\n\n#ifdef CONFIG_RTW_IOT_CCK_PD_INIT\n\tphydm_iot_patch_id_update(phydm, 0x021f0800, true);\n#endif\n\tret = config_phydm_parameter_init_8822c(phydm, ODM_PRE_SETTING);\n\tif (FALSE == ret)\n\t\treturn _FALSE;\n\n\tok = init_bb_reg(adapter);\n\tif (_FALSE == ok)\n\t\treturn _FALSE;\n\tok = init_rf_reg(adapter);\n\tif (_FALSE == ok)\n\t\treturn _FALSE;\n\n#ifdef CONFIG_RTW_IOT_CCK_PD_INIT\n\tphydm_iot_patch_id_update(phydm, 0x021f0800, true);\n#endif\n\tret = config_phydm_parameter_init_8822c(phydm, ODM_POST_SETTING);\n\tif (FALSE == ret)\n\t\treturn _FALSE;\n\n\trtw_hal_get_rf_path(d, NULL, &txpath, &rxpath);\n\tret = config_phydm_trx_mode_8822c(phydm, txpath, rxpath, BB_PATH_A);\n\tif (FALSE == ret)\n\t\treturn _FALSE;\n\n\treturn _TRUE;\n}\n\n#ifdef CONFIG_SUPPORT_HW_WPS_PBC\nstatic void dm_CheckPbcGPIO(PADAPTER adapter)\n{\n\tu8 tmp1byte;\n\tu8 bPbcPressed = _FALSE;\n\n\tif (!adapter->registrypriv.hw_wps_pbc)\n\t\treturn;\n\n#ifdef CONFIG_USB_HCI\n\ttmp1byte = rtw_read8(adapter, GPIO_IO_SEL);\n\ttmp1byte |= (HAL_8192C_HW_GPIO_WPS_BIT);\n\trtw_write8(adapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as output mode */\n\n\ttmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);\n\trtw_write8(adapter, GPIO_IN, tmp1byte); /* reset the floating voltage level */\n\n\ttmp1byte = rtw_read8(adapter, GPIO_IO_SEL);\n\ttmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);\n\trtw_write8(adapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as input mode */\n\n\ttmp1byte = rtw_read8(adapter, GPIO_IN);\n\tif (tmp1byte == 0xff)\n\t\treturn;\n\n\tif (tmp1byte & HAL_8192C_HW_GPIO_WPS_BIT)\n\t\tbPbcPressed = _TRUE;\n#else\n\ttmp1byte = rtw_read8(adapter, GPIO_IN);\n\n\tif ((tmp1byte == 0xff) || adapter->init_adpt_in_progress)\n\t\treturn;\n\n\tif ((tmp1byte & HAL_8192C_HW_GPIO_WPS_BIT) == 0)\n\t\tbPbcPressed = _TRUE;\n#endif\n\n\tif (_TRUE == bPbcPressed) {\n\t\t/*\n\t\t * Here we only set bPbcPressed to true\n\t\t * After trigger PBC, the variable will be set to false\n\t\t */\n\t\tRTW_INFO(\"CheckPbcGPIO - PBC is pressed\\n\");\n\t\trtw_request_wps_pbc_event(adapter);\n\t}\n}\n#endif /* CONFIG_SUPPORT_HW_WPS_PBC */\n\n\n#ifdef CONFIG_PCI_HCI\n/*\n * Description:\n *\tPerform interrupt migration dynamically to reduce CPU utilization.\n *\n * Assumption:\n *\t1. Do not enable migration under WIFI test.\n */\nvoid dm_InterruptMigration(PADAPTER adapter)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tstruct mlme_priv *pmlmepriv = &adapter->mlmepriv;\n\tBOOLEAN bCurrentIntMt, bCurrentACIntDisable;\n\tBOOLEAN IntMtToSet = _FALSE;\n\tBOOLEAN ACIntToSet = _FALSE;\n\n\n\t/* Retrieve current interrupt migration and Tx four ACs IMR settings first. */\n\tbCurrentIntMt = hal->bInterruptMigration;\n\tbCurrentACIntDisable = hal->bDisableTxInt;\n\n\t/*\n\t * <Roger_Notes> Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics\n\t * when interrupt migration is set before. 2010.03.05.\n\t */\n\tif (!adapter->registrypriv.wifi_spec\n\t    && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t    && pmlmepriv->LinkDetectInfo.bHigherBusyTraffic) {\n\t\tIntMtToSet = _TRUE;\n\n\t\t/* To check whether we should disable Tx interrupt or not. */\n\t\tif (pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic)\n\t\t\tACIntToSet = _TRUE;\n\t}\n\n\t/* Update current settings. */\n\tif (bCurrentIntMt != IntMtToSet) {\n\t\tRTW_INFO(\"%s: Update interrupt migration(%d)\\n\", __FUNCTION__, IntMtToSet);\n\t\tif (IntMtToSet) {\n\t\t\t/*\n\t\t\t * <Roger_Notes> Set interrupt migration timer and corresponging Tx/Rx counter.\n\t\t\t * timer 25ns*0xfa0=100us for 0xf packets.\n\t\t\t * 2010.03.05.\n\t\t\t */\n\t\t\trtw_write32(adapter, REG_INT_MIG, 0xff000fa0); /* 0x306:Rx, 0x307:Tx */\n\t\t\thal->bInterruptMigration = IntMtToSet;\n\t\t} else {\n\t\t\t/* Reset all interrupt migration settings. */\n\t\t\trtw_write32(adapter, REG_INT_MIG, 0);\n\t\t\thal->bInterruptMigration = IntMtToSet;\n\t\t}\n\t}\n}\n#endif /* CONFIG_PCI_HCI */\n\n/*\n * ============================================================\n * functions\n * ============================================================\n */\nstatic void init_phydm_cominfo(PADAPTER adapter)\n{\n\tPHAL_DATA_TYPE hal;\n\tstruct dm_struct *p_dm_odm;\n\tu32 support_ability = 0;\n\tu8 cut_ver = ODM_CUT_A, fab_ver = ODM_TSMC;\n\n\n\thal = GET_HAL_DATA(adapter);\n\tp_dm_odm = &hal->odmpriv;\n\n\tInit_ODM_ComInfo(adapter);\n\n\todm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, hal->PackageType);\n\todm_cmn_info_init(p_dm_odm, ODM_CMNINFO_IC_TYPE, ODM_RTL8822C);\n\n\tif (IS_CHIP_VENDOR_TSMC(hal->version_id))\n\t\tfab_ver = ODM_TSMC;\n\telse if (IS_CHIP_VENDOR_UMC(hal->version_id))\n\t\tfab_ver = ODM_UMC;\n\telse if (IS_CHIP_VENDOR_SMIC(hal->version_id))\n\t\tfab_ver = ODM_UMC + 1;\n\telse\n\t\tRTW_INFO(\"%s: unknown fab_ver=%d !!\\n\",\n\t\t\t __FUNCTION__, GET_CVID_MANUFACTUER(hal->version_id));\n\n\tif (IS_A_CUT(hal->version_id))\n\t\tcut_ver = ODM_CUT_A;\n\telse if (IS_B_CUT(hal->version_id))\n\t\tcut_ver = ODM_CUT_B;\n\telse if (IS_C_CUT(hal->version_id))\n\t\tcut_ver = ODM_CUT_C;\n\telse if (IS_D_CUT(hal->version_id))\n\t\tcut_ver = ODM_CUT_D;\n\telse if (IS_E_CUT(hal->version_id))\n\t\tcut_ver = ODM_CUT_E;\n\telse if (IS_F_CUT(hal->version_id))\n\t\tcut_ver = ODM_CUT_F;\n\telse if (IS_I_CUT(hal->version_id))\n\t\tcut_ver = ODM_CUT_I;\n\telse if (IS_J_CUT(hal->version_id))\n\t\tcut_ver = ODM_CUT_J;\n\telse if (IS_K_CUT(hal->version_id))\n\t\tcut_ver = ODM_CUT_K;\n\telse\n\t\tRTW_INFO(\"%s: unknown cut_ver=%d !!\\n\",\n\t\t\t __FUNCTION__, GET_CVID_CUT_VERSION(hal->version_id));\n\n\tRTW_INFO(\"%s: fab_ver=%d cut_ver=%d\\n\", __FUNCTION__, fab_ver, cut_ver);\n\todm_cmn_info_init(p_dm_odm, ODM_CMNINFO_FAB_VER, fab_ver);\n\todm_cmn_info_init(p_dm_odm, ODM_CMNINFO_CUT_VER, cut_ver);\n\todm_cmn_info_init(p_dm_odm, ODM_CMNINFO_DIS_DPD, _TRUE);\n}\n\nvoid rtl8822c_phy_init_dm_priv(PADAPTER adapter)\n{\n\tstruct dm_struct *podmpriv = adapter_to_phydm(adapter);\n\n\tinit_phydm_cominfo(adapter);\n\todm_init_all_timers(podmpriv);\n}\n\nvoid rtl8822c_phy_deinit_dm_priv(PADAPTER adapter)\n{\n\tstruct dm_struct *podmpriv = adapter_to_phydm(adapter);\n\n\todm_cancel_all_timers(podmpriv);\n}\n\nvoid rtl8822c_phy_init_haldm(PADAPTER adapter)\n{\n\trtw_phydm_init(adapter);\n}\n\nstatic void check_rxfifo_full(PADAPTER adapter)\n{\n\tstruct dvobj_priv *psdpriv = adapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &psdpriv->drv_dbg;\n\tstruct registry_priv *regsty = &adapter->registrypriv;\n\tu8 val8 = 0;\n\n\tif (regsty->check_hw_status == 1) {\n\t\t/* switch counter to RX fifo */\n\t\tval8 = rtw_read8(adapter, REG_RXERR_RPT_8822C + 3);\n\t\trtw_write8(adapter, REG_RXERR_RPT_8822C + 3, (val8 | 0xa0));\n\n\t\tpdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow;\n\t\tpdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT_8822C);\n\t\tpdbgpriv->dbg_rx_fifo_diff_overflow =\n\t\t\tpdbgpriv->dbg_rx_fifo_curr_overflow - pdbgpriv->dbg_rx_fifo_last_overflow;\n\t}\n}\n\nvoid rtl8822c_phy_haldm_watchdog(PADAPTER adapter)\n{\n\tBOOLEAN bFwCurrentInPSMode = _FALSE;\n\tu8 bFwPSAwake = _TRUE;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);\n\tu8 lps_changed = _FALSE;\n\tu8 in_lps = _FALSE;\n\tPADAPTER current_lps_iface = NULL, iface = NULL;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tu8 i = 0;\n\n\n\tif (!rtw_is_hw_init_completed(adapter))\n\t\tgoto skip_dm;\n\n#ifdef CONFIG_LPS\n\tbFwCurrentInPSMode = adapter_to_pwrctl(adapter)->bFwCurrentInPSMode;\n\trtw_hal_get_hwreg(adapter, HW_VAR_FWLPS_RF_ON, &bFwPSAwake);\n#endif /* CONFIG_LPS */\n\n#ifdef CONFIG_P2P_PS\n\t/*\n\t * Fw is under p2p powersaving mode, driver should stop dynamic mechanism.\n\t */\n\tif (adapter->wdinfo.p2p_ps_mode)\n\t\tbFwPSAwake = _FALSE;\n#endif /* CONFIG_P2P_PS */\n\n\tif ((rtw_is_hw_init_completed(adapter))\n\t    && ((!bFwCurrentInPSMode) && bFwPSAwake)) {\n\n\t\t/* check rx fifo */\n\t\tcheck_rxfifo_full(adapter);\n\t}\n\n#ifdef CONFIG_LPS\n\tif (pwrpriv->bLeisurePs && bFwCurrentInPSMode && pwrpriv->pwr_mode != PS_MODE_ACTIVE\n#ifdef CONFIG_WMMPS_STA\t\n\t\t&& !rtw_is_wmmps_mode(adapter)\n#endif /* CONFIG_WMMPS_STA */\n\t) {\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tif (pwrpriv->current_lps_hw_port_id == rtw_hal_get_port(iface))\n\t\t\t\tcurrent_lps_iface = iface;\n\t\t}\n\n\t\tlps_changed = _TRUE;\n\t\tin_lps = _TRUE;\n\t\tLPS_Leave(current_lps_iface, \"LPS_CTRL_PHYDM\");\n\t}\n#endif\n\n#ifdef CONFIG_BEAMFORMING\n#ifdef RTW_BEAMFORMING_VERSION_2\n\tif (check_fwstate(&adapter->mlmepriv, WIFI_STATION_STATE) &&\n\t\t\tcheck_fwstate(&adapter->mlmepriv, _FW_LINKED))\n\t\trtw_hal_beamforming_config_csirate(adapter);\n#endif\n#endif\n\n#ifdef CONFIG_DISABLE_ODM\n\tgoto skip_dm;\n#endif\n\n\trtw_phydm_watchdog(adapter, in_lps);\n\nskip_dm:\n\n#ifdef CONFIG_LPS\n\tif (lps_changed)\n\t\tLPS_Enter(current_lps_iface, \"LPS_CTRL_PHYDM\");\n#endif\n\t/*\n\t * Check GPIO to determine current RF on/off and Pbc status.\n\t * Check Hardware Radio ON/OFF or not\n\t */\n#ifdef CONFIG_SUPPORT_HW_WPS_PBC\n\tdm_CheckPbcGPIO(adapter);\n#else /* !CONFIG_SUPPORT_HW_WPS_PBC */\n\treturn;\n#endif /* !CONFIG_SUPPORT_HW_WPS_PBC */\n}\n\nstatic u32 phy_calculatebitshift(u32 mask)\n{\n\tu32 i;\n\n\n\tfor (i = 0; i <= 31; i++)\n\t\tif (mask & BIT(i))\n\t\t\tbreak;\n\n\treturn i;\n}\n\nu32 rtl8822c_read_bb_reg(PADAPTER adapter, u32 addr, u32 mask)\n{\n\tu32 val = 0, val_org, shift;\n\n\n#if (DISABLE_BB_RF == 1)\n\treturn 0;\n#endif\n\n\tval_org = rtw_read32(adapter, addr);\n\tshift = phy_calculatebitshift(mask);\n\tval = (val_org & mask) >> shift;\n\n\treturn val;\n}\n\nvoid rtl8822c_write_bb_reg(PADAPTER adapter, u32 addr, u32 mask, u32 val)\n{\n\tu32 val_org, shift;\n\n\n#if (DISABLE_BB_RF == 1)\n\treturn;\n#endif\n\n\tif (mask != 0xFFFFFFFF) {\n\t\t/* not \"double word\" write */\n\t\tval_org = rtw_read32(adapter, addr);\n\t\tshift = phy_calculatebitshift(mask);\n\t\tval = ((val_org & (~mask)) | ((val << shift) & mask));\n\t}\n\n\trtw_write32(adapter, addr, val);\n}\n\nu32 rtl8822c_read_rf_reg(PADAPTER adapter, enum rf_path path, u32 addr, u32 mask)\n{\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n\tu32 val;\n\n\tval = config_phydm_read_rf_reg_8822c(phydm, path, addr, mask);\n\tif (!config_phydm_read_rf_check_8822c(val))\n\t\tRTW_INFO(FUNC_ADPT_FMT \": read RF reg path=%d addr=0x%x mask=0x%x FAIL!\\n\",\n\t\t\t FUNC_ADPT_ARG(adapter), path, addr, mask);\n\n\treturn val;\n}\n\nvoid rtl8822c_write_rf_reg(PADAPTER adapter, enum rf_path path, u32 addr, u32 mask, u32 val)\n{\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n\tu8 ret;\n\n\tret = config_phydm_write_rf_reg_8822c(phydm, path, addr, mask, val);\n\tif (_FALSE == ret)\n\t\tRTW_INFO(FUNC_ADPT_FMT \": write RF reg path=%d addr=0x%x mask=0x%x val=0x%x FAIL!\\n\",\n\t\t\t FUNC_ADPT_ARG(adapter), path, addr, mask, val);\n}\n\nstatic void set_tx_power_level_by_path(PADAPTER adapter, u8 channel, u8 path)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tu8 under_survey_ch = phy_check_under_survey_ch(adapter);\n\tu8 under_24g = (hal->current_band_type == BAND_ON_2_4G);\n\n\tif (under_24g)\n\tphy_set_tx_power_index_by_rate_section(adapter, path, channel, CCK);\n\n\tphy_set_tx_power_index_by_rate_section(adapter, path, channel, OFDM);\n\n\tif (!under_survey_ch) {\n\tphy_set_tx_power_index_by_rate_section(adapter, path, channel, HT_MCS0_MCS7);\n\tphy_set_tx_power_index_by_rate_section(adapter, path, channel, HT_MCS8_MCS15);\n\tphy_set_tx_power_index_by_rate_section(adapter, path, channel, VHT_1SSMCS0_1SSMCS9);\n\tphy_set_tx_power_index_by_rate_section(adapter, path, channel, VHT_2SSMCS0_2SSMCS9);\n}\n}\n\nvoid rtl8822c_set_tx_power_level(PADAPTER adapter, u8 channel)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tstruct dm_struct *phydm;\n\t#ifdef CONFIG_ANTENNA_DIVERSITY\n\tstruct phydm_fat_struct *p_dm_fat_table;\n\t#endif\n\tu8 path = RF_PATH_A;\n\n\n\thal = GET_HAL_DATA(adapter);\n\tphydm = &hal->odmpriv;\n\n\t#ifdef CONFIG_ANTENNA_DIVERSITY\n\tp_dm_fat_table = &phydm->dm_fat_table;\n\n\tif (hal->AntDivCfg) {\n\t\t/* antenna diversity Enable */\n\t\tpath = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? RF_PATH_A : RF_PATH_B;\n\t\tset_tx_power_level_by_path(adapter, channel, path);\n\t} else\n\t#endif\n\t{\n\t\t/* antenna diversity disable */\n\t\tfor (path = RF_PATH_A; path < hal->NumTotalRFPath; ++path)\n\t\t\tset_tx_power_level_by_path(adapter, channel, path);\n\t}\n}\n\nvoid rtl8822c_set_txpwr_done(_adapter *adapter)\n{\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n\n\tconfig_phydm_set_txagc_to_hw_8822c(phydm);\n}\n\n#ifndef DBG_TX_POWER_IDX\n#define DBG_TX_POWER_IDX 0\n#endif\n\nstatic u8 rtl8822c_get_dis_dpd_by_rate_diff(PADAPTER adapter, u8 rate)\n{\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n\tu16 dis_dpd_rate;\n\tu8 dis_dpd_rate_diff = 0;\n\n\tdis_dpd_rate = phydm_get_dis_dpd_by_rate_8822c(phydm);\n\tswitch (rate) {\n\t\tcase MGN_6M:\n\t\t\t\t((dis_dpd_rate & BIT(0)) == BIT(0))?(dis_dpd_rate_diff = 3):(dis_dpd_rate_diff = 0);\n\t\t\tbreak;\n\t\tcase MGN_9M:\n\t\t\t\t((dis_dpd_rate & BIT(1)) == BIT(1))?(dis_dpd_rate_diff = 3):(dis_dpd_rate_diff = 0);\n\t\t\tbreak;\n\t\tcase MGN_MCS0:\n\t\t\t\t((dis_dpd_rate & BIT(2)) == BIT(2))?(dis_dpd_rate_diff = 3):(dis_dpd_rate_diff = 0);\t\t\t\n\t\t\tbreak;\n\t\tcase MGN_MCS1:\n\t\t\t\t((dis_dpd_rate & BIT(3)) == BIT(3))?(dis_dpd_rate_diff = 3):(dis_dpd_rate_diff = 0);\t\t\t\n\t\t\tbreak;\n\t\tcase MGN_MCS8:\n\t\t\t\t((dis_dpd_rate & BIT(4)) == BIT(4))?(dis_dpd_rate_diff = 3):(dis_dpd_rate_diff = 0);\t\t\t\t\n\t\t\tbreak;\n\t\tcase MGN_MCS9:\n\t\t\t\t((dis_dpd_rate & BIT(5)) == BIT(5))?(dis_dpd_rate_diff = 3):(dis_dpd_rate_diff = 0);\t\t\t\n\t\t\tbreak;\n\t\tcase MGN_VHT1SS_MCS0:\n\t\t\t\t((dis_dpd_rate & BIT(6)) == BIT(6))?(dis_dpd_rate_diff = 3):(dis_dpd_rate_diff = 0);\t\t\t\t\n\t\t\tbreak;\n\t\tcase MGN_VHT1SS_MCS1:\n\t\t\t\t((dis_dpd_rate & BIT(7)) == BIT(7))?(dis_dpd_rate_diff = 3):(dis_dpd_rate_diff = 0);\t\t\t\t\n\t\t\tbreak;\n\t\tcase MGN_VHT2SS_MCS0:\n\t\t\t\t((dis_dpd_rate & BIT(8)) == BIT(8))?(dis_dpd_rate_diff = 3):(dis_dpd_rate_diff = 0);\t\t\t\n\t\t\tbreak;\n\t\tcase MGN_VHT2SS_MCS1:\n\t\t\t\t((dis_dpd_rate & BIT(9)) == BIT(9))?(dis_dpd_rate_diff = 3):(dis_dpd_rate_diff = 0);\t\t\t\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tdis_dpd_rate_diff = 0;\n\t\t\tbreak;\n\t}\n\n\treturn dis_dpd_rate_diff;\n}\n\n/*\n * Parameters:\n *\tpadatper\n *\tpowerindex\tpower index for rate\n *\trfpath\t\tAntenna(RF) path, type \"enum rf_path\"\n *\trate\t\tdata rate, type \"enum MGN_RATE\"\n */\nvoid rtl8822c_set_tx_power_index(PADAPTER adapter, u32 powerindex, enum rf_path rfpath, u8 rate)\n{\n\tHAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);\n\tstruct dm_struct *phydm = adapter_to_phydm(adapter);\n\tu8 shift = 0;\n\tboolean write_ret;\n\n\tif (!IS_1T_RATE(rate) && !IS_2T_RATE(rate)) {\n\t\tRTW_ERR(FUNC_ADPT_FMT\" invalid rate(%s)\\n\", FUNC_ADPT_ARG(adapter), MGN_RATE_STR(rate));\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\trate = MRateToHwRate(rate);\n\n\t/*\n\t* For 8822C, phydm api use 4 bytes txagc value\n\t* driver must combine every four 1 byte to one 4 byte and send to phydm api\n\t*/\n\tshift = rate % 4;\n\thal->txagc_set_buf |= ((powerindex & 0xff) << (shift * 8));\n\n\tif (shift != 3)\n\t\tgoto exit;\n\n\trate = rate & 0xFC;\n\twrite_ret = config_phydm_write_txagc_8822c(phydm, hal->txagc_set_buf, rfpath, rate);\n\n\tif (write_ret == true && !DBG_TX_POWER_IDX)\n\t\tgoto clear_buf;\n\n\tRTW_INFO(FUNC_ADPT_FMT\" (index:0x%08x, %c, rate:%s(0x%02x), disable api:%d) %s\\n\"\n\t\t, FUNC_ADPT_ARG(adapter), hal->txagc_set_buf, rf_path_char(rfpath)\n\t\t, HDATA_RATE(rate), rate, phydm->is_disable_phy_api\n\t\t, write_ret == true ? \"OK\" : \"FAIL\");\n\n\trtw_warn_on(write_ret != true);\n\nclear_buf:\n\thal->txagc_set_buf = 0;\n\nexit:\n\treturn;\n}\n\n/*\n * Parameters:\n *\tpadatper\n *\trfpath\t\tAntenna(RF) path, type \"enum rf_path\"\n *\trate\t\tdata rate, type \"enum MGN_RATE\"\n *\tbandwidth\tBandwidth, type \"enum _CHANNEL_WIDTH\"\n *\tchannel\t\tChannel number\n *\n * Rteurn:\n *\ttx_power\tpower index for rate\n */\nu8 rtl8822c_get_tx_power_index(PADAPTER adapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\ts16 power_idx;\n\tu8 pg = 0;\n\ts8 by_rate_diff = 0, limit = 0, tpt_offset = 0, btc_diff = 0, dis_dpd_rate_diff = 0;\n\tu8 ntx_idx = phy_get_current_tx_num(adapter, rate);\n\tu8 bIn24G = _FALSE;\n\n\tpg = phy_get_pg_txpwr_idx(adapter, rfpath, rate, ntx_idx, bandwidth, channel, &bIn24G);\n\n\tby_rate_diff = PHY_GetTxPowerByRate(adapter, (u8)(!bIn24G), rfpath, rate);\n\tlimit = PHY_GetTxPowerLimit(adapter, NULL, (BAND_TYPE)(!bIn24G),\n\t\t\thal->current_channel_bw, rfpath, rate, ntx_idx, hal->current_channel);\n\n\t/* tpt_offset += PHY_GetTxPowerTrackingOffset(adapter, rfpath, rate); */\n\n#ifdef CONFIG_BT_COEXIST\n\tif (hal->EEPROMBluetoothCoexist == _TRUE)\n\t\tbtc_diff = -(rtw_btcoex_query_reduced_wl_pwr_lvl(adapter) * hal_spec->txgi_pdbm);\n#endif\n\n\tdis_dpd_rate_diff = -(rtl8822c_get_dis_dpd_by_rate_diff(adapter, rate) * hal_spec->txgi_pdbm);\n\n\tif (tic)\n\t\ttxpwr_idx_comp_set(tic, ntx_idx, pg, by_rate_diff, limit, tpt_offset, 0, btc_diff, dis_dpd_rate_diff);\n\n\tby_rate_diff = by_rate_diff > limit ? limit : by_rate_diff;\n\tpower_idx = pg + by_rate_diff + tpt_offset + btc_diff + dis_dpd_rate_diff;\n\n#if 0\n#if CCX_SUPPORT\n\tCCX_CellPowerLimit(adapter, channel, rate, (u8 *)&power_idx);\n#endif\n#endif\n\n\tif (power_idx < 0)\n\t\tpower_idx = 0;\n\telse if (power_idx > hal_spec->txgi_max)\n\t\tpower_idx = hal_spec->txgi_max;\n\n\treturn power_idx;\n}\n\n/*\n * Description:\n *\tCheck need to switch band or not\n * Parameters:\n *\tchannelToSW\tchannel wiii be switch to\n * Return:\n *\t_TRUE\t\tneed to switch band\n *\t_FALSE\t\tnot need to switch band\n */\nstatic u8 need_switch_band(PADAPTER adapter, u8 channelToSW)\n{\n\tu8 u1tmp = 0;\n\tu8 ret_value = _TRUE;\n\tu8 Band = BAND_ON_5G, BandToSW = BAND_ON_5G;\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\n\tBand = hal->current_band_type;\n\n\t/* Use current swich channel to judge Band Type and switch Band if need */\n\tif (channelToSW > 14)\n\t\tBandToSW = BAND_ON_5G;\n\telse\n\t\tBandToSW = BAND_ON_2_4G;\n\n\tif (BandToSW != Band) {\n\t\t/* record current band type for other hal use */\n\t\thal->current_band_type = (BAND_TYPE)BandToSW;\n\t\tret_value = _TRUE;\n\t} else\n\t\tret_value = _FALSE;\n\n\treturn ret_value;\n}\n\nstatic u8 get_pri_ch_id(PADAPTER adapter)\n{\n\tu8 pri_ch_idx = 0;\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\n\tif (hal->current_channel_bw == CHANNEL_WIDTH_80) {\n\t\t/* primary channel is at lower subband of 80MHz & 40MHz */\n\t\tif ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))\n\t\t\tpri_ch_idx = VHT_DATA_SC_20_LOWEST_OF_80MHZ;\n\t\t/* primary channel is at lower subband of 80MHz & upper subband of 40MHz */\n\t\telse if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))\n\t\t\tpri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;\n\t\t/* primary channel is at upper subband of 80MHz & lower subband of 40MHz */\n\t\telse if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))\n\t\t\tpri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;\n\t\t/* primary channel is at upper subband of 80MHz & upper subband of 40MHz */\n\t\telse if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))\n\t\t\tpri_ch_idx = VHT_DATA_SC_20_UPPERST_OF_80MHZ;\n\t\telse {\n\t\t\tif (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)\n\t\t\t\tpri_ch_idx = VHT_DATA_SC_40_LOWER_OF_80MHZ;\n\t\t\telse if (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)\n\t\t\t\tpri_ch_idx = VHT_DATA_SC_40_UPPER_OF_80MHZ;\n\t\t\telse\n\t\t\t\tRTW_INFO(\"SCMapping: DONOT CARE Mode Setting\\n\");\n\t\t}\n\t} else if (hal->current_channel_bw == CHANNEL_WIDTH_40) {\n\t\t/* primary channel is at upper subband of 40MHz */\n\t\tif (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)\n\t\t\tpri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;\n\t\t/* primary channel is at lower subband of 40MHz */\n\t\telse if (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)\n\t\t\tpri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;\n\t\telse\n\t\t\tRTW_INFO(\"SCMapping: DONOT CARE Mode Setting\\n\");\n\t}\n\n\treturn  pri_ch_idx;\n}\n\nstatic void mac_switch_bandwidth(PADAPTER adapter, u8 pri_ch_idx)\n{\n\tu8 channel = 0, bw = 0;\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tint err;\n\n\tchannel = hal->current_channel;\n\tbw = hal->current_channel_bw;\n\terr = rtw_halmac_set_bandwidth(adapter_to_dvobj(adapter), channel, pri_ch_idx, bw);\n\tif (err) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": (channel=%d, pri_ch_idx=%d, bw=%d) fail\\n\",\n\t\t\t FUNC_ADPT_ARG(adapter), channel, pri_ch_idx, bw);\n\t}\n}\n\nstatic void switch_chnl_and_set_bw_by_drv(PADAPTER adapter, u8 switch_band)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tstruct dm_struct *p_dm_odm = &hal->odmpriv;\n\tu8 center_ch = 0, ret = 0;\n\n\t/* set channel & Bandwidth register */\n\t/* 1. set switch band register if need to switch band */\n\tif (switch_band) {\n\t\t/* hal->current_channel is center channel of pmlmeext->cur_channel(primary channel) */\n\t\tret = config_phydm_switch_band_8822c(p_dm_odm, hal->current_channel);\n\n\t\tif (!ret) {\n\t\t\tRTW_INFO(\"%s: config_phydm_switch_band_8822c fail\\n\", __FUNCTION__);\n\t\t\trtw_warn_on(1);\n\t\t\treturn;\n\t\t}\n\t}\n\n\t/* 2. set channel register */\n\tif (hal->bSwChnl) {\n\t\tret = config_phydm_switch_channel_8822c(p_dm_odm, hal->current_channel);\n\t\thal->bSwChnl = _FALSE;\n\n\t\tif (!ret) {\n\t\t\tRTW_INFO(\"%s: config_phydm_switch_channel_8822c fail\\n\", __FUNCTION__);\n\t\t\trtw_warn_on(1);\n\t\t\treturn;\n\t\t}\n\t}\n\n\t/* 3. set Bandwidth register */\n\tif (hal->bSetChnlBW) {\n\t\t/* get primary channel index */\n\t\tu8 pri_ch_idx = get_pri_ch_id(adapter);\n\n\t\t/* 3.1 set MAC register */\n\t\tmac_switch_bandwidth(adapter, pri_ch_idx);\n\n\t\t/* 3.2 set BB/RF registet */\n\t\tret = config_phydm_switch_bandwidth_8822c(p_dm_odm, pri_ch_idx, hal->current_channel_bw);\n\t\thal->bSetChnlBW = _FALSE;\n\n\t\tif (!ret) {\n\t\t\tRTW_INFO(\"%s: config_phydm_switch_bandwidth_8822c fail\\n\", __FUNCTION__);\n\t\t\trtw_warn_on(1);\n\t\t\treturn;\n\t\t}\n\t}\n}\n\n#ifdef RTW_CHANNEL_SWITCH_OFFLOAD\nstatic void switch_chnl_and_set_bw_by_fw(PADAPTER adapter, u8 switch_band)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\n\tif (switch_band ||hal->bSwChnl || hal->bSetChnlBW) {\n\t\trtw_hal_switch_chnl_and_set_bw_offload(adapter,\n\t\t\thal->current_channel, get_pri_ch_id(adapter), hal->current_channel_bw);\n\n\t\thal->bSwChnl = _FALSE;\n\t\thal->bSetChnlBW = _FALSE;\n\t}\n}\n#endif\n\n/*\n * Description:\n *\tSet channel & bandwidth & offset\n */\nvoid rtl8822c_switch_chnl_and_set_bw(PADAPTER adapter)\n{\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);\n\tstruct dm_struct *p_dm_odm = &hal->odmpriv;\n\tu8 center_ch = 0, ret = 0, switch_band = _FALSE;\n\n\tif (adapter->bNotifyChannelChange) {\n\t\tRTW_INFO(\"[%s] bSwChnl=%d, ch=%d, bSetChnlBW=%d, bw=%d\\n\",\n\t\t\t __FUNCTION__,\n\t\t\t hal->bSwChnl,\n\t\t\t hal->current_channel,\n\t\t\t hal->bSetChnlBW,\n\t\t\t hal->current_channel_bw);\n\t}\n\n\tif (RTW_CANNOT_RUN(adapter)) {\n\t\thal->bSwChnlAndSetBWInProgress = _FALSE;\n\t\treturn;\n\t}\n\n\tswitch_band = need_switch_band(adapter, hal->current_channel);\n\n\t/* config channel, bw, offset setting */\n#ifdef RTW_CHANNEL_SWITCH_OFFLOAD\n\tif (hal->ch_switch_offload) {\n\n\t#ifdef RTW_REDUCE_SCAN_SWITCH_CH_TIME\n\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\t\t_adapter *iface;\n\t\tstruct mlme_ext_priv *mlmeext;\n\t\tu8 drv_switch = _TRUE;\n\t\tint i;\n\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tmlmeext = &iface->mlmeextpriv;\n\n\t\t\t/* check scan state */\n\t\t\tif (mlmeext_scan_state(mlmeext) != SCAN_DISABLE\n\t\t\t\t&& mlmeext_scan_state(mlmeext) != SCAN_COMPLETE\n\t\t\t\t\t&& mlmeext_scan_state(mlmeext) != SCAN_BACKING_OP)\n\t\t\t\tdrv_switch = _FALSE;\n\t\t}\n\t#else\n\t\tu8 drv_switch = _FALSE;\n\t#endif\n\n\t\tif (drv_switch == _TRUE)\n\t\t\tswitch_chnl_and_set_bw_by_drv(adapter, switch_band);\n\t\telse\n\t\tswitch_chnl_and_set_bw_by_fw(adapter, switch_band);\n\n\t} else {\n\t\tswitch_chnl_and_set_bw_by_drv(adapter, switch_band);\n\t}\n#else\n\tswitch_chnl_and_set_bw_by_drv(adapter, switch_band);\n#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */\n\n\n\t/* config coex setting */\n\tif (switch_band) {\n#ifdef CONFIG_BT_COEXIST\n\t\tif (hal->EEPROMBluetoothCoexist) {\n\t\t\tstruct mlme_ext_priv *mlmeext;\n\n\t\t\t/* switch band under site survey or not, must notify to BT COEX */\n\t\t\tmlmeext = &adapter->mlmeextpriv;\n\t\t\tif (mlmeext_scan_state(mlmeext) != SCAN_DISABLE)\n\t\t\t\trtw_btcoex_switchband_notify(_TRUE, hal->current_band_type);\n\t\t\telse\n\t\t\t\trtw_btcoex_switchband_notify(_FALSE, hal->current_band_type);\n\t\t} else\n\t\t\trtw_btcoex_wifionly_switchband_notify(adapter);\n#else /* !CONFIG_BT_COEXIST */\n\t\trtw_btcoex_wifionly_switchband_notify(adapter);\n#endif /* CONFIG_BT_COEXIST */\n\t}\n\n\tphydm_config_kfree(p_dm_odm, hal->current_channel);\n\n\t/* TX Power Setting */\n\todm_clear_txpowertracking_state(p_dm_odm);\n\trtw_hal_set_tx_power_level(adapter, hal->current_channel);\n\n\t/* IQK */\n\tif ((hal->bNeedIQK == _TRUE)\n\t    || (adapter->registrypriv.mp_mode == 1)) {\n\t\t/*phy_iq_calibrate_8822c(p_dm_odm, _FALSE);*/\n\t\trtw_phydm_iqk_trigger(adapter);\n\t\thal->bNeedIQK = _FALSE;\n\t}\n}\n\n/*\n * Description:\n *\tStore channel setting to hal date\n * Parameters:\n *\tbSwitchChannel\t\tswith channel or not\n *\tbSetBandWidth\t\tset band or not\n *\tChannelNum\t\tcenter channel\n *\tChnlWidth\t\tbandwidth\n *\tChnlOffsetOf40MHz\tchannel offset for 40MHz Bandwidth\n *\tChnlOffsetOf80MHz\tchannel offset for 80MHz Bandwidth\n *\tCenterFrequencyIndex1\tcenter channel index\n */\n\nvoid rtl8822c_handle_sw_chnl_and_set_bw(\n\tPADAPTER Adapter, u8 bSwitchChannel, u8 bSetBandWidth,\n\tu8 ChannelNum, enum channel_width ChnlWidth, u8 ChnlOffsetOf40MHz,\n\tu8 ChnlOffsetOf80MHz, u8 CenterFrequencyIndex1)\n{\n\tPADAPTER pDefAdapter = GetDefaultAdapter(Adapter);\n\tPHAL_DATA_TYPE hal = GET_HAL_DATA(pDefAdapter);\n\tu8 tmpChannel = hal->current_channel;\n\tenum channel_width tmpBW = hal->current_channel_bw;\n\tu8 tmpnCur40MhzPrimeSC = hal->nCur40MhzPrimeSC;\n\tu8 tmpnCur80MhzPrimeSC = hal->nCur80MhzPrimeSC;\n\tu8 tmpCenterFrequencyIndex1 = hal->CurrentCenterFrequencyIndex1;\n\tstruct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;\n\n\n\t/* check swchnl or setbw */\n\tif (!bSwitchChannel && !bSetBandWidth) {\n\t\tRTW_INFO(\"%s: not switch channel and not set bandwidth\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n\t/* skip switch channel operation for current channel & ChannelNum(will be switch) are the same */\n\tif (bSwitchChannel) {\n\t\tif (hal->current_channel != ChannelNum) {\n\t\t\tif (HAL_IsLegalChannel(Adapter, ChannelNum))\n\t\t\t\thal->bSwChnl = _TRUE;\n\t\t\telse\n\t\t\t\treturn;\n\t\t}\n\t}\n\n\t/* check set BandWidth */\n\tif (bSetBandWidth) {\n\t\t/* initial channel bw setting */\n\t\tif (hal->bChnlBWInitialized == _FALSE) {\n\t\t\thal->bChnlBWInitialized = _TRUE;\n\t\t\thal->bSetChnlBW = _TRUE;\n\t\t} else if ((hal->current_channel_bw != ChnlWidth) || /* check whether need set band or not */\n\t\t\t   (hal->nCur40MhzPrimeSC != ChnlOffsetOf40MHz) ||\n\t\t\t   (hal->nCur80MhzPrimeSC != ChnlOffsetOf80MHz) ||\n\t\t\t(hal->CurrentCenterFrequencyIndex1 != CenterFrequencyIndex1))\n\t\t\thal->bSetChnlBW = _TRUE;\n\t}\n\n\t/* return if not need set bandwidth nor channel after check*/\n\tif (!hal->bSetChnlBW && !hal->bSwChnl && hal->bNeedIQK != _TRUE)\n\t\treturn;\n\n\t/* set channel number to hal data */\n\tif (hal->bSwChnl) {\n\t\thal->current_channel = ChannelNum;\n\t\thal->CurrentCenterFrequencyIndex1 = ChannelNum;\n\t}\n\n\t/* set bandwidth info to hal data */\n\tif (hal->bSetChnlBW) {\n\t\thal->current_channel_bw = ChnlWidth;\n\t\thal->nCur40MhzPrimeSC = ChnlOffsetOf40MHz;\n\t\thal->nCur80MhzPrimeSC = ChnlOffsetOf80MHz;\n\t\thal->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1;\n\t}\n\n\t/* switch channel & bandwidth */\n\tif (!RTW_CANNOT_RUN(Adapter))\n\t\trtl8822c_switch_chnl_and_set_bw(Adapter);\n\telse {\n\t\tif (hal->bSwChnl) {\n\t\t\thal->current_channel = tmpChannel;\n\t\t\thal->CurrentCenterFrequencyIndex1 = tmpChannel;\n\t\t}\n\n\t\tif (hal->bSetChnlBW) {\n\t\t\thal->current_channel_bw = tmpBW;\n\t\t\thal->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC;\n\t\t\thal->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC;\n\t\t\thal->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1;\n\t\t}\n\t}\n}\n\n/*\n * Description:\n *\tChange channel, bandwidth & offset\n * Parameters:\n *\tcenter_ch\tcenter channel\n *\tbw\t\tbandwidth\n *\toffset40\tchannel offset for 40MHz Bandwidth\n *\toffset80\tchannel offset for 80MHz Bandwidth\n */\nvoid rtl8822c_set_channel_bw(PADAPTER adapter, u8 center_ch, enum channel_width bw, u8 offset40, u8 offset80)\n{\n\trtl8822c_handle_sw_chnl_and_set_bw(adapter, _TRUE, _TRUE, center_ch, bw, offset40, offset80, center_ch);\n}\n\nvoid rtl8822c_notch_filter_switch(PADAPTER adapter, bool enable)\n{\n\tif (enable)\n\t\tRTW_INFO(\"%s: Enable notch filter\\n\", __FUNCTION__);\n\telse\n\t\tRTW_INFO(\"%s: Disable notch filter\\n\", __FUNCTION__);\n}\n\n#ifdef CONFIG_MP_INCLUDED\n/*\n * Description:\n *\tConfig RF path\n *\n * Parameters:\n *\tadapter\tpointer of struct _ADAPTER\n */\nvoid rtl8822c_mp_config_rfpath(PADAPTER adapter)\n{\n\tPHAL_DATA_TYPE hal;\n\tPMPT_CONTEXT mpt;\n\tANTENNA_PATH anttx, antrx;\n\tenum bb_path bb_tx, bb_rx;\n\n\n\thal = GET_HAL_DATA(adapter);\n\tmpt = &adapter->mppriv.mpt_ctx;\n\tanttx = hal->antenna_tx_path;\n\tantrx = hal->AntennaRxPath;\n\thal->antenna_test = _TRUE;\n\tRTW_INFO(\"+Config RF Path, tx=0x%x rx=0x%x\\n\", anttx, antrx);\n\n\tswitch (anttx) {\n\tcase ANTENNA_A:\n\t\tmpt->mpt_rf_path = RF_PATH_A;\n\t\tbb_tx = BB_PATH_A;\n\t\tbreak;\n\tcase ANTENNA_B:\n\t\tmpt->mpt_rf_path = RF_PATH_B;\n\t\tbb_tx = BB_PATH_B;\n\t\tbreak;\n\tcase ANTENNA_AB:\n\tdefault:\n\t\tmpt->mpt_rf_path = RF_PATH_AB;\n\t\tbb_tx = BB_PATH_A | BB_PATH_B;\n\t\tbreak;\n\t}\n\n\tswitch (antrx) {\n\tcase ANTENNA_A:\n\t\tbb_rx = BB_PATH_A;\n\t\tbreak;\n\tcase ANTENNA_B:\n\t\tbb_rx = BB_PATH_B;\n\t\tbreak;\n\tcase ANTENNA_AB:\n\tdefault:\n\t\tbb_rx = BB_PATH_A | BB_PATH_B;\n\t\tbreak;\n\t}\n\n\tconfig_phydm_trx_mode_8822c(GET_PDM_ODM(adapter), bb_tx, bb_rx, bb_tx);\n\n\tRTW_INFO(\"-Config RF Path Finish\\n\");\n}\n#endif /* CONFIG_MP_INCLUDED */\n\n#ifdef CONFIG_BEAMFORMING\n/* REG_TXBF_CTRL\t\t(Offset 0x42C) */\n#define BITS_R_TXBF1_AID_8822C\t\t\t(BIT_MASK_R_TXBF1_AID_8822C << BIT_SHIFT_R_TXBF1_AID_8822C)\n#define BIT_CLEAR_R_TXBF1_AID_8822C(x)\t\t((x) & (~BITS_R_TXBF1_AID_8822C))\n#define BIT_SET_R_TXBF1_AID_8822C(x, v)\t\t(BIT_CLEAR_R_TXBF1_AID_8822C(x) | BIT_R_TXBF1_AID_8822C(v))\n\n#define BITS_R_TXBF0_AID_8822C\t\t\t(BIT_MASK_R_TXBF0_AID_8822C << BIT_SHIFT_R_TXBF0_AID_8822C)\n#define BIT_CLEAR_R_TXBF0_AID_8822C(x)\t\t((x) & (~BITS_R_TXBF0_AID_8822C))\n#define BIT_SET_R_TXBF0_AID_8822C(x, v)\t\t(BIT_CLEAR_R_TXBF0_AID_8822C(x) | BIT_R_TXBF0_AID_8822C(v))\n\n/* REG_NDPA_OPT_CTRL\t\t(Offset 0x45F) */\n#define BITS_R_NDPA_BW_8822C\t\t\t(BIT_MASK_R_NDPA_BW_8822C << BIT_SHIFT_R_NDPA_BW_8822C)\n#define BIT_CLEAR_R_NDPA_BW_8822C(x)\t\t((x) & (~BITS_R_NDPA_BW_8822C))\n#define BIT_SET_R_NDPA_BW_8822C(x, v)\t\t(BIT_CLEAR_R_NDPA_BW_8822C(x) | BIT_R_NDPA_BW_8822C(v))\n\n/* REG_ASSOCIATED_BFMEE_SEL\t(Offset 0x714) */\n#define BITS_AID1_8822C\t\t\t\t(BIT_MASK_AID1_8822C << BIT_SHIFT_AID1_8822C)\n#define BIT_CLEAR_AID1_8822C(x)\t\t\t((x) & (~BITS_AID1_8822C))\n#define BIT_SET_AID1_8822C(x, v)\t\t(BIT_CLEAR_AID1_8822C(x) | BIT_AID1_8822C(v))\n\n#define BITS_AID0_8822C\t\t\t\t(BIT_MASK_AID0_8822C << BIT_SHIFT_AID0_8822C)\n#define BIT_CLEAR_AID0_8822C(x)\t\t\t((x) & (~BITS_AID0_8822C))\n#define BIT_SET_AID0_8822C(x, v)\t\t(BIT_CLEAR_AID0_8822C(x) | BIT_AID0_8822C(v))\n\n/* REG_SND_PTCL_CTRL\t\t(Offset 0x718) */\n#define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL_8822C\tBIT(15)\n\n/* REG_MU_TX_CTL\t\t(Offset 0x14C0) */\n#define BIT_R_MU_P1_WAIT_STATE_EN_8822C\t\tBIT(16)\n\n#define BIT_SHIFT_R_MU_RL_8822C\t\t\t12\n/* #define BIT_MASK_R_MU_RL_8822C\t\t\t0xF */\n#define BITS_R_MU_RL_8822C\t\t\t(BIT_MASK_R_MU_RL_8822C << BIT_SHIFT_R_MU_RL_8822C)\n#define BIT_R_MU_RL_8822C(x)\t\t\t(((x) & BIT_MASK_R_MU_RL_8822C) << BIT_SHIFT_R_MU_RL_8822C)\n#define BIT_CLEAR_R_MU_RL_8822C(x)\t\t((x) & (~BITS_R_MU_RL_8822C))\n#define BIT_SET_R_MU_RL_8822C(x, v)\t\t(BIT_CLEAR_R_MU_RL_8822C(x) | BIT_R_MU_RL_8822C(v))\n\n#define BIT_SHIFT_R_MU_TAB_SEL_8822C\t\t8\n#define BIT_MASK_R_MU_TAB_SEL_8822C\t\t0x7\n#define BITS_R_MU_TAB_SEL_8822C\t\t\t(BIT_MASK_R_MU_TAB_SEL_8822C << BIT_SHIFT_R_MU_TAB_SEL_8822C)\n#define BIT_R_MU_TAB_SEL_8822C(x)\t\t(((x) & BIT_MASK_R_MU_TAB_SEL_8822C) << BIT_SHIFT_R_MU_TAB_SEL_8822C)\n#define BIT_CLEAR_R_MU_TAB_SEL_8822C(x)\t\t((x) & (~BITS_R_MU_TAB_SEL_8822C))\n#define BIT_SET_R_MU_TAB_SEL_8822C(x, v)\t(BIT_CLEAR_R_MU_TAB_SEL_8822C(x) | BIT_R_MU_TAB_SEL_8822C(v))\n\n#define BIT_R_EN_MU_MIMO_8822C\t\t\tBIT(7)\n\n#define BITS_R_MU_TABLE_VALID_8822C\t\t(BIT_MASK_R_MU_TABLE_VALID_8822C << BIT_SHIFT_R_MU_TABLE_VALID_8822C)\n#define BIT_CLEAR_R_MU_TABLE_VALID_8822C(x)\t((x) & (~BITS_R_MU_TABLE_VALID_8822C))\n#define BIT_SET_R_MU_TABLE_VALID_8822C(x, v)\t(BIT_CLEAR_R_MU_TABLE_VALID_8822C(x) | BIT_R_MU_TABLE_VALID_8822C(v))\n\n/* REG_WMAC_MU_BF_CTL\t\t(Offset 0x1680) */\n#define BITS_WMAC_MU_BFRPTSEG_SEL_8822C\t\t\t(BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C)\n#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822C(x)\t\t((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8822C))\n#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8822C(x, v)\t(BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822C(x) | BIT_WMAC_MU_BFRPTSEG_SEL_8822C(v))\n\n#define BITS_WMAC_MU_BF_MYAID_8822C\t\t(BIT_MASK_WMAC_MU_BF_MYAID_8822C << BIT_SHIFT_WMAC_MU_BF_MYAID_8822C)\n#define BIT_CLEAR_WMAC_MU_BF_MYAID_8822C(x)\t((x) & (~BITS_WMAC_MU_BF_MYAID_8822C))\n#define BIT_SET_WMAC_MU_BF_MYAID_8822C(x, v)\t(BIT_CLEAR_WMAC_MU_BF_MYAID_8822C(x) | BIT_WMAC_MU_BF_MYAID_8822C(v))\n\n/* REG_WMAC_ASSOCIATED_MU_BFMEE7\t(Offset 0x168E) */\n#define BIT_STATUS_BFEE7_8822C\t\t\tBIT(10)\n\nenum _HW_CFG_SOUNDING_TYPE {\n\tHW_CFG_SOUNDING_TYPE_SOUNDDOWN,\n\tHW_CFG_SOUNDING_TYPE_LEAVE,\n\tHW_CFG_SOUNDING_TYPE_RESET,\n\tHW_CFG_SOUNDING_TYPE_MAX\n};\n\nstatic u8 _bf_get_nrx(PADAPTER adapter)\n{\n\tu8 rf;\n\tu8 nrx = 0;\n\n\n\trtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, &rf);\n\tswitch (rf) {\n\tcase RF_1T1R:\n\t\tnrx = 0;\n\t\tbreak;\n\tdefault:\n\tcase RF_1T2R:\n\tcase RF_2T2R:\n\t\tnrx = 1;\n\t\tbreak;\n\t}\n\n\treturn nrx;\n}\n\nstatic void _sounding_reset_all(PADAPTER adapter)\n{\n\tstruct beamforming_info *info;\n\tstruct beamformee_entry *bfee;\n\tu8 i;\n\tu32 mu_tx_ctl;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\trtw_write8(adapter, REG_TXBF_CTRL_8822C+3, 0);\n\n\t/* Clear all MU entry table */\n\tfor (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {\n\t\tbfee = &info->bfee_entry[i];\n\t\tfor (i = 0; i < 8; i++)\n\t\t\tbfee->gid_valid[i] = 0;\n\t}\n\n\tmu_tx_ctl = rtw_read32(adapter, REG_MU_TX_CTL_8822C);\n\tfor (i = 0; i < 6; i++) {\n\t\tmu_tx_ctl = BIT_SET_R_MU_TAB_SEL_8822C(mu_tx_ctl, i);\n\t\trtw_write32(adapter, REG_MU_TX_CTL_8822C, mu_tx_ctl);\n\t\t/* set MU STA gid valid table */\n\t\trtw_write32(adapter, REG_MU_STA_GID_VLD_8822C, 0);\n\t}\n\n\t/* Disable TxMU PPDU */\n\tmu_tx_ctl &= ~BIT_R_EN_MU_MIMO_8822C;\n\trtw_write32(adapter, REG_MU_TX_CTL_8822C, mu_tx_ctl);\n}\n\nstatic void _sounding_config_su(PADAPTER adapter, struct beamformee_entry *bfee, enum _HW_CFG_SOUNDING_TYPE cfg_type)\n{\n\tu32 txbf_ctrl, new_ctrl;\n\n\n\ttxbf_ctrl = rtw_read32(adapter, REG_TXBF_CTRL_8822C);\n\tnew_ctrl = txbf_ctrl;\n\n\t/* Clear TxBF status at 20M/40/80M first */\n\tswitch (bfee->su_reg_index) {\n\tcase 0:\n\t\tnew_ctrl &= ~(BIT_R_TXBF0_20M_8822C|BIT_R_TXBF0_40M_8822C|BIT_R_TXBF0_80M_8822C);\n\t\tbreak;\n\tcase 1:\n\t\tnew_ctrl &= ~(BIT_R_TXBF1_20M_8822C|BIT_R_TXBF1_40M_8822C|BIT_R_TXBF1_80M_8822C);\n\t\tbreak;\n\t}\n\n\tswitch (cfg_type) {\n\tcase HW_CFG_SOUNDING_TYPE_SOUNDDOWN:\n\t\tswitch (bfee->sound_bw) {\n\t\tdefault:\n\t\tcase CHANNEL_WIDTH_80:\n\t\t\tif (0 == bfee->su_reg_index)\n\t\t\t\tnew_ctrl |= BIT_R_TXBF0_80M_8822C;\n\t\t\telse if (1 == bfee->su_reg_index)\n\t\t\t\tnew_ctrl |= BIT_R_TXBF1_80M_8822C;\n\t\t\t/* fall through */\n\t\tcase CHANNEL_WIDTH_40:\n\t\t\tif (0 == bfee->su_reg_index)\n\t\t\t\tnew_ctrl |= BIT_R_TXBF0_40M_8822C;\n\t\t\telse if (1 == bfee->su_reg_index)\n\t\t\t\tnew_ctrl |= BIT_R_TXBF1_40M_8822C;\n\t\t\t/* fall through */\n\t\tcase CHANNEL_WIDTH_20:\n\t\t\tif (0 == bfee->su_reg_index)\n\t\t\t\tnew_ctrl |= BIT_R_TXBF0_20M_8822C;\n\t\t\telse if (1 == bfee->su_reg_index)\n\t\t\t\tnew_ctrl |= BIT_R_TXBF1_20M_8822C;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\n\tdefault:\n\t\tRTW_INFO(\"%s: SU cfg_type=%d, don't apply Vmatrix!\\n\", __FUNCTION__, cfg_type);\n\t\tbreak;\n\t}\n\n\tif (new_ctrl != txbf_ctrl)\n\t\trtw_write32(adapter, REG_TXBF_CTRL_8822C, new_ctrl);\n}\n\nstatic void _sounding_config_mu(PADAPTER adapter, struct beamformee_entry *bfee, enum _HW_CFG_SOUNDING_TYPE cfg_type)\n{\n\tstruct beamforming_info *info;\n\tu8 is_bitmap_ready = _FALSE;\n\tu32 mu_tx_ctl;\n\tu16 bitmap;\n\tu8 id1, id0, gid;\n\tu32 gid_valid[6] = {0};\n\tu8 i, j;\n\tu32 val32;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\tswitch (cfg_type) {\n\tcase HW_CFG_SOUNDING_TYPE_LEAVE:\n\t\tRTW_INFO(\"%s: MU HW_CFG_SOUNDING_TYPE_LEAVE\\n\", __FUNCTION__);\n\n\t\t/* Clear the entry table */\n\t\tmu_tx_ctl = rtw_read32(adapter, REG_MU_TX_CTL_8822C);\n\t\tif (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU)) {\n\t\t\tfor (i = 0; i < 8; i++)\n\t\t\t\tbfee->gid_valid[i] = 0;\n\n\t\t\tmu_tx_ctl = BIT_SET_R_MU_TAB_SEL_8822C(mu_tx_ctl, bfee->mu_reg_index);\n\t\t\trtw_write32(adapter, REG_MU_TX_CTL_8822C, mu_tx_ctl);\n\t\t\t/* Set MU STA gid valid table */\n\t\t\trtw_write32(adapter, REG_MU_STA_GID_VLD_8822C, 0);\n\t\t} else {\n\t\t\tRTW_ERR(\"%s: ERROR! It is not an MU BFee entry!!\\n\",  __FUNCTION__);\n\t\t}\n\n\t\tif (info->beamformee_su_cnt == 0) {\n\t\t\t/* Disable TxMU PPDU */\n\t\t\tmu_tx_ctl &= ~BIT_R_EN_MU_MIMO_8822C;\n\t\t\trtw_write32(adapter, REG_MU_TX_CTL_8822C, mu_tx_ctl);\n\t\t}\n\n\t\tbreak;\n\n\tcase HW_CFG_SOUNDING_TYPE_SOUNDDOWN:\n\t\tRTW_INFO(\"%s: MU HW_CFG_SOUNDING_TYPE_SOUNDDOWN\\n\",  __FUNCTION__);\n\n\t\t/* Update all MU entry table */\n\t\ti = 0;\n\t\tdo {\n\t\t\t/* Check BB GID bitmap ready */\n\t\t\tval32 = phy_query_bb_reg(adapter, 0xF4C, 0xFFFF0000);\n\n\t\t\tis_bitmap_ready = (val32 & BIT(15)) ? _TRUE : _FALSE;\n\t\t\ti++;\n\t\t\trtw_udelay_os(5);\n\t\t} while ((_FALSE == is_bitmap_ready) && (i < 100));\n\n\t\tbitmap = (u16)(val32 & 0x3FFF);\n\n\t\tfor (i = 0; i < 15; i++) {\n\t\t\tif (i < 5) {\n\t\t\t\t/* bit0~4 */\n\t\t\t\tid0 = 0;\n\t\t\t\tid1 = i + 1;\n\t\t\t} else if (i < 9) {\n\t\t\t\t/* bit5~8 */\n\t\t\t\tid0 = 1;\n\t\t\t\tid1 = i - 3;\n\t\t\t} else if (i < 12) {\n\t\t\t\t/* bit9~11 */\n\t\t\t\tid0 = 2;\n\t\t\t\tid1 = i - 6;\n\t\t\t} else if (i < 14) {\n\t\t\t\t/* bit12~13 */\n\t\t\t\tid0 = 3;\n\t\t\t\tid1 = i - 8;\n\t\t\t} else {\n\t\t\t\t/* bit14 */\n\t\t\t\tid0 = 4;\n\t\t\t\tid1 = i - 9;\n\t\t\t}\n\t\t\tif (bitmap & BIT(i)) {\n\t\t\t\t/* Pair 1 */\n\t\t\t\tgid = (i << 1) + 1;\n\t\t\t\tgid_valid[id0] |= (BIT(gid));\n\t\t\t\tgid_valid[id1] |= (BIT(gid));\n\t\t\t\t/* Pair 2 */\n\t\t\t\tgid += 1;\n\t\t\t\tgid_valid[id0] |= (BIT(gid));\n\t\t\t\tgid_valid[id1] |= (BIT(gid));\n\t\t\t} else {\n\t\t\t\t/* Pair 1 */\n\t\t\t\tgid = (i << 1) + 1;\n\t\t\t\tgid_valid[id0] &= ~(BIT(gid));\n\t\t\t\tgid_valid[id1] &= ~(BIT(gid));\n\t\t\t\t/* Pair 2 */\n\t\t\t\tgid += 1;\n\t\t\t\tgid_valid[id0] &= ~(BIT(gid));\n\t\t\t\tgid_valid[id1] &= ~(BIT(gid));\n\t\t\t}\n\t\t}\n\n\t\tfor (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {\n\t\t\tbfee = &info->bfee_entry[i];\n\t\t\tif (_FALSE == bfee->used)\n\t\t\t\tcontinue;\n\t\t\tif (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU)\n\t\t\t    && (bfee->mu_reg_index < 6)) {\n\t\t\t\tval32 = gid_valid[bfee->mu_reg_index];\n\t\t\t\tfor (j = 0; j < 4; j++) {\n\t\t\t\t\tbfee->gid_valid[j] = (u8)(val32 & 0xFF);\n\t\t\t\t\tval32 >>= 8;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tmu_tx_ctl = rtw_read32(adapter, REG_MU_TX_CTL_8822C);\n\t\tfor (i = 0; i < 6; i++) {\n\t\t\tmu_tx_ctl = BIT_SET_R_MU_TAB_SEL_8822C(mu_tx_ctl, i);\n\t\t\trtw_write32(adapter, REG_MU_TX_CTL_8822C, mu_tx_ctl);\n\t\t\t/* Set MU STA gid valid table */\n\t\t\trtw_write32(adapter, REG_MU_STA_GID_VLD_8822C, gid_valid[i]);\n\t\t}\n\n\t\t/* Enable TxMU PPDU */\n\t\tmu_tx_ctl |= BIT_R_EN_MU_MIMO_8822C;\n\t\trtw_write32(adapter, REG_MU_TX_CTL_8822C, mu_tx_ctl);\n\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nstatic void _config_sounding(PADAPTER adapter, struct beamformee_entry *bfee, u8 mu_sounding, enum _HW_CFG_SOUNDING_TYPE cfg_type)\n{\n\tif (cfg_type == HW_CFG_SOUNDING_TYPE_RESET) {\n\t\tRTW_INFO(\"%s: HW_CFG_SOUNDING_TYPE_RESET\\n\", __FUNCTION__);\n\t\t_sounding_reset_all(adapter);\n\t\treturn;\n\t}\n\n\tif (_FALSE == mu_sounding)\n\t\t_sounding_config_su(adapter, bfee, cfg_type);\n\telse\n\t\t_sounding_config_mu(adapter, bfee, cfg_type);\n}\n\nstatic void _config_beamformer_su(PADAPTER adapter, struct beamformer_entry *bfer)\n{\n\t/* Beamforming */\n\tu8 nc_index = 0, nr_index = 0;\n\tu8 grouping = 0, codebookinfo = 0, coefficientsize = 0;\n\tu32 addr_bfer_info, addr_csi_rpt;\n\tu32 csi_param;\n\t/* Misc */\n\tu8 i;\n\n\n\tRTW_INFO(\"%s: Config SU BFer entry HW setting\\n\", __FUNCTION__);\n\n\tif (bfer->su_reg_index == 0) {\n\t\taddr_bfer_info = REG_ASSOCIATED_BFMER0_INFO_8822C;\n\t\taddr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20_8822C;\n\t} else {\n\t\taddr_bfer_info = REG_ASSOCIATED_BFMER1_INFO_8822C;\n\t\taddr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20_8822C + 2;\n\t}\n\n\t/* Sounding protocol control */\n\trtw_write8(adapter, REG_SND_PTCL_CTRL_8822C, 0xDB);\n\n\t/* MAC address/Partial AID of Beamformer */\n\tfor (i = 0; i < ETH_ALEN; i++)\n\t\trtw_write8(adapter, addr_bfer_info+i, bfer->mac_addr[i]);\n\n\t/* CSI report parameters of Beamformer */\n\tnc_index = _bf_get_nrx(adapter);\n\t/*\n\t * 0x718[7] = 1 use Nsts\n\t * 0x718[7] = 0 use reg setting\n\t * As Bfee, we use Nsts, so nr_index don't care\n\t */\n\tnr_index = bfer->NumofSoundingDim;\n\tgrouping = 0;\n\t/* for ac = 1, for n = 3 */\n\tif (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_SU))\n\t\tcodebookinfo = 1;\n\telse if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_HT_EXPLICIT))\n\t\tcodebookinfo = 3;\n\tcoefficientsize = 3;\n\tcsi_param = (u16)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(nr_index<<3)|(nc_index));\n\trtw_write16(adapter, addr_csi_rpt, csi_param);\n\tRTW_INFO(\"%s: nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\\n\",\n\t\t __FUNCTION__, nc_index, nr_index, grouping, codebookinfo, coefficientsize);\n\tRTW_INFO(\"%s: csi=0x%04x\\n\", __FUNCTION__, csi_param);\n\n\t/* ndp_rx_standby_timer */\n\trtw_write8(adapter, REG_SND_PTCL_CTRL_8822C+3, 0x70);\n\n\t/* partial merge from halmac api cfg_sounding_88xx(), may need to refine to apply the api immediately */\n\t{\n\t\tu32 tmp6dc = 0;\n\t\tu8 csi_rsc = 0x0;\n\n\t\ttmp6dc = (rtw_read32(adapter, REG_BBPSF_CTRL_8822C) | BIT(30) |  (csi_rsc << 13));\n\t\tif (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE)\n\t\t\ttmp6dc |= BIT(12);\n\t\telse\n\t\t\ttmp6dc &= ~BIT(12);\n\t\trtw_write32(adapter, REG_BBPSF_CTRL_8822C, tmp6dc);\n\n\t\trtw_write32(adapter, REG_CSI_RRSR_8822C, 0x550);\n\t}\n}\n\nstatic void _config_beamformer_mu(PADAPTER adapter, struct beamformer_entry *bfer)\n{\n\t/* General */\n\tPHAL_DATA_TYPE hal;\n\t/* Beamforming */\n\tstruct beamforming_info *bf_info;\n\tu8 nc_index = 0, nr_index = 0;\n\tu8 grouping = 0, codebookinfo = 0, coefficientsize = 0;\n\tu32 csi_param;\n\t/* Misc */\n\tu8 i, val8;\n\tu16 val16;\n\n\tRTW_INFO(\"%s: Config MU BFer entry HW setting\\n\", __FUNCTION__);\n\n\thal = GET_HAL_DATA(adapter);\n\tbf_info = GET_BEAMFORM_INFO(adapter);\n\n\t/* Reset GID table */\n\tfor (i = 0; i < 8; i++)\n\t\tbfer->gid_valid[i] = 0;\n\tfor (i = 0; i < 16; i++)\n\t\tbfer->user_position[i] = 0;\n\n\t/* CSI report parameters of Beamformer */\n\tnc_index = _bf_get_nrx(adapter);\n\tnr_index = 1; /* 0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care */\n\tgrouping = 0; /* no grouping */\n\tcodebookinfo = 1; /* 7 bit for psi, 9 bit for phi */\n\tcoefficientsize = 0; /* This is nothing really matter */\n\tcsi_param = (u16)((coefficientsize<<10)|(codebookinfo<<8)|\n\t\t\t(grouping<<6)|(nr_index<<3)|(nc_index));\n\n\tRTW_INFO(\"%s: nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\\n\",\n\t\t__func__, nc_index, nr_index, grouping, codebookinfo,\n\t\tcoefficientsize);\n\tRTW_INFO(\"%s: csi=0x%04x\\n\", __func__, csi_param);\n\n\trtw_halmac_bf_add_mu_bfer(adapter_to_dvobj(adapter), bfer->p_aid,\n\t\t\tcsi_param, bfer->aid & 0xfff, HAL_CSI_SEG_4K,\n\t\t\tbfer->mac_addr);\n\n\tbf_info->cur_csi_rpt_rate = HALMAC_OFDM6;\n\trtw_halmac_bf_cfg_sounding(adapter_to_dvobj(adapter), HAL_BFEE,\n\t\t\tbf_info->cur_csi_rpt_rate);\n\n\t/* Set 0x6A0[14] = 1 to accept action_no_ack */\n\tval8 = rtw_read8(adapter, REG_RXFLTMAP0_8822C+1);\n\tval8 |= (BIT_MGTFLT14EN_8822C >> 8);\n\trtw_write8(adapter, REG_RXFLTMAP0_8822C+1, val8);\n\n\t/* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */\n\tval8 = rtw_read8(adapter, REG_RXFLTMAP1_8822C);\n\tval8 |= BIT_CTRLFLT4EN_8822C | BIT_CTRLFLT5EN_8822C;\n\trtw_write8(adapter, REG_RXFLTMAP1_8822C, val8);\n\n}\n\nstatic void _config_beamformee_su(PADAPTER adapter, struct beamformee_entry *bfee)\n{\n\t/* General */\n\tstruct mlme_priv *mlme;\n\t/* Beamforming */\n\tstruct beamforming_info *info;\n\tu8 idx;\n\tu16 p_aid = 0;\n\t/* Misc */\n\tu8 val8;\n\tu16 val16;\n\tu32 val32;\n\n\n\tRTW_INFO(\"%s: Config SU BFee entry HW setting\\n\", __FUNCTION__);\n\n\tmlme = &adapter->mlmepriv;\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tidx = bfee->su_reg_index;\n\n\tif ((check_fwstate(mlme, WIFI_ADHOC_STATE) == _TRUE)\n\t    || (check_fwstate(mlme, WIFI_ADHOC_MASTER_STATE) == _TRUE))\n\t\tp_aid = bfee->mac_id;\n\telse\n\t\tp_aid = bfee->p_aid;\n\n\tphydm_txbf_rfmode(GET_PDM_ODM(adapter), info->beamformee_su_cnt, info->beamformee_mu_cnt);\n\n\t/* P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt */\n\tval32 = rtw_read32(adapter, REG_TXBF_CTRL_8822C);\n\tif (idx == 0) {\n\t\tval32 = BIT_SET_R_TXBF0_AID_8822C(val32, p_aid);\n\t\tval32 &= ~(BIT_R_TXBF0_20M_8822C | BIT_R_TXBF0_40M_8822C | BIT_R_TXBF0_80M_8822C);\n\t} else {\n\t\tval32 = BIT_SET_R_TXBF1_AID_8822C(val32, p_aid);\n\t\tval32 &= ~(BIT_R_TXBF1_20M_8822C | BIT_R_TXBF1_40M_8822C | BIT_R_TXBF1_80M_8822C);\n\t}\n\tval32 |= BIT_R_EN_NDPA_INT_8822C | BIT_USE_NDPA_PARAMETER_8822C | BIT_R_ENABLE_NDPA_8822C;\n\trtw_write32(adapter, REG_TXBF_CTRL_8822C, val32);\n\n\t/* CSI report parameters of Beamformee */\n\tval32 = rtw_read32(adapter, REG_ASSOCIATED_BFMEE_SEL_8822C);\n\tif (idx == 0) {\n\t\tval32 = BIT_SET_AID0_8822C(val32, p_aid);\n\t\tval32 |= BIT_TXUSER_ID0_8822C;\n\n\t\t/* unknown? */\n\t\tval32 &= 0x03FFFFFF;\n\t\tval32 |= 0x60000000;\n\t} else {\n\t\tval32 = BIT_SET_AID1_8822C(val32, p_aid);\n\t\tval32 |= BIT_TXUSER_ID1_8822C;\n\n\t\t/* unknown? */\n\t\tval32 &= 0x03FFFFFF;\n\t\tval32 |= 0xE0000000;\n\t}\n\trtw_write32(adapter, REG_ASSOCIATED_BFMEE_SEL_8822C, val32);\n}\n\nstatic void _config_beamformee_mu(PADAPTER adapter, struct beamformee_entry *bfee)\n{\n\t/* General */\n\tPHAL_DATA_TYPE hal;\n\t/* Beamforming */\n\tstruct beamforming_info *info;\n\tu8 idx;\n\tu32 gid_valid = 0, user_position_l = 0, user_position_h = 0;\n\tu32 mu_reg[6] = {REG_WMAC_ASSOCIATED_MU_BFMEE2_8822C,\n\t\t\t REG_WMAC_ASSOCIATED_MU_BFMEE3_8822C,\n\t\t\t REG_WMAC_ASSOCIATED_MU_BFMEE4_8822C,\n\t\t\t REG_WMAC_ASSOCIATED_MU_BFMEE5_8822C,\n\t\t\t REG_WMAC_ASSOCIATED_MU_BFMEE6_8822C,\n\t\t\t REG_WMAC_ASSOCIATED_MU_BFMEE7_8822C};\n\t/* Misc */\n\tu8 i, val8;\n\tu16 val16;\n\tu32 val32;\n\n\n\tRTW_INFO(\"%s: Config MU BFee entry HW setting\\n\", __FUNCTION__);\n\n\thal = GET_HAL_DATA(adapter);\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tidx = bfee->mu_reg_index;\n\n\t/* User position table */\n\tswitch (idx) {\n\tcase 0:\n\t\tgid_valid = 0x7fe;\n\t\tuser_position_l = 0x111110;\n\t\tuser_position_h = 0x0;\n\t\tbreak;\n\tcase 1:\n\t\tgid_valid = 0x7f806;\n\t\tuser_position_l = 0x11000004;\n\t\tuser_position_h = 0x11;\n\t\tbreak;\n\tcase 2:\n\t\tgid_valid = 0x1f81818;\n\t\tuser_position_l = 0x400040;\n\t\tuser_position_h = 0x11100;\n\t\tbreak;\n\tcase 3:\n\t\tgid_valid = 0x1e186060;\n\t\tuser_position_l = 0x4000400;\n\t\tuser_position_h = 0x1100040;\n\t\tbreak;\n\tcase 4:\n\t\tgid_valid = 0x66618180;\n\t\tuser_position_l = 0x40004000;\n\t\tuser_position_h = 0x10040400;\n\t\tbreak;\n\tcase 5:\n\t\tgid_valid = 0x79860600;\n\t\tuser_position_l = 0x40000;\n\t\tuser_position_h = 0x4404004;\n\t\tbreak;\n\t}\n\n\tfor (i = 0; i < 8; i++) {\n\t\tif (i < 4) {\n\t\t\tbfee->gid_valid[i] = (u8)(gid_valid & 0xFF);\n\t\t\tgid_valid >>= 8;\n\t\t} else {\n\t\t\tbfee->gid_valid[i] = 0;\n\t\t}\n\t}\n\tfor (i = 0; i < 16; i++) {\n\t\tif (i < 4)\n\t\t\tbfee->user_position[i] = (u8)((user_position_l >> (i*8)) & 0xFF);\n\t\telse if (i < 8)\n\t\t\tbfee->user_position[i] = (u8)((user_position_h >> ((i-4)*8)) & 0xFF);\n\t\telse\n\t\t\tbfee->user_position[i] = 0;\n\t}\n\n\t/* Sounding protocol control */\n\trtw_write8(adapter, REG_SND_PTCL_CTRL_8822C, 0xDB);\n\n\t/* select MU STA table */\n\tval32 = rtw_read32(adapter, REG_MU_TX_CTL_8822C);\n\tval32 = BIT_SET_R_MU_TAB_SEL_8822C(val32, idx);\n\trtw_write32(adapter, REG_MU_TX_CTL_8822C, val32);\n\n\t/* Reset gid_valid table */\n\trtw_write32(adapter, REG_MU_STA_GID_VLD_8822C, 0);\n\trtw_write32(adapter, REG_MU_STA_USER_POS_INFO_8822C , user_position_l);\n\trtw_write32(adapter, REG_MU_STA_USER_POS_INFO_8822C+4 , user_position_h);\n\n\t/* set validity of MU STAs */\n\tval32 = BIT_SET_R_MU_TABLE_VALID_8822C(val32, info->beamformee_mu_reg_maping);\n\trtw_write32(adapter, REG_MU_TX_CTL_8822C, val32);\n\n\tRTW_INFO(\"%s: RegMUTxCtrl=0x%x, user_position_l=0x%x, user_position_h=0x%x\\n\",\n\t\t __FUNCTION__, val32, user_position_l, user_position_h);\n\n\tval16 = rtw_read16(adapter, mu_reg[idx]);\n\tval16 &= 0xFE00; /* Clear PAID */\n\tval16 |= BIT(9); /* Enable MU BFee */\n\tval16 |= bfee->p_aid;\n\trtw_write16(adapter, mu_reg[idx], val16);\n\tRTW_INFO(\"%s: Write mu_reg 0x%x = 0x%x\\n\",\n\t\t __FUNCTION__, mu_reg[idx], val16);\n\n\t/* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */\n\tval8 = rtw_read8(adapter, REG_TXBF_CTRL_8822C+3);\n\tval8 |= 0xD0; /* Set bit 28, 30, 31 to 3b'111 */\n\trtw_write8(adapter, REG_TXBF_CTRL_8822C+3, val8);\n\n\t/* Set NDPA rate*/\n\tval8 = phydm_get_ndpa_rate(GET_PDM_ODM(adapter));\n\trtw_write8(adapter, REG_NDPA_RATE_8822C, val8);\n\n\tval8 = rtw_read8(adapter, REG_NDPA_OPT_CTRL_8822C);\n\tval8 = BIT_SET_R_NDPA_BW_8822C(val8, 0); /* Clear bit 0, 1 */\n\trtw_write8(adapter, REG_NDPA_OPT_CTRL_8822C, val8);\n\n\tval32 = rtw_read32(adapter, REG_SND_PTCL_CTRL_8822C);\n\tval32 = (val32 & 0xFF0000FF) | 0x020200; /* Set [23:8] to 0x0202 */\n\trtw_write32(adapter, REG_SND_PTCL_CTRL_8822C, val32);\n\n\t/* Set 0x6A0[14] = 1 to accept action_no_ack */\n\tval8 = rtw_read8(adapter, REG_RXFLTMAP0_8822C+1);\n\tval8 |= (BIT_MGTFLT14EN_8822C >> 8);\n\trtw_write8(adapter, REG_RXFLTMAP0_8822C+1, val8);\n\n\t/* 0x718[15] = 1. Patch for STA2 CSI report start offset error issue */\n\tval8 = rtw_read8(adapter, REG_SND_PTCL_CTRL_8822C+1);\n\tval8 |= (BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL_8822C >> 8);\n\trtw_write8(adapter, REG_SND_PTCL_CTRL_8822C+1, val8);\n\n\t/* End of MAC registers setting */\n\n\tphydm_txbf_rfmode(GET_PDM_ODM(adapter), info->beamformee_su_cnt, info->beamformee_mu_cnt);\n\n\t/* <tynli_mark> <TODO> Need to set timer 2015.12.23 */\n\t/* Special for plugfest */\n\trtw_mdelay_os(50); /* wait for 4-way handshake ending */\n\trtw_bf_send_vht_gid_mgnt_packet(adapter, bfee->mac_addr, bfee->gid_valid, bfee->user_position);\n}\n\nstatic void _reset_beamformer_su(PADAPTER adapter, struct beamformer_entry *bfer)\n{\n\t/* Beamforming */\n\tstruct beamforming_info *info;\n\tu8 idx;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\t/* SU BFer */\n\tidx = bfer->su_reg_index;\n\n\tif (idx == 0) {\n\t\trtw_write32(adapter, REG_ASSOCIATED_BFMER0_INFO_8822C, 0);\n\t\trtw_write16(adapter, REG_ASSOCIATED_BFMER0_INFO_8822C+4, 0);\n\t\trtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822C, 0);\n\t} else {\n\t\trtw_write32(adapter, REG_ASSOCIATED_BFMER1_INFO_8822C, 0);\n\t\trtw_write16(adapter, REG_ASSOCIATED_BFMER1_INFO_8822C+4, 0);\n\t\trtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822C+2, 0);\n\t}\n\n\tinfo->beamformer_su_reg_maping &= ~BIT(idx);\n\tbfer->su_reg_index = 0xFF;\n\n\tRTW_INFO(\"%s: Clear SU BFer entry(%d) HW setting\\n\", __FUNCTION__, idx);\n}\n\nstatic void _reset_beamformer_mu(PADAPTER adapter, struct beamformer_entry *bfer)\n{\n\tstruct beamforming_info *bf_info;\n\n\tbf_info = GET_BEAMFORM_INFO(adapter);\n\n\trtw_halmac_bf_del_mu_bfer(adapter_to_dvobj(adapter));\n\n\tif (bf_info->beamformer_su_cnt == 0 &&\n\t\t\tbf_info->beamformer_mu_cnt == 0)\n\t\trtw_halmac_bf_del_sounding(adapter_to_dvobj(adapter), HAL_BFEE);\n\n\tRTW_INFO(\"%s: Clear MU BFer entry HW setting\\n\", __FUNCTION__);\n}\n\nstatic void _reset_beamformee_su(PADAPTER adapter, struct beamformee_entry *bfee)\n{\n\t/* Beamforming */\n\tstruct beamforming_info *info;\n\tu8 idx;\n\t/* Misc */\n\tu32 txbf_ctrl, bfmee_sel;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\t/* SU BFee */\n\tidx = bfee->su_reg_index;\n\n\t/* Force disable sounding config */\n\t_config_sounding(adapter, bfee, _FALSE, HW_CFG_SOUNDING_TYPE_LEAVE);\n\n\t/* clear P_AID */\n\ttxbf_ctrl = rtw_read32(adapter, REG_TXBF_CTRL_8822C);\n\tbfmee_sel = rtw_read32(adapter, REG_ASSOCIATED_BFMEE_SEL_8822C);\n\tif (idx == 0) {\n\t\ttxbf_ctrl = BIT_SET_R_TXBF0_AID_8822C(txbf_ctrl, 0);\n\t\ttxbf_ctrl &= ~(BIT_R_TXBF0_20M_8822C | BIT_R_TXBF0_40M_8822C | BIT_R_TXBF0_80M_8822C);\n\n\t\tbfmee_sel = BIT_SET_AID0_8822C(bfmee_sel, 0);\n\t\tbfmee_sel &= ~BIT_TXUSER_ID0_8822C;\n\t} else {\n\t\ttxbf_ctrl = BIT_SET_R_TXBF1_AID_8822C(txbf_ctrl, 0);\n\t\ttxbf_ctrl &= ~(BIT_R_TXBF1_20M_8822C | BIT_R_TXBF1_40M_8822C | BIT_R_TXBF1_80M_8822C);\n\n\t\tbfmee_sel = BIT_SET_AID1_8822C(bfmee_sel, 0);\n\t\tbfmee_sel &= ~BIT_TXUSER_ID1_8822C;\n\t}\n\ttxbf_ctrl |= BIT_R_EN_NDPA_INT_8822C | BIT_USE_NDPA_PARAMETER_8822C | BIT_R_ENABLE_NDPA_8822C;\n\trtw_write32(adapter, REG_TXBF_CTRL_8822C, txbf_ctrl);\n\trtw_write32(adapter, REG_ASSOCIATED_BFMEE_SEL_8822C, bfmee_sel);\n\n\tinfo->beamformee_su_reg_maping &= ~BIT(idx);\n\tbfee->su_reg_index = 0xFF;\n\n\tRTW_INFO(\"%s: Clear SU BFee entry(%d) HW setting\\n\", __FUNCTION__, idx);\n}\n\nstatic void _reset_beamformee_mu(PADAPTER adapter, struct beamformee_entry *bfee)\n{\n\t/* Beamforming */\n\tstruct beamforming_info *info;\n\tu8 idx;\n\tu32 mu_reg[6] = {REG_WMAC_ASSOCIATED_MU_BFMEE2_8822C,\n\t\t\t REG_WMAC_ASSOCIATED_MU_BFMEE3_8822C,\n\t\t\t REG_WMAC_ASSOCIATED_MU_BFMEE4_8822C,\n\t\t\t REG_WMAC_ASSOCIATED_MU_BFMEE5_8822C,\n\t\t\t REG_WMAC_ASSOCIATED_MU_BFMEE6_8822C,\n\t\t\t REG_WMAC_ASSOCIATED_MU_BFMEE7_8822C};\n\t/* Misc */\n\tu32 val32;\n\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\t/* MU BFee */\n\tidx = bfee->mu_reg_index;\n\n\t/* Disable sending NDPA & BF-rpt-poll to this BFee */\n\trtw_write16(adapter, mu_reg[idx] , 0);\n\t/* Set validity of MU STA */\n\tval32 = rtw_read32(adapter, REG_MU_TX_CTL_8822C);\n\tval32 &= ~BIT(idx);\n\trtw_write32(adapter, REG_MU_TX_CTL_8822C, val32);\n\n\t/* Force disable sounding config */\n\t_config_sounding(adapter, bfee, _TRUE, HW_CFG_SOUNDING_TYPE_LEAVE);\n\n\tinfo->beamformee_mu_reg_maping &= ~BIT(idx);\n\tbfee->mu_reg_index = 0xFF;\n\n\tRTW_INFO(\"%s: Clear MU BFee entry(%d) HW setting\\n\", __FUNCTION__, idx);\n}\n\nvoid rtl8822c_phy_bf_reset_all(PADAPTER adapter)\n{\n\tstruct beamforming_info *info;\n\tu8 i, val8;\n\tu32 val32;\n\n\n\tRTW_INFO(\"+%s\\n\", __FUNCTION__);\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\tinfo->bSetBFHwConfigInProgess = _TRUE;\n\n\t/* Reset MU BFer entry setting */\n\t/* Clear validity of MU STA0 and MU STA1 */\n\tval32 = rtw_read32(adapter, REG_MU_TX_CTL_8822C);\n\tval32 = BIT_SET_R_MU_TABLE_VALID_8822C(val32, 0);\n\trtw_write32(adapter, REG_MU_TX_CTL_8822C, val32);\n\n\t/* Reset SU BFer entry setting */\n\trtw_write32(adapter, REG_ASSOCIATED_BFMER0_INFO_8822C, 0);\n\trtw_write16(adapter, REG_ASSOCIATED_BFMER0_INFO_8822C+4, 0);\n\trtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822C, 0);\n\n\trtw_write32(adapter, REG_ASSOCIATED_BFMER1_INFO_8822C, 0);\n\trtw_write16(adapter, REG_ASSOCIATED_BFMER1_INFO_8822C+4, 0);\n\trtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822C+2, 0);\n\n\t/* Force disable sounding */\n\t_config_sounding(adapter, NULL, _FALSE, HW_CFG_SOUNDING_TYPE_RESET);\n\n\t/* Config RF mode */\n\tphydm_txbf_rfmode(GET_PDM_ODM(adapter), info->beamformee_su_cnt, info->beamformee_mu_cnt);\n\n\t/* Reset MU BFee entry setting */\n\n\t/* Disable sending NDPA & BF-rpt-poll to all BFee */\n\tfor (i=0; i < MAX_NUM_BEAMFORMEE_MU; i++)\n\t\trtw_write16(adapter, REG_WMAC_ASSOCIATED_MU_BFMEE2_8822C+(i*2), 0);\n\n\t/* set validity of MU STA */\n\trtw_write32(adapter, REG_MU_TX_CTL_8822C, 0);\n\n\t/* Reset SU BFee entry setting */\n\t/* SU BF0 and BF1 */\n\tval32 = BIT_R_EN_NDPA_INT_8822C | BIT_USE_NDPA_PARAMETER_8822C | BIT_R_ENABLE_NDPA_8822C;\n\trtw_write32(adapter, REG_TXBF_CTRL_8822C, val32);\n\trtw_write32(adapter, REG_ASSOCIATED_BFMEE_SEL_8822C, 0);\n\n\tinfo->bSetBFHwConfigInProgess = _FALSE;\n\n\tRTW_INFO(\"-%s\\n\", __FUNCTION__);\n}\n\nvoid rtl8822c_phy_bf_init(PADAPTER adapter)\n{\n\tu8 v8;\n\tu32 v32;\n\n\tv32 = rtw_read32(adapter, REG_MU_TX_CTL_8822C);\n\t/* Enable P1 aggr new packet according to P0 transfer time */\n\tv32 |= BIT_R_MU_P1_WAIT_STATE_EN_8822C;\n\t/* MU Retry Limit */\n\tv32 = BIT_SET_R_MU_RL_8822C(v32, 0xA);\n\t/* Disable Tx MU-MIMO until sounding done */\n\tv32 &= ~BIT_R_EN_MU_MIMO_8822C;\n\t/* Clear validity of MU STAs */\n\tv32 = BIT_SET_R_MU_TABLE_VALID_8822C(v32, 0);\n\trtw_write32(adapter, REG_MU_TX_CTL_8822C, v32);\n\n\t/* MU-MIMO Option as default value */\n\tv8 = BIT_WMAC_TXMU_ACKPOLICY_8822C(3);\n\tv8 |= BIT_WMAC_TXMU_ACKPOLICY_EN_8822C;\n\trtw_write8(adapter, REG_MU_BF_OPTION_8822C, v8);\n\t/* MU-MIMO Control as default value */\n\trtw_write16(adapter, REG_WMAC_MU_BF_CTL_8822C, 0);\n\n\t/* Set MU NDPA rate & BW source */\n\t/* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */\n\tv8 = rtw_read8(adapter, REG_TXBF_CTRL_8822C+3);\n\tv8 |= (BIT_USE_NDPA_PARAMETER_8822C >> 24);\n\trtw_write8(adapter, REG_TXBF_CTRL_8822C+3, v8);\n\t/* 0x45F[7:0] = 0x10 (Rate=OFDM_6M, BW20) */\n\trtw_write8(adapter, REG_NDPA_OPT_CTRL_8822C, 0x10);\n\n\t/* Temp Settings */\n\t/* STA2's CSI rate is fixed at 6M */\n\tv8 = rtw_read8(adapter, 0x6DF);\n\tv8 = (v8 & 0xC0) | 0x4;\n\trtw_write8(adapter, 0x6DF, v8);\n}\n\nvoid rtl8822c_phy_bf_enter(PADAPTER adapter, struct sta_info *sta)\n{\n\tstruct beamforming_info *info;\n\tstruct beamformer_entry *bfer;\n\tstruct beamformee_entry *bfee;\n\n\n\tRTW_INFO(\"+%s: \" MAC_FMT \"\\n\", __FUNCTION__, MAC_ARG(sta->cmn.mac_addr));\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tbfer = rtw_bf_bfer_get_entry_by_addr(adapter, sta->cmn.mac_addr);\n\tbfee = rtw_bf_bfee_get_entry_by_addr(adapter, sta->cmn.mac_addr);\n\n\tinfo->bSetBFHwConfigInProgess = _TRUE;\n\n\tif (bfer) {\n\t\tbfer->state = BEAMFORM_ENTRY_HW_STATE_ADDING;\n\n\t\tif (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_MU))\n\t\t\t_config_beamformer_mu(adapter, bfer);\n\t\telse if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT))\n\t\t\t_config_beamformer_su(adapter, bfer);\n\n\t\tbfer->state = BEAMFORM_ENTRY_HW_STATE_ADDED;\n\t}\n\n\tif (bfee) {\n\t\tbfee->state = BEAMFORM_ENTRY_HW_STATE_ADDING;\n\n\t\tif (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU))\n\t\t\t_config_beamformee_mu(adapter, bfee);\n\t\telse if (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT))\n\t\t\t_config_beamformee_su(adapter, bfee);\n\n\t\tbfee->state = BEAMFORM_ENTRY_HW_STATE_ADDED;\n\t}\n\n\tinfo->bSetBFHwConfigInProgess = _FALSE;\n\n\tRTW_INFO(\"-%s\\n\", __FUNCTION__);\n}\n\nvoid rtl8822c_phy_bf_leave(PADAPTER adapter, u8 *addr)\n{\n\tstruct beamforming_info *info;\n\tstruct beamformer_entry *bfer;\n\tstruct beamformee_entry *bfee;\n\n\n\tRTW_INFO(\"+%s: \" MAC_FMT \"\\n\", __FUNCTION__, MAC_ARG(addr));\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\n\tbfer = rtw_bf_bfer_get_entry_by_addr(adapter, addr);\n\tbfee = rtw_bf_bfee_get_entry_by_addr(adapter, addr);\n\n\t/* Clear P_AID of Beamformee */\n\t/* Clear MAC address of Beamformer */\n\t/* Clear Associated Bfmee Sel */\n\tif (bfer) {\n\t\tbfer->state = BEAMFORM_ENTRY_HW_STATE_DELETING;\n\n\t\trtw_write8(adapter, REG_SND_PTCL_CTRL_8822C, 0xD8);\n\n\t\tif (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_MU))\n\t\t\t_reset_beamformer_mu(adapter, bfer);\n\t\telse if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT))\n\t\t\t_reset_beamformer_su(adapter, bfer);\n\n\t\tbfer->state = BEAMFORM_ENTRY_HW_STATE_NONE;\n\t\tbfer->cap = BEAMFORMING_CAP_NONE;\n\t\tbfer->used = _FALSE;\n\t}\n\n\tif (bfee) {\n\t\tbfee->state = BEAMFORM_ENTRY_HW_STATE_DELETING;\n\n\t\tphydm_txbf_rfmode(GET_PDM_ODM(adapter), info->beamformee_su_cnt, info->beamformee_mu_cnt);\n\n\t\tif (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU))\n\t\t\t_reset_beamformee_mu(adapter, bfee);\n\t\telse if (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT))\n\t\t\t_reset_beamformee_su(adapter, bfee);\n\n\t\tbfee->state = BEAMFORM_ENTRY_HW_STATE_NONE;\n\t\tbfee->cap = BEAMFORMING_CAP_NONE;\n\t\tbfee->used = _FALSE;\n\t}\n\n\tRTW_INFO(\"-%s\\n\", __FUNCTION__);\n}\n\nvoid rtl8822c_phy_bf_set_gid_table(PADAPTER adapter,\n\t\tstruct beamformer_entry\t*bfer_info)\n{\n\tstruct beamformer_entry *bfer;\n\tstruct beamforming_info *info;\n\tu32 gid_valid[2] = {0};\n\tu32 user_position[4] = {0};\n\tint i;\n\n\t/* update bfer info */\n\tbfer = rtw_bf_bfer_get_entry_by_addr(adapter, bfer_info->mac_addr);\n\tif (!bfer) {\n\t\tRTW_INFO(\"%s: Cannot find BFer entry!!\\n\", __func__);\n\t\treturn;\n\t}\n\t_rtw_memcpy(bfer->gid_valid, bfer_info->gid_valid, 8);\n\t_rtw_memcpy(bfer->user_position, bfer_info->user_position, 16);\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tinfo->bSetBFHwConfigInProgess = _TRUE;\n\n\t/* For GID 0~31 */\n\tfor (i = 0; i < 4; i++)\n\t\tgid_valid[0] |= (bfer->gid_valid[i] << (i << 3));\n\n\tfor (i = 0; i < 8; i++) {\n\t\tif (i < 4)\n\t\t\tuser_position[0] |= (bfer->user_position[i] << (i << 3));\n\t\telse\n\t\t\tuser_position[1] |= (bfer->user_position[i] << ((i - 4) << 3));\n\t}\n\n\tRTW_INFO(\"%s: STA0: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\\n\",\n\t\t__func__, gid_valid[0], user_position[0], user_position[1]);\n\n\t/* For GID 32~64 */\n\tfor (i = 4; i < 8; i++)\n\t\tgid_valid[1] |= (bfer->gid_valid[i] << ((i - 4) << 3));\n\n\tfor (i = 8; i < 16; i++) {\n\t\tif (i < 12)\n\t\t\tuser_position[2] |= (bfer->user_position[i] << ((i - 8) << 3));\n\t\telse\n\t\t\tuser_position[3] |= (bfer->user_position[i] << ((i - 12) << 3));\n\t}\n\n\tRTW_INFO(\"%s: STA1: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\\n\",\n\t\t__func__, gid_valid[1], user_position[2], user_position[3]);\n\n\trtw_halmac_bf_cfg_mu_bfee(adapter_to_dvobj(adapter), gid_valid, user_position);\n\n\tinfo->bSetBFHwConfigInProgess = _FALSE;\n}\n\nvoid rtl8822c_phy_bf_sounding_status(PADAPTER adapter, u8 status)\n{\n\tstruct beamforming_info\t*info;\n\tstruct sounding_info *sounding;\n\tstruct beamformee_entry *bfee;\n\tenum _HW_CFG_SOUNDING_TYPE sounding_type;\n\tu16 val16;\n\tu32 val32;\n\tu8 is_sounding_success[6] = {0};\n\n\n\tRTW_INFO(\"+%s\\n\", __FUNCTION__);\n\n\tinfo = GET_BEAMFORM_INFO(adapter);\n\tsounding = &info->sounding_info;\n\n\tinfo->bSetBFHwConfigInProgess = _TRUE;\n\n\tif (sounding->state == SOUNDING_STATE_SU_SOUNDDOWN) {\n\t\t/* SU sounding done */\n\t\tRTW_INFO(\"%s: SUBFeeCurIdx=%d\\n\", __FUNCTION__, sounding->su_bfee_curidx);\n\n\t\tbfee = &info->bfee_entry[sounding->su_bfee_curidx];\n\t\tif (bfee->bSoundingTimeout) {\n\t\t\tRTW_INFO(\"%s: Return because SUBFeeCurIdx(%d) is sounding timeout!!!\\n\", __FUNCTION__, sounding->su_bfee_curidx);\n\t\t\tinfo->bSetBFHwConfigInProgess = _FALSE;\n\t\t\treturn;\n\t\t}\n\n\t\tRTW_INFO(\"%s: Config SU sound down HW settings\\n\", __FUNCTION__);\n\t\t/* Config SU sounding */\n\t\tif (_TRUE == status)\n\t\t\tsounding_type = HW_CFG_SOUNDING_TYPE_SOUNDDOWN;\n\t\telse\n\t\t\tsounding_type = HW_CFG_SOUNDING_TYPE_LEAVE;\n\t\t_config_sounding(adapter, bfee, _FALSE, sounding_type);\n\n\t\t/* <tynli_note> Why set here? */\n\t\t/* disable NDP packet use beamforming */\n\t\tval16 = rtw_read16(adapter, REG_TXBF_CTRL_8822C);\n\t\tval16 |= BIT_DIS_NDP_BFEN_8822C;\n\t\trtw_write16(adapter, REG_TXBF_CTRL_8822C, val16);\n\t} else if (sounding->state == SOUNDING_STATE_MU_SOUNDDOWN) {\n\t\t/* MU sounding done */\n\t\tRTW_INFO(\"%s: Config MU sound down HW settings\\n\", __FUNCTION__);\n\n\t\tval32 = rtw_read32(adapter, REG_WMAC_ASSOCIATED_MU_BFMEE2_8822C);\n\t\tis_sounding_success[0] = (val32 & BIT_STATUS_BFEE2_8822C) ? 1:0;\n\t\tis_sounding_success[1] = ((val32 >> 16) & BIT_STATUS_BFEE3_8822C) ? 1:0;\n\t\tval32 = rtw_read32(adapter, REG_WMAC_ASSOCIATED_MU_BFMEE4_8822C);\n\t\tis_sounding_success[2] = (val32 & BIT_STATUS_BFEE4_8822C) ? 1:0;\n\t\tis_sounding_success[3] = ((val32 >> 16) & BIT_BIT_STATUS_BFEE5_8822C) ? 1:0;\n\t\tval32 = rtw_read32(adapter, REG_WMAC_ASSOCIATED_MU_BFMEE6_8822C);\n\t\tis_sounding_success[4] = (val32 & BIT_STATUS_BFEE6_8822C) ? 1:0;\n\t\tis_sounding_success[5] = ((val32 >> 16) & BIT_STATUS_BFEE7_8822C) ? 1:0;\n\n\t\tRTW_INFO(\"%s: is_sounding_success STA1:%d, STA2:%d, STA3:%d, STA4:%d, STA5:%d, STA6:%d\\n\",\n\t\t\t __FUNCTION__, is_sounding_success[0], is_sounding_success[1] , is_sounding_success[2],\n\t\t\t is_sounding_success[3], is_sounding_success[4], is_sounding_success[5]);\n\n\t\t/* Config MU sounding */\n\t\t_config_sounding(adapter, NULL, _TRUE, HW_CFG_SOUNDING_TYPE_SOUNDDOWN);\n\t} else {\n\t\tRTW_INFO(\"%s: Invalid sounding state(%d). Do nothing!\\n\", __FUNCTION__, sounding->state);\n\t}\n\n\tinfo->bSetBFHwConfigInProgess = _FALSE;\n\n\tRTW_INFO(\"-%s\\n\", __FUNCTION__);\n}\n#endif /* CONFIG_BEAMFORMING */\n\n"
  },
  {
    "path": "halmac.mk",
    "content": "# All needed files would be added to _HAL_INTFS_FILES, and it would include\n# hal/hal_halmac.c and all related files in directory hal/halmac/.\n# Before include this makefile, be sure interface (CONFIG_*_HCI) and IC\n# (CONFIG_RTL*) setting are all ready!\n\n# Base directory\npath_hm := hal/halmac\n# Level 1 directory\npath_hm_d1 := $(path_hm)/halmac_88xx\n\nifeq ($(CONFIG_PCI_HCI), y)\npci := y\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\nsdio := y\nendif\nifeq ($(CONFIG_USB_HCI), y)\nusb := y\nendif\n\nifeq ($(CONFIG_RTL8822B), y)\nic := 8822b\nendif\n\nifeq ($(CONFIG_RTL8822C), y)\nic := 8822c\nendif\n\nifeq ($(CONFIG_RTL8821C), y)\nic := 8821c\nendif\n\nifeq ($(CONFIG_RTL8814B), y)\nv1 := \"_v1\"\nic := 8814b\nendif\n\nhalmac-y +=\t\t$(path_hm)/halmac_api.o\n\n# Modify level 1 directory if needed\npath_hm_d1 := $(path_hm_d1)$(v1)\nhalmac-y +=\t\t$(path_hm_d1)/halmac_bb_rf_88xx$(v1).o \\\n\t\t\t$(path_hm_d1)/halmac_cfg_wmac_88xx$(v1).o \\\n\t\t\t$(path_hm_d1)/halmac_common_88xx$(v1).o \\\n\t\t\t$(path_hm_d1)/halmac_efuse_88xx$(v1).o \\\n\t\t\t$(path_hm_d1)/halmac_flash_88xx$(v1).o \\\n\t\t\t$(path_hm_d1)/halmac_fw_88xx$(v1).o \\\n\t\t\t$(path_hm_d1)/halmac_gpio_88xx$(v1).o \\\n\t\t\t$(path_hm_d1)/halmac_init_88xx$(v1).o \\\n\t\t\t$(path_hm_d1)/halmac_mimo_88xx$(v1).o\nhalmac-$(pci) += \t$(path_hm_d1)/halmac_pcie_88xx$(v1).o\nhalmac-$(sdio) +=\t$(path_hm_d1)/halmac_sdio_88xx$(v1).o\nhalmac-$(usb) += \t$(path_hm_d1)/halmac_usb_88xx$(v1).o\n\n# Level 2 directory\npath_hm_d2 := $(path_hm_d1)/halmac_$(ic)\nhalmac-y +=\t\t$(path_hm_d2)/halmac_cfg_wmac_$(ic).o \\\n\t\t\t$(path_hm_d2)/halmac_common_$(ic).o \\\n\t\t\t$(path_hm_d2)/halmac_gpio_$(ic).o \\\n\t\t\t$(path_hm_d2)/halmac_init_$(ic).o \\\n\t\t\t$(path_hm_d2)/halmac_phy_$(ic).o \\\n\t\t\t$(path_hm_d2)/halmac_pwr_seq_$(ic).o\nhalmac-$(pci) += \t$(path_hm_d2)/halmac_pcie_$(ic).o\nhalmac-$(sdio) +=\t$(path_hm_d2)/halmac_sdio_$(ic).o\nhalmac-$(usb) += \t$(path_hm_d2)/halmac_usb_$(ic).o\n\n_HAL_INTFS_FILES +=\thal/hal_halmac.o\n_HAL_INTFS_FILES +=\t$(halmac-y)\n"
  },
  {
    "path": "ifcfg-wlan0",
    "content": "#DHCP client\r\nDEVICE=wlan0\r\nBOOTPROTO=dhcp\r\nONBOOT=yes"
  },
  {
    "path": "include/Hal8188EPhyCfg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8188EPHYCFG_H__\n#define __INC_HAL8188EPHYCFG_H__\n\n\n/*--------------------------Define Parameters-------------------------------*/\n#define LOOP_LIMIT\t\t\t\t5\n#define MAX_STALL_TIME\t\t\t50\t\t/* us */\n#define AntennaDiversityValue\t\t0x80\t/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */\n#define MAX_TXPWR_IDX_NMODE_92S\t63\n#define Reset_Cnt_Limit\t\t\t3\n\n#ifdef CONFIG_PCI_HCI\n\t#define MAX_AGGR_NUM\t0x0B\n#else\n\t#define MAX_AGGR_NUM\t0x07\n#endif /* CONFIG_PCI_HCI */\n\n\n/*--------------------------Define Parameters-------------------------------*/\n\n\n/*------------------------------Define structure----------------------------*/\n\n#define\tMAX_TX_COUNT_8188E\t\t\t1\n\n/* BB/RF related */\n\n\n/*------------------------------Define structure----------------------------*/\n\n\n/*------------------------Export global variable----------------------------*/\n/*------------------------Export global variable----------------------------*/\n\n\n/*------------------------Export Marco Definition---------------------------*/\n/*------------------------Export Marco Definition---------------------------*/\n\n\n/*--------------------------Exported Function prototype---------------------*/\n/*\n * BB and RF register read/write\n *   */\nu32\tPHY_QueryBBReg8188E(PADAPTER\tAdapter,\n\t\t\t\tu32\t\tRegAddr,\n\t\t\t\tu32\t\tBitMask);\nvoid\tPHY_SetBBReg8188E(PADAPTER\tAdapter,\n\t\t\t\tu32\t\tRegAddr,\n\t\t\t\tu32\t\tBitMask,\n\t\t\t\tu32\t\tData);\nu32\tPHY_QueryRFReg8188E(PADAPTER\tAdapter,\n\t\t\t\tenum rf_path\t\teRFPath,\n\t\t\t\tu32\t\t\t\tRegAddr,\n\t\t\t\tu32\t\t\t\tBitMask);\nvoid\tPHY_SetRFReg8188E(PADAPTER\t\tAdapter,\n\t\t\t\tenum rf_path\t\teRFPath,\n\t\t\t\tu32\t\t\t\tRegAddr,\n\t\t\t\tu32\t\t\t\tBitMask,\n\t\t\t\tu32\t\t\t\tData);\n\n/*\n * Initialization related function\n */\n/* MAC/BB/RF HAL config */\nint\tPHY_MACConfig8188E(PADAPTER\tAdapter);\nint\tPHY_BBConfig8188E(PADAPTER\tAdapter);\nint\tPHY_RFConfig8188E(PADAPTER\tAdapter);\n\n/* RF config */\nint\trtl8188e_PHY_ConfigRFWithParaFile( PADAPTER Adapter, u8 *pFileName, enum rf_path eRFPath);\n\n/*\n * RF Power setting\n */\n/* extern\tBOOLEAN\tPHY_SetRFPowerState(PADAPTER\t\t\tAdapter,\n *\t\t\t\t\t\t\t\t\t\tRT_RF_POWER_STATE\teRFPowerState); */\n\n/*\n * BB TX Power R/W\n *   */\nvoid\tPHY_SetTxPowerLevel8188E(PADAPTER\t\tAdapter,\n\t\t\t\t\tu8\t\t\tchannel);\n\nvoid\nPHY_SetTxPowerIndex_8188E(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu32\t\t\t\t\tPowerIndex,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate\n);\n\nu8\nPHY_GetTxPowerIndex_8188E(\n\t\tPADAPTER\t\tpAdapter,\n\t\tenum rf_path\t\tRFPath,\n\t\tu8\t\t\t\tRate,\n\t\tu8\t\t\t\tBandWidth,\n\t\tu8\t\t\t\tChannel,\n\tstruct txpwr_idx_comp *tic\n);\n\n/*\n * Switch bandwidth for 8192S\n */\n/* extern\tvoid\tPHY_SetBWModeCallback8192C(PRT_TIMER\t\tpTimer\t); */\nvoid\tPHY_SetBWMode8188E(PADAPTER\t\t\tpAdapter,\n\t\t\t\tenum channel_width\tChnlWidth,\n\t\t\t\tunsigned char\tOffset);\n\n/*\n * Set FW CMD IO for 8192S.\n */\n/* extern\tBOOLEAN HalSetIO8192C(PADAPTER\t\t\tAdapter,\n *\t\t\t\t\t\t\t\tIO_TYPE\t\t\t\tIOType); */\n\n/*\n * Set A2 entry to fw for 8192S\n *   */\nextern\tvoid FillA2Entry8192C(PADAPTER\t\t\tAdapter,\n\t\t\t\tu8\t\t\t\tindex,\n\t\t\t\tu8\t\t\t\t*val);\n\n\n/*\n * channel switch related funciton\n */\n/* extern\tvoid\tPHY_SwChnlCallback8192C(PRT_TIMER\t\tpTimer\t); */\nvoid\tPHY_SwChnl8188E(PADAPTER\t\tpAdapter,\n\t\t\t\tu8\t\t\tchannel);\n\nvoid\nPHY_SetSwChnlBWMode8188E(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu8\t\t\t\t\tchannel,\n\t\tenum channel_width\tBandwidth,\n\t\tu8\t\t\t\t\tOffset40,\n\t\tu8\t\t\t\t\tOffset80\n);\n\nvoid\nPHY_SetRFEReg_8188E(\n\t\tPADAPTER\t\tAdapter\n);\n/*\n * BB/MAC/RF other monitor API\n *   */\nvoid phy_set_rf_path_switch_8188e(struct dm_struct\t*phydm, bool\t\tbMain);\n\nextern\tvoid\nPHY_SwitchEphyParameter(\n\t\tPADAPTER\t\t\tAdapter\n);\n\nextern\tvoid\nPHY_EnableHostClkReq(\n\t\tPADAPTER\t\t\tAdapter\n);\n\nBOOLEAN\nSetAntennaConfig92C(\n\t\tPADAPTER\tAdapter,\n\t\tu8\t\tDefaultAnt\n);\n\n/*--------------------------Exported Function prototype---------------------*/\n\n/*\n * Initialization related function\n *\n * MAC/BB/RF HAL config */\n/* extern s32 PHY_MACConfig8723(PADAPTER padapter);\n * s32 PHY_BBConfig8723(PADAPTER padapter);\n * s32 PHY_RFConfig8723(PADAPTER padapter); */\n\n\n\n/* ******************************************************************\n * Note: If SIC_ENABLE under PCIE, because of the slow operation\n *\tyou should\n * \t2) \"#define RTL8723_FPGA_VERIFICATION\t1\"\t\t\t\tin Precomp.h.WlanE.Windows\n * \t3) \"#define RTL8190_Download_Firmware_From_Header\t0\"\tin Precomp.h.WlanE.Windows if needed.\n *   */\n#if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1)\n\t#define\tSIC_ENABLE\t\t\t\t1\n\t#define\tSIC_HW_SUPPORT\t\t1\n#else\n\t#define\tSIC_ENABLE\t\t\t\t0\n\t#define\tSIC_HW_SUPPORT\t\t0\n#endif\n/* ****************************************************************** */\n\n\n#define\tSIC_MAX_POLL_CNT\t\t5\n\n#if (SIC_HW_SUPPORT == 1)\n\t#define\tSIC_CMD_READY\t\t\t0\n\t#define\tSIC_CMD_PREWRITE\t\t0x1\n\t#if (RTL8188E_SUPPORT == 1)\n\t\t#define\tSIC_CMD_WRITE\t\t\t0x40\n\t\t#define\tSIC_CMD_PREREAD\t\t0x2\n\t\t#define\tSIC_CMD_READ\t\t\t0x80\n\t\t#define\tSIC_CMD_INIT\t\t\t0xf0\n\t\t#define\tSIC_INIT_VAL\t\t\t0xff\n\n\t\t#define\tSIC_INIT_REG\t\t\t0x1b7\n\t\t#define\tSIC_CMD_REG\t\t\t0x1EB\t\t/* 1byte */\n\t\t#define\tSIC_ADDR_REG\t\t\t0x1E8\t\t/* 1b4~1b5, 2 bytes */\n\t\t#define\tSIC_DATA_REG\t\t\t0x1EC\t\t/* 1b0~1b3 */\n\t#else\n\t\t#define\tSIC_CMD_WRITE\t\t\t0x11\n\t\t#define\tSIC_CMD_PREREAD\t\t0x2\n\t\t#define\tSIC_CMD_READ\t\t\t0x12\n\t\t#define\tSIC_CMD_INIT\t\t\t0x1f\n\t\t#define\tSIC_INIT_VAL\t\t\t0xff\n\n\t\t#define\tSIC_INIT_REG\t\t\t0x1b7\n\t\t#define\tSIC_CMD_REG\t\t\t0x1b6\t\t/* 1byte */\n\t\t#define\tSIC_ADDR_REG\t\t\t0x1b4\t\t/* 1b4~1b5, 2 bytes */\n\t\t#define\tSIC_DATA_REG\t\t\t0x1b0\t\t/* 1b0~1b3 */\n\t#endif\n#else\n\t#define\tSIC_CMD_READY\t\t\t0\n\t#define\tSIC_CMD_WRITE\t\t\t1\n\t#define\tSIC_CMD_READ\t\t\t2\n\n\t#if (RTL8188E_SUPPORT == 1)\n\t\t#define\tSIC_CMD_REG\t\t\t0x1EB\t\t/* 1byte */\n\t\t#define\tSIC_ADDR_REG\t\t\t0x1E8\t\t/* 1b9~1ba, 2 bytes */\n\t\t#define\tSIC_DATA_REG\t\t\t0x1EC\t\t/* 1bc~1bf */\n\t#else\n\t\t#define\tSIC_CMD_REG\t\t\t0x1b8\t\t/* 1byte */\n\t\t#define\tSIC_ADDR_REG\t\t\t0x1b9\t\t/* 1b9~1ba, 2 bytes */\n\t\t#define\tSIC_DATA_REG\t\t\t0x1bc\t\t/* 1bc~1bf */\n\t#endif\n#endif\n\n#if (SIC_ENABLE == 1)\n\tvoid SIC_Init( PADAPTER Adapter);\n#endif\n\n\n#endif /* __INC_HAL8192CPHYCFG_H */\n"
  },
  {
    "path": "include/Hal8188EPhyReg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8188EPHYREG_H__\n#define __INC_HAL8188EPHYREG_H__\n/*--------------------------Define Parameters-------------------------------*/\n/*\n * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00\n * 3. RF register 0x00-2E\n * 4. Bit Mask for BB/RF register\n * 5. Other defintion for BB/RF R/W\n *   */\n\n\n/*\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 1. Page1(0x100)\n *   */\n#define\t\trPMAC_Reset\t\t\t\t\t0x100\n#define\t\trPMAC_TxStart\t\t\t\t0x104\n#define\t\trPMAC_TxLegacySIG\t\t\t0x108\n#define\t\trPMAC_TxHTSIG1\t\t\t\t0x10c\n#define\t\trPMAC_TxHTSIG2\t\t\t\t0x110\n#define\t\trPMAC_PHYDebug\t\t\t\t0x114\n#define\t\trPMAC_TxPacketNum\t\t\t0x118\n#define\t\trPMAC_TxIdle\t\t\t\t\t0x11c\n#define\t\trPMAC_TxMACHeader0\t\t\t0x120\n#define\t\trPMAC_TxMACHeader1\t\t\t0x124\n#define\t\trPMAC_TxMACHeader2\t\t\t0x128\n#define\t\trPMAC_TxMACHeader3\t\t\t0x12c\n#define\t\trPMAC_TxMACHeader4\t\t\t0x130\n#define\t\trPMAC_TxMACHeader5\t\t\t0x134\n#define\t\trPMAC_TxDataType\t\t\t\t0x138\n#define\t\trPMAC_TxRandomSeed\t\t\t0x13c\n#define\t\trPMAC_CCKPLCPPreamble\t\t0x140\n#define\t\trPMAC_CCKPLCPHeader\t\t\t0x144\n#define\t\trPMAC_CCKCRC16\t\t\t\t0x148\n#define\t\trPMAC_OFDMRxCRC32OK\t\t0x170\n#define\t\trPMAC_OFDMRxCRC32Er\t\t0x174\n#define\t\trPMAC_OFDMRxParityEr\t\t\t0x178\n#define\t\trPMAC_OFDMRxCRC8Er\t\t\t0x17c\n#define\t\trPMAC_CCKCRxRC16Er\t\t\t0x180\n#define\t\trPMAC_CCKCRxRC32Er\t\t\t0x184\n#define\t\trPMAC_CCKCRxRC32OK\t\t\t0x188\n#define\t\trPMAC_TxStatus\t\t\t\t0x18c\n\n/*\n * 2. Page2(0x200)\n *\n * The following two definition are only used for USB interface. */\n#define\t\tRF_BB_CMD_ADDR\t\t\t\t0x02c0\t/* RF/BB read/write command address. */\n#define\t\tRF_BB_CMD_DATA\t\t\t\t0x02c4\t/* RF/BB read/write command data. */\n\n/*\n * 3. Page8(0x800)\n *   */\n#define\t\trFPGA0_RFMOD\t\t\t\t0x800\t/* RF mode & CCK TxSC */ /* RF BW Setting?? */\n\n#define\t\trFPGA0_TxInfo\t\t\t\t\t0x804\t/* Status report?? */\n#define\t\trFPGA0_PSDFunction\t\t\t0x808\n\n#define\t\trFPGA0_TxGainStage\t\t\t0x80c\t/* Set TX PWR init gain? */\n\n#define\t\trFPGA0_RFTiming1\t\t\t\t0x810\t/* Useless now */\n#define\t\trFPGA0_RFTiming2\t\t\t\t0x814\n\n#define\t\trFPGA0_XA_HSSIParameter1\t\t0x820\t/* RF 3 wire register */\n#define\t\trFPGA0_XA_HSSIParameter2\t\t0x824\n#define\t\trFPGA0_XB_HSSIParameter1\t\t0x828\n#define\t\trFPGA0_XB_HSSIParameter2\t\t0x82c\n\n#define\t\trFPGA0_XA_LSSIParameter\t\t0x840\n#define\t\trFPGA0_XB_LSSIParameter\t\t0x844\n\n#define\t\trFPGA0_RFWakeUpParameter\t0x850\t/* Useless now */\n#define\t\trFPGA0_RFSleepUpParameter\t\t0x854\n\n#define\t\trFPGA0_XAB_SwitchControl\t\t0x858\t/* RF Channel switch */\n#define\t\trFPGA0_XCD_SwitchControl\t\t0x85c\n\n#define\t\trFPGA0_XA_RFInterfaceOE\t\t0x860\t/* RF Channel switch */\n#define\t\trFPGA0_XB_RFInterfaceOE\t\t0x864\n#define\t\trFPGA0_XAB_RFInterfaceSW\t\t0x870\t/* RF Interface Software Control */\n#define\t\trFPGA0_XCD_RFInterfaceSW\t\t0x874\n\n#define\t\trFPGA0_XAB_RFParameter\t\t0x878\t/* RF Parameter */\n#define\t\trFPGA0_XCD_RFParameter\t\t0x87c\n\n#define\t\trFPGA0_AnalogParameter1\t\t0x880\t/* Crystal cap setting RF-R/W protection for parameter4?? */\n#define\t\trFPGA0_AnalogParameter2\t\t0x884\n#define\t\trFPGA0_AnalogParameter3\t\t0x888\n#define\t\trFPGA0_AdDaClockEn\t\t\t0x888\t/* enable ad/da clock1 for dual-phy */\n#define\t\trFPGA0_AnalogParameter4\t\t0x88c\n\n#define\t\trFPGA0_XA_LSSIReadBack\t\t0x8a0\t/* Tranceiver LSSI Readback */\n#define\t\trFPGA0_XB_LSSIReadBack\t\t0x8a4\n#define\t\trFPGA0_XC_LSSIReadBack\t\t0x8a8\n#define\t\trFPGA0_XD_LSSIReadBack\t\t0x8ac\n\n#define\t\trFPGA0_PSDReport\t\t\t\t0x8b4\t/* Useless now */\n#define\t\tTransceiverA_HSPI_Readback\t\t0x8b8\t/* Transceiver A HSPI Readback */\n#define\t\tTransceiverB_HSPI_Readback\t\t0x8bc\t/* Transceiver B HSPI Readback */\n#define\t\trFPGA0_XAB_RFInterfaceRB\t\t0x8e0\t/* Useless now */ /* RF Interface Readback Value */\n#define\t\trFPGA0_XCD_RFInterfaceRB\t\t0x8e4\t/* Useless now */\n\n/*\n * 4. Page9(0x900)\n *   */\n#define\t\trFPGA1_RFMOD\t\t\t\t0x900\t/* RF mode & OFDM TxSC */ /* RF BW Setting?? */\n\n#define\t\trFPGA1_TxBlock\t\t\t\t0x904\t/* Useless now */\n#define\t\trFPGA1_DebugSelect\t\t\t0x908\t/* Useless now */\n#define\t\trFPGA1_TxInfo\t\t\t\t\t0x90c\t/* Useless now */ /* Status report?? */\n\n/*\n * 5. PageA(0xA00)\n *\n * Set Control channel to upper or lower. These settings are required only for 40MHz */\n#define\t\trCCK0_System\t\t\t\t\t0xa00\n\n#define\t\trCCK0_AFESetting\t\t\t\t0xa04\t/* Disable init gain now */ /* Select RX path by RSSI */\n#define\t\trCCK0_CCA\t\t\t\t\t0xa08\t/* Disable init gain now */ /* Init gain */\n\n#define\t\trCCK0_RxAGC1\t\t\t\t0xa0c\t/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */\n#define\t\trCCK0_RxAGC2\t\t\t\t0xa10\t/* AGC & DAGC */\n\n#define\t\trCCK0_RxHP\t\t\t\t\t0xa14\n\n#define\t\trCCK0_DSPParameter1\t\t\t0xa18\t/* Timing recovery & Channel estimation threshold */\n#define\t\trCCK0_DSPParameter2\t\t\t0xa1c\t/* SQ threshold */\n\n#define\t\trCCK0_TxFilter1\t\t\t\t0xa20\n#define\t\trCCK0_TxFilter2\t\t\t\t0xa24\n#define\t\trCCK0_DebugPort\t\t\t\t0xa28\t/* debug port and Tx filter3 */\n#define\t\trCCK0_FalseAlarmReport\t\t0xa2c\t/* 0xa2d\tuseless now 0xa30-a4f channel report */\n#define\t\trCCK0_TRSSIReport\t\t\t0xa50\n#define\t\trCCK0_RxReport            \t\t\t0xa54  /* 0xa57 */\n#define\t\trCCK0_FACounterLower      \t\t0xa5c  /* 0xa5b */\n#define\t\trCCK0_FACounterUpper      \t\t0xa58  /* 0xa5c */\n\n/*\n * PageB(0xB00)\n *   */\n#define\t\trPdp_AntA\t\t\t\t\t0xb00\n#define\t\trPdp_AntA_4\t\t\t\t0xb04\n#define\t\trConfig_Pmpd_AntA\t\t\t0xb28\n#define\t\trConfig_ram64x16\t\t\t\t0xb2c\n#define\t\trConfig_AntA\t\t\t\t\t0xb68\n#define\t\trConfig_AntB\t\t\t\t\t0xb6c\n#define\t\trPdp_AntB\t\t\t\t\t0xb70\n#define\t\trPdp_AntB_4\t\t\t\t\t0xb74\n#define\t\trConfig_Pmpd_AntB\t\t\t0xb98\n#define\t\trAPK\t\t\t\t\t\t\t0xbd8\n\n\n\n/*\n * 6. PageC(0xC00)\n *   */\n#define\t\trOFDM0_LSTF\t\t\t\t\t0xc00\n\n#define\t\trOFDM0_TRxPathEnable\t\t\t0xc04\n#define\t\trOFDM0_TRMuxPar\t\t\t\t0xc08\n#define\t\trOFDM0_TRSWIsolation\t\t\t0xc0c\n\n#define\t\trOFDM0_XARxAFE\t\t\t\t0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */\n#define\t\trOFDM0_XARxIQImbalance    \t\t0xc14  /* RxIQ imblance matrix */\n#define\t\trOFDM0_XBRxAFE\t\t\t0xc18\n#define\t\trOFDM0_XBRxIQImbalance\t\t0xc1c\n#define\t\trOFDM0_XCRxAFE\t\t\t0xc20\n#define\t\trOFDM0_XCRxIQImbalance\t\t0xc24\n#define\t\trOFDM0_XDRxAFE\t\t\t0xc28\n#define\t\trOFDM0_XDRxIQImbalance\t\t0xc2c\n\n#define\t\trOFDM0_RxDetector1\t\t\t0xc30  /* PD, BW & SBD\t */ /* DM tune init gain */\n#define\t\trOFDM0_RxDetector2\t\t\t0xc34  /* SBD & Fame Sync. */\n#define\t\trOFDM0_RxDetector3\t\t\t0xc38  /* Frame Sync. */\n#define\t\trOFDM0_RxDetector4\t\t\t0xc3c  /* PD, SBD, Frame Sync & Short-GI */\n\n#define\t\trOFDM0_RxDSP\t\t\t\t0xc40  /* Rx Sync Path */\n#define\t\trOFDM0_CFOandDAGC\t\t\t0xc44  /* CFO & DAGC */\n#define\t\trOFDM0_CCADropThreshold\t\t0xc48 /* CCA Drop threshold */\n#define\t\trOFDM0_ECCAThreshold\t\t\t0xc4c /* energy CCA */\n\n#define\t\trOFDM0_XAAGCCore1\t\t\t0xc50\t/* DIG */\n#define\t\trOFDM0_XAAGCCore2\t\t\t0xc54\n#define\t\trOFDM0_XBAGCCore1\t\t\t0xc58\n#define\t\trOFDM0_XBAGCCore2\t\t\t0xc5c\n#define\t\trOFDM0_XCAGCCore1\t\t\t0xc60\n#define\t\trOFDM0_XCAGCCore2\t\t\t0xc64\n#define\t\trOFDM0_XDAGCCore1\t\t\t0xc68\n#define\t\trOFDM0_XDAGCCore2\t\t\t0xc6c\n\n#define\t\trOFDM0_AGCParameter1\t\t0xc70\n#define\t\trOFDM0_AGCParameter2\t\t0xc74\n#define\t\trOFDM0_AGCRSSITable\t\t\t0xc78\n#define\t\trOFDM0_HTSTFAGC\t\t\t\t0xc7c\n\n#define\t\trOFDM0_XATxIQImbalance\t\t0xc80\t/* TX PWR TRACK and DIG */\n#define\t\trOFDM0_XATxAFE\t\t\t\t0xc84\n#define\t\trOFDM0_XBTxIQImbalance\t\t0xc88\n#define\t\trOFDM0_XBTxAFE\t\t\t\t0xc8c\n#define\t\trOFDM0_XCTxIQImbalance\t\t0xc90\n#define\t\trOFDM0_XCTxAFE\t\t\t0xc94\n#define\t\trOFDM0_XDTxIQImbalance\t\t0xc98\n#define\t\trOFDM0_XDTxAFE\t\t\t\t0xc9c\n\n#define\t\trOFDM0_RxIQExtAnta\t\t\t0xca0\n#define\t\trOFDM0_TxCoeff1\t\t\t\t0xca4\n#define\t\trOFDM0_TxCoeff2\t\t\t\t0xca8\n#define\t\trOFDM0_TxCoeff3\t\t\t\t0xcac\n#define\t\trOFDM0_TxCoeff4\t\t\t\t0xcb0\n#define\t\trOFDM0_TxCoeff5\t\t\t\t0xcb4\n#define\t\trOFDM0_TxCoeff6\t\t\t\t0xcb8\n#define\t\trOFDM0_RxHPParameter\t\t0xce0\n#define\t\trOFDM0_TxPseudoNoiseWgt\t\t0xce4\n#define\t\trOFDM0_FrameSync\t\t\t0xcf0\n#define\t\trOFDM0_DFSReport\t\t\t0xcf4\n\n\n/*\n * 7. PageD(0xD00)\n *   */\n#define\t\trOFDM1_LSTF\t\t\t\t\t0xd00\n#define\t\trOFDM1_TRxPathEnable\t\t\t0xd04\n\n#define\t\trOFDM1_CFO\t\t\t\t\t0xd08\t/* No setting now */\n#define\t\trOFDM1_CSI1\t\t\t\t\t0xd10\n#define\t\trOFDM1_SBD\t\t\t\t\t0xd14\n#define\t\trOFDM1_CSI2\t\t\t\t\t0xd18\n#define\t\trOFDM1_CFOTracking\t\t\t0xd2c\n#define\t\trOFDM1_TRxMesaure1\t\t\t0xd34\n#define\t\trOFDM1_IntfDet\t\t\t\t0xd3c\n#define\t\trOFDM1_csi_fix_mask1\t\t\t\t0xd40\n#define\t\trOFDM1_csi_fix_mask2\t\t\t\t0xd44\n#define\t\trOFDM1_PseudoNoiseStateAB\t0xd50\n#define\t\trOFDM1_PseudoNoiseStateCD\t0xd54\n#define\t\trOFDM1_RxPseudoNoiseWgt\t\t0xd58\n\n#define\t\trOFDM_PHYCounter1\t\t\t0xda0  /* cca, parity fail */\n#define\t\trOFDM_PHYCounter2\t\t\t0xda4  /* rate illegal, crc8 fail */\n#define\t\trOFDM_PHYCounter3\t\t\t0xda8  /* MCS not support */\n\n#define\t\trOFDM_ShortCFOAB\t\t\t0xdac\t/* No setting now */\n#define\t\trOFDM_ShortCFOCD\t\t\t0xdb0\n#define\t\trOFDM_LongCFOAB\t\t\t\t0xdb4\n#define\t\trOFDM_LongCFOCD\t\t\t\t0xdb8\n#define\t\trOFDM_TailCFOAB\t\t\t\t0xdbc\n#define\t\trOFDM_TailCFOCD\t\t\t\t0xdc0\n#define\t\trOFDM_PWMeasure1\t\t0xdc4\n#define\t\trOFDM_PWMeasure2\t\t0xdc8\n#define\t\trOFDM_BWReport\t\t\t\t0xdcc\n#define\t\trOFDM_AGCReport\t\t\t\t0xdd0\n#define\t\trOFDM_RxSNR\t\t\t\t0xdd4\n#define\t\trOFDM_RxEVMCSI\t\t\t\t0xdd8\n#define\t\trOFDM_SIGReport\t\t\t\t0xddc\n\n\n/*\n * 8. PageE(0xE00)\n *   */\n#define\t\trTxAGC_A_Rate18_06\t\t\t0xe00\n#define\t\trTxAGC_A_Rate54_24\t\t\t0xe04\n#define\t\trTxAGC_A_CCK1_Mcs32\t\t\t0xe08\n#define\t\trTxAGC_A_Mcs03_Mcs00\t\t0xe10\n#define\t\trTxAGC_A_Mcs07_Mcs04\t\t0xe14\n#define\t\trTxAGC_A_Mcs11_Mcs08\t\t0xe18\n#define\t\trTxAGC_A_Mcs15_Mcs12\t\t0xe1c\n\n#define\t\trTxAGC_B_Rate18_06\t\t\t0x830\n#define\t\trTxAGC_B_Rate54_24\t\t\t0x834\n#define\t\trTxAGC_B_CCK1_55_Mcs32\t\t0x838\n#define\t\trTxAGC_B_Mcs03_Mcs00\t\t0x83c\n#define\t\trTxAGC_B_Mcs07_Mcs04\t\t0x848\n#define\t\trTxAGC_B_Mcs11_Mcs08\t\t0x84c\n#define\t\trTxAGC_B_Mcs15_Mcs12\t\t0x868\n#define\t\trTxAGC_B_CCK11_A_CCK2_11\t\t0x86c\n\n#define\t\trFPGA0_IQK\t\t\t\t\t0xe28\n#define\t\trTx_IQK_Tone_A\t\t\t\t0xe30\n#define\t\trRx_IQK_Tone_A\t\t\t\t0xe34\n#define\t\trTx_IQK_PI_A\t\t\t\t\t0xe38\n#define\t\trRx_IQK_PI_A\t\t\t\t\t0xe3c\n\n#define\t\trTx_IQK\t\t\t\t\t\t0xe40\n#define\t\trRx_IQK\t\t\t\t\t\t0xe44\n#define\t\trIQK_AGC_Pts\t\t\t\t\t0xe48\n#define\t\trIQK_AGC_Rsp\t\t\t\t\t0xe4c\n#define\t\trTx_IQK_Tone_B\t\t\t\t0xe50\n#define\t\trRx_IQK_Tone_B\t\t\t\t0xe54\n#define\t\trTx_IQK_PI_B\t\t\t\t\t0xe58\n#define\t\trRx_IQK_PI_B\t\t\t\t\t0xe5c\n#define\t\trIQK_AGC_Cont\t\t\t\t0xe60\n\n#define\t\trBlue_Tooth\t\t\t\t\t0xe6c\n#define\t\trRx_Wait_CCA\t\t\t\t\t0xe70\n#define\t\trTx_CCK_RFON\t\t\t\t\t0xe74\n#define\t\trTx_CCK_BBON\t\t\t\t0xe78\n#define\t\trTx_OFDM_RFON\t\t\t\t0xe7c\n#define\t\trTx_OFDM_BBON\t\t\t\t0xe80\n#define\t\trTx_To_Rx\t\t\t\t\t0xe84\n#define\t\trTx_To_Tx\t\t\t\t\t0xe88\n#define\t\trRx_CCK\t\t\t\t\t\t0xe8c\n\n#define\t\trTx_Power_Before_IQK_A\t\t0xe94\n#define\t\trTx_Power_After_IQK_A\t\t\t0xe9c\n\n#define\t\trRx_Power_Before_IQK_A\t\t0xea0\n#define\t\trRx_Power_Before_IQK_A_2\t\t0xea4\n#define\t\trRx_Power_After_IQK_A\t\t\t0xea8\n#define\t\trRx_Power_After_IQK_A_2\t\t0xeac\n\n#define\t\trTx_Power_Before_IQK_B\t\t0xeb4\n#define\t\trTx_Power_After_IQK_B\t\t\t0xebc\n\n#define\t\trRx_Power_Before_IQK_B\t\t0xec0\n#define\t\trRx_Power_Before_IQK_B_2\t\t0xec4\n#define\t\trRx_Power_After_IQK_B\t\t\t0xec8\n#define\t\trRx_Power_After_IQK_B_2\t\t0xecc\n\n#define\t\trRx_OFDM\t\t\t\t\t0xed0\n#define\t\trRx_Wait_RIFS\t\t\t\t0xed4\n#define\t\trRx_TO_Rx\t\t\t\t\t0xed8\n#define\t\trStandby\t\t\t\t\t\t0xedc\n#define\t\trSleep\t\t\t\t\t\t0xee0\n#define\t\trPMPD_ANAEN\t\t\t\t0xeec\n\n/*\n * 7. RF Register 0x00-0x2E (RF 8256)\n * RF-0222D 0x00-3F\n *\n * Zebra1 */\n#define\t\trZebra1_HSSIEnable\t\t\t\t0x0\t/* Useless now */\n#define\t\trZebra1_TRxEnable1\t\t\t0x1\n#define\t\trZebra1_TRxEnable2\t\t\t0x2\n#define\t\trZebra1_AGC\t\t\t\t\t0x4\n#define\t\trZebra1_ChargePump\t\t\t0x5\n#define\t\trZebra1_Channel\t\t\t\t0x7\t/* RF channel switch */\n\n/* #endif */\n#define\t\trZebra1_TxGain\t\t\t\t0x8\t/* Useless now */\n#define\t\trZebra1_TxLPF\t\t\t\t\t0x9\n#define\t\trZebra1_RxLPF\t\t\t\t\t0xb\n#define\t\trZebra1_RxHPFCorner\t\t\t0xc\n\n/* Zebra4 */\n#define\t\trGlobalCtrl\t\t\t\t\t0\t/* Useless now */\n#define\t\trRTL8256_TxLPF\t\t\t\t19\n#define\t\trRTL8256_RxLPF\t\t\t\t11\n\n/* RTL8258 */\n#define\t\trRTL8258_TxLPF\t\t\t\t0x11\t/* Useless now */\n#define\t\trRTL8258_RxLPF\t\t\t\t0x13\n#define\t\trRTL8258_RSSILPF\t\t\t\t0xa\n\n/*\n * RL6052 Register definition\n *   */\n#define\t\tRF_AC\t\t\t\t\t\t0x00\t/*  */\n\n#define\t\tRF_IQADJ_G1\t\t\t\t\t0x01\t/*  */\n#define\t\tRF_IQADJ_G2\t\t\t\t\t0x02\t/*  */\n\n#define\t\tRF_POW_TRSW\t\t\t\t0x05\t/*  */\n\n#define\t\tRF_GAIN_RX\t\t\t\t\t0x06\t/*  */\n#define\t\tRF_GAIN_TX\t\t\t\t\t0x07\t/*  */\n\n#define\t\tRF_TXM_IDAC\t\t\t\t\t0x08\t/*  */\n#define\t\tRF_IPA_G\t\t\t\t\t\t0x09\t/*  */\n#define\t\tRF_TXBIAS_G\t\t\t\t\t0x0A\n#define\t\tRF_TXPA_AG\t\t\t\t\t0x0B\n#define\t\tRF_IPA_A\t\t\t\t\t\t0x0C\t/*  */\n#define\t\tRF_TXBIAS_A\t\t\t\t\t0x0D\n#define\t\tRF_BS_PA_APSET_G9_G11\t\t0x0E\n#define\t\tRF_BS_IQGEN\t\t\t\t\t0x0F\t/*  */\n\n#define\t\tRF_MODE1\t\t\t\t\t0x10\t/*  */\n#define\t\tRF_MODE2\t\t\t\t\t0x11\t/*  */\n\n#define\t\tRF_RX_AGC_HP\t\t\t\t0x12\t/*  */\n#define\t\tRF_TX_AGC\t\t\t\t\t0x13\t/*  */\n#define\t\tRF_BIAS\t\t\t\t\t\t0x14\t/*  */\n#define\t\tRF_IPA\t\t\t\t\t\t0x15\t/*  */\n#define\t\tRF_TXBIAS\t\t\t\t\t0x16\n#define\t\tRF_POW_ABILITY\t\t\t\t0x17\t/*  */\n#define\t\tRF_CHNLBW\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define\t\tRF_TOP\t\t\t\t\t\t0x19\t/*  */\n\n#define\t\tRF_RX_G1\t\t\t\t\t0x1A\t/*  */\n#define\t\tRF_RX_G2\t\t\t\t\t0x1B\t/*  */\n\n#define\t\tRF_RX_BB2\t\t\t\t\t0x1C\t/*  */\n#define\t\tRF_RX_BB1\t\t\t\t\t0x1D\t/*  */\n\n#define\t\tRF_RCK1\t\t\t\t\t\t0x1E\t/*  */\n#define\t\tRF_RCK2\t\t\t\t\t\t0x1F\t/*  */\n\n#define\t\tRF_TX_G1\t\t\t\t\t\t0x20\t/*  */\n#define\t\tRF_TX_G2\t\t\t\t\t\t0x21\t/*  */\n#define\t\tRF_TX_G3\t\t\t\t\t\t0x22\t/*  */\n\n#define\t\tRF_TX_BB1\t\t\t\t\t0x23\t/*  */\n\n#define\t\tRF_T_METER_88E\t\t\t\t\t0x42\t/*  */\n#define\t\tRF_T_METER\t\t\t\t\t0x24\t/*  */\n\n#define\t\tRF_SYN_G1\t\t\t\t\t0x25\t/* RF TX Power control */\n#define\t\tRF_SYN_G2\t\t\t\t\t0x26\t/* RF TX Power control */\n#define\t\tRF_SYN_G3\t\t\t\t\t0x27\t/* RF TX Power control */\n#define\t\tRF_SYN_G4\t\t\t\t\t0x28\t/* RF TX Power control */\n#define\t\tRF_SYN_G5\t\t\t\t\t0x29\t/* RF TX Power control */\n#define\t\tRF_SYN_G6\t\t\t\t\t0x2A\t/* RF TX Power control */\n#define\t\tRF_SYN_G7\t\t\t\t\t0x2B\t/* RF TX Power control */\n#define\t\tRF_SYN_G8\t\t\t\t\t0x2C\t/* RF TX Power control */\n\n#define\t\tRF_RCK_OS\t\t\t\t\t0x30\t/* RF TX PA control */\n#define\t\tRF_TXPA_G1\t\t\t\t\t0x31\t/* RF TX PA control */\n#define\t\tRF_TXPA_G2\t\t\t\t\t0x32\t/* RF TX PA control */\n#define\t\tRF_TXPA_G3\t\t\t\t\t0x33\t/* RF TX PA control */\n#define\t\tRF_TX_BIAS_A\t\t\t\t\t0x35\n#define\t\tRF_TX_BIAS_D\t\t\t\t\t0x36\n#define\t\tRF_LOBF_9\t\t\t\t\t0x38\n#define\t\tRF_RXRF_A3\t\t\t\t\t0x3C\t/*\t */\n#define\t\tRF_TRSW\t\t\t\t\t\t0x3F\n\n#define\t\tRF_TXRF_A2\t\t\t\t\t0x41\n#define\t\tRF_TXPA_G4\t\t\t\t\t0x46\n#define\t\tRF_TXPA_A4\t\t\t\t\t0x4B\n#define\tRF_0x52\t\t\t\t\t0x52\n#define\t\tRF_WE_LUT\t\t\t\t\t0xEF\n\n\n/*\n * Bit Mask\n *\n * 1. Page1(0x100) */\n#define\t\tbBBResetB\t\t\t\t\t0x100\t/* Useless now? */\n#define\t\tbGlobalResetB\t\t\t\t\t0x200\n#define\t\tbOFDMTxStart\t\t\t\t\t0x4\n#define\t\tbCCKTxStart\t\t\t\t\t0x8\n#define\t\tbCRC32Debug\t\t\t\t\t0x100\n#define\t\tbPMACLoopback\t\t\t\t0x10\n#define\t\tbTxLSIG\t\t\t\t\t\t0xffffff\n#define\t\tbOFDMTxRate\t\t\t\t\t0xf\n#define\t\tbOFDMTxReserved\t\t\t\t0x10\n#define\t\tbOFDMTxLength\t\t\t\t0x1ffe0\n#define\t\tbOFDMTxParity\t\t\t\t0x20000\n#define\t\tbTxHTSIG1\t\t\t\t\t0xffffff\n#define\t\tbTxHTMCSRate\t\t\t\t0x7f\n#define\t\tbTxHTBW\t\t\t\t\t\t0x80\n#define\t\tbTxHTLength\t\t\t\t\t0xffff00\n#define\t\tbTxHTSIG2\t\t\t\t\t0xffffff\n#define\t\tbTxHTSmoothing\t\t\t\t0x1\n#define\t\tbTxHTSounding\t\t\t\t0x2\n#define\t\tbTxHTReserved\t\t\t\t0x4\n#define\t\tbTxHTAggreation\t\t\t\t0x8\n#define\t\tbTxHTSTBC\t\t\t\t\t0x30\n#define\t\tbTxHTAdvanceCoding\t\t\t0x40\n#define\t\tbTxHTShortGI\t\t\t\t\t0x80\n#define\t\tbTxHTNumberHT_LTF\t\t\t0x300\n#define\t\tbTxHTCRC8\t\t\t\t\t0x3fc00\n#define\t\tbCounterReset\t\t\t\t0x10000\n#define\t\tbNumOfOFDMTx\t\t\t\t0xffff\n#define\t\tbNumOfCCKTx\t\t\t\t\t0xffff0000\n#define\t\tbTxIdleInterval\t\t\t\t0xffff\n#define\t\tbOFDMService\t\t\t\t\t0xffff0000\n#define\t\tbTxMACHeader\t\t\t\t0xffffffff\n#define\t\tbTxDataInit\t\t\t\t\t0xff\n#define\t\tbTxHTMode\t\t\t\t\t0x100\n#define\t\tbTxDataType\t\t\t\t\t0x30000\n#define\t\tbTxRandomSeed\t\t\t\t0xffffffff\n#define\t\tbCCKTxPreamble\t\t\t\t0x1\n#define\t\tbCCKTxSFD\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxSIG\t\t\t\t\t0xff\n#define\t\tbCCKTxService\t\t\t\t\t0xff00\n#define\t\tbCCKLengthExt\t\t\t\t\t0x8000\n#define\t\tbCCKTxLength\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxCRC16\t\t\t\t\t0xffff\n#define\t\tbCCKTxStatus\t\t\t\t\t0x1\n#define\t\tbOFDMTxStatus\t\t\t\t0x2\n\n#define\t\tIS_BB_REG_OFFSET_92S(_Offset)\t\t((_Offset >= 0x800) && (_Offset <= 0xfff))\n\n/* 2. Page8(0x800) */\n#define\t\tbRFMOD\t\t\t\t\t\t0x1\t/* Reg 0x800 rFPGA0_RFMOD */\n#define\t\tbJapanMode\t\t\t\t\t0x2\n#define\t\tbCCKTxSC\t\t\t\t\t\t0x30\n#define\t\tbCCKEn\t\t\t\t\t\t0x1000000\n#define\t\tbOFDMEn\t\t\t\t\t0x2000000\n\n#define\t\tbOFDMRxADCPhase           \t\t0x10000\t/* Useless now */\n#define\t\tbOFDMTxDACPhase\t\t0x40000\n#define\t\tbXATxAGC\t\t\t\t0x3f\n\n#define\t\tbAntennaSelect\t\t\t0x0300\n\n#define\t\tbXBTxAGC                  \t\t\t\t0xf00\t/* Reg 80c rFPGA0_TxGainStage */\n#define\t\tbXCTxAGC\t\t\t\t0xf000\n#define\t\tbXDTxAGC\t\t\t\t0xf0000\n\n#define\t\tbPAStart                  \t\t\t\t0xf0000000\t/* Useless now */\n#define\t\tbTRStart\t\t\t\t0x00f00000\n#define\t\tbRFStart\t\t\t\t0x0000f000\n#define\t\tbBBStart\t\t\t\t0x000000f0\n#define\t\tbBBCCKStart\t\t\t0x0000000f\n#define\t\tbPAEnd                    \t\t\t\t0xf          /* Reg0x814 */\n#define\t\tbTREnd\t\t\t\t0x0f000000\n#define\t\tbRFEnd\t\t\t\t0x000f0000\n#define\t\tbCCAMask                  \t\t\t\t0x000000f0   /* T2R */\n#define\t\tbR2RCCAMask\t\t\t0x00000f00\n#define\t\tbHSSI_R2TDelay\t\t\t0xf8000000\n#define\t\tbHSSI_T2RDelay\t\t\t0xf80000\n#define\t\tbContTxHSSI               \t\t\t0x400     /* chane gain at continue Tx */\n#define\t\tbIGFromCCK\t\t\t0x200\n#define\t\tbAGCAddress\t\t\t0x3f\n#define\t\tbRxHPTx\t\t\t\t0x7000\n#define\t\tbRxHPT2R\t\t\t\t0x38000\n#define\t\tbRxHPCCKIni\t\t\t0xc0000\n#define\t\tbAGCTxCode\t\t\t0xc00000\n#define\t\tbAGCRxCode\t\t\t0x300000\n\n#define\t\tb3WireDataLength          \t\t\t0x800\t/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */\n#define\t\tb3WireAddressLength\t\t0x400\n\n#define\t\tb3WireRFPowerDown         \t\t0x1\t/* Useless now\n * #define bHWSISelect\t\t0x8 */\n#define\t\tb5GPAPEPolarity\t\t\t0x40000000\n#define\t\tb2GPAPEPolarity\t\t\t0x80000000\n#define\t\tbRFSW_TxDefaultAnt\t\t0x3\n#define\t\tbRFSW_TxOptionAnt\t\t0x30\n#define\t\tbRFSW_RxDefaultAnt\t\t0x300\n#define\t\tbRFSW_RxOptionAnt\t\t0x3000\n#define\t\tbRFSI_3WireData\t\t\t0x1\n#define\t\tbRFSI_3WireClock\t\t\t0x2\n#define\t\tbRFSI_3WireLoad\t\t\t0x4\n#define\t\tbRFSI_3WireRW\t\t\t0x8\n#define\t\tbRFSI_3Wire\t\t\t0xf\n\n#define\t\tbRFSI_RFENV               \t\t0x10\t/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */\n\n#define\t\tbRFSI_TRSW                \t\t0x20\t/* Useless now */\n#define\t\tbRFSI_TRSWB\t\t0x40\n#define\t\tbRFSI_ANTSW\t\t0x100\n#define\t\tbRFSI_ANTSWB\t\t0x200\n#define\t\tbRFSI_PAPE\t\t\t0x400\n#define\t\tbRFSI_PAPE5G\t\t0x800\n#define\t\tbBandSelect\t\t\t0x1\n#define\t\tbHTSIG2_GI\t\t\t0x80\n#define\t\tbHTSIG2_Smoothing\t\t0x01\n#define\t\tbHTSIG2_Sounding\t\t0x02\n#define\t\tbHTSIG2_Aggreaton\t\t0x08\n#define\t\tbHTSIG2_STBC\t\t0x30\n#define\t\tbHTSIG2_AdvCoding\t\t0x40\n#define\t\tbHTSIG2_NumOfHTLTF\t0x300\n#define\t\tbHTSIG2_CRC8\t\t0x3fc\n#define\t\tbHTSIG1_MCS\t\t0x7f\n#define\t\tbHTSIG1_BandWidth\t\t0x80\n#define\t\tbHTSIG1_HTLength\t\t0xffff\n#define\t\tbLSIG_Rate\t\t\t0xf\n#define\t\tbLSIG_Reserved\t\t0x10\n#define\t\tbLSIG_Length\t\t0x1fffe\n#define\t\tbLSIG_Parity\t\t\t0x20\n#define\t\tbCCKRxPhase\t\t0x4\n\n#define\t\tbLSSIReadAddress          \t\t0x7f800000   /* T65 RF */\n\n#define\t\tbLSSIReadEdge             \t\t0x80000000   /* LSSI \"Read\" edge signal */\n\n#define\t\tbLSSIReadBackData         \t\t0xfffff\t\t/* T65 RF */\n\n#define\t\tbLSSIReadOKFlag           \t\t0x1000\t/* Useless now */\n#define\t\tbCCKSampleRate            \t\t0x8       /* 0: 44MHz, 1:88MHz      \t\t */\n#define\t\tbRegulator0Standby\t\t0x1\n#define\t\tbRegulatorPLLStandby\t0x2\n#define\t\tbRegulator1Standby\t\t0x4\n#define\t\tbPLLPowerUp\t\t0x8\n#define\t\tbDPLLPowerUp\t\t0x10\n#define\t\tbDA10PowerUp\t\t0x20\n#define\t\tbAD7PowerUp\t\t0x200\n#define\t\tbDA6PowerUp\t\t0x2000\n#define\t\tbXtalPowerUp\t\t0x4000\n#define\t\tb40MDClkPowerUP\t0x8000\n#define\t\tbDA6DebugMode\t\t0x20000\n#define\t\tbDA6Swing\t\t\t0x380000\n\n#define\t\tbADClkPhase               \t\t0x4000000\t/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */\n\n#define\t\tb80MClkDelay              \t\t0x18000000\t/* Useless */\n#define\t\tbAFEWatchDogEnable\t0x20000000\n\n#define\t\tbXtalCap01                \t\t\t0xc0000000\t/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */\n#define\t\tbXtalCap23\t\t\t0x3\n#define\t\tbXtalCap92x\t\t\t\t0x0f000000\n#define\t\tbXtalCap\t\t\t0x0f000000\n\n#define\t\tbIntDifClkEnable          \t\t0x400\t/* Useless */\n#define\t\tbExtSigClkEnable\t\t0x800\n#define\t\tbBandgapMbiasPowerUp\t0x10000\n#define\t\tbAD11SHGain\t\t0xc0000\n#define\t\tbAD11InputRange\t\t0x700000\n#define\t\tbAD11OPCurrent\t\t0x3800000\n#define\t\tbIPathLoopback\t\t0x4000000\n#define\t\tbQPathLoopback\t\t0x8000000\n#define\t\tbAFELoopback\t\t0x10000000\n#define\t\tbDA10Swing\t\t0x7e0\n#define\t\tbDA10Reverse\t\t0x800\n#define\t\tbDAClkSource\t\t0x1000\n#define\t\tbAD7InputRange\t\t0x6000\n#define\t\tbAD7Gain\t\t\t0x38000\n#define\t\tbAD7OutputCMMode\t0x40000\n#define\t\tbAD7InputCMMode\t0x380000\n#define\t\tbAD7Current\t\t0xc00000\n#define\t\tbRegulatorAdjust\t\t0x7000000\n#define\t\tbAD11PowerUpAtTx\t0x1\n#define\t\tbDA10PSAtTx\t\t0x10\n#define\t\tbAD11PowerUpAtRx\t0x100\n#define\t\tbDA10PSAtRx\t\t0x1000\n#define\t\tbCCKRxAGCFormat\t\t0x200\n#define\t\tbPSDFFTSamplepPoint\t0xc000\n#define\t\tbPSDAverageNum\t\t0x3000\n#define\t\tbIQPathControl\t\t0xc00\n#define\t\tbPSDFreq\t\t\t0x3ff\n#define\t\tbPSDAntennaPath\t\t0x30\n#define\t\tbPSDIQSwitch\t\t0x40\n#define\t\tbPSDRxTrigger\t\t0x400000\n#define\t\tbPSDTxTrigger\t\t0x80000000\n#define\t\tbPSDSineToneScale\t\t0x7f000000\n#define\t\tbPSDReport\t\t0xffff\n\n/* 3. Page9(0x900) */\n#define\t\tbOFDMTxSC                 \t\t0x30000000\t/* Useless */\n#define\t\tbCCKTxOn\t\t\t0x1\n#define\t\tbOFDMTxOn\t\t0x2\n#define\t\tbDebugPage                \t\t0xfff  /* reset debug page and also HWord, LWord */\n#define\t\tbDebugItem                \t\t0xff   /* reset debug page and LWord */\n#define\t\tbAntL\t\t\t\t0x10\n#define\t\tbAntNonHT\t\t\t0x100\n#define\t\tbAntHT1\t\t\t0x1000\n#define\t\tbAntHT2\t\t\t0x10000\n#define\t\tbAntHT1S1\t\t\t0x100000\n#define\t\tbAntNonHTS1\t\t0x1000000\n\n/* 4. PageA(0xA00) */\n#define\t\tbCCKBBMode                \t\t0x3\t/* Useless */\n#define\t\tbCCKTxPowerSaving\t\t0x80\n#define\t\tbCCKRxPowerSaving\t\t0x40\n\n#define\t\tbCCKSideBand              \t\t0x10\t/* Reg 0xa00 rCCK0_System 20/40 switch */\n\n#define\t\tbCCKScramble              \t\t0x8\t/* Useless */\n#define\t\tbCCKAntDiversity\t\t\t0x8000\n#define\t\tbCCKCarrierRecovery\t\t0x4000\n#define\t\tbCCKTxRate\t\t\t0x3000\n#define\t\tbCCKDCCancel\t\t0x0800\n#define\t\tbCCKISICancel\t\t0x0400\n#define\t\tbCCKMatchFilter\t\t0x0200\n#define\t\tbCCKEqualizer\t\t0x0100\n#define\t\tbCCKPreambleDetect\t\t0x800000\n#define\t\tbCCKFastFalseCCA\t\t0x400000\n#define\t\tbCCKChEstStart\t\t0x300000\n#define\t\tbCCKCCACount\t\t0x080000\n#define\t\tbCCKcs_lim\t\t\t0x070000\n#define\t\tbCCKBistMode\t\t0x80000000\n#define\t\tbCCKCCAMask\t\t0x40000000\n#define\t\tbCCKTxDACPhase\t\t0x4\n#define\t\tbCCKRxADCPhase         \t   \t0x20000000   /* r_rx_clk */\n#define\t\tbCCKr_cp_mode0\t\t0x0100\n#define\t\tbCCKTxDCOffset\t\t0xf0\n#define\t\tbCCKRxDCOffset\t\t0xf\n#define\t\tbCCKCCAMode\t\t0xc000\n#define\t\tbCCKFalseCS_lim\t\t0x3f00\n#define\t\tbCCKCS_ratio\t\t0xc00000\n#define\t\tbCCKCorgBit_sel\t\t0x300000\n#define\t\tbCCKPD_lim\t\t0x0f0000\n#define\t\tbCCKNewCCA\t\t0x80000000\n#define\t\tbCCKRxHPofIG\t\t0x8000\n#define\t\tbCCKRxIG\t\t\t0x7f00\n#define\t\tbCCKLNAPolarity\t\t0x800000\n#define\t\tbCCKRx1stGain\t\t0x7f0000\n#define\t\tbCCKRFExtend              \t\t0x20000000 /* CCK Rx Iinital gain polarity */\n#define\t\tbCCKRxAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKRxAGCSatCount\t\t0xe0\n#define\t\tbCCKRxRFSettle            \t\t0x1f       /* AGCsamp_dly */\n#define\t\tbCCKFixedRxAGC\t\t0x8000\n/* #define bCCKRxAGCFormat\t\t0x4000 */   /* remove to HSSI register 0x824 */\n#define\t\tbCCKAntennaPolarity\t\t0x2000\n#define\t\tbCCKTxFilterType\t\t0x0c00\n#define\t\tbCCKRxAGCReportType\t\t0x0300\n#define\t\tbCCKRxDAGCEn\t\t0x80000000\n#define\t\tbCCKRxDAGCPeriod\t\t0x20000000\n#define\t\tbCCKRxDAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKTimingRecovery\t\t0x800000\n#define\t\tbCCKTxC0\t\t\t0x3f0000\n#define\t\tbCCKTxC1\t\t\t0x3f000000\n#define\t\tbCCKTxC2\t\t\t0x3f\n#define\t\tbCCKTxC3\t\t\t0x3f00\n#define\t\tbCCKTxC4\t\t\t0x3f0000\n#define\t\tbCCKTxC5\t\t\t0x3f000000\n#define\t\tbCCKTxC6\t\t\t0x3f\n#define\t\tbCCKTxC7\t\t\t0x3f00\n#define\t\tbCCKDebugPort\t\t0xff0000\n#define\t\tbCCKDACDebug\t\t0x0f000000\n#define\t\tbCCKFalseAlarmEnable\t0x8000\n#define\t\tbCCKFalseAlarmRead\t0x4000\n#define\t\tbCCKTRSSI\t\t\t0x7f\n#define\t\tbCCKRxAGCReport\t\t0xfe\n#define\t\tbCCKRxReport_AntSel\t0x80000000\n#define\t\tbCCKRxReport_MFOff\t0x40000000\n#define\t\tbCCKRxRxReport_SQLoss\t0x20000000\n#define\t\tbCCKRxReport_Pktloss\t0x10000000\n#define\t\tbCCKRxReport_Lockedbit\t0x08000000\n#define\t\tbCCKRxReport_RateError\t0x04000000\n#define\t\tbCCKRxReport_RxRate\t0x03000000\n#define\t\tbCCKRxFACounterLower\t0xff\n#define\t\tbCCKRxFACounterUpper\t0xff000000\n#define\t\tbCCKRxHPAGCStart\t\t0xe000\n#define\t\tbCCKRxHPAGCFinal\t\t0x1c00\n#define\t\tbCCKRxFalseAlarmEnable\t0x8000\n#define\t\tbCCKFACounterFreeze\t0x4000\n#define\t\tbCCKTxPathSel\t\t0x10000000\n#define\t\tbCCKDefaultRxPath\t\t0xc000000\n#define\t\tbCCKOptionRxPath\t\t0x3000000\n\n/* 5. PageC(0xC00) */\n#define\t\tbNumOfSTF                \t\t\t0x3\t/* Useless */\n#define\t\tbShift_L\t\t\t0xc0\n#define\t\tbGI_TH\t\t\t0xc\n#define\t\tbRxPathA\t\t\t0x1\n#define\t\tbRxPathB\t\t\t0x2\n#define\t\tbRxPathC\t\t\t0x4\n#define\t\tbRxPathD\t\t\t0x8\n#define\t\tbTxPathA\t\t\t0x1\n#define\t\tbTxPathB\t\t\t0x2\n#define\t\tbTxPathC\t\t\t0x4\n#define\t\tbTxPathD\t\t\t0x8\n#define\t\tbTRSSIFreq\t\t\t0x200\n#define\t\tbADCBackoff\t\t\t0x3000\n#define\t\tbDFIRBackoff\t\t\t0xc000\n#define\t\tbTRSSILatchPhase\t\t0x10000\n#define\t\tbRxIDCOffset\t\t\t0xff\n#define\t\tbRxQDCOffset\t\t0xff00\n#define\t\tbRxDFIRMode\t\t0x1800000\n#define\t\tbRxDCNFType\t\t0xe000000\n#define\t\tbRXIQImb_A\t\t0x3ff\n#define\t\tbRXIQImb_B\t\t\t0xfc00\n#define\t\tbRXIQImb_C\t\t\t0x3f0000\n#define\t\tbRXIQImb_D\t\t0xffc00000\n#define\t\tbDC_dc_Notch\t\t0x60000\n#define\t\tbRxNBINotch\t\t0x1f000000\n#define\t\tbPD_TH\t\t\t0xf\n#define\t\tbPD_TH_Opt2\t\t0xc000\n#define\t\tbPWED_TH\t\t\t0x700\n#define\t\tbIfMF_Win_L\t\t0x800\n#define\t\tbPD_Option\t\t\t0x1000\n#define\t\tbMF_Win_L\t\t\t0xe000\n#define\t\tbBW_Search_L\t\t0x30000\n#define\t\tbwin_enh_L\t\t\t0xc0000\n#define\t\tbBW_TH\t\t\t0x700000\n#define\t\tbED_TH2\t\t\t0x3800000\n#define\t\tbBW_option\t\t\t0x4000000\n#define\t\tbRatio_TH\t\t\t0x18000000\n#define\t\tbWindow_L\t\t\t0xe0000000\n#define\t\tbSBD_Option\t\t0x1\n#define\t\tbFrame_TH\t\t\t0x1c\n#define\t\tbFS_Option\t\t\t0x60\n#define\t\tbDC_Slope_check\t\t0x80\n#define\t\tbFGuard_Counter_DC_L\t0xe00\n#define\t\tbFrame_Weight_Short\t0x7000\n#define\t\tbSub_Tune\t\t\t0xe00000\n#define\t\tbFrame_DC_Length\t\t0xe000000\n#define\t\tbSBD_start_offset\t\t0x30000000\n#define\t\tbFrame_TH_2\t\t0x7\n#define\t\tbFrame_GI2_TH\t\t0x38\n#define\t\tbGI2_Sync_en\t\t0x40\n#define\t\tbSarch_Short_Early\t\t0x300\n#define\t\tbSarch_Short_Late\t\t0xc00\n#define\t\tbSarch_GI2_Late\t\t0x70000\n#define\t\tbCFOAntSum\t\t0x1\n#define\t\tbCFOAcc\t\t\t0x2\n#define\t\tbCFOStartOffset\t\t0xc\n#define\t\tbCFOLookBack\t\t0x70\n#define\t\tbCFOSumWeight\t\t0x80\n#define\t\tbDAGCEnable\t\t0x10000\n#define\t\tbTXIQImb_A\t\t\t0x3ff\n#define\t\tbTXIQImb_B\t\t\t0xfc00\n#define\t\tbTXIQImb_C\t\t\t0x3f0000\n#define\t\tbTXIQImb_D\t\t\t0xffc00000\n#define\t\tbTxIDCOffset\t\t\t0xff\n#define\t\tbTxQDCOffset\t\t0xff00\n#define\t\tbTxDFIRMode\t\t0x10000\n#define\t\tbTxPesudoNoiseOn\t\t0x4000000\n#define\t\tbTxPesudoNoise_A\t\t0xff\n#define\t\tbTxPesudoNoise_B\t\t0xff00\n#define\t\tbTxPesudoNoise_C\t\t0xff0000\n#define\t\tbTxPesudoNoise_D\t\t0xff000000\n#define\t\tbCCADropOption\t\t0x20000\n#define\t\tbCCADropThres\t\t0xfff00000\n#define\t\tbEDCCA_H\t\t\t0xf\n#define\t\tbEDCCA_L\t\t\t0xf0\n#define\t\tbLambda_ED\t\t0x300\n#define\t\tbRxInitialGain\t\t\t0x7f\n#define\t\tbRxAntDivEn\t\t0x80\n#define\t\tbRxAGCAddressForLNA\t0x7f00\n#define\t\tbRxHighPowerFlow\t\t0x8000\n#define\t\tbRxAGCFreezeThres\t\t0xc0000\n#define\t\tbRxFreezeStep_AGC1\t0x300000\n#define\t\tbRxFreezeStep_AGC2\t0xc00000\n#define\t\tbRxFreezeStep_AGC3\t0x3000000\n#define\t\tbRxFreezeStep_AGC0\t0xc000000\n#define\t\tbRxRssi_Cmp_En\t\t0x10000000\n#define\t\tbRxQuickAGCEn\t\t0x20000000\n#define\t\tbRxAGCFreezeThresMode\t0x40000000\n#define\t\tbRxOverFlowCheckType\t0x80000000\n#define\t\tbRxAGCShift\t\t\t0x7f\n#define\t\tbTRSW_Tri_Only\t\t0x80\n#define\t\tbPowerThres\t\t0x300\n#define\t\tbRxAGCEn\t\t\t0x1\n#define\t\tbRxAGCTogetherEn\t\t0x2\n#define\t\tbRxAGCMin\t\t0x4\n#define\t\tbRxHP_Ini\t\t\t0x7\n#define\t\tbRxHP_TRLNA\t\t0x70\n#define\t\tbRxHP_RSSI\t\t\t0x700\n#define\t\tbRxHP_BBP1\t\t0x7000\n#define\t\tbRxHP_BBP2\t\t0x70000\n#define\t\tbRxHP_BBP3\t\t0x700000\n#define\t\tbRSSI_H                  \t\t\t0x7f0000     /* the threshold for high power */\n#define\t\tbRSSI_Gen                \t\t\t0x7f000000   /* the threshold for ant diversity */\n#define\t\tbRxSettle_TRSW\t\t0x7\n#define\t\tbRxSettle_LNA\t\t0x38\n#define\t\tbRxSettle_RSSI\t\t0x1c0\n#define\t\tbRxSettle_BBP\t\t0xe00\n#define\t\tbRxSettle_RxHP\t\t0x7000\n#define\t\tbRxSettle_AntSW_RSSI\t0x38000\n#define\t\tbRxSettle_AntSW\t\t0xc0000\n#define\t\tbRxProcessTime_DAGC\t0x300000\n#define\t\tbRxSettle_HSSI\t\t0x400000\n#define\t\tbRxProcessTime_BBPPW\t0x800000\n#define\t\tbRxAntennaPowerShift\t0x3000000\n#define\t\tbRSSITableSelect\t\t0xc000000\n#define\t\tbRxHP_Final\t\t\t0x7000000\n#define\t\tbRxHTSettle_BBP\t\t0x7\n#define\t\tbRxHTSettle_HSSI\t\t0x8\n#define\t\tbRxHTSettle_RxHP\t\t0x70\n#define\t\tbRxHTSettle_BBPPW\t\t0x80\n#define\t\tbRxHTSettle_Idle\t\t0x300\n#define\t\tbRxHTSettle_Reserved\t0x1c00\n#define\t\tbRxHTRxHPEn\t\t0x8000\n#define\t\tbRxHTAGCFreezeThres\t0x30000\n#define\t\tbRxHTAGCTogetherEn\t0x40000\n#define\t\tbRxHTAGCMin\t\t0x80000\n#define\t\tbRxHTAGCEn\t\t0x100000\n#define\t\tbRxHTDAGCEn\t\t0x200000\n#define\t\tbRxHTRxHP_BBP\t\t0x1c00000\n#define\t\tbRxHTRxHP_Final\t\t0xe0000000\n#define\t\tbRxPWRatioTH\t\t0x3\n#define\t\tbRxPWRatioEn\t\t0x4\n#define\t\tbRxMFHold\t\t\t0x3800\n#define\t\tbRxPD_Delay_TH1\t\t0x38\n#define\t\tbRxPD_Delay_TH2\t\t0x1c0\n#define\t\tbRxPD_DC_COUNT_MAX\t0x600\n/* #define bRxMF_Hold               0x3800 */\n#define\t\tbRxPD_Delay_TH\t\t0x8000\n#define\t\tbRxProcess_Delay\t\t0xf0000\n#define\t\tbRxSearchrange_GI2_Early\t0x700000\n#define\t\tbRxFrame_Guard_Counter_L\t0x3800000\n#define\t\tbRxSGI_Guard_L\t\t0xc000000\n#define\t\tbRxSGI_Search_L\t\t0x30000000\n#define\t\tbRxSGI_TH\t\t\t0xc0000000\n#define\t\tbDFSCnt0\t\t\t0xff\n#define\t\tbDFSCnt1\t\t\t0xff00\n#define\t\tbDFSFlag\t\t\t0xf0000\n#define\t\tbMFWeightSum\t\t0x300000\n#define\t\tbMinIdxTH\t\t\t0x7f000000\n#define\t\tbDAFormat\t\t\t0x40000\n#define\t\tbTxChEmuEnable\t\t0x01000000\n#define\t\tbTRSWIsolation_A\t\t0x7f\n#define\t\tbTRSWIsolation_B\t\t0x7f00\n#define\t\tbTRSWIsolation_C\t\t0x7f0000\n#define\t\tbTRSWIsolation_D\t\t0x7f000000\n#define\t\tbExtLNAGain\t\t0x7c00\n\n/* 6. PageE(0xE00) */\n#define\t\tbSTBCEn                  \t\t\t0x4\t/* Useless */\n#define\t\tbAntennaMapping\t\t0x10\n#define\t\tbNss\t\t\t0x20\n#define\t\tbCFOAntSumD\t\t0x200\n#define\t\tbPHYCounterReset\t\t0x8000000\n#define\t\tbCFOReportGet\t\t0x4000000\n#define\t\tbOFDMContinueTx\t\t0x10000000\n#define\t\tbOFDMSingleCarrier\t\t0x20000000\n#define\t\tbOFDMSingleTone\t\t0x40000000\n/* #define bRxPath1                 0x01 */\n/* #define bRxPath2                 0x02 */\n/* #define bRxPath3                 0x04 */\n/* #define bRxPath4                 0x08 */\n/* #define bTxPath1                 0x10 */\n/* #define bTxPath2                 0x20 */\n#define\t\tbHTDetect\t\t\t0x100\n#define\t\tbCFOEn\t\t\t0x10000\n#define\t\tbCFOValue\t\t\t0xfff00000\n#define\t\tbSigTone_Re\t\t\t0x3f\n#define\t\tbSigTone_Im\t\t\t0x7f00\n#define\t\tbCounter_CCA\t\t0xffff\n#define\t\tbCounter_ParityFail\t\t0xffff0000\n#define\t\tbCounter_RateIllegal\t\t0xffff\n#define\t\tbCounter_CRC8Fail\t\t0xffff0000\n#define\t\tbCounter_MCSNoSupport\t0xffff\n#define\t\tbCounter_FastSync\t\t0xffff\n#define\t\tbShortCFO\t\t\t0xfff\n#define\t\tbShortCFOTLength         \t\t12   /* total */\n#define\t\tbShortCFOFLength         \t\t11   /* fraction */\n#define\t\tbLongCFO\t\t\t0x7ff\n#define\t\tbLongCFOTLength\t\t11\n#define\t\tbLongCFOFLength\t\t11\n#define\t\tbTailCFO\t\t\t0x1fff\n#define\t\tbTailCFOTLength\t\t13\n#define\t\tbTailCFOFLength\t\t12\n#define\t\tbmax_en_pwdB\t\t0xffff\n#define\t\tbCC_power_dB\t\t0xffff0000\n#define\t\tbnoise_pwdB\t\t0xffff\n#define\t\tbPowerMeasTLength\t10\n#define\t\tbPowerMeasFLength\t3\n#define\t\tbRx_HT_BW\t\t0x1\n#define\t\tbRxSC\t\t\t0x6\n#define\t\tbRx_HT\t\t\t0x8\n#define\t\tbNB_intf_det_on\t\t0x1\n#define\t\tbIntf_win_len_cfg\t\t0x30\n#define\t\tbNB_Intf_TH_cfg\t\t0x1c0\n#define\t\tbRFGain\t\t\t0x3f\n#define\t\tbTableSel\t\t\t0x40\n#define\t\tbTRSW\t\t\t0x80\n#define\t\tbRxSNR_A\t\t\t0xff\n#define\t\tbRxSNR_B\t\t\t0xff00\n#define\t\tbRxSNR_C\t\t\t0xff0000\n#define\t\tbRxSNR_D\t\t\t0xff000000\n#define\t\tbSNREVMTLength\t\t8\n#define\t\tbSNREVMFLength\t\t1\n#define\t\tbCSI1st\t\t\t0xff\n#define\t\tbCSI2nd\t\t\t0xff00\n#define\t\tbRxEVM1st\t\t\t0xff0000\n#define\t\tbRxEVM2nd\t\t0xff000000\n#define\t\tbSIGEVM\t\t\t0xff\n#define\t\tbPWDB\t\t\t0xff00\n#define\t\tbSGIEN\t\t\t0x10000\n\n#define\t\tbSFactorQAM1             \t\t0xf\t/* Useless */\n#define\t\tbSFactorQAM2\t\t0xf0\n#define\t\tbSFactorQAM3\t\t0xf00\n#define\t\tbSFactorQAM4\t\t0xf000\n#define\t\tbSFactorQAM5\t\t0xf0000\n#define\t\tbSFactorQAM6\t\t0xf0000\n#define\t\tbSFactorQAM7\t\t0xf00000\n#define\t\tbSFactorQAM8\t\t0xf000000\n#define\t\tbSFactorQAM9\t\t0xf0000000\n#define\t\tbCSIScheme\t\t\t0x100000\n\n#define\t\tbNoiseLvlTopSet          \t\t0x3\t/* Useless */\n#define\t\tbChSmooth\t\t\t0x4\n#define\t\tbChSmoothCfg1\t\t0x38\n#define\t\tbChSmoothCfg2\t\t0x1c0\n#define\t\tbChSmoothCfg3\t\t0xe00\n#define\t\tbChSmoothCfg4\t\t0x7000\n#define\t\tbMRCMode\t\t0x800000\n#define\t\tbTHEVMCfg\t\t\t0x7000000\n\n#define\t\tbLoopFitType             \t\t\t0x1\t/* Useless */\n#define\t\tbUpdCFO\t\t\t0x40\n#define\t\tbUpdCFOOffData\t\t0x80\n#define\t\tbAdvUpdCFO\t\t0x100\n#define\t\tbAdvTimeCtrl\t\t0x800\n#define\t\tbUpdClko\t\t\t0x1000\n#define\t\tbFC\t\t\t\t0x6000\n#define\t\tbTrackingMode\t\t0x8000\n#define\t\tbPhCmpEnable\t\t0x10000\n#define\t\tbUpdClkoLTF\t\t\t0x20000\n#define\t\tbComChCFO\t\t0x40000\n#define\t\tbCSIEstiMode\t\t0x80000\n#define\t\tbAdvUpdEqz\t\t0x100000\n#define\t\tbUChCfg\t\t\t0x7000000\n#define\t\tbUpdEqz\t\t\t0x8000000\n\n/* Rx Pseduo noise */\n#define\t\tbRxPesudoNoiseOn         \t\t0x20000000\t/* Useless */\n#define\t\tbRxPesudoNoise_A\t\t0xff\n#define\t\tbRxPesudoNoise_B\t\t0xff00\n#define\t\tbRxPesudoNoise_C\t\t0xff0000\n#define\t\tbRxPesudoNoise_D\t\t0xff000000\n#define\t\tbPesudoNoiseState_A\t0xffff\n#define\t\tbPesudoNoiseState_B\t0xffff0000\n#define\t\tbPesudoNoiseState_C\t\t0xffff\n#define\t\tbPesudoNoiseState_D\t0xffff0000\n\n/* 7. RF Register\n * Zebra1 */\n#define\t\tbZebra1_HSSIEnable        \t\t0x8\t\t/* Useless */\n#define\t\tbZebra1_TRxControl\t\t0xc00\n#define\t\tbZebra1_TRxGainSetting\t0x07f\n#define\t\tbZebra1_RxCorner\t\t0xc00\n#define\t\tbZebra1_TxChargePump\t0x38\n#define\t\tbZebra1_RxChargePump\t0x7\n#define\t\tbZebra1_ChannelNum\t0xf80\n#define\t\tbZebra1_TxLPFBW\t\t0x400\n#define\t\tbZebra1_RxLPFBW\t\t0x600\n\n/* Zebra4 */\n#define\t\tbRTL8256RegModeCtrl1      \t0x100\t/* Useless */\n#define\t\tbRTL8256RegModeCtrl0\t0x40\n#define\t\tbRTL8256_TxLPFBW\t0x18\n#define\t\tbRTL8256_RxLPFBW\t0x600\n\n/* RTL8258 */\n#define\t\tbRTL8258_TxLPFBW          \t0xc\t/* Useless */\n#define\t\tbRTL8258_RxLPFBW\t0xc00\n#define\t\tbRTL8258_RSSILPFBW\t0xc0\n\n\n/*\n * Other Definition\n *   */\n\n/* byte endable for sb_write */\n#define\t\tbByte0                    \t\t\t0x1\t/* Useless */\n#define\t\tbByte1\t\t\t0x2\n#define\t\tbByte2\t\t\t0x4\n#define\t\tbByte3\t\t\t0x8\n#define\t\tbWord0\t\t\t0x3\n#define\t\tbWord1\t\t\t0xc\n#define\t\tbDWord\t\t\t0xf\n\n/* for PutRegsetting & GetRegSetting BitMask */\n#define\t\tbMaskByte0                \t\t0xff\t/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */\n#define\t\tbMaskByte1\t\t0xff00\n#define\t\tbMaskByte2\t\t0xff0000\n#define\t\tbMaskByte3\t\t0xff000000\n#define\t\tbMaskHWord\t\t0xffff0000\n#define\t\tbMaskLWord\t\t0x0000ffff\n#define\t\tbMaskDWord\t\t0xffffffff\n#define\t\tbMaskH3Bytes\t\t\t\t0xffffff00\n#define\t\tbMask12Bits\t\t\t\t0xfff\n#define\t\tbMaskH4Bits\t\t\t\t0xf0000000\n#define\t\tbMaskOFDM_D\t\t\t0xffc00000\n#define\t\tbMaskCCK\t\t\t\t0x3f3f3f3f\n\n\n\n#define\t\tbEnable                   0x1\t/* Useless */\n#define\t\tbDisable                  0x0\n\n#define\t\tLeftAntenna               \t\t\t0x0\t/* Useless */\n#define\t\tRightAntenna\t\t0x1\n\n#define\t\ttCheckTxStatus            \t\t500   /* 500ms */ /* Useless */\n#define\t\ttUpdateRxCounter          \t\t100   /* 100ms */\n\n#define\t\trateCCK     \t\t\t\t0\t/* Useless */\n#define\t\trateOFDM\t\t\t\t1\n#define\t\trateHT\t\t\t\t\t2\n\n/* define Register-End */\n#define\t\tbPMAC_End                 \t\t0x1ff\t/* Useless */\n#define\t\tbFPGAPHY0_End\t\t0x8ff\n#define\t\tbFPGAPHY1_End\t\t0x9ff\n#define\t\tbCCKPHY0_End\t\t0xaff\n#define\t\tbOFDMPHY0_End\t\t0xcff\n#define\t\tbOFDMPHY1_End\t\t0xdff\n\n/* define max debug item in each debug page\n * #define bMaxItem_FPGA_PHY0        0x9\n * #define bMaxItem_FPGA_PHY1        0x3\n * #define bMaxItem_PHY_11B          0x16\n * #define bMaxItem_OFDM_PHY0        0x29\n * #define bMaxItem_OFDM_PHY1        0x0 */\n\n#define\t\tbPMACControl              \t\t0x0\t\t/* Useless */\n#define\t\tbWMACControl\t\t0x1\n#define\t\tbWNICControl\t\t0x2\n\n#define\t\tPathA                     \t\t\t0x0\t/* Useless */\n#define\t\tPathB\t\t\t0x1\n#define\t\tPathC\t\t\t0x2\n#define\t\tPathD\t\t\t0x3\n\n/*--------------------------Define Parameters-------------------------------*/\n\n\n#endif\n"
  },
  {
    "path": "include/Hal8188EPwrSeq.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n\n#ifndef __HAL8188EPWRSEQ_H__\n#define __HAL8188EPWRSEQ_H__\n\n#include \"HalPwrSeqCmd.h\"\n\n/*\n\tCheck document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd\n\tThere are 6 HW Power States:\n\t0: POFF--Power Off\n\t1: PDN--Power Down\n\t2: CARDEMU--Card Emulation\n\t3: ACT--Active Mode\n\t4: LPS--Low Power State\n\t5: SUS--Suspend\n\n\tThe transision from different states are defined below\n\tTRANS_CARDEMU_TO_ACT\n\tTRANS_ACT_TO_CARDEMU\n\tTRANS_CARDEMU_TO_SUS\n\tTRANS_SUS_TO_CARDEMU\n\tTRANS_CARDEMU_TO_PDN\n\tTRANS_ACT_TO_LPS\n\tTRANS_LPS_TO_ACT\n\n\tTRANS_END\n\n    PWR SEQ Version: rtl8188E_PwrSeq_V09.h\n*/\n#define\tRTL8188E_TRANS_CARDEMU_TO_ACT_STEPS\t10\n#define\tRTL8188E_TRANS_ACT_TO_CARDEMU_STEPS\t10\n#define\tRTL8188E_TRANS_CARDEMU_TO_SUS_STEPS\t10\n#define\tRTL8188E_TRANS_SUS_TO_CARDEMU_STEPS\t10\n#define\tRTL8188E_TRANS_CARDEMU_TO_PDN_STEPS\t10\n#define\tRTL8188E_TRANS_PDN_TO_CARDEMU_STEPS\t10\n#define\tRTL8188E_TRANS_ACT_TO_LPS_STEPS\t15\n#define\tRTL8188E_TRANS_LPS_TO_ACT_STEPS\t15\n#define\tRTL8188E_TRANS_END_STEPS\t1\n\n\n#define RTL8188E_TRANS_CARDEMU_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0}, /* 0x02[1:0] = 0\treset BB*/\t\t\t\\\n\t{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[8] = 1 polling until return 0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, /*wait till 0x04[8] = 0*/\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*LDO normal mode*/\t\\\n\n#define RTL8188E_TRANS_ACT_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/\t\\\n\n#define RTL8188E_TRANS_CARDEMU_TO_SUS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT7}, /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\t\\\n\t{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */\t\\\n\t{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register  0xfe10[4]=1 */\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/\n\n#define RTL8188E_TRANS_SUS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\n\n#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\t\\\n\t{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */\t\\\n\t{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register  0xfe10[4]=1 */\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/\n\n#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\n\n#define RTL8188E_TRANS_CARDEMU_TO_PDN\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/\n\n#define RTL8188E_TRANS_PDN_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/\n\n\t/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */\n#define RTL8188E_TRANS_ACT_TO_LPS\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/\t\\\n\t{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\t\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/\t\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\t\\\n\t{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/\t\\\n\n\n#define RTL8188E_TRANS_LPS_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\\\n\t{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\\\n\t{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.\t0x08[4] = 0\t\t switch TSF to 40M*/\\\n\t{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\\\n\t{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.\t0x29[7:6] = 2b'00\t enable BB clock*/\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.\t0x101[1] = 1*/\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.\t0x100[7:0] = 0xFF\t enable WMAC TRX*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.\t0x02[1:0] = 2b'11\t enable BB macro*/\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.\t0x522 = 0*/\n\n#define RTL8188E_TRANS_END\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},\n\n\n\textern WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188E_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188E_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS + RTL8188E_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];\n\n#endif /* __HAL8188EPWRSEQ_H__ */\n"
  },
  {
    "path": "include/Hal8188FPhyCfg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8188FPHYCFG_H__\n#define __INC_HAL8188FPHYCFG_H__\n\n/*--------------------------Define Parameters-------------------------------*/\n#define LOOP_LIMIT\t\t\t\t5\n#define MAX_STALL_TIME\t\t\t50\t\t/* us */\n#define AntennaDiversityValue\t0x80\t/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */\n#define MAX_TXPWR_IDX_NMODE_92S\t63\n#define Reset_Cnt_Limit\t\t\t3\n\n#ifdef CONFIG_PCI_HCI\n\t#define MAX_AGGR_NUM\t0x0B\n#else\n\t#define MAX_AGGR_NUM\t0x07\n#endif /* CONFIG_PCI_HCI */\n\n\n/*--------------------------Define Parameters End-------------------------------*/\n\n\n/*------------------------------Define structure----------------------------*/\n\n/*------------------------------Define structure End----------------------------*/\n\n/*--------------------------Exported Function prototype---------------------*/\nu32\nPHY_QueryBBReg_8188F(\n\t\tPADAPTER\tAdapter,\n\t\tu32\t\tRegAddr,\n\t\tu32\t\tBitMask\n);\n\nvoid\nPHY_SetBBReg_8188F(\n\t\tPADAPTER\tAdapter,\n\t\tu32\t\tRegAddr,\n\t\tu32\t\tBitMask,\n\t\tu32\t\tData\n);\n\nu32\nPHY_QueryRFReg_8188F(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tenum rf_path\t\t\teRFPath,\n\t\tu32\t\t\t\tRegAddr,\n\t\tu32\t\t\t\tBitMask\n);\n\nvoid\nPHY_SetRFReg_8188F(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tenum rf_path\t\t\teRFPath,\n\t\tu32\t\t\t\tRegAddr,\n\t\tu32\t\t\t\tBitMask,\n\t\tu32\t\t\t\tData\n);\n\n/* MAC/BB/RF HAL config */\nint PHY_BBConfig8188F(PADAPTER\tAdapter);\n\nint PHY_RFConfig8188F(PADAPTER\tAdapter);\n\ns32 PHY_MACConfig8188F(PADAPTER padapter);\n\nint\nPHY_ConfigRFWithParaFile_8188F(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu8\t\t\t\t\t*pFileName,\n\tenum rf_path\t\t\t\teRFPath\n);\n\nvoid\nPHY_SetTxPowerIndex_8188F(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu32\t\t\t\t\tPowerIndex,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate\n);\n\nu8\nPHY_GetTxPowerIndex_8188F(\n\t\tPADAPTER\t\t\tpAdapter,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate,\n\t\tu8\t\tBandWidth,\n\t\tu8\t\t\t\t\tChannel,\n\tstruct txpwr_idx_comp *tic\n);\n\nvoid\nPHY_SetTxPowerLevel8188F(\n\t\tPADAPTER\t\tAdapter,\n\t\tu8\t\t\tchannel\n);\n\nvoid\nPHY_SetSwChnlBWMode8188F(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu8\t\t\t\t\tchannel,\n\t\tenum channel_width\tBandwidth,\n\t\tu8\t\t\t\t\tOffset40,\n\t\tu8\t\t\t\t\tOffset80\n);\n\nvoid phy_set_rf_path_switch_8188f(\n\t\tstruct\t\tdm_struct *phydm,\n\t\tbool\t\tbMain\n);\n\nvoid BBTurnOnBlock_8188F(_adapter *adapter);\n\n/*--------------------------Exported Function prototype End---------------------*/\n\n#endif\n"
  },
  {
    "path": "include/Hal8188FPhyReg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8188FPHYREG_H__\n#define __INC_HAL8188FPHYREG_H__\n\n/*--------------------------Define Parameters-------------------------------*/\n\n/* ************************************************************\n * Regsiter offset definition\n * ************************************************************ */\n\n/*\n * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00\n * 3. RF register 0x00-2E\n * 4. Bit Mask for BB/RF register\n * 5. Other defintion for BB/RF R/W\n *   */\n\n\n/*\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 1. Page1(0x100)\n *   */\n#define\t\trPMAC_Reset\t\t\t\t\t0x100\n#define\t\trPMAC_TxStart\t\t\t\t\t0x104\n#define\t\trPMAC_TxLegacySIG\t\t\t\t0x108\n#define\t\trPMAC_TxHTSIG1\t\t\t\t0x10c\n#define\t\trPMAC_TxHTSIG2\t\t\t\t0x110\n#define\t\trPMAC_PHYDebug\t\t\t\t0x114\n#define\t\trPMAC_TxPacketNum\t\t\t\t0x118\n#define\t\trPMAC_TxIdle\t\t\t\t\t0x11c\n#define\t\trPMAC_TxMACHeader0\t\t\t0x120\n#define\t\trPMAC_TxMACHeader1\t\t\t0x124\n#define\t\trPMAC_TxMACHeader2\t\t\t0x128\n#define\t\trPMAC_TxMACHeader3\t\t\t0x12c\n#define\t\trPMAC_TxMACHeader4\t\t\t0x130\n#define\t\trPMAC_TxMACHeader5\t\t\t0x134\n#define\t\trPMAC_TxDataType\t\t\t\t0x138\n#define\t\trPMAC_TxRandomSeed\t\t\t0x13c\n#define\t\trPMAC_CCKPLCPPreamble\t\t\t0x140\n#define\t\trPMAC_CCKPLCPHeader\t\t\t0x144\n#define\t\trPMAC_CCKCRC16\t\t\t\t0x148\n#define\t\trPMAC_OFDMRxCRC32OK\t\t\t0x170\n#define\t\trPMAC_OFDMRxCRC32Er\t\t\t0x174\n#define\t\trPMAC_OFDMRxParityEr\t\t\t0x178\n#define\t\trPMAC_OFDMRxCRC8Er\t\t\t0x17c\n#define\t\trPMAC_CCKCRxRC16Er\t\t\t0x180\n#define\t\trPMAC_CCKCRxRC32Er\t\t\t0x184\n#define\t\trPMAC_CCKCRxRC32OK\t\t\t0x188\n#define\t\trPMAC_TxStatus\t\t\t\t\t0x18c\n\n/*\n * 2. Page2(0x200)\n *\n * The following two definition are only used for USB interface. */\n#define\t\tRF_BB_CMD_ADDR\t\t\t\t0x02c0\t/* RF/BB read/write command address. */\n#define\t\tRF_BB_CMD_DATA\t\t\t\t0x02c4\t/* RF/BB read/write command data. */\n\n/*\n * 3. Page8(0x800)\n *   */\n#define\t\trFPGA0_RFMOD\t\t\t\t0x800\t/* RF mode & CCK TxSC */ /* RF BW Setting?? */\n\n#define\t\trFPGA0_TxInfo\t\t\t\t0x804\t/* Status report?? */\n#define\t\trFPGA0_PSDFunction\t\t\t0x808\n\n#define\t\trFPGA0_TxGainStage\t\t\t0x80c\t/* Set TX PWR init gain? */\n\n#define\t\trFPGA0_RFTiming1\t\t\t0x810\t/* Useless now */\n#define\t\trFPGA0_RFTiming2\t\t\t0x814\n\n#define\t\trFPGA0_XA_HSSIParameter1\t\t0x820\t/* RF 3 wire register */\n#define\t\trFPGA0_XA_HSSIParameter2\t\t0x824\n#define\t\trFPGA0_XB_HSSIParameter1\t\t0x828\n#define\t\trFPGA0_XB_HSSIParameter2\t\t0x82c\n#define\t\trTxAGC_B_Rate18_06\t\t\t\t0x830\n#define\t\trTxAGC_B_Rate54_24\t\t\t\t0x834\n#define\t\trTxAGC_B_CCK1_55_Mcs32\t\t0x838\n#define\t\trTxAGC_B_Mcs03_Mcs00\t\t\t0x83c\n\n#define\t\trTxAGC_B_Mcs07_Mcs04\t\t\t0x848\n#define\t\trTxAGC_B_Mcs11_Mcs08\t\t\t0x84c\n\n#define\t\trFPGA0_XA_LSSIParameter\t\t0x840\n#define\t\trFPGA0_XB_LSSIParameter\t\t0x844\n\n#define\t\trFPGA0_RFWakeUpParameter\t\t0x850\t/* Useless now */\n#define\t\trFPGA0_RFSleepUpParameter\t\t0x854\n\n#define\t\trFPGA0_XAB_SwitchControl\t\t0x858\t/* RF Channel switch */\n#define\t\trFPGA0_XCD_SwitchControl\t\t0x85c\n\n#define\t\trFPGA0_XA_RFInterfaceOE\t\t0x860\t/* RF Channel switch */\n#define\t\trFPGA0_XB_RFInterfaceOE\t\t0x864\n\n#define\t\trTxAGC_B_Mcs15_Mcs12\t\t\t0x868\n#define\t\trTxAGC_B_CCK11_A_CCK2_11\t\t0x86c\n\n#define\t\trFPGA0_XAB_RFInterfaceSW\t\t0x870\t/* RF Interface Software Control */\n#define\t\trFPGA0_XCD_RFInterfaceSW\t\t0x874\n\n#define\t\trFPGA0_XAB_RFParameter\t\t0x878\t/* RF Parameter */\n#define\t\trFPGA0_XCD_RFParameter\t\t0x87c\n\n#define\t\trFPGA0_AnalogParameter1\t\t0x880\t/* Crystal cap setting RF-R/W protection for parameter4?? */\n#define\t\trFPGA0_AnalogParameter2\t\t0x884\n#define\t\trFPGA0_AnalogParameter3\t\t0x888\t/* Useless now */\n#define\t\trFPGA0_AnalogParameter4\t\t0x88c\n\n#define\t\trFPGA0_XA_LSSIReadBack\t\t0x8a0\t/* Tranceiver LSSI Readback */\n#define\t\trFPGA0_XB_LSSIReadBack\t\t0x8a4\n#define\t\trFPGA0_XC_LSSIReadBack\t\t0x8a8\n#define\t\trFPGA0_XD_LSSIReadBack\t\t0x8ac\n\n#define\t\trFPGA0_PSDReport\t\t\t\t0x8b4\t/* Useless now */\n#define\t\tTransceiverA_HSPI_Readback\t0x8b8\t/* Transceiver A HSPI Readback */\n#define\t\tTransceiverB_HSPI_Readback\t0x8bc\t/* Transceiver B HSPI Readback */\n#define\t\trFPGA0_XAB_RFInterfaceRB\t\t0x8e0\t/* Useless now */ /* RF Interface Readback Value */\n#define\t\trFPGA0_XCD_RFInterfaceRB\t\t0x8e4\t/* Useless now */\n\n/*\n * 4. Page9(0x900)\n *   */\n#define\t\trFPGA1_RFMOD\t\t\t\t0x900\t/* RF mode & OFDM TxSC */ /* RF BW Setting?? */\n\n#define\t\trFPGA1_TxBlock\t\t\t\t0x904\t/* Useless now */\n#define\t\trFPGA1_DebugSelect\t\t\t0x908\t/* Useless now */\n#define\t\trFPGA1_TxInfo\t\t\t\t0x90c\t/* Useless now */ /* Status report?? */\n#define\trS0S1_PathSwitch\t\t\t0x948\n\n/*\n * 5. PageA(0xA00)\n *\n * Set Control channel to upper or lower. These settings are required only for 40MHz */\n#define\t\trCCK0_System\t\t\t\t0xa00\n\n#define\t\trCCK0_AFESetting\t\t\t0xa04\t/* Disable init gain now */ /* Select RX path by RSSI */\n#define\t\trCCK0_CCA\t\t\t\t\t0xa08\t/* Disable init gain now */ /* Init gain */\n\n#define\t\trCCK0_RxAGC1\t\t\t\t0xa0c\t/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */\n#define\t\trCCK0_RxAGC2\t\t\t\t0xa10\t/* AGC & DAGC */\n\n#define\t\trCCK0_RxHP\t\t\t\t\t0xa14\n\n#define\t\trCCK0_DSPParameter1\t\t0xa18\t/* Timing recovery & Channel estimation threshold */\n#define\t\trCCK0_DSPParameter2\t\t0xa1c\t/* SQ threshold */\n\n#define\t\trCCK0_TxFilter1\t\t\t\t0xa20\n#define\t\trCCK0_TxFilter2\t\t\t\t0xa24\n#define\t\trCCK0_DebugPort\t\t\t0xa28\t/* debug port and Tx filter3 */\n#define\t\trCCK0_FalseAlarmReport\t\t0xa2c\t/* 0xa2d\tuseless now 0xa30-a4f channel report */\n#define\t\trCCK0_TRSSIReport\t\t0xa50\n#define\t\trCCK0_RxReport            \t\t0xa54  /* 0xa57 */\n#define\t\trCCK0_FACounterLower      \t0xa5c  /* 0xa5b */\n#define\t\trCCK0_FACounterUpper      \t0xa58  /* 0xa5c\n *\n * PageB(0xB00)\n *   */\n#define\t\trPdp_AntA\t\t\t\t0xb00\n#define\t\trPdp_AntA_4\t\t\t\t0xb04\n#define\t\trConfig_Pmpd_AntA\t\t\t0xb28\n#define\t\trConfig_AntA\t\t\t\t0xb68\n#define\t\trConfig_AntB\t\t\t\t0xb6c\n#define\t\trPdp_AntB\t\t\t\t\t0xb70\n#define\t\trPdp_AntB_4\t\t\t\t0xb74\n#define\t\trConfig_Pmpd_AntB\t\t\t0xb98\n#define\t\trAPK\t\t\t\t\t\t0xbd8\n\n/*\n * 6. PageC(0xC00)\n *   */\n#define\t\trOFDM0_LSTF\t\t\t\t0xc00\n\n#define\t\trOFDM0_TRxPathEnable\t\t0xc04\n#define\t\trOFDM0_TRMuxPar\t\t\t0xc08\n#define\t\trOFDM0_TRSWIsolation\t\t0xc0c\n\n#define\t\trOFDM0_XARxAFE\t\t\t0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */\n#define\t\trOFDM0_XARxIQImbalance    \t0xc14  /* RxIQ imblance matrix */\n#define\t\trOFDM0_XBRxAFE\t\t0xc18\n#define\t\trOFDM0_XBRxIQImbalance\t0xc1c\n#define\t\trOFDM0_XCRxAFE\t\t0xc20\n#define\t\trOFDM0_XCRxIQImbalance\t0xc24\n#define\t\trOFDM0_XDRxAFE\t\t0xc28\n#define\t\trOFDM0_XDRxIQImbalance\t0xc2c\n\n#define\t\trOFDM0_RxDetector1\t\t\t0xc30  /* PD, BW & SBD\t */ /* DM tune init gain */\n#define\t\trOFDM0_RxDetector2\t\t\t0xc34  /* SBD & Fame Sync. */\n#define\t\trOFDM0_RxDetector3\t\t\t0xc38  /* Frame Sync. */\n#define\t\trOFDM0_RxDetector4\t\t\t0xc3c  /* PD, SBD, Frame Sync & Short-GI */\n\n#define\t\trOFDM0_RxDSP\t\t\t\t0xc40  /* Rx Sync Path */\n#define\t\trOFDM0_CFOandDAGC\t\t0xc44  /* CFO & DAGC */\n#define\t\trOFDM0_CCADropThreshold\t0xc48 /* CCA Drop threshold */\n#define\t\trOFDM0_ECCAThreshold\t\t0xc4c /* energy CCA */\n\n#define\t\trOFDM0_XAAGCCore1\t\t\t0xc50\t/* DIG */\n#define\t\trOFDM0_XAAGCCore2\t\t\t0xc54\n#define\t\trOFDM0_XBAGCCore1\t\t\t0xc58\n#define\t\trOFDM0_XBAGCCore2\t\t\t0xc5c\n#define\t\trOFDM0_XCAGCCore1\t\t\t0xc60\n#define\t\trOFDM0_XCAGCCore2\t\t\t0xc64\n#define\t\trOFDM0_XDAGCCore1\t\t\t0xc68\n#define\t\trOFDM0_XDAGCCore2\t\t\t0xc6c\n\n#define\t\trOFDM0_AGCParameter1\t\t\t0xc70\n#define\t\trOFDM0_AGCParameter2\t\t\t0xc74\n#define\t\trOFDM0_AGCRSSITable\t\t\t0xc78\n#define\t\trOFDM0_HTSTFAGC\t\t\t\t0xc7c\n\n#define\t\trOFDM0_XATxIQImbalance\t\t0xc80\t/* TX PWR TRACK and DIG */\n#define\t\trOFDM0_XATxAFE\t\t\t\t0xc84\n#define\t\trOFDM0_XBTxIQImbalance\t\t0xc88\n#define\t\trOFDM0_XBTxAFE\t\t\t\t0xc8c\n#define\t\trOFDM0_XCTxIQImbalance\t\t0xc90\n#define\t\trOFDM0_XCTxAFE\t\t\t0xc94\n#define\t\trOFDM0_XDTxIQImbalance\t\t0xc98\n#define\t\trOFDM0_XDTxAFE\t\t\t\t0xc9c\n\n#define\t\trOFDM0_RxIQExtAnta\t\t\t0xca0\n#define\t\trOFDM0_TxCoeff1\t\t\t\t0xca4\n#define\t\trOFDM0_TxCoeff2\t\t\t\t0xca8\n#define\t\trOFDM0_TxCoeff3\t\t\t\t0xcac\n#define\t\trOFDM0_TxCoeff4\t\t\t\t0xcb0\n#define\t\trOFDM0_TxCoeff5\t\t\t\t0xcb4\n#define\t\trOFDM0_TxCoeff6\t\t\t\t0xcb8\n#define\t\trOFDM0_RxHPParameter\t\t\t0xce0\n#define\t\trOFDM0_TxPseudoNoiseWgt\t\t0xce4\n#define\t\trOFDM0_FrameSync\t\t\t\t0xcf0\n#define\t\trOFDM0_DFSReport\t\t\t\t0xcf4\n\n/*\n * 7. PageD(0xD00)\n *   */\n#define\t\trOFDM1_LSTF\t\t\t\t\t0xd00\n#define\t\trOFDM1_TRxPathEnable\t\t\t0xd04\n\n#define\t\trOFDM1_CFO\t\t\t\t\t\t0xd08\t/* No setting now */\n#define\t\trOFDM1_CSI1\t\t\t\t\t0xd10\n#define\t\trOFDM1_SBD\t\t\t\t\t\t0xd14\n#define\t\trOFDM1_CSI2\t\t\t\t\t0xd18\n#define\t\trOFDM1_CFOTracking\t\t\t0xd2c\n#define\t\trOFDM1_TRxMesaure1\t\t\t0xd34\n#define\t\trOFDM1_IntfDet\t\t\t\t\t0xd3c\n#define\t\trOFDM1_PseudoNoiseStateAB\t\t0xd50\n#define\t\trOFDM1_PseudoNoiseStateCD\t\t0xd54\n#define\t\trOFDM1_RxPseudoNoiseWgt\t\t0xd58\n\n#define\t\trOFDM_PHYCounter1\t\t\t\t0xda0  /* cca, parity fail */\n#define\t\trOFDM_PHYCounter2\t\t\t\t0xda4  /* rate illegal, crc8 fail */\n#define\t\trOFDM_PHYCounter3\t\t\t\t0xda8  /* MCS not support */\n\n#define\t\trOFDM_ShortCFOAB\t\t\t\t0xdac\t/* No setting now */\n#define\t\trOFDM_ShortCFOCD\t\t\t\t0xdb0\n#define\t\trOFDM_LongCFOAB\t\t\t\t0xdb4\n#define\t\trOFDM_LongCFOCD\t\t\t\t0xdb8\n#define\t\trOFDM_TailCFOAB\t\t\t\t0xdbc\n#define\t\trOFDM_TailCFOCD\t\t\t\t0xdc0\n#define\t\trOFDM_PWMeasure1\t\t0xdc4\n#define\t\trOFDM_PWMeasure2\t\t0xdc8\n#define\t\trOFDM_BWReport\t\t\t\t0xdcc\n#define\t\trOFDM_AGCReport\t\t\t\t0xdd0\n#define\t\trOFDM_RxSNR\t\t\t\t\t0xdd4\n#define\t\trOFDM_RxEVMCSI\t\t\t\t0xdd8\n#define\t\trOFDM_SIGReport\t\t\t\t0xddc\n\n\n/*\n * 8. PageE(0xE00)\n *   */\n#define\t\trTxAGC_A_Rate18_06\t\t\t0xe00\n#define\t\trTxAGC_A_Rate54_24\t\t\t0xe04\n#define\t\trTxAGC_A_CCK1_Mcs32\t\t\t0xe08\n#define\t\trTxAGC_A_Mcs03_Mcs00\t\t\t0xe10\n#define\t\trTxAGC_A_Mcs07_Mcs04\t\t\t0xe14\n#define\t\trTxAGC_A_Mcs11_Mcs08\t\t\t0xe18\n#define\t\trTxAGC_A_Mcs15_Mcs12\t\t\t0xe1c\n\n#define\t\trFPGA0_IQK\t\t\t\t\t0xe28\n#define\t\trTx_IQK_Tone_A\t\t\t\t0xe30\n#define\t\trRx_IQK_Tone_A\t\t\t\t0xe34\n#define\t\trTx_IQK_PI_A\t\t\t\t\t0xe38\n#define\t\trRx_IQK_PI_A\t\t\t\t\t0xe3c\n\n#define\t\trTx_IQK\t\t\t\t\t\t0xe40\n#define\t\trRx_IQK\t\t\t\t\t\t0xe44\n#define\t\trIQK_AGC_Pts\t\t\t\t\t0xe48\n#define\t\trIQK_AGC_Rsp\t\t\t\t\t0xe4c\n#define\t\trTx_IQK_Tone_B\t\t\t\t0xe50\n#define\t\trRx_IQK_Tone_B\t\t\t\t0xe54\n#define\t\trTx_IQK_PI_B\t\t\t\t\t0xe58\n#define\t\trRx_IQK_PI_B\t\t\t\t\t0xe5c\n#define\t\trIQK_AGC_Cont\t\t\t\t0xe60\n\n#define\t\trBlue_Tooth\t\t\t\t\t0xe6c\n#define\t\trRx_Wait_CCA\t\t\t\t\t0xe70\n#define\t\trTx_CCK_RFON\t\t\t\t\t0xe74\n#define\t\trTx_CCK_BBON\t\t\t\t0xe78\n#define\t\trTx_OFDM_RFON\t\t\t\t0xe7c\n#define\t\trTx_OFDM_BBON\t\t\t\t0xe80\n#define\t\trTx_To_Rx\t\t\t\t\t0xe84\n#define\t\trTx_To_Tx\t\t\t\t\t0xe88\n#define\t\trRx_CCK\t\t\t\t\t\t0xe8c\n\n#define\t\trTx_Power_Before_IQK_A\t\t0xe94\n#define\t\trTx_Power_After_IQK_A\t\t\t0xe9c\n\n#define\t\trRx_Power_Before_IQK_A\t\t0xea0\n#define\t\trRx_Power_Before_IQK_A_2\t\t0xea4\n#define\t\trRx_Power_After_IQK_A\t\t\t0xea8\n#define\t\trRx_Power_After_IQK_A_2\t\t0xeac\n\n#define\t\trTx_Power_Before_IQK_B\t\t0xeb4\n#define\t\trTx_Power_After_IQK_B\t\t\t0xebc\n\n#define\t\trRx_Power_Before_IQK_B\t\t0xec0\n#define\t\trRx_Power_Before_IQK_B_2\t\t0xec4\n#define\t\trRx_Power_After_IQK_B\t\t\t0xec8\n#define\t\trRx_Power_After_IQK_B_2\t\t0xecc\n\n#define\t\trRx_OFDM\t\t\t\t\t0xed0\n#define\t\trRx_Wait_RIFS\t\t\t\t0xed4\n#define\t\trRx_TO_Rx\t\t\t\t\t0xed8\n#define\t\trStandby\t\t\t\t\t\t0xedc\n#define\t\trSleep\t\t\t\t\t\t0xee0\n#define\t\trPMPD_ANAEN\t\t\t\t0xeec\n\n/*\n * 7. RF Register 0x00-0x2E (RF 8256)\n * RF-0222D 0x00-3F\n *\n * Zebra1 */\n#define\t\trZebra1_HSSIEnable\t\t\t\t0x0\t/* Useless now */\n#define\t\trZebra1_TRxEnable1\t\t\t\t0x1\n#define\t\trZebra1_TRxEnable2\t\t\t\t0x2\n#define\t\trZebra1_AGC\t\t\t\t\t0x4\n#define\t\trZebra1_ChargePump\t\t\t0x5\n#define\t\trZebra1_Channel\t\t\t\t0x7\t/* RF channel switch */\n\n/* #endif */\n#define\t\trZebra1_TxGain\t\t\t\t\t0x8\t/* Useless now */\n#define\t\trZebra1_TxLPF\t\t\t\t\t0x9\n#define\t\trZebra1_RxLPF\t\t\t\t\t0xb\n#define\t\trZebra1_RxHPFCorner\t\t\t0xc\n\n/* Zebra4 */\n#define\t\trGlobalCtrl\t\t\t\t\t\t0\t/* Useless now */\n#define\t\trRTL8256_TxLPF\t\t\t\t\t19\n#define\t\trRTL8256_RxLPF\t\t\t\t\t11\n\n/* RTL8258 */\n#define\t\trRTL8258_TxLPF\t\t\t\t\t0x11\t/* Useless now */\n#define\t\trRTL8258_RxLPF\t\t\t\t\t0x13\n#define\t\trRTL8258_RSSILPF\t\t\t\t0xa\n\n/*\n * RL6052 Register definition\n *   */\n#define\t\tRF_AC\t\t\t\t\t\t0x00\t/*  */\n\n#define\t\tRF_IQADJ_G1\t\t\t\t0x01\t/*  */\n#define\t\tRF_IQADJ_G2\t\t\t\t0x02\t/*  */\n#define\t\tRF_BS_PA_APSET_G1_G4\t\t0x03\n#define\t\tRF_BS_PA_APSET_G5_G8\t\t0x04\n#define\t\tRF_POW_TRSW\t\t\t\t0x05\t/*  */\n\n#define\t\tRF_GAIN_RX\t\t\t\t\t0x06\t/*  */\n#define\t\tRF_GAIN_TX\t\t\t\t\t0x07\t/*  */\n\n#define\t\tRF_TXM_IDAC\t\t\t\t0x08\t/*  */\n#define\t\tRF_IPA_G\t\t\t\t\t0x09\t/*  */\n#define\t\tRF_TXBIAS_G\t\t\t\t0x0A\n#define\t\tRF_TXPA_AG\t\t\t\t\t0x0B\n#define\t\tRF_IPA_A\t\t\t\t\t0x0C\t/*  */\n#define\t\tRF_TXBIAS_A\t\t\t\t0x0D\n#define\t\tRF_BS_PA_APSET_G9_G11\t0x0E\n#define\t\tRF_BS_IQGEN\t\t\t\t0x0F\t/*  */\n\n#define\t\tRF_MODE1\t\t\t\t\t0x10\t/*  */\n#define\t\tRF_MODE2\t\t\t\t\t0x11\t/*  */\n\n#define\t\tRF_RX_AGC_HP\t\t\t\t0x12\t/*  */\n#define\t\tRF_TX_AGC\t\t\t\t\t0x13\t/*  */\n#define\t\tRF_BIAS\t\t\t\t\t\t0x14\t/*  */\n#define\t\tRF_IPA\t\t\t\t\t\t0x15\t/*  */\n#define\t\tRF_TXBIAS\t\t\t\t\t0x16\n#define\t\tRF_POW_ABILITY\t\t\t0x17\t/*  */\n#define\t\tRF_MODE_AG\t\t\t\t0x18\t/*  */\n#define\t\trRfChannel\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define\t\tRF_CHNLBW\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define\t\tRF_TOP\t\t\t\t\t\t0x19\t/*  */\n\n#define\t\tRF_RX_G1\t\t\t\t\t0x1A\t/*  */\n#define\t\tRF_RX_G2\t\t\t\t\t0x1B\t/*  */\n\n#define\t\tRF_RX_BB2\t\t\t\t\t0x1C\t/*  */\n#define\t\tRF_RX_BB1\t\t\t\t\t0x1D\t/*  */\n\n#define\t\tRF_RCK1\t\t\t\t\t0x1E\t/*  */\n#define\t\tRF_RCK2\t\t\t\t\t0x1F\t/*  */\n\n#define\t\tRF_TX_G1\t\t\t\t\t0x20\t/*  */\n#define\t\tRF_TX_G2\t\t\t\t\t0x21\t/*  */\n#define\t\tRF_TX_G3\t\t\t\t\t0x22\t/*  */\n\n#define\t\tRF_TX_BB1\t\t\t\t\t0x23\t/*  */\n\n#define\t\tRF_T_METER\t\t\t\t\t0x24\t/*  */\n\n#define\t\tRF_SYN_G1\t\t\t\t\t0x25\t/* RF TX Power control */\n#define\t\tRF_SYN_G2\t\t\t\t\t0x26\t/* RF TX Power control */\n#define\t\tRF_SYN_G3\t\t\t\t\t0x27\t/* RF TX Power control */\n#define\t\tRF_SYN_G4\t\t\t\t\t0x28\t/* RF TX Power control */\n#define\t\tRF_SYN_G5\t\t\t\t\t0x29\t/* RF TX Power control */\n#define\t\tRF_SYN_G6\t\t\t\t\t0x2A\t/* RF TX Power control */\n#define\t\tRF_SYN_G7\t\t\t\t\t0x2B\t/* RF TX Power control */\n#define\t\tRF_SYN_G8\t\t\t\t\t0x2C\t/* RF TX Power control */\n\n#define\t\tRF_RCK_OS\t\t\t\t\t0x30\t/* RF TX PA control */\n\n#define\t\tRF_TXPA_G1\t\t\t\t\t0x31\t/* RF TX PA control */\n#define\t\tRF_TXPA_G2\t\t\t\t\t0x32\t/* RF TX PA control */\n#define\t\tRF_TXPA_G3\t\t\t\t\t0x33\t/* RF TX PA control */\n#define\tRF_TX_BIAS_A\t\t\t\t0x35\n#define\tRF_TX_BIAS_D\t\t\t\t0x36\n#define\tRF_LOBF_9\t\t\t\t\t0x38\n#define \tRF_RXRF_A3\t\t\t\t\t0x3C\t/*\t */\n#define\tRF_TRSW\t\t\t\t\t0x3F\n\n#define\tRF_TXRF_A2\t\t\t\t\t0x41\n#define\tRF_TXPA_G4\t\t\t\t\t0x46\n#define\tRF_TXPA_A4\t\t\t\t\t0x4B\n#define\tRF_0x52\t\t\t\t\t0x52\n#define\t\tRF_RXG_MIX_SWBW\t\t\t\t0x87\n#define\t\tRF_DBG_LP_RX2\t\t\t\t0xDF\n#define\tRF_WE_LUT\t\t\t\t\t0xEF\n#define\tRF_S0S1\t\t\t\t\t0xB0\n\n#define RF_TX_GAIN_OFFSET_8188F(_val) (abs((_val)) | (((_val) > 0) ? BIT5 : 0))\n\n/*\n * Bit Mask\n *\n * 1. Page1(0x100) */\n#define\t\tbBBResetB\t\t\t\t\t\t0x100\t/* Useless now? */\n#define\t\tbGlobalResetB\t\t\t\t\t0x200\n#define\t\tbOFDMTxStart\t\t\t\t\t0x4\n#define\t\tbCCKTxStart\t\t\t\t\t\t0x8\n#define\t\tbCRC32Debug\t\t\t\t\t0x100\n#define\t\tbPMACLoopback\t\t\t\t\t0x10\n#define\t\tbTxLSIG\t\t\t\t\t\t\t0xffffff\n#define\t\tbOFDMTxRate\t\t\t\t\t0xf\n#define\t\tbOFDMTxReserved\t\t\t\t0x10\n#define\t\tbOFDMTxLength\t\t\t\t\t0x1ffe0\n#define\t\tbOFDMTxParity\t\t\t\t\t0x20000\n#define\t\tbTxHTSIG1\t\t\t\t\t\t0xffffff\n#define\t\tbTxHTMCSRate\t\t\t\t\t0x7f\n#define\t\tbTxHTBW\t\t\t\t\t\t0x80\n#define\t\tbTxHTLength\t\t\t\t\t0xffff00\n#define\t\tbTxHTSIG2\t\t\t\t\t\t0xffffff\n#define\t\tbTxHTSmoothing\t\t\t\t\t0x1\n#define\t\tbTxHTSounding\t\t\t\t\t0x2\n#define\t\tbTxHTReserved\t\t\t\t\t0x4\n#define\t\tbTxHTAggreation\t\t\t\t0x8\n#define\t\tbTxHTSTBC\t\t\t\t\t\t0x30\n#define\t\tbTxHTAdvanceCoding\t\t\t0x40\n#define\t\tbTxHTShortGI\t\t\t\t\t0x80\n#define\t\tbTxHTNumberHT_LTF\t\t\t0x300\n#define\t\tbTxHTCRC8\t\t\t\t\t\t0x3fc00\n#define\t\tbCounterReset\t\t\t\t\t0x10000\n#define\t\tbNumOfOFDMTx\t\t\t\t\t0xffff\n#define\t\tbNumOfCCKTx\t\t\t\t\t0xffff0000\n#define\t\tbTxIdleInterval\t\t\t\t\t0xffff\n#define\t\tbOFDMService\t\t\t\t\t0xffff0000\n#define\t\tbTxMACHeader\t\t\t\t\t0xffffffff\n#define\t\tbTxDataInit\t\t\t\t\t\t0xff\n#define\t\tbTxHTMode\t\t\t\t\t\t0x100\n#define\t\tbTxDataType\t\t\t\t\t0x30000\n#define\t\tbTxRandomSeed\t\t\t\t\t0xffffffff\n#define\t\tbCCKTxPreamble\t\t\t\t\t0x1\n#define\t\tbCCKTxSFD\t\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxSIG\t\t\t\t\t\t0xff\n#define\t\tbCCKTxService\t\t\t\t\t0xff00\n#define\t\tbCCKLengthExt\t\t\t\t\t0x8000\n#define\t\tbCCKTxLength\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxCRC16\t\t\t\t\t0xffff\n#define\t\tbCCKTxStatus\t\t\t\t\t0x1\n#define\t\tbOFDMTxStatus\t\t\t\t\t0x2\n\n#define\t\tIS_BB_REG_OFFSET_92S(_Offset)\t\t((_Offset >= 0x800) && (_Offset <= 0xfff))\n\n/* 2. Page8(0x800) */\n#define\t\tbRFMOD\t\t\t\t\t\t\t0x1\t/* Reg 0x800 rFPGA0_RFMOD */\n#define\t\tbJapanMode\t\t\t\t\t\t0x2\n#define\t\tbCCKTxSC\t\t\t\t\t\t0x30\n#define\t\tbCCKEn\t\t\t\t\t\t\t0x1000000\n#define\t\tbOFDMEn\t\t\t\t\t\t0x2000000\n\n#define\t\tbOFDMRxADCPhase           \t\t0x10000\t/* Useless now */\n#define\t\tbOFDMTxDACPhase\t\t0x40000\n#define\t\tbXATxAGC\t\t\t0x3f\n\n#define\t\tbAntennaSelect\t\t0x0300\n\n#define\t\tbXBTxAGC                  \t\t\t0xf00\t/* Reg 80c rFPGA0_TxGainStage */\n#define\t\tbXCTxAGC\t\t\t0xf000\n#define\t\tbXDTxAGC\t\t\t0xf0000\n\n#define\t\tbPAStart                  \t\t\t0xf0000000\t/* Useless now */\n#define\t\tbTRStart\t\t\t0x00f00000\n#define\t\tbRFStart\t\t\t0x0000f000\n#define\t\tbBBStart\t\t\t0x000000f0\n#define\t\tbBBCCKStart\t\t0x0000000f\n#define\t\tbPAEnd                    \t\t\t0xf          /* Reg0x814 */\n#define\t\tbTREnd\t\t\t0x0f000000\n#define\t\tbRFEnd\t\t\t0x000f0000\n#define\t\tbCCAMask                  \t\t\t0x000000f0   /* T2R */\n#define\t\tbR2RCCAMask\t\t0x00000f00\n#define\t\tbHSSI_R2TDelay\t\t0xf8000000\n#define\t\tbHSSI_T2RDelay\t\t0xf80000\n#define\t\tbContTxHSSI               \t\t0x400     /* chane gain at continue Tx */\n#define\t\tbIGFromCCK\t\t0x200\n#define\t\tbAGCAddress\t\t0x3f\n#define\t\tbRxHPTx\t\t\t0x7000\n#define\t\tbRxHPT2R\t\t\t0x38000\n#define\t\tbRxHPCCKIni\t\t0xc0000\n#define\t\tbAGCTxCode\t\t0xc00000\n#define\t\tbAGCRxCode\t\t0x300000\n\n#define\t\tb3WireDataLength          \t\t0x800\t/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */\n#define\t\tb3WireAddressLength\t\t0x400\n\n#define\t\tb3WireRFPowerDown         \t\t0x1\t/* Useless now\n * #define bHWSISelect\t\t0x8 */\n#define\t\tb5GPAPEPolarity\t\t0x40000000\n#define\t\tb2GPAPEPolarity\t\t0x80000000\n#define\t\tbRFSW_TxDefaultAnt\t\t0x3\n#define\t\tbRFSW_TxOptionAnt\t\t0x30\n#define\t\tbRFSW_RxDefaultAnt\t\t0x300\n#define\t\tbRFSW_RxOptionAnt\t\t0x3000\n#define\t\tbRFSI_3WireData\t\t0x1\n#define\t\tbRFSI_3WireClock\t\t0x2\n#define\t\tbRFSI_3WireLoad\t\t0x4\n#define\t\tbRFSI_3WireRW\t\t0x8\n#define\t\tbRFSI_3Wire\t\t\t0xf\n\n#define\t\tbRFSI_RFENV               \t\t0x10\t/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */\n\n#define\t\tbRFSI_TRSW                \t\t0x20\t/* Useless now */\n#define\t\tbRFSI_TRSWB\t\t0x40\n#define\t\tbRFSI_ANTSW\t\t0x100\n#define\t\tbRFSI_ANTSWB\t\t0x200\n#define\t\tbRFSI_PAPE\t\t\t0x400\n#define\t\tbRFSI_PAPE5G\t\t0x800\n#define\t\tbBandSelect\t\t\t0x1\n#define\t\tbHTSIG2_GI\t\t\t0x80\n#define\t\tbHTSIG2_Smoothing\t\t0x01\n#define\t\tbHTSIG2_Sounding\t\t0x02\n#define\t\tbHTSIG2_Aggreaton\t\t0x08\n#define\t\tbHTSIG2_STBC\t\t0x30\n#define\t\tbHTSIG2_AdvCoding\t\t0x40\n#define\t\tbHTSIG2_NumOfHTLTF\t0x300\n#define\t\tbHTSIG2_CRC8\t\t0x3fc\n#define\t\tbHTSIG1_MCS\t\t0x7f\n#define\t\tbHTSIG1_BandWidth\t\t0x80\n#define\t\tbHTSIG1_HTLength\t\t0xffff\n#define\t\tbLSIG_Rate\t\t\t0xf\n#define\t\tbLSIG_Reserved\t\t0x10\n#define\t\tbLSIG_Length\t\t0x1fffe\n#define\t\tbLSIG_Parity\t\t\t0x20\n#define\t\tbCCKRxPhase\t\t0x4\n\n#define\t\tbLSSIReadAddress          \t\t0x7f800000   /* T65 RF */\n\n#define\t\tbLSSIReadEdge             \t\t0x80000000   /* LSSI \"Read\" edge signal */\n\n#define\t\tbLSSIReadBackData         \t\t0xfffff\t\t/* T65 RF */\n\n#define\t\tbLSSIReadOKFlag           \t\t0x1000\t/* Useless now */\n#define\t\tbCCKSampleRate            \t\t0x8       /* 0: 44MHz, 1:88MHz      \t\t */\n#define\t\tbRegulator0Standby\t\t0x1\n#define\t\tbRegulatorPLLStandby\t\t0x2\n#define\t\tbRegulator1Standby\t\t0x4\n#define\t\tbPLLPowerUp\t\t0x8\n#define\t\tbDPLLPowerUp\t\t0x10\n#define\t\tbDA10PowerUp\t\t0x20\n#define\t\tbAD7PowerUp\t\t0x200\n#define\t\tbDA6PowerUp\t\t0x2000\n#define\t\tbXtalPowerUp\t\t0x4000\n#define\t\tb40MDClkPowerUP\t\t0x8000\n#define\t\tbDA6DebugMode\t\t0x20000\n#define\t\tbDA6Swing\t\t\t0x380000\n\n#define\t\tbADClkPhase               \t\t0x4000000\t/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */\n\n#define\t\tb80MClkDelay              \t\t0x18000000\t/* Useless */\n#define\t\tbAFEWatchDogEnable\t\t0x20000000\n\n#define\t\tbXtalCap01                \t\t\t0xc0000000\t/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */\n#define\t\tbXtalCap23\t\t\t0x3\n#define\t\tbXtalCap92x\t\t\t\t\t0x0f000000\n#define\t\tbXtalCap\t\t\t0x0f000000\n\n#define\t\tbIntDifClkEnable          \t\t0x400\t/* Useless */\n#define\t\tbExtSigClkEnable\t\t0x800\n#define\t\tbBandgapMbiasPowerUp\t0x10000\n#define\t\tbAD11SHGain\t\t0xc0000\n#define\t\tbAD11InputRange\t\t0x700000\n#define\t\tbAD11OPCurrent\t\t0x3800000\n#define\t\tbIPathLoopback\t\t0x4000000\n#define\t\tbQPathLoopback\t\t0x8000000\n#define\t\tbAFELoopback\t\t0x10000000\n#define\t\tbDA10Swing\t\t0x7e0\n#define\t\tbDA10Reverse\t\t0x800\n#define\t\tbDAClkSource\t\t0x1000\n#define\t\tbAD7InputRange\t\t0x6000\n#define\t\tbAD7Gain\t\t\t0x38000\n#define\t\tbAD7OutputCMMode\t\t0x40000\n#define\t\tbAD7InputCMMode\t\t0x380000\n#define\t\tbAD7Current\t\t\t0xc00000\n#define\t\tbRegulatorAdjust\t\t0x7000000\n#define\t\tbAD11PowerUpAtTx\t\t0x1\n#define\t\tbDA10PSAtTx\t\t0x10\n#define\t\tbAD11PowerUpAtRx\t\t0x100\n#define\t\tbDA10PSAtRx\t\t0x1000\n#define\t\tbCCKRxAGCFormat\t\t0x200\n#define\t\tbPSDFFTSamplepPoint\t\t0xc000\n#define\t\tbPSDAverageNum\t\t0x3000\n#define\t\tbIQPathControl\t\t0xc00\n#define\t\tbPSDFreq\t\t\t0x3ff\n#define\t\tbPSDAntennaPath\t\t0x30\n#define\t\tbPSDIQSwitch\t\t0x40\n#define\t\tbPSDRxTrigger\t\t0x400000\n#define\t\tbPSDTxTrigger\t\t0x80000000\n#define\t\tbPSDSineToneScale\t\t0x7f000000\n#define\t\tbPSDReport\t\t\t0xffff\n\n/* 3. Page9(0x900) */\n#define\t\tbOFDMTxSC                 \t\t0x30000000\t/* Useless */\n#define\t\tbCCKTxOn\t\t\t0x1\n#define\t\tbOFDMTxOn\t\t0x2\n#define\t\tbDebugPage                \t\t0xfff  /* reset debug page and also HWord, LWord */\n#define\t\tbDebugItem                \t\t0xff   /* reset debug page and LWord */\n#define\t\tbAntL\t\t\t0x10\n#define\t\tbAntNonHT\t\t\t\t0x100\n#define\t\tbAntHT1\t\t\t0x1000\n#define\t\tbAntHT2\t\t\t0x10000\n#define\t\tbAntHT1S1\t\t\t0x100000\n#define\t\tbAntNonHTS1\t\t0x1000000\n\n/* 4. PageA(0xA00) */\n#define\t\tbCCKBBMode\t\t\t\t0x3\t/* Useless */\n#define\t\tbCCKTxPowerSaving\t\t0x80\n#define\t\tbCCKRxPowerSaving\t\t0x40\n\n#define\t\tbCCKSideBand\t\t\t0x10\t/* Reg 0xa00 rCCK0_System 20/40 switch */\n\n#define\t\tbCCKScramble\t\t\t0x8\t/* Useless */\n#define\t\tbCCKAntDiversity\t\t0x8000\n#define\t\tbCCKCarrierRecovery\t\t0x4000\n#define\t\tbCCKTxRate\t\t\t\t0x3000\n#define\t\tbCCKDCCancel\t\t\t0x0800\n#define\t\tbCCKISICancel\t\t\t0x0400\n#define\t\tbCCKMatchFilter\t\t\t0x0200\n#define\t\tbCCKEqualizer\t\t\t0x0100\n#define\t\tbCCKPreambleDetect\t\t0x800000\n#define\t\tbCCKFastFalseCCA\t\t0x400000\n#define\t\tbCCKChEstStart\t\t\t0x300000\n#define\t\tbCCKCCACount\t\t\t0x080000\n#define\t\tbCCKcs_lim\t\t\t\t0x070000\n#define\t\tbCCKBistMode\t\t\t0x80000000\n#define\t\tbCCKCCAMask\t\t\t0x40000000\n#define\t\tbCCKTxDACPhase\t\t0x4\n#define\t\tbCCKRxADCPhase\t\t0x20000000   /* r_rx_clk */\n#define\t\tbCCKr_cp_mode0\t\t0x0100\n#define\t\tbCCKTxDCOffset\t\t\t0xf0\n#define\t\tbCCKRxDCOffset\t\t\t0xf\n#define\t\tbCCKCCAMode\t\t\t0xc000\n#define\t\tbCCKFalseCS_lim\t\t\t0x3f00\n#define\t\tbCCKCS_ratio\t\t\t0xc00000\n#define\t\tbCCKCorgBit_sel\t\t\t0x300000\n#define\t\tbCCKPD_lim\t\t\t\t0x0f0000\n#define\t\tbCCKNewCCA\t\t\t0x80000000\n#define\t\tbCCKRxHPofIG\t\t\t0x8000\n#define\t\tbCCKRxIG\t\t\t\t0x7f00\n#define\t\tbCCKLNAPolarity\t\t\t0x800000\n#define\t\tbCCKRx1stGain\t\t\t0x7f0000\n#define\t\tbCCKRFExtend\t\t\t0x20000000 /* CCK Rx Iinital gain polarity */\n#define\t\tbCCKRxAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKRxAGCSatCount\t\t0xe0\n#define\t\tbCCKRxRFSettle\t\t\t0x1f       /* AGCsamp_dly */\n#define\t\tbCCKFixedRxAGC\t\t\t0x8000\n/* #define bCCKRxAGCFormat\t\t0x4000 */   /* remove to HSSI register 0x824 */\n#define\t\tbCCKAntennaPolarity\t\t0x2000\n#define\t\tbCCKTxFilterType\t\t0x0c00\n#define\t\tbCCKRxAGCReportType\t0x0300\n#define\t\tbCCKRxDAGCEn\t\t\t0x80000000\n#define\t\tbCCKRxDAGCPeriod\t\t0x20000000\n#define\t\tbCCKRxDAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKTimingRecovery\t\t0x800000\n#define\t\tbCCKTxC0\t\t\t\t0x3f0000\n#define\t\tbCCKTxC1\t\t\t\t0x3f000000\n#define\t\tbCCKTxC2\t\t\t\t0x3f\n#define\t\tbCCKTxC3\t\t\t\t0x3f00\n#define\t\tbCCKTxC4\t\t\t\t0x3f0000\n#define\t\tbCCKTxC5\t\t\t\t0x3f000000\n#define\t\tbCCKTxC6\t\t\t\t0x3f\n#define\t\tbCCKTxC7\t\t\t\t0x3f00\n#define\t\tbCCKDebugPort\t\t\t0xff0000\n#define\t\tbCCKDACDebug\t\t\t0x0f000000\n#define\t\tbCCKFalseAlarmEnable\t0x8000\n#define\t\tbCCKFalseAlarmRead\t\t0x4000\n#define\t\tbCCKTRSSI\t\t\t\t0x7f\n#define\t\tbCCKRxAGCReport\t\t0xfe\n#define\t\tbCCKRxReport_AntSel\t0x80000000\n#define\t\tbCCKRxReport_MFOff\t\t0x40000000\n#define\t\tbCCKRxRxReport_SQLoss\t0x20000000\n#define\t\tbCCKRxReport_Pktloss\t0x10000000\n#define\t\tbCCKRxReport_Lockedbit\t0x08000000\n#define\t\tbCCKRxReport_RateError\t0x04000000\n#define\t\tbCCKRxReport_RxRate\t0x03000000\n#define\t\tbCCKRxFACounterLower\t0xff\n#define\t\tbCCKRxFACounterUpper\t0xff000000\n#define\t\tbCCKRxHPAGCStart\t\t0xe000\n#define\t\tbCCKRxHPAGCFinal\t\t0x1c00\n#define\t\tbCCKRxFalseAlarmEnable\t0x8000\n#define\t\tbCCKFACounterFreeze\t0x4000\n#define\t\tbCCKTxPathSel\t\t\t0x10000000\n#define\t\tbCCKDefaultRxPath\t\t0xc000000\n#define\t\tbCCKOptionRxPath\t\t0x3000000\n\n/* 5. PageC(0xC00) */\n#define\t\tbNumOfSTF\t\t\t\t0x3\t/* Useless */\n#define\t\tbShift_L\t\t\t\t\t0xc0\n#define\t\tbGI_TH\t\t\t\t\t0xc\n#define\t\tbRxPathA\t\t\t\t0x1\n#define\t\tbRxPathB\t\t\t\t0x2\n#define\t\tbRxPathC\t\t\t\t0x4\n#define\t\tbRxPathD\t\t\t\t0x8\n#define\t\tbTxPathA\t\t\t\t0x1\n#define\t\tbTxPathB\t\t\t\t0x2\n#define\t\tbTxPathC\t\t\t\t0x4\n#define\t\tbTxPathD\t\t\t\t0x8\n#define\t\tbTRSSIFreq\t\t\t\t0x200\n#define\t\tbADCBackoff\t\t\t\t0x3000\n#define\t\tbDFIRBackoff\t\t\t0xc000\n#define\t\tbTRSSILatchPhase\t\t0x10000\n#define\t\tbRxIDCOffset\t\t\t0xff\n#define\t\tbRxQDCOffset\t\t\t0xff00\n#define\t\tbRxDFIRMode\t\t\t0x1800000\n#define\t\tbRxDCNFType\t\t\t0xe000000\n#define\t\tbRXIQImb_A\t\t\t\t0x3ff\n#define\t\tbRXIQImb_B\t\t\t\t0xfc00\n#define\t\tbRXIQImb_C\t\t\t\t0x3f0000\n#define\t\tbRXIQImb_D\t\t\t\t0xffc00000\n#define\t\tbDC_dc_Notch\t\t\t0x60000\n#define\t\tbRxNBINotch\t\t\t0x1f000000\n#define\t\tbPD_TH\t\t\t\t\t0xf\n#define\t\tbPD_TH_Opt2\t\t\t0xc000\n#define\t\tbPWED_TH\t\t\t\t0x700\n#define\t\tbIfMF_Win_L\t\t\t0x800\n#define\t\tbPD_Option\t\t\t\t0x1000\n#define\t\tbMF_Win_L\t\t\t\t0xe000\n#define\t\tbBW_Search_L\t\t\t0x30000\n#define\t\tbwin_enh_L\t\t\t\t0xc0000\n#define\t\tbBW_TH\t\t\t\t\t0x700000\n#define\t\tbED_TH2\t\t\t\t0x3800000\n#define\t\tbBW_option\t\t\t\t0x4000000\n#define\t\tbRatio_TH\t\t\t\t0x18000000\n#define\t\tbWindow_L\t\t\t\t0xe0000000\n#define\t\tbSBD_Option\t\t\t\t0x1\n#define\t\tbFrame_TH\t\t\t\t0x1c\n#define\t\tbFS_Option\t\t\t\t0x60\n#define\t\tbDC_Slope_check\t\t0x80\n#define\t\tbFGuard_Counter_DC_L\t0xe00\n#define\t\tbFrame_Weight_Short\t0x7000\n#define\t\tbSub_Tune\t\t\t\t0xe00000\n#define\t\tbFrame_DC_Length\t\t0xe000000\n#define\t\tbSBD_start_offset\t\t0x30000000\n#define\t\tbFrame_TH_2\t\t\t0x7\n#define\t\tbFrame_GI2_TH\t\t\t0x38\n#define\t\tbGI2_Sync_en\t\t\t0x40\n#define\t\tbSarch_Short_Early\t\t0x300\n#define\t\tbSarch_Short_Late\t\t0xc00\n#define\t\tbSarch_GI2_Late\t\t0x70000\n#define\t\tbCFOAntSum\t\t\t\t0x1\n#define\t\tbCFOAcc\t\t\t\t0x2\n#define\t\tbCFOStartOffset\t\t\t0xc\n#define\t\tbCFOLookBack\t\t\t0x70\n#define\t\tbCFOSumWeight\t\t\t0x80\n#define\t\tbDAGCEnable\t\t\t0x10000\n#define\t\tbTXIQImb_A\t\t\t\t0x3ff\n#define\t\tbTXIQImb_B\t\t\t\t0xfc00\n#define\t\tbTXIQImb_C\t\t\t\t0x3f0000\n#define\t\tbTXIQImb_D\t\t\t\t0xffc00000\n#define\t\tbTxIDCOffset\t\t\t0xff\n#define\t\tbTxQDCOffset\t\t\t0xff00\n#define\t\tbTxDFIRMode\t\t\t0x10000\n#define\t\tbTxPesudoNoiseOn\t\t0x4000000\n#define\t\tbTxPesudoNoise_A\t\t0xff\n#define\t\tbTxPesudoNoise_B\t\t0xff00\n#define\t\tbTxPesudoNoise_C\t\t0xff0000\n#define\t\tbTxPesudoNoise_D\t\t0xff000000\n#define\t\tbCCADropOption\t\t\t0x20000\n#define\t\tbCCADropThres\t\t\t0xfff00000\n#define\t\tbEDCCA_H\t\t\t\t0xf\n#define\t\tbEDCCA_L\t\t\t\t0xf0\n#define\t\tbLambda_ED\t\t\t0x300\n#define\t\tbRxInitialGain\t\t\t0x7f\n#define\t\tbRxAntDivEn\t\t\t\t0x80\n#define\t\tbRxAGCAddressForLNA\t0x7f00\n#define\t\tbRxHighPowerFlow\t\t0x8000\n#define\t\tbRxAGCFreezeThres\t\t0xc0000\n#define\t\tbRxFreezeStep_AGC1\t0x300000\n#define\t\tbRxFreezeStep_AGC2\t0xc00000\n#define\t\tbRxFreezeStep_AGC3\t0x3000000\n#define\t\tbRxFreezeStep_AGC0\t0xc000000\n#define\t\tbRxRssi_Cmp_En\t\t\t0x10000000\n#define\t\tbRxQuickAGCEn\t\t\t0x20000000\n#define\t\tbRxAGCFreezeThresMode\t0x40000000\n#define\t\tbRxOverFlowCheckType\t0x80000000\n#define\t\tbRxAGCShift\t\t\t\t0x7f\n#define\t\tbTRSW_Tri_Only\t\t\t0x80\n#define\t\tbPowerThres\t\t\t0x300\n#define\t\tbRxAGCEn\t\t\t\t0x1\n#define\t\tbRxAGCTogetherEn\t\t0x2\n#define\t\tbRxAGCMin\t\t\t\t0x4\n#define\t\tbRxHP_Ini\t\t\t\t0x7\n#define\t\tbRxHP_TRLNA\t\t\t0x70\n#define\t\tbRxHP_RSSI\t\t\t\t0x700\n#define\t\tbRxHP_BBP1\t\t\t\t0x7000\n#define\t\tbRxHP_BBP2\t\t\t\t0x70000\n#define\t\tbRxHP_BBP3\t\t\t\t0x700000\n#define\t\tbRSSI_H\t\t\t\t\t0x7f0000     /* the threshold for high power */\n#define\t\tbRSSI_Gen\t\t\t\t0x7f000000   /* the threshold for ant diversity */\n#define\t\tbRxSettle_TRSW\t\t\t0x7\n#define\t\tbRxSettle_LNA\t\t\t0x38\n#define\t\tbRxSettle_RSSI\t\t\t0x1c0\n#define\t\tbRxSettle_BBP\t\t\t0xe00\n#define\t\tbRxSettle_RxHP\t\t\t0x7000\n#define\t\tbRxSettle_AntSW_RSSI\t0x38000\n#define\t\tbRxSettle_AntSW\t\t0xc0000\n#define\t\tbRxProcessTime_DAGC\t0x300000\n#define\t\tbRxSettle_HSSI\t\t\t0x400000\n#define\t\tbRxProcessTime_BBPPW\t0x800000\n#define\t\tbRxAntennaPowerShift\t0x3000000\n#define\t\tbRSSITableSelect\t\t0xc000000\n#define\t\tbRxHP_Final\t\t\t\t0x7000000\n#define\t\tbRxHTSettle_BBP\t\t\t0x7\n#define\t\tbRxHTSettle_HSSI\t\t0x8\n#define\t\tbRxHTSettle_RxHP\t\t0x70\n#define\t\tbRxHTSettle_BBPPW\t\t0x80\n#define\t\tbRxHTSettle_Idle\t\t0x300\n#define\t\tbRxHTSettle_Reserved\t0x1c00\n#define\t\tbRxHTRxHPEn\t\t\t0x8000\n#define\t\tbRxHTAGCFreezeThres\t0x30000\n#define\t\tbRxHTAGCTogetherEn\t0x40000\n#define\t\tbRxHTAGCMin\t\t\t0x80000\n#define\t\tbRxHTAGCEn\t\t\t\t0x100000\n#define\t\tbRxHTDAGCEn\t\t\t0x200000\n#define\t\tbRxHTRxHP_BBP\t\t\t0x1c00000\n#define\t\tbRxHTRxHP_Final\t\t0xe0000000\n#define\t\tbRxPWRatioTH\t\t\t0x3\n#define\t\tbRxPWRatioEn\t\t\t0x4\n#define\t\tbRxMFHold\t\t\t\t0x3800\n#define\t\tbRxPD_Delay_TH1\t\t0x38\n#define\t\tbRxPD_Delay_TH2\t\t0x1c0\n#define\t\tbRxPD_DC_COUNT_MAX\t0x600\n/* #define bRxMF_Hold               0x3800 */\n#define\t\tbRxPD_Delay_TH\t\t\t0x8000\n#define\t\tbRxProcess_Delay\t\t0xf0000\n#define\t\tbRxSearchrange_GI2_Early\t0x700000\n#define\t\tbRxFrame_Guard_Counter_L\t0x3800000\n#define\t\tbRxSGI_Guard_L\t\t\t0xc000000\n#define\t\tbRxSGI_Search_L\t\t0x30000000\n#define\t\tbRxSGI_TH\t\t\t\t0xc0000000\n#define\t\tbDFSCnt0\t\t\t\t0xff\n#define\t\tbDFSCnt1\t\t\t\t0xff00\n#define\t\tbDFSFlag\t\t\t\t0xf0000\n#define\t\tbMFWeightSum\t\t\t0x300000\n#define\t\tbMinIdxTH\t\t\t\t0x7f000000\n#define\t\tbDAFormat\t\t\t\t0x40000\n#define\t\tbTxChEmuEnable\t\t0x01000000\n#define\t\tbTRSWIsolation_A\t\t0x7f\n#define\t\tbTRSWIsolation_B\t\t0x7f00\n#define\t\tbTRSWIsolation_C\t\t0x7f0000\n#define\t\tbTRSWIsolation_D\t\t0x7f000000\n#define\t\tbExtLNAGain\t\t\t\t0x7c00\n\n/* 6. PageE(0xE00) */\n#define\t\tbSTBCEn\t\t\t\t0x4\t/* Useless */\n#define\t\tbAntennaMapping\t\t0x10\n#define\t\tbNss\t\t\t\t\t0x20\n#define\t\tbCFOAntSumD\t\t\t0x200\n#define\t\tbPHYCounterReset\t\t0x8000000\n#define\t\tbCFOReportGet\t\t\t0x4000000\n#define\t\tbOFDMContinueTx\t\t0x10000000\n#define\t\tbOFDMSingleCarrier\t\t0x20000000\n#define\t\tbOFDMSingleTone\t\t0x40000000\n/* #define bRxPath1                 0x01 */\n/* #define bRxPath2                 0x02 */\n/* #define bRxPath3                 0x04 */\n/* #define bRxPath4                 0x08 */\n/* #define bTxPath1                 0x10 */\n/* #define bTxPath2                 0x20 */\n#define\t\tbHTDetect\t\t\t0x100\n#define\t\tbCFOEn\t\t\t\t0x10000\n#define\t\tbCFOValue\t\t\t0xfff00000\n#define\t\tbSigTone_Re\t\t0x3f\n#define\t\tbSigTone_Im\t\t0x7f00\n#define\t\tbCounter_CCA\t\t0xffff\n#define\t\tbCounter_ParityFail\t0xffff0000\n#define\t\tbCounter_RateIllegal\t\t0xffff\n#define\t\tbCounter_CRC8Fail\t0xffff0000\n#define\t\tbCounter_MCSNoSupport\t0xffff\n#define\t\tbCounter_FastSync\t0xffff\n#define\t\tbShortCFO\t\t\t0xfff\n#define\t\tbShortCFOTLength\t12   /* total */\n#define\t\tbShortCFOFLength\t11   /* fraction */\n#define\t\tbLongCFO\t\t\t0x7ff\n#define\t\tbLongCFOTLength\t11\n#define\t\tbLongCFOFLength\t11\n#define\t\tbTailCFO\t\t\t0x1fff\n#define\t\tbTailCFOTLength\t\t13\n#define\t\tbTailCFOFLength\t\t12\n#define\t\tbmax_en_pwdB\t\t0xffff\n#define\t\tbCC_power_dB\t\t0xffff0000\n#define\t\tbnoise_pwdB\t\t0xffff\n#define\t\tbPowerMeasTLength\t10\n#define\t\tbPowerMeasFLength\t3\n#define\t\tbRx_HT_BW\t\t\t0x1\n#define\t\tbRxSC\t\t\t\t0x6\n#define\t\tbRx_HT\t\t\t\t0x8\n#define\t\tbNB_intf_det_on\t\t0x1\n#define\t\tbIntf_win_len_cfg\t0x30\n#define\t\tbNB_Intf_TH_cfg\t\t0x1c0\n#define\t\tbRFGain\t\t\t\t0x3f\n#define\t\tbTableSel\t\t\t0x40\n#define\t\tbTRSW\t\t\t\t0x80\n#define\t\tbRxSNR_A\t\t\t0xff\n#define\t\tbRxSNR_B\t\t\t0xff00\n#define\t\tbRxSNR_C\t\t\t0xff0000\n#define\t\tbRxSNR_D\t\t\t0xff000000\n#define\t\tbSNREVMTLength\t\t8\n#define\t\tbSNREVMFLength\t\t1\n#define\t\tbCSI1st\t\t\t\t0xff\n#define\t\tbCSI2nd\t\t\t\t0xff00\n#define\t\tbRxEVM1st\t\t\t0xff0000\n#define\t\tbRxEVM2nd\t\t\t0xff000000\n#define\t\tbSIGEVM\t\t\t0xff\n#define\t\tbPWDB\t\t\t\t0xff00\n#define\t\tbSGIEN\t\t\t\t0x10000\n\n#define\t\tbSFactorQAM1\t\t0xf\t/* Useless */\n#define\t\tbSFactorQAM2\t\t0xf0\n#define\t\tbSFactorQAM3\t\t0xf00\n#define\t\tbSFactorQAM4\t\t0xf000\n#define\t\tbSFactorQAM5\t\t0xf0000\n#define\t\tbSFactorQAM6\t\t0xf0000\n#define\t\tbSFactorQAM7\t\t0xf00000\n#define\t\tbSFactorQAM8\t\t0xf000000\n#define\t\tbSFactorQAM9\t\t0xf0000000\n#define\t\tbCSIScheme\t\t\t0x100000\n\n#define\t\tbNoiseLvlTopSet\t\t0x3\t/* Useless */\n#define\t\tbChSmooth\t\t\t0x4\n#define\t\tbChSmoothCfg1\t\t0x38\n#define\t\tbChSmoothCfg2\t\t0x1c0\n#define\t\tbChSmoothCfg3\t\t0xe00\n#define\t\tbChSmoothCfg4\t\t0x7000\n#define\t\tbMRCMode\t\t\t0x800000\n#define\t\tbTHEVMCfg\t\t\t0x7000000\n\n#define\t\tbLoopFitType\t\t0x1\t/* Useless */\n#define\t\tbUpdCFO\t\t\t0x40\n#define\t\tbUpdCFOOffData\t\t0x80\n#define\t\tbAdvUpdCFO\t\t\t0x100\n#define\t\tbAdvTimeCtrl\t\t0x800\n#define\t\tbUpdClko\t\t\t0x1000\n#define\t\tbFC\t\t\t\t\t0x6000\n#define\t\tbTrackingMode\t\t0x8000\n#define\t\tbPhCmpEnable\t\t0x10000\n#define\t\tbUpdClkoLTF\t\t0x20000\n#define\t\tbComChCFO\t\t\t0x40000\n#define\t\tbCSIEstiMode\t\t0x80000\n#define\t\tbAdvUpdEqz\t\t\t0x100000\n#define\t\tbUChCfg\t\t\t\t0x7000000\n#define\t\tbUpdEqz\t\t\t0x8000000\n\n/* Rx Pseduo noise */\n#define\t\tbRxPesudoNoiseOn\t\t0x20000000\t/* Useless */\n#define\t\tbRxPesudoNoise_A\t\t0xff\n#define\t\tbRxPesudoNoise_B\t\t0xff00\n#define\t\tbRxPesudoNoise_C\t\t0xff0000\n#define\t\tbRxPesudoNoise_D\t\t0xff000000\n#define\t\tbPesudoNoiseState_A\t0xffff\n#define\t\tbPesudoNoiseState_B\t0xffff0000\n#define\t\tbPesudoNoiseState_C\t0xffff\n#define\t\tbPesudoNoiseState_D\t0xffff0000\n\n/* 7. RF Register\n * Zebra1 */\n#define\t\tbZebra1_HSSIEnable\t\t0x8\t\t/* Useless */\n#define\t\tbZebra1_TRxControl\t\t0xc00\n#define\t\tbZebra1_TRxGainSetting\t0x07f\n#define\t\tbZebra1_RxCorner\t\t0xc00\n#define\t\tbZebra1_TxChargePump\t0x38\n#define\t\tbZebra1_RxChargePump\t0x7\n#define\t\tbZebra1_ChannelNum\t0xf80\n#define\t\tbZebra1_TxLPFBW\t\t0x400\n#define\t\tbZebra1_RxLPFBW\t\t0x600\n\n/* Zebra4 */\n#define\t\tbRTL8256RegModeCtrl1\t0x100\t/* Useless */\n#define\t\tbRTL8256RegModeCtrl0\t0x40\n#define\t\tbRTL8256_TxLPFBW\t\t0x18\n#define\t\tbRTL8256_RxLPFBW\t\t0x600\n\n/* RTL8258 */\n#define\t\tbRTL8258_TxLPFBW\t\t0xc\t/* Useless */\n#define\t\tbRTL8258_RxLPFBW\t\t0xc00\n#define\t\tbRTL8258_RSSILPFBW\t0xc0\n\n\n/*\n * Other Definition\n *   */\n\n/* byte endable for sb_write */\n#define\t\tbByte0\t\t\t\t0x1\t/* Useless */\n#define\t\tbByte1\t\t\t\t0x2\n#define\t\tbByte2\t\t\t\t0x4\n#define\t\tbByte3\t\t\t\t0x8\n#define\t\tbWord0\t\t\t\t0x3\n#define\t\tbWord1\t\t\t\t0xc\n#define\t\tbDWord\t\t\t\t0xf\n\n/* for PutRegsetting & GetRegSetting BitMask */\n#define\t\tbMaskByte0\t\t\t0xff\t/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */\n#define\t\tbMaskByte1\t\t\t0xff00\n#define\t\tbMaskByte2\t\t\t0xff0000\n#define\t\tbMaskByte3\t\t\t0xff000000\n#define\t\tbMaskHWord\t\t0xffff0000\n#define\t\tbMaskLWord\t\t\t0x0000ffff\n#define\t\tbMaskDWord\t\t0xffffffff\n#define\t\tbMaskH3Bytes\t\t0xffffff00\n#define\t\tbMask12Bits\t\t\t0xfff\n#define\t\tbMaskH4Bits\t\t\t0xf0000000\n#define\t\tbMaskOFDM_D\t\t0xffc00000\n#define\t\tbMaskCCK\t\t\t0x3f3f3f3f\n\n\n#define\t\tbEnable\t\t\t0x1\t/* Useless */\n#define\t\tbDisable\t\t0x0\n\n#define\t\tLeftAntenna\t\t0x0\t/* Useless */\n#define\t\tRightAntenna\t0x1\n\n#define\t\ttCheckTxStatus\t\t500   /* 500ms */ /* Useless */\n#define\t\ttUpdateRxCounter\t100   /* 100ms */\n\n#define\t\trateCCK\t\t0\t/* Useless */\n#define\t\trateOFDM\t1\n#define\t\trateHT\t\t2\n\n/* define Register-End */\n#define\t\tbPMAC_End\t\t\t0x1ff\t/* Useless */\n#define\t\tbFPGAPHY0_End\t\t0x8ff\n#define\t\tbFPGAPHY1_End\t\t0x9ff\n#define\t\tbCCKPHY0_End\t\t0xaff\n#define\t\tbOFDMPHY0_End\t\t0xcff\n#define\t\tbOFDMPHY1_End\t\t0xdff\n\n/* define max debug item in each debug page\n * #define bMaxItem_FPGA_PHY0        0x9\n * #define bMaxItem_FPGA_PHY1        0x3\n * #define bMaxItem_PHY_11B          0x16\n * #define bMaxItem_OFDM_PHY0        0x29\n * #define bMaxItem_OFDM_PHY1        0x0 */\n\n#define\t\tbPMACControl\t\t0x0\t\t/* Useless */\n#define\t\tbWMACControl\t\t0x1\n#define\t\tbWNICControl\t\t0x2\n\n#define\t\tPathA\t\t\t0x0\t/* Useless */\n#define\t\tPathB\t\t\t0x1\n#define\t\tPathC\t\t\t0x2\n#define\t\tPathD\t\t\t0x3\n\n/*--------------------------Define Parameters-------------------------------*/\n\n\n/* BB Register Definition\n *\n * 4. Page9(0x900)\n *   */\n#define rDPDT_control\t\t\t\t0x92c\n#define rfe_ctrl_anta_src\t\t\t\t0x930\n#define rS0S1_PathSwitch\t\t\t0x948\n#define\tBBrx_DFIR\t\t\t\t\t\t0x954\n#define AGC_table_select\t\t\t\t0xb2c\n\n/*\n * PageB(0xB00)\n *   */\n#define rPdp_AntA\t\t\t\t\t\t0xb00\n#define rPdp_AntA_4\t\t\t\t\t\t0xb04\n#define rPdp_AntA_8\t\t\t\t\t\t0xb08\n#define rPdp_AntA_C\t\t\t\t\t\t0xb0c\n#define rPdp_AntA_10\t\t\t\t\t0xb10\n#define rPdp_AntA_14\t\t\t\t\t0xb14\n#define rPdp_AntA_18\t\t\t\t\t0xb18\n#define rPdp_AntA_1C\t\t\t\t\t0xb1c\n#define rPdp_AntA_20\t\t\t\t\t0xb20\n#define rPdp_AntA_24\t\t\t\t\t0xb24\n\n#define rConfig_Pmpd_AntA\t\t\t\t0xb28\n#define rConfig_ram64x16\t\t\t\t0xb2c\n\n#define rBndA\t\t\t\t\t\t\t0xb30\n#define rHssiPar\t\t\t\t\t\t0xb34\n\n#define rConfig_AntA\t\t\t\t\t0xb68\n#define rConfig_AntB\t\t\t\t\t0xb6c\n\n#define rPdp_AntB\t\t\t\t\t\t0xb70\n#define rPdp_AntB_4\t\t\t\t\t\t0xb74\n#define rPdp_AntB_8\t\t\t\t\t\t0xb78\n#define rPdp_AntB_C\t\t\t\t\t\t0xb7c\n#define rPdp_AntB_10\t\t\t\t\t0xb80\n#define rPdp_AntB_14\t\t\t\t\t0xb84\n#define rPdp_AntB_18\t\t\t\t\t0xb88\n#define rPdp_AntB_1C\t\t\t\t\t0xb8c\n#define rPdp_AntB_20\t\t\t\t\t0xb90\n#define rPdp_AntB_24\t\t\t\t\t0xb94\n\n#define rConfig_Pmpd_AntB\t\t\t\t0xb98\n\n#define rBndB\t\t\t\t\t\t\t0xba0\n\n#define rAPK\t\t\t\t\t\t\t0xbd8\n#define rPm_Rx0_AntA\t\t\t\t\t0xbdc\n#define rPm_Rx1_AntA\t\t\t\t\t0xbe0\n#define rPm_Rx2_AntA\t\t\t\t\t0xbe4\n#define rPm_Rx3_AntA\t\t\t\t\t0xbe8\n#define rPm_Rx0_AntB\t\t\t\t\t0xbec\n#define rPm_Rx1_AntB\t\t\t\t\t0xbf0\n#define rPm_Rx2_AntB\t\t\t\t\t0xbf4\n#define rPm_Rx3_AntB\t\t\t\t\t0xbf8\n\n#endif\n"
  },
  {
    "path": "include/Hal8188FPwrSeq.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef REALTEK_POWER_SEQUENCE_8188F\n#define REALTEK_POWER_SEQUENCE_8188F\n\n#include \"HalPwrSeqCmd.h\"\n\n/*\n\tCheck document WM-20130815-JackieLau-RTL8188F_Power_Architecture v08.vsd\n\tThere are 6 HW Power States:\n\t0: POFF--Power Off\n\t1: PDN--Power Down\n\t2: CARDEMU--Card Emulation\n\t3: ACT--Active Mode\n\t4: LPS--Low Power State\n\t5: SUS--Suspend\n\n\tThe transision from different states are defined below\n\tTRANS_CARDEMU_TO_ACT\n\tTRANS_ACT_TO_CARDEMU\n\tTRANS_CARDEMU_TO_SUS\n\tTRANS_SUS_TO_CARDEMU\n\tTRANS_CARDEMU_TO_PDN\n\tTRANS_ACT_TO_LPS\n\tTRANS_LPS_TO_ACT\n\n\tTRANS_END\n*/\n#define\tRTL8188F_TRANS_CARDEMU_TO_ACT_STEPS\t13\n#define\tRTL8188F_TRANS_ACT_TO_CARDEMU_STEPS\t15\n#define\tRTL8188F_TRANS_CARDEMU_TO_SUS_STEPS\t14\n#define\tRTL8188F_TRANS_SUS_TO_CARDEMU_STEPS\t15\n#define\tRTL8188F_TRANS_CARDEMU_TO_PDN_STEPS\t15\n#define\tRTL8188F_TRANS_PDN_TO_CARDEMU_STEPS\t15\n#define\tRTL8188F_TRANS_ACT_TO_LPS_STEPS\t\t11\n#define\tRTL8188F_TRANS_LPS_TO_ACT_STEPS\t\t13\n#define\tRTL8188F_TRANS_ACT_TO_SWLPS_STEPS\t\t21\n#define\tRTL8188F_TRANS_SWLPS_TO_ACT_STEPS\t\t14\n#define\tRTL8188F_TRANS_END_STEPS\t\t1\n\n\n#define RTL8188F_TRANS_CARDEMU_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT3), 0},/*  0x4[11]=1'b0 disable WL suspend*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* 0x4[8]=1 polling until return 0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/\t \\\n\t{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x35}, /*0x27<=35 to reduce RF noise*/\n\n#define RTL8188F_TRANS_ACT_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/\t\\\n\t{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\\\n\t{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x34}, /*0x27 <= 34, xtal_qsel = 0 to xtal bring up*/\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/\t\\\n\n#define RTL8188F_TRANS_CARDEMU_TO_SUS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /*0x07 = 0x00 , SOP option to disable BG/MB*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ \\\n\t{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/\n\n#define RTL8188F_TRANS_SUS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\t\\\n\t{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/\n\n#define RTL8188F_TRANS_CARDEMU_TO_CARDDIS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /*0x07 = 0x00 , SOP option to disable BG/MB*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ \\\n\t{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/\n\n#define RTL8188F_TRANS_CARDDIS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\t\\\n\t{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/\n\n\n#define RTL8188F_TRANS_CARDEMU_TO_PDN\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/\n\n#define RTL8188F_TRANS_PDN_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/\n\n#define RTL8188F_TRANS_ACT_TO_LPS\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*set RPWM IMR*/\t\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/\t\\\n\t{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/\t\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/\t\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\t\\\n\t{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/\n\n\n#define RTL8188F_TRANS_LPS_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84},  /*SDIO RPWM*/\\\n\t{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\\\n\t{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x35},/*xtal_qsel = 1 for low noise*/\t\\\n\t{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\\\n\t{0x002B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x1c, 0x1c},   /*.\t0x2b[4:2] = 3b'111\tto enable BB, AFE clock*/\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.\t0x101[1] = 1*/\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.\t0x100[7:0] = 0xFF\t enable WMAC TRX*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0},  /*.\t0x02[1:0] = 2b'11\t enable BB macro*/\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.\t0x522 = 0*/\n\n\n#define RTL8188F_TRANS_ACT_TO_SWLPS\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*set RPWM IMR*/\t\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/\t\\\n\t{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/\t\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/\t\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\t\\\n\t{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/\t\\\n\t{0x002b, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x1C, 0x00},/*0x2b[4:2]<=0 to gated BB, AFE clock*/\t\\\n\t{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x34},/*xtal_qsel = 0 for bring up*/\t\\\n\t{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x00},/* sdio LPS option*/\t\\\n\t{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x83},/* usb LPS option, open bandgap, xtal*/\t\\\n\t{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /* 0xC4[5]<=0, digital LDO no standby mode*/\t\\\n\t{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /* 0xC4[7]<=1, on domain voltage adjust*/\t\\\n\t{0x00a7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0xe0}, /* low power LPS enable for sdio*/\t\\\n\t{0x00a7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0xe4}, /* low power LPS enable for usb*/\t\\\n\t{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /* enable WL_LPS_EN*/\n\n\n#define RTL8188F_TRANS_SWLPS_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.\t0x101[1] = 1, enable security engine*/\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.\t0x100[7:0] = 0xFF\t enable WMAC TRX*/\\\n\t{0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x09}, /*.\treset MAC rx state machine*/\\\n\t{0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x86}, /*.\treset MAC rx state machine*/\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/\t\\\n\t{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/\t\\\n\t{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/\t\\\n\t{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/\t\\\n\t{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*.\t0x02[1:0] = 2b'11\t enable BB macro*/\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.\t0x522 = 0*/\n\n#define RTL8188F_TRANS_END\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},\n\n\n\textern WLAN_PWR_CFG rtl8188F_power_on_flow[RTL8188F_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188F_radio_off_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188F_card_disable_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188F_card_enable_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188F_suspend_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188F_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188F_resume_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188F_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188F_hwpdn_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188F_enter_lps_flow[RTL8188F_TRANS_ACT_TO_LPS_STEPS + RTL8188F_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188F_leave_lps_flow[RTL8188F_TRANS_LPS_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188F_enter_swlps_flow[RTL8188F_TRANS_ACT_TO_SWLPS_STEPS + RTL8188F_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8188F_leave_swlps_flow[RTL8188F_TRANS_SWLPS_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS];\n#endif\n"
  },
  {
    "path": "include/Hal8192EPhyCfg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2012 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8192EPHYCFG_H__\n#define __INC_HAL8192EPHYCFG_H__\n\n\n/*--------------------------Define Parameters-------------------------------*/\n#define LOOP_LIMIT\t\t\t\t5\n#define MAX_STALL_TIME\t\t\t50\t\t/* us */\n#define AntennaDiversityValue\t0x80\t/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */\n#define MAX_TXPWR_IDX_NMODE_92S\t63\n#define Reset_Cnt_Limit\t\t\t3\n\n#ifdef CONFIG_PCI_HCI\n\t#define MAX_AGGR_NUM\t0x0B\n#else\n\t#define MAX_AGGR_NUM\t0x07\n#endif /* CONFIG_PCI_HCI */\n\n\n/*--------------------------Define Parameters-------------------------------*/\n\n/*------------------------------Define structure----------------------------*/\n\n/* BB/RF related */\n\n/*------------------------------Define structure----------------------------*/\n\n\n/*------------------------Export global variable----------------------------*/\n/*------------------------Export global variable----------------------------*/\n\n\n/*------------------------Export Marco Definition---------------------------*/\n/*------------------------Export Marco Definition---------------------------*/\n\n\n/*--------------------------Exported Function prototype---------------------*/\n/*\n * BB and RF register read/write\n *   */\nu32\tPHY_QueryBBReg8192E(PADAPTER\tAdapter,\n\t\t\t\tu32\t\t\tRegAddr,\n\t\t\t\tu32\t\t\tBitMask);\nvoid\tPHY_SetBBReg8192E(PADAPTER\t\tAdapter,\n\t\t\t\tu32\t\t\tRegAddr,\n\t\t\t\tu32\t\t\tBitMask,\n\t\t\t\tu32\t\t\tData);\nu32\tPHY_QueryRFReg8192E(PADAPTER\tAdapter,\n\t\t\t\tenum rf_path\teRFPath,\n\t\t\t\tu32\t\t\tRegAddr,\n\t\t\t\tu32\t\t\tBitMask);\nvoid\tPHY_SetRFReg8192E(PADAPTER\t\tAdapter,\n\t\t\t\tenum rf_path\teRFPath,\n\t\t\t\tu32\t\t\tRegAddr,\n\t\t\t\tu32\t\t\tBitMask,\n\t\t\t\tu32\t\t\tData);\n\n/*\n * Initialization related function\n *\n * MAC/BB/RF HAL config */\nint\tPHY_MACConfig8192E(PADAPTER\tAdapter);\nint\tPHY_BBConfig8192E(PADAPTER\tAdapter);\nint\tPHY_RFConfig8192E(PADAPTER\tAdapter);\n\n/* RF config */\n\n\n/*\n * BB TX Power R/W\n *   */\nvoid\tPHY_SetTxPowerLevel8192E(PADAPTER\tAdapter, u8\tchannel);\n\nvoid\nPHY_SetTxPowerIndex_8192E(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu32\t\t\t\t\tPowerIndex,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate\n);\n\nu8\nPHY_GetTxPowerIndex_8192E(\n\t\tPADAPTER\t\t\tpAdapter,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate,\n\t\tu8\t\t\t\t\tBandWidth,\n\t\tu8\t\t\t\t\tChannel,\n\tstruct txpwr_idx_comp *tic\n);\n\n/*\n * channel switch related funciton\n *   */\nvoid\nPHY_SetSwChnlBWMode8192E(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu8\t\t\t\t\tchannel,\n\t\tenum channel_width\tBandwidth,\n\t\tu8\t\t\t\t\tOffset40,\n\t\tu8\t\t\t\t\tOffset80\n);\n\nvoid\nPHY_SetRFEReg_8192E(\n\t\tPADAPTER\t\tAdapter\n);\n\nvoid\nphy_SpurCalibration_8192E(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tenum spur_cal_method\tmethod\n);\nvoid PHY_SpurCalibration_8192E( PADAPTER Adapter);\n\n#ifdef CONFIG_SPUR_CAL_NBI\nvoid\nphy_SpurCalibration_8192E_NBI(\n\t\tPADAPTER\t\t\tAdapter\n);\n#endif\n/*\n * BB/MAC/RF other monitor API\n *   */\n\nvoid\nphy_set_rf_path_switch_8192e(\n\t\tstruct dm_struct\t\t*phydm,\n\t\tbool\t\tbMain\n);\n\n/*--------------------------Exported Function prototype---------------------*/\n#endif /* __INC_HAL8192CPHYCFG_H */\n"
  },
  {
    "path": "include/Hal8192EPhyReg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2012 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n/*****************************************************************************\n *\tCopyright(c) 2008,  RealTEK Technology Inc. All Right Reserved.\n *\n * Module:\t__INC_HAL8192SPHYREG_H\n *\n *\n * Note:\t1. Define PMAC/BB register map\n *\t\t\t2. Define RF register map\n *\t\t\t3. PMAC/BB register bit mask.\n *\t\t\t4. RF reg bit mask.\n *\t\t\t5. Other BB/RF relative definition.\n *\n *\n * Export:\tConstants, macro, functions(API), global variables(None).\n *\n * Abbrev:\n *\n * History:\n *\t\tData\t\tWho\t\tRemark\n *      08/07/2007  MHC\t1. Porting from 9x series PHYCFG.h.\n *\t\t\t\t\t\t\t2. Reorganize code architecture.\n *\t09/25/2008\tMH\t\t1. Add RL6052 register definition\n *\n *****************************************************************************/\n#ifndef __INC_HAL8192EPHYREG_H\n#define __INC_HAL8192EPHYREG_H\n\n\n/*--------------------------Define Parameters-------------------------------*/\n\n/* ************************************************************\n * 8192S Regsiter offset definition\n * ************************************************************ */\n\n/*\n * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00\n * 3. RF register 0x00-2E\n * 4. Bit Mask for BB/RF register\n * 5. Other defintion for BB/RF R/W\n *   */\n\n\n/*\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 1. Page1(0x100)\n *   */\n#define\t\trPMAC_Reset\t\t\t\t\t0x100\n#define\t\trPMAC_TxStart\t\t\t\t0x104\n#define\t\trPMAC_TxLegacySIG\t\t\t0x108\n#define\t\trPMAC_TxHTSIG1\t\t\t\t0x10c\n#define\t\trPMAC_TxHTSIG2\t\t\t\t0x110\n#define\t\trPMAC_PHYDebug\t\t\t\t0x114\n#define\t\trPMAC_TxPacketNum\t\t\t0x118\n#define\t\trPMAC_TxIdle\t\t\t\t\t0x11c\n#define\t\trPMAC_TxMACHeader0\t\t\t0x120\n#define\t\trPMAC_TxMACHeader1\t\t\t0x124\n#define\t\trPMAC_TxMACHeader2\t\t\t0x128\n#define\t\trPMAC_TxMACHeader3\t\t\t0x12c\n#define\t\trPMAC_TxMACHeader4\t\t\t0x130\n#define\t\trPMAC_TxMACHeader5\t\t\t0x134\n#define\t\trPMAC_TxDataType\t\t\t\t0x138\n#define\t\trPMAC_TxRandomSeed\t\t\t0x13c\n#define\t\trPMAC_CCKPLCPPreamble\t\t0x140\n#define\t\trPMAC_CCKPLCPHeader\t\t\t0x144\n#define\t\trPMAC_CCKCRC16\t\t\t\t0x148\n#define\t\trPMAC_OFDMRxCRC32OK\t\t0x170\n#define\t\trPMAC_OFDMRxCRC32Er\t\t0x174\n#define\t\trPMAC_OFDMRxParityEr\t\t\t0x178\n#define\t\trPMAC_OFDMRxCRC8Er\t\t\t0x17c\n#define\t\trPMAC_CCKCRxRC16Er\t\t\t0x180\n#define\t\trPMAC_CCKCRxRC32Er\t\t\t0x184\n#define\t\trPMAC_CCKCRxRC32OK\t\t\t0x188\n#define\t\trPMAC_TxStatus\t\t\t\t0x18c\n\n\n/*\n * 3. Page8(0x800)\n *   */\n#define\t\trFPGA0_RFMOD\t\t\t\t0x800\t/* RF mode & CCK TxSC */ /* RF BW Setting?? */\n\n#define\t\trFPGA0_TxInfo\t\t\t\t\t0x804\t/* Status report?? */\n#define\t\trFPGA0_PSDFunction\t\t\t0x808\n\n#define\t\trFPGA0_TxGainStage\t\t\t0x80c\t/* Set TX PWR init gain? */\n\n#define\t\trFPGA0_RFTiming1\t\t\t\t0x810\t/* Useless now */\n#define\t\trFPGA0_RFTiming2\t\t\t\t0x814\n\n#define\t\trFPGA0_XA_HSSIParameter1\t\t0x820\t/* RF 3 wire register */\n#define\t\trFPGA0_XA_HSSIParameter2\t\t0x824\n#define\t\trFPGA0_XB_HSSIParameter1\t\t0x828\n#define\t\trFPGA0_XB_HSSIParameter2\t\t0x82c\n\n#define\t\trFPGA0_XA_LSSIParameter\t\t0x840\n#define\t\trFPGA0_XB_LSSIParameter\t\t0x844\n\n#define\t\trFPGA0_RFWakeUpParameter\t0x850\t/* Useless now */\n#define\t\trFPGA0_RFSleepUpParameter\t\t0x854\n\n#define\t\trFPGA0_XAB_SwitchControl\t\t0x858\t/* RF Channel switch */\n#define\t\trFPGA0_XCD_SwitchControl\t\t0x85c\n\n#define\t\trFPGA0_XA_RFInterfaceOE\t\t0x860\t/* RF Channel switch */\n#define\t\trFPGA0_XB_RFInterfaceOE\t\t0x864\n\n#define\t\trFPGA0_XAB_RFInterfaceSW\t\t0x870\t/* RF Interface Software Control */\n#define\t\trFPGA0_XCD_RFInterfaceSW\t\t0x874\n\n#define\t\trFPGA0_XAB_RFParameter\t\t0x878\t/* RF Parameter */\n#define\t\trFPGA0_XCD_RFParameter\t\t0x87c\n\n#define\t\trFPGA0_AnalogParameter1\t\t0x880\t/* Crystal cap setting RF-R/W protection for parameter4?? */\n#define\t\trFPGA0_AnalogParameter2\t\t0x884\n#define\t\trFPGA0_AnalogParameter3\t\t0x888\n#define\t\trFPGA0_AdDaClockEn\t\t\t0x888\t/* enable ad/da clock1 for dual-phy */\n#define\t\trFPGA0_AnalogParameter4\t\t0x88c\n\n#define\t\trFPGA0_XA_LSSIReadBack\t\t0x8a0\t/* Tranceiver LSSI Readback */\n#define\t\trFPGA0_XB_LSSIReadBack\t\t0x8a4\n#define\t\trFPGA0_XC_LSSIReadBack\t\t0x8a8\n#define\t\trFPGA0_XD_LSSIReadBack\t\t0x8ac\n\n#define\t\trFPGA0_PSDReport\t\t\t\t0x8b4\t/* Useless now */\n#define\t\tTransceiverA_HSPI_Readback\t\t0x8b8\t/* Transceiver A HSPI Readback */\n#define\t\tTransceiverB_HSPI_Readback\t\t0x8bc\t/* Transceiver B HSPI Readback */\n#define\t\trFPGA0_XAB_RFInterfaceRB\t\t0x8e0\t/* Useless now */ /* RF Interface Readback Value */\n#define\t\trFPGA0_XCD_RFInterfaceRB\t\t0x8e4\t/* Useless now */\n\n/*\n * 4. Page9(0x900)\n *   */\n#define\t\trFPGA1_RFMOD\t\t\t\t0x900\t/* RF mode & OFDM TxSC */ /* RF BW Setting?? */\n\n#define\t\trFPGA1_TxBlock\t\t\t\t0x904\t/* Useless now */\n#define\t\trFPGA1_DebugSelect\t\t\t0x908\t/* Useless now */\n#define\t\trFPGA1_TxInfo\t\t\t\t\t0x90c\t/* Useless now */ /* Status report?? */\n\n/*\n * 5. PageA(0xA00)\n *\n * Set Control channel to upper or lower. These settings are required only for 40MHz */\n#define\t\trCCK0_System\t\t\t\t\t0xa00\n\n#define\t\trCCK0_AFESetting\t\t\t\t0xa04\t/* Disable init gain now */ /* Select RX path by RSSI */\n#define\t\trCCK0_CCA\t\t\t\t\t0xa08\t/* Disable init gain now */ /* Init gain */\n\n#define\t\trCCK0_RxAGC1\t\t\t\t0xa0c\t/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */\n#define\t\trCCK0_RxAGC2\t\t\t\t0xa10\t/* AGC & DAGC */\n\n#define\t\trCCK0_RxHP\t\t\t\t\t0xa14\n\n#define\t\trCCK0_DSPParameter1\t\t\t0xa18\t/* Timing recovery & Channel estimation threshold */\n#define\t\trCCK0_DSPParameter2\t\t\t0xa1c\t/* SQ threshold */\n\n#define\t\trCCK0_TxFilter1\t\t\t\t0xa20\n#define\t\trCCK0_TxFilter2\t\t\t\t0xa24\n#define\t\trCCK0_DebugPort\t\t\t\t0xa28\t/* debug port and Tx filter3 */\n#define\t\trCCK0_FalseAlarmReport\t\t0xa2c\t/* 0xa2d\tuseless now 0xa30-a4f channel report */\n#define\t\trCCK0_TRSSIReport\t\t\t0xa50\n#define\t\trCCK0_RxReport            \t\t\t0xa54  /* 0xa57 */\n#define\t\trCCK0_FACounterLower      \t\t0xa5c  /* 0xa5b */\n#define\t\trCCK0_FACounterUpper      \t\t0xa58  /* 0xa5c */\n\n/*\n * PageB(0xB00)\n *   */\n#define\t\trPdp_AntA\t\t\t\t\t0xb00\n#define\t\trPdp_AntA_4\t\t\t\t0xb04\n#define\t\trConfig_Pmpd_AntA\t\t\t0xb28\n#define\t\trConfig_ram64x16\t\t\t\t0xb2c\n\n#define\t\trConfig_AntA\t\t\t\t\t0xb68\n#define\t\trConfig_AntB\t\t\t\t\t0xb6c\n#define\t\trPdp_AntB\t\t\t\t\t0xb70\n#define\t\trPdp_AntB_4\t\t\t\t\t0xb74\n#define\t\trConfig_Pmpd_AntB\t\t\t0xb98\n#define\t\trAPK\t\t\t\t\t\t\t0xbd8\n\n\n\n/*\n * 6. PageC(0xC00)\n *   */\n#define\t\trOFDM0_LSTF\t\t\t\t\t0xc00\n\n#define\t\trOFDM0_TRxPathEnable\t\t\t0xc04\n#define\t\trOFDM0_TRMuxPar\t\t\t\t0xc08\n#define\t\trOFDM0_TRSWIsolation\t\t\t0xc0c\n\n#define\t\trOFDM0_XARxAFE\t\t\t\t0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */\n#define\t\trOFDM0_XARxIQImbalance    \t\t0xc14  /* RxIQ imblance matrix */\n#define\t\trOFDM0_XBRxAFE\t\t\t0xc18\n#define\t\trOFDM0_XBRxIQImbalance\t\t0xc1c\n#define\t\trOFDM0_XCRxAFE\t\t\t0xc20\n#define\t\trOFDM0_XCRxIQImbalance\t\t0xc24\n#define\t\trOFDM0_XDRxAFE\t\t\t0xc28\n#define\t\trOFDM0_XDRxIQImbalance\t\t0xc2c\n\n#define\t\trOFDM0_RxDetector1\t\t\t0xc30  /* PD, BW & SBD\t */ /* DM tune init gain */\n#define\t\trOFDM0_RxDetector2\t\t\t0xc34  /* SBD & Fame Sync. */\n#define\t\trOFDM0_RxDetector3\t\t\t0xc38  /* Frame Sync. */\n#define\t\trOFDM0_RxDetector4\t\t\t0xc3c  /* PD, SBD, Frame Sync & Short-GI */\n\n#define\t\trOFDM0_RxDSP\t\t\t\t0xc40  /* Rx Sync Path */\n#define\t\trOFDM0_CFOandDAGC\t\t\t0xc44  /* CFO & DAGC */\n#define\t\trOFDM0_CCADropThreshold\t\t0xc48 /* CCA Drop threshold */\n#define\t\trOFDM0_ECCAThreshold\t\t\t0xc4c /* energy CCA */\n\n#define\t\trOFDM0_XAAGCCore1\t\t\t0xc50\t/* DIG */\n#define\t\trOFDM0_XAAGCCore2\t\t\t0xc54\n#define\t\trOFDM0_XBAGCCore1\t\t\t0xc58\n#define\t\trOFDM0_XBAGCCore2\t\t\t0xc5c\n#define\t\trOFDM0_XCAGCCore1\t\t\t0xc60\n#define\t\trOFDM0_XCAGCCore2\t\t\t0xc64\n#define\t\trOFDM0_XDAGCCore1\t\t\t0xc68\n#define\t\trOFDM0_XDAGCCore2\t\t\t0xc6c\n\n#define\t\trOFDM0_AGCParameter1\t\t0xc70\n#define\t\trOFDM0_AGCParameter2\t\t0xc74\n#define\t\trOFDM0_AGCRSSITable\t\t\t0xc78\n#define\t\trOFDM0_HTSTFAGC\t\t\t\t0xc7c\n\n#define\t\trOFDM0_XATxIQImbalance\t\t0xc80\t/* TX PWR TRACK and DIG */\n#define\t\trOFDM0_XATxAFE\t\t\t\t0xc84\n#define\t\trOFDM0_XBTxIQImbalance\t\t0xc88\n#define\t\trOFDM0_XBTxAFE\t\t\t\t0xc8c\n#define\t\trOFDM0_XCTxIQImbalance\t\t0xc90\n#define\t\trOFDM0_XCTxAFE\t\t\t0xc94\n#define\t\trOFDM0_XDTxIQImbalance\t\t0xc98\n#define\t\trOFDM0_XDTxAFE\t\t\t\t0xc9c\n\n#define\t\trOFDM0_RxIQExtAnta\t\t\t0xca0\n#define\t\trOFDM0_TxCoeff1\t\t\t\t0xca4\n#define\t\trOFDM0_TxCoeff2\t\t\t\t0xca8\n#define\t\trOFDM0_TxCoeff3\t\t\t\t0xcac\n#define\t\trOFDM0_TxCoeff4\t\t\t\t0xcb0\n#define\t\trOFDM0_TxCoeff5\t\t\t\t0xcb4\n#define\t\trOFDM0_RxHPParameter\t\t0xce0\n#define\t\trOFDM0_TxPseudoNoiseWgt\t\t0xce4\n#define\t\trOFDM0_FrameSync\t\t\t0xcf0\n#define\t\trOFDM0_DFSReport\t\t\t0xcf4\n\n\n/*\n * 7. PageD(0xD00)\n *   */\n#define\t\trOFDM1_LSTF\t\t\t\t\t0xd00\n#define\t\trOFDM1_TRxPathEnable\t\t\t0xd04\n\n#define\t\trOFDM1_CFO\t\t\t\t\t0xd08\t/* No setting now */\n#define\t\trOFDM1_CSI1\t\t\t\t\t0xd10\n#define\t\trOFDM1_SBD\t\t\t\t\t0xd14\n#define\t\trOFDM1_CSI2\t\t\t\t\t0xd18\n#define\t\trOFDM1_CFOTracking\t\t\t0xd2c\n#define\t\trOFDM1_TRxMesaure1\t\t\t0xd34\n#define\t\trOFDM1_IntfDet\t\t\t\t0xd3c\n#define\t\trOFDM1_PseudoNoiseStateAB\t0xd50\n#define\t\trOFDM1_PseudoNoiseStateCD\t0xd54\n#define\t\trOFDM1_RxPseudoNoiseWgt\t\t0xd58\n\n#define\t\trOFDM_PHYCounter1\t\t\t0xda0  /* cca, parity fail */\n#define\t\trOFDM_PHYCounter2\t\t\t0xda4  /* rate illegal, crc8 fail */\n#define\t\trOFDM_PHYCounter3\t\t\t0xda8  /* MCS not support */\n\n#define\t\trOFDM_ShortCFOAB\t\t\t0xdac\t/* No setting now */\n#define\t\trOFDM_ShortCFOCD\t\t\t0xdb0\n#define\t\trOFDM_LongCFOAB\t\t\t\t0xdb4\n#define\t\trOFDM_LongCFOCD\t\t\t\t0xdb8\n#define\t\trOFDM_TailCFOAB\t\t\t\t0xdbc\n#define\t\trOFDM_TailCFOCD\t\t\t\t0xdc0\n#define\t\trOFDM_PWMeasure1\t\t0xdc4\n#define\t\trOFDM_PWMeasure2\t\t0xdc8\n#define\t\trOFDM_BWReport\t\t\t\t0xdcc\n#define\t\trOFDM_AGCReport\t\t\t\t0xdd0\n#define\t\trOFDM_RxSNR\t\t\t\t0xdd4\n#define\t\trOFDM_RxEVMCSI\t\t\t\t0xdd8\n#define\t\trOFDM_SIGReport\t\t\t\t0xddc\n\n\n/*\n * 8. PageE(0xE00)\n *   */\n#define\t\trTxAGC_A_Rate18_06\t\t\t0xe00\n#define\t\trTxAGC_A_Rate54_24\t\t\t0xe04\n#define\t\trTxAGC_A_CCK1_Mcs32\t\t\t0xe08\n#define\t\trTxAGC_A_Mcs03_Mcs00\t\t0xe10\n#define\t\trTxAGC_A_Mcs07_Mcs04\t\t0xe14\n#define\t\trTxAGC_A_Mcs11_Mcs08\t\t0xe18\n#define\t\trTxAGC_A_Mcs15_Mcs12\t\t0xe1c\n\n#define\t\trTxAGC_B_Rate18_06\t\t\t0x830\n#define\t\trTxAGC_B_Rate54_24\t\t\t0x834\n#define\t\trTxAGC_B_CCK1_55_Mcs32\t\t0x838\n#define\t\trTxAGC_B_Mcs03_Mcs00\t\t0x83c\n#define\t\trTxAGC_B_Mcs07_Mcs04\t\t0x848\n#define\t\trTxAGC_B_Mcs11_Mcs08\t\t0x84c\n#define\t\trTxAGC_B_Mcs15_Mcs12\t\t0x868\n#define\t\trTxAGC_B_CCK11_A_CCK2_11\t\t0x86c\n\n#define\t\trFPGA0_IQK\t\t\t\t\t0xe28\n#define\t\trTx_IQK_Tone_A\t\t\t\t0xe30\n#define\t\trRx_IQK_Tone_A\t\t\t\t0xe34\n#define\t\trTx_IQK_PI_A\t\t\t\t\t0xe38\n#define\t\trRx_IQK_PI_A\t\t\t\t\t0xe3c\n\n#define\t\trTx_IQK\t\t\t\t\t\t0xe40\n#define\t\trRx_IQK\t\t\t\t\t\t0xe44\n#define\t\trIQK_AGC_Pts\t\t\t\t\t0xe48\n#define\t\trIQK_AGC_Rsp\t\t\t\t\t0xe4c\n#define\t\trTx_IQK_Tone_B\t\t\t\t0xe50\n#define\t\trRx_IQK_Tone_B\t\t\t\t0xe54\n#define\t\trTx_IQK_PI_B\t\t\t\t\t0xe58\n#define\t\trRx_IQK_PI_B\t\t\t\t\t0xe5c\n#define\t\trIQK_AGC_Cont\t\t\t\t0xe60\n\n#define\t\trBlue_Tooth\t\t\t\t\t0xe6c\n#define\t\trRx_Wait_CCA\t\t\t\t\t0xe70\n#define\t\trTx_CCK_RFON\t\t\t\t\t0xe74\n#define\t\trTx_CCK_BBON\t\t\t\t0xe78\n#define\t\trTx_OFDM_RFON\t\t\t\t0xe7c\n#define\t\trTx_OFDM_BBON\t\t\t\t0xe80\n#define\t\trTx_To_Rx\t\t\t\t\t0xe84\n#define\t\trTx_To_Tx\t\t\t\t\t0xe88\n#define\t\trRx_CCK\t\t\t\t\t\t0xe8c\n\n#define\t\trTx_Power_Before_IQK_A\t\t0xe94\n#define\t\trTx_Power_After_IQK_A\t\t\t0xe9c\n\n#define\t\trRx_Power_Before_IQK_A\t\t0xea0\n#define\t\trRx_Power_Before_IQK_A_2\t\t0xea4\n#define\t\trRx_Power_After_IQK_A\t\t\t0xea8\n#define\t\trRx_Power_After_IQK_A_2\t\t0xeac\n\n#define\t\trTx_Power_Before_IQK_B\t\t0xeb4\n#define\t\trTx_Power_After_IQK_B\t\t\t0xebc\n\n#define\t\trRx_Power_Before_IQK_B\t\t0xec0\n#define\t\trRx_Power_Before_IQK_B_2\t\t0xec4\n#define\t\trRx_Power_After_IQK_B\t\t\t0xec8\n#define\t\trRx_Power_After_IQK_B_2\t\t0xecc\n\n#define\t\trRx_OFDM\t\t\t\t\t0xed0\n#define\t\trRx_Wait_RIFS\t\t\t\t0xed4\n#define\t\trRx_TO_Rx\t\t\t\t\t0xed8\n#define\t\trStandby\t\t\t\t\t\t0xedc\n#define\t\trSleep\t\t\t\t\t\t0xee0\n#define\t\trPMPD_ANAEN\t\t\t\t0xeec\n\n/*\n * 7. RF Register 0x00-0x2E (RF 8256)\n * RF-0222D 0x00-3F\n *\n * Zebra1 */\n#define\t\trZebra1_HSSIEnable\t\t\t\t0x0\t/* Useless now */\n#define\t\trZebra1_TRxEnable1\t\t\t0x1\n#define\t\trZebra1_TRxEnable2\t\t\t0x2\n#define\t\trZebra1_AGC\t\t\t\t\t0x4\n#define\t\trZebra1_ChargePump\t\t\t0x5\n#define\t\trZebra1_Channel\t\t\t\t0x7\t/* RF channel switch */\n\n/* #endif */\n#define\t\trZebra1_TxGain\t\t\t\t0x8\t/* Useless now */\n#define\t\trZebra1_TxLPF\t\t\t\t\t0x9\n#define\t\trZebra1_RxLPF\t\t\t\t\t0xb\n#define\t\trZebra1_RxHPFCorner\t\t\t0xc\n\n/* Zebra4 */\n#define\t\trGlobalCtrl\t\t\t\t\t0\t/* Useless now */\n#define\t\trRTL8256_TxLPF\t\t\t\t19\n#define\t\trRTL8256_RxLPF\t\t\t\t11\n\n/* RTL8258 */\n#define\t\trRTL8258_TxLPF\t\t\t\t0x11\t/* Useless now */\n#define\t\trRTL8258_RxLPF\t\t\t\t0x13\n#define\t\trRTL8258_RSSILPF\t\t\t\t0xa\n\n/*\n * RL6052 Register definition\n *   */\n#define\t\tRF_AC\t\t\t\t\t\t0x00\t/*  */\n\n#define\t\tRF_IQADJ_G1\t\t\t\t\t0x01\t/*  */\n#define\t\tRF_IQADJ_G2\t\t\t\t\t0x02\t/*  */\n\n#define\t\tRF_POW_TRSW\t\t\t\t0x05\t/*  */\n\n#define\t\tRF_GAIN_RX\t\t\t\t\t0x06\t/*  */\n#define\t\tRF_GAIN_TX\t\t\t\t\t0x07\t/*  */\n\n#define\t\tRF_TXM_IDAC\t\t\t\t\t0x08\t/*  */\n#define\t\tRF_IPA_G\t\t\t\t\t\t0x09\t/*  */\n#define\t\tRF_TXBIAS_G\t\t\t\t\t0x0A\n#define\t\tRF_TXPA_AG\t\t\t\t\t0x0B\n#define\t\tRF_IPA_A\t\t\t\t\t\t0x0C\t/*  */\n#define\t\tRF_TXBIAS_A\t\t\t\t\t0x0D\n#define\t\tRF_BS_PA_APSET_G9_G11\t\t0x0E\n#define\t\tRF_BS_IQGEN\t\t\t\t\t0x0F\t/*  */\n\n#define\t\tRF_MODE1\t\t\t\t\t0x10\t/*  */\n#define\t\tRF_MODE2\t\t\t\t\t0x11\t/*  */\n\n#define\t\tRF_RX_AGC_HP\t\t\t\t0x12\t/*  */\n#define\t\tRF_TX_AGC\t\t\t\t\t0x13\t/*  */\n#define\t\tRF_BIAS\t\t\t\t\t\t0x14\t/*  */\n#define\t\tRF_IPA\t\t\t\t\t\t0x15\t/*  */\n#define\t\tRF_TXBIAS\t\t\t\t\t0x16\n#define\t\tRF_POW_ABILITY\t\t\t\t0x17\t/*  */\n#define\t\tRF_CHNLBW\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define\t\tRF_TOP\t\t\t\t\t\t0x19\t/*  */\n\n#define\t\tRF_RX_G1\t\t\t\t\t0x1A\t/*  */\n#define\t\tRF_RX_G2\t\t\t\t\t0x1B\t/*  */\n\n#define\t\tRF_RX_BB2\t\t\t\t\t0x1C\t/*  */\n#define\t\tRF_RX_BB1\t\t\t\t\t0x1D\t/*  */\n\n#define\t\tRF_RCK1\t\t\t\t\t\t0x1E\t/*  */\n#define\t\tRF_RCK2\t\t\t\t\t\t0x1F\t/*  */\n\n#define\t\tRF_TX_G1\t\t\t\t\t\t0x20\t/*  */\n#define\t\tRF_TX_G2\t\t\t\t\t\t0x21\t/*  */\n#define\t\tRF_TX_G3\t\t\t\t\t\t0x22\t/*  */\n\n#define\t\tRF_TX_BB1\t\t\t\t\t0x23\t/*  */\n\n#define\t\tRF_T_METER_8192E\t\t\t0x42\t/*  */\n#define\t\tRF_T_METER_88E\t\t\t\t0x42\n#define\t\tRF_T_METER\t\t\t\t\t0x24\t/*  */\n\n/* #endif */\n\n#define\t\tRF_SYN_G1\t\t\t\t\t0x25\t/* RF TX Power control */\n#define\t\tRF_SYN_G2\t\t\t\t\t0x26\t/* RF TX Power control */\n#define\t\tRF_SYN_G3\t\t\t\t\t0x27\t/* RF TX Power control */\n#define\t\tRF_SYN_G4\t\t\t\t\t0x28\t/* RF TX Power control */\n#define\t\tRF_SYN_G5\t\t\t\t\t0x29\t/* RF TX Power control */\n#define\t\tRF_SYN_G6\t\t\t\t\t0x2A\t/* RF TX Power control */\n#define\t\tRF_SYN_G7\t\t\t\t\t0x2B\t/* RF TX Power control */\n#define\t\tRF_SYN_G8\t\t\t\t\t0x2C\t/* RF TX Power control */\n\n#define\t\tRF_RCK_OS\t\t\t\t\t0x30\t/* RF TX PA control */\n#define\t\tRF_TXPA_G1\t\t\t\t\t0x31\t/* RF TX PA control */\n#define\t\tRF_TXPA_G2\t\t\t\t\t0x32\t/* RF TX PA control */\n#define\t\tRF_TXPA_G3\t\t\t\t\t0x33\t/* RF TX PA control */\n#define\t\tRF_TX_BIAS_A\t\t\t\t\t0x35\n#define\t\tRF_TX_BIAS_D\t\t\t\t\t0x36\n#define\t\tRF_LOBF_9\t\t\t\t\t0x38\n#define\t\tRF_RXRF_A3\t\t\t\t\t0x3C\t/*\t */\n#define\t\tRF_TRSW\t\t\t\t\t\t0x3F\n\n#define\t\tRF_TXRF_A2\t\t\t\t\t0x41\n#define\t\tRF_TXPA_G4\t\t\t\t\t0x46\n#define\t\tRF_TXPA_A4\t\t\t\t\t0x4B\n#define\t\tRF_0x52\t\t\t\t\t\t0x52\n#define\t\tRF_LDO\t\t\t\t\t\t0xB1\n#define\t\tRF_WE_LUT\t\t\t\t\t0xEF\n\n\n/*\n * Bit Mask\n *\n * 1. Page1(0x100) */\n#define\t\tbBBResetB\t\t\t\t\t0x100\t/* Useless now? */\n#define\t\tbGlobalResetB\t\t\t\t\t0x200\n#define\t\tbOFDMTxStart\t\t\t\t\t0x4\n#define\t\tbCCKTxStart\t\t\t\t\t0x8\n#define\t\tbCRC32Debug\t\t\t\t\t0x100\n#define\t\tbPMACLoopback\t\t\t\t0x10\n#define\t\tbTxLSIG\t\t\t\t\t\t0xffffff\n#define\t\tbOFDMTxRate\t\t\t\t\t0xf\n#define\t\tbOFDMTxReserved\t\t\t\t0x10\n#define\t\tbOFDMTxLength\t\t\t\t0x1ffe0\n#define\t\tbOFDMTxParity\t\t\t\t0x20000\n#define\t\tbTxHTSIG1\t\t\t\t\t0xffffff\n#define\t\tbTxHTMCSRate\t\t\t\t0x7f\n#define\t\tbTxHTBW\t\t\t\t\t\t0x80\n#define\t\tbTxHTLength\t\t\t\t\t0xffff00\n#define\t\tbTxHTSIG2\t\t\t\t\t0xffffff\n#define\t\tbTxHTSmoothing\t\t\t\t0x1\n#define\t\tbTxHTSounding\t\t\t\t0x2\n#define\t\tbTxHTReserved\t\t\t\t0x4\n#define\t\tbTxHTAggreation\t\t\t\t0x8\n#define\t\tbTxHTSTBC\t\t\t\t\t0x30\n#define\t\tbTxHTAdvanceCoding\t\t\t0x40\n#define\t\tbTxHTShortGI\t\t\t\t\t0x80\n#define\t\tbTxHTNumberHT_LTF\t\t\t0x300\n#define\t\tbTxHTCRC8\t\t\t\t\t0x3fc00\n#define\t\tbCounterReset\t\t\t\t0x10000\n#define\t\tbNumOfOFDMTx\t\t\t\t0xffff\n#define\t\tbNumOfCCKTx\t\t\t\t\t0xffff0000\n#define\t\tbTxIdleInterval\t\t\t\t0xffff\n#define\t\tbOFDMService\t\t\t\t\t0xffff0000\n#define\t\tbTxMACHeader\t\t\t\t0xffffffff\n#define\t\tbTxDataInit\t\t\t\t\t0xff\n#define\t\tbTxHTMode\t\t\t\t\t0x100\n#define\t\tbTxDataType\t\t\t\t\t0x30000\n#define\t\tbTxRandomSeed\t\t\t\t0xffffffff\n#define\t\tbCCKTxPreamble\t\t\t\t0x1\n#define\t\tbCCKTxSFD\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxSIG\t\t\t\t\t0xff\n#define\t\tbCCKTxService\t\t\t\t\t0xff00\n#define\t\tbCCKLengthExt\t\t\t\t\t0x8000\n#define\t\tbCCKTxLength\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxCRC16\t\t\t\t\t0xffff\n#define\t\tbCCKTxStatus\t\t\t\t\t0x1\n#define\t\tbOFDMTxStatus\t\t\t\t0x2\n\n#define\t\tIS_BB_REG_OFFSET_92S(_Offset)\t\t((_Offset >= 0x800) && (_Offset <= 0xfff))\n#define\t\tRF_TX_GAIN_OFFSET_8192E(_val)\t\t((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))\n\n\n/* 2. Page8(0x800) */\n#define\t\tbRFMOD\t\t\t\t\t\t0x1\t/* Reg 0x800 rFPGA0_RFMOD */\n#define\t\tbJapanMode\t\t\t\t\t0x2\n#define\t\tbCCKTxSC\t\t\t\t\t\t0x30\n#define\t\tbCCKEn\t\t\t\t\t\t0x1000000\n#define\t\tbOFDMEn\t\t\t\t\t0x2000000\n\n#define\t\tbOFDMRxADCPhase           \t\t0x10000\t/* Useless now */\n#define\t\tbOFDMTxDACPhase\t\t0x40000\n#define\t\tbXATxAGC\t\t\t\t0x3f\n\n#define\t\tbAntennaSelect\t\t\t0x0300\n\n#define\t\tbXBTxAGC                  \t\t\t\t0xf00\t/* Reg 80c rFPGA0_TxGainStage */\n#define\t\tbXCTxAGC\t\t\t\t0xf000\n#define\t\tbXDTxAGC\t\t\t\t0xf0000\n\n#define\t\tbPAStart                  \t\t\t\t0xf0000000\t/* Useless now */\n#define\t\tbTRStart\t\t\t\t0x00f00000\n#define\t\tbRFStart\t\t\t\t0x0000f000\n#define\t\tbBBStart\t\t\t\t0x000000f0\n#define\t\tbBBCCKStart\t\t\t0x0000000f\n#define\t\tbPAEnd                    \t\t\t\t0xf          /* Reg0x814 */\n#define\t\tbTREnd\t\t\t\t0x0f000000\n#define\t\tbRFEnd\t\t\t\t0x000f0000\n#define\t\tbCCAMask                  \t\t\t\t0x000000f0   /* T2R */\n#define\t\tbR2RCCAMask\t\t\t0x00000f00\n#define\t\tbHSSI_R2TDelay\t\t\t0xf8000000\n#define\t\tbHSSI_T2RDelay\t\t\t0xf80000\n#define\t\tbContTxHSSI               \t\t\t0x400     /* chane gain at continue Tx */\n#define\t\tbIGFromCCK\t\t\t0x200\n#define\t\tbAGCAddress\t\t\t0x3f\n#define\t\tbRxHPTx\t\t\t\t0x7000\n#define\t\tbRxHPT2R\t\t\t\t0x38000\n#define\t\tbRxHPCCKIni\t\t\t0xc0000\n#define\t\tbAGCTxCode\t\t\t0xc00000\n#define\t\tbAGCRxCode\t\t\t0x300000\n\n#define\t\tb3WireDataLength          \t\t\t0x800\t/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */\n#define\t\tb3WireAddressLength\t\t0x400\n\n#define\t\tb3WireRFPowerDown         \t\t0x1\t/* Useless now\n * #define bHWSISelect\t\t0x8 */\n#define\t\tb5GPAPEPolarity\t\t\t0x40000000\n#define\t\tb2GPAPEPolarity\t\t\t0x80000000\n#define\t\tbRFSW_TxDefaultAnt\t\t0x3\n#define\t\tbRFSW_TxOptionAnt\t\t0x30\n#define\t\tbRFSW_RxDefaultAnt\t\t0x300\n#define\t\tbRFSW_RxOptionAnt\t\t0x3000\n#define\t\tbRFSI_3WireData\t\t\t0x1\n#define\t\tbRFSI_3WireClock\t\t\t0x2\n#define\t\tbRFSI_3WireLoad\t\t\t0x4\n#define\t\tbRFSI_3WireRW\t\t\t0x8\n#define\t\tbRFSI_3Wire\t\t\t0xf\n\n#define\t\tbRFSI_RFENV               \t\t0x10\t/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */\n\n#define\t\tbRFSI_TRSW                \t\t0x20\t/* Useless now */\n#define\t\tbRFSI_TRSWB\t\t0x40\n#define\t\tbRFSI_ANTSW\t\t0x100\n#define\t\tbRFSI_ANTSWB\t\t0x200\n#define\t\tbRFSI_PAPE\t\t\t0x400\n#define\t\tbRFSI_PAPE5G\t\t0x800\n#define\t\tbBandSelect\t\t\t0x1\n#define\t\tbHTSIG2_GI\t\t\t0x80\n#define\t\tbHTSIG2_Smoothing\t\t0x01\n#define\t\tbHTSIG2_Sounding\t\t0x02\n#define\t\tbHTSIG2_Aggreaton\t\t0x08\n#define\t\tbHTSIG2_STBC\t\t0x30\n#define\t\tbHTSIG2_AdvCoding\t\t0x40\n#define\t\tbHTSIG2_NumOfHTLTF\t0x300\n#define\t\tbHTSIG2_CRC8\t\t0x3fc\n#define\t\tbHTSIG1_MCS\t\t0x7f\n#define\t\tbHTSIG1_BandWidth\t\t0x80\n#define\t\tbHTSIG1_HTLength\t\t0xffff\n#define\t\tbLSIG_Rate\t\t\t0xf\n#define\t\tbLSIG_Reserved\t\t0x10\n#define\t\tbLSIG_Length\t\t0x1fffe\n#define\t\tbLSIG_Parity\t\t\t0x20\n#define\t\tbCCKRxPhase\t\t0x4\n\n#define\t\tbLSSIReadAddress          \t\t0x7f800000   /* T65 RF */\n\n#define\t\tbLSSIReadEdge             \t\t0x80000000   /* LSSI \"Read\" edge signal */\n\n#define\t\tbLSSIReadBackData         \t\t0xfffff\t\t/* T65 RF */\n\n#define\t\tbLSSIReadOKFlag           \t\t0x1000\t/* Useless now */\n#define\t\tbCCKSampleRate            \t\t0x8       /* 0: 44MHz, 1:88MHz      \t\t */\n#define\t\tbRegulator0Standby\t\t0x1\n#define\t\tbRegulatorPLLStandby\t0x2\n#define\t\tbRegulator1Standby\t\t0x4\n#define\t\tbPLLPowerUp\t\t0x8\n#define\t\tbDPLLPowerUp\t\t0x10\n#define\t\tbDA10PowerUp\t\t0x20\n#define\t\tbAD7PowerUp\t\t0x200\n#define\t\tbDA6PowerUp\t\t0x2000\n#define\t\tbXtalPowerUp\t\t0x4000\n#define\t\tb40MDClkPowerUP\t0x8000\n#define\t\tbDA6DebugMode\t\t0x20000\n#define\t\tbDA6Swing\t\t\t0x380000\n\n#define\t\tbADClkPhase               \t\t0x4000000\t/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */\n\n#define\t\tb80MClkDelay              \t\t0x18000000\t/* Useless */\n#define\t\tbAFEWatchDogEnable\t0x20000000\n\n#define\t\tbXtalCap01                \t\t\t0xc0000000\t/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */\n#define\t\tbXtalCap23\t\t\t0x3\n#define\t\tbXtalCap92x\t\t\t\t0x0f000000\n#define\t\tbXtalCap\t\t\t0x0f000000\n\n#define\t\tbIntDifClkEnable          \t\t0x400\t/* Useless */\n#define\t\tbExtSigClkEnable\t\t0x800\n#define\t\tbBandgapMbiasPowerUp\t0x10000\n#define\t\tbAD11SHGain\t\t0xc0000\n#define\t\tbAD11InputRange\t\t0x700000\n#define\t\tbAD11OPCurrent\t\t0x3800000\n#define\t\tbIPathLoopback\t\t0x4000000\n#define\t\tbQPathLoopback\t\t0x8000000\n#define\t\tbAFELoopback\t\t0x10000000\n#define\t\tbDA10Swing\t\t0x7e0\n#define\t\tbDA10Reverse\t\t0x800\n#define\t\tbDAClkSource\t\t0x1000\n#define\t\tbAD7InputRange\t\t0x6000\n#define\t\tbAD7Gain\t\t\t0x38000\n#define\t\tbAD7OutputCMMode\t0x40000\n#define\t\tbAD7InputCMMode\t0x380000\n#define\t\tbAD7Current\t\t0xc00000\n#define\t\tbRegulatorAdjust\t\t0x7000000\n#define\t\tbAD11PowerUpAtTx\t0x1\n#define\t\tbDA10PSAtTx\t\t0x10\n#define\t\tbAD11PowerUpAtRx\t0x100\n#define\t\tbDA10PSAtRx\t\t0x1000\n#define\t\tbCCKRxAGCFormat\t\t0x200\n#define\t\tbPSDFFTSamplepPoint\t0xc000\n#define\t\tbPSDAverageNum\t\t0x3000\n#define\t\tbIQPathControl\t\t0xc00\n#define\t\tbPSDFreq\t\t\t0x3ff\n#define\t\tbPSDAntennaPath\t\t0x30\n#define\t\tbPSDIQSwitch\t\t0x40\n#define\t\tbPSDRxTrigger\t\t0x400000\n#define\t\tbPSDTxTrigger\t\t0x80000000\n#define\t\tbPSDSineToneScale\t\t0x7f000000\n#define\t\tbPSDReport\t\t0xffff\n\n/* 3. Page9(0x900) */\n#define\t\tbOFDMTxSC                 \t\t0x30000000\t/* Useless */\n#define\t\tbCCKTxOn\t\t\t0x1\n#define\t\tbOFDMTxOn\t\t0x2\n#define\t\tbDebugPage                \t\t0xfff  /* reset debug page and also HWord, LWord */\n#define\t\tbDebugItem                \t\t0xff   /* reset debug page and LWord */\n#define\t\tbAntL\t\t\t\t0x10\n#define\t\tbAntNonHT\t\t\t0x100\n#define\t\tbAntHT1\t\t\t0x1000\n#define\t\tbAntHT2\t\t\t0x10000\n#define\t\tbAntHT1S1\t\t\t0x100000\n#define\t\tbAntNonHTS1\t\t0x1000000\n\n/* 4. PageA(0xA00) */\n#define\t\tbCCKBBMode                \t\t0x3\t/* Useless */\n#define\t\tbCCKTxPowerSaving\t\t0x80\n#define\t\tbCCKRxPowerSaving\t\t0x40\n\n#define\t\tbCCKSideBand              \t\t0x10\t/* Reg 0xa00 rCCK0_System 20/40 switch */\n\n#define\t\tbCCKScramble              \t\t0x8\t/* Useless */\n#define\t\tbCCKAntDiversity\t\t\t0x8000\n#define\t\tbCCKCarrierRecovery\t\t0x4000\n#define\t\tbCCKTxRate\t\t\t0x3000\n#define\t\tbCCKDCCancel\t\t0x0800\n#define\t\tbCCKISICancel\t\t0x0400\n#define\t\tbCCKMatchFilter\t\t0x0200\n#define\t\tbCCKEqualizer\t\t0x0100\n#define\t\tbCCKPreambleDetect\t\t0x800000\n#define\t\tbCCKFastFalseCCA\t\t0x400000\n#define\t\tbCCKChEstStart\t\t0x300000\n#define\t\tbCCKCCACount\t\t0x080000\n#define\t\tbCCKcs_lim\t\t\t0x070000\n#define\t\tbCCKBistMode\t\t0x80000000\n#define\t\tbCCKCCAMask\t\t0x40000000\n#define\t\tbCCKTxDACPhase\t\t0x4\n#define\t\tbCCKRxADCPhase         \t   \t0x20000000   /* r_rx_clk */\n#define\t\tbCCKr_cp_mode0\t\t0x0100\n#define\t\tbCCKTxDCOffset\t\t0xf0\n#define\t\tbCCKRxDCOffset\t\t0xf\n#define\t\tbCCKCCAMode\t\t0xc000\n#define\t\tbCCKFalseCS_lim\t\t0x3f00\n#define\t\tbCCKCS_ratio\t\t0xc00000\n#define\t\tbCCKCorgBit_sel\t\t0x300000\n#define\t\tbCCKPD_lim\t\t0x0f0000\n#define\t\tbCCKNewCCA\t\t0x80000000\n#define\t\tbCCKRxHPofIG\t\t0x8000\n#define\t\tbCCKRxIG\t\t\t0x7f00\n#define\t\tbCCKLNAPolarity\t\t0x800000\n#define\t\tbCCKRx1stGain\t\t0x7f0000\n#define\t\tbCCKRFExtend              \t\t0x20000000 /* CCK Rx Iinital gain polarity */\n#define\t\tbCCKRxAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKRxAGCSatCount\t\t0xe0\n#define\t\tbCCKRxRFSettle            \t\t0x1f       /* AGCsamp_dly */\n#define\t\tbCCKFixedRxAGC\t\t0x8000\n/* #define bCCKRxAGCFormat\t\t0x4000 */   /* remove to HSSI register 0x824 */\n#define\t\tbCCKAntennaPolarity\t\t0x2000\n#define\t\tbCCKTxFilterType\t\t0x0c00\n#define\t\tbCCKRxAGCReportType\t\t0x0300\n#define\t\tbCCKRxDAGCEn\t\t0x80000000\n#define\t\tbCCKRxDAGCPeriod\t\t0x20000000\n#define\t\tbCCKRxDAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKTimingRecovery\t\t0x800000\n#define\t\tbCCKTxC0\t\t\t0x3f0000\n#define\t\tbCCKTxC1\t\t\t0x3f000000\n#define\t\tbCCKTxC2\t\t\t0x3f\n#define\t\tbCCKTxC3\t\t\t0x3f00\n#define\t\tbCCKTxC4\t\t\t0x3f0000\n#define\t\tbCCKTxC5\t\t\t0x3f000000\n#define\t\tbCCKTxC6\t\t\t0x3f\n#define\t\tbCCKTxC7\t\t\t0x3f00\n#define\t\tbCCKDebugPort\t\t0xff0000\n#define\t\tbCCKDACDebug\t\t0x0f000000\n#define\t\tbCCKFalseAlarmEnable\t0x8000\n#define\t\tbCCKFalseAlarmRead\t0x4000\n#define\t\tbCCKTRSSI\t\t\t0x7f\n#define\t\tbCCKRxAGCReport\t\t0xfe\n#define\t\tbCCKRxReport_AntSel\t0x80000000\n#define\t\tbCCKRxReport_MFOff\t0x40000000\n#define\t\tbCCKRxRxReport_SQLoss\t0x20000000\n#define\t\tbCCKRxReport_Pktloss\t0x10000000\n#define\t\tbCCKRxReport_Lockedbit\t0x08000000\n#define\t\tbCCKRxReport_RateError\t0x04000000\n#define\t\tbCCKRxReport_RxRate\t0x03000000\n#define\t\tbCCKRxFACounterLower\t0xff\n#define\t\tbCCKRxFACounterUpper\t0xff000000\n#define\t\tbCCKRxHPAGCStart\t\t0xe000\n#define\t\tbCCKRxHPAGCFinal\t\t0x1c00\n#define\t\tbCCKRxFalseAlarmEnable\t0x8000\n#define\t\tbCCKFACounterFreeze\t0x4000\n#define\t\tbCCKTxPathSel\t\t0x10000000\n#define\t\tbCCKDefaultRxPath\t\t0xc000000\n#define\t\tbCCKOptionRxPath\t\t0x3000000\n\n/* 5. PageC(0xC00) */\n#define\t\tbNumOfSTF                \t\t\t0x3\t/* Useless */\n#define\t\tbShift_L\t\t\t0xc0\n#define\t\tbGI_TH\t\t\t0xc\n#define\t\tbRxPathA\t\t\t0x1\n#define\t\tbRxPathB\t\t\t0x2\n#define\t\tbRxPathC\t\t\t0x4\n#define\t\tbRxPathD\t\t\t0x8\n#define\t\tbTxPathA\t\t\t0x1\n#define\t\tbTxPathB\t\t\t0x2\n#define\t\tbTxPathC\t\t\t0x4\n#define\t\tbTxPathD\t\t\t0x8\n#define\t\tbTRSSIFreq\t\t\t0x200\n#define\t\tbADCBackoff\t\t\t0x3000\n#define\t\tbDFIRBackoff\t\t\t0xc000\n#define\t\tbTRSSILatchPhase\t\t0x10000\n#define\t\tbRxIDCOffset\t\t\t0xff\n#define\t\tbRxQDCOffset\t\t0xff00\n#define\t\tbRxDFIRMode\t\t0x1800000\n#define\t\tbRxDCNFType\t\t0xe000000\n#define\t\tbRXIQImb_A\t\t0x3ff\n#define\t\tbRXIQImb_B\t\t\t0xfc00\n#define\t\tbRXIQImb_C\t\t\t0x3f0000\n#define\t\tbRXIQImb_D\t\t0xffc00000\n#define\t\tbDC_dc_Notch\t\t0x60000\n#define\t\tbRxNBINotch\t\t0x1f000000\n#define\t\tbPD_TH\t\t\t0xf\n#define\t\tbPD_TH_Opt2\t\t0xc000\n#define\t\tbPWED_TH\t\t\t0x700\n#define\t\tbIfMF_Win_L\t\t0x800\n#define\t\tbPD_Option\t\t\t0x1000\n#define\t\tbMF_Win_L\t\t\t0xe000\n#define\t\tbBW_Search_L\t\t0x30000\n#define\t\tbwin_enh_L\t\t\t0xc0000\n#define\t\tbBW_TH\t\t\t0x700000\n#define\t\tbED_TH2\t\t\t0x3800000\n#define\t\tbBW_option\t\t\t0x4000000\n#define\t\tbRatio_TH\t\t\t0x18000000\n#define\t\tbWindow_L\t\t\t0xe0000000\n#define\t\tbSBD_Option\t\t0x1\n#define\t\tbFrame_TH\t\t\t0x1c\n#define\t\tbFS_Option\t\t\t0x60\n#define\t\tbDC_Slope_check\t\t0x80\n#define\t\tbFGuard_Counter_DC_L\t0xe00\n#define\t\tbFrame_Weight_Short\t0x7000\n#define\t\tbSub_Tune\t\t\t0xe00000\n#define\t\tbFrame_DC_Length\t\t0xe000000\n#define\t\tbSBD_start_offset\t\t0x30000000\n#define\t\tbFrame_TH_2\t\t0x7\n#define\t\tbFrame_GI2_TH\t\t0x38\n#define\t\tbGI2_Sync_en\t\t0x40\n#define\t\tbSarch_Short_Early\t\t0x300\n#define\t\tbSarch_Short_Late\t\t0xc00\n#define\t\tbSarch_GI2_Late\t\t0x70000\n#define\t\tbCFOAntSum\t\t0x1\n#define\t\tbCFOAcc\t\t\t0x2\n#define\t\tbCFOStartOffset\t\t0xc\n#define\t\tbCFOLookBack\t\t0x70\n#define\t\tbCFOSumWeight\t\t0x80\n#define\t\tbDAGCEnable\t\t0x10000\n#define\t\tbTXIQImb_A\t\t\t0x3ff\n#define\t\tbTXIQImb_B\t\t\t0xfc00\n#define\t\tbTXIQImb_C\t\t\t0x3f0000\n#define\t\tbTXIQImb_D\t\t\t0xffc00000\n#define\t\tbTxIDCOffset\t\t\t0xff\n#define\t\tbTxQDCOffset\t\t0xff00\n#define\t\tbTxDFIRMode\t\t0x10000\n#define\t\tbTxPesudoNoiseOn\t\t0x4000000\n#define\t\tbTxPesudoNoise_A\t\t0xff\n#define\t\tbTxPesudoNoise_B\t\t0xff00\n#define\t\tbTxPesudoNoise_C\t\t0xff0000\n#define\t\tbTxPesudoNoise_D\t\t0xff000000\n#define\t\tbCCADropOption\t\t0x20000\n#define\t\tbCCADropThres\t\t0xfff00000\n#define\t\tbEDCCA_H\t\t\t0xf\n#define\t\tbEDCCA_L\t\t\t0xf0\n#define\t\tbLambda_ED\t\t0x300\n#define\t\tbRxInitialGain\t\t\t0x7f\n#define\t\tbRxAntDivEn\t\t0x80\n#define\t\tbRxAGCAddressForLNA\t0x7f00\n#define\t\tbRxHighPowerFlow\t\t0x8000\n#define\t\tbRxAGCFreezeThres\t\t0xc0000\n#define\t\tbRxFreezeStep_AGC1\t0x300000\n#define\t\tbRxFreezeStep_AGC2\t0xc00000\n#define\t\tbRxFreezeStep_AGC3\t0x3000000\n#define\t\tbRxFreezeStep_AGC0\t0xc000000\n#define\t\tbRxRssi_Cmp_En\t\t0x10000000\n#define\t\tbRxQuickAGCEn\t\t0x20000000\n#define\t\tbRxAGCFreezeThresMode\t0x40000000\n#define\t\tbRxOverFlowCheckType\t0x80000000\n#define\t\tbRxAGCShift\t\t\t0x7f\n#define\t\tbTRSW_Tri_Only\t\t0x80\n#define\t\tbPowerThres\t\t0x300\n#define\t\tbRxAGCEn\t\t\t0x1\n#define\t\tbRxAGCTogetherEn\t\t0x2\n#define\t\tbRxAGCMin\t\t0x4\n#define\t\tbRxHP_Ini\t\t\t0x7\n#define\t\tbRxHP_TRLNA\t\t0x70\n#define\t\tbRxHP_RSSI\t\t\t0x700\n#define\t\tbRxHP_BBP1\t\t0x7000\n#define\t\tbRxHP_BBP2\t\t0x70000\n#define\t\tbRxHP_BBP3\t\t0x700000\n#define\t\tbRSSI_H                  \t\t\t0x7f0000     /* the threshold for high power */\n#define\t\tbRSSI_Gen                \t\t\t0x7f000000   /* the threshold for ant diversity */\n#define\t\tbRxSettle_TRSW\t\t0x7\n#define\t\tbRxSettle_LNA\t\t0x38\n#define\t\tbRxSettle_RSSI\t\t0x1c0\n#define\t\tbRxSettle_BBP\t\t0xe00\n#define\t\tbRxSettle_RxHP\t\t0x7000\n#define\t\tbRxSettle_AntSW_RSSI\t0x38000\n#define\t\tbRxSettle_AntSW\t\t0xc0000\n#define\t\tbRxProcessTime_DAGC\t0x300000\n#define\t\tbRxSettle_HSSI\t\t0x400000\n#define\t\tbRxProcessTime_BBPPW\t0x800000\n#define\t\tbRxAntennaPowerShift\t0x3000000\n#define\t\tbRSSITableSelect\t\t0xc000000\n#define\t\tbRxHP_Final\t\t\t0x7000000\n#define\t\tbRxHTSettle_BBP\t\t0x7\n#define\t\tbRxHTSettle_HSSI\t\t0x8\n#define\t\tbRxHTSettle_RxHP\t\t0x70\n#define\t\tbRxHTSettle_BBPPW\t\t0x80\n#define\t\tbRxHTSettle_Idle\t\t0x300\n#define\t\tbRxHTSettle_Reserved\t0x1c00\n#define\t\tbRxHTRxHPEn\t\t0x8000\n#define\t\tbRxHTAGCFreezeThres\t0x30000\n#define\t\tbRxHTAGCTogetherEn\t0x40000\n#define\t\tbRxHTAGCMin\t\t0x80000\n#define\t\tbRxHTAGCEn\t\t0x100000\n#define\t\tbRxHTDAGCEn\t\t0x200000\n#define\t\tbRxHTRxHP_BBP\t\t0x1c00000\n#define\t\tbRxHTRxHP_Final\t\t0xe0000000\n#define\t\tbRxPWRatioTH\t\t0x3\n#define\t\tbRxPWRatioEn\t\t0x4\n#define\t\tbRxMFHold\t\t\t0x3800\n#define\t\tbRxPD_Delay_TH1\t\t0x38\n#define\t\tbRxPD_Delay_TH2\t\t0x1c0\n#define\t\tbRxPD_DC_COUNT_MAX\t0x600\n/* #define bRxMF_Hold               0x3800 */\n#define\t\tbRxPD_Delay_TH\t\t0x8000\n#define\t\tbRxProcess_Delay\t\t0xf0000\n#define\t\tbRxSearchrange_GI2_Early\t0x700000\n#define\t\tbRxFrame_Guard_Counter_L\t0x3800000\n#define\t\tbRxSGI_Guard_L\t\t0xc000000\n#define\t\tbRxSGI_Search_L\t\t0x30000000\n#define\t\tbRxSGI_TH\t\t\t0xc0000000\n#define\t\tbDFSCnt0\t\t\t0xff\n#define\t\tbDFSCnt1\t\t\t0xff00\n#define\t\tbDFSFlag\t\t\t0xf0000\n#define\t\tbMFWeightSum\t\t0x300000\n#define\t\tbMinIdxTH\t\t\t0x7f000000\n#define\t\tbDAFormat\t\t\t0x40000\n#define\t\tbTxChEmuEnable\t\t0x01000000\n#define\t\tbTRSWIsolation_A\t\t0x7f\n#define\t\tbTRSWIsolation_B\t\t0x7f00\n#define\t\tbTRSWIsolation_C\t\t0x7f0000\n#define\t\tbTRSWIsolation_D\t\t0x7f000000\n#define\t\tbExtLNAGain\t\t0x7c00\n\n/* 6. PageE(0xE00) */\n#define\t\tbSTBCEn                  \t\t\t0x4\t/* Useless */\n#define\t\tbAntennaMapping\t\t0x10\n#define\t\tbNss\t\t\t0x20\n#define\t\tbCFOAntSumD\t\t0x200\n#define\t\tbPHYCounterReset\t\t0x8000000\n#define\t\tbCFOReportGet\t\t0x4000000\n#define\t\tbOFDMContinueTx\t\t0x10000000\n#define\t\tbOFDMSingleCarrier\t\t0x20000000\n#define\t\tbOFDMSingleTone\t\t0x40000000\n/* #define bRxPath1                 0x01 */\n/* #define bRxPath2                 0x02 */\n/* #define bRxPath3                 0x04 */\n/* #define bRxPath4                 0x08 */\n/* #define bTxPath1                 0x10 */\n/* #define bTxPath2                 0x20 */\n#define\t\tbHTDetect\t\t\t0x100\n#define\t\tbCFOEn\t\t\t0x10000\n#define\t\tbCFOValue\t\t\t0xfff00000\n#define\t\tbSigTone_Re\t\t\t0x3f\n#define\t\tbSigTone_Im\t\t\t0x7f00\n#define\t\tbCounter_CCA\t\t0xffff\n#define\t\tbCounter_ParityFail\t\t0xffff0000\n#define\t\tbCounter_RateIllegal\t\t0xffff\n#define\t\tbCounter_CRC8Fail\t\t0xffff0000\n#define\t\tbCounter_MCSNoSupport\t0xffff\n#define\t\tbCounter_FastSync\t\t0xffff\n#define\t\tbShortCFO\t\t\t0xfff\n#define\t\tbShortCFOTLength         \t\t12   /* total */\n#define\t\tbShortCFOFLength         \t\t11   /* fraction */\n#define\t\tbLongCFO\t\t\t0x7ff\n#define\t\tbLongCFOTLength\t\t11\n#define\t\tbLongCFOFLength\t\t11\n#define\t\tbTailCFO\t\t\t0x1fff\n#define\t\tbTailCFOTLength\t\t13\n#define\t\tbTailCFOFLength\t\t12\n#define\t\tbmax_en_pwdB\t\t0xffff\n#define\t\tbCC_power_dB\t\t0xffff0000\n#define\t\tbnoise_pwdB\t\t0xffff\n#define\t\tbPowerMeasTLength\t10\n#define\t\tbPowerMeasFLength\t3\n#define\t\tbRx_HT_BW\t\t0x1\n#define\t\tbRxSC\t\t\t0x6\n#define\t\tbRx_HT\t\t\t0x8\n#define\t\tbNB_intf_det_on\t\t0x1\n#define\t\tbIntf_win_len_cfg\t\t0x30\n#define\t\tbNB_Intf_TH_cfg\t\t0x1c0\n#define\t\tbRFGain\t\t\t0x3f\n#define\t\tbTableSel\t\t\t0x40\n#define\t\tbTRSW\t\t\t0x80\n#define\t\tbRxSNR_A\t\t\t0xff\n#define\t\tbRxSNR_B\t\t\t0xff00\n#define\t\tbRxSNR_C\t\t\t0xff0000\n#define\t\tbRxSNR_D\t\t\t0xff000000\n#define\t\tbSNREVMTLength\t\t8\n#define\t\tbSNREVMFLength\t\t1\n#define\t\tbCSI1st\t\t\t0xff\n#define\t\tbCSI2nd\t\t\t0xff00\n#define\t\tbRxEVM1st\t\t\t0xff0000\n#define\t\tbRxEVM2nd\t\t0xff000000\n#define\t\tbSIGEVM\t\t\t0xff\n#define\t\tbPWDB\t\t\t0xff00\n#define\t\tbSGIEN\t\t\t0x10000\n\n#define\t\tbSFactorQAM1             \t\t0xf\t/* Useless */\n#define\t\tbSFactorQAM2\t\t0xf0\n#define\t\tbSFactorQAM3\t\t0xf00\n#define\t\tbSFactorQAM4\t\t0xf000\n#define\t\tbSFactorQAM5\t\t0xf0000\n#define\t\tbSFactorQAM6\t\t0xf0000\n#define\t\tbSFactorQAM7\t\t0xf00000\n#define\t\tbSFactorQAM8\t\t0xf000000\n#define\t\tbSFactorQAM9\t\t0xf0000000\n#define\t\tbCSIScheme\t\t\t0x100000\n\n#define\t\tbNoiseLvlTopSet          \t\t0x3\t/* Useless */\n#define\t\tbChSmooth\t\t\t0x4\n#define\t\tbChSmoothCfg1\t\t0x38\n#define\t\tbChSmoothCfg2\t\t0x1c0\n#define\t\tbChSmoothCfg3\t\t0xe00\n#define\t\tbChSmoothCfg4\t\t0x7000\n#define\t\tbMRCMode\t\t0x800000\n#define\t\tbTHEVMCfg\t\t\t0x7000000\n\n#define\t\tbLoopFitType             \t\t\t0x1\t/* Useless */\n#define\t\tbUpdCFO\t\t\t0x40\n#define\t\tbUpdCFOOffData\t\t0x80\n#define\t\tbAdvUpdCFO\t\t0x100\n#define\t\tbAdvTimeCtrl\t\t0x800\n#define\t\tbUpdClko\t\t\t0x1000\n#define\t\tbFC\t\t\t\t0x6000\n#define\t\tbTrackingMode\t\t0x8000\n#define\t\tbPhCmpEnable\t\t0x10000\n#define\t\tbUpdClkoLTF\t\t\t0x20000\n#define\t\tbComChCFO\t\t0x40000\n#define\t\tbCSIEstiMode\t\t0x80000\n#define\t\tbAdvUpdEqz\t\t0x100000\n#define\t\tbUChCfg\t\t\t0x7000000\n#define\t\tbUpdEqz\t\t\t0x8000000\n\n/* Rx Pseduo noise */\n#define\t\tbRxPesudoNoiseOn         \t\t0x20000000\t/* Useless */\n#define\t\tbRxPesudoNoise_A\t\t0xff\n#define\t\tbRxPesudoNoise_B\t\t0xff00\n#define\t\tbRxPesudoNoise_C\t\t0xff0000\n#define\t\tbRxPesudoNoise_D\t\t0xff000000\n#define\t\tbPesudoNoiseState_A\t0xffff\n#define\t\tbPesudoNoiseState_B\t0xffff0000\n#define\t\tbPesudoNoiseState_C\t\t0xffff\n#define\t\tbPesudoNoiseState_D\t0xffff0000\n\n/* 7. RF Register\n * Zebra1 */\n#define\t\tbZebra1_HSSIEnable        \t\t0x8\t\t/* Useless */\n#define\t\tbZebra1_TRxControl\t\t0xc00\n#define\t\tbZebra1_TRxGainSetting\t0x07f\n#define\t\tbZebra1_RxCorner\t\t0xc00\n#define\t\tbZebra1_TxChargePump\t0x38\n#define\t\tbZebra1_RxChargePump\t0x7\n#define\t\tbZebra1_ChannelNum\t0xf80\n#define\t\tbZebra1_TxLPFBW\t\t0x400\n#define\t\tbZebra1_RxLPFBW\t\t0x600\n\n/* Zebra4 */\n#define\t\tbRTL8256RegModeCtrl1      \t0x100\t/* Useless */\n#define\t\tbRTL8256RegModeCtrl0\t0x40\n#define\t\tbRTL8256_TxLPFBW\t0x18\n#define\t\tbRTL8256_RxLPFBW\t0x600\n\n/* RTL8258 */\n#define\t\tbRTL8258_TxLPFBW          \t0xc\t/* Useless */\n#define\t\tbRTL8258_RxLPFBW\t0xc00\n#define\t\tbRTL8258_RSSILPFBW\t0xc0\n\n\n/*\n * Other Definition\n *   */\n\n/* byte endable for sb_write */\n#define\t\tbByte0                    \t\t\t0x1\t/* Useless */\n#define\t\tbByte1\t\t\t0x2\n#define\t\tbByte2\t\t\t0x4\n#define\t\tbByte3\t\t\t0x8\n#define\t\tbWord0\t\t\t0x3\n#define\t\tbWord1\t\t\t0xc\n#define\t\tbDWord\t\t\t0xf\n\n/* for PutRegsetting & GetRegSetting BitMask */\n#define\t\tbMaskByte0                \t\t0xff\t/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */\n#define\t\tbMaskByte1\t\t0xff00\n#define\t\tbMaskByte2\t\t0xff0000\n#define\t\tbMaskByte3\t\t0xff000000\n#define\t\tbMaskHWord\t\t0xffff0000\n#define\t\tbMaskLWord\t\t0x0000ffff\n#define\t\tbMaskDWord\t\t0xffffffff\n#define\t\tbMaskH3Bytes\t\t\t\t0xffffff00\n#define\t\tbMask12Bits\t\t\t\t0xfff\n#define\t\tbMaskH4Bits\t\t\t\t0xf0000000\n#define\t\tbMaskOFDM_D\t\t\t0xffc00000\n#define\t\tbMaskCCK\t\t\t\t0x3f3f3f3f\n\n/* for PutRFRegsetting & GetRFRegSetting BitMask\n * #define\t\tbMask12Bits               0xfffff */\t/* RF Reg mask bits\n * #define\t\tbMask20Bits               0xfffff */\t/* RF Reg mask bits T65 RF */\n#define\t\tbRFRegOffsetMask\t\t\t0xfffff\n\n#define\t\tbEnable                   0x1\t/* Useless */\n#define\t\tbDisable                  0x0\n\n#define\t\tLeftAntenna               \t\t\t0x0\t/* Useless */\n#define\t\tRightAntenna\t\t0x1\n\n#define\t\ttCheckTxStatus            \t\t500   /* 500ms */ /* Useless */\n#define\t\ttUpdateRxCounter          \t\t100   /* 100ms */\n\n#define\t\trateCCK     \t\t\t\t0\t/* Useless */\n#define\t\trateOFDM\t\t\t\t1\n#define\t\trateHT\t\t\t\t\t2\n\n/* define Register-End */\n#define\t\tbPMAC_End                 \t\t0x1ff\t/* Useless */\n#define\t\tbFPGAPHY0_End\t\t0x8ff\n#define\t\tbFPGAPHY1_End\t\t0x9ff\n#define\t\tbCCKPHY0_End\t\t0xaff\n#define\t\tbOFDMPHY0_End\t\t0xcff\n#define\t\tbOFDMPHY1_End\t\t0xdff\n\n/* define max debug item in each debug page\n * #define bMaxItem_FPGA_PHY0        0x9\n * #define bMaxItem_FPGA_PHY1        0x3\n * #define bMaxItem_PHY_11B          0x16\n * #define bMaxItem_OFDM_PHY0        0x29\n * #define bMaxItem_OFDM_PHY1        0x0 */\n\n#define\t\tbPMACControl              \t\t0x0\t\t/* Useless */\n#define\t\tbWMACControl\t\t0x1\n#define\t\tbWNICControl\t\t0x2\n\n#define\t\tPathA                     \t\t\t0x0\t/* Useless */\n#define\t\tPathB\t\t\t0x1\n#define\t\tPathC\t\t\t0x2\n#define\t\tPathD\t\t\t0x3\n\n\n/* RSSI Dump Message */\n#define\t\trA_RSSIDump_92E\t\t\t0xcb0\n#define\t\trB_RSSIDump_92E\t\t\t0xcb1\n#define\t\trS1_RXevmDump_92E\t\t\t0xcb2\n#define\t\trS2_RXevmDump_92E\t\t\t0xcb3\n#define\t\trA_RXsnrDump_92E\t\t\t0xcb4\n#define\t\trB_RXsnrDump_92E\t\t\t0xcb5\n#define\t\trA_CfoShortDump_92E\t\t0xcb6\n#define\t\trB_CfoShortDump_92E\t\t0xcb8\n#define\trA_CfoLongDump_92E\t\t\t0xcba\n#define\t\trB_CfoLongDump_92E\t\t\t0xcbc\n\n/*--------------------------Define Parameters-------------------------------*/\n\n\n#endif /* __INC_HAL8188EPHYREG_H */\n"
  },
  {
    "path": "include/Hal8192EPwrSeq.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2012 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef REALTEK_POWER_SEQUENCE_8192E\n#define REALTEK_POWER_SEQUENCE_8192E\n\n#include \"HalPwrSeqCmd.h\"\n/*\n\tCheck document WM-20110607-Paul-RTL8192E_Power_Architecture-R02.vsd\n\tThere are 6 HW Power States:\n\t0: POFF--Power Off\n\t1: PDN--Power Down\n\t2: CARDEMU--Card Emulation\n\t3: ACT--Active Mode\n\t4: LPS--Low Power State\n\t5: SUS--Suspend\n\n\tThe transision from different states are defined below\n\tTRANS_CARDEMU_TO_ACT\n\tTRANS_ACT_TO_CARDEMU\n\tTRANS_CARDEMU_TO_SUS\n\tTRANS_SUS_TO_CARDEMU\n\tTRANS_CARDEMU_TO_PDN\n\tTRANS_ACT_TO_LPS\n\tTRANS_LPS_TO_ACT\n\n\tTRANS_END\n*/\n#define\tRTL8192E_TRANS_CARDEMU_TO_ACT_STEPS\t18\n#define\tRTL8192E_TRANS_ACT_TO_CARDEMU_STEPS\t18\n#define\tRTL8192E_TRANS_CARDEMU_TO_SUS_STEPS\t18\n#define\tRTL8192E_TRANS_SUS_TO_CARDEMU_STEPS\t18\n#define\tRTL8192E_TRANS_CARDEMU_TO_PDN_STEPS\t18\n#define\tRTL8192E_TRANS_PDN_TO_CARDEMU_STEPS\t18\n#define\tRTL8192E_TRANS_ACT_TO_LPS_STEPS\t23\n#define\tRTL8192E_TRANS_LPS_TO_ACT_STEPS\t23\n#define\tRTL8192E_TRANS_END_STEPS\t1\n\n\n#define RTL8192E_TRANS_CARDEMU_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/\t\\\n\n\n#define RTL8192E_TRANS_ACT_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/\t\\\n\t{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/\t\\\n\n\n#define RTL8192E_TRANS_CARDEMU_TO_SUS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/\n\n#define RTL8192E_TRANS_SUS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\n\n#define RTL8192E_TRANS_CARDEMU_TO_CARDDIS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/\t\\\n\t{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*Unlock small LDO Register*/\t\\\n\t{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*Disable small LDO*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/\n\n#define RTL8192E_TRANS_CARDDIS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\\\n\t{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*Enable small LDO*/\t\\\n\t{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*Lock small LDO Register*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\\\n\n\n#define RTL8192E_TRANS_CARDEMU_TO_PDN\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/\n\n#define RTL8192E_TRANS_PDN_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/\n\n#define RTL8192E_TRANS_ACT_TO_LPS\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/\t\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/\t\\\n\t{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/\t\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/\t\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\t\\\n\t{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/\t\\\n\t{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/\t\\\n\n\n#define RTL8192E_TRANS_LPS_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM, For Repeatly In and out, Taggle bit should be changed*/\\\n\t{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\\\n\t{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.\t0x08[4] = 0\t\t switch TSF to 40M*/\\\n\t{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.\t0x101[1] = 1*/\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.\t0x100[7:0] = 0xFF\t enable WMAC TRX*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.\t0x02[1:0] = 2b'11\t enable BB macro*/\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.\t0x522 = 0*/\\\n\t{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*Clear ISR*/\n\n#define RTL8192E_TRANS_END\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},\n\n\n\textern WLAN_PWR_CFG rtl8192E_power_on_flow[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8192E_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8192E_radio_off_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8192E_card_disable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8192E_card_enable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8192E_suspend_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8192E_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8192E_resume_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8192E_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8192E_hwpdn_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8192E_enter_lps_flow[RTL8192E_TRANS_ACT_TO_LPS_STEPS + RTL8192E_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8192E_leave_lps_flow[RTL8192E_TRANS_LPS_TO_ACT_STEPS + RTL8192E_TRANS_END_STEPS];\n\n#endif\n"
  },
  {
    "path": "include/Hal8192FPhyCfg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8192FPHYCFG_H__\n#define __INC_HAL8192FPHYCFG_H__\n\n/*--------------------------Define Parameters-------------------------------*/\n#define LOOP_LIMIT\t\t\t\t5\n#define MAX_STALL_TIME\t\t\t50\t\t/* us */\n#define AntennaDiversityValue\t0x80\t/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */\n#define MAX_TXPWR_IDX_NMODE_92S\t63\n#define Reset_Cnt_Limit\t\t\t3\n\n#ifdef CONFIG_PCI_HCI\n\t#define MAX_AGGR_NUM\t0x0B\n#else\n\t#define MAX_AGGR_NUM\t0x07\n#endif /* CONFIG_PCI_HCI */\n\n\n/*--------------------------Define Parameters End-------------------------------*/\n\n\n/*------------------------------Define structure----------------------------*/\n\n/*------------------------------Define structure End----------------------------*/\n\n/*--------------------------Exported Function prototype---------------------*/\nu32\nPHY_QueryBBReg_8192F(\n\t\tPADAPTER\tAdapter,\n\t\tu32\t\tRegAddr,\n\t\tu32\t\tBitMask\n);\n\nvoid\nPHY_SetBBReg_8192F(\n\t\tPADAPTER\tAdapter,\n\t\tu32\t\tRegAddr,\n\t\tu32\t\tBitMask,\n\t\tu32\t\tData\n);\n\nu32\nPHY_QueryRFReg_8192F(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tRegAddr,\n\t\tu32\t\t\t\tBitMask\n);\n\nvoid\nPHY_SetRFReg_8192F(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tRegAddr,\n\t\tu32\t\t\t\tBitMask,\n\t\tu32\t\t\t\tData\n);\n\n/* MAC/BB/RF HAL config */\nint PHY_BBConfig8192F(PADAPTER\tAdapter\t);\n\nint PHY_RFConfig8192F(PADAPTER\tAdapter);\n\ns32 PHY_MACConfig8192F(PADAPTER padapter);\n\nint\nPHY_ConfigRFWithParaFile_8192F(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu8\t\t\t\t*pFileName,\n\tenum rf_path\t\t\t\teRFPath\n);\n\nvoid\nPHY_SetTxPowerIndex_8192F(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu32\t\t\t\t\tPowerIndex,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate\n);\n\nu8\nPHY_GetTxPowerIndex_8192F(\n\t\tPADAPTER\t\t\tpAdapter,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate,\n\t\tu8\t\t\t\t\tBandWidth,\n\t\tu8\t\t\t\t\tChannel,\n\tstruct txpwr_idx_comp *tic\n);\n\nvoid\nPHY_SetTxPowerLevel8192F(\n\t\tPADAPTER\t\tAdapter,\n\t\tu8\t\t\tchannel\n);\n\nvoid\nPHY_SetSwChnlBWMode8192F(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu8\t\t\t\t\tchannel,\n\t\tenum channel_width\tBandwidth,\n\t\tu8\t\t\t\t\tOffset40,\n\t\tu8\t\t\t\t\tOffset80\n);\n\nvoid phy_set_rf_path_switch_8192f(\n\t\tPADAPTER\tpAdapter,\n\t\tbool\t\tbMain\n);\n/*--------------------------Exported Function prototype End---------------------*/\n\n#endif\n"
  },
  {
    "path": "include/Hal8192FPhyReg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8192FPHYREG_H__\n#define __INC_HAL8192FPHYREG_H__\n\n#define\t\trSYM_WLBT_PAPE_SEL\t\t0x64\n/*\n * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00\n * 3. RF register 0x00-2E\n * 4. Bit Mask for BB/RF register\n * 5. Other definition for BB/RF R/W\n *   */\n\n\n/*\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 1. Page1(0x100)\n *   */\n#define\t\trPMAC_Reset\t\t\t\t\t0x100\n#define\t\trPMAC_TxStart\t\t\t\t\t0x104\n#define\t\trPMAC_TxLegacySIG\t\t\t\t0x108\n#define\t\trPMAC_TxHTSIG1\t\t\t\t0x10c\n#define\t\trPMAC_TxHTSIG2\t\t\t\t0x110\n#define\t\trPMAC_PHYDebug\t\t\t\t0x114\n#define\t\trPMAC_TxPacketNum\t\t\t\t0x118\n#define\t\trPMAC_TxIdle\t\t\t\t\t0x11c\n#define\t\trPMAC_TxMACHeader0\t\t\t0x120\n#define\t\trPMAC_TxMACHeader1\t\t\t0x124\n#define\t\trPMAC_TxMACHeader2\t\t\t0x128\n#define\t\trPMAC_TxMACHeader3\t\t\t0x12c\n#define\t\trPMAC_TxMACHeader4\t\t\t0x130\n#define\t\trPMAC_TxMACHeader5\t\t\t0x134\n#define\t\trPMAC_TxDataType\t\t\t\t0x138\n#define\t\trPMAC_TxRandomSeed\t\t\t0x13c\n#define\t\trPMAC_CCKPLCPPreamble\t\t\t0x140\n#define\t\trPMAC_CCKPLCPHeader\t\t\t0x144\n#define\t\trPMAC_CCKCRC16\t\t\t\t0x148\n#define\t\trPMAC_OFDMRxCRC32OK\t\t\t0x170\n#define\t\trPMAC_OFDMRxCRC32Er\t\t\t0x174\n#define\t\trPMAC_OFDMRxParityEr\t\t\t0x178\n#define\t\trPMAC_OFDMRxCRC8Er\t\t\t0x17c\n#define\t\trPMAC_CCKCRxRC16Er\t\t\t0x180\n#define\t\trPMAC_CCKCRxRC32Er\t\t\t0x184\n#define\t\trPMAC_CCKCRxRC32OK\t\t\t0x188\n#define\t\trPMAC_TxStatus\t\t\t\t\t0x18c\n\n/*\n * 2. Page2(0x200)\n *\n * The following two definition are only used for USB interface. */\n#define\t\tRF_BB_CMD_ADDR\t\t\t\t0x02c0\t/* RF/BB read/write command address. */\n#define\t\tRF_BB_CMD_DATA\t\t\t\t0x02c4\t/* RF/BB read/write command data. */\n\n/*\n * 3. Page8(0x800)\n *   */\n#define\t\trFPGA0_RFMOD\t\t\t\t0x800\t/* RF mode & CCK TxSC // RF BW Setting?? */\n\n#define\t\trFPGA0_TxInfo\t\t\t\t0x804\t/* Status report?? */\n#define\t\trFPGA0_PSDFunction\t\t\t0x808\n\n#define\t\trFPGA0_TxGainStage\t\t\t0x80c\t/* Set TX PWR init gain? */\n\n#define\t\trFPGA0_RFTiming1\t\t\t0x810\t/* Useless now */\n#define\t\trFPGA0_RFTiming2\t\t\t0x814\n\n#define\t\trFPGA0_XA_HSSIParameter1\t\t0x820\t/* RF 3 wire register */\n#define\t\trFPGA0_XA_HSSIParameter2\t\t0x824\n#define\t\trFPGA0_XB_HSSIParameter1\t\t0x828\n#define\t\trFPGA0_XB_HSSIParameter2\t\t0x82c\n#define\t\trTxAGC_B_Rate18_06\t\t\t\t0x830\n#define\t\trTxAGC_B_Rate54_24\t\t\t\t0x834\n#define\t\trTxAGC_B_CCK1_55_Mcs32\t\t0x838\n#define\t\trTxAGC_B_Mcs03_Mcs00\t\t\t0x83c\n\n#define\t\trTxAGC_B_Mcs07_Mcs04\t\t\t0x848\n#define\t\trTxAGC_B_Mcs11_Mcs08\t\t\t0x84c\n\n#define\t\trFPGA0_XA_LSSIParameter\t\t0x840\n#define\t\trFPGA0_XB_LSSIParameter\t\t0x844\n\n#define\t\trFPGA0_RFWakeUpParameter\t\t0x850\t/* Useless now */\n#define\t\trFPGA0_RFSleepUpParameter\t\t0x854\n\n#define\t\trFPGA0_XAB_SwitchControl\t\t0x858\t/* RF Channel switch */\n#define\t\trFPGA0_XCD_SwitchControl\t\t0x85c\n\n#define\t\trFPGA0_XA_RFInterfaceOE\t\t0x860\t/* RF Channel switch */\n#define\t\trFPGA0_XB_RFInterfaceOE\t\t0x864\n\n#define\t\trTxAGC_B_Mcs15_Mcs12\t\t\t0x868\n#define\t\trTxAGC_B_CCK11_A_CCK2_11\t\t0x86c\n\n#define\t\trFPGA0_XAB_RFInterfaceSW\t\t0x870\t/* RF Interface Software Control */\n#define\t\trFPGA0_XCD_RFInterfaceSW\t\t0x874\n\n#define\t\trFPGA0_XAB_RFParameter\t\t0x878\t/* RF Parameter */\n#define\t\trFPGA0_XCD_RFParameter\t\t0x87c\n\n#define\t\trFPGA0_AnalogParameter1\t\t0x880\t/* Crystal cap setting RF-R/W protection for parameter4?? */\n#define\t\trFPGA0_AnalogParameter2\t\t0x884\n#define\t\trFPGA0_AnalogParameter3\t\t0x888\t/* Useless now */\n#define\t\trFPGA0_AnalogParameter4\t\t0x88c\n\n#define\t\trFPGA0_XA_LSSIReadBack\t\t0x8a0\t/* Tranceiver LSSI Readback */\n#define\t\trFPGA0_XB_LSSIReadBack\t\t0x8a4\n#define\t\trFPGA0_XC_LSSIReadBack\t\t0x8a8\n#define\t\trFPGA0_XD_LSSIReadBack\t\t0x8ac\n\n#define\t\trFPGA0_PSDReport\t\t\t\t0x8b4\t/* Useless now */\n#define\t\tTransceiverA_HSPI_Readback\t0x8b8\t/* Transceiver A HSPI Readback */\n#define\t\tTransceiverB_HSPI_Readback\t0x8bc\t/* Transceiver B HSPI Readback */\n#define\t\trFPGA0_XAB_RFInterfaceRB\t\t0x8e0\t/* Useless now // RF Interface Readback Value */\n#define\t\trFPGA0_XCD_RFInterfaceRB\t\t0x8e4\t/* Useless now */\n\n/*\n * 4. Page9(0x900)\n *   */\n#define\trFPGA1_RFMOD\t\t\t\t0x900\t/* RF mode & OFDM TxSC // RF BW Setting?? */\n#define\trFPGA1_TxBlock\t\t\t\t0x904\t/* Useless now */\n#define\trFPGA1_DebugSelect\t\t\t0x908\t/* Useless now */\n#define\trFPGA1_TxInfo\t\t\t\t0x90c\t/* Useless now // Status report?? */\n#define\trDPDT_control\t\t\t\t0x92c\n#define\trfe_ctrl_anta_src\t\t\t\t0x930\n#define\trS0S1_PathSwitch\t\t\t0x948\n#define\trBBrx_DFIR\t\t\t\t\t0x954\n\n/*\n * 5. PageA(0xA00)\n *\n * Set Control channel to upper or lower. These settings are required only for 40MHz */\n#define\t\trCCK0_System\t\t\t\t0xa00\n\n#define\t\trCCK0_AFESetting\t\t\t0xa04\t/* Disable init gain now // Select RX path by RSSI */\n#define\t\trCCK0_CCA\t\t\t\t\t0xa08\t/* Disable init gain now // Init gain */\n\n#define\t\trCCK0_RxAGC1\t\t\t\t0xa0c\t/* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */\n#define\t\trCCK0_RxAGC2\t\t\t\t0xa10\t/* AGC & DAGC */\n\n#define\t\trCCK0_RxHP\t\t\t\t\t0xa14\n\n#define\t\trCCK0_DSPParameter1\t\t0xa18\t/* Timing recovery & Channel estimation threshold */\n#define\t\trCCK0_DSPParameter2\t\t0xa1c\t/* SQ threshold */\n\n#define\t\trCCK0_TxFilter1\t\t\t\t0xa20\n#define\t\trCCK0_TxFilter2\t\t\t\t0xa24\n#define\t\trCCK0_DebugPort\t\t\t0xa28\t/* debug port and Tx filter3 */\n#define\t\trCCK0_FalseAlarmReport\t\t0xa2c\t/* 0xa2d\tuseless now 0xa30-a4f channel report */\n#define\t\trCCK0_TRSSIReport\t\t0xa50\n#define\t\trCCK0_RxReport\t\t\t0xa54  /* 0xa57 */\n#define\t\trCCK0_FACounterLower\t\t0xa5c  /* 0xa5b */\n#define\t\trCCK0_FACounterUpper\t\t0xa58  /* 0xa5c */\n\n/*\n * PageB(0xB00)\n *   */\n#define rPdp_AntA\t\t\t\t\t\t0xb00\n#define rPdp_AntA_4\t\t\t\t\t\t0xb04\n#define rPdp_AntA_8\t\t\t\t\t\t0xb08\n#define rPdp_AntA_C\t\t\t\t\t\t0xb0c\n#define rPdp_AntA_10\t\t\t\t\t0xb10\n#define rPdp_AntA_14\t\t\t\t\t0xb14\n#define rPdp_AntA_18\t\t\t\t\t0xb18\n#define rPdp_AntA_1C\t\t\t\t\t0xb1c\n#define rPdp_AntA_20\t\t\t\t\t0xb20\n#define rPdp_AntA_24\t\t\t\t\t0xb24\n\n#define rConfig_Pmpd_AntA\t\t\t\t0xb28\n#define rConfig_ram64x16\t\t\t\t0xb2c\n\n#define rBndA\t\t\t\t\t\t\t0xb30\n#define rHssiPar\t\t\t\t\t\t0xb34\n\n#define rConfig_AntA\t\t\t\t\t0xb68\n#define rConfig_AntB\t\t\t\t\t0xb6c\n\n#define rPdp_AntB\t\t\t\t\t\t0xb70\n#define rPdp_AntB_4\t\t\t\t\t\t0xb74\n#define rPdp_AntB_8\t\t\t\t\t\t0xb78\n#define rPdp_AntB_C\t\t\t\t\t\t0xb7c\n#define rPdp_AntB_10\t\t\t\t\t0xb80\n#define rPdp_AntB_14\t\t\t\t\t0xb84\n#define rPdp_AntB_18\t\t\t\t\t0xb88\n#define rPdp_AntB_1C\t\t\t\t\t0xb8c\n#define rPdp_AntB_20\t\t\t\t\t0xb90\n#define rPdp_AntB_24\t\t\t\t\t0xb94\n\n#define rConfig_Pmpd_AntB\t\t\t\t0xb98\n\n#define rBndB\t\t\t\t\t\t\t0xba0\n\n#define rAPK\t\t\t\t\t\t\t0xbd8\n#define rPm_Rx0_AntA\t\t\t\t\t0xbdc\n#define rPm_Rx1_AntA\t\t\t\t\t0xbe0\n#define rPm_Rx2_AntA\t\t\t\t\t0xbe4\n#define rPm_Rx3_AntA\t\t\t\t\t0xbe8\n#define rPm_Rx0_AntB\t\t\t\t\t0xbec\n#define rPm_Rx1_AntB\t\t\t\t\t0xbf0\n#define rPm_Rx2_AntB\t\t\t\t\t0xbf4\n#define rPm_Rx3_AntB\t\t\t\t\t0xbf8\n/*\n * 6. PageC(0xC00)\n *   */\n#define\t\trOFDM0_LSTF\t\t\t\t0xc00\n\n#define\t\trOFDM0_TRxPathEnable\t\t0xc04\n#define\t\trOFDM0_TRMuxPar\t\t\t0xc08\n#define\t\trOFDM0_TRSWIsolation\t\t0xc0c\n\n#define\t\trOFDM0_XARxAFE\t\t\t0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */\n#define\t\trOFDM0_XARxIQImbalance\t\t0xc14  /* RxIQ imbalance matrix */\n#define\t\trOFDM0_XBRxAFE\t\t0xc18\n#define\t\trOFDM0_XBRxIQImbalance\t0xc1c\n#define\t\trOFDM0_XCRxAFE\t\t0xc20\n#define\t\trOFDM0_XCRxIQImbalance\t0xc24\n#define\t\trOFDM0_XDRxAFE\t\t0xc28\n#define\t\trOFDM0_XDRxIQImbalance\t0xc2c\n\n#define\t\trOFDM0_RxDetector1\t\t\t0xc30  /* PD, BW & SBD\t// DM tune init gain */\n#define\t\trOFDM0_RxDetector2\t\t\t0xc34  /* SBD & Fame Sync. */\n#define\t\trOFDM0_RxDetector3\t\t\t0xc38  /* Frame Sync. */\n#define\t\trOFDM0_RxDetector4\t\t\t0xc3c  /* PD, SBD, Frame Sync & Short-GI */\n\n#define\t\trOFDM0_RxDSP\t\t\t\t0xc40  /* Rx Sync Path */\n#define\t\trOFDM0_CFOandDAGC\t\t0xc44  /* CFO & DAGC */\n#define\t\trOFDM0_CCADropThreshold\t0xc48 /* CCA Drop threshold */\n#define\t\trOFDM0_ECCAThreshold\t\t0xc4c /* energy CCA */\n\n#define\t\trOFDM0_XAAGCCore1\t\t\t0xc50\t/* DIG */\n#define\t\trOFDM0_XAAGCCore2\t\t\t0xc54\n#define\t\trOFDM0_XBAGCCore1\t\t\t0xc58\n#define\t\trOFDM0_XBAGCCore2\t\t\t0xc5c\n#define\t\trOFDM0_XCAGCCore1\t\t\t0xc60\n#define\t\trOFDM0_XCAGCCore2\t\t\t0xc64\n#define\t\trOFDM0_XDAGCCore1\t\t\t0xc68\n#define\t\trOFDM0_XDAGCCore2\t\t\t0xc6c\n\n#define\t\trOFDM0_AGCParameter1\t\t\t0xc70\n#define\t\trOFDM0_AGCParameter2\t\t\t0xc74\n#define\t\trOFDM0_AGCRSSITable\t\t\t0xc78\n#define\t\trOFDM0_HTSTFAGC\t\t\t\t0xc7c\n\n#define\t\trOFDM0_XATxIQImbalance\t\t0xc80\t/* TX PWR TRACK and DIG */\n#define\t\trOFDM0_XATxAFE\t\t\t\t0xc84\n#define\t\trOFDM0_XBTxIQImbalance\t\t0xc88\n#define\t\trOFDM0_XBTxAFE\t\t\t\t0xc8c\n#define\t\trOFDM0_XCTxIQImbalance\t\t0xc90\n#define\t\trOFDM0_XCTxAFE\t\t\t0xc94\n#define\t\trOFDM0_XDTxIQImbalance\t\t0xc98\n#define\t\trOFDM0_XDTxAFE\t\t\t\t0xc9c\n\n#define\t\trOFDM0_RxIQExtAnta\t\t\t0xca0\n#define\t\trOFDM0_TxCoeff1\t\t\t\t0xca4\n#define\t\trOFDM0_TxCoeff2\t\t\t\t0xca8\n#define\t\trOFDM0_TxCoeff3\t\t\t\t0xcac\n#define\t\trOFDM0_TxCoeff4\t\t\t\t0xcb0\n#define\t\trOFDM0_TxCoeff5\t\t\t\t0xcb4\n#define\t\trOFDM0_TxCoeff6\t\t\t\t0xcb8\n#define\t\trOFDM0_RxHPParameter\t\t\t0xce0\n#define\t\trOFDM0_TxPseudoNoiseWgt\t\t0xce4\n#define\t\trOFDM0_FrameSync\t\t\t\t0xcf0\n#define\t\trOFDM0_DFSReport\t\t\t\t0xcf4\n\n/*\n * 7. PageD(0xD00)\n *   */\n#define\t\trOFDM1_LSTF\t\t\t\t\t0xd00\n#define\t\trOFDM1_TRxPathEnable\t\t\t0xd04\n\n#define\t\trOFDM1_CFO\t\t\t\t\t\t0xd08\t/* No setting now */\n#define\t\trOFDM1_CSI1\t\t\t\t\t0xd10\n#define\t\trOFDM1_SBD\t\t\t\t\t\t0xd14\n#define\t\trOFDM1_CSI2\t\t\t\t\t0xd18\n#define\t\trOFDM1_CFOTracking\t\t\t0xd2c\n#define\t\trOFDM1_TRxMesaure1\t\t\t0xd34\n#define\t\trOFDM1_IntfDet\t\t\t\t\t0xd3c\n#define\t\trOFDM1_PseudoNoiseStateAB\t\t0xd50\n#define\t\trOFDM1_PseudoNoiseStateCD\t\t0xd54\n#define\t\trOFDM1_RxPseudoNoiseWgt\t\t0xd58\n\n#define\t\trOFDM_PHYCounter1\t\t\t\t0xda0  /* cca, parity fail */\n#define\t\trOFDM_PHYCounter2\t\t\t\t0xda4  /* rate illegal, crc8 fail */\n#define\t\trOFDM_PHYCounter3\t\t\t\t0xda8  /* MCS not support */\n\n#define\t\trOFDM_ShortCFOAB\t\t\t\t0xdac\t/* No setting now */\n#define\t\trOFDM_ShortCFOCD\t\t\t\t0xdb0\n#define\t\trOFDM_LongCFOAB\t\t\t\t0xdb4\n#define\t\trOFDM_LongCFOCD\t\t\t\t0xdb8\n#define\t\trOFDM_TailCFOAB\t\t\t\t0xdbc\n#define\t\trOFDM_TailCFOCD\t\t\t\t0xdc0\n#define\t\trOFDM_PWMeasure1\t\t0xdc4\n#define\t\trOFDM_PWMeasure2\t\t0xdc8\n#define\t\trOFDM_BWReport\t\t\t\t0xdcc\n#define\t\trOFDM_AGCReport\t\t\t\t0xdd0\n#define\t\trOFDM_RxSNR\t\t\t\t\t0xdd4\n#define\t\trOFDM_RxEVMCSI\t\t\t\t0xdd8\n#define\t\trOFDM_SIGReport\t\t\t\t0xddc\n\n\n/*\n * 8. PageE(0xE00)\n *   */\n#define\t\trTxAGC_A_Rate18_06\t\t\t0xe00\n#define\t\trTxAGC_A_Rate54_24\t\t\t0xe04\n#define\t\trTxAGC_A_CCK1_Mcs32\t\t\t0xe08\n#define\t\trTxAGC_A_Mcs03_Mcs00\t\t\t0xe10\n#define\t\trTxAGC_A_Mcs07_Mcs04\t\t\t0xe14\n#define\t\trTxAGC_A_Mcs11_Mcs08\t\t\t0xe18\n#define\t\trTxAGC_A_Mcs15_Mcs12\t\t\t0xe1c\n\n#define\t\trFPGA0_IQK\t\t\t\t\t0xe28\n#define\t\trTx_IQK_Tone_A\t\t\t\t0xe30\n#define\t\trRx_IQK_Tone_A\t\t\t\t0xe34\n#define\t\trTx_IQK_PI_A\t\t\t\t\t0xe38\n#define\t\trRx_IQK_PI_A\t\t\t\t\t0xe3c\n\n#define\t\trTx_IQK\t\t\t\t\t\t0xe40\n#define\t\trRx_IQK\t\t\t\t\t\t0xe44\n#define\t\trIQK_AGC_Pts\t\t\t\t\t0xe48\n#define\t\trIQK_AGC_Rsp\t\t\t\t\t0xe4c\n#define\t\trTx_IQK_Tone_B\t\t\t\t0xe50\n#define\t\trRx_IQK_Tone_B\t\t\t\t0xe54\n#define\t\trTx_IQK_PI_B\t\t\t\t\t0xe58\n#define\t\trRx_IQK_PI_B\t\t\t\t\t0xe5c\n#define\t\trIQK_AGC_Cont\t\t\t\t0xe60\n\n#define\t\trBlue_Tooth\t\t\t\t\t0xe6c\n#define\t\trRx_Wait_CCA\t\t\t\t\t0xe70\n#define\t\trTx_CCK_RFON\t\t\t\t\t0xe74\n#define\t\trTx_CCK_BBON\t\t\t\t0xe78\n#define\t\trTx_OFDM_RFON\t\t\t\t0xe7c\n#define\t\trTx_OFDM_BBON\t\t\t\t0xe80\n#define\t\trTx_To_Rx\t\t\t\t\t0xe84\n#define\t\trTx_To_Tx\t\t\t\t\t0xe88\n#define\t\trRx_CCK\t\t\t\t\t\t0xe8c\n\n#define\t\trTx_Power_Before_IQK_A\t\t0xe94\n#define\t\trTx_Power_After_IQK_A\t\t\t0xe9c\n\n#define\t\trRx_Power_Before_IQK_A\t\t0xea0\n#define\t\trRx_Power_Before_IQK_A_2\t\t0xea4\n#define\t\trRx_Power_After_IQK_A\t\t\t0xea8\n#define\t\trRx_Power_After_IQK_A_2\t\t0xeac\n\n#define\t\trTx_Power_Before_IQK_B\t\t0xeb4\n#define\t\trTx_Power_After_IQK_B\t\t\t0xebc\n\n#define\t\trRx_Power_Before_IQK_B\t\t0xec0\n#define\t\trRx_Power_Before_IQK_B_2\t\t0xec4\n#define\t\trRx_Power_After_IQK_B\t\t\t0xec8\n#define\t\trRx_Power_After_IQK_B_2\t\t0xecc\n\n#define\t\trRx_OFDM\t\t\t\t\t0xed0\n#define\t\trRx_Wait_RIFS\t\t\t\t0xed4\n#define\t\trRx_TO_Rx\t\t\t\t\t0xed8\n#define\t\trStandby\t\t\t\t\t\t0xedc\n#define\t\trSleep\t\t\t\t\t\t0xee0\n#define\t\trPMPD_ANAEN\t\t\t\t0xeec\n\n/*\n * 7. RF Register 0x00-0x2E (RF 8256)\n * RF-0222D 0x00-3F\n *\n * Zebra1 */\n#define\t\trZebra1_HSSIEnable\t\t\t\t0x0\t/* Useless now */\n#define\t\trZebra1_TRxEnable1\t\t\t\t0x1\n#define\t\trZebra1_TRxEnable2\t\t\t\t0x2\n#define\t\trZebra1_AGC\t\t\t\t\t0x4\n#define\t\trZebra1_ChargePump\t\t\t0x5\n#define\t\trZebra1_Channel\t\t\t\t0x7\t/* RF channel switch */\n\n/* #endif */\n#define\t\trZebra1_TxGain\t\t\t\t\t0x8\t/* Useless now */\n#define\t\trZebra1_TxLPF\t\t\t\t\t0x9\n#define\t\trZebra1_RxLPF\t\t\t\t\t0xb\n#define\t\trZebra1_RxHPFCorner\t\t\t0xc\n\n/* Zebra4 */\n#define\t\trGlobalCtrl\t\t\t\t\t\t0\t/* Useless now */\n#define\t\trRTL8256_TxLPF\t\t\t\t\t19\n#define\t\trRTL8256_RxLPF\t\t\t\t\t11\n\n/* RTL8258 */\n#define\t\trRTL8258_TxLPF\t\t\t\t\t0x11\t/* Useless now */\n#define\t\trRTL8258_RxLPF\t\t\t\t\t0x13\n#define\t\trRTL8258_RSSILPF\t\t\t\t0xa\n\n/*\n * RL6052 Register definition\n *   */\n#define\t\tRF_AC\t\t\t\t\t\t0x00\t/* */\n\n#define\t\tRF_IQADJ_G1\t\t\t\t0x01\t/* */\n#define\t\tRF_IQADJ_G2\t\t\t\t0x02\t/* */\n#define\t\tRF_BS_PA_APSET_G1_G4\t\t0x03\n#define\t\tRF_BS_PA_APSET_G5_G8\t\t0x04\n#define\t\tRF_POW_TRSW\t\t\t\t0x05\t/* */\n\n#define\t\tRF_GAIN_RX\t\t\t\t\t0x06\t/* */\n#define\t\tRF_GAIN_TX\t\t\t\t\t0x07\t/* */\n\n#define\t\tRF_TXM_IDAC\t\t\t\t0x08\t/* */\n#define\t\tRF_IPA_G\t\t\t\t\t0x09\t/* */\n#define\t\tRF_TXBIAS_G\t\t\t\t0x0A\n#define\t\tRF_TXPA_AG\t\t\t\t\t0x0B\n#define\t\tRF_IPA_A\t\t\t\t\t0x0C\t/* */\n#define\t\tRF_TXBIAS_A\t\t\t\t0x0D\n#define\t\tRF_BS_PA_APSET_G9_G11\t0x0E\n#define\t\tRF_BS_IQGEN\t\t\t\t0x0F\t/* */\n\n#define\t\tRF_MODE1\t\t\t\t\t0x10\t/* */\n#define\t\tRF_MODE2\t\t\t\t\t0x11\t/* */\n\n#define\t\tRF_RX_AGC_HP\t\t\t\t0x12\t/* */\n#define\t\tRF_TX_AGC\t\t\t\t\t0x13\t/* */\n#define\t\tRF_BIAS\t\t\t\t\t\t0x14\t/* */\n#define\t\tRF_IPA\t\t\t\t\t\t0x15\t/* */\n#define\t\tRF_TXBIAS\t\t\t\t\t0x16\n#define\t\tRF_POW_ABILITY\t\t\t0x17\t/* */\n#define\t\tRF_MODE_AG\t\t\t\t0x18\t/* */\n#define\t\trRfChannel\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define\t\tRF_CHNLBW\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define\t\tRF_TOP\t\t\t\t\t\t0x19\t/* */\n\n#define\t\tRF_RX_G1\t\t\t\t\t0x1A\t/* */\n#define\t\tRF_RX_G2\t\t\t\t\t0x1B\t/* */\n\n#define\t\tRF_RX_BB2\t\t\t\t\t0x1C\t/* */\n#define\t\tRF_RX_BB1\t\t\t\t\t0x1D\t/* */\n\n#define\t\tRF_RCK1\t\t\t\t\t0x1E\t/* */\n#define\t\tRF_RCK2\t\t\t\t\t0x1F\t/* */\n\n#define\t\tRF_TX_G1\t\t\t\t\t0x20\t/* */\n#define\t\tRF_TX_G2\t\t\t\t\t0x21\t/* */\n#define\t\tRF_TX_G3\t\t\t\t\t0x22\t/* */\n\n#define\t\tRF_TX_BB1\t\t\t\t\t0x23\t/* */\n\n#define\t\tRF_T_METER\t\t\t\t\t0x24\t/* */\n\n#define\t\tRF_SYN_G1\t\t\t\t\t0x25\t/* RF TX Power control */\n#define\t\tRF_SYN_G2\t\t\t\t\t0x26\t/* RF TX Power control */\n#define\t\tRF_SYN_G3\t\t\t\t\t0x27\t/* RF TX Power control */\n#define\t\tRF_SYN_G4\t\t\t\t\t0x28\t/* RF TX Power control */\n#define\t\tRF_SYN_G5\t\t\t\t\t0x29\t/* RF TX Power control */\n#define\t\tRF_SYN_G6\t\t\t\t\t0x2A\t/* RF TX Power control */\n#define\t\tRF_SYN_G7\t\t\t\t\t0x2B\t/* RF TX Power control */\n#define\t\tRF_SYN_G8\t\t\t\t\t0x2C\t/* RF TX Power control */\n\n#define\t\tRF_RCK_OS\t\t\t\t\t0x30\t/* RF TX PA control */\n\n#define\t\tRF_TXPA_G1\t\t\t\t\t0x31\t/* RF TX PA control */\n#define\t\tRF_TXPA_G2\t\t\t\t\t0x32\t/* RF TX PA control */\n#define\t\tRF_TXPA_G3\t\t\t\t\t0x33\t/* RF TX PA control */\n#define\tRF_TX_BIAS_A\t\t\t\t0x35\n#define\tRF_TX_BIAS_D\t\t\t\t0x36\n#define\tRF_LOBF_9\t\t\t\t\t0x38\n#define\tRF_RXRF_A3\t\t\t\t\t0x3C\t/*\t */\n#define\tRF_TRSW\t\t\t\t\t0x3F\n\n#define\tRF_TXRF_A2\t\t\t\t\t0x41\n#define\tRF_T_METER_88E\t\t\t\t0x42\n#define\tRF_TXPA_G4\t\t\t\t\t0x46\n#define\tRF_TXPA_A4\t\t\t\t\t0x4B\n#define\tRF_0x52\t\t\t\t\t0x52\n#define\tRF_WE_LUT\t\t\t\t\t0xEF\n#define\tRF_S0S1\t\t\t\t\t0xB0\n\n/*\n * Bit Mask\n *\n * 1. Page1(0x100) */\n#define\t\tbBBResetB\t\t\t\t\t\t0x100\t/* Useless now? */\n#define\t\tbGlobalResetB\t\t\t\t\t0x200\n#define\t\tbOFDMTxStart\t\t\t\t\t0x4\n#define\t\tbCCKTxStart\t\t\t\t\t\t0x8\n#define\t\tbCRC32Debug\t\t\t\t\t0x100\n#define\t\tbPMACLoopback\t\t\t\t\t0x10\n#define\t\tbTxLSIG\t\t\t\t\t\t\t0xffffff\n#define\t\tbOFDMTxRate\t\t\t\t\t0xf\n#define\t\tbOFDMTxReserved\t\t\t\t0x10\n#define\t\tbOFDMTxLength\t\t\t\t\t0x1ffe0\n#define\t\tbOFDMTxParity\t\t\t\t\t0x20000\n#define\t\tbTxHTSIG1\t\t\t\t\t\t0xffffff\n#define\t\tbTxHTMCSRate\t\t\t\t\t0x7f\n#define\t\tbTxHTBW\t\t\t\t\t\t0x80\n#define\t\tbTxHTLength\t\t\t\t\t0xffff00\n#define\t\tbTxHTSIG2\t\t\t\t\t\t0xffffff\n#define\t\tbTxHTSmoothing\t\t\t\t\t0x1\n#define\t\tbTxHTSounding\t\t\t\t\t0x2\n#define\t\tbTxHTReserved\t\t\t\t\t0x4\n#define\t\tbTxHTAggreation\t\t\t\t0x8\n#define\t\tbTxHTSTBC\t\t\t\t\t\t0x30\n#define\t\tbTxHTAdvanceCoding\t\t\t0x40\n#define\t\tbTxHTShortGI\t\t\t\t\t0x80\n#define\t\tbTxHTNumberHT_LTF\t\t\t0x300\n#define\t\tbTxHTCRC8\t\t\t\t\t\t0x3fc00\n#define\t\tbCounterReset\t\t\t\t\t0x10000\n#define\t\tbNumOfOFDMTx\t\t\t\t\t0xffff\n#define\t\tbNumOfCCKTx\t\t\t\t\t0xffff0000\n#define\t\tbTxIdleInterval\t\t\t\t\t0xffff\n#define\t\tbOFDMService\t\t\t\t\t0xffff0000\n#define\t\tbTxMACHeader\t\t\t\t\t0xffffffff\n#define\t\tbTxDataInit\t\t\t\t\t\t0xff\n#define\t\tbTxHTMode\t\t\t\t\t\t0x100\n#define\t\tbTxDataType\t\t\t\t\t0x30000\n#define\t\tbTxRandomSeed\t\t\t\t\t0xffffffff\n#define\t\tbCCKTxPreamble\t\t\t\t\t0x1\n#define\t\tbCCKTxSFD\t\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxSIG\t\t\t\t\t\t0xff\n#define\t\tbCCKTxService\t\t\t\t\t0xff00\n#define\t\tbCCKLengthExt\t\t\t\t\t0x8000\n#define\t\tbCCKTxLength\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxCRC16\t\t\t\t\t0xffff\n#define\t\tbCCKTxStatus\t\t\t\t\t0x1\n#define\t\tbOFDMTxStatus\t\t\t\t\t0x2\n\n#define\t\tIS_BB_REG_OFFSET_92S(_Offset)\t\t((_Offset >= 0x800) && (_Offset <= 0xfff))\n#define\t\tRF_TX_GAIN_OFFSET_8192F(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0))\n\n/* 2. Page8(0x800) */\n#define\t\tbRFMOD\t\t\t\t\t\t\t0x1\t/* Reg 0x800 rFPGA0_RFMOD */\n#define\t\tbJapanMode\t\t\t\t\t\t0x2\n#define\t\tbCCKTxSC\t\t\t\t\t\t0x30\n#define\t\tbCCKEn\t\t\t\t\t\t\t0x1000000\n#define\t\tbOFDMEn\t\t\t\t\t\t0x2000000\n\n#define\t\tbOFDMRxADCPhase           0x10000\t/* Useless now */\n#define\t\tbOFDMTxDACPhase\t\t0x40000\n#define\t\tbXATxAGC\t\t\t0x3f\n\n#define\t\tbAntennaSelect\t\t0x0300\n\n#define\t\tbXBTxAGC                 0xf00\t/* Reg 80c rFPGA0_TxGainStage */\n#define\t\tbXCTxAGC\t\t\t0xf000\n#define\t\tbXDTxAGC\t\t\t0xf0000\n\n#define\t\tbPAStart                 0xf0000000\t/* Useless now */\n#define\t\tbTRStart\t\t\t0x00f00000\n#define\t\tbRFStart\t\t\t0x0000f000\n#define\t\tbBBStart\t\t\t0x000000f0\n#define\t\tbBBCCKStart\t\t0x0000000f\n#define\t\tbPAEnd                    0xf          /* Reg0x814 */\n#define\t\tbTREnd\t\t\t0x0f000000\n#define\t\tbRFEnd\t\t\t0x000f0000\n#define\t\tbCCAMask                  0x000000f0   /* T2R */\n#define\t\tbR2RCCAMask\t\t0x00000f00\n#define\t\tbHSSI_R2TDelay\t\t0xf8000000\n#define\t\tbHSSI_T2RDelay\t\t0xf80000\n#define\t\tbContTxHSSI              0x400     /* chane gain at continue Tx */\n#define\t\tbIGFromCCK\t\t0x200\n#define\t\tbAGCAddress\t\t0x3f\n#define\t\tbRxHPTx\t\t\t0x7000\n#define\t\tbRxHPT2R\t\t\t0x38000\n#define\t\tbRxHPCCKIni\t\t0xc0000\n#define\t\tbAGCTxCode\t\t0xc00000\n#define\t\tbAGCRxCode\t\t0x300000\n\n#define\t\tb3WireDataLength         0x800\t/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */\n#define\t\tb3WireAddressLength\t\t0x400\n\n#define\t\tb3WireRFPowerDown         0x1\t/* Useless now\n * #define bHWSISelect\t\t0x8 */\n#define\t\tb5GPAPEPolarity\t\t0x40000000\n#define\t\tb2GPAPEPolarity\t\t0x80000000\n#define\t\tbRFSW_TxDefaultAnt\t\t0x3\n#define\t\tbRFSW_TxOptionAnt\t\t0x30\n#define\t\tbRFSW_RxDefaultAnt\t\t0x300\n#define\t\tbRFSW_RxOptionAnt\t\t0x3000\n#define\t\tbRFSI_3WireData\t\t0x1\n#define\t\tbRFSI_3WireClock\t\t0x2\n#define\t\tbRFSI_3WireLoad\t\t0x4\n#define\t\tbRFSI_3WireRW\t\t0x8\n#define\t\tbRFSI_3Wire\t\t\t0xf\n\n#define\t\tbRFSI_RFENV              0x10\t/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */\n\n#define\t\tbRFSI_TRSW               0x20\t/* Useless now */\n#define\t\tbRFSI_TRSWB\t\t0x40\n#define\t\tbRFSI_ANTSW\t\t0x100\n#define\t\tbRFSI_ANTSWB\t\t0x200\n#define\t\tbRFSI_PAPE\t\t\t0x400\n#define\t\tbRFSI_PAPE5G\t\t0x800\n#define\t\tbBandSelect\t\t\t0x1\n#define\t\tbHTSIG2_GI\t\t\t0x80\n#define\t\tbHTSIG2_Smoothing\t\t0x01\n#define\t\tbHTSIG2_Sounding\t\t0x02\n#define\t\tbHTSIG2_Aggreaton\t\t0x08\n#define\t\tbHTSIG2_STBC\t\t0x30\n#define\t\tbHTSIG2_AdvCoding\t\t0x40\n#define\t\tbHTSIG2_NumOfHTLTF\t0x300\n#define\t\tbHTSIG2_CRC8\t\t0x3fc\n#define\t\tbHTSIG1_MCS\t\t0x7f\n#define\t\tbHTSIG1_BandWidth\t\t0x80\n#define\t\tbHTSIG1_HTLength\t\t0xffff\n#define\t\tbLSIG_Rate\t\t\t0xf\n#define\t\tbLSIG_Reserved\t\t0x10\n#define\t\tbLSIG_Length\t\t0x1fffe\n#define\t\tbLSIG_Parity\t\t\t0x20\n#define\t\tbCCKRxPhase\t\t0x4\n\n#define\t\tbLSSIReadAddress          0x7f800000   /* T65 RF */\n\n#define\t\tbLSSIReadEdge             0x80000000   /* LSSI \"Read\" edge signal */\n\n#define\t\tbLSSIReadBackData         0xfffff\t\t/* T65 RF */\n\n#define\t\tbLSSIReadOKFlag           0x1000\t/* Useless now */\n#define\t\tbCCKSampleRate            0x8       /* 0: 44MHz, 1:88MHz     */\n#define\t\tbRegulator0Standby\t\t0x1\n#define\t\tbRegulatorPLLStandby\t\t0x2\n#define\t\tbRegulator1Standby\t\t0x4\n#define\t\tbPLLPowerUp\t\t0x8\n#define\t\tbDPLLPowerUp\t\t0x10\n#define\t\tbDA10PowerUp\t\t0x20\n#define\t\tbAD7PowerUp\t\t0x200\n#define\t\tbDA6PowerUp\t\t0x2000\n#define\t\tbXtalPowerUp\t\t0x4000\n#define\t\tb40MDClkPowerUP\t\t0x8000\n#define\t\tbDA6DebugMode\t\t0x20000\n#define\t\tbDA6Swing\t\t\t0x380000\n\n#define\t\tbADClkPhase               0x4000000\t/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */\n\n#define\t\tb80MClkDelay              0x18000000\t/* Useless */\n#define\t\tbAFEWatchDogEnable\t\t0x20000000\n\n#define\t\tbXtalCap01                0xc0000000\t/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */\n#define\t\tbXtalCap23\t\t\t0x3\n#define\t\tbXtalCap92x\t\t\t\t\t0x0f000000\n#define\t\tbXtalCap\t\t\t0x0f000000\n\n#define\t\tbIntDifClkEnable          0x400\t/* Useless */\n#define\t\tbExtSigClkEnable\t\t0x800\n#define\t\tbBandgapMbiasPowerUp\t0x10000\n#define\t\tbAD11SHGain\t\t0xc0000\n#define\t\tbAD11InputRange\t\t0x700000\n#define\t\tbAD11OPCurrent\t\t0x3800000\n#define\t\tbIPathLoopback\t\t0x4000000\n#define\t\tbQPathLoopback\t\t0x8000000\n#define\t\tbAFELoopback\t\t0x10000000\n#define\t\tbDA10Swing\t\t0x7e0\n#define\t\tbDA10Reverse\t\t0x800\n#define\t\tbDAClkSource\t\t0x1000\n#define\t\tbAD7InputRange\t\t0x6000\n#define\t\tbAD7Gain\t\t\t0x38000\n#define\t\tbAD7OutputCMMode\t\t0x40000\n#define\t\tbAD7InputCMMode\t\t0x380000\n#define\t\tbAD7Current\t\t\t0xc00000\n#define\t\tbRegulatorAdjust\t\t0x7000000\n#define\t\tbAD11PowerUpAtTx\t\t0x1\n#define\t\tbDA10PSAtTx\t\t0x10\n#define\t\tbAD11PowerUpAtRx\t\t0x100\n#define\t\tbDA10PSAtRx\t\t0x1000\n#define\t\tbCCKRxAGCFormat\t\t0x200\n#define\t\tbPSDFFTSamplepPoint\t\t0xc000\n#define\t\tbPSDAverageNum\t\t0x3000\n#define\t\tbIQPathControl\t\t0xc00\n#define\t\tbPSDFreq\t\t\t0x3ff\n#define\t\tbPSDAntennaPath\t\t0x30\n#define\t\tbPSDIQSwitch\t\t0x40\n#define\t\tbPSDRxTrigger\t\t0x400000\n#define\t\tbPSDTxTrigger\t\t0x80000000\n#define\t\tbPSDSineToneScale\t\t0x7f000000\n#define\t\tbPSDReport\t\t\t0xffff\n\n/* 3. Page9(0x900) */\n#define\t\tbOFDMTxSC                 0x30000000\t/* Useless */\n#define\t\tbCCKTxOn\t\t\t0x1\n#define\t\tbOFDMTxOn\t\t0x2\n#define\t\tbDebugPage                0xfff  /* reset debug page and also HWord, LWord */\n#define\t\tbDebugItem                0xff   /* reset debug page and LWord */\n#define\t\tbAntL\t\t\t0x10\n#define\t\tbAntNonHT\t\t\t\t0x100\n#define\t\tbAntHT1\t\t\t0x1000\n#define\t\tbAntHT2\t\t\t0x10000\n#define\t\tbAntHT1S1\t\t\t0x100000\n#define\t\tbAntNonHTS1\t\t0x1000000\n\n/* 4. PageA(0xA00) */\n#define\t\tbCCKBBMode\t\t\t\t0x3\t/* Useless */\n#define\t\tbCCKTxPowerSaving\t\t0x80\n#define\t\tbCCKRxPowerSaving\t\t0x40\n\n#define\t\tbCCKSideBand\t\t\t0x10\t/* Reg 0xa00 rCCK0_System 20/40 switch */\n\n#define\t\tbCCKScramble\t\t\t0x8\t/* Useless */\n#define\t\tbCCKAntDiversity\t\t0x8000\n#define\t\tbCCKCarrierRecovery\t\t0x4000\n#define\t\tbCCKTxRate\t\t\t\t0x3000\n#define\t\tbCCKDCCancel\t\t\t0x0800\n#define\t\tbCCKISICancel\t\t\t0x0400\n#define\t\tbCCKMatchFilter\t\t\t0x0200\n#define\t\tbCCKEqualizer\t\t\t0x0100\n#define\t\tbCCKPreambleDetect\t\t0x800000\n#define\t\tbCCKFastFalseCCA\t\t0x400000\n#define\t\tbCCKChEstStart\t\t\t0x300000\n#define\t\tbCCKCCACount\t\t\t0x080000\n#define\t\tbCCKcs_lim\t\t\t\t0x070000\n#define\t\tbCCKBistMode\t\t\t0x80000000\n#define\t\tbCCKCCAMask\t\t\t0x40000000\n#define\t\tbCCKTxDACPhase\t\t0x4\n#define\t\tbCCKRxADCPhase\t\t0x20000000   /* r_rx_clk */\n#define\t\tbCCKr_cp_mode0\t\t0x0100\n#define\t\tbCCKTxDCOffset\t\t\t0xf0\n#define\t\tbCCKRxDCOffset\t\t\t0xf\n#define\t\tbCCKCCAMode\t\t\t0xc000\n#define\t\tbCCKFalseCS_lim\t\t\t0x3f00\n#define\t\tbCCKCS_ratio\t\t\t0xc00000\n#define\t\tbCCKCorgBit_sel\t\t\t0x300000\n#define\t\tbCCKPD_lim\t\t\t\t0x0f0000\n#define\t\tbCCKNewCCA\t\t\t0x80000000\n#define\t\tbCCKRxHPofIG\t\t\t0x8000\n#define\t\tbCCKRxIG\t\t\t\t0x7f00\n#define\t\tbCCKLNAPolarity\t\t\t0x800000\n#define\t\tbCCKRx1stGain\t\t\t0x7f0000\n#define\t\tbCCKRFExtend\t\t\t0x20000000 /* CCK Rx Iinital gain polarity */\n#define\t\tbCCKRxAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKRxAGCSatCount\t\t0xe0\n#define\t\tbCCKRxRFSettle\t\t\t0x1f       /* AGCsamp_dly */\n#define\t\tbCCKFixedRxAGC\t\t\t0x8000\n/* #define bCCKRxAGCFormat\t\t0x4000 */   /* remove to HSSI register 0x824 */\n#define\t\tbCCKAntennaPolarity\t\t0x2000\n#define\t\tbCCKTxFilterType\t\t0x0c00\n#define\t\tbCCKRxAGCReportType\t0x0300\n#define\t\tbCCKRxDAGCEn\t\t\t0x80000000\n#define\t\tbCCKRxDAGCPeriod\t\t0x20000000\n#define\t\tbCCKRxDAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKTimingRecovery\t\t0x800000\n#define\t\tbCCKTxC0\t\t\t\t0x3f0000\n#define\t\tbCCKTxC1\t\t\t\t0x3f000000\n#define\t\tbCCKTxC2\t\t\t\t0x3f\n#define\t\tbCCKTxC3\t\t\t\t0x3f00\n#define\t\tbCCKTxC4\t\t\t\t0x3f0000\n#define\t\tbCCKTxC5\t\t\t\t0x3f000000\n#define\t\tbCCKTxC6\t\t\t\t0x3f\n#define\t\tbCCKTxC7\t\t\t\t0x3f00\n#define\t\tbCCKDebugPort\t\t\t0xff0000\n#define\t\tbCCKDACDebug\t\t\t0x0f000000\n#define\t\tbCCKFalseAlarmEnable\t0x8000\n#define\t\tbCCKFalseAlarmRead\t\t0x4000\n#define\t\tbCCKTRSSI\t\t\t\t0x7f\n#define\t\tbCCKRxAGCReport\t\t0xfe\n#define\t\tbCCKRxReport_AntSel\t0x80000000\n#define\t\tbCCKRxReport_MFOff\t\t0x40000000\n#define\t\tbCCKRxRxReport_SQLoss\t0x20000000\n#define\t\tbCCKRxReport_Pktloss\t0x10000000\n#define\t\tbCCKRxReport_Lockedbit\t0x08000000\n#define\t\tbCCKRxReport_RateError\t0x04000000\n#define\t\tbCCKRxReport_RxRate\t0x03000000\n#define\t\tbCCKRxFACounterLower\t0xff\n#define\t\tbCCKRxFACounterUpper\t0xff000000\n#define\t\tbCCKRxHPAGCStart\t\t0xe000\n#define\t\tbCCKRxHPAGCFinal\t\t0x1c00\n#define\t\tbCCKRxFalseAlarmEnable\t0x8000\n#define\t\tbCCKFACounterFreeze\t0x4000\n#define\t\tbCCKTxPathSel\t\t\t0x10000000\n#define\t\tbCCKDefaultRxPath\t\t0xc000000\n#define\t\tbCCKOptionRxPath\t\t0x3000000\n\n/* 5. PageC(0xC00) */\n#define\t\tbNumOfSTF\t\t\t\t0x3\t/* Useless */\n#define\t\tbShift_L\t\t\t\t\t0xc0\n#define\t\tbGI_TH\t\t\t\t\t0xc\n#define\t\tbRxPathA\t\t\t\t0x1\n#define\t\tbRxPathB\t\t\t\t0x2\n#define\t\tbRxPathC\t\t\t\t0x4\n#define\t\tbRxPathD\t\t\t\t0x8\n#define\t\tbTxPathA\t\t\t\t0x1\n#define\t\tbTxPathB\t\t\t\t0x2\n#define\t\tbTxPathC\t\t\t\t0x4\n#define\t\tbTxPathD\t\t\t\t0x8\n#define\t\tbTRSSIFreq\t\t\t\t0x200\n#define\t\tbADCBackoff\t\t\t\t0x3000\n#define\t\tbDFIRBackoff\t\t\t0xc000\n#define\t\tbTRSSILatchPhase\t\t0x10000\n#define\t\tbRxIDCOffset\t\t\t0xff\n#define\t\tbRxQDCOffset\t\t\t0xff00\n#define\t\tbRxDFIRMode\t\t\t0x1800000\n#define\t\tbRxDCNFType\t\t\t0xe000000\n#define\t\tbRXIQImb_A\t\t\t\t0x3ff\n#define\t\tbRXIQImb_B\t\t\t\t0xfc00\n#define\t\tbRXIQImb_C\t\t\t\t0x3f0000\n#define\t\tbRXIQImb_D\t\t\t\t0xffc00000\n#define\t\tbDC_dc_Notch\t\t\t0x60000\n#define\t\tbRxNBINotch\t\t\t0x1f000000\n#define\t\tbPD_TH\t\t\t\t\t0xf\n#define\t\tbPD_TH_Opt2\t\t\t0xc000\n#define\t\tbPWED_TH\t\t\t\t0x700\n#define\t\tbIfMF_Win_L\t\t\t0x800\n#define\t\tbPD_Option\t\t\t\t0x1000\n#define\t\tbMF_Win_L\t\t\t\t0xe000\n#define\t\tbBW_Search_L\t\t\t0x30000\n#define\t\tbwin_enh_L\t\t\t\t0xc0000\n#define\t\tbBW_TH\t\t\t\t\t0x700000\n#define\t\tbED_TH2\t\t\t\t0x3800000\n#define\t\tbBW_option\t\t\t\t0x4000000\n#define\t\tbRatio_TH\t\t\t\t0x18000000\n#define\t\tbWindow_L\t\t\t\t0xe0000000\n#define\t\tbSBD_Option\t\t\t\t0x1\n#define\t\tbFrame_TH\t\t\t\t0x1c\n#define\t\tbFS_Option\t\t\t\t0x60\n#define\t\tbDC_Slope_check\t\t0x80\n#define\t\tbFGuard_Counter_DC_L\t0xe00\n#define\t\tbFrame_Weight_Short\t0x7000\n#define\t\tbSub_Tune\t\t\t\t0xe00000\n#define\t\tbFrame_DC_Length\t\t0xe000000\n#define\t\tbSBD_start_offset\t\t0x30000000\n#define\t\tbFrame_TH_2\t\t\t0x7\n#define\t\tbFrame_GI2_TH\t\t\t0x38\n#define\t\tbGI2_Sync_en\t\t\t0x40\n#define\t\tbSarch_Short_Early\t\t0x300\n#define\t\tbSarch_Short_Late\t\t0xc00\n#define\t\tbSarch_GI2_Late\t\t0x70000\n#define\t\tbCFOAntSum\t\t\t\t0x1\n#define\t\tbCFOAcc\t\t\t\t0x2\n#define\t\tbCFOStartOffset\t\t\t0xc\n#define\t\tbCFOLookBack\t\t\t0x70\n#define\t\tbCFOSumWeight\t\t\t0x80\n#define\t\tbDAGCEnable\t\t\t0x10000\n#define\t\tbTXIQImb_A\t\t\t\t0x3ff\n#define\t\tbTXIQImb_B\t\t\t\t0xfc00\n#define\t\tbTXIQImb_C\t\t\t\t0x3f0000\n#define\t\tbTXIQImb_D\t\t\t\t0xffc00000\n#define\t\tbTxIDCOffset\t\t\t0xff\n#define\t\tbTxQDCOffset\t\t\t0xff00\n#define\t\tbTxDFIRMode\t\t\t0x10000\n#define\t\tbTxPesudoNoiseOn\t\t0x4000000\n#define\t\tbTxPesudoNoise_A\t\t0xff\n#define\t\tbTxPesudoNoise_B\t\t0xff00\n#define\t\tbTxPesudoNoise_C\t\t0xff0000\n#define\t\tbTxPesudoNoise_D\t\t0xff000000\n#define\t\tbCCADropOption\t\t\t0x20000\n#define\t\tbCCADropThres\t\t\t0xfff00000\n#define\t\tbEDCCA_H\t\t\t\t0xf\n#define\t\tbEDCCA_L\t\t\t\t0xf0\n#define\t\tbLambda_ED\t\t\t0x300\n#define\t\tbRxInitialGain\t\t\t0x7f\n#define\t\tbRxAntDivEn\t\t\t\t0x80\n#define\t\tbRxAGCAddressForLNA\t0x7f00\n#define\t\tbRxHighPowerFlow\t\t0x8000\n#define\t\tbRxAGCFreezeThres\t\t0xc0000\n#define\t\tbRxFreezeStep_AGC1\t0x300000\n#define\t\tbRxFreezeStep_AGC2\t0xc00000\n#define\t\tbRxFreezeStep_AGC3\t0x3000000\n#define\t\tbRxFreezeStep_AGC0\t0xc000000\n#define\t\tbRxRssi_Cmp_En\t\t\t0x10000000\n#define\t\tbRxQuickAGCEn\t\t\t0x20000000\n#define\t\tbRxAGCFreezeThresMode\t0x40000000\n#define\t\tbRxOverFlowCheckType\t0x80000000\n#define\t\tbRxAGCShift\t\t\t\t0x7f\n#define\t\tbTRSW_Tri_Only\t\t\t0x80\n#define\t\tbPowerThres\t\t\t0x300\n#define\t\tbRxAGCEn\t\t\t\t0x1\n#define\t\tbRxAGCTogetherEn\t\t0x2\n#define\t\tbRxAGCMin\t\t\t\t0x4\n#define\t\tbRxHP_Ini\t\t\t\t0x7\n#define\t\tbRxHP_TRLNA\t\t\t0x70\n#define\t\tbRxHP_RSSI\t\t\t\t0x700\n#define\t\tbRxHP_BBP1\t\t\t\t0x7000\n#define\t\tbRxHP_BBP2\t\t\t\t0x70000\n#define\t\tbRxHP_BBP3\t\t\t\t0x700000\n#define\t\tbRSSI_H\t\t\t\t\t0x7f0000     /* the threshold for high power */\n#define\t\tbRSSI_Gen\t\t\t\t0x7f000000   /* the threshold for ant diversity */\n#define\t\tbRxSettle_TRSW\t\t\t0x7\n#define\t\tbRxSettle_LNA\t\t\t0x38\n#define\t\tbRxSettle_RSSI\t\t\t0x1c0\n#define\t\tbRxSettle_BBP\t\t\t0xe00\n#define\t\tbRxSettle_RxHP\t\t\t0x7000\n#define\t\tbRxSettle_AntSW_RSSI\t0x38000\n#define\t\tbRxSettle_AntSW\t\t0xc0000\n#define\t\tbRxProcessTime_DAGC\t0x300000\n#define\t\tbRxSettle_HSSI\t\t\t0x400000\n#define\t\tbRxProcessTime_BBPPW\t0x800000\n#define\t\tbRxAntennaPowerShift\t0x3000000\n#define\t\tbRSSITableSelect\t\t0xc000000\n#define\t\tbRxHP_Final\t\t\t\t0x7000000\n#define\t\tbRxHTSettle_BBP\t\t\t0x7\n#define\t\tbRxHTSettle_HSSI\t\t0x8\n#define\t\tbRxHTSettle_RxHP\t\t0x70\n#define\t\tbRxHTSettle_BBPPW\t\t0x80\n#define\t\tbRxHTSettle_Idle\t\t0x300\n#define\t\tbRxHTSettle_Reserved\t0x1c00\n#define\t\tbRxHTRxHPEn\t\t\t0x8000\n#define\t\tbRxHTAGCFreezeThres\t0x30000\n#define\t\tbRxHTAGCTogetherEn\t0x40000\n#define\t\tbRxHTAGCMin\t\t\t0x80000\n#define\t\tbRxHTAGCEn\t\t\t\t0x100000\n#define\t\tbRxHTDAGCEn\t\t\t0x200000\n#define\t\tbRxHTRxHP_BBP\t\t\t0x1c00000\n#define\t\tbRxHTRxHP_Final\t\t0xe0000000\n#define\t\tbRxPWRatioTH\t\t\t0x3\n#define\t\tbRxPWRatioEn\t\t\t0x4\n#define\t\tbRxMFHold\t\t\t\t0x3800\n#define\t\tbRxPD_Delay_TH1\t\t0x38\n#define\t\tbRxPD_Delay_TH2\t\t0x1c0\n#define\t\tbRxPD_DC_COUNT_MAX\t0x600\n/* #define bRxMF_Hold               0x3800 */\n#define\t\tbRxPD_Delay_TH\t\t\t0x8000\n#define\t\tbRxProcess_Delay\t\t0xf0000\n#define\t\tbRxSearchrange_GI2_Early\t0x700000\n#define\t\tbRxFrame_Guard_Counter_L\t0x3800000\n#define\t\tbRxSGI_Guard_L\t\t\t0xc000000\n#define\t\tbRxSGI_Search_L\t\t0x30000000\n#define\t\tbRxSGI_TH\t\t\t\t0xc0000000\n#define\t\tbDFSCnt0\t\t\t\t0xff\n#define\t\tbDFSCnt1\t\t\t\t0xff00\n#define\t\tbDFSFlag\t\t\t\t0xf0000\n#define\t\tbMFWeightSum\t\t\t0x300000\n#define\t\tbMinIdxTH\t\t\t\t0x7f000000\n#define\t\tbDAFormat\t\t\t\t0x40000\n#define\t\tbTxChEmuEnable\t\t0x01000000\n#define\t\tbTRSWIsolation_A\t\t0x7f\n#define\t\tbTRSWIsolation_B\t\t0x7f00\n#define\t\tbTRSWIsolation_C\t\t0x7f0000\n#define\t\tbTRSWIsolation_D\t\t0x7f000000\n#define\t\tbExtLNAGain\t\t\t\t0x7c00\n\n/* 6. PageE(0xE00) */\n#define\t\tbSTBCEn\t\t\t\t0x4\t/* Useless */\n#define\t\tbAntennaMapping\t\t0x10\n#define\t\tbNss\t\t\t\t\t0x20\n#define\t\tbCFOAntSumD\t\t\t0x200\n#define\t\tbPHYCounterReset\t\t0x8000000\n#define\t\tbCFOReportGet\t\t\t0x4000000\n#define\t\tbOFDMContinueTx\t\t0x10000000\n#define\t\tbOFDMSingleCarrier\t\t0x20000000\n#define\t\tbOFDMSingleTone\t\t0x40000000\n/* #define bRxPath1                 0x01 */\n/* #define bRxPath2                 0x02 */\n/* #define bRxPath3                 0x04 */\n/* #define bRxPath4                 0x08 */\n/* #define bTxPath1                 0x10 */\n/* #define bTxPath2                 0x20 */\n#define\t\tbHTDetect\t\t\t0x100\n#define\t\tbCFOEn\t\t\t\t0x10000\n#define\t\tbCFOValue\t\t\t0xfff00000\n#define\t\tbSigTone_Re\t\t0x3f\n#define\t\tbSigTone_Im\t\t0x7f00\n#define\t\tbCounter_CCA\t\t0xffff\n#define\t\tbCounter_ParityFail\t0xffff0000\n#define\t\tbCounter_RateIllegal\t\t0xffff\n#define\t\tbCounter_CRC8Fail\t0xffff0000\n#define\t\tbCounter_MCSNoSupport\t0xffff\n#define\t\tbCounter_FastSync\t0xffff\n#define\t\tbShortCFO\t\t\t0xfff\n#define\t\tbShortCFOTLength\t12   /* total */\n#define\t\tbShortCFOFLength\t11   /* fraction */\n#define\t\tbLongCFO\t\t\t0x7ff\n#define\t\tbLongCFOTLength\t11\n#define\t\tbLongCFOFLength\t11\n#define\t\tbTailCFO\t\t\t0x1fff\n#define\t\tbTailCFOTLength\t\t13\n#define\t\tbTailCFOFLength\t\t12\n#define\t\tbmax_en_pwdB\t\t0xffff\n#define\t\tbCC_power_dB\t\t0xffff0000\n#define\t\tbnoise_pwdB\t\t0xffff\n#define\t\tbPowerMeasTLength\t10\n#define\t\tbPowerMeasFLength\t3\n#define\t\tbRx_HT_BW\t\t\t0x1\n#define\t\tbRxSC\t\t\t\t0x6\n#define\t\tbRx_HT\t\t\t\t0x8\n#define\t\tbNB_intf_det_on\t\t0x1\n#define\t\tbIntf_win_len_cfg\t0x30\n#define\t\tbNB_Intf_TH_cfg\t\t0x1c0\n#define\t\tbRFGain\t\t\t\t0x3f\n#define\t\tbTableSel\t\t\t0x40\n#define\t\tbTRSW\t\t\t\t0x80\n#define\t\tbRxSNR_A\t\t\t0xff\n#define\t\tbRxSNR_B\t\t\t0xff00\n#define\t\tbRxSNR_C\t\t\t0xff0000\n#define\t\tbRxSNR_D\t\t\t0xff000000\n#define\t\tbSNREVMTLength\t\t8\n#define\t\tbSNREVMFLength\t\t1\n#define\t\tbCSI1st\t\t\t\t0xff\n#define\t\tbCSI2nd\t\t\t\t0xff00\n#define\t\tbRxEVM1st\t\t\t0xff0000\n#define\t\tbRxEVM2nd\t\t\t0xff000000\n#define\t\tbSIGEVM\t\t\t0xff\n#define\t\tbPWDB\t\t\t\t0xff00\n#define\t\tbSGIEN\t\t\t\t0x10000\n\n#define\t\tbSFactorQAM1\t\t0xf\t/* Useless */\n#define\t\tbSFactorQAM2\t\t0xf0\n#define\t\tbSFactorQAM3\t\t0xf00\n#define\t\tbSFactorQAM4\t\t0xf000\n#define\t\tbSFactorQAM5\t\t0xf0000\n#define\t\tbSFactorQAM6\t\t0xf0000\n#define\t\tbSFactorQAM7\t\t0xf00000\n#define\t\tbSFactorQAM8\t\t0xf000000\n#define\t\tbSFactorQAM9\t\t0xf0000000\n#define\t\tbCSIScheme\t\t\t0x100000\n\n#define\t\tbNoiseLvlTopSet\t\t0x3\t/* Useless */\n#define\t\tbChSmooth\t\t\t0x4\n#define\t\tbChSmoothCfg1\t\t0x38\n#define\t\tbChSmoothCfg2\t\t0x1c0\n#define\t\tbChSmoothCfg3\t\t0xe00\n#define\t\tbChSmoothCfg4\t\t0x7000\n#define\t\tbMRCMode\t\t\t0x800000\n#define\t\tbTHEVMCfg\t\t\t0x7000000\n\n#define\t\tbLoopFitType\t\t0x1\t/* Useless */\n#define\t\tbUpdCFO\t\t\t0x40\n#define\t\tbUpdCFOOffData\t\t0x80\n#define\t\tbAdvUpdCFO\t\t\t0x100\n#define\t\tbAdvTimeCtrl\t\t0x800\n#define\t\tbUpdClko\t\t\t0x1000\n#define\t\tbFC\t\t\t\t\t0x6000\n#define\t\tbTrackingMode\t\t0x8000\n#define\t\tbPhCmpEnable\t\t0x10000\n#define\t\tbUpdClkoLTF\t\t0x20000\n#define\t\tbComChCFO\t\t\t0x40000\n#define\t\tbCSIEstiMode\t\t0x80000\n#define\t\tbAdvUpdEqz\t\t\t0x100000\n#define\t\tbUChCfg\t\t\t\t0x7000000\n#define\t\tbUpdEqz\t\t\t0x8000000\n\n/* Rx Pseduo noise */\n#define\t\tbRxPesudoNoiseOn\t\t0x20000000\t/* Useless */\n#define\t\tbRxPesudoNoise_A\t\t0xff\n#define\t\tbRxPesudoNoise_B\t\t0xff00\n#define\t\tbRxPesudoNoise_C\t\t0xff0000\n#define\t\tbRxPesudoNoise_D\t\t0xff000000\n#define\t\tbPesudoNoiseState_A\t0xffff\n#define\t\tbPesudoNoiseState_B\t0xffff0000\n#define\t\tbPesudoNoiseState_C\t0xffff\n#define\t\tbPesudoNoiseState_D\t0xffff0000\n\n/* 7. RF Register\n * Zebra1 */\n#define\t\tbZebra1_HSSIEnable\t\t0x8\t\t/* Useless */\n#define\t\tbZebra1_TRxControl\t\t0xc00\n#define\t\tbZebra1_TRxGainSetting\t0x07f\n#define\t\tbZebra1_RxCorner\t\t0xc00\n#define\t\tbZebra1_TxChargePump\t0x38\n#define\t\tbZebra1_RxChargePump\t0x7\n#define\t\tbZebra1_ChannelNum\t0xf80\n#define\t\tbZebra1_TxLPFBW\t\t0x400\n#define\t\tbZebra1_RxLPFBW\t\t0x600\n\n/* Zebra4 */\n#define\t\tbRTL8256RegModeCtrl1\t0x100\t/* Useless */\n#define\t\tbRTL8256RegModeCtrl0\t0x40\n#define\t\tbRTL8256_TxLPFBW\t\t0x18\n#define\t\tbRTL8256_RxLPFBW\t\t0x600\n\n/* RTL8258 */\n#define\t\tbRTL8258_TxLPFBW\t\t0xc\t/* Useless */\n#define\t\tbRTL8258_RxLPFBW\t\t0xc00\n#define\t\tbRTL8258_RSSILPFBW\t0xc0\n\n\n/*\n * Other Definition\n *   */\n\n/* byte endable for sb_write */\n#define\t\tbByte0\t\t\t\t0x1\t/* Useless */\n#define\t\tbByte1\t\t\t\t0x2\n#define\t\tbByte2\t\t\t\t0x4\n#define\t\tbByte3\t\t\t\t0x8\n#define\t\tbWord0\t\t\t\t0x3\n#define\t\tbWord1\t\t\t\t0xc\n#define\t\tbDWord\t\t\t\t0xf\n\n/* for PutRegsetting & GetRegSetting BitMask */\n#define\t\tbMaskByte0\t\t\t0xff\t/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */\n#define\t\tbMaskByte1\t\t\t0xff00\n#define\t\tbMaskByte2\t\t\t0xff0000\n#define\t\tbMaskByte3\t\t\t0xff000000\n#define\t\tbMaskHWord\t\t0xffff0000\n#define\t\tbMaskLWord\t\t\t0x0000ffff\n#define\t\tbMaskDWord\t\t0xffffffff\n#define\t\tbMaskH3Bytes\t\t0xffffff00\n#define\t\tbMask12Bits\t\t\t0xfff\n#define\t\tbMaskH4Bits\t\t\t0xf0000000\n#define\t\tbMaskOFDM_D\t\t0xffc00000\n#define\t\tbMaskCCK\t\t\t0x3f3f3f3f\n\n\n#define\t\tbEnable\t\t\t0x1\t/* Useless */\n#define\t\tbDisable\t\t0x0\n\n#define\t\tLeftAntenna\t\t0x0\t/* Useless */\n#define\t\tRightAntenna\t0x1\n\n#define\t\ttCheckTxStatus\t\t500   /* 500ms // Useless */\n#define\t\ttUpdateRxCounter\t100   /* 100ms */\n\n#define\t\trateCCK\t\t0\t/* Useless */\n#define\t\trateOFDM\t1\n#define\t\trateHT\t\t2\n\n/* define Register-End */\n#define\t\tbPMAC_End\t\t\t0x1ff\t/* Useless */\n#define\t\tbFPGAPHY0_End\t\t0x8ff\n#define\t\tbFPGAPHY1_End\t\t0x9ff\n#define\t\tbCCKPHY0_End\t\t0xaff\n#define\t\tbOFDMPHY0_End\t\t0xcff\n#define\t\tbOFDMPHY1_End\t\t0xdff\n\n/* define max debug item in each debug page\n * #define bMaxItem_FPGA_PHY0        0x9\n * #define bMaxItem_FPGA_PHY1        0x3\n * #define bMaxItem_PHY_11B          0x16\n * #define bMaxItem_OFDM_PHY0        0x29\n * #define bMaxItem_OFDM_PHY1        0x0 */\n\n#define\t\tbPMACControl\t\t0x0\t\t/* Useless */\n#define\t\tbWMACControl\t\t0x1\n#define\t\tbWNICControl\t\t0x2\n\n#define\t\tPathA\t\t\t0x0\t/* Useless */\n#define\t\tPathB\t\t\t0x1\n#define\t\tPathC\t\t\t0x2\n#define\t\tPathD\t\t\t0x3\n\n#endif\n"
  },
  {
    "path": "include/Hal8192FPwrSeq.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef REALTEK_POWER_SEQUENCE_8192F\n#define REALTEK_POWER_SEQUENCE_8192F\n#define POWER_SEQUENCE_8192F_VER 04\n/* #include \"PwrSeqCmd.h\" */\n#include \"HalPwrSeqCmd.h\"\n\n/*\n\tCheck document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd\n\tThere are 6 HW Power States:\n\t0: POFF--Power Off\n\t1: PDN--Power Down\n\t2: CARDEMU--Card Emulation\n\t3: ACT--Active Mode\n\t4: LPS--Low Power State\n\t5: SUS--Suspend\n\n\tThe transition from different states are defined below\n\tTRANS_CARDEMU_TO_ACT\n\tTRANS_ACT_TO_CARDEMU\n\tTRANS_CARDEMU_TO_SUS\n\tTRANS_SUS_TO_CARDEMU\n\tTRANS_CARDEMU_TO_PDN\n\tTRANS_ACT_TO_LPS\n\tTRANS_LPS_TO_ACT\n\n\tTRANS_END\n*/\n#define\tRTL8192F_TRANS_CARDEMU_TO_ACT_STEPS\t38\n#define\tRTL8192F_TRANS_ACT_TO_CARDEMU_STEPS\t8\n#define\tRTL8192F_TRANS_CARDEMU_TO_SUS_STEPS\t7\n#define\tRTL8192F_TRANS_SUS_TO_CARDEMU_STEPS\t5\n#define\tRTL8192F_TRANS_CARDEMU_TO_CARDDIS_STEPS\t8\n#define\tRTL8192F_TRANS_CARDDIS_TO_CARDEMU_STEPS\t8\n#define\tRTL8192F_TRANS_CARDEMU_TO_PDN_STEPS\t4\n#define\tRTL8192F_TRANS_PDN_TO_CARDEMU_STEPS\t1\n#define\tRTL8192F_TRANS_ACT_TO_LPS_STEPS\t\t13\n#define\tRTL8192F_TRANS_LPS_TO_ACT_STEPS\t\t11\t\n#define\tRTL8192F_TRANS_END_STEPS\t1\n\n\n#define RTL8192F_TRANS_CARDEMU_TO_ACT \t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/\t\\\n\t{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/\t\\\n\t{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \\\n\t{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \\\n\t{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/\t\\\n\t{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/ \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, (BIT1|BIT0), 0}, \\\n\t{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},/* SWR OCP enable 0x10[18]=1*/ \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \\\n\t{0x007f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x7c[31]=1,LDO has max output capability*/ \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \\\n\t{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \\\n\t{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\\\n\t{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 data mode*/\\\n\t{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\\\n\t{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\\\n\t{0x0068, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/*RF HW ON/OFF Enable*/\\\n\t{0x001C, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/*Register Lock Disable*/\\\n\t{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\\\n\t{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S1*/\\\n\t{0x007B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S0*/\\\n\t{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/*enable RF path S1*/\\\n\t{0x007B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/*enalbe RF path S0*/\\\n\t{0x0097, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*AFE_Ctrl*/\\\n\t{0x00DC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xCC},/*AFE_Ctrl*/\\\n\t{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x18, 0x00},/*AFE_Ctrl 0x24[4:3]=00 for xtal gmn*/\\\n\t{0x1050, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[7:0] Pull down software register*/\\\n\t{0x1051, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[15:8] Pull down software register*/\\\n\t{0x1052, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[23:16] Pull down software register*/\\\n\t{0x1053, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[31:24] Pull down software register*/\\\n\t{0x105B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_B[7:0] Pull down software register*/\\\n\t{0x001C, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*Register Lock Enable*/\\\n\t{0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT7|BIT6), 0x3},/*set HCI Power sequence state delay time:0*/\n\n\t\n#define RTL8192F_TRANS_ACT_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x2[0]=0 Reset BB,RF enter Power Down mode*/ \\\n\t{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/ \\\n\t{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x10[18] = 0 to disable ocp*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \\\n\t{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \\\n\t{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\\\n\n\n#define RTL8192F_TRANS_CARDEMU_TO_SUS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 USB|SDIO SOP option to disable BG/MB/ACK/SWR*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/\n\n#define RTL8192F_TRANS_SUS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\n\t\n\n#define RTL8192F_TRANS_CARDEMU_TO_CARDDIS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend*/\t\\\n\t{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/\n\n#define RTL8192F_TRANS_CARDDIS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\\\n\t{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/\t\\\n\t{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x10[18] = 1 to enable ocp*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/\n\n\n#define RTL8192F_TRANS_CARDEMU_TO_PDN\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/\n\n#define RTL8192F_TRANS_PDN_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/\n\n#define RTL8192F_TRANS_ACT_TO_LPS\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/\t\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/\t\\\n\t{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/\t\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/\t\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \\\n\t{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/\t\\\n\t{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/\t\\\n\n\n#define RTL8192F_TRANS_LPS_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\\\n\t{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\\\n\t{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*.\t0x08[4] = 0 \t switch TSF to 40M*/\\\n\t{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\\\n\t{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*.\t0x29[7:6] = 2b'00\t enable BB clock*/\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*.\t0x101[1] = 1*/\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*.\t0x100[7:0] = 0xFF\t enable WMAC TRX*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*.\t0x02[1:0] = 2b'11\t enable BB macro*/\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*.\t0x522 = 0*/\n \n#define RTL8192F_TRANS_END\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //\n\n\nextern WLAN_PWR_CFG rtl8192F_power_on_flow[RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8192F_radio_off_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8192F_card_disable_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_CARDDIS_STEPS+RTL8192F_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8192F_card_enable_flow[RTL8192F_TRANS_CARDDIS_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8192F_suspend_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_SUS_STEPS+RTL8192F_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8192F_resume_flow[RTL8192F_TRANS_SUS_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8192F_hwpdn_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192F_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8192F_enter_lps_flow[RTL8192F_TRANS_ACT_TO_LPS_STEPS+RTL8192F_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8192F_leave_lps_flow[RTL8192F_TRANS_LPS_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];\n\n#endif\n"
  },
  {
    "path": "include/Hal8703BPhyCfg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8703BPHYCFG_H__\n#define __INC_HAL8703BPHYCFG_H__\n\n/*--------------------------Define Parameters-------------------------------*/\n#define LOOP_LIMIT\t\t\t\t5\n#define MAX_STALL_TIME\t\t\t50\t\t/* us */\n#define AntennaDiversityValue\t0x80\t/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */\n#define MAX_TXPWR_IDX_NMODE_92S\t63\n#define Reset_Cnt_Limit\t\t\t3\n\n#ifdef CONFIG_PCI_HCI\n\t#define MAX_AGGR_NUM\t0x0B\n#else\n\t#define MAX_AGGR_NUM\t0x07\n#endif /* CONFIG_PCI_HCI */\n\n\n/*--------------------------Define Parameters End-------------------------------*/\n\n\n/*------------------------------Define structure----------------------------*/\n\n/*------------------------------Define structure End----------------------------*/\n\n/*--------------------------Exported Function prototype---------------------*/\nu32\nPHY_QueryBBReg_8703B(\n\t\tPADAPTER\tAdapter,\n\t\tu32\t\tRegAddr,\n\t\tu32\t\tBitMask\n);\n\nvoid\nPHY_SetBBReg_8703B(\n\t\tPADAPTER\tAdapter,\n\t\tu32\t\tRegAddr,\n\t\tu32\t\tBitMask,\n\t\tu32\t\tData\n);\n\nu32\nPHY_QueryRFReg_8703B(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tRegAddr,\n\t\tu32\t\t\t\tBitMask\n);\n\nvoid\nPHY_SetRFReg_8703B(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tRegAddr,\n\t\tu32\t\t\t\tBitMask,\n\t\tu32\t\t\t\tData\n);\n\n/* MAC/BB/RF HAL config */\nint PHY_BBConfig8703B(PADAPTER\tAdapter);\n\nint PHY_RFConfig8703B(PADAPTER\tAdapter);\n\ns32 PHY_MACConfig8703B(PADAPTER padapter);\n\nint\nPHY_ConfigRFWithParaFile_8703B(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu8\t\t\t\t\t*pFileName,\n\tenum rf_path\t\t\t\teRFPath\n);\n\nvoid\nPHY_SetTxPowerIndex_8703B(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu32\t\t\t\t\tPowerIndex,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate\n);\n\nu8\nPHY_GetTxPowerIndex_8703B(\n\t\tPADAPTER\t\t\tpAdapter,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate,\n\t\tu8\t\t\t\t\tBandWidth,\n\t\tu8\t\t\t\t\tChannel,\n\tstruct txpwr_idx_comp *tic\n);\n\nvoid\nPHY_SetTxPowerLevel8703B(\n\t\tPADAPTER\t\tAdapter,\n\t\tu8\t\t\tchannel\n);\n\nvoid\nPHY_SetSwChnlBWMode8703B(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu8\t\t\t\t\tchannel,\n\t\tenum channel_width\tBandwidth,\n\t\tu8\t\t\t\t\tOffset40,\n\t\tu8\t\t\t\t\tOffset80\n);\n\nvoid phy_set_rf_path_switch_8703b(\n\t\tstruct dm_struct\t\t*phydm,\n\t\tbool\t\tbMain\n);\n\n/*--------------------------Exported Function prototype End---------------------*/\n\n#endif\n"
  },
  {
    "path": "include/Hal8703BPhyReg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8703BPHYREG_H__\n#define __INC_HAL8703BPHYREG_H__\n\n#define\t\trSYM_WLBT_PAPE_SEL\t\t0x64\n/*\n * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00\n * 3. RF register 0x00-2E\n * 4. Bit Mask for BB/RF register\n * 5. Other defintion for BB/RF R/W\n *   */\n\n\n/*\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 1. Page1(0x100)\n *   */\n#define\t\trPMAC_Reset\t\t\t\t\t0x100\n#define\t\trPMAC_TxStart\t\t\t\t\t0x104\n#define\t\trPMAC_TxLegacySIG\t\t\t\t0x108\n#define\t\trPMAC_TxHTSIG1\t\t\t\t0x10c\n#define\t\trPMAC_TxHTSIG2\t\t\t\t0x110\n#define\t\trPMAC_PHYDebug\t\t\t\t0x114\n#define\t\trPMAC_TxPacketNum\t\t\t\t0x118\n#define\t\trPMAC_TxIdle\t\t\t\t\t0x11c\n#define\t\trPMAC_TxMACHeader0\t\t\t0x120\n#define\t\trPMAC_TxMACHeader1\t\t\t0x124\n#define\t\trPMAC_TxMACHeader2\t\t\t0x128\n#define\t\trPMAC_TxMACHeader3\t\t\t0x12c\n#define\t\trPMAC_TxMACHeader4\t\t\t0x130\n#define\t\trPMAC_TxMACHeader5\t\t\t0x134\n#define\t\trPMAC_TxDataType\t\t\t\t0x138\n#define\t\trPMAC_TxRandomSeed\t\t\t0x13c\n#define\t\trPMAC_CCKPLCPPreamble\t\t\t0x140\n#define\t\trPMAC_CCKPLCPHeader\t\t\t0x144\n#define\t\trPMAC_CCKCRC16\t\t\t\t0x148\n#define\t\trPMAC_OFDMRxCRC32OK\t\t\t0x170\n#define\t\trPMAC_OFDMRxCRC32Er\t\t\t0x174\n#define\t\trPMAC_OFDMRxParityEr\t\t\t0x178\n#define\t\trPMAC_OFDMRxCRC8Er\t\t\t0x17c\n#define\t\trPMAC_CCKCRxRC16Er\t\t\t0x180\n#define\t\trPMAC_CCKCRxRC32Er\t\t\t0x184\n#define\t\trPMAC_CCKCRxRC32OK\t\t\t0x188\n#define\t\trPMAC_TxStatus\t\t\t\t\t0x18c\n\n/*\n * 2. Page2(0x200)\n *\n * The following two definition are only used for USB interface. */\n#define\t\tRF_BB_CMD_ADDR\t\t\t\t0x02c0\t/* RF/BB read/write command address. */\n#define\t\tRF_BB_CMD_DATA\t\t\t\t0x02c4\t/* RF/BB read/write command data. */\n\n/*\n * 3. Page8(0x800)\n *   */\n#define\t\trFPGA0_RFMOD\t\t\t\t0x800\t/* RF mode & CCK TxSC */ /* RF BW Setting?? */\n\n#define\t\trFPGA0_TxInfo\t\t\t\t0x804\t/* Status report?? */\n#define\t\trFPGA0_PSDFunction\t\t\t0x808\n\n#define\t\trFPGA0_TxGainStage\t\t\t0x80c\t/* Set TX PWR init gain? */\n\n#define\t\trFPGA0_RFTiming1\t\t\t0x810\t/* Useless now */\n#define\t\trFPGA0_RFTiming2\t\t\t0x814\n\n#define\t\trFPGA0_XA_HSSIParameter1\t\t0x820\t/* RF 3 wire register */\n#define\t\trFPGA0_XA_HSSIParameter2\t\t0x824\n#define\t\trFPGA0_XB_HSSIParameter1\t\t0x828\n#define\t\trFPGA0_XB_HSSIParameter2\t\t0x82c\n#define\t\trTxAGC_B_Rate18_06\t\t\t\t0x830\n#define\t\trTxAGC_B_Rate54_24\t\t\t\t0x834\n#define\t\trTxAGC_B_CCK1_55_Mcs32\t\t0x838\n#define\t\trTxAGC_B_Mcs03_Mcs00\t\t\t0x83c\n\n#define\t\trTxAGC_B_Mcs07_Mcs04\t\t\t0x848\n#define\t\trTxAGC_B_Mcs11_Mcs08\t\t\t0x84c\n\n#define\t\trFPGA0_XA_LSSIParameter\t\t0x840\n#define\t\trFPGA0_XB_LSSIParameter\t\t0x844\n\n#define\t\trFPGA0_RFWakeUpParameter\t\t0x850\t/* Useless now */\n#define\t\trFPGA0_RFSleepUpParameter\t\t0x854\n\n#define\t\trFPGA0_XAB_SwitchControl\t\t0x858\t/* RF Channel switch */\n#define\t\trFPGA0_XCD_SwitchControl\t\t0x85c\n\n#define\t\trFPGA0_XA_RFInterfaceOE\t\t0x860\t/* RF Channel switch */\n#define\t\trFPGA0_XB_RFInterfaceOE\t\t0x864\n\n#define\t\trTxAGC_B_Mcs15_Mcs12\t\t\t0x868\n#define\t\trTxAGC_B_CCK11_A_CCK2_11\t\t0x86c\n\n#define\t\trFPGA0_XAB_RFInterfaceSW\t\t0x870\t/* RF Interface Software Control */\n#define\t\trFPGA0_XCD_RFInterfaceSW\t\t0x874\n\n#define\t\trFPGA0_XAB_RFParameter\t\t0x878\t/* RF Parameter */\n#define\t\trFPGA0_XCD_RFParameter\t\t0x87c\n\n#define\t\trFPGA0_AnalogParameter1\t\t0x880\t/* Crystal cap setting RF-R/W protection for parameter4?? */\n#define\t\trFPGA0_AnalogParameter2\t\t0x884\n#define\t\trFPGA0_AnalogParameter3\t\t0x888\t/* Useless now */\n#define\t\trFPGA0_AnalogParameter4\t\t0x88c\n\n#define\t\trFPGA0_XA_LSSIReadBack\t\t0x8a0\t/* Tranceiver LSSI Readback */\n#define\t\trFPGA0_XB_LSSIReadBack\t\t0x8a4\n#define\t\trFPGA0_XC_LSSIReadBack\t\t0x8a8\n#define\t\trFPGA0_XD_LSSIReadBack\t\t0x8ac\n\n#define\t\trFPGA0_PSDReport\t\t\t\t0x8b4\t/* Useless now */\n#define\t\tTransceiverA_HSPI_Readback\t0x8b8\t/* Transceiver A HSPI Readback */\n#define\t\tTransceiverB_HSPI_Readback\t0x8bc\t/* Transceiver B HSPI Readback */\n#define\t\trFPGA0_XAB_RFInterfaceRB\t\t0x8e0\t/* Useless now */ /* RF Interface Readback Value */\n#define\t\trFPGA0_XCD_RFInterfaceRB\t\t0x8e4\t/* Useless now */\n\n/*\n * 4. Page9(0x900)\n *   */\n#define\trFPGA1_RFMOD\t\t\t\t0x900\t/* RF mode & OFDM TxSC */ /* RF BW Setting?? */\n#define\trFPGA1_TxBlock\t\t\t\t0x904\t/* Useless now */\n#define\trFPGA1_DebugSelect\t\t\t0x908\t/* Useless now */\n#define\trFPGA1_TxInfo\t\t\t\t0x90c\t/* Useless now */ /* Status report?? */\n#define\trDPDT_control\t\t\t\t0x92c\n#define\trfe_ctrl_anta_src\t\t\t\t0x930\n#define\trS0S1_PathSwitch\t\t\t0x948\n#define\trBBrx_DFIR\t\t\t\t\t0x954\n\n/*\n * 5. PageA(0xA00)\n *\n * Set Control channel to upper or lower. These settings are required only for 40MHz */\n#define\t\trCCK0_System\t\t\t\t0xa00\n\n#define\t\trCCK0_AFESetting\t\t\t0xa04\t/* Disable init gain now */ /* Select RX path by RSSI */\n#define\t\trCCK0_CCA\t\t\t\t\t0xa08\t/* Disable init gain now */ /* Init gain */\n\n#define\t\trCCK0_RxAGC1\t\t\t\t0xa0c\t/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */\n#define\t\trCCK0_RxAGC2\t\t\t\t0xa10\t/* AGC & DAGC */\n\n#define\t\trCCK0_RxHP\t\t\t\t\t0xa14\n\n#define\t\trCCK0_DSPParameter1\t\t0xa18\t/* Timing recovery & Channel estimation threshold */\n#define\t\trCCK0_DSPParameter2\t\t0xa1c\t/* SQ threshold */\n\n#define\t\trCCK0_TxFilter1\t\t\t\t0xa20\n#define\t\trCCK0_TxFilter2\t\t\t\t0xa24\n#define\t\trCCK0_DebugPort\t\t\t0xa28\t/* debug port and Tx filter3 */\n#define\t\trCCK0_FalseAlarmReport\t\t0xa2c\t/* 0xa2d\tuseless now 0xa30-a4f channel report */\n#define\t\trCCK0_TRSSIReport\t\t0xa50\n#define\t\trCCK0_RxReport            \t\t0xa54  /* 0xa57 */\n#define\t\trCCK0_FACounterLower      \t0xa5c  /* 0xa5b */\n#define\t\trCCK0_FACounterUpper      \t0xa58  /* 0xa5c */\n\n/*\n * PageB(0xB00)\n *   */\n#define rPdp_AntA\t\t\t\t\t\t0xb00\n#define rPdp_AntA_4\t\t\t\t\t\t0xb04\n#define rPdp_AntA_8\t\t\t\t\t\t0xb08\n#define rPdp_AntA_C\t\t\t\t\t\t0xb0c\n#define rPdp_AntA_10\t\t\t\t\t0xb10\n#define rPdp_AntA_14\t\t\t\t\t0xb14\n#define rPdp_AntA_18\t\t\t\t\t0xb18\n#define rPdp_AntA_1C\t\t\t\t\t0xb1c\n#define rPdp_AntA_20\t\t\t\t\t0xb20\n#define rPdp_AntA_24\t\t\t\t\t0xb24\n\n#define rConfig_Pmpd_AntA\t\t\t\t0xb28\n#define rConfig_ram64x16\t\t\t\t0xb2c\n\n#define rBndA\t\t\t\t\t\t\t0xb30\n#define rHssiPar\t\t\t\t\t\t0xb34\n\n#define rConfig_AntA\t\t\t\t\t0xb68\n#define rConfig_AntB\t\t\t\t\t0xb6c\n\n#define rPdp_AntB\t\t\t\t\t\t0xb70\n#define rPdp_AntB_4\t\t\t\t\t\t0xb74\n#define rPdp_AntB_8\t\t\t\t\t\t0xb78\n#define rPdp_AntB_C\t\t\t\t\t\t0xb7c\n#define rPdp_AntB_10\t\t\t\t\t0xb80\n#define rPdp_AntB_14\t\t\t\t\t0xb84\n#define rPdp_AntB_18\t\t\t\t\t0xb88\n#define rPdp_AntB_1C\t\t\t\t\t0xb8c\n#define rPdp_AntB_20\t\t\t\t\t0xb90\n#define rPdp_AntB_24\t\t\t\t\t0xb94\n\n#define rConfig_Pmpd_AntB\t\t\t\t0xb98\n\n#define rBndB\t\t\t\t\t\t\t0xba0\n\n#define rAPK\t\t\t\t\t\t\t0xbd8\n#define rPm_Rx0_AntA\t\t\t\t\t0xbdc\n#define rPm_Rx1_AntA\t\t\t\t\t0xbe0\n#define rPm_Rx2_AntA\t\t\t\t\t0xbe4\n#define rPm_Rx3_AntA\t\t\t\t\t0xbe8\n#define rPm_Rx0_AntB\t\t\t\t\t0xbec\n#define rPm_Rx1_AntB\t\t\t\t\t0xbf0\n#define rPm_Rx2_AntB\t\t\t\t\t0xbf4\n#define rPm_Rx3_AntB\t\t\t\t\t0xbf8\n/*\n * 6. PageC(0xC00)\n *   */\n#define\t\trOFDM0_LSTF\t\t\t\t0xc00\n\n#define\t\trOFDM0_TRxPathEnable\t\t0xc04\n#define\t\trOFDM0_TRMuxPar\t\t\t0xc08\n#define\t\trOFDM0_TRSWIsolation\t\t0xc0c\n\n#define\t\trOFDM0_XARxAFE\t\t\t0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */\n#define\t\trOFDM0_XARxIQImbalance    \t0xc14  /* RxIQ imblance matrix */\n#define\t\trOFDM0_XBRxAFE\t\t0xc18\n#define\t\trOFDM0_XBRxIQImbalance\t0xc1c\n#define\t\trOFDM0_XCRxAFE\t\t0xc20\n#define\t\trOFDM0_XCRxIQImbalance\t0xc24\n#define\t\trOFDM0_XDRxAFE\t\t0xc28\n#define\t\trOFDM0_XDRxIQImbalance\t0xc2c\n\n#define\t\trOFDM0_RxDetector1\t\t\t0xc30  /* PD, BW & SBD\t */ /* DM tune init gain */\n#define\t\trOFDM0_RxDetector2\t\t\t0xc34  /* SBD & Fame Sync. */\n#define\t\trOFDM0_RxDetector3\t\t\t0xc38  /* Frame Sync. */\n#define\t\trOFDM0_RxDetector4\t\t\t0xc3c  /* PD, SBD, Frame Sync & Short-GI */\n\n#define\t\trOFDM0_RxDSP\t\t\t\t0xc40  /* Rx Sync Path */\n#define\t\trOFDM0_CFOandDAGC\t\t0xc44  /* CFO & DAGC */\n#define\t\trOFDM0_CCADropThreshold\t0xc48 /* CCA Drop threshold */\n#define\t\trOFDM0_ECCAThreshold\t\t0xc4c /* energy CCA */\n\n#define\t\trOFDM0_XAAGCCore1\t\t\t0xc50\t/* DIG */\n#define\t\trOFDM0_XAAGCCore2\t\t\t0xc54\n#define\t\trOFDM0_XBAGCCore1\t\t\t0xc58\n#define\t\trOFDM0_XBAGCCore2\t\t\t0xc5c\n#define\t\trOFDM0_XCAGCCore1\t\t\t0xc60\n#define\t\trOFDM0_XCAGCCore2\t\t\t0xc64\n#define\t\trOFDM0_XDAGCCore1\t\t\t0xc68\n#define\t\trOFDM0_XDAGCCore2\t\t\t0xc6c\n\n#define\t\trOFDM0_AGCParameter1\t\t\t0xc70\n#define\t\trOFDM0_AGCParameter2\t\t\t0xc74\n#define\t\trOFDM0_AGCRSSITable\t\t\t0xc78\n#define\t\trOFDM0_HTSTFAGC\t\t\t\t0xc7c\n\n#define\t\trOFDM0_XATxIQImbalance\t\t0xc80\t/* TX PWR TRACK and DIG */\n#define\t\trOFDM0_XATxAFE\t\t\t\t0xc84\n#define\t\trOFDM0_XBTxIQImbalance\t\t0xc88\n#define\t\trOFDM0_XBTxAFE\t\t\t\t0xc8c\n#define\t\trOFDM0_XCTxIQImbalance\t\t0xc90\n#define\t\trOFDM0_XCTxAFE\t\t\t0xc94\n#define\t\trOFDM0_XDTxIQImbalance\t\t0xc98\n#define\t\trOFDM0_XDTxAFE\t\t\t\t0xc9c\n\n#define\t\trOFDM0_RxIQExtAnta\t\t\t0xca0\n#define\t\trOFDM0_TxCoeff1\t\t\t\t0xca4\n#define\t\trOFDM0_TxCoeff2\t\t\t\t0xca8\n#define\t\trOFDM0_TxCoeff3\t\t\t\t0xcac\n#define\t\trOFDM0_TxCoeff4\t\t\t\t0xcb0\n#define\t\trOFDM0_TxCoeff5\t\t\t\t0xcb4\n#define\t\trOFDM0_TxCoeff6\t\t\t\t0xcb8\n#define\t\trOFDM0_RxHPParameter\t\t\t0xce0\n#define\t\trOFDM0_TxPseudoNoiseWgt\t\t0xce4\n#define\t\trOFDM0_FrameSync\t\t\t\t0xcf0\n#define\t\trOFDM0_DFSReport\t\t\t\t0xcf4\n\n/*\n * 7. PageD(0xD00)\n *   */\n#define\t\trOFDM1_LSTF\t\t\t\t\t0xd00\n#define\t\trOFDM1_TRxPathEnable\t\t\t0xd04\n\n#define\t\trOFDM1_CFO\t\t\t\t\t\t0xd08\t/* No setting now */\n#define\t\trOFDM1_CSI1\t\t\t\t\t0xd10\n#define\t\trOFDM1_SBD\t\t\t\t\t\t0xd14\n#define\t\trOFDM1_CSI2\t\t\t\t\t0xd18\n#define\t\trOFDM1_CFOTracking\t\t\t0xd2c\n#define\t\trOFDM1_TRxMesaure1\t\t\t0xd34\n#define\t\trOFDM1_IntfDet\t\t\t\t\t0xd3c\n#define\t\trOFDM1_PseudoNoiseStateAB\t\t0xd50\n#define\t\trOFDM1_PseudoNoiseStateCD\t\t0xd54\n#define\t\trOFDM1_RxPseudoNoiseWgt\t\t0xd58\n\n#define\t\trOFDM_PHYCounter1\t\t\t\t0xda0  /* cca, parity fail */\n#define\t\trOFDM_PHYCounter2\t\t\t\t0xda4  /* rate illegal, crc8 fail */\n#define\t\trOFDM_PHYCounter3\t\t\t\t0xda8  /* MCS not support */\n\n#define\t\trOFDM_ShortCFOAB\t\t\t\t0xdac\t/* No setting now */\n#define\t\trOFDM_ShortCFOCD\t\t\t\t0xdb0\n#define\t\trOFDM_LongCFOAB\t\t\t\t0xdb4\n#define\t\trOFDM_LongCFOCD\t\t\t\t0xdb8\n#define\t\trOFDM_TailCFOAB\t\t\t\t0xdbc\n#define\t\trOFDM_TailCFOCD\t\t\t\t0xdc0\n#define\t\trOFDM_PWMeasure1\t\t0xdc4\n#define\t\trOFDM_PWMeasure2\t\t0xdc8\n#define\t\trOFDM_BWReport\t\t\t\t0xdcc\n#define\t\trOFDM_AGCReport\t\t\t\t0xdd0\n#define\t\trOFDM_RxSNR\t\t\t\t\t0xdd4\n#define\t\trOFDM_RxEVMCSI\t\t\t\t0xdd8\n#define\t\trOFDM_SIGReport\t\t\t\t0xddc\n\n\n/*\n * 8. PageE(0xE00)\n *   */\n#define\t\trTxAGC_A_Rate18_06\t\t\t0xe00\n#define\t\trTxAGC_A_Rate54_24\t\t\t0xe04\n#define\t\trTxAGC_A_CCK1_Mcs32\t\t\t0xe08\n#define\t\trTxAGC_A_Mcs03_Mcs00\t\t\t0xe10\n#define\t\trTxAGC_A_Mcs07_Mcs04\t\t\t0xe14\n#define\t\trTxAGC_A_Mcs11_Mcs08\t\t\t0xe18\n#define\t\trTxAGC_A_Mcs15_Mcs12\t\t\t0xe1c\n\n#define\t\trFPGA0_IQK\t\t\t\t\t0xe28\n#define\t\trTx_IQK_Tone_A\t\t\t\t0xe30\n#define\t\trRx_IQK_Tone_A\t\t\t\t0xe34\n#define\t\trTx_IQK_PI_A\t\t\t\t\t0xe38\n#define\t\trRx_IQK_PI_A\t\t\t\t\t0xe3c\n\n#define\t\trTx_IQK\t\t\t\t\t\t0xe40\n#define\t\trRx_IQK\t\t\t\t\t\t0xe44\n#define\t\trIQK_AGC_Pts\t\t\t\t\t0xe48\n#define\t\trIQK_AGC_Rsp\t\t\t\t\t0xe4c\n#define\t\trTx_IQK_Tone_B\t\t\t\t0xe50\n#define\t\trRx_IQK_Tone_B\t\t\t\t0xe54\n#define\t\trTx_IQK_PI_B\t\t\t\t\t0xe58\n#define\t\trRx_IQK_PI_B\t\t\t\t\t0xe5c\n#define\t\trIQK_AGC_Cont\t\t\t\t0xe60\n\n#define\t\trBlue_Tooth\t\t\t\t\t0xe6c\n#define\t\trRx_Wait_CCA\t\t\t\t\t0xe70\n#define\t\trTx_CCK_RFON\t\t\t\t\t0xe74\n#define\t\trTx_CCK_BBON\t\t\t\t0xe78\n#define\t\trTx_OFDM_RFON\t\t\t\t0xe7c\n#define\t\trTx_OFDM_BBON\t\t\t\t0xe80\n#define\t\trTx_To_Rx\t\t\t\t\t0xe84\n#define\t\trTx_To_Tx\t\t\t\t\t0xe88\n#define\t\trRx_CCK\t\t\t\t\t\t0xe8c\n\n#define\t\trTx_Power_Before_IQK_A\t\t0xe94\n#define\t\trTx_Power_After_IQK_A\t\t\t0xe9c\n\n#define\t\trRx_Power_Before_IQK_A\t\t0xea0\n#define\t\trRx_Power_Before_IQK_A_2\t\t0xea4\n#define\t\trRx_Power_After_IQK_A\t\t\t0xea8\n#define\t\trRx_Power_After_IQK_A_2\t\t0xeac\n\n#define\t\trTx_Power_Before_IQK_B\t\t0xeb4\n#define\t\trTx_Power_After_IQK_B\t\t\t0xebc\n\n#define\t\trRx_Power_Before_IQK_B\t\t0xec0\n#define\t\trRx_Power_Before_IQK_B_2\t\t0xec4\n#define\t\trRx_Power_After_IQK_B\t\t\t0xec8\n#define\t\trRx_Power_After_IQK_B_2\t\t0xecc\n\n#define\t\trRx_OFDM\t\t\t\t\t0xed0\n#define\t\trRx_Wait_RIFS\t\t\t\t0xed4\n#define\t\trRx_TO_Rx\t\t\t\t\t0xed8\n#define\t\trStandby\t\t\t\t\t\t0xedc\n#define\t\trSleep\t\t\t\t\t\t0xee0\n#define\t\trPMPD_ANAEN\t\t\t\t0xeec\n\n/*\n * 7. RF Register 0x00-0x2E (RF 8256)\n * RF-0222D 0x00-3F\n *\n * Zebra1 */\n#define\t\trZebra1_HSSIEnable\t\t\t\t0x0\t/* Useless now */\n#define\t\trZebra1_TRxEnable1\t\t\t\t0x1\n#define\t\trZebra1_TRxEnable2\t\t\t\t0x2\n#define\t\trZebra1_AGC\t\t\t\t\t0x4\n#define\t\trZebra1_ChargePump\t\t\t0x5\n#define\t\trZebra1_Channel\t\t\t\t0x7\t/* RF channel switch */\n\n/* #endif */\n#define\t\trZebra1_TxGain\t\t\t\t\t0x8\t/* Useless now */\n#define\t\trZebra1_TxLPF\t\t\t\t\t0x9\n#define\t\trZebra1_RxLPF\t\t\t\t\t0xb\n#define\t\trZebra1_RxHPFCorner\t\t\t0xc\n\n/* Zebra4 */\n#define\t\trGlobalCtrl\t\t\t\t\t\t0\t/* Useless now */\n#define\t\trRTL8256_TxLPF\t\t\t\t\t19\n#define\t\trRTL8256_RxLPF\t\t\t\t\t11\n\n/* RTL8258 */\n#define\t\trRTL8258_TxLPF\t\t\t\t\t0x11\t/* Useless now */\n#define\t\trRTL8258_RxLPF\t\t\t\t\t0x13\n#define\t\trRTL8258_RSSILPF\t\t\t\t0xa\n\n/*\n * RL6052 Register definition\n *   */\n#define\t\tRF_AC\t\t\t\t\t\t0x00\t/*  */\n\n#define\t\tRF_IQADJ_G1\t\t\t\t0x01\t/*  */\n#define\t\tRF_IQADJ_G2\t\t\t\t0x02\t/*  */\n#define\t\tRF_BS_PA_APSET_G1_G4\t\t0x03\n#define\t\tRF_BS_PA_APSET_G5_G8\t\t0x04\n#define\t\tRF_POW_TRSW\t\t\t\t0x05\t/*  */\n\n#define\t\tRF_GAIN_RX\t\t\t\t\t0x06\t/*  */\n#define\t\tRF_GAIN_TX\t\t\t\t\t0x07\t/*  */\n\n#define\t\tRF_TXM_IDAC\t\t\t\t0x08\t/*  */\n#define\t\tRF_IPA_G\t\t\t\t\t0x09\t/*  */\n#define\t\tRF_TXBIAS_G\t\t\t\t0x0A\n#define\t\tRF_TXPA_AG\t\t\t\t\t0x0B\n#define\t\tRF_IPA_A\t\t\t\t\t0x0C\t/*  */\n#define\t\tRF_TXBIAS_A\t\t\t\t0x0D\n#define\t\tRF_BS_PA_APSET_G9_G11\t0x0E\n#define\t\tRF_BS_IQGEN\t\t\t\t0x0F\t/*  */\n\n#define\t\tRF_MODE1\t\t\t\t\t0x10\t/*  */\n#define\t\tRF_MODE2\t\t\t\t\t0x11\t/*  */\n\n#define\t\tRF_RX_AGC_HP\t\t\t\t0x12\t/*  */\n#define\t\tRF_TX_AGC\t\t\t\t\t0x13\t/*  */\n#define\t\tRF_BIAS\t\t\t\t\t\t0x14\t/*  */\n#define\t\tRF_IPA\t\t\t\t\t\t0x15\t/*  */\n#define\t\tRF_TXBIAS\t\t\t\t\t0x16\n#define\t\tRF_POW_ABILITY\t\t\t0x17\t/*  */\n#define\t\tRF_MODE_AG\t\t\t\t0x18\t/*  */\n#define\t\trRfChannel\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define\t\tRF_CHNLBW\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define\t\tRF_TOP\t\t\t\t\t\t0x19\t/*  */\n\n#define\t\tRF_RX_G1\t\t\t\t\t0x1A\t/*  */\n#define\t\tRF_RX_G2\t\t\t\t\t0x1B\t/*  */\n\n#define\t\tRF_RX_BB2\t\t\t\t\t0x1C\t/*  */\n#define\t\tRF_RX_BB1\t\t\t\t\t0x1D\t/*  */\n\n#define\t\tRF_RCK1\t\t\t\t\t0x1E\t/*  */\n#define\t\tRF_RCK2\t\t\t\t\t0x1F\t/*  */\n\n#define\t\tRF_TX_G1\t\t\t\t\t0x20\t/*  */\n#define\t\tRF_TX_G2\t\t\t\t\t0x21\t/*  */\n#define\t\tRF_TX_G3\t\t\t\t\t0x22\t/*  */\n\n#define\t\tRF_TX_BB1\t\t\t\t\t0x23\t/*  */\n\n#define\t\tRF_T_METER\t\t\t\t\t0x24\t/*  */\n\n#define\t\tRF_SYN_G1\t\t\t\t\t0x25\t/* RF TX Power control */\n#define\t\tRF_SYN_G2\t\t\t\t\t0x26\t/* RF TX Power control */\n#define\t\tRF_SYN_G3\t\t\t\t\t0x27\t/* RF TX Power control */\n#define\t\tRF_SYN_G4\t\t\t\t\t0x28\t/* RF TX Power control */\n#define\t\tRF_SYN_G5\t\t\t\t\t0x29\t/* RF TX Power control */\n#define\t\tRF_SYN_G6\t\t\t\t\t0x2A\t/* RF TX Power control */\n#define\t\tRF_SYN_G7\t\t\t\t\t0x2B\t/* RF TX Power control */\n#define\t\tRF_SYN_G8\t\t\t\t\t0x2C\t/* RF TX Power control */\n\n#define\t\tRF_RCK_OS\t\t\t\t\t0x30\t/* RF TX PA control */\n\n#define\t\tRF_TXPA_G1\t\t\t\t\t0x31\t/* RF TX PA control */\n#define\t\tRF_TXPA_G2\t\t\t\t\t0x32\t/* RF TX PA control */\n#define\t\tRF_TXPA_G3\t\t\t\t\t0x33\t/* RF TX PA control */\n#define\tRF_TX_BIAS_A\t\t\t\t0x35\n#define\tRF_TX_BIAS_D\t\t\t\t0x36\n#define\tRF_LOBF_9\t\t\t\t\t0x38\n#define \tRF_RXRF_A3\t\t\t\t\t0x3C\t/*\t */\n#define\tRF_TRSW\t\t\t\t\t0x3F\n\n#define\tRF_TXRF_A2\t\t\t\t\t0x41\n#define\tRF_TXPA_G4\t\t\t\t\t0x46\n#define\tRF_TXPA_A4\t\t\t\t\t0x4B\n#define\tRF_0x52\t\t\t\t\t0x52\n#define\tRF_WE_LUT\t\t\t\t\t0xEF\n#define\tRF_S0S1\t\t\t\t\t0xB0\n\n/*\n * Bit Mask\n *\n * 1. Page1(0x100) */\n#define\t\tbBBResetB\t\t\t\t\t\t0x100\t/* Useless now? */\n#define\t\tbGlobalResetB\t\t\t\t\t0x200\n#define\t\tbOFDMTxStart\t\t\t\t\t0x4\n#define\t\tbCCKTxStart\t\t\t\t\t\t0x8\n#define\t\tbCRC32Debug\t\t\t\t\t0x100\n#define\t\tbPMACLoopback\t\t\t\t\t0x10\n#define\t\tbTxLSIG\t\t\t\t\t\t\t0xffffff\n#define\t\tbOFDMTxRate\t\t\t\t\t0xf\n#define\t\tbOFDMTxReserved\t\t\t\t0x10\n#define\t\tbOFDMTxLength\t\t\t\t\t0x1ffe0\n#define\t\tbOFDMTxParity\t\t\t\t\t0x20000\n#define\t\tbTxHTSIG1\t\t\t\t\t\t0xffffff\n#define\t\tbTxHTMCSRate\t\t\t\t\t0x7f\n#define\t\tbTxHTBW\t\t\t\t\t\t0x80\n#define\t\tbTxHTLength\t\t\t\t\t0xffff00\n#define\t\tbTxHTSIG2\t\t\t\t\t\t0xffffff\n#define\t\tbTxHTSmoothing\t\t\t\t\t0x1\n#define\t\tbTxHTSounding\t\t\t\t\t0x2\n#define\t\tbTxHTReserved\t\t\t\t\t0x4\n#define\t\tbTxHTAggreation\t\t\t\t0x8\n#define\t\tbTxHTSTBC\t\t\t\t\t\t0x30\n#define\t\tbTxHTAdvanceCoding\t\t\t0x40\n#define\t\tbTxHTShortGI\t\t\t\t\t0x80\n#define\t\tbTxHTNumberHT_LTF\t\t\t0x300\n#define\t\tbTxHTCRC8\t\t\t\t\t\t0x3fc00\n#define\t\tbCounterReset\t\t\t\t\t0x10000\n#define\t\tbNumOfOFDMTx\t\t\t\t\t0xffff\n#define\t\tbNumOfCCKTx\t\t\t\t\t0xffff0000\n#define\t\tbTxIdleInterval\t\t\t\t\t0xffff\n#define\t\tbOFDMService\t\t\t\t\t0xffff0000\n#define\t\tbTxMACHeader\t\t\t\t\t0xffffffff\n#define\t\tbTxDataInit\t\t\t\t\t\t0xff\n#define\t\tbTxHTMode\t\t\t\t\t\t0x100\n#define\t\tbTxDataType\t\t\t\t\t0x30000\n#define\t\tbTxRandomSeed\t\t\t\t\t0xffffffff\n#define\t\tbCCKTxPreamble\t\t\t\t\t0x1\n#define\t\tbCCKTxSFD\t\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxSIG\t\t\t\t\t\t0xff\n#define\t\tbCCKTxService\t\t\t\t\t0xff00\n#define\t\tbCCKLengthExt\t\t\t\t\t0x8000\n#define\t\tbCCKTxLength\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxCRC16\t\t\t\t\t0xffff\n#define\t\tbCCKTxStatus\t\t\t\t\t0x1\n#define\t\tbOFDMTxStatus\t\t\t\t\t0x2\n\n#define\t\tIS_BB_REG_OFFSET_92S(_Offset)\t\t((_Offset >= 0x800) && (_Offset <= 0xfff))\n#define\tRF_TX_GAIN_OFFSET_8703B(_val) (abs((_val)) | (((_val) > 0) ? BIT5 : 0))\n\n/* 2. Page8(0x800) */\n#define\t\tbRFMOD\t\t\t\t\t\t\t0x1\t/* Reg 0x800 rFPGA0_RFMOD */\n#define\t\tbJapanMode\t\t\t\t\t\t0x2\n#define\t\tbCCKTxSC\t\t\t\t\t\t0x30\n#define\t\tbCCKEn\t\t\t\t\t\t\t0x1000000\n#define\t\tbOFDMEn\t\t\t\t\t\t0x2000000\n\n#define\t\tbOFDMRxADCPhase           \t\t0x10000\t/* Useless now */\n#define\t\tbOFDMTxDACPhase\t\t0x40000\n#define\t\tbXATxAGC\t\t\t0x3f\n\n#define\t\tbAntennaSelect\t\t0x0300\n\n#define\t\tbXBTxAGC                  \t\t\t0xf00\t/* Reg 80c rFPGA0_TxGainStage */\n#define\t\tbXCTxAGC\t\t\t0xf000\n#define\t\tbXDTxAGC\t\t\t0xf0000\n\n#define\t\tbPAStart                  \t\t\t0xf0000000\t/* Useless now */\n#define\t\tbTRStart\t\t\t0x00f00000\n#define\t\tbRFStart\t\t\t0x0000f000\n#define\t\tbBBStart\t\t\t0x000000f0\n#define\t\tbBBCCKStart\t\t0x0000000f\n#define\t\tbPAEnd                    \t\t\t0xf          /* Reg0x814 */\n#define\t\tbTREnd\t\t\t0x0f000000\n#define\t\tbRFEnd\t\t\t0x000f0000\n#define\t\tbCCAMask                  \t\t\t0x000000f0   /* T2R */\n#define\t\tbR2RCCAMask\t\t0x00000f00\n#define\t\tbHSSI_R2TDelay\t\t0xf8000000\n#define\t\tbHSSI_T2RDelay\t\t0xf80000\n#define\t\tbContTxHSSI               \t\t0x400     /* chane gain at continue Tx */\n#define\t\tbIGFromCCK\t\t0x200\n#define\t\tbAGCAddress\t\t0x3f\n#define\t\tbRxHPTx\t\t\t0x7000\n#define\t\tbRxHPT2R\t\t\t0x38000\n#define\t\tbRxHPCCKIni\t\t0xc0000\n#define\t\tbAGCTxCode\t\t0xc00000\n#define\t\tbAGCRxCode\t\t0x300000\n\n#define\t\tb3WireDataLength          \t\t0x800\t/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */\n#define\t\tb3WireAddressLength\t\t0x400\n\n#define\t\tb3WireRFPowerDown         \t\t0x1\t/* Useless now\n * #define bHWSISelect\t\t0x8 */\n#define\t\tb5GPAPEPolarity\t\t0x40000000\n#define\t\tb2GPAPEPolarity\t\t0x80000000\n#define\t\tbRFSW_TxDefaultAnt\t\t0x3\n#define\t\tbRFSW_TxOptionAnt\t\t0x30\n#define\t\tbRFSW_RxDefaultAnt\t\t0x300\n#define\t\tbRFSW_RxOptionAnt\t\t0x3000\n#define\t\tbRFSI_3WireData\t\t0x1\n#define\t\tbRFSI_3WireClock\t\t0x2\n#define\t\tbRFSI_3WireLoad\t\t0x4\n#define\t\tbRFSI_3WireRW\t\t0x8\n#define\t\tbRFSI_3Wire\t\t\t0xf\n\n#define\t\tbRFSI_RFENV               \t\t0x10\t/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */\n\n#define\t\tbRFSI_TRSW                \t\t0x20\t/* Useless now */\n#define\t\tbRFSI_TRSWB\t\t0x40\n#define\t\tbRFSI_ANTSW\t\t0x100\n#define\t\tbRFSI_ANTSWB\t\t0x200\n#define\t\tbRFSI_PAPE\t\t\t0x400\n#define\t\tbRFSI_PAPE5G\t\t0x800\n#define\t\tbBandSelect\t\t\t0x1\n#define\t\tbHTSIG2_GI\t\t\t0x80\n#define\t\tbHTSIG2_Smoothing\t\t0x01\n#define\t\tbHTSIG2_Sounding\t\t0x02\n#define\t\tbHTSIG2_Aggreaton\t\t0x08\n#define\t\tbHTSIG2_STBC\t\t0x30\n#define\t\tbHTSIG2_AdvCoding\t\t0x40\n#define\t\tbHTSIG2_NumOfHTLTF\t0x300\n#define\t\tbHTSIG2_CRC8\t\t0x3fc\n#define\t\tbHTSIG1_MCS\t\t0x7f\n#define\t\tbHTSIG1_BandWidth\t\t0x80\n#define\t\tbHTSIG1_HTLength\t\t0xffff\n#define\t\tbLSIG_Rate\t\t\t0xf\n#define\t\tbLSIG_Reserved\t\t0x10\n#define\t\tbLSIG_Length\t\t0x1fffe\n#define\t\tbLSIG_Parity\t\t\t0x20\n#define\t\tbCCKRxPhase\t\t0x4\n\n#define\t\tbLSSIReadAddress          \t\t0x7f800000   /* T65 RF */\n\n#define\t\tbLSSIReadEdge             \t\t0x80000000   /* LSSI \"Read\" edge signal */\n\n#define\t\tbLSSIReadBackData         \t\t0xfffff\t\t/* T65 RF */\n\n#define\t\tbLSSIReadOKFlag           \t\t0x1000\t/* Useless now */\n#define\t\tbCCKSampleRate            \t\t0x8       /* 0: 44MHz, 1:88MHz      \t\t */\n#define\t\tbRegulator0Standby\t\t0x1\n#define\t\tbRegulatorPLLStandby\t\t0x2\n#define\t\tbRegulator1Standby\t\t0x4\n#define\t\tbPLLPowerUp\t\t0x8\n#define\t\tbDPLLPowerUp\t\t0x10\n#define\t\tbDA10PowerUp\t\t0x20\n#define\t\tbAD7PowerUp\t\t0x200\n#define\t\tbDA6PowerUp\t\t0x2000\n#define\t\tbXtalPowerUp\t\t0x4000\n#define\t\tb40MDClkPowerUP\t\t0x8000\n#define\t\tbDA6DebugMode\t\t0x20000\n#define\t\tbDA6Swing\t\t\t0x380000\n\n#define\t\tbADClkPhase               \t\t0x4000000\t/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */\n\n#define\t\tb80MClkDelay              \t\t0x18000000\t/* Useless */\n#define\t\tbAFEWatchDogEnable\t\t0x20000000\n\n#define\t\tbXtalCap01                \t\t\t0xc0000000\t/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */\n#define\t\tbXtalCap23\t\t\t0x3\n#define\t\tbXtalCap92x\t\t\t\t\t0x0f000000\n#define\t\tbXtalCap\t\t\t0x0f000000\n\n#define\t\tbIntDifClkEnable          \t\t0x400\t/* Useless */\n#define\t\tbExtSigClkEnable\t\t0x800\n#define\t\tbBandgapMbiasPowerUp\t0x10000\n#define\t\tbAD11SHGain\t\t0xc0000\n#define\t\tbAD11InputRange\t\t0x700000\n#define\t\tbAD11OPCurrent\t\t0x3800000\n#define\t\tbIPathLoopback\t\t0x4000000\n#define\t\tbQPathLoopback\t\t0x8000000\n#define\t\tbAFELoopback\t\t0x10000000\n#define\t\tbDA10Swing\t\t0x7e0\n#define\t\tbDA10Reverse\t\t0x800\n#define\t\tbDAClkSource\t\t0x1000\n#define\t\tbAD7InputRange\t\t0x6000\n#define\t\tbAD7Gain\t\t\t0x38000\n#define\t\tbAD7OutputCMMode\t\t0x40000\n#define\t\tbAD7InputCMMode\t\t0x380000\n#define\t\tbAD7Current\t\t\t0xc00000\n#define\t\tbRegulatorAdjust\t\t0x7000000\n#define\t\tbAD11PowerUpAtTx\t\t0x1\n#define\t\tbDA10PSAtTx\t\t0x10\n#define\t\tbAD11PowerUpAtRx\t\t0x100\n#define\t\tbDA10PSAtRx\t\t0x1000\n#define\t\tbCCKRxAGCFormat\t\t0x200\n#define\t\tbPSDFFTSamplepPoint\t\t0xc000\n#define\t\tbPSDAverageNum\t\t0x3000\n#define\t\tbIQPathControl\t\t0xc00\n#define\t\tbPSDFreq\t\t\t0x3ff\n#define\t\tbPSDAntennaPath\t\t0x30\n#define\t\tbPSDIQSwitch\t\t0x40\n#define\t\tbPSDRxTrigger\t\t0x400000\n#define\t\tbPSDTxTrigger\t\t0x80000000\n#define\t\tbPSDSineToneScale\t\t0x7f000000\n#define\t\tbPSDReport\t\t\t0xffff\n\n/* 3. Page9(0x900) */\n#define\t\tbOFDMTxSC                 \t\t0x30000000\t/* Useless */\n#define\t\tbCCKTxOn\t\t\t0x1\n#define\t\tbOFDMTxOn\t\t0x2\n#define\t\tbDebugPage                \t\t0xfff  /* reset debug page and also HWord, LWord */\n#define\t\tbDebugItem                \t\t0xff   /* reset debug page and LWord */\n#define\t\tbAntL\t\t\t0x10\n#define\t\tbAntNonHT\t\t\t\t0x100\n#define\t\tbAntHT1\t\t\t0x1000\n#define\t\tbAntHT2\t\t\t0x10000\n#define\t\tbAntHT1S1\t\t\t0x100000\n#define\t\tbAntNonHTS1\t\t0x1000000\n\n/* 4. PageA(0xA00) */\n#define\t\tbCCKBBMode\t\t\t\t0x3\t/* Useless */\n#define\t\tbCCKTxPowerSaving\t\t0x80\n#define\t\tbCCKRxPowerSaving\t\t0x40\n\n#define\t\tbCCKSideBand\t\t\t0x10\t/* Reg 0xa00 rCCK0_System 20/40 switch */\n\n#define\t\tbCCKScramble\t\t\t0x8\t/* Useless */\n#define\t\tbCCKAntDiversity\t\t0x8000\n#define\t\tbCCKCarrierRecovery\t\t0x4000\n#define\t\tbCCKTxRate\t\t\t\t0x3000\n#define\t\tbCCKDCCancel\t\t\t0x0800\n#define\t\tbCCKISICancel\t\t\t0x0400\n#define\t\tbCCKMatchFilter\t\t\t0x0200\n#define\t\tbCCKEqualizer\t\t\t0x0100\n#define\t\tbCCKPreambleDetect\t\t0x800000\n#define\t\tbCCKFastFalseCCA\t\t0x400000\n#define\t\tbCCKChEstStart\t\t\t0x300000\n#define\t\tbCCKCCACount\t\t\t0x080000\n#define\t\tbCCKcs_lim\t\t\t\t0x070000\n#define\t\tbCCKBistMode\t\t\t0x80000000\n#define\t\tbCCKCCAMask\t\t\t0x40000000\n#define\t\tbCCKTxDACPhase\t\t0x4\n#define\t\tbCCKRxADCPhase\t\t0x20000000   /* r_rx_clk */\n#define\t\tbCCKr_cp_mode0\t\t0x0100\n#define\t\tbCCKTxDCOffset\t\t\t0xf0\n#define\t\tbCCKRxDCOffset\t\t\t0xf\n#define\t\tbCCKCCAMode\t\t\t0xc000\n#define\t\tbCCKFalseCS_lim\t\t\t0x3f00\n#define\t\tbCCKCS_ratio\t\t\t0xc00000\n#define\t\tbCCKCorgBit_sel\t\t\t0x300000\n#define\t\tbCCKPD_lim\t\t\t\t0x0f0000\n#define\t\tbCCKNewCCA\t\t\t0x80000000\n#define\t\tbCCKRxHPofIG\t\t\t0x8000\n#define\t\tbCCKRxIG\t\t\t\t0x7f00\n#define\t\tbCCKLNAPolarity\t\t\t0x800000\n#define\t\tbCCKRx1stGain\t\t\t0x7f0000\n#define\t\tbCCKRFExtend\t\t\t0x20000000 /* CCK Rx Iinital gain polarity */\n#define\t\tbCCKRxAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKRxAGCSatCount\t\t0xe0\n#define\t\tbCCKRxRFSettle\t\t\t0x1f       /* AGCsamp_dly */\n#define\t\tbCCKFixedRxAGC\t\t\t0x8000\n/* #define bCCKRxAGCFormat\t\t0x4000 */   /* remove to HSSI register 0x824 */\n#define\t\tbCCKAntennaPolarity\t\t0x2000\n#define\t\tbCCKTxFilterType\t\t0x0c00\n#define\t\tbCCKRxAGCReportType\t0x0300\n#define\t\tbCCKRxDAGCEn\t\t\t0x80000000\n#define\t\tbCCKRxDAGCPeriod\t\t0x20000000\n#define\t\tbCCKRxDAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKTimingRecovery\t\t0x800000\n#define\t\tbCCKTxC0\t\t\t\t0x3f0000\n#define\t\tbCCKTxC1\t\t\t\t0x3f000000\n#define\t\tbCCKTxC2\t\t\t\t0x3f\n#define\t\tbCCKTxC3\t\t\t\t0x3f00\n#define\t\tbCCKTxC4\t\t\t\t0x3f0000\n#define\t\tbCCKTxC5\t\t\t\t0x3f000000\n#define\t\tbCCKTxC6\t\t\t\t0x3f\n#define\t\tbCCKTxC7\t\t\t\t0x3f00\n#define\t\tbCCKDebugPort\t\t\t0xff0000\n#define\t\tbCCKDACDebug\t\t\t0x0f000000\n#define\t\tbCCKFalseAlarmEnable\t0x8000\n#define\t\tbCCKFalseAlarmRead\t\t0x4000\n#define\t\tbCCKTRSSI\t\t\t\t0x7f\n#define\t\tbCCKRxAGCReport\t\t0xfe\n#define\t\tbCCKRxReport_AntSel\t0x80000000\n#define\t\tbCCKRxReport_MFOff\t\t0x40000000\n#define\t\tbCCKRxRxReport_SQLoss\t0x20000000\n#define\t\tbCCKRxReport_Pktloss\t0x10000000\n#define\t\tbCCKRxReport_Lockedbit\t0x08000000\n#define\t\tbCCKRxReport_RateError\t0x04000000\n#define\t\tbCCKRxReport_RxRate\t0x03000000\n#define\t\tbCCKRxFACounterLower\t0xff\n#define\t\tbCCKRxFACounterUpper\t0xff000000\n#define\t\tbCCKRxHPAGCStart\t\t0xe000\n#define\t\tbCCKRxHPAGCFinal\t\t0x1c00\n#define\t\tbCCKRxFalseAlarmEnable\t0x8000\n#define\t\tbCCKFACounterFreeze\t0x4000\n#define\t\tbCCKTxPathSel\t\t\t0x10000000\n#define\t\tbCCKDefaultRxPath\t\t0xc000000\n#define\t\tbCCKOptionRxPath\t\t0x3000000\n\n/* 5. PageC(0xC00) */\n#define\t\tbNumOfSTF\t\t\t\t0x3\t/* Useless */\n#define\t\tbShift_L\t\t\t\t\t0xc0\n#define\t\tbGI_TH\t\t\t\t\t0xc\n#define\t\tbRxPathA\t\t\t\t0x1\n#define\t\tbRxPathB\t\t\t\t0x2\n#define\t\tbRxPathC\t\t\t\t0x4\n#define\t\tbRxPathD\t\t\t\t0x8\n#define\t\tbTxPathA\t\t\t\t0x1\n#define\t\tbTxPathB\t\t\t\t0x2\n#define\t\tbTxPathC\t\t\t\t0x4\n#define\t\tbTxPathD\t\t\t\t0x8\n#define\t\tbTRSSIFreq\t\t\t\t0x200\n#define\t\tbADCBackoff\t\t\t\t0x3000\n#define\t\tbDFIRBackoff\t\t\t0xc000\n#define\t\tbTRSSILatchPhase\t\t0x10000\n#define\t\tbRxIDCOffset\t\t\t0xff\n#define\t\tbRxQDCOffset\t\t\t0xff00\n#define\t\tbRxDFIRMode\t\t\t0x1800000\n#define\t\tbRxDCNFType\t\t\t0xe000000\n#define\t\tbRXIQImb_A\t\t\t\t0x3ff\n#define\t\tbRXIQImb_B\t\t\t\t0xfc00\n#define\t\tbRXIQImb_C\t\t\t\t0x3f0000\n#define\t\tbRXIQImb_D\t\t\t\t0xffc00000\n#define\t\tbDC_dc_Notch\t\t\t0x60000\n#define\t\tbRxNBINotch\t\t\t0x1f000000\n#define\t\tbPD_TH\t\t\t\t\t0xf\n#define\t\tbPD_TH_Opt2\t\t\t0xc000\n#define\t\tbPWED_TH\t\t\t\t0x700\n#define\t\tbIfMF_Win_L\t\t\t0x800\n#define\t\tbPD_Option\t\t\t\t0x1000\n#define\t\tbMF_Win_L\t\t\t\t0xe000\n#define\t\tbBW_Search_L\t\t\t0x30000\n#define\t\tbwin_enh_L\t\t\t\t0xc0000\n#define\t\tbBW_TH\t\t\t\t\t0x700000\n#define\t\tbED_TH2\t\t\t\t0x3800000\n#define\t\tbBW_option\t\t\t\t0x4000000\n#define\t\tbRatio_TH\t\t\t\t0x18000000\n#define\t\tbWindow_L\t\t\t\t0xe0000000\n#define\t\tbSBD_Option\t\t\t\t0x1\n#define\t\tbFrame_TH\t\t\t\t0x1c\n#define\t\tbFS_Option\t\t\t\t0x60\n#define\t\tbDC_Slope_check\t\t0x80\n#define\t\tbFGuard_Counter_DC_L\t0xe00\n#define\t\tbFrame_Weight_Short\t0x7000\n#define\t\tbSub_Tune\t\t\t\t0xe00000\n#define\t\tbFrame_DC_Length\t\t0xe000000\n#define\t\tbSBD_start_offset\t\t0x30000000\n#define\t\tbFrame_TH_2\t\t\t0x7\n#define\t\tbFrame_GI2_TH\t\t\t0x38\n#define\t\tbGI2_Sync_en\t\t\t0x40\n#define\t\tbSarch_Short_Early\t\t0x300\n#define\t\tbSarch_Short_Late\t\t0xc00\n#define\t\tbSarch_GI2_Late\t\t0x70000\n#define\t\tbCFOAntSum\t\t\t\t0x1\n#define\t\tbCFOAcc\t\t\t\t0x2\n#define\t\tbCFOStartOffset\t\t\t0xc\n#define\t\tbCFOLookBack\t\t\t0x70\n#define\t\tbCFOSumWeight\t\t\t0x80\n#define\t\tbDAGCEnable\t\t\t0x10000\n#define\t\tbTXIQImb_A\t\t\t\t0x3ff\n#define\t\tbTXIQImb_B\t\t\t\t0xfc00\n#define\t\tbTXIQImb_C\t\t\t\t0x3f0000\n#define\t\tbTXIQImb_D\t\t\t\t0xffc00000\n#define\t\tbTxIDCOffset\t\t\t0xff\n#define\t\tbTxQDCOffset\t\t\t0xff00\n#define\t\tbTxDFIRMode\t\t\t0x10000\n#define\t\tbTxPesudoNoiseOn\t\t0x4000000\n#define\t\tbTxPesudoNoise_A\t\t0xff\n#define\t\tbTxPesudoNoise_B\t\t0xff00\n#define\t\tbTxPesudoNoise_C\t\t0xff0000\n#define\t\tbTxPesudoNoise_D\t\t0xff000000\n#define\t\tbCCADropOption\t\t\t0x20000\n#define\t\tbCCADropThres\t\t\t0xfff00000\n#define\t\tbEDCCA_H\t\t\t\t0xf\n#define\t\tbEDCCA_L\t\t\t\t0xf0\n#define\t\tbLambda_ED\t\t\t0x300\n#define\t\tbRxInitialGain\t\t\t0x7f\n#define\t\tbRxAntDivEn\t\t\t\t0x80\n#define\t\tbRxAGCAddressForLNA\t0x7f00\n#define\t\tbRxHighPowerFlow\t\t0x8000\n#define\t\tbRxAGCFreezeThres\t\t0xc0000\n#define\t\tbRxFreezeStep_AGC1\t0x300000\n#define\t\tbRxFreezeStep_AGC2\t0xc00000\n#define\t\tbRxFreezeStep_AGC3\t0x3000000\n#define\t\tbRxFreezeStep_AGC0\t0xc000000\n#define\t\tbRxRssi_Cmp_En\t\t\t0x10000000\n#define\t\tbRxQuickAGCEn\t\t\t0x20000000\n#define\t\tbRxAGCFreezeThresMode\t0x40000000\n#define\t\tbRxOverFlowCheckType\t0x80000000\n#define\t\tbRxAGCShift\t\t\t\t0x7f\n#define\t\tbTRSW_Tri_Only\t\t\t0x80\n#define\t\tbPowerThres\t\t\t0x300\n#define\t\tbRxAGCEn\t\t\t\t0x1\n#define\t\tbRxAGCTogetherEn\t\t0x2\n#define\t\tbRxAGCMin\t\t\t\t0x4\n#define\t\tbRxHP_Ini\t\t\t\t0x7\n#define\t\tbRxHP_TRLNA\t\t\t0x70\n#define\t\tbRxHP_RSSI\t\t\t\t0x700\n#define\t\tbRxHP_BBP1\t\t\t\t0x7000\n#define\t\tbRxHP_BBP2\t\t\t\t0x70000\n#define\t\tbRxHP_BBP3\t\t\t\t0x700000\n#define\t\tbRSSI_H\t\t\t\t\t0x7f0000     /* the threshold for high power */\n#define\t\tbRSSI_Gen\t\t\t\t0x7f000000   /* the threshold for ant diversity */\n#define\t\tbRxSettle_TRSW\t\t\t0x7\n#define\t\tbRxSettle_LNA\t\t\t0x38\n#define\t\tbRxSettle_RSSI\t\t\t0x1c0\n#define\t\tbRxSettle_BBP\t\t\t0xe00\n#define\t\tbRxSettle_RxHP\t\t\t0x7000\n#define\t\tbRxSettle_AntSW_RSSI\t0x38000\n#define\t\tbRxSettle_AntSW\t\t0xc0000\n#define\t\tbRxProcessTime_DAGC\t0x300000\n#define\t\tbRxSettle_HSSI\t\t\t0x400000\n#define\t\tbRxProcessTime_BBPPW\t0x800000\n#define\t\tbRxAntennaPowerShift\t0x3000000\n#define\t\tbRSSITableSelect\t\t0xc000000\n#define\t\tbRxHP_Final\t\t\t\t0x7000000\n#define\t\tbRxHTSettle_BBP\t\t\t0x7\n#define\t\tbRxHTSettle_HSSI\t\t0x8\n#define\t\tbRxHTSettle_RxHP\t\t0x70\n#define\t\tbRxHTSettle_BBPPW\t\t0x80\n#define\t\tbRxHTSettle_Idle\t\t0x300\n#define\t\tbRxHTSettle_Reserved\t0x1c00\n#define\t\tbRxHTRxHPEn\t\t\t0x8000\n#define\t\tbRxHTAGCFreezeThres\t0x30000\n#define\t\tbRxHTAGCTogetherEn\t0x40000\n#define\t\tbRxHTAGCMin\t\t\t0x80000\n#define\t\tbRxHTAGCEn\t\t\t\t0x100000\n#define\t\tbRxHTDAGCEn\t\t\t0x200000\n#define\t\tbRxHTRxHP_BBP\t\t\t0x1c00000\n#define\t\tbRxHTRxHP_Final\t\t0xe0000000\n#define\t\tbRxPWRatioTH\t\t\t0x3\n#define\t\tbRxPWRatioEn\t\t\t0x4\n#define\t\tbRxMFHold\t\t\t\t0x3800\n#define\t\tbRxPD_Delay_TH1\t\t0x38\n#define\t\tbRxPD_Delay_TH2\t\t0x1c0\n#define\t\tbRxPD_DC_COUNT_MAX\t0x600\n/* #define bRxMF_Hold               0x3800 */\n#define\t\tbRxPD_Delay_TH\t\t\t0x8000\n#define\t\tbRxProcess_Delay\t\t0xf0000\n#define\t\tbRxSearchrange_GI2_Early\t0x700000\n#define\t\tbRxFrame_Guard_Counter_L\t0x3800000\n#define\t\tbRxSGI_Guard_L\t\t\t0xc000000\n#define\t\tbRxSGI_Search_L\t\t0x30000000\n#define\t\tbRxSGI_TH\t\t\t\t0xc0000000\n#define\t\tbDFSCnt0\t\t\t\t0xff\n#define\t\tbDFSCnt1\t\t\t\t0xff00\n#define\t\tbDFSFlag\t\t\t\t0xf0000\n#define\t\tbMFWeightSum\t\t\t0x300000\n#define\t\tbMinIdxTH\t\t\t\t0x7f000000\n#define\t\tbDAFormat\t\t\t\t0x40000\n#define\t\tbTxChEmuEnable\t\t0x01000000\n#define\t\tbTRSWIsolation_A\t\t0x7f\n#define\t\tbTRSWIsolation_B\t\t0x7f00\n#define\t\tbTRSWIsolation_C\t\t0x7f0000\n#define\t\tbTRSWIsolation_D\t\t0x7f000000\n#define\t\tbExtLNAGain\t\t\t\t0x7c00\n\n/* 6. PageE(0xE00) */\n#define\t\tbSTBCEn\t\t\t\t0x4\t/* Useless */\n#define\t\tbAntennaMapping\t\t0x10\n#define\t\tbNss\t\t\t\t\t0x20\n#define\t\tbCFOAntSumD\t\t\t0x200\n#define\t\tbPHYCounterReset\t\t0x8000000\n#define\t\tbCFOReportGet\t\t\t0x4000000\n#define\t\tbOFDMContinueTx\t\t0x10000000\n#define\t\tbOFDMSingleCarrier\t\t0x20000000\n#define\t\tbOFDMSingleTone\t\t0x40000000\n/* #define bRxPath1                 0x01 */\n/* #define bRxPath2                 0x02 */\n/* #define bRxPath3                 0x04 */\n/* #define bRxPath4                 0x08 */\n/* #define bTxPath1                 0x10 */\n/* #define bTxPath2                 0x20 */\n#define\t\tbHTDetect\t\t\t0x100\n#define\t\tbCFOEn\t\t\t\t0x10000\n#define\t\tbCFOValue\t\t\t0xfff00000\n#define\t\tbSigTone_Re\t\t0x3f\n#define\t\tbSigTone_Im\t\t0x7f00\n#define\t\tbCounter_CCA\t\t0xffff\n#define\t\tbCounter_ParityFail\t0xffff0000\n#define\t\tbCounter_RateIllegal\t\t0xffff\n#define\t\tbCounter_CRC8Fail\t0xffff0000\n#define\t\tbCounter_MCSNoSupport\t0xffff\n#define\t\tbCounter_FastSync\t0xffff\n#define\t\tbShortCFO\t\t\t0xfff\n#define\t\tbShortCFOTLength\t12   /* total */\n#define\t\tbShortCFOFLength\t11   /* fraction */\n#define\t\tbLongCFO\t\t\t0x7ff\n#define\t\tbLongCFOTLength\t11\n#define\t\tbLongCFOFLength\t11\n#define\t\tbTailCFO\t\t\t0x1fff\n#define\t\tbTailCFOTLength\t\t13\n#define\t\tbTailCFOFLength\t\t12\n#define\t\tbmax_en_pwdB\t\t0xffff\n#define\t\tbCC_power_dB\t\t0xffff0000\n#define\t\tbnoise_pwdB\t\t0xffff\n#define\t\tbPowerMeasTLength\t10\n#define\t\tbPowerMeasFLength\t3\n#define\t\tbRx_HT_BW\t\t\t0x1\n#define\t\tbRxSC\t\t\t\t0x6\n#define\t\tbRx_HT\t\t\t\t0x8\n#define\t\tbNB_intf_det_on\t\t0x1\n#define\t\tbIntf_win_len_cfg\t0x30\n#define\t\tbNB_Intf_TH_cfg\t\t0x1c0\n#define\t\tbRFGain\t\t\t\t0x3f\n#define\t\tbTableSel\t\t\t0x40\n#define\t\tbTRSW\t\t\t\t0x80\n#define\t\tbRxSNR_A\t\t\t0xff\n#define\t\tbRxSNR_B\t\t\t0xff00\n#define\t\tbRxSNR_C\t\t\t0xff0000\n#define\t\tbRxSNR_D\t\t\t0xff000000\n#define\t\tbSNREVMTLength\t\t8\n#define\t\tbSNREVMFLength\t\t1\n#define\t\tbCSI1st\t\t\t\t0xff\n#define\t\tbCSI2nd\t\t\t\t0xff00\n#define\t\tbRxEVM1st\t\t\t0xff0000\n#define\t\tbRxEVM2nd\t\t\t0xff000000\n#define\t\tbSIGEVM\t\t\t0xff\n#define\t\tbPWDB\t\t\t\t0xff00\n#define\t\tbSGIEN\t\t\t\t0x10000\n\n#define\t\tbSFactorQAM1\t\t0xf\t/* Useless */\n#define\t\tbSFactorQAM2\t\t0xf0\n#define\t\tbSFactorQAM3\t\t0xf00\n#define\t\tbSFactorQAM4\t\t0xf000\n#define\t\tbSFactorQAM5\t\t0xf0000\n#define\t\tbSFactorQAM6\t\t0xf0000\n#define\t\tbSFactorQAM7\t\t0xf00000\n#define\t\tbSFactorQAM8\t\t0xf000000\n#define\t\tbSFactorQAM9\t\t0xf0000000\n#define\t\tbCSIScheme\t\t\t0x100000\n\n#define\t\tbNoiseLvlTopSet\t\t0x3\t/* Useless */\n#define\t\tbChSmooth\t\t\t0x4\n#define\t\tbChSmoothCfg1\t\t0x38\n#define\t\tbChSmoothCfg2\t\t0x1c0\n#define\t\tbChSmoothCfg3\t\t0xe00\n#define\t\tbChSmoothCfg4\t\t0x7000\n#define\t\tbMRCMode\t\t\t0x800000\n#define\t\tbTHEVMCfg\t\t\t0x7000000\n\n#define\t\tbLoopFitType\t\t0x1\t/* Useless */\n#define\t\tbUpdCFO\t\t\t0x40\n#define\t\tbUpdCFOOffData\t\t0x80\n#define\t\tbAdvUpdCFO\t\t\t0x100\n#define\t\tbAdvTimeCtrl\t\t0x800\n#define\t\tbUpdClko\t\t\t0x1000\n#define\t\tbFC\t\t\t\t\t0x6000\n#define\t\tbTrackingMode\t\t0x8000\n#define\t\tbPhCmpEnable\t\t0x10000\n#define\t\tbUpdClkoLTF\t\t0x20000\n#define\t\tbComChCFO\t\t\t0x40000\n#define\t\tbCSIEstiMode\t\t0x80000\n#define\t\tbAdvUpdEqz\t\t\t0x100000\n#define\t\tbUChCfg\t\t\t\t0x7000000\n#define\t\tbUpdEqz\t\t\t0x8000000\n\n/* Rx Pseduo noise */\n#define\t\tbRxPesudoNoiseOn\t\t0x20000000\t/* Useless */\n#define\t\tbRxPesudoNoise_A\t\t0xff\n#define\t\tbRxPesudoNoise_B\t\t0xff00\n#define\t\tbRxPesudoNoise_C\t\t0xff0000\n#define\t\tbRxPesudoNoise_D\t\t0xff000000\n#define\t\tbPesudoNoiseState_A\t0xffff\n#define\t\tbPesudoNoiseState_B\t0xffff0000\n#define\t\tbPesudoNoiseState_C\t0xffff\n#define\t\tbPesudoNoiseState_D\t0xffff0000\n\n/* 7. RF Register\n * Zebra1 */\n#define\t\tbZebra1_HSSIEnable\t\t0x8\t\t/* Useless */\n#define\t\tbZebra1_TRxControl\t\t0xc00\n#define\t\tbZebra1_TRxGainSetting\t0x07f\n#define\t\tbZebra1_RxCorner\t\t0xc00\n#define\t\tbZebra1_TxChargePump\t0x38\n#define\t\tbZebra1_RxChargePump\t0x7\n#define\t\tbZebra1_ChannelNum\t0xf80\n#define\t\tbZebra1_TxLPFBW\t\t0x400\n#define\t\tbZebra1_RxLPFBW\t\t0x600\n\n/* Zebra4 */\n#define\t\tbRTL8256RegModeCtrl1\t0x100\t/* Useless */\n#define\t\tbRTL8256RegModeCtrl0\t0x40\n#define\t\tbRTL8256_TxLPFBW\t\t0x18\n#define\t\tbRTL8256_RxLPFBW\t\t0x600\n\n/* RTL8258 */\n#define\t\tbRTL8258_TxLPFBW\t\t0xc\t/* Useless */\n#define\t\tbRTL8258_RxLPFBW\t\t0xc00\n#define\t\tbRTL8258_RSSILPFBW\t0xc0\n\n\n/*\n * Other Definition\n *   */\n\n/* byte endable for sb_write */\n#define\t\tbByte0\t\t\t\t0x1\t/* Useless */\n#define\t\tbByte1\t\t\t\t0x2\n#define\t\tbByte2\t\t\t\t0x4\n#define\t\tbByte3\t\t\t\t0x8\n#define\t\tbWord0\t\t\t\t0x3\n#define\t\tbWord1\t\t\t\t0xc\n#define\t\tbDWord\t\t\t\t0xf\n\n/* for PutRegsetting & GetRegSetting BitMask */\n#define\t\tbMaskByte0\t\t\t0xff\t/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */\n#define\t\tbMaskByte1\t\t\t0xff00\n#define\t\tbMaskByte2\t\t\t0xff0000\n#define\t\tbMaskByte3\t\t\t0xff000000\n#define\t\tbMaskHWord\t\t0xffff0000\n#define\t\tbMaskLWord\t\t\t0x0000ffff\n#define\t\tbMaskDWord\t\t0xffffffff\n#define\t\tbMaskH3Bytes\t\t0xffffff00\n#define\t\tbMask12Bits\t\t\t0xfff\n#define\t\tbMaskH4Bits\t\t\t0xf0000000\n#define\t\tbMaskOFDM_D\t\t0xffc00000\n#define\t\tbMaskCCK\t\t\t0x3f3f3f3f\n\n\n#define\t\tbEnable\t\t\t0x1\t/* Useless */\n#define\t\tbDisable\t\t0x0\n\n#define\t\tLeftAntenna\t\t0x0\t/* Useless */\n#define\t\tRightAntenna\t0x1\n\n#define\t\ttCheckTxStatus\t\t500   /* 500ms */ /* Useless */\n#define\t\ttUpdateRxCounter\t100   /* 100ms */\n\n#define\t\trateCCK\t\t0\t/* Useless */\n#define\t\trateOFDM\t1\n#define\t\trateHT\t\t2\n\n/* define Register-End */\n#define\t\tbPMAC_End\t\t\t0x1ff\t/* Useless */\n#define\t\tbFPGAPHY0_End\t\t0x8ff\n#define\t\tbFPGAPHY1_End\t\t0x9ff\n#define\t\tbCCKPHY0_End\t\t0xaff\n#define\t\tbOFDMPHY0_End\t\t0xcff\n#define\t\tbOFDMPHY1_End\t\t0xdff\n\n/* define max debug item in each debug page\n * #define bMaxItem_FPGA_PHY0        0x9\n * #define bMaxItem_FPGA_PHY1        0x3\n * #define bMaxItem_PHY_11B          0x16\n * #define bMaxItem_OFDM_PHY0        0x29\n * #define bMaxItem_OFDM_PHY1        0x0 */\n\n#define\t\tbPMACControl\t\t0x0\t\t/* Useless */\n#define\t\tbWMACControl\t\t0x1\n#define\t\tbWNICControl\t\t0x2\n\n#define\t\tPathA\t\t\t0x0\t/* Useless */\n#define\t\tPathB\t\t\t0x1\n#define\t\tPathC\t\t\t0x2\n#define\t\tPathD\t\t\t0x3\n\n#endif\n"
  },
  {
    "path": "include/Hal8703BPwrSeq.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef REALTEK_POWER_SEQUENCE_8703B\n#define REALTEK_POWER_SEQUENCE_8703B\n\n#include \"HalPwrSeqCmd.h\"\n\n/*\n\tCheck document WM-20140402-JackieLau-RTL8703B_Power_Architecture v09.vsd\n\tThere are 6 HW Power States:\n\t0: POFF--Power Off\n\t1: PDN--Power Down\n\t2: CARDEMU--Card Emulation\n\t3: ACT--Active Mode\n\t4: LPS--Low Power State\n\t5: SUS--Suspend\n\n\tThe transision from different states are defined below\n\tTRANS_CARDEMU_TO_ACT\n\tTRANS_ACT_TO_CARDEMU\n\tTRANS_CARDEMU_TO_SUS\n\tTRANS_SUS_TO_CARDEMU\n\tTRANS_CARDEMU_TO_PDN\n\tTRANS_ACT_TO_LPS\n\tTRANS_LPS_TO_ACT\n\n\tTRANS_END\n*/\n#define\tRTL8703B_TRANS_CARDEMU_TO_ACT_STEPS\t23\n#define\tRTL8703B_TRANS_ACT_TO_CARDEMU_STEPS\t15\n#define\tRTL8703B_TRANS_CARDEMU_TO_SUS_STEPS\t15\n#define\tRTL8703B_TRANS_SUS_TO_CARDEMU_STEPS\t15\n#define\tRTL8703B_TRANS_CARDEMU_TO_PDN_STEPS\t15\n#define\tRTL8703B_TRANS_PDN_TO_CARDEMU_STEPS\t15\n#define\tRTL8703B_TRANS_ACT_TO_LPS_STEPS\t\t15\n#define\tRTL8703B_TRANS_LPS_TO_ACT_STEPS\t\t15\n#define\tRTL8703B_TRANS_END_STEPS\t\t1\n\n\n#define RTL8703B_TRANS_CARDEMU_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \\\n\t{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/\t\\\n\t{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \\\n\t{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/\t\\\n\t{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */\t\\\n\t{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 , BIT3},/* enabled usb resume */\t\\\n\t{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 , 0},/* disable usb resume */\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/\t\\\n\t{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/\t\\\n\t{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/\t\\\n\t{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\\\n\t{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\\\n\t{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\\\n\t{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\\\n\t{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\\\n\t{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\\\n\t{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\\\n\n\n#define RTL8703B_TRANS_ACT_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/\t\\\n\t{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/\t\\\n\t{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\\\n\t{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \\\n\t{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\\\n\n\n#define RTL8703B_TRANS_CARDEMU_TO_SUS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/\n\n#define RTL8703B_TRANS_SUS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\n\n#define RTL8703B_TRANS_CARDEMU_TO_CARDDIS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/\t\\\n\t{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/\n\n#define RTL8703B_TRANS_CARDDIS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\\\n\t{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/\n\n\n#define RTL8703B_TRANS_CARDEMU_TO_PDN\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/\n\n#define RTL8703B_TRANS_PDN_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/\n\n#define RTL8703B_TRANS_ACT_TO_LPS\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/\t\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/\t\\\n\t{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/\t\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/\t\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\t\\\n\t{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/\t\\\n\t{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/\t\\\n\n\n#define RTL8703B_TRANS_LPS_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\\\n\t{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\\\n\t{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.\t0x08[4] = 0\t\t switch TSF to 40M*/\\\n\t{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\\\n\t{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.\t0x29[7:6] = 2b'00\t enable BB clock*/\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.\t0x101[1] = 1*/\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.\t0x100[7:0] = 0xFF\t enable WMAC TRX*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.\t0x02[1:0] = 2b'11\t enable BB macro*/\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.\t0x522 = 0*/\n\n#define RTL8703B_TRANS_END\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},\n\n\n\textern WLAN_PWR_CFG rtl8703B_power_on_flow[RTL8703B_TRANS_CARDEMU_TO_ACT_STEPS + RTL8703B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8703B_radio_off_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8703B_card_disable_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8703B_card_enable_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8703B_suspend_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8703B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8703B_resume_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8703B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8703B_hwpdn_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8703B_enter_lps_flow[RTL8703B_TRANS_ACT_TO_LPS_STEPS + RTL8703B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8703B_leave_lps_flow[RTL8703B_TRANS_LPS_TO_ACT_STEPS + RTL8703B_TRANS_END_STEPS];\n\n#endif\n"
  },
  {
    "path": "include/Hal8710BPhyCfg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8710BPHYCFG_H__\n#define __INC_HAL8710BPHYCFG_H__\n\n/*--------------------------Define Parameters-------------------------------*/\n#define LOOP_LIMIT\t\t\t\t5\n#define MAX_STALL_TIME\t\t\t50\t\t/* us */\n#define AntennaDiversityValue\t0x80\t/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */\n#define MAX_TXPWR_IDX_NMODE_92S\t63\n#define Reset_Cnt_Limit\t\t\t3\n\n#ifdef CONFIG_PCI_HCI\n\t#define MAX_AGGR_NUM\t0x0B\n#else\n\t#define MAX_AGGR_NUM\t0x07\n#endif /* CONFIG_PCI_HCI */\n\n\n/*--------------------------Define Parameters End-------------------------------*/\n\n\n/*------------------------------Define structure----------------------------*/\n\n/*------------------------------Define structure End----------------------------*/\n\n/*--------------------------Exported Function prototype---------------------*/\nu32\nPHY_QueryBBReg_8710B(\n\t\tPADAPTER\tAdapter,\n\t\tu32\t\tRegAddr,\n\t\tu32\t\tBitMask\n);\n\nvoid\nPHY_SetBBReg_8710B(\n\t\tPADAPTER\tAdapter,\n\t\tu32\t\tRegAddr,\n\t\tu32\t\tBitMask,\n\t\tu32\t\tData\n);\n\nu32\nPHY_QueryRFReg_8710B(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tRegAddr,\n\t\tu32\t\t\t\tBitMask\n);\n\nvoid\nPHY_SetRFReg_8710B(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tRegAddr,\n\t\tu32\t\t\t\tBitMask,\n\t\tu32\t\t\t\tData\n);\n\n/* MAC/BB/RF HAL config */\nint PHY_BBConfig8710B(PADAPTER\tAdapter);\n\nint PHY_RFConfig8710B(PADAPTER\tAdapter);\n\ns32 PHY_MACConfig8710B(PADAPTER padapter);\n\nint\nPHY_ConfigRFWithParaFile_8710B(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu8\t\t\t\t*pFileName,\n\tenum rf_path\t\t\t\teRFPath\n);\n\nvoid\nPHY_SetTxPowerIndex_8710B(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu32\t\t\t\t\tPowerIndex,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate\n);\n\nu8\nPHY_GetTxPowerIndex_8710B(\n\t\tPADAPTER\t\t\tpAdapter,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate,\n\t\tu8\t\t\t\t\tBandWidth,\n\t\tu8\t\t\t\t\tChannel,\n\tstruct txpwr_idx_comp *tic\n);\n\nvoid\nPHY_SetTxPowerLevel8710B(\n\t\tPADAPTER\t\tAdapter,\n\t\tu8\t\t\tchannel\n);\n\nvoid\nPHY_SetSwChnlBWMode8710B(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu8\t\t\t\t\tchannel,\n\t\tenum channel_width\tBandwidth,\n\t\tu8\t\t\t\t\tOffset40,\n\t\tu8\t\t\t\t\tOffset80\n);\n\n/*--------------------------Exported Function prototype End---------------------*/\n\n#endif\n"
  },
  {
    "path": "include/Hal8710BPhyReg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8710BPHYREG_H__\n#define __INC_HAL8710BPHYREG_H__\n\n#define\t\trSYM_WLBT_PAPE_SEL\t\t0x64\n/*\n * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00\n * 3. RF register 0x00-2E\n * 4. Bit Mask for BB/RF register\n * 5. Other definition for BB/RF R/W\n *   */\n\n\n/*\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 1. Page1(0x100)\n *   */\n#define\t\trPMAC_Reset\t\t\t\t\t0x100\n#define\t\trPMAC_TxStart\t\t\t\t\t0x104\n#define\t\trPMAC_TxLegacySIG\t\t\t\t0x108\n#define\t\trPMAC_TxHTSIG1\t\t\t\t0x10c\n#define\t\trPMAC_TxHTSIG2\t\t\t\t0x110\n#define\t\trPMAC_PHYDebug\t\t\t\t0x114\n#define\t\trPMAC_TxPacketNum\t\t\t\t0x118\n#define\t\trPMAC_TxIdle\t\t\t\t\t0x11c\n#define\t\trPMAC_TxMACHeader0\t\t\t0x120\n#define\t\trPMAC_TxMACHeader1\t\t\t0x124\n#define\t\trPMAC_TxMACHeader2\t\t\t0x128\n#define\t\trPMAC_TxMACHeader3\t\t\t0x12c\n#define\t\trPMAC_TxMACHeader4\t\t\t0x130\n#define\t\trPMAC_TxMACHeader5\t\t\t0x134\n#define\t\trPMAC_TxDataType\t\t\t\t0x138\n#define\t\trPMAC_TxRandomSeed\t\t\t0x13c\n#define\t\trPMAC_CCKPLCPPreamble\t\t\t0x140\n#define\t\trPMAC_CCKPLCPHeader\t\t\t0x144\n#define\t\trPMAC_CCKCRC16\t\t\t\t0x148\n#define\t\trPMAC_OFDMRxCRC32OK\t\t\t0x170\n#define\t\trPMAC_OFDMRxCRC32Er\t\t\t0x174\n#define\t\trPMAC_OFDMRxParityEr\t\t\t0x178\n#define\t\trPMAC_OFDMRxCRC8Er\t\t\t0x17c\n#define\t\trPMAC_CCKCRxRC16Er\t\t\t0x180\n#define\t\trPMAC_CCKCRxRC32Er\t\t\t0x184\n#define\t\trPMAC_CCKCRxRC32OK\t\t\t0x188\n#define\t\trPMAC_TxStatus\t\t\t\t\t0x18c\n\n/*\n * 2. Page2(0x200)\n *\n * The following two definition are only used for USB interface. */\n#define\t\tRF_BB_CMD_ADDR\t\t\t\t0x02c0\t/* RF/BB read/write command address. */\n#define\t\tRF_BB_CMD_DATA\t\t\t\t0x02c4\t/* RF/BB read/write command data. */\n\n/*\n * 3. Page8(0x800)\n *   */\n#define\t\trFPGA0_RFMOD\t\t\t\t0x800\t/* RF mode & CCK TxSC // RF BW Setting?? */\n\n#define\t\trFPGA0_TxInfo\t\t\t\t0x804\t/* Status report?? */\n#define\t\trFPGA0_PSDFunction\t\t\t0x808\n\n#define\t\trFPGA0_TxGainStage\t\t\t0x80c\t/* Set TX PWR init gain? */\n\n#define\t\trFPGA0_RFTiming1\t\t\t0x810\t/* Useless now */\n#define\t\trFPGA0_RFTiming2\t\t\t0x814\n\n#define\t\trFPGA0_XA_HSSIParameter1\t\t0x820\t/* RF 3 wire register */\n#define\t\trFPGA0_XA_HSSIParameter2\t\t0x824\n#define\t\trFPGA0_XB_HSSIParameter1\t\t0x828\n#define\t\trFPGA0_XB_HSSIParameter2\t\t0x82c\n#define\t\trTxAGC_B_Rate18_06\t\t\t\t0x830\n#define\t\trTxAGC_B_Rate54_24\t\t\t\t0x834\n#define\t\trTxAGC_B_CCK1_55_Mcs32\t\t0x838\n#define\t\trTxAGC_B_Mcs03_Mcs00\t\t\t0x83c\n\n#define\t\trTxAGC_B_Mcs07_Mcs04\t\t\t0x848\n#define\t\trTxAGC_B_Mcs11_Mcs08\t\t\t0x84c\n\n#define\t\trFPGA0_XA_LSSIParameter\t\t0x840\n#define\t\trFPGA0_XB_LSSIParameter\t\t0x844\n\n#define\t\trFPGA0_RFWakeUpParameter\t\t0x850\t/* Useless now */\n#define\t\trFPGA0_RFSleepUpParameter\t\t0x854\n\n#define\t\trFPGA0_XAB_SwitchControl\t\t0x858\t/* RF Channel switch */\n#define\t\trFPGA0_XCD_SwitchControl\t\t0x85c\n\n#define\t\trFPGA0_XA_RFInterfaceOE\t\t0x860\t/* RF Channel switch */\n#define\t\trFPGA0_XB_RFInterfaceOE\t\t0x864\n\n#define\t\trTxAGC_B_Mcs15_Mcs12\t\t\t0x868\n#define\t\trTxAGC_B_CCK11_A_CCK2_11\t\t0x86c\n\n#define\t\trFPGA0_XAB_RFInterfaceSW\t\t0x870\t/* RF Interface Software Control */\n#define\t\trFPGA0_XCD_RFInterfaceSW\t\t0x874\n\n#define\t\trFPGA0_XAB_RFParameter\t\t0x878\t/* RF Parameter */\n#define\t\trFPGA0_XCD_RFParameter\t\t0x87c\n\n#define\t\trFPGA0_AnalogParameter1\t\t0x880\t/* Crystal cap setting RF-R/W protection for parameter4?? */\n#define\t\trFPGA0_AnalogParameter2\t\t0x884\n#define\t\trFPGA0_AnalogParameter3\t\t0x888\t/* Useless now */\n#define\t\trFPGA0_AnalogParameter4\t\t0x88c\n\n#define\t\trFPGA0_XA_LSSIReadBack\t\t0x8a0\t/* Tranceiver LSSI Readback */\n#define\t\trFPGA0_XB_LSSIReadBack\t\t0x8a4\n#define\t\trFPGA0_XC_LSSIReadBack\t\t0x8a8\n#define\t\trFPGA0_XD_LSSIReadBack\t\t0x8ac\n\n#define\t\trFPGA0_PSDReport\t\t\t\t0x8b4\t/* Useless now */\n#define\t\tTransceiverA_HSPI_Readback\t0x8b8\t/* Transceiver A HSPI Readback */\n#define\t\tTransceiverB_HSPI_Readback\t0x8bc\t/* Transceiver B HSPI Readback */\n#define\t\trFPGA0_XAB_RFInterfaceRB\t\t0x8e0\t/* Useless now // RF Interface Readback Value */\n#define\t\trFPGA0_XCD_RFInterfaceRB\t\t0x8e4\t/* Useless now */\n\n/*\n * 4. Page9(0x900)\n *   */\n#define\trFPGA1_RFMOD\t\t\t\t0x900\t/* RF mode & OFDM TxSC // RF BW Setting?? */\n#define\trFPGA1_TxBlock\t\t\t\t0x904\t/* Useless now */\n#define\trFPGA1_DebugSelect\t\t\t0x908\t/* Useless now */\n#define\trFPGA1_TxInfo\t\t\t\t0x90c\t/* Useless now // Status report?? */\n#define\trDPDT_control\t\t\t\t0x92c\n#define\trfe_ctrl_anta_src\t\t\t\t0x930\n#define\trS0S1_PathSwitch\t\t\t0x948\n#define\trBBrx_DFIR\t\t\t\t\t0x954\n\n/*\n * 5. PageA(0xA00)\n *\n * Set Control channel to upper or lower. These settings are required only for 40MHz */\n#define\t\trCCK0_System\t\t\t\t0xa00\n\n#define\t\trCCK0_AFESetting\t\t\t0xa04\t/* Disable init gain now // Select RX path by RSSI */\n#define\t\trCCK0_CCA\t\t\t\t\t0xa08\t/* Disable init gain now // Init gain */\n\n#define\t\trCCK0_RxAGC1\t\t\t\t0xa0c\t/* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */\n#define\t\trCCK0_RxAGC2\t\t\t\t0xa10\t/* AGC & DAGC */\n\n#define\t\trCCK0_RxHP\t\t\t\t\t0xa14\n\n#define\t\trCCK0_DSPParameter1\t\t0xa18\t/* Timing recovery & Channel estimation threshold */\n#define\t\trCCK0_DSPParameter2\t\t0xa1c\t/* SQ threshold */\n\n#define\t\trCCK0_TxFilter1\t\t\t\t0xa20\n#define\t\trCCK0_TxFilter2\t\t\t\t0xa24\n#define\t\trCCK0_DebugPort\t\t\t0xa28\t/* debug port and Tx filter3 */\n#define\t\trCCK0_FalseAlarmReport\t\t0xa2c\t/* 0xa2d\tuseless now 0xa30-a4f channel report */\n#define\t\trCCK0_TRSSIReport\t\t0xa50\n#define\t\trCCK0_RxReport\t\t\t0xa54  /* 0xa57 */\n#define\t\trCCK0_FACounterLower\t\t0xa5c  /* 0xa5b */\n#define\t\trCCK0_FACounterUpper\t\t0xa58  /* 0xa5c */\n\n/*\n * PageB(0xB00)\n *   */\n#define rPdp_AntA\t\t\t\t\t\t0xb00\n#define rPdp_AntA_4\t\t\t\t\t\t0xb04\n#define rPdp_AntA_8\t\t\t\t\t\t0xb08\n#define rPdp_AntA_C\t\t\t\t\t\t0xb0c\n#define rPdp_AntA_10\t\t\t\t\t0xb10\n#define rPdp_AntA_14\t\t\t\t\t0xb14\n#define rPdp_AntA_18\t\t\t\t\t0xb18\n#define rPdp_AntA_1C\t\t\t\t\t0xb1c\n#define rPdp_AntA_20\t\t\t\t\t0xb20\n#define rPdp_AntA_24\t\t\t\t\t0xb24\n\n#define rConfig_Pmpd_AntA\t\t\t\t0xb28\n#define rConfig_ram64x16\t\t\t\t0xb2c\n\n#define rBndA\t\t\t\t\t\t\t0xb30\n#define rHssiPar\t\t\t\t\t\t0xb34\n\n#define rConfig_AntA\t\t\t\t\t0xb68\n#define rConfig_AntB\t\t\t\t\t0xb6c\n\n#define rPdp_AntB\t\t\t\t\t\t0xb70\n#define rPdp_AntB_4\t\t\t\t\t\t0xb74\n#define rPdp_AntB_8\t\t\t\t\t\t0xb78\n#define rPdp_AntB_C\t\t\t\t\t\t0xb7c\n#define rPdp_AntB_10\t\t\t\t\t0xb80\n#define rPdp_AntB_14\t\t\t\t\t0xb84\n#define rPdp_AntB_18\t\t\t\t\t0xb88\n#define rPdp_AntB_1C\t\t\t\t\t0xb8c\n#define rPdp_AntB_20\t\t\t\t\t0xb90\n#define rPdp_AntB_24\t\t\t\t\t0xb94\n\n#define rConfig_Pmpd_AntB\t\t\t\t0xb98\n\n#define rBndB\t\t\t\t\t\t\t0xba0\n\n#define rAPK\t\t\t\t\t\t\t0xbd8\n#define rPm_Rx0_AntA\t\t\t\t\t0xbdc\n#define rPm_Rx1_AntA\t\t\t\t\t0xbe0\n#define rPm_Rx2_AntA\t\t\t\t\t0xbe4\n#define rPm_Rx3_AntA\t\t\t\t\t0xbe8\n#define rPm_Rx0_AntB\t\t\t\t\t0xbec\n#define rPm_Rx1_AntB\t\t\t\t\t0xbf0\n#define rPm_Rx2_AntB\t\t\t\t\t0xbf4\n#define rPm_Rx3_AntB\t\t\t\t\t0xbf8\n/*\n * 6. PageC(0xC00)\n *   */\n#define\t\trOFDM0_LSTF\t\t\t\t0xc00\n\n#define\t\trOFDM0_TRxPathEnable\t\t0xc04\n#define\t\trOFDM0_TRMuxPar\t\t\t0xc08\n#define\t\trOFDM0_TRSWIsolation\t\t0xc0c\n\n#define\t\trOFDM0_XARxAFE\t\t\t0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */\n#define\t\trOFDM0_XARxIQImbalance\t\t0xc14  /* RxIQ imbalance matrix */\n#define\t\trOFDM0_XBRxAFE\t\t0xc18\n#define\t\trOFDM0_XBRxIQImbalance\t0xc1c\n#define\t\trOFDM0_XCRxAFE\t\t0xc20\n#define\t\trOFDM0_XCRxIQImbalance\t0xc24\n#define\t\trOFDM0_XDRxAFE\t\t0xc28\n#define\t\trOFDM0_XDRxIQImbalance\t0xc2c\n\n#define\t\trOFDM0_RxDetector1\t\t\t0xc30  /* PD, BW & SBD\t// DM tune init gain */\n#define\t\trOFDM0_RxDetector2\t\t\t0xc34  /* SBD & Fame Sync. */\n#define\t\trOFDM0_RxDetector3\t\t\t0xc38  /* Frame Sync. */\n#define\t\trOFDM0_RxDetector4\t\t\t0xc3c  /* PD, SBD, Frame Sync & Short-GI */\n\n#define\t\trOFDM0_RxDSP\t\t\t\t0xc40  /* Rx Sync Path */\n#define\t\trOFDM0_CFOandDAGC\t\t0xc44  /* CFO & DAGC */\n#define\t\trOFDM0_CCADropThreshold\t0xc48 /* CCA Drop threshold */\n#define\t\trOFDM0_ECCAThreshold\t\t0xc4c /* energy CCA */\n\n#define\t\trOFDM0_XAAGCCore1\t\t\t0xc50\t/* DIG */\n#define\t\trOFDM0_XAAGCCore2\t\t\t0xc54\n#define\t\trOFDM0_XBAGCCore1\t\t\t0xc58\n#define\t\trOFDM0_XBAGCCore2\t\t\t0xc5c\n#define\t\trOFDM0_XCAGCCore1\t\t\t0xc60\n#define\t\trOFDM0_XCAGCCore2\t\t\t0xc64\n#define\t\trOFDM0_XDAGCCore1\t\t\t0xc68\n#define\t\trOFDM0_XDAGCCore2\t\t\t0xc6c\n\n#define\t\trOFDM0_AGCParameter1\t\t\t0xc70\n#define\t\trOFDM0_AGCParameter2\t\t\t0xc74\n#define\t\trOFDM0_AGCRSSITable\t\t\t0xc78\n#define\t\trOFDM0_HTSTFAGC\t\t\t\t0xc7c\n\n#define\t\trOFDM0_XATxIQImbalance\t\t0xc80\t/* TX PWR TRACK and DIG */\n#define\t\trOFDM0_XATxAFE\t\t\t\t0xc84\n#define\t\trOFDM0_XBTxIQImbalance\t\t0xc88\n#define\t\trOFDM0_XBTxAFE\t\t\t\t0xc8c\n#define\t\trOFDM0_XCTxIQImbalance\t\t0xc90\n#define\t\trOFDM0_XCTxAFE\t\t\t0xc94\n#define\t\trOFDM0_XDTxIQImbalance\t\t0xc98\n#define\t\trOFDM0_XDTxAFE\t\t\t\t0xc9c\n\n#define\t\trOFDM0_RxIQExtAnta\t\t\t0xca0\n#define\t\trOFDM0_TxCoeff1\t\t\t\t0xca4\n#define\t\trOFDM0_TxCoeff2\t\t\t\t0xca8\n#define\t\trOFDM0_TxCoeff3\t\t\t\t0xcac\n#define\t\trOFDM0_TxCoeff4\t\t\t\t0xcb0\n#define\t\trOFDM0_TxCoeff5\t\t\t\t0xcb4\n#define\t\trOFDM0_TxCoeff6\t\t\t\t0xcb8\n#define\t\trOFDM0_RxHPParameter\t\t\t0xce0\n#define\t\trOFDM0_TxPseudoNoiseWgt\t\t0xce4\n#define\t\trOFDM0_FrameSync\t\t\t\t0xcf0\n#define\t\trOFDM0_DFSReport\t\t\t\t0xcf4\n\n/*\n * 7. PageD(0xD00)\n *   */\n#define\t\trOFDM1_LSTF\t\t\t\t\t0xd00\n#define\t\trOFDM1_TRxPathEnable\t\t\t0xd04\n\n#define\t\trOFDM1_CFO\t\t\t\t\t\t0xd08\t/* No setting now */\n#define\t\trOFDM1_CSI1\t\t\t\t\t0xd10\n#define\t\trOFDM1_SBD\t\t\t\t\t\t0xd14\n#define\t\trOFDM1_CSI2\t\t\t\t\t0xd18\n#define\t\trOFDM1_CFOTracking\t\t\t0xd2c\n#define\t\trOFDM1_TRxMesaure1\t\t\t0xd34\n#define\t\trOFDM1_IntfDet\t\t\t\t\t0xd3c\n#define\t\trOFDM1_PseudoNoiseStateAB\t\t0xd50\n#define\t\trOFDM1_PseudoNoiseStateCD\t\t0xd54\n#define\t\trOFDM1_RxPseudoNoiseWgt\t\t0xd58\n\n#define\t\trOFDM_PHYCounter1\t\t\t\t0xda0  /* cca, parity fail */\n#define\t\trOFDM_PHYCounter2\t\t\t\t0xda4  /* rate illegal, crc8 fail */\n#define\t\trOFDM_PHYCounter3\t\t\t\t0xda8  /* MCS not support */\n\n#define\t\trOFDM_ShortCFOAB\t\t\t\t0xdac\t/* No setting now */\n#define\t\trOFDM_ShortCFOCD\t\t\t\t0xdb0\n#define\t\trOFDM_LongCFOAB\t\t\t\t0xdb4\n#define\t\trOFDM_LongCFOCD\t\t\t\t0xdb8\n#define\t\trOFDM_TailCFOAB\t\t\t\t0xdbc\n#define\t\trOFDM_TailCFOCD\t\t\t\t0xdc0\n#define\t\trOFDM_PWMeasure1\t\t0xdc4\n#define\t\trOFDM_PWMeasure2\t\t0xdc8\n#define\t\trOFDM_BWReport\t\t\t\t0xdcc\n#define\t\trOFDM_AGCReport\t\t\t\t0xdd0\n#define\t\trOFDM_RxSNR\t\t\t\t\t0xdd4\n#define\t\trOFDM_RxEVMCSI\t\t\t\t0xdd8\n#define\t\trOFDM_SIGReport\t\t\t\t0xddc\n\n\n/*\n * 8. PageE(0xE00)\n *   */\n#define\t\trTxAGC_A_Rate18_06\t\t\t0xe00\n#define\t\trTxAGC_A_Rate54_24\t\t\t0xe04\n#define\t\trTxAGC_A_CCK1_Mcs32\t\t\t0xe08\n#define\t\trTxAGC_A_Mcs03_Mcs00\t\t\t0xe10\n#define\t\trTxAGC_A_Mcs07_Mcs04\t\t\t0xe14\n#define\t\trTxAGC_A_Mcs11_Mcs08\t\t\t0xe18\n#define\t\trTxAGC_A_Mcs15_Mcs12\t\t\t0xe1c\n\n#define\t\trFPGA0_IQK\t\t\t\t\t0xe28\n#define\t\trTx_IQK_Tone_A\t\t\t\t0xe30\n#define\t\trRx_IQK_Tone_A\t\t\t\t0xe34\n#define\t\trTx_IQK_PI_A\t\t\t\t\t0xe38\n#define\t\trRx_IQK_PI_A\t\t\t\t\t0xe3c\n\n#define\t\trTx_IQK\t\t\t\t\t\t0xe40\n#define\t\trRx_IQK\t\t\t\t\t\t0xe44\n#define\t\trIQK_AGC_Pts\t\t\t\t\t0xe48\n#define\t\trIQK_AGC_Rsp\t\t\t\t\t0xe4c\n#define\t\trTx_IQK_Tone_B\t\t\t\t0xe50\n#define\t\trRx_IQK_Tone_B\t\t\t\t0xe54\n#define\t\trTx_IQK_PI_B\t\t\t\t\t0xe58\n#define\t\trRx_IQK_PI_B\t\t\t\t\t0xe5c\n#define\t\trIQK_AGC_Cont\t\t\t\t0xe60\n\n#define\t\trBlue_Tooth\t\t\t\t\t0xe6c\n#define\t\trRx_Wait_CCA\t\t\t\t\t0xe70\n#define\t\trTx_CCK_RFON\t\t\t\t\t0xe74\n#define\t\trTx_CCK_BBON\t\t\t\t0xe78\n#define\t\trTx_OFDM_RFON\t\t\t\t0xe7c\n#define\t\trTx_OFDM_BBON\t\t\t\t0xe80\n#define\t\trTx_To_Rx\t\t\t\t\t0xe84\n#define\t\trTx_To_Tx\t\t\t\t\t0xe88\n#define\t\trRx_CCK\t\t\t\t\t\t0xe8c\n\n#define\t\trTx_Power_Before_IQK_A\t\t0xe94\n#define\t\trTx_Power_After_IQK_A\t\t\t0xe9c\n\n#define\t\trRx_Power_Before_IQK_A\t\t0xea0\n#define\t\trRx_Power_Before_IQK_A_2\t\t0xea4\n#define\t\trRx_Power_After_IQK_A\t\t\t0xea8\n#define\t\trRx_Power_After_IQK_A_2\t\t0xeac\n\n#define\t\trTx_Power_Before_IQK_B\t\t0xeb4\n#define\t\trTx_Power_After_IQK_B\t\t\t0xebc\n\n#define\t\trRx_Power_Before_IQK_B\t\t0xec0\n#define\t\trRx_Power_Before_IQK_B_2\t\t0xec4\n#define\t\trRx_Power_After_IQK_B\t\t\t0xec8\n#define\t\trRx_Power_After_IQK_B_2\t\t0xecc\n\n#define\t\trRx_OFDM\t\t\t\t\t0xed0\n#define\t\trRx_Wait_RIFS\t\t\t\t0xed4\n#define\t\trRx_TO_Rx\t\t\t\t\t0xed8\n#define\t\trStandby\t\t\t\t\t\t0xedc\n#define\t\trSleep\t\t\t\t\t\t0xee0\n#define\t\trPMPD_ANAEN\t\t\t\t0xeec\n\n/*\n * 7. RF Register 0x00-0x2E (RF 8256)\n * RF-0222D 0x00-3F\n *\n * Zebra1 */\n#define\t\trZebra1_HSSIEnable\t\t\t\t0x0\t/* Useless now */\n#define\t\trZebra1_TRxEnable1\t\t\t\t0x1\n#define\t\trZebra1_TRxEnable2\t\t\t\t0x2\n#define\t\trZebra1_AGC\t\t\t\t\t0x4\n#define\t\trZebra1_ChargePump\t\t\t0x5\n#define\t\trZebra1_Channel\t\t\t\t0x7\t/* RF channel switch */\n\n/* #endif */\n#define\t\trZebra1_TxGain\t\t\t\t\t0x8\t/* Useless now */\n#define\t\trZebra1_TxLPF\t\t\t\t\t0x9\n#define\t\trZebra1_RxLPF\t\t\t\t\t0xb\n#define\t\trZebra1_RxHPFCorner\t\t\t0xc\n\n/* Zebra4 */\n#define\t\trGlobalCtrl\t\t\t\t\t\t0\t/* Useless now */\n#define\t\trRTL8256_TxLPF\t\t\t\t\t19\n#define\t\trRTL8256_RxLPF\t\t\t\t\t11\n\n/* RTL8258 */\n#define\t\trRTL8258_TxLPF\t\t\t\t\t0x11\t/* Useless now */\n#define\t\trRTL8258_RxLPF\t\t\t\t\t0x13\n#define\t\trRTL8258_RSSILPF\t\t\t\t0xa\n\n/*\n * RL6052 Register definition\n *   */\n#define\t\tRF_AC\t\t\t\t\t\t0x00\t/* */\n\n#define\t\tRF_IQADJ_G1\t\t\t\t0x01\t/* */\n#define\t\tRF_IQADJ_G2\t\t\t\t0x02\t/* */\n#define\t\tRF_BS_PA_APSET_G1_G4\t\t0x03\n#define\t\tRF_BS_PA_APSET_G5_G8\t\t0x04\n#define\t\tRF_POW_TRSW\t\t\t\t0x05\t/* */\n\n#define\t\tRF_GAIN_RX\t\t\t\t\t0x06\t/* */\n#define\t\tRF_GAIN_TX\t\t\t\t\t0x07\t/* */\n\n#define\t\tRF_TXM_IDAC\t\t\t\t0x08\t/* */\n#define\t\tRF_IPA_G\t\t\t\t\t0x09\t/* */\n#define\t\tRF_TXBIAS_G\t\t\t\t0x0A\n#define\t\tRF_TXPA_AG\t\t\t\t\t0x0B\n#define\t\tRF_IPA_A\t\t\t\t\t0x0C\t/* */\n#define\t\tRF_TXBIAS_A\t\t\t\t0x0D\n#define\t\tRF_BS_PA_APSET_G9_G11\t0x0E\n#define\t\tRF_BS_IQGEN\t\t\t\t0x0F\t/* */\n\n#define\t\tRF_MODE1\t\t\t\t\t0x10\t/* */\n#define\t\tRF_MODE2\t\t\t\t\t0x11\t/* */\n\n#define\t\tRF_RX_AGC_HP\t\t\t\t0x12\t/* */\n#define\t\tRF_TX_AGC\t\t\t\t\t0x13\t/* */\n#define\t\tRF_BIAS\t\t\t\t\t\t0x14\t/* */\n#define\t\tRF_IPA\t\t\t\t\t\t0x15\t/* */\n#define\t\tRF_TXBIAS\t\t\t\t\t0x16\n#define\t\tRF_POW_ABILITY\t\t\t0x17\t/* */\n#define\t\tRF_MODE_AG\t\t\t\t0x18\t/* */\n#define\t\trRfChannel\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define\t\tRF_CHNLBW\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define\t\tRF_TOP\t\t\t\t\t\t0x19\t/* */\n\n#define\t\tRF_RX_G1\t\t\t\t\t0x1A\t/* */\n#define\t\tRF_RX_G2\t\t\t\t\t0x1B\t/* */\n\n#define\t\tRF_RX_BB2\t\t\t\t\t0x1C\t/* */\n#define\t\tRF_RX_BB1\t\t\t\t\t0x1D\t/* */\n\n#define\t\tRF_RCK1\t\t\t\t\t0x1E\t/* */\n#define\t\tRF_RCK2\t\t\t\t\t0x1F\t/* */\n\n#define\t\tRF_TX_G1\t\t\t\t\t0x20\t/* */\n#define\t\tRF_TX_G2\t\t\t\t\t0x21\t/* */\n#define\t\tRF_TX_G3\t\t\t\t\t0x22\t/* */\n\n#define\t\tRF_TX_BB1\t\t\t\t\t0x23\t/* */\n\n#define\t\tRF_T_METER\t\t\t\t\t0x24\t/* */\n\n#define\t\tRF_SYN_G1\t\t\t\t\t0x25\t/* RF TX Power control */\n#define\t\tRF_SYN_G2\t\t\t\t\t0x26\t/* RF TX Power control */\n#define\t\tRF_SYN_G3\t\t\t\t\t0x27\t/* RF TX Power control */\n#define\t\tRF_SYN_G4\t\t\t\t\t0x28\t/* RF TX Power control */\n#define\t\tRF_SYN_G5\t\t\t\t\t0x29\t/* RF TX Power control */\n#define\t\tRF_SYN_G6\t\t\t\t\t0x2A\t/* RF TX Power control */\n#define\t\tRF_SYN_G7\t\t\t\t\t0x2B\t/* RF TX Power control */\n#define\t\tRF_SYN_G8\t\t\t\t\t0x2C\t/* RF TX Power control */\n\n#define\t\tRF_RCK_OS\t\t\t\t\t0x30\t/* RF TX PA control */\n\n#define\t\tRF_TXPA_G1\t\t\t\t\t0x31\t/* RF TX PA control */\n#define\t\tRF_TXPA_G2\t\t\t\t\t0x32\t/* RF TX PA control */\n#define\t\tRF_TXPA_G3\t\t\t\t\t0x33\t/* RF TX PA control */\n#define\tRF_TX_BIAS_A\t\t\t\t0x35\n#define\tRF_TX_BIAS_D\t\t\t\t0x36\n#define\tRF_LOBF_9\t\t\t\t\t0x38\n#define\tRF_RXRF_A3\t\t\t\t\t0x3C\t/*\t */\n#define\tRF_TRSW\t\t\t\t\t0x3F\n\n#define\tRF_TXRF_A2\t\t\t\t\t0x41\n#define\tRF_T_METER_88E\t\t\t\t0x42\n#define\tRF_TXPA_G4\t\t\t\t\t0x46\n#define\tRF_TXPA_A4\t\t\t\t\t0x4B\n#define\tRF_0x52\t\t\t\t\t0x52\n#define\tRF_WE_LUT\t\t\t\t\t0xEF\n#define\tRF_S0S1\t\t\t\t\t0xB0\n\n/*\n * Bit Mask\n *\n * 1. Page1(0x100) */\n#define\t\tbBBResetB\t\t\t\t\t\t0x100\t/* Useless now? */\n#define\t\tbGlobalResetB\t\t\t\t\t0x200\n#define\t\tbOFDMTxStart\t\t\t\t\t0x4\n#define\t\tbCCKTxStart\t\t\t\t\t\t0x8\n#define\t\tbCRC32Debug\t\t\t\t\t0x100\n#define\t\tbPMACLoopback\t\t\t\t\t0x10\n#define\t\tbTxLSIG\t\t\t\t\t\t\t0xffffff\n#define\t\tbOFDMTxRate\t\t\t\t\t0xf\n#define\t\tbOFDMTxReserved\t\t\t\t0x10\n#define\t\tbOFDMTxLength\t\t\t\t\t0x1ffe0\n#define\t\tbOFDMTxParity\t\t\t\t\t0x20000\n#define\t\tbTxHTSIG1\t\t\t\t\t\t0xffffff\n#define\t\tbTxHTMCSRate\t\t\t\t\t0x7f\n#define\t\tbTxHTBW\t\t\t\t\t\t0x80\n#define\t\tbTxHTLength\t\t\t\t\t0xffff00\n#define\t\tbTxHTSIG2\t\t\t\t\t\t0xffffff\n#define\t\tbTxHTSmoothing\t\t\t\t\t0x1\n#define\t\tbTxHTSounding\t\t\t\t\t0x2\n#define\t\tbTxHTReserved\t\t\t\t\t0x4\n#define\t\tbTxHTAggreation\t\t\t\t0x8\n#define\t\tbTxHTSTBC\t\t\t\t\t\t0x30\n#define\t\tbTxHTAdvanceCoding\t\t\t0x40\n#define\t\tbTxHTShortGI\t\t\t\t\t0x80\n#define\t\tbTxHTNumberHT_LTF\t\t\t0x300\n#define\t\tbTxHTCRC8\t\t\t\t\t\t0x3fc00\n#define\t\tbCounterReset\t\t\t\t\t0x10000\n#define\t\tbNumOfOFDMTx\t\t\t\t\t0xffff\n#define\t\tbNumOfCCKTx\t\t\t\t\t0xffff0000\n#define\t\tbTxIdleInterval\t\t\t\t\t0xffff\n#define\t\tbOFDMService\t\t\t\t\t0xffff0000\n#define\t\tbTxMACHeader\t\t\t\t\t0xffffffff\n#define\t\tbTxDataInit\t\t\t\t\t\t0xff\n#define\t\tbTxHTMode\t\t\t\t\t\t0x100\n#define\t\tbTxDataType\t\t\t\t\t0x30000\n#define\t\tbTxRandomSeed\t\t\t\t\t0xffffffff\n#define\t\tbCCKTxPreamble\t\t\t\t\t0x1\n#define\t\tbCCKTxSFD\t\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxSIG\t\t\t\t\t\t0xff\n#define\t\tbCCKTxService\t\t\t\t\t0xff00\n#define\t\tbCCKLengthExt\t\t\t\t\t0x8000\n#define\t\tbCCKTxLength\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxCRC16\t\t\t\t\t0xffff\n#define\t\tbCCKTxStatus\t\t\t\t\t0x1\n#define\t\tbOFDMTxStatus\t\t\t\t\t0x2\n\n#define\t\tIS_BB_REG_OFFSET_92S(_Offset)\t\t((_Offset >= 0x800) && (_Offset <= 0xfff))\n#define\t\tRF_TX_GAIN_OFFSET_8710B(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0))\n\n/* 2. Page8(0x800) */\n#define\t\tbRFMOD\t\t\t\t\t\t\t0x1\t/* Reg 0x800 rFPGA0_RFMOD */\n#define\t\tbJapanMode\t\t\t\t\t\t0x2\n#define\t\tbCCKTxSC\t\t\t\t\t\t0x30\n#define\t\tbCCKEn\t\t\t\t\t\t\t0x1000000\n#define\t\tbOFDMEn\t\t\t\t\t\t0x2000000\n\n#define\t\tbOFDMRxADCPhase           0x10000\t/* Useless now */\n#define\t\tbOFDMTxDACPhase\t\t0x40000\n#define\t\tbXATxAGC\t\t\t0x3f\n\n#define\t\tbAntennaSelect\t\t0x0300\n\n#define\t\tbXBTxAGC                 0xf00\t/* Reg 80c rFPGA0_TxGainStage */\n#define\t\tbXCTxAGC\t\t\t0xf000\n#define\t\tbXDTxAGC\t\t\t0xf0000\n\n#define\t\tbPAStart                 0xf0000000\t/* Useless now */\n#define\t\tbTRStart\t\t\t0x00f00000\n#define\t\tbRFStart\t\t\t0x0000f000\n#define\t\tbBBStart\t\t\t0x000000f0\n#define\t\tbBBCCKStart\t\t0x0000000f\n#define\t\tbPAEnd                    0xf          /* Reg0x814 */\n#define\t\tbTREnd\t\t\t0x0f000000\n#define\t\tbRFEnd\t\t\t0x000f0000\n#define\t\tbCCAMask                  0x000000f0   /* T2R */\n#define\t\tbR2RCCAMask\t\t0x00000f00\n#define\t\tbHSSI_R2TDelay\t\t0xf8000000\n#define\t\tbHSSI_T2RDelay\t\t0xf80000\n#define\t\tbContTxHSSI              0x400     /* chane gain at continue Tx */\n#define\t\tbIGFromCCK\t\t0x200\n#define\t\tbAGCAddress\t\t0x3f\n#define\t\tbRxHPTx\t\t\t0x7000\n#define\t\tbRxHPT2R\t\t\t0x38000\n#define\t\tbRxHPCCKIni\t\t0xc0000\n#define\t\tbAGCTxCode\t\t0xc00000\n#define\t\tbAGCRxCode\t\t0x300000\n\n#define\t\tb3WireDataLength         0x800\t/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */\n#define\t\tb3WireAddressLength\t\t0x400\n\n#define\t\tb3WireRFPowerDown         0x1\t/* Useless now\n * #define bHWSISelect\t\t0x8 */\n#define\t\tb5GPAPEPolarity\t\t0x40000000\n#define\t\tb2GPAPEPolarity\t\t0x80000000\n#define\t\tbRFSW_TxDefaultAnt\t\t0x3\n#define\t\tbRFSW_TxOptionAnt\t\t0x30\n#define\t\tbRFSW_RxDefaultAnt\t\t0x300\n#define\t\tbRFSW_RxOptionAnt\t\t0x3000\n#define\t\tbRFSI_3WireData\t\t0x1\n#define\t\tbRFSI_3WireClock\t\t0x2\n#define\t\tbRFSI_3WireLoad\t\t0x4\n#define\t\tbRFSI_3WireRW\t\t0x8\n#define\t\tbRFSI_3Wire\t\t\t0xf\n\n#define\t\tbRFSI_RFENV              0x10\t/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */\n\n#define\t\tbRFSI_TRSW               0x20\t/* Useless now */\n#define\t\tbRFSI_TRSWB\t\t0x40\n#define\t\tbRFSI_ANTSW\t\t0x100\n#define\t\tbRFSI_ANTSWB\t\t0x200\n#define\t\tbRFSI_PAPE\t\t\t0x400\n#define\t\tbRFSI_PAPE5G\t\t0x800\n#define\t\tbBandSelect\t\t\t0x1\n#define\t\tbHTSIG2_GI\t\t\t0x80\n#define\t\tbHTSIG2_Smoothing\t\t0x01\n#define\t\tbHTSIG2_Sounding\t\t0x02\n#define\t\tbHTSIG2_Aggreaton\t\t0x08\n#define\t\tbHTSIG2_STBC\t\t0x30\n#define\t\tbHTSIG2_AdvCoding\t\t0x40\n#define\t\tbHTSIG2_NumOfHTLTF\t0x300\n#define\t\tbHTSIG2_CRC8\t\t0x3fc\n#define\t\tbHTSIG1_MCS\t\t0x7f\n#define\t\tbHTSIG1_BandWidth\t\t0x80\n#define\t\tbHTSIG1_HTLength\t\t0xffff\n#define\t\tbLSIG_Rate\t\t\t0xf\n#define\t\tbLSIG_Reserved\t\t0x10\n#define\t\tbLSIG_Length\t\t0x1fffe\n#define\t\tbLSIG_Parity\t\t\t0x20\n#define\t\tbCCKRxPhase\t\t0x4\n\n#define\t\tbLSSIReadAddress          0x7f800000   /* T65 RF */\n\n#define\t\tbLSSIReadEdge             0x80000000   /* LSSI \"Read\" edge signal */\n\n#define\t\tbLSSIReadBackData         0xfffff\t\t/* T65 RF */\n\n#define\t\tbLSSIReadOKFlag           0x1000\t/* Useless now */\n#define\t\tbCCKSampleRate            0x8       /* 0: 44MHz, 1:88MHz     */\n#define\t\tbRegulator0Standby\t\t0x1\n#define\t\tbRegulatorPLLStandby\t\t0x2\n#define\t\tbRegulator1Standby\t\t0x4\n#define\t\tbPLLPowerUp\t\t0x8\n#define\t\tbDPLLPowerUp\t\t0x10\n#define\t\tbDA10PowerUp\t\t0x20\n#define\t\tbAD7PowerUp\t\t0x200\n#define\t\tbDA6PowerUp\t\t0x2000\n#define\t\tbXtalPowerUp\t\t0x4000\n#define\t\tb40MDClkPowerUP\t\t0x8000\n#define\t\tbDA6DebugMode\t\t0x20000\n#define\t\tbDA6Swing\t\t\t0x380000\n\n#define\t\tbADClkPhase               0x4000000\t/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */\n\n#define\t\tb80MClkDelay              0x18000000\t/* Useless */\n#define\t\tbAFEWatchDogEnable\t\t0x20000000\n\n#define\t\tbXtalCap01                0xc0000000\t/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */\n#define\t\tbXtalCap23\t\t\t0x3\n#define\t\tbXtalCap92x\t\t\t\t\t0x0f000000\n#define\t\tbXtalCap\t\t\t0x0f000000\n\n#define\t\tbIntDifClkEnable          0x400\t/* Useless */\n#define\t\tbExtSigClkEnable\t\t0x800\n#define\t\tbBandgapMbiasPowerUp\t0x10000\n#define\t\tbAD11SHGain\t\t0xc0000\n#define\t\tbAD11InputRange\t\t0x700000\n#define\t\tbAD11OPCurrent\t\t0x3800000\n#define\t\tbIPathLoopback\t\t0x4000000\n#define\t\tbQPathLoopback\t\t0x8000000\n#define\t\tbAFELoopback\t\t0x10000000\n#define\t\tbDA10Swing\t\t0x7e0\n#define\t\tbDA10Reverse\t\t0x800\n#define\t\tbDAClkSource\t\t0x1000\n#define\t\tbAD7InputRange\t\t0x6000\n#define\t\tbAD7Gain\t\t\t0x38000\n#define\t\tbAD7OutputCMMode\t\t0x40000\n#define\t\tbAD7InputCMMode\t\t0x380000\n#define\t\tbAD7Current\t\t\t0xc00000\n#define\t\tbRegulatorAdjust\t\t0x7000000\n#define\t\tbAD11PowerUpAtTx\t\t0x1\n#define\t\tbDA10PSAtTx\t\t0x10\n#define\t\tbAD11PowerUpAtRx\t\t0x100\n#define\t\tbDA10PSAtRx\t\t0x1000\n#define\t\tbCCKRxAGCFormat\t\t0x200\n#define\t\tbPSDFFTSamplepPoint\t\t0xc000\n#define\t\tbPSDAverageNum\t\t0x3000\n#define\t\tbIQPathControl\t\t0xc00\n#define\t\tbPSDFreq\t\t\t0x3ff\n#define\t\tbPSDAntennaPath\t\t0x30\n#define\t\tbPSDIQSwitch\t\t0x40\n#define\t\tbPSDRxTrigger\t\t0x400000\n#define\t\tbPSDTxTrigger\t\t0x80000000\n#define\t\tbPSDSineToneScale\t\t0x7f000000\n#define\t\tbPSDReport\t\t\t0xffff\n\n/* 3. Page9(0x900) */\n#define\t\tbOFDMTxSC                 0x30000000\t/* Useless */\n#define\t\tbCCKTxOn\t\t\t0x1\n#define\t\tbOFDMTxOn\t\t0x2\n#define\t\tbDebugPage                0xfff  /* reset debug page and also HWord, LWord */\n#define\t\tbDebugItem                0xff   /* reset debug page and LWord */\n#define\t\tbAntL\t\t\t0x10\n#define\t\tbAntNonHT\t\t\t\t0x100\n#define\t\tbAntHT1\t\t\t0x1000\n#define\t\tbAntHT2\t\t\t0x10000\n#define\t\tbAntHT1S1\t\t\t0x100000\n#define\t\tbAntNonHTS1\t\t0x1000000\n\n/* 4. PageA(0xA00) */\n#define\t\tbCCKBBMode\t\t\t\t0x3\t/* Useless */\n#define\t\tbCCKTxPowerSaving\t\t0x80\n#define\t\tbCCKRxPowerSaving\t\t0x40\n\n#define\t\tbCCKSideBand\t\t\t0x10\t/* Reg 0xa00 rCCK0_System 20/40 switch */\n\n#define\t\tbCCKScramble\t\t\t0x8\t/* Useless */\n#define\t\tbCCKAntDiversity\t\t0x8000\n#define\t\tbCCKCarrierRecovery\t\t0x4000\n#define\t\tbCCKTxRate\t\t\t\t0x3000\n#define\t\tbCCKDCCancel\t\t\t0x0800\n#define\t\tbCCKISICancel\t\t\t0x0400\n#define\t\tbCCKMatchFilter\t\t\t0x0200\n#define\t\tbCCKEqualizer\t\t\t0x0100\n#define\t\tbCCKPreambleDetect\t\t0x800000\n#define\t\tbCCKFastFalseCCA\t\t0x400000\n#define\t\tbCCKChEstStart\t\t\t0x300000\n#define\t\tbCCKCCACount\t\t\t0x080000\n#define\t\tbCCKcs_lim\t\t\t\t0x070000\n#define\t\tbCCKBistMode\t\t\t0x80000000\n#define\t\tbCCKCCAMask\t\t\t0x40000000\n#define\t\tbCCKTxDACPhase\t\t0x4\n#define\t\tbCCKRxADCPhase\t\t0x20000000   /* r_rx_clk */\n#define\t\tbCCKr_cp_mode0\t\t0x0100\n#define\t\tbCCKTxDCOffset\t\t\t0xf0\n#define\t\tbCCKRxDCOffset\t\t\t0xf\n#define\t\tbCCKCCAMode\t\t\t0xc000\n#define\t\tbCCKFalseCS_lim\t\t\t0x3f00\n#define\t\tbCCKCS_ratio\t\t\t0xc00000\n#define\t\tbCCKCorgBit_sel\t\t\t0x300000\n#define\t\tbCCKPD_lim\t\t\t\t0x0f0000\n#define\t\tbCCKNewCCA\t\t\t0x80000000\n#define\t\tbCCKRxHPofIG\t\t\t0x8000\n#define\t\tbCCKRxIG\t\t\t\t0x7f00\n#define\t\tbCCKLNAPolarity\t\t\t0x800000\n#define\t\tbCCKRx1stGain\t\t\t0x7f0000\n#define\t\tbCCKRFExtend\t\t\t0x20000000 /* CCK Rx Iinital gain polarity */\n#define\t\tbCCKRxAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKRxAGCSatCount\t\t0xe0\n#define\t\tbCCKRxRFSettle\t\t\t0x1f       /* AGCsamp_dly */\n#define\t\tbCCKFixedRxAGC\t\t\t0x8000\n/* #define bCCKRxAGCFormat\t\t0x4000 */   /* remove to HSSI register 0x824 */\n#define\t\tbCCKAntennaPolarity\t\t0x2000\n#define\t\tbCCKTxFilterType\t\t0x0c00\n#define\t\tbCCKRxAGCReportType\t0x0300\n#define\t\tbCCKRxDAGCEn\t\t\t0x80000000\n#define\t\tbCCKRxDAGCPeriod\t\t0x20000000\n#define\t\tbCCKRxDAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKTimingRecovery\t\t0x800000\n#define\t\tbCCKTxC0\t\t\t\t0x3f0000\n#define\t\tbCCKTxC1\t\t\t\t0x3f000000\n#define\t\tbCCKTxC2\t\t\t\t0x3f\n#define\t\tbCCKTxC3\t\t\t\t0x3f00\n#define\t\tbCCKTxC4\t\t\t\t0x3f0000\n#define\t\tbCCKTxC5\t\t\t\t0x3f000000\n#define\t\tbCCKTxC6\t\t\t\t0x3f\n#define\t\tbCCKTxC7\t\t\t\t0x3f00\n#define\t\tbCCKDebugPort\t\t\t0xff0000\n#define\t\tbCCKDACDebug\t\t\t0x0f000000\n#define\t\tbCCKFalseAlarmEnable\t0x8000\n#define\t\tbCCKFalseAlarmRead\t\t0x4000\n#define\t\tbCCKTRSSI\t\t\t\t0x7f\n#define\t\tbCCKRxAGCReport\t\t0xfe\n#define\t\tbCCKRxReport_AntSel\t0x80000000\n#define\t\tbCCKRxReport_MFOff\t\t0x40000000\n#define\t\tbCCKRxRxReport_SQLoss\t0x20000000\n#define\t\tbCCKRxReport_Pktloss\t0x10000000\n#define\t\tbCCKRxReport_Lockedbit\t0x08000000\n#define\t\tbCCKRxReport_RateError\t0x04000000\n#define\t\tbCCKRxReport_RxRate\t0x03000000\n#define\t\tbCCKRxFACounterLower\t0xff\n#define\t\tbCCKRxFACounterUpper\t0xff000000\n#define\t\tbCCKRxHPAGCStart\t\t0xe000\n#define\t\tbCCKRxHPAGCFinal\t\t0x1c00\n#define\t\tbCCKRxFalseAlarmEnable\t0x8000\n#define\t\tbCCKFACounterFreeze\t0x4000\n#define\t\tbCCKTxPathSel\t\t\t0x10000000\n#define\t\tbCCKDefaultRxPath\t\t0xc000000\n#define\t\tbCCKOptionRxPath\t\t0x3000000\n\n/* 5. PageC(0xC00) */\n#define\t\tbNumOfSTF\t\t\t\t0x3\t/* Useless */\n#define\t\tbShift_L\t\t\t\t\t0xc0\n#define\t\tbGI_TH\t\t\t\t\t0xc\n#define\t\tbRxPathA\t\t\t\t0x1\n#define\t\tbRxPathB\t\t\t\t0x2\n#define\t\tbRxPathC\t\t\t\t0x4\n#define\t\tbRxPathD\t\t\t\t0x8\n#define\t\tbTxPathA\t\t\t\t0x1\n#define\t\tbTxPathB\t\t\t\t0x2\n#define\t\tbTxPathC\t\t\t\t0x4\n#define\t\tbTxPathD\t\t\t\t0x8\n#define\t\tbTRSSIFreq\t\t\t\t0x200\n#define\t\tbADCBackoff\t\t\t\t0x3000\n#define\t\tbDFIRBackoff\t\t\t0xc000\n#define\t\tbTRSSILatchPhase\t\t0x10000\n#define\t\tbRxIDCOffset\t\t\t0xff\n#define\t\tbRxQDCOffset\t\t\t0xff00\n#define\t\tbRxDFIRMode\t\t\t0x1800000\n#define\t\tbRxDCNFType\t\t\t0xe000000\n#define\t\tbRXIQImb_A\t\t\t\t0x3ff\n#define\t\tbRXIQImb_B\t\t\t\t0xfc00\n#define\t\tbRXIQImb_C\t\t\t\t0x3f0000\n#define\t\tbRXIQImb_D\t\t\t\t0xffc00000\n#define\t\tbDC_dc_Notch\t\t\t0x60000\n#define\t\tbRxNBINotch\t\t\t0x1f000000\n#define\t\tbPD_TH\t\t\t\t\t0xf\n#define\t\tbPD_TH_Opt2\t\t\t0xc000\n#define\t\tbPWED_TH\t\t\t\t0x700\n#define\t\tbIfMF_Win_L\t\t\t0x800\n#define\t\tbPD_Option\t\t\t\t0x1000\n#define\t\tbMF_Win_L\t\t\t\t0xe000\n#define\t\tbBW_Search_L\t\t\t0x30000\n#define\t\tbwin_enh_L\t\t\t\t0xc0000\n#define\t\tbBW_TH\t\t\t\t\t0x700000\n#define\t\tbED_TH2\t\t\t\t0x3800000\n#define\t\tbBW_option\t\t\t\t0x4000000\n#define\t\tbRatio_TH\t\t\t\t0x18000000\n#define\t\tbWindow_L\t\t\t\t0xe0000000\n#define\t\tbSBD_Option\t\t\t\t0x1\n#define\t\tbFrame_TH\t\t\t\t0x1c\n#define\t\tbFS_Option\t\t\t\t0x60\n#define\t\tbDC_Slope_check\t\t0x80\n#define\t\tbFGuard_Counter_DC_L\t0xe00\n#define\t\tbFrame_Weight_Short\t0x7000\n#define\t\tbSub_Tune\t\t\t\t0xe00000\n#define\t\tbFrame_DC_Length\t\t0xe000000\n#define\t\tbSBD_start_offset\t\t0x30000000\n#define\t\tbFrame_TH_2\t\t\t0x7\n#define\t\tbFrame_GI2_TH\t\t\t0x38\n#define\t\tbGI2_Sync_en\t\t\t0x40\n#define\t\tbSarch_Short_Early\t\t0x300\n#define\t\tbSarch_Short_Late\t\t0xc00\n#define\t\tbSarch_GI2_Late\t\t0x70000\n#define\t\tbCFOAntSum\t\t\t\t0x1\n#define\t\tbCFOAcc\t\t\t\t0x2\n#define\t\tbCFOStartOffset\t\t\t0xc\n#define\t\tbCFOLookBack\t\t\t0x70\n#define\t\tbCFOSumWeight\t\t\t0x80\n#define\t\tbDAGCEnable\t\t\t0x10000\n#define\t\tbTXIQImb_A\t\t\t\t0x3ff\n#define\t\tbTXIQImb_B\t\t\t\t0xfc00\n#define\t\tbTXIQImb_C\t\t\t\t0x3f0000\n#define\t\tbTXIQImb_D\t\t\t\t0xffc00000\n#define\t\tbTxIDCOffset\t\t\t0xff\n#define\t\tbTxQDCOffset\t\t\t0xff00\n#define\t\tbTxDFIRMode\t\t\t0x10000\n#define\t\tbTxPesudoNoiseOn\t\t0x4000000\n#define\t\tbTxPesudoNoise_A\t\t0xff\n#define\t\tbTxPesudoNoise_B\t\t0xff00\n#define\t\tbTxPesudoNoise_C\t\t0xff0000\n#define\t\tbTxPesudoNoise_D\t\t0xff000000\n#define\t\tbCCADropOption\t\t\t0x20000\n#define\t\tbCCADropThres\t\t\t0xfff00000\n#define\t\tbEDCCA_H\t\t\t\t0xf\n#define\t\tbEDCCA_L\t\t\t\t0xf0\n#define\t\tbLambda_ED\t\t\t0x300\n#define\t\tbRxInitialGain\t\t\t0x7f\n#define\t\tbRxAntDivEn\t\t\t\t0x80\n#define\t\tbRxAGCAddressForLNA\t0x7f00\n#define\t\tbRxHighPowerFlow\t\t0x8000\n#define\t\tbRxAGCFreezeThres\t\t0xc0000\n#define\t\tbRxFreezeStep_AGC1\t0x300000\n#define\t\tbRxFreezeStep_AGC2\t0xc00000\n#define\t\tbRxFreezeStep_AGC3\t0x3000000\n#define\t\tbRxFreezeStep_AGC0\t0xc000000\n#define\t\tbRxRssi_Cmp_En\t\t\t0x10000000\n#define\t\tbRxQuickAGCEn\t\t\t0x20000000\n#define\t\tbRxAGCFreezeThresMode\t0x40000000\n#define\t\tbRxOverFlowCheckType\t0x80000000\n#define\t\tbRxAGCShift\t\t\t\t0x7f\n#define\t\tbTRSW_Tri_Only\t\t\t0x80\n#define\t\tbPowerThres\t\t\t0x300\n#define\t\tbRxAGCEn\t\t\t\t0x1\n#define\t\tbRxAGCTogetherEn\t\t0x2\n#define\t\tbRxAGCMin\t\t\t\t0x4\n#define\t\tbRxHP_Ini\t\t\t\t0x7\n#define\t\tbRxHP_TRLNA\t\t\t0x70\n#define\t\tbRxHP_RSSI\t\t\t\t0x700\n#define\t\tbRxHP_BBP1\t\t\t\t0x7000\n#define\t\tbRxHP_BBP2\t\t\t\t0x70000\n#define\t\tbRxHP_BBP3\t\t\t\t0x700000\n#define\t\tbRSSI_H\t\t\t\t\t0x7f0000     /* the threshold for high power */\n#define\t\tbRSSI_Gen\t\t\t\t0x7f000000   /* the threshold for ant diversity */\n#define\t\tbRxSettle_TRSW\t\t\t0x7\n#define\t\tbRxSettle_LNA\t\t\t0x38\n#define\t\tbRxSettle_RSSI\t\t\t0x1c0\n#define\t\tbRxSettle_BBP\t\t\t0xe00\n#define\t\tbRxSettle_RxHP\t\t\t0x7000\n#define\t\tbRxSettle_AntSW_RSSI\t0x38000\n#define\t\tbRxSettle_AntSW\t\t0xc0000\n#define\t\tbRxProcessTime_DAGC\t0x300000\n#define\t\tbRxSettle_HSSI\t\t\t0x400000\n#define\t\tbRxProcessTime_BBPPW\t0x800000\n#define\t\tbRxAntennaPowerShift\t0x3000000\n#define\t\tbRSSITableSelect\t\t0xc000000\n#define\t\tbRxHP_Final\t\t\t\t0x7000000\n#define\t\tbRxHTSettle_BBP\t\t\t0x7\n#define\t\tbRxHTSettle_HSSI\t\t0x8\n#define\t\tbRxHTSettle_RxHP\t\t0x70\n#define\t\tbRxHTSettle_BBPPW\t\t0x80\n#define\t\tbRxHTSettle_Idle\t\t0x300\n#define\t\tbRxHTSettle_Reserved\t0x1c00\n#define\t\tbRxHTRxHPEn\t\t\t0x8000\n#define\t\tbRxHTAGCFreezeThres\t0x30000\n#define\t\tbRxHTAGCTogetherEn\t0x40000\n#define\t\tbRxHTAGCMin\t\t\t0x80000\n#define\t\tbRxHTAGCEn\t\t\t\t0x100000\n#define\t\tbRxHTDAGCEn\t\t\t0x200000\n#define\t\tbRxHTRxHP_BBP\t\t\t0x1c00000\n#define\t\tbRxHTRxHP_Final\t\t0xe0000000\n#define\t\tbRxPWRatioTH\t\t\t0x3\n#define\t\tbRxPWRatioEn\t\t\t0x4\n#define\t\tbRxMFHold\t\t\t\t0x3800\n#define\t\tbRxPD_Delay_TH1\t\t0x38\n#define\t\tbRxPD_Delay_TH2\t\t0x1c0\n#define\t\tbRxPD_DC_COUNT_MAX\t0x600\n/* #define bRxMF_Hold               0x3800 */\n#define\t\tbRxPD_Delay_TH\t\t\t0x8000\n#define\t\tbRxProcess_Delay\t\t0xf0000\n#define\t\tbRxSearchrange_GI2_Early\t0x700000\n#define\t\tbRxFrame_Guard_Counter_L\t0x3800000\n#define\t\tbRxSGI_Guard_L\t\t\t0xc000000\n#define\t\tbRxSGI_Search_L\t\t0x30000000\n#define\t\tbRxSGI_TH\t\t\t\t0xc0000000\n#define\t\tbDFSCnt0\t\t\t\t0xff\n#define\t\tbDFSCnt1\t\t\t\t0xff00\n#define\t\tbDFSFlag\t\t\t\t0xf0000\n#define\t\tbMFWeightSum\t\t\t0x300000\n#define\t\tbMinIdxTH\t\t\t\t0x7f000000\n#define\t\tbDAFormat\t\t\t\t0x40000\n#define\t\tbTxChEmuEnable\t\t0x01000000\n#define\t\tbTRSWIsolation_A\t\t0x7f\n#define\t\tbTRSWIsolation_B\t\t0x7f00\n#define\t\tbTRSWIsolation_C\t\t0x7f0000\n#define\t\tbTRSWIsolation_D\t\t0x7f000000\n#define\t\tbExtLNAGain\t\t\t\t0x7c00\n\n/* 6. PageE(0xE00) */\n#define\t\tbSTBCEn\t\t\t\t0x4\t/* Useless */\n#define\t\tbAntennaMapping\t\t0x10\n#define\t\tbNss\t\t\t\t\t0x20\n#define\t\tbCFOAntSumD\t\t\t0x200\n#define\t\tbPHYCounterReset\t\t0x8000000\n#define\t\tbCFOReportGet\t\t\t0x4000000\n#define\t\tbOFDMContinueTx\t\t0x10000000\n#define\t\tbOFDMSingleCarrier\t\t0x20000000\n#define\t\tbOFDMSingleTone\t\t0x40000000\n/* #define bRxPath1                 0x01 */\n/* #define bRxPath2                 0x02 */\n/* #define bRxPath3                 0x04 */\n/* #define bRxPath4                 0x08 */\n/* #define bTxPath1                 0x10 */\n/* #define bTxPath2                 0x20 */\n#define\t\tbHTDetect\t\t\t0x100\n#define\t\tbCFOEn\t\t\t\t0x10000\n#define\t\tbCFOValue\t\t\t0xfff00000\n#define\t\tbSigTone_Re\t\t0x3f\n#define\t\tbSigTone_Im\t\t0x7f00\n#define\t\tbCounter_CCA\t\t0xffff\n#define\t\tbCounter_ParityFail\t0xffff0000\n#define\t\tbCounter_RateIllegal\t\t0xffff\n#define\t\tbCounter_CRC8Fail\t0xffff0000\n#define\t\tbCounter_MCSNoSupport\t0xffff\n#define\t\tbCounter_FastSync\t0xffff\n#define\t\tbShortCFO\t\t\t0xfff\n#define\t\tbShortCFOTLength\t12   /* total */\n#define\t\tbShortCFOFLength\t11   /* fraction */\n#define\t\tbLongCFO\t\t\t0x7ff\n#define\t\tbLongCFOTLength\t11\n#define\t\tbLongCFOFLength\t11\n#define\t\tbTailCFO\t\t\t0x1fff\n#define\t\tbTailCFOTLength\t\t13\n#define\t\tbTailCFOFLength\t\t12\n#define\t\tbmax_en_pwdB\t\t0xffff\n#define\t\tbCC_power_dB\t\t0xffff0000\n#define\t\tbnoise_pwdB\t\t0xffff\n#define\t\tbPowerMeasTLength\t10\n#define\t\tbPowerMeasFLength\t3\n#define\t\tbRx_HT_BW\t\t\t0x1\n#define\t\tbRxSC\t\t\t\t0x6\n#define\t\tbRx_HT\t\t\t\t0x8\n#define\t\tbNB_intf_det_on\t\t0x1\n#define\t\tbIntf_win_len_cfg\t0x30\n#define\t\tbNB_Intf_TH_cfg\t\t0x1c0\n#define\t\tbRFGain\t\t\t\t0x3f\n#define\t\tbTableSel\t\t\t0x40\n#define\t\tbTRSW\t\t\t\t0x80\n#define\t\tbRxSNR_A\t\t\t0xff\n#define\t\tbRxSNR_B\t\t\t0xff00\n#define\t\tbRxSNR_C\t\t\t0xff0000\n#define\t\tbRxSNR_D\t\t\t0xff000000\n#define\t\tbSNREVMTLength\t\t8\n#define\t\tbSNREVMFLength\t\t1\n#define\t\tbCSI1st\t\t\t\t0xff\n#define\t\tbCSI2nd\t\t\t\t0xff00\n#define\t\tbRxEVM1st\t\t\t0xff0000\n#define\t\tbRxEVM2nd\t\t\t0xff000000\n#define\t\tbSIGEVM\t\t\t0xff\n#define\t\tbPWDB\t\t\t\t0xff00\n#define\t\tbSGIEN\t\t\t\t0x10000\n\n#define\t\tbSFactorQAM1\t\t0xf\t/* Useless */\n#define\t\tbSFactorQAM2\t\t0xf0\n#define\t\tbSFactorQAM3\t\t0xf00\n#define\t\tbSFactorQAM4\t\t0xf000\n#define\t\tbSFactorQAM5\t\t0xf0000\n#define\t\tbSFactorQAM6\t\t0xf0000\n#define\t\tbSFactorQAM7\t\t0xf00000\n#define\t\tbSFactorQAM8\t\t0xf000000\n#define\t\tbSFactorQAM9\t\t0xf0000000\n#define\t\tbCSIScheme\t\t\t0x100000\n\n#define\t\tbNoiseLvlTopSet\t\t0x3\t/* Useless */\n#define\t\tbChSmooth\t\t\t0x4\n#define\t\tbChSmoothCfg1\t\t0x38\n#define\t\tbChSmoothCfg2\t\t0x1c0\n#define\t\tbChSmoothCfg3\t\t0xe00\n#define\t\tbChSmoothCfg4\t\t0x7000\n#define\t\tbMRCMode\t\t\t0x800000\n#define\t\tbTHEVMCfg\t\t\t0x7000000\n\n#define\t\tbLoopFitType\t\t0x1\t/* Useless */\n#define\t\tbUpdCFO\t\t\t0x40\n#define\t\tbUpdCFOOffData\t\t0x80\n#define\t\tbAdvUpdCFO\t\t\t0x100\n#define\t\tbAdvTimeCtrl\t\t0x800\n#define\t\tbUpdClko\t\t\t0x1000\n#define\t\tbFC\t\t\t\t\t0x6000\n#define\t\tbTrackingMode\t\t0x8000\n#define\t\tbPhCmpEnable\t\t0x10000\n#define\t\tbUpdClkoLTF\t\t0x20000\n#define\t\tbComChCFO\t\t\t0x40000\n#define\t\tbCSIEstiMode\t\t0x80000\n#define\t\tbAdvUpdEqz\t\t\t0x100000\n#define\t\tbUChCfg\t\t\t\t0x7000000\n#define\t\tbUpdEqz\t\t\t0x8000000\n\n/* Rx Pseduo noise */\n#define\t\tbRxPesudoNoiseOn\t\t0x20000000\t/* Useless */\n#define\t\tbRxPesudoNoise_A\t\t0xff\n#define\t\tbRxPesudoNoise_B\t\t0xff00\n#define\t\tbRxPesudoNoise_C\t\t0xff0000\n#define\t\tbRxPesudoNoise_D\t\t0xff000000\n#define\t\tbPesudoNoiseState_A\t0xffff\n#define\t\tbPesudoNoiseState_B\t0xffff0000\n#define\t\tbPesudoNoiseState_C\t0xffff\n#define\t\tbPesudoNoiseState_D\t0xffff0000\n\n/* 7. RF Register\n * Zebra1 */\n#define\t\tbZebra1_HSSIEnable\t\t0x8\t\t/* Useless */\n#define\t\tbZebra1_TRxControl\t\t0xc00\n#define\t\tbZebra1_TRxGainSetting\t0x07f\n#define\t\tbZebra1_RxCorner\t\t0xc00\n#define\t\tbZebra1_TxChargePump\t0x38\n#define\t\tbZebra1_RxChargePump\t0x7\n#define\t\tbZebra1_ChannelNum\t0xf80\n#define\t\tbZebra1_TxLPFBW\t\t0x400\n#define\t\tbZebra1_RxLPFBW\t\t0x600\n\n/* Zebra4 */\n#define\t\tbRTL8256RegModeCtrl1\t0x100\t/* Useless */\n#define\t\tbRTL8256RegModeCtrl0\t0x40\n#define\t\tbRTL8256_TxLPFBW\t\t0x18\n#define\t\tbRTL8256_RxLPFBW\t\t0x600\n\n/* RTL8258 */\n#define\t\tbRTL8258_TxLPFBW\t\t0xc\t/* Useless */\n#define\t\tbRTL8258_RxLPFBW\t\t0xc00\n#define\t\tbRTL8258_RSSILPFBW\t0xc0\n\n\n/*\n * Other Definition\n *   */\n\n/* byte endable for sb_write */\n#define\t\tbByte0\t\t\t\t0x1\t/* Useless */\n#define\t\tbByte1\t\t\t\t0x2\n#define\t\tbByte2\t\t\t\t0x4\n#define\t\tbByte3\t\t\t\t0x8\n#define\t\tbWord0\t\t\t\t0x3\n#define\t\tbWord1\t\t\t\t0xc\n#define\t\tbDWord\t\t\t\t0xf\n\n/* for PutRegsetting & GetRegSetting BitMask */\n#define\t\tbMaskByte0\t\t\t0xff\t/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */\n#define\t\tbMaskByte1\t\t\t0xff00\n#define\t\tbMaskByte2\t\t\t0xff0000\n#define\t\tbMaskByte3\t\t\t0xff000000\n#define\t\tbMaskHWord\t\t0xffff0000\n#define\t\tbMaskLWord\t\t\t0x0000ffff\n#define\t\tbMaskDWord\t\t0xffffffff\n#define\t\tbMaskH3Bytes\t\t0xffffff00\n#define\t\tbMask12Bits\t\t\t0xfff\n#define\t\tbMaskH4Bits\t\t\t0xf0000000\n#define\t\tbMaskOFDM_D\t\t0xffc00000\n#define\t\tbMaskCCK\t\t\t0x3f3f3f3f\n\n\n#define\t\tbEnable\t\t\t0x1\t/* Useless */\n#define\t\tbDisable\t\t0x0\n\n#define\t\tLeftAntenna\t\t0x0\t/* Useless */\n#define\t\tRightAntenna\t0x1\n\n#define\t\ttCheckTxStatus\t\t500   /* 500ms // Useless */\n#define\t\ttUpdateRxCounter\t100   /* 100ms */\n\n#define\t\trateCCK\t\t0\t/* Useless */\n#define\t\trateOFDM\t1\n#define\t\trateHT\t\t2\n\n/* define Register-End */\n#define\t\tbPMAC_End\t\t\t0x1ff\t/* Useless */\n#define\t\tbFPGAPHY0_End\t\t0x8ff\n#define\t\tbFPGAPHY1_End\t\t0x9ff\n#define\t\tbCCKPHY0_End\t\t0xaff\n#define\t\tbOFDMPHY0_End\t\t0xcff\n#define\t\tbOFDMPHY1_End\t\t0xdff\n\n/* define max debug item in each debug page\n * #define bMaxItem_FPGA_PHY0        0x9\n * #define bMaxItem_FPGA_PHY1        0x3\n * #define bMaxItem_PHY_11B          0x16\n * #define bMaxItem_OFDM_PHY0        0x29\n * #define bMaxItem_OFDM_PHY1        0x0 */\n\n#define\t\tbPMACControl\t\t0x0\t\t/* Useless */\n#define\t\tbWMACControl\t\t0x1\n#define\t\tbWNICControl\t\t0x2\n\n#define\t\tPathA\t\t\t0x0\t/* Useless */\n#define\t\tPathB\t\t\t0x1\n#define\t\tPathC\t\t\t0x2\n#define\t\tPathD\t\t\t0x3\n\n#endif\n"
  },
  {
    "path": "include/Hal8710BPwrSeq.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef REALTEK_POWER_SEQUENCE_8710B\n#define REALTEK_POWER_SEQUENCE_8710B\n\n/* #include \"PwrSeqCmd.h\" */\n#include \"HalPwrSeqCmd.h\"\n\n/*\n\tCheck document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd\n\tThere are 6 HW Power States:\n\t0: POFF--Power Off\n\t1: PDN--Power Down\n\t2: CARDEMU--Card Emulation\n\t3: ACT--Active Mode\n\t4: LPS--Low Power State\n\t5: SUS--Suspend\n\n\tThe transition from different states are defined below\n\tTRANS_CARDEMU_TO_ACT\n\tTRANS_ACT_TO_CARDEMU\n\tTRANS_CARDEMU_TO_SUS\n\tTRANS_SUS_TO_CARDEMU\n\tTRANS_CARDEMU_TO_PDN\n\tTRANS_ACT_TO_LPS\n\tTRANS_LPS_TO_ACT\n\n\tTRANS_END\n*/\n#define RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS 5\n#define RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS 4\n#define RTL8710B_TRANS_CARDEMU_TO_SUS_STEPS 7\n#define RTL8710B_TRANS_SUS_TO_CARDEMU_STEPS 15\n#define RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS 15\n#define RTL8710B_TRANS_PDN_TO_CARDEMU_STEPS 15\n#define RTL8710B_TRANS_ACT_TO_LPS_STEPS \t15\n#define RTL8710B_TRANS_LPS_TO_ACT_STEPS \t15\t\n#define RTL8710B_TRANS_ACT_TO_SWLPS_STEPS\t\t22\n#define RTL8710B_TRANS_SWLPS_TO_ACT_STEPS\t\t15\n#define RTL8710B_TRANS_END_STEPS\t\t1\n\n\n#define RTL8710B_TRANS_CARDEMU_TO_ACT \t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x005D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*AFE power mode selection:1:  LDO mode ,0:  Power-cut mode*/\\\n\t{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\\\n\t{0x0056, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x0E},\\\n\t{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\\\n\t{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \n\n\t\n#define RTL8710B_TRANS_ACT_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1|BIT2), 0},/*0x04[24:26] = 0 turn off RF*/\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1), 0},/*0x04[16:17] = 0 BB reset*/\t\\\n\t{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x20[1] = 1 turn off MAC by HW state machine*/\t\\\n\t{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x20[1] = 0 polling until return 0 to disable*/ \\\n\n\n#define RTL8710B_TRANS_CARDEMU_TO_SUS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/\n\n#define RTL8710B_TRANS_SUS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\n\t\n\n#define RTL8710B_TRANS_CARDEMU_TO_CARDDIS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\\\n\n#define RTL8710B_TRANS_CARDDIS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\n\n#define RTL8710B_TRANS_CARDEMU_TO_PDN\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/\n\n#define RTL8710B_TRANS_PDN_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/\n\n#define RTL8710B_TRANS_ACT_TO_LPS\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/\t\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/\t\\\n\t{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/\t\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/\t\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \\\n\t{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/\t\\\n\t{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/\t\n\n\n#define RTL8710B_TRANS_LPS_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\\\n\t{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\\\n\t{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*.\t0x08[4] = 0 \t switch TSF to 40M*/\\\n\t{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\\\n\t{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*.\t0x29[7:6] = 2b'00\t enable BB clock*/\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*.\t0x101[1] = 1*/\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*.\t0x100[7:0] = 0xFF\t enable WMAC TRX*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*.\t0x02[1:0] = 2b'11\t enable BB macro*/\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*.\t0x522 = 0*/\n \n#define RTL8710B_TRANS_END\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //\n\n\nextern WLAN_PWR_CFG rtl8710B_power_on_flow[RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8710B_radio_off_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8710B_card_disable_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8710B_card_enable_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8710B_suspend_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8710B_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8710B_resume_flow[RTL8710B_TRANS_SUS_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8710B_hwpdn_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8710B_enter_lps_flow[RTL8710B_TRANS_ACT_TO_LPS_STEPS+RTL8710B_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8710B_leave_lps_flow[RTL8710B_TRANS_LPS_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];\n\n#endif\n"
  },
  {
    "path": "include/Hal8723BPhyCfg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8723BPHYCFG_H__\n#define __INC_HAL8723BPHYCFG_H__\n\n/*--------------------------Define Parameters-------------------------------*/\n#define LOOP_LIMIT\t\t\t\t5\n#define MAX_STALL_TIME\t\t\t50\t\t/* us */\n#define AntennaDiversityValue\t0x80\t/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */\n#define MAX_TXPWR_IDX_NMODE_92S\t63\n#define Reset_Cnt_Limit\t\t\t3\n\n#ifdef CONFIG_PCI_HCI\n\t#define MAX_AGGR_NUM\t0x0B\n#else\n\t#define MAX_AGGR_NUM\t0x07\n#endif /* CONFIG_PCI_HCI */\n\n\n/*--------------------------Define Parameters End-------------------------------*/\n\n\n/*------------------------------Define structure----------------------------*/\n\n/*------------------------------Define structure End----------------------------*/\n\n/*--------------------------Exported Function prototype---------------------*/\nu32\nPHY_QueryBBReg_8723B(\n\t\tPADAPTER\tAdapter,\n\t\tu32\t\tRegAddr,\n\t\tu32\t\tBitMask\n);\n\nvoid\nPHY_SetBBReg_8723B(\n\t\tPADAPTER\tAdapter,\n\t\tu32\t\tRegAddr,\n\t\tu32\t\tBitMask,\n\t\tu32\t\tData\n);\n\nu32\nPHY_QueryRFReg_8723B(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tenum rf_path\t\t\teRFPath,\n\t\tu32\t\t\t\tRegAddr,\n\t\tu32\t\t\t\tBitMask\n);\n\nvoid\nPHY_SetRFReg_8723B(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tenum rf_path\t\t\teRFPath,\n\t\tu32\t\t\t\tRegAddr,\n\t\tu32\t\t\t\tBitMask,\n\t\tu32\t\t\t\tData\n);\n\n/* MAC/BB/RF HAL config */\nint PHY_BBConfig8723B(PADAPTER\tAdapter);\n\nint PHY_RFConfig8723B(PADAPTER\tAdapter);\n\ns32 PHY_MACConfig8723B(PADAPTER padapter);\n\nint\nPHY_ConfigRFWithParaFile_8723B(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu8\t\t\t\t\t*pFileName,\n\tenum rf_path\t\t\t\teRFPath\n);\n\nvoid\nPHY_SetTxPowerIndex_8723B(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu32\t\t\t\t\tPowerIndex,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate\n);\n\nu8\nPHY_GetTxPowerIndex_8723B(\n\t\tPADAPTER\t\t\tpAdapter,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate,\n\t\tu8\t\t\t\t\tBandWidth,\n\t\tu8\t\t\t\t\tChannel,\n\tstruct txpwr_idx_comp *tic\n);\n\nvoid\nPHY_SetTxPowerLevel8723B(\n\t\tPADAPTER\t\tAdapter,\n\t\tu8\t\t\tchannel\n);\n\nvoid\nPHY_SetSwChnlBWMode8723B(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu8\t\t\t\t\tchannel,\n\t\tenum channel_width\tBandwidth,\n\t\tu8\t\t\t\t\tOffset40,\n\t\tu8\t\t\t\t\tOffset80\n);\n\nvoid phy_set_rf_path_switch_8723b(\n\t\tstruct dm_struct\t\t*phydm,\n\t\tbool\t\tbMain\n);\n\n/*--------------------------Exported Function prototype End---------------------*/\n\n#endif\n"
  },
  {
    "path": "include/Hal8723BPhyReg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8723BPHYREG_H__\n#define __INC_HAL8723BPHYREG_H__\n\n#define\t\trSYM_WLBT_PAPE_SEL\t\t0x64\n/*\n * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00\n * 3. RF register 0x00-2E\n * 4. Bit Mask for BB/RF register\n * 5. Other defintion for BB/RF R/W\n *   */\n\n\n/*\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 1. Page1(0x100)\n *   */\n#define\t\trPMAC_Reset\t\t\t\t\t0x100\n#define\t\trPMAC_TxStart\t\t\t\t\t0x104\n#define\t\trPMAC_TxLegacySIG\t\t\t\t0x108\n#define\t\trPMAC_TxHTSIG1\t\t\t\t0x10c\n#define\t\trPMAC_TxHTSIG2\t\t\t\t0x110\n#define\t\trPMAC_PHYDebug\t\t\t\t0x114\n#define\t\trPMAC_TxPacketNum\t\t\t\t0x118\n#define\t\trPMAC_TxIdle\t\t\t\t\t0x11c\n#define\t\trPMAC_TxMACHeader0\t\t\t0x120\n#define\t\trPMAC_TxMACHeader1\t\t\t0x124\n#define\t\trPMAC_TxMACHeader2\t\t\t0x128\n#define\t\trPMAC_TxMACHeader3\t\t\t0x12c\n#define\t\trPMAC_TxMACHeader4\t\t\t0x130\n#define\t\trPMAC_TxMACHeader5\t\t\t0x134\n#define\t\trPMAC_TxDataType\t\t\t\t0x138\n#define\t\trPMAC_TxRandomSeed\t\t\t0x13c\n#define\t\trPMAC_CCKPLCPPreamble\t\t\t0x140\n#define\t\trPMAC_CCKPLCPHeader\t\t\t0x144\n#define\t\trPMAC_CCKCRC16\t\t\t\t0x148\n#define\t\trPMAC_OFDMRxCRC32OK\t\t\t0x170\n#define\t\trPMAC_OFDMRxCRC32Er\t\t\t0x174\n#define\t\trPMAC_OFDMRxParityEr\t\t\t0x178\n#define\t\trPMAC_OFDMRxCRC8Er\t\t\t0x17c\n#define\t\trPMAC_CCKCRxRC16Er\t\t\t0x180\n#define\t\trPMAC_CCKCRxRC32Er\t\t\t0x184\n#define\t\trPMAC_CCKCRxRC32OK\t\t\t0x188\n#define\t\trPMAC_TxStatus\t\t\t\t\t0x18c\n\n/*\n * 2. Page2(0x200)\n *\n * The following two definition are only used for USB interface. */\n#define\t\tRF_BB_CMD_ADDR\t\t\t\t0x02c0\t/* RF/BB read/write command address. */\n#define\t\tRF_BB_CMD_DATA\t\t\t\t0x02c4\t/* RF/BB read/write command data. */\n\n/*\n * 3. Page8(0x800)\n *   */\n#define\t\trFPGA0_RFMOD\t\t\t\t0x800\t/* RF mode & CCK TxSC */ /* RF BW Setting?? */\n\n#define\t\trFPGA0_TxInfo\t\t\t\t0x804\t/* Status report?? */\n#define\t\trFPGA0_PSDFunction\t\t\t0x808\n\n#define\t\trFPGA0_TxGainStage\t\t\t0x80c\t/* Set TX PWR init gain? */\n\n#define\t\trFPGA0_RFTiming1\t\t\t0x810\t/* Useless now */\n#define\t\trFPGA0_RFTiming2\t\t\t0x814\n\n#define\t\trFPGA0_XA_HSSIParameter1\t\t0x820\t/* RF 3 wire register */\n#define\t\trFPGA0_XA_HSSIParameter2\t\t0x824\n#define\t\trFPGA0_XB_HSSIParameter1\t\t0x828\n#define\t\trFPGA0_XB_HSSIParameter2\t\t0x82c\n#define\t\trTxAGC_B_Rate18_06\t\t\t\t0x830\n#define\t\trTxAGC_B_Rate54_24\t\t\t\t0x834\n#define\t\trTxAGC_B_CCK1_55_Mcs32\t\t0x838\n#define\t\trTxAGC_B_Mcs03_Mcs00\t\t\t0x83c\n\n#define\t\trTxAGC_B_Mcs07_Mcs04\t\t\t0x848\n#define\t\trTxAGC_B_Mcs11_Mcs08\t\t\t0x84c\n\n#define\t\trFPGA0_XA_LSSIParameter\t\t0x840\n#define\t\trFPGA0_XB_LSSIParameter\t\t0x844\n\n#define\t\trFPGA0_RFWakeUpParameter\t\t0x850\t/* Useless now */\n#define\t\trFPGA0_RFSleepUpParameter\t\t0x854\n\n#define\t\trFPGA0_XAB_SwitchControl\t\t0x858\t/* RF Channel switch */\n#define\t\trFPGA0_XCD_SwitchControl\t\t0x85c\n\n#define\t\trFPGA0_XA_RFInterfaceOE\t\t0x860\t/* RF Channel switch */\n#define\t\trFPGA0_XB_RFInterfaceOE\t\t0x864\n\n#define\t\trTxAGC_B_Mcs15_Mcs12\t\t\t0x868\n#define\t\trTxAGC_B_CCK11_A_CCK2_11\t\t0x86c\n\n#define\t\trFPGA0_XAB_RFInterfaceSW\t\t0x870\t/* RF Interface Software Control */\n#define\t\trFPGA0_XCD_RFInterfaceSW\t\t0x874\n\n#define\t\trFPGA0_XAB_RFParameter\t\t0x878\t/* RF Parameter */\n#define\t\trFPGA0_XCD_RFParameter\t\t0x87c\n\n#define\t\trFPGA0_AnalogParameter1\t\t0x880\t/* Crystal cap setting RF-R/W protection for parameter4?? */\n#define\t\trFPGA0_AnalogParameter2\t\t0x884\n#define\t\trFPGA0_AnalogParameter3\t\t0x888\t/* Useless now */\n#define\t\trFPGA0_AnalogParameter4\t\t0x88c\n\n#define\t\trFPGA0_XA_LSSIReadBack\t\t0x8a0\t/* Tranceiver LSSI Readback */\n#define\t\trFPGA0_XB_LSSIReadBack\t\t0x8a4\n#define\t\trFPGA0_XC_LSSIReadBack\t\t0x8a8\n#define\t\trFPGA0_XD_LSSIReadBack\t\t0x8ac\n\n#define\t\trFPGA0_PSDReport\t\t\t\t0x8b4\t/* Useless now */\n#define\t\tTransceiverA_HSPI_Readback\t0x8b8\t/* Transceiver A HSPI Readback */\n#define\t\tTransceiverB_HSPI_Readback\t0x8bc\t/* Transceiver B HSPI Readback */\n#define\t\trFPGA0_XAB_RFInterfaceRB\t\t0x8e0\t/* Useless now */ /* RF Interface Readback Value */\n#define\t\trFPGA0_XCD_RFInterfaceRB\t\t0x8e4\t/* Useless now */\n\n/*\n * 4. Page9(0x900)\n *   */\n#define\trFPGA1_RFMOD\t\t\t\t0x900\t/* RF mode & OFDM TxSC */ /* RF BW Setting?? */\n#define\trFPGA1_TxBlock\t\t\t\t0x904\t/* Useless now */\n#define\trFPGA1_DebugSelect\t\t\t0x908\t/* Useless now */\n#define\trFPGA1_TxInfo\t\t\t\t0x90c\t/* Useless now */ /* Status report?? */\n#define\trDPDT_control\t\t\t\t0x92c\n#define\trfe_ctrl_anta_src\t\t\t\t0x930\n#define\trS0S1_PathSwitch\t\t\t0x948\n\n/*\n * 5. PageA(0xA00)\n *\n * Set Control channel to upper or lower. These settings are required only for 40MHz */\n#define\t\trCCK0_System\t\t\t\t0xa00\n\n#define\t\trCCK0_AFESetting\t\t\t0xa04\t/* Disable init gain now */ /* Select RX path by RSSI */\n#define\t\trCCK0_CCA\t\t\t\t\t0xa08\t/* Disable init gain now */ /* Init gain */\n\n#define\t\trCCK0_RxAGC1\t\t\t\t0xa0c\t/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */\n#define\t\trCCK0_RxAGC2\t\t\t\t0xa10\t/* AGC & DAGC */\n\n#define\t\trCCK0_RxHP\t\t\t\t\t0xa14\n\n#define\t\trCCK0_DSPParameter1\t\t0xa18\t/* Timing recovery & Channel estimation threshold */\n#define\t\trCCK0_DSPParameter2\t\t0xa1c\t/* SQ threshold */\n\n#define\t\trCCK0_TxFilter1\t\t\t\t0xa20\n#define\t\trCCK0_TxFilter2\t\t\t\t0xa24\n#define\t\trCCK0_DebugPort\t\t\t0xa28\t/* debug port and Tx filter3 */\n#define\t\trCCK0_FalseAlarmReport\t\t0xa2c\t/* 0xa2d\tuseless now 0xa30-a4f channel report */\n#define\t\trCCK0_TRSSIReport\t\t0xa50\n#define\t\trCCK0_RxReport            \t\t0xa54  /* 0xa57 */\n#define\t\trCCK0_FACounterLower      \t0xa5c  /* 0xa5b */\n#define\t\trCCK0_FACounterUpper      \t0xa58  /* 0xa5c */\n\n/*\n * PageB(0xB00)\n *   */\n#define rPdp_AntA\t\t\t\t\t\t0xb00\n#define rPdp_AntA_4\t\t\t\t\t\t0xb04\n#define rPdp_AntA_8\t\t\t\t\t\t0xb08\n#define rPdp_AntA_C\t\t\t\t\t\t0xb0c\n#define rPdp_AntA_10\t\t\t\t\t0xb10\n#define rPdp_AntA_14\t\t\t\t\t0xb14\n#define rPdp_AntA_18\t\t\t\t\t0xb18\n#define rPdp_AntA_1C\t\t\t\t\t0xb1c\n#define rPdp_AntA_20\t\t\t\t\t0xb20\n#define rPdp_AntA_24\t\t\t\t\t0xb24\n\n#define rConfig_Pmpd_AntA\t\t\t\t0xb28\n#define rConfig_ram64x16\t\t\t\t0xb2c\n\n#define rBndA\t\t\t\t\t\t\t0xb30\n#define rHssiPar\t\t\t\t\t\t0xb34\n\n#define rConfig_AntA\t\t\t\t\t0xb68\n#define rConfig_AntB\t\t\t\t\t0xb6c\n\n#define rPdp_AntB\t\t\t\t\t\t0xb70\n#define rPdp_AntB_4\t\t\t\t\t\t0xb74\n#define rPdp_AntB_8\t\t\t\t\t\t0xb78\n#define rPdp_AntB_C\t\t\t\t\t\t0xb7c\n#define rPdp_AntB_10\t\t\t\t\t0xb80\n#define rPdp_AntB_14\t\t\t\t\t0xb84\n#define rPdp_AntB_18\t\t\t\t\t0xb88\n#define rPdp_AntB_1C\t\t\t\t\t0xb8c\n#define rPdp_AntB_20\t\t\t\t\t0xb90\n#define rPdp_AntB_24\t\t\t\t\t0xb94\n\n#define rConfig_Pmpd_AntB\t\t\t\t0xb98\n\n#define rBndB\t\t\t\t\t\t\t0xba0\n\n#define rAPK\t\t\t\t\t\t\t0xbd8\n#define rPm_Rx0_AntA\t\t\t\t\t0xbdc\n#define rPm_Rx1_AntA\t\t\t\t\t0xbe0\n#define rPm_Rx2_AntA\t\t\t\t\t0xbe4\n#define rPm_Rx3_AntA\t\t\t\t\t0xbe8\n#define rPm_Rx0_AntB\t\t\t\t\t0xbec\n#define rPm_Rx1_AntB\t\t\t\t\t0xbf0\n#define rPm_Rx2_AntB\t\t\t\t\t0xbf4\n#define rPm_Rx3_AntB\t\t\t\t\t0xbf8\n/*\n * 6. PageC(0xC00)\n *   */\n#define\t\trOFDM0_LSTF\t\t\t\t0xc00\n\n#define\t\trOFDM0_TRxPathEnable\t\t0xc04\n#define\t\trOFDM0_TRMuxPar\t\t\t0xc08\n#define\t\trOFDM0_TRSWIsolation\t\t0xc0c\n\n#define\t\trOFDM0_XARxAFE\t\t\t0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */\n#define\t\trOFDM0_XARxIQImbalance    \t0xc14  /* RxIQ imblance matrix */\n#define\t\trOFDM0_XBRxAFE\t\t0xc18\n#define\t\trOFDM0_XBRxIQImbalance\t0xc1c\n#define\t\trOFDM0_XCRxAFE\t\t0xc20\n#define\t\trOFDM0_XCRxIQImbalance\t0xc24\n#define\t\trOFDM0_XDRxAFE\t\t0xc28\n#define\t\trOFDM0_XDRxIQImbalance\t0xc2c\n\n#define\t\trOFDM0_RxDetector1\t\t\t0xc30  /* PD, BW & SBD\t */ /* DM tune init gain */\n#define\t\trOFDM0_RxDetector2\t\t\t0xc34  /* SBD & Fame Sync. */\n#define\t\trOFDM0_RxDetector3\t\t\t0xc38  /* Frame Sync. */\n#define\t\trOFDM0_RxDetector4\t\t\t0xc3c  /* PD, SBD, Frame Sync & Short-GI */\n\n#define\t\trOFDM0_RxDSP\t\t\t\t0xc40  /* Rx Sync Path */\n#define\t\trOFDM0_CFOandDAGC\t\t0xc44  /* CFO & DAGC */\n#define\t\trOFDM0_CCADropThreshold\t0xc48 /* CCA Drop threshold */\n#define\t\trOFDM0_ECCAThreshold\t\t0xc4c /* energy CCA */\n\n#define\t\trOFDM0_XAAGCCore1\t\t\t0xc50\t/* DIG */\n#define\t\trOFDM0_XAAGCCore2\t\t\t0xc54\n#define\t\trOFDM0_XBAGCCore1\t\t\t0xc58\n#define\t\trOFDM0_XBAGCCore2\t\t\t0xc5c\n#define\t\trOFDM0_XCAGCCore1\t\t\t0xc60\n#define\t\trOFDM0_XCAGCCore2\t\t\t0xc64\n#define\t\trOFDM0_XDAGCCore1\t\t\t0xc68\n#define\t\trOFDM0_XDAGCCore2\t\t\t0xc6c\n\n#define\t\trOFDM0_AGCParameter1\t\t\t0xc70\n#define\t\trOFDM0_AGCParameter2\t\t\t0xc74\n#define\t\trOFDM0_AGCRSSITable\t\t\t0xc78\n#define\t\trOFDM0_HTSTFAGC\t\t\t\t0xc7c\n\n#define\t\trOFDM0_XATxIQImbalance\t\t0xc80\t/* TX PWR TRACK and DIG */\n#define\t\trOFDM0_XATxAFE\t\t\t\t0xc84\n#define\t\trOFDM0_XBTxIQImbalance\t\t0xc88\n#define\t\trOFDM0_XBTxAFE\t\t\t\t0xc8c\n#define\t\trOFDM0_XCTxIQImbalance\t\t0xc90\n#define\t\trOFDM0_XCTxAFE\t\t\t0xc94\n#define\t\trOFDM0_XDTxIQImbalance\t\t0xc98\n#define\t\trOFDM0_XDTxAFE\t\t\t\t0xc9c\n\n#define\t\trOFDM0_RxIQExtAnta\t\t\t0xca0\n#define\t\trOFDM0_TxCoeff1\t\t\t\t0xca4\n#define\t\trOFDM0_TxCoeff2\t\t\t\t0xca8\n#define\t\trOFDM0_TxCoeff3\t\t\t\t0xcac\n#define\t\trOFDM0_TxCoeff4\t\t\t\t0xcb0\n#define\t\trOFDM0_TxCoeff5\t\t\t\t0xcb4\n#define\t\trOFDM0_TxCoeff6\t\t\t\t0xcb8\n#define\t\trOFDM0_RxHPParameter\t\t\t0xce0\n#define\t\trOFDM0_TxPseudoNoiseWgt\t\t0xce4\n#define\t\trOFDM0_FrameSync\t\t\t\t0xcf0\n#define\t\trOFDM0_DFSReport\t\t\t\t0xcf4\n\n/*\n * 7. PageD(0xD00)\n *   */\n#define\t\trOFDM1_LSTF\t\t\t\t\t0xd00\n#define\t\trOFDM1_TRxPathEnable\t\t\t0xd04\n\n#define\t\trOFDM1_CFO\t\t\t\t\t\t0xd08\t/* No setting now */\n#define\t\trOFDM1_CSI1\t\t\t\t\t0xd10\n#define\t\trOFDM1_SBD\t\t\t\t\t\t0xd14\n#define\t\trOFDM1_CSI2\t\t\t\t\t0xd18\n#define\t\trOFDM1_CFOTracking\t\t\t0xd2c\n#define\t\trOFDM1_TRxMesaure1\t\t\t0xd34\n#define\t\trOFDM1_IntfDet\t\t\t\t\t0xd3c\n#define\t\trOFDM1_PseudoNoiseStateAB\t\t0xd50\n#define\t\trOFDM1_PseudoNoiseStateCD\t\t0xd54\n#define\t\trOFDM1_RxPseudoNoiseWgt\t\t0xd58\n\n#define\t\trOFDM_PHYCounter1\t\t\t\t0xda0  /* cca, parity fail */\n#define\t\trOFDM_PHYCounter2\t\t\t\t0xda4  /* rate illegal, crc8 fail */\n#define\t\trOFDM_PHYCounter3\t\t\t\t0xda8  /* MCS not support */\n\n#define\t\trOFDM_ShortCFOAB\t\t\t\t0xdac\t/* No setting now */\n#define\t\trOFDM_ShortCFOCD\t\t\t\t0xdb0\n#define\t\trOFDM_LongCFOAB\t\t\t\t0xdb4\n#define\t\trOFDM_LongCFOCD\t\t\t\t0xdb8\n#define\t\trOFDM_TailCFOAB\t\t\t\t0xdbc\n#define\t\trOFDM_TailCFOCD\t\t\t\t0xdc0\n#define\t\trOFDM_PWMeasure1\t\t0xdc4\n#define\t\trOFDM_PWMeasure2\t\t0xdc8\n#define\t\trOFDM_BWReport\t\t\t\t0xdcc\n#define\t\trOFDM_AGCReport\t\t\t\t0xdd0\n#define\t\trOFDM_RxSNR\t\t\t\t\t0xdd4\n#define\t\trOFDM_RxEVMCSI\t\t\t\t0xdd8\n#define\t\trOFDM_SIGReport\t\t\t\t0xddc\n\n\n/*\n * 8. PageE(0xE00)\n *   */\n#define\t\trTxAGC_A_Rate18_06\t\t\t0xe00\n#define\t\trTxAGC_A_Rate54_24\t\t\t0xe04\n#define\t\trTxAGC_A_CCK1_Mcs32\t\t\t0xe08\n#define\t\trTxAGC_A_Mcs03_Mcs00\t\t\t0xe10\n#define\t\trTxAGC_A_Mcs07_Mcs04\t\t\t0xe14\n#define\t\trTxAGC_A_Mcs11_Mcs08\t\t\t0xe18\n#define\t\trTxAGC_A_Mcs15_Mcs12\t\t\t0xe1c\n\n#define\t\trFPGA0_IQK\t\t\t\t\t0xe28\n#define\t\trTx_IQK_Tone_A\t\t\t\t0xe30\n#define\t\trRx_IQK_Tone_A\t\t\t\t0xe34\n#define\t\trTx_IQK_PI_A\t\t\t\t\t0xe38\n#define\t\trRx_IQK_PI_A\t\t\t\t\t0xe3c\n\n#define\t\trTx_IQK\t\t\t\t\t\t0xe40\n#define\t\trRx_IQK\t\t\t\t\t\t0xe44\n#define\t\trIQK_AGC_Pts\t\t\t\t\t0xe48\n#define\t\trIQK_AGC_Rsp\t\t\t\t\t0xe4c\n#define\t\trTx_IQK_Tone_B\t\t\t\t0xe50\n#define\t\trRx_IQK_Tone_B\t\t\t\t0xe54\n#define\t\trTx_IQK_PI_B\t\t\t\t\t0xe58\n#define\t\trRx_IQK_PI_B\t\t\t\t\t0xe5c\n#define\t\trIQK_AGC_Cont\t\t\t\t0xe60\n\n#define\t\trBlue_Tooth\t\t\t\t\t0xe6c\n#define\t\trRx_Wait_CCA\t\t\t\t\t0xe70\n#define\t\trTx_CCK_RFON\t\t\t\t\t0xe74\n#define\t\trTx_CCK_BBON\t\t\t\t0xe78\n#define\t\trTx_OFDM_RFON\t\t\t\t0xe7c\n#define\t\trTx_OFDM_BBON\t\t\t\t0xe80\n#define\t\trTx_To_Rx\t\t\t\t\t0xe84\n#define\t\trTx_To_Tx\t\t\t\t\t0xe88\n#define\t\trRx_CCK\t\t\t\t\t\t0xe8c\n\n#define\t\trTx_Power_Before_IQK_A\t\t0xe94\n#define\t\trTx_Power_After_IQK_A\t\t\t0xe9c\n\n#define\t\trRx_Power_Before_IQK_A\t\t0xea0\n#define\t\trRx_Power_Before_IQK_A_2\t\t0xea4\n#define\t\trRx_Power_After_IQK_A\t\t\t0xea8\n#define\t\trRx_Power_After_IQK_A_2\t\t0xeac\n\n#define\t\trTx_Power_Before_IQK_B\t\t0xeb4\n#define\t\trTx_Power_After_IQK_B\t\t\t0xebc\n\n#define\t\trRx_Power_Before_IQK_B\t\t0xec0\n#define\t\trRx_Power_Before_IQK_B_2\t\t0xec4\n#define\t\trRx_Power_After_IQK_B\t\t\t0xec8\n#define\t\trRx_Power_After_IQK_B_2\t\t0xecc\n\n#define\t\trRx_OFDM\t\t\t\t\t0xed0\n#define\t\trRx_Wait_RIFS\t\t\t\t0xed4\n#define\t\trRx_TO_Rx\t\t\t\t\t0xed8\n#define\t\trStandby\t\t\t\t\t\t0xedc\n#define\t\trSleep\t\t\t\t\t\t0xee0\n#define\t\trPMPD_ANAEN\t\t\t\t0xeec\n\n/*\n * 7. RF Register 0x00-0x2E (RF 8256)\n * RF-0222D 0x00-3F\n *\n * Zebra1 */\n#define\t\trZebra1_HSSIEnable\t\t\t\t0x0\t/* Useless now */\n#define\t\trZebra1_TRxEnable1\t\t\t\t0x1\n#define\t\trZebra1_TRxEnable2\t\t\t\t0x2\n#define\t\trZebra1_AGC\t\t\t\t\t0x4\n#define\t\trZebra1_ChargePump\t\t\t0x5\n#define\t\trZebra1_Channel\t\t\t\t0x7\t/* RF channel switch */\n\n/* #endif */\n#define\t\trZebra1_TxGain\t\t\t\t\t0x8\t/* Useless now */\n#define\t\trZebra1_TxLPF\t\t\t\t\t0x9\n#define\t\trZebra1_RxLPF\t\t\t\t\t0xb\n#define\t\trZebra1_RxHPFCorner\t\t\t0xc\n\n/* Zebra4 */\n#define\t\trGlobalCtrl\t\t\t\t\t\t0\t/* Useless now */\n#define\t\trRTL8256_TxLPF\t\t\t\t\t19\n#define\t\trRTL8256_RxLPF\t\t\t\t\t11\n\n/* RTL8258 */\n#define\t\trRTL8258_TxLPF\t\t\t\t\t0x11\t/* Useless now */\n#define\t\trRTL8258_RxLPF\t\t\t\t\t0x13\n#define\t\trRTL8258_RSSILPF\t\t\t\t0xa\n\n/*\n * RL6052 Register definition\n *   */\n#define\t\tRF_AC\t\t\t\t\t\t0x00\t/*  */\n\n#define\t\tRF_IQADJ_G1\t\t\t\t0x01\t/*  */\n#define\t\tRF_IQADJ_G2\t\t\t\t0x02\t/*  */\n#define\t\tRF_BS_PA_APSET_G1_G4\t\t0x03\n#define\t\tRF_BS_PA_APSET_G5_G8\t\t0x04\n#define\t\tRF_POW_TRSW\t\t\t\t0x05\t/*  */\n\n#define\t\tRF_GAIN_RX\t\t\t\t\t0x06\t/*  */\n#define\t\tRF_GAIN_TX\t\t\t\t\t0x07\t/*  */\n\n#define\t\tRF_TXM_IDAC\t\t\t\t0x08\t/*  */\n#define\t\tRF_IPA_G\t\t\t\t\t0x09\t/*  */\n#define\t\tRF_TXBIAS_G\t\t\t\t0x0A\n#define\t\tRF_TXPA_AG\t\t\t\t\t0x0B\n#define\t\tRF_IPA_A\t\t\t\t\t0x0C\t/*  */\n#define\t\tRF_TXBIAS_A\t\t\t\t0x0D\n#define\t\tRF_BS_PA_APSET_G9_G11\t0x0E\n#define\t\tRF_BS_IQGEN\t\t\t\t0x0F\t/*  */\n\n#define\t\tRF_MODE1\t\t\t\t\t0x10\t/*  */\n#define\t\tRF_MODE2\t\t\t\t\t0x11\t/*  */\n\n#define\t\tRF_RX_AGC_HP\t\t\t\t0x12\t/*  */\n#define\t\tRF_TX_AGC\t\t\t\t\t0x13\t/*  */\n#define\t\tRF_BIAS\t\t\t\t\t\t0x14\t/*  */\n#define\t\tRF_IPA\t\t\t\t\t\t0x15\t/*  */\n#define\t\tRF_TXBIAS\t\t\t\t\t0x16\n#define\t\tRF_POW_ABILITY\t\t\t0x17\t/*  */\n#define\t\tRF_MODE_AG\t\t\t\t0x18\t/*  */\n#define\t\trRfChannel\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define\t\tRF_CHNLBW\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define\t\tRF_TOP\t\t\t\t\t\t0x19\t/*  */\n\n#define\t\tRF_RX_G1\t\t\t\t\t0x1A\t/*  */\n#define\t\tRF_RX_G2\t\t\t\t\t0x1B\t/*  */\n\n#define\t\tRF_RX_BB2\t\t\t\t\t0x1C\t/*  */\n#define\t\tRF_RX_BB1\t\t\t\t\t0x1D\t/*  */\n\n#define\t\tRF_RCK1\t\t\t\t\t0x1E\t/*  */\n#define\t\tRF_RCK2\t\t\t\t\t0x1F\t/*  */\n\n#define\t\tRF_TX_G1\t\t\t\t\t0x20\t/*  */\n#define\t\tRF_TX_G2\t\t\t\t\t0x21\t/*  */\n#define\t\tRF_TX_G3\t\t\t\t\t0x22\t/*  */\n\n#define\t\tRF_TX_BB1\t\t\t\t\t0x23\t/*  */\n\n#define\t\tRF_T_METER\t\t\t\t\t0x24\t/*  */\n\n#define\t\tRF_SYN_G1\t\t\t\t\t0x25\t/* RF TX Power control */\n#define\t\tRF_SYN_G2\t\t\t\t\t0x26\t/* RF TX Power control */\n#define\t\tRF_SYN_G3\t\t\t\t\t0x27\t/* RF TX Power control */\n#define\t\tRF_SYN_G4\t\t\t\t\t0x28\t/* RF TX Power control */\n#define\t\tRF_SYN_G5\t\t\t\t\t0x29\t/* RF TX Power control */\n#define\t\tRF_SYN_G6\t\t\t\t\t0x2A\t/* RF TX Power control */\n#define\t\tRF_SYN_G7\t\t\t\t\t0x2B\t/* RF TX Power control */\n#define\t\tRF_SYN_G8\t\t\t\t\t0x2C\t/* RF TX Power control */\n\n#define\t\tRF_RCK_OS\t\t\t\t\t0x30\t/* RF TX PA control */\n\n#define\t\tRF_TXPA_G1\t\t\t\t\t0x31\t/* RF TX PA control */\n#define\t\tRF_TXPA_G2\t\t\t\t\t0x32\t/* RF TX PA control */\n#define\t\tRF_TXPA_G3\t\t\t\t\t0x33\t/* RF TX PA control */\n#define\tRF_TX_BIAS_A\t\t\t\t0x35\n#define\tRF_TX_BIAS_D\t\t\t\t0x36\n#define\tRF_LOBF_9\t\t\t\t\t0x38\n#define \tRF_RXRF_A3\t\t\t\t\t0x3C\t/*\t */\n#define\tRF_TRSW\t\t\t\t\t0x3F\n\n#define\tRF_TXRF_A2\t\t\t\t\t0x41\n#define\tRF_TXPA_G4\t\t\t\t\t0x46\n#define\tRF_TXPA_A4\t\t\t\t\t0x4B\n#define\tRF_0x52\t\t\t\t\t0x52\n#define\tRF_WE_LUT\t\t\t\t\t0xEF\n#define\tRF_S0S1\t\t\t\t\t0xB0\n\n/*\n * Bit Mask\n *\n * 1. Page1(0x100) */\n#define\t\tbBBResetB\t\t\t\t\t\t0x100\t/* Useless now? */\n#define\t\tbGlobalResetB\t\t\t\t\t0x200\n#define\t\tbOFDMTxStart\t\t\t\t\t0x4\n#define\t\tbCCKTxStart\t\t\t\t\t\t0x8\n#define\t\tbCRC32Debug\t\t\t\t\t0x100\n#define\t\tbPMACLoopback\t\t\t\t\t0x10\n#define\t\tbTxLSIG\t\t\t\t\t\t\t0xffffff\n#define\t\tbOFDMTxRate\t\t\t\t\t0xf\n#define\t\tbOFDMTxReserved\t\t\t\t0x10\n#define\t\tbOFDMTxLength\t\t\t\t\t0x1ffe0\n#define\t\tbOFDMTxParity\t\t\t\t\t0x20000\n#define\t\tbTxHTSIG1\t\t\t\t\t\t0xffffff\n#define\t\tbTxHTMCSRate\t\t\t\t\t0x7f\n#define\t\tbTxHTBW\t\t\t\t\t\t0x80\n#define\t\tbTxHTLength\t\t\t\t\t0xffff00\n#define\t\tbTxHTSIG2\t\t\t\t\t\t0xffffff\n#define\t\tbTxHTSmoothing\t\t\t\t\t0x1\n#define\t\tbTxHTSounding\t\t\t\t\t0x2\n#define\t\tbTxHTReserved\t\t\t\t\t0x4\n#define\t\tbTxHTAggreation\t\t\t\t0x8\n#define\t\tbTxHTSTBC\t\t\t\t\t\t0x30\n#define\t\tbTxHTAdvanceCoding\t\t\t0x40\n#define\t\tbTxHTShortGI\t\t\t\t\t0x80\n#define\t\tbTxHTNumberHT_LTF\t\t\t0x300\n#define\t\tbTxHTCRC8\t\t\t\t\t\t0x3fc00\n#define\t\tbCounterReset\t\t\t\t\t0x10000\n#define\t\tbNumOfOFDMTx\t\t\t\t\t0xffff\n#define\t\tbNumOfCCKTx\t\t\t\t\t0xffff0000\n#define\t\tbTxIdleInterval\t\t\t\t\t0xffff\n#define\t\tbOFDMService\t\t\t\t\t0xffff0000\n#define\t\tbTxMACHeader\t\t\t\t\t0xffffffff\n#define\t\tbTxDataInit\t\t\t\t\t\t0xff\n#define\t\tbTxHTMode\t\t\t\t\t\t0x100\n#define\t\tbTxDataType\t\t\t\t\t0x30000\n#define\t\tbTxRandomSeed\t\t\t\t\t0xffffffff\n#define\t\tbCCKTxPreamble\t\t\t\t\t0x1\n#define\t\tbCCKTxSFD\t\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxSIG\t\t\t\t\t\t0xff\n#define\t\tbCCKTxService\t\t\t\t\t0xff00\n#define\t\tbCCKLengthExt\t\t\t\t\t0x8000\n#define\t\tbCCKTxLength\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxCRC16\t\t\t\t\t0xffff\n#define\t\tbCCKTxStatus\t\t\t\t\t0x1\n#define\t\tbOFDMTxStatus\t\t\t\t\t0x2\n\n#define\t\tIS_BB_REG_OFFSET_92S(_Offset)\t\t((_Offset >= 0x800) && (_Offset <= 0xfff))\n\n/* 2. Page8(0x800) */\n#define\t\tbRFMOD\t\t\t\t\t\t\t0x1\t/* Reg 0x800 rFPGA0_RFMOD */\n#define\t\tbJapanMode\t\t\t\t\t\t0x2\n#define\t\tbCCKTxSC\t\t\t\t\t\t0x30\n#define\t\tbCCKEn\t\t\t\t\t\t\t0x1000000\n#define\t\tbOFDMEn\t\t\t\t\t\t0x2000000\n\n#define\t\tbOFDMRxADCPhase           \t\t0x10000\t/* Useless now */\n#define\t\tbOFDMTxDACPhase\t\t0x40000\n#define\t\tbXATxAGC\t\t\t0x3f\n\n#define\t\tbAntennaSelect\t\t0x0300\n\n#define\t\tbXBTxAGC                  \t\t\t0xf00\t/* Reg 80c rFPGA0_TxGainStage */\n#define\t\tbXCTxAGC\t\t\t0xf000\n#define\t\tbXDTxAGC\t\t\t0xf0000\n\n#define\t\tbPAStart                  \t\t\t0xf0000000\t/* Useless now */\n#define\t\tbTRStart\t\t\t0x00f00000\n#define\t\tbRFStart\t\t\t0x0000f000\n#define\t\tbBBStart\t\t\t0x000000f0\n#define\t\tbBBCCKStart\t\t0x0000000f\n#define\t\tbPAEnd                    \t\t\t0xf          /* Reg0x814 */\n#define\t\tbTREnd\t\t\t0x0f000000\n#define\t\tbRFEnd\t\t\t0x000f0000\n#define\t\tbCCAMask                  \t\t\t0x000000f0   /* T2R */\n#define\t\tbR2RCCAMask\t\t0x00000f00\n#define\t\tbHSSI_R2TDelay\t\t0xf8000000\n#define\t\tbHSSI_T2RDelay\t\t0xf80000\n#define\t\tbContTxHSSI               \t\t0x400     /* chane gain at continue Tx */\n#define\t\tbIGFromCCK\t\t0x200\n#define\t\tbAGCAddress\t\t0x3f\n#define\t\tbRxHPTx\t\t\t0x7000\n#define\t\tbRxHPT2R\t\t\t0x38000\n#define\t\tbRxHPCCKIni\t\t0xc0000\n#define\t\tbAGCTxCode\t\t0xc00000\n#define\t\tbAGCRxCode\t\t0x300000\n\n#define\t\tb3WireDataLength          \t\t0x800\t/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */\n#define\t\tb3WireAddressLength\t\t0x400\n\n#define\t\tb3WireRFPowerDown         \t\t0x1\t/* Useless now\n * #define bHWSISelect\t\t0x8 */\n#define\t\tb5GPAPEPolarity\t\t0x40000000\n#define\t\tb2GPAPEPolarity\t\t0x80000000\n#define\t\tbRFSW_TxDefaultAnt\t\t0x3\n#define\t\tbRFSW_TxOptionAnt\t\t0x30\n#define\t\tbRFSW_RxDefaultAnt\t\t0x300\n#define\t\tbRFSW_RxOptionAnt\t\t0x3000\n#define\t\tbRFSI_3WireData\t\t0x1\n#define\t\tbRFSI_3WireClock\t\t0x2\n#define\t\tbRFSI_3WireLoad\t\t0x4\n#define\t\tbRFSI_3WireRW\t\t0x8\n#define\t\tbRFSI_3Wire\t\t\t0xf\n\n#define\t\tbRFSI_RFENV               \t\t0x10\t/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */\n\n#define\t\tbRFSI_TRSW                \t\t0x20\t/* Useless now */\n#define\t\tbRFSI_TRSWB\t\t0x40\n#define\t\tbRFSI_ANTSW\t\t0x100\n#define\t\tbRFSI_ANTSWB\t\t0x200\n#define\t\tbRFSI_PAPE\t\t\t0x400\n#define\t\tbRFSI_PAPE5G\t\t0x800\n#define\t\tbBandSelect\t\t\t0x1\n#define\t\tbHTSIG2_GI\t\t\t0x80\n#define\t\tbHTSIG2_Smoothing\t\t0x01\n#define\t\tbHTSIG2_Sounding\t\t0x02\n#define\t\tbHTSIG2_Aggreaton\t\t0x08\n#define\t\tbHTSIG2_STBC\t\t0x30\n#define\t\tbHTSIG2_AdvCoding\t\t0x40\n#define\t\tbHTSIG2_NumOfHTLTF\t0x300\n#define\t\tbHTSIG2_CRC8\t\t0x3fc\n#define\t\tbHTSIG1_MCS\t\t0x7f\n#define\t\tbHTSIG1_BandWidth\t\t0x80\n#define\t\tbHTSIG1_HTLength\t\t0xffff\n#define\t\tbLSIG_Rate\t\t\t0xf\n#define\t\tbLSIG_Reserved\t\t0x10\n#define\t\tbLSIG_Length\t\t0x1fffe\n#define\t\tbLSIG_Parity\t\t\t0x20\n#define\t\tbCCKRxPhase\t\t0x4\n\n#define\t\tbLSSIReadAddress          \t\t0x7f800000   /* T65 RF */\n\n#define\t\tbLSSIReadEdge             \t\t0x80000000   /* LSSI \"Read\" edge signal */\n\n#define\t\tbLSSIReadBackData         \t\t0xfffff\t\t/* T65 RF */\n\n#define\t\tbLSSIReadOKFlag           \t\t0x1000\t/* Useless now */\n#define\t\tbCCKSampleRate            \t\t0x8       /* 0: 44MHz, 1:88MHz      \t\t */\n#define\t\tbRegulator0Standby\t\t0x1\n#define\t\tbRegulatorPLLStandby\t\t0x2\n#define\t\tbRegulator1Standby\t\t0x4\n#define\t\tbPLLPowerUp\t\t0x8\n#define\t\tbDPLLPowerUp\t\t0x10\n#define\t\tbDA10PowerUp\t\t0x20\n#define\t\tbAD7PowerUp\t\t0x200\n#define\t\tbDA6PowerUp\t\t0x2000\n#define\t\tbXtalPowerUp\t\t0x4000\n#define\t\tb40MDClkPowerUP\t\t0x8000\n#define\t\tbDA6DebugMode\t\t0x20000\n#define\t\tbDA6Swing\t\t\t0x380000\n\n#define\t\tbADClkPhase               \t\t0x4000000\t/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */\n\n#define\t\tb80MClkDelay              \t\t0x18000000\t/* Useless */\n#define\t\tbAFEWatchDogEnable\t\t0x20000000\n\n#define\t\tbXtalCap01                \t\t\t0xc0000000\t/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */\n#define\t\tbXtalCap23\t\t\t0x3\n#define\t\tbXtalCap92x\t\t\t\t\t0x0f000000\n#define\t\tbXtalCap\t\t\t0x0f000000\n\n#define\t\tbIntDifClkEnable          \t\t0x400\t/* Useless */\n#define\t\tbExtSigClkEnable\t\t0x800\n#define\t\tbBandgapMbiasPowerUp\t0x10000\n#define\t\tbAD11SHGain\t\t0xc0000\n#define\t\tbAD11InputRange\t\t0x700000\n#define\t\tbAD11OPCurrent\t\t0x3800000\n#define\t\tbIPathLoopback\t\t0x4000000\n#define\t\tbQPathLoopback\t\t0x8000000\n#define\t\tbAFELoopback\t\t0x10000000\n#define\t\tbDA10Swing\t\t0x7e0\n#define\t\tbDA10Reverse\t\t0x800\n#define\t\tbDAClkSource\t\t0x1000\n#define\t\tbAD7InputRange\t\t0x6000\n#define\t\tbAD7Gain\t\t\t0x38000\n#define\t\tbAD7OutputCMMode\t\t0x40000\n#define\t\tbAD7InputCMMode\t\t0x380000\n#define\t\tbAD7Current\t\t\t0xc00000\n#define\t\tbRegulatorAdjust\t\t0x7000000\n#define\t\tbAD11PowerUpAtTx\t\t0x1\n#define\t\tbDA10PSAtTx\t\t0x10\n#define\t\tbAD11PowerUpAtRx\t\t0x100\n#define\t\tbDA10PSAtRx\t\t0x1000\n#define\t\tbCCKRxAGCFormat\t\t0x200\n#define\t\tbPSDFFTSamplepPoint\t\t0xc000\n#define\t\tbPSDAverageNum\t\t0x3000\n#define\t\tbIQPathControl\t\t0xc00\n#define\t\tbPSDFreq\t\t\t0x3ff\n#define\t\tbPSDAntennaPath\t\t0x30\n#define\t\tbPSDIQSwitch\t\t0x40\n#define\t\tbPSDRxTrigger\t\t0x400000\n#define\t\tbPSDTxTrigger\t\t0x80000000\n#define\t\tbPSDSineToneScale\t\t0x7f000000\n#define\t\tbPSDReport\t\t\t0xffff\n\n/* 3. Page9(0x900) */\n#define\t\tbOFDMTxSC                 \t\t0x30000000\t/* Useless */\n#define\t\tbCCKTxOn\t\t\t0x1\n#define\t\tbOFDMTxOn\t\t0x2\n#define\t\tbDebugPage                \t\t0xfff  /* reset debug page and also HWord, LWord */\n#define\t\tbDebugItem                \t\t0xff   /* reset debug page and LWord */\n#define\t\tbAntL\t\t\t0x10\n#define\t\tbAntNonHT\t\t\t\t0x100\n#define\t\tbAntHT1\t\t\t0x1000\n#define\t\tbAntHT2\t\t\t0x10000\n#define\t\tbAntHT1S1\t\t\t0x100000\n#define\t\tbAntNonHTS1\t\t0x1000000\n\n/* 4. PageA(0xA00) */\n#define\t\tbCCKBBMode\t\t\t\t0x3\t/* Useless */\n#define\t\tbCCKTxPowerSaving\t\t0x80\n#define\t\tbCCKRxPowerSaving\t\t0x40\n\n#define\t\tbCCKSideBand\t\t\t0x10\t/* Reg 0xa00 rCCK0_System 20/40 switch */\n\n#define\t\tbCCKScramble\t\t\t0x8\t/* Useless */\n#define\t\tbCCKAntDiversity\t\t0x8000\n#define\t\tbCCKCarrierRecovery\t\t0x4000\n#define\t\tbCCKTxRate\t\t\t\t0x3000\n#define\t\tbCCKDCCancel\t\t\t0x0800\n#define\t\tbCCKISICancel\t\t\t0x0400\n#define\t\tbCCKMatchFilter\t\t\t0x0200\n#define\t\tbCCKEqualizer\t\t\t0x0100\n#define\t\tbCCKPreambleDetect\t\t0x800000\n#define\t\tbCCKFastFalseCCA\t\t0x400000\n#define\t\tbCCKChEstStart\t\t\t0x300000\n#define\t\tbCCKCCACount\t\t\t0x080000\n#define\t\tbCCKcs_lim\t\t\t\t0x070000\n#define\t\tbCCKBistMode\t\t\t0x80000000\n#define\t\tbCCKCCAMask\t\t\t0x40000000\n#define\t\tbCCKTxDACPhase\t\t0x4\n#define\t\tbCCKRxADCPhase\t\t0x20000000   /* r_rx_clk */\n#define\t\tbCCKr_cp_mode0\t\t0x0100\n#define\t\tbCCKTxDCOffset\t\t\t0xf0\n#define\t\tbCCKRxDCOffset\t\t\t0xf\n#define\t\tbCCKCCAMode\t\t\t0xc000\n#define\t\tbCCKFalseCS_lim\t\t\t0x3f00\n#define\t\tbCCKCS_ratio\t\t\t0xc00000\n#define\t\tbCCKCorgBit_sel\t\t\t0x300000\n#define\t\tbCCKPD_lim\t\t\t\t0x0f0000\n#define\t\tbCCKNewCCA\t\t\t0x80000000\n#define\t\tbCCKRxHPofIG\t\t\t0x8000\n#define\t\tbCCKRxIG\t\t\t\t0x7f00\n#define\t\tbCCKLNAPolarity\t\t\t0x800000\n#define\t\tbCCKRx1stGain\t\t\t0x7f0000\n#define\t\tbCCKRFExtend\t\t\t0x20000000 /* CCK Rx Iinital gain polarity */\n#define\t\tbCCKRxAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKRxAGCSatCount\t\t0xe0\n#define\t\tbCCKRxRFSettle\t\t\t0x1f       /* AGCsamp_dly */\n#define\t\tbCCKFixedRxAGC\t\t\t0x8000\n/* #define bCCKRxAGCFormat\t\t0x4000 */   /* remove to HSSI register 0x824 */\n#define\t\tbCCKAntennaPolarity\t\t0x2000\n#define\t\tbCCKTxFilterType\t\t0x0c00\n#define\t\tbCCKRxAGCReportType\t0x0300\n#define\t\tbCCKRxDAGCEn\t\t\t0x80000000\n#define\t\tbCCKRxDAGCPeriod\t\t0x20000000\n#define\t\tbCCKRxDAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKTimingRecovery\t\t0x800000\n#define\t\tbCCKTxC0\t\t\t\t0x3f0000\n#define\t\tbCCKTxC1\t\t\t\t0x3f000000\n#define\t\tbCCKTxC2\t\t\t\t0x3f\n#define\t\tbCCKTxC3\t\t\t\t0x3f00\n#define\t\tbCCKTxC4\t\t\t\t0x3f0000\n#define\t\tbCCKTxC5\t\t\t\t0x3f000000\n#define\t\tbCCKTxC6\t\t\t\t0x3f\n#define\t\tbCCKTxC7\t\t\t\t0x3f00\n#define\t\tbCCKDebugPort\t\t\t0xff0000\n#define\t\tbCCKDACDebug\t\t\t0x0f000000\n#define\t\tbCCKFalseAlarmEnable\t0x8000\n#define\t\tbCCKFalseAlarmRead\t\t0x4000\n#define\t\tbCCKTRSSI\t\t\t\t0x7f\n#define\t\tbCCKRxAGCReport\t\t0xfe\n#define\t\tbCCKRxReport_AntSel\t0x80000000\n#define\t\tbCCKRxReport_MFOff\t\t0x40000000\n#define\t\tbCCKRxRxReport_SQLoss\t0x20000000\n#define\t\tbCCKRxReport_Pktloss\t0x10000000\n#define\t\tbCCKRxReport_Lockedbit\t0x08000000\n#define\t\tbCCKRxReport_RateError\t0x04000000\n#define\t\tbCCKRxReport_RxRate\t0x03000000\n#define\t\tbCCKRxFACounterLower\t0xff\n#define\t\tbCCKRxFACounterUpper\t0xff000000\n#define\t\tbCCKRxHPAGCStart\t\t0xe000\n#define\t\tbCCKRxHPAGCFinal\t\t0x1c00\n#define\t\tbCCKRxFalseAlarmEnable\t0x8000\n#define\t\tbCCKFACounterFreeze\t0x4000\n#define\t\tbCCKTxPathSel\t\t\t0x10000000\n#define\t\tbCCKDefaultRxPath\t\t0xc000000\n#define\t\tbCCKOptionRxPath\t\t0x3000000\n\n/* 5. PageC(0xC00) */\n#define\t\tbNumOfSTF\t\t\t\t0x3\t/* Useless */\n#define\t\tbShift_L\t\t\t\t\t0xc0\n#define\t\tbGI_TH\t\t\t\t\t0xc\n#define\t\tbRxPathA\t\t\t\t0x1\n#define\t\tbRxPathB\t\t\t\t0x2\n#define\t\tbRxPathC\t\t\t\t0x4\n#define\t\tbRxPathD\t\t\t\t0x8\n#define\t\tbTxPathA\t\t\t\t0x1\n#define\t\tbTxPathB\t\t\t\t0x2\n#define\t\tbTxPathC\t\t\t\t0x4\n#define\t\tbTxPathD\t\t\t\t0x8\n#define\t\tbTRSSIFreq\t\t\t\t0x200\n#define\t\tbADCBackoff\t\t\t\t0x3000\n#define\t\tbDFIRBackoff\t\t\t0xc000\n#define\t\tbTRSSILatchPhase\t\t0x10000\n#define\t\tbRxIDCOffset\t\t\t0xff\n#define\t\tbRxQDCOffset\t\t\t0xff00\n#define\t\tbRxDFIRMode\t\t\t0x1800000\n#define\t\tbRxDCNFType\t\t\t0xe000000\n#define\t\tbRXIQImb_A\t\t\t\t0x3ff\n#define\t\tbRXIQImb_B\t\t\t\t0xfc00\n#define\t\tbRXIQImb_C\t\t\t\t0x3f0000\n#define\t\tbRXIQImb_D\t\t\t\t0xffc00000\n#define\t\tbDC_dc_Notch\t\t\t0x60000\n#define\t\tbRxNBINotch\t\t\t0x1f000000\n#define\t\tbPD_TH\t\t\t\t\t0xf\n#define\t\tbPD_TH_Opt2\t\t\t0xc000\n#define\t\tbPWED_TH\t\t\t\t0x700\n#define\t\tbIfMF_Win_L\t\t\t0x800\n#define\t\tbPD_Option\t\t\t\t0x1000\n#define\t\tbMF_Win_L\t\t\t\t0xe000\n#define\t\tbBW_Search_L\t\t\t0x30000\n#define\t\tbwin_enh_L\t\t\t\t0xc0000\n#define\t\tbBW_TH\t\t\t\t\t0x700000\n#define\t\tbED_TH2\t\t\t\t0x3800000\n#define\t\tbBW_option\t\t\t\t0x4000000\n#define\t\tbRatio_TH\t\t\t\t0x18000000\n#define\t\tbWindow_L\t\t\t\t0xe0000000\n#define\t\tbSBD_Option\t\t\t\t0x1\n#define\t\tbFrame_TH\t\t\t\t0x1c\n#define\t\tbFS_Option\t\t\t\t0x60\n#define\t\tbDC_Slope_check\t\t0x80\n#define\t\tbFGuard_Counter_DC_L\t0xe00\n#define\t\tbFrame_Weight_Short\t0x7000\n#define\t\tbSub_Tune\t\t\t\t0xe00000\n#define\t\tbFrame_DC_Length\t\t0xe000000\n#define\t\tbSBD_start_offset\t\t0x30000000\n#define\t\tbFrame_TH_2\t\t\t0x7\n#define\t\tbFrame_GI2_TH\t\t\t0x38\n#define\t\tbGI2_Sync_en\t\t\t0x40\n#define\t\tbSarch_Short_Early\t\t0x300\n#define\t\tbSarch_Short_Late\t\t0xc00\n#define\t\tbSarch_GI2_Late\t\t0x70000\n#define\t\tbCFOAntSum\t\t\t\t0x1\n#define\t\tbCFOAcc\t\t\t\t0x2\n#define\t\tbCFOStartOffset\t\t\t0xc\n#define\t\tbCFOLookBack\t\t\t0x70\n#define\t\tbCFOSumWeight\t\t\t0x80\n#define\t\tbDAGCEnable\t\t\t0x10000\n#define\t\tbTXIQImb_A\t\t\t\t0x3ff\n#define\t\tbTXIQImb_B\t\t\t\t0xfc00\n#define\t\tbTXIQImb_C\t\t\t\t0x3f0000\n#define\t\tbTXIQImb_D\t\t\t\t0xffc00000\n#define\t\tbTxIDCOffset\t\t\t0xff\n#define\t\tbTxQDCOffset\t\t\t0xff00\n#define\t\tbTxDFIRMode\t\t\t0x10000\n#define\t\tbTxPesudoNoiseOn\t\t0x4000000\n#define\t\tbTxPesudoNoise_A\t\t0xff\n#define\t\tbTxPesudoNoise_B\t\t0xff00\n#define\t\tbTxPesudoNoise_C\t\t0xff0000\n#define\t\tbTxPesudoNoise_D\t\t0xff000000\n#define\t\tbCCADropOption\t\t\t0x20000\n#define\t\tbCCADropThres\t\t\t0xfff00000\n#define\t\tbEDCCA_H\t\t\t\t0xf\n#define\t\tbEDCCA_L\t\t\t\t0xf0\n#define\t\tbLambda_ED\t\t\t0x300\n#define\t\tbRxInitialGain\t\t\t0x7f\n#define\t\tbRxAntDivEn\t\t\t\t0x80\n#define\t\tbRxAGCAddressForLNA\t0x7f00\n#define\t\tbRxHighPowerFlow\t\t0x8000\n#define\t\tbRxAGCFreezeThres\t\t0xc0000\n#define\t\tbRxFreezeStep_AGC1\t0x300000\n#define\t\tbRxFreezeStep_AGC2\t0xc00000\n#define\t\tbRxFreezeStep_AGC3\t0x3000000\n#define\t\tbRxFreezeStep_AGC0\t0xc000000\n#define\t\tbRxRssi_Cmp_En\t\t\t0x10000000\n#define\t\tbRxQuickAGCEn\t\t\t0x20000000\n#define\t\tbRxAGCFreezeThresMode\t0x40000000\n#define\t\tbRxOverFlowCheckType\t0x80000000\n#define\t\tbRxAGCShift\t\t\t\t0x7f\n#define\t\tbTRSW_Tri_Only\t\t\t0x80\n#define\t\tbPowerThres\t\t\t0x300\n#define\t\tbRxAGCEn\t\t\t\t0x1\n#define\t\tbRxAGCTogetherEn\t\t0x2\n#define\t\tbRxAGCMin\t\t\t\t0x4\n#define\t\tbRxHP_Ini\t\t\t\t0x7\n#define\t\tbRxHP_TRLNA\t\t\t0x70\n#define\t\tbRxHP_RSSI\t\t\t\t0x700\n#define\t\tbRxHP_BBP1\t\t\t\t0x7000\n#define\t\tbRxHP_BBP2\t\t\t\t0x70000\n#define\t\tbRxHP_BBP3\t\t\t\t0x700000\n#define\t\tbRSSI_H\t\t\t\t\t0x7f0000     /* the threshold for high power */\n#define\t\tbRSSI_Gen\t\t\t\t0x7f000000   /* the threshold for ant diversity */\n#define\t\tbRxSettle_TRSW\t\t\t0x7\n#define\t\tbRxSettle_LNA\t\t\t0x38\n#define\t\tbRxSettle_RSSI\t\t\t0x1c0\n#define\t\tbRxSettle_BBP\t\t\t0xe00\n#define\t\tbRxSettle_RxHP\t\t\t0x7000\n#define\t\tbRxSettle_AntSW_RSSI\t0x38000\n#define\t\tbRxSettle_AntSW\t\t0xc0000\n#define\t\tbRxProcessTime_DAGC\t0x300000\n#define\t\tbRxSettle_HSSI\t\t\t0x400000\n#define\t\tbRxProcessTime_BBPPW\t0x800000\n#define\t\tbRxAntennaPowerShift\t0x3000000\n#define\t\tbRSSITableSelect\t\t0xc000000\n#define\t\tbRxHP_Final\t\t\t\t0x7000000\n#define\t\tbRxHTSettle_BBP\t\t\t0x7\n#define\t\tbRxHTSettle_HSSI\t\t0x8\n#define\t\tbRxHTSettle_RxHP\t\t0x70\n#define\t\tbRxHTSettle_BBPPW\t\t0x80\n#define\t\tbRxHTSettle_Idle\t\t0x300\n#define\t\tbRxHTSettle_Reserved\t0x1c00\n#define\t\tbRxHTRxHPEn\t\t\t0x8000\n#define\t\tbRxHTAGCFreezeThres\t0x30000\n#define\t\tbRxHTAGCTogetherEn\t0x40000\n#define\t\tbRxHTAGCMin\t\t\t0x80000\n#define\t\tbRxHTAGCEn\t\t\t\t0x100000\n#define\t\tbRxHTDAGCEn\t\t\t0x200000\n#define\t\tbRxHTRxHP_BBP\t\t\t0x1c00000\n#define\t\tbRxHTRxHP_Final\t\t0xe0000000\n#define\t\tbRxPWRatioTH\t\t\t0x3\n#define\t\tbRxPWRatioEn\t\t\t0x4\n#define\t\tbRxMFHold\t\t\t\t0x3800\n#define\t\tbRxPD_Delay_TH1\t\t0x38\n#define\t\tbRxPD_Delay_TH2\t\t0x1c0\n#define\t\tbRxPD_DC_COUNT_MAX\t0x600\n/* #define bRxMF_Hold               0x3800 */\n#define\t\tbRxPD_Delay_TH\t\t\t0x8000\n#define\t\tbRxProcess_Delay\t\t0xf0000\n#define\t\tbRxSearchrange_GI2_Early\t0x700000\n#define\t\tbRxFrame_Guard_Counter_L\t0x3800000\n#define\t\tbRxSGI_Guard_L\t\t\t0xc000000\n#define\t\tbRxSGI_Search_L\t\t0x30000000\n#define\t\tbRxSGI_TH\t\t\t\t0xc0000000\n#define\t\tbDFSCnt0\t\t\t\t0xff\n#define\t\tbDFSCnt1\t\t\t\t0xff00\n#define\t\tbDFSFlag\t\t\t\t0xf0000\n#define\t\tbMFWeightSum\t\t\t0x300000\n#define\t\tbMinIdxTH\t\t\t\t0x7f000000\n#define\t\tbDAFormat\t\t\t\t0x40000\n#define\t\tbTxChEmuEnable\t\t0x01000000\n#define\t\tbTRSWIsolation_A\t\t0x7f\n#define\t\tbTRSWIsolation_B\t\t0x7f00\n#define\t\tbTRSWIsolation_C\t\t0x7f0000\n#define\t\tbTRSWIsolation_D\t\t0x7f000000\n#define\t\tbExtLNAGain\t\t\t\t0x7c00\n\n/* 6. PageE(0xE00) */\n#define\t\tbSTBCEn\t\t\t\t0x4\t/* Useless */\n#define\t\tbAntennaMapping\t\t0x10\n#define\t\tbNss\t\t\t\t\t0x20\n#define\t\tbCFOAntSumD\t\t\t0x200\n#define\t\tbPHYCounterReset\t\t0x8000000\n#define\t\tbCFOReportGet\t\t\t0x4000000\n#define\t\tbOFDMContinueTx\t\t0x10000000\n#define\t\tbOFDMSingleCarrier\t\t0x20000000\n#define\t\tbOFDMSingleTone\t\t0x40000000\n/* #define bRxPath1                 0x01 */\n/* #define bRxPath2                 0x02 */\n/* #define bRxPath3                 0x04 */\n/* #define bRxPath4                 0x08 */\n/* #define bTxPath1                 0x10 */\n/* #define bTxPath2                 0x20 */\n#define\t\tbHTDetect\t\t\t0x100\n#define\t\tbCFOEn\t\t\t\t0x10000\n#define\t\tbCFOValue\t\t\t0xfff00000\n#define\t\tbSigTone_Re\t\t0x3f\n#define\t\tbSigTone_Im\t\t0x7f00\n#define\t\tbCounter_CCA\t\t0xffff\n#define\t\tbCounter_ParityFail\t0xffff0000\n#define\t\tbCounter_RateIllegal\t\t0xffff\n#define\t\tbCounter_CRC8Fail\t0xffff0000\n#define\t\tbCounter_MCSNoSupport\t0xffff\n#define\t\tbCounter_FastSync\t0xffff\n#define\t\tbShortCFO\t\t\t0xfff\n#define\t\tbShortCFOTLength\t12   /* total */\n#define\t\tbShortCFOFLength\t11   /* fraction */\n#define\t\tbLongCFO\t\t\t0x7ff\n#define\t\tbLongCFOTLength\t11\n#define\t\tbLongCFOFLength\t11\n#define\t\tbTailCFO\t\t\t0x1fff\n#define\t\tbTailCFOTLength\t\t13\n#define\t\tbTailCFOFLength\t\t12\n#define\t\tbmax_en_pwdB\t\t0xffff\n#define\t\tbCC_power_dB\t\t0xffff0000\n#define\t\tbnoise_pwdB\t\t0xffff\n#define\t\tbPowerMeasTLength\t10\n#define\t\tbPowerMeasFLength\t3\n#define\t\tbRx_HT_BW\t\t\t0x1\n#define\t\tbRxSC\t\t\t\t0x6\n#define\t\tbRx_HT\t\t\t\t0x8\n#define\t\tbNB_intf_det_on\t\t0x1\n#define\t\tbIntf_win_len_cfg\t0x30\n#define\t\tbNB_Intf_TH_cfg\t\t0x1c0\n#define\t\tbRFGain\t\t\t\t0x3f\n#define\t\tbTableSel\t\t\t0x40\n#define\t\tbTRSW\t\t\t\t0x80\n#define\t\tbRxSNR_A\t\t\t0xff\n#define\t\tbRxSNR_B\t\t\t0xff00\n#define\t\tbRxSNR_C\t\t\t0xff0000\n#define\t\tbRxSNR_D\t\t\t0xff000000\n#define\t\tbSNREVMTLength\t\t8\n#define\t\tbSNREVMFLength\t\t1\n#define\t\tbCSI1st\t\t\t\t0xff\n#define\t\tbCSI2nd\t\t\t\t0xff00\n#define\t\tbRxEVM1st\t\t\t0xff0000\n#define\t\tbRxEVM2nd\t\t\t0xff000000\n#define\t\tbSIGEVM\t\t\t0xff\n#define\t\tbPWDB\t\t\t\t0xff00\n#define\t\tbSGIEN\t\t\t\t0x10000\n\n#define\t\tbSFactorQAM1\t\t0xf\t/* Useless */\n#define\t\tbSFactorQAM2\t\t0xf0\n#define\t\tbSFactorQAM3\t\t0xf00\n#define\t\tbSFactorQAM4\t\t0xf000\n#define\t\tbSFactorQAM5\t\t0xf0000\n#define\t\tbSFactorQAM6\t\t0xf0000\n#define\t\tbSFactorQAM7\t\t0xf00000\n#define\t\tbSFactorQAM8\t\t0xf000000\n#define\t\tbSFactorQAM9\t\t0xf0000000\n#define\t\tbCSIScheme\t\t\t0x100000\n\n#define\t\tbNoiseLvlTopSet\t\t0x3\t/* Useless */\n#define\t\tbChSmooth\t\t\t0x4\n#define\t\tbChSmoothCfg1\t\t0x38\n#define\t\tbChSmoothCfg2\t\t0x1c0\n#define\t\tbChSmoothCfg3\t\t0xe00\n#define\t\tbChSmoothCfg4\t\t0x7000\n#define\t\tbMRCMode\t\t\t0x800000\n#define\t\tbTHEVMCfg\t\t\t0x7000000\n\n#define\t\tbLoopFitType\t\t0x1\t/* Useless */\n#define\t\tbUpdCFO\t\t\t0x40\n#define\t\tbUpdCFOOffData\t\t0x80\n#define\t\tbAdvUpdCFO\t\t\t0x100\n#define\t\tbAdvTimeCtrl\t\t0x800\n#define\t\tbUpdClko\t\t\t0x1000\n#define\t\tbFC\t\t\t\t\t0x6000\n#define\t\tbTrackingMode\t\t0x8000\n#define\t\tbPhCmpEnable\t\t0x10000\n#define\t\tbUpdClkoLTF\t\t0x20000\n#define\t\tbComChCFO\t\t\t0x40000\n#define\t\tbCSIEstiMode\t\t0x80000\n#define\t\tbAdvUpdEqz\t\t\t0x100000\n#define\t\tbUChCfg\t\t\t\t0x7000000\n#define\t\tbUpdEqz\t\t\t0x8000000\n\n/* Rx Pseduo noise */\n#define\t\tbRxPesudoNoiseOn\t\t0x20000000\t/* Useless */\n#define\t\tbRxPesudoNoise_A\t\t0xff\n#define\t\tbRxPesudoNoise_B\t\t0xff00\n#define\t\tbRxPesudoNoise_C\t\t0xff0000\n#define\t\tbRxPesudoNoise_D\t\t0xff000000\n#define\t\tbPesudoNoiseState_A\t0xffff\n#define\t\tbPesudoNoiseState_B\t0xffff0000\n#define\t\tbPesudoNoiseState_C\t0xffff\n#define\t\tbPesudoNoiseState_D\t0xffff0000\n\n/* 7. RF Register\n * Zebra1 */\n#define\t\tbZebra1_HSSIEnable\t\t0x8\t\t/* Useless */\n#define\t\tbZebra1_TRxControl\t\t0xc00\n#define\t\tbZebra1_TRxGainSetting\t0x07f\n#define\t\tbZebra1_RxCorner\t\t0xc00\n#define\t\tbZebra1_TxChargePump\t0x38\n#define\t\tbZebra1_RxChargePump\t0x7\n#define\t\tbZebra1_ChannelNum\t0xf80\n#define\t\tbZebra1_TxLPFBW\t\t0x400\n#define\t\tbZebra1_RxLPFBW\t\t0x600\n\n/* Zebra4 */\n#define\t\tbRTL8256RegModeCtrl1\t0x100\t/* Useless */\n#define\t\tbRTL8256RegModeCtrl0\t0x40\n#define\t\tbRTL8256_TxLPFBW\t\t0x18\n#define\t\tbRTL8256_RxLPFBW\t\t0x600\n\n/* RTL8258 */\n#define\t\tbRTL8258_TxLPFBW\t\t0xc\t/* Useless */\n#define\t\tbRTL8258_RxLPFBW\t\t0xc00\n#define\t\tbRTL8258_RSSILPFBW\t0xc0\n\n\n/*\n * Other Definition\n *   */\n\n/* byte endable for sb_write */\n#define\t\tbByte0\t\t\t\t0x1\t/* Useless */\n#define\t\tbByte1\t\t\t\t0x2\n#define\t\tbByte2\t\t\t\t0x4\n#define\t\tbByte3\t\t\t\t0x8\n#define\t\tbWord0\t\t\t\t0x3\n#define\t\tbWord1\t\t\t\t0xc\n#define\t\tbDWord\t\t\t\t0xf\n\n/* for PutRegsetting & GetRegSetting BitMask */\n#define\t\tbMaskByte0\t\t\t0xff\t/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */\n#define\t\tbMaskByte1\t\t\t0xff00\n#define\t\tbMaskByte2\t\t\t0xff0000\n#define\t\tbMaskByte3\t\t\t0xff000000\n#define\t\tbMaskHWord\t\t0xffff0000\n#define\t\tbMaskLWord\t\t\t0x0000ffff\n#define\t\tbMaskDWord\t\t0xffffffff\n#define\t\tbMaskH3Bytes\t\t0xffffff00\n#define\t\tbMask12Bits\t\t\t0xfff\n#define\t\tbMaskH4Bits\t\t\t0xf0000000\n#define\t\tbMaskOFDM_D\t\t0xffc00000\n#define\t\tbMaskCCK\t\t\t0x3f3f3f3f\n\n\n#define\t\tbEnable\t\t\t0x1\t/* Useless */\n#define\t\tbDisable\t\t0x0\n\n#define\t\tLeftAntenna\t\t0x0\t/* Useless */\n#define\t\tRightAntenna\t0x1\n\n#define\t\ttCheckTxStatus\t\t500   /* 500ms */ /* Useless */\n#define\t\ttUpdateRxCounter\t100   /* 100ms */\n\n#define\t\trateCCK\t\t0\t/* Useless */\n#define\t\trateOFDM\t1\n#define\t\trateHT\t\t2\n\n/* define Register-End */\n#define\t\tbPMAC_End\t\t\t0x1ff\t/* Useless */\n#define\t\tbFPGAPHY0_End\t\t0x8ff\n#define\t\tbFPGAPHY1_End\t\t0x9ff\n#define\t\tbCCKPHY0_End\t\t0xaff\n#define\t\tbOFDMPHY0_End\t\t0xcff\n#define\t\tbOFDMPHY1_End\t\t0xdff\n\n/* define max debug item in each debug page\n * #define bMaxItem_FPGA_PHY0        0x9\n * #define bMaxItem_FPGA_PHY1        0x3\n * #define bMaxItem_PHY_11B          0x16\n * #define bMaxItem_OFDM_PHY0        0x29\n * #define bMaxItem_OFDM_PHY1        0x0 */\n\n#define\t\tbPMACControl\t\t0x0\t\t/* Useless */\n#define\t\tbWMACControl\t\t0x1\n#define\t\tbWNICControl\t\t0x2\n\n#define\t\tPathA\t\t\t0x0\t/* Useless */\n#define\t\tPathB\t\t\t0x1\n#define\t\tPathC\t\t\t0x2\n#define\t\tPathD\t\t\t0x3\n\n#endif\n"
  },
  {
    "path": "include/Hal8723BPwrSeq.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef REALTEK_POWER_SEQUENCE_8723B\n#define REALTEK_POWER_SEQUENCE_8723B\n\n#include \"HalPwrSeqCmd.h\"\n\n/*\n\tCheck document WM-20130815-JackieLau-RTL8723B_Power_Architecture v08.vsd\n\tThere are 6 HW Power States:\n\t0: POFF--Power Off\n\t1: PDN--Power Down\n\t2: CARDEMU--Card Emulation\n\t3: ACT--Active Mode\n\t4: LPS--Low Power State\n\t5: SUS--Suspend\n\n\tThe transision from different states are defined below\n\tTRANS_CARDEMU_TO_ACT\n\tTRANS_ACT_TO_CARDEMU\n\tTRANS_CARDEMU_TO_SUS\n\tTRANS_SUS_TO_CARDEMU\n\tTRANS_CARDEMU_TO_PDN\n\tTRANS_ACT_TO_LPS\n\tTRANS_LPS_TO_ACT\n\n\tTRANS_END\n*/\n#define\tRTL8723B_TRANS_CARDEMU_TO_ACT_STEPS\t26\n#define\tRTL8723B_TRANS_ACT_TO_CARDEMU_STEPS\t15\n#define\tRTL8723B_TRANS_CARDEMU_TO_SUS_STEPS\t15\n#define\tRTL8723B_TRANS_SUS_TO_CARDEMU_STEPS\t15\n#define\tRTL8723B_TRANS_CARDEMU_TO_PDN_STEPS\t15\n#define\tRTL8723B_TRANS_PDN_TO_CARDEMU_STEPS\t15\n#define\tRTL8723B_TRANS_ACT_TO_LPS_STEPS\t\t15\n#define\tRTL8723B_TRANS_LPS_TO_ACT_STEPS\t\t15\n#define\tRTL8723B_TRANS_ACT_TO_SWLPS_STEPS\t\t22\n#define\tRTL8723B_TRANS_SWLPS_TO_ACT_STEPS\t\t15\n#define\tRTL8723B_TRANS_END_STEPS\t\t1\n\n\n#define RTL8723B_TRANS_CARDEMU_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \\\n\t{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/\t\\\n\t{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \\\n\t{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/\t\\\n\t{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/\t\\\n\t{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/\t\\\n\t{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/\t\\\n\t{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\\\n\t{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\\\n\t{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\\\n\t{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\\\n\t{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\\\n\t{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\\\n\t{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\\\n\n\n#define RTL8723B_TRANS_ACT_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/\t\\\n\t{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/\t\\\n\t{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\\\n\t{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \\\n\t{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\\\n\n\n#define RTL8723B_TRANS_CARDEMU_TO_SUS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/\n\n#define RTL8723B_TRANS_SUS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\n\n#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/\t\\\n\t{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/\n\n#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\\\n\t{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/\n\n\n#define RTL8723B_TRANS_CARDEMU_TO_PDN\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/\n\n#define RTL8723B_TRANS_PDN_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/\n\n#define RTL8723B_TRANS_ACT_TO_LPS\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/\t\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/\t\\\n\t{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/\t\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/\t\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\t\\\n\t{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/\t\\\n\t{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/\t\\\n\n\n#define RTL8723B_TRANS_LPS_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\\\n\t{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\\\n\t{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.\t0x08[4] = 0\t\t switch TSF to 40M*/\\\n\t{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\\\n\t{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.\t0x29[7:6] = 2b'00\t enable BB clock*/\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.\t0x101[1] = 1*/\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.\t0x100[7:0] = 0xFF\t enable WMAC TRX*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.\t0x02[1:0] = 2b'11\t enable BB macro*/\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.\t0x522 = 0*/\n\n\n#define RTL8723B_TRANS_ACT_TO_SWLPS\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable 32 K source*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/\t\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/\t\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*disable security engine*/\t\\\n\t{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x40},/*When driver enter Sus/ Disable, enable LOP for BT*/\t\\\n\t{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TSF*/\t\\\n\t{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*Reset MCUFWDL register*/\t\\\n\t{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/\t\\\n\t{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*Reset CPU IO Wrapper*/\t\\\n\t{0x0287, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*polling RXFF packet number = 0 */\t\\\n\t{0x0286, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/*polling RXDMA idle */\t\\\n\t{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Clear FW RPWM interrupt */\\\n\t{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW RPWM interrupt source*/\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*switch TSF to 32K*/\\\n\t{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF stable*/\\\n\t{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW LPS*/\t\\\n\t{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/*polling FW LPS ready */\n\n\n#define RTL8723B_TRANS_SWLPS_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*switch TSF to 32K*/\\\n\t{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.\t0x101[1] = 1, enable security engine*/\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.\t0x100[7:0] = 0xFF\t enable WMAC TRX*/\\\n\t{0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x09}, /*.\treset MAC rx state machine*/\\\n\t{0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x86}, /*.\treset MAC rx state machine*/\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/\t\\\n\t{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/\t\\\n\t{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/\t\\\n\t{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/\t\\\n\t{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*.\t0x02[1:0] = 2b'11\t enable BB macro*/\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.\t0x522 = 0*/\n\n#define RTL8723B_TRANS_END\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},\n\n\n\textern WLAN_PWR_CFG rtl8723B_power_on_flow[RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723B_radio_off_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723B_card_disable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723B_card_enable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723B_suspend_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723B_resume_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723B_hwpdn_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723B_enter_lps_flow[RTL8723B_TRANS_ACT_TO_LPS_STEPS + RTL8723B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723B_leave_lps_flow[RTL8723B_TRANS_LPS_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723B_enter_swlps_flow[RTL8723B_TRANS_ACT_TO_SWLPS_STEPS + RTL8723B_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723B_leave_swlps_flow[RTL8723B_TRANS_SWLPS_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS];\n#endif\n"
  },
  {
    "path": "include/Hal8723DPhyCfg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8723DPHYCFG_H__\n#define __INC_HAL8723DPHYCFG_H__\n\n/*--------------------------Define Parameters-------------------------------*/\n#define LOOP_LIMIT\t\t\t\t5\n#define MAX_STALL_TIME\t\t\t50\t\t/* us */\n#define AntennaDiversityValue\t0x80\t/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */\n#define MAX_TXPWR_IDX_NMODE_92S\t63\n#define Reset_Cnt_Limit\t\t\t3\n\n#ifdef CONFIG_PCI_HCI\n\t#define MAX_AGGR_NUM\t0x0B\n#else\n\t#define MAX_AGGR_NUM\t0x07\n#endif /* CONFIG_PCI_HCI */\n\n\n/*--------------------------Define Parameters End-------------------------------*/\n\n\n/*------------------------------Define structure----------------------------*/\n\n/*------------------------------Define structure End----------------------------*/\n\n/*--------------------------Exported Function prototype---------------------*/\nu32\nPHY_QueryBBReg_8723D(\n\t\tPADAPTER\tAdapter,\n\t\tu32\t\tRegAddr,\n\t\tu32\t\tBitMask\n);\n\nvoid\nPHY_SetBBReg_8723D(\n\t\tPADAPTER\tAdapter,\n\t\tu32\t\tRegAddr,\n\t\tu32\t\tBitMask,\n\t\tu32\t\tData\n);\n\nu32\nPHY_QueryRFReg_8723D(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tRegAddr,\n\t\tu32\t\t\t\tBitMask\n);\n\nvoid\nPHY_SetRFReg_8723D(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tRegAddr,\n\t\tu32\t\t\t\tBitMask,\n\t\tu32\t\t\t\tData\n);\n\n/* MAC/BB/RF HAL config */\nint PHY_BBConfig8723D(PADAPTER\tAdapter);\n\nint PHY_RFConfig8723D(PADAPTER\tAdapter);\n\ns32 PHY_MACConfig8723D(PADAPTER padapter);\n\nint\nPHY_ConfigRFWithParaFile_8723D(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu8\t\t\t\t*pFileName,\n\tenum rf_path\t\t\t\teRFPath\n);\n\nvoid\nPHY_SetTxPowerIndex_8723D(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu32\t\t\t\t\tPowerIndex,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate\n);\n\nu8\nPHY_GetTxPowerIndex_8723D(\n\t\tPADAPTER\t\t\tpAdapter,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate,\n\t\tu8\t\t\t\t\tBandWidth,\n\t\tu8\t\t\t\t\tChannel,\n\tstruct txpwr_idx_comp *tic\n);\n\nvoid\nPHY_SetTxPowerLevel8723D(\n\t\tPADAPTER\t\tAdapter,\n\t\tu8\t\t\tchannel\n);\n\nvoid\nPHY_SetSwChnlBWMode8723D(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu8\t\t\t\t\tchannel,\n\t\tenum channel_width\tBandwidth,\n\t\tu8\t\t\t\t\tOffset40,\n\t\tu8\t\t\t\t\tOffset80\n);\n\nvoid phy_set_rf_path_switch_8723d(\n\t\tstruct dm_struct\t\t*phydm,\n\t\tbool\t\tbMain\n);\n/*--------------------------Exported Function prototype End---------------------*/\n\n#endif\n"
  },
  {
    "path": "include/Hal8723DPhyReg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8723DPHYREG_H__\n#define __INC_HAL8723DPHYREG_H__\n\n#define\t\trSYM_WLBT_PAPE_SEL\t\t0x64\n/*\n * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00\n * 3. RF register 0x00-2E\n * 4. Bit Mask for BB/RF register\n * 5. Other definition for BB/RF R/W\n *   */\n\n\n/*\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 1. Page1(0x100)\n *   */\n#define\t\trPMAC_Reset\t\t\t\t\t0x100\n#define\t\trPMAC_TxStart\t\t\t\t\t0x104\n#define\t\trPMAC_TxLegacySIG\t\t\t\t0x108\n#define\t\trPMAC_TxHTSIG1\t\t\t\t0x10c\n#define\t\trPMAC_TxHTSIG2\t\t\t\t0x110\n#define\t\trPMAC_PHYDebug\t\t\t\t0x114\n#define\t\trPMAC_TxPacketNum\t\t\t\t0x118\n#define\t\trPMAC_TxIdle\t\t\t\t\t0x11c\n#define\t\trPMAC_TxMACHeader0\t\t\t0x120\n#define\t\trPMAC_TxMACHeader1\t\t\t0x124\n#define\t\trPMAC_TxMACHeader2\t\t\t0x128\n#define\t\trPMAC_TxMACHeader3\t\t\t0x12c\n#define\t\trPMAC_TxMACHeader4\t\t\t0x130\n#define\t\trPMAC_TxMACHeader5\t\t\t0x134\n#define\t\trPMAC_TxDataType\t\t\t\t0x138\n#define\t\trPMAC_TxRandomSeed\t\t\t0x13c\n#define\t\trPMAC_CCKPLCPPreamble\t\t\t0x140\n#define\t\trPMAC_CCKPLCPHeader\t\t\t0x144\n#define\t\trPMAC_CCKCRC16\t\t\t\t0x148\n#define\t\trPMAC_OFDMRxCRC32OK\t\t\t0x170\n#define\t\trPMAC_OFDMRxCRC32Er\t\t\t0x174\n#define\t\trPMAC_OFDMRxParityEr\t\t\t0x178\n#define\t\trPMAC_OFDMRxCRC8Er\t\t\t0x17c\n#define\t\trPMAC_CCKCRxRC16Er\t\t\t0x180\n#define\t\trPMAC_CCKCRxRC32Er\t\t\t0x184\n#define\t\trPMAC_CCKCRxRC32OK\t\t\t0x188\n#define\t\trPMAC_TxStatus\t\t\t\t\t0x18c\n\n/*\n * 2. Page2(0x200)\n *\n * The following two definition are only used for USB interface. */\n#define\t\tRF_BB_CMD_ADDR\t\t\t\t0x02c0\t/* RF/BB read/write command address. */\n#define\t\tRF_BB_CMD_DATA\t\t\t\t0x02c4\t/* RF/BB read/write command data. */\n\n/*\n * 3. Page8(0x800)\n *   */\n#define\t\trFPGA0_RFMOD\t\t\t\t0x800\t/* RF mode & CCK TxSC // RF BW Setting?? */\n\n#define\t\trFPGA0_TxInfo\t\t\t\t0x804\t/* Status report?? */\n#define\t\trFPGA0_PSDFunction\t\t\t0x808\n\n#define\t\trFPGA0_TxGainStage\t\t\t0x80c\t/* Set TX PWR init gain? */\n\n#define\t\trFPGA0_RFTiming1\t\t\t0x810\t/* Useless now */\n#define\t\trFPGA0_RFTiming2\t\t\t0x814\n\n#define\t\trFPGA0_XA_HSSIParameter1\t\t0x820\t/* RF 3 wire register */\n#define\t\trFPGA0_XA_HSSIParameter2\t\t0x824\n#define\t\trFPGA0_XB_HSSIParameter1\t\t0x828\n#define\t\trFPGA0_XB_HSSIParameter2\t\t0x82c\n#define\t\trTxAGC_B_Rate18_06\t\t\t\t0x830\n#define\t\trTxAGC_B_Rate54_24\t\t\t\t0x834\n#define\t\trTxAGC_B_CCK1_55_Mcs32\t\t0x838\n#define\t\trTxAGC_B_Mcs03_Mcs00\t\t\t0x83c\n\n#define\t\trTxAGC_B_Mcs07_Mcs04\t\t\t0x848\n#define\t\trTxAGC_B_Mcs11_Mcs08\t\t\t0x84c\n\n#define\t\trFPGA0_XA_LSSIParameter\t\t0x840\n#define\t\trFPGA0_XB_LSSIParameter\t\t0x844\n\n#define\t\trFPGA0_RFWakeUpParameter\t\t0x850\t/* Useless now */\n#define\t\trFPGA0_RFSleepUpParameter\t\t0x854\n\n#define\t\trFPGA0_XAB_SwitchControl\t\t0x858\t/* RF Channel switch */\n#define\t\trFPGA0_XCD_SwitchControl\t\t0x85c\n\n#define\t\trFPGA0_XA_RFInterfaceOE\t\t0x860\t/* RF Channel switch */\n#define\t\trFPGA0_XB_RFInterfaceOE\t\t0x864\n\n#define\t\trTxAGC_B_Mcs15_Mcs12\t\t\t0x868\n#define\t\trTxAGC_B_CCK11_A_CCK2_11\t\t0x86c\n\n#define\t\trFPGA0_XAB_RFInterfaceSW\t\t0x870\t/* RF Interface Software Control */\n#define\t\trFPGA0_XCD_RFInterfaceSW\t\t0x874\n\n#define\t\trFPGA0_XAB_RFParameter\t\t0x878\t/* RF Parameter */\n#define\t\trFPGA0_XCD_RFParameter\t\t0x87c\n\n#define\t\trFPGA0_AnalogParameter1\t\t0x880\t/* Crystal cap setting RF-R/W protection for parameter4?? */\n#define\t\trFPGA0_AnalogParameter2\t\t0x884\n#define\t\trFPGA0_AnalogParameter3\t\t0x888\t/* Useless now */\n#define\t\trFPGA0_AnalogParameter4\t\t0x88c\n\n#define\t\trFPGA0_XA_LSSIReadBack\t\t0x8a0\t/* Tranceiver LSSI Readback */\n#define\t\trFPGA0_XB_LSSIReadBack\t\t0x8a4\n#define\t\trFPGA0_XC_LSSIReadBack\t\t0x8a8\n#define\t\trFPGA0_XD_LSSIReadBack\t\t0x8ac\n\n#define\t\trFPGA0_PSDReport\t\t\t\t0x8b4\t/* Useless now */\n#define\t\tTransceiverA_HSPI_Readback\t0x8b8\t/* Transceiver A HSPI Readback */\n#define\t\tTransceiverB_HSPI_Readback\t0x8bc\t/* Transceiver B HSPI Readback */\n#define\t\trFPGA0_XAB_RFInterfaceRB\t\t0x8e0\t/* Useless now // RF Interface Readback Value */\n#define\t\trFPGA0_XCD_RFInterfaceRB\t\t0x8e4\t/* Useless now */\n\n/*\n * 4. Page9(0x900)\n *   */\n#define\trFPGA1_RFMOD\t\t\t\t0x900\t/* RF mode & OFDM TxSC // RF BW Setting?? */\n#define\trFPGA1_TxBlock\t\t\t\t0x904\t/* Useless now */\n#define\trFPGA1_DebugSelect\t\t\t0x908\t/* Useless now */\n#define\trFPGA1_TxInfo\t\t\t\t0x90c\t/* Useless now // Status report?? */\n#define\trDPDT_control\t\t\t\t0x92c\n#define\trfe_ctrl_anta_src\t\t\t\t0x930\n#define\trS0S1_PathSwitch\t\t\t0x948\n#define\trBBrx_DFIR\t\t\t\t\t0x954\n\n/*\n * 5. PageA(0xA00)\n *\n * Set Control channel to upper or lower. These settings are required only for 40MHz */\n#define\t\trCCK0_System\t\t\t\t0xa00\n\n#define\t\trCCK0_AFESetting\t\t\t0xa04\t/* Disable init gain now // Select RX path by RSSI */\n#define\t\trCCK0_CCA\t\t\t\t\t0xa08\t/* Disable init gain now // Init gain */\n\n#define\t\trCCK0_RxAGC1\t\t\t\t0xa0c\t/* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */\n#define\t\trCCK0_RxAGC2\t\t\t\t0xa10\t/* AGC & DAGC */\n\n#define\t\trCCK0_RxHP\t\t\t\t\t0xa14\n\n#define\t\trCCK0_DSPParameter1\t\t0xa18\t/* Timing recovery & Channel estimation threshold */\n#define\t\trCCK0_DSPParameter2\t\t0xa1c\t/* SQ threshold */\n\n#define\t\trCCK0_TxFilter1\t\t\t\t0xa20\n#define\t\trCCK0_TxFilter2\t\t\t\t0xa24\n#define\t\trCCK0_DebugPort\t\t\t0xa28\t/* debug port and Tx filter3 */\n#define\t\trCCK0_FalseAlarmReport\t\t0xa2c\t/* 0xa2d\tuseless now 0xa30-a4f channel report */\n#define\t\trCCK0_TRSSIReport\t\t0xa50\n#define\t\trCCK0_RxReport\t\t\t0xa54  /* 0xa57 */\n#define\t\trCCK0_FACounterLower\t\t0xa5c  /* 0xa5b */\n#define\t\trCCK0_FACounterUpper\t\t0xa58  /* 0xa5c */\n\n/*\n * PageB(0xB00)\n *   */\n#define rPdp_AntA\t\t\t\t\t\t0xb00\n#define rPdp_AntA_4\t\t\t\t\t\t0xb04\n#define rPdp_AntA_8\t\t\t\t\t\t0xb08\n#define rPdp_AntA_C\t\t\t\t\t\t0xb0c\n#define rPdp_AntA_10\t\t\t\t\t0xb10\n#define rPdp_AntA_14\t\t\t\t\t0xb14\n#define rPdp_AntA_18\t\t\t\t\t0xb18\n#define rPdp_AntA_1C\t\t\t\t\t0xb1c\n#define rPdp_AntA_20\t\t\t\t\t0xb20\n#define rPdp_AntA_24\t\t\t\t\t0xb24\n\n#define rConfig_Pmpd_AntA\t\t\t\t0xb28\n#define rConfig_ram64x16\t\t\t\t0xb2c\n\n#define rBndA\t\t\t\t\t\t\t0xb30\n#define rHssiPar\t\t\t\t\t\t0xb34\n\n#define rConfig_AntA\t\t\t\t\t0xb68\n#define rConfig_AntB\t\t\t\t\t0xb6c\n\n#define rPdp_AntB\t\t\t\t\t\t0xb70\n#define rPdp_AntB_4\t\t\t\t\t\t0xb74\n#define rPdp_AntB_8\t\t\t\t\t\t0xb78\n#define rPdp_AntB_C\t\t\t\t\t\t0xb7c\n#define rPdp_AntB_10\t\t\t\t\t0xb80\n#define rPdp_AntB_14\t\t\t\t\t0xb84\n#define rPdp_AntB_18\t\t\t\t\t0xb88\n#define rPdp_AntB_1C\t\t\t\t\t0xb8c\n#define rPdp_AntB_20\t\t\t\t\t0xb90\n#define rPdp_AntB_24\t\t\t\t\t0xb94\n\n#define rConfig_Pmpd_AntB\t\t\t\t0xb98\n\n#define rBndB\t\t\t\t\t\t\t0xba0\n\n#define rAPK\t\t\t\t\t\t\t0xbd8\n#define rPm_Rx0_AntA\t\t\t\t\t0xbdc\n#define rPm_Rx1_AntA\t\t\t\t\t0xbe0\n#define rPm_Rx2_AntA\t\t\t\t\t0xbe4\n#define rPm_Rx3_AntA\t\t\t\t\t0xbe8\n#define rPm_Rx0_AntB\t\t\t\t\t0xbec\n#define rPm_Rx1_AntB\t\t\t\t\t0xbf0\n#define rPm_Rx2_AntB\t\t\t\t\t0xbf4\n#define rPm_Rx3_AntB\t\t\t\t\t0xbf8\n/*\n * 6. PageC(0xC00)\n *   */\n#define\t\trOFDM0_LSTF\t\t\t\t0xc00\n\n#define\t\trOFDM0_TRxPathEnable\t\t0xc04\n#define\t\trOFDM0_TRMuxPar\t\t\t0xc08\n#define\t\trOFDM0_TRSWIsolation\t\t0xc0c\n\n#define\t\trOFDM0_XARxAFE\t\t\t0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */\n#define\t\trOFDM0_XARxIQImbalance\t\t0xc14  /* RxIQ imbalance matrix */\n#define\t\trOFDM0_XBRxAFE\t\t0xc18\n#define\t\trOFDM0_XBRxIQImbalance\t0xc1c\n#define\t\trOFDM0_XCRxAFE\t\t0xc20\n#define\t\trOFDM0_XCRxIQImbalance\t0xc24\n#define\t\trOFDM0_XDRxAFE\t\t0xc28\n#define\t\trOFDM0_XDRxIQImbalance\t0xc2c\n\n#define\t\trOFDM0_RxDetector1\t\t\t0xc30  /* PD, BW & SBD\t// DM tune init gain */\n#define\t\trOFDM0_RxDetector2\t\t\t0xc34  /* SBD & Fame Sync. */\n#define\t\trOFDM0_RxDetector3\t\t\t0xc38  /* Frame Sync. */\n#define\t\trOFDM0_RxDetector4\t\t\t0xc3c  /* PD, SBD, Frame Sync & Short-GI */\n\n#define\t\trOFDM0_RxDSP\t\t\t\t0xc40  /* Rx Sync Path */\n#define\t\trOFDM0_CFOandDAGC\t\t0xc44  /* CFO & DAGC */\n#define\t\trOFDM0_CCADropThreshold\t0xc48 /* CCA Drop threshold */\n#define\t\trOFDM0_ECCAThreshold\t\t0xc4c /* energy CCA */\n\n#define\t\trOFDM0_XAAGCCore1\t\t\t0xc50\t/* DIG */\n#define\t\trOFDM0_XAAGCCore2\t\t\t0xc54\n#define\t\trOFDM0_XBAGCCore1\t\t\t0xc58\n#define\t\trOFDM0_XBAGCCore2\t\t\t0xc5c\n#define\t\trOFDM0_XCAGCCore1\t\t\t0xc60\n#define\t\trOFDM0_XCAGCCore2\t\t\t0xc64\n#define\t\trOFDM0_XDAGCCore1\t\t\t0xc68\n#define\t\trOFDM0_XDAGCCore2\t\t\t0xc6c\n\n#define\t\trOFDM0_AGCParameter1\t\t\t0xc70\n#define\t\trOFDM0_AGCParameter2\t\t\t0xc74\n#define\t\trOFDM0_AGCRSSITable\t\t\t0xc78\n#define\t\trOFDM0_HTSTFAGC\t\t\t\t0xc7c\n\n#define\t\trOFDM0_XATxIQImbalance\t\t0xc80\t/* TX PWR TRACK and DIG */\n#define\t\trOFDM0_XATxAFE\t\t\t\t0xc84\n#define\t\trOFDM0_XBTxIQImbalance\t\t0xc88\n#define\t\trOFDM0_XBTxAFE\t\t\t\t0xc8c\n#define\t\trOFDM0_XCTxIQImbalance\t\t0xc90\n#define\t\trOFDM0_XCTxAFE\t\t\t0xc94\n#define\t\trOFDM0_XDTxIQImbalance\t\t0xc98\n#define\t\trOFDM0_XDTxAFE\t\t\t\t0xc9c\n\n#define\t\trOFDM0_RxIQExtAnta\t\t\t0xca0\n#define\t\trOFDM0_TxCoeff1\t\t\t\t0xca4\n#define\t\trOFDM0_TxCoeff2\t\t\t\t0xca8\n#define\t\trOFDM0_TxCoeff3\t\t\t\t0xcac\n#define\t\trOFDM0_TxCoeff4\t\t\t\t0xcb0\n#define\t\trOFDM0_TxCoeff5\t\t\t\t0xcb4\n#define\t\trOFDM0_TxCoeff6\t\t\t\t0xcb8\n#define\t\trOFDM0_RxHPParameter\t\t\t0xce0\n#define\t\trOFDM0_TxPseudoNoiseWgt\t\t0xce4\n#define\t\trOFDM0_FrameSync\t\t\t\t0xcf0\n#define\t\trOFDM0_DFSReport\t\t\t\t0xcf4\n\n/*\n * 7. PageD(0xD00)\n *   */\n#define\t\trOFDM1_LSTF\t\t\t\t\t0xd00\n#define\t\trOFDM1_TRxPathEnable\t\t\t0xd04\n\n#define\t\trOFDM1_CFO\t\t\t\t\t\t0xd08\t/* No setting now */\n#define\t\trOFDM1_CSI1\t\t\t\t\t0xd10\n#define\t\trOFDM1_SBD\t\t\t\t\t\t0xd14\n#define\t\trOFDM1_CSI2\t\t\t\t\t0xd18\n#define\t\trOFDM1_CFOTracking\t\t\t0xd2c\n#define\t\trOFDM1_TRxMesaure1\t\t\t0xd34\n#define\t\trOFDM1_IntfDet\t\t\t\t\t0xd3c\n#define\t\trOFDM1_PseudoNoiseStateAB\t\t0xd50\n#define\t\trOFDM1_PseudoNoiseStateCD\t\t0xd54\n#define\t\trOFDM1_RxPseudoNoiseWgt\t\t0xd58\n\n#define\t\trOFDM_PHYCounter1\t\t\t\t0xda0  /* cca, parity fail */\n#define\t\trOFDM_PHYCounter2\t\t\t\t0xda4  /* rate illegal, crc8 fail */\n#define\t\trOFDM_PHYCounter3\t\t\t\t0xda8  /* MCS not support */\n\n#define\t\trOFDM_ShortCFOAB\t\t\t\t0xdac\t/* No setting now */\n#define\t\trOFDM_ShortCFOCD\t\t\t\t0xdb0\n#define\t\trOFDM_LongCFOAB\t\t\t\t0xdb4\n#define\t\trOFDM_LongCFOCD\t\t\t\t0xdb8\n#define\t\trOFDM_TailCFOAB\t\t\t\t0xdbc\n#define\t\trOFDM_TailCFOCD\t\t\t\t0xdc0\n#define\t\trOFDM_PWMeasure1\t\t0xdc4\n#define\t\trOFDM_PWMeasure2\t\t0xdc8\n#define\t\trOFDM_BWReport\t\t\t\t0xdcc\n#define\t\trOFDM_AGCReport\t\t\t\t0xdd0\n#define\t\trOFDM_RxSNR\t\t\t\t\t0xdd4\n#define\t\trOFDM_RxEVMCSI\t\t\t\t0xdd8\n#define\t\trOFDM_SIGReport\t\t\t\t0xddc\n\n\n/*\n * 8. PageE(0xE00)\n *   */\n#define\t\trTxAGC_A_Rate18_06\t\t\t0xe00\n#define\t\trTxAGC_A_Rate54_24\t\t\t0xe04\n#define\t\trTxAGC_A_CCK1_Mcs32\t\t\t0xe08\n#define\t\trTxAGC_A_Mcs03_Mcs00\t\t\t0xe10\n#define\t\trTxAGC_A_Mcs07_Mcs04\t\t\t0xe14\n#define\t\trTxAGC_A_Mcs11_Mcs08\t\t\t0xe18\n#define\t\trTxAGC_A_Mcs15_Mcs12\t\t\t0xe1c\n\n#define\t\trFPGA0_IQK\t\t\t\t\t0xe28\n#define\t\trTx_IQK_Tone_A\t\t\t\t0xe30\n#define\t\trRx_IQK_Tone_A\t\t\t\t0xe34\n#define\t\trTx_IQK_PI_A\t\t\t\t\t0xe38\n#define\t\trRx_IQK_PI_A\t\t\t\t\t0xe3c\n\n#define\t\trTx_IQK\t\t\t\t\t\t0xe40\n#define\t\trRx_IQK\t\t\t\t\t\t0xe44\n#define\t\trIQK_AGC_Pts\t\t\t\t\t0xe48\n#define\t\trIQK_AGC_Rsp\t\t\t\t\t0xe4c\n#define\t\trTx_IQK_Tone_B\t\t\t\t0xe50\n#define\t\trRx_IQK_Tone_B\t\t\t\t0xe54\n#define\t\trTx_IQK_PI_B\t\t\t\t\t0xe58\n#define\t\trRx_IQK_PI_B\t\t\t\t\t0xe5c\n#define\t\trIQK_AGC_Cont\t\t\t\t0xe60\n\n#define\t\trBlue_Tooth\t\t\t\t\t0xe6c\n#define\t\trRx_Wait_CCA\t\t\t\t\t0xe70\n#define\t\trTx_CCK_RFON\t\t\t\t\t0xe74\n#define\t\trTx_CCK_BBON\t\t\t\t0xe78\n#define\t\trTx_OFDM_RFON\t\t\t\t0xe7c\n#define\t\trTx_OFDM_BBON\t\t\t\t0xe80\n#define\t\trTx_To_Rx\t\t\t\t\t0xe84\n#define\t\trTx_To_Tx\t\t\t\t\t0xe88\n#define\t\trRx_CCK\t\t\t\t\t\t0xe8c\n\n#define\t\trTx_Power_Before_IQK_A\t\t0xe94\n#define\t\trTx_Power_After_IQK_A\t\t\t0xe9c\n\n#define\t\trRx_Power_Before_IQK_A\t\t0xea0\n#define\t\trRx_Power_Before_IQK_A_2\t\t0xea4\n#define\t\trRx_Power_After_IQK_A\t\t\t0xea8\n#define\t\trRx_Power_After_IQK_A_2\t\t0xeac\n\n#define\t\trTx_Power_Before_IQK_B\t\t0xeb4\n#define\t\trTx_Power_After_IQK_B\t\t\t0xebc\n\n#define\t\trRx_Power_Before_IQK_B\t\t0xec0\n#define\t\trRx_Power_Before_IQK_B_2\t\t0xec4\n#define\t\trRx_Power_After_IQK_B\t\t\t0xec8\n#define\t\trRx_Power_After_IQK_B_2\t\t0xecc\n\n#define\t\trRx_OFDM\t\t\t\t\t0xed0\n#define\t\trRx_Wait_RIFS\t\t\t\t0xed4\n#define\t\trRx_TO_Rx\t\t\t\t\t0xed8\n#define\t\trStandby\t\t\t\t\t\t0xedc\n#define\t\trSleep\t\t\t\t\t\t0xee0\n#define\t\trPMPD_ANAEN\t\t\t\t0xeec\n\n/*\n * 7. RF Register 0x00-0x2E (RF 8256)\n * RF-0222D 0x00-3F\n *\n * Zebra1 */\n#define\t\trZebra1_HSSIEnable\t\t\t\t0x0\t/* Useless now */\n#define\t\trZebra1_TRxEnable1\t\t\t\t0x1\n#define\t\trZebra1_TRxEnable2\t\t\t\t0x2\n#define\t\trZebra1_AGC\t\t\t\t\t0x4\n#define\t\trZebra1_ChargePump\t\t\t0x5\n#define\t\trZebra1_Channel\t\t\t\t0x7\t/* RF channel switch */\n\n/* #endif */\n#define\t\trZebra1_TxGain\t\t\t\t\t0x8\t/* Useless now */\n#define\t\trZebra1_TxLPF\t\t\t\t\t0x9\n#define\t\trZebra1_RxLPF\t\t\t\t\t0xb\n#define\t\trZebra1_RxHPFCorner\t\t\t0xc\n\n/* Zebra4 */\n#define\t\trGlobalCtrl\t\t\t\t\t\t0\t/* Useless now */\n#define\t\trRTL8256_TxLPF\t\t\t\t\t19\n#define\t\trRTL8256_RxLPF\t\t\t\t\t11\n\n/* RTL8258 */\n#define\t\trRTL8258_TxLPF\t\t\t\t\t0x11\t/* Useless now */\n#define\t\trRTL8258_RxLPF\t\t\t\t\t0x13\n#define\t\trRTL8258_RSSILPF\t\t\t\t0xa\n\n/*\n * RL6052 Register definition\n *   */\n#define\t\tRF_AC\t\t\t\t\t\t0x00\t/* */\n\n#define\t\tRF_IQADJ_G1\t\t\t\t0x01\t/* */\n#define\t\tRF_IQADJ_G2\t\t\t\t0x02\t/* */\n#define\t\tRF_BS_PA_APSET_G1_G4\t\t0x03\n#define\t\tRF_BS_PA_APSET_G5_G8\t\t0x04\n#define\t\tRF_POW_TRSW\t\t\t\t0x05\t/* */\n\n#define\t\tRF_GAIN_RX\t\t\t\t\t0x06\t/* */\n#define\t\tRF_GAIN_TX\t\t\t\t\t0x07\t/* */\n\n#define\t\tRF_TXM_IDAC\t\t\t\t0x08\t/* */\n#define\t\tRF_IPA_G\t\t\t\t\t0x09\t/* */\n#define\t\tRF_TXBIAS_G\t\t\t\t0x0A\n#define\t\tRF_TXPA_AG\t\t\t\t\t0x0B\n#define\t\tRF_IPA_A\t\t\t\t\t0x0C\t/* */\n#define\t\tRF_TXBIAS_A\t\t\t\t0x0D\n#define\t\tRF_BS_PA_APSET_G9_G11\t0x0E\n#define\t\tRF_BS_IQGEN\t\t\t\t0x0F\t/* */\n\n#define\t\tRF_MODE1\t\t\t\t\t0x10\t/* */\n#define\t\tRF_MODE2\t\t\t\t\t0x11\t/* */\n\n#define\t\tRF_RX_AGC_HP\t\t\t\t0x12\t/* */\n#define\t\tRF_TX_AGC\t\t\t\t\t0x13\t/* */\n#define\t\tRF_BIAS\t\t\t\t\t\t0x14\t/* */\n#define\t\tRF_IPA\t\t\t\t\t\t0x15\t/* */\n#define\t\tRF_TXBIAS\t\t\t\t\t0x16\n#define\t\tRF_POW_ABILITY\t\t\t0x17\t/* */\n#define\t\tRF_MODE_AG\t\t\t\t0x18\t/* */\n#define\t\trRfChannel\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define\t\tRF_CHNLBW\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define\t\tRF_TOP\t\t\t\t\t\t0x19\t/* */\n\n#define\t\tRF_RX_G1\t\t\t\t\t0x1A\t/* */\n#define\t\tRF_RX_G2\t\t\t\t\t0x1B\t/* */\n\n#define\t\tRF_RX_BB2\t\t\t\t\t0x1C\t/* */\n#define\t\tRF_RX_BB1\t\t\t\t\t0x1D\t/* */\n\n#define\t\tRF_RCK1\t\t\t\t\t0x1E\t/* */\n#define\t\tRF_RCK2\t\t\t\t\t0x1F\t/* */\n\n#define\t\tRF_TX_G1\t\t\t\t\t0x20\t/* */\n#define\t\tRF_TX_G2\t\t\t\t\t0x21\t/* */\n#define\t\tRF_TX_G3\t\t\t\t\t0x22\t/* */\n\n#define\t\tRF_TX_BB1\t\t\t\t\t0x23\t/* */\n\n#define\t\tRF_T_METER\t\t\t\t\t0x24\t/* */\n\n#define\t\tRF_SYN_G1\t\t\t\t\t0x25\t/* RF TX Power control */\n#define\t\tRF_SYN_G2\t\t\t\t\t0x26\t/* RF TX Power control */\n#define\t\tRF_SYN_G3\t\t\t\t\t0x27\t/* RF TX Power control */\n#define\t\tRF_SYN_G4\t\t\t\t\t0x28\t/* RF TX Power control */\n#define\t\tRF_SYN_G5\t\t\t\t\t0x29\t/* RF TX Power control */\n#define\t\tRF_SYN_G6\t\t\t\t\t0x2A\t/* RF TX Power control */\n#define\t\tRF_SYN_G7\t\t\t\t\t0x2B\t/* RF TX Power control */\n#define\t\tRF_SYN_G8\t\t\t\t\t0x2C\t/* RF TX Power control */\n\n#define\t\tRF_RCK_OS\t\t\t\t\t0x30\t/* RF TX PA control */\n\n#define\t\tRF_TXPA_G1\t\t\t\t\t0x31\t/* RF TX PA control */\n#define\t\tRF_TXPA_G2\t\t\t\t\t0x32\t/* RF TX PA control */\n#define\t\tRF_TXPA_G3\t\t\t\t\t0x33\t/* RF TX PA control */\n#define\tRF_TX_BIAS_A\t\t\t\t0x35\n#define\tRF_TX_BIAS_D\t\t\t\t0x36\n#define\tRF_LOBF_9\t\t\t\t\t0x38\n#define\tRF_RXRF_A3\t\t\t\t\t0x3C\t/*\t */\n#define\tRF_TRSW\t\t\t\t\t0x3F\n\n#define\tRF_TXRF_A2\t\t\t\t\t0x41\n#define\tRF_T_METER_88E\t\t\t\t0x42\n#define\tRF_TXPA_G4\t\t\t\t\t0x46\n#define\tRF_TXPA_A4\t\t\t\t\t0x4B\n#define\tRF_0x52\t\t\t\t\t0x52\n#define\tRF_WE_LUT\t\t\t\t\t0xEF\n#define\tRF_S0S1\t\t\t\t\t0xB0\n\n/*\n * Bit Mask\n *\n * 1. Page1(0x100) */\n#define\t\tbBBResetB\t\t\t\t\t\t0x100\t/* Useless now? */\n#define\t\tbGlobalResetB\t\t\t\t\t0x200\n#define\t\tbOFDMTxStart\t\t\t\t\t0x4\n#define\t\tbCCKTxStart\t\t\t\t\t\t0x8\n#define\t\tbCRC32Debug\t\t\t\t\t0x100\n#define\t\tbPMACLoopback\t\t\t\t\t0x10\n#define\t\tbTxLSIG\t\t\t\t\t\t\t0xffffff\n#define\t\tbOFDMTxRate\t\t\t\t\t0xf\n#define\t\tbOFDMTxReserved\t\t\t\t0x10\n#define\t\tbOFDMTxLength\t\t\t\t\t0x1ffe0\n#define\t\tbOFDMTxParity\t\t\t\t\t0x20000\n#define\t\tbTxHTSIG1\t\t\t\t\t\t0xffffff\n#define\t\tbTxHTMCSRate\t\t\t\t\t0x7f\n#define\t\tbTxHTBW\t\t\t\t\t\t0x80\n#define\t\tbTxHTLength\t\t\t\t\t0xffff00\n#define\t\tbTxHTSIG2\t\t\t\t\t\t0xffffff\n#define\t\tbTxHTSmoothing\t\t\t\t\t0x1\n#define\t\tbTxHTSounding\t\t\t\t\t0x2\n#define\t\tbTxHTReserved\t\t\t\t\t0x4\n#define\t\tbTxHTAggreation\t\t\t\t0x8\n#define\t\tbTxHTSTBC\t\t\t\t\t\t0x30\n#define\t\tbTxHTAdvanceCoding\t\t\t0x40\n#define\t\tbTxHTShortGI\t\t\t\t\t0x80\n#define\t\tbTxHTNumberHT_LTF\t\t\t0x300\n#define\t\tbTxHTCRC8\t\t\t\t\t\t0x3fc00\n#define\t\tbCounterReset\t\t\t\t\t0x10000\n#define\t\tbNumOfOFDMTx\t\t\t\t\t0xffff\n#define\t\tbNumOfCCKTx\t\t\t\t\t0xffff0000\n#define\t\tbTxIdleInterval\t\t\t\t\t0xffff\n#define\t\tbOFDMService\t\t\t\t\t0xffff0000\n#define\t\tbTxMACHeader\t\t\t\t\t0xffffffff\n#define\t\tbTxDataInit\t\t\t\t\t\t0xff\n#define\t\tbTxHTMode\t\t\t\t\t\t0x100\n#define\t\tbTxDataType\t\t\t\t\t0x30000\n#define\t\tbTxRandomSeed\t\t\t\t\t0xffffffff\n#define\t\tbCCKTxPreamble\t\t\t\t\t0x1\n#define\t\tbCCKTxSFD\t\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxSIG\t\t\t\t\t\t0xff\n#define\t\tbCCKTxService\t\t\t\t\t0xff00\n#define\t\tbCCKLengthExt\t\t\t\t\t0x8000\n#define\t\tbCCKTxLength\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxCRC16\t\t\t\t\t0xffff\n#define\t\tbCCKTxStatus\t\t\t\t\t0x1\n#define\t\tbOFDMTxStatus\t\t\t\t\t0x2\n\n#define\t\tIS_BB_REG_OFFSET_92S(_Offset)\t\t((_Offset >= 0x800) && (_Offset <= 0xfff))\n#define\t\tRF_TX_GAIN_OFFSET_8723D(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0))\n\n/* 2. Page8(0x800) */\n#define\t\tbRFMOD\t\t\t\t\t\t\t0x1\t/* Reg 0x800 rFPGA0_RFMOD */\n#define\t\tbJapanMode\t\t\t\t\t\t0x2\n#define\t\tbCCKTxSC\t\t\t\t\t\t0x30\n#define\t\tbCCKEn\t\t\t\t\t\t\t0x1000000\n#define\t\tbOFDMEn\t\t\t\t\t\t0x2000000\n\n#define\t\tbOFDMRxADCPhase           0x10000\t/* Useless now */\n#define\t\tbOFDMTxDACPhase\t\t0x40000\n#define\t\tbXATxAGC\t\t\t0x3f\n\n#define\t\tbAntennaSelect\t\t0x0300\n\n#define\t\tbXBTxAGC                 0xf00\t/* Reg 80c rFPGA0_TxGainStage */\n#define\t\tbXCTxAGC\t\t\t0xf000\n#define\t\tbXDTxAGC\t\t\t0xf0000\n\n#define\t\tbPAStart                 0xf0000000\t/* Useless now */\n#define\t\tbTRStart\t\t\t0x00f00000\n#define\t\tbRFStart\t\t\t0x0000f000\n#define\t\tbBBStart\t\t\t0x000000f0\n#define\t\tbBBCCKStart\t\t0x0000000f\n#define\t\tbPAEnd                    0xf          /* Reg0x814 */\n#define\t\tbTREnd\t\t\t0x0f000000\n#define\t\tbRFEnd\t\t\t0x000f0000\n#define\t\tbCCAMask                  0x000000f0   /* T2R */\n#define\t\tbR2RCCAMask\t\t0x00000f00\n#define\t\tbHSSI_R2TDelay\t\t0xf8000000\n#define\t\tbHSSI_T2RDelay\t\t0xf80000\n#define\t\tbContTxHSSI              0x400     /* chane gain at continue Tx */\n#define\t\tbIGFromCCK\t\t0x200\n#define\t\tbAGCAddress\t\t0x3f\n#define\t\tbRxHPTx\t\t\t0x7000\n#define\t\tbRxHPT2R\t\t\t0x38000\n#define\t\tbRxHPCCKIni\t\t0xc0000\n#define\t\tbAGCTxCode\t\t0xc00000\n#define\t\tbAGCRxCode\t\t0x300000\n\n#define\t\tb3WireDataLength         0x800\t/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */\n#define\t\tb3WireAddressLength\t\t0x400\n\n#define\t\tb3WireRFPowerDown         0x1\t/* Useless now\n * #define bHWSISelect\t\t0x8 */\n#define\t\tb5GPAPEPolarity\t\t0x40000000\n#define\t\tb2GPAPEPolarity\t\t0x80000000\n#define\t\tbRFSW_TxDefaultAnt\t\t0x3\n#define\t\tbRFSW_TxOptionAnt\t\t0x30\n#define\t\tbRFSW_RxDefaultAnt\t\t0x300\n#define\t\tbRFSW_RxOptionAnt\t\t0x3000\n#define\t\tbRFSI_3WireData\t\t0x1\n#define\t\tbRFSI_3WireClock\t\t0x2\n#define\t\tbRFSI_3WireLoad\t\t0x4\n#define\t\tbRFSI_3WireRW\t\t0x8\n#define\t\tbRFSI_3Wire\t\t\t0xf\n\n#define\t\tbRFSI_RFENV              0x10\t/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */\n\n#define\t\tbRFSI_TRSW               0x20\t/* Useless now */\n#define\t\tbRFSI_TRSWB\t\t0x40\n#define\t\tbRFSI_ANTSW\t\t0x100\n#define\t\tbRFSI_ANTSWB\t\t0x200\n#define\t\tbRFSI_PAPE\t\t\t0x400\n#define\t\tbRFSI_PAPE5G\t\t0x800\n#define\t\tbBandSelect\t\t\t0x1\n#define\t\tbHTSIG2_GI\t\t\t0x80\n#define\t\tbHTSIG2_Smoothing\t\t0x01\n#define\t\tbHTSIG2_Sounding\t\t0x02\n#define\t\tbHTSIG2_Aggreaton\t\t0x08\n#define\t\tbHTSIG2_STBC\t\t0x30\n#define\t\tbHTSIG2_AdvCoding\t\t0x40\n#define\t\tbHTSIG2_NumOfHTLTF\t0x300\n#define\t\tbHTSIG2_CRC8\t\t0x3fc\n#define\t\tbHTSIG1_MCS\t\t0x7f\n#define\t\tbHTSIG1_BandWidth\t\t0x80\n#define\t\tbHTSIG1_HTLength\t\t0xffff\n#define\t\tbLSIG_Rate\t\t\t0xf\n#define\t\tbLSIG_Reserved\t\t0x10\n#define\t\tbLSIG_Length\t\t0x1fffe\n#define\t\tbLSIG_Parity\t\t\t0x20\n#define\t\tbCCKRxPhase\t\t0x4\n\n#define\t\tbLSSIReadAddress          0x7f800000   /* T65 RF */\n\n#define\t\tbLSSIReadEdge             0x80000000   /* LSSI \"Read\" edge signal */\n\n#define\t\tbLSSIReadBackData         0xfffff\t\t/* T65 RF */\n\n#define\t\tbLSSIReadOKFlag           0x1000\t/* Useless now */\n#define\t\tbCCKSampleRate            0x8       /* 0: 44MHz, 1:88MHz     */\n#define\t\tbRegulator0Standby\t\t0x1\n#define\t\tbRegulatorPLLStandby\t\t0x2\n#define\t\tbRegulator1Standby\t\t0x4\n#define\t\tbPLLPowerUp\t\t0x8\n#define\t\tbDPLLPowerUp\t\t0x10\n#define\t\tbDA10PowerUp\t\t0x20\n#define\t\tbAD7PowerUp\t\t0x200\n#define\t\tbDA6PowerUp\t\t0x2000\n#define\t\tbXtalPowerUp\t\t0x4000\n#define\t\tb40MDClkPowerUP\t\t0x8000\n#define\t\tbDA6DebugMode\t\t0x20000\n#define\t\tbDA6Swing\t\t\t0x380000\n\n#define\t\tbADClkPhase               0x4000000\t/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */\n\n#define\t\tb80MClkDelay              0x18000000\t/* Useless */\n#define\t\tbAFEWatchDogEnable\t\t0x20000000\n\n#define\t\tbXtalCap01                0xc0000000\t/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */\n#define\t\tbXtalCap23\t\t\t0x3\n#define\t\tbXtalCap92x\t\t\t\t\t0x0f000000\n#define\t\tbXtalCap\t\t\t0x0f000000\n\n#define\t\tbIntDifClkEnable          0x400\t/* Useless */\n#define\t\tbExtSigClkEnable\t\t0x800\n#define\t\tbBandgapMbiasPowerUp\t0x10000\n#define\t\tbAD11SHGain\t\t0xc0000\n#define\t\tbAD11InputRange\t\t0x700000\n#define\t\tbAD11OPCurrent\t\t0x3800000\n#define\t\tbIPathLoopback\t\t0x4000000\n#define\t\tbQPathLoopback\t\t0x8000000\n#define\t\tbAFELoopback\t\t0x10000000\n#define\t\tbDA10Swing\t\t0x7e0\n#define\t\tbDA10Reverse\t\t0x800\n#define\t\tbDAClkSource\t\t0x1000\n#define\t\tbAD7InputRange\t\t0x6000\n#define\t\tbAD7Gain\t\t\t0x38000\n#define\t\tbAD7OutputCMMode\t\t0x40000\n#define\t\tbAD7InputCMMode\t\t0x380000\n#define\t\tbAD7Current\t\t\t0xc00000\n#define\t\tbRegulatorAdjust\t\t0x7000000\n#define\t\tbAD11PowerUpAtTx\t\t0x1\n#define\t\tbDA10PSAtTx\t\t0x10\n#define\t\tbAD11PowerUpAtRx\t\t0x100\n#define\t\tbDA10PSAtRx\t\t0x1000\n#define\t\tbCCKRxAGCFormat\t\t0x200\n#define\t\tbPSDFFTSamplepPoint\t\t0xc000\n#define\t\tbPSDAverageNum\t\t0x3000\n#define\t\tbIQPathControl\t\t0xc00\n#define\t\tbPSDFreq\t\t\t0x3ff\n#define\t\tbPSDAntennaPath\t\t0x30\n#define\t\tbPSDIQSwitch\t\t0x40\n#define\t\tbPSDRxTrigger\t\t0x400000\n#define\t\tbPSDTxTrigger\t\t0x80000000\n#define\t\tbPSDSineToneScale\t\t0x7f000000\n#define\t\tbPSDReport\t\t\t0xffff\n\n/* 3. Page9(0x900) */\n#define\t\tbOFDMTxSC                 0x30000000\t/* Useless */\n#define\t\tbCCKTxOn\t\t\t0x1\n#define\t\tbOFDMTxOn\t\t0x2\n#define\t\tbDebugPage                0xfff  /* reset debug page and also HWord, LWord */\n#define\t\tbDebugItem                0xff   /* reset debug page and LWord */\n#define\t\tbAntL\t\t\t0x10\n#define\t\tbAntNonHT\t\t\t\t0x100\n#define\t\tbAntHT1\t\t\t0x1000\n#define\t\tbAntHT2\t\t\t0x10000\n#define\t\tbAntHT1S1\t\t\t0x100000\n#define\t\tbAntNonHTS1\t\t0x1000000\n\n/* 4. PageA(0xA00) */\n#define\t\tbCCKBBMode\t\t\t\t0x3\t/* Useless */\n#define\t\tbCCKTxPowerSaving\t\t0x80\n#define\t\tbCCKRxPowerSaving\t\t0x40\n\n#define\t\tbCCKSideBand\t\t\t0x10\t/* Reg 0xa00 rCCK0_System 20/40 switch */\n\n#define\t\tbCCKScramble\t\t\t0x8\t/* Useless */\n#define\t\tbCCKAntDiversity\t\t0x8000\n#define\t\tbCCKCarrierRecovery\t\t0x4000\n#define\t\tbCCKTxRate\t\t\t\t0x3000\n#define\t\tbCCKDCCancel\t\t\t0x0800\n#define\t\tbCCKISICancel\t\t\t0x0400\n#define\t\tbCCKMatchFilter\t\t\t0x0200\n#define\t\tbCCKEqualizer\t\t\t0x0100\n#define\t\tbCCKPreambleDetect\t\t0x800000\n#define\t\tbCCKFastFalseCCA\t\t0x400000\n#define\t\tbCCKChEstStart\t\t\t0x300000\n#define\t\tbCCKCCACount\t\t\t0x080000\n#define\t\tbCCKcs_lim\t\t\t\t0x070000\n#define\t\tbCCKBistMode\t\t\t0x80000000\n#define\t\tbCCKCCAMask\t\t\t0x40000000\n#define\t\tbCCKTxDACPhase\t\t0x4\n#define\t\tbCCKRxADCPhase\t\t0x20000000   /* r_rx_clk */\n#define\t\tbCCKr_cp_mode0\t\t0x0100\n#define\t\tbCCKTxDCOffset\t\t\t0xf0\n#define\t\tbCCKRxDCOffset\t\t\t0xf\n#define\t\tbCCKCCAMode\t\t\t0xc000\n#define\t\tbCCKFalseCS_lim\t\t\t0x3f00\n#define\t\tbCCKCS_ratio\t\t\t0xc00000\n#define\t\tbCCKCorgBit_sel\t\t\t0x300000\n#define\t\tbCCKPD_lim\t\t\t\t0x0f0000\n#define\t\tbCCKNewCCA\t\t\t0x80000000\n#define\t\tbCCKRxHPofIG\t\t\t0x8000\n#define\t\tbCCKRxIG\t\t\t\t0x7f00\n#define\t\tbCCKLNAPolarity\t\t\t0x800000\n#define\t\tbCCKRx1stGain\t\t\t0x7f0000\n#define\t\tbCCKRFExtend\t\t\t0x20000000 /* CCK Rx Iinital gain polarity */\n#define\t\tbCCKRxAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKRxAGCSatCount\t\t0xe0\n#define\t\tbCCKRxRFSettle\t\t\t0x1f       /* AGCsamp_dly */\n#define\t\tbCCKFixedRxAGC\t\t\t0x8000\n/* #define bCCKRxAGCFormat\t\t0x4000 */   /* remove to HSSI register 0x824 */\n#define\t\tbCCKAntennaPolarity\t\t0x2000\n#define\t\tbCCKTxFilterType\t\t0x0c00\n#define\t\tbCCKRxAGCReportType\t0x0300\n#define\t\tbCCKRxDAGCEn\t\t\t0x80000000\n#define\t\tbCCKRxDAGCPeriod\t\t0x20000000\n#define\t\tbCCKRxDAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKTimingRecovery\t\t0x800000\n#define\t\tbCCKTxC0\t\t\t\t0x3f0000\n#define\t\tbCCKTxC1\t\t\t\t0x3f000000\n#define\t\tbCCKTxC2\t\t\t\t0x3f\n#define\t\tbCCKTxC3\t\t\t\t0x3f00\n#define\t\tbCCKTxC4\t\t\t\t0x3f0000\n#define\t\tbCCKTxC5\t\t\t\t0x3f000000\n#define\t\tbCCKTxC6\t\t\t\t0x3f\n#define\t\tbCCKTxC7\t\t\t\t0x3f00\n#define\t\tbCCKDebugPort\t\t\t0xff0000\n#define\t\tbCCKDACDebug\t\t\t0x0f000000\n#define\t\tbCCKFalseAlarmEnable\t0x8000\n#define\t\tbCCKFalseAlarmRead\t\t0x4000\n#define\t\tbCCKTRSSI\t\t\t\t0x7f\n#define\t\tbCCKRxAGCReport\t\t0xfe\n#define\t\tbCCKRxReport_AntSel\t0x80000000\n#define\t\tbCCKRxReport_MFOff\t\t0x40000000\n#define\t\tbCCKRxRxReport_SQLoss\t0x20000000\n#define\t\tbCCKRxReport_Pktloss\t0x10000000\n#define\t\tbCCKRxReport_Lockedbit\t0x08000000\n#define\t\tbCCKRxReport_RateError\t0x04000000\n#define\t\tbCCKRxReport_RxRate\t0x03000000\n#define\t\tbCCKRxFACounterLower\t0xff\n#define\t\tbCCKRxFACounterUpper\t0xff000000\n#define\t\tbCCKRxHPAGCStart\t\t0xe000\n#define\t\tbCCKRxHPAGCFinal\t\t0x1c00\n#define\t\tbCCKRxFalseAlarmEnable\t0x8000\n#define\t\tbCCKFACounterFreeze\t0x4000\n#define\t\tbCCKTxPathSel\t\t\t0x10000000\n#define\t\tbCCKDefaultRxPath\t\t0xc000000\n#define\t\tbCCKOptionRxPath\t\t0x3000000\n\n/* 5. PageC(0xC00) */\n#define\t\tbNumOfSTF\t\t\t\t0x3\t/* Useless */\n#define\t\tbShift_L\t\t\t\t\t0xc0\n#define\t\tbGI_TH\t\t\t\t\t0xc\n#define\t\tbRxPathA\t\t\t\t0x1\n#define\t\tbRxPathB\t\t\t\t0x2\n#define\t\tbRxPathC\t\t\t\t0x4\n#define\t\tbRxPathD\t\t\t\t0x8\n#define\t\tbTxPathA\t\t\t\t0x1\n#define\t\tbTxPathB\t\t\t\t0x2\n#define\t\tbTxPathC\t\t\t\t0x4\n#define\t\tbTxPathD\t\t\t\t0x8\n#define\t\tbTRSSIFreq\t\t\t\t0x200\n#define\t\tbADCBackoff\t\t\t\t0x3000\n#define\t\tbDFIRBackoff\t\t\t0xc000\n#define\t\tbTRSSILatchPhase\t\t0x10000\n#define\t\tbRxIDCOffset\t\t\t0xff\n#define\t\tbRxQDCOffset\t\t\t0xff00\n#define\t\tbRxDFIRMode\t\t\t0x1800000\n#define\t\tbRxDCNFType\t\t\t0xe000000\n#define\t\tbRXIQImb_A\t\t\t\t0x3ff\n#define\t\tbRXIQImb_B\t\t\t\t0xfc00\n#define\t\tbRXIQImb_C\t\t\t\t0x3f0000\n#define\t\tbRXIQImb_D\t\t\t\t0xffc00000\n#define\t\tbDC_dc_Notch\t\t\t0x60000\n#define\t\tbRxNBINotch\t\t\t0x1f000000\n#define\t\tbPD_TH\t\t\t\t\t0xf\n#define\t\tbPD_TH_Opt2\t\t\t0xc000\n#define\t\tbPWED_TH\t\t\t\t0x700\n#define\t\tbIfMF_Win_L\t\t\t0x800\n#define\t\tbPD_Option\t\t\t\t0x1000\n#define\t\tbMF_Win_L\t\t\t\t0xe000\n#define\t\tbBW_Search_L\t\t\t0x30000\n#define\t\tbwin_enh_L\t\t\t\t0xc0000\n#define\t\tbBW_TH\t\t\t\t\t0x700000\n#define\t\tbED_TH2\t\t\t\t0x3800000\n#define\t\tbBW_option\t\t\t\t0x4000000\n#define\t\tbRatio_TH\t\t\t\t0x18000000\n#define\t\tbWindow_L\t\t\t\t0xe0000000\n#define\t\tbSBD_Option\t\t\t\t0x1\n#define\t\tbFrame_TH\t\t\t\t0x1c\n#define\t\tbFS_Option\t\t\t\t0x60\n#define\t\tbDC_Slope_check\t\t0x80\n#define\t\tbFGuard_Counter_DC_L\t0xe00\n#define\t\tbFrame_Weight_Short\t0x7000\n#define\t\tbSub_Tune\t\t\t\t0xe00000\n#define\t\tbFrame_DC_Length\t\t0xe000000\n#define\t\tbSBD_start_offset\t\t0x30000000\n#define\t\tbFrame_TH_2\t\t\t0x7\n#define\t\tbFrame_GI2_TH\t\t\t0x38\n#define\t\tbGI2_Sync_en\t\t\t0x40\n#define\t\tbSarch_Short_Early\t\t0x300\n#define\t\tbSarch_Short_Late\t\t0xc00\n#define\t\tbSarch_GI2_Late\t\t0x70000\n#define\t\tbCFOAntSum\t\t\t\t0x1\n#define\t\tbCFOAcc\t\t\t\t0x2\n#define\t\tbCFOStartOffset\t\t\t0xc\n#define\t\tbCFOLookBack\t\t\t0x70\n#define\t\tbCFOSumWeight\t\t\t0x80\n#define\t\tbDAGCEnable\t\t\t0x10000\n#define\t\tbTXIQImb_A\t\t\t\t0x3ff\n#define\t\tbTXIQImb_B\t\t\t\t0xfc00\n#define\t\tbTXIQImb_C\t\t\t\t0x3f0000\n#define\t\tbTXIQImb_D\t\t\t\t0xffc00000\n#define\t\tbTxIDCOffset\t\t\t0xff\n#define\t\tbTxQDCOffset\t\t\t0xff00\n#define\t\tbTxDFIRMode\t\t\t0x10000\n#define\t\tbTxPesudoNoiseOn\t\t0x4000000\n#define\t\tbTxPesudoNoise_A\t\t0xff\n#define\t\tbTxPesudoNoise_B\t\t0xff00\n#define\t\tbTxPesudoNoise_C\t\t0xff0000\n#define\t\tbTxPesudoNoise_D\t\t0xff000000\n#define\t\tbCCADropOption\t\t\t0x20000\n#define\t\tbCCADropThres\t\t\t0xfff00000\n#define\t\tbEDCCA_H\t\t\t\t0xf\n#define\t\tbEDCCA_L\t\t\t\t0xf0\n#define\t\tbLambda_ED\t\t\t0x300\n#define\t\tbRxInitialGain\t\t\t0x7f\n#define\t\tbRxAntDivEn\t\t\t\t0x80\n#define\t\tbRxAGCAddressForLNA\t0x7f00\n#define\t\tbRxHighPowerFlow\t\t0x8000\n#define\t\tbRxAGCFreezeThres\t\t0xc0000\n#define\t\tbRxFreezeStep_AGC1\t0x300000\n#define\t\tbRxFreezeStep_AGC2\t0xc00000\n#define\t\tbRxFreezeStep_AGC3\t0x3000000\n#define\t\tbRxFreezeStep_AGC0\t0xc000000\n#define\t\tbRxRssi_Cmp_En\t\t\t0x10000000\n#define\t\tbRxQuickAGCEn\t\t\t0x20000000\n#define\t\tbRxAGCFreezeThresMode\t0x40000000\n#define\t\tbRxOverFlowCheckType\t0x80000000\n#define\t\tbRxAGCShift\t\t\t\t0x7f\n#define\t\tbTRSW_Tri_Only\t\t\t0x80\n#define\t\tbPowerThres\t\t\t0x300\n#define\t\tbRxAGCEn\t\t\t\t0x1\n#define\t\tbRxAGCTogetherEn\t\t0x2\n#define\t\tbRxAGCMin\t\t\t\t0x4\n#define\t\tbRxHP_Ini\t\t\t\t0x7\n#define\t\tbRxHP_TRLNA\t\t\t0x70\n#define\t\tbRxHP_RSSI\t\t\t\t0x700\n#define\t\tbRxHP_BBP1\t\t\t\t0x7000\n#define\t\tbRxHP_BBP2\t\t\t\t0x70000\n#define\t\tbRxHP_BBP3\t\t\t\t0x700000\n#define\t\tbRSSI_H\t\t\t\t\t0x7f0000     /* the threshold for high power */\n#define\t\tbRSSI_Gen\t\t\t\t0x7f000000   /* the threshold for ant diversity */\n#define\t\tbRxSettle_TRSW\t\t\t0x7\n#define\t\tbRxSettle_LNA\t\t\t0x38\n#define\t\tbRxSettle_RSSI\t\t\t0x1c0\n#define\t\tbRxSettle_BBP\t\t\t0xe00\n#define\t\tbRxSettle_RxHP\t\t\t0x7000\n#define\t\tbRxSettle_AntSW_RSSI\t0x38000\n#define\t\tbRxSettle_AntSW\t\t0xc0000\n#define\t\tbRxProcessTime_DAGC\t0x300000\n#define\t\tbRxSettle_HSSI\t\t\t0x400000\n#define\t\tbRxProcessTime_BBPPW\t0x800000\n#define\t\tbRxAntennaPowerShift\t0x3000000\n#define\t\tbRSSITableSelect\t\t0xc000000\n#define\t\tbRxHP_Final\t\t\t\t0x7000000\n#define\t\tbRxHTSettle_BBP\t\t\t0x7\n#define\t\tbRxHTSettle_HSSI\t\t0x8\n#define\t\tbRxHTSettle_RxHP\t\t0x70\n#define\t\tbRxHTSettle_BBPPW\t\t0x80\n#define\t\tbRxHTSettle_Idle\t\t0x300\n#define\t\tbRxHTSettle_Reserved\t0x1c00\n#define\t\tbRxHTRxHPEn\t\t\t0x8000\n#define\t\tbRxHTAGCFreezeThres\t0x30000\n#define\t\tbRxHTAGCTogetherEn\t0x40000\n#define\t\tbRxHTAGCMin\t\t\t0x80000\n#define\t\tbRxHTAGCEn\t\t\t\t0x100000\n#define\t\tbRxHTDAGCEn\t\t\t0x200000\n#define\t\tbRxHTRxHP_BBP\t\t\t0x1c00000\n#define\t\tbRxHTRxHP_Final\t\t0xe0000000\n#define\t\tbRxPWRatioTH\t\t\t0x3\n#define\t\tbRxPWRatioEn\t\t\t0x4\n#define\t\tbRxMFHold\t\t\t\t0x3800\n#define\t\tbRxPD_Delay_TH1\t\t0x38\n#define\t\tbRxPD_Delay_TH2\t\t0x1c0\n#define\t\tbRxPD_DC_COUNT_MAX\t0x600\n/* #define bRxMF_Hold               0x3800 */\n#define\t\tbRxPD_Delay_TH\t\t\t0x8000\n#define\t\tbRxProcess_Delay\t\t0xf0000\n#define\t\tbRxSearchrange_GI2_Early\t0x700000\n#define\t\tbRxFrame_Guard_Counter_L\t0x3800000\n#define\t\tbRxSGI_Guard_L\t\t\t0xc000000\n#define\t\tbRxSGI_Search_L\t\t0x30000000\n#define\t\tbRxSGI_TH\t\t\t\t0xc0000000\n#define\t\tbDFSCnt0\t\t\t\t0xff\n#define\t\tbDFSCnt1\t\t\t\t0xff00\n#define\t\tbDFSFlag\t\t\t\t0xf0000\n#define\t\tbMFWeightSum\t\t\t0x300000\n#define\t\tbMinIdxTH\t\t\t\t0x7f000000\n#define\t\tbDAFormat\t\t\t\t0x40000\n#define\t\tbTxChEmuEnable\t\t0x01000000\n#define\t\tbTRSWIsolation_A\t\t0x7f\n#define\t\tbTRSWIsolation_B\t\t0x7f00\n#define\t\tbTRSWIsolation_C\t\t0x7f0000\n#define\t\tbTRSWIsolation_D\t\t0x7f000000\n#define\t\tbExtLNAGain\t\t\t\t0x7c00\n\n/* 6. PageE(0xE00) */\n#define\t\tbSTBCEn\t\t\t\t0x4\t/* Useless */\n#define\t\tbAntennaMapping\t\t0x10\n#define\t\tbNss\t\t\t\t\t0x20\n#define\t\tbCFOAntSumD\t\t\t0x200\n#define\t\tbPHYCounterReset\t\t0x8000000\n#define\t\tbCFOReportGet\t\t\t0x4000000\n#define\t\tbOFDMContinueTx\t\t0x10000000\n#define\t\tbOFDMSingleCarrier\t\t0x20000000\n#define\t\tbOFDMSingleTone\t\t0x40000000\n/* #define bRxPath1                 0x01 */\n/* #define bRxPath2                 0x02 */\n/* #define bRxPath3                 0x04 */\n/* #define bRxPath4                 0x08 */\n/* #define bTxPath1                 0x10 */\n/* #define bTxPath2                 0x20 */\n#define\t\tbHTDetect\t\t\t0x100\n#define\t\tbCFOEn\t\t\t\t0x10000\n#define\t\tbCFOValue\t\t\t0xfff00000\n#define\t\tbSigTone_Re\t\t0x3f\n#define\t\tbSigTone_Im\t\t0x7f00\n#define\t\tbCounter_CCA\t\t0xffff\n#define\t\tbCounter_ParityFail\t0xffff0000\n#define\t\tbCounter_RateIllegal\t\t0xffff\n#define\t\tbCounter_CRC8Fail\t0xffff0000\n#define\t\tbCounter_MCSNoSupport\t0xffff\n#define\t\tbCounter_FastSync\t0xffff\n#define\t\tbShortCFO\t\t\t0xfff\n#define\t\tbShortCFOTLength\t12   /* total */\n#define\t\tbShortCFOFLength\t11   /* fraction */\n#define\t\tbLongCFO\t\t\t0x7ff\n#define\t\tbLongCFOTLength\t11\n#define\t\tbLongCFOFLength\t11\n#define\t\tbTailCFO\t\t\t0x1fff\n#define\t\tbTailCFOTLength\t\t13\n#define\t\tbTailCFOFLength\t\t12\n#define\t\tbmax_en_pwdB\t\t0xffff\n#define\t\tbCC_power_dB\t\t0xffff0000\n#define\t\tbnoise_pwdB\t\t0xffff\n#define\t\tbPowerMeasTLength\t10\n#define\t\tbPowerMeasFLength\t3\n#define\t\tbRx_HT_BW\t\t\t0x1\n#define\t\tbRxSC\t\t\t\t0x6\n#define\t\tbRx_HT\t\t\t\t0x8\n#define\t\tbNB_intf_det_on\t\t0x1\n#define\t\tbIntf_win_len_cfg\t0x30\n#define\t\tbNB_Intf_TH_cfg\t\t0x1c0\n#define\t\tbRFGain\t\t\t\t0x3f\n#define\t\tbTableSel\t\t\t0x40\n#define\t\tbTRSW\t\t\t\t0x80\n#define\t\tbRxSNR_A\t\t\t0xff\n#define\t\tbRxSNR_B\t\t\t0xff00\n#define\t\tbRxSNR_C\t\t\t0xff0000\n#define\t\tbRxSNR_D\t\t\t0xff000000\n#define\t\tbSNREVMTLength\t\t8\n#define\t\tbSNREVMFLength\t\t1\n#define\t\tbCSI1st\t\t\t\t0xff\n#define\t\tbCSI2nd\t\t\t\t0xff00\n#define\t\tbRxEVM1st\t\t\t0xff0000\n#define\t\tbRxEVM2nd\t\t\t0xff000000\n#define\t\tbSIGEVM\t\t\t0xff\n#define\t\tbPWDB\t\t\t\t0xff00\n#define\t\tbSGIEN\t\t\t\t0x10000\n\n#define\t\tbSFactorQAM1\t\t0xf\t/* Useless */\n#define\t\tbSFactorQAM2\t\t0xf0\n#define\t\tbSFactorQAM3\t\t0xf00\n#define\t\tbSFactorQAM4\t\t0xf000\n#define\t\tbSFactorQAM5\t\t0xf0000\n#define\t\tbSFactorQAM6\t\t0xf0000\n#define\t\tbSFactorQAM7\t\t0xf00000\n#define\t\tbSFactorQAM8\t\t0xf000000\n#define\t\tbSFactorQAM9\t\t0xf0000000\n#define\t\tbCSIScheme\t\t\t0x100000\n\n#define\t\tbNoiseLvlTopSet\t\t0x3\t/* Useless */\n#define\t\tbChSmooth\t\t\t0x4\n#define\t\tbChSmoothCfg1\t\t0x38\n#define\t\tbChSmoothCfg2\t\t0x1c0\n#define\t\tbChSmoothCfg3\t\t0xe00\n#define\t\tbChSmoothCfg4\t\t0x7000\n#define\t\tbMRCMode\t\t\t0x800000\n#define\t\tbTHEVMCfg\t\t\t0x7000000\n\n#define\t\tbLoopFitType\t\t0x1\t/* Useless */\n#define\t\tbUpdCFO\t\t\t0x40\n#define\t\tbUpdCFOOffData\t\t0x80\n#define\t\tbAdvUpdCFO\t\t\t0x100\n#define\t\tbAdvTimeCtrl\t\t0x800\n#define\t\tbUpdClko\t\t\t0x1000\n#define\t\tbFC\t\t\t\t\t0x6000\n#define\t\tbTrackingMode\t\t0x8000\n#define\t\tbPhCmpEnable\t\t0x10000\n#define\t\tbUpdClkoLTF\t\t0x20000\n#define\t\tbComChCFO\t\t\t0x40000\n#define\t\tbCSIEstiMode\t\t0x80000\n#define\t\tbAdvUpdEqz\t\t\t0x100000\n#define\t\tbUChCfg\t\t\t\t0x7000000\n#define\t\tbUpdEqz\t\t\t0x8000000\n\n/* Rx Pseduo noise */\n#define\t\tbRxPesudoNoiseOn\t\t0x20000000\t/* Useless */\n#define\t\tbRxPesudoNoise_A\t\t0xff\n#define\t\tbRxPesudoNoise_B\t\t0xff00\n#define\t\tbRxPesudoNoise_C\t\t0xff0000\n#define\t\tbRxPesudoNoise_D\t\t0xff000000\n#define\t\tbPesudoNoiseState_A\t0xffff\n#define\t\tbPesudoNoiseState_B\t0xffff0000\n#define\t\tbPesudoNoiseState_C\t0xffff\n#define\t\tbPesudoNoiseState_D\t0xffff0000\n\n/* 7. RF Register\n * Zebra1 */\n#define\t\tbZebra1_HSSIEnable\t\t0x8\t\t/* Useless */\n#define\t\tbZebra1_TRxControl\t\t0xc00\n#define\t\tbZebra1_TRxGainSetting\t0x07f\n#define\t\tbZebra1_RxCorner\t\t0xc00\n#define\t\tbZebra1_TxChargePump\t0x38\n#define\t\tbZebra1_RxChargePump\t0x7\n#define\t\tbZebra1_ChannelNum\t0xf80\n#define\t\tbZebra1_TxLPFBW\t\t0x400\n#define\t\tbZebra1_RxLPFBW\t\t0x600\n\n/* Zebra4 */\n#define\t\tbRTL8256RegModeCtrl1\t0x100\t/* Useless */\n#define\t\tbRTL8256RegModeCtrl0\t0x40\n#define\t\tbRTL8256_TxLPFBW\t\t0x18\n#define\t\tbRTL8256_RxLPFBW\t\t0x600\n\n/* RTL8258 */\n#define\t\tbRTL8258_TxLPFBW\t\t0xc\t/* Useless */\n#define\t\tbRTL8258_RxLPFBW\t\t0xc00\n#define\t\tbRTL8258_RSSILPFBW\t0xc0\n\n\n/*\n * Other Definition\n *   */\n\n/* byte endable for sb_write */\n#define\t\tbByte0\t\t\t\t0x1\t/* Useless */\n#define\t\tbByte1\t\t\t\t0x2\n#define\t\tbByte2\t\t\t\t0x4\n#define\t\tbByte3\t\t\t\t0x8\n#define\t\tbWord0\t\t\t\t0x3\n#define\t\tbWord1\t\t\t\t0xc\n#define\t\tbDWord\t\t\t\t0xf\n\n/* for PutRegsetting & GetRegSetting BitMask */\n#define\t\tbMaskByte0\t\t\t0xff\t/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */\n#define\t\tbMaskByte1\t\t\t0xff00\n#define\t\tbMaskByte2\t\t\t0xff0000\n#define\t\tbMaskByte3\t\t\t0xff000000\n#define\t\tbMaskHWord\t\t0xffff0000\n#define\t\tbMaskLWord\t\t\t0x0000ffff\n#define\t\tbMaskDWord\t\t0xffffffff\n#define\t\tbMaskH3Bytes\t\t0xffffff00\n#define\t\tbMask12Bits\t\t\t0xfff\n#define\t\tbMaskH4Bits\t\t\t0xf0000000\n#define\t\tbMaskOFDM_D\t\t0xffc00000\n#define\t\tbMaskCCK\t\t\t0x3f3f3f3f\n\n\n#define\t\tbEnable\t\t\t0x1\t/* Useless */\n#define\t\tbDisable\t\t0x0\n\n#define\t\tLeftAntenna\t\t0x0\t/* Useless */\n#define\t\tRightAntenna\t0x1\n\n#define\t\ttCheckTxStatus\t\t500   /* 500ms // Useless */\n#define\t\ttUpdateRxCounter\t100   /* 100ms */\n\n#define\t\trateCCK\t\t0\t/* Useless */\n#define\t\trateOFDM\t1\n#define\t\trateHT\t\t2\n\n/* define Register-End */\n#define\t\tbPMAC_End\t\t\t0x1ff\t/* Useless */\n#define\t\tbFPGAPHY0_End\t\t0x8ff\n#define\t\tbFPGAPHY1_End\t\t0x9ff\n#define\t\tbCCKPHY0_End\t\t0xaff\n#define\t\tbOFDMPHY0_End\t\t0xcff\n#define\t\tbOFDMPHY1_End\t\t0xdff\n\n/* define max debug item in each debug page\n * #define bMaxItem_FPGA_PHY0        0x9\n * #define bMaxItem_FPGA_PHY1        0x3\n * #define bMaxItem_PHY_11B          0x16\n * #define bMaxItem_OFDM_PHY0        0x29\n * #define bMaxItem_OFDM_PHY1        0x0 */\n\n#define\t\tbPMACControl\t\t0x0\t\t/* Useless */\n#define\t\tbWMACControl\t\t0x1\n#define\t\tbWNICControl\t\t0x2\n\n#define\t\tPathA\t\t\t0x0\t/* Useless */\n#define\t\tPathB\t\t\t0x1\n#define\t\tPathC\t\t\t0x2\n#define\t\tPathD\t\t\t0x3\n\n#endif\n"
  },
  {
    "path": "include/Hal8723DPwrSeq.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef REALTEK_POWER_SEQUENCE_8723D\n#define REALTEK_POWER_SEQUENCE_8723D\n\n/* #include \"PwrSeqCmd.h\" */\n#include \"HalPwrSeqCmd.h\"\n\n/*\n\tCheck document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd\n\tThere are 6 HW Power States:\n\t0: POFF--Power Off\n\t1: PDN--Power Down\n\t2: CARDEMU--Card Emulation\n\t3: ACT--Active Mode\n\t4: LPS--Low Power State\n\t5: SUS--Suspend\n\n\tThe transition from different states are defined below\n\tTRANS_CARDEMU_TO_ACT\n\tTRANS_ACT_TO_CARDEMU\n\tTRANS_CARDEMU_TO_SUS\n\tTRANS_SUS_TO_CARDEMU\n\tTRANS_CARDEMU_TO_PDN\n\tTRANS_ACT_TO_LPS\n\tTRANS_LPS_TO_ACT\n\n\tTRANS_END\n*/\n#define\tRTL8723D_TRANS_CARDEMU_TO_ACT_STEPS\t27\n#define\tRTL8723D_TRANS_ACT_TO_CARDEMU_STEPS\t8\n#define\tRTL8723D_TRANS_CARDEMU_TO_SUS_STEPS\t7\n#define\tRTL8723D_TRANS_SUS_TO_CARDEMU_STEPS\t5\n#define\tRTL8723D_TRANS_CARDEMU_TO_CARDDIS_STEPS\t8\n#define\tRTL8723D_TRANS_CARDDIS_TO_CARDEMU_STEPS\t7\n#define\tRTL8723D_TRANS_CARDEMU_TO_PDN_STEPS\t4\n#define\tRTL8723D_TRANS_PDN_TO_CARDEMU_STEPS\t1\n#define\tRTL8723D_TRANS_ACT_TO_LPS_STEPS\t\t13\n#define\tRTL8723D_TRANS_LPS_TO_ACT_STEPS\t\t11\n#define\tRTL8723D_TRANS_END_STEPS\t1\n\n\n#define RTL8723D_TRANS_CARDEMU_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/\t\\\n\t{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \\\n\t{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \\\n\t{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)},/* Disable USB suspend */\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},/* wait till 0x04[17] = 1    power ready*/\t\\\n\t{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0},/* Enable USB suspend */\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* release WLON reset  0x04[16]=1*/ \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0}, \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* disable HWPDN 0x04[15]=0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},/* disable WL suspend*/ \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* polling until return 0*/ \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},/**/ \\\n\t{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},/* Enable WL control XTAL setting*/ \\\n\t{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable falling edge triggering interrupt*/\\\n\t{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable GPIO9 interrupt mode*/\\\n\t{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Enable GPIO9 input mode*/\\\n\t{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/*Enable HSISR GPIO[C:0] interrupt*/\\\n\t{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable HSISR GPIO9 interrupt*/\\\n\t{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)},/*For GPIO9 internal pull high setting by test chip*/\\\n\t{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},/*For GPIO9 internal pull high setting*/\\\n\t{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S1*/\\\n\t{0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S0*/\\\n\t{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/*enable RF path S1*/\\\n\t{0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/*enalbe RF path S0*/\\\n\n\n#define RTL8723D_TRANS_ACT_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/\t\t\t\t\t\t\t\t\\\n\t/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x2[0]=0 Reset BB, RF enter Power Down mode*/ \\\n\t{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Enable rising edge triggering interrupt*/ \\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* release WLON reset  0x04[16]=1*/ \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \\\n\t{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0},/* Enable BT control XTAL setting*/\\\n\t{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \\\n\t{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\\\n\n\n#define RTL8723D_TRANS_CARDEMU_TO_SUS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/\n\n#define RTL8723D_TRANS_SUS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/ \\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\n\n\n#define RTL8723D_TRANS_CARDEMU_TO_CARDDIS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, /*0x04[10] = 1, enable SW LPS*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend*/\t\\\n\t{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/\n\n#define RTL8723D_TRANS_CARDDIS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/ \\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\\\n\t{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/\n\n\n#define RTL8723D_TRANS_CARDEMU_TO_PDN\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/\n\n#define RTL8723D_TRANS_PDN_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/\n\n#define RTL8723D_TRANS_ACT_TO_LPS\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/\t\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/\t\\\n\t{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/*CCK and OFDM are disabled, and clock are gated*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/\t\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/\t\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \\\n\t{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/\t\\\n\t{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},/*Respond TxOK to scheduler*/\t\\\n\n\n#define RTL8723D_TRANS_LPS_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\\\n\t{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\\\n\t{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*.\t0x08[4] = 0  switch TSF to 40M*/\\\n\t{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0  TSF in 40M*/\\\n\t{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, /*.\t0x29[7:6] = 2b'00\t enable BB clock*/\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, /*.\t0x101[1] = 1*/\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.\t0x100[7:0] = 0xFF\t enable WMAC TRX*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT1 | BIT0}, /*.\t0x02[1:0] = 2b'11\t enable BB macro*/\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.\t0x522 = 0*/\n\n#define RTL8723D_TRANS_END\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/\t\t\t\t\t\t\t\t\\\n\t{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},\n\n\n\textern WLAN_PWR_CFG rtl8723D_power_on_flow[RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723D_radio_off_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723D_card_disable_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_CARDDIS_STEPS + RTL8723D_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723D_card_enable_flow[RTL8723D_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723D_suspend_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723D_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723D_resume_flow[RTL8723D_TRANS_SUS_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723D_hwpdn_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723D_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723D_enter_lps_flow[RTL8723D_TRANS_ACT_TO_LPS_STEPS + RTL8723D_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723D_leave_lps_flow[RTL8723D_TRANS_LPS_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];\n\n#endif\n"
  },
  {
    "path": "include/Hal8723PwrSeq.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HAL8723PWRSEQ_H__\n#define __HAL8723PWRSEQ_H__\n/*\n\tCheck document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd\n\tThere are 6 HW Power States:\n\t0: POFF--Power Off\n\t1: PDN--Power Down\n\t2: CARDEMU--Card Emulation\n\t3: ACT--Active Mode\n\t4: LPS--Low Power State\n\t5: SUS--Suspend\n\n\tThe transision from different states are defined below\n\tTRANS_CARDEMU_TO_ACT\n\tTRANS_ACT_TO_CARDEMU\n\tTRANS_CARDEMU_TO_SUS\n\tTRANS_SUS_TO_CARDEMU\n\tTRANS_CARDEMU_TO_PDN\n\tTRANS_ACT_TO_LPS\n\tTRANS_LPS_TO_ACT\n\n\tTRANS_END\n*/\n#include \"HalPwrSeqCmd.h\"\n\n#define\tRTL8723A_TRANS_CARDEMU_TO_ACT_STEPS\t15\n#define\tRTL8723A_TRANS_ACT_TO_CARDEMU_STEPS\t15\n#define\tRTL8723A_TRANS_CARDEMU_TO_SUS_STEPS\t15\n#define\tRTL8723A_TRANS_SUS_TO_CARDEMU_STEPS\t15\n#define\tRTL8723A_TRANS_CARDEMU_TO_PDN_STEPS\t15\n#define\tRTL8723A_TRANS_PDN_TO_CARDEMU_STEPS\t15\n#define\tRTL8723A_TRANS_ACT_TO_LPS_STEPS\t15\n#define\tRTL8723A_TRANS_LPS_TO_ACT_STEPS\t15\n#define\tRTL8723A_TRANS_END_STEPS\t1\n\n\n#define RTL8723A_TRANS_CARDEMU_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \\\n\t{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/\t\\\n\t{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \\\n\t{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/\t\\\n\t{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 1},/*0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */\\\n\n#define RTL8723A_TRANS_ACT_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/\t\\\n\t{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/\t\\\n\t{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \\\n\t{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/   \\\n\n\n#define RTL8723A_TRANS_CARDEMU_TO_SUS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/\n\n#define RTL8723A_TRANS_SUS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\n\n#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/\t\\\n\t{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/\n\n#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\\\n\t{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/\n\n\n#define RTL8723A_TRANS_CARDEMU_TO_PDN\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/\n\n#define RTL8723A_TRANS_PDN_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/\n\n#define RTL8723A_TRANS_ACT_TO_LPS\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/\t\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/\t\\\n\t{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/\t\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/\t\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\t\\\n\t{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/\t\\\n\t{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/\t\\\n\n\n#define RTL8723A_TRANS_LPS_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\\\n\t{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\\\n\t{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.\t0x08[4] = 0\t\t switch TSF to 40M*/\\\n\t{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\\\n\t{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.\t0x29[7:6] = 2b'00\t enable BB clock*/\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.\t0x101[1] = 1*/\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.\t0x100[7:0] = 0xFF\t enable WMAC TRX*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.\t0x02[1:0] = 2b'11\t enable BB macro*/\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.\t0x522 = 0*/\n\n#define RTL8723A_TRANS_END\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},\n\n\n\textern WLAN_PWR_CFG rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723A_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723A_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS + RTL8723A_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS];\n\n#endif\n"
  },
  {
    "path": "include/Hal8812PhyCfg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8812PHYCFG_H__\n#define __INC_HAL8812PHYCFG_H__\n\n\n/*--------------------------Define Parameters-------------------------------*/\n#define LOOP_LIMIT\t\t\t\t5\n#define MAX_STALL_TIME\t\t\t50\t\t/* us */\n#define AntennaDiversityValue\t0x80\t/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */\n#define MAX_TXPWR_IDX_NMODE_92S\t63\n#define Reset_Cnt_Limit\t\t\t3\n\n\n#ifdef CONFIG_PCI_HCI\n\t#define MAX_AGGR_NUM\t0x0B\n#else\n\t#define MAX_AGGR_NUM\t0x07\n#endif /* CONFIG_PCI_HCI */\n\n\n/*--------------------------Define Parameters-------------------------------*/\n\n/*------------------------------Define structure----------------------------*/\n\n\n/* BB/RF related */\n\n/*------------------------------Define structure----------------------------*/\n\n\n/*------------------------Export global variable----------------------------*/\n/*------------------------Export global variable----------------------------*/\n\n\n/*------------------------Export Marco Definition---------------------------*/\n/*------------------------Export Marco Definition---------------------------*/\n\n\n/*--------------------------Exported Function prototype---------------------*/\n/*\n * BB and RF register read/write\n *   */\nu32\tPHY_QueryBBReg8812(PADAPTER\tAdapter,\n\t\t\t\tu32\t\t\tRegAddr,\n\t\t\t\tu32\t\t\tBitMask);\nvoid\tPHY_SetBBReg8812(PADAPTER\t\tAdapter,\n\t\t\t\tu32\t\t\tRegAddr,\n\t\t\t\tu32\t\t\tBitMask,\n\t\t\t\tu32\t\t\tData);\nu32\tPHY_QueryRFReg8812(PADAPTER\tAdapter,\n\t\t\t\tenum rf_path\teRFPath,\n\t\t\t\tu32\t\t\tRegAddr,\n\t\t\t\tu32\t\t\tBitMask);\nvoid\tPHY_SetRFReg8812(PADAPTER\t\tAdapter,\n\t\t\t\tenum rf_path\teRFPath,\n\t\t\t\tu32\t\t\tRegAddr,\n\t\t\t\tu32\t\t\tBitMask,\n\t\t\t\tu32\t\t\tData);\n\n/*\n * Initialization related function\n *\n * MAC/BB/RF HAL config */\nint\tPHY_MACConfig8812(PADAPTER\tAdapter);\nint\tPHY_BBConfig8812(PADAPTER\tAdapter);\nvoid\tPHY_BB8812_Config_1T(PADAPTER\tAdapter);\nint\tPHY_RFConfig8812(PADAPTER\tAdapter);\n\n/* RF config */\n\ns32\nPHY_SwitchWirelessBand8812(\n\t\tPADAPTER\t\tAdapter,\n\t\tu8\t\t\tBand\n);\n\n/*\n * BB TX Power R/W\n *   */\nvoid\tPHY_SetTxPowerLevel8812(PADAPTER\tAdapter, u8\tChannel);\n\nu8 PHY_GetTxPowerIndex_8812A(\n\t\tPADAPTER\t\t\tpAdapter,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate,\n\t\tu8\t\t\t\t\tBandWidth,\n\t\tu8\t\t\t\t\tChannel,\n\tstruct txpwr_idx_comp *tic\n);\n\nu32 phy_get_tx_bb_swing_8812a(\n\t\tPADAPTER\tAdapter,\n\t\tBAND_TYPE\tBand,\n\t\tenum rf_path\tRFPath\n);\n\nvoid\nPHY_SetTxPowerIndex_8812A(\n\t\tPADAPTER\t\tAdapter,\n\t\tu32\t\t\t\tPowerIndex,\n\t\tenum rf_path\t\tRFPath,\n\t\tu8\t\t\t\tRate\n);\n\n/*\n * channel switch related funciton\n *   */\nvoid\nPHY_SetSwChnlBWMode8812(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu8\t\t\t\t\tchannel,\n\t\tenum channel_width\tBandwidth,\n\t\tu8\t\t\t\t\tOffset40,\n\t\tu8\t\t\t\t\tOffset80\n);\n\n/*\n * BB/MAC/RF other monitor API\n *   */\n\nvoid\nphy_set_rf_path_switch_8812a(\n\t\tstruct dm_struct\t\t*phydm,\n\t\tbool\t\tbMain\n);\n\n/*--------------------------Exported Function prototype---------------------*/\n#endif /* __INC_HAL8192CPHYCFG_H */\n"
  },
  {
    "path": "include/Hal8812PhyReg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8812PHYREG_H__\n#define __INC_HAL8812PHYREG_H__\n/*--------------------------Define Parameters-------------------------------*/\n/*\n * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00\n * 3. RF register 0x00-2E\n * 4. Bit Mask for BB/RF register\n * 5. Other defintion for BB/RF R/W\n *   */\n\n\n/* BB Register Definition */\n\n#define rCCAonSec_Jaguar\t\t0x838\n#define rPwed_TH_Jaguar\t\t\t0x830\n\n/* BW and sideband setting */\n#define rBWIndication_Jaguar\t\t0x834\n#define rL1PeakTH_Jaguar\t\t\t0x848\n#define rFPGA0_XA_LSSIReadBack\t0x8a0\t/*Tranceiver LSSI Readback*/\n#define rRFMOD_Jaguar\t\t\t0x8ac\t/* RF mode */\n#define rADC_Buf_Clk_Jaguar\t\t0x8c4\n#define rRFECTRL_Jaguar\t\t\t0x900\n#define bRFMOD_Jaguar\t\t\t0xc3\n#define rCCK_System_Jaguar\t\t0xa00   /* for cck sideband */\n#define bCCK_System_Jaguar\t\t0x10\n\n/* Block & Path enable */\n#define rOFDMCCKEN_Jaguar \t\t0x808 /* OFDM/CCK block enable */\n#define bOFDMEN_Jaguar\t\t\t0x20000000\n#define bCCKEN_Jaguar\t\t\t0x10000000\n#define rRxPath_Jaguar\t\t\t0x808\t/* Rx antenna */\n#define bRxPath_Jaguar\t\t\t0xff\n#define rTxPath_Jaguar\t\t\t0x80c\t/* Tx antenna */\n#define bTxPath_Jaguar\t\t\t0x0fffffff\n#define rCCK_RX_Jaguar\t\t\t0xa04\t/* for cck rx path selection */\n#define bCCK_RX_Jaguar\t\t\t0x0c000000\n#define rVhtlen_Use_Lsig_Jaguar\t0x8c3\t/* Use LSIG for VHT length */\n\n/* RF read/write-related */\n#define rHSSIRead_Jaguar\t\t\t0x8b0  /* RF read addr */\n#define bHSSIRead_addr_Jaguar\t\t0xff\n#define bHSSIRead_trigger_Jaguar\t0x100\n#define rA_PIRead_Jaguar\t\t\t0xd04 /* RF readback with PI */\n#define rB_PIRead_Jaguar\t\t\t0xd44 /* RF readback with PI */\n#define rA_SIRead_Jaguar\t\t\t0xd08 /* RF readback with SI */\n#define rB_SIRead_Jaguar\t\t\t0xd48 /* RF readback with SI */\n#define rRead_data_Jaguar\t\t\t0xfffff\n#define rA_LSSIWrite_Jaguar\t\t\t0xc90 /* RF write addr */\n#define rB_LSSIWrite_Jaguar\t\t\t0xe90 /* RF write addr */\n#define bLSSIWrite_data_Jaguar\t\t0x000fffff\n#define bLSSIWrite_addr_Jaguar\t\t0x0ff00000\n\n\n\n/* YN: mask the following register definition temporarily */\n#define rFPGA0_XA_RFInterfaceOE\t\t\t0x860\t/* RF Channel switch */\n#define rFPGA0_XB_RFInterfaceOE\t\t\t0x864\n\n#define rFPGA0_XAB_RFInterfaceSW\t\t0x870\t/* RF Interface Software Control */\n#define rFPGA0_XCD_RFInterfaceSW\t\t0x874\n\n/* #define rFPGA0_XAB_RFParameter\t\t0x878 */\t/* RF Parameter\n * #define rFPGA0_XCD_RFParameter\t\t0x87c */\n\n/* #define rFPGA0_AnalogParameter1\t\t0x880 */\t/* Crystal cap setting RF-R/W protection for parameter4??\n * #define rFPGA0_AnalogParameter2\t\t0x884\n * #define rFPGA0_AnalogParameter3\t\t0x888\n * #define rFPGA0_AdDaClockEn\t\t\t0x888 */\t/* enable ad/da clock1 for dual-phy\n * #define rFPGA0_AnalogParameter4\t\t0x88c */\n\n\n/* CCK TX scaling */\n#define rCCK_TxFilter1_Jaguar\t\t0xa20\n#define bCCK_TxFilter1_C0_Jaguar\t0x00ff0000\n#define bCCK_TxFilter1_C1_Jaguar\t\t0xff000000\n#define rCCK_TxFilter2_Jaguar\t\t0xa24\n#define bCCK_TxFilter2_C2_Jaguar\t\t0x000000ff\n#define bCCK_TxFilter2_C3_Jaguar\t\t0x0000ff00\n#define bCCK_TxFilter2_C4_Jaguar\t\t0x00ff0000\n#define bCCK_TxFilter2_C5_Jaguar\t\t0xff000000\n#define rCCK_TxFilter3_Jaguar\t\t0xa28\n#define bCCK_TxFilter3_C6_Jaguar\t\t0x000000ff\n#define bCCK_TxFilter3_C7_Jaguar\t\t0x0000ff00\n\n\n/* YN: mask the following register definition temporarily\n * #define rPdp_AntA\t\t\t\t\t0xb00\n * #define rPdp_AntA_4\t\t\t\t0xb04\n * #define rConfig_Pmpd_AntA\t\t\t0xb28\n * #define rConfig_AntA\t\t\t\t\t0xb68\n * #define rConfig_AntB\t\t\t\t\t0xb6c\n * #define rPdp_AntB\t\t\t\t\t0xb70\n * #define rPdp_AntB_4\t\t\t\t\t0xb74\n * #define rConfig_Pmpd_AntB\t\t\t0xb98\n * #define rAPK\t\t\t\t\t\t\t0xbd8 */\n\n/* RXIQC */\n#define rA_RxIQC_AB_Jaguar    \t0xc10  /* RxIQ imblance matrix coeff. A & B */\n#define rA_RxIQC_CD_Jaguar    \t0xc14  /* RxIQ imblance matrix coeff. C & D */\n#define rA_TxScale_Jaguar \t\t0xc1c  /* Pah_A TX scaling factor */\n#define rB_TxScale_Jaguar \t\t0xe1c  /* Path_B TX scaling factor */\n#define rB_RxIQC_AB_Jaguar    \t0xe10  /* RxIQ imblance matrix coeff. A & B */\n#define rB_RxIQC_CD_Jaguar    \t0xe14  /* RxIQ imblance matrix coeff. C & D */\n#define b_RxIQC_AC_Jaguar\t\t0x02ff  /* bit mask for IQC matrix element A & C */\n#define b_RxIQC_BD_Jaguar\t\t0x02ff0000 /* bit mask for IQC matrix element A & C */\n\n\n/* DIG-related */\n#define rA_IGI_Jaguar\t\t\t\t0xc50\t/* Initial Gain for path-A */\n#define rB_IGI_Jaguar\t\t\t\t0xe50\t/* Initial Gain for path-B */\n#define rOFDM_FalseAlarm1_Jaguar\t0xf48  /* counter for break */\n#define rOFDM_FalseAlarm2_Jaguar\t0xf4c  /* counter for spoofing */\n#define rCCK_FalseAlarm_Jaguar        \t0xa5c /* counter for cck false alarm */\n#define b_FalseAlarm_Jaguar\t\t\t0xffff\n#define rCCK_CCA_Jaguar\t\t\t\t0xa08\t/* cca threshold */\n#define bCCK_CCA_Jaguar\t\t\t\t0x00ff0000\n\n/* Tx Power Ttraining-related */\n#define rA_TxPwrTraing_Jaguar\t\t0xc54\n#define rB_TxPwrTraing_Jaguar\t\t0xe54\n\n/* Report-related */\n#define rOFDM_ShortCFOAB_Jaguar\t0xf60\n#define rOFDM_LongCFOAB_Jaguar\t\t0xf64\n#define rOFDM_EndCFOAB_Jaguar\t\t0xf70\n#define rOFDM_AGCReport_Jaguar\t\t0xf84\n#define rOFDM_RxSNR_Jaguar\t\t\t0xf88\n#define rOFDM_RxEVMCSI_Jaguar\t\t0xf8c\n#define rOFDM_SIGReport_Jaguar\t\t0xf90\n\n/* Misc functions */\n#define rEDCCA_Jaguar\t\t\t\t0x8a4 /* EDCCA */\n#define bEDCCA_Jaguar\t\t\t\t0xffff\n#define rAGC_table_Jaguar\t\t\t0x82c   /* AGC tabel select */\n#define bAGC_table_Jaguar\t\t\t0x3\n#define b_sel5g_Jaguar    \t\t\t\t0x1000 /* sel5g */\n#define b_LNA_sw_Jaguar\t\t\t\t0x8000 /* HW/WS control for LNA */\n#define rFc_area_Jaguar\t\t\t\t0x860   /* fc_area */\n#define bFc_area_Jaguar\t\t\t\t0x1ffe000\n#define rSingleTone_ContTx_Jaguar\t0x914\n\n/* RFE */\n#define rA_RFE_Pinmux_Jaguar\t0xcb0  /* Path_A RFE cotrol pinmux */\n#define rB_RFE_Pinmux_Jaguar\t0xeb0 /* Path_B RFE control pinmux */\n#define rA_RFE_Inv_Jaguar\t\t0xcb4  /* Path_A RFE cotrol   */\n#define rB_RFE_Inv_Jaguar\t\t0xeb4 /* Path_B RFE control */\n#define rA_RFE_Jaguar\t\t\t0xcb8  /* Path_A RFE cotrol   */\n#define rB_RFE_Jaguar\t\t\t0xeb8 /* Path_B RFE control */\n#define\trA_RFE_Inverse_Jaguar\t0xCBC\t/* Path_A RFE control inverse */\n#define\trB_RFE_Inverse_Jaguar\t0xEBC\t/* Path_B RFE control inverse */\n#define r_ANTSEL_SW_Jaguar\t\t0x900 /* ANTSEL SW Control */\n#define bMask_RFEInv_Jaguar\t\t0x3ff00000\n#define bMask_AntselPathFollow_Jaguar 0x00030000\n\n/* TX AGC */\n#define rTxAGC_A_CCK11_CCK1_JAguar\t\t\t\t0xc20\n#define rTxAGC_A_Ofdm18_Ofdm6_JAguar\t\t\t\t0xc24\n#define rTxAGC_A_Ofdm54_Ofdm24_JAguar\t\t\t0xc28\n#define rTxAGC_A_MCS3_MCS0_JAguar\t\t\t\t\t0xc2c\n#define rTxAGC_A_MCS7_MCS4_JAguar\t\t\t\t\t0xc30\n#define rTxAGC_A_MCS11_MCS8_JAguar\t\t\t\t0xc34\n#define rTxAGC_A_MCS15_MCS12_JAguar\t\t\t\t0xc38\n#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar\t0xc3c\n#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar\t0xc40\n#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar\t0xc44\n#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar\t0xc48\n#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar\t0xc4c\n#define rTxAGC_B_CCK11_CCK1_JAguar\t\t\t\t0xe20\n#define rTxAGC_B_Ofdm18_Ofdm6_JAguar\t\t\t\t0xe24\n#define rTxAGC_B_Ofdm54_Ofdm24_JAguar\t\t\t0xe28\n#define rTxAGC_B_MCS3_MCS0_JAguar\t\t\t\t\t0xe2c\n#define rTxAGC_B_MCS7_MCS4_JAguar\t\t\t\t\t0xe30\n#define rTxAGC_B_MCS11_MCS8_JAguar\t\t\t\t0xe34\n#define rTxAGC_B_MCS15_MCS12_JAguar\t\t\t\t0xe38\n#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar\t\t0xe3c\n#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar\t\t0xe40\n#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar\t\t0xe44\n#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar\t\t0xe48\n#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar\t\t0xe4c\n#define bTxAGC_byte0_Jaguar\t\t\t\t\t\t\t0xff\n#define bTxAGC_byte1_Jaguar\t\t\t\t\t\t\t0xff00\n#define bTxAGC_byte2_Jaguar\t\t\t\t\t\t\t0xff0000\n#define bTxAGC_byte3_Jaguar\t\t\t\t\t\t\t0xff000000\n\n/* IQK YN: temporaily mask this part\n * #define rFPGA0_IQK\t\t\t\t\t0xe28\n * #define rTx_IQK_Tone_A\t\t\t\t0xe30\n * #define rRx_IQK_Tone_A\t\t\t\t0xe34\n * #define rTx_IQK_PI_A\t\t\t\t\t0xe38\n * #define rRx_IQK_PI_A\t\t\t\t\t0xe3c */\n\n/* #define rTx_IQK\t\t\t\t\t\t0xe40 */\n/* #define rRx_IQK\t\t\t\t\t\t0xe44 */\n/* #define rIQK_AGC_Pts\t\t\t\t\t0xe48 */\n/* #define rIQK_AGC_Rsp\t\t\t\t\t0xe4c */\n/* #define rTx_IQK_Tone_B\t\t\t\t0xe50 */\n/* #define rRx_IQK_Tone_B\t\t\t\t0xe54 */\n/* #define rTx_IQK_PI_B\t\t\t\t\t0xe58 */\n/* #define rRx_IQK_PI_B\t\t\t\t\t0xe5c */\n/* #define rIQK_AGC_Cont\t\t\t\t0xe60 */\n\n\n/* AFE-related */\n#define rA_AFEPwr1_Jaguar\t\t\t\t\t0xc60 /* dynamic AFE power control */\n#define rA_AFEPwr2_Jaguar\t\t\t\t\t0xc64 /* dynamic AFE power control */\n#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar\t0xc68\n#define rA_Tx_CCKBBON_OFDMRFON_Jaguar\t0xc6c\n#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar\t\t0xc70\n#define rA_Tx2Tx_RXCCK_Jaguar\t\t\t\t0xc74\n#define rA_Rx_OFDM_WaitRIFS_Jaguar\t\t\t0xc78\n#define rA_Rx2Rx_BT_Jaguar\t\t\t\t\t0xc7c\n#define rA_sleep_nav_Jaguar\t\t\t\t\t0xc80\n#define rA_pmpd_Jaguar\t\t\t\t\t\t0xc84\n#define rB_AFEPwr1_Jaguar\t\t\t\t\t0xe60 /* dynamic AFE power control */\n#define rB_AFEPwr2_Jaguar\t\t\t\t\t0xe64 /* dynamic AFE power control */\n#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar\t0xe68\n#define rB_Tx_CCKBBON_OFDMRFON_Jaguar\t0xe6c\n#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar\t\t0xe70\n#define rB_Tx2Tx_RXCCK_Jaguar\t\t\t\t0xe74\n#define rB_Rx_OFDM_WaitRIFS_Jaguar\t\t\t0xe78\n#define rB_Rx2Rx_BT_Jaguar\t\t\t\t\t0xe7c\n#define rB_sleep_nav_Jaguar\t\t\t\t\t0xe80\n#define rB_pmpd_Jaguar\t\t\t\t\t\t0xe84\n\n\n/* YN: mask these registers temporaily\n * #define rTx_Power_Before_IQK_A\t\t0xe94\n * #define rTx_Power_After_IQK_A\t\t\t0xe9c */\n\n/* #define rRx_Power_Before_IQK_A\t\t0xea0 */\n/* #define rRx_Power_Before_IQK_A_2\t\t0xea4 */\n/* #define rRx_Power_After_IQK_A\t\t\t0xea8 */\n/* #define rRx_Power_After_IQK_A_2\t\t0xeac */\n\n/* #define rTx_Power_Before_IQK_B\t\t0xeb4 */\n/* #define rTx_Power_After_IQK_B\t\t\t0xebc */\n\n/* #define rRx_Power_Before_IQK_B\t\t0xec0 */\n/* #define rRx_Power_Before_IQK_B_2\t\t0xec4 */\n/* #define rRx_Power_After_IQK_B\t\t\t0xec8 */\n/* #define rRx_Power_After_IQK_B_2\t\t0xecc */\n\n\n/* RSSI Dump */\n#define rA_RSSIDump_Jaguar\t\t\t0xBF0\n#define rB_RSSIDump_Jaguar\t\t\t0xBF1\n#define rS1_RXevmDump_Jaguar\t\t0xBF4\n#define rS2_RXevmDump_Jaguar\t\t0xBF5\n#define rA_RXsnrDump_Jaguar\t\t0xBF6\n#define rB_RXsnrDump_Jaguar\t\t0xBF7\n#define rA_CfoShortDump_Jaguar\t\t0xBF8\n#define rB_CfoShortDump_Jaguar\t\t0xBFA\n#define rA_CfoLongDump_Jaguar\t\t0xBEC\n#define rB_CfoLongDump_Jaguar\t\t0xBEE\n\n\n/* RF Register\n *   */\n#define RF_AC_Jaguar\t\t\t\t0x00\t/*  */\n#define RF_RF_Top_Jaguar\t\t\t0x07\t/*  */\n#define RF_TXLOK_Jaguar\t\t\t\t0x08\t/*  */\n#define RF_TXAPK_Jaguar\t\t\t\t0x0B\n#define RF_CHNLBW_Jaguar \t\t\t0x18\t/* RF channel and BW switch */\n#define RF_RCK1_Jaguar\t\t\t\t0x1c\t/*  */\n#define RF_RCK2_Jaguar\t\t\t\t0x1d\n#define RF_RCK3_Jaguar\t\t\t0x1e\n#define RF_ModeTableAddr\t\t\t0x30\n#define RF_ModeTableData0\t\t\t0x31\n#define RF_ModeTableData1\t\t\t0x32\n#define RF_TxLCTank_Jaguar\t0x54\n#define RF_APK_Jaguar\t\t\t\t0x63\n#define RF_LCK\t\t\t\t\t\t0xB4\n#define RF_WeLut_Jaguar\t\t\t\t0xEF\n\n#define bRF_CHNLBW_MOD_AG_Jaguar\t0x70300\n#define bRF_CHNLBW_BW\t\t\t\t0xc00\n\n\n/*\n * RL6052 Register definition\n *   */\n#define RF_AC\t\t\t\t\t\t0x00\t/*  */\n#define RF_IPA_A\t\t\t\t\t0x0C\t/*  */\n#define RF_TXBIAS_A\t\t\t\t\t0x0D\n#define RF_BS_PA_APSET_G9_G11\t\t0x0E\n#define RF_MODE1\t\t\t\t\t0x10\t/*  */\n#define RF_MODE2\t\t\t\t\t0x11\t/*  */\n#define RF_CHNLBW\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define RF_RCK_OS\t\t\t\t\t0x30\t/* RF TX PA control */\n#define RF_TXPA_G1\t\t\t\t\t0x31\t/* RF TX PA control */\n#define RF_TXPA_G2\t\t\t\t\t0x32\t/* RF TX PA control */\n#define RF_TXPA_G3\t\t\t\t\t0x33\t/* RF TX PA control */\n#define RF_0x52\t\t\t\t\t\t0x52\n#define RF_WE_LUT\t\t\t\t\t0xEF\n\n#define RF_TX_GAIN_OFFSET_8812A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))\n#define RF_TX_GAIN_OFFSET_8821A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))\n\n/*\n * Bit Mask\n *\n * 1. Page1(0x100) */\n#define bBBResetB\t\t\t\t\t0x100\t/* Useless now? */\n#define bGlobalResetB\t\t\t\t0x200\n#define bOFDMTxStart\t\t\t\t0x4\n#define bCCKTxStart\t\t\t\t\t0x8\n#define bCRC32Debug\t\t\t\t\t0x100\n#define bPMACLoopback\t\t\t\t0x10\n#define bTxLSIG\t\t\t\t\t\t0xffffff\n#define bOFDMTxRate\t\t\t\t\t0xf\n#define bOFDMTxReserved\t\t\t0x10\n#define bOFDMTxLength\t\t\t\t0x1ffe0\n#define bOFDMTxParity\t\t\t\t0x20000\n#define bTxHTSIG1\t\t\t\t\t0xffffff\n#define bTxHTMCSRate\t\t\t\t0x7f\n#define bTxHTBW\t\t\t\t\t\t0x80\n#define bTxHTLength\t\t\t\t\t0xffff00\n#define bTxHTSIG2\t\t\t\t\t0xffffff\n#define bTxHTSmoothing\t\t\t\t0x1\n#define bTxHTSounding\t\t\t\t0x2\n#define bTxHTReserved\t\t\t\t0x4\n#define bTxHTAggreation\t\t\t\t0x8\n#define bTxHTSTBC\t\t\t\t\t0x30\n#define bTxHTAdvanceCoding\t\t\t0x40\n#define bTxHTShortGI\t\t\t\t\t0x80\n#define bTxHTNumberHT_LTF\t\t\t0x300\n#define bTxHTCRC8\t\t\t\t\t0x3fc00\n#define bCounterReset\t\t\t\t0x10000\n#define bNumOfOFDMTx\t\t\t\t0xffff\n#define bNumOfCCKTx\t\t\t\t\t0xffff0000\n#define bTxIdleInterval\t\t\t\t0xffff\n#define bOFDMService\t\t\t\t0xffff0000\n#define bTxMACHeader\t\t\t\t0xffffffff\n#define bTxDataInit\t\t\t\t\t0xff\n#define bTxHTMode\t\t\t\t\t0x100\n#define bTxDataType\t\t\t\t\t0x30000\n#define bTxRandomSeed\t\t\t\t0xffffffff\n#define bCCKTxPreamble\t\t\t\t0x1\n#define bCCKTxSFD\t\t\t\t\t0xffff0000\n#define bCCKTxSIG\t\t\t\t\t0xff\n#define bCCKTxService\t\t\t\t0xff00\n#define bCCKLengthExt\t\t\t\t0x8000\n#define bCCKTxLength\t\t\t\t0xffff0000\n#define bCCKTxCRC16\t\t\t\t\t0xffff\n#define bCCKTxStatus\t\t\t\t\t0x1\n#define bOFDMTxStatus\t\t\t\t0x2\n\n\n/*\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 1. Page1(0x100)\n *   */\n#define rPMAC_Reset\t\t\t\t\t0x100\n#define rPMAC_TxStart\t\t\t\t0x104\n#define rPMAC_TxLegacySIG\t\t\t0x108\n#define rPMAC_TxHTSIG1\t\t\t\t0x10c\n#define rPMAC_TxHTSIG2\t\t\t\t0x110\n#define rPMAC_PHYDebug\t\t\t\t0x114\n#define rPMAC_TxPacketNum\t\t\t0x118\n#define rPMAC_TxIdle\t\t\t\t\t0x11c\n#define rPMAC_TxMACHeader0\t\t\t0x120\n#define rPMAC_TxMACHeader1\t\t\t0x124\n#define rPMAC_TxMACHeader2\t\t\t0x128\n#define rPMAC_TxMACHeader3\t\t\t0x12c\n#define rPMAC_TxMACHeader4\t\t\t0x130\n#define rPMAC_TxMACHeader5\t\t\t0x134\n#define rPMAC_TxDataType\t\t\t0x138\n#define rPMAC_TxRandomSeed\t\t0x13c\n#define rPMAC_CCKPLCPPreamble\t\t0x140\n#define rPMAC_CCKPLCPHeader\t\t0x144\n#define rPMAC_CCKCRC16\t\t\t\t0x148\n#define rPMAC_OFDMRxCRC32OK\t\t0x170\n#define rPMAC_OFDMRxCRC32Er\t\t0x174\n#define rPMAC_OFDMRxParityEr\t\t0x178\n#define rPMAC_OFDMRxCRC8Er\t\t\t0x17c\n#define rPMAC_CCKCRxRC16Er\t\t\t0x180\n#define rPMAC_CCKCRxRC32Er\t\t\t0x184\n#define rPMAC_CCKCRxRC32OK\t\t\t0x188\n#define rPMAC_TxStatus\t\t\t\t0x18c\n\n/*\n * 3. Page8(0x800)\n *   */\n#define rFPGA0_RFMOD\t\t\t\t0x800\t/* RF mode & CCK TxSC */ /* RF BW Setting?? */\n\n#define rFPGA0_TxInfo\t\t\t\t0x804\t/* Status report?? */\n#define rFPGA0_PSDFunction\t\t\t0x808\n#define rFPGA0_TxGainStage\t\t\t0x80c\t/* Set TX PWR init gain? */\n\n#define rFPGA0_XA_HSSIParameter1\t0x820\t/* RF 3 wire register */\n#define rFPGA0_XA_HSSIParameter2\t0x824\n#define rFPGA0_XB_HSSIParameter1\t0x828\n#define rFPGA0_XB_HSSIParameter2\t0x82c\n\n#define rFPGA0_XAB_SwitchControl\t0x858\t/* RF Channel switch */\n#define rFPGA0_XCD_SwitchControl\t0x85c\n\n#define rFPGA0_XAB_RFParameter\t\t0x878\t/* RF Parameter */\n#define rFPGA0_XCD_RFParameter\t\t0x87c\n\n#define rFPGA0_AnalogParameter1\t0x880\t/* Crystal cap setting RF-R/W protection for parameter4?? */\n#define rFPGA0_AnalogParameter2\t0x884\n#define rFPGA0_AnalogParameter3\t0x888\n#define rFPGA0_AdDaClockEn\t\t\t0x888\t/* enable ad/da clock1 for dual-phy */\n#define rFPGA0_AnalogParameter4\t0x88c\n#define rFPGA0_XB_LSSIReadBack\t\t0x8a4\n#define rFPGA0_XCD_RFPara\t0x8b4\n\n/*\n * 4. Page9(0x900)\n *   */\n#define rFPGA1_RFMOD\t\t\t\t0x900\t/* RF mode & OFDM TxSC */ /* RF BW Setting?? */\n\n#define rFPGA1_TxBlock\t\t\t\t0x904\t/* Useless now */\n#define rFPGA1_DebugSelect\t\t\t0x908\t/* Useless now */\n#define rFPGA1_TxInfo\t\t\t\t0x90c\t/* Useless now */ /* Status report?? */\n\n/*\n * PageA(0xA00)\n *   */\n#define rCCK0_System\t\t\t\t0xa00\n#define rCCK0_AFESetting\t\t\t\t0xa04\t/* Disable init gain now */ /* Select RX path by RSSI */\n#define\trCCK0_DSPParameter2\t\t\t0xa1c\t/* SQ threshold */\n#define rCCK0_TxFilter1\t\t\t\t0xa20\n#define rCCK0_TxFilter2\t\t\t\t0xa24\n#define rCCK0_DebugPort\t\t\t\t0xa28\t/* debug port and Tx filter3 */\n#define\trCCK0_FalseAlarmReport\t\t\t0xa2c\t/* 0xa2d\tuseless now 0xa30-a4f channel report */\n\n/*\n * PageB(0xB00)\n *   */\n#define rPdp_AntA\t\t\t\t0xb00\n#define rPdp_AntA_4\t\t\t\t0xb04\n#define rConfig_Pmpd_AntA\t\t\t0xb28\n#define rConfig_AntA\t\t\t\t\t0xb68\n#define rConfig_AntB\t\t\t\t\t0xb6c\n#define rPdp_AntB\t\t\t\t\t0xb70\n#define rPdp_AntB_4\t\t\t\t\t0xb74\n#define rConfig_Pmpd_AntB\t\t\t0xb98\n#define rAPK\t\t\t\t\t\t\t0xbd8\n\n/*\n * 6. PageC(0xC00)\n *   */\n#define rOFDM0_LSTF\t\t\t\t\t0xc00\n\n#define rOFDM0_TRxPathEnable\t\t0xc04\n#define rOFDM0_TRMuxPar\t\t\t0xc08\n#define rOFDM0_TRSWIsolation\t\t0xc0c\n\n#define rOFDM0_XARxAFE\t\t\t\t0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */\n#define rOFDM0_XARxIQImbalance    \t0xc14  /* RxIQ imblance matrix */\n#define rOFDM0_XBRxAFE\t\t0xc18\n#define rOFDM0_XBRxIQImbalance\t0xc1c\n#define rOFDM0_XCRxAFE\t\t0xc20\n#define rOFDM0_XCRxIQImbalance\t0xc24\n#define rOFDM0_XDRxAFE\t\t0xc28\n#define rOFDM0_XDRxIQImbalance\t0xc2c\n\n#define rOFDM0_RxDetector1\t\t\t0xc30  /* PD, BW & SBD\t */ /* DM tune init gain */\n#define rOFDM0_RxDetector2\t\t\t0xc34  /* SBD & Fame Sync. */\n#define rOFDM0_RxDetector3\t\t\t0xc38  /* Frame Sync. */\n#define rOFDM0_RxDetector4\t\t\t0xc3c  /* PD, SBD, Frame Sync & Short-GI */\n\n#define rOFDM0_RxDSP\t\t\t\t0xc40  /* Rx Sync Path */\n#define rOFDM0_CFOandDAGC\t\t\t0xc44  /* CFO & DAGC */\n#define rOFDM0_CCADropThreshold\t0xc48 /* CCA Drop threshold */\n#define rOFDM0_ECCAThreshold\t\t0xc4c /* energy CCA */\n\n#define rOFDM0_XAAGCCore1\t\t\t0xc50\t/* DIG */\n#define rOFDM0_XAAGCCore2\t\t\t0xc54\n#define rOFDM0_XBAGCCore1\t\t\t0xc58\n#define rOFDM0_XBAGCCore2\t\t\t0xc5c\n#define rOFDM0_XCAGCCore1\t\t\t0xc60\n#define rOFDM0_XCAGCCore2\t\t\t0xc64\n#define rOFDM0_XDAGCCore1\t\t\t0xc68\n#define rOFDM0_XDAGCCore2\t\t\t0xc6c\n\n#define rOFDM0_AGCParameter1\t\t0xc70\n#define rOFDM0_AGCParameter2\t\t0xc74\n#define rOFDM0_AGCRSSITable\t\t0xc78\n#define rOFDM0_HTSTFAGC\t\t\t0xc7c\n\n#define rOFDM0_XATxIQImbalance\t\t0xc80\t/* TX PWR TRACK and DIG */\n#define rOFDM0_XATxAFE\t\t\t\t0xc84\n#define rOFDM0_XBTxIQImbalance\t\t0xc88\n#define rOFDM0_XBTxAFE\t\t\t\t0xc8c\n#define rOFDM0_XCTxIQImbalance\t\t0xc90\n#define rOFDM0_XCTxAFE\t\t0xc94\n#define rOFDM0_XDTxIQImbalance\t\t0xc98\n#define rOFDM0_XDTxAFE\t\t\t\t0xc9c\n\n#define rOFDM0_RxIQExtAnta\t\t\t0xca0\n#define rOFDM0_TxCoeff1\t\t\t\t0xca4\n#define rOFDM0_TxCoeff2\t\t\t\t0xca8\n#define rOFDM0_TxCoeff3\t\t\t\t0xcac\n#define rOFDM0_TxCoeff4\t\t\t\t0xcb0\n#define rOFDM0_TxCoeff5\t\t\t\t0xcb4\n#define rOFDM0_TxCoeff6\t\t\t\t0xcb8\n#define rOFDM0_RxHPParameter\t\t0xce0\n#define rOFDM0_TxPseudoNoiseWgt\t0xce4\n#define rOFDM0_FrameSync\t\t\t0xcf0\n#define rOFDM0_DFSReport\t\t\t0xcf4\n\n/*\n * 7. PageD(0xD00)\n *   */\n#define rOFDM1_LSTF\t\t\t\t\t0xd00\n#define rOFDM1_TRxPathEnable\t\t0xd04\n\n/*\n * 8. PageE(0xE00)\n *   */\n#define rTxAGC_A_Rate18_06\t\t\t0xe00\n#define rTxAGC_A_Rate54_24\t\t\t0xe04\n#define rTxAGC_A_CCK1_Mcs32\t\t0xe08\n#define rTxAGC_A_Mcs03_Mcs00\t\t0xe10\n#define rTxAGC_A_Mcs07_Mcs04\t\t0xe14\n#define rTxAGC_A_Mcs11_Mcs08\t\t0xe18\n#define rTxAGC_A_Mcs15_Mcs12\t\t0xe1c\n\n#define rTxAGC_B_Rate18_06\t\t\t0x830\n#define rTxAGC_B_Rate54_24\t\t\t0x834\n#define rTxAGC_B_CCK1_55_Mcs32\t0x838\n#define rTxAGC_B_Mcs03_Mcs00\t\t0x83c\n#define rTxAGC_B_Mcs07_Mcs04\t\t0x848\n#define rTxAGC_B_Mcs11_Mcs08\t\t0x84c\n#define rTxAGC_B_Mcs15_Mcs12\t\t0x868\n#define rTxAGC_B_CCK11_A_CCK2_11\t0x86c\n\n#define rFPGA0_IQK\t\t\t\t\t0xe28\n#define rTx_IQK_Tone_A\t\t\t\t0xe30\n#define rRx_IQK_Tone_A\t\t\t\t0xe34\n#define rTx_IQK_PI_A\t\t\t\t0xe38\n#define rRx_IQK_PI_A\t\t\t\t0xe3c\n\n#define rTx_IQK\t\t\t\t\t\t0xe40\n#define rRx_IQK\t\t\t\t\t\t0xe44\n#define rIQK_AGC_Pts\t\t\t\t\t0xe48\n#define rIQK_AGC_Rsp\t\t\t\t0xe4c\n#define rTx_IQK_Tone_B\t\t\t\t0xe50\n#define rRx_IQK_Tone_B\t\t\t\t0xe54\n#define rTx_IQK_PI_B\t\t\t\t\t0xe58\n#define rRx_IQK_PI_B\t\t\t\t\t0xe5c\n#define rIQK_AGC_Cont\t\t\t\t0xe60\n\n#define rBlue_Tooth\t\t\t\t\t0xe6c\n#define rRx_Wait_CCA\t\t\t\t0xe70\n#define rTx_CCK_RFON\t\t\t\t0xe74\n#define rTx_CCK_BBON\t\t\t\t0xe78\n#define rTx_OFDM_RFON\t\t\t\t0xe7c\n#define rTx_OFDM_BBON\t\t\t\t0xe80\n#define rTx_To_Rx\t\t\t\t\t0xe84\n#define rTx_To_Tx\t\t\t\t\t0xe88\n#define rRx_CCK\t\t\t\t\t\t0xe8c\n\n#define rTx_Power_Before_IQK_A\t\t0xe94\n#define rTx_Power_After_IQK_A\t\t0xe9c\n\n#define rRx_Power_Before_IQK_A\t\t0xea0\n#define rRx_Power_Before_IQK_A_2\t0xea4\n#define rRx_Power_After_IQK_A\t\t0xea8\n#define rRx_Power_After_IQK_A_2\t\t0xeac\n\n#define rTx_Power_Before_IQK_B\t\t0xeb4\n#define rTx_Power_After_IQK_B\t\t0xebc\n\n#define rRx_Power_Before_IQK_B\t\t0xec0\n#define rRx_Power_Before_IQK_B_2\t0xec4\n#define rRx_Power_After_IQK_B\t\t0xec8\n#define rRx_Power_After_IQK_B_2\t\t0xecc\n\n#define rRx_OFDM\t\t\t\t\t0xed0\n#define rRx_Wait_RIFS\t\t\t\t0xed4\n#define rRx_TO_Rx\t\t\t\t\t0xed8\n#define rStandby\t\t\t\t\t\t0xedc\n#define rSleep\t\t\t\t\t\t0xee0\n#define rPMPD_ANAEN\t\t\t\t0xeec\n\n\n/* 2. Page8(0x800) */\n#define bRFMOD\t\t\t\t\t\t0x1\t/* Reg 0x800 rFPGA0_RFMOD */\n#define bJapanMode\t\t\t\t\t0x2\n#define bCCKTxSC\t\t\t\t\t0x30\n#define bCCKEn\t\t\t\t\t\t0x1000000\n#define bOFDMEn\t\t\t\t\t\t0x2000000\n#define bXBTxAGC                  \t\t\t0xf00\t/* Reg 80c rFPGA0_TxGainStage */\n#define bXCTxAGC\t\t\t0xf000\n#define bXDTxAGC\t\t\t0xf0000\n\n/* 4. PageA(0xA00) */\n#define bCCKBBMode                \t\t\t0x3\t/* Useless */\n#define bCCKTxPowerSaving\t\t0x80\n#define bCCKRxPowerSaving\t\t0x40\n\n#define bCCKSideBand              \t\t0x10\t/* Reg 0xa00 rCCK0_System 20/40 switch */\n\n#define bCCKScramble              \t\t0x8\t/* Useless */\n#define bCCKAntDiversity\t\t\t0x8000\n#define bCCKCarrierRecovery\t\t0x4000\n#define bCCKTxRate\t\t\t0x3000\n#define bCCKDCCancel\t\t\t0x0800\n#define bCCKISICancel\t\t\t0x0400\n#define bCCKMatchFilter\t\t0x0200\n#define bCCKEqualizer\t\t\t0x0100\n#define bCCKPreambleDetect\t\t0x800000\n#define bCCKFastFalseCCA\t\t0x400000\n#define bCCKChEstStart\t\t0x300000\n#define bCCKCCACount\t\t0x080000\n#define bCCKcs_lim\t\t\t0x070000\n#define bCCKBistMode\t\t\t0x80000000\n#define bCCKCCAMask\t\t\t0x40000000\n#define bCCKTxDACPhase\t\t0x4\n#define bCCKRxADCPhase         \t   \t0x20000000   /* r_rx_clk */\n#define bCCKr_cp_mode0\t\t0x0100\n#define bCCKTxDCOffset\t\t0xf0\n#define bCCKRxDCOffset\t\t0xf\n#define bCCKCCAMode\t\t\t0xc000\n#define bCCKFalseCS_lim\t\t0x3f00\n#define bCCKCS_ratio\t\t\t0xc00000\n#define bCCKCorgBit_sel\t\t0x300000\n#define bCCKPD_lim\t\t\t0x0f0000\n#define bCCKNewCCA\t\t0x80000000\n#define bCCKRxHPofIG\t\t0x8000\n#define bCCKRxIG\t\t\t0x7f00\n#define bCCKLNAPolarity\t\t0x800000\n#define bCCKRx1stGain\t\t0x7f0000\n#define bCCKRFExtend              \t\t0x20000000 /* CCK Rx Iinital gain polarity */\n#define bCCKRxAGCSatLevel\t\t0x1f000000\n#define bCCKRxAGCSatCount\t\t0xe0\n#define bCCKRxRFSettle            \t\t0x1f       /* AGCsamp_dly */\n#define bCCKFixedRxAGC\t\t0x8000\n/* #define bCCKRxAGCFormat\t\t0x4000 */   /* remove to HSSI register 0x824 */\n#define bCCKAntennaPolarity\t\t0x2000\n#define bCCKTxFilterType\t\t0x0c00\n#define bCCKRxAGCReportType\t\t0x0300\n#define bCCKRxDAGCEn\t\t0x80000000\n#define bCCKRxDAGCPeriod\t\t0x20000000\n#define bCCKRxDAGCSatLevel\t\t0x1f000000\n#define bCCKTimingRecovery\t\t0x800000\n#define bCCKTxC0\t\t\t0x3f0000\n#define bCCKTxC1\t\t\t0x3f000000\n#define bCCKTxC2\t\t\t0x3f\n#define bCCKTxC3\t\t\t0x3f00\n#define bCCKTxC4\t\t\t0x3f0000\n#define bCCKTxC5\t\t\t0x3f000000\n#define bCCKTxC6\t\t\t0x3f\n#define bCCKTxC7\t\t\t0x3f00\n#define bCCKDebugPort\t\t0xff0000\n#define bCCKDACDebug\t\t0x0f000000\n#define bCCKFalseAlarmEnable\t\t0x8000\n#define bCCKFalseAlarmRead\t\t0x4000\n#define bCCKTRSSI\t\t\t0x7f\n#define bCCKRxAGCReport\t\t0xfe\n#define bCCKRxReport_AntSel\t\t0x80000000\n#define bCCKRxReport_MFOff\t\t0x40000000\n#define bCCKRxRxReport_SQLoss\t0x20000000\n#define bCCKRxReport_Pktloss\t\t0x10000000\n#define bCCKRxReport_Lockedbit\t0x08000000\n#define bCCKRxReport_RateError\t0x04000000\n#define bCCKRxReport_RxRate\t\t0x03000000\n#define bCCKRxFACounterLower\t0xff\n#define bCCKRxFACounterUpper\t0xff000000\n#define bCCKRxHPAGCStart\t\t0xe000\n#define bCCKRxHPAGCFinal\t\t0x1c00\n#define bCCKRxFalseAlarmEnable\t0x8000\n#define bCCKFACounterFreeze\t\t0x4000\n#define bCCKTxPathSel\t\t0x10000000\n#define bCCKDefaultRxPath\t\t0xc000000\n#define bCCKOptionRxPath\t\t0x3000000\n\n/* 6. PageE(0xE00) */\n#define bSTBCEn                  \t\t\t0x4\t/* Useless */\n#define bAntennaMapping\t\t0x10\n#define bNss\t\t\t\t0x20\n#define bCFOAntSumD\t\t0x200\n#define bPHYCounterReset\t\t0x8000000\n#define bCFOReportGet\t\t\t0x4000000\n#define bOFDMContinueTx\t\t0x10000000\n#define bOFDMSingleCarrier\t\t0x20000000\n#define bOFDMSingleTone\t\t0x40000000\n\n\n/*\n * Other Definition\n *   */\n\n#define bEnable                   0x1\t/* Useless */\n#define bDisable                  0x0\n\n/* byte endable for srwrite */\n#define bByte0                    \t\t0x1\t/* Useless */\n#define bByte1\t\t0x2\n#define bByte2\t\t0x4\n#define bByte3\t\t0x8\n#define bWord0\t\t0x3\n#define bWord1\t\t0xc\n#define bDWord\t\t0xf\n\n/* for PutRegsetting & GetRegSetting BitMask */\n#define bMaskByte0                \t\t0xff\t/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */\n#define bMaskByte1\t\t0xff00\n#define bMaskByte2\t\t0xff0000\n#define bMaskByte3\t\t0xff000000\n#define bMaskHWord\t0xffff0000\n#define bMaskLWord\t\t0x0000ffff\n#define bMaskDWord\t0xffffffff\n#define bMaskH3Bytes\t\t\t\t0xffffff00\n#define bMask12Bits\t\t\t\t0xfff\n#define bMaskH4Bits\t\t\t\t0xf0000000\n#define bMaskOFDM_D\t\t\t0xffc00000\n#define bMaskCCK\t\t\t\t0x3f3f3f3f\n\n\n/*--------------------------Define Parameters-------------------------------*/\n\n\n#endif\n"
  },
  {
    "path": "include/Hal8812PwrSeq.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n\n#ifndef __HAL8812PWRSEQ_H__\n#define __HAL8812PWRSEQ_H__\n\n#include \"HalPwrSeqCmd.h\"\n\n/*\n\tCheck document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf\n\tThere are 6 HW Power States:\n\t0: POFF--Power Off\n\t1: PDN--Power Down\n\t2: CARDEMU--Card Emulation\n\t3: ACT--Active Mode\n\t4: LPS--Low Power State\n\t5: SUS--Suspend\n\n\tThe transision from different states are defined below\n\tTRANS_CARDEMU_TO_ACT\n\tTRANS_ACT_TO_CARDEMU\n\tTRANS_CARDEMU_TO_SUS\n\tTRANS_SUS_TO_CARDEMU\n\tTRANS_CARDEMU_TO_PDN\n\tTRANS_ACT_TO_LPS\n\tTRANS_LPS_TO_ACT\n\n\tTRANS_END\n*/\n#define\tRTL8812_TRANS_CARDEMU_TO_ACT_STEPS\t15\n#define\tRTL8812_TRANS_ACT_TO_CARDEMU_STEPS\t15\n#define\tRTL8812_TRANS_CARDEMU_TO_SUS_STEPS\t15\n#define\tRTL8812_TRANS_SUS_TO_CARDEMU_STEPS\t15\n#define\tRTL8812_TRANS_CARDEMU_TO_PDN_STEPS\t15\n#define\tRTL8812_TRANS_PDN_TO_CARDEMU_STEPS\t15\n#define\tRTL8812_TRANS_ACT_TO_LPS_STEPS\t15\n#define\tRTL8812_TRANS_LPS_TO_ACT_STEPS\t15\n#define\tRTL8812_TRANS_END_STEPS\t1\n\n\n#define RTL8812_TRANS_CARDEMU_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/\t\\\n\t/*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, disable HWPDN 0x04[15]=0*/ \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/   \\\n\t{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x24[1] Choose the type of buffer after xosc: nand*/   \\\n\t{0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /* 0x28[33] Choose the type of buffer after xosc: nand*/\n\n#define RTL8812_TRANS_ACT_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4\tturn off 3-wire */\t\\\n\t{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4\tturn off 3-wire */\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0\t RESET BB, CLOSE RF */\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/\t\t\t\\\n\t/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},//0x1F[7:0] = 0 turn off RF*/\t\\\n\t/*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},//0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x2A}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/\t\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */\t\\\n\t/*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0}, //  0x02[1:0] = 0\treset BB */\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/\n\n#define RTL8812_TRANS_CARDEMU_TO_SUS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\\\n\t{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\\\n\t{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */\t\\\n\t{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */\t\\\n\t{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */\t\\\n\t{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */\t\\\n\t{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */\t\\\n\t{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */\t\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'11 enable WL suspend for PCIe*/\n\n#define RTL8812_TRANS_SUS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/   \\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */\t\\\n\t{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */\t\\\n\t{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */\t\\\n\t{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */\t\\\n\t{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */\n\n#define RTL8812_TRANS_CARDEMU_TO_CARDDIS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t/**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/\t\\\n\t/**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/\t\\\n\t{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 8051*/\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x05}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/\t\\\n\t{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\\\n\t{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\\\n\t{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */\t\\\n\t{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */\t\\\n\t{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */\t\\\n\t{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */\t\\\n\t{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */\t\\\n\t{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */\t\\\n\t{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/*0x12[0] = 0 force PFM mode */\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */\t\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/\t\\\n\t{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x01f[1]=0 , disable RFC_0  control  REG_RF_CTRL_8812 */\t\\\n\t{0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x076[1]=0 , disable RFC_1  control REG_OPT_CTRL_8812 +2 */\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'01 enable WL suspend*/\n\n#define RTL8812_TRANS_CARDDIS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/                       \\\n\t{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x12[0] = 1 force PWM mode */\t\\\n\t{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */\t\\\n\t{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */\t\\\n\t{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */\t\\\n\t{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/\t\\\n\t{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x03[2] = 1, enable 8051*/\t\\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/  \\\n\t{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /* 0x24[1] Choose the type of buffer after xosc: schmitt trigger*/ \\\n\t{0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /* 0x28[33] Choose the type of buffer after xosc: schmitt trigger*/\n\n\n#define RTL8812_TRANS_CARDEMU_TO_PDN\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/\n\n#define RTL8812_TRANS_PDN_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/\n\n#define RTL8812_TRANS_ACT_TO_LPS\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/\t\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/\t\t\\\n\t{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4\tturn off 3-wire */\t\\\n\t{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4\tturn off 3-wire */\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/\t\t\t\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/\t\t\t\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\t\t\\\n\t{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/\n\n\n#define RTL8812_TRANS_LPS_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\t\\\n\t{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\t\\\n\t{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\t\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.\t0x08[4] = 0\t\t switch TSF to 40M*/\t\\\n\t{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\t\t\t\\\n\t{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.\t0x29[7:6] = 2b'00\t enable BB clock*/\t\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.\t0x101[1] = 1*/\t\t\t\t\t\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.\t0x100[7:0] = 0xFF\t enable WMAC TRX*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.\t0x02[1:0] = 2b'11\t enable BB macro*/\t\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.\t0x522 = 0*/\n\n#define RTL8812_TRANS_END\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\\\n\t{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},\n\n\nextern WLAN_PWR_CFG rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS + RTL8812_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS];\n\n#endif /* __HAL8812PWRSEQ_H__ */\n"
  },
  {
    "path": "include/Hal8814PhyCfg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8814PHYCFG_H__\n#define __INC_HAL8814PHYCFG_H__\n\n\n/*--------------------------Define Parameters-------------------------------*/\n#define LOOP_LIMIT\t\t\t\t5\n#define MAX_STALL_TIME\t\t\t50\t\t/* us */\n#define AntennaDiversityValue\t0x80\t/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */\n#define MAX_TXPWR_IDX_NMODE_92S\t63\n#define Reset_Cnt_Limit\t\t\t3\n\n\n#ifdef CONFIG_PCI_HCI\n\t#define MAX_AGGR_NUM\t0x0B\n#else\n\t#define MAX_AGGR_NUM\t0x07\n#endif /* CONFIG_PCI_HCI */\n\n\n/*--------------------------Define Parameters-------------------------------*/\n\n/*------------------------------Define structure----------------------------*/\n\n\n/* BB/RF related */\n\n#define\tSIC_ENABLE\t\t\t\t0\n\n/*------------------------------Define structure----------------------------*/\n\n\n/*------------------------Export global variable----------------------------*/\n/*------------------------Export global variable----------------------------*/\n\n\n/*------------------------Export Marco Definition---------------------------*/\n/*------------------------Export Marco Definition---------------------------*/\n\n\n/*--------------------------Exported Function prototype---------------------*/\n/* 1. BB register R/W API */\n\nextern\tu32\nPHY_QueryBBReg8814A(PADAPTER\tAdapter,\n\t\t\tu32\t\tRegAddr,\n\t\t\tu32\t\tBitMask);\n\n\nvoid\nPHY_SetBBReg8814A(PADAPTER\tAdapter,\n\t\t\tu32\t\tRegAddr,\n\t\t\tu32\t\tBitMask,\n\t\t\tu32\t\tData);\n\n\nextern\tu32\nPHY_QueryRFReg8814A(PADAPTER\t\t\tAdapter,\n\t\t\tenum rf_path\teRFPath,\n\t\t\tu32\t\t\tRegAddr,\n\t\t\tu32\t\t\tBitMask);\n\n\nvoid\nPHY_SetRFReg8814A(PADAPTER\t\t\tAdapter,\n\t\t\tenum rf_path\t\teRFPath,\n\t\t\tu32\t\t\t\tRegAddr,\n\t\t\tu32\t\t\t\tBitMask,\n\t\t\tu32\t\t\t\tData);\n\n/* 1 3. Initial BB/RF config by reading MAC/BB/RF txt. */\ns32\nphy_BB8814A_Config_ParaFile(\n\t\tPADAPTER\tAdapter\n);\n\nvoid\nPHY_ConfigBB_8814A(\n\t\tPADAPTER\tAdapter\n);\n\n\nvoid\nphy_ADC_CLK_8814A(\n\t\tPADAPTER\tAdapter\n);\n\ns32\nPHY_RFConfig8814A(\n\t\tPADAPTER\tAdapter\n);\n\n/*\n * RF Power setting\n *\n * BOOLEAN\tPHY_SetRFPowerState8814A(PADAPTER Adapter, rt_rf_power_state\teRFPowerState); */\n\n/* 1 5. Tx  Power setting API */\n\nvoid\nPHY_SetTxPowerLevel8814(\n\t\tPADAPTER\t\tAdapter,\n\t\tu8\t\t\tChannel\n);\n\nu8\nphy_get_tx_power_index_8814a(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\tRFPath,\n\t\tu8\t\t\t\tRate,\n\t\tenum channel_width BandWidth,\n\t\tu8\t\t\t\tChannel\n);\n\nu8\nPHY_GetTxPowerIndex8814A(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\tRFPath,\n\t\tu8\t\t\t\tRate,\n\t\tu8\t\t\t\tBandWidth,\n\t\tu8\t\t\t\tChannel,\n\tstruct txpwr_idx_comp *tic\n);\n\nvoid\nPHY_SetTxPowerIndex_8814A(\n\t\tPADAPTER\t\tAdapter,\n\t\tu32\t\t\t\tPowerIndex,\n\t\tenum rf_path\t\tRFPath,\n\t\tu8\t\t\t\tRate\n);\n\nu32\nPHY_GetTxBBSwing_8814A(\n\t\tPADAPTER\tAdapter,\n\t\tBAND_TYPE\tBand,\n\t\tenum rf_path\tRFPath\n);\n\n\n\n/* 1 6. Channel setting API */\n#if 0\nvoid\nPHY_SwChnlTimerCallback8814A(\n\t\tstruct timer_list\t\t*p_timer\n);\n#endif\nvoid\nPHY_SwChnlWorkItemCallback8814A(\n\t\tvoid *pContext\n);\n\n\nvoid\nHAL_HandleSwChnl8814A(\n\t\tPADAPTER\tpAdapter,\n\t\tu8\t\tchannel\n);\n\nvoid\nPHY_SwChnlSynchronously8814A(PADAPTER\t\tpAdapter,\n\t\t\t\tu8\t\t\tchannel);\n\nvoid\nPHY_SwChnlAndSetBWModeCallback8814A(void *pContext);\n\n\nvoid\nPHY_HandleSwChnlAndSetBW8814A(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tBOOLEAN\t\t\t\tbSwitchChannel,\n\t\tBOOLEAN\t\t\t\tbSetBandWidth,\n\t\tu8\t\t\t\t\tChannelNum,\n\t\tenum channel_width\tChnlWidth,\n\t\tu8\t\t\t\t\tChnlOffsetOf40MHz,\n\t\tu8\t\t\t\t\tChnlOffsetOf80MHz,\n\t\tu8\t\t\t\t\tCenterFrequencyIndex1\n);\n\n\nBOOLEAN\nPHY_QueryRFPathSwitch_8814A(PADAPTER\tpAdapter);\n\n\n\n#if (USE_WORKITEM)\nvoid\nRtCheckForHangWorkItemCallback8814A(\n\t\tvoid *pContext\n);\n#endif\n\nBOOLEAN\nSetAntennaConfig8814A(\n\t\tPADAPTER\tAdapter,\n\t\tu8\t\tDefaultAnt\n);\n\nvoid\nPHY_SetRFEReg8814A(\n\t\tPADAPTER\t\tAdapter,\n\t\tBOOLEAN\t\tbInit,\n\t\tu8\t\tBand\n);\n\n\ns32\nPHY_SwitchWirelessBand8814A(\n\t\tPADAPTER\t\t Adapter,\n\t\tu8\t\tBand\n);\n\nvoid\nPHY_SetIO_8814A(\n\tPADAPTER\t\tpAdapter\n);\n\nvoid\nPHY_SetSwChnlBWMode8814(\n\t\tPADAPTER\t\t\tAdapter,\n\t\tu8\t\t\t\t\tchannel,\n\t\tenum channel_width\tBandwidth,\n\t\tu8\t\t\t\t\tOffset40,\n\t\tu8\t\t\t\t\tOffset80\n);\n\ns32 PHY_MACConfig8814(PADAPTER Adapter);\nint PHY_BBConfig8814(PADAPTER\tAdapter);\nvoid PHY_Set_SecCCATH_by_RXANT_8814A(PADAPTER\tpAdapter, u32 ulAntennaRx);\n\n\n\n/*--------------------------Exported Function prototype---------------------*/\n\n/*--------------------------Exported Function prototype---------------------*/\n#endif /* __INC_HAL8192CPHYCFG_H */\n"
  },
  {
    "path": "include/Hal8814PhyReg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_HAL8814PHYREG_H__\n#define __INC_HAL8814PHYREG_H__\n/*--------------------------Define Parameters-------------------------------*/\n/*\n * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00\n * 3. RF register 0x00-2E\n * 4. Bit Mask for BB/RF register\n * 5. Other defintion for BB/RF R/W\n *   */\n\n\n/* BB Register Definition */\n\n#define rCCAonSec_Jaguar\t\t0x838\n#define rPwed_TH_Jaguar\t\t\t0x830\n#define rL1_Weight_Jaguar\t\t0x840\n#define\tr_L1_SBD_start_time\t\t0x844\n\n/* BW and sideband setting */\n#define rBWIndication_Jaguar\t\t0x834\n#define rL1PeakTH_Jaguar\t\t0x848\n#define rRFMOD_Jaguar\t\t\t0x8ac\t/* RF mode */\n#define rADC_Buf_Clk_Jaguar\t\t0x8c4\n#define\trADC_Buf_40_Clk_Jaguar2\t\t0x8c8\n#define rRFECTRL_Jaguar\t\t\t0x900\n#define bRFMOD_Jaguar\t\t\t0xc3\n#define rCCK_System_Jaguar\t\t0xa00   /* for cck sideband */\n#define bCCK_System_Jaguar\t\t0x10\n\n/* Block & Path enable */\n#define rOFDMCCKEN_Jaguar \t\t0x808 /* OFDM/CCK block enable */\n#define bOFDMEN_Jaguar\t\t\t0x20000000\n#define bCCKEN_Jaguar\t\t\t0x10000000\n#define rRxPath_Jaguar\t\t\t0x808\t/* Rx antenna */\n#define bRxPath_Jaguar\t\t\t0xff\n#define rTxPath_Jaguar\t\t\t0x80c\t/* Tx antenna */\n#define bTxPath_Jaguar\t\t\t0x0fffffff\n#define rCCK_RX_Jaguar\t\t\t0xa04\t/* for cck rx path selection */\n#define bCCK_RX_Jaguar\t\t\t0x0c000000\n#define rVhtlen_Use_Lsig_Jaguar\t0x8c3\t/* Use LSIG for VHT length */\n\n#define\trRxPath_Jaguar2\t\t\t\t0xa04\t/* Rx antenna */\n#define\trTxAnt_1Nsts_Jaguar2\t\t0x93c\t/* Tx antenna for 1Nsts */\n#define\trTxAnt_23Nsts_Jaguar2\t\t0x940\t/* Tx antenna for 2Nsts and 3Nsts */\n\n\n/* RF read/write-related */\n#define rHSSIRead_Jaguar\t\t\t0x8b0  /* RF read addr */\n#define bHSSIRead_addr_Jaguar\t\t0xff\n#define bHSSIRead_trigger_Jaguar\t0x100\n#define rA_PIRead_Jaguar\t\t\t0xd04 /* RF readback with PI */\n#define rB_PIRead_Jaguar\t\t\t0xd44 /* RF readback with PI */\n#define rA_SIRead_Jaguar\t\t\t0xd08 /* RF readback with SI */\n#define rB_SIRead_Jaguar\t\t\t0xd48 /* RF readback with SI */\n#define rRead_data_Jaguar\t\t\t0xfffff\n#define rA_LSSIWrite_Jaguar\t\t\t0xc90 /* RF write addr */\n#define rB_LSSIWrite_Jaguar\t\t\t0xe90 /* RF write addr */\n#define bLSSIWrite_data_Jaguar\t\t0x000fffff\n#define bLSSIWrite_addr_Jaguar\t\t0x0ff00000\n\n#define\trC_PIRead_Jaguar2\t\t\t0xd84 /* RF readback with PI */\n#define\trD_PIRead_Jaguar2\t\t\t0xdC4 /* RF readback with PI */\n#define\trC_SIRead_Jaguar2\t\t\t0xd88 /* RF readback with SI */\n#define\trD_SIRead_Jaguar2\t\t\t0xdC8 /* RF readback with SI */\n#define\trC_LSSIWrite_Jaguar2\t\t0x1890 /* RF write addr */\n#define\trD_LSSIWrite_Jaguar2\t\t0x1A90 /* RF write addr */\n\n\n/* YN: mask the following register definition temporarily */\n#define rFPGA0_XA_RFInterfaceOE\t\t\t0x860\t/* RF Channel switch */\n#define rFPGA0_XB_RFInterfaceOE\t\t\t0x864\n\n#define rFPGA0_XAB_RFInterfaceSW\t\t0x870\t/* RF Interface Software Control */\n#define rFPGA0_XCD_RFInterfaceSW\t\t0x874\n\n/* #define rFPGA0_XAB_RFParameter\t\t0x878 */\t/* RF Parameter\n * #define rFPGA0_XCD_RFParameter\t\t0x87c */\n\n/* #define rFPGA0_AnalogParameter1\t\t0x880 */\t/* Crystal cap setting RF-R/W protection for parameter4??\n * #define rFPGA0_AnalogParameter2\t\t0x884\n * #define rFPGA0_AnalogParameter3\t\t0x888\n * #define rFPGA0_AdDaClockEn\t\t\t0x888 */\t/* enable ad/da clock1 for dual-phy\n * #define rFPGA0_AnalogParameter4\t\t0x88c */\n\n\n/* CCK TX scaling */\n#define rCCK_TxFilter1_Jaguar\t\t0xa20\n#define bCCK_TxFilter1_C0_Jaguar\t0x00ff0000\n#define bCCK_TxFilter1_C1_Jaguar\t\t0xff000000\n#define rCCK_TxFilter2_Jaguar\t\t0xa24\n#define bCCK_TxFilter2_C2_Jaguar\t\t0x000000ff\n#define bCCK_TxFilter2_C3_Jaguar\t\t0x0000ff00\n#define bCCK_TxFilter2_C4_Jaguar\t\t0x00ff0000\n#define bCCK_TxFilter2_C5_Jaguar\t\t0xff000000\n#define rCCK_TxFilter3_Jaguar\t\t0xa28\n#define bCCK_TxFilter3_C6_Jaguar\t\t0x000000ff\n#define bCCK_TxFilter3_C7_Jaguar\t\t0x0000ff00\n/* NBI & CSI Mask setting */\n#define\trCSI_Mask_Setting1_Jaguar\t0x874\n#define\trCSI_Fix_Mask0_Jaguar\t\t0x880\n#define\trCSI_Fix_Mask1_Jaguar\t\t0x884\n#define\trCSI_Fix_Mask2_Jaguar\t\t0x888\n#define\trCSI_Fix_Mask3_Jaguar\t\t0x88c\n#define\trCSI_Fix_Mask4_Jaguar\t\t0x890\n#define\trCSI_Fix_Mask5_Jaguar\t\t0x894\n#define\trCSI_Fix_Mask6_Jaguar\t\t0x898\n#define\trCSI_Fix_Mask7_Jaguar\t\t0x89c\n#define\trNBI_Setting_Jaguar\t\t\t0x87c\n\n\n/* YN: mask the following register definition temporarily\n * #define rPdp_AntA\t\t\t\t\t0xb00\n * #define rPdp_AntA_4\t\t\t\t0xb04\n * #define rConfig_Pmpd_AntA\t\t\t0xb28\n * #define rConfig_AntA\t\t\t\t\t0xb68\n * #define rConfig_AntB\t\t\t\t\t0xb6c\n * #define rPdp_AntB\t\t\t\t\t0xb70\n * #define rPdp_AntB_4\t\t\t\t\t0xb74\n * #define rConfig_Pmpd_AntB\t\t\t0xb98\n * #define rAPK\t\t\t\t\t\t\t0xbd8 */\n\n/* RXIQC */\n#define rA_RxIQC_AB_Jaguar    \t0xc10  /* RxIQ imblance matrix coeff. A & B */\n#define rA_RxIQC_CD_Jaguar    \t0xc14  /* RxIQ imblance matrix coeff. C & D */\n#define rA_TxScale_Jaguar \t\t0xc1c  /* Pah_A TX scaling factor */\n#define rB_TxScale_Jaguar \t\t0xe1c  /* Path_B TX scaling factor */\n#define rB_RxIQC_AB_Jaguar    \t0xe10  /* RxIQ imblance matrix coeff. A & B */\n#define rB_RxIQC_CD_Jaguar    \t0xe14  /* RxIQ imblance matrix coeff. C & D */\n#define b_RxIQC_AC_Jaguar\t\t0x02ff  /* bit mask for IQC matrix element A & C */\n#define b_RxIQC_BD_Jaguar\t\t0x02ff0000 /* bit mask for IQC matrix element A & C */\n\n#define\trC_TxScale_Jaguar2 \t\t0x181c  /* Pah_C TX scaling factor */\n#define\trD_TxScale_Jaguar2 \t\t0x1A1c  /* Path_D TX scaling factor */\n#define\trRF_TxGainOffset\t\t0x55\n\n/* DIG-related */\n#define rA_IGI_Jaguar\t\t\t\t0xc50\t/* Initial Gain for path-A */\n#define rB_IGI_Jaguar\t\t\t\t0xe50\t/* Initial Gain for path-B */\n#define\trC_IGI_Jaguar2\t\t\t\t0x1850\t/* Initial Gain for path-C */\n#define\trD_IGI_Jaguar2\t\t\t\t0x1A50\t/* Initial Gain for path-D */\n\n#define rOFDM_FalseAlarm1_Jaguar\t0xf48  /* counter for break */\n#define rOFDM_FalseAlarm2_Jaguar\t0xf4c  /* counter for spoofing */\n#define rCCK_FalseAlarm_Jaguar        \t0xa5c /* counter for cck false alarm */\n#define b_FalseAlarm_Jaguar\t\t\t0xffff\n#define rCCK_CCA_Jaguar\t\t\t\t0xa08\t/* cca threshold */\n#define bCCK_CCA_Jaguar\t\t\t\t0x00ff0000\n\n/* Tx Power Ttraining-related */\n#define rA_TxPwrTraing_Jaguar\t\t0xc54\n#define rB_TxPwrTraing_Jaguar\t\t0xe54\n\n/* Report-related */\n#define rOFDM_ShortCFOAB_Jaguar\t0xf60\n#define rOFDM_LongCFOAB_Jaguar\t\t0xf64\n#define rOFDM_EndCFOAB_Jaguar\t\t0xf70\n#define rOFDM_AGCReport_Jaguar\t\t0xf84\n#define rOFDM_RxSNR_Jaguar\t\t\t0xf88\n#define rOFDM_RxEVMCSI_Jaguar\t\t0xf8c\n#define rOFDM_SIGReport_Jaguar\t\t0xf90\n\n/* Misc functions */\n#define rEDCCA_Jaguar\t\t\t\t0x8a4 /* EDCCA */\n#define bEDCCA_Jaguar\t\t\t\t0xffff\n#define rAGC_table_Jaguar\t\t\t0x82c   /* AGC tabel select */\n#define bAGC_table_Jaguar\t\t\t0x3\n#define b_sel5g_Jaguar    \t\t\t\t0x1000 /* sel5g */\n#define b_LNA_sw_Jaguar\t\t\t\t0x8000 /* HW/WS control for LNA */\n#define rFc_area_Jaguar\t\t\t\t0x860   /* fc_area */\n#define bFc_area_Jaguar\t\t\t\t0x1ffe000\n#define rSingleTone_ContTx_Jaguar\t0x914\n\n#define\trAGC_table_Jaguar2\t\t\t0x958\t/* AGC tabel select */\n#define\trDMA_trigger_Jaguar2\t\t0x95C\t/* ADC sample mode */\n\n\n/* RFE */\n#define rA_RFE_Pinmux_Jaguar\t0xcb0  /* Path_A RFE cotrol pinmux */\n#define rB_RFE_Pinmux_Jaguar\t0xeb0 /* Path_B RFE control pinmux */\n#define rA_RFE_Inv_Jaguar\t\t0xcb4  /* Path_A RFE cotrol   */\n#define rB_RFE_Inv_Jaguar\t\t0xeb4 /* Path_B RFE control */\n#define rA_RFE_Jaguar\t\t\t0xcb8  /* Path_A RFE cotrol   */\n#define rB_RFE_Jaguar\t\t\t0xeb8 /* Path_B RFE control */\n#define\trA_RFE_Inverse_Jaguar\t0xCBC\t/* Path_A RFE control inverse */\n#define\trB_RFE_Inverse_Jaguar\t0xEBC\t/* Path_B RFE control inverse */\n#define r_ANTSEL_SW_Jaguar\t\t0x900 /* ANTSEL SW Control */\n#define bMask_RFEInv_Jaguar\t\t0x3ff00000\n#define bMask_AntselPathFollow_Jaguar 0x00030000\n\n#define\trC_RFE_Pinmux_Jaguar\t0x18B4\t/* Path_C RFE cotrol pinmux */\n#define\trD_RFE_Pinmux_Jaguar\t0x1AB4\t/* Path_D RFE cotrol pinmux */\n#define\trA_RFE_Sel_Jaguar2\t\t0x1990\n\n\n\n/* TX AGC */\n#define rTxAGC_A_CCK11_CCK1_JAguar\t\t\t\t0xc20\n#define rTxAGC_A_Ofdm18_Ofdm6_JAguar\t\t\t\t0xc24\n#define rTxAGC_A_Ofdm54_Ofdm24_JAguar\t\t\t0xc28\n#define rTxAGC_A_MCS3_MCS0_JAguar\t\t\t\t\t0xc2c\n#define rTxAGC_A_MCS7_MCS4_JAguar\t\t\t\t\t0xc30\n#define rTxAGC_A_MCS11_MCS8_JAguar\t\t\t\t0xc34\n#define rTxAGC_A_MCS15_MCS12_JAguar\t\t\t\t0xc38\n#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar\t0xc3c\n#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar\t0xc40\n#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar\t0xc44\n#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar\t0xc48\n#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar\t0xc4c\n#define rTxAGC_B_CCK11_CCK1_JAguar\t\t\t\t0xe20\n#define rTxAGC_B_Ofdm18_Ofdm6_JAguar\t\t\t\t0xe24\n#define rTxAGC_B_Ofdm54_Ofdm24_JAguar\t\t\t0xe28\n#define rTxAGC_B_MCS3_MCS0_JAguar\t\t\t\t\t0xe2c\n#define rTxAGC_B_MCS7_MCS4_JAguar\t\t\t\t\t0xe30\n#define rTxAGC_B_MCS11_MCS8_JAguar\t\t\t\t0xe34\n#define rTxAGC_B_MCS15_MCS12_JAguar\t\t\t\t0xe38\n#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar\t\t0xe3c\n#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar\t\t0xe40\n#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar\t\t0xe44\n#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar\t\t0xe48\n#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar\t\t0xe4c\n#define bTxAGC_byte0_Jaguar\t\t\t\t\t\t\t0xff\n#define bTxAGC_byte1_Jaguar\t\t\t\t\t\t\t0xff00\n#define bTxAGC_byte2_Jaguar\t\t\t\t\t\t\t0xff0000\n#define bTxAGC_byte3_Jaguar\t\t\t\t\t\t\t0xff000000\n\n\n/* TX AGC */\n#define\t\trTxAGC_A_CCK11_CCK1_Jaguar2\t0xc20\n#define\t\trTxAGC_A_Ofdm18_Ofdm6_Jaguar2\t0xc24\n#define\t\trTxAGC_A_Ofdm54_Ofdm24_Jaguar2\t0xc28\n#define\t\trTxAGC_A_MCS3_MCS0_Jaguar2\t0xc2c\n#define\t\trTxAGC_A_MCS7_MCS4_Jaguar2\t0xc30\n#define\t\trTxAGC_A_MCS11_MCS8_Jaguar2\t0xc34\n#define\t\trTxAGC_A_MCS15_MCS12_Jaguar2\t0xc38\n#define\t\trTxAGC_A_MCS19_MCS16_Jaguar2\t0xcd8\n#define\t\trTxAGC_A_MCS23_MCS20_Jaguar2\t0xcdc\n#define\t\trTxAGC_A_Nss1Index3_Nss1Index0_Jaguar2\t0xc3c\n#define\t\trTxAGC_A_Nss1Index7_Nss1Index4_Jaguar2\t0xc40\n#define\t\trTxAGC_A_Nss2Index1_Nss1Index8_Jaguar2\t0xc44\n#define\t\trTxAGC_A_Nss2Index5_Nss2Index2_Jaguar2\t0xc48\n#define\t\trTxAGC_A_Nss2Index9_Nss2Index6_Jaguar2\t0xc4c\n#define\t\trTxAGC_A_Nss3Index3_Nss3Index0_Jaguar2\t0xce0\n#define\t\trTxAGC_A_Nss3Index7_Nss3Index4_Jaguar2\t0xce4\n#define\t\trTxAGC_A_Nss3Index9_Nss3Index8_Jaguar2\t0xce8\n#define\t\trTxAGC_B_CCK11_CCK1_Jaguar2\t0xe20\n#define\t\trTxAGC_B_Ofdm18_Ofdm6_Jaguar2\t0xe24\n#define\t\trTxAGC_B_Ofdm54_Ofdm24_Jaguar2\t0xe28\n#define\t\trTxAGC_B_MCS3_MCS0_Jaguar2\t0xe2c\n#define\t\trTxAGC_B_MCS7_MCS4_Jaguar2\t0xe30\n#define\t\trTxAGC_B_MCS11_MCS8_Jaguar2\t0xe34\n#define\t\trTxAGC_B_MCS15_MCS12_Jaguar2\t0xe38\n#define\t\trTxAGC_B_MCS19_MCS16_Jaguar2\t0xed8\n#define\t\trTxAGC_B_MCS23_MCS20_Jaguar2\t0xedc\n#define\t\trTxAGC_B_Nss1Index3_Nss1Index0_Jaguar2\t0xe3c\n#define\t\trTxAGC_B_Nss1Index7_Nss1Index4_Jaguar2\t0xe40\n#define\t\trTxAGC_B_Nss2Index1_Nss1Index8_Jaguar2\t0xe44\n#define\t\trTxAGC_B_Nss2Index5_Nss2Index2_Jaguar2\t0xe48\n#define\t\trTxAGC_B_Nss2Index9_Nss2Index6_Jaguar2\t0xe4c\n#define\t\trTxAGC_B_Nss3Index3_Nss3Index0_Jaguar2\t0xee0\n#define\t\trTxAGC_B_Nss3Index7_Nss3Index4_Jaguar2\t0xee4\n#define\t\trTxAGC_B_Nss3Index9_Nss3Index8_Jaguar2\t0xee8\n#define\t\trTxAGC_C_CCK11_CCK1_Jaguar2\t0x1820\n#define\t\trTxAGC_C_Ofdm18_Ofdm6_Jaguar2\t0x1824\n#define\t\trTxAGC_C_Ofdm54_Ofdm24_Jaguar2\t0x1828\n#define\t\trTxAGC_C_MCS3_MCS0_Jaguar2\t0x182c\n#define\t\trTxAGC_C_MCS7_MCS4_Jaguar2\t0x1830\n#define\t\trTxAGC_C_MCS11_MCS8_Jaguar2\t0x1834\n#define\t\trTxAGC_C_MCS15_MCS12_Jaguar2\t0x1838\n#define\t\trTxAGC_C_MCS19_MCS16_Jaguar2\t0x18d8\n#define\t\trTxAGC_C_MCS23_MCS20_Jaguar2\t0x18dc\n#define\t\trTxAGC_C_Nss1Index3_Nss1Index0_Jaguar2\t0x183c\n#define\t\trTxAGC_C_Nss1Index7_Nss1Index4_Jaguar2\t0x1840\n#define\t\trTxAGC_C_Nss2Index1_Nss1Index8_Jaguar2\t0x1844\n#define\t\trTxAGC_C_Nss2Index5_Nss2Index2_Jaguar2\t0x1848\n#define\t\trTxAGC_C_Nss2Index9_Nss2Index6_Jaguar2\t0x184c\n#define\t\trTxAGC_C_Nss3Index3_Nss3Index0_Jaguar2\t0x18e0\n#define\t\trTxAGC_C_Nss3Index7_Nss3Index4_Jaguar2\t0x18e4\n#define\t\trTxAGC_C_Nss3Index9_Nss3Index8_Jaguar2\t0x18e8\n#define\t\trTxAGC_D_CCK11_CCK1_Jaguar2\t0x1a20\n#define\t\trTxAGC_D_Ofdm18_Ofdm6_Jaguar2\t0x1a24\n#define\t\trTxAGC_D_Ofdm54_Ofdm24_Jaguar2\t0x1a28\n#define\t\trTxAGC_D_MCS3_MCS0_Jaguar2\t0x1a2c\n#define\t\trTxAGC_D_MCS7_MCS4_Jaguar2\t0x1a30\n#define\t\trTxAGC_D_MCS11_MCS8_Jaguar2\t0x1a34\n#define\t\trTxAGC_D_MCS15_MCS12_Jaguar2\t0x1a38\n#define\t\trTxAGC_D_MCS19_MCS16_Jaguar2\t0x1ad8\n#define\t\trTxAGC_D_MCS23_MCS20_Jaguar2\t0x1adc\n#define\t\trTxAGC_D_Nss1Index3_Nss1Index0_Jaguar2\t0x1a3c\n#define\t\trTxAGC_D_Nss1Index7_Nss1Index4_Jaguar2\t0x1a40\n#define\t\trTxAGC_D_Nss2Index1_Nss1Index8_Jaguar2\t0x1a44\n#define\t\trTxAGC_D_Nss2Index5_Nss2Index2_Jaguar2\t0x1a48\n#define\t\trTxAGC_D_Nss2Index9_Nss2Index6_Jaguar2\t0x1a4c\n#define\t\trTxAGC_D_Nss3Index3_Nss3Index0_Jaguar2\t0x1ae0\n#define\t\trTxAGC_D_Nss3Index7_Nss3Index4_Jaguar2\t0x1ae4\n#define\t\trTxAGC_D_Nss3Index9_Nss3Index8_Jaguar2\t0x1ae8\n/* IQK YN: temporaily mask this part\n * #define rFPGA0_IQK\t\t\t\t\t0xe28\n * #define rTx_IQK_Tone_A\t\t\t\t0xe30\n * #define rRx_IQK_Tone_A\t\t\t\t0xe34\n * #define rTx_IQK_PI_A\t\t\t\t\t0xe38\n * #define rRx_IQK_PI_A\t\t\t\t\t0xe3c */\n\n/* #define rTx_IQK\t\t\t\t\t\t0xe40 */\n/* #define rRx_IQK\t\t\t\t\t\t0xe44 */\n/* #define rIQK_AGC_Pts\t\t\t\t\t0xe48 */\n/* #define rIQK_AGC_Rsp\t\t\t\t\t0xe4c */\n/* #define rTx_IQK_Tone_B\t\t\t\t0xe50 */\n/* #define rRx_IQK_Tone_B\t\t\t\t0xe54 */\n/* #define rTx_IQK_PI_B\t\t\t\t\t0xe58 */\n/* #define rRx_IQK_PI_B\t\t\t\t\t0xe5c */\n/* #define rIQK_AGC_Cont\t\t\t\t0xe60 */\n\n\n/* AFE-related */\n#define rA_AFEPwr1_Jaguar\t\t\t\t\t0xc60 /* dynamic AFE power control */\n#define rA_AFEPwr2_Jaguar\t\t\t\t\t0xc64 /* dynamic AFE power control */\n#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar\t0xc68\n#define rA_Tx_CCKBBON_OFDMRFON_Jaguar\t0xc6c\n#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar\t\t0xc70\n#define rA_Tx2Tx_RXCCK_Jaguar\t\t\t\t0xc74\n#define rA_Rx_OFDM_WaitRIFS_Jaguar\t\t\t0xc78\n#define rA_Rx2Rx_BT_Jaguar\t\t\t\t\t0xc7c\n#define rA_sleep_nav_Jaguar\t\t\t\t\t0xc80\n#define rA_pmpd_Jaguar\t\t\t\t\t\t0xc84\n#define rB_AFEPwr1_Jaguar\t\t\t\t\t0xe60 /* dynamic AFE power control */\n#define rB_AFEPwr2_Jaguar\t\t\t\t\t0xe64 /* dynamic AFE power control */\n#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar\t0xe68\n#define rB_Tx_CCKBBON_OFDMRFON_Jaguar\t0xe6c\n#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar\t\t0xe70\n#define rB_Tx2Tx_RXCCK_Jaguar\t\t\t\t0xe74\n#define rB_Rx_OFDM_WaitRIFS_Jaguar\t\t\t0xe78\n#define rB_Rx2Rx_BT_Jaguar\t\t\t\t\t0xe7c\n#define rB_sleep_nav_Jaguar\t\t\t\t\t0xe80\n#define rB_pmpd_Jaguar\t\t\t\t\t\t0xe84\n\n\n/* YN: mask these registers temporaily\n * #define rTx_Power_Before_IQK_A\t\t0xe94\n * #define rTx_Power_After_IQK_A\t\t\t0xe9c */\n\n/* #define rRx_Power_Before_IQK_A\t\t0xea0 */\n/* #define rRx_Power_Before_IQK_A_2\t\t0xea4 */\n/* #define rRx_Power_After_IQK_A\t\t\t0xea8 */\n/* #define rRx_Power_After_IQK_A_2\t\t0xeac */\n\n/* #define rTx_Power_Before_IQK_B\t\t0xeb4 */\n/* #define rTx_Power_After_IQK_B\t\t\t0xebc */\n\n/* #define rRx_Power_Before_IQK_B\t\t0xec0 */\n/* #define rRx_Power_Before_IQK_B_2\t\t0xec4 */\n/* #define rRx_Power_After_IQK_B\t\t\t0xec8 */\n/* #define rRx_Power_After_IQK_B_2\t\t0xecc */\n\n\n/* RSSI Dump */\n#define rA_RSSIDump_Jaguar\t\t\t0xBF0\n#define rB_RSSIDump_Jaguar\t\t\t0xBF1\n#define rS1_RXevmDump_Jaguar\t\t0xBF4\n#define rS2_RXevmDump_Jaguar\t\t0xBF5\n#define rA_RXsnrDump_Jaguar\t\t0xBF6\n#define rB_RXsnrDump_Jaguar\t\t0xBF7\n#define rA_CfoShortDump_Jaguar\t\t0xBF8\n#define rB_CfoShortDump_Jaguar\t\t0xBFA\n#define rA_CfoLongDump_Jaguar\t\t0xBEC\n#define rB_CfoLongDump_Jaguar\t\t0xBEE\n\n\n/* RF Register\n *   */\n#define RF_AC_Jaguar\t\t\t\t0x00\t/*  */\n#define RF_RF_Top_Jaguar\t\t\t0x07\t/*  */\n#define RF_TXLOK_Jaguar\t\t\t\t0x08\t/*  */\n#define RF_TXAPK_Jaguar\t\t\t\t0x0B\n#define RF_CHNLBW_Jaguar \t\t\t0x18\t/* RF channel and BW switch */\n#define RF_RCK1_Jaguar\t\t\t\t0x1c\t/*  */\n#define RF_RCK2_Jaguar\t\t\t\t0x1d\n#define RF_RCK3_Jaguar\t\t\t0x1e\n#define RF_ModeTableAddr\t\t\t0x30\n#define RF_ModeTableData0\t\t\t0x31\n#define RF_ModeTableData1\t\t\t0x32\n#define RF_TxLCTank_Jaguar\t0x54\n#define RF_APK_Jaguar\t\t\t\t0x63\n#define RF_LCK\t\t\t\t\t\t0xB4\n#define RF_WeLut_Jaguar\t\t\t\t0xEF\n\n#define bRF_CHNLBW_MOD_AG_Jaguar\t0x70300\n#define bRF_CHNLBW_BW\t\t\t\t0xc00\n\n\n/*\n * RL6052 Register definition\n *   */\n#define RF_AC\t\t\t\t\t\t0x00\t/*  */\n#define RF_IPA_A\t\t\t\t\t0x0C\t/*  */\n#define RF_TXBIAS_A\t\t\t\t\t0x0D\n#define RF_BS_PA_APSET_G9_G11\t\t0x0E\n#define RF_MODE1\t\t\t\t\t0x10\t/*  */\n#define RF_MODE2\t\t\t\t\t0x11\t/*  */\n#define RF_CHNLBW\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define RF_RCK_OS\t\t\t\t\t0x30\t/* RF TX PA control */\n#define RF_TXPA_G1\t\t\t\t\t0x31\t/* RF TX PA control */\n#define RF_TXPA_G2\t\t\t\t\t0x32\t/* RF TX PA control */\n#define RF_TXPA_G3\t\t\t\t\t0x33\t/* RF TX PA control */\n#define RF_0x52\t\t\t\t\t\t0x52\n#define RF_WE_LUT\t\t\t\t\t0xEF\n\n/*\n * Bit Mask\n *\n * 1. Page1(0x100) */\n#define bBBResetB\t\t\t\t\t0x100\t/* Useless now? */\n#define bGlobalResetB\t\t\t\t0x200\n#define bOFDMTxStart\t\t\t\t0x4\n#define bCCKTxStart\t\t\t\t\t0x8\n#define bCRC32Debug\t\t\t\t\t0x100\n#define bPMACLoopback\t\t\t\t0x10\n#define bTxLSIG\t\t\t\t\t\t0xffffff\n#define bOFDMTxRate\t\t\t\t\t0xf\n#define bOFDMTxReserved\t\t\t0x10\n#define bOFDMTxLength\t\t\t\t0x1ffe0\n#define bOFDMTxParity\t\t\t\t0x20000\n#define bTxHTSIG1\t\t\t\t\t0xffffff\n#define bTxHTMCSRate\t\t\t\t0x7f\n#define bTxHTBW\t\t\t\t\t\t0x80\n#define bTxHTLength\t\t\t\t\t0xffff00\n#define bTxHTSIG2\t\t\t\t\t0xffffff\n#define bTxHTSmoothing\t\t\t\t0x1\n#define bTxHTSounding\t\t\t\t0x2\n#define bTxHTReserved\t\t\t\t0x4\n#define bTxHTAggreation\t\t\t\t0x8\n#define bTxHTSTBC\t\t\t\t\t0x30\n#define bTxHTAdvanceCoding\t\t\t0x40\n#define bTxHTShortGI\t\t\t\t\t0x80\n#define bTxHTNumberHT_LTF\t\t\t0x300\n#define bTxHTCRC8\t\t\t\t\t0x3fc00\n#define bCounterReset\t\t\t\t0x10000\n#define bNumOfOFDMTx\t\t\t\t0xffff\n#define bNumOfCCKTx\t\t\t\t\t0xffff0000\n#define bTxIdleInterval\t\t\t\t0xffff\n#define bOFDMService\t\t\t\t0xffff0000\n#define bTxMACHeader\t\t\t\t0xffffffff\n#define bTxDataInit\t\t\t\t\t0xff\n#define bTxHTMode\t\t\t\t\t0x100\n#define bTxDataType\t\t\t\t\t0x30000\n#define bTxRandomSeed\t\t\t\t0xffffffff\n#define bCCKTxPreamble\t\t\t\t0x1\n#define bCCKTxSFD\t\t\t\t\t0xffff0000\n#define bCCKTxSIG\t\t\t\t\t0xff\n#define bCCKTxService\t\t\t\t0xff00\n#define bCCKLengthExt\t\t\t\t0x8000\n#define bCCKTxLength\t\t\t\t0xffff0000\n#define bCCKTxCRC16\t\t\t\t\t0xffff\n#define bCCKTxStatus\t\t\t\t\t0x1\n#define bOFDMTxStatus\t\t\t\t0x2\n\n\n/*\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 1. Page1(0x100)\n *   */\n#define rPMAC_Reset\t\t\t\t\t0x100\n#define rPMAC_TxStart\t\t\t\t0x104\n#define rPMAC_TxLegacySIG\t\t\t0x108\n#define rPMAC_TxHTSIG1\t\t\t\t0x10c\n#define rPMAC_TxHTSIG2\t\t\t\t0x110\n#define rPMAC_PHYDebug\t\t\t\t0x114\n#define rPMAC_TxPacketNum\t\t\t0x118\n#define rPMAC_TxIdle\t\t\t\t\t0x11c\n#define rPMAC_TxMACHeader0\t\t\t0x120\n#define rPMAC_TxMACHeader1\t\t\t0x124\n#define rPMAC_TxMACHeader2\t\t\t0x128\n#define rPMAC_TxMACHeader3\t\t\t0x12c\n#define rPMAC_TxMACHeader4\t\t\t0x130\n#define rPMAC_TxMACHeader5\t\t\t0x134\n#define rPMAC_TxDataType\t\t\t0x138\n#define rPMAC_TxRandomSeed\t\t0x13c\n#define rPMAC_CCKPLCPPreamble\t\t0x140\n#define rPMAC_CCKPLCPHeader\t\t0x144\n#define rPMAC_CCKCRC16\t\t\t\t0x148\n#define rPMAC_OFDMRxCRC32OK\t\t0x170\n#define rPMAC_OFDMRxCRC32Er\t\t0x174\n#define rPMAC_OFDMRxParityEr\t\t0x178\n#define rPMAC_OFDMRxCRC8Er\t\t\t0x17c\n#define rPMAC_CCKCRxRC16Er\t\t\t0x180\n#define rPMAC_CCKCRxRC32Er\t\t\t0x184\n#define rPMAC_CCKCRxRC32OK\t\t\t0x188\n#define rPMAC_TxStatus\t\t\t\t0x18c\n\n/*\n * 3. Page8(0x800)\n *   */\n#define rFPGA0_RFMOD\t\t\t\t0x800\t/* RF mode & CCK TxSC */ /* RF BW Setting?? */\n\n#define rFPGA0_TxInfo\t\t\t\t0x804\t/* Status report?? */\n#define rFPGA0_PSDFunction\t\t\t0x808\n#define rFPGA0_TxGainStage\t\t\t0x80c\t/* Set TX PWR init gain? */\n\n#define rFPGA0_XA_HSSIParameter1\t0x820\t/* RF 3 wire register */\n#define rFPGA0_XA_HSSIParameter2\t0x824\n#define rFPGA0_XB_HSSIParameter1\t0x828\n#define rFPGA0_XB_HSSIParameter2\t0x82c\n\n#define\trFPGA0_XA_LSSIParameter\t\t0x840\n#define\trFPGA0_XB_LSSIParameter\t\t0x844\n\n#define rFPGA0_XAB_SwitchControl\t0x858\t/* RF Channel switch */\n#define rFPGA0_XCD_SwitchControl\t0x85c\n\n#define rFPGA0_XAB_RFParameter\t\t0x878\t/* RF Parameter */\n#define rFPGA0_XCD_RFParameter\t\t0x87c\n\n#define rFPGA0_AnalogParameter1\t0x880\t/* Crystal cap setting RF-R/W protection for parameter4?? */\n#define rFPGA0_AnalogParameter2\t0x884\n#define rFPGA0_AnalogParameter3\t0x888\n#define rFPGA0_AdDaClockEn\t\t\t0x888\t/* enable ad/da clock1 for dual-phy */\n#define rFPGA0_AnalogParameter4\t0x88c\n\n#define\trFPGA0_XA_LSSIReadBack\t\t0x8a0\t/* Tranceiver LSSI Readback */\n#define\trFPGA0_XB_LSSIReadBack\t\t0x8a4\n#define\trFPGA0_XC_LSSIReadBack\t\t0x8a8\n#define\trFPGA0_XD_LSSIReadBack\t\t0x8ac\n\n#define rFPGA0_XCD_RFPara\t0x8b4\n#define\trFPGA0_PSDReport\t\t\t\t0x8b4\t/* Useless now */\n#define\tTransceiverA_HSPI_Readback\t\t0x8b8\t/* Transceiver A HSPI Readback */\n#define\tTransceiverB_HSPI_Readback\t\t0x8bc\t/* Transceiver B HSPI Readback */\n#define\trFPGA0_XAB_RFInterfaceRB\t\t0x8e0\t/* Useless now */ /* RF Interface Readback Value */\n#define\trFPGA0_XCD_RFInterfaceRB\t\t0x8e4\t/* Useless now */\n\n/*\n * 4. Page9(0x900)\n *   */\n#define rFPGA1_RFMOD\t\t\t\t0x900\t/* RF mode & OFDM TxSC */ /* RF BW Setting?? */\n#define\tREG_BB_TX_PATH_SEL_1_8814A\t\t0x93c\n#define\tREG_BB_TX_PATH_SEL_2_8814A\t\t0x940\n#define rFPGA1_TxBlock\t\t\t\t0x904\t/* Useless now */\n#define rFPGA1_DebugSelect\t\t\t0x908\t/* Useless now */\n#define rFPGA1_TxInfo\t\t\t\t0x90c\t/* Useless now */ /* Status report?? */\n/*Page 19 for TxBF*/\n#define\tREG_BB_TXBF_ANT_SET_BF1_8814A\t0x19ac\n#define\tREG_BB_TXBF_ANT_SET_BF0_8814A\t0x19b4\n/*\n * PageA(0xA00)\n *   */\n#define rCCK0_System\t\t\t\t0xa00\n#define rCCK0_AFESetting\t\t\t\t0xa04\t/* Disable init gain now */ /* Select RX path by RSSI */\n#define\trCCK0_DSPParameter2\t\t\t0xa1c\t/* SQ threshold */\n#define rCCK0_TxFilter1\t\t\t\t0xa20\n#define rCCK0_TxFilter2\t\t\t\t0xa24\n#define rCCK0_DebugPort\t\t\t\t0xa28\t/* debug port and Tx filter3 */\n#define\trCCK0_FalseAlarmReport\t\t\t0xa2c\t/* 0xa2d\tuseless now 0xa30-a4f channel report */\n\n/*\n * PageB(0xB00)\n *   */\n#define rPdp_AntA\t\t\t\t0xb00\n#define rPdp_AntA_4\t\t\t\t0xb04\n#define rConfig_Pmpd_AntA\t\t\t0xb28\n#define rConfig_AntA\t\t\t\t\t0xb68\n#define rConfig_AntB\t\t\t\t\t0xb6c\n#define rPdp_AntB\t\t\t\t\t0xb70\n#define rPdp_AntB_4\t\t\t\t\t0xb74\n#define rConfig_Pmpd_AntB\t\t\t0xb98\n#define rAPK\t\t\t\t\t\t\t0xbd8\n\n/*\n * 6. PageC(0xC00)\n *   */\n#define rOFDM0_LSTF\t\t\t\t\t0xc00\n\n#define rOFDM0_TRxPathEnable\t\t0xc04\n#define rOFDM0_TRMuxPar\t\t\t0xc08\n#define rOFDM0_TRSWIsolation\t\t0xc0c\n\n#define rOFDM0_XARxAFE\t\t\t\t0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */\n#define rOFDM0_XARxIQImbalance    \t0xc14  /* RxIQ imblance matrix */\n#define rOFDM0_XBRxAFE\t\t0xc18\n#define rOFDM0_XBRxIQImbalance\t0xc1c\n#define rOFDM0_XCRxAFE\t\t0xc20\n#define rOFDM0_XCRxIQImbalance\t0xc24\n#define rOFDM0_XDRxAFE\t\t0xc28\n#define rOFDM0_XDRxIQImbalance\t0xc2c\n\n#define rOFDM0_RxDetector1\t\t\t0xc30  /* PD, BW & SBD\t */ /* DM tune init gain */\n#define rOFDM0_RxDetector2\t\t\t0xc34  /* SBD & Fame Sync. */\n#define rOFDM0_RxDetector3\t\t\t0xc38  /* Frame Sync. */\n#define rOFDM0_RxDetector4\t\t\t0xc3c  /* PD, SBD, Frame Sync & Short-GI */\n\n#define rOFDM0_RxDSP\t\t\t\t0xc40  /* Rx Sync Path */\n#define rOFDM0_CFOandDAGC\t\t\t0xc44  /* CFO & DAGC */\n#define rOFDM0_CCADropThreshold\t0xc48 /* CCA Drop threshold */\n#define rOFDM0_ECCAThreshold\t\t0xc4c /* energy CCA */\n\n#define rOFDM0_XAAGCCore1\t\t\t0xc50\t/* DIG */\n#define rOFDM0_XAAGCCore2\t\t\t0xc54\n#define rOFDM0_XBAGCCore1\t\t\t0xc58\n#define rOFDM0_XBAGCCore2\t\t\t0xc5c\n#define rOFDM0_XCAGCCore1\t\t\t0xc60\n#define rOFDM0_XCAGCCore2\t\t\t0xc64\n#define rOFDM0_XDAGCCore1\t\t\t0xc68\n#define rOFDM0_XDAGCCore2\t\t\t0xc6c\n\n#define rOFDM0_AGCParameter1\t\t0xc70\n#define rOFDM0_AGCParameter2\t\t0xc74\n#define rOFDM0_AGCRSSITable\t\t0xc78\n#define rOFDM0_HTSTFAGC\t\t\t0xc7c\n\n#define rOFDM0_XATxIQImbalance\t\t0xc80\t/* TX PWR TRACK and DIG */\n#define rOFDM0_XATxAFE\t\t\t\t0xc84\n#define rOFDM0_XBTxIQImbalance\t\t0xc88\n#define rOFDM0_XBTxAFE\t\t\t\t0xc8c\n#define rOFDM0_XCTxIQImbalance\t\t0xc90\n#define rOFDM0_XCTxAFE\t\t0xc94\n#define rOFDM0_XDTxIQImbalance\t\t0xc98\n#define rOFDM0_XDTxAFE\t\t\t\t0xc9c\n\n#define rOFDM0_RxIQExtAnta\t\t\t0xca0\n#define rOFDM0_TxCoeff1\t\t\t\t0xca4\n#define rOFDM0_TxCoeff2\t\t\t\t0xca8\n#define rOFDM0_TxCoeff3\t\t\t\t0xcac\n#define rOFDM0_TxCoeff4\t\t\t\t0xcb0\n#define rOFDM0_TxCoeff5\t\t\t\t0xcb4\n#define rOFDM0_TxCoeff6\t\t\t\t0xcb8\n#define rOFDM0_RxHPParameter\t\t0xce0\n#define rOFDM0_TxPseudoNoiseWgt\t0xce4\n#define rOFDM0_FrameSync\t\t\t0xcf0\n#define rOFDM0_DFSReport\t\t\t0xcf4\n\n/*\n * 7. PageD(0xD00)\n *   */\n#define rOFDM1_LSTF\t\t\t\t\t0xd00\n#define rOFDM1_TRxPathEnable\t\t0xd04\n\n/*\n * 8. PageE(0xE00)\n *   */\n#define rTxAGC_A_Rate18_06\t\t\t0xe00\n#define rTxAGC_A_Rate54_24\t\t\t0xe04\n#define rTxAGC_A_CCK1_Mcs32\t\t0xe08\n#define rTxAGC_A_Mcs03_Mcs00\t\t0xe10\n#define rTxAGC_A_Mcs07_Mcs04\t\t0xe14\n#define rTxAGC_A_Mcs11_Mcs08\t\t0xe18\n#define rTxAGC_A_Mcs15_Mcs12\t\t0xe1c\n\n#define rTxAGC_B_Rate18_06\t\t\t0x830\n#define rTxAGC_B_Rate54_24\t\t\t0x834\n#define rTxAGC_B_CCK1_55_Mcs32\t0x838\n#define rTxAGC_B_Mcs03_Mcs00\t\t0x83c\n#define rTxAGC_B_Mcs07_Mcs04\t\t0x848\n#define rTxAGC_B_Mcs11_Mcs08\t\t0x84c\n#define rTxAGC_B_Mcs15_Mcs12\t\t0x868\n#define rTxAGC_B_CCK11_A_CCK2_11\t0x86c\n\n#define rFPGA0_IQK\t\t\t\t\t0xe28\n#define rTx_IQK_Tone_A\t\t\t\t0xe30\n#define rRx_IQK_Tone_A\t\t\t\t0xe34\n#define rTx_IQK_PI_A\t\t\t\t0xe38\n#define rRx_IQK_PI_A\t\t\t\t0xe3c\n\n#define rTx_IQK\t\t\t\t\t\t0xe40\n#define rRx_IQK\t\t\t\t\t\t0xe44\n#define rIQK_AGC_Pts\t\t\t\t\t0xe48\n#define rIQK_AGC_Rsp\t\t\t\t0xe4c\n#define rTx_IQK_Tone_B\t\t\t\t0xe50\n#define rRx_IQK_Tone_B\t\t\t\t0xe54\n#define rTx_IQK_PI_B\t\t\t\t\t0xe58\n#define rRx_IQK_PI_B\t\t\t\t\t0xe5c\n#define rIQK_AGC_Cont\t\t\t\t0xe60\n\n#define rBlue_Tooth\t\t\t\t\t0xe6c\n#define rRx_Wait_CCA\t\t\t\t0xe70\n#define rTx_CCK_RFON\t\t\t\t0xe74\n#define rTx_CCK_BBON\t\t\t\t0xe78\n#define rTx_OFDM_RFON\t\t\t\t0xe7c\n#define rTx_OFDM_BBON\t\t\t\t0xe80\n#define rTx_To_Rx\t\t\t\t\t0xe84\n#define rTx_To_Tx\t\t\t\t\t0xe88\n#define rRx_CCK\t\t\t\t\t\t0xe8c\n\n#define rTx_Power_Before_IQK_A\t\t0xe94\n#define rTx_Power_After_IQK_A\t\t0xe9c\n\n#define rRx_Power_Before_IQK_A\t\t0xea0\n#define rRx_Power_Before_IQK_A_2\t0xea4\n#define rRx_Power_After_IQK_A\t\t0xea8\n#define rRx_Power_After_IQK_A_2\t\t0xeac\n\n#define rTx_Power_Before_IQK_B\t\t0xeb4\n#define rTx_Power_After_IQK_B\t\t0xebc\n\n#define rRx_Power_Before_IQK_B\t\t0xec0\n#define rRx_Power_Before_IQK_B_2\t0xec4\n#define rRx_Power_After_IQK_B\t\t0xec8\n#define rRx_Power_After_IQK_B_2\t\t0xecc\n\n#define rRx_OFDM\t\t\t\t\t0xed0\n#define rRx_Wait_RIFS\t\t\t\t0xed4\n#define rRx_TO_Rx\t\t\t\t\t0xed8\n#define rStandby\t\t\t\t\t\t0xedc\n#define rSleep\t\t\t\t\t\t0xee0\n#define rPMPD_ANAEN\t\t\t\t0xeec\n\n\n/* 2. Page8(0x800) */\n#define bRFMOD\t\t\t\t\t\t0x1\t/* Reg 0x800 rFPGA0_RFMOD */\n#define bJapanMode\t\t\t\t\t0x2\n#define bCCKTxSC\t\t\t\t\t0x30\n#define bCCKEn\t\t\t\t\t\t0x1000000\n#define bOFDMEn\t\t\t\t\t\t0x2000000\n#define bXBTxAGC                  \t\t\t0xf00\t/* Reg 80c rFPGA0_TxGainStage */\n#define bXCTxAGC\t\t\t0xf000\n#define bXDTxAGC\t\t\t0xf0000\n\n/* 4. PageA(0xA00) */\n#define bCCKBBMode                \t\t\t0x3\t/* Useless */\n#define bCCKTxPowerSaving\t\t0x80\n#define bCCKRxPowerSaving\t\t0x40\n\n#define bCCKSideBand              \t\t0x10\t/* Reg 0xa00 rCCK0_System 20/40 switch */\n\n#define bCCKScramble              \t\t0x8\t/* Useless */\n#define bCCKAntDiversity\t\t\t0x8000\n#define bCCKCarrierRecovery\t\t0x4000\n#define bCCKTxRate\t\t\t0x3000\n#define bCCKDCCancel\t\t\t0x0800\n#define bCCKISICancel\t\t\t0x0400\n#define bCCKMatchFilter\t\t0x0200\n#define bCCKEqualizer\t\t\t0x0100\n#define bCCKPreambleDetect\t\t0x800000\n#define bCCKFastFalseCCA\t\t0x400000\n#define bCCKChEstStart\t\t0x300000\n#define bCCKCCACount\t\t0x080000\n#define bCCKcs_lim\t\t\t0x070000\n#define bCCKBistMode\t\t\t0x80000000\n#define bCCKCCAMask\t\t\t0x40000000\n#define bCCKTxDACPhase\t\t0x4\n#define bCCKRxADCPhase         \t   \t0x20000000   /* r_rx_clk */\n#define bCCKr_cp_mode0\t\t0x0100\n#define bCCKTxDCOffset\t\t0xf0\n#define bCCKRxDCOffset\t\t0xf\n#define bCCKCCAMode\t\t\t0xc000\n#define bCCKFalseCS_lim\t\t0x3f00\n#define bCCKCS_ratio\t\t\t0xc00000\n#define bCCKCorgBit_sel\t\t0x300000\n#define bCCKPD_lim\t\t\t0x0f0000\n#define bCCKNewCCA\t\t0x80000000\n#define bCCKRxHPofIG\t\t0x8000\n#define bCCKRxIG\t\t\t0x7f00\n#define bCCKLNAPolarity\t\t0x800000\n#define bCCKRx1stGain\t\t0x7f0000\n#define bCCKRFExtend              \t\t0x20000000 /* CCK Rx Iinital gain polarity */\n#define bCCKRxAGCSatLevel\t\t0x1f000000\n#define bCCKRxAGCSatCount\t\t0xe0\n#define bCCKRxRFSettle            \t\t0x1f       /* AGCsamp_dly */\n#define bCCKFixedRxAGC\t\t0x8000\n/* #define bCCKRxAGCFormat\t\t0x4000 */   /* remove to HSSI register 0x824 */\n#define bCCKAntennaPolarity\t\t0x2000\n#define bCCKTxFilterType\t\t0x0c00\n#define bCCKRxAGCReportType\t\t0x0300\n#define bCCKRxDAGCEn\t\t0x80000000\n#define bCCKRxDAGCPeriod\t\t0x20000000\n#define bCCKRxDAGCSatLevel\t\t0x1f000000\n#define bCCKTimingRecovery\t\t0x800000\n#define bCCKTxC0\t\t\t0x3f0000\n#define bCCKTxC1\t\t\t0x3f000000\n#define bCCKTxC2\t\t\t0x3f\n#define bCCKTxC3\t\t\t0x3f00\n#define bCCKTxC4\t\t\t0x3f0000\n#define bCCKTxC5\t\t\t0x3f000000\n#define bCCKTxC6\t\t\t0x3f\n#define bCCKTxC7\t\t\t0x3f00\n#define bCCKDebugPort\t\t0xff0000\n#define bCCKDACDebug\t\t0x0f000000\n#define bCCKFalseAlarmEnable\t\t0x8000\n#define bCCKFalseAlarmRead\t\t0x4000\n#define bCCKTRSSI\t\t\t0x7f\n#define bCCKRxAGCReport\t\t0xfe\n#define bCCKRxReport_AntSel\t\t0x80000000\n#define bCCKRxReport_MFOff\t\t0x40000000\n#define bCCKRxRxReport_SQLoss\t0x20000000\n#define bCCKRxReport_Pktloss\t\t0x10000000\n#define bCCKRxReport_Lockedbit\t0x08000000\n#define bCCKRxReport_RateError\t0x04000000\n#define bCCKRxReport_RxRate\t\t0x03000000\n#define bCCKRxFACounterLower\t0xff\n#define bCCKRxFACounterUpper\t0xff000000\n#define bCCKRxHPAGCStart\t\t0xe000\n#define bCCKRxHPAGCFinal\t\t0x1c00\n#define bCCKRxFalseAlarmEnable\t0x8000\n#define bCCKFACounterFreeze\t\t0x4000\n#define bCCKTxPathSel\t\t0x10000000\n#define bCCKDefaultRxPath\t\t0xc000000\n#define bCCKOptionRxPath\t\t0x3000000\n\n#define\t\tRF_T_METER_88E\t\t\t\t0x42\n\n/* 6. PageE(0xE00) */\n#define bSTBCEn                  \t\t\t0x4\t/* Useless */\n#define bAntennaMapping\t\t0x10\n#define bNss\t\t\t\t0x20\n#define bCFOAntSumD\t\t0x200\n#define bPHYCounterReset\t\t0x8000000\n#define bCFOReportGet\t\t\t0x4000000\n#define bOFDMContinueTx\t\t0x10000000\n#define bOFDMSingleCarrier\t\t0x20000000\n#define bOFDMSingleTone\t\t0x40000000\n\n\n/*\n * Other Definition\n *   */\n\n#define bEnable                   0x1\t/* Useless */\n#define bDisable                  0x0\n\n/* byte endable for srwrite */\n#define bByte0                    \t\t0x1\t/* Useless */\n#define bByte1\t\t0x2\n#define bByte2\t\t0x4\n#define bByte3\t\t0x8\n#define bWord0\t\t0x3\n#define bWord1\t\t0xc\n#define bDWord\t\t0xf\n\n/* for PutRegsetting & GetRegSetting BitMask */\n#define bMaskByte0                \t\t0xff\t/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */\n#define bMaskByte1\t\t0xff00\n#define bMaskByte2\t\t0xff0000\n#define bMaskByte3\t\t0xff000000\n#define bMaskHWord\t0xffff0000\n#define bMaskLWord\t\t0x0000ffff\n#define bMaskDWord\t0xffffffff\n#define bMaskH3Bytes\t\t\t\t0xffffff00\n#define bMask12Bits\t\t\t\t0xfff\n#define bMaskH4Bits\t\t\t\t0xf0000000\n#define bMaskOFDM_D\t\t\t0xffc00000\n#define bMaskCCK\t\t\t\t0x3f3f3f3f\n#define bMask7bits\t\t\t\t0x7f\n#define bMaskByte2HighNibble\t\t\t0x00f00000\n#define bMaskByte3LowNibble\t\t\t\t0x0f000000\n#define bMaskL3Bytes\t\t\t0x00ffffff\n\n/*--------------------------Define Parameters-------------------------------*/\n\n\n#endif\n"
  },
  {
    "path": "include/Hal8814PwrSeq.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n\n#ifndef __HAL8814PWRSEQ_H__\n#define __HAL8814PWRSEQ_H__\n\n#include \"HalPwrSeqCmd.h\"\n\n/*\n\tCheck document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf\n\tThere are 6 HW Power States:\n\t0: POFF--Power Off\n\t1: PDN--Power Down\n\t2: CARDEMU--Card Emulation\n\t3: ACT--Active Mode\n\t4: LPS--Low Power State\n\t5: SUS--Suspend\n\n\tThe transision from different states are defined below\n\tTRANS_CARDEMU_TO_ACT\n\tTRANS_ACT_TO_CARDEMU\n\tTRANS_CARDEMU_TO_SUS\n\tTRANS_SUS_TO_CARDEMU\n\tTRANS_CARDEMU_TO_PDN\n\tTRANS_ACT_TO_LPS\n\tTRANS_LPS_TO_ACT\n\n\tTRANS_END\n*/\n#define\tRTL8814A_TRANS_CARDEMU_TO_ACT_STEPS\t16\n#define\tRTL8814A_TRANS_ACT_TO_CARDEMU_STEPS\t20\n#define\tRTL8814A_TRANS_CARDEMU_TO_SUS_STEPS\t17\n#define\tRTL8814A_TRANS_SUS_TO_CARDEMU_STEPS\t15\n#define\tRTL8814A_TRANS_CARDEMU_TO_PDN_STEPS\t17\n#define\tRTL8814A_TRANS_PDN_TO_CARDEMU_STEPS\t16\n#define\tRTL8814A_TRANS_ACT_TO_LPS_STEPS\t20\n#define\tRTL8814A_TRANS_LPS_TO_ACT_STEPS\t15\n#define\tRTL8814A_TRANS_END_STEPS\t1\n\n\n#define RTL8814A_TRANS_CARDEMU_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/\t\\\n\t{0x002B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /* ??0x28[24]=1, enable pll phase select*/ \\\n\t{0x0015, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT3 | BIT2 | BIT1), (BIT3 | BIT2 | BIT1)},/* 0x14[11:9]=3'b111, OCP current threshold = 1.5A */ \\\n\t{0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0E, 0x08},/* 0x2C[11:9]=3'b100, select lpf R3 */ \\\n\t{0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x70, 0x50},/* 0x2C[14:12]=3'b101, select lpf Rs*/ \\\n\t{0x007B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x78[30]=1'b1, SDM order select*/ \\\n\t/*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, */ /* disable HWPDN 0x04[15]=0*/ \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/\t\\\n\t{0x00F0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* */\t\\\n\t{0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x30, 0x20},/* */\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/\n\n#define RTL8814A_TRANS_ACT_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4\tturn off 3-wire */\t\\\n\t{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4\tturn off 3-wire */\t\\\n\t{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},  /* 0x2[0] = 0\t RESET BB, CLOSE RF */\t\\\n\t{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/\t\\\n\t{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/\t\t\t\\\n\t{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},  /* 0x2[0] = 0\t RESET BB, CLOSE RF */\t\\\n\t{0x0002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/\t\\\n\t{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/\t\t\t\\\n\t{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},  /*0x1F[7:0] = 0 turn off RF*/\t\\\n\t/*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},*/  /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x28},   /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/\t\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},   /*0x8[1] = 0 ANA clk = 500k */\t\\\n\t/*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0},*/   /*  0x02[1:0] = 0\treset BB */\t\\\n\t{0x0066, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},   /*0x66[7]=0, disable ckreq for gpio7 output SUS */\t\\\n\t{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},   /*0x41[4]=0, disable sic for gpio7 output SUS */\t\\\n\t{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},   /*0x42[1]=0, disable ckout for gpio7 output SUS */\t\\\n\t{0x004e, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},   /*0x4E[5]=1, disable LED2 for gpio7 output SUS */\t\\\n\t{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},   /*0x41[0]=0, disable uart for gpio7 output SUS */\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/\n\n#define RTL8814A_TRANS_CARDEMU_TO_SUS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0c},\\\n\t{0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0E},\\\n\t{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x07},/* gpio11 input mode, gpio10~8 output mode */\t\\\n\t{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */\t\\\n\t{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */\t\\\n\t{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */\t\\\n\t{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x14[13] = 1 turn on ZCD */\t\\\n\t{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x14[14] =1 trun on ZCD */\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */\t\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */\t\\\n\t{0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */\t\\\n\t{0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend */\n\n#define RTL8814A_TRANS_SUS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0 enable WL suspend*/   \\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */\t\\\n\t{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x14[14] =0 trun off ZCD */\t\\\n\t{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x14[13] = 0 turn off ZCD */\t\\\n\t{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */\t\\\n\t{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */\n\n#define RTL8814A_TRANS_CARDEMU_TO_CARDDIS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t/**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/\t\\\n\t/**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/\t\\\n\t{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 3081*/\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x01}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/\t\\\n\t{0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x30}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/\t\\\n\t/*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},*/   \\\n\t/*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},*/   \\\n\t/*{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},*/  /* gpio11 input mode, gpio10~8 output mode */\t\\\n\t{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */\t\\\n\t{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */\t\\\n\t{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */\t\\\n\t{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x15[6] =1 trun on ZCD output */\t\\\n\t{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x15[5] = 1 turn on ZCD */\t\\\n\t{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*0x12[6] = 0 force PFM mode */\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */\t\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/\t\\\n\t{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x01f[1]=0 , disable RFC_0  control  REG_RF_CTRL_8814A */\t\\\n\t{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x020[1]=0 , disable RFC_1  control  REG_RF_CTRL_8814A */\t\\\n\t{0x0021, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x021[1]=0 , disable RFC_2  control  REG_RF_CTRL_8814A */\t\\\n\t{0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x076[1]=0 , disable RFC_3  control REG_OPT_CTRL_8814A +2 */\t\\\n\t{0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */\t\\\n\t{0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend*/\n\n#define RTL8814A_TRANS_CARDDIS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/                       \\\n\t{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*0x12[6] = 1 force PWM mode */\t\\\n\t{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x15[5] = 0 turn off ZCD */\t\\\n\t{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x15[6] =0 trun off ZCD output */\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */\t\\\n\t{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */\t\\\n\t{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /* gpio11 input mode, gpio10~8 input mode */ \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0, enable WL suspend*/\t\\\n\t/*{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},*/ /*0x03[2] = 1, enable 3081*/\t\\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/\t\t\\\n\t{0x0071, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*0x70[10] = 0, CPHY_MBIAS_EN disable*/\n\n\n#define RTL8814A_TRANS_CARDEMU_TO_PDN\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/\n\n#define RTL8814A_TRANS_PDN_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/\n\n#define RTL8814A_TRANS_ACT_TO_LPS\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/\t\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/\t\t\\\n\t{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4\tturn off 3-wire */\t\\\n\t{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4\tturn off 3-wire */\t\\\n\t{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/\t\\\n\t{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\t\\\n\t{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/\t\t\t\\\n\t{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/\t\\\n\t{0x0002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\t\\\n\t{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/\t\t\t\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/\t\t\t\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\t\t\\\n\t{0x05F1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Respond TxOK to scheduler*/\n\n\n#define RTL8814A_TRANS_LPS_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\t\\\n\t{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\t\\\n\t{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /* Delay*/\t\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.\t0x08[4] = 0\t\t switch TSF to 40M*/\t\\\n\t{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /* Polling 0x109[7]=0  TSF in 40M*/\t\t\t\\\n\t/*{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, */ /*.\t??0x29[7:6] = 2b'00\t enable BB clock*/\t\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.\t0x101[1] = 1*/\t\t\t\t\t\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.\t0x100[7:0] = 0xFF\t enable WMAC TRX*/\t\\\n\t{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.\t0x02[1:0] = 2b'11\t enable BB macro*/\t\\\n\t{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.\t0x1002[1:0] = 2b'11\t enable BB macro*/\t\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.\t0x522 = 0*/\n\n#define RTL8814A_TRANS_END\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\\\n\t{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},\n\n\nextern WLAN_PWR_CFG rtl8814A_power_on_flow[RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8814A_radio_off_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8814A_card_disable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8814A_card_enable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8814A_suspend_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8814A_resume_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8814A_hwpdn_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8814A_enter_lps_flow[RTL8814A_TRANS_ACT_TO_LPS_STEPS + RTL8814A_TRANS_END_STEPS];\nextern WLAN_PWR_CFG rtl8814A_leave_lps_flow[RTL8814A_TRANS_LPS_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS];\n\n#endif /* __HAL8814PWRSEQ_H__ */\n"
  },
  {
    "path": "include/Hal8821APwrSeq.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef REALTEK_POWER_SEQUENCE_8821\n#define REALTEK_POWER_SEQUENCE_8821\n\n#include \"HalPwrSeqCmd.h\"\n\n/*\n\tCheck document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd\n\tThere are 6 HW Power States:\n\t0: POFF--Power Off\n\t1: PDN--Power Down\n\t2: CARDEMU--Card Emulation\n\t3: ACT--Active Mode\n\t4: LPS--Low Power State\n\t5: SUS--Suspend\n\n\tThe transision from different states are defined below\n\tTRANS_CARDEMU_TO_ACT\n\tTRANS_ACT_TO_CARDEMU\n\tTRANS_CARDEMU_TO_SUS\n\tTRANS_SUS_TO_CARDEMU\n\tTRANS_CARDEMU_TO_PDN\n\tTRANS_ACT_TO_LPS\n\tTRANS_LPS_TO_ACT\n\n\tTRANS_END\n*/\n#define\tRTL8821A_TRANS_CARDEMU_TO_ACT_STEPS\t25\n#define\tRTL8821A_TRANS_ACT_TO_CARDEMU_STEPS\t15\n#define\tRTL8821A_TRANS_CARDEMU_TO_SUS_STEPS\t15\n#define\tRTL8821A_TRANS_SUS_TO_CARDEMU_STEPS\t15\n#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS\t15\n#define\tRTL8821A_TRANS_CARDEMU_TO_PDN_STEPS\t15\n#define\tRTL8821A_TRANS_PDN_TO_CARDEMU_STEPS\t15\n#define\tRTL8821A_TRANS_ACT_TO_LPS_STEPS\t15\n#define\tRTL8821A_TRANS_LPS_TO_ACT_STEPS\t15\n#define\tRTL8821A_TRANS_END_STEPS\t1\n\n\n#define RTL8821A_TRANS_CARDEMU_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \\\n\t{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/\t\\\n\t{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \\\n\t{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/\t\\\n\t{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/\t\\\n\t{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */\t\\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/\t\\\n\t{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */\\\n\t{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5 | BIT4), (BIT5 | BIT4)},/*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */\\\n\t{0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*anapar_mac<118> , 0x25[6]=0 by wlan single function*/\\\n\t{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\\\n\t{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\\\n\t{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\\\n\t{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\\\n\t{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\\\n\t{0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3A},/*0x7A = 0x3A start BT*/\\\n\t{0x002E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF , 0x82 },/* 0x2C[23:12]=0x820 ; XTAL trim */ \\\n\t{0x0010, PWR_CUT_A_MSK , PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 },/* 0x10[6]=1 ; MPsW0x2CvA0x10[6]]1~WLAN */ \\\n\n\n#define RTL8821A_TRANS_ACT_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/\t\\\n\t{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from register 0x65[2] */\\\n\t{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/\t\\\n\t{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \\\n\t{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/   \\\n\n\n#define RTL8821A_TRANS_CARDEMU_TO_SUS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/\n\n#define RTL8821A_TRANS_SUS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\n\n#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/\t\\\n\t{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/\n\n#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/\t\\\n\t{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\\\n\t{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/\n\n\n#define RTL8821A_TRANS_CARDEMU_TO_PDN\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \\\n\t{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \\\n\t{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/\n\n#define RTL8821A_TRANS_PDN_TO_CARDEMU\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/\n\n#define RTL8821A_TRANS_ACT_TO_LPS\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/\t\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/\t\\\n\t{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\t\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/\t\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/\t\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\t\\\n\t{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/\t\\\n\t{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/\t\\\n\n\n#define RTL8821A_TRANS_LPS_TO_ACT\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\\\n\t{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\\\n\t{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\\\n\t{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.\t0x08[4] = 0\t\t switch TSF to 40M*/\\\n\t{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\\\n\t{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.\t0x29[7:6] = 2b'00\t enable BB clock*/\\\n\t{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.\t0x101[1] = 1*/\\\n\t{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.\t0x100[7:0] = 0xFF\t enable WMAC TRX*/\\\n\t{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.\t0x02[1:0] = 2b'11\t enable BB macro*/\\\n\t{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.\t0x522 = 0*/\n\n#define RTL8821A_TRANS_END\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* format */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\t\t\t\t\t\t\t\t\\\n\t{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},\n\n\n\textern WLAN_PWR_CFG rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8821A_card_enable_flow[RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS + RTL8821A_TRANS_END_STEPS];\n\textern WLAN_PWR_CFG rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];\n\n#endif\n"
  },
  {
    "path": "include/HalPwrSeqCmd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HALPWRSEQCMD_H__\n#define __HALPWRSEQCMD_H__\n\n#include <drv_types.h>\n\n/*---------------------------------------------*/\n/* 3 The value of cmd: 4 bits\n *---------------------------------------------*/\n#define PWR_CMD_READ\t\t\t0x00\n/* offset: the read register offset\n * msk: the mask of the read value\n * value: N/A, left by 0\n * note: dirver shall implement this function by read & msk */\n\n#define PWR_CMD_WRITE\t\t\t0x01\n/* offset: the read register offset\n * msk: the mask of the write bits\n * value: write value\n * note: driver shall implement this cmd by read & msk after write */\n\n#define PWR_CMD_POLLING\t\t\t0x02\n/* offset: the read register offset\n * msk: the mask of the polled value\n * value: the value to be polled, masked by the msd field.\n * note: driver shall implement this cmd by\n * do {\n * if( (Read(offset) & msk) == (value & msk) )\n * break;\n * } while(not timeout); */\n\n#define PWR_CMD_DELAY\t\t\t0x03\n/* offset: the value to delay\n * msk: N/A\n * value: the unit of delay, 0: us, 1: ms */\n\n#define PWR_CMD_END\t\t\t\t0x04\n/* offset: N/A\n * msk: N/A\n * value: N/A */\n\n/*---------------------------------------------*/\n/* 3 The value of base: 4 bits\n *---------------------------------------------\n    * define the base address of each block */\n#define PWR_BASEADDR_MAC\t\t0x00\n#define PWR_BASEADDR_USB\t\t0x01\n#define PWR_BASEADDR_PCIE\t\t0x02\n#define PWR_BASEADDR_SDIO\t\t0x03\n\n/*---------------------------------------------*/\n/* 3 The value of interface_msk: 4 bits\n *---------------------------------------------*/\n#define\tPWR_INTF_SDIO_MSK\t\tBIT(0)\n#define\tPWR_INTF_USB_MSK\t\tBIT(1)\n#define\tPWR_INTF_PCI_MSK\t\tBIT(2)\n#define\tPWR_INTF_ALL_MSK\t\t(BIT(0) | BIT(1) | BIT(2) | BIT(3))\n\n/*---------------------------------------------*/\n/* 3 The value of fab_msk: 4 bits\n *---------------------------------------------*/\n#define\tPWR_FAB_TSMC_MSK\t\tBIT(0)\n#define\tPWR_FAB_UMC_MSK\t\t\tBIT(1)\n#define\tPWR_FAB_ALL_MSK\t\t\t(BIT(0) | BIT(1) | BIT(2) | BIT(3))\n\n/*---------------------------------------------*/\n/* 3 The value of cut_msk: 8 bits\n *---------------------------------------------*/\n#define\tPWR_CUT_TESTCHIP_MSK\tBIT(0)\n#define\tPWR_CUT_A_MSK\t\t\tBIT(1)\n#define\tPWR_CUT_B_MSK\t\t\tBIT(2)\n#define\tPWR_CUT_C_MSK\t\t\tBIT(3)\n#define\tPWR_CUT_D_MSK\t\t\tBIT(4)\n#define\tPWR_CUT_E_MSK\t\t\tBIT(5)\n#define\tPWR_CUT_F_MSK\t\t\tBIT(6)\n#define\tPWR_CUT_G_MSK\t\t\tBIT(7)\n#define\tPWR_CUT_ALL_MSK\t\t\t0xFF\n\n\ntypedef enum _PWRSEQ_CMD_DELAY_UNIT_ {\n\tPWRSEQ_DELAY_US,\n\tPWRSEQ_DELAY_MS,\n} PWRSEQ_DELAY_UNIT;\n\ntypedef struct _WL_PWR_CFG_ {\n\tu16 offset;\n\tu8 cut_msk;\n\tu8 fab_msk:4;\n\tu8 interface_msk:4;\n\tu8 base:4;\n\tu8 cmd:4;\n\tu8 msk;\n\tu8 value;\n} WLAN_PWR_CFG, *PWLAN_PWR_CFG;\n\n\n#define GET_PWR_CFG_OFFSET(__PWR_CMD)\t\t((__PWR_CMD).offset)\n#define GET_PWR_CFG_CUT_MASK(__PWR_CMD)\t\t((__PWR_CMD).cut_msk)\n#define GET_PWR_CFG_FAB_MASK(__PWR_CMD)\t\t((__PWR_CMD).fab_msk)\n#define GET_PWR_CFG_INTF_MASK(__PWR_CMD)\t((__PWR_CMD).interface_msk)\n#define GET_PWR_CFG_BASE(__PWR_CMD)\t\t\t((__PWR_CMD).base)\n#define GET_PWR_CFG_CMD(__PWR_CMD)\t\t\t((__PWR_CMD).cmd)\n#define GET_PWR_CFG_MASK(__PWR_CMD)\t\t\t((__PWR_CMD).msk)\n#define GET_PWR_CFG_VALUE(__PWR_CMD)\t\t((__PWR_CMD).value)\n\n\n/* ********************************************************************************\n *\tPrototype of protected function.\n * ******************************************************************************** */\nu8 HalPwrSeqCmdParsing(\n\tPADAPTER\t\tpadapter,\n\tu8\t\t\t\tCutVersion,\n\tu8\t\t\t\tFabVersion,\n\tu8\t\t\t\tInterfaceType,\n\tWLAN_PWR_CFG\tPwrCfgCmd[]);\n\n#endif\n"
  },
  {
    "path": "include/HalVerDef.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HAL_VERSION_DEF_H__\n#define __HAL_VERSION_DEF_H__\n\n#define TRUE\t_TRUE\n#define FALSE\t_FALSE\n\n/* HAL_IC_TYPE_E */\ntypedef enum tag_HAL_IC_Type_Definition {\n\tCHIP_8192S\t=\t0,\n\tCHIP_8188C\t=\t1,\n\tCHIP_8192C\t=\t2,\n\tCHIP_8192D\t=\t3,\n\tCHIP_8723A\t=\t4,\n\tCHIP_8188E\t=\t5,\n\tCHIP_8812\t=\t6,\n\tCHIP_8821\t=\t7,\n\tCHIP_8723B\t=\t8,\n\tCHIP_8192E\t=\t9,\n\tCHIP_8814A\t=\t10,\n\tCHIP_8703B\t=\t11,\n\tCHIP_8188F\t=\t12,\n\tCHIP_8822B\t=\t13,\n\tCHIP_8723D\t=\t14,\n\tCHIP_8821C\t=\t15,\n\tCHIP_8710B\t=\t16,\n\tCHIP_8192F\t=\t17,\n\tCHIP_8188GTV =\t18,\n\tCHIP_8822C\t=\t19,\n} HAL_IC_TYPE_E;\n\n/* HAL_CHIP_TYPE_E */\ntypedef enum tag_HAL_CHIP_Type_Definition {\n\tTEST_CHIP\t\t=\t0,\n\tNORMAL_CHIP\t=\t1,\n\tFPGA\t\t\t=\t2,\n} HAL_CHIP_TYPE_E;\n\n/* HAL_CUT_VERSION_E */\ntypedef enum tag_HAL_Cut_Version_Definition {\n\tA_CUT_VERSION\t\t=\t0,\n\tB_CUT_VERSION\t\t=\t1,\n\tC_CUT_VERSION\t\t=\t2,\n\tD_CUT_VERSION\t\t=\t3,\n\tE_CUT_VERSION\t\t=\t4,\n\tF_CUT_VERSION\t\t=\t5,\n\tG_CUT_VERSION\t\t=\t6,\n\tH_CUT_VERSION\t\t=\t7,\n\tI_CUT_VERSION\t\t=\t8,\n\tJ_CUT_VERSION\t\t=\t9,\n\tK_CUT_VERSION\t\t=\t10,\n} HAL_CUT_VERSION_E;\n\n/* HAL_Manufacturer */\ntypedef enum tag_HAL_Manufacturer_Version_Definition {\n\tCHIP_VENDOR_TSMC\t=\t0,\n\tCHIP_VENDOR_UMC\t=\t1,\n\tCHIP_VENDOR_SMIC\t=\t2,\n} HAL_VENDOR_E;\n\ntypedef enum tag_HAL_RF_Type_Definition {\n\tRF_TYPE_1T1R\t=\t0,\n\tRF_TYPE_1T2R\t=\t1,\n\tRF_TYPE_2T2R\t=\t2,\n\tRF_TYPE_2T3R\t=\t3,\n\tRF_TYPE_2T4R\t=\t4,\n\tRF_TYPE_3T3R\t=\t5,\n\tRF_TYPE_3T4R\t=\t6,\n\tRF_TYPE_4T4R\t=\t7,\n} HAL_RF_TYPE_E;\n\ntypedef\tstruct tag_HAL_VERSION {\n\tHAL_IC_TYPE_E\t\tICType;\n\tHAL_CHIP_TYPE_E\t\tChipType;\n\tHAL_CUT_VERSION_E\tCUTVersion;\n\tHAL_VENDOR_E\t\tVendorType;\n\tHAL_RF_TYPE_E\t\tRFType;\n\tu8\t\t\t\t\tROMVer;\n} HAL_VERSION, *PHAL_VERSION;\n\n/* VERSION_8192C\t\t\tVersionID;\n * HAL_VERSION\t\t\tVersionID; */\n\n/* Get element */\n#define GET_CVID_IC_TYPE(version)\t\t\t((HAL_IC_TYPE_E)(((HAL_VERSION)version).ICType))\n#define GET_CVID_CHIP_TYPE(version)\t\t\t((HAL_CHIP_TYPE_E)(((HAL_VERSION)version).ChipType))\n#define GET_CVID_RF_TYPE(version)\t\t\t((HAL_RF_TYPE_E)(((HAL_VERSION)version).RFType))\n#define GET_CVID_MANUFACTUER(version)\t\t((HAL_VENDOR_E)(((HAL_VERSION)version).VendorType))\n#define GET_CVID_CUT_VERSION(version)\t\t((HAL_CUT_VERSION_E)(((HAL_VERSION)version).CUTVersion))\n#define GET_CVID_ROM_VERSION(version)\t\t((((HAL_VERSION)version).ROMVer) & ROM_VERSION_MASK)\n\n/* ----------------------------------------------------------------------------\n * Common Macro. --\n * ----------------------------------------------------------------------------\n * HAL_VERSION VersionID */\n\n/* HAL_IC_TYPE_E */\n#if 0\n\t#define IS_81XXC(version)\t\t\t\t(((GET_CVID_IC_TYPE(version) == CHIP_8192C) || (GET_CVID_IC_TYPE(version) == CHIP_8188C)) ? TRUE : FALSE)\n\t#define IS_8723_SERIES(version)\t\t\t((GET_CVID_IC_TYPE(version) == CHIP_8723A) ? TRUE : FALSE)\n\t#define IS_92D(version)\t\t\t\t\t((GET_CVID_IC_TYPE(version) == CHIP_8192D) ? TRUE : FALSE)\n#endif\n\n#define IS_8188E(version)\t\t\t\t\t((GET_CVID_IC_TYPE(version) == CHIP_8188E) ? TRUE : FALSE)\n#define IS_8188F(version)\t\t\t\t\t((GET_CVID_IC_TYPE(version) == CHIP_8188F) ? TRUE : FALSE)\n#define IS_8188GTV(version)\t\t\t\t\t((GET_CVID_IC_TYPE(version) == CHIP_8188GTV) ? TRUE : FALSE)\n#define IS_8192E(version)\t\t\t\t\t((GET_CVID_IC_TYPE(version) == CHIP_8192E) ? TRUE : FALSE)\n#define IS_8812_SERIES(version)\t\t\t((GET_CVID_IC_TYPE(version) == CHIP_8812) ? TRUE : FALSE)\n#define IS_8821_SERIES(version)\t\t\t((GET_CVID_IC_TYPE(version) == CHIP_8821) ? TRUE : FALSE)\n#define IS_8814A_SERIES(version)\t\t\t((GET_CVID_IC_TYPE(version) == CHIP_8814A) ? TRUE : FALSE)\n#define IS_8723B_SERIES(version)\t\t\t((GET_CVID_IC_TYPE(version) == CHIP_8723B) ? TRUE : FALSE)\n#define IS_8703B_SERIES(version)\t\t\t((GET_CVID_IC_TYPE(version) == CHIP_8703B) ? TRUE : FALSE)\n#define IS_8822B_SERIES(version)\t\t\t((GET_CVID_IC_TYPE(version) == CHIP_8822B) ? TRUE : FALSE)\n#define IS_8821C_SERIES(version)\t\t\t((GET_CVID_IC_TYPE(version) == CHIP_8821C) ? TRUE : FALSE)\n#define IS_8723D_SERIES(version)\t\t\t((GET_CVID_IC_TYPE(version) == CHIP_8723D) ? TRUE : FALSE)\n#define IS_8710B_SERIES(version)\t\t\t((GET_CVID_IC_TYPE(version) == CHIP_8710B) ? TRUE : FALSE)\n#define IS_8822C_SERIES(version)\t\t\t((GET_CVID_IC_TYPE(version) == CHIP_8822C) ? TRUE : FALSE)\n\n#define IS_8192F_SERIES(version)\\\n\t((GET_CVID_IC_TYPE(version) == CHIP_8192F) ? TRUE : FALSE)\n/* HAL_CHIP_TYPE_E */\n#define IS_TEST_CHIP(version)\t\t\t((GET_CVID_CHIP_TYPE(version) == TEST_CHIP) ? TRUE : FALSE)\n#define IS_NORMAL_CHIP(version)\t\t\t((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE)\n\n/* HAL_CUT_VERSION_E */\n#define IS_A_CUT(version)\t\t\t\t((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? TRUE : FALSE)\n#define IS_B_CUT(version)\t\t\t\t((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? TRUE : FALSE)\n#define IS_C_CUT(version)\t\t\t\t((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? TRUE : FALSE)\n#define IS_D_CUT(version)\t\t\t\t((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? TRUE : FALSE)\n#define IS_E_CUT(version)\t\t\t\t((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE)\n#define IS_F_CUT(version)\t\t\t\t((GET_CVID_CUT_VERSION(version) == F_CUT_VERSION) ? TRUE : FALSE)\n#define IS_I_CUT(version)\t\t\t\t((GET_CVID_CUT_VERSION(version) == I_CUT_VERSION) ? TRUE : FALSE)\n#define IS_J_CUT(version)\t\t\t\t((GET_CVID_CUT_VERSION(version) == J_CUT_VERSION) ? TRUE : FALSE)\n#define IS_K_CUT(version)\t\t\t\t((GET_CVID_CUT_VERSION(version) == K_CUT_VERSION) ? TRUE : FALSE)\n\n/* HAL_VENDOR_E */\n#define IS_CHIP_VENDOR_TSMC(version)\t((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC) ? TRUE : FALSE)\n#define IS_CHIP_VENDOR_UMC(version)\t((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC) ? TRUE : FALSE)\n#define IS_CHIP_VENDOR_SMIC(version)\t((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_SMIC) ? TRUE : FALSE)\n\n/* HAL_RF_TYPE_E */\n#define IS_1T1R(version)\t\t\t\t\t((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R) ? TRUE : FALSE)\n#define IS_1T2R(version)\t\t\t\t\t((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? TRUE : FALSE)\n#define IS_2T2R(version)\t\t\t\t\t((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? TRUE : FALSE)\n#define IS_3T3R(version)\t\t\t\t\t((GET_CVID_RF_TYPE(version) == RF_TYPE_3T3R) ? TRUE : FALSE)\n#define IS_3T4R(version)\t\t\t\t\t((GET_CVID_RF_TYPE(version) == RF_TYPE_3T4R) ? TRUE : FALSE)\n#define IS_4T4R(version)\t\t\t\t\t((GET_CVID_RF_TYPE(version) == RF_TYPE_4T4R) ? TRUE : FALSE)\n\n\n\n/* ----------------------------------------------------------------------------\n * Chip version Macro. --\n * ---------------------------------------------------------------------------- */\n#if 0\n\t#define IS_81XXC_TEST_CHIP(version)\t\t((IS_81XXC(version) && (!IS_NORMAL_CHIP(version))) ? TRUE : FALSE)\n\n\t#define IS_92C_SERIAL(version)\t\t\t\t\t((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE)\n\t#define IS_81xxC_VENDOR_UMC_A_CUT(version)\t(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)\n\t#define IS_81xxC_VENDOR_UMC_B_CUT(version)\t(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)\n\t#define IS_81xxC_VENDOR_UMC_C_CUT(version)\t(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)\n\n\t#define IS_NORMAL_CHIP92D(version)\t\t((IS_92D(version)) ? ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE) : FALSE)\n\n\t#define IS_92D_SINGLEPHY(version)\t\t((IS_92D(version)) ? (IS_2T2R(version) ? TRUE : FALSE) : FALSE)\n\t#define IS_92D_C_CUT(version)\t\t\t((IS_92D(version)) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE)\n\t#define IS_92D_D_CUT(version)\t\t\t((IS_92D(version)) ? (IS_D_CUT(version) ? TRUE : FALSE) : FALSE)\n\t#define IS_92D_E_CUT(version)\t\t\t((IS_92D(version)) ? (IS_E_CUT(version) ? TRUE : FALSE) : FALSE)\n\n\t#define IS_8723A_A_CUT(version)\t\t\t\t((IS_8723_SERIES(version)) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE)\n\t#define IS_8723A_B_CUT(version)\t\t\t\t((IS_8723_SERIES(version)) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE)\n#endif\n#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter)\t\t((IS_8188E(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE)\n#define IS_VENDOR_8812A_TEST_CHIP(_Adapter)\t\t((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)\n#define IS_VENDOR_8812A_MP_CHIP(_Adapter)\t\t((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)\n#define IS_VENDOR_8812A_C_CUT(_Adapter)\t\t\t((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == C_CUT_VERSION) ? TRUE : FALSE) : FALSE)\n\n#define IS_VENDOR_8821A_TEST_CHIP(_Adapter)\t((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)\n#define IS_VENDOR_8821A_MP_CHIP(_Adapter)\t\t((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)\n\n#define IS_VENDOR_8192E_B_CUT(_Adapter)\t\t((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == B_CUT_VERSION) ? TRUE : FALSE)\n\n#define IS_VENDOR_8723B_TEST_CHIP(_Adapter)\t((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)\n#define IS_VENDOR_8723B_MP_CHIP(_Adapter)\t\t((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)\n\n#define IS_VENDOR_8703B_TEST_CHIP(_Adapter)\t((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)\n#define IS_VENDOR_8703B_MP_CHIP(_Adapter)\t\t((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)\n#define IS_VENDOR_8814A_TEST_CHIP(_Adapter)\t((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)\n#define IS_VENDOR_8814A_MP_CHIP(_Adapter)\t\t((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)\n\n#endif\n"
  },
  {
    "path": "include/autoconf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n/***** temporarily flag *******/\n#define CONFIG_SINGLE_IMG\n/* #define CONFIG_DISABLE_ODM */\n\n/***** temporarily flag *******/\n/*\n * Public  General Config\n */\n#define AUTOCONF_INCLUDED\n#define DRV_NAME \"rtl88x2ce\"\n\n#define CONFIG_PCI_HCI\n#define CONFIG_PCIE_HCI\n#define PLATFORM_LINUX\n\n/*\n * Wi-Fi Functions Config\n */\n\n#define CONFIG_RECV_REORDERING_CTRL\n\n#define CONFIG_80211N_HT\n#define CONFIG_80211AC_VHT\n#ifdef CONFIG_80211AC_VHT\n\t#ifndef CONFIG_80211N_HT\n\t\t#define CONFIG_80211N_HT\n\t#endif\n#endif\n\n#define CONFIG_IEEE80211_BAND_5GHZ\n\n/*#define CONFIG_IOCTL_CFG80211*/\n#ifdef CONFIG_IOCTL_CFG80211\n\t/*#define RTW_USE_CFG80211_STA_EVENT*/ /* Indecate new sta asoc through cfg80211_new_sta */\n\t#define CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER\n\t/*#define CONFIG_DEBUG_CFG80211*/\n\t/*#define CONFIG_DRV_ISSUE_PROV_REQ*/ /* IOT FOR S2 */\n\t#define CONFIG_SET_SCAN_DENY_TIMER\n#endif\n#define CONFIG_TX_AMSDU\n\n/*\n * Internal  General Config\n */\n/*#define CONFIG_PWRCTRL*/\n/*#define CONFIG_H2CLBK*/\n#define CONFIG_TRX_BD_ARCH\t/* PCI only */\n#define USING_RX_TAG\n\n#define CONFIG_EMBEDDED_FWIMG\n\n#ifdef CONFIG_EMBEDDED_FWIMG\n\t#define\tLOAD_FW_HEADER_FROM_DRIVER\n#endif\n/*#define CONFIG_FILE_FWIMG*/\n\n#define CONFIG_XMIT_ACK\n#ifdef CONFIG_XMIT_ACK\n\t#define CONFIG_ACTIVE_KEEP_ALIVE_CHECK\n#endif\n\n/*#define CONFIG_DISABLE_MCS13TO15\t1*/\t/* Disable MSC13-15 rates for more stable TX throughput with some 5G APs */\n\n#define BUF_DESC_ARCH\t\t/* if defined, hardware follows Rx buffer descriptor architecture */\n\n#ifdef CONFIG_POWER_SAVING\n\n\t#define CONFIG_IPS\n\t#ifdef CONFIG_IPS\n\t\t/*#define CONFIG_IPS_LEVEL_2*/ /* enable this to set default IPS mode to IPS_LEVEL_2 */\n\t\t/*#define CONFIG_FWLPS_IN_IPS*/\n\t#endif\n\n\t#define CONFIG_LPS\n\n\t#if defined(CONFIG_LPS)\n\t\t/*#define CONFIG_LPS_LCLK*/ /* 32K */\n\t#endif\n\n\t#ifdef CONFIG_LPS_LCLK\n\t\t#define CONFIG_XMIT_THREAD_MODE\n\t\t#define LPS_RPWM_WAIT_MS 300\n\t\t/*#define CONFIG_LPS_PG*/\n\t\t#define DBG_CHECK_FW_PS_STATE\n\t#endif\n\n\t#ifdef CONFIG_LPS\n\t\t#define CONFIG_WMMPS_STA 1\n\t#endif /* CONFIG_LPS */\n\n#endif\n\n/*#define CONFIG_PCI_ASPM*/\n#ifdef CONFIG_PCI_ASPM\n#define CONFIG_PCI_DYNAMIC_ASPM\n#endif\n\n#define CONFIG_HIGH_CHAN_SUPER_CALIBRATION\n/*#define SUPPORT_HW_RFOFF_DETECTED*/\n/*#define CONFIG_ANTENNA_DIVERSITY*/\n\n#define CONFIG_AP_MODE\n#ifdef CONFIG_AP_MODE\n\t/*#define CONFIG_INTERRUPT_BASED_TXBCN*/ /* Tx Beacon when driver BCN_OK ,BCN_ERR interrupt occurs */\n\t#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_INTERRUPT_BASED_TXBCN)\n\t\t#undef CONFIG_INTERRUPT_BASED_TXBCN\n\t#endif\n\t#ifdef CONFIG_INTERRUPT_BASED_TXBCN\n\t\t/*#define CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT*/\n\t\t#define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR\n\t#endif\n\n\t#define CONFIG_NATIVEAP_MLME\n\t#ifndef CONFIG_NATIVEAP_MLME\n\t\t#define CONFIG_HOSTAPD_MLME\n\t#endif\n\t#define CONFIG_FIND_BEST_CHANNEL\n\t/*#define CONFIG_AUTO_AP_MODE*/\n#endif\n\n#define CONFIG_P2P\n#ifdef CONFIG_P2P\n\t/* The CONFIG_WFD is for supporting the Wi-Fi display */\n\t#define CONFIG_WFD\n\n\t#define CONFIG_P2P_REMOVE_GROUP_INFO\n\n\t/*#define CONFIG_DBG_P2P*/\n\n\t#define CONFIG_P2P_PS\n\t/*#define CONFIG_P2P_IPS*/\n\t#define CONFIG_P2P_OP_CHK_SOCIAL_CH\n\t#define CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT  /* replace CONFIG_P2P_CHK_INVITE_CH_LIST flag */\n\t/*#define CONFIG_P2P_INVITE_IOT*/\n#endif\n\n/* Added by Kurt 20110511 */\n#ifdef CONFIG_TDLS\n\t#define CONFIG_TDLS_DRIVER_SETUP\n#if 0\n\t#ifndef CONFIG_WFD\n\t\t#define CONFIG_WFD\n\t#endif\n\t#define CONFIG_TDLS_AUTOSETUP\n#endif\n\t#define CONFIG_TDLS_AUTOCHECKALIVE\n\t#define CONFIG_TDLS_CH_SW\t\t/* Enable \"CONFIG_TDLS_CH_SW\" by default, however limit it to only work in wifi logo test mode but not in normal mode currently */\n#endif\n\n#define CONFIG_SKB_COPY\t/* for amsdu */\n\n/*#define CONFIG_RTW_LED*/\n#ifdef CONFIG_RTW_LED\n\t/*#define CONFIG_RTW_SW_LED*/\n\t#ifdef CONFIG_RTW_SW_LED\n\t\t/*#define CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD*/\n\t#endif\n#endif /* CONFIG_RTW_LED */\n\n#define CONFIG_GLOBAL_UI_PID\n\n/*#define CONFIG_RTW_80211K*/\n\n#define CONFIG_LAYER2_ROAMING\n#define CONFIG_LAYER2_ROAMING_RESUME\n/*#define CONFIG_ADAPTOR_INFO_CACHING_FILE*/ /* now just applied on 8192cu only, should make it general...*/\n/*#define CONFIG_RESUME_IN_WORKQUEUE*/\n/*#define CONFIG_SET_SCAN_DENY_TIMER*/\n#define CONFIG_LONG_DELAY_ISSUE\n#define CONFIG_NEW_SIGNAL_STAT_PROCESS\n/*#define CONFIG_SIGNAL_DISPLAY_DBM*/ /* display RX signal with dbm */\n#ifdef CONFIG_SIGNAL_DISPLAY_DBM\n/*#define CONFIG_BACKGROUND_NOISE_MONITOR*/\n#endif\n\n#define RTW_NOTCH_FILTER 0 /* 0:Disable, 1:Enable, */\n\n#define CONFIG_BEAMFORMING\n\n/*#define CONFIG_SUPPORT_TRX_SHARED*/\n#ifdef CONFIG_SUPPORT_TRX_SHARED\n#define DFT_TRX_SHARE_MODE\t1\n#endif\n\n/*\n * Software feature Related Config\n */\n#define RTW_HALMAC\t\t/* Use HALMAC architecture, necessary for 8822B */\n\n/*\n * Interface  Related Config\n */\n\n/*\n * HAL  Related Config\n */\n\n#define RTL8192E_RX_PACKET_INCLUDE_CRC\t0\n#define CONFIG_RX_PACKET_APPEND_FCS\n#define SUPPORTED_BLOCK_IO\n#define RTL8188E_FW_DOWNLOAD_ENABLE\n\n/*#define CONFIG_ONLY_ONE_OUT_EP_TO_LOW\t0*/\n\n#define CONFIG_OUT_EP_WIFI_MODE\t0\n\n#define ENABLE_USB_DROP_INCORRECT_OUT\n\n\n#define DISABLE_BB_RF\t0\n\n/*#define RTL8191C_FPGA_NETWORKTYPE_ADHOC 0*/\n\n#ifdef CONFIG_MP_INCLUDED\n\t#define MP_DRIVER 1\n\t#define CONFIG_MP_IWPRIV_SUPPORT\t1\n#else\n\t#define MP_DRIVER 0\n#endif\n\n/* Use cmd frame to issue beacon. Use a fixed buffer for beacon. */\n#define CONFIG_BCN_ICF\n\n/*\n * Platform  Related Config\n */\n\n\n#ifdef CONFIG_BT_COEXIST\n\t/* for ODM and outsrc BT-Coex */\n\t#ifndef CONFIG_LPS\n\t\t#define CONFIG_LPS\t/* download reserved page to FW */\n\t#endif\n\t/* Enable ZigBee coexist */\n\t/* #define CONFIG_RF4CE_COEXIST */\n\n#endif /* !CONFIG_BT_COEXIST */\n\n\n#ifdef CONFIG_USB_TX_AGGREGATION\n/*#define CONFIG_TX_EARLY_MODE*/\n#endif\n\n#ifdef CONFIG_TX_EARLY_MODE\n#define\tRTL8192E_EARLY_MODE_PKT_NUM_10\t0\n#endif\n\n/* Try to handle the Beacon error found in some types of TP-LINK APs */\n#define CONFIG_ATTEMPT_TO_FIX_AP_BEACON_ERROR\n\n/*\n * Debug Related Config\n */\n#define DBG\t1\n\n#define CONFIG_PROC_DEBUG\n\n#define CONFIG_DBG_COUNTER\n\n#define DBG_CONFIG_ERROR_DETECT\n/*\n#define DBG_CONFIG_ERROR_DETECT_INT\n#define DBG_CONFIG_ERROR_RESET\n\n#define DBG_IO\n#define DBG_DELAY_OS\n#define DBG_MEM_ALLOC\n#define DBG_IOCTL\n\n#define DBG_TX\n#define DBG_XMIT_BUF\n#define DBG_XMIT_BUF_EXT\n#define DBG_TX_DROP_FRAME\n\n#define DBG_RX_DROP_FRAME\n#define DBG_RX_SEQ\n#define DBG_RX_SIGNAL_DISPLAY_PROCESSING\n#define DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED \"jeff-ap\"\n*/\n#define DBG_RX_SIGNAL_DISPLAY_RAW_DATA\n#if 0\n#define DBG_NOISE_MONITOR\n\n#define DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE\n#define DBG_ROAMING_TEST\n\n#define DBG_HAL_INIT_PROFILING\n\n#define DBG_MEMORY_LEAK\t1\n\n/* TX use 1 urb */\n#define CONFIG_SINGLE_XMIT_BUF\n/* RX use 1 urb */\n#define CONFIG_SINGLE_RECV_BUF\n#endif\n\n#define\tDBG_TXBD_DESC_DUMP\n\n\n/* #define CONFIG_RTW_8822C_BETA_DEV */\n#ifdef CONFIG_RTW_8822C_BETA_DEV\n/* #define CONFIG_NO_FW */\n/* #define CONFIG_DISABLE_ODM */\n/* #define CONFIG_DEFAULT_PWR_BY_RATE_TABLE */\n#endif\n\n#define CONFIG_8822CE_INT_MIGRATION\n\n#define CONFIG_PCI_BCN_POLLING\n\n/*#define CONFIG_PCI_TX_POLLING*/\n/*#define CONFIG_PCI_TX_POLLING_V2*/\n"
  },
  {
    "path": "include/basic_types.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __BASIC_TYPES_H__\n#define __BASIC_TYPES_H__\n\n\n#define SUCCESS\t0\n#define FAIL\t(-1)\n\n#ifndef TRUE\n\t#define _TRUE\t1\n#else\n\t#define _TRUE\tTRUE\n#endif\n\n#ifndef FALSE\n\t#define _FALSE\t0\n#else\n\t#define _FALSE\tFALSE\n#endif\n\n#ifdef PLATFORM_WINDOWS\n\n\ttypedef signed char s8;\n\ttypedef unsigned char u8;\n\n\ttypedef signed short s16;\n\ttypedef unsigned short u16;\n\n\ttypedef signed long s32;\n\ttypedef unsigned long u32;\n\n\ttypedef unsigned int\tuint;\n\ttypedef\tsigned int\t\tsint;\n\n\n\ttypedef signed long long s64;\n\ttypedef unsigned long long u64;\n\n\t#ifdef NDIS50_MINIPORT\n\n\t\t#define NDIS_MAJOR_VERSION       5\n\t\t#define NDIS_MINOR_VERSION       0\n\n\t#endif\n\n\t#ifdef NDIS51_MINIPORT\n\n\t\t#define NDIS_MAJOR_VERSION       5\n\t\t#define NDIS_MINOR_VERSION       1\n\n\t#endif\n\n\ttypedef NDIS_PROC proc_t;\n\n\ttypedef LONG atomic_t;\n\n#endif\n\n\n#ifdef PLATFORM_LINUX\n\t#include <linux/version.h>\n\t#include <linux/types.h>\n\t#include <linux/module.h>\n\t#include <linux/kernel.h>\n\t#include <linux/init.h>\n\t#include <linux/utsname.h>\n\n\ttypedef\tsigned int sint;\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19))\ntypedef _Bool bool;\n\nenum {\n\tfalse\t= 0,\n\ttrue\t= 1\n};\n#endif\n\n\ttypedef void (*proc_t)(void *);\n\n\ttypedef\t__kernel_size_t\tSIZE_T;\n\ttypedef\t__kernel_ssize_t\tSSIZE_T;\n\t#define FIELD_OFFSET(s, field)\t((SSIZE_T)&((s *)(0))->field)\n\n#define NDIS_OID uint\n#endif /*PLATFORM_LINUX*/\n\n\n#ifdef PLATFORM_FREEBSD\n\n\ttypedef signed char s8;\n\ttypedef unsigned char u8;\n\n\ttypedef signed short s16;\n\ttypedef unsigned short u16;\n\n\ttypedef signed int s32;\n\ttypedef unsigned int u32;\n\n\ttypedef unsigned int\tuint;\n\ttypedef\tsigned int\t\tsint;\n\ttypedef long atomic_t;\n\n\ttypedef signed long long s64;\n\ttypedef unsigned long long u64;\n\n\ttypedef u32 dma_addr_t;\n\n\ttypedef void (*proc_t)(void *);\n\n\ttypedef unsigned int __kernel_size_t;\n\ttypedef int __kernel_ssize_t;\n\n\ttypedef\t__kernel_size_t\tSIZE_T;\n\ttypedef\t__kernel_ssize_t\tSSIZE_T;\n\t#define FIELD_OFFSET(s, field)\t((SSIZE_T)&((s *)(0))->field)\n\n#endif\n\n#define MEM_ALIGNMENT_OFFSET\t(sizeof (SIZE_T))\n#define MEM_ALIGNMENT_PADDING\t(sizeof(SIZE_T) - 1)\n\n#define SIZE_PTR SIZE_T\n#define SSIZE_PTR SSIZE_T\n\n/*\n* Continuous bits starting from least significant bit\n* Example:\n* BIT_LEN_MASK_32(0) => 0x00000000\n* BIT_LEN_MASK_32(1) => 0x00000001\n* BIT_LEN_MASK_32(2) => 0x00000003\n* BIT_LEN_MASK_32(32) => 0xFFFFFFFF\n*/\n#define BIT_LEN_MASK_32(__BitLen) ((u32)(0xFFFFFFFF >> (32 - (__BitLen))))\n#define BIT_LEN_MASK_16(__BitLen) ((u16)(0xFFFF >> (16 - (__BitLen))))\n#define BIT_LEN_MASK_8(__BitLen) ((u8)(0xFF >> (8 - (__BitLen))))\n\n/*\n* Continuous bits starting from least significant bit\n* Example:\n* BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003\n* BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000\n*/\n#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ((u32)(BIT_LEN_MASK_32(__BitLen) << (__BitOffset)))\n#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ((u16)(BIT_LEN_MASK_16(__BitLen) << (__BitOffset)))\n#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ((u8)(BIT_LEN_MASK_8(__BitLen) << (__BitOffset)))\n\n/*\n* Convert LE data to host byte order\n*/\n#define EF1Byte (u8)\n#define EF2Byte le16_to_cpu\n#define EF4Byte le32_to_cpu\n\n/*\n* Read LE data from memory to host byte order\n*/\n#define ReadLE4Byte(_ptr)\tle32_to_cpu(*((u32 *)(_ptr)))\n#define ReadLE2Byte(_ptr)\tle16_to_cpu(*((u16 *)(_ptr)))\n#define ReadLE1Byte(_ptr)\t(*((u8 *)(_ptr)))\n\n/*\n* Read BE data from memory to host byte order\n*/\n#define ReadBEE4Byte(_ptr)\tbe32_to_cpu(*((u32 *)(_ptr)))\n#define ReadBE2Byte(_ptr)\tbe16_to_cpu(*((u16 *)(_ptr)))\n#define ReadBE1Byte(_ptr)\t(*((u8 *)(_ptr)))\n\n/*\n* Write host byte order data to memory in LE order\n*/\n#define WriteLE4Byte(_ptr, _val)\t((*((u32 *)(_ptr))) = cpu_to_le32(_val))\n#define WriteLE2Byte(_ptr, _val)\t((*((u16 *)(_ptr))) = cpu_to_le16(_val))\n#define WriteLE1Byte(_ptr, _val)\t((*((u8 *)(_ptr))) = ((u8)(_val)))\n\n/*\n* Write host byte order data to memory in BE order\n*/\n#define WriteBE4Byte(_ptr, _val)\t((*((u32 *)(_ptr))) = cpu_to_be32(_val))\n#define WriteBE2Byte(_ptr, _val)\t((*((u16 *)(_ptr))) = cpu_to_be16(_val))\n#define WriteBE1Byte(_ptr, _val)\t((*((u8 *)(_ptr))) = ((u8)(_val)))\n\n/*\n* Return 4-byte value in host byte ordering from 4-byte pointer in litten-endian system.\n*/\n#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) (le32_to_cpu(*((u32 *)(__pStart))))\n#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) (le16_to_cpu(*((u16 *)(__pStart))))\n#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) ((*((u8 *)(__pStart))))\n\n/*\n* Return 4-byte value in host byte ordering from 4-byte pointer in big-endian system.\n*/\n#define BE_P4BYTE_TO_HOST_4BYTE(__pStart) (be32_to_cpu(*((u32 *)(__pStart))))\n#define BE_P2BYTE_TO_HOST_2BYTE(__pStart) (be16_to_cpu(*((u16 *)(__pStart))))\n#define BE_P1BYTE_TO_HOST_1BYTE(__pStart) ((*((u8 *)(__pStart))))\n\n/*\n* Translate subfield (continuous bits in little-endian) of 4-byte value in LE byte to\n* 4-byte value in host byte ordering.\n*/\n#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \\\n\t((LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_32(__BitLen))\n\n#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \\\n\t((LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_16(__BitLen))\n\n#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \\\n\t((LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_8(__BitLen))\n\n/*\n* Translate subfield (continuous bits in big-endian) of 4-byte value in BE byte to\n* 4-byte value in host byte ordering.\n*/\n#define BE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \\\n\t((BE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_32(__BitLen))\n\n#define BE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \\\n\t((BE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_16(__BitLen))\n\n#define BE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \\\n\t((BE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_8(__BitLen))\n\n/*\n* Mask subfield (continuous bits in little-endian) of 4-byte value in LE byte oredering\n* and return the result in 4-byte value in host byte ordering.\n*/\n#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \\\n\t(LE_P4BYTE_TO_HOST_4BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)))\n\n#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \\\n\t(LE_P2BYTE_TO_HOST_2BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen)))\n\n#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \\\n\t(LE_P1BYTE_TO_HOST_1BYTE(__pStart) & ((u8)(~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen))))\n\n/*\n* Mask subfield (continuous bits in big-endian) of 4-byte value in BE byte oredering\n* and return the result in 4-byte value in host byte ordering.\n*/\n#define BE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \\\n\t(BE_P4BYTE_TO_HOST_4BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)))\n\n#define BE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \\\n\t(BE_P2BYTE_TO_HOST_2BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen)))\n\n#define BE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \\\n\t(BE_P1BYTE_TO_HOST_1BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen)))\n\n/*\n* Set subfield of little-endian 4-byte value to specified value.\n*/\n#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \\\n\tdo { \\\n\t\tif (__BitOffset == 0 && __BitLen == 32) \\\n\t\t\tWriteLE4Byte(__pStart, __Value); \\\n\t\telse { \\\n\t\t\tWriteLE4Byte(__pStart, \\\n\t\t\t\tLE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \\\n\t\t\t\t| \\\n\t\t\t\t((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \\\n\t\t\t); \\\n\t\t} \\\n\t} while (0)\n\n#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \\\n\tdo { \\\n\t\tif (__BitOffset == 0 && __BitLen == 16) \\\n\t\t\tWriteLE2Byte(__pStart, __Value); \\\n\t\telse { \\\n\t\t\tWriteLE2Byte(__pStart, \\\n\t\t\t\tLE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \\\n\t\t\t\t| \\\n\t\t\t\t((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \\\n\t\t\t); \\\n\t\t} \\\n\t} while (0)\n\n#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \\\n\tdo { \\\n\t\tif (__BitOffset == 0 && __BitLen == 8) \\\n\t\t\tWriteLE1Byte(__pStart, __Value); \\\n\t\telse { \\\n\t\t\tWriteLE1Byte(__pStart, \\\n\t\t\t\tLE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \\\n\t\t\t\t| \\\n\t\t\t\t((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \\\n\t\t\t); \\\n\t\t} \\\n\t} while (0)\n\n/*\n* Set subfield of big-endian 4-byte value to specified value.\n*/\n#define SET_BITS_TO_BE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \\\n\tdo { \\\n\t\tif (__BitOffset == 0 && __BitLen == 32) \\\n\t\t\tWriteBE4Byte(__pStart, __Value); \\\n\t\telse { \\\n\t\t\tWriteBE4Byte(__pStart, \\\n\t\t\t\tBE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \\\n\t\t\t\t| \\\n\t\t\t\t((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \\\n\t\t\t); \\\n\t\t} \\\n\t} while (0)\n\n#define SET_BITS_TO_BE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \\\n\tdo { \\\n\t\tif (__BitOffset == 0 && __BitLen == 16) \\\n\t\t\tWriteBE2Byte(__pStart, __Value); \\\n\t\telse { \\\n\t\t\tWriteBE2Byte(__pStart, \\\n\t\t\t\tBE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \\\n\t\t\t\t| \\\n\t\t\t\t((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \\\n\t\t\t); \\\n\t\t} \\\n\t} while (0)\n\n#define SET_BITS_TO_BE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \\\n\tdo { \\\n\t\tif (__BitOffset == 0 && __BitLen == 8) \\\n\t\t\tWriteBE1Byte(__pStart, __Value); \\\n\t\telse { \\\n\t\t\tWriteBE1Byte(__pStart, \\\n\t\t\t\tBE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \\\n\t\t\t\t| \\\n\t\t\t\t((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \\\n\t\t\t); \\\n\t\t} \\\n\t} while (0)\n\n/* Get the N-bytes aligment offset from the current length */\n#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment))\n\ntypedef unsigned char\tBOOLEAN, *PBOOLEAN, boolean;\n\n#define TEST_FLAG(__Flag, __testFlag)\t\t(((__Flag) & (__testFlag)) != 0)\n#define SET_FLAG(__Flag, __setFlag)\t\t\t((__Flag) |= __setFlag)\n#define CLEAR_FLAG(__Flag, __clearFlag)\t\t((__Flag) &= ~(__clearFlag))\n#define CLEAR_FLAGS(__Flag)\t\t\t\t\t((__Flag) = 0)\n#define TEST_FLAGS(__Flag, __testFlags)\t\t(((__Flag) & (__testFlags)) == (__testFlags))\n\n#endif /* __BASIC_TYPES_H__ */\n"
  },
  {
    "path": "include/byteorder/big_endian.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H\n#define _LINUX_BYTEORDER_BIG_ENDIAN_H\n\n#ifndef __BIG_ENDIAN\n\t#define __BIG_ENDIAN 4321\n#endif\n#ifndef __BIG_ENDIAN_BITFIELD\n\t#define __BIG_ENDIAN_BITFIELD\n#endif\n\n#include <byteorder/swab.h>\n\n#define __constant_htonl(x) ((__u32)(x))\n#define __constant_ntohl(x) ((__u32)(x))\n#define __constant_htons(x) ((__u16)(x))\n#define __constant_ntohs(x) ((__u16)(x))\n#define __constant_cpu_to_le64(x) ___constant_swab64((x))\n#define __constant_le64_to_cpu(x) ___constant_swab64((x))\n#define __constant_cpu_to_le32(x) ___constant_swab32((x))\n#define __constant_le32_to_cpu(x) ___constant_swab32((x))\n#define __constant_cpu_to_le16(x) ___constant_swab16((x))\n#define __constant_le16_to_cpu(x) ___constant_swab16((x))\n#define __constant_cpu_to_be64(x) ((__u64)(x))\n#define __constant_be64_to_cpu(x) ((__u64)(x))\n#define __constant_cpu_to_be32(x) ((__u32)(x))\n#define __constant_be32_to_cpu(x) ((__u32)(x))\n#define __constant_cpu_to_be16(x) ((__u16)(x))\n#define __constant_be16_to_cpu(x) ((__u16)(x))\n#define __cpu_to_le64(x) __swab64((x))\n#define __le64_to_cpu(x) __swab64((x))\n#define __cpu_to_le32(x) __swab32((x))\n#define __le32_to_cpu(x) __swab32((x))\n#define __cpu_to_le16(x) __swab16((x))\n#define __le16_to_cpu(x) __swab16((x))\n#define __cpu_to_be64(x) ((__u64)(x))\n#define __be64_to_cpu(x) ((__u64)(x))\n#define __cpu_to_be32(x) ((__u32)(x))\n#define __be32_to_cpu(x) ((__u32)(x))\n#define __cpu_to_be16(x) ((__u16)(x))\n#define __be16_to_cpu(x) ((__u16)(x))\n#define __cpu_to_le64p(x) __swab64p((x))\n#define __le64_to_cpup(x) __swab64p((x))\n#define __cpu_to_le32p(x) __swab32p((x))\n#define __le32_to_cpup(x) __swab32p((x))\n#define __cpu_to_le16p(x) __swab16p((x))\n#define __le16_to_cpup(x) __swab16p((x))\n#define __cpu_to_be64p(x) (*(__u64 *)(x))\n#define __be64_to_cpup(x) (*(__u64 *)(x))\n#define __cpu_to_be32p(x) (*(__u32 *)(x))\n#define __be32_to_cpup(x) (*(__u32 *)(x))\n#define __cpu_to_be16p(x) (*(__u16 *)(x))\n#define __be16_to_cpup(x) (*(__u16 *)(x))\n#define __cpu_to_le64s(x) __swab64s((x))\n#define __le64_to_cpus(x) __swab64s((x))\n#define __cpu_to_le32s(x) __swab32s((x))\n#define __le32_to_cpus(x) __swab32s((x))\n#define __cpu_to_le16s(x) __swab16s((x))\n#define __le16_to_cpus(x) __swab16s((x))\n#define __cpu_to_be64s(x) do {} while (0)\n#define __be64_to_cpus(x) do {} while (0)\n#define __cpu_to_be32s(x) do {} while (0)\n#define __be32_to_cpus(x) do {} while (0)\n#define __cpu_to_be16s(x) do {} while (0)\n#define __be16_to_cpus(x) do {} while (0)\n\n#include <byteorder/generic.h>\n\n#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */\n"
  },
  {
    "path": "include/byteorder/generic.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _LINUX_BYTEORDER_GENERIC_H\n#define _LINUX_BYTEORDER_GENERIC_H\n\n/*\n * linux/byteorder_generic.h\n * Generic Byte-reordering support\n *\n * Francois-Rene Rideau <fare@tunes.org> 19970707\n *    gathered all the good ideas from all asm-foo/byteorder.h into one file,\n *    cleaned them up.\n *    I hope it is compliant with non-GCC compilers.\n *    I decided to put __BYTEORDER_HAS_U64__ in byteorder.h,\n *    because I wasn't sure it would be ok to put it in types.h\n *    Upgraded it to 2.1.43\n * Francois-Rene Rideau <fare@tunes.org> 19971012\n *    Upgraded it to 2.1.57\n *    to please Linus T., replaced huge #ifdef's between little/big endian\n *    by nestedly #include'd files.\n * Francois-Rene Rideau <fare@tunes.org> 19971205\n *    Made it to 2.1.71; now a facelift:\n *    Put files under include/linux/byteorder/\n *    Split swab from generic support.\n *\n * TODO:\n *   = Regular kernel maintainers could also replace all these manual\n *    byteswap macros that remain, disseminated among drivers,\n *    after some grep or the sources...\n *   = Linus might want to rename all these macros and files to fit his taste,\n *    to fit his personal naming scheme.\n *   = it seems that a few drivers would also appreciate\n *    nybble swapping support...\n *   = every architecture could add their byteswap macro in asm/byteorder.h\n *    see how some architectures already do (i386, alpha, ppc, etc)\n *   = cpu_to_beXX and beXX_to_cpu might some day need to be well\n *    distinguished throughout the kernel. This is not the case currently,\n *    since little endian, big endian, and pdp endian machines needn't it.\n *    But this might be the case for, say, a port of Linux to 20/21 bit\n *    architectures (and F21 Linux addict around?).\n */\n\n/*\n * The following macros are to be defined by <asm/byteorder.h>:\n *\n * Conversion of long and short int between network and host format\n *\tntohl(__u32 x)\n *\tntohs(__u16 x)\n *\thtonl(__u32 x)\n *\thtons(__u16 x)\n * It seems that some programs (which? where? or perhaps a standard? POSIX?)\n * might like the above to be functions, not macros (why?).\n * if that's true, then detect them, and take measures.\n * Anyway, the measure is: define only ___ntohl as a macro instead,\n * and in a separate file, have\n * unsigned long inline ntohl(x){return ___ntohl(x);}\n *\n * The same for constant arguments\n *\t__constant_ntohl(__u32 x)\n *\t__constant_ntohs(__u16 x)\n *\t__constant_htonl(__u32 x)\n *\t__constant_htons(__u16 x)\n *\n * Conversion of XX-bit integers (16- 32- or 64-)\n * between native CPU format and little/big endian format\n * 64-bit stuff only defined for proper architectures\n *\tcpu_to_[bl]eXX(__uXX x)\n *\t[bl]eXX_to_cpu(__uXX x)\n *\n * The same, but takes a pointer to the value to convert\n *\tcpu_to_[bl]eXXp(__uXX x)\n *\t[bl]eXX_to_cpup(__uXX x)\n *\n * The same, but change in situ\n *\tcpu_to_[bl]eXXs(__uXX x)\n *\t[bl]eXX_to_cpus(__uXX x)\n *\n * See asm-foo/byteorder.h for examples of how to provide\n * architecture-optimized versions\n *\n */\n\n\n#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS) || defined(PLATFORM_MPIXEL) || defined(PLATFORM_FREEBSD)\n\t/*\n\t* inside the kernel, we can use nicknames;\n\t* outside of it, we must avoid POSIX namespace pollution...\n\t*/\n\t#define cpu_to_le64 __cpu_to_le64\n\t#define le64_to_cpu __le64_to_cpu\n\t#define cpu_to_le32 __cpu_to_le32\n\t#define le32_to_cpu __le32_to_cpu\n\t#define cpu_to_le16 __cpu_to_le16\n\t#define le16_to_cpu __le16_to_cpu\n\t#define cpu_to_be64 __cpu_to_be64\n\t#define be64_to_cpu __be64_to_cpu\n\t#define cpu_to_be32 __cpu_to_be32\n\t#define be32_to_cpu __be32_to_cpu\n\t#define cpu_to_be16 __cpu_to_be16\n\t#define be16_to_cpu __be16_to_cpu\n\t#define cpu_to_le64p __cpu_to_le64p\n\t#define le64_to_cpup __le64_to_cpup\n\t#define cpu_to_le32p __cpu_to_le32p\n\t#define le32_to_cpup __le32_to_cpup\n\t#define cpu_to_le16p __cpu_to_le16p\n\t#define le16_to_cpup __le16_to_cpup\n\t#define cpu_to_be64p __cpu_to_be64p\n\t#define be64_to_cpup __be64_to_cpup\n\t#define cpu_to_be32p __cpu_to_be32p\n\t#define be32_to_cpup __be32_to_cpup\n\t#define cpu_to_be16p __cpu_to_be16p\n\t#define be16_to_cpup __be16_to_cpup\n\t#define cpu_to_le64s __cpu_to_le64s\n\t#define le64_to_cpus __le64_to_cpus\n\t#define cpu_to_le32s __cpu_to_le32s\n\t#define le32_to_cpus __le32_to_cpus\n\t#define cpu_to_le16s __cpu_to_le16s\n\t#define le16_to_cpus __le16_to_cpus\n\t#define cpu_to_be64s __cpu_to_be64s\n\t#define be64_to_cpus __be64_to_cpus\n\t#define cpu_to_be32s __cpu_to_be32s\n\t#define be32_to_cpus __be32_to_cpus\n\t#define cpu_to_be16s __cpu_to_be16s\n\t#define be16_to_cpus __be16_to_cpus\n#endif\n\n\n/*\n * Handle ntohl and suches. These have various compatibility\n * issues - like we want to give the prototype even though we\n * also have a macro for them in case some strange program\n * wants to take the address of the thing or something..\n *\n * Note that these used to return a \"long\" in libc5, even though\n * long is often 64-bit these days.. Thus the casts.\n *\n * They have to be macros in order to do the constant folding\n * correctly - if the argument passed into a inline function\n * it is no longer constant according to gcc..\n */\n\n#undef ntohl\n#undef ntohs\n#undef htonl\n#undef htons\n\n/*\n * Do the prototypes. Somebody might want to take the\n * address or some such sick thing..\n */\n#if defined(PLATFORM_LINUX) || (defined(__GLIBC__) && __GLIBC__ >= 2)\n\textern __u32\t\t\tntohl(__u32);\n\textern __u32\t\t\thtonl(__u32);\n#else /* defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2) */\n\t#ifndef PLATFORM_FREEBSD\n\t\textern unsigned long int\tntohl(unsigned long int);\n\t\textern unsigned long int\thtonl(unsigned long int);\n\t#endif\n#endif\n#ifndef PLATFORM_FREEBSD\n\textern unsigned short int\tntohs(unsigned short int);\n\textern unsigned short int\thtons(unsigned short int);\n#endif\n\n#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) || defined(PLATFORM_MPIXEL)\n\n\t#define ___htonl(x) __cpu_to_be32(x)\n\t#define ___htons(x) __cpu_to_be16(x)\n\t#define ___ntohl(x) __be32_to_cpu(x)\n\t#define ___ntohs(x) __be16_to_cpu(x)\n\n\t#if defined(PLATFORM_LINUX) || (defined(__GLIBC__) && __GLIBC__ >= 2)\n\t\t#define htonl(x) ___htonl(x)\n\t\t#define ntohl(x) ___ntohl(x)\n\t#else\n\t\t#define htonl(x) ((unsigned long)___htonl(x))\n\t\t#define ntohl(x) ((unsigned long)___ntohl(x))\n\t#endif\n\t#define htons(x) ___htons(x)\n\t#define ntohs(x) ___ntohs(x)\n\n#endif /* OPTIMIZE */\n\n\n#if defined(PLATFORM_WINDOWS)\n\n\t#define htonl(x) __cpu_to_be32(x)\n\t#define ntohl(x) __be32_to_cpu(x)\n\t#define htons(x) __cpu_to_be16(x)\n\t#define ntohs(x) __be16_to_cpu(x)\n\n\n#endif\n\n#endif /* _LINUX_BYTEORDER_GENERIC_H */\n"
  },
  {
    "path": "include/byteorder/little_endian.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H\n#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H\n\n#ifndef __LITTLE_ENDIAN\n\t#define __LITTLE_ENDIAN 1234\n#endif\n#ifndef __LITTLE_ENDIAN_BITFIELD\n\t#define __LITTLE_ENDIAN_BITFIELD\n#endif\n\n#include <byteorder/swab.h>\n\n#ifndef __constant_htonl\n\t#define __constant_htonl(x) ___constant_swab32((x))\n\t#define __constant_ntohl(x) ___constant_swab32((x))\n\t#define __constant_htons(x) ___constant_swab16((x))\n\t#define __constant_ntohs(x) ___constant_swab16((x))\n\t#define __constant_cpu_to_le64(x) ((__u64)(x))\n\t#define __constant_le64_to_cpu(x) ((__u64)(x))\n\t#define __constant_cpu_to_le32(x) ((__u32)(x))\n\t#define __constant_le32_to_cpu(x) ((__u32)(x))\n\t#define __constant_cpu_to_le16(x) ((__u16)(x))\n\t#define __constant_le16_to_cpu(x) ((__u16)(x))\n\t#define __constant_cpu_to_be64(x) ___constant_swab64((x))\n\t#define __constant_be64_to_cpu(x) ___constant_swab64((x))\n\t#define __constant_cpu_to_be32(x) ___constant_swab32((x))\n\t#define __constant_be32_to_cpu(x) ___constant_swab32((x))\n\t#define __constant_cpu_to_be16(x) ___constant_swab16((x))\n\t#define __constant_be16_to_cpu(x) ___constant_swab16((x))\n\t#define __cpu_to_le64(x) ((__u64)(x))\n\t#define __le64_to_cpu(x) ((__u64)(x))\n\t#define __cpu_to_le32(x) ((__u32)(x))\n\t#define __le32_to_cpu(x) ((__u32)(x))\n\t#define __cpu_to_le16(x) ((__u16)(x))\n\t#define __le16_to_cpu(x) ((__u16)(x))\n\t#define __cpu_to_be64(x) __swab64((x))\n\t#define __be64_to_cpu(x) __swab64((x))\n\t#define __cpu_to_be32(x) __swab32((x))\n\t#define __be32_to_cpu(x) __swab32((x))\n\t#define __cpu_to_be16(x) __swab16((x))\n\t#define __be16_to_cpu(x) __swab16((x))\n\t#define __cpu_to_le64p(x) (*(__u64 *)(x))\n\t#define __le64_to_cpup(x) (*(__u64 *)(x))\n\t#define __cpu_to_le32p(x) (*(__u32 *)(x))\n\t#define __le32_to_cpup(x) (*(__u32 *)(x))\n\t#define __cpu_to_le16p(x) (*(__u16 *)(x))\n\t#define __le16_to_cpup(x) (*(__u16 *)(x))\n\t#define __cpu_to_be64p(x) __swab64p((x))\n\t#define __be64_to_cpup(x) __swab64p((x))\n\t#define __cpu_to_be32p(x) __swab32p((x))\n\t#define __be32_to_cpup(x) __swab32p((x))\n\t#define __cpu_to_be16p(x) __swab16p((x))\n\t#define __be16_to_cpup(x) __swab16p((x))\n\t#define __cpu_to_le64s(x) do {} while (0)\n\t#define __le64_to_cpus(x) do {} while (0)\n\t#define __cpu_to_le32s(x) do {} while (0)\n\t#define __le32_to_cpus(x) do {} while (0)\n\t#define __cpu_to_le16s(x) do {} while (0)\n\t#define __le16_to_cpus(x) do {} while (0)\n\t#define __cpu_to_be64s(x) __swab64s((x))\n\t#define __be64_to_cpus(x) __swab64s((x))\n\t#define __cpu_to_be32s(x) __swab32s((x))\n\t#define __be32_to_cpus(x) __swab32s((x))\n\t#define __cpu_to_be16s(x) __swab16s((x))\n\t#define __be16_to_cpus(x) __swab16s((x))\n#endif /* __constant_htonl */\n\n#include <byteorder/generic.h>\n\n#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */\n"
  },
  {
    "path": "include/byteorder/swab.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _LINUX_BYTEORDER_SWAB_H\n#define _LINUX_BYTEORDER_SWAB_H\n\n#if !defined(CONFIG_PLATFORM_MSTAR)\n#ifndef __u16\n\ttypedef unsigned short __u16;\n#endif\n\n#ifndef __u32\n\ttypedef unsigned int\t__u32;\n#endif\n\n#ifndef __u8\n\ttypedef unsigned char __u8;\n#endif\n\n#ifndef __u64\n\ttypedef unsigned long long\t__u64;\n#endif\n\n\n__inline static __u16  ___swab16(__u16 x)\n{\n\t__u16 __x = x;\n\treturn\n\t\t (__u16)(\n\t\t\t (((__u16)(__x)&(__u16)0x00ffU) << 8) |\n\t\t\t (((__u16)(__x)&(__u16)0xff00U) >> 8));\n\n}\n\n__inline static __u32  ___swab32(__u32 x)\n{\n\t__u32 __x = (x);\n\treturn  (__u32)(\n\t\t\t(((__u32)(__x)&(__u32)0x000000ffUL) << 24) |\n\t\t\t(((__u32)(__x)&(__u32)0x0000ff00UL) <<  8) |\n\t\t\t(((__u32)(__x)&(__u32)0x00ff0000UL) >>  8) |\n\t\t\t(((__u32)(__x)&(__u32)0xff000000UL) >> 24));\n}\n\n__inline static __u64  ___swab64(__u64 x)\n{\n\t__u64 __x = (x);\n\n\treturn\n\t\t (__u64)(\\\n\t\t (__u64)(((__u64)(__x)&(__u64)0x00000000000000ffULL) << 56) | \\\n\t\t (__u64)(((__u64)(__x)&(__u64)0x000000000000ff00ULL) << 40) | \\\n\t\t (__u64)(((__u64)(__x)&(__u64)0x0000000000ff0000ULL) << 24) | \\\n\t\t (__u64)(((__u64)(__x)&(__u64)0x00000000ff000000ULL) <<  8) | \\\n\t\t (__u64)(((__u64)(__x)&(__u64)0x000000ff00000000ULL) >>  8) | \\\n\t\t (__u64)(((__u64)(__x)&(__u64)0x0000ff0000000000ULL) >> 24) | \\\n\t\t (__u64)(((__u64)(__x)&(__u64)0x00ff000000000000ULL) >> 40) | \\\n\t\t (__u64)(((__u64)(__x)&(__u64)0xff00000000000000ULL) >> 56));\n\t\\\n}\n#endif /* CONFIG_PLATFORM_MSTAR */\n\n#ifndef __arch__swab16\n__inline static __u16 __arch__swab16(__u16 x)\n{\n\treturn ___swab16(x);\n}\n\n#endif\n\n#ifndef __arch__swab32\n__inline static __u32 __arch__swab32(__u32 x)\n{\n\t__u32 __tmp = (x) ;\n\treturn ___swab32(__tmp);\n}\n#endif\n\n#ifndef __arch__swab64\n\n__inline static __u64 __arch__swab64(__u64 x)\n{\n\t__u64 __tmp = (x) ;\n\treturn ___swab64(__tmp);\n}\n\n\n#endif\n\n#ifndef __swab16\n\t#define __swab16(x) __fswab16(x)\n\t#define __swab32(x) __fswab32(x)\n\t#define __swab64(x) __fswab64(x)\n#endif /* __swab16 */\n\n#ifdef PLATFORM_FREEBSD\n\t__inline static __u16 __fswab16(__u16 x)\n#else\n\t__inline static const __u16 __fswab16(__u16 x)\n#endif /* PLATFORM_FREEBSD */\n{\n\treturn __arch__swab16(x);\n}\n#ifdef PLATFORM_FREEBSD\n\t__inline static __u32 __fswab32(__u32 x)\n#else\n\t__inline static const __u32 __fswab32(__u32 x)\n#endif /* PLATFORM_FREEBSD */\n{\n\treturn __arch__swab32(x);\n}\n\n#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS)\n\t#define swab16 __swab16\n\t#define swab32 __swab32\n\t#define swab64 __swab64\n\t#define swab16p __swab16p\n\t#define swab32p __swab32p\n\t#define swab64p __swab64p\n\t#define swab16s __swab16s\n\t#define swab32s __swab32s\n\t#define swab64s __swab64s\n#endif\n\n#endif /* _LINUX_BYTEORDER_SWAB_H */\n"
  },
  {
    "path": "include/byteorder/swabb.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _LINUX_BYTEORDER_SWABB_H\n#define _LINUX_BYTEORDER_SWABB_H\n\n/*\n * linux/byteorder/swabb.h\n * SWAp Bytes Bizarrely\n *\tswaHHXX[ps]?(foo)\n *\n * Support for obNUXIous pdp-endian and other bizarre architectures.\n * Will Linux ever run on such ancient beasts? if not, this file\n * will be but a programming pearl. Still, it's a reminder that we\n * shouldn't be making too many assumptions when trying to be portable.\n *\n */\n\n/*\n * Meaning of the names I chose (vaxlinux people feel free to correct them):\n * swahw32\tswap 16-bit half-words in a 32-bit word\n * swahb32\tswap 8-bit halves of each 16-bit half-word in a 32-bit word\n *\n * No 64-bit support yet. I don't know NUXI conventions for long longs.\n * I guarantee it will be a mess when it's there, though :->\n * It will be even worse if there are conflicting 64-bit conventions.\n * Hopefully, no one ever used 64-bit objects on NUXI machines.\n *\n */\n\n#define ___swahw32(x) \\\n\t({ \\\n\t\t__u32 __x = (x); \\\n\t\t((__u32)(\\\n\t\t\t (((__u32)(__x) & (__u32)0x0000ffffUL) << 16) | \\\n\t\t\t (((__u32)(__x) & (__u32)0xffff0000UL) >> 16))); \\\n\t})\n#define ___swahb32(x) \\\n\t({ \\\n\t\t__u32 __x = (x); \\\n\t\t((__u32)(\\\n\t\t\t (((__u32)(__x) & (__u32)0x00ff00ffUL) << 8) | \\\n\t\t\t (((__u32)(__x) & (__u32)0xff00ff00UL) >> 8))); \\\n\t})\n\n#define ___constant_swahw32(x) \\\n\t((__u32)(\\\n\t\t (((__u32)(x) & (__u32)0x0000ffffUL) << 16) | \\\n\t\t (((__u32)(x) & (__u32)0xffff0000UL) >> 16)))\n#define ___constant_swahb32(x) \\\n\t((__u32)(\\\n\t\t (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) | \\\n\t\t (((__u32)(x) & (__u32)0xff00ff00UL) >> 8)))\n\n/*\n * provide defaults when no architecture-specific optimization is detected\n */\n#ifndef __arch__swahw32\n\t#define __arch__swahw32(x) ___swahw32(x)\n#endif\n#ifndef __arch__swahb32\n\t#define __arch__swahb32(x) ___swahb32(x)\n#endif\n\n#ifndef __arch__swahw32p\n\t#define __arch__swahw32p(x) __swahw32(*(x))\n#endif\n#ifndef __arch__swahb32p\n\t#define __arch__swahb32p(x) __swahb32(*(x))\n#endif\n\n#ifndef __arch__swahw32s\n\t#define __arch__swahw32s(x) do { *(x) = __swahw32p((x)); } while (0)\n#endif\n#ifndef __arch__swahb32s\n\t#define __arch__swahb32s(x) do { *(x) = __swahb32p((x)); } while (0)\n#endif\n\n\n/*\n * Allow constant folding\n */\n#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__)\n#  define __swahw32(x) \\\n\t(__builtin_constant_p((__u32)(x)) ? \\\n\t ___swahw32((x)) : \\\n\t __fswahw32((x)))\n#  define __swahb32(x) \\\n\t(__builtin_constant_p((__u32)(x)) ? \\\n\t ___swahb32((x)) : \\\n\t __fswahb32((x)))\n#else\n#  define __swahw32(x) __fswahw32(x)\n#  define __swahb32(x) __fswahb32(x)\n#endif /* OPTIMIZE */\n\n\n__inline static__ __const__ __u32 __fswahw32(__u32 x)\n{\n\treturn __arch__swahw32(x);\n}\n__inline static__ __u32 __swahw32p(__u32 *x)\n{\n\treturn __arch__swahw32p(x);\n}\n__inline static__ void __swahw32s(__u32 *addr)\n{\n\t__arch__swahw32s(addr);\n}\n\n\n__inline static__ __const__ __u32 __fswahb32(__u32 x)\n{\n\treturn __arch__swahb32(x);\n}\n__inline static__ __u32 __swahb32p(__u32 *x)\n{\n\treturn __arch__swahb32p(x);\n}\n__inline static__ void __swahb32s(__u32 *addr)\n{\n\t__arch__swahb32s(addr);\n}\n\n#ifdef __BYTEORDER_HAS_U64__\n\t/*\n\t* Not supported yet\n\t*/\n#endif /* __BYTEORDER_HAS_U64__ */\n\n#if defined(PLATFORM_LINUX)\n\t#define swahw32 __swahw32\n\t#define swahb32 __swahb32\n\t#define swahw32p __swahw32p\n\t#define swahb32p __swahb32p\n\t#define swahw32s __swahw32s\n\t#define swahb32s __swahb32s\n#endif\n\n#endif /* _LINUX_BYTEORDER_SWABB_H */\n"
  },
  {
    "path": "include/circ_buf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __CIRC_BUF_H_\n#define __CIRC_BUF_H_ 1\n\n#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1))\n\n#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))\n\n#endif //_CIRC_BUF_H_\n\n"
  },
  {
    "path": "include/cmd_osdep.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __CMD_OSDEP_H_\n#define __CMD_OSDEP_H_\n\n\nextern sint _rtw_init_cmd_priv(struct\tcmd_priv *pcmdpriv);\nextern sint _rtw_init_evt_priv(struct evt_priv *pevtpriv);\nextern void _rtw_free_evt_priv(struct\tevt_priv *pevtpriv);\nextern void _rtw_free_cmd_priv(struct\tcmd_priv *pcmdpriv);\nextern sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head);\nextern struct cmd_obj *_rtw_dequeue_cmd(_queue *queue);\n\n#endif\n"
  },
  {
    "path": "include/cmn_info/rtw_sta_info.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along with\n * this program; if not, write to the Free Software Foundation, Inc.,\n * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\n *\n *\n ******************************************************************************/\n\n /*This header file is for all driver teams to use the same station info.\nIf you want to change this file please make sure notify all driver teams maintainers.*/\n\n/*Created by YuChen 20170301*/\n\n#ifndef __INC_RTW_STA_INFO_H\n#define __INC_RTW_STA_INFO_H\n\n/*--------------------Define ---------------------------------------*/\n\n#define STA_DM_CTRL_ACTIVE\t\t\tBIT(0)\n#define STA_DM_CTRL_CFO_TRACKING\tBIT(1)\n\n#ifdef CONFIG_BEAMFORMING\n#define\tBEAMFORMING_HT_BEAMFORMER_ENABLE\tBIT(0)\t/*Declare sta support beamformer*/\n#define\tBEAMFORMING_HT_BEAMFORMEE_ENABLE\tBIT(1)\t/*Declare sta support beamformee*/\n#define\tBEAMFORMING_HT_BEAMFORMER_TEST\t\tBIT(2)\t/*Transmiting Beamforming no matter the target supports it or not*/\n#define\tBEAMFORMING_HT_BEAMFORMER_STEER_NUM\t\t(BIT(4)|BIT(5))\t\t/*Sta Bfer's capability*/\n#define\tBEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP\t(BIT(6)|BIT(7))\t\t/*Sta BFee's capability*/\n\n#define\tBEAMFORMING_VHT_BEAMFORMER_ENABLE\tBIT(0)\t/*Declare sta support beamformer*/\n#define\tBEAMFORMING_VHT_BEAMFORMEE_ENABLE\tBIT(1)\t/*Declare sta support beamformee*/\n#define\tBEAMFORMING_VHT_MU_MIMO_AP_ENABLE\tBIT(2)\t/*Declare sta support MU beamformer*/\n#define\tBEAMFORMING_VHT_MU_MIMO_STA_ENABLE\tBIT(3)\t/*Declare sta support MU beamformer*/\n#define\tBEAMFORMING_VHT_BEAMFORMER_TEST\t\tBIT(4)\t/*Transmiting Beamforming no matter the target supports it or not*/\n#define\tBEAMFORMING_VHT_BEAMFORMER_STS_CAP\t\t(BIT(8)|BIT(9)|BIT(10))\t\t/*Sta BFee's capability*/\n#define\tBEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM\t(BIT(12)|BIT(13)|BIT(14))\t/*Sta Bfer's capability*/\n#endif\n\n#define HT_STBC_EN\tBIT(0)\n#define VHT_STBC_EN\tBIT(1)\n\n#define HT_LDPC_EN\tBIT(0)\n#define VHT_LDPC_EN\tBIT(1)\n\n#define\tSM_PS_STATIC\t0\n#define\tSM_PS_DYNAMIC\t1\n#define\tSM_PS_INVALID\t2\n#define\tSM_PS_DISABLE\t3\n\n\n/*cmn_sta_info.ra_sta_info.txrx_state*/\n#define\tTX_STATE\t\t\t\t0\n#define\tRX_STATE\t\t\t\t1\n#define\tBI_DIRECTION_STATE\t2\n\n/*--------------------Define Enum-----------------------------------*/\nenum channel_width {\n\tCHANNEL_WIDTH_20\t\t= 0,\n\tCHANNEL_WIDTH_40\t\t= 1,\n\tCHANNEL_WIDTH_80\t\t= 2,\n\tCHANNEL_WIDTH_160\t\t= 3,\n\tCHANNEL_WIDTH_80_80\t= 4,\n\tCHANNEL_WIDTH_5\t\t= 5,\n\tCHANNEL_WIDTH_10\t= 6,\n\tCHANNEL_WIDTH_MAX\t= 7,\n};\n\nenum rf_type {\n\tRF_1T1R\t\t\t= 0,\n\tRF_1T2R\t\t\t= 1,\n\tRF_2T2R\t\t\t= 2,\n\tRF_2T3R\t\t\t= 3,\n\tRF_2T4R\t\t\t= 4,\n\tRF_3T3R\t\t\t= 5,\n\tRF_3T4R\t\t\t= 6,\n\tRF_4T4R\t\t\t= 7,\n\tRF_TYPE_MAX,\n};\n\nenum bb_path {\n\tBB_PATH_NON = 0,\n\tBB_PATH_A = 0x00000001,\n\tBB_PATH_B = 0x00000002,\n\tBB_PATH_C = 0x00000004,\n\tBB_PATH_D = 0x00000008,\n\n\tBB_PATH_AB = (BB_PATH_A | BB_PATH_B),\n\tBB_PATH_AC = (BB_PATH_A | BB_PATH_C),\n\tBB_PATH_AD = (BB_PATH_A | BB_PATH_D),\n\tBB_PATH_BC = (BB_PATH_B | BB_PATH_C),\n\tBB_PATH_BD = (BB_PATH_B | BB_PATH_D),\n\tBB_PATH_CD = (BB_PATH_C | BB_PATH_D),\n\n\tBB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),\n\tBB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),\n\tBB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),\n\tBB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),\n\n\tBB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),\n\tBB_PATH_AUTO = 0xff /*for path diversity*/\n};\n\nenum rf_path {\n\tRF_PATH_A = 0,\n\tRF_PATH_B = 1,\n\tRF_PATH_C = 2,\n\tRF_PATH_D = 3,\n\tRF_PATH_AB,\n\tRF_PATH_AC,\n\tRF_PATH_AD,\n\tRF_PATH_BC,\n\tRF_PATH_BD,\n\tRF_PATH_CD,\n\tRF_PATH_ABC,\n\tRF_PATH_ABD,\n\tRF_PATH_ACD,\n\tRF_PATH_BCD,\n\tRF_PATH_ABCD,\n};\n\nenum rf_syn {\n\tRF_SYN0 = 0,\n\tRF_SYN1 = 1,\n};\n\nenum rfc_mode {\n\trfc_4x4 = 0,\n\trfc_2x2 = 1,\n};\n\nenum wireless_set {\n\tWIRELESS_CCK\t= 0x00000001,\n\tWIRELESS_OFDM\t= 0x00000002,\n\tWIRELESS_HT\t= 0x00000004,\n\tWIRELESS_VHT\t= 0x00000008,\n};\n\n/*--------------------Define MACRO---------------------------------*/\n\n/*--------------------Define Struct-----------------------------------*/\n\n#ifdef CONFIG_BEAMFORMING\nstruct bf_cmn_info {\n\tu8\tht_beamform_cap;\t\t/*Sta capablity*/\n\tu16\tvht_beamform_cap;\t\t/*Sta capablity*/\n\tu16\tp_aid;\n\tu8\tg_id;\n};\n#endif\nstruct rssi_info {\n\ts8\t\trssi;\n\ts8\t\trssi_cck;\n\ts8\t\trssi_ofdm;\n\tu8\t\tpacket_map;\n\tu8\t\tofdm_pkt_cnt;\n\tu8\t\tcck_pkt_cnt;\n\tu16\t\tcck_sum_power;\n\tu8\t\tis_send_rssi;\n\tu8\t\tvalid_bit;\n\ts16\t\trssi_acc;\t/*accumulate RSSI for per packet MA sum*/\n};\n\nstruct ra_sta_info {\n\tu8\trate_id;\t\t\t/*[PHYDM] ratr_idx*/\n\tu8\trssi_level;\t\t\t/*[PHYDM]*/\n\tu8\tis_first_connect:1;\t\t/*[PHYDM] CE: ra_rpt_linked, AP: H2C_rssi_rpt*/\n\tu8\tis_support_sgi:1;\t\t/*[driver]*/\n\tu8\tis_vht_enable:2;\t\t/*[driver]*/\n\tu8\tdisable_ra:1;\t\t\t/*[driver]*/\n\tu8\tdisable_pt:1;\t\t\t/*[driver] remove is_disable_power_training*/\n\tu8\ttxrx_state:2;\t\t\t/*[PHYDM] 0: Tx, 1:Rx, 2:bi-direction*/\n\tu8\tis_noisy:1;\t\t\t/*[PHYDM]*/\n\tu8\tcurr_tx_rate;\t\t\t/*[PHYDM] FW->Driver*/\n\tenum channel_width\tra_bw_mode;\t/*[Driver] max bandwidth, for RA only*/\n\tenum channel_width\tcurr_tx_bw;\t/*[PHYDM] FW->Driver*/\n\tu8\tcurr_retry_ratio;\t\t/*[PHYDM] FW->Driver*/\n\tu64\tramask;\n};\n\nstruct dtp_info {\n\tu8\tdyn_tx_power;\t/*Dynamic Tx power offset*/\n\tu8\tlast_tx_power;\n\tu8\tsta_tx_high_power_lvl:4;\n\tu8\tsta_last_dtp_lvl:4;\n};\n\nstruct cmn_sta_info {\n\tu16\tdm_ctrl;\t\t\t/*[Driver]*/\n\tenum channel_width\tbw_mode;\t/*[Driver] max support BW*/\n\tu8\tmac_id;\t\t\t\t/*[Driver]*/\n\tu8\tmac_addr[6];\t\t\t/*[Driver]*/\n\tu16\taid;\t\t\t\t/*[Driver]*/\n\tenum rf_type mimo_type;\t\t\t/*[Driver] sta XTXR*/\n\tstruct rssi_info\trssi_stat;\t/*[PHYDM]*/\n\tstruct ra_sta_info\tra_info;\t/*[Driver&PHYDM]*/\n\tu16\ttx_moving_average_tp;\t\t/*[Driver] tx average MBps*/\n\tu16\trx_moving_average_tp;\t\t/*[Driver] rx average MBps*/\n\tu8\tstbc_en:2;\t\t\t/*[Driver] really transmitt STBC*/\n\tu8\tldpc_en:2;\t\t\t/*[Driver] really transmitt LDPC*/\n\tenum wireless_set\tsupport_wireless_set;/*[Driver]*/\n#ifdef CONFIG_BEAMFORMING\n\tstruct bf_cmn_info\tbf_info;\t/*[Driver]*/\n#endif\n\tu8\tsm_ps:2;\t\t\t/*[Driver]*/\n\tstruct dtp_info dtp_stat;\t\t/*[PHYDM] Dynamic Tx power offset*/\n\t/*u8\t\tpw2cca_over_TH_cnt;*/\n\t/*u8\t\ttotal_pw2cca_cnt;*/\n};\n\nstruct phydm_phyinfo_fw_struct {\n\tu8\t\trx_rssi[4];\t/* RSSI in 0~100 index */\n};\n\nstruct phydm_phyinfo_struct {\n\tu8\t\trx_pwdb_all;\n\tu8\t\tsignal_quality;\t\t\t\t/* OFDM: signal_quality=rx_mimo_signal_quality[0], CCK: signal qualityin 0-100 index. */\n\tu8\t\trx_mimo_signal_strength[4];\t/* RSSI in 0~100 index */\n\ts8\t\trx_mimo_signal_quality[4];\t\t/* OFDM: per-path's EVM translate to 0~100% , no used for CCK*/\n\tu8\t\trx_mimo_evm_dbm[4];\t\t\t/* per-path's original EVM (dbm) */\n\ts16\t\tcfo_short[4];\t\t\t\t\t/* per-path's cfo_short */\n\ts16\t\tcfo_tail[4];\t\t\t\t\t/* per-path's cfo_tail */\n\ts8\t\trx_power;\t\t\t\t\t/* in dBm Translate from PWdB */\n\ts8\t\trecv_signal_power;\t\t\t/* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */\n\tu8\t\tbt_rx_rssi_percentage;\n\tu8\t\tsignal_strength;\t\t\t\t/* in 0-100 index. */\n\ts8\t\trx_pwr[4];\t\t\t\t\t/* per-path's pwdb */\n\ts8\t\trx_snr[4];\t\t\t\t\t/* per-path's SNR\t*/\n\tu8\t\tant_idx[4];\t/*per-path's antenna index*/\n/*ODM_PHY_STATUS_NEW_TYPE_SUPPORT*/\n\tu8\t\trx_count:2;\t\t\t\t\t/* RX path counter---*/\n\tu8\t\tband_width:3;\n\tu8\t\trxsc:4;\t\t\t\t\t\t/* sub-channel---*/\n\tu8\t\tchannel;\t\t\t\t\t\t/* channel number---*/\n\tu8\t\tis_mu_packet:1;\t\t\t\t/* is MU packet or not---boolean*/\n\tu8\t\tis_beamformed:1;\t\t\t\t/* BF packet---boolean*/\n\tu8\t\tcnt_pw2cca;\n\tu8\t\tcnt_cca2agc_rdy;\n/*ODM_PHY_STATUS_NEW_TYPE_SUPPORT*/\n};\n\nstruct phydm_perpkt_info_struct {\n\tu8\t\tdata_rate;\n\tu8\t\tstation_id;\n\tu8\t\tis_cck_rate: 1;\n\tu8\t\trate_ss:3;\t\t\t/*spatial stream of data rate*/\n\tu8\t\tis_packet_match_bssid:1;\t/*boolean*/\n\tu8\t\tis_packet_to_self:1;\t\t/*boolean*/\n\tu8\t\tis_packet_beacon:1;\t\t/*boolean*/\n\tu8\t\tis_to_self:1;\t\t\t\t/*boolean*/\n\tu8\t\tppdu_cnt;\n};\n\n/*--------------------Export global variable----------------------------*/\n\n/*--------------------Function declaration-----------------------------*/\n\n#endif\n"
  },
  {
    "path": "include/custom_gpio.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __CUSTOM_GPIO_H__\n#define __CUSTOM_GPIO_H___\n\n#include <drv_conf.h>\n#include <osdep_service.h>\n\ntypedef enum cust_gpio_modes {\n\tWLAN_PWDN_ON,\n\tWLAN_PWDN_OFF,\n\tWLAN_POWER_ON,\n\tWLAN_POWER_OFF,\n\tWLAN_BT_PWDN_ON,\n\tWLAN_BT_PWDN_OFF\n} cust_gpio_modes_t;\n\nextern int rtw_wifi_gpio_init(void);\nextern int rtw_wifi_gpio_deinit(void);\nextern void rtw_wifi_gpio_wlan_ctrl(int onoff);\n\n#endif\n"
  },
  {
    "path": "include/drv_conf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __DRV_CONF_H__\n#define __DRV_CONF_H__\n#include \"autoconf.h\"\n#include \"hal_ic_cfg.h\"\n\n#define CONFIG_RSSI_PRIORITY\n#ifdef CONFIG_RTW_REPEATER_SON\n\t#ifndef CONFIG_AP\n\t\t#define CONFIG_AP\n\t#endif\n\t#ifndef CONFIG_CONCURRENT_MODE\n\t\t#define CONFIG_CONCURRENT_MODE\n\t#endif\n\t#ifndef CONFIG_BR_EXT\n\t\t#define CONFIG_BR_EXT\n\t#endif\n\t#ifndef CONFIG_RTW_REPEATER_SON_ID\n\t\t#define CONFIG_RTW_REPEATER_SON_ID\t\t\t0x02040608\n\t#endif\n\t//#define CONFIG_RTW_REPEATER_SON_ROOT\n\t#ifndef CONFIG_RTW_REPEATER_SON_ROOT\n\t\t#define CONFIG_LAYER2_ROAMING_ACTIVE\n\t#endif\n\t#undef CONFIG_POWER_SAVING\n#endif\n\n#if defined(CONFIG_MCC_MODE) && (!defined(CONFIG_CONCURRENT_MODE))\n\n\t#error \"Enable CONCURRENT_MODE before enable MCC MODE\\n\"\n\n#endif\n\n#if defined(CONFIG_MCC_MODE) && defined(CONFIG_BT_COEXIST)\n\n\t#error \"Disable BT COEXIST before enable MCC MODE\\n\"\n\n#endif\n\n#if defined(CONFIG_MCC_MODE) && defined(CONFIG_TDLS)\n\n\t#error \"Disable TDLS before enable MCC MODE\\n\"\n\n#endif\n\n#if defined(CONFIG_RTW_80211R) && !defined(CONFIG_LAYER2_ROAMING)\n\n\t#error \"Enable CONFIG_LAYER2_ROAMING before enable CONFIG_RTW_80211R\\n\"\n\n#endif\n\n/* Older Android kernel doesn't has CONFIG_ANDROID defined,\n * add this to force CONFIG_ANDROID defined */\n#ifdef CONFIG_PLATFORM_ANDROID\n\t#ifndef CONFIG_ANDROID\n\t\t#define CONFIG_ANDROID\n\t#endif\n#endif\n\n#ifdef CONFIG_ANDROID\n\t/* Some Android build will restart the UI while non-printable ascii is passed\n\t* between java and c/c++ layer (JNI). We force CONFIG_VALIDATE_SSID\n\t* for Android here. If you are sure there is no risk on your system about this,\n\t* mask this macro define to support non-printable ascii ssid.\n\t* #define CONFIG_VALIDATE_SSID */\n\n\t/* Android expect dbm as the rx signal strength unit */\n\t#define CONFIG_SIGNAL_DISPLAY_DBM\n#endif\n\n/*\n#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(CONFIG_RESUME_IN_WORKQUEUE)\n\t#warning \"You have CONFIG_HAS_EARLYSUSPEND enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically\"\n\t#undef CONFIG_RESUME_IN_WORKQUEUE\n#endif\n\n#if defined(CONFIG_ANDROID_POWER) && defined(CONFIG_RESUME_IN_WORKQUEUE)\n\t#warning \"You have CONFIG_ANDROID_POWER enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically\"\n\t#undef CONFIG_RESUME_IN_WORKQUEUE\n#endif\n*/\n\n#ifdef CONFIG_RESUME_IN_WORKQUEUE /* this can be removed, because there is no case for this... */\n\t#if !defined(CONFIG_WAKELOCK) && !defined(CONFIG_ANDROID_POWER)\n\t\t#error \"enable CONFIG_RESUME_IN_WORKQUEUE without CONFIG_WAKELOCK or CONFIG_ANDROID_POWER will suffer from the danger of wifi's unfunctionality...\"\n\t\t#error \"If you still want to enable CONFIG_RESUME_IN_WORKQUEUE in this case, mask this preprossor checking and GOOD LUCK...\"\n\t#endif\n#endif\n\n/* About USB VENDOR REQ */\n#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)\n\t#warning \"define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically\"\n\t#define CONFIG_USB_VENDOR_REQ_MUTEX\n#endif\n#if defined(CONFIG_VENDOR_REQ_RETRY) &&  !defined(CONFIG_USB_VENDOR_REQ_MUTEX)\n\t#warning \"define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_VENDOR_REQ_RETRY automatically\"\n\t#define CONFIG_USB_VENDOR_REQ_MUTEX\n#endif\n\n#if defined(CONFIG_DFS_SLAVE_WITH_RADAR_DETECT) && !defined(CONFIG_DFS_MASTER)\n\t#define CONFIG_DFS_MASTER\n#endif\n\n#if !defined(CONFIG_AP_MODE) && defined(CONFIG_DFS_MASTER)\n\t#error \"enable CONFIG_DFS_MASTER without CONFIG_AP_MODE\"\n#endif\n\n#ifdef CONFIG_WIFI_MONITOR\n\t/*\t#define CONFIG_MONITOR_MODE_XMIT\t*/\n#endif\n\n#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL\n\t#ifndef CONFIG_WIFI_MONITOR\n\t\t#define CONFIG_WIFI_MONITOR\n\t#endif\n\t#ifndef CONFIG_MONITOR_MODE_XMIT\n\t\t#define CONFIG_MONITOR_MODE_XMIT\n\t#endif\n\t#ifdef CONFIG_POWER_SAVING\n\t\t#undef CONFIG_POWER_SAVING\n\t#endif\n#endif\n\n#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA\n\t#ifdef CONFIG_POWER_SAVING\n\t\t#undef CONFIG_POWER_SAVING\n\t#endif\n\t#ifdef CONFIG_BEAMFORMING\n\t\t#undef CONFIG_BEAMFORMING\n\t#endif\n#endif\n\n#ifdef CONFIG_AP_MODE\n\t#define CONFIG_TX_MCAST2UNI /* AP mode support IP multicast->unicast */\n#endif\n\n#ifdef CONFIG_RTW_MESH\n\t#ifndef CONFIG_RTW_MESH_ACNODE_PREVENT\n\t#define CONFIG_RTW_MESH_ACNODE_PREVENT 1\n\t#endif\n\n\t#ifndef CONFIG_RTW_MESH_OFFCH_CAND\n\t#define CONFIG_RTW_MESH_OFFCH_CAND 1\n\t#endif\n\n\t#ifndef CONFIG_RTW_MESH_PEER_BLACKLIST\n\t#define CONFIG_RTW_MESH_PEER_BLACKLIST 1\n\t#endif\n\n\t#ifndef CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\t#define CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST 1\n\t#endif\n\t#ifndef CONFIG_RTW_MESH_CTO_MGATE_CARRIER\n\t#define CONFIG_RTW_MESH_CTO_MGATE_CARRIER CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\t#endif\n\n\t#ifndef CONFIG_RTW_MPM_TX_IES_SYNC_BSS\n\t#define CONFIG_RTW_MPM_TX_IES_SYNC_BSS 1\n\t#endif\n\t#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS\n\t\t#ifndef CONFIG_RTW_MESH_AEK\n\t\t#define CONFIG_RTW_MESH_AEK\n\t\t#endif\n\t#endif\n\n\t#ifndef CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\t#define CONFIG_RTW_MESH_DATA_BMC_TO_UC 1\n\t#endif\n#endif\n\n#if !defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE)\n#define CONFIG_SCAN_BACKOP\n#endif\n\n#define RTW_SCAN_SPARSE_MIRACAST 1\n#define RTW_SCAN_SPARSE_BG 0\n#define RTW_SCAN_SPARSE_ROAMING_ACTIVE 1\n\n#ifndef CONFIG_TX_AC_LIFETIME\n#define CONFIG_TX_AC_LIFETIME 1\n#endif\n#ifndef CONFIG_TX_ACLT_FLAGS\n#define CONFIG_TX_ACLT_FLAGS 0x00\n#endif\n#ifndef CONFIG_TX_ACLT_CONF_DEFAULT\n#define CONFIG_TX_ACLT_CONF_DEFAULT {0x0, 1024 * 1000, 1024 * 1000}\n#endif\n#ifndef CONFIG_TX_ACLT_CONF_AP_M2U\n#define CONFIG_TX_ACLT_CONF_AP_M2U {0xF, 256 * 1000, 256 * 1000}\n#endif\n#ifndef CONFIG_TX_ACLT_CONF_MESH\n#define CONFIG_TX_ACLT_CONF_MESH {0xF, 256 * 1000, 256 * 1000}\n#endif\n\n#ifndef CONFIG_RTW_HIQ_FILTER\n\t#define CONFIG_RTW_HIQ_FILTER 1\n#endif\n\n#ifndef CONFIG_RTW_ADAPTIVITY_EN\n\t#define CONFIG_RTW_ADAPTIVITY_EN 0\n#endif\n\n#ifndef CONFIG_RTW_ADAPTIVITY_MODE\n\t#define CONFIG_RTW_ADAPTIVITY_MODE 0\n#endif\n\n#ifndef CONFIG_RTW_ADAPTIVITY_TH_L2H_INI\n\t#define CONFIG_RTW_ADAPTIVITY_TH_L2H_INI 0\n#endif\n\n#ifndef CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF\n\t#define CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF 0\n#endif\n\n#ifndef CONFIG_RTW_EXCL_CHS\n\t#define CONFIG_RTW_EXCL_CHS {0}\n#endif\n\n#ifndef CONFIG_RTW_DFS_REGION_DOMAIN\n\t#define CONFIG_RTW_DFS_REGION_DOMAIN 0\n#endif\n\n#ifndef CONFIG_TXPWR_BY_RATE_EN\n#define CONFIG_TXPWR_BY_RATE_EN 2 /* by efuse */\n#endif\n#ifndef CONFIG_TXPWR_LIMIT_EN\n#define CONFIG_TXPWR_LIMIT_EN 2 /* by efuse */\n#endif\n\n#ifndef CONFIG_RTW_CHPLAN\n#define CONFIG_RTW_CHPLAN 0xFF /* RTW_CHPLAN_UNSPECIFIED */\n#endif\n\n/* compatible with old fashion configuration */\n#if defined(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY)\n\t#undef CONFIG_TXPWR_BY_RATE_EN\n\t#undef CONFIG_TXPWR_LIMIT_EN\n\t#define CONFIG_TXPWR_BY_RATE_EN 1\n\t#define CONFIG_TXPWR_LIMIT_EN 1\n#elif defined(CONFIG_CALIBRATE_TX_POWER_TO_MAX)\n\t#undef CONFIG_TXPWR_BY_RATE_EN\n\t#undef CONFIG_TXPWR_LIMIT_EN\n\t#define CONFIG_TXPWR_BY_RATE_EN 1\n\t#define CONFIG_TXPWR_LIMIT_EN 0\n#endif\n\n#ifndef RTW_DEF_MODULE_REGULATORY_CERT\n\t#define RTW_DEF_MODULE_REGULATORY_CERT 0\n#endif\n\n#if RTW_DEF_MODULE_REGULATORY_CERT\n\t/* force enable TX power by rate and TX power limit */\n\t#undef CONFIG_TXPWR_BY_RATE_EN\n\t#undef CONFIG_TXPWR_LIMIT_EN\n\t#define CONFIG_TXPWR_BY_RATE_EN 1\n\t#define CONFIG_TXPWR_LIMIT_EN 1\n#endif\n\n#if !CONFIG_TXPWR_LIMIT && CONFIG_TXPWR_LIMIT_EN\n\t#undef CONFIG_TXPWR_LIMIT\n\t#define CONFIG_TXPWR_LIMIT 1\n#endif\n\n#ifdef CONFIG_RTW_IPCAM_APPLICATION\n\t#undef CONFIG_TXPWR_BY_RATE_EN\n\t#define CONFIG_TXPWR_BY_RATE_EN 1\n\t#define CONFIG_RTW_CUSTOMIZE_BEEDCA\t\t0x0000431C\n\t#define CONFIG_RTW_CUSTOMIZE_BWMODE\t\t0x00\n\t#define CONFIG_RTW_CUSTOMIZE_RLSTA\t\t0x7\n#if defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B)\n\t#define CONFIG_RTW_TX_2PATH_EN\t\t/*\tmutually incompatible with STBC_TX & Beamformer\t*/\n#endif\n#endif\n/*#define CONFIG_EXTEND_LOWRATE_TXOP\t\t\t*/\n\n#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS\n\t#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS {0xFF, 0xFF, 0xFF, 0xFF}\n#endif\n#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS\n\t#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS {0xFF, 0xFF, 0xFF, 0xFF}\n#endif\n#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS\n\t#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS {0xFF, 0xFF, 0xFF, 0xFF}\n#endif\n#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS\n\t#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS {0xFF, 0xFF, 0xFF, 0xFF}\n#endif\n\n#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_A\n\t#define CONFIG_RTW_TARGET_TX_PWR_2G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}\n#endif\n\n#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_B\n\t#define CONFIG_RTW_TARGET_TX_PWR_2G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}\n#endif\n\n#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_C\n\t#define CONFIG_RTW_TARGET_TX_PWR_2G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}\n#endif\n\n#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_D\n\t#define CONFIG_RTW_TARGET_TX_PWR_2G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}\n#endif\n\n#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_A\n\t#define CONFIG_RTW_TARGET_TX_PWR_5G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1}\n#endif\n\n#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_B\n\t#define CONFIG_RTW_TARGET_TX_PWR_5G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1}\n#endif\n\n#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_C\n\t#define CONFIG_RTW_TARGET_TX_PWR_5G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1}\n#endif\n\n#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_D\n\t#define CONFIG_RTW_TARGET_TX_PWR_5G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1}\n#endif\n\n#ifndef CONFIG_RTW_AMPLIFIER_TYPE_2G\n\t#define CONFIG_RTW_AMPLIFIER_TYPE_2G 0\n#endif\n\n#ifndef CONFIG_RTW_AMPLIFIER_TYPE_5G\n\t#define CONFIG_RTW_AMPLIFIER_TYPE_5G 0\n#endif\n\n#ifndef CONFIG_RTW_RFE_TYPE\n\t#define CONFIG_RTW_RFE_TYPE 64\n#endif\n\n#ifndef CONFIG_RTW_GLNA_TYPE\n\t#define CONFIG_RTW_GLNA_TYPE 0\n#endif\n\n#ifndef CONFIG_RTW_PLL_REF_CLK_SEL\n\t#define CONFIG_RTW_PLL_REF_CLK_SEL 0x0F\n#endif\n\n#ifndef CONFIG_IFACE_NUMBER\n\t#ifdef CONFIG_CONCURRENT_MODE\n\t\t#define CONFIG_IFACE_NUMBER\t2\n\t#else\n\t\t#define CONFIG_IFACE_NUMBER\t1\n\t#endif\n#endif\n\n#ifndef CONFIG_CONCURRENT_MODE\n\t#if (CONFIG_IFACE_NUMBER > 1)\n\t\t#error \"CONFIG_IFACE_NUMBER over 1,but CONFIG_CONCURRENT_MODE not defined\"\n\t#endif\n#endif\n\n#if (CONFIG_IFACE_NUMBER == 0)\n\t#error \"CONFIG_IFACE_NUMBER cound not be 0 !!\"\n#endif\n\n#if (CONFIG_IFACE_NUMBER > 4)\n\t#error \"Not support over 4 interfaces yet !!\"\n#endif\n\n#if (CONFIG_IFACE_NUMBER > 8)\t/*IFACE_ID_MAX*/\n\t#error \"HW count not support over 8 interfaces !!\"\n#endif\n\n#if (CONFIG_IFACE_NUMBER > 2)\n\t#define CONFIG_MI_WITH_MBSSID_CAM\n\n\t#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\t\t#define CONFIG_MBSSID_CAM\n\t\t#if defined(CONFIG_RUNTIME_PORT_SWITCH)\n\t\t\t#undef CONFIG_RUNTIME_PORT_SWITCH\n\t\t#endif\n\t#endif\n\n\t#ifdef CONFIG_AP_MODE\n\t\t#define CONFIG_SUPPORT_MULTI_BCN\n\n\t\t#define CONFIG_SWTIMER_BASED_TXBCN\n\n\t\t#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) /* || defined(CONFIG_RTL8822C)*/\n\t\t#define CONFIG_FW_HANDLE_TXBCN\n\n\t\t#ifdef CONFIG_FW_HANDLE_TXBCN\n\t\t\t#ifdef CONFIG_SWTIMER_BASED_TXBCN\n\t\t\t\t#undef CONFIG_SWTIMER_BASED_TXBCN\n\t\t\t#endif\n\n\t\t\t#define CONFIG_LIMITED_AP_NUM\t4\n\t\t#endif\n\t#endif /*defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) */ /*|| defined(CONFIG_RTL8822C)*/\n\t#endif /*CONFIG_AP_MODE*/\n\n\t#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)\n\t#define CONFIG_CLIENT_PORT_CFG\n\t#define CONFIG_NEW_NETDEV_HDL\n\t#endif/*defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)*/\n\n#endif/*(CONFIG_IFACE_NUMBER > 2)*/\n\n#define MACID_NUM_SW_LIMIT 32\n#define SEC_CAM_ENT_NUM_SW_LIMIT 32\n\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)\n\t#define CONFIG_IEEE80211_BAND_5GHZ\n#endif\n\n#if defined(CONFIG_WOWLAN) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822C))\n\t#define CONFIG_WOW_PATTERN_HW_CAM\n#endif\n\n#ifndef CONFIG_TSF_UPDATE_PAUSE_FACTOR\n#define CONFIG_TSF_UPDATE_PAUSE_FACTOR 200\n#endif\n\n#ifndef CONFIG_TSF_UPDATE_RESTORE_FACTOR\n#define CONFIG_TSF_UPDATE_RESTORE_FACTOR 5\n#endif\n\n/*\n\tMark CONFIG_DEAUTH_BEFORE_CONNECT by Arvin 2015/07/20\n\tIf the failure of Wi-Fi connection is due to some irregular disconnection behavior (like unplug dongle,\n\tpower down etc.) in last time, we can unmark this flag to avoid some unpredictable response from AP.\n*/\n/*#define CONFIG_DEAUTH_BEFORE_CONNECT */\n\n/*#define CONFIG_WEXT_DONT_JOIN_BYSSID\t*/\n/* #include <rtl871x_byteorder.h> */\n\n\n/*#define CONFIG_DOSCAN_IN_BUSYTRAFFIC\t*/\n/*#define CONFIG_PHDYM_FW_FIXRATE\t\t*/\t/*\tAnother way to fix tx rate\t*/\n\n/*Don't release SDIO irq in suspend/resume procedure*/\n#define CONFIG_RTW_SDIO_KEEP_IRQ\t0\n\n/*\n * Add by Lucas@2016/02/15\n * For RX Aggregation\n */\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_RX_AGGREGATION)\n\t#define RTW_RX_AGGREGATION\n#endif /* CONFIG_SDIO_HCI || CONFIG_USB_RX_AGGREGATION */\n\n#ifdef CONFIG_RTW_HOSTAPD_ACS\n\t#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)\n\t\t#ifndef CONFIG_FIND_BEST_CHANNEL\n\t\t\t#define CONFIG_FIND_BEST_CHANNEL\n\t\t#endif\n\t#else\n\t\t#ifdef CONFIG_FIND_BEST_CHANNEL\n\t\t\t#undef CONFIG_FIND_BEST_CHANNEL\n\t\t#endif\n\t\t#ifndef CONFIG_RTW_ACS\n\t\t\t#define CONFIG_RTW_ACS\n\t\t#endif\n\t\t#ifndef CONFIG_BACKGROUND_NOISE_MONITOR\n\t\t\t#define CONFIG_BACKGROUND_NOISE_MONITOR\n\t\t#endif\n\t#endif\n#endif\n\n#ifdef CONFIG_RTW_80211K\n\t#ifndef CONFIG_RTW_ACS\n\t\t#define CONFIG_RTW_ACS\n\t#endif\n#endif /*CONFIG_RTW_80211K*/\n\n#ifdef DBG_CONFIG_ERROR_RESET\n#ifndef CONFIG_IPS\n#define CONFIG_IPS\n#endif\n#endif\n\n/* IPS */\n#ifndef RTW_IPS_MODE\n\t#if defined(CONFIG_IPS)\n\t\t#define RTW_IPS_MODE 1\n\t#else\n\t\t#define RTW_IPS_MODE 0\n\t#endif\n#endif /* !RTW_IPS_MODE */\n\n#if (RTW_IPS_MODE > 1 || RTW_IPS_MODE < 0)\n\t#error \"The CONFIG_IPS_MODE value is wrong. Please follow HowTo_enable_the_power_saving_functionality.pdf.\\n\"\n#endif\n\n/* LPS */\n#ifndef RTW_LPS_MODE\n\t#if defined(CONFIG_LPS_PG) || defined(CONFIG_LPS_PG_DDMA)\n\t\t#define RTW_LPS_MODE 3\n\t#elif defined(CONFIG_LPS_LCLK)\n\t\t#define RTW_LPS_MODE 2\n\t#elif defined(CONFIG_LPS)\n\t\t#define RTW_LPS_MODE 1\n\t#else\n\t\t#define RTW_LPS_MODE 0\n\t#endif \n#endif /* !RTW_LPS_MODE */\n\n#if (RTW_LPS_MODE > 3 || RTW_LPS_MODE < 0)\n\t#error \"The CONFIG_LPS_MODE value is wrong. Please follow HowTo_enable_the_power_saving_functionality.pdf.\\n\"\n#endif\n\n#ifndef RTW_LPS_1T1R\n#define RTW_LPS_1T1R 0\n#endif\n\n#ifndef RTW_WOW_LPS_1T1R\n#define RTW_WOW_LPS_1T1R 0\n#endif\n\n/* WOW LPS */\n#ifndef RTW_WOW_LPS_MODE\n\t#if defined(CONFIG_LPS_PG) || defined(CONFIG_LPS_PG_DDMA)\n\t\t#define RTW_WOW_LPS_MODE 3\n\t#elif defined(CONFIG_LPS_LCLK)\n\t\t#define RTW_WOW_LPS_MODE 2\n\t#elif defined(CONFIG_LPS)\n\t\t#define RTW_WOW_LPS_MODE 1\n\t#else\n\t\t#define RTW_WOW_LPS_MODE 0\n\t#endif\n#endif /* !RTW_WOW_LPS_MODE */\n\n#if (RTW_WOW_LPS_MODE > 3 || RTW_WOW_LPS_MODE < 0)\n\t#error \"The RTW_WOW_LPS_MODE value is wrong. Please follow HowTo_enable_the_power_saving_functionality.pdf.\\n\"\n#endif\n\n#ifdef RTW_REDUCE_SCAN_SWITCH_CH_TIME\n#ifndef CONFIG_RTL8822B\n\t#error \"Only 8822B support RTW_REDUCE_SCAN_SWITCH_CH_TIME\"\n#endif\n\t#ifndef RTW_CHANNEL_SWITCH_OFFLOAD\n\t\t#define RTW_CHANNEL_SWITCH_OFFLOAD\n\t#endif\n#endif\n\n#define CONFIG_RTW_TPT_MODE \n\n#ifdef CONFIG_PCI_BCN_POLLING\n#define CONFIG_BCN_ICF\n#endif \n\n#ifndef CONFIG_PCI_MSI\n#define CONFIG_RTW_PCI_MSI_DISABLE\n#endif\n\n#endif /* __DRV_CONF_H__ */\n"
  },
  {
    "path": "include/drv_types.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n/*-------------------------------------------------------------------------------\n\n\tFor type defines and data structure defines\n\n--------------------------------------------------------------------------------*/\n\n\n#ifndef __DRV_TYPES_H__\n#define __DRV_TYPES_H__\n\n#include <drv_conf.h>\n#include <basic_types.h>\n#include <osdep_service.h>\n#include <rtw_byteorder.h>\n#include <wlan_bssdef.h>\n#include <wifi.h>\n#include <ieee80211.h>\n#ifdef CONFIG_ARP_KEEP_ALIVE\n\t#include <net/neighbour.h>\n\t#include <net/arp.h>\n#endif\n\n#ifdef PLATFORM_OS_XP\n\t#include <drv_types_xp.h>\n#endif\n\n#ifdef PLATFORM_OS_CE\n\t#include <drv_types_ce.h>\n#endif\n\n#ifdef PLATFORM_LINUX\n\t#include <drv_types_linux.h>\n#endif\n\nenum _NIC_VERSION {\n\n\tRTL8711_NIC,\n\tRTL8712_NIC,\n\tRTL8713_NIC,\n\tRTL8716_NIC\n\n};\n\ntypedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER;\n\n#include <rtw_debug.h>\n#include <cmn_info/rtw_sta_info.h>\n#include <rtw_rf.h>\n#include \"../core/rtw_chplan.h\"\n\n#ifdef CONFIG_80211N_HT\n\t#include <rtw_ht.h>\n#endif\n\n#ifdef CONFIG_80211AC_VHT\n\t#include <rtw_vht.h>\n#endif\n\n#include <rtw_cmd.h>\n#include <cmd_osdep.h>\n#include <rtw_security.h>\n#include <rtw_xmit.h>\n#include <xmit_osdep.h>\n#include <rtw_recv.h>\n#include <rtw_rm.h>\n\n#ifdef CONFIG_BEAMFORMING\n\t#include <rtw_beamforming.h>\n#endif\n\n#include <recv_osdep.h>\n#include <rtw_efuse.h>\n#include <rtw_sreset.h>\n#include <hal_intf.h>\n#include <hal_com.h>\n#include<hal_com_h2c.h>\n#include <hal_com_led.h>\n#include \"../hal/hal_dm.h\"\n#include <rtw_qos.h>\n#include <rtw_pwrctrl.h>\n#include <rtw_mlme.h>\n#include <mlme_osdep.h>\n#include <rtw_io.h>\n#include <rtw_ioctl.h>\n#include <rtw_ioctl_set.h>\n#include <rtw_ioctl_query.h>\n#include <osdep_intf.h>\n#include <rtw_eeprom.h>\n#include <sta_info.h>\n#include <rtw_event.h>\n#include <rtw_mlme_ext.h>\n#include <rtw_mi.h>\n#include <rtw_ap.h>\n#ifdef CONFIG_RTW_MESH\n#include \"../core/mesh/rtw_mesh.h\"\n#endif\n#include <rtw_efuse.h>\n#include <rtw_version.h>\n#include <rtw_odm.h>\n\n#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER\n\t#include <rtw_mem.h>\n#endif\n\n#include <rtw_p2p.h>\n\n#ifdef CONFIG_TDLS\n\t#include <rtw_tdls.h>\n#endif /* CONFIG_TDLS */\n\n#ifdef CONFIG_WAPI_SUPPORT\n\t#include <rtw_wapi.h>\n#endif /* CONFIG_WAPI_SUPPORT */\n\n#ifdef CONFIG_MP_INCLUDED\n\t#include <rtw_mp.h>\n#endif /* CONFIG_MP_INCLUDED */\n\n#ifdef CONFIG_BR_EXT\n\t#include <rtw_br_ext.h>\n#endif /* CONFIG_BR_EXT */\n\n#ifdef CONFIG_IOL\n\t#include <rtw_iol.h>\n#endif /* CONFIG_IOL */\n\n#include <ip.h>\n#include <if_ether.h>\n#include <ethernet.h>\n#include <circ_buf.h>\n\n#include <rtw_android.h>\n\n#include <rtw_btcoex_wifionly.h>\n#include <rtw_btcoex.h>\n\n#ifdef CONFIG_MCC_MODE\n\t#include <rtw_mcc.h>\n#endif /*CONFIG_MCC_MODE */\n\n#ifdef CONFIG_RTW_REPEATER_SON\n\t#include <rtw_rson.h>\n#endif /*CONFIG_RTW_REPEATER_SON */\n\n#define SPEC_DEV_ID_NONE BIT(0)\n#define SPEC_DEV_ID_DISABLE_HT BIT(1)\n#define SPEC_DEV_ID_ENABLE_PS BIT(2)\n#define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3)\n#define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4)\n#define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5)\n\nstruct specific_device_id {\n\n\tu32\t\tflags;\n\n\tu16\t\tidVendor;\n\tu16\t\tidProduct;\n\n};\n\nstruct registry_priv {\n\tu8\tchip_version;\n\tu8\trfintfs;\n\tu8\tlbkmode;\n\tu8\thci;\n\tNDIS_802_11_SSID\tssid;\n\tu8\tnetwork_mode;\t/* infra, ad-hoc, auto */\n\tu8\tchannel;/* ad-hoc support requirement */\n\tu8\twireless_mode;/* A, B, G, auto */\n\tu8\tscan_mode;/* active, passive */\n\tu8\tradio_enable;\n\tu8\tpreamble;/* long, short, auto */\n\tu8\tvrtl_carrier_sense;/* Enable, Disable, Auto */\n\tu8\tvcs_type;/* RTS/CTS, CTS-to-self */\n\tu16\trts_thresh;\n\tu16  frag_thresh;\n\tu8\tadhoc_tx_pwr;\n\tu8\tsoft_ap;\n\tu8\tpower_mgnt;\n\tu8\tips_mode;\n\tu8\tlps_level;\n#ifdef CONFIG_LPS_1T1R\n\tu8\tlps_1t1r;\n#endif\n\tu8\tlps_chk_by_tp;\n#ifdef CONFIG_WOWLAN\n\tu8\twow_power_mgnt;\n\tu8\twow_lps_level;\n\t#ifdef CONFIG_LPS_1T1R\n\tu8\twow_lps_1t1r;\n\t#endif\n#endif /* CONFIG_WOWLAN */\n\tu8\tsmart_ps;\n#ifdef CONFIG_WMMPS_STA\n\tu8\twmm_smart_ps;\n#endif /* CONFIG_WMMPS_STA */\n\tu8   usb_rxagg_mode;\n\tu8\tdynamic_agg_enable;\n\tu8\tlong_retry_lmt;\n\tu8\tshort_retry_lmt;\n\tu16\tbusy_thresh;\n\tu16\tmax_bss_cnt;\n\tu8\tack_policy;\n\tu8\tmp_mode;\n#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)\n\tu8 mp_customer_str;\n#endif\n\tu8  mp_dm;\n\tu8\tsoftware_encrypt;\n\tu8\tsoftware_decrypt;\n#ifdef CONFIG_TX_EARLY_MODE\n\tu8   early_mode;\n#endif\n\tu8\tacm_method;\n\t/* WMM */\n\tu8\twmm_enable;\n#ifdef CONFIG_WMMPS_STA\n\t/* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */\n\tu8\tuapsd_max_sp_len;\n\t/* BIT0: AC_VO UAPSD, BIT1: AC_VI UAPSD, BIT2: AC_BK UAPSD, BIT3: AC_BE UAPSD */\n\tu8\tuapsd_ac_enable;\n#endif /* CONFIG_WMMPS_STA */\n\n\tWLAN_BSSID_EX    dev_network;\n\n#if CONFIG_TX_AC_LIFETIME\n\tu8 tx_aclt_flags;\n\tstruct tx_aclt_conf_t tx_aclt_confs[TX_ACLT_CONF_NUM];\n#endif\n\n\tu8 tx_bw_mode;\n#ifdef CONFIG_AP_MODE\n\tu8 bmc_tx_rate;\n#endif\n#ifdef CONFIG_80211N_HT\n\tu8\tht_enable;\n\t/* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz */\n\t/* 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7 */\n\t/* 0x21 means enable 2.4G 40MHz & 5G 80MHz */\n\tu8\tbw_mode;\n\tu8\tampdu_enable;/* for tx */\n\tu8\trx_stbc;\n\tu8\trx_ampdu_amsdu;/* Rx A-MPDU Supports A-MSDU is permitted */\n\tu8\ttx_ampdu_amsdu;/* Tx A-MPDU Supports A-MSDU is permitted */\n\tu8\ttx_quick_addba_req;\n\tu8 rx_ampdu_sz_limit_by_nss_bw[4][4]; /* 1~4SS, BW20~BW160 */\n\t/* Short GI support Bit Map */\n\t/* BIT0 - 20MHz, 1: support, 0: non-support */\n\t/* BIT1 - 40MHz, 1: support, 0: non-support */\n\t/* BIT2 - 80MHz, 1: support, 0: non-support */\n\t/* BIT3 - 160MHz, 1: support, 0: non-support */\n\tu8\tshort_gi;\n\t/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */\n\tu8\tldpc_cap;\n\t/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */\n\tu8\tstbc_cap;\n\t/*\n\t * BIT0: Enable VHT SU Beamformer\n\t * BIT1: Enable VHT SU Beamformee\n\t * BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer\n\t * BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee\n\t * BIT4: Enable HT Beamformer\n\t * BIT5: Enable HT Beamformee\n\t */\n\tu8\tbeamform_cap;\n\tu8\tbeamformer_rf_num;\n\tu8\tbeamformee_rf_num;\n#endif /* CONFIG_80211N_HT */\n\n#ifdef CONFIG_80211AC_VHT\n\tu8\tvht_enable; /* 0:disable, 1:enable, 2:auto */\n\tu8\tampdu_factor;\n\tu8 vht_rx_mcs_map[2];\n#endif /* CONFIG_80211AC_VHT */\n\n\tu8\tlowrate_two_xmit;\n\n\tu8\trf_config ;\n\tu8\tlow_power ;\n\n\tu8\twifi_spec;/* !turbo_mode */\n\tu8\tspecial_rf_path; /* 0: 2T2R ,1: only turn on path A 1T1R */\n\tchar alpha2[2];\n\tu8\tchannel_plan;\n\tu8\texcl_chs[MAX_CHANNEL_NUM];\n\tu8\tfull_ch_in_p2p_handshake; /* 0: reply only softap channel, 1: reply full channel list*/\n\n#ifdef CONFIG_BT_COEXIST\n\tu8\tbtcoex;\n\tu8\tbt_iso;\n\tu8\tbt_sco;\n\tu8\tbt_ampdu;\n\tu8\tant_num;\n\tu8\tsingle_ant_path;\n#endif\n\tBOOLEAN\tbAcceptAddbaReq;\n\n\tu8\tantdiv_cfg;\n\tu8\tantdiv_type;\n\tu8\tdrv_ant_band_switch;\n\n\tu8\tswitch_usb_mode;\n\n\tu8\tusbss_enable;/* 0:disable,1:enable */\n\tu8\thwpdn_mode;/* 0:disable,1:enable,2:decide by EFUSE config */\n\tu8\thwpwrp_detect;/* 0:disable,1:enable */\n\n\tu8\thw_wps_pbc;/* 0:disable,1:enable */\n\n#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE\n\tchar\tadaptor_info_caching_file_path[PATH_LENGTH_MAX];\n#endif\n\n#ifdef CONFIG_LAYER2_ROAMING\n\tu8\tmax_roaming_times; /* the max number driver will try to roaming */\n#endif\n\n#ifdef CONFIG_IOL\n\tu8 fw_iol; /* enable iol without other concern */\n#endif\n\n#ifdef CONFIG_80211D\n\tu8 enable80211d;\n#endif\n\n\tu8 ifname[16];\n\tu8 if2name[16];\n\n\tu8 notch_filter;\n\n\t/* for pll reference clock selction */\n\tu8 pll_ref_clk_sel;\n\n\t/* define for tx power adjust */\n#if CONFIG_TXPWR_LIMIT\n\tu8\tRegEnableTxPowerLimit;\n#endif\n\tu8\tRegEnableTxPowerByRate;\n\n\tu8 target_tx_pwr_valid;\n\ts8 target_tx_pwr_2g[RF_PATH_MAX][RATE_SECTION_NUM];\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\ts8 target_tx_pwr_5g[RF_PATH_MAX][RATE_SECTION_NUM - 1];\n#endif\n\n\tu8 tsf_update_pause_factor;\n\tu8 tsf_update_restore_factor;\n\n\ts8\tTxBBSwing_2G;\n\ts8\tTxBBSwing_5G;\n\tu8\tAmplifierType_2G;\n\tu8\tAmplifierType_5G;\n\tu8\tbEn_RFE;\n\tu8\tRFE_Type;\n\tu8\tPowerTracking_Type;\n\tu8\tGLNA_Type;\n\tu8  check_fw_ps;\n\tu8\tRegPwrTrimEnable;\n\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\tu8\tload_phy_file;\n\tu8\tRegDecryptCustomFile;\n#endif\n#ifdef CONFIG_CONCURRENT_MODE\n\tu8 virtual_iface_num;\n#endif\n\tu8 qos_opt_enable;\n\n\tu8 hiq_filter;\n\tu8 adaptivity_en;\n\tu8 adaptivity_mode;\n\ts8 adaptivity_th_l2h_ini;\n\ts8 adaptivity_th_edcca_hl_diff;\n\n\tu8 boffefusemask;\n\tBOOLEAN bFileMaskEfuse;\n\tBOOLEAN bBTFileMaskEfuse;\n#ifdef CONFIG_RTW_ACS\n\tu8 acs_auto_scan;\n\tu8 acs_mode;\n#endif\n\n#ifdef CONFIG_BACKGROUND_NOISE_MONITOR\n\tu8 nm_mode;\n#endif\n\tu32\treg_rxgain_offset_2g;\n\tu32\treg_rxgain_offset_5gl;\n\tu32\treg_rxgain_offset_5gm;\n\tu32\treg_rxgain_offset_5gh;\n\n#ifdef CONFIG_DFS_MASTER\n\tu8 dfs_region_domain;\n#endif\n\n#ifdef CONFIG_MCC_MODE\n\tu8 en_mcc;\n\tu32 rtw_mcc_single_tx_cri;\n\tu32 rtw_mcc_ap_bw20_target_tx_tp;\n\tu32 rtw_mcc_ap_bw40_target_tx_tp;\n\tu32 rtw_mcc_ap_bw80_target_tx_tp;\n\tu32 rtw_mcc_sta_bw20_target_tx_tp;\n\tu32 rtw_mcc_sta_bw40_target_tx_tp;\n\tu32 rtw_mcc_sta_bw80_target_tx_tp;\n\ts8 rtw_mcc_policy_table_idx;\n\tu8 rtw_mcc_duration;\n\tu8 rtw_mcc_enable_runtime_duration;\n\tu8 rtw_mcc_phydm_offload;\n#endif /* CONFIG_MCC_MODE */\n\n#ifdef CONFIG_RTW_NAPI\n\tu8 en_napi;\n#ifdef CONFIG_RTW_NAPI_DYNAMIC\n\tu32 napi_threshold;\t/* unit: Mbps */\n#endif /* CONFIG_RTW_NAPI_DYNAMIC */\n#ifdef CONFIG_RTW_GRO\n\tu8 en_gro;\n#endif /* CONFIG_RTW_GRO */\n#endif /* CONFIG_RTW_NAPI */\n\n#ifdef CONFIG_WOWLAN\n\tu8 wakeup_event;\n\tu8 suspend_type;\n#endif\n\n#ifdef CONFIG_SUPPORT_TRX_SHARED\n\tu8 trx_share_mode;\n#endif\n\tu8 check_hw_status;\n\tu8 wowlan_sta_mix_mode;\n\tu32 pci_aspm_config;\n\n\tu8 iqk_fw_offload;\n\tu8 ch_switch_offload;\n\n#ifdef CONFIG_TDLS\n\tu8 en_tdls;\n#endif\n\n#ifdef CONFIG_ADVANCE_OTA\n\tu8\tadv_ota;\n#endif\n\n#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT\n\tu8 fw_param_init;\n#endif\n#ifdef CONFIG_DYNAMIC_SOML\n\tu8 dyn_soml_en;\n\tu8 dyn_soml_train_num;\n\tu8 dyn_soml_interval;\n\tu8 dyn_soml_period;\n\tu8 dyn_soml_delay;\n#endif\n#ifdef CONFIG_FW_HANDLE_TXBCN\n\tu8 fw_tbtt_rpt;\n#endif\n\n#ifdef DBG_LA_MODE\n\tu8 la_mode_en;\n#endif\n\tu32 phydm_ability;\n\tu32 halrf_ability;\n#ifdef CONFIG_TDMADIG\n\tu8 tdmadig_en;\n\tu8 tdmadig_mode;\n\tu8 tdmadig_dynamic;\n#endif/*CONFIG_TDMADIG*/\n#ifdef CONFIG_RTW_MESH\n\tu8 peer_alive_based_preq;\n#endif\n\n#ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY\n\tu8 rtw_8822c_xcap_overwrite;\n#endif\n};\n\n/* For registry parameters */\n#define RGTRY_OFT(field) ((u32)FIELD_OFFSET(struct registry_priv, field))\n#define RGTRY_SZ(field)   sizeof(((struct registry_priv *) 0)->field)\n\n#define GetRegAmplifierType2G(_Adapter)\t(_Adapter->registrypriv.AmplifierType_2G)\n#define GetRegAmplifierType5G(_Adapter)\t(_Adapter->registrypriv.AmplifierType_5G)\n\n#define GetRegTxBBSwing_2G(_Adapter)\t(_Adapter->registrypriv.TxBBSwing_2G)\n#define GetRegTxBBSwing_5G(_Adapter)\t(_Adapter->registrypriv.TxBBSwing_5G)\n\n#define GetRegbENRFEType(_Adapter)\t(_Adapter->registrypriv.bEn_RFE)\n#define GetRegRFEType(_Adapter)\t(_Adapter->registrypriv.RFE_Type)\n#define GetRegGLNAType(_Adapter)\t(_Adapter->registrypriv.GLNA_Type)\n#define GetRegPowerTrackingType(_Adapter)\t(_Adapter->registrypriv.PowerTracking_Type)\n\n#define WOWLAN_IS_STA_MIX_MODE(_Adapter)\t(_Adapter->registrypriv.wowlan_sta_mix_mode)\n#define BSSID_OFT(field) ((u32)FIELD_OFFSET(WLAN_BSSID_EX, field))\n#define BSSID_SZ(field)   sizeof(((PWLAN_BSSID_EX) 0)->field)\n\n#define BW_MODE_2G(bw_mode) ((bw_mode) & 0x0F)\n#define BW_MODE_5G(bw_mode) ((bw_mode) >> 4)\n#ifdef CONFIG_80211N_HT\n#define REGSTY_BW_2G(regsty) BW_MODE_2G((regsty)->bw_mode)\n#define REGSTY_BW_5G(regsty) BW_MODE_5G((regsty)->bw_mode)\n#else\n#define REGSTY_BW_2G(regsty) CHANNEL_WIDTH_20\n#define REGSTY_BW_5G(regsty) CHANNEL_WIDTH_20\n#endif\n#define REGSTY_IS_BW_2G_SUPPORT(regsty, bw) (REGSTY_BW_2G((regsty)) >= (bw))\n#define REGSTY_IS_BW_5G_SUPPORT(regsty, bw) (REGSTY_BW_5G((regsty)) >= (bw))\n\n#define REGSTY_IS_11AC_ENABLE(regsty) ((regsty)->vht_enable != 0)\n#define REGSTY_IS_11AC_AUTO(regsty) ((regsty)->vht_enable == 2)\n\ntypedef struct rtw_if_operations {\n\tint __must_check (*read)(struct dvobj_priv *d, unsigned int addr, void *buf,\n\t\t\t\tsize_t len, bool fixed);\n\tint __must_check (*write)(struct dvobj_priv *d, unsigned int addr, void *buf,\n\t\t\t\t size_t len, bool fixed);\n} RTW_IF_OPS, *PRTW_IF_OPS;\n\n#ifdef CONFIG_SDIO_HCI\n\t#include <drv_types_sdio.h>\n\t#define INTF_DATA\tSDIO_DATA\n\t#define INTF_OPS\tPRTW_IF_OPS\n#elif defined(CONFIG_GSPI_HCI)\n\t#include <drv_types_gspi.h>\n\t#define INTF_DATA GSPI_DATA\n#elif defined(CONFIG_PCI_HCI)\n\t#include <drv_types_pci.h>\n#endif\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t#define is_primary_adapter(adapter) (adapter->adapter_type == PRIMARY_ADAPTER)\n\t#define is_vir_adapter(adapter) (adapter->adapter_type == VIRTUAL_ADAPTER)\n\t#define get_hw_port(adapter) (adapter->hw_port)\n#else\n\t#define is_primary_adapter(adapter) (1)\n\t#define is_vir_adapter(adapter) (0)\n\t#define get_hw_port(adapter) (HW_PORT0)\n#endif\n#define GET_PRIMARY_ADAPTER(padapter) (((_adapter *)padapter)->dvobj->padapters[IFACE_ID0])\n#define GET_IFACE_NUMS(padapter) (((_adapter *)padapter)->dvobj->iface_nums)\n#define GET_ADAPTER(padapter, iface_id) (((_adapter *)padapter)->dvobj->padapters[iface_id])\n\n#define GetDefaultAdapter(padapter)\tpadapter\n\nenum _IFACE_ID {\n\tIFACE_ID0, /*PRIMARY_ADAPTER*/\n\tIFACE_ID1,\n\tIFACE_ID2,\n\tIFACE_ID3,\n\tIFACE_ID4,\n\tIFACE_ID5,\n\tIFACE_ID6,\n\tIFACE_ID7,\n\tIFACE_ID_MAX,\n};\n\n#define VIF_START_ID\t1\n\n#ifdef CONFIG_DBG_COUNTER\n\nstruct rx_logs {\n\tu32 intf_rx;\n\tu32 intf_rx_err_recvframe;\n\tu32 intf_rx_err_skb;\n\tu32 intf_rx_report;\n\tu32 core_rx;\n\tu32 core_rx_pre;\n\tu32 core_rx_pre_ver_err;\n\tu32 core_rx_pre_mgmt;\n\tu32 core_rx_pre_mgmt_err_80211w;\n\tu32 core_rx_pre_mgmt_err;\n\tu32 core_rx_pre_ctrl;\n\tu32 core_rx_pre_ctrl_err;\n\tu32 core_rx_pre_data;\n\tu32 core_rx_pre_data_wapi_seq_err;\n\tu32 core_rx_pre_data_wapi_key_err;\n\tu32 core_rx_pre_data_handled;\n\tu32 core_rx_pre_data_err;\n\tu32 core_rx_pre_data_unknown;\n\tu32 core_rx_pre_unknown;\n\tu32 core_rx_enqueue;\n\tu32 core_rx_dequeue;\n\tu32 core_rx_post;\n\tu32 core_rx_post_decrypt;\n\tu32 core_rx_post_decrypt_wep;\n\tu32 core_rx_post_decrypt_tkip;\n\tu32 core_rx_post_decrypt_aes;\n\tu32 core_rx_post_decrypt_wapi;\n\tu32 core_rx_post_decrypt_hw;\n\tu32 core_rx_post_decrypt_unknown;\n\tu32 core_rx_post_decrypt_err;\n\tu32 core_rx_post_defrag_err;\n\tu32 core_rx_post_portctrl_err;\n\tu32 core_rx_post_indicate;\n\tu32 core_rx_post_indicate_in_oder;\n\tu32 core_rx_post_indicate_reoder;\n\tu32 core_rx_post_indicate_err;\n\tu32 os_indicate;\n\tu32 os_indicate_ap_mcast;\n\tu32 os_indicate_ap_forward;\n\tu32 os_indicate_ap_self;\n\tu32 os_indicate_err;\n\tu32 os_netif_ok;\n\tu32 os_netif_err;\n};\n\nstruct tx_logs {\n\tu32 os_tx;\n\tu32 os_tx_err_up;\n\tu32 os_tx_err_xmit;\n\tu32 os_tx_m2u;\n\tu32 os_tx_m2u_ignore_fw_linked;\n\tu32 os_tx_m2u_ignore_self;\n\tu32 os_tx_m2u_entry;\n\tu32 os_tx_m2u_entry_err_xmit;\n\tu32 os_tx_m2u_entry_err_skb;\n\tu32 os_tx_m2u_stop;\n\tu32 core_tx;\n\tu32 core_tx_err_pxmitframe;\n\tu32 core_tx_err_brtx;\n\tu32 core_tx_upd_attrib;\n\tu32 core_tx_upd_attrib_adhoc;\n\tu32 core_tx_upd_attrib_sta;\n\tu32 core_tx_upd_attrib_ap;\n\tu32 core_tx_upd_attrib_unknown;\n\tu32 core_tx_upd_attrib_dhcp;\n\tu32 core_tx_upd_attrib_icmp;\n\tu32 core_tx_upd_attrib_active;\n\tu32 core_tx_upd_attrib_err_ucast_sta;\n\tu32 core_tx_upd_attrib_err_ucast_ap_link;\n\tu32 core_tx_upd_attrib_err_sta;\n\tu32 core_tx_upd_attrib_err_link;\n\tu32 core_tx_upd_attrib_err_sec;\n\tu32 core_tx_ap_enqueue_warn_fwstate;\n\tu32 core_tx_ap_enqueue_warn_sta;\n\tu32 core_tx_ap_enqueue_warn_nosta;\n\tu32 core_tx_ap_enqueue_warn_link;\n\tu32 core_tx_ap_enqueue_warn_trigger;\n\tu32 core_tx_ap_enqueue_mcast;\n\tu32 core_tx_ap_enqueue_ucast;\n\tu32 core_tx_ap_enqueue;\n\tu32 intf_tx;\n\tu32 intf_tx_pending_ac;\n\tu32 intf_tx_pending_fw_under_survey;\n\tu32 intf_tx_pending_fw_under_linking;\n\tu32 intf_tx_pending_xmitbuf;\n\tu32 intf_tx_enqueue;\n\tu32 core_tx_enqueue;\n\tu32 core_tx_enqueue_class;\n\tu32 core_tx_enqueue_class_err_sta;\n\tu32 core_tx_enqueue_class_err_nosta;\n\tu32 core_tx_enqueue_class_err_fwlink;\n\tu32 intf_tx_direct;\n\tu32 intf_tx_direct_err_coalesce;\n\tu32 intf_tx_dequeue;\n\tu32 intf_tx_dequeue_err_coalesce;\n\tu32 intf_tx_dump_xframe;\n\tu32 intf_tx_dump_xframe_err_txdesc;\n\tu32 intf_tx_dump_xframe_err_port;\n};\n\nstruct int_logs {\n\tu32 all;\n\tu32 err;\n\tu32 tbdok;\n\tu32 tbder;\n\tu32 bcnderr;\n\tu32 bcndma;\n\tu32 bcndma_e;\n\tu32 rx;\n\tu32 rx_rdu;\n\tu32 rx_fovw;\n\tu32 txfovw;\n\tu32 mgntok;\n\tu32 highdok;\n\tu32 bkdok;\n\tu32 bedok;\n\tu32 vidok;\n\tu32 vodok;\n};\n\n#endif /* CONFIG_DBG_COUNTER */\n\nstruct debug_priv {\n\tu32 dbg_sdio_free_irq_error_cnt;\n\tu32 dbg_sdio_alloc_irq_error_cnt;\n\tu32 dbg_sdio_free_irq_cnt;\n\tu32 dbg_sdio_alloc_irq_cnt;\n\tu32 dbg_sdio_deinit_error_cnt;\n\tu32 dbg_sdio_init_error_cnt;\n\tu32 dbg_suspend_error_cnt;\n\tu32 dbg_suspend_cnt;\n\tu32 dbg_resume_cnt;\n\tu32 dbg_resume_error_cnt;\n\tu32 dbg_deinit_fail_cnt;\n\tu32 dbg_carddisable_cnt;\n\tu32 dbg_carddisable_error_cnt;\n\tu32 dbg_ps_insuspend_cnt;\n\tu32\tdbg_dev_unload_inIPS_cnt;\n\tu32 dbg_wow_leave_ps_fail_cnt;\n\tu32 dbg_scan_pwr_state_cnt;\n\tu32 dbg_downloadfw_pwr_state_cnt;\n\tu32 dbg_fw_read_ps_state_fail_cnt;\n\tu32 dbg_leave_ips_fail_cnt;\n\tu32 dbg_leave_lps_fail_cnt;\n\tu32 dbg_h2c_leave32k_fail_cnt;\n\tu32 dbg_diswow_dload_fw_fail_cnt;\n\tu32 dbg_enwow_dload_fw_fail_cnt;\n\tu32 dbg_ips_drvopen_fail_cnt;\n\tu32 dbg_poll_fail_cnt;\n\tu32 dbg_rpwm_toogle_cnt;\n\tu32 dbg_rpwm_timeout_fail_cnt;\n\tu32 dbg_sreset_cnt;\n\tu32 dbg_fw_mem_dl_error_cnt;\n\tu64 dbg_rx_fifo_last_overflow;\n\tu64 dbg_rx_fifo_curr_overflow;\n\tu64 dbg_rx_fifo_diff_overflow;\n};\n\nstruct rtw_traffic_statistics {\n\t/* tx statistics */\n\tu64\ttx_bytes;\n\tu64\ttx_pkts;\n\tu64\ttx_drop;\n\tu64\tcur_tx_bytes;\n\tu64\tlast_tx_bytes;\n\tu32\tcur_tx_tp; /* Tx throughput in Mbps. */\n\n\t/* rx statistics */\n\tu64\trx_bytes;\n\tu64\trx_pkts;\n\tu64\trx_drop;\n\tu64\tcur_rx_bytes;\n\tu64\tlast_rx_bytes;\n\tu32\tcur_rx_tp; /* Rx throughput in Mbps. */\n};\n\n#define SEC_CAP_CHK_BMC\tBIT0\n\n#define SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH\tBIT0\n\nstruct sec_cam_bmp {\n\tu32 m0;\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)\n\tu32 m1;\n#endif\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)\n\tu32 m2;\n#endif\n#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)\n\tu32 m3;\n#endif\n};\n\nstruct cam_ctl_t {\n\t_lock lock;\n\n\tu8 sec_cap;\n\tu32 flags;\n\n\tu8 num;\n\tstruct sec_cam_bmp used;\n\n\t_mutex sec_cam_access_mutex;\n};\n\nstruct sec_cam_ent {\n\tu16 ctrl;\n\tu8 mac[ETH_ALEN];\n\tu8 key[16];\n};\n\n#define KEY_FMT \"%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\"\n#define KEY_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \\\n\t((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9], ((u8 *)(x))[10], ((u8 *)(x))[11], \\\n\t((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15]\n\n#define RTW_DEFAULT_MGMT_MACID 1\n\nstruct macid_bmp {\n\tu32 m0;\n#if (MACID_NUM_SW_LIMIT > 32)\n\tu32 m1;\n#endif\n#if (MACID_NUM_SW_LIMIT > 64)\n\tu32 m2;\n#endif\n#if (MACID_NUM_SW_LIMIT > 96)\n\tu32 m3;\n#endif\n};\n\n#ifdef CONFIG_CLIENT_PORT_CFG\nstruct clt_port_t{\n\t_lock lock;\n\tu8 bmp;\n\ts8 num;\n};\n#define get_clt_num(adapter) (adapter_to_dvobj(adapter)->clt_port.num)\n#endif\n\nstruct macid_ctl_t {\n\t_lock lock;\n\tu8 num;\n\tstruct macid_bmp used;\n\tstruct macid_bmp bmc;\n\tstruct macid_bmp if_g[CONFIG_IFACE_NUMBER];\n\tstruct macid_bmp ch_g[2]; /* 2 ch concurrency */\n\n\tu8 iface_bmc[CONFIG_IFACE_NUMBER]; /* bmc TX macid for each iface*/\n\n\tu8 h2c_msr[MACID_NUM_SW_LIMIT];\n\tu8 bw[MACID_NUM_SW_LIMIT];\n\tu8 vht_en[MACID_NUM_SW_LIMIT];\n\tu32 rate_bmp0[MACID_NUM_SW_LIMIT];\n\tu32 rate_bmp1[MACID_NUM_SW_LIMIT];\n\tu8 op_num[H2C_MSR_ROLE_MAX]; /* number of macid having h2c_msr's OPMODE = 1 for specific ROLE */\n\n\tstruct sta_info *sta[MACID_NUM_SW_LIMIT]; /* corresponding stainfo when macid is not shared */\n\n\t/* macid sleep registers */\n\tu16 reg_sleep_m0;\n#if (MACID_NUM_SW_LIMIT > 32)\n\tu16 reg_sleep_m1;\n#endif\n#if (MACID_NUM_SW_LIMIT > 64)\n\tu16 reg_sleep_m2;\n#endif\n#if (MACID_NUM_SW_LIMIT > 96)\n\tu16 reg_sleep_m3;\n#endif\n};\n\n/* used for rf_ctl_t.rate_bmp_cck_ofdm */\n#define RATE_BMP_CCK\t\t0x000F\n#define RATE_BMP_OFDM\t\t0xFFF0\n#define RATE_BMP_HAS_CCK(_bmp_cck_ofdm)\t\t(_bmp_cck_ofdm & RATE_BMP_CCK)\n#define RATE_BMP_HAS_OFDM(_bmp_cck_ofdm)\t(_bmp_cck_ofdm & RATE_BMP_OFDM)\n#define RATE_BMP_GET_CCK(_bmp_cck_ofdm)\t\t(_bmp_cck_ofdm & RATE_BMP_CCK)\n#define RATE_BMP_GET_OFDM(_bmp_cck_ofdm)\t((_bmp_cck_ofdm & RATE_BMP_OFDM) >> 4)\n\n/* used for rf_ctl_t.rate_bmp_ht_by_bw */\n#define RATE_BMP_HT_1SS\t\t0x000000FF\n#define RATE_BMP_HT_2SS\t\t0x0000FF00\n#define RATE_BMP_HT_3SS\t\t0x00FF0000\n#define RATE_BMP_HT_4SS\t\t0xFF000000\n#define RATE_BMP_HAS_HT_1SS(_bmp_ht)\t\t(_bmp_ht & RATE_BMP_HT_1SS)\n#define RATE_BMP_HAS_HT_2SS(_bmp_ht)\t\t(_bmp_ht & RATE_BMP_HT_2SS)\n#define RATE_BMP_HAS_HT_3SS(_bmp_ht)\t\t(_bmp_ht & RATE_BMP_HT_3SS)\n#define RATE_BMP_HAS_HT_4SS(_bmp_ht)\t\t(_bmp_ht & RATE_BMP_HT_4SS)\n#define RATE_BMP_GET_HT_1SS(_bmp_ht)\t\t(_bmp_ht & RATE_BMP_HT_1SS)\n#define RATE_BMP_GET_HT_2SS(_bmp_ht)\t\t((_bmp_ht & RATE_BMP_HT_2SS) >> 8)\n#define RATE_BMP_GET_HT_3SS(_bmp_ht)\t\t((_bmp_ht & RATE_BMP_HT_3SS) >> 16)\n#define RATE_BMP_GET_HT_4SS(_bmp_ht)\t\t((_bmp_ht & RATE_BMP_HT_4SS) >> 24)\n\n/* used for rf_ctl_t.rate_bmp_vht_by_bw */\n#define RATE_BMP_VHT_1SS\t0x000003FF\n#define RATE_BMP_VHT_2SS\t0x000FFC00\n#define RATE_BMP_VHT_3SS\t0x3FF00000\n#define RATE_BMP_HAS_VHT_1SS(_bmp_vht)\t\t(_bmp_vht & RATE_BMP_VHT_1SS)\n#define RATE_BMP_HAS_VHT_2SS(_bmp_vht)\t\t(_bmp_vht & RATE_BMP_VHT_2SS)\n#define RATE_BMP_HAS_VHT_3SS(_bmp_vht)\t\t(_bmp_vht & RATE_BMP_VHT_3SS)\n#define RATE_BMP_GET_VHT_1SS(_bmp_vht)\t\t(_bmp_vht & RATE_BMP_VHT_1SS)\n#define RATE_BMP_GET_VHT_2SS(_bmp_vht)\t\t((_bmp_vht & RATE_BMP_VHT_2SS) >> 10)\n#define RATE_BMP_GET_VHT_3SS(_bmp_vht)\t\t((_bmp_vht & RATE_BMP_VHT_3SS) >> 20)\n\n#define TXPWR_LMT_REF_VHT_FROM_HT\tBIT0\n#define TXPWR_LMT_REF_HT_FROM_VHT\tBIT1\n\n#define TXPWR_LMT_HAS_CCK_1T\tBIT0\n#define TXPWR_LMT_HAS_CCK_2T\tBIT1\n#define TXPWR_LMT_HAS_CCK_3T\tBIT2\n#define TXPWR_LMT_HAS_CCK_4T\tBIT3\n#define TXPWR_LMT_HAS_OFDM_1T\tBIT4\n#define TXPWR_LMT_HAS_OFDM_2T\tBIT5\n#define TXPWR_LMT_HAS_OFDM_3T\tBIT6\n#define TXPWR_LMT_HAS_OFDM_4T\tBIT7\n\n#define OFFCHS_NONE\t\t\t0\n#define OFFCHS_LEAVING_OP\t1\n#define OFFCHS_LEAVE_OP\t\t2\n#define OFFCHS_BACKING_OP\t3\n\nstruct rf_ctl_t {\n\tconst struct country_chplan *country_ent;\n\tu8 ChannelPlan;\n\tu8 max_chan_nums;\n\tRT_CHANNEL_INFO channel_set[MAX_CHANNEL_NUM];\n\tstruct p2p_channels channel_list;\n\n\t_mutex offch_mutex;\n\tu8 offch_state;\n\n\t/* used for debug or by tx power limit */\n\tu16 rate_bmp_cck_ofdm;\t\t/* 20MHz */\n\tu32 rate_bmp_ht_by_bw[2];\t/* 20MHz, 40MHz. 4SS supported */\n\tu32 rate_bmp_vht_by_bw[4];\t/* 20MHz, 40MHz, 80MHz, 160MHz. up to 3SS supported */\n\n\t/* used by tx power limit */\n\tu8 highest_ht_rate_bw_bmp;\n\tu8 highest_vht_rate_bw_bmp;\n\n#if CONFIG_TXPWR_LIMIT\n\t_mutex txpwr_lmt_mutex;\n\t_list reg_exc_list;\n\tu8 regd_exc_num;\n\t_list txpwr_lmt_list;\n\tu8 txpwr_regd_num;\n\tconst char *regd_name;\n\n\tu8 txpwr_lmt_2g_cck_ofdm_state;\n\t#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\tu8 txpwr_lmt_5g_cck_ofdm_state;\n\tu8 txpwr_lmt_5g_20_40_ref;\n\t#endif\n#endif\n\n\tu8 ch_sel_same_band_prefer;\n\n#ifdef CONFIG_DFS\n\tu8 csa_ch;\n\n#ifdef CONFIG_DFS_MASTER\n\t_timer radar_detect_timer;\n\tbool radar_detect_by_others;\n\tu8 radar_detect_enabled;\n\tbool radar_detected;\n\n\tu8 radar_detect_ch;\n\tu8 radar_detect_bw;\n\tu8 radar_detect_offset;\n\n\tsystime cac_start_time;\n\tsystime cac_end_time;\n\tu8 cac_force_stop;\n\n#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT\n\tu8 dfs_slave_with_rd;\n#endif\n\tu8 dfs_ch_sel_d_flags;\n\n\tu8 dbg_dfs_fake_radar_detect_cnt;\n\tu8 dbg_dfs_radar_detect_trigger_non;\n\tu8 dbg_dfs_choose_dfs_ch_first;\n#endif /* CONFIG_DFS_MASTER */\n#endif /* CONFIG_DFS */\n};\n\n#define RTW_CAC_STOPPED 0\n#ifdef CONFIG_DFS_MASTER\n#define IS_CAC_STOPPED(rfctl) ((rfctl)->cac_end_time == RTW_CAC_STOPPED)\n#define IS_CH_WAITING(rfctl) (!IS_CAC_STOPPED(rfctl) && rtw_time_after((rfctl)->cac_end_time, rtw_get_current_time()))\n#define IS_UNDER_CAC(rfctl) (IS_CH_WAITING(rfctl) && rtw_time_after(rtw_get_current_time(), (rfctl)->cac_start_time))\n#define IS_RADAR_DETECTED(rfctl) ((rfctl)->radar_detected)\n#else\n#define IS_CAC_STOPPED(rfctl) 1\n#define IS_CH_WAITING(rfctl) 0\n#define IS_UNDER_CAC(rfctl) 0\n#define IS_RADAR_DETECTED(rfctl) 0\n#endif /* CONFIG_DFS_MASTER */\n\n#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT\n#define IS_DFS_SLAVE_WITH_RD(rfctl) ((rfctl)->dfs_slave_with_rd)\n#else\n#define IS_DFS_SLAVE_WITH_RD(rfctl) 0\n#endif\n\n#ifdef CONFIG_MBSSID_CAM\n#define TOTAL_MBID_CAM_NUM\t8\n#define INVALID_CAM_ID\t\t\t0xFF\nstruct mbid_cam_ctl_t {\n\t_lock lock;\n\tu8 bitmap;\n\tATOMIC_T mbid_entry_num;\n};\nstruct mbid_cam_cache {\n\tu8 iface_id;\n\t/*u8 role;*/ /*WIFI_STATION_STATE or WIFI_AP_STATE*/\n\tu8 mac_addr[ETH_ALEN];\n};\n#endif /*CONFIG_MBSSID_CAM*/\n\n#ifdef RTW_HALMAC\nstruct halmac_indicator {\n\tstruct submit_ctx *sctx;\n\tu8 *buffer;\n\tu32 buf_size;\n\tu32 ret_size;\n\tu32 status;\n};\n\nstruct halmacpriv {\n\t/* flags */\n\n\t/* For asynchronous functions */\n\tstruct halmac_indicator *indicator;\n\n\t/* Hardware parameters */\n#ifdef CONFIG_SDIO_HCI\n\t/* Store hardware tx queue page number setting */\n\tu16 txpage[HW_QUEUE_ENTRY];\n#endif /* CONFIG_SDIO_HCI */\n};\n#endif /* RTW_HALMAC */\n\n#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n/*info for H2C-0x2C*/\nstruct dft_info {\n\tu8 port_id;\n\tu8 mac_id;\n};\n#endif\n\n#ifdef CONFIG_HW_P0_TSF_SYNC\nstruct tsf_info {\n\tu8 sync_port;/*port_x's tsf sync to port_0*/\n\tu8 offset; /*tsf timer offset*/\n};\n#endif\n\nstruct dvobj_priv {\n\t/*-------- below is common data --------*/\n\tu8\tchip_type;\n\tu8\tHardwareType;\n\tu8\tinterface_type;/*USB,SDIO,SPI,PCI*/\n\n\tATOMIC_T\tbSurpriseRemoved;\n\tATOMIC_T\tbDriverStopped;\n\n\ts32\tprocessing_dev_remove;\n\n\tstruct debug_priv drv_dbg;\n\n\t_mutex hw_init_mutex;\n\t_mutex h2c_fwcmd_mutex;\n\n\t_mutex ioctrl_mutex;\n\n#ifdef CONFIG_RTW_CUSTOMER_STR\n\t_mutex customer_str_mutex;\n\tstruct submit_ctx *customer_str_sctx;\n\tu8 customer_str[RTW_CUSTOMER_STR_LEN];\n#endif\n\n\t_mutex setch_mutex;\n\t_mutex setbw_mutex;\n\t_mutex rf_read_reg_mutex;\n#ifdef CONFIG_SDIO_INDIRECT_ACCESS\n\t_mutex sd_indirect_access_mutex;\n#endif\n\n#ifdef CONFIG_SYSON_INDIRECT_ACCESS\n\t_mutex syson_indirect_access_mutex;\t/* System On Reg R/W */\n#endif\n\n\tunsigned char\toper_channel; /* saved channel info when call set_channel_bw */\n\tunsigned char\toper_bwmode;\n\tunsigned char\toper_ch_offset;/* PRIME_CHNL_OFFSET */\n\tsystime on_oper_ch_time;\n\n\t_adapter *padapters[CONFIG_IFACE_NUMBER];/*IFACE_ID_MAX*/\n\tu8 iface_nums; /* total number of ifaces used runtime */\n\tstruct mi_state iface_state;\n\n#ifdef CONFIG_AP_MODE\n\t#ifdef CONFIG_SUPPORT_MULTI_BCN\n\tu8\t\tnr_ap_if; /* total interface number of ap /go /mesh / nan mode. */\n\tu16\t\tinter_bcn_space; /* unit:ms */\n\t_queue\tap_if_q;\n\tu8\t\tvap_map;\n\tu8\t\tfw_bcn_offload;\n\tu8\t\tvap_tbtt_rpt_map;\n\t#endif /*CONFIG_SUPPORT_MULTI_BCN*/\n\t#ifdef CONFIG_RTW_REPEATER_SON\n\tstruct rtw_rson_struct  rson_data;\n\t#endif\n#endif\n#ifdef CONFIG_CLIENT_PORT_CFG\n\tstruct clt_port_t clt_port;\n#endif\n\n#ifdef CONFIG_HW_P0_TSF_SYNC\n\tstruct tsf_info p0_tsf;\n#endif\n\tsystime periodic_tsf_update_etime;\n\t_timer periodic_tsf_update_end_timer;\n\n\tstruct macid_ctl_t macid_ctl;\n\n\tstruct cam_ctl_t cam_ctl;\n\tstruct sec_cam_ent cam_cache[SEC_CAM_ENT_NUM_SW_LIMIT];\n\n#ifdef CONFIG_MBSSID_CAM\n\tstruct mbid_cam_ctl_t mbid_cam_ctl;\n\tstruct mbid_cam_cache mbid_cam_cache[TOTAL_MBID_CAM_NUM];\n#endif\n\n\tstruct rf_ctl_t rf_ctl;\n\n#if CONFIG_TX_AC_LIFETIME\n\tstruct tx_aclt_conf_t tx_aclt_force_val;\n\tu8 tx_aclt_flags;\n\tstruct tx_aclt_conf_t tx_aclt_confs[TX_ACLT_CONF_NUM];\n#endif\n\n\t/* For 92D, DMDP have 2 interface. */\n\tu8\tInterfaceNumber;\n\tu8\tNumInterfaces;\n\n\t/* In /Out Pipe information */\n\tint\tRtInPipe[2];\n\tint\tRtOutPipe[4];\n\tu8\tQueue2Pipe[HW_QUEUE_ENTRY];/* for out pipe mapping */\n\n\tu8\tirq_alloc;\n\tATOMIC_T continual_io_error;\n\n\tATOMIC_T disable_func;\n\n\tu8 xmit_block;\n\t_lock xmit_block_lock;\n\n\tstruct pwrctrl_priv pwrctl_priv;\n\n\tstruct rtw_traffic_statistics\ttraffic_stat;\n\n#ifdef PLATFORM_LINUX\n\t_thread_hdl_ rtnl_lock_holder;\n\n\t#if defined(CONFIG_IOCTL_CFG80211) && defined(RTW_SINGLE_WIPHY)\n\tstruct wiphy *wiphy;\n\t#endif\n#endif /* PLATFORM_LINUX */\n\n#ifdef CONFIG_SWTIMER_BASED_TXBCN\n\t_timer txbcn_timer;\n#endif\n\t_timer dynamic_chk_timer; /* dynamic/periodic check timer */\n\t\n#ifdef CONFIG_RTW_NAPI_DYNAMIC\n\tu8 en_napi_dynamic;\n#endif /* CONFIG_RTW_NAPI_DYNAMIC */\n\n#ifdef RTW_HALMAC\n\tvoid *halmac;\n\tstruct halmacpriv hmpriv;\n#endif /* RTW_HALMAC */\n\n#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\t/*info for H2C-0x2C*/\n\tstruct dft_info dft;\n#endif\n\n#ifdef CONFIG_RTW_WIFI_HAL\n\tu32 nodfs;\n#endif\n\n\t/*-------- below is for SDIO INTERFACE --------*/\n\n#ifdef INTF_DATA\n\tINTF_DATA intf_data;\n#endif\n#ifdef INTF_OPS\n\tINTF_OPS intf_ops;\n#endif\n\n\t/*-------- below is for USB INTERFACE --------*/\n\n#ifdef CONFIG_USB_HCI\n\n\tu8\tusb_speed; /* 1.1, 2.0 or 3.0 */\n\tu8\tnr_endpoint;\n\tu8\tRtNumInPipes;\n\tu8\tRtNumOutPipes;\n\tint\tep_num[6]; /* endpoint number */\n\n\tint\tRegUsbSS;\n\n\t_sema\tusb_suspend_sema;\n\n#ifdef CONFIG_USB_VENDOR_REQ_MUTEX\n\t_mutex  usb_vendor_req_mutex;\n#endif\n\n#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC\n\tu8 *usb_alloc_vendor_req_buf;\n\tu8 *usb_vendor_req_buf;\n#endif\n\n#ifdef PLATFORM_LINUX\n\tstruct usb_interface *pusbintf;\n\tstruct usb_device *pusbdev;\n#endif/* PLATFORM_LINUX */\n\n#ifdef PLATFORM_FREEBSD\n\tstruct usb_interface *pusbintf;\n\tstruct usb_device *pusbdev;\n#endif/* PLATFORM_FREEBSD */\n\n#endif/* CONFIG_USB_HCI */\n\n\t/*-------- below is for PCIE INTERFACE --------*/\n\n#ifdef CONFIG_PCI_HCI\n\n#ifdef PLATFORM_LINUX\n\tstruct pci_dev *ppcidev;\n\n\t/* PCI MEM map */\n\tunsigned long\tpci_mem_end;\t/* shared mem end\t*/\n\tunsigned long\tpci_mem_start;\t/* shared mem start\t*/\n\n\t/* PCI IO map */\n\tunsigned long\tpci_base_addr;\t/* device I/O address\t*/\n\n#ifdef RTK_129X_PLATFORM\n\tunsigned long\tctrl_start;\n\t/* PCI MASK addr */\n\tunsigned long\tmask_addr;\n\n\t/* PCI TRANSLATE addr */\n\tunsigned long\ttran_addr;\n\n\t_lock   io_reg_lock;\n#endif\n\n\t/* PciBridge */\n\tstruct pci_priv\tpcipriv;\n\n\tunsigned int irq; /* get from pci_dev.irq, store to net_device.irq */\n\tu16\tirqline;\n\tu8\tirq_enabled;\n\tRT_ISR_CONTENT\tisr_content;\n\t_lock\tirq_th_lock;\n\n\t/* ASPM */\n\tu8\tconst_pci_aspm;\n\tu8\tconst_amdpci_aspm;\n\tu8\tconst_hwsw_rfoff_d3;\n\tu8\tconst_support_pciaspm;\n\t/* pci-e bridge */\n\tu8\tconst_hostpci_aspm_setting;\n\t/* pci-e device */\n\tu8\tconst_devicepci_aspm_setting;\n\tu8\tb_support_aspm; /* If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00. */\n\tu8\tb_support_backdoor;\n\tu8\tbdma64;\n#endif/* PLATFORM_LINUX */\n\n#endif/* CONFIG_PCI_HCI */\n\n#ifdef CONFIG_MCC_MODE\n\tstruct mcc_obj_priv mcc_objpriv;\n#endif /*CONFIG_MCC_MODE */\n\n#ifdef CONFIG_RTW_TPT_MODE\n\tu8 tpt_mode; /* RTK T/P Testing Mode, 0:default mode */\n\tu32 edca_be_ul;\n\tu32 edca_be_dl;\n#endif \n\t/* also for RTK T/P Testing Mode */ \n\tu8 scan_deny;\n\n};\n\n#define DEV_STA_NUM(_dvobj)\t\t\tMSTATE_STA_NUM(&((_dvobj)->iface_state))\n#define DEV_STA_LD_NUM(_dvobj)\t\tMSTATE_STA_LD_NUM(&((_dvobj)->iface_state))\n#define DEV_STA_LG_NUM(_dvobj)\t\tMSTATE_STA_LG_NUM(&((_dvobj)->iface_state))\n#define DEV_TDLS_LD_NUM(_dvobj)\t\tMSTATE_TDLS_LD_NUM(&((_dvobj)->iface_state))\n#define DEV_AP_NUM(_dvobj)\t\t\tMSTATE_AP_NUM(&((_dvobj)->iface_state))\n#define DEV_AP_STARTING_NUM(_dvobj)\tMSTATE_AP_STARTING_NUM(&((_dvobj)->iface_state))\n#define DEV_AP_LD_NUM(_dvobj)\t\tMSTATE_AP_LD_NUM(&((_dvobj)->iface_state))\n#define DEV_ADHOC_NUM(_dvobj)\t\tMSTATE_ADHOC_NUM(&((_dvobj)->iface_state))\n#define DEV_ADHOC_LD_NUM(_dvobj)\tMSTATE_ADHOC_LD_NUM(&((_dvobj)->iface_state))\n#define DEV_MESH_NUM(_dvobj)\t\tMSTATE_MESH_NUM(&((_dvobj)->iface_state))\n#define DEV_MESH_LD_NUM(_dvobj)\t\tMSTATE_MESH_LD_NUM(&((_dvobj)->iface_state))\n#define DEV_P2P_DV_NUM(_dvobj)\t\tMSTATE_P2P_DV_NUM(&((_dvobj)->iface_state))\n#define DEV_P2P_GC_NUM(_dvobj)\t\tMSTATE_P2P_GC_NUM(&((_dvobj)->iface_state))\n#define DEV_P2P_GO_NUM(_dvobj)\t\tMSTATE_P2P_GO_NUM(&((_dvobj)->iface_state))\n#define DEV_SCAN_NUM(_dvobj)\t\tMSTATE_SCAN_NUM(&((_dvobj)->iface_state))\n#define DEV_WPS_NUM(_dvobj)\t\t\tMSTATE_WPS_NUM(&((_dvobj)->iface_state))\n#define DEV_ROCH_NUM(_dvobj)\t\tMSTATE_ROCH_NUM(&((_dvobj)->iface_state))\n#define DEV_MGMT_TX_NUM(_dvobj)\t\tMSTATE_MGMT_TX_NUM(&((_dvobj)->iface_state))\n#define DEV_U_CH(_dvobj)\t\t\tMSTATE_U_CH(&((_dvobj)->iface_state))\n#define DEV_U_BW(_dvobj)\t\t\tMSTATE_U_BW(&((_dvobj)->iface_state))\n#define DEV_U_OFFSET(_dvobj)\t\tMSTATE_U_OFFSET(&((_dvobj)->iface_state))\n\n#define dvobj_to_pwrctl(dvobj) (&(dvobj->pwrctl_priv))\n#define pwrctl_to_dvobj(pwrctl) container_of(pwrctl, struct dvobj_priv, pwrctl_priv)\n#define dvobj_to_macidctl(dvobj) (&(dvobj->macid_ctl))\n#define dvobj_to_sec_camctl(dvobj) (&(dvobj->cam_ctl))\n#define dvobj_to_regsty(dvobj) (&(dvobj->padapters[IFACE_ID0]->registrypriv))\n#if defined(CONFIG_IOCTL_CFG80211) && defined(RTW_SINGLE_WIPHY)\n#define dvobj_to_wiphy(dvobj) ((dvobj)->wiphy)\n#endif\n#define dvobj_to_rfctl(dvobj) (&(dvobj->rf_ctl))\n#define rfctl_to_dvobj(rfctl) container_of((rfctl), struct dvobj_priv, rf_ctl)\n\nstatic inline void dev_set_surprise_removed(struct dvobj_priv *dvobj)\n{\n\tATOMIC_SET(&dvobj->bSurpriseRemoved, _TRUE);\n}\nstatic inline void dev_clr_surprise_removed(struct dvobj_priv *dvobj)\n{\n\tATOMIC_SET(&dvobj->bSurpriseRemoved, _FALSE);\n}\nstatic inline void dev_set_drv_stopped(struct dvobj_priv *dvobj)\n{\n\tATOMIC_SET(&dvobj->bDriverStopped, _TRUE);\n}\nstatic inline void dev_clr_drv_stopped(struct dvobj_priv *dvobj)\n{\n\tATOMIC_SET(&dvobj->bDriverStopped, _FALSE);\n}\n#define dev_is_surprise_removed(dvobj)\t(ATOMIC_READ(&dvobj->bSurpriseRemoved) == _TRUE)\n#define dev_is_drv_stopped(dvobj)\t\t(ATOMIC_READ(&dvobj->bDriverStopped) == _TRUE)\n\n#ifdef PLATFORM_LINUX\nstatic inline struct device *dvobj_to_dev(struct dvobj_priv *dvobj)\n{\n\t/* todo: get interface type from dvobj and the return the dev accordingly */\n#ifdef RTW_DVOBJ_CHIP_HW_TYPE\n#endif\n\n#ifdef CONFIG_USB_HCI\n\treturn &dvobj->pusbintf->dev;\n#endif\n#ifdef CONFIG_SDIO_HCI\n\treturn &dvobj->intf_data.func->dev;\n#endif\n#ifdef CONFIG_GSPI_HCI\n\treturn &dvobj->intf_data.func->dev;\n#endif\n#ifdef CONFIG_PCI_HCI\n\treturn &dvobj->ppcidev->dev;\n#endif\n}\n#endif\n\n_adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj);\n_adapter *dvobj_get_unregisterd_adapter(struct dvobj_priv *dvobj);\n_adapter *dvobj_get_adapter_by_addr(struct dvobj_priv *dvobj, u8 *addr);\n#define dvobj_get_primary_adapter(dvobj)\t((dvobj)->padapters[IFACE_ID0])\n\nenum _hw_port {\n\tHW_PORT0,\n\tHW_PORT1,\n\tHW_PORT2,\n\tHW_PORT3,\n\tHW_PORT4,\n\tMAX_HW_PORT,\n};\n\n#ifdef CONFIG_CLIENT_PORT_CFG\nenum _client_port {\n\tCLT_PORT0 = HW_PORT1,\n\tCLT_PORT1 = HW_PORT2,\n\tCLT_PORT2 = HW_PORT3,\n\tCLT_PORT3 = HW_PORT4,\n\tCLT_PORT_INVALID = HW_PORT0,\n};\n\n#define MAX_CLIENT_PORT_NUM\t4\n#define get_clt_port(adapter) (adapter->client_port)\n#endif\n\nenum _ADAPTER_TYPE {\n\tPRIMARY_ADAPTER,\n\tVIRTUAL_ADAPTER,\n\tMAX_ADAPTER = 0xFF,\n};\n\ntypedef enum _DRIVER_STATE {\n\tDRIVER_NORMAL = 0,\n\tDRIVER_DISAPPEAR = 1,\n\tDRIVER_REPLACE_DONGLE = 2,\n} DRIVER_STATE;\n\n#ifdef CONFIG_RTW_NAPI\nenum _NAPI_STATE {\n\tNAPI_DISABLE = 0,\n\tNAPI_ENABLE = 1,\n};\n#endif\n\n#ifdef CONFIG_MAC_LOOPBACK_DRIVER\ntypedef struct loopbackdata {\n\t_sema\tsema;\n\t_thread_hdl_ lbkthread;\n\tu8 bstop;\n\tu32 cnt;\n\tu16 size;\n\tu16 txsize;\n\tu8 txbuf[0x8000];\n\tu16 rxsize;\n\tu8 rxbuf[0x8000];\n\tu8 msg[100];\n\n} LOOPBACKDATA, *PLOOPBACKDATA;\n#endif\n\n#define ADAPTER_TX_BW_2G(adapter) BW_MODE_2G((adapter)->driver_tx_bw_mode)\n#define ADAPTER_TX_BW_5G(adapter) BW_MODE_5G((adapter)->driver_tx_bw_mode)\n\nstruct _ADAPTER {\n\tint\tDriverState;/* for disable driver using module, use dongle to replace module. */\n\tint\tpid[3];/* process id from UI, 0:wps, 1:hostapd, 2:dhcpcd */\n\tint\tbDongle;/* build-in module or external dongle */\n\n\t#if defined(CONFIG_AP_MODE) && defined(CONFIG_SUPPORT_MULTI_BCN)\n\t_list\tlist;\n\tu8 vap_id;\n\t#endif\n\tstruct dvobj_priv *dvobj;\n\tstruct\tmlme_priv mlmepriv;\n\tstruct\tmlme_ext_priv mlmeextpriv;\n\tstruct\tcmd_priv\tcmdpriv;\n\tstruct\tevt_priv\tevtpriv;\n\n#ifdef CONFIG_RTW_80211K\n\tstruct\trm_priv\t\trmpriv;\n#endif\n\t/* struct\tio_queue\t*pio_queue; */\n\tstruct\tio_priv\tiopriv;\n\tstruct\txmit_priv\txmitpriv;\n\tstruct\trecv_priv\trecvpriv;\n\tstruct\tsta_priv\tstapriv;\n\tstruct\tsecurity_priv\tsecuritypriv;\n\t_lock   security_key_mutex; /* add for CONFIG_IEEE80211W, none 11w also can use */\n\tstruct\tregistry_priv\tregistrypriv;\n\n#ifdef CONFIG_RTW_NAPI\n\tstruct\tnapi_struct napi;\n\tu8\tnapi_state;\n#endif\n\n#ifdef CONFIG_MP_INCLUDED\n\tstruct\tmp_priv\tmppriv;\n#endif\n\n#ifdef CONFIG_AP_MODE\n\tstruct\thostapd_priv\t*phostapdpriv;\n#endif\n\n#ifdef CONFIG_IOCTL_CFG80211\n#ifdef CONFIG_P2P\n\tstruct cfg80211_wifidirect_info\tcfg80211_wdinfo;\n#endif /* CONFIG_P2P */\n#endif /* CONFIG_IOCTL_CFG80211 */\n\tu32\tsetband;\n\tATOMIC_T bandskip;\n\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info\twdinfo;\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_TDLS\n\tstruct tdls_info\ttdlsinfo;\n#endif /* CONFIG_TDLS */\n\n#ifdef CONFIG_WAPI_SUPPORT\n\tu8\tWapiSupport;\n\tRT_WAPI_T\twapiInfo;\n#endif\n\n#ifdef CONFIG_RTW_REPEATER_SON\n\tu8\trtw_rson_scanstage;\n#endif\n\n#ifdef CONFIG_WFD\n\tstruct wifi_display_info wfd_info;\n#endif /* CONFIG_WFD */\n\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\tstruct bt_coex_info coex_info;\n#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */\n\n\tERROR_CODE\t\tLastError; /* <20130613, Kordan> Only the functions associated with MP records the error code by now. */\n\n\tvoid *HalData;\n\tu32 hal_data_sz;\n\tstruct hal_ops\thal_func;\n\n\tu32\tIsrContent;\n\tu32\tImrContent;\n\n\tu8\tEepromAddressSize;\n\tu8\tbDriverIsGoingToUnload;\n\tu8\tinit_adpt_in_progress;\n\tu8\tbHaltInProgress;\n#ifdef CONFIG_GPIO_API\n\tu8\tpre_gpio_pin;\n\tstruct gpio_int_priv {\n\t\tu8 interrupt_mode;\n\t\tu8 interrupt_enable_mask;\n\t\tvoid (*callback[8])(u8 level);\n\t} gpiointpriv;\n#endif\n\t_thread_hdl_ cmdThread;\n#ifdef CONFIG_EVENT_THREAD_MODE\n\t_thread_hdl_ evtThread;\n#endif\n#ifdef CONFIG_XMIT_THREAD_MODE\n\t_thread_hdl_ xmitThread;\n#endif\n#ifdef CONFIG_RECV_THREAD_MODE\n\t_thread_hdl_ recvThread;\n#endif\n\tu8 registered;\n\n\tvoid (*intf_start)(_adapter *adapter);\n\tvoid (*intf_stop)(_adapter *adapter);\n\n#ifdef PLATFORM_LINUX\n\t_nic_hdl pnetdev;\n\tchar old_ifname[IFNAMSIZ];\n\n\t/* used by rtw_rereg_nd_name related function */\n\tstruct rereg_nd_name_data {\n\t\t_nic_hdl old_pnetdev;\n\t\tchar old_ifname[IFNAMSIZ];\n\t\tu8 old_ips_mode;\n\t\tu8 old_bRegUseLed;\n\t} rereg_nd_name_priv;\n\n\tu8 ndev_unregistering;\n\tint bup;\n\tstruct net_device_stats stats;\n\tstruct iw_statistics iwstats;\n\tstruct proc_dir_entry *dir_dev;/* for proc directory */\n\tstruct proc_dir_entry *dir_odm;\n\n#ifdef CONFIG_MCC_MODE\n\tstruct proc_dir_entry *dir_mcc;\n#endif /* CONFIG_MCC_MODE */\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tstruct wireless_dev *rtw_wdev;\n\tstruct rtw_wdev_priv wdev_data;\n\n#if !defined(RTW_SINGLE_WIPHY)\n\tstruct wiphy *wiphy;\n#endif\n\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n#endif /* PLATFORM_LINUX */\n\n#ifdef PLATFORM_FREEBSD\n\t_nic_hdl pifp;\n\tint bup;\n\t_lock glock;\n#endif /* PLATFORM_FREEBSD */\n\tu8 mac_addr[ETH_ALEN];\n\tint net_closed;\n\n\tu8 netif_up;\n\n\tu8 bLinkInfoDump;\n\t/*\tAdded by Albert 2012/10/26 */\n\t/*\tThe driver will show up the desired channel number when this flag is 1. */\n\tu8 bNotifyChannelChange;\n\tu8 bsta_tp_dump;\n#ifdef CONFIG_P2P\n\t/*\tAdded by Albert 2012/12/06 */\n\t/*\tThe driver will show the current P2P status when the upper application reads it. */\n\tu8 bShowGetP2PState;\n#endif\n#ifdef CONFIG_AUTOSUSPEND\n\tu8\tbDisableAutosuspend;\n#endif\n\n\tu8 isprimary; /* is primary adapter or not */\n\t/* notes:\n\t**\tif isprimary is true, the adapter_type value is 0, iface_id is IFACE_ID0 for PRIMARY_ADAPTER\n\t**\tif isprimary is false, the adapter_type value is 1, iface_id is IFACE_ID1 for VIRTUAL_ADAPTER\n\t**\trefer to iface_id if iface_nums>2 and isprimary is false and the adapter_type value is 0xff.*/\n\tu8 adapter_type;/*be used in  Multi-interface to recognize whether is PRIMARY_ADAPTER  or not(PRIMARY_ADAPTER/VIRTUAL_ADAPTER) .*/\n\tu8 hw_port; /*interface port type, it depends on HW port */\n\n\t#ifdef CONFIG_CLIENT_PORT_CFG\n\tu8 client_id;\n\tu8 client_port;\n\t#endif\n\t/*struct tsf_info tsf;*//*reserve define for 8814B*/\n\n\t/*extend to support multi interface*/\n\tu8 iface_id;\n\n#ifdef CONFIG_BR_EXT\n\t_lock\t\t\t\t\tbr_ext_lock;\n\t/* unsigned int\t\t\tmacclone_completed; */\n\tstruct nat25_network_db_entry\t*nethash[NAT25_HASH_SIZE];\n\tint\t\t\t\tpppoe_connection_in_progress;\n\tunsigned char\t\t\tpppoe_addr[MACADDRLEN];\n\tunsigned char\t\t\tscdb_mac[MACADDRLEN];\n\tunsigned char\t\t\tscdb_ip[4];\n\tstruct nat25_network_db_entry\t*scdb_entry;\n\tunsigned char\t\t\tbr_mac[MACADDRLEN];\n\tunsigned char\t\t\tbr_ip[4];\n\n\tstruct br_ext_info\t\tethBrExtInfo;\n#endif /* CONFIG_BR_EXT */\n\n#ifdef CONFIG_MAC_LOOPBACK_DRIVER\n\tPLOOPBACKDATA ploopback;\n#endif\n#ifdef CONFIG_AP_MODE\n\tu8 bmc_tx_rate;\n#endif\n\n\t/* for debug purpose */\n\tu8 fix_rate;\n\tu8 fix_bw;\n\tu8 data_fb; /* data rate fallback, valid only when fix_rate is not 0xff */\n\tu8 power_offset;\n\tu8 driver_tx_bw_mode;\n\tu8 rsvd_page_offset;\n\tu8 rsvd_page_num;\n#ifdef CONFIG_SUPPORT_FIFO_DUMP\n\tu8 fifo_sel;\n\tu32 fifo_addr;\n\tu32 fifo_size;\n#endif\n\n\tu8 driver_vcs_en; /* Enable=1, Disable=0 driver control vrtl_carrier_sense for tx */\n\tu8 driver_vcs_type;/* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */\n\tu8 driver_ampdu_spacing;/* driver control AMPDU Density for peer sta's rx */\n\tu8 driver_rx_ampdu_factor;/* 0xff: disable drv ctrl, 0:8k, 1:16k, 2:32k, 3:64k; */\n\tu8 driver_rx_ampdu_spacing;  /* driver control Rx AMPDU Density */\n\tu8 fix_rx_ampdu_accept;\n\tu8 fix_rx_ampdu_size; /* 0~127, TODO:consider each sta and each TID */\n#ifdef CONFIG_TX_AMSDU\n\tu8 tx_amsdu;\n\tu16 tx_amsdu_rate;\n#endif\n\tu8 driver_tx_max_agg_num; /*fix tx desc max agg num , 0xff: disable drv ctrl*/\n#ifdef DBG_RX_COUNTER_DUMP\n\tu8 dump_rx_cnt_mode;/*BIT0:drv,BIT1:mac,BIT2:phy*/\n\tu32 drv_rx_cnt_ok;\n\tu32 drv_rx_cnt_crcerror;\n\tu32 drv_rx_cnt_drop;\n#endif\n\n#ifdef CONFIG_DBG_COUNTER\n\tstruct rx_logs rx_logs;\n\tstruct tx_logs tx_logs;\n\tstruct int_logs int_logs;\n#endif\n\n#ifdef CONFIG_MCC_MODE\n\tstruct mcc_adapter_priv mcc_adapterpriv;\n#endif /* CONFIG_MCC_MODE */\n\n#ifdef CONFIG_RTW_MESH\n\tstruct rtw_mesh_cfg mesh_cfg;\n\tstruct rtw_mesh_info mesh_info;\n\t_timer mesh_path_timer;\n\t_timer mesh_path_root_timer;\n\t_timer mesh_atlm_param_req_timer; /* airtime link metrics param request timer */\n\t_workitem mesh_work;\n\tunsigned long wrkq_flags;\n#endif /* CONFIG_RTW_MESH */\n};\n\n#define adapter_to_dvobj(adapter) ((adapter)->dvobj)\n#define adapter_to_regsty(adapter) dvobj_to_regsty(adapter_to_dvobj((adapter)))\n#define adapter_to_pwrctl(adapter) dvobj_to_pwrctl(adapter_to_dvobj((adapter)))\n#define adapter_wdev_data(adapter) (&((adapter)->wdev_data))\n#if defined(RTW_SINGLE_WIPHY)\n#define adapter_to_wiphy(adapter) dvobj_to_wiphy(adapter_to_dvobj(adapter))\n#else\n#define adapter_to_wiphy(adapter) ((adapter)->wiphy)\n#endif\n\n#define adapter_to_rfctl(adapter) dvobj_to_rfctl(adapter_to_dvobj((adapter)))\n#define adapter_to_macidctl(adapter) dvobj_to_macidctl(adapter_to_dvobj((adapter)))\n\n#define adapter_mac_addr(adapter) (adapter->mac_addr)\n#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI\n#define adapter_pno_mac_addr(adapter) \\\n\t((adapter_wdev_data(adapter))->pno_mac_addr)\n#endif\n\n#define adapter_to_chset(adapter) (adapter_to_rfctl((adapter))->channel_set)\n\n#define mlme_to_adapter(mlme) container_of((mlme), struct _ADAPTER, mlmepriv)\n#define tdls_info_to_adapter(tdls) container_of((tdls), struct _ADAPTER, tdlsinfo)\n\n#define rtw_get_chip_type(adapter) (((PADAPTER)adapter)->dvobj->chip_type)\n#define rtw_get_hw_type(adapter) (((PADAPTER)adapter)->dvobj->HardwareType)\n#define rtw_get_intf_type(adapter) (((PADAPTER)adapter)->dvobj->interface_type)\n\n#define rtw_get_mi_nums(adapter) (((PADAPTER)adapter)->dvobj->iface_nums)\n\nstatic inline void rtw_set_surprise_removed(_adapter *padapter)\n{\n\tdev_set_surprise_removed(adapter_to_dvobj(padapter));\n}\nstatic inline void rtw_clr_surprise_removed(_adapter *padapter)\n{\n\tdev_clr_surprise_removed(adapter_to_dvobj(padapter));\n}\nstatic inline void rtw_set_drv_stopped(_adapter *padapter)\n{\n\tdev_set_drv_stopped(adapter_to_dvobj(padapter));\n}\nstatic inline void rtw_clr_drv_stopped(_adapter *padapter)\n{\n\tdev_clr_drv_stopped(adapter_to_dvobj(padapter));\n}\n#define rtw_is_surprise_removed(padapter)\t(dev_is_surprise_removed(adapter_to_dvobj(padapter)))\n#define rtw_is_drv_stopped(padapter)\t\t(dev_is_drv_stopped(adapter_to_dvobj(padapter)))\n\n/*\n * Function disabled.\n *   */\n#define DF_TX_BIT\t\tBIT0\t\t\t/*write_port_cancel*/\n#define DF_RX_BIT\t\tBIT1\t\t\t/*read_port_cancel*/\n#define DF_IO_BIT\t\tBIT2\n\n/* #define RTW_DISABLE_FUNC(padapter, func) (ATOMIC_ADD(&adapter_to_dvobj(padapter)->disable_func, (func))) */\n/* #define RTW_ENABLE_FUNC(padapter, func) (ATOMIC_SUB(&adapter_to_dvobj(padapter)->disable_func, (func))) */\n__inline static void RTW_DISABLE_FUNC(_adapter *padapter, int func_bit)\n{\n\tint\tdf = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func);\n\tdf |= func_bit;\n\tATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df);\n}\n\n__inline static void RTW_ENABLE_FUNC(_adapter *padapter, int func_bit)\n{\n\tint\tdf = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func);\n\tdf &= ~(func_bit);\n\tATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df);\n}\n\n#define RTW_CANNOT_RUN(padapter) \\\n\t(rtw_is_surprise_removed(padapter) || \\\n\t rtw_is_drv_stopped(padapter))\n\n#define RTW_IS_FUNC_DISABLED(padapter, func_bit) (ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func) & (func_bit))\n\n#define RTW_CANNOT_IO(padapter) \\\n\t(rtw_is_surprise_removed(padapter) || \\\n\t RTW_IS_FUNC_DISABLED((padapter), DF_IO_BIT))\n\n#define RTW_CANNOT_RX(padapter) \\\n\t(RTW_CANNOT_RUN(padapter) || \\\n\t RTW_IS_FUNC_DISABLED((padapter), DF_RX_BIT))\n\n#define RTW_CANNOT_TX(padapter) \\\n\t(RTW_CANNOT_RUN(padapter) || \\\n\t RTW_IS_FUNC_DISABLED((padapter), DF_TX_BIT))\n\n#ifdef CONFIG_PNO_SUPPORT\nint rtw_parse_ssid_list_tlv(char **list_str, pno_ssid_t *ssid, int max, int *bytes_left);\nint rtw_dev_pno_set(struct net_device *net, pno_ssid_t *ssid, int num,\n\t\t    int pno_time, int pno_repeat, int pno_freq_expo_max);\n#ifdef CONFIG_PNO_SET_DEBUG\n\tvoid rtw_dev_pno_debug(struct net_device *net);\n#endif /* CONFIG_PNO_SET_DEBUG */\n#endif /* CONFIG_PNO_SUPPORT */\n\nint rtw_suspend_free_assoc_resource(_adapter *padapter);\n#ifdef CONFIG_WOWLAN\n\tint rtw_suspend_wow(_adapter *padapter);\n\tint rtw_resume_process_wow(_adapter *padapter);\n#endif\n\n/* HCI Related header file */\n#ifdef CONFIG_USB_HCI\n\t#include <usb_osintf.h>\n\t#include <usb_ops.h>\n\t#include <usb_hal.h>\n#endif\n\n#ifdef CONFIG_SDIO_HCI\n\t#include <sdio_osintf.h>\n\t#include <sdio_ops.h>\n\t#include <sdio_hal.h>\n#endif\n\n#ifdef CONFIG_GSPI_HCI\n\t#include <gspi_osintf.h>\n\t#include <gspi_ops.h>\n\t#include <gspi_hal.h>\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\t#include <pci_osintf.h>\n\t#include <pci_ops.h>\n\t#include <pci_hal.h>\n#endif\n\n#endif /* __DRV_TYPES_H__ */\n"
  },
  {
    "path": "include/drv_types_ce.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __DRV_TYPES_CE_H__\n#define __DRV_TYPES_CE_H__\n\n#include <drv_conf.h>\n#include <osdep_service.h>\n\n#include <Sdcardddk.h>\n\n#define MAX_ACTIVE_REG_PATH 256\n\n#define MAX_MCAST_LIST_NUM\t\t\t\t\t32\n\n\n\n/* for ioctl */\n#define MAKE_DRIVER_VERSION(_MainVer, _MinorVer)\t((((u32)(_MainVer))<<16)+_MinorVer)\n\n#define NIC_HEADER_SIZE\t\t\t\t14\t\t\t/* !< can be moved to typedef.h */\n#define NIC_MAX_PACKET_SIZE\t\t\t1514\t\t/* !< can be moved to typedef.h */\n#define NIC_MAX_SEND_PACKETS\t\t\t10\t\t/* max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h */\n#define NIC_VENDOR_DRIVER_VERSION       MAKE_DRIVER_VERSION(0, 001)\t/* !< can be moved to typedef.h */\n#define NIC_MAX_PACKET_SIZE\t\t\t1514\t\t/* !< can be moved to typedef.h */\n\ntypedef struct _MP_REG_ENTRY {\n\n\tNDIS_STRING\t\tRegName;\t/* variable name text */\n\tBOOLEAN\t\t\tbRequired;\t/* 1->required, 0->optional */\n\n\tu8\t\t\tType;\t\t/* NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString */\n\tuint\t\t\tFieldOffset;\t/* offset to MP_ADAPTER field */\n\tuint\t\t\tFieldSize;\t/* size (in bytes) of the field */\n\n#ifdef UNDER_AMD64\n\tu64\t\t\tDefault;\n#else\n\tu32\t\t\tDefault;\t\t/* default value to use */\n#endif\n\n\tu32\t\t\tMin;\t\t\t/* minimum value allowed */\n\tu32\t\t\tMax;\t\t/* maximum value allowed */\n} MP_REG_ENTRY, *PMP_REG_ENTRY;\n\n#ifdef CONFIG_USB_HCI\ntypedef struct _USB_EXTENSION {\n\tLPCUSB_FUNCS    _lpUsbFuncs;\n\tUSB_HANDLE\t    _hDevice;\n\tPVOID\t\t    pAdapter;\n\n#if 0\n\tUSB_ENDPOINT_DESCRIPTOR\t\t_endpACLIn;\n\tUSB_ENDPOINT_DESCRIPTOR\t\t_endpACLOutHigh;\n\tUSB_ENDPOINT_DESCRIPTOR\t\t_endpACLOutNormal;\n\n\tUSB_PIPE        pPipeIn;\n\tUSB_PIPE        pPipeOutNormal;\n\tUSB_PIPE        pPipeOutHigh;\n#endif\n\n} USB_EXTENSION, *PUSB_EXTENSION;\n#endif\n\n\ntypedef struct _OCTET_STRING {\n\tu8      *Octet;\n\tu16      Length;\n} OCTET_STRING, *POCTET_STRING;\n\n\n\n\n\n#endif\n"
  },
  {
    "path": "include/drv_types_gspi.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __DRV_TYPES_GSPI_H__\n#define __DRV_TYPES_GSPI_H__\n\n/* SPI Header Files */\n#ifdef PLATFORM_LINUX\n\t#include <linux/platform_device.h>\n\t#include <linux/spi/spi.h>\n\t#include <linux/gpio.h>\n\t/* #include <mach/ldo.h> */\n\t#include <asm/mach-types.h>\n\t#include <asm/gpio.h>\n\t#include <asm/io.h>\n\t#include <mach/board.h>\n\t#include <mach/hardware.h>\n\t#include <mach/irqs.h>\n\t#include <custom_gpio.h>\n#endif\n\n\ntypedef struct gspi_data {\n\tu8  func_number;\n\n\tu8  tx_block_mode;\n\tu8  rx_block_mode;\n\tu32 block_transfer_len;\n\n#ifdef PLATFORM_LINUX\n\tstruct spi_device *func;\n\n\tstruct workqueue_struct *priv_wq;\n\tstruct delayed_work irq_work;\n#endif\n} GSPI_DATA, *PGSPI_DATA;\n\n#endif /*  #ifndef __DRV_TYPES_GSPI_H__ */\n"
  },
  {
    "path": "include/drv_types_linux.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __DRV_TYPES_LINUX_H__\n#define __DRV_TYPES_LINUX_H__\n\n\n#endif\n"
  },
  {
    "path": "include/drv_types_pci.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __DRV_TYPES_PCI_H__\n#define __DRV_TYPES_PCI_H__\n\n\n#ifdef PLATFORM_LINUX\n\t#include <linux/pci.h>\n#endif\n\n\n#define\tINTEL_VENDOR_ID\t\t\t\t0x8086\n#define\tSIS_VENDOR_ID\t\t\t\t\t0x1039\n#define\tATI_VENDOR_ID\t\t\t\t\t0x1002\n#define\tATI_DEVICE_ID\t\t\t\t\t0x7914\n#define\tAMD_VENDOR_ID\t\t\t\t\t0x1022\n\n#define\tPCI_MAX_BRIDGE_NUMBER\t\t\t255\n#define\tPCI_MAX_DEVICES\t\t\t\t32\n#define\tPCI_MAX_FUNCTION\t\t\t\t8\n\n#define\tPCI_CONF_ADDRESS   \t\t\t\t0x0CF8   /* PCI Configuration Space Address */\n#define\tPCI_CONF_DATA\t\t\t\t\t0x0CFC   /* PCI Configuration Space Data */\n\n#define\tPCI_CLASS_BRIDGE_DEV\t\t\t0x06\n#define\tPCI_SUBCLASS_BR_PCI_TO_PCI\t0x04\n\n#define\tPCI_CAPABILITY_ID_PCI_EXPRESS\t0x10\n\n#define\tU1DONTCARE\t\t\t\t\t0xFF\n#define\tU2DONTCARE\t\t\t\t\t0xFFFF\n#define\tU4DONTCARE\t\t\t\t\t0xFFFFFFFF\n\n#define PCI_VENDER_ID_REALTEK\t\t0x10ec\n\n#define HAL_HW_PCI_8180_DEVICE_ID\t0x8180\n#define HAL_HW_PCI_8185_DEVICE_ID           \t0x8185\t/* 8185 or 8185b */\n#define HAL_HW_PCI_8188_DEVICE_ID           \t0x8188\t/* 8185b\t\t */\n#define HAL_HW_PCI_8198_DEVICE_ID           \t0x8198\t/* 8185b\t\t */\n#define HAL_HW_PCI_8190_DEVICE_ID           \t0x8190\t/* 8190 */\n#define HAL_HW_PCI_8723E_DEVICE_ID\t\t0x8723\t/* 8723E */\n#define HAL_HW_PCI_8192_DEVICE_ID           \t0x8192\t/* 8192 PCI-E */\n#define HAL_HW_PCI_8192SE_DEVICE_ID\t\t0x8192\t/* 8192 SE */\n#define HAL_HW_PCI_8174_DEVICE_ID           \t0x8174\t/* 8192 SE */\n#define HAL_HW_PCI_8173_DEVICE_ID           \t0x8173\t/* 8191 SE Crab */\n#define HAL_HW_PCI_8172_DEVICE_ID           \t0x8172\t/* 8191 SE RE */\n#define HAL_HW_PCI_8171_DEVICE_ID           \t0x8171\t/* 8191 SE Unicron */\n#define HAL_HW_PCI_0045_DEVICE_ID\t\t\t0x0045\t/* 8190 PCI for Ceraga */\n#define HAL_HW_PCI_0046_DEVICE_ID\t\t\t0x0046\t/* 8190 Cardbus for Ceraga */\n#define HAL_HW_PCI_0044_DEVICE_ID\t\t\t0x0044\t/* 8192e PCIE for Ceraga */\n#define HAL_HW_PCI_0047_DEVICE_ID\t\t\t0x0047\t/* 8192e Express Card for Ceraga */\n#define HAL_HW_PCI_700F_DEVICE_ID\t\t\t0x700F\n#define HAL_HW_PCI_701F_DEVICE_ID\t\t\t0x701F\n#define HAL_HW_PCI_DLINK_DEVICE_ID\t\t0x3304\n#define HAL_HW_PCI_8188EE_DEVICE_ID\t\t0x8179\n\n#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI \t\t0x1000     /* 8190 support 16 pages of IO registers */\n#define HAL_HW_PCI_REVISION_ID_8190PCI\t\t\t0x00\n#define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE\t0x4000\t/* 8192 support 16 pages of IO registers */\n#define HAL_HW_PCI_REVISION_ID_8192PCIE\t\t\t0x01\n#define HAL_MEMORY_MAPPED_IO_RANGE_8192SE\t\t0x4000\t/* 8192 support 16 pages of IO registers */\n#define HAL_HW_PCI_REVISION_ID_8192SE\t\t\t0x10\n#define HAL_HW_PCI_REVISION_ID_8192CE\t\t\t0x1\n#define HAL_MEMORY_MAPPED_IO_RANGE_8192CE\t\t0x4000\t/* 8192 support 16 pages of IO registers */\n#define HAL_HW_PCI_REVISION_ID_8192DE\t\t\t0x0\n#define HAL_MEMORY_MAPPED_IO_RANGE_8192DE\t\t0x4000\t/* 8192 support 16 pages of IO registers */\n\nenum pci_bridge_vendor {\n\tPCI_BRIDGE_VENDOR_INTEL = 0x0,/* 0b'0000,0001 */\n\tPCI_BRIDGE_VENDOR_ATI, /* = 0x02, */ /* 0b'0000,0010 */\n\tPCI_BRIDGE_VENDOR_AMD, /* = 0x04, */ /* 0b'0000,0100 */\n\tPCI_BRIDGE_VENDOR_SIS ,/* = 0x08, */ /* 0b'0000,1000 */\n\tPCI_BRIDGE_VENDOR_UNKNOWN, /* = 0x40, */ /* 0b'0100,0000 */\n\tPCI_BRIDGE_VENDOR_MAX ,/* = 0x80 */\n} ;\n\n/* copy this data structor defination from MSDN SDK */\ntypedef struct _PCI_COMMON_CONFIG {\n\tu16\tVendorID;\n\tu16\tDeviceID;\n\tu16\tCommand;\n\tu16\tStatus;\n\tu8\tRevisionID;\n\tu8\tProgIf;\n\tu8\tSubClass;\n\tu8\tBaseClass;\n\tu8\tCacheLineSize;\n\tu8\tLatencyTimer;\n\tu8\tHeaderType;\n\tu8\tBIST;\n\n\tunion {\n\t\tstruct _PCI_HEADER_TYPE_0 {\n\t\t\tu32\tBaseAddresses[6];\n\t\t\tu32\tCIS;\n\t\t\tu16\tSubVendorID;\n\t\t\tu16\tSubSystemID;\n\t\t\tu32\tROMBaseAddress;\n\t\t\tu8\tCapabilitiesPtr;\n\t\t\tu8\tReserved1[3];\n\t\t\tu32\tReserved2;\n\n\t\t\tu8\tInterruptLine;\n\t\t\tu8\tInterruptPin;\n\t\t\tu8\tMinimumGrant;\n\t\t\tu8\tMaximumLatency;\n\t\t} type0;\n#if 0\n\t\tstruct _PCI_HEADER_TYPE_1 {\n\t\t\tu32 BaseAddresses[PCI_TYPE1_ADDRESSES];\n\t\t\tu8 PrimaryBusNumber;\n\t\t\tu8 SecondaryBusNumber;\n\t\t\tu8 SubordinateBusNumber;\n\t\t\tu8 SecondaryLatencyTimer;\n\t\t\tu8 IOBase;\n\t\t\tu8 IOLimit;\n\t\t\tu16 SecondaryStatus;\n\t\t\tu16 MemoryBase;\n\t\t\tu16 MemoryLimit;\n\t\t\tu16 PrefetchableMemoryBase;\n\t\t\tu16 PrefetchableMemoryLimit;\n\t\t\tu32 PrefetchableMemoryBaseUpper32;\n\t\t\tu32 PrefetchableMemoryLimitUpper32;\n\t\t\tu16 IOBaseUpper;\n\t\t\tu16 IOLimitUpper;\n\t\t\tu32 Reserved2;\n\t\t\tu32 ExpansionROMBase;\n\t\t\tu8 InterruptLine;\n\t\t\tu8 InterruptPin;\n\t\t\tu16 BridgeControl;\n\t\t} type1;\n\n\t\tstruct _PCI_HEADER_TYPE_2 {\n\t\t\tu32 BaseAddress;\n\t\t\tu8 CapabilitiesPtr;\n\t\t\tu8 Reserved2;\n\t\t\tu16 SecondaryStatus;\n\t\t\tu8 PrimaryBusNumber;\n\t\t\tu8 CardbusBusNumber;\n\t\t\tu8 SubordinateBusNumber;\n\t\t\tu8 CardbusLatencyTimer;\n\t\t\tu32 MemoryBase0;\n\t\t\tu32 MemoryLimit0;\n\t\t\tu32 MemoryBase1;\n\t\t\tu32 MemoryLimit1;\n\t\t\tu16 IOBase0_LO;\n\t\t\tu16 IOBase0_HI;\n\t\t\tu16 IOLimit0_LO;\n\t\t\tu16 IOLimit0_HI;\n\t\t\tu16 IOBase1_LO;\n\t\t\tu16 IOBase1_HI;\n\t\t\tu16 IOLimit1_LO;\n\t\t\tu16 IOLimit1_HI;\n\t\t\tu8 InterruptLine;\n\t\t\tu8 InterruptPin;\n\t\t\tu16 BridgeControl;\n\t\t\tu16 SubVendorID;\n\t\t\tu16 SubSystemID;\n\t\t\tu32 LegacyBaseAddress;\n\t\t\tu8 Reserved3[56];\n\t\t\tu32 SystemControl;\n\t\t\tu8 MultiMediaControl;\n\t\t\tu8 GeneralStatus;\n\t\t\tu8 Reserved4[2];\n\t\t\tu8 GPIO0Control;\n\t\t\tu8 GPIO1Control;\n\t\t\tu8 GPIO2Control;\n\t\t\tu8 GPIO3Control;\n\t\t\tu32 IRQMuxRouting;\n\t\t\tu8 RetryStatus;\n\t\t\tu8 CardControl;\n\t\t\tu8 DeviceControl;\n\t\t\tu8 Diagnostic;\n\t\t} type2;\n#endif\n\t} u;\n\n\tu8\tDeviceSpecific[108];\n} PCI_COMMON_CONFIG , *PPCI_COMMON_CONFIG;\n\ntypedef struct _RT_PCI_CAPABILITIES_HEADER {\n\tu8   CapabilityID;\n\tu8   Next;\n} RT_PCI_CAPABILITIES_HEADER, *PRT_PCI_CAPABILITIES_HEADER;\n\nstruct pci_priv {\n\tBOOLEAN\t\tpci_clk_req;\n\n\tu8\tpciehdr_offset;\n\t/* PCIeCap is only differece between B-cut and C-cut. */\n\t/* Configuration Space offset 72[7:4] */\n\t/* 0: A/B cut */\n\t/* 1: C cut and later. */\n\tu8\tpcie_cap;\n\tu8\tlinkctrl_reg;\n\n\tu8\tbusnumber;\n\tu8\tdevnumber;\n\tu8\tfuncnumber;\n\n\tu8\tpcibridge_busnum;\n\tu8\tpcibridge_devnum;\n\tu8\tpcibridge_funcnum;\n\tu8\tpcibridge_vendor;\n\tu16\tpcibridge_vendorid;\n\tu16\tpcibridge_deviceid;\n\tu8\tpcibridge_pciehdr_offset;\n\tu8\tpcibridge_linkctrlreg;\n\n\tu8\tamd_l1_patch;\n};\n\ntypedef struct _RT_ISR_CONTENT {\n\tunion {\n\t\tu32\t\t\tIntArray[2];\n\t\tu32\t\t\tIntReg4Byte;\n\t\tu16\t\t\tIntReg2Byte;\n\t};\n} RT_ISR_CONTENT, *PRT_ISR_CONTENT;\n\n/* #define RegAddr(addr)           (addr + 0xB2000000UL) */\n/* some platform macros will def here */\nstatic inline void NdisRawWritePortUlong(u32 port,  u32 val)\n{\n\toutl(val, port);\n\t/* writel(val, (u8 *)RegAddr(port));\t */\n}\n\nstatic inline void NdisRawWritePortUchar(u32 port,  u8 val)\n{\n\toutb(val, port);\n\t/* writeb(val, (u8 *)RegAddr(port)); */\n}\n\nstatic inline void NdisRawReadPortUchar(u32 port, u8 *pval)\n{\n\t*pval = inb(port);\n\t/* *pval = readb((u8 *)RegAddr(port)); */\n}\n\nstatic inline void NdisRawReadPortUshort(u32 port, u16 *pval)\n{\n\t*pval = inw(port);\n\t/* *pval = readw((u8 *)RegAddr(port)); */\n}\n\nstatic inline void NdisRawReadPortUlong(u32 port, u32 *pval)\n{\n\t*pval = inl(port);\n\t/* *pval = readl((u8 *)RegAddr(port)); */\n}\n\n\n#endif\n"
  },
  {
    "path": "include/drv_types_sdio.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __DRV_TYPES_SDIO_H__\n#define __DRV_TYPES_SDIO_H__\n\n/* SDIO Header Files */\n#ifdef PLATFORM_LINUX\n\t#include <linux/mmc/sdio_func.h>\n\t#include <linux/mmc/sdio_ids.h>\n\t#include <linux/mmc/host.h>\n\t#include <linux/mmc/card.h>\n\n\t#ifdef CONFIG_PLATFORM_SPRD\n\t\t#include <linux/gpio.h>\n\t\t#include <custom_gpio.h>\n\t#endif /* CONFIG_PLATFORM_SPRD */\n#endif\n\n#define RTW_SDIO_CLK_33M\t33000000\n#define RTW_SDIO_CLK_40M\t40000000\n#define RTW_SDIO_CLK_80M\t80000000\n#define RTW_SDIO_CLK_160M\t160000000\n\ntypedef struct sdio_data {\n\tu8  func_number;\n\n\tu8  tx_block_mode;\n\tu8  rx_block_mode;\n\tu32 block_transfer_len;\n\n#ifdef PLATFORM_LINUX\n\tstruct mmc_card *card;\n\tstruct sdio_func\t*func;\n\t_thread_hdl_ sys_sdio_irq_thd;\n\tunsigned int clock;\n\tunsigned int timing;\n\tu8\tsd3_bus_mode;\n#endif\n\n#ifdef DBG_SDIO\n#ifdef PLATFORM_LINUX\n\tstruct proc_dir_entry *proc_sdio_dbg;\n#endif /* PLATFORM_LINUX */\n\n\tu32 cmd52_err_cnt;\t/* CMD52 I/O error count */\n\tu32 cmd53_err_cnt;\t/* CMD53 I/O error count */\n\n#if (DBG_SDIO >= 1)\n\tu32 reg_dump_mark;\t/* reg dump at specific error count */\n#endif /* DBG_SDIO >= 1 */\n\n#if (DBG_SDIO >= 2)\n\tu8 *dbg_msg;\t\t/* Messages for debug */\n\tu8 dbg_msg_size;\n\tu8 *reg_mac;\t\t/* Device MAC register, 0x0~0x800 */\n\tu8 *reg_mac_ext;\t/* Device MAC extend register, 0x1000~0x1800 */\n\tu8 *reg_local;\t\t/* Device SDIO local register, 0x0~0xFF */\n\tu8 *reg_cia;\t\t/* SDIO CIA(CCCR, FBR and etc.), 0x0~0x1FF */\n#endif /* DBG_SDIO >= 2 */\n\n#if (DBG_SDIO >= 3)\n\tu8 dbg_enable;\t\t/* 0/1: disable/enable debug mode */\n\tu8 err_stop;\t\t/* Stop(surprise remove) when I/O error happen */\n\tu8 err_test;\t\t/* Simulate error happen */\n\tu8 err_test_triggered;\t/* Simulate error already triggered */\n#endif /* DBG_SDIO >= 3 */\n#endif /* DBG_SDIO */\n} SDIO_DATA, *PSDIO_DATA;\n\n#define dvobj_to_sdio_func(d)\t((d)->intf_data.func)\n\n#define RTW_SDIO_ADDR_CMD52_BIT\t\t(1<<17)\n#define RTW_SDIO_ADDR_CMD52_GEN(a)\t(a | RTW_SDIO_ADDR_CMD52_BIT)\n#define RTW_SDIO_ADDR_CMD52_CLR(a)\t(a&~RTW_SDIO_ADDR_CMD52_BIT)\n#define RTW_SDIO_ADDR_CMD52_CHK(a)\t(a&RTW_SDIO_ADDR_CMD52_BIT ? 1 : 0)\n\n#define RTW_SDIO_ADDR_F0_BIT\t\t(1<<18)\n#define RTW_SDIO_ADDR_F0_GEN(a)\t\t(a | RTW_SDIO_ADDR_F0_BIT)\n#define RTW_SDIO_ADDR_F0_CLR(a)\t\t(a&~RTW_SDIO_ADDR_F0_BIT)\n#define RTW_SDIO_ADDR_F0_CHK(a)\t\t(a&RTW_SDIO_ADDR_F0_BIT ? 1 : 0)\n\n#endif\n"
  },
  {
    "path": "include/drv_types_xp.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __DRV_TYPES_XP_H__\n#define __DRV_TYPES_XP_H__\n\n#include <drv_conf.h>\n#include <osdep_service.h>\n\n\n\n#define MAX_MCAST_LIST_NUM\t\t\t\t\t32\n\n\n\n/* for ioctl */\n#define MAKE_DRIVER_VERSION(_MainVer, _MinorVer)\t((((u32)(_MainVer))<<16)+_MinorVer)\n\n#define NIC_HEADER_SIZE\t\t\t\t14\t\t\t/* !< can be moved to typedef.h */\n#define NIC_MAX_PACKET_SIZE\t\t\t1514\t\t/* !< can be moved to typedef.h */\n#define NIC_MAX_SEND_PACKETS\t\t\t10\t\t/* max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h */\n#define NIC_VENDOR_DRIVER_VERSION       MAKE_DRIVER_VERSION(0, 001)\t/* !< can be moved to typedef.h */\n#define NIC_MAX_PACKET_SIZE\t\t\t1514\t\t/* !< can be moved to typedef.h */\n\n\n#undef ON_VISTA\n/* added by Jackson */\n#ifndef ON_VISTA\n\t/*\n\t* Bus driver versions\n\t*   */\n\n\t#define SDBUS_DRIVER_VERSION_1          0x100\n\t#define SDBUS_DRIVER_VERSION_2          0x200\n\n\t#define    SDP_FUNCTION_TYPE\t4\n\t#define    SDP_BUS_DRIVER_VERSION 5\n\t#define    SDP_BUS_WIDTH 6\n\t#define    SDP_BUS_CLOCK 7\n\t#define    SDP_BUS_INTERFACE_CONTROL 8\n\t#define    SDP_HOST_BLOCK_LENGTH 9\n\t#define    SDP_FUNCTION_BLOCK_LENGTH 10\n\t#define    SDP_FN0_BLOCK_LENGTH 11\n\t#define    SDP_FUNCTION_INT_ENABLE 12\n#endif\n\n\ntypedef struct _MP_REG_ENTRY {\n\n\tNDIS_STRING\t\tRegName;\t/* variable name text */\n\tBOOLEAN\t\t\tbRequired;\t/* 1->required, 0->optional */\n\n\tu8\t\t\tType;\t\t/* NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString */\n\tuint\t\t\tFieldOffset;\t/* offset to MP_ADAPTER field */\n\tuint\t\t\tFieldSize;\t/* size (in bytes) of the field */\n\n#ifdef UNDER_AMD64\n\tu64\t\t\tDefault;\n#else\n\tu32\t\t\tDefault;\t\t/* default value to use */\n#endif\n\n\tu32\t\t\tMin;\t\t\t/* minimum value allowed */\n\tu32\t\t\tMax;\t\t/* maximum value allowed */\n} MP_REG_ENTRY, *PMP_REG_ENTRY;\n\n\ntypedef struct _OCTET_STRING {\n\tu8      *Octet;\n\tu16      Length;\n} OCTET_STRING, *POCTET_STRING;\n\n\n\n\n\n#endif\n"
  },
  {
    "path": "include/ethernet.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n/*! \\file */\n#ifndef __INC_ETHERNET_H\n#define __INC_ETHERNET_H\n\n#define ETHERNET_ADDRESS_LENGTH\t\t\t\t6\t\t/* !< Ethernet Address Length */\n#define ETHERNET_HEADER_SIZE\t\t\t\t14\t\t/* !< Ethernet Header Length */\n#define LLC_HEADER_SIZE\t\t\t\t\t\t6\t\t/* !< LLC Header Length */\n#define TYPE_LENGTH_FIELD_SIZE\t\t\t\t2\t\t/* !< Type/Length Size */\n#define MINIMUM_ETHERNET_PACKET_SIZE\t\t60\t\t/* !< Minimum Ethernet Packet Size */\n#define MAXIMUM_ETHERNET_PACKET_SIZE\t\t1514\t/* !< Maximum Ethernet Packet Size */\n\n#define RT_ETH_IS_MULTICAST(_pAddr)\t((((u8 *)(_pAddr))[0]&0x01) != 0)\t\t/* !< Is Multicast Address? */\n#define RT_ETH_IS_BROADCAST(_pAddr)\t(\\\n\t\t((u8 *)(_pAddr))[0] == 0xff\t&&\t\t\\\n\t\t((u8 *)(_pAddr))[1] == 0xff\t&&\t\t\\\n\t\t((u8 *)(_pAddr))[2] == 0xff\t&&\t\t\\\n\t\t((u8 *)(_pAddr))[3] == 0xff\t&&\t\t\\\n\t\t((u8 *)(_pAddr))[4] == 0xff\t&&\t\t\\\n\t\t((u8 *)(_pAddr))[5] == 0xff)\t/* !< Is Broadcast Address? */\n\n\n#endif /*  #ifndef __INC_ETHERNET_H */\n"
  },
  {
    "path": "include/gspi_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __GSPI_HAL_H__\n#define __GSPI_HAL_H__\n\n\nvoid spi_int_dpc(PADAPTER padapter, u32 sdio_hisr);\nu8 rtw_set_hal_ops(_adapter *padapter);\n\n#ifdef CONFIG_RTL8188E\n\tvoid rtl8188es_set_hal_ops(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_RTL8723B\n\tvoid rtl8723bs_set_hal_ops(PADAPTER padapter);\n#endif\n\n#endif /* __GSPI_HAL_H__ */\n"
  },
  {
    "path": "include/gspi_ops.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __GSPI_OPS_H__\n#define __GSPI_OPS_H__\n\n/* follwing defination is based on\n * GSPI spec of RTL8723, we temp\n * suppose that it will be the same\n * for diff chips of GSPI, if not\n * we should move it to HAL folder */\n#define SPI_LOCAL_DOMAIN\t\t\t\t0x0\n#define WLAN_IOREG_DOMAIN\t\t\t0x8\n#define FW_FIFO_DOMAIN\t\t\t\t0x4\n#define TX_HIQ_DOMAIN\t\t\t\t\t0xc\n#define TX_MIQ_DOMAIN\t\t\t\t\t0xd\n#define TX_LOQ_DOMAIN\t\t\t\t\t0xe\n#define RX_RXFIFO_DOMAIN\t\t\t\t0x1f\n\n/* IO Bus domain address mapping */\n#define DEFUALT_OFFSET\t\t\t\t\t0x0\n#define SPI_LOCAL_OFFSET\t\t\t\t0x10250000\n#define WLAN_IOREG_OFFSET\t\t\t0x10260000\n#define FW_FIFO_OFFSET\t\t\t\t0x10270000\n#define TX_HIQ_OFFSET\t\t\t\t\t0x10310000\n#define TX_MIQ_OFFSET\t\t\t\t\t0x1032000\n#define TX_LOQ_OFFSET\t\t\t\t\t0x10330000\n#define RX_RXOFF_OFFSET\t\t\t\t0x10340000\n\n/* SPI Local registers */\n#define SPI_REG_TX_CTRL\t\t\t\t\t0x0000 /* SPI Tx Control */\n#define SPI_REG_STATUS_RECOVERY\t\t0x0004\n#define SPI_REG_INT_TIMEOUT\t\t\t0x0006\n#define SPI_REG_HIMR\t\t\t\t\t0x0014 /* SPI Host Interrupt Mask */\n#define SPI_REG_HISR\t\t\t\t\t0x0018 /* SPI Host Interrupt Service Routine */\n#define SPI_REG_RX0_REQ_LEN\t\t\t0x001C /* RXDMA Request Length */\n#define SPI_REG_FREE_TXPG\t\t\t\t0x0020 /* Free Tx Buffer Page */\n#define SPI_REG_HCPWM1\t\t\t\t\t0x0024 /* HCI Current Power Mode 1 */\n#define SPI_REG_HCPWM2\t\t\t\t\t0x0026 /* HCI Current Power Mode 2 */\n#define SPI_REG_HTSFR_INFO\t\t\t\t0x0030 /* HTSF Informaion */\n#define SPI_REG_HRPWM1\t\t\t\t\t0x0080 /* HCI Request Power Mode 1 */\n#define SPI_REG_HRPWM2\t\t\t\t\t0x0082 /* HCI Request Power Mode 2 */\n#define SPI_REG_HPS_CLKR\t\t\t\t0x0084 /* HCI Power Save Clock */\n#define SPI_REG_HSUS_CTRL\t\t\t\t0x0086 /* SPI HCI Suspend Control */\n#define SPI_REG_HIMR_ON\t\t\t\t0x0090 /* SPI Host Extension Interrupt Mask Always */\n#define SPI_REG_HISR_ON\t\t\t\t0x0091 /* SPI Host Extension Interrupt Status Always */\n#define SPI_REG_CFG\t\t\t\t\t\t0x00F0 /* SPI Configuration Register */\n\n#define SPI_TX_CTRL\t\t\t\t(SPI_REG_TX_CTRL | SPI_LOCAL_OFFSET)\n#define SPI_STATUS_RECOVERY\t\t\t(SPI_REG_STATUS_RECOVERY | SPI_LOCAL_OFFSET)\n#define SPI_INT_TIMEOUT\t\t\t\t\t(SPI_REG_INT_TIMEOUT | SPI_LOCAL_OFFSET)\n#define SPI_HIMR\t\t\t\t(SPI_REG_HIMR | SPI_LOCAL_OFFSET)\n#define SPI_HISR\t\t\t\t(SPI_REG_HISR | SPI_LOCAL_OFFSET)\n#define SPI_RX0_REQ_LEN_1_BYTE\t\t(SPI_REG_RX0_REQ_LEN | SPI_LOCAL_OFFSET)\n#define SPI_FREE_TXPG\t\t\t(SPI_REG_FREE_TXPG | SPI_LOCAL_OFFSET)\n\n#define\tSPI_HIMR_DISABLED\t\t\t\t0\n\n/* SPI HIMR MASK diff with SDIO */\n#define SPI_HISR_RX_REQUEST\t\t\tBIT(0)\n#define SPI_HISR_AVAL\t\t\t\t\tBIT(1)\n#define SPI_HISR_TXERR\t\t\t\t\tBIT(2)\n#define SPI_HISR_RXERR\t\t\t\t\tBIT(3)\n#define SPI_HISR_TXFOVW\t\t\t\tBIT(4)\n#define SPI_HISR_RXFOVW\t\t\t\tBIT(5)\n#define SPI_HISR_TXBCNOK\t\t\t\tBIT(6)\n#define SPI_HISR_TXBCNERR\t\t\t\tBIT(7)\n#define SPI_HISR_BCNERLY_INT\t\t\tBIT(16)\n#define SPI_HISR_ATIMEND\t\t\t\tBIT(17)\n#define SPI_HISR_ATIMEND_E\t\t\t\tBIT(18)\n#define SPI_HISR_CTWEND\t\t\t\tBIT(19)\n#define SPI_HISR_C2HCMD\t\t\t\tBIT(20)\n#define SPI_HISR_CPWM1\t\t\t\t\tBIT(21)\n#define SPI_HISR_CPWM2\t\t\t\t\tBIT(22)\n#define SPI_HISR_HSISR_IND\t\t\t\tBIT(23)\n#define SPI_HISR_GTINT3_IND\t\t\t\tBIT(24)\n#define SPI_HISR_GTINT4_IND\t\t\t\tBIT(25)\n#define SPI_HISR_PSTIMEOUT\t\t\t\tBIT(26)\n#define SPI_HISR_OCPINT\t\t\t\t\tBIT(27)\n#define SPI_HISR_TSF_BIT32_TOGGLE\t\tBIT(29)\n\n#define MASK_SPI_HISR_CLEAR\t\t(SPI_HISR_TXERR |\\\n\t\tSPI_HISR_RXERR |\\\n\t\tSPI_HISR_TXFOVW |\\\n\t\tSPI_HISR_RXFOVW |\\\n\t\tSPI_HISR_TXBCNOK |\\\n\t\tSPI_HISR_TXBCNERR |\\\n\t\tSPI_HISR_C2HCMD |\\\n\t\tSPI_HISR_CPWM1 |\\\n\t\tSPI_HISR_CPWM2 |\\\n\t\tSPI_HISR_HSISR_IND |\\\n\t\tSPI_HISR_GTINT3_IND |\\\n\t\tSPI_HISR_GTINT4_IND |\\\n\t\tSPI_HISR_PSTIMEOUT |\\\n\t\tSPI_HISR_OCPINT)\n\n#define REG_LEN_FORMAT(pcmd, x) \t\t\tSET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)/* (x<<(unsigned int)24) */\n#define REG_ADDR_FORMAT(pcmd, x) \t\t\tSET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)/* (x<<(unsigned int)16) */\n#define REG_DOMAIN_ID_FORMAT(pcmd, x) \t\tSET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)/* (x<<(unsigned int)0) */\n#define REG_FUN_FORMAT(pcmd, x) \t\t\tSET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)/* (x<<(unsigned int)5) */\n#define REG_RW_FORMAT(pcmd, x) \t\t\t\tSET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)/* (x<<(unsigned int)7) */\n\n#define FIFO_LEN_FORMAT(pcmd, x) \t\t\tSET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)/* (x<<(unsigned int)24)\n * #define FIFO_ADDR_FORMAT(pcmd,x) \t\t\tSET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x) */ /* (x<<(unsigned int)16) */\n#define FIFO_DOMAIN_ID_FORMAT(pcmd, x) \tSET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)/* (x<<(unsigned int)0) */\n#define FIFO_FUN_FORMAT(pcmd, x) \t\t\tSET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)/* (x<<(unsigned int)5) */\n#define FIFO_RW_FORMAT(pcmd, x) \t\t\tSET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)/* (x<<(unsigned int)7) */\n\n\n/* get status dword0 */\n#define GET_STATUS_PUB_PAGE_NUM(status)\t\tLE_BITS_TO_4BYTE(status, 24, 8)\n#define GET_STATUS_HI_PAGE_NUM(status)\t\tLE_BITS_TO_4BYTE(status, 18, 6)\n#define GET_STATUS_MID_PAGE_NUM(status)\t\tLE_BITS_TO_4BYTE(status, 12, 6)\n#define GET_STATUS_LOW_PAGE_NUM(status)\t\tLE_BITS_TO_4BYTE(status, 6, 6)\n#define GET_STATUS_HISR_HI6BIT(status)\t\t\tLE_BITS_TO_4BYTE(status, 0, 6)\n\n/* get status dword1 */\n#define GET_STATUS_HISR_MID8BIT(status)\t\tLE_BITS_TO_4BYTE(status + 4, 24, 8)\n#define GET_STATUS_HISR_LOW8BIT(status)\t\tLE_BITS_TO_4BYTE(status + 4, 16, 8)\n#define GET_STATUS_ERROR(status)\t\t\t\tLE_BITS_TO_4BYTE(status + 4, 17, 1)\n#define GET_STATUS_INT(status)\t\t\t\tLE_BITS_TO_4BYTE(status + 4, 16, 1)\n#define GET_STATUS_RX_LENGTH(status)\t\t\tLE_BITS_TO_4BYTE(status + 4, 0, 16)\n\n\n#define RXDESC_SIZE\t24\n\n\nstruct spi_more_data {\n\tunsigned long more_data;\n\tunsigned long len;\n};\n\n#ifdef CONFIG_RTL8188E\n\tvoid rtl8188es_set_hal_ops(PADAPTER padapter);\n\t#define set_hal_ops rtl8188es_set_hal_ops\n#endif\nextern void spi_set_chip_endian(PADAPTER padapter);\nextern unsigned int spi_write8_endian(ADAPTER *Adapter, unsigned int addr, unsigned int buf, u32 big);\nextern void spi_set_intf_ops(_adapter *padapter, struct _io_ops *pops);\nextern void spi_set_chip_endian(PADAPTER padapter);\nextern void InitInterrupt8723ASdio(PADAPTER padapter);\nextern void InitSysInterrupt8723ASdio(PADAPTER padapter);\nextern void EnableInterrupt8723ASdio(PADAPTER padapter);\nextern void DisableInterrupt8723ASdio(PADAPTER padapter);\nextern void spi_int_hdl(PADAPTER padapter);\nextern u8 HalQueryTxBufferStatus8723ASdio(PADAPTER padapter);\n#ifdef CONFIG_RTL8723B\n\textern void InitInterrupt8723BSdio(PADAPTER padapter);\n\textern void InitSysInterrupt8723BSdio(PADAPTER padapter);\n\textern void EnableInterrupt8723BSdio(PADAPTER padapter);\n\textern void DisableInterrupt8723BSdio(PADAPTER padapter);\n\textern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_RTL8188E\n\textern void InitInterrupt8188EGspi(PADAPTER padapter);\n\textern void EnableInterrupt8188EGspi(PADAPTER padapter);\n\textern void DisableInterrupt8188EGspi(PADAPTER padapter);\n\textern void UpdateInterruptMask8188EGspi(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);\n\textern u8 HalQueryTxBufferStatus8189EGspi(PADAPTER padapter);\n\textern u8 HalQueryTxOQTBufferStatus8189EGspi(PADAPTER padapter);\n\textern void ClearInterrupt8188EGspi(PADAPTER padapter);\n\textern u8 CheckIPSStatus(PADAPTER padapter);\n#endif /* CONFIG_RTL8188E */\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\n\textern u8 RecvOnePkt(PADAPTER padapter);\n#endif /* CONFIG_WOWLAN */\n\n#endif /* __GSPI_OPS_H__ */\n"
  },
  {
    "path": "include/gspi_ops_linux.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __SDIO_OPS_LINUX_H__\n#define __SDIO_OPS_LINUX_H__\n\n#endif\n"
  },
  {
    "path": "include/gspi_osintf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __SDIO_OSINTF_H__\n#define __SDIO_OSINTF_H__\n\n\n#endif\n"
  },
  {
    "path": "include/h2clbk.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n\n#define _H2CLBK_H_\n\n\nvoid _lbk_cmd(PADAPTER Adapter);\n\nvoid _lbk_rsp(PADAPTER Adapter);\n\nvoid _lbk_evt(PADAPTER Adapter);\n\nvoid h2c_event_callback(unsigned char *dev, unsigned char *pbuf);\n"
  },
  {
    "path": "include/hal_btcoex.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HAL_BTCOEX_H__\n#define __HAL_BTCOEX_H__\n\n#include <drv_types.h>\n\n/* Some variables can't get from outsrc BT-Coex,\n * so we need to save here */\ntypedef struct _BT_COEXIST {\n\tu8 bBtExist;\n\tu8 btTotalAntNum;\n\tu8 btChipType;\n\tu8 bInitlized;\n\tu8 btAntisolation;\n} BT_COEXIST, *PBT_COEXIST;\n\nvoid DBG_BT_INFO(u8 *dbgmsg);\n\nvoid hal_btcoex_SetBTCoexist(PADAPTER padapter, u8 bBtExist);\nu8 hal_btcoex_IsBtExist(PADAPTER padapter);\nu8 hal_btcoex_IsBtDisabled(PADAPTER);\nvoid hal_btcoex_SetChipType(PADAPTER padapter, u8 chipType);\nvoid hal_btcoex_SetPgAntNum(PADAPTER padapter, u8 antNum);\n\nu8 hal_btcoex_Initialize(PADAPTER padapter);\nvoid hal_btcoex_PowerOnSetting(PADAPTER padapter);\nvoid hal_btcoex_AntInfoSetting(PADAPTER padapter);\nvoid hal_btcoex_PowerOffSetting(PADAPTER padapter);\nvoid hal_btcoex_PreLoadFirmware(PADAPTER padapter);\nvoid hal_btcoex_InitHwConfig(PADAPTER padapter, u8 bWifiOnly);\n\nvoid hal_btcoex_IpsNotify(PADAPTER padapter, u8 type);\nvoid hal_btcoex_LpsNotify(PADAPTER padapter, u8 type);\nvoid hal_btcoex_ScanNotify(PADAPTER padapter, u8 type);\nvoid hal_btcoex_ConnectNotify(PADAPTER padapter, u8 action);\nvoid hal_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus);\nvoid hal_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType);\nvoid hal_btcoex_IQKNotify(PADAPTER padapter, u8 state);\nvoid hal_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf);\nvoid hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf);\nvoid hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state);\nvoid hal_btcoex_HaltNotify(PADAPTER padapter, u8 do_halt);\nvoid hal_btcoex_SwitchBtTRxMask(PADAPTER padapter);\n\nvoid hal_btcoex_Hanlder(PADAPTER padapter);\n\ns32 hal_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter);\ns32 hal_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter);\nu32 hal_btcoex_GetAMPDUSize(PADAPTER padapter);\nvoid hal_btcoex_SetManualControl(PADAPTER padapter, u8 bmanual);\nu8 hal_btcoex_1Ant(PADAPTER padapter);\nu8 hal_btcoex_IsBtControlLps(PADAPTER);\nu8 hal_btcoex_IsLpsOn(PADAPTER);\nu8 hal_btcoex_RpwmVal(PADAPTER);\nu8 hal_btcoex_LpsVal(PADAPTER);\nu32 hal_btcoex_GetRaMask(PADAPTER);\nu8 hal_btcoex_query_reduced_wl_pwr_lvl(PADAPTER padapter);\nvoid hal_btcoex_set_reduced_wl_pwr_lvl(PADAPTER padapter, u8 val);\nvoid hal_btcoex_do_reduce_wl_pwr_lvl(PADAPTER padapter);\nvoid hal_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen);\nvoid hal_btcoex_DisplayBtCoexInfo(PADAPTER, u8 *pbuf, u32 bufsize);\nvoid hal_btcoex_SetDBG(PADAPTER, u32 *pDbgModule);\nu32 hal_btcoex_GetDBG(PADAPTER, u8 *pStrBuf, u32 bufSize);\nu8 hal_btcoex_IncreaseScanDeviceNum(PADAPTER);\nu8 hal_btcoex_IsBtLinkExist(PADAPTER);\nvoid hal_btcoex_SetBtPatchVersion(PADAPTER, u16 btHciVer, u16 btPatchVer);\nvoid hal_btcoex_SetHciVersion(PADAPTER, u16 hciVersion);\nvoid hal_btcoex_SendScanNotify(PADAPTER, u8 type);\nvoid hal_btcoex_StackUpdateProfileInfo(void);\nvoid hal_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON);\nvoid hal_btcoex_SetAntIsolationType(PADAPTER padapter, u8 anttype);\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\tint hal_btcoex_AntIsolationConfig_ParaFile(PADAPTER\tAdapter, char *pFileName);\n\tint hal_btcoex_ParseAntIsolationConfigFile(PADAPTER Adapter, char\t*buffer);\n#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */\nu16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data);\nu16 hal_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val);\nvoid hal_btcoex_set_rfe_type(u8 type);\nvoid hal_btcoex_switchband_notify(u8 under_scan, u8 band_type);\nvoid hal_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length);\nvoid hal_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id);\nu16 hal_btcoex_btset_testode(PADAPTER padapter, u8 type);\n\n#ifdef CONFIG_RF4CE_COEXIST\nvoid hal_btcoex_set_rf4ce_link_state(u8 state);\nu8 hal_btcoex_get_rf4ce_link_state(void);\n#endif\n\n#ifdef CONFIG_SDIO_HCI\n#include <hal_sdio_coex.h>\t/* sdio multi coex */\n#endif\n\n#endif /* !__HAL_BTCOEX_H__ */\n"
  },
  {
    "path": "include/hal_btcoex_wifionly.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HALBTC_WIFIONLY_H__\n#define __HALBTC_WIFIONLY_H__\n\n#include <drv_types.h>\n#include <hal_data.h>\n\n/* Define the ICs that support wifi only cfg in coex. codes */\n#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)\n#define CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG 1\n#else\n#define CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG 0\n#endif\n\n/* Define the ICs that support hal btc common file structure */\n#if defined(CONFIG_RTL8822C)\n#define CONFIG_BTCOEX_SUPPORT_BTC_CMN 1\n#else\n#define CONFIG_BTCOEX_SUPPORT_BTC_CMN 0\n#endif\n\n#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1)\n\ntypedef enum _WIFIONLY_CHIP_INTERFACE {\n\tWIFIONLY_INTF_UNKNOWN\t= 0,\n\tWIFIONLY_INTF_PCI\t\t= 1,\n\tWIFIONLY_INTF_USB\t\t= 2,\n\tWIFIONLY_INTF_SDIO\t\t= 3,\n\tWIFIONLY_INTF_MAX\n} WIFIONLY_CHIP_INTERFACE, *PWIFIONLY_CHIP_INTERFACE;\n\ntypedef enum _WIFIONLY_CUSTOMER_ID {\n\tCUSTOMER_NORMAL\t\t\t= 0,\n\tCUSTOMER_HP_1\t\t\t= 1\n} WIFIONLY_CUSTOMER_ID, *PWIFIONLY_CUSTOMER_ID;\n\nstruct wifi_only_haldata {\n\tu16\t\tcustomer_id;\n\tu8\t\tefuse_pg_antnum;\n\tu8\t\tefuse_pg_antpath;\n\tu8\t\trfe_type;\n\tu8\t\tant_div_cfg;\n};\n\nstruct wifi_only_cfg {\n\tvoid *Adapter;\n\tstruct wifi_only_haldata\thaldata_info;\n\tWIFIONLY_CHIP_INTERFACE\tchip_interface;\n};\n\nvoid halwifionly_write1byte(void *pwifionlyContext, u32 RegAddr, u8 Data);\nvoid halwifionly_write2byte(void *pwifionlyContext, u32 RegAddr, u16 Data);\nvoid halwifionly_write4byte(void *pwifionlyContext, u32 RegAddr, u32 Data);\nu8 halwifionly_read1byte(void *pwifionlyContext, u32 RegAddr);\nu16 halwifionly_read2byte(void *pwifionlyContext, u32 RegAddr);\nu32 halwifionly_read4byte(void *pwifionlyContext, u32 RegAddr);\nvoid halwifionly_bitmaskwrite1byte(void *pwifionlyContext, u32 regAddr, u8 bitMask, u8 data);\nvoid halwifionly_phy_set_rf_reg(void *pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);\nvoid halwifionly_phy_set_bb_reg(void *pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data);\nvoid hal_btcoex_wifionly_switchband_notify(PADAPTER padapter);\nvoid hal_btcoex_wifionly_scan_notify(PADAPTER padapter);\nvoid hal_btcoex_wifionly_connect_notify(PADAPTER padapter);\nvoid hal_btcoex_wifionly_hw_config(PADAPTER padapter);\nvoid hal_btcoex_wifionly_initlizevariables(PADAPTER padapter);\nvoid hal_btcoex_wifionly_AntInfoSetting(PADAPTER padapter);\n#else\n#define hal_btcoex_wifionly_switchband_notify(padapter)\n#define hal_btcoex_wifionly_scan_notify(padapter)\n#define hal_btcoex_wifionly_connect_notify(padapter)\n#define hal_btcoex_wifionly_hw_config(padapter)\n#define hal_btcoex_wifionly_initlizevariables(padapter)\n#define hal_btcoex_wifionly_AntInfoSetting(padapter)\n#endif\n\n#endif\n"
  },
  {
    "path": "include/hal_com.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HAL_COMMON_H__\n#define __HAL_COMMON_H__\n\n#include \"HalVerDef.h\"\n#include \"hal_pg.h\"\n#include \"hal_phy.h\"\n#include \"hal_phy_reg.h\"\n#include \"hal_com_reg.h\"\n#include \"hal_com_phycfg.h\"\n#include \"../hal/hal_com_c2h.h\"\n\n/*------------------------------ Tx Desc definition Macro ------------------------*/\n/* #pragma mark -- Tx Desc related definition. -- */\n/* ----------------------------------------------------------------------------\n * -----------------------------------------------------------\n *\tRate\n * -----------------------------------------------------------\n * CCK Rates, TxHT = 0 */\n#define DESC_RATE1M\t\t\t\t\t0x00\n#define DESC_RATE2M\t\t\t\t\t0x01\n#define DESC_RATE5_5M\t\t\t\t0x02\n#define DESC_RATE11M\t\t\t\t0x03\n\n/* OFDM Rates, TxHT = 0 */\n#define DESC_RATE6M\t\t\t\t\t0x04\n#define DESC_RATE9M\t\t\t\t\t0x05\n#define DESC_RATE12M\t\t\t\t0x06\n#define DESC_RATE18M\t\t\t\t0x07\n#define DESC_RATE24M\t\t\t\t0x08\n#define DESC_RATE36M\t\t\t\t0x09\n#define DESC_RATE48M\t\t\t\t0x0a\n#define DESC_RATE54M\t\t\t\t0x0b\n\n/* MCS Rates, TxHT = 1 */\n#define DESC_RATEMCS0\t\t\t\t0x0c\n#define DESC_RATEMCS1\t\t\t\t0x0d\n#define DESC_RATEMCS2\t\t\t\t0x0e\n#define DESC_RATEMCS3\t\t\t\t0x0f\n#define DESC_RATEMCS4\t\t\t\t0x10\n#define DESC_RATEMCS5\t\t\t\t0x11\n#define DESC_RATEMCS6\t\t\t\t0x12\n#define DESC_RATEMCS7\t\t\t\t0x13\n#define DESC_RATEMCS8\t\t\t\t0x14\n#define DESC_RATEMCS9\t\t\t\t0x15\n#define DESC_RATEMCS10\t\t\t\t0x16\n#define DESC_RATEMCS11\t\t\t\t0x17\n#define DESC_RATEMCS12\t\t\t\t0x18\n#define DESC_RATEMCS13\t\t\t\t0x19\n#define DESC_RATEMCS14\t\t\t\t0x1a\n#define DESC_RATEMCS15\t\t\t\t0x1b\n#define DESC_RATEMCS16\t\t\t\t0x1C\n#define DESC_RATEMCS17\t\t\t\t0x1D\n#define DESC_RATEMCS18\t\t\t\t0x1E\n#define DESC_RATEMCS19\t\t\t\t0x1F\n#define DESC_RATEMCS20\t\t\t\t0x20\n#define DESC_RATEMCS21\t\t\t\t0x21\n#define DESC_RATEMCS22\t\t\t\t0x22\n#define DESC_RATEMCS23\t\t\t\t0x23\n#define DESC_RATEMCS24\t\t\t\t0x24\n#define DESC_RATEMCS25\t\t\t\t0x25\n#define DESC_RATEMCS26\t\t\t\t0x26\n#define DESC_RATEMCS27\t\t\t\t0x27\n#define DESC_RATEMCS28\t\t\t\t0x28\n#define DESC_RATEMCS29\t\t\t\t0x29\n#define DESC_RATEMCS30\t\t\t\t0x2A\n#define DESC_RATEMCS31\t\t\t\t0x2B\n#define DESC_RATEVHTSS1MCS0\t\t0x2C\n#define DESC_RATEVHTSS1MCS1\t\t0x2D\n#define DESC_RATEVHTSS1MCS2\t\t0x2E\n#define DESC_RATEVHTSS1MCS3\t\t0x2F\n#define DESC_RATEVHTSS1MCS4\t\t0x30\n#define DESC_RATEVHTSS1MCS5\t\t0x31\n#define DESC_RATEVHTSS1MCS6\t\t0x32\n#define DESC_RATEVHTSS1MCS7\t\t0x33\n#define DESC_RATEVHTSS1MCS8\t\t0x34\n#define DESC_RATEVHTSS1MCS9\t\t0x35\n#define DESC_RATEVHTSS2MCS0\t\t0x36\n#define DESC_RATEVHTSS2MCS1\t\t0x37\n#define DESC_RATEVHTSS2MCS2\t\t0x38\n#define DESC_RATEVHTSS2MCS3\t\t0x39\n#define DESC_RATEVHTSS2MCS4\t\t0x3A\n#define DESC_RATEVHTSS2MCS5\t\t0x3B\n#define DESC_RATEVHTSS2MCS6\t\t0x3C\n#define DESC_RATEVHTSS2MCS7\t\t0x3D\n#define DESC_RATEVHTSS2MCS8\t\t0x3E\n#define DESC_RATEVHTSS2MCS9\t\t0x3F\n#define DESC_RATEVHTSS3MCS0\t\t0x40\n#define DESC_RATEVHTSS3MCS1\t\t0x41\n#define DESC_RATEVHTSS3MCS2\t\t0x42\n#define DESC_RATEVHTSS3MCS3\t\t0x43\n#define DESC_RATEVHTSS3MCS4\t\t0x44\n#define DESC_RATEVHTSS3MCS5\t\t0x45\n#define DESC_RATEVHTSS3MCS6\t\t0x46\n#define DESC_RATEVHTSS3MCS7\t\t0x47\n#define DESC_RATEVHTSS3MCS8\t\t0x48\n#define DESC_RATEVHTSS3MCS9\t\t0x49\n#define DESC_RATEVHTSS4MCS0\t\t0x4A\n#define DESC_RATEVHTSS4MCS1\t\t0x4B\n#define DESC_RATEVHTSS4MCS2\t\t0x4C\n#define DESC_RATEVHTSS4MCS3\t\t0x4D\n#define DESC_RATEVHTSS4MCS4\t\t0x4E\n#define DESC_RATEVHTSS4MCS5\t\t0x4F\n#define DESC_RATEVHTSS4MCS6\t\t0x50\n#define DESC_RATEVHTSS4MCS7\t\t0x51\n#define DESC_RATEVHTSS4MCS8\t\t0x52\n#define DESC_RATEVHTSS4MCS9\t\t0x53\n\n#define HDATA_RATE(rate)\\\n\t(rate == DESC_RATE1M) ? \"CCK_1M\" :\\\n\t(rate == DESC_RATE2M) ? \"CCK_2M\" :\\\n\t(rate == DESC_RATE5_5M) ? \"CCK5_5M\" :\\\n\t(rate == DESC_RATE11M) ? \"CCK_11M\" :\\\n\t(rate == DESC_RATE6M) ? \"OFDM_6M\" :\\\n\t(rate == DESC_RATE9M) ? \"OFDM_9M\" :\\\n\t(rate == DESC_RATE12M) ? \"OFDM_12M\" :\\\n\t(rate == DESC_RATE18M) ? \"OFDM_18M\" :\\\n\t(rate == DESC_RATE24M) ? \"OFDM_24M\" :\\\n\t(rate == DESC_RATE36M) ? \"OFDM_36M\" :\\\n\t(rate == DESC_RATE48M) ? \"OFDM_48M\" :\\\n\t(rate == DESC_RATE54M) ? \"OFDM_54M\" :\\\n\t(rate == DESC_RATEMCS0) ? \"MCS0\" :\\\n\t(rate == DESC_RATEMCS1) ? \"MCS1\" :\\\n\t(rate == DESC_RATEMCS2) ? \"MCS2\" :\\\n\t(rate == DESC_RATEMCS3) ? \"MCS3\" :\\\n\t(rate == DESC_RATEMCS4) ? \"MCS4\" :\\\n\t(rate == DESC_RATEMCS5) ? \"MCS5\" :\\\n\t(rate == DESC_RATEMCS6) ? \"MCS6\" :\\\n\t(rate == DESC_RATEMCS7) ? \"MCS7\" :\\\n\t(rate == DESC_RATEMCS8) ? \"MCS8\" :\\\n\t(rate == DESC_RATEMCS9) ? \"MCS9\" :\\\n\t(rate == DESC_RATEMCS10) ? \"MCS10\" :\\\n\t(rate == DESC_RATEMCS11) ? \"MCS11\" :\\\n\t(rate == DESC_RATEMCS12) ? \"MCS12\" :\\\n\t(rate == DESC_RATEMCS13) ? \"MCS13\" :\\\n\t(rate == DESC_RATEMCS14) ? \"MCS14\" :\\\n\t(rate == DESC_RATEMCS15) ? \"MCS15\" :\\\n\t(rate == DESC_RATEMCS16) ? \"MCS16\" :\\\n\t(rate == DESC_RATEMCS17) ? \"MCS17\" :\\\n\t(rate == DESC_RATEMCS18) ? \"MCS18\" :\\\n\t(rate == DESC_RATEMCS19) ? \"MCS19\" :\\\n\t(rate == DESC_RATEMCS20) ? \"MCS20\" :\\\n\t(rate == DESC_RATEMCS21) ? \"MCS21\" :\\\n\t(rate == DESC_RATEMCS22) ? \"MCS22\" :\\\n\t(rate == DESC_RATEMCS23) ? \"MCS23\" :\\\n\t(rate == DESC_RATEVHTSS1MCS0) ? \"VHTSS1MCS0\" :\\\n\t(rate == DESC_RATEVHTSS1MCS1) ? \"VHTSS1MCS1\" :\\\n\t(rate == DESC_RATEVHTSS1MCS2) ? \"VHTSS1MCS2\" :\\\n\t(rate == DESC_RATEVHTSS1MCS3) ? \"VHTSS1MCS3\" :\\\n\t(rate == DESC_RATEVHTSS1MCS4) ? \"VHTSS1MCS4\" :\\\n\t(rate == DESC_RATEVHTSS1MCS5) ? \"VHTSS1MCS5\" :\\\n\t(rate == DESC_RATEVHTSS1MCS6) ? \"VHTSS1MCS6\" :\\\n\t(rate == DESC_RATEVHTSS1MCS7) ? \"VHTSS1MCS7\" :\\\n\t(rate == DESC_RATEVHTSS1MCS8) ? \"VHTSS1MCS8\" :\\\n\t(rate == DESC_RATEVHTSS1MCS9) ? \"VHTSS1MCS9\" :\\\n\t(rate == DESC_RATEVHTSS2MCS0) ? \"VHTSS2MCS0\" :\\\n\t(rate == DESC_RATEVHTSS2MCS1) ? \"VHTSS2MCS1\" :\\\n\t(rate == DESC_RATEVHTSS2MCS2) ? \"VHTSS2MCS2\" :\\\n\t(rate == DESC_RATEVHTSS2MCS3) ? \"VHTSS2MCS3\" :\\\n\t(rate == DESC_RATEVHTSS2MCS4) ? \"VHTSS2MCS4\" :\\\n\t(rate == DESC_RATEVHTSS2MCS5) ? \"VHTSS2MCS5\" :\\\n\t(rate == DESC_RATEVHTSS2MCS6) ? \"VHTSS2MCS6\" :\\\n\t(rate == DESC_RATEVHTSS2MCS7) ? \"VHTSS2MCS7\" :\\\n\t(rate == DESC_RATEVHTSS2MCS8) ? \"VHTSS2MCS8\" :\\\n\t(rate == DESC_RATEVHTSS2MCS9) ? \"VHTSS2MCS9\" :\\\n\t(rate == DESC_RATEVHTSS3MCS0) ? \"VHTSS3MCS0\" :\\\n\t(rate == DESC_RATEVHTSS3MCS1) ? \"VHTSS3MCS1\" :\\\n\t(rate == DESC_RATEVHTSS3MCS2) ? \"VHTSS3MCS2\" :\\\n\t(rate == DESC_RATEVHTSS3MCS3) ? \"VHTSS3MCS3\" :\\\n\t(rate == DESC_RATEVHTSS3MCS4) ? \"VHTSS3MCS4\" :\\\n\t(rate == DESC_RATEVHTSS3MCS5) ? \"VHTSS3MCS5\" :\\\n\t(rate == DESC_RATEVHTSS3MCS6) ? \"VHTSS3MCS6\" :\\\n\t(rate == DESC_RATEVHTSS3MCS7) ? \"VHTSS3MCS7\" :\\\n\t(rate == DESC_RATEVHTSS3MCS8) ? \"VHTSS3MCS8\" :\\\n\t(rate == DESC_RATEVHTSS3MCS9) ? \"VHTSS3MCS9\" : \"UNKNOWN\"\n\nenum {\n\tUP_LINK,\n\tDOWN_LINK,\n};\ntypedef enum _RT_MEDIA_STATUS {\n\tRT_MEDIA_DISCONNECT = 0,\n\tRT_MEDIA_CONNECT       = 1\n} RT_MEDIA_STATUS;\n\n#define MAX_DLFW_PAGE_SIZE\t\t\t4096\t/* @ page : 4k bytes */\ntypedef enum _FIRMWARE_SOURCE {\n\tFW_SOURCE_IMG_FILE = 0,\n\tFW_SOURCE_HEADER_FILE = 1,\t\t/* from header file */\n} FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;\n\ntypedef enum _CH_SW_USE_CASE {\n\tCH_SW_USE_CASE_TDLS\t\t= 0,\n\tCH_SW_USE_CASE_MCC\t\t= 1\n} CH_SW_USE_CASE;\n\ntypedef enum _WAKEUP_REASON{\n\tRX_PAIRWISEKEY\t\t\t\t\t= 0x01,\n\tRX_GTK\t\t\t\t\t\t\t= 0x02,\n\tRX_FOURWAY_HANDSHAKE\t\t\t= 0x03,\n\tRX_DISASSOC\t\t\t\t\t\t= 0x04,\n\tRX_DEAUTH\t\t\t\t\t\t= 0x08,\n\tRX_ARP_REQUEST\t\t\t\t\t= 0x09,\n\tFW_DECISION_DISCONNECT\t\t\t= 0x10,\n\tRX_MAGIC_PKT\t\t\t\t\t= 0x21,\n\tRX_UNICAST_PKT\t\t\t\t\t= 0x22,\n\tRX_PATTERN_PKT\t\t\t\t\t= 0x23,\n\tRTD3_SSID_MATCH\t\t\t\t\t= 0x24,\n\tRX_REALWOW_V2_WAKEUP_PKT\t\t= 0x30,\n\tRX_REALWOW_V2_ACK_LOST\t\t\t= 0x31,\n\tENABLE_FAIL_DMA_IDLE\t\t\t= 0x40,\n\tENABLE_FAIL_DMA_PAUSE\t\t\t= 0x41,\n\tRTIME_FAIL_DMA_IDLE\t\t\t\t= 0x42,\n\tRTIME_FAIL_DMA_PAUSE\t\t\t= 0x43,\n\tRX_PNO\t\t\t\t\t\t\t= 0x55,\n\tAP_OFFLOAD_WAKEUP\t\t\t\t= 0x66,\n\tCLK_32K_UNLOCK\t\t\t\t\t= 0xFD,\n\tCLK_32K_LOCK\t\t\t\t\t= 0xFE\n}WAKEUP_REASON;\n\n/*\n * Queue Select Value in TxDesc\n *   */\n#define QSLT_BK\t\t\t\t\t\t\t0x2/* 0x01 */\n#define QSLT_BE\t\t\t\t\t\t\t0x0\n#define QSLT_VI\t\t\t\t\t\t\t0x5/* 0x4 */\n#define QSLT_VO\t\t\t\t\t\t\t0x7/* 0x6 */\n#define QSLT_BEACON\t\t\t\t\t\t0x10\n#define QSLT_HIGH\t\t\t\t\t\t0x11\n#define QSLT_MGNT\t\t\t\t\t\t0x12\n#define QSLT_CMD\t\t\t\t\t\t0x13\n\n/* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.\n * #define MAX_TX_QUEUE\t\t9 */\n\n#define TX_SELE_HQ\t\t\tBIT(0)\t\t/* High Queue */\n#define TX_SELE_LQ\t\t\tBIT(1)\t\t/* Low Queue */\n#define TX_SELE_NQ\t\t\tBIT(2)\t\t/* Normal Queue */\n#define TX_SELE_EQ\t\t\tBIT(3)\t\t/* Extern Queue */\n\n#define PageNum_128(_Len)\t\t(u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))\n#define PageNum_256(_Len)\t\t(u32)(((_Len)>>8) + ((_Len) & 0xFF ? 1 : 0))\n#define PageNum_512(_Len)\t\t(u32)(((_Len)>>9) + ((_Len) & 0x1FF ? 1 : 0))\n#define PageNum(_Len, _Size)\t\t(u32)(((_Len)/(_Size)) + ((_Len)&((_Size) - 1) ? 1 : 0))\n\nstruct dbg_rx_counter {\n\tu32\trx_pkt_ok;\n\tu32\trx_pkt_crc_error;\n\tu32\trx_pkt_drop;\n\tu32\trx_ofdm_fa;\n\tu32\trx_cck_fa;\n\tu32\trx_ht_fa;\n};\n\nu8 rtw_hal_get_port(_adapter *adapter);\n\n#ifdef CONFIG_MBSSID_CAM\n\t#define DBG_MBID_CAM_DUMP\n\n\tvoid rtw_mbid_cam_init(struct dvobj_priv *dvobj);\n\tvoid rtw_mbid_cam_deinit(struct dvobj_priv *dvobj);\n\tvoid rtw_mbid_cam_reset(_adapter *adapter);\n\tu8 rtw_get_max_mbid_cam_id(_adapter *adapter);\n\tu8 rtw_get_mbid_cam_entry_num(_adapter *adapter);\n\tint rtw_mbid_cam_cache_dump(void *sel, const char *fun_name , _adapter *adapter);\n\tint rtw_mbid_cam_dump(void *sel, const char *fun_name, _adapter *adapter);\n\tvoid rtw_mi_set_mbid_cam(_adapter *adapter);\n\tu8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr);\n\tvoid rtw_ap_set_mbid_num(_adapter *adapter, u8 ap_num);\n\tvoid rtw_mbid_cam_enable(_adapter *adapter);\n#endif\n\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\tvoid rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr);\n\tvoid rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr);\n\t#ifdef CONFIG_SWTIMER_BASED_TXBCN\n\tu16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval);\n\t#endif\n\tvoid hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode);\n#endif\n\nvoid rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter);\nvoid rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter);\nvoid rtw_reset_mac_rx_counters(_adapter *padapter);\nvoid rtw_reset_phy_rx_counters(_adapter *padapter);\nvoid rtw_reset_phy_trx_ok_counters(_adapter *padapter);\n\n#ifdef DBG_RX_COUNTER_DUMP\n\t#define DUMP_DRV_RX_COUNTER\tBIT0\n\t#define DUMP_MAC_RX_COUNTER\tBIT1\n\t#define DUMP_PHY_RX_COUNTER\tBIT2\n\t#define DUMP_DRV_TRX_COUNTER_DATA\tBIT3\n\n\tvoid rtw_dump_phy_rxcnts_preprocess(_adapter *padapter, u8 rx_cnt_mode);\n\tvoid rtw_dump_rx_counters(_adapter *padapter);\n#endif\n\nvoid dump_chip_info(HAL_VERSION\tChipVersion);\nvoid rtw_hal_config_rftype(PADAPTER  padapter);\n\n#define BAND_CAP_2G\t\t\tBIT0\n#define BAND_CAP_5G\t\t\tBIT1\n#define BAND_CAP_BIT_NUM\t2\n\n#define BW_CAP_5M\t\tBIT0\n#define BW_CAP_10M\t\tBIT1\n#define BW_CAP_20M\t\tBIT2\n#define BW_CAP_40M\t\tBIT3\n#define BW_CAP_80M\t\tBIT4\n#define BW_CAP_160M\t\tBIT5\n#define BW_CAP_80_80M\tBIT6\n#define BW_CAP_BIT_NUM\t7\n\n#define PROTO_CAP_11B\t\tBIT0\n#define PROTO_CAP_11G\t\tBIT1\n#define PROTO_CAP_11N\t\tBIT2\n#define PROTO_CAP_11AC\t\tBIT3\n#define PROTO_CAP_BIT_NUM\t4\n\n#define WL_FUNC_P2P\t\t\tBIT0\n#define WL_FUNC_MIRACAST\tBIT1\n#define WL_FUNC_TDLS\t\tBIT2\n#define WL_FUNC_FTM\t\t\tBIT3\n#define WL_FUNC_BIT_NUM\t\t4\n\n#define TBTT_PROHIBIT_SETUP_TIME 0x04 /* 128us, unit is 32us */\n#define TBTT_PROHIBIT_HOLD_TIME 0x80 /* 4ms, unit is 32us*/\n#define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64 /* 3.2ms unit is 32us*/\n\nint hal_spec_init(_adapter *adapter);\nvoid dump_hal_spec(void *sel, _adapter *adapter);\n\nbool hal_chk_band_cap(_adapter *adapter, u8 cap);\nbool hal_chk_bw_cap(_adapter *adapter, u8 cap);\nbool hal_chk_proto_cap(_adapter *adapter, u8 cap);\nbool hal_is_band_support(_adapter *adapter, u8 band);\nbool hal_is_bw_support(_adapter *adapter, u8 bw);\nbool hal_is_wireless_mode_support(_adapter *adapter, u8 mode);\nbool hal_is_mimo_support(_adapter *adapter);\nu8 hal_largest_bw(_adapter *adapter, u8 in_bw);\n\nbool hal_chk_wl_func(_adapter *adapter, u8 func);\n\nvoid hal_com_config_channel_plan(\n\t\tPADAPTER padapter,\n\t\tchar *hw_alpha2,\n\t\tu8 hw_chplan,\n\t\tchar *sw_alpha2,\n\t\tu8 sw_chplan,\n\t\tu8 def_chplan,\n\t\tBOOLEAN AutoLoadFail\n);\n\nint hal_config_macaddr(_adapter *adapter, bool autoload_fail);\n#ifdef RTW_HALMAC\nvoid rtw_hal_hw_port_enable(_adapter *adapter);\nvoid rtw_hal_hw_port_disable(_adapter *adapter);\n#endif\n\nBOOLEAN\nHAL_IsLegalChannel(\n\t\tPADAPTER\tAdapter,\n\t\tu32\t\t\tChannel\n);\n\nu8\tMRateToHwRate(u8 rate);\n\nu8\thw_rate_to_m_rate(u8 rate);\n\nvoid\tHalSetBrateCfg(\n\t\tPADAPTER\t\tAdapter,\n\t\tu8\t\t\t*mBratesOS,\n\t\tu16\t\t\t*pBrateCfg);\n\nBOOLEAN\nHal_MappingOutPipe(\n\t\tPADAPTER\tpAdapter,\n\t\tu8\t\tNumOutPipe\n);\n\nvoid rtw_dump_fw_info(void *sel, _adapter *adapter);\nvoid rtw_restore_hw_port_cfg(_adapter *adapter);\nvoid rtw_mi_set_mac_addr(_adapter *adapter);/*set mac addr when hal_init for all iface*/\nvoid rtw_hal_dump_macaddr(void *sel, _adapter *adapter);\n\nvoid rtw_init_hal_com_default_value(PADAPTER Adapter);\n\n#ifdef CONFIG_FW_C2H_REG\nvoid c2h_evt_clear(_adapter *adapter);\ns32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf);\n#endif\n\n#ifdef CONFIG_FW_C2H_PKT\nvoid rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len);\nvoid rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len);\n#endif\n\nu8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type);\n\nvoid rtw_hal_update_sta_wset(_adapter *adapter, struct sta_info *psta);\ns8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta);\ns8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta);\nvoid rtw_hal_update_sta_ra_info(PADAPTER padapter, struct sta_info *psta);\n\n/* access HW only */\nu32 rtw_sec_read_cam(_adapter *adapter, u8 addr);\nvoid rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata);\nvoid rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key);\nvoid rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key);\nvoid rtw_sec_clr_cam_ent(_adapter *adapter, u8 id);\nbool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id);\n\nu8 rtw_hal_rcr_check(_adapter *adapter, u32 check_bit);\n\nu8 rtw_hal_rcr_add(_adapter *adapter, u32 add);\nu8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear);\nvoid rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action);\n\nvoid rtw_iface_enable_tsf_update(_adapter *adapter);\nvoid rtw_iface_disable_tsf_update(_adapter *adapter);\nvoid rtw_hal_periodic_tsf_update_chk(_adapter *adapter);\nvoid rtw_hal_periodic_tsf_update_end_timer_hdl(void *ctx);\n\n#if CONFIG_TX_AC_LIFETIME\n#define TX_ACLT_CONF_DEFAULT\t0\n#define TX_ACLT_CONF_AP_M2U\t\t1\n#define TX_ACLT_CONF_MESH\t\t2\n#define TX_ACLT_CONF_NUM\t\t3\n\nextern const char *const _tx_aclt_conf_str[];\n#define tx_aclt_conf_str(conf) (((conf) >= TX_ACLT_CONF_NUM) ? _tx_aclt_conf_str[TX_ACLT_CONF_NUM] : _tx_aclt_conf_str[(conf)])\n\nstruct tx_aclt_conf_t {\n\tu8 en;\n\tu32 vo_vi;\n\tu32 be_bk;\n};\n\nvoid dump_tx_aclt_force_val(void *sel, struct dvobj_priv *dvobj);\nvoid rtw_hal_set_tx_aclt_force_val(_adapter *adapter, struct tx_aclt_conf_t *input, u8 arg_num);\nvoid dump_tx_aclt_confs(void *sel, struct dvobj_priv *dvobj);\nvoid rtw_hal_set_tx_aclt_conf(_adapter *adapter, u8 conf_idx, struct tx_aclt_conf_t *input, u8 arg_num);\nvoid rtw_hal_update_tx_aclt(_adapter *adapter);\n#endif\n\nvoid hw_var_port_switch(_adapter *adapter);\nvoid rtw_var_set_basic_rate(PADAPTER padapter, u8 *val);\nu8 SetHwReg(PADAPTER padapter, u8 variable, u8 *val);\nvoid GetHwReg(PADAPTER padapter, u8 variable, u8 *val);\nvoid rtw_hal_check_rxfifo_full(_adapter *adapter);\nvoid rtw_hal_reqtxrpt(_adapter *padapter, u8 macid);\n\nu8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);\nu8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);\n\nBOOLEAN\neqNByte(\n\tu8\t*str1,\n\tu8\t*str2,\n\tu32\tnum\n);\n\nu32\nMapCharToHexDigit(\n\t\tchar\tchTmp\n);\n\nBOOLEAN\nGetHexValueFromString(\n\t\t\tchar\t\t*szStr,\n\t\t\tu32\t\t\t*pu4bVal,\n\t\t\tu32\t\t\t*pu4bMove\n);\n\nBOOLEAN\nGetFractionValueFromString(\n\t\t\tchar\t*szStr,\n\t\t\tu8\t\t*pInteger,\n\t\t\tu8\t\t*pFraction,\n\t\t\tu32\t\t*pu4bMove\n);\n\nBOOLEAN\nIsCommentString(\n\t\t\tchar\t\t*szStr\n);\n\nBOOLEAN\nParseQualifiedString(\n\t\tchar *In,\n\t\tu32 *Start,\n\t\tchar *Out,\n\t\tchar LeftQualifier,\n\t\tchar RightQualifier\n);\n\nBOOLEAN\nGetU1ByteIntegerFromStringInDecimal(\n\t\t\tchar *Str,\n\t\t\tu8 *pInt\n);\n\nBOOLEAN\nisAllSpaceOrTab(\n\tu8\t*data,\n\tu8\tsize\n);\n\nvoid linked_info_dump(_adapter *padapter, u8 benable);\n#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA\n\tvoid rtw_get_raw_rssi_info(void *sel, _adapter *padapter);\n\tvoid rtw_dump_raw_rssi_info(_adapter *padapter, void *sel);\n#endif\n\n#ifdef DBG_RX_DFRAME_RAW_DATA\n\tvoid rtw_dump_rx_dframe_info(_adapter *padapter, void *sel);\n#endif\nvoid rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe);\n#define\t\tHWSET_MAX_SIZE\t\t\t1024\n\n#ifdef CONFIG_EFUSE_CONFIG_FILE\nu32 Hal_readPGDataFromConfigFile(PADAPTER padapter);\nu32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr);\n#endif /* CONFIG_EFUSE_CONFIG_FILE */\n\nint hal_efuse_macaddr_offset(_adapter *adapter);\nint Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr);\nvoid rtw_dump_cur_efuse(PADAPTER padapter);\n\n#ifdef CONFIG_RF_POWER_TRIM\n\tvoid rtw_bb_rf_gain_offset(_adapter *padapter);\n#endif /*CONFIG_RF_POWER_TRIM*/\n\nvoid dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer);\nu8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qsel);\n\nu8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta);\nu8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta);\n#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA\nvoid rtw_hal_set_pathb_phase(_adapter *adapter, u8 phase_idx);\n#endif\nvoid rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished);\nu8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter);\n\n#ifdef CONFIG_TSF_RESET_OFFLOAD\nint rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port);\n#endif\nu64 rtw_hal_get_tsftr_by_port(_adapter *adapter, u8 port);\n\n#ifdef CONFIG_TDLS\n\t#ifdef CONFIG_TDLS_CH_SW\n\t\ts32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode);\n\t#endif\n#endif\n#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)\ns32 rtw_hal_set_wifi_btc_port_id_cmd(_adapter *adapter);\n#endif\n\n#ifdef CONFIG_GPIO_API\n\tu8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num);\n\tint rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh);\n\tint rtw_hal_config_gpio(_adapter *adapter, u8 gpio_num, bool isOutput);\n\tint rtw_hal_register_gpio_interrupt(_adapter *adapter, int gpio_num, void(*callback)(u8 level));\n\tint rtw_hal_disable_gpio_interrupt(_adapter *adapter, int gpio_num);\n#endif\n\ns8 rtw_hal_ch_sw_iqk_info_search(_adapter *padapter, u8 central_chnl, u8 bw_mode);\nvoid rtw_hal_ch_sw_iqk_info_backup(_adapter *adapter);\nvoid rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case);\n\n#ifdef CONFIG_GPIO_WAKEUP\n\tvoid rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable);\n\tvoid rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval);\n\tvoid rtw_hal_set_input_gpio(_adapter *padapter, u8 index);\n#endif\n\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\textern char *rtw_phy_file_path;\n\textern char rtw_phy_para_file_path[PATH_LENGTH_MAX];\n\t#define GetLineFromBuffer(buffer)   strsep(&buffer, \"\\r\\n\")\n#endif\n\nvoid update_IOT_info(_adapter *padapter);\n#ifdef CONFIG_RTS_FULL_BW\nvoid rtw_set_rts_bw(_adapter *padapter);\n#endif/*CONFIG_RTS_FULL_BW*/\n\nvoid ResumeTxBeacon(_adapter *padapter);\nvoid StopTxBeacon(_adapter *padapter);\n\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\tu8\trtw_hal_antdiv_before_linked(_adapter *padapter);\n\tvoid\trtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);\n#endif\n\n#ifdef DBG_SEC_CAM_MOVE\n\tvoid rtw_hal_move_sta_gk_to_dk(_adapter *adapter);\n\tvoid rtw_hal_read_sta_dk_key(_adapter *adapter, u8 key_id);\n#endif\n\n#ifdef CONFIG_LPS_PG\n#define LPSPG_RSVD_PAGE_SET_MACID(_rsvd_pag, _value)\t\tSET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 0, 8, _value)/*used macid*/\n#define LPSPG_RSVD_PAGE_SET_MBSSCAMID(_rsvd_pag, _value)\tSET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 8, 8, _value)/*used BSSID CAM entry*/\n#define LPSPG_RSVD_PAGE_SET_PMC_NUM(_rsvd_pag, _value)\t\tSET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 16, 8, _value)/*Max used Pattern Match CAM entry*/\n#define LPSPG_RSVD_PAGE_SET_MU_RAID_GID(_rsvd_pag, _value)\tSET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 24, 8, _value)/*Max MU rate table Group ID*/\n#define LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(_rsvd_pag, _value)\tSET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 0, 8, _value)/*used Security CAM entry number*/\n#define LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(_rsvd_pag, _value)\tSET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 8, 8, _value)/*Txbuf used page number for fw offload*/\n#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID1(_rsvd_pag, _value)\tSET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 0, 8, _value)/*used Security CAM entry -1*/\n#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID2(_rsvd_pag, _value)\tSET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 8, 8, _value)/*used Security CAM entry -2*/\n#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID3(_rsvd_pag, _value)\tSET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 16, 8, _value)/*used Security CAM entry -3*/\n#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID4(_rsvd_pag, _value)\tSET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 24, 8, _value)/*used Security CAM entry -4*/\n#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID5(_rsvd_pag, _value)\tSET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 0, 8, _value)/*used Security CAM entry -5*/\n#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID6(_rsvd_pag, _value)\tSET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 8, 8, _value)/*used Security CAM entry -6*/\n#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID7(_rsvd_pag, _value)\tSET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 16, 8, _value)/*used Security CAM entry -7*/\n#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID8(_rsvd_pag, _value)\tSET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 24, 8, _value)/*used Security CAM entry -8*/\nenum lps_pg_hdl_id {\n\tLPS_PG_INFO_CFG = 0,\n\tLPS_PG_REDLEMEM,\n\tLPS_PG_PHYDM_DIS,\n\tLPS_PG_PHYDM_EN,\n};\n\nu8 rtw_hal_set_lps_pg_info(_adapter *adapter);\n#endif\n\nint rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, u32 page_num, u8 *buffer, u32 buffer_size);\nvoid rtw_hal_construct_beacon(_adapter *padapter, u8 *pframe, u32 *pLength);\nvoid rtw_hal_construct_NullFunctionData(PADAPTER, u8 *pframe, u32 *pLength,\n\t\t\t\tu8 bQoS, u8 AC, u8 bEosp, u8 bForcePowerSave);\n\n#ifdef CONFIG_WOWLAN\nstruct rtl_wow_pattern {\n\tu16\tcrc;\n\tu8\ttype;\n\tu32\tmask[4];\n};\nvoid rtw_wow_pattern_cam_dump(_adapter *adapter);\n\n#ifdef CONFIG_WOW_PATTERN_HW_CAM\nvoid rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct  rtl_wow_pattern *context);\nvoid rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx);\n#endif\n\nstruct rtw_ndp_info {\n\tu8 enable:1;\n\tu8 check_remote_ip:1; /* Need to Check Sender IP or not */\n\tu8 rsvd:6;\n\tu8 num_of_target_ip; /* Number of Check IP which NA query IP */\n\tu8 target_link_addr[6]; /* DUT's MAC address */\n\tu8 remote_ipv6_addr[16]; /* Just respond IP */\n\tu8 target_ipv6_addr[16]; /* target IP */\n};\n#define REMOTE_INFO_CTRL_SET_VALD_EN(target, _value) \\\n\tSET_BITS_TO_LE_4BYTE(target + 0, 0, 8, _value)\n#define REMOTE_INFO_CTRL_SET_PTK_EN(target, _value) \\\n\tSET_BITS_TO_LE_4BYTE(target + 1, 0, 1, _value)\n#define REMOTE_INFO_CTRL_SET_GTK_EN(target, _value) \\\n\tSET_BITS_TO_LE_4BYTE(target + 1, 1, 1, _value)\n#define REMOTE_INFO_CTRL_SET_GTK_IDX(target, _value) \\\n\tSET_BITS_TO_LE_4BYTE(target + 2, 0, 8, _value)\n#endif /*CONFIG_WOWLAN*/\n\nvoid rtw_dump_phy_cap(void *sel, _adapter *adapter);\nvoid rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num);\n#ifdef CONFIG_SUPPORT_FIFO_DUMP\nvoid rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 fifo_size);\n#endif\n\n#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\ns32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id);\ns32 rtw_set_default_port_id(_adapter *adapter);\ns32 rtw_set_ps_rsvd_page(_adapter *adapter);\n\n#define get_dft_portid(adapter) (adapter_to_dvobj(adapter)->dft.port_id)\n#define get_dft_macid(adapter) (adapter_to_dvobj(adapter)->dft.mac_id)\n\n/*void rtw_search_default_port(_adapter *adapter);*/\n#endif\n\n#ifdef CONFIG_P2P_PS\n#ifdef RTW_HALMAC\nvoid rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state);\n#endif\n#endif\n\n#ifdef RTW_CHANNEL_SWITCH_OFFLOAD\nvoid rtw_hal_switch_chnl_and_set_bw_offload(_adapter *adapter, u8 central_ch, u8 pri_ch_idx, u8 bw);\n#endif\n\ns16 translate_dbm_to_percentage(s16 signal);\n\n#ifdef CONFIG_SUPPORT_MULTI_BCN\nvoid rtw_ap_multi_bcn_cfg(_adapter *adapter);\n#endif\n\n#ifdef CONFIG_SWTIMER_BASED_TXBCN\n#ifdef CONFIG_BCN_RECOVERY\nu8 rtw_ap_bcn_recovery(_adapter *padapter);\n#endif\n#ifdef CONFIG_BCN_XMIT_PROTECT\nu8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms);\n#endif\n#endif /*CONFIG_SWTIMER_BASED_TXBCN*/\n\n#ifdef CONFIG_FW_HANDLE_TXBCN\nvoid rtw_ap_mbid_bcn_en(_adapter *adapter, u8 mbcn_id);\nvoid rtw_ap_mbid_bcn_dis(_adapter *adapter, u8 mbcn_id);\n#endif\n\nvoid rtw_hal_get_rf_path(struct dvobj_priv *d, enum rf_type *type,\n\t\t\t enum bb_path *tx, enum bb_path *rx);\n#ifdef CONFIG_BEAMFORMING\n#ifdef RTW_BEAMFORMING_VERSION_2\nvoid rtw_hal_beamforming_config_csirate(PADAPTER adapter);\n#endif\n#endif\n#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8812A) ||\\\n\tdefined(CONFIG_RTL8192F) || defined(CONFIG_RTL8192E) ||\\\n\tdefined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821A) || \\\n\tdefined(CONFIG_RTL8822C)\nu8 phy_get_current_tx_num(PADAPTER pAdapter, u8 Rate);\n#endif\n\n#ifdef CONFIG_RTL8812A\nu8 * rtw_hal_set_8812a_vendor_ie(_adapter *padapter , u8 *pframe ,uint *frlen );\n#endif\n\n#endif /* __HAL_COMMON_H__ */\n"
  },
  {
    "path": "include/hal_com_h2c.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __COMMON_H2C_H__\n#define __COMMON_H2C_H__\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------\n * ---------------------------------------------------------------------------------------------------------\n * 88e, 8723b, 8812, 8821, 92e use the same FW code base */\nenum h2c_cmd {\n\t/* Common Class: 000 */\n\tH2C_RSVD_PAGE = 0x00,\n\tH2C_MEDIA_STATUS_RPT = 0x01,\n\tH2C_SCAN_ENABLE = 0x02,\n\tH2C_KEEP_ALIVE = 0x03,\n\tH2C_DISCON_DECISION = 0x04,\n\tH2C_PSD_OFFLOAD = 0x05,\n\tH2C_CUSTOMER_STR_REQ = 0x06,\n\tH2C_AP_OFFLOAD = 0x08,\n\tH2C_BCN_RSVDPAGE = 0x09,\n\tH2C_PROBERSP_RSVDPAGE = 0x0A,\n\tH2C_FCS_RSVDPAGE = 0x10,\n\tH2C_FCS_INFO = 0x11,\n\tH2C_AP_WOW_GPIO_CTRL = 0x13,\n#ifdef CONFIG_MCC_MODE\n\tH2C_MCC_RQT_TSF = 0x15,\n\tH2C_MCC_MACID_BITMAP = 0x16,\n\tH2C_MCC_LOCATION = 0x10,\n\tH2C_MCC_CTRL_V2 = 0x17,\n\tH2C_MCC_CTRL = 0x18,\n\tH2C_MCC_TIME_SETTING = 0x19,\n\tH2C_MCC_IQK_PARAM = 0x1A,\n#endif /* CONFIG_MCC_MODE */\n\tH2C_CHNL_SWITCH_OPER_OFFLOAD = 0x1C,\n\tH2C_SINGLE_CHANNELSWITCH_V2 = 0x1D,\n\n\t/* PoweSave Class: 001 */\n\tH2C_SET_PWR_MODE = 0x20,\n\tH2C_PS_TUNING_PARA = 0x21,\n\tH2C_PS_TUNING_PARA2 = 0x22,\n\tH2C_P2P_LPS_PARAM = 0x23,\n\tH2C_P2P_PS_OFFLOAD = 0x24,\n\tH2C_PS_SCAN_ENABLE = 0x25,\n\tH2C_SAP_PS_ = 0x26,\n\tH2C_INACTIVE_PS_ = 0x27, /* Inactive_PS */\n\tH2C_FWLPS_IN_IPS_ = 0x28,\n#ifdef CONFIG_LPS_POFF\n\tH2C_LPS_POFF_CTRL = 0x29,\n\tH2C_LPS_POFF_PARAM = 0x2A,\n#endif\n#ifdef CONFIG_LPS_PG\n\tH2C_LPS_PG_INFO = 0x2B,\n#endif\n\n#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n\tH2C_DEFAULT_PORT_ID = 0x2C,\n#endif\n\t/* Dynamic Mechanism Class: 010 */\n\tH2C_MACID_CFG = 0x40,\n\tH2C_TXBF = 0x41,\n\tH2C_RSSI_SETTING = 0x42,\n\tH2C_AP_REQ_TXRPT = 0x43,\n\tH2C_INIT_RATE_COLLECT = 0x44,\n\tH2C_IQ_CALIBRATION\t= 0x45,\n\n\tH2C_RA_MASK_3SS = 0x46,/* for 8814A */\n\tH2C_RA_PARA_ADJUST = 0x47,/* CONFIG_RA_DBG_CMD */\n\tH2C_DYNAMIC_TX_PATH = 0x48,/* for 8814A */\n\n\tH2C_FW_TRACE_EN = 0x49,\n#ifdef RTW_PER_CMD_SUPPORT_FW\n\tH2C_REQ_PER_RPT = 0x4e,\n#endif\n\t/* BT Class: 011 */\n\tH2C_B_TYPE_TDMA = 0x60,\n\tH2C_BT_INFO = 0x61,\n\tH2C_FORCE_BT_TXPWR = 0x62,\n\tH2C_BT_IGNORE_WLANACT = 0x63,\n\tH2C_DAC_SWING_VALUE = 0x64,\n\tH2C_ANT_SEL_RSV = 0x65,\n\tH2C_WL_OPMODE = 0x66,\n\tH2C_BT_MP_OPER = 0x67,\n\tH2C_BT_CONTROL = 0x68,\n\tH2C_BT_WIFI_CTRL = 0x69,\n\tH2C_BT_FW_PATCH = 0x6A,\n#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)\n\tH2C_BTC_WL_PORT_ID = 0x71,\n#endif\n\t/* WOWLAN Class: 100 */\n\tH2C_WOWLAN = 0x80,\n\tH2C_REMOTE_WAKE_CTRL = 0x81,\n\tH2C_AOAC_GLOBAL_INFO = 0x82,\n\tH2C_AOAC_RSVD_PAGE = 0x83,\n\tH2C_AOAC_RSVD_PAGE2 = 0x84,\n\tH2C_D0_SCAN_OFFLOAD_CTRL = 0x85,\n\tH2C_D0_SCAN_OFFLOAD_INFO = 0x86,\n\tH2C_CHNL_SWITCH_OFFLOAD = 0x87,\n\tH2C_AOAC_RSVDPAGE3 = 0x88,\n\tH2C_P2P_OFFLOAD_RSVD_PAGE = 0x8A,\n\tH2C_P2P_OFFLOAD = 0x8B,\n#ifdef CONFIG_FW_HANDLE_TXBCN\n\tH2C_FW_BCN_OFFLOAD = 0xBA,\n#endif\n\tH2C_RESET_TSF = 0xC0,\n#ifdef CONFIG_FW_CORRECT_BCN\n\tH2C_BCNHWSEQ = 0xC5,\n#endif\n\tH2C_CUSTOMER_STR_W1 = 0xC6,\n\tH2C_CUSTOMER_STR_W2 = 0xC7,\n\tH2C_CUSTOMER_STR_W3 = 0xC8,\n#ifdef DBG_FW_DEBUG_MSG_PKT\n\tH2C_FW_DBG_MSG_PKT = 0xE1,\n#endif /*DBG_FW_DEBUG_MSG_PKT*/\n\tH2C_MAXID,\n};\n\n#define H2C_INACTIVE_PS_LEN\t\t4\n#define H2C_RSVDPAGE_LOC_LEN\t\t5\n#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n#define H2C_DEFAULT_PORT_ID_LEN\t\t2\n#define H2C_MEDIA_STATUS_RPT_LEN\t\t4\n#else\n#define H2C_MEDIA_STATUS_RPT_LEN\t\t3\n#endif\n#define H2C_KEEP_ALIVE_CTRL_LEN\t2\n#define H2C_DISCON_DECISION_LEN\t\t3\n#define H2C_AP_OFFLOAD_LEN\t\t3\n#define H2C_AP_WOW_GPIO_CTRL_LEN\t4\n#define H2C_AP_PS_LEN\t\t\t2\n#define H2C_PWRMODE_LEN\t\t\t7\n#define H2C_PSTUNEPARAM_LEN\t\t\t4\n#define H2C_MACID_CFG_LEN\t\t7\n#define H2C_BTMP_OPER_LEN\t\t\t5\n#define H2C_WOWLAN_LEN\t\t\t7\n#define H2C_REMOTE_WAKE_CTRL_LEN\t3\n#define H2C_AOAC_GLOBAL_INFO_LEN\t2\n#define H2C_AOAC_RSVDPAGE_LOC_LEN\t7\n#define H2C_SCAN_OFFLOAD_CTRL_LEN\t4\n#define H2C_BT_FW_PATCH_LEN\t\t\t6\n#define H2C_RSSI_SETTING_LEN\t\t4\n#define H2C_AP_REQ_TXRPT_LEN\t\t3\n#define H2C_FORCE_BT_TXPWR_LEN\t\t3\n#define H2C_BCN_RSVDPAGE_LEN\t\t5\n#define H2C_PROBERSP_RSVDPAGE_LEN\t5\n#define H2C_P2PRSVDPAGE_LOC_LEN\t5\n#define H2C_P2P_OFFLOAD_LEN\t3\n#ifdef CONFIG_MCC_MODE\n\t#define H2C_MCC_CTRL_LEN\t\t\t7\n#ifdef CONFIG_MCC_MODE_V2\n\t#define H2C_MCC_LOCATION_LEN\t\t7\n#else\n\t#define H2C_MCC_LOCATION_LEN\t\t3\n#endif\n\t#define H2C_MCC_MACID_BITMAP_LEN\t6\n\t#define H2C_MCC_RQT_TSF_LEN\t\t1\n\t#define H2C_MCC_TIME_SETTING_LEN\t\t6\n\t#define H2C_MCC_IQK_PARAM_LEN\t\t7\n#endif /* CONFIG_MCC_MODE */\n#ifdef CONFIG_LPS_PG\n#ifdef CONFIG_RTL8822C\n\t#define H2C_LPS_PG_INFO_LEN\t\t4\n#else\n\t#define H2C_LPS_PG_INFO_LEN\t\t2\n#endif\n\t#define H2C_LPSPG_LEN\t\t\t16\n#endif\n#ifdef CONFIG_LPS_POFF\n\t#define H2C_LPS_POFF_CTRL_LEN\t\t1\n\t#define H2C_LPS_POFF_PARAM_LEN\t\t5\n#endif\n\n#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)\n#define H2C_BTC_WL_PORT_ID_LEN\t1\n#endif\n\n#ifdef DBG_FW_DEBUG_MSG_PKT\n\t#define H2C_FW_DBG_MSG_PKT_LEN\t2\n#endif /*DBG_FW_DEBUG_MSG_PKT*/\n\n#define H2C_SINGLE_CHANNELSWITCH_V2_LEN 2\n\n#define eq_mac_addr(a, b)\t\t\t\t\t\t(((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0)\n#define cp_mac_addr(des, src)\t\t\t\t\t((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5])\n#define cpIpAddr(des, src)\t\t\t\t\t((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3])\n\n\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\n#define FW_WOWLAN_FUN_EN\t\t\t\tBIT(0)\n#define FW_WOWLAN_PATTERN_MATCH\t\t\tBIT(1)\n#define FW_WOWLAN_MAGIC_PKT\t\t\t\tBIT(2)\n#define FW_WOWLAN_UNICAST\t\t\t\tBIT(3)\n#define FW_WOWLAN_ALL_PKT_DROP\t\t\tBIT(4)\n#define FW_WOWLAN_GPIO_ACTIVE\t\t\tBIT(5)\n#define FW_WOWLAN_REKEY_WAKEUP\t\t\tBIT(6)\n#define FW_WOWLAN_DEAUTH_WAKEUP\t\t\tBIT(7)\n\n#define FW_WOWLAN_GPIO_WAKEUP_EN\t\tBIT(0)\n#define FW_FW_PARSE_MAGIC_PKT\t\t\tBIT(1)\n\n#define FW_REMOTE_WAKE_CTRL_EN\t\t\tBIT(0)\n#define FW_REALWOWLAN_EN\t\t\t\tBIT(5)\n\n#define FW_WOWLAN_KEEP_ALIVE_EN\t\t\tBIT(0)\n#define FW_ADOPT_USER\t\t\t\t\tBIT(1)\n#define FW_WOWLAN_KEEP_ALIVE_PKT_TYPE\tBIT(2)\n\n#define FW_REMOTE_WAKE_CTRL_EN\t\t\tBIT(0)\n#define FW_ARP_EN\t\t\t\t\t\tBIT(1)\n#define FW_REALWOWLAN_EN\t\t\t\tBIT(5)\n#define FW_WOW_FW_UNICAST_EN\t\t\tBIT(7)\n\n#define FW_IPS_DISABLE_BBRF\t\tBIT(0)\n#define FW_IPS_WRC\t\t\t\tBIT(1)\n\n#endif /* CONFIG_WOWLAN */\n\n/* _RSVDPAGE_LOC_CMD_0x00 */\n#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n/* _MEDIA_STATUS_RPT_PARM_CMD_0x01 */\n#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))\n#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 1, 1, (__Value))\n#define SET_H2CCMD_MSRRPT_PARM_MIRACAST(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 2, 1, (__Value))\n#define SET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 3, 1, (__Value))\n#define SET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 4, 4, (__Value))\n#define SET_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 1, 0, 8, (__Value))\n#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 2, 0, 8, (__Value))\n#define SET_H2CCMD_MSRRPT_PARM_PORT_NUM(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 3, 0, 3, (__Value))\n\n#define GET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd)\t\tLE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 0, 1)\n#define GET_H2CCMD_MSRRPT_PARM_MIRACAST(__pH2CCmd)\t\tLE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 2, 1)\n#define GET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(__pH2CCmd)\tLE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 3, 1)\n#define GET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 4, 4)\n\n#define H2C_MSR_ROLE_RSVD\t0\n#define H2C_MSR_ROLE_STA\t1\n#define H2C_MSR_ROLE_AP\t\t2\n#define H2C_MSR_ROLE_GC\t\t3\n#define H2C_MSR_ROLE_GO\t\t4\n#define H2C_MSR_ROLE_TDLS\t5\n#define H2C_MSR_ROLE_ADHOC\t6\n#define H2C_MSR_ROLE_MESH\t7\n#define H2C_MSR_ROLE_MAX\t8\n\nextern const char *const _h2c_msr_role_str[];\n#define h2c_msr_role_str(role) (((role) >= H2C_MSR_ROLE_MAX) ? _h2c_msr_role_str[H2C_MSR_ROLE_MAX] : _h2c_msr_role_str[(role)])\n\n#define H2C_MSR_FMT \"%s %s%s\"\n#define H2C_MSR_ARG(h2c_msr) \\\n\tGET_H2CCMD_MSRRPT_PARM_OPMODE((h2c_msr)) ? \" C\" : \"\", \\\n\th2c_msr_role_str(GET_H2CCMD_MSRRPT_PARM_ROLE((h2c_msr))), \\\n\tGET_H2CCMD_MSRRPT_PARM_MIRACAST((h2c_msr)) ? (GET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK((h2c_msr)) ? \" MSINK\" : \" MSRC\") : \"\"\n\ns32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, bool macid_ind, u8 macid_end);\ns32 rtw_hal_set_FwMediaStatusRpt_single_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid);\ns32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, u8 macid_end);\n\n/* _KEEP_ALIVE_CMD_0x03 */\n#define SET_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)\n#define SET_H2CCMD_KEEPALIVE_PARM_PORT_NUM(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 3, __Value)\n#define SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n\n/* _DISCONNECT_DECISION_CMD_0x04 */\n#define SET_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_H2CCMD_DISCONDECISION_PARM_TRY_BCN_FAIL_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)\n#define SET_H2CCMD_DISCONDECISION_PARM_DISCONNECT_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)\n#define SET_H2CCMD_DISCONDECISION_PORT_NUM(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 3, __Value)\n#define SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)\n#define SET_H2CCMD_DISCONDECISION_PARM_TRY_OK_BCN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n\n#ifdef CONFIG_RTW_CUSTOMER_STR\n#define RTW_CUSTOMER_STR_LEN 16\n#define RTW_CUSTOMER_STR_FMT \"%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\"\n#define RTW_CUSTOMER_STR_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \\\n\t((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9], ((u8 *)(x))[10], ((u8 *)(x))[11], \\\n\t((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15]\n\n/* H2C_CUSTOMER_STR_REQ  0x06 */\n#define H2C_CUSTOMER_STR_REQ_LEN 1\n#define SET_H2CCMD_CUSTOMER_STR_REQ_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))\ns32 rtw_hal_h2c_customer_str_req(_adapter *adapter);\ns32 rtw_hal_customer_str_read(_adapter *adapter, u8 *cs);\n\n/* H2C_CUSTOMER_STR_W1 0xC6 */\n#define H2C_CUSTOMER_STR_W1_LEN 7\n#define SET_H2CCMD_CUSTOMER_STR_W1_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))\n#define H2CCMD_CUSTOMER_STR_W1_BYTE0(__pH2CCmd)\t\t\t\t(((u8 *)(__pH2CCmd)) + 1)\n\n/* H2C_CUSTOMER_STR_W2 0xC7 */\n#define H2C_CUSTOMER_STR_W2_LEN 7\n#define SET_H2CCMD_CUSTOMER_STR_W2_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))\n#define H2CCMD_CUSTOMER_STR_W2_BYTE6(__pH2CCmd)\t\t\t\t(((u8 *)(__pH2CCmd)) + 1)\n\n/* H2C_CUSTOMER_STR_W3 0xC8 */\n#define H2C_CUSTOMER_STR_W3_LEN 5\n#define SET_H2CCMD_CUSTOMER_STR_W3_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))\n#define H2CCMD_CUSTOMER_STR_W3_BYTE12(__pH2CCmd)\t\t\t(((u8 *)(__pH2CCmd)) + 1)\ns32 rtw_hal_h2c_customer_str_write(_adapter *adapter, const u8 *cs);\ns32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs);\n#endif /* CONFIG_RTW_CUSTOMER_STR */\n\n/* _AP_Offload 0x08 */\n#define SET_H2CCMD_AP_WOWLAN_EN(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n/* _BCN_RsvdPage\t0x09 */\n#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_BCN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n/* _Probersp_RsvdPage 0x0a */\n#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_ProbeRsp(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n/* _Probersp_RsvdPage 0x13 */\n#define SET_H2CCMD_AP_WOW_GPIO_CTRL_INDEX(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)\n#define SET_H2CCMD_AP_WOW_GPIO_CTRL_C2H_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)\n#define SET_H2CCMD_AP_WOW_GPIO_CTRL_PLUS(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)\n#define SET_H2CCMD_AP_WOW_GPIO_CTRL_HIGH_ACTIVE(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)\n#define SET_H2CCMD_AP_WOW_GPIO_CTRL_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)\n#define SET_H2CCMD_AP_WOW_GPIO_CTRL_DURATION(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_H2CCMD_AP_WOW_GPIO_CTRL_C2H_DURATION(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n/* _AP_PS 0x26 */\n#define SET_H2CCMD_AP_WOW_PS_EN(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_H2CCMD_AP_WOW_PS_32K_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_H2CCMD_AP_WOW_PS_RF(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)\n#define SET_H2CCMD_AP_WOW_PS_DURATION(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n\n/* INACTIVE_PS 0x27, duration unit is TBTT */\n#define SET_H2CCMD_INACTIVE_PS_EN(__pH2CCmd, __Value) \\\n\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_H2CCMD_INACTIVE_IGNORE_PS(__pH2CCmd, __Value) \\\n\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_H2CCMD_INACTIVE_PERIOD_SCAN_EN(__pH2CCmd, __Value) \\\n\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)\n#define SET_H2CCMD_INACTIVE_DISBBRF(__pH2CCmd, __Value) \\\n\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)\n#define SET_H2CCMD_INACTIVE_PS_FREQ(__pH2CCmd, __Value) \\\n\tSET_BITS_TO_LE_1BYTE(__pH2CCmd + 1, 0, 8, __Value)\n#define SET_H2CCMD_INACTIVE_PS_DURATION(__pH2CCmd, __Value) \\\n\tSET_BITS_TO_LE_1BYTE(__pH2CCmd + 2, 0, 8, __Value)\n#define SET_H2CCMD_INACTIVE_PS_PERIOD_SCAN_TIME(__pH2CCmd, __Value) \\\n\tSET_BITS_TO_LE_1BYTE(__pH2CCmd + 3, 0, 8, __Value)\n\n#ifdef CONFIG_LPS_POFF\n/*PARTIAL OFF Control 0x29*/\n#define SET_H2CCMD_LPS_POFF_CTRL_EN(__pH2CCmd, __Value) \\\n\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n/*PARTIAL OFF PARAM   0x2A*/\n#define SET_H2CCMD_LPS_POFF_PARAM_RDVLD(__pH2CCmd, __Value) \\\n\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_H2CCMD_LPS_POFF_PARAM_WRVLD(__pH2CCmd, __Value) \\\n\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_H2CCMD_LPS_POFF_PARAM_STARTADDL(__pH2CCmd, __Value) \\\n\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_H2CCMD_LPS_POFF_PARAM_STARTADDH(__pH2CCmd, __Value) \\\n\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)\n#define SET_H2CCMD_LPS_POFF_PARAM_ENDADDL(__pH2CCmd, __Value) \\\n\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n#define SET_H2CCMD_LPS_POFF_PARAM_ENDADDH(__pH2CCmd, __Value) \\\n\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)\n#endif\n\n#ifdef CONFIG_FW_MULTI_PORT_SUPPORT\n/* DEFAULT PORT ID 0x2C*/\n#define SET_H2CCMD_DFTPID_PORT_ID(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 8, (__Value))\n#define SET_H2CCMD_DFTPID_MAC_ID(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 1, 0, 8, (__Value))\n#endif\n\n#ifdef CONFIG_MCC_MODE\n/* MCC LOC CMD 0x10 */\n#define SET_H2CCMD_MCC_RSVDPAGE_LOC(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_H2CCMD_MCC_PWRIDX_OFFLOAD_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 0, 1, __Value)\n#define SET_H2CCMD_MCC_PWRIDX_OFFLOAD_RFNUM(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 4, 4, __Value)\n#define SET_H2CCMD_MCC_PWRIDX_RSVDPAGE_LOC(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd) + 4, 0, 8, __Value)\n\n/* MCC RQT TSF 0x15 */\n#define SET_H2CCMD_MCC_RQT_TSFX(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)\n#define SET_H2CCMD_MCC_RQT_TSFY(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)\n\n/* MCC MAC ID CMD 0x16 */\n#define SET_H2CCMD_MCC_MACID_BITMAP_L(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_H2CCMD_MCC_MACID_BITMAP_H(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n\n/* NEW MCC CTRL CMD 0x17 */\n#define SET_H2CCMD_MCC_CTRL_V2_ORDER(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)\n#define SET_H2CCMD_MCC_CTRL_V2_TOTALNUM(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)\n#define SET_H2CCMD_MCC_CTRL_V2_CENTRAL_CH(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_H2CCMD_MCC_CTRL_V2_PRIMARY_CH(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 4, __Value)\n#define SET_H2CCMD_MCC_CTRL_V2_BW(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 4, 4, __Value)\n#define SET_H2CCMD_MCC_CTRL_V2_DURATION(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_H2CCMD_MCC_CTRL_V2_ROLE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 3, __Value)\t\t\t\n#define SET_H2CCMD_MCC_CTRL_V2_INCURCH(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value)\n#define SET_H2CCMD_MCC_CTRL_V2_DIS_SW_RETRY(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 1, __Value)\n#define SET_H2CCMD_MCC_CTRL_V2_DISTXNULL(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 5, 1, __Value)\n#define SET_H2CCMD_MCC_CTRL_V2_C2HRPT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 6, 2, __Value)\n#define SET_H2CCMD_MCC_CTRL_V2_TSFX(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 4, __Value)\n#define SET_H2CCMD_MCC_CTRL_V2_NULL_EARLY(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 4, 4, __Value)\n#define SET_H2CCMD_MCC_CTRL_V2_UPDATE_PARM(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 7, 1, __Value)\n\n\n/* MCC CTRL CMD 0x18 */\n#define SET_H2CCMD_MCC_CTRL_ORDER(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)\n#define SET_H2CCMD_MCC_CTRL_TOTALNUM(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)\n#define SET_H2CCMD_MCC_CTRL_CHIDX(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_H2CCMD_MCC_CTRL_BW(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value)\n#define SET_H2CCMD_MCC_CTRL_BW40SC(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 2, 3, __Value)\n#define SET_H2CCMD_MCC_CTRL_BW80SC(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 5, 3, __Value)\n#define SET_H2CCMD_MCC_CTRL_DURATION(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_H2CCMD_MCC_CTRL_ROLE(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 3, __Value)\n#define SET_H2CCMD_MCC_CTRL_INCURCH(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value)\n#define SET_H2CCMD_MCC_CTRL_RSVD0(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 4, __Value)\n#define SET_H2CCMD_MCC_CTRL_RSVD1(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)\n#define SET_H2CCMD_MCC_CTRL_RFETYPE(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 4, __Value)\n#define SET_H2CCMD_MCC_CTRL_DISTXNULL(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 4, 1, __Value)\n#define SET_H2CCMD_MCC_CTRL_C2HRPT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 5, 2, __Value)\n#define SET_H2CCMD_MCC_CTRL_CHSCAN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 7, 1, __Value)\n\n/* MCC Time CMD 0x19 */\n#define SET_H2CCMD_MCC_TIME_SETTING_FW_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 7, __Value)\n#define SET_H2CCMD_MCC_TIME_SETTING_START_TIME(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define  SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 4, __Value)\n#define  SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 4, __Value)\n#define  SET_H2CCMD_MCC_TIME_SETTING_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 1, __Value)\n#define  SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 1, 7, __Value)\n\n/* MCC IQK CMD 0x1A */\n#define SET_H2CCMD_MCC_IQK_READY(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_H2CCMD_MCC_IQK_ORDER(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 4, __Value)\n#define SET_H2CCMD_MCC_IQK_PATH(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 2, __Value)\n#define SET_H2CCMD_MCC_IQK_RX_L(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_H2CCMD_MCC_IQK_RX_M1(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value)\n#define SET_H2CCMD_MCC_IQK_RX_M2(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 2, 6, __Value)\n#define SET_H2CCMD_MCC_IQK_RX_H(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 4, __Value)\n#define SET_H2CCMD_MCC_IQK_TX_L(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n#define SET_H2CCMD_MCC_IQK_TX_M1(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 3, __Value)\n#define SET_H2CCMD_MCC_IQK_TX_M2(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 3, 5, __Value)\n#define SET_H2CCMD_MCC_IQK_TX_H(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 6, __Value)\n#endif /* CONFIG_MCC_MODE */\n\n/* CHNL SWITCH OPER OFFLOAD 0x1C */\n#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_CH_NUM(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_MODE(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 2, __Value)\n#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_40M_SC(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 2, 3, __Value)\n#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_80M_SC(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 5, 3, __Value)\n#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd) + 2, 0, 4, __Value)\n\n/* H2C_SINGLE_CHANNELSWITCH_V2 = 0x1D */\n#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_CENTRAL_CH_NUM(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_PRIMARY_CH_IDX(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 4, __Value)\n#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_BW(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 4, 4, __Value)\n\n\n#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)\n#define SET_H2CCMD_BTC_WL_PORT_ID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)\n#endif\n\n/* _WoWLAN PARAM_CMD_0x80 */\n#define SET_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)\n#define SET_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)\n#define SET_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)\n#define SET_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)\n#define SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)\n#define SET_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)\n#define SET_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 7, __Value)\n#define SET_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 7, 1, __Value)\n#define SET_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 1, __Value)\n#define SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 1, 7, __Value)\n#define SET_H2CCMD_WOWLAN_DISABLE_UPHY(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 1, __Value)\n#define SET_H2CCMD_WOWLAN_HST2DEV_EN(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 1, 1, __Value)\n#define SET_H2CCMD_WOWLAN_GPIO_DURATION_MS(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 2, 1, __Value)\n#define SET_H2CCMD_WOWLAN_CHANGE_UNIT(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 2, 1, __Value)\n#define SET_H2CCMD_WOWLAN_UNIT_FOR_UPHY_DISABLE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value)\n#define SET_H2CCMD_WOWLAN_TAKE_PDN_UPHY_DIS_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 1, __Value)\n#define SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 5, 1, __Value)\n#define SET_H2CCMD_WOWLAN_DEV2HST_EN(__pH2CCmd, __Value) \tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 7, 1, __Value)\n#define SET_H2CCMD_WOWLAN_TIME_FOR_UPHY_DISABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)\n#define SET_H2CCMD_WOWLAN_RISE_HST2DEV(__pH2CCmd, __Value) \tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 2, 1, __Value)\n\n/* _REMOTE_WAKEUP_CMD_0x81 */\n#define SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)\n#define SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)\n#define SET_H2CCMD_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)\n#define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)\n#define SET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 1, __Value)\n#define SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 2, 1, __Value)\n#define SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(__pH2CCmd, __Value) \\\n\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 3, 1, __Value)\n\n#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 1, __Value)\n#define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_PARSING_UNTIL_WAKEUP(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 4, 1, __Value)\n\n/* AOAC_GLOBAL_INFO_0x82 */\n#define SET_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n\n/* AOAC_RSVDPAGE_LOC_0x83 */\n#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)\n#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n#ifdef CONFIG_GTK_OL\n#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)\n#endif /* CONFIG_GTK_OL */\n#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NDP_INFO(__pH2CCmd, __Value) \\\n\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 8, __Value)\n\n/* AOAC_RSVDPAGE_2_0x84 */\n\n/* AOAC_RSVDPAGE_3_0x88 */\n#ifdef CONFIG_PNO_SUPPORT\n#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NLO_INFO(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)\n#endif\n#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_AOAC_REPORT(__pH2CCmd, __Value) \\\n\tSET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 8, __Value)\n\n#ifdef CONFIG_PNO_SUPPORT\n/* D0_Scan_Offload_Info_0x86 */\n#define SET_H2CCMD_AOAC_NLO_FUN_EN(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd), 3, 1, __Value)\n#define SET_H2CCMD_AOAC_NLO_IPS_EN(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd), 4, 1, __Value)\n#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_PACKET(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SCAN_INFO(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SSID_INFO(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#endif /* CONFIG_PNO_SUPPORT */\n\n#ifdef CONFIG_P2P_WOWLAN\n/* P2P_RsvdPage_0x8a */\n#define SET_H2CCMD_RSVDPAGE_LOC_P2P_BCN(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_H2CCMD_RSVDPAGE_LOC_P2P_PROBE_RSP(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_H2CCMD_RSVDPAGE_LOC_P2P_NEGO_RSP(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_H2CCMD_RSVDPAGE_LOC_P2P_INVITE_RSP(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_H2CCMD_RSVDPAGE_LOC_P2P_PD_RSP(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n#endif /* CONFIG_P2P_WOWLAN */\n\n#ifdef CONFIG_LPS_PG\n#define SET_H2CCMD_LPSPG_SEC_CAM_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)/*SecurityCAM_En*/\n#define SET_H2CCMD_LPSPG_MBID_CAM_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)/*BSSIDCAM_En*/\n#define SET_H2CCMD_LPSPG_PMC_CAM_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)/*PatternMatchCAM_En*/\n#define SET_H2CCMD_LPSPG_MACID_SEARCH_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)/*MACIDSearch_En*/\n#define SET_H2CCMD_LPSPG_TXSC_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)/*TXSC_En*/\n#define SET_H2CCMD_LPSPG_MU_RATE_TB_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)/*MURateTable_En*/\n#define SET_H2CCMD_LPSPG_LOC(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)/*Loc_LPS_PG*/\n#define SET_H2CCMD_LPSPG_DPK_INFO_LOC(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)/*Loc_LPS_PG_DPK_info*/\n#define SET_H2CCMD_LPSPG_IQK_INFO_LOC(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 0, 8, __Value)/*Loc_IQK_result*/\n#endif\n\n#ifdef DBG_FW_DEBUG_MSG_PKT\n#define SET_H2CCMD_FW_DBG_MSG_PKT_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)/*sniffer_dbg_en*/\n#define SET_H2CCMD_RSVDPAGE_LOC_FW_DBG_MSG_PKT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) /*loc_debug_packet*/\n#endif /*DBG_FW_DEBUG_MSG_PKT*/\n\n#ifdef DBG_RSVD_PAGE_CFG\n#define RSVD_PAGE_CFG(ops, v1, v2, v3)\t\\\n\tRTW_INFO(\"=== [RSVD][%s]-NeedPage:%d, TotalPageNum:%d TotalPacketLen:%d ===\\n\",\t\\\n\t\tops, v1, v2, v3)\n#else\n#define RSVD_PAGE_CFG(ops, v1, v2, v3) do {} while (0)\n#endif\n\n/* ---------------------------------------------------------------------------------------------------------\n * -------------------------------------------    Structure    --------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\ntypedef struct _RSVDPAGE_LOC {\n\tu8 LocProbeRsp;\n\tu8 LocPsPoll;\n\tu8 LocNullData;\n\tu8 LocQosNull;\n\tu8 LocBTQosNull;\n#ifdef CONFIG_WOWLAN\n\tu8 LocRemoteCtrlInfo;\n\tu8 LocArpRsp;\n\tu8 LocNbrAdv;\n\tu8 LocGTKRsp;\n\tu8 LocGTKInfo;\n\tu8 LocProbeReq;\n\tu8 LocNetList;\n#ifdef CONFIG_GTK_OL\n\tu8 LocGTKEXTMEM;\n#endif /* CONFIG_GTK_OL */\n\tu8 LocNDPInfo;\n\tu8 LocAOACReport;\n#ifdef CONFIG_PNO_SUPPORT\n\tu8 LocPNOInfo;\n\tu8 LocScanInfo;\n\tu8 LocSSIDInfo;\n\tu8 LocProbePacket;\n#endif /* CONFIG_PNO_SUPPORT */\n#endif /* CONFIG_WOWLAN\t */\n\tu8 LocApOffloadBCN;\n#ifdef CONFIG_P2P_WOWLAN\n\tu8 LocP2PBeacon;\n\tu8 LocP2PProbeRsp;\n\tu8 LocNegoRsp;\n\tu8 LocInviteRsp;\n\tu8 LocPDRsp;\n#endif /* CONFIG_P2P_WOWLAN */\n#ifdef DBG_FW_DEBUG_MSG_PKT\n\tu8 loc_fw_dbg_msg_pkt;\n#endif /*DBG_FW_DEBUG_MSG_PKT*/\n} RSVDPAGE_LOC, *PRSVDPAGE_LOC;\n\nstruct rsvd_page_cache_t {\n\tchar *name;\n\tu8 loc;\n\tu8 page_num;\n\tu8 *data;\n\tu32 size;\n};\n\nbool rsvd_page_cache_update_all(struct rsvd_page_cache_t *cache, u8 loc\n\t, u8 txdesc_len, u32 page_size, u8 *info, u32 info_len);\nbool rsvd_page_cache_update_data(struct rsvd_page_cache_t *cache, u8 *info\n\t, u32 info_len);\nvoid rsvd_page_cache_free_data(struct rsvd_page_cache_t *cache);\nvoid rsvd_page_cache_free(struct rsvd_page_cache_t *cache);\n\n#endif\nvoid dump_TX_FIFO(PADAPTER padapter, u8 page_num, u16 page_size);\nu8 rtw_hal_set_fw_media_status_cmd(_adapter *adapter, u8 mstatus, u8 macid);\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\n\t/* WOW command function */\n\tvoid rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable);\n\t#ifdef CONFIG_P2P_WOWLAN\n\t\t/* H2C 0x8A */\n\t\tu8 rtw_hal_set_FwP2PRsvdPage_cmd(_adapter *adapter, PRSVDPAGE_LOC rsvdpageloc);\n\t\t/* H2C 0x8B */\n\t\tu8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter *adapter);\n\t#endif /* CONFIG_P2P_WOWLAN */\n#endif\n\n#ifdef RTW_PER_CMD_SUPPORT_FW\nu8 rtw_hal_set_req_per_rpt_cmd(_adapter *adapter, u8 group_macid,\n\t\t\t       u8 rpt_type, u32 macid_bitmap);\n#endif\n"
  },
  {
    "path": "include/hal_com_led.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HAL_COMMON_LED_H_\n#define __HAL_COMMON_LED_H_\n\n#define NO_LED 0\n#define HW_LED 1\n\n#ifdef CONFIG_RTW_LED\n#define MSECS(t)        (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000)\n\n/* ********************************************************************************\n *\tLED Behavior Constant.\n * ********************************************************************************\n * Default LED behavior.\n *   */\n#define LED_BLINK_NORMAL_INTERVAL\t100\n#define LED_BLINK_SLOWLY_INTERVAL\t200\n#define LED_BLINK_LONG_INTERVAL\t400\n#define LED_INITIAL_INTERVAL\t\t1800\n\n/* LED Customerization */\n\n/* NETTRONIX */\n#define LED_BLINK_NORMAL_INTERVAL_NETTRONIX\t100\n#define LED_BLINK_SLOWLY_INTERVAL_NETTRONIX\t2000\n\n/* PORNET */\n#define LED_BLINK_SLOWLY_INTERVAL_PORNET\t1000\n#define LED_BLINK_NORMAL_INTERVAL_PORNET\t100\n#define LED_BLINK_FAST_INTERVAL_BITLAND\t\t30\n\n/* AzWave. */\n#define LED_CM2_BLINK_ON_INTERVAL\t\t250\n#define LED_CM2_BLINK_OFF_INTERVAL\t\t4750\n#define LED_CM8_BLINK_OFF_INTERVAL\t\t3750\t/* for QMI */\n\n/* RunTop */\n#define LED_RunTop_BLINK_INTERVAL\t\t300\n\n/* ALPHA */\n#define LED_BLINK_NO_LINK_INTERVAL_ALPHA\t1000\n#define LED_BLINK_NO_LINK_INTERVAL_ALPHA_500MS 500 /* add by ylb 20121012 for customer led for alpha */\n#define LED_BLINK_LINK_INTERVAL_ALPHA\t\t500\t/* 500 */\n#define LED_BLINK_SCAN_INTERVAL_ALPHA\t\t180\t/* 150 */\n#define LED_BLINK_FASTER_INTERVAL_ALPHA\t\t50\n#define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA\t5000\n\n/* 111122 by hpfan: Customized for Xavi */\n#define LED_CM11_BLINK_INTERVAL\t\t\t300\n#define LED_CM11_LINK_ON_INTERVEL\t\t3000\n\n/* Netgear */\n#define LED_BLINK_LINK_INTERVAL_NETGEAR\t\t500\n#define LED_BLINK_LINK_SLOWLY_INTERVAL_NETGEAR\t\t1000\n\n#define LED_WPS_BLINK_OFF_INTERVAL_NETGEAR\t\t100\n#define LED_WPS_BLINK_ON_INTERVAL_NETGEAR\t\t500\n\n/* Belkin AC950 */\n#define LED_BLINK_LINK_INTERVAL_ON_BELKIN\t\t200\n#define LED_BLINK_LINK_INTERVAL_OFF_BELKIN\t\t100\n#define LED_BLINK_ERROR_INTERVAL_BELKIN\t\t100\n\n/* by chiyokolin for Azurewave */\n#define LED_CM12_BLINK_INTERVAL_5Mbps\t\t160\n#define LED_CM12_BLINK_INTERVAL_10Mbps\t\t80\n#define LED_CM12_BLINK_INTERVAL_20Mbps\t\t50\n#define LED_CM12_BLINK_INTERVAL_40Mbps\t\t40\n#define LED_CM12_BLINK_INTERVAL_80Mbps\t\t30\n#define LED_CM12_BLINK_INTERVAL_MAXMbps\t\t25\n\n/* Dlink */\n#define\tLED_BLINK_NO_LINK_INTERVAL\t\t1000\n#define\tLED_BLINK_LINK_IDEL_INTERVAL\t\t100\n\n#define\tLED_BLINK_SCAN_ON_INTERVAL\t\t30\n#define\tLED_BLINK_SCAN_OFF_INTERVAL\t\t300\n\n#define LED_WPS_BLINK_ON_INTERVAL_DLINK\t\t30\n#define LED_WPS_BLINK_OFF_INTERVAL_DLINK\t\t\t300\n#define LED_WPS_BLINK_LINKED_ON_INTERVAL_DLINK\t\t\t5000\n\n/* ********************************************************************************\n * LED object.\n * ******************************************************************************** */\n\ntypedef enum _LED_CTL_MODE {\n\tLED_CTL_POWER_ON = 1,\n\tLED_CTL_LINK = 2,\n\tLED_CTL_NO_LINK = 3,\n\tLED_CTL_TX = 4, /* unspecific data TX, including single & group addressed */\n\tLED_CTL_RX = 5, /* unspecific data RX, including single & group addressed */\n\tLED_CTL_UC_TX = 6, /* single addressed data TX */\n\tLED_CTL_UC_RX = 7, /* single addressed data RX */\n\tLED_CTL_BMC_TX = 8, /* group addressed data TX */\n\tLED_CTL_BMC_RX = 9, /* group addressed data RX */\n\tLED_CTL_SITE_SURVEY = 10,\n\tLED_CTL_POWER_OFF = 11,\n\tLED_CTL_START_TO_LINK = 12,\n\tLED_CTL_START_WPS = 13,\n\tLED_CTL_STOP_WPS = 14,\n\tLED_CTL_START_WPS_BOTTON = 15, /* added for runtop */\n\tLED_CTL_STOP_WPS_FAIL = 16, /* added for ALPHA\t */\n\tLED_CTL_STOP_WPS_FAIL_OVERLAP = 17, /* added for BELKIN */\n\tLED_CTL_CONNECTION_NO_TRANSFER = 18,\n} LED_CTL_MODE;\n\ntypedef\tenum _LED_STATE {\n\tLED_UNKNOWN = 0,\n\tRTW_LED_ON = 1,\n\tRTW_LED_OFF = 2,\n\tLED_BLINK_NORMAL = 3,\n\tLED_BLINK_SLOWLY = 4,\n\tLED_BLINK_POWER_ON = 5,\n\tLED_BLINK_SCAN = 6,\t/* LED is blinking during scanning period, the # of times to blink is depend on time for scanning. */\n\tLED_BLINK_NO_LINK = 7, /* LED is blinking during no link state. */\n\tLED_BLINK_StartToBlink = 8, /* Customzied for Sercomm Printer Server case */\n\tLED_BLINK_TXRX = 9,\n\tLED_BLINK_WPS = 10,\t/* LED is blinkg during WPS communication */\n\tLED_BLINK_WPS_STOP = 11,\t/* for ALPHA */\n\tLED_BLINK_WPS_STOP_OVERLAP = 12,\t/* for BELKIN */\n\tLED_BLINK_RUNTOP = 13,\t/* Customized for RunTop */\n\tLED_BLINK_CAMEO = 14,\n\tLED_BLINK_XAVI = 15,\n\tLED_BLINK_ALWAYS_ON = 16,\n\tLED_BLINK_LINK_IN_PROCESS = 17,  /* Customized for Belkin AC950 */\n\tLED_BLINK_AUTH_ERROR = 18,  /* Customized for Belkin AC950 */\n\tLED_BLINK_Azurewave_5Mbps = 19,\n\tLED_BLINK_Azurewave_10Mbps = 20,\n\tLED_BLINK_Azurewave_20Mbps = 21,\n\tLED_BLINK_Azurewave_40Mbps = 22,\n\tLED_BLINK_Azurewave_80Mbps = 23,\n\tLED_BLINK_Azurewave_MAXMbps = 24,\n\tLED_BLINK_LINK_IDEL = 25,\n\tLED_BLINK_WPS_LINKED = 26,\n} LED_STATE;\n\ntypedef enum _LED_PIN {\n\tLED_PIN_GPIO0,\n\tLED_PIN_LED0,\n\tLED_PIN_LED1,\n\tLED_PIN_LED2\n} LED_PIN;\n\n\n/* ********************************************************************************\n * PCIE LED Definition.\n * ******************************************************************************** */\n#ifdef CONFIG_PCI_HCI\ntypedef\tenum _LED_STRATEGY_PCIE {\n\t/* start from 2 */\n\tSW_LED_MODE_UC_TRX_ONLY = 2,\n\tSW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */\n\tSW_LED_MODE1, /* SW control for PCI Express */\n\tSW_LED_MODE2, /* SW control for Cameo. */\n\tSW_LED_MODE3, /* SW contorl for RunTop. */\n\tSW_LED_MODE4, /* SW control for Netcore */\n\tSW_LED_MODE5, /* added by vivi, for led new mode, DLINK */\n\tSW_LED_MODE6, /* added by vivi, for led new mode, PRONET */\n\tSW_LED_MODE7, /* added by chiyokolin, for Lenovo, PCI Express Minicard Spec Rev.1.2 spec */\n\tSW_LED_MODE8, /* added by chiyokolin, for QMI */\n\tSW_LED_MODE9, /* added by chiyokolin, for BITLAND-LENOVO, PCI Express Minicard Spec Rev.1.1\t */\n\tSW_LED_MODE10, /* added by chiyokolin, for Edimax-ASUS */\n\tSW_LED_MODE11,\t/* added by hpfan, for Xavi */\n\tSW_LED_MODE12,\t/* added by chiyokolin, for Azurewave */\n} LED_STRATEGY_PCIE, *PLED_STRATEGY_PCIE;\n\ntypedef struct _LED_PCIE {\n\tPADAPTER\t\tpadapter;\n\n\tLED_PIN\t\t\tLedPin;\t/* Identify how to implement this SW led. */\n\n\tLED_STATE\t\tCurrLedState; /* Current LED state. */\n\tBOOLEAN\t\t\tbLedOn; /* TRUE if LED is ON, FALSE if LED is OFF. */\n\n\tBOOLEAN\t\t\tbLedBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */\n\tBOOLEAN\t\t\tbLedWPSBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */\n\n\tBOOLEAN\t\t\tbLedSlowBlinkInProgress;/* added by vivi, for led new mode */\n\tu32\t\t\t\tBlinkTimes; /* Number of times to toggle led state for blinking. */\n\tLED_STATE\t\tBlinkingLedState; /* Next state for blinking, either LED_ON or LED_OFF are. */\n\n\t_timer\t\t\tBlinkTimer; /* Timer object for led blinking. */\n} LED_PCIE, *PLED_PCIE;\n\ntypedef struct _LED_PCIE\tLED_DATA, *PLED_DATA;\ntypedef enum _LED_STRATEGY_PCIE\tLED_STRATEGY, *PLED_STRATEGY;\n\nvoid\nLedControlPCIE(\n\t\tPADAPTER\t\tAdapter,\n\t\tLED_CTL_MODE\t\tLedAction\n);\n\nvoid\ngen_RefreshLedState(\n\t\tPADAPTER\t\tAdapter);\n\n/* ********************************************************************************\n * USB  LED Definition.\n * ******************************************************************************** */\n#elif defined(CONFIG_USB_HCI)\n\n#define IS_LED_WPS_BLINKING(_LED_USB)\t(((PLED_USB)_LED_USB)->CurrLedState == LED_BLINK_WPS \\\n\t\t|| ((PLED_USB)_LED_USB)->CurrLedState == LED_BLINK_WPS_STOP \\\n\t\t|| ((PLED_USB)_LED_USB)->bLedWPSBlinkInProgress)\n\n#define IS_LED_BLINKING(_LED_USB)\t(((PLED_USB)_LED_USB)->bLedWPSBlinkInProgress \\\n\t\t|| ((PLED_USB)_LED_USB)->bLedScanBlinkInProgress)\n\n\ntypedef\tenum _LED_STRATEGY_USB {\n\t/* start from 2 */\n\tSW_LED_MODE_UC_TRX_ONLY = 2,\n\tSW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */\n\tSW_LED_MODE1, /* 2 LEDs, through LED0 and LED1. For ALPHA. */\n\tSW_LED_MODE2, /* SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. */\n\tSW_LED_MODE3, /* SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. */\n\tSW_LED_MODE4, /* for Edimax / Belkin */\n\tSW_LED_MODE5, /* for Sercomm / Belkin\t */\n\tSW_LED_MODE6,\t/* for 88CU minicard, porting from ce SW_LED_MODE7 */\n\tSW_LED_MODE7,\t/* for Netgear special requirement */\n\tSW_LED_MODE8, /* for LC */\n\tSW_LED_MODE9, /* for Belkin AC950 */\n\tSW_LED_MODE10, /* for Netgear A6200V2 */\n\tSW_LED_MODE11, /* for Edimax / ASUS */\n\tSW_LED_MODE12, /* for WNC/NEC */\n\tSW_LED_MODE13, /* for Netgear A6100, 8811Au */\n\tSW_LED_MODE14, /* for Buffalo, DNI, 8811Au */\n\tSW_LED_MODE15, /* for DLINK,  8811Au/8812AU\t */\n} LED_STRATEGY_USB, *PLED_STRATEGY_USB;\n\n\ntypedef struct _LED_USB {\n\tPADAPTER\t\t\tpadapter;\n\n\tLED_PIN\t\t\t\tLedPin;\t/* Identify how to implement this SW led. */\n\n\tLED_STATE\t\t\tCurrLedState; /* Current LED state. */\n\tBOOLEAN\t\t\t\tbLedOn; /* TRUE if LED is ON, FALSE if LED is OFF. */\n\n\tBOOLEAN\t\t\t\tbSWLedCtrl;\n\n\tBOOLEAN\t\t\t\tbLedBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */\n\t/* ALPHA, added by chiyoko, 20090106 */\n\tBOOLEAN\t\t\t\tbLedNoLinkBlinkInProgress;\n\tBOOLEAN\t\t\t\tbLedLinkBlinkInProgress;\n\tBOOLEAN\t\t\t\tbLedStartToLinkBlinkInProgress;\n\tBOOLEAN\t\t\t\tbLedScanBlinkInProgress;\n\tBOOLEAN\t\t\t\tbLedWPSBlinkInProgress;\n\n\tu32\t\t\t\t\tBlinkTimes; /* Number of times to toggle led state for blinking. */\n\tu8\t\t\t\t\tBlinkCounter; /* Added for turn off overlap led after blinking a while, by page, 20120821 */\n\tLED_STATE\t\t\tBlinkingLedState; /* Next state for blinking, either LED_ON or LED_OFF are. */\n\n\t_timer\t\t\t\tBlinkTimer; /* Timer object for led blinking. */\n\n\t_workitem\t\t\tBlinkWorkItem; /* Workitem used by BlinkTimer to manipulate H/W to blink LED.' */\n} LED_USB, *PLED_USB;\n\ntypedef struct _LED_USB\tLED_DATA, *PLED_DATA;\ntypedef enum _LED_STRATEGY_USB\tLED_STRATEGY, *PLED_STRATEGY;\n#ifdef CONFIG_RTW_SW_LED\nvoid\nLedControlUSB(\n\t\tPADAPTER\t\tAdapter,\n\t\tLED_CTL_MODE\t\tLedAction\n);\n#endif\n\n\n/* ********************************************************************************\n * SDIO LED Definition.\n * ******************************************************************************** */\n#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\n#define IS_LED_WPS_BLINKING(_LED_SDIO)\t(((PLED_SDIO)_LED_SDIO)->CurrLedState == LED_BLINK_WPS \\\n\t\t|| ((PLED_SDIO)_LED_SDIO)->CurrLedState == LED_BLINK_WPS_STOP \\\n\t\t|| ((PLED_SDIO)_LED_SDIO)->bLedWPSBlinkInProgress)\n\n#define IS_LED_BLINKING(_LED_SDIO)\t(((PLED_SDIO)_LED_SDIO)->bLedWPSBlinkInProgress \\\n\t\t|| ((PLED_SDIO)_LED_SDIO)->bLedScanBlinkInProgress)\n\n\ntypedef\tenum _LED_STRATEGY_SDIO {\n\t/* start from 2 */\n\tSW_LED_MODE_UC_TRX_ONLY = 2,\n\tSW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */\n\tSW_LED_MODE1, /* 2 LEDs, through LED0 and LED1. For ALPHA. */\n\tSW_LED_MODE2, /* SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. */\n\tSW_LED_MODE3, /* SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. */\n\tSW_LED_MODE4, /* for Edimax / Belkin */\n\tSW_LED_MODE5, /* for Sercomm / Belkin\t */\n\tSW_LED_MODE6,\t/* for 88CU minicard, porting from ce SW_LED_MODE7 */\n} LED_STRATEGY_SDIO, *PLED_STRATEGY_SDIO;\n\ntypedef struct _LED_SDIO {\n\tPADAPTER\t\t\tpadapter;\n\n\tLED_PIN\t\t\t\tLedPin;\t/* Identify how to implement this SW led. */\n\n\tLED_STATE\t\t\tCurrLedState; /* Current LED state. */\n\tBOOLEAN\t\t\t\tbLedOn; /* TRUE if LED is ON, FALSE if LED is OFF. */\n\n\tBOOLEAN\t\t\t\tbSWLedCtrl;\n\n\tBOOLEAN\t\t\t\tbLedBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */\n\t/* ALPHA, added by chiyoko, 20090106 */\n\tBOOLEAN\t\t\t\tbLedNoLinkBlinkInProgress;\n\tBOOLEAN\t\t\t\tbLedLinkBlinkInProgress;\n\tBOOLEAN\t\t\t\tbLedStartToLinkBlinkInProgress;\n\tBOOLEAN\t\t\t\tbLedScanBlinkInProgress;\n\tBOOLEAN\t\t\t\tbLedWPSBlinkInProgress;\n\n\tu32\t\t\t\t\tBlinkTimes; /* Number of times to toggle led state for blinking. */\n\tLED_STATE\t\t\tBlinkingLedState; /* Next state for blinking, either LED_ON or LED_OFF are. */\n\n\t_timer\t\t\t\tBlinkTimer; /* Timer object for led blinking. */\n\n\t_workitem\t\t\tBlinkWorkItem; /* Workitem used by BlinkTimer to manipulate H/W to blink LED. */\n} LED_SDIO, *PLED_SDIO;\n\ntypedef struct _LED_SDIO\tLED_DATA, *PLED_DATA;\ntypedef enum _LED_STRATEGY_SDIO\tLED_STRATEGY, *PLED_STRATEGY;\n\nvoid\nLedControlSDIO(\n\t\tPADAPTER\t\tAdapter,\n\t\tLED_CTL_MODE\t\tLedAction\n);\n\n#endif\n\nstruct led_priv {\n\tLED_STRATEGY\t\tLedStrategy;\n#ifdef CONFIG_RTW_SW_LED\n\tLED_DATA\t\t\tSwLed0;\n\tLED_DATA\t\t\tSwLed1;\n\tLED_DATA\t\t\tSwLed2;\n\tu8\t\t\t\t\tbRegUseLed;\n\tu8 iface_en_mask;\n\tu32 ctl_en_mask[CONFIG_IFACE_NUMBER];\n\tvoid (*LedControlHandler)(_adapter *padapter, LED_CTL_MODE LedAction);\n\tvoid (*SwLedOn)(_adapter *padapter, PLED_DATA pLed);\n\tvoid (*SwLedOff)(_adapter *padapter, PLED_DATA pLed);\n#endif\n};\n\n#define SwLedOn(adapter, pLed) \\\n\tdo { \\\n\t\tif (adapter_to_led(adapter)->SwLedOn) \\\n\t\t\tadapter_to_led(adapter)->SwLedOn((adapter), (pLed)); \\\n\t} while (0)\n\n#define SwLedOff(adapter, pLed) \\\n\tdo { \\\n\t\tif (adapter_to_led(adapter)->SwLedOff) \\\n\t\t\tadapter_to_led(adapter)->SwLedOff((adapter), (pLed)); \\\n\t} while (0)\n\nvoid BlinkTimerCallback(void *data);\nvoid BlinkWorkItemCallback(_workitem *work);\n\nvoid ResetLedStatus(PLED_DATA pLed);\n\nvoid\nInitLed(\n\t_adapter\t\t\t*padapter,\n\tPLED_DATA\t\tpLed,\n\tLED_PIN\t\t\tLedPin\n);\n\nvoid\nDeInitLed(\n\tPLED_DATA\t\tpLed\n);\n\n/* hal... */\nextern void BlinkHandler(PLED_DATA\tpLed);\nvoid dump_led_config(void *sel, _adapter *adapter);\nvoid rtw_led_set_strategy(_adapter *adapter, u8 strategy);\n#endif /* CONFIG_RTW_LED */\n\n#if defined(CONFIG_RTW_LED)\n#define rtw_led_get_strategy(adapter) (adapter_to_led(adapter)->LedStrategy)\n#else\n#define rtw_led_get_strategy(adapter) NO_LED\n#endif\n\n#define IS_NO_LED_STRATEGY(s) ((s) == NO_LED)\n#define IS_HW_LED_STRATEGY(s) ((s) == HW_LED)\n#define IS_SW_LED_STRATEGY(s) ((s) != NO_LED && (s) != HW_LED)\n\n#if defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED)\n\n#ifndef CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY\n#define CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY 0\n#endif\n\n#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY\nvoid rtw_sw_led_blink_uc_trx_only(LED_DATA *led);\nvoid rtw_sw_led_ctl_mode_uc_trx_only(_adapter *adapter, LED_CTL_MODE ctl);\n#endif\nvoid rtw_led_control(_adapter *adapter, LED_CTL_MODE ctl);\nvoid rtw_led_tx_control(_adapter *adapter, const u8 *da);\nvoid rtw_led_rx_control(_adapter *adapter, const u8 *da);\nvoid rtw_led_set_iface_en(_adapter *adapter, u8 en);\nvoid rtw_led_set_iface_en_mask(_adapter *adapter, u8 mask);\nvoid rtw_led_set_ctl_en_mask(_adapter *adapter, u32 ctl_mask);\nvoid rtw_led_set_ctl_en_mask_primary(_adapter *adapter);\nvoid rtw_led_set_ctl_en_mask_virtual(_adapter *adapter);\n#else\n#define rtw_led_control(adapter, ctl) do {} while (0)\n#define rtw_led_tx_control(adapter, da) do {} while (0)\n#define rtw_led_rx_control(adapter, da) do {} while (0)\n#define rtw_led_set_iface_en(adapter, en) do {} while (0)\n#define rtw_led_set_iface_en_mask(adapter, mask) do {} while (0)\n#define rtw_led_set_ctl_en_mask(adapter, ctl_mask) do {} while (0)\n#define rtw_led_set_ctl_en_mask_primary(adapter) do {} while (0)\n#define rtw_led_set_ctl_en_mask_virtual(adapter) do {} while (0)\n#endif /* defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED) */\n\n#endif /*__HAL_COMMON_LED_H_*/\n\n"
  },
  {
    "path": "include/hal_com_phycfg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HAL_COM_PHYCFG_H__\n#define __HAL_COM_PHYCFG_H__\n\n#define\t\tPathA                     \t\t\t0x0\t/* Useless */\n#define\t\tPathB\t\t\t0x1\n#define\t\tPathC\t\t\t0x2\n#define\t\tPathD\t\t\t0x3\n\ntypedef enum _RF_TX_NUM {\n\tRF_1TX = 0,\n\tRF_2TX,\n\tRF_3TX,\n\tRF_4TX,\n\tRF_MAX_TX_NUM,\n\tRF_TX_NUM_NONIMPLEMENT,\n} RF_TX_NUM;\n\n/*------------------------------Define structure----------------------------*/\ntypedef struct _BB_REGISTER_DEFINITION {\n\tu32 rfintfs;\t\t\t/* set software control: */\n\t/*\t\t0x870~0x877[8 bytes] */\n\n\tu32 rfintfo; \t\t\t/* output data: */\n\t/*\t\t0x860~0x86f [16 bytes] */\n\n\tu32 rfintfe; \t\t\t/* output enable: */\n\t/*\t\t0x860~0x86f [16 bytes] */\n\n\tu32 rf3wireOffset;\t/* LSSI data: */\n\t/*\t\t0x840~0x84f [16 bytes] */\n\n\tu32 rfHSSIPara2;\t/* wire parameter control2 :  */\n\t/*\t\t0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] */\n\n\tu32 rfLSSIReadBack;\t/* LSSI RF readback data SI mode */\n\t/*\t\t0x8a0~0x8af [16 bytes] */\n\n\tu32 rfLSSIReadBackPi;\t/* LSSI RF readback data PI mode 0x8b8-8bc for Path A and B */\n\n} BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;\n\n\n/* ---------------------------------------------------------------------- */\nu8\nPHY_GetTxPowerByRateBase(\n\t\tPADAPTER\t\tAdapter,\n\t\tu8\t\t\t\tBand,\n\t\tu8\t\t\t\tRfPath,\n\t\tRATE_SECTION\tRateSection\n);\n\nvoid\nPHY_GetRateValuesOfTxPowerByRate(\n\t\tPADAPTER pAdapter,\n\t\tu32 RegAddr,\n\t\tu32 BitMask,\n\t\tu32 Value,\n\t\tu8 *Rate,\n\t\ts8 *PwrByRateVal,\n\t\tu8 *RateNum\n);\n\nu8\nPHY_GetRateIndexOfTxPowerByRate(\n\t\tu8\tRate\n);\n\nvoid\nphy_set_tx_power_index_by_rate_section(\n\t\tPADAPTER\t\tpAdapter,\n\t\tenum rf_path\t\tRFPath,\n\t\tu8\t\t\t\tChannel,\n\t\tu8\t\t\t\tRateSection\n);\n\ns8\n_PHY_GetTxPowerByRate(\n\t\tPADAPTER\tpAdapter,\n\t\tu8\t\t\tBand,\n\t\tenum rf_path\tRFPath,\n\t\tu8\t\t\tRateIndex\n);\n\ns8\nPHY_GetTxPowerByRate(\n\t\tPADAPTER\tpAdapter,\n\t\tu8\t\t\tBand,\n\t\tenum rf_path\tRFPath,\n\t\tu8\t\t\tRateIndex\n);\n\nvoid\nPHY_SetTxPowerByRate(\n\t\tPADAPTER\tpAdapter,\n\t\tu8\t\t\tBand,\n\t\tenum rf_path\tRFPath,\n\t\tu8\t\t\tRate,\n\t\ts8\t\t\tValue\n);\n\nvoid\nphy_set_tx_power_level_by_path(\n\t\tPADAPTER\tAdapter,\n\t\tu8\t\t\tchannel,\n\t\tu8\t\t\tpath\n);\n\nvoid\nPHY_SetTxPowerIndexByRateArray(\n\t\tPADAPTER\t\tpAdapter,\n\t\tenum rf_path\t\tRFPath,\n\t\tenum channel_width BandWidth,\n\t\tu8\t\t\t\tChannel,\n\t\tu8\t\t\t\t*Rates,\n\t\tu8\t\t\t\tRateArraySize\n);\n\nvoid\nPHY_InitTxPowerByRate(\n\t\tPADAPTER\tpAdapter\n);\n\nvoid\nphy_store_tx_power_by_rate(\n\t\tPADAPTER\tpAdapter,\n\t\tu32\t\t\tBand,\n\t\tu32\t\t\tRfPath,\n\t\tu32\t\t\tTxNum,\n\t\tu32\t\t\tRegAddr,\n\t\tu32\t\t\tBitMask,\n\t\tu32\t\t\tData\n);\n\nvoid\nPHY_TxPowerByRateConfiguration(\n\t  PADAPTER\t\t\tpAdapter\n);\n\nu8 phy_get_pg_txpwr_idx(\n\t\tPADAPTER\t\tpAdapter,\n\t\tenum rf_path\t\tRFPath,\n\t\tu8\t\t\t\tRate,\n\tu8 ntx_idx,\n\t\tenum channel_width\tBandWidth,\n\t\tu8\t\t\t\tChannel,\n\t\tPBOOLEAN\t\tbIn24G\n);\n\n#if CONFIG_TXPWR_LIMIT\ns8 phy_get_txpwr_lmt_abs(_adapter *adapter\n\t, const char *regd_name\n\t, BAND_TYPE band, enum channel_width bw\n\t, u8 tlrs, u8 ntx_idx, u8 cch, u8 lock\n);\n\ns8 phy_get_txpwr_lmt(_adapter *adapter\n\t, const char *regd_name\n\t, BAND_TYPE band, enum channel_width bw\n\t, u8 rfpath, u8 rs, u8 ntx_idx, u8 cch, u8 lock\n);\n\ns8 PHY_GetTxPowerLimit(_adapter *adapter\n\t, const char *regd_name\n\t, BAND_TYPE band, enum channel_width bw\n\t, u8 rfpath, u8 rate, u8 ntx_idx, u8 cch\n);\n#else\n#define phy_get_txpwr_lmt_abs(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max)\n#define phy_get_txpwr_lmt(adapter, regd_name, band, bw, rfpath, rs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max)\n#define PHY_GetTxPowerLimit(adapter, regd_name, band, bw, rfpath, rate, ntx_idx, cch) (GET_HAL_SPEC(adapter)->txgi_max)\n#endif /* CONFIG_TXPWR_LIMIT */\n\ns8\nPHY_GetTxPowerTrackingOffset(\n\tPADAPTER\tpAdapter,\n\tenum rf_path\tRFPath,\n\tu8\t\t\tRate\n);\n\nstruct txpwr_idx_comp {\n\tu8 ntx_idx;\n\tu8 pg;\n\ts8 by_rate;\n\ts8 limit;\n\ts8 tpt;\n\ts8 ebias;\n\ts8 btc;\n\ts8 dpd;\n};\n\n#define txpwr_idx_comp_set(_tic, _ntx_idx, _pg, _by_rate, _limit, _tpt, _ebias, _btc, _dpd) \\\n\tdo { \\\n\t\t(_tic)->ntx_idx = _ntx_idx; \\\n\t\t(_tic)->pg = _pg; \\\n\t\t(_tic)->by_rate = _by_rate; \\\n\t\t(_tic)->limit = _limit; \\\n\t\t(_tic)->tpt = _tpt; \\\n\t\t(_tic)->ebias = _ebias; \\\n\t\t(_tic)->btc = _btc; \\\n\t\t(_tic)->dpd = _dpd; \\\n\t} while (0)\n\nu8\nphy_get_tx_power_index(\n\t\tPADAPTER\t\t\tpAdapter,\n\t\tenum rf_path\t\t\tRFPath,\n\t\tu8\t\t\t\t\tRate,\n\t\tenum channel_width\tBandWidth,\n\t\tu8\t\t\t\t\tChannel\n);\n\nvoid\nPHY_SetTxPowerIndex(\n\t\tPADAPTER\t\tpAdapter,\n\t\tu32\t\t\t\tPowerIndex,\n\t\tenum rf_path\t\tRFPath,\n\t\tu8\t\t\t\tRate\n);\n\nvoid dump_tx_power_idx_title(void *sel, _adapter *adapter);\nvoid dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath, u8 rs);\nvoid dump_tx_power_idx(void *sel, _adapter *adapter);\n\nbool phy_is_tx_power_limit_needed(_adapter *adapter);\nbool phy_is_tx_power_by_rate_needed(_adapter *adapter);\nint phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file);\n#if CONFIG_TXPWR_LIMIT\nint phy_load_tx_power_limit(_adapter *adapter, u8 chk_file);\n#endif\nvoid phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file);\nvoid phy_reload_tx_power_ext_info(_adapter *adapter);\nvoid phy_reload_default_tx_power_ext_info(_adapter *adapter);\n\nconst struct map_t *hal_pg_txpwr_def_info(_adapter *adapter);\n\n#ifdef CONFIG_EFUSE_CONFIG_FILE\nint check_phy_efuse_tx_power_info_valid(_adapter *adapter);\n#endif\n\nvoid dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt);\nvoid dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt);\n\nvoid hal_load_txpwr_info(\n\t_adapter *adapter,\n\tTxPowerInfo24G *pwr_info_2g,\n\tTxPowerInfo5G *pwr_info_5g,\n\tu8 *pg_data\n);\n\nvoid dump_tx_power_ext_info(void *sel, _adapter *adapter);\nvoid dump_target_tx_power(void *sel, _adapter *adapter);\nvoid dump_tx_power_by_rate(void *sel, _adapter *adapter);\n\nint rtw_get_phy_file_path(_adapter *adapter, const char *file_name);\n\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n#define MAC_FILE_FW_NIC\t\t\t\"FW_NIC.bin\"\n#define MAC_FILE_FW_WW_IMG\t\t\"FW_WoWLAN.bin\"\n#define PHY_FILE_MAC_REG\t\t\"MAC_REG.txt\"\n\n#define PHY_FILE_AGC_TAB\t\t\"AGC_TAB.txt\"\n#define PHY_FILE_PHY_REG\t\t\"PHY_REG.txt\"\n#define PHY_FILE_PHY_REG_MP\t\t\"PHY_REG_MP.txt\"\n#define PHY_FILE_PHY_REG_PG\t\t\"PHY_REG_PG.txt\"\n\n#define PHY_FILE_RADIO_A\t\t\"RadioA.txt\"\n#define PHY_FILE_RADIO_B\t\t\"RadioB.txt\"\n#define PHY_FILE_RADIO_C\t\t\"RadioC.txt\"\n#define PHY_FILE_RADIO_D\t\t\"RadioD.txt\"\n#define PHY_FILE_TXPWR_TRACK\t\"TxPowerTrack.txt\"\n#define PHY_FILE_TXPWR_LMT\t\t\"TXPWR_LMT.txt\"\n\n#define PHY_FILE_WIFI_ANT_ISOLATION\t\"wifi_ant_isolation.txt\"\n\n#define MAX_PARA_FILE_BUF_LEN\t32768 /* 32k */\n\n#define LOAD_MAC_PARA_FILE\t\t\t\tBIT0\n#define LOAD_BB_PARA_FILE\t\t\t\t\tBIT1\n#define LOAD_BB_PG_PARA_FILE\t\t\t\tBIT2\n#define LOAD_BB_MP_PARA_FILE\t\t\t\tBIT3\n#define LOAD_RF_PARA_FILE\t\t\t\t\tBIT4\n#define LOAD_RF_TXPWR_TRACK_PARA_FILE\tBIT5\n#define LOAD_RF_TXPWR_LMT_PARA_FILE\t\tBIT6\n\nint phy_ConfigMACWithParaFile(PADAPTER\tAdapter, char\t*pFileName);\nint phy_ConfigBBWithParaFile(PADAPTER\tAdapter, char\t*pFileName, u32\tConfigType);\nint phy_ConfigBBWithPgParaFile(PADAPTER\tAdapter, const char *pFileName);\nint phy_ConfigBBWithMpParaFile(PADAPTER\tAdapter, char\t*pFileName);\nint PHY_ConfigRFWithParaFile(PADAPTER\tAdapter, char\t*pFileName, enum rf_path\teRFPath);\nint PHY_ConfigRFWithTxPwrTrackParaFile(PADAPTER\tAdapter, char\t*pFileName);\n#if CONFIG_TXPWR_LIMIT\nint PHY_ConfigRFWithPowerLimitTableParaFile(PADAPTER\tAdapter, const char *pFileName);\n#endif\nvoid phy_free_filebuf_mask(_adapter *padapter, u8 mask);\nvoid phy_free_filebuf(_adapter *padapter);\n#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */\nu8 phy_check_under_survey_ch(_adapter *adapter);\n#endif /* __HAL_COMMON_H__ */\n"
  },
  {
    "path": "include/hal_com_reg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HAL_COMMON_REG_H__\n#define __HAL_COMMON_REG_H__\n\n\n#define MAC_ADDR_LEN\t\t\t\t6\n\n#define HAL_NAV_UPPER_UNIT\t\t128\t\t/* micro-second */\n\n/* 8188E PKT_BUFF_ACCESS_CTRL value */\n#define TXPKT_BUF_SELECT\t\t\t\t0x69\n#define RXPKT_BUF_SELECT\t\t\t\t0xA5\n#define DISABLE_TRXPKT_BUF_ACCESS\t\t0x0\n\n#ifndef RTW_HALMAC\n/* ************************************************************\n*\n* ************************************************************ */\n\n/* -----------------------------------------------------\n*\n*\t0x0000h ~ 0x00FFh\tSystem Configuration\n*\n* ----------------------------------------------------- */\n#define REG_SYS_ISO_CTRL\t\t\t\t0x0000\n#define REG_SYS_FUNC_EN\t\t\t\t0x0002\n#define REG_APS_FSMCO\t\t\t\t\t0x0004\n#define REG_SYS_CLKR\t\t\t\t\t0x0008\n#define REG_SYS_CLK_CTRL\t\t\t\tREG_SYS_CLKR\n#define REG_9346CR\t\t\t\t\t\t0x000A\n#define REG_SYS_EEPROM_CTRL\t\t\t0x000A\n#define REG_EE_VPD\t\t\t\t\t\t0x000C\n#define REG_AFE_MISC\t\t\t\t\t0x0010\n#define REG_SPS0_CTRL\t\t\t\t\t0x0011\n#define REG_SPS0_CTRL_6\t\t\t\t\t0x0016\n#define REG_POWER_OFF_IN_PROCESS\t\t0x0017\n#define REG_SPS_OCP_CFG\t\t\t\t0x0018\n#define REG_RSV_CTRL\t\t\t\t\t0x001C\n#define REG_RF_CTRL\t\t\t\t\t\t0x001F\n#define REG_LDOA15_CTRL\t\t\t\t0x0020\n#define REG_LDOV12D_CTRL\t\t\t\t0x0021\n#define REG_LDOHCI12_CTRL\t\t\t\t0x0022\n#define REG_LPLDO_CTRL\t\t\t\t\t0x0023\n#define REG_AFE_XTAL_CTRL\t\t\t\t0x0024\n#define REG_AFE_LDO_CTRL\t\t\t\t0x0027 /* 1.5v for 8188EE test chip, 1.4v for MP chip */\n#define REG_AFE_PLL_CTRL\t\t\t\t0x0028\n#define REG_MAC_PHY_CTRL\t\t\t\t0x002c /* for 92d, DMDP, SMSP, DMSP contrl */\n#define REG_APE_PLL_CTRL_EXT\t\t\t0x002c\n#define REG_EFUSE_CTRL\t\t\t\t\t0x0030\n#define REG_EFUSE_TEST\t\t\t\t\t0x0034\n#define REG_PWR_DATA\t\t\t\t\t0x0038\n#define REG_CAL_TIMER\t\t\t\t\t0x003C\n#define REG_ACLK_MON\t\t\t\t\t0x003E\n#define REG_GPIO_MUXCFG\t\t\t\t0x0040\n#define REG_GPIO_IO_SEL\t\t\t\t\t0x0042\n#define REG_MAC_PINMUX_CFG\t\t\t0x0043\n#define REG_GPIO_PIN_CTRL\t\t\t\t0x0044\n#define REG_GPIO_INTM\t\t\t\t\t0x0048\n#define REG_LEDCFG0\t\t\t\t\t\t0x004C\n#define REG_LEDCFG1\t\t\t\t\t\t0x004D\n#define REG_LEDCFG2\t\t\t\t\t\t0x004E\n#define REG_LEDCFG3\t\t\t\t\t\t0x004F\n#define REG_FSIMR\t\t\t\t\t\t0x0050\n#define REG_FSISR\t\t\t\t\t\t0x0054\n#define REG_HSIMR\t\t\t\t\t\t0x0058\n#define REG_HSISR\t\t\t\t\t\t0x005c\n#define REG_GPIO_PIN_CTRL_2\t\t\t0x0060 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */\n#define REG_GPIO_IO_SEL_2\t\t\t\t0x0062 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */\n#define REG_PAD_CTRL_1\t\t\t\t0x0064\n#define REG_MULTI_FUNC_CTRL\t\t\t0x0068 /* RTL8723 WIFI/BT/GPS Multi-Function control source. */\n#define REG_GSSR\t\t\t\t\t\t0x006c\n#define REG_AFE_XTAL_CTRL_EXT\t\t\t0x0078 /* RTL8188E */\n#define REG_XCK_OUT_CTRL\t\t\t\t0x007c /* RTL8188E */\n#define REG_MCUFWDL\t\t\t\t\t0x0080\n#define REG_WOL_EVENT\t\t\t\t\t0x0081 /* RTL8188E */\n#define REG_MCUTSTCFG\t\t\t\t\t0x0084\n#define REG_FDHM0\t\t\t\t\t\t0x0088\n#define REG_HOST_SUSP_CNT\t\t\t\t0x00BC\t/* RTL8192C Host suspend counter on FPGA platform */\n#define REG_SYSTEM_ON_CTRL\t\t\t0x00CC\t/* For 8723AE Reset after S3 */\n#define REG_EFUSE_ACCESS\t\t\t\t0x00CF\t/* Efuse access protection for RTL8723 */\n#define REG_BIST_SCAN\t\t\t\t\t0x00D0\n#define REG_BIST_RPT\t\t\t\t\t0x00D4\n#define REG_BIST_ROM_RPT\t\t\t\t0x00D8\n#define REG_USB_SIE_INTF\t\t\t\t0x00E0\n#define REG_PCIE_MIO_INTF\t\t\t\t0x00E4\n#define REG_PCIE_MIO_INTD\t\t\t\t0x00E8\n#define REG_HPON_FSM\t\t\t\t\t0x00EC\n#define REG_SYS_CFG\t\t\t\t\t\t0x00F0\n#define REG_GPIO_OUTSTS\t\t\t\t0x00F4\t/* For RTL8723 only. */\n#define REG_TYPE_ID\t\t\t\t\t\t0x00FC\n\n/*\n* 2010/12/29 MH Add for 92D\n*   */\n#define REG_MAC_PHY_CTRL_NORMAL\t\t0x00f8\n\n\n/* -----------------------------------------------------\n*\n*\t0x0100h ~ 0x01FFh\tMACTOP General Configuration\n*\n* ----------------------------------------------------- */\n#define REG_CR\t\t\t\t\t\t\t0x0100\n#define REG_PBP\t\t\t\t\t\t\t0x0104\n#define REG_PKT_BUFF_ACCESS_CTRL\t\t0x0106\n#define REG_TRXDMA_CTRL\t\t\t\t0x010C\n#define REG_TRXFF_BNDY\t\t\t\t\t0x0114\n#define REG_TRXFF_STATUS\t\t\t\t0x0118\n#define REG_RXFF_PTR\t\t\t\t\t0x011C\n#define REG_HIMR\t\t\t\t\t\t0x0120\n#define REG_FE1IMR\t\t\t\t\t\t0x0120\n#define REG_HISR\t\t\t\t\t\t\t0x0124\n#define REG_HIMRE\t\t\t\t\t\t0x0128\n#define REG_HISRE\t\t\t\t\t\t0x012C\n#define REG_CPWM\t\t\t\t\t\t0x012F\n#define REG_FWIMR\t\t\t\t\t\t0x0130\n#define REG_FWISR\t\t\t\t\t\t0x0134\n#define REG_FTIMR\t\t\t\t\t\t0x0138\n#define REG_FTISR\t\t\t\t\t\t0x013C /* RTL8192C */\n#define REG_PKTBUF_DBG_CTRL\t\t\t0x0140\n#define REG_RXPKTBUF_CTRL\t\t\t\t(REG_PKTBUF_DBG_CTRL+2)\n#define REG_PKTBUF_DBG_DATA_L\t\t\t0x0144\n#define REG_PKTBUF_DBG_DATA_H\t\t0x0148\n\n#define REG_TC0_CTRL\t\t\t\t\t0x0150\n#define REG_TC1_CTRL\t\t\t\t\t0x0154\n#define REG_TC2_CTRL\t\t\t\t\t0x0158\n#define REG_TC3_CTRL\t\t\t\t\t0x015C\n#define REG_TC4_CTRL\t\t\t\t\t0x0160\n#define REG_TCUNIT_BASE\t\t\t\t0x0164\n#define REG_MBIST_START\t\t\t\t0x0174\n#define REG_MBIST_DONE\t\t\t\t\t0x0178\n#define REG_MBIST_FAIL\t\t\t\t\t0x017C\n#define REG_32K_CTRL\t\t\t\t\t0x0194 /* RTL8188E */\n#define REG_C2HEVT_MSG_NORMAL\t\t0x01A0\n#define REG_C2HEVT_CLEAR\t\t\t\t0x01AF\n#define REG_MCUTST_1\t\t\t\t\t0x01c0\n#define REG_MCUTST_WOWLAN\t\t\t0x01C7\t/* Defined after 8188E series. */\n#define REG_FMETHR\t\t\t\t\t\t0x01C8\n#define REG_HMETFR\t\t\t\t\t\t0x01CC\n#define REG_HMEBOX_0\t\t\t\t\t0x01D0\n#define REG_HMEBOX_1\t\t\t\t\t0x01D4\n#define REG_HMEBOX_2\t\t\t\t\t0x01D8\n#define REG_HMEBOX_3\t\t\t\t\t0x01DC\n#define REG_LLT_INIT\t\t\t\t\t0x01E0\n#define REG_HMEBOX_EXT_0\t\t\t\t0x01F0\n#define REG_HMEBOX_EXT_1\t\t\t\t0x01F4\n#define REG_HMEBOX_EXT_2\t\t\t\t0x01F8\n#define REG_HMEBOX_EXT_3\t\t\t\t0x01FC\n\n\n/* -----------------------------------------------------\n*\n*\t0x0200h ~ 0x027Fh\tTXDMA Configuration\n*\n* ----------------------------------------------------- */\n#define REG_RQPN\t\t\t\t\t\t0x0200\n#define REG_FIFOPAGE\t\t\t\t\t0x0204\n#define REG_TDECTRL\t\t\t\t\t\t0x0208\n#define REG_TXDMA_OFFSET_CHK\t\t\t0x020C\n#define REG_TXDMA_STATUS\t\t\t\t0x0210\n#define REG_RQPN_NPQ\t\t\t\t\t0x0214\n#define REG_AUTO_LLT\t\t\t\t\t0x0224\n\n\n/* -----------------------------------------------------\n*\n*\t0x0280h ~ 0x02FFh\tRXDMA Configuration\n*\n* ----------------------------------------------------- */\n#define REG_RXDMA_AGG_PG_TH\t\t\t0x0280\n#define REG_RXPKT_NUM\t\t\t\t\t0x0284\n#define REG_RXDMA_STATUS\t\t\t\t0x0288\n\n/* -----------------------------------------------------\n*\n*\t0x0300h ~ 0x03FFh\tPCIe\n*\n* ----------------------------------------------------- */\n#ifndef CONFIG_TRX_BD_ARCH\t/* prevent CONFIG_TRX_BD_ARCH to use old registers */\n\n#define REG_PCIE_CTRL_REG\t\t\t\t0x0300\n#define REG_INT_MIG\t\t\t\t\t0x0304\t/* Interrupt Migration */\n#define REG_BCNQ_DESA\t\t\t\t\t0x0308\t/* TX Beacon Descriptor Address */\n#define REG_HQ_DESA\t\t\t\t\t0x0310\t/* TX High Queue Descriptor Address */\n#define REG_MGQ_DESA\t\t\t\t\t0x0318\t/* TX Manage Queue Descriptor Address */\n#define REG_VOQ_DESA\t\t\t\t\t0x0320\t/* TX VO Queue Descriptor Address */\n#define REG_VIQ_DESA\t\t\t\t\t0x0328\t/* TX VI Queue Descriptor Address */\n#define REG_BEQ_DESA\t\t\t\t\t0x0330\t/* TX BE Queue Descriptor Address */\n#define REG_BKQ_DESA\t\t\t\t\t0x0338\t/* TX BK Queue Descriptor Address */\n#define REG_RX_DESA\t\t\t\t\t0x0340\t/* RX Queue Descriptor Address */\n/* sherry added for DBI Read/Write  20091126 */\n#define REG_DBI_WDATA\t\t\t\t\t0x0348\t/*  Backdoor REG for Access Configuration */\n#define REG_DBI_RDATA\t\t\t\t\t0x034C\t/* Backdoor REG for Access Configuration */\n#define REG_DBI_CTRL\t\t\t\t\t0x0350\t/* Backdoor REG for Access Configuration */\n#define REG_DBI_FLAG\t\t\t\t\t0x0352\t/* Backdoor REG for Access Configuration */\n#define REG_MDIO\t\t\t\t\t0x0354\t/* MDIO for Access PCIE PHY */\n#define REG_DBG_SEL\t\t\t\t\t0x0360\t/* Debug Selection Register */\n#define REG_WATCH_DOG\t\t\t\t\t0x0368\n#define REG_RX_RXBD_NUM\t\t\t\t\t0x0382\n\n/* RTL8723 series ------------------------------- */\n#define REG_PCIE_HISR_EN\t\t\t\t0x0394\t/* PCIE Local Interrupt Enable Register */\n#define REG_PCIE_HISR\t\t\t\t\t0x03A0\n#define REG_PCIE_HISRE\t\t\t\t\t0x03A4\n#define REG_PCIE_HIMR\t\t\t\t\t0x03A8\n#define REG_PCIE_HIMRE\t\t\t\t\t0x03AC\n\n#endif /* !CONFIG_TRX_BD_ARCH */\n\n#define REG_USB_HIMR\t\t\t\t\t0xFE38\n#define REG_USB_HIMRE\t\t\t\t\t0xFE3C\n#define REG_USB_HISR\t\t\t\t\t0xFE78\n#define REG_USB_HISRE\t\t\t\t\t0xFE7C\n\n\n/* -----------------------------------------------------\n*\n*\t0x0400h ~ 0x047Fh\tProtocol Configuration\n*\n* ----------------------------------------------------- */\n\n/* 92C, 92D */\n#define REG_VOQ_INFO\t0x0400\n#define REG_VIQ_INFO\t0x0404\n#define REG_BEQ_INFO\t0x0408\n#define REG_BKQ_INFO\t0x040C\n\n/* 88E, 8723A, 8812A, 8821A, 92E, 8723B */\n#define REG_Q0_INFO\t0x400\n#define REG_Q1_INFO\t0x404\n#define REG_Q2_INFO\t0x408\n#define REG_Q3_INFO\t0x40C\n\n#define REG_MGQ_INFO\t0x0410\n#define REG_HGQ_INFO\t0x0414\n#define REG_BCNQ_INFO\t0x0418\n#define REG_TXPKT_EMPTY\t\t\t\t0x041A\n#define REG_CPU_MGQ_INFORMATION\t\t0x041C\n#define REG_FWHW_TXQ_CTRL\t\t\t\t0x0420\n#define REG_HWSEQ_CTRL\t\t\t\t\t0x0423\n#define REG_BCNQ_BDNY\t\t\t\t\t0x0424\n#define REG_MGQ_BDNY\t\t\t\t\t0x0425\n#define REG_LIFETIME_EN\t\t\t\t\t0x0426\n#define REG_MULTI_BCNQ_OFFSET\t\t\t0x0427\n#define REG_SPEC_SIFS\t\t\t\t\t0x0428\n#define REG_RETRY_LIMIT\t\t\t\t\t0x042A\n#define REG_DARFRC\t\t\t\t\t\t0x0430\n#define REG_RARFRC\t\t\t\t\t\t0x0438\n#define REG_RRSR\t\t\t\t\t\t0x0440\n#define REG_ARFR0\t\t\t\t\t\t0x0444\n#define REG_ARFR1\t\t\t\t\t\t0x0448\n#define REG_ARFR2\t\t\t\t\t\t0x044C\n#define REG_ARFR3\t\t\t\t\t\t0x0450\n#define REG_CCK_CHECK\t\t\t\t\t0x0454\n#define REG_BCNQ1_BDNY\t\t\t\t\t0x0457\n\n#define REG_AGGLEN_LMT\t\t\t\t\t0x0458\n#define REG_AMPDU_MIN_SPACE\t\t\t0x045C\n#define REG_WMAC_LBK_BF_HD\t\t\t0x045D\n#define REG_FAST_EDCA_CTRL\t\t\t\t0x0460\n#define REG_RD_RESP_PKT_TH\t\t\t\t0x0463\n\n/* 8723A, 8812A, 8821A, 92E, 8723B */\n#define REG_Q4_INFO\t0x468\n#define REG_Q5_INFO\t0x46C\n#define REG_Q6_INFO\t0x470\n#define REG_Q7_INFO\t0x474\n\n#define REG_INIRTS_RATE_SEL\t\t\t\t0x0480\n#define REG_INIDATA_RATE_SEL\t\t\t0x0484\n\n/* 8723B, 92E, 8812A, 8821A*/\n#define REG_MACID_SLEEP_3\t\t\t\t0x0484\n#define REG_MACID_SLEEP_1\t\t\t\t0x0488\n\n#define REG_POWER_STAGE1\t\t\t\t0x04B4\n#define REG_POWER_STAGE2\t\t\t\t0x04B8\n#define REG_PKT_LIFE_TIME\t\t\t0x04C0\n#define REG_PKT_LIFE_TIME_VO_VI\t\t0x04C0\n#define REG_PKT_LIFE_TIME_BE_BK\t\t0x04C2\n#define REG_STBC_SETTING\t\t\t\t0x04C4\n#define REG_QUEUE_CTRL\t\t\t\t\t0x04C6\n#define REG_SINGLE_AMPDU_CTRL\t\t\t0x04c7\n#define REG_PROT_MODE_CTRL\t\t\t0x04C8\n#define REG_MAX_AGGR_NUM\t\t\t\t0x04CA\n#define REG_RTS_MAX_AGGR_NUM\t\t\t0x04CB\n#define REG_BAR_MODE_CTRL\t\t\t\t0x04CC\n#define REG_RA_TRY_RATE_AGG_LMT\t\t0x04CF\n\n/* 8723A */\n#define REG_MACID_DROP\t0x04D0\n\n/* 88E */\n#define REG_EARLY_MODE_CONTROL\t0x04D0\n\n/* 8723B, 92E, 8812A, 8821A */\n#define REG_MACID_SLEEP_2\t0x04D0\n\n/* 8723A, 8723B, 92E, 8812A, 8821A */\n#define REG_MACID_SLEEP\t0x04D4\n\n#define REG_NQOS_SEQ\t\t\t\t\t0x04DC\n#define REG_HW_SEQ0\t\t\t\t\t\t0x04D8\n#define REG_HW_SEQ1\t\t\t\t\t\t0x04DA\n#define REG_HW_SEQ2\t\t\t\t\t\t0x04DC\n#define REG_HW_SEQ3\t\t\t\t\t\t0x04DE\n\n#define REG_QOS_SEQ\t\t\t\t\t0x04DE\n#define REG_NEED_CPU_HANDLE\t\t\t0x04E0\n#define REG_PKT_LOSE_RPT\t\t\t\t0x04E1\n#define REG_PTCL_ERR_STATUS\t\t\t0x04E2\n#define REG_TX_RPT_CTRL\t\t\t\t\t0x04EC\n#define REG_TX_RPT_TIME\t\t\t\t\t0x04F0\t/* 2 byte */\n#define REG_DUMMY\t\t\t\t\t\t0x04FC\n\n/* -----------------------------------------------------\n*\n*\t0x0500h ~ 0x05FFh\tEDCA Configuration\n*\n* ----------------------------------------------------- */\n#define REG_EDCA_VO_PARAM\t\t\t\t0x0500\n#define REG_EDCA_VI_PARAM\t\t\t\t0x0504\n#define REG_EDCA_BE_PARAM\t\t\t\t0x0508\n#define REG_EDCA_BK_PARAM\t\t\t\t0x050C\n#define REG_BCNTCFG\t\t\t\t\t\t0x0510\n#define REG_PIFS\t\t\t\t\t\t\t0x0512\n#define REG_RDG_PIFS\t\t\t\t\t0x0513\n#define REG_SIFS_CTX\t\t\t\t\t0x0514\n#define REG_SIFS_TRX\t\t\t\t\t0x0516\n#define REG_TSFTR_SYN_OFFSET\t\t\t0x0518\n#define REG_AGGR_BREAK_TIME\t\t\t0x051A\n#define REG_SLOT\t\t\t\t\t\t0x051B\n#define REG_TX_PTCL_CTRL\t\t\t\t0x0520\n#define REG_TXPAUSE\t\t\t\t\t\t0x0522\n#define REG_DIS_TXREQ_CLR\t\t\t\t0x0523\n#define REG_RD_CTRL\t\t\t\t\t\t0x0524\n/*\n* Format for offset 540h-542h:\n*\t[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.\n*\t[7:4]:   Reserved.\n*\t[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.\n*\t[23:20]: Reserved\n* Description:\n*\t              |\n*      |<--Setup--|--Hold------------>|\n*   --------------|----------------------\n*                 |\n*                TBTT\n* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.\n* Described by Designer Tim and Bruce, 2011-01-14.\n*   */\n#define REG_TBTT_PROHIBIT\t\t\t\t0x0540\n#define REG_RD_NAV_NXT\t\t\t\t\t0x0544\n#define REG_NAV_PROT_LEN\t\t\t\t0x0546\n#define REG_BCN_CTRL\t\t\t\t\t0x0550\n#define REG_BCN_CTRL_1\t\t\t\t\t0x0551\n#define REG_MBID_NUM\t\t\t\t\t0x0552\n#define REG_DUAL_TSF_RST\t\t\t\t0x0553\n#define REG_MBSSID_BCN_SPACE\t\t\t0x0554\n#define REG_DRVERLYINT\t\t\t\t\t0x0558\n#define REG_BCNDMATIM\t\t\t\t\t0x0559\n#define REG_ATIMWND\t\t\t\t\t0x055A\n#define REG_USTIME_TSF\t\t\t\t\t0x055C\n#define REG_BCN_MAX_ERR\t\t\t\t0x055D\n#define REG_RXTSF_OFFSET_CCK\t\t\t0x055E\n#define REG_RXTSF_OFFSET_OFDM\t\t\t0x055F\n#define REG_TSFTR\t\t\t\t\t\t0x0560\n#define REG_TSFTR1\t\t\t\t\t\t0x0568\t/* HW Port 1 TSF Register */\n#define REG_ATIMWND_1\t\t\t\t\t0x0570\n#define REG_P2P_CTWIN\t\t\t\t\t0x0572 /* 1 Byte long (in unit of TU) */\n#define REG_PSTIMER\t\t\t\t\t\t0x0580\n#define REG_TIMER0\t\t\t\t\t\t0x0584\n#define REG_TIMER1\t\t\t\t\t\t0x0588\n#define REG_HIQ_NO_LMT_EN\t\t\t\t0x05A7\n#define REG_ACMHWCTRL\t\t\t\t\t0x05C0\n#define REG_NOA_DESC_SEL\t\t\t\t0x05CF\n#define REG_NOA_DESC_DURATION\t\t0x05E0\n#define REG_NOA_DESC_INTERVAL\t\t\t0x05E4\n#define REG_NOA_DESC_START\t\t\t0x05E8\n#define REG_NOA_DESC_COUNT\t\t\t0x05EC\n\n#define REG_DMC\t\t\t\t\t\t\t0x05F0\t/* Dual MAC Co-Existence Register */\n#define REG_SCH_TX_CMD\t\t\t\t\t0x05F8\n\n#define REG_FW_RESET_TSF_CNT_1\t\t0x05FC\n#define REG_FW_RESET_TSF_CNT_0\t\t0x05FD\n#define REG_FW_BCN_DIS_CNT\t\t\t0x05FE\n\n/* -----------------------------------------------------\n*\n*\t0x0600h ~ 0x07FFh\tWMAC Configuration\n*\n* ----------------------------------------------------- */\n#define REG_APSD_CTRL\t\t\t\t\t0x0600\n#define REG_BWOPMODE\t\t\t\t\t0x0603\n#define REG_TCR\t\t\t\t\t\t\t0x0604\n#define REG_RCR\t\t\t\t\t\t\t0x0608\n#define REG_RX_PKT_LIMIT\t\t\t\t0x060C\n#define REG_RX_DLK_TIME\t\t\t\t0x060D\n#define REG_RX_DRVINFO_SZ\t\t\t\t0x060F\n\n#define REG_MACID\t\t\t\t\t\t0x0610\n#define REG_BSSID\t\t\t\t\t\t0x0618\n#define REG_MAR\t\t\t\t\t\t\t0x0620\n#define REG_MBIDCAMCFG_1\t\t\t\t0x0628\n#define REG_MBIDCAMCFG_2\t\t\t\t0x062C\n\n#define REG_PNO_STATUS\t\t\t\t\t0x0631\n#define REG_USTIME_EDCA\t\t\t\t0x0638\n#define REG_MAC_SPEC_SIFS\t\t\t\t0x063A\n/* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */\n#define REG_RESP_SIFS_CCK\t\t\t\t0x063C\t/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */\n#define REG_RESP_SIFS_OFDM                    0x063E\t/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */\n\n#define REG_ACKTO\t\t\t\t\t\t0x0640\n#define REG_CTS2TO\t\t\t\t\t\t0x0641\n#define REG_EIFS\t\t\t\t\t\t\t0x0642\n\n/*REG_TCR*/\n#define BIT_PWRBIT_OW_EN BIT(7)\n\n/* RXERR_RPT */\n#define RXERR_TYPE_OFDM_PPDU\t\t\t0\n#define RXERR_TYPE_OFDM_FALSE_ALARM\t1\n#define RXERR_TYPE_OFDM_MPDU_OK\t\t2\n#define RXERR_TYPE_OFDM_MPDU_FAIL\t3\n#define RXERR_TYPE_CCK_PPDU\t\t\t4\n#define RXERR_TYPE_CCK_FALSE_ALARM\t5\n#define RXERR_TYPE_CCK_MPDU_OK\t\t6\n#define RXERR_TYPE_CCK_MPDU_FAIL\t\t7\n#define RXERR_TYPE_HT_PPDU\t\t\t\t8\n#define RXERR_TYPE_HT_FALSE_ALARM\t9\n#define RXERR_TYPE_HT_MPDU_TOTAL\t\t10\n#define RXERR_TYPE_HT_MPDU_OK\t\t\t11\n#define RXERR_TYPE_HT_MPDU_FAIL\t\t12\n#define RXERR_TYPE_RX_FULL_DROP\t\t15\n\n#define RXERR_COUNTER_MASK\t\t\t0xFFFFF\n#define RXERR_RPT_RST\t\t\t\t\tBIT(27)\n#define _RXERR_RPT_SEL(type)\t\t\t((type) << 28)\n\n/*\n* Note:\n*\tThe NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is\n*\talways too small, but the WiFi TestPlan test by 25,000 microseconds of NAV through sending\n*\tCTS in the air. We must update this value greater than 25,000 microseconds to pass the item.\n*\tThe offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented\n*\tby SD1 Scott.\n* By Bruce, 2011-07-18.\n*   */\n#define REG_NAV_UPPER\t\t\t\t\t0x0652\t/* unit of 128 */\n\n/* WMA, BA, CCX */\n#define REG_NAV_CTRL\t\t\t\t\t0x0650\n#define REG_BACAMCMD\t\t\t\t\t0x0654\n#define REG_BACAMCONTENT\t\t\t\t0x0658\n#define REG_LBDLY\t\t\t\t\t\t0x0660\n#define REG_FWDLY\t\t\t\t\t\t0x0661\n#define REG_RXERR_RPT\t\t\t\t\t0x0664\n#define REG_WMAC_TRXPTCL_CTL\t\t\t0x0668\n\n/* Security */\n#define REG_CAMCMD\t\t\t\t\t\t0x0670\n#define REG_CAMWRITE\t\t\t\t\t0x0674\n#define REG_CAMREAD\t\t\t\t\t0x0678\n#define REG_CAMDBG\t\t\t\t\t\t0x067C\n#define REG_SECCFG\t\t\t\t\t\t0x0680\n\n/* Power */\n#define REG_WOW_CTRL\t\t\t\t\t0x0690\n#define REG_PS_RX_INFO\t\t\t\t\t0x0692\n#define REG_WMMPS_UAPSD_TID\t\t\t0x0693\n#define REG_WKFMCAM_CMD\t\t\t\t0x0698\n#define REG_WKFMCAM_NUM\t\t\t\tREG_WKFMCAM_CMD\n#define REG_WKFMCAM_RWD\t\t\t\t0x069C\n#define REG_RXFLTMAP0\t\t\t\t\t0x06A0\n#define REG_RXFLTMAP1\t\t\t\t\t0x06A2\n#define REG_RXFLTMAP2\t\t\t\t\t0x06A4\n#define REG_BCN_PSR_RPT\t\t\t\t0x06A8\n#define REG_BT_COEX_TABLE\t\t\t\t0x06C0\n\n#define BIT_WKFCAM_WE\t\t\t\t\tBIT(16)\n#define BIT_WKFCAM_POLLING_V1\t\t\t\tBIT(31)\n#define BIT_WKFCAM_CLR_V1\t\t\t\tBIT(30)\n#define BIT_SHIFT_WKFCAM_ADDR_V2\t\t\t8\n#define BIT_MASK_WKFCAM_ADDR_V2\t\t\t0xff\n#define BIT_WKFCAM_ADDR_V2(x)\t\t\t\t(((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2)\n\n/* Hardware Port 1 */\n#define REG_MACID1\t\t\t\t\t\t0x0700\n#define REG_BSSID1\t\t\t\t\t\t0x0708\n\n/* Enable/Disable Port 0 and Port 1 for Specific ICs (ex. 8192F)*/\n#define REG_WLAN_ACT_MASK_CTRL_1\t\t0x076C\n\n/* GPIO Control */\n#define REG_SW_GPIO_SHARE_CTRL\t\t\t0x1038\n#define REG_SW_GPIO_A_OUT\t\t\t\t0x1040\n#define REG_SW_GPIO_A_OEN\t\t\t\t0x1044\n\n/* Hardware Port 2 */\n#define REG_MACID2\t\t\t\t\t\t0x1620\n#define REG_BSSID2\t\t\t\t\t\t0x1628\n/* Hardware Port 3*/\n#define REG_MACID3\t\t\t\t\t\t0x1630\n#define REG_BSSID3\t\t\t\t\t\t0x1638\n/* Hardware Port 4 */\n#define REG_MACID4\t\t\t\t\t\t0x1640\n#define REG_BSSID4\t\t\t\t\t\t0x1648\n\n\n#define REG_CR_EXT\t\t\t\t\t\t0x1100\n\n/* -----------------------------------------------------\n*\n*\t0xFE00h ~ 0xFE55h\tUSB Configuration\n*\n* ----------------------------------------------------- */\n#define REG_USB_INFO\t\t\t\t\t0xFE17\n#define REG_USB_SPECIAL_OPTION\t\t0xFE55\n#define REG_USB_DMA_AGG_TO\t\t\t0xFE5B\n#define REG_USB_AGG_TO\t\t\t\t\t0xFE5C\n#define REG_USB_AGG_TH\t\t\t\t\t0xFE5D\n\n#define REG_USB_HRPWM\t\t\t\t\t0xFE58\n#define REG_USB_HCPWM\t\t\t\t\t0xFE57\n\n/* for 92DU high_Queue low_Queue Normal_Queue select */\n#define REG_USB_High_NORMAL_Queue_Select_MAC0\t0xFE44\n/* #define REG_USB_LOW_Queue_Select_MAC0\t\t0xFE45 */\n#define REG_USB_High_NORMAL_Queue_Select_MAC1\t0xFE47\n/* #define REG_USB_LOW_Queue_Select_MAC1\t\t0xFE48 */\n\n/* For test chip */\n#define REG_TEST_USB_TXQS\t\t\t\t0xFE48\n#define REG_TEST_SIE_VID\t\t\t\t0xFE60\t\t/* 0xFE60~0xFE61 */\n#define REG_TEST_SIE_PID\t\t\t\t0xFE62\t\t/* 0xFE62~0xFE63 */\n#define REG_TEST_SIE_OPTIONAL\t\t\t0xFE64\n#define REG_TEST_SIE_CHIRP_K\t\t\t0xFE65\n#define REG_TEST_SIE_PHY\t\t\t\t0xFE66\t\t/* 0xFE66~0xFE6B */\n#define REG_TEST_SIE_MAC_ADDR\t\t\t0xFE70\t\t/* 0xFE70~0xFE75 */\n#define REG_TEST_SIE_STRING\t\t\t0xFE80\t\t/* 0xFE80~0xFEB9 */\n\n\n/* For normal chip */\n#define REG_NORMAL_SIE_VID\t\t\t\t0xFE60\t\t/* 0xFE60~0xFE61 */\n#define REG_NORMAL_SIE_PID\t\t\t\t0xFE62\t\t/* 0xFE62~0xFE63 */\n#define REG_NORMAL_SIE_OPTIONAL\t\t0xFE64\n#define REG_NORMAL_SIE_EP\t\t\t\t0xFE65\t\t/* 0xFE65~0xFE67 */\n#define REG_NORMAL_SIE_PHY\t\t\t0xFE68\t\t/* 0xFE68~0xFE6B */\n#define REG_NORMAL_SIE_OPTIONAL2\t\t0xFE6C\n#define REG_NORMAL_SIE_GPS_EP\t\t\t0xFE6D\t\t/* 0xFE6D, for RTL8723 only. */\n#define REG_NORMAL_SIE_MAC_ADDR\t\t0xFE70\t\t/* 0xFE70~0xFE75 */\n#define REG_NORMAL_SIE_STRING\t\t\t0xFE80\t\t/* 0xFE80~0xFEDF */\n\n\n/* -----------------------------------------------------\n*\n*\tRedifine 8192C register definition for compatibility\n*\n* ----------------------------------------------------- */\n\n/* TODO: use these definition when using REG_xxx naming rule.\n* NOTE: DO NOT Remove these definition. Use later. */\n\n#define EFUSE_CTRL\t\t\t\tREG_EFUSE_CTRL\t\t/* E-Fuse Control. */\n#define EFUSE_TEST\t\t\t\tREG_EFUSE_TEST\t\t/* E-Fuse Test. */\n#define MSR\t\t\t\t\t\t(REG_CR + 2)\t\t/* Media Status register */\n/* #define ISR\t\t\t\t\t\tREG_HISR */\n#define MSR1\t\t\t\t\t\tREG_CR_EXT\n\n#define TSFR\t\t\t\t\t\tREG_TSFTR\t\t\t/* Timing Sync Function Timer Register. */\n#define TSFR1\t\t\t\t\tREG_TSFTR1\t\t\t/* HW Port 1 TSF Register */\n\n#define PBP\t\t\t\t\t\tREG_PBP\n\n/* Redifine MACID register, to compatible prior ICs. */\n#define IDR0\t\t\t\t\t\tREG_MACID\t\t\t/* MAC ID Register, Offset 0x0050-0x0053 */\n#define IDR4\t\t\t\t\t\t(REG_MACID + 4)\t\t/* MAC ID Register, Offset 0x0054-0x0055 */\n\n/* Unused register */\n#define UnusedRegister\t\t\t0x1BF\n#define DCAM\t\t\t\t\tUnusedRegister\n#define PSR\t\t\t\t\t\tUnusedRegister\n#define BBAddr\t\t\t\t\tUnusedRegister\n#define PhyDataR\t\t\t\t\tUnusedRegister\n\n/* Min Spacing related settings. */\n#define MAX_MSS_DENSITY_2T\t\t\t0x13\n#define MAX_MSS_DENSITY_1T\t\t\t0x0A\n\n/* ----------------------------------------------------------------------------\n* 8192C Cmd9346CR bits\t\t\t\t\t(Offset 0xA, 16bit)\n* ---------------------------------------------------------------------------- */\n#define CmdEEPROM_En\t\t\t\tBIT(5)\t /* EEPROM enable when set 1 */\n#define CmdEERPOMSEL\t\t\t\tBIT(4)\t/* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */\n#define Cmd9346CR_9356SEL\t\t\tBIT(4)\n\n/* ----------------------------------------------------------------------------\n* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte)\n* ---------------------------------------------------------------------------- */\n#define GPIOSEL_GPIO\t\t\t\t0\n#define GPIOSEL_ENBT\t\t\t\tBIT(5)\n\n/* ----------------------------------------------------------------------------\n* 8192C GPIO PIN Control Register (offset 0x44, 4 byte)\n* ---------------------------------------------------------------------------- */\n#define GPIO_IN\t\t\t\t\tREG_GPIO_PIN_CTRL\t\t/* GPIO pins input value */\n#define GPIO_OUT\t\t\t\t(REG_GPIO_PIN_CTRL+1)\t/* GPIO pins output value */\n#define GPIO_IO_SEL\t\t\t\t(REG_GPIO_PIN_CTRL+2)\t/* GPIO pins output enable when a bit is set to \"1\"; otherwise, input is configured. */\n#define GPIO_MOD\t\t\t\t(REG_GPIO_PIN_CTRL+3)\n\n/* ----------------------------------------------------------------------------\n* 8811A GPIO PIN Control Register (offset 0x60, 4 byte)\n* ---------------------------------------------------------------------------- */\n#define GPIO_IN_8811A\t\t\tREG_GPIO_PIN_CTRL_2\t\t/* GPIO pins input value */\n#define GPIO_OUT_8811A\t\t\t(REG_GPIO_PIN_CTRL_2+1)\t/* GPIO pins output value */\n#define GPIO_IO_SEL_8811A\t\t(REG_GPIO_PIN_CTRL_2+2)\t/* GPIO pins output enable when a bit is set to \"1\"; otherwise, input is configured. */\n#define GPIO_MOD_8811A\t\t\t(REG_GPIO_PIN_CTRL_2+3)\n\n/* ----------------------------------------------------------------------------\n* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte)\n* ---------------------------------------------------------------------------- */\n#define HSIMR_GPIO12_0_INT_EN\t\t\tBIT(0)\n#define HSIMR_SPS_OCP_INT_EN\t\t\tBIT(5)\n#define HSIMR_RON_INT_EN\t\t\t\tBIT(6)\n#define HSIMR_PDN_INT_EN\t\t\t\tBIT(7)\n#define HSIMR_GPIO9_INT_EN\t\t\t\tBIT(25)\n\n/* ----------------------------------------------------------------------------\n* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte)\n* ---------------------------------------------------------------------------- */\n#define HSISR_GPIO12_0_INT\t\t\t\tBIT(0)\n#define HSISR_SPS_OCP_INT\t\t\t\tBIT(5)\n#define HSISR_RON_INT\t\t\t\t\tBIT(6)\n#define HSISR_PDNINT\t\t\t\t\tBIT(7)\n#define HSISR_GPIO9_INT\t\t\t\t\tBIT(25)\n\n/* ----------------------------------------------------------------------------\n* 8192C (MSR) Media Status Register\t(Offset 0x4C, 8 bits)\n* ---------------------------------------------------------------------------- */\n/*\nNetwork Type\n00: No link\n01: Link in ad hoc network\n10: Link in infrastructure network\n11: AP mode\nDefault: 00b.\n*/\n#define MSR_NOLINK\t\t\t\t0x00\n#define MSR_ADHOC\t\t\t\t0x01\n#define MSR_INFRA\t\t\t\t0x02\n#define MSR_AP\t\t\t\t\t0x03\n\n/* ----------------------------------------------------------------------------\n* USB INTR CONTENT\n* ---------------------------------------------------------------------------- */\n#define USB_C2H_CMDID_OFFSET\t\t\t\t\t0\n#define USB_C2H_SEQ_OFFSET\t\t\t\t\t1\n#define USB_C2H_EVENT_OFFSET\t\t\t\t\t2\n#define USB_INTR_CPWM_OFFSET\t\t\t\t\t16\n#define USB_INTR_CONTENT_C2H_OFFSET\t\t\t0\n#define USB_INTR_CONTENT_CPWM1_OFFSET\t\t16\n#define USB_INTR_CONTENT_CPWM2_OFFSET\t\t20\n#define USB_INTR_CONTENT_HISR_OFFSET\t\t\t48\n#define USB_INTR_CONTENT_HISRE_OFFSET\t\t52\n#define USB_INTR_CONTENT_LENGTH\t\t\t\t56\n\n/* WOL bit information */\n#define HAL92C_WOL_PTK_UPDATE_EVENT\t\tBIT(0)\n#define HAL92C_WOL_GTK_UPDATE_EVENT\t\tBIT(1)\n#define HAL92C_WOL_DISASSOC_EVENT\t\tBIT(2)\n#define HAL92C_WOL_DEAUTH_EVENT\t\t\tBIT(3)\n#define HAL92C_WOL_FW_DISCONNECT_EVENT\tBIT(4)\n\n\n/*----------------------------------------------------------------------------\n**      REG_CCK_CHECK\t\t\t\t\t\t(offset 0x454)\n------------------------------------------------------------------------------*/\n#define BIT_BCN_PORT_SEL\t\tBIT(5)\n#define BIT_EN_BCN_PKT_REL\t\tBIT(6)\n\n#endif /* RTW_HALMAC */\n\n/* ----------------------------------------------------------------------------\n* Response Rate Set Register\t(offset 0x440, 24bits)\n* ---------------------------------------------------------------------------- */\n#define RRSR_1M\t\t\t\t\tBIT(0)\n#define RRSR_2M\t\t\t\t\tBIT(1)\n#define RRSR_5_5M\t\t\t\tBIT(2)\n#define RRSR_11M\t\t\t\tBIT(3)\n#define RRSR_6M\t\t\t\t\tBIT(4)\n#define RRSR_9M\t\t\t\t\tBIT(5)\n#define RRSR_12M\t\t\t\tBIT(6)\n#define RRSR_18M\t\t\t\tBIT(7)\n#define RRSR_24M\t\t\t\tBIT(8)\n#define RRSR_36M\t\t\t\tBIT(9)\n#define RRSR_48M\t\t\t\tBIT(10)\n#define RRSR_54M\t\t\t\tBIT(11)\n#define RRSR_MCS0\t\t\t\tBIT(12)\n#define RRSR_MCS1\t\t\t\tBIT(13)\n#define RRSR_MCS2\t\t\t\tBIT(14)\n#define RRSR_MCS3\t\t\t\tBIT(15)\n#define RRSR_MCS4\t\t\t\tBIT(16)\n#define RRSR_MCS5\t\t\t\tBIT(17)\n#define RRSR_MCS6\t\t\t\tBIT(18)\n#define RRSR_MCS7\t\t\t\tBIT(19)\n\n#define RRSR_CCK_RATES (RRSR_11M | RRSR_5_5M | RRSR_2M | RRSR_1M)\n#define RRSR_OFDM_RATES (RRSR_54M | RRSR_48M | RRSR_36M | RRSR_24M | RRSR_18M | RRSR_12M | RRSR_9M | RRSR_6M)\n\n\n/* ----------------------------------------------------------------------------\n * Rate Definition\n * ---------------------------------------------------------------------------- */\n/* CCK */\n#define\tRATR_1M\t\t\t\t\t0x00000001\n#define\tRATR_2M\t\t\t\t\t0x00000002\n#define\tRATR_55M\t\t\t\t\t0x00000004\n#define\tRATR_11M\t\t\t\t\t0x00000008\n/* OFDM\t\t */\n#define\tRATR_6M\t\t\t\t\t0x00000010\n#define\tRATR_9M\t\t\t\t\t0x00000020\n#define\tRATR_12M\t\t\t\t\t0x00000040\n#define\tRATR_18M\t\t\t\t\t0x00000080\n#define\tRATR_24M\t\t\t\t\t0x00000100\n#define\tRATR_36M\t\t\t\t\t0x00000200\n#define\tRATR_48M\t\t\t\t\t0x00000400\n#define\tRATR_54M\t\t\t\t\t0x00000800\n/* MCS 1 Spatial Stream\t */\n#define\tRATR_MCS0\t\t\t\t\t0x00001000\n#define\tRATR_MCS1\t\t\t\t\t0x00002000\n#define\tRATR_MCS2\t\t\t\t\t0x00004000\n#define\tRATR_MCS3\t\t\t\t\t0x00008000\n#define\tRATR_MCS4\t\t\t\t\t0x00010000\n#define\tRATR_MCS5\t\t\t\t\t0x00020000\n#define\tRATR_MCS6\t\t\t\t\t0x00040000\n#define\tRATR_MCS7\t\t\t\t\t0x00080000\n/* MCS 2 Spatial Stream */\n#define\tRATR_MCS8\t\t\t\t\t0x00100000\n#define\tRATR_MCS9\t\t\t\t\t0x00200000\n#define\tRATR_MCS10\t\t\t\t\t0x00400000\n#define\tRATR_MCS11\t\t\t\t\t0x00800000\n#define\tRATR_MCS12\t\t\t\t\t0x01000000\n#define\tRATR_MCS13\t\t\t\t\t0x02000000\n#define\tRATR_MCS14\t\t\t\t\t0x04000000\n#define\tRATR_MCS15\t\t\t\t\t0x08000000\n\n/* CCK */\n#define RATE_1M\t\t\t\t\tBIT(0)\n#define RATE_2M\t\t\t\t\tBIT(1)\n#define RATE_5_5M\t\t\t\tBIT(2)\n#define RATE_11M\t\t\t\tBIT(3)\n/* OFDM */\n#define RATE_6M\t\t\t\t\tBIT(4)\n#define RATE_9M\t\t\t\t\tBIT(5)\n#define RATE_12M\t\t\t\tBIT(6)\n#define RATE_18M\t\t\t\tBIT(7)\n#define RATE_24M\t\t\t\tBIT(8)\n#define RATE_36M\t\t\t\tBIT(9)\n#define RATE_48M\t\t\t\tBIT(10)\n#define RATE_54M\t\t\t\tBIT(11)\n/* MCS 1 Spatial Stream */\n#define RATE_MCS0\t\t\t\tBIT(12)\n#define RATE_MCS1\t\t\t\tBIT(13)\n#define RATE_MCS2\t\t\t\tBIT(14)\n#define RATE_MCS3\t\t\t\tBIT(15)\n#define RATE_MCS4\t\t\t\tBIT(16)\n#define RATE_MCS5\t\t\t\tBIT(17)\n#define RATE_MCS6\t\t\t\tBIT(18)\n#define RATE_MCS7\t\t\t\tBIT(19)\n/* MCS 2 Spatial Stream */\n#define RATE_MCS8\t\t\t\tBIT(20)\n#define RATE_MCS9\t\t\t\tBIT(21)\n#define RATE_MCS10\t\t\t\tBIT(22)\n#define RATE_MCS11\t\t\t\tBIT(23)\n#define RATE_MCS12\t\t\t\tBIT(24)\n#define RATE_MCS13\t\t\t\tBIT(25)\n#define RATE_MCS14\t\t\t\tBIT(26)\n#define RATE_MCS15\t\t\t\tBIT(27)\n\n\n/* ALL CCK Rate */\n#define\tRATE_ALL_CCK\t\t\t\t(RATR_1M | RATR_2M | RATR_55M | RATR_11M)\n#define\tRATE_ALL_OFDM_AG\t\t\t(RATR_6M | RATR_9M | RATR_12M | RATR_18M | RATR_24M|\\\n\tRATR_36M | RATR_48M | RATR_54M)\n#define\tRATE_ALL_OFDM_1SS\t\t\t(RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | RATR_MCS3 |\\\n\tRATR_MCS4 | RATR_MCS5 | RATR_MCS6 | RATR_MCS7)\n#define\tRATE_ALL_OFDM_2SS\t\t\t(RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | RATR_MCS11|\\\n\tRATR_MCS12 | RATR_MCS13 | RATR_MCS14 | RATR_MCS15)\n\n#define RATE_BITMAP_ALL\t\t\t0xFFFFF\n\n/* Only use CCK 1M rate for ACK */\n#define RATE_RRSR_CCK_ONLY_1M\t\t0xFFFF1\n#define RATE_RRSR_WITHOUT_CCK\t\t0xFFFF0\n\n/* ----------------------------------------------------------------------------\n * BW_OPMODE bits\t\t\t\t(Offset 0x603, 8bit)\n * ---------------------------------------------------------------------------- */\n#define BW_OPMODE_20MHZ\t\t\tBIT(2)\n#define BW_OPMODE_5G\t\t\t\tBIT(1)\n\n/* ----------------------------------------------------------------------------\n * CAM Config Setting (offset 0x680, 1 byte)\n * ----------------------------------------------------------------------------\t\t\t */\n#define CAM_VALID\t\t\t\tBIT(15)\n#define CAM_NOTVALID\t\t\t0x0000\n#define CAM_USEDK\t\t\t\tBIT(5)\n\n#define CAM_CONTENT_COUNT\t8\n\n#define CAM_NONE\t\t\t\t0x0\n#define CAM_WEP40\t\t\t\t0x01\n#define CAM_TKIP\t\t\t\t0x02\n#define CAM_AES\t\t\t\t\t0x04\n#define CAM_WEP104\t\t\t\t0x05\n#define CAM_SMS4\t\t\t\t0x6\n\n#define TOTAL_CAM_ENTRY\t\t32\n#define HALF_CAM_ENTRY\t\t\t16\n\n#define CAM_CONFIG_USEDK\t\t_TRUE\n#define CAM_CONFIG_NO_USEDK\t_FALSE\n\n#define CAM_WRITE\t\t\t\tBIT(16)\n#define CAM_READ\t\t\t\t0x00000000\n#define CAM_POLLINIG\t\t\tBIT(31)\n\n/*\n * 10. Power Save Control Registers\n *   */\n#define WOW_PMEN\t\t\t\tBIT(0) /* Power management Enable. */\n#define WOW_WOMEN\t\t\t\tBIT(1) /* WoW function on or off. */\n#define WOW_MAGIC\t\t\t\tBIT(2) /* Magic packet */\n#define WOW_UWF\t\t\t\tBIT(3) /* Unicast Wakeup frame. */\n\n/*\n * 12. Host Interrupt Status Registers\n *\n * ----------------------------------------------------------------------------\n * 8190 IMR/ISR bits\n * ---------------------------------------------------------------------------- */\n#define IMR8190_DISABLED\t\t0x0\n#define IMR_DISABLED\t\t\t0x0\n/* IMR DW0 Bit 0-31 */\n#define IMR_BCNDMAINT6\t\t\tBIT(31)\t\t/* Beacon DMA Interrupt 6 */\n#define IMR_BCNDMAINT5\t\t\tBIT(30)\t\t/* Beacon DMA Interrupt 5 */\n#define IMR_BCNDMAINT4\t\t\tBIT(29)\t\t/* Beacon DMA Interrupt 4 */\n#define IMR_BCNDMAINT3\t\t\tBIT(28)\t\t/* Beacon DMA Interrupt 3 */\n#define IMR_BCNDMAINT2\t\t\tBIT(27)\t\t/* Beacon DMA Interrupt 2 */\n#define IMR_BCNDMAINT1\t\t\tBIT(26)\t\t/* Beacon DMA Interrupt 1 */\n#define IMR_BCNDOK8\t\t\t\tBIT(25)\t\t/* Beacon Queue DMA OK Interrupt 8 */\n#define IMR_BCNDOK7\t\t\t\tBIT(24)\t\t/* Beacon Queue DMA OK Interrupt 7 */\n#define IMR_BCNDOK6\t\t\t\tBIT(23)\t\t/* Beacon Queue DMA OK Interrupt 6 */\n#define IMR_BCNDOK5\t\t\t\tBIT(22)\t\t/* Beacon Queue DMA OK Interrupt 5 */\n#define IMR_BCNDOK4\t\t\t\tBIT(21)\t\t/* Beacon Queue DMA OK Interrupt 4 */\n#define IMR_BCNDOK3\t\t\t\tBIT(20)\t\t/* Beacon Queue DMA OK Interrupt 3 */\n#define IMR_BCNDOK2\t\t\t\tBIT(19)\t\t/* Beacon Queue DMA OK Interrupt 2 */\n#define IMR_BCNDOK1\t\t\t\tBIT(18)\t\t/* Beacon Queue DMA OK Interrupt 1 */\n#define IMR_TIMEOUT2\t\t\tBIT(17)\t\t/* Timeout interrupt 2 */\n#define IMR_TIMEOUT1\t\t\tBIT(16)\t\t/* Timeout interrupt 1 */\n#define IMR_TXFOVW\t\t\t\tBIT(15)\t\t/* Transmit FIFO Overflow */\n#define IMR_PSTIMEOUT\t\t\tBIT(14)\t\t/* Power save time out interrupt */\n#define IMR_BcnInt\t\t\t\tBIT(13)\t\t/* Beacon DMA Interrupt 0 */\n#define IMR_RXFOVW\t\t\t\tBIT(12)\t\t/* Receive FIFO Overflow */\n#define IMR_RDU\t\t\t\t\tBIT(11)\t\t/* Receive Descriptor Unavailable */\n#define IMR_ATIMEND\t\t\t\tBIT(10)\t\t/* For 92C, ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt. */\n#define IMR_BDOK\t\t\t\tBIT(9)\t\t/* Beacon Queue DMA OK Interrupt */\n#define IMR_HIGHDOK\t\t\t\tBIT(8)\t\t/* High Queue DMA OK Interrupt */\n#define IMR_TBDOK\t\t\t\tBIT(7)\t\t/* Transmit Beacon OK interrupt */\n#define IMR_MGNTDOK\t\t\tBIT(6)\t\t/* Management Queue DMA OK Interrupt */\n#define IMR_TBDER\t\t\t\tBIT(5)\t\t/* For 92C, Transmit Beacon Error Interrupt */\n#define IMR_BKDOK\t\t\t\tBIT(4)\t\t/* AC_BK DMA OK Interrupt */\n#define IMR_BEDOK\t\t\t\tBIT(3)\t\t/* AC_BE DMA OK Interrupt */\n#define IMR_VIDOK\t\t\t\tBIT(2)\t\t/* AC_VI DMA OK Interrupt */\n#define IMR_VODOK\t\t\t\tBIT(1)\t\t/* AC_VO DMA Interrupt */\n#define IMR_ROK\t\t\t\t\tBIT(0)\t\t/* Receive DMA OK Interrupt */\n\n/* 13. Host Interrupt Status Extension Register\t (Offset: 0x012C-012Eh) */\n#define IMR_TSF_BIT32_TOGGLE\tBIT(15)\n#define IMR_BcnInt_E\t\t\t\tBIT(12)\n#define IMR_TXERR\t\t\t\tBIT(11)\n#define IMR_RXERR\t\t\t\tBIT(10)\n#define IMR_C2HCMD\t\t\t\tBIT(9)\n#define IMR_CPWM\t\t\t\tBIT(8)\n/* RSVD [2-7] */\n#define IMR_OCPINT\t\t\t\tBIT(1)\n#define IMR_WLANOFF\t\t\tBIT(0)\n\n/* ----------------------------------------------------------------------------\n * 8723E series PCIE Host IMR/ISR bit\n * ---------------------------------------------------------------------------- */\n/* IMR DW0 Bit 0-31 */\n#define PHIMR_TIMEOUT2\t\t\t\tBIT(31)\n#define PHIMR_TIMEOUT1\t\t\t\tBIT(30)\n#define PHIMR_PSTIMEOUT\t\t\tBIT(29)\n#define PHIMR_GTINT4\t\t\t\tBIT(28)\n#define PHIMR_GTINT3\t\t\t\tBIT(27)\n#define PHIMR_TXBCNERR\t\t\t\tBIT(26)\n#define PHIMR_TXBCNOK\t\t\t\tBIT(25)\n#define PHIMR_TSF_BIT32_TOGGLE\tBIT(24)\n#define PHIMR_BCNDMAINT3\t\t\tBIT(23)\n#define PHIMR_BCNDMAINT2\t\t\tBIT(22)\n#define PHIMR_BCNDMAINT1\t\t\tBIT(21)\n#define PHIMR_BCNDMAINT0\t\t\tBIT(20)\n#define PHIMR_BCNDOK3\t\t\t\tBIT(19)\n#define PHIMR_BCNDOK2\t\t\t\tBIT(18)\n#define PHIMR_BCNDOK1\t\t\t\tBIT(17)\n#define PHIMR_BCNDOK0\t\t\t\tBIT(16)\n#define PHIMR_HSISR_IND_ON\t\t\tBIT(15)\n#define PHIMR_BCNDMAINT_E\t\t\tBIT(14)\n#define PHIMR_ATIMEND_E\t\t\tBIT(13)\n#define PHIMR_ATIM_CTW_END\t\tBIT(12)\n#define PHIMR_HISRE_IND\t\t\tBIT(11)\t/* RO. HISRE Indicator (HISRE & HIMRE is true, this bit is set to 1) */\n#define PHIMR_C2HCMD\t\t\t\tBIT(10)\n#define PHIMR_CPWM2\t\t\t\tBIT(9)\n#define PHIMR_CPWM\t\t\t\t\tBIT(8)\n#define PHIMR_HIGHDOK\t\t\t\tBIT(7)\t\t/* High Queue DMA OK Interrupt */\n#define PHIMR_MGNTDOK\t\t\t\tBIT(6)\t\t/* Management Queue DMA OK Interrupt */\n#define PHIMR_BKDOK\t\t\t\t\tBIT(5)\t\t/* AC_BK DMA OK Interrupt */\n#define PHIMR_BEDOK\t\t\t\t\tBIT(4)\t\t/* AC_BE DMA OK Interrupt */\n#define PHIMR_VIDOK\t\t\t\t\tBIT(3)\t\t/* AC_VI DMA OK Interrupt */\n#define PHIMR_VODOK\t\t\t\tBIT(2)\t\t/* AC_VO DMA Interrupt */\n#define PHIMR_RDU\t\t\t\t\tBIT(1)\t\t/* Receive Descriptor Unavailable */\n#define PHIMR_ROK\t\t\t\t\tBIT(0)\t\t/* Receive DMA OK Interrupt */\n\n/* PCIE Host Interrupt Status Extension bit */\n#define PHIMR_BCNDMAINT7\t\t\tBIT(23)\n#define PHIMR_BCNDMAINT6\t\t\tBIT(22)\n#define PHIMR_BCNDMAINT5\t\t\tBIT(21)\n#define PHIMR_BCNDMAINT4\t\t\tBIT(20)\n#define PHIMR_BCNDOK7\t\t\t\tBIT(19)\n#define PHIMR_BCNDOK6\t\t\t\tBIT(18)\n#define PHIMR_BCNDOK5\t\t\t\tBIT(17)\n#define PHIMR_BCNDOK4\t\t\t\tBIT(16)\n/* bit12 15: RSVD */\n#define PHIMR_TXERR\t\t\t\t\tBIT(11)\n#define PHIMR_RXERR\t\t\t\t\tBIT(10)\n#define PHIMR_TXFOVW\t\t\t\tBIT(9)\n#define PHIMR_RXFOVW\t\t\t\tBIT(8)\n/* bit2-7: RSVD */\n#define PHIMR_OCPINT\t\t\t\tBIT(1)\n/* bit0: RSVD */\n\n#define UHIMR_TIMEOUT2\t\t\t\tBIT(31)\n#define UHIMR_TIMEOUT1\t\t\t\tBIT(30)\n#define UHIMR_PSTIMEOUT\t\t\tBIT(29)\n#define UHIMR_GTINT4\t\t\t\tBIT(28)\n#define UHIMR_GTINT3\t\t\t\tBIT(27)\n#define UHIMR_TXBCNERR\t\t\t\tBIT(26)\n#define UHIMR_TXBCNOK\t\t\t\tBIT(25)\n#define UHIMR_TSF_BIT32_TOGGLE\tBIT(24)\n#define UHIMR_BCNDMAINT3\t\t\tBIT(23)\n#define UHIMR_BCNDMAINT2\t\t\tBIT(22)\n#define UHIMR_BCNDMAINT1\t\t\tBIT(21)\n#define UHIMR_BCNDMAINT0\t\t\tBIT(20)\n#define UHIMR_BCNDOK3\t\t\t\tBIT(19)\n#define UHIMR_BCNDOK2\t\t\t\tBIT(18)\n#define UHIMR_BCNDOK1\t\t\t\tBIT(17)\n#define UHIMR_BCNDOK0\t\t\t\tBIT(16)\n#define UHIMR_HSISR_IND\t\t\tBIT(15)\n#define UHIMR_BCNDMAINT_E\t\t\tBIT(14)\n/* RSVD\tBIT(13) */\n#define UHIMR_CTW_END\t\t\t\tBIT(12)\n/* RSVD\tBIT(11) */\n#define UHIMR_C2HCMD\t\t\t\tBIT(10)\n#define UHIMR_CPWM2\t\t\t\tBIT(9)\n#define UHIMR_CPWM\t\t\t\t\tBIT(8)\n#define UHIMR_HIGHDOK\t\t\t\tBIT(7)\t\t/* High Queue DMA OK Interrupt */\n#define UHIMR_MGNTDOK\t\t\t\tBIT(6)\t\t/* Management Queue DMA OK Interrupt */\n#define UHIMR_BKDOK\t\t\t\tBIT(5)\t\t/* AC_BK DMA OK Interrupt */\n#define UHIMR_BEDOK\t\t\t\tBIT(4)\t\t/* AC_BE DMA OK Interrupt */\n#define UHIMR_VIDOK\t\t\t\t\tBIT(3)\t\t/* AC_VI DMA OK Interrupt */\n#define UHIMR_VODOK\t\t\t\tBIT(2)\t\t/* AC_VO DMA Interrupt */\n#define UHIMR_RDU\t\t\t\t\tBIT(1)\t\t/* Receive Descriptor Unavailable */\n#define UHIMR_ROK\t\t\t\t\tBIT(0)\t\t/* Receive DMA OK Interrupt */\n\n/* USB Host Interrupt Status Extension bit */\n#define UHIMR_BCNDMAINT7\t\t\tBIT(23)\n#define UHIMR_BCNDMAINT6\t\t\tBIT(22)\n#define UHIMR_BCNDMAINT5\t\t\tBIT(21)\n#define UHIMR_BCNDMAINT4\t\t\tBIT(20)\n#define UHIMR_BCNDOK7\t\t\t\tBIT(19)\n#define UHIMR_BCNDOK6\t\t\t\tBIT(18)\n#define UHIMR_BCNDOK5\t\t\t\tBIT(17)\n#define UHIMR_BCNDOK4\t\t\t\tBIT(16)\n/* bit14-15: RSVD */\n#define UHIMR_ATIMEND_E\t\t\tBIT(13)\n#define UHIMR_ATIMEND\t\t\t\tBIT(12)\n#define UHIMR_TXERR\t\t\t\t\tBIT(11)\n#define UHIMR_RXERR\t\t\t\t\tBIT(10)\n#define UHIMR_TXFOVW\t\t\t\tBIT(9)\n#define UHIMR_RXFOVW\t\t\t\tBIT(8)\n/* bit2-7: RSVD */\n#define UHIMR_OCPINT\t\t\t\tBIT(1)\n/* bit0: RSVD */\n\n\n#define HAL_NIC_UNPLUG_ISR\t\t\t0xFFFFFFFF\t/* The value when the NIC is unplugged for PCI. */\n#define HAL_NIC_UNPLUG_PCI_ISR\t\t0xEAEAEAEA\t/* The value when the NIC is unplugged for PCI in PCI interrupt (page 3). */\n\n/* ----------------------------------------------------------------------------\n * 8188 IMR/ISR bits\n * ---------------------------------------------------------------------------- */\n#define IMR_DISABLED_88E\t\t\t0x0\n/* IMR DW0(0x0060-0063) Bit 0-31 */\n#define IMR_TXCCK_88E\t\t\t\tBIT(30)\t\t/* TXRPT interrupt when CCX bit of the packet is set\t */\n#define IMR_PSTIMEOUT_88E\t\t\tBIT(29)\t\t/* Power Save Time Out Interrupt */\n#define IMR_GTINT4_88E\t\t\t\tBIT(28)\t\t/* When GTIMER4 expires, this bit is set to 1\t */\n#define IMR_GTINT3_88E\t\t\t\tBIT(27)\t\t/* When GTIMER3 expires, this bit is set to 1\t */\n#define IMR_TBDER_88E\t\t\t\tBIT(26)\t\t/* Transmit Beacon0 Error\t\t\t */\n#define IMR_TBDOK_88E\t\t\t\tBIT(25)\t\t/* Transmit Beacon0 OK\t\t\t */\n#define IMR_TSF_BIT32_TOGGLE_88E\tBIT(24)\t\t/* TSF Timer BIT32 toggle indication interrupt\t\t\t */\n#define IMR_BCNDMAINT0_88E\t\tBIT(20)\t\t/* Beacon DMA Interrupt 0\t\t\t */\n#define IMR_BCNDERR0_88E\t\t\tBIT(16)\t\t/* Beacon Queue DMA Error 0 */\n#define IMR_HSISR_IND_ON_INT_88E\tBIT(15)\t\t/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)\t\t\t */\n#define IMR_BCNDMAINT_E_88E\t\tBIT(14)\t\t/* Beacon DMA Interrupt Extension for Win7\t\t\t */\n#define IMR_ATIMEND_88E\t\t\tBIT(12)\t\t/* CTWidnow End or ATIM Window End */\n#define IMR_HISR1_IND_INT_88E\t\tBIT(11)\t\t/* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */\n#define IMR_C2HCMD_88E\t\t\t\tBIT(10)\t\t/* CPU to Host Command INT Status, Write 1 clear\t */\n#define IMR_CPWM2_88E\t\t\t\tBIT(9)\t\t\t/* CPU power Mode exchange INT Status, Write 1 clear\t */\n#define IMR_CPWM_88E\t\t\t\tBIT(8)\t\t\t/* CPU power Mode exchange INT Status, Write 1 clear\t */\n#define IMR_HIGHDOK_88E\t\t\tBIT(7)\t\t\t/* High Queue DMA OK\t */\n#define IMR_MGNTDOK_88E\t\t\tBIT(6)\t\t\t/* Management Queue DMA OK\t */\n#define IMR_BKDOK_88E\t\t\t\tBIT(5)\t\t\t/* AC_BK DMA OK\t\t */\n#define IMR_BEDOK_88E\t\t\t\tBIT(4)\t\t\t/* AC_BE DMA OK\t */\n#define IMR_VIDOK_88E\t\t\t\tBIT(3)\t\t\t/* AC_VI DMA OK\t\t */\n#define IMR_VODOK_88E\t\t\t\tBIT(2)\t\t\t/* AC_VO DMA OK\t */\n#define IMR_RDU_88E\t\t\t\t\tBIT(1)\t\t\t/* Rx Descriptor Unavailable\t */\n#define IMR_ROK_88E\t\t\t\t\tBIT(0)\t\t\t/* Receive DMA OK */\n\n/* IMR DW1(0x00B4-00B7) Bit 0-31 */\n#define IMR_BCNDMAINT7_88E\t\tBIT(27)\t\t/* Beacon DMA Interrupt 7 */\n#define IMR_BCNDMAINT6_88E\t\tBIT(26)\t\t/* Beacon DMA Interrupt 6 */\n#define IMR_BCNDMAINT5_88E\t\tBIT(25)\t\t/* Beacon DMA Interrupt 5 */\n#define IMR_BCNDMAINT4_88E\t\tBIT(24)\t\t/* Beacon DMA Interrupt 4 */\n#define IMR_BCNDMAINT3_88E\t\tBIT(23)\t\t/* Beacon DMA Interrupt 3 */\n#define IMR_BCNDMAINT2_88E\t\tBIT(22)\t\t/* Beacon DMA Interrupt 2 */\n#define IMR_BCNDMAINT1_88E\t\tBIT(21)\t\t/* Beacon DMA Interrupt 1 */\n#define IMR_BCNDOK7_88E\t\t\tBIT(20)\t\t/* Beacon Queue DMA OK Interrupt 7 */\n#define IMR_BCNDOK6_88E\t\t\tBIT(19)\t\t/* Beacon Queue DMA OK Interrupt 6 */\n#define IMR_BCNDOK5_88E\t\t\tBIT(18)\t\t/* Beacon Queue DMA OK Interrupt 5 */\n#define IMR_BCNDOK4_88E\t\t\tBIT(17)\t\t/* Beacon Queue DMA OK Interrupt 4 */\n#define IMR_BCNDOK3_88E\t\t\tBIT(16)\t\t/* Beacon Queue DMA OK Interrupt 3 */\n#define IMR_BCNDOK2_88E\t\t\tBIT(15)\t\t/* Beacon Queue DMA OK Interrupt 2 */\n#define IMR_BCNDOK1_88E\t\t\tBIT(14)\t\t/* Beacon Queue DMA OK Interrupt 1 */\n#define IMR_ATIMEND_E_88E\t\t\tBIT(13)\t\t/* ATIM Window End Extension for Win7 */\n#define IMR_TXERR_88E\t\t\t\tBIT(11)\t\t/* Tx Error Flag Interrupt Status, write 1 clear. */\n#define IMR_RXERR_88E\t\t\t\tBIT(10)\t\t/* Rx Error Flag INT Status, Write 1 clear */\n#define IMR_TXFOVW_88E\t\t\t\tBIT(9)\t\t\t/* Transmit FIFO Overflow */\n#define IMR_RXFOVW_88E\t\t\t\tBIT(8)\t\t\t/* Receive FIFO Overflow */\n\n/*===================================================================\n=====================================================================\nHere the register defines are for 92C. When the define is as same with 92C,\nwe will use the 92C's define for the consistency\nSo the following defines for 92C is not entire!!!!!!\n=====================================================================\n=====================================================================*/\n/*\nBased on Datasheet V33---090401\nRegister Summary\nCurrent IOREG MAP\n0x0000h ~ 0x00FFh   System Configuration (256 Bytes)\n0x0100h ~ 0x01FFh   MACTOP General Configuration (256 Bytes)\n0x0200h ~ 0x027Fh   TXDMA Configuration (128 Bytes)\n0x0280h ~ 0x02FFh   RXDMA Configuration (128 Bytes)\n0x0300h ~ 0x03FFh   PCIE EMAC Reserved Region (256 Bytes)\n0x0400h ~ 0x04FFh   Protocol Configuration (256 Bytes)\n0x0500h ~ 0x05FFh   EDCA Configuration (256 Bytes)\n0x0600h ~ 0x07FFh   WMAC Configuration (512 Bytes)\n0x2000h ~ 0x3FFFh   8051 FW Download Region (8196 Bytes)\n*/\n/* ---------------------------------------------------------------------------- */\n/*\t\t 8192C (TXPAUSE) transmission pause \t(Offset 0x522, 8 bits) */\n/* ---------------------------------------------------------------------------- */\n/* Note:\n*\tThe the bits of stoping AC(VO/VI/BE/BK) queue in datasheet RTL8192S/RTL8192C are wrong,\n*\tthe correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, and BK - Bit3.\n*\t8723 and 88E may be not correct either in the eralier version. Confirmed with DD Tim.\n* By Bruce, 2011-09-22. */\n#define StopBecon\t\tBIT(6)\n#define StopHigh\t\t\tBIT(5)\n#define StopMgt\t\t\tBIT(4)\n#define StopBK\t\t\tBIT(3)\n#define StopBE\t\t\tBIT(2)\n#define StopVI\t\t\tBIT(1)\n#define StopVO\t\t\tBIT(0)\n\n/* ----------------------------------------------------------------------------\n * 8192C (RCR) Receive Configuration Register\t(Offset 0x608, 32 bits)\n * ---------------------------------------------------------------------------- */\n#define RCR_APPFCS\t\t\t\tBIT(31)\t/* WMAC append FCS after pauload */\n#define RCR_APP_MIC\t\t\t\tBIT(30)\t/* MACRX will retain the MIC at the bottom of the packet. */\n#define RCR_APP_ICV\t\t\t\tBIT(29)\t/* MACRX will retain the ICV at the bottom of the packet. */\n#define RCR_APP_PHYST_RXFF\t\tBIT(28)\t/* PHY Status is appended before RX packet in RXFF */\n#define RCR_APP_BA_SSN\t\t\tBIT(27)\t/* SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */\n#define RCR_VHT_DACK\t\t\tBIT(26)\t/* This bit to control response type for vht single mpdu data packet. 1. ACK as response 0. BA as response */\n#define RCR_TCPOFLD_EN\t\t\tBIT(25)\t/* Enable TCP checksum offload */\n#define RCR_ENMBID\t\t\t\tBIT(24)\t/* Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. */\n#define RCR_LSIGEN\t\t\t\tBIT(23)\t/* Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. */\n#define RCR_MFBEN\t\t\t\tBIT(22)\t/* Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. */\n#define RCR_DISCHKPPDLLEN\t\tBIT(21)\t/* Do not check PPDU while the PPDU length is smaller than 14 byte. */\n#define RCR_PKTCTL_DLEN\t\t\tBIT(20)\t/* While rx path dead lock occurs, reset rx path */\n#define RCR_DISGCLK\t\t\t\tBIT(19)\t/* Disable macrx clock gating control (no used) */\n#define RCR_TIM_PARSER_EN\t\tBIT(18)\t/* RX Beacon TIM Parser. */\n#define RCR_BC_MD_EN\t\t\tBIT(17)\t/* Broadcast data packet more data bit check interrupt enable.*/\n#define RCR_UC_MD_EN\t\t\tBIT(16)\t/* Unicast data packet more data bit check interrupt enable. */\n#define RCR_RXSK_PERPKT\t\t\tBIT(15)\t/* Executing key search per MPDU */\n#define RCR_HTC_LOC_CTRL\t\tBIT(14)\t/* MFC<--HTC = 1 MFC-->HTC = 0 */\n#define RCR_AMF\t\t\t\t\tBIT(13)\t/* Accept management type frame */\n#define RCR_ACF\t\t\t\t\tBIT(12)\t/* Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. */\n#define RCR_ADF\t\t\t\t\tBIT(11)\t/* Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). */\n#define RCR_DISDECMYPKT\t\t\tBIT(10)\t/* This bit determines whether hw need to do decryption.1: If A1 match, do decryption.0: Do decryption. */\n#define RCR_AICV\t\t\t\t\tBIT(9)\t\t/* Accept ICV error packet */\n#define RCR_ACRC32\t\t\t\tBIT(8)\t\t/* Accept CRC32 error packet */\n#define RCR_CBSSID_BCN\t\t\tBIT(7)\t\t/* Accept BSSID match packet (Rx beacon, probe rsp) */\n#define RCR_CBSSID_DATA\t\tBIT(6)\t\t/* Accept BSSID match packet (Data) */\n#define RCR_APWRMGT\t\t\tBIT(5)\t\t/* Accept power management packet */\n#define RCR_ADD3\t\t\t\tBIT(4)\t\t/* Accept address 3 match packet */\n#define RCR_AB\t\t\t\t\tBIT(3)\t\t/* Accept broadcast packet */\n#define RCR_AM\t\t\t\t\tBIT(2)\t\t/* Accept multicast packet */\n#define RCR_APM\t\t\t\t\tBIT(1)\t\t/* Accept physical match packet */\n#define RCR_AAP\t\t\t\t\tBIT(0)\t\t/* Accept all unicast packet */\n\n\n/* -----------------------------------------------------\n *\n *\t0x0000h ~ 0x00FFh\tSystem Configuration\n *\n * ----------------------------------------------------- */\n\n/* 2 SYS_ISO_CTRL */\n#define ISO_MD2PP\t\t\t\tBIT(0)\n#define ISO_UA2USB\t\t\t\tBIT(1)\n#define ISO_UD2CORE\t\t\t\tBIT(2)\n#define ISO_PA2PCIE\t\t\t\tBIT(3)\n#define ISO_PD2CORE\t\t\t\tBIT(4)\n#define ISO_IP2MAC\t\t\t\tBIT(5)\n#define ISO_DIOP\t\t\t\t\tBIT(6)\n#define ISO_DIOE\t\t\t\t\tBIT(7)\n#define ISO_EB2CORE\t\t\t\tBIT(8)\n#define ISO_DIOR\t\t\t\t\tBIT(9)\n#define PWC_EV12V\t\t\t\tBIT(15)\n\n\n/* 2 SYS_FUNC_EN */\n#define FEN_BBRSTB\t\t\t\tBIT(0)\n#define FEN_BB_GLB_RSTn\t\tBIT(1)\n#define FEN_USBA\t\t\t\tBIT(2)\n#define FEN_UPLL\t\t\t\tBIT(3)\n#define FEN_USBD\t\t\t\tBIT(4)\n#define FEN_DIO_PCIE\t\t\tBIT(5)\n#define FEN_PCIEA\t\t\t\tBIT(6)\n#define FEN_PPLL\t\t\t\t\tBIT(7)\n#define FEN_PCIED\t\t\t\tBIT(8)\n#define FEN_DIOE\t\t\t\tBIT(9)\n#define FEN_CPUEN\t\t\t\tBIT(10)\n#define FEN_DCORE\t\t\t\tBIT(11)\n#define FEN_ELDR\t\t\t\tBIT(12)\n#define FEN_EN_25_1\t\t\t\tBIT(13)\n#define FEN_HWPDN\t\t\t\tBIT(14)\n#define FEN_MREGEN\t\t\t\tBIT(15)\n\n/* 2 APS_FSMCO */\n#define PFM_LDALL\t\t\t\tBIT(0)\n#define PFM_ALDN\t\t\t\tBIT(1)\n#define PFM_LDKP\t\t\t\tBIT(2)\n#define PFM_WOWL\t\t\t\tBIT(3)\n#define EnPDN\t\t\t\t\tBIT(4)\n#define PDN_PL\t\t\t\t\tBIT(5)\n#define APFM_ONMAC\t\t\t\tBIT(8)\n#define APFM_OFF\t\t\t\tBIT(9)\n#define APFM_RSM\t\t\t\tBIT(10)\n#define AFSM_HSUS\t\t\t\tBIT(11)\n#define AFSM_PCIE\t\t\t\tBIT(12)\n#define APDM_MAC\t\t\t\tBIT(13)\n#define APDM_HOST\t\t\t\tBIT(14)\n#define APDM_HPDN\t\t\t\tBIT(15)\n#define RDY_MACON\t\t\t\tBIT(16)\n#define SUS_HOST\t\t\t\tBIT(17)\n#define ROP_ALD\t\t\t\t\tBIT(20)\n#define ROP_PWR\t\t\t\t\tBIT(21)\n#define ROP_SPS\t\t\t\t\tBIT(22)\n#define SOP_MRST\t\t\t\tBIT(25)\n#define SOP_FUSE\t\t\t\tBIT(26)\n#define SOP_ABG\t\t\t\t\tBIT(27)\n#define SOP_AMB\t\t\t\t\tBIT(28)\n#define SOP_RCK\t\t\t\t\tBIT(29)\n#define SOP_A8M\t\t\t\t\tBIT(30)\n#define XOP_BTCK\t\t\t\tBIT(31)\n\n/* 2 SYS_CLKR */\n#define ANAD16V_EN\t\t\t\tBIT(0)\n#define ANA8M\t\t\t\t\tBIT(1)\n#define MACSLP\t\t\t\t\tBIT(4)\n#define LOADER_CLK_EN\t\t\tBIT(5)\n\n\n/* 2 9346CR /REG_SYS_EEPROM_CTRL */\n#define BOOT_FROM_EEPROM\t\tBIT(4)\n#define EEPROMSEL\t\t\t\tBIT(4)\n#define EEPROM_EN\t\t\t\tBIT(5)\n\n\n/* 2 RF_CTRL */\n#define RF_EN\t\t\t\t\tBIT(0)\n#define RF_RSTB\t\t\t\t\tBIT(1)\n#define RF_SDMRSTB\t\t\t\tBIT(2)\n\n\n/* 2 LDOV12D_CTRL */\n#define LDV12_EN\t\t\t\tBIT(0)\n#define LDV12_SDBY\t\t\t\tBIT(1)\n#define LPLDO_HSM\t\t\t\tBIT(2)\n#define LPLDO_LSM_DIS\t\t\tBIT(3)\n#define _LDV12_VADJ(x)\t\t\t(((x) & 0xF) << 4)\n\n\n\n/* 2 EFUSE_TEST (For RTL8723 partially) */\n#define EF_TRPT\t\t\t\t\tBIT(7)\n#define EF_CELL_SEL\t\t\t\t(BIT(8) | BIT(9)) /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */\n#define LDOE25_EN\t\t\t\tBIT(31)\n#define EFUSE_SEL(x)\t\t\t\t(((x) & 0x3) << 8)\n#define EFUSE_SEL_MASK\t\t\t0x300\n#define EFUSE_WIFI_SEL_0\t\t0x0\n#define EFUSE_BT_SEL_0\t\t\t0x1\n#define EFUSE_BT_SEL_1\t\t\t0x2\n#define EFUSE_BT_SEL_2\t\t\t0x3\n\n/* 2 REG_GPIO_INTM\t\t\t\t(Offset 0x0048) */\n#define BIT_EXTWOL_EN \t\t\tBIT(16)\n\n/* 2 REG_LED_CFG\t\t\t\t(Offset 0x004C) */\n#define BIT_SW_SPDT_SEL\t\t\tBIT(22)\n\n/* 2 REG_SW_GPIO_SHARE_CTRL\t\t(Offset 0x1038) */\n#define BIT_BTGP_WAKE_LOC\t\t(BIT(10) | BIT(11))\n#define BIT_SW_GPIO_FUNC \t\tBIT(0)\n\n/* 2 8051FWDL\n * 2 MCUFWDL */\n#define MCUFWDL_EN\t\t\t\tBIT(0)\n#define MCUFWDL_RDY\t\t\tBIT(1)\n#define FWDL_ChkSum_rpt\t\tBIT(2)\n#define MACINI_RDY\t\t\t\tBIT(3)\n#define BBINI_RDY\t\t\t\tBIT(4)\n#define RFINI_RDY\t\t\t\tBIT(5)\n#define WINTINI_RDY\t\t\t\tBIT(6)\n#define RAM_DL_SEL\t\t\t\tBIT(7)\n#define CPU_DL_READY\t\t\tBIT(15) /* add flag  by gw for fw download ready 20130826 */\n#define ROM_DLEN\t\t\t\tBIT(19)\n#define CPRST\t\t\t\t\tBIT(23)\n\n\n/* 2 REG_SYS_CFG */\n#define XCLK_VLD\t\t\t\tBIT(0)\n#define ACLK_VLD\t\t\t\tBIT(1)\n#define UCLK_VLD\t\t\t\tBIT(2)\n#define PCLK_VLD\t\t\t\tBIT(3)\n#define PCIRSTB\t\t\t\t\tBIT(4)\n#define V15_VLD\t\t\t\t\tBIT(5)\n#define SW_OFFLOAD_EN\t\t\tBIT(7)\n#define SIC_IDLE\t\t\t\t\tBIT(8)\n#define BD_MAC2\t\t\t\t\tBIT(9)\n#define BD_MAC1\t\t\t\t\tBIT(10)\n#define IC_MACPHY_MODE\t\tBIT(11)\n#define CHIP_VER\t\t\t\t(BIT(12) | BIT(13) | BIT(14) | BIT(15))\n#define BT_FUNC\t\t\t\t\tBIT(16)\n#define VENDOR_ID\t\t\t\tBIT(19)\n#define EXT_VENDOR_ID\t\t\t(BIT(18) | BIT(19)) /* Currently only for RTL8723B */\n#define PAD_HWPD_IDN\t\t\tBIT(22)\n#define TRP_VAUX_EN\t\t\t\tBIT(23)\t/* RTL ID */\n#define TRP_BT_EN\t\t\t\tBIT(24)\n#define BD_PKG_SEL\t\t\t\tBIT(25)\n#define BD_HCI_SEL\t\t\t\tBIT(26)\n#define TYPE_ID\t\t\t\t\tBIT(27)\n#define RF_TYPE_ID\t\t\t\tBIT(27)\n\n#define RTL_ID\t\t\t\t\tBIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */\n#define SPS_SEL\t\t\t\t\tBIT(24) /* 1:LDO regulator mode; 0:Switching regulator mode */\n\n\n#define CHIP_VER_RTL_MASK\t\t0xF000\t/* Bit 12 ~ 15 */\n#define CHIP_VER_RTL_SHIFT\t\t12\n#define EXT_VENDOR_ID_SHIFT\t18\n\n/* 2 REG_GPIO_OUTSTS (For RTL8723 only) */\n#define EFS_HCI_SEL\t\t\t\t(BIT(0) | BIT(1))\n#define PAD_HCI_SEL\t\t\t\t(BIT(2) | BIT(3))\n#define HCI_SEL\t\t\t\t\t(BIT(4) | BIT(5))\n#define PKG_SEL_HCI\t\t\t\tBIT(6)\n#define FEN_GPS\t\t\t\t\tBIT(7)\n#define FEN_BT\t\t\t\t\tBIT(8)\n#define FEN_WL\t\t\t\t\tBIT(9)\n#define FEN_PCI\t\t\t\t\tBIT(10)\n#define FEN_USB\t\t\t\t\tBIT(11)\n#define BTRF_HWPDN_N\t\t\tBIT(12)\n#define WLRF_HWPDN_N\t\t\tBIT(13)\n#define PDN_BT_N\t\t\t\tBIT(14)\n#define PDN_GPS_N\t\t\t\tBIT(15)\n#define BT_CTL_HWPDN\t\t\tBIT(16)\n#define GPS_CTL_HWPDN\t\t\tBIT(17)\n#define PPHY_SUSB\t\t\t\tBIT(20)\n#define UPHY_SUSB\t\t\t\tBIT(21)\n#define PCI_SUSEN\t\t\t\tBIT(22)\n#define USB_SUSEN\t\t\t\tBIT(23)\n#define RF_RL_ID\t\t\t\t\t(BIT(31) | BIT(30) | BIT(29) | BIT(28))\n\n\n/* -----------------------------------------------------\n *\n *\t0x0100h ~ 0x01FFh\tMACTOP General Configuration\n *\n * ----------------------------------------------------- */\n\n/* 2 Function Enable Registers\n * 2 CR */\n#define HCI_TXDMA_EN\t\t\tBIT(0)\n#define HCI_RXDMA_EN\t\t\tBIT(1)\n#define TXDMA_EN\t\t\t\tBIT(2)\n#define RXDMA_EN\t\t\t\tBIT(3)\n#define PROTOCOL_EN\t\t\t\tBIT(4)\n#define SCHEDULE_EN\t\t\t\tBIT(5)\n#define MACTXEN\t\t\t\t\tBIT(6)\n#define MACRXEN\t\t\t\t\tBIT(7)\n#define ENSWBCN\t\t\t\t\tBIT(8)\n#define ENSEC\t\t\t\t\tBIT(9)\n#define CALTMR_EN\t\t\t\tBIT(10)\t/* 32k CAL TMR enable */\n\n/* Network type */\n#define _NETTYPE(x)\t\t\t\t(((x) & 0x3) << 16)\n#define MASK_NETTYPE\t\t\t0x30000\n#define NT_NO_LINK\t\t\t\t0x0\n#define NT_LINK_AD_HOC\t\t\t0x1\n#define NT_LINK_AP\t\t\t\t0x2\n#define NT_AS_AP\t\t\t\t0x3\n\n/* 2 PBP - Page Size Register */\n#define GET_RX_PAGE_SIZE(value)\t\t\t((value) & 0xF)\n#define GET_TX_PAGE_SIZE(value)\t\t\t(((value) & 0xF0) >> 4)\n#define _PSRX_MASK\t\t\t\t0xF\n#define _PSTX_MASK\t\t\t\t0xF0\n#define _PSRX(x)\t\t\t\t(x)\n#define _PSTX(x)\t\t\t\t((x) << 4)\n\n#define PBP_64\t\t\t\t\t0x0\n#define PBP_128\t\t\t\t\t0x1\n#define PBP_256\t\t\t\t\t0x2\n#define PBP_512\t\t\t\t\t0x3\n#define PBP_1024\t\t\t\t0x4\n\n\n/* 2 TX/RXDMA */\n#define RXDMA_ARBBW_EN\t\tBIT(0)\n#define RXSHFT_EN\t\t\t\tBIT(1)\n#define RXDMA_AGG_EN\t\t\tBIT(2)\n#define QS_VO_QUEUE\t\t\tBIT(8)\n#define QS_VI_QUEUE\t\t\t\tBIT(9)\n#define QS_BE_QUEUE\t\t\tBIT(10)\n#define QS_BK_QUEUE\t\t\tBIT(11)\n#define QS_MANAGER_QUEUE\t\tBIT(12)\n#define QS_HIGH_QUEUE\t\t\tBIT(13)\n\n#define HQSEL_VOQ\t\t\t\tBIT(0)\n#define HQSEL_VIQ\t\t\t\tBIT(1)\n#define HQSEL_BEQ\t\t\t\tBIT(2)\n#define HQSEL_BKQ\t\t\t\tBIT(3)\n#define HQSEL_MGTQ\t\t\t\tBIT(4)\n#define HQSEL_HIQ\t\t\t\tBIT(5)\n\n/* For normal driver, 0x10C */\n#define _TXDMA_CMQ_MAP(x)\t\t\t(((x) & 0x3) << 16)\n#define _TXDMA_HIQ_MAP(x)\t\t\t(((x) & 0x3) << 14)\n#define _TXDMA_MGQ_MAP(x)\t\t\t(((x) & 0x3) << 12)\n#define _TXDMA_BKQ_MAP(x)\t\t\t(((x) & 0x3) << 10)\n#define _TXDMA_BEQ_MAP(x)\t\t\t(((x) & 0x3) << 8)\n#define _TXDMA_VIQ_MAP(x)\t\t\t(((x) & 0x3) << 6)\n#define _TXDMA_VOQ_MAP(x)\t\t\t(((x) & 0x3) << 4)\n\n#define QUEUE_EXTRA\t\t\t\t0\n#define QUEUE_LOW\t\t\t\t1\n#define QUEUE_NORMAL\t\t\t2\n#define QUEUE_HIGH\t\t\t\t3\n#define QUEUE_EXTRA_1\t\t\t4\n#define QUEUE_EXTRA_2\t\t\t5\n\n/* 2 TRXFF_BNDY */\n\n\n/* 2 LLT_INIT */\n#define _LLT_NO_ACTIVE\t\t\t\t0x0\n#define _LLT_WRITE_ACCESS\t\t\t0x1\n#define _LLT_READ_ACCESS\t\t\t0x2\n\n#define _LLT_INIT_DATA(x)\t\t\t((x) & 0xFF)\n#define _LLT_INIT_ADDR(x)\t\t\t(((x) & 0xFF) << 8)\n#define _LLT_OP(x)\t\t\t\t\t(((x) & 0x3) << 30)\n#define _LLT_OP_VALUE(x)\t\t\t(((x) >> 30) & 0x3)\n\n\n/* -----------------------------------------------------\n *\n *\t0x0200h ~ 0x027Fh\tTXDMA Configuration\n *\n * ----------------------------------------------------- */\n/* 2 RQPN */\n#define _HPQ(x)\t\t\t\t\t((x) & 0xFF)\n#define _LPQ(x)\t\t\t\t\t(((x) & 0xFF) << 8)\n#define _PUBQ(x)\t\t\t\t\t(((x) & 0xFF) << 16)\n#define _NPQ(x)\t\t\t\t\t((x) & 0xFF)\t\t\t/* NOTE: in RQPN_NPQ register */\n#define _EPQ(x)\t\t\t\t\t(((x) & 0xFF) << 16)\t/* NOTE: in RQPN_EPQ register */\n\n\n#define HPQ_PUBLIC_DIS\t\t\tBIT(24)\n#define LPQ_PUBLIC_DIS\t\t\tBIT(25)\n#define LD_RQPN\t\t\t\t\tBIT(31)\n\n\n/* 2 TDECTL */\n#define BLK_DESC_NUM_SHIFT\t\t\t4\n#define BLK_DESC_NUM_MASK\t\t\t0xF\n\n\n/* 2 TXDMA_OFFSET_CHK */\n#define DROP_DATA_EN\t\t\t\tBIT(9)\n\n/* 2 AUTO_LLT */\n#define BIT_SHIFT_TXPKTNUM 24\n#define BIT_MASK_TXPKTNUM 0xff\n#define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM)\n\n#define BIT_TDE_DBG_SEL BIT(23)\n#define BIT_AUTO_INIT_LLT BIT(16)\n\n#define BIT_SHIFT_Tx_OQT_free_space 8\n#define BIT_MASK_Tx_OQT_free_space 0xff\n#define BIT_Tx_OQT_free_space(x) (((x) & BIT_MASK_Tx_OQT_free_space) << BIT_SHIFT_Tx_OQT_free_space)\n\n\n/* -----------------------------------------------------\n *\n *\t0x0120h ~ 0x0123h\tRX DMA Configuration\n *\n * ----------------------------------------------------- */\n#define BIT_FS_RXDONE_INT_EN\t\t\t\tBIT(16)\n\n\n/* REG_RXPKT_NUM\t\t\t\t(Offset 0x0284) */\n#define BIT_RW_RELEASE_EN\t\t\t\tBIT(18)\n\n/* -----------------------------------------------------\n *\n *\t0x0280h ~ 0x028Bh\tRX DMA Configuration\n *\n * ----------------------------------------------------- */\n\n/* 2 REG_RXDMA_CONTROL, 0x0286h\n * Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before\n * this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear.\n * #define RXPKT_RELEASE_POLL\t\t\tBIT(0)\n * Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in\n * this bit. FW can start releasing packets after RXDMA entering idle mode.\n * #define RXDMA_IDLE\t\t\t\t\tBIT(1)\n * When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host\n * completed, and stop DMA packet to host. RXDMA will then report Default: 0;\n * #define RW_RELEASE_EN\t\t\t\tBIT(2) */\n\n/* 2 REG_RXPKT_NUM, 0x0284 */\n#define\tRXPKT_RELEASE_POLL\tBIT(16)\n#define\tRXDMA_IDLE\t\t\t\tBIT(17)\n#define\tRW_RELEASE_EN\t\t\tBIT(18)\n\n/* -----------------------------------------------------\n *\n *\t0x0400h ~ 0x047Fh\tProtocol Configuration\n *\n * ----------------------------------------------------- */\n/* 2 FWHW_TXQ_CTRL */\n#define EN_AMPDU_RTY_NEW\t\t\tBIT(7)\n\n\n/* 2 SPEC SIFS */\n#define _SPEC_SIFS_CCK(x)\t\t\t((x) & 0xFF)\n#define _SPEC_SIFS_OFDM(x)\t\t\t(((x) & 0xFF) << 8)\n\n/* 2 RL */\n#define BIT_SHIFT_SRL 8\n#define BIT_MASK_SRL 0x3f\n#define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL)\n\n#define BIT_SHIFT_LRL 0\n#define BIT_MASK_LRL 0x3f\n#define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL)\n\n#define\tRL_VAL_AP\t\t\t\t\t7\n#ifdef CONFIG_RTW_CUSTOMIZE_RLSTA\n#define\tRL_VAL_STA\t\t\t\t\tCONFIG_RTW_CUSTOMIZE_RLSTA\n#else\n#define\tRL_VAL_STA\t\t\t\t\t0x30\n#endif\n/* -----------------------------------------------------\n *\n *\t0x0500h ~ 0x05FFh\tEDCA Configuration\n *\n * ----------------------------------------------------- */\n\n/* 2 EDCA setting */\n#define AC_PARAM_TXOP_LIMIT_OFFSET\t\t16\n#define AC_PARAM_ECW_MAX_OFFSET\t\t\t12\n#define AC_PARAM_ECW_MIN_OFFSET\t\t\t8\n#define AC_PARAM_AIFS_OFFSET\t\t\t\t0\n\n/* 2 BCN_CTRL */\n#define EN_TXBCN_RPT\t\t\tBIT(2)\n#define EN_BCN_FUNCTION\t\tBIT(3)\n#define STOP_BCNQ\t\t\t\tBIT(6)\n#define DIS_RX_BSSID_FIT\t\tBIT(6)\n\n#define DIS_ATIM\t\t\t\t\tBIT(0)\n#define DIS_BCNQ_SUB\t\t\tBIT(1)\n#define DIS_TSF_UDT\t\t\t\tBIT(4)\n\n/* 2 ACMHWCTRL */\n#define AcmHw_HwEn\t\t\t\tBIT(0)\n#define AcmHw_VoqEn\t\t\tBIT(1)\n#define AcmHw_ViqEn\t\t\t\tBIT(2)\n#define AcmHw_BeqEn\t\t\tBIT(3)\n#define AcmHw_VoqStatus\t\tBIT(5)\n#define AcmHw_ViqStatus\t\t\tBIT(6)\n#define AcmHw_BeqStatus\t\tBIT(7)\n\n/* 2 */ /* REG_DUAL_TSF_RST (0x553) */\n#define DUAL_TSF_RST_P2P\t\tBIT(4)\n\n/* 2 */ /* REG_NOA_DESC_SEL (0x5CF) */\n#define NOA_DESC_SEL_0\t\t\t0\n#define NOA_DESC_SEL_1\t\t\tBIT(4)\n\n/* -----------------------------------------------------\n *\n *\t0x0600h ~ 0x07FFh\tWMAC Configuration\n *\n * ----------------------------------------------------- */\n\n/* 2 APSD_CTRL */\n#define APSDOFF\t\t\t\t\tBIT(6)\n\n/* 2 TCR */\n#define TSFRST\t\t\t\t\tBIT(0)\n#define DIS_GCLK\t\t\t\t\tBIT(1)\n#define PAD_SEL\t\t\t\t\tBIT(2)\n#define PWR_ST\t\t\t\t\tBIT(6)\n#define PWRBIT_OW_EN\t\t\tBIT(7)\n#define ACRC\t\t\t\t\t\tBIT(8)\n#define CFENDFORM\t\t\t\tBIT(9)\n#define ICV\t\t\t\t\t\tBIT(10)\n\n\n/* 2 RCR */\n#define AAP\t\t\t\t\t\tBIT(0)\n#define APM\t\t\t\t\t\tBIT(1)\n#define AM\t\t\t\t\t\tBIT(2)\n#define AB\t\t\t\t\t\tBIT(3)\n#define ADD3\t\t\t\t\t\tBIT(4)\n#define APWRMGT\t\t\t\tBIT(5)\n#define CBSSID\t\t\t\t\tBIT(6)\n#define CBSSID_DATA\t\t\t\tBIT(6)\n#define CBSSID_BCN\t\t\t\tBIT(7)\n#define ACRC32\t\t\t\t\tBIT(8)\n#define AICV\t\t\t\t\t\tBIT(9)\n#define ADF\t\t\t\t\t\tBIT(11)\n#define ACF\t\t\t\t\t\tBIT(12)\n#define AMF\t\t\t\t\t\tBIT(13)\n#define HTC_LOC_CTRL\t\t\tBIT(14)\n#define UC_DATA_EN\t\t\t\tBIT(16)\n#define BM_DATA_EN\t\t\t\tBIT(17)\n#define MFBEN\t\t\t\t\tBIT(22)\n#define LSIGEN\t\t\t\t\tBIT(23)\n#define EnMBID\t\t\t\t\tBIT(24)\n#define FORCEACK\t\t\t\tBIT(26)\n#define APP_BASSN\t\t\t\tBIT(27)\n#define APP_PHYSTS\t\t\t\tBIT(28)\n#define APP_ICV\t\t\t\t\tBIT(29)\n#define APP_MIC\t\t\t\t\tBIT(30)\n#define APP_FCS\t\t\t\t\tBIT(31)\n\n\n/* 2 SECCFG */\n#define SCR_TxUseDK\t\t\t\tBIT(0)\t\t\t/* Force Tx Use Default Key */\n#define SCR_RxUseDK\t\t\t\tBIT(1)\t\t\t/* Force Rx Use Default Key */\n#define SCR_TxEncEnable\t\t\tBIT(2)\t\t\t/* Enable Tx Encryption */\n#define SCR_RxDecEnable\t\t\tBIT(3)\t\t\t/* Enable Rx Decryption */\n#define SCR_SKByA2\t\t\t\tBIT(4)\t\t\t/* Search kEY BY A2 */\n#define SCR_NoSKMC\t\t\t\tBIT(5)\t\t\t/* No Key Search Multicast */\n#define SCR_TXBCUSEDK\t\t\tBIT(6)\t\t\t/* Force Tx Broadcast packets Use Default Key */\n#define SCR_RXBCUSEDK\t\t\tBIT(7)\t\t\t/* Force Rx Broadcast packets Use Default Key */\n#define SCR_CHK_KEYID\t\t\tBIT(8)\n#define SCR_CHK_BMC\t\t\t\tBIT(9)\t\t\t/* add option to support a2+keyid+bcm */\n\n/*REG_MBIDCAMCFG           (Offset 0x0628/0x62C)*/\n#define BIT_MBIDCAM_POLL\t\tBIT(31)\n#define BIT_MBIDCAM_WT_EN\t\tBIT(30)\n\n#define MBIDCAM_ADDR_MASK\t\t0x1F\n#define MBIDCAM_ADDR_SHIFT\t\t24\n\n#define BIT_MBIDCAM_VALID\t\tBIT(23)\n#define BIT_LSIC_TXOP_EN\t\tBIT(17)\n#define BIT_CTS_EN\t\t\t\tBIT(16)\n\n/*REG_RXFLTMAP1 (Offset 0x6A2)*/\n#define BIT_CTRLFLT10EN\tBIT(10) /*PS-POLL*/\n\n/*REG_WLAN_ACT_MASK_CTRL_1\t(Offset 0x76C)*/\n#define EN_PORT_0_FUNCTION\t\tBIT(12)\n#define EN_PORT_1_FUNCTION\t\tBIT(13)\n\n/* -----------------------------------------------------\n *\n *\tSDIO Bus Specification\n *\n * ----------------------------------------------------- */\n\n/* I/O bus domain address mapping */\n#define SDIO_LOCAL_BASE\t\t0x10250000\n#define WLAN_IOREG_BASE\t\t0x10260000\n#define FIRMWARE_FIFO_BASE\t0x10270000\n#define TX_HIQ_BASE\t\t\t\t0x10310000\n#define TX_MIQ_BASE\t\t\t\t0x10320000\n#define TX_LOQ_BASE\t\t\t\t0x10330000\n#define TX_EPQ_BASE\t\t\t\t0x10350000\n#define RX_RX0FF_BASE\t\t\t0x10340000\n\n/* SDIO host local register space mapping. */\n#define SDIO_LOCAL_MSK\t\t\t\t0x0FFF\n#define WLAN_IOREG_MSK\t\t0x7FFF\n#define WLAN_FIFO_MSK\t\t\t      \t0x1FFF\t/* Aggregation Length[12:0] */\n#define WLAN_RX0FF_MSK\t\t\t\t0x0003\n\n#define SDIO_WITHOUT_REF_DEVICE_ID\t0\t/* Without reference to the SDIO Device ID */\n#define SDIO_LOCAL_DEVICE_ID           \t\t0\t/* 0b[16], 000b[15:13] */\n#define WLAN_TX_HIQ_DEVICE_ID\t\t\t4\t/* 0b[16], 100b[15:13] */\n#define WLAN_TX_MIQ_DEVICE_ID \t\t5\t/* 0b[16], 101b[15:13] */\n#define WLAN_TX_LOQ_DEVICE_ID \t\t6\t/* 0b[16], 110b[15:13] */\n#define WLAN_TX_EXQ_DEVICE_ID\t\t3\t/* 0b[16], 011b[15:13] */\n#define WLAN_RX0FF_DEVICE_ID \t\t\t7\t/* 0b[16], 111b[15:13] */\n#define WLAN_IOREG_DEVICE_ID \t\t\t8\t/* 1b[16] */\n\n/* SDIO Tx Free Page Index */\n#define HI_QUEUE_IDX\t\t\t0\n#define MID_QUEUE_IDX\t\t\t1\n#define LOW_QUEUE_IDX\t\t\t\t2\n#define PUBLIC_QUEUE_IDX\t\t\t3\n\n#define SDIO_MAX_TX_QUEUE\t\t\t3\t\t/* HIQ, MIQ and LOQ */\n#define SDIO_MAX_RX_QUEUE\t\t\t1\n\n#define SDIO_REG_TX_CTRL\t\t\t0x0000 /* SDIO Tx Control */\n#define SDIO_REG_TIMEOUT\t\t\t0x0002/*SDIO status timeout*/\n#define SDIO_REG_HIMR\t\t\t\t0x0014 /* SDIO Host Interrupt Mask */\n#define SDIO_REG_HISR\t\t\t\t0x0018 /* SDIO Host Interrupt Service Routine */\n#define SDIO_REG_HCPWM\t\t\t0x0019 /* HCI Current Power Mode */\n#define SDIO_REG_RX0_REQ_LEN\t\t0x001C /* RXDMA Request Length */\n#define SDIO_REG_OQT_FREE_PG\t\t0x001E /* OQT Free Page */\n#define SDIO_REG_FREE_TXPG\t\t\t0x0020 /* Free Tx Buffer Page */\n#define SDIO_REG_HCPWM1\t\t\t0x0024 /* HCI Current Power Mode 1 */\n#define SDIO_REG_HCPWM2\t\t\t0x0026 /* HCI Current Power Mode 2 */\n#define SDIO_REG_FREE_TXPG_SEQ\t0x0028 /* Free Tx Page Sequence */\n#define SDIO_REG_HTSFR_INFO\t\t0x0030 /* HTSF Informaion */\n#define SDIO_REG_HRPWM1\t\t\t0x0080 /* HCI Request Power Mode 1 */\n#define SDIO_REG_HRPWM2\t\t\t0x0082 /* HCI Request Power Mode 2 */\n#define SDIO_REG_HPS_CLKR\t\t\t0x0084 /* HCI Power Save Clock */\n#define SDIO_REG_HSUS_CTRL\t\t\t0x0086 /* SDIO HCI Suspend Control */\n#define SDIO_REG_HIMR_ON\t\t\t0x0090 /* SDIO Host Extension Interrupt Mask Always */\n#define SDIO_REG_HISR_ON\t\t\t0x0091 /* SDIO Host Extension Interrupt Status Always */\n\n#define SDIO_HIMR_DISABLED\t\t\t0\n\n/* RTL8723/RTL8188E SDIO Host Interrupt Mask Register */\n#define SDIO_HIMR_RX_REQUEST_MSK\t\tBIT(0)\n#define SDIO_HIMR_AVAL_MSK\t\t\tBIT(1)\n#define SDIO_HIMR_TXERR_MSK\t\t\tBIT(2)\n#define SDIO_HIMR_RXERR_MSK\t\t\tBIT(3)\n#define SDIO_HIMR_TXFOVW_MSK\t\t\tBIT(4)\n#define SDIO_HIMR_RXFOVW_MSK\t\t\tBIT(5)\n#define SDIO_HIMR_TXBCNOK_MSK\t\t\tBIT(6)\n#define SDIO_HIMR_TXBCNERR_MSK\t\tBIT(7)\n#define SDIO_HIMR_BCNERLY_INT_MSK\t\tBIT(16)\n#define SDIO_HIMR_C2HCMD_MSK\t\t\tBIT(17)\n#define SDIO_HIMR_CPWM1_MSK\t\t\tBIT(18)\n#define SDIO_HIMR_CPWM2_MSK\t\t\tBIT(19)\n#define SDIO_HIMR_HSISR_IND_MSK\t\tBIT(20)\n#define SDIO_HIMR_GTINT3_IND_MSK\t\tBIT(21)\n#define SDIO_HIMR_GTINT4_IND_MSK\t\tBIT(22)\n#define SDIO_HIMR_PSTIMEOUT_MSK\t\tBIT(23)\n#define SDIO_HIMR_OCPINT_MSK\t\t\tBIT(24)\n#define SDIO_HIMR_ATIMEND_MSK\t\t\tBIT(25)\n#define SDIO_HIMR_ATIMEND_E_MSK\t\tBIT(26)\n#define SDIO_HIMR_CTWEND_MSK\t\t\tBIT(27)\n\n/* RTL8188E SDIO Specific */\n#define SDIO_HIMR_MCU_ERR_MSK\t\t\tBIT(28)\n#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK\t\tBIT(29)\n\n/* SDIO Host Interrupt Service Routine */\n#define SDIO_HISR_RX_REQUEST\t\t\tBIT(0)\n#define SDIO_HISR_AVAL\t\t\t\t\tBIT(1)\n#define SDIO_HISR_TXERR\t\t\t\t\tBIT(2)\n#define SDIO_HISR_RXERR\t\t\t\t\tBIT(3)\n#define SDIO_HISR_TXFOVW\t\t\t\tBIT(4)\n#define SDIO_HISR_RXFOVW\t\t\t\tBIT(5)\n#define SDIO_HISR_TXBCNOK\t\t\t\tBIT(6)\n#define SDIO_HISR_TXBCNERR\t\t\t\tBIT(7)\n#define SDIO_HISR_BCNERLY_INT\t\t\tBIT(16)\n#define SDIO_HISR_C2HCMD\t\t\t\tBIT(17)\n#define SDIO_HISR_CPWM1\t\t\t\tBIT(18)\n#define SDIO_HISR_CPWM2\t\t\t\tBIT(19)\n#define SDIO_HISR_HSISR_IND\t\t\tBIT(20)\n#define SDIO_HISR_GTINT3_IND\t\t\tBIT(21)\n#define SDIO_HISR_GTINT4_IND\t\t\tBIT(22)\n#define SDIO_HISR_PSTIMEOUT\t\t\tBIT(23)\n#define SDIO_HISR_OCPINT\t\t\t\tBIT(24)\n#define SDIO_HISR_ATIMEND\t\t\t\tBIT(25)\n#define SDIO_HISR_ATIMEND_E\t\t\tBIT(26)\n#define SDIO_HISR_CTWEND\t\t\t\tBIT(27)\n\n/* RTL8188E SDIO Specific */\n#define SDIO_HISR_MCU_ERR\t\t\t\tBIT(28)\n#define SDIO_HISR_TSF_BIT32_TOGGLE\tBIT(29)\n\n#define MASK_SDIO_HISR_CLEAR\t\t(SDIO_HISR_TXERR |\\\n\t\tSDIO_HISR_RXERR |\\\n\t\tSDIO_HISR_TXFOVW |\\\n\t\tSDIO_HISR_RXFOVW |\\\n\t\tSDIO_HISR_TXBCNOK |\\\n\t\tSDIO_HISR_TXBCNERR |\\\n\t\tSDIO_HISR_C2HCMD |\\\n\t\tSDIO_HISR_CPWM1 |\\\n\t\tSDIO_HISR_CPWM2 |\\\n\t\tSDIO_HISR_HSISR_IND |\\\n\t\tSDIO_HISR_GTINT3_IND |\\\n\t\tSDIO_HISR_GTINT4_IND |\\\n\t\tSDIO_HISR_PSTIMEOUT |\\\n\t\tSDIO_HISR_OCPINT)\n\n/* SDIO HCI Suspend Control Register */\n#define HCI_RESUME_PWR_RDY\t\t\tBIT(1)\n#define HCI_SUS_CTRL\t\t\t\t\tBIT(0)\n\n/* SDIO Tx FIFO related */\n#define SDIO_TX_FREE_PG_QUEUE\t\t\t4\t/* The number of Tx FIFO free page */\n#define SDIO_TX_FIFO_PAGE_SZ\t\t\t128\n\n/* indirect access */\n#ifdef CONFIG_SDIO_INDIRECT_ACCESS\n#define SDIO_REG_INDIRECT_REG_CFG\t\t0x40\n#define SDIO_REG_INDIRECT_REG_DATA\t0x44\n#define SET_INDIRECT_REG_ADDR(_cmd, _addr)\tSET_BITS_TO_LE_2BYTE(((u8 *)(_cmd)) + 0, 0, 16, (_addr))\n#define SET_INDIRECT_REG_SIZE_1BYTE(_cmd)\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 0)\n#define SET_INDIRECT_REG_SIZE_2BYTE(_cmd)\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 1)\n#define SET_INDIRECT_REG_SIZE_4BYTE(_cmd)\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 2)\n#define SET_INDIRECT_REG_WRITE(_cmd)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 2, 1, 1)\n#define SET_INDIRECT_REG_READ(_cmd)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 3, 1, 1)\n#define GET_INDIRECT_REG_RDY(_cmd)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_cmd)) + 2, 4, 1)\n#endif/*CONFIG_SDIO_INDIRECT_ACCESS*/\n\n#ifdef CONFIG_SDIO_HCI\n\t#define MAX_TX_AGG_PACKET_NUMBER\t0x8\n#else\n\t#define MAX_TX_AGG_PACKET_NUMBER\t0xFF\n\t#define MAX_TX_AGG_PACKET_NUMBER_8812\t64\n#endif\n\n/* -----------------------------------------------------\n *\n *\t0xFE00h ~ 0xFE55h\tUSB Configuration\n *\n * ----------------------------------------------------- */\n\n/* 2 USB Information (0xFE17) */\n#define USB_IS_HIGH_SPEED\t\t\t0\n#define USB_IS_FULL_SPEED\t\t\t1\n#define USB_SPEED_MASK\t\t\t\tBIT(5)\n\n#define USB_NORMAL_SIE_EP_MASK\t0xF\n#define USB_NORMAL_SIE_EP_SHIFT\t4\n\n/* 2 Special Option */\n#define USB_AGG_EN\t\t\t\tBIT(3)\n\n/* 0; Use interrupt endpoint to upload interrupt pkt\n * 1; Use bulk endpoint to upload interrupt pkt, */\n#define INT_BULK_SEL\t\t\tBIT(4)\n\n/* 2REG_C2HEVT_CLEAR */\n#define C2H_EVT_HOST_CLOSE\t\t0x00\t/* Set by driver and notify FW that the driver has read the C2H command message */\n#define C2H_EVT_FW_CLOSE\t\t0xFF\t/* Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. */\n\n\n/* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */\n#define WL_HWPDN_EN\t\t\tBIT(0)\t/* Enable GPIO[9] as WiFi HW PDn source */\n#define WL_HWPDN_SL\t\t\tBIT(1)\t/* WiFi HW PDn polarity control */\n#define WL_FUNC_EN\t\t\t\tBIT(2)\t/* WiFi function enable */\n#define WL_HWROF_EN\t\t\tBIT(3)\t/* Enable GPIO[9] as WiFi RF HW PDn source */\n#define BT_HWPDN_EN\t\t\tBIT(16)\t/* Enable GPIO[11] as BT HW PDn source */\n#define BT_HWPDN_SL\t\t\tBIT(17)\t/* BT HW PDn polarity control */\n#define BT_FUNC_EN\t\t\t\tBIT(18)\t/* BT function enable */\n#define BT_HWROF_EN\t\t\tBIT(19)\t/* Enable GPIO[11] as BT/GPS RF HW PDn source */\n#define GPS_HWPDN_EN\t\t\tBIT(20)\t/* Enable GPIO[10] as GPS HW PDn source */\n#define GPS_HWPDN_SL\t\t\tBIT(21)\t/* GPS HW PDn polarity control */\n#define GPS_FUNC_EN\t\t\tBIT(22)\t/* GPS function enable */\n\n/* 3 REG_LIFECTRL_CTRL */\n#define HAL92C_EN_PKT_LIFE_TIME_BK\t\tBIT(3)\n#define HAL92C_EN_PKT_LIFE_TIME_BE\t\tBIT(2)\n#define HAL92C_EN_PKT_LIFE_TIME_VI\t\tBIT(1)\n#define HAL92C_EN_PKT_LIFE_TIME_VO\t\tBIT(0)\n\n#define HAL92C_MSDU_LIFE_TIME_UNIT\t\t128\t/* in us, said by Tim. */\n\n/* 2 8192D PartNo. */\n#define PARTNO_92D_NIC\t\t\t\t\t\t\t(BIT7 | BIT6)\n#define PARTNO_92D_NIC_REMARK\t\t\t\t(BIT5 | BIT4)\n#define PARTNO_SINGLE_BAND_VS\t\t\t\tBIT(3)\n#define PARTNO_SINGLE_BAND_VS_REMARK\t\tBIT(1)\n#define PARTNO_CONCURRENT_BAND_VC\t\t\t(BIT3 | BIT2)\n#define PARTNO_CONCURRENT_BAND_VC_REMARK\t(BIT1 | BIT0)\n\n/* ********************************************************\n * General definitions\n * ******************************************************** */\n\n#ifdef CONFIG_USB_HCI\n\t#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter)\t(175)\n#else\n\t#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter)\t(IS_VENDOR_8188E_I_CUT_SERIES(__Adapter) ? 255 : 175)\n#endif\n#define LAST_ENTRY_OF_TX_PKT_BUFFER_8812\t\t\t255\n#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B\t\t255\n#define LAST_ENTRY_OF_TX_PKT_BUFFER_8192C\t\t255\n#define LAST_ENTRY_OF_TX_PKT_BUFFER_8703B\t\t255\n#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC\t127\n#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188F\t\t255\n#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188GTV\t\t255\n#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723D\t\t255\n#define LAST_ENTRY_OF_TX_PKT_BUFFER_8710B\t\t255\n#define LAST_ENTRY_OF_TX_PKT_BUFFER_8192F\t\t255\n#define POLLING_LLT_THRESHOLD\t\t\t\t20\n#if defined(CONFIG_RTL8723B) && defined(CONFIG_PCI_HCI)\n\t#define POLLING_READY_TIMEOUT_COUNT\t\t6000\n#else\n\t#define POLLING_READY_TIMEOUT_COUNT\t\t1000\n#endif\n\n\n/* GPIO BIT */\n#define\tHAL_8812A_HW_GPIO_WPS_BIT\tBIT(2)\n#define\tHAL_8192C_HW_GPIO_WPS_BIT\tBIT(2)\n#define\tHAL_8192EU_HW_GPIO_WPS_BIT\tBIT(7)\n#define\tHAL_8188E_HW_GPIO_WPS_BIT\tBIT(7)\n\n#endif /* __HAL_COMMON_H__ */\n"
  },
  {
    "path": "include/hal_data.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HAL_DATA_H__\n#define __HAL_DATA_H__\n\n#if 1/* def  CONFIG_SINGLE_IMG */\n\n#include \"../hal/phydm/phydm_precomp.h\"\n#ifdef CONFIG_BT_COEXIST\n\t#include <hal_btcoex.h>\n#endif\n\t#include <hal_btcoex_wifionly.h>\n\n#ifdef CONFIG_SDIO_HCI\n\t#include <hal_sdio.h>\n#endif\n#ifdef CONFIG_GSPI_HCI\n\t#include <hal_gspi.h>\n#endif\n\n#if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)\n#include \"../hal/hal_dm_acs.h\"\n#endif\n\n/*\n * <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.\n *   */\ntypedef enum _RT_MULTI_FUNC {\n\tRT_MULTI_FUNC_NONE\t= 0x00,\n\tRT_MULTI_FUNC_WIFI\t= 0x01,\n\tRT_MULTI_FUNC_BT\t\t= 0x02,\n\tRT_MULTI_FUNC_GPS\t= 0x04,\n} RT_MULTI_FUNC, *PRT_MULTI_FUNC;\n/*\n * <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.\n *   */\ntypedef enum _RT_POLARITY_CTL {\n\tRT_POLARITY_LOW_ACT\t= 0,\n\tRT_POLARITY_HIGH_ACT\t= 1,\n} RT_POLARITY_CTL, *PRT_POLARITY_CTL;\n\n/* For RTL8723 regulator mode. by tynli. 2011.01.14. */\ntypedef enum _RT_REGULATOR_MODE {\n\tRT_SWITCHING_REGULATOR\t= 0,\n\tRT_LDO_REGULATOR\t\t\t= 1,\n} RT_REGULATOR_MODE, *PRT_REGULATOR_MODE;\n\n/*\n * Interface type.\n *   */\ntypedef\tenum _INTERFACE_SELECT_PCIE {\n\tINTF_SEL0_SOLO_MINICARD\t\t\t= 0,\t\t/* WiFi solo-mCard */\n\tINTF_SEL1_BT_COMBO_MINICARD\t\t= 1,\t\t/* WiFi+BT combo-mCard */\n\tINTF_SEL2_PCIe\t\t\t\t\t\t= 2,\t\t/* PCIe Card */\n} INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE;\n\n\ntypedef\tenum _INTERFACE_SELECT_USB {\n\tINTF_SEL0_USB \t\t\t\t= 0,\t\t/* USB */\n\tINTF_SEL1_USB_High_Power  \t= 1,\t\t/* USB with high power PA */\n\tINTF_SEL2_MINICARD\t\t  \t= 2,\t\t/* Minicard */\n\tINTF_SEL3_USB_Solo \t\t= 3,\t\t/* USB solo-Slim module */\n\tINTF_SEL4_USB_Combo\t\t= 4,\t\t/* USB Combo-Slim module */\n\tINTF_SEL5_USB_Combo_MF\t= 5,\t\t/* USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card */\n} INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB;\n\ntypedef enum _RT_AMPDU_BRUST_MODE {\n\tRT_AMPDU_BRUST_NONE\t\t= 0,\n\tRT_AMPDU_BRUST_92D\t\t= 1,\n\tRT_AMPDU_BRUST_88E\t\t= 2,\n\tRT_AMPDU_BRUST_8812_4\t= 3,\n\tRT_AMPDU_BRUST_8812_8\t= 4,\n\tRT_AMPDU_BRUST_8812_12\t= 5,\n\tRT_AMPDU_BRUST_8812_15\t= 6,\n\tRT_AMPDU_BRUST_8723B\t\t= 7,\n} RT_AMPDU_BRUST, *PRT_AMPDU_BRUST_MODE;\n\n/* Tx Power Limit Table Size */\n#define MAX_REGULATION_NUM\t\t\t\t\t\t4\n#define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE\t4\n#define MAX_2_4G_BANDWIDTH_NUM\t\t\t\t\t2\n#define MAX_RATE_SECTION_NUM\t\t\t\t\t\t10\n#define MAX_5G_BANDWIDTH_NUM\t\t\t\t\t\t4\n\n#define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G\t\t\t10 /* CCK:1, OFDM:1, HT:4, VHT:4 */\n#define MAX_BASE_NUM_IN_PHY_REG_PG_5G\t\t\t9 /* OFDM:1, HT:4, VHT:4 */\n\n#ifdef RTW_RX_AGGREGATION\ntypedef enum _RX_AGG_MODE {\n\tRX_AGG_DISABLE,\n\tRX_AGG_DMA,\n\tRX_AGG_USB,\n\tRX_AGG_MIX\n} RX_AGG_MODE;\n\n/* #define MAX_RX_DMA_BUFFER_SIZE\t10240 */\t\t/* 10K for 8192C RX DMA buffer */\n\n#endif /* RTW_RX_AGGREGATION */\n\n#ifdef CONFIG_SDIO_HCI\n#ifdef CONFIG_SDIO_MONITOR\ntypedef enum _SDIO_MONITOR_MODE {\n\tSDIO_MONITOR_MODE_DISABLE,\n\tSDIO_MONITOR_MODE_INT_LAT,\n\tSDIO_MONITOR_MODE_CMD53W_INTVL,\n\tSDIO_MONITOR_MODE_SDIO_CLK_5US,\n\tSDIO_MONITOR_MODE_SDIO_CLK_50US,\n\tSDIO_MONITOR_MODE_SDIO_CLK_9MS,\n\tSDIO_MONITOR_MODE_MAX\n} SDIO_MONITOR_MODE;\n#endif\n#endif\n\n/* E-Fuse */\n#ifdef CONFIG_RTL8188E\n\t#define EFUSE_MAP_SIZE\t512\n#endif\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)\n\t#define EFUSE_MAP_SIZE\t512\n#endif\n#ifdef CONFIG_RTL8192E\n\t#define EFUSE_MAP_SIZE\t512\n#endif\n#ifdef CONFIG_RTL8723B\n\t#define EFUSE_MAP_SIZE\t512\n#endif\n#ifdef CONFIG_RTL8814A\n\t#define EFUSE_MAP_SIZE\t512\n#endif\n#ifdef CONFIG_RTL8703B\n\t#define EFUSE_MAP_SIZE\t512\n#endif\n#ifdef CONFIG_RTL8723D\n\t#define EFUSE_MAP_SIZE\t512\n#endif\n#ifdef CONFIG_RTL8188F\n\t#define EFUSE_MAP_SIZE\t512\n#endif\n#ifdef CONFIG_RTL8188GTV\n\t#define EFUSE_MAP_SIZE\t512\n#endif\n#ifdef CONFIG_RTL8710B\n\t#define EFUSE_MAP_SIZE\t512\n#endif\n#ifdef CONFIG_RTL8192F\n\t#define EFUSE_MAP_SIZE\t512\n#endif\n\n#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)\n\t#define EFUSE_MAX_SIZE\t1024\n#elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8710B)\n\t#define EFUSE_MAX_SIZE\t256\n#else\n\t#define EFUSE_MAX_SIZE\t512\n#endif\n/* end of E-Fuse */\n\n#define Mac_OFDM_OK\t\t\t0x00000000\n#define Mac_OFDM_Fail\t\t0x10000000\n#define Mac_OFDM_FasleAlarm\t0x20000000\n#define Mac_CCK_OK\t\t\t0x30000000\n#define Mac_CCK_Fail\t\t0x40000000\n#define Mac_CCK_FasleAlarm\t0x50000000\n#define Mac_HT_OK\t\t\t0x60000000\n#define Mac_HT_Fail\t\t\t0x70000000\n#define Mac_HT_FasleAlarm\t0x90000000\n#define Mac_DropPacket\t\t0xA0000000\n\n#ifdef CONFIG_RF_POWER_TRIM\n#if defined(CONFIG_RTL8723B)\n\t#define REG_RF_BB_GAIN_OFFSET\t0x7f\n\t#define RF_GAIN_OFFSET_MASK\t\t0xfffff\n#elif defined(CONFIG_RTL8188E)\n\t#define REG_RF_BB_GAIN_OFFSET\t0x55\n\t#define RF_GAIN_OFFSET_MASK\t\t0xfffff\n#else\n\t#define REG_RF_BB_GAIN_OFFSET\t0x55\n\t#define RF_GAIN_OFFSET_MASK\t\t0xfffff\n#endif /* CONFIG_RTL8723B */\n#endif /*CONFIG_RF_POWER_TRIM*/\n\n/* For store initial value of BB register */\ntypedef struct _BB_INIT_REGISTER {\n\tu16\toffset;\n\tu32\tvalue;\n\n} BB_INIT_REGISTER, *PBB_INIT_REGISTER;\n\n#define PAGE_SIZE_128\t128\n#define PAGE_SIZE_256\t256\n#define PAGE_SIZE_512\t512\n\n#define HCI_SUS_ENTER\t\t0\n#define HCI_SUS_LEAVING\t\t1\n#define HCI_SUS_LEAVE\t\t2\n#define HCI_SUS_ENTERING\t3\n#define HCI_SUS_ERR\t\t\t4\n\n#define EFUSE_FILE_UNUSED 0\n#define EFUSE_FILE_FAILED 1\n#define EFUSE_FILE_LOADED 2\n\n#define MACADDR_FILE_UNUSED 0\n#define MACADDR_FILE_FAILED 1\n#define MACADDR_FILE_LOADED 2\n\n#define MAX_IQK_INFO_BACKUP_CHNL_NUM\t5\n#define MAX_IQK_INFO_BACKUP_REG_NUM\t\t10\n\n#ifdef CONFIG_SDIO_MONITOR\n#define SDIO_MONITOR_MAX_SAMPLE_NUM\t10000\n#endif\n\nstruct kfree_data_t {\n\tu8 flag;\n\ts8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX];\n\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\ts8 pa_bias_5g[RF_PATH_MAX];\n\ts8 pad_bias_5g[RF_PATH_MAX];\n#endif\n\ts8 thermal;\n};\n\nbool kfree_data_is_bb_gain_empty(struct kfree_data_t *data);\n\nstruct hal_spec_t {\n\tchar *ic_name;\n\tu8 macid_num;\n\n\tu8 sec_cam_ent_num;\n\tu8 sec_cap;\n\n\tu8 rfpath_num_2g:4;\t/* used for tx power index path */\n\tu8 rfpath_num_5g:4;\t/* used for tx power index path */\n\tu8 txgi_max; /* maximum tx power gain index */\n\tu8 txgi_pdbm; /* tx power gain index per dBm */\n\n\tu8 max_tx_cnt;\n\tu8 tx_nss_num:4;\n\tu8 rx_nss_num:4;\n\tu8 band_cap;\t/* value of BAND_CAP_XXX */\n\tu8 bw_cap;\t\t/* value of BW_CAP_XXX */\n\tu8 port_num;\n\tu8 proto_cap;\t/* value of PROTO_CAP_XXX */\n\tu8 wl_func;\t\t/* value of WL_FUNC_XXX */\n\n#if CONFIG_TX_AC_LIFETIME\n\tu8 tx_aclt_unit_factor; /* how many 32us */\n#endif\n\n\tu8 rx_tsf_filter:1;\n\n\tu8 pg_txpwr_saddr; /* starting address of PG tx power info */\n\tu8 pg_txgi_diff_factor; /* PG tx power gain index diff to tx power gain index */\n\n\tu8 hci_type;\t/* value of HCI Type */\n};\n\n#define HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) ((_spec)->rfpath_num_2g > (_path))\n#define HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) ((_spec)->rfpath_num_5g > (_path))\n#define HAL_SPEC_CHK_RF_PATH(_spec, _band, _path) ( \\\n\t_band == BAND_ON_2_4G ? HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) : \\\n\t_band == BAND_ON_5G ? HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) : 0)\n\n#define HAL_SPEC_CHK_TX_CNT(_spec, _cnt_idx) ((_spec)->max_tx_cnt > (_cnt_idx))\n\n#ifdef CONFIG_PHY_CAPABILITY_QUERY\nstruct phy_spec_t {\n\tu32 trx_cap;\n\tu32 stbc_cap;\n\tu32 ldpc_cap;\n\tu32 txbf_param;\n\tu32 txbf_cap;\n};\n#endif\nstruct hal_iqk_reg_backup {\n\tu8 central_chnl;\n\tu8 bw_mode;\n\tu32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM];\n};\n\n\ntypedef struct hal_p2p_ps_para {\n\t/*DW0*/\n\tu8  offload_en:1;\n\tu8  role:1;\n\tu8  ctwindow_en:1;\n\tu8  noa_en:1;\n\tu8  noa_sel:1;\n\tu8  all_sta_sleep:1;\n\tu8  discovery:1;\n\tu8  disable_close_rf:1;\n\tu8  p2p_port_id;\n\tu8  p2p_group;\n\tu8  p2p_macid;\n\n\t/*DW1*/\n\tu8 ctwindow_length;\n\tu8 rsvd3;\n\tu8 rsvd4;\n\tu8 rsvd5;\n\n\t/*DW2*/\n\tu32 noa_duration_para;\n\n\t/*DW3*/\n\tu32 noa_interval_para;\n\n\t/*DW4*/\n\tu32 noa_start_time_para;\n\n\t/*DW5*/\n\tu32 noa_count_para;\n} HAL_P2P_PS_PARA, *PHAL_P2P_PS_PARA;\n\n#define TXPWR_LMT_RS_CCK\t0\n#define TXPWR_LMT_RS_OFDM\t1\n#define TXPWR_LMT_RS_HT\t\t2\n#define TXPWR_LMT_RS_VHT\t3\n#define TXPWR_LMT_RS_NUM\t4\n\n#define TXPWR_LMT_RS_NUM_2G\t4 /* CCK, OFDM, HT, VHT */\n#define TXPWR_LMT_RS_NUM_5G\t3 /* OFDM, HT, VHT */\n\n#if CONFIG_TXPWR_LIMIT\nextern const char *const _txpwr_lmt_rs_str[];\n#define txpwr_lmt_rs_str(rs) (((rs) >= TXPWR_LMT_RS_NUM) ? _txpwr_lmt_rs_str[TXPWR_LMT_RS_NUM] : _txpwr_lmt_rs_str[(rs)])\n\nstruct txpwr_lmt_ent {\n\t_list list;\n\n\ts8 lmt_2g[MAX_2_4G_BANDWIDTH_NUM]\n\t\t[TXPWR_LMT_RS_NUM_2G]\n\t\t[CENTER_CH_2G_NUM]\n\t\t[MAX_TX_COUNT];\n\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\ts8 lmt_5g[MAX_5G_BANDWIDTH_NUM]\n\t\t[TXPWR_LMT_RS_NUM_5G]\n\t\t[CENTER_CH_5G_ALL_NUM]\n\t\t[MAX_TX_COUNT];\n#endif\n\n\tchar regd_name[0];\n};\n#endif /* CONFIG_TXPWR_LIMIT */\n\ntypedef struct hal_com_data {\n\tHAL_VERSION\t\t\tversion_id;\n\tRT_MULTI_FUNC\t\tMultiFunc; /* For multi-function consideration. */\n\tRT_POLARITY_CTL\t\tPolarityCtl; /* For Wifi PDn Polarity control. */\n\tRT_REGULATOR_MODE\tRegulatorMode; /* switching regulator or LDO */\n\tu8\thw_init_completed;\n\t/****** FW related ******/\n\tu32 firmware_size;\n\tu16 firmware_version;\n\tu16\tFirmwareVersionRev;\n\tu16 firmware_sub_version;\n\tu16\tFirmwareSignature;\n\tu8\tRegFWOffload;\n\tu8\tbFWReady;\n\tu8\tbBTFWReady;\n\tu8\tfw_ractrl;\n\tu8\tLastHMEBoxNum;\t/* H2C - for host message to fw */\n#ifdef CONFIG_LPS_1T1R\n\tu8 lps_1t1r;\n#endif\n\n\t/****** current WIFI_PHY values ******/\n\tWIRELESS_MODE\tCurrentWirelessMode;\n\tenum channel_width current_channel_bw;\n\tBAND_TYPE\t\tcurrent_band_type;\t/* 0:2.4G, 1:5G */\n\tBAND_TYPE\t\tBandSet;\n\tu8\t\t\t\tcurrent_channel;\n\tu8\t\t\t\tcch_20;\n\tu8\t\t\t\tcch_40;\n\tu8\t\t\t\tcch_80;\n\tu8\t\t\t\tCurrentCenterFrequencyIndex1;\n\tu8\t\t\t\tnCur40MhzPrimeSC;\t/* Control channel sub-carrier */\n\tu8\t\t\t\tnCur80MhzPrimeSC;   /* used for primary 40MHz of 80MHz mode */\n\tBOOLEAN\t\tbSwChnlAndSetBWInProgress;\n\tu8\t\t\t\tbDisableSWChannelPlan; /* flag of disable software change channel plan\t */\n\tu16\t\t\t\tBasicRateSet;\n\tu32\t\t\t\tReceiveConfig;\n\tu32\t\t\t\trcr_backup; /* used for switching back from monitor mode */\n\tu8\t\t\t\trx_tsf_addr_filter_config; /* for 8822B/8821C USE */\n\tBOOLEAN\t\t\tbSwChnl;\n\tBOOLEAN\t\t\tbSetChnlBW;\n\tBOOLEAN\t\t\tbSWToBW40M;\n\tBOOLEAN\t\t\tbSWToBW80M;\n\tBOOLEAN\t\t\tbChnlBWInitialized;\n\tu32\t\t\t\tBackUp_BB_REG_4_2nd_CCA[3];\n\n#ifdef CONFIG_RTW_ACS\n\tstruct auto_chan_sel acs;\n#endif\n#ifdef CONFIG_BCN_RECOVERY\n\tu8 issue_bcn_fail;\n#endif /*CONFIG_BCN_RECOVERY*/\n\n\t/****** rf_ctrl *****/\n\tu8\trf_chip;\n\tu8\trf_type;\t/*enum rf_type*/\n\tu8\tPackageType;\n\tu8\tNumTotalRFPath;\n\tu8\tantenna_test;\n\n\t/****** Debug ******/\n\tu16\tForcedDataRate;\t/* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */\n\tu8\tbDumpRxPkt;\n\tu8\tbDumpTxPkt;\n\tu8\tdis_turboedca; /* 1: disable turboedca, \n\t\t\t\t\t\t  2: disable turboedca and setting EDCA parameter based on the input parameter*/\n\tu32 edca_param_mode;\n\n\t/****** EEPROM setting.******/\n\tu8\tbautoload_fail_flag;\n\tu8\tefuse_file_status;\n\tu8\tmacaddr_file_status;\n\tu8\tEepromOrEfuse;\n\tu8\tefuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/\n\tu8\tInterfaceSel; /* board type kept in eFuse */\n\tu16\tCustomerID;\n\n\tu16\tEEPROMVID;\n\tu16\tEEPROMSVID;\n#ifdef CONFIG_USB_HCI\n\tu8\tEEPROMUsbSwitch;\n\tu16\tEEPROMPID;\n\tu16\tEEPROMSDID;\n#endif\n#ifdef CONFIG_PCI_HCI\n\tu16\tEEPROMDID;\n\tu16\tEEPROMSMID;\n#endif\n\n\tu8\tEEPROMCustomerID;\n\tu8\tEEPROMSubCustomerID;\n\tu8\tEEPROMVersion;\n\tu8\tEEPROMRegulatory;\n\tu8\teeprom_thermal_meter;\n\tu8\tEEPROMBluetoothCoexist;\n\tu8\tEEPROMBluetoothType;\n\tu8\tEEPROMBluetoothAntNum;\n\tu8\tEEPROMBluetoothAntIsolation;\n\tu8\tEEPROMBluetoothRadioShared;\n\tu8\tEEPROMMACAddr[ETH_ALEN];\n\tu8\ttx_bbswing_24G;\n\tu8\ttx_bbswing_5G;\n\tu8\tefuse0x3d7;\t/* efuse[0x3D7] */\n\tu8\tefuse0x3d8;\t/* efuse[0x3D8] */\n\n#ifdef CONFIG_RF_POWER_TRIM\n\tu8\tEEPROMRFGainOffset;\n\tu8\tEEPROMRFGainVal;\n\tstruct kfree_data_t kfree_data;\n#endif /*CONFIG_RF_POWER_TRIM*/\n\n#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \\\n\tdefined(CONFIG_RTL8723D) || \\\n\tdefined(CONFIG_RTL8192F)\n\n\tu8\tadjuseVoltageVal;\n\tu8\tneed_restore;\n#endif\n\tu8\tEfuseUsedPercentage;\n\tu16\tEfuseUsedBytes;\n\t/*u8\t\tEfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/\n\tEFUSE_HAL\tEfuseHal;\n\n\t/*---------------------------------------------------------------------------------*/\n\t/* 2.4G TX power info for target TX power*/\n\tu8\tIndex24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];\n\tu8\tIndex24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];\n\ts8\tCCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];\n\ts8\tOFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];\n\ts8\tBW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];\n\ts8\tBW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];\n\n\t/* 5G TX power info for target TX power*/\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\tu8\tIndex5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM];\n\tu8\tIndex5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM];\n\ts8\tOFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];\n\ts8\tBW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];\n\ts8\tBW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];\n\ts8\tBW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];\n#endif\n\n\tu8 txpwr_by_rate_undefined_band_path[TX_PWR_BY_RATE_NUM_BAND]\n\t\t[TX_PWR_BY_RATE_NUM_RF];\n\n\ts8\tTxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND]\n\t\t[TX_PWR_BY_RATE_NUM_RF]\n\t\t[TX_PWR_BY_RATE_NUM_RATE];\n\n\t/* Store the original power by rate value of the base rate for each rate section and rf path */\n\tu8\tTxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF]\n\t\t[MAX_BASE_NUM_IN_PHY_REG_PG_2_4G];\n\tu8\tTxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF]\n\t\t[MAX_BASE_NUM_IN_PHY_REG_PG_5G];\n\n#if defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)\n\tu32 txagc_set_buf;\n#endif\n\n\tu8\ttxpwr_by_rate_loaded:1;\n\tu8\ttxpwr_by_rate_from_file:1;\n\tu8\ttxpwr_limit_loaded:1;\n\tu8\ttxpwr_limit_from_file:1;\n\tu8\trf_power_tracking_type;\n\n\t/* Read/write are allow for following hardware information variables\t */\n\tu8\tcrystal_cap;\n\n\tu8\tPAType_2G;\n\tu8\tPAType_5G;\n\tu8\tLNAType_2G;\n\tu8\tLNAType_5G;\n\tu8\tExternalPA_2G;\n\tu8\tExternalLNA_2G;\n\tu8\texternal_pa_5g;\n\tu8\texternal_lna_5g;\n\tu16\tTypeGLNA;\n\tu16\tTypeGPA;\n\tu16\tTypeALNA;\n\tu16\tTypeAPA;\n\tu16\trfe_type;\n\n\tu8\tbLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */\n\tu32\tac_param_be; /* Original parameter for BE, use for EDCA turbo.\t*/\n\tu8\tis_turbo_edca;\n\tu8\tprv_traffic_idx;\n\tBB_REGISTER_DEFINITION_T\tPHYRegDef[MAX_RF_PATH];\t/* Radio A/B/C/D */\n\n\tu32\tRfRegChnlVal[MAX_RF_PATH];\n\n\t/* RDG enable */\n\tBOOLEAN\t bRDGEnable;\n\n\t#if defined (CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\n\tu32 RegRRSR;\n\t#endif\n\n\t/****** antenna diversity ******/\n\tu8\tAntDivCfg;\n\tu8\twith_extenal_ant_switch;\n\tu8\tb_fix_tx_ant;\n\tu8\tAntDetection;\n\tu8\tTRxAntDivType;\n\tu8\tant_path; /* for 8723B s0/s1 selection\t */\n\tu32\tantenna_tx_path;\t\t\t\t\t/* Antenna path Tx */\n\tu32\tAntennaRxPath;\t\t\t\t\t/* Antenna path Rx */\n\tu8 sw_antdiv_bl_state;\n\n\t/******** PHY DM & DM Section **********/\n\t_lock\t\tIQKSpinLock;\n\tu8\t\t\tINIDATA_RATE[MACID_NUM_SW_LIMIT];\n\n\tstruct dm_struct\t odmpriv;\n\tu64\t\t\tbk_rf_ability;\n\tu8\t\t\tbIQKInitialized;\n\tu8\t\t\tbNeedIQK;\n\tu8\t\t\tneediqk_24g;\n\tu8\t\t\tIQK_MP_Switch;\n\tu8\t\t\tbScanInProcess;\n\t/******** PHY DM & DM Section **********/\n\n\n\n\t/* 2010/08/09 MH Add CU power down mode. */\n\tBOOLEAN\t\tpwrdown;\n\n\t/* Add for dual MAC  0--Mac0 1--Mac1 */\n\tu32\tinterfaceIndex;\n\n#ifdef CONFIG_P2P\n#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP\n\tu16 p2p_ps_offload;\n#else\n\tu8\tp2p_ps_offload;\n#endif\n#endif\n\t/* Auto FSM to Turn On, include clock, isolation, power control for MAC only */\n\tu8\tbMacPwrCtrlOn;\n\tu8 hci_sus_state;\n\n\tu8\tRegIQKFWOffload;\n\tstruct submit_ctx\tiqk_sctx;\n\tu8 ch_switch_offload;\n\tstruct submit_ctx chsw_sctx;\n\n\tRT_AMPDU_BRUST\t\tAMPDUBurstMode; /* 92C maybe not use, but for compile successfully */\n\n\tu8\tOutEpQueueSel;\n\tu8\tOutEpNumber;\n\n#ifdef RTW_RX_AGGREGATION\n\tRX_AGG_MODE rxagg_mode;\n\n\t/* For RX Aggregation DMA Mode */\n\tu8 rxagg_dma_size;\n\tu8 rxagg_dma_timeout;\n#endif /* RTW_RX_AGGREGATION */\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t/*  */\n\t/* For SDIO Interface HAL related */\n\t/*  */\n\n\t/*  */\n\t/* SDIO ISR Related */\n\t/*\n\t*\tu32\t\t\tIntrMask[1];\n\t*\tu32\t\t\tIntrMaskToSet[1];\n\t*\tLOG_INTERRUPT\t\tInterruptLog; */\n\tu32\t\t\tsdio_himr;\n\tu32\t\t\tsdio_hisr;\n#ifndef RTW_HALMAC\n\t/*  */\n\t/* SDIO Tx FIFO related. */\n\t/*  */\n\t/* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */\n#ifdef CONFIG_RTL8192F\n\tu16\t\t\tSdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];\n#else\n\tu8\t\t\tSdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];\n#endif/*CONFIG_RTL8192F*/\n\t_lock\t\tSdioTxFIFOFreePageLock;\n\tu8\t\t\tSdioTxOQTMaxFreeSpace;\n\tu8\t\t\tSdioTxOQTFreeSpace;\n#else /* RTW_HALMAC */\n\tu16\t\t\tSdioTxOQTFreeSpace;\n#endif /* RTW_HALMAC */\n\n\t/*  */\n\t/* SDIO Rx FIFO related. */\n\t/*  */\n\tu8\t\t\tSdioRxFIFOCnt;\n#ifdef CONFIG_RTL8822C\n\tu32\t\t\tSdioRxFIFOSize;\n#else\n\tu16\t\t\tSdioRxFIFOSize;\n#endif\n\n#ifndef RTW_HALMAC\n\tu32\t\t\tsdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */\n#else\n#ifdef CONFIG_RTL8821C\n\tu16\t\t\ttx_high_page;\n\tu16\t\t\ttx_low_page;\n\tu16\t\t\ttx_normal_page;\n\tu16\t\t\ttx_extra_page;\n\tu16\t\t\ttx_pub_page;\n\tu8\t\t\tmax_oqt_size;\n\t#ifdef XMIT_BUF_SIZE\n\tu32\t\t\tmax_xmit_size_vovi;\n\tu32\t\t\tmax_xmit_size_bebk;\n\t#endif /*XMIT_BUF_SIZE*/\n\tu16\t\t\tmax_xmit_page;\n\tu16\t\t\tmax_xmit_page_vo;\n\tu16\t\t\tmax_xmit_page_vi;\n\tu16\t\t\tmax_xmit_page_be;\n\tu16\t\t\tmax_xmit_page_bk;\n\n#endif /*#ifdef CONFIG_RTL8821C*/\n#endif /* !RTW_HALMAC */\n\n#ifdef CONFIG_SDIO_MONITOR\n\tu8\t\t\tsdio_monitor_enable;\n\tu32\t\t\tsdio_monitor_sample_data[SDIO_MONITOR_MAX_SAMPLE_NUM];\n\tu32\t\t\tsdio_monitor_sample_num;\n#endif\n#endif /* CONFIG_SDIO_HCI */\n\n#ifdef CONFIG_USB_HCI\n\n\t/* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */\n\tBOOLEAN\t\tUsbRxHighSpeedMode;\n\tBOOLEAN\t\tUsbTxVeryHighSpeedMode;\n\tu32\t\t\tUsbBulkOutSize;\n\tBOOLEAN\t\tbSupportUSB3;\n\tu8\t\t\tusb_intf_start;\n\n\t/* Interrupt relatd register information. */\n\tu32\t\t\tIntArray[3];/* HISR0,HISR1,HSISR */\n\tu32\t\t\tIntrMask[3];\n#ifdef CONFIG_USB_TX_AGGREGATION\n\tu8\t\t\tUsbTxAggMode;\n\tu8\t\t\tUsbTxAggDescNum;\n#endif /* CONFIG_USB_TX_AGGREGATION */\n\n#ifdef CONFIG_USB_RX_AGGREGATION\n\tu16\t\t\tHwRxPageSize;\t\t\t\t/* Hardware setting */\n\n\t/* For RX Aggregation USB Mode */\n\tu8\t\t\trxagg_usb_size;\n\tu8\t\t\trxagg_usb_timeout;\n#endif/* CONFIG_USB_RX_AGGREGATION */\n#endif /* CONFIG_USB_HCI */\n\n\n#ifdef CONFIG_PCI_HCI\n\t/*  */\n\t/* EEPROM setting. */\n\t/*  */\n\tu32\t\t\tTransmitConfig;\n\tu32\t\t\tIntrMaskToSet[2];\n\tu32\t\t\tIntArray[4];\n\tu32\t\t\tIntrMask[4];\n\tu32\t\t\tSysIntArray[1];\n\tu32\t\t\tSysIntrMask[1];\n\tu32\t\t\tIntrMaskReg[2];\n\tu32\t\t\tIntrMaskDefault[4];\n\n\tBOOLEAN\t\tbL1OffSupport;\n\tBOOLEAN\tbSupportBackDoor;\n\tu32\t\t\tpci_backdoor_ctrl;\n\n\tu8\t\t\tbDefaultAntenna;\n\n\tu8\t\t\tbInterruptMigration;\n\tu8\t\t\tbDisableTxInt;\n\n\tu16\t\t\tRxTag;\n#ifdef CONFIG_PCI_DYNAMIC_ASPM\n\tBOOLEAN\t\tbAspmL1LastIdle;\n#endif\n#endif /* CONFIG_PCI_HCI */\n\n\n#ifdef DBG_CONFIG_ERROR_DETECT\n\tstruct sreset_priv srestpriv;\n#endif /* #ifdef DBG_CONFIG_ERROR_DETECT */\n\n#ifdef CONFIG_BT_COEXIST\n\t/* For bluetooth co-existance */\n\tBT_COEXIST\t\tbt_coexist;\n#endif /* CONFIG_BT_COEXIST */\n\n#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) \\\n\t|| defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D)|| defined(CONFIG_RTL8192F)\n#ifndef CONFIG_PCI_HCI\t/* mutual exclusive with PCI -- so they're SDIO and GSPI */\n\t/* Interrupt relatd register information. */\n\tu32\t\t\tSysIntrStatus;\n\tu32\t\t\tSysIntrMask;\n#endif\n#endif /*endif CONFIG_RTL8723B\t*/\n\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\tchar\tpara_file_buf[MAX_PARA_FILE_BUF_LEN];\n\tchar *mac_reg;\n\tu32\tmac_reg_len;\n\tchar *bb_phy_reg;\n\tu32\tbb_phy_reg_len;\n\tchar *bb_agc_tab;\n\tu32\tbb_agc_tab_len;\n\tchar *bb_phy_reg_pg;\n\tu32\tbb_phy_reg_pg_len;\n\tchar *bb_phy_reg_mp;\n\tu32\tbb_phy_reg_mp_len;\n\tchar *rf_radio_a;\n\tu32\trf_radio_a_len;\n\tchar *rf_radio_b;\n\tu32\trf_radio_b_len;\n\tchar *rf_tx_pwr_track;\n\tu32\trf_tx_pwr_track_len;\n\tchar *rf_tx_pwr_lmt;\n\tu32\trf_tx_pwr_lmt_len;\n#endif\n\n#ifdef CONFIG_BACKGROUND_NOISE_MONITOR\n\tstruct noise_monitor nm;\n#endif\n\n\tstruct hal_spec_t hal_spec;\n#ifdef CONFIG_PHY_CAPABILITY_QUERY\n\tstruct phy_spec_t phy_spec;\n#endif\n\tu8\tRfKFreeEnable;\n\tu8\tRfKFree_ch_group;\n\tBOOLEAN\t\t\t\tbCCKinCH14;\n\tBB_INIT_REGISTER\tRegForRecover[5];\n\n#if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN)\n\tBOOLEAN bCorrectBCN;\n#endif\n\tu32 RxGainOffset[4]; /*{2G, 5G_Low, 5G_Middle, G_High}*/\n\tu8 BackUp_IG_REG_4_Chnl_Section[4]; /*{A,B,C,D}*/\n\n\tstruct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM];\n\n#ifdef RTW_HALMAC\n\tu16 drv_rsvd_page_number;\n#endif\n\n#ifdef CONFIG_BEAMFORMING\n\tu8 backup_snd_ptcl_ctrl;\n#ifdef RTW_BEAMFORMING_VERSION_2\n\tstruct beamforming_info beamforming_info;\n#endif /* RTW_BEAMFORMING_VERSION_2 */\n#endif /* CONFIG_BEAMFORMING */\n\n\tu8 not_xmitframe_fw_dl; /*not use xmitframe to download fw*/\n\tu8 phydm_op_mode;\n\n\tu8 in_cta_test;\n\n#ifdef CONFIG_RTW_LED\n\tstruct led_priv led;\n#endif\n\t/* for multi channel case (ex: MCC/TDLS) */\n\tu8 multi_ch_switch_mode;\n\n} HAL_DATA_COMMON, *PHAL_DATA_COMMON;\n\ntypedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE;\n#define GET_HAL_DATA(__pAdapter)\t\t\t((HAL_DATA_TYPE *)(((struct _ADAPTER*)__pAdapter)->HalData))\n#define GET_HAL_SPEC(__pAdapter)\t\t\t(&(GET_HAL_DATA((__pAdapter))->hal_spec))\n#define adapter_to_led(adapter) (&(GET_HAL_DATA(adapter)->led))\n\n#define GET_HAL_RFPATH_NUM(__pAdapter)\t\t(((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath)\n#define RT_GetInterfaceSelection(_Adapter)\t\t(GET_HAL_DATA(_Adapter)->InterfaceSel)\n#define GET_RF_TYPE(__pAdapter)\t\t\t\t(GET_HAL_DATA(__pAdapter)->rf_type)\n#define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data))\n\n#define\tSUPPORT_HW_RADIO_DETECT(Adapter)\t(RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD || \\\n\t\tRT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo || \\\n\t\tRT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo)\n\n#define get_hal_mac_addr(adapter)\t\t\t\t(GET_HAL_DATA(adapter)->EEPROMMACAddr)\n#define is_boot_from_eeprom(adapter)\t\t\t(GET_HAL_DATA(adapter)->EepromOrEfuse)\n#define rtw_get_hw_init_completed(adapter)\t\t(GET_HAL_DATA(adapter)->hw_init_completed)\n#define rtw_set_hw_init_completed(adapter, cmp)\t(GET_HAL_DATA(adapter)->hw_init_completed = cmp)\n#define rtw_is_hw_init_completed(adapter)\t\t(GET_HAL_DATA(adapter)->hw_init_completed == _TRUE)\n#endif\n\n#ifdef RTW_HALMAC\nint rtw_halmac_deinit_adapter(struct dvobj_priv *);\n#endif /* RTW_HALMAC */\n\n#endif /* __HAL_DATA_H__ */\n"
  },
  {
    "path": "include/hal_gspi.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HAL_GSPI_H_\n#define __HAL_GSPI_H_\n\n#define ffaddr2deviceId(pdvobj, addr)\t(pdvobj->Queue2Pipe[addr])\n\nu8 rtw_hal_gspi_max_txoqt_free_space(_adapter *padapter);\nu8 rtw_hal_gspi_query_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);\nvoid rtw_hal_gspi_update_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);\nvoid rtw_hal_set_gspi_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ);\nu32 rtw_hal_get_gspi_tx_max_length(PADAPTER padapter, u8 queue_idx);\n\n#endif\n"
  },
  {
    "path": "include/hal_ic_cfg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HAL_IC_CFG_H__\n#define __HAL_IC_CFG_H__\n\n#define RTL8188E_SUPPORT\t\t\t\t0\n#define RTL8812A_SUPPORT\t\t\t\t0\n#define RTL8821A_SUPPORT\t\t\t\t0\n#define RTL8723B_SUPPORT\t\t\t\t0\n#define RTL8723D_SUPPORT\t\t\t\t0\n#define RTL8192E_SUPPORT\t\t\t\t0\n#define RTL8192F_SUPPORT\t\t\t\t0\n#define RTL8814A_SUPPORT\t\t\t\t0\n#define RTL8195A_SUPPORT\t\t\t\t0\n#define RTL8197F_SUPPORT\t\t\t\t0\n#define RTL8703B_SUPPORT\t\t\t\t0\n#define RTL8188F_SUPPORT\t\t\t\t0\n#define RTL8822B_SUPPORT\t\t\t\t0\n#define RTL8821B_SUPPORT\t\t\t\t0\n#define RTL8821C_SUPPORT\t\t\t\t0\n#define RTL8710B_SUPPORT\t\t\t\t0\n#define RTL8814B_SUPPORT\t\t\t\t0\n#define RTL8824B_SUPPORT\t\t\t\t0\n#define RTL8198F_SUPPORT\t\t\t\t0\n#define RTL8195B_SUPPORT\t\t\t\t0\n#define RTL8822C_SUPPORT\t\t\t\t0\n#define RTL8721D_SUPPORT\t\t\t\t0\n#define RTL8812F_SUPPORT\t\t\t\t0\n#define RTL8197G_SUPPORT\t\t\t\t0\n#define RTL8721D_SUPPORT\t\t\t\t0\n\n/*#if (RTL8188E_SUPPORT==1)*/\n#define RATE_ADAPTIVE_SUPPORT\t\t\t0\n#define POWER_TRAINING_ACTIVE\t\t\t0\n\n#ifdef CONFIG_MULTIDRV\n#endif\n\n/*feature for all IC*/\n#define RTW_DYNAMIC_RRSR\n\n#ifdef CONFIG_RTL8188E\n\t#undef RTL8188E_SUPPORT\n\t#undef RATE_ADAPTIVE_SUPPORT\n\t#undef POWER_TRAINING_ACTIVE\n\n\t#define RTL8188E_SUPPORT\t\t\t\t1\n\t#define RATE_ADAPTIVE_SUPPORT\t\t\t1\n\t#define POWER_TRAINING_ACTIVE\t\t\t1\n#endif\n\n#ifdef CONFIG_RTL8812A\n\t#undef RTL8812A_SUPPORT\n\t#define RTL8812A_SUPPORT\t\t\t\t1\n\t#ifndef CONFIG_FW_C2H_PKT\n\t\t#define CONFIG_FW_C2H_PKT\n\t#endif\n\t#ifdef CONFIG_BEAMFORMING\n\t\t#define CONFIG_BEAMFORMER_FW_NDPA\n\t\t#define BEAMFORMING_SUPPORT\t\t1\t/*for phydm beamforming*/\n\t\t#define SUPPORT_MU_BF\t\t\t\t0\n\t#endif /*CONFIG_BEAMFORMING*/\n\t#define CONFIG_RTS_FULL_BW\n#endif\n\n#ifdef CONFIG_RTL8821A\n\t#undef RTL8821A_SUPPORT\n\t#define RTL8821A_SUPPORT\t\t\t\t1\n\t#ifndef CONFIG_FW_C2H_PKT\n\t\t#define CONFIG_FW_C2H_PKT\n\t#endif\n\t#ifdef CONFIG_BEAMFORMING\n\t\t#define CONFIG_BEAMFORMER_FW_NDPA\n\t\t#define BEAMFORMING_SUPPORT\t\t1\t/*for phydm beamforming*/\n\t\t#define SUPPORT_MU_BF\t\t\t\t0\n\t#endif\n\t#define CONFIG_RTS_FULL_BW\n#endif\n\n#ifdef CONFIG_RTL8192E\n\t#undef RTL8192E_SUPPORT\n\t#define RTL8192E_SUPPORT\t\t\t\t1\n\t#ifndef CONFIG_FW_C2H_PKT\n\t\t#define CONFIG_FW_C2H_PKT\n\t#endif\n\t#define CONFIG_RTS_FULL_BW\n#endif\n\n#ifdef CONFIG_RTL8192F\n\t#undef RTL8192F_SUPPORT\n\t#define RTL8192F_SUPPORT\t\t\t\t1\n\t#ifndef CONFIG_FW_C2H_PKT\n\t\t#define CONFIG_FW_C2H_PKT\n\t#endif\n\t#ifndef CONFIG_RTW_MAC_HIDDEN_RPT\n\t\t#define CONFIG_RTW_MAC_HIDDEN_RPT\n\t#endif\n\t/*#define CONFIG_AMPDU_PRETX_CD*/\n\t/*#define DBG_LA_MODE*/\n\t#ifdef CONFIG_P2P_PS\n\t\t#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP\n\t#endif\n\t#define CONFIG_RTS_FULL_BW\n#endif\n\n#ifdef CONFIG_RTL8723B\n\t#undef RTL8723B_SUPPORT\n\t#define RTL8723B_SUPPORT\t\t\t\t1\n\t#ifndef CONFIG_FW_C2H_PKT\n\t\t#define CONFIG_FW_C2H_PKT\n\t#endif\n\t#define CONFIG_RTS_FULL_BW\n#endif\n\n#ifdef CONFIG_RTL8723D\n\t#undef RTL8723D_SUPPORT\n\t#define RTL8723D_SUPPORT\t\t\t\t1\n\t#ifndef CONFIG_FW_C2H_PKT\n\t\t#define CONFIG_FW_C2H_PKT\n\t#endif\n\t#ifndef CONFIG_RTW_MAC_HIDDEN_RPT\n\t\t#define CONFIG_RTW_MAC_HIDDEN_RPT\n\t#endif\n\t#ifndef CONFIG_RTW_CUSTOMER_STR\n\t\t#define CONFIG_RTW_CUSTOMER_STR\n\t#endif\n\t#define CONFIG_RTS_FULL_BW\n#endif\n\n#ifdef CONFIG_RTL8814A\n\t#undef RTL8814A_SUPPORT\n\t#define RTL8814A_SUPPORT\t\t\t\t1\n\t#ifndef CONFIG_FW_C2H_PKT\n\t\t#define CONFIG_FW_C2H_PKT\n\t#endif\n\t#define CONFIG_FW_CORRECT_BCN\n\t#ifdef CONFIG_BEAMFORMING\n\t\t#define BEAMFORMING_SUPPORT\t\t1\t/*for phydm beamforming*/\n\t\t#define SUPPORT_MU_BF\t\t\t\t0\n\t#endif\n\t#define CONFIG_RTS_FULL_BW\n#endif\n\n#ifdef CONFIG_RTL8703B\n\t#undef RTL8703B_SUPPORT\n\t#define RTL8703B_SUPPORT\t\t\t\t1\n\t#ifndef CONFIG_FW_C2H_PKT\n\t\t#define CONFIG_FW_C2H_PKT\n\t#endif\n\t#ifndef CONFIG_RTW_MAC_HIDDEN_RPT\n\t\t#define CONFIG_RTW_MAC_HIDDEN_RPT\n\t#endif\n\t#define CONFIG_RTS_FULL_BW\n#endif\n\n#ifdef CONFIG_RTL8188F\n\t#undef RTL8188F_SUPPORT\n\t#define RTL8188F_SUPPORT\t\t\t\t1\n\t#ifndef CONFIG_FW_C2H_PKT\n\t\t#define CONFIG_FW_C2H_PKT\n\t#endif\n\t#ifndef CONFIG_RTW_MAC_HIDDEN_RPT\n\t\t#define CONFIG_RTW_MAC_HIDDEN_RPT\n\t#endif\n\t#ifndef CONFIG_RTW_CUSTOMER_STR\n\t\t#define CONFIG_RTW_CUSTOMER_STR\n\t#endif\n\t#define CONFIG_RTS_FULL_BW\n#endif\n\n#ifdef CONFIG_RTL8188GTV\n\t#undef RTL8188F_SUPPORT\n\t#define RTL8188F_SUPPORT\t\t\t\t1\n\t#ifndef CONFIG_FW_C2H_PKT\n\t\t#define CONFIG_FW_C2H_PKT\n\t#endif\n\t#ifndef CONFIG_RTW_MAC_HIDDEN_RPT\n\t\t#define CONFIG_RTW_MAC_HIDDEN_RPT\n\t#endif\n\t#ifndef CONFIG_RTW_CUSTOMER_STR\n\t\t#define CONFIG_RTW_CUSTOMER_STR\n\t#endif\n\t#define CONFIG_RTS_FULL_BW\n#endif\n\n#ifdef CONFIG_RTL8822B\n\t#undef RTL8822B_SUPPORT\n\t#define RTL8822B_SUPPORT\t\t\t\t1\n\t#ifndef CONFIG_FW_C2H_PKT\n\t\t#define CONFIG_FW_C2H_PKT\n\t#endif /* CONFIG_FW_C2H_PKT */\n\t#define RTW_TX_PA_BIAS\t/* Adjust TX PA Bias from eFuse */\n\t#define CONFIG_DFS\t/* Enable 5G band 2&3 channel */\n\t#define RTW_AMPDU_AGG_RETRY_AND_NEW\n\n\t#ifdef CONFIG_WOWLAN\n\t\t#define CONFIG_GTK_OL\n\t\t/*#define CONFIG_ARP_KEEP_ALIVE*/\n\n\t\t#ifdef CONFIG_GPIO_WAKEUP\n\t\t\t#ifndef WAKEUP_GPIO_IDX\n\t\t\t\t#define WAKEUP_GPIO_IDX\t6\t/* WIFI Chip Side */\n\t\t\t#endif /* !WAKEUP_GPIO_IDX */\n\t\t#endif /* CONFIG_GPIO_WAKEUP */\n\t#endif /* CONFIG_WOWLAN */\n\n\t#ifdef CONFIG_CONCURRENT_MODE\n\t\t#define CONFIG_AP_PORT_SWAP\n\t\t#define CONFIG_FW_MULTI_PORT_SUPPORT\n\t#endif /* CONFIG_CONCURRENT_MODE */\n\n\t/*\n\t * Beamforming related definition\n\t */\n\t/* Only support new beamforming mechanism */\n\t#ifdef CONFIG_BEAMFORMING\n\t\t#define RTW_BEAMFORMING_VERSION_2\n\t#endif /* CONFIG_BEAMFORMING */\n\n\t#ifndef CONFIG_RTW_MAC_HIDDEN_RPT\n\t\t#define CONFIG_RTW_MAC_HIDDEN_RPT\n\t#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */\n\n\t#ifndef DBG_RX_DFRAME_RAW_DATA\n\t\t#define DBG_RX_DFRAME_RAW_DATA\n\t#endif /* DBG_RX_DFRAME_RAW_DATA */\n\n\t#ifndef RTW_IQK_FW_OFFLOAD\n\t\t#define RTW_IQK_FW_OFFLOAD\n\t#endif /* RTW_IQK_FW_OFFLOAD */\n\n\t/* Checksum offload feature */\n\t/*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/ /* not ready */\n\t#define CONFIG_TCP_CSUM_OFFLOAD_RX\n\n\t#define CONFIG_ADVANCE_OTA\n\n\t#ifdef CONFIG_MCC_MODE\n\t\t#define CONFIG_MCC_MODE_V2\n\t\t#define CONFIG_MCC_PHYDM_OFFLOAD\n\t#endif /* CONFIG_MCC_MODE */\n\n\t#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)\n\t\t#define CONFIG_TDLS_CH_SW_V2\n\t#endif\n\n\t#ifndef RTW_CHANNEL_SWITCH_OFFLOAD\n\t\t#ifdef CONFIG_TDLS_CH_SW_V2\n\t\t\t#define RTW_CHANNEL_SWITCH_OFFLOAD\n\t\t#endif\n\t#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */\n\n\t#if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW)\n\t\t/* Supported since fw v22.1 */\n\t\t#define RTW_PER_CMD_SUPPORT_FW\n\t#endif /* RTW_PER_CMD_SUPPORT_FW */\n\t#define CONFIG_SUPPORT_FIFO_DUMP\n\t#define CONFIG_HW_P0_TSF_SYNC\n\t#define CONFIG_BCN_RECV_TIME\n\t#ifdef CONFIG_P2P_PS\n\t\t#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP\n\t#endif\n\t#define CONFIG_RTS_FULL_BW\n#endif /* CONFIG_RTL8822B */\n\n#ifdef CONFIG_RTL8822C\n\t#undef RTL8822C_SUPPORT\n\t#define RTL8822C_SUPPORT\t\t\t\t1\n\t#define DBG_LA_MODE\n\t#ifndef CONFIG_FW_C2H_PKT\n\t\t#define CONFIG_FW_C2H_PKT\n\t#endif /* CONFIG_FW_C2H_PKT */\n\t#define RTW_TX_PA_BIAS\t/* Adjust TX PA Bias from eFuse */\n\t#define CONFIG_DFS\t/* Enable 5G band 2&3 channel */\n\n\t#ifdef CONFIG_WOWLAN\n\t\t#define CONFIG_GTK_OL\n\t\t/*#define CONFIG_ARP_KEEP_ALIVE*/\n\n\t\t#ifdef CONFIG_GPIO_WAKEUP\n\t\t\t#ifndef WAKEUP_GPIO_IDX\n\t\t\t\t#define WAKEUP_GPIO_IDX\t6\t/* WIFI Chip Side */\n\t\t\t#endif /* !WAKEUP_GPIO_IDX */\n\t\t#endif /* CONFIG_GPIO_WAKEUP */\n\t#endif /* CONFIG_WOWLAN */\n\n\t#ifdef CONFIG_CONCURRENT_MODE\n\t\t#define CONFIG_AP_PORT_SWAP\n\t\t#define CONFIG_FW_MULTI_PORT_SUPPORT\n\t#endif /* CONFIG_CONCURRENT_MODE */\n\n\t/*\n\t * Beamforming related definition\n\t */\n\t/* Only support new beamforming mechanism */\n\t#ifdef CONFIG_BEAMFORMING\n\t\t#define RTW_BEAMFORMING_VERSION_2\n\t#endif /* CONFIG_BEAMFORMING */\n\n\t#ifndef CONFIG_RTW_MAC_HIDDEN_RPT\n\t\t#define CONFIG_RTW_MAC_HIDDEN_RPT\n\t#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */\n\n\t#ifndef DBG_RX_DFRAME_RAW_DATA\n\t\t#define DBG_RX_DFRAME_RAW_DATA\n\t#endif /* DBG_RX_DFRAME_RAW_DATA */\n\n\t#ifndef RTW_IQK_FW_OFFLOAD\n\t\t/* #define RTW_IQK_FW_OFFLOAD */\n\t#endif /* RTW_IQK_FW_OFFLOAD */\n\n\t/* Checksum offload feature */\n\t/* #define CONFIG_TX_CSUM_OFFLOAD */\n\t#if defined(CONFIG_TX_CSUM_OFFLOAD) && !defined(CONFIG_RTW_NETIF_SG)\n\t\t#define CONFIG_RTW_NETIF_SG\n\t#endif\n\t#define CONFIG_TCP_CSUM_OFFLOAD_RX\n\n\t#define CONFIG_ADVANCE_OTA\n\n\t#ifdef CONFIG_MCC_MODE\n\t\t#define CONFIG_MCC_MODE_V2\n\t#endif /* CONFIG_MCC_MODE */\n\n\t#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)\n\t\t#define CONFIG_TDLS_CH_SW_V2\n\t#endif\n\n\t#ifndef RTW_CHANNEL_SWITCH_OFFLOAD\n\t\t#ifdef CONFIG_TDLS_CH_SW_V2\n\t\t\t#define RTW_CHANNEL_SWITCH_OFFLOAD\n\t\t#endif\n\t#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */\n\n\t#if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW)\n\t\t/* Supported since fw v22.1 */\n\t\t#define RTW_PER_CMD_SUPPORT_FW\n\t#endif /* RTW_PER_CMD_SUPPORT_FW */\n\t#define CONFIG_SUPPORT_FIFO_DUMP\n\t#define CONFIG_HW_P0_TSF_SYNC\n\t#define CONFIG_BCN_RECV_TIME\n\n\t#ifdef CONFIG_P2P_PS\n\t\t#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP\n\t#endif\n\t#define CONFIG_RTS_FULL_BW\n\t#ifdef CONFIG_LPS\n\t\t/* #define CONFIG_LPS_1T1R */ /* Supported after FW v07 */\n\t#endif\n\n\t#define CONFIG_RTL8822C_XCAP_NEW_POLICY\n#endif /* CONFIG_RTL8822C */\n\n#ifdef CONFIG_RTL8821C\n\t#undef RTL8821C_SUPPORT\n\t#define RTL8821C_SUPPORT\t\t\t\t1\n\t#ifndef CONFIG_FW_C2H_PKT\n\t\t#define CONFIG_FW_C2H_PKT\n\t#endif\n\t#ifdef CONFIG_NO_FW\n\t\t#ifdef CONFIG_RTW_MAC_HIDDEN_RPT\n\t\t\t#undef CONFIG_RTW_MAC_HIDDEN_RPT\n\t\t#endif\n\t#else\n\t\t#ifndef CONFIG_RTW_MAC_HIDDEN_RPT\n\t\t\t#define CONFIG_RTW_MAC_HIDDEN_RPT\n\t\t#endif\n\t#endif\n\t#define LOAD_FW_HEADER_FROM_DRIVER\n\t#define CONFIG_PHY_CAPABILITY_QUERY\n\t#ifdef CONFIG_CONCURRENT_MODE\n\t#define CONFIG_AP_PORT_SWAP\n\t#define CONFIG_FW_MULTI_PORT_SUPPORT\n\t#endif\n\t#define CONFIG_SUPPORT_FIFO_DUMP\n\t#ifndef RTW_IQK_FW_OFFLOAD\n\t\t#define RTW_IQK_FW_OFFLOAD\n\t#endif /* RTW_IQK_FW_OFFLOAD */\n\t/*#define CONFIG_AMPDU_PRETX_CD*/\n\t/*#define DBG_PRE_TX_HANG*/\n\n\t/* Beamforming related definition */\n\t/* Only support new beamforming mechanism */\n\t#ifdef CONFIG_BEAMFORMING\n\t\t#define RTW_BEAMFORMING_VERSION_2\n\t#endif /* CONFIG_BEAMFORMING */\n\t#define CONFIG_HW_P0_TSF_SYNC\n\t#define CONFIG_BCN_RECV_TIME\n\t#ifdef CONFIG_P2P_PS\n\t\t#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP\n\t#endif\n\t#define CONFIG_RTS_FULL_BW\n#endif /*CONFIG_RTL8821C*/\n\n#ifdef CONFIG_RTL8710B\n\t#undef RTL8710B_SUPPORT\n\t#define RTL8710B_SUPPORT\t\t\t\t1\n\t#ifndef CONFIG_FW_C2H_PKT\n\t\t#define CONFIG_FW_C2H_PKT\n\t#endif\n\t#define CONFIG_RTS_FULL_BW\n#endif\n\n#endif /*__HAL_IC_CFG_H__*/\n"
  },
  {
    "path": "include/hal_intf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HAL_INTF_H__\n#define __HAL_INTF_H__\n\n\nenum RTL871X_HCI_TYPE {\n\tRTW_PCIE\t= BIT0,\n\tRTW_USB\t= BIT1,\n\tRTW_SDIO\t= BIT2,\n\tRTW_GSPI\t= BIT3,\n};\n\nenum _CHIP_TYPE {\n\n\tNULL_CHIP_TYPE,\n\tRTL8188E,\n\tRTL8192E,\n\tRTL8812,\n\tRTL8821, /* RTL8811 */\n\tRTL8723B,\n\tRTL8814A,\n\tRTL8703B,\n\tRTL8188F,\n\tRTL8188GTV,\n\tRTL8822B,\n\tRTL8723D,\n\tRTL8821C,\n\tRTL8710B,\n\tRTL8192F,\n\tRTL8822C,\n\tMAX_CHIP_TYPE\n};\n\n#ifdef RTW_HALMAC\nenum fw_mem {\n\tFW_EMEM,\n\tFW_IMEM,\n\tFW_DMEM,\n};\n#endif\n\nextern const u32 _chip_type_to_odm_ic_type[];\n#define chip_type_to_odm_ic_type(chip_type) (((chip_type) >= MAX_CHIP_TYPE) ? _chip_type_to_odm_ic_type[MAX_CHIP_TYPE] : _chip_type_to_odm_ic_type[(chip_type)])\n\ntypedef enum _HAL_HW_TIMER_TYPE {\n\tHAL_TIMER_NONE = 0,\n\tHAL_TIMER_TXBF = 1,\n\tHAL_TIMER_EARLYMODE = 2,\n} HAL_HW_TIMER_TYPE, *PHAL_HW_TIMER_TYPE;\n\n\ntypedef enum _HW_VARIABLES {\n\tHW_VAR_MEDIA_STATUS,\n\tHW_VAR_SET_OPMODE,\n\tHW_VAR_MAC_ADDR,\n\tHW_VAR_BSSID,\n\tHW_VAR_INIT_RTS_RATE,\n\tHW_VAR_BASIC_RATE,\n\tHW_VAR_TXPAUSE,\n\tHW_VAR_BCN_FUNC,\n\tHW_VAR_BCN_CTRL_ADDR,\n\tHW_VAR_CORRECT_TSF,\n\tHW_VAR_RCR,\n\tHW_VAR_MLME_DISCONNECT,\n\tHW_VAR_MLME_SITESURVEY,\n\tHW_VAR_MLME_JOIN,\n\tHW_VAR_ON_RCR_AM,\n\tHW_VAR_OFF_RCR_AM,\n\tHW_VAR_BEACON_INTERVAL,\n\tHW_VAR_SLOT_TIME,\n\tHW_VAR_RESP_SIFS,\n\tHW_VAR_ACK_PREAMBLE,\n\tHW_VAR_SEC_CFG,\n\tHW_VAR_SEC_DK_CFG,\n\tHW_VAR_BCN_VALID,\n\tHW_VAR_RF_TYPE,\n\tHW_VAR_FREECNT,\n\n\t/* PHYDM odm->SupportAbility */\n\tHW_VAR_CAM_EMPTY_ENTRY,\n\tHW_VAR_CAM_INVALID_ALL,\n\tHW_VAR_AC_PARAM_VO,\n\tHW_VAR_AC_PARAM_VI,\n\tHW_VAR_AC_PARAM_BE,\n\tHW_VAR_AC_PARAM_BK,\n\tHW_VAR_ACM_CTRL,\n#ifdef CONFIG_WMMPS_STA\n\tHW_VAR_UAPSD_TID,\n#endif /* CONFIG_WMMPS_STA */\n\tHW_VAR_AMPDU_MIN_SPACE,\n#ifdef CONFIG_80211N_HT\n\tHW_VAR_AMPDU_FACTOR,\n#endif /* CONFIG_80211N_HT */\n\tHW_VAR_RXDMA_AGG_PG_TH,\n\tHW_VAR_SET_RPWM,\n\tHW_VAR_CPWM,\n\tHW_VAR_H2C_FW_PWRMODE,\n\tHW_VAR_H2C_INACTIVE_IPS,\n\tHW_VAR_H2C_PS_TUNE_PARAM,\n\tHW_VAR_H2C_FW_JOINBSSRPT,\n\tHW_VAR_FWLPS_RF_ON,\n\tHW_VAR_H2C_FW_P2P_PS_OFFLOAD,\n#ifdef CONFIG_LPS_POFF\n\tHW_VAR_LPS_POFF_INIT,\n\tHW_VAR_LPS_POFF_DEINIT,\n\tHW_VAR_LPS_POFF_SET_MODE,\n\tHW_VAR_LPS_POFF_WOW_EN,\n#endif\n#ifdef CONFIG_LPS_PG\n\tHW_VAR_LPS_PG_HANDLE,\n#endif\n\tHW_VAR_TRIGGER_GPIO_0,\n\tHW_VAR_BT_SET_COEXIST,\n\tHW_VAR_BT_ISSUE_DELBA,\n\tHW_VAR_SWITCH_EPHY_WoWLAN,\n\tHW_VAR_EFUSE_USAGE,\n\tHW_VAR_EFUSE_BYTES,\n\tHW_VAR_EFUSE_BT_USAGE,\n\tHW_VAR_EFUSE_BT_BYTES,\n\tHW_VAR_FIFO_CLEARN_UP,\n\tHW_VAR_RESTORE_HW_SEQ,\n\tHW_VAR_CHECK_TXBUF,\n\tHW_VAR_PCIE_STOP_TX_DMA,\n\tHW_VAR_APFM_ON_MAC, /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */\n\tHW_VAR_HCI_SUS_STATE,\n\t/* The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. */\n\t/* Unit in microsecond. 0 means disable this function. */\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\n\tHW_VAR_WOWLAN,\n\tHW_VAR_WAKEUP_REASON,\n#endif\n\tHW_VAR_RPWM_TOG,\n#ifdef CONFIG_GPIO_WAKEUP\n\tHW_VAR_WOW_OUTPUT_GPIO,\n\tHW_VAR_WOW_INPUT_GPIO,\n\tHW_SET_GPIO_WL_CTRL,\n#endif\n\tHW_VAR_SYS_CLKR,\n\tHW_VAR_NAV_UPPER,\n\tHW_VAR_RPT_TIMER_SETTING,\n\tHW_VAR_TX_RPT_MAX_MACID,\n\tHW_VAR_CHK_HI_QUEUE_EMPTY,\n\tHW_VAR_CHK_MGQ_CPU_EMPTY,\n\tHW_VAR_DL_BCN_SEL,\n\tHW_VAR_AMPDU_MAX_TIME,\n\tHW_VAR_WIRELESS_MODE,\n\tHW_VAR_USB_MODE,\n\tHW_VAR_PORT_SWITCH,\n\tHW_VAR_PORT_CFG,\n\tHW_VAR_DO_IQK,\n\tHW_VAR_DM_IN_LPS_LCLK,/*flag CONFIG_LPS_LCLK_WD_TIMER*/\n\tHW_VAR_SET_REQ_FW_PS,\n\tHW_VAR_FW_PS_STATE,\n\tHW_VAR_SOUNDING_ENTER,\n\tHW_VAR_SOUNDING_LEAVE,\n\tHW_VAR_SOUNDING_RATE,\n\tHW_VAR_SOUNDING_STATUS,\n\tHW_VAR_SOUNDING_FW_NDPA,\n\tHW_VAR_SOUNDING_CLK,\n\tHW_VAR_SOUNDING_SET_GID_TABLE,\n\tHW_VAR_SOUNDING_CSI_REPORT,\n\t/*Add by YuChen for TXBF HW timer*/\n\tHW_VAR_HW_REG_TIMER_INIT,\n\tHW_VAR_HW_REG_TIMER_RESTART,\n\tHW_VAR_HW_REG_TIMER_START,\n\tHW_VAR_HW_REG_TIMER_STOP,\n\t/*Add by YuChen for TXBF HW timer*/\n\tHW_VAR_DL_RSVD_PAGE,\n\tHW_VAR_MACID_LINK,\n\tHW_VAR_MACID_NOLINK,\n\tHW_VAR_DUMP_MAC_QUEUE_INFO,\n\tHW_VAR_ASIX_IOT,\n#ifdef CONFIG_MBSSID_CAM\n\tHW_VAR_MBSSID_CAM_WRITE,\n\tHW_VAR_MBSSID_CAM_CLEAR,\n\tHW_VAR_RCR_MBSSID_EN,\n#endif\n\tHW_VAR_EN_HW_UPDATE_TSF,\n\tHW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO,\n\tHW_VAR_CH_SW_IQK_INFO_BACKUP,\n\tHW_VAR_CH_SW_IQK_INFO_RESTORE,\n\n\tHW_VAR_DBI,\n\tHW_VAR_MDIO,\n\tHW_VAR_L1OFF_CAPABILITY,\n\tHW_VAR_L1OFF_NIC_SUPPORT,\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\n\tHW_VAR_TDLS_BCN_EARLY_C2H_RPT,\n#endif\n#endif\n\tHW_VAR_DUMP_MAC_TXFIFO,\n\tHW_VAR_PWR_CMD,\n#ifdef CONFIG_FW_HANDLE_TXBCN\n\tHW_VAR_BCN_HEAD_SEL,\n#endif\n\tHW_VAR_SET_SOML_PARAM,\n\tHW_VAR_ENABLE_RX_BAR,\n\tHW_VAR_TSF_AUTO_SYNC,\n\tHW_VAR_LPS_STATE_CHK,\n\t#ifdef CONFIG_RTS_FULL_BW\n\tHW_VAR_SET_RTS_BW,\n\t#endif\n#if defined(CONFIG_PCI_HCI)\n\tHW_VAR_ENSWBCN,\n#endif\n} HW_VARIABLES;\n\ntypedef enum _HAL_DEF_VARIABLE {\n\tHAL_DEF_UNDERCORATEDSMOOTHEDPWDB,\n\tHAL_DEF_IS_SUPPORT_ANT_DIV,\n\tHAL_DEF_DRVINFO_SZ,\n\tHAL_DEF_MAX_RECVBUF_SZ,\n\tHAL_DEF_RX_PACKET_OFFSET,\n\tHAL_DEF_RX_DMA_SZ_WOW,\n\tHAL_DEF_RX_DMA_SZ,\n\tHAL_DEF_RX_PAGE_SIZE,\n\tHAL_DEF_DBG_DUMP_RXPKT,/* for dbg */\n\tHAL_DEF_RA_DECISION_RATE,\n\tHAL_DEF_RA_SGI,\n\tHAL_DEF_PT_PWR_STATUS,\n\tHAL_DEF_TX_LDPC,\t\t\t\t/* LDPC support */\n\tHAL_DEF_RX_LDPC,\t\t\t\t/* LDPC support */\n\tHAL_DEF_TX_STBC,\t\t\t\t/* TX STBC support */\n\tHAL_DEF_RX_STBC,\t\t\t\t/* RX STBC support */\n\tHAL_DEF_EXPLICIT_BEAMFORMER,/* Explicit  Compressed Steering Capable */\n\tHAL_DEF_EXPLICIT_BEAMFORMEE,/* Explicit Compressed Beamforming Feedback Capable */\n\tHAL_DEF_VHT_MU_BEAMFORMER,\t/* VHT MU Beamformer support */\n\tHAL_DEF_VHT_MU_BEAMFORMEE,\t/* VHT MU Beamformee support */\n\tHAL_DEF_BEAMFORMER_CAP,\n\tHAL_DEF_BEAMFORMEE_CAP,\n\tHW_VAR_MAX_RX_AMPDU_FACTOR,\n\tHW_DEF_RA_INFO_DUMP,\n\tHAL_DEF_DBG_DUMP_TXPKT,\n\n\tHAL_DEF_TX_PAGE_SIZE,\n\tHAL_DEF_TX_PAGE_BOUNDARY,\n\tHAL_DEF_TX_PAGE_BOUNDARY_WOWLAN,\n\tHAL_DEF_ANT_DETECT,/* to do for 8723a */\n\tHAL_DEF_PCI_SUUPORT_L1_BACKDOOR, /* Determine if the L1 Backdoor setting is turned on. */\n\tHAL_DEF_PCI_AMD_L1_SUPPORT,\n\tHAL_DEF_PCI_ASPM_OSC, /* Support for ASPM OSC, added by Roger, 2013.03.27. */\n\tHAL_DEF_EFUSE_USAGE,\t/* Get current EFUSE utilization. 2008.12.19. Added by Roger. */\n\tHAL_DEF_EFUSE_BYTES,\n\tHW_VAR_BEST_AMPDU_DENSITY,\n} HAL_DEF_VARIABLE;\n\ntypedef enum _HAL_ODM_VARIABLE {\n\tHAL_ODM_STA_INFO,\n\tHAL_ODM_P2P_STATE,\n\tHAL_ODM_WIFI_DISPLAY_STATE,\n\tHAL_ODM_REGULATION,\n\tHAL_ODM_INITIAL_GAIN,\n\tHAL_ODM_RX_INFO_DUMP,\n\tHAL_ODM_RX_Dframe_INFO,\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\tHAL_ODM_ANTDIV_SELECT\n#endif\n} HAL_ODM_VARIABLE;\n\ntypedef enum _HAL_INTF_PS_FUNC {\n\tHAL_USB_SELECT_SUSPEND,\n\tHAL_MAX_ID,\n} HAL_INTF_PS_FUNC;\n\ntypedef s32(*c2h_id_filter)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);\n\nstruct txpwr_idx_comp;\n\nstruct hal_ops {\n\t/*** initialize section ***/\n\tvoid\t(*read_chip_version)(_adapter *padapter);\n\tvoid\t(*init_default_value)(_adapter *padapter);\n\tvoid\t(*intf_chip_configure)(_adapter *padapter);\n\tu8\t(*read_adapter_info)(_adapter *padapter);\n\tu32(*hal_power_on)(_adapter *padapter);\n\tvoid\t(*hal_power_off)(_adapter *padapter);\n\tu32(*hal_init)(_adapter *padapter);\n\tu32(*hal_deinit)(_adapter *padapter);\n\tvoid\t(*dm_init)(_adapter *padapter);\n\tvoid\t(*dm_deinit)(_adapter *padapter);\n\n\t/*** xmit section ***/\n\ts32(*init_xmit_priv)(_adapter *padapter);\n\tvoid\t(*free_xmit_priv)(_adapter *padapter);\n\ts32(*hal_xmit)(_adapter *padapter, struct xmit_frame *pxmitframe);\n\t/*\n\t * mgnt_xmit should be implemented to run in interrupt context\n\t */\n\ts32(*mgnt_xmit)(_adapter *padapter, struct xmit_frame *pmgntframe);\n\ts32(*hal_xmitframe_enqueue)(_adapter *padapter, struct xmit_frame *pxmitframe);\n#ifdef CONFIG_XMIT_THREAD_MODE\n\ts32(*xmit_thread_handler)(_adapter *padapter);\n#endif\n\tvoid\t(*run_thread)(_adapter *padapter);\n\tvoid\t(*cancel_thread)(_adapter *padapter);\n\n\t/*** recv section ***/\n\ts32(*init_recv_priv)(_adapter *padapter);\n\tvoid\t(*free_recv_priv)(_adapter *padapter);\n#ifdef CONFIG_RECV_THREAD_MODE\n\ts32 (*recv_hdl)(_adapter *adapter);\n#endif\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)\n\tu32(*inirp_init)(_adapter *padapter);\n\tu32(*inirp_deinit)(_adapter *padapter);\n#endif\n\t/*** interrupt hdl section ***/\n\tvoid\t(*enable_interrupt)(_adapter *padapter);\n\tvoid\t(*disable_interrupt)(_adapter *padapter);\n\tu8(*check_ips_status)(_adapter *padapter);\n#if defined(CONFIG_PCI_HCI)\n\ts32(*interrupt_handler)(_adapter *padapter);\n\tvoid (*unmap_beacon_icf)(_adapter *padapter);\n#endif\n\n#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)\n\tvoid\t(*interrupt_handler)(_adapter *padapter, u16 pkt_len, u8 *pbuf);\n#endif\n\n#if defined(CONFIG_PCI_HCI)\n\tvoid\t(*irp_reset)(_adapter *padapter);\n#endif\n\n\t/*** DM section ***/\n#ifdef CONFIG_RTW_SW_LED\n\tvoid\t(*InitSwLeds)(_adapter *padapter);\n\tvoid\t(*DeInitSwLeds)(_adapter *padapter);\n#endif\n\tvoid\t(*set_chnl_bw_handler)(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80);\n\n\tvoid (*set_tx_power_level_handler)(_adapter *adapter, u8 channel);\n\tvoid (*set_txpwr_done)(_adapter *adapter);\n\tvoid (*set_tx_power_index_handler)(_adapter *adapter, u32 powerindex, enum rf_path rfpath, u8 rate);\n\tu8 (*get_tx_power_index_handler)(_adapter *adapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic);\n\n\tvoid\t(*hal_dm_watchdog)(_adapter *padapter);\n\n\tu8\t(*set_hw_reg_handler)(_adapter *padapter, u8\tvariable, u8 *val);\n\n\tvoid\t(*GetHwRegHandler)(_adapter *padapter, u8\tvariable, u8 *val);\n\n\n\n\tu8 (*get_hal_def_var_handler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);\n\n\tu8(*SetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);\n\n\tvoid\t(*GetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2);\n\tvoid\t(*SetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet);\n\n\tvoid\t(*SetBeaconRelatedRegistersHandler)(_adapter *padapter);\n\n\tu8(*interface_ps_func)(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);\n\n\tu32(*read_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask);\n\tvoid\t(*write_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);\n\tu32 (*read_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask);\n\tvoid\t(*write_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);\n#ifdef CONFIG_SYSON_INDIRECT_ACCESS\n\tu32 (*read_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask);\n\tvoid (*write_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);\n#endif\n\tvoid (*read_wmmedca_reg)(_adapter *padapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params);\n\t\n#ifdef CONFIG_HOSTAPD_MLME\n\ts32(*hostap_mgnt_xmit_entry)(_adapter *padapter, _pkt *pkt);\n#endif\n\n\tvoid (*EfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState);\n\tvoid (*BTEfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState);\n\tvoid (*ReadEFuse)(_adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, BOOLEAN bPseudoTest);\n\tvoid (*EFUSEGetEfuseDefinition)(_adapter *padapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest);\n\tu16(*EfuseGetCurrentSize)(_adapter *padapter, u8 efuseType, BOOLEAN bPseudoTest);\n\tint\t(*Efuse_PgPacketRead)(_adapter *padapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);\n\tint\t(*Efuse_PgPacketWrite)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);\n\tu8(*Efuse_WordEnableDataWrite)(_adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);\n\tBOOLEAN(*Efuse_PgPacketWrite_BT)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);\n#if defined(CONFIG_RTL8710B)\n\tBOOLEAN(*efuse_indirect_read4)(_adapter *padapter, u16 regaddr, u8 *value);\n#endif\n\n#ifdef DBG_CONFIG_ERROR_DETECT\n\tvoid (*sreset_init_value)(_adapter *padapter);\n\tvoid (*sreset_reset_value)(_adapter *padapter);\n\tvoid (*silentreset)(_adapter *padapter);\n\tvoid (*sreset_xmit_status_check)(_adapter *padapter);\n\tvoid (*sreset_linked_status_check)(_adapter *padapter);\n\tu8(*sreset_get_wifi_status)(_adapter *padapter);\n\tbool (*sreset_inprogress)(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_IOL\n\tint (*IOL_exec_cmds_sync)(_adapter *padapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);\n#endif\n\n\tvoid (*hal_notch_filter)(_adapter *adapter, bool enable);\n#ifdef RTW_HALMAC\n\tvoid (*hal_mac_c2h_handler)(_adapter *adapter, u8 *pbuf, u16 length);\n#else\n\ts32(*c2h_handler)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);\n#endif\n\tvoid (*reqtxrpt)(_adapter *padapter, u8 macid);\n\ts32(*fill_h2c_cmd)(PADAPTER, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);\n\tvoid (*fill_fake_txdesc)(PADAPTER, u8 *pDesc, u32 BufferLen,\n\t\t\t\t u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);\n\ts32(*fw_dl)(_adapter *adapter, u8 wowlan);\n#ifdef RTW_HALMAC\n\ts32 (*fw_mem_dl)(_adapter *adapter, enum fw_mem mem);\n#endif\n\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_PCI_HCI)\n\tvoid (*clear_interrupt)(_adapter *padapter);\n#endif\n\tu8(*hal_get_tx_buff_rsvd_page_num)(_adapter *adapter, bool wowlan);\n#ifdef CONFIG_GPIO_API\n\tvoid (*update_hisr_hsisr_ind)(PADAPTER padapter, u32 flag);\n\tint (*hal_gpio_func_check)(_adapter *padapter, u8 gpio_num);\n\tvoid (*hal_gpio_multi_func_reset)(_adapter *padapter, u8 gpio_num);\n#endif\n#ifdef CONFIG_FW_CORRECT_BCN\n\tvoid (*fw_correct_bcn)(PADAPTER padapter);\n#endif\n\n#ifdef RTW_HALMAC\n\tu8(*init_mac_register)(PADAPTER);\n\tu8(*init_phy)(PADAPTER);\n#endif /* RTW_HALMAC */\n\n#ifdef CONFIG_PCI_HCI\n\tvoid (*hal_set_l1ssbackdoor_handler)(_adapter *padapter, u8 enable);\n#endif\n\n#ifdef CONFIG_RFKILL_POLL\n\tbool (*hal_radio_onoff_check)(_adapter *adapter, u8 *valid);\n#endif\n#ifdef CONFIG_PCI_TX_POLLING\n\tvoid (*tx_poll_handler)(_adapter *adapter);\n#endif\n};\n\ntypedef\tenum _RT_EEPROM_TYPE {\n\tEEPROM_93C46,\n\tEEPROM_93C56,\n\tEEPROM_BOOT_EFUSE,\n} RT_EEPROM_TYPE, *PRT_EEPROM_TYPE;\n\n\n\n#define RF_CHANGE_BY_INIT\t0\n#define RF_CHANGE_BY_IPS\tBIT28\n#define RF_CHANGE_BY_PS\tBIT29\n#define RF_CHANGE_BY_HW\tBIT30\n#define RF_CHANGE_BY_SW\tBIT31\n\ntypedef enum _HARDWARE_TYPE {\n\tHARDWARE_TYPE_RTL8188EE,\n\tHARDWARE_TYPE_RTL8188EU,\n\tHARDWARE_TYPE_RTL8188ES,\n\t/*\tNEW_GENERATION_IC */\n\tHARDWARE_TYPE_RTL8192EE,\n\tHARDWARE_TYPE_RTL8192EU,\n\tHARDWARE_TYPE_RTL8192ES,\n\tHARDWARE_TYPE_RTL8812E,\n\tHARDWARE_TYPE_RTL8812AU,\n\tHARDWARE_TYPE_RTL8811AU,\n\tHARDWARE_TYPE_RTL8821E,\n\tHARDWARE_TYPE_RTL8821U,\n\tHARDWARE_TYPE_RTL8821S,\n\tHARDWARE_TYPE_RTL8723BE,\n\tHARDWARE_TYPE_RTL8723BU,\n\tHARDWARE_TYPE_RTL8723BS,\n\tHARDWARE_TYPE_RTL8814AE,\n\tHARDWARE_TYPE_RTL8814AU,\n\tHARDWARE_TYPE_RTL8814AS,\n\tHARDWARE_TYPE_RTL8821BE,\n\tHARDWARE_TYPE_RTL8821BU,\n\tHARDWARE_TYPE_RTL8821BS,\n\tHARDWARE_TYPE_RTL8822BE,\n\tHARDWARE_TYPE_RTL8822BU,\n\tHARDWARE_TYPE_RTL8822BS,\n\tHARDWARE_TYPE_RTL8703BE,\n\tHARDWARE_TYPE_RTL8703BU,\n\tHARDWARE_TYPE_RTL8703BS,\n\tHARDWARE_TYPE_RTL8188FE,\n\tHARDWARE_TYPE_RTL8188FU,\n\tHARDWARE_TYPE_RTL8188FS,\n\tHARDWARE_TYPE_RTL8188GTVU,\n\tHARDWARE_TYPE_RTL8188GTVS,\n\tHARDWARE_TYPE_RTL8723DE,\n\tHARDWARE_TYPE_RTL8723DU,\n\tHARDWARE_TYPE_RTL8723DS,\n\tHARDWARE_TYPE_RTL8821CE,\n\tHARDWARE_TYPE_RTL8821CU,\n\tHARDWARE_TYPE_RTL8821CS,\n\tHARDWARE_TYPE_RTL8710BU,\n\tHARDWARE_TYPE_RTL8192FS,\n\tHARDWARE_TYPE_RTL8192FU,\n\tHARDWARE_TYPE_RTL8192FE,\n\tHARDWARE_TYPE_RTL8822CE,\n\tHARDWARE_TYPE_RTL8822CU,\n\tHARDWARE_TYPE_RTL8822CS,\n\tHARDWARE_TYPE_RTL8814BE,\n\tHARDWARE_TYPE_RTL8814BU,\n\tHARDWARE_TYPE_RTL8814BS,\n\tHARDWARE_TYPE_MAX,\n} HARDWARE_TYPE;\n\n#define IS_NEW_GENERATION_IC(_Adapter)\t(rtw_get_hw_type(_Adapter) >= HARDWARE_TYPE_RTL8192EE)\n/*\n * RTL8188E Series\n *   */\n#define IS_HARDWARE_TYPE_8188EE(_Adapter)\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EE)\n#define IS_HARDWARE_TYPE_8188EU(_Adapter)\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EU)\n#define IS_HARDWARE_TYPE_8188ES(_Adapter)\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188ES)\n#define\tIS_HARDWARE_TYPE_8188E(_Adapter)\t\\\n\t(IS_HARDWARE_TYPE_8188EE(_Adapter) || IS_HARDWARE_TYPE_8188EU(_Adapter) || IS_HARDWARE_TYPE_8188ES(_Adapter))\n\n/* RTL8812 Series */\n#define IS_HARDWARE_TYPE_8812E(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812E)\n#define IS_HARDWARE_TYPE_8812AU(_Adapter)\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812AU)\n#define IS_HARDWARE_TYPE_8812(_Adapter)\t\t\t\\\n\t(IS_HARDWARE_TYPE_8812E(_Adapter) || IS_HARDWARE_TYPE_8812AU(_Adapter))\n\n/* RTL8821 Series */\n#define IS_HARDWARE_TYPE_8821E(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821E)\n#define IS_HARDWARE_TYPE_8811AU(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU)\n#define IS_HARDWARE_TYPE_8821U(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821U || \\\n\t\trtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU)\n#define IS_HARDWARE_TYPE_8821S(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821S)\n#define IS_HARDWARE_TYPE_8821(_Adapter)\t\t\t\\\n\t(IS_HARDWARE_TYPE_8821E(_Adapter) || IS_HARDWARE_TYPE_8821U(_Adapter) || IS_HARDWARE_TYPE_8821S(_Adapter))\n\n#define IS_HARDWARE_TYPE_JAGUAR(_Adapter)\t\t\\\n\t(IS_HARDWARE_TYPE_8812(_Adapter) || IS_HARDWARE_TYPE_8821(_Adapter))\n\n/* RTL8192E Series */\n#define IS_HARDWARE_TYPE_8192EE(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EE)\n#define IS_HARDWARE_TYPE_8192EU(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EU)\n#define IS_HARDWARE_TYPE_8192ES(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192ES)\n\n#define IS_HARDWARE_TYPE_8192E(_Adapter)\t\t\\\n\t(IS_HARDWARE_TYPE_8192EE(_Adapter) || IS_HARDWARE_TYPE_8192EU(_Adapter) || IS_HARDWARE_TYPE_8192ES(_Adapter))\n\n#define IS_HARDWARE_TYPE_8723BE(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BE)\n#define IS_HARDWARE_TYPE_8723BU(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BU)\n#define IS_HARDWARE_TYPE_8723BS(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BS)\n\n#define IS_HARDWARE_TYPE_8723B(_Adapter) \\\n\t(IS_HARDWARE_TYPE_8723BE(_Adapter) || IS_HARDWARE_TYPE_8723BU(_Adapter) || IS_HARDWARE_TYPE_8723BS(_Adapter))\n\n/* RTL8814A Series */\n#define IS_HARDWARE_TYPE_8814AE(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AE)\n#define IS_HARDWARE_TYPE_8814AU(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AU)\n#define IS_HARDWARE_TYPE_8814AS(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AS)\n\n#define IS_HARDWARE_TYPE_8814A(_Adapter)\t\t\\\n\t(IS_HARDWARE_TYPE_8814AE(_Adapter) || IS_HARDWARE_TYPE_8814AU(_Adapter) || IS_HARDWARE_TYPE_8814AS(_Adapter))\n\n/* RTL8703B Series */\n#define IS_HARDWARE_TYPE_8703BE(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BE)\n#define IS_HARDWARE_TYPE_8703BS(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BS)\n#define IS_HARDWARE_TYPE_8703BU(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BU)\n#define\tIS_HARDWARE_TYPE_8703B(_Adapter)\t\t\t\\\n\t(IS_HARDWARE_TYPE_8703BE(_Adapter) || IS_HARDWARE_TYPE_8703BU(_Adapter) || IS_HARDWARE_TYPE_8703BS(_Adapter))\n\n/* RTL8723D Series */\n#define IS_HARDWARE_TYPE_8723DE(_Adapter)\\\n\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DE)\n#define IS_HARDWARE_TYPE_8723DS(_Adapter)\\\n\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DS)\n#define IS_HARDWARE_TYPE_8723DU(_Adapter)\\\n\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DU)\n#define\tIS_HARDWARE_TYPE_8723D(_Adapter)\\\n\t(IS_HARDWARE_TYPE_8723DE(_Adapter) || \\\n\t IS_HARDWARE_TYPE_8723DU(_Adapter) || \\\n\t IS_HARDWARE_TYPE_8723DS(_Adapter))\n\n/* RTL8192F Series */\n#define IS_HARDWARE_TYPE_8192FS(_Adapter)\\\n\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FS)\n#define IS_HARDWARE_TYPE_8192FU(_Adapter)\\\n\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FU)\t\n#define IS_HARDWARE_TYPE_8192FE(_Adapter)\\\n\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FE)\t\n#define\tIS_HARDWARE_TYPE_8192F(_Adapter)\\\n\t(IS_HARDWARE_TYPE_8192FS(_Adapter) ||\\\n\t IS_HARDWARE_TYPE_8192FU(_Adapter) ||\\\n\t IS_HARDWARE_TYPE_8192FE(_Adapter))\n\n/* RTL8188F Series */\n#define IS_HARDWARE_TYPE_8188FE(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FE)\n#define IS_HARDWARE_TYPE_8188FS(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FS)\n#define IS_HARDWARE_TYPE_8188FU(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FU)\n#define\tIS_HARDWARE_TYPE_8188F(_Adapter)\t\t\t\\\n\t(IS_HARDWARE_TYPE_8188FE(_Adapter) || IS_HARDWARE_TYPE_8188FU(_Adapter) || IS_HARDWARE_TYPE_8188FS(_Adapter))\n\n#define IS_HARDWARE_TYPE_8188GTVU(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVU)\n#define IS_HARDWARE_TYPE_8188GTVS(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVS)\n#define\tIS_HARDWARE_TYPE_8188GTV(_Adapter)\t\t\t\\\n\t(IS_HARDWARE_TYPE_8188GTVU(_Adapter) || IS_HARDWARE_TYPE_8188GTVS(_Adapter))\n\n/* RTL8710B Series */\n#define IS_HARDWARE_TYPE_8710BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8710BU)\n#define IS_HARDWARE_TYPE_8710B(_Adapter) (IS_HARDWARE_TYPE_8710BU(_Adapter))\n\n#define IS_HARDWARE_TYPE_8821BE(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BE)\n#define IS_HARDWARE_TYPE_8821BU(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BU)\n#define IS_HARDWARE_TYPE_8821BS(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BS)\n\n#define IS_HARDWARE_TYPE_8821B(_Adapter)\t\t\\\n\t(IS_HARDWARE_TYPE_8821BE(_Adapter) || IS_HARDWARE_TYPE_8821BU(_Adapter) || IS_HARDWARE_TYPE_8821BS(_Adapter))\n\n#define IS_HARDWARE_TYPE_8822BE(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BE)\n#define IS_HARDWARE_TYPE_8822BU(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BU)\n#define IS_HARDWARE_TYPE_8822BS(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BS)\n#define IS_HARDWARE_TYPE_8822B(_Adapter)\t\t\\\n\t(IS_HARDWARE_TYPE_8822BE(_Adapter) || IS_HARDWARE_TYPE_8822BU(_Adapter) || IS_HARDWARE_TYPE_8822BS(_Adapter))\n\n#define IS_HARDWARE_TYPE_8821CE(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CE)\n#define IS_HARDWARE_TYPE_8821CU(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CU)\n#define IS_HARDWARE_TYPE_8821CS(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CS)\n#define IS_HARDWARE_TYPE_8821C(_Adapter)\t\t\\\n\t(IS_HARDWARE_TYPE_8821CE(_Adapter) || IS_HARDWARE_TYPE_8821CU(_Adapter) || IS_HARDWARE_TYPE_8821CS(_Adapter))\n\n#define IS_HARDWARE_TYPE_8822CE(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CE)\n#define IS_HARDWARE_TYPE_8822CU(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CU)\n#define IS_HARDWARE_TYPE_8822CS(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CS)\n#define IS_HARDWARE_TYPE_8822C(_Adapter)\t\t\\\n\t(IS_HARDWARE_TYPE_8822CE(_Adapter) || IS_HARDWARE_TYPE_8822CU(_Adapter) || IS_HARDWARE_TYPE_8822CS(_Adapter))\n\n#define IS_HARDWARE_TYPE_8814BE(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BE)\n#define IS_HARDWARE_TYPE_8814BU(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BU)\n#define IS_HARDWARE_TYPE_8814BS(_Adapter)\t\t(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BS)\n#define IS_HARDWARE_TYPE_8814B(_Adapter)\t\t\\\n\t\t(IS_HARDWARE_TYPE_8814BE(_Adapter) || IS_HARDWARE_TYPE_8814BU(_Adapter) || IS_HARDWARE_TYPE_8814BS(_Adapter))\n\n#define IS_HARDWARE_TYPE_JAGUAR2(_Adapter)\t\t\\\n\t(IS_HARDWARE_TYPE_8814A(_Adapter) || IS_HARDWARE_TYPE_8821B(_Adapter) || IS_HARDWARE_TYPE_8822B(_Adapter) || IS_HARDWARE_TYPE_8821C(_Adapter))\n\n#define IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter)\t\t\\\n\t(IS_HARDWARE_TYPE_JAGUAR(_Adapter) || IS_HARDWARE_TYPE_JAGUAR2(_Adapter))\n\n#define IS_HARDWARE_TYPE_JAGUAR3(_Adapter)\t\t\\\n\t(IS_HARDWARE_TYPE_8814B(_Adapter) || IS_HARDWARE_TYPE_8822C(_Adapter))\n\n#define IS_HARDWARE_TYPE_JAGUAR_ALL(_Adapter)\t\t\\\n\t(IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter) || IS_HARDWARE_TYPE_JAGUAR3(_Adapter))\n\n\ntypedef enum _wowlan_subcode {\n\tWOWLAN_ENABLE\t\t\t= 0,\n\tWOWLAN_DISABLE\t\t\t= 1,\n\tWOWLAN_AP_ENABLE\t\t= 2,\n\tWOWLAN_AP_DISABLE\t\t= 3,\n\tWOWLAN_PATTERN_CLEAN\t\t= 4\n} wowlan_subcode;\n\nstruct wowlan_ioctl_param {\n\tunsigned int subcode;\n\tunsigned int subcode_value;\n\tunsigned int wakeup_reason;\n};\n\nu8 rtw_hal_data_init(_adapter *padapter);\nvoid rtw_hal_data_deinit(_adapter *padapter);\n\nvoid rtw_hal_def_value_init(_adapter *padapter);\n\nvoid\trtw_hal_free_data(_adapter *padapter);\n\nvoid rtw_hal_dm_init(_adapter *padapter);\nvoid rtw_hal_dm_deinit(_adapter *padapter);\n#ifdef CONFIG_RTW_SW_LED\nvoid rtw_hal_sw_led_init(_adapter *padapter);\nvoid rtw_hal_sw_led_deinit(_adapter *padapter);\n#endif\nu32 rtw_hal_power_on(_adapter *padapter);\nvoid rtw_hal_power_off(_adapter *padapter);\n\nuint rtw_hal_init(_adapter *padapter);\n#ifdef CONFIG_NEW_NETDEV_HDL\nuint rtw_hal_iface_init(_adapter *adapter);\n#endif\nuint rtw_hal_deinit(_adapter *padapter);\nvoid rtw_hal_stop(_adapter *padapter);\nu8 rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val);\nvoid rtw_hal_get_hwreg(PADAPTER padapter, u8 variable, u8 *val);\n\nvoid rtw_hal_chip_configure(_adapter *padapter);\nu8 rtw_hal_read_chip_info(_adapter *padapter);\nvoid rtw_hal_read_chip_version(_adapter *padapter);\n\nu8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);\nu8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);\n\nvoid rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet);\nvoid\trtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2);\n\nvoid rtw_hal_enable_interrupt(_adapter *padapter);\nvoid rtw_hal_disable_interrupt(_adapter *padapter);\n\nu8 rtw_hal_check_ips_status(_adapter *padapter);\n\n#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)\n\tu32\trtw_hal_inirp_init(_adapter *padapter);\n\tu32\trtw_hal_inirp_deinit(_adapter *padapter);\n#endif\n\n#if defined(CONFIG_PCI_HCI)\n\tvoid\trtw_hal_irp_reset(_adapter *padapter);\nvoid\trtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data);\nu8\trtw_hal_pci_dbi_read(_adapter *padapter, u16 addr);\nvoid\trtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data);\nu16\trtw_hal_pci_mdio_read(_adapter *padapter, u8 addr);\nu8\trtw_hal_pci_l1off_nic_support(_adapter *padapter);\nu8\trtw_hal_pci_l1off_capability(_adapter *padapter);\n#endif\n\nu8\trtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);\n\ns32\trtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\ns32\trtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);\ns32\trtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);\n\ns32\trtw_hal_init_xmit_priv(_adapter *padapter);\nvoid\trtw_hal_free_xmit_priv(_adapter *padapter);\n\ns32\trtw_hal_init_recv_priv(_adapter *padapter);\nvoid\trtw_hal_free_recv_priv(_adapter *padapter);\n\nvoid rtw_hal_update_ra_mask(struct sta_info *psta);\n\nvoid\trtw_hal_start_thread(_adapter *padapter);\nvoid\trtw_hal_stop_thread(_adapter *padapter);\n\nvoid rtw_hal_bcn_related_reg_setting(_adapter *padapter);\n\nu32\trtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask);\nvoid\trtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);\nu32\trtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask);\nvoid\trtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);\n\n\n#define phy_query_bb_reg(Adapter, RegAddr, BitMask) rtw_hal_read_bbreg((Adapter), (RegAddr), (BitMask))\n#define phy_set_bb_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_bbreg((Adapter), (RegAddr), (BitMask), (Data))\n#define phy_query_rf_reg(Adapter, eRFPath, RegAddr, BitMask) rtw_hal_read_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask))\n#define phy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data) rtw_hal_write_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))\n\n#ifdef CONFIG_SYSON_INDIRECT_ACCESS\nu32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask);\nvoid rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);\n#define hal_query_syson_reg(Adapter, RegAddr, BitMask) rtw_hal_read_syson_reg((Adapter), (RegAddr), (BitMask))\n#define hal_set_syson_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_syson_reg((Adapter), (RegAddr), (BitMask), (Data))\n#endif\n\n#define phy_set_mac_reg\tphy_set_bb_reg\n#define phy_query_mac_reg phy_query_bb_reg\n\n#if defined(CONFIG_PCI_HCI)\n\ts32\trtw_hal_interrupt_handler(_adapter *padapter);\n\tvoid\trtw_hal_unmap_beacon_icf(_adapter *padapter);\n#endif\n#if  defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)\n\tvoid\trtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf);\n#endif\n\nvoid\trtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80);\nvoid\trtw_hal_dm_watchdog(_adapter *padapter);\nvoid\trtw_hal_dm_watchdog_in_lps(_adapter *padapter);\n\n#ifdef CONFIG_HOSTAPD_MLME\n\ts32\trtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);\n#endif\n\n#ifdef DBG_CONFIG_ERROR_DETECT\nvoid rtw_hal_sreset_init(_adapter *padapter);\nvoid rtw_hal_sreset_reset(_adapter *padapter);\nvoid rtw_hal_sreset_reset_value(_adapter *padapter);\nvoid rtw_hal_sreset_xmit_status_check(_adapter *padapter);\nvoid rtw_hal_sreset_linked_status_check(_adapter *padapter);\nu8   rtw_hal_sreset_get_wifi_status(_adapter *padapter);\nbool rtw_hal_sreset_inprogress(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_IOL\nint rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);\n#endif\n\n#ifdef CONFIG_XMIT_THREAD_MODE\ns32 rtw_hal_xmit_thread_handler(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_RECV_THREAD_MODE\ns32 rtw_hal_recv_hdl(_adapter *adapter);\n#endif\n\nvoid rtw_hal_notch_filter(_adapter *adapter, bool enable);\n\n#ifdef CONFIG_FW_C2H_REG\nbool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload);\nbool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf);\ns32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf);\n#endif\n\n#ifdef CONFIG_FW_C2H_PKT\nbool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload);\n#endif\n\ns32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);\n#ifndef RTW_HALMAC\ns32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);\ns32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);\n#endif\n\ns32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter);\n\ns32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid);\ns32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid);\ns32 rtw_hal_macid_sleep_all_used(_adapter *adapter);\ns32 rtw_hal_macid_wakeup_all_used(_adapter *adapter);\n\ns32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);\nvoid rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen,\n\t\t\t      u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);\nu8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan);\n\n#ifdef CONFIG_GPIO_API\nvoid rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag);\nint rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num);\nvoid rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num);\n#endif\n#ifdef CONFIG_FW_CORRECT_BCN\nvoid rtw_hal_fw_correct_bcn(_adapter *padapter);\n#endif\ns32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan);\n\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\n\tvoid rtw_hal_clear_interrupt(_adapter *padapter);\n#endif\n\nvoid rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel);\nvoid rtw_hal_set_txpwr_done(_adapter *adapter);\nvoid rtw_hal_set_tx_power_index(_adapter *adapter, u32 powerindex\n\t, enum rf_path rfpath, u8 rate);\nu8 rtw_hal_get_tx_power_index(_adapter *adapter, enum rf_path rfpath, u8 rate\n\t, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic);\n\nu8 rtw_hal_ops_check(_adapter *padapter);\n\n#ifdef RTW_HALMAC\n\tu8 rtw_hal_init_mac_register(PADAPTER);\n\tu8 rtw_hal_init_phy(PADAPTER);\ns32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem);\n#endif /* RTW_HALMAC */\n\n#ifdef CONFIG_RFKILL_POLL\nbool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid);\n#endif\n\n#endif /* __HAL_INTF_H__ */\n"
  },
  {
    "path": "include/hal_pg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef __HAL_PG_H__\n#define __HAL_PG_H__\n\n#define PPG_BB_GAIN_2G_TX_OFFSET_MASK\t0x0F\n#define PPG_BB_GAIN_2G_TXB_OFFSET_MASK\t0xF0\n\n#define PPG_BB_GAIN_5G_TX_OFFSET_MASK\t0x1F\n#define PPG_THERMAL_OFFSET_MASK\t\t\t0x1F\n#define KFREE_BB_GAIN_2G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))\n#define KFREE_BB_GAIN_2G_TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg_v) >> 5) : (-((_ppg_v) >> 5))))\n#define KFREE_BB_GAIN_5G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))\n#define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))\n\n/* ****************************************************\n *\t\t\tEEPROM/Efuse PG Offset for 88EE/88EU/88ES\n * **************************************************** */\n#define EEPROM_ChannelPlan_88E\t\t\t\t\t0xB8\n#define EEPROM_XTAL_88E\t\t\t\t\t\t0xB9\n#define EEPROM_THERMAL_METER_88E\t\t\t\t0xBA\n#define EEPROM_IQK_LCK_88E\t\t\t\t\t\t0xBB\n\n#define EEPROM_RF_BOARD_OPTION_88E\t\t\t0xC1\n#define EEPROM_RF_FEATURE_OPTION_88E\t\t\t0xC2\n#define EEPROM_RF_BT_SETTING_88E\t\t\t\t0xC3\n#define EEPROM_VERSION_88E\t\t\t\t\t\t0xC4\n#define EEPROM_CustomID_88E\t\t\t\t\t0xC5\n#define EEPROM_RF_ANTENNA_OPT_88E\t\t\t0xC9\n#define EEPROM_COUNTRY_CODE_88E\t\t\t\t0xCB\n\n/* RTL88EE */\n#define EEPROM_MAC_ADDR_88EE\t\t\t\t\t0xD0\n#define EEPROM_VID_88EE\t\t\t\t\t\t0xD6\n#define EEPROM_DID_88EE\t\t\t\t\t\t0xD8\n#define EEPROM_SVID_88EE\t\t\t\t\t\t0xDA\n#define EEPROM_SMID_88EE\t\t\t\t\t\t0xDC\n\n/* RTL88EU */\n#define EEPROM_MAC_ADDR_88EU\t\t\t\t\t0xD7\n#define EEPROM_VID_88EU\t\t\t\t\t\t0xD0\n#define EEPROM_PID_88EU\t\t\t\t\t\t0xD2\n#define EEPROM_USB_OPTIONAL_FUNCTION0\t\t0xD4 /* 8188EU, 8192EU, 8812AU is the same */\n#define EEPROM_USB_OPTIONAL_FUNCTION0_8811AU 0x104\n\n/* RTL88ES */\n#define EEPROM_MAC_ADDR_88ES\t\t\t\t\t0x11A\n/* ****************************************************\n *\t\t\tEEPROM/Efuse PG Offset for 8192EE/8192EU/8192ES\n * **************************************************** */\n#define GET_PG_KFREE_ON_8192E(_pg_m)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)\n#define GET_PG_KFREE_THERMAL_K_ON_8192E(_pg_m)\tLE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)\n\n#define PPG_BB_GAIN_2G_TXA_OFFSET_8192E\t0x1F6\n#define PPG_THERMAL_OFFSET_8192E\t\t0x1F5\n\n#define\tEEPROM_ChannelPlan_8192E\t\t\t\t0xB8\n#define\tEEPROM_XTAL_8192E\t\t\t\t\t\t0xB9\n#define\tEEPROM_THERMAL_METER_8192E\t\t\t0xBA\n#define\tEEPROM_IQK_LCK_8192E\t\t\t\t\t0xBB\n#define\tEEPROM_2G_5G_PA_TYPE_8192E\t\t\t0xBC\n#define\tEEPROM_2G_LNA_TYPE_GAIN_SEL_8192E\t0xBD\n#define\tEEPROM_5G_LNA_TYPE_GAIN_SEL_8192E\t0xBF\n\n#define\tEEPROM_RF_BOARD_OPTION_8192E\t\t0xC1\n#define\tEEPROM_RF_FEATURE_OPTION_8192E\t\t0xC2\n#define\tEEPROM_RF_BT_SETTING_8192E\t\t\t0xC3\n#define\tEEPROM_VERSION_8192E\t\t\t\t\t0xC4\n#define\tEEPROM_CustomID_8192E\t\t\t\t0xC5\n#define\tEEPROM_TX_BBSWING_2G_8192E\t\t\t0xC6\n#define\tEEPROM_TX_BBSWING_5G_8192E\t\t\t0xC7\n#define\tEEPROM_TX_PWR_CALIBRATE_RATE_8192E\t0xC8\n#define\tEEPROM_RF_ANTENNA_OPT_8192E\t\t\t0xC9\n#define\tEEPROM_RFE_OPTION_8192E\t\t\t\t0xCA\n#define\tEEPROM_RFE_OPTION_8188E\t\t\t\t0xCA\n#define EEPROM_COUNTRY_CODE_8192E\t\t\t0xCB\n\n/* RTL8192EE */\n#define\tEEPROM_MAC_ADDR_8192EE\t\t\t\t0xD0\n#define\tEEPROM_VID_8192EE\t\t\t\t\t\t0xD6\n#define\tEEPROM_DID_8192EE\t\t\t\t\t\t0xD8\n#define\tEEPROM_SVID_8192EE\t\t\t\t\t0xDA\n#define\tEEPROM_SMID_8192EE\t\t\t\t\t0xDC\n\n/* RTL8192EU */\n#define\tEEPROM_MAC_ADDR_8192EU\t\t\t\t0xD7\n#define\tEEPROM_VID_8192EU\t\t\t\t\t\t0xD0\n#define\tEEPROM_PID_8192EU\t\t\t\t\t\t0xD2\n#define\tEEPROM_PA_TYPE_8192EU\t\t0xBC\n#define\tEEPROM_LNA_TYPE_2G_8192EU\t0xBD\n#define\tEEPROM_LNA_TYPE_5G_8192EU\t0xBF\n\n/* RTL8192ES */\n#define\tEEPROM_MAC_ADDR_8192ES\t\t\t\t0x11A\n/* ****************************************************\n *\t\t\tEEPROM/Efuse PG Offset for 8812AE/8812AU/8812AS\n * *****************************************************/\n#define EEPROM_USB_MODE_8812\t\t\t\t\t0x08\n\n#define EEPROM_ChannelPlan_8812\t\t\t\t0xB8\n#define EEPROM_XTAL_8812\t\t\t\t\t\t0xB9\n#define EEPROM_THERMAL_METER_8812\t\t\t0xBA\n#define EEPROM_IQK_LCK_8812\t\t\t\t\t0xBB\n#define EEPROM_2G_5G_PA_TYPE_8812\t\t\t0xBC\n#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8812\t0xBD\n#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8812\t0xBF\n\n#define EEPROM_RF_BOARD_OPTION_8812\t\t\t0xC1\n#define EEPROM_RF_FEATURE_OPTION_8812\t\t0xC2\n#define EEPROM_RF_BT_SETTING_8812\t\t\t\t0xC3\n#define EEPROM_VERSION_8812\t\t\t\t\t0xC4\n#define EEPROM_CustomID_8812\t\t\t\t\t0xC5\n#define EEPROM_TX_BBSWING_2G_8812\t\t\t0xC6\n#define EEPROM_TX_BBSWING_5G_8812\t\t\t0xC7\n#define EEPROM_TX_PWR_CALIBRATE_RATE_8812\t0xC8\n#define EEPROM_RF_ANTENNA_OPT_8812\t\t\t0xC9\n#define EEPROM_RFE_OPTION_8812\t\t\t\t0xCA\n#define EEPROM_COUNTRY_CODE_8812\t\t\t0xCB\n\n/* RTL8812AE */\n#define EEPROM_MAC_ADDR_8812AE\t\t\t\t0xD0\n#define EEPROM_VID_8812AE\t\t\t\t\t\t0xD6\n#define EEPROM_DID_8812AE\t\t\t\t\t\t0xD8\n#define EEPROM_SVID_8812AE\t\t\t\t\t\t0xDA\n#define EEPROM_SMID_8812AE\t\t\t\t\t0xDC\n\n/* RTL8812AU */\n#define EEPROM_MAC_ADDR_8812AU\t\t\t\t0xD7\n#define EEPROM_VID_8812AU\t\t\t\t\t\t0xD0\n#define EEPROM_PID_8812AU\t\t\t\t\t\t0xD2\n#define EEPROM_PA_TYPE_8812AU\t\t\t\t\t0xBC\n#define EEPROM_LNA_TYPE_2G_8812AU\t\t\t0xBD\n#define EEPROM_LNA_TYPE_5G_8812AU\t\t\t0xBF\n\n/* RTL8814AU */\n#define\tEEPROM_MAC_ADDR_8814AU\t\t\t\t0xD8\n#define\tEEPROM_VID_8814AU\t\t\t\t\t\t0xD0\n#define\tEEPROM_PID_8814AU\t\t\t\t\t\t0xD2\n#define\tEEPROM_PA_TYPE_8814AU\t\t\t\t0xBC\n#define\tEEPROM_LNA_TYPE_2G_8814AU\t\t\t0xBD\n#define\tEEPROM_LNA_TYPE_5G_8814AU\t\t\t0xBF\n\n/* RTL8814AE */\n#define EEPROM_MAC_ADDR_8814AE\t\t\t\t0xD0\n#define EEPROM_VID_8814AE\t\t\t\t\t\t0xD6\n#define EEPROM_DID_8814AE\t\t\t\t\t\t0xD8\n#define EEPROM_SVID_8814AE\t\t\t\t\t\t0xDA\n#define EEPROM_SMID_8814AE\t\t\t\t\t0xDC\n\n/* ****************************************************\n *\t\t\tEEPROM/Efuse PG Offset for 8814AU\n * **************************************************** */\n#define GET_PG_KFREE_ON_8814A(_pg_m)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1)\n#define GET_PG_KFREE_THERMAL_K_ON_8814A(_pg_m)\tLE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)\n#define GET_PG_TX_POWER_TRACKING_MODE_8814A(_pg_m)\tLE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 6, 2)\n\n#define KFREE_GAIN_DATA_LENGTH_8814A\t22\n\n#define PPG_BB_GAIN_2G_TXBA_OFFSET_8814A\t0x3EE\n\n#define PPG_THERMAL_OFFSET_8814A\t\t0x3EF\n\n#define EEPROM_USB_MODE_8814A\t\t\t\t0x0E\n#define EEPROM_ChannelPlan_8814\t\t\t\t0xB8\n#define EEPROM_XTAL_8814\t\t\t\t\t0xB9\n#define EEPROM_THERMAL_METER_8814\t\t\t0xBA\n#define\tEEPROM_IQK_LCK_8814\t\t\t\t\t0xBB\n\n\n#define EEPROM_PA_TYPE_8814\t\t\t\t\t0xBC\n#define EEPROM_LNA_TYPE_AB_2G_8814\t\t\t0xBD\n#define\tEEPROM_LNA_TYPE_CD_2G_8814\t\t\t0xBE\n#define EEPROM_LNA_TYPE_AB_5G_8814\t\t\t0xBF\n#define EEPROM_LNA_TYPE_CD_5G_8814\t\t\t0xC0\n#define\tEEPROM_RF_BOARD_OPTION_8814\t\t\t0xC1\n#define\tEEPROM_RF_BT_SETTING_8814\t\t\t0xC3\n#define\tEEPROM_VERSION_8814\t\t\t\t\t0xC4\n#define\tEEPROM_CustomID_8814\t\t\t\t0xC5\n#define\tEEPROM_TX_BBSWING_2G_8814\t\t\t0xC6\n#define\tEEPROM_TX_BBSWING_5G_8814\t\t\t0xC7\n#define EEPROM_TRX_ANTENNA_OPTION_8814\t\t0xC9\n#define\tEEPROM_RFE_OPTION_8814\t\t\t\t0xCA\n#define EEPROM_COUNTRY_CODE_8814\t\t\t0xCB\n\n/*Extra Info for 8814A Initial Gain Fine Tune  suggested by Willis, JIRA: MP123*/\n#define\tEEPROM_IG_OFFSET_4_AB_2G_8814A\t\t\t\t0x120\n#define\tEEPROM_IG_OFFSET_4_CD_2G_8814A\t\t\t\t0x121\n#define\tEEPROM_IG_OFFSET_4_AB_5GL_8814A\t\t\t\t0x122\n#define\tEEPROM_IG_OFFSET_4_CD_5GL_8814A\t\t\t\t0x123\n#define\tEEPROM_IG_OFFSET_4_AB_5GM_8814A\t\t\t\t0x124\n#define\tEEPROM_IG_OFFSET_4_CD_5GM_8814A\t\t\t\t0x125\n#define\tEEPROM_IG_OFFSET_4_AB_5GH_8814A\t\t\t\t0x126\n#define\tEEPROM_IG_OFFSET_4_CD_5GH_8814A\t\t\t\t0x127\n\n/* ****************************************************\n *\t\t\tEEPROM/Efuse PG Offset for 8821AE/8821AU/8821AS\n * **************************************************** */\n\n#define GET_PG_KFREE_ON_8821A(_pg_m)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1)\n#define GET_PG_KFREE_THERMAL_K_ON_8821A(_pg_m)\tLE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)\n\n#define PPG_BB_GAIN_2G_TXA_OFFSET_8821A\t\t0x1F6\n#define PPG_THERMAL_OFFSET_8821A\t\t\t0x1F5\n#define PPG_BB_GAIN_5GLB1_TXA_OFFSET_8821A\t0x1F4\n#define PPG_BB_GAIN_5GLB2_TXA_OFFSET_8821A\t0x1F3\n#define PPG_BB_GAIN_5GMB1_TXA_OFFSET_8821A\t0x1F2\n#define PPG_BB_GAIN_5GMB2_TXA_OFFSET_8821A\t0x1F1\n#define PPG_BB_GAIN_5GHB_TXA_OFFSET_8821A\t0x1F0\n\n#define EEPROM_ChannelPlan_8821\t\t\t\t0xB8\n#define EEPROM_XTAL_8821\t\t\t\t\t\t0xB9\n#define EEPROM_THERMAL_METER_8821\t\t\t0xBA\n#define EEPROM_IQK_LCK_8821\t\t\t\t\t0xBB\n\n\n#define EEPROM_RF_BOARD_OPTION_8821\t\t\t0xC1\n#define EEPROM_RF_FEATURE_OPTION_8821\t\t0xC2\n#define EEPROM_RF_BT_SETTING_8821\t\t\t\t0xC3\n#define EEPROM_VERSION_8821\t\t\t\t\t0xC4\n#define EEPROM_CustomID_8821\t\t\t\t\t0xC5\n#define EEPROM_RF_ANTENNA_OPT_8821\t\t\t0xC9\n\n/* RTL8821AE */\n#define EEPROM_MAC_ADDR_8821AE\t\t\t\t0xD0\n#define EEPROM_VID_8821AE\t\t\t\t\t\t0xD6\n#define EEPROM_DID_8821AE\t\t\t\t\t\t0xD8\n#define EEPROM_SVID_8821AE\t\t\t\t\t\t0xDA\n#define EEPROM_SMID_8821AE\t\t\t\t\t0xDC\n\n/* RTL8821AU */\n#define EEPROM_PA_TYPE_8821AU\t\t\t\t\t0xBC\n#define EEPROM_LNA_TYPE_8821AU\t\t\t\t0xBF\n\n/* RTL8821AS */\n#define EEPROM_MAC_ADDR_8821AS\t\t\t\t0x11A\n\n/* RTL8821AU */\n#define EEPROM_MAC_ADDR_8821AU\t\t\t\t0x107\n#define EEPROM_VID_8821AU\t\t\t\t\t\t0x100\n#define EEPROM_PID_8821AU\t\t\t\t\t\t0x102\n\n\n/* ****************************************************\n *\t\t\tEEPROM/Efuse PG Offset for 8192 SE/SU\n * **************************************************** */\n#define EEPROM_VID_92SE\t\t\t\t\t\t0x0A\n#define EEPROM_DID_92SE\t\t\t\t\t\t0x0C\n#define EEPROM_SVID_92SE\t\t\t\t\t\t0x0E\n#define EEPROM_SMID_92SE\t\t\t\t\t\t0x10\n\n#define EEPROM_MAC_ADDR_92S\t\t\t\t\t0x12\n\n#define EEPROM_TSSI_A_92SE\t\t\t\t\t\t0x74\n#define EEPROM_TSSI_B_92SE\t\t\t\t\t\t0x75\n\n#define EEPROM_Version_92SE\t\t\t\t\t0x7C\n\n\n#define EEPROM_VID_92SU\t\t\t\t\t\t0x08\n#define EEPROM_PID_92SU\t\t\t\t\t\t0x0A\n\n#define EEPROM_Version_92SU\t\t\t\t\t0x50\n#define EEPROM_TSSI_A_92SU\t\t\t\t\t\t0x6b\n#define EEPROM_TSSI_B_92SU\t\t\t\t\t\t0x6c\n\n/* ====================================================\n\tEEPROM/Efuse PG Offset for 8188FE/8188FU/8188FS\n   ====================================================\n */\n\n#define GET_PG_KFREE_ON_8188F(_pg_m)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)\n#define GET_PG_KFREE_THERMAL_K_ON_8188F(_pg_m)\tLE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)\n\n#define PPG_BB_GAIN_2G_TXA_OFFSET_8188F\t0xEE\n#define PPG_THERMAL_OFFSET_8188F\t\t0xEF\n\n#define\tEEPROM_ChannelPlan_8188F\t\t\t0xB8\n#define\tEEPROM_XTAL_8188F\t\t\t\t\t0xB9\n#define\tEEPROM_THERMAL_METER_8188F\t\t\t0xBA\n#define\tEEPROM_IQK_LCK_8188F\t\t\t\t0xBB\n#define\tEEPROM_2G_5G_PA_TYPE_8188F\t\t\t0xBC\n#define\tEEPROM_2G_LNA_TYPE_GAIN_SEL_8188F\t0xBD\n#define\tEEPROM_5G_LNA_TYPE_GAIN_SEL_8188F\t0xBF\n\n#define\tEEPROM_RF_BOARD_OPTION_8188F\t\t0xC1\n#define\tEEPROM_FEATURE_OPTION_8188F\t\t\t0xC2\n#define\tEEPROM_RF_BT_SETTING_8188F\t\t\t0xC3\n#define\tEEPROM_VERSION_8188F\t\t\t\t0xC4\n#define\tEEPROM_CustomID_8188F\t\t\t\t0xC5\n#define\tEEPROM_TX_BBSWING_2G_8188F\t\t\t0xC6\n#define\tEEPROM_TX_PWR_CALIBRATE_RATE_8188F\t0xC8\n#define\tEEPROM_RF_ANTENNA_OPT_8188F\t\t\t0xC9\n#define\tEEPROM_RFE_OPTION_8188F\t\t\t\t0xCA\n#define EEPROM_COUNTRY_CODE_8188F\t\t\t0xCB\n#define EEPROM_CUSTOMER_ID_8188F\t\t\t0x7F\n#define EEPROM_SUBCUSTOMER_ID_8188F\t\t\t0x59\n\n/* RTL8188FU */\n#define EEPROM_MAC_ADDR_8188FU\t\t\t\t0xD7\n#define EEPROM_VID_8188FU\t\t\t\t\t0xD0\n#define EEPROM_PID_8188FU\t\t\t\t\t0xD2\n#define EEPROM_PA_TYPE_8188FU\t\t\t\t0xBC\n#define EEPROM_LNA_TYPE_2G_8188FU\t\t\t0xBD\n#define EEPROM_USB_OPTIONAL_FUNCTION0_8188FU 0xD4\n\n/* RTL8188FS */\n#define\tEEPROM_MAC_ADDR_8188FS\t\t\t\t0x11A\n#define EEPROM_Voltage_ADDR_8188F\t\t\t0x8\n\n/* ====================================================\n\tEEPROM/Efuse PG Offset for 8188GTV/8188GTVS\n   ====================================================\n */\n\n#define GET_PG_KFREE_ON_8188GTV(_pg_m)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)\n#define GET_PG_KFREE_THERMAL_K_ON_8188GTV(_pg_m)\tLE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)\n\n#define PPG_BB_GAIN_2G_TXA_OFFSET_8188GTV\t0xEE\n#define PPG_THERMAL_OFFSET_8188GTV\t\t\t0xEF\n\n#define\tEEPROM_ChannelPlan_8188GTV\t\t\t\t0xB8\n#define\tEEPROM_XTAL_8188GTV\t\t\t\t\t\t0xB9\n#define\tEEPROM_THERMAL_METER_8188GTV\t\t\t0xBA\n#define\tEEPROM_IQK_LCK_8188GTV\t\t\t\t\t0xBB\n#define\tEEPROM_2G_5G_PA_TYPE_8188GTV\t\t\t0xBC\n#define\tEEPROM_2G_LNA_TYPE_GAIN_SEL_8188GTV\t\t0xBD\n#define\tEEPROM_5G_LNA_TYPE_GAIN_SEL_8188GTV\t\t0xBF\n\n#define\tEEPROM_RF_BOARD_OPTION_8188GTV\t\t\t0xC1\n#define\tEEPROM_FEATURE_OPTION_8188GTV\t\t\t0xC2\n#define\tEEPROM_RF_BT_SETTING_8188GTV\t\t\t0xC3\n#define\tEEPROM_VERSION_8188GTV\t\t\t\t\t0xC4\n#define\tEEPROM_CustomID_8188GTV\t\t\t\t\t0xC5\n#define\tEEPROM_TX_BBSWING_2G_8188GTV\t\t\t0xC6\n#define\tEEPROM_TX_PWR_CALIBRATE_RATE_8188GTV\t0xC8\n#define\tEEPROM_RF_ANTENNA_OPT_8188GTV\t\t\t0xC9\n#define\tEEPROM_RFE_OPTION_8188GTV\t\t\t\t0xCA\n#define EEPROM_COUNTRY_CODE_8188GTV\t\t\t\t0xCB\n#define EEPROM_CUSTOMER_ID_8188GTV\t\t\t\t0x7F\n#define EEPROM_SUBCUSTOMER_ID_8188GTV\t\t\t0x59\n\n/* RTL8188GTVU */\n#define EEPROM_MAC_ADDR_8188GTVU\t\t\t\t0xD7\n#define EEPROM_VID_8188GTVU\t\t\t\t\t\t0xD0\n#define EEPROM_PID_8188GTVU\t\t\t\t\t\t0xD2\n#define EEPROM_PA_TYPE_8188GTVU\t\t\t\t\t0xBC\n#define EEPROM_LNA_TYPE_2G_8188GTVU\t\t\t\t0xBD\n#define EEPROM_USB_OPTIONAL_FUNCTION0_8188GTVU\t0xD4\n\n/* RTL8188GTVS */\n#define\tEEPROM_MAC_ADDR_8188GTVS\t\t\t\t0x11A\n#define EEPROM_Voltage_ADDR_8188GTV\t\t\t\t0x8\n\n/* ****************************************************\n *\t\t\tEEPROM/Efuse PG Offset for 8723BE/8723BU/8723BS\n * *****************************************************/\n#define\tEEPROM_ChannelPlan_8723B\t\t\t\t0xB8\n#define\tEEPROM_XTAL_8723B\t\t\t\t\t\t0xB9\n#define\tEEPROM_THERMAL_METER_8723B\t\t\t0xBA\n#define\tEEPROM_IQK_LCK_8723B\t\t\t\t\t0xBB\n#define\tEEPROM_2G_5G_PA_TYPE_8723B\t\t\t0xBC\n#define\tEEPROM_2G_LNA_TYPE_GAIN_SEL_8723B\t0xBD\n#define\tEEPROM_5G_LNA_TYPE_GAIN_SEL_8723B\t0xBF\n\n#define\tEEPROM_RF_BOARD_OPTION_8723B\t\t0xC1\n#define\tEEPROM_FEATURE_OPTION_8723B\t\t\t0xC2\n#define\tEEPROM_RF_BT_SETTING_8723B\t\t\t0xC3\n#define\tEEPROM_VERSION_8723B\t\t\t\t\t0xC4\n#define\tEEPROM_CustomID_8723B\t\t\t\t0xC5\n#define\tEEPROM_TX_BBSWING_2G_8723B\t\t\t0xC6\n#define\tEEPROM_TX_PWR_CALIBRATE_RATE_8723B\t0xC8\n#define\tEEPROM_RF_ANTENNA_OPT_8723B\t\t0xC9\n#define\tEEPROM_RFE_OPTION_8723B\t\t\t\t0xCA\n#define EEPROM_COUNTRY_CODE_8723B\t\t\t0xCB\n\n/* RTL8723BE */\n#define EEPROM_MAC_ADDR_8723BE\t\t\t\t0xD0\n#define EEPROM_VID_8723BE\t\t\t\t\t\t0xD6\n#define EEPROM_DID_8723BE\t\t\t\t\t\t0xD8\n#define EEPROM_SVID_8723BE\t\t\t\t\t\t0xDA\n#define EEPROM_SMID_8723BE\t\t\t\t\t\t0xDC\n\n/* RTL8723BU */\n#define EEPROM_MAC_ADDR_8723BU\t\t\t\t0x107\n#define EEPROM_VID_8723BU\t\t\t\t\t\t0x100\n#define EEPROM_PID_8723BU\t\t\t\t\t\t0x102\n#define EEPROM_PA_TYPE_8723BU\t\t\t\t\t0xBC\n#define EEPROM_LNA_TYPE_2G_8723BU\t\t\t\t0xBD\n\n\n/* RTL8723BS */\n#define\tEEPROM_MAC_ADDR_8723BS\t\t\t\t0x11A\n#define EEPROM_Voltage_ADDR_8723B\t\t\t0x8\n\n/* ****************************************************\n *\t\t\tEEPROM/Efuse PG Offset for 8703B\n * **************************************************** */\n#define GET_PG_KFREE_ON_8703B(_pg_m)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)\n#define GET_PG_KFREE_THERMAL_K_ON_8703B(_pg_m)\tLE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)\n\n#define PPG_BB_GAIN_2G_TXA_OFFSET_8703B\t0xEE\n#define PPG_THERMAL_OFFSET_8703B\t\t0xEF\n\n#define\tEEPROM_ChannelPlan_8703B\t\t\t\t0xB8\n#define\tEEPROM_XTAL_8703B\t\t\t\t\t0xB9\n#define\tEEPROM_THERMAL_METER_8703B\t\t\t0xBA\n#define\tEEPROM_IQK_LCK_8703B\t\t\t\t\t0xBB\n#define\tEEPROM_2G_5G_PA_TYPE_8703B\t\t\t0xBC\n#define\tEEPROM_2G_LNA_TYPE_GAIN_SEL_8703B\t0xBD\n#define\tEEPROM_5G_LNA_TYPE_GAIN_SEL_8703B\t0xBF\n\n#define\tEEPROM_RF_BOARD_OPTION_8703B\t\t0xC1\n#define\tEEPROM_FEATURE_OPTION_8703B\t\t\t0xC2\n#define\tEEPROM_RF_BT_SETTING_8703B\t\t\t0xC3\n#define\tEEPROM_VERSION_8703B\t\t\t\t\t0xC4\n#define\tEEPROM_CustomID_8703B\t\t\t\t\t0xC5\n#define\tEEPROM_TX_BBSWING_2G_8703B\t\t\t0xC6\n#define\tEEPROM_TX_PWR_CALIBRATE_RATE_8703B\t0xC8\n#define\tEEPROM_RF_ANTENNA_OPT_8703B\t\t0xC9\n#define\tEEPROM_RFE_OPTION_8703B\t\t\t\t0xCA\n#define EEPROM_COUNTRY_CODE_8703B\t\t\t0xCB\n\n/* RTL8703BU */\n#define EEPROM_MAC_ADDR_8703BU                          0x107\n#define EEPROM_VID_8703BU                               0x100\n#define EEPROM_PID_8703BU                               0x102\n#define EEPROM_USB_OPTIONAL_FUNCTION0_8703BU            0x104\n#define EEPROM_PA_TYPE_8703BU                           0xBC\n#define EEPROM_LNA_TYPE_2G_8703BU                       0xBD\n\n/* RTL8703BS */\n#define\tEEPROM_MAC_ADDR_8703BS\t\t\t\t0x11A\n#define\tEEPROM_Voltage_ADDR_8703B\t\t\t0x8\n\n/*\n * ====================================================\n *\tEEPROM/Efuse PG Offset for 8822B\n * ====================================================\n */\n#define\tEEPROM_ChannelPlan_8822B\t\t0xB8\n#define\tEEPROM_XTAL_8822B\t\t\t0xB9\n#define\tEEPROM_THERMAL_METER_8822B\t\t0xBA\n#define\tEEPROM_IQK_LCK_8822B\t\t\t0xBB\n#define\tEEPROM_2G_5G_PA_TYPE_8822B\t\t0xBC\n/* PATH A & PATH B */\n#define\tEEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B\t0xBD\n/* PATH C & PATH D */\n#define\tEEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8822B\t0xBE\n/* PATH A & PATH B */\n#define\tEEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B\t0xBF\n/* PATH C & PATH D */\n#define\tEEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8822B\t0xC0\n\n#define\tEEPROM_RF_BOARD_OPTION_8822B\t\t0xC1\n#define\tEEPROM_FEATURE_OPTION_8822B\t\t0xC2\n#define\tEEPROM_RF_BT_SETTING_8822B\t\t0xC3\n#define\tEEPROM_VERSION_8822B\t\t\t0xC4\n#define\tEEPROM_CustomID_8822B\t\t\t0xC5\n#define\tEEPROM_TX_BBSWING_2G_8822B\t\t0xC6\n#define\tEEPROM_TX_PWR_CALIBRATE_RATE_8822B\t0xC8\n#define\tEEPROM_RF_ANTENNA_OPT_8822B\t\t0xC9\n#define\tEEPROM_RFE_OPTION_8822B\t\t\t0xCA\n#define EEPROM_COUNTRY_CODE_8822B\t\t0xCB\n\n/* RTL8822BU */\n#define EEPROM_MAC_ADDR_8822BU\t\t\t0x107\n#define EEPROM_VID_8822BU\t\t\t0x100\n#define EEPROM_PID_8822BU\t\t\t0x102\n#define EEPROM_USB_OPTIONAL_FUNCTION0_8822BU\t0x104\n#define EEPROM_USB_MODE_8822BU\t\t\t0x06\n\n/* RTL8822BS */\n#define\tEEPROM_MAC_ADDR_8822BS\t\t\t0x11A\n\n/* RTL8822BE */\n#define\tEEPROM_MAC_ADDR_8822BE\t\t\t0xD0\n/*\n * ====================================================\n *\tEEPROM/Efuse PG Offset for 8821C\n * ====================================================\n */\n#define\tEEPROM_CHANNEL_PLAN_8821C\t\t0xB8\n#define\tEEPROM_XTAL_8821C\t\t\t0xB9\n#define\tEEPROM_THERMAL_METER_8821C\t\t0xBA\n#define\tEEPROM_IQK_LCK_8821C\t\t\t0xBB\n#define\tEEPROM_2G_5G_PA_TYPE_8821C\t\t0xBC\n/* PATH A & PATH B */\n#define\tEEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8821C\t0xBD\n/* PATH C & PATH D */\n#define\tEEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8821C\t0xBE\n/* PATH A & PATH B */\n#define\tEEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8821C\t0xBF\n/* PATH C & PATH D */\n#define\tEEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8821C\t0xC0\n\n#define\tEEPROM_RF_BOARD_OPTION_8821C\t\t0xC1\n#define\tEEPROM_FEATURE_OPTION_8821C\t\t0xC2\n#define\tEEPROM_RF_BT_SETTING_8821C\t\t0xC3\n#define\tEEPROM_VERSION_8821C\t\t\t0xC4\n#define\tEEPROM_CUSTOMER_ID_8821C\t\t\t0xC5\n#define\tEEPROM_TX_BBSWING_2G_8821C\t\t0xC6\n#define\tEEPROM_TX_BBSWING_5G_8821C\t\t0xC7\n#define\tEEPROM_TX_PWR_CALIBRATE_RATE_8821C\t0xC8\n#define\tEEPROM_RF_ANTENNA_OPT_8821C\t\t0xC9\n#define\tEEPROM_RFE_OPTION_8821C\t\t\t0xCA\n#define EEPROM_COUNTRY_CODE_8821C\t\t0xCB\n\n/* RTL8821CU */\n#define EEPROM_MAC_ADDR_8821CU\t\t\t0x107\n#define EEPROM_VID_8821CU\t\t\t\t\t0x100\n#define EEPROM_PID_8821CU\t\t\t\t\t0x102\n#define EEPROM_USB_OPTIONAL_FUNCTION0_8821CU\t0x104\n#define EEPROM_USB_MODE_8821CU\t\t\t0x06\n\n/* RTL8821CS */\n#define\tEEPROM_MAC_ADDR_8821CS\t\t\t0x11A\n\n/* RTL8821CE */\n#define\tEEPROM_MAC_ADDR_8821CE\t\t\t0xD0\n/* ****************************************************\n *\tEEPROM/Efuse PG Offset for 8723D\n * **************************************************** */\n#define GET_PG_KFREE_ON_8723D(_pg_m)\t\\\n\tLE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)\n#define GET_PG_KFREE_THERMAL_K_ON_8723D(_pg_m)\t\\\n\tLE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)\n\n#define PPG_8723D_S1\t0\n#define PPG_8723D_S0\t1\n\n#define PPG_BB_GAIN_2G_TXA_OFFSET_8723D\t\t0xEE\n#define PPG_BB_GAIN_2G_TX_OFFSET_8723D\t\t0x1EE\n#define PPG_THERMAL_OFFSET_8723D\t\t0xEF\n\n#define\tEEPROM_ChannelPlan_8723D\t\t0xB8\n#define\tEEPROM_XTAL_8723D\t\t\t0xB9\n#define\tEEPROM_THERMAL_METER_8723D\t\t0xBA\n#define\tEEPROM_IQK_LCK_8723D\t\t\t0xBB\n#define\tEEPROM_2G_5G_PA_TYPE_8723D\t\t0xBC\n#define\tEEPROM_2G_LNA_TYPE_GAIN_SEL_8723D\t0xBD\n#define\tEEPROM_5G_LNA_TYPE_GAIN_SEL_8723D\t0xBF\n\n#define\tEEPROM_RF_BOARD_OPTION_8723D\t\t0xC1\n#define\tEEPROM_FEATURE_OPTION_8723D\t\t0xC2\n#define\tEEPROM_RF_BT_SETTING_8723D\t\t0xC3\n#define\tEEPROM_VERSION_8723D\t\t\t0xC4\n#define\tEEPROM_CustomID_8723D\t\t\t0xC5\n#define\tEEPROM_TX_BBSWING_2G_8723D\t\t0xC6\n#define\tEEPROM_TX_PWR_CALIBRATE_RATE_8723D\t0xC8\n#define\tEEPROM_RF_ANTENNA_OPT_8723D\t\t0xC9\n#define\tEEPROM_RFE_OPTION_8723D\t\t\t0xCA\n#define EEPROM_COUNTRY_CODE_8723D\t\t0xCB\n\n/* RTL8723DE */\n#define EEPROM_MAC_ADDR_8723DE              0xD0\n#define EEPROM_VID_8723DE                   0xD6\n#define EEPROM_DID_8723DE                   0xD8\n#define EEPROM_SVID_8723DE                  0xDA\n#define EEPROM_SMID_8723DE                  0xDC\n\n/* RTL8723DU */\n#define EEPROM_MAC_ADDR_8723DU                  0x107\n#define EEPROM_VID_8723DU                       0x100\n#define EEPROM_PID_8723DU                       0x102\n#define EEPROM_USB_OPTIONAL_FUNCTION0_8723DU    0x104\n\n/* RTL8723BS */\n#define\tEEPROM_MAC_ADDR_8723DS\t\t\t0x11A\n#define\tEEPROM_Voltage_ADDR_8723D\t\t0x8\n\n/*\n * ====================================================\n *\tEEPROM/Efuse PG Offset for 8822C\n * ====================================================\n */\n#define\tEEPROM_TX_PWR_INX_8822C\t\t\t0x10\n#define\tEEPROM_ChannelPlan_8822C\t\t0xB8\n#define\tEEPROM_XTAL_B9_8822C\t\t\t0xB9\n#define\tEEPROM_IQK_LCK_8822C\t\t\t0xBB\n#define\tEEPROM_2G_5G_PA_TYPE_8822C\t\t0xBC\n/* PATH A & PATH B */\n#define\tEEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822C\t0xBD\n/* PATH C & PATH D */\n#define\tEEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8822C\t0xBE\n/* PATH A & PATH B */\n#define\tEEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822C\t0xBF\n/* PATH C & PATH D */\n#define\tEEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8822C\t0xC0\n\n#define\tEEPROM_RF_BOARD_OPTION_8822C\t\t0xC1\n#define\tEEPROM_FEATURE_OPTION_8822C\t\t0xC2\n#define\tEEPROM_RF_BT_SETTING_8822C\t\t0xC3\n#define\tEEPROM_VERSION_8822C\t\t\t0xC4\n#define\tEEPROM_CustomID_8822C\t\t\t0xC5\n#define\tEEPROM_TX_BBSWING_2G_8822C\t\t0xC6\n#define\tEEPROM_TX_PWR_CALIBRATE_RATE_8822C\t0xC8\n#define\tEEPROM_RF_ANTENNA_OPT_8822C\t\t0xC9\n#define\tEEPROM_RFE_OPTION_8822C\t\t\t0xCA\n#define EEPROM_COUNTRY_CODE_8822C\t\t0xCB\n#define\tEEPROM_THERMAL_METER_A_8822C\t\t0xD0\n#define\tEEPROM_THERMAL_METER_B_8822C\t\t0xD1\n\n#define\tEEPROM_XTAL_110_8822C\t\t\t0x110\n#define\tEEPROM_XTAL_111_8822C\t\t\t0x111\n\n/* RTL8822CU */\n#define EEPROM_MAC_ADDR_8822CU\t\t\t0x157\n#define EEPROM_VID_8822CU\t\t\t0x100\n#define EEPROM_PID_8822CU\t\t\t0x102\n#define EEPROM_USB_OPTIONAL_FUNCTION0_8822CU\t0x104\n#define EEPROM_USB_MODE_8822CU\t\t\t0x06\n\n/* RTL8822CS */\n#define\tEEPROM_MAC_ADDR_8822CS\t\t\t0x16A\n\n/* RTL8822CE */\n#define\tEEPROM_MAC_ADDR_8822CE\t\t\t0x120\n\n/* ****************************************************\n *\tEEPROM/Efuse PG Offset for 8192F\n * **************************************************** */\n#define\tEEPROM_ChannelPlan_8192F\t\t\t0xB8\n#define\tEEPROM_XTAL_8192F\t\t\t\t\t0xB9\n#define\tEEPROM_THERMAL_METER_8192F\t\t\t0xBA\n#define\tEEPROM_IQK_LCK_8192F\t\t\t\t0xBB\n#define\tEEPROM_2G_5G_PA_TYPE_8192F\t\t\t0xBC\n#define\tEEPROM_2G_LNA_TYPE_GAIN_SEL_8192F\t0xBD\n#define\tEEPROM_5G_LNA_TYPE_GAIN_SEL_8192F\t0xBF\n\n#define\tEEPROM_RF_BOARD_OPTION_8192F\t\t0xC1\n#define\tEEPROM_FEATURE_OPTION_8192F\t\t\t0xC2\n#define\tEEPROM_RF_BT_SETTING_8192F\t\t\t0xC3\n#define\tEEPROM_VERSION_8192F\t\t\t\t0xC4\n#define\tEEPROM_CustomID_8192F\t\t\t\t0xC5\n#define\tEEPROM_TX_BBSWING_2G_8192F\t\t\t0xC6\n#define\tEEPROM_TX_BBSWING_5G_8192F\t\t\t0xC7\n#define\tEEPROM_TX_PWR_CALIBRATE_RATE_8192F\t0xC8\n#define\tEEPROM_RF_ANTENNA_OPT_8192F\t\t\t0xC9\n#define\tEEPROM_RFE_OPTION_8192F\t\t\t\t0xCA\n#define EEPROM_COUNTRY_CODE_8192F\t\t\t0xCB\n/*RTL8192FS*/\n#define\tEEPROM_MAC_ADDR_8192FS\t\t\t\t0x11A\n#define EEPROM_Voltage_ADDR_8192F\t\t\t0x8\n/* RTL8192FU */\n#define EEPROM_MAC_ADDR_8192FU\t\t\t\t\t0x107\n#define EEPROM_VID_8192FU\t\t\t\t\t\t\t0x100\n#define EEPROM_PID_8192FU\t\t\t\t\t\t\t0x102\n#define EEPROM_USB_OPTIONAL_FUNCTION0_8192FU\t0x104\n/* RTL8192FE */\n#define EEPROM_MAC_ADDR_8192FE\t\t\t\t\t0xD0\n#define EEPROM_VID_8192FE\t\t\t\t\t\t\t0xD6\n#define EEPROM_DID_8192FE\t\t\t\t\t\t\t0xD8\n#define EEPROM_SVID_8192FE\t\t\t\t\t\t\t0xDA\n#define EEPROM_SMID_8192FE\t\t\t\t\t\t0xDC\n\n/* ****************************************************\n *\tEEPROM/Efuse PG Offset for 8710B\n * **************************************************** */\n#define RTL_EEPROM_ID_8710B \t\t\t\t\t0x8195\n#define EEPROM_Default_ThermalMeter_8710B\t\t0x1A\n\n#define\tEEPROM_CHANNEL_PLAN_8710B\t\t\t0xC8\n#define\tEEPROM_XTAL_8710B\t\t\t\t\t0xC9\n#define\tEEPROM_THERMAL_METER_8710B\t\t\t0xCA\n#define\tEEPROM_IQK_LCK_8710B\t\t\t\t\t0xCB\n#define\tEEPROM_2G_5G_PA_TYPE_8710B\t\t\t0xCC\n#define\tEEPROM_2G_LNA_TYPE_GAIN_SEL_8710B\t0xCD\n#define\tEEPROM_5G_LNA_TYPE_GAIN_SEL_8710B\t0xCF\n#define \tEEPROM_TX_KFREE_8710B\t\t\t\t0xEE    //Physical  Efuse Address\n#define \tEEPROM_THERMAL_8710B\t\t\t\t0xEF    //Physical  Efuse Address\n#define \tEEPROM_PACKAGE_TYPE_8710B\t\t\t0xF8    //Physical  Efuse Address\n\n#define EEPROM_RF_BOARD_OPTION_8710B\t\t0x131\n#define EEPROM_RF_FEATURE_OPTION_8710B\t\t0x132\n#define EEPROM_RF_BT_SETTING_8710B\t\t\t0x133\n#define EEPROM_VERSION_8710B\t\t\t\t\t0x134\n#define EEPROM_CUSTOM_ID_8710B\t\t\t\t0x135\n#define EEPROM_TX_BBSWING_2G_8710B\t\t\t0x136\n#define EEPROM_TX_BBSWING_5G_8710B\t\t\t0x137\n#define EEPROM_TX_PWR_CALIBRATE_RATE_8710B\t0x138\n#define EEPROM_RF_ANTENNA_OPT_8710B\t\t\t0x139\n#define EEPROM_RFE_OPTION_8710B\t\t\t\t0x13A\n#define EEPROM_COUNTRY_CODE_8710B\t\t\t0x13B\n#define EEPROM_COUNTRY_CODE_2_8710B\t\t\t0x13C\n\n#define EEPROM_MAC_ADDR_8710B \t\t\t\t0x11A\n#define EEPROM_VID_8710BU\t\t\t\t\t\t0x1C0\n#define EEPROM_PID_8710BU\t\t\t\t\t\t0x1C2\n\n/* ****************************************************\n *\t\t\tEEPROM/Efuse Value Type\n * **************************************************** */\n#define EETYPE_TX_PWR\t\t\t\t\t\t\t0x0\n#define EETYPE_MAX_RFE_8192F\t\t\t\t\t0x31\n/* ****************************************************\n *\t\t\tEEPROM/Efuse Default Value\n * **************************************************** */\n#define EEPROM_CID_DEFAULT\t\t\t\t\t0x0\n#define EEPROM_CID_DEFAULT_EXT\t\t\t\t0xFF /* Reserved for Realtek */\n#define EEPROM_CID_TOSHIBA\t\t\t\t\t\t0x4\n#define EEPROM_CID_CCX\t\t\t\t\t\t\t0x10\n#define EEPROM_CID_QMI\t\t\t\t\t\t\t0x0D\n#define EEPROM_CID_WHQL\t\t\t\t\t\t0xFE\n\n#define EEPROM_CHANNEL_PLAN_FCC\t\t\t\t0x0\n#define EEPROM_CHANNEL_PLAN_IC\t\t\t\t0x1\n#define EEPROM_CHANNEL_PLAN_ETSI\t\t\t\t0x2\n#define EEPROM_CHANNEL_PLAN_SPAIN\t\t\t0x3\n#define EEPROM_CHANNEL_PLAN_FRANCE\t\t\t0x4\n#define EEPROM_CHANNEL_PLAN_MKK\t\t\t\t0x5\n#define EEPROM_CHANNEL_PLAN_MKK1\t\t\t\t0x6\n#define EEPROM_CHANNEL_PLAN_ISRAEL\t\t\t0x7\n#define EEPROM_CHANNEL_PLAN_TELEC\t\t\t0x8\n#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN\t0x9\n#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13\t0xA\n#define EEPROM_CHANNEL_PLAN_NCC_TAIWAN\t\t0xB\n#define EEPROM_CHANNEL_PLAN_CHIAN\t\t\t0XC\n#define EEPROM_CHANNEL_PLAN_SINGAPORE_INDIA_MEXICO  0XD\n#define EEPROM_CHANNEL_PLAN_KOREA\t\t\t0xE\n#define EEPROM_CHANNEL_PLAN_TURKEY\t0xF\n#define EEPROM_CHANNEL_PLAN_JAPAN\t0x10\n#define EEPROM_CHANNEL_PLAN_FCC_NO_DFS\t\t0x11\n#define EEPROM_CHANNEL_PLAN_JAPAN_NO_DFS\t0x12\n#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_5G\t0x13\n#define EEPROM_CHANNEL_PLAN_TAIWAN_NO_DFS\t0x14\n\n#define EEPROM_USB_OPTIONAL1\t\t\t\t\t0xE\n#define EEPROM_CHANNEL_PLAN_BY_HW_MASK\t\t0x80\n\n#define RTL_EEPROM_ID\t\t\t\t\t\t\t0x8129\n#define EEPROM_Default_TSSI\t\t\t\t\t\t0x0\n#define EEPROM_Default_BoardType\t\t\t\t0x02\n#define EEPROM_Default_ThermalMeter\t\t\t0x12\n#define EEPROM_Default_ThermalMeter_92SU\t\t0x7\n#define EEPROM_Default_ThermalMeter_88E\t\t0x18\n#define EEPROM_Default_ThermalMeter_8812\t\t0x18\n#define\tEEPROM_Default_ThermalMeter_8192E\t\t\t0x1A\n#define\tEEPROM_Default_ThermalMeter_8723B\t\t0x18\n#define\tEEPROM_Default_ThermalMeter_8703B\t\t0x18\n#define\tEEPROM_Default_ThermalMeter_8723D\t\t0x18\n#define\tEEPROM_Default_ThermalMeter_8188F\t\t0x18\n#define\tEEPROM_Default_ThermalMeter_8188GTV\t\t0x18\n#define EEPROM_Default_ThermalMeter_8814A\t\t0x18\n#define\tEEPROM_Default_ThermalMeter_8192F\t\t0x1A\n\n#define EEPROM_Default_CrystalCap\t\t\t\t0x0\n#define EEPROM_Default_CrystalCap_8723A\t\t0x20\n#define EEPROM_Default_CrystalCap_88E\t\t\t0x20\n#define EEPROM_Default_CrystalCap_8812\t\t\t0x20\n#define EEPROM_Default_CrystalCap_8814\t\t\t0x20\n#define EEPROM_Default_CrystalCap_8192E\t\t\t0x20\n#define EEPROM_Default_CrystalCap_8723B\t\t\t0x20\n#define EEPROM_Default_CrystalCap_8703B\t\t\t0x20\n#define EEPROM_Default_CrystalCap_8723D\t\t\t0x20\n#define EEPROM_Default_CrystalCap_8188F\t\t\t0x20\n#define EEPROM_Default_CrystalCap_8188GTV\t\t0x20\n#define EEPROM_Default_CrystalCap_8192F\t\t\t0x20\n#define EEPROM_Default_CrystalCap_B9_8822C\t\t0x3F\n#define EEPROM_Default_CrystalCap_110_8822C\t\t0x40\n#define EEPROM_Default_CrystalCap_111_8822C\t\t0x40\n#define EEPROM_Default_CrystalFreq\t\t\t\t0x0\n#define EEPROM_Default_TxPowerLevel_92C\t\t0x22\n#define EEPROM_Default_TxPowerLevel_2G\t\t\t0x2C\n#define EEPROM_Default_TxPowerLevel_5G\t\t\t0x22\n#define EEPROM_Default_TxPowerLevel\t\t\t0x22\n#define EEPROM_Default_HT40_2SDiff\t\t\t\t0x0\n#define EEPROM_Default_HT20_Diff\t\t\t\t2\n#define EEPROM_Default_LegacyHTTxPowerDiff\t\t0x3\n#define EEPROM_Default_LegacyHTTxPowerDiff_92C\t0x3\n#define EEPROM_Default_LegacyHTTxPowerDiff_92D\t0x4\n#define EEPROM_Default_HT40_PwrMaxOffset\t\t0\n#define EEPROM_Default_HT20_PwrMaxOffset\t\t0\n\n#define EEPROM_Default_PID\t\t\t\t\t\t0x1234\n#define EEPROM_Default_VID\t\t\t\t\t\t0x5678\n#define EEPROM_Default_CustomerID\t\t\t\t0xAB\n#define EEPROM_Default_CustomerID_8188E\t\t0x00\n#define EEPROM_Default_SubCustomerID\t\t\t0xCD\n#define EEPROM_Default_Version\t\t\t\t\t0\n\n#define EEPROM_Default_externalPA_C9\t\t0x00\n#define EEPROM_Default_externalPA_CC\t\t0xFF\n#define EEPROM_Default_internalPA_SP3T_C9\t0xAA\n#define EEPROM_Default_internalPA_SP3T_CC\t0xAF\n#define EEPROM_Default_internalPA_SPDT_C9\t0xAA\n#ifdef CONFIG_PCI_HCI\n\t#define EEPROM_Default_internalPA_SPDT_CC\t0xA0\n#else\n\t#define EEPROM_Default_internalPA_SPDT_CC\t0xFA\n#endif\n#define EEPROM_Default_PAType\t\t\t\t\t\t0\n#define EEPROM_Default_LNAType\t\t\t\t\t\t0\n\n/* New EFUSE default value */\n#define EEPROM_DEFAULT_CHANNEL_PLAN\t\t0x7F\n#define EEPROM_DEFAULT_BOARD_OPTION\t\t0x00\n#define EEPROM_DEFAULT_RFE_OPTION_8192E 0xFF\n#define EEPROM_DEFAULT_RFE_OPTION_8188E 0xFF\n#define EEPROM_DEFAULT_RFE_OPTION\t\t0x04\n#define EEPROM_DEFAULT_FEATURE_OPTION\t0x00\n#define EEPROM_DEFAULT_BT_OPTION\t\t\t0x10\n\n\n#define EEPROM_DEFAULT_TX_CALIBRATE_RATE\t0x00\n\n/* PCIe related */\n#define\tEEPROM_PCIE_DEV_CAP_01\t\t\t\t0xE0 /* Express device capability in PCIe configuration space, i.e., map to offset 0x74 */\n#define\tEEPROM_PCIE_DEV_CAP_02\t\t\t\t0xE1 /* Express device capability in PCIe configuration space, i.e., map to offset 0x75 */\n\n\n/*\n * For VHT series TX power by rate table.\n * VHT TX power by rate off setArray =\n * Band:-2G&5G = 0 / 1\n * RF: at most 4*4 = ABCD=0/1/2/3\n * CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11\n *   */\n#define TX_PWR_BY_RATE_NUM_BAND\t\t\t2\n#define TX_PWR_BY_RATE_NUM_RF\t\t\t4\n#define TX_PWR_BY_RATE_NUM_RATE\t\t\t84\n\n#define TXPWR_LMT_MAX_RF\t\t\t\t4\n\n/* ----------------------------------------------------------------------------\n * EEPROM/EFUSE data structure definition.\n * ---------------------------------------------------------------------------- */\n\n/* For 88E new structure */\n\n/*\n2.4G:\n{\n{1,2},\n{3,4,5},\n{6,7,8},\n{9,10,11},\n{12,13},\n{14}\n}\n\n5G:\n{\n{36,38,40},\n{44,46,48},\n{52,54,56},\n{60,62,64},\n{100,102,104},\n{108,110,112},\n{116,118,120},\n{124,126,128},\n{132,134,136},\n{140,142,144},\n{149,151,153},\n{157,159,161},\n{173,175,177},\n}\n*/\n#define\tMAX_RF_PATH\t\t\t\t4\n#define RF_PATH_MAX\t\t\t\tMAX_RF_PATH\n#define\tMAX_CHNL_GROUP_24G\t\t6\n#define\tMAX_CHNL_GROUP_5G\t\t14\n\n/* It must always set to 4, otherwise read efuse table sequence will be wrong. */\n#define\tMAX_TX_COUNT\t\t\t\t4\n\ntypedef struct _TxPowerInfo24G {\n\tu8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];\n\tu8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];\n\t/* If only one tx, only BW20 and OFDM are used. */\n\ts8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];\n\ts8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];\n\ts8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];\n\ts8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];\n} TxPowerInfo24G, *PTxPowerInfo24G;\n\ntypedef struct _TxPowerInfo5G {\n\tu8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];\n\t/* If only one tx, only BW20, OFDM, BW80 and BW160 are used. */\n\ts8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];\n\ts8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];\n\ts8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];\n\ts8 BW80_Diff[MAX_RF_PATH][MAX_TX_COUNT];\n\ts8 BW160_Diff[MAX_RF_PATH][MAX_TX_COUNT];\n} TxPowerInfo5G, *PTxPowerInfo5G;\n\n\ntypedef\tenum _BT_Ant_NUM {\n\tAnt_x2\t= 0,\n\tAnt_x1\t= 1\n} BT_Ant_NUM, *PBT_Ant_NUM;\n\ntypedef\tenum _BT_CoType {\n\tBT_2WIRE\t\t= 0,\n\tBT_ISSC_3WIRE\t= 1,\n\tBT_ACCEL\t\t= 2,\n\tBT_CSR_BC4\t\t= 3,\n\tBT_CSR_BC8\t\t= 4,\n\tBT_RTL8756\t\t= 5,\n\tBT_RTL8723A\t\t= 6,\n\tBT_RTL8821\t\t= 7,\n\tBT_RTL8723B\t\t= 8,\n\tBT_RTL8192E\t\t= 9,\n\tBT_RTL8814A\t\t= 10,\n\tBT_RTL8812A\t\t= 11,\n\tBT_RTL8703B\t\t= 12,\n\tBT_RTL8822B\t\t= 13,\n\tBT_RTL8723D\t\t= 14,\n\tBT_RTL8821C\t\t= 15,\n\tBT_RTL8192F\t\t= 16,\n\tBT_RTL8822C\t\t= 17\t\n} BT_CoType, *PBT_CoType;\n\ntypedef\tenum _BT_RadioShared {\n\tBT_Radio_Shared\t= 0,\n\tBT_Radio_Individual\t= 1,\n} BT_RadioShared, *PBT_RadioShared;\n\n\n#endif\n"
  },
  {
    "path": "include/hal_phy.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HAL_PHY_H__\n#define __HAL_PHY_H__\n\n\n#if DISABLE_BB_RF\n\t#define\tHAL_FW_ENABLE\t\t\t\t0\n\t#define\tHAL_MAC_ENABLE\t\t\t0\n\t#define\tHAL_BB_ENABLE\t\t\t\t0\n\t#define\tHAL_RF_ENABLE\t\t\t\t0\n#else /* FPGA_PHY and ASIC */\n\t#define\tHAL_FW_ENABLE\t\t\t\t1\n\t#define\tHAL_MAC_ENABLE\t\t\t1\n\t#define\tHAL_BB_ENABLE\t\t\t\t1\n\t#define\tHAL_RF_ENABLE\t\t\t\t1\n#endif\n\n#define\tRF6052_MAX_TX_PWR\t\t\t0x3F\n#define\tRF6052_MAX_REG_88E\t\t\t0xFF\n#define\tRF6052_MAX_REG_92C\t\t\t0x7F\n\n#define\tRF6052_MAX_REG\t\\\n\t((RF6052_MAX_REG_88E > RF6052_MAX_REG_92C) ? RF6052_MAX_REG_88E : RF6052_MAX_REG_92C)\n\n#define GET_RF6052_REAL_MAX_REG(_Adapter)\t\\\n\t(IS_HARDWARE_TYPE_8188E(_Adapter) ? RF6052_MAX_REG_88E : RF6052_MAX_REG_92C)\n\n#define\tRF6052_MAX_PATH\t\t\t\t2\n\n/*\n * Antenna detection method, i.e., using single tone detection or RSSI reported from each antenna detected.\n * Added by Roger, 2013.05.22.\n *   */\n#define ANT_DETECT_BY_SINGLE_TONE\tBIT0\n#define ANT_DETECT_BY_RSSI\t\t\t\tBIT1\n#define IS_ANT_DETECT_SUPPORT_SINGLE_TONE(__Adapter)\t\t((GET_HAL_DATA(__Adapter)->AntDetection) & ANT_DETECT_BY_SINGLE_TONE)\n#define IS_ANT_DETECT_SUPPORT_RSSI(__Adapter)\t\t((GET_HAL_DATA(__Adapter)->AntDetection) & ANT_DETECT_BY_RSSI)\n\n\n/*--------------------------Define Parameters-------------------------------*/\ntypedef\tenum _RF_CHIP {\n\tRF_CHIP_MIN = 0,\t/* 0 */\n\tRF_8225 = 1,\t\t\t/* 1 11b/g RF for verification only */\n\tRF_8256 = 2,\t\t\t/* 2 11b/g/n */\n\tRF_8258 = 3,\t\t\t/* 3 11a/b/g/n RF */\n\tRF_6052 = 4,\t\t\t/* 4 11b/g/n RF */\n\tRF_PSEUDO_11N = 5,\t/* 5, It is a temporality RF. */\n\tRF_CHIP_MAX\n} RF_CHIP_E, *PRF_CHIP_E;\n\ntypedef enum _ANTENNA_PATH {\n\tANTENNA_NONE\t= 0,\n\tANTENNA_D\t\t= 1,\n\tANTENNA_C\t\t= 2,\n\tANTENNA_CD\t= 3,\n\tANTENNA_B\t\t= 4,\n\tANTENNA_BD\t= 5,\n\tANTENNA_BC\t= 6,\n\tANTENNA_BCD\t= 7,\n\tANTENNA_A\t\t= 8,\n\tANTENNA_AD\t= 9,\n\tANTENNA_AC\t= 10,\n\tANTENNA_ACD\t= 11,\n\tANTENNA_AB\t= 12,\n\tANTENNA_ABD\t= 13,\n\tANTENNA_ABC\t= 14,\n\tANTENNA_ABCD\t= 15\n} ANTENNA_PATH;\n\ntypedef enum _RF_CONTENT {\n\tradioa_txt = 0x1000,\n\tradiob_txt = 0x1001,\n\tradioc_txt = 0x1002,\n\tradiod_txt = 0x1003\n} RF_CONTENT;\n\ntypedef enum _BaseBand_Config_Type {\n\tBaseBand_Config_PHY_REG = 0,\t\t\t/* Radio Path A */\n\tBaseBand_Config_AGC_TAB = 1,\t\t\t/* Radio Path B */\n\tBaseBand_Config_AGC_TAB_2G = 2,\n\tBaseBand_Config_AGC_TAB_5G = 3,\n\tBaseBand_Config_PHY_REG_PG\n} BaseBand_Config_Type, *PBaseBand_Config_Type;\n\ntypedef enum _HW_BLOCK {\n\tHW_BLOCK_MAC = 0,\n\tHW_BLOCK_PHY0 = 1,\n\tHW_BLOCK_PHY1 = 2,\n\tHW_BLOCK_RF = 3,\n\tHW_BLOCK_MAXIMUM = 4, /* Never use this */\n} HW_BLOCK_E, *PHW_BLOCK_E;\n\ntypedef enum _WIRELESS_MODE {\n\tWIRELESS_MODE_UNKNOWN = 0x00,\n\tWIRELESS_MODE_A = 0x01,\n\tWIRELESS_MODE_B = 0x02,\n\tWIRELESS_MODE_G = 0x04,\n\tWIRELESS_MODE_AUTO = 0x08,\n\tWIRELESS_MODE_N_24G = 0x10,\n\tWIRELESS_MODE_N_5G = 0x20,\n\tWIRELESS_MODE_AC_5G = 0x40,\n\tWIRELESS_MODE_AC_24G  = 0x80,\n\tWIRELESS_MODE_AC_ONLY  = 0x100,\n} WIRELESS_MODE;\n\ntypedef enum _SwChnlCmdID {\n\tCmdID_End,\n\tCmdID_SetTxPowerLevel,\n\tCmdID_BBRegWrite10,\n\tCmdID_WritePortUlong,\n\tCmdID_WritePortUshort,\n\tCmdID_WritePortUchar,\n\tCmdID_RF_WriteReg,\n} SwChnlCmdID;\n\ntypedef struct _SwChnlCmd {\n\tSwChnlCmdID\tCmdID;\n\tu32\t\t\t\tPara1;\n\tu32\t\t\t\tPara2;\n\tu32\t\t\t\tmsDelay;\n} SwChnlCmd;\n\ntypedef struct _R_ANTENNA_SELECT_OFDM {\n\tu32\t\t\tr_tx_antenna:4;\n\tu32\t\t\tr_ant_l:4;\n\tu32\t\t\tr_ant_non_ht:4;\n\tu32\t\t\tr_ant_ht1:4;\n\tu32\t\t\tr_ant_ht2:4;\n\tu32\t\t\tr_ant_ht_s1:4;\n\tu32\t\t\tr_ant_non_ht_s1:4;\n\tu32\t\t\tOFDM_TXSC:2;\n\tu32\t\t\tReserved:2;\n} R_ANTENNA_SELECT_OFDM;\n\ntypedef struct _R_ANTENNA_SELECT_CCK {\n\tu8\t\t\tr_cckrx_enable_2:2;\n\tu8\t\t\tr_cckrx_enable:2;\n\tu8\t\t\tr_ccktx_enable:4;\n} R_ANTENNA_SELECT_CCK;\n\n\n/*--------------------------Exported Function prototype---------------------*/\nu32\nPHY_CalculateBitShift(\n\tu32 BitMask\n);\n\n#ifdef CONFIG_RF_SHADOW_RW\ntypedef struct RF_Shadow_Compare_Map {\n\t/* Shadow register value */\n\tu32\t\tValue;\n\t/* Compare or not flag */\n\tu8\t\tCompare;\n\t/* Record If it had ever modified unpredicted */\n\tu8\t\tErrorOrNot;\n\t/* Recorver Flag */\n\tu8\t\tRecorver;\n\t/*  */\n\tu8\t\tDriver_Write;\n} RF_SHADOW_T;\n\nu32\nPHY_RFShadowRead(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tOffset);\n\nvoid\nPHY_RFShadowWrite(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tOffset,\n\t\tu32\t\t\t\tData);\n\nBOOLEAN\nPHY_RFShadowCompare(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tOffset);\n\nvoid\nPHY_RFShadowRecorver(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tOffset);\n\nvoid\nPHY_RFShadowCompareAll(\n\t\tPADAPTER\t\tAdapter);\n\nvoid\nPHY_RFShadowRecorverAll(\n\t\tPADAPTER\t\tAdapter);\n\nvoid\nPHY_RFShadowCompareFlagSet(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tOffset,\n\t\tu8\t\t\t\tType);\n\nvoid\nPHY_RFShadowRecorverFlagSet(\n\t\tPADAPTER\t\tAdapter,\n\t\tenum rf_path\t\teRFPath,\n\t\tu32\t\t\t\tOffset,\n\t\tu8\t\t\t\tType);\n\nvoid\nPHY_RFShadowCompareFlagSetAll(\n\t\tPADAPTER\t\tAdapter);\n\nvoid\nPHY_RFShadowRecorverFlagSetAll(\n\t\tPADAPTER\t\tAdapter);\n\nvoid\nPHY_RFShadowRefresh(\n\t\tPADAPTER\t\tAdapter);\n#endif /*#CONFIG_RF_SHADOW_RW*/\n#endif /* __HAL_COMMON_H__ */\n"
  },
  {
    "path": "include/hal_phy_reg.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HAL_PHY_REG_H__\n#define __HAL_PHY_REG_H__\n\n/* for PutRFRegsetting & GetRFRegSetting BitMask*/\n#define\t\tbRFRegOffsetMask\t0xfffff\n\n/* alias for phydm coding style */\n#define REG_OFDM_0_XA_TX_IQ_IMBALANCE\trOFDM0_XATxIQImbalance\n#define REG_OFDM_0_ECCA_THRESHOLD\t\trOFDM0_ECCAThreshold\n#define REG_FPGA0_XB_LSSI_READ_BACK\t\trFPGA0_XB_LSSIReadBack\n#define REG_FPGA0_TX_GAIN_STAGE\t\t\trFPGA0_TxGainStage\n#define REG_OFDM_0_XA_AGC_CORE1\t\t\trOFDM0_XAAGCCore1\n#define REG_OFDM_0_XB_AGC_CORE1\t\t\trOFDM0_XBAGCCore1\n#define REG_A_TX_SCALE_JAGUAR\t\t\trA_TxScale_Jaguar\n#define REG_B_TX_SCALE_JAGUAR\t\t\trB_TxScale_Jaguar\n\n#define REG_FPGA0_XAB_RF_INTERFACE_SW\trFPGA0_XAB_RFInterfaceSW\n#define REG_FPGA0_XAB_RF_PARAMETER\trFPGA0_XAB_RFParameter\n#define REG_FPGA0_XA_HSSI_PARAMETER1\trFPGA0_XA_HSSIParameter1\n#define REG_FPGA0_XA_LSSI_PARAMETER\trFPGA0_XA_LSSIParameter\n#define REG_FPGA0_XA_RF_INTERFACE_OE\trFPGA0_XA_RFInterfaceOE\n#define REG_FPGA0_XB_HSSI_PARAMETER1\trFPGA0_XB_HSSIParameter1\n#define REG_FPGA0_XB_LSSI_PARAMETER\trFPGA0_XB_LSSIParameter\n#define REG_FPGA0_XB_LSSI_READ_BACK\trFPGA0_XB_LSSIReadBack\n#define REG_FPGA0_XB_RF_INTERFACE_OE\trFPGA0_XB_RFInterfaceOE\n#define REG_FPGA0_XCD_RF_INTERFACE_SW\trFPGA0_XCD_RFInterfaceSW\n#define REG_FPGA0_XCD_SWITCH_CONTROL\trFPGA0_XCD_SwitchControl\n#define REG_FPGA1_TX_BLOCK\trFPGA1_TxBlock\n#define REG_FPGA1_TX_INFO\trFPGA1_TxInfo\n#define REG_IQK_AGC_CONT\trIQK_AGC_Cont\n#define REG_IQK_AGC_PTS\trIQK_AGC_Pts\n#define REG_IQK_AGC_RSP\trIQK_AGC_Rsp\n#define REG_OFDM_0_AGC_RSSI_TABLE\trOFDM0_AGCRSSITable\n#define REG_OFDM_0_ECCA_THRESHOLD\trOFDM0_ECCAThreshold\n#define REG_OFDM_0_RX_IQ_EXT_ANTA\trOFDM0_RxIQExtAnta\n#define REG_OFDM_0_TR_MUX_PAR\trOFDM0_TRMuxPar\n#define REG_OFDM_0_TRX_PATH_ENABLE\trOFDM0_TRxPathEnable\n#define REG_OFDM_0_XA_AGC_CORE1\trOFDM0_XAAGCCore1\n#define REG_OFDM_0_XA_RX_IQ_IMBALANCE\trOFDM0_XARxIQImbalance\n#define REG_OFDM_0_XA_TX_IQ_IMBALANCE\trOFDM0_XATxIQImbalance\n#define REG_OFDM_0_XB_AGC_CORE1\trOFDM0_XBAGCCore1\n#define REG_OFDM_0_XB_RX_IQ_IMBALANCE\trOFDM0_XBRxIQImbalance\n#define REG_OFDM_0_XB_TX_IQ_IMBALANCE\trOFDM0_XBTxIQImbalance\n#define REG_OFDM_0_XC_TX_AFE\trOFDM0_XCTxAFE\n#define REG_OFDM_0_XD_TX_AFE\trOFDM0_XDTxAFE\n\n/*#define REG_A_CFO_LONG_DUMP_92E\trA_CfoLongDump_92E*/\n#define REG_A_CFO_LONG_DUMP_JAGUAR\trA_CfoLongDump_Jaguar\n/*#define REG_A_CFO_SHORT_DUMP_92E\trA_CfoShortDump_92E*/\n#define REG_A_CFO_SHORT_DUMP_JAGUAR\trA_CfoShortDump_Jaguar\n#define REG_A_RFE_PINMUX_JAGUAR\trA_RFE_Pinmux_Jaguar\n/*#define REG_A_RSSI_DUMP_92E\trA_RSSIDump_92E*/\n#define REG_A_RSSI_DUMP_JAGUAR\trA_RSSIDump_Jaguar\n/*#define REG_A_RX_SNR_DUMP_92E\trA_RXsnrDump_92E*/\n#define REG_A_RX_SNR_DUMP_JAGUAR\trA_RXsnrDump_Jaguar\n/*#define REG_A_TX_AGC\trA_TXAGC*/\n#define REG_A_TX_SCALE_JAGUAR\trA_TxScale_Jaguar\n#define REG_BW_INDICATION_JAGUAR\trBWIndication_Jaguar\n/*#define REG_B_BBSWING\trB_BBSWING*/\n/*#define REG_B_CFO_LONG_DUMP_92E\trB_CfoLongDump_92E*/\n#define REG_B_CFO_LONG_DUMP_JAGUAR\trB_CfoLongDump_Jaguar\n/*#define REG_B_CFO_SHORT_DUMP_92E\trB_CfoShortDump_92E*/\n#define REG_B_CFO_SHORT_DUMP_JAGUAR\trB_CfoShortDump_Jaguar\n/*#define REG_B_RSSI_DUMP_92E\trB_RSSIDump_92E*/\n#define REG_B_RSSI_DUMP_JAGUAR\trB_RSSIDump_Jaguar\n/*#define REG_B_RX_SNR_DUMP_92E\trB_RXsnrDump_92E*/\n#define REG_B_RX_SNR_DUMP_JAGUAR\trB_RXsnrDump_Jaguar\n/*#define REG_B_TX_AGC\trB_TXAGC*/\n#define REG_B_TX_SCALE_JAGUAR\trB_TxScale_Jaguar\n#define REG_BLUE_TOOTH\trBlue_Tooth\n#define REG_CCK_0_AFE_SETTING\trCCK0_AFESetting\n/*#define REG_C_BBSWING\trC_BBSWING*/\n/*#define REG_C_TX_AGC\trC_TXAGC*/\n#define REG_C_TX_SCALE_JAGUAR2\trC_TxScale_Jaguar2\n#define REG_CONFIG_ANT_A\trConfig_AntA\n#define REG_CONFIG_ANT_B\trConfig_AntB\n#define REG_CONFIG_PMPD_ANT_A\trConfig_Pmpd_AntA\n#define REG_CONFIG_PMPD_ANT_B\trConfig_Pmpd_AntB\n#define REG_DPDT_CONTROL\trDPDT_control\n/*#define REG_D_BBSWING\trD_BBSWING*/\n/*#define REG_D_TX_AGC\trD_TXAGC*/\n#define REG_D_TX_SCALE_JAGUAR2\trD_TxScale_Jaguar2\n#define REG_FPGA0_ANALOG_PARAMETER4\trFPGA0_AnalogParameter4\n#define REG_FPGA0_IQK\trFPGA0_IQK\n#define REG_FPGA0_PSD_FUNCTION\trFPGA0_PSDFunction\n#define REG_FPGA0_PSD_REPORT\trFPGA0_PSDReport\n#define REG_FPGA0_RFMOD\trFPGA0_RFMOD\n#define REG_FPGA0_TX_GAIN_STAGE\trFPGA0_TxGainStage\n#define REG_FPGA0_XAB_RF_INTERFACE_SW\trFPGA0_XAB_RFInterfaceSW\n#define REG_FPGA0_XAB_RF_PARAMETER\trFPGA0_XAB_RFParameter\n#define REG_FPGA0_XA_HSSI_PARAMETER1\trFPGA0_XA_HSSIParameter1\n#define REG_FPGA0_XA_LSSI_PARAMETER\trFPGA0_XA_LSSIParameter\n#define REG_FPGA0_XA_RF_INTERFACE_OE\trFPGA0_XA_RFInterfaceOE\n#define REG_FPGA0_XB_HSSI_PARAMETER1\trFPGA0_XB_HSSIParameter1\n#define REG_FPGA0_XB_LSSI_PARAMETER\trFPGA0_XB_LSSIParameter\n#define REG_FPGA0_XB_LSSI_READ_BACK\trFPGA0_XB_LSSIReadBack\n#define REG_FPGA0_XB_RF_INTERFACE_OE\trFPGA0_XB_RFInterfaceOE\n#define REG_FPGA0_XCD_RF_INTERFACE_SW\trFPGA0_XCD_RFInterfaceSW\n#define REG_FPGA0_XCD_SWITCH_CONTROL\trFPGA0_XCD_SwitchControl\n#define REG_FPGA1_TX_BLOCK\trFPGA1_TxBlock\n#define REG_FPGA1_TX_INFO\trFPGA1_TxInfo\n#define REG_IQK_AGC_CONT\trIQK_AGC_Cont\n#define REG_IQK_AGC_PTS\trIQK_AGC_Pts\n#define REG_IQK_AGC_RSP\trIQK_AGC_Rsp\n#define REG_OFDM_0_AGC_RSSI_TABLE\trOFDM0_AGCRSSITable\n#define REG_OFDM_0_ECCA_THRESHOLD\trOFDM0_ECCAThreshold\n#define REG_OFDM_0_RX_IQ_EXT_ANTA\trOFDM0_RxIQExtAnta\n#define REG_OFDM_0_TR_MUX_PAR\trOFDM0_TRMuxPar\n#define REG_OFDM_0_TRX_PATH_ENABLE\trOFDM0_TRxPathEnable\n#define REG_OFDM_0_XA_AGC_CORE1\trOFDM0_XAAGCCore1\n#define REG_OFDM_0_XA_RX_IQ_IMBALANCE\trOFDM0_XARxIQImbalance\n#define REG_OFDM_0_XA_TX_IQ_IMBALANCE\trOFDM0_XATxIQImbalance\n#define REG_OFDM_0_XB_AGC_CORE1\trOFDM0_XBAGCCore1\n#define REG_OFDM_0_XB_RX_IQ_IMBALANCE\trOFDM0_XBRxIQImbalance\n#define REG_OFDM_0_XB_TX_IQ_IMBALANCE\trOFDM0_XBTxIQImbalance\n#define REG_OFDM_0_XC_TX_AFE\trOFDM0_XCTxAFE\n#define REG_OFDM_0_XD_TX_AFE\trOFDM0_XDTxAFE\n#define REG_PMPD_ANAEN\trPMPD_ANAEN\n#define REG_PDP_ANT_A\trPdp_AntA\n#define REG_PDP_ANT_A_4\trPdp_AntA_4\n#define REG_PDP_ANT_B\trPdp_AntB\n#define REG_PDP_ANT_B_4\trPdp_AntB_4\n#define REG_PWED_TH_JAGUAR\trPwed_TH_Jaguar\n#define REG_RX_CCK\trRx_CCK\n#define REG_RX_IQK\trRx_IQK\n#define REG_RX_IQK_PI_A\trRx_IQK_PI_A\n#define REG_RX_IQK_PI_B\trRx_IQK_PI_B\n#define REG_RX_IQK_TONE_A\trRx_IQK_Tone_A\n#define REG_RX_IQK_TONE_B\trRx_IQK_Tone_B\n#define REG_RX_OFDM\trRx_OFDM\n#define REG_RX_POWER_AFTER_IQK_A_2\trRx_Power_After_IQK_A_2\n#define REG_RX_POWER_AFTER_IQK_B_2\trRx_Power_After_IQK_B_2\n#define REG_RX_POWER_BEFORE_IQK_A_2\trRx_Power_Before_IQK_A_2\n#define REG_RX_POWER_BEFORE_IQK_B_2\trRx_Power_Before_IQK_B_2\n#define REG_RX_TO_RX\trRx_TO_Rx\n#define REG_RX_WAIT_CCA\trRx_Wait_CCA\n#define REG_RX_WAIT_RIFS\trRx_Wait_RIFS\n#define REG_S0_S1_PATH_SWITCH\trS0S1_PathSwitch\n/*#define REG_S1_RXEVM_DUMP_92E\trS1_RXevmDump_92E*/\n#define REG_S1_RXEVM_DUMP_JAGUAR\trS1_RXevmDump_Jaguar\n/*#define REG_S2_RXEVM_DUMP_92E\trS2_RXevmDump_92E*/\n#define REG_S2_RXEVM_DUMP_JAGUAR\trS2_RXevmDump_Jaguar\n#define REG_SYM_WLBT_PAPE_SEL\trSYM_WLBT_PAPE_SEL\n#define REG_SINGLE_TONE_CONT_TX_JAGUAR\trSingleTone_ContTx_Jaguar\n#define REG_SLEEP\trSleep\n#define REG_STANDBY\trStandby\n#define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR\trTxAGC_A_CCK11_CCK1_JAguar\n#define REG_TX_AGC_A_CCK_1_MCS32\trTxAGC_A_CCK1_Mcs32\n#define REG_TX_AGC_A_MCS11_MCS8_JAGUAR\trTxAGC_A_MCS11_MCS8_JAguar\n#define REG_TX_AGC_A_MCS15_MCS12_JAGUAR\trTxAGC_A_MCS15_MCS12_JAguar\n#define REG_TX_AGC_A_MCS19_MCS16_JAGUAR\trTxAGC_A_MCS19_MCS16_JAguar\n#define REG_TX_AGC_A_MCS23_MCS20_JAGUAR\trTxAGC_A_MCS23_MCS20_JAguar\n#define REG_TX_AGC_A_MCS3_MCS0_JAGUAR\trTxAGC_A_MCS3_MCS0_JAguar\n#define REG_TX_AGC_A_MCS7_MCS4_JAGUAR\trTxAGC_A_MCS7_MCS4_JAguar\n#define REG_TX_AGC_A_MCS03_MCS00\trTxAGC_A_Mcs03_Mcs00\n#define REG_TX_AGC_A_MCS07_MCS04\trTxAGC_A_Mcs07_Mcs04\n#define REG_TX_AGC_A_MCS11_MCS08\trTxAGC_A_Mcs11_Mcs08\n#define REG_TX_AGC_A_MCS15_MCS12\trTxAGC_A_Mcs15_Mcs12\n#define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR\trTxAGC_A_Nss1Index3_Nss1Index0_JAguar\n#define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR\trTxAGC_A_Nss1Index7_Nss1Index4_JAguar\n#define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR\trTxAGC_A_Nss2Index1_Nss1Index8_JAguar\n#define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR\trTxAGC_A_Nss2Index5_Nss2Index2_JAguar\n#define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR\trTxAGC_A_Nss2Index9_Nss2Index6_JAguar\n#define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR\trTxAGC_A_Nss3Index3_Nss3Index0_JAguar\n#define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR\trTxAGC_A_Nss3Index7_Nss3Index4_JAguar\n#define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR\trTxAGC_A_Nss3Index9_Nss3Index8_JAguar\n#define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR\trTxAGC_A_Ofdm18_Ofdm6_JAguar\n#define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR\trTxAGC_A_Ofdm54_Ofdm24_JAguar\n#define REG_TX_AGC_A_RATE18_06\trTxAGC_A_Rate18_06\n#define REG_TX_AGC_A_RATE54_24\trTxAGC_A_Rate54_24\n#define REG_TX_AGC_B_CCK_11_A_CCK_2_11\trTxAGC_B_CCK11_A_CCK2_11\n#define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR\trTxAGC_B_CCK11_CCK1_JAguar\n#define REG_TX_AGC_B_CCK_1_55_MCS32\trTxAGC_B_CCK1_55_Mcs32\n#define REG_TX_AGC_B_MCS11_MCS8_JAGUAR\trTxAGC_B_MCS11_MCS8_JAguar\n#define REG_TX_AGC_B_MCS15_MCS12_JAGUAR\trTxAGC_B_MCS15_MCS12_JAguar\n#define REG_TX_AGC_B_MCS19_MCS16_JAGUAR\trTxAGC_B_MCS19_MCS16_JAguar\n#define REG_TX_AGC_B_MCS23_MCS20_JAGUAR\trTxAGC_B_MCS23_MCS20_JAguar\n#define REG_TX_AGC_B_MCS3_MCS0_JAGUAR\trTxAGC_B_MCS3_MCS0_JAguar\n#define REG_TX_AGC_B_MCS7_MCS4_JAGUAR\trTxAGC_B_MCS7_MCS4_JAguar\n#define REG_TX_AGC_B_MCS03_MCS00\trTxAGC_B_Mcs03_Mcs00\n#define REG_TX_AGC_B_MCS07_MCS04\trTxAGC_B_Mcs07_Mcs04\n#define REG_TX_AGC_B_MCS11_MCS08\trTxAGC_B_Mcs11_Mcs08\n#define REG_TX_AGC_B_MCS15_MCS12\trTxAGC_B_Mcs15_Mcs12\n#define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR\trTxAGC_B_Nss1Index3_Nss1Index0_JAguar\n#define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR\trTxAGC_B_Nss1Index7_Nss1Index4_JAguar\n#define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR\trTxAGC_B_Nss2Index1_Nss1Index8_JAguar\n#define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR\trTxAGC_B_Nss2Index5_Nss2Index2_JAguar\n#define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR\trTxAGC_B_Nss2Index9_Nss2Index6_JAguar\n#define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR\trTxAGC_B_Nss3Index3_Nss3Index0_JAguar\n#define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR\trTxAGC_B_Nss3Index7_Nss3Index4_JAguar\n#define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR\trTxAGC_B_Nss3Index9_Nss3Index8_JAguar\n#define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR\trTxAGC_B_Ofdm18_Ofdm6_JAguar\n#define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR\trTxAGC_B_Ofdm54_Ofdm24_JAguar\n#define REG_TX_AGC_B_RATE18_06\trTxAGC_B_Rate18_06\n#define REG_TX_AGC_B_RATE54_24\trTxAGC_B_Rate54_24\n#define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR\trTxAGC_C_CCK11_CCK1_JAguar\n#define REG_TX_AGC_C_MCS11_MCS8_JAGUAR\trTxAGC_C_MCS11_MCS8_JAguar\n#define REG_TX_AGC_C_MCS15_MCS12_JAGUAR\trTxAGC_C_MCS15_MCS12_JAguar\n#define REG_TX_AGC_C_MCS19_MCS16_JAGUAR\trTxAGC_C_MCS19_MCS16_JAguar\n#define REG_TX_AGC_C_MCS23_MCS20_JAGUAR\trTxAGC_C_MCS23_MCS20_JAguar\n#define REG_TX_AGC_C_MCS3_MCS0_JAGUAR\trTxAGC_C_MCS3_MCS0_JAguar\n#define REG_TX_AGC_C_MCS7_MCS4_JAGUAR\trTxAGC_C_MCS7_MCS4_JAguar\n#define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR\trTxAGC_C_Nss1Index3_Nss1Index0_JAguar\n#define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR\trTxAGC_C_Nss1Index7_Nss1Index4_JAguar\n#define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR\trTxAGC_C_Nss2Index1_Nss1Index8_JAguar\n#define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR\trTxAGC_C_Nss2Index5_Nss2Index2_JAguar\n#define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR\trTxAGC_C_Nss2Index9_Nss2Index6_JAguar\n#define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR\trTxAGC_C_Nss3Index3_Nss3Index0_JAguar\n#define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR\trTxAGC_C_Nss3Index7_Nss3Index4_JAguar\n#define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR\trTxAGC_C_Nss3Index9_Nss3Index8_JAguar\n#define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR\trTxAGC_C_Ofdm18_Ofdm6_JAguar\n#define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR\trTxAGC_C_Ofdm54_Ofdm24_JAguar\n#define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR\trTxAGC_D_CCK11_CCK1_JAguar\n#define REG_TX_AGC_D_MCS11_MCS8_JAGUAR\trTxAGC_D_MCS11_MCS8_JAguar\n#define REG_TX_AGC_D_MCS15_MCS12_JAGUAR\trTxAGC_D_MCS15_MCS12_JAguar\n#define REG_TX_AGC_D_MCS19_MCS16_JAGUAR\trTxAGC_D_MCS19_MCS16_JAguar\n#define REG_TX_AGC_D_MCS23_MCS20_JAGUAR\trTxAGC_D_MCS23_MCS20_JAguar\n#define REG_TX_AGC_D_MCS3_MCS0_JAGUAR\trTxAGC_D_MCS3_MCS0_JAguar\n#define REG_TX_AGC_D_MCS7_MCS4_JAGUAR\trTxAGC_D_MCS7_MCS4_JAguar\n#define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR\trTxAGC_D_Nss1Index3_Nss1Index0_JAguar\n#define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR\trTxAGC_D_Nss1Index7_Nss1Index4_JAguar\n#define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR\trTxAGC_D_Nss2Index1_Nss1Index8_JAguar\n#define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR\trTxAGC_D_Nss2Index5_Nss2Index2_JAguar\n#define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR\trTxAGC_D_Nss2Index9_Nss2Index6_JAguar\n#define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR\trTxAGC_D_Nss3Index3_Nss3Index0_JAguar\n#define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR\trTxAGC_D_Nss3Index7_Nss3Index4_JAguar\n#define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR\trTxAGC_D_Nss3Index9_Nss3Index8_JAguar\n#define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR\trTxAGC_D_Ofdm18_Ofdm6_JAguar\n#define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR\trTxAGC_D_Ofdm54_Ofdm24_JAguar\n#define REG_TX_PATH_JAGUAR\trTxPath_Jaguar\n#define REG_TX_CCK_BBON\trTx_CCK_BBON\n#define REG_TX_CCK_RFON\trTx_CCK_RFON\n#define REG_TX_IQK\trTx_IQK\n#define REG_TX_IQK_PI_A\trTx_IQK_PI_A\n#define REG_TX_IQK_PI_B\trTx_IQK_PI_B\n#define REG_TX_IQK_TONE_A\trTx_IQK_Tone_A\n#define REG_TX_IQK_TONE_B\trTx_IQK_Tone_B\n#define REG_TX_OFDM_BBON\trTx_OFDM_BBON\n#define REG_TX_OFDM_RFON\trTx_OFDM_RFON\n#define REG_TX_POWER_AFTER_IQK_A\trTx_Power_After_IQK_A\n#define REG_TX_POWER_AFTER_IQK_B\trTx_Power_After_IQK_B\n#define REG_TX_POWER_BEFORE_IQK_A\trTx_Power_Before_IQK_A\n#define REG_TX_POWER_BEFORE_IQK_B\trTx_Power_Before_IQK_B\n#define REG_TX_TO_RX\trTx_To_Rx\n#define REG_TX_TO_TX\trTx_To_Tx\n#define REG_APK\trAPK\n#define REG_ANTSEL_SW_JAGUAR\tr_ANTSEL_SW_Jaguar\n\n#define rf_welut_jaguar\tRF_WeLut_Jaguar\n#define rf_mode_table_addr\tRF_ModeTableAddr\n#define rf_mode_table_data0\tRF_ModeTableData0\n#define rf_mode_table_data1\tRF_ModeTableData1\n\n#define RX_SMOOTH_FACTOR\tRx_Smooth_Factor\n\n#endif /* __HAL_PHY_REG_H__ */\n"
  },
  {
    "path": "include/hal_sdio.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __HAL_SDIO_H_\n#define __HAL_SDIO_H_\n\n#define ffaddr2deviceId(pdvobj, addr)\t(pdvobj->Queue2Pipe[addr])\n\nu8 rtw_hal_sdio_max_txoqt_free_space(_adapter *padapter);\nu8 rtw_hal_sdio_query_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);\nvoid rtw_hal_sdio_update_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);\nvoid rtw_hal_set_sdio_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ, u8 div_num);\nu32 rtw_hal_get_sdio_tx_max_length(PADAPTER padapter, u8 queue_idx);\nbool sdio_power_on_check(PADAPTER padapter);\n\n#ifdef CONFIG_FW_C2H_REG\nvoid sd_c2h_hisr_hdl(_adapter *adapter);\n#endif\n\n#if defined(CONFIG_RTL8188F) || defined (CONFIG_RTL8188GTV) || defined (CONFIG_RTL8192F)\n#define SDIO_LOCAL_CMD_ADDR(addr) ((SDIO_LOCAL_DEVICE_ID << 13) | ((addr) & SDIO_LOCAL_MSK))\n#endif\n\n#ifdef CONFIG_SDIO_CHK_HCI_RESUME\nbool sdio_chk_hci_resume(struct intf_hdl *pintfhdl);\nvoid sdio_chk_hci_suspend(struct intf_hdl *pintfhdl);\n#else\n#define sdio_chk_hci_resume(pintfhdl) _FALSE\n#define sdio_chk_hci_suspend(pintfhdl) do {} while (0)\n#endif /* CONFIG_SDIO_CHK_HCI_RESUME */\n\n#ifdef CONFIG_SDIO_INDIRECT_ACCESS\n/* program indirect access register in sdio local to read/write page0 registers */\ns32 sdio_iread(PADAPTER padapter, u32 addr, u8 size, u8 *v);\ns32 sdio_iwrite(PADAPTER padapter, u32 addr, u8 size, u8 *v);\nu8 sdio_iread8(struct intf_hdl *pintfhdl, u32 addr);\nu16 sdio_iread16(struct intf_hdl *pintfhdl, u32 addr);\nu32 sdio_iread32(struct intf_hdl *pintfhdl, u32 addr);\ns32 sdio_iwrite8(struct intf_hdl *pintfhdl, u32 addr, u8 val);\ns32 sdio_iwrite16(struct intf_hdl *pintfhdl, u32 addr, u16 val);\ns32 sdio_iwrite32(struct intf_hdl *pintfhdl, u32 addr, u32 val);\n#endif /* CONFIG_SDIO_INDIRECT_ACCESS */\nu32 cmd53_4byte_alignment(struct intf_hdl *pintfhdl, u32 addr);\n\n#endif /* __HAL_SDIO_H_ */\n"
  },
  {
    "path": "include/hal_sdio_coex.h",
    "content": "/******************************************************************************\r\n *\r\n * Copyright(c) 2013 Realtek Corporation. All rights reserved.\r\n *\r\n * This program is free software; you can redistribute it and/or modify it\r\n * under the terms of version 2 of the GNU General Public License as\r\n * published by the Free Software Foundation.\r\n *\r\n * This program is distributed in the hope that it will be useful, but WITHOUT\r\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r\n * more details.\r\n *\r\n * You should have received a copy of the GNU General Public License along with\r\n * this program; if not, write to the Free Software Foundation, Inc.,\r\n * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r\n *\r\n *\r\n ******************************************************************************/\r\n#ifndef __HAL_SDIO_COEX_H__\r\n#define __HAL_SDIO_COEX_H__\r\n\r\n#include <drv_types.h>\r\n\r\n#ifdef CONFIG_SDIO_MULTI_FUNCTION_COEX\r\n\r\nenum { /* for sdio multi-func. coex */\r\n\tSDIO_MULTI_WIFI = 0,\r\n\tSDIO_MULTI_BT,\r\n\tSDIO_MULTI_NUM\r\n};\r\n\r\nbool ex_hal_sdio_multi_if_bus_available(PADAPTER adapter);\r\n\r\n#else\r\n\r\n#define ex_hal_sdio_multi_if_bus_available(adapter) TRUE\r\n\r\n#endif  /* CONFIG_SDIO_MULTI_FUNCTION_COEX */\r\n#endif  /* !__HAL_SDIO_COEX_H__ */\r\n\r\n"
  },
  {
    "path": "include/ieee80211.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __IEEE80211_H\n#define __IEEE80211_H\n\n#define MGMT_QUEUE_NUM 5\n\n#define ETH_ALEN\t6\n#define ETH_TYPE_LEN\t\t2\n#define PAYLOAD_TYPE_LEN\t1\n\n#define NET80211_TU_TO_US\t1024\t\t/* unit:us */\n#define DEFAULT_BCN_INTERVAL 100 /* 100 ms */\n\n#ifdef CONFIG_AP_MODE\n\n#define RTL_IOCTL_HOSTAPD (SIOCIWFIRSTPRIV + 28)\n\n/* RTL871X_IOCTL_HOSTAPD ioctl() cmd: */\nenum {\n\tRTL871X_HOSTAPD_FLUSH = 1,\n\tRTL871X_HOSTAPD_ADD_STA = 2,\n\tRTL871X_HOSTAPD_REMOVE_STA = 3,\n\tRTL871X_HOSTAPD_GET_INFO_STA = 4,\n\t/* REMOVED: PRISM2_HOSTAPD_RESET_TXEXC_STA = 5, */\n\tRTL871X_HOSTAPD_GET_WPAIE_STA = 5,\n\tRTL871X_SET_ENCRYPTION = 6,\n\tRTL871X_GET_ENCRYPTION = 7,\n\tRTL871X_HOSTAPD_SET_FLAGS_STA = 8,\n\tRTL871X_HOSTAPD_GET_RID = 9,\n\tRTL871X_HOSTAPD_SET_RID = 10,\n\tRTL871X_HOSTAPD_SET_ASSOC_AP_ADDR = 11,\n\tRTL871X_HOSTAPD_SET_GENERIC_ELEMENT = 12,\n\tRTL871X_HOSTAPD_MLME = 13,\n\tRTL871X_HOSTAPD_SCAN_REQ = 14,\n\tRTL871X_HOSTAPD_STA_CLEAR_STATS = 15,\n\tRTL871X_HOSTAPD_SET_BEACON = 16,\n\tRTL871X_HOSTAPD_SET_WPS_BEACON = 17,\n\tRTL871X_HOSTAPD_SET_WPS_PROBE_RESP = 18,\n\tRTL871X_HOSTAPD_SET_WPS_ASSOC_RESP = 19,\n\tRTL871X_HOSTAPD_SET_HIDDEN_SSID = 20,\n\tRTL871X_HOSTAPD_SET_MACADDR_ACL = 21,\n\tRTL871X_HOSTAPD_ACL_ADD_STA = 22,\n\tRTL871X_HOSTAPD_ACL_REMOVE_STA = 23,\n};\n\n/* STA flags */\n#define WLAN_STA_AUTH BIT(0)\n#define WLAN_STA_ASSOC BIT(1)\n#define WLAN_STA_PS BIT(2)\n#define WLAN_STA_TIM BIT(3)\n#define WLAN_STA_PERM BIT(4)\n#define WLAN_STA_AUTHORIZED BIT(5)\n#define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */\n#define WLAN_STA_SHORT_PREAMBLE BIT(7)\n#define WLAN_STA_PREAUTH BIT(8)\n#define WLAN_STA_WME BIT(9)\n#define WLAN_STA_MFP BIT(10)\n#define WLAN_STA_HT BIT(11)\n#define WLAN_STA_WPS BIT(12)\n#define WLAN_STA_MAYBE_WPS BIT(13)\n#define WLAN_STA_VHT BIT(14)\n#define WLAN_STA_NONERP BIT(31)\n\n#endif\n\n#define IEEE_CMD_SET_WPA_PARAM\t\t\t1\n#define IEEE_CMD_SET_WPA_IE\t\t\t\t2\n#define IEEE_CMD_SET_ENCRYPTION\t\t\t3\n#define IEEE_CMD_MLME\t\t\t\t\t\t4\n\n#define IEEE_PARAM_WPA_ENABLED\t\t\t\t1\n#define IEEE_PARAM_TKIP_COUNTERMEASURES\t\t2\n#define IEEE_PARAM_DROP_UNENCRYPTED\t\t\t3\n#define IEEE_PARAM_PRIVACY_INVOKED\t\t\t4\n#define IEEE_PARAM_AUTH_ALGS\t\t\t\t\t5\n#define IEEE_PARAM_IEEE_802_1X\t\t\t\t6\n#define IEEE_PARAM_WPAX_SELECT\t\t\t\t7\n\n#define AUTH_ALG_OPEN_SYSTEM\t\t\t0x1\n#define AUTH_ALG_SHARED_KEY\t\t\t0x2\n#define AUTH_ALG_LEAP\t\t\t\t0x00000004\n\n#define IEEE_MLME_STA_DEAUTH\t\t\t\t1\n#define IEEE_MLME_STA_DISASSOC\t\t\t2\n\n#define IEEE_CRYPT_ERR_UNKNOWN_ALG\t\t\t2\n#define IEEE_CRYPT_ERR_UNKNOWN_ADDR\t\t\t3\n#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED\t\t4\n#define IEEE_CRYPT_ERR_KEY_SET_FAILED\t\t\t5\n#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED\t\t6\n#define IEEE_CRYPT_ERR_CARD_CONF_FAILED\t\t7\n\n\n#define\tIEEE_CRYPT_ALG_NAME_LEN\t\t\t16\n\n#define WPA_CIPHER_NONE\tBIT(0)\n#define WPA_CIPHER_WEP40\tBIT(1)\n#define WPA_CIPHER_WEP104 BIT(2)\n#define WPA_CIPHER_TKIP\tBIT(3)\n#define WPA_CIPHER_CCMP\tBIT(4)\n\n\n\n#define WPA_SELECTOR_LEN 4\nextern u8 RTW_WPA_OUI_TYPE[] ;\nextern u16 RTW_WPA_VERSION ;\nextern u8 WPA_AUTH_KEY_MGMT_NONE[];\nextern u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[];\nextern u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[];\nextern u8 WPA_CIPHER_SUITE_NONE[];\nextern u8 WPA_CIPHER_SUITE_WEP40[];\nextern u8 WPA_CIPHER_SUITE_TKIP[];\nextern u8 WPA_CIPHER_SUITE_WRAP[];\nextern u8 WPA_CIPHER_SUITE_CCMP[];\nextern u8 WPA_CIPHER_SUITE_WEP104[];\n\n\n#define RSN_HEADER_LEN 4\n#define RSN_SELECTOR_LEN 4\n\nextern u16 RSN_VERSION_BSD;\nextern u8 RSN_CIPHER_SUITE_NONE[];\nextern u8 RSN_CIPHER_SUITE_WEP40[];\nextern u8 RSN_CIPHER_SUITE_TKIP[];\nextern u8 RSN_CIPHER_SUITE_WRAP[];\nextern u8 RSN_CIPHER_SUITE_CCMP[];\nextern u8 RSN_CIPHER_SUITE_WEP104[];\n\n/* AKM suite type */\nextern u8 WLAN_AKM_8021X[];\nextern u8 WLAN_AKM_PSK[];\nextern u8 WLAN_AKM_FT_8021X[];\nextern u8 WLAN_AKM_FT_PSK[];\nextern u8 WLAN_AKM_8021X_SHA256[];\nextern u8 WLAN_AKM_PSK_SHA256[];\nextern u8 WLAN_AKM_TDLS[];\nextern u8 WLAN_AKM_SAE[];\nextern u8 WLAN_AKM_FT_OVER_SAE[];\nextern u8 WLAN_AKM_8021X_SUITE_B[];\nextern u8 WLAN_AKM_8021X_SUITE_B_192[];\nextern u8 WLAN_AKM_FILS_SHA256[];\nextern u8 WLAN_AKM_FILS_SHA384[];\nextern u8 WLAN_AKM_FT_FILS_SHA256[];\nextern u8 WLAN_AKM_FT_FILS_SHA384[];\n\n#define WLAN_AKM_TYPE_8021X BIT(0)\n#define WLAN_AKM_TYPE_PSK BIT(1)\n#define WLAN_AKM_TYPE_FT_8021X BIT(2)\n#define WLAN_AKM_TYPE_FT_PSK BIT(3)\n#define WLAN_AKM_TYPE_8021X_SHA256 BIT(4)\n#define WLAN_AKM_TYPE_PSK_SHA256 BIT(5)\n#define WLAN_AKM_TYPE_TDLS BIT(6)\n#define WLAN_AKM_TYPE_SAE BIT(7)\n#define WLAN_AKM_TYPE_FT_OVER_SAE BIT(8)\n#define WLAN_AKM_TYPE_8021X_SUITE_B BIT(9)\n#define WLAN_AKM_TYPE_8021X_SUITE_B_192 BIT(10)\n#define WLAN_AKM_TYPE_FILS_SHA256 BIT(11)\n#define WLAN_AKM_TYPE_FILS_SHA384 BIT(12)\n#define WLAN_AKM_TYPE_FT_FILS_SHA256 BIT(13)\n#define WLAN_AKM_TYPE_FT_FILS_SHA384 BIT(14)\n\n/* IEEE 802.11i */\n#define PMKID_LEN 16\n#define PMK_LEN 32\n#define PMK_LEN_SUITE_B_192 48\n#define PMK_LEN_MAX 48\n#define WPA_REPLAY_COUNTER_LEN 8\n#define WPA_NONCE_LEN 32\n#define WPA_KEY_RSC_LEN 8\n#define WPA_GMK_LEN 32\n#define WPA_GTK_MAX_LEN 32\n\n/* IEEE 802.11, 8.5.2 EAPOL-Key frames */\n#define WPA_KEY_INFO_TYPE_MASK ((u16) (BIT(0) | BIT(1) | BIT(2)))\n#define WPA_KEY_INFO_TYPE_AKM_DEFINED 0\n#define WPA_KEY_INFO_TYPE_HMAC_MD5_RC4 BIT(0)\n#define WPA_KEY_INFO_TYPE_HMAC_SHA1_AES BIT(1)\n#define WPA_KEY_INFO_TYPE_AES_128_CMAC 3\n#define WPA_KEY_INFO_KEY_TYPE BIT(3) /* 1 = Pairwise, 0 = Group key */\n/* bit4..5 is used in WPA, but is reserved in IEEE 802.11i/RSN */\n#define WPA_KEY_INFO_KEY_INDEX_MASK (BIT(4) | BIT(5))\n#define WPA_KEY_INFO_KEY_INDEX_SHIFT 4\n#define WPA_KEY_INFO_INSTALL BIT(6) /* pairwise */\n#define WPA_KEY_INFO_TXRX BIT(6) /* group */\n#define WPA_KEY_INFO_ACK BIT(7)\n#define WPA_KEY_INFO_MIC BIT(8)\n#define WPA_KEY_INFO_SECURE BIT(9)\n#define WPA_KEY_INFO_ERROR BIT(10)\n#define WPA_KEY_INFO_REQUEST BIT(11)\n#define WPA_KEY_INFO_ENCR_KEY_DATA BIT(12) /* IEEE 802.11i/RSN only */\n#define WPA_KEY_INFO_SMK_MESSAGE BIT(13)\n\nstruct ieee802_1x_hdr {\n\tu8 version;\n\tu8 type;\n\tu16 length;\n\t/* followed by length octets of data */\n};\n\nstruct wpa_eapol_key {\n\tu8 type;\n\t/* Note: key_info, key_length, and key_data_length are unaligned */\n\tu8 key_info[2]; /* big endian */\n\tu8 key_length[2]; /* big endian */\n\tu8 replay_counter[WPA_REPLAY_COUNTER_LEN];\n\tu8 key_nonce[WPA_NONCE_LEN];\n\tu8 key_iv[16];\n\tu8 key_rsc[WPA_KEY_RSC_LEN];\n\tu8 key_id[8]; /* Reserved in IEEE 802.11i/RSN */\n\tu8 key_mic[16];\n\tu8 key_data_length[2]; /* big endian */\n\t/* followed by key_data_length bytes of key_data */\n};\n\ntypedef enum _RATEID_IDX_ {\n\tRATEID_IDX_BGN_40M_2SS = 0,\n\tRATEID_IDX_BGN_40M_1SS = 1,\n\tRATEID_IDX_BGN_20M_2SS_BN = 2,\n\tRATEID_IDX_BGN_20M_1SS_BN = 3,\n\tRATEID_IDX_GN_N2SS = 4,\n\tRATEID_IDX_GN_N1SS = 5,\n\tRATEID_IDX_BG = 6,\n\tRATEID_IDX_G = 7,\n\tRATEID_IDX_B = 8,\n\tRATEID_IDX_VHT_2SS = 9,\n\tRATEID_IDX_VHT_1SS = 10,\n\tRATEID_IDX_MIX1 = 11,\n\tRATEID_IDX_MIX2 = 12,\n\tRATEID_IDX_VHT_3SS = 13,\n\tRATEID_IDX_BGN_3SS = 14,\n} RATEID_IDX, *PRATEID_IDX;\n\ntypedef enum _RATR_TABLE_MODE {\n\tRATR_INX_WIRELESS_NGB = 0,\t/* BGN 40 Mhz 2SS 1SS */\n\tRATR_INX_WIRELESS_NG = 1,\t\t/* GN or N */\n\tRATR_INX_WIRELESS_NB = 2,\t\t/* BGN 20 Mhz 2SS 1SS  or BN */\n\tRATR_INX_WIRELESS_N = 3,\n\tRATR_INX_WIRELESS_GB = 4,\n\tRATR_INX_WIRELESS_G = 5,\n\tRATR_INX_WIRELESS_B = 6,\n\tRATR_INX_WIRELESS_MC = 7,\n\tRATR_INX_WIRELESS_AC_N = 8,\n} RATR_TABLE_MODE, *PRATR_TABLE_MODE;\n\n\nenum NETWORK_TYPE {\n\tWIRELESS_INVALID = 0,\n\t/* Sub-Element */\n\tWIRELESS_11B = BIT(0), /* tx: cck only , rx: cck only, hw: cck */\n\tWIRELESS_11G = BIT(1), /* tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm */\n\tWIRELESS_11A = BIT(2), /* tx: ofdm only, rx: ofdm only, hw: ofdm only */\n\tWIRELESS_11_24N = BIT(3), /* tx: MCS only, rx: MCS & cck, hw: MCS & cck */\n\tWIRELESS_11_5N = BIT(4), /* tx: MCS only, rx: MCS & ofdm, hw: ofdm only */\n\tWIRELESS_AUTO = BIT(5),\n\tWIRELESS_11AC = BIT(6),\n\n\t/* Combination */\n\t/* Type for current wireless mode */\n\tWIRELESS_11BG = (WIRELESS_11B | WIRELESS_11G), /* tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm */\n\tWIRELESS_11G_24N = (WIRELESS_11G | WIRELESS_11_24N), /* tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm */\n\tWIRELESS_11A_5N = (WIRELESS_11A | WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */\n\tWIRELESS_11B_24N = (WIRELESS_11B | WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */\n\tWIRELESS_11BG_24N = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */\n\tWIRELESS_11_24AC = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11AC),\n\tWIRELESS_11_5AC = (WIRELESS_11A | WIRELESS_11AC),\n\n\n\t/* Type for registry default wireless mode */\n\tWIRELESS_11AGN = (WIRELESS_11A | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */\n\tWIRELESS_11ABGN = (WIRELESS_11A | WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N),\n\tWIRELESS_MODE_24G = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N),\n\tWIRELESS_MODE_5G = (WIRELESS_11A | WIRELESS_11_5N | WIRELESS_11AC),\n\tWIRELESS_MODE_MAX = (WIRELESS_11A | WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N | WIRELESS_11AC),\n};\n\n#define SUPPORTED_24G_NETTYPE_MSK WIRELESS_MODE_24G\n#define SUPPORTED_5G_NETTYPE_MSK WIRELESS_MODE_5G\n\n#define IsLegacyOnly(NetType)  ((NetType) == ((NetType) & (WIRELESS_11BG | WIRELESS_11A)))\n\n#define IsSupported24G(NetType) ((NetType) & SUPPORTED_24G_NETTYPE_MSK ? _TRUE : _FALSE)\n#define is_supported_5g(NetType) ((NetType) & SUPPORTED_5G_NETTYPE_MSK ? _TRUE : _FALSE)\n\n#define IsEnableHWCCK(NetType) IsSupported24G(NetType)\n#define IsEnableHWOFDM(NetType) ((NetType) & (WIRELESS_11G | WIRELESS_11_24N | SUPPORTED_5G_NETTYPE_MSK) ? _TRUE : _FALSE)\n\n#define IsSupportedRxCCK(NetType) IsEnableHWCCK(NetType)\n#define IsSupportedRxOFDM(NetType) IsEnableHWOFDM(NetType)\n#define IsSupportedRxHT(NetType) IsEnableHWOFDM(NetType)\n\n#define IsSupportedTxCCK(NetType) ((NetType) & (WIRELESS_11B) ? _TRUE : _FALSE)\n#define IsSupportedTxOFDM(NetType) ((NetType) & (WIRELESS_11G | WIRELESS_11A) ? _TRUE : _FALSE)\n#define is_supported_ht(NetType) ((NetType) & (WIRELESS_11_24N | WIRELESS_11_5N) ? _TRUE : _FALSE)\n\n#define is_supported_vht(NetType) ((NetType) & (WIRELESS_11AC) ? _TRUE : _FALSE)\n\n\n\n\n\ntypedef struct ieee_param {\n\tu32 cmd;\n\tu8 sta_addr[ETH_ALEN];\n\tunion {\n\t\tstruct {\n\t\t\tu8 name;\n\t\t\tu32 value;\n\t\t} wpa_param;\n\t\tstruct {\n\t\t\tu32 len;\n\t\t\tu8 reserved[32];\n\t\t\tu8 data[0];\n\t\t} wpa_ie;\n\t\tstruct {\n\t\t\tint command;\n\t\t\tint reason_code;\n\t\t} mlme;\n\t\tstruct {\n\t\t\tu8 alg[IEEE_CRYPT_ALG_NAME_LEN];\n\t\t\tu8 set_tx;\n\t\t\tu32 err;\n\t\t\tu8 idx;\n\t\t\tu8 seq[8]; /* sequence counter (set: RX, get: TX) */\n\t\t\tu16 key_len;\n\t\t\tu8 key[0];\n\t\t} crypt;\n#ifdef CONFIG_AP_MODE\n\t\tstruct {\n\t\t\tu16 aid;\n\t\t\tu16 capability;\n\t\t\tint flags;\n\t\t\tu8 tx_supp_rates[16];\n\t\t\tstruct rtw_ieee80211_ht_cap ht_cap;\n\t\t} add_sta;\n\t\tstruct {\n\t\t\tu8\treserved[2];/* for set max_num_sta */\n\t\t\tu8\tbuf[0];\n\t\t} bcn_ie;\n#endif\n\n\t} u;\n} ieee_param;\n\n#ifdef CONFIG_AP_MODE\ntypedef struct ieee_param_ex {\n\tu32 cmd;\n\tu8 sta_addr[ETH_ALEN];\n\tu8 data[0];\n} ieee_param_ex;\n\nstruct sta_data {\n\tu16 aid;\n\tu16 capability;\n\tint flags;\n\tu32 sta_set;\n\tu8 tx_supp_rates[16];\n\tu32 tx_supp_rates_len;\n\tstruct rtw_ieee80211_ht_cap ht_cap;\n\tu64\trx_pkts;\n\tu64\trx_bytes;\n\tu64\trx_drops;\n\tu64\ttx_pkts;\n\tu64\ttx_bytes;\n\tu64\ttx_drops;\n};\n#endif\n\n\n#if WIRELESS_EXT < 17\n\t#define IW_QUAL_QUAL_INVALID   0x10\n\t#define IW_QUAL_LEVEL_INVALID  0x20\n\t#define IW_QUAL_NOISE_INVALID  0x40\n\t#define IW_QUAL_QUAL_UPDATED   0x1\n\t#define IW_QUAL_LEVEL_UPDATED  0x2\n\t#define IW_QUAL_NOISE_UPDATED  0x4\n#endif\n\n#define IEEE80211_DATA_LEN\t\t2304\n/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section\n   6.2.1.1.2.\n\n   The figure in section 7.1.2 suggests a body size of up to 2312\n   bytes is allowed, which is a bit confusing, I suspect this\n   represents the 2304 bytes of real data, plus a possible 8 bytes of\n   WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */\n\n\n#define IEEE80211_HLEN\t\t\t30\n#define IEEE80211_FRAME_LEN\t\t(IEEE80211_DATA_LEN + IEEE80211_HLEN)\n\n\n/* this is stolen from ipw2200 driver */\n#define IEEE_IBSS_MAC_HASH_SIZE 31\n\nstruct ieee_ibss_seq {\n\tu8 mac[ETH_ALEN];\n\tu16 seq_num;\n\tu16 frag_num;\n\tunsigned long packet_time;\n\t_list\tlist;\n};\n\n#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)\n\nstruct rtw_ieee80211_hdr {\n\tu16 frame_ctl;\n\tu16 duration_id;\n\tu8 addr1[ETH_ALEN];\n\tu8 addr2[ETH_ALEN];\n\tu8 addr3[ETH_ALEN];\n\tu16 seq_ctl;\n\tu8 addr4[ETH_ALEN];\n} __attribute__((packed));\n\nstruct rtw_ieee80211_hdr_3addr {\n\tu16 frame_ctl;\n\tu16 duration_id;\n\tu8 addr1[ETH_ALEN];\n\tu8 addr2[ETH_ALEN];\n\tu8 addr3[ETH_ALEN];\n\tu16 seq_ctl;\n} __attribute__((packed));\n\n\nstruct rtw_ieee80211_hdr_qos {\n\tu16 frame_ctl;\n\tu16 duration_id;\n\tu8 addr1[ETH_ALEN];\n\tu8 addr2[ETH_ALEN];\n\tu8 addr3[ETH_ALEN];\n\tu16 seq_ctl;\n\tu8 addr4[ETH_ALEN];\n\tu16\tqc;\n}  __attribute__((packed));\n\nstruct rtw_ieee80211_hdr_3addr_qos {\n\tu16 frame_ctl;\n\tu16 duration_id;\n\tu8 addr1[ETH_ALEN];\n\tu8 addr2[ETH_ALEN];\n\tu8 addr3[ETH_ALEN];\n\tu16 seq_ctl;\n\tu16     qc;\n}  __attribute__((packed));\n\nstruct eapol {\n\tu8 snap[6];\n\tu16 ethertype;\n\tu8 version;\n\tu8 type;\n\tu16 length;\n} __attribute__((packed));\n\nstruct rtw_ieee80211s_hdr {\n\tu8 flags;\n\tu8 ttl;\n\tu32 seqnum;\n\tu8 eaddr1[ETH_ALEN];\n\tu8 eaddr2[ETH_ALEN];\n} __attribute__((packed));\n\n/**\n * struct rtw_ieee80211_rann_ie\n *\n * This structure refers to \"Root Announcement information element\"\n */\n struct rtw_ieee80211_rann_ie {\n\tu8 rann_flags;\n\tu8 rann_hopcount;\n\tu8 rann_ttl;\n\tu8 rann_addr[ETH_ALEN];\n\tu32 rann_seq;\n\tu32 rann_interval;\n\tu32 rann_metric;\n} __attribute__((packed));\n#endif\n\nenum eap_type {\n\tEAP_PACKET = 0,\n\tEAPOL_START,\n\tEAPOL_LOGOFF,\n\tEAPOL_KEY,\n\tEAPOL_ENCAP_ASF_ALERT\n};\n\n#define IEEE80211_3ADDR_LEN 24\n#define IEEE80211_4ADDR_LEN 30\n#define IEEE80211_FCS_LEN    4\n\n#define MIN_FRAG_THRESHOLD     256U\n#define\tMAX_FRAG_THRESHOLD     2346U\n\n/* Frame control field constants */\n#define RTW_IEEE80211_FCTL_VERS\t\t0x0003\n#define RTW_IEEE80211_FCTL_FTYPE\t\t0x000c\n#define RTW_IEEE80211_FCTL_STYPE\t\t0x00f0\n#define RTW_IEEE80211_FCTL_TODS\t\t0x0100\n#define RTW_IEEE80211_FCTL_FROMDS\t0x0200\n#define RTW_IEEE80211_FCTL_MOREFRAGS\t0x0400\n#define RTW_IEEE80211_FCTL_RETRY\t\t0x0800\n#define RTW_IEEE80211_FCTL_PM\t\t0x1000\n#define RTW_IEEE80211_FCTL_MOREDATA\t0x2000\n#define RTW_IEEE80211_FCTL_PROTECTED\t0x4000\n#define RTW_IEEE80211_FCTL_ORDER\t\t0x8000\n#define RTW_IEEE80211_FCTL_CTL_EXT\t0x0f00\n\n#define RTW_IEEE80211_FTYPE_MGMT\t\t0x0000\n#define RTW_IEEE80211_FTYPE_CTL\t\t0x0004\n#define RTW_IEEE80211_FTYPE_DATA\t\t0x0008\n#define RTW_IEEE80211_FTYPE_EXT\t\t0x000c\n\n/* management */\n#define RTW_IEEE80211_STYPE_ASSOC_REQ\t0x0000\n#define RTW_IEEE80211_STYPE_ASSOC_RESP\t0x0010\n#define RTW_IEEE80211_STYPE_REASSOC_REQ\t0x0020\n#define RTW_IEEE80211_STYPE_REASSOC_RESP\t0x0030\n#define RTW_IEEE80211_STYPE_PROBE_REQ\t0x0040\n#define RTW_IEEE80211_STYPE_PROBE_RESP\t0x0050\n#define RTW_IEEE80211_STYPE_BEACON\t\t0x0080\n#define RTW_IEEE80211_STYPE_ATIM\t\t0x0090\n#define RTW_IEEE80211_STYPE_DISASSOC\t0x00A0\n#define RTW_IEEE80211_STYPE_AUTH\t\t0x00B0\n#define RTW_IEEE80211_STYPE_DEAUTH\t\t0x00C0\n#define RTW_IEEE80211_STYPE_ACTION\t\t0x00D0\n\n/* control */\n#define RTW_IEEE80211_STYPE_CTL_EXT\t\t0x0060\n#define RTW_IEEE80211_STYPE_BACK_REQ\t\t0x0080\n#define RTW_IEEE80211_STYPE_BACK\t\t0x0090\n#define RTW_IEEE80211_STYPE_PSPOLL\t\t0x00A0\n#define RTW_IEEE80211_STYPE_RTS\t\t0x00B0\n#define RTW_IEEE80211_STYPE_CTS\t\t0x00C0\n#define RTW_IEEE80211_STYPE_ACK\t\t0x00D0\n#define RTW_IEEE80211_STYPE_CFEND\t\t0x00E0\n#define RTW_IEEE80211_STYPE_CFENDACK\t\t0x00F0\n\n/* data */\n#define RTW_IEEE80211_STYPE_DATA\t\t0x0000\n#define RTW_IEEE80211_STYPE_DATA_CFACK\t0x0010\n#define RTW_IEEE80211_STYPE_DATA_CFPOLL\t0x0020\n#define RTW_IEEE80211_STYPE_DATA_CFACKPOLL\t0x0030\n#define RTW_IEEE80211_STYPE_NULLFUNC\t0x0040\n#define RTW_IEEE80211_STYPE_CFACK\t\t0x0050\n#define RTW_IEEE80211_STYPE_CFPOLL\t\t0x0060\n#define RTW_IEEE80211_STYPE_CFACKPOLL\t0x0070\n#define RTW_IEEE80211_STYPE_QOS_DATA\t\t0x0080\n#define RTW_IEEE80211_STYPE_QOS_DATA_CFACK\t\t0x0090\n#define RTW_IEEE80211_STYPE_QOS_DATA_CFPOLL\t\t0x00A0\n#define RTW_IEEE80211_STYPE_QOS_DATA_CFACKPOLL\t0x00B0\n#define RTW_IEEE80211_STYPE_QOS_NULLFUNC\t0x00C0\n#define RTW_IEEE80211_STYPE_QOS_CFACK\t\t0x00D0\n#define RTW_IEEE80211_STYPE_QOS_CFPOLL\t\t0x00E0\n#define RTW_IEEE80211_STYPE_QOS_CFACKPOLL\t0x00F0\n\n/* sequence control field */\n#define RTW_IEEE80211_SCTL_FRAG\t0x000F\n#define RTW_IEEE80211_SCTL_SEQ\t0xFFF0\n\n\n#define RTW_ERP_INFO_NON_ERP_PRESENT BIT(0)\n#define RTW_ERP_INFO_USE_PROTECTION BIT(1)\n#define RTW_ERP_INFO_BARKER_PREAMBLE_MODE BIT(2)\n\n/* QoS,QOS */\n#define NORMAL_ACK\t\t\t0\n#define NO_ACK\t\t\t\t1\n#define NON_EXPLICIT_ACK\t2\n#define BLOCK_ACK\t\t\t3\n\n#ifndef ETH_P_PAE\n\t#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */\n#endif /* ETH_P_PAE */\n\n#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */\n\n#define ETH_P_ECONET\t0x0018\n\n#ifndef ETH_P_80211_RAW\n\t#define ETH_P_80211_RAW (ETH_P_ECONET + 1)\n#endif\n\n/* IEEE 802.11 defines */\n\n#define P80211_OUI_LEN 3\n\n#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)\n\nstruct ieee80211_snap_hdr {\n\n\tu8    dsap;   /* always 0xAA */\n\tu8    ssap;   /* always 0xAA */\n\tu8    ctrl;   /* always 0x03 */\n\tu8    oui[P80211_OUI_LEN];    /* organizational universal id */\n\n} __attribute__((packed));\n\n#endif\n\n#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)\n\n#define WLAN_FC_GET_TYPE(fc) ((fc) & RTW_IEEE80211_FCTL_FTYPE)\n#define WLAN_FC_GET_STYPE(fc) ((fc) & RTW_IEEE80211_FCTL_STYPE)\n\n#define WLAN_QC_GET_TID(qc) ((qc) & 0x0f)\n\n#define WLAN_GET_SEQ_FRAG(seq) ((seq) & RTW_IEEE80211_SCTL_FRAG)\n#define WLAN_GET_SEQ_SEQ(seq)  ((seq) & RTW_IEEE80211_SCTL_SEQ)\n\n/* Authentication algorithms */\n#define WLAN_AUTH_OPEN 0\n#define WLAN_AUTH_SHARED_KEY 1\n#define WLAN_AUTH_SAE 3\n\n#define WLAN_AUTH_CHALLENGE_LEN 128\n\n#define WLAN_CAPABILITY_BSS (1<<0)\n#define WLAN_CAPABILITY_IBSS (1<<1)\n#define WLAN_CAPABILITY_CF_POLLABLE (1<<2)\n#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3)\n#define WLAN_CAPABILITY_PRIVACY (1<<4)\n#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5)\n#define WLAN_CAPABILITY_PBCC (1<<6)\n#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7)\n#define WLAN_CAPABILITY_SHORT_SLOT (1<<10)\n\n/* Status codes */\n#define WLAN_STATUS_SUCCESS 0\n#define WLAN_STATUS_UNSPECIFIED_FAILURE 1\n#define WLAN_STATUS_CAPS_UNSUPPORTED 10\n#define WLAN_STATUS_REASSOC_NO_ASSOC 11\n#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12\n#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13\n#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14\n#define WLAN_STATUS_CHALLENGE_FAIL 15\n#define WLAN_STATUS_AUTH_TIMEOUT 16\n#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17\n#define WLAN_STATUS_ASSOC_DENIED_RATES 18\n/* 802.11b */\n#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19\n#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20\n#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21\n\n/* Reason codes */\n#define WLAN_REASON_UNSPECIFIED 1\n#define WLAN_REASON_PREV_AUTH_NOT_VALID 2\n#define WLAN_REASON_DEAUTH_LEAVING 3\n#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4\n#define WLAN_REASON_DISASSOC_AP_BUSY 5\n#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6\n#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7\n#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8\n#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9\n#define WLAN_REASON_MESH_PEER_CANCELED 52\n#define WLAN_REASON_MESH_MAX_PEERS 53\n#define WLAN_REASON_MESH_CONFIG 54\n#define WLAN_REASON_MESH_CLOSE 55\n#define WLAN_REASON_MESH_MAX_RETRIES 56 \n#define WLAN_REASON_MESH_CONFIRM_TIMEOUT 57\n#define WLAN_REASON_MESH_INVALID_GTK 58\n#define WLAN_REASON_MESH_INCONSISTENT_PARAM 59\n#define WLAN_REASON_MESH_INVALID_SECURITY 60\n#define WLAN_REASON_MESH_PATH_NOPROXY 61\n#define WLAN_REASON_MESH_PATH_NOFORWARD 62\n#define WLAN_REASON_MESH_PATH_DEST_UNREACHABLE 63\n#define WLAN_REASON_MAC_EXISTS_IN_MBSS 64\n#define WLAN_REASON_MESH_CHAN_REGULATORY 65\n#define WLAN_REASON_MESH_CHAN 66\n#define WLAN_REASON_SA_QUERY_TIMEOUT 65532\n#define WLAN_REASON_ACTIVE_ROAM 65533\n#define WLAN_REASON_JOIN_WRONG_CHANNEL       65534\n#define WLAN_REASON_EXPIRATION_CHK 65535\n\n#define WLAN_REASON_IS_PRIVATE(reason) ( \\\n\treason == WLAN_REASON_EXPIRATION_CHK \\\n\t|| reason == WLAN_REASON_JOIN_WRONG_CHANNEL \\\n\t|| reason == WLAN_REASON_ACTIVE_ROAM \\\n\t|| reason == WLAN_REASON_SA_QUERY_TIMEOUT \\\n\t)\n\n/* Information Element IDs */\n#define WLAN_EID_SSID 0\n#define WLAN_EID_SUPP_RATES 1\n#define WLAN_EID_FH_PARAMS 2\n#define WLAN_EID_DS_PARAMS 3\n#define WLAN_EID_CF_PARAMS 4\n#define WLAN_EID_TIM 5\n#define WLAN_EID_IBSS_PARAMS 6\n#define WLAN_EID_CHALLENGE 16\n/* EIDs defined by IEEE 802.11h - START */\n#define WLAN_EID_PWR_CONSTRAINT 32\n#define WLAN_EID_PWR_CAPABILITY 33\n#define WLAN_EID_TPC_REQUEST 34\n#define WLAN_EID_TPC_REPORT 35\n#define WLAN_EID_SUPPORTED_CHANNELS 36\n#define WLAN_EID_CHANNEL_SWITCH 37\n#define WLAN_EID_MEASURE_REQUEST 38\n#define WLAN_EID_MEASURE_REPORT 39\n#define WLAN_EID_QUITE 40\n#define WLAN_EID_IBSS_DFS 41\n/* EIDs defined by IEEE 802.11h - END */\n#define WLAN_EID_ERP_INFO 42\n#define WLAN_EID_HT_CAP 45\n#define WLAN_EID_RSN 48\n#define WLAN_EID_EXT_SUPP_RATES 50\n#define WLAN_EID_MOBILITY_DOMAIN 54\n#define WLAN_EID_FAST_BSS_TRANSITION 55\n#define WLAN_EID_TIMEOUT_INTERVAL 56\n#define WLAN_EID_RIC_DATA 57\n#define WLAN_EID_HT_OPERATION 61\n#define WLAN_EID_SECONDARY_CHANNEL_OFFSET 62\n#define WLAN_EID_20_40_BSS_COEXISTENCE 72\n#define WLAN_EID_20_40_BSS_INTOLERANT 73\n#define WLAN_EID_OVERLAPPING_BSS_SCAN_PARAMS 74\n#define WLAN_EID_MMIE 76\n#define WLAN_EID_MESH_CONFIG 113\n#define WLAN_EID_MESH_ID 114\n#define WLAN_EID_MPM 117\n#define\tWLAN_EID_RANN 126\n#define\tWLAN_EID_PREQ 130\n#define\tWLAN_EID_PREP 131\n#define\tWLAN_EID_PERR 132\n#define WLAN_EID_AMPE 139\n#define WLAN_EID_MIC 140\n#define WLAN_EID_VENDOR_SPECIFIC 221\n#define WLAN_EID_GENERIC (WLAN_EID_VENDOR_SPECIFIC)\n#define WLAN_EID_VHT_CAPABILITY 191\n#define WLAN_EID_VHT_OPERATION 192\n#define WLAN_EID_VHT_OP_MODE_NOTIFY 199\n\n#define IEEE80211_MGMT_HDR_LEN 24\n#define IEEE80211_DATA_HDR3_LEN 24\n#define IEEE80211_DATA_HDR4_LEN 30\n\n\n#define IEEE80211_STATMASK_SIGNAL (1<<0)\n#define IEEE80211_STATMASK_RSSI (1<<1)\n#define IEEE80211_STATMASK_NOISE (1<<2)\n#define IEEE80211_STATMASK_RATE (1<<3)\n#define IEEE80211_STATMASK_WEMASK 0x7\n\n\n#define IEEE80211_CCK_MODULATION    (1<<0)\n#define IEEE80211_OFDM_MODULATION   (1<<1)\n\n#define IEEE80211_24GHZ_BAND     (1<<0)\n#define IEEE80211_52GHZ_BAND     (1<<1)\n\n#define IEEE80211_CCK_RATE_LEN\t\t4\n#define IEEE80211_NUM_OFDM_RATESLEN\t8\n\n\n#define IEEE80211_CCK_RATE_1MB\t\t        0x02\n#define IEEE80211_CCK_RATE_2MB\t\t        0x04\n#define IEEE80211_CCK_RATE_5MB\t\t        0x0B\n#define IEEE80211_CCK_RATE_11MB\t\t        0x16\n#define IEEE80211_OFDM_RATE_LEN\t\t8\n#define IEEE80211_OFDM_RATE_6MB\t\t        0x0C\n#define IEEE80211_OFDM_RATE_9MB\t\t        0x12\n#define IEEE80211_OFDM_RATE_12MB\t\t0x18\n#define IEEE80211_OFDM_RATE_18MB\t\t0x24\n#define IEEE80211_OFDM_RATE_24MB\t\t0x30\n#define IEEE80211_OFDM_RATE_36MB\t\t0x48\n#define IEEE80211_OFDM_RATE_48MB\t\t0x60\n#define IEEE80211_OFDM_RATE_54MB\t\t0x6C\n#define IEEE80211_PBCC_RATE_22MB\t\t0x2c\n#define IEEE80211_PBCC_RATE_33MB\t\t0x42\n#define IEEE80211_BASIC_RATE_MASK\t\t0x80\n\n#define IEEE80211_CCK_RATE_1MB_MASK\t\t(1<<0)\n#define IEEE80211_CCK_RATE_2MB_MASK\t\t(1<<1)\n#define IEEE80211_CCK_RATE_5MB_MASK\t\t(1<<2)\n#define IEEE80211_CCK_RATE_11MB_MASK\t\t(1<<3)\n#define IEEE80211_OFDM_RATE_6MB_MASK\t\t(1<<4)\n#define IEEE80211_OFDM_RATE_9MB_MASK\t\t(1<<5)\n#define IEEE80211_OFDM_RATE_12MB_MASK\t\t(1<<6)\n#define IEEE80211_OFDM_RATE_18MB_MASK\t\t(1<<7)\n#define IEEE80211_OFDM_RATE_24MB_MASK\t\t(1<<8)\n#define IEEE80211_OFDM_RATE_36MB_MASK\t\t(1<<9)\n#define IEEE80211_OFDM_RATE_48MB_MASK\t\t(1<<10)\n#define IEEE80211_OFDM_RATE_54MB_MASK\t\t(1<<11)\n\n#define IEEE80211_CCK_RATES_MASK\t        0x0000000F\n#define IEEE80211_CCK_BASIC_RATES_MASK\t(IEEE80211_CCK_RATE_1MB_MASK | \\\n\t\tIEEE80211_CCK_RATE_2MB_MASK)\n#define IEEE80211_CCK_DEFAULT_RATES_MASK\t(IEEE80211_CCK_BASIC_RATES_MASK | \\\n\t\tIEEE80211_CCK_RATE_5MB_MASK | \\\n\t\tIEEE80211_CCK_RATE_11MB_MASK)\n\n#define IEEE80211_OFDM_RATES_MASK\t\t0x00000FF0\n#define IEEE80211_OFDM_BASIC_RATES_MASK\t(IEEE80211_OFDM_RATE_6MB_MASK | \\\n\t\tIEEE80211_OFDM_RATE_12MB_MASK | \\\n\t\tIEEE80211_OFDM_RATE_24MB_MASK)\n#define IEEE80211_OFDM_DEFAULT_RATES_MASK\t(IEEE80211_OFDM_BASIC_RATES_MASK | \\\n\t\tIEEE80211_OFDM_RATE_9MB_MASK  | \\\n\t\tIEEE80211_OFDM_RATE_18MB_MASK | \\\n\t\tIEEE80211_OFDM_RATE_36MB_MASK | \\\n\t\tIEEE80211_OFDM_RATE_48MB_MASK | \\\n\t\tIEEE80211_OFDM_RATE_54MB_MASK)\n#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \\\n\t\t\t\t      IEEE80211_CCK_DEFAULT_RATES_MASK)\n\n#define IEEE80211_NUM_OFDM_RATES\t    8\n#define IEEE80211_NUM_CCK_RATES\t            4\n#define IEEE80211_OFDM_SHIFT_MASK_A         4\n\n\nenum MGN_RATE {\n\tMGN_1M\t\t= 0x02,\n\tMGN_2M\t\t= 0x04,\n\tMGN_5_5M\t= 0x0B,\n\tMGN_6M\t\t= 0x0C,\n\tMGN_9M\t\t= 0x12,\n\tMGN_11M\t= 0x16,\n\tMGN_12M\t= 0x18,\n\tMGN_18M\t= 0x24,\n\tMGN_24M\t= 0x30,\n\tMGN_36M\t= 0x48,\n\tMGN_48M\t= 0x60,\n\tMGN_54M\t= 0x6C,\n\tMGN_MCS32\t= 0x7F,\n\tMGN_MCS0,\n\tMGN_MCS1,\n\tMGN_MCS2,\n\tMGN_MCS3,\n\tMGN_MCS4,\n\tMGN_MCS5,\n\tMGN_MCS6,\n\tMGN_MCS7,\n\tMGN_MCS8,\n\tMGN_MCS9,\n\tMGN_MCS10,\n\tMGN_MCS11,\n\tMGN_MCS12,\n\tMGN_MCS13,\n\tMGN_MCS14,\n\tMGN_MCS15,\n\tMGN_MCS16,\n\tMGN_MCS17,\n\tMGN_MCS18,\n\tMGN_MCS19,\n\tMGN_MCS20,\n\tMGN_MCS21,\n\tMGN_MCS22,\n\tMGN_MCS23,\n\tMGN_MCS24,\n\tMGN_MCS25,\n\tMGN_MCS26,\n\tMGN_MCS27,\n\tMGN_MCS28,\n\tMGN_MCS29,\n\tMGN_MCS30,\n\tMGN_MCS31,\n\tMGN_VHT1SS_MCS0,\n\tMGN_VHT1SS_MCS1,\n\tMGN_VHT1SS_MCS2,\n\tMGN_VHT1SS_MCS3,\n\tMGN_VHT1SS_MCS4,\n\tMGN_VHT1SS_MCS5,\n\tMGN_VHT1SS_MCS6,\n\tMGN_VHT1SS_MCS7,\n\tMGN_VHT1SS_MCS8,\n\tMGN_VHT1SS_MCS9,\n\tMGN_VHT2SS_MCS0,\n\tMGN_VHT2SS_MCS1,\n\tMGN_VHT2SS_MCS2,\n\tMGN_VHT2SS_MCS3,\n\tMGN_VHT2SS_MCS4,\n\tMGN_VHT2SS_MCS5,\n\tMGN_VHT2SS_MCS6,\n\tMGN_VHT2SS_MCS7,\n\tMGN_VHT2SS_MCS8,\n\tMGN_VHT2SS_MCS9,\n\tMGN_VHT3SS_MCS0,\n\tMGN_VHT3SS_MCS1,\n\tMGN_VHT3SS_MCS2,\n\tMGN_VHT3SS_MCS3,\n\tMGN_VHT3SS_MCS4,\n\tMGN_VHT3SS_MCS5,\n\tMGN_VHT3SS_MCS6,\n\tMGN_VHT3SS_MCS7,\n\tMGN_VHT3SS_MCS8,\n\tMGN_VHT3SS_MCS9,\n\tMGN_VHT4SS_MCS0,\n\tMGN_VHT4SS_MCS1,\n\tMGN_VHT4SS_MCS2,\n\tMGN_VHT4SS_MCS3,\n\tMGN_VHT4SS_MCS4,\n\tMGN_VHT4SS_MCS5,\n\tMGN_VHT4SS_MCS6,\n\tMGN_VHT4SS_MCS7,\n\tMGN_VHT4SS_MCS8,\n\tMGN_VHT4SS_MCS9,\n\tMGN_UNKNOWN\n};\n\n#define IS_HT_RATE(_rate)\t((_rate) >= MGN_MCS0 && (_rate) <= MGN_MCS31)\n#define IS_VHT_RATE(_rate)\t((_rate) >= MGN_VHT1SS_MCS0 && (_rate) <= MGN_VHT4SS_MCS9)\n#define IS_CCK_RATE(_rate)\t((_rate) == MGN_1M || (_rate) == MGN_2M || (_rate) == MGN_5_5M || (_rate) == MGN_11M)\n#define IS_OFDM_RATE(_rate)\t((_rate) >= MGN_6M && (_rate) <= MGN_54M  && (_rate) != MGN_11M)\n\n#define IS_HT1SS_RATE(_rate) ((_rate) >= MGN_MCS0 && (_rate) <= MGN_MCS7)\n#define IS_HT2SS_RATE(_rate) ((_rate) >= MGN_MCS8 && (_rate) <= MGN_MCS15)\n#define IS_HT3SS_RATE(_rate) ((_rate) >= MGN_MCS16 && (_rate) <= MGN_MCS23)\n#define IS_HT4SS_RATE(_rate) ((_rate) >= MGN_MCS24 && (_rate) <= MGN_MCS31)\n\n#define IS_VHT1SS_RATE(_rate) ((_rate) >= MGN_VHT1SS_MCS0 && (_rate) <= MGN_VHT1SS_MCS9)\n#define IS_VHT2SS_RATE(_rate) ((_rate) >= MGN_VHT2SS_MCS0 && (_rate) <= MGN_VHT2SS_MCS9)\n#define IS_VHT3SS_RATE(_rate) ((_rate) >= MGN_VHT3SS_MCS0 && (_rate) <= MGN_VHT3SS_MCS9)\n#define IS_VHT4SS_RATE(_rate) ((_rate) >= MGN_VHT4SS_MCS0 && (_rate) <= MGN_VHT4SS_MCS9)\n\n#define IS_1T_RATE(_rate)\t(IS_CCK_RATE((_rate)) || IS_OFDM_RATE((_rate)) || IS_HT1SS_RATE((_rate)) || IS_VHT1SS_RATE((_rate)))\n#define IS_2T_RATE(_rate)\t(IS_HT2SS_RATE((_rate)) || IS_VHT2SS_RATE((_rate)))\n#define IS_3T_RATE(_rate)\t(IS_HT3SS_RATE((_rate)) || IS_VHT3SS_RATE((_rate)))\n#define IS_4T_RATE(_rate)\t(IS_HT4SS_RATE((_rate)) || IS_VHT4SS_RATE((_rate)))\n\n#define MGN_RATE_STR(_rate) \\\n\t(_rate == MGN_1M) ? \"CCK_1M\" : \\\n\t(_rate == MGN_2M) ? \"CCK_2M\" : \\\n\t(_rate == MGN_5_5M) ? \"CCK_5.5M\" : \\\n\t(_rate == MGN_11M) ? \"CCK_11M\" : \\\n\t(_rate == MGN_6M) ? \"OFDM_6M\" : \\\n\t(_rate == MGN_9M) ? \"OFDM_9M\" : \\\n\t(_rate == MGN_12M) ? \"OFDM_12M\" : \\\n\t(_rate == MGN_18M) ? \"OFDM_18M\" : \\\n\t(_rate == MGN_24M) ? \"OFDM_24M\" : \\\n\t(_rate == MGN_36M) ? \"OFDM_36M\" : \\\n\t(_rate == MGN_48M) ? \"OFDM_48M\" : \\\n\t(_rate == MGN_54M) ? \"OFDM_54M\" : \\\n\t(_rate == MGN_MCS32) ? \"MCS32\" : \\\n\t(_rate == MGN_MCS0) ? \"MCS0\" : \\\n\t(_rate == MGN_MCS1) ? \"MCS1\" : \\\n\t(_rate == MGN_MCS2) ? \"MCS2\" : \\\n\t(_rate == MGN_MCS3) ? \"MCS3\" : \\\n\t(_rate == MGN_MCS4) ? \"MCS4\" : \\\n\t(_rate == MGN_MCS5) ? \"MCS5\" : \\\n\t(_rate == MGN_MCS6) ? \"MCS6\" : \\\n\t(_rate == MGN_MCS7) ? \"MCS7\" : \\\n\t(_rate == MGN_MCS8) ? \"MCS8\" : \\\n\t(_rate == MGN_MCS9) ? \"MCS9\" : \\\n\t(_rate == MGN_MCS10) ? \"MCS10\" : \\\n\t(_rate == MGN_MCS11) ? \"MCS11\" : \\\n\t(_rate == MGN_MCS12) ? \"MCS12\" : \\\n\t(_rate == MGN_MCS13) ? \"MCS13\" : \\\n\t(_rate == MGN_MCS14) ? \"MCS14\" : \\\n\t(_rate == MGN_MCS15) ? \"MCS15\" : \\\n\t(_rate == MGN_MCS16) ? \"MCS16\" : \\\n\t(_rate == MGN_MCS17) ? \"MCS17\" : \\\n\t(_rate == MGN_MCS18) ? \"MCS18\" : \\\n\t(_rate == MGN_MCS19) ? \"MCS19\" : \\\n\t(_rate == MGN_MCS20) ? \"MCS20\" : \\\n\t(_rate == MGN_MCS21) ? \"MCS21\" : \\\n\t(_rate == MGN_MCS22) ? \"MCS22\" : \\\n\t(_rate == MGN_MCS23) ? \"MCS23\" : \\\n\t(_rate == MGN_MCS24) ? \"MCS24\" : \\\n\t(_rate == MGN_MCS25) ? \"MCS25\" : \\\n\t(_rate == MGN_MCS26) ? \"MCS26\" : \\\n\t(_rate == MGN_MCS27) ? \"MCS27\" : \\\n\t(_rate == MGN_MCS28) ? \"MCS28\" : \\\n\t(_rate == MGN_MCS29) ? \"MCS29\" : \\\n\t(_rate == MGN_MCS30) ? \"MCS30\" : \\\n\t(_rate == MGN_MCS31) ? \"MCS31\" : \\\n\t(_rate == MGN_VHT1SS_MCS0) ? \"VHT1SMCS0\" : \\\n\t(_rate == MGN_VHT1SS_MCS1) ? \"VHT1SMCS1\" : \\\n\t(_rate == MGN_VHT1SS_MCS2) ? \"VHT1SMCS2\" : \\\n\t(_rate == MGN_VHT1SS_MCS3) ? \"VHT1SMCS3\" : \\\n\t(_rate == MGN_VHT1SS_MCS4) ? \"VHT1SMCS4\" : \\\n\t(_rate == MGN_VHT1SS_MCS5) ? \"VHT1SMCS5\" : \\\n\t(_rate == MGN_VHT1SS_MCS6) ? \"VHT1SMCS6\" : \\\n\t(_rate == MGN_VHT1SS_MCS7) ? \"VHT1SMCS7\" : \\\n\t(_rate == MGN_VHT1SS_MCS8) ? \"VHT1SMCS8\" : \\\n\t(_rate == MGN_VHT1SS_MCS9) ? \"VHT1SMCS9\" : \\\n\t(_rate == MGN_VHT2SS_MCS0) ? \"VHT2SMCS0\" : \\\n\t(_rate == MGN_VHT2SS_MCS1) ? \"VHT2SMCS1\" : \\\n\t(_rate == MGN_VHT2SS_MCS2) ? \"VHT2SMCS2\" : \\\n\t(_rate == MGN_VHT2SS_MCS3) ? \"VHT2SMCS3\" : \\\n\t(_rate == MGN_VHT2SS_MCS4) ? \"VHT2SMCS4\" : \\\n\t(_rate == MGN_VHT2SS_MCS5) ? \"VHT2SMCS5\" : \\\n\t(_rate == MGN_VHT2SS_MCS6) ? \"VHT2SMCS6\" : \\\n\t(_rate == MGN_VHT2SS_MCS7) ? \"VHT2SMCS7\" : \\\n\t(_rate == MGN_VHT2SS_MCS8) ? \"VHT2SMCS8\" : \\\n\t(_rate == MGN_VHT2SS_MCS9) ? \"VHT2SMCS9\" : \\\n\t(_rate == MGN_VHT3SS_MCS0) ? \"VHT3SMCS0\" : \\\n\t(_rate == MGN_VHT3SS_MCS1) ? \"VHT3SMCS1\" : \\\n\t(_rate == MGN_VHT3SS_MCS2) ? \"VHT3SMCS2\" : \\\n\t(_rate == MGN_VHT3SS_MCS3) ? \"VHT3SMCS3\" : \\\n\t(_rate == MGN_VHT3SS_MCS4) ? \"VHT3SMCS4\" : \\\n\t(_rate == MGN_VHT3SS_MCS5) ? \"VHT3SMCS5\" : \\\n\t(_rate == MGN_VHT3SS_MCS6) ? \"VHT3SMCS6\" : \\\n\t(_rate == MGN_VHT3SS_MCS7) ? \"VHT3SMCS7\" : \\\n\t(_rate == MGN_VHT3SS_MCS8) ? \"VHT3SMCS8\" : \\\n\t(_rate == MGN_VHT3SS_MCS9) ? \"VHT3SMCS9\" : \\\n\t(_rate == MGN_VHT4SS_MCS0) ? \"VHT4SMCS0\" : \\\n\t(_rate == MGN_VHT4SS_MCS1) ? \"VHT4SMCS1\" : \\\n\t(_rate == MGN_VHT4SS_MCS2) ? \"VHT4SMCS2\" : \\\n\t(_rate == MGN_VHT4SS_MCS3) ? \"VHT4SMCS3\" : \\\n\t(_rate == MGN_VHT4SS_MCS4) ? \"VHT4SMCS4\" : \\\n\t(_rate == MGN_VHT4SS_MCS5) ? \"VHT4SMCS5\" : \\\n\t(_rate == MGN_VHT4SS_MCS6) ? \"VHT4SMCS6\" : \\\n\t(_rate == MGN_VHT4SS_MCS7) ? \"VHT4SMCS7\" : \\\n\t(_rate == MGN_VHT4SS_MCS8) ? \"VHT4SMCS8\" : \\\n\t(_rate == MGN_VHT4SS_MCS9) ? \"VHT4SMCS9\" : \"UNKNOWN\"\n\ntypedef enum _RATE_SECTION {\n\tCCK = 0,\n\tOFDM = 1,\n\tHT_MCS0_MCS7 = 2,\n\tHT_MCS8_MCS15 = 3,\n\tHT_MCS16_MCS23 = 4,\n\tHT_MCS24_MCS31 = 5,\n\tHT_1SS = HT_MCS0_MCS7,\n\tHT_2SS = HT_MCS8_MCS15,\n\tHT_3SS = HT_MCS16_MCS23,\n\tHT_4SS = HT_MCS24_MCS31,\n\tVHT_1SSMCS0_1SSMCS9 = 6,\n\tVHT_2SSMCS0_2SSMCS9 = 7,\n\tVHT_3SSMCS0_3SSMCS9 = 8,\n\tVHT_4SSMCS0_4SSMCS9 = 9,\n\tVHT_1SS = VHT_1SSMCS0_1SSMCS9,\n\tVHT_2SS = VHT_2SSMCS0_2SSMCS9,\n\tVHT_3SS = VHT_3SSMCS0_3SSMCS9,\n\tVHT_4SS = VHT_4SSMCS0_4SSMCS9,\n\tRATE_SECTION_NUM,\n} RATE_SECTION;\n\nconst char *rate_section_str(u8 section);\n\n#define IS_CCK_RATE_SECTION(section) ((section) == CCK)\n#define IS_OFDM_RATE_SECTION(section) ((section) == OFDM)\n#define IS_HT_RATE_SECTION(section) ((section) >= HT_1SS && (section) <= HT_4SS)\n#define IS_VHT_RATE_SECTION(section) ((section) >= VHT_1SS && (section) <= VHT_4SS)\n\n#define IS_1T_RATE_SECTION(section) ((section) == CCK || (section) == OFDM || (section) == HT_1SS || (section) == VHT_1SS)\n#define IS_2T_RATE_SECTION(section) ((section) == HT_2SS || (section) == VHT_2SS)\n#define IS_3T_RATE_SECTION(section) ((section) == HT_3SS || (section) == VHT_3SS)\n#define IS_4T_RATE_SECTION(section) ((section) == HT_4SS || (section) == VHT_4SS)\n\nextern u8 mgn_rates_cck[];\nextern u8 mgn_rates_ofdm[];\nextern u8 mgn_rates_mcs0_7[];\nextern u8 mgn_rates_mcs8_15[];\nextern u8 mgn_rates_mcs16_23[];\nextern u8 mgn_rates_mcs24_31[];\nextern u8 mgn_rates_vht1ss[];\nextern u8 mgn_rates_vht2ss[];\nextern u8 mgn_rates_vht3ss[];\nextern u8 mgn_rates_vht4ss[];\n\nstruct rate_section_ent {\n\tu8 tx_num; /* value of RF_TX_NUM */\n\tu8 rate_num;\n\tu8 *rates;\n};\n\nextern struct rate_section_ent rates_by_sections[];\n\n#define rate_section_to_tx_num(section) (rates_by_sections[(section)].tx_num)\n#define rate_section_rate_num(section) (rates_by_sections[(section)].rate_num)\n\n/* NOTE: This data is for statistical purposes; not all hardware provides this\n *       information for frames received.  Not setting these will not cause\n *       any adverse affects. */\nstruct ieee80211_rx_stats {\n\t/* u32 mac_time[2]; */\n\ts8 rssi;\n\tu8 signal;\n\tu8 noise;\n\tu8 received_channel;\n\tu16 rate; /* in 100 kbps */\n\t/* u8 control; */\n\tu8 mask;\n\tu8 freq;\n\tu16 len;\n};\n\n/* IEEE 802.11 requires that STA supports concurrent reception of at least\n * three fragmented frames. This define can be increased to support more\n * concurrent frames, but it should be noted that each entry can consume about\n * 2 kB of RAM and increasing cache size will slow down frame reassembly. */\n#define IEEE80211_FRAG_CACHE_LEN 4\n\nstruct ieee80211_frag_entry {\n\tu32 first_frag_time;\n\tuint seq;\n\tuint last_frag;\n\tuint qos;   /* jackson */\n\tuint tid;\t/* jackson */\n\tstruct sk_buff *skb;\n\tu8 src_addr[ETH_ALEN];\n\tu8 dst_addr[ETH_ALEN];\n};\n\n#ifndef PLATFORM_FREEBSD /* Baron BSD has already defined */\nstruct ieee80211_stats {\n\tuint tx_unicast_frames;\n\tuint tx_multicast_frames;\n\tuint tx_fragments;\n\tuint tx_unicast_octets;\n\tuint tx_multicast_octets;\n\tuint tx_deferred_transmissions;\n\tuint tx_single_retry_frames;\n\tuint tx_multiple_retry_frames;\n\tuint tx_retry_limit_exceeded;\n\tuint tx_discards;\n\tuint rx_unicast_frames;\n\tuint rx_multicast_frames;\n\tuint rx_fragments;\n\tuint rx_unicast_octets;\n\tuint rx_multicast_octets;\n\tuint rx_fcs_errors;\n\tuint rx_discards_no_buffer;\n\tuint tx_discards_wrong_sa;\n\tuint rx_discards_undecryptable;\n\tuint rx_message_in_msg_fragments;\n\tuint rx_message_in_bad_msg_fragments;\n};\n#endif /* PLATFORM_FREEBSD */\nstruct ieee80211_softmac_stats {\n\tuint rx_ass_ok;\n\tuint rx_ass_err;\n\tuint rx_probe_rq;\n\tuint tx_probe_rs;\n\tuint tx_beacons;\n\tuint rx_auth_rq;\n\tuint rx_auth_rs_ok;\n\tuint rx_auth_rs_err;\n\tuint tx_auth_rq;\n\tuint no_auth_rs;\n\tuint no_ass_rs;\n\tuint tx_ass_rq;\n\tuint rx_ass_rq;\n\tuint tx_probe_rq;\n\tuint reassoc;\n\tuint swtxstop;\n\tuint swtxawake;\n};\n\n#define SEC_KEY_1         (1<<0)\n#define SEC_KEY_2         (1<<1)\n#define SEC_KEY_3         (1<<2)\n#define SEC_KEY_4         (1<<3)\n#define SEC_ACTIVE_KEY    (1<<4)\n#define SEC_AUTH_MODE     (1<<5)\n#define SEC_UNICAST_GROUP (1<<6)\n#define SEC_LEVEL         (1<<7)\n#define SEC_ENABLED       (1<<8)\n\n#define SEC_LEVEL_0      0 /* None */\n#define SEC_LEVEL_1      1 /* WEP 40 and 104 bit */\n#define SEC_LEVEL_2      2 /* Level 1 + TKIP */\n#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */\n#define SEC_LEVEL_3      4 /* Level 2 + CCMP */\n\n#define WEP_KEYS 4\n#define WEP_KEY_LEN 13\n#define BIP_MAX_KEYID 5\n#define BIP_AAD_SIZE  20\n\n#if defined(PLATFORM_LINUX)\nstruct ieee80211_security {\n\tu16 active_key:2,\n\t    enabled:1,\n\t    auth_mode:2,\n\t    auth_algo:4,\n\t    unicast_uses_group:1;\n\tu8 key_sizes[WEP_KEYS];\n\tu8 keys[WEP_KEYS][WEP_KEY_LEN];\n\tu8 level;\n\tu16 flags;\n} __attribute__((packed));\n\n#endif\n\n/*\n\n 802.11 data frame from AP\n\n      ,-------------------------------------------------------------------.\nBytes |  2   |  2   |    6    |    6    |    6    |  2   | 0..2312 |   4  |\n      |------|------|---------|---------|---------|------|---------|------|\nDesc. | ctrl | dura |  DA/RA  |   TA    |    SA   | Sequ |  frame  |  fcs |\n      |      | tion | (BSSID) |         |         | ence |  data   |      |\n      `-------------------------------------------------------------------'\n\nTotal: 28-2340 bytes\n\n*/\n\nstruct ieee80211_header_data {\n\tu16 frame_ctl;\n\tu16 duration_id;\n\tu8 addr1[6];\n\tu8 addr2[6];\n\tu8 addr3[6];\n\tu16 seq_ctrl;\n};\n\n#define BEACON_PROBE_SSID_ID_POSITION 12\n\n/* Management Frame Information Element Types */\n#define MFIE_TYPE_SSID       0\n#define MFIE_TYPE_RATES      1\n#define MFIE_TYPE_FH_SET     2\n#define MFIE_TYPE_DS_SET     3\n#define MFIE_TYPE_CF_SET     4\n#define MFIE_TYPE_TIM        5\n#define MFIE_TYPE_IBSS_SET   6\n#define MFIE_TYPE_CHALLENGE  16\n#define MFIE_TYPE_ERP        42\n#define MFIE_TYPE_RSN\t     48\n#define MFIE_TYPE_RATES_EX   50\n#define MFIE_TYPE_GENERIC    221\n\n#if defined(PLATFORM_LINUX)\nstruct ieee80211_info_element_hdr {\n\tu8 id;\n\tu8 len;\n} __attribute__((packed));\n\nstruct ieee80211_info_element {\n\tu8 id;\n\tu8 len;\n\tu8 data[0];\n} __attribute__((packed));\n#endif\n\n\n/*\n * These are the data types that can make up management packets\n *\n\tu16 auth_algorithm;\n\tu16 auth_sequence;\n\tu16 beacon_interval;\n\tu16 capability;\n\tu8 current_ap[ETH_ALEN];\n\tu16 listen_interval;\n\tstruct {\n\t\tu16 association_id:14, reserved:2;\n\t} __attribute__ ((packed));\n\tu32 time_stamp[2];\n\tu16 reason;\n\tu16 status;\n*/\n\n#define IEEE80211_DEFAULT_TX_ESSID \"Penguin\"\n#define IEEE80211_DEFAULT_BASIC_RATE 10\n\n\n#if defined(PLATFORM_LINUX)\nstruct ieee80211_authentication {\n\tstruct ieee80211_header_data header;\n\tu16 algorithm;\n\tu16 transaction;\n\tu16 status;\n\t/* struct ieee80211_info_element_hdr info_element; */\n} __attribute__((packed));\n\n\nstruct ieee80211_probe_response {\n\tstruct ieee80211_header_data header;\n\tu32 time_stamp[2];\n\tu16 beacon_interval;\n\tu16 capability;\n\tstruct ieee80211_info_element info_element;\n} __attribute__((packed));\n\nstruct ieee80211_probe_request {\n\tstruct ieee80211_header_data header;\n\t/*struct ieee80211_info_element info_element;*/\n} __attribute__((packed));\n\nstruct ieee80211_assoc_request_frame {\n\tstruct rtw_ieee80211_hdr_3addr header;\n\tu16 capability;\n\tu16 listen_interval;\n\t/* u8 current_ap[ETH_ALEN]; */\n\tstruct ieee80211_info_element_hdr info_element;\n} __attribute__((packed));\n\nstruct ieee80211_assoc_response_frame {\n\tstruct rtw_ieee80211_hdr_3addr header;\n\tu16 capability;\n\tu16 status;\n\tu16 aid;\n\t/*\tstruct ieee80211_info_element info_element;  supported rates  */\n} __attribute__((packed));\n#endif\n\nstruct ieee80211_txb {\n\tu8 nr_frags;\n\tu8 encrypted;\n\tu16 reserved;\n\tu16 frag_size;\n\tu16 payload_size;\n\tstruct sk_buff *fragments[0];\n};\n\n\n/* SWEEP TABLE ENTRIES NUMBER*/\n#define MAX_SWEEP_TAB_ENTRIES\t\t  42\n#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET  7\n/* MAX_RATES_LENGTH needs to be 12.  The spec says 8, and many APs\n * only use 8, and then use extended rates for the remaining supported\n * rates.  Other APs, however, stick all of their supported rates on the\n * main rates information element... */\n#define MAX_RATES_LENGTH                  ((u8)12)\n#define MAX_RATES_EX_LENGTH               ((u8)16)\n#define MAX_NETWORK_COUNT                  128\n#define IEEE80211_SOFTMAC_SCAN_TIME\t  400\n/* (HZ / 2) */\n#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2)\n\n#define CRC_LENGTH                 4U\n\n#define MAX_WPA_IE_LEN (256)\n#define MAX_WPS_IE_LEN (512)\n#define MAX_P2P_IE_LEN (256)\n#define MAX_WFD_IE_LEN (128)\n\n#define NETWORK_EMPTY_ESSID (1<<0)\n#define NETWORK_HAS_OFDM    (1<<1)\n#define NETWORK_HAS_CCK     (1<<2)\n\n#define IEEE80211_DTIM_MBCAST 4\n#define IEEE80211_DTIM_UCAST 2\n#define IEEE80211_DTIM_VALID 1\n#define IEEE80211_DTIM_INVALID 0\n\n#define IEEE80211_PS_DISABLED 0\n#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST\n#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST\n#define IW_ESSID_MAX_SIZE 32\n#if 0\nstruct ieee80211_network {\n\t/* These entries are used to identify a unique network */\n\tu8 bssid[ETH_ALEN];\n\tu8 channel;\n\t/* Ensure null-terminated for any debug msgs */\n\tu8 ssid[IW_ESSID_MAX_SIZE + 1];\n\tu8 ssid_len;\n\tu8\trssi;\t/* relative signal strength */\n\tu8\tsq;\t\t/* signal quality */\n\n\t/* These are network statistics */\n\t/* struct ieee80211_rx_stats stats; */\n\tu16 capability;\n\tu16\taid;\n\tu8 rates[MAX_RATES_LENGTH];\n\tu8 rates_len;\n\tu8 rates_ex[MAX_RATES_EX_LENGTH];\n\tu8 rates_ex_len;\n\n\tu8 edca_parmsets[18];\n\n\tu8 mode;\n\tu8 flags;\n\tu8 time_stamp[8];\n\tu16 beacon_interval;\n\tu16 listen_interval;\n\tu16 atim_window;\n\tu8 wpa_ie[MAX_WPA_IE_LEN];\n\tsize_t wpa_ie_len;\n\tu8 rsn_ie[MAX_WPA_IE_LEN];\n\tsize_t rsn_ie_len;\n\tu8 country[6];\n\tu8 dtim_period;\n\tu8 dtim_data;\n\tu8 power_constraint;\n\tu8 qosinfo;\n\tu8 qbssload[5];\n\tu8 network_type;\n\tint join_res;\n\tunsigned long\tlast_scanned;\n};\n#endif\n/*\njoin_res:\n-1: authentication fail\n-2: association fail\n> 0: TID\n*/\n\n#ifndef PLATFORM_FREEBSD /* Baron BSD has already defined */\n\nenum ieee80211_state {\n\n\t/* the card is not linked at all */\n\tIEEE80211_NOLINK = 0,\n\n\t/* IEEE80211_ASSOCIATING* are for BSS client mode\n\t * the driver shall not perform RX filtering unless\n\t * the state is LINKED.\n\t * The driver shall just check for the state LINKED and\n\t * defaults to NOLINK for ALL the other states (including\n\t * LINKED_SCANNING)\n\t */\n\n\t/* the association procedure will start (wq scheduling)*/\n\tIEEE80211_ASSOCIATING,\n\tIEEE80211_ASSOCIATING_RETRY,\n\n\t/* the association procedure is sending AUTH request*/\n\tIEEE80211_ASSOCIATING_AUTHENTICATING,\n\n\t/* the association procedure has successfully authentcated\n\t * and is sending association request\n\t */\n\tIEEE80211_ASSOCIATING_AUTHENTICATED,\n\n\t/* the link is ok. the card associated to a BSS or linked\n\t * to a ibss cell or acting as an AP and creating the bss\n\t */\n\tIEEE80211_LINKED,\n\n\t/* same as LINKED, but the driver shall apply RX filter\n\t * rules as we are in NO_LINK mode. As the card is still\n\t * logically linked, but it is doing a syncro site survey\n\t * then it will be back to LINKED state.\n\t */\n\tIEEE80211_LINKED_SCANNING,\n\n};\n#endif /* PLATFORM_FREEBSD */\n\n#define DEFAULT_MAX_SCAN_AGE (15 * HZ)\n#define DEFAULT_FTS 2346\n#define MAC_FMT \"%02x:%02x:%02x:%02x:%02x:%02x\"\n#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5]\n#define MAC_SFMT \"%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx\"\n#define MAC_SARG(x) ((u8*)(x)),((u8*)(x)) + 1,((u8*)(x)) + 2,((u8*)(x)) + 3,((u8*)(x)) + 4,((u8*)(x)) + 5\n#define IP_FMT \"%d.%d.%d.%d\"\n#define IP_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3]\n#define PORT_FMT \"%u\"\n#define PORT_ARG(x) ntohs(*((u16 *)(x)))\n\n#define is_multicast_mac_addr(Addr) ((((Addr[0]) & 0x01) == 0x01) && ((Addr[0]) != 0xff))\n#define is_broadcast_mac_addr(Addr) ((((Addr[0]) & 0xff) == 0xff) && (((Addr[1]) & 0xff) == 0xff) && \\\n\t(((Addr[2]) & 0xff) == 0xff) && (((Addr[3]) & 0xff) == 0xff) && (((Addr[4]) & 0xff) == 0xff) && \\\n\t\t\t\t     (((Addr[5]) & 0xff) == 0xff))\n#define is_zero_mac_addr(Addr)\t((Addr[0] == 0x00) && (Addr[1] == 0x00) && (Addr[2] == 0x00) &&   \\\n                (Addr[3] == 0x00) && (Addr[4] == 0x00) && (Addr[5] == 0x00))\n\n\n#define CFG_IEEE80211_RESERVE_FCS (1<<0)\n#define CFG_IEEE80211_COMPUTE_FCS (1<<1)\n\ntypedef struct tx_pending_t {\n\tint frag;\n\tstruct ieee80211_txb *txb;\n} tx_pending_t;\n\n\n\n#define TID_NUM\t16\n\n#define IEEE_A            (1<<0)\n#define IEEE_B            (1<<1)\n#define IEEE_G            (1<<2)\n#define IEEE_MODE_MASK    (IEEE_A | IEEE_B | IEEE_G)\n\n/* Baron move to ieee80211.c */\nint ieee80211_is_empty_essid(const char *essid, int essid_len);\nint ieee80211_get_hdrlen(u16 fc);\n\n#if 0\n\t/* Action frame categories (IEEE 802.11-2007, 7.3.1.11, Table 7-24) */\n\t#define WLAN_ACTION_SPECTRUM_MGMT 0\n\t#define WLAN_ACTION_QOS 1\n\t#define WLAN_ACTION_DLS 2\n\t#define WLAN_ACTION_BLOCK_ACK 3\n\t#define WLAN_ACTION_RADIO_MEASUREMENT 5\n\t#define WLAN_ACTION_FT 6\n\t#define WLAN_ACTION_SA_QUERY 8\n\t#define WLAN_ACTION_WMM 17\n#endif\n\n\n/* Action category code */\nenum rtw_ieee80211_category {\n\tRTW_WLAN_CATEGORY_SPECTRUM_MGMT = 0,\n\tRTW_WLAN_CATEGORY_QOS = 1,\n\tRTW_WLAN_CATEGORY_DLS = 2,\n\tRTW_WLAN_CATEGORY_BACK = 3,\n\tRTW_WLAN_CATEGORY_PUBLIC = 4, /* IEEE 802.11 public action frames */\n\tRTW_WLAN_CATEGORY_RADIO_MEAS = 5,\n\tRTW_WLAN_CATEGORY_FT = 6,\n\tRTW_WLAN_CATEGORY_HT = 7,\n\tRTW_WLAN_CATEGORY_SA_QUERY = 8,\n\tRTW_WLAN_CATEGORY_WNM = 10,\n\tRTW_WLAN_CATEGORY_UNPROTECTED_WNM = 11, /* add for CONFIG_IEEE80211W, none 11w also can use */\n\tRTW_WLAN_CATEGORY_TDLS = 12,\n\tRTW_WLAN_CATEGORY_MESH = 13,\n\tRTW_WLAN_CATEGORY_MULTIHOP = 14,\n\tRTW_WLAN_CATEGORY_SELF_PROTECTED = 15,\n\tRTW_WLAN_CATEGORY_WMM = 17,\n\tRTW_WLAN_CATEGORY_VHT = 21,\n\tRTW_WLAN_CATEGORY_P2P = 0x7f,/* P2P action frames */\n};\n\n#define CATEGORY_IS_GROUP_PRIVACY(cat) \\\n\t(cat == RTW_WLAN_CATEGORY_MESH || cat == RTW_WLAN_CATEGORY_MULTIHOP)\n\n#define CATEGORY_IS_NON_ROBUST(cat) \\\n\t(cat == RTW_WLAN_CATEGORY_PUBLIC \\\n\t|| cat == RTW_WLAN_CATEGORY_HT \\\n\t|| cat == RTW_WLAN_CATEGORY_UNPROTECTED_WNM \\\n\t|| cat == RTW_WLAN_CATEGORY_SELF_PROTECTED \\\n\t|| cat == RTW_WLAN_CATEGORY_VHT \\\n\t|| cat == RTW_WLAN_CATEGORY_P2P)\n\n#define CATEGORY_IS_ROBUST(cat) !CATEGORY_IS_NON_ROBUST(cat)\n\n/* SPECTRUM_MGMT action code */\nenum rtw_ieee80211_spectrum_mgmt_actioncode {\n\tRTW_WLAN_ACTION_SPCT_MSR_REQ = 0,\n\tRTW_WLAN_ACTION_SPCT_MSR_RPRT = 1,\n\tRTW_WLAN_ACTION_SPCT_TPC_REQ = 2,\n\tRTW_WLAN_ACTION_SPCT_TPC_RPRT = 3,\n\tRTW_WLAN_ACTION_SPCT_CHL_SWITCH = 4,\n\tRTW_WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,\n};\n\n/* SELF_PROTECTED action code */\nenum rtw_ieee80211_self_protected_actioncode {\n\tRTW_ACT_SELF_PROTECTED_RSVD = 0,\n\tRTW_ACT_SELF_PROTECTED_MESH_OPEN = 1,\n\tRTW_ACT_SELF_PROTECTED_MESH_CONF = 2,\n\tRTW_ACT_SELF_PROTECTED_MESH_CLOSE = 3,\n\tRTW_ACT_SELF_PROTECTED_MESH_GK_INFORM = 4,\n\tRTW_ACT_SELF_PROTECTED_MESH_GK_ACK = 5,\n\tRTW_ACT_SELF_PROTECTED_NUM,\n};\n\n/* MESH action code */\nenum rtw_ieee80211_mesh_actioncode {\n\tRTW_ACT_MESH_LINK_METRIC_REPORT,\n\tRTW_ACT_MESH_HWMP_PATH_SELECTION,\n\tRTW_ACT_MESH_GATE_ANNOUNCEMENT,\n\tRTW_ACT_MESH_CONGESTION_CONTROL_NOTIFICATION,\n\tRTW_ACT_MESH_MCCA_SETUP_REQUEST,\n\tRTW_ACT_MESH_MCCA_SETUP_REPLY,\n\tRTW_ACT_MESH_MCCA_ADVERTISEMENT_REQUEST,\n\tRTW_ACT_MESH_MCCA_ADVERTISEMENT,\n\tRTW_ACT_MESH_MCCA_TEARDOWN,\n\tRTW_ACT_MESH_TBTT_ADJUSTMENT_REQUEST,\n\tRTW_ACT_MESH_TBTT_ADJUSTMENT_RESPONSE,\n};\n\nenum _PUBLIC_ACTION {\n\tACT_PUBLIC_BSSCOEXIST = 0, /* 20/40 BSS Coexistence */\n\tACT_PUBLIC_DSE_ENABLE = 1,\n\tACT_PUBLIC_DSE_DEENABLE = 2,\n\tACT_PUBLIC_DSE_REG_LOCATION = 3,\n\tACT_PUBLIC_EXT_CHL_SWITCH = 4,\n\tACT_PUBLIC_DSE_MSR_REQ = 5,\n\tACT_PUBLIC_DSE_MSR_RPRT = 6,\n\tACT_PUBLIC_MP = 7, /* Measurement Pilot */\n\tACT_PUBLIC_DSE_PWR_CONSTRAINT = 8,\n\tACT_PUBLIC_VENDOR = 9, /* for WIFI_DIRECT */\n\tACT_PUBLIC_GAS_INITIAL_REQ = 10,\n\tACT_PUBLIC_GAS_INITIAL_RSP = 11,\n\tACT_PUBLIC_GAS_COMEBACK_REQ = 12,\n\tACT_PUBLIC_GAS_COMEBACK_RSP = 13,\n\tACT_PUBLIC_TDLS_DISCOVERY_RSP = 14,\n\tACT_PUBLIC_LOCATION_TRACK = 15,\n\tACT_PUBLIC_MAX\n};\n\n#ifdef CONFIG_TDLS\nenum TDLS_ACTION_FIELD {\n\tTDLS_SETUP_REQUEST = 0,\n\tTDLS_SETUP_RESPONSE = 1,\n\tTDLS_SETUP_CONFIRM = 2,\n\tTDLS_TEARDOWN = 3,\n\tTDLS_PEER_TRAFFIC_INDICATION = 4,\n\tTDLS_CHANNEL_SWITCH_REQUEST = 5,\n\tTDLS_CHANNEL_SWITCH_RESPONSE = 6,\n\tTDLS_PEER_PSM_REQUEST = 7,\n\tTDLS_PEER_PSM_RESPONSE = 8,\n\tTDLS_PEER_TRAFFIC_RESPONSE = 9,\n\tTDLS_DISCOVERY_REQUEST = 10,\n\tTDLS_DISCOVERY_RESPONSE = 14,\t/* it's used in public action frame */\n};\n\n#define\tTUNNELED_PROBE_REQ\t15\n#define\tTUNNELED_PROBE_RSP\t16\n#endif /* CONFIG_TDLS */\n\n/* BACK action code */\nenum rtw_ieee80211_back_actioncode {\n\tRTW_WLAN_ACTION_ADDBA_REQ = 0,\n\tRTW_WLAN_ACTION_ADDBA_RESP = 1,\n\tRTW_WLAN_ACTION_DELBA = 2,\n};\n\n/* HT features action code */\nenum rtw_ieee80211_ht_actioncode {\n\tRTW_WLAN_ACTION_HT_NOTI_CHNL_WIDTH = 0,\n\tRTW_WLAN_ACTION_HT_SM_PS = 1,\n\tRTW_WLAN_ACTION_HT_PSMP = 2,\n\tRTW_WLAN_ACTION_HT_SET_PCO_PHASE = 3,\n\tRTW_WLAN_ACTION_HT_CSI = 4,\n\tRTW_WLAN_ACTION_HT_NON_COMPRESS_BEAMFORMING = 5,\n\tRTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING = 6,\n\tRTW_WLAN_ACTION_HT_ASEL_FEEDBACK = 7,\n};\n\n/* BACK (block-ack) parties */\nenum rtw_ieee80211_back_parties {\n\tRTW_WLAN_BACK_RECIPIENT = 0,\n\tRTW_WLAN_BACK_INITIATOR = 1,\n\tRTW_WLAN_BACK_TIMER = 2,\n};\n\n/*20/40 BSS Coexistence element */\n#define RTW_WLAN_20_40_BSS_COEX_INFO_REQ            BIT(0)\n#define RTW_WLAN_20_40_BSS_COEX_40MHZ_INTOL         BIT(1)\n#define RTW_WLAN_20_40_BSS_COEX_20MHZ_WIDTH_REQ     BIT(2)\n#define RTW_WLAN_20_40_BSS_COEX_OBSS_EXEMPT_REQ     BIT(3)\n#define RTW_WLAN_20_40_BSS_COEX_OBSS_EXEMPT_GRNT    BIT(4)\n\n/* VHT features action code */\nenum rtw_ieee80211_vht_actioncode {\n\tRTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING = 0,\n\tRTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT = 1,\n\tRTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION = 2,\n};\n\n/*IEEE 802.11r action code*/\n#ifdef CONFIG_RTW_80211R\nenum rtw_ieee80211_ft_actioncode {\n\tRTW_WLAN_ACTION_FT_RESV,\n\tRTW_WLAN_ACTION_FT_REQ,\n\tRTW_WLAN_ACTION_FT_RSP,\n\tRTW_WLAN_ACTION_FT_CONF,\n\tRTW_WLAN_ACTION_FT_ACK,\n\tRTW_WLAN_ACTION_FT_MAX,\n};\n#endif\n\n#ifdef CONFIG_RTW_WNM\nenum rtw_ieee80211_wnm_actioncode {\n\tRTW_WLAN_ACTION_WNM_BTM_QUERY = 6,\n\tRTW_WLAN_ACTION_WNM_BTM_REQ = 7,\n\tRTW_WLAN_ACTION_WNM_BTM_RSP = 8,\n};\n#endif\n\n#define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs)\n\t\t\t\t* 00:50:F2 */\n#ifndef PLATFORM_FREEBSD /* Baron BSD has defined */\n\t#define WME_OUI_TYPE 2\n#endif /* PLATFORM_FREEBSD */\n#define WME_OUI_SUBTYPE_INFORMATION_ELEMENT 0\n#define WME_OUI_SUBTYPE_PARAMETER_ELEMENT 1\n#define WME_OUI_SUBTYPE_TSPEC_ELEMENT 2\n#define WME_VERSION 1\n\n#define WME_ACTION_CODE_SETUP_REQUEST 0\n#define WME_ACTION_CODE_SETUP_RESPONSE 1\n#define WME_ACTION_CODE_TEARDOWN 2\n\n#define WME_SETUP_RESPONSE_STATUS_ADMISSION_ACCEPTED 0\n#define WME_SETUP_RESPONSE_STATUS_INVALID_PARAMETERS 1\n#define WME_SETUP_RESPONSE_STATUS_REFUSED 3\n\n#define WME_TSPEC_DIRECTION_UPLINK 0\n#define WME_TSPEC_DIRECTION_DOWNLINK 1\n#define WME_TSPEC_DIRECTION_BI_DIRECTIONAL 3\n\n\n#define OUI_BROADCOM 0x00904c /* Broadcom (Epigram) */\n\n#define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */\n\nenum rtw_ieee80211_rann_flags {\n\tRTW_RANN_FLAG_IS_GATE = 1 << 0,\n};\n\n/**\n * enum rtw_ieee80211_preq_flags - mesh PREQ element flags\n *\n * @RTW_IEEE80211_PREQ_IS_GATE_FLAG: Gate Announcement subfield\n * @RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG: proactive PREP subfield\n */\nenum rtw_ieee80211_preq_flags {\n\tRTW_IEEE80211_PREQ_IS_GATE_FLAG = 1 << 0,\n\tRTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG\t= 1 << 2,\n};\n\n/**\n * enum rtw_ieee80211_preq_target_flags - mesh PREQ element per target flags\n *\n * @RTW_IEEE80211_PREQ_TO_FLAG: target only subfield\n * @RTW_IEEE80211_PREQ_USN_FLAG: unknown target HWMP sequence number subfield\n */\nenum rtw_ieee80211_preq_target_flags {\n\tRTW_IEEE80211_PREQ_TO_FLAG\t= 1<<0,\n\tRTW_IEEE80211_PREQ_USN_FLAG\t= 1<<2,\n};\n\n/**\n * enum rtw_ieee80211_root_mode_identifier - root mesh STA mode identifier\n *\n * These attribute are used by dot11MeshHWMPRootMode to set root mesh STA mode\n *\n * @RTW_IEEE80211_ROOTMODE_NO_ROOT: the mesh STA is not a root mesh STA (default)\n * @RTW_IEEE80211_ROOTMODE_ROOT: the mesh STA is a root mesh STA if greater than\n *\tthis value\n * @RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP: the mesh STA is a root mesh STA supports\n *\tthe proactive PREQ with proactive PREP subfield set to 0\n * @RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP: the mesh STA is a root mesh STA\n *\tsupports the proactive PREQ with proactive PREP subfield set to 1\n * @RTW_IEEE80211_PROACTIVE_RANN: the mesh STA is a root mesh STA supports\n *\tthe proactive RANN\n */\nenum rtw_ieee80211_root_mode_identifier {\n\tRTW_IEEE80211_ROOTMODE_NO_ROOT = 0,\n\tRTW_IEEE80211_ROOTMODE_ROOT = 1,\n\tRTW_IEEE80211_PROACTIVE_PREQ_NO_PREP = 2,\n\tRTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP = 3,\n\tRTW_IEEE80211_PROACTIVE_RANN = 4,\n};\n\n/**\n * enum rtw_ieee80211_channel_flags - channel flags\n *\n * Channel flags set by the regulatory control code.\n *\n * @RTW_IEEE80211_CHAN_DISABLED: This channel is disabled.\n * @RTW_IEEE80211_CHAN_PASSIVE_SCAN: Only passive scanning is permitted\n *      on this channel.\n * @RTW_IEEE80211_CHAN_NO_IBSS: IBSS is not allowed on this channel.\n * @RTW_IEEE80211_CHAN_RADAR: Radar detection is required on this channel.\n * @RTW_IEEE80211_CHAN_NO_HT40PLUS: extension channel above this channel\n *      is not permitted.\n * @RTW_IEEE80211_CHAN_NO_HT40MINUS: extension channel below this channel\n *      is not permitted.\n */\nenum rtw_ieee80211_channel_flags {\n\tRTW_IEEE80211_CHAN_DISABLED         = 1 << 0,\n\tRTW_IEEE80211_CHAN_PASSIVE_SCAN     = 1 << 1,\n\tRTW_IEEE80211_CHAN_NO_IBSS          = 1 << 2,\n\tRTW_IEEE80211_CHAN_RADAR            = 1 << 3,\n\tRTW_IEEE80211_CHAN_NO_HT40PLUS      = 1 << 4,\n\tRTW_IEEE80211_CHAN_NO_HT40MINUS     = 1 << 5,\n};\n\n#define RTW_IEEE80211_CHAN_NO_HT40 \\\n\t(RTW_IEEE80211_CHAN_NO_HT40PLUS | RTW_IEEE80211_CHAN_NO_HT40MINUS)\n\n/* Represent channel details, subset of ieee80211_channel */\nstruct rtw_ieee80211_channel {\n\t/* enum ieee80211_band band; */\n\t/* u16 center_freq; */\n\tu16 hw_value;\n\tu32 flags;\n\t/* int max_antenna_gain; */\n\t/* int max_power; */\n\t/* int max_reg_power; */\n\t/* bool beacon_found; */\n\t/* u32 orig_flags; */\n\t/* int orig_mag; */\n\t/* int orig_mpwr; */\n};\n\n#define CHAN_FMT \\\n\t/*\"band:%d, \"*/ \\\n\t/*\"center_freq:%u, \"*/ \\\n\t\"hw_value:%u, \" \\\n\t\"flags:0x%08x\" \\\n\t/*\"max_antenna_gain:%d\\n\"*/ \\\n\t/*\"max_power:%d\\n\"*/ \\\n\t/*\"max_reg_power:%d\\n\"*/ \\\n\t/*\"beacon_found:%u\\n\"*/ \\\n\t/*\"orig_flags:0x%08x\\n\"*/ \\\n\t/*\"orig_mag:%d\\n\"*/ \\\n\t/*\"orig_mpwr:%d\\n\"*/\n\n#define CHAN_ARG(channel) \\\n\t/*(channel)->band*/ \\\n\t/*, (channel)->center_freq*/ \\\n\t(channel)->hw_value \\\n\t, (channel)->flags \\\n\t/*, (channel)->max_antenna_gain*/ \\\n\t/*, (channel)->max_power*/ \\\n\t/*, (channel)->max_reg_power*/ \\\n\t/*, (channel)->beacon_found*/ \\\n\t/*, (channel)->orig_flags*/ \\\n\t/*, (channel)->orig_mag*/ \\\n\t/*, (channel)->orig_mpwr*/ \\\n\n/* Parsed Information Elements */\nstruct rtw_ieee802_11_elems {\n\tu8 *ssid;\n\tu8 ssid_len;\n\tu8 *supp_rates;\n\tu8 supp_rates_len;\n\tu8 *fh_params;\n\tu8 fh_params_len;\n\tu8 *ds_params;\n\tu8 ds_params_len;\n\tu8 *cf_params;\n\tu8 cf_params_len;\n\tu8 *tim;\n\tu8 tim_len;\n\tu8 *ibss_params;\n\tu8 ibss_params_len;\n\tu8 *challenge;\n\tu8 challenge_len;\n\tu8 *erp_info;\n\tu8 erp_info_len;\n\tu8 *ext_supp_rates;\n\tu8 ext_supp_rates_len;\n\tu8 *wpa_ie;\n\tu8 wpa_ie_len;\n\tu8 *rsn_ie;\n\tu8 rsn_ie_len;\n\tu8 *wme;\n\tu8 wme_len;\n\tu8 *wme_tspec;\n\tu8 wme_tspec_len;\n\tu8 *wps_ie;\n\tu8 wps_ie_len;\n\tu8 *power_cap;\n\tu8 power_cap_len;\n\tu8 *supp_channels;\n\tu8 supp_channels_len;\n\tu8 *mdie;\n\tu8 mdie_len;\n\tu8 *ftie;\n\tu8 ftie_len;\n\tu8 *timeout_int;\n\tu8 timeout_int_len;\n\tu8 *ht_capabilities;\n\tu8 ht_capabilities_len;\n\tu8 *ht_operation;\n\tu8 ht_operation_len;\n\tu8 *vendor_ht_cap;\n\tu8 vendor_ht_cap_len;\n\tu8 *vht_capabilities;\n\tu8 vht_capabilities_len;\n\tu8 *vht_operation;\n\tu8 vht_operation_len;\n\tu8 *vht_op_mode_notify;\n\tu8 vht_op_mode_notify_len;\n\tu8 *rm_en_cap;\n\tu8 rm_en_cap_len;\n#ifdef CONFIG_RTW_MESH\n\tu8 *preq;\n\tu8 preq_len;\n\tu8 *prep;\n\tu8 prep_len;\n\tu8 *perr;\n\tu8 perr_len;\n\tu8 *rann;\n\tu8 rann_len;\n#endif\n};\n\ntypedef enum { ParseOK = 0, ParseUnknown = 1, ParseFailed = -1 } ParseRes;\n\nParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len,\n\t\t\t\tstruct rtw_ieee802_11_elems *elems,\n\t\t\t\tint show_errors);\n\nu8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, unsigned int *frlen);\nu8 *rtw_set_ie(u8 *pbuf, sint index, uint len, const u8 *source, uint *frlen);\n\nenum secondary_ch_offset {\n\tSCN = 0, /* no secondary channel */\n\tSCA = 1, /* secondary channel above */\n\tSCB = 3,  /* secondary channel below */\n};\nu8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset);\nu8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset);\nu8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode, u8 new_ch, u8 ch_switch_cnt);\nu8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset);\nu8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, u8 flags, u16 reason, u16 precedence);\n\nu8 *rtw_get_ie(const u8 *pbuf, sint index, sint *len, sint limit);\nu8 rtw_update_rate_bymode(WLAN_BSSID_EX *pbss_network, u32 mode);\n\nu8 *rtw_get_ie_ex(const u8 *in_ie, uint in_len, u8 eid, const u8 *oui, u8 oui_len, u8 *ie, uint *ielen);\nint rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len);\n\nvoid rtw_set_supported_rate(u8 *SupportedRates, uint mode) ;\n\n#define GET_RSN_CAP_MFP_OPTION(cap)\tLE_BITS_TO_2BYTE(((u8 *)(cap)), 6, 2)\n\n#define MFP_NO\t\t\t0\n#define MFP_INVALID\t\t1\n#define MFP_OPTIONAL\t2\n#define MFP_REQUIRED\t3\n\nstruct rsne_info {\n\tu8 *gcs;\n\tu16 pcs_cnt;\n\tu8 *pcs_list;\n\tu16 akm_cnt;\n\tu8 *akm_list;\n\tu8 *cap;\n\tu16 pmkid_cnt;\n\tu8 *pmkid_list;\n\tu8 *gmcs;\n\n\tu8 err;\n};\nint rtw_rsne_info_parse(const u8 *ie, uint ie_len, struct rsne_info *info);\n\nunsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit);\nunsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit);\nint rtw_get_wpa_cipher_suite(u8 *s);\nint rtw_get_wpa2_cipher_suite(u8 *s);\nint rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len);\nint rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, u32 *akm);\nint rtw_parse_wpa2_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, u32 *akm, u8 *mfp_opt);\n\nint rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie, u16 *wpa_len);\n\nu8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen);\nu8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, enum bss_type frame_type);\nu8 *rtw_get_wps_ie(const u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen);\nu8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_attr, u32 *len_attr);\nu8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_content, uint *len_content);\n\n/**\n * for_each_ie - iterate over continuous IEs\n * @ie:\n * @buf:\n * @buf_len:\n */\n#define for_each_ie(ie, buf, buf_len) \\\n\tfor (ie = (void *)buf; (((u8 *)ie) - ((u8 *)buf) + 1) < buf_len; ie = (void *)(((u8 *)ie) + *(((u8 *)ie)+1) + 2))\n\nvoid dump_ies(void *sel, const u8 *buf, u32 buf_len);\n\n#ifdef CONFIG_80211N_HT\n#define HT_SC_OFFSET_MAX 4\nextern const char *const _ht_sc_offset_str[];\n#define ht_sc_offset_str(sc) (((sc) >= HT_SC_OFFSET_MAX) ? _ht_sc_offset_str[2] : _ht_sc_offset_str[(sc)])\n\nvoid dump_ht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len);\n#endif\n\nvoid dump_wps_ie(void *sel, const u8 *ie, u32 ie_len);\n\nvoid rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht);\n\nvoid rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht);\n\nbool rtw_is_chbw_grouped(u8 ch_a, u8 bw_a, u8 offset_a\n\t, u8 ch_b, u8 bw_b, u8 offset_b);\nvoid rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset\n\t, u8 *g_ch, u8 *g_bw, u8 *g_offset);\n\nu32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len);\nint rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie);\nvoid dump_p2p_ie(void *sel, const u8 *ie, u32 ie_len);\nu8 *rtw_get_p2p_ie(const u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen);\nu8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr);\nu8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content);\nu32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr);\nuint rtw_del_p2p_ie(u8 *ies, uint ies_len_ori, const char *msg);\nuint rtw_del_p2p_attr(u8 *ie, uint ielen_ori, u8 attr_id);\nu8 *rtw_bss_ex_get_p2p_ie(WLAN_BSSID_EX *bss_ex, u8 *p2p_ie, uint *p2p_ielen);\nvoid rtw_bss_ex_del_p2p_ie(WLAN_BSSID_EX *bss_ex);\nvoid rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id);\n\nvoid dump_wfd_ie(void *sel, const u8 *ie, u32 ie_len);\nu8 *rtw_get_wfd_ie(const u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen);\nu8 *rtw_get_wfd_attr(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr);\nu8 *rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content);\nuint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg);\nuint rtw_del_wfd_attr(u8 *ie, uint ielen_ori, u8 attr_id);\nu8 *rtw_bss_ex_get_wfd_ie(WLAN_BSSID_EX *bss_ex, u8 *wfd_ie, uint *wfd_ielen);\nvoid rtw_bss_ex_del_wfd_ie(WLAN_BSSID_EX *bss_ex);\nvoid rtw_bss_ex_del_wfd_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id);\n\nuint\trtw_get_rateset_len(u8\t*rateset);\n\nstruct registry_priv;\nint rtw_generate_ie(struct registry_priv *pregistrypriv);\n\nint rtw_get_bit_value_from_ieee_value(u8 val);\n\nuint\trtw_is_cckrates_included(u8 *rate);\n\nuint\trtw_is_cckratesonly_included(u8 *rate);\nuint rtw_get_cckrate_size(u8 *rate,u32 rate_length);\nint rtw_check_network_type(unsigned char *rate, int ratelen, int channel);\n\nu8 rtw_check_invalid_mac_address(u8 *mac_addr, u8 check_local_bit);\nvoid rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr);\n\nu16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI, unsigned char *MCS_rate);\nu8\trtw_ht_mcsset_to_nss(u8 *supp_mcs_set);\nu32\trtw_ht_mcs_set_to_bitmap(u8 *mcs_set, u8 nss);\n\nint rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8 *category, u8 *action);\nconst char *action_public_str(u8 action);\n\nu8 key_2char2num(u8 hch, u8 lch);\nu8 str_2char2num(u8 hch, u8 lch);\nvoid macstr2num(u8 *dst, u8 *src);\nu8 convert_ip_addr(u8 hch, u8 mch, u8 lch);\nint wifirate2_ratetbl_inx(unsigned char rate);\n\n\n#endif /* IEEE80211_H */\n"
  },
  {
    "path": "include/ieee80211_ext.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __IEEE80211_EXT_H\n#define __IEEE80211_EXT_H\n\n#include <drv_conf.h>\n#include <osdep_service.h>\n#include <drv_types.h>\n\n#define WMM_OUI_TYPE 2\n#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0\n#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1\n#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2\n#define WMM_VERSION 1\n\n#define WPA_PROTO_WPA BIT(0)\n#define WPA_PROTO_RSN BIT(1)\n\n#define WPA_KEY_MGMT_IEEE8021X BIT(0)\n#define WPA_KEY_MGMT_PSK BIT(1)\n#define WPA_KEY_MGMT_NONE BIT(2)\n#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3)\n#define WPA_KEY_MGMT_WPA_NONE BIT(4)\n\n\n#define WPA_CAPABILITY_PREAUTH BIT(0)\n#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6)\n#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9)\n\n\n#define PMKID_LEN 16\n\n\n#ifdef PLATFORM_LINUX\nstruct wpa_ie_hdr {\n\tu8 elem_id;\n\tu8 len;\n\tu8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */\n\tu8 version[2]; /* little endian */\n} __attribute__((packed));\n\nstruct rsn_ie_hdr {\n\tu8 elem_id; /* WLAN_EID_RSN */\n\tu8 len;\n\tu8 version[2]; /* little endian */\n} __attribute__((packed));\n\nstruct wme_ac_parameter {\n#if defined(CONFIG_LITTLE_ENDIAN)\n\t/* byte 1 */\n\tu8\taifsn:4,\n\t     acm:1,\n\t     aci:2,\n\t     reserved:1;\n\n\t/* byte 2 */\n\tu8\teCWmin:4,\n\t     eCWmax:4;\n#elif defined(CONFIG_BIG_ENDIAN)\n\t/* byte 1 */\n\tu8\treserved:1,\n\t     aci:2,\n\t     acm:1,\n\t     aifsn:4;\n\n\t/* byte 2 */\n\tu8\teCWmax:4,\n\t     eCWmin:4;\n#else\n#error\t\"Please fix <endian.h>\"\n#endif\n\n\t/* bytes 3 & 4 */\n\tu16 txopLimit;\n} __attribute__((packed));\n\nstruct wme_parameter_element {\n\t/* required fields for WME version 1 */\n\tu8 oui[3];\n\tu8 oui_type;\n\tu8 oui_subtype;\n\tu8 version;\n\tu8 acInfo;\n\tu8 reserved;\n\tstruct wme_ac_parameter ac[4];\n\n} __attribute__((packed));\n\n#endif\n\n#define WPA_PUT_LE16(a, val)\t\t\t\\\n\tdo {\t\t\t\t\t\\\n\t\t(a)[1] = ((u16) (val)) >> 8;\t\\\n\t\t(a)[0] = ((u16) (val)) & 0xff;\t\\\n\t} while (0)\n\n#define WPA_PUT_BE32(a, val)\t\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\t(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff);\t\\\n\t\t(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff);\t\\\n\t\t(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff);\t\\\n\t\t(a)[3] = (u8) (((u32) (val)) & 0xff);\t\t\\\n\t} while (0)\n\n#define WPA_PUT_LE32(a, val)\t\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\t(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff);\t\\\n\t\t(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff);\t\\\n\t\t(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff);\t\\\n\t\t(a)[0] = (u8) (((u32) (val)) & 0xff);\t\t\\\n\t} while (0)\n\n#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val))\n/* #define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val)) */\n\n\n\n/* Action category code */\nenum ieee80211_category {\n\tWLAN_CATEGORY_SPECTRUM_MGMT = 0,\n\tWLAN_CATEGORY_QOS = 1,\n\tWLAN_CATEGORY_DLS = 2,\n\tWLAN_CATEGORY_BACK = 3,\n\tWLAN_CATEGORY_HT = 7,\n\tWLAN_CATEGORY_WMM = 17,\n};\n\n/* SPECTRUM_MGMT action code */\nenum ieee80211_spectrum_mgmt_actioncode {\n\tWLAN_ACTION_SPCT_MSR_REQ = 0,\n\tWLAN_ACTION_SPCT_MSR_RPRT = 1,\n\tWLAN_ACTION_SPCT_TPC_REQ = 2,\n\tWLAN_ACTION_SPCT_TPC_RPRT = 3,\n\tWLAN_ACTION_SPCT_CHL_SWITCH = 4,\n\tWLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,\n};\n\n/* BACK action code */\nenum ieee80211_back_actioncode {\n\tWLAN_ACTION_ADDBA_REQ = 0,\n\tWLAN_ACTION_ADDBA_RESP = 1,\n\tWLAN_ACTION_DELBA = 2,\n};\n\n/* HT features action code */\nenum ieee80211_ht_actioncode {\n\tWLAN_ACTION_NOTIFY_CH_WIDTH = 0,\n\tWLAN_ACTION_SM_PS = 1,\n\tWLAN_ACTION_PSPM = 2,\n\tWLAN_ACTION_PCO_PHASE = 3,\n\tWLAN_ACTION_MIMO_CSI_MX = 4,\n\tWLAN_ACTION_MIMO_NONCP_BF = 5,\n\tWLAN_ACTION_MIMP_CP_BF = 6,\n\tWLAN_ACTION_ASEL_INDICATES_FB = 7,\n\tWLAN_ACTION_HI_INFO_EXCHG = 8,\n};\n\n/* BACK (block-ack) parties */\nenum ieee80211_back_parties {\n\tWLAN_BACK_RECIPIENT = 0,\n\tWLAN_BACK_INITIATOR = 1,\n\tWLAN_BACK_TIMER = 2,\n};\n\n#ifdef PLATFORM_LINUX\n\nstruct ieee80211_mgmt {\n\tu16 frame_control;\n\tu16 duration;\n\tu8 da[6];\n\tu8 sa[6];\n\tu8 bssid[6];\n\tu16 seq_ctrl;\n\tunion {\n\t\tstruct {\n\t\t\tu16 auth_alg;\n\t\t\tu16 auth_transaction;\n\t\t\tu16 status_code;\n\t\t\t/* possibly followed by Challenge text */\n\t\t\tu8 variable[0];\n\t\t}  __attribute__((packed)) auth;\n\t\tstruct {\n\t\t\tu16 reason_code;\n\t\t}  __attribute__((packed)) deauth;\n\t\tstruct {\n\t\t\tu16 capab_info;\n\t\t\tu16 listen_interval;\n\t\t\t/* followed by SSID and Supported rates */\n\t\t\tu8 variable[0];\n\t\t}  __attribute__((packed)) assoc_req;\n\t\tstruct {\n\t\t\tu16 capab_info;\n\t\t\tu16 status_code;\n\t\t\tu16 aid;\n\t\t\t/* followed by Supported rates */\n\t\t\tu8 variable[0];\n\t\t}  __attribute__((packed)) assoc_resp, reassoc_resp;\n\t\tstruct {\n\t\t\tu16 capab_info;\n\t\t\tu16 listen_interval;\n\t\t\tu8 current_ap[6];\n\t\t\t/* followed by SSID and Supported rates */\n\t\t\tu8 variable[0];\n\t\t}  __attribute__((packed)) reassoc_req;\n\t\tstruct {\n\t\t\tu16 reason_code;\n\t\t}  __attribute__((packed)) disassoc;\n\t\tstruct {\n\t\t\t__le64 timestamp;\n\t\t\tu16 beacon_int;\n\t\t\tu16 capab_info;\n\t\t\t/* followed by some of SSID, Supported rates,\n\t\t\t * FH Params, DS Params, CF Params, IBSS Params, TIM */\n\t\t\tu8 variable[0];\n\t\t}  __attribute__((packed)) beacon;\n\t\tstruct {\n\t\t\t/* only variable items: SSID, Supported rates */\n\t\t\tu8 variable[0];\n\t\t}  __attribute__((packed)) probe_req;\n\t\tstruct {\n\t\t\t__le64 timestamp;\n\t\t\tu16 beacon_int;\n\t\t\tu16 capab_info;\n\t\t\t/* followed by some of SSID, Supported rates,\n\t\t\t * FH Params, DS Params, CF Params, IBSS Params */\n\t\t\tu8 variable[0];\n\t\t}  __attribute__((packed)) probe_resp;\n\t\tstruct {\n\t\t\tu8 category;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\tu8 status_code;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t}  __attribute__((packed)) wme_action;\n#if 0\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 element_id;\n\t\t\t\t\tu8 length;\n\t\t\t\t\tstruct ieee80211_channel_sw_ie sw_elem;\n\t\t\t\t}  __attribute__((packed)) chan_switch;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\tu8 element_id;\n\t\t\t\t\tu8 length;\n\t\t\t\t\tstruct ieee80211_msrment_ie msr_elem;\n\t\t\t\t}  __attribute__((packed)) measurement;\n#endif\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\tu16 capab;\n\t\t\t\t\tu16 timeout;\n\t\t\t\t\tu16 start_seq_num;\n\t\t\t\t}  __attribute__((packed)) addba_req;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\tu16 status;\n\t\t\t\t\tu16 capab;\n\t\t\t\t\tu16 timeout;\n\t\t\t\t}  __attribute__((packed)) addba_resp;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu16 params;\n\t\t\t\t\tu16 reason_code;\n\t\t\t\t}  __attribute__((packed)) delba;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\t/* capab_info for open and confirm,\n\t\t\t\t\t * reason for close\n\t\t\t\t\t */\n\t\t\t\t\tu16 aux;\n\t\t\t\t\t/* Followed in plink_confirm by status\n\t\t\t\t\t * code, AID and supported rates,\n\t\t\t\t\t * and directly by supported rates in\n\t\t\t\t\t * plink_open and plink_close\n\t\t\t\t\t */\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t}  __attribute__((packed)) plink_action;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t}  __attribute__((packed)) mesh_action;\n\t\t\t} __attribute__((packed)) u;\n\t\t}  __attribute__((packed)) action;\n\t} __attribute__((packed)) u;\n} __attribute__((packed));\n\n#endif\n\n/* mgmt header + 1 byte category code */\n#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u)\n\n\n\n#endif\n"
  },
  {
    "path": "include/if_ether.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef _LINUX_IF_ETHER_H\n#define _LINUX_IF_ETHER_H\n\n/*\n *\tIEEE 802.3 Ethernet magic constants.  The frame sizes omit the preamble\n *\tand FCS/CRC (frame check sequence).\n */\n\n#define ETH_ALEN\t6\t\t/* Octets in one ethernet addr\t */\n#define ETH_HLEN\t14\t\t/* Total octets in header.\t */\n#define ETH_ZLEN\t60\t\t/* Min. octets in frame sans FCS */\n#define ETH_DATA_LEN\t1500\t\t/* Max. octets in payload\t */\n#define ETH_FRAME_LEN\t1514\t\t/* Max. octets in frame sans FCS */\n\n/*\n *\tThese are the defined Ethernet Protocol ID's.\n */\n\n#define ETH_P_LOOP\t0x0060\t\t/* Ethernet Loopback packet\t*/\n#define ETH_P_PUP\t0x0200\t\t/* Xerox PUP packet\t\t*/\n#define ETH_P_PUPAT\t0x0201\t\t/* Xerox PUP Addr Trans packet\t*/\n#define ETH_P_IP\t0x0800\t\t/* Internet Protocol packet\t*/\n#define ETH_P_X25\t0x0805\t\t/* CCITT X.25\t\t\t*/\n#define ETH_P_ARP\t0x0806\t\t/* Address Resolution packet\t*/\n#define\tETH_P_BPQ\t0x08FF\t\t/* G8BPQ AX.25 Ethernet Packet\t[ NOT AN OFFICIALLY REGISTERED ID ] */\n#define ETH_P_IEEEPUP\t0x0a00\t\t/* Xerox IEEE802.3 PUP packet */\n#define ETH_P_IEEEPUPAT\t0x0a01\t\t/* Xerox IEEE802.3 PUP Addr Trans packet */\n#define ETH_P_DEC       0x6000          /* DEC Assigned proto          */\n#define ETH_P_DNA_DL    0x6001          /* DEC DNA Dump/Load           */\n#define ETH_P_DNA_RC    0x6002          /* DEC DNA Remote Console      */\n#define ETH_P_DNA_RT    0x6003          /* DEC DNA Routing             */\n#define ETH_P_LAT       0x6004          /* DEC LAT                     */\n#define ETH_P_DIAG      0x6005          /* DEC Diagnostics             */\n#define ETH_P_CUST      0x6006          /* DEC Customer use            */\n#define ETH_P_SCA       0x6007          /* DEC Systems Comms Arch      */\n#define ETH_P_RARP      0x8035\t\t/* Reverse Addr Res packet\t*/\n#define ETH_P_ATALK\t0x809B\t\t/* Appletalk DDP\t\t*/\n#define ETH_P_AARP\t0x80F3\t\t/* Appletalk AARP\t\t*/\n#define ETH_P_8021Q\t0x8100          /* 802.1Q VLAN Extended Header */\n#define ETH_P_IPX\t0x8137\t\t/* IPX over DIX\t\t\t*/\n#define ETH_P_IPV6\t0x86DD\t\t/* IPv6 over bluebook\t\t*/\n#define ETH_P_PPP_DISC\t0x8863\t\t/* PPPoE discovery messages    */\n#define ETH_P_PPP_SES\t0x8864\t\t/* PPPoE session messages\t*/\n#define ETH_P_ATMMPOA\t0x884c\t\t/* MultiProtocol Over ATM\t*/\n#define ETH_P_ATMFATE\t0x8884\t\t/* Frame-based ATM Transport\n\t\t\t\t\t * over Ethernet\n\t\t\t\t\t */\n\n/*\n *\tNon DIX types. Won't clash for 1500 types.\n */\n\n#define ETH_P_802_3\t0x0001\t\t/* Dummy type for 802.3 frames */\n#define ETH_P_AX25\t0x0002\t\t/* Dummy protocol id for AX.25 */\n#define ETH_P_ALL\t0x0003\t\t/* Every packet (be careful!!!) */\n#define ETH_P_802_2\t0x0004\t\t/* 802.2 frames \t\t*/\n#define ETH_P_SNAP\t0x0005\t\t/* Internal only\t\t*/\n#define ETH_P_DDCMP     0x0006          /* DEC DDCMP: Internal only    */\n#define ETH_P_WAN_PPP   0x0007          /* Dummy type for WAN PPP frames*/\n#define ETH_P_PPP_MP    0x0008          /* Dummy type for PPP MP frames */\n#define ETH_P_LOCALTALK 0x0009\t\t/* Localtalk pseudo type \t*/\n#define ETH_P_PPPTALK\t0x0010\t\t/* Dummy type for Atalk over PPP*/\n#define ETH_P_TR_802_2\t0x0011\t\t/* 802.2 frames \t\t*/\n#define ETH_P_MOBITEX\t0x0015\t\t/* Mobitex (kaz@cafe.net)\t*/\n#define ETH_P_CONTROL\t0x0016\t\t/* Card specific control frames */\n#define ETH_P_IRDA\t0x0017\t\t/* Linux-IrDA\t\t\t*/\n#define ETH_P_ECONET\t0x0018\t\t/* Acorn Econet\t\t\t*/\n\n/*\n *\tThis is an Ethernet frame header.\n */\n\nstruct ethhdr {\n\tunsigned char\th_dest[ETH_ALEN];\t/* destination eth addr\t*/\n\tunsigned char\th_source[ETH_ALEN];\t/* source ether addr\t*/\n\tunsigned short\th_proto;\t\t/* packet type ID field\t*/\n};\n\nstruct _vlan {\n\tunsigned short       h_vlan_TCI;                /* Encapsulates priority and VLAN ID */\n\tunsigned short       h_vlan_encapsulated_proto;\n};\n\n\n\n#define get_vlan_id(pvlan) ((ntohs((unsigned short)pvlan->h_vlan_TCI)) & 0xfff)\n#define get_vlan_priority(pvlan) ((ntohs((unsigned short)pvlan->h_vlan_TCI))>>13)\n#define get_vlan_encap_proto(pvlan) (ntohs((unsigned short)pvlan->h_vlan_encapsulated_proto))\n\n\n#endif\t/* _LINUX_IF_ETHER_H */\n"
  },
  {
    "path": "include/ip.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _LINUX_IP_H\n#define _LINUX_IP_H\n\n/* SOL_IP socket options */\n\n#define IPTOS_TOS_MASK\t\t0x1E\n#define IPTOS_TOS(tos)\t\t((tos)&IPTOS_TOS_MASK)\n#define\tIPTOS_LOWDELAY\t\t0x10\n#define\tIPTOS_THROUGHPUT\t0x08\n#define\tIPTOS_RELIABILITY\t0x04\n#define\tIPTOS_MINCOST\t\t0x02\n\n#define IPTOS_PREC_MASK\t\t0xE0\n#define IPTOS_PREC(tos)\t\t((tos)&IPTOS_PREC_MASK)\n#define IPTOS_PREC_NETCONTROL           0xe0\n#define IPTOS_PREC_INTERNETCONTROL      0xc0\n#define IPTOS_PREC_CRITIC_ECP           0xa0\n#define IPTOS_PREC_FLASHOVERRIDE        0x80\n#define IPTOS_PREC_FLASH                0x60\n#define IPTOS_PREC_IMMEDIATE            0x40\n#define IPTOS_PREC_PRIORITY             0x20\n#define IPTOS_PREC_ROUTINE              0x00\n\n\n/* IP options */\n#define IPOPT_COPY\t\t0x80\n#define IPOPT_CLASS_MASK\t0x60\n#define IPOPT_NUMBER_MASK\t0x1f\n\n#define\tIPOPT_COPIED(o)\t\t((o)&IPOPT_COPY)\n#define\tIPOPT_CLASS(o)\t\t((o)&IPOPT_CLASS_MASK)\n#define\tIPOPT_NUMBER(o)\t\t((o)&IPOPT_NUMBER_MASK)\n\n#define\tIPOPT_CONTROL\t\t0x00\n#define\tIPOPT_RESERVED1\t\t0x20\n#define\tIPOPT_MEASUREMENT\t0x40\n#define\tIPOPT_RESERVED2\t\t0x60\n\n#define IPOPT_END\t(0 | IPOPT_CONTROL)\n#define IPOPT_NOOP\t(1 | IPOPT_CONTROL)\n#define IPOPT_SEC\t(2 | IPOPT_CONTROL | IPOPT_COPY)\n#define IPOPT_LSRR\t(3 | IPOPT_CONTROL | IPOPT_COPY)\n#define IPOPT_TIMESTAMP\t(4 | IPOPT_MEASUREMENT)\n#define IPOPT_RR\t(7 | IPOPT_CONTROL)\n#define IPOPT_SID\t(8 | IPOPT_CONTROL | IPOPT_COPY)\n#define IPOPT_SSRR\t(9 | IPOPT_CONTROL | IPOPT_COPY)\n#define IPOPT_RA\t(20 | IPOPT_CONTROL | IPOPT_COPY)\n\n#define IPVERSION\t4\n#define MAXTTL\t\t255\n#define IPDEFTTL\t64\n\n/* struct timestamp, struct route and MAX_ROUTES are removed.\n\n   REASONS: it is clear that nobody used them because:\n   - MAX_ROUTES value was wrong.\n   - \"struct route\" was wrong.\n   - \"struct timestamp\" had fatally misaligned bitfields and was completely unusable.\n */\n\n#define IPOPT_OPTVAL 0\n#define IPOPT_OLEN   1\n#define IPOPT_OFFSET 2\n#define IPOPT_MINOFF 4\n#define MAX_IPOPTLEN 40\n#define IPOPT_NOP IPOPT_NOOP\n#define IPOPT_EOL IPOPT_END\n#define IPOPT_TS  IPOPT_TIMESTAMP\n\n#define\tIPOPT_TS_TSONLY\t\t0\t\t/* timestamps only */\n#define\tIPOPT_TS_TSANDADDR\t1\t\t/* timestamps and addresses */\n#define\tIPOPT_TS_PRESPEC\t3\t\t/* specified modules only */\n\n#ifdef PLATFORM_LINUX\n\nstruct ip_options {\n\t__u32\t\tfaddr;\t\t\t\t/* Saved first hop address */\n\tunsigned char\toptlen;\n\tunsigned char srr;\n\tunsigned char rr;\n\tunsigned char ts;\n\tunsigned char is_setbyuser:1,\t\t\t/* Set by setsockopt?\t\t\t*/\n\t\t is_data:1,\t\t\t/* Options in __data, rather than skb\t*/\n\t\t is_strictroute:1,\t\t/* Strict source route\t\t\t*/\n\t\t srr_is_hit:1,\t\t\t/* Packet destination addr was our one\t*/\n\t\t is_changed:1,\t\t\t/* IP checksum more not valid\t\t*/\n\t\t rr_needaddr:1,\t\t\t/* Need to record addr of outgoing dev\t*/\n\t\t ts_needtime:1,\t\t\t/* Need to record timestamp\t\t*/\n\t\t ts_needaddr:1;\t\t\t/* Need to record addr of outgoing dev */\n\tunsigned char router_alert;\n\tunsigned char __pad1;\n\tunsigned char __pad2;\n\tunsigned char __data[0];\n};\n\n#define optlength(opt) (sizeof(struct ip_options) + opt->optlen)\n#endif\n\nstruct iphdr {\n#if defined(__LITTLE_ENDIAN_BITFIELD)\n\t__u8\tihl:4,\n\t\tversion:4;\n#elif defined (__BIG_ENDIAN_BITFIELD)\n\t__u8\tversion:4,\n\t\tihl:4;\n#else\n#error\t\"Please fix <asm/byteorder.h>\"\n#endif\n\t__u8\ttos;\n\t__u16\ttot_len;\n\t__u16\tid;\n\t__u16\tfrag_off;\n\t__u8\tttl;\n\t__u8\tprotocol;\n\t__u16\tcheck;\n\t__u32\tsaddr;\n\t__u32\tdaddr;\n\t/*The options start here. */\n};\n\n#endif\t/* _LINUX_IP_H */\n"
  },
  {
    "path": "include/linux/wireless.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef _LINUX_WIRELESS_H\n#define _LINUX_WIRELESS_H\n\n/***************************** INCLUDES *****************************/\n\n#if 0\n\t#include <linux/types.h>\t\t/* for __u* and __s* typedefs */\n\t#include <linux/socket.h>\t\t/* for \"struct sockaddr\" et al\t*/\n\t#include <linux/if.h>\t\t\t/* for IFNAMSIZ and co... */\n#else\n\t#define __user\n\t/* typedef uint16_t\t__u16; */\n\t#include <sys/socket.h>\t\t\t/* for \"struct sockaddr\" et al\t*/\n\t#include <net/if.h>\t\t\t/* for IFNAMSIZ and co... */\n#endif\n\n/****************************** TYPES ******************************/\n#ifdef CONFIG_COMPAT\nstruct compat_iw_point {\n\tcompat_caddr_t pointer;\n\t__u16 length;\n\t__u16 flags;\n};\n#endif\n/* --------------------------- SUBTYPES --------------------------- */\n/*\n *\tFor all data larger than 16 octets, we need to use a\n *\tpointer to memory allocated in user space.\n */\nstruct\tiw_point {\n\tvoid __user\t*pointer;\t/* Pointer to the data  (in user space) */\n\t__u16\t\tlength;\t\t/* number of fields or size in bytes */\n\t__u16\t\tflags;\t\t/* Optional params */\n};\n\n\n/* ------------------------ IOCTL REQUEST ------------------------ */\n/*\n * This structure defines the payload of an ioctl, and is used\n * below.\n *\n * Note that this structure should fit on the memory footprint\n * of iwreq (which is the same as ifreq), which mean a max size of\n * 16 octets = 128 bits. Warning, pointers might be 64 bits wide...\n * You should check this when increasing the structures defined\n * above in this file...\n */\nunion\tiwreq_data {\n\t/* Config - generic */\n\tchar\t\tname[IFNAMSIZ];\n\t/* Name : used to verify the presence of  wireless extensions.\n\t * Name of the protocol/provider... */\n\n\tstruct iw_point\tdata;\t\t/* Other large parameters */\n};\n\n/*\n * The structure to exchange data for ioctl.\n * This structure is the same as 'struct ifreq', but (re)defined for\n * convenience...\n * Do I need to remind you about structure size (32 octets) ?\n */\nstruct\tiwreq {\n\tunion {\n\t\tchar\tifrn_name[IFNAMSIZ];\t/* if name, e.g. \"eth0\" */\n\t} ifr_ifrn;\n\n\t/* Data part (defined just above) */\n\tunion\tiwreq_data\tu;\n};\n\n#endif\t/* _LINUX_WIRELESS_H */\n"
  },
  {
    "path": "include/mlme_osdep.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef\t__MLME_OSDEP_H_\n#define __MLME_OSDEP_H_\n\nextern void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated);\nextern void rtw_os_indicate_connect(_adapter *adapter);\nvoid rtw_os_indicate_scan_done(_adapter *padapter, bool aborted);\nextern void rtw_report_sec_ie(_adapter *adapter, u8 authmode, u8 *sec_ie);\n\nvoid rtw_reset_securitypriv(_adapter *adapter);\n\n#endif /* _MLME_OSDEP_H_ */\n"
  },
  {
    "path": "include/nic_spec.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n\n#ifndef __NIC_SPEC_H__\n#define __NIC_SPEC_H__\n\n#include <drv_conf.h>\n\n#define RTL8711_MCTRL_\t\t(0x20000)\n#define RTL8711_UART_\t\t(0x30000)\n#define RTL8711_TIMER_\t\t(0x40000)\n#define RTL8711_FINT_\t\t(0x50000)\n#define RTL8711_HINT_\t\t(0x50000)\n#define RTL8711_GPIO_\t\t(0x60000)\n#define RTL8711_WLANCTRL_\t(0x200000)\n#define RTL8711_WLANFF_\t\t(0xe00000)\n#define RTL8711_HCICTRL_\t(0x600000)\n#define RTL8711_SYSCFG_\t\t(0x620000)\n#define RTL8711_SYSCTRL_\t(0x620000)\n#define RTL8711_MCCTRL_\t\t(0x020000)\n\n\n#include <rtl8711_regdef.h>\n\n#include <rtl8711_bitdef.h>\n\n\n#endif /* __RTL8711_SPEC_H__ */\n"
  },
  {
    "path": "include/osdep_intf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef __OSDEP_INTF_H_\n#define __OSDEP_INTF_H_\n\n\nstruct intf_priv {\n\n\tu8 *intf_dev;\n\tu32\tmax_iosz;\t/* USB2.0: 128, USB1.1: 64, SDIO:64 */\n\tu32\tmax_xmitsz; /* USB2.0: unlimited, SDIO:512 */\n\tu32\tmax_recvsz; /* USB2.0: unlimited, SDIO:512 */\n\n\tvolatile u8 *io_rwmem;\n\tvolatile u8 *allocated_io_rwmem;\n\tu32\tio_wsz; /* unit: 4bytes */\n\tu32\tio_rsz;/* unit: 4bytes */\n\tu8 intf_status;\n\n\tvoid (*_bus_io)(u8 *priv);\n\n\t/*\n\tUnder Sync. IRP (SDIO/USB)\n\tA protection mechanism is necessary for the io_rwmem(read/write protocol)\n\n\tUnder Async. IRP (SDIO/USB)\n\tThe protection mechanism is through the pending queue.\n\t*/\n\n\t_mutex ioctl_mutex;\n\n\n#ifdef PLATFORM_LINUX\n#ifdef CONFIG_USB_HCI\n\t/* when in USB, IO is through interrupt in/out endpoints */\n\tstruct usb_device\t*udev;\n\tPURB\tpiorw_urb;\n\tu8 io_irp_cnt;\n\tu8 bio_irp_pending;\n\t_sema io_retevt;\n\t_timer\tio_timer;\n\tu8 bio_irp_timeout;\n\tu8 bio_timer_cancel;\n#endif\n#endif\n\n};\n\nstruct dvobj_priv *devobj_init(void);\nvoid devobj_deinit(struct dvobj_priv *pdvobj);\n\nu8 rtw_init_drv_sw(_adapter *padapter);\nu8 rtw_free_drv_sw(_adapter *padapter);\nu8 rtw_reset_drv_sw(_adapter *padapter);\nvoid rtw_dev_unload(PADAPTER padapter);\n\nu32 rtw_start_drv_threads(_adapter *padapter);\nvoid rtw_stop_drv_threads(_adapter *padapter);\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\nvoid rtw_cancel_dynamic_chk_timer(_adapter *padapter);\n#endif\nvoid rtw_cancel_all_timer(_adapter *padapter);\n\nuint loadparam(_adapter *adapter);\n\n#ifdef PLATFORM_LINUX\nint rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);\n\nint rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname);\nstruct net_device *rtw_init_netdev(_adapter *padapter);\n\nvoid rtw_os_ndev_free(_adapter *adapter);\nint rtw_os_ndev_init(_adapter *adapter, const char *name);\nvoid rtw_os_ndev_deinit(_adapter *adapter);\nvoid rtw_os_ndev_unregister(_adapter *adapter);\nvoid rtw_os_ndevs_unregister(struct dvobj_priv *dvobj);\nint rtw_os_ndevs_init(struct dvobj_priv *dvobj);\nvoid rtw_os_ndevs_deinit(struct dvobj_priv *dvobj);\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\nu16 rtw_recv_select_queue(struct sk_buff *skb);\n#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) */\n\nint rtw_ndev_notifier_register(void);\nvoid rtw_ndev_notifier_unregister(void);\nvoid rtw_inetaddr_notifier_register(void);\nvoid rtw_inetaddr_notifier_unregister(void);\n\n#include \"../os_dep/linux/rtw_proc.h\"\n\n#ifdef CONFIG_IOCTL_CFG80211\n\t#include \"../os_dep/linux/ioctl_cfg80211.h\"\n#endif /* CONFIG_IOCTL_CFG80211 */\n\nu8 rtw_rtnl_lock_needed(struct dvobj_priv *dvobj);\nvoid rtw_set_rtnl_lock_holder(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl);\n\n#endif /* PLATFORM_LINUX */\n\n\n#ifdef PLATFORM_FREEBSD\nextern int rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);\n#endif\n\nvoid rtw_ips_dev_unload(_adapter *padapter);\n\n#ifdef CONFIG_IPS\nint rtw_ips_pwr_up(_adapter *padapter);\nvoid rtw_ips_pwr_down(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_CONCURRENT_MODE\nstruct _io_ops;\nstruct dvobj_priv;\n_adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, void (*set_intf_ops)(_adapter *primary_padapter, struct _io_ops *pops));\nvoid rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj);\nvoid rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj);\n#endif\n\nvoid rtw_ndev_destructor(_nic_hdl ndev);\n#ifdef CONFIG_ARP_KEEP_ALIVE\nint rtw_gw_addr_query(_adapter *padapter);\n#endif\n\nint rtw_suspend_common(_adapter *padapter);\nint rtw_resume_common(_adapter *padapter);\n\n#endif /* _OSDEP_INTF_H_ */\n"
  },
  {
    "path": "include/osdep_service.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __OSDEP_SERVICE_H_\n#define __OSDEP_SERVICE_H_\n\n\n#define _FAIL\t\t\t\t\t0\n#define _SUCCESS\t\t\t\t1\n#define RTW_RX_HANDLED\t\t\t2\n#define RTW_RFRAME_UNAVAIL\t\t3\n#define RTW_RFRAME_PKT_UNAVAIL\t4\n#define RTW_RBUF_UNAVAIL\t\t5\n#define RTW_RBUF_PKT_UNAVAIL\t6\n#define RTW_SDIO_READ_PORT_FAIL\t7\n#define RTW_ALREADY\t\t\t\t8\n#define RTW_RA_RESOLVING\t\t9\n#define RTW_BMC_NO_NEED\t\t\t10\n\n/* #define RTW_STATUS_TIMEDOUT -110 */\n\n#undef _TRUE\n#define _TRUE\t\t1\n\n#undef _FALSE\n#define _FALSE\t\t0\n\n\n#ifdef PLATFORM_FREEBSD\n\t#include <osdep_service_bsd.h>\n#endif\n\n#ifdef PLATFORM_LINUX\n\t#include <linux/version.h>\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0))\n\t#include <linux/sched/signal.h>\n\t#include <linux/sched/types.h>\n#endif\n\t#include <osdep_service_linux.h>\n\t#include <drv_types_linux.h>\n#endif\n\n#ifdef PLATFORM_OS_XP\n\t#include <osdep_service_xp.h>\n\t#include <drv_types_xp.h>\n#endif\n\n#ifdef PLATFORM_OS_CE\n\t#include <osdep_service_ce.h>\n\t#include <drv_types_ce.h>\n#endif\n\n/* #include <rtw_byteorder.h> */\n\n#ifndef BIT\n\t#define BIT(x)\t(1 << (x))\n#endif\n\n#define CHECK_BIT(a, b) (!!((a) & (b)))\n\n#define BIT0\t0x00000001\n#define BIT1\t0x00000002\n#define BIT2\t0x00000004\n#define BIT3\t0x00000008\n#define BIT4\t0x00000010\n#define BIT5\t0x00000020\n#define BIT6\t0x00000040\n#define BIT7\t0x00000080\n#define BIT8\t0x00000100\n#define BIT9\t0x00000200\n#define BIT10\t0x00000400\n#define BIT11\t0x00000800\n#define BIT12\t0x00001000\n#define BIT13\t0x00002000\n#define BIT14\t0x00004000\n#define BIT15\t0x00008000\n#define BIT16\t0x00010000\n#define BIT17\t0x00020000\n#define BIT18\t0x00040000\n#define BIT19\t0x00080000\n#define BIT20\t0x00100000\n#define BIT21\t0x00200000\n#define BIT22\t0x00400000\n#define BIT23\t0x00800000\n#define BIT24\t0x01000000\n#define BIT25\t0x02000000\n#define BIT26\t0x04000000\n#define BIT27\t0x08000000\n#define BIT28\t0x10000000\n#define BIT29\t0x20000000\n#define BIT30\t0x40000000\n#define BIT31\t0x80000000\n#define BIT32\t0x0100000000\n#define BIT33\t0x0200000000\n#define BIT34\t0x0400000000\n#define BIT35\t0x0800000000\n#define BIT36\t0x1000000000\n\nextern int RTW_STATUS_CODE(int error_code);\n\n#ifndef RTK_DMP_PLATFORM\n\t#define CONFIG_USE_VMALLOC\n#endif\n\n/* flags used for rtw_mstat_update() */\nenum mstat_f {\n\t/* type: 0x00ff */\n\tMSTAT_TYPE_VIR = 0x00,\n\tMSTAT_TYPE_PHY = 0x01,\n\tMSTAT_TYPE_SKB = 0x02,\n\tMSTAT_TYPE_USB = 0x03,\n\tMSTAT_TYPE_MAX = 0x04,\n\n\t/* func: 0xff00 */\n\tMSTAT_FUNC_UNSPECIFIED = 0x00 << 8,\n\tMSTAT_FUNC_IO = 0x01 << 8,\n\tMSTAT_FUNC_TX_IO = 0x02 << 8,\n\tMSTAT_FUNC_RX_IO = 0x03 << 8,\n\tMSTAT_FUNC_TX = 0x04 << 8,\n\tMSTAT_FUNC_RX = 0x05 << 8,\n\tMSTAT_FUNC_CFG_VENDOR = 0x06 << 8,\n\tMSTAT_FUNC_MAX = 0x07 << 8,\n};\n\n#define mstat_tf_idx(flags) ((flags) & 0xff)\n#define mstat_ff_idx(flags) (((flags) & 0xff00) >> 8)\n\ntypedef enum mstat_status {\n\tMSTAT_ALLOC_SUCCESS = 0,\n\tMSTAT_ALLOC_FAIL,\n\tMSTAT_FREE\n} MSTAT_STATUS;\n\n#ifdef DBG_MEM_ALLOC\nvoid rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz);\nvoid rtw_mstat_dump(void *sel);\nbool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size);\nvoid *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);\nvoid *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);\nvoid dbg_rtw_vmfree(void *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line);\nvoid *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line);\nvoid *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);\nvoid dbg_rtw_mfree(void *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line);\n\nstruct sk_buff *dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, const int line);\nvoid dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);\nstruct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);\nstruct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);\nint dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);\n#ifdef CONFIG_RTW_NAPI\nint dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);\n#ifdef CONFIG_RTW_GRO\ngro_result_t dbg_rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);\n#endif\n#endif /* CONFIG_RTW_NAPI */\nvoid dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line);\n#ifdef CONFIG_USB_HCI\nvoid *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, const int line);\nvoid dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, const int line);\n#endif /* CONFIG_USB_HCI */\n\n#ifdef CONFIG_USE_VMALLOC\n#define rtw_vmalloc(sz)\t\t\tdbg_rtw_vmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)\n#define rtw_zvmalloc(sz)\t\t\tdbg_rtw_zvmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)\n#define rtw_vmfree(pbuf, sz)\t\tdbg_rtw_vmfree((pbuf), (sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)\n#define rtw_vmalloc_f(sz, mstat_f)\t\t\tdbg_rtw_vmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)\n#define rtw_zvmalloc_f(sz, mstat_f)\t\tdbg_rtw_zvmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)\n#define rtw_vmfree_f(pbuf, sz, mstat_f)\tdbg_rtw_vmfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)\n#else /* CONFIG_USE_VMALLOC */\n#define rtw_vmalloc(sz)\t\t\tdbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)\n#define rtw_zvmalloc(sz)\t\t\tdbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)\n#define rtw_vmfree(pbuf, sz)\t\tdbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)\n#define rtw_vmalloc_f(sz, mstat_f)\t\t\tdbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)\n#define rtw_zvmalloc_f(sz, mstat_f)\t\tdbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)\n#define rtw_vmfree_f(pbuf, sz, mstat_f)\tdbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)\n#endif /* CONFIG_USE_VMALLOC */\n#define rtw_malloc(sz)\t\t\tdbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)\n#define rtw_zmalloc(sz)\t\t\tdbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)\n#define rtw_mfree(pbuf, sz)\t\tdbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)\n#define rtw_malloc_f(sz, mstat_f)\t\t\tdbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)\n#define rtw_zmalloc_f(sz, mstat_f)\t\t\tdbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)\n#define rtw_mfree_f(pbuf, sz, mstat_f)\t\tdbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)\n\n#define rtw_skb_alloc(size)\tdbg_rtw_skb_alloc((size), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)\n#define rtw_skb_free(skb)\tdbg_rtw_skb_free((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)\n#define rtw_skb_alloc_f(size, mstat_f)\tdbg_rtw_skb_alloc((size), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)\n#define rtw_skb_free_f(skb, mstat_f)\tdbg_rtw_skb_free((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)\n#define rtw_skb_copy(skb)\tdbg_rtw_skb_copy((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)\n#define rtw_skb_clone(skb)\tdbg_rtw_skb_clone((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)\n#define rtw_skb_copy_f(skb, mstat_f)\tdbg_rtw_skb_copy((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)\n#define rtw_skb_clone_f(skb, mstat_f)\tdbg_rtw_skb_clone((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)\n#define rtw_netif_rx(ndev, skb)\tdbg_rtw_netif_rx(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)\n#ifdef CONFIG_RTW_NAPI\n#define rtw_netif_receive_skb(ndev, skb) dbg_rtw_netif_receive_skb(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)\n#ifdef CONFIG_RTW_GRO\n#define rtw_napi_gro_receive(napi, skb) dbg_rtw_napi_gro_receive(napi, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)\n#endif\n#endif /* CONFIG_RTW_NAPI */\n#define rtw_skb_queue_purge(sk_buff_head) dbg_rtw_skb_queue_purge(sk_buff_head, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)\n#ifdef CONFIG_USB_HCI\n#define rtw_usb_buffer_alloc(dev, size, dma)\t\tdbg_rtw_usb_buffer_alloc((dev), (size), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__)\n#define rtw_usb_buffer_free(dev, size, addr, dma)\tdbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__)\n#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f)\t\t\tdbg_rtw_usb_buffer_alloc((dev), (size), (dma), ((mstat_f) & 0xff00) | MSTAT_TYPE_USB, __FUNCTION__, __LINE__)\n#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f)\tdbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), ((mstat_f) & 0xff00) | MSTAT_TYPE_USB, __FUNCTION__, __LINE__)\n#endif /* CONFIG_USB_HCI */\n\n#else /* DBG_MEM_ALLOC */\n#define rtw_mstat_update(flag, status, sz) do {} while (0)\n#define rtw_mstat_dump(sel) do {} while (0)\n#define match_mstat_sniff_rules(flags, size) _FALSE\nvoid *_rtw_vmalloc(u32 sz);\nvoid *_rtw_zvmalloc(u32 sz);\nvoid _rtw_vmfree(void *pbuf, u32 sz);\nvoid *_rtw_zmalloc(u32 sz);\nvoid *_rtw_malloc(u32 sz);\nvoid _rtw_mfree(void *pbuf, u32 sz);\n\nstruct sk_buff *_rtw_skb_alloc(u32 sz);\nvoid _rtw_skb_free(struct sk_buff *skb);\nstruct sk_buff *_rtw_skb_copy(const struct sk_buff *skb);\nstruct sk_buff *_rtw_skb_clone(struct sk_buff *skb);\nint _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb);\n#ifdef CONFIG_RTW_NAPI\nint _rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb);\n#ifdef CONFIG_RTW_GRO\ngro_result_t _rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb);\n#endif\n#endif /* CONFIG_RTW_NAPI */\nvoid _rtw_skb_queue_purge(struct sk_buff_head *list);\n\n#ifdef CONFIG_USB_HCI\nvoid *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma);\nvoid _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma);\n#endif /* CONFIG_USB_HCI */\n\n#ifdef CONFIG_USE_VMALLOC\n#define rtw_vmalloc(sz)\t\t\t_rtw_vmalloc((sz))\n#define rtw_zvmalloc(sz)\t\t\t_rtw_zvmalloc((sz))\n#define rtw_vmfree(pbuf, sz)\t\t_rtw_vmfree((pbuf), (sz))\n#define rtw_vmalloc_f(sz, mstat_f)\t\t\t_rtw_vmalloc((sz))\n#define rtw_zvmalloc_f(sz, mstat_f)\t\t_rtw_zvmalloc((sz))\n#define rtw_vmfree_f(pbuf, sz, mstat_f)\t_rtw_vmfree((pbuf), (sz))\n#else /* CONFIG_USE_VMALLOC */\n#define rtw_vmalloc(sz)\t\t\t_rtw_malloc((sz))\n#define rtw_zvmalloc(sz)\t\t\t_rtw_zmalloc((sz))\n#define rtw_vmfree(pbuf, sz)\t\t_rtw_mfree((pbuf), (sz))\n#define rtw_vmalloc_f(sz, mstat_f)\t\t\t_rtw_malloc((sz))\n#define rtw_zvmalloc_f(sz, mstat_f)\t\t_rtw_zmalloc((sz))\n#define rtw_vmfree_f(pbuf, sz, mstat_f)\t_rtw_mfree((pbuf), (sz))\n#endif /* CONFIG_USE_VMALLOC */\n#define rtw_malloc(sz)\t\t\t_rtw_malloc((sz))\n#define rtw_zmalloc(sz)\t\t\t_rtw_zmalloc((sz))\n#define rtw_mfree(pbuf, sz)\t\t_rtw_mfree((pbuf), (sz))\n#define rtw_malloc_f(sz, mstat_f)\t\t\t_rtw_malloc((sz))\n#define rtw_zmalloc_f(sz, mstat_f)\t\t\t_rtw_zmalloc((sz))\n#define rtw_mfree_f(pbuf, sz, mstat_f)\t\t_rtw_mfree((pbuf), (sz))\n\n#define rtw_skb_alloc(size) _rtw_skb_alloc((size))\n#define rtw_skb_free(skb) _rtw_skb_free((skb))\n#define rtw_skb_alloc_f(size, mstat_f)\t_rtw_skb_alloc((size))\n#define rtw_skb_free_f(skb, mstat_f)\t_rtw_skb_free((skb))\n#define rtw_skb_copy(skb)\t_rtw_skb_copy((skb))\n#define rtw_skb_clone(skb)\t_rtw_skb_clone((skb))\n#define rtw_skb_copy_f(skb, mstat_f)\t_rtw_skb_copy((skb))\n#define rtw_skb_clone_f(skb, mstat_f)\t_rtw_skb_clone((skb))\n#define rtw_netif_rx(ndev, skb) _rtw_netif_rx(ndev, skb)\n#ifdef CONFIG_RTW_NAPI\n#define rtw_netif_receive_skb(ndev, skb) _rtw_netif_receive_skb(ndev, skb)\n#ifdef CONFIG_RTW_GRO\n#define rtw_napi_gro_receive(napi, skb) _rtw_napi_gro_receive(napi, skb)\n#endif\n#endif /* CONFIG_RTW_NAPI */\n#define rtw_skb_queue_purge(sk_buff_head) _rtw_skb_queue_purge(sk_buff_head)\n#ifdef CONFIG_USB_HCI\n#define rtw_usb_buffer_alloc(dev, size, dma) _rtw_usb_buffer_alloc((dev), (size), (dma))\n#define rtw_usb_buffer_free(dev, size, addr, dma) _rtw_usb_buffer_free((dev), (size), (addr), (dma))\n#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) _rtw_usb_buffer_alloc((dev), (size), (dma))\n#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) _rtw_usb_buffer_free((dev), (size), (addr), (dma))\n#endif /* CONFIG_USB_HCI */\n#endif /* DBG_MEM_ALLOC */\n\nextern void\t*rtw_malloc2d(int h, int w, size_t size);\nextern void\trtw_mfree2d(void *pbuf, int h, int w, int size);\n\nvoid rtw_os_pkt_free(_pkt *pkt);\n_pkt *rtw_os_pkt_copy(_pkt *pkt);\nvoid *rtw_os_pkt_data(_pkt *pkt);\nu32 rtw_os_pkt_len(_pkt *pkt);\n\nextern void\t_rtw_memcpy(void *dec, const void *sour, u32 sz);\nextern void _rtw_memmove(void *dst, const void *src, u32 sz);\nextern int\t_rtw_memcmp(const void *dst, const void *src, u32 sz);\nextern void\t_rtw_memset(void *pbuf, int c, u32 sz);\n\nextern void\t_rtw_init_listhead(_list *list);\nextern u32\trtw_is_list_empty(_list *phead);\nextern void\trtw_list_insert_head(_list *plist, _list *phead);\nextern void\trtw_list_insert_tail(_list *plist, _list *phead);\nvoid rtw_list_splice(_list *list, _list *head);\nvoid rtw_list_splice_init(_list *list, _list *head);\nvoid rtw_list_splice_tail(_list *list, _list *head);\n\n#ifndef PLATFORM_FREEBSD\nextern void\trtw_list_delete(_list *plist);\n#endif /* PLATFORM_FREEBSD */\n\nvoid rtw_hlist_head_init(rtw_hlist_head *h);\nvoid rtw_hlist_add_head(rtw_hlist_node *n, rtw_hlist_head *h);\nvoid rtw_hlist_del(rtw_hlist_node *n);\nvoid rtw_hlist_add_head_rcu(rtw_hlist_node *n, rtw_hlist_head *h);\nvoid rtw_hlist_del_rcu(rtw_hlist_node *n);\n\nextern void\t_rtw_init_sema(_sema *sema, int init_val);\nextern void\t_rtw_free_sema(_sema\t*sema);\nextern void\t_rtw_up_sema(_sema\t*sema);\nextern u32\t_rtw_down_sema(_sema *sema);\nextern void\t_rtw_mutex_init(_mutex *pmutex);\nextern void\t_rtw_mutex_free(_mutex *pmutex);\n#ifndef PLATFORM_FREEBSD\nextern void\t_rtw_spinlock_init(_lock *plock);\n#endif /* PLATFORM_FREEBSD */\nextern void\t_rtw_spinlock_free(_lock *plock);\nextern void\t_rtw_spinlock(_lock\t*plock);\nextern void\t_rtw_spinunlock(_lock\t*plock);\nextern void\t_rtw_spinlock_ex(_lock\t*plock);\nextern void\t_rtw_spinunlock_ex(_lock\t*plock);\n\nextern void\t_rtw_init_queue(_queue *pqueue);\nextern void _rtw_deinit_queue(_queue *pqueue);\nextern u32\t_rtw_queue_empty(_queue\t*pqueue);\nextern u32\trtw_end_of_queue_search(_list *queue, _list *pelement);\n\nextern systime _rtw_get_current_time(void);\nextern u32\t_rtw_systime_to_ms(systime stime);\nextern systime _rtw_ms_to_systime(u32 ms);\nextern systime _rtw_us_to_systime(u32 us);\nextern s32\t_rtw_get_passing_time_ms(systime start);\nextern s32 _rtw_get_remaining_time_ms(systime end);\nextern s32\t_rtw_get_time_interval_ms(systime start, systime end);\nextern bool _rtw_time_after(systime a, systime b);\n\n#ifdef DBG_SYSTIME\n#define rtw_get_current_time() ({systime __stime = _rtw_get_current_time(); __stime;})\n#define rtw_systime_to_ms(stime) ({u32 __ms = _rtw_systime_to_ms(stime); typecheck(systime, stime); __ms;})\n#define rtw_ms_to_systime(ms) ({systime __stime = _rtw_ms_to_systime(ms); __stime;})\n#define rtw_us_to_systime(us) ({systime __stime = _rtw_us_to_systime(us); __stime;})\n#define rtw_get_passing_time_ms(start) ({u32 __ms = _rtw_get_passing_time_ms(start); typecheck(systime, start); __ms;})\n#define rtw_get_remaining_time_ms(end) ({u32 __ms = _rtw_get_remaining_time_ms(end); typecheck(systime, end); __ms;})\n#define rtw_get_time_interval_ms(start, end) ({u32 __ms = _rtw_get_time_interval_ms(start, end); typecheck(systime, start); typecheck(systime, end); __ms;})\n#define rtw_time_after(a,b) ({bool __r = _rtw_time_after(a,b); typecheck(systime, a); typecheck(systime, b); __r;})\n#define rtw_time_before(a,b) ({bool __r = _rtw_time_after(b, a); typecheck(systime, a); typecheck(systime, b); __r;})\n#else\n#define rtw_get_current_time() _rtw_get_current_time()\n#define rtw_systime_to_ms(stime) _rtw_systime_to_ms(stime)\n#define rtw_ms_to_systime(ms) _rtw_ms_to_systime(ms)\n#define rtw_us_to_systime(us) _rtw_us_to_systime(us)\n#define rtw_get_passing_time_ms(start) _rtw_get_passing_time_ms(start)\n#define rtw_get_remaining_time_ms(end) _rtw_get_remaining_time_ms(end)\n#define rtw_get_time_interval_ms(start, end) _rtw_get_time_interval_ms(start, end)\n#define rtw_time_after(a,b) _rtw_time_after(a,b)\n#define rtw_time_before(a,b) _rtw_time_after(b,a)\n#endif\n\nextern void\trtw_sleep_schedulable(int ms);\n\nextern void\trtw_msleep_os(int ms);\nextern void\trtw_usleep_os(int us);\n\nextern u32\trtw_atoi(u8 *s);\n\n#ifdef DBG_DELAY_OS\n#define rtw_mdelay_os(ms) _rtw_mdelay_os((ms), __FUNCTION__, __LINE__)\n#define rtw_udelay_os(ms) _rtw_udelay_os((ms), __FUNCTION__, __LINE__)\nextern void _rtw_mdelay_os(int ms, const char *func, const int line);\nextern void _rtw_udelay_os(int us, const char *func, const int line);\n#else\nextern void\trtw_mdelay_os(int ms);\nextern void\trtw_udelay_os(int us);\n#endif\n\nextern void rtw_yield_os(void);\n\n\nextern void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx);\n\n\n__inline static unsigned char _cancel_timer_ex(_timer *ptimer)\n{\n\tu8 bcancelled;\n\n\t_cancel_timer(ptimer, &bcancelled);\n\n\treturn bcancelled;\n}\n\nstatic __inline void thread_enter(char *name)\n{\n#ifdef PLATFORM_LINUX\n\tallow_signal(SIGTERM);\n#endif\n#ifdef PLATFORM_FREEBSD\n\tprintf(\"%s\", \"RTKTHREAD_enter\");\n#endif\n}\n__noreturn void thread_exit(_completion *comp);\nvoid _rtw_init_completion(_completion *comp);\nvoid _rtw_wait_for_comp_timeout(_completion *comp);\nvoid _rtw_wait_for_comp(_completion *comp);\n\nstatic inline bool rtw_thread_stop(_thread_hdl_ th)\n{\n#ifdef PLATFORM_LINUX\n\treturn kthread_stop(th);\n#endif\n}\nstatic inline void rtw_thread_wait_stop(void)\n{\n#ifdef PLATFORM_LINUX\n\t#if 0\n\twhile (!kthread_should_stop())\n\t\trtw_msleep_os(10);\n\t#else\n\tset_current_state(TASK_INTERRUPTIBLE);\n\twhile (!kthread_should_stop()) {\n\t\tschedule();\n\t\tset_current_state(TASK_INTERRUPTIBLE);\n\t}\n\t__set_current_state(TASK_RUNNING);\n\t#endif\n#endif\n}\n\n__inline static void flush_signals_thread(void)\n{\n#ifdef PLATFORM_LINUX\n\tif (signal_pending(current))\n\t\tflush_signals(current);\n#endif\n}\n\n__inline static _OS_STATUS res_to_status(sint res)\n{\n\n#if defined(PLATFORM_LINUX) || defined (PLATFORM_MPIXEL) || defined (PLATFORM_FREEBSD)\n\treturn res;\n#endif\n\n#ifdef PLATFORM_WINDOWS\n\n\tif (res == _SUCCESS)\n\t\treturn NDIS_STATUS_SUCCESS;\n\telse\n\t\treturn NDIS_STATUS_FAILURE;\n\n#endif\n\n}\n\n__inline static void rtw_dump_stack(void)\n{\n#ifdef PLATFORM_LINUX\n\tdump_stack();\n#endif\n}\n\n#ifdef PLATFORM_LINUX\n#define rtw_warn_on(condition) WARN_ON(condition)\n#else\n#define rtw_warn_on(condition) do {} while (0)\n#endif\n\n__inline static int rtw_bug_check(void *parg1, void *parg2, void *parg3, void *parg4)\n{\n\tint ret = _TRUE;\n\n#ifdef PLATFORM_WINDOWS\n\tif (((uint)parg1) <= 0x7fffffff ||\n\t    ((uint)parg2) <= 0x7fffffff ||\n\t    ((uint)parg3) <= 0x7fffffff ||\n\t    ((uint)parg4) <= 0x7fffffff) {\n\t\tret = _FALSE;\n\t\tKeBugCheckEx(0x87110000, (ULONG_PTR)parg1, (ULONG_PTR)parg2, (ULONG_PTR)parg3, (ULONG_PTR)parg4);\n\t}\n#endif\n\n\treturn ret;\n\n}\n#ifdef PLATFORM_LINUX\n#define RTW_DIV_ROUND_UP(n, d)\tDIV_ROUND_UP(n, d)\n#else /* !PLATFORM_LINUX */\n#define RTW_DIV_ROUND_UP(n, d)\t(((n) + (d - 1)) / d)\n#endif /* !PLATFORM_LINUX */\n\n#define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r))\n#define RND4(x)\t(((x >> 2) + (((x & 3) == 0) ? 0 : 1)) << 2)\n\n__inline static u32 _RND4(u32 sz)\n{\n\n\tu32\tval;\n\n\tval = ((sz >> 2) + ((sz & 3) ? 1 : 0)) << 2;\n\n\treturn val;\n\n}\n\n__inline static u32 _RND8(u32 sz)\n{\n\n\tu32\tval;\n\n\tval = ((sz >> 3) + ((sz & 7) ? 1 : 0)) << 3;\n\n\treturn val;\n\n}\n\n__inline static u32 _RND128(u32 sz)\n{\n\n\tu32\tval;\n\n\tval = ((sz >> 7) + ((sz & 127) ? 1 : 0)) << 7;\n\n\treturn val;\n\n}\n\n__inline static u32 _RND256(u32 sz)\n{\n\n\tu32\tval;\n\n\tval = ((sz >> 8) + ((sz & 255) ? 1 : 0)) << 8;\n\n\treturn val;\n\n}\n\n__inline static u32 _RND512(u32 sz)\n{\n\n\tu32\tval;\n\n\tval = ((sz >> 9) + ((sz & 511) ? 1 : 0)) << 9;\n\n\treturn val;\n\n}\n\n__inline static u32 bitshift(u32 bitmask)\n{\n\tu32 i;\n\n\tfor (i = 0; i <= 31; i++)\n\t\tif (((bitmask >> i) &  0x1) == 1)\n\t\t\tbreak;\n\n\treturn i;\n}\n\nstatic inline int largest_bit(u32 bitmask)\n{\n\tint i;\n\n\tfor (i = 31; i >= 0; i--)\n\t\tif (bitmask & BIT(i))\n\t\t\tbreak;\n\n\treturn i;\n}\n\n#define rtw_abs(a) (a < 0 ? -a : a)\n#define rtw_min(a, b) ((a > b) ? b : a)\n#define rtw_is_range_a_in_b(hi_a, lo_a, hi_b, lo_b) (((hi_a) <= (hi_b)) && ((lo_a) >= (lo_b)))\n#define rtw_is_range_overlap(hi_a, lo_a, hi_b, lo_b) (((hi_a) > (lo_b)) && ((lo_a) < (hi_b)))\n\n#ifndef MAC_FMT\n#define MAC_FMT \"%02x:%02x:%02x:%02x:%02x:%02x\"\n#endif\n#ifndef MAC_ARG\n#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5]\n#endif\n\nbool rtw_macaddr_is_larger(const u8 *a, const u8 *b);\n\nextern void rtw_suspend_lock_init(void);\nextern void rtw_suspend_lock_uninit(void);\nextern void rtw_lock_suspend(void);\nextern void rtw_unlock_suspend(void);\nextern void rtw_lock_suspend_timeout(u32 timeout_ms);\nextern void rtw_lock_traffic_suspend_timeout(u32 timeout_ms);\nextern void rtw_resume_lock_suspend(void);\nextern void rtw_resume_unlock_suspend(void);\n#ifdef CONFIG_AP_WOWLAN\nextern void rtw_softap_lock_suspend(void);\nextern void rtw_softap_unlock_suspend(void);\n#endif\n\nextern void rtw_set_bit(int nr, unsigned long *addr);\nextern void rtw_clear_bit(int nr, unsigned long *addr);\nextern int rtw_test_and_clear_bit(int nr, unsigned long *addr);\n\nextern void ATOMIC_SET(ATOMIC_T *v, int i);\nextern int ATOMIC_READ(ATOMIC_T *v);\nextern void ATOMIC_ADD(ATOMIC_T *v, int i);\nextern void ATOMIC_SUB(ATOMIC_T *v, int i);\nextern void ATOMIC_INC(ATOMIC_T *v);\nextern void ATOMIC_DEC(ATOMIC_T *v);\nextern int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i);\nextern int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i);\nextern int ATOMIC_INC_RETURN(ATOMIC_T *v);\nextern int ATOMIC_DEC_RETURN(ATOMIC_T *v);\nextern bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u);\n\n/* File operation APIs, just for linux now */\nextern int rtw_is_file_readable(const char *path);\nextern int rtw_is_file_readable_with_size(const char *path, u32 *sz);\nextern int rtw_readable_file_sz_chk(const char *path, u32 sz);\nextern int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz);\nextern int rtw_store_to_file(const char *path, u8 *buf, u32 sz);\n\n\n#ifndef PLATFORM_FREEBSD\nextern void rtw_free_netdev(struct net_device *netdev);\n#endif /* PLATFORM_FREEBSD */\n\n\nextern u64 rtw_modular64(u64 x, u64 y);\nextern u64 rtw_division64(u64 x, u64 y);\nextern u32 rtw_random32(void);\n\n/* Macros for handling unaligned memory accesses */\n\n#define RTW_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1]))\n#define RTW_PUT_BE16(a, val)\t\t\t\\\n\tdo {\t\t\t\t\t\\\n\t\t(a)[0] = ((u16) (val)) >> 8;\t\\\n\t\t(a)[1] = ((u16) (val)) & 0xff;\t\\\n\t} while (0)\n\n#define RTW_GET_LE16(a) ((u16) (((a)[1] << 8) | (a)[0]))\n#define RTW_PUT_LE16(a, val)\t\t\t\\\n\tdo {\t\t\t\t\t\\\n\t\t(a)[1] = ((u16) (val)) >> 8;\t\\\n\t\t(a)[0] = ((u16) (val)) & 0xff;\t\\\n\t} while (0)\n\n#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \\\n\t\t\t ((u32) (a)[2]))\n#define RTW_PUT_BE24(a, val)\t\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\t(a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff);\t\\\n\t\t(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff);\t\\\n\t\t(a)[2] = (u8) (((u32) (val)) & 0xff);\t\t\\\n\t} while (0)\n\n#define RTW_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \\\n\t\t\t (((u32) (a)[2]) << 8) | ((u32) (a)[3]))\n#define RTW_PUT_BE32(a, val)\t\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\t(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff);\t\\\n\t\t(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff);\t\\\n\t\t(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff);\t\\\n\t\t(a)[3] = (u8) (((u32) (val)) & 0xff);\t\t\\\n\t} while (0)\n\n#define RTW_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \\\n\t\t\t (((u32) (a)[1]) << 8) | ((u32) (a)[0]))\n#define RTW_PUT_LE32(a, val)\t\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\t(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff);\t\\\n\t\t(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff);\t\\\n\t\t(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff);\t\\\n\t\t(a)[0] = (u8) (((u32) (val)) & 0xff);\t\t\\\n\t} while (0)\n\n#define RTW_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \\\n\t\t\t (((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \\\n\t\t\t (((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \\\n\t\t\t (((u64) (a)[6]) << 8) | ((u64) (a)[7]))\n#define RTW_PUT_BE64(a, val)\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\\\n\t\t(a)[0] = (u8) (((u64) (val)) >> 56);\t\\\n\t\t(a)[1] = (u8) (((u64) (val)) >> 48);\t\\\n\t\t(a)[2] = (u8) (((u64) (val)) >> 40);\t\\\n\t\t(a)[3] = (u8) (((u64) (val)) >> 32);\t\\\n\t\t(a)[4] = (u8) (((u64) (val)) >> 24);\t\\\n\t\t(a)[5] = (u8) (((u64) (val)) >> 16);\t\\\n\t\t(a)[6] = (u8) (((u64) (val)) >> 8);\t\\\n\t\t(a)[7] = (u8) (((u64) (val)) & 0xff);\t\\\n\t} while (0)\n\n#define RTW_GET_LE64(a) ((((u64) (a)[7]) << 56) | (((u64) (a)[6]) << 48) | \\\n\t\t\t (((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \\\n\t\t\t (((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \\\n\t\t\t (((u64) (a)[1]) << 8) | ((u64) (a)[0]))\n#define RTW_PUT_LE64(a, val)\t\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\t(a)[7] = (u8) ((((u64) (val)) >> 56) & 0xff);\t\\\n\t\t(a)[6] = (u8) ((((u64) (val)) >> 48) & 0xff);\t\\\n\t\t(a)[5] = (u8) ((((u64) (val)) >> 40) & 0xff);\t\\\n\t\t(a)[4] = (u8) ((((u64) (val)) >> 32) & 0xff);\t\\\n\t\t(a)[3] = (u8) ((((u64) (val)) >> 24) & 0xff);\t\\\n\t\t(a)[2] = (u8) ((((u64) (val)) >> 16) & 0xff);\t\\\n\t\t(a)[1] = (u8) ((((u64) (val)) >> 8) & 0xff);\t\\\n\t\t(a)[0] = (u8) (((u64) (val)) & 0xff);\t\t\\\n\t} while (0)\n\nvoid rtw_buf_free(u8 **buf, u32 *buf_len);\nvoid rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len);\n\nstruct rtw_cbuf {\n\tu32 write;\n\tu32 read;\n\tu32 size;\n\tvoid *bufs[0];\n};\n\nbool rtw_cbuf_full(struct rtw_cbuf *cbuf);\nbool rtw_cbuf_empty(struct rtw_cbuf *cbuf);\nbool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf);\nvoid *rtw_cbuf_pop(struct rtw_cbuf *cbuf);\nstruct rtw_cbuf *rtw_cbuf_alloc(u32 size);\nvoid rtw_cbuf_free(struct rtw_cbuf *cbuf);\n\nstruct map_seg_t {\n\tu16 sa;\n\tu16 len;\n\tu8 *c;\n};\n\nstruct map_t {\n\tu16 len;\n\tu16 seg_num;\n\tu8 init_value;\n\tstruct map_seg_t *segs;\n};\n\n#define MAPSEG_ARRAY_ENT(_sa, _len, _c, arg...) \\\n\t{ .sa = _sa, .len = _len, .c = (u8[_len]){ _c, ##arg}, }\n\n#define MAPSEG_PTR_ENT(_sa, _len, _p) \\\n\t{ .sa = _sa, .len = _len, .c = _p, }\n\n#define MAP_ENT(_len, _seg_num, _init_v, _seg, arg...) \\\n\t{ .len = _len, .seg_num = _seg_num, .init_value = _init_v, .segs = (struct map_seg_t[_seg_num]){ _seg, ##arg}, }\n\nint map_readN(const struct map_t *map, u16 offset, u16 len, u8 *buf);\nu8 map_read8(const struct map_t *map, u16 offset);\n\nstruct blacklist_ent {\n\t_list list;\n\tu8 addr[ETH_ALEN];\n\tsystime exp_time;\n};\n\nint rtw_blacklist_add(_queue *blist, const u8 *addr, u32 timeout_ms);\nint rtw_blacklist_del(_queue *blist, const u8 *addr);\nint rtw_blacklist_search(_queue *blist, const u8 *addr);\nvoid rtw_blacklist_flush(_queue *blist);\nvoid dump_blacklist(void *sel, _queue *blist, const char *title);\n\n/* String handler */\n\nBOOLEAN is_null(char c);\nBOOLEAN is_all_null(char *c, int len);\nBOOLEAN is_eol(char c);\nBOOLEAN is_space(char c);\nBOOLEAN IsHexDigit(char chTmp);\nBOOLEAN is_alpha(char chTmp);\nchar alpha_to_upper(char c);\n\nint hex2num_i(char c);\nint hex2byte_i(const char *hex);\nint hexstr2bin(const char *hex, u8 *buf, size_t len);\n\n/*\n * Write formatted output to sized buffer\n */\n#ifdef PLATFORM_LINUX\n#define rtw_sprintf(buf, size, format, arg...)\tsnprintf(buf, size, format, ##arg)\n#else /* !PLATFORM_LINUX */\n#error \"NOT DEFINE \\\"rtw_sprintf\\\"!!\"\n#endif /* !PLATFORM_LINUX */\n\n#endif\n"
  },
  {
    "path": "include/osdep_service_bsd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __OSDEP_BSD_SERVICE_H_\n#define __OSDEP_BSD_SERVICE_H_\n\n\n#include <sys/cdefs.h>\n#include <sys/types.h>\n#include <sys/systm.h>\n#include <sys/param.h>\n#include <sys/sockio.h>\n#include <sys/sysctl.h>\n#include <sys/lock.h>\n#include <sys/mutex.h>\n#include <sys/mbuf.h>\n#include <sys/kernel.h>\n#include <sys/socket.h>\n#include <sys/systm.h>\n#include <sys/malloc.h>\n#include <sys/module.h>\n#include <sys/bus.h>\n#include <sys/endian.h>\n#include <sys/kdb.h>\n#include <sys/kthread.h>\n#include <sys/malloc.h>\n#include <sys/time.h>\n#include <machine/atomic.h>\n#include <machine/bus.h>\n#include <machine/resource.h>\n#include <sys/rman.h>\n\n#include <net/bpf.h>\n#include <net/if.h>\n#include <net/if_arp.h>\n#include <net/ethernet.h>\n#include <net/if_dl.h>\n#include <net/if_media.h>\n#include <net/if_types.h>\n#include <net/route.h>\n\n\n#include <netinet/in.h>\n#include <netinet/in_systm.h>\n#include <netinet/in_var.h>\n#include <netinet/if_ether.h>\n#include <if_ether.h>\n\n#include <net80211/ieee80211_var.h>\n#include <net80211/ieee80211_regdomain.h>\n#include <net80211/ieee80211_radiotap.h>\n#include <net80211/ieee80211_ratectl.h>\n\n#include <dev/usb/usb.h>\n#include <dev/usb/usbdi.h>\n#include \"usbdevs.h\"\n\n#define\tUSB_DEBUG_VAR rum_debug\n#include <dev/usb/usb_debug.h>\n\n#if 1 //Baron porting from linux, it's all temp solution, needs to check again\n#include <sys/sema.h>\n#include <sys/pcpu.h> /* XXX for PCPU_GET */\n//\ttypedef struct \tsemaphore _sema;\n\ttypedef struct \tsema _sema;\n//\ttypedef\tspinlock_t\t_lock;\n\ttypedef\tstruct mtx\t_lock;\n\ttypedef struct mtx \t\t_mutex;\n\ttypedef struct rtw_timer_list _timer;\n\tstruct list_head {\n\tstruct list_head *next, *prev;\n\t};\n\tstruct\t__queue\t{\n\t\tstruct\tlist_head\tqueue;\t\n\t\t_lock\tlock;\n\t};\n\n\ttypedef\tstruct mbuf _pkt;\n\ttypedef struct mbuf\t_buffer;\n\t\n\ttypedef struct\t__queue\t_queue;\n\ttypedef struct\tlist_head\t_list;\n\ttypedef\tint\t_OS_STATUS;\n\t//typedef u32\t_irqL;\n\ttypedef unsigned long _irqL;\n\ttypedef\tstruct\tifnet * _nic_hdl;\n\t\n\ttypedef pid_t\t\t_thread_hdl_;\n//\ttypedef struct thread\t\t_thread_hdl_;\n\ttypedef void\t\tthread_return;\n\ttypedef void*\tthread_context;\n\n\ttypedef void timer_hdl_return;\n\ttypedef void* timer_hdl_context;\n\ttypedef struct work_struct _workitem;\n\ttypedef struct task _tasklet;\n\n#define   KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))\n/* emulate a modern version */\n#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 35)\n\n#define WIRELESS_EXT -1\n#define HZ hz\n#define spin_lock_irqsave mtx_lock_irqsave\n#define spin_lock_bh mtx_lock_irqsave\n#define mtx_lock_irqsave(lock, x) mtx_lock(lock)//{local_irq_save((x)); mtx_lock_spin((lock));}\n//#define IFT_RTW\t0xf9 //ifnet allocate type for RTW\n#define free_netdev if_free\n#define LIST_CONTAINOR(ptr, type, member) \\\n        ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))\n#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n))\n/* \n * Linux timers are emulated using FreeBSD callout functions\n * (and taskqueue functionality).\n *\n * Currently no timer stats functionality.\n *\n * See (linux_compat) processes.c\n *\n */\nstruct rtw_timer_list {\n\tstruct callout callout;\n\tvoid (*function)(void *);\n\tvoid *arg;\n};\n\nstruct workqueue_struct;\nstruct work_struct;\ntypedef void (*work_func_t)(struct work_struct *work);\n/* Values for the state of an item of work (work_struct) */\ntypedef enum work_state {\n        WORK_STATE_UNSET = 0,\n        WORK_STATE_CALLOUT_PENDING = 1,\n        WORK_STATE_TASK_PENDING = 2,\n        WORK_STATE_WORK_CANCELLED = 3        \n} work_state_t;\n\nstruct work_struct {\n        struct task task; /* FreeBSD task */\n        work_state_t state; /* the pending or otherwise state of work. */\n        work_func_t func;       \n};\n#define spin_unlock_irqrestore mtx_unlock_irqrestore\n#define spin_unlock_bh mtx_unlock_irqrestore\n#define mtx_unlock_irqrestore(lock,x)    mtx_unlock(lock);\nextern void\t_rtw_spinlock_init(_lock *plock);\n\n//modify private structure to match freebsd\n#define BITS_PER_LONG 32\nunion ktime {\n\ts64\ttv64;\n#if BITS_PER_LONG != 64 && !defined(CONFIG_KTIME_SCALAR)\n\tstruct {\n#ifdef __BIG_ENDIAN\n\ts32\tsec, nsec;\n#else\n\ts32\tnsec, sec;\n#endif\n\t} tv;\n#endif\n};\n#define kmemcheck_bitfield_begin(name)\n#define kmemcheck_bitfield_end(name)\n#define CHECKSUM_NONE 0\ntypedef unsigned char *sk_buff_data_t;\ntypedef union ktime ktime_t;\t\t/* Kill this */\n\nvoid rtw_mtx_lock(_lock *plock);\n\t\nvoid rtw_mtx_unlock(_lock *plock);\n\n/** \n *\tstruct sk_buff - socket buffer\n *\t@next: Next buffer in list\n *\t@prev: Previous buffer in list\n *\t@sk: Socket we are owned by\n *\t@tstamp: Time we arrived\n *\t@dev: Device we arrived on/are leaving by\n *\t@transport_header: Transport layer header\n *\t@network_header: Network layer header\n *\t@mac_header: Link layer header\n *\t@_skb_refdst: destination entry (with norefcount bit)\n *\t@sp: the security path, used for xfrm\n *\t@cb: Control buffer. Free for use by every layer. Put private vars here\n *\t@len: Length of actual data\n *\t@data_len: Data length\n *\t@mac_len: Length of link layer header\n *\t@hdr_len: writable header length of cloned skb\n *\t@csum: Checksum (must include start/offset pair)\n *\t@csum_start: Offset from skb->head where checksumming should start\n *\t@csum_offset: Offset from csum_start where checksum should be stored\n *\t@local_df: allow local fragmentation\n *\t@cloned: Head may be cloned (check refcnt to be sure)\n *\t@nohdr: Payload reference only, must not modify header\n *\t@pkt_type: Packet class\n *\t@fclone: skbuff clone status\n *\t@ip_summed: Driver fed us an IP checksum\n *\t@priority: Packet queueing priority\n *\t@users: User count - see {datagram,tcp}.c\n *\t@protocol: Packet protocol from driver\n *\t@truesize: Buffer size \n *\t@head: Head of buffer\n *\t@data: Data head pointer\n *\t@tail: Tail pointer\n *\t@end: End pointer\n *\t@destructor: Destruct function\n *\t@mark: Generic packet mark\n *\t@nfct: Associated connection, if any\n *\t@ipvs_property: skbuff is owned by ipvs\n *\t@peeked: this packet has been seen already, so stats have been\n *\t\tdone for it, don't do them again\n *\t@nf_trace: netfilter packet trace flag\n *\t@nfctinfo: Relationship of this skb to the connection\n *\t@nfct_reasm: netfilter conntrack re-assembly pointer\n *\t@nf_bridge: Saved data about a bridged frame - see br_netfilter.c\n *\t@skb_iif: ifindex of device we arrived on\n *\t@rxhash: the packet hash computed on receive\n *\t@queue_mapping: Queue mapping for multiqueue devices\n *\t@tc_index: Traffic control index\n *\t@tc_verd: traffic control verdict\n *\t@ndisc_nodetype: router type (from link layer)\n *\t@dma_cookie: a cookie to one of several possible DMA operations\n *\t\tdone by skb DMA functions\n *\t@secmark: security marking\n *\t@vlan_tci: vlan tag control information\n */\n\nstruct sk_buff {\n\t/* These two members must be first. */\n\tstruct sk_buff\t\t*next;\n\tstruct sk_buff\t\t*prev;\n\n\tktime_t\t\t\ttstamp;\n\n\tstruct sock\t\t*sk;\n\t//struct net_device\t*dev;\n\tstruct ifnet *dev;\n\n\t/*\n\t * This is the control buffer. It is free to use for every\n\t * layer. Please put your private variables there. If you\n\t * want to keep them across layers you have to do a skb_clone()\n\t * first. This is owned by whoever has the skb queued ATM.\n\t */\n\tchar\t\t\tcb[48] __aligned(8);\n\n\tunsigned long\t\t_skb_refdst;\n#ifdef CONFIG_XFRM\n\tstruct\tsec_path\t*sp;\n#endif\n\tunsigned int\t\tlen,\n\t\t\t\tdata_len;\n\tu16\t\t\tmac_len,\n\t\t\t\thdr_len;\n\tunion {\n\t\tu32\t\tcsum;\n\t\tstruct {\n\t\t\tu16\tcsum_start;\n\t\t\tu16\tcsum_offset;\n\t\t}smbol2;\n\t}smbol1;\n\tu32\t\t\tpriority;\n\tkmemcheck_bitfield_begin(flags1);\n\tu8\t\t\tlocal_df:1,\n\t\t\t\tcloned:1,\n\t\t\t\tip_summed:2,\n\t\t\t\tnohdr:1,\n\t\t\t\tnfctinfo:3;\n\tu8\t\t\tpkt_type:3,\n\t\t\t\tfclone:2,\n\t\t\t\tipvs_property:1,\n\t\t\t\tpeeked:1,\n\t\t\t\tnf_trace:1;\n\tkmemcheck_bitfield_end(flags1);\n\tu16\t\t\tprotocol;\n\n\tvoid\t\t\t(*destructor)(struct sk_buff *skb);\n#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE)\n\tstruct nf_conntrack\t*nfct;\n\tstruct sk_buff\t\t*nfct_reasm;\n#endif\n#ifdef CONFIG_BRIDGE_NETFILTER\n\tstruct nf_bridge_info\t*nf_bridge;\n#endif\n\n\tint\t\t\tskb_iif;\n#ifdef CONFIG_NET_SCHED\n\tu16\t\t\ttc_index;\t/* traffic control index */\n#ifdef CONFIG_NET_CLS_ACT\n\tu16\t\t\ttc_verd;\t/* traffic control verdict */\n#endif\n#endif\n\n\tu32\t\t\trxhash;\n\n\tkmemcheck_bitfield_begin(flags2);\n\tu16\t\t\tqueue_mapping:16;\n#ifdef CONFIG_IPV6_NDISC_NODETYPE\n\tu8\t\t\tndisc_nodetype:2,\n\t\t\t\tdeliver_no_wcard:1;\n#else\n\tu8\t\t\tdeliver_no_wcard:1;\n#endif\n\tkmemcheck_bitfield_end(flags2);\n\n\t/* 0/14 bit hole */\n\n#ifdef CONFIG_NET_DMA\n\tdma_cookie_t\t\tdma_cookie;\n#endif\n#ifdef CONFIG_NETWORK_SECMARK\n\tu32\t\t\tsecmark;\n#endif\n\tunion {\n\t\tu32\t\tmark;\n\t\tu32\t\tdropcount;\n\t}symbol3;\n\n\tu16\t\t\tvlan_tci;\n\n\tsk_buff_data_t\t\ttransport_header;\n\tsk_buff_data_t\t\tnetwork_header;\n\tsk_buff_data_t\t\tmac_header;\n\t/* These elements must be at the end, see alloc_skb() for details.  */\n\tsk_buff_data_t\t\ttail;\n\tsk_buff_data_t\t\tend;\n\tunsigned char\t\t*head,\n\t\t\t\t*data;\n\tunsigned int\t\ttruesize;\n\tatomic_t\t\tusers;\n};\nstruct sk_buff_head {\n\t/* These two members must be first. */\n\tstruct sk_buff\t*next;\n\tstruct sk_buff\t*prev;\n\n\tu32\t\tqlen;\n\t_lock\tlock;\n};\n#define skb_tail_pointer(skb)\tskb->tail\nstatic inline unsigned char *skb_put(struct sk_buff *skb, unsigned int len)\n{\n\tunsigned char *tmp = skb_tail_pointer(skb);\n\t//SKB_LINEAR_ASSERT(skb);\n\tskb->tail += len;\n\tskb->len  += len;\n\treturn tmp;\n}\n\nstatic inline unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len)\n{\n\tskb->len -= len;\n\tif(skb->len < skb->data_len)\n\t\tprintf(\"%s(),%d,error!\\n\",__FUNCTION__,__LINE__);\n\treturn skb->data += len;\n}\nstatic inline unsigned char *skb_pull(struct sk_buff *skb, unsigned int len)\n{\n\t#ifdef PLATFORM_FREEBSD\n\treturn __skb_pull(skb, len);\n\t#else\n\treturn unlikely(len > skb->len) ? NULL : __skb_pull(skb, len);\n\t#endif //PLATFORM_FREEBSD\n}\nstatic inline u32 skb_queue_len(const struct sk_buff_head *list_)\n{\n\treturn list_->qlen;\n}\nstatic inline void __skb_insert(struct sk_buff *newsk,\n\t\t\t\tstruct sk_buff *prev, struct sk_buff *next,\n\t\t\t\tstruct sk_buff_head *list)\n{\n\tnewsk->next = next;\n\tnewsk->prev = prev;\n\tnext->prev  = prev->next = newsk;\n\tlist->qlen++;\n}\nstatic inline void __skb_queue_before(struct sk_buff_head *list,\n\t\t\t\t      struct sk_buff *next,\n\t\t\t\t      struct sk_buff *newsk)\n{\n\t__skb_insert(newsk, next->prev, next, list);\n}\nstatic inline void skb_queue_tail(struct sk_buff_head *list,\n\t\t\t\t   struct sk_buff *newsk)\n{\n\tmtx_lock(&list->lock);\n\t__skb_queue_before(list, (struct sk_buff *)list, newsk);\n\tmtx_unlock(&list->lock);\n}\nstatic inline struct sk_buff *skb_peek(struct sk_buff_head *list_)\n{\n\tstruct sk_buff *list = ((struct sk_buff *)list_)->next;\n\tif (list == (struct sk_buff *)list_)\n\t\tlist = NULL;\n\treturn list;\n}\nstatic inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list)\n{\n\tstruct sk_buff *next, *prev;\n\n\tlist->qlen--;\n\tnext\t   = skb->next;\n\tprev\t   = skb->prev;\n\tskb->next  = skb->prev = NULL;\n\tnext->prev = prev;\n\tprev->next = next;\n}\n\nstatic inline struct sk_buff *skb_dequeue(struct sk_buff_head *list)\n{\n\tmtx_lock(&list->lock);\n\n\tstruct sk_buff *skb = skb_peek(list);\n\tif (skb)\n\t\t__skb_unlink(skb, list);\n\n\tmtx_unlock(&list->lock);\n\n\treturn skb;\n}\nstatic inline void skb_reserve(struct sk_buff *skb, int len)\n{\n\tskb->data += len;\n\tskb->tail += len;\n}\nstatic inline void __skb_queue_head_init(struct sk_buff_head *list)\n{\n\tlist->prev = list->next = (struct sk_buff *)list;\n\tlist->qlen = 0;\n}\n/*\n * This function creates a split out lock class for each invocation;\n * this is needed for now since a whole lot of users of the skb-queue\n * infrastructure in drivers have different locking usage (in hardirq)\n * than the networking core (in softirq only). In the long run either the\n * network layer or drivers should need annotation to consolidate the\n * main types of usage into 3 classes.\n */\nstatic inline void skb_queue_head_init(struct sk_buff_head *list)\n{\n\t_rtw_spinlock_init(&list->lock);\n\t__skb_queue_head_init(list);\n}\nunsigned long copy_from_user(void *to, const void *from, unsigned long n);\nunsigned long copy_to_user(void *to, const void *from, unsigned long n);\nstruct sk_buff * dev_alloc_skb(unsigned int size);\nstruct sk_buff *skb_clone(const struct sk_buff *skb);\nvoid dev_kfree_skb_any(struct sk_buff *skb);\n#endif //Baron porting from linux, it's all temp solution, needs to check again\n\n\n#if 1 // kenny add Linux compatibility code for Linux USB driver\n#include <dev/usb/usb_compat_linux.h>\n\n#define __init\t\t// __attribute ((constructor))\n#define __exit\t\t// __attribute ((destructor))\n\n/*\n * Definitions for module_init and module_exit macros.\n *\n * These macros will use the SYSINIT framework to call a specified\n * function (with no arguments) on module loading or unloading.\n * \n */\n\nvoid module_init_exit_wrapper(void *arg);\n\n#define module_init(initfn)                             \\\n        SYSINIT(mod_init_ ## initfn,                    \\\n                SI_SUB_KLD, SI_ORDER_FIRST,             \\\n                module_init_exit_wrapper, initfn)\n\n#define module_exit(exitfn)                             \\\n        SYSUNINIT(mod_exit_ ## exitfn,                  \\\n                  SI_SUB_KLD, SI_ORDER_ANY,             \\\n                  module_init_exit_wrapper, exitfn)\n\n/*\n * The usb_register and usb_deregister functions are used to register\n * usb drivers with the usb subsystem. \n */\nint usb_register(struct usb_driver *driver);\nint usb_deregister(struct usb_driver *driver);\n\n/*\n * usb_get_dev and usb_put_dev - increment/decrement the reference count \n * of the usb device structure.\n *\n * Original body of usb_get_dev:\n *\n *       if (dev)\n *               get_device(&dev->dev);\n *       return dev;\n *\n * Reference counts are not currently used in this compatibility\n * layer. So these functions will do nothing.\n */\nstatic inline struct usb_device *\nusb_get_dev(struct usb_device *dev)\n{\n        return dev;\n}\n\nstatic inline void \nusb_put_dev(struct usb_device *dev)\n{\n        return;\n}\n\n\n// rtw_usb_compat_linux\nint rtw_usb_submit_urb(struct urb *urb, uint16_t mem_flags);\nint rtw_usb_unlink_urb(struct urb *urb);\nint rtw_usb_clear_halt(struct usb_device *dev, struct usb_host_endpoint *uhe);\nint rtw_usb_control_msg(struct usb_device *dev, struct usb_host_endpoint *uhe,\n    uint8_t request, uint8_t requesttype,\n    uint16_t value, uint16_t index, void *data,\n    uint16_t size, usb_timeout_t timeout);\nint rtw_usb_set_interface(struct usb_device *dev, uint8_t iface_no, uint8_t alt_index);\nint rtw_usb_setup_endpoint(struct usb_device *dev,\n    struct usb_host_endpoint *uhe, usb_size_t bufsize);\nstruct urb *rtw_usb_alloc_urb(uint16_t iso_packets, uint16_t mem_flags);\nstruct usb_host_endpoint *rtw_usb_find_host_endpoint(struct usb_device *dev, uint8_t type, uint8_t ep);\nstruct usb_host_interface *rtw_usb_altnum_to_altsetting(const struct usb_interface *intf, uint8_t alt_index);\nstruct usb_interface *rtw_usb_ifnum_to_if(struct usb_device *dev, uint8_t iface_no);\nvoid *rtw_usbd_get_intfdata(struct usb_interface *intf);\nvoid rtw_usb_linux_register(void *arg);\nvoid rtw_usb_linux_deregister(void *arg);\nvoid rtw_usb_linux_free_device(struct usb_device *dev);\nvoid rtw_usb_free_urb(struct urb *urb);\nvoid rtw_usb_init_urb(struct urb *urb);\nvoid rtw_usb_kill_urb(struct urb *urb);\nvoid rtw_usb_set_intfdata(struct usb_interface *intf, void *data);\nvoid rtw_usb_fill_bulk_urb(struct urb *urb, struct usb_device *udev,\n    struct usb_host_endpoint *uhe, void *buf,\n    int length, usb_complete_t callback, void *arg);\nint rtw_usb_bulk_msg(struct usb_device *udev, struct usb_host_endpoint *uhe,\n    void *data, int len, uint16_t *pactlen, usb_timeout_t timeout);\nvoid *usb_get_intfdata(struct usb_interface *intf);\nint usb_linux_init_endpoints(struct usb_device *udev);\n\n\n\ntypedef struct urb *  PURB;\n\ntypedef unsigned gfp_t;\n#define __GFP_WAIT      ((gfp_t)0x10u)  /* Can wait and reschedule? */\n#define __GFP_HIGH      ((gfp_t)0x20u)  /* Should access emergency pools? */\n#define __GFP_IO        ((gfp_t)0x40u)  /* Can start physical IO? */\n#define __GFP_FS        ((gfp_t)0x80u)  /* Can call down to low-level FS? */\n#define __GFP_COLD      ((gfp_t)0x100u) /* Cache-cold page required */\n#define __GFP_NOWARN    ((gfp_t)0x200u) /* Suppress page allocation failure warning */\n#define __GFP_REPEAT    ((gfp_t)0x400u) /* Retry the allocation.  Might fail */\n#define __GFP_NOFAIL    ((gfp_t)0x800u) /* Retry for ever.  Cannot fail */\n#define __GFP_NORETRY   ((gfp_t)0x1000u)/* Do not retry.  Might fail */\n#define __GFP_NO_GROW   ((gfp_t)0x2000u)/* Slab internal usage */\n#define __GFP_COMP      ((gfp_t)0x4000u)/* Add compound page metadata */\n#define __GFP_ZERO      ((gfp_t)0x8000u)/* Return zeroed page on success */\n#define __GFP_NOMEMALLOC ((gfp_t)0x10000u) /* Don't use emergency reserves */\n#define __GFP_HARDWALL   ((gfp_t)0x20000u) /* Enforce hardwall cpuset memory allocs */\n\n/* This equals 0, but use constants in case they ever change */\n#define GFP_NOWAIT      (GFP_ATOMIC & ~__GFP_HIGH)\n/* GFP_ATOMIC means both !wait (__GFP_WAIT not set) and use emergency pool */\n#define GFP_ATOMIC      (__GFP_HIGH)\n#define GFP_NOIO        (__GFP_WAIT)\n#define GFP_NOFS        (__GFP_WAIT | __GFP_IO)\n#define GFP_KERNEL      (__GFP_WAIT | __GFP_IO | __GFP_FS)\n#define GFP_USER        (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL)\n#define GFP_HIGHUSER    (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL | \\\n                         __GFP_HIGHMEM)\n\n\n#endif // kenny add Linux compatibility code for Linux USB\n\n__inline static _list *get_next(_list\t*list)\n{\n\treturn list->next;\n}\t\n\n__inline static _list\t*get_list_head(_queue\t*queue)\n{\n\treturn (&(queue->queue));\n}\n\n\t\n#define LIST_CONTAINOR(ptr, type, member) \\\n        ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))\t\n\n        \n__inline static void _enter_critical(_lock *plock, _irqL *pirqL)\n{\n\tspin_lock_irqsave(plock, *pirqL);\n}\n\n__inline static void _exit_critical(_lock *plock, _irqL *pirqL)\n{\n\tspin_unlock_irqrestore(plock, *pirqL);\n}\n\n__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL)\n{\n\tspin_lock_irqsave(plock, *pirqL);\n}\n\n__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL)\n{\n\tspin_unlock_irqrestore(plock, *pirqL);\n}\n\n__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)\n{\n\tspin_lock_bh(plock, *pirqL);\n}\n\n__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)\n{\n\tspin_unlock_bh(plock, *pirqL);\n}\n\n__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)\n{\n\n\t\tmtx_lock(pmutex);\n\n}\n\n\n__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)\n{\n\n\t\tmtx_unlock(pmutex);\n\n}\nstatic inline void __list_del(struct list_head * prev, struct list_head * next)\n{\n\tnext->prev = prev;\n\tprev->next = next;\n}\nstatic inline void INIT_LIST_HEAD(struct list_head *list)\n{\n\tlist->next = list;\n\tlist->prev = list;\n}\n__inline static void rtw_list_delete(_list *plist)\n{\n\t__list_del(plist->prev, plist->next);\n\tINIT_LIST_HEAD(plist);\n}\n\nstatic inline void timer_hdl(void *ctx)\n{\n\t_timer *timer = (_timer *)ctx;\n\n\trtw_mtx_lock(NULL);\n\tif (callout_pending(&timer->callout)) {\n\t\t/* callout was reset */\n\t\trtw_mtx_unlock(NULL);\n\t\treturn;\n\t}\n\n\tif (!callout_active(&timer->callout)) {\n\t\t/* callout was stopped */\n\t\trtw_mtx_unlock(NULL);\n\t\treturn;\n\t}\n\n\tcallout_deactivate(&timer->callout);\n\n\ttimer->function(timer->arg);\n\n\trtw_mtx_unlock(NULL);\n}\n\nstatic inline void _init_timer(_timer *ptimer, _nic_hdl padapter, void *pfunc, void *cntx)\n{\n\tptimer->function = pfunc;\n\tptimer->arg = cntx;\n\tcallout_init(&ptimer->callout, CALLOUT_MPSAFE);\n}\n\n__inline static void _set_timer(_timer *ptimer,u32 delay_time)\n{\t\n\tif (ptimer->function && ptimer->arg) {\n\t\trtw_mtx_lock(NULL);\n\t\tcallout_reset(&ptimer->callout, delay_time, timer_hdl, ptimer);\n\t\trtw_mtx_unlock(NULL);\n\t}\n}\n\n__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)\n{\n\trtw_mtx_lock(NULL);\n\tcallout_drain(&ptimer->callout);\n\trtw_mtx_unlock(NULL);\n\t*bcancelled = 1; /* assume an pending timer to be canceled */\n}\n\n__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)\n{\n\tprintf(\"%s Not implement yet! \\n\",__FUNCTION__);\n}\n\n__inline static void _set_workitem(_workitem *pwork)\n{\n\tprintf(\"%s Not implement yet! \\n\",__FUNCTION__);\n//\tschedule_work(pwork);\n}\n\n//\n// Global Mutex: can only be used at PASSIVE level.\n//\n\n#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter)                              \\\n{                                                               \\\n}\n\n#define RELEASE_GLOBAL_MUTEX(_MutexCounter)                              \\\n{                                                               \\\n}\n\n#define ATOMIC_INIT(i)  { (i) }\n\nstatic __inline void thread_enter(char *name);\n\n//Atomic integer operations\ntypedef uint32_t ATOMIC_T ;\n\n#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc)\n\n#define rtw_free_netdev(netdev) if_free((netdev))\n\n#define NDEV_FMT \"%s\"\n#define NDEV_ARG(ndev) \"\"\n#define ADPT_FMT \"%s\"\n#define ADPT_ARG(adapter) \"\"\n#define FUNC_NDEV_FMT \"%s\"\n#define FUNC_NDEV_ARG(ndev) __func__\n#define FUNC_ADPT_FMT \"%s\"\n#define FUNC_ADPT_ARG(adapter) __func__\n\n#define STRUCT_PACKED\n\n#endif\n\n"
  },
  {
    "path": "include/osdep_service_ce.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef __OSDEP_CE_SERVICE_H_\n#define __OSDEP_CE_SERVICE_H_\n\n\n#include <ndis.h>\n#include <ntddndis.h>\n\n#ifdef CONFIG_SDIO_HCI\n#include \"SDCardDDK.h\"\n#endif\n\n#ifdef CONFIG_USB_HCI\n#include <usbdi.h>\n#endif\n\ntypedef HANDLE \t_sema;\ntypedef\tLIST_ENTRY\t_list;\ntypedef NDIS_STATUS _OS_STATUS;\n\ntypedef NDIS_SPIN_LOCK\t_lock;\n\ntypedef HANDLE \t\t_rwlock; //Mutex\n\ntypedef u32\t_irqL;\n\ntypedef NDIS_HANDLE  _nic_hdl;\n\nstruct rtw_timer_list {\n\tNDIS_MINIPORT_TIMER ndis_timer;\n\tvoid (*function)(void *);\n\tvoid *arg;\n};\n\nstruct\t__queue\t{\n\tLIST_ENTRY\tqueue;\n\t_lock\tlock;\n};\n\ntypedef\tNDIS_PACKET\t_pkt;\ntypedef NDIS_BUFFER\t_buffer;\ntypedef struct\t__queue\t_queue;\n\ntypedef HANDLE \t_thread_hdl_;\ntypedef DWORD thread_return;\ntypedef void*\tthread_context;\ntypedef NDIS_WORK_ITEM _workitem;\n\n\n\n#define SEMA_UPBND\t(0x7FFFFFFF)   //8192\n\n__inline static _list *get_prev(_list\t*list)\n{\n\treturn list->Blink;\n}\n\t\n__inline static _list *get_next(_list\t*list)\n{\n\treturn list->Flink;\n}\n\n__inline static _list\t*get_list_head(_queue\t*queue)\n{\n\treturn (&(queue->queue));\n}\n\n#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)\n\n__inline static void _enter_critical(_lock *plock, _irqL *pirqL)\n{\n\tNdisAcquireSpinLock(plock);\n}\n\n__inline static void _exit_critical(_lock *plock, _irqL *pirqL)\n{\n\tNdisReleaseSpinLock(plock);\n}\n\n__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)\n{\n\tNdisDprAcquireSpinLock(plock);\t\n}\n\n__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)\n{\n\tNdisDprReleaseSpinLock(plock);\t\n}\n\n\n__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL)\n{\n\tWaitForSingleObject(*prwlock, INFINITE );\n\n}\n\n__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL)\n{\n\tReleaseMutex(*prwlock);\n}\n\n__inline static void rtw_list_delete(_list *plist)\n{\n\tRemoveEntryList(plist);\n\tInitializeListHead(plist);\n}\n\nstatic inline void timer_hdl(\n\tIN PVOID SystemSpecific1,\n\tIN PVOID FunctionContext,\n\tIN PVOID SystemSpecific2,\n\tIN PVOID SystemSpecific3)\n{\n\t_timer *timer = (_timer *)FunctionContext;\n\n\ttimer->function(timer->arg);\n}\n\nstatic inline void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx)\n{\n\tptimer->function = pfunc;\n\tptimer->arg = cntx;\n\tNdisMInitializeTimer(&ptimer->ndis_timer, nic_hdl, timer_hdl, ptimer);\n}\n\nstatic inline void _set_timer(_timer *ptimer, u32 delay_time)\n{\n\tNdisMSetTimer(ptimer, delay_time);\n}\n\nstatic inline void _cancel_timer(_timer *ptimer, u8 *bcancelled)\n{\n\tNdisMCancelTimer(ptimer, bcancelled);\n}\n\n__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)\n{\n\n\tNdisInitializeWorkItem(pwork, pfunc, cntx);\n}\n\n__inline static void _set_workitem(_workitem *pwork)\n{\n\tNdisScheduleWorkItem(pwork);\n}\n\n#define ATOMIC_INIT(i)  { (i) }\n\n//\n// Global Mutex: can only be used at PASSIVE level.\n//\n\n#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter)                              \\\n{                                                               \\\n    while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\\\n    {                                                           \\\n        NdisInterlockedDecrement((PULONG)&(_MutexCounter));        \\\n        NdisMSleep(10000);                          \\\n    }                                                           \\\n}\n\n#define RELEASE_GLOBAL_MUTEX(_MutexCounter)                              \\\n{                                                               \\\n    NdisInterlockedDecrement((PULONG)&(_MutexCounter));              \\\n}\n\n// limitation of path length\n#define PATH_LENGTH_MAX MAX_PATH\n\n//Atomic integer operations\n#define ATOMIC_T LONG\n\n#define NDEV_FMT \"%s\"\n#define NDEV_ARG(ndev) \"\"\n#define ADPT_FMT \"%s\"\n#define ADPT_ARG(adapter) \"\"\n#define FUNC_NDEV_FMT \"%s\"\n#define FUNC_NDEV_ARG(ndev) __func__\n#define FUNC_ADPT_FMT \"%s\"\n#define FUNC_ADPT_ARG(adapter) __func__\n\n#define STRUCT_PACKED\n\n\n#endif\n\n"
  },
  {
    "path": "include/osdep_service_linux.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __OSDEP_LINUX_SERVICE_H_\n#define __OSDEP_LINUX_SERVICE_H_\n\n#include <linux/version.h>\n#include <linux/spinlock.h>\n#include <linux/compiler.h>\n#include <linux/kernel.h>\n#include <linux/errno.h>\n#include <linux/init.h>\n#include <linux/slab.h>\n#include <linux/module.h>\n#include <linux/namei.h>\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 5))\n\t#include <linux/kref.h>\n#endif\n/* #include <linux/smp_lock.h> */\n#include <linux/netdevice.h>\n#include <linux/inetdevice.h>\n#include <linux/skbuff.h>\n#include <linux/circ_buf.h>\n#include <asm/uaccess.h>\n#include <asm/byteorder.h>\n#include <asm/atomic.h>\n#include <asm/io.h>\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))\n\t#include <asm/semaphore.h>\n#else\n\t#include <linux/semaphore.h>\n#endif\n#include <linux/sem.h>\n#include <linux/sched.h>\n#include <linux/etherdevice.h>\n#include <linux/wireless.h>\n#include <net/iw_handler.h>\n#include <net/addrconf.h>\n#include <linux/if_arp.h>\n#include <linux/rtnetlink.h>\n#include <linux/delay.h>\n#include <linux/interrupt.h>\t/* for struct tasklet_struct */\n#include <linux/ip.h>\n#include <linux/kthread.h>\n#include <linux/list.h>\n#include <linux/vmalloc.h>\n\n#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 5, 41))\n\t#include <linux/tqueue.h>\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))\n\t#include <uapi/linux/limits.h>\n#else\n\t#include <linux/limits.h>\n#endif\n\n#ifdef RTK_DMP_PLATFORM\n\t#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12))\n\t\t#include <linux/pageremap.h>\n\t#endif\n\t#include <asm/io.h>\n#endif\n\n#ifdef CONFIG_NET_RADIO\n\t#define CONFIG_WIRELESS_EXT\n#endif\n\n/* Monitor mode */\n#include <net/ieee80211_radiotap.h>\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))\n\t#include <linux/ieee80211.h>\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25) && \\\n\t LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29))\n\t#define CONFIG_IEEE80211_HT_ADDT_INFO\n#endif\n\n#ifdef CONFIG_IOCTL_CFG80211\n\t/*\t#include <linux/ieee80211.h> */\n\t#include <net/cfg80211.h>\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n\n#ifdef CONFIG_HAS_EARLYSUSPEND\n\t#include <linux/earlysuspend.h>\n#endif /* CONFIG_HAS_EARLYSUSPEND */\n\n#ifdef CONFIG_EFUSE_CONFIG_FILE\n\t#include <linux/fs.h>\n#endif\n\n#ifdef CONFIG_USB_HCI\n\t#include <linux/usb.h>\n\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 21))\n\t\t#include <linux/usb_ch9.h>\n\t#else\n\t\t#include <linux/usb/ch9.h>\n\t#endif\n#endif\n\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\t#include <net/sock.h>\n\t#include <net/tcp.h>\n\t#include <linux/udp.h>\n\t#include <linux/in.h>\n\t#include <linux/netlink.h>\n#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */\n\n#ifdef CONFIG_USB_HCI\n\ttypedef struct urb   *PURB;\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22))\n\t\t#ifdef CONFIG_USB_SUSPEND\n\t\t\t#define CONFIG_AUTOSUSPEND\t1\n\t\t#endif\n\t#endif\n#endif\n\n#if defined(CONFIG_RTW_GRO) && (!defined(CONFIG_RTW_NAPI))\n\n\t#error \"Enable NAPI before enable GRO\\n\"\n\n#endif\n\n\n#if (KERNEL_VERSION(2, 6, 29) > LINUX_VERSION_CODE && defined(CONFIG_RTW_NAPI))\n\n\t#undef CONFIG_RTW_NAPI\n\t/*#warning \"Linux Kernel version too old to support NAPI (should newer than 2.6.29)\\n\"*/\n\n#endif\n\n#if (KERNEL_VERSION(2, 6, 33) > LINUX_VERSION_CODE && defined(CONFIG_RTW_GRO))\n\n\t#undef CONFIG_RTW_GRO\n\t/*#warning \"Linux Kernel version too old to support GRO(should newer than 2.6.33)\\n\"*/\n\n#endif\n\ntypedef struct\tsemaphore _sema;\ntypedef\tspinlock_t\t_lock;\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))\n\ttypedef struct mutex\t\t_mutex;\n#else\n\ttypedef struct semaphore\t_mutex;\n#endif\nstruct rtw_timer_list {\n\tstruct timer_list timer;\n\tvoid (*function)(void *);\n\tvoid *arg;\n};\n\ntypedef struct rtw_timer_list _timer;\ntypedef struct completion _completion;\n\nstruct\t__queue\t{\n\tstruct\tlist_head\tqueue;\n\t_lock\tlock;\n};\n\ntypedef\tstruct sk_buff\t_pkt;\ntypedef unsigned char\t_buffer;\n\ntypedef struct\t__queue\t_queue;\ntypedef struct\tlist_head\t_list;\n\n/* hlist */\ntypedef struct\thlist_head\trtw_hlist_head;\ntypedef struct\thlist_node\trtw_hlist_node;\n\n/* RCU */\ntypedef struct rcu_head rtw_rcu_head;\n#define rtw_rcu_dereference(p) rcu_dereference((p))\n#define rtw_rcu_dereference_protected(p, c) rcu_dereference_protected(p, c)\n#define rtw_rcu_assign_pointer(p, v) rcu_assign_pointer((p), (v))\n#define rtw_rcu_read_lock() rcu_read_lock()\n#define rtw_rcu_read_unlock() rcu_read_unlock()\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34))\n#define rtw_rcu_access_pointer(p) rcu_access_pointer(p)\n#endif\n\n/* rhashtable */\n#include \"../os_dep/linux/rtw_rhashtable.h\"\n\ntypedef\tint\t_OS_STATUS;\n/* typedef u32\t_irqL; */\ntypedef unsigned long _irqL;\ntypedef\tstruct\tnet_device *_nic_hdl;\n\ntypedef void\t\t*_thread_hdl_;\ntypedef int\t\tthread_return;\ntypedef void\t*thread_context;\n\ntypedef void timer_hdl_return;\ntypedef void *timer_hdl_context;\n\n#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))\n\ttypedef struct work_struct _workitem;\n#else\n\ttypedef struct tq_struct _workitem;\n#endif\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))\n\t#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))\n#endif\n\ntypedef unsigned long systime;\ntypedef struct tasklet_struct _tasklet;\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22))\n/* Porting from linux kernel, for compatible with old kernel. */\nstatic inline unsigned char *skb_tail_pointer(const struct sk_buff *skb)\n{\n\treturn skb->tail;\n}\n\nstatic inline void skb_reset_tail_pointer(struct sk_buff *skb)\n{\n\tskb->tail = skb->data;\n}\n\nstatic inline void skb_set_tail_pointer(struct sk_buff *skb, const int offset)\n{\n\tskb->tail = skb->data + offset;\n}\n\nstatic inline unsigned char *skb_end_pointer(const struct sk_buff *skb)\n{\n\treturn skb->end;\n}\n#endif\n\n__inline static void rtw_list_delete(_list *plist)\n{\n\tlist_del_init(plist);\n}\n\n__inline static _list *get_next(_list\t*list)\n{\n\treturn list->next;\n}\n\n#define LIST_CONTAINOR(ptr, type, member) \\\n\t((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))\n\n#define rtw_list_first_entry(ptr, type, member) list_first_entry(ptr, type, member)\n\n#define rtw_hlist_for_each_entry(pos, head, member) hlist_for_each_entry(pos, head, member)\n#define rtw_hlist_for_each_safe(pos, n, head) hlist_for_each_safe(pos, n, head)\n#define rtw_hlist_entry(ptr, type, member) hlist_entry(ptr, type, member)\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))\n#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, n, head, member)\n#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, head, member)\n#else\n#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, np, n, head, member)\n#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, node, head, member)\n#endif\n\n__inline static void _enter_critical(_lock *plock, _irqL *pirqL)\n{\n\tspin_lock_irqsave(plock, *pirqL);\n}\n\n__inline static void _exit_critical(_lock *plock, _irqL *pirqL)\n{\n\tspin_unlock_irqrestore(plock, *pirqL);\n}\n\n__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL)\n{\n\tspin_lock_irqsave(plock, *pirqL);\n}\n\n__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL)\n{\n\tspin_unlock_irqrestore(plock, *pirqL);\n}\n\n__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)\n{\n\tspin_lock_bh(plock);\n}\n\n__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)\n{\n\tspin_unlock_bh(plock);\n}\n\n__inline static void enter_critical_bh(_lock *plock)\n{\n\tspin_lock_bh(plock);\n}\n\n__inline static void exit_critical_bh(_lock *plock)\n{\n\tspin_unlock_bh(plock);\n}\n\n__inline static int _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)\n{\n\tint ret = 0;\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))\n\t/* mutex_lock(pmutex); */\n\tret = mutex_lock_interruptible(pmutex);\n#else\n\tret = down_interruptible(pmutex);\n#endif\n\treturn ret;\n}\n\n\n__inline static int _enter_critical_mutex_lock(_mutex *pmutex, _irqL *pirqL)\n{\n\tint ret = 0;\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))\n\tmutex_lock(pmutex);\n#else\n\tdown(pmutex);\n#endif\n\treturn ret;\n}\n\n__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))\n\tmutex_unlock(pmutex);\n#else\n\tup(pmutex);\n#endif\n}\n\n__inline static _list\t*get_list_head(_queue\t*queue)\n{\n\treturn &(queue->queue);\n}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))\nstatic inline void timer_hdl(struct timer_list *in_timer)\n#else\nstatic inline void timer_hdl(unsigned long cntx)\n#endif\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 16, 0))\n\t_timer *ptimer = timer_container_of(ptimer, in_timer, timer);\n\t#else\n\t_timer *ptimer = from_timer(ptimer, in_timer, timer);\n\t#endif\n#else\n\t_timer *ptimer = (_timer *)cntx;\n#endif\n\tptimer->function(ptimer->arg);\n}\n\n__inline static void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx)\n{\n\tptimer->function = pfunc;\n\tptimer->arg = cntx;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))\n\ttimer_setup(&ptimer->timer, timer_hdl, 0);\n#else\n\t/* setup_timer(ptimer, pfunc,(u32)cntx);\t */\n\tptimer->timer.function = timer_hdl;\n\tptimer->timer.data = (unsigned long)ptimer;\n\tinit_timer(&ptimer->timer);\n#endif\n}\n\n__inline static void _set_timer(_timer *ptimer, u32 delay_time)\n{\n\tmod_timer(&ptimer->timer , (jiffies + (delay_time * HZ / 1000)));\n}\n\n__inline static void _cancel_timer(_timer *ptimer, u8 *bcancelled)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 15, 0))\n\t*bcancelled = timer_delete_sync(&ptimer->timer) == 1 ? 1 : 0;\n#else\n\t*bcancelled = del_timer_sync(&ptimer->timer) == 1 ? 1 : 0;\n#endif\n}\n\n__inline static void _cancel_timer_async(_timer *ptimer)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 15, 0))\n\ttimer_delete(&ptimer->timer);\n#else\n\tdel_timer(&ptimer->timer);\t\n#endif\n}\n\nstatic inline void _init_workitem(_workitem *pwork, void *pfunc, void *cntx)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20))\n\tINIT_WORK(pwork, pfunc);\n#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))\n\tINIT_WORK(pwork, pfunc, pwork);\n#else\n\tINIT_TQUEUE(pwork, pfunc, pwork);\n#endif\n}\n\n__inline static void _set_workitem(_workitem *pwork)\n{\n#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))\n\tschedule_work(pwork);\n#else\n\tschedule_task(pwork);\n#endif\n}\n\n__inline static void _cancel_workitem_sync(_workitem *pwork)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22))\n\tcancel_work_sync(pwork);\n#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))\n\tflush_scheduled_work();\n#else\n\tflush_scheduled_tasks();\n#endif\n}\n/*\n * Global Mutex: can only be used at PASSIVE level.\n *   */\n\n#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter)                              \\\n\t{                                                               \\\n\t\twhile (atomic_inc_return((atomic_t *)&(_MutexCounter)) != 1) { \\\n\t\t\tatomic_dec((atomic_t *)&(_MutexCounter));        \\\n\t\t\tmsleep(10);                          \\\n\t\t}                                                           \\\n\t}\n\n#define RELEASE_GLOBAL_MUTEX(_MutexCounter)                              \\\n\t{                                                               \\\n\t\tatomic_dec((atomic_t *)&(_MutexCounter));        \\\n\t}\n\nstatic inline int rtw_netif_queue_stopped(struct net_device *pnetdev)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\treturn (netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) &&\n\t\tnetif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 1)) &&\n\t\tnetif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 2)) &&\n\t\tnetif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3)));\n#else\n\treturn netif_queue_stopped(pnetdev);\n#endif\n}\n\nstatic inline void rtw_netif_wake_queue(struct net_device *pnetdev)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\tnetif_tx_wake_all_queues(pnetdev);\n#else\n\tnetif_wake_queue(pnetdev);\n#endif\n}\n\nstatic inline void rtw_netif_start_queue(struct net_device *pnetdev)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\tnetif_tx_start_all_queues(pnetdev);\n#else\n\tnetif_start_queue(pnetdev);\n#endif\n}\n\nstatic inline void rtw_netif_stop_queue(struct net_device *pnetdev)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\tnetif_tx_stop_all_queues(pnetdev);\n#else\n\tnetif_stop_queue(pnetdev);\n#endif\n}\nstatic inline void rtw_netif_device_attach(struct net_device *pnetdev)\n{\n\tnetif_device_attach(pnetdev);\n}\nstatic inline void rtw_netif_device_detach(struct net_device *pnetdev)\n{\n\tnetif_device_detach(pnetdev);\n}\nstatic inline void rtw_netif_carrier_on(struct net_device *pnetdev)\n{\n\tnetif_carrier_on(pnetdev);\n}\nstatic inline void rtw_netif_carrier_off(struct net_device *pnetdev)\n{\n\tnetif_carrier_off(pnetdev);\n}\n\nstatic inline int rtw_merge_string(char *dst, int dst_len, const char *src1, const char *src2)\n{\n\tint\tlen = 0;\n\tlen += snprintf(dst + len, dst_len - len, \"%s\", src1);\n\tlen += snprintf(dst + len, dst_len - len, \"%s\", src2);\n\n\treturn len;\n}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))\n\t#define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)), (sig), 1)\n#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */\n\t#define rtw_signal_process(pid, sig) kill_proc((pid), (sig), 1)\n#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */\n\n\n/* Suspend lock prevent system from going suspend */\n#ifdef CONFIG_WAKELOCK\n\t#include <linux/wakelock.h>\n#elif defined(CONFIG_ANDROID_POWER)\n\t#include <linux/android_power.h>\n#endif\n\n/* limitation of path length */\n#define PATH_LENGTH_MAX PATH_MAX\n\n/* Atomic integer operations */\n#define ATOMIC_T atomic_t\n\n#define rtw_netdev_priv(netdev) (((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv)\n\n#define NDEV_FMT \"%s\"\n#define NDEV_ARG(ndev) ndev->name\n#define ADPT_FMT \"%s\"\n#define ADPT_ARG(adapter) (adapter->pnetdev ? adapter->pnetdev->name : NULL)\n#define FUNC_NDEV_FMT \"%s(%s)\"\n#define FUNC_NDEV_ARG(ndev) __func__, ndev->name\n#define FUNC_ADPT_FMT \"%s(%s)\"\n#define FUNC_ADPT_ARG(adapter) __func__, (adapter->pnetdev ? adapter->pnetdev->name : NULL)\n\nstruct rtw_netdev_priv_indicator {\n\tvoid *priv;\n\tu32 sizeof_priv;\n};\nstruct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv);\nextern struct net_device *rtw_alloc_etherdev(int sizeof_priv);\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))\n#define rtw_get_same_net_ndev_by_name(ndev, name) dev_get_by_name(name)\n#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))\n#define rtw_get_same_net_ndev_by_name(ndev, name) dev_get_by_name(ndev->nd_net, name)\n#else\n#define rtw_get_same_net_ndev_by_name(ndev, name) dev_get_by_name(dev_net(ndev), name)\n#endif\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))\n#define rtw_get_bridge_ndev_by_name(name) dev_get_by_name(name)\n#else\n#define rtw_get_bridge_ndev_by_name(name) dev_get_by_name(&init_net, name)\n#endif\n\n#define STRUCT_PACKED __attribute__ ((packed))\n\n\n#endif /* __OSDEP_LINUX_SERVICE_H_ */\n"
  },
  {
    "path": "include/osdep_service_xp.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __OSDEP_LINUX_SERVICE_H_\n#define __OSDEP_LINUX_SERVICE_H_\n\n\t#include <ndis.h>\n\t#include <ntddk.h>\n\t#include <ntddndis.h>\n\t#include <ntdef.h>\n\n#ifdef CONFIG_USB_HCI\n\t#include <usb.h>\n\t#include <usbioctl.h>\n\t#include <usbdlib.h>\n#endif\n\n\ttypedef KSEMAPHORE \t_sema;\n\ttypedef\tLIST_ENTRY\t_list;\n\ttypedef NDIS_STATUS _OS_STATUS;\n\t\n\n\ttypedef NDIS_SPIN_LOCK\t_lock;\n\n\ttypedef KMUTEX \t\t\t_mutex;\n\n\ttypedef KIRQL\t_irqL;\n\n\t// USB_PIPE for WINCE , but handle can be use just integer under windows\n\ttypedef NDIS_HANDLE  _nic_hdl;\n\n\tstruct rtw_timer_list {\n\t\tNDIS_MINIPORT_TIMER ndis_timer;\n\t\tvoid (*function)(void *);\n\t\tvoid *arg;\n\t};\n\n\tstruct\t__queue\t{\n\t\tLIST_ENTRY\tqueue;\t\n\t\t_lock\tlock;\n\t};\n\n\ttypedef\tNDIS_PACKET\t_pkt;\n\ttypedef NDIS_BUFFER\t_buffer;\n\ttypedef struct\t__queue\t_queue;\n\t\n\ttypedef PKTHREAD _thread_hdl_;\n\ttypedef void\tthread_return;\n\ttypedef void* thread_context;\n\n\ttypedef NDIS_WORK_ITEM _workitem;\n\n\n\t#define HZ\t\t\t10000000\n\t#define SEMA_UPBND\t(0x7FFFFFFF)   //8192\n\t\n__inline static _list *get_next(_list\t*list)\n{\n\treturn list->Flink;\n}\t\n\n__inline static _list\t*get_list_head(_queue\t*queue)\n{\n\treturn (&(queue->queue));\n}\n\t\n\n#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)\n     \n\n__inline static _enter_critical(_lock *plock, _irqL *pirqL)\n{\n\tNdisAcquireSpinLock(plock);\t\n}\n\n__inline static _exit_critical(_lock *plock, _irqL *pirqL)\n{\n\tNdisReleaseSpinLock(plock);\t\n}\n\n\n__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)\n{\n\tNdisDprAcquireSpinLock(plock);\t\n}\n\n__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)\n{\n\tNdisDprReleaseSpinLock(plock);\t\n}\n\n__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)\n{\n\tNdisDprAcquireSpinLock(plock);\n}\n\n__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)\n{\n\tNdisDprReleaseSpinLock(plock);\n}\n\n__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)\n{\n\tKeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL);\n}\n\n\n__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)\n{\n\tKeReleaseMutex(pmutex, FALSE);\n}\n\n\n__inline static void rtw_list_delete(_list *plist)\n{\n\tRemoveEntryList(plist);\n\tInitializeListHead(plist);\t\n}\n\nstatic inline void timer_hdl(\n\tIN PVOID SystemSpecific1,\n\tIN PVOID FunctionContext,\n\tIN PVOID SystemSpecific2,\n\tIN PVOID SystemSpecific3)\n{\n\t_timer *timer = (_timer *)FunctionContext;\n\n\ttimer->function(timer->arg);\n}\n\nstatic inline void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx)\n{\n\tptimer->function = pfunc;\n\tptimer->arg = cntx;\n\tNdisMInitializeTimer(&ptimer->ndis_timer, nic_hdl, timer_hdl, ptimer);\n}\n\nstatic inline void _set_timer(_timer *ptimer, u32 delay_time)\n{\n\tNdisMSetTimer(ptimer, delay_time);\n}\n\nstatic inline void _cancel_timer(_timer *ptimer, u8 *bcancelled)\n{\n\tNdisMCancelTimer(ptimer, bcancelled);\n}\n\n__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)\n{\n\n\tNdisInitializeWorkItem(pwork, pfunc, cntx);\n}\n\n__inline static void _set_workitem(_workitem *pwork)\n{\n\tNdisScheduleWorkItem(pwork);\n}\n\n\n#define ATOMIC_INIT(i)  { (i) }\n\n//\n// Global Mutex: can only be used at PASSIVE level.\n//\n\n#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter)                              \\\n{                                                               \\\n    while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\\\n    {                                                           \\\n        NdisInterlockedDecrement((PULONG)&(_MutexCounter));        \\\n        NdisMSleep(10000);                          \\\n    }                                                           \\\n}\n\n#define RELEASE_GLOBAL_MUTEX(_MutexCounter)                              \\\n{                                                               \\\n    NdisInterlockedDecrement((PULONG)&(_MutexCounter));              \\\n}\n\n// limitation of path length\n#define PATH_LENGTH_MAX MAX_PATH\n\n//Atomic integer operations\n#define ATOMIC_T LONG\n\n\n#define NDEV_FMT \"%s\"\n#define NDEV_ARG(ndev) \"\"\n#define ADPT_FMT \"%s\"\n#define ADPT_ARG(adapter) \"\"\n#define FUNC_NDEV_FMT \"%s\"\n#define FUNC_NDEV_ARG(ndev) __func__\n#define FUNC_ADPT_FMT \"%s\"\n#define FUNC_ADPT_ARG(adapter) __func__\n\n#define STRUCT_PACKED\n\n#endif\n\n"
  },
  {
    "path": "include/pci_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __PCI_HAL_H__\n#define __PCI_HAL_H__\n\n#ifdef CONFIG_RTL8188E\n\tvoid rtl8188ee_set_hal_ops(_adapter *padapter);\n#endif\n\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\n\tvoid rtl8812ae_set_hal_ops(_adapter *padapter);\n#endif\n\n#if defined(CONFIG_RTL8192E)\n\tvoid rtl8192ee_set_hal_ops(_adapter *padapter);\n#endif\n\n#if defined(CONFIG_RTL8192F)\n\tvoid rtl8192fe_set_hal_ops(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_RTL8723B\n\tvoid rtl8723be_set_hal_ops(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_RTL8723D\n\tvoid rtl8723de_set_hal_ops(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_RTL8814A\n\tvoid rtl8814ae_set_hal_ops(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_RTL8822B\n\tvoid rtl8822be_set_hal_ops(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_RTL8822C\n\tvoid rtl8822ce_set_hal_ops(PADAPTER padapter);\n#endif\n\nu8 rtw_set_hal_ops(_adapter *padapter);\n\n#endif /* __PCIE_HAL_H__ */\n"
  },
  {
    "path": "include/pci_ops.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __PCI_OPS_H_\n#define __PCI_OPS_H_\n\n\n#ifdef CONFIG_RTL8188E\n\tu32\trtl8188ee_init_desc_ring(_adapter *padapter);\n\tu32\trtl8188ee_free_desc_ring(_adapter *padapter);\n\tvoid\trtl8188ee_reset_desc_ring(_adapter *padapter);\n\tint\trtl8188ee_interrupt(PADAPTER Adapter);\n\tvoid\trtl8188ee_xmit_tasklet(void *priv);\n\tvoid\trtl8188ee_recv_tasklet(void *priv);\n\tvoid\trtl8188ee_prepare_bcn_tasklet(void *priv);\n\tvoid\trtl8188ee_set_intf_ops(struct _io_ops\t*pops);\n\tvoid\trtw8188ee_unmap_beacon_icf(_adapter *padapter);\n#endif\n\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\n\tu32\trtl8812ae_init_desc_ring(_adapter *padapter);\n\tu32\trtl8812ae_free_desc_ring(_adapter *padapter);\n\tvoid\trtl8812ae_reset_desc_ring(_adapter *padapter);\n\tint\trtl8812ae_interrupt(PADAPTER Adapter);\n\tvoid\trtl8812ae_xmit_tasklet(void *priv);\n\tvoid\trtl8812ae_recv_tasklet(void *priv);\n\tvoid\trtl8812ae_prepare_bcn_tasklet(void *priv);\n\tvoid\trtl8812ae_set_intf_ops(struct _io_ops\t*pops);\n\tvoid\trtw8812ae_unmap_beacon_icf(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_RTL8192E\n\tu32\trtl8192ee_init_desc_ring(_adapter *padapter);\n\tu32\trtl8192ee_free_desc_ring(_adapter *padapter);\n\tvoid\trtl8192ee_reset_desc_ring(_adapter *padapter);\n\tvoid\trtl8192ee_recv_tasklet(void *priv);\n\tvoid\trtl8192ee_prepare_bcn_tasklet(void *priv);\n\tint\trtl8192ee_interrupt(PADAPTER Adapter);\n\tvoid\trtl8192ee_set_intf_ops(struct _io_ops\t*pops);\n\tvoid\trtw8192ee_unmap_beacon_icf(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_RTL8192F\n\tu32\trtl8192fe_init_desc_ring(_adapter *padapter);\n\tu32\trtl8192fe_free_desc_ring(_adapter *padapter);\n\tvoid\trtl8192fe_reset_desc_ring(_adapter *padapter);\n\tint\trtl8192fe_interrupt(PADAPTER Adapter);\n\tvoid\trtl8192fe_recv_tasklet(void *priv);\n\tvoid\trtl8192fe_prepare_bcn_tasklet(void *priv);\n\tvoid\trtl8192fe_set_intf_ops(struct _io_ops\t*pops);\n\tu8 check_tx_desc_resource(_adapter *padapter, int prio);\n\tvoid\trtl8192fe_unmap_beacon_icf(PADAPTER Adapter);\n#endif\n\n#ifdef CONFIG_RTL8723B\n\tu32\trtl8723be_init_desc_ring(_adapter *padapter);\n\tu32\trtl8723be_free_desc_ring(_adapter *padapter);\n\tvoid\trtl8723be_reset_desc_ring(_adapter *padapter);\n\tint\trtl8723be_interrupt(PADAPTER Adapter);\n\tvoid\trtl8723be_recv_tasklet(void *priv);\n\tvoid\trtl8723be_prepare_bcn_tasklet(void *priv);\n\tvoid\trtl8723be_set_intf_ops(struct _io_ops\t*pops);\n\tvoid\trtl8723be_unmap_beacon_icf(PADAPTER Adapter);\n#endif\n\n#ifdef CONFIG_RTL8723D\n\tu32\trtl8723de_init_desc_ring(_adapter *padapter);\n\tu32\trtl8723de_free_desc_ring(_adapter *padapter);\n\tvoid\trtl8723de_reset_desc_ring(_adapter *padapter);\n\tint\trtl8723de_interrupt(PADAPTER Adapter);\n\tvoid\trtl8723de_recv_tasklet(void *priv);\n\tvoid\trtl8723de_prepare_bcn_tasklet(void *priv);\n\tvoid\trtl8723de_set_intf_ops(struct _io_ops\t*pops);\n\tu8 check_tx_desc_resource(_adapter *padapter, int prio);\n\tvoid \trtl8723de_unmap_beacon_icf(PADAPTER Adapter);\n#endif\n\n#ifdef CONFIG_RTL8814A\n\tu32\trtl8814ae_init_desc_ring(_adapter *padapter);\n\tu32\trtl8814ae_free_desc_ring(_adapter *padapter);\n\tvoid\trtl8814ae_reset_desc_ring(_adapter *padapter);\n\tint\trtl8814ae_interrupt(PADAPTER Adapter);\n\tvoid\trtl8814ae_xmit_tasklet(void *priv);\n\tvoid\trtl8814ae_recv_tasklet(void *priv);\n\tvoid\trtl8814ae_prepare_bcn_tasklet(void *priv);\n\tvoid\trtl8814ae_set_intf_ops(struct _io_ops\t*pops);\n\tvoid\trtl8814ae_unmap_beacon_icf(PADAPTER Adapter);\n#endif\n\n#ifdef CONFIG_RTL8822B\n\tvoid rtl8822be_set_intf_ops(struct _io_ops *pops);\n#endif\n\n#ifdef CONFIG_RTL8821C\n\tvoid rtl8821ce_set_intf_ops(struct _io_ops *pops);\n#endif\n\n#ifdef CONFIG_RTL8822C\n\tvoid rtl8822ce_set_intf_ops(struct _io_ops *pops);\n#endif\n\n#endif\n"
  },
  {
    "path": "include/pci_osintf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __PCI_OSINTF_H\n#define __PCI_OSINTF_H\n\n#ifdef RTK_129X_PLATFORM\n#define PCIE_SLOT1_MEM_START\t0x9804F000\n#define PCIE_SLOT1_MEM_LEN\t0x1000\n#define PCIE_SLOT1_CTRL_START\t0x9804EC00\n\n#define PCIE_SLOT2_MEM_START\t0x9803C000\n#define PCIE_SLOT2_MEM_LEN\t0x1000\n#define PCIE_SLOT2_CTRL_START\t0x9803BC00\n\n#define PCIE_MASK_OFFSET\t0x100 /* mask offset from CTRL_START */\n#define PCIE_TRANSLATE_OFFSET\t0x104 /* translate offset from CTRL_START */\n#endif\n\n#define PCI_BC_CLK_REQ\t\tBIT0\n#define PCI_BC_ASPM_L0s\t\tBIT1\n#define PCI_BC_ASPM_L1\t\tBIT2\n#define PCI_BC_ASPM_L1Off\tBIT3\n//#define PCI_BC_ASPM_LTR\tBIT4\n//#define PCI_BC_ASPM_OBFF\tBIT5\n\nvoid\trtw_pci_disable_aspm(_adapter *padapter);\nvoid\trtw_pci_enable_aspm(_adapter *padapter);\nvoid\tPlatformClearPciPMEStatus(PADAPTER Adapter);\nvoid\trtw_pci_aspm_config(_adapter *padapter);\nvoid\trtw_pci_aspm_config_l1off_general(_adapter *padapter, u8 eanble);\n#ifdef CONFIG_PCI_DYNAMIC_ASPM\nvoid\trtw_pci_aspm_config_dynamic_l1_ilde_time(_adapter *padapter);\n#endif\n#ifdef CONFIG_64BIT_DMA\n\tu8\tPlatformEnableDMA64(PADAPTER Adapter);\n#endif\n\n#endif\n"
  },
  {
    "path": "include/recv_osdep.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RECV_OSDEP_H_\n#define __RECV_OSDEP_H_\n\n\nextern sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter);\nextern void _rtw_free_recv_priv(struct recv_priv *precvpriv);\n\n\nextern s32  rtw_recv_entry(union recv_frame *precv_frame);\nvoid rtw_rframe_set_os_pkt(union recv_frame *rframe);\nextern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame);\nextern void rtw_recv_returnpacket(_nic_hdl cnxt, _pkt *preturnedpkt);\n\nextern int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame);\n\n#ifdef CONFIG_HOSTAPD_MLME\nextern void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame);\n#endif\n\nstruct sta_info;\nextern void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup);\n\n\nint rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter);\nint rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe);\nvoid rtw_os_recv_resource_free(struct recv_priv *precvpriv);\n\n\nint rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 *pdata, _pkt *pskb);\nint rtw_os_recvframe_duplicate_skb(_adapter *padapter, union recv_frame *pcloneframe, _pkt *pskb);\nvoid rtw_os_free_recvframe(union recv_frame *precvframe);\n\n\nint rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf);\nint rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf);\n\n_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, const u8 *da, const u8 *sa, u8 *msdu ,u16 msdu_len);\nvoid rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, union recv_frame *rframe);\n\nvoid rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf);\n\n#ifdef PLATFORM_LINUX\n#ifdef CONFIG_RTW_NAPI\n#include <linux/netdevice.h>\t/* struct napi_struct */\n\nint rtw_recv_napi_poll(struct napi_struct *, int budget);\n#ifdef CONFIG_RTW_NAPI_DYNAMIC\nvoid dynamic_napi_th_chk (_adapter *adapter);\n#endif /* CONFIG_RTW_NAPI_DYNAMIC */\n#endif /* CONFIG_RTW_NAPI */\n#endif /* PLATFORM_LINUX */\n\n#endif /*  */\n"
  },
  {
    "path": "include/rtl8188e_cmd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8188E_CMD_H__\n#define __RTL8188E_CMD_H__\n\n#if 0\nenum cmd_msg_element_id {\n\tNONE_CMDMSG_EID,\n\tAP_OFFLOAD_EID = 0,\n\tSET_PWRMODE_EID = 1,\n\tJOINBSS_RPT_EID = 2,\n\tRSVD_PAGE_EID = 3,\n\tRSSI_4_EID = 4,\n\tRSSI_SETTING_EID = 5,\n\tMACID_CONFIG_EID = 6,\n\tMACID_PS_MODE_EID = 7,\n\tP2P_PS_OFFLOAD_EID = 8,\n\tSELECTIVE_SUSPEND_ROF_CMD = 9,\n\tP2P_PS_CTW_CMD_EID = 32,\n\tMAX_CMDMSG_EID\n};\n#else\ntypedef enum _RTL8188E_H2C_CMD_ID {\n\t/* Class Common */\n\tH2C_COM_RSVD_PAGE\t\t\t= 0x00,\n\tH2C_COM_MEDIA_STATUS_RPT\t= 0x01,\n\tH2C_COM_SCAN\t\t\t\t\t= 0x02,\n\tH2C_COM_KEEP_ALIVE\t\t\t= 0x03,\n\tH2C_COM_DISCNT_DECISION\t\t= 0x04,\n#ifndef CONFIG_WOWLAN\n\tH2C_COM_WWLAN\t\t\t\t= 0x05,\n#endif\n\tH2C_COM_INIT_OFFLOAD\t\t\t= 0x06,\n\tH2C_COM_REMOTE_WAKE_CTL\t= 0x07,\n\tH2C_COM_AP_OFFLOAD\t\t\t= 0x08,\n\tH2C_COM_BCN_RSVD_PAGE\t\t= 0x09,\n\tH2C_COM_PROB_RSP_RSVD_PAGE\t= 0x0A,\n\n\t/* Class PS */\n\tH2C_PS_PWR_MODE\t\t\t\t= 0x20,\n\tH2C_PS_TUNE_PARA\t\t\t\t= 0x21,\n\tH2C_PS_TUNE_PARA_2\t\t\t= 0x22,\n\tH2C_PS_LPS_PARA\t\t\t\t= 0x23,\n\tH2C_PS_P2P_OFFLOAD\t\t\t= 0x24,\n\n\t/* Class DM */\n\tH2C_DM_MACID_CFG\t\t\t\t= 0x40,\n\tH2C_DM_TXBF\t\t\t\t\t= 0x41,\n\tH2C_RSSI_REPORT\t\t\t\t= 0x42,\n\t/* Class BT */\n\tH2C_BT_COEX_MASK\t\t\t\t= 0x60,\n\tH2C_BT_COEX_GPIO_MODE\t\t= 0x61,\n\tH2C_BT_DAC_SWING_VAL\t\t\t= 0x62,\n\tH2C_BT_PSD_RST\t\t\t\t= 0x63,\n\n\t/* Class Remote WakeUp */\n#ifdef CONFIG_WOWLAN\n\tH2C_COM_WWLAN\t\t\t\t= 0x80,\n\tH2C_COM_REMOTE_WAKE_CTRL\t= 0x81,\n\tH2C_COM_AOAC_GLOBAL_INFO\t= 0x82,\n\tH2C_COM_AOAC_RSVD_PAGE\t\t= 0x83,\n#endif\n\n\t/* Class */\n\t/* H2C_RESET_TSF\t\t\t\t=0xc0, */\n} RTL8188E_H2C_CMD_ID;\n\n#endif\n\n\nstruct cmd_msg_parm {\n\tu8 eid; /* element id */\n\tu8 sz; /* sz */\n\tu8 buf[6];\n};\n\nenum {\n\tPWRS\n};\n\ntypedef struct _SETPWRMODE_PARM {\n\tu8 Mode;/* 0:Active,1:LPS,2:WMMPS */\n\t/* u8 RLBM:4; */ /* 0:Min,1:Max,2: User define */\n\tu8 SmartPS_RLBM;/* LPS=0:PS_Poll,1:PS_Poll,2:NullData,WMM=0:PS_Poll,1:NullData */\n\tu8 AwakeInterval;\t/* unit: beacon interval */\n\tu8 bAllQueueUAPSD;\n\tu8 PwrState;/* AllON(0x0c),RFON(0x04),RFOFF(0x00) */\n} SETPWRMODE_PARM, *PSETPWRMODE_PARM;\n\nstruct H2C_SS_RFOFF_PARAM {\n\tu8 ROFOn; /* 1: on, 0:off */\n\tu16 gpio_period; /* unit: 1024 us */\n} __attribute__((packed));\n\n\ntypedef struct JOINBSSRPT_PARM_88E {\n\tu8 OpMode;\t/* RT_MEDIA_STATUS */\n#ifdef CONFIG_WOWLAN\n\tu8 MacID;       /* MACID */\n#endif /* CONFIG_WOWLAN */\n} JOINBSSRPT_PARM_88E, *PJOINBSSRPT_PARM_88E;\n\n#if 0\n/* move to hal_com_h2c.h */\ntypedef struct _RSVDPAGE_LOC_88E {\n\tu8 LocProbeRsp;\n\tu8 LocPsPoll;\n\tu8 LocNullData;\n\tu8 LocQosNull;\n\tu8 LocBTQosNull;\n#ifdef CONFIG_WOWLAN\n\tu8 LocRemoteCtrlInfo;\n\tu8 LocArpRsp;\n\tu8 LocNbrAdv;\n\tu8 LocGTKRsp;\n\tu8 LocGTKInfo;\n\tu8 LocProbeReq;\n\tu8 LocNetList;\n#endif /* CONFIG_WOWLAN\t */\n} RSVDPAGE_LOC_88E, *PRSVDPAGE_LOC_88E;\n#endif\n\n/* host message to firmware cmd */\nvoid rtl8188e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);\nvoid rtl8188e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);\ns32 FillH2CCmd_88E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);\n/* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */\nu8 GetTxBufferRsvdPageNum8188E(_adapter *padapter, bool wowlan);\n\n\n#ifdef CONFIG_P2P\n\tvoid rtl8188e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);\n#endif /* CONFIG_P2P */\n\n/* #define H2C_8188E_RSVDPAGE_LOC_LEN      5 */\n/* #define H2C_8188E_AOAC_RSVDPAGE_LOC_LEN 7 */\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------\n * ---------------------------------------------------------------------------------------------------------\n *   */\n#if 0\n\t/* move to hal_com_h2c.h\n\t* _RSVDPAGE_LOC_CMD_0x00 */\n\t#define SET_8188E_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)     SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n\t#define SET_8188E_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)            SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n\t#define SET_8188E_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)     SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n\t#define SET_8188E_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)     SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n\t/*  AOAC_RSVDPAGE_LOC_0x83 */\n\t#define SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value)        SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)\n\t#define SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value)                  SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#endif\n#endif/* __RTL8188E_CMD_H__ */\n"
  },
  {
    "path": "include/rtl8188e_dm.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8188E_DM_H__\n#define __RTL8188E_DM_H__\n\nvoid rtl8188e_init_dm_priv(PADAPTER Adapter);\nvoid rtl8188e_deinit_dm_priv(PADAPTER Adapter);\nvoid rtl8188e_InitHalDm(PADAPTER Adapter);\nvoid rtl8188e_HalDmWatchDog(PADAPTER Adapter);\n\n/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */\n\n/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */\n\n#endif\n"
  },
  {
    "path": "include/rtl8188e_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8188E_HAL_H__\n#define __RTL8188E_HAL_H__\n\n/* #include \"hal_com.h\" */\n#include \"hal_data.h\"\n\n/* include HAL Related header after HAL Related compiling flags */\n#include \"rtl8188e_spec.h\"\n#include \"Hal8188EPhyReg.h\"\n#include \"Hal8188EPhyCfg.h\"\n#include \"rtl8188e_rf.h\"\n#include \"rtl8188e_dm.h\"\n#include \"rtl8188e_recv.h\"\n#include \"rtl8188e_xmit.h\"\n#include \"rtl8188e_cmd.h\"\n#include \"rtl8188e_led.h\"\n#include \"Hal8188EPwrSeq.h\"\n#ifdef DBG_CONFIG_ERROR_DETECT\n\t#include \"rtl8188e_sreset.h\"\n#endif\n\n/* --------------------------------------------------------------------- */\n/*\t\tRTL8188E Power Configuration CMDs for USB/SDIO/PCIE interfaces */\n/* --------------------------------------------------------------------- */\n#define Rtl8188E_NIC_PWR_ON_FLOW\t\t\t\trtl8188E_power_on_flow\n#define Rtl8188E_NIC_RF_OFF_FLOW\t\t\t\trtl8188E_radio_off_flow\n#define Rtl8188E_NIC_DISABLE_FLOW\t\t\t\trtl8188E_card_disable_flow\n#define Rtl8188E_NIC_ENABLE_FLOW\t\t\t\trtl8188E_card_enable_flow\n#define Rtl8188E_NIC_SUSPEND_FLOW\t\t\t\trtl8188E_suspend_flow\n#define Rtl8188E_NIC_RESUME_FLOW\t\t\t\trtl8188E_resume_flow\n#define Rtl8188E_NIC_PDN_FLOW\t\t\t\t\trtl8188E_hwpdn_flow\n#define Rtl8188E_NIC_LPS_ENTER_FLOW\t\t\trtl8188E_enter_lps_flow\n#define Rtl8188E_NIC_LPS_LEAVE_FLOW\t\t\trtl8188E_leave_lps_flow\n\n\n#if 1 /* download firmware related data structure */\n#define MAX_FW_8188E_SIZE\t\t\t0x8000 /* 32768, 32k / 16384, 16k */\n\n#define FW_8188E_SIZE\t\t\t\t0x4000 /* 16384, 16k */\n#define FW_8188E_SIZE_2\t\t\t0x8000 /* 32768, 32k */\n\n#define FW_8188E_START_ADDRESS\t0x1000\n#define FW_8188E_END_ADDRESS\t\t0x1FFF /* 0x5FFF */\n\n\n#define IS_FW_HEADER_EXIST_88E(_pFwHdr)\t((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x88E0)\n\ntypedef struct _RT_FIRMWARE_8188E {\n\tFIRMWARE_SOURCE\teFWSource;\n#ifdef CONFIG_EMBEDDED_FWIMG\n\tu8\t\t\t*szFwBuffer;\n#else\n\tu8\t\t\tszFwBuffer[MAX_FW_8188E_SIZE];\n#endif\n\tu32\t\t\tulFwLength;\n} RT_FIRMWARE_8188E, *PRT_FIRMWARE_8188E;\n\n/*\n * This structure must be cared byte-ordering\n *   */\n\ntypedef struct _RT_8188E_FIRMWARE_HDR {\n\t/* 8-byte alinment required */\n\n\t/* --- LONG WORD 0 ---- */\n\tu16\t\tSignature;\t/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */\n\tu8\t\tCategory;\t/* AP/NIC and USB/PCI */\n\tu8\t\tFunction;\t/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */\n\tu16\t\tVersion;\t\t/* FW Version */\n\tu8\t\tSubversion;\t/* FW Subversion, default 0x00 */\n\tu16\t\tRsvd1;\n\n\n\t/* --- LONG WORD 1 ---- */\n\tu8\t\tMonth;\t/* Release time Month field */\n\tu8\t\tDate;\t/* Release time Date field */\n\tu8\t\tHour;\t/* Release time Hour field */\n\tu8\t\tMinute;\t/* Release time Minute field */\n\tu16\t\tRamCodeSize;\t/* The size of RAM code */\n\tu8\t\tFoundry;\n\tu8\t\tRsvd2;\n\n\t/* --- LONG WORD 2 ---- */\n\tu32\t\tSvnIdx;\t/* The SVN entry index */\n\tu32\t\tRsvd3;\n\n\t/* --- LONG WORD 3 ---- */\n\tu32\t\tRsvd4;\n\tu32\t\tRsvd5;\n} RT_8188E_FIRMWARE_HDR, *PRT_8188E_FIRMWARE_HDR;\n#endif /* download firmware related data structure */\n\n\n#define DRIVER_EARLY_INT_TIME_8188E\t\t\t0x05\n#define BCN_DMA_ATIME_INT_TIME_8188E\t\t0x02\n\n\n/* #define MAX_RX_DMA_BUFFER_SIZE_88E\t      0x2400 */ /* 9k for 88E nornal chip , */ /* MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */\n#ifdef CONFIG_USB_HCI\n\t#define RX_DMA_SIZE_88E(__Adapter) 0x2800\n#else\n\t#define RX_DMA_SIZE_88E(__Adapter) ((!IS_VENDOR_8188E_I_CUT_SERIES(__Adapter))?0x2800:0x4000)\n#endif\n\n#ifdef CONFIG_WOWLAN\n\t#define RESV_FMWF\t(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/\n#else\n\t#define RESV_FMWF\t0\n#endif\n\n#define RX_DMA_RESERVD_FW_FEATURE\t0x200 /* for tx report (64*8) */\n\n#define MAX_RX_DMA_BUFFER_SIZE_88E(__Adapter) (RX_DMA_SIZE_88E(__Adapter)-RX_DMA_RESERVD_FW_FEATURE)\n\n#define MAX_TX_REPORT_BUFFER_SIZE\t\t\t0x0400 /* 1k */\n\n#define PAGE_SIZE_TX_88E PAGE_SIZE_128\n/* Note: We will divide number of page equally for each queue other than public queue!\n * 22k = 22528 bytes = 176 pages (@page =  128 bytes)\n * BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_88E\n * 1 ps-poll / 1 null-data /1 prob_rsp /1 QOS null-data = 4 pages */\n\n#define BCNQ_PAGE_NUM_88E\t\t(MAX_BEACON_LEN / PAGE_SIZE_TX_88E + 4) /*0x09*/\n\n/* For WoWLan , more reserved page */\n#ifdef CONFIG_WOWLAN\n\t/* 1 ArpRsp + 2 NbrAdv + 2 NDPInfo + 1 RCI + 1 AOAC = 7 pages */\n\t#define WOWLAN_PAGE_NUM_88E\t0x07\n#else\n\t#define WOWLAN_PAGE_NUM_88E\t0x00\n#endif\n\n/* Note:\nTx FIFO Size : previous CUT:22K /I_CUT after:32KB\nTx page Size : 128B\nTotal page numbers : 176(0xB0) / 256(0x100)\n*/\n#ifdef CONFIG_USB_HCI\n\t#define TOTAL_PAGE_NUMBER_88E(_Adapter) (0xB0 - 1)\n#else\n\t#define TOTAL_PAGE_NUMBER_88E(_Adapter)\t((IS_VENDOR_8188E_I_CUT_SERIES(_Adapter)?0x100:0xB0) - 1)/* must reserved 1 page for dma issue */\n#endif\n#define TX_TOTAL_PAGE_NUMBER_88E(_Adapter)\t(TOTAL_PAGE_NUMBER_88E(_Adapter) - BCNQ_PAGE_NUM_88E - WOWLAN_PAGE_NUM_88E)\n#define TX_PAGE_BOUNDARY_88E(_Adapter)\t\t(TX_TOTAL_PAGE_NUMBER_88E(_Adapter) + 1) /* beacon header start address */\n\n#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_88E(_Adapter)\tTX_TOTAL_PAGE_NUMBER_88E(_Adapter)\n#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E(_Adapter)\t\t(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_88E(_Adapter) + 1)\n\n/* For Normal Chip Setting\n * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723B */\n#define NORMAL_PAGE_NUM_HPQ_88E\t\t0x0\n#define NORMAL_PAGE_NUM_LPQ_88E\t\t0x09\n#define NORMAL_PAGE_NUM_NPQ_88E\t\t0x0\n\n/* Note: For Normal Chip Setting, modify later */\n#define WMM_NORMAL_PAGE_NUM_HPQ_88E\t\t0x29\n#define WMM_NORMAL_PAGE_NUM_LPQ_88E\t\t0x1C\n#define WMM_NORMAL_PAGE_NUM_NPQ_88E\t\t0x1C\n\n\n/* -------------------------------------------------------------------------\n *\tChip specific\n * ------------------------------------------------------------------------- */\n#define CHIP_BONDING_IDENTIFIER(_value)\t(((_value)>>22) & 0x3)\n#define CHIP_BONDING_92C_1T2R\t0x1\n#define CHIP_BONDING_88C_USB_MCARD\t0x2\n#define CHIP_BONDING_88C_USB_HP\t0x1\n\n/* -------------------------------------------------------------------------\n *\tChannel Plan\n * ------------------------------------------------------------------------- */\n\n\n#define EFUSE_REAL_CONTENT_LEN\t\t512\n#define EFUSE_MAP_LEN\t\t\t\t128\n#define EFUSE_MAX_SECTION\t\t\t16\n#define EFUSE_IC_ID_OFFSET\t\t\t506\t/* For some inferiority IC purpose. added by Roger, 2009.09.02. */\n#define AVAILABLE_EFUSE_ADDR(addr)\t(addr < EFUSE_REAL_CONTENT_LEN)\n/*\n * <Roger_Notes>\n * To prevent out of boundary programming case,\n * leave 1byte and program full section\n * 9bytes + 1byt + 5bytes and pre 1byte.\n * For worst case:\n * | 1byte|----8bytes----|1byte|--5bytes--|\n * |         |            Reserved(14bytes)\t      |\n *   */\n#define EFUSE_OOB_PROTECT_BYTES \t\t15\t/* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */\n\n#define\t\tEFUSE_REAL_CONTENT_LEN_88E\t256\n#define\t\tEFUSE_MAP_LEN_88E\t\t512\n#define\t\tEFUSE_MAX_SECTION_88E\t\t64\n#define\t\tEFUSE_MAX_WORD_UNIT_88E\t\t4\n#define\t\tEFUSE_IC_ID_OFFSET_88E\t\t\t506\t/* For some inferiority IC purpose. added by Roger, 2009.09.02. */\n#define\t\tAVAILABLE_EFUSE_ADDR_88E(addr)\t(addr < EFUSE_REAL_CONTENT_LEN_88E)\n/* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section\n * 9bytes + 1byt + 5bytes and pre 1byte.\n * For worst case:\n * | 2byte|----8bytes----|1byte|--7bytes--|  */ /* 92D */\n#define \t\tEFUSE_OOB_PROTECT_BYTES_88E\t18\t/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */\n#define\t\tEFUSE_PROTECT_BYTES_BANK_88E\t16\n\n\n/* ********************************************************\n *\t\t\tEFUSE for BT definition\n * ******************************************************** */\n#define EFUSE_BT_REAL_CONTENT_LEN\t\t1536\t/* 512*3 */\n#define EFUSE_BT_MAP_LEN\t\t\t\t1024\t/* 1k bytes */\n#define EFUSE_BT_MAX_SECTION\t\t\t128\t\t/* 1024/8 */\n\n#define EFUSE_PROTECT_BYTES_BANK\t\t16\n\n#define INCLUDE_MULTI_FUNC_BT(_Adapter)\t(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)\n#define INCLUDE_MULTI_FUNC_GPS(_Adapter)\t(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)\n\n/* #define IS_MULTI_FUNC_CHIP(_Adapter)\t(((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */\n\n/* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */\n\n#ifdef CONFIG_PCI_HCI\n\t/* according to the define in the rtw_xmit.h, rtw_recv.h */\n\t#define TX_DESC_NUM_8188EE  TXDESC_NUM   /* 128 */\n\t#ifdef CONFIG_CONCURRENT_MODE\n\t\t/*#define BE_QUEUE_TX_DESC_NUM_8188EE  (TXDESC_NUM<<1)*/\t\t/* 256 */\n\t\t#define BE_QUEUE_TX_DESC_NUM_8188EE  ((TXDESC_NUM<<1)+(TXDESC_NUM>>1))    /* 320 */\n\t\t/*#define BE_QUEUE_TX_DESC_NUM_8188EE  ((TXDESC_NUM<<1)+TXDESC_NUM)*/    /* 384 */\n\t#else\n\t\t#define BE_QUEUE_TX_DESC_NUM_8188EE  TXDESC_NUM /* 128 */\n\t\t/*#define BE_QUEUE_TX_DESC_NUM_8188EE  (TXDESC_NUM+(TXDESC_NUM>>1)) */ /* 192 */\n\t#endif\n\n\tvoid InterruptRecognized8188EE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent);\n\tvoid UpdateInterruptMask8188EE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);\n#endif /* CONFIG_PCI_HCI */\n\n/* rtl8188e_hal_init.c */\n\ns32 rtl8188e_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);\nvoid _8051Reset88E(PADAPTER padapter);\nvoid rtl8188e_InitializeFirmwareVars(PADAPTER padapter);\n\n\ns32 InitLLTTable(PADAPTER padapter, u8 txpktbuf_bndy);\n\n/* EFuse */\nu8 GetEEPROMSize8188E(PADAPTER padapter);\nvoid Hal_InitPGData88E(PADAPTER padapter);\nvoid Hal_EfuseParseIDCode88E(PADAPTER padapter, u8 *hwinfo);\nvoid Hal_ReadTxPowerInfo88E(PADAPTER padapter, u8 *hwinfo, BOOLEAN\tAutoLoadFail);\n\nvoid Hal_EfuseParseEEPROMVer88E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid rtl8188e_EfuseParseChnlPlan(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseCustomerID88E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_ReadAntennaDiversity88E(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);\nvoid Hal_ReadThermalMeter_88E(PADAPTER\tAdapter, u8 *PROMContent, BOOLEAN\tAutoloadFail);\nvoid Hal_EfuseParseXtal_8188E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseBoardType88E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_ReadPowerSavingMode88E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_ReadPAType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);\nvoid Hal_ReadAmplifierType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);\nvoid Hal_ReadRFEType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);\n\nBOOLEAN HalDetectPwrDownMode88E(PADAPTER Adapter);\n\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\n\tvoid Hal_DetectWoWMode(PADAPTER pAdapter);\n#endif /* CONFIG_WOWLAN */\n\n\n#ifdef CONFIG_RF_POWER_TRIM\n\tvoid Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\n#endif /*CONFIG_RF_POWER_TRIM*/\n\n\nvoid InitBeaconParameters_8188e(_adapter *adapter);\nvoid SetBeaconRelatedRegisters8188E(PADAPTER padapter);\n\nvoid rtl8188e_set_hal_ops(struct hal_ops *pHalFunc);\nvoid init_hal_spec_8188e(_adapter *adapter);\n\nvoid rtl8188e_start_thread(_adapter *padapter);\nvoid rtl8188e_stop_thread(_adapter *padapter);\n\nvoid rtw_IOL_cmd_tx_pkt_buf_dump(ADAPTER *Adapter, int data_len);\n#ifdef CONFIG_IOL_EFUSE_PATCH\n\ts32 rtl8188e_iol_efuse_patch(PADAPTER padapter);\n#endif/* CONFIG_IOL_EFUSE_PATCH */\nvoid _InitTransferPageSize(PADAPTER padapter);\n\nu8 SetHwReg8188E(PADAPTER padapter, u8 variable, u8 *val);\nvoid GetHwReg8188E(PADAPTER padapter, u8 variable, u8 *val);\n\nu8\nGetHalDefVar8188E(\n\t\tPADAPTER\t\t\t\tAdapter,\n\t\tHAL_DEF_VARIABLE\t\teVariable,\n\t\tvoid\t\t\t\t\t\t*pValue\n);\n#ifdef CONFIG_GPIO_API\nint rtl8188e_GpioFuncCheck(PADAPTER adapter, u8 gpio_num);\n#endif\n#endif /* __RTL8188E_HAL_H__ */\n"
  },
  {
    "path": "include/rtl8188e_led.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8188E_LED_H__\n#define __RTL8188E_LED_H__\n\n#ifdef CONFIG_RTW_SW_LED\n\n/* ********************************************************************************\n * Interface to manipulate LED objects.\n * ******************************************************************************** */\n#ifdef CONFIG_USB_HCI\n\tvoid rtl8188eu_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8188eu_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_PCI_HCI\n\tvoid rtl8188ee_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8188ee_DeInitSwLeds(PADAPTER padapter);\n#endif\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\tvoid rtl8188es_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8188es_DeInitSwLeds(PADAPTER padapter);\n#endif\n\n#endif\n#endif /*CONFIG_RTW_SW_LED*/\n"
  },
  {
    "path": "include/rtl8188e_recv.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8188E_RECV_H__\n#define __RTL8188E_RECV_H__\n\n#define RECV_BLK_SZ 512\n#define RECV_BLK_CNT 16\n#define RECV_BLK_TH RECV_BLK_CNT\n\n#if defined(CONFIG_USB_HCI)\n\t#ifndef MAX_RECVBUF_SZ\n\t\t#ifndef CONFIG_MINIMAL_MEMORY_USAGE\n\t\t\t/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */\n\t\t\t/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */\n\t\t\t/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */\n\t\t\t#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */\n\t\t\t/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */\n\t\t#else\n\t\t\t#define MAX_RECVBUF_SZ (4000) /* about 4K */\n\t\t#endif\n\t#endif /* !MAX_RECVBUF_SZ */\n\n#elif defined(CONFIG_PCI_HCI)\n\t/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */\n\t/*\t#define MAX_RECVBUF_SZ (9100) */\n\t/* #else */\n\t#define MAX_RECVBUF_SZ (4000) /* about 4K\n\t* #endif */\n\n\n#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\n\t#define MAX_RECVBUF_SZ (10240)\n\n#endif\n\n/* Rx smooth factor */\n#define\tRx_Smooth_Factor (20)\n\n#define TX_RPT1_PKT_LEN 8\n\ntypedef struct rxreport_8188e {\n\t/* Offset 0 */\n\tu32 pktlen:14;\n\tu32 crc32:1;\n\tu32 icverr:1;\n\tu32 drvinfosize:4;\n\tu32 security:3;\n\tu32 qos:1;\n\tu32 shift:2;\n\tu32 physt:1;\n\tu32 swdec:1;\n\tu32 ls:1;\n\tu32 fs:1;\n\tu32 eor:1;\n\tu32 own:1;\n\n\t/* Offset 4 */\n\tu32 macid:5;\n\tu32 tid:4;\n\tu32 hwrsvd:4;\n\tu32 amsdu:1;\n\tu32 paggr:1;\n\tu32 faggr:1;\n\tu32 a1fit:4;\n\tu32 a2fit:4;\n\tu32 pam:1;\n\tu32 pwr:1;\n\tu32 md:1;\n\tu32 mf:1;\n\tu32 type:2;\n\tu32 mc:1;\n\tu32 bc:1;\n\n\t/* Offset 8 */\n\tu32 seq:12;\n\tu32 frag:4;\n\tu32 nextpktlen:14;\n\tu32 nextind:1;\n\tu32 rsvd0831:1;\n\n\t/* Offset 12 */\n\tu32 rxmcs:6;\n\tu32 rxht:1;\n\tu32 gf:1;\n\tu32 splcp:1;\n\tu32 bw:1;\n\tu32 htc:1;\n\tu32 eosp:1;\n\tu32 bssidfit:2;\n\tu32 rpt_sel:2;\n\tu32 rsvd1216:13;\n\tu32 pattern_match:1;\n\tu32 unicastwake:1;\n\tu32 magicwake:1;\n\n\t/* Offset 16 */\n\t/*\n\tu32 pattern0match:1;\n\tu32 pattern1match:1;\n\tu32 pattern2match:1;\n\tu32 pattern3match:1;\n\tu32 pattern4match:1;\n\tu32 pattern5match:1;\n\tu32 pattern6match:1;\n\tu32 pattern7match:1;\n\tu32 pattern8match:1;\n\tu32 pattern9match:1;\n\tu32 patternamatch:1;\n\tu32 patternbmatch:1;\n\tu32 patterncmatch:1;\n\tu32 rsvd1613:19;\n\t*/\n\tu32 rsvd16;\n\n\t/* Offset 20 */\n\tu32 tsfl;\n\n\t/* Offset 24 */\n\tu32 bassn:12;\n\tu32 bavld:1;\n\tu32 rsvd2413:19;\n} RXREPORT, *PRXREPORT;\n\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\ts32 rtl8188es_init_recv_priv(PADAPTER padapter);\n\tvoid rtl8188es_free_recv_priv(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_USB_HCI\n\tvoid rtl8188eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);\n\ts32 rtl8188eu_init_recv_priv(PADAPTER padapter);\n\tvoid rtl8188eu_free_recv_priv(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\ts32 rtl8188ee_init_recv_priv(PADAPTER padapter);\n\tvoid rtl8188ee_free_recv_priv(PADAPTER padapter);\n#endif\n\nvoid rtl8188e_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *prxstat);\n\n#endif /* __RTL8188E_RECV_H__ */\n"
  },
  {
    "path": "include/rtl8188e_rf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8188E_RF_H__\n#define __RTL8188E_RF_H__\n\n\n\nint\tPHY_RF6052_Config8188E(PADAPTER\t\tAdapter);\nvoid\t\trtl8188e_RF_ChangeTxPath(PADAPTER\tAdapter,\n\t\t\tu16\t\tDataRate);\nvoid\t\trtl8188e_PHY_RF6052SetBandwidth(\n\t\tPADAPTER\t\t\t\tAdapter,\n\t\tenum channel_width\t\tBandwidth);\n\n#endif/* __RTL8188E_RF_H__ */\n"
  },
  {
    "path": "include/rtl8188e_spec.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8188E_SPEC_H__\n#define __RTL8188E_SPEC_H__\n\n\n/* ************************************************************\n * 8188E Regsiter offset definition\n * ************************************************************ */\n\n\n/* ************************************************************\n *\n * ************************************************************ */\n\n/* -----------------------------------------------------\n *\n *\t0x0000h ~ 0x00FFh\tSystem Configuration\n *\n * ----------------------------------------------------- */\n#define REG_BB_PAD_CTRL\t\t\t\t0x0064\n#define REG_HMEBOX_E0\t\t\t\t\t0x0088\n#define REG_HMEBOX_E1\t\t\t\t\t0x008A\n#define REG_HMEBOX_E2\t\t\t\t\t0x008C\n#define REG_HMEBOX_E3\t\t\t\t\t0x008E\n#define REG_HMEBOX_EXT_0\t\t\t\t0x01F0\n#define REG_HMEBOX_EXT_1\t\t\t\t0x01F4\n#define REG_HMEBOX_EXT_2\t\t\t\t0x01F8\n#define REG_HMEBOX_EXT_3\t\t\t\t0x01FC\n#define REG_HIMR_88E\t\t\t\t\t0x00B0 /* RTL8188E */\n#define REG_HISR_88E\t\t\t\t\t0x00B4 /* RTL8188E */\n#define REG_HIMRE_88E\t\t\t\t\t0x00B8 /* RTL8188E */\n#define REG_HISRE_88E\t\t\t\t\t0x00BC /* RTL8188E */\n\n#define\tREG_DBI_WDATA_8188E\t\t\t\t0x0348\t/* DBI Write data */\n#define\tREG_DBI_RDATA_8188E\t\t\t\t0x034C\t/* DBI Read data */\n#define\tREG_DBI_ADDR_8188E\t\t\t\t0x0350\t/* DBI Address */\n#define\tREG_DBI_FLAG_8188E\t\t\t\t0x0352\t/* DBI Read/Write Flag */\n#define\tREG_MDIO_WDATA_8188E\t\t\t\t0x0354\t/* MDIO for Write PCIE PHY */\n#define\tREG_MDIO_RDATA_8188E\t\t\t\t0x0356\t/* MDIO for Reads PCIE PHY */\n#define\tREG_MDIO_CTL_8188E\t\t\t\t0x0358\t/* MDIO for Control */\n\n#define REG_MACID_NO_LINK_0\t\t\t0x0484\n#define REG_MACID_NO_LINK_1\t\t\t0x0488\n#define REG_MACID_PAUSE_0\t\t\t0x048c\n#define REG_MACID_PAUSE_1\t\t\t0x0490\n\n/* -----------------------------------------------------\n *\n *\t0x0100h ~ 0x01FFh\tMACTOP General Configuration\n *\n * ----------------------------------------------------- */\n#define REG_PKTBUF_DBG_ADDR\t\t\t(REG_PKTBUF_DBG_CTRL)\n#define REG_RXPKTBUF_DBG\t\t\t\t(REG_PKTBUF_DBG_CTRL+2)\n#define REG_TXPKTBUF_DBG\t\t\t\t(REG_PKTBUF_DBG_CTRL+3)\n#define REG_WOWLAN_WAKE_REASON\t\tREG_MCUTST_WOWLAN\n\n/* -----------------------------------------------------\n *\n *\t0x0200h ~ 0x027Fh\tTXDMA Configuration\n *\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n *\n *\t0x0280h ~ 0x02FFh\tRXDMA Configuration\n *\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n *\n *\t0x0300h ~ 0x03FFh\tPCIe\n *\n * ----------------------------------------------------- */\n#define REG_PCIE_HRPWM_8188E\t\t0x0361\t/* PCIe RPWM */\n#define REG_PCIE_HCPWM_8188E\t\t0x0363\t/* PCIe CPWM */\n\n/* -----------------------------------------------------\n *\n *\t0x0400h ~ 0x047Fh\tProtocol Configuration\n *\n * ----------------------------------------------------- */\n#ifdef CONFIG_WOWLAN\n\t#define REG_TXPKTBUF_IV_LOW             0x01a4\n\t#define REG_TXPKTBUF_IV_HIGH            0x01a8\n#endif\n\n/* -----------------------------------------------------\n *\n *\t0x0500h ~ 0x05FFh\tEDCA Configuration\n *\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n *\n *\t0x0600h ~ 0x07FFh\tWMAC Configuration\n *\n * ----------------------------------------------------- */\n#ifdef CONFIG_RF_POWER_TRIM\n\t#define EEPROM_RF_GAIN_OFFSET\t\t\t0xC1\n\t#define EEPROM_RF_GAIN_VAL\t\t\t\t0xF6\n\t#define EEPROM_THERMAL_OFFSET\t\t\t0xF5\n#endif /*CONFIG_RF_POWER_TRIM*/\n/* ----------------------------------------------------------------------------\n * 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits)\n * ----------------------------------------------------------------------------\n * IOL config for REG_FDHM0(Reg0x88) */\n#define CMD_INIT_LLT\t\t\t\t\tBIT0\n#define CMD_READ_EFUSE_MAP\t\tBIT1\n#define CMD_EFUSE_PATCH\t\t\tBIT2\n#define CMD_IOCONFIG\t\t\t\tBIT3\n#define CMD_INIT_LLT_ERR\t\t\tBIT4\n#define CMD_READ_EFUSE_MAP_ERR\tBIT5\n#define CMD_EFUSE_PATCH_ERR\t\tBIT6\n#define CMD_IOCONFIG_ERR\t\t\tBIT7\n\n/* -----------------------------------------------------\n *\n *\tRedifine register definition for compatibility\n *\n * ----------------------------------------------------- */\n\n/* TODO: use these definition when using REG_xxx naming rule.\n * NOTE: DO NOT Remove these definition. Use later. */\n#define ISR_88E\t\t\t\tREG_HISR_88E\n\n#ifdef CONFIG_PCI_HCI\n\t/* #define IMR_RX_MASK\t\t(IMR_ROK_88E|IMR_RDU_88E|IMR_RXFOVW_88E) */\n\t#define IMR_TX_MASK\t\t\t(IMR_VODOK_88E | IMR_VIDOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E | IMR_MGNTDOK_88E | IMR_HIGHDOK_88E | IMR_BCNDERR0_88E)\n\n\t#ifdef CONFIG_CONCURRENT_MODE\n\t\t#define RT_BCN_INT_MASKS\t(IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E | IMR_BCNDMAINT_E_88E)\n\t#else\n\t\t#define RT_BCN_INT_MASKS\t(IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E)\n\t#endif\n\n\t#define RT_AC_INT_MASKS\t(IMR_VIDOK_88E | IMR_VODOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E)\n#endif\n\n/* ----------------------------------------------------------------------------\n * 8192C EEPROM/EFUSE share register definition.\n * ---------------------------------------------------------------------------- */\n\n#define EFUSE_ACCESS_ON\t\t\t0x69\t/* For RTL8723 only. */\n#define EFUSE_ACCESS_OFF\t\t\t0x00\t/* For RTL8723 only. */\n\n#endif /* __RTL8188E_SPEC_H__ */\n"
  },
  {
    "path": "include/rtl8188e_sreset.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8188E_SRESET_H_\n#define _RTL8188E_SRESET_H_\n\n#include <rtw_sreset.h>\n\n#ifdef DBG_CONFIG_ERROR_DETECT\n\textern void rtl8188e_sreset_xmit_status_check(_adapter *padapter);\n\textern void rtl8188e_sreset_linked_status_check(_adapter *padapter);\n#endif\n#endif\n"
  },
  {
    "path": "include/rtl8188e_xmit.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8188E_XMIT_H__\n#define __RTL8188E_XMIT_H__\n\n\n\n\n/* For 88e early mode */\n#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)\n#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)\n#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)\n#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)\n#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)\n#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)\n#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)\n\n/*\n * defined for TX DESC Operation\n *   */\n\n#define MAX_TID (15)\n\n/* OFFSET 0 */\n#define OFFSET_SZ\t0\n#define OFFSET_SHT\t16\n#define BMC\t\tBIT(24)\n#define LSG\t\tBIT(26)\n#define FSG\t\tBIT(27)\n#define OWN\t\tBIT(31)\n\n\n/* OFFSET 4 */\n#define PKT_OFFSET_SZ\t\t0\n#define QSEL_SHT\t\t\t8\n#define RATE_ID_SHT\t\t\t16\n#define NAVUSEHDR\t\t\tBIT(20)\n#define SEC_TYPE_SHT\t\t22\n#define PKT_OFFSET_SHT\t\t26\n\n/* OFFSET 8 */\n#define AGG_EN\t\t\t\tBIT(12)\n#define AGG_BK\t\t\t\t\tBIT(16)\n#define AMPDU_DENSITY_SHT\t20\n#define ANTSEL_A\t\t\tBIT(24)\n#define ANTSEL_B\t\t\tBIT(25)\n#define TX_ANT_CCK_SHT\t\t26\n#define TX_ANTL_SHT\t\t\t28\n#define TX_ANT_HT_SHT\t\t30\n\n/* OFFSET 12 */\n#define SEQ_SHT\t\t\t\t16\n#define EN_HWSEQ\t\t\tBIT(31)\n\n/* OFFSET 16 */\n#define\tQOS                          BIT(6)\n#define\tHW_SSN\t\t\t\tBIT(7)\n#define\tUSERATE\t\t\tBIT(8)\n#define\tDISDATAFB\t\t\tBIT(10)\n#define   CTS_2_SELF\t\t\tBIT(11)\n#define\tRTS_EN\t\t\t\tBIT(12)\n#define\tHW_RTS_EN\t\t\tBIT(13)\n#define\tDATA_SHORT\t\t\tBIT(24)\n#define\tPWR_STATUS_SHT\t15\n#define\tDATA_SC_SHT\t\t20\n#define\tDATA_BW\t\t\tBIT(25)\n\n/* OFFSET 20 */\n#define\tRTY_LMT_EN\t\t\tBIT(17)\n\n\n/* OFFSET 20 */\n#define SGI\t\t\t\t\tBIT(6)\n#define USB_TXAGG_NUM_SHT\t24\n\ntypedef struct txdesc_88e {\n\t/* Offset 0 */\n\tu32 pktlen:16;\n\tu32 offset:8;\n\tu32 bmc:1;\n\tu32 htc:1;\n\tu32 ls:1;\n\tu32 fs:1;\n\tu32 linip:1;\n\tu32 noacm:1;\n\tu32 gf:1;\n\tu32 own:1;\n\n\t/* Offset 4 */\n\tu32 macid:6;\n\tu32 rsvd0406:2;\n\tu32 qsel:5;\n\tu32 rd_nav_ext:1;\n\tu32 lsig_txop_en:1;\n\tu32 pifs:1;\n\tu32 rate_id:4;\n\tu32 navusehdr:1;\n\tu32 en_desc_id:1;\n\tu32 sectype:2;\n\tu32 rsvd0424:2;\n\tu32 pkt_offset:5;\t/* unit: 8 bytes */\n\tu32 rsvd0431:1;\n\n\t/* Offset 8 */\n\tu32 rts_rc:6;\n\tu32 data_rc:6;\n\tu32 agg_en:1;\n\tu32 rd_en:1;\n\tu32 bar_rty_th:2;\n\tu32 bk:1;\n\tu32 morefrag:1;\n\tu32 raw:1;\n\tu32 ccx:1;\n\tu32 ampdu_density:3;\n\tu32 bt_null:1;\n\tu32 ant_sel_a:1;\n\tu32 ant_sel_b:1;\n\tu32 tx_ant_cck:2;\n\tu32 tx_antl:2;\n\tu32 tx_ant_ht:2;\n\n\t/* Offset 12 */\n\tu32 nextheadpage:8;\n\tu32 tailpage:8;\n\tu32 seq:12;\n\tu32 cpu_handle:1;\n\tu32 tag1:1;\n\tu32 trigger_int:1;\n\tu32 hwseq_en:1;\n\n\t/* Offset 16 */\n\tu32 rtsrate:5;\n\tu32 ap_dcfe:1;\n\tu32 hwseq_sel:2;\n\tu32 userate:1;\n\tu32 disrtsfb:1;\n\tu32 disdatafb:1;\n\tu32 cts2self:1;\n\tu32 rtsen:1;\n\tu32 hw_rts_en:1;\n\tu32 port_id:1;\n\tu32 pwr_status:3;\n\tu32 wait_dcts:1;\n\tu32 cts2ap_en:1;\n\tu32 data_sc:2;\n\tu32 data_stbc:2;\n\tu32 data_short:1;\n\tu32 data_bw:1;\n\tu32 rts_short:1;\n\tu32 rts_bw:1;\n\tu32 rts_sc:2;\n\tu32 vcs_stbc:2;\n\n\t/* Offset 20 */\n\tu32 datarate:6;\n\tu32 sgi:1;\n\tu32 try_rate:1;\n\tu32 data_ratefb_lmt:5;\n\tu32 rts_ratefb_lmt:4;\n\tu32 rty_lmt_en:1;\n\tu32 data_rt_lmt:6;\n\tu32 usb_txagg_num:8;\n\n\t/* Offset 24 */\n\tu32 txagg_a:5;\n\tu32 txagg_b:5;\n\tu32 use_max_len:1;\n\tu32 max_agg_num:5;\n\tu32 mcsg1_max_len:4;\n\tu32 mcsg2_max_len:4;\n\tu32 mcsg3_max_len:4;\n\tu32 mcs7_sgi_max_len:4;\n\n\t/* Offset 28 */\n\tu32 checksum:16;\t/* TxBuffSize(PCIe)/CheckSum(USB) */\n\tu32 sw0:8; /* offset 30 */\n\tu32 sw1:4;\n\tu32 mcs15_sgi_max_len:4;\n} TXDESC_8188E, *PTXDESC_8188E;\n\n#define txdesc_set_ccx_sw_88e(txdesc, value) \\\n\tdo { \\\n\t\t((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \\\n\t\t((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \\\n\t} while (0)\n\nstruct txrpt_ccx_88e {\n\t/* offset 0 */\n\tu8 tag1:1;\n\tu8 pkt_num:3;\n\tu8 txdma_underflow:1;\n\tu8 int_bt:1;\n\tu8 int_tri:1;\n\tu8 int_ccx:1;\n\n\t/* offset 1 */\n\tu8 mac_id:6;\n\tu8 pkt_ok:1;\n\tu8 bmc:1;\n\n\t/* offset 2 */\n\tu8 retry_cnt:6;\n\tu8 lifetime_over:1;\n\tu8 retry_over:1;\n\n\t/* offset 3 */\n\tu8 ccx_qtime0;\n\tu8 ccx_qtime1;\n\n\t/* offset 5 */\n\tu8 final_data_rate;\n\n\t/* offset 6 */\n\tu8 sw1:4;\n\tu8 qsel:4;\n\n\t/* offset 7 */\n\tu8 sw0;\n};\n\n#define txrpt_ccx_sw_88e(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8))\n#define txrpt_ccx_qtime_88e(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))\n\n#define SET_TX_DESC_SEC_TYPE_8188E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)\n\nvoid rtl8188e_fill_fake_txdesc(PADAPTER\tpadapter, u8 *pDesc, u32 BufferLen,\n\t\t\t       u8 IsPsPoll, u8\tIsBTQosNull, u8 bDataFrame);\nvoid rtl8188e_cal_txdesc_chksum(struct tx_desc\t*ptxdesc);\n#if defined(CONFIG_CONCURRENT_MODE)\n\tvoid fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);\n#endif\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\ts32 rtl8188es_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8188es_free_xmit_priv(PADAPTER padapter);\n\ts32 rtl8188es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8188es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\trtl8188es_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\tthread_return rtl8188es_xmit_thread(thread_context context);\n\ts32 rtl8188es_xmit_buf_handler(PADAPTER padapter);\n\n\t#ifdef CONFIG_SDIO_TX_TASKLET\n\t\tvoid rtl8188es_xmit_tasklet(void *priv);\n\t#endif\n#endif\n\n#ifdef CONFIG_USB_HCI\n\ts32 rtl8188eu_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8188eu_free_xmit_priv(PADAPTER padapter);\n\ts32 rtl8188eu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8188eu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\trtl8188eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8188eu_xmit_buf_handler(PADAPTER padapter);\n\tvoid rtl8188eu_xmit_tasklet(void *priv);\n\ts32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\ts32 rtl8188ee_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8188ee_free_xmit_priv(PADAPTER padapter);\n\tvoid\trtl8188ee_xmitframe_resume(_adapter *padapter);\n\ts32 rtl8188ee_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8188ee_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\trtl8188ee_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\tvoid rtl8188ee_xmit_tasklet(void *priv);\n#endif\n\n\n\n#ifdef CONFIG_TX_EARLY_MODE\n\tvoid UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\n#endif\n\n#ifdef CONFIG_XMIT_ACK\n\tvoid dump_txrpt_ccx_88e(void *buf);\n\tvoid handle_txrpt_ccx_88e(_adapter *adapter, u8 *buf);\n#else\n\t#define dump_txrpt_ccx_88e(buf) do {} while (0)\n\t#define handle_txrpt_ccx_88e(adapter, buf) do {} while (0)\n#endif /* CONFIG_XMIT_ACK */\n\nvoid _dbg_dump_tx_info(_adapter\t*padapter, int frame_tag, struct tx_desc *ptxdesc);\n#endif /* __RTL8188E_XMIT_H__ */\n"
  },
  {
    "path": "include/rtl8188f_cmd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8188F_CMD_H__\n#define __RTL8188F_CMD_H__\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\nenum h2c_cmd_8188F {\n\t/* Common Class: 000 */\n\tH2C_8188F_RSVD_PAGE = 0x00,\n\tH2C_8188F_MEDIA_STATUS_RPT = 0x01,\n\tH2C_8188F_SCAN_ENABLE = 0x02,\n\tH2C_8188F_KEEP_ALIVE = 0x03,\n\tH2C_8188F_DISCON_DECISION = 0x04,\n\tH2C_8188F_PSD_OFFLOAD = 0x05,\n\tH2C_8188F_AP_OFFLOAD = 0x08,\n\tH2C_8188F_BCN_RSVDPAGE = 0x09,\n\tH2C_8188F_PROBERSP_RSVDPAGE = 0x0A,\n\tH2C_8188F_FCS_RSVDPAGE = 0x10,\n\tH2C_8188F_FCS_INFO = 0x11,\n\tH2C_8188F_AP_WOW_GPIO_CTRL = 0x13,\n\n\t/* PoweSave Class: 001 */\n\tH2C_8188F_SET_PWR_MODE = 0x20,\n\tH2C_8188F_PS_TUNING_PARA = 0x21,\n\tH2C_8188F_PS_TUNING_PARA2 = 0x22,\n\tH2C_8188F_P2P_LPS_PARAM = 0x23,\n\tH2C_8188F_P2P_PS_OFFLOAD = 0x24,\n\tH2C_8188F_PS_SCAN_ENABLE = 0x25,\n\tH2C_8188F_SAP_PS_ = 0x26,\n\tH2C_8188F_INACTIVE_PS_ = 0x27, /* Inactive_PS */\n\tH2C_8188F_FWLPS_IN_IPS_ = 0x28,\n\n\t/* Dynamic Mechanism Class: 010 */\n\tH2C_8188F_MACID_CFG = 0x40,\n\tH2C_8188F_TXBF = 0x41,\n\tH2C_8188F_RSSI_SETTING = 0x42,\n\tH2C_8188F_AP_REQ_TXRPT = 0x43,\n\tH2C_8188F_INIT_RATE_COLLECT = 0x44,\n\tH2C_8188F_RA_PARA_ADJUST = 0x46,\n\n\t/* BT Class: 011 */\n\tH2C_8188F_B_TYPE_TDMA = 0x60,\n\tH2C_8188F_BT_INFO = 0x61,\n\tH2C_8188F_FORCE_BT_TXPWR = 0x62,\n\tH2C_8188F_BT_IGNORE_WLANACT = 0x63,\n\tH2C_8188F_DAC_SWING_VALUE = 0x64,\n\tH2C_8188F_ANT_SEL_RSV = 0x65,\n\tH2C_8188F_WL_OPMODE = 0x66,\n\tH2C_8188F_BT_MP_OPER = 0x67,\n\tH2C_8188F_BT_CONTROL = 0x68,\n\tH2C_8188F_BT_WIFI_CTRL = 0x69,\n\tH2C_8188F_BT_FW_PATCH = 0x6A,\n\tH2C_8188F_BT_WLAN_CALIBRATION = 0x6D,\n\n\t/* WOWLAN Class: 100 */\n\tH2C_8188F_WOWLAN = 0x80,\n\tH2C_8188F_REMOTE_WAKE_CTRL = 0x81,\n\tH2C_8188F_AOAC_GLOBAL_INFO = 0x82,\n\tH2C_8188F_AOAC_RSVD_PAGE = 0x83,\n\tH2C_8188F_AOAC_RSVD_PAGE2 = 0x84,\n\tH2C_8188F_D0_SCAN_OFFLOAD_CTRL = 0x85,\n\tH2C_8188F_D0_SCAN_OFFLOAD_INFO = 0x86,\n\tH2C_8188F_CHNL_SWITCH_OFFLOAD = 0x87,\n\tH2C_8188F_P2P_OFFLOAD_RSVD_PAGE = 0x8A,\n\tH2C_8188F_P2P_OFFLOAD = 0x8B,\n\n\tH2C_8188F_RESET_TSF = 0xC0,\n\tH2C_8188F_MAXID,\n};\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------\n * ---------------------------------------------------------------------------------------------------------\n * _RSVDPAGE_LOC_CMD_0x00 */\n#define SET_8188F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8188F_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_8188F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8188F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8188F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n/* _KEEP_ALIVE_CMD_0x03 */\n#define SET_8188F_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_8188F_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_8188F_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)\n#define SET_8188F_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n\n/* _DISCONNECT_DECISION_CMD_0x04 */\n#define SET_8188F_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_8188F_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_8188F_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_8188F_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)\n\n/* _PWR_MOD_CMD_0x20 */\n#define SET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8188F_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)\n#define SET_8188F_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)\n#define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8188F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)\n#define SET_8188F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n#define GET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)\t\t\t\t\tLE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)\n\n/* _PS_TUNE_PARAM_CMD_0x21 */\n#define SET_8188F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_8188F_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)\n#define SET_8188F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)\n#define SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n\n/* _MACID_CFG_CMD_0x40 */\n#define SET_8188F_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8188F_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)\n#define SET_8188F_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)\n#define SET_8188F_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)\n#define SET_8188F_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)\n#define SET_8188F_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)\n#define SET_8188F_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)\n#define SET_8188F_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)\n#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)\n#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)\n#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)\n\n/* _RSSI_SETTING_CMD_0x42 */\n#define SET_8188F_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8188F_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)\n#define SET_8188F_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n\n/* _AP_REQ_TXRPT_CMD_0x43 */\n#define SET_8188F_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8188F_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n\n/* _FORCE_BT_TXPWR_CMD_0x62 */\n#define SET_8188F_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n\n/* _FORCE_BT_MP_OPER_CMD_0x67 */\n#define SET_8188F_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)\n#define SET_8188F_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)\n#define SET_8188F_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_8188F_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)\n#define SET_8188F_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n#define SET_8188F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)\n\n/* _BT_FW_PATCH_0x6A */\n#define SET_8188F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)\n#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)\n\n\n/* ---------------------------------------------------------------------------------------------------------\n * -------------------------------------------    Structure    --------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    Function Statement     --------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\n/* host message to firmware cmd */\nvoid rtl8188f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);\nvoid rtl8188f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);\nvoid rtl8188f_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);\n/* s32 rtl8188f_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */\nvoid rtl8188f_set_FwPsTuneParam_cmd(PADAPTER padapter);\nvoid rtl8188f_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);\nvoid rtl8188f_download_rsvd_page(PADAPTER padapter, u8 mstatus);\n#ifdef CONFIG_BT_COEXIST\n\tvoid rtl8188f_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);\n#endif /* CONFIG_BT_COEXIST */\n#ifdef CONFIG_P2P\nvoid rtl8188f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\nvoid rtl8188f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);\n#endif\n#endif\n\n#ifdef CONFIG_P2P_WOWLAN\nvoid rtl8188f_set_p2p_wowlan_offload_cmd(PADAPTER padapter);\n#endif\n\nvoid rtl8188f_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);\n\ns32 FillH2CCmd8188F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);\nu8 GetTxBufferRsvdPageNum8188F(_adapter *padapter, bool wowlan);\n#endif\n"
  },
  {
    "path": "include/rtl8188f_dm.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8188F_DM_H__\n#define __RTL8188F_DM_H__\n/* ************************************************************\n * Description:\n *\n * This file is for 8188F dynamic mechanism only\n *\n *\n * ************************************************************ */\n\n/* ************************************************************\n * structure and define\n * ************************************************************ */\n\n/* ************************************************************\n * function prototype\n * ************************************************************ */\n\nvoid rtl8188f_init_dm_priv(PADAPTER padapter);\nvoid rtl8188f_deinit_dm_priv(PADAPTER padapter);\n\nvoid rtl8188f_InitHalDm(PADAPTER padapter);\nvoid rtl8188f_HalDmWatchDog(PADAPTER padapter);\n\n#endif\n"
  },
  {
    "path": "include/rtl8188f_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8188F_HAL_H__\n#define __RTL8188F_HAL_H__\n\n#include \"hal_data.h\"\n\n#include \"rtl8188f_spec.h\"\n#include \"rtl8188f_rf.h\"\n#include \"rtl8188f_dm.h\"\n#include \"rtl8188f_recv.h\"\n#include \"rtl8188f_xmit.h\"\n#include \"rtl8188f_cmd.h\"\n#include \"rtl8188f_led.h\"\n#include \"Hal8188FPwrSeq.h\"\n#include \"Hal8188FPhyReg.h\"\n#include \"Hal8188FPhyCfg.h\"\n#ifdef DBG_CONFIG_ERROR_DETECT\n#include \"rtl8188f_sreset.h\"\n#endif\n\n#define FW_8188F_SIZE\t\t\t0x8000\n#define FW_8188F_START_ADDRESS\t0x1000\n#define FW_8188F_END_ADDRESS\t\t0x1FFF /* 0x5FFF */\n\n#define IS_FW_HEADER_EXIST_8188F(_pFwHdr)\t((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x88F0)\n\ntypedef struct _RT_FIRMWARE {\n\tFIRMWARE_SOURCE\teFWSource;\n#ifdef CONFIG_EMBEDDED_FWIMG\n\tu8\t\t\t*szFwBuffer;\n#else\n\tu8\t\t\tszFwBuffer[FW_8188F_SIZE];\n#endif\n\tu32\t\t\tulFwLength;\n} RT_FIRMWARE_8188F, *PRT_FIRMWARE_8188F;\n\n/*\n * This structure must be cared byte-ordering\n *\n * Added by tynli. 2009.12.04. */\ntypedef struct _RT_8188F_FIRMWARE_HDR {\n\t/* 8-byte alinment required */\n\n\t/* --- LONG WORD 0 ---- */\n\tu16\t\tSignature;\t/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */\n\tu8\t\tCategory;\t/* AP/NIC and USB/PCI */\n\tu8\t\tFunction;\t/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */\n\tu16\t\tVersion;\t\t/* FW Version */\n\tu16\t\tSubversion;\t/* FW Subversion, default 0x00 */\n\n\t/* --- LONG WORD 1 ---- */\n\tu8\t\tMonth;\t/* Release time Month field */\n\tu8\t\tDate;\t/* Release time Date field */\n\tu8\t\tHour;\t/* Release time Hour field */\n\tu8\t\tMinute;\t/* Release time Minute field */\n\tu16\t\tRamCodeSize;\t/* The size of RAM code */\n\tu16\t\tRsvd2;\n\n\t/* --- LONG WORD 2 ---- */\n\tu32\t\tSvnIdx;\t/* The SVN entry index */\n\tu32\t\tRsvd3;\n\n\t/* --- LONG WORD 3 ---- */\n\tu32\t\tRsvd4;\n\tu32\t\tRsvd5;\n} RT_8188F_FIRMWARE_HDR, *PRT_8188F_FIRMWARE_HDR;\n\n#define DRIVER_EARLY_INT_TIME_8188F\t\t0x05\n#define BCN_DMA_ATIME_INT_TIME_8188F\t\t0x02\n\n/* for 8188F\n * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */\n#define PAGE_SIZE_TX_8188F\t\t\t128\n#define PAGE_SIZE_RX_8188F\t\t\t8\n\n#define RX_DMA_SIZE_8188F\t\t\t0x4000\t/* 16K */\n#ifdef CONFIG_FW_C2H_DEBUG\n\t#define RX_DMA_RESERVED_SIZE_8188F\t0x100\t/* 256B, reserved for c2h debug message */\n#else\n\t#define RX_DMA_RESERVED_SIZE_8188F\t0x80\t/* 128B, reserved for tx report */\n#endif\n\n#ifdef CONFIG_WOWLAN\n\t#define RESV_FMWF\t(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/\n#else\n\t#define RESV_FMWF\t0\n#endif\n\n#define RX_DMA_BOUNDARY_8188F\t\t(RX_DMA_SIZE_8188F - RX_DMA_RESERVED_SIZE_8188F - 1)\n\n/* Note: We will divide number of page equally for each queue other than public queue! */\n\n/* For General Reserved Page Number(Beacon Queue is reserved page)\n * BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_8188F,\n * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1, CTS-2-SELF / LTE QoS Null */\n\n#define BCNQ_PAGE_NUM_8188F\t\t(MAX_BEACON_LEN / PAGE_SIZE_TX_8188F + 6) /*0x08*/\n\n/* For WoWLan , more reserved page\n * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt:1 ,PNO: 6\n * NS offload:2 NDP info: 1\n */\n#ifdef CONFIG_WOWLAN\n\t#define WOWLAN_PAGE_NUM_8188F\t0x0b\n#else\n\t#define WOWLAN_PAGE_NUM_8188F\t0x00\n#endif\n\n#ifdef CONFIG_PNO_SUPPORT\n#undef WOWLAN_PAGE_NUM_8188F\n#define WOWLAN_PAGE_NUM_8188F\t0x15\n#endif\n\n#ifdef CONFIG_AP_WOWLAN\n#define AP_WOWLAN_PAGE_NUM_8188F\t0x02\n#endif\n\n#define TX_TOTAL_PAGE_NUMBER_8188F\t(0xFF - BCNQ_PAGE_NUM_8188F - WOWLAN_PAGE_NUM_8188F)\n#define TX_PAGE_BOUNDARY_8188F\t\t(TX_TOTAL_PAGE_NUMBER_8188F + 1)\n\n#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F\tTX_TOTAL_PAGE_NUMBER_8188F\n#define WMM_NORMAL_TX_PAGE_BOUNDARY_8188F\t\t(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F + 1)\n\n/* For Normal Chip Setting\n * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8188F */\n#define NORMAL_PAGE_NUM_HPQ_8188F\t\t0x0C\n#define NORMAL_PAGE_NUM_LPQ_8188F\t\t0x02\n#define NORMAL_PAGE_NUM_NPQ_8188F\t\t0x02\n\n/* Note: For Normal Chip Setting, modify later */\n#define WMM_NORMAL_PAGE_NUM_HPQ_8188F\t\t0x30\n#define WMM_NORMAL_PAGE_NUM_LPQ_8188F\t\t0x20\n#define WMM_NORMAL_PAGE_NUM_NPQ_8188F\t\t0x20\n\n\n#include \"HalVerDef.h\"\n#include \"hal_com.h\"\n\n#define EFUSE_OOB_PROTECT_BYTES (34 + 1)\n\n#define HAL_EFUSE_MEMORY\n\n#define HWSET_MAX_SIZE_8188F\t\t\t512\n#define EFUSE_REAL_CONTENT_LEN_8188F\t256\n#define EFUSE_MAP_LEN_8188F\t\t\t\t512\n#define EFUSE_MAX_SECTION_8188F\t\t\t(EFUSE_MAP_LEN_8188F / 8)\n\n#define EFUSE_IC_ID_OFFSET\t\t\t506\t/* For some inferiority IC purpose. added by Roger, 2009.09.02. */\n#define AVAILABLE_EFUSE_ADDR(addr)\t(addr < EFUSE_REAL_CONTENT_LEN_8188F)\n\n#define EFUSE_ACCESS_ON\t\t\t0x69\t/* For RTL8188 only. */\n#define EFUSE_ACCESS_OFF\t\t\t0x00\t/* For RTL8188 only. */\n\n/* ********************************************************\n *\t\t\tEFUSE for BT definition\n * ******************************************************** */\n#define EFUSE_BT_REAL_BANK_CONTENT_LEN\t512\n#define EFUSE_BT_REAL_CONTENT_LEN\t\t1536\t/* 512*3 */\n#define EFUSE_BT_MAP_LEN\t\t\t\t1024\t/* 1k bytes */\n#define EFUSE_BT_MAX_SECTION\t\t\t128\t\t/* 1024/8 */\n\n#define EFUSE_PROTECT_BYTES_BANK\t\t16\n\n#define INCLUDE_MULTI_FUNC_BT(_Adapter)\t\t(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)\n#define INCLUDE_MULTI_FUNC_GPS(_Adapter)\t(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)\n\n/* rtl8188a_hal_init.c */\ns32 rtl8188f_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);\nvoid rtl8188f_FirmwareSelfReset(PADAPTER padapter);\nvoid rtl8188f_InitializeFirmwareVars(PADAPTER padapter);\n\nvoid rtl8188f_InitAntenna_Selection(PADAPTER padapter);\nvoid rtl8188f_DeinitAntenna_Selection(PADAPTER padapter);\nvoid rtl8188f_CheckAntenna_Selection(PADAPTER padapter);\nvoid rtl8188f_init_default_value(PADAPTER padapter);\n\ns32 rtl8188f_InitLLTTable(PADAPTER padapter);\n\ns32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);\ns32 CardDisableWithoutHWSM(PADAPTER padapter);\n\n/* EFuse */\nu8 GetEEPROMSize8188F(PADAPTER padapter);\nvoid Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);\nvoid Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);\nvoid Hal_EfuseParseTxPowerInfo_8188F(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);\n/* void Hal_EfuseParseBTCoexistInfo_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); */\nvoid Hal_EfuseParseEEPROMVer_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseChnlPlan_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseCustomerID_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParsePowerSavingMode_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseAntennaDiversity_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseXtal_8188F(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);\nvoid Hal_EfuseParseThermalMeter_8188F(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);\nvoid Hal_EfuseParseKFreeData_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\n\n#if 0 /* Do not need for rtl8188f */\nvoid Hal_EfuseParseVoltage_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN\tAutoLoadFail);\n#endif\n\nvoid rtl8188f_set_pll_ref_clk_sel(_adapter *adapter, u8 sel);\n\nvoid rtl8188f_set_hal_ops(struct hal_ops *pHalFunc);\nvoid init_hal_spec_8188f(_adapter *adapter);\nu8 SetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val);\nvoid GetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val);\nu8 SetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);\nu8 GetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);\n\n/* register */\nvoid rtl8188f_InitBeaconParameters(PADAPTER padapter);\nvoid rtl8188f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);\nvoid\t_InitBurstPktLen_8188FS(PADAPTER Adapter);\nvoid _8051Reset8188(PADAPTER padapter);\n#ifdef CONFIG_WOWLAN\nvoid Hal_DetectWoWMode(PADAPTER pAdapter);\n#endif /* CONFIG_WOWLAN */\n\nvoid rtl8188f_start_thread(_adapter *padapter);\nvoid rtl8188f_stop_thread(_adapter *padapter);\n\n#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)\n\tvoid rtl8188fs_init_checkbthang_workqueue(_adapter *adapter);\n\tvoid rtl8188fs_free_checkbthang_workqueue(_adapter *adapter);\n\tvoid rtl8188fs_cancle_checkbthang_workqueue(_adapter *adapter);\n\tvoid rtl8188fs_hal_check_bt_hang(_adapter *adapter);\n#endif\n\n#ifdef CONFIG_GPIO_WAKEUP\nvoid HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);\n#endif\n\n#ifdef CONFIG_MP_INCLUDED\nint FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);\n#endif\n\nvoid CCX_FwC2HTxRpt_8188f(PADAPTER padapter, u8 *pdata, u8 len);\n\nu8 MRateToHwRate8188F(u8  rate);\nu8 HwRateToMRate8188F(u8\t rate);\n\n#ifdef CONFIG_PCI_HCI\nBOOLEAN\tInterruptRecognized8188FE(PADAPTER Adapter);\nvoid\tUpdateInterruptMask8188FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);\n#endif\n\n#endif\n"
  },
  {
    "path": "include/rtl8188f_led.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8188F_LED_H__\n#define __RTL8188F_LED_H__\n#ifdef CONFIG_RTW_SW_LED\n\n#include <drv_conf.h>\n#include <osdep_service.h>\n#include <drv_types.h>\n\n\n/* ********************************************************************************\n * Interface to manipulate LED objects.\n * ******************************************************************************** */\n#ifdef CONFIG_USB_HCI\nvoid rtl8188fu_InitSwLeds(PADAPTER padapter);\nvoid rtl8188fu_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_SDIO_HCI\nvoid rtl8188fs_InitSwLeds(PADAPTER padapter);\nvoid rtl8188fs_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_GSPI_HCI\nvoid rtl8188fs_InitSwLeds(PADAPTER padapter);\nvoid rtl8188fs_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_PCI_HCI\nvoid rtl8188fe_InitSwLeds(PADAPTER padapter);\nvoid rtl8188fe_DeInitSwLeds(PADAPTER padapter);\n#endif\n\n#endif\n#endif/*CONFIG_RTW_SW_LED*/\n"
  },
  {
    "path": "include/rtl8188f_recv.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8188F_RECV_H__\n#define __RTL8188F_RECV_H__\n\n#if defined(CONFIG_USB_HCI)\n\t#ifndef MAX_RECVBUF_SZ\n\n\t\t#ifdef CONFIG_MINIMAL_MEMORY_USAGE\n\t\t\t#define MAX_RECVBUF_SZ (4000) /* about 4K */\n\t\t#else\n\t\t\t#ifdef CONFIG_PLATFORM_MSTAR\n\t\t\t\t#define MAX_RECVBUF_SZ (8192) /* 8K */\n\t\t\t#elif defined(CONFIG_PLATFORM_HISILICON)\n\t\t\t\t#define MAX_RECVBUF_SZ (16384) /* 16k */\n\t\t\t#else\n\t\t\t\t#define MAX_RECVBUF_SZ (32768) /* 32k */\n\t\t\t#endif\n\t\t\t/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */\n\t\t\t/* #define MAX_RECVBUF_SZ (10240)  */ /* 10K */\n\t\t\t/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */\n\t\t\t/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k\t\t */\n\t\t#endif\n\t#endif /* !MAX_RECVBUF_SZ */\n#elif defined(CONFIG_PCI_HCI)\n\t#define MAX_RECVBUF_SZ (4000) /* about 4K */\n#elif defined(CONFIG_SDIO_HCI)\n\t#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8188F + 1)\n#endif /* CONFIG_SDIO_HCI */\n\n/* Rx smooth factor */\n#define\tRx_Smooth_Factor (20)\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\ns32 rtl8188fs_init_recv_priv(PADAPTER padapter);\nvoid rtl8188fs_free_recv_priv(PADAPTER padapter);\ns32 rtl8188fs_recv_hdl(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_USB_HCI\nint rtl8188fu_init_recv_priv(_adapter *padapter);\nvoid rtl8188fu_free_recv_priv(_adapter *padapter);\nvoid rtl8188fu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);\n#endif\n\n#ifdef CONFIG_PCI_HCI\ns32 rtl8188fe_init_recv_priv(PADAPTER padapter);\nvoid rtl8188fe_free_recv_priv(PADAPTER padapter);\n#endif\n\nvoid rtl8188f_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);\n\n#endif /* __RTL8188F_RECV_H__ */\n"
  },
  {
    "path": "include/rtl8188f_rf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8188F_RF_H__\n#define __RTL8188F_RF_H__\n\nint\tPHY_RF6052_Config8188F(PADAPTER\t\tAdapter);\n\nvoid\nPHY_RF6052SetBandwidth8188F(\n\t\tPADAPTER\t\t\t\tAdapter,\n\t\tenum channel_width\t\tBandwidth);\n\n#endif\n"
  },
  {
    "path": "include/rtl8188f_spec.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8188F_SPEC_H__\n#define __RTL8188F_SPEC_H__\n\n#include <drv_conf.h>\n\n\n#define HAL_NAV_UPPER_UNIT_8188F\t\t128\t\t/* micro-second */\n\n/* -----------------------------------------------------\n *\n *\t0x0000h ~ 0x00FFh\tSystem Configuration\n *\n * ----------------------------------------------------- */\n#define REG_RSV_CTRL_8188F\t\t\t\t0x001C\t/* 3 Byte */\n#define REG_BT_WIFI_ANTENNA_SWITCH_8188F\t0x0038\n#define REG_HSISR_8188F\t\t\t\t\t0x005c\n#define REG_PAD_CTRL1_8188F\t\t0x0064\n#define REG_AFE_CTRL_4_8188F\t\t0x0078\n#define REG_HMEBOX_DBG_0_8188F\t0x0088\n#define REG_HMEBOX_DBG_1_8188F\t0x008A\n#define REG_HMEBOX_DBG_2_8188F\t0x008C\n#define REG_HMEBOX_DBG_3_8188F\t0x008E\n#define REG_HIMR0_8188F\t\t\t\t\t0x00B0\n#define REG_HISR0_8188F\t\t\t\t\t0x00B4\n#define REG_HIMR1_8188F\t\t\t\t\t0x00B8\n#define REG_HISR1_8188F\t\t\t\t\t0x00BC\n#define REG_PMC_DBG_CTRL2_8188F\t\t\t0x00CC\n\n/* -----------------------------------------------------\n *\n *\t0x0100h ~ 0x01FFh\tMACTOP General Configuration\n *\n * ----------------------------------------------------- */\n#define REG_C2HEVT_CMD_ID_8188F\t0x01A0\n#define REG_C2HEVT_CMD_LEN_8188F\t0x01AE\n#define REG_WOWLAN_WAKE_REASON 0x01C7\n#define REG_WOWLAN_GTK_DBG1\t0x630\n#define REG_WOWLAN_GTK_DBG2\t0x634\n\n#define REG_HMEBOX_EXT0_8188F\t\t\t0x01F0\n#define REG_HMEBOX_EXT1_8188F\t\t\t0x01F4\n#define REG_HMEBOX_EXT2_8188F\t\t\t0x01F8\n#define REG_HMEBOX_EXT3_8188F\t\t\t0x01FC\n\n/* -----------------------------------------------------\n *\n *\t0x0200h ~ 0x027Fh\tTXDMA Configuration\n *\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n *\n *\t0x0280h ~ 0x02FFh\tRXDMA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_RXDMA_CONTROL_8188F\t\t0x0286 /* Control the RX DMA. */\n#define REG_RXDMA_MODE_CTRL_8188F\t\t0x0290\n\n/* -----------------------------------------------------\n *\n *\t0x0300h ~ 0x03FFh\tPCIe\n *\n * ----------------------------------------------------- */\n#define\tREG_PCIE_CTRL_REG_8188F\t\t0x0300\n#define\tREG_INT_MIG_8188F\t\t\t\t0x0304\t/* Interrupt Migration */\n#define\tREG_BCNQ_DESA_8188F\t\t\t0x0308\t/* TX Beacon Descriptor Address */\n#define\tREG_HQ_DESA_8188F\t\t\t\t0x0310\t/* TX High Queue Descriptor Address */\n#define\tREG_MGQ_DESA_8188F\t\t\t0x0318\t/* TX Manage Queue Descriptor Address */\n#define\tREG_VOQ_DESA_8188F\t\t\t0x0320\t/* TX VO Queue Descriptor Address */\n#define\tREG_VIQ_DESA_8188F\t\t\t\t0x0328\t/* TX VI Queue Descriptor Address */\n#define\tREG_BEQ_DESA_8188F\t\t\t0x0330\t/* TX BE Queue Descriptor Address */\n#define\tREG_BKQ_DESA_8188F\t\t\t0x0338\t/* TX BK Queue Descriptor Address */\n#define\tREG_RX_DESA_8188F\t\t\t\t0x0340\t/* RX Queue\tDescriptor Address */\n#define\tREG_DBI_WDATA_8188F\t\t\t0x0348\t/* DBI Write Data */\n#define\tREG_DBI_RDATA_8188F\t\t\t0x034C\t/* DBI Read Data */\n#define\tREG_DBI_ADDR_8188F\t\t\t\t0x0350\t/* DBI Address */\n#define\tREG_DBI_FLAG_8188F\t\t\t\t0x0352\t/* DBI Read/Write Flag */\n#define\tREG_MDIO_WDATA_8188F\t\t0x0354\t/* MDIO for Write PCIE PHY */\n#define\tREG_MDIO_RDATA_8188F\t\t\t0x0356\t/* MDIO for Reads PCIE PHY */\n#define\tREG_MDIO_CTL_8188F\t\t\t0x0358\t/* MDIO for Control */\n#define\tREG_DBG_SEL_8188F\t\t\t\t0x0360\t/* Debug Selection Register */\n#define\tREG_PCIE_HRPWM_8188F\t\t\t0x0361\t/* PCIe RPWM */\n#define\tREG_PCIE_HCPWM_8188F\t\t\t0x0363\t/* PCIe CPWM */\n#define\tREG_PCIE_MULTIFET_CTRL_8188F\t0x036A\t/* PCIE Multi-Fethc Control */\n\n/* -----------------------------------------------------\n *\n *\t0x0400h ~ 0x047Fh\tProtocol Configuration\n *\n * ----------------------------------------------------- */\n#define REG_TXPKTBUF_BCNQ_BDNY_8188F\t0x0424\n#define REG_TXPKTBUF_MGQ_BDNY_8188F\t0x0425\n#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F\t0x045D\n#ifdef CONFIG_WOWLAN\n#define REG_TXPKTBUF_IV_LOW             0x0484\n#define REG_TXPKTBUF_IV_HIGH            0x0488\n#endif\n#define REG_AMPDU_BURST_MODE_8188F\t0x04BC\n\n/* -----------------------------------------------------\n *\n *\t0x0500h ~ 0x05FFh\tEDCA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_SECONDARY_CCA_CTRL_8188F\t0x0577\n\n/* -----------------------------------------------------\n *\n *\t0x0600h ~ 0x07FFh\tWMAC Configuration\n *\n * ----------------------------------------------------- */\n\n\n/* ************************************************************\n * SDIO Bus Specification\n * ************************************************************ */\n\n/* -----------------------------------------------------\n * SDIO CMD Address Mapping\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n * I/O bus domain (Host)\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n * SDIO register\n * ----------------------------------------------------- */\n#define SDIO_REG_HIQ_FREEPG_8188F\t\t0x0020\n#define SDIO_REG_MID_FREEPG_8188F\t\t0x0022\n#define SDIO_REG_LOW_FREEPG_8188F\t\t0x0024\n#define SDIO_REG_PUB_FREEPG_8188F\t\t0x0026\n#define SDIO_REG_EXQ_FREEPG_8188F\t\t0x0028\n#define SDIO_REG_AC_OQT_FREEPG_8188F\t0x002A\n#define SDIO_REG_NOAC_OQT_FREEPG_8188F\t0x002B\n\n#define SDIO_REG_HCPWM1_8188F\t\t\t0x0038\n\n/* ****************************************************************************\n *\t8188 Regsiter Bit and Content definition\n * **************************************************************************** */\n\n/* 2 HSISR\n * interrupt mask which needs to clear */\n#define MASK_HSISR_CLEAR\t\t(HSISR_GPIO12_0_INT |\\\n\t\tHSISR_SPS_OCP_INT |\\\n\t\tHSISR_RON_INT |\\\n\t\tHSISR_PDNINT |\\\n\t\tHSISR_GPIO9_INT)\n\n/* -----------------------------------------------------\n *\n *\t0x0100h ~ 0x01FFh\tMACTOP General Configuration\n *\n * ----------------------------------------------------- */\n\n\n/* -----------------------------------------------------\n *\n *\t0x0200h ~ 0x027Fh\tTXDMA Configuration\n *\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n *\n *\t0x0280h ~ 0x02FFh\tRXDMA Configuration\n *\n * ----------------------------------------------------- */\n#define BIT_USB_RXDMA_AGG_EN\tBIT(31)\n#define RXDMA_AGG_MODE_EN\t\tBIT(1)\n\n#ifdef CONFIG_WOWLAN\n#define RXPKT_RELEASE_POLL\t\tBIT(16)\n#define RXDMA_IDLE\t\t\t\tBIT(17)\n#define RW_RELEASE_EN\t\t\tBIT(18)\n#endif\n\n/* -----------------------------------------------------\n *\n *\t0x0400h ~ 0x047Fh\tProtocol Configuration\n *\n * ----------------------------------------------------- */\n\n/* ----------------------------------------------------------------------------\n * 8188F REG_CCK_CHECK\t\t\t\t\t\t(offset 0x454)\n * ---------------------------------------------------------------------------- */\n#define BIT_BCN_PORT_SEL\t\tBIT(5)\n\n/* -----------------------------------------------------\n *\n *\t0x0500h ~ 0x05FFh\tEDCA Configuration\n *\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n *\n *\t0x0600h ~ 0x07FFh\tWMAC Configuration\n *\n * ----------------------------------------------------- */\n\n/* ----------------------------------------------------------------------------\n * 8195 IMR/ISR bits\t\t\t\t\t\t(offset 0xB0,  8bits)\n * ---------------------------------------------------------------------------- */\n#define\tIMR_DISABLED_8188F\t\t\t\t\t0\n/* IMR DW0(0x00B0-00B3) Bit 0-31 */\n#define\tIMR_TIMER2_8188F\t\t\t\t\tBIT(31)\t\t/* Timeout interrupt 2 */\n#define\tIMR_TIMER1_8188F\t\t\t\t\tBIT(30)\t\t/* Timeout interrupt 1\t */\n#define\tIMR_PSTIMEOUT_8188F\t\t\t\tBIT(29)\t\t/* Power Save Time Out Interrupt */\n#define\tIMR_GTINT4_8188F\t\t\t\t\tBIT(28)\t\t/* When GTIMER4 expires, this bit is set to 1\t */\n#define\tIMR_GTINT3_8188F\t\t\t\t\tBIT(27)\t\t/* When GTIMER3 expires, this bit is set to 1\t */\n#define\tIMR_TXBCN0ERR_8188F\t\t\t\tBIT(26)\t\t/* Transmit Beacon0 Error\t\t\t */\n#define\tIMR_TXBCN0OK_8188F\t\t\t\tBIT(25)\t\t/* Transmit Beacon0 OK\t\t\t */\n#define\tIMR_TSF_BIT32_TOGGLE_8188F\t\tBIT(24)\t\t/* TSF Timer BIT(32) toggle indication interrupt\t\t\t */\n#define\tIMR_BCNDMAINT0_8188F\t\t\t\tBIT(20)\t\t/* Beacon DMA Interrupt 0\t\t\t */\n#define\tIMR_BCNDERR0_8188F\t\t\t\tBIT(16)\t\t/* Beacon Queue DMA OK0\t\t\t */\n#define\tIMR_HSISR_IND_ON_INT_8188F\t\tBIT(15)\t\t/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */\n#define\tIMR_BCNDMAINT_E_8188F\t\t\tBIT(14)\t\t/* Beacon DMA Interrupt Extension for Win7\t\t\t */\n#define\tIMR_ATIMEND_8188F\t\t\t\tBIT(12)\t\t/* CTWidnow End or ATIM Window End */\n#define\tIMR_C2HCMD_8188F\t\t\t\t\tBIT(10)\t\t/* CPU to Host Command INT Status, Write 1 clear\t */\n#define\tIMR_CPWM2_8188F\t\t\t\t\tBIT(9)\t\t\t/* CPU power Mode exchange INT Status, Write 1 clear\t */\n#define\tIMR_CPWM_8188F\t\t\t\t\tBIT(8)\t\t\t/* CPU power Mode exchange INT Status, Write 1 clear\t */\n#define\tIMR_HIGHDOK_8188F\t\t\t\tBIT(7)\t\t\t/* High Queue DMA OK\t */\n#define\tIMR_MGNTDOK_8188F\t\t\t\tBIT(6)\t\t\t/* Management Queue DMA OK\t */\n#define\tIMR_BKDOK_8188F\t\t\t\t\tBIT(5)\t\t\t/* AC_BK DMA OK\t\t */\n#define\tIMR_BEDOK_8188F\t\t\t\t\tBIT(4)\t\t\t/* AC_BE DMA OK\t */\n#define\tIMR_VIDOK_8188F\t\t\t\t\tBIT(3)\t\t\t/* AC_VI DMA OK\t\t */\n#define\tIMR_VODOK_8188F\t\t\t\t\tBIT(2)\t\t\t/* AC_VO DMA OK\t */\n#define\tIMR_RDU_8188F\t\t\t\t\tBIT(1)\t\t\t/* Rx Descriptor Unavailable\t */\n#define\tIMR_ROK_8188F\t\t\t\t\tBIT(0)\t\t\t/* Receive DMA OK */\n\n/* IMR DW1(0x00B4-00B7) Bit 0-31 */\n#define\tIMR_BCNDMAINT7_8188F\t\t\t\tBIT(27)\t\t/* Beacon DMA Interrupt 7 */\n#define\tIMR_BCNDMAINT6_8188F\t\t\t\tBIT(26)\t\t/* Beacon DMA Interrupt 6 */\n#define\tIMR_BCNDMAINT5_8188F\t\t\t\tBIT(25)\t\t/* Beacon DMA Interrupt 5 */\n#define\tIMR_BCNDMAINT4_8188F\t\t\t\tBIT(24)\t\t/* Beacon DMA Interrupt 4 */\n#define\tIMR_BCNDMAINT3_8188F\t\t\t\tBIT(23)\t\t/* Beacon DMA Interrupt 3 */\n#define\tIMR_BCNDMAINT2_8188F\t\t\t\tBIT(22)\t\t/* Beacon DMA Interrupt 2 */\n#define\tIMR_BCNDMAINT1_8188F\t\t\t\tBIT(21)\t\t/* Beacon DMA Interrupt 1 */\n#define\tIMR_BCNDOK7_8188F\t\t\t\t\tBIT(20)\t\t/* Beacon Queue DMA OK Interrupt 7 */\n#define\tIMR_BCNDOK6_8188F\t\t\t\t\tBIT(19)\t\t/* Beacon Queue DMA OK Interrupt 6 */\n#define\tIMR_BCNDOK5_8188F\t\t\t\t\tBIT(18)\t\t/* Beacon Queue DMA OK Interrupt 5 */\n#define\tIMR_BCNDOK4_8188F\t\t\t\t\tBIT(17)\t\t/* Beacon Queue DMA OK Interrupt 4 */\n#define\tIMR_BCNDOK3_8188F\t\t\t\t\tBIT(16)\t\t/* Beacon Queue DMA OK Interrupt 3 */\n#define\tIMR_BCNDOK2_8188F\t\t\t\t\tBIT(15)\t\t/* Beacon Queue DMA OK Interrupt 2 */\n#define\tIMR_BCNDOK1_8188F\t\t\t\t\tBIT(14)\t\t/* Beacon Queue DMA OK Interrupt 1 */\n#define\tIMR_ATIMEND_E_8188F\t\t\t\tBIT(13)\t\t/* ATIM Window End Extension for Win7 */\n#define\tIMR_TXERR_8188F\t\t\t\t\tBIT(11)\t\t/* Tx Error Flag Interrupt Status, write 1 clear. */\n#define\tIMR_RXERR_8188F\t\t\t\t\tBIT(10)\t\t/* Rx Error Flag INT Status, Write 1 clear */\n#define\tIMR_TXFOVW_8188F\t\t\t\t\tBIT(9)\t\t\t/* Transmit FIFO Overflow */\n#define\tIMR_RXFOVW_8188F\t\t\t\t\tBIT(8)\t\t\t/* Receive FIFO Overflow */\n\n#ifdef CONFIG_PCI_HCI\n/* #define IMR_RX_MASK\t\t(IMR_ROK_8188F|IMR_RDU_8188F|IMR_RXFOVW_8188F) */\n#define IMR_TX_MASK\t\t\t(IMR_VODOK_8188F | IMR_VIDOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F | IMR_MGNTDOK_8188F | IMR_HIGHDOK_8188F)\n\n#define RT_BCN_INT_MASKS\t(IMR_BCNDMAINT0_8188F | IMR_TXBCN0OK_8188F | IMR_TXBCN0ERR_8188F | IMR_BCNDERR0_8188F)\n\n#define RT_AC_INT_MASKS\t(IMR_VIDOK_8188F | IMR_VODOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F)\n#endif\n\n#endif /* __RTL8188F_SPEC_H__ */\n"
  },
  {
    "path": "include/rtl8188f_sreset.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8188F_SRESET_H_\n#define _RTL8188F_SRESET_H_\n\n#include <rtw_sreset.h>\n\n#ifdef DBG_CONFIG_ERROR_DETECT\nextern void rtl8188f_sreset_xmit_status_check(_adapter *padapter);\nextern void rtl8188f_sreset_linked_status_check(_adapter *padapter);\n#endif\n#endif\n"
  },
  {
    "path": "include/rtl8188f_xmit.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8188F_XMIT_H__\n#define __RTL8188F_XMIT_H__\n\n\n#define MAX_TID (15)\n\n\n#ifndef __INC_HAL8188FDESC_H\n#define __INC_HAL8188FDESC_H\n\n#define RX_STATUS_DESC_SIZE_8188F\t\t24\n#define RX_DRV_INFO_SIZE_UNIT_8188F 8\n\n\n/* DWORD 0 */\n#define SET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)\n#define SET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)\n#define SET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)\n\n#define GET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)\n#define GET_RX_STATUS_DESC_CRC32_8188F(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)\n#define GET_RX_STATUS_DESC_ICV_8188F(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)\n#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8188F(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)\n#define GET_RX_STATUS_DESC_SECURITY_8188F(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)\n#define GET_RX_STATUS_DESC_QOS_8188F(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)\n#define GET_RX_STATUS_DESC_SHIFT_8188F(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)\n#define GET_RX_STATUS_DESC_PHY_STATUS_8188F(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)\n#define GET_RX_STATUS_DESC_SWDEC_8188F(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)\n#define GET_RX_STATUS_DESC_LAST_SEG_8188F(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)\n#define GET_RX_STATUS_DESC_FIRST_SEG_8188F(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)\n#define GET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)\n#define GET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)\n\n/* DWORD 1 */\n#define GET_RX_STATUS_DESC_MACID_8188F(__pRxDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)\n#define GET_RX_STATUS_DESC_TID_8188F(__pRxDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)\n#define GET_RX_STATUS_DESC_AMSDU_8188F(__pRxDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)\n#define GET_RX_STATUS_DESC_RXID_MATCH_8188F(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)\n#define GET_RX_STATUS_DESC_PAGGR_8188F(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)\n#define GET_RX_STATUS_DESC_A1_FIT_8188F(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)\n#define GET_RX_STATUS_DESC_CHKERR_8188F(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)\n#define GET_RX_STATUS_DESC_IPVER_8188F(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)\n#define GET_RX_STATUS_DESC_IS_TCPUDP__8188F(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)\n#define GET_RX_STATUS_DESC_CHK_VLD_8188F(__pRxDesc)\tLE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)\n#define GET_RX_STATUS_DESC_PAM_8188F(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)\n#define GET_RX_STATUS_DESC_PWR_8188F(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)\n#define GET_RX_STATUS_DESC_MORE_DATA_8188F(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)\n#define GET_RX_STATUS_DESC_MORE_FRAG_8188F(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)\n#define GET_RX_STATUS_DESC_TYPE_8188F(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)\n#define GET_RX_STATUS_DESC_MC_8188F(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)\n#define GET_RX_STATUS_DESC_BC_8188F(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)\n\n/* DWORD 2 */\n#define GET_RX_STATUS_DESC_SEQ_8188F(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)\n#define GET_RX_STATUS_DESC_FRAG_8188F(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)\n#define GET_RX_STATUS_DESC_RX_IS_QOS_8188F(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)\n#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8188F(__pRxStatusDesc)\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)\n#define GET_RX_STATUS_DESC_RPT_SEL_8188F(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)\n\n/* DWORD 3 */\n#define GET_RX_STATUS_DESC_RX_RATE_8188F(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)\n#define GET_RX_STATUS_DESC_HTC_8188F(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)\n#define GET_RX_STATUS_DESC_EOSP_8188F(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)\n#define GET_RX_STATUS_DESC_BSSID_FIT_8188F(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)\n#ifdef CONFIG_USB_RX_AGGREGATION\n#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8188F(__pRxStatusDesc)\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)\n#endif\n#define GET_RX_STATUS_DESC_PATTERN_MATCH_8188F(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)\n#define GET_RX_STATUS_DESC_UNICAST_MATCH_8188F(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)\n#define GET_RX_STATUS_DESC_MAGIC_MATCH_8188F(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)\n\n/* DWORD 6 */\n#define GET_RX_STATUS_DESC_SPLCP_8188F(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)\n#define GET_RX_STATUS_DESC_LDPC_8188F(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)\n#define GET_RX_STATUS_DESC_STBC_8188F(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)\n#define GET_RX_STATUS_DESC_BW_8188F(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)\n\n/* DWORD 5 */\n#define GET_RX_STATUS_DESC_TSFL_8188F(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)\n\n#define GET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)\n#define GET_RX_STATUS_DESC_BUFF_ADDR64_8188F(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)\n\n#define SET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)\n\n\n/* Dword 0 */\n#define GET_TX_DESC_OWN_8188F(__pTxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pTxDesc, 31, 1)\n\n#define SET_TX_DESC_PKT_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)\n#define SET_TX_DESC_OFFSET_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)\n#define SET_TX_DESC_BMC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)\n#define SET_TX_DESC_HTC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)\n#define SET_TX_DESC_LAST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)\n#define SET_TX_DESC_FIRST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)\n#define SET_TX_DESC_LINIP_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)\n#define SET_TX_DESC_NO_ACM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)\n#define SET_TX_DESC_GF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)\n#define SET_TX_DESC_OWN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)\n\n/* Dword 1 */\n#define SET_TX_DESC_MACID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)\n#define SET_TX_DESC_QUEUE_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)\n#define SET_TX_DESC_RDG_NAV_EXT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)\n#define SET_TX_DESC_LSIG_TXOP_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)\n#define SET_TX_DESC_PIFS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)\n#define SET_TX_DESC_RATE_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)\n#define SET_TX_DESC_EN_DESC_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)\n#define SET_TX_DESC_SEC_TYPE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)\n#define SET_TX_DESC_PKT_OFFSET_8188F(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)\n\n\n/* Dword 2 */\n#define SET_TX_DESC_PAID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)\n#define SET_TX_DESC_CCA_RTS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)\n#define SET_TX_DESC_AGG_ENABLE_8188F(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)\n#define SET_TX_DESC_RDG_ENABLE_8188F(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)\n#define SET_TX_DESC_AGG_BREAK_8188F(__pTxDesc, __Value)\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)\n#define SET_TX_DESC_MORE_FRAG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)\n#define SET_TX_DESC_RAW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)\n#define SET_TX_DESC_SPE_RPT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)\n#define SET_TX_DESC_AMPDU_DENSITY_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)\n#define SET_TX_DESC_BT_INT_8188F(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)\n#define SET_TX_DESC_GID_8188F(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)\n\n\n/* Dword 3 */\n#define SET_TX_DESC_WHEADER_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)\n#define SET_TX_DESC_CHK_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)\n#define SET_TX_DESC_EARLY_MODE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)\n#define SET_TX_DESC_HWSEQ_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)\n#define SET_TX_DESC_USE_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)\n#define SET_TX_DESC_DISABLE_RTS_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)\n#define SET_TX_DESC_DISABLE_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)\n#define SET_TX_DESC_CTS2SELF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)\n#define SET_TX_DESC_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)\n#define SET_TX_DESC_HW_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)\n#define SET_TX_DESC_NAV_USE_HDR_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)\n#define SET_TX_DESC_USE_MAX_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)\n#define SET_TX_DESC_MAX_AGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)\n#define SET_TX_DESC_NDPA_8188F(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)\n#define SET_TX_DESC_AMPDU_MAX_TIME_8188F(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)\n\n/* Dword 4 */\n#define SET_TX_DESC_TX_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)\n#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)\n#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)\n#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)\n#define SET_TX_DESC_DATA_RETRY_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)\n#define SET_TX_DESC_RTS_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)\n\n\n/* Dword 5 */\n#define SET_TX_DESC_DATA_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)\n#define SET_TX_DESC_DATA_SHORT_8188F(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)\n#define SET_TX_DESC_DATA_BW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)\n#define SET_TX_DESC_DATA_LDPC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)\n#define SET_TX_DESC_DATA_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)\n#define SET_TX_DESC_CTROL_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)\n#define SET_TX_DESC_RTS_SHORT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)\n#define SET_TX_DESC_RTS_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)\n\n\n/* Dword 6 */\n#define SET_TX_DESC_SW_DEFINE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)\n#define SET_TX_DESC_MBSSID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)\n#define SET_TX_DESC_ANTSEL_A_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)\n#define SET_TX_DESC_ANTSEL_B_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)\n#define SET_TX_DESC_ANTSEL_C_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)\n#define SET_TX_DESC_ANTSEL_D_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)\n\n/* Dword 7 */\n#ifdef CONFIG_PCI_HCI\n#define SET_TX_DESC_TX_BUFFER_SIZE_8188F(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n#endif\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)\n#define SET_TX_DESC_TX_DESC_CHECKSUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n#endif\n#define SET_TX_DESC_USB_TXAGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)\n#ifdef CONFIG_SDIO_HCI\n#define SET_TX_DESC_SDIO_TXSEQ_8188F(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)\n#endif\n\n/* Dword 8 */\n#define SET_TX_DESC_HWSEQ_EN_8188F(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)\n\n/* Dword 9 */\n#define SET_TX_DESC_SEQ_8188F(__pTxDesc, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)\n\n/* Dword 10 */\n#define SET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)\n#define GET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc)\tLE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)\n\n/* Dword 11 */\n#define SET_TX_DESC_NEXT_DESC_ADDRESS_8188F(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)\n\n\n#define SET_EARLYMODE_PKTNUM_8188F(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)\n#define SET_EARLYMODE_LEN0_8188F(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)\n#define SET_EARLYMODE_LEN1_1_8188F(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)\n#define SET_EARLYMODE_LEN1_2_8188F(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)\n#define SET_EARLYMODE_LEN2_8188F(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,\t__Value)\n#define SET_EARLYMODE_LEN3_8188F(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)\n\n#endif\n/* -----------------------------------------------------------\n *\n *\tRate\n *\n * -----------------------------------------------------------\n * CCK Rates, TxHT = 0 */\n#define DESC8188F_RATE1M\t\t\t\t0x00\n#define DESC8188F_RATE2M\t\t\t\t0x01\n#define DESC8188F_RATE5_5M\t\t\t\t0x02\n#define DESC8188F_RATE11M\t\t\t\t0x03\n\n/* OFDM Rates, TxHT = 0 */\n#define DESC8188F_RATE6M\t\t\t\t0x04\n#define DESC8188F_RATE9M\t\t\t\t0x05\n#define DESC8188F_RATE12M\t\t\t\t0x06\n#define DESC8188F_RATE18M\t\t\t\t0x07\n#define DESC8188F_RATE24M\t\t\t\t0x08\n#define DESC8188F_RATE36M\t\t\t\t0x09\n#define DESC8188F_RATE48M\t\t\t\t0x0a\n#define DESC8188F_RATE54M\t\t\t\t0x0b\n\n/* MCS Rates, TxHT = 1 */\n#define DESC8188F_RATEMCS0\t\t\t\t0x0c\n#define DESC8188F_RATEMCS1\t\t\t\t0x0d\n#define DESC8188F_RATEMCS2\t\t\t\t0x0e\n#define DESC8188F_RATEMCS3\t\t\t\t0x0f\n#define DESC8188F_RATEMCS4\t\t\t\t0x10\n#define DESC8188F_RATEMCS5\t\t\t\t0x11\n#define DESC8188F_RATEMCS6\t\t\t\t0x12\n#define DESC8188F_RATEMCS7\t\t\t\t0x13\n#define DESC8188F_RATEMCS8\t\t\t\t0x14\n#define DESC8188F_RATEMCS9\t\t\t\t0x15\n#define DESC8188F_RATEMCS10\t\t0x16\n#define DESC8188F_RATEMCS11\t\t0x17\n#define DESC8188F_RATEMCS12\t\t0x18\n#define DESC8188F_RATEMCS13\t\t0x19\n#define DESC8188F_RATEMCS14\t\t0x1a\n#define DESC8188F_RATEMCS15\t\t0x1b\n#define DESC8188F_RATEVHTSS1MCS0\t\t0x2c\n#define DESC8188F_RATEVHTSS1MCS1\t\t0x2d\n#define DESC8188F_RATEVHTSS1MCS2\t\t0x2e\n#define DESC8188F_RATEVHTSS1MCS3\t\t0x2f\n#define DESC8188F_RATEVHTSS1MCS4\t\t0x30\n#define DESC8188F_RATEVHTSS1MCS5\t\t0x31\n#define DESC8188F_RATEVHTSS1MCS6\t\t0x32\n#define DESC8188F_RATEVHTSS1MCS7\t\t0x33\n#define DESC8188F_RATEVHTSS1MCS8\t\t0x34\n#define DESC8188F_RATEVHTSS1MCS9\t\t0x35\n#define DESC8188F_RATEVHTSS2MCS0\t\t0x36\n#define DESC8188F_RATEVHTSS2MCS1\t\t0x37\n#define DESC8188F_RATEVHTSS2MCS2\t\t0x38\n#define DESC8188F_RATEVHTSS2MCS3\t\t0x39\n#define DESC8188F_RATEVHTSS2MCS4\t\t0x3a\n#define DESC8188F_RATEVHTSS2MCS5\t\t0x3b\n#define DESC8188F_RATEVHTSS2MCS6\t\t0x3c\n#define DESC8188F_RATEVHTSS2MCS7\t\t0x3d\n#define DESC8188F_RATEVHTSS2MCS8\t\t0x3e\n#define DESC8188F_RATEVHTSS2MCS9\t\t0x3f\n\n\n#define\tRX_HAL_IS_CCK_RATE_8188F(pDesc)\\\n\t(GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE1M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE2M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE5_5M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE11M)\n\n\nvoid rtl8188f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);\nvoid rtl8188f_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);\n#if defined(CONFIG_CONCURRENT_MODE)\nvoid fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);\n#endif\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\ns32 rtl8188fs_init_xmit_priv(PADAPTER padapter);\nvoid rtl8188fs_free_xmit_priv(PADAPTER padapter);\ns32 rtl8188fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\ns32 rtl8188fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\ns32\trtl8188fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\ns32 rtl8188fs_xmit_buf_handler(PADAPTER padapter);\nthread_return rtl8188fs_xmit_thread(thread_context context);\n#define hal_xmit_handler rtl8188fs_xmit_buf_handler\n#endif\n\n#ifdef CONFIG_USB_HCI\n#ifdef CONFIG_XMIT_THREAD_MODE\ns32 rtl8188fu_xmit_buf_handler(PADAPTER padapter);\n#define hal_xmit_handler rtl8188fu_xmit_buf_handler\n#endif\n\ns32 rtl8188fu_init_xmit_priv(PADAPTER padapter);\nvoid rtl8188fu_free_xmit_priv(PADAPTER padapter);\ns32 rtl8188fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\ns32 rtl8188fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\ns32\t rtl8188fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n/* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */\nvoid rtl8188fu_xmit_tasklet(void *priv);\ns32 rtl8188fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\nvoid _dbg_dump_tx_info(_adapter\t*padapter, int frame_tag, struct tx_desc *ptxdesc);\n#endif\n\n#ifdef CONFIG_PCI_HCI\ns32 rtl8188fe_init_xmit_priv(PADAPTER padapter);\nvoid rtl8188fe_free_xmit_priv(PADAPTER padapter);\nstruct xmit_buf *rtl8188fe_dequeue_xmitbuf(struct rtw_tx_ring *ring);\nvoid\trtl8188fe_xmitframe_resume(_adapter *padapter);\ns32 rtl8188fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\ns32 rtl8188fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\ns32\trtl8188fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\nvoid rtl8188fe_xmit_tasklet(void *priv);\n#endif\n\nu8\tBWMapping_8188F(PADAPTER Adapter, struct pkt_attrib *pattrib);\nu8\tSCMapping_8188F(PADAPTER Adapter, struct pkt_attrib\t*pattrib);\n\n#endif\n"
  },
  {
    "path": "include/rtl8192e_cmd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2012 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8192E_CMD_H__\n#define __RTL8192E_CMD_H__\n\ntypedef enum _RTL8192E_H2C_CMD {\n\tH2C_8192E_RSVDPAGE\t= 0x00,\n\tH2C_8192E_MSRRPT\t= 0x01,\n\tH2C_8192E_SCAN\t\t= 0x02,\n\tH2C_8192E_KEEP_ALIVE_CTRL = 0x03,\n\tH2C_8192E_DISCONNECT_DECISION = 0x04,\n\tH2C_8192E_INIT_OFFLOAD = 0x06,\n\tH2C_8192E_AP_OFFLOAD = 0x08,\n\tH2C_8192E_BCN_RSVDPAGE = 0x09,\n\tH2C_8192E_PROBERSP_RSVDPAGE = 0x0a,\n\n\tH2C_8192E_AP_WOW_GPIO_CTRL = 0x13,\n\n\tH2C_8192E_SETPWRMODE = 0x20,\n\tH2C_8192E_PS_TUNING_PARA = 0x21,\n\tH2C_8192E_PS_TUNING_PARA2 = 0x22,\n\tH2C_8192E_PS_LPS_PARA = 0x23,\n\tH2C_8192E_P2P_PS_OFFLOAD = 0x24,\n\tH2C_8192E_SAP_PS = 0x26,\n\tH2C_8192E_RA_MASK = 0x40,\n\tH2C_8192E_RSSI_REPORT = 0x42,\n\tH2C_8192E_RA_PARA_ADJUST = 0x46,\n\n\tH2C_8192E_WO_WLAN = 0x80,\n\tH2C_8192E_REMOTE_WAKE_CTRL = 0x81,\n\tH2C_8192E_AOAC_GLOBAL_INFO = 0x82,\n\tH2C_8192E_AOAC_RSVDPAGE = 0x83,\n\n\t/* Not defined in new 88E H2C CMD Format */\n\tH2C_8192E_SELECTIVE_SUSPEND_ROF_CMD,\n\tH2C_8192E_P2P_PS_MODE,\n\tH2C_8192E_PSD_RESULT,\n\tMAX_8192E_H2CCMD\n} RTL8192E_H2C_CMD;\n\nstruct cmd_msg_parm {\n\tu8 eid; /* element id */\n\tu8 sz; /* sz */\n\tu8 buf[6];\n};\n\nenum {\n\tPWRS\n};\n\ntypedef struct _SETPWRMODE_PARM {\n\tu8 Mode;/* 0:Active,1:LPS,2:WMMPS */\n\t/* u8 RLBM:4; */ /* 0:Min,1:Max,2: User define */\n\tu8 SmartPS_RLBM;/* LPS=0:PS_Poll,1:PS_Poll,2:NullData,WMM=0:PS_Poll,1:NullData */\n\tu8 AwakeInterval;\t/* unit: beacon interval */\n\tu8 bAllQueueUAPSD;\n\tu8 PwrState;/* AllON(0x0c),RFON(0x04),RFOFF(0x00) */\n} SETPWRMODE_PARM, *PSETPWRMODE_PARM;\n\nstruct H2C_SS_RFOFF_PARAM {\n\tu8 ROFOn; /* 1: on, 0:off */\n\tu16 gpio_period; /* unit: 1024 us */\n} __attribute__((packed));\n\n\ntypedef struct JOINBSSRPT_PARM_92E {\n\tu8 OpMode;\t/* RT_MEDIA_STATUS */\n#ifdef CONFIG_WOWLAN\n\tu8 MacID;       /* MACID */\n#endif /* CONFIG_WOWLAN */\n} JOINBSSRPT_PARM_92E, *PJOINBSSRPT_PARM_92E;\n\n/* move to hal_com_h2c.h\ntypedef struct _RSVDPAGE_LOC_92E {\n\tu8 LocProbeRsp;\n\tu8 LocPsPoll;\n\tu8 LocNullData;\n\tu8 LocQosNull;\n\tu8 LocBTQosNull;\n} RSVDPAGE_LOC_92E, *PRSVDPAGE_LOC_92E;\n*/\n\n\n/* _SETPWRMODE_PARM */\n#define SET_8192E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8192E_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)\n#define SET_8192E_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)\n#define SET_8192E_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8192E_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8192E_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)\n#define SET_8192E_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n#define GET_8192E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)\t\t\t\t\t\tLE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)\n\n/* _P2P_PS_OFFLOAD */\n#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ENABLE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_CTWINDOW_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)\n#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_NOA0_EN(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)\n#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_NOA1_EN(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)\n#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)\n\n\n/* host message to firmware cmd */\nvoid rtl8192e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);\nvoid rtl8192e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);\ns32 FillH2CCmd_8192E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);\nu8 GetTxBufferRsvdPageNum8192E(_adapter *padapter, bool wowlan);\n/* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */\ns32 c2h_handler_8192e(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);\n#ifdef CONFIG_BT_COEXIST\n\tvoid rtl8192e_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);\n#endif /* CONFIG_BT_COEXIST */\n#ifdef CONFIG_P2P_PS\n\tvoid rtl8192e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_TDLS\n\t#ifdef CONFIG_TDLS_CH_SW\n\t\tvoid rtl8192e_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);\n\t#endif\n#endif\n\n/* / TX Feedback Content */\n#define\tUSEC_UNIT_FOR_8192E_C2H_TX_RPT_QUEUE_TIME\t\t\t256\n\n#define\tGET_8192E_C2H_TX_RPT_QUEUE_SELECT(_Header)\t\t\tLE_BITS_TO_1BYTE((_Header + 0), 0, 5)\n#define\tGET_8192E_C2H_TX_RPT_PKT_BROCAST(_Header)\t\t\tLE_BITS_TO_1BYTE((_Header + 0), 5, 1)\n#define\tGET_8192E_C2H_TX_RPT_LIFE_TIME_OVER(_Header)\t\t\tLE_BITS_TO_1BYTE((_Header + 0), 6, 1)\n#define\tGET_8192E_C2H_TX_RPT_RETRY_OVER(_Header)\t\t\t\tLE_BITS_TO_1BYTE((_Header + 0), 7, 1)\n#define\tGET_8192E_C2H_TX_RPT_MAC_ID(_Header)\t\t\t\t\tLE_BITS_TO_1BYTE((_Header + 1), 0, 8)\n#define\tGET_8192E_C2H_TX_RPT_DATA_RETRY_CNT(_Header)\t\tLE_BITS_TO_1BYTE((_Header + 2), 0, 6)\n#define\tGET_8192E_C2H_TX_RPT_QUEUE_TIME(_Header)\t\t\t\tLE_BITS_TO_2BYTE((_Header + 3), 0, 16)\t/* In unit of 256 microseconds. */\n#define\tGET_8192E_C2H_TX_RPT_FINAL_DATA_RATE(_Header)\t\tLE_BITS_TO_1BYTE((_Header + 5), 0, 8)\n\n#endif /* __RTL8192E_CMD_H__ */\n"
  },
  {
    "path": "include/rtl8192e_dm.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2012 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8192E_DM_H__\n#define __RTL8192E_DM_H__\n\n\nvoid rtl8192e_init_dm_priv(PADAPTER Adapter);\nvoid rtl8192e_deinit_dm_priv(PADAPTER Adapter);\nvoid rtl8192e_InitHalDm(PADAPTER Adapter);\nvoid rtl8192e_HalDmWatchDog(PADAPTER Adapter);\n\n/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */\n\n/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */\n\n#endif\n"
  },
  {
    "path": "include/rtl8192e_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2012 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8192E_HAL_H__\n#define __RTL8192E_HAL_H__\n\n/* #include \"hal_com.h\" */\n\n#include \"hal_data.h\"\n\n/* include HAL Related header after HAL Related compiling flags */\n#include \"rtl8192e_spec.h\"\n#include \"rtl8192e_rf.h\"\n#include \"rtl8192e_dm.h\"\n#include \"rtl8192e_recv.h\"\n#include \"rtl8192e_xmit.h\"\n#include \"rtl8192e_cmd.h\"\n#include \"rtl8192e_led.h\"\n#include \"Hal8192EPwrSeq.h\"\n#include \"Hal8192EPhyReg.h\"\n#include \"Hal8192EPhyCfg.h\"\n\n\n#ifdef DBG_CONFIG_ERROR_DETECT\n\t#include \"rtl8192e_sreset.h\"\n#endif\n\n/* ---------------------------------------------------------------------\n *\t\tRTL8192E Power Configuration CMDs for PCIe interface\n * --------------------------------------------------------------------- */\n#define Rtl8192E_NIC_PWR_ON_FLOW\t\t\t\trtl8192E_power_on_flow\n#define Rtl8192E_NIC_RF_OFF_FLOW\t\t\t\trtl8192E_radio_off_flow\n#define Rtl8192E_NIC_DISABLE_FLOW\t\t\t\trtl8192E_card_disable_flow\n#define Rtl8192E_NIC_ENABLE_FLOW\t\t\t\trtl8192E_card_enable_flow\n#define Rtl8192E_NIC_SUSPEND_FLOW\t\t\t\trtl8192E_suspend_flow\n#define Rtl8192E_NIC_RESUME_FLOW\t\t\t\trtl8192E_resume_flow\n#define Rtl8192E_NIC_PDN_FLOW\t\t\t\t\trtl8192E_hwpdn_flow\n#define Rtl8192E_NIC_LPS_ENTER_FLOW\t\t\trtl8192E_enter_lps_flow\n#define Rtl8192E_NIC_LPS_LEAVE_FLOW\t\t\trtl8192E_leave_lps_flow\n\n\n#if 1 /* download firmware related data structure */\n#define FW_SIZE_8192E\t\t\t0x8000 /* Compatible with RTL8192e Maximal RAM code size 32k */\n#define FW_START_ADDRESS\t\t0x1000\n#define FW_END_ADDRESS\t\t\t0x5FFF\n\n\n#define IS_FW_HEADER_EXIST_8192E(_pFwHdr)\t((GET_FIRMWARE_HDR_SIGNATURE_8192E(_pFwHdr) & 0xFFF0) == 0x92E0)\n\n\n\ntypedef struct _RT_FIRMWARE_8192E {\n\tFIRMWARE_SOURCE\teFWSource;\n#ifdef CONFIG_EMBEDDED_FWIMG\n\tu8\t\t\t*szFwBuffer;\n#else\n\tu8\t\t\tszFwBuffer[FW_SIZE_8192E];\n#endif\n\tu32\t\t\tulFwLength;\n} RT_FIRMWARE_8192E, *PRT_FIRMWARE_8192E;\n\n/*\n * This structure must be cared byte-ordering\n *\n * Added by tynli. 2009.12.04. */\n\n/* *****************************************************\n *\t\t\t\t\tFirmware Header(8-byte alinment required)\n * *****************************************************\n * --- LONG WORD 0 ---- */\n#define GET_FIRMWARE_HDR_SIGNATURE_8192E(__FwHdr)\t\tLE_BITS_TO_4BYTE(__FwHdr, 0, 16) /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */\n#define GET_FIRMWARE_HDR_CATEGORY_8192E(__FwHdr)\t\tLE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */\n#define GET_FIRMWARE_HDR_FUNCTION_8192E(__FwHdr)\t\tLE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */\n#define GET_FIRMWARE_HDR_VERSION_8192E(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */\n#define GET_FIRMWARE_HDR_SUB_VER_8192E(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */\n#define GET_FIRMWARE_HDR_RSVD1_8192E(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+4, 24, 8)\n\n/* --- LONG WORD 1 ---- */\n#define GET_FIRMWARE_HDR_MONTH_8192E(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+8, 0, 8) /* Release time Month field */\n#define GET_FIRMWARE_HDR_DATE_8192E(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+8, 8, 8) /* Release time Date field */\n#define GET_FIRMWARE_HDR_HOUR_8192E(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+8, 16, 8)/* Release time Hour field */\n#define GET_FIRMWARE_HDR_MINUTE_8192E(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+8, 24, 8)/* Release time Minute field */\n#define GET_FIRMWARE_HDR_ROMCODE_SIZE_8192E(__FwHdr)\tLE_BITS_TO_4BYTE(__FwHdr+12, 0, 16)/* The size of RAM code */\n#define GET_FIRMWARE_HDR_RSVD2_8192E(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+12, 16, 16)\n\n/* --- LONG WORD 2 ---- */\n#define GET_FIRMWARE_HDR_SVN_IDX_8192E(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+16, 0, 32)/* The SVN entry index */\n#define GET_FIRMWARE_HDR_RSVD3_8192E(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+20, 0, 32)\n\n/* --- LONG WORD 3 ---- */\n#define GET_FIRMWARE_HDR_RSVD4_8192E(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+24, 0, 32)\n#define GET_FIRMWARE_HDR_RSVD5_8192E(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+28, 0, 32)\n\n#endif /* download firmware related data structure */\n\n#define DRIVER_EARLY_INT_TIME_8192E\t\t0x05\n#define BCN_DMA_ATIME_INT_TIME_8192E\t\t0x02\n#define RX_DMA_SIZE_8192E\t\t\t\t\t0x4000\t/* 16K*/\n\n#ifdef CONFIG_WOWLAN\n\t#define RESV_FMWF\t(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/\n#else\n\t#define RESV_FMWF\t0\n#endif\n\n#ifdef CONFIG_FW_C2H_DEBUG\n\t#define RX_DMA_RESERVED_SIZE_8192E\t0x100\t/* 256B, reserved for c2h debug message*/\n#else\n\t#define RX_DMA_RESERVED_SIZE_8192E\t0x40\t/* 64B, reserved for c2h event(16bytes) or ccx(8 Bytes)*/\n#endif\n#define MAX_RX_DMA_BUFFER_SIZE_8192E\t\t(RX_DMA_SIZE_8192E-RX_DMA_RESERVED_SIZE_8192E)\t/*RX 16K*/\n\n\n#define PAGE_SIZE_TX_92E\tPAGE_SIZE_256\n\n/* For General Reserved Page Number(Beacon Queue is reserved page)\n * if (CONFIG_2BCN_EN) Beacon:4, PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1\n * Beacon: MAX_BEACON_LEN / PAGE_SIZE_TX_92E\n * PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1,CTS-2-SELF / LTE QoS Null*/\n\n#define RSVD_PAGE_NUM_8192E\t\t(MAX_BEACON_LEN / PAGE_SIZE_TX_92E + 6) /*0x08*/\n/* For WoWLan , more reserved page\n * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6\n * NS offload: 2 NDP info: 1\n */\n#ifdef CONFIG_WOWLAN\n\t#define WOWLAN_PAGE_NUM_8192E\t0x0b\n#else\n\t#define WOWLAN_PAGE_NUM_8192E\t0x00\n#endif\n\n#ifdef CONFIG_PNO_SUPPORT\n\t#undef WOWLAN_PAGE_NUM_8192E\n\t#define WOWLAN_PAGE_NUM_8192E\t0x0d\n#endif\n\n/* Note:\nTx FIFO Size : 64KB\nTx page Size : 256B\nTotal page numbers : 256(0x100)\n*/\n\n#define\tTOTAL_RSVD_PAGE_NUMBER_8192E\t(RSVD_PAGE_NUM_8192E + WOWLAN_PAGE_NUM_8192E)\n\n#define\tTOTAL_PAGE_NUMBER_8192E\t(0x100)\n#define\tTX_TOTAL_PAGE_NUMBER_8192E\t(TOTAL_PAGE_NUMBER_8192E - TOTAL_RSVD_PAGE_NUMBER_8192E)\n\n#define\tTX_PAGE_BOUNDARY_8192E\t(TX_TOTAL_PAGE_NUMBER_8192E) /* beacon header start address */\n\n\n#define RSVD_PKT_LEN_92E\t(TOTAL_RSVD_PAGE_NUMBER_8192E * PAGE_SIZE_TX_92E)\n\n#define TX_PAGE_LOAD_FW_BOUNDARY_8192E\t\t0x47 /* 0xA5 */\n#define TX_PAGE_BOUNDARY_WOWLAN_8192E\t\t0xE0\n\n/* For Normal Chip Setting\n * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_92C */\n\n#define NORMAL_PAGE_NUM_HPQ_8192E\t\t\t0x10\n#define NORMAL_PAGE_NUM_LPQ_8192E\t\t\t0x10\n#define NORMAL_PAGE_NUM_NPQ_8192E\t\t\t0x10\n#define NORMAL_PAGE_NUM_EPQ_8192E\t\t\t0x00\n\n\n/* Note: For WMM Normal Chip Setting ,modify later */\n#define WMM_NORMAL_PAGE_NUM_HPQ_8192E\t\tNORMAL_PAGE_NUM_HPQ_8192E\n#define WMM_NORMAL_PAGE_NUM_LPQ_8192E\t\tNORMAL_PAGE_NUM_LPQ_8192E\n#define WMM_NORMAL_PAGE_NUM_NPQ_8192E\t\tNORMAL_PAGE_NUM_NPQ_8192E\n\n\n/* -------------------------------------------------------------------------\n *\tChip specific\n * ------------------------------------------------------------------------- */\n\n/* pic buffer descriptor */\n#define RTL8192EE_SEG_NUM\t\t\tTX_BUFFER_SEG_NUM\n#define TX_DESC_NUM_92E\t\t\t128\n#define RX_DESC_NUM_92E\t\t\t128\n\n/* -------------------------------------------------------------------------\n *\tChannel Plan\n * ------------------------------------------------------------------------- */\n\n#define\t\tHWSET_MAX_SIZE_8192E\t\t\t512\n\n#define\t\tEFUSE_REAL_CONTENT_LEN_8192E\t512\n\n#define\t\tEFUSE_MAP_LEN_8192E\t\t\t512\n#define\t\tEFUSE_MAX_SECTION_8192E\t\t64\n#define\t\tEFUSE_MAX_WORD_UNIT_8192E\t\t4\n#define\t\tEFUSE_IC_ID_OFFSET_8192E\t\t506\t/* For some inferiority IC purpose. added by Roger, 2009.09.02. */\n#define\t\tAVAILABLE_EFUSE_ADDR_8192E(addr)\t(addr < EFUSE_REAL_CONTENT_LEN_8192E)\n/*\n * <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section\n * 9bytes + 1byt + 5bytes and pre 1byte.\n * For worst case:\n * | 1byte|----8bytes----|1byte|--5bytes--|\n * |         |            Reserved(14bytes)\t      |\n *   */\n#define\t\tEFUSE_OOB_PROTECT_BYTES_8192E \t\t15\t/* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */\n\n\n\n/* ********************************************************\n *\t\t\tEFUSE for BT definition\n * ******************************************************** */\n#define\t\tEFUSE_BT_REAL_BANK_CONTENT_LEN_8192E\t512\n#define\t\tEFUSE_BT_REAL_CONTENT_LEN_8192E\t\t\t1024\t/* 512*2 */\n#define\t\tEFUSE_BT_MAP_LEN_8192E\t\t\t\t\t1024\t/* 1k bytes */\n#define\t\tEFUSE_BT_MAX_SECTION_8192E\t\t\t\t128\t\t/* 1024/8 */\n\n#define\t\tEFUSE_PROTECT_BYTES_BANK_8192E\t\t\t16\n#define\t\tEFUSE_MAX_BANK_8192E\t\t\t\t\t3\n/* *********************************************************** */\n\n#define INCLUDE_MULTI_FUNC_BT(_Adapter)\t(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)\n#define INCLUDE_MULTI_FUNC_GPS(_Adapter)\t(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)\n\n/* #define IS_MULTI_FUNC_CHIP(_Adapter)\t(((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */\n\n/* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */\n\n/* rtl8812_hal_init.c */\nvoid\t_8051Reset8192E(PADAPTER padapter);\ns32\tFirmwareDownload8192E(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw);\nvoid\tInitializeFirmwareVars8192E(PADAPTER padapter);\n\ns32\tInitLLTTable8192E(PADAPTER padapter, u8 txpktbuf_bndy);\n\n/* EFuse */\nu8\tGetEEPROMSize8192E(PADAPTER padapter);\nvoid\thal_InitPGData_8192E(PADAPTER padapter, u8 *PROMContent);\nvoid\tHal_EfuseParseIDCode8192E(PADAPTER padapter, u8 *hwinfo);\nvoid\tHal_ReadPROMVersion8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid\tHal_ReadPowerSavingMode8192E(PADAPTER padapter, u8\t*hwinfo, BOOLEAN\tAutoLoadFail);\nvoid\tHal_ReadTxPowerInfo8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN\tAutoLoadFail);\nvoid\tHal_ReadBoardType8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid\tHal_ReadThermalMeter_8192E(PADAPTER\tAdapter, u8 *PROMContent, BOOLEAN\tAutoloadFail);\nvoid\tHal_ReadChannelPlan8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid\tHal_EfuseParseXtal_8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid\tHal_ReadAntennaDiversity8192E(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);\nvoid\tHal_ReadPAType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);\nvoid\tHal_ReadAmplifierType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);\nvoid\tHal_ReadRFEType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);\nvoid\tHal_EfuseParseBTCoexistInfo8192E(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid\tHal_EfuseParseKFreeData_8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\n\nu8 Hal_CrystalAFEAdjust(_adapter *Adapter);\n\nBOOLEAN HalDetectPwrDownMode8192E(PADAPTER Adapter);\n\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\n\tvoid Hal_DetectWoWMode(PADAPTER pAdapter);\n#endif /* CONFIG_WOWLAN */\n\n/***********************************************************/\n/* RTL8192E-MAC Setting */\nvoid _InitQueueReservedPage_8192E(PADAPTER Adapter);\nvoid _InitQueuePriority_8192E(PADAPTER Adapter);\nvoid _InitTxBufferBoundary_8192E(PADAPTER Adapter, u8 txpktbuf_bndy);\nvoid _InitPageBoundary_8192E(PADAPTER Adapter);\n/* void _InitTransferPageSize_8192E(PADAPTER Adapter); */\nvoid _InitDriverInfoSize_8192E(PADAPTER Adapter, u8 drvInfoSize);\nvoid _InitRDGSetting_8192E(PADAPTER Adapter);\nvoid _InitID_8192E(PADAPTER Adapter);\nvoid _InitNetworkType_8192E(PADAPTER Adapter);\nvoid _InitWMACSetting_8192E(PADAPTER Adapter);\nvoid _InitAdaptiveCtrl_8192E(PADAPTER Adapter);\nvoid _InitEDCA_8192E(PADAPTER Adapter);\nvoid _InitRetryFunction_8192E(PADAPTER Adapter);\nvoid _BBTurnOnBlock_8192E(PADAPTER Adapter);\nvoid _InitBeaconParameters_8192E(PADAPTER Adapter);\nvoid _InitBeaconMaxError_8192E(\n\t\tPADAPTER\tAdapter,\n\t\tBOOLEAN\t\tInfraMode\n);\nvoid SetBeaconRelatedRegisters8192E(PADAPTER padapter);\nvoid hal_ReadRFType_8192E(PADAPTER\tAdapter);\n/* RTL8192E-MAC Setting\n ***********************************************************/\n\nu8 SetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val);\nvoid GetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val);\nu8\nSetHalDefVar8192E(\n\t\tPADAPTER\t\t\t\tAdapter,\n\t\tHAL_DEF_VARIABLE\t\teVariable,\n\t\tvoid\t\t\t\t\t\t*pValue\n);\nu8\nGetHalDefVar8192E(\n\t\tPADAPTER\t\t\t\tAdapter,\n\t\tHAL_DEF_VARIABLE\t\teVariable,\n\t\tvoid\t\t\t\t\t\t*pValue\n);\n\nvoid rtl8192e_set_hal_ops(struct hal_ops *pHalFunc);\nvoid init_hal_spec_8192e(_adapter *adapter);\nvoid rtl8192e_init_default_value(_adapter *padapter);\n\nvoid rtl8192e_start_thread(_adapter *padapter);\nvoid rtl8192e_stop_thread(_adapter *padapter);\n\n#ifdef CONFIG_PCI_HCI\n\tBOOLEAN\tInterruptRecognized8192EE(PADAPTER Adapter);\n\tu16\tget_txbd_rw_reg(u16 ff_hwaddr);\n#endif\n\n#ifdef CONFIG_SDIO_HCI\n\t#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT\n\t\tvoid _init_available_page_threshold(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ);\n\t#endif\n#endif\n\n#ifdef CONFIG_BT_COEXIST\n\tvoid rtl8192e_combo_card_WifiOnlyHwInit(PADAPTER Adapter);\n#endif\n\n#endif /* __RTL8192E_HAL_H__ */\n"
  },
  {
    "path": "include/rtl8192e_led.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2012 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8192E_LED_H__\n#define __RTL8192E_LED_H__\n\n#ifdef CONFIG_RTW_SW_LED\n/* ********************************************************************************\n * Interface to manipulate LED objects.\n * ******************************************************************************** */\n#ifdef CONFIG_USB_HCI\n\tvoid rtl8192eu_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8192eu_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_PCI_HCI\n\tvoid rtl8192ee_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8192ee_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_SDIO_HCI\n\tvoid rtl8192es_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8192es_DeInitSwLeds(PADAPTER padapter);\n#endif\n\n#endif\n#endif/*CONFIG_RTW_SW_LED*/\n"
  },
  {
    "path": "include/rtl8192e_recv.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2012 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8192E_RECV_H__\n#define __RTL8192E_RECV_H__\n\n#if defined(CONFIG_USB_HCI)\n\n\t#ifndef MAX_RECVBUF_SZ\n\t\t#ifdef CONFIG_MINIMAL_MEMORY_USAGE\n\t\t\t#define MAX_RECVBUF_SZ (4000) /* about 4K */\n\t\t#else\n\t\t\t#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER\n\t\t\t\t#define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/\n\t\t\t#elif defined(CONFIG_PLATFORM_HISILICON)\n\t\t\t\t#define MAX_RECVBUF_SZ (16384) /* 16k */\n\t\t\t#else\n\t\t\t\t#define MAX_RECVBUF_SZ (32768) /* 32k */\n\t\t\t#endif\n\t\t\t/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */\n\t\t\t/* #define MAX_RECVBUF_SZ (10240)  */ /* 10K */\n\t\t\t/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */\n\t\t\t/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k\t\t */\n\t\t\t#ifdef CONFIG_PLATFORM_NOVATEK_NT72668\n\t\t\t\t#undef MAX_RECVBUF_SZ\n\t\t\t\t#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */\n\t\t\t#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */\n\t\t#endif\n\t#endif /* !MAX_RECVBUF_SZ */\n\n#elif defined(CONFIG_PCI_HCI)\n\t/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */\n\t/*\t#define MAX_RECVBUF_SZ (9100) */\n\t/* #else */\n\t#define MAX_RECVBUF_SZ (4000) /* about 4K\n\t* #endif */\n\n\n#elif defined(CONFIG_SDIO_HCI)\n\n\t#define MAX_RECVBUF_SZ (16384)\n\n#endif\n\n\n/* Rx smooth factor */\n#define Rx_Smooth_Factor (20)\n\n/* *************\n * [1] Rx Buffer Descriptor (for PCIE) buffer descriptor architecture\n * DWORD 0 */\n#define SET_RX_BUFFER_DESC_DATA_LENGTH_92E(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)\n#define SET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)\n#define SET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)\n#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_92E(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)\n\n#define GET_RX_BUFFER_DESC_OWN_92E(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)\n#define GET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)\n#define GET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)\n#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_92E(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)\n\n\n/* DWORD 1 */\n#define SET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)\n#define GET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 32)\n\n/* DWORD 2 */\n#define SET_RX_BUFFER_PHYSICAL_HIGH_92E(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)\n\n/* *************\n * [2] Rx Descriptor\n * DWORD 0 */\n#define GET_RX_STATUS_DESC_PKT_LEN_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)\n#define GET_RX_STATUS_DESC_CRC32_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)\n#define GET_RX_STATUS_DESC_ICVERR_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)\n#define GET_RX_STATUS_DESC_DRVINFO_SIZE_92E(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)\n#define GET_RX_STATUS_DESC_SECURITY_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)\n#define GET_RX_STATUS_DESC_QOS_92E(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)\n#define GET_RX_STATUS_DESC_SHIFT_92E(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)\n#define GET_RX_STATUS_DESC_PHY_STATUS_92E(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)\n#define GET_RX_STATUS_DESC_SWDEC_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)\n#define GET_RX_STATUS_DESC_EOR_92E(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)\n#define GET_RX_STATUS_DESC_OWN_92E(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)\n\n\n#define SET_RX_STATUS_DESC_PKT_LEN_92E(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)\n#define SET_RX_STATUS_DESC_EOR_92E(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)\n#define SET_RX_STATUS_DESC_OWN_92E(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)\n\n/* DWORD 1 */\n#define GET_RX_STATUS_DESC_MACID_92E(__pRxDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)\n#define GET_RX_STATUS_DESC_TID_92E(__pRxDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)\n#define GET_RX_STATUS_DESC_MACID_VLD_92E(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 12, 1)\n#define GET_RX_STATUS_DESC_AMSDU_92E(__pRxDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)\n#define GET_RX_STATUS_DESC_RXID_MATCH_92E(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)\n#define GET_RX_STATUS_DESC_PAGGR_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 15, 1)\n#define GET_RX_STATUS_DESC_A1_FITS_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 16, 4)\n#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHKERR_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 20, 1)\n#define GET_RX_STATUS_DESC_TCPOFFLOAD_IPVER_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 21, 1)\n#define GET_RX_STATUS_DESC_TCPOFFLOAD_IS_TCPUDP_92E(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 22, 1)\n#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHK_VLD_92E(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 23, 1)\n#define GET_RX_STATUS_DESC_PAM_92E(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 24, 1)\n#define GET_RX_STATUS_DESC_PWR_92E(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 25, 1)\n#define GET_RX_STATUS_DESC_MORE_DATA_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 26, 1)\n#define GET_RX_STATUS_DESC_MORE_FRAG_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 27, 1)\n#define GET_RX_STATUS_DESC_TYPE_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 28, 2)\n#define GET_RX_STATUS_DESC_MC_92E(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 30, 1)\n#define GET_RX_STATUS_DESC_BC_92E(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 31, 1)\n\n/* DWORD 2 */\n#define GET_RX_STATUS_DESC_SEQ_92E(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)\n#define GET_RX_STATUS_DESC_FRAG_92E(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)\n#define GET_RX_STATUS_DESC_RX_IS_QOS_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)\n\n#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)\n#define GET_RX_STATUS_DESC_HWRSVD_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 24, 4)\n#define GET_RX_STATUS_DESC_FCS_OK_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)\n#define GET_RX_STATUS_DESC_RPT_SEL_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)\n\n/* DWORD 3 */\n#define GET_RX_STATUS_DESC_RX_RATE_92E(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)\n#define GET_RX_STATUS_DESC_HTC_92E(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)\n#define GET_RX_STATUS_DESC_EOSP_92E(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)\n#define GET_RX_STATUS_DESC_BSSID_FIT_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)\n#define GET_RX_STATUS_DESC_DMA_AGG_NUM_92E(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)\n\n#define GET_RX_STATUS_DESC_PATTERN_MATCH_92E(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)\n#define GET_RX_STATUS_DESC_UNICAST_92E(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)\n#define GET_RX_STATUS_DESC_MAGIC_WAKE_92E(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)\n\n/* DWORD 6 */\n#define GET_RX_STATUS_DESC_SPLCP_92E(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)\n#define GET_RX_STATUS_DESC_LDPC_92E(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)\n#define GET_RX_STATUS_DESC_STBC_92E(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)\n#define GET_RX_STATUS_DESC_BW_92E(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)\n\n\n/* DWORD 5 */\n#define GET_RX_STATUS_DESC_TSFL_92E(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)\n\n#define GET_RX_STATUS_DESC_BUFF_ADDR_92E(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)\n#define GET_RX_STATUS_DESC_BUFF_ADDR64_92E(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)\n\n\n#ifdef CONFIG_SDIO_HCI\n\ts32 rtl8192es_init_recv_priv(PADAPTER padapter);\n\tvoid rtl8192es_free_recv_priv(PADAPTER padapter);\n\ts32 rtl8192es_recv_hdl(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_USB_HCI\n\tvoid rtl8192eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);\n\ts32 rtl8192eu_init_recv_priv(PADAPTER padapter);\n\tvoid rtl8192eu_free_recv_priv(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\ts32 rtl8192ee_init_recv_priv(PADAPTER padapter);\n\tvoid rtl8192ee_free_recv_priv(PADAPTER padapter);\n#endif\n\nvoid rtl8192e_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);\n\n#endif /* __RTL8192E_RECV_H__ */\n"
  },
  {
    "path": "include/rtl8192e_rf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2012 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8192E_RF_H__\n#define __RTL8192E_RF_H__\n\nvoid\nPHY_RF6052SetBandwidth8192E(\n\t\tPADAPTER\t\t\t\tAdapter,\n\t\tenum channel_width\t\tBandwidth);\n\n\nint\nPHY_RF6052_Config_8192E(\n\t\tPADAPTER\tAdapter);\n\n#endif/* __RTL8192E_RF_H__ */\n"
  },
  {
    "path": "include/rtl8192e_spec.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2012 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8192E_SPEC_H__\n#define __RTL8192E_SPEC_H__\n\n#include <drv_conf.h>\n\n#define HAL_NAV_UPPER_UNIT_8192E\t\t128\t\t/* micro-second */\n\n/* ************************************************************\n * 8192E Regsiter offset definition\n * ************************************************************ */\n\n/* ************************************************************\n *\n * ************************************************************ */\n\n/* -----------------------------------------------------\n *\n *\t0x0000h ~ 0x00FFh\tSystem Configuration\n *\n * ----------------------------------------------------- */\n#define REG_SYS_SWR_CTRL1_8192E\t\t0x0010\t/* 1 Byte        */\n#define REG_SYS_SWR_CTRL2_8192E\t\t0x0014\t/* 1 Byte      */\n#define REG_AFE_CTRL1_8192E\t\t\t0x0024\n#define REG_AFE_CTRL2_8192E\t\t\t0x0028\n#define REG_AFE_CTRL3_8192E\t\t\t0x002c\n\n#define REG_PAD_CTRL1_8192E\t\t\t0x0064\n#define REG_SDIO_CTRL_8192E\t\t\t0x0070\n#define REG_OPT_CTRL_8192E\t\t\t\t0x0074\n#define REG_RF_B_CTRL_8192E\t\t\t0x0076\n#define REG_AFE_CTRL4_8192E\t\t\t0x0078\n#define REG_LDO_SWR_CTRL\t\t\t\t0x007C\n#define REG_FW_DRV_MSG_8192E\t\t\t0x0088\n#define REG_HMEBOX_E2_E3_8192E\t\t0x008C\n#define REG_HIMR0_8192E\t\t\t\t0x00B0\n#define REG_HISR0_8192E\t\t\t\t\t0x00B4\n#define REG_HIMR1_8192E\t\t\t\t\t0x00B8\n#define REG_HISR1_8192E\t\t\t\t\t0x00BC\n\n#define REG_SYS_CFG1_8192E\t\t\t\t0x00F0\n#define REG_SYS_CFG2_8192E\t\t\t\t0x00FC\n/* -----------------------------------------------------\n *\n *\t0x0100h ~ 0x01FFh\tMACTOP General Configuration\n *\n * ----------------------------------------------------- */\n#define REG_PKTBUF_DBG_ADDR\t\t\t(REG_PKTBUF_DBG_CTRL)\n#define REG_RXPKTBUF_DBG\t\t\t\t(REG_PKTBUF_DBG_CTRL+2)\n#define REG_TXPKTBUF_DBG\t\t\t\t(REG_PKTBUF_DBG_CTRL+3)\n#define REG_WOWLAN_WAKE_REASON\t\tREG_MCUTST_WOWLAN\n\n#define REG_RSVD3_8192E\t\t\t\t\t0x0168\n#define REG_C2HEVT_CMD_SEQ_88XX\t\t0x01A1\n#define REG_C2hEVT_CMD_CONTENT_88XX\t0x01A2\n#define REG_C2HEVT_CMD_LEN_88XX\t\t0x01AE\n\n#define REG_HMEBOX_EXT0_8192E\t\t\t0x01F0\n#define REG_HMEBOX_EXT1_8192E\t\t\t0x01F4\n#define REG_HMEBOX_EXT2_8192E\t\t\t0x01F8\n#define REG_HMEBOX_EXT3_8192E\t\t\t0x01FC\n\n/* -----------------------------------------------------\n *\n *\t0x0200h ~ 0x027Fh\tTXDMA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_DWBCN0_CTRL             0x0208\n#define REG_DWBCN1_CTRL             0x0228\n\n/* -----------------------------------------------------\n *\n *\t0x0280h ~ 0x02FFh\tRXDMA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_RXDMA_8192E\t\t\t\t\t0x0290\n#define REG_EARLY_MODE_CONTROL_8192E\t\t0x02BC\n\n#define REG_RSVD5_8192E\t\t\t\t\t0x02F0\n#define REG_RSVD6_8192E\t\t\t\t\t0x02F4\n#define REG_RSVD7_8192E\t\t\t\t\t0x02F8\n#define REG_RSVD8_8192E\t\t\t\t\t0x02FC\n\n/* -----------------------------------------------------\n *\n *\t0x0300h ~ 0x03FFh\tPCIe\n *\n * ----------------------------------------------------- */\n#define\tREG_PCIE_CTRL_REG_8192E\t\t\t0x0300\n#define\tREG_INT_MIG_8192E\t\t\t\t\t0x0304\t/* Interrupt Migration */\n#define\tREG_BCNQ_TXBD_DESA_8192E\t\t0x0308\t/* TX Beacon Descriptor Address */\n#define\tREG_MGQ_TXBD_DESA_8192E\t\t\t0x0310\t/* TX Manage Queue Descriptor Address */\n#define\tREG_VOQ_TXBD_DESA_8192E\t\t\t0x0318\t/* TX VO Queue Descriptor Address */\n#define\tREG_VIQ_TXBD_DESA_8192E\t\t\t0x0320\t/* TX VI Queue Descriptor Address */\n#define\tREG_BEQ_TXBD_DESA_8192E\t\t\t0x0328\t/* TX BE Queue Descriptor Address */\n#define\tREG_BKQ_TXBD_DESA_8192E\t\t\t0x0330\t/* TX BK Queue Descriptor Address */\n#define\tREG_RXQ_RXBD_DESA_8192E\t\t\t0x0338\t/* RX Queue\tDescriptor Address */\n#define\tREG_HI0Q_TXBD_DESA_8192E\t\t\t0x0340\n#define\tREG_HI1Q_TXBD_DESA_8192E\t\t\t0x0348\n#define\tREG_HI2Q_TXBD_DESA_8192E\t\t\t0x0350\n#define\tREG_HI3Q_TXBD_DESA_8192E\t\t\t0x0358\n#define\tREG_HI4Q_TXBD_DESA_8192E\t\t\t0x0360\n#define\tREG_HI5Q_TXBD_DESA_8192E\t\t\t0x0368\n#define\tREG_HI6Q_TXBD_DESA_8192E\t\t\t0x0370\n#define\tREG_HI7Q_TXBD_DESA_8192E\t\t\t0x0378\n#define\tREG_MGQ_TXBD_NUM_8192E\t\t\t0x0380\n#define\tREG_RX_RXBD_NUM_8192E\t\t\t0x0382\n#define\tREG_VOQ_TXBD_NUM_8192E\t\t\t0x0384\n#define\tREG_VIQ_TXBD_NUM_8192E\t\t\t0x0386\n#define\tREG_BEQ_TXBD_NUM_8192E\t\t\t0x0388\n#define\tREG_BKQ_TXBD_NUM_8192E\t\t\t0x038A\n#define\tREG_HI0Q_TXBD_NUM_8192E\t\t\t0x038C\n#define\tREG_HI1Q_TXBD_NUM_8192E\t\t\t0x038E\n#define\tREG_HI2Q_TXBD_NUM_8192E\t\t\t0x0390\n#define\tREG_HI3Q_TXBD_NUM_8192E\t\t\t0x0392\n#define\tREG_HI4Q_TXBD_NUM_8192E\t\t\t0x0394\n#define\tREG_HI5Q_TXBD_NUM_8192E\t\t\t0x0396\n#define\tREG_HI6Q_TXBD_NUM_8192E\t\t\t0x0398\n#define\tREG_HI7Q_TXBD_NUM_8192E\t\t\t0x039A\n#define\tREG_TSFTIMER_HCI_8192E\t\t\t0x039C\n\n/* Read Write Point */\n#define\tREG_VOQ_TXBD_IDX_8192E\t\t\t0x03A0\n#define\tREG_VIQ_TXBD_IDX_8192E\t\t\t0x03A4\n#define\tREG_BEQ_TXBD_IDX_8192E\t\t\t0x03A8\n#define\tREG_BKQ_TXBD_IDX_8192E\t\t\t0x03AC\n#define\tREG_MGQ_TXBD_IDX_8192E\t\t\t0x03B0\n#define\tREG_RXQ_TXBD_IDX_8192E\t\t\t0x03B4\n#define\tREG_HI0Q_TXBD_IDX_8192E\t\t\t0x03B8\n#define\tREG_HI1Q_TXBD_IDX_8192E\t\t\t0x03BC\n#define\tREG_HI2Q_TXBD_IDX_8192E\t\t\t0x03C0\n#define\tREG_HI3Q_TXBD_IDX_8192E\t\t\t0x03C4\n#define\tREG_HI4Q_TXBD_IDX_8192E\t\t\t0x03C8\n#define\tREG_HI5Q_TXBD_IDX_8192E\t\t\t0x03CC\n#define\tREG_HI6Q_TXBD_IDX_8192E\t\t\t0x03D0\n#define\tREG_HI7Q_TXBD_IDX_8192E\t\t\t0x03D4\n\n#define\tREG_PCIE_HCPWM_8192EE\t\t\t0x03D8 /* ?????? */\n#define\tREG_PCIE_HRPWM_8192EE\t\t\t0x03DC\t/* PCIe RPWM */ /* ?????? */\n#define\tREG_DBI_WDATA_V1_8192E\t\t\t0x03E8\n#define\tREG_DBI_RDATA_V1_8192E\t\t\t0x03EC\n#define\tREG_DBI_FLAG_V1_8192E\t\t\t\t0x03F0\n#define\tREG_MDIO_V1_8192E\t\t\t\t\t0x3F4\n#define\tREG_PCIE_MIX_CFG_8192E\t\t\t\t0x3F8\n\n/* -----------------------------------------------------\n *\n *\t0x0400h ~ 0x047Fh\tProtocol Configuration\n *\n * ----------------------------------------------------- */\n#define REG_TXBF_CTRL_8192E\t\t\t\t0x042C\n#define REG_ARFR0_8192E\t\t\t\t\t0x0444\n#define REG_ARFR1_8192E\t\t\t\t\t0x044C\n#define REG_CCK_CHECK_8192E\t\t\t\t0x0454\n#define REG_AMPDU_MAX_TIME_8192E\t\t\t0x0456\n#define REG_BCNQ1_BDNY_8192E\t\t\t\t0x0457\n\n#define REG_AMPDU_MAX_LENGTH_8192E\t0x0458\n#define REG_WMAC_LBK_BUF_HD_8192E\t\t\t0x045D\n#define REG_NDPA_OPT_CTRL_8192E\t\t0x045F\n#define REG_DATA_SC_8192E\t\t\t\t0x0483\n#ifdef CONFIG_WOWLAN\n\t#define REG_TXPKTBUF_IV_LOW             0x0484\n\t#define REG_TXPKTBUF_IV_HIGH            0x0488\n#endif\n#define REG_ARFR2_8192E\t\t\t\t\t0x048C\n#define REG_ARFR3_8192E\t\t\t\t\t0x0494\n#define REG_TXRPT_START_OFFSET\t\t\t0x04AC\n#define REG_AMPDU_BURST_MODE_8192E\t0x04BC\n#define REG_HT_SINGLE_AMPDU_8192E\t\t0x04C7\n#define REG_MACID_PKT_DROP0_8192E\t\t0x04D0\n\n/* -----------------------------------------------------\n *\n *\t0x0500h ~ 0x05FFh\tEDCA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_CTWND_8192E\t\t\t\t\t0x0572\n#define REG_SECONDARY_CCA_CTRL_8192E\t0x0577\n#define REG_SCH_TXCMD_8192E\t\t\t0x05F8\n\n/* -----------------------------------------------------\n *\n *\t0x0600h ~ 0x07FFh\tWMAC Configuration\n *\n * ----------------------------------------------------- */\n#define REG_MAC_CR_8192E\t\t\t\t0x0600\n\n#define REG_MAC_TX_SM_STATE_8192E\t\t0x06B4\n\n/* Power */\n#define REG_BFMER0_INFO_8192E\t\t\t0x06E4\n#define REG_BFMER1_INFO_8192E\t\t\t0x06EC\n#define REG_CSI_RPT_PARAM_BW20_8192E\t0x06F4\n#define REG_CSI_RPT_PARAM_BW40_8192E\t0x06F8\n#define REG_CSI_RPT_PARAM_BW80_8192E\t0x06FC\n\n/* Hardware Port 2 */\n#define REG_BFMEE_SEL_8192E\t\t\t\t0x0714\n#define REG_SND_PTCL_CTRL_8192E\t\t0x0718\n\n\n/* -----------------------------------------------------\n *\n *\tRedifine register definition for compatibility\n *\n * ----------------------------------------------------- */\n\n/* TODO: use these definition when using REG_xxx naming rule.\n * NOTE: DO NOT Remove these definition. Use later. */\n#define\tISR_8192E\t\t\t\t\t\t\tREG_HISR0_8192E\n\n/* ----------------------------------------------------------------------------\n * 8192E IMR/ISR bits\t\t\t\t\t\t(offset 0xB0,  8bits)\n * ---------------------------------------------------------------------------- */\n#define\tIMR_DISABLED_8192E\t\t\t\t\t0\n/* IMR DW0(0x00B0-00B3) Bit 0-31 */\n#define\tIMR_TIMER2_8192E\t\t\t\t\tBIT(31)\t\t/* Timeout interrupt 2 */\n#define\tIMR_TIMER1_8192E\t\t\t\t\tBIT(30)\t\t/* Timeout interrupt 1\t */\n#define\tIMR_PSTIMEOUT_8192E\t\t\t\tBIT(29)\t\t/* Power Save Time Out Interrupt */\n#define\tIMR_GTINT4_8192E\t\t\t\t\tBIT(28)\t\t/* When GTIMER4 expires, this bit is set to 1\t */\n#define\tIMR_GTINT3_8192E\t\t\t\t\tBIT(27)\t\t/* When GTIMER3 expires, this bit is set to 1\t */\n#define\tIMR_TXBCN0ERR_8192E\t\t\t\tBIT(26)\t\t/* Transmit Beacon0 Error\t\t\t */\n#define\tIMR_TXBCN0OK_8192E\t\t\t\t\tBIT(25)\t\t/* Transmit Beacon0 OK\t\t\t */\n#define\tIMR_TSF_BIT32_TOGGLE_8192E\t\tBIT(24)\t\t/* TSF Timer BIT(32) toggle indication interrupt\t\t\t */\n#define\tIMR_BCNDMAINT0_8192E\t\t\t\tBIT(20)\t\t/* Beacon DMA Interrupt 0\t\t\t */\n#define\tIMR_BCNDERR0_8192E\t\t\t\t\tBIT(16)\t\t/* Beacon Queue DMA OK0\t\t\t */\n#define\tIMR_HSISR_IND_ON_INT_8192E\t\tBIT(15)\t\t/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */\n#define\tIMR_BCNDMAINT_E_8192E\t\t\t\tBIT(14)\t\t/* Beacon DMA Interrupt Extension for Win7\t\t\t */\n#define\tIMR_ATIMEND_8192E\t\t\t\t\tBIT(12)\t\t/* CTWidnow End or ATIM Window End */\n#define\tIMR_C2HCMD_8192E\t\t\t\t\tBIT(10)\t\t/* CPU to Host Command INT Status, Write 1 clear\t */\n#define\tIMR_CPWM2_8192E\t\t\t\t\tBIT(9)\t\t\t/* CPU power Mode exchange INT Status, Write 1 clear\t */\n#define\tIMR_CPWM_8192E\t\t\t\t\t\tBIT(8)\t\t\t/* CPU power Mode exchange INT Status, Write 1 clear\t */\n#define\tIMR_HIGHDOK_8192E\t\t\t\t\tBIT(7)\t\t\t/* High Queue DMA OK\t */\n#define\tIMR_MGNTDOK_8192E\t\t\t\t\tBIT(6)\t\t\t/* Management Queue DMA OK\t */\n#define\tIMR_BKDOK_8192E\t\t\t\t\tBIT(5)\t\t\t/* AC_BK DMA OK\t\t */\n#define\tIMR_BEDOK_8192E\t\t\t\t\tBIT(4)\t\t\t/* AC_BE DMA OK\t */\n#define\tIMR_VIDOK_8192E\t\t\t\t\tBIT(3)\t\t\t/* AC_VI DMA OK\t\t */\n#define\tIMR_VODOK_8192E\t\t\t\t\tBIT(2)\t\t\t/* AC_VO DMA OK\t */\n#define\tIMR_RDU_8192E\t\t\t\t\t\tBIT(1)\t\t\t/* Rx Descriptor Unavailable\t */\n#define\tIMR_ROK_8192E\t\t\t\t\t\tBIT(0)\t\t\t/* Receive DMA OK */\n\n/* IMR DW1(0x00B4-00B7) Bit 0-31 */\n#define\tIMR_BCNDMAINT7_8192E\t\t\t\tBIT(27)\t\t/* Beacon DMA Interrupt 7 */\n#define\tIMR_BCNDMAINT6_8192E\t\t\t\tBIT(26)\t\t/* Beacon DMA Interrupt 6 */\n#define\tIMR_BCNDMAINT5_8192E\t\t\t\tBIT(25)\t\t/* Beacon DMA Interrupt 5 */\n#define\tIMR_BCNDMAINT4_8192E\t\t\t\tBIT(24)\t\t/* Beacon DMA Interrupt 4 */\n#define\tIMR_BCNDMAINT3_8192E\t\t\t\tBIT(23)\t\t/* Beacon DMA Interrupt 3 */\n#define\tIMR_BCNDMAINT2_8192E\t\t\t\tBIT(22)\t\t/* Beacon DMA Interrupt 2 */\n#define\tIMR_BCNDMAINT1_8192E\t\t\t\tBIT(21)\t\t/* Beacon DMA Interrupt 1 */\n#define\tIMR_BCNDOK7_8192E\t\t\t\t\tBIT(20)\t\t/* Beacon Queue DMA OK Interrupt 7 */\n#define\tIMR_BCNDOK6_8192E\t\t\t\t\tBIT(19)\t\t/* Beacon Queue DMA OK Interrupt 6 */\n#define\tIMR_BCNDOK5_8192E\t\t\t\t\tBIT(18)\t\t/* Beacon Queue DMA OK Interrupt 5 */\n#define\tIMR_BCNDOK4_8192E\t\t\t\t\tBIT(17)\t\t/* Beacon Queue DMA OK Interrupt 4 */\n#define\tIMR_BCNDOK3_8192E\t\t\t\t\tBIT(16)\t\t/* Beacon Queue DMA OK Interrupt 3 */\n#define\tIMR_BCNDOK2_8192E\t\t\t\t\tBIT(15)\t\t/* Beacon Queue DMA OK Interrupt 2 */\n#define\tIMR_BCNDOK1_8192E\t\t\t\t\tBIT(14)\t\t/* Beacon Queue DMA OK Interrupt 1 */\n#define\tIMR_ATIMEND_E_8192E\t\t\t\tBIT(13)\t\t/* ATIM Window End Extension for Win7 */\n#define\tIMR_TXERR_8192E\t\t\t\t\tBIT(11)\t\t/* Tx Error Flag Interrupt Status, write 1 clear. */\n#define\tIMR_RXERR_8192E\t\t\t\t\tBIT(10)\t\t/* Rx Error Flag INT Status, Write 1 clear */\n#define\tIMR_TXFOVW_8192E\t\t\t\t\tBIT(9)\t\t\t/* Transmit FIFO Overflow */\n#define\tIMR_RXFOVW_8192E\t\t\t\t\tBIT(8)\t\t\t/* Receive FIFO Overflow */\n\n/* ----------------------------------------------------------------------------\n * 8192E Auto LLT bits\t\t\t\t\t\t(offset 0x224,  8bits)\n * ----------------------------------------------------------------------------\n * 224 REG_AUTO_LLT\n * move to hal_com_reg.h */\n\n/* ----------------------------------------------------------------------------\n * 8192E Auto LLT bits\t\t\t\t\t\t(offset 0x290,  32bits)\n * ---------------------------------------------------------------------------- */\n#define BIT_DMA_MODE\t\t\tBIT(1)\n#define BIT_USB_RXDMA_AGG_EN\tBIT(31)\n\n/* ----------------------------------------------------------------------------\n * 8192E REG_SYS_CFG1\t\t\t\t\t\t(offset 0xF0,  32bits)\n * ---------------------------------------------------------------------------- */\n#define BIT_SPSLDO_SEL\t\t\tBIT(24)\n\n\n/* ----------------------------------------------------------------------------\n * 8192E REG_CCK_CHECK\t\t\t\t\t\t(offset 0x454,  8bits)\n * ---------------------------------------------------------------------------- */\n#define BIT_BCN_PORT_SEL\t\tBIT(5)\n\n/* ****************************************************************************\n * Regsiter Bit and Content definition\n * **************************************************************************** */\n\n/* 2 ACMHWCTRL 0x05C0 */\n#define\tAcmHw_HwEn_8192E\t\t\t\tBIT(0)\n#define\tAcmHw_VoqEn_8192E\t\t\t\tBIT(1)\n#define\tAcmHw_ViqEn_8192E\t\t\t\tBIT(2)\n#define\tAcmHw_BeqEn_8192E\t\t\t\tBIT(3)\n#define\tAcmHw_VoqStatus_8192E\t\t\tBIT(5)\n#define\tAcmHw_ViqStatus_8192E\t\t\tBIT(6)\n#define\tAcmHw_BeqStatus_8192E\t\t\tBIT(7)\n\n#endif /* __RTL8192E_SPEC_H__ */\n"
  },
  {
    "path": "include/rtl8192e_sreset.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2012 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL88812A_SRESET_H_\n#define _RTL8812A_SRESET_H_\n\n#include <rtw_sreset.h>\n\n#ifdef DBG_CONFIG_ERROR_DETECT\n\textern void rtl8192e_sreset_xmit_status_check(_adapter *padapter);\n\textern void rtl8192e_sreset_linked_status_check(_adapter *padapter);\n#endif\n#endif\n"
  },
  {
    "path": "include/rtl8192e_xmit.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2012 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8192E_XMIT_H__\n#define __RTL8192E_XMIT_H__\n\ntypedef struct txdescriptor_8192e {\n\t/* Offset 0 */\n\tu32 pktlen:16;\n\tu32 offset:8;\n\tu32 bmc:1;\n\tu32 htc:1;\n\tu32 ls:1;\n\tu32 fs:1;\n\tu32 linip:1;\n\tu32 noacm:1;\n\tu32 gf:1;\n\tu32 own:1;\n\n\t/* Offset 4 */\n\tu32 macid:6;\n\tu32 rsvd0406:2;\n\tu32 qsel:5;\n\tu32 rd_nav_ext:1;\n\tu32 lsig_txop_en:1;\n\tu32 pifs:1;\n\tu32 rate_id:4;\n\tu32 navusehdr:1;\n\tu32 en_desc_id:1;\n\tu32 sectype:2;\n\tu32 rsvd0424:2;\n\tu32 pkt_offset:5;\t/* unit: 8 bytes */\n\tu32 rsvd0431:1;\n\n\t/* Offset 8 */\n\tu32 rts_rc:6;\n\tu32 data_rc:6;\n\tu32 agg_en:1;\n\tu32 rd_en:1;\n\tu32 bar_rty_th:2;\n\tu32 bk:1;\n\tu32 morefrag:1;\n\tu32 raw:1;\n\tu32 ccx:1;\n\tu32 ampdu_density:3;\n\tu32 bt_null:1;\n\tu32 ant_sel_a:1;\n\tu32 ant_sel_b:1;\n\tu32 tx_ant_cck:2;\n\tu32 tx_antl:2;\n\tu32 tx_ant_ht:2;\n\n\t/* Offset 12 */\n\tu32 nextheadpage:8;\n\tu32 tailpage:8;\n\tu32 seq:12;\n\tu32 cpu_handle:1;\n\tu32 tag1:1;\n\tu32 trigger_int:1;\n\tu32 hwseq_en:1;\n\n\t/* Offset 16 */\n\tu32 rtsrate:5;\n\tu32 ap_dcfe:1;\n\tu32 hwseq_sel:2;\n\tu32 userate:1;\n\tu32 disrtsfb:1;\n\tu32 disdatafb:1;\n\tu32 cts2self:1;\n\tu32 rtsen:1;\n\tu32 hw_rts_en:1;\n\tu32 port_id:1;\n\tu32 pwr_status:3;\n\tu32 wait_dcts:1;\n\tu32 cts2ap_en:1;\n\tu32 data_sc:2;\n\tu32 data_stbc:2;\n\tu32 data_short:1;\n\tu32 data_bw:1;\n\tu32 rts_short:1;\n\tu32 rts_bw:1;\n\tu32 rts_sc:2;\n\tu32 vcs_stbc:2;\n\n\t/* Offset 20 */\n\tu32 datarate:6;\n\tu32 sgi:1;\n\tu32 try_rate:1;\n\tu32 data_ratefb_lmt:5;\n\tu32 rts_ratefb_lmt:4;\n\tu32 rty_lmt_en:1;\n\tu32 data_rt_lmt:6;\n\tu32 usb_txagg_num:8;\n\n\t/* Offset 24 */\n\tu32 txagg_a:5;\n\tu32 txagg_b:5;\n\tu32 use_max_len:1;\n\tu32 max_agg_num:5;\n\tu32 mcsg1_max_len:4;\n\tu32 mcsg2_max_len:4;\n\tu32 mcsg3_max_len:4;\n\tu32 mcs7_sgi_max_len:4;\n\n\t/* Offset 28 */\n\tu32 checksum:16;\t/* TxBuffSize(PCIe)/CheckSum(USB) */\n\tu32 mcsg4_max_len:4;\n\tu32 mcsg5_max_len:4;\n\tu32 mcsg6_max_len:4;\n\tu32 mcs15_sgi_max_len:4;\n} TXDESC_8192E, *PTXDESC_8192E;\n\n\n\n/* For 88e early mode */\n#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)\n#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)\n#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)\n#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)\n#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)\n#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)\n#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)\n\n/*\n * defined for TX DESC Operation\n *   */\n\n#define MAX_TID (15)\n\n/* OFFSET 0 */\n#define OFFSET_SZ\t0\n#define OFFSET_SHT\t16\n#define BMC\t\tBIT(24)\n#define LSG\t\tBIT(26)\n#define FSG\t\tBIT(27)\n#define OWN\t\tBIT(31)\n\n\n/* OFFSET 4 */\n#define PKT_OFFSET_SZ\t\t0\n#define QSEL_SHT\t\t\t8\n#define RATE_ID_SHT\t\t\t16\n#define NAVUSEHDR\t\t\tBIT(20)\n#define SEC_TYPE_SHT\t\t22\n#define PKT_OFFSET_SHT\t\t26\n\n/* OFFSET 8 */\n#define AGG_EN\t\t\t\tBIT(12)\n#define AGG_BK\t\t\t\t\tBIT(16)\n#define AMPDU_DENSITY_SHT\t20\n#define ANTSEL_A\t\t\tBIT(24)\n#define ANTSEL_B\t\t\tBIT(25)\n#define TX_ANT_CCK_SHT\t\t26\n#define TX_ANTL_SHT\t\t\t28\n#define TX_ANT_HT_SHT\t\t30\n\n/* OFFSET 12 */\n#define SEQ_SHT\t\t\t\t16\n#define EN_HWSEQ\t\t\tBIT(31)\n\n/* OFFSET 16 */\n#define\tQOS                          BIT(6)\n#define\tHW_SSN\t\t\t\tBIT(7)\n#define\tUSERATE\t\t\tBIT(8)\n#define\tDISDATAFB\t\t\tBIT(10)\n#define   CTS_2_SELF\t\t\tBIT(11)\n#define\tRTS_EN\t\t\t\tBIT(12)\n#define\tHW_RTS_EN\t\t\tBIT(13)\n#define\tDATA_SHORT\t\t\tBIT(24)\n#define\tPWR_STATUS_SHT\t15\n#define\tDATA_SC_SHT\t\t20\n#define\tDATA_BW\t\t\tBIT(25)\n\n/* OFFSET 20 */\n#define\tRTY_LMT_EN\t\t\tBIT(17)\n\n\n/* OFFSET 20 */\n#define SGI\t\t\t\t\tBIT(6)\n#define USB_TXAGG_NUM_SHT\t24\n\n\n/* *****Tx Desc Buffer content */\n\n/* config element for each tx buffer\n *\n#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 0, 16, __Valeu)\n#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 31, 1, __Valeu)\n#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+4, 0, 32, __Valeu)\n#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu)\n*/\n#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)\n#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)\n#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)\n#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu)\n\n\n/* Dword 0 */\n#define SET_TX_BUFF_DESC_LEN_0_92E(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)\n#define SET_TX_BUFF_DESC_PSB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)\n#define SET_TX_BUFF_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)\n/* Dword 1 */\n#define SET_TX_BUFF_DESC_ADDR_LOW_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)\n#define GET_TX_DESC_TX_BUFFER_ADDRESS_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)\n\n\n/* Dword 2 */\n#define SET_TX_BUFF_DESC_ADDR_HIGH_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 32, __Value)\n/* Dword 3, RESERVED */\n\n\n/* *****Tx Desc content\n * Dword 0 */\n#define SET_TX_DESC_PKT_SIZE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)\n#define SET_TX_DESC_OFFSET_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)\n#define SET_TX_DESC_BMC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)\n#define SET_TX_DESC_HTC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)\n#define SET_TX_DESC_LAST_SEG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)\n#define SET_TX_DESC_FIRST_SEG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)\n#define SET_TX_DESC_LINIP_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)\n#define SET_TX_DESC_NO_ACM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)\n#define SET_TX_DESC_GF_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)\n#define SET_TX_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)\n#define GET_TX_DESC_OWN_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)\n\n/* Dword 1 */\n#define SET_TX_DESC_MACID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)\n#define SET_TX_DESC_QUEUE_SEL_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)\n#define SET_TX_DESC_RDG_NAV_EXT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)\n#define SET_TX_DESC_LSIG_TXOP_EN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)\n#define SET_TX_DESC_PIFS_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)\n#define SET_TX_DESC_RATE_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)\n#define SET_TX_DESC_EN_DESC_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)\n#define SET_TX_DESC_SEC_TYPE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)\n#define SET_TX_DESC_PKT_OFFSET_92E(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)\n#define SET_TX_DESC_MORE_DATA_92E(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)\n#define SET_TX_DESC_TXOP_PS_CAP_92E(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 30, 1, __Value)\n#define SET_TX_DESC_TXOP_PS_MODE_92E(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 31, 1, __Value)\n\n\n/* Dword 2 */\n#define SET_TX_DESC_PAID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)\n#define SET_TX_DESC_CCA_RTS_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)\n#define SET_TX_DESC_AGG_ENABLE_92E(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)\n#define SET_TX_DESC_RDG_ENABLE_92E(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)\n#define SET_TX_DESC_NULL_0_92E(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)\n#define SET_TX_DESC_NULL_1_92E(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)\n#define SET_TX_DESC_BK_92E(__pTxDesc, __Value)\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)\n#define SET_TX_DESC_MORE_FRAG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)\n#define SET_TX_DESC_RAW_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)\n#define GET_TX_DESC_MORE_FRAG_92E(__pTxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pTxDesc+8, 17, 1)\n#define SET_TX_DESC_SPE_RPT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)\n#define SET_TX_DESC_AMPDU_DENSITY_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)\n#define SET_TX_DESC_BT_NULL_92E(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)\n#define SET_TX_DESC_GID_92E(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)\n\n\n/* Dword 3 */\n#define SET_TX_DESC_WHEADER_LEN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)\n#define SET_TX_DESC_CHK_EN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)\n#define SET_TX_DESC_EARLY_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)\n#define SET_TX_DESC_HWSEQ_SEL_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)\n#define SET_TX_DESC_USE_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)\n#define SET_TX_DESC_DISABLE_RTS_FB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)\n#define SET_TX_DESC_DISABLE_FB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)\n#define SET_TX_DESC_CTS2SELF_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)\n#define SET_TX_DESC_RTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)\n#define SET_TX_DESC_HW_RTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)\n#define SET_TX_DESC_HW_PORT_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value)\n#define SET_TX_DESC_NAV_USE_HDR_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)\n#define SET_TX_DESC_USE_MAX_LEN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)\n#define SET_TX_DESC_MAX_AGG_NUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)\n#define SET_TX_DESC_NDPA_92E(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)\n#define SET_TX_DESC_AMPDU_MAX_TIME_92E(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)\n\n/* Dword 4 */\n#define SET_TX_DESC_TX_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)\n#define SET_TX_DESC_TRY_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)\n#define SET_TX_DESC_DATA_RATE_FB_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)\n#define SET_TX_DESC_RTS_RATE_FB_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)\n#define SET_TX_DESC_RETRY_LIMIT_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)\n#define SET_TX_DESC_DATA_RETRY_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)\n#define SET_TX_DESC_RTS_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)\n#define SET_TX_DESC_PCTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)\n#define SET_TX_DESC_PCTS_MASK_IDX_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)\n\n\n/* Dword 5 */\n#define SET_TX_DESC_DATA_SC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)\n#define SET_TX_DESC_DATA_SHORT_92E(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)\n#define SET_TX_DESC_DATA_BW_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)\n#define SET_TX_DESC_DATA_LDPC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)\n#define SET_TX_DESC_DATA_STBC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)\n#define SET_TX_DESC_VCS_STBC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)\n#define SET_TX_DESC_RTS_SHORT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)\n#define SET_TX_DESC_RTS_SC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)\n#define SET_TX_DESC_TX_ANT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value)\n#define SET_TX_DESC_TX_POWER_0_PSET_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)\n\n/* Dword 6 */\n#define SET_TX_DESC_SW_DEFINE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)\n#define SET_TX_DESC_MBSSID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)\n#define SET_TX_DESC_ANTSEL_A_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)\n#define SET_TX_DESC_ANTSEL_B_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)\n#define SET_TX_DESC_ANTSEL_C_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)\n#define SET_TX_DESC_ANTSEL_D_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)\n\n/* Dword 7 */\n#ifdef CONFIG_PCI_HCI\n\t#define SET_TX_DESC_TX_BUFFER_SIZE_92E(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n#endif\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)\n\t#define SET_TX_DESC_TX_DESC_CHECKSUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n#endif\n#define SET_TX_DESC_USB_TXAGG_NUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)\n\n\n/* #define SET_TX_DESC_HWSEQ_EN_92E(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) */\n/* Dword 8 */\n\n#define SET_TX_DESC_RTS_RC_92E(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)\n#define SET_TX_DESC_BAR_RTY_TH_92E(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)\n#define SET_TX_DESC_DATA_RC_92E(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)\n#define SET_TX_DESC_EN_HWSEQ_92E(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)\n#define SET_TX_DESC_NEXT_HEAD_PAGE_92E(__pTxDesc, __Value)(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)\n#define SET_TX_DESC_TAIL_PAGE_92E(__pTxDesc, __Value)(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)\n\n/* Dword 9 */\n#define SET_TX_DESC_PADDING_LENGTH_92E(__pTxDesc, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)\n#define SET_TX_DESC_TXBF_PATH_92E(__pTxDesc, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 11, 1, __Value)\n#define SET_TX_DESC_SEQ_92E(__pTxDesc, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)\n#define SET_TX_DESC_FINAL_DATA_RATE_92E(__pTxDesc, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)\n\n\n#define SET_EARLYMODE_PKTNUM_92E(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)\n#define SET_EARLYMODE_LEN0_92E(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)\n#define SET_EARLYMODE_LEN1_1_92E(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)\n#define SET_EARLYMODE_LEN1_2_92E(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)\n#define SET_EARLYMODE_LEN2_92E(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,  __Value)\n#define SET_EARLYMODE_LEN3_92E(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)\n\nvoid rtl8192e_cal_txdesc_chksum(u8 *ptxdesc);\n\n#ifdef CONFIG_USB_HCI\n\ts32 rtl8192eu_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8192eu_free_xmit_priv(PADAPTER padapter);\n\ts32 rtl8192eu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8192eu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\trtl8192eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8192eu_xmit_buf_handler(PADAPTER padapter);\n\t#define hal_xmit_handler rtl8192eu_xmit_buf_handler\n\tvoid rtl8192eu_xmit_tasklet(void *priv);\n\ts32 rtl8192eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\ts32 rtl8192ee_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8192ee_free_xmit_priv(PADAPTER padapter);\n\tstruct xmit_buf *rtl8192ee_dequeue_xmitbuf(struct rtw_tx_ring *ring);\n\ts32\trtl8192ee_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\tvoid\trtl8192ee_xmitframe_resume(_adapter *padapter);\n\ts32 rtl8192ee_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8192ee_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\tvoid rtl8192ee_xmit_tasklet(void *priv);\n#endif\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\ts32 rtl8192es_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8192es_free_xmit_priv(PADAPTER padapter);\n\n\ts32 rtl8192es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8192es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\trtl8192es_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\tthread_return rtl8192es_xmit_thread(thread_context context);\n\ts32 rtl8192es_xmit_buf_handler(PADAPTER padapter);\n\n\t#ifdef CONFIG_SDIO_TX_TASKLET\n\t\tvoid rtl8192es_xmit_tasklet(void *priv);\n\t#endif\n#endif\n\nstruct txrpt_ccx_92e {\n\t/* offset 0 */\n\tu8 tag1:1;\n\tu8 pkt_num:3;\n\tu8 txdma_underflow:1;\n\tu8 int_bt:1;\n\tu8 int_tri:1;\n\tu8 int_ccx:1;\n\n\t/* offset 1 */\n\tu8 mac_id:6;\n\tu8 pkt_ok:1;\n\tu8 bmc:1;\n\n\t/* offset 2 */\n\tu8 retry_cnt:6;\n\tu8 lifetime_over:1;\n\tu8 retry_over:1;\n\n\t/* offset 3 */\n\tu8 ccx_qtime0;\n\tu8 ccx_qtime1;\n\n\t/* offset 5 */\n\tu8 final_data_rate;\n\n\t/* offset 6 */\n\tu8 sw1:4;\n\tu8 qsel:4;\n\n\t/* offset 7 */\n\tu8 sw0;\n};\n\n#ifdef CONFIG_TX_EARLY_MODE\n\tvoid UpdateEarlyModeInfo8192E(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\n#endif\ns32\trtl8192e_init_xmit_priv(_adapter *padapter);\nvoid _dbg_dump_tx_info(_adapter\t*padapter, int frame_tag, u8 *ptxdesc);\n\nvoid rtl8192e_fill_fake_txdesc(PADAPTER\tpadapter, u8 *pDesc, u32 BufferLen,\n\t\t\t       u8 IsPsPoll, u8\tIsBTQosNull, u8 bDataFrame);\nvoid rtl8192e_cal_txdesc_chksum(u8 *ptxdesc);\n\nu8\tBWMapping_92E(PADAPTER Adapter, struct pkt_attrib *pattrib);\nu8\tSCMapping_92E(PADAPTER Adapter, struct pkt_attrib\t*pattrib);\nvoid fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);\nvoid fill_txdesc_vcs(struct pkt_attrib *pattrib, u8 *ptxdesc);\n#if defined(CONFIG_CONCURRENT_MODE)\n\tvoid fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);\n#endif\nvoid fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);\n\nvoid fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc);\nvoid rtl8192e_fixed_rate(_adapter *padapter, u8 *ptxdesc);\n\n#endif /* __RTL8192E_XMIT_H__ */\n"
  },
  {
    "path": "include/rtl8192f_cmd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8192F_CMD_H__\n#define __RTL8192F_CMD_H__\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\nenum h2c_cmd_8192F {\n\t/* Common Class: 000 */\n\tH2C_8192F_RSVD_PAGE = 0x00,\n\tH2C_8192F_MEDIA_STATUS_RPT = 0x01,\n\tH2C_8192F_SCAN_ENABLE = 0x02,\n\tH2C_8192F_KEEP_ALIVE = 0x03,\n\tH2C_8192F_DISCON_DECISION = 0x04,\t\n\tH2C_8192F_PSD_OFFLOAD = 0x05,\t\n\tH2C_8192F_AP_OFFLOAD = 0x08,\t\n\tH2C_8192F_BCN_RSVDPAGE = 0x09,\t\n\tH2C_8192F_PROBERSP_RSVDPAGE = 0x0A,\t\n\tH2C_8192F_FCS_RSVDPAGE = 0x10,\t\n\tH2C_8192F_FCS_INFO = 0x11,\t\n\tH2C_8192F_AP_WOW_GPIO_CTRL = 0x13,\n\n\t/* PoweSave Class: 001 */\n\tH2C_8192F_SET_PWR_MODE = 0x20,\n\tH2C_8192F_PS_TUNING_PARA = 0x21,\n\tH2C_8192F_PS_TUNING_PARA2 = 0x22,\n\tH2C_8192F_P2P_LPS_PARAM = 0x23,\t\n\tH2C_8192F_P2P_PS_OFFLOAD = 0x24,\t\n\tH2C_8192F_PS_SCAN_ENABLE = 0x25,\t\n\tH2C_8192F_SAP_PS_ = 0x26,\n\tH2C_8192F_INACTIVE_PS_ = 0x27,/* Inactive_PS */\n\tH2C_8192F_FWLPS_IN_IPS_ = 0x28,\n\n\t/* Dynamic Mechanism Class: 010 */\n\tH2C_8192F_MACID_CFG = 0x40,\t\n\tH2C_8192F_TXBF = 0x41,\t\n\tH2C_8192F_RSSI_SETTING = 0x42,\t\n\tH2C_8192F_AP_REQ_TXRPT = 0x43,\t\n\tH2C_8192F_INIT_RATE_COLLECT = 0x44,\t\n\tH2C_8192F_RA_PARA_ADJUST = 0x46,\n\n\t/* BT Class: 011 */\n\tH2C_8192F_B_TYPE_TDMA = 0x60,\n\tH2C_8192F_BT_INFO = 0x61,\n\tH2C_8192F_FORCE_BT_TXPWR = 0x62,\n\tH2C_8192F_BT_IGNORE_WLANACT = 0x63,\n\tH2C_8192F_DAC_SWING_VALUE = 0x64,\n\tH2C_8192F_ANT_SEL_RSV = 0x65,\n\tH2C_8192F_WL_OPMODE = 0x66,\n\tH2C_8192F_BT_MP_OPER = 0x67,\n\tH2C_8192F_BT_CONTROL = 0x68,\n\tH2C_8192F_BT_WIFI_CTRL = 0x69,\n\tH2C_8192F_BT_FW_PATCH = 0x6A,\n\tH2C_8192F_BT_WLAN_CALIBRATION = 0x6D,\n\n\t/* WOWLAN Class: 100 */\n\tH2C_8192F_WOWLAN = 0x80,\n\tH2C_8192F_REMOTE_WAKE_CTRL = 0x81,\n\tH2C_8192F_AOAC_GLOBAL_INFO = 0x82,\t\n\tH2C_8192F_AOAC_RSVD_PAGE = 0x83,\t\n\tH2C_8192F_AOAC_RSVD_PAGE2 = 0x84,\n\tH2C_8192F_D0_SCAN_OFFLOAD_CTRL = 0x85,\n\tH2C_8192F_D0_SCAN_OFFLOAD_INFO = 0x86,\n\tH2C_8192F_CHNL_SWITCH_OFFLOAD = 0x87,\n\tH2C_8192F_P2P_OFFLOAD_RSVD_PAGE = 0x8A,\t\n\tH2C_8192F_P2P_OFFLOAD = 0x8B,\n\n\tH2C_8192F_RESET_TSF = 0xC0,\n\tH2C_8192F_MAXID,\n};\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------\n * ---------------------------------------------------------------------------------------------------------\n * _RSVDPAGE_LOC_CMD_0x00 */\n#define SET_8192F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8192F_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_8192F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8192F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8192F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n/*_MEDIA_STATUS_RPT_PARM_CMD_0x01*/\n#define SET_8192F_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)\n/* _PWR_MOD_CMD_0x20 */\n#define SET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8192F_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)\n#define SET_8192F_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)\n#define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8192F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)\n#define SET_8192F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n#define GET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)\t\t\t\t\tLE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)\n\n/* _PS_TUNE_PARAM_CMD_0x21 */\n#define SET_8192F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_8192F_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)\n#define SET_8192F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)\n#define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n\n/* _MACID_CFG_CMD_0x40 */\n#define SET_8192F_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8192F_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)\n#define SET_8192F_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)\n#define SET_8192F_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)\n#define SET_8192F_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)\n#define SET_8192F_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)\n#define SET_8192F_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)\n#define SET_8192F_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)\n#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)\n#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)\n#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)\n\n/* _RSSI_SETTING_CMD_0x42 */\n#define SET_8192F_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8192F_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)\n#define SET_8192F_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n\n/* _AP_REQ_TXRPT_CMD_0x43 */\n#define SET_8192F_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8192F_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n\n/* _FORCE_BT_TXPWR_CMD_0x62 */\n#define SET_8192F_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n\n/* _FORCE_BT_MP_OPER_CMD_0x67 */\n#define SET_8192F_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)\n#define SET_8192F_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)\n#define SET_8192F_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_8192F_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)\n#define SET_8192F_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n#define SET_8192F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)\n\n/* _BT_FW_PATCH_0x6A */\n#define SET_8192F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)\n#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)\n\n/* ---------------------------------------------------------------------------------------------------------\n * -------------------------------------------    Structure    --------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    Function Statement     --------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\n/* host message to firmware cmd */\nvoid rtl8192f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);\nvoid rtl8192f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);\n/* s32 rtl8192f__set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */\nvoid rtl8192f_set_FwPsTuneParam_cmd(PADAPTER padapter);\nvoid rtl8192f_download_rsvd_page(PADAPTER padapter, u8 mstatus);\n#ifdef CONFIG_BT_COEXIST\n\tvoid rtl8192f__download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);\n#endif /* CONFIG_BT_COEXIST */\n#ifdef CONFIG_P2P\n\tvoid rtl8192f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\nvoid rtl8192f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);\n#endif\n#endif\n\n#ifdef CONFIG_P2P_WOWLAN\n\tvoid rtl8192f_set_p2p_wowlan_offload_cmd(PADAPTER padapter);\n#endif\n\ns32 FillH2CCmd8192F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);\nu8 GetTxBufferRsvdPageNum8192F(_adapter *padapter, bool wowlan);\n#endif\n"
  },
  {
    "path": "include/rtl8192f_dm.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2012 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8192F_DM_H__\n#define __RTL8192F_DM_H__\n\nvoid rtl8192f_init_dm_priv(PADAPTER Adapter);\nvoid rtl8192f_deinit_dm_priv(PADAPTER Adapter);\nvoid rtl8192f_InitHalDm(PADAPTER Adapter);\nvoid rtl8192f_HalDmWatchDog(PADAPTER Adapter);\n\n/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */\n\n/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */\n\n#endif\n"
  },
  {
    "path": "include/rtl8192f_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8192F_HAL_H__\n#define __RTL8192F_HAL_H__\n\n#include \"hal_data.h\"\n\n#include \"rtl8192f_spec.h\"\n#include \"rtl8192f_rf.h\"\n#include \"rtl8192f_dm.h\"\n#include \"rtl8192f_recv.h\"\n#include \"rtl8192f_xmit.h\"\n#include \"rtl8192f_cmd.h\"\n#include \"rtl8192f_led.h\"\n#include \"Hal8192FPwrSeq.h\"\n#include \"Hal8192FPhyReg.h\"\n#include \"Hal8192FPhyCfg.h\"\n#ifdef DBG_CONFIG_ERROR_DETECT\n#include \"rtl8192f_sreset.h\"\n#endif\n#ifdef CONFIG_LPS_POFF\n\t#include \"rtl8192f_lps_poff.h\"\n#endif\n\n#define FW_8192F_SIZE\t\t0x8000\n#define FW_8192F_START_ADDRESS\t0x4000\n#define FW_8192F_END_ADDRESS\t0x5000 /* brian_zhang@realsil.com.cn */\n\n#define IS_FW_HEADER_EXIST_8192F(_pFwHdr)\\\n\t((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x92F0)\n\ntypedef struct _RT_FIRMWARE {\n\tFIRMWARE_SOURCE\teFWSource;\n#ifdef CONFIG_EMBEDDED_FWIMG\n\tu8\t\t\t*szFwBuffer;\n#else\n\tu8\t\t\tszFwBuffer[FW_8192F_SIZE];\n#endif\n\tu32\t\t\tulFwLength;\n} RT_FIRMWARE_8192F, *PRT_FIRMWARE_8192F;\n\n/*\n * This structure must be cared byte-ordering\n *\n * Added by tynli. 2009.12.04. */\ntypedef struct _RT_8192F_FIRMWARE_HDR {\n\t/* 8-byte alinment required */\n\n\t/* --- LONG WORD 0 ---- */\n\tu16\t\tSignature;\t/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */\n\tu8\t\tCategory;\t/* AP/NIC and USB/PCI */\n\tu8\t\tFunction;\t/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */\n\tu16\t\tVersion;\t\t/* FW Version */\n\tu16\t\tSubversion;\t/* FW Subversion, default 0x00 */\n\n\t/* --- LONG WORD 1 ---- */\n\tu8\t\tMonth;\t/* Release time Month field */\n\tu8\t\tDate;\t/* Release time Date field */\n\tu8\t\tHour;\t/* Release time Hour field */\n\tu8\t\tMinute;\t/* Release time Minute field */\n\tu16\t\tRamCodeSize;\t/* The size of RAM code */\n\tu16\t\tRsvd2;\n\n\t/* --- LONG WORD 2 ---- */\n\tu32\t\tSvnIdx;\t/* The SVN entry index */\n\tu32\t\tRsvd3;\n\n\t/* --- LONG WORD 3 ---- */\n\tu32\t\tRsvd4;\n\tu32\t\tRsvd5;\n} RT_8192F_FIRMWARE_HDR, *PRT_8192F_FIRMWARE_HDR;\n#define DRIVER_EARLY_INT_TIME_8192F\t\t0x05\n#define BCN_DMA_ATIME_INT_TIME_8192F\t\t0x02\n/* for 8192F\n * TX 64K, RX 16K, Page size 256B for TX*/\n#define PAGE_SIZE_TX_8192F\t\t\t256\n#define PAGE_SIZE_RX_8192F\t\t\t8\n#define TX_DMA_SIZE_8192F\t\t\t0x10000/* 64K(TX) */\n#define RX_DMA_SIZE_8192F\t\t\t0x4000/* 16K(RX) */\n#ifdef CONFIG_WOWLAN\n\t#define RESV_FMWF\t(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/\n#else\n\t#define RESV_FMWF\t0\n#endif\n\n#ifdef CONFIG_FW_C2H_DEBUG\n\t#define RX_DMA_RESERVED_SIZE_8192F\t0x100\t/* 256B, reserved for c2h debug message */\n#else\n\t#define RX_DMA_RESERVED_SIZE_8192F\t0xc0\t/* 192B, reserved for tx report 24*8=192*/\n#endif\n#define RX_DMA_BOUNDARY_8192F\\\n\t(RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F - 1)\n\n\n/* Note: We will divide number of page equally for each queue other than public queue! */\n\n/* For General Reserved Page Number(Beacon Queue is reserved page)\n * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8192F\n * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/\n#define BCNQ_PAGE_NUM_8192F\t\t(MAX_BEACON_LEN/PAGE_SIZE_TX_8192F + 6) /*0x08*/\n\n\n/* For WoWLan , more reserved page\n * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6\n * NS offload: 2 NDP info: 1\n */\n#ifdef CONFIG_WOWLAN\n\t#define WOWLAN_PAGE_NUM_8192F\t0x07\n#else\n\t#define WOWLAN_PAGE_NUM_8192F\t0x00\n#endif\n\n#ifdef CONFIG_PNO_SUPPORT\n\t#undef WOWLAN_PAGE_NUM_8192F\n\t#define WOWLAN_PAGE_NUM_8192F\t0x15\n#endif\n\n#ifdef CONFIG_AP_WOWLAN\n\t#define AP_WOWLAN_PAGE_NUM_8192F\t0x02\n#endif\n\n#ifdef DBG_LA_MODE\n\t#define LA_MODE_PAGE_NUM 0xE0\n#endif\n\n#define MAX_RX_DMA_BUFFER_SIZE_8192F\t(RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F)\n\n#ifdef DBG_LA_MODE\n\t#define TX_TOTAL_PAGE_NUMBER_8192F\t(0xFF - LA_MODE_PAGE_NUM)\n#else\n\t#define TX_TOTAL_PAGE_NUMBER_8192F\t(0xFF - BCNQ_PAGE_NUM_8192F - WOWLAN_PAGE_NUM_8192F)\n#endif\n\n#define TX_PAGE_BOUNDARY_8192F\t\t(TX_TOTAL_PAGE_NUMBER_8192F + 1)\n\n#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8192F \\\n\tTX_TOTAL_PAGE_NUMBER_8192F\n#define WMM_NORMAL_TX_PAGE_BOUNDARY_8192F \\\n\t(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8192F + 1)\n\n/* For Normal Chip Setting\n * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8192F */\n#define NORMAL_PAGE_NUM_HPQ_8192F\t\t0x8\n#define NORMAL_PAGE_NUM_LPQ_8192F\t\t0x8\n#define NORMAL_PAGE_NUM_NPQ_8192F\t\t0x8\n#define NORMAL_PAGE_NUM_EPQ_8192F\t\t0x00\n\n/* Note: For Normal Chip Setting, modify later */\n#define WMM_NORMAL_PAGE_NUM_HPQ_8192F\t\t0x30\n#define WMM_NORMAL_PAGE_NUM_LPQ_8192F\t\t0x20\n#define WMM_NORMAL_PAGE_NUM_NPQ_8192F\t\t0x20\n#define WMM_NORMAL_PAGE_NUM_EPQ_8192F\t\t0x00\n\n\n#include \"HalVerDef.h\"\n#include \"hal_com.h\"\n\n#define EFUSE_OOB_PROTECT_BYTES 56 /*0x1C8~0x1FF*/\n\n#define HAL_EFUSE_MEMORY\n#define HWSET_MAX_SIZE_8192F                512\n#define EFUSE_REAL_CONTENT_LEN_8192F        512\n#define EFUSE_MAP_LEN_8192F                 512\n#define EFUSE_MAX_SECTION_8192F            64\n\n/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/\n#define EFUSE_IC_ID_OFFSET\t\t\t506\n#define AVAILABLE_EFUSE_ADDR(addr)\t(addr < EFUSE_REAL_CONTENT_LEN_8192F)\n\n#define EFUSE_ACCESS_ON\t\t0x69\n#define EFUSE_ACCESS_OFF\t0x00\n\n/* ********************************************************\n *\t\t\tEFUSE for BT definition\n * ******************************************************** */\n#define BANK_NUM\t\t\t1\n#define EFUSE_BT_REAL_BANK_CONTENT_LEN\t512\n#define EFUSE_BT_REAL_CONTENT_LEN\t1536/*512 * 3 */\n/*\t(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)*/\n#define EFUSE_BT_MAP_LEN\t\t1024\t/* 1k bytes */\n#define EFUSE_BT_MAX_SECTION\t\t128 /* 1024/8 */\n#define EFUSE_PROTECT_BYTES_BANK\t16\n\ntypedef enum tag_Package_Definition {\n\tPACKAGE_DEFAULT,\n\tPACKAGE_QFN32,\n\tPACKAGE_QFN40,\n\tPACKAGE_QFN46\n} PACKAGE_TYPE_E;\n\n#define INCLUDE_MULTI_FUNC_BT(_Adapter) \\\n\t(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)\n#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \\\n\t(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)\n\n#ifdef CONFIG_FILE_FWIMG\n\textern char *rtw_fw_file_path;\n\textern char *rtw_fw_wow_file_path;\n\t#ifdef CONFIG_MP_INCLUDED\n\t\textern char *rtw_fw_mp_bt_file_path;\n\t#endif /* CONFIG_MP_INCLUDED */\n#endif /* CONFIG_FILE_FWIMG */\n\n/* rtl8192f_hal_init.c */\ns32 rtl8192f_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);\nvoid rtl8192f_FirmwareSelfReset(PADAPTER padapter);\nvoid rtl8192f_InitializeFirmwareVars(PADAPTER padapter);\n\nvoid rtl8192f_InitAntenna_Selection(PADAPTER padapter);\nvoid rtl8192f_DeinitAntenna_Selection(PADAPTER padapter);\nvoid rtl8192f_CheckAntenna_Selection(PADAPTER padapter);\nvoid rtl8192f_init_default_value(PADAPTER padapter);\n\ns32 rtl8192f_InitLLTTable(PADAPTER padapter);\n\ns32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);\ns32 CardDisableWithoutHWSM(PADAPTER padapter);\n\n/* EFuse */\nu8 GetEEPROMSize8192F(PADAPTER padapter);\nvoid Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);\nvoid Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);\nvoid Hal_EfuseParseTxPowerInfo_8192F(PADAPTER padapter,\n\t\t\t\t\tu8 *PROMContent, BOOLEAN AutoLoadFail);\n/*\nvoid Hal_EfuseParseBTCoexistInfo_8192F(PADAPTER padapter,\n\t\t\t\t       u8 *hwinfo, BOOLEAN AutoLoadFail);\n*/\nvoid Hal_EfuseParseEEPROMVer_8192F(PADAPTER padapter,\n\t\t\t\t   u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseChnlPlan_8192F(PADAPTER padapter,\n\t\t\t\t  u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseCustomerID_8192F(PADAPTER padapter,\n\t\t\t\t    u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseAntennaDiversity_8192F(PADAPTER padapter,\n\t\tu8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseXtal_8192F(PADAPTER pAdapter,\n\t\t\t      u8 *hwinfo, u8 AutoLoadFail);\nvoid Hal_EfuseParseThermalMeter_8192F(PADAPTER padapter,\n\t\t\t\t      u8 *hwinfo, u8 AutoLoadFail);\nvoid Hal_EfuseParseVoltage_8192F(PADAPTER pAdapter,\n\t\t\t\t u8 *hwinfo, BOOLEAN\tAutoLoadFail);\nvoid Hal_EfuseParseBoardType_8192F(PADAPTER Adapter,\n\t\t\t\t   u8\t*PROMContent, BOOLEAN AutoloadFail);\nu8\tHal_ReadRFEType_8192F(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);\nvoid rtl8192f_set_hal_ops(struct hal_ops *pHalFunc);\nvoid init_hal_spec_8192f(_adapter *adapter);\nu8 SetHwReg8192F(PADAPTER padapter, u8 variable, u8 *val);\nvoid GetHwReg8192F(PADAPTER padapter, u8 variable, u8 *val);\nu8 SetHalDefVar8192F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);\nu8 GetHalDefVar8192F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);\n\n/* register */\nvoid rtl8192f_InitBeaconParameters(PADAPTER padapter);\nvoid rtl8192f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);\n\nvoid _InitMacAPLLSetting_8192F(PADAPTER Adapter);\nvoid _8051Reset8192F(PADAPTER padapter);\n#ifdef CONFIG_WOWLAN\n\tvoid Hal_DetectWoWMode(PADAPTER pAdapter);\n#endif /* CONFIG_WOWLAN */\n\nvoid rtl8192f_start_thread(_adapter *padapter);\nvoid rtl8192f_stop_thread(_adapter *padapter);\n\n#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)\n\tvoid rtl8192fs_init_checkbthang_workqueue(_adapter *adapter);\n\tvoid rtl8192fs_free_checkbthang_workqueue(_adapter *adapter);\n\tvoid rtl8192fs_cancle_checkbthang_workqueue(_adapter *adapter);\n\tvoid rtl8192fs_hal_check_bt_hang(_adapter *adapter);\n#endif\n\n#ifdef CONFIG_GPIO_WAKEUP\n\tvoid HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);\n#endif\n#ifdef CONFIG_MP_INCLUDED\nint FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);\n#endif\nvoid CCX_FwC2HTxRpt_8192f(PADAPTER padapter, u8 *pdata, u8 len);\n\nu8 MRateToHwRate8192F(u8 rate);\nu8 HwRateToMRate8192F(u8 rate);\n\n#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)\n\tvoid check_bt_status_work(void *data);\n#endif\n\n\nvoid rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc);\n\n#ifdef CONFIG_AMPDU_PRETX_CD\nvoid rtl8192f_pretx_cd_config(_adapter *adapter);\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\tBOOLEAN\tInterruptRecognized8192FE(PADAPTER Adapter);\n\tvoid\tUpdateInterruptMask8192FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);\n\tvoid InitMAC_TRXBD_8192FE(PADAPTER Adapter);\n\n\tu16 get_txbd_rw_reg(u16 ff_hwaddr);\n#endif\n\n#endif\n"
  },
  {
    "path": "include/rtl8192f_led.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8192F_LED_H__\n#define __RTL8192F_LED_H__\n\n#include <drv_conf.h>\n#include <osdep_service.h>\n#include <drv_types.h>\n\n#ifdef CONFIG_RTW_SW_LED\n/* ********************************************************************************\n * Interface to manipulate LED objects.\n * ******************************************************************************** */\n#ifdef CONFIG_USB_HCI\nvoid rtl8192fu_InitSwLeds(PADAPTER padapter);\nvoid rtl8192fu_DeInitSwLeds(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_SDIO_HCI\nvoid rtl8192fs_InitSwLeds(PADAPTER padapter);\nvoid rtl8192fs_DeInitSwLeds(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_PCI_HCI\nvoid rtl8192fe_InitSwLeds(PADAPTER padapter);\nvoid rtl8192fe_DeInitSwLeds(PADAPTER padapter);\n#endif\n#endif /*#ifdef CONFIG_RTW_SW_LED*/\n\n#endif\n"
  },
  {
    "path": "include/rtl8192f_recv.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8192F_RECV_H__\n#define __RTL8192F_RECV_H__\n\n#define RECV_BLK_SZ 512\n#define RECV_BLK_CNT 16\n#define RECV_BLK_TH RECV_BLK_CNT\n\n#if defined(CONFIG_USB_HCI)\n\n\t#ifndef MAX_RECVBUF_SZ\n\t\t#ifndef CONFIG_MINIMAL_MEMORY_USAGE\n\t\t\t/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */\n\t\t\t/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */\n\t\t\t/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */\n\t\t\t#ifdef CONFIG_PLATFORM_MSTAR\n\t\t\t\t#define MAX_RECVBUF_SZ (8192) /* 8K */\n\t\t\t#else\n\t\t\t\t#define MAX_RECVBUF_SZ (32768) /* 32k */\n\t\t\t#endif\n\t\t\t/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */\n\t\t#else\n\t\t\t#define MAX_RECVBUF_SZ (4000) /* about 4K */\n\t\t#endif\n\t#endif /* !MAX_RECVBUF_SZ */\n\n#elif defined(CONFIG_PCI_HCI)\n\t#define MAX_RECVBUF_SZ (4000) /* about 4K */\n\n#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\n\t#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8192F + 1)\n\n#endif\n\n/* Rx smooth factor */\n#define\tRx_Smooth_Factor (20)\n\n#ifdef CONFIG_SDIO_HCI\n\t#ifndef CONFIG_SDIO_RX_COPY\n\t\t#undef MAX_RECVBUF_SZ\n\t\t#define MAX_RECVBUF_SZ\t(RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F)\n\t#endif /* !CONFIG_SDIO_RX_COPY */\n#endif /* CONFIG_SDIO_HCI */\n\n/*-----------------------------------------------------------------*/\n/*\tRTL8192F RX BUFFER DESC                                      */\n/*-----------------------------------------------------------------*/\n/*DWORD 0*/\n#define SET_RX_BUFFER_DESC_DATA_LENGTH_8192F(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)\n#define SET_RX_BUFFER_DESC_LS_8192F(__pRxStatusDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)\n#define SET_RX_BUFFER_DESC_FS_8192F(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)\n#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8192F(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)\n\n#define GET_RX_BUFFER_DESC_OWN_8192F(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)\n#define GET_RX_BUFFER_DESC_LS_8192F(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)\n#define GET_RX_BUFFER_DESC_FS_8192F(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)\n#ifdef USING_RX_TAG\n\t#define GET_RX_BUFFER_DESC_RX_TAG_8192F(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13)\n#else\n\t#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8192F(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)\n#endif\n\n/*DWORD 1*/\n#define SET_RX_BUFFER_PHYSICAL_LOW_8192F(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)\n\n/*DWORD 2*/\n#ifdef CONFIG_64BIT_DMA\n\t#define SET_RX_BUFFER_PHYSICAL_HIGH_8192F(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)\n#else\n\t#define SET_RX_BUFFER_PHYSICAL_HIGH_8192F(__pRxStatusDesc, __Value)\n#endif\n\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\ts32 rtl8192fs_init_recv_priv(PADAPTER padapter);\n\tvoid rtl8192fs_free_recv_priv(PADAPTER padapter);\n\ts32 rtl8192fs_recv_hdl(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_USB_HCI\n\tint rtl8192fu_init_recv_priv(_adapter *padapter);\n\tvoid rtl8192fu_free_recv_priv(_adapter *padapter);\n\tvoid rtl8192fu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\ts32 rtl8192fe_init_recv_priv(_adapter *padapter);\n\tvoid rtl8192fe_free_recv_priv(_adapter *padapter);\n#endif\n\nvoid rtl8192f_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);\n\n#endif /* __RTL8192F_RECV_H__ */\n"
  },
  {
    "path": "include/rtl8192f_rf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2012 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8192F_RF_H__\n#define __RTL8192F_RF_H__\n\nint PHY_RF6052_Config8192F(PADAPTER pdapter);\n\nvoid PHY_RF6052SetBandwidth8192F(PADAPTER Adapter, enum channel_width Bandwidth);\n\n#endif/* __RTL8192F_RF_H__ */\n"
  },
  {
    "path": "include/rtl8192f_spec.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8192F_SPEC_H__\n#define __RTL8192F_SPEC_H__\n\n#include <drv_conf.h>\n\n\n#define HAL_NAV_UPPER_UNIT_8192F\t\t128\t\t/* micro-second */\n\n/* -----------------------------------------------------\n *\n *\t0x0000h ~ 0x00FFh\tSystem Configuration\n *\n * ----------------------------------------------------- */\n#define REG_SYS_ISO_CTRL_8192F\t\t\t0x0000\t/* 2 Byte */\n#define REG_SYS_FUNC_EN_8192F\t\t\t0x0002\t/* 2 Byte */\n#define REG_APS_FSMCO_8192F\t\t\t0x0004\t/* 4 Byte */\n#define REG_SYS_CLKR_8192F\t\t\t\t0x0008\t/* 2 Byte */\n#define REG_9346CR_8192F\t\t\t\t0x000A\t/* 2 Byte */\n#define REG_EE_VPD_8192F\t\t\t\t0x000C\t/* 2 Byte */\n#define REG_AFE_MISC_8192F\t\t\t\t0x0010\t/* 1 Byte */\n#define REG_SPS0_CTRL_8192F\t\t\t\t0x0011\t/* 7 Byte */\n#define REG_SPS_OCP_CFG_8192F\t\t\t0x0018\t/* 4 Byte */\n#define REG_RSV_CTRL_8192F\t\t\t\t0x001C\t/* 3 Byte */\n#define REG_RF_CTRL_8192F\t\t\t\t0x001F\t/* 1 Byte */\n#define REG_LPLDO_CTRL_8192F\t\t\t0x0023\t/* 1 Byte */\n#define REG_AFE_XTAL_CTRL_8192F\t\t0x0024\t/* 4 Byte */\n#define REG_AFE_PLL_CTRL_8192F\t\t\t0x0028\t/* 4 Byte */\n#define REG_MAC_PLL_CTRL_EXT_8192F\t\t0x002c\t/* 4 Byte */\n#define REG_EFUSE_CTRL_8192F\t\t\t0x0030\n#define REG_EFUSE_TEST_8192F\t\t\t0x0034\n#define REG_PWR_DATA_8192F\t\t\t\t0x0038\n#define REG_CAL_TIMER_8192F\t\t\t\t0x003C\n#define REG_ACLK_MON_8192F\t\t\t\t0x003E\n#define REG_GPIO_MUXCFG_8192F\t\t\t0x0040\n#define REG_GPIO_IO_SEL_8192F\t\t\t0x0042\n#define REG_MAC_PINMUX_CFG_8192F\t\t0x0043\n#define REG_GPIO_PIN_CTRL_8192F\t\t\t0x0044\n#define REG_GPIO_INTM_8192F\t\t\t\t0x0048\n#define REG_LEDCFG0_8192F\t\t\t\t0x004C\n#define REG_LEDCFG1_8192F\t\t\t\t0x004D\n#define REG_LEDCFG2_8192F\t\t\t\t0x004E\n#define REG_LEDCFG3_8192F\t\t\t\t0x004F\n#define REG_FSIMR_8192F\t\t\t\t\t0x0050\n#define REG_FSISR_8192F\t\t\t\t\t0x0054\n#define REG_HSIMR_8192F\t\t\t\t\t0x0058\n#define REG_HSISR_8192F\t\t\t\t\t0x005c\n#define REG_GPIO_EXT_CTRL\t\t\t\t0x0060\n#define REG_PAD_CTRL1_8192F\t\t0x0064\n#define REG_MULTI_FUNC_CTRL_8192F\t\t0x0068\n#define REG_GPIO_STATUS_8192F\t\t\t0x006C\n#define REG_SDIO_CTRL_8192F\t\t\t\t0x0070\n#define REG_OPT_CTRL_8192F\t\t\t\t0x0074\n#define REG_AFE_CTRL_4_8192F\t\t0x0078\n#define REG_MCUFWDL_8192F\t\t\t\t0x0080\n#define REG_8051FW_CTRL_8192F\t\t\t0x0080\n#define REG_HMEBOX_DBG_0_8192F\t0x0088\n#define REG_HMEBOX_DBG_1_8192F\t0x008A\n#define REG_HMEBOX_DBG_2_8192F\t0x008C\n#define REG_HMEBOX_DBG_3_8192F\t0x008E\n#define REG_WLLPS_CTRL\t\t0x0090\n#define REG_HIMR0_8192F\t\t\t\t\t0x00B0\n#define REG_HISR0_8192F\t\t\t\t0x00B4\n#define REG_HIMR1_8192F\t\t\t\t\t0x00B8\n#define REG_HISR1_8192F\t\t\t\t\t0x00BC\n#define REG_PMC_DBG_CTRL2_8192F\t\t\t0x00CC\n#define\tREG_EFUSE_BURN_GNT_8192F\t\t0x00CF\n#define REG_HPON_FSM_8192F\t\t\t\t0x00EC\n#define REG_SYS_CFG1_8192F\t\t\t\t0x00F0\n#define REG_SYS_CFG2_8192F\t\t\t\t0x00FC\n#define REG_ROM_VERSION\t\t\t\t\t0x00FD\n\n/* -----------------------------------------------------\n *\n *\t0x0100h ~ 0x01FFh\tMACTOP General Configuration\n *\n * ----------------------------------------------------- */\n#define REG_CR_8192F\t\t\t\t\t\t0x0100\n#define REG_PBP_8192F\t\t\t\t\t0x0104\n#define REG_PKT_BUFF_ACCESS_CTRL_8192F\t0x0106\n#define REG_TRXDMA_CTRL_8192F\t\t\t0x010C\n#define REG_TRXFF_BNDY_8192F\t\t\t0x0114\n#define REG_TRXFF_STATUS_8192F\t\t\t0x0118\n#define REG_RXFF_PTR_8192F\t\t\t\t0x011C\n#define REG_CPWM_8192F\t\t\t\t\t0x012C\n#define REG_FWIMR_8192F\t\t\t\t\t0x0130\n#define REG_FWISR_8192F\t\t\t\t\t0x0134\n#define REG_FTIMR_8192F\t\t\t\t\t0x0138\n#define REG_PKTBUF_DBG_CTRL_8192F\t\t0x0140\n#define REG_RXPKTBUF_CTRL_8192F\t\t0x0142\n#define REG_PKTBUF_DBG_DATA_L_8192F\t0x0144\n#define REG_PKTBUF_DBG_DATA_H_8192F\t0x0148\n\n#define REG_TC0_CTRL_8192F\t\t\t\t0x0150\n#define REG_TC1_CTRL_8192F\t\t\t\t0x0154\n#define REG_TC2_CTRL_8192F\t\t\t\t0x0158\n#define REG_TC3_CTRL_8192F\t\t\t\t0x015C\n#define REG_TC4_CTRL_8192F\t\t\t\t0x0160\n#define REG_TCUNIT_BASE_8192F\t\t\t0x0164\n#define REG_RSVD3_8192F\t\t\t\t\t0x0168\n#define REG_C2HEVT_CMD_ID_8192F\t0x01A0\n#define REG_C2HEVT_CMD_SEQ_88XX\t\t0x01A1\n#define REG_C2hEVT_CMD_CONTENT_88XX\t0x01A2\n#define REG_C2HEVT_CMD_LEN_8192F        0x01AE\n#define REG_C2HEVT_CLEAR_8192F\t\t\t0x01AF\n#define REG_MCUTST_1_8192F\t\t\t\t0x01C0\n#define REG_WOWLAN_WAKE_REASON 0x01C7\n#define REG_FMETHR_8192F\t\t\t\t0x01C8\n#define REG_HMETFR_8192F\t\t\t\t0x01CC\n#define REG_HMEBOX_0_8192F\t\t\t\t0x01D0\n#define REG_HMEBOX_1_8192F\t\t\t\t0x01D4\n#define REG_HMEBOX_2_8192F\t\t\t\t0x01D8\n#define REG_HMEBOX_3_8192F\t\t\t\t0x01DC\n#define REG_LLT_INIT_8192F\t\t\t\t0x01E0\n#define REG_HMEBOX_EXT0_8192F\t\t\t0x01F0\n#define REG_HMEBOX_EXT1_8192F\t\t\t0x01F4\n#define REG_HMEBOX_EXT2_8192F\t\t\t0x01F8\n#define REG_HMEBOX_EXT3_8192F\t\t\t0x01FC\n\n/* -----------------------------------------------------\n *\n *\t0x0200h ~ 0x027Fh\tTXDMA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_RQPN_8192F\t\t\t\t\t0x0200\n#define REG_FIFOPAGE_8192F\t\t\t\t0x0204\n#define REG_DWBCN0_CTRL_8192F\t\t\tREG_TDECTRL\n#define REG_TXDMA_OFFSET_CHK_8192F\t0x020C\n#define REG_TXDMA_STATUS_8192F\t\t0x0210\n#define REG_RQPN_NPQ_8192F\t\t\t0x0214\n#define REG_DWBCN1_CTRL_8192F\t\t\t0x0228\n#define REG_RQPN_EXQ1_EXQ2\t\t\t0x0230\n\n/* -----------------------------------------------------\n *\n *\t0x0280h ~ 0x02FFh\tRXDMA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_RXDMA_AGG_PG_TH_8192F\t\t0x0280\n#define REG_FW_UPD_RDPTR_8192F\t\t0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */\n#define REG_RXDMA_CONTROL_8192F\t\t0x0286 /* Control the RX DMA. */\n#define REG_RXDMA_STATUS_8192F\t\t\t0x0288\n#define REG_RXDMA_MODE_CTRL_8192F\t\t0x0290\n#define REG_EARLY_MODE_CONTROL_8192F\t0x02BC\n#define REG_RSVD5_8192F\t\t\t\t\t0x02F0\n#define REG_RSVD6_8192F\t\t\t\t\t0x02F4\n\n/* -----------------------------------------------------\n *\n *\t0x0300h ~ 0x03FFh\tPCIe\n *\n * ----------------------------------------------------- */\n#define\tREG_PCIE_CTRL_REG_8192F\t\t0x0300\n#define\tREG_INT_MIG_8192F\t\t\t\t0x0304\t/* Interrupt Migration */\n#define\tREG_BCNQ_TXBD_DESA_8192F\t\t0x0308\t/* TX Beacon Descriptor Address */\n#define\tREG_MGQ_TXBD_DESA_8192F\t\t\t0x0310\t/* TX Manage Queue Descriptor Address */\n#define\tREG_VOQ_TXBD_DESA_8192F\t\t\t0x0318\t/* TX VO Queue Descriptor Address */\n#define\tREG_VIQ_TXBD_DESA_8192F\t\t\t0x0320\t/* TX VI Queue Descriptor Address */\n#define\tREG_BEQ_TXBD_DESA_8192F\t\t\t0x0328\t/* TX BE Queue Descriptor Address */\n#define\tREG_BKQ_TXBD_DESA_8192F\t\t\t0x0330\t/* TX BK Queue Descriptor Address */\n#define\tREG_RXQ_RXBD_DESA_8192F\t\t\t0x0338\t/* RX Queue\tDescriptor Address */\n#define REG_HI0Q_TXBD_DESA_8192F\t\t0x0340\n#define REG_HI1Q_TXBD_DESA_8192F\t\t0x0348\n#define REG_HI2Q_TXBD_DESA_8192F\t\t0x0350\n#define REG_HI3Q_TXBD_DESA_8192F\t\t0x0358\n#define REG_HI4Q_TXBD_DESA_8192F\t\t0x0360\n#define REG_HI5Q_TXBD_DESA_8192F\t\t0x0368\n#define REG_HI6Q_TXBD_DESA_8192F\t\t0x0370\n#define REG_HI7Q_TXBD_DESA_8192F\t\t0x0378\n#define\tREG_MGQ_TXBD_NUM_8192F\t\t\t0x0380\n#define\tREG_RX_RXBD_NUM_8192F\t\t\t0x0382\n#define\tREG_VOQ_TXBD_NUM_8192F\t\t\t0x0384\n#define\tREG_VIQ_TXBD_NUM_8192F\t\t\t0x0386\n#define\tREG_BEQ_TXBD_NUM_8192F\t\t\t0x0388\n#define\tREG_BKQ_TXBD_NUM_8192F\t\t\t0x038A\n#define\tREG_HI0Q_TXBD_NUM_8192F\t\t\t0x038C\n#define\tREG_HI1Q_TXBD_NUM_8192F\t\t\t0x038E\n#define\tREG_HI2Q_TXBD_NUM_8192F\t\t\t0x0390\n#define\tREG_HI3Q_TXBD_NUM_8192F\t\t\t0x0392\n#define\tREG_HI4Q_TXBD_NUM_8192F\t\t\t0x0394\n#define\tREG_HI5Q_TXBD_NUM_8192F\t\t\t0x0396\n#define\tREG_HI6Q_TXBD_NUM_8192F\t\t\t0x0398\n#define\tREG_HI7Q_TXBD_NUM_8192F\t\t\t0x039A\n#define\tREG_TSFTIMER_HCI_8192F\t\t\t0x039C\n#define\tREG_BD_RW_PTR_CLR_8192F\t\t\t0x039C\n\n/* Read Write Point */\n#define\tREG_VOQ_TXBD_IDX_8192F\t\t\t0x03A0\n#define\tREG_VIQ_TXBD_IDX_8192F\t\t\t0x03A4\n#define\tREG_BEQ_TXBD_IDX_8192F\t\t\t0x03A8\n#define\tREG_BKQ_TXBD_IDX_8192F\t\t\t0x03AC\n#define\tREG_MGQ_TXBD_IDX_8192F\t\t\t0x03B0\n#define\tREG_RXQ_TXBD_IDX_8192F\t\t\t0x03B4\n#define\tREG_HI0Q_TXBD_IDX_8192F\t\t\t0x03B8\n#define\tREG_HI1Q_TXBD_IDX_8192F\t\t\t0x03BC\n#define\tREG_HI2Q_TXBD_IDX_8192F\t\t\t0x03C0\n#define\tREG_HI3Q_TXBD_IDX_8192F\t\t\t0x03C4\n#define\tREG_HI4Q_TXBD_IDX_8192F\t\t\t0x03C8\n#define\tREG_HI5Q_TXBD_IDX_8192F\t\t\t0x03CC\n#define\tREG_HI6Q_TXBD_IDX_8192F\t\t\t0x03D0\n#define\tREG_HI7Q_TXBD_IDX_8192F\t\t\t0x03D4\n#define\tREG_DBI_WDATA_V1_8192F\t\t\t0x03E8\n#define\tREG_DBI_RDATA_V1_8192F\t\t\t0x03EC\n#define\tREG_DBI_FLAG_V1_8192F\t\t\t0x03F0\n#define REG_MDIO_V1_8192F\t\t\t0x03F4\n#define REG_HCI_MIX_CFG_8192F\t\t\t0x03FC\n#define REG_PCIE_HCPWM_8192FE\t\t\t\t0x03D8\n#define REG_PCIE_HRPWM_8192FE\t\t\t\t0x03DC\n#define REG_PCIE_MIX_CFG_8192F\t\t\t\t0x03F8\n\n/* -----------------------------------------------------\n *\n *\t0x0400h ~ 0x047Fh\tProtocol Configuration\n *\n * ----------------------------------------------------- */\n#define REG_QUEUELIST_INFO0_8192F\t\t0x0400\n#define REG_QUEUELIST_INFO1_8192F\t\t0x0404\n#define REG_QUEUELIST_INFO2_8192F\t\t0x0414\n#define REG_TXPKT_EMPTY_8192F\t\t\t0x0418\n\n#define REG_FWHW_TXQ_CTRL_8192F\t\t0x0420\n#define REG_HWSEQ_CTRL_8192F\t\t\t0x0423\n#define REG_TXPKTBUF_BCNQ_BDNY_8192F\t0x0424\n#define REG_TXPKTBUF_MGQ_BDNY_8192F\t0x0425\n#define REG_LIFECTRL_CTRL_8192F\t\t\t0x0426\n#define REG_MULTI_BCNQ_OFFSET_8192F\t0x0427\n#define REG_SPEC_SIFS_8192F\t\t\t\t0x0428\n#define REG_RL_8192F\t\t\t\t\t\t0x042A\n#define REG_TXBF_CTRL_8192F\t\t\t\t0x042C\n#define REG_DARFRC_8192F\t\t\t\t0x0430\n#define REG_RARFRC_8192F\t\t\t\t0x0438\n#define REG_RRSR_8192F\t\t\t\t\t0x0440\n#define REG_ARFR0_8192F\t\t\t\t\t0x0444\n#define REG_ARFR1_8192F\t\t\t\t\t0x044C\n#define REG_CCK_CHECK_8192F\t\t\t\t0x0454\n#define REG_AMPDU_MAX_TIME_8192F\t\t0x0456\n#define REG_TXPKTBUF_BCNQ_BDNY1_8192F\t0x0457\n\n#define REG_AMPDU_MAX_LENGTH_8192F\t0x0458\n#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8192F\t0x045D\n#define REG_NDPA_OPT_CTRL_8192F\t\t0x045F\n#define REG_FAST_EDCA_CTRL_8192F\t\t0x0460\n#define REG_RD_RESP_PKT_TH_8192F\t\t0x0463\n#define REG_DATA_SC_8192F\t\t\t\t0x0483\n#define REG_TXRPT_START_OFFSET\t\t0x04AC\n#define REG_POWER_STAGE1_8192F\t\t0x04B4\n#define REG_POWER_STAGE2_8192F\t\t0x04B8\n#define REG_AMPDU_BURST_MODE_8192F\t0x04BC\n#define REG_PKT_VO_VI_LIFE_TIME_8192F\t0x04C0\n#define REG_PKT_BE_BK_LIFE_TIME_8192F\t0x04C2\n#define REG_STBC_SETTING_8192F\t\t\t0x04C4\n#define REG_HT_SINGLE_AMPDU_8192F\t\t0x04C7\n#define REG_PROT_MODE_CTRL_8192F\t\t0x04C8\n#define REG_MAX_AGGR_NUM_8192F\t\t0x04CA\n#define REG_RTS_MAX_AGGR_NUM_8192F\t0x04CB\n#define REG_BAR_MODE_CTRL_8192F\t\t0x04CC\n#define REG_RA_TRY_RATE_AGG_LMT_8192F\t0x04CF\n#define REG_MACID_PKT_DROP0_8192F\t\t0x04D0\n#define REG_MACID_PKT_SLEEP_8192F\t\t0x04D4\n#define REG_PRECNT_CTRL_8192F\t\t\t0x04E5\n/* -----------------------------------------------------\n *\n *\t0x0500h ~ 0x05FFh\tEDCA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_EDCA_VO_PARAM_8192F\t\t0x0500\n#define REG_EDCA_VI_PARAM_8192F\t\t0x0504\n#define REG_EDCA_BE_PARAM_8192F\t\t0x0508\n#define REG_EDCA_BK_PARAM_8192F\t\t0x050C\n#define REG_BCNTCFG_8192F\t\t\t\t0x0510\n#define REG_PIFS_8192F\t\t\t\t\t0x0512\n#define REG_RDG_PIFS_8192F\t\t\t\t0x0513\n#define REG_SIFS_CTX_8192F\t\t\t\t0x0514\n#define REG_SIFS_TRX_8192F\t\t\t\t0x0516\n#define REG_AGGR_BREAK_TIME_8192F\t\t0x051A\n#define REG_SLOT_8192F\t\t\t\t\t0x051B\n#define REG_TX_PTCL_CTRL_8192F\t\t\t0x0520\n#define REG_TXPAUSE_8192F\t\t\t\t0x0522\n#define REG_DIS_TXREQ_CLR_8192F\t\t0x0523\n#define REG_RD_CTRL_8192F\t\t\t\t0x0524\n/*\n * Format for offset 540h-542h:\n *\t[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.\n *\t[7:4]:   Reserved.\n *\t[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.\n *\t[23:20]: Reserved\n * Description:\n *\t              |\n * |<--Setup--|--Hold------------>|\n *\t--------------|----------------------\n * |\n * TBTT\n * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.\n * Described by Designer Tim and Bruce, 2011-01-14.\n *   */\n#define REG_TBTT_PROHIBIT_8192F\t\t\t0x0540\n#define REG_RD_NAV_NXT_8192F\t\t\t0x0544\n#define REG_NAV_PROT_LEN_8192F\t\t\t0x0546\n#define REG_BCN_CTRL_8192F\t\t\t\t0x0550\n#define REG_BCN_CTRL_1_8192F\t\t\t0x0551\n#define REG_MBID_NUM_8192F\t\t\t\t0x0552\n#define REG_DUAL_TSF_RST_8192F\t\t\t0x0553\n#define REG_BCN_INTERVAL_8192F\t\t\t0x0554\n#define REG_DRVERLYINT_8192F\t\t\t0x0558\n#define REG_BCNDMATIM_8192F\t\t\t0x0559\n#define REG_ATIMWND_8192F\t\t\t\t0x055A\n#define REG_USTIME_TSF_8192F\t\t\t0x055C\n#define REG_BCN_MAX_ERR_8192F\t\t\t0x055D\n#define REG_RXTSF_OFFSET_CCK_8192F\t\t0x055E\n#define REG_RXTSF_OFFSET_OFDM_8192F\t0x055F\t\n#define REG_TSFTR_8192F\t\t\t\t\t0x0560\n#define REG_CTWND_8192F\t\t\t\t\t0x0572\n#define REG_SECONDARY_CCA_CTRL_8192F\t0x0577\n#define REG_PSTIMER_8192F\t\t\t\t0x0580\n#define REG_TIMER0_8192F\t\t\t\t0x0584\n#define REG_TIMER1_8192F\t\t\t\t0x0588\n#define REG_ACMHWCTRL_8192F\t\t\t0x05C0\n#define REG_SCH_TXCMD_8192F\t\t\t0x05F8\n\n/* -----------------------------------------------------\n *\n *\t0x0600h ~ 0x07FFh\tWMAC Configuration\n *\n * ----------------------------------------------------- */\n#define REG_MAC_CR_8192F\t\t\t\t0x0600\n#define REG_TCR_8192F\t\t\t\t\t0x0604\n#define REG_RCR_8192F\t\t\t\t\t0x0608\n#define REG_RX_PKT_LIMIT_8192F\t\t\t0x060C\n#define REG_RX_DLK_TIME_8192F\t\t\t0x060D\n#define REG_RX_DRVINFO_SZ_8192F\t0x060F\n\n#define REG_MACID_8192F\t\t\t\t\t0x0610\n#define REG_BSSID_8192F\t\t\t\t\t0x0618\n#define REG_MAR_8192F\t\t\t\t\t0x0620\n#define REG_MBIDCAMCFG_8192F\t\t\t0x0628\n\n\n#define REG_USTIME_EDCA_8192F\t\t\t0x0638\n#define REG_MAC_SPEC_SIFS_8192F\t\t0x063A\n#define REG_RESP_SIFP_CCK_8192F\t\t\t0x063C\n#define REG_RESP_SIFS_OFDM_8192F\t\t0x063E\n#define REG_ACKTO_8192F\t\t\t\t\t0x0640\n#define REG_CTS2TO_8192F\t\t\t\t0x0641\n#define REG_EIFS_8192F\t\t\t\t\t0x0642\n\n#define REG_NAV_UPPER_8192F\t\t\t0x0652\t/* unit of 128*/\n#define REG_TRXPTCL_CTL_8192F\t\t\t0x0668\n\n/* Security*/\n#define REG_CAMCMD_8192F\t\t\t\t0x0670\n#define REG_CAMWRITE_8192F\t\t\t\t0x0674\n#define REG_CAMREAD_8192F\t\t\t\t0x0678\n#define REG_CAMDBG_8192F\t\t\t\t0x067C\n#define REG_SECCFG_8192F\t\t\t\t0x0680\n\n/* Power */\n#define REG_WOW_CTRL_8192F\t\t\t\t0x0690\n#define REG_PS_RX_INFO_8192F\t\t\t0x0692\n#define REG_UAPSD_TID_8192F\t\t\t\t0x0693\n#define REG_WKFMCAM_CMD_8192F\t\t\t0x0698\n#define REG_WKFMCAM_NUM_8192F\t\t\t0x0698\n#define REG_WKFMCAM_RWD_8192F\t\t\t0x069C\n#define REG_RXFLTMAP0_8192F\t\t\t\t0x06A0\n#define REG_RXFLTMAP1_8192F\t\t\t\t0x06A2\n#define REG_RXFLTMAP2_8192F\t\t\t\t0x06A4\n#define REG_BCN_PSR_RPT_8192F\t\t\t0x06A8\n#define REG_BT_COEX_TABLE_8192F\t\t0x06C0\n#define REG_BFMER0_INFO_8192F\t\t\t0x06E4\n#define REG_BFMER1_INFO_8192F\t\t\t0x06EC\n#define REG_CSI_RPT_PARAM_BW20_8192F\t0x06F4\n#define REG_CSI_RPT_PARAM_BW40_8192F\t0x06F8\n#define REG_CSI_RPT_PARAM_BW80_8192F\t0x06FC\n\n/* Hardware Port 2 */\n#define REG_MACID1_8192F\t\t\t\t0x0700\n#define REG_BSSID1_8192F\t\t\t\t0x0708\n#define REG_BFMEE_SEL_8192F\t\t\t\t0x0714\n#define REG_SND_PTCL_CTRL_8192F\t\t0x0718\n\n/* LTR */\n#define REG_LTR_CTRL_BASIC_8192F\t\t0x07A4\n#define REG_LTR_IDLE_LATENCY_V1_8192F\t\t0x0798\n#define REG_LTR_ACTIVE_LATENCY_V1_8192F\t0x079C\n\n/* GPIO Control */\n#define REG_SW_GPIO_SHARE_CTRL_8192F\t0x1038\n#define REG_SW_GPIO_A_OUT_8192F\t\t\t0x1040\n#define REG_SW_GPIO_A_OEN_8192F\t\t\t0x1044\n\n/* ************************************************************\n * SDIO Bus Specification\n * ************************************************************ */\n\n/* -----------------------------------------------------\n * SDIO CMD Address Mapping\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n * I/O bus domain (Host)\n * ----------------------------------------------------- */\n/*SDIO Host Interrupt Mask Register */\n#define SDIO_HIMR_CRCERR_MSK\t\t\tBIT(31)\n/* SDIO Host Interrupt Service Routine */\n#define SDIO_HISR_HEISR_IND_INT\t\tBIT(28)\n#define SDIO_HISR_HSISR2_IND_INT\t\tBIT(29)\n#define SDIO_HISR_HSISR3_IND_INT\t\tBIT(30)\n#define SDIO_HISR_SDIO_CRCERR\t\t\tBIT(31)\n/* -----------------------------------------------------\n * SDIO register\n * ----------------------------------------------------- */\n#define SDIO_REG_HCPWM1_8192F\t0x038/* HCI Current Power Mode 1 */\n#define SDIO_REG_FREE_TXPG1_8192F\t\t0x0020 /* Free Tx Buffer Page1*/\n#define SDIO_REG_FREE_TXPG2_8192F\t\t0x0024 /* Free Tx Buffer Page1*/\n#define SDIO_REG_FREE_TXPG3_8192F\t\t0x0028\n#define SDIO_REG_AC_OQT_FREEPG_8192F\t\t0x002A\n#define SDIO_REG_NOAC_OQT_FREEPG_8192F\t\t0x002B\n/* ****************************************************************************\n *\t8192F Regsiter Bit and Content definition\n * **************************************************************************** */\n\n#define BIT_USB_RXDMA_AGG_EN\tBIT(31)\n#define RXDMA_AGG_MODE_EN\t\tBIT(1)\n\n#ifdef CONFIG_WOWLAN\n\t#define RXPKT_RELEASE_POLL\t\tBIT(16)\n\t#define RXDMA_IDLE\t\t\t\tBIT(17)\n\t#define RW_RELEASE_EN\t\t\tBIT(18)\n#endif\n\n#ifdef CONFIG_AMPDU_PRETX_CD\n/*#define BIT_ERRORHDL_INT\t\t\tBIT(2)*/\n/*#define BIT_MACTX_ERR_3\t\t\tBIT(4)*/\n#define BIT_PRE_TX_CMD_8192F\t\tBIT(6)\n#define BIT_EN_PRECNT_8192F\t\tBIT(11)\n#endif\n/* SDIO Host Interrupt Service Routine */\n#define SDIO_HISR_HEISR_IND_INT\tBIT(28)\n#define SDIO_HISR_HSISR2_IND_INT\tBIT(29)\n#define SDIO_HISR_HSISR3_IND_INT\tBIT(30)\n#define SDIO_HISR_SDIO_CRCERR\t\tBIT(31)\n\n/* PCIE Host Interrupt Mask Register (HIMR) */\n#ifdef CONFIG_PCI_HCI\n/* ----------------------------------------------------------------------------\n *   * 8192F IMR/ISR bits\t\t\t\t\t\t\t(offset 0xB0,  8bits)\n *     * ---------------------------------------------------------------------------- */\n\n#define IMR_DISABLED_8192F\t\t\t\t\t0\n/* IMR DW0(0x00B0-00B3) Bit 0-31 */\n#define IMR_TIMER2_8192F\t\t\t\t\tBIT(31)         /* Timeout interrupt 2 */\n#define IMR_TIMER1_8192F\t\t\t\t\tBIT(30)\t\t/* Timeout interrupt 1 */\n#define IMR_PSTIMEOUT_8192F\t\t\t\tBIT(29)\t\t/* Power Save Time Out Interrupt */\n#define IMR_GTINT4_8192F\t\t\t\t\tBIT(28)\t\t/* When GTIMER4 expires, this bit is set to 1 */\n#define IMR_GTINT3_8192F\t\t\t\t\tBIT(27)\t\t/* When GTIMER3 expires, this bit is set to 1 */\n#define IMR_TXBCN0ERR_8192F\t\t\t\tBIT(26)\t\t/* Transmit Beacon0 Error */\n#define IMR_TXBCN0OK_8192F\t\t\t\tBIT(25)\t\t/* Transmit Beacon0 OK */\n#define IMR_TSF_BIT32_TOGGLE_8192F\t\tBIT(24)\t\t/* TSF Timer BIT32 toggle indication interrupt */\n#define IMR_BCNDMAINT0_8192F\t\t\t\tBIT(20)\t\t/* Beacon DMA Interrupt 0 */\n#define IMR_BCNDERR0_8192F\t\t\t\tBIT(16)\t\t/* Beacon Queue DMA OK0 */\n#define IMR_HSISR_IND_ON_INT_8192F\t\tBIT(15)\t\t/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */\n#define IMR_BCNDMAINT_E_8192F\t\t\t\tBIT(14)\t\t/* Beacon DMA Interrupt Extension for Win7 */\n#define IMR_ATIMEND_8192F\t\t\t\t\tBIT(12)         /* CTWidnow End or ATIM Window End */\n#define IMR_C2HCMD_8192F\t\t\t\t\tBIT(10)\t\t/* CPU to Host Command INT status, Write 1 clear */\n#define IMR_CPWM2_8192F\t\t\t\t\tBIT(9)          /* CPU power mode exchange INT status, Write 1 clear */\n#define IMR_CPWM_8192F\t\t\t\t\t\tBIT(8)\t\t/* CPU power mode exchange INT status, Write 1 clear */\n#define IMR_HIGHDOK_8192F\t\t\t\t\tBIT(7)\t\t/* High Queue DMA OK */\n#define IMR_MGNTDOK_8192F\t\t\t\t\tBIT(6)\t\t/* Management Queue DMA OK */\n#define IMR_BKDOK_8192F\t\t\t\t\tBIT(5)\t\t/* AC_BK DMA OK */\n#define IMR_BEDOK_8192F\t\t\t\t\tBIT(4)\t\t/* AC_BE DMA OK */\n#define IMR_VIDOK_8192F\t\t\t\t\tBIT(3)\t\t/* AC_VI DMA OK */\n#define IMR_VODOK_8192F\t\t\t\t\tBIT(2)\t\t/* AC_VO DMA OK */\n#define IMR_RDU_8192F\t\t\t\t\t\tBIT(1)\t\t/* Rx Descriptor Unavailable */\n#define IMR_ROK_8192F\t\t\t\t\t\tBIT(0)\t\t/* Receive DMA OK */\n\n/* IMR DW1(0x00B4-00B7) Bit 0-31 */\n#define IMR_MCUERR_8192F\t\t\t\t\tBIT(28)\n#define IMR_BCNDMAINT7_8192F\t\t\t\tBIT(27) \t\t/* Beacon DMA Interrupt 7 */\n#define IMR_BCNDMAINT6_8192F\t\t\t\tBIT(26)\t\t/* Beacon DMA Interrupt 6 */\n#define IMR_BCNDMAINT5_8192F\t\t\t\tBIT(25)\t\t/* Beacon DMA Interrupt 5 */\n#define IMR_BCNDMAINT4_8192F\t\t\t\tBIT(24)\t\t/* Beacon DMA Interrupt 4 */\n#define IMR_BCNDMAINT3_8192F\t\t\t\tBIT(23)\t\t/* Beacon DMA Interrupt 3 */\n#define IMR_BCNDMAINT2_8192F\t\t\t\tBIT(22)\t\t/* Beacon DMA Interrupt 2 */\n#define IMR_BCNDMAINT1_8192F \t\t\t\tBIT(21)\t\t/* Beacon DMA Interrupt 1 */\n#define IMR_BCNDOK7_8192F \t\t\t\t\tBIT(20)\t\t/* Beacon Queue DMA OK Interrup 7 */\n#define IMR_BCNDOK6_8192F\t\t\t\t\tBIT(19) \t\t/* Beacon Queue DMA OK Interrup 6 */\n#define IMR_BCNDOK5_8192F\t\t\t\t\tBIT(18)\t\t/* Beacon Queue DMA OK Interrup 5 */\n#define IMR_BCNDOK4_8192F\t\t\t\t\tBIT(17)\t\t/* Beacon Queue DMA OK Interrup 4 */\n#define IMR_BCNDOK3_8192F\t\t\t\t\tBIT(16)\t\t/* Beacon Queue DMA OK Interrup 3 */\n#define IMR_BCNDOK2_8192F\t\t\t\t\tBIT(15)\t\t/* Beacon Queue DMA OK Interrup 2 */\n#define IMR_BCNDOK1_8192F\t\t\t\t\tBIT(14)\t\t/* Beacon Queue DMA OK Interrup 1 */\n#define IMR_ATIMEND_E_8192F\t\t\t\tBIT(13)\t\t/* ATIM Window End Extension for Win7 */\n#define IMR_TXERR_8192F\t\t\t\t\tBIT(11)\t\t/* Tx Error Flag Interrupt status, write 1 clear. */\n#define IMR_RXERR_8192F\t\t\t\t\tBIT(10)\t\t/* Rx Error Flag INT status, Write 1 clear */\n#define IMR_TXFOVW_8192F\t\t\t\t\tBIT(9)\t\t/* Transmit FIFO Overflow */\n#define IMR_RXFOVW_8192F \t\t\t\t\tBIT(8)\t\t/* Receive FIFO Overflow */\n\n/* #define IMR_RX_MASK\t\t\t(IMR_ROK_8192F|IMR_RDU_8192F|IMR_RXFOVW_8192F) */\n#define IMR_TX_MASK\t\t\t(IMR_VODOK_8192F | IMR_VIDOK_8192F | IMR_BEDOK_8192F | IMR_BKDOK_8192F | IMR_MGNTDOK_8192F | IMR_HIGHDOK_8192F)\n#define RT_BCN_INT_MASKS\t\t(IMR_BCNDMAINT0_8192F | IMR_TXBCN0OK_8192F | IMR_TXBCN0ERR_8192F | IMR_BCNDERR0_8192F)\n#define RT_AC_INT_MASKS\t\t(IMR_VIDOK_8192F | IMR_VODOK_8192F | IMR_BEDOK_8192F | IMR_BKDOK_8192F)\n#endif /* CONFIG_PCI_HCI */\n\n/* 2 HSISR\n * interrupt mask which needs to clear */\n#define MASK_HSISR_CLEAR\t\t(HSISR_GPIO12_0_INT |\\\n\t\tHSISR_SPS_OCP_INT |\\\n\t\tHSISR_RON_INT |\\\n\t\tHSISR_PDNINT |\\\n\t\tHSISR_GPIO9_INT)\n\n#define _TXDMA_HIQ_MAP_8192F(x)\t\t\t(((x) & 0x7) << 19)\n#define _TXDMA_MGQ_MAP_8192F(x)\t\t\t(((x) & 0x7) << 16)\n#define _TXDMA_BKQ_MAP_8192F(x)\t\t\t(((x) & 0x7) << 13)\n#define _TXDMA_BEQ_MAP_8192F(x)\t\t\t(((x) & 0x7) << 10)\n#define _TXDMA_VIQ_MAP_8192F(x)\t\t\t(((x) & 0x7) << 7)\n#define _TXDMA_VOQ_MAP_8192F(x)\t\t\t(((x) & 0x7) << 4)\n\n/*mac queue info*/\n#define QUEUE_TOTAL_NUM\t20/*reg414h : 0~f ac queue 0x10~0x13MGQ HIQ BCNQ CMDQ*/\n#define QUEUE_ACQ_NUM\t\t16 \n#define QUEUE_INDEX_MGQ\t\t0x10\n#define QUEUE_INDEX_HIQ\t\t0x11\n#define QUEUE_INDEX_BCNQ\t0x12\n#define QUEUE_INDEX_CMDQ\t0x13\n#endif /* __RTL8192F_SPEC_H__ */\n"
  },
  {
    "path": "include/rtl8192f_sreset.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8192F_SRESET_H_\n#define _RTL8192F_SRESET_H_\n\n#include <rtw_sreset.h>\n\n#ifdef DBG_CONFIG_ERROR_DETECT\n\textern void rtl8192f_sreset_xmit_status_check(_adapter *padapter);\n\textern void rtl8192f_sreset_linked_status_check(_adapter *padapter);\n#endif /* DBG_CONFIG_ERROR_DETECT */\n#endif /* _RTL8192F_SRESET_H_ */"
  },
  {
    "path": "include/rtl8192f_xmit.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8192F_XMIT_H__\n#define __RTL8192F_XMIT_H__\n\n\n#define MAX_TID (15)\n\n\n#ifndef __INC_HAL8192FDESC_H\n#define __INC_HAL8192FDESC_H\n\n#define RX_STATUS_DESC_SIZE_8192F\t\t24\n#define RX_DRV_INFO_SIZE_UNIT_8192F \t8\n\n\n/* DWORD 0 */\n#define SET_RX_STATUS_DESC_PKT_LEN_8192F(__pRxStatusDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)\n#define SET_RX_STATUS_DESC_EOR_8192F(__pRxStatusDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)\n#define SET_RX_STATUS_DESC_OWN_8192F(__pRxStatusDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)\n\n#define GET_RX_STATUS_DESC_PKT_LEN_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)\n#define GET_RX_STATUS_DESC_CRC32_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)\n#define GET_RX_STATUS_DESC_ICV_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)\n#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)\n#define GET_RX_STATUS_DESC_SECURITY_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)\n#define GET_RX_STATUS_DESC_QOS_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)\n#define GET_RX_STATUS_DESC_SHIFT_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)\n#define GET_RX_STATUS_DESC_PHY_STATUS_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)\n#define GET_RX_STATUS_DESC_SWDEC_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)\n#define GET_RX_STATUS_DESC_EOR_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)\n#define GET_RX_STATUS_DESC_OWN_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)\n\n/* DWORD 1 */\n#define GET_RX_STATUS_DESC_MACID_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)\n#define GET_RX_STATUS_DESC_TID_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)\n#define GET_RX_STATUS_DESC_AMSDU_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)\n#define GET_RX_STATUS_DESC_RXID_MATCH_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)\n#define GET_RX_STATUS_DESC_PAGGR_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)\n#define GET_RX_STATUS_DESC_A1_FIT_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)\n#define GET_RX_STATUS_DESC_CHKERR_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)\n#define GET_RX_STATUS_DESC_IPVER_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)\n#define GET_RX_STATUS_DESC_IS_TCPUDP__8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)\n#define GET_RX_STATUS_DESC_CHK_VLD_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)\n#define GET_RX_STATUS_DESC_PAM_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)\n#define GET_RX_STATUS_DESC_PWR_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)\n#define GET_RX_STATUS_DESC_MORE_DATA_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)\n#define GET_RX_STATUS_DESC_MORE_FRAG_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)\n#define GET_RX_STATUS_DESC_TYPE_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)\n#define GET_RX_STATUS_DESC_MC_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)\n#define GET_RX_STATUS_DESC_BC_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)\n\n/* DWORD 2 */\n#define GET_RX_STATUS_DESC_SEQ_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)\n#define GET_RX_STATUS_DESC_FRAG_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)\n#define GET_RX_STATUS_DESC_RX_IS_QOS_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)\n#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)\n#define GET_RX_STATUS_DESC_RPT_SEL_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)\n#define GET_RX_STATUS_DESC_FCS_OK_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)\n\n/* DWORD 3 */\n#define GET_RX_STATUS_DESC_RX_RATE_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)\n#define GET_RX_STATUS_DESC_HTC_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)\n#define GET_RX_STATUS_DESC_EOSP_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)\n#define GET_RX_STATUS_DESC_BSSID_FIT_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)\n#ifdef CONFIG_USB_RX_AGGREGATION\n#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)\n#endif\n#define GET_RX_STATUS_DESC_PATTERN_MATCH_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)\n#define GET_RX_STATUS_DESC_UNICAST_MATCH_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)\n#define GET_RX_STATUS_DESC_MAGIC_MATCH_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)\n\n/* DWORD 6 */\n#define GET_RX_STATUS_DESC_MATCH_ID_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7)\n\n/* DWORD 5 */\n#define GET_RX_STATUS_DESC_TSFL_8192F(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)\n\n#define GET_RX_STATUS_DESC_BUFF_ADDR64_8192F(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)\n\n\n\n/* Dword 0, rsvd: bit26, bit28 */\n#define GET_TX_DESC_OWN_8192F(__pTxDesc)\\\n\tLE_BITS_TO_4BYTE(__pTxDesc, 31, 1)\n\n#define SET_TX_DESC_PKT_SIZE_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)\n#define SET_TX_DESC_OFFSET_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)\n#define SET_TX_DESC_BMC_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)\n#define SET_TX_DESC_HTC_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)\n#define SET_TX_DESC_AMSDU_PAD_EN_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)\n#define SET_TX_DESC_NO_ACM_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)\n#define SET_TX_DESC_GF_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)\n\n/* Dword 1 */\n#define SET_TX_DESC_MACID_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)\n#define SET_TX_DESC_QUEUE_SEL_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)\n#define SET_TX_DESC_RDG_NAV_EXT_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)\n#define SET_TX_DESC_LSIG_TXOP_EN_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)\n#define SET_TX_DESC_PIFS_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)\n#define SET_TX_DESC_RATE_ID_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)\n#define SET_TX_DESC_EN_DESC_ID_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)\n#define SET_TX_DESC_SEC_TYPE_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)\n#define SET_TX_DESC_PKT_OFFSET_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)\n#define SET_TX_DESC_MORE_DATA_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)\n\n/* Dword 2 ADD HW_DIG*/\n#define SET_TX_DESC_PAID_92F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value)\n#define SET_TX_DESC_CCA_RTS_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)\n#define SET_TX_DESC_AGG_ENABLE_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)\n#define SET_TX_DESC_RDG_ENABLE_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)\n#define SET_TX_DESC_NULL0_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)\n#define SET_TX_DESC_NULL1_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)\n#define SET_TX_DESC_BK_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)\n#define SET_TX_DESC_MORE_FRAG_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)\n#define SET_TX_DESC_RAW_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)\n#define SET_TX_DESC_CCX_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)\n#define SET_TX_DESC_AMPDU_DENSITY_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)\n#define SET_TX_DESC_BT_INT_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)\n#define SET_TX_DESC_HW_DIG_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 7, __Value)\n\n/* Dword 3 */\n#define SET_TX_DESC_HWSEQ_SEL_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)\n#define SET_TX_DESC_USE_RATE_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)\n#define SET_TX_DESC_DISABLE_RTS_FB_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)\n#define SET_TX_DESC_DISABLE_FB_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)\n#define SET_TX_DESC_CTS2SELF_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)\n#define SET_TX_DESC_RTS_ENABLE_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)\n#define SET_TX_DESC_HW_RTS_ENABLE_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)\n#define SET_TX_DESC_CHK_EN_92F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value)\n#define SET_TX_DESC_NAV_USE_HDR_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)\n#define SET_TX_DESC_USE_MAX_LEN_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)\n#define SET_TX_DESC_MAX_AGG_NUM_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)\n#define SET_TX_DESC_NDPA_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)\n#define SET_TX_DESC_AMPDU_MAX_TIME_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)\n\n/* Dword 4 */\n#define SET_TX_DESC_TX_RATE_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)\n#define SET_TX_DESC_TX_TRY_RATE_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)\n#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)\n#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)\n#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)\n#define SET_TX_DESC_DATA_RETRY_LIMIT_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)\n#define SET_TX_DESC_RTS_RATE_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)\n#define SET_TX_DESC_PCTS_EN_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)\n#define SET_TX_DESC_PCTS_MASK_IDX_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)\n\n/* Dword 5 */\n#define SET_TX_DESC_DATA_SC_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)\n#define SET_TX_DESC_DATA_SHORT_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)\n#define SET_TX_DESC_DATA_BW_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)\n#define SET_TX_DESC_DATA_LDPC_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)\n#define SET_TX_DESC_DATA_STBC_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)\n#define SET_TX_DESC_RTS_STBC_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)\n#define SET_TX_DESC_RTS_SHORT_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)\n#define SET_TX_DESC_RTS_SC_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)\n#define SET_TX_DESC_PORT_ID_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 21, 1, __Value)\n#define SET_TX_DESC_DROP_ID_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 22, 2, __Value)\n#define SET_TX_DESC_PATH_A_EN_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value)\n#define SET_TX_DESC_PATH_B_EN_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 25, 1, __Value)\n#define SET_TX_DESC_TXPWR_OF_SET_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)\n\n/* Dword 6 */\n#define SET_TX_DESC_SW_DEFINE_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)\n#define SET_TX_DESC_MBSSID_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)\n#define SET_TX_DESC_RF_SEL_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)\n\n/* Dword 7 */\n#ifdef CONFIG_PCI_HCI\n#define SET_TX_DESC_TX_BUFFER_SIZE_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n#endif\n\n#ifdef CONFIG_USB_HCI\n#define SET_TX_DESC_TX_DESC_CHECKSUM_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n#endif\n\n#ifdef CONFIG_SDIO_HCI\n#define SET_TX_DESC_TX_TIMESTAMP_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)\n#endif\n\n#define SET_TX_DESC_USB_TXAGG_NUM_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)\n\n/* Dword 8 */\n#define SET_TX_DESC_RTS_RC_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)\n#define SET_TX_DESC_BAR_RC_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)\n#define SET_TX_DESC_DATA_RC_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)\n#define SET_TX_DESC_HWSEQ_EN_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)\n#define SET_TX_DESC_NEXTHEADPAGE_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)\n#define SET_TX_DESC_TAILPAGE_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)\n\n/* Dword 9 */\n#define SET_TX_DESC_PADDING_LEN_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)\n#define SET_TX_DESC_SEQ_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)\n#define SET_TX_DESC_FINAL_DATA_RATE_8192F(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)\n\n\n#define SET_EARLYMODE_PKTNUM_8192F(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)\n#define SET_EARLYMODE_LEN0_8192F(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)\n#define SET_EARLYMODE_LEN1_1_8192F(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)\n#define SET_EARLYMODE_LEN1_2_8192F(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)\n#define SET_EARLYMODE_LEN2_8192F(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,\t__Value)\n#define SET_EARLYMODE_LEN3_8192F(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)\n\n\n/*-----------------------------------------------------------------*/\n/*\tRTL8192F TX BUFFER DESC                                      */\n/*-----------------------------------------------------------------*/\n#ifdef CONFIG_64BIT_DMA\n\t#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)\n\t#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)\n\t#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)\n\t#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)\n#else\n\t#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)\n\t#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)\n\t#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)\n\t#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu)\t/* 64 BIT mode only */\n#endif\n/* ********************************************************* */\n\n/* 64 bits  -- 32 bits */\n/* =======     ======= */\n/* Dword 0     0 */\n#define SET_TX_BUFF_DESC_LEN_0_8192F(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)\n#define SET_TX_BUFF_DESC_PSB_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)\n#define SET_TX_BUFF_DESC_OWN_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)\n\n/* Dword 1     1 */\n#define SET_TX_BUFF_DESC_ADDR_LOW_0_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)\n#define GET_TX_BUFF_DESC_ADDR_LOW_0_8192F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)\n/* Dword 2     NA */\n#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value)\n#ifdef CONFIG_64BIT_DMA\n\t#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)\n#else\n\t#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc) 0\n#endif\n/* Dword 3     NA */\n/* RESERVED 0 */\n/* Dword 4     2 */\n#define SET_TX_BUFF_DESC_LEN_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value)\n#define SET_TX_BUFF_DESC_AMSDU_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value)\n/* Dword 5     3 */\n#define SET_TX_BUFF_DESC_ADDR_LOW_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value)\n/* Dword 6     NA */\n#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value)\n/* Dword 7     NA */\n/*RESERVED 0 */\n/* Dword 8     4 */\n#define SET_TX_BUFF_DESC_LEN_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value)\n#define SET_TX_BUFF_DESC_AMSDU_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value)\n/* Dword 9     5 */\n#define SET_TX_BUFF_DESC_ADDR_LOW_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value)\n/* Dword 10    NA */\n#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value)\n/* Dword 11    NA */\n/*RESERVED 0 */\n/* Dword 12    6 */\n#define SET_TX_BUFF_DESC_LEN_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value)\n#define SET_TX_BUFF_DESC_AMSDU_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value)\n/* Dword 13    7 */\n#define SET_TX_BUFF_DESC_ADDR_LOW_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value)\n/* Dword 14    NA */\n#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value)\n/* Dword 15    NA */\n/*RESERVED 0 */\n\n\n#endif\n/* -----------------------------------------------------------\n *\n *\tRate\n *\n * -----------------------------------------------------------\n * CCK Rates, TxHT = 0 */\n#define DESC8192F_RATE1M\t\t\t\t0x00\n#define DESC8192F_RATE2M\t\t\t\t0x01\n#define DESC8192F_RATE5_5M\t\t\t\t0x02\n#define DESC8192F_RATE11M\t\t\t\t0x03\n\n/* OFDM Rates, TxHT = 0 */\n#define DESC8192F_RATE6M\t\t\t\t0x04\n#define DESC8192F_RATE9M\t\t\t\t0x05\n#define DESC8192F_RATE12M\t\t\t\t0x06\n#define DESC8192F_RATE18M\t\t\t\t0x07\n#define DESC8192F_RATE24M\t\t\t\t0x08\n#define DESC8192F_RATE36M\t\t\t\t0x09\n#define DESC8192F_RATE48M\t\t\t\t0x0a\n#define DESC8192F_RATE54M\t\t\t\t0x0b\n\n/* MCS Rates, TxHT = 1 */\n#define DESC8192F_RATEMCS0\t\t\t\t0x0c\n#define DESC8192F_RATEMCS1\t\t\t\t0x0d\n#define DESC8192F_RATEMCS2\t\t\t\t0x0e\n#define DESC8192F_RATEMCS3\t\t\t\t0x0f\n#define DESC8192F_RATEMCS4\t\t\t\t0x10\n#define DESC8192F_RATEMCS5\t\t\t\t0x11\n#define DESC8192F_RATEMCS6\t\t\t\t0x12\n#define DESC8192F_RATEMCS7\t\t\t\t0x13\n#define DESC8192F_RATEMCS8\t\t\t\t0x14\n#define DESC8192F_RATEMCS9\t\t\t\t0x15\n#define DESC8192F_RATEMCS10\t\t0x16\n#define DESC8192F_RATEMCS11\t\t0x17\n#define DESC8192F_RATEMCS12\t\t0x18\n#define DESC8192F_RATEMCS13\t\t0x19\n#define DESC8192F_RATEMCS14\t\t0x1a\n#define DESC8192F_RATEMCS15\t\t0x1b\n#define DESC8192F_RATEVHTSS1MCS0\t\t0x2c\n#define DESC8192F_RATEVHTSS1MCS1\t\t0x2d\n#define DESC8192F_RATEVHTSS1MCS2\t\t0x2e\n#define DESC8192F_RATEVHTSS1MCS3\t\t0x2f\n#define DESC8192F_RATEVHTSS1MCS4\t\t0x30\n#define DESC8192F_RATEVHTSS1MCS5\t\t0x31\n#define DESC8192F_RATEVHTSS1MCS6\t\t0x32\n#define DESC8192F_RATEVHTSS1MCS7\t\t0x33\n#define DESC8192F_RATEVHTSS1MCS8\t\t0x34\n#define DESC8192F_RATEVHTSS1MCS9\t\t0x35\n#define DESC8192F_RATEVHTSS2MCS0\t\t0x36\n#define DESC8192F_RATEVHTSS2MCS1\t\t0x37\n#define DESC8192F_RATEVHTSS2MCS2\t\t0x38\n#define DESC8192F_RATEVHTSS2MCS3\t\t0x39\n#define DESC8192F_RATEVHTSS2MCS4\t\t0x3a\n#define DESC8192F_RATEVHTSS2MCS5\t\t0x3b\n#define DESC8192F_RATEVHTSS2MCS6\t\t0x3c\n#define DESC8192F_RATEVHTSS2MCS7\t\t0x3d\n#define DESC8192F_RATEVHTSS2MCS8\t\t0x3e\n#define DESC8192F_RATEVHTSS2MCS9\t\t0x3f\n\n\n#define\tRX_HAL_IS_CCK_RATE_8192F(pDesc)\\\n\t(GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE1M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE2M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE5_5M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE11M)\n\n#ifdef CONFIG_TRX_BD_ARCH\n\tstruct tx_desc;\n#endif\n\nvoid rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc);\nvoid rtl8192f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);\nvoid rtl8192f_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);\nvoid rtl8192f_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);\nvoid rtl8192f_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);\nvoid rtl8192f_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);\n\n#if defined(CONFIG_CONCURRENT_MODE)\n\tvoid fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);\n#endif\nvoid fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\ts32 rtl8192fs_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8192fs_free_xmit_priv(PADAPTER padapter);\n\ts32 rtl8192fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8192fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\trtl8192fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8192fs_xmit_buf_handler(PADAPTER padapter);\n\tthread_return rtl8192fs_xmit_thread(thread_context context);\n\t#define hal_xmit_handler rtl8192fs_xmit_buf_handler\n#endif\n\n#ifdef CONFIG_USB_HCI\n\ts32 rtl8192fu_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8192fu_free_xmit_priv(PADAPTER padapter);\n\ts32 rtl8192fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8192fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\t rtl8192fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8192fu_xmit_buf_handler(PADAPTER padapter);\n\t#define hal_xmit_handler rtl8192fu_xmit_buf_handler\n\tvoid rtl8192fu_xmit_tasklet(void *priv);\n\ts32 rtl8192fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\n\tvoid _dbg_dump_tx_info(_adapter\t*padapter,int frame_tag,struct tx_desc *ptxdesc);\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\ts32 rtl8192fe_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8192fe_free_xmit_priv(PADAPTER padapter);\n\tstruct xmit_buf *rtl8192fe_dequeue_xmitbuf(struct rtw_tx_ring *ring);\n\tvoid    rtl8192fe_xmitframe_resume(_adapter *padapter);\n\ts32 rtl8192fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8192fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32     rtl8192fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\tvoid rtl8192fe_xmit_tasklet(void *priv);\n#endif\n\nu8\tBWMapping_8192F(PADAPTER Adapter, struct pkt_attrib *pattrib);\nu8\tSCMapping_8192F(PADAPTER Adapter, struct pkt_attrib\t*pattrib);\n\n#endif\n"
  },
  {
    "path": "include/rtl8703b_cmd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8703B_CMD_H__\n#define __RTL8703B_CMD_H__\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\nenum h2c_cmd_8703B {\n\t/* Common Class: 000 */\n\tH2C_8703B_RSVD_PAGE = 0x00,\n\tH2C_8703B_MEDIA_STATUS_RPT = 0x01,\n\tH2C_8703B_SCAN_ENABLE = 0x02,\n\tH2C_8703B_KEEP_ALIVE = 0x03,\n\tH2C_8703B_DISCON_DECISION = 0x04,\n\tH2C_8703B_PSD_OFFLOAD = 0x05,\n\tH2C_8703B_AP_OFFLOAD = 0x08,\n\tH2C_8703B_BCN_RSVDPAGE = 0x09,\n\tH2C_8703B_PROBERSP_RSVDPAGE = 0x0A,\n\tH2C_8703B_FCS_RSVDPAGE = 0x10,\n\tH2C_8703B_FCS_INFO = 0x11,\n\tH2C_8703B_AP_WOW_GPIO_CTRL = 0x13,\n\n\t/* PoweSave Class: 001 */\n\tH2C_8703B_SET_PWR_MODE = 0x20,\n\tH2C_8703B_PS_TUNING_PARA = 0x21,\n\tH2C_8703B_PS_TUNING_PARA2 = 0x22,\n\tH2C_8703B_P2P_LPS_PARAM = 0x23,\n\tH2C_8703B_P2P_PS_OFFLOAD = 0x24,\n\tH2C_8703B_PS_SCAN_ENABLE = 0x25,\n\tH2C_8703B_SAP_PS_ = 0x26,\n\tH2C_8703B_INACTIVE_PS_ = 0x27, /* Inactive_PS */\n\tH2C_8703B_FWLPS_IN_IPS_ = 0x28,\n\n\t/* Dynamic Mechanism Class: 010 */\n\tH2C_8703B_MACID_CFG = 0x40,\n\tH2C_8703B_TXBF = 0x41,\n\tH2C_8703B_RSSI_SETTING = 0x42,\n\tH2C_8703B_AP_REQ_TXRPT = 0x43,\n\tH2C_8703B_INIT_RATE_COLLECT = 0x44,\n\tH2C_8703B_RA_PARA_ADJUST = 0x46,\n\n\t/* BT Class: 011 */\n\tH2C_8703B_B_TYPE_TDMA = 0x60,\n\tH2C_8703B_BT_INFO = 0x61,\n\tH2C_8703B_FORCE_BT_TXPWR = 0x62,\n\tH2C_8703B_BT_IGNORE_WLANACT = 0x63,\n\tH2C_8703B_DAC_SWING_VALUE = 0x64,\n\tH2C_8703B_ANT_SEL_RSV = 0x65,\n\tH2C_8703B_WL_OPMODE = 0x66,\n\tH2C_8703B_BT_MP_OPER = 0x67,\n\tH2C_8703B_BT_CONTROL = 0x68,\n\tH2C_8703B_BT_WIFI_CTRL = 0x69,\n\tH2C_8703B_BT_FW_PATCH = 0x6A,\n\tH2C_8703B_BT_WLAN_CALIBRATION = 0x6D,\n\n\t/* WOWLAN Class: 100 */\n\tH2C_8703B_WOWLAN = 0x80,\n\tH2C_8703B_REMOTE_WAKE_CTRL = 0x81,\n\tH2C_8703B_AOAC_GLOBAL_INFO = 0x82,\n\tH2C_8703B_AOAC_RSVD_PAGE = 0x83,\n\tH2C_8703B_AOAC_RSVD_PAGE2 = 0x84,\n\tH2C_8703B_D0_SCAN_OFFLOAD_CTRL = 0x85,\n\tH2C_8703B_D0_SCAN_OFFLOAD_INFO = 0x86,\n\tH2C_8703B_CHNL_SWITCH_OFFLOAD = 0x87,\n\tH2C_8703B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,\n\tH2C_8703B_P2P_OFFLOAD = 0x8B,\n\n\tH2C_8703B_RESET_TSF = 0xC0,\n\tH2C_8703B_MAXID,\n};\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------\n * ---------------------------------------------------------------------------------------------------------\n * _RSVDPAGE_LOC_CMD_0x00 */\n#define SET_8703B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8703B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_8703B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8703B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8703B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n/* _KEEP_ALIVE_CMD_0x03 */\n#define SET_8703B_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_8703B_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_8703B_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)\n#define SET_8703B_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n\n/* _DISCONNECT_DECISION_CMD_0x04 */\n#define SET_8703B_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_8703B_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_8703B_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_8703B_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)\n\n/* _PWR_MOD_CMD_0x20 */\n#define SET_8703B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8703B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)\n#define SET_8703B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)\n#define SET_8703B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8703B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8703B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)\n#define SET_8703B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n#define GET_8703B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)\t\t\t\t\tLE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)\n\n/* _PS_TUNE_PARAM_CMD_0x21 */\n#define SET_8703B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8703B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_8703B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)\n#define SET_8703B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)\n#define SET_8703B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n\n/* _MACID_CFG_CMD_0x40 */\n#define SET_8703B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8703B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)\n#define SET_8703B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)\n#define SET_8703B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)\n#define SET_8703B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)\n#define SET_8703B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)\n#define SET_8703B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)\n#define SET_8703B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)\n#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)\n#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)\n#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)\n\n/* _RSSI_SETTING_CMD_0x42 */\n#define SET_8703B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8703B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)\n#define SET_8703B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n\n/* _AP_REQ_TXRPT_CMD_0x43 */\n#define SET_8703B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8703B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n\n/* _FORCE_BT_TXPWR_CMD_0x62 */\n#define SET_8703B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n\n/* _FORCE_BT_MP_OPER_CMD_0x67 */\n#define SET_8703B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)\n#define SET_8703B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)\n#define SET_8703B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_8703B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)\n#define SET_8703B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n#define SET_8703B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)\n\n/* _BT_FW_PATCH_0x6A */\n#define SET_8703B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)\n#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)\n\n/* ---------------------------------------------------------------------------------------------------------\n * -------------------------------------------    Structure    --------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    Function Statement     --------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\n/* host message to firmware cmd */\nvoid rtl8703b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);\nvoid rtl8703b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);\nvoid rtl8703b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);\n/* s32 rtl8703b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */\nvoid rtl8703b_set_FwPsTuneParam_cmd(PADAPTER padapter);\nvoid rtl8703b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);\nvoid rtl8703b_download_rsvd_page(PADAPTER padapter, u8 mstatus);\n#ifdef CONFIG_BT_COEXIST\n\tvoid rtl8703b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);\n#endif /* CONFIG_BT_COEXIST */\n#ifdef CONFIG_P2P\n\tvoid rtl8703b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_TDLS\n\t#ifdef CONFIG_TDLS_CH_SW\n\t\tvoid rtl8703b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);\n\t#endif\n#endif\n\n#ifdef CONFIG_P2P_WOWLAN\n\tvoid rtl8703b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);\n#endif\n\nvoid rtl8703b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);\n\ns32 FillH2CCmd8703B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);\nu8 GetTxBufferRsvdPageNum8703B(_adapter *padapter, bool wowlan);\n#endif\n"
  },
  {
    "path": "include/rtl8703b_dm.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8703B_DM_H__\n#define __RTL8703B_DM_H__\n/* ************************************************************\n * Description:\n *\n * This file is for 8703B dynamic mechanism only\n *\n *\n * ************************************************************ */\n\n/* ************************************************************\n * structure and define\n * ************************************************************ */\n\n/* ************************************************************\n * function prototype\n * ************************************************************ */\n\nvoid rtl8703b_init_dm_priv(PADAPTER padapter);\nvoid rtl8703b_deinit_dm_priv(PADAPTER padapter);\n\nvoid rtl8703b_InitHalDm(PADAPTER padapter);\nvoid rtl8703b_HalDmWatchDog(PADAPTER padapter);\n\n#endif\n"
  },
  {
    "path": "include/rtl8703b_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8703B_HAL_H__\n#define __RTL8703B_HAL_H__\n\n#include \"hal_data.h\"\n\n#include \"rtl8703b_spec.h\"\n#include \"rtl8703b_rf.h\"\n#include \"rtl8703b_dm.h\"\n#include \"rtl8703b_recv.h\"\n#include \"rtl8703b_xmit.h\"\n#include \"rtl8703b_cmd.h\"\n#include \"rtl8703b_led.h\"\n#include \"Hal8703BPwrSeq.h\"\n#include \"Hal8703BPhyReg.h\"\n#include \"Hal8703BPhyCfg.h\"\n#ifdef DBG_CONFIG_ERROR_DETECT\n\t#include \"rtl8703b_sreset.h\"\n#endif\n\n#define FW_8703B_SIZE\t\t\t0x8000\n#define FW_8703B_START_ADDRESS\t0x1000\n#define FW_8703B_END_ADDRESS\t\t0x1FFF /* 0x5FFF */\n\n#define IS_FW_HEADER_EXIST_8703B(_pFwHdr)\t((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x03B0)\n\ntypedef struct _RT_FIRMWARE {\n\tFIRMWARE_SOURCE\teFWSource;\n#ifdef CONFIG_EMBEDDED_FWIMG\n\tu8\t\t\t*szFwBuffer;\n#else\n\tu8\t\t\tszFwBuffer[FW_8703B_SIZE];\n#endif\n\tu32\t\t\tulFwLength;\n} RT_FIRMWARE_8703B, *PRT_FIRMWARE_8703B;\n\n/*\n * This structure must be cared byte-ordering\n *\n * Added by tynli. 2009.12.04. */\ntypedef struct _RT_8703B_FIRMWARE_HDR {\n\t/* 8-byte alinment required */\n\n\t/* --- LONG WORD 0 ---- */\n\tu16\t\tSignature;\t/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */\n\tu8\t\tCategory;\t/* AP/NIC and USB/PCI */\n\tu8\t\tFunction;\t/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */\n\tu16\t\tVersion;\t\t/* FW Version */\n\tu16\t\tSubversion;\t/* FW Subversion, default 0x00 */\n\n\t/* --- LONG WORD 1 ---- */\n\tu8\t\tMonth;\t/* Release time Month field */\n\tu8\t\tDate;\t/* Release time Date field */\n\tu8\t\tHour;\t/* Release time Hour field */\n\tu8\t\tMinute;\t/* Release time Minute field */\n\tu16\t\tRamCodeSize;\t/* The size of RAM code */\n\tu16\t\tRsvd2;\n\n\t/* --- LONG WORD 2 ---- */\n\tu32\t\tSvnIdx;\t/* The SVN entry index */\n\tu32\t\tRsvd3;\n\n\t/* --- LONG WORD 3 ---- */\n\tu32\t\tRsvd4;\n\tu32\t\tRsvd5;\n} RT_8703B_FIRMWARE_HDR, *PRT_8703B_FIRMWARE_HDR;\n\n#define DRIVER_EARLY_INT_TIME_8703B\t\t0x05\n#define BCN_DMA_ATIME_INT_TIME_8703B\t\t0x02\n\n/* for 8703B\n * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */\n#define PAGE_SIZE_TX_8703B\t\t\t128\n#define PAGE_SIZE_RX_8703B\t\t\t8\n\n#define TX_DMA_SIZE_8703B\t\t\t0x8000\t/* 32K(TX) */\n#define RX_DMA_SIZE_8703B\t\t\t0x4000\t/* 16K(RX) */\n\n#ifdef CONFIG_WOWLAN\n\t#define RESV_FMWF\t(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/\n#else\n\t#define RESV_FMWF\t0\n#endif\n\n#ifdef CONFIG_FW_C2H_DEBUG\n\t#define RX_DMA_RESERVED_SIZE_8703B\t0x100\t/* 256B, reserved for c2h debug message */\n#else\n\t#define RX_DMA_RESERVED_SIZE_8703B\t0x80\t/* 128B, reserved for tx report */\n#endif\n#define RX_DMA_BOUNDARY_8703B\t\t(RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B - 1)\n\n\n/* Note: We will divide number of page equally for each queue other than public queue! */\n\n/* For General Reserved Page Number(Beacon Queue is reserved page)\n * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8703B\n * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/\n\n#define BCNQ_PAGE_NUM_8703B\t\t(MAX_BEACON_LEN/PAGE_SIZE_TX_8703B + 6) /*0x08*/\n\n/* For WoWLan , more reserved page\n * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1 PNO: 6\n * NS offload: 2NDP info: 1\n */\n#ifdef CONFIG_WOWLAN\n\t#define WOWLAN_PAGE_NUM_8703B\t0x0b\n#else\n\t#define WOWLAN_PAGE_NUM_8703B\t0x00\n#endif\n\n#ifdef CONFIG_PNO_SUPPORT\n\t#undef WOWLAN_PAGE_NUM_8703B\n\t#define WOWLAN_PAGE_NUM_8703B\t0x15\n#endif\n\n#ifdef CONFIG_AP_WOWLAN\n\t#define AP_WOWLAN_PAGE_NUM_8703B\t0x02\n#endif\n\n#define TX_TOTAL_PAGE_NUMBER_8703B\t(0xFF - BCNQ_PAGE_NUM_8703B - WOWLAN_PAGE_NUM_8703B)\n#define TX_PAGE_BOUNDARY_8703B\t\t(TX_TOTAL_PAGE_NUMBER_8703B + 1)\n\n#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8703B\tTX_TOTAL_PAGE_NUMBER_8703B\n#define WMM_NORMAL_TX_PAGE_BOUNDARY_8703B\t\t(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8703B + 1)\n\n/* For Normal Chip Setting\n * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8703B */\n#define NORMAL_PAGE_NUM_HPQ_8703B\t\t0x0C\n#define NORMAL_PAGE_NUM_LPQ_8703B\t\t0x02\n#define NORMAL_PAGE_NUM_NPQ_8703B\t\t0x02\n\n/* Note: For Normal Chip Setting, modify later */\n#define WMM_NORMAL_PAGE_NUM_HPQ_8703B\t\t0x30\n#define WMM_NORMAL_PAGE_NUM_LPQ_8703B\t\t0x20\n#define WMM_NORMAL_PAGE_NUM_NPQ_8703B\t\t0x20\n\n\n#include \"HalVerDef.h\"\n#include \"hal_com.h\"\n\n#define EFUSE_OOB_PROTECT_BYTES\t\t15\n\n#define HAL_EFUSE_MEMORY\n\n#define HWSET_MAX_SIZE_8703B\t\t\t256\n#define EFUSE_REAL_CONTENT_LEN_8703B\t\t256\n#define EFUSE_MAP_LEN_8703B\t\t\t\t512\n#define EFUSE_MAX_SECTION_8703B\t\t\t64\n\n#define EFUSE_IC_ID_OFFSET\t\t\t506\t/* For some inferiority IC purpose. added by Roger, 2009.09.02. */\n#define AVAILABLE_EFUSE_ADDR(addr)\t(addr < EFUSE_REAL_CONTENT_LEN_8703B)\n\n#define EFUSE_ACCESS_ON\t\t\t0x69\n#define EFUSE_ACCESS_OFF\t\t\t0x00\n\n/* ********************************************************\n *\t\t\tEFUSE for BT definition\n * ******************************************************** */\n#define BANK_NUM\t\t1\n#define EFUSE_BT_REAL_BANK_CONTENT_LEN\t128\n#define EFUSE_BT_REAL_CONTENT_LEN\t\t(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)\n#define EFUSE_BT_MAP_LEN\t\t\t\t1024\t/* 1k bytes */\n#define EFUSE_BT_MAX_SECTION\t\t\t(EFUSE_BT_MAP_LEN / 8)\n#define EFUSE_PROTECT_BYTES_BANK\t\t16\n\ntypedef enum tag_Package_Definition {\n\tPACKAGE_DEFAULT,\n\tPACKAGE_QFN68,\n\tPACKAGE_TFBGA90,\n\tPACKAGE_TFBGA80,\n\tPACKAGE_TFBGA79\n} PACKAGE_TYPE_E;\n\n#define INCLUDE_MULTI_FUNC_BT(_Adapter)\t\t(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)\n#define INCLUDE_MULTI_FUNC_GPS(_Adapter)\t(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)\n\n/* rtl8703b_hal_init.c */\ns32 rtl8703b_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);\nvoid rtl8703b_FirmwareSelfReset(PADAPTER padapter);\nvoid rtl8703b_InitializeFirmwareVars(PADAPTER padapter);\n\nvoid rtl8703b_InitAntenna_Selection(PADAPTER padapter);\nvoid rtl8703b_DeinitAntenna_Selection(PADAPTER padapter);\nvoid rtl8703b_CheckAntenna_Selection(PADAPTER padapter);\nvoid rtl8703b_init_default_value(PADAPTER padapter);\n\ns32 rtl8703b_InitLLTTable(PADAPTER padapter);\n\ns32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);\ns32 CardDisableWithoutHWSM(PADAPTER padapter);\n\n/* EFuse */\nu8 GetEEPROMSize8703B(PADAPTER padapter);\nvoid Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);\nvoid Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);\nvoid Hal_EfuseParseTxPowerInfo_8703B(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseBTCoexistInfo_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseEEPROMVer_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseChnlPlan_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseCustomerID_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseAntennaDiversity_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseXtal_8703B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);\nvoid Hal_EfuseParseThermalMeter_8703B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);\nvoid Hal_EfuseParseVoltage_8703B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN\tAutoLoadFail);\nvoid Hal_EfuseParseBoardType_8703B(PADAPTER Adapter,\tu8\t*PROMContent, BOOLEAN AutoloadFail);\n\nvoid rtl8703b_set_hal_ops(struct hal_ops *pHalFunc);\nvoid init_hal_spec_8703b(_adapter *adapter);\nu8 SetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val);\nvoid GetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val);\nu8 SetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);\nu8 GetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);\n\n/* register */\nvoid rtl8703b_InitBeaconParameters(PADAPTER padapter);\nvoid rtl8703b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);\nvoid\t_InitBurstPktLen_8703BS(PADAPTER Adapter);\nvoid _InitLTECoex_8703BS(PADAPTER Adapter);\nvoid _InitMacAPLLSetting_8703B(PADAPTER Adapter);\nvoid _8051Reset8703(PADAPTER padapter);\n#ifdef CONFIG_WOWLAN\n\tvoid Hal_DetectWoWMode(PADAPTER pAdapter);\n#endif /* CONFIG_WOWLAN */\n\nvoid rtl8703b_start_thread(_adapter *padapter);\nvoid rtl8703b_stop_thread(_adapter *padapter);\n\n#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)\n\tvoid rtl8703bs_init_checkbthang_workqueue(_adapter *adapter);\n\tvoid rtl8703bs_free_checkbthang_workqueue(_adapter *adapter);\n\tvoid rtl8703bs_cancle_checkbthang_workqueue(_adapter *adapter);\n\tvoid rtl8703bs_hal_check_bt_hang(_adapter *adapter);\n#endif\n\n#ifdef CONFIG_GPIO_WAKEUP\n\tvoid HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);\n#endif\n#ifdef CONFIG_MP_INCLUDED\nint FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);\n#endif\nvoid CCX_FwC2HTxRpt_8703b(PADAPTER padapter, u8 *pdata, u8 len);\n\nu8 MRateToHwRate8703B(u8  rate);\nu8 HwRateToMRate8703B(u8\t rate);\n\nvoid Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\n\n#ifdef CONFIG_PCI_HCI\n\tBOOLEAN\tInterruptRecognized8703BE(PADAPTER Adapter);\n\tvoid\tUpdateInterruptMask8703BE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);\n#endif\n\n#endif\n"
  },
  {
    "path": "include/rtl8703b_led.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8703B_LED_H__\n#define __RTL8703B_LED_H__\n\n#include <drv_conf.h>\n#include <osdep_service.h>\n#include <drv_types.h>\n\n#ifdef CONFIG_RTW_SW_LED\n/* ********************************************************************************\n * Interface to manipulate LED objects.\n * ******************************************************************************** */\n#ifdef CONFIG_USB_HCI\n\tvoid rtl8703bu_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8703bu_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_SDIO_HCI\n\tvoid rtl8703bs_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8703bs_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_GSPI_HCI\n\tvoid rtl8703bs_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8703bs_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_PCI_HCI\n\tvoid rtl8703be_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8703be_DeInitSwLeds(PADAPTER padapter);\n#endif\n\n#endif/*CONFIG_RTW_SW_LED*/\n#endif /*__RTL8703B_LED_H__*/\n"
  },
  {
    "path": "include/rtl8703b_recv.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8703B_RECV_H__\n#define __RTL8703B_RECV_H__\n\n#define RECV_BLK_SZ 512\n#define RECV_BLK_CNT 16\n#define RECV_BLK_TH RECV_BLK_CNT\n\n#if defined(CONFIG_USB_HCI)\n\n\t#ifndef MAX_RECVBUF_SZ\n\t\t#ifndef CONFIG_MINIMAL_MEMORY_USAGE\n\t\t\t/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */\n\t\t\t/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */\n\t\t\t/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */\n\t\t\t#ifdef CONFIG_PLATFORM_MSTAR\n\t\t\t\t#define MAX_RECVBUF_SZ (8192) /* 8K */\n\t\t\t#else\n\t\t\t\t#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */\n\t\t\t#endif\n\t\t\t/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */\n\t\t#else\n\t\t\t#define MAX_RECVBUF_SZ (4000) /* about 4K */\n\t\t#endif\n\t#endif /* !MAX_RECVBUF_SZ */\n\n#elif defined(CONFIG_PCI_HCI)\n\t/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */\n\t/*\t#define MAX_RECVBUF_SZ (9100) */\n\t/* #else */\n\t#define MAX_RECVBUF_SZ (4000) /* about 4K\n\t* #endif */\n\n\n#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\n\t#define MAX_RECVBUF_SZ (RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B)\n\n#endif\n\n/* Rx smooth factor */\n#define\tRx_Smooth_Factor (20)\n\n#ifdef CONFIG_SDIO_HCI\n\t#ifndef CONFIG_SDIO_RX_COPY\n\t\t#undef MAX_RECVBUF_SZ\n\t\t#define MAX_RECVBUF_SZ\t(RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B)\n\t#endif /* !CONFIG_SDIO_RX_COPY */\n#endif /* CONFIG_SDIO_HCI */\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\ts32 rtl8703bs_init_recv_priv(PADAPTER padapter);\n\tvoid rtl8703bs_free_recv_priv(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_USB_HCI\n\tint rtl8703bu_init_recv_priv(_adapter *padapter);\n\tvoid rtl8703bu_free_recv_priv(_adapter *padapter);\n\tvoid rtl8703bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\ts32 rtl8703be_init_recv_priv(PADAPTER padapter);\n\tvoid rtl8703be_free_recv_priv(PADAPTER padapter);\n#endif\n\nvoid rtl8703b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);\n\n#endif /* __RTL8703B_RECV_H__ */\n"
  },
  {
    "path": "include/rtl8703b_rf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8703B_RF_H__\n#define __RTL8703B_RF_H__\n\nint\tPHY_RF6052_Config8703B(PADAPTER\t\tAdapter);\n\nvoid\nPHY_RF6052SetBandwidth8703B(\n\t\tPADAPTER\t\t\t\tAdapter,\n\t\tenum channel_width\t\tBandwidth);\n\n#endif\n"
  },
  {
    "path": "include/rtl8703b_spec.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8703B_SPEC_H__\n#define __RTL8703B_SPEC_H__\n\n#include <drv_conf.h>\n\n\n#define HAL_NAV_UPPER_UNIT_8703B\t\t128\t\t/* micro-second */\n\n/* -----------------------------------------------------\n *\n *\t0x0000h ~ 0x00FFh\tSystem Configuration\n *\n * ----------------------------------------------------- */\n#define REG_SYS_ISO_CTRL_8703B\t\t\t0x0000\t/* 2 Byte */\n#define REG_SYS_FUNC_EN_8703B\t\t\t0x0002\t/* 2 Byte */\n#define REG_APS_FSMCO_8703B\t\t\t0x0004\t/* 4 Byte */\n#define REG_SYS_CLKR_8703B\t\t\t\t0x0008\t/* 2 Byte */\n#define REG_9346CR_8703B\t\t\t\t0x000A\t/* 2 Byte */\n#define REG_EE_VPD_8703B\t\t\t\t0x000C\t/* 2 Byte */\n#define REG_AFE_MISC_8703B\t\t\t\t0x0010\t/* 1 Byte */\n#define REG_SPS0_CTRL_8703B\t\t\t\t0x0011\t/* 7 Byte */\n#define REG_SPS_OCP_CFG_8703B\t\t\t0x0018\t/* 4 Byte */\n#define REG_RSV_CTRL_8703B\t\t\t\t0x001C\t/* 3 Byte */\n#define REG_RF_CTRL_8703B\t\t\t\t0x001F\t/* 1 Byte */\n#define REG_LPLDO_CTRL_8703B\t\t\t0x0023\t/* 1 Byte */\n#define REG_AFE_XTAL_CTRL_8703B\t\t0x0024\t/* 4 Byte */\n#define REG_AFE_PLL_CTRL_8703B\t\t\t0x0028\t/* 4 Byte */\n#define REG_MAC_PLL_CTRL_EXT_8703B\t\t0x002c\t/* 4 Byte */\n#define REG_EFUSE_CTRL_8703B\t\t\t0x0030\n#define REG_EFUSE_TEST_8703B\t\t\t0x0034\n#define REG_PWR_DATA_8703B\t\t\t\t0x0038\n#define REG_CAL_TIMER_8703B\t\t\t\t0x003C\n#define REG_ACLK_MON_8703B\t\t\t\t0x003E\n#define REG_GPIO_MUXCFG_8703B\t\t\t0x0040\n#define REG_GPIO_IO_SEL_8703B\t\t\t0x0042\n#define REG_MAC_PINMUX_CFG_8703B\t\t0x0043\n#define REG_GPIO_PIN_CTRL_8703B\t\t\t0x0044\n#define REG_GPIO_INTM_8703B\t\t\t\t0x0048\n#define REG_LEDCFG0_8703B\t\t\t\t0x004C\n#define REG_LEDCFG1_8703B\t\t\t\t0x004D\n#define REG_LEDCFG2_8703B\t\t\t\t0x004E\n#define REG_LEDCFG3_8703B\t\t\t\t0x004F\n#define REG_FSIMR_8703B\t\t\t\t\t0x0050\n#define REG_FSISR_8703B\t\t\t\t\t0x0054\n#define REG_HSIMR_8703B\t\t\t\t\t0x0058\n#define REG_HSISR_8703B\t\t\t\t\t0x005c\n#define REG_GPIO_EXT_CTRL\t\t\t\t0x0060\n#define REG_PAD_CTRL1_8703B\t\t0x0064\n#define REG_MULTI_FUNC_CTRL_8703B\t\t0x0068\n#define REG_GPIO_STATUS_8703B\t\t\t0x006C\n#define REG_SDIO_CTRL_8703B\t\t\t\t0x0070\n#define REG_OPT_CTRL_8703B\t\t\t\t0x0074\n#define REG_AFE_CTRL_4_8703B\t\t0x0078\n#define REG_MCUFWDL_8703B\t\t\t\t0x0080\n#define REG_HMEBOX_DBG_0_8703B\t0x0088\n#define REG_HMEBOX_DBG_1_8703B\t0x008A\n#define REG_HMEBOX_DBG_2_8703B\t0x008C\n#define REG_HMEBOX_DBG_3_8703B\t0x008E\n#define REG_HIMR0_8703B\t\t\t\t\t0x00B0\n#define REG_HISR0_8703B\t\t\t\t\t0x00B4\n#define REG_HIMR1_8703B\t\t\t\t\t0x00B8\n#define REG_HISR1_8703B\t\t\t\t\t0x00BC\n#define REG_PMC_DBG_CTRL2_8703B\t\t\t0x00CC\n#define\tREG_EFUSE_BURN_GNT_8703B\t\t0x00CF\n#define REG_HPON_FSM_8703B\t\t\t\t0x00EC\n#define REG_SYS_CFG_8703B\t\t\t\t0x00F0\n#define REG_SYS_CFG1_8703B\t\t\t\t0x00FC\n#define REG_ROM_VERSION\t\t\t\t\t0x00FD\n\n/* -----------------------------------------------------\n *\n *\t0x0100h ~ 0x01FFh\tMACTOP General Configuration\n *\n * ----------------------------------------------------- */\n#define REG_C2HEVT_CMD_ID_8703B\t0x01A0\n#define REG_C2HEVT_CMD_SEQ_88XX\t\t0x01A1\n#define REG_C2hEVT_CMD_CONTENT_88XX\t0x01A2\n#define REG_C2HEVT_CMD_LEN_8703B        0x01AE\n#define REG_C2HEVT_CMD_LEN_88XX\t\tREG_C2HEVT_CMD_LEN_8703B\n#define REG_C2HEVT_CLEAR_8703B\t\t\t0x01AF\n#define REG_MCUTST_1_8703B\t\t\t\t0x01C0\n#define REG_WOWLAN_WAKE_REASON 0x01C7\n#define REG_FMETHR_8703B\t\t\t\t0x01C8\n#define REG_HMETFR_8703B\t\t\t\t0x01CC\n#define REG_HMEBOX_0_8703B\t\t\t\t0x01D0\n#define REG_HMEBOX_1_8703B\t\t\t\t0x01D4\n#define REG_HMEBOX_2_8703B\t\t\t\t0x01D8\n#define REG_HMEBOX_3_8703B\t\t\t\t0x01DC\n#define REG_LLT_INIT_8703B\t\t\t\t0x01E0\n#define REG_HMEBOX_EXT0_8703B\t\t\t0x01F0\n#define REG_HMEBOX_EXT1_8703B\t\t\t0x01F4\n#define REG_HMEBOX_EXT2_8703B\t\t\t0x01F8\n#define REG_HMEBOX_EXT3_8703B\t\t\t0x01FC\n\n/* -----------------------------------------------------\n *\n *\t0x0200h ~ 0x027Fh\tTXDMA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_RQPN_8703B\t\t\t\t\t0x0200\n#define REG_FIFOPAGE_8703B\t\t\t\t0x0204\n#define REG_DWBCN0_CTRL_8703B\t\t\tREG_TDECTRL\n#define REG_TXDMA_OFFSET_CHK_8703B\t0x020C\n#define REG_TXDMA_STATUS_8703B\t\t0x0210\n#define REG_RQPN_NPQ_8703B\t\t\t0x0214\n#define REG_DWBCN1_CTRL_8703B\t\t\t0x0228\n\n\n/* -----------------------------------------------------\n *\n *\t0x0280h ~ 0x02FFh\tRXDMA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_RXDMA_AGG_PG_TH_8703B\t\t0x0280\n#define REG_FW_UPD_RDPTR_8703B\t\t0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */\n#define REG_RXDMA_CONTROL_8703B\t\t0x0286 /* Control the RX DMA. */\n#define REG_RXPKT_NUM_8703B\t\t\t0x0287 /* The number of packets in RXPKTBUF.\t */\n#define REG_RXDMA_STATUS_8703B\t\t\t0x0288\n#define REG_RXDMA_MODE_CTRL_8703B\t\t0x0290\n#define REG_EARLY_MODE_CONTROL_8703B\t0x02BC\n#define REG_RSVD5_8703B\t\t\t\t\t0x02F0\n#define REG_RSVD6_8703B\t\t\t\t\t0x02F4\n\n/* -----------------------------------------------------\n *\n *\t0x0300h ~ 0x03FFh\tPCIe\n *\n * ----------------------------------------------------- */\n#define\tREG_PCIE_CTRL_REG_8703B\t\t0x0300\n#define\tREG_INT_MIG_8703B\t\t\t\t0x0304\t/* Interrupt Migration */\n#define\tREG_BCNQ_DESA_8703B\t\t\t0x0308\t/* TX Beacon Descriptor Address */\n#define\tREG_HQ_DESA_8703B\t\t\t\t0x0310\t/* TX High Queue Descriptor Address */\n#define\tREG_MGQ_DESA_8703B\t\t\t0x0318\t/* TX Manage Queue Descriptor Address */\n#define\tREG_VOQ_DESA_8703B\t\t\t0x0320\t/* TX VO Queue Descriptor Address */\n#define\tREG_VIQ_DESA_8703B\t\t\t\t0x0328\t/* TX VI Queue Descriptor Address */\n#define\tREG_BEQ_DESA_8703B\t\t\t0x0330\t/* TX BE Queue Descriptor Address */\n#define\tREG_BKQ_DESA_8703B\t\t\t0x0338\t/* TX BK Queue Descriptor Address */\n#define\tREG_RX_DESA_8703B\t\t\t\t0x0340\t/* RX Queue\tDescriptor Address */\n#define\tREG_DBI_WDATA_8703B\t\t\t0x0348\t/* DBI Write Data */\n#define\tREG_DBI_RDATA_8703B\t\t\t0x034C\t/* DBI Read Data */\n#define\tREG_DBI_ADDR_8703B\t\t\t\t0x0350\t/* DBI Address */\n#define\tREG_DBI_FLAG_8703B\t\t\t\t0x0352\t/* DBI Read/Write Flag */\n#define\tREG_MDIO_WDATA_8703B\t\t0x0354\t/* MDIO for Write PCIE PHY */\n#define\tREG_MDIO_RDATA_8703B\t\t\t0x0356\t/* MDIO for Reads PCIE PHY */\n#define\tREG_MDIO_CTL_8703B\t\t\t0x0358\t/* MDIO for Control */\n#define\tREG_DBG_SEL_8703B\t\t\t\t0x0360\t/* Debug Selection Register */\n#define\tREG_PCIE_HRPWM_8703B\t\t\t0x0361\t/* PCIe RPWM */\n#define\tREG_PCIE_HCPWM_8703B\t\t\t0x0363\t/* PCIe CPWM */\n#define\tREG_PCIE_MULTIFET_CTRL_8703B\t0x036A\t/* PCIE Multi-Fethc Control */\n\n/* -----------------------------------------------------\n *\n *\t0x0400h ~ 0x047Fh\tProtocol Configuration\n *\n * ----------------------------------------------------- */\n#define REG_VOQ_INFORMATION_8703B\t\t0x0400\n#define REG_VIQ_INFORMATION_8703B\t\t0x0404\n#define REG_BEQ_INFORMATION_8703B\t\t0x0408\n#define REG_BKQ_INFORMATION_8703B\t\t0x040C\n#define REG_MGQ_INFORMATION_8703B\t\t0x0410\n#define REG_HGQ_INFORMATION_8703B\t\t0x0414\n#define REG_BCNQ_INFORMATION_8703B\t0x0418\n#define REG_TXPKT_EMPTY_8703B\t\t\t0x041A\n\n#define REG_FWHW_TXQ_CTRL_8703B\t\t0x0420\n#define REG_HWSEQ_CTRL_8703B\t\t\t0x0423\n#define REG_TXPKTBUF_BCNQ_BDNY_8703B\t0x0424\n#define REG_TXPKTBUF_MGQ_BDNY_8703B\t0x0425\n#define REG_LIFECTRL_CTRL_8703B\t\t\t0x0426\n#define REG_MULTI_BCNQ_OFFSET_8703B\t0x0427\n#define REG_SPEC_SIFS_8703B\t\t\t\t0x0428\n#define REG_RL_8703B\t\t\t\t\t\t0x042A\n#define REG_TXBF_CTRL_8703B\t\t\t\t0x042C\n#define REG_DARFRC_8703B\t\t\t\t0x0430\n#define REG_RARFRC_8703B\t\t\t\t0x0438\n#define REG_RRSR_8703B\t\t\t\t\t0x0440\n#define REG_ARFR0_8703B\t\t\t\t\t0x0444\n#define REG_ARFR1_8703B\t\t\t\t\t0x044C\n#define REG_CCK_CHECK_8703B\t\t\t\t0x0454\n#define REG_AMPDU_MAX_TIME_8703B\t\t0x0456\n#define REG_TXPKTBUF_BCNQ_BDNY1_8703B\t0x0457\n\n#define REG_AMPDU_MAX_LENGTH_8703B\t0x0458\n#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8703B\t0x045D\n#define REG_NDPA_OPT_CTRL_8703B\t\t0x045F\n#define REG_FAST_EDCA_CTRL_8703B\t\t0x0460\n#define REG_RD_RESP_PKT_TH_8703B\t\t0x0463\n#define REG_DATA_SC_8703B\t\t\t\t0x0483\n#ifdef CONFIG_WOWLAN\n\t#define REG_TXPKTBUF_IV_LOW             0x0484\n\t#define REG_TXPKTBUF_IV_HIGH            0x0488\n#endif\n#define REG_TXRPT_START_OFFSET\t\t0x04AC\n#define REG_POWER_STAGE1_8703B\t\t0x04B4\n#define REG_POWER_STAGE2_8703B\t\t0x04B8\n#define REG_AMPDU_BURST_MODE_8703B\t0x04BC\n#define REG_PKT_VO_VI_LIFE_TIME_8703B\t0x04C0\n#define REG_PKT_BE_BK_LIFE_TIME_8703B\t0x04C2\n#define REG_STBC_SETTING_8703B\t\t\t0x04C4\n#define REG_HT_SINGLE_AMPDU_8703B\t\t0x04C7\n#define REG_PROT_MODE_CTRL_8703B\t\t0x04C8\n#define REG_MAX_AGGR_NUM_8703B\t\t0x04CA\n#define REG_RTS_MAX_AGGR_NUM_8703B\t0x04CB\n#define REG_BAR_MODE_CTRL_8703B\t\t0x04CC\n#define REG_RA_TRY_RATE_AGG_LMT_8703B\t0x04CF\n#define REG_MACID_PKT_DROP0_8703B\t\t0x04D0\n#define REG_MACID_PKT_SLEEP_8703B\t\t0x04D4\n\n/* -----------------------------------------------------\n *\n *\t0x0500h ~ 0x05FFh\tEDCA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_EDCA_VO_PARAM_8703B\t\t0x0500\n#define REG_EDCA_VI_PARAM_8703B\t\t0x0504\n#define REG_EDCA_BE_PARAM_8703B\t\t0x0508\n#define REG_EDCA_BK_PARAM_8703B\t\t0x050C\n#define REG_BCNTCFG_8703B\t\t\t\t0x0510\n#define REG_PIFS_8703B\t\t\t\t\t0x0512\n#define REG_RDG_PIFS_8703B\t\t\t\t0x0513\n#define REG_SIFS_CTX_8703B\t\t\t\t0x0514\n#define REG_SIFS_TRX_8703B\t\t\t\t0x0516\n#define REG_AGGR_BREAK_TIME_8703B\t\t0x051A\n#define REG_SLOT_8703B\t\t\t\t\t0x051B\n#define REG_TX_PTCL_CTRL_8703B\t\t\t0x0520\n#define REG_TXPAUSE_8703B\t\t\t\t0x0522\n#define REG_DIS_TXREQ_CLR_8703B\t\t0x0523\n#define REG_RD_CTRL_8703B\t\t\t\t0x0524\n/*\n * Format for offset 540h-542h:\n *\t[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.\n *\t[7:4]:   Reserved.\n *\t[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.\n *\t[23:20]: Reserved\n * Description:\n *\t              |\n * |<--Setup--|--Hold------------>|\n *\t--------------|----------------------\n * |\n * TBTT\n * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.\n * Described by Designer Tim and Bruce, 2011-01-14.\n *   */\n#define REG_TBTT_PROHIBIT_8703B\t\t\t0x0540\n#define REG_RD_NAV_NXT_8703B\t\t\t0x0544\n#define REG_NAV_PROT_LEN_8703B\t\t\t0x0546\n#define REG_BCN_CTRL_8703B\t\t\t\t0x0550\n#define REG_BCN_CTRL_1_8703B\t\t\t0x0551\n#define REG_MBID_NUM_8703B\t\t\t\t0x0552\n#define REG_DUAL_TSF_RST_8703B\t\t\t0x0553\n#define REG_BCN_INTERVAL_8703B\t\t\t0x0554\n#define REG_DRVERLYINT_8703B\t\t\t0x0558\n#define REG_BCNDMATIM_8703B\t\t\t0x0559\n#define REG_ATIMWND_8703B\t\t\t\t0x055A\n#define REG_USTIME_TSF_8703B\t\t\t0x055C\n#define REG_BCN_MAX_ERR_8703B\t\t\t0x055D\n#define REG_RXTSF_OFFSET_CCK_8703B\t\t0x055E\n#define REG_RXTSF_OFFSET_OFDM_8703B\t0x055F\n#define REG_TSFTR_8703B\t\t\t\t\t0x0560\n#define REG_CTWND_8703B\t\t\t\t\t0x0572\n#define REG_SECONDARY_CCA_CTRL_8703B\t0x0577\n#define REG_PSTIMER_8703B\t\t\t\t0x0580\n#define REG_TIMER0_8703B\t\t\t\t0x0584\n#define REG_TIMER1_8703B\t\t\t\t0x0588\n#define REG_ACMHWCTRL_8703B\t\t\t0x05C0\n#define REG_SCH_TXCMD_8703B\t\t\t0x05F8\n\n/* -----------------------------------------------------\n *\n *\t0x0600h ~ 0x07FFh\tWMAC Configuration\n *\n * ----------------------------------------------------- */\n#define REG_MAC_CR_8703B\t\t\t\t0x0600\n#define REG_TCR_8703B\t\t\t\t\t0x0604\n#define REG_RCR_8703B\t\t\t\t\t0x0608\n#define REG_RX_PKT_LIMIT_8703B\t\t\t0x060C\n#define REG_RX_DLK_TIME_8703B\t\t\t0x060D\n#define REG_RX_DRVINFO_SZ_8703B\t\t0x060F\n\n#define REG_MACID_8703B\t\t\t\t\t0x0610\n#define REG_BSSID_8703B\t\t\t\t\t0x0618\n#define REG_MAR_8703B\t\t\t\t\t0x0620\n#define REG_MBIDCAMCFG_8703B\t\t\t0x0628\n#define REG_WOWLAN_GTK_DBG1\t0x630\n#define REG_WOWLAN_GTK_DBG2\t0x634\n\n#define REG_USTIME_EDCA_8703B\t\t\t0x0638\n#define REG_MAC_SPEC_SIFS_8703B\t\t0x063A\n#define REG_RESP_SIFP_CCK_8703B\t\t\t0x063C\n#define REG_RESP_SIFS_OFDM_8703B\t\t0x063E\n#define REG_ACKTO_8703B\t\t\t\t\t0x0640\n#define REG_CTS2TO_8703B\t\t\t\t0x0641\n#define REG_EIFS_8703B\t\t\t\t\t0x0642\n\n#define REG_NAV_UPPER_8703B\t\t\t0x0652\t/* unit of 128 */\n#define REG_TRXPTCL_CTL_8703B\t\t\t0x0668\n\n/* Security */\n#define REG_CAMCMD_8703B\t\t\t\t0x0670\n#define REG_CAMWRITE_8703B\t\t\t\t0x0674\n#define REG_CAMREAD_8703B\t\t\t\t0x0678\n#define REG_CAMDBG_8703B\t\t\t\t0x067C\n#define REG_SECCFG_8703B\t\t\t\t0x0680\n\n/* Power */\n#define REG_WOW_CTRL_8703B\t\t\t\t0x0690\n#define REG_PS_RX_INFO_8703B\t\t\t0x0692\n#define REG_UAPSD_TID_8703B\t\t\t\t0x0693\n#define REG_WKFMCAM_CMD_8703B\t\t\t0x0698\n#define REG_WKFMCAM_NUM_8703B\t\t\t0x0698\n#define REG_WKFMCAM_RWD_8703B\t\t\t0x069C\n#define REG_RXFLTMAP0_8703B\t\t\t\t0x06A0\n#define REG_RXFLTMAP1_8703B\t\t\t\t0x06A2\n#define REG_RXFLTMAP2_8703B\t\t\t\t0x06A4\n#define REG_BCN_PSR_RPT_8703B\t\t\t0x06A8\n#define REG_BT_COEX_TABLE_8703B\t\t0x06C0\n#define REG_BFMER0_INFO_8703B\t\t\t0x06E4\n#define REG_BFMER1_INFO_8703B\t\t\t0x06EC\n#define REG_CSI_RPT_PARAM_BW20_8703B\t0x06F4\n#define REG_CSI_RPT_PARAM_BW40_8703B\t0x06F8\n#define REG_CSI_RPT_PARAM_BW80_8703B\t0x06FC\n\n/* Hardware Port 2 */\n#define REG_MACID1_8703B\t\t\t\t0x0700\n#define REG_BSSID1_8703B\t\t\t\t0x0708\n#define REG_BFMEE_SEL_8703B\t\t\t\t0x0714\n#define REG_SND_PTCL_CTRL_8703B\t\t0x0718\n\n/* LTE_COEX */\n#define REG_LTECOEX_CTRL\t\t\t0x07C0\n#define REG_LTECOEX_WRITE_DATA\t\t0x07C4\n#define REG_LTECOEX_READ_DATA\t\t0x07C8\n#define REG_LTECOEX_PATH_CONTROL\t0x70\n\n/* ************************************************************\n * SDIO Bus Specification\n * ************************************************************ */\n\n/* -----------------------------------------------------\n * SDIO CMD Address Mapping\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n * I/O bus domain (Host)\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n * SDIO register\n * ----------------------------------------------------- */\n#define SDIO_REG_HCPWM1_8703B\t0x025 /* HCI Current Power Mode 1 */\n\n\n/* ****************************************************************************\n *\t8703 Regsiter Bit and Content definition\n * **************************************************************************** */\n\n#define BIT_USB_RXDMA_AGG_EN\tBIT(31)\n#define RXDMA_AGG_MODE_EN\t\tBIT(1)\n\n#ifdef CONFIG_WOWLAN\n\t#define RXPKT_RELEASE_POLL\t\tBIT(16)\n\t#define RXDMA_IDLE\t\t\t\tBIT(17)\n\t#define RW_RELEASE_EN\t\t\tBIT(18)\n#endif\n\n/* 2 HSISR\n * interrupt mask which needs to clear */\n#define MASK_HSISR_CLEAR\t\t(HSISR_GPIO12_0_INT |\\\n\t\tHSISR_SPS_OCP_INT |\\\n\t\tHSISR_RON_INT |\\\n\t\tHSISR_PDNINT |\\\n\t\tHSISR_GPIO9_INT)\n\n\n/* ----------------------------------------------------------------------------\n * 8703B REG_CCK_CHECK\t\t\t\t\t\t(offset 0x454)\n * ---------------------------------------------------------------------------- */\n#define BIT_BCN_PORT_SEL\t\tBIT(5)\n\n#ifdef CONFIG_RF_POWER_TRIM\n\n\t#ifdef CONFIG_RTL8703B\n\t\t#define EEPROM_RF_GAIN_OFFSET\t\t\t0xC1\n\t#endif\n\n\t#define EEPROM_RF_GAIN_VAL\t\t\t\t0x1F6\n#endif /*CONFIG_RF_POWER_TRIM*/\n\n\n/* ----------------------------------------------------------------------------\n * 8195 IMR/ISR bits\t\t\t\t\t\t(offset 0xB0,  8bits)\n * ---------------------------------------------------------------------------- */\n#define\tIMR_DISABLED_8703B\t\t\t\t\t0\n/* IMR DW0(0x00B0-00B3) Bit 0-31 */\n#define\tIMR_TIMER2_8703B\t\t\t\t\tBIT(31)\t\t/* Timeout interrupt 2 */\n#define\tIMR_TIMER1_8703B\t\t\t\t\tBIT(30)\t\t/* Timeout interrupt 1\t */\n#define\tIMR_PSTIMEOUT_8703B\t\t\t\tBIT(29)\t\t/* Power Save Time Out Interrupt */\n#define\tIMR_GTINT4_8703B\t\t\t\t\tBIT(28)\t\t/* When GTIMER4 expires, this bit is set to 1\t */\n#define\tIMR_GTINT3_8703B\t\t\t\t\tBIT(27)\t\t/* When GTIMER3 expires, this bit is set to 1\t */\n#define\tIMR_TXBCN0ERR_8703B\t\t\t\tBIT(26)\t\t/* Transmit Beacon0 Error\t\t\t */\n#define\tIMR_TXBCN0OK_8703B\t\t\t\tBIT(25)\t\t/* Transmit Beacon0 OK\t\t\t */\n#define\tIMR_TSF_BIT32_TOGGLE_8703B\t\tBIT(24)\t\t/* TSF Timer BIT32 toggle indication interrupt\t\t\t */\n#define\tIMR_BCNDMAINT0_8703B\t\t\t\tBIT(20)\t\t/* Beacon DMA Interrupt 0\t\t\t */\n#define\tIMR_BCNDERR0_8703B\t\t\t\tBIT(16)\t\t/* Beacon Queue DMA OK0\t\t\t */\n#define\tIMR_HSISR_IND_ON_INT_8703B\t\tBIT(15)\t\t/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */\n#define\tIMR_BCNDMAINT_E_8703B\t\t\tBIT(14)\t\t/* Beacon DMA Interrupt Extension for Win7\t\t\t */\n#define\tIMR_ATIMEND_8703B\t\t\t\tBIT(12)\t\t/* CTWidnow End or ATIM Window End */\n#define\tIMR_C2HCMD_8703B\t\t\t\t\tBIT(10)\t\t/* CPU to Host Command INT Status, Write 1 clear\t */\n#define\tIMR_CPWM2_8703B\t\t\t\t\tBIT(9)\t\t\t/* CPU power Mode exchange INT Status, Write 1 clear\t */\n#define\tIMR_CPWM_8703B\t\t\t\t\tBIT(8)\t\t\t/* CPU power Mode exchange INT Status, Write 1 clear\t */\n#define\tIMR_HIGHDOK_8703B\t\t\t\tBIT(7)\t\t\t/* High Queue DMA OK\t */\n#define\tIMR_MGNTDOK_8703B\t\t\t\tBIT(6)\t\t\t/* Management Queue DMA OK\t */\n#define\tIMR_BKDOK_8703B\t\t\t\t\tBIT(5)\t\t\t/* AC_BK DMA OK\t\t */\n#define\tIMR_BEDOK_8703B\t\t\t\t\tBIT(4)\t\t\t/* AC_BE DMA OK\t */\n#define\tIMR_VIDOK_8703B\t\t\t\t\tBIT(3)\t\t\t/* AC_VI DMA OK\t\t */\n#define\tIMR_VODOK_8703B\t\t\t\t\tBIT(2)\t\t\t/* AC_VO DMA OK\t */\n#define\tIMR_RDU_8703B\t\t\t\t\tBIT(1)\t\t\t/* Rx Descriptor Unavailable\t */\n#define\tIMR_ROK_8703B\t\t\t\t\tBIT(0)\t\t\t/* Receive DMA OK */\n\n/* IMR DW1(0x00B4-00B7) Bit 0-31 */\n#define\tIMR_BCNDMAINT7_8703B\t\t\t\tBIT(27)\t\t/* Beacon DMA Interrupt 7 */\n#define\tIMR_BCNDMAINT6_8703B\t\t\t\tBIT(26)\t\t/* Beacon DMA Interrupt 6 */\n#define\tIMR_BCNDMAINT5_8703B\t\t\t\tBIT(25)\t\t/* Beacon DMA Interrupt 5 */\n#define\tIMR_BCNDMAINT4_8703B\t\t\t\tBIT(24)\t\t/* Beacon DMA Interrupt 4 */\n#define\tIMR_BCNDMAINT3_8703B\t\t\t\tBIT(23)\t\t/* Beacon DMA Interrupt 3 */\n#define\tIMR_BCNDMAINT2_8703B\t\t\t\tBIT(22)\t\t/* Beacon DMA Interrupt 2 */\n#define\tIMR_BCNDMAINT1_8703B\t\t\t\tBIT(21)\t\t/* Beacon DMA Interrupt 1 */\n#define\tIMR_BCNDOK7_8703B\t\t\t\t\tBIT(20)\t\t/* Beacon Queue DMA OK Interrupt 7 */\n#define\tIMR_BCNDOK6_8703B\t\t\t\t\tBIT(19)\t\t/* Beacon Queue DMA OK Interrupt 6 */\n#define\tIMR_BCNDOK5_8703B\t\t\t\t\tBIT(18)\t\t/* Beacon Queue DMA OK Interrupt 5 */\n#define\tIMR_BCNDOK4_8703B\t\t\t\t\tBIT(17)\t\t/* Beacon Queue DMA OK Interrupt 4 */\n#define\tIMR_BCNDOK3_8703B\t\t\t\t\tBIT(16)\t\t/* Beacon Queue DMA OK Interrupt 3 */\n#define\tIMR_BCNDOK2_8703B\t\t\t\t\tBIT(15)\t\t/* Beacon Queue DMA OK Interrupt 2 */\n#define\tIMR_BCNDOK1_8703B\t\t\t\t\tBIT(14)\t\t/* Beacon Queue DMA OK Interrupt 1 */\n#define\tIMR_ATIMEND_E_8703B\t\t\t\tBIT(13)\t\t/* ATIM Window End Extension for Win7 */\n#define\tIMR_TXERR_8703B\t\t\t\t\tBIT(11)\t\t/* Tx Error Flag Interrupt Status, write 1 clear. */\n#define\tIMR_RXERR_8703B\t\t\t\t\tBIT(10)\t\t/* Rx Error Flag INT Status, Write 1 clear */\n#define\tIMR_TXFOVW_8703B\t\t\t\t\tBIT(9)\t\t\t/* Transmit FIFO Overflow */\n#define\tIMR_RXFOVW_8703B\t\t\t\t\tBIT(8)\t\t\t/* Receive FIFO Overflow */\n\n#ifdef CONFIG_PCI_HCI\n\t/* #define IMR_RX_MASK\t\t(IMR_ROK_8703B|IMR_RDU_8703B|IMR_RXFOVW_8703B) */\n\t#define IMR_TX_MASK\t\t\t(IMR_VODOK_8703B | IMR_VIDOK_8703B | IMR_BEDOK_8703B | IMR_BKDOK_8703B | IMR_MGNTDOK_8703B | IMR_HIGHDOK_8703B)\n\n\t#define RT_BCN_INT_MASKS\t(IMR_BCNDMAINT0_8703B | IMR_TXBCN0OK_8703B | IMR_TXBCN0ERR_8703B | IMR_BCNDERR0_8703B)\n\n\t#define RT_AC_INT_MASKS\t(IMR_VIDOK_8703B | IMR_VODOK_8703B | IMR_BEDOK_8703B | IMR_BKDOK_8703B)\n#endif\n\n#endif /* __RTL8703B_SPEC_H__ */\n"
  },
  {
    "path": "include/rtl8703b_sreset.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8703B_SRESET_H_\n#define _RTL8703B_SRESET_H_\n\n#include <rtw_sreset.h>\n\n#ifdef DBG_CONFIG_ERROR_DETECT\n\textern void rtl8703b_sreset_xmit_status_check(_adapter *padapter);\n\textern void rtl8703b_sreset_linked_status_check(_adapter *padapter);\n#endif\n#endif\n"
  },
  {
    "path": "include/rtl8703b_xmit.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8703B_XMIT_H__\n#define __RTL8703B_XMIT_H__\n\n\n#define MAX_TID (15)\n\n\n#ifndef __INC_HAL8703BDESC_H\n\t#define __INC_HAL8703BDESC_H\n\n\t#define RX_STATUS_DESC_SIZE_8703B\t\t24\n\t#define RX_DRV_INFO_SIZE_UNIT_8703B 8\n\n\n\t/* DWORD 0 */\n\t#define SET_RX_STATUS_DESC_PKT_LEN_8703B(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)\n\t#define SET_RX_STATUS_DESC_EOR_8703B(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)\n\t#define SET_RX_STATUS_DESC_OWN_8703B(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)\n\n\t#define GET_RX_STATUS_DESC_PKT_LEN_8703B(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)\n\t#define GET_RX_STATUS_DESC_CRC32_8703B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)\n\t#define GET_RX_STATUS_DESC_ICV_8703B(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)\n\t#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8703B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)\n\t#define GET_RX_STATUS_DESC_SECURITY_8703B(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)\n\t#define GET_RX_STATUS_DESC_QOS_8703B(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)\n\t#define GET_RX_STATUS_DESC_SHIFT_8703B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)\n\t#define GET_RX_STATUS_DESC_PHY_STATUS_8703B(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)\n\t#define GET_RX_STATUS_DESC_SWDEC_8703B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)\n\t#define GET_RX_STATUS_DESC_LAST_SEG_8703B(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)\n\t#define GET_RX_STATUS_DESC_FIRST_SEG_8703B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)\n\t#define GET_RX_STATUS_DESC_EOR_8703B(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)\n\t#define GET_RX_STATUS_DESC_OWN_8703B(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)\n\n\t/* DWORD 1 */\n\t#define GET_RX_STATUS_DESC_MACID_8703B(__pRxDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)\n\t#define GET_RX_STATUS_DESC_TID_8703B(__pRxDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)\n\t#define GET_RX_STATUS_DESC_AMSDU_8703B(__pRxDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)\n\t#define GET_RX_STATUS_DESC_RXID_MATCH_8703B(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)\n\t#define GET_RX_STATUS_DESC_PAGGR_8703B(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)\n\t#define GET_RX_STATUS_DESC_A1_FIT_8703B(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)\n\t#define GET_RX_STATUS_DESC_CHKERR_8703B(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)\n\t#define GET_RX_STATUS_DESC_IPVER_8703B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)\n\t#define GET_RX_STATUS_DESC_IS_TCPUDP__8703B(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)\n\t#define GET_RX_STATUS_DESC_CHK_VLD_8703B(__pRxDesc)\tLE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)\n\t#define GET_RX_STATUS_DESC_PAM_8703B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)\n\t#define GET_RX_STATUS_DESC_PWR_8703B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)\n\t#define GET_RX_STATUS_DESC_MORE_DATA_8703B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)\n\t#define GET_RX_STATUS_DESC_MORE_FRAG_8703B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)\n\t#define GET_RX_STATUS_DESC_TYPE_8703B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)\n\t#define GET_RX_STATUS_DESC_MC_8703B(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)\n\t#define GET_RX_STATUS_DESC_BC_8703B(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)\n\n\t/* DWORD 2 */\n\t#define GET_RX_STATUS_DESC_SEQ_8703B(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)\n\t#define GET_RX_STATUS_DESC_FRAG_8703B(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)\n\t#define GET_RX_STATUS_DESC_RX_IS_QOS_8703B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)\n\t#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8703B(__pRxStatusDesc)\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)\n\t#define GET_RX_STATUS_DESC_RPT_SEL_8703B(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)\n\n\t/* DWORD 3 */\n\t#define GET_RX_STATUS_DESC_RX_RATE_8703B(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)\n\t#define GET_RX_STATUS_DESC_HTC_8703B(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)\n\t#define GET_RX_STATUS_DESC_EOSP_8703B(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)\n\t#define GET_RX_STATUS_DESC_BSSID_FIT_8703B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)\n\t#ifdef CONFIG_USB_RX_AGGREGATION\n\t\t#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8703B(__pRxStatusDesc)\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)\n\t#endif\n\t#define GET_RX_STATUS_DESC_PATTERN_MATCH_8703B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)\n\t#define GET_RX_STATUS_DESC_UNICAST_MATCH_8703B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)\n\t#define GET_RX_STATUS_DESC_MAGIC_MATCH_8703B(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)\n\n\t/* DWORD 6 */\n\t#define GET_RX_STATUS_DESC_SPLCP_8703B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)\n\t#define GET_RX_STATUS_DESC_LDPC_8703B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)\n\t#define GET_RX_STATUS_DESC_STBC_8703B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)\n\t#define GET_RX_STATUS_DESC_BW_8703B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)\n\n\t/* DWORD 5 */\n\t#define GET_RX_STATUS_DESC_TSFL_8703B(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)\n\n\t#define GET_RX_STATUS_DESC_BUFF_ADDR_8703B(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)\n\t#define GET_RX_STATUS_DESC_BUFF_ADDR64_8703B(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)\n\n\t#define SET_RX_STATUS_DESC_BUFF_ADDR_8703B(__pRxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)\n\n\n\t/* Dword 0 */\n\t#define GET_TX_DESC_OWN_8703B(__pTxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pTxDesc, 31, 1)\n\n\t#define SET_TX_DESC_PKT_SIZE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)\n\t#define SET_TX_DESC_OFFSET_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)\n\t#define SET_TX_DESC_BMC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)\n\t#define SET_TX_DESC_HTC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)\n\t#define SET_TX_DESC_LAST_SEG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)\n\t#define SET_TX_DESC_FIRST_SEG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)\n\t#define SET_TX_DESC_LINIP_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)\n\t#define SET_TX_DESC_NO_ACM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)\n\t#define SET_TX_DESC_GF_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)\n\t#define SET_TX_DESC_OWN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)\n\n\t/* Dword 1 */\n\t#define SET_TX_DESC_MACID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)\n\t#define SET_TX_DESC_QUEUE_SEL_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)\n\t#define SET_TX_DESC_RDG_NAV_EXT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)\n\t#define SET_TX_DESC_LSIG_TXOP_EN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)\n\t#define SET_TX_DESC_PIFS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)\n\t#define SET_TX_DESC_RATE_ID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)\n\t#define SET_TX_DESC_EN_DESC_ID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)\n\t#define SET_TX_DESC_SEC_TYPE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)\n\t#define SET_TX_DESC_PKT_OFFSET_8703B(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)\n\n\n\t/* Dword 2 */\n\t#define SET_TX_DESC_PAID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)\n\t#define SET_TX_DESC_CCA_RTS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)\n\t#define SET_TX_DESC_AGG_ENABLE_8703B(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)\n\t#define SET_TX_DESC_RDG_ENABLE_8703B(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)\n\t#define SET_TX_DESC_AGG_BREAK_8703B(__pTxDesc, __Value)\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)\n\t#define SET_TX_DESC_MORE_FRAG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)\n\t#define SET_TX_DESC_RAW_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)\n\t#define SET_TX_DESC_SPE_RPT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)\n\t#define SET_TX_DESC_AMPDU_DENSITY_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)\n\t#define SET_TX_DESC_BT_INT_8703B(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)\n\t#define SET_TX_DESC_GID_8703B(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)\n\n\n\t/* Dword 3 */\n\t#define SET_TX_DESC_WHEADER_LEN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)\n\t#define SET_TX_DESC_CHK_EN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)\n\t#define SET_TX_DESC_EARLY_MODE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)\n\t#define SET_TX_DESC_HWSEQ_SEL_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)\n\t#define SET_TX_DESC_USE_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)\n\t#define SET_TX_DESC_DISABLE_RTS_FB_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)\n\t#define SET_TX_DESC_DISABLE_FB_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)\n\t#define SET_TX_DESC_CTS2SELF_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)\n\t#define SET_TX_DESC_RTS_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)\n\t#define SET_TX_DESC_HW_RTS_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)\n\t#define SET_TX_DESC_NAV_USE_HDR_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)\n\t#define SET_TX_DESC_USE_MAX_LEN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)\n\t#define SET_TX_DESC_MAX_AGG_NUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)\n\t#define SET_TX_DESC_NDPA_8703B(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)\n\t#define SET_TX_DESC_AMPDU_MAX_TIME_8703B(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)\n\n\t/* Dword 4 */\n\t#define SET_TX_DESC_TX_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)\n\t#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)\n\t#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)\n\t#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)\n\t#define SET_TX_DESC_DATA_RETRY_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)\n\t#define SET_TX_DESC_RTS_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)\n\n\n\t/* Dword 5 */\n\t#define SET_TX_DESC_DATA_SC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)\n\t#define SET_TX_DESC_DATA_SHORT_8703B(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)\n\t#define SET_TX_DESC_DATA_BW_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)\n\t#define SET_TX_DESC_DATA_LDPC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)\n\t#define SET_TX_DESC_DATA_STBC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)\n\t#define SET_TX_DESC_CTROL_STBC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)\n\t#define SET_TX_DESC_RTS_SHORT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)\n\t#define SET_TX_DESC_RTS_SC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)\n\n\n\t/* Dword 6 */\n\t#define SET_TX_DESC_SW_DEFINE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)\n\t#define SET_TX_DESC_MBSSID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)\n\t#define SET_TX_DESC_ANTSEL_A_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)\n\t#define SET_TX_DESC_ANTSEL_B_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)\n\t#define SET_TX_DESC_ANTSEL_C_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)\n\t#define SET_TX_DESC_ANTSEL_D_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)\n\n\t/* Dword 7 */\n\t#ifdef CONFIG_PCI_HCI\n\t\t#define SET_TX_DESC_TX_BUFFER_SIZE_8703B(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n\t#endif /*CONFIG_PCI_HCI*/\n\t#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)\n\t\t#define SET_TX_DESC_TX_DESC_CHECKSUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n\t#endif\n\t#define SET_TX_DESC_USB_TXAGG_NUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)\n\t#ifdef CONFIG_SDIO_HCI\n\t\t#define SET_TX_DESC_SDIO_TXSEQ_8703B(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)\n\t#endif\n\n\t/* Dword 8 */\n\t#define SET_TX_DESC_HWSEQ_EN_8703B(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)\n\n\t/* Dword 9 */\n\t#define SET_TX_DESC_SEQ_8703B(__pTxDesc, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)\n\n\t/* Dword 10 */\n\t#define SET_TX_DESC_TX_BUFFER_ADDRESS_8703B(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)\n\t#define GET_TX_DESC_TX_BUFFER_ADDRESS_8703B(__pTxDesc)\tLE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)\n\n\t/* Dword 11 */\n\t#define SET_TX_DESC_NEXT_DESC_ADDRESS_8703B(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)\n\n\n\t#define SET_EARLYMODE_PKTNUM_8703B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)\n\t#define SET_EARLYMODE_LEN0_8703B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)\n\t#define SET_EARLYMODE_LEN1_1_8703B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)\n\t#define SET_EARLYMODE_LEN1_2_8703B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)\n\t#define SET_EARLYMODE_LEN2_8703B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,\t__Value)\n\t#define SET_EARLYMODE_LEN3_8703B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)\n\n#endif\n/* -----------------------------------------------------------\n *\n *\tRate\n *\n * -----------------------------------------------------------\n * CCK Rates, TxHT = 0 */\n#define DESC8703B_RATE1M\t\t\t\t0x00\n#define DESC8703B_RATE2M\t\t\t\t0x01\n#define DESC8703B_RATE5_5M\t\t\t\t0x02\n#define DESC8703B_RATE11M\t\t\t\t0x03\n\n/* OFDM Rates, TxHT = 0 */\n#define DESC8703B_RATE6M\t\t\t\t0x04\n#define DESC8703B_RATE9M\t\t\t\t0x05\n#define DESC8703B_RATE12M\t\t\t\t0x06\n#define DESC8703B_RATE18M\t\t\t\t0x07\n#define DESC8703B_RATE24M\t\t\t\t0x08\n#define DESC8703B_RATE36M\t\t\t\t0x09\n#define DESC8703B_RATE48M\t\t\t\t0x0a\n#define DESC8703B_RATE54M\t\t\t\t0x0b\n\n/* MCS Rates, TxHT = 1 */\n#define DESC8703B_RATEMCS0\t\t\t\t0x0c\n#define DESC8703B_RATEMCS1\t\t\t\t0x0d\n#define DESC8703B_RATEMCS2\t\t\t\t0x0e\n#define DESC8703B_RATEMCS3\t\t\t\t0x0f\n#define DESC8703B_RATEMCS4\t\t\t\t0x10\n#define DESC8703B_RATEMCS5\t\t\t\t0x11\n#define DESC8703B_RATEMCS6\t\t\t\t0x12\n#define DESC8703B_RATEMCS7\t\t\t\t0x13\n#define DESC8703B_RATEMCS8\t\t\t\t0x14\n#define DESC8703B_RATEMCS9\t\t\t\t0x15\n#define DESC8703B_RATEMCS10\t\t0x16\n#define DESC8703B_RATEMCS11\t\t0x17\n#define DESC8703B_RATEMCS12\t\t0x18\n#define DESC8703B_RATEMCS13\t\t0x19\n#define DESC8703B_RATEMCS14\t\t0x1a\n#define DESC8703B_RATEMCS15\t\t0x1b\n#define DESC8703B_RATEVHTSS1MCS0\t\t0x2c\n#define DESC8703B_RATEVHTSS1MCS1\t\t0x2d\n#define DESC8703B_RATEVHTSS1MCS2\t\t0x2e\n#define DESC8703B_RATEVHTSS1MCS3\t\t0x2f\n#define DESC8703B_RATEVHTSS1MCS4\t\t0x30\n#define DESC8703B_RATEVHTSS1MCS5\t\t0x31\n#define DESC8703B_RATEVHTSS1MCS6\t\t0x32\n#define DESC8703B_RATEVHTSS1MCS7\t\t0x33\n#define DESC8703B_RATEVHTSS1MCS8\t\t0x34\n#define DESC8703B_RATEVHTSS1MCS9\t\t0x35\n#define DESC8703B_RATEVHTSS2MCS0\t\t0x36\n#define DESC8703B_RATEVHTSS2MCS1\t\t0x37\n#define DESC8703B_RATEVHTSS2MCS2\t\t0x38\n#define DESC8703B_RATEVHTSS2MCS3\t\t0x39\n#define DESC8703B_RATEVHTSS2MCS4\t\t0x3a\n#define DESC8703B_RATEVHTSS2MCS5\t\t0x3b\n#define DESC8703B_RATEVHTSS2MCS6\t\t0x3c\n#define DESC8703B_RATEVHTSS2MCS7\t\t0x3d\n#define DESC8703B_RATEVHTSS2MCS8\t\t0x3e\n#define DESC8703B_RATEVHTSS2MCS9\t\t0x3f\n\n\n#define\tRX_HAL_IS_CCK_RATE_8703B(pDesc)\\\n\t(GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE1M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE2M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE5_5M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE11M)\n\n\nvoid rtl8703b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);\nvoid rtl8703b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);\n#if defined(CONFIG_CONCURRENT_MODE)\n\tvoid fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);\n#endif\nvoid fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\ts32 rtl8703bs_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8703bs_free_xmit_priv(PADAPTER padapter);\n\ts32 rtl8703bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8703bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\trtl8703bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8703bs_xmit_buf_handler(PADAPTER padapter);\n\tthread_return rtl8703bs_xmit_thread(thread_context context);\n\t#define hal_xmit_handler rtl8703bs_xmit_buf_handler\n#endif\n\n#ifdef CONFIG_USB_HCI\n\ts32 rtl8703bu_xmit_buf_handler(PADAPTER padapter);\n\t#define hal_xmit_handler rtl8703bu_xmit_buf_handler\n\n\n\ts32 rtl8703bu_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8703bu_free_xmit_priv(PADAPTER padapter);\n\ts32 rtl8703bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8703bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\t rtl8703bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\t/* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */\n\tvoid rtl8703bu_xmit_tasklet(void *priv);\n\ts32 rtl8703bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\n\tvoid _dbg_dump_tx_info(_adapter\t*padapter, int frame_tag, struct tx_desc *ptxdesc);\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\ts32 rtl8703be_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8703be_free_xmit_priv(PADAPTER padapter);\n\tstruct xmit_buf *rtl8703be_dequeue_xmitbuf(struct rtw_tx_ring *ring);\n\tvoid\trtl8703be_xmitframe_resume(_adapter *padapter);\n\ts32 rtl8703be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8703be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\trtl8703be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\tvoid rtl8703be_xmit_tasklet(void *priv);\n#endif\n\nu8\tBWMapping_8703B(PADAPTER Adapter, struct pkt_attrib *pattrib);\nu8\tSCMapping_8703B(PADAPTER Adapter, struct pkt_attrib\t*pattrib);\n\n#endif\n"
  },
  {
    "path": "include/rtl8710b_cmd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8710B_CMD_H__\n#define __RTL8710B_CMD_H__\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\nenum h2c_cmd_8710B {\n\t/* Common Class: 000 */\n\tH2C_8710B_RSVD_PAGE = 0x00,\n\tH2C_8710B_MEDIA_STATUS_RPT = 0x01,\n\tH2C_8710B_SCAN_ENABLE = 0x02,\n\tH2C_8710B_KEEP_ALIVE = 0x03,\n\tH2C_8710B_DISCON_DECISION = 0x04,\n\tH2C_8710B_PSD_OFFLOAD = 0x05,\n\tH2C_8710B_AP_OFFLOAD = 0x08,\n\tH2C_8710B_BCN_RSVDPAGE = 0x09,\n\tH2C_8710B_PROBERSP_RSVDPAGE = 0x0A,\n\tH2C_8710B_FCS_RSVDPAGE = 0x10,\n\tH2C_8710B_FCS_INFO = 0x11,\n\tH2C_8710B_AP_WOW_GPIO_CTRL = 0x13,\n\n\t/* PoweSave Class: 001 */\n\tH2C_8710B_SET_PWR_MODE = 0x20,\n\tH2C_8710B_PS_TUNING_PARA = 0x21,\n\tH2C_8710B_PS_TUNING_PARA2 = 0x22,\n\tH2C_8710B_P2P_LPS_PARAM = 0x23,\n\tH2C_8710B_P2P_PS_OFFLOAD = 0x24,\n\tH2C_8710B_PS_SCAN_ENABLE = 0x25,\n\tH2C_8710B_SAP_PS_ = 0x26,\n\tH2C_8710B_INACTIVE_PS_ = 0x27, /* Inactive_PS */\n\tH2C_8710B_FWLPS_IN_IPS_ = 0x28,\n\n\t/* Dynamic Mechanism Class: 010 */\n\tH2C_8710B_MACID_CFG = 0x40,\n\tH2C_8710B_TXBF = 0x41,\n\tH2C_8710B_RSSI_SETTING = 0x42,\n\tH2C_8710B_AP_REQ_TXRPT = 0x43,\n\tH2C_8710B_INIT_RATE_COLLECT = 0x44,\n\tH2C_8710B_RA_PARA_ADJUST = 0x46,\n\n\t/* WOWLAN Class: 100 */\n\tH2C_8710B_WOWLAN = 0x80,\n\tH2C_8710B_REMOTE_WAKE_CTRL = 0x81,\n\tH2C_8710B_AOAC_GLOBAL_INFO = 0x82,\n\tH2C_8710B_AOAC_RSVD_PAGE = 0x83,\n\tH2C_8710B_AOAC_RSVD_PAGE2 = 0x84,\n\tH2C_8710B_D0_SCAN_OFFLOAD_CTRL = 0x85,\n\tH2C_8710B_D0_SCAN_OFFLOAD_INFO = 0x86,\n\tH2C_8710B_CHNL_SWITCH_OFFLOAD = 0x87,\n\tH2C_8710B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,\n\tH2C_8710B_P2P_OFFLOAD = 0x8B,\n\n\tH2C_8710B_RESET_TSF = 0xC0,\n\tH2C_8710B_MAXID,\n};\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------\n * ---------------------------------------------------------------------------------------------------------\n * _RSVDPAGE_LOC_CMD_0x00 */\n#define SET_8710B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8710B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_8710B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8710B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8710B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n/* _PWR_MOD_CMD_0x20 */\n#define SET_8710B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8710B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)\n#define SET_8710B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)\n#define SET_8710B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8710B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8710B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)\n#define SET_8710B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n#define GET_8710B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)\t\t\t\t\tLE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)\n\n/* _PS_TUNE_PARAM_CMD_0x21 */\n#define SET_8710B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8710B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_8710B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)\n#define SET_8710B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)\n#define SET_8710B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n\n/* _MACID_CFG_CMD_0x40 */\n#define SET_8710B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8710B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)\n#define SET_8710B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)\n#define SET_8710B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)\n#define SET_8710B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)\n#define SET_8710B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)\n#define SET_8710B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)\n#define SET_8710B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)\n#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)\n#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)\n#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)\n\n/* _RSSI_SETTING_CMD_0x42 */\n#define SET_8710B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8710B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)\n#define SET_8710B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n\n/* _AP_REQ_TXRPT_CMD_0x43 */\n#define SET_8710B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8710B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n\n/* _FORCE_BT_TXPWR_CMD_0x62 */\n#define SET_8710B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n\n/* _FORCE_BT_MP_OPER_CMD_0x67 */\n#define SET_8710B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)\n#define SET_8710B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)\n#define SET_8710B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_8710B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)\n#define SET_8710B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n#define SET_8710B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)\n\n/* _BT_FW_PATCH_0x6A */\n#define SET_8710B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)\n#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)\n\n/* ---------------------------------------------------------------------------------------------------------\n * -------------------------------------------    Structure    --------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    Function Statement     --------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\n/* host message to firmware cmd */\nvoid rtl8710b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);\nvoid rtl8710b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);\n/* s32 rtl8710b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */\nvoid rtl8710b_set_FwPsTuneParam_cmd(PADAPTER padapter);\nvoid rtl8710b_download_rsvd_page(PADAPTER padapter, u8 mstatus);\n#ifdef CONFIG_BT_COEXIST\n\tvoid rtl8710b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);\n#endif /* CONFIG_BT_COEXIST */\n#ifdef CONFIG_P2P\n\tvoid rtl8710b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\nvoid rtl8710b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);\n#endif\n#endif\n\n#ifdef CONFIG_P2P_WOWLAN\n\tvoid rtl8710b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);\n#endif\n\ns32 FillH2CCmd8710B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);\nu8 GetTxBufferRsvdPageNum8710B(_adapter *padapter, bool wowlan);\n#endif\n"
  },
  {
    "path": "include/rtl8710b_dm.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8710B_DM_H__\n#define __RTL8710B_DM_H__\n/* ************************************************************\n * Description:\n *\n * This file is for 8710B dynamic mechanism only\n *\n *\n * ************************************************************ */\n\n/* ************************************************************\n * structure and define\n * ************************************************************ */\n\n/* ************************************************************\n * function prototype\n * ************************************************************ */\n\nvoid rtl8710b_init_dm_priv(PADAPTER padapter);\nvoid rtl8710b_deinit_dm_priv(PADAPTER padapter);\n\nvoid rtl8710b_InitHalDm(PADAPTER padapter);\nvoid rtl8710b_HalDmWatchDog(PADAPTER padapter);\n\n#endif\n"
  },
  {
    "path": "include/rtl8710b_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8710B_HAL_H__\n#define __RTL8710B_HAL_H__\n\n#include \"hal_data.h\"\n\n#include \"rtl8710b_spec.h\"\n#include \"rtl8710b_rf.h\"\n#include \"rtl8710b_dm.h\"\n#include \"rtl8710b_recv.h\"\n#include \"rtl8710b_xmit.h\"\n#include \"rtl8710b_cmd.h\"\n#include \"rtl8710b_led.h\"\n#include \"Hal8710BPwrSeq.h\"\n#include \"Hal8710BPhyReg.h\"\n#include \"Hal8710BPhyCfg.h\"\n#ifdef DBG_CONFIG_ERROR_DETECT\n\t#include \"rtl8710b_sreset.h\"\n#endif\n#ifdef CONFIG_LPS_POFF\n\t#include \"rtl8710b_lps_poff.h\"\n#endif\n\n#define FW_8710B_SIZE\t\t0x8000\n#define FW_8710B_START_ADDRESS\t0x1000\n#define FW_8710B_END_ADDRESS\t0x1FFF /* 0x5FFF */\n\ntypedef struct _RT_FIRMWARE {\n\tFIRMWARE_SOURCE\teFWSource;\n#ifdef CONFIG_EMBEDDED_FWIMG\n\tu8\t\t\t*szFwBuffer;\n#else\n\tu8\t\t\tszFwBuffer[FW_8710B_SIZE];\n#endif\n\tu32\t\t\tulFwLength;\n} RT_FIRMWARE_8710B, *PRT_FIRMWARE_8710B;\n\n/*\n * This structure must be cared byte-ordering\n *\n * Added by tynli. 2009.12.04. */\ntypedef struct _RT_8710B_FIRMWARE_HDR {\n\t/* 8-byte alinment required */\n\n\t/* --- LONG WORD 0 ---- */\n\tu16\t\tSignature;\t/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */\n\tu8\t\tCategory;\t/* AP/NIC and USB/PCI */\n\tu8\t\tFunction;\t/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */\n\tu16\t\tVersion;\t\t/* FW Version */\n\tu16\t\tSubversion;\t/* FW Subversion, default 0x00 */\n\n\t/* --- LONG WORD 1 ---- */\n\tu8\t\tMonth;\t/* Release time Month field */\n\tu8\t\tDate;\t/* Release time Date field */\n\tu8\t\tHour;\t/* Release time Hour field */\n\tu8\t\tMinute;\t/* Release time Minute field */\n\tu16\t\tRamCodeSize;\t/* The size of RAM code */\n\tu16\t\tRsvd2;\n\n\t/* --- LONG WORD 2 ---- */\n\tu32\t\tSvnIdx;\t/* The SVN entry index */\n\tu32\t\tRsvd3;\n\n\t/* --- LONG WORD 3 ---- */\n\tu32\t\tRsvd4;\n\tu32\t\tRsvd5;\n} RT_8710B_FIRMWARE_HDR, *PRT_8710B_FIRMWARE_HDR;\n\n#define DRIVER_EARLY_INT_TIME_8710B\t\t0x05\n#define BCN_DMA_ATIME_INT_TIME_8710B\t\t0x02\n\n/* for 8710B\n * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */\n#define PAGE_SIZE_TX_8710B\t\t\t128\n#define PAGE_SIZE_RX_8710B\t\t\t8\n\n#define TX_DMA_SIZE_8710B\t\t\t0x8000\t/* 32K(TX) */\n#define RX_DMA_SIZE_8710B\t\t\t0x4000\t/* 16K(RX) */\n\n#ifdef CONFIG_WOWLAN\n\t#define RESV_FMWF\t(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/\n#else\n\t#define RESV_FMWF\t0\n#endif\n\n#ifdef CONFIG_FW_C2H_DEBUG\n\t#define RX_DMA_RESERVED_SIZE_8710B\t0x100\t/* 256B, reserved for c2h debug message */\n#else\n\t#define RX_DMA_RESERVED_SIZE_8710B\t0x80\t/* 128B, reserved for tx report */\n#endif\n#define RX_DMA_BOUNDARY_8710B\\\n\t(RX_DMA_SIZE_8710B - RX_DMA_RESERVED_SIZE_8710B - 1)\n\n\n/* Note: We will divide number of page equally for each queue other than public queue! */\n\n/* For General Reserved Page Number(Beacon Queue is reserved page)\n * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8710B\n * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/\n#define BCNQ_PAGE_NUM_8710B\t(MAX_BEACON_LEN/PAGE_SIZE_TX_8710B + 6) /*0x08*/\n\n\n/* For WoWLan , more reserved page\n * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6\n * NS offload: 2 NDP info: 1\n */\n#ifdef CONFIG_WOWLAN\n\t#define WOWLAN_PAGE_NUM_8710B\t0x0b\n#else\n\t#define WOWLAN_PAGE_NUM_8710B\t0x00\n#endif\n\n#ifdef CONFIG_PNO_SUPPORT\n\t#undef WOWLAN_PAGE_NUM_8710B\n\t#define WOWLAN_PAGE_NUM_8710B\t0x15\n#endif\n\n#ifdef CONFIG_AP_WOWLAN\n\t#define AP_WOWLAN_PAGE_NUM_8710B\t0x02\n#endif\n\n#define TX_TOTAL_PAGE_NUMBER_8710B\\\n\t(0xFF - BCNQ_PAGE_NUM_8710B -WOWLAN_PAGE_NUM_8710B)\n#define TX_PAGE_BOUNDARY_8710B\t\t(TX_TOTAL_PAGE_NUMBER_8710B + 1)\n\n#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8710B\tTX_TOTAL_PAGE_NUMBER_8710B\n#define WMM_NORMAL_TX_PAGE_BOUNDARY_8710B\\\n\t(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8710B + 1)\n\n/* For Normal Chip Setting\n * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8710B */\n#define NORMAL_PAGE_NUM_HPQ_8710B\t\t0x0C\n#define NORMAL_PAGE_NUM_LPQ_8710B\t\t0x02\n#define NORMAL_PAGE_NUM_NPQ_8710B\t\t0x02\n#define NORMAL_PAGE_NUM_EPQ_8710B\t\t0x04\n\n/* Note: For Normal Chip Setting, modify later */\n#define WMM_NORMAL_PAGE_NUM_HPQ_8710B\t\t0x30\n#define WMM_NORMAL_PAGE_NUM_LPQ_8710B\t\t0x20\n#define WMM_NORMAL_PAGE_NUM_NPQ_8710B\t\t0x20\n#define WMM_NORMAL_PAGE_NUM_EPQ_8710B\t\t0x00\n\n\n#include \"HalVerDef.h\"\n#include \"hal_com.h\"\n\n#define EFUSE_OOB_PROTECT_BYTES (96 + 1)\n\n#define HAL_EFUSE_MEMORY\n#define HWSET_MAX_SIZE_8710B                512\n#define EFUSE_REAL_CONTENT_LEN_8710B        512\n#define EFUSE_MAP_LEN_8710B                 512\n#define EFUSE_MAX_SECTION_8710B             64\n\n/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/\n#define EFUSE_IC_ID_OFFSET\t\t\t506\n#define AVAILABLE_EFUSE_ADDR(addr)\t(addr < EFUSE_REAL_CONTENT_LEN_8710B)\n\n#define EFUSE_ACCESS_ON\t0x69\n#define EFUSE_ACCESS_OFF\t0x00\n\n#define   PACKAGE_QFN32_S           0\n#define   PACKAGE_QFN48M_S        1    //definiton 8188GU Dongle Package, Efuse Physical Address 0xF8 = 0xFE\n#define   PACKAGE_QFN48_S  \t       2\n#define   PACKAGE_QFN64_S  \t       3     \n#define   PACKAGE_QFN32_U  \t\t4    \n#define   PACKAGE_QFN48M_U  \t5   //definiton 8188GU Dongle Package, Efuse Physical Address 0xF8 = 0xEE\n#define   PACKAGE_QFN48_U  \t\t6 \n#define   PACKAGE_QFN68_U  \t\t7\n\ntypedef enum _PACKAGE_TYPE_E\n{\n    PACKAGE_DEFAULT,\n    PACKAGE_QFN68,\n    PACKAGE_TFBGA90,\n    PACKAGE_TFBGA80,\n    PACKAGE_TFBGA79\n}PACKAGE_TYPE_E;\n\n#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \\\n\t(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)\n\n#ifdef CONFIG_FILE_FWIMG\n\textern char *rtw_fw_file_path;\n\textern char *rtw_fw_wow_file_path;\n\t#ifdef CONFIG_MP_INCLUDED\n\t\textern char *rtw_fw_mp_bt_file_path;\n\t#endif /* CONFIG_MP_INCLUDED */\n#endif /* CONFIG_FILE_FWIMG */\n\n/* rtl8710b_hal_init.c */\ns32 rtl8710b_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);\nvoid rtl8710b_FirmwareSelfReset(PADAPTER padapter);\nvoid rtl8710b_InitializeFirmwareVars(PADAPTER padapter);\n\nvoid rtl8710b_InitAntenna_Selection(PADAPTER padapter);\nvoid rtl8710b_DeinitAntenna_Selection(PADAPTER padapter);\nvoid rtl8710b_CheckAntenna_Selection(PADAPTER padapter);\nvoid rtl8710b_init_default_value(PADAPTER padapter);\n\n\nu32 indirect_read32_8710b(PADAPTER padapter, u32 regaddr);\nvoid indirect_write32_8710b(PADAPTER padapter, u32 regaddr, u32 data);\nu32 hal_query_syson_reg_8710b(PADAPTER padapter, u32 regaddr, u32 bitmask);\nvoid hal_set_syson_reg_8710b(PADAPTER padapter, u32 regaddr, u32 bitmask, u32 data);\n#define HAL_SetSYSOnReg hal_set_syson_reg_8710b\n\n\n/* EFuse */\nu8 GetEEPROMSize8710B(PADAPTER padapter);\n\n#if 0\nvoid Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);\nvoid Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);\nvoid Hal_EfuseParseTxPowerInfo_8710B(PADAPTER padapter,\n\t\t\t\t     u8 *PROMContent, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseEEPROMVer_8710B(PADAPTER padapter,\n\t\t\t\t   u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParsePackageType_8710B(PADAPTER pAdapter,\n\t\t\t\t     u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseChnlPlan_8710B(PADAPTER padapter,\n\t\t\t\t  u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseCustomerID_8710B(PADAPTER padapter,\n\t\t\t\t    u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseAntennaDiversity_8710B(PADAPTER padapter,\n\t\tu8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseXtal_8710B(PADAPTER pAdapter,\n\t\t\t      u8 *hwinfo, u8 AutoLoadFail);\nvoid Hal_EfuseParseThermalMeter_8710B(PADAPTER padapter,\n\t\t\t\t      u8 *hwinfo, u8 AutoLoadFail);\nvoid Hal_EfuseParseBoardType_8710B(PADAPTER Adapter,\n\t\t\t\t   u8\t*PROMContent, BOOLEAN AutoloadFail);\n#endif\n\nvoid rtl8710b_set_hal_ops(struct hal_ops *pHalFunc);\nvoid init_hal_spec_8710b(_adapter *adapter);\nu8 SetHwReg8710B(PADAPTER padapter, u8 variable, u8 *val);\nvoid GetHwReg8710B(PADAPTER padapter, u8 variable, u8 *val);\nu8 SetHalDefVar8710B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);\nu8 GetHalDefVar8710B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);\n\n/* register */\nvoid rtl8710b_InitBeaconParameters(PADAPTER padapter);\nvoid rtl8710b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);\nvoid _8051Reset8710(PADAPTER padapter);\n\nvoid rtl8710b_start_thread(_adapter *padapter);\nvoid rtl8710b_stop_thread(_adapter *padapter);\n\n#ifdef CONFIG_GPIO_WAKEUP\n\tvoid HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);\n#endif\n\nvoid CCX_FwC2HTxRpt_8710b(PADAPTER padapter, u8 *pdata, u8 len);\n\nu8 MRateToHwRate8710B(u8 rate);\nu8 HwRateToMRate8710B(u8 rate);\n\n#ifdef CONFIG_USB_HCI\n\tvoid rtl8710b_cal_txdesc_chksum(struct tx_desc *ptxdesc);\n#endif\n\n\n#endif\n"
  },
  {
    "path": "include/rtl8710b_led.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8710B_LED_H__\n#define __RTL8710B_LED_H__\n\n#include <drv_conf.h>\n#include <osdep_service.h>\n#include <drv_types.h>\n\n#ifdef CONFIG_RTW_SW_LED\n/* ********************************************************************************\n * Interface to manipulate LED objects.\n * ******************************************************************************** */\n#ifdef CONFIG_USB_HCI\n\tvoid rtl8710bu_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8710bu_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_SDIO_HCI\n\tvoid rtl8710bs_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8710bs_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_GSPI_HCI\n\tvoid rtl8710bs_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8710bs_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_PCI_HCI\n\tvoid rtl8710be_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8710be_DeInitSwLeds(PADAPTER padapter);\n#endif\n\n#endif /*#ifdef CONFIG_RTW_SW_LED*/\n#endif\n"
  },
  {
    "path": "include/rtl8710b_lps_poff.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n/******************************************** CONST  ************************/\n#define NUM_OF_REGISTER_BANK\t13\n#define NUM_OF_TOTAL_DWORD (NUM_OF_REGISTER_BANK * 64)\n#define TOTAL_LEN_FOR_HIOE ((NUM_OF_TOTAL_DWORD + 1) * 8)\n#define LPS_POFF_STATIC_FILE_LEN (TOTAL_LEN_FOR_HIOE + TXDESC_SIZE)\n#define LPS_POFF_DYNAMIC_FILE_LEN\t(512 + TXDESC_SIZE)\n/******************************************** CONST  ************************/\n\n/******************************************** MACRO   ************************/\n/* HOIE Entry Definition */\n#define SET_HOIE_ENTRY_LOW_DATA(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE),\t0, 16, __Value)\n#define SET_HOIE_ENTRY_HIGH_DATA(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE), 16, 16, __Value)\n#define SET_HOIE_ENTRY_MODE_SELECT(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 0, 1, __Value)\n#define SET_HOIE_ENTRY_ADDRESS(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 1, 14, __Value)\n#define SET_HOIE_ENTRY_BYTE_MASK(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 15, 4, __Value)\n#define SET_HOIE_ENTRY_IO_LOCK(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 19, 1, __Value)\n#define SET_HOIE_ENTRY_RD_EN(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 20, 1, __Value)\n#define SET_HOIE_ENTRY_WR_EN(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 21, 1, __Value)\n#define SET_HOIE_ENTRY_RAW_RW(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 22, 1, __Value)\n#define SET_HOIE_ENTRY_RAW(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 23, 1, __Value)\n#define SET_HOIE_ENTRY_IO_DELAY(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 24, 8, __Value)\n\n/*********************Function Definition*******************************************/\nvoid rtl8710b_lps_poff_init(PADAPTER padapter);\nvoid rtl8710b_lps_poff_deinit(PADAPTER padapter);\nbool rtl8710b_lps_poff_get_txbndy_status(PADAPTER padapter);\nvoid rtl8710b_lps_poff_h2c_ctrl(PADAPTER padapter, u8 enable);\nvoid rtl8710b_lps_poff_set_ps_mode(PADAPTER padapter, bool bEnterLPS);\nbool rtl8710b_lps_poff_get_status(PADAPTER padapter);\nvoid rtl8710b_lps_poff_wow(PADAPTER padapter);\n"
  },
  {
    "path": "include/rtl8710b_recv.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8710B_RECV_H__\n#define __RTL8710B_RECV_H__\n\n#define RECV_BLK_SZ 512\n#define RECV_BLK_CNT 16\n#define RECV_BLK_TH RECV_BLK_CNT\n\n#if defined(CONFIG_USB_HCI)\n\t#ifndef MAX_RECVBUF_SZ\n\t\t#ifdef CONFIG_MINIMAL_MEMORY_USAGE\n\t\t\t#define MAX_RECVBUF_SZ (4000) /* about 4K */\n\t\t#else\n\t\t\t#ifdef CONFIG_PLATFORM_MSTAR\n\t\t\t\t#define MAX_RECVBUF_SZ (8192) /* 8K */\n\t\t\t\t#elif defined(CONFIG_PLATFORM_HISILICON)\n\t\t\t\t#define MAX_RECVBUF_SZ (16384) /* 16k */\n\t\t\t#else\n\t\t\t\t#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */\n\t\t\t\t/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */\n\t\t\t\t/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */\n\t\t\t\t/* #define MAX_RECVBUF_SZ (10240)  */ /* 10K */\n\t\t\t\t/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */\n\t\t\t#endif\n\t\t#endif\n\t#endif /* !MAX_RECVBUF_SZ */\n#endif\n\n/* Rx smooth factor */\n#define\tRx_Smooth_Factor (20)\n\n/*-----------------------------------------------------------------*/\n/*\tRTL8710B RX BUFFER DESC                                      */\n/*-----------------------------------------------------------------*/\n/*DWORD 0*/\n#define SET_RX_BUFFER_DESC_DATA_LENGTH_8710B(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)\n#define SET_RX_BUFFER_DESC_LS_8710B(__pRxStatusDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)\n#define SET_RX_BUFFER_DESC_FS_8710B(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)\n#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8710B(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)\n\n#define GET_RX_BUFFER_DESC_OWN_8710B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)\n#define GET_RX_BUFFER_DESC_LS_8710B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)\n#define GET_RX_BUFFER_DESC_FS_8710B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)\n#ifdef USING_RX_TAG\n\t#define GET_RX_BUFFER_DESC_RX_TAG_8710B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13)\n#else\n\t#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8710B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)\n#endif\n\n/*DWORD 1*/\n#define SET_RX_BUFFER_PHYSICAL_LOW_8710B(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)\n\n/*DWORD 2*/\n#ifdef CONFIG_64BIT_DMA\n\t#define SET_RX_BUFFER_PHYSICAL_HIGH_8710B(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)\n#else\n\t#define SET_RX_BUFFER_PHYSICAL_HIGH_8710B(__pRxStatusDesc, __Value)\n#endif\n\n#ifdef CONFIG_USB_HCI\n\tint rtl8710bu_init_recv_priv(_adapter *padapter);\n\tvoid rtl8710bu_free_recv_priv(_adapter *padapter);\n\tvoid rtl8710bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);\n#endif\n\nvoid rtl8710b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);\n\n#endif /* __RTL8710B_RECV_H__ */\n"
  },
  {
    "path": "include/rtl8710b_rf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8710B_RF_H__\n#define __RTL8710B_RF_H__\n\nint PHY_RF6052_Config8710B(PADAPTER pdapter);\n\n#endif\n"
  },
  {
    "path": "include/rtl8710b_spec.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8710B_SPEC_H__\n#define __RTL8710B_SPEC_H__\n\n#include <drv_conf.h>\n\n\n#define HAL_NAV_UPPER_UNIT_8710B\t\t128\t\t/* micro-second */\n\n/* -----------------------------------------------------\n *\n *\t0x0000h ~ 0x00FFh\tSystem Configuration\n *\n * ----------------------------------------------------- */\n#define REG_SYS_ISO_CTRL_8710B\t\t\t0x0000\t/* 2 Byte */\n#define REG_APS_FSMCO_8710B\t\t\t0x0004\t/* 4 Byte */\n#define REG_SYS_CLKR_8710B\t\t\t\t0x0008\t/* 2 Byte */\n#define REG_9346CR_8710B\t\t\t\t0x000A\t/* 2 Byte */\n#define REG_EE_VPD_8710B\t\t\t\t0x000C\t/* 2 Byte */\n#define REG_AFE_MISC_8710B\t\t\t\t0x0010\t/* 1 Byte */\n#define REG_SPS0_CTRL_8710B\t\t\t\t0x0011\t/* 7 Byte */\n#define REG_SPS_OCP_CFG_8710B\t\t\t0x0018\t/* 4 Byte */\n#define REG_RSV_CTRL_8710B\t\t\t\t0x001C\t/* 3 Byte */\n#define REG_RF_CTRL_8710B\t\t\t\t0x001F\t/* 1 Byte */\n#define REG_LPLDO_CTRL_8710B\t\t\t0x0023\t/* 1 Byte */\n#define REG_AFE_XTAL_CTRL_8710B\t\t0x0024\t/* 4 Byte */\n#define REG_AFE_PLL_CTRL_8710B\t\t\t0x0028\t/* 4 Byte */\n#define REG_MAC_PLL_CTRL_EXT_8710B\t\t0x002c\t/* 4 Byte */\n#define REG_EFUSE_CTRL_8710B\t\t\t0x0030\n#define REG_EFUSE_TEST_8710B\t\t\t0x0034\n#define REG_PWR_DATA_8710B\t\t\t\t0x0038\n#define REG_CAL_TIMER_8710B\t\t\t\t0x003C\n#define REG_ACLK_MON_8710B\t\t\t\t0x003E\n#define REG_GPIO_MUXCFG_8710B\t\t\t0x0040\n#define REG_GPIO_IO_SEL_8710B\t\t\t0x0042\n#define REG_MAC_PINMUX_CFG_8710B\t\t0x0043\n#define REG_GPIO_PIN_CTRL_8710B\t\t\t0x0044\n#define REG_GPIO_INTM_8710B\t\t\t\t0x0048\n#define REG_LEDCFG0_8710B\t\t\t\t0x004C\n#define REG_LEDCFG1_8710B\t\t\t\t0x004D\n#define REG_LEDCFG2_8710B\t\t\t\t0x004E\n#define REG_LEDCFG3_8710B\t\t\t\t0x004F\n#define REG_FSIMR_8710B\t\t\t\t\t0x0050\n#define REG_FSISR_8710B\t\t\t\t\t0x0054\n#define REG_HSIMR_8710B\t\t\t\t\t0x0058\n#define REG_HSISR_8710B\t\t\t\t\t0x005c\n#define REG_GPIO_EXT_CTRL\t\t\t\t0x0060\n#define REG_PAD_CTRL1_8710B\t\t0x0064\n#define REG_MULTI_FUNC_CTRL_8710B\t\t0x0068\n#define REG_GPIO_STATUS_8710B\t\t\t0x006C\n#define REG_SDIO_CTRL_8710B\t\t\t\t0x0070\n#define REG_OPT_CTRL_8710B\t\t\t\t0x0074\n#define REG_AFE_CTRL_4_8710B\t\t0x0078\n#define REG_MCUFWDL_8710B\t\t\t\t0x0080\n#define REG_8051FW_CTRL_8710B\t\t\t0x0080\n#define REG_HMEBOX_DBG_0_8710B\t0x0088\n#define REG_HMEBOX_DBG_1_8710B\t0x008A\n#define REG_HMEBOX_DBG_2_8710B\t0x008C\n#define REG_HMEBOX_DBG_3_8710B\t0x008E\n#define REG_WLLPS_CTRL\t\t0x0090\n\n#define REG_PMC_DBG_CTRL2_8710B\t\t\t0x00CC\n#define\tREG_EFUSE_BURN_GNT_8710B\t\t0x00CF\n#define REG_HPON_FSM_8710B\t\t\t\t0x00EC\n#define REG_SYS_CFG1_8710B\t\t\t\t0x00F0\n#define REG_SYS_CFG_8710B\t\t\t\t0x00FC\n#define REG_ROM_VERSION\t\t\t\t\t0x00FD\n\n/* -----------------------------------------------------\n *\n *\t0x0100h ~ 0x01FFh\tMACTOP General Configuration\n *\n * ----------------------------------------------------- */\n#define REG_C2HEVT_CMD_ID_8710B\t0x01A0\n#define REG_C2HEVT_CMD_SEQ_88XX\t\t0x01A1\n#define REG_C2hEVT_CMD_CONTENT_88XX\t0x01A2\n#define REG_C2HEVT_CMD_LEN_8710B        0x01AE\n#define REG_C2HEVT_CLEAR_8710B\t\t\t0x01AF\n#define REG_MCUTST_1_8710B\t\t\t\t0x01C0\n#define REG_WOWLAN_WAKE_REASON 0x01C7\n#define REG_FMETHR_8710B\t\t\t\t0x01C8\n#define REG_HMETFR_8710B\t\t\t\t0x01CC\n#define REG_HMEBOX_0_8710B\t\t\t\t0x01D0\n#define REG_HMEBOX_1_8710B\t\t\t\t0x01D4\n#define REG_HMEBOX_2_8710B\t\t\t\t0x01D8\n#define REG_HMEBOX_3_8710B\t\t\t\t0x01DC\n#define REG_LLT_INIT_8710B\t\t\t\t0x01E0\n#define REG_HMEBOX_EXT0_8710B\t\t\t0x01F0\n#define REG_HMEBOX_EXT1_8710B\t\t\t0x01F4\n#define REG_HMEBOX_EXT2_8710B\t\t\t0x01F8\n#define REG_HMEBOX_EXT3_8710B\t\t\t0x01FC\n\n/* -----------------------------------------------------\n *\n *\t0x0200h ~ 0x027Fh\tTXDMA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_RQPN_8710B\t\t\t\t\t0x0200\n#define REG_FIFOPAGE_8710B\t\t\t\t0x0204\n#define REG_DWBCN0_CTRL_8710B\t\t\tREG_TDECTRL\n#define REG_TXDMA_OFFSET_CHK_8710B\t0x020C\n#define REG_TXDMA_STATUS_8710B\t\t0x0210\n#define REG_RQPN_NPQ_8710B\t\t\t0x0214\n#define REG_DWBCN1_CTRL_8710B\t\t\t0x0228\n\n\n/* -----------------------------------------------------\n *\n *\t0x0280h ~ 0x02FFh\tRXDMA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_RXDMA_AGG_PG_TH_8710B\t\t0x0280\n#define REG_FW_UPD_RDPTR_8710B\t\t0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */\n#define REG_RXDMA_CONTROL_8710B\t\t0x0286 /* Control the RX DMA. */\n#define REG_RXDMA_STATUS_8710B\t\t\t0x0288\n#define REG_RXDMA_MODE_CTRL_8710B\t\t0x0290\n#define REG_EARLY_MODE_CONTROL_8710B\t0x02BC\n#define REG_RSVD5_8710B\t\t\t\t\t0x02F0\n#define REG_RSVD6_8710B\t\t\t\t\t0x02F4\n\n/* -----------------------------------------------------\n *\n *\t0x0300h ~ 0x03FFh\tPCIe\n *\n * ----------------------------------------------------- */\n#define\tREG_PCIE_CTRL_REG_8710B\t\t\t0x0300\n#define\tREG_INT_MIG_8710B\t\t\t\t0x0304\t/* Interrupt Migration */\n#define\tREG_BCNQ_TXBD_DESA_8710B\t\t0x0308\t/* TX Beacon Descriptor Address */\n#define\tREG_MGQ_TXBD_DESA_8710B\t\t\t0x0310\t/* TX Manage Queue Descriptor Address */\n#define\tREG_VOQ_TXBD_DESA_8710B\t\t\t0x0318\t/* TX VO Queue Descriptor Address */\n#define\tREG_VIQ_TXBD_DESA_8710B\t\t\t0x0320\t/* TX VI Queue Descriptor Address */\n#define\tREG_BEQ_TXBD_DESA_8710B\t\t\t0x0328\t/* TX BE Queue Descriptor Address */\n#define\tREG_BKQ_TXBD_DESA_8710B\t\t\t0x0330\t/* TX BK Queue Descriptor Address */\n#define\tREG_RXQ_RXBD_DESA_8710B\t\t\t0x0338\t/* RX Queue\tDescriptor Address */\n#define REG_HI0Q_TXBD_DESA_8710B\t\t0x0340\n#define REG_HI1Q_TXBD_DESA_8710B\t\t0x0348\n#define REG_HI2Q_TXBD_DESA_8710B\t\t0x0350\n#define REG_HI3Q_TXBD_DESA_8710B\t\t0x0358\n#define REG_HI4Q_TXBD_DESA_8710B\t\t0x0360\n#define REG_HI5Q_TXBD_DESA_8710B\t\t0x0368\n#define REG_HI6Q_TXBD_DESA_8710B\t\t0x0370\n#define REG_HI7Q_TXBD_DESA_8710B\t\t0x0378\n#define\tREG_MGQ_TXBD_NUM_8710B\t\t\t0x0380\n#define\tREG_RX_RXBD_NUM_8710B\t\t\t0x0382\n#define\tREG_VOQ_TXBD_NUM_8710B\t\t\t0x0384\n#define\tREG_VIQ_TXBD_NUM_8710B\t\t\t0x0386\n#define\tREG_BEQ_TXBD_NUM_8710B\t\t\t0x0388\n#define\tREG_BKQ_TXBD_NUM_8710B\t\t\t0x038A\n#define\tREG_HI0Q_TXBD_NUM_8710B\t\t\t0x038C\n#define\tREG_HI1Q_TXBD_NUM_8710B\t\t\t0x038E\n#define\tREG_HI2Q_TXBD_NUM_8710B\t\t\t0x0390\n#define\tREG_HI3Q_TXBD_NUM_8710B\t\t\t0x0392\n#define\tREG_HI4Q_TXBD_NUM_8710B\t\t\t0x0394\n#define\tREG_HI5Q_TXBD_NUM_8710B\t\t\t0x0396\n#define\tREG_HI6Q_TXBD_NUM_8710B\t\t\t0x0398\n#define\tREG_HI7Q_TXBD_NUM_8710B\t\t\t0x039A\n#define\tREG_TSFTIMER_HCI_8710B\t\t\t0x039C\n#define\tREG_BD_RW_PTR_CLR_8710B\t\t\t0x039C\n\n/* Read Write Point */\n#define\tREG_VOQ_TXBD_IDX_8710B\t\t\t0x03A0\n#define\tREG_VIQ_TXBD_IDX_8710B\t\t\t0x03A4\n#define\tREG_BEQ_TXBD_IDX_8710B\t\t\t0x03A8\n#define\tREG_BKQ_TXBD_IDX_8710B\t\t\t0x03AC\n#define\tREG_MGQ_TXBD_IDX_8710B\t\t\t0x03B0\n#define\tREG_RXQ_TXBD_IDX_8710B\t\t\t0x03B4\n#define\tREG_HI0Q_TXBD_IDX_8710B\t\t\t0x03B8\n#define\tREG_HI1Q_TXBD_IDX_8710B\t\t\t0x03BC\n#define\tREG_HI2Q_TXBD_IDX_8710B\t\t\t0x03C0\n#define\tREG_HI3Q_TXBD_IDX_8710B\t\t\t0x03C4\n#define\tREG_HI4Q_TXBD_IDX_8710B\t\t\t0x03C8\n#define\tREG_HI5Q_TXBD_IDX_8710B\t\t\t0x03CC\n#define\tREG_HI6Q_TXBD_IDX_8710B\t\t\t0x03D0\n#define\tREG_HI7Q_TXBD_IDX_8710B\t\t\t0x03D4\n\n#define\tREG_PCIE_HCPWM_8710BE\t\t\t0x03D8 /* ?????? */\n#define\tREG_PCIE_HRPWM_8710BE\t\t\t0x03DC\t/* PCIe RPWM  ?????? */\n#define\tREG_DBI_WDATA_V1_8710B\t\t\t0x03E8\n#define\tREG_DBI_RDATA_V1_8710B\t\t\t0x03EC\n#define\tREG_DBI_FLAG_V1_8710B\t\t\t0x03F0\n#define REG_MDIO_V1_8710B\t\t\t\t0x03F4\n#define REG_PCIE_MIX_CFG_8710B\t\t\t0x03F8\n#define REG_HCI_MIX_CFG_8710B\t\t\t0x03FC\n\n/* -----------------------------------------------------\n *\n *\t0x0400h ~ 0x047Fh\tProtocol Configuration\n *\n * ----------------------------------------------------- */\n#define REG_VOQ_INFORMATION_8710B\t\t0x0400\n#define REG_VIQ_INFORMATION_8710B\t\t0x0404\n#define REG_BEQ_INFORMATION_8710B\t\t0x0408\n#define REG_BKQ_INFORMATION_8710B\t\t0x040C\n#define REG_MGQ_INFORMATION_8710B\t\t0x0410\n#define REG_HGQ_INFORMATION_8710B\t\t0x0414\n#define REG_BCNQ_INFORMATION_8710B\t0x0418\n#define REG_TXPKT_EMPTY_8710B\t\t\t0x041A\n\n#define REG_FWHW_TXQ_CTRL_8710B\t\t0x0420\n#define REG_HWSEQ_CTRL_8710B\t\t\t0x0423\n#define REG_TXPKTBUF_BCNQ_BDNY_8710B\t0x0424\n#define REG_TXPKTBUF_MGQ_BDNY_8710B\t0x0425\n#define REG_LIFECTRL_CTRL_8710B\t\t\t0x0426\n#define REG_MULTI_BCNQ_OFFSET_8710B\t0x0427\n#define REG_SPEC_SIFS_8710B\t\t\t\t0x0428\n#define REG_RL_8710B\t\t\t\t\t\t0x042A\n#define REG_TXBF_CTRL_8710B\t\t\t\t0x042C\n#define REG_DARFRC_8710B\t\t\t\t0x0430\n#define REG_RARFRC_8710B\t\t\t\t0x0438\n#define REG_RRSR_8710B\t\t\t\t\t0x0440\n#define REG_ARFR0_8710B\t\t\t\t\t0x0444\n#define REG_ARFR1_8710B\t\t\t\t\t0x044C\n#define REG_CCK_CHECK_8710B\t\t\t\t0x0454\n#define REG_AMPDU_MAX_TIME_8710B\t\t0x0456\n#define REG_TXPKTBUF_BCNQ_BDNY1_8710B\t0x0457\n\n#define REG_AMPDU_MAX_LENGTH_8710B\t0x0458\n#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8710B\t0x045D\n#define REG_NDPA_OPT_CTRL_8710B\t\t0x045F\n#define REG_FAST_EDCA_CTRL_8710B\t\t0x0460\n#define REG_RD_RESP_PKT_TH_8710B\t\t0x0463\n#define REG_DATA_SC_8710B\t\t\t\t0x0483\n#ifdef CONFIG_WOWLAN\n\t#define REG_TXPKTBUF_IV_LOW             0x0484\n\t#define REG_TXPKTBUF_IV_HIGH            0x0488\n#endif\n#define REG_TXRPT_START_OFFSET\t\t0x04AC\n#define REG_POWER_STAGE1_8710B\t\t0x04B4\n#define REG_POWER_STAGE2_8710B\t\t0x04B8\n#define REG_AMPDU_BURST_MODE_8710B\t0x04BC\n#define REG_PKT_VO_VI_LIFE_TIME_8710B\t0x04C0\n#define REG_PKT_BE_BK_LIFE_TIME_8710B\t0x04C2\n#define REG_STBC_SETTING_8710B\t\t\t0x04C4\n#define REG_HT_SINGLE_AMPDU_8710B\t\t0x04C7\n#define REG_PROT_MODE_CTRL_8710B\t\t0x04C8\n#define REG_MAX_AGGR_NUM_8710B\t\t0x04CA\n#define REG_RTS_MAX_AGGR_NUM_8710B\t0x04CB\n#define REG_BAR_MODE_CTRL_8710B\t\t0x04CC\n#define REG_RA_TRY_RATE_AGG_LMT_8710B\t0x04CF\n#define REG_MACID_PKT_DROP0_8710B\t\t0x04D0\n#define REG_MACID_PKT_SLEEP_8710B\t\t0x04D4\n\n/* -----------------------------------------------------\n *\n *\t0x0500h ~ 0x05FFh\tEDCA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_EDCA_VO_PARAM_8710B\t\t0x0500\n#define REG_EDCA_VI_PARAM_8710B\t\t0x0504\n#define REG_EDCA_BE_PARAM_8710B\t\t0x0508\n#define REG_EDCA_BK_PARAM_8710B\t\t0x050C\n#define REG_BCNTCFG_8710B\t\t\t\t0x0510\n#define REG_PIFS_8710B\t\t\t\t\t0x0512\n#define REG_RDG_PIFS_8710B\t\t\t\t0x0513\n#define REG_SIFS_CTX_8710B\t\t\t\t0x0514\n#define REG_SIFS_TRX_8710B\t\t\t\t0x0516\n#define REG_AGGR_BREAK_TIME_8710B\t\t0x051A\n#define REG_SLOT_8710B\t\t\t\t\t0x051B\n#define REG_TX_PTCL_CTRL_8710B\t\t\t0x0520\n#define REG_TXPAUSE_8710B\t\t\t\t0x0522\n#define REG_DIS_TXREQ_CLR_8710B\t\t0x0523\n#define REG_RD_CTRL_8710B\t\t\t\t0x0524\n/*\n * Format for offset 540h-542h:\n *\t[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.\n *\t[7:4]:   Reserved.\n *\t[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.\n *\t[23:20]: Reserved\n * Description:\n *\t              |\n * |<--Setup--|--Hold------------>|\n *\t--------------|----------------------\n * |\n * TBTT\n * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.\n * Described by Designer Tim and Bruce, 2011-01-14.\n *   */\n#define REG_TBTT_PROHIBIT_8710B\t\t\t0x0540\n#define REG_RD_NAV_NXT_8710B\t\t\t0x0544\n#define REG_NAV_PROT_LEN_8710B\t\t\t0x0546\n#define REG_BCN_CTRL_8710B\t\t\t\t0x0550\n#define REG_BCN_CTRL_1_8710B\t\t\t0x0551\n#define REG_MBID_NUM_8710B\t\t\t\t0x0552\n#define REG_DUAL_TSF_RST_8710B\t\t\t0x0553\n#define REG_BCN_INTERVAL_8710B\t\t\t0x0554\n#define REG_DRVERLYINT_8710B\t\t\t0x0558\n#define REG_BCNDMATIM_8710B\t\t\t0x0559\n#define REG_ATIMWND_8710B\t\t\t\t0x055A\n#define REG_USTIME_TSF_8710B\t\t\t0x055C\n#define REG_BCN_MAX_ERR_8710B\t\t\t0x055D\n#define REG_RXTSF_OFFSET_CCK_8710B\t\t0x055E\n#define REG_RXTSF_OFFSET_OFDM_8710B\t0x055F\n#define REG_TSFTR_8710B\t\t\t\t\t0x0560\n#define REG_CTWND_8710B\t\t\t\t\t0x0572\n#define REG_SECONDARY_CCA_CTRL_8710B\t0x0577\n#define REG_PSTIMER_8710B\t\t\t\t0x0580\n#define REG_TIMER0_8710B\t\t\t\t0x0584\n#define REG_TIMER1_8710B\t\t\t\t0x0588\n#define REG_ACMHWCTRL_8710B\t\t\t0x05C0\n#define REG_SCH_TXCMD_8710B\t\t\t0x05F8\n\n/* -----------------------------------------------------\n *\n *\t0x0600h ~ 0x07FFh\tWMAC Configuration\n *\n * ----------------------------------------------------- */\n#define REG_MAC_CR_8710B\t\t\t\t0x0600\n#define REG_TCR_8710B\t\t\t\t\t0x0604\n#define REG_RCR_8710B\t\t\t\t\t0x0608\n#define REG_RX_PKT_LIMIT_8710B\t\t\t0x060C\n#define REG_RX_DLK_TIME_8710B\t\t\t0x060D\n#define REG_RX_DRVINFO_SZ_8710B\t\t0x060F\n\n#define REG_MACID_8710B\t\t\t\t\t0x0610\n#define REG_BSSID_8710B\t\t\t\t\t0x0618\n#define REG_MAR_8710B\t\t\t\t\t0x0620\n#define REG_MBIDCAMCFG_8710B\t\t\t0x0628\n#define REG_WOWLAN_GTK_DBG1\t0x630\n#define REG_WOWLAN_GTK_DBG2\t0x634\n\n#define REG_USTIME_EDCA_8710B\t\t\t0x0638\n#define REG_MAC_SPEC_SIFS_8710B\t\t0x063A\n#define REG_RESP_SIFP_CCK_8710B\t\t\t0x063C\n#define REG_RESP_SIFS_OFDM_8710B\t\t0x063E\n#define REG_ACKTO_8710B\t\t\t\t\t0x0640\n#define REG_CTS2TO_8710B\t\t\t\t0x0641\n#define REG_EIFS_8710B\t\t\t\t\t0x0642\n\n#define REG_NAV_UPPER_8710B\t\t\t0x0652\t/* unit of 128 */\n#define REG_TRXPTCL_CTL_8710B\t\t\t0x0668\n\n/* Security */\n#define REG_CAMCMD_8710B\t\t\t\t0x0670\n#define REG_CAMWRITE_8710B\t\t\t\t0x0674\n#define REG_CAMREAD_8710B\t\t\t\t0x0678\n#define REG_CAMDBG_8710B\t\t\t\t0x067C\n#define REG_SECCFG_8710B\t\t\t\t0x0680\n\n/* Power */\n#define REG_WOW_CTRL_8710B\t\t\t\t0x0690\n#define REG_PS_RX_INFO_8710B\t\t\t0x0692\n#define REG_UAPSD_TID_8710B\t\t\t\t0x0693\n#define REG_WKFMCAM_CMD_8710B\t\t\t0x0698\n#define REG_WKFMCAM_NUM_8710B\t\t\t0x0698\n#define REG_WKFMCAM_RWD_8710B\t\t\t0x069C\n#define REG_RXFLTMAP0_8710B\t\t\t\t0x06A0\n#define REG_RXFLTMAP1_8710B\t\t\t\t0x06A2\n#define REG_RXFLTMAP2_8710B\t\t\t\t0x06A4\n#define REG_BCN_PSR_RPT_8710B\t\t\t0x06A8\n#define REG_BT_COEX_TABLE_8710B\t\t0x06C0\n#define REG_BFMER0_INFO_8710B\t\t\t0x06E4\n#define REG_BFMER1_INFO_8710B\t\t\t0x06EC\n#define REG_CSI_RPT_PARAM_BW20_8710B\t0x06F4\n#define REG_CSI_RPT_PARAM_BW40_8710B\t0x06F8\n#define REG_CSI_RPT_PARAM_BW80_8710B\t0x06FC\n\n/* Hardware Port 2 */\n#define REG_MACID1_8710B\t\t\t\t0x0700\n#define REG_BSSID1_8710B\t\t\t\t0x0708\n#define REG_BFMEE_SEL_8710B\t\t\t\t0x0714\n#define REG_SND_PTCL_CTRL_8710B\t\t0x0718\n\n/* LTR */\n#define REG_LTR_CTRL_BASIC_8710B\t\t0x07A4\n#define REG_LTR_IDLE_LATENCY_V1_8710B\t\t0x0798\n#define REG_LTR_ACTIVE_LATENCY_V1_8710B\t\t0x079C\n\n/* LTE_COEX */\n#define REG_LTECOEX_CTRL\t\t\t0x07C0\n#define REG_LTECOEX_WRITE_DATA\t\t0x07C4\n#define REG_LTECOEX_READ_DATA\t\t0x07C8\n#define REG_LTECOEX_PATH_CONTROL\t0x70\n\n/* Other */\n#define REG_USB_ACCESS_TIMEOUT 0xFE4C\n\n/* -----------------------------------------------------\n * SYSON_REG_SPEC\n * ----------------------------------------------------- */\n#define SYSON_REG_BASE_ADDR_8710B 0x40000000\n#define REG_SYS_XTAL_CTRL0\t0x0060\n#define REG_SYS_SYSTEM_CFG0 0x1F0\n#define REG_SYS_SYSTEM_CFG1 0x1F4\n#define REG_SYS_SYSTEM_CFG2 0x1F8\n#define REG_SYS_EEPROM_CTRL0 0x0E0\n\n\n/* -----------------------------------------------------\n * Indirect_R/W_SPEC\n * ----------------------------------------------------- */\n#define NORMAL_REG_READ_OFFSET 0x83000000\n#define NORMAL_REG_WRITE_OFFSET 0x84000000\n#define EFUSE_READ_OFFSET 0x85000000\n#define EFUSE_WRITE_OFFSET 0x86000000\n\n\n/* -----------------------------------------------------\n * PAGE0_WLANON_REG_SPEC\n * ----------------------------------------------------- */\n#define PAGE0_OFFSET 0x0 // WLANON_PAGE0_REG needs to add an offset.\n\n\n\n/* ****************************************************************************\n *\t8723 Regsiter Bit and Content definition\n * **************************************************************************** */\n \n /* -----------------------------------------------------\n * REG_SYS_SYSTEM_CFG0 \n * ----------------------------------------------------- */\n#define BIT_RTL_ID_8710B BIT(16)\n\n#define BIT_MASK_CHIP_VER_8710B 0xf\n#define BIT_GET_CHIP_VER_8710B(x) ((x) & BIT_MASK_CHIP_VER_8710B)\n\n#define BIT_SHIFT_VENDOR_ID_8710B 4\n#define BIT_MASK_VENDOR_ID_8710B 0xf\n#define BIT_GET_VENDOR_ID_8710B(x) (((x) >> BIT_SHIFT_VENDOR_ID_8710B) & BIT_MASK_VENDOR_ID_8710B)\n\n /* -----------------------------------------------------\n * REG_SYS_SYSTEM_CFG1 \n * ----------------------------------------------------- */\n#define BIT_SPSLDO_SEL_8710B BIT(25)\n\n /* -----------------------------------------------------\n * REG_SYS_SYSTEM_CFG2 \n * ----------------------------------------------------- */\n#define BIT_MASK_RF_RL_ID_8710B 0xf\n#define BIT_GET_RF_RL_ID_8710B(x) ((x) & BIT_MASK_RF_RL_ID_8710B)\n\n /* -----------------------------------------------------\n * REG_SYS_SYSTEM_CFG2 \n * ----------------------------------------------------- */\n#define BIT_EERPOMSEL_8710B BIT(4)\n#define BIT_AUTOLOAD_SUS_8710B BIT(5)\n\n\n /* -----------------------------------------------------\n * Other\n * ----------------------------------------------------- */\n\n\n#define BIT_USB_RXDMA_AGG_EN\tBIT(31)\n#define RXDMA_AGG_MODE_EN\t\tBIT(1)\n\n#ifdef CONFIG_WOWLAN\n\t#define RXPKT_RELEASE_POLL\t\tBIT(16)\n\t#define RXDMA_IDLE\t\t\t\tBIT(17)\n\t#define RW_RELEASE_EN\t\t\tBIT(18)\n#endif\n\n/* 2 HSISR\n * interrupt mask which needs to clear */\n#define MASK_HSISR_CLEAR\t\t(HSISR_GPIO12_0_INT |\\\n\t\tHSISR_SPS_OCP_INT |\\\n\t\tHSISR_RON_INT |\\\n\t\tHSISR_PDNINT |\\\n\t\tHSISR_GPIO9_INT)\n\n#ifdef CONFIG_RF_POWER_TRIM\n\t#ifdef CONFIG_RTL8710B\n\t\t#define EEPROM_RF_GAIN_OFFSET\t\t\t0xC1\n\t#endif\n\n\t#define EEPROM_RF_GAIN_VAL\t\t\t\t0x1F6\n#endif /*CONFIG_RF_POWER_TRIM*/\n\n#endif /* __RTL8710B_SPEC_H__ */\n"
  },
  {
    "path": "include/rtl8710b_sreset.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8710B_SRESET_H_\n#define _RTL8710B_SRESET_H_\n\n#include <rtw_sreset.h>\n\n#ifdef DBG_CONFIG_ERROR_DETECT\n\textern void rtl8710b_sreset_xmit_status_check(_adapter *padapter);\n\textern void rtl8710b_sreset_linked_status_check(_adapter *padapter);\n#endif\n#endif\n"
  },
  {
    "path": "include/rtl8710b_xmit.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8710B_XMIT_H__\n#define __RTL8710B_XMIT_H__\n\n\n#define MAX_TID (15)\n\n\n#ifndef __INC_HAL8710BDESC_H\n#define __INC_HAL8710BDESC_H\n\n#define RX_STATUS_DESC_SIZE_8710B\t\t24\n#define RX_DRV_INFO_SIZE_UNIT_8710B 8\n\n\n/* DWORD 0 */\n#define SET_RX_STATUS_DESC_PKT_LEN_8710B(__pRxStatusDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)\n#define SET_RX_STATUS_DESC_EOR_8710B(__pRxStatusDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)\n#define SET_RX_STATUS_DESC_OWN_8710B(__pRxStatusDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)\n\n#define GET_RX_STATUS_DESC_PKT_LEN_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)\n#define GET_RX_STATUS_DESC_CRC32_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)\n#define GET_RX_STATUS_DESC_ICV_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)\n#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)\n#define GET_RX_STATUS_DESC_SECURITY_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)\n#define GET_RX_STATUS_DESC_QOS_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)\n#define GET_RX_STATUS_DESC_SHIFT_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)\n#define GET_RX_STATUS_DESC_PHY_STATUS_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)\n#define GET_RX_STATUS_DESC_SWDEC_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)\n#define GET_RX_STATUS_DESC_EOR_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)\n#define GET_RX_STATUS_DESC_OWN_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)\n\n/* DWORD 1 */\n#define GET_RX_STATUS_DESC_MACID_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)\n#define GET_RX_STATUS_DESC_TID_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)\n#define GET_RX_STATUS_DESC_AMSDU_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)\n#define GET_RX_STATUS_DESC_RXID_MATCH_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)\n#define GET_RX_STATUS_DESC_PAGGR_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)\n#define GET_RX_STATUS_DESC_A1_FIT_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)\n#define GET_RX_STATUS_DESC_CHKERR_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)\n#define GET_RX_STATUS_DESC_IPVER_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)\n#define GET_RX_STATUS_DESC_IS_TCPUDP__8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)\n#define GET_RX_STATUS_DESC_CHK_VLD_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)\n#define GET_RX_STATUS_DESC_PAM_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)\n#define GET_RX_STATUS_DESC_PWR_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)\n#define GET_RX_STATUS_DESC_MORE_DATA_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)\n#define GET_RX_STATUS_DESC_MORE_FRAG_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)\n#define GET_RX_STATUS_DESC_TYPE_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)\n#define GET_RX_STATUS_DESC_MC_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)\n#define GET_RX_STATUS_DESC_BC_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)\n\n/* DWORD 2 */\n#define GET_RX_STATUS_DESC_SEQ_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)\n#define GET_RX_STATUS_DESC_FRAG_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)\n#define GET_RX_STATUS_DESC_RX_IS_QOS_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)\n#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)\n#define GET_RX_STATUS_DESC_RPT_SEL_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)\n#define GET_RX_STATUS_DESC_FCS_OK_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)\n\n/* DWORD 3 */\n#define GET_RX_STATUS_DESC_RX_RATE_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)\n#define GET_RX_STATUS_DESC_HTC_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)\n#define GET_RX_STATUS_DESC_EOSP_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)\n#define GET_RX_STATUS_DESC_BSSID_FIT_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)\n#ifdef CONFIG_USB_RX_AGGREGATION\n#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)\n#endif\n#define GET_RX_STATUS_DESC_PATTERN_MATCH_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)\n#define GET_RX_STATUS_DESC_UNICAST_MATCH_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)\n#define GET_RX_STATUS_DESC_MAGIC_MATCH_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)\n\n/* DWORD 6 */\n#define GET_RX_STATUS_DESC_MATCH_ID_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7)\n\n/* DWORD 5 */\n#define GET_RX_STATUS_DESC_TSFL_8710B(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)\n\n#define GET_RX_STATUS_DESC_BUFF_ADDR_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)\n#define GET_RX_STATUS_DESC_BUFF_ADDR64_8710B(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)\n\n#define SET_RX_STATUS_DESC_BUFF_ADDR_8710B(__pRxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)\n\n\n/* Dword 0, rsvd: bit26, bit28 */\n#define GET_TX_DESC_OWN_8710B(__pTxDesc)\\\n\tLE_BITS_TO_4BYTE(__pTxDesc, 31, 1)\n\n#define SET_TX_DESC_PKT_SIZE_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)\n#define SET_TX_DESC_OFFSET_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)\n#define SET_TX_DESC_BMC_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)\n#define SET_TX_DESC_HTC_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)\n#define SET_TX_DESC_AMSDU_PAD_EN_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)\n#define SET_TX_DESC_NO_ACM_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)\n#define SET_TX_DESC_GF_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)\n\n/* Dword 1 */\n#define SET_TX_DESC_MACID_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)\n#define SET_TX_DESC_QUEUE_SEL_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)\n#define SET_TX_DESC_RDG_NAV_EXT_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)\n#define SET_TX_DESC_LSIG_TXOP_EN_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)\n#define SET_TX_DESC_PIFS_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)\n#define SET_TX_DESC_RATE_ID_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)\n#define SET_TX_DESC_EN_DESC_ID_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)\n#define SET_TX_DESC_SEC_TYPE_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)\n#define SET_TX_DESC_PKT_OFFSET_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)\n#define SET_TX_DESC_MORE_DATA_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)\n\n/* Dword 2  remove P_AID, G_ID field*/\n#define SET_TX_DESC_CCA_RTS_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)\n#define SET_TX_DESC_AGG_ENABLE_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)\n#define SET_TX_DESC_RDG_ENABLE_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)\n#define SET_TX_DESC_NULL0_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)\n#define SET_TX_DESC_NULL1_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)\n#define SET_TX_DESC_BK_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)\n#define SET_TX_DESC_MORE_FRAG_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)\n#define SET_TX_DESC_RAW_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)\n#define SET_TX_DESC_CCX_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)\n#define SET_TX_DESC_AMPDU_DENSITY_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)\n#define SET_TX_DESC_BT_INT_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)\n#define SET_TX_DESC_FTM_EN_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 30, 1, __Value)\n\n/* Dword 3 */\n#define SET_TX_DESC_NAV_USE_HDR_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)\n#define SET_TX_DESC_HWSEQ_SEL_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)\n#define SET_TX_DESC_USE_RATE_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)\n#define SET_TX_DESC_DISABLE_RTS_FB_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)\n#define SET_TX_DESC_DISABLE_FB_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)\n#define SET_TX_DESC_CTS2SELF_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)\n#define SET_TX_DESC_RTS_ENABLE_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)\n#define SET_TX_DESC_HW_RTS_ENABLE_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)\n#define SET_TX_DESC_PORT_ID_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 2, __Value)\n#define SET_TX_DESC_USE_MAX_LEN_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)\n#define SET_TX_DESC_MAX_AGG_NUM_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)\n#define SET_TX_DESC_AMPDU_MAX_TIME_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)\n\n/* Dword 4 */\n#define SET_TX_DESC_TX_RATE_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)\n#define SET_TX_DESC_TX_TRY_RATE_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)\n#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)\n#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)\n#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)\n#define SET_TX_DESC_DATA_RETRY_LIMIT_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)\n#define SET_TX_DESC_RTS_RATE_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)\n#define SET_TX_DESC_PCTS_EN_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)\n#define SET_TX_DESC_PCTS_MASK_IDX_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)\n\n/* Dword 5 */\n#define SET_TX_DESC_DATA_SC_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)\n#define SET_TX_DESC_DATA_SHORT_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)\n#define SET_TX_DESC_DATA_BW_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)\n#define SET_TX_DESC_DATA_STBC_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)\n#define SET_TX_DESC_RTS_STBC_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)\n#define SET_TX_DESC_RTS_SHORT_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)\n#define SET_TX_DESC_RTS_SC_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)\n#define SET_TX_DESC_PATH_A_EN_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value)\n#define SET_TX_DESC_TXPWR_OF_SET_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)\n\n/* Dword 6 */\n#define SET_TX_DESC_SW_DEFINE_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)\n#define SET_TX_DESC_MBSSID_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)\n#define SET_TX_DESC_RF_SEL_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)\n\n/* Dword 7 */\n#ifdef CONFIG_PCI_HCI\n#define SET_TX_DESC_TX_BUFFER_SIZE_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n#endif\n\n#ifdef CONFIG_USB_HCI\n#define SET_TX_DESC_TX_DESC_CHECKSUM_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n#endif\n\n#ifdef CONFIG_SDIO_HCI\n#define SET_TX_DESC_TX_TIMESTAMP_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)\n#endif\n\n#define SET_TX_DESC_USB_TXAGG_NUM_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)\n\n/* Dword 8 */\n#define SET_TX_DESC_RTS_RC_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)\n#define SET_TX_DESC_BAR_RC_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)\n#define SET_TX_DESC_DATA_RC_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)\n#define SET_TX_DESC_HWSEQ_EN_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)\n#define SET_TX_DESC_NEXTHEADPAGE_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)\n#define SET_TX_DESC_TAILPAGE_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)\n\n/* Dword 9 */\n#define SET_TX_DESC_PADDING_LEN_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)\n#define SET_TX_DESC_SEQ_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)\n#define SET_TX_DESC_FINAL_DATA_RATE_8710B(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)\n\n\n#define SET_EARLYMODE_PKTNUM_8710B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)\n#define SET_EARLYMODE_LEN0_8710B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)\n#define SET_EARLYMODE_LEN1_1_8710B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)\n#define SET_EARLYMODE_LEN1_2_8710B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)\n#define SET_EARLYMODE_LEN2_8710B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,\t__Value)\n#define SET_EARLYMODE_LEN3_8710B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)\n\n\n/*-----------------------------------------------------------------*/\n/*\tRTL8710B TX BUFFER DESC                                      */\n/*-----------------------------------------------------------------*/\n#ifdef CONFIG_64BIT_DMA\n\t#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)\n\t#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)\n\t#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)\n\t#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)\n#else\n\t#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)\n\t#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)\n\t#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)\n\t#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu)\t/* 64 BIT mode only */\n#endif\n/* ********************************************************* */\n\n/* 64 bits  -- 32 bits */\n/* =======     ======= */\n/* Dword 0     0 */\n#define SET_TX_BUFF_DESC_LEN_0_8710B(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)\n#define SET_TX_BUFF_DESC_PSB_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)\n#define SET_TX_BUFF_DESC_OWN_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)\n\n/* Dword 1     1 */\n#define SET_TX_BUFF_DESC_ADDR_LOW_0_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)\n#define GET_TX_BUFF_DESC_ADDR_LOW_0_8710B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)\n/* Dword 2     NA */\n#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value)\n#ifdef CONFIG_64BIT_DMA\n\t#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)\n#else\n\t#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc) 0\n#endif\n/* Dword 3     NA */\n/* RESERVED 0 */\n/* Dword 4     2 */\n#define SET_TX_BUFF_DESC_LEN_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value)\n#define SET_TX_BUFF_DESC_AMSDU_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value)\n/* Dword 5     3 */\n#define SET_TX_BUFF_DESC_ADDR_LOW_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value)\n/* Dword 6     NA */\n#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value)\n/* Dword 7     NA */\n/*RESERVED 0 */\n/* Dword 8     4 */\n#define SET_TX_BUFF_DESC_LEN_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value)\n#define SET_TX_BUFF_DESC_AMSDU_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value)\n/* Dword 9     5 */\n#define SET_TX_BUFF_DESC_ADDR_LOW_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value)\n/* Dword 10    NA */\n#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value)\n/* Dword 11    NA */\n/*RESERVED 0 */\n/* Dword 12    6 */\n#define SET_TX_BUFF_DESC_LEN_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value)\n#define SET_TX_BUFF_DESC_AMSDU_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value)\n/* Dword 13    7 */\n#define SET_TX_BUFF_DESC_ADDR_LOW_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value)\n/* Dword 14    NA */\n#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value)\n/* Dword 15    NA */\n/*RESERVED 0 */\n\n\n#endif\n/* -----------------------------------------------------------\n *\n *\tRate\n *\n * -----------------------------------------------------------\n * CCK Rates, TxHT = 0 */\n#define DESC8710B_RATE1M\t\t\t\t0x00\n#define DESC8710B_RATE2M\t\t\t\t0x01\n#define DESC8710B_RATE5_5M\t\t\t\t0x02\n#define DESC8710B_RATE11M\t\t\t\t0x03\n\n/* OFDM Rates, TxHT = 0 */\n#define DESC8710B_RATE6M\t\t\t\t0x04\n#define DESC8710B_RATE9M\t\t\t\t0x05\n#define DESC8710B_RATE12M\t\t\t\t0x06\n#define DESC8710B_RATE18M\t\t\t\t0x07\n#define DESC8710B_RATE24M\t\t\t\t0x08\n#define DESC8710B_RATE36M\t\t\t\t0x09\n#define DESC8710B_RATE48M\t\t\t\t0x0a\n#define DESC8710B_RATE54M\t\t\t\t0x0b\n\n/* MCS Rates, TxHT = 1 */\n#define DESC8710B_RATEMCS0\t\t\t\t0x0c\n#define DESC8710B_RATEMCS1\t\t\t\t0x0d\n#define DESC8710B_RATEMCS2\t\t\t\t0x0e\n#define DESC8710B_RATEMCS3\t\t\t\t0x0f\n#define DESC8710B_RATEMCS4\t\t\t\t0x10\n#define DESC8710B_RATEMCS5\t\t\t\t0x11\n#define DESC8710B_RATEMCS6\t\t\t\t0x12\n#define DESC8710B_RATEMCS7\t\t\t\t0x13\n#define DESC8710B_RATEMCS8\t\t\t\t0x14\n#define DESC8710B_RATEMCS9\t\t\t\t0x15\n#define DESC8710B_RATEMCS10\t\t0x16\n#define DESC8710B_RATEMCS11\t\t0x17\n#define DESC8710B_RATEMCS12\t\t0x18\n#define DESC8710B_RATEMCS13\t\t0x19\n#define DESC8710B_RATEMCS14\t\t0x1a\n#define DESC8710B_RATEMCS15\t\t0x1b\n#define DESC8710B_RATEVHTSS1MCS0\t\t0x2c\n#define DESC8710B_RATEVHTSS1MCS1\t\t0x2d\n#define DESC8710B_RATEVHTSS1MCS2\t\t0x2e\n#define DESC8710B_RATEVHTSS1MCS3\t\t0x2f\n#define DESC8710B_RATEVHTSS1MCS4\t\t0x30\n#define DESC8710B_RATEVHTSS1MCS5\t\t0x31\n#define DESC8710B_RATEVHTSS1MCS6\t\t0x32\n#define DESC8710B_RATEVHTSS1MCS7\t\t0x33\n#define DESC8710B_RATEVHTSS1MCS8\t\t0x34\n#define DESC8710B_RATEVHTSS1MCS9\t\t0x35\n#define DESC8710B_RATEVHTSS2MCS0\t\t0x36\n#define DESC8710B_RATEVHTSS2MCS1\t\t0x37\n#define DESC8710B_RATEVHTSS2MCS2\t\t0x38\n#define DESC8710B_RATEVHTSS2MCS3\t\t0x39\n#define DESC8710B_RATEVHTSS2MCS4\t\t0x3a\n#define DESC8710B_RATEVHTSS2MCS5\t\t0x3b\n#define DESC8710B_RATEVHTSS2MCS6\t\t0x3c\n#define DESC8710B_RATEVHTSS2MCS7\t\t0x3d\n#define DESC8710B_RATEVHTSS2MCS8\t\t0x3e\n#define DESC8710B_RATEVHTSS2MCS9\t\t0x3f\n\n\n#define\tRX_HAL_IS_CCK_RATE_8710B(pDesc)\\\n\t(GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE1M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE2M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE5_5M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE11M)\n\n#ifdef CONFIG_TRX_BD_ARCH\n\tstruct tx_desc;\n#endif\n\nvoid rtl8710b_cal_txdesc_chksum(struct tx_desc *ptxdesc);\nvoid rtl8710b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);\nvoid rtl8710b_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);\nvoid rtl8710b_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);\nvoid rtl8710b_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);\nvoid rtl8710b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);\n\n#if defined(CONFIG_CONCURRENT_MODE)\n\tvoid fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);\n#endif\nvoid fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\ts32 rtl8710bs_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8710bs_free_xmit_priv(PADAPTER padapter);\n\ts32 rtl8710bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8710bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\trtl8710bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8710bs_xmit_buf_handler(PADAPTER padapter);\n\tthread_return rtl8710bs_xmit_thread(thread_context context);\n\t#define hal_xmit_handler rtl8710bs_xmit_buf_handler\n#endif\n\n#ifdef CONFIG_USB_HCI\n\ts32 rtl8710bu_xmit_buf_handler(PADAPTER padapter);\n\t#define hal_xmit_handler rtl8710bu_xmit_buf_handler\n\ts32 rtl8710bu_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8710bu_free_xmit_priv(PADAPTER padapter);\n\ts32 rtl8710bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8710bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\t rtl8710bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\tvoid rtl8710bu_xmit_tasklet(void *priv);\n\ts32 rtl8710bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\n\tvoid _dbg_dump_tx_info(_adapter\t*padapter, int frame_tag, struct tx_desc *ptxdesc);\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\ts32 rtl8710be_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8710be_free_xmit_priv(PADAPTER padapter);\n\tstruct xmit_buf *rtl8710be_dequeue_xmitbuf(struct rtw_tx_ring *ring);\n\tvoid\trtl8710be_xmitframe_resume(_adapter *padapter);\n\ts32 rtl8710be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8710be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\trtl8710be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\tvoid rtl8710be_xmit_tasklet(void *priv);\n#endif\n\nu8\tBWMapping_8710B(PADAPTER Adapter, struct pkt_attrib *pattrib);\nu8\tSCMapping_8710B(PADAPTER Adapter, struct pkt_attrib\t*pattrib);\n\n#endif\n"
  },
  {
    "path": "include/rtl8723b_cmd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8723B_CMD_H__\n#define __RTL8723B_CMD_H__\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\nenum h2c_cmd_8723B {\n\t/* Common Class: 000 */\n\tH2C_8723B_RSVD_PAGE = 0x00,\n\tH2C_8723B_MEDIA_STATUS_RPT = 0x01,\n\tH2C_8723B_SCAN_ENABLE = 0x02,\n\tH2C_8723B_KEEP_ALIVE = 0x03,\n\tH2C_8723B_DISCON_DECISION = 0x04,\n\tH2C_8723B_PSD_OFFLOAD = 0x05,\n\tH2C_8723B_AP_OFFLOAD = 0x08,\n\tH2C_8723B_BCN_RSVDPAGE = 0x09,\n\tH2C_8723B_PROBERSP_RSVDPAGE = 0x0A,\n\tH2C_8723B_FCS_RSVDPAGE = 0x10,\n\tH2C_8723B_FCS_INFO = 0x11,\n\tH2C_8723B_AP_WOW_GPIO_CTRL = 0x13,\n\n\t/* PoweSave Class: 001 */\n\tH2C_8723B_SET_PWR_MODE = 0x20,\n\tH2C_8723B_PS_TUNING_PARA = 0x21,\n\tH2C_8723B_PS_TUNING_PARA2 = 0x22,\n\tH2C_8723B_P2P_LPS_PARAM = 0x23,\n\tH2C_8723B_P2P_PS_OFFLOAD = 0x24,\n\tH2C_8723B_PS_SCAN_ENABLE = 0x25,\n\tH2C_8723B_SAP_PS_ = 0x26,\n\tH2C_8723B_INACTIVE_PS_ = 0x27, /* Inactive_PS */\n\tH2C_8723B_FWLPS_IN_IPS_ = 0x28,\n\n\t/* Dynamic Mechanism Class: 010 */\n\tH2C_8723B_MACID_CFG = 0x40,\n\tH2C_8723B_TXBF = 0x41,\n\tH2C_8723B_RSSI_SETTING = 0x42,\n\tH2C_8723B_AP_REQ_TXRPT = 0x43,\n\tH2C_8723B_INIT_RATE_COLLECT = 0x44,\n\tH2C_8723B_RA_PARA_ADJUST = 0x46,\n\n\t/* BT Class: 011 */\n\tH2C_8723B_B_TYPE_TDMA = 0x60,\n\tH2C_8723B_BT_INFO = 0x61,\n\tH2C_8723B_FORCE_BT_TXPWR = 0x62,\n\tH2C_8723B_BT_IGNORE_WLANACT = 0x63,\n\tH2C_8723B_DAC_SWING_VALUE = 0x64,\n\tH2C_8723B_ANT_SEL_RSV = 0x65,\n\tH2C_8723B_WL_OPMODE = 0x66,\n\tH2C_8723B_BT_MP_OPER = 0x67,\n\tH2C_8723B_BT_CONTROL = 0x68,\n\tH2C_8723B_BT_WIFI_CTRL = 0x69,\n\tH2C_8723B_BT_FW_PATCH = 0x6A,\n\tH2C_8723B_BT_WLAN_CALIBRATION = 0x6D,\n\n\t/* WOWLAN Class: 100 */\n\tH2C_8723B_WOWLAN = 0x80,\n\tH2C_8723B_REMOTE_WAKE_CTRL = 0x81,\n\tH2C_8723B_AOAC_GLOBAL_INFO = 0x82,\n\tH2C_8723B_AOAC_RSVD_PAGE = 0x83,\n\tH2C_8723B_AOAC_RSVD_PAGE2 = 0x84,\n\tH2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85,\n\tH2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86,\n\tH2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87,\n\tH2C_8723B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,\n\tH2C_8723B_P2P_OFFLOAD = 0x8B,\n\n\tH2C_8723B_RESET_TSF = 0xC0,\n\tH2C_8723B_MAXID,\n};\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------\n * ---------------------------------------------------------------------------------------------------------\n * _RSVDPAGE_LOC_CMD_0x00 */\n#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_8723B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8723B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8723B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n/* _KEEP_ALIVE_CMD_0x03 */\n#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_8723B_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)\n#define SET_8723B_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n\n/* _DISCONNECT_DECISION_CMD_0x04 */\n#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_8723B_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_8723B_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)\n\n/* _PWR_MOD_CMD_0x20 */\n#define SET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8723B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)\n#define SET_8723B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)\n#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8723B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)\n#define SET_8723B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n#define GET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)\t\t\t\t\tLE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)\n\n/* _PS_TUNE_PARAM_CMD_0x21 */\n#define SET_8723B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8723B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_8723B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)\n#define SET_8723B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)\n#define SET_8723B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n\n/* _MACID_CFG_CMD_0x40 */\n#define SET_8723B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8723B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)\n#define SET_8723B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)\n#define SET_8723B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)\n#define SET_8723B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)\n#define SET_8723B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)\n#define SET_8723B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)\n#define SET_8723B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)\n#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)\n#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)\n#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)\n\n/* _RSSI_SETTING_CMD_0x42 */\n#define SET_8723B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8723B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)\n#define SET_8723B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n\n/* _AP_REQ_TXRPT_CMD_0x43 */\n#define SET_8723B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8723B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n\n/* _FORCE_BT_TXPWR_CMD_0x62 */\n#define SET_8723B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n\n/* _FORCE_BT_MP_OPER_CMD_0x67 */\n#define SET_8723B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)\n#define SET_8723B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)\n#define SET_8723B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_8723B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)\n#define SET_8723B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n#define SET_8723B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)\n\n/* _BT_FW_PATCH_0x6A */\n#define SET_8723B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)\n#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)\n\n/* ---------------------------------------------------------------------------------------------------------\n * -------------------------------------------    Structure    --------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    Function Statement     --------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\n/* host message to firmware cmd */\nvoid rtl8723b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);\nvoid rtl8723b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);\nvoid rtl8723b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);\n/* s32 rtl8723b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */\nvoid rtl8723b_set_FwPsTuneParam_cmd(PADAPTER padapter);\nvoid rtl8723b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);\nvoid rtl8723b_download_rsvd_page(PADAPTER padapter, u8 mstatus);\n#ifdef CONFIG_BT_COEXIST\n\tvoid rtl8723b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);\n#endif /* CONFIG_BT_COEXIST */\n#ifdef CONFIG_P2P\n\tvoid rtl8723b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_TDLS\n\t#ifdef CONFIG_TDLS_CH_SW\n\t\tvoid rtl8723b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);\n\t#endif\n#endif\n\n#ifdef CONFIG_P2P_WOWLAN\n\tvoid rtl8723b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);\n#endif\n\nvoid rtl8723b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);\n\ns32 FillH2CCmd8723B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);\nu8 GetTxBufferRsvdPageNum8723B(_adapter *padapter, bool wowlan);\n#endif\n"
  },
  {
    "path": "include/rtl8723b_dm.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8723B_DM_H__\n#define __RTL8723B_DM_H__\n/* ************************************************************\n * Description:\n *\n * This file is for 8723B dynamic mechanism only\n *\n *\n * ************************************************************ */\n\n/* ************************************************************\n * structure and define\n * ************************************************************ */\n\n/* ************************************************************\n * function prototype\n * ************************************************************ */\n\nvoid rtl8723b_init_dm_priv(PADAPTER padapter);\nvoid rtl8723b_deinit_dm_priv(PADAPTER padapter);\n\nvoid rtl8723b_InitHalDm(PADAPTER padapter);\nvoid rtl8723b_HalDmWatchDog(PADAPTER padapter);\n#endif\n"
  },
  {
    "path": "include/rtl8723b_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8723B_HAL_H__\n#define __RTL8723B_HAL_H__\n\n#include \"hal_data.h\"\n\n#include \"rtl8723b_spec.h\"\n#include \"rtl8723b_rf.h\"\n#include \"rtl8723b_dm.h\"\n#include \"rtl8723b_recv.h\"\n#include \"rtl8723b_xmit.h\"\n#include \"rtl8723b_cmd.h\"\n#include \"rtl8723b_led.h\"\n#include \"Hal8723BPwrSeq.h\"\n#include \"Hal8723BPhyReg.h\"\n#include \"Hal8723BPhyCfg.h\"\n#ifdef DBG_CONFIG_ERROR_DETECT\n\t#include \"rtl8723b_sreset.h\"\n#endif\n\n#define FW_8723B_SIZE\t\t\t0x8000\n#define FW_8723B_START_ADDRESS\t0x1000\n#define FW_8723B_END_ADDRESS\t\t0x1FFF /* 0x5FFF */\n\n#define IS_FW_HEADER_EXIST_8723B(_pFwHdr)\t((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x5300)\n\ntypedef struct _RT_FIRMWARE {\n\tFIRMWARE_SOURCE\teFWSource;\n#ifdef CONFIG_EMBEDDED_FWIMG\n\tu8\t\t\t*szFwBuffer;\n#else\n\tu8\t\t\tszFwBuffer[FW_8723B_SIZE];\n#endif\n\tu32\t\t\tulFwLength;\n} RT_FIRMWARE_8723B, *PRT_FIRMWARE_8723B;\n\n/*\n * This structure must be cared byte-ordering\n *\n * Added by tynli. 2009.12.04. */\ntypedef struct _RT_8723B_FIRMWARE_HDR {\n\t/* 8-byte alinment required */\n\n\t/* --- LONG WORD 0 ---- */\n\tu16\t\tSignature;\t/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */\n\tu8\t\tCategory;\t/* AP/NIC and USB/PCI */\n\tu8\t\tFunction;\t/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */\n\tu16\t\tVersion;\t\t/* FW Version */\n\tu16\t\tSubversion;\t/* FW Subversion, default 0x00 */\n\n\t/* --- LONG WORD 1 ---- */\n\tu8\t\tMonth;\t/* Release time Month field */\n\tu8\t\tDate;\t/* Release time Date field */\n\tu8\t\tHour;\t/* Release time Hour field */\n\tu8\t\tMinute;\t/* Release time Minute field */\n\tu16\t\tRamCodeSize;\t/* The size of RAM code */\n\tu16\t\tRsvd2;\n\n\t/* --- LONG WORD 2 ---- */\n\tu32\t\tSvnIdx;\t/* The SVN entry index */\n\tu32\t\tRsvd3;\n\n\t/* --- LONG WORD 3 ---- */\n\tu32\t\tRsvd4;\n\tu32\t\tRsvd5;\n} RT_8723B_FIRMWARE_HDR, *PRT_8723B_FIRMWARE_HDR;\n\n#define DRIVER_EARLY_INT_TIME_8723B\t\t0x05\n#define BCN_DMA_ATIME_INT_TIME_8723B\t\t0x02\n\n/* for 8723B\n * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */\n#define PAGE_SIZE_TX_8723B\t\t\t128\n#define PAGE_SIZE_RX_8723B\t\t\t8\n\n#define TX_DMA_SIZE_8723B\t\t\t0x8000\t/* 32K(TX) */\n#define RX_DMA_SIZE_8723B\t\t\t0x4000\t/* 16K(RX) */\n\n#ifdef CONFIG_WOWLAN\n\t#define RESV_FMWF\t(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/\n#else\n\t#define RESV_FMWF\t0\n#endif\n\n#ifdef CONFIG_FW_C2H_DEBUG\n\t#define RX_DMA_RESERVED_SIZE_8723B\t0x100\t/* 256B, reserved for c2h debug message */\n#else\n\t#define RX_DMA_RESERVED_SIZE_8723B\t0x80\t/* 128B, reserved for tx report */\n#endif\n#define RX_DMA_BOUNDARY_8723B\t\t(RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B - 1)\n\n\n/* Note: We will divide number of page equally for each queue other than public queue! */\n\n/* For General Reserved Page Number(Beacon Queue is reserved page)\n * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8723B\n * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/\n#define BCNQ_PAGE_NUM_8723B\t\t(MAX_BEACON_LEN / PAGE_SIZE_TX_8723B + 6) /*0x08*/\n\n\n/* For WoWLan , more reserved page\n * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6\n * NS offload: 2 NDP info: 1\n */\n#ifdef CONFIG_WOWLAN\n\t#define WOWLAN_PAGE_NUM_8723B\t0x0b\n#else\n\t#define WOWLAN_PAGE_NUM_8723B\t0x00\n#endif\n\n#ifdef CONFIG_PNO_SUPPORT\n\t#undef WOWLAN_PAGE_NUM_8723B\n\t#define WOWLAN_PAGE_NUM_8723B\t0x15\n#endif\n\n#ifdef CONFIG_AP_WOWLAN\n\t#define AP_WOWLAN_PAGE_NUM_8723B\t0x02\n#endif\n\n#define TX_TOTAL_PAGE_NUMBER_8723B\t(0xFF - BCNQ_PAGE_NUM_8723B - WOWLAN_PAGE_NUM_8723B)\n#define TX_PAGE_BOUNDARY_8723B\t\t(TX_TOTAL_PAGE_NUMBER_8723B + 1)\n\n#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723B\tTX_TOTAL_PAGE_NUMBER_8723B\n#define WMM_NORMAL_TX_PAGE_BOUNDARY_8723B\t\t(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723B + 1)\n\n/* For Normal Chip Setting\n * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723B */\n#define NORMAL_PAGE_NUM_HPQ_8723B\t\t0x0C\n#define NORMAL_PAGE_NUM_LPQ_8723B\t\t0x02\n#define NORMAL_PAGE_NUM_NPQ_8723B\t\t0x02\n#define NORMAL_PAGE_NUM_EPQ_8723B\t\t0x04\n\n/* Note: For Normal Chip Setting, modify later */\n#define WMM_NORMAL_PAGE_NUM_HPQ_8723B\t\t0x30\n#define WMM_NORMAL_PAGE_NUM_LPQ_8723B\t\t0x20\n#define WMM_NORMAL_PAGE_NUM_NPQ_8723B\t\t0x20\n#define WMM_NORMAL_PAGE_NUM_EPQ_8723B\t\t0x00\n\n\n#include \"HalVerDef.h\"\n#include \"hal_com.h\"\n\n#define EFUSE_OOB_PROTECT_BYTES\t\t15\n\n#define HAL_EFUSE_MEMORY\n\n#define HWSET_MAX_SIZE_8723B\t\t\t512\n#define EFUSE_REAL_CONTENT_LEN_8723B\t\t512\n#define EFUSE_MAP_LEN_8723B\t\t\t\t512\n#define EFUSE_MAX_SECTION_8723B\t\t\t64\n\n#define EFUSE_IC_ID_OFFSET\t\t\t506\t/* For some inferiority IC purpose. added by Roger, 2009.09.02. */\n#define AVAILABLE_EFUSE_ADDR(addr)\t(addr < EFUSE_REAL_CONTENT_LEN_8723B)\n\n#define EFUSE_ACCESS_ON\t\t\t0x69\t/* For RTL8723 only. */\n#define EFUSE_ACCESS_OFF\t\t\t0x00\t/* For RTL8723 only. */\n\n/* ********************************************************\n *\t\t\tEFUSE for BT definition\n * ******************************************************** */\n#define EFUSE_BT_REAL_BANK_CONTENT_LEN\t512\n#define EFUSE_BT_REAL_CONTENT_LEN\t\t1536\t/* 512*3 */\n#define EFUSE_BT_MAP_LEN\t\t\t\t1024\t/* 1k bytes */\n#define EFUSE_BT_MAX_SECTION\t\t\t128\t\t/* 1024/8 */\n\n#define EFUSE_PROTECT_BYTES_BANK\t\t16\n\ntypedef enum tag_Package_Definition {\n\tPACKAGE_DEFAULT,\n\tPACKAGE_QFN68,\n\tPACKAGE_TFBGA90,\n\tPACKAGE_TFBGA80,\n\tPACKAGE_TFBGA79\n} PACKAGE_TYPE_E;\n\n#define INCLUDE_MULTI_FUNC_BT(_Adapter)\t\t(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)\n#define INCLUDE_MULTI_FUNC_GPS(_Adapter)\t(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)\n\n/* rtl8723a_hal_init.c */\ns32 rtl8723b_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);\nvoid rtl8723b_FirmwareSelfReset(PADAPTER padapter);\nvoid rtl8723b_InitializeFirmwareVars(PADAPTER padapter);\n\nvoid rtl8723b_InitAntenna_Selection(PADAPTER padapter);\nvoid rtl8723b_DeinitAntenna_Selection(PADAPTER padapter);\nvoid rtl8723b_CheckAntenna_Selection(PADAPTER padapter);\nvoid rtl8723b_init_default_value(PADAPTER padapter);\n\ns32 rtl8723b_InitLLTTable(PADAPTER padapter);\n\ns32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);\ns32 CardDisableWithoutHWSM(PADAPTER padapter);\n\n/* EFuse */\nu8 GetEEPROMSize8723B(PADAPTER padapter);\nvoid Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);\nvoid Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);\nvoid Hal_EfuseParseTxPowerInfo_8723B(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseBTCoexistInfo_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseEEPROMVer_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseChnlPlan_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseCustomerID_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseAntennaDiversity_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseXtal_8723B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);\nvoid Hal_EfuseParseThermalMeter_8723B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);\nvoid Hal_EfuseParsePackageType_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseVoltage_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN\tAutoLoadFail);\nvoid Hal_EfuseParseBoardType_8723B(PADAPTER Adapter,\tu8\t*PROMContent, BOOLEAN AutoloadFail);\n\nvoid rtl8723b_set_hal_ops(struct hal_ops *pHalFunc);\nvoid init_hal_spec_8723b(_adapter *adapter);\nu8 SetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val);\nvoid GetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val);\nu8 SetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);\nu8 GetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);\n\n/* register */\nvoid rtl8723b_InitBeaconParameters(PADAPTER padapter);\nvoid rtl8723b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);\nvoid\t_InitBurstPktLen_8723BS(PADAPTER Adapter);\nvoid _8051Reset8723(PADAPTER padapter);\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\n\tvoid Hal_DetectWoWMode(PADAPTER pAdapter);\n#endif /* CONFIG_WOWLAN */\n\nvoid rtl8723b_start_thread(_adapter *padapter);\nvoid rtl8723b_stop_thread(_adapter *padapter);\n\n#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)\n\tvoid rtl8723bs_init_checkbthang_workqueue(_adapter *adapter);\n\tvoid rtl8723bs_free_checkbthang_workqueue(_adapter *adapter);\n\tvoid rtl8723bs_cancle_checkbthang_workqueue(_adapter *adapter);\n\tvoid rtl8723bs_hal_check_bt_hang(_adapter *adapter);\n#endif\n\n#ifdef CONFIG_GPIO_WAKEUP\n\tvoid HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);\n#endif\n#ifdef CONFIG_MP_INCLUDED\nint FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);\n#endif\nvoid CCX_FwC2HTxRpt_8723b(PADAPTER padapter, u8 *pdata, u8 len);\n\nu8 MRateToHwRate8723B(u8  rate);\nu8 HwRateToMRate8723B(u8\t rate);\n\n#ifdef CONFIG_RF_POWER_TRIM\n\tvoid Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\n#endif /*CONFIG_RF_POWER_TRIM*/\n\n#ifdef CONFIG_PCI_HCI\n\tBOOLEAN\tInterruptRecognized8723BE(PADAPTER Adapter);\n\tvoid\tUpdateInterruptMask8723BE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);\n#endif\n\n#ifdef CONFIG_GPIO_API\nint rtl8723b_GpioFuncCheck(PADAPTER adapter, u8 gpio_num);\nvoid rtl8723b_GpioMultiFuncReset(PADAPTER adapter, u8 gpio_num);\n#endif\n\n#endif\n"
  },
  {
    "path": "include/rtl8723b_led.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8723B_LED_H__\n#define __RTL8723B_LED_H__\n\n#include <drv_conf.h>\n#include <osdep_service.h>\n#include <drv_types.h>\n\n#ifdef CONFIG_RTW_SW_LED\n/* ********************************************************************************\n * Interface to manipulate LED objects.\n * ******************************************************************************** */\n#ifdef CONFIG_USB_HCI\n\tvoid rtl8723bu_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8723bu_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_SDIO_HCI\n\tvoid rtl8723bs_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8723bs_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_GSPI_HCI\n\tvoid rtl8723bs_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8723bs_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_PCI_HCI\n\tvoid rtl8723be_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8723be_DeInitSwLeds(PADAPTER padapter);\n#endif\n\n#endif\n#endif/*CONFIG_RTW_SW_LED*/\n"
  },
  {
    "path": "include/rtl8723b_recv.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8723B_RECV_H__\n#define __RTL8723B_RECV_H__\n\n#define RECV_BLK_SZ 512\n#define RECV_BLK_CNT 16\n#define RECV_BLK_TH RECV_BLK_CNT\n\n#if defined(CONFIG_USB_HCI)\n\n\t#ifndef MAX_RECVBUF_SZ\n\t\t#ifndef CONFIG_MINIMAL_MEMORY_USAGE\n\t\t\t/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */\n\t\t\t/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */\n\t\t\t/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */\n\t\t\t#ifdef CONFIG_PLATFORM_MSTAR\n\t\t\t\t#define MAX_RECVBUF_SZ (8192) /* 8K */\n\t\t\t#else\n\t\t\t\t#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */\n\t\t\t#endif\n\t\t\t/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */\n\t\t#else\n\t\t\t#define MAX_RECVBUF_SZ (4000) /* about 4K */\n\t\t#endif\n\t#endif /* !MAX_RECVBUF_SZ */\n\n#elif defined(CONFIG_PCI_HCI)\n\t/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */\n\t/*\t#define MAX_RECVBUF_SZ (9100) */\n\t/* #else */\n\t#define MAX_RECVBUF_SZ (4000) /* about 4K\n\t* #endif */\n\n\n#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\n\t#define MAX_RECVBUF_SZ  (RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B)\n\n#endif\n\n/* Rx smooth factor */\n#define\tRx_Smooth_Factor (20)\n\n#ifdef CONFIG_SDIO_HCI\n\t#ifndef CONFIG_SDIO_RX_COPY\n\t\t#undef MAX_RECVBUF_SZ\n\t\t#define MAX_RECVBUF_SZ\t(RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B)\n\t#endif /* !CONFIG_SDIO_RX_COPY */\n#endif /* CONFIG_SDIO_HCI */\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\ts32 rtl8723bs_init_recv_priv(PADAPTER padapter);\n\tvoid rtl8723bs_free_recv_priv(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_USB_HCI\n\tint rtl8723bu_init_recv_priv(_adapter *padapter);\n\tvoid rtl8723bu_free_recv_priv(_adapter *padapter);\n\tvoid rtl8723bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\ts32 rtl8723be_init_recv_priv(PADAPTER padapter);\n\tvoid rtl8723be_free_recv_priv(PADAPTER padapter);\n#endif\n\nvoid rtl8723b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);\n\n#endif /* __RTL8723B_RECV_H__ */\n"
  },
  {
    "path": "include/rtl8723b_rf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8723B_RF_H__\n#define __RTL8723B_RF_H__\n\nint\tPHY_RF6052_Config8723B(PADAPTER\t\tAdapter);\n\nvoid\nPHY_RF6052SetBandwidth8723B(\n\t\tPADAPTER\t\t\t\tAdapter,\n\t\tenum channel_width\t\tBandwidth);\n\n#endif\n"
  },
  {
    "path": "include/rtl8723b_spec.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8723B_SPEC_H__\n#define __RTL8723B_SPEC_H__\n\n#include <drv_conf.h>\n\n\n#define HAL_NAV_UPPER_UNIT_8723B\t\t128\t\t/* micro-second */\n\n/* -----------------------------------------------------\n *\n *\t0x0000h ~ 0x00FFh\tSystem Configuration\n *\n * ----------------------------------------------------- */\n#define REG_RSV_CTRL_8723B\t\t\t\t0x001C\t/* 3 Byte */\n#define REG_BT_WIFI_ANTENNA_SWITCH_8723B\t0x0038\n#define REG_HSISR_8723B\t\t\t\t\t0x005c\n#define REG_PAD_CTRL1_8723B\t\t0x0064\n#define REG_AFE_CTRL_4_8723B\t\t0x0078\n#define REG_HMEBOX_DBG_0_8723B\t0x0088\n#define REG_HMEBOX_DBG_1_8723B\t0x008A\n#define REG_HMEBOX_DBG_2_8723B\t0x008C\n#define REG_HMEBOX_DBG_3_8723B\t0x008E\n#define REG_HIMR0_8723B\t\t\t\t\t0x00B0\n#define REG_HISR0_8723B\t\t\t\t\t0x00B4\n#define REG_HIMR1_8723B\t\t\t\t\t0x00B8\n#define REG_HISR1_8723B\t\t\t\t\t0x00BC\n#define REG_PMC_DBG_CTRL2_8723B\t\t\t0x00CC\n\n/* -----------------------------------------------------\n *\n *\t0x0100h ~ 0x01FFh\tMACTOP General Configuration\n *\n * ----------------------------------------------------- */\n#define REG_C2HEVT_CMD_ID_8723B\t0x01A0\n#define REG_C2HEVT_CMD_LEN_8723B\t0x01AE\n#define REG_WOWLAN_WAKE_REASON 0x01C7\n#define REG_WOWLAN_GTK_DBG1\t0x630\n#define REG_WOWLAN_GTK_DBG2\t0x634\n\n#define REG_HMEBOX_EXT0_8723B\t\t\t0x01F0\n#define REG_HMEBOX_EXT1_8723B\t\t\t0x01F4\n#define REG_HMEBOX_EXT2_8723B\t\t\t0x01F8\n#define REG_HMEBOX_EXT3_8723B\t\t\t0x01FC\n\n/* -----------------------------------------------------\n *\n *\t0x0200h ~ 0x027Fh\tTXDMA Configuration\n *\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n *\n *\t0x0280h ~ 0x02FFh\tRXDMA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_RXDMA_CONTROL_8723B\t\t0x0286 /* Control the RX DMA. */\n#define REG_RXDMA_MODE_CTRL_8723B\t\t0x0290\n\n/* -----------------------------------------------------\n *\n *\t0x0300h ~ 0x03FFh\tPCIe\n *\n * ----------------------------------------------------- */\n#define\tREG_PCIE_CTRL_REG_8723B\t\t0x0300\n#define\tREG_INT_MIG_8723B\t\t\t\t0x0304\t/* Interrupt Migration */\n#define\tREG_BCNQ_DESA_8723B\t\t\t0x0308\t/* TX Beacon Descriptor Address */\n#define\tREG_HQ_DESA_8723B\t\t\t\t0x0310\t/* TX High Queue Descriptor Address */\n#define\tREG_MGQ_DESA_8723B\t\t\t0x0318\t/* TX Manage Queue Descriptor Address */\n#define\tREG_VOQ_DESA_8723B\t\t\t0x0320\t/* TX VO Queue Descriptor Address */\n#define\tREG_VIQ_DESA_8723B\t\t\t\t0x0328\t/* TX VI Queue Descriptor Address */\n#define\tREG_BEQ_DESA_8723B\t\t\t0x0330\t/* TX BE Queue Descriptor Address */\n#define\tREG_BKQ_DESA_8723B\t\t\t0x0338\t/* TX BK Queue Descriptor Address */\n#define\tREG_RX_DESA_8723B\t\t\t\t0x0340\t/* RX Queue\tDescriptor Address */\n#define\tREG_DBI_WDATA_8723B\t\t\t0x0348\t/* DBI Write Data */\n#define\tREG_DBI_RDATA_8723B\t\t\t0x034C\t/* DBI Read Data */\n#define\tREG_DBI_ADDR_8723B\t\t\t\t0x0350\t/* DBI Address */\n#define\tREG_DBI_FLAG_8723B\t\t\t\t0x0352\t/* DBI Read/Write Flag */\n#define\tREG_MDIO_WDATA_8723B\t\t0x0354\t/* MDIO for Write PCIE PHY */\n#define\tREG_MDIO_RDATA_8723B\t\t\t0x0356\t/* MDIO for Reads PCIE PHY */\n#define\tREG_MDIO_CTL_8723B\t\t\t0x0358\t/* MDIO for Control */\n#define\tREG_DBG_SEL_8723B\t\t\t\t0x0360\t/* Debug Selection Register */\n#define\tREG_PCIE_HRPWM_8723B\t\t\t0x0361\t/* PCIe RPWM */\n#define\tREG_PCIE_HCPWM_8723B\t\t\t0x0363\t/* PCIe CPWM */\n#define\tREG_PCIE_MULTIFET_CTRL_8723B\t0x036A\t/* PCIE Multi-Fethc Control */\n\n/* -----------------------------------------------------\n *\n *\t0x0400h ~ 0x047Fh\tProtocol Configuration\n *\n * ----------------------------------------------------- */\n#define REG_TXPKTBUF_BCNQ_BDNY_8723B\t0x0424\n#define REG_TXPKTBUF_MGQ_BDNY_8723B\t0x0425\n#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B\t0x045D\n#ifdef CONFIG_WOWLAN\n\t#define REG_TXPKTBUF_IV_LOW             0x0484\n\t#define REG_TXPKTBUF_IV_HIGH            0x0488\n#endif\n#define REG_AMPDU_BURST_MODE_8723B\t0x04BC\n\n/* -----------------------------------------------------\n *\n *\t0x0500h ~ 0x05FFh\tEDCA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_SECONDARY_CCA_CTRL_8723B\t0x0577\n\n/* -----------------------------------------------------\n *\n *\t0x0600h ~ 0x07FFh\tWMAC Configuration\n *\n * ----------------------------------------------------- */\n\n\n/* ************************************************************\n * SDIO Bus Specification\n * ************************************************************ */\n\n/* -----------------------------------------------------\n * SDIO CMD Address Mapping\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n * I/O bus domain (Host)\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n * SDIO register\n * ----------------------------------------------------- */\n#define SDIO_REG_HCPWM1_8723B\t0x025 /* HCI Current Power Mode 1 */\n\n\n/* ****************************************************************************\n *\t8723 Regsiter Bit and Content definition\n * **************************************************************************** */\n\n/* 2 HSISR\n * interrupt mask which needs to clear */\n#define MASK_HSISR_CLEAR\t\t(HSISR_GPIO12_0_INT |\\\n\t\tHSISR_SPS_OCP_INT |\\\n\t\tHSISR_RON_INT |\\\n\t\tHSISR_PDNINT |\\\n\t\tHSISR_GPIO9_INT)\n\n/* -----------------------------------------------------\n *\n *\t0x0100h ~ 0x01FFh\tMACTOP General Configuration\n *\n * ----------------------------------------------------- */\n#undef IS_E_CUT\n#define IS_E_CUT(version)\t\tFALSE\n#undef IS_F_CUT\n#define IS_F_CUT(version)\t\t((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE)\n\n/* -----------------------------------------------------\n *\n *\t0x0200h ~ 0x027Fh\tTXDMA Configuration\n *\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n *\n *\t0x0280h ~ 0x02FFh\tRXDMA Configuration\n *\n * ----------------------------------------------------- */\n#define BIT_USB_RXDMA_AGG_EN\tBIT(31)\n#define RXDMA_AGG_MODE_EN\t\tBIT(1)\n\n#ifdef CONFIG_WOWLAN\n\t#define RXPKT_RELEASE_POLL\t\tBIT(16)\n\t#define RXDMA_IDLE\t\t\t\tBIT(17)\n\t#define RW_RELEASE_EN\t\t\tBIT(18)\n#endif\n\n/* -----------------------------------------------------\n *\n *\t0x0400h ~ 0x047Fh\tProtocol Configuration\n *\n * ----------------------------------------------------- */\n\n/* ----------------------------------------------------------------------------\n * 8723B REG_CCK_CHECK\t\t\t\t\t\t(offset 0x454)\n * ---------------------------------------------------------------------------- */\n#define BIT_BCN_PORT_SEL\t\tBIT(5)\n\n/* -----------------------------------------------------\n *\n *\t0x0500h ~ 0x05FFh\tEDCA Configuration\n *\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n *\n *\t0x0600h ~ 0x07FFh\tWMAC Configuration\n *\n * ----------------------------------------------------- */\n#ifdef CONFIG_RF_POWER_TRIM\n\n\t#ifdef CONFIG_RTL8723B\n\t\t#define EEPROM_RF_GAIN_OFFSET\t\t\t0xC1\n\t#endif\n\n\t#define EEPROM_RF_GAIN_VAL\t\t\t\t0x1F6\n#endif /*CONFIG_RF_POWER_TRIM*/\n\n\n/* ----------------------------------------------------------------------------\n * 8195 IMR/ISR bits\t\t\t\t\t\t(offset 0xB0,  8bits)\n * ---------------------------------------------------------------------------- */\n#define\tIMR_DISABLED_8723B\t\t\t\t\t0\n/* IMR DW0(0x00B0-00B3) Bit 0-31 */\n#define\tIMR_TIMER2_8723B\t\t\t\t\tBIT(31)\t\t/* Timeout interrupt 2 */\n#define\tIMR_TIMER1_8723B\t\t\t\t\tBIT(30)\t\t/* Timeout interrupt 1\t */\n#define\tIMR_PSTIMEOUT_8723B\t\t\t\tBIT(29)\t\t/* Power Save Time Out Interrupt */\n#define\tIMR_GTINT4_8723B\t\t\t\t\tBIT(28)\t\t/* When GTIMER4 expires, this bit is set to 1\t */\n#define\tIMR_GTINT3_8723B\t\t\t\t\tBIT(27)\t\t/* When GTIMER3 expires, this bit is set to 1\t */\n#define\tIMR_TXBCN0ERR_8723B\t\t\t\tBIT(26)\t\t/* Transmit Beacon0 Error\t\t\t */\n#define\tIMR_TXBCN0OK_8723B\t\t\t\tBIT(25)\t\t/* Transmit Beacon0 OK\t\t\t */\n#define\tIMR_TSF_BIT32_TOGGLE_8723B\t\tBIT(24)\t\t/* TSF Timer BIT(32) toggle indication interrupt\t\t\t */\n#define\tIMR_BCNDMAINT0_8723B\t\t\t\tBIT(20)\t\t/* Beacon DMA Interrupt 0\t\t\t */\n#define\tIMR_BCNDERR0_8723B\t\t\t\tBIT(16)\t\t/* Beacon Queue DMA OK0\t\t\t */\n#define\tIMR_HSISR_IND_ON_INT_8723B\t\tBIT(15)\t\t/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */\n#define\tIMR_BCNDMAINT_E_8723B\t\t\tBIT(14)\t\t/* Beacon DMA Interrupt Extension for Win7\t\t\t */\n#define\tIMR_ATIMEND_8723B\t\t\t\tBIT(12)\t\t/* CTWidnow End or ATIM Window End */\n#define\tIMR_C2HCMD_8723B\t\t\t\t\tBIT(10)\t\t/* CPU to Host Command INT Status, Write 1 clear\t */\n#define\tIMR_CPWM2_8723B\t\t\t\t\tBIT(9)\t\t\t/* CPU power Mode exchange INT Status, Write 1 clear\t */\n#define\tIMR_CPWM_8723B\t\t\t\t\tBIT(8)\t\t\t/* CPU power Mode exchange INT Status, Write 1 clear\t */\n#define\tIMR_HIGHDOK_8723B\t\t\t\tBIT(7)\t\t\t/* High Queue DMA OK\t */\n#define\tIMR_MGNTDOK_8723B\t\t\t\tBIT(6)\t\t\t/* Management Queue DMA OK\t */\n#define\tIMR_BKDOK_8723B\t\t\t\t\tBIT(5)\t\t\t/* AC_BK DMA OK\t\t */\n#define\tIMR_BEDOK_8723B\t\t\t\t\tBIT(4)\t\t\t/* AC_BE DMA OK\t */\n#define\tIMR_VIDOK_8723B\t\t\t\t\tBIT(3)\t\t\t/* AC_VI DMA OK\t\t */\n#define\tIMR_VODOK_8723B\t\t\t\t\tBIT(2)\t\t\t/* AC_VO DMA OK\t */\n#define\tIMR_RDU_8723B\t\t\t\t\tBIT(1)\t\t\t/* Rx Descriptor Unavailable\t */\n#define\tIMR_ROK_8723B\t\t\t\t\tBIT(0)\t\t\t/* Receive DMA OK */\n\n/* IMR DW1(0x00B4-00B7) Bit 0-31 */\n#define\tIMR_BCNDMAINT7_8723B\t\t\t\tBIT(27)\t\t/* Beacon DMA Interrupt 7 */\n#define\tIMR_BCNDMAINT6_8723B\t\t\t\tBIT(26)\t\t/* Beacon DMA Interrupt 6 */\n#define\tIMR_BCNDMAINT5_8723B\t\t\t\tBIT(25)\t\t/* Beacon DMA Interrupt 5 */\n#define\tIMR_BCNDMAINT4_8723B\t\t\t\tBIT(24)\t\t/* Beacon DMA Interrupt 4 */\n#define\tIMR_BCNDMAINT3_8723B\t\t\t\tBIT(23)\t\t/* Beacon DMA Interrupt 3 */\n#define\tIMR_BCNDMAINT2_8723B\t\t\t\tBIT(22)\t\t/* Beacon DMA Interrupt 2 */\n#define\tIMR_BCNDMAINT1_8723B\t\t\t\tBIT(21)\t\t/* Beacon DMA Interrupt 1 */\n#define\tIMR_BCNDOK7_8723B\t\t\t\t\tBIT(20)\t\t/* Beacon Queue DMA OK Interrupt 7 */\n#define\tIMR_BCNDOK6_8723B\t\t\t\t\tBIT(19)\t\t/* Beacon Queue DMA OK Interrupt 6 */\n#define\tIMR_BCNDOK5_8723B\t\t\t\t\tBIT(18)\t\t/* Beacon Queue DMA OK Interrupt 5 */\n#define\tIMR_BCNDOK4_8723B\t\t\t\t\tBIT(17)\t\t/* Beacon Queue DMA OK Interrupt 4 */\n#define\tIMR_BCNDOK3_8723B\t\t\t\t\tBIT(16)\t\t/* Beacon Queue DMA OK Interrupt 3 */\n#define\tIMR_BCNDOK2_8723B\t\t\t\t\tBIT(15)\t\t/* Beacon Queue DMA OK Interrupt 2 */\n#define\tIMR_BCNDOK1_8723B\t\t\t\t\tBIT(14)\t\t/* Beacon Queue DMA OK Interrupt 1 */\n#define\tIMR_ATIMEND_E_8723B\t\t\t\tBIT(13)\t\t/* ATIM Window End Extension for Win7 */\n#define\tIMR_TXERR_8723B\t\t\t\t\tBIT(11)\t\t/* Tx Error Flag Interrupt Status, write 1 clear. */\n#define\tIMR_RXERR_8723B\t\t\t\t\tBIT(10)\t\t/* Rx Error Flag INT Status, Write 1 clear */\n#define\tIMR_TXFOVW_8723B\t\t\t\t\tBIT(9)\t\t\t/* Transmit FIFO Overflow */\n#define\tIMR_RXFOVW_8723B\t\t\t\t\tBIT(8)\t\t\t/* Receive FIFO Overflow */\n\n#ifdef CONFIG_PCI_HCI\n\t/* #define IMR_RX_MASK\t\t(IMR_ROK_8723B|IMR_RDU_8723B|IMR_RXFOVW_8723B) */\n\t#define IMR_TX_MASK\t\t\t(IMR_VODOK_8723B | IMR_VIDOK_8723B | IMR_BEDOK_8723B | IMR_BKDOK_8723B | IMR_MGNTDOK_8723B | IMR_HIGHDOK_8723B)\n\n\t#define RT_BCN_INT_MASKS\t(IMR_BCNDMAINT0_8723B | IMR_TXBCN0OK_8723B | IMR_TXBCN0ERR_8723B | IMR_BCNDERR0_8723B)\n\n\t#define RT_AC_INT_MASKS\t(IMR_VIDOK_8723B | IMR_VODOK_8723B | IMR_BEDOK_8723B | IMR_BKDOK_8723B)\n#endif\n\n#endif /* __RTL8723B_SPEC_H__ */\n"
  },
  {
    "path": "include/rtl8723b_sreset.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8723B_SRESET_H_\n#define _RTL8723B_SRESET_H_\n\n#include <rtw_sreset.h>\n\n#ifdef DBG_CONFIG_ERROR_DETECT\n\textern void rtl8723b_sreset_xmit_status_check(_adapter *padapter);\n\textern void rtl8723b_sreset_linked_status_check(_adapter *padapter);\n#endif\n#endif\n"
  },
  {
    "path": "include/rtl8723b_xmit.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8723B_XMIT_H__\n#define __RTL8723B_XMIT_H__\n\n\n#define MAX_TID (15)\n\n\n#ifndef __INC_HAL8723BDESC_H\n\t#define __INC_HAL8723BDESC_H\n\n\t#define RX_STATUS_DESC_SIZE_8723B\t\t24\n\t#define RX_DRV_INFO_SIZE_UNIT_8723B 8\n\n\n\t/* DWORD 0 */\n\t#define SET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)\n\t#define SET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)\n\t#define SET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)\n\n\t#define GET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)\n\t#define GET_RX_STATUS_DESC_CRC32_8723B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)\n\t#define GET_RX_STATUS_DESC_ICV_8723B(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)\n\t#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8723B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)\n\t#define GET_RX_STATUS_DESC_SECURITY_8723B(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)\n\t#define GET_RX_STATUS_DESC_QOS_8723B(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)\n\t#define GET_RX_STATUS_DESC_SHIFT_8723B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)\n\t#define GET_RX_STATUS_DESC_PHY_STATUS_8723B(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)\n\t#define GET_RX_STATUS_DESC_SWDEC_8723B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)\n\t#define GET_RX_STATUS_DESC_LAST_SEG_8723B(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)\n\t#define GET_RX_STATUS_DESC_FIRST_SEG_8723B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)\n\t#define GET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)\n\t#define GET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)\n\n\t/* DWORD 1 */\n\t#define GET_RX_STATUS_DESC_MACID_8723B(__pRxDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)\n\t#define GET_RX_STATUS_DESC_TID_8723B(__pRxDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)\n\t#define GET_RX_STATUS_DESC_AMSDU_8723B(__pRxDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)\n\t#define GET_RX_STATUS_DESC_RXID_MATCH_8723B(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)\n\t#define GET_RX_STATUS_DESC_PAGGR_8723B(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)\n\t#define GET_RX_STATUS_DESC_A1_FIT_8723B(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)\n\t#define GET_RX_STATUS_DESC_CHKERR_8723B(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)\n\t#define GET_RX_STATUS_DESC_IPVER_8723B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)\n\t#define GET_RX_STATUS_DESC_IS_TCPUDP__8723B(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)\n\t#define GET_RX_STATUS_DESC_CHK_VLD_8723B(__pRxDesc)\tLE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)\n\t#define GET_RX_STATUS_DESC_PAM_8723B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)\n\t#define GET_RX_STATUS_DESC_PWR_8723B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)\n\t#define GET_RX_STATUS_DESC_MORE_DATA_8723B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)\n\t#define GET_RX_STATUS_DESC_MORE_FRAG_8723B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)\n\t#define GET_RX_STATUS_DESC_TYPE_8723B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)\n\t#define GET_RX_STATUS_DESC_MC_8723B(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)\n\t#define GET_RX_STATUS_DESC_BC_8723B(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)\n\n\t/* DWORD 2 */\n\t#define GET_RX_STATUS_DESC_SEQ_8723B(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)\n\t#define GET_RX_STATUS_DESC_FRAG_8723B(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)\n\t#define GET_RX_STATUS_DESC_RX_IS_QOS_8723B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)\n\t#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723B(__pRxStatusDesc)\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)\n\t#define GET_RX_STATUS_DESC_RPT_SEL_8723B(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)\n\n\t/* DWORD 3 */\n\t#define GET_RX_STATUS_DESC_RX_RATE_8723B(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)\n\t#define GET_RX_STATUS_DESC_HTC_8723B(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)\n\t#define GET_RX_STATUS_DESC_EOSP_8723B(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)\n\t#define GET_RX_STATUS_DESC_BSSID_FIT_8723B(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)\n\t#ifdef CONFIG_USB_RX_AGGREGATION\n\t\t#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8723B(__pRxStatusDesc)\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)\n\t#endif\n\t#define GET_RX_STATUS_DESC_PATTERN_MATCH_8723B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)\n\t#define GET_RX_STATUS_DESC_UNICAST_MATCH_8723B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)\n\t#define GET_RX_STATUS_DESC_MAGIC_MATCH_8723B(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)\n\n\t/* DWORD 6 */\n\t#define GET_RX_STATUS_DESC_SPLCP_8723B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)\n\t#define GET_RX_STATUS_DESC_LDPC_8723B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)\n\t#define GET_RX_STATUS_DESC_STBC_8723B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)\n\t#define GET_RX_STATUS_DESC_BW_8723B(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)\n\n\t/* DWORD 5 */\n\t#define GET_RX_STATUS_DESC_TSFL_8723B(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)\n\n\t#define GET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)\n\t#define GET_RX_STATUS_DESC_BUFF_ADDR64_8723B(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)\n\n\t#define SET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)\n\n\n\t/* Dword 0 */\n\t#define GET_TX_DESC_OWN_8723B(__pTxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pTxDesc, 31, 1)\n\n\t#define SET_TX_DESC_PKT_SIZE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)\n\t#define SET_TX_DESC_OFFSET_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)\n\t#define SET_TX_DESC_BMC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)\n\t#define SET_TX_DESC_HTC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)\n\t#define SET_TX_DESC_LAST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)\n\t#define SET_TX_DESC_FIRST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)\n\t#define SET_TX_DESC_LINIP_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)\n\t#define SET_TX_DESC_NO_ACM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)\n\t#define SET_TX_DESC_GF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)\n\t#define SET_TX_DESC_OWN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)\n\n\t/* Dword 1 */\n\t#define SET_TX_DESC_MACID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)\n\t#define SET_TX_DESC_QUEUE_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)\n\t#define SET_TX_DESC_RDG_NAV_EXT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)\n\t#define SET_TX_DESC_LSIG_TXOP_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)\n\t#define SET_TX_DESC_PIFS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)\n\t#define SET_TX_DESC_RATE_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)\n\t#define SET_TX_DESC_EN_DESC_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)\n\t#define SET_TX_DESC_SEC_TYPE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)\n\t#define SET_TX_DESC_PKT_OFFSET_8723B(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)\n\n\n\t/* Dword 2 */\n\t#define SET_TX_DESC_PAID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)\n\t#define SET_TX_DESC_CCA_RTS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)\n\t#define SET_TX_DESC_AGG_ENABLE_8723B(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)\n\t#define SET_TX_DESC_RDG_ENABLE_8723B(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)\n\t#define SET_TX_DESC_AGG_BREAK_8723B(__pTxDesc, __Value)\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)\n\t#define SET_TX_DESC_MORE_FRAG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)\n\t#define SET_TX_DESC_RAW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)\n\t#define SET_TX_DESC_SPE_RPT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)\n\t#define SET_TX_DESC_AMPDU_DENSITY_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)\n\t#define SET_TX_DESC_BT_INT_8723B(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)\n\t#define SET_TX_DESC_GID_8723B(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)\n\n\n\t/* Dword 3 */\n\t#define SET_TX_DESC_WHEADER_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)\n\t#define SET_TX_DESC_CHK_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)\n\t#define SET_TX_DESC_EARLY_MODE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)\n\t#define SET_TX_DESC_HWSEQ_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)\n\t#define SET_TX_DESC_USE_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)\n\t#define SET_TX_DESC_DISABLE_RTS_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)\n\t#define SET_TX_DESC_DISABLE_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)\n\t#define SET_TX_DESC_CTS2SELF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)\n\t#define SET_TX_DESC_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)\n\t#define SET_TX_DESC_HW_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)\n\t#define SET_TX_DESC_NAV_USE_HDR_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)\n\t#define SET_TX_DESC_USE_MAX_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)\n\t#define SET_TX_DESC_MAX_AGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)\n\t#define SET_TX_DESC_NDPA_8723B(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)\n\t#define SET_TX_DESC_AMPDU_MAX_TIME_8723B(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)\n\n\t/* Dword 4 */\n\t#define SET_TX_DESC_TX_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)\n\t#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)\n\t#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)\n\t#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)\n\t#define SET_TX_DESC_DATA_RETRY_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)\n\t#define SET_TX_DESC_RTS_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)\n\n\n\t/* Dword 5 */\n\t#define SET_TX_DESC_DATA_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)\n\t#define SET_TX_DESC_DATA_SHORT_8723B(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)\n\t#define SET_TX_DESC_DATA_BW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)\n\t#define SET_TX_DESC_DATA_LDPC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)\n\t#define SET_TX_DESC_DATA_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)\n\t#define SET_TX_DESC_CTROL_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)\n\t#define SET_TX_DESC_RTS_SHORT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)\n\t#define SET_TX_DESC_RTS_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)\n\n\n\t/* Dword 6 */\n\t#define SET_TX_DESC_SW_DEFINE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)\n\t#define SET_TX_DESC_MBSSID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)\n\t#define SET_TX_DESC_ANTSEL_A_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)\n\t#define SET_TX_DESC_ANTSEL_B_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)\n\t#define SET_TX_DESC_ANTSEL_C_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)\n\t#define SET_TX_DESC_ANTSEL_D_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)\n\n\t/* Dword 7 */\n\t#ifdef CONFIG_PCI_HCI\n\t\t#define SET_TX_DESC_TX_BUFFER_SIZE_8723B(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n\t#endif\n\t#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)\n\t\t#define SET_TX_DESC_TX_DESC_CHECKSUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n\t#endif\n\t#define SET_TX_DESC_USB_TXAGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)\n\t#ifdef CONFIG_SDIO_HCI\n\t\t#define SET_TX_DESC_SDIO_TXSEQ_8723B(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)\n\t#endif\n\n\t/* Dword 8 */\n\t#define SET_TX_DESC_HWSEQ_EN_8723B(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)\n\n\t/* Dword 9 */\n\t#define SET_TX_DESC_SEQ_8723B(__pTxDesc, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)\n\n\t/* Dword 10 */\n\t#define SET_TX_DESC_TX_BUFFER_ADDRESS_8723B(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)\n\t#define GET_TX_DESC_TX_BUFFER_ADDRESS_8723B(__pTxDesc)\tLE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)\n\n\t/* Dword 11 */\n\t#define SET_TX_DESC_NEXT_DESC_ADDRESS_8723B(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)\n\n\n\t#define SET_EARLYMODE_PKTNUM_8723B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)\n\t#define SET_EARLYMODE_LEN0_8723B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)\n\t#define SET_EARLYMODE_LEN1_1_8723B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)\n\t#define SET_EARLYMODE_LEN1_2_8723B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)\n\t#define SET_EARLYMODE_LEN2_8723B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,\t__Value)\n\t#define SET_EARLYMODE_LEN3_8723B(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)\n\n#endif\n/* -----------------------------------------------------------\n *\n *\tRate\n *\n * -----------------------------------------------------------\n * CCK Rates, TxHT = 0 */\n#define DESC8723B_RATE1M\t\t\t\t0x00\n#define DESC8723B_RATE2M\t\t\t\t0x01\n#define DESC8723B_RATE5_5M\t\t\t\t0x02\n#define DESC8723B_RATE11M\t\t\t\t0x03\n\n/* OFDM Rates, TxHT = 0 */\n#define DESC8723B_RATE6M\t\t\t\t0x04\n#define DESC8723B_RATE9M\t\t\t\t0x05\n#define DESC8723B_RATE12M\t\t\t\t0x06\n#define DESC8723B_RATE18M\t\t\t\t0x07\n#define DESC8723B_RATE24M\t\t\t\t0x08\n#define DESC8723B_RATE36M\t\t\t\t0x09\n#define DESC8723B_RATE48M\t\t\t\t0x0a\n#define DESC8723B_RATE54M\t\t\t\t0x0b\n\n/* MCS Rates, TxHT = 1 */\n#define DESC8723B_RATEMCS0\t\t\t\t0x0c\n#define DESC8723B_RATEMCS1\t\t\t\t0x0d\n#define DESC8723B_RATEMCS2\t\t\t\t0x0e\n#define DESC8723B_RATEMCS3\t\t\t\t0x0f\n#define DESC8723B_RATEMCS4\t\t\t\t0x10\n#define DESC8723B_RATEMCS5\t\t\t\t0x11\n#define DESC8723B_RATEMCS6\t\t\t\t0x12\n#define DESC8723B_RATEMCS7\t\t\t\t0x13\n#define DESC8723B_RATEMCS8\t\t\t\t0x14\n#define DESC8723B_RATEMCS9\t\t\t\t0x15\n#define DESC8723B_RATEMCS10\t\t0x16\n#define DESC8723B_RATEMCS11\t\t0x17\n#define DESC8723B_RATEMCS12\t\t0x18\n#define DESC8723B_RATEMCS13\t\t0x19\n#define DESC8723B_RATEMCS14\t\t0x1a\n#define DESC8723B_RATEMCS15\t\t0x1b\n#define DESC8723B_RATEVHTSS1MCS0\t\t0x2c\n#define DESC8723B_RATEVHTSS1MCS1\t\t0x2d\n#define DESC8723B_RATEVHTSS1MCS2\t\t0x2e\n#define DESC8723B_RATEVHTSS1MCS3\t\t0x2f\n#define DESC8723B_RATEVHTSS1MCS4\t\t0x30\n#define DESC8723B_RATEVHTSS1MCS5\t\t0x31\n#define DESC8723B_RATEVHTSS1MCS6\t\t0x32\n#define DESC8723B_RATEVHTSS1MCS7\t\t0x33\n#define DESC8723B_RATEVHTSS1MCS8\t\t0x34\n#define DESC8723B_RATEVHTSS1MCS9\t\t0x35\n#define DESC8723B_RATEVHTSS2MCS0\t\t0x36\n#define DESC8723B_RATEVHTSS2MCS1\t\t0x37\n#define DESC8723B_RATEVHTSS2MCS2\t\t0x38\n#define DESC8723B_RATEVHTSS2MCS3\t\t0x39\n#define DESC8723B_RATEVHTSS2MCS4\t\t0x3a\n#define DESC8723B_RATEVHTSS2MCS5\t\t0x3b\n#define DESC8723B_RATEVHTSS2MCS6\t\t0x3c\n#define DESC8723B_RATEVHTSS2MCS7\t\t0x3d\n#define DESC8723B_RATEVHTSS2MCS8\t\t0x3e\n#define DESC8723B_RATEVHTSS2MCS9\t\t0x3f\n\n\n#define\tRX_HAL_IS_CCK_RATE_8723B(pDesc)\\\n\t(GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE1M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE2M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE5_5M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE11M)\n\n\nvoid rtl8723b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);\nvoid rtl8723b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);\n#if defined(CONFIG_CONCURRENT_MODE)\n\tvoid fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);\n#endif\nvoid fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\ts32 rtl8723bs_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8723bs_free_xmit_priv(PADAPTER padapter);\n\ts32 rtl8723bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8723bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\trtl8723bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8723bs_xmit_buf_handler(PADAPTER padapter);\n\tthread_return rtl8723bs_xmit_thread(thread_context context);\n\t#define hal_xmit_handler rtl8723bs_xmit_buf_handler\n#endif\n\n#ifdef CONFIG_USB_HCI\n\ts32 rtl8723bu_xmit_buf_handler(PADAPTER padapter);\n\t#define hal_xmit_handler rtl8723bu_xmit_buf_handler\n\n\n\ts32 rtl8723bu_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8723bu_free_xmit_priv(PADAPTER padapter);\n\ts32 rtl8723bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8723bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\t rtl8723bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\t/* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */\n\tvoid rtl8723bu_xmit_tasklet(void *priv);\n\ts32 rtl8723bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\n\tvoid _dbg_dump_tx_info(_adapter\t*padapter, int frame_tag, struct tx_desc *ptxdesc);\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\ts32 rtl8723be_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8723be_free_xmit_priv(PADAPTER padapter);\n\tstruct xmit_buf *rtl8723be_dequeue_xmitbuf(struct rtw_tx_ring *ring);\n\tvoid\trtl8723be_xmitframe_resume(_adapter *padapter);\n\ts32 rtl8723be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8723be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\trtl8723be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\tvoid rtl8723be_xmit_tasklet(void *priv);\n#endif\n\nu8\tBWMapping_8723B(PADAPTER Adapter, struct pkt_attrib *pattrib);\nu8\tSCMapping_8723B(PADAPTER Adapter, struct pkt_attrib\t*pattrib);\n\n#endif\n"
  },
  {
    "path": "include/rtl8723d_cmd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8723D_CMD_H__\n#define __RTL8723D_CMD_H__\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\nenum h2c_cmd_8723D {\n\t/* Common Class: 000 */\n\tH2C_8723D_RSVD_PAGE = 0x00,\n\tH2C_8723D_MEDIA_STATUS_RPT = 0x01,\n\tH2C_8723D_SCAN_ENABLE = 0x02,\n\tH2C_8723D_KEEP_ALIVE = 0x03,\n\tH2C_8723D_DISCON_DECISION = 0x04,\n\tH2C_8723D_PSD_OFFLOAD = 0x05,\n\tH2C_8723D_AP_OFFLOAD = 0x08,\n\tH2C_8723D_BCN_RSVDPAGE = 0x09,\n\tH2C_8723D_PROBERSP_RSVDPAGE = 0x0A,\n\tH2C_8723D_FCS_RSVDPAGE = 0x10,\n\tH2C_8723D_FCS_INFO = 0x11,\n\tH2C_8723D_AP_WOW_GPIO_CTRL = 0x13,\n\n\t/* PoweSave Class: 001 */\n\tH2C_8723D_SET_PWR_MODE = 0x20,\n\tH2C_8723D_PS_TUNING_PARA = 0x21,\n\tH2C_8723D_PS_TUNING_PARA2 = 0x22,\n\tH2C_8723D_P2P_LPS_PARAM = 0x23,\n\tH2C_8723D_P2P_PS_OFFLOAD = 0x24,\n\tH2C_8723D_PS_SCAN_ENABLE = 0x25,\n\tH2C_8723D_SAP_PS_ = 0x26,\n\tH2C_8723D_INACTIVE_PS_ = 0x27, /* Inactive_PS */\n\tH2C_8723D_FWLPS_IN_IPS_ = 0x28,\n\n\t/* Dynamic Mechanism Class: 010 */\n\tH2C_8723D_MACID_CFG = 0x40,\n\tH2C_8723D_TXBF = 0x41,\n\tH2C_8723D_RSSI_SETTING = 0x42,\n\tH2C_8723D_AP_REQ_TXRPT = 0x43,\n\tH2C_8723D_INIT_RATE_COLLECT = 0x44,\n\tH2C_8723D_RA_PARA_ADJUST = 0x46,\n\n\t/* BT Class: 011 */\n\tH2C_8723D_B_TYPE_TDMA = 0x60,\n\tH2C_8723D_BT_INFO = 0x61,\n\tH2C_8723D_FORCE_BT_TXPWR = 0x62,\n\tH2C_8723D_BT_IGNORE_WLANACT = 0x63,\n\tH2C_8723D_DAC_SWING_VALUE = 0x64,\n\tH2C_8723D_ANT_SEL_RSV = 0x65,\n\tH2C_8723D_WL_OPMODE = 0x66,\n\tH2C_8723D_BT_MP_OPER = 0x67,\n\tH2C_8723D_BT_CONTROL = 0x68,\n\tH2C_8723D_BT_WIFI_CTRL = 0x69,\n\tH2C_8723D_BT_FW_PATCH = 0x6A,\n\tH2C_8723D_BT_WLAN_CALIBRATION = 0x6D,\n\n\t/* WOWLAN Class: 100 */\n\tH2C_8723D_WOWLAN = 0x80,\n\tH2C_8723D_REMOTE_WAKE_CTRL = 0x81,\n\tH2C_8723D_AOAC_GLOBAL_INFO = 0x82,\n\tH2C_8723D_AOAC_RSVD_PAGE = 0x83,\n\tH2C_8723D_AOAC_RSVD_PAGE2 = 0x84,\n\tH2C_8723D_D0_SCAN_OFFLOAD_CTRL = 0x85,\n\tH2C_8723D_D0_SCAN_OFFLOAD_INFO = 0x86,\n\tH2C_8723D_CHNL_SWITCH_OFFLOAD = 0x87,\n\tH2C_8723D_P2P_OFFLOAD_RSVD_PAGE = 0x8A,\n\tH2C_8723D_P2P_OFFLOAD = 0x8B,\n\n\tH2C_8723D_RESET_TSF = 0xC0,\n\tH2C_8723D_MAXID,\n};\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------\n * ---------------------------------------------------------------------------------------------------------\n * _RSVDPAGE_LOC_CMD_0x00 */\n#define SET_8723D_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8723D_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_8723D_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8723D_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8723D_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n/* _PWR_MOD_CMD_0x20 */\n#define SET_8723D_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8723D_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)\n#define SET_8723D_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)\n#define SET_8723D_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8723D_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8723D_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)\n#define SET_8723D_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n#define GET_8723D_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)\t\t\t\t\tLE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)\n\n/* _PS_TUNE_PARAM_CMD_0x21 */\n#define SET_8723D_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8723D_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_8723D_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)\n#define SET_8723D_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)\n#define SET_8723D_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n\n/* _MACID_CFG_CMD_0x40 */\n#define SET_8723D_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8723D_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)\n#define SET_8723D_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)\n#define SET_8723D_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)\n#define SET_8723D_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)\n#define SET_8723D_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)\n#define SET_8723D_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)\n#define SET_8723D_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)\n#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)\n#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)\n#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)\n\n/* _RSSI_SETTING_CMD_0x42 */\n#define SET_8723D_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8723D_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)\n#define SET_8723D_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n\n/* _AP_REQ_TXRPT_CMD_0x43 */\n#define SET_8723D_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8723D_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n\n/* _FORCE_BT_TXPWR_CMD_0x62 */\n#define SET_8723D_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n\n/* _FORCE_BT_MP_OPER_CMD_0x67 */\n#define SET_8723D_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)\n#define SET_8723D_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)\n#define SET_8723D_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)\n#define SET_8723D_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)\n#define SET_8723D_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)\n#define SET_8723D_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)\n\n/* _BT_FW_PATCH_0x6A */\n#define SET_8723D_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)\n#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)\n\n/* ---------------------------------------------------------------------------------------------------------\n * -------------------------------------------    Structure    --------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\n\n/* ---------------------------------------------------------------------------------------------------------\n * ----------------------------------    Function Statement     --------------------------------------------------\n * --------------------------------------------------------------------------------------------------------- */\n\n/* host message to firmware cmd */\nvoid rtl8723d_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);\nvoid rtl8723d_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);\n/* s32 rtl8723d_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */\nvoid rtl8723d_set_FwPsTuneParam_cmd(PADAPTER padapter);\nvoid rtl8723d_download_rsvd_page(PADAPTER padapter, u8 mstatus);\n#ifdef CONFIG_BT_COEXIST\n\tvoid rtl8723d_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);\n#endif /* CONFIG_BT_COEXIST */\n#ifdef CONFIG_P2P\n\tvoid rtl8723d_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\nvoid rtl8723d_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);\n#endif\n#endif\n\n#ifdef CONFIG_P2P_WOWLAN\n\tvoid rtl8723d_set_p2p_wowlan_offload_cmd(PADAPTER padapter);\n#endif\n\ns32 FillH2CCmd8723D(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);\nu8 GetTxBufferRsvdPageNum8723D(_adapter *padapter, bool wowlan);\n#endif\n"
  },
  {
    "path": "include/rtl8723d_dm.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8723D_DM_H__\n#define __RTL8723D_DM_H__\n/* ************************************************************\n * Description:\n *\n * This file is for 8723D dynamic mechanism only\n *\n *\n * ************************************************************ */\n\n/* ************************************************************\n * structure and define\n * ************************************************************ */\n\n/* ************************************************************\n * function prototype\n * ************************************************************ */\n\nvoid rtl8723d_init_dm_priv(PADAPTER padapter);\nvoid rtl8723d_deinit_dm_priv(PADAPTER padapter);\n\nvoid rtl8723d_InitHalDm(PADAPTER padapter);\nvoid rtl8723d_HalDmWatchDog(PADAPTER padapter);\n\n#endif\n"
  },
  {
    "path": "include/rtl8723d_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8723D_HAL_H__\n#define __RTL8723D_HAL_H__\n\n#include \"hal_data.h\"\n\n#include \"rtl8723d_spec.h\"\n#include \"rtl8723d_rf.h\"\n#include \"rtl8723d_dm.h\"\n#include \"rtl8723d_recv.h\"\n#include \"rtl8723d_xmit.h\"\n#include \"rtl8723d_cmd.h\"\n#include \"rtl8723d_led.h\"\n#include \"Hal8723DPwrSeq.h\"\n#include \"Hal8723DPhyReg.h\"\n#include \"Hal8723DPhyCfg.h\"\n#ifdef DBG_CONFIG_ERROR_DETECT\n\t#include \"rtl8723d_sreset.h\"\n#endif\n#ifdef CONFIG_LPS_POFF\n\t#include \"rtl8723d_lps_poff.h\"\n#endif\n\n#define FW_8723D_SIZE\t\t0x8000\n#define FW_8723D_START_ADDRESS\t0x1000\n#define FW_8723D_END_ADDRESS\t0x1FFF /* 0x5FFF */\n\n#define IS_FW_HEADER_EXIST_8723D(_pFwHdr)\\\n\t((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x23D0)\n\ntypedef struct _RT_FIRMWARE {\n\tFIRMWARE_SOURCE\teFWSource;\n#ifdef CONFIG_EMBEDDED_FWIMG\n\tu8\t\t\t*szFwBuffer;\n#else\n\tu8\t\t\tszFwBuffer[FW_8723D_SIZE];\n#endif\n\tu32\t\t\tulFwLength;\n} RT_FIRMWARE_8723D, *PRT_FIRMWARE_8723D;\n\n/*\n * This structure must be cared byte-ordering\n *\n * Added by tynli. 2009.12.04. */\ntypedef struct _RT_8723D_FIRMWARE_HDR {\n\t/* 8-byte alinment required */\n\n\t/* --- LONG WORD 0 ---- */\n\tu16\t\tSignature;\t/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */\n\tu8\t\tCategory;\t/* AP/NIC and USB/PCI */\n\tu8\t\tFunction;\t/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */\n\tu16\t\tVersion;\t\t/* FW Version */\n\tu16\t\tSubversion;\t/* FW Subversion, default 0x00 */\n\n\t/* --- LONG WORD 1 ---- */\n\tu8\t\tMonth;\t/* Release time Month field */\n\tu8\t\tDate;\t/* Release time Date field */\n\tu8\t\tHour;\t/* Release time Hour field */\n\tu8\t\tMinute;\t/* Release time Minute field */\n\tu16\t\tRamCodeSize;\t/* The size of RAM code */\n\tu16\t\tRsvd2;\n\n\t/* --- LONG WORD 2 ---- */\n\tu32\t\tSvnIdx;\t/* The SVN entry index */\n\tu32\t\tRsvd3;\n\n\t/* --- LONG WORD 3 ---- */\n\tu32\t\tRsvd4;\n\tu32\t\tRsvd5;\n} RT_8723D_FIRMWARE_HDR, *PRT_8723D_FIRMWARE_HDR;\n\n#define DRIVER_EARLY_INT_TIME_8723D\t\t0x05\n#define BCN_DMA_ATIME_INT_TIME_8723D\t\t0x02\n\n/* for 8723D\n * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */\n#define PAGE_SIZE_TX_8723D\t\t\t128\n#define PAGE_SIZE_RX_8723D\t\t\t8\n\n#define TX_DMA_SIZE_8723D\t\t\t0x8000\t/* 32K(TX) */\n#define RX_DMA_SIZE_8723D\t\t\t0x4000\t/* 16K(RX) */\n\n#ifdef CONFIG_WOWLAN\n\t#define RESV_FMWF\t(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/\n#else\n\t#define RESV_FMWF\t0\n#endif\n\n#ifdef CONFIG_FW_C2H_DEBUG\n\t#define RX_DMA_RESERVED_SIZE_8723D\t0x100\t/* 256B, reserved for c2h debug message */\n#else\n\t#define RX_DMA_RESERVED_SIZE_8723D\t0x80\t/* 128B, reserved for tx report */\n#endif\n#define RX_DMA_BOUNDARY_8723D\\\n\t(RX_DMA_SIZE_8723D - RX_DMA_RESERVED_SIZE_8723D - 1)\n\n\n/* Note: We will divide number of page equally for each queue other than public queue! */\n\n/* For General Reserved Page Number(Beacon Queue is reserved page)\n * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8723D\n * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/\n\n#define BCNQ_PAGE_NUM_8723D\t\t(MAX_BEACON_LEN/PAGE_SIZE_TX_8723D + 6) /*0x08*/\n\n/* For WoWLan , more reserved page\n * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6\n * NS offload: 2 NDP info: 1\n */\n#ifdef CONFIG_WOWLAN\n\t#define WOWLAN_PAGE_NUM_8723D\t0x0b\n#else\n\t#define WOWLAN_PAGE_NUM_8723D\t0x00\n#endif\n\n#ifdef CONFIG_PNO_SUPPORT\n\t#undef WOWLAN_PAGE_NUM_8723D\n\t#define WOWLAN_PAGE_NUM_8723D\t0x15\n#endif\n\n#ifdef CONFIG_AP_WOWLAN\n\t#define AP_WOWLAN_PAGE_NUM_8723D\t0x02\n#endif\n\n#define TX_TOTAL_PAGE_NUMBER_8723D\\\n\t(0xFF - BCNQ_PAGE_NUM_8723D - WOWLAN_PAGE_NUM_8723D)\n#define TX_PAGE_BOUNDARY_8723D\t\t(TX_TOTAL_PAGE_NUMBER_8723D + 1)\n\n#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723D\tTX_TOTAL_PAGE_NUMBER_8723D\n#define WMM_NORMAL_TX_PAGE_BOUNDARY_8723D\\\n\t(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723D + 1)\n\n/* For Normal Chip Setting\n * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723D */\n#define NORMAL_PAGE_NUM_HPQ_8723D\t\t0x0C\n#define NORMAL_PAGE_NUM_LPQ_8723D\t\t0x02\n#define NORMAL_PAGE_NUM_NPQ_8723D\t\t0x02\n#define NORMAL_PAGE_NUM_EPQ_8723D\t\t0x04\n\n/* Note: For Normal Chip Setting, modify later */\n#define WMM_NORMAL_PAGE_NUM_HPQ_8723D\t\t0x30\n#define WMM_NORMAL_PAGE_NUM_LPQ_8723D\t\t0x20\n#define WMM_NORMAL_PAGE_NUM_NPQ_8723D\t\t0x20\n#define WMM_NORMAL_PAGE_NUM_EPQ_8723D\t\t0x00\n\n\n#include \"HalVerDef.h\"\n#include \"hal_com.h\"\n\n#define EFUSE_OOB_PROTECT_BYTES (96 + 1)\n\n#define HAL_EFUSE_MEMORY\n#define HWSET_MAX_SIZE_8723D                512\n#define EFUSE_REAL_CONTENT_LEN_8723D        512\n#define EFUSE_MAP_LEN_8723D                 512\n#define EFUSE_MAX_SECTION_8723D             64\n\n/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/\n#define EFUSE_IC_ID_OFFSET\t\t\t506\n#define AVAILABLE_EFUSE_ADDR(addr)\t(addr < EFUSE_REAL_CONTENT_LEN_8723D)\n\n#define EFUSE_ACCESS_ON\t\t0x69\n#define EFUSE_ACCESS_OFF\t0x00\n\n/* ********************************************************\n *\t\t\tEFUSE for BT definition\n * ******************************************************** */\n#define BANK_NUM\t\t\t1\n#define EFUSE_BT_REAL_BANK_CONTENT_LEN\t128\n#define EFUSE_BT_REAL_CONTENT_LEN\t\\\n\t(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)\n#define EFUSE_BT_MAP_LEN\t\t1024\t/* 1k bytes */\n#define EFUSE_BT_MAX_SECTION\t\t(EFUSE_BT_MAP_LEN / 8)\n#define EFUSE_PROTECT_BYTES_BANK\t16\n\ntypedef enum tag_Package_Definition {\n\tPACKAGE_DEFAULT,\n\tPACKAGE_QFN68,\n\tPACKAGE_TFBGA90,\n\tPACKAGE_TFBGA80,\n\tPACKAGE_TFBGA79\n} PACKAGE_TYPE_E;\n\n#define INCLUDE_MULTI_FUNC_BT(_Adapter) \\\n\t(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)\n#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \\\n\t(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)\n\n#ifdef CONFIG_FILE_FWIMG\n\textern char *rtw_fw_file_path;\n\textern char *rtw_fw_wow_file_path;\n\t#ifdef CONFIG_MP_INCLUDED\n\t\textern char *rtw_fw_mp_bt_file_path;\n\t#endif /* CONFIG_MP_INCLUDED */\n#endif /* CONFIG_FILE_FWIMG */\n\n/* rtl8723d_hal_init.c */\ns32 rtl8723d_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);\nvoid rtl8723d_FirmwareSelfReset(PADAPTER padapter);\nvoid rtl8723d_InitializeFirmwareVars(PADAPTER padapter);\n\nvoid rtl8723d_InitAntenna_Selection(PADAPTER padapter);\nvoid rtl8723d_DeinitAntenna_Selection(PADAPTER padapter);\nvoid rtl8723d_CheckAntenna_Selection(PADAPTER padapter);\nvoid rtl8723d_init_default_value(PADAPTER padapter);\n\ns32 rtl8723d_InitLLTTable(PADAPTER padapter);\n\ns32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);\ns32 CardDisableWithoutHWSM(PADAPTER padapter);\n\n/* EFuse */\nu8 GetEEPROMSize8723D(PADAPTER padapter);\nvoid Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);\nvoid Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);\nvoid Hal_EfuseParseTxPowerInfo_8723D(PADAPTER padapter,\n\t\t\t\t     u8 *PROMContent, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseBTCoexistInfo_8723D(PADAPTER padapter,\n\t\t\t\t       u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseEEPROMVer_8723D(PADAPTER padapter,\n\t\t\t\t   u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseChnlPlan_8723D(PADAPTER padapter,\n\t\t\t\t  u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseCustomerID_8723D(PADAPTER padapter,\n\t\t\t\t    u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseAntennaDiversity_8723D(PADAPTER padapter,\n\t\tu8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid Hal_EfuseParseXtal_8723D(PADAPTER pAdapter,\n\t\t\t      u8 *hwinfo, u8 AutoLoadFail);\nvoid Hal_EfuseParseThermalMeter_8723D(PADAPTER padapter,\n\t\t\t\t      u8 *hwinfo, u8 AutoLoadFail);\nvoid Hal_EfuseParseVoltage_8723D(PADAPTER pAdapter,\n\t\t\t\t u8 *hwinfo, BOOLEAN\tAutoLoadFail);\nvoid Hal_EfuseParseBoardType_8723D(PADAPTER Adapter,\n\t\t\t\t   u8\t*PROMContent, BOOLEAN AutoloadFail);\n\nvoid rtl8723d_set_hal_ops(struct hal_ops *pHalFunc);\nvoid init_hal_spec_8723d(_adapter *adapter);\nu8 SetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val);\nvoid GetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val);\nu8 SetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);\nu8 GetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);\n\n/* register */\nvoid rtl8723d_InitBeaconParameters(PADAPTER padapter);\nvoid rtl8723d_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);\nvoid _InitMacAPLLSetting_8723D(PADAPTER Adapter);\nvoid _8051Reset8723(PADAPTER padapter);\n#ifdef CONFIG_WOWLAN\n\tvoid Hal_DetectWoWMode(PADAPTER pAdapter);\n#endif /* CONFIG_WOWLAN */\n\nvoid rtl8723d_start_thread(_adapter *padapter);\nvoid rtl8723d_stop_thread(_adapter *padapter);\n\n#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)\n\tvoid rtl8723ds_init_checkbthang_workqueue(_adapter *adapter);\n\tvoid rtl8723ds_free_checkbthang_workqueue(_adapter *adapter);\n\tvoid rtl8723ds_cancle_checkbthang_workqueue(_adapter *adapter);\n\tvoid rtl8723ds_hal_check_bt_hang(_adapter *adapter);\n#endif\n\n#ifdef CONFIG_GPIO_WAKEUP\n\tvoid HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);\n#endif\n#ifdef CONFIG_MP_INCLUDED\nint FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);\n#endif\nvoid CCX_FwC2HTxRpt_8723d(PADAPTER padapter, u8 *pdata, u8 len);\n\nu8 MRateToHwRate8723D(u8 rate);\nu8 HwRateToMRate8723D(u8 rate);\n\nvoid Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\n\n#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)\n\tvoid check_bt_status_work(void *data);\n#endif\n\n#ifdef CONFIG_USB_HCI\n\tvoid rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc);\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\tBOOLEAN\tInterruptRecognized8723DE(PADAPTER Adapter);\n\tvoid\tUpdateInterruptMask8723DE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);\n\tu16 get_txbd_rw_reg(u16 ff_hwaddr);\n#endif\n\n#endif\n"
  },
  {
    "path": "include/rtl8723d_led.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8723D_LED_H__\n#define __RTL8723D_LED_H__\n\n#include <drv_conf.h>\n#include <osdep_service.h>\n#include <drv_types.h>\n\n#ifdef CONFIG_RTW_SW_LED\n/* ********************************************************************************\n * Interface to manipulate LED objects.\n * ******************************************************************************** */\n#ifdef CONFIG_USB_HCI\n\tvoid rtl8723du_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8723du_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_SDIO_HCI\n\tvoid rtl8723ds_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8723ds_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_GSPI_HCI\n\tvoid rtl8723ds_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8723ds_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_PCI_HCI\n\tvoid rtl8723de_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8723de_DeInitSwLeds(PADAPTER padapter);\n#endif\n\n#endif /*#ifdef CONFIG_RTW_SW_LED*/\n#endif\n"
  },
  {
    "path": "include/rtl8723d_lps_poff.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n/******************************************** CONST  ************************/\n#define NUM_OF_REGISTER_BANK\t13\n#define NUM_OF_TOTAL_DWORD (NUM_OF_REGISTER_BANK * 64)\n#define TOTAL_LEN_FOR_HIOE ((NUM_OF_TOTAL_DWORD + 1) * 8)\n#define LPS_POFF_STATIC_FILE_LEN (TOTAL_LEN_FOR_HIOE + TXDESC_SIZE)\n#define LPS_POFF_DYNAMIC_FILE_LEN\t(512 + TXDESC_SIZE)\n/******************************************** CONST  ************************/\n\n/******************************************** MACRO   ************************/\n/* HOIE Entry Definition */\n#define SET_HOIE_ENTRY_LOW_DATA(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE),\t0, 16, __Value)\n#define SET_HOIE_ENTRY_HIGH_DATA(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE), 16, 16, __Value)\n#define SET_HOIE_ENTRY_MODE_SELECT(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 0, 1, __Value)\n#define SET_HOIE_ENTRY_ADDRESS(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 1, 14, __Value)\n#define SET_HOIE_ENTRY_BYTE_MASK(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 15, 4, __Value)\n#define SET_HOIE_ENTRY_IO_LOCK(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 19, 1, __Value)\n#define SET_HOIE_ENTRY_RD_EN(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 20, 1, __Value)\n#define SET_HOIE_ENTRY_WR_EN(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 21, 1, __Value)\n#define SET_HOIE_ENTRY_RAW_RW(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 22, 1, __Value)\n#define SET_HOIE_ENTRY_RAW(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 23, 1, __Value)\n#define SET_HOIE_ENTRY_IO_DELAY(__pHOIE, __Value) \\\n\tSET_BITS_TO_LE_4BYTE((__pHOIE)+4, 24, 8, __Value)\n\n/*********************Function Definition*******************************************/\nvoid rtl8723d_lps_poff_init(PADAPTER padapter);\nvoid rtl8723d_lps_poff_deinit(PADAPTER padapter);\nbool rtl8723d_lps_poff_get_txbndy_status(PADAPTER padapter);\nvoid rtl8723d_lps_poff_h2c_ctrl(PADAPTER padapter, u8 enable);\nvoid rtl8723d_lps_poff_set_ps_mode(PADAPTER padapter, bool bEnterLPS);\nbool rtl8723d_lps_poff_get_status(PADAPTER padapter);\nvoid rtl8723d_lps_poff_wow(PADAPTER padapter);\n"
  },
  {
    "path": "include/rtl8723d_recv.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8723D_RECV_H__\n#define __RTL8723D_RECV_H__\n\n#define RECV_BLK_SZ 512\n#define RECV_BLK_CNT 16\n#define RECV_BLK_TH RECV_BLK_CNT\n\n#if defined(CONFIG_USB_HCI)\n\n\t#ifndef MAX_RECVBUF_SZ\n\t\t#ifndef CONFIG_MINIMAL_MEMORY_USAGE\n\t\t\t/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */\n\t\t\t/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */\n\t\t\t/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */\n\t\t\t#ifdef CONFIG_PLATFORM_MSTAR\n\t\t\t\t#define MAX_RECVBUF_SZ (8192) /* 8K */\n\t\t\t#else\n\t\t\t\t#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */\n\t\t\t#endif\n\t\t\t/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */\n\t\t#else\n\t\t\t#define MAX_RECVBUF_SZ (4000) /* about 4K */\n\t\t#endif\n\t#endif /* !MAX_RECVBUF_SZ */\n\n#elif defined(CONFIG_PCI_HCI)\n\t/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */\n\t/*\t#define MAX_RECVBUF_SZ (9100) */\n\t/* #else */\n\t#define MAX_RECVBUF_SZ (4000) /* about 4K\n\t* #endif */\n\n\n#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\n\t#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8723D + 1)\n\n#endif\n\n/* Rx smooth factor */\n#define\tRx_Smooth_Factor (20)\n\n#ifdef CONFIG_SDIO_HCI\n\t#ifndef CONFIG_SDIO_RX_COPY\n\t\t#undef MAX_RECVBUF_SZ\n\t\t#define MAX_RECVBUF_SZ\t(RX_DMA_SIZE_8723D - RX_DMA_RESERVED_SIZE_8723D)\n\t#endif /* !CONFIG_SDIO_RX_COPY */\n#endif /* CONFIG_SDIO_HCI */\n\n/*-----------------------------------------------------------------*/\n/*\tRTL8723D RX BUFFER DESC                                      */\n/*-----------------------------------------------------------------*/\n/*DWORD 0*/\n#define SET_RX_BUFFER_DESC_DATA_LENGTH_8723D(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)\n#define SET_RX_BUFFER_DESC_LS_8723D(__pRxStatusDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)\n#define SET_RX_BUFFER_DESC_FS_8723D(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)\n#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8723D(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)\n\n#define GET_RX_BUFFER_DESC_OWN_8723D(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)\n#define GET_RX_BUFFER_DESC_LS_8723D(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)\n#define GET_RX_BUFFER_DESC_FS_8723D(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)\n#ifdef USING_RX_TAG\n\t#define GET_RX_BUFFER_DESC_RX_TAG_8723D(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13)\n#else\n\t#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8723D(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)\n#endif\n\n/*DWORD 1*/\n#define SET_RX_BUFFER_PHYSICAL_LOW_8723D(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)\n\n/*DWORD 2*/\n#ifdef CONFIG_64BIT_DMA\n\t#define SET_RX_BUFFER_PHYSICAL_HIGH_8723D(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)\n#else\n\t#define SET_RX_BUFFER_PHYSICAL_HIGH_8723D(__pRxStatusDesc, __Value)\n#endif\n\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\ts32 rtl8723ds_init_recv_priv(PADAPTER padapter);\n\tvoid rtl8723ds_free_recv_priv(PADAPTER padapter);\n\ts32 rtl8723ds_recv_hdl(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_USB_HCI\n\tint rtl8723du_init_recv_priv(_adapter *padapter);\n\tvoid rtl8723du_free_recv_priv(_adapter *padapter);\n\tvoid rtl8723du_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\ts32 rtl8723de_init_recv_priv(PADAPTER padapter);\n\tvoid rtl8723de_free_recv_priv(PADAPTER padapter);\n#endif\n\nvoid rtl8723d_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);\n\n#endif /* __RTL8723D_RECV_H__ */\n"
  },
  {
    "path": "include/rtl8723d_rf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8723D_RF_H__\n#define __RTL8723D_RF_H__\n\nint PHY_RF6052_Config8723D(PADAPTER pdapter);\n\nvoid PHY_RF6052SetBandwidth8723D(PADAPTER Adapter, enum channel_width Bandwidth);\n#endif\n"
  },
  {
    "path": "include/rtl8723d_spec.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8723D_SPEC_H__\n#define __RTL8723D_SPEC_H__\n\n#include <drv_conf.h>\n\n\n#define HAL_NAV_UPPER_UNIT_8723D\t\t128\t\t/* micro-second */\n\n/* -----------------------------------------------------\n *\n *\t0x0000h ~ 0x00FFh\tSystem Configuration\n *\n * ----------------------------------------------------- */\n#define REG_SYS_ISO_CTRL_8723D\t\t\t0x0000\t/* 2 Byte */\n#define REG_SYS_FUNC_EN_8723D\t\t\t0x0002\t/* 2 Byte */\n#define REG_APS_FSMCO_8723D\t\t\t0x0004\t/* 4 Byte */\n#define REG_SYS_CLKR_8723D\t\t\t\t0x0008\t/* 2 Byte */\n#define REG_9346CR_8723D\t\t\t\t0x000A\t/* 2 Byte */\n#define REG_EE_VPD_8723D\t\t\t\t0x000C\t/* 2 Byte */\n#define REG_AFE_MISC_8723D\t\t\t\t0x0010\t/* 1 Byte */\n#define REG_SPS0_CTRL_8723D\t\t\t\t0x0011\t/* 7 Byte */\n#define REG_SPS_OCP_CFG_8723D\t\t\t0x0018\t/* 4 Byte */\n#define REG_RSV_CTRL_8723D\t\t\t\t0x001C\t/* 3 Byte */\n#define REG_RF_CTRL_8723D\t\t\t\t0x001F\t/* 1 Byte */\n#define REG_LPLDO_CTRL_8723D\t\t\t0x0023\t/* 1 Byte */\n#define REG_AFE_XTAL_CTRL_8723D\t\t0x0024\t/* 4 Byte */\n#define REG_AFE_PLL_CTRL_8723D\t\t\t0x0028\t/* 4 Byte */\n#define REG_MAC_PLL_CTRL_EXT_8723D\t\t0x002c\t/* 4 Byte */\n#define REG_EFUSE_CTRL_8723D\t\t\t0x0030\n#define REG_EFUSE_TEST_8723D\t\t\t0x0034\n#define REG_PWR_DATA_8723D\t\t\t\t0x0038\n#define REG_CAL_TIMER_8723D\t\t\t\t0x003C\n#define REG_ACLK_MON_8723D\t\t\t\t0x003E\n#define REG_GPIO_MUXCFG_8723D\t\t\t0x0040\n#define REG_GPIO_IO_SEL_8723D\t\t\t0x0042\n#define REG_MAC_PINMUX_CFG_8723D\t\t0x0043\n#define REG_GPIO_PIN_CTRL_8723D\t\t\t0x0044\n#define REG_GPIO_INTM_8723D\t\t\t\t0x0048\n#define REG_LEDCFG0_8723D\t\t\t\t0x004C\n#define REG_LEDCFG1_8723D\t\t\t\t0x004D\n#define REG_LEDCFG2_8723D\t\t\t\t0x004E\n#define REG_LEDCFG3_8723D\t\t\t\t0x004F\n#define REG_FSIMR_8723D\t\t\t\t\t0x0050\n#define REG_FSISR_8723D\t\t\t\t\t0x0054\n#define REG_HSIMR_8723D\t\t\t\t\t0x0058\n#define REG_HSISR_8723D\t\t\t\t\t0x005c\n#define REG_GPIO_EXT_CTRL\t\t\t\t0x0060\n#define REG_PAD_CTRL1_8723D\t\t0x0064\n#define REG_MULTI_FUNC_CTRL_8723D\t\t0x0068\n#define REG_GPIO_STATUS_8723D\t\t\t0x006C\n#define REG_SDIO_CTRL_8723D\t\t\t\t0x0070\n#define REG_OPT_CTRL_8723D\t\t\t\t0x0074\n#define REG_AFE_CTRL_4_8723D\t\t0x0078\n#define REG_MCUFWDL_8723D\t\t\t\t0x0080\n#define REG_8051FW_CTRL_8723D\t\t\t0x0080\n#define REG_HMEBOX_DBG_0_8723D\t0x0088\n#define REG_HMEBOX_DBG_1_8723D\t0x008A\n#define REG_HMEBOX_DBG_2_8723D\t0x008C\n#define REG_HMEBOX_DBG_3_8723D\t0x008E\n#define REG_WLLPS_CTRL\t\t0x0090\n#define REG_HIMR0_8723D\t\t\t\t\t0x00B0\n#define REG_HISR0_8723D\t\t\t\t\t0x00B4\n#define REG_HIMR1_8723D\t\t\t\t\t0x00B8\n#define REG_HISR1_8723D\t\t\t\t\t0x00BC\n#define REG_PMC_DBG_CTRL2_8723D\t\t\t0x00CC\n#define\tREG_EFUSE_BURN_GNT_8723D\t\t0x00CF\n#define REG_HPON_FSM_8723D\t\t\t\t0x00EC\n#define REG_SYS_CFG1_8723D\t\t\t\t0x00F0\n#define REG_SYS_CFG_8723D\t\t\t\t0x00FC\n#define REG_ROM_VERSION\t\t\t\t\t0x00FD\n\n/* -----------------------------------------------------\n *\n *\t0x0100h ~ 0x01FFh\tMACTOP General Configuration\n *\n * ----------------------------------------------------- */\n#define REG_C2HEVT_CMD_ID_8723D\t0x01A0\n#define REG_C2HEVT_CMD_SEQ_88XX\t\t0x01A1\n#define REG_C2hEVT_CMD_CONTENT_88XX\t0x01A2\n#define REG_C2HEVT_CMD_LEN_8723D        0x01AE\n#define REG_C2HEVT_CLEAR_8723D\t\t\t0x01AF\n#define REG_MCUTST_1_8723D\t\t\t\t0x01C0\n#define REG_WOWLAN_WAKE_REASON 0x01C7\n#define REG_FMETHR_8723D\t\t\t\t0x01C8\n#define REG_HMETFR_8723D\t\t\t\t0x01CC\n#define REG_HMEBOX_0_8723D\t\t\t\t0x01D0\n#define REG_HMEBOX_1_8723D\t\t\t\t0x01D4\n#define REG_HMEBOX_2_8723D\t\t\t\t0x01D8\n#define REG_HMEBOX_3_8723D\t\t\t\t0x01DC\n#define REG_LLT_INIT_8723D\t\t\t\t0x01E0\n#define REG_HMEBOX_EXT0_8723D\t\t\t0x01F0\n#define REG_HMEBOX_EXT1_8723D\t\t\t0x01F4\n#define REG_HMEBOX_EXT2_8723D\t\t\t0x01F8\n#define REG_HMEBOX_EXT3_8723D\t\t\t0x01FC\n\n/* -----------------------------------------------------\n *\n *\t0x0200h ~ 0x027Fh\tTXDMA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_RQPN_8723D\t\t\t\t\t0x0200\n#define REG_FIFOPAGE_8723D\t\t\t\t0x0204\n#define REG_DWBCN0_CTRL_8723D\t\t\tREG_TDECTRL\n#define REG_TXDMA_OFFSET_CHK_8723D\t0x020C\n#define REG_TXDMA_STATUS_8723D\t\t0x0210\n#define REG_RQPN_NPQ_8723D\t\t\t0x0214\n#define REG_DWBCN1_CTRL_8723D\t\t\t0x0228\n\n\n/* -----------------------------------------------------\n *\n *\t0x0280h ~ 0x02FFh\tRXDMA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_RXDMA_AGG_PG_TH_8723D\t\t0x0280\n#define REG_FW_UPD_RDPTR_8723D\t\t0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */\n#define REG_RXDMA_CONTROL_8723D\t\t0x0286 /* Control the RX DMA. */\n#define REG_RXDMA_STATUS_8723D\t\t\t0x0288\n#define REG_RXDMA_MODE_CTRL_8723D\t\t0x0290\n#define REG_EARLY_MODE_CONTROL_8723D\t0x02BC\n#define REG_RSVD5_8723D\t\t\t\t\t0x02F0\n#define REG_RSVD6_8723D\t\t\t\t\t0x02F4\n\n/* -----------------------------------------------------\n *\n *\t0x0300h ~ 0x03FFh\tPCIe\n *\n * ----------------------------------------------------- */\n#define\tREG_PCIE_CTRL_REG_8723D\t\t\t0x0300\n#define\tREG_INT_MIG_8723D\t\t\t\t0x0304\t/* Interrupt Migration */\n#define\tREG_BCNQ_TXBD_DESA_8723D\t\t0x0308\t/* TX Beacon Descriptor Address */\n#define\tREG_MGQ_TXBD_DESA_8723D\t\t\t0x0310\t/* TX Manage Queue Descriptor Address */\n#define\tREG_VOQ_TXBD_DESA_8723D\t\t\t0x0318\t/* TX VO Queue Descriptor Address */\n#define\tREG_VIQ_TXBD_DESA_8723D\t\t\t0x0320\t/* TX VI Queue Descriptor Address */\n#define\tREG_BEQ_TXBD_DESA_8723D\t\t\t0x0328\t/* TX BE Queue Descriptor Address */\n#define\tREG_BKQ_TXBD_DESA_8723D\t\t\t0x0330\t/* TX BK Queue Descriptor Address */\n#define\tREG_RXQ_RXBD_DESA_8723D\t\t\t0x0338\t/* RX Queue\tDescriptor Address */\n#define REG_HI0Q_TXBD_DESA_8723D\t\t0x0340\n#define REG_HI1Q_TXBD_DESA_8723D\t\t0x0348\n#define REG_HI2Q_TXBD_DESA_8723D\t\t0x0350\n#define REG_HI3Q_TXBD_DESA_8723D\t\t0x0358\n#define REG_HI4Q_TXBD_DESA_8723D\t\t0x0360\n#define REG_HI5Q_TXBD_DESA_8723D\t\t0x0368\n#define REG_HI6Q_TXBD_DESA_8723D\t\t0x0370\n#define REG_HI7Q_TXBD_DESA_8723D\t\t0x0378\n#define\tREG_MGQ_TXBD_NUM_8723D\t\t\t0x0380\n#define\tREG_RX_RXBD_NUM_8723D\t\t\t0x0382\n#define\tREG_VOQ_TXBD_NUM_8723D\t\t\t0x0384\n#define\tREG_VIQ_TXBD_NUM_8723D\t\t\t0x0386\n#define\tREG_BEQ_TXBD_NUM_8723D\t\t\t0x0388\n#define\tREG_BKQ_TXBD_NUM_8723D\t\t\t0x038A\n#define\tREG_HI0Q_TXBD_NUM_8723D\t\t\t0x038C\n#define\tREG_HI1Q_TXBD_NUM_8723D\t\t\t0x038E\n#define\tREG_HI2Q_TXBD_NUM_8723D\t\t\t0x0390\n#define\tREG_HI3Q_TXBD_NUM_8723D\t\t\t0x0392\n#define\tREG_HI4Q_TXBD_NUM_8723D\t\t\t0x0394\n#define\tREG_HI5Q_TXBD_NUM_8723D\t\t\t0x0396\n#define\tREG_HI6Q_TXBD_NUM_8723D\t\t\t0x0398\n#define\tREG_HI7Q_TXBD_NUM_8723D\t\t\t0x039A\n#define\tREG_TSFTIMER_HCI_8723D\t\t\t0x039C\n#define\tREG_BD_RW_PTR_CLR_8723D\t\t\t0x039C\n\n/* Read Write Point */\n#define\tREG_VOQ_TXBD_IDX_8723D\t\t\t0x03A0\n#define\tREG_VIQ_TXBD_IDX_8723D\t\t\t0x03A4\n#define\tREG_BEQ_TXBD_IDX_8723D\t\t\t0x03A8\n#define\tREG_BKQ_TXBD_IDX_8723D\t\t\t0x03AC\n#define\tREG_MGQ_TXBD_IDX_8723D\t\t\t0x03B0\n#define\tREG_RXQ_TXBD_IDX_8723D\t\t\t0x03B4\n#define\tREG_HI0Q_TXBD_IDX_8723D\t\t\t0x03B8\n#define\tREG_HI1Q_TXBD_IDX_8723D\t\t\t0x03BC\n#define\tREG_HI2Q_TXBD_IDX_8723D\t\t\t0x03C0\n#define\tREG_HI3Q_TXBD_IDX_8723D\t\t\t0x03C4\n#define\tREG_HI4Q_TXBD_IDX_8723D\t\t\t0x03C8\n#define\tREG_HI5Q_TXBD_IDX_8723D\t\t\t0x03CC\n#define\tREG_HI6Q_TXBD_IDX_8723D\t\t\t0x03D0\n#define\tREG_HI7Q_TXBD_IDX_8723D\t\t\t0x03D4\n\n#define\tREG_PCIE_HCPWM_8723DE\t\t\t0x03D8 /* ?????? */\n#define\tREG_PCIE_HRPWM_8723DE\t\t\t0x03DC\t/* PCIe RPWM  ?????? */\n#define\tREG_DBI_WDATA_V1_8723D\t\t\t0x03E8\n#define\tREG_DBI_RDATA_V1_8723D\t\t\t0x03EC\n#define\tREG_DBI_FLAG_V1_8723D\t\t\t0x03F0\n#define REG_MDIO_V1_8723D\t\t\t\t0x03F4\n#define REG_PCIE_MIX_CFG_8723D\t\t\t0x03F8\n#define REG_HCI_MIX_CFG_8723D\t\t\t0x03FC\n\n/* -----------------------------------------------------\n *\n *\t0x0400h ~ 0x047Fh\tProtocol Configuration\n *\n * ----------------------------------------------------- */\n#define REG_VOQ_INFORMATION_8723D\t\t0x0400\n#define REG_VIQ_INFORMATION_8723D\t\t0x0404\n#define REG_BEQ_INFORMATION_8723D\t\t0x0408\n#define REG_BKQ_INFORMATION_8723D\t\t0x040C\n#define REG_MGQ_INFORMATION_8723D\t\t0x0410\n#define REG_HGQ_INFORMATION_8723D\t\t0x0414\n#define REG_BCNQ_INFORMATION_8723D\t0x0418\n#define REG_TXPKT_EMPTY_8723D\t\t\t0x041A\n\n#define REG_FWHW_TXQ_CTRL_8723D\t\t0x0420\n#define REG_HWSEQ_CTRL_8723D\t\t\t0x0423\n#define REG_TXPKTBUF_BCNQ_BDNY_8723D\t0x0424\n#define REG_TXPKTBUF_MGQ_BDNY_8723D\t0x0425\n#define REG_LIFECTRL_CTRL_8723D\t\t\t0x0426\n#define REG_MULTI_BCNQ_OFFSET_8723D\t0x0427\n#define REG_SPEC_SIFS_8723D\t\t\t\t0x0428\n#define REG_RL_8723D\t\t\t\t\t\t0x042A\n#define REG_TXBF_CTRL_8723D\t\t\t\t0x042C\n#define REG_DARFRC_8723D\t\t\t\t0x0430\n#define REG_RARFRC_8723D\t\t\t\t0x0438\n#define REG_RRSR_8723D\t\t\t\t\t0x0440\n#define REG_ARFR0_8723D\t\t\t\t\t0x0444\n#define REG_ARFR1_8723D\t\t\t\t\t0x044C\n#define REG_CCK_CHECK_8723D\t\t\t\t0x0454\n#define REG_AMPDU_MAX_TIME_8723D\t\t0x0456\n#define REG_TXPKTBUF_BCNQ_BDNY1_8723D\t0x0457\n\n#define REG_AMPDU_MAX_LENGTH_8723D\t0x0458\n#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723D\t0x045D\n#define REG_NDPA_OPT_CTRL_8723D\t\t0x045F\n#define REG_FAST_EDCA_CTRL_8723D\t\t0x0460\n#define REG_RD_RESP_PKT_TH_8723D\t\t0x0463\n#define REG_DATA_SC_8723D\t\t\t\t0x0483\n#ifdef CONFIG_WOWLAN\n\t#define REG_TXPKTBUF_IV_LOW             0x0484\n\t#define REG_TXPKTBUF_IV_HIGH            0x0488\n#endif\n#define REG_TXRPT_START_OFFSET\t\t0x04AC\n#define REG_POWER_STAGE1_8723D\t\t0x04B4\n#define REG_POWER_STAGE2_8723D\t\t0x04B8\n#define REG_AMPDU_BURST_MODE_8723D\t0x04BC\n#define REG_PKT_VO_VI_LIFE_TIME_8723D\t0x04C0\n#define REG_PKT_BE_BK_LIFE_TIME_8723D\t0x04C2\n#define REG_STBC_SETTING_8723D\t\t\t0x04C4\n#define REG_HT_SINGLE_AMPDU_8723D\t\t0x04C7\n#define REG_PROT_MODE_CTRL_8723D\t\t0x04C8\n#define REG_MAX_AGGR_NUM_8723D\t\t0x04CA\n#define REG_RTS_MAX_AGGR_NUM_8723D\t0x04CB\n#define REG_BAR_MODE_CTRL_8723D\t\t0x04CC\n#define REG_RA_TRY_RATE_AGG_LMT_8723D\t0x04CF\n#define REG_MACID_PKT_DROP0_8723D\t\t0x04D0\n#define REG_MACID_PKT_SLEEP_8723D\t\t0x04D4\n\n/* -----------------------------------------------------\n *\n *\t0x0500h ~ 0x05FFh\tEDCA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_EDCA_VO_PARAM_8723D\t\t0x0500\n#define REG_EDCA_VI_PARAM_8723D\t\t0x0504\n#define REG_EDCA_BE_PARAM_8723D\t\t0x0508\n#define REG_EDCA_BK_PARAM_8723D\t\t0x050C\n#define REG_BCNTCFG_8723D\t\t\t\t0x0510\n#define REG_PIFS_8723D\t\t\t\t\t0x0512\n#define REG_RDG_PIFS_8723D\t\t\t\t0x0513\n#define REG_SIFS_CTX_8723D\t\t\t\t0x0514\n#define REG_SIFS_TRX_8723D\t\t\t\t0x0516\n#define REG_AGGR_BREAK_TIME_8723D\t\t0x051A\n#define REG_SLOT_8723D\t\t\t\t\t0x051B\n#define REG_TX_PTCL_CTRL_8723D\t\t\t0x0520\n#define REG_TXPAUSE_8723D\t\t\t\t0x0522\n#define REG_DIS_TXREQ_CLR_8723D\t\t0x0523\n#define REG_RD_CTRL_8723D\t\t\t\t0x0524\n/*\n * Format for offset 540h-542h:\n *\t[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.\n *\t[7:4]:   Reserved.\n *\t[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.\n *\t[23:20]: Reserved\n * Description:\n *\t              |\n * |<--Setup--|--Hold------------>|\n *\t--------------|----------------------\n * |\n * TBTT\n * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.\n * Described by Designer Tim and Bruce, 2011-01-14.\n *   */\n#define REG_TBTT_PROHIBIT_8723D\t\t\t0x0540\n#define REG_RD_NAV_NXT_8723D\t\t\t0x0544\n#define REG_NAV_PROT_LEN_8723D\t\t\t0x0546\n#define REG_BCN_CTRL_8723D\t\t\t\t0x0550\n#define REG_BCN_CTRL_1_8723D\t\t\t0x0551\n#define REG_MBID_NUM_8723D\t\t\t\t0x0552\n#define REG_DUAL_TSF_RST_8723D\t\t\t0x0553\n#define REG_BCN_INTERVAL_8723D\t\t\t0x0554\n#define REG_DRVERLYINT_8723D\t\t\t0x0558\n#define REG_BCNDMATIM_8723D\t\t\t0x0559\n#define REG_ATIMWND_8723D\t\t\t\t0x055A\n#define REG_USTIME_TSF_8723D\t\t\t0x055C\n#define REG_BCN_MAX_ERR_8723D\t\t\t0x055D\n#define REG_RXTSF_OFFSET_CCK_8723D\t\t0x055E\n#define REG_RXTSF_OFFSET_OFDM_8723D\t0x055F\n#define REG_TSFTR_8723D\t\t\t\t\t0x0560\n#define REG_CTWND_8723D\t\t\t\t\t0x0572\n#define REG_SECONDARY_CCA_CTRL_8723D\t0x0577\n#define REG_PSTIMER_8723D\t\t\t\t0x0580\n#define REG_TIMER0_8723D\t\t\t\t0x0584\n#define REG_TIMER1_8723D\t\t\t\t0x0588\n#define REG_ACMHWCTRL_8723D\t\t\t0x05C0\n#define REG_SCH_TXCMD_8723D\t\t\t0x05F8\n\n/* -----------------------------------------------------\n *\n *\t0x0600h ~ 0x07FFh\tWMAC Configuration\n *\n * ----------------------------------------------------- */\n#define REG_MAC_CR_8723D\t\t\t\t0x0600\n#define REG_TCR_8723D\t\t\t\t\t0x0604\n#define REG_RCR_8723D\t\t\t\t\t0x0608\n#define REG_RX_PKT_LIMIT_8723D\t\t\t0x060C\n#define REG_RX_DLK_TIME_8723D\t\t\t0x060D\n#define REG_RX_DRVINFO_SZ_8723D\t\t0x060F\n\n#define REG_MACID_8723D\t\t\t\t\t0x0610\n#define REG_BSSID_8723D\t\t\t\t\t0x0618\n#define REG_MAR_8723D\t\t\t\t\t0x0620\n#define REG_MBIDCAMCFG_8723D\t\t\t0x0628\n#define REG_WOWLAN_GTK_DBG1\t0x630\n#define REG_WOWLAN_GTK_DBG2\t0x634\n\n#define REG_USTIME_EDCA_8723D\t\t\t0x0638\n#define REG_MAC_SPEC_SIFS_8723D\t\t0x063A\n#define REG_RESP_SIFP_CCK_8723D\t\t\t0x063C\n#define REG_RESP_SIFS_OFDM_8723D\t\t0x063E\n#define REG_ACKTO_8723D\t\t\t\t\t0x0640\n#define REG_CTS2TO_8723D\t\t\t\t0x0641\n#define REG_EIFS_8723D\t\t\t\t\t0x0642\n\n#define REG_NAV_UPPER_8723D\t\t\t0x0652\t/* unit of 128 */\n#define REG_TRXPTCL_CTL_8723D\t\t\t0x0668\n\n/* Security */\n#define REG_CAMCMD_8723D\t\t\t\t0x0670\n#define REG_CAMWRITE_8723D\t\t\t\t0x0674\n#define REG_CAMREAD_8723D\t\t\t\t0x0678\n#define REG_CAMDBG_8723D\t\t\t\t0x067C\n#define REG_SECCFG_8723D\t\t\t\t0x0680\n\n/* Power */\n#define REG_WOW_CTRL_8723D\t\t\t\t0x0690\n#define REG_PS_RX_INFO_8723D\t\t\t0x0692\n#define REG_UAPSD_TID_8723D\t\t\t\t0x0693\n#define REG_WKFMCAM_CMD_8723D\t\t\t0x0698\n#define REG_WKFMCAM_NUM_8723D\t\t\t0x0698\n#define REG_WKFMCAM_RWD_8723D\t\t\t0x069C\n#define REG_RXFLTMAP0_8723D\t\t\t\t0x06A0\n#define REG_RXFLTMAP1_8723D\t\t\t\t0x06A2\n#define REG_RXFLTMAP2_8723D\t\t\t\t0x06A4\n#define REG_BCN_PSR_RPT_8723D\t\t\t0x06A8\n#define REG_BT_COEX_TABLE_8723D\t\t0x06C0\n#define REG_BFMER0_INFO_8723D\t\t\t0x06E4\n#define REG_BFMER1_INFO_8723D\t\t\t0x06EC\n#define REG_CSI_RPT_PARAM_BW20_8723D\t0x06F4\n#define REG_CSI_RPT_PARAM_BW40_8723D\t0x06F8\n#define REG_CSI_RPT_PARAM_BW80_8723D\t0x06FC\n\n/* Hardware Port 2 */\n#define REG_MACID1_8723D\t\t\t\t0x0700\n#define REG_BSSID1_8723D\t\t\t\t0x0708\n#define REG_BFMEE_SEL_8723D\t\t\t\t0x0714\n#define REG_SND_PTCL_CTRL_8723D\t\t0x0718\n\n/* LTR */\n#define REG_LTR_CTRL_BASIC_8723D\t\t0x07A4\n#define REG_LTR_IDLE_LATENCY_V1_8723D\t\t0x0798\n#define REG_LTR_ACTIVE_LATENCY_V1_8723D\t\t0x079C\n\n/* LTE_COEX */\n#define REG_LTECOEX_CTRL\t\t\t0x07C0\n#define REG_LTECOEX_WRITE_DATA\t\t0x07C4\n#define REG_LTECOEX_READ_DATA\t\t0x07C8\n#define REG_LTECOEX_PATH_CONTROL\t0x70\n\n/* ************************************************************\n * SDIO Bus Specification\n * ************************************************************ */\n\n/* -----------------------------------------------------\n * SDIO CMD Address Mapping\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n * I/O bus domain (Host)\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n * SDIO register\n * ----------------------------------------------------- */\n#define SDIO_REG_HCPWM1_8723D\t0x025 /* HCI Current Power Mode 1 */\n\n\n/* ****************************************************************************\n *\t8723 Regsiter Bit and Content definition\n * **************************************************************************** */\n\n#define BIT_USB_RXDMA_AGG_EN\tBIT(31)\n#define RXDMA_AGG_MODE_EN\t\tBIT(1)\n\n#ifdef CONFIG_WOWLAN\n\t#define RXPKT_RELEASE_POLL\t\tBIT(16)\n\t#define RXDMA_IDLE\t\t\t\tBIT(17)\n\t#define RW_RELEASE_EN\t\t\tBIT(18)\n#endif\n\n/* 2 HSISR\n * interrupt mask which needs to clear */\n#define MASK_HSISR_CLEAR\t\t(HSISR_GPIO12_0_INT |\\\n\t\tHSISR_SPS_OCP_INT |\\\n\t\tHSISR_RON_INT |\\\n\t\tHSISR_PDNINT |\\\n\t\tHSISR_GPIO9_INT)\n\n#ifdef CONFIG_RF_POWER_TRIM\n\t#ifdef CONFIG_RTL8723D\n\t\t#define EEPROM_RF_GAIN_OFFSET\t\t\t0xC1\n\t#endif\n\n\t#define EEPROM_RF_GAIN_VAL\t\t\t\t0x1F6\n#endif /*CONFIG_RF_POWER_TRIM*/\n\n#ifdef CONFIG_PCI_HCI\n\t/* #define IMR_RX_MASK\t\t(IMR_ROK_8723D|IMR_RDU_8723D|IMR_RXFOVW_8723D) */\n\t#define IMR_TX_MASK\t\t\t(IMR_VODOK_8723D | IMR_VIDOK_8723D | IMR_BEDOK_8723D | IMR_BKDOK_8723D | IMR_MGNTDOK_8723D | IMR_HIGHDOK_8723D)\n\n\t#define RT_BCN_INT_MASKS\t(IMR_BCNDMAINT0_8723D | IMR_TXBCN0OK_8723D | IMR_TXBCN0ERR_8723D | IMR_BCNDERR0_8723D)\n\n\t#define RT_AC_INT_MASKS\t(IMR_VIDOK_8723D | IMR_VODOK_8723D | IMR_BEDOK_8723D | IMR_BKDOK_8723D)\n#endif\n\n#endif /* __RTL8723D_SPEC_H__ */\n"
  },
  {
    "path": "include/rtl8723d_sreset.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8723D_SRESET_H_\n#define _RTL8723D_SRESET_H_\n\n#include <rtw_sreset.h>\n\n#ifdef DBG_CONFIG_ERROR_DETECT\n\textern void rtl8723d_sreset_xmit_status_check(_adapter *padapter);\n\textern void rtl8723d_sreset_linked_status_check(_adapter *padapter);\n#endif\n#endif\n"
  },
  {
    "path": "include/rtl8723d_xmit.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8723D_XMIT_H__\n#define __RTL8723D_XMIT_H__\n\n\n#define MAX_TID (15)\n\n\n#ifndef __INC_HAL8723DDESC_H\n#define __INC_HAL8723DDESC_H\n\n#define RX_STATUS_DESC_SIZE_8723D\t\t24\n#define RX_DRV_INFO_SIZE_UNIT_8723D 8\n\n\n/* DWORD 0 */\n#define SET_RX_STATUS_DESC_PKT_LEN_8723D(__pRxStatusDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)\n#define SET_RX_STATUS_DESC_EOR_8723D(__pRxStatusDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)\n#define SET_RX_STATUS_DESC_OWN_8723D(__pRxStatusDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)\n\n#define GET_RX_STATUS_DESC_PKT_LEN_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)\n#define GET_RX_STATUS_DESC_CRC32_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)\n#define GET_RX_STATUS_DESC_ICV_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)\n#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)\n#define GET_RX_STATUS_DESC_SECURITY_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)\n#define GET_RX_STATUS_DESC_QOS_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)\n#define GET_RX_STATUS_DESC_SHIFT_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)\n#define GET_RX_STATUS_DESC_PHY_STATUS_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)\n#define GET_RX_STATUS_DESC_SWDEC_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)\n#define GET_RX_STATUS_DESC_EOR_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)\n#define GET_RX_STATUS_DESC_OWN_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)\n\n/* DWORD 1 */\n#define GET_RX_STATUS_DESC_MACID_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)\n#define GET_RX_STATUS_DESC_TID_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)\n#define GET_RX_STATUS_DESC_AMSDU_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)\n#define GET_RX_STATUS_DESC_RXID_MATCH_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)\n#define GET_RX_STATUS_DESC_PAGGR_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)\n#define GET_RX_STATUS_DESC_A1_FIT_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)\n#define GET_RX_STATUS_DESC_CHKERR_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)\n#define GET_RX_STATUS_DESC_IPVER_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)\n#define GET_RX_STATUS_DESC_IS_TCPUDP__8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)\n#define GET_RX_STATUS_DESC_CHK_VLD_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)\n#define GET_RX_STATUS_DESC_PAM_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)\n#define GET_RX_STATUS_DESC_PWR_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)\n#define GET_RX_STATUS_DESC_MORE_DATA_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)\n#define GET_RX_STATUS_DESC_MORE_FRAG_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)\n#define GET_RX_STATUS_DESC_TYPE_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)\n#define GET_RX_STATUS_DESC_MC_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)\n#define GET_RX_STATUS_DESC_BC_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)\n\n/* DWORD 2 */\n#define GET_RX_STATUS_DESC_SEQ_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)\n#define GET_RX_STATUS_DESC_FRAG_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)\n#define GET_RX_STATUS_DESC_RX_IS_QOS_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)\n#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)\n#define GET_RX_STATUS_DESC_RPT_SEL_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)\n#define GET_RX_STATUS_DESC_FCS_OK_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)\n\n/* DWORD 3 */\n#define GET_RX_STATUS_DESC_RX_RATE_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)\n#define GET_RX_STATUS_DESC_HTC_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)\n#define GET_RX_STATUS_DESC_EOSP_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)\n#define GET_RX_STATUS_DESC_BSSID_FIT_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)\n#ifdef CONFIG_USB_RX_AGGREGATION\n#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)\n#endif\n#define GET_RX_STATUS_DESC_PATTERN_MATCH_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)\n#define GET_RX_STATUS_DESC_UNICAST_MATCH_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)\n#define GET_RX_STATUS_DESC_MAGIC_MATCH_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)\n\n/* DWORD 6 */\n#define GET_RX_STATUS_DESC_MATCH_ID_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7)\n\n/* DWORD 5 */\n#define GET_RX_STATUS_DESC_TSFL_8723D(__pRxStatusDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)\n\n#define GET_RX_STATUS_DESC_BUFF_ADDR_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)\n#define GET_RX_STATUS_DESC_BUFF_ADDR64_8723D(__pRxDesc) \\\n\tLE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)\n\n#define SET_RX_STATUS_DESC_BUFF_ADDR_8723D(__pRxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)\n\n\n/* Dword 0, rsvd: bit26, bit28 */\n#define GET_TX_DESC_OWN_8723D(__pTxDesc)\\\n\tLE_BITS_TO_4BYTE(__pTxDesc, 31, 1)\n\n#define SET_TX_DESC_PKT_SIZE_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)\n#define SET_TX_DESC_OFFSET_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)\n#define SET_TX_DESC_BMC_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)\n#define SET_TX_DESC_HTC_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)\n#define SET_TX_DESC_AMSDU_PAD_EN_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)\n#define SET_TX_DESC_NO_ACM_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)\n#define SET_TX_DESC_GF_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)\n\n/* Dword 1 */\n#define SET_TX_DESC_MACID_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)\n#define SET_TX_DESC_QUEUE_SEL_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)\n#define SET_TX_DESC_RDG_NAV_EXT_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)\n#define SET_TX_DESC_LSIG_TXOP_EN_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)\n#define SET_TX_DESC_PIFS_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)\n#define SET_TX_DESC_RATE_ID_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)\n#define SET_TX_DESC_EN_DESC_ID_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)\n#define SET_TX_DESC_SEC_TYPE_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)\n#define SET_TX_DESC_PKT_OFFSET_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)\n#define SET_TX_DESC_MORE_DATA_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)\n\n/* Dword 2  remove P_AID, G_ID field*/\n#define SET_TX_DESC_CCA_RTS_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)\n#define SET_TX_DESC_AGG_ENABLE_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)\n#define SET_TX_DESC_RDG_ENABLE_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)\n#define SET_TX_DESC_NULL0_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)\n#define SET_TX_DESC_NULL1_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)\n#define SET_TX_DESC_BK_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)\n#define SET_TX_DESC_MORE_FRAG_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)\n#define SET_TX_DESC_RAW_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)\n#define SET_TX_DESC_CCX_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)\n#define SET_TX_DESC_AMPDU_DENSITY_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)\n#define SET_TX_DESC_BT_INT_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)\n#define SET_TX_DESC_FTM_EN_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 30, 1, __Value)\n\n/* Dword 3 */\n#define SET_TX_DESC_HWSEQ_SEL_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)\n#define SET_TX_DESC_USE_RATE_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)\n#define SET_TX_DESC_DISABLE_RTS_FB_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)\n#define SET_TX_DESC_DISABLE_FB_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)\n#define SET_TX_DESC_CTS2SELF_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)\n#define SET_TX_DESC_RTS_ENABLE_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)\n#define SET_TX_DESC_HW_RTS_ENABLE_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)\n#define SET_TX_DESC_PORT_ID_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 2, __Value)\n#define SET_TX_DESC_NAV_USE_HDR_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)\n#define SET_TX_DESC_USE_MAX_LEN_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)\n#define SET_TX_DESC_MAX_AGG_NUM_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)\n#define SET_TX_DESC_AMPDU_MAX_TIME_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)\n\n/* Dword 4 */\n#define SET_TX_DESC_TX_RATE_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)\n#define SET_TX_DESC_TX_TRY_RATE_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)\n#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)\n#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)\n#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)\n#define SET_TX_DESC_DATA_RETRY_LIMIT_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)\n#define SET_TX_DESC_RTS_RATE_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)\n#define SET_TX_DESC_PCTS_EN_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)\n#define SET_TX_DESC_PCTS_MASK_IDX_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)\n\n/* Dword 5 */\n#define SET_TX_DESC_DATA_SC_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)\n#define SET_TX_DESC_DATA_SHORT_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)\n#define SET_TX_DESC_DATA_BW_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)\n#define SET_TX_DESC_DATA_STBC_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)\n#define SET_TX_DESC_RTS_STBC_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)\n#define SET_TX_DESC_RTS_SHORT_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)\n#define SET_TX_DESC_RTS_SC_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)\n#define SET_TX_DESC_PATH_A_EN_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value)\n#define SET_TX_DESC_TXPWR_OF_SET_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)\n\n/* Dword 6 */\n#define SET_TX_DESC_SW_DEFINE_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)\n#define SET_TX_DESC_MBSSID_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)\n#define SET_TX_DESC_RF_SEL_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)\n\n/* Dword 7 */\n#ifdef CONFIG_PCI_HCI\n#define SET_TX_DESC_TX_BUFFER_SIZE_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n#endif\n\n#ifdef CONFIG_USB_HCI\n#define SET_TX_DESC_TX_DESC_CHECKSUM_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n#endif\n\n#ifdef CONFIG_SDIO_HCI\n#define SET_TX_DESC_TX_TIMESTAMP_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)\n#endif\n\n#define SET_TX_DESC_USB_TXAGG_NUM_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)\n\n/* Dword 8 */\n#define SET_TX_DESC_RTS_RC_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)\n#define SET_TX_DESC_BAR_RC_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)\n#define SET_TX_DESC_DATA_RC_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)\n#define SET_TX_DESC_HWSEQ_EN_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)\n#define SET_TX_DESC_NEXTHEADPAGE_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)\n#define SET_TX_DESC_TAILPAGE_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)\n\n/* Dword 9 */\n#define SET_TX_DESC_PADDING_LEN_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)\n#define SET_TX_DESC_SEQ_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)\n#define SET_TX_DESC_FINAL_DATA_RATE_8723D(__pTxDesc, __Value) \\\n\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)\n\n\n#define SET_EARLYMODE_PKTNUM_8723D(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)\n#define SET_EARLYMODE_LEN0_8723D(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)\n#define SET_EARLYMODE_LEN1_1_8723D(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)\n#define SET_EARLYMODE_LEN1_2_8723D(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)\n#define SET_EARLYMODE_LEN2_8723D(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,\t__Value)\n#define SET_EARLYMODE_LEN3_8723D(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)\n\n\n/*-----------------------------------------------------------------*/\n/*\tRTL8723D TX BUFFER DESC                                      */\n/*-----------------------------------------------------------------*/\n#ifdef CONFIG_64BIT_DMA\n\t#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)\n\t#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)\n\t#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)\n\t#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)\n#else\n\t#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)\n\t#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)\n\t#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)\n\t#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu)\t/* 64 BIT mode only */\n#endif\n/* ********************************************************* */\n\n/* 64 bits  -- 32 bits */\n/* =======     ======= */\n/* Dword 0     0 */\n#define SET_TX_BUFF_DESC_LEN_0_8723D(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)\n#define SET_TX_BUFF_DESC_PSB_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)\n#define SET_TX_BUFF_DESC_OWN_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)\n\n/* Dword 1     1 */\n#define SET_TX_BUFF_DESC_ADDR_LOW_0_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)\n#define GET_TX_BUFF_DESC_ADDR_LOW_0_8723D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)\n/* Dword 2     NA */\n#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value)\n#ifdef CONFIG_64BIT_DMA\n\t#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)\n#else\n\t#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc) 0\n#endif\n/* Dword 3     NA */\n/* RESERVED 0 */\n/* Dword 4     2 */\n#define SET_TX_BUFF_DESC_LEN_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value)\n#define SET_TX_BUFF_DESC_AMSDU_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value)\n/* Dword 5     3 */\n#define SET_TX_BUFF_DESC_ADDR_LOW_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value)\n/* Dword 6     NA */\n#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value)\n/* Dword 7     NA */\n/*RESERVED 0 */\n/* Dword 8     4 */\n#define SET_TX_BUFF_DESC_LEN_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value)\n#define SET_TX_BUFF_DESC_AMSDU_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value)\n/* Dword 9     5 */\n#define SET_TX_BUFF_DESC_ADDR_LOW_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value)\n/* Dword 10    NA */\n#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value)\n/* Dword 11    NA */\n/*RESERVED 0 */\n/* Dword 12    6 */\n#define SET_TX_BUFF_DESC_LEN_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value)\n#define SET_TX_BUFF_DESC_AMSDU_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value)\n/* Dword 13    7 */\n#define SET_TX_BUFF_DESC_ADDR_LOW_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value)\n/* Dword 14    NA */\n#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value)\n/* Dword 15    NA */\n/*RESERVED 0 */\n\n\n#endif\n/* -----------------------------------------------------------\n *\n *\tRate\n *\n * -----------------------------------------------------------\n * CCK Rates, TxHT = 0 */\n#define DESC8723D_RATE1M\t\t\t\t0x00\n#define DESC8723D_RATE2M\t\t\t\t0x01\n#define DESC8723D_RATE5_5M\t\t\t\t0x02\n#define DESC8723D_RATE11M\t\t\t\t0x03\n\n/* OFDM Rates, TxHT = 0 */\n#define DESC8723D_RATE6M\t\t\t\t0x04\n#define DESC8723D_RATE9M\t\t\t\t0x05\n#define DESC8723D_RATE12M\t\t\t\t0x06\n#define DESC8723D_RATE18M\t\t\t\t0x07\n#define DESC8723D_RATE24M\t\t\t\t0x08\n#define DESC8723D_RATE36M\t\t\t\t0x09\n#define DESC8723D_RATE48M\t\t\t\t0x0a\n#define DESC8723D_RATE54M\t\t\t\t0x0b\n\n/* MCS Rates, TxHT = 1 */\n#define DESC8723D_RATEMCS0\t\t\t\t0x0c\n#define DESC8723D_RATEMCS1\t\t\t\t0x0d\n#define DESC8723D_RATEMCS2\t\t\t\t0x0e\n#define DESC8723D_RATEMCS3\t\t\t\t0x0f\n#define DESC8723D_RATEMCS4\t\t\t\t0x10\n#define DESC8723D_RATEMCS5\t\t\t\t0x11\n#define DESC8723D_RATEMCS6\t\t\t\t0x12\n#define DESC8723D_RATEMCS7\t\t\t\t0x13\n#define DESC8723D_RATEMCS8\t\t\t\t0x14\n#define DESC8723D_RATEMCS9\t\t\t\t0x15\n#define DESC8723D_RATEMCS10\t\t0x16\n#define DESC8723D_RATEMCS11\t\t0x17\n#define DESC8723D_RATEMCS12\t\t0x18\n#define DESC8723D_RATEMCS13\t\t0x19\n#define DESC8723D_RATEMCS14\t\t0x1a\n#define DESC8723D_RATEMCS15\t\t0x1b\n#define DESC8723D_RATEVHTSS1MCS0\t\t0x2c\n#define DESC8723D_RATEVHTSS1MCS1\t\t0x2d\n#define DESC8723D_RATEVHTSS1MCS2\t\t0x2e\n#define DESC8723D_RATEVHTSS1MCS3\t\t0x2f\n#define DESC8723D_RATEVHTSS1MCS4\t\t0x30\n#define DESC8723D_RATEVHTSS1MCS5\t\t0x31\n#define DESC8723D_RATEVHTSS1MCS6\t\t0x32\n#define DESC8723D_RATEVHTSS1MCS7\t\t0x33\n#define DESC8723D_RATEVHTSS1MCS8\t\t0x34\n#define DESC8723D_RATEVHTSS1MCS9\t\t0x35\n#define DESC8723D_RATEVHTSS2MCS0\t\t0x36\n#define DESC8723D_RATEVHTSS2MCS1\t\t0x37\n#define DESC8723D_RATEVHTSS2MCS2\t\t0x38\n#define DESC8723D_RATEVHTSS2MCS3\t\t0x39\n#define DESC8723D_RATEVHTSS2MCS4\t\t0x3a\n#define DESC8723D_RATEVHTSS2MCS5\t\t0x3b\n#define DESC8723D_RATEVHTSS2MCS6\t\t0x3c\n#define DESC8723D_RATEVHTSS2MCS7\t\t0x3d\n#define DESC8723D_RATEVHTSS2MCS8\t\t0x3e\n#define DESC8723D_RATEVHTSS2MCS9\t\t0x3f\n\n\n#define\tRX_HAL_IS_CCK_RATE_8723D(pDesc)\\\n\t(GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE1M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE2M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE5_5M || \\\n\t GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE11M)\n\n#ifdef CONFIG_TRX_BD_ARCH\n\tstruct tx_desc;\n#endif\n\nvoid rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc);\nvoid rtl8723d_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);\nvoid rtl8723d_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);\nvoid rtl8723d_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);\nvoid rtl8723d_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);\nvoid rtl8723d_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);\n\n#if defined(CONFIG_CONCURRENT_MODE)\n\tvoid fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);\n#endif\nvoid fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\ts32 rtl8723ds_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8723ds_free_xmit_priv(PADAPTER padapter);\n\ts32 rtl8723ds_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8723ds_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\trtl8723ds_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8723ds_xmit_buf_handler(PADAPTER padapter);\n\tthread_return rtl8723ds_xmit_thread(thread_context context);\n\t#define hal_xmit_handler rtl8723ds_xmit_buf_handler\n#endif\n\n#ifdef CONFIG_USB_HCI\n\ts32 rtl8723du_xmit_buf_handler(PADAPTER padapter);\n\t#define hal_xmit_handler rtl8723du_xmit_buf_handler\n\ts32 rtl8723du_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8723du_free_xmit_priv(PADAPTER padapter);\n\ts32 rtl8723du_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8723du_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\t rtl8723du_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\tvoid rtl8723du_xmit_tasklet(void *priv);\n\ts32 rtl8723du_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\n\tvoid _dbg_dump_tx_info(_adapter\t*padapter, int frame_tag, struct tx_desc *ptxdesc);\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\ts32 rtl8723de_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8723de_free_xmit_priv(PADAPTER padapter);\n\tstruct xmit_buf *rtl8723de_dequeue_xmitbuf(struct rtw_tx_ring *ring);\n\tvoid\trtl8723de_xmitframe_resume(_adapter *padapter);\n\ts32 rtl8723de_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8723de_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\trtl8723de_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\tvoid rtl8723de_xmit_tasklet(void *priv);\n#endif\n\nu8\tBWMapping_8723D(PADAPTER Adapter, struct pkt_attrib *pattrib);\nu8\tSCMapping_8723D(PADAPTER Adapter, struct pkt_attrib\t*pattrib);\n\n#endif\n"
  },
  {
    "path": "include/rtl8812a_cmd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8812A_CMD_H__\n#define __RTL8812A_CMD_H__\n\ntypedef enum _RTL8812_H2C_CMD {\n\tH2C_8812_RSVDPAGE = 0,\n\tH2C_8812_MSRRPT = 1,\n\tH2C_8812_SCAN = 2,\n\tH2C_8812_KEEP_ALIVE_CTRL = 3,\n\tH2C_8812_DISCONNECT_DECISION = 4,\n\n\tH2C_8812_INIT_OFFLOAD = 6,\n\tH2C_8812_AP_OFFLOAD = 8,\n\tH2C_8812_BCN_RSVDPAGE = 9,\n\tH2C_8812_PROBERSP_RSVDPAGE = 10,\n\n\tH2C_8812_SETPWRMODE = 0x20,\n\tH2C_8812_PS_TUNING_PARA = 0x21,\n\tH2C_8812_PS_TUNING_PARA2 = 0x22,\n\tH2C_8812_PS_LPS_PARA = 0x23,\n\tH2C_8812_P2P_PS_OFFLOAD = 0x24,\n\tH2C_8812_INACTIVE_PS = 0x27,\n\tH2C_8812_RA_MASK = 0x40,\n\tH2C_8812_TxBF = 0x41,\n\tH2C_8812_RSSI_REPORT = 0x42,\n\tH2C_8812_IQ_CALIBRATION = 0x45,\n\tH2C_8812_RA_PARA_ADJUST = 0x46,\n\n\tH2C_8812_BT_FW_PATCH = 0x6a,\n\n\tH2C_8812_WO_WLAN = 0x80,\n\tH2C_8812_REMOTE_WAKE_CTRL = 0x81,\n\tH2C_8812_AOAC_GLOBAL_INFO = 0x82,\n\tH2C_8812_AOAC_RSVDPAGE = 0x83,\n\tH2C_8812_FW_SWCHANNL = 0x87,\n\n\tH2C_8812_TSF_RESET = 0xC0,\n\n\tMAX_8812_H2CCMD\n} RTL8812_H2C_CMD;\n\nstruct cmd_msg_parm {\n\tu8 eid; /* element id */\n\tu8 sz; /* sz */\n\tu8 buf[6];\n};\n\nenum {\n\tPWRS\n};\n\nstruct H2C_SS_RFOFF_PARAM {\n\tu8 ROFOn; /* 1: on, 0:off */\n\tu16 gpio_period; /* unit: 1024 us */\n} __attribute__((packed));\n\n\n\n/* _RSVDPAGE_LOC_CMD0 */\n#define SET_8812_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8812_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_8812_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8812_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8812_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n/* _SETPWRMODE_PARM */\n#define SET_8812_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8812_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)\n#define SET_8812_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)\n#define SET_8812_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8812_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8812_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)\n#define SET_8812_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n#define GET_8812_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)\t\t\t\t\t\t\tLE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)\n\n/* _P2P_PS_OFFLOAD */\n#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ENABLE(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_CTWINDOW_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)\n#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_NOA0_EN(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)\n#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_NOA1_EN(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)\n#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)\n#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)\n\n\nvoid\tset_ra_ldpc_8812(struct cmn_sta_info *cmn_sta_info, BOOLEAN bLDPC);\n\n/* host message to firmware cmd */\ns32 fill_h2c_cmd_8812(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);\nvoid rtl8812_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode);\nvoid rtl8812_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);\nu8 rtl8812_set_rssi_cmd(PADAPTER padapter, u8 *param);\nvoid rtl8812_set_wowlan_cmd(_adapter *padapter, u8 enable);\nu8 GetTxBufferRsvdPageNum8812(_adapter *padapter, bool wowlan);\n\n#ifdef CONFIG_BT_COEXIST\nvoid rtl8812a_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);\n#endif /* CONFIG_BT_COEXIST */\n#ifdef CONFIG_P2P_PS\nvoid rtl8812_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_FWLPS_IN_IPS\nvoid rtl8812_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);\n#endif\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\nvoid rtl8812_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);\n#endif\n#endif\n\n/* ------------------------------------\n * C2H format\n * ------------------------------------ */\n\n/* TX Beamforming */\n#define GET_8812_C2H_TXBF_ORIGINATE(_Header)\t\t\tLE_BITS_TO_1BYTE(_Header, 0, 8)\n#define GET_8812_C2H_TXBF_MACID(_Header)\t\t\t\tLE_BITS_TO_1BYTE((_Header + 1), 0, 8)\n\n\n\n/* / TX Feedback Content */\n#define\tUSEC_UNIT_FOR_8812_C2H_TX_RPT_QUEUE_TIME\t\t\t256\n\n#define\tGET_8812_C2H_TX_RPT_QUEUE_SELECT(_Header)\t\t\tLE_BITS_TO_1BYTE((_Header + 0), 0, 5)\n#define\tGET_8812_C2H_TX_RPT_PKT_BROCAST(_Header)\t\t\tLE_BITS_TO_1BYTE((_Header + 0), 5, 1)\n#define\tGET_8812_C2H_TX_RPT_LIFE_TIME_OVER(_Header)\t\t\tLE_BITS_TO_1BYTE((_Header + 0), 6, 1)\n#define\tGET_8812_C2H_TX_RPT_RETRY_OVER(_Header)\t\t\t\tLE_BITS_TO_1BYTE((_Header + 0), 7, 1)\n#define\tGET_8812_C2H_TX_RPT_MAC_ID(_Header)\t\t\t\t\tLE_BITS_TO_1BYTE((_Header + 1), 0, 8)\n#define\tGET_8812_C2H_TX_RPT_DATA_RETRY_CNT(_Header)\t\tLE_BITS_TO_1BYTE((_Header + 2), 0, 6)\n#define\tGET_8812_C2H_TX_RPT_QUEUE_TIME(_Header)\t\t\t\tLE_BITS_TO_2BYTE((_Header + 3), 0, 16)\t/* In unit of 256 microseconds. */\n#define\tGET_8812_C2H_TX_RPT_FINAL_DATA_RATE(_Header)\t\tLE_BITS_TO_1BYTE((_Header + 5), 0, 8)\n\n/* BT_FW_PATCH */\n#define SET_8812_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)\n#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+4, 0, 8, __Value)\n#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+5, 0, 8, __Value)\n\ns32 c2h_handler_8812a(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);\n\n#endif/* __RTL8812A_CMD_H__ */\n"
  },
  {
    "path": "include/rtl8812a_dm.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8812A_DM_H__\n#define __RTL8812A_DM_H__\n\nvoid rtl8812_init_dm_priv(PADAPTER Adapter);\nvoid rtl8812_deinit_dm_priv(PADAPTER Adapter);\nvoid rtl8812_InitHalDm(PADAPTER Adapter);\nvoid rtl8812_HalDmWatchDog(PADAPTER Adapter);\n\n/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */\n\n/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */\n\n#endif\n"
  },
  {
    "path": "include/rtl8812a_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8812A_HAL_H__\n#define __RTL8812A_HAL_H__\n\n/* #include \"hal_com.h\" */\n#include \"hal_data.h\"\n\n/* include HAL Related header after HAL Related compiling flags */\n#include \"rtl8812a_spec.h\"\n#include \"rtl8812a_rf.h\"\n#include \"rtl8812a_dm.h\"\n#include \"rtl8812a_recv.h\"\n#include \"rtl8812a_xmit.h\"\n#include \"rtl8812a_cmd.h\"\n#include \"rtl8812a_led.h\"\n#include \"Hal8812PwrSeq.h\"\n#include \"Hal8821APwrSeq.h\" /* for 8821A/8811A */\n#include \"Hal8812PhyReg.h\"\n#include \"Hal8812PhyCfg.h\"\n#ifdef DBG_CONFIG_ERROR_DETECT\n#include \"rtl8812a_sreset.h\"\n#endif\n\n/* ---------------------------------------------------------------------\n *\t\tRTL8812 Power Configuration CMDs for PCIe interface\n * --------------------------------------------------------------------- */\n#define Rtl8812_NIC_PWR_ON_FLOW\t\t\t\trtl8812_power_on_flow\n#define Rtl8812_NIC_RF_OFF_FLOW\t\t\t\trtl8812_radio_off_flow\n#define Rtl8812_NIC_DISABLE_FLOW\t\t\t\trtl8812_card_disable_flow\n#define Rtl8812_NIC_ENABLE_FLOW\t\t\t\trtl8812_card_enable_flow\n#define Rtl8812_NIC_SUSPEND_FLOW\t\t\t\trtl8812_suspend_flow\n#define Rtl8812_NIC_RESUME_FLOW\t\t\t\trtl8812_resume_flow\n#define Rtl8812_NIC_PDN_FLOW\t\t\t\t\trtl8812_hwpdn_flow\n#define Rtl8812_NIC_LPS_ENTER_FLOW\t\t\trtl8812_enter_lps_flow\n#define Rtl8812_NIC_LPS_LEAVE_FLOW\t\t\t\trtl8812_leave_lps_flow\n\n/* ---------------------------------------------------------------------\n *\t\tRTL8821 Power Configuration CMDs for PCIe interface\n * --------------------------------------------------------------------- */\n#define Rtl8821A_NIC_PWR_ON_FLOW\t\t\t\trtl8821A_power_on_flow\n#define Rtl8821A_NIC_RF_OFF_FLOW\t\t\t\trtl8821A_radio_off_flow\n#define Rtl8821A_NIC_DISABLE_FLOW\t\t\t\trtl8821A_card_disable_flow\n#define Rtl8821A_NIC_ENABLE_FLOW\t\t\t\trtl8821A_card_enable_flow\n#define Rtl8821A_NIC_SUSPEND_FLOW\t\t\t\trtl8821A_suspend_flow\n#define Rtl8821A_NIC_RESUME_FLOW\t\t\t\trtl8821A_resume_flow\n#define Rtl8821A_NIC_PDN_FLOW\t\t\t\t\trtl8821A_hwpdn_flow\n#define Rtl8821A_NIC_LPS_ENTER_FLOW\t\t\trtl8821A_enter_lps_flow\n#define Rtl8821A_NIC_LPS_LEAVE_FLOW\t\t\trtl8821A_leave_lps_flow\n\n\n#if 1 /* download firmware related data structure */\n#define FW_SIZE_8812\t\t\t0x8000 /* Compatible with RTL8723 Maximal RAM code size 24K.   modified to 32k, TO compatible with 92d maximal fw size 32k */\n#define FW_START_ADDRESS\t\t0x1000\n#define FW_END_ADDRESS\t\t0x5FFF\n\n\n\ntypedef struct _RT_FIRMWARE_8812 {\n\tFIRMWARE_SOURCE\teFWSource;\n#ifdef CONFIG_EMBEDDED_FWIMG\n\tu8\t\t\t*szFwBuffer;\n#else\n\tu8\t\t\tszFwBuffer[FW_SIZE_8812];\n#endif\n\tu32\t\t\tulFwLength;\n} RT_FIRMWARE_8812, *PRT_FIRMWARE_8812;\n\n/*\n * This structure must be cared byte-ordering\n *\n * Added by tynli. 2009.12.04. */\n#define IS_FW_HEADER_EXIST_8812(_pFwHdr)\t((GET_FIRMWARE_HDR_SIGNATURE_8812(_pFwHdr) & 0xFFF0) == 0x9500)\n\n#define IS_FW_HEADER_EXIST_8821(_pFwHdr)\t((GET_FIRMWARE_HDR_SIGNATURE_8812(_pFwHdr) & 0xFFF0) == 0x2100)\n/* *****************************************************\n *\t\t\t\t\tFirmware Header(8-byte alinment required)\n * *****************************************************\n * --- LONG WORD 0 ---- */\n#define GET_FIRMWARE_HDR_SIGNATURE_8812(__FwHdr)\t\tLE_BITS_TO_4BYTE(__FwHdr, 0, 16) /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */\n#define GET_FIRMWARE_HDR_CATEGORY_8812(__FwHdr)\t\tLE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */\n#define GET_FIRMWARE_HDR_FUNCTION_8812(__FwHdr)\t\tLE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */\n#define GET_FIRMWARE_HDR_VERSION_8812(__FwHdr)\t\tLE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */\n#define GET_FIRMWARE_HDR_SUB_VER_8812(__FwHdr)\t\tLE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */\n#define GET_FIRMWARE_HDR_RSVD1_8812(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+4, 24, 8)\n\n/* --- LONG WORD 1 ---- */\n#define GET_FIRMWARE_HDR_MONTH_8812(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+8, 0, 8) /* Release time Month field */\n#define GET_FIRMWARE_HDR_DATE_8812(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+8, 8, 8) /* Release time Date field */\n#define GET_FIRMWARE_HDR_HOUR_8812(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+8, 16, 8)/* Release time Hour field */\n#define GET_FIRMWARE_HDR_MINUTE_8812(__FwHdr)\t\tLE_BITS_TO_4BYTE(__FwHdr+8, 24, 8)/* Release time Minute field */\n#define GET_FIRMWARE_HDR_ROMCODE_SIZE_8812(__FwHdr)\tLE_BITS_TO_4BYTE(__FwHdr+12, 0, 16)/* The size of RAM code */\n#define GET_FIRMWARE_HDR_RSVD2_8812(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+12, 16, 16)\n\n/* --- LONG WORD 2 ---- */\n#define GET_FIRMWARE_HDR_SVN_IDX_8812(__FwHdr)\t\tLE_BITS_TO_4BYTE(__FwHdr+16, 0, 32)/* The SVN entry index */\n#define GET_FIRMWARE_HDR_RSVD3_8812(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+20, 0, 32)\n\n/* --- LONG WORD 3 ---- */\n#define GET_FIRMWARE_HDR_RSVD4_8812(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+24, 0, 32)\n#define GET_FIRMWARE_HDR_RSVD5_8812(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+28, 0, 32)\n\n#endif /* download firmware related data structure */\n\n\n#define DRIVER_EARLY_INT_TIME_8812\t\t0x05\n#define BCN_DMA_ATIME_INT_TIME_8812\t\t0x02\n\n/* for 8812\n * TX 128K, RX 16K, Page size 512B for TX, 128B for RX */\n#define MAX_RX_DMA_BUFFER_SIZE_8812\t0x3E80 /* RX 16K */\n\n#ifdef CONFIG_WOWLAN\n\t#define RESV_FMWF\t(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/\n#else\n\t#define RESV_FMWF\t0\n#endif\n\n#ifdef CONFIG_FW_C2H_DEBUG\n\t#define RX_DMA_RESERVED_SIZE_8812\t0x100\t/* 256B, reserved for c2h debug message */\n#else\n\t#define RX_DMA_RESERVED_SIZE_8812\t0x0\t/* 0B */\n#endif\n#define RX_DMA_BOUNDARY_8812\t\t(MAX_RX_DMA_BUFFER_SIZE_8812 - RX_DMA_RESERVED_SIZE_8812 - 1)\n\n#define PAGE_SIZE_TX_8812A PAGE_SIZE_512\n\n/* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8812A\n * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/\n#define BCNQ_PAGE_NUM_8812\t\t(MAX_BEACON_LEN / PAGE_SIZE_TX_8812A + 6) /*0x07*/\n\n/* For WoWLan , more reserved page\n * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, AOAC rpt: 1,PNO: 6\n * NS offload: 1 NDP info: 1\n */\n#ifdef CONFIG_WOWLAN\n\t#define WOWLAN_PAGE_NUM_8812\t0x08\n#else\n\t#define WOWLAN_PAGE_NUM_8812\t0x00\n#endif\n\n\n#ifdef CONFIG_BEAMFORMER_FW_NDPA\n\t#define FW_NDPA_PAGE_NUM\t0x02\n#else\n\t#define FW_NDPA_PAGE_NUM\t0x00\n#endif\n\n#ifdef DBG_FW_DEBUG_MSG_PKT\n\t#define FW_DBG_MSG_PKT_PAGE_NUM_8812\t0x01\n#else\n\t#define FW_DBG_MSG_PKT_PAGE_NUM_8812\t0x00\n#endif /*DBG_FW_DEBUG_MSG_PKT*/\n\n#define TX_TOTAL_PAGE_NUMBER_8812\t(0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812 - FW_NDPA_PAGE_NUM - FW_DBG_MSG_PKT_PAGE_NUM_8812)\n#define TX_PAGE_BOUNDARY_8812\t\t\t(TX_TOTAL_PAGE_NUMBER_8812 + 1)\n\n#define TX_PAGE_BOUNDARY_WOWLAN_8812\t\t(0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812 + 1)\n\n#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8812\tTX_TOTAL_PAGE_NUMBER_8812\n#define WMM_NORMAL_TX_PAGE_BOUNDARY_8812\t\t(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8812 + 1)\n\n/* For Normal Chip Setting\n * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8812 */\n#define NORMAL_PAGE_NUM_LPQ_8812\t\t\t\t0x10\n#define NORMAL_PAGE_NUM_HPQ_8812\t\t\t0x10\n#define NORMAL_PAGE_NUM_NPQ_8812\t\t\t0x00\n\n#define WMM_NORMAL_PAGE_NUM_HPQ_8812\t\t0x30\n#define WMM_NORMAL_PAGE_NUM_LPQ_8812\t\t0x20\n#define WMM_NORMAL_PAGE_NUM_NPQ_8812\t\t0x20\n\n\n/* for 8821A\n * TX 64K, RX 16K, Page size 256B for TX, 128B for RX */\n#define PAGE_SIZE_TX_8821A\t\t\t\t\t256\n#define PAGE_SIZE_RX_8821A\t\t\t\t\t128\n\n#define MAX_RX_DMA_BUFFER_SIZE_8821\t\t\t0x3E80 /* RX 16K */\n\n#ifdef CONFIG_FW_C2H_DEBUG\n\t#define RX_DMA_RESERVED_SIZE_8821\t0x100\t/* 256B, reserved for c2h debug message */\n#else\n\t#define RX_DMA_RESERVED_SIZE_8821\t0x0\t/* 0B */\n#endif\n#define RX_DMA_BOUNDARY_8821\t\t(MAX_RX_DMA_BUFFER_SIZE_8821 - RX_DMA_RESERVED_SIZE_8821 - 1)\n\n/* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8821A\n * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/\n\n#define BCNQ_PAGE_NUM_8821\t\t(MAX_BEACON_LEN / PAGE_SIZE_TX_8821A + 6) /*0x08*/\n\n\n/* For WoWLan , more reserved page\n * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, PNO: 6 */\n#ifdef CONFIG_WOWLAN\n\t#define WOWLAN_PAGE_NUM_8821\t0x06\n#else\n\t#define WOWLAN_PAGE_NUM_8821\t0x00\n#endif\n\n#define TX_TOTAL_PAGE_NUMBER_8821\t(0xFF - BCNQ_PAGE_NUM_8821 - WOWLAN_PAGE_NUM_8821)\n#define TX_PAGE_BOUNDARY_8821\t\t\t\t(TX_TOTAL_PAGE_NUMBER_8821 + 1)\n/* #define TX_PAGE_BOUNDARY_WOWLAN_8821\t\t0xE0 */\n\n#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8821\tTX_TOTAL_PAGE_NUMBER_8821\n#define WMM_NORMAL_TX_PAGE_BOUNDARY_8821\t\t(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8821 + 1)\n\n\n/* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */\n#define NORMAL_PAGE_NUM_LPQ_8821\t\t\t0x08/* 0x10 */\n#define NORMAL_PAGE_NUM_HPQ_8821\t\t0x08/* 0x10 */\n#define NORMAL_PAGE_NUM_NPQ_8821\t\t0x00\n#define NORMAL_PAGE_NUM_EPQ_8821\t\t\t0x04\n\n#define WMM_NORMAL_PAGE_NUM_HPQ_8821\t\t0x30\n#define WMM_NORMAL_PAGE_NUM_LPQ_8821\t\t0x20\n#define WMM_NORMAL_PAGE_NUM_NPQ_8821\t\t0x20\n#define WMM_NORMAL_PAGE_NUM_EPQ_8821\t\t0x00\n\n#define MCC_NORMAL_PAGE_NUM_HPQ_8821\t\t0x10\n#define MCC_NORMAL_PAGE_NUM_LPQ_8821\t\t0x10\n#define MCC_NORMAL_PAGE_NUM_NPQ_8821\t\t0x10\n\n#define\tEFUSE_HIDDEN_812AU\t\t\t\t\t0\n#define\tEFUSE_HIDDEN_812AU_VS\t\t\t\t1\n#define\tEFUSE_HIDDEN_812AU_VL\t\t\t\t2\n#define\tEFUSE_HIDDEN_812AU_VN\t\t\t\t3\n\n#if 0\n#define EFUSE_REAL_CONTENT_LEN_JAGUAR\t\t1024\n#define HWSET_MAX_SIZE_JAGUAR\t\t\t\t\t1024\n#else\n#define EFUSE_REAL_CONTENT_LEN_JAGUAR\t\t512\n#define HWSET_MAX_SIZE_JAGUAR\t\t\t\t\t512\n#endif\n\n#define EFUSE_MAX_BANK_8812A\t\t\t\t\t2\n#define EFUSE_MAP_LEN_JAGUAR\t\t\t\t\t512\n#define EFUSE_MAX_SECTION_JAGUAR\t\t\t\t64\n#define EFUSE_MAX_WORD_UNIT_JAGUAR\t\t\t4\n#define EFUSE_IC_ID_OFFSET_JAGUAR\t\t\t\t506\t/* For some inferiority IC purpose. added by Roger, 2009.09.02. */\n#define AVAILABLE_EFUSE_ADDR_8812(addr)\t(addr < EFUSE_REAL_CONTENT_LEN_JAGUAR)\n/* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section\n * 9bytes + 1byt + 5bytes and pre 1byte.\n * For worst case:\n * | 2byte|----8bytes----|1byte|--7bytes--|  */ /* 92D */\n#define EFUSE_OOB_PROTECT_BYTES_JAGUAR\t\t18\t/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */\n#define EFUSE_PROTECT_BYTES_BANK_JAGUAR\t\t16\n\n#define INCLUDE_MULTI_FUNC_BT(_Adapter)\t(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)\n#define INCLUDE_MULTI_FUNC_GPS(_Adapter)\t(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)\n\n/* #define IS_MULTI_FUNC_CHIP(_Adapter)\t(((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */\n\n/* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */\n#define HAL_EFUSE_MEMORY\n\n/* ********************************************************\n *\t\t\tEFUSE for BT definition\n * ******************************************************** */\n#define BANK_NUM\t\t\t2\n#define EFUSE_BT_REAL_BANK_CONTENT_LEN\t512\n#define EFUSE_BT_REAL_CONTENT_LEN\t\\\n\t(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)\n#define EFUSE_BT_MAP_LEN\t\t1024\t/* 1k bytes */\n#define EFUSE_BT_MAX_SECTION\t\t(EFUSE_BT_MAP_LEN / 8)\n#define EFUSE_PROTECT_BYTES_BANK\t16\n\n#define AVAILABLE_EFUSE_ADDR(addr)\t(addr < EFUSE_BT_REAL_CONTENT_LEN)\n\n#ifdef CONFIG_FILE_FWIMG\nextern char *rtw_fw_file_path;\n#ifdef CONFIG_WOWLAN\nextern char *rtw_fw_wow_file_path;\n#endif\n#ifdef CONFIG_MP_INCLUDED\nextern char *rtw_fw_mp_bt_file_path;\n#endif\n#endif\n\n\n/* rtl8812_hal_init.c */\nvoid\t_8051Reset8812(PADAPTER padapter);\ns32\tFirmwareDownload8812(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw);\nvoid\tInitializeFirmwareVars8812(PADAPTER padapter);\n\ns32\t_LLTWrite_8812A(PADAPTER Adapter, u32 address, u32 data);\ns32\tInitLLTTable8812A(PADAPTER padapter, u8 txpktbuf_bndy);\nvoid InitRDGSetting8812A(PADAPTER padapter);\n\nvoid CheckAutoloadState8812A(PADAPTER padapter);\n\n/* EFuse */\nu8\tGetEEPROMSize8812A(PADAPTER padapter);\nvoid InitPGData8812A(PADAPTER padapter);\nvoid\tHal_EfuseParseIDCode8812A(PADAPTER padapter, u8 *hwinfo);\nvoid\tHal_ReadPROMVersion8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid\tHal_ReadTxPowerInfo8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN\tAutoLoadFail);\nvoid\tHal_ReadBoardType8812A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid\tHal_ReadThermalMeter_8812A(PADAPTER\tAdapter, u8 *PROMContent, BOOLEAN\tAutoloadFail);\nvoid\tHal_ReadChannelPlan8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid\tHal_EfuseParseXtal_8812A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid\tHal_ReadAntennaDiversity8812A(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);\nvoid\tHal_ReadAmplifierType_8812A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);\nvoid\tHal_ReadPAType_8821A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);\nvoid\tHal_ReadRFEType_8812A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);\nvoid\tHal_EfuseParseBTCoexistInfo8812A(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid\thal_ReadUsbType_8812AU(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);\n#ifdef CONFIG_MP_INCLUDED\nint\tFirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);\n#endif\nvoid\tHal_ReadRemoteWakeup_8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\n\nBOOLEAN HalDetectPwrDownMode8812(PADAPTER Adapter);\nvoid Hal_EfuseParseKFreeData_8821A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);\n\n#ifdef CONFIG_WOWLAN\nvoid Hal_DetectWoWMode(PADAPTER pAdapter);\n#endif /* CONFIG_WOWLAN */\n\nvoid _InitBeaconParameters_8812A(PADAPTER padapter);\nvoid SetBeaconRelatedRegisters8812A(PADAPTER padapter);\n\nvoid ReadRFType8812A(PADAPTER padapter);\nvoid InitDefaultValue8821A(PADAPTER padapter);\n\nu8 SetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval);\nvoid GetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval);\nu8 SetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);\nu8 GetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);\nvoid rtl8812_set_hal_ops(struct hal_ops *pHalFunc);\nvoid init_hal_spec_8812a(_adapter *adapter);\nvoid init_hal_spec_8821a(_adapter *adapter);\n\nu32 upload_txpktbuf_8812au(_adapter *adapter, u8 *buf, u32 buflen);\n\nvoid rtl8812_start_thread(PADAPTER padapter);\nvoid rtl8812_stop_thread(PADAPTER padapter);\n\n#ifdef CONFIG_PCI_HCI\nBOOLEAN\tInterruptRecognized8812AE(PADAPTER Adapter);\nvoid\tUpdateInterruptMask8812AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);\nvoid\tInitTRXDescHwAddress8812AE(PADAPTER Adapter);\n#endif\n\n#ifdef CONFIG_BT_COEXIST\nvoid rtl8812a_combo_card_WifiOnlyHwInit(PADAPTER Adapter);\n#endif\n\nvoid\nHal_PatchwithJaguar_8812(\n\t\tPADAPTER\t\t\t\tAdapter,\n\t\tRT_MEDIA_STATUS\t\tMediaStatus\n);\n\n#endif /* __RTL8188E_HAL_H__ */\n"
  },
  {
    "path": "include/rtl8812a_led.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8812A_LED_H__\n#define __RTL8812A_LED_H__\n#ifdef CONFIG_RTW_LED\n#ifdef CONFIG_RTW_SW_LED\n/* ********************************************************************************\n * Interface to manipulate LED objects.\n * ******************************************************************************** */\n#ifdef CONFIG_USB_HCI\nvoid rtl8812au_InitSwLeds(PADAPTER padapter);\nvoid rtl8812au_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_PCI_HCI\nvoid rtl8812ae_InitSwLeds(PADAPTER padapter);\nvoid rtl8812ae_DeInitSwLeds(PADAPTER padapter);\n#endif\n#ifdef CONFIG_SDIO_HCI\nvoid rtl8821as_InitSwLeds(PADAPTER padapter);\nvoid rtl8821as_DeInitSwLeds(PADAPTER padapter);\n#endif\n#endif/*CONFIG_RTW_SW_LED*/\n#endif/*#ifdef CONFIG_RTW_LED*/\n\n#ifdef CONFIG_SDIO_HCI\nvoid rtl8821as_init_led_circuit(PADAPTER adapter);\n#endif\n\n#endif /*__RTL8812A_LED_H__*/\n"
  },
  {
    "path": "include/rtl8812a_recv.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8812A_RECV_H__\n#define __RTL8812A_RECV_H__\n\n#if defined(CONFIG_USB_HCI)\n\n\t#ifndef MAX_RECVBUF_SZ\n\t\t#ifndef CONFIG_MINIMAL_MEMORY_USAGE\n\t\t\t#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER\n\t\t\t\t#define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/\n\t\t\t#else\n\t\t\t\t#define MAX_RECVBUF_SZ (32768)  /*32k*/\n\t\t\t#endif\n\t\t\t/* #define MAX_RECVBUF_SZ (24576) */ /* 24k */\n\t\t\t/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */\n\t\t\t/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */\n\t\t\t/* #define MAX_RECVBUF_SZ (15360) */ /* 15k < 16k */\n\t\t\t/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */\n\t\t\t#ifdef CONFIG_PLATFORM_NOVATEK_NT72668\n\t\t\t\t#undef MAX_RECVBUF_SZ\n\t\t\t\t#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */\n\t\t\t#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */\n\t\t#else\n\t\t\t#define MAX_RECVBUF_SZ (4000) /* about 4K */\n\t\t#endif\n\t#endif /* !MAX_RECVBUF_SZ */\n\n#elif defined(CONFIG_PCI_HCI)\n\t/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */\n\t/*\t#define MAX_RECVBUF_SZ (9100) */\n\t/* #else */\n\t#define MAX_RECVBUF_SZ (4000) /* about 4K\n\t* #endif */\n\n\n#elif defined(CONFIG_SDIO_HCI)\n\n\t#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8821 + 1)\n\n#endif\n\n\n/* Rx smooth factor */\n#define Rx_Smooth_Factor (20)\n\n/* DWORD 0 */\n#define SET_RX_STATUS_DESC_PKT_LEN_8812(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)\n#define SET_RX_STATUS_DESC_EOR_8812(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)\n#define SET_RX_STATUS_DESC_OWN_8812(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)\n\n#define GET_RX_STATUS_DESC_PKT_LEN_8812(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)\n#define GET_RX_STATUS_DESC_CRC32_8812(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)\n#define GET_RX_STATUS_DESC_ICV_8812(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)\n#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8812(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)\n#define GET_RX_STATUS_DESC_SECURITY_8812(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)\n#define GET_RX_STATUS_DESC_QOS_8812(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)\n#define GET_RX_STATUS_DESC_SHIFT_8812(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)\n#define GET_RX_STATUS_DESC_PHY_STATUS_8812(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)\n#define GET_RX_STATUS_DESC_SWDEC_8812(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)\n#define GET_RX_STATUS_DESC_LAST_SEG_8812(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)\n#define GET_RX_STATUS_DESC_FIRST_SEG_8812(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)\n#define GET_RX_STATUS_DESC_EOR_8812(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)\n#define GET_RX_STATUS_DESC_OWN_8812(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)\n\n/* DWORD 1 */\n#define GET_RX_STATUS_DESC_MACID_8812(__pRxDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)\n#define GET_RX_STATUS_DESC_TID_8812(__pRxDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)\n#define GET_RX_STATUS_DESC_AMSDU_8812(__pRxDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)\n#define GET_RX_STATUS_DESC_RXID_MATCH_8812(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)\n#define GET_RX_STATUS_DESC_PAGGR_8812(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)\n#define GET_RX_STATUS_DESC_A1_FIT_8812(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)\n#define GET_RX_STATUS_DESC_CHKERR_8812(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)\n#define GET_RX_STATUS_DESC_IPVER_8812(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)\n#define GET_RX_STATUS_DESC_IS_TCPUDP__8812(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)\n#define GET_RX_STATUS_DESC_CHK_VLD_8812(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)\n#define GET_RX_STATUS_DESC_PAM_8812(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)\n#define GET_RX_STATUS_DESC_PWR_8812(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)\n#define GET_RX_STATUS_DESC_MORE_DATA_8812(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)\n#define GET_RX_STATUS_DESC_MORE_FRAG_8812(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)\n#define GET_RX_STATUS_DESC_TYPE_8812(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)\n#define GET_RX_STATUS_DESC_MC_8812(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)\n#define GET_RX_STATUS_DESC_BC_8812(__pRxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)\n\n/* DWORD 2 */\n#define GET_RX_STATUS_DESC_SEQ_8812(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)\n#define GET_RX_STATUS_DESC_FRAG_8812(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)\n#define GET_RX_STATUS_DESC_RX_IS_QOS_8812(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)\n#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8812(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)\n#define GET_RX_STATUS_DESC_RPT_SEL_8812(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)\n\n/* DWORD 3 */\n#define GET_RX_STATUS_DESC_RX_RATE_8812(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)\n#define GET_RX_STATUS_DESC_HTC_8812(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)\n#define GET_RX_STATUS_DESC_EOSP_8812(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)\n#define GET_RX_STATUS_DESC_BSSID_FIT_8812(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)\n#ifdef CONFIG_USB_RX_AGGREGATION\n#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8812(__pRxStatusDesc)\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)\n#endif\n#define GET_RX_STATUS_DESC_PATTERN_MATCH_8812(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)\n#define GET_RX_STATUS_DESC_UNICAST_MATCH_8812(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)\n#define GET_RX_STATUS_DESC_MAGIC_MATCH_8812(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)\n\n/* DWORD 6 */\n#define GET_RX_STATUS_DESC_SPLCP_8812(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)\n#define GET_RX_STATUS_DESC_LDPC_8812(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)\n#define GET_RX_STATUS_DESC_STBC_8812(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)\n#define GET_RX_STATUS_DESC_BW_8812(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)\n\n/* DWORD 5 */\n#define GET_RX_STATUS_DESC_TSFL_8812(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)\n\n#define GET_RX_STATUS_DESC_BUFF_ADDR_8812(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)\n#define GET_RX_STATUS_DESC_BUFF_ADDR64_8812(__pRxDesc)\t\tLE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)\n\n#define SET_RX_STATUS_DESC_BUFF_ADDR_8812(__pRxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)\n\n\n#ifdef CONFIG_SDIO_HCI\ns32 InitRecvPriv8821AS(PADAPTER padapter);\nvoid FreeRecvPriv8821AS(PADAPTER padapter);\n#endif /* CONFIG_SDIO_HCI */\n\n#ifdef CONFIG_USB_HCI\nvoid rtl8812au_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);\ns32 rtl8812au_init_recv_priv(PADAPTER padapter);\nvoid rtl8812au_free_recv_priv(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_PCI_HCI\ns32 rtl8812ae_init_recv_priv(PADAPTER padapter);\nvoid rtl8812ae_free_recv_priv(PADAPTER padapter);\n#endif\n\nvoid rtl8812_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);\n\n#endif /* __RTL8812A_RECV_H__ */\n"
  },
  {
    "path": "include/rtl8812a_rf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8812A_RF_H__\n#define __RTL8812A_RF_H__\n\nvoid\nPHY_RF6052SetBandwidth8812(\n\t\tPADAPTER\t\t\t\tAdapter,\n\t\tenum channel_width\t\tBandwidth);\n\n\nint\nPHY_RF6052_Config_8812(\n\t\tPADAPTER\tAdapter);\n\n#endif/* __RTL8188E_RF_H__ */\n"
  },
  {
    "path": "include/rtl8812a_spec.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8812A_SPEC_H__\n#define __RTL8812A_SPEC_H__\n\n#include <drv_conf.h>\n\n\n/* ************************************************************\n* 8812 Regsiter offset definition\n* ************************************************************ */\n\n/* ************************************************************\n*\n* ************************************************************ */\n\n/* -----------------------------------------------------\n*\n*\t0x0000h ~ 0x00FFh\tSystem Configuration\n*\n* ----------------------------------------------------- */\n#define REG_SYS_CLKR_8812A\t\t\t\t0x0008\n#define REG_AFE_PLL_CTRL_8812A\t\t0x0028\n#define REG_HSIMR_8812\t\t\t\t\t0x0058\n#define REG_HSISR_8812\t\t\t\t\t0x005c\n#define REG_GPIO_EXT_CTRL\t\t\t\t0x0060\n#define REG_GPIO_STATUS_8812\t\t\t0x006C\n#define REG_SDIO_CTRL_8812\t\t\t\t0x0070\n#define REG_OPT_CTRL_8812\t\t\t\t0x0074\n#define REG_RF_B_CTRL_8812\t\t\t\t0x0076\n#define REG_FW_DRV_MSG_8812\t\t\t0x0088\n#define REG_HMEBOX_E2_E3_8812\t\t\t0x008C\n#define REG_HIMR0_8812\t\t\t\t\t0x00B0\n#define REG_HISR0_8812\t\t\t\t\t0x00B4\n#define REG_HIMR1_8812\t\t\t\t\t0x00B8\n#define REG_HISR1_8812\t\t\t\t\t0x00BC\n#define REG_EFUSE_BURN_GNT_8812\t\t0x00CF\n#define REG_SYS_CFG1_8812\t\t\t\t0x00FC\n\n/* -----------------------------------------------------\n*\n*\t0x0100h ~ 0x01FFh\tMACTOP General Configuration\n*\n* ----------------------------------------------------- */\n#define REG_CR_8812A\t\t\t\t\t0x100\n#define REG_PKTBUF_DBG_ADDR\t\t\t(REG_PKTBUF_DBG_CTRL)\n#define REG_RXPKTBUF_DBG\t\t\t\t(REG_PKTBUF_DBG_CTRL+2)\n#define REG_TXPKTBUF_DBG\t\t\t\t(REG_PKTBUF_DBG_CTRL+3)\n#define REG_WOWLAN_WAKE_REASON\t\t\tREG_MCUTST_WOWLAN\n\n#define REG_RSVD3_8812\t\t\t\t\t0x0168\n#define REG_C2HEVT_CMD_SEQ_88XX\t\t0x01A1\n#define REG_C2hEVT_CMD_CONTENT_88XX\t0x01A2\n#define REG_C2HEVT_CMD_LEN_88XX\t\t0x01AE\n\n#define REG_HMEBOX_EXT0_8812\t\t\t0x01F0\n#define REG_HMEBOX_EXT1_8812\t\t\t0x01F4\n#define REG_HMEBOX_EXT2_8812\t\t\t0x01F8\n#define REG_HMEBOX_EXT3_8812\t\t\t0x01FC\n\n/* -----------------------------------------------------\n*\n*\t0x0200h ~ 0x027Fh\tTXDMA Configuration\n*\n* ----------------------------------------------------- */\n#define REG_DWBCN0_CTRL_8812\t\t\t\tREG_TDECTRL\n#define REG_DWBCN1_CTRL_8812\t\t\t\t0x0228\n\n/* -----------------------------------------------------\n*\n*\t0x0280h ~ 0x02FFh\tRXDMA Configuration\n*\n* ----------------------------------------------------- */\n#define REG_TDECTRL_8812A\t\t\t\t0x0208\n#define REG_RXDMA_CONTROL_8812A\t\t0x0286\t\t/*Control the RX DMA.*/\n#define REG_RXDMA_PRO_8812\t\t\t0x0290\n#define REG_EARLY_MODE_CONTROL_8812\t0x02BC\n#define REG_RSVD5_8812\t\t\t\t\t0x02F0\n#define REG_RSVD6_8812\t\t\t\t\t0x02F4\n#define REG_RSVD7_8812\t\t\t\t\t0x02F8\n#define REG_RSVD8_8812\t\t\t\t\t0x02FC\n\n\n/* -----------------------------------------------------\n*\n*\t0x0300h ~ 0x03FFh\tPCIe\n*\n* ----------------------------------------------------- */\n#define\tREG_PCIE_CTRL_REG_8812A\t\t\t0x0300\n#define\tREG_DBI_WDATA_8812\t\t\t0x0348\t/* DBI Write Data */\n#define\tREG_DBI_RDATA_8812\t\t\t0x034C\t/* DBI Read Data */\n#define\tREG_DBI_ADDR_8812\t\t\t0x0350\t/* DBI Address */\n#define\tREG_DBI_FLAG_8812\t\t\t0x0352\t/* DBI Read/Write Flag */\n#define\tREG_MDIO_WDATA_8812\t\t\t0x0354\t/* MDIO for Write PCIE PHY */\n#define\tREG_MDIO_RDATA_8812\t\t\t0x0356\t/* MDIO for Reads PCIE PHY */\n#define\tREG_MDIO_CTL_8812\t\t\t0x0358\t/* MDIO for Control */\n#define REG_PCIE_HRPWM_8812A\t\t\t0x0361  /* PCIe RPWM */\n#define REG_PCIE_HCPWM_8812A\t\t\t0x0363  /* PCIe CPWM */\n\n#define\tREG_PCIE_MULTIFET_CTRL_8812\t0x036A\t/* PCIE Multi-Fethc Control */\n\n/* -----------------------------------------------------\n*\n*\t0x0400h ~ 0x047Fh\tProtocol Configuration\n*\n* ----------------------------------------------------- */\n#define REG_TXPKT_EMPTY_8812A\t\t\t0x041A\n#define REG_FWHW_TXQ_CTRL_8812A\t\t0x0420\n#define REG_TXBF_CTRL_8812A\t\t\t0x042C\n#define REG_ARFR0_8812\t\t\t\t\t0x0444\n#define REG_ARFR1_8812\t\t\t\t\t0x044C\n#define REG_CCK_CHECK_8812\t\t\t\t0x0454\n#define REG_AMPDU_MAX_TIME_8812\t\t0x0456\n#define REG_TXPKTBUF_BCNQ_BDNY1_8812\t0x0457\n\n#define REG_AMPDU_MAX_LENGTH_8812\t0x0458\n#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8812\t0x045D\n#define REG_NDPA_OPT_CTRL_8812A\t\t0x045F\n#define REG_DATA_SC_8812\t\t\t\t0x0483\n#ifdef CONFIG_WOWLAN\n#define REG_TXPKTBUF_IV_LOW             0x0484\n#define REG_TXPKTBUF_IV_HIGH            0x0488\n#endif\n#define REG_ARFR2_8812\t\t\t\t\t0x048C\n#define REG_ARFR3_8812\t\t\t\t\t0x0494\n#define REG_TXRPT_START_OFFSET\t\t0x04AC\n#define REG_AMPDU_BURST_MODE_8812\t0x04BC\n#define REG_HT_SINGLE_AMPDU_8812\t\t0x04C7\n#define REG_MACID_PKT_DROP0_8812\t\t0x04D0\n\n/* -----------------------------------------------------\n*\n*\t0x0500h ~ 0x05FFh\tEDCA Configuration\n*\n* ----------------------------------------------------- */\n#define REG_TXPAUSE_8812A\t\t\t\t0x0522\n#define REG_CTWND_8812\t\t\t\t\t0x0572\n#define REG_SECONDARY_CCA_CTRL_8812\t0x0577\n#define REG_SCH_TXCMD_8812A\t\t\t0x05F8\n\n/* -----------------------------------------------------\n*\n*\t0x0600h ~ 0x07FFh\tWMAC Configuration\n*\n* ----------------------------------------------------- */\n#define REG_MAC_CR_8812\t\t\t\t0x0600\n\n#define REG_MAC_TX_SM_STATE_8812\t\t0x06B4\n\n/* Power */\n#define REG_BFMER0_INFO_8812A\t\t\t0x06E4\n#define REG_BFMER1_INFO_8812A\t\t\t0x06EC\n#define REG_CSI_RPT_PARAM_BW20_8812A\t0x06F4\n#define REG_CSI_RPT_PARAM_BW40_8812A\t0x06F8\n#define REG_CSI_RPT_PARAM_BW80_8812A\t0x06FC\n\n/* Hardware Port 2 */\n#define REG_BFMEE_SEL_8812A\t\t\t0x0714\n#define REG_SND_PTCL_CTRL_8812A\t\t0x0718\n\n\n/* -----------------------------------------------------\n*\n*\tRedifine register definition for compatibility\n*\n* ----------------------------------------------------- */\n\n/* TODO: use these definition when using REG_xxx naming rule.\n* NOTE: DO NOT Remove these definition. Use later. */\n#define\tISR_8812\t\t\t\t\t\t\tREG_HISR0_8812\n\n/* ----------------------------------------------------------------------------\n* 8195 IMR/ISR bits\t\t\t\t\t\t(offset 0xB0,  8bits)\n* ---------------------------------------------------------------------------- */\n#define\tIMR_DISABLED_8812\t\t\t\t\t0\n/* IMR DW0(0x00B0-00B3) Bit 0-31 */\n#define\tIMR_TIMER2_8812\t\t\t\t\tBIT31\t\t/* Timeout interrupt 2 */\n#define\tIMR_TIMER1_8812\t\t\t\t\tBIT30\t\t/* Timeout interrupt 1\t */\n#define\tIMR_PSTIMEOUT_8812\t\t\t\tBIT29\t\t/* Power Save Time Out Interrupt */\n#define\tIMR_GTINT4_8812\t\t\t\t\tBIT28\t\t/* When GTIMER4 expires, this bit is set to 1\t */\n#define\tIMR_GTINT3_8812\t\t\t\t\tBIT27\t\t/* When GTIMER3 expires, this bit is set to 1\t */\n#define\tIMR_TXBCN0ERR_8812\t\t\t\tBIT26\t\t/* Transmit Beacon0 Error\t\t\t */\n#define\tIMR_TXBCN0OK_8812\t\t\t\t\tBIT25\t\t/* Transmit Beacon0 OK\t\t\t */\n#define\tIMR_TSF_BIT32_TOGGLE_8812\t\tBIT24\t\t/* TSF Timer BIT32 toggle indication interrupt\t\t\t */\n#define\tIMR_BCNDMAINT0_8812\t\t\t\tBIT20\t\t/* Beacon DMA Interrupt 0\t\t\t */\n#define\tIMR_BCNDERR0_8812\t\t\t\t\tBIT16\t\t/* Beacon Queue DMA OK0\t\t\t */\n#define\tIMR_HSISR_IND_ON_INT_8812\t\tBIT15\t\t/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */\n#define\tIMR_BCNDMAINT_E_8812\t\t\t\tBIT14\t\t/* Beacon DMA Interrupt Extension for Win7\t\t\t */\n#define\tIMR_ATIMEND_8812\t\t\t\t\tBIT12\t\t/* CTWidnow End or ATIM Window End */\n#define\tIMR_C2HCMD_8812\t\t\t\t\tBIT10\t\t/* CPU to Host Command INT Status, Write 1 clear\t */\n#define\tIMR_CPWM2_8812\t\t\t\t\tBIT9\t\t\t/* CPU power Mode exchange INT Status, Write 1 clear\t */\n#define\tIMR_CPWM_8812\t\t\t\t\t\tBIT8\t\t\t/* CPU power Mode exchange INT Status, Write 1 clear\t */\n#define\tIMR_HIGHDOK_8812\t\t\t\t\tBIT7\t\t\t/* High Queue DMA OK\t */\n#define\tIMR_MGNTDOK_8812\t\t\t\t\tBIT6\t\t\t/* Management Queue DMA OK\t */\n#define\tIMR_BKDOK_8812\t\t\t\t\tBIT5\t\t\t/* AC_BK DMA OK\t\t */\n#define\tIMR_BEDOK_8812\t\t\t\t\tBIT4\t\t\t/* AC_BE DMA OK\t */\n#define\tIMR_VIDOK_8812\t\t\t\t\tBIT3\t\t\t/* AC_VI DMA OK\t\t */\n#define\tIMR_VODOK_8812\t\t\t\t\tBIT2\t\t\t/* AC_VO DMA OK\t */\n#define\tIMR_RDU_8812\t\t\t\t\t\tBIT1\t\t\t/* Rx Descriptor Unavailable\t */\n#define\tIMR_ROK_8812\t\t\t\t\t\tBIT0\t\t\t/* Receive DMA OK */\n\n/* IMR DW1(0x00B4-00B7) Bit 0-31 */\n#define\tIMR_BCNDMAINT7_8812\t\t\t\tBIT27\t\t/* Beacon DMA Interrupt 7 */\n#define\tIMR_BCNDMAINT6_8812\t\t\t\tBIT26\t\t/* Beacon DMA Interrupt 6 */\n#define\tIMR_BCNDMAINT5_8812\t\t\t\tBIT25\t\t/* Beacon DMA Interrupt 5 */\n#define\tIMR_BCNDMAINT4_8812\t\t\t\tBIT24\t\t/* Beacon DMA Interrupt 4 */\n#define\tIMR_BCNDMAINT3_8812\t\t\t\tBIT23\t\t/* Beacon DMA Interrupt 3 */\n#define\tIMR_BCNDMAINT2_8812\t\t\t\tBIT22\t\t/* Beacon DMA Interrupt 2 */\n#define\tIMR_BCNDMAINT1_8812\t\t\t\tBIT21\t\t/* Beacon DMA Interrupt 1 */\n#define\tIMR_BCNDOK7_8812\t\t\t\t\tBIT20\t\t/* Beacon Queue DMA OK Interrup 7 */\n#define\tIMR_BCNDOK6_8812\t\t\t\t\tBIT19\t\t/* Beacon Queue DMA OK Interrup 6 */\n#define\tIMR_BCNDOK5_8812\t\t\t\t\tBIT18\t\t/* Beacon Queue DMA OK Interrup 5 */\n#define\tIMR_BCNDOK4_8812\t\t\t\t\tBIT17\t\t/* Beacon Queue DMA OK Interrup 4 */\n#define\tIMR_BCNDOK3_8812\t\t\t\t\tBIT16\t\t/* Beacon Queue DMA OK Interrup 3 */\n#define\tIMR_BCNDOK2_8812\t\t\t\t\tBIT15\t\t/* Beacon Queue DMA OK Interrup 2 */\n#define\tIMR_BCNDOK1_8812\t\t\t\t\tBIT14\t\t/* Beacon Queue DMA OK Interrup 1 */\n#define\tIMR_ATIMEND_E_8812\t\t\t\tBIT13\t\t/* ATIM Window End Extension for Win7 */\n#define\tIMR_TXERR_8812\t\t\t\t\tBIT11\t\t/* Tx Error Flag Interrupt Status, write 1 clear. */\n#define\tIMR_RXERR_8812\t\t\t\t\tBIT10\t\t/* Rx Error Flag INT Status, Write 1 clear */\n#define\tIMR_TXFOVW_8812\t\t\t\t\tBIT9\t\t\t/* Transmit FIFO Overflow */\n#define\tIMR_RXFOVW_8812\t\t\t\t\tBIT8\t\t\t/* Receive FIFO Overflow */\n\n\n#ifdef CONFIG_PCI_HCI\n/* #define IMR_RX_MASK\t\t(IMR_ROK_8812|IMR_RDU_8812|IMR_RXFOVW_8812) */\n#define IMR_TX_MASK\t\t\t(IMR_VODOK_8812 | IMR_VIDOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812 | IMR_MGNTDOK_8812 | IMR_HIGHDOK_8812)\n\n#define RT_BCN_INT_MASKS\t(IMR_BCNDMAINT0_8812 | IMR_TXBCN0OK_8812 | IMR_TXBCN0ERR_8812 | IMR_BCNDERR0_8812)\n\n#define RT_AC_INT_MASKS\t(IMR_VIDOK_8812 | IMR_VODOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812)\n#endif\n\n\n/* ****************************************************************************\n* Regsiter Bit and Content definition\n* **************************************************************************** */\n\n/* 2 ACMHWCTRL 0x05C0 */\n#define\tAcmHw_HwEn_8812\t\t\t\tBIT(0)\n#define\tAcmHw_VoqEn_8812\t\t\t\tBIT(1)\n#define\tAcmHw_ViqEn_8812\t\t\t\tBIT(2)\n#define\tAcmHw_BeqEn_8812\t\t\t\tBIT(3)\n#define\tAcmHw_VoqStatus_8812\t\t\tBIT(5)\n#define\tAcmHw_ViqStatus_8812\t\t\tBIT(6)\n#define\tAcmHw_BeqStatus_8812\t\t\tBIT(7)\n\n#endif /* __RTL8812A_SPEC_H__ */\n\n#ifdef CONFIG_RTL8821A\n#include \"rtl8821a_spec.h\"\n#endif /* CONFIG_RTL8821A */\n"
  },
  {
    "path": "include/rtl8812a_sreset.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL88812A_SRESET_H_\n#define _RTL8812A_SRESET_H_\n\n#include <rtw_sreset.h>\n\n#ifdef DBG_CONFIG_ERROR_DETECT\nextern void rtl8812_sreset_xmit_status_check(_adapter *padapter);\nextern void rtl8812_sreset_linked_status_check(_adapter *padapter);\n#endif\n#endif\n"
  },
  {
    "path": "include/rtl8812a_xmit.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8812A_XMIT_H__\n#define __RTL8812A_XMIT_H__\n\n\n/* For 88e early mode */\n#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)\n#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)\n#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)\n#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)\n#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)\n#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)\n#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)\n\n/*\n * defined for TX DESC Operation\n *   */\n\n#define MAX_TID (15)\n\n/* OFFSET 0 */\n#define OFFSET_SZ\t0\n#define OFFSET_SHT\t16\n#define BMC\t\t\tBIT(24)\n#define LSG\t\t\tBIT(26)\n#define FSG\t\t\tBIT(27)\n#define OWN\t\tBIT(31)\n\n\n/* OFFSET 4 */\n#define PKT_OFFSET_SZ\t\t0\n#define QSEL_SHT\t\t\t8\n#define RATE_ID_SHT\t\t\t16\n#define NAVUSEHDR\t\t\tBIT(20)\n#define SEC_TYPE_SHT\t\t22\n#define PKT_OFFSET_SHT\t\t26\n\n/* OFFSET 8 */\n#define AGG_EN\t\t\t\tBIT(12)\n#define AGG_BK\t\t\t\tBIT(16)\n#define AMPDU_DENSITY_SHT\t20\n#define ANTSEL_A\t\t\tBIT(24)\n#define ANTSEL_B\t\t\tBIT(25)\n#define TX_ANT_CCK_SHT\t\t26\n#define TX_ANTL_SHT\t\t\t28\n#define TX_ANT_HT_SHT\t\t30\n\n/* OFFSET 12 */\n#define SEQ_SHT\t\t\t\t16\n#define EN_HWSEQ\t\t\tBIT(31)\n\n/* OFFSET 16 */\n#define QOS\t\t\t\t\tBIT(6)\n#define\tHW_SSN\t\t\t\tBIT(7)\n#define USERATE\t\t\t\tBIT(8)\n#define DISDATAFB\t\t\tBIT(10)\n#define CTS_2_SELF\t\t\tBIT(11)\n#define\tRTS_EN\t\t\t\tBIT(12)\n#define\tHW_RTS_EN\t\t\tBIT(13)\n#define DATA_SHORT\t\t\tBIT(24)\n#define PWR_STATUS_SHT\t15\n#define DATA_SC_SHT\t\t20\n#define DATA_BW\t\t\t\tBIT(25)\n\n/* OFFSET 20 */\n#define\tRTY_LMT_EN\t\t\tBIT(17)\n\n/* OFFSET 20 */\n#define SGI\t\t\t\t\tBIT(6)\n#define USB_TXAGG_NUM_SHT\t24\n\ntypedef struct txdescriptor_8812 {\n\t/* Offset 0 */\n\tu32 pktlen:16;\n\tu32 offset:8;\n\tu32 bmc:1;\n\tu32 htc:1;\n\tu32 ls:1;\n\tu32 fs:1;\n\tu32 linip:1;\n\tu32 noacm:1;\n\tu32 gf:1;\n\tu32 own:1;\n\n\t/* Offset 4 */\n\tu32 macid:6;\n\tu32 rsvd0406:2;\n\tu32 qsel:5;\n\tu32 rd_nav_ext:1;\n\tu32 lsig_txop_en:1;\n\tu32 pifs:1;\n\tu32 rate_id:4;\n\tu32 navusehdr:1;\n\tu32 en_desc_id:1;\n\tu32 sectype:2;\n\tu32 rsvd0424:2;\n\tu32 pkt_offset:5;\t/* unit: 8 bytes */\n\tu32 rsvd0431:1;\n\n\t/* Offset 8 */\n\tu32 rts_rc:6;\n\tu32 data_rc:6;\n\tu32 agg_en:1;\n\tu32 rd_en:1;\n\tu32 bar_rty_th:2;\n\tu32 bk:1;\n\tu32 morefrag:1;\n\tu32 raw:1;\n\tu32 ccx:1;\n\tu32 ampdu_density:3;\n\tu32 bt_null:1;\n\tu32 ant_sel_a:1;\n\tu32 ant_sel_b:1;\n\tu32 tx_ant_cck:2;\n\tu32 tx_antl:2;\n\tu32 tx_ant_ht:2;\n\n\t/* Offset 12 */\n\tu32 nextheadpage:8;\n\tu32 tailpage:8;\n\tu32 seq:12;\n\tu32 cpu_handle:1;\n\tu32 tag1:1;\n\tu32 trigger_int:1;\n\tu32 hwseq_en:1;\n\n\t/* Offset 16 */\n\tu32 rtsrate:5;\n\tu32 ap_dcfe:1;\n\tu32 hwseq_sel:2;\n\tu32 userate:1;\n\tu32 disrtsfb:1;\n\tu32 disdatafb:1;\n\tu32 cts2self:1;\n\tu32 rtsen:1;\n\tu32 hw_rts_en:1;\n\tu32 port_id:1;\n\tu32 pwr_status:3;\n\tu32 wait_dcts:1;\n\tu32 cts2ap_en:1;\n\tu32 data_sc:2;\n\tu32 data_stbc:2;\n\tu32 data_short:1;\n\tu32 data_bw:1;\n\tu32 rts_short:1;\n\tu32 rts_bw:1;\n\tu32 rts_sc:2;\n\tu32 vcs_stbc:2;\n\n\t/* Offset 20 */\n\tu32 datarate:6;\n\tu32 sgi:1;\n\tu32 try_rate:1;\n\tu32 data_ratefb_lmt:5;\n\tu32 rts_ratefb_lmt:4;\n\tu32 rty_lmt_en:1;\n\tu32 data_rt_lmt:6;\n\tu32 usb_txagg_num:8;\n\n\t/* Offset 24 */\n\tu32 txagg_a:5;\n\tu32 txagg_b:5;\n\tu32 use_max_len:1;\n\tu32 max_agg_num:5;\n\tu32 mcsg1_max_len:4;\n\tu32 mcsg2_max_len:4;\n\tu32 mcsg3_max_len:4;\n\tu32 mcs7_sgi_max_len:4;\n\n\t/* Offset 28 */\n\tu32 checksum:16;\t/* TxBuffSize(PCIe)/CheckSum(USB) */\n\tu32 mcsg4_max_len:4;\n\tu32 mcsg5_max_len:4;\n\tu32 mcsg6_max_len:4;\n\tu32 mcs15_sgi_max_len:4;\n\n\t/* Offset 32 */\n\tu32 rsvd32;\n\n\t/* Offset 36 */\n\tu32 rsvd36;\n} TXDESC_8812, *PTXDESC_8812;\n\n\n/* Dword 0 */\n#define GET_TX_DESC_OWN_8812(__pTxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pTxDesc, 31, 1)\n#define SET_TX_DESC_PKT_SIZE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)\n#define SET_TX_DESC_OFFSET_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)\n#define SET_TX_DESC_BMC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)\n#define SET_TX_DESC_HTC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)\n#define SET_TX_DESC_LAST_SEG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)\n#define SET_TX_DESC_FIRST_SEG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)\n#define SET_TX_DESC_LINIP_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)\n#define SET_TX_DESC_NO_ACM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)\n#define SET_TX_DESC_GF_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)\n#define SET_TX_DESC_OWN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)\n\n/* Dword 1 */\n#define SET_TX_DESC_MACID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)\n#define SET_TX_DESC_QUEUE_SEL_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)\n#define SET_TX_DESC_RDG_NAV_EXT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)\n#define SET_TX_DESC_LSIG_TXOP_EN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)\n#define SET_TX_DESC_PIFS_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)\n#define SET_TX_DESC_RATE_ID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)\n#define SET_TX_DESC_EN_DESC_ID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)\n#define SET_TX_DESC_SEC_TYPE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)\n#define SET_TX_DESC_PKT_OFFSET_8812(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)\n\n/* Dword 2 */\n#define SET_TX_DESC_PAID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)\n#define SET_TX_DESC_CCA_RTS_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)\n#define SET_TX_DESC_AGG_ENABLE_8812(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)\n#define SET_TX_DESC_RDG_ENABLE_8812(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)\n#define SET_TX_DESC_AGG_BREAK_8812(__pTxDesc, __Value)\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)\n#define SET_TX_DESC_MORE_FRAG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)\n#define SET_TX_DESC_RAW_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)\n#define SET_TX_DESC_SPE_RPT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)\n#define SET_TX_DESC_AMPDU_DENSITY_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)\n#define SET_TX_DESC_BT_INT_8812(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)\n#define SET_TX_DESC_GID_8812(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)\n\n/* Dword 3 */\n#define SET_TX_DESC_WHEADER_LEN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)\n#define SET_TX_DESC_CHK_EN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)\n#define SET_TX_DESC_EARLY_MODE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)\n#define SET_TX_DESC_HWSEQ_SEL_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)\n#define SET_TX_DESC_USE_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)\n#define SET_TX_DESC_DISABLE_RTS_FB_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)\n#define SET_TX_DESC_DISABLE_FB_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)\n#define SET_TX_DESC_CTS2SELF_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)\n#define SET_TX_DESC_RTS_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)\n#define SET_TX_DESC_HW_RTS_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)\n#define SET_TX_DESC_NAV_USE_HDR_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)\n#define SET_TX_DESC_USE_MAX_LEN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)\n#define SET_TX_DESC_MAX_AGG_NUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)\n#define SET_TX_DESC_NDPA_8812(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)\n#define SET_TX_DESC_AMPDU_MAX_TIME_8812(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)\n\n/* Dword 4 */\n#define SET_TX_DESC_TX_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)\n#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)\n#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)\n#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)\n#define SET_TX_DESC_DATA_RETRY_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)\n#define SET_TX_DESC_RTS_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)\n\n/* Dword 5 */\n#define SET_TX_DESC_DATA_SC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)\n#define SET_TX_DESC_DATA_SHORT_8812(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)\n#define SET_TX_DESC_DATA_BW_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)\n#define SET_TX_DESC_DATA_LDPC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)\n#define SET_TX_DESC_DATA_STBC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)\n#define SET_TX_DESC_CTROL_STBC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)\n#define SET_TX_DESC_RTS_SHORT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)\n#define SET_TX_DESC_RTS_SC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)\n#define SET_TX_DESC_TX_ANT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value)\n\n/* Dword 6 */\n#define SET_TX_DESC_SW_DEFINE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)\n#define SET_TX_DESC_ANTSEL_A_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)\n#define SET_TX_DESC_ANTSEL_B_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)\n#define SET_TX_DESC_ANTSEL_C_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)\n#define SET_TX_DESC_ANTSEL_D_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)\n#define SET_TX_DESC_MBSSID_8821(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)\n\n/* Dword 7 */\n#define SET_TX_DESC_TX_BUFFER_SIZE_8812(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n#define SET_TX_DESC_TX_DESC_CHECKSUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n#define SET_TX_DESC_USB_TXAGG_NUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)\n#ifdef CONFIG_SDIO_HCI\n#define SET_TX_DESC_SDIO_TXSEQ_8812(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)\n#endif\n\n/* Dword 8 */\n#define SET_TX_DESC_HWSEQ_EN_8812(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)\n\n/* Dword 9 */\n#define SET_TX_DESC_SEQ_8812(__pTxDesc, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)\n\n/* Dword 10 */\n#define SET_TX_DESC_TX_BUFFER_ADDRESS_8812(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)\n#define GET_TX_DESC_TX_BUFFER_ADDRESS_8812(__pTxDesc)\tLE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)\n\n/* Dword 11 */\n#define SET_TX_DESC_NEXT_DESC_ADDRESS_8812(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)\n\n\n#define SET_EARLYMODE_PKTNUM_8812(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)\n#define SET_EARLYMODE_LEN0_8812(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)\n#define SET_EARLYMODE_LEN1_1_8812(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)\n#define SET_EARLYMODE_LEN1_2_8812(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)\n#define SET_EARLYMODE_LEN2_8812(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,  __Value)\n#define SET_EARLYMODE_LEN3_8812(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)\n\n#ifdef CONFIG_TX_EARLY_MODE\n\t#define USB_DUMMY_OFFSET\t\t2\n#else\n\t#define USB_DUMMY_OFFSET\t\t1\n#endif\n#define USB_DUMMY_LENGTH\t\t(USB_DUMMY_OFFSET * PACKET_OFFSET_SZ)\n\n\nvoid rtl8812a_cal_txdesc_chksum(u8 *ptxdesc);\nvoid rtl8812a_fill_fake_txdesc(PADAPTER\tpadapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8\tIsBTQosNull, u8 bDataFrame);\nvoid rtl8812a_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc);\nvoid rtl8812a_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);\nvoid rtl8812a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);\n#if defined(CONFIG_CONCURRENT_MODE)\nvoid fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);\n#endif\nvoid fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);\n\n#ifdef CONFIG_USB_HCI\ns32 rtl8812au_init_xmit_priv(PADAPTER padapter);\nvoid rtl8812au_free_xmit_priv(PADAPTER padapter);\ns32 rtl8812au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\ns32 rtl8812au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\ns32\t rtl8812au_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\ns32 rtl8812au_xmit_buf_handler(PADAPTER padapter);\nvoid rtl8812au_xmit_tasklet(void *priv);\ns32 rtl8812au_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\n#endif\n\n#ifdef CONFIG_PCI_HCI\ns32 rtl8812ae_init_xmit_priv(PADAPTER padapter);\nvoid rtl8812ae_free_xmit_priv(PADAPTER padapter);\nstruct xmit_buf *rtl8812ae_dequeue_xmitbuf(struct rtw_tx_ring *ring);\nvoid\trtl8812ae_xmitframe_resume(_adapter *padapter);\ns32 rtl8812ae_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\ns32 rtl8812ae_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\ns32\trtl8812ae_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\nvoid rtl8812ae_xmit_tasklet(void *priv);\n\n#ifdef CONFIG_XMIT_THREAD_MODE\ns32 rtl8812ae_xmit_buf_handler(_adapter *padapter);\n#endif\n\n#endif\n\n#ifdef CONFIG_TX_EARLY_MODE\nvoid UpdateEarlyModeInfo8812(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\n#endif\n\nvoid _dbg_dump_tx_info(_adapter\t*padapter, int frame_tag, u8 *ptxdesc);\n\nu8\tBWMapping_8812(PADAPTER Adapter, struct pkt_attrib *pattrib);\n\nu8\tSCMapping_8812(PADAPTER Adapter, struct pkt_attrib\t*pattrib);\n\n#endif /* __RTL8812_XMIT_H__ */\n\n#ifdef CONFIG_RTL8821A\n#include \"rtl8821a_xmit.h\"\n#endif /* CONFIG_RTL8821A */\n"
  },
  {
    "path": "include/rtl8814a_cmd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8814A_CMD_H__\n#define __RTL8814A_CMD_H__\n#include \"hal_com_h2c.h\"\n\n/* _RSVDPAGE_LOC_CMD0 */\n#define SET_8814A_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8814A_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_8814A_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8814A_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8814A_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n/* _SETPWRMODE_PARM */\n#define SET_8814A_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8814A_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)\n#define SET_8814A_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)\n#define SET_8814A_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8814A_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_8814A_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)\n#define SET_8814A_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n#define GET_8814A_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)\t\t\t\t\tLE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)\n\n\n/* _WoWLAN PARAM_CMD5 */\n#define SET_8814A_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_8814A_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_8814A_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)\n#define SET_8814A_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)\n#define SET_8814A_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)\n#define SET_8814A_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)\n#define SET_8814A_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)\n#define SET_8814A_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)\n#define SET_8814A_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value)\t\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_8814A_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n\n\n/* WLANINFO_PARM */\n#define SET_8814A_H2CCMD_WLANINFO_PARM_OPMODE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8814A_H2CCMD_WLANINFO_PARM_CHANNEL(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_8814A_H2CCMD_WLANINFO_PARM_BW40MHZ(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n\n/* _REMOTE_WAKEUP_CMD7 */\n#define SET_8814A_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_8814A_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_8814A_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)\n#define SET_8814A_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)\n\n\n/* _AP_OFFLOAD_CMD8 */\n#define SET_8814A_H2CCMD_AP_OFFLOAD_ON(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8814A_H2CCMD_AP_OFFLOAD_HIDDEN(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_8814A_H2CCMD_AP_OFFLOAD_DENYANY(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_8814A_H2CCMD_AP_OFFLOAD_WAKEUP_EVT_RPT(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n\n/* _PWR_MOD_CMD20 */\n#define SET_88E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_88E_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)\n#define SET_88E_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)\n#define SET_88E_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)\n#define SET_88E_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)\n#define SET_88E_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)\n\n/*\tAP_REQ_TXREP_CMD 0x43\t*/\n#define SET_8814A_H2CCMD_TXREP_PARM_STA1(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)\n#define SET_8814A_H2CCMD_TXREP_PARM_STA2(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\n#define SET_8814A_H2CCMD_TXREP_PARM_RTY(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value)\n\n/*\t\tC2H_AP_REQ_TXRPT\t\t*/\n#define\tGET_8814A_C2H_TC2H_APREQ_TXRPT_MACID1(_Header)\t\t\tLE_BITS_TO_1BYTE((_Header + 0), 0, 8)\n#define\tGET_8814A_C2H_TC2H_APREQ_TXRPT_TXOK1(_Header)\t\t\tLE_BITS_TO_2BYTE((_Header + 1), 0, 16)\n#define\tGET_8814A_C2H_TC2H_APREQ_TXRPT_TXFAIL1(_Header)\t\t\tLE_BITS_TO_2BYTE((_Header + 3), 0, 16)\n#define\tGET_8814A_C2H_TC2H_APREQ_TXRPT_INIRATE1(_Header)\t\tLE_BITS_TO_1BYTE((_Header + 5), 0, 8)\n#define\tGET_8814A_C2H_TC2H_APREQ_TXRPT_MACID2(_Header)\t\t\tLE_BITS_TO_1BYTE((_Header + 6), 0, 8)\n#define\tGET_8814A_C2H_TC2H_APREQ_TXRPT_TXOK2(_Header)\t\t\tLE_BITS_TO_2BYTE((_Header + 7), 0, 16)\n#define\tGET_8814A_C2H_TC2H_APREQ_TXRPT_TXFAIL2(_Header)\t\t\tLE_BITS_TO_2BYTE((_Header + 9), 0, 16)\n#define\tGET_8814A_C2H_TC2H_APREQ_TXRPT_INIRATE2(_Header)\t\tLE_BITS_TO_1BYTE((_Header + 11), 0, 8)\n\n/*\t\tC2H_SPC_STAT\t\t\t*/\n#define\tGET_8814A_C2H_SPC_STAT_IDX(_Header)\t\t\t\t\t\tLE_BITS_TO_1BYTE((_Header + 0), 0, 8)\n\t/*\tTip :TYPE_A data3 is msb and data0 is lsb\t*/\n#define\tGET_8814A_C2H_SPC_STAT_TYPEA_RETRY(_Header)\t\t\t\tLE_BITS_TO_4BYTE((_Header + 1), 0, 32)\n#define\tGET_8814A_C2H_SPC_STAT_TYPEB_PKT1(_Header)\t\t\t\tLE_BITS_TO_2BYTE((_Header + 1), 0, 16)\n#define\tGET_8814A_C2H_SPC_STAT_TYPEB_RETRY1(_Header)\t\t\tLE_BITS_TO_2BYTE((_Header + 3), 0, 16)\n#define\tGET_8814A_C2H_SPC_STAT_TYPEB_PKT2(_Header)\t\t\t\tLE_BITS_TO_2BYTE((_Header + 5), 0, 16)\n#define\tGET_8814A_C2H_SPC_STAT_TYPEB_RETRY2(_Header)\t\t\tLE_BITS_TO_2BYTE((_Header + 7), 0, 16)\n\n/*BCNHWSEQ*/\n#define SET_8814A_H2CCMD_BCNHWSEQ_EN(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 1, __Value)\n#define SET_8814A_H2CCMD_BCNHWSEQ_BCN_NUMBER(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd), 1, 3, __Value)\n#define SET_8814A_H2CCMD_BCNHWSEQ_HWSEQ(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd), 6, 1, __Value)\n#define SET_8814A_H2CCMD_BCNHWSEQ_EXHWSEQ(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd), 7, 1, __Value)\n#define SET_8814A_H2CCMD_BCNHWSEQ_PAGE(__pH2CCmd, __Value)\tSET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)\nvoid rtl8814_fw_update_beacon_cmd(_adapter *padapter);\n\n/* TX Beamforming */\n#define GET_8814A_C2H_TXBF_ORIGINATE(_Header)\t\t\tLE_BITS_TO_1BYTE(_Header, 0, 8)\n#define GET_8814A_C2H_TXBF_MACID(_Header)\t\t\t\tLE_BITS_TO_1BYTE((_Header + 1), 0, 8)\n\n\n\n/* / TX Feedback Content */\n#define\tUSEC_UNIT_FOR_8814A_C2H_TX_RPT_QUEUE_TIME\t\t\t256\n\n#define\tGET_8814A_C2H_TX_RPT_QUEUE_SELECT(_Header)\t\t\tLE_BITS_TO_1BYTE((_Header + 0), 0, 5)\n#define\tGET_8814A_C2H_TX_RPT_PKT_BROCAST(_Header)\t\t\tLE_BITS_TO_1BYTE((_Header + 0), 5, 1)\n#define\tGET_8814A_C2H_TX_RPT_LIFE_TIME_OVER(_Header)\t\t\tLE_BITS_TO_1BYTE((_Header + 0), 6, 1)\n#define\tGET_8814A_C2H_TX_RPT_RETRY_OVER(_Header)\t\t\t\tLE_BITS_TO_1BYTE((_Header + 0), 7, 1)\n#define\tGET_8814A_C2H_TX_RPT_MAC_ID(_Header)\t\t\t\t\tLE_BITS_TO_1BYTE((_Header + 1), 0, 8)\n#define\tGET_8814A_C2H_TX_RPT_DATA_RETRY_CNT(_Header)\t\tLE_BITS_TO_1BYTE((_Header + 2), 0, 6)\n#define\tGET_8814A_C2H_TX_RPT_QUEUE_TIME(_Header)\t\t\t\tLE_BITS_TO_2BYTE((_Header + 3), 0, 16)\t/* In unit of 256 microseconds. */\n#define\tGET_8814A_C2H_TX_RPT_FINAL_DATA_RATE(_Header)\t\tLE_BITS_TO_1BYTE((_Header + 5), 0, 8)\n\n\n/* _P2P_PS_OFFLOAD */\n#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_ENABLE(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)\n#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value)\t\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)\n#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_CTWINDOW_EN(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)\n#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_NOA0_EN(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)\n#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_NOA1_EN(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)\n#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value)\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)\n#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value)\t\t\tSET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)\n\ns32 FillH2CCmd_8814(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);\nvoid rtl8814_set_wowlan_cmd(_adapter *padapter, u8 enable);\nvoid rtl8814_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);\nvoid rtl8814_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode);\nu8 GetTxBufferRsvdPageNum8814(_adapter *padapter, bool wowlan);\nvoid rtl8814_req_txrpt_cmd(PADAPTER padapter, u8 macid);\n\n#ifdef CONFIG_TDLS\n\t#ifdef CONFIG_TDLS_CH_SW\n\t\tvoid rtl8814_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);\n\t#endif\n#endif\n\nvoid\nSet_RA_LDPC_8814(\n\tstruct sta_info\t*psta,\n\tBOOLEAN\t\t\tbLDPC\n);\n\ns32 c2h_handler_8814a(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);\n\n#ifdef CONFIG_BT_COEXIST\nvoid rtl8814a_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);\n#endif /* CONFIG_BT_COEXIST */\n#ifdef CONFIG_P2P_PS\n\tvoid rtl8814_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);\n#endif /* CONFIG_P2P */\n\n#endif/* __RTL8814A_CMD_H__ */\n"
  },
  {
    "path": "include/rtl8814a_dm.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8814A_DM_H__\n#define __RTL8814A_DM_H__\n\nvoid rtl8814_init_dm_priv(PADAPTER Adapter);\nvoid rtl8814_deinit_dm_priv(PADAPTER Adapter);\nvoid rtl8814_InitHalDm(PADAPTER Adapter);\nvoid rtl8814_HalDmWatchDog(PADAPTER Adapter);\n\n#endif\n"
  },
  {
    "path": "include/rtl8814a_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8814A_HAL_H__\n#define __RTL8814A_HAL_H__\n\n/* #include \"hal_com.h\" */\n#include \"hal_data.h\"\n\n/* include HAL Related header after HAL Related compiling flags */\n#include \"rtl8814a_spec.h\"\n#include \"rtl8814a_rf.h\"\n#include \"rtl8814a_dm.h\"\n#include \"rtl8814a_recv.h\"\n#include \"rtl8814a_xmit.h\"\n#include \"rtl8814a_cmd.h\"\n#include \"rtl8814a_led.h\"\n#include \"Hal8814PwrSeq.h\"\n#include \"Hal8814PhyReg.h\"\n#include \"Hal8814PhyCfg.h\"\n#ifdef DBG_CONFIG_ERROR_DETECT\n\t#include \"rtl8814a_sreset.h\"\n#endif /* DBG_CONFIG_ERROR_DETECT */\n\nenum {\n\tVOLTAGE_V25\t\t\t\t\t\t= 0x03,\n\tLDOE25_SHIFT\t\t\t\t\t= 28 ,\n};\n/* max. iram is 64k , max dmen is 32k. Total = 96k = 0x18000*/\n#define FW_SIZE\t\t\t\t\t\t\t0x18000\n#define FW_START_ADDRESS   0x1000\ntypedef struct _RT_FIRMWARE_8814 {\n\tFIRMWARE_SOURCE\teFWSource;\n#ifdef CONFIG_EMBEDDED_FWIMG\n\tu8\t\t\t*szFwBuffer;\n#else\n\tu8\t\t\tszFwBuffer[FW_SIZE];\n#endif\n\tu32\t\t\tulFwLength;\n} RT_FIRMWARE_8814, *PRT_FIRMWARE_8814;\n\n#define PAGE_SIZE_TX_8814\tPAGE_SIZE_128\n/* BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_8814\n * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/\n\n#define BCNQ_PAGE_NUM_8814\t\t(MAX_BEACON_LEN / PAGE_SIZE_TX_8814 + 6) /*0x08*/\n\n#define Rtl8814A_NIC_PWR_ON_FLOW\t\t\t\trtl8814A_power_on_flow\n#define Rtl8814A_NIC_RF_OFF_FLOW\t\t\t\trtl8814A_radio_off_flow\n#define Rtl8814A_NIC_DISABLE_FLOW\t\t\t\trtl8814A_card_disable_flow\n#define Rtl8814A_NIC_ENABLE_FLOW\t\t\t\trtl8814A_card_enable_flow\n#define Rtl8814A_NIC_SUSPEND_FLOW\t\t\t\trtl8814A_suspend_flow\n#define Rtl8814A_NIC_RESUME_FLOW\t\t\t\trtl8814A_resume_flow\n#define Rtl8814A_NIC_PDN_FLOW\t\t\t\t\trtl8814A_hwpdn_flow\n#define Rtl8814A_NIC_LPS_ENTER_FLOW\t\t\trtl8814A_enter_lps_flow\n#define Rtl8814A_NIC_LPS_LEAVE_FLOW\t\t\trtl8814A_leave_lps_flow\n\n/* *****************************************************\n *\t\t\t\tNew\tFirmware Header(8-byte alinment required)\n * *****************************************************\n * --- LONG WORD 0 ---- */\n#define GET_FIRMWARE_HDR_SIGNATURE_3081(__FwHdr)\t\tLE_BITS_TO_4BYTE(__FwHdr, 0, 16)\n#define GET_FIRMWARE_HDR_CATEGORY_3081(__FwHdr)\t\tLE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */\n#define GET_FIRMWARE_HDR_FUNCTION_3081(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */\n#define GET_FIRMWARE_HDR_VERSION_3081(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */\n#define GET_FIRMWARE_HDR_SUB_VER_3081(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */\n#define GET_FIRMWARE_HDR_SUB_IDX_3081(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+4, 24, 8) /* FW Subversion Index */\n\n/* --- LONG WORD 1 ---- */\n#define GET_FIRMWARE_HDR_SVN_IDX_3081(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+8, 0, 32)/* The SVN entry index */\n#define GET_FIRMWARE_HDR_RSVD1_3081(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+12, 0, 32)\n\n/* --- LONG WORD 2 ---- */\n#define GET_FIRMWARE_HDR_MONTH_3081(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+16, 0, 8) /* Release time Month field */\n#define GET_FIRMWARE_HDR_DATE_3081(__FwHdr)\t\t\t\tLE_BITS_TO_4BYTE(__FwHdr+16, 8, 8) /* Release time Date field */\n#define GET_FIRMWARE_HDR_HOUR_3081(__FwHdr)\t\t\t\tLE_BITS_TO_4BYTE(__FwHdr+16, 16, 8)/* Release time Hour field */\n#define GET_FIRMWARE_HDR_MINUTE_3081(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+16, 24, 8)/* Release time Minute field */\n#define GET_FIRMWARE_HDR_YEAR_3081(__FwHdr)\t\t\t\tLE_BITS_TO_4BYTE(__FwHdr+20, 0, 16)/* Release time Year field */\n#define GET_FIRMWARE_HDR_FOUNDRY_3081(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+20, 16, 8)/* Release time Foundry field */\n#define GET_FIRMWARE_HDR_RSVD2_3081(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+20, 24, 8)\n\n/* --- LONG WORD 3 ---- */\n#define GET_FIRMWARE_HDR_MEM_UASGE_DL_FROM_3081(__FwHdr)\t\tLE_BITS_TO_4BYTE(__FwHdr+24, 0, 1)\n#define GET_FIRMWARE_HDR_MEM_UASGE_BOOT_FROM_3081(__FwHdr)\tLE_BITS_TO_4BYTE(__FwHdr+24, 1, 1)\n#define GET_FIRMWARE_HDR_MEM_UASGE_BOOT_LOADER_3081(__FwHdr)LE_BITS_TO_4BYTE(__FwHdr+24, 2, 1)\n#define GET_FIRMWARE_HDR_MEM_UASGE_IRAM_3081(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+24, 3, 1)\n#define GET_FIRMWARE_HDR_MEM_UASGE_ERAM_3081(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+24, 4, 1)\n#define GET_FIRMWARE_HDR_MEM_UASGE_RSVD4_3081(__FwHdr)\t\tLE_BITS_TO_4BYTE(__FwHdr+24, 5, 3)\n#define GET_FIRMWARE_HDR_RSVD3_3081(__FwHdr)\t\t\t\t\tLE_BITS_TO_4BYTE(__FwHdr+24, 8, 8)\n#define GET_FIRMWARE_HDR_BOOT_LOADER_SZ_3081(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+24, 16, 16)\n#define GET_FIRMWARE_HDR_RSVD5_3081(__FwHdr)\t\t\t\t\tLE_BITS_TO_4BYTE(__FwHdr+28, 0, 32)\n\n/* --- LONG WORD 4 ---- */\n#define GET_FIRMWARE_HDR_TOTAL_DMEM_SZ_3081(__FwHdr)\tLE_BITS_TO_4BYTE(__FwHdr+36, 0, 32)\n#define GET_FIRMWARE_HDR_FW_CFG_SZ_3081(__FwHdr)\t\tLE_BITS_TO_4BYTE(__FwHdr+36, 0, 16)\n#define GET_FIRMWARE_HDR_FW_ATTR_SZ_3081(__FwHdr)\t\tLE_BITS_TO_4BYTE(__FwHdr+36, 16, 16)\n\n/* --- LONG WORD 5 ---- */\n#define GET_FIRMWARE_HDR_IROM_3081(__FwHdr)\t\t\t\tLE_BITS_TO_4BYTE(__FwHdr+40, 0, 32)\n#define GET_FIRMWARE_HDR_EROM_3081(__FwHdr)\t\t\t\tLE_BITS_TO_4BYTE(__FwHdr+44, 0, 32)\n\n/* --- LONG WORD 6 ---- */\n#define GET_FIRMWARE_HDR_IRAM_SZ_3081(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+48, 0, 32)\n#define GET_FIRMWARE_HDR_ERAM_SZ_3081(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+52, 0, 32)\n\n/* --- LONG WORD 7 ---- */\n#define GET_FIRMWARE_HDR_RSVD6_3081(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+56, 0, 32)\n#define GET_FIRMWARE_HDR_RSVD7_3081(__FwHdr)\t\t\tLE_BITS_TO_4BYTE(__FwHdr+60, 0, 32)\n\n\n\n/*\n * 2013/08/16 MH MOve from SDIO.h for common use.\n *   */\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)\n\t#define TRX_SHARE_MODE_8814A\t\t\t\t0\t/* TRX Buffer Share Index */\n\t#define BASIC_RXFF_SIZE_8814A\t\t\t\t24576/* Basic RXFF Size is 24K = 24*1024 Unit: Byte */\n\t#define TRX_SHARE_BUFF_UNIT_8814A\t\t\t65536/* TRX Share Buffer unit Size 64K = 64*1024 Unit: Byte */\n\t#define TRX_SHARE_BUFF_UNIT_PAGE_8814A\t(TRX_SHARE_BUFF_UNIT_8814A/PAGE_SIZE_8814A)/* 512 Pages */\n\n\t/* Origin: */\n\t#define  HPQ_PGNUM_8814A\t\t\t\t\t0x20\t/* High Queue */\n\t#define  LPQ_PGNUM_8814A\t\t\t\t\t0x20\t/* Low Queue */\n\t#define  NPQ_PGNUM_8814A\t\t\t\t\t0x20\t/* Normal Queue */\n\t#define  EPQ_PGNUM_8814A\t\t\t\t\t0x20\t/* Extra Queue */\n\n#else\t/*  #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) */\n\n\t#define  HPQ_PGNUM_8814A\t\t20\n\t#define  NPQ_PGNUM_8814A\t\t20\n\t#define  LPQ_PGNUM_8814A\t\t20 /* 1972 */\n\t#define  EPQ_PGNUM_8814A\t\t20\n\t#define  BCQ_PGNUM_8814A\t\t32\n\n#endif /* #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) */\n\n#ifdef CONFIG_WOWLAN\n\t#define WOWLAN_PAGE_NUM_8814\t0x06\n#else\n\t#define WOWLAN_PAGE_NUM_8814\t0x00\n#endif\n\n#define PAGE_SIZE_8814A\t\t\t\t\t\t128/* TXFF Page Size, Unit: Byte */\n#define MAX_RX_DMA_BUFFER_SIZE_8814A\t\t0x5C00\t/* BASIC_RXFF_SIZE_8814A + TRX_SHARE_MODE_8814A * TRX_SHARE_BUFF_UNIT_8814A */ /* Basic RXFF Size + ShareBuffer Size */\n#define TX_PAGE_BOUNDARY_8814A\t\t\tTXPKT_PGNUM_8814A\t/* Need to enlarge boundary, by KaiYuan */\n#define TX_PAGE_BOUNDARY_WOWLAN_8814A\tTXPKT_PGNUM_8814A\t/* TODO: 20130415 KaiYuan Check this value later */\n\n#ifdef CONFIG_FW_C2H_DEBUG\n\t#define RX_DMA_RESERVED_SIZE_8814A\t0x100\t/* 256B, reserved for c2h debug message */\n#else\n\t#define RX_DMA_RESERVED_SIZE_8814A\t0x0\t/* 0B */\n#endif\n#define RX_DMA_BOUNDARY_8814A\t\t(MAX_RX_DMA_BUFFER_SIZE_8814A - RX_DMA_RESERVED_SIZE_8814A - 1)\n\n#define  TOTAL_PGNUM_8814A\t\t2048\n#define  TXPKT_PGNUM_8814A\t\t(2048 - BCNQ_PAGE_NUM_8814-WOWLAN_PAGE_NUM_8814)\n#define  PUB_PGNUM_8814A\t\t(TXPKT_PGNUM_8814A-HPQ_PGNUM_8814A-NPQ_PGNUM_8814A-LPQ_PGNUM_8814A-EPQ_PGNUM_8814A)\n\n/* Note: For WMM Normal Chip Setting ,modify later */\n#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8814A\tTX_PAGE_BOUNDARY_8814A\n#define WMM_NORMAL_TX_PAGE_BOUNDARY_8814A\t\t(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8814A + 1)\n\n#define DRIVER_EARLY_INT_TIME_8814\t\t0x05\n#define BCN_DMA_ATIME_INT_TIME_8814\t\t0x02\n\n\n#define MAX_PAGE_SIZE\t\t\t4096\t/* @ page : 4k bytes */\n\n#define EFUSE_MAX_SECTION_JAGUAR\t\t\t\t64\n\n#define\tHWSET_MAX_SIZE_8814A\t\t\t512\n\n#define\tEFUSE_REAL_CONTENT_LEN_8814A\t1024\n#define\tEFUSE_MAX_BANK_8814A\t\t2\n\n#define\tEFUSE_MAP_LEN_8814A\t\t\t512\n#define\tEFUSE_MAX_SECTION_8814A\t\t64\n#define\tEFUSE_MAX_WORD_UNIT_8814A\t\t4\n#define\tEFUSE_PROTECT_BYTES_BANK_8814A\t\t16\n\n#define\tEFUSE_IC_ID_OFFSET_8814A\t\t506\t/* For some inferiority IC purpose. added by Roger, 2009.09.02. */\n#define AVAILABLE_EFUSE_ADDR_8814A(addr)\t(addr < EFUSE_REAL_CONTENT_LEN_8814A)\n\n/*-------------------------------------------------------------------------\nChip specific\n-------------------------------------------------------------------------*/\n\n/* pic buffer descriptor */\n#if 1 /* according to the define in the rtw_xmit.h, rtw_recv.h */\n\t#define RTL8814AE_SEG_NUM  TX_BUFFER_SEG_NUM /* 0:2 seg, 1: 4 seg, 2: 8 seg */\n\t#define TX_DESC_NUM_8814A  TX_BD_NUM   /* 128 */\n\t#define RX_DESC_NUM_8814A  PCI_MAX_RX_COUNT /* 128 */\n\t#ifdef CONFIG_CONCURRENT_MODE\n\t\t#define BE_QUEUE_TX_DESC_NUM_8814A  (TX_BD_NUM<<1)    /* 256 */\n\t#else\n\t\t#define BE_QUEUE_TX_DESC_NUM_8814A  (TX_BD_NUM+(TX_BD_NUM>>1)) /* 192 */\n\t#endif\n#else\n\t#define RTL8814AE_SEG_NUM  TX_BUFFER_SEG_NUM /* 0:2 seg, 1: 4 seg, 2: 8 seg */\n\t#define TX_DESC_NUM_8814A  128 /* 1024//2048 change by ylb 20130624 */\n\t#define RX_DESC_NUM_8814A  128 /* 1024 //512 change by ylb 20130624 */\n#endif\n\n/* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section\n * 9bytes + 1byt + 5bytes and pre 1byte.\n * For worst case:\n * | 1byte|----8bytes----|1byte|--5bytes--|\n * |         |            Reserved(14bytes)\t      |\n *   */\n#define\tEFUSE_OOB_PROTECT_BYTES\t\t15\t/* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */\n\n#ifdef CONFIG_FILE_FWIMG\nextern char *rtw_fw_file_path;\n#ifdef CONFIG_WOWLAN\nextern char *rtw_fw_wow_file_path;\n#endif\n#ifdef CONFIG_MP_INCLUDED\nextern char *rtw_fw_mp_bt_file_path;\n#endif /* CONFIG_MP_INCLUDED */\n#endif /* CONFIG_FILE_FWIMG */\n\n/* rtl8814_hal_init.c */\ns32 FirmwareDownload8814A(PADAPTER\tAdapter, BOOLEAN bUsedWoWLANFw);\nvoid\tInitializeFirmwareVars8814(PADAPTER padapter);\n\nvoid\nHal_InitEfuseVars_8814A(\n\t\tPADAPTER\tAdapter\n);\n\ns32 InitLLTTable8814A(\n\t\tPADAPTER\tAdapter\n);\n\n\nvoid InitRDGSetting8814A(PADAPTER padapter);\n\n/* void CheckAutoloadState8812A(PADAPTER padapter); */\n\n/* EFuse */\nu8\tGetEEPROMSize8814A(PADAPTER padapter);\nvoid hal_InitPGData_8814A(\n\t\tPADAPTER padapter,\n\t\tu8 *PROMContent\n);\n\nvoid\thal_ReadPROMVersion8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid\thal_ReadTxPowerInfo8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN\tAutoLoadFail);\nvoid\thal_ReadBoardType8814A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid\thal_ReadThermalMeter_8814A(PADAPTER\tAdapter, u8 *PROMContent, BOOLEAN\tAutoloadFail);\nvoid\thal_ReadChannelPlan8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid\thal_EfuseParseXtal_8814A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nvoid\thal_ReadAntennaDiversity8814A(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);\nvoid\thal_Read_TRX_antenna_8814A(PADAPTER\tAdapter, u8 *PROMContent, BOOLEAN AutoloadFail);\nvoid hal_ReadAmplifierType_8814A(\n\t\tPADAPTER\t\tAdapter\n);\nvoid hal_ReadPAType_8814A(\n\t\tPADAPTER\tAdapter,\n\t\tu8\t\t\t*PROMContent,\n\t\tBOOLEAN\t\tAutoloadFail,\n\t\tu8\t\t*pPAType,\n\t\tu8\t\t*pLNAType\n);\n\nvoid hal_ReadPowerTrackingType_8814A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);\n\nvoid hal_GetRxGainOffset_8814A(\n\tPADAPTER\tAdapter,\n\tu8 \t\t\t*PROMContent,\n\tBOOLEAN\t\tAutoloadFail\n);\nvoid Hal_EfuseParseKFreeData_8814A(\n\t\t\tPADAPTER\t\tAdapter,\n\t\t\tu8\t\t\t\t*PROMContent,\n\t\t\tBOOLEAN\t\t\tAutoloadFail);\nvoid\thal_ReadRFEType_8814A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);\nvoid\thal_EfuseParseBTCoexistInfo8814A(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\n\n/* void\thal_ReadUsbType_8812AU(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);\n * int\tFirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); */\nvoid\thal_ReadRemoteWakeup_8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);\nu8\tMgntQuery_NssTxRate(u16 Rate);\n\n/* BOOLEAN HalDetectPwrDownMode8812(PADAPTER Adapter); */\n\n#ifdef CONFIG_WOWLAN\n\tvoid Hal_DetectWoWMode(PADAPTER pAdapter);\n#endif /* CONFIG_WOWLAN */\n\nvoid _InitBeaconParameters_8814A(PADAPTER padapter);\nvoid SetBeaconRelatedRegisters8814A(PADAPTER padapter);\n\nvoid ReadRFType8814A(PADAPTER padapter);\nvoid InitDefaultValue8814A(PADAPTER padapter);\n\nu8 SetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval);\nvoid GetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval);\nu8 SetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);\nu8 GetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);\nvoid rtl8814_set_hal_ops(struct hal_ops *pHalFunc);\nvoid init_hal_spec_8814a(_adapter *adapter);\n\nvoid rtl8814_start_thread(PADAPTER padapter);\nvoid rtl8814_stop_thread(PADAPTER padapter);\n\n\n#ifdef CONFIG_PCI_HCI\n\tBOOLEAN\tInterruptRecognized8814AE(PADAPTER Adapter);\n\tvoid\tUpdateInterruptMask8814AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);\n\tvoid\tInitMAC_TRXBD_8814AE(PADAPTER Adapter);\n\tu16\tget_txbd_rw_reg(u16 ff_hwaddr);\n#endif\n\n#ifdef CONFIG_BT_COEXIST\n\tvoid rtl8814a_combo_card_WifiOnlyHwInit(PADAPTER Adapter);\n#endif\n\n#endif /* __RTL8188E_HAL_H__ */\n"
  },
  {
    "path": "include/rtl8814a_led.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8814A_LED_H__\n#define __RTL8814A_LED_H__\n\n#ifdef CONFIG_RTW_SW_LED\n/* ********************************************************************************\n * Interface to manipulate LED objects.\n * ******************************************************************************** */\n#ifdef CONFIG_USB_HCI\n\tvoid rtl8814au_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8814au_DeInitSwLeds(PADAPTER padapter);\n#endif /* CONFIG_USB_HCI */\n#ifdef CONFIG_PCI_HCI\n\tvoid rtl8814ae_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8814ae_DeInitSwLeds(PADAPTER padapter);\n#endif /* CONFIG_PCI_HCI */\n#ifdef CONFIG_SDIO_HCI\n\tvoid rtl8814s_InitSwLeds(PADAPTER padapter);\n\tvoid rtl8814s_DeInitSwLeds(PADAPTER padapter);\n#endif /* CONFIG_SDIO_HCI */\n\n#endif /* __RTL8814A_LED_H__ */\n#endif /*CONFIG_RTW_SW_LED*/\n"
  },
  {
    "path": "include/rtl8814a_recv.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8814A_RECV_H__\n#define __RTL8814A_RECV_H__\n\n#if defined(CONFIG_USB_HCI)\n\n\t#ifndef MAX_RECVBUF_SZ\n\t\t#ifndef CONFIG_MINIMAL_MEMORY_USAGE\n\t\t\t#ifdef CONFIG_PLATFORM_MSTAR\n\t\t\t\t#define MAX_RECVBUF_SZ (8192) /* 8K */\n\t\t\t#else\n\t\t\t\t#define MAX_RECVBUF_SZ (32768) /* 32k */\n\t\t\t#endif\n\t\t\t/* #define MAX_RECVBUF_SZ (24576) */ /* 24k */\n\t\t\t/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */\n\t\t\t/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */\n\t\t\t/* #define MAX_RECVBUF_SZ (15360) */ /* 15k < 16k */\n\t\t\t/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */\n\t\t#else\n\t\t\t#define MAX_RECVBUF_SZ (4000) /* about 4K */\n\t\t#endif\n\t#endif /* !MAX_RECVBUF_SZ */\n\n#elif defined(CONFIG_PCI_HCI)\n\t/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */\n\t/*\t#define MAX_RECVBUF_SZ (9100) */\n\t/* #else */\n\t#define MAX_RECVBUF_SZ (4000) /* about 4K\n\t* #endif */\n\n\n#elif defined(CONFIG_SDIO_HCI)\n\t#if 0\n\t\t/* temp solution */\n\t\t#ifdef CONFIG_SDIO_RX_COPY\n\t\t\t#define MAX_RECVBUF_SZ (10240)\n\t\t#else /*  !CONFIG_SDIO_RX_COPY */\n\t\t\t#define MAX_RECVBUF_SZ\tMAX_RX_DMA_BUFFER_SIZE_8821\n\t\t#endif /*  !CONFIG_SDIO_RX_COPY */\n\t#endif\n#endif\n\n\n/* RX buffer descriptor */\n/* DWORD 0 */\n#define SET_RX_BUFFER_DESC_DATA_LENGTH_8814A(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)\n#define SET_RX_BUFFER_DESC_LS_8814A(__pRxStatusDesc, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 14, 1, __Value)\n#define SET_RX_BUFFER_DESC_FS_8814A(__pRxStatusDesc, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)\n#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8814A(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 16, __Value)\n\n#define GET_RX_BUFFER_DESC_OWN_8814A(__pRxStatusDesc)\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)\n#define GET_RX_BUFFER_DESC_LS_8814A(__pRxStatusDesc)\t\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)\n#define GET_RX_BUFFER_DESC_FS_8814A(__pRxStatusDesc)\t\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)\n#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8814A(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)\n\n/* DWORD 1 */\n#define SET_RX_BUFFER_PHYSICAL_LOW_8814A(__pRxStatusDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)\n#define GET_RX_BUFFER_PHYSICAL_LOW_8814A(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 32)\n\n/* DWORD 2 */\n#define SET_RX_BUFFER_PHYSICAL_HIGH_8814A(__pRxStatusDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)\n\n/* DWORD 3*/ /* RESERVED */\n\n\n#if 0\n\t/* =============\n\t* RX Info\n\t* ============== */\n#endif\n/* DWORD 0 */\n#define SET_RX_STATUS_DESC_PKT_LEN_8814A(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)\n#define SET_RX_STATUS_DESC_EOR_8814A(__pRxStatusDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)\n#define SET_RX_STATUS_DESC_OWN_8814AE(__pRxStatusDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)\n\n#define GET_RX_STATUS_DESC_PKT_LEN_8814A(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)\n#define GET_RX_STATUS_DESC_CRC32_8814A(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)\n#define GET_RX_STATUS_DESC_ICV_8814A(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)\n#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8814A(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)\n#define GET_RX_STATUS_DESC_SECURITY_8814A(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)\n#define GET_RX_STATUS_DESC_QOS_8814A(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)\n#define GET_RX_STATUS_DESC_SHIFT_8814A(__pRxStatusDesc)\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)\n#define GET_RX_STATUS_DESC_PHY_STATUS_8814A(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)\n#define GET_RX_STATUS_DESC_SWDEC_8814A(__pRxStatusDesc)\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)\n#define GET_RX_STATUS_DESC_LAST_SEG_8814AE(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)\n#define GET_RX_STATUS_DESC_EOR_8814A(__pRxStatusDesc)\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)\n\n/* DWORD 1 */\n#define GET_RX_STATUS_DESC_MACID_8814A(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 7)\n#define GET_RX_STATUS_DESC_EXT_SECTYPE_8814A(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 7, 1)/* 20130415 KaiYuan add for 8814 */\n#define GET_RX_STATUS_DESC_TID_8814A(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 8, 4)\n#define GET_RX_STATUS_DESC_MACID_VLD_8814A(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 12, 1)\n#define GET_RX_STATUS_DESC_AMSDU_8814A(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 13, 1)\n#define GET_RX_STATUS_DESC_RXID_MATCH_8814A(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 14, 1)\n#define GET_RX_STATUS_DESC_PAGGR_8814A(__pRxStatusDesc)\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 15, 1)\n#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHKERR_8814A(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 20, 1)\n#define GET_RX_STATUS_DESC_TCPOFFLOAD_IPVER_8814A(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 21, 1)\n#define GET_RX_STATUS_DESC_TCPOFFLOAD_IS_TCPUDP_8814A(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 22, 1)\n#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHK_VLD_8814A(__pRxStatusDesc)\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 23, 1)\n#define GET_RX_STATUS_DESC_PAM_8814A(__pRxStatusDesc)\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 24, 1)\n#define GET_RX_STATUS_DESC_PWR_8814A(__pRxStatusDesc)\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 25, 1)\n#define GET_RX_STATUS_DESC_MORE_DATA_8814A(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 26, 1)\n#define GET_RX_STATUS_DESC_MORE_FRAG_8814A(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 27, 1)\n#define GET_RX_STATUS_DESC_TYPE_8814A(__pRxStatusDesc)\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 28, 2)\n#define GET_RX_STATUS_DESC_FIRST_SEG_8814AE(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)\n#define GET_RX_STATUS_DESC_EOR_8814AE(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)\n#define GET_RX_STATUS_DESC_MC_8814A(__pRxStatusDesc)\t\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 30, 1)\n#define GET_RX_STATUS_DESC_BC_8814A(__pRxStatusDesc)\t\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+4, 31, 1)\n\n/* DWORD 2 */\n#define GET_RX_STATUS_DESC_SEQ_8814A(__pRxStatusDesc)\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)\n#define GET_RX_STATUS_DESC_FRAG_8814A(__pRxStatusDesc)\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)\n#ifdef CONFIG_USB_RX_AGGREGATION\n\t#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8814A(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 8)\n#else\n\t#define GET_RX_STATUS_DESC_RX_IS_QOS_8814A(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)\n#endif\n#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8814A(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)\n#define GET_RX_STATUS_DESC_HWRSVD_8814A(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 24, 4)\n#define GET_RX_STATUS_C2H_8814A(__pRxStatusDesc)\t\t\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)\n#define GET_RX_STATUS_DESC_FCS_OK_8814A(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)\n\n/* DWORD 3 */\n#define GET_RX_STATUS_DESC_RX_RATE_8814A(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)\n#define GET_RX_STATUS_DESC_BSSID_FIT_H_8814A(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 7, 3)/* 20130415 KaiYuan add for 8814 */\n#define GET_RX_STATUS_DESC_HTC_8814A(__pRxStatusDesc)\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)\n#define GET_RX_STATUS_DESC_EOSP_8814A(__pRxStatusDesc)\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)\n#define GET_RX_STATUS_DESC_BSSID_FIT_L_8814A(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)\n#define GET_RX_STATUS_DESC_DMA_AGG_NUM_8814A(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)/* 20130415 KaiYuan Check if it exist anymore */\n#define GET_RX_STATUS_DESC_PATTERN_MATCH_8814A(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 29, 1)\n#define GET_RX_STATUS_DESC_UNICAST_8814A(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 30, 1)\n#define GET_RX_STATUS_DESC_MAGIC_WAKE_8814A(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+12, 31, 1)\n\n/* DWORD 4 */\n#define GET_RX_STATUS_DESC_PATTERN_IDX_8814A(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+16, 0, 8)\n#define GET_RX_STATUS_DESC_RX_EOF_8814A(__pRxStatusDesc)\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+16, 8, 1)\n#define GET_RX_STATUS_DESC_RX_SCRAMBLER_8814A(__pRxStatusDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+16, 9, 7)\n#define GET_RX_STATUS_DESC_RX_PRE_NDP_VLD_8814A(__pRxStatusDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+16, 16, 1)\n#define GET_RX_STATUS_DESC_A1_FIT_8814A(__pRxStatusDesc)\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+16, 24, 5)\n\n\n/* DWORD 5 */\n#define GET_RX_STATUS_DESC_TSFL_8814A(__pRxStatusDesc)\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)\n\n\n/* Rx smooth factor */\n#define Rx_Smooth_Factor (20)\n\n#ifdef CONFIG_USB_HCI\n\ts32 rtl8814au_init_recv_priv(PADAPTER padapter);\n\tvoid rtl8814au_free_recv_priv(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\ts32 rtl8814ae_init_recv_priv(PADAPTER padapter);\n\tvoid rtl8814ae_free_recv_priv(PADAPTER padapter);\n#endif\n\n#if 0\n\t/* temp solution */\n\t#ifdef CONFIG_SDIO_HCI\n\t\ts32 InitRecvPriv8821AS(PADAPTER padapter);\n\t\tvoid FreeRecvPriv8821AS(PADAPTER padapter);\n\t#endif /*  CONFIG_SDIO_HCI */\n#endif\n\nvoid rtl8814_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);\n\n#endif /* __RTL8814A_RECV_H__ */\n"
  },
  {
    "path": "include/rtl8814a_rf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8814A_RF_H__\n#define __RTL8814A_RF_H__\n\nvoid\nPHY_RF6052SetBandwidth8814A(\n\t\tPADAPTER\t\t\t\tAdapter,\n\t\tenum channel_width\t\tBandwidth);\n\n\nint\nPHY_RF6052_Config_8814A(\n\t\tPADAPTER\tAdapter);\n\n#endif/* __RTL8188E_RF_H__ */\n"
  },
  {
    "path": "include/rtl8814a_spec.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8814A_SPEC_H__\n#define __RTL8814A_SPEC_H__\n\n#include <drv_conf.h>\n\n\n/* ************************************************************\n *\n * ************************************************************ */\n\n/* -----------------------------------------------------\n *\n *\t0x0000h ~ 0x00FFh\tSystem Configuration\n *\n * ----------------------------------------------------- */\n#define REG_SYS_ISO_CTRL_8814A\t\t\t0x0000\t/* 2 Byte */\n#define REG_SYS_FUNC_EN_8814A\t\t\t0x0002\t/* 2 Byte */\n#define REG_SYS_PW_CTRL_8814A\t\t\t0x0004\t/* 4 Byte        */\n#define REG_SYS_CLKR_8814A\t\t\t\t0x0008\t/* 2 Byte */\n#define REG_SYS_EEPROM_CTRL_8814A\t\t0x000A\t/* 2 Byte        */\n#define REG_EE_VPD_8814A\t\t\t\t0x000C\t/* 2 Byte */\n#define REG_SYS_SWR_CTRL1_8814A\t\t\t0x0010\t/* 1 Byte */\n#define REG_SPS0_CTRL_8814A\t\t\t\t0x0011\t/* 7 Byte */\n#define REG_SYS_SWR_CTRL3_8814A\t\t\t0x0018\t/* 4 Byte */\n#define REG_RSV_CTRL_8814A\t\t\t\t0x001C\t/* 3 Byte */\n#define REG_RF_CTRL0_8814A\t\t\t\t0x001F\t/* 1 Byte */\n#define REG_RF_CTRL1_8814A\t\t\t\t0x0020\t/* 1 Byte */\n#define REG_RF_CTRL2_8814A\t\t\t\t0x0021\t/* 1 Byte */\n#define REG_LPLDO_CTRL_8814A\t\t\t0x0023\t/* 1 Byte */\n#define REG_AFE_CTRL1_8814A\t\t\t\t0x0024\t/* 4 Byte        */\n#define REG_AFE_CTRL2_8814A\t\t\t\t0x0028\t/* 4 Byte        */\n#define REG_AFE_CTRL3_8814A\t\t\t\t0x002c\t/* 4 Byte  */\n#define REG_EFUSE_CTRL_8814A\t\t\t0x0030\n#define REG_LDO_EFUSE_CTRL_8814A\t\t0x0034\n#define REG_PWR_DATA_8814A\t\t\t\t0x0038\n#define REG_CAL_TIMER_8814A\t\t\t\t0x003C\n#define REG_ACLK_MON_8814A\t\t\t\t0x003E\n#define REG_GPIO_MUXCFG_8814A\t\t\t0x0040\n#define REG_GPIO_IO_SEL_8814A\t\t\t0x0042\n#define REG_MAC_PINMUX_CFG_8814A\t\t0x0043\n#define REG_GPIO_PIN_CTRL_8814A\t\t\t0x0044\n#define REG_GPIO_INTM_8814A\t\t\t\t0x0048\n#define REG_LEDCFG0_8814A\t\t\t\t0x004C\n#define REG_LEDCFG1_8814A\t\t\t\t0x004D\n#define REG_LEDCFG2_8814A\t\t\t\t0x004E\n#define REG_LEDCFG3_8814A\t\t\t\t0x004F\n#define REG_FSIMR_8814A\t\t\t\t\t0x0050\n#define REG_FSISR_8814A\t\t\t\t\t0x0054\n#define REG_HSIMR_8814A\t\t\t\t\t0x0058\n#define REG_HSISR_8814A\t\t\t\t\t0x005c\n#define REG_GPIO_EXT_CTRL_8814A\t\t\t0x0060\n#define REG_GPIO_STATUS_8814A\t\t\t0x006C\n#define REG_SDIO_CTRL_8814A\t\t\t\t0x0070\n#define REG_HCI_OPT_CTRL_8814A\t\t\t0x0074\n#define REG_RF_CTRL3_8814A\t\t\t\t0x0076\t/* 1 Byte */\n#define REG_AFE_CTRL4_8814A\t\t\t\t0x0078\n#define REG_8051FW_CTRL_8814A\t\t\t0x0080\n#define REG_HIMR0_8814A\t\t\t\t\t0x00B0\n#define REG_HISR0_8814A\t\t\t\t\t0x00B4\n#define REG_HIMR1_8814A\t\t\t\t\t0x00B8\n#define REG_HISR1_8814A\t\t\t\t\t0x00BC\n#define REG_SYS_CFG1_8814A\t\t\t\t0x00F0\n#define REG_SYS_CFG2_8814A\t\t\t\t0x00FC\n#define REG_SYS_CFG3_8814A\t\t\t\t0x1000\n\n/* -----------------------------------------------------\n *\n *\t0x0100h ~ 0x01FFh\tMACTOP General Configuration\n *\n * ----------------------------------------------------- */\n#define REG_CR_8814A\t\t\t\t\t\t0x0100\n#define REG_PBP_8814A\t\t\t\t\t0x0104\n#define REG_PKT_BUFF_ACCESS_CTRL_8814A\t0x0106\n#define REG_TRXDMA_CTRL_8814A\t\t\t0x010C\n#define REG_TRXFF_BNDY_8814A\t\t\t0x0114\n#define REG_TRXFF_STATUS_8814A\t\t\t0x0118\n#define REG_RXFF_PTR_8814A\t\t\t\t0x011C\n#define REG_CPWM_8814A\t\t\t\t\t0x012F\n#define REG_FWIMR_8814A\t\t\t\t\t0x0130\n#define REG_FWISR_8814A\t\t\t\t\t0x0134\n#define REG_FTIMR_8814A\t\t\t\t\t0x0138\n#define REG_PKTBUF_DBG_CTRL_8814A\t\t0x0140\n#define REG_RXPKTBUF_CTRL_8814A\t\t0x0142\n#define REG_PKTBUF_DBG_DATA_L_8814A\t0x0144\n#define REG_PKTBUF_DBG_DATA_H_8814A\t0x0148\n\n#define REG_WOWLAN_WAKE_REASON\t\t\tREG_MCUTST_WOWLAN\n\n#define REG_TC0_CTRL_8814A\t\t\t\t0x0150\n#define REG_TC1_CTRL_8814A\t\t\t\t0x0154\n#define REG_TC2_CTRL_8814A\t\t\t\t0x0158\n#define REG_TC3_CTRL_8814A\t\t\t\t0x015C\n#define REG_TC4_CTRL_8814A\t\t\t\t0x0160\n#define REG_TCUNIT_BASE_8814A\t\t\t0x0164\n#define REG_RSVD3_8814A\t\t\t\t\t0x0168\n#define REG_C2HEVT_MSG_NORMAL_8814A\t0x01A0\n#define REG_C2HEVT_CLEAR_8814A\t\t\t0x01AF\n#define REG_MCUTST_1_8814A\t\t\t\t0x01C0\n#define REG_MCUTST_WOWLAN_8814A\t\t0x01C7\n#define REG_FMETHR_8814A\t\t\t\t0x01C8\n#define REG_HMETFR_8814A\t\t\t\t0x01CC\n#define REG_HMEBOX_0_8814A\t\t\t\t0x01D0\n#define REG_HMEBOX_1_8814A\t\t\t\t0x01D4\n#define REG_HMEBOX_2_8814A\t\t\t\t0x01D8\n#define REG_HMEBOX_3_8814A\t\t\t\t0x01DC\n#define REG_LLT_INIT_8814A\t\t\t\t0x01E0\n#define REG_LLT_ADDR_8814A\t\t\t\t0x01E4 /* 20130415 KaiYuan add for 8814 */\n#define REG_HMEBOX_EXT0_8814A\t\t\t0x01F0\n#define REG_HMEBOX_EXT1_8814A\t\t\t0x01F4\n#define REG_HMEBOX_EXT2_8814A\t\t\t0x01F8\n#define REG_HMEBOX_EXT3_8814A\t\t\t0x01FC\n\n/* -----------------------------------------------------\n *\n *\t0x0200h ~ 0x027Fh\tTXDMA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_FIFOPAGE_CTRL_1_8814A\t\t\t0x0200\n#define REG_FIFOPAGE_CTRL_2_8814A\t\t0x0204\n#define REG_AUTO_LLT_8814A\t\t\t\t\t0x0208\n#define REG_TXDMA_OFFSET_CHK_8814A\t0x020C\n#define REG_TXDMA_STATUS_8814A\t\t\t0x0210\n#define REG_RQPN_NPQ_8814A\t\t\t\t0x0214\n#define REG_TQPNT1_8814A\t\t\t\t\t0x0218\n#define REG_TQPNT2_8814A\t\t\t\t\t0x021C\n#define REG_TQPNT3_8814A\t\t\t\t\t0x0220\n#define REG_TQPNT4_8814A\t\t\t\t\t0x0224\n#define REG_RQPN_CTRL_1_8814A\t\t\t\t0x0228\n#define REG_RQPN_CTRL_2_8814A\t\t\t\t0x022C\n#define REG_FIFOPAGE_INFO_1_8814A\t\t\t0x0230\n#define REG_FIFOPAGE_INFO_2_8814A\t\t\t0x0234\n#define REG_FIFOPAGE_INFO_3_8814A\t\t\t0x0238\n#define REG_FIFOPAGE_INFO_4_8814A\t\t\t0x023C\n#define REG_FIFOPAGE_INFO_5_8814A\t\t\t0x0240\n\n\n/* -----------------------------------------------------\n *\n *\t0x0280h ~ 0x02FFh\tRXDMA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_RXDMA_AGG_PG_TH_8814A\t\t0x0280\n#define REG_RXPKT_NUM_8814A\t\t\t\t0x0284 /* The number of packets in RXPKTBUF. */\n#define REG_RXDMA_CONTROL_8814A\t\t\t0x0286 /* ?????? Control the RX DMA. */\n#define REG_RXDMA_STATUS_8814A\t\t\t0x0288\n#define REG_RXDMA_MODE_8814A\t\t\t\t0x0290 /* ?????? */\n#define REG_EARLY_MODE_CONTROL_8814A\t0x02BC /* ?????? */\n#define REG_RSVD5_8814A\t\t\t\t\t0x02F0 /* ?????? */\n\n\n/* -----------------------------------------------------\n *\n *\t0x0300h ~ 0x03FFh\tPCIe\n *\n * ----------------------------------------------------- */\n#define\tREG_PCIE_CTRL_REG_8814A\t\t\t0x0300\n#define\tREG_INT_MIG_8814A\t\t\t\t0x0304\t/* Interrupt Migration */\n#define\tREG_BCNQ_TXBD_DESA_8814A\t\t0x0308\t/* TX Beacon Descriptor Address */\n#define\tREG_MGQ_TXBD_DESA_8814A\t\t\t0x0310\t/* TX Manage Queue Descriptor Address */\n#define\tREG_VOQ_TXBD_DESA_8814A\t\t\t0x0318\t/* TX VO Queue Descriptor Address */\n#define\tREG_VIQ_TXBD_DESA_8814A\t\t\t0x0320\t/* TX VI Queue Descriptor Address */\n#define\tREG_BEQ_TXBD_DESA_8814A\t\t\t0x0328\t/* TX BE Queue Descriptor Address */\n#define\tREG_BKQ_TXBD_DESA_8814A\t\t\t0x0330\t/* TX BK Queue Descriptor Address */\n#define\tREG_RXQ_RXBD_DESA_8814A\t\t\t0x0338\t/* RX Queue\tDescriptor Address */\n#define REG_HI0Q_TXBD_DESA_8814A\t\t0x0340\n#define REG_HI1Q_TXBD_DESA_8814A\t\t0x0348\n#define REG_HI2Q_TXBD_DESA_8814A\t\t0x0350\n#define REG_HI3Q_TXBD_DESA_8814A\t\t0x0358\n#define REG_HI4Q_TXBD_DESA_8814A\t\t0x0360\n#define REG_HI5Q_TXBD_DESA_8814A\t\t0x0368\n#define REG_HI6Q_TXBD_DESA_8814A\t\t0x0370\n#define REG_HI7Q_TXBD_DESA_8814A\t\t0x0378\n#define\tREG_MGQ_TXBD_NUM_8814A\t\t\t0x0380\n#define\tREG_RX_RXBD_NUM_8814A\t\t\t0x0382\n#define\tREG_VOQ_TXBD_NUM_8814A\t\t\t0x0384\n#define\tREG_VIQ_TXBD_NUM_8814A\t\t\t0x0386\n#define\tREG_BEQ_TXBD_NUM_8814A\t\t\t0x0388\n#define\tREG_BKQ_TXBD_NUM_8814A\t\t\t0x038A\n#define\tREG_HI0Q_TXBD_NUM_8814A\t\t\t0x038C\n#define\tREG_HI1Q_TXBD_NUM_8814A\t\t\t0x038E\n#define\tREG_HI2Q_TXBD_NUM_8814A\t\t\t0x0390\n#define\tREG_HI3Q_TXBD_NUM_8814A\t\t\t0x0392\n#define\tREG_HI4Q_TXBD_NUM_8814A\t\t\t0x0394\n#define\tREG_HI5Q_TXBD_NUM_8814A\t\t\t0x0396\n#define\tREG_HI6Q_TXBD_NUM_8814A\t\t\t0x0398\n#define\tREG_HI7Q_TXBD_NUM_8814A\t\t\t0x039A\n#define\tREG_TSFTIMER_HCI_8814A\t\t\t0x039C\n\n/* Read Write Point */\n#define\tREG_VOQ_TXBD_IDX_8814A\t\t\t0x03A0\n#define\tREG_VIQ_TXBD_IDX_8814A\t\t\t0x03A4\n#define\tREG_BEQ_TXBD_IDX_8814A\t\t\t0x03A8\n#define\tREG_BKQ_TXBD_IDX_8814A\t\t\t0x03AC\n#define\tREG_MGQ_TXBD_IDX_8814A\t\t\t0x03B0\n#define\tREG_RXQ_TXBD_IDX_8814A\t\t\t0x03B4\n#define\tREG_HI0Q_TXBD_IDX_8814A\t\t\t0x03B8\n#define\tREG_HI1Q_TXBD_IDX_8814A\t\t\t0x03BC\n#define\tREG_HI2Q_TXBD_IDX_8814A\t\t\t0x03C0\n#define\tREG_HI3Q_TXBD_IDX_8814A\t\t\t0x03C4\n#define\tREG_HI4Q_TXBD_IDX_8814A\t\t\t0x03C8\n#define\tREG_HI5Q_TXBD_IDX_8814A\t\t\t0x03CC\n#define\tREG_HI6Q_TXBD_IDX_8814A\t\t\t0x03D0\n#define\tREG_HI7Q_TXBD_IDX_8814A\t\t\t0x03D4\n#define REG_DBG_SEL_V1_8814A\t\t\t\t0x03D8\n#define REG_PCIE_HRPWM1_V1_8814A\t\t\t0x03D9\n#define REG_PCIE_HCPWM1_V1_8814A\t\t\t0x03DA\n#define REG_PCIE_CTRL2_8814A\t\t\t\t0x03DB\n#define REG_PCIE_HRPWM2_V1_8814A\t\t\t0x03DC\n#define REG_PCIE_HCPWM2_V1_8814A\t\t\t0x03DE\n#define REG_PCIE_H2C_MSG_V1_8814A\t\t0x03E0\n#define REG_PCIE_C2H_MSG_V1_8814A\t\t0x03E4\n#define REG_DBI_WDATA_V1_8814A\t\t\t0x03E8\n#define REG_DBI_RDATA_V1_8814A\t\t\t0x03EC\n#define REG_DBI_FLAG_V1_8814A\t\t\t\t0x03F0\n#define REG_MDIO_V1_8814A\t\t\t\t\t0x03F4\n#define REG_PCIE_MIX_CFG_8814A\t\t\t0x03F8\n#define REG_DBG_8814A\t\t\t\t\t\t0x03FC\n/* -----------------------------------------------------\n *\n *\t0x0400h ~ 0x047Fh\tProtocol Configuration\n *\n * ----------------------------------------------------- */\n#define REG_VOQ_INFORMATION_8814A\t\t0x0400\n#define REG_VIQ_INFORMATION_8814A\t\t0x0404\n#define REG_BEQ_INFORMATION_8814A\t\t0x0408\n#define REG_BKQ_INFORMATION_8814A\t\t0x040C\n#define REG_MGQ_INFORMATION_8814A\t\t0x0410\n#define REG_HGQ_INFORMATION_8814A\t\t0x0414\n#define REG_BCNQ_INFORMATION_8814A\t0x0418\n#define REG_TXPKT_EMPTY_8814A\t\t\t0x041A\n#define REG_CPU_MGQ_INFORMATION_8814A\t0x041C\n#define REG_FWHW_TXQ_CTRL_8814A\t\t0x0420\n#define REG_HWSEQ_CTRL_8814A\t\t\t0x0423\n#define REG_TXPKTBUF_BCNQ_BDNY_8814A\t0x0424\n/* #define REG_MGQ_BDNY_8814A\t\t\t\t0x0425 */\n#define REG_LIFETIME_EN_8814A\t\t\t\t0x0426\n/* #define REG_FW_FREE_TAIL_8814A\t\t\t0x0427 */\n#define REG_SPEC_SIFS_8814A\t\t\t\t0x0428\n#define REG_RETRY_LIMIT_8814A\t\t\t\t0x042A\n#define REG_TXBF_CTRL_8814A\t\t\t\t0x042C\n#define REG_DARFRC_8814A\t\t\t\t0x0430\n#define REG_RARFRC_8814A\t\t\t\t0x0438\n#define REG_RRSR_8814A\t\t\t\t\t0x0440\n#define REG_ARFR0_8814A\t\t\t\t\t0x0444\n#define REG_ARFR1_8814A\t\t\t\t\t0x044C\n#define REG_CCK_CHECK_8814A\t\t\t\t0x0454\n#define REG_AMPDU_MAX_TIME_8814A\t\t\t0x0455\n#define REG_TXPKTBUF_BCNQ1_BDNY_8814A\t0x0456\n#define REG_AMPDU_MAX_LENGTH_8814A\t0x0458\n#define REG_ACQ_STOP_8814A\t\t\t\t0x045C\n#define REG_NDPA_RATE_8814A\t\t\t\t0x045D\n#define REG_TX_HANG_CTRL_8814A\t\t\t0x045E\n#define REG_NDPA_OPT_CTRL_8814A\t\t0x045F\n#define REG_FAST_EDCA_CTRL_8814A\t\t0x0460\n#define REG_RD_RESP_PKT_TH_8814A\t\t0x0463\n#define REG_CMDQ_INFO_8814A\t\t\t\t0x0464\n#define REG_Q4_INFO_8814A\t\t\t\t\t0x0468\n#define REG_Q5_INFO_8814A\t\t\t\t\t0x046C\n#define REG_Q6_INFO_8814A\t\t\t\t\t0x0470\n#define REG_Q7_INFO_8814A\t\t\t\t\t0x0474\n#define REG_WMAC_LBK_BUF_HD_8814A\t\t0x0478\n#define REG_MGQ_PGBNDY_8814A\t\t\t\t0x047A\n#define REG_INIRTS_RATE_SEL_8814A\t\t\t0x0480\n#define REG_BASIC_CFEND_RATE_8814A\t\t0x0481\n#define REG_STBC_CFEND_RATE_8814A\t\t0x0482\n#define REG_DATA_SC_8814A\t\t\t\t\t0x0483\n#define REG_MACID_SLEEP3_8814A\t\t\t0x0484\n#define REG_MACID_SLEEP1_8814A\t\t\t0x0488\n#ifdef CONFIG_WOWLAN\n\t#define REG_TXPKTBUF_IV_LOW\t\t\t\t0x0484\n\t#define REG_TXPKTBUF_IV_HIGH\t\t\t0x0488\n#endif /* CONFIG_WOWLAN */\n#define REG_ARFR2_8814A\t\t\t\t\t0x048C\n#define REG_ARFR3_8814A\t\t\t\t\t0x0494\n#define REG_ARFR4_8814A\t\t\t\t\t0x049C\n#define REG_ARFR5_8814A\t\t\t\t\t0x04A4\n#define REG_TXRPT_START_OFFSET_8814A\t\t0x04AC\n#define REG_TRYING_CNT_TH_8814A\t\t\t0x04B0\n#define REG_POWER_STAGE1_8814A\t\t0x04B4\n#define REG_POWER_STAGE2_8814A\t\t0x04B8\n#define REG_SW_AMPDU_BURST_MODE_CTRL_8814A\t0x04BC\n#define REG_PKT_LIFE_TIME_8814A\t\t\t0x04C0\n#define REG_PKT_BE_BK_LIFE_TIME_8814A\t\t0x04C2 /* ?????? */\n#define REG_STBC_SETTING_8814A\t\t\t0x04C4\n#define REG_STBC_8814A\t\t\t\t\t\t0x04C5\n#define REG_QUEUE_CTRL_8814A\t\t\t\t0x04C6\n#define REG_SINGLE_AMPDU_CTRL_8814A\t\t0x04C7\n#define REG_PROT_MODE_CTRL_8814A\t\t0x04C8\n#define REG_MAX_AGGR_NUM_8814A\t\t0x04CA\n#define REG_RTS_MAX_AGGR_NUM_8814A\t0x04CB\n#define REG_BAR_MODE_CTRL_8814A\t\t0x04CC\n#define REG_RA_TRY_RATE_AGG_LMT_8814A\t0x04CF\n#define REG_MACID_SLEEP2_8814A\t\t\t0x04D0\n#define REG_MACID_SLEEP0_8814A\t\t\t0x04D4\n#define REG_HW_SEQ0_8814A\t\t\t\t0x04D8\n#define REG_HW_SEQ1_8814A\t\t\t\t0x04DA\n#define REG_HW_SEQ2_8814A\t\t\t\t0x04DC\n#define REG_HW_SEQ3_8814A\t\t\t\t0x04DE\n#define REG_NULL_PKT_STATUS_8814A\t\t\t0x04E0\n#define REG_PTCL_ERR_STATUS_8814A\t\t\t0x04E2\n#define REG_DROP_PKT_NUM_8814A\t\t\t0x04EC\n#define REG_PTCL_TX_RPT_8814A\t\t\t\t0x04F0\n#define REG_Dummy_8814A\t\t\t\t\t0x04FC\n\n\n/* -----------------------------------------------------\n *\n *\t0x0500h ~ 0x05FFh\tEDCA Configuration\n *\n * ----------------------------------------------------- */\n#define REG_EDCA_VO_PARAM_8814A\t\t\t0x0500\n#define REG_EDCA_VI_PARAM_8814A\t\t\t0x0504\n#define REG_EDCA_BE_PARAM_8814A\t\t\t0x0508\n#define REG_EDCA_BK_PARAM_8814A\t\t\t0x050C\n#define REG_BCNTCFG_8814A\t\t\t\t\t0x0510\n#define REG_PIFS_8814A\t\t\t\t\t\t0x0512\n#define REG_RDG_PIFS_8814A\t\t\t\t\t0x0513\n#define REG_SIFS_CTX_8814A\t\t\t\t\t0x0514\n#define REG_SIFS_TRX_8814A\t\t\t\t\t0x0516\n#define REG_AGGR_BREAK_TIME_8814A\t\t\t0x051A\n#define REG_SLOT_8814A\t\t\t\t\t\t0x051B\n#define REG_TX_PTCL_CTRL_8814A\t\t\t\t0x0520\n#define REG_TXPAUSE_8814A\t\t\t\t\t0x0522\n#define REG_DIS_TXREQ_CLR_8814A\t\t\t0x0523\n#define REG_RD_CTRL_8814A\t\t\t\t\t0x0524\n/*\n * Format for offset 540h-542h:\n *\t[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.\n *\t[7:4]:   Reserved.\n *\t[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.\n *\t[23:20]: Reserved\n * Description:\n *\t              |\n * |<--Setup--|--Hold------------>|\n *\t--------------|----------------------\n * |\n * TBTT\n * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.\n * Described by Designer Tim and Bruce, 2011-01-14.\n *   */\n#define REG_TBTT_PROHIBIT_8814A\t\t\t0x0540\n#define REG_RD_NAV_NXT_8814A\t\t\t\t0x0544\n#define REG_NAV_PROT_LEN_8814A\t\t\t0x0546\n#define REG_BCN_CTRL_8814A\t\t\t\t\t0x0550\n#define REG_BCN_CTRL_1_8814A\t\t\t\t0x0551\n#define REG_MBID_NUM_8814A\t\t\t\t0x0552\n#define REG_DUAL_TSF_RST_8814A\t\t\t\t0x0553\n#define REG_MBSSID_BCN_SPACE_8814A\t\t0x0554\n#define REG_DRVERLYINT_8814A\t\t\t\t0x0558\n#define REG_BCNDMATIM_8814A\t\t\t\t0x0559\n#define REG_ATIMWND_8814A\t\t\t\t\t0x055A\n#define REG_USTIME_TSF_8814A\t\t\t\t0x055C\n#define REG_BCN_MAX_ERR_8814A\t\t\t\t0x055D\n#define REG_RXTSF_OFFSET_CCK_8814A\t\t0x055E\n#define REG_RXTSF_OFFSET_OFDM_8814A\t\t0x055F\n#define REG_TSFTR_8814A\t\t\t\t\t\t0x0560\n#define REG_CTWND_8814A\t\t\t\t\t0x0572\n#define REG_SECONDARY_CCA_CTRL_8814A\t\t0x0577 /* ?????? */\n#define REG_PSTIMER_8814A\t\t\t\t\t0x0580\n#define REG_TIMER0_8814A\t\t\t\t\t0x0584\n#define REG_TIMER1_8814A\t\t\t\t\t0x0588\n#define REG_BCN_PREDL_ITV_8814A\t\t\t0x058F\t/* Pre download beacon interval */\n#define REG_ACMHWCTRL_8814A\t\t\t\t0x05C0\n#define REG_P2P_RST_8814A\t\t\t\t0x05F0\n\n/* -----------------------------------------------------\n *\n *\t0x0600h ~ 0x07FFh\tWMAC Configuration\n *\n * ----------------------------------------------------- */\n#define REG_MAC_CR_8814A\t\t\t\t\t0x0600\n#define REG_TCR_8814A\t\t\t\t\t\t0x0604\n#define REG_RCR_8814A\t\t\t\t\t\t0x0608\n#define REG_RX_PKT_LIMIT_8814A\t\t\t\t0x060C\n#define REG_RX_DLK_TIME_8814A\t\t\t\t0x060D\n#define REG_RX_DRVINFO_SZ_8814A\t\t\t0x060F\n\n#define REG_MACID_8814A\t\t\t\t\t0x0610\n#define REG_BSSID_8814A\t\t\t\t\t\t0x0618\n#define REG_MAR_8814A\t\t\t\t\t\t0x0620\n#define REG_MBIDCAMCFG_8814A\t\t\t\t0x0628\n\n#define REG_USTIME_EDCA_8814A\t\t\t\t0x0638\n#define REG_MAC_SPEC_SIFS_8814A\t\t\t0x063A\n#define REG_RESP_SIFP_CCK_8814A\t\t\t0x063C\n#define REG_RESP_SIFS_OFDM_8814A\t\t\t0x063E\n#define REG_ACKTO_8814A\t\t\t\t\t0x0640\n#define REG_CTS2TO_8814A\t\t\t\t\t0x0641\n#define REG_EIFS_8814A\t\t\t\t\t\t0x0642\n\n#define\tREG_NAV_UPPER_8814A\t\t\t\t0x0652\t/* unit of 128 */\n#define REG_TRXPTCL_CTL_8814A\t\t\t\t0x0668\n\n/* Security */\n#define REG_CAMCMD_8814A\t\t\t\t\t0x0670\n#define REG_CAMWRITE_8814A\t\t\t\t0x0674\n#define REG_CAMREAD_8814A\t\t\t\t\t0x0678\n#define REG_CAMDBG_8814A\t\t\t\t\t0x067C\n#define REG_SECCFG_8814A\t\t\t\t\t0x0680\n\n/* Power */\n#define REG_WOW_CTRL_8814A\t\t\t\t0x0690\n#define REG_PS_RX_INFO_8814A\t\t\t\t0x0692\n#define REG_UAPSD_TID_8814A\t\t\t\t0x0693\n#define REG_WKFMCAM_NUM_8814A\t\t\t0x0698\n#define REG_RXFLTMAP0_8814A\t\t\t\t0x06A0\n#define REG_RXFLTMAP1_8814A\t\t\t\t0x06A2\n#define REG_RXFLTMAP2_8814A\t\t\t\t0x06A4\n#define REG_BCN_PSR_RPT_8814A\t\t\t\t0x06A8\n#define REG_BT_COEX_TABLE_8814A\t\t\t0x06C0\n#define REG_TX_DATA_RSP_RATE_8814A\t\t0x06DE\n#define REG_ASSOCIATED_BFMER0_INFO_8814A\t0x06E4\n#define REG_ASSOCIATED_BFMER1_INFO_8814A\t0x06EC\n#define REG_CSI_RPT_PARAM_BW20_8814A\t\t0x06F4\n#define REG_CSI_RPT_PARAM_BW40_8814A\t\t0x06F8\n#define REG_CSI_RPT_PARAM_BW80_8814A\t\t0x06FC\n\n/* Hardware Port 2 */\n#define REG_MACID1_8814A\t\t\t\t\t0x0700\n#define REG_BSSID1_8814A\t\t\t\t\t0x0708\n/* Hardware Port 3 */\n#define REG_MACID2_8814A\t\t\t\t\t0x1620\n#define REG_BSSID2_8814A\t\t\t\t\t0x1628\n/* Hardware Port 4 */\n#define REG_MACID3_8814A\t\t\t\t\t0x1630\n#define REG_BSSID3_8814A\t\t\t\t\t0x1638\n/* Hardware Port 5 */\n#define REG_MACID4_8814A\t\t\t\t\t0x1640\n#define REG_BSSID4_8814A\t\t\t\t\t0x1648\n\n#define REG_ASSOCIATED_BFMEE_SEL_8814A\t0x0714\n#define REG_SND_PTCL_CTRL_8814A\t\t\t0x0718\n#define REG_IQ_DUMP_8814A\t\t\t\t\t0x07C0\n\n#define REG_CPU_DMEM_CON_8814A\t\t\t0x1080\n\n/**** page 19 ****/\n/* TX BeamForming */\n#define\tREG_BB_TXBF_ANT_SET_BF1\t\t\t\t0x19ac\n#define\tREG_BB_TXBF_ANT_SET_BF0\t\t\t\t0x19b4\n\n/*\t0x1200h ~ 0x12FFh\tDDMA CTRL\n *\n * ----------------------------------------------------- */\n#define REG_DDMA_CH0SA                   0x1200\n#define REG_DDMA_CH0DA                   0x1204\n#define REG_DDMA_CH0CTRL                0x1208\n#define REG_DDMA_CH1SA                   0x1210\n#define REG_DDMA_CH1DA\t0x1214\n#define REG_DDMA_CH1CTRL                0x1218\n#define REG_DDMA_CH2SA                   0x1220\n#define REG_DDMA_CH2DA                   0x1224\n#define REG_DDMA_CH2CTRL                0x1228\n#define REG_DDMA_CH3SA                   0x1230\n#define REG_DDMA_CH3DA                   0x1234\n#define REG_DDMA_CH3CTRL                0x1238\n#define REG_DDMA_CH4SA                   0x1240\n#define REG_DDMA_CH4DA                   0x1244\n#define REG_DDMA_CH4CTRL                0x1248\n#define REG_DDMA_CH5SA                   0x1250\n#define REG_DDMA_CH5DA                   0x1254\n#define REG_DDMA_CH5CTRL                0x1258\n#define REG_DDMA_INT_MSK                0x12E0\n#define REG_DDMA_CHSTATUS              0x12E8\n#define REG_DDMA_CHKSUM                 0x12F0\n#define REG_DDMA_MONITER                0x12FC\n\n#define REG_Q0_Q1_INFO_8814A\t\t0x1400\n#define REG_Q2_Q3_INFO_8814A\t\t0x1404\n#define REG_Q4_Q5_INFO_8814A\t\t0x1408\n#define REG_Q6_Q7_INFO_8814A\t\t0x140C\n#define REG_MGQ_HIQ_INFO_8814A\t0x1410\n#define REG_CMDQ_BCNQ_INFO_8814A\t0x1414\n\n#define DDMA_LEN_MASK\t\t0x0001FFFF\n#define FW_CHKSUM_DUMMY_SZ\t\t8\n#define DDMA_CH_CHKSUM_CNT\t\tBIT(24)\n#define DDMA_RST_CHKSUM_STS\t\tBIT(25)\n#define DDMA_MODE_BLOCK_CPU\t\tBIT(26)\n#define DDMA_CHKSUM_FAIL\t\t\tBIT(27)\n#define DDMA_DA_W_DISABLE\t\t\tBIT(28)\n#define DDMA_CHKSUM_EN\t\t\tBIT(29)\n#define DDMA_CH_OWN\tBIT(31)\n\n\n/* 3081 FWDL */\n#define FWDL_EN                 BIT0\n#define IMEM_BOOT_DL_RDY        BIT1\n#define IMEM_BOOT_CHKSUM_FAIL   BIT2\n#define IMEM_DL_RDY             BIT3\n#define IMEM_CHKSUM_OK        BIT4\n#define DMEM_DL_RDY             BIT5\n#define DMEM_CHKSUM_OK        BIT6\n#define EMEM_DL_RDY             BIT7\n#define EMEM_CHKSUM_FAIL        BIT8\n#define EMEM_TXBUF_DL_RDY       BIT9\n#define EMEM_TXBUF_CHKSUM_FAIL  BIT10\n#define CPU_CLK_SWITCH_BUSY     BIT11\n#define CPU_CLK_SEL             (BIT12 | BIT13)\n#define FWDL_OK                 BIT14\n#define FW_INIT_RDY             BIT15\n#define R_EN_BOOT_FLASH         BIT20\n\n#define OCPBASE_IMEM_3081        0x00000000\n#define OCPBASE_DMEM_3081        0x00200000\n#define OCPBASE_RPTBUF_3081      0x18660000\n#define OCPBASE_RXBUF2_3081      0x18680000\n#define OCPBASE_RXBUF_3081       0x18700000\n#define OCPBASE_TXBUF_3081       0x18780000\n\n\n#define REG_FAST_EDCA_VOVI_SETTING_8814A 0x1448\n#define REG_FAST_EDCA_BEBK_SETTING_8814A 0x144C\n\n\n/* -----------------------------------------------------\n *   */\n\n\n/* -----------------------------------------------------\n *\n *\tRedifine 8192C register definition for compatibility\n *\n * ----------------------------------------------------- */\n\n/* TODO: use these definition when using REG_xxx naming rule.\n * NOTE: DO NOT Remove these definition. Use later. */\n#define\tEFUSE_CTRL_8814A\t\t\t\t\tREG_EFUSE_CTRL_8814A\t\t/* E-Fuse Control. */\n#define\tEFUSE_TEST_8814A\t\t\t\t\tREG_LDO_EFUSE_CTRL_8814A\t\t/* E-Fuse Test. */\n#define\tMSR_8814A\t\t\t\t\t\t\t(REG_CR_8814A + 2)\t\t/* Media Status register */\n#define\tISR_8814A\t\t\t\t\t\t\tREG_HISR0_8814A\n#define\tTSFR_8814A\t\t\t\t\t\t\tREG_TSFTR_8814A\t\t\t/* Timing Sync Function Timer Register. */\n\n#define PBP_8814A\t\t\t\t\t\t\tREG_PBP_8814A\n\n/* Redifine MACID register, to compatible prior ICs. */\n#define\tIDR0_8814A\t\t\t\t\t\t\tREG_MACID_8814A\t\t\t/* MAC ID Register, Offset 0x0050-0x0053 */\n#define\tIDR4_8814A\t\t\t\t\t\t\t(REG_MACID_8814A + 4)\t/* MAC ID Register, Offset 0x0054-0x0055 */\n\n\n/*\n * 9. Security Control Registers\t(Offset: )\n *   */\n#define\tRWCAM_8814A\t\t\t\t\t\tREG_CAMCMD_8814A\t\t/*  8190 Data Sheet is called CAMcmd */\n#define\tWCAMI_8814A\t\t\t\t\t\tREG_CAMWRITE_8814A\t\t/* Software write CAM input content */\n#define\tRCAMO_8814A\t\t\t\t\t\tREG_CAMREAD_8814A\t\t/* Software read/write CAM config */\n#define\tCAMDBG_8814A\t\t\t\t\t\tREG_CAMDBG_8814A\n#define\tSECR_8814A\t\t\t\t\t\t\tREG_SECCFG_8814A\t\t/* Security Configuration Register */\n\n\n/* ----------------------------------------------------------------------------\n * 8195 IMR/ISR bits\t\t\t\t\t\t(offset 0xB0,  8bits)\n * ---------------------------------------------------------------------------- */\n#define\tIMR_DISABLED_8814A\t\t\t\t\t0\n/* IMR DW0(0x00B0-00B3) Bit 0-31 */\n#define\tIMR_TIMER2_8814A\t\t\t\t\tBIT31\t\t/* Timeout interrupt 2 */\n#define\tIMR_TIMER1_8814A\t\t\t\t\tBIT30\t\t/* Timeout interrupt 1\t */\n#define\tIMR_PSTIMEOUT_8814A\t\t\t\tBIT29\t\t/* Power Save Time Out Interrupt */\n#define\tIMR_GTINT4_8814A\t\t\t\t\tBIT28\t\t/* When GTIMER4 expires, this bit is set to 1\t */\n#define\tIMR_GTINT3_8814A\t\t\t\t\tBIT27\t\t/* When GTIMER3 expires, this bit is set to 1\t */\n#define\tIMR_TXBCN0ERR_8814A\t\t\t\tBIT26\t\t/* Transmit Beacon0 Error\t\t\t */\n#define\tIMR_TXBCN0OK_8814A\t\t\t\t\tBIT25\t\t/* Transmit Beacon0 OK\t\t\t */\n#define\tIMR_TSF_BIT32_TOGGLE_8814A\t\tBIT24\t\t/* TSF Timer BIT32 toggle indication interrupt\t\t\t */\n#define\tIMR_BCNDMAINT0_8814A\t\t\t\tBIT20\t\t/* Beacon DMA Interrupt 0\t\t\t */\n#define\tIMR_BCNDERR0_8814A\t\t\t\t\tBIT16\t\t/* Beacon Queue DMA OK0\t\t\t */\n#define\tIMR_HSISR_IND_ON_INT_8814A\t\tBIT15\t\t/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */\n#define\tIMR_BCNDMAINT_E_8814A\t\t\t\tBIT14\t\t/* Beacon DMA Interrupt Extension for Win7\t\t\t */\n#define\tIMR_ATIMEND_8814A\t\t\t\t\tBIT12\t\t/* CTWidnow End or ATIM Window End */\n#define\tIMR_C2HCMD_8814A\t\t\t\t\tBIT10\t\t/* CPU to Host Command INT Status, Write 1 clear\t */\n#define\tIMR_CPWM2_8814A\t\t\t\t\tBIT9\t\t\t/* CPU power Mode exchange INT Status, Write 1 clear\t */\n#define\tIMR_CPWM_8814A\t\t\t\t\t\tBIT8\t\t\t/* CPU power Mode exchange INT Status, Write 1 clear\t */\n#define\tIMR_HIGHDOK_8814A\t\t\t\t\tBIT7\t\t\t/* High Queue DMA OK\t */\n#define\tIMR_MGNTDOK_8814A\t\t\t\t\tBIT6\t\t\t/* Management Queue DMA OK\t */\n#define\tIMR_BKDOK_8814A\t\t\t\t\tBIT5\t\t\t/* AC_BK DMA OK\t\t */\n#define\tIMR_BEDOK_8814A\t\t\t\t\tBIT4\t\t\t/* AC_BE DMA OK\t */\n#define\tIMR_VIDOK_8814A\t\t\t\t\tBIT3\t\t\t/* AC_VI DMA OK\t\t */\n#define\tIMR_VODOK_8814A\t\t\t\t\tBIT2\t\t\t/* AC_VO DMA OK\t */\n#define\tIMR_RDU_8814A\t\t\t\t\t\tBIT1\t\t\t/* Rx Descriptor Unavailable\t */\n#define\tIMR_ROK_8814A\t\t\t\t\t\tBIT0\t\t\t/* Receive DMA OK */\n\n/* IMR DW1(0x00B4-00B7) Bit 0-31 */\n#define\tIMR_MCUERR_8814A\t\t\t\t\t\tBIT28\t\t/* Beacon DMA Interrupt 7 */\n#define\tIMR_BCNDMAINT7_8814A\t\t\t\tBIT27\t\t/* Beacon DMA Interrupt 7 */\n#define\tIMR_BCNDMAINT6_8814A\t\t\t\tBIT26\t\t/* Beacon DMA Interrupt 6 */\n#define\tIMR_BCNDMAINT5_8814A\t\t\t\tBIT25\t\t/* Beacon DMA Interrupt 5 */\n#define\tIMR_BCNDMAINT4_8814A\t\t\t\tBIT24\t\t/* Beacon DMA Interrupt 4 */\n#define\tIMR_BCNDMAINT3_8814A\t\t\t\tBIT23\t\t/* Beacon DMA Interrupt 3 */\n#define\tIMR_BCNDMAINT2_8814A\t\t\t\tBIT22\t\t/* Beacon DMA Interrupt 2 */\n#define\tIMR_BCNDMAINT1_8814A\t\t\t\tBIT21\t\t/* Beacon DMA Interrupt 1 */\n#define\tIMR_BCNDOK7_8814A\t\t\t\t\tBIT20\t\t/* Beacon Queue DMA OK Interrup 7 */\n#define\tIMR_BCNDOK6_8814A\t\t\t\t\tBIT19\t\t/* Beacon Queue DMA OK Interrup 6 */\n#define\tIMR_BCNDOK5_8814A\t\t\t\t\tBIT18\t\t/* Beacon Queue DMA OK Interrup 5 */\n#define\tIMR_BCNDOK4_8814A\t\t\t\t\tBIT17\t\t/* Beacon Queue DMA OK Interrup 4 */\n#define\tIMR_BCNDOK3_8814A\t\t\t\t\tBIT16\t\t/* Beacon Queue DMA OK Interrup 3 */\n#define\tIMR_BCNDOK2_8814A\t\t\t\t\tBIT15\t\t/* Beacon Queue DMA OK Interrup 2 */\n#define\tIMR_BCNDOK1_8814A\t\t\t\t\tBIT14\t\t/* Beacon Queue DMA OK Interrup 1 */\n#define\tIMR_ATIMEND_E_8814A\t\t\t\tBIT13\t\t/* ATIM Window End Extension for Win7 */\n#define\tIMR_TXERR_8814A\t\t\t\t\tBIT11\t\t/* Tx Error Flag Interrupt Status, write 1 clear. */\n#define\tIMR_RXERR_8814A\t\t\t\t\tBIT10\t\t/* Rx Error Flag INT Status, Write 1 clear */\n#define\tIMR_TXFOVW_8814A\t\t\t\t\tBIT9\t\t\t/* Transmit FIFO Overflow */\n#define\tIMR_RXFOVW_8814A\t\t\t\t\tBIT8\t\t\t/* Receive FIFO Overflow */\n\n\n#ifdef CONFIG_PCI_HCI\n\t#define IMR_TX_MASK\t\t\t(IMR_VODOK_8814A | IMR_VIDOK_8814A | IMR_BEDOK_8814A | IMR_BKDOK_8814A | IMR_MGNTDOK_8814A | IMR_HIGHDOK_8814A)\n\n\t#define RT_BCN_INT_MASKS\t(IMR_BCNDMAINT0_8814A | IMR_TXBCN0OK_8814A | IMR_TXBCN0ERR_8814A | IMR_BCNDERR0_8814A)\n\n\t#define RT_AC_INT_MASKS\t(IMR_VIDOK_8814A | IMR_VODOK_8814A | IMR_BEDOK_8814A | IMR_BKDOK_8814A)\n#endif\n\n\n/*===================================================================\n=====================================================================\nHere the register defines are for 92C. When the define is as same with 92C,\nwe will use the 92C's define for the consistency\nSo the following defines for 92C is not entire!!!!!!\n=====================================================================\n=====================================================================*/\n\n\n/* -----------------------------------------------------\n *\n *\t0xFE00h ~ 0xFE55h\tUSB Configuration\n *\n * ----------------------------------------------------- */\n\n/* 2 Special Option */\n#define USB_AGG_EN_8814A\t\t\tBIT(7)\n#define REG_USB_HRPWM_U3\t\t\t0xF052\n\n#define LAST_ENTRY_OF_TX_PKT_BUFFER_8814A       (2048-1)\t/* 20130415 KaiYuan add for 8814 */\n\n#endif /* __RTL8814A_SPEC_H__ */\n"
  },
  {
    "path": "include/rtl8814a_sreset.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL88814A_SRESET_H_\n#define _RTL8814A_SRESET_H_\n\n#include <rtw_sreset.h>\n\n#ifdef DBG_CONFIG_ERROR_DETECT\n\textern void rtl8814_sreset_xmit_status_check(_adapter *padapter);\n\textern void rtl8814_sreset_linked_status_check(_adapter *padapter);\n#endif\n#endif\n"
  },
  {
    "path": "include/rtl8814a_xmit.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8814A_XMIT_H__\n#define __RTL8814A_XMIT_H__\n\ntypedef struct txdescriptor_8814 {\n\t/* Offset 0 */\n\tu32 pktlen:16;\n\tu32 offset:8;\n\tu32 bmc:1;\n\tu32 htc:1;\n\tu32 ls:1;\n} TXDESC_8814, *PTXDESC_8814;\n\n\n#define OFFSET_SZ\t0\n#define OFFSET_SHT\t16\n\n\n\n#ifdef CONFIG_SDIO_HCI\n\t#define SET_TX_DESC_SDIO_TXSEQ_8814A(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)\n#endif /* CONFIG_SDIO_HCI */\n\n/* -----------------------------------------------------------------\n *\tRTL8814A TX BUFFER DESC\n * -----------------------------------------------------------------\n *\n- Each TXBD has 4 segment.\n -- For 32 bit, each segment is 8 bytes.\n -- For 64 bit, each segment is 16 bytes.\n*/\n#if 0\n\t#if 1 /* 32 bit */\n\t\t#define SET_TX_EXTBUFF_DESC_LEN_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*8), 0, 16, __Value)\n\t\t#define SET_TX_EXTBUFF_DESC_ADDR_LOW_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*8)+4, 0, 32, __Value)\n\t#else /* 64 bit */\n\t\t#define SET_TX_EXTBUFF_DESC_LEN_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*16), 0, 16, __Value)\n\t\t#define SET_TX_EXTBUFF_DESC_ADDR_LOW_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*16)+4, 0, 32, __Value)\n\t#endif\n\t#define SET_TX_EXTBUFF_DESC_ADDR_HIGH_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*16)+8, 0, 32, __Value)\n#endif\n/*c2h-DWORD 2*/\n#define GET_RX_STATUS_DESC_RPT_SEL_8814A(__pRxDesc)\t\t\tLE_BITS_TO_4BYTE(__pRxDesc+8, 28, 1)\n\n/* *********************************************************\n * for Txfilldescroptor8814Ae, fill the desc content. */\n#if 1 /* 32 bit */\n\t#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*8), 0, 16, __Valeu)\n\t#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*8), 31, 1, __Valeu)\n\t#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*8)+4, 0, 32, __Valeu)\n#else /* 64 bit */\n\t#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)\n\t#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)\n\t#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)\n#endif\n#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)\n\n/* ********************************************************* */\n\n/* TX buffer\n * *************\n * Dword 0 */\n#define SET_TX_BUFF_DESC_LEN_0_8814A(__pTxDesc, __Valeu)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Valeu)\n#define SET_TX_BUFF_DESC_PSB_8814A(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)\n#define SET_TX_BUFF_DESC_OWN_8814A(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)\n#define GET_TX_BUFF_DESC_OWN_8814A(__pTxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pTxDesc, 31, 1)\n\n/* Dword 1 */\n#define SET_TX_BUFF_DESC_ADDR_LOW_0_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)\n#define GET_TX_BUFF_DESC_ADDR_LOW_0_8814A(__pTxDesc)\t\t\tLE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)\n/* Dword 2 */\n#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 32, __Value)\n#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8814A(__pTxDesc)\t\t\tLE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)\n/* Dword 3 */ /* RESERVED 0 */\n\n#if 0 /* 64 bit */\n\t/* Dword 4 */\n\t#define SET_TX_BUFF_DESC_LEN_1_8814A(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 16, __Value)\n\t#define SET_TX_BUFF_DESC_AMSDU_1_8814A(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+16, 31, 1, __Value)\n\t/* Dword 5 */\n\t#define SET_TX_BUFF_DESC_ADDR_LOW_1_8814A(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 32, __Value)\n\t/* Dword 6 */\n\t#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8814A(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 32, __Value)\n\t/* Dword 7 */ /* RESERVED 0 */\n\t/* Dword 8 */\n\t#define SET_TX_BUFF_DESC_LEN_2_8814A(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 16, __Value)\n\t#define SET_TX_BUFF_DESC_AMSDU_2_8814A(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 31, 1, __Value)\n\t/* Dword 9 */\n\t#define SET_TX_BUFF_DESC_ADDR_LOW_2_8814A(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 32, __Value)\n\t/* Dword 10 */\n\t#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8814A(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)\n\t/* Dword 11 */ /* RESERVED 0 */\n\t/* Dword 12 */\n\t#define SET_TX_BUFF_DESC_LEN_3_8814A(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 16, __Value)\n\t#define SET_TX_BUFF_DESC_AMSDU_3_8814A(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+48, 31, 1, __Value)\n\t/* Dword 13 */\n\t#define SET_TX_BUFF_DESC_ADDR_LOW_3_8814A(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+52, 0, 32, __Value)\n\t/* Dword 14 */\n\t#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8814A(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+56, 0, 32, __Value)\n\t/* Dword 15 */ /* RESERVED 0 */\n#endif\n\n/* *****Desc content\n * TX Info\n * *************\n * Dword 0 */\n#define SET_TX_DESC_PKT_SIZE_8814A(__pTxDesc, __Value)\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)\n#define GET_TX_DESC_PKT_SIZE_8814A(__pTxDesc)\t\t\t\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pTxDesc, 0, 16)\n#define SET_TX_DESC_OFFSET_8814A(__pTxDesc, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)\n#define GET_TX_DESC_OFFSET_8814A(__pTxDesc)\t\t\t\t\t\t\t\t\tLE_BITS_TO_4BYTE(__pTxDesc, 16, 8)\n#define SET_TX_DESC_BMC_8814A(__pTxDesc, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)\n#define SET_TX_DESC_HTC_8814A(__pTxDesc, __Value)\t\t\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)\n#define SET_TX_DESC_LAST_SEG_8814A(__pTxDesc, __Value)\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)\n#define SET_TX_DESC_LINIP_8814A(__pTxDesc, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)\n#define SET_TX_DESC_AMSDU_PAD_EN_8814A(__pTxDesc, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)\n#define SET_TX_DESC_NO_ACM_8814A(__pTxDesc, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)\n#define SET_TX_DESC_GF_8814A(__pTxDesc, __Value)\t\t\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)\n#define SET_TX_DESC_DISQSELSEQ_8814A(__pTxDesc, __Value)\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)\n\n/* Dword 1 */\n#define SET_TX_DESC_MACID_8814A(__pTxDesc, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)\n#define SET_TX_DESC_QUEUE_SEL_8814A(__pTxDesc, __Value)\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)\n#define SET_TX_DESC_RDG_NAV_EXT_8814A(__pTxDesc, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)\n#define SET_TX_DESC_LSIG_TXOP_EN_8814A(__pTxDesc, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)\n#define SET_TX_DESC_PIFS_8814A(__pTxDesc, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)\n#define SET_TX_DESC_RATE_ID_8814A(__pTxDesc, __Value)\t\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)\n#define SET_TX_DESC_EN_DESC_ID_8814A(__pTxDesc, __Value)\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)\n#define SET_TX_DESC_SEC_TYPE_8814A(__pTxDesc, __Value)\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)\n#define SET_TX_DESC_PKT_OFFSET_8814A(__pTxDesc, __Value)\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)\n#define SET_TX_DESC_MORE_DATA_8814A(__pTxDesc, __Value)\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)\n#define SET_TX_DESC_TXOP_PS_CAP_8814A(__pTxDesc, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 30, 1, __Value)\n#define SET_TX_DESC_TXOP_PS_MODE_8814A(__pTxDesc, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+4, 31, 1, __Value)\n\n\n/* Dword 2 */\n#define SET_TX_DESC_PAID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)\n#define SET_TX_DESC_CCA_RTS_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)\n#define SET_TX_DESC_AGG_ENABLE_8814A(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)\n#define SET_TX_DESC_RDG_ENABLE_8814A(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)\n#define SET_TX_DESC_NULL_0_8814A(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)\n#define SET_TX_DESC_NULL_1_8814A(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)\n#define SET_TX_DESC_BK_8814A(__pTxDesc, __Value)\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)\n#define SET_TX_DESC_MORE_FRAG_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)\n#define GET_TX_DESC_MORE_FRAG_8814A(__pTxDesc)\t\t\t\tLE_BITS_TO_4BYTE(__pTxDesc+8, 17, 1)\n#define SET_TX_DESC_RAW_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)\n#define SET_TX_DESC_SPE_RPT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)\n#define SET_TX_DESC_AMPDU_DENSITY_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)\n#define SET_TX_DESC_BT_NULL_8814A(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)\n#define SET_TX_DESC_GID_8814A(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)\n#define SET_TX_DESC_HW_AES_IV_8814A(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+8, 31, 1, __Value)\n\n\n/* Dword 3 */\n#define SET_TX_DESC_WHEADER_LEN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 5, __Value)\n#define SET_TX_DESC_EARLY_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)\n#define SET_TX_DESC_HW_SSN_SEL_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)\n#define SET_TX_DESC_USE_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)\n#define SET_TX_DESC_DISABLE_RTS_FB_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)\n#define SET_TX_DESC_DISABLE_FB_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)\n#define SET_TX_DESC_CTS2SELF_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)\n#define SET_TX_DESC_RTS_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)\n#define SET_TX_DESC_HW_RTS_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)\n#define SET_TX_DESC_CHECK_EN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value)\n#define SET_TX_DESC_NAV_USE_HDR_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)\n#define SET_TX_DESC_USE_MAX_LEN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)\n#define SET_TX_DESC_MAX_AGG_NUM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)\n#define SET_TX_DESC_NDPA_8814A(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)\n#define SET_TX_DESC_AMPDU_MAX_TIME_8814A(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)\n\n/* Dword 4 */\n#define SET_TX_DESC_TX_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)\n#define SET_TX_DESC_TRY_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)\n#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)\n#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)\n#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)\n#define SET_TX_DESC_DATA_RETRY_LIMIT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)\n#define SET_TX_DESC_RTS_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)\n#define SET_TX_DESC_PCTS_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)\n#define SET_TX_DESC_PCTS_MASK_IDX_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)\n\n\n/* Dword 5 */\n#define SET_TX_DESC_DATA_SC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)\n#define SET_TX_DESC_DATA_SHORT_8814A(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)\n#define SET_TX_DESC_DATA_BW_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)\n#define SET_TX_DESC_DATA_LDPC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)\n#define SET_TX_DESC_DATA_STBC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)\n#define SET_TX_DESC_CTROL_STBC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)\n#define SET_TX_DESC_RTS_SHORT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)\n#define SET_TX_DESC_RTS_SC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)\n#define SET_TX_DESC_SIGNALING_TA_PKT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 17, 1, __Value)\n#define SET_TX_DESC_PORT_ID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 21, 3, __Value)/* 20130415 KaiYuan add for 8814 */\n#define SET_TX_DESC_TX_ANT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value)\n#define SET_TX_DESC_TX_POWER_OFFSET_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)\n\n/* Dword 6 */\n#define SET_TX_DESC_SW_DEFINE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)\n#define SET_TX_DESC_MBSSID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)\n#define SET_TX_DESC_ANTSEL_A_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)\n#define SET_TX_DESC_ANTSEL_B_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)\n#define SET_TX_DESC_ANT_MAPA_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 2, __Value)\n#define SET_TX_DESC_ANT_MAPB_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 24, 2, __Value)\n#define SET_TX_DESC_ANT_MAPC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 26, 2, __Value)\n#define SET_TX_DESC_ANT_MAPD_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 28, 2, __Value)\n\n\n/* Dword 7 */\n#ifdef CONFIG_PCI_HCI\n\t#define SET_TX_DESC_TX_BUFFER_SIZE_8814A(__pTxDesc, __Value)\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n#endif\n#if defined(CONFIG_SDIO_HCI)|| defined(CONFIG_USB_HCI)\n\t#define SET_TX_DESC_TX_DESC_CHECKSUM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)\n#endif\n#define SET_TX_DESC_NTX_MAP_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 20, 4, __Value)\n#define SET_TX_DESC_USB_TXAGG_NUM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)\n\n\n/* Dword 8 */\n#define SET_TX_DESC_RTS_RC_8814A(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)\n#define SET_TX_DESC_BAR_RTY_TH_8814A(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)\n#define SET_TX_DESC_DATA_RC_8814A(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)\n#define SET_TX_DESC_EN_HWEXSEQ_8814A(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 14, 1, __Value)\n#define SET_TX_DESC_HWSEQ_EN_8814A(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)\n#if defined(CONFIG_PCI_HCI)|| defined(CONFIG_USB_HCI)\n\t#define SET_TX_DESC_NEXT_HEAD_PAGE_L_8814A(__pTxDesc, __Value)(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)\n#endif\n#ifdef CONFIG_SDIO_HCI\n\t#define SET_TX_DESC_SDIO_SEQ_8814A(__pTxDesc, __Value)(__pTxDesc, __Value) \t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value) /* 20130415 KaiYuan add for 8814AS */\n#endif\n#define SET_TX_DESC_TAIL_PAGE_L_8814A(__pTxDesc, __Value)(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)\n\n/* Dword 9 */\n#define SET_TX_DESC_PADDING_LENGTH_8814A(__pTxDesc, __Value)\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)\n#define SET_TX_DESC_TXBF_PATH_8814A(__pTxDesc, __Value)\t\t\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 11, 1, __Value)\n#define SET_TX_DESC_SEQ_8814A(__pTxDesc, __Value)\t\t\t\t\t\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)\n#define SET_TX_DESC_NEXT_HEAD_PAGE_H_8814A(__pTxDesc, __Value)(__pTxDesc, __Value)\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 4, __Value)\n#define SET_TX_DESC_TAIL_PAGE_H_8814A(__pTxDesc, __Value)(__pTxDesc, __Value)\t\t\tSET_BITS_TO_LE_4BYTE(__pTxDesc+36, 28, 4, __Value)\n\n\n\n#define SET_EARLYMODE_PKTNUM_8814A(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)\n#define SET_EARLYMODE_LEN0_8814A(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)\n#define SET_EARLYMODE_LEN1_1_8814A(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)\n#define SET_EARLYMODE_LEN1_2_8814A(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)\n#define SET_EARLYMODE_LEN2_8814A(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,  __Value)\n#define SET_EARLYMODE_LEN3_8814A(__pAddr, __Value)\t\t\t\t\tSET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)\n\n\nvoid rtl8814a_cal_txdesc_chksum(u8 *ptxdesc);\nvoid rtl8814a_fill_fake_txdesc(PADAPTER\tpadapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8\tIsBTQosNull, u8 bDataFrame);\nvoid rtl8814a_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc);\nvoid rtl8814a_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);\nvoid rtl8814a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);\n#if defined(CONFIG_CONCURRENT_MODE)\n\tvoid fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);\n#endif\nvoid fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);\n\n#ifdef CONFIG_USB_HCI\n\ts32 rtl8814au_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8814au_free_xmit_priv(PADAPTER padapter);\n\ts32 rtl8814au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8814au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\t rtl8814au_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8814au_xmit_buf_handler(PADAPTER padapter);\n\tvoid rtl8814au_xmit_tasklet(void *priv);\n\ts32 rtl8814au_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\n#endif /* CONFIG_USB_HCI */\n\n#ifdef CONFIG_PCI_HCI\n\ts32 rtl8814ae_init_xmit_priv(PADAPTER padapter);\n\tvoid rtl8814ae_free_xmit_priv(PADAPTER padapter);\n\tstruct xmit_buf *rtl8814ae_dequeue_xmitbuf(struct rtw_tx_ring *ring);\n\tvoid rtl8814ae_xmitframe_resume(_adapter *padapter);\n\ts32 rtl8814ae_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\n\ts32 rtl8814ae_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\n\ts32\trtl8814ae_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\n\tvoid rtl8814ae_xmit_tasklet(void *priv);\n#ifdef CONFIG_XMIT_THREAD_MODE\n\ts32 rtl8814ae_xmit_buf_handler(_adapter *padapter);\n#endif\n#endif\n\nvoid _dbg_dump_tx_info(_adapter\t*padapter, int frame_tag, u8 *ptxdesc);\nu8\nSCMapping_8814(\n\t\tPADAPTER\t\tAdapter,\n\t\tstruct pkt_attrib\t*pattrib\n);\n\nu8\nBWMapping_8814(\n\t\tPADAPTER\t\tAdapter,\n\t\tstruct pkt_attrib\t*pattrib\n);\n\n\n#endif /* __RTL8814_XMIT_H__ */\n"
  },
  {
    "path": "include/rtl8821a_spec.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8821A_SPEC_H__\n#define __RTL8821A_SPEC_H__\n\n#include <drv_conf.h>\n/* This file should based on \"hal_com_reg.h\" */\n#include <hal_com_reg.h>\n/* Because 8812a and 8821a is the same serial,\n * most of 8821a register definitions are the same as 8812a. */\n#include <rtl8812a_spec.h>\n\n\n/* ************************************************************\n * 8821A Regsiter offset definition\n * ************************************************************ */\n\n/* ************************************************************\n * MAC register\n * ************************************************************ */\n\n/* -----------------------------------------------------\n *\t0x0000h ~ 0x00FFh\tSystem Configuration\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n *\t0x0100h ~ 0x01FFh\tMACTOP General Configuration\n * ----------------------------------------------------- */\n#define REG_WOWLAN_WAKE_REASON          REG_MCUTST_WOWLAN\n\n/* -----------------------------------------------------\n *\t0x0200h ~ 0x027Fh\tTXDMA Configuration\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n *\t0x0280h ~ 0x02FFh\tRXDMA Configuration\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n *\t0x0300h ~ 0x03FFh\tPCIe\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n *\t0x0400h ~ 0x047Fh\tProtocol Configuration\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n *\t0x0500h ~ 0x05FFh\tEDCA Configuration\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n *\t0x0600h ~ 0x07FFh\tWMAC Configuration\n * ----------------------------------------------------- */\n\n\n/* ************************************************************\n * SDIO Bus Specification\n * ************************************************************ */\n\n/* -----------------------------------------------------\n * SDIO CMD Address Mapping\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n * I/O bus domain (Host)\n * ----------------------------------------------------- */\n\n/* -----------------------------------------------------\n * SDIO register\n * ----------------------------------------------------- */\n#define SDIO_REG_FREE_TXPG2\t\t0x024\n#define SDIO_REG_HCPWM1_8821A\t0x025\n\n/* ************************************************************\n * Regsiter Bit and Content definition\n * ************************************************************ */\n\n#endif /* __RTL8821A_SPEC_H__ */\n"
  },
  {
    "path": "include/rtl8821a_xmit.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8821A_XMIT_H__\n#define __RTL8821A_XMIT_H__\n\n#include <drv_types.h>\n\ntypedef struct txdescriptor_8821a {\n\t/* Offset 0 */\n\tu32 pktlen:16;\n\tu32 offset:8;\n\tu32 bmc:1;\n\tu32 htc:1;\n\tu32 rsvd0026:1;\n\tu32 rsvd0027:1;\n\tu32 linip:1;\n\tu32 noacm:1;\n\tu32 gf:1;\n\tu32 rsvd0031:1;\n\n\t/* Offset 4 */\n\tu32 macid:7;\n\tu32 rsvd0407:1;\n\tu32 qsel:5;\n\tu32 rdg_nav_ext:1;\n\tu32 lsig_txop_en:1;\n\tu32 pifs:1;\n\tu32 rate_id:5;\n\tu32 en_desc_id:1;\n\tu32 sectype:2;\n\tu32 pkt_offset:5; /* unit: 8 bytes */\n\tu32 moredata:1;\n\tu32 txop_ps_cap:1;\n\tu32 txop_ps_mode:1;\n\n\t/* Offset 8 */\n\tu32 p_aid:9;\n\tu32 rsvd0809:1;\n\tu32 cca_rts:2;\n\tu32 agg_en:1;\n\tu32 rdg_en:1;\n\tu32 null_0:1;\n\tu32 null_1:1;\n\tu32 bk:1;\n\tu32 morefrag:1;\n\tu32 raw:1;\n\tu32 spe_rpt:1;\n\tu32 ampdu_density:3;\n\tu32 bt_null:1;\n\tu32 g_id:6;\n\tu32 rsvd0830:2;\n\n\t/* Offset 12 */\n\tu32 wheader_len:4;\n\tu32 chk_en:1;\n\tu32 early_rate:1;\n\tu32 hw_ssn_sel:2;\n\tu32 userate:1;\n\tu32 disrtsfb:1;\n\tu32 disdatafb:1;\n\tu32 cts2self:1;\n\tu32 rtsen:1;\n\tu32 hw_rts_en:1;\n\tu32 port_id:1;\n\tu32 navusehdr:1;\n\tu32 use_max_len:1;\n\tu32 max_agg_num:5;\n\tu32 ndpa:2;\n\tu32 ampdu_max_time:8;\n\n\t/* Offset 16 */\n\tu32 datarate:7;\n\tu32 try_rate:1;\n\tu32 data_ratefb_lmt:5;\n\tu32 rts_ratefb_lmt:4;\n\tu32 rty_lmt_en:1;\n\tu32 data_rt_lmt:6;\n\tu32 rtsrate:5;\n\tu32 pcts_en:1;\n\tu32 pcts_mask_idx:2;\n\n\t/* Offset 20 */\n\tu32 data_sc:4;\n\tu32 data_short:1;\n\tu32 data_bw:2;\n\tu32 data_ldpc:1;\n\tu32 data_stbc:2;\n\tu32 vcs_stbc:2;\n\tu32 rts_short:1;\n\tu32 rts_sc:4;\n\tu32 rsvd2016:7;\n\tu32 tx_ant:4;\n\tu32 txpwr_offset:3;\n\tu32 rsvd2031:1;\n\n\t/* Offset 24 */\n\tu32 sw_define:12;\n\tu32 mbssid:4;\n\tu32 antsel_A:3;\n\tu32 antsel_B:3;\n\tu32 antsel_C:3;\n\tu32 antsel_D:3;\n\tu32 rsvd2428:4;\n\n\t/* Offset 28 */\n\tu32 checksum:16;\n\tu32 rsvd2816:8;\n\tu32 usb_txagg_num:8;\n\n\t/* Offset 32 */\n\tu32 rts_rc:6;\n\tu32 bar_rty_th:2;\n\tu32 data_rc:6;\n\tu32 rsvd3214:1;\n\tu32 en_hwseq:1;\n\tu32 nextneadpage:8;\n\tu32 tailpage:8;\n\n\t/* Offset 36 */\n\tu32 padding_len:11;\n\tu32 txbf_path:1;\n\tu32 seq:12;\n\tu32 final_data_rate:8;\n} TXDESC_8821A, *PTXDESC_8821A;\n\n#ifdef CONFIG_SDIO_HCI\ns32 InitXmitPriv8821AS(PADAPTER padapter);\nvoid FreeXmitPriv8821AS(PADAPTER padapter);\ns32 XmitBufHandler8821AS(PADAPTER padapter);\ns32 MgntXmit8821AS(PADAPTER padapter, struct xmit_frame *pmgntframe);\ns32\tHalXmitNoLock8821AS(PADAPTER padapter, struct xmit_frame *pxmitframe);\ns32 HalXmit8821AS(PADAPTER padapter, struct xmit_frame *pxmitframe);\n#ifndef CONFIG_SDIO_TX_TASKLET\nthread_return XmitThread8821AS(thread_context context);\n#endif /* !CONFIG_SDIO_TX_TASKLET */\n#endif /* CONFIG_SDIO_HCI */\n\n#if 0\n#ifdef CONFIG_USB_HCI\ns32 rtl8821au_init_xmit_priv(PADAPTER padapter);\nvoid rtl8821au_free_xmit_priv(PADAPTER padapter);\ns32 rtl8821au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\ns32 rtl8821au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\ns32 rtl8821au_hal_xmitframe_enqueue(PADAPTER padapter, struct xmit_frame *pxmitframe);\ns32 rtl8821au_xmit_buf_handler(PADAPTER padapter);\nvoid rtl8821au_xmit_tasklet(void *priv);\ns32 rtl8821au_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\n#endif /* CONFIG_USB_HCI */\n\n#ifdef CONFIG_PCI_HCI\ns32 rtl8821e_init_xmit_priv(PADAPTER padapter);\nvoid rtl8821e_free_xmit_priv(PADAPTER padapter);\nstruct xmit_buf *rtl8821e_dequeue_xmitbuf(struct rtw_tx_ring *ring);\nvoid rtl8821e_xmitframe_resume(PADAPTER padapter);\ns32 rtl8821e_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);\ns32 rtl8821e_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);\nvoid rtl8821e_xmit_tasklet(void *priv);\n#endif /* CONFIG_PCI_HCI */\n#endif\n\n#endif /* __RTL8821_XMIT_H__ */\n"
  },
  {
    "path": "include/rtl8821c_dm.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8812C_DM_H__\n#define __RTL8812C_DM_H__\n\nvoid rtl8821c_phy_init_dm_priv(PADAPTER);\nvoid rtl8821c_phy_deinit_dm_priv(PADAPTER);\nvoid rtl8821c_phy_init_haldm(PADAPTER);\nvoid rtl8821c_phy_haldm_watchdog(PADAPTER);\n\n#endif\n"
  },
  {
    "path": "include/rtl8821c_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8821C_HAL_H_\n#define _RTL8821C_HAL_H_\n\n#include <osdep_service.h>\t\t/* BIT(x) */\n#include \"../hal/halmac/halmac_api.h\"\t/* MAC REG definition */\n#include \"hal_data.h\"\n#include \"rtl8821c_spec.h\"\n#include \"../hal/rtl8821c/hal8821c_fw.h\"\n\n#ifdef CONFIG_USB_HCI\n#include <rtl8821cu_hal.h>\n#endif\n#ifdef CONFIG_SDIO_HCI\n#include <rtl8821cs_hal.h>\n#endif\n#ifdef CONFIG_PCI_HCI\n#include <rtl8821ce_hal.h>\n#endif\n\n#ifdef CONFIG_SUPPORT_TRX_SHARED\n#define FIFO_BLOCK_SIZE\t\t32768 /*@Block size = 32K*/\n#define RX_FIFO_EXPANDING\t(1 * FIFO_BLOCK_SIZE)\n#else\n#define RX_FIFO_EXPANDING\t0\n#endif\n\n\n#if defined(CONFIG_USB_HCI)\n\n\t#ifndef MAX_RECVBUF_SZ\n\t\t#ifndef CONFIG_MINIMAL_MEMORY_USAGE\n\t\t\t/* 8821C - RX FIFO :16K ,for RX agg DMA mode = 16K, Rx agg USB mode could large than 16k*/\n\t\t\t/* #define MAX_RECVBUF_SZ\t\t(16384 + RX_FIFO_EXPANDING)*/\n\t\t\t/* For Max throughput issue , need to use USB AGG mode to replace DMA AGG mode*/\n\t\t\t#define MAX_RECVBUF_SZ (32768)\n\n\t\t\t/*#define MAX_RECVBUF_SZ_8821C (24576)*/ /* 24k*/\n\t\t\t/*#define MAX_RECVBUF_SZ_8821C (20480)*/ /*20K*/\n\t\t\t/*#define MAX_RECVBUF_SZ_8821C (10240) */ /*10K*/\n\t\t\t/*#define MAX_RECVBUF_SZ_8821C (15360)*/ /*15k < 16k*/\n\t\t\t/*#define MAX_RECVBUF_SZ_8821C (8192+1024)*/ /* 8K+1k*/\n\t\t#else\n\t\t\t#define MAX_RECVBUF_SZ (4096 + RX_FIFO_EXPANDING) /* about 4K */\n\t\t#endif\n\t#endif/* !MAX_RECVBUF_SZ*/\n\n#elif defined(CONFIG_PCI_HCI)\n\t/*#ifndef CONFIG_MINIMAL_MEMORY_USAGE\n\t#define MAX_RECVBUF_SZ (9100)\n\t#else*/\n\t#define MAX_RECVBUF_SZ (4096 + RX_FIFO_EXPANDING) /* about 4K */\n\t/*#endif*/\n\n#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t#define MAX_RECVBUF_SZ\t(16384 + RX_FIFO_EXPANDING)\n#endif\n\nvoid init_hal_spec_rtl8821c(PADAPTER);\n/* MP Functions */\n#ifdef CONFIG_MP_INCLUDED\nvoid rtl8821c_prepare_mp_txdesc(PADAPTER, struct mp_priv *);\t/* rtw_mp.c */\nvoid rtl8821c_mp_config_rfpath(PADAPTER);\t\t\t/* hal_mp.c */\n#endif\nvoid rtl8821c_dl_rsvd_page(PADAPTER adapter, u8 mstatus);\n\n#ifdef CONFIG_PCI_HCI\nu16 get_txbd_rw_reg(u16 q_idx);\n#endif\n\n#endif /* _RTL8821C_HAL_H_ */\n"
  },
  {
    "path": "include/rtl8821c_spec.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTL8821C_SPEC_H__\n#define __RTL8821C_SPEC_H__\n\n#define EFUSE_MAP_SIZE\t\tHALMAC_EFUSE_SIZE_8821C\n\n/*\n * MAC Register definition\n */\n#define REG_AFE_XTAL_CTRL\t\t\tREG_AFE_CTRL1_8821C\t/* hal_com.c & phydm */\n#define REG_AFE_PLL_CTRL\t\t\tREG_AFE_CTRL2_8821C\t/* hal_com.c & phydm */\n#define REG_MAC_PHY_CTRL\t\t\tREG_AFE_CTRL3_8821C\t/* phydm only */\n#define REG_LEDCFG0\t\t\t\t\tREG_LED_CFG_8821C\t/* rtw_mp.c */\n#define MSR\t\t\t\t\t\t\t(REG_CR_8821C + 2)\t/* rtw_mp.c */\n#define MSR1\t\t\t\t\t\tREG_CR_EXT_8821C\t/* rtw_mp.c & hal_com.c */\n#define REG_C2HEVT_MSG_NORMAL\t\t0x1A0\t\t\t/* hal_com.c */\n#define REG_C2HEVT_CLEAR\t\t\t0x1AF\t\t\t/* hal_com.c */\n#define REG_BCN_CTRL_1\t\t\t\tREG_BCN_CTRL_CLINT0_8821C/* hal_com.c */\n\n#define REG_WOWLAN_WAKE_REASON\t0x01C7\n#define REG_GPIO_PIN_CTRL_2\t\t\tREG_GPIO_EXT_CTRL_8821C\n\n/* RXERR_RPT, for rtw_mp.c */\n#define RXERR_TYPE_OFDM_PPDU\t\t0\n#define RXERR_TYPE_OFDM_FALSE_ALARM\t2\n#define RXERR_TYPE_OFDM_MPDU_OK\t\t0\n#define RXERR_TYPE_OFDM_MPDU_FAIL\t1\n#define RXERR_TYPE_CCK_PPDU\t\t3\n#define RXERR_TYPE_CCK_FALSE_ALARM\t5\n#define RXERR_TYPE_CCK_MPDU_OK\t\t3\n#define RXERR_TYPE_CCK_MPDU_FAIL\t4\n#define RXERR_TYPE_HT_PPDU\t\t8\n#define RXERR_TYPE_HT_FALSE_ALARM\t9\n#define RXERR_TYPE_HT_MPDU_TOTAL\t6\n#define RXERR_TYPE_HT_MPDU_OK\t\t6\n#define RXERR_TYPE_HT_MPDU_FAIL\t\t7\n#define RXERR_TYPE_RX_FULL_DROP\t\t10\n\n#define RXERR_COUNTER_MASK\t\tBIT_MASK_RPT_COUNTER_8821C\n#define RXERR_RPT_RST\t\t\tBIT_RXERR_RPT_RST_8821C\n#define _RXERR_RPT_SEL(type)\t\t(BIT_RXERR_RPT_SEL_V1_3_0_8821C(type) \\\n\t\t| ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8821C : 0))\n\n/*\n * BB Register definition\n */\n#define rPMAC_Reset\t\t\t\t0x100\t/* hal_mp.c */\n\n#define rFPGA0_RFMOD\t\t\t\t0x800\n#define rFPGA0_TxInfo\t\t\t\t0x804\n#define rOFDMCCKEN_Jaguar\t\t0x808\t/* hal_mp.c */\n#define rFPGA0_TxGainStage\t\t0x80C\t/* phydm only */\n#define rFPGA0_XA_HSSIParameter1\t0x820\t/* hal_mp.c */\n#define rFPGA0_XA_HSSIParameter2\t0x824\t/* hal_mp.c */\n#define rFPGA0_XB_HSSIParameter1\t0x828\t/* hal_mp.c */\n#define rFPGA0_XB_HSSIParameter2\t0x82C\t/* hal_mp.c */\n#define rTxAGC_B_Rate18_06\t\t0x830\n#define rTxAGC_B_Rate54_24\t\t0x834\n#define rTxAGC_B_CCK1_55_Mcs32\t0x838\n#define rCCAonSec_Jaguar\t\t\t0x838\t/* hal_mp.c */\n#define rTxAGC_B_Mcs03_Mcs00\t\t0x83C\n#define rTxAGC_B_Mcs07_Mcs04\t\t0x848\n#define rTxAGC_B_Mcs11_Mcs08\t\t0x84C\n#define rFPGA0_XA_RFInterfaceOE\t\t0x860\n#define rFPGA0_XB_RFInterfaceOE\t\t0x864\n#define rTxAGC_B_Mcs15_Mcs12\t\t0x868\n#define rTxAGC_B_CCK11_A_CCK2_11\t0x86C\n#define rFPGA0_XAB_RFInterfaceSW\t\t0x870\n#define rFPGA0_XAB_RFParameter\t\t0x878\n#define rFPGA0_AnalogParameter4\t\t0x88C\t/* hal_mp.c & phydm */\n#define rFPGA0_XB_LSSIReadBack\t\t0x8A4\t/* phydm */\n#define rHSSIRead_Jaguar\t\t\t\t0x8B0\t/* RF read addr (rtl8821c_phy.c) */\n\n#define\trC_TxScale_Jaguar2\t\t\t0x181C  /* Pah_C TX scaling factor (hal_mp.c) */\n#define\trC_IGI_Jaguar2\t\t\t\t0x1850\t/* Initial Gain for path-C (hal_mp.c) */\n\n#define rFPGA1_TxInfo\t\t\t\t\t0x90C\t/* hal_mp.c */\n#define rSingleTone_ContTx_Jaguar\t\t0x914\t/* hal_mp.c */\n\n#define rCCK0_System\t\t\t\t\t0xA00\n#define rCCK0_AFESetting\t\t\t\t0xA04\n\n#define rCCK0_DSPParameter2\t\t\t0xA1C\n#define rCCK0_TxFilter1\t\t\t\t0xA20\n#define rCCK0_TxFilter2\t\t\t\t0xA24\n#define rCCK0_DebugPort\t\t\t\t0xA28\n#define rCCK0_FalseAlarmReport\t\t0xA2C\n\n#define\trD_TxScale_Jaguar2\t\t\t0x1A1C  /* Path_D TX scaling factor (hal_mp.c) */\n#define\trD_IGI_Jaguar2\t\t\t\t0x1A50\t/* Initial Gain for path-D (hal_mp.c) */\n\n#define rOFDM0_TRxPathEnable\t\t\t0xC04\n#define rOFDM0_TRMuxPar\t\t\t\t0xC08\n#define rA_TxScale_Jaguar\t\t\t\t0xC1C\t/* Pah_A TX scaling factor (hal_mp.c) */\n#define rOFDM0_RxDetector1\t\t\t0xC30\t/* rtw_mp.c */\n#define rOFDM0_ECCAThreshold\t\t\t0xC4C\t/* phydm only */\n#define rOFDM0_XAAGCCore1\t\t\t0xC50\t/* phydm only */\n#define rA_IGI_Jaguar\t\t\t\t\t0xC50\t/* Initial Gain for path-A (hal_mp.c) */\n#define rOFDM0_XBAGCCore1\t\t\t0xC58\t/* phydm only */\n#define rOFDM0_XATxIQImbalance\t\t0xC80\t/* phydm only */\n#define rA_LSSIWrite_Jaguar\t\t\t0xC90\t/* RF write addr, LSSI Parameter (rtl8821c_phy.c) */\n/* RFE */\n#define rA_RFE_Pinmux_Jaguar\t0xCB0\t/* hal_mp.c */\n#define\trB_RFE_Pinmux_Jaguar\t0xEB0\t/* Path_B RFE control pinmux */\n#define\trA_RFE_Inv_Jaguar\t\t0xCB4\t/* Path_A RFE cotrol */  \n#define\trB_RFE_Inv_Jaguar\t\t0xEB4\t/* Path_B RFE control */\n#define\trA_RFE_Jaguar\t\t\t0xCB8 \t/* Path_A RFE cotrol */  \n#define\trB_RFE_Jaguar\t\t\t0xEB8\t/* Path_B RFE control */\n#define\trA_RFE_Inverse_Jaguar\t0xCBC\t/* Path_A RFE control inverse */\n#define\trB_RFE_Inverse_Jaguar\t0xEBC\t/* Path_B RFE control inverse */\n#define\tr_ANTSEL_SW_Jaguar\t\t0x900\t/* ANTSEL SW Control */\n#define\tbMask_RFEInv_Jaguar\t0x3FF00000\n#define\tbMask_AntselPathFollow_Jaguar 0x00030000   \n\n#define rOFDM1_LSTF\t\t\t\t\t0xD00\n#define rOFDM1_TRxPathEnable\t\t\t0xD04\t/* hal_mp.c */\n#define rA_PIRead_Jaguar\t\t\t\t0xD04\t/* RF readback with PI (rtl8821c_phy.c) */\n#define rA_SIRead_Jaguar\t\t\t\t0xD08\t/* RF readback with SI (rtl8821c_phy.c) */\n#define rB_PIRead_Jaguar\t\t\t\t0xD44\t/* RF readback with PI (rtl8821c_phy.c) */\n#define rB_SIRead_Jaguar\t\t\t\t0xD48\t/* RF readback with SI (rtl8821c_phy.c) */\n\n#define rTxAGC_A_Rate18_06\t\t\t0xE00\n#define rTxAGC_A_Rate54_24\t\t\t0xE04\n#define rTxAGC_A_CCK1_Mcs32\t\t\t0xE08\n#define rTxAGC_A_Mcs03_Mcs00\t\t0xE10\n#define rTxAGC_A_Mcs07_Mcs04\t\t0xE14\n#define rTxAGC_A_Mcs11_Mcs08\t\t0xE18\n#define rTxAGC_A_Mcs15_Mcs12\t\t0xE1C\n#define rB_TxScale_Jaguar\t\t\t\t0xE1C\t/* Path_B TX scaling factor (hal_mp.c) */\n#define rB_IGI_Jaguar\t\t\t\t\t0xE50\t/* Initial Gain for path-B (hal_mp.c) */\n#define rB_LSSIWrite_Jaguar\t\t\t0xE90\t/* RF write addr, LSSI Parameter (rtl8821c_phy.c) */\n\n/* Page1(0x100) */\n#define bBBResetB\t\t\t\t\t0x100\n\n/* Page8(0x800) */\n#define bCCKEn\t\t\t\t\t\t0x1000000\n#define bOFDMEn\t\t\t\t\t\t0x2000000\n/* Reg 0x80C rFPGA0_TxGainStage */\n#define bXBTxAGC\t\t\t\t\t\t0xF00\n#define bXCTxAGC\t\t\t\t\t\t0xF000\n#define bXDTxAGC\t\t\t\t\t\t0xF0000\n\n/* PageA(0xA00) */\n#define bCCKBBMode\t\t\t\t\t0x3\n\n#define bCCKScramble\t\t\t\t\t0x8\n#define bCCKTxRate\t\t\t\t\t0x3000\n\n/* General */\n#define bMaskByte0\t\t0xFF\t\t/* mp, rtw_odm.c & phydm */\n#define bMaskByte1\t\t0xFF00\t\t/* hal_mp.c & phydm */\n#define bMaskByte2\t\t0xFF0000\t/* hal_mp.c & phydm */\n#define bMaskByte3\t\t0xFF000000\t/* hal_mp.c & phydm */\n#define bMaskHWord\t\t0xFFFF0000\t/* hal_com.c, rtw_mp.c */\n#define bMaskLWord\t\t0x0000FFFF\t/* mp, hal_com.c & phydm */\n#define bMaskDWord\t\t0xFFFFFFFF\t/* mp, hal, rtw_odm.c & phydm */\n\n#define bEnable\t\t\t0x1\t\t/* hal_mp.c, rtw_mp.c */\n#define bDisable\t\t\t0x0\t\t/* rtw_mp.c */\n\n#define MAX_STALL_TIME\t\t50\t\t/* unit: us, hal_com_phycfg.c */\n\n#define Rx_Smooth_Factor\t\t20\t\t/* phydm only */\n\n/*\n * RF Register definition\n */\n#define RF_AC\t\t\t0x00\n#define RF_AC_Jaguar\t\t0x00\t/* hal_mp.c */\n#define RF_CHNLBW\t\t0x18\t/* rtl8821c_phy.c */\n#define RF_0x52\t\t\t0x52\n\nstruct hw_port_reg {\n\tu32 net_type;\t/*reg_offset*/\n\tu8 net_type_shift;\n\tu32 macaddr;\t\t/*reg_offset*/\n\tu32 bssid;\t\t/*reg_offset*/\n\tu32 bcn_ctl;\t\t\t/*reg_offset*/\n\tu32 tsf_rst;\t\t\t/*reg_offset*/\n\tu8 tsf_rst_bit;\n\tu32 bcn_space;\t\t/*reg_offset*/\n\tu8 bcn_space_shift;\n\tu16 bcn_space_mask;\n\tu32\tps_aid;\t\t\t/*reg_offset*/\n\tu32\tta;\t\t\t\t/*reg_offset*/\n};\n\n#endif /* __RTL8192E_SPEC_H__ */\n"
  },
  {
    "path": "include/rtl8821ce_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8821CE_HAL_H_\n#define _RTL8821CE_HAL_H_\n\n#include <drv_types.h>\t\t/* PADAPTER */\n\n/* rtl8821ce_ops.c */\nvoid rtl8821ce_set_hal_ops(PADAPTER);\n\n#endif /* _RTL8821CE_HAL_H_ */\n"
  },
  {
    "path": "include/rtl8821cs_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8821CS_HAL_H_\n#define _RTL8821CS_HAL_H_\n\n#include <drv_types.h>\t\t/* PADAPTER */\n\n/* rtl8821cs_ops.c */\nu8 rtl8821cs_set_hal_ops(PADAPTER);\n\n#endif /* _RTL8821CS_HAL_H_ */\n"
  },
  {
    "path": "include/rtl8821cu_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8821CU_HAL_H_\n#define _RTL8821CU_HAL_H_\n\n#include <drv_types.h>\t\t/* PADAPTER */\n\n/* rtl8821cu_ops.c */\nu8 rtl8821cu_set_hal_ops(PADAPTER);\nvoid rtl8821cu_set_hw_type(struct dvobj_priv *pdvobj);\n\n#endif /* _RTL8821CU_HAL_H_ */\n"
  },
  {
    "path": "include/rtl8822b_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8822B_HAL_H_\n#define _RTL8822B_HAL_H_\n\n#include <osdep_service.h>\t\t/* BIT(x) */\n#include <drv_types.h>\t\t\t/* PADAPTER */\n#include \"../hal/halmac/halmac_api.h\"\t/* MAC REG definition */\n\n\n#ifdef CONFIG_SUPPORT_TRX_SHARED\n#define MAX_RECVBUF_SZ\t\t46080\t/* 45KB, TX: (256-64)KB */\n#else /* !CONFIG_SUPPORT_TRX_SHARED */\n#define MAX_RECVBUF_SZ\t\t24576\t/* 24KB, TX: 256KB */\n#endif /* !CONFIG_SUPPORT_TRX_SHARED */\n\n/*\n * MAC Register definition\n */\n#define REG_AFE_XTAL_CTRL\tREG_AFE_CTRL1_8822B\t/* hal_com.c & phydm */\n#define REG_AFE_PLL_CTRL\tREG_AFE_CTRL2_8822B\t/* hal_com.c & phydm */\n#define REG_MAC_PHY_CTRL\tREG_AFE_CTRL3_8822B\t/* phydm only */\n#define REG_LEDCFG0\t\tREG_LED_CFG_8822B\t/* rtw_mp.c */\n#define MSR\t\t\t(REG_CR_8822B + 2)\t/* rtw_mp.c & hal_com.c */\n#define MSR1\t\t\tREG_CR_EXT_8822B\t/* rtw_mp.c & hal_com.c */\n#define REG_C2HEVT_MSG_NORMAL\t0x1A0\t\t\t/* hal_com.c */\n#define REG_C2HEVT_CLEAR\t0x1AF\t\t\t/* hal_com.c */\n#define REG_BCN_CTRL_1\t\tREG_BCN_CTRL_CLINT0_8822B\t/* hal_com.c */\n\n#define REG_WOWLAN_WAKE_REASON\t0x01C7 /* hal_com.c */\n#define REG_GPIO_PIN_CTRL_2\t\tREG_GPIO_EXT_CTRL_8822B\t\t/* hal_com.c */\n\n/* RXERR_RPT, for rtw_mp.c */\n#define RXERR_TYPE_OFDM_PPDU\t\t0\n#define RXERR_TYPE_OFDM_FALSE_ALARM\t2\n#define RXERR_TYPE_OFDM_MPDU_OK\t\t0\n#define RXERR_TYPE_OFDM_MPDU_FAIL\t1\n#define RXERR_TYPE_CCK_PPDU\t\t3\n#define RXERR_TYPE_CCK_FALSE_ALARM\t5\n#define RXERR_TYPE_CCK_MPDU_OK\t\t3\n#define RXERR_TYPE_CCK_MPDU_FAIL\t4\n#define RXERR_TYPE_HT_PPDU\t\t8\n#define RXERR_TYPE_HT_FALSE_ALARM\t9\n#define RXERR_TYPE_HT_MPDU_TOTAL\t6\n#define RXERR_TYPE_HT_MPDU_OK\t\t6\n#define RXERR_TYPE_HT_MPDU_FAIL\t\t7\n#define RXERR_TYPE_RX_FULL_DROP\t\t10\n\n#define RXERR_COUNTER_MASK\t\tBIT_MASK_RPT_COUNTER_8822B\n#define RXERR_RPT_RST\t\t\tBIT_RXERR_RPT_RST_8822B\n#define _RXERR_RPT_SEL(type)\t\t(BIT_RXERR_RPT_SEL_V1_3_0_8822B(type) \\\n\t\t\t\t\t| ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8822B : 0))\n\n/*\n * BB Register definition\n */\n#define rPMAC_Reset\t\t\t0x100\t/* hal_mp.c */\n\n#define\trFPGA0_RFMOD\t\t\t0x800\n#define rFPGA0_TxInfo\t\t\t0x804\n#define rOFDMCCKEN_Jaguar\t\t0x808\t/* hal_mp.c */\n#define rFPGA0_TxGainStage\t\t0x80C\t/* phydm only */\n#define rFPGA0_XA_HSSIParameter1\t0x820\t/* hal_mp.c */\n#define rFPGA0_XA_HSSIParameter2\t0x824\t/* hal_mp.c */\n#define rFPGA0_XB_HSSIParameter1\t0x828\t/* hal_mp.c */\n#define rFPGA0_XB_HSSIParameter2\t0x82C\t/* hal_mp.c */\n#define rTxAGC_B_Rate18_06\t\t0x830\n#define rTxAGC_B_Rate54_24\t\t0x834\n#define rTxAGC_B_CCK1_55_Mcs32\t\t0x838\n#define rCCAonSec_Jaguar\t\t0x838\t/* hal_mp.c */\n#define rTxAGC_B_Mcs03_Mcs00\t\t0x83C\n#define rTxAGC_B_Mcs07_Mcs04\t\t0x848\n#define rTxAGC_B_Mcs11_Mcs08\t\t0x84C\n#define rFPGA0_XA_RFInterfaceOE\t\t0x860\n#define rFPGA0_XB_RFInterfaceOE\t\t0x864\n#define rTxAGC_B_Mcs15_Mcs12\t\t0x868\n#define rTxAGC_B_CCK11_A_CCK2_11\t0x86C\n#define rFPGA0_XAB_RFInterfaceSW\t0x870\n#define rFPGA0_XAB_RFParameter\t\t0x878\n#define rFPGA0_AnalogParameter4\t\t0x88C\t/* hal_mp.c & phydm */\n#define rFPGA0_XB_LSSIReadBack\t\t0x8A4\t/* phydm */\n#define rHSSIRead_Jaguar\t\t0x8B0\t/* RF read addr (rtl8822b_phy.c) */\n\n#define\trC_TxScale_Jaguar2\t\t0x181C  /* Pah_C TX scaling factor (hal_mp.c) */\n#define\trC_IGI_Jaguar2\t\t\t0x1850\t/* Initial Gain for path-C (hal_mp.c) */\n\n#define rFPGA1_TxInfo\t\t\t0x90C\t/* hal_mp.c */\n#define rSingleTone_ContTx_Jaguar\t0x914\t/* hal_mp.c */\n/* TX BeamForming */\n#define REG_BB_TX_PATH_SEL_1_8822B\t0x93C\t/* rtl8822b_phy.c */\n#define REG_BB_TX_PATH_SEL_2_8822B\t0x940\t/* rtl8822b_phy.c */\n\n/* TX BeamForming */\n#define REG_BB_TXBF_ANT_SET_BF1_8822B\t0x19AC\t/* rtl8822b_phy.c */\n#define REG_BB_TXBF_ANT_SET_BF0_8822B\t0x19B4\t/* rtl8822b_phy.c */\n\n#define rCCK0_System\t\t\t0xA00\n#define rCCK0_AFESetting\t\t0xA04\n\n#define rCCK0_DSPParameter2\t\t0xA1C\n#define rCCK0_TxFilter1\t\t\t0xA20\n#define rCCK0_TxFilter2\t\t\t0xA24\n#define rCCK0_DebugPort\t\t\t0xA28\n#define rCCK0_FalseAlarmReport\t\t0xA2C\n\n#define\trD_TxScale_Jaguar2\t\t0x1A1C  /* Path_D TX scaling factor (hal_mp.c) */\n#define\trD_IGI_Jaguar2\t\t\t0x1A50\t/* Initial Gain for path-D (hal_mp.c) */\n\n#define rOFDM0_TRxPathEnable\t\t0xC04\n#define rOFDM0_TRMuxPar\t\t\t0xC08\n#define rA_TxScale_Jaguar\t\t0xC1C\t/* Pah_A TX scaling factor (hal_mp.c) */\n#define rOFDM0_RxDetector1\t\t0xC30\t/* rtw_mp.c */\n#define rOFDM0_ECCAThreshold\t\t0xC4C\t/* phydm only */\n#define rOFDM0_XAAGCCore1\t\t0xC50\t/* phydm only */\n#define rA_IGI_Jaguar\t\t\t0xC50\t/* Initial Gain for path-A (hal_mp.c) */\n#define rOFDM0_XBAGCCore1\t\t0xC58\t/* phydm only */\n#define rOFDM0_XATxIQImbalance\t\t0xC80\t/* phydm only */\n#define rA_LSSIWrite_Jaguar\t\t0xC90\t/* RF write addr, LSSI Parameter (rtl8822b_phy.c) */\n\n#define rOFDM1_LSTF\t\t\t0xD00\n#define rOFDM1_TRxPathEnable\t\t0xD04\t/* hal_mp.c */\n#define rA_PIRead_Jaguar\t\t0xD04\t/* RF readback with PI (rtl8822b_phy.c) */\n#define rA_SIRead_Jaguar\t\t0xD08\t/* RF readback with SI (rtl8822b_phy.c) */\n#define rB_PIRead_Jaguar\t\t0xD44\t/* RF readback with PI (rtl8822b_phy.c) */\n#define rB_SIRead_Jaguar\t\t0xD48\t/* RF readback with SI (rtl8822b_phy.c) */\n\n#define rTxAGC_A_Rate18_06\t\t0xE00\n#define rTxAGC_A_Rate54_24\t\t0xE04\n#define rTxAGC_A_CCK1_Mcs32\t\t0xE08\n#define rTxAGC_A_Mcs03_Mcs00\t\t0xE10\n#define rTxAGC_A_Mcs07_Mcs04\t\t0xE14\n#define rTxAGC_A_Mcs11_Mcs08\t\t0xE18\n#define rTxAGC_A_Mcs15_Mcs12\t\t0xE1C\n#define rB_TxScale_Jaguar\t\t0xE1C\t/* Path_B TX scaling factor (hal_mp.c) */\n#define rB_IGI_Jaguar\t\t\t0xE50\t/* Initial Gain for path-B (hal_mp.c) */\n#define rB_LSSIWrite_Jaguar\t\t0xE90\t/* RF write addr, LSSI Parameter (rtl8822b_phy.c) */\n/* RFE */\n#define rA_RFE_Pinmux_Jaguar\t0xCB0\t/* hal_mp.c */\n#define\trB_RFE_Pinmux_Jaguar\t0xEB0\t/* Path_B RFE control pinmux */\n#define\trA_RFE_Inv_Jaguar\t\t0xCB4\t/* Path_A RFE cotrol */  \n#define\trB_RFE_Inv_Jaguar\t\t0xEB4\t/* Path_B RFE control */\n#define\trA_RFE_Jaguar\t\t\t0xCB8 \t/* Path_A RFE cotrol */  \n#define\trB_RFE_Jaguar\t\t\t0xEB8\t/* Path_B RFE control */\n#define\trA_RFE_Inverse_Jaguar\t0xCBC\t/* Path_A RFE control inverse */\n#define\trB_RFE_Inverse_Jaguar\t0xEBC\t/* Path_B RFE control inverse */\n#define\tr_ANTSEL_SW_Jaguar\t\t0x900\t/* ANTSEL SW Control */\n#define\tbMask_RFEInv_Jaguar\t0x3FF00000\n#define\tbMask_AntselPathFollow_Jaguar 0x00030000\n\n#define\t\trC_RFE_Pinmux_Jaguar\t0x18B4\t/* Path_C RFE cotrol pinmux*/\n#define\t\trD_RFE_Pinmux_Jaguar\t0x1AB4\t/* Path_D RFE cotrol pinmux*/\n#define\t\trA_RFE_Sel_Jaguar2\t\t0x1990\n\n/* Page1(0x100) */\n#define bBBResetB\t\t\t0x100\n\n/* Page8(0x800) */\n#define bCCKEn\t\t\t\t0x1000000\n#define bOFDMEn\t\t\t\t0x2000000\n/* Reg 0x80C rFPGA0_TxGainStage */\n#define bXBTxAGC\t\t\t0xF00\n#define bXCTxAGC\t\t\t0xF000\n#define bXDTxAGC\t\t\t0xF0000\n\n/* PageA(0xA00) */\n#define bCCKBBMode\t\t\t0x3\n\n#define bCCKScramble\t\t\t0x8\n#define bCCKTxRate\t\t\t0x3000\n\n/* General */\n#define bMaskByte0\t\t0xFF\t\t/* mp, rtw_odm.c & phydm */\n#define bMaskByte1\t\t0xFF00\t\t/* hal_mp.c & phydm */\n#define bMaskByte2\t\t0xFF0000\t/* hal_mp.c & phydm */\n#define bMaskByte3\t\t0xFF000000\t/* hal_mp.c & phydm */\n#define bMaskHWord\t\t0xFFFF0000\t/* hal_com.c, rtw_mp.c */\n#define bMaskLWord\t\t0x0000FFFF\t/* mp, hal_com.c & phydm */\n#define bMaskDWord\t\t0xFFFFFFFF\t/* mp, hal, rtw_odm.c & phydm */\n\n#define bEnable\t\t\t0x1\t\t/* hal_mp.c, rtw_mp.c */\n#define bDisable\t\t0x0\t\t/* rtw_mp.c */\n\n#define MAX_STALL_TIME\t\t50\t\t/* unit: us, hal_com_phycfg.c */\n\n#define Rx_Smooth_Factor\t20\t\t/* phydm only */\n\n/*\n * RF Register definition\n */\n#define RF_AC\t\t\t0x00\n#define RF_AC_Jaguar\t\t0x00\t/* hal_mp.c */\n#define RF_CHNLBW\t\t0x18\t/* rtl8822b_phy.c */\n#define RF_ModeTableAddr\t0x30\t/* rtl8822b_phy.c */\n#define RF_ModeTableData0\t0x31\t/* rtl8822b_phy.c */\n#define RF_ModeTableData1\t0x32\t/* rtl8822b_phy.c */\n#define RF_0x52\t\t\t0x52\n#define RF_WeLut_Jaguar\t\t0xEF\t/* rtl8822b_phy.c */\n\n/* General Functions */\nvoid rtl8822b_init_hal_spec(PADAPTER);\t\t\t\t/* hal/hal_com.c */\n\n#ifdef CONFIG_MP_INCLUDED\n/* MP Functions */\n#include <rtw_mp.h>\t\t/* struct mp_priv */\nvoid rtl8822b_prepare_mp_txdesc(PADAPTER, struct mp_priv *);\t/* rtw_mp.c */\nvoid rtl8822b_mp_config_rfpath(PADAPTER);\t\t\t/* hal_mp.c */\n#endif\nvoid hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus);\n\n#ifdef CONFIG_USB_HCI\n#include <rtl8822bu_hal.h>\n#elif defined(CONFIG_SDIO_HCI)\n#include <rtl8822bs_hal.h>\n#elif defined(CONFIG_PCI_HCI)\n#include <rtl8822be_hal.h>\n#endif\n\n#endif /* _RTL8822B_HAL_H_ */\n"
  },
  {
    "path": "include/rtl8822be_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8822BE_HAL_H_\n#define _RTL8822BE_HAL_H_\n\n#include <drv_types.h>\t\t/* PADAPTER */\n\n#define RT_BCN_INT_MASKS\t(BIT20 | BIT25 | BIT26 | BIT16)\n\n/* rtl8822be_ops.c */\nvoid UpdateInterruptMask8822BE(PADAPTER, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);\nu16 get_txbd_rw_reg(u16 q_idx);\n\n\n#endif /* _RTL8822BE_HAL_H_ */\n"
  },
  {
    "path": "include/rtl8822bs_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8822BS_HAL_H_\n#define _RTL8822BS_HAL_H_\n\n#include <drv_types.h>\t\t/* PADAPTER */\n\n/* rtl8822bs_ops.c */\nvoid rtl8822bs_set_hal_ops(PADAPTER);\n\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\nvoid rtl8822bs_disable_interrupt_but_cpwm2(PADAPTER adapter);\n#endif\n\n/* rtl8822bs_xmit.c */\ns32 rtl8822bs_dequeue_writeport(PADAPTER);\n#define _dequeue_writeport(a)\trtl8822bs_dequeue_writeport(a)\n\n#endif /* _RTL8822BS_HAL_H_ */\n"
  },
  {
    "path": "include/rtl8822bu_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8822BU_HAL_H_\n#define _RTL8822BU_HAL_H_\n\n#ifdef CONFIG_USB_HCI\n\t#include <drv_types.h>\t\t/* PADAPTER */\n\n\t#ifdef CONFIG_USB_HCI\n\t\t#ifdef USB_PACKET_OFFSET_SZ\n\t\t\t#define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ)\n\t\t#else\n\t\t\t#define PACKET_OFFSET_SZ (8)\n\t\t#endif\n\t\t#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)\n\t#endif\n\n\t/* undefine MAX_RECVBUF_SZ from rtl8822b_hal.h  */\n\t#ifdef MAX_RECVBUF_SZ\n\t\t#undef MAX_RECVBUF_SZ\n\t#endif\n\n\t/* recv_buffer must be large than usb agg size */\n\t#ifndef MAX_RECVBUF_SZ\n\t\t#ifndef CONFIG_MINIMAL_MEMORY_USAGE\n\t\t\t#ifdef CONFIG_PLATFORM_NOVATEK_NT72668\n\t\t\t\t#define MAX_RECVBUF_SZ (15360) /* 15k */\n\t\t\t\t#elif defined(CONFIG_PLATFORM_HISILICON)\n\t\t\t\t/* use 16k to workaround for HISILICON platform */\n\t\t\t\t#define MAX_RECVBUF_SZ (16384)\n\t\t\t#else\n\t\t\t\t#define MAX_RECVBUF_SZ (32768)\n\t\t\t#endif\n\t\t#else\n\t\t\t#define MAX_RECVBUF_SZ (4000)\n\t\t#endif\n\t#endif /* !MAX_RECVBUF_SZ */\n\n\t/* rtl8822bu_ops.c */\n\tvoid rtl8822bu_set_hal_ops(PADAPTER padapter);\n\tvoid rtl8822bu_set_hw_type(struct dvobj_priv *pdvobj);\n\n\t/* rtl8822bu_io.c */\n\tvoid rtl8822bu_set_intf_ops(struct _io_ops *pops);\n\n#endif /* CONFIG_USB_HCI */\n\n\n#endif /* _RTL8822BU_HAL_H_ */\n"
  },
  {
    "path": "include/rtl8822c_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8822C_HAL_H_\n#define _RTL8822C_HAL_H_\n\n#include <osdep_service.h>\t\t/* BIT(x) */\n#include <drv_types.h>\t\t\t/* PADAPTER */\n#include \"../hal/halmac/halmac_api.h\"\t/* MAC REG definition */\n\n#ifdef CONFIG_SUPPORT_TRX_SHARED\n#define DEF_RECVBUF_SZ\t\t24576\t/* RX 24K */\n#if (DFT_TRX_SHARE_MODE == 1)\n#define RX_FIFO_EXPANDING 40960\t/* RX= 24K+40K=64K , TX=256K-40K=216K */\n#elif (DFT_TRX_SHARE_MODE == 2)\n#define RX_FIFO_EXPANDING 65536\t/* RX= 24K+40K+24=88K , TX=256K-40K-24K=192K */\n#elif (DFT_TRX_SHARE_MODE ==3)\n#define RX_FIFO_EXPANDING 106496\t/* RX= 24K+40K+24+40K=128K , TX=256K-40K-24K-40K=152K */\n#elif (DFT_TRX_SHARE_MODE ==4)\n#define RX_FIFO_EXPANDING 131072\t/* RX= 24K+40K+24+40K+24K=128K , TX=256K-40K-24K-40K-24K=128K */\n#else\n#define RX_FIFO_EXPANDING 0\n#endif\n#define MAX_RECVBUF_SZ\t(DEF_RECVBUF_SZ + RX_FIFO_EXPANDING)\t\n#else /* !CONFIG_SUPPORT_TRX_SHARED */\n#define MAX_RECVBUF_SZ\t\t24576\t/* 24KB, TX: 256KB */\n#endif /* !CONFIG_SUPPORT_TRX_SHARED */\n\n/*\n * MAC Register definition\n */\n#define REG_AFE_XTAL_CTRL\tREG_AFE_CTRL1_8822C\t/* hal_com.c & phydm */\n#define REG_LEDCFG0\t\tREG_LED_CFG_8822C\t/* rtw_mp.c */\n#define MSR\t\t\t(REG_CR_8822C + 2)\t/* rtw_mp.c & hal_com.c */\n#define MSR1\t\t\tREG_CR_EXT_8822C\t/* rtw_mp.c & hal_com.c */\n#define REG_C2HEVT_MSG_NORMAL\t0x1A0\t\t\t/* hal_com.c */\n#define REG_C2HEVT_CLEAR\t0x1AF\t\t\t/* hal_com.c */\n#define REG_BCN_CTRL_1\t\tREG_BCN_CTRL_CLINT0_8822C\t/* hal_com.c */\n\n#define REG_WOWLAN_WAKE_REASON\t0x01C7 /* hal_com.c */\n#define REG_GPIO_PIN_CTRL_2\t\tREG_GPIO_EXT_CTRL_8822C\t\t/* hal_com.c */\n\n/* RXERR_RPT, for rtw_mp.c */\n#define RXERR_TYPE_OFDM_PPDU\t\t0\n#define RXERR_TYPE_OFDM_FALSE_ALARM\t2\n#define RXERR_TYPE_OFDM_MPDU_OK\t\t0\n#define RXERR_TYPE_OFDM_MPDU_FAIL\t1\n#define RXERR_TYPE_CCK_PPDU\t\t3\n#define RXERR_TYPE_CCK_FALSE_ALARM\t5\n#define RXERR_TYPE_CCK_MPDU_OK\t\t3\n#define RXERR_TYPE_CCK_MPDU_FAIL\t4\n#define RXERR_TYPE_HT_PPDU\t\t8\n#define RXERR_TYPE_HT_FALSE_ALARM\t9\n#define RXERR_TYPE_HT_MPDU_TOTAL\t6\n#define RXERR_TYPE_HT_MPDU_OK\t\t6\n#define RXERR_TYPE_HT_MPDU_FAIL\t\t7\n#define RXERR_TYPE_RX_FULL_DROP\t\t10\n\n#define RXERR_COUNTER_MASK\t\tBIT_MASK_RPT_COUNTER_8822C\n#define RXERR_RPT_RST\t\t\tBIT_RXERR_RPT_RST_8822C\n#define _RXERR_RPT_SEL(type)\t\t(BIT_RXERR_RPT_SEL_V1_3_0_8822C(type) \\\n\t\t\t\t\t| ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8822C : 0))\n\n/*\n * BB Register definition\n */\n#define rPMAC_Reset\t\t\t0x100\t/* hal_mp.c */\n\n#define\trFPGA0_RFMOD\t\t\t0x800\n#define rFPGA0_TxInfo\t\t\t0x804\n#define rOFDMCCKEN_Jaguar\t\t0x808\t/* hal_mp.c */\n#define rFPGA0_TxGainStage\t\t0x80C\t/* phydm only */\n#define rFPGA0_XA_HSSIParameter1\t0x820\t/* hal_mp.c */\n#define rFPGA0_XA_HSSIParameter2\t0x824\t/* hal_mp.c */\n#define rFPGA0_XB_HSSIParameter1\t0x828\t/* hal_mp.c */\n#define rFPGA0_XB_HSSIParameter2\t0x82C\t/* hal_mp.c */\n#define rTxAGC_B_Rate18_06\t\t0x830\n#define rTxAGC_B_Rate54_24\t\t0x834\n#define rTxAGC_B_CCK1_55_Mcs32\t\t0x838\n#define rCCAonSec_Jaguar\t\t0x838\t/* hal_mp.c */\n#define rTxAGC_B_Mcs03_Mcs00\t\t0x83C\n#define rTxAGC_B_Mcs07_Mcs04\t\t0x848\n#define rTxAGC_B_Mcs11_Mcs08\t\t0x84C\n#define rFPGA0_XA_RFInterfaceOE\t\t0x860\n#define rFPGA0_XB_RFInterfaceOE\t\t0x864\n#define rTxAGC_B_Mcs15_Mcs12\t\t0x868\n#define rTxAGC_B_CCK11_A_CCK2_11\t0x86C\n#define rFPGA0_XAB_RFInterfaceSW\t0x870\n#define rFPGA0_XAB_RFParameter\t\t0x878\n#define rFPGA0_AnalogParameter4\t\t0x88C\t/* hal_mp.c & phydm */\n#define rFPGA0_XB_LSSIReadBack\t\t0x8A4\t/* phydm */\n#define rHSSIRead_Jaguar\t\t0x8B0\t/* RF read addr (rtl8822c_phy.c) */\n\n#define\trC_TxScale_Jaguar2\t\t0x181C  /* Pah_C TX scaling factor (hal_mp.c) */\n#define\trC_IGI_Jaguar2\t\t\t0x1850\t/* Initial Gain for path-C (hal_mp.c) */\n\n#define rFPGA1_TxInfo\t\t\t0x90C\t/* hal_mp.c */\n#define rSingleTone_ContTx_Jaguar\t0x914\t/* hal_mp.c */\n/* TX BeamForming */\n#define REG_BB_TX_PATH_SEL_1_8822C\t0x93C\t/* rtl8822c_phy.c */\n#define REG_BB_TX_PATH_SEL_2_8822C\t0x940\t/* rtl8822c_phy.c */\n\n/* TX BeamForming */\n#define REG_BB_TXBF_ANT_SET_BF1_8822C\t0x19AC\t/* rtl8822c_phy.c */\n#define REG_BB_TXBF_ANT_SET_BF0_8822C\t0x19B4\t/* rtl8822c_phy.c */\n\n#define rCCK0_System\t\t\t0xA00\n#define rCCK0_AFESetting\t\t0xA04\n\n#define rCCK0_DSPParameter2\t\t0xA1C\n#define rCCK0_TxFilter1\t\t\t0xA20\n#define rCCK0_TxFilter2\t\t\t0xA24\n#define rCCK0_DebugPort\t\t\t0xA28\n#define rCCK0_FalseAlarmReport\t\t0xA2C\n\n#define\trD_TxScale_Jaguar2\t\t0x1A1C  /* Path_D TX scaling factor (hal_mp.c) */\n#define\trD_IGI_Jaguar2\t\t\t0x1A50\t/* Initial Gain for path-D (hal_mp.c) */\n\n#define rOFDM0_TRxPathEnable\t\t0xC04\n#define rOFDM0_TRMuxPar\t\t\t0xC08\n#define rA_TxScale_Jaguar\t\t0xC1C\t/* Pah_A TX scaling factor (hal_mp.c) */\n#define rOFDM0_RxDetector1\t\t0xC30\t/* rtw_mp.c */\n#define rOFDM0_ECCAThreshold\t\t0xC4C\t/* phydm only */\n#define rOFDM0_XAAGCCore1\t\t0xC50\t/* phydm only */\n#define rA_IGI_Jaguar\t\t\t0xC50\t/* Initial Gain for path-A (hal_mp.c) */\n#define rOFDM0_XBAGCCore1\t\t0xC58\t/* phydm only */\n#define rOFDM0_XATxIQImbalance\t\t0xC80\t/* phydm only */\n#define rA_LSSIWrite_Jaguar\t\t0xC90\t/* RF write addr, LSSI Parameter (rtl8822b_phy.c) */\n\n#define rOFDM1_LSTF\t\t\t0xD00\n#define rOFDM1_TRxPathEnable\t\t0xD04\t/* hal_mp.c */\n#define rA_PIRead_Jaguar\t\t0xD04\t/* RF readback with PI (rtl8822c_phy.c) */\n#define rA_SIRead_Jaguar\t\t0xD08\t/* RF readback with SI (rtl8822c_phy.c) */\n#define rB_PIRead_Jaguar\t\t0xD44\t/* RF readback with PI (rtl8822c_phy.c) */\n#define rB_SIRead_Jaguar\t\t0xD48\t/* RF readback with SI (rtl8822c_phy.c) */\n\n#define rTxAGC_A_Rate18_06\t\t0xE00\n#define rTxAGC_A_Rate54_24\t\t0xE04\n#define rTxAGC_A_CCK1_Mcs32\t\t0xE08\n#define rTxAGC_A_Mcs03_Mcs00\t\t0xE10\n#define rTxAGC_A_Mcs07_Mcs04\t\t0xE14\n#define rTxAGC_A_Mcs11_Mcs08\t\t0xE18\n#define rTxAGC_A_Mcs15_Mcs12\t\t0xE1C\n#define rB_TxScale_Jaguar\t\t0xE1C\t/* Path_B TX scaling factor (hal_mp.c) */\n#define rB_IGI_Jaguar\t\t\t0xE50\t/* Initial Gain for path-B (hal_mp.c) */\n#define rB_LSSIWrite_Jaguar\t\t0xE90\t/* RF write addr, LSSI Parameter (rtl8822b_phy.c) */\n/* RFE */\n#define rA_RFE_Pinmux_Jaguar\t0xCB0\t/* hal_mp.c */\n#define\trB_RFE_Pinmux_Jaguar\t0xEB0\t/* Path_B RFE control pinmux */\n#define\trA_RFE_Inv_Jaguar\t\t0xCB4\t/* Path_A RFE cotrol */  \n#define\trB_RFE_Inv_Jaguar\t\t0xEB4\t/* Path_B RFE control */\n#define\trA_RFE_Jaguar\t\t\t0xCB8 \t/* Path_A RFE cotrol */  \n#define\trB_RFE_Jaguar\t\t\t0xEB8\t/* Path_B RFE control */\n#define\trA_RFE_Inverse_Jaguar\t0xCBC\t/* Path_A RFE control inverse */\n#define\trB_RFE_Inverse_Jaguar\t0xEBC\t/* Path_B RFE control inverse */\n#define\tr_ANTSEL_SW_Jaguar\t\t0x900\t/* ANTSEL SW Control */\n#define\tbMask_RFEInv_Jaguar\t0x3FF00000\n#define\tbMask_AntselPathFollow_Jaguar 0x00030000\n\n#define\t\trC_RFE_Pinmux_Jaguar\t0x18B4\t/* Path_C RFE cotrol pinmux*/\n#define\t\trD_RFE_Pinmux_Jaguar\t0x1AB4\t/* Path_D RFE cotrol pinmux*/\n#define\t\trA_RFE_Sel_Jaguar2\t\t0x1990\n\n/* Page1(0x100) */\n#define bBBResetB\t\t\t0x100\n\n/* Page8(0x800) */\n#define bCCKEn\t\t\t\t0x1000000\n#define bOFDMEn\t\t\t\t0x2000000\n/* Reg 0x80C rFPGA0_TxGainStage */\n#define bXBTxAGC\t\t\t0xF00\n#define bXCTxAGC\t\t\t0xF000\n#define bXDTxAGC\t\t\t0xF0000\n\n/* PageA(0xA00) */\n#define bCCKBBMode\t\t\t0x3\n\n#define bCCKScramble\t\t\t0x8\n#define bCCKTxRate\t\t\t0x3000\n\n/* General */\n#define bMaskByte0\t\t0xFF\t\t/* mp, rtw_odm.c & phydm */\n#define bMaskByte1\t\t0xFF00\t\t/* hal_mp.c & phydm */\n#define bMaskByte2\t\t0xFF0000\t/* hal_mp.c & phydm */\n#define bMaskByte3\t\t0xFF000000\t/* hal_mp.c & phydm */\n#define bMaskHWord\t\t0xFFFF0000\t/* hal_com.c, rtw_mp.c */\n#define bMaskLWord\t\t0x0000FFFF\t/* mp, hal_com.c & phydm */\n#define bMaskDWord\t\t0xFFFFFFFF\t/* mp, hal, rtw_odm.c & phydm */\n\n#define bEnable\t\t\t0x1\t\t/* hal_mp.c, rtw_mp.c */\n#define bDisable\t\t0x0\t\t/* rtw_mp.c */\n\n#define MAX_STALL_TIME\t\t50\t\t/* unit: us, hal_com_phycfg.c */\n\n#define Rx_Smooth_Factor\t20\t\t/* phydm only */\n\n/*\n * RF Register definition\n */\n#define RF_AC\t\t\t0x00\n#define RF_AC_Jaguar\t\t0x00\t/* hal_mp.c */\n#define RF_CHNLBW\t\t0x18\t/* rtl8822c_phy.c */\n#define RF_ModeTableAddr\t0x30\t/* rtl8822c_phy.c */\n#define RF_ModeTableData0\t0x31\t/* rtl8822c_phy.c */\n#define RF_ModeTableData1\t0x32\t/* rtl8822c_phy.c */\n#define RF_0x52\t\t\t0x52\n#define RF_WeLut_Jaguar\t\t0xEF\t/* rtl8822c_phy.c */\n\n/* rtw_lps_state_chk()@hal_com.c */\n#define BIT_PWRBIT_OW_EN\tBIT_WMAC_TCRPWRMGT_HWDATA_EN_8822C \n\n/* General Functions */\nvoid rtl8822c_init_hal_spec(PADAPTER);\t\t\t\t/* hal/hal_com.c */\n\n#ifdef CONFIG_MP_INCLUDED\n/* MP Functions */\n#include <rtw_mp.h>\t\t/* struct mp_priv */\nvoid rtl8822c_prepare_mp_txdesc(PADAPTER, struct mp_priv *);\t/* rtw_mp.c */\nvoid rtl8822c_mp_config_rfpath(PADAPTER);\t\t\t/* hal_mp.c */\n#endif\nvoid hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus);\n\n#ifdef CONFIG_USB_HCI\n#include <rtl8822cu_hal.h>\n#elif defined(CONFIG_SDIO_HCI)\n#include <rtl8822cs_hal.h>\n#elif defined(CONFIG_PCI_HCI)\n#include <rtl8822ce_hal.h>\n#endif\n\n#endif /* _RTL8822C_HAL_H_ */\n"
  },
  {
    "path": "include/rtl8822ce_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8822CE_HAL_H_\n#define _RTL8822CE_HAL_H_\n\n#include <drv_types.h>\t\t/* PADAPTER */\n\n#define RT_BCN_INT_MASKS\t(BIT20 | BIT25 | BIT26 | BIT16)\n\n/* rtl8822ce_ops.c */\nvoid UpdateInterruptMask8822CE(PADAPTER, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);\nu16 get_txbd_rw_reg(u16 q_idx);\n\n\n#endif /* _RTL8822CE_HAL_H_ */\n"
  },
  {
    "path": "include/rtl8822cs_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8822CS_HAL_H_\n#define _RTL8822CS_HAL_H_\n\n#include <drv_types.h>\t\t/* PADAPTER */\n\n/* rtl8822cs_ops.c */\nvoid rtl8822cs_set_hal_ops(PADAPTER);\n\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\nvoid rtl8822cs_disable_interrupt_but_cpwm2(PADAPTER adapter);\n#endif\n\n/* rtl8822cs_xmit.c */\ns32 rtl8822cs_dequeue_writeport(PADAPTER);\n#define _dequeue_writeport(a)\trtl8822cs_dequeue_writeport(a)\n\n#endif /* _RTL8822CS_HAL_H_ */\n"
  },
  {
    "path": "include/rtl8822cu_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL8822CU_HAL_H_\n#define _RTL8822CU_HAL_H_\n\n#ifdef CONFIG_USB_HCI\n\t#include <drv_types.h>\t\t/* PADAPTER */\n\n\t#ifdef CONFIG_USB_HCI\n\t\t#ifdef USB_PACKET_OFFSET_SZ\n\t\t\t#define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ)\n\t\t#else\n\t\t\t#define PACKET_OFFSET_SZ (8)\n\t\t#endif\n\t\t#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)\n\t#endif\n\n\t/* undefine MAX_RECVBUF_SZ from rtl8822c_hal.h  */\n\t#ifdef MAX_RECVBUF_SZ\n\t\t#undef MAX_RECVBUF_SZ\n\t#endif\n\n\t/* recv_buffer must be large than usb agg size */\n\t#ifndef MAX_RECVBUF_SZ\n\t\t#ifndef CONFIG_MINIMAL_MEMORY_USAGE\n\t\t\t#ifdef CONFIG_PLATFORM_NOVATEK_NT72668\n\t\t\t\t#define MAX_RECVBUF_SZ (15360) /* 15k */\n\t\t\t\t#elif defined(CONFIG_PLATFORM_HISILICON)\n\t\t\t\t/* use 16k to workaround for HISILICON platform */\n\t\t\t\t#define MAX_RECVBUF_SZ (16384)\n\t\t\t#else\n\t\t\t\t#define MAX_RECVBUF_SZ (32768)\n\t\t\t#endif\n\t\t#else\n\t\t\t#define MAX_RECVBUF_SZ (4000)\n\t\t#endif\n\t#endif /* !MAX_RECVBUF_SZ */\n\n\t/* rtl8822cu_ops.c */\n\tvoid rtl8822cu_set_hal_ops(PADAPTER padapter);\n\tvoid rtl8822cu_set_hw_type(struct dvobj_priv *pdvobj);\n\n\t/* rtl8822cu_io.c */\n\tvoid rtl8822cu_set_intf_ops(struct _io_ops *pops);\n\n#endif /* CONFIG_USB_HCI */\n\n\n#endif /* _RTL8822CU_HAL_H_ */\n"
  },
  {
    "path": "include/rtw_android.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef __RTW_ANDROID_H__\n#define __RTW_ANDROID_H__\n\nenum ANDROID_WIFI_CMD {\n\tANDROID_WIFI_CMD_START,\n\tANDROID_WIFI_CMD_STOP,\n\tANDROID_WIFI_CMD_SCAN_ACTIVE,\n\tANDROID_WIFI_CMD_SCAN_PASSIVE,\n\tANDROID_WIFI_CMD_RSSI,\n\tANDROID_WIFI_CMD_LINKSPEED,\n\tANDROID_WIFI_CMD_RXFILTER_START,\n\tANDROID_WIFI_CMD_RXFILTER_STOP,\n\tANDROID_WIFI_CMD_RXFILTER_ADD,\n\tANDROID_WIFI_CMD_RXFILTER_REMOVE,\n\tANDROID_WIFI_CMD_BTCOEXSCAN_START,\n\tANDROID_WIFI_CMD_BTCOEXSCAN_STOP,\n\tANDROID_WIFI_CMD_BTCOEXMODE,\n\tANDROID_WIFI_CMD_SETSUSPENDMODE,\n\tANDROID_WIFI_CMD_SETSUSPENDOPT,\n\tANDROID_WIFI_CMD_P2P_DEV_ADDR,\n\tANDROID_WIFI_CMD_SETFWPATH,\n\tANDROID_WIFI_CMD_SETBAND,\n\tANDROID_WIFI_CMD_GETBAND,\n\tANDROID_WIFI_CMD_COUNTRY,\n\tANDROID_WIFI_CMD_P2P_SET_NOA,\n\tANDROID_WIFI_CMD_P2P_GET_NOA,\n\tANDROID_WIFI_CMD_P2P_SET_PS,\n\tANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE,\n\n\tANDROID_WIFI_CMD_MIRACAST,\n\n#ifdef CONFIG_PNO_SUPPORT\n\tANDROID_WIFI_CMD_PNOSSIDCLR_SET,\n\tANDROID_WIFI_CMD_PNOSETUP_SET,\n\tANDROID_WIFI_CMD_PNOENABLE_SET,\n\tANDROID_WIFI_CMD_PNODEBUG_SET,\n#endif\n\n\tANDROID_WIFI_CMD_MACADDR,\n\n\tANDROID_WIFI_CMD_BLOCK_SCAN,\n\tANDROID_WIFI_CMD_BLOCK,\n\n\tANDROID_WIFI_CMD_WFD_ENABLE,\n\tANDROID_WIFI_CMD_WFD_DISABLE,\n\n\tANDROID_WIFI_CMD_WFD_SET_TCPPORT,\n\tANDROID_WIFI_CMD_WFD_SET_MAX_TPUT,\n\tANDROID_WIFI_CMD_WFD_SET_DEVTYPE,\n\tANDROID_WIFI_CMD_CHANGE_DTIM,\n\tANDROID_WIFI_CMD_HOSTAPD_SET_MACADDR_ACL,\n\tANDROID_WIFI_CMD_HOSTAPD_ACL_ADD_STA,\n\tANDROID_WIFI_CMD_HOSTAPD_ACL_REMOVE_STA,\n#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))\n\tANDROID_WIFI_CMD_GTK_REKEY_OFFLOAD,\n#endif /* CONFIG_GTK_OL */\n\tANDROID_WIFI_CMD_P2P_DISABLE,\n\tANDROID_WIFI_CMD_SET_AEK,\n\tANDROID_WIFI_CMD_EXT_AUTH_STATUS,\n\tANDROID_WIFI_CMD_DRIVERVERSION,\n\tANDROID_WIFI_CMD_MAX\n};\n\nint rtw_android_cmdstr_to_num(char *cmdstr);\nint rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd);\n\n#if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))\nint rtw_android_pno_enable(struct net_device *net, int pno_enable);\nint rtw_android_cfg80211_pno_setup(struct net_device *net,\n\t\t   struct cfg80211_ssid *ssid, int n_ssids, int interval);\n#endif\n\n#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC)\nint rtw_android_wifictrl_func_add(void);\nvoid rtw_android_wifictrl_func_del(void);\nvoid *wl_android_prealloc(int section, unsigned long size);\n\nint wifi_get_irq_number(unsigned long *irq_flags_ptr);\nint wifi_set_power(int on, unsigned long msec);\nint wifi_get_mac_addr(unsigned char *buf);\nvoid *wifi_get_country_code(char *ccode);\n#else\nstatic inline int rtw_android_wifictrl_func_add(void)\n{\n\treturn 0;\n}\nstatic inline void rtw_android_wifictrl_func_del(void) {}\n#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */\n\n#ifdef CONFIG_GPIO_WAKEUP\n#ifdef CONFIG_PLATFORM_INTEL_BYT\nint wifi_configure_gpio(void);\n#endif /* CONFIG_PLATFORM_INTEL_BYT */\nvoid wifi_free_gpio(unsigned int gpio);\n#endif /* CONFIG_GPIO_WAKEUP */\n\n\n#endif /* __RTW_ANDROID_H__ */\n"
  },
  {
    "path": "include/rtw_ap.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_AP_H_\n#define __RTW_AP_H_\n\n\n#ifdef CONFIG_AP_MODE\n\n/* external function */\nextern void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta);\nextern void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta);\n\n\nvoid init_mlme_ap_info(_adapter *padapter);\nvoid free_mlme_ap_info(_adapter *padapter);\nu8 rtw_set_tim_ie(u8 dtim_cnt, u8 dtim_period\n\t, const u8 *tim_bmp, u8 tim_bmp_len, u8 *tim_ie);\n/* void update_BCNTIM(_adapter *padapter); */\nvoid rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len);\nvoid rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index);\nvoid _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, u8 flags, const char *tag);\n#define update_beacon(adapter, ie_id, oui, tx, flags) _update_beacon((adapter), (ie_id), (oui), (tx), (flags), __func__)\n/*update_beacon - (flags) can set to normal enqueue (0) and RTW_CMDF_WAIT_ACK enqueue. \n (flags) = RTW_CMDF_DIRECTLY  is not currently implemented, it will do normal enqueue.*/\n\nvoid rtw_ap_update_sta_ra_info(_adapter *padapter, struct sta_info *psta);\n\nvoid expire_timeout_chk(_adapter *padapter);\nvoid update_sta_info_apmode(_adapter *padapter, struct sta_info *psta);\nvoid rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter);\nvoid start_bss_network(_adapter *padapter, struct createbss_parm *parm);\nint rtw_check_beacon_data(_adapter *padapter, u8 *pbuf,  int len);\nvoid rtw_ap_restore_network(_adapter *padapter);\n\n#if CONFIG_RTW_MACADDR_ACL\nvoid rtw_macaddr_acl_init(_adapter *adapter, u8 period);\nvoid rtw_macaddr_acl_deinit(_adapter *adapter, u8 period);\nvoid rtw_macaddr_acl_clear(_adapter *adapter, u8 period);\nvoid rtw_set_macaddr_acl(_adapter *adapter, u8 period, int mode);\nint rtw_acl_add_sta(_adapter *adapter, u8 period, const u8 *addr);\nint rtw_acl_remove_sta(_adapter *adapter, u8 period, const u8 *addr);\n#endif /* CONFIG_RTW_MACADDR_ACL */\n\nu8 rtw_ap_set_sta_key(_adapter *adapter, const u8 *addr, u8 alg, const u8 *key, u8 keyid, u8 gk);\nu8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta);\nint rtw_ap_set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid);\nint rtw_ap_set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid, u8 set_tx);\n\n#ifdef CONFIG_NATIVEAP_MLME\nvoid associated_clients_update(_adapter *padapter, u8 updated, u32 sta_info_type);\nvoid bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta);\nu8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta);\nvoid sta_info_update(_adapter *padapter, struct sta_info *psta);\nvoid ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta);\nu8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue);\nint rtw_sta_flush(_adapter *padapter, bool enqueue);\nint rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset);\nvoid start_ap_mode(_adapter *padapter);\nvoid stop_ap_mode(_adapter *padapter);\n#endif\n\nvoid rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset);\nu8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp\n\t, s16 req_ch, s8 req_bw, s8 req_offset, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow);\n\n#ifdef CONFIG_AUTO_AP_MODE\nvoid rtw_auto_ap_rx_msg_dump(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_pos);\nextern void rtw_start_auto_ap(_adapter *adapter);\n#endif /* CONFIG_AUTO_AP_MODE */\n\nvoid rtw_ap_parse_sta_capability(_adapter *adapter, struct sta_info *sta, u8 *cap);\nu16 rtw_ap_parse_sta_supported_rates(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len);\nu16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems);\nvoid rtw_ap_parse_sta_wmm_ie(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len);\nvoid rtw_ap_parse_sta_ht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems);\nvoid rtw_ap_parse_sta_vht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems);\n\nvoid update_bmc_sta(_adapter *padapter);\n\n#ifdef CONFIG_BMC_TX_RATE_SELECT\nvoid rtw_update_bmc_sta_tx_rate(_adapter *adapter);\n#endif\n\nvoid rtw_process_ht_action_smps(_adapter *padapter, u8 *ta, u8 ctrl_field);\nvoid rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_len);\n#ifdef CONFIG_80211N_HT\nint rtw_ht_operation_update(_adapter *padapter);\n#endif /* CONFIG_80211N_HT */\nu8 rtw_ap_sta_states_check(_adapter *adapter);\n\n#ifdef CONFIG_FW_HANDLE_TXBCN\n#define rtw_ap_get_nums(adapter)\t(adapter_to_dvobj(adapter)->nr_ap_if)\nbool rtw_ap_nums_check(_adapter *adapter);\n#endif\n\n#ifdef CONFIG_SWTIMER_BASED_TXBCN\nvoid tx_beacon_handlder(struct dvobj_priv *pdvobj);\nvoid tx_beacon_timer_handlder(void *ctx);\n#endif /*CONFIG_SWTIMER_BASED_TXBCN*/\n\n#endif /* end of CONFIG_AP_MODE */\n#endif /*__RTW_AP_H_*/\n"
  },
  {
    "path": "include/rtw_beamforming.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_BEAMFORMING_H_\n#define __RTW_BEAMFORMING_H_\n\n#ifdef CONFIG_BEAMFORMING\n\n#ifdef RTW_BEAMFORMING_VERSION_2\n#define MAX_NUM_BEAMFORMEE_SU\t2\n#define MAX_NUM_BEAMFORMER_SU\t2\n#define MAX_NUM_BEAMFORMEE_MU\t6\n#define MAX_NUM_BEAMFORMER_MU\t1\n\n#define MAX_BEAMFORMEE_ENTRY_NUM\t(MAX_NUM_BEAMFORMEE_SU + MAX_NUM_BEAMFORMEE_MU)\n#define MAX_BEAMFORMER_ENTRY_NUM\t(MAX_NUM_BEAMFORMER_SU + MAX_NUM_BEAMFORMER_MU)\n\n/* <Note> Need to be defined by IC */\n#define SU_SOUNDING_TIMEOUT\t5\t/* unit: ms */\n#define MU_SOUNDING_TIMEOUT\t8\t/* unit: ms */\n\n#define GET_BEAMFORM_INFO(adapter)\t(&GET_HAL_DATA(adapter)->beamforming_info)\n#define GetInitSoundCnt(_SoundPeriod, _MinSoundPeriod)\t((_SoundPeriod)/(_MinSoundPeriod))\n\nenum BEAMFORMING_CTRL_TYPE {\n\tBEAMFORMING_CTRL_ENTER = 0,\n\tBEAMFORMING_CTRL_LEAVE = 1,\n\tBEAMFORMING_CTRL_START_PERIOD = 2,\n\tBEAMFORMING_CTRL_END_PERIOD = 3,\n\tBEAMFORMING_CTRL_SOUNDING_FAIL = 4,\n\tBEAMFORMING_CTRL_SOUNDING_CLK = 5,\n\tBEAMFORMING_CTRL_SET_GID_TABLE = 6,\n\tBEAMFORMING_CTRL_SET_CSI_REPORT = 7,\n};\n\nenum _BEAMFORMING_STATE {\n\tBEAMFORMING_STATE_IDLE,\n\tBEAMFORMING_STATE_START,\n\tBEAMFORMING_STATE_END,\n};\n\n/*\n * typedef BEAMFORMING_CAP for phydm\n */\ntypedef enum beamforming_cap {\n\tBEAMFORMING_CAP_NONE = 0x0,\n\tBEAMFORMER_CAP_HT_EXPLICIT = 0x1,\n\tBEAMFORMEE_CAP_HT_EXPLICIT = 0x2,\n\tBEAMFORMER_CAP_VHT_SU = 0x4,\t\t\t/* Self has er Cap, because Reg er  & peer ee */\n\tBEAMFORMEE_CAP_VHT_SU = 0x8, \t\t\t/* Self has ee Cap, because Reg ee & peer er */\n\tBEAMFORMER_CAP_VHT_MU = 0x10,\t\t\t/* Self has er Cap, because Reg er & peer ee */\n\tBEAMFORMEE_CAP_VHT_MU = 0x20,\t\t\t/* Self has ee Cap, because Reg ee & peer er */\n\tBEAMFORMER_CAP = 0x40,\n\tBEAMFORMEE_CAP = 0x80,\n} BEAMFORMING_CAP;\n\nenum _BEAMFORM_ENTRY_HW_STATE {\n\tBEAMFORM_ENTRY_HW_STATE_NONE,\n\tBEAMFORM_ENTRY_HW_STATE_ADD_INIT,\n\tBEAMFORM_ENTRY_HW_STATE_ADDING,\n\tBEAMFORM_ENTRY_HW_STATE_ADDED,\n\tBEAMFORM_ENTRY_HW_STATE_DELETE_INIT,\n\tBEAMFORM_ENTRY_HW_STATE_DELETING,\n\tBEAMFORM_ENTRY_HW_STATE_MAX\n};\n\n/* The sounding state is recorded by BFer. */\nenum _SOUNDING_STATE {\n\tSOUNDING_STATE_NONE\t\t= 0,\n\tSOUNDING_STATE_INIT\t\t= 1,\n\tSOUNDING_STATE_SU_START\t\t= 2,\n\tSOUNDING_STATE_SU_SOUNDDOWN\t= 3,\n\tSOUNDING_STATE_MU_START\t\t= 4,\n\tSOUNDING_STATE_MU_SOUNDDOWN\t= 5,\n\tSOUNDING_STATE_SOUNDING_TIMEOUT\t= 6,\n\tSOUNDING_STATE_MAX\n};\n\nstruct beamformee_entry {\n\tu8 used;\t/* _TRUE/_FALSE */\n\tu8 txbf;\n\tu8 sounding;\n\t/* Used to construct AID field of NDPA packet */\n\tu16 aid;\n\t/* Used to Set Reg42C in IBSS mode */\n\tu16 mac_id;\n\t/* Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC */\n\tu16 p_aid;\n\tu8 g_id;\n\t/* Used to fill Reg6E4 to fill Mac address of CSI report frame */\n\tu8 mac_addr[ETH_ALEN];\n\t/* Sounding BandWidth */\n\tenum channel_width sound_bw;\n\tu16 sound_period;\n\n\tenum beamforming_cap cap;\n\tenum _BEAMFORM_ENTRY_HW_STATE state;\n\n\t/* The BFee need to be sounded when count to zero */\n\tu8 SoundCnt;\n\tu8 bCandidateSoundingPeer;\n\tu8 bSoundingTimeout;\n\tu8 bDeleteSounding;\n\t/* Get the result through throughput and Tx rate from BB API */\n\tu8 bApplySounding;\n\n\t/* information for sounding judgement */\n\tsystime tx_timestamp;\n\tu64 tx_bytes;\n\n\tu16 LogStatusFailCnt:5;\t/* 0~21 */\n\tu16 DefaultCSICnt:5; /* 0~21 */\n\tu8 CSIMatrix[327];\n\tu16 CSIMatrixLen;\n\n\tu8 NumofSoundingDim;\n\n\tu8 comp_steering_num_of_bfer;\n\n\n\t/* SU-MIMO */\n\tu8 su_reg_index;\n\n\t/* MU-MIMO */\n\tu8 mu_reg_index;\n\tu8 gid_valid[8];\n\tu8 user_position[16];\n\n\t/* For 8822B C-cut workaround */\n\t/* If the flag set to _TRUE, do not sound this STA */\n\tu8 bSuspendSUCap;\n};\n\nstruct beamformer_entry {\n\tu8 used;\n\t/* p_aid of BFer entry is probably not used */\n\t/* Used to fill Reg42C & Reg714 to compare with p_aid of Tx DESC */\n\tu16 p_aid;\n\tu8 g_id;\n\tu8 mac_addr[ETH_ALEN];\n\n\tenum beamforming_cap cap;\n\tenum _BEAMFORM_ENTRY_HW_STATE state;\n\n\tu8 NumofSoundingDim;\n\n\t/* SU-MIMO */\n\tu8 su_reg_index;\n\n\t/* MU-MIMO */\n\tu8 gid_valid[8];\n\tu8 user_position[16];\n\tu16 aid;\n};\n\nstruct sounding_info {\n\tu8 su_sounding_list[MAX_NUM_BEAMFORMEE_SU];\n\tu8 mu_sounding_list[MAX_NUM_BEAMFORMEE_MU];\n\n\tenum _SOUNDING_STATE state;\n\t/*\n\t * su_bfee_curidx is index for beamforming_info.bfee_entry[]\n\t * range: 0~MAX_BEAMFORMEE_ENTRY_NUM\n\t */\n\tu8 su_bfee_curidx;\n\tu8 candidate_mu_bfee_cnt;\n\n\t/* For sounding schedule maintenance */\n\tu16 min_sounding_period;\n\t/* Get from sounding list */\n\t/* Ex: SU STA1, SU STA2, MU STA(1~n) => the value will be 2+1=3 */\n\tu8 sound_remain_cnt_per_period;\n};\n\nstruct _RT_CSI_INFO{\n\tu8 Nc;\n\tu8 Nr;\n\tu8 Ng;\n\tu8 CodeBook;\n\tu8 ChnlWidth;\n\tu8 bVHT;\n};\n\nstruct beamforming_info {\n\tenum beamforming_cap beamforming_cap;\n\tenum _BEAMFORMING_STATE beamforming_state;\n\tstruct beamformee_entry bfee_entry[MAX_BEAMFORMEE_ENTRY_NUM];\n\tstruct beamformer_entry bfer_entry[MAX_BEAMFORMER_ENTRY_NUM];\n\tu8 sounding_sequence;\n\tu8 beamformee_su_cnt;\n\tu8 beamformer_su_cnt;\n\tu32 beamformee_su_reg_maping;\n\tu32 beamformer_su_reg_maping;\n\t/* For MU-MINO */\n\tu8 beamformee_mu_cnt;\n\tu8 beamformer_mu_cnt;\n\tu32 beamformee_mu_reg_maping;\n\tu8 first_mu_bfee_index;\n\tu8 mu_bfer_curidx;\n\tu8 cur_csi_rpt_rate;\n\n\tstruct sounding_info sounding_info;\n\t/* schedule regular timer for sounding */\n\t_timer sounding_timer;\n\t/* moniter if soudning too long */\n\t_timer sounding_timeout_timer;\n\n\t/* For HW configuration */\n\tu8 SetHalBFEnterOnDemandCnt;\n\tu8 SetHalBFLeaveOnDemandCnt;\n\tu8 SetHalSoundownOnDemandCnt;\n\tu8 bSetBFHwConfigInProgess;\n\n\t/*\n\t * Target CSI report info.\n\t * Keep the first SU CSI report info for 8822B HW bug workaround.\n\t */\n\tu8 bEnableSUTxBFWorkAround;\n\tstruct _RT_CSI_INFO TargetCSIInfo;\n\t/* Only peform sounding to the first SU BFee */\n\tstruct beamformee_entry *TargetSUBFee;\n\n\t/* For debug */\n\ts8 sounding_running;\n};\n\nenum beamforming_cap rtw_bf_bfee_get_entry_cap_by_macid(void *mlmepriv, u8 mac_id);\nstruct beamformer_entry *rtw_bf_bfer_get_entry_by_addr(PADAPTER, u8 *ra);\nstruct beamformee_entry *rtw_bf_bfee_get_entry_by_addr(PADAPTER, u8 *ra);\nvoid rtw_bf_get_ndpa_packet(PADAPTER, union recv_frame *);\nu32 rtw_bf_get_report_packet(PADAPTER, union recv_frame *);\nu8 rtw_bf_send_vht_gid_mgnt_packet(PADAPTER, u8 *ra, u8 *gid, u8 *position);\nvoid rtw_bf_get_vht_gid_mgnt_packet(PADAPTER, union recv_frame *);\nvoid rtw_bf_init(PADAPTER);\nvoid rtw_bf_cmd_hdl(PADAPTER, u8 type, u8 *pbuf);\nu8 rtw_bf_cmd(PADAPTER, s32 type, u8 *pbuf, s32 size, u8 enqueue);\nvoid rtw_bf_update_attrib(PADAPTER, struct pkt_attrib *, struct sta_info *);\nvoid rtw_bf_c2h_handler(PADAPTER, u8 id, u8 *buf, u8 buf_len);\nvoid rtw_bf_update_traffic(PADAPTER);\n\n/* Compatible with old function name, only for using outside rtw_beamforming.c */\n#define beamforming_get_entry_beam_cap_by_mac_id\trtw_bf_bfee_get_entry_cap_by_macid\n#define rtw_beamforming_get_ndpa_frame\t\t\trtw_bf_get_ndpa_packet\n#define rtw_beamforming_get_report_frame\t\t\trtw_bf_get_report_packet\n#define rtw_beamforming_get_vht_gid_mgnt_frame\t\trtw_bf_get_vht_gid_mgnt_packet\n#define beamforming_wk_hdl\t\t\t\trtw_bf_cmd_hdl\n#define beamforming_wk_cmd\t\t\t\trtw_bf_cmd\n#define update_attrib_txbf_info\t\t\t\trtw_bf_update_attrib\n\n#define HT_BF_CAP(adapter) ((adapter)->mlmepriv.htpriv.beamform_cap)\n#define VHT_BF_CAP(adapter) ((adapter)->mlmepriv.vhtpriv.beamform_cap)\n\n#define IS_HT_BEAMFORMEE(adapter) \\\n\t\t(HT_BF_CAP(adapter) & \\\n\t\t(BEAMFORMING_HT_BEAMFORMEE_ENABLE))\n\n#define IS_VHT_BEAMFORMEE(adapter) \\\n\t\t(VHT_BF_CAP(adapter) & \\\n\t\t(BEAMFORMING_VHT_BEAMFORMEE_ENABLE | \\\n\t\t BEAMFORMING_VHT_MU_MIMO_STA_ENABLE))\n\n#define IS_BEAMFORMEE(adapter) (IS_HT_BEAMFORMEE(adapter) | \\\n\t\t\t\tIS_VHT_BEAMFORMEE(adapter))\n\n#else /* !RTW_BEAMFORMING_VERSION_2 */\n/*PHYDM_BF - (BEAMFORMING_SUPPORT == 1)*/\nenum BEAMFORMING_CTRL_TYPE {\n\tBEAMFORMING_CTRL_ENTER = 0,\n\tBEAMFORMING_CTRL_LEAVE = 1,\n\tBEAMFORMING_CTRL_START_PERIOD = 2,\n\tBEAMFORMING_CTRL_END_PERIOD = 3,\n\tBEAMFORMING_CTRL_SOUNDING_FAIL = 4,\n\tBEAMFORMING_CTRL_SOUNDING_CLK = 5,\n};\nu32\trtw_beamforming_get_report_frame(PADAPTER\t Adapter, union recv_frame *precv_frame);\nvoid\trtw_beamforming_get_ndpa_frame(PADAPTER\t Adapter, union recv_frame *precv_frame);\n\nvoid\tbeamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf);\nu8\tbeamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enqueue);\nvoid update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta);\n\n#endif /* !RTW_BEAMFORMING_VERSION_2 */\n\n#endif /*#ifdef CONFIG_BEAMFORMING */\n\n#endif /*__RTW_BEAMFORMING_H_*/\n"
  },
  {
    "path": "include/rtw_br_ext.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTW_BR_EXT_H_\n#define _RTW_BR_EXT_H_\n\n#if 1\t/* rtw_wifi_driver */\n#define CL_IPV6_PASS\t1\n#define MACADDRLEN\t\t6\n#define _DEBUG_ERR\t\tRTW_INFO\n#define _DEBUG_INFO\t\t/* RTW_INFO */\n#define DEBUG_WARN\t\tRTW_INFO\n#define DEBUG_INFO\t\t/* RTW_INFO */\n#define DEBUG_ERR\t\tRTW_INFO\n/* #define GET_MY_HWADDR\t\t((GET_MIB(priv))->dot11OperationEntry.hwaddr) */\n#define GET_MY_HWADDR(padapter)\t\t(adapter_mac_addr(padapter))\n#endif /* rtw_wifi_driver */\n\n#define NAT25_HASH_BITS\t\t4\n#define NAT25_HASH_SIZE\t\t(1 << NAT25_HASH_BITS)\n#define NAT25_AGEING_TIME\t300\n\n#ifdef CL_IPV6_PASS\n\t#define MAX_NETWORK_ADDR_LEN\t17\n#else\n\t#define MAX_NETWORK_ADDR_LEN\t11\n#endif\n\nstruct nat25_network_db_entry {\n\tstruct nat25_network_db_entry\t*next_hash;\n\tstruct nat25_network_db_entry\t**pprev_hash;\n\tatomic_t\t\t\t\t\t\tuse_count;\n\tunsigned char\t\t\t\t\tmacAddr[6];\n\tunsigned long\t\t\t\t\tageing_timer;\n\tunsigned char\t\t\t\tnetworkAddr[MAX_NETWORK_ADDR_LEN];\n};\n\nenum NAT25_METHOD {\n\tNAT25_MIN,\n\tNAT25_CHECK,\n\tNAT25_INSERT,\n\tNAT25_LOOKUP,\n\tNAT25_PARSE,\n\tNAT25_MAX\n};\n\nstruct br_ext_info {\n\tunsigned int\tnat25_disable;\n\tunsigned int\tmacclone_enable;\n\tunsigned int\tdhcp_bcst_disable;\n\tint\t\taddPPPoETag;\t\t/* 1: Add PPPoE relay-SID, 0: disable */\n\tunsigned char\tnat25_dmzMac[MACADDRLEN];\n\tunsigned int\tnat25sc_disable;\n};\n\nvoid nat25_db_cleanup(_adapter *priv);\n\n#endif /* _RTW_BR_EXT_H_ */\n"
  },
  {
    "path": "include/rtw_bt_mp.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef __RTW_BT_MP_H\n#define __RTW_BT_MP_H\n\n\n#if (MP_DRIVER == 1)\n\n#pragma pack(1)\n\n/* definition for BT_UP_OP_BT_READY */\n#define\tMP_BT_NOT_READY\t\t\t\t\t\t0\n#define\tMP_BT_READY\t\t\t\t\t\t\t1\n\n/* definition for BT_UP_OP_BT_SET_MODE */\ntypedef enum _MP_BT_MODE {\n\tMP_BT_MODE_RF_TXRX_TEST_MODE\t\t\t\t\t\t\t= 0,\n\tMP_BT_MODE_BT20_DUT_TEST_MODE\t\t\t\t\t\t\t= 1,\n\tMP_BT_MODE_BT40_DIRECT_TEST_MODE\t\t\t\t\t\t= 2,\n\tMP_BT_MODE_CONNECT_TEST_MODE\t\t\t\t\t\t\t= 3,\n\tMP_BT_MODE_MAX\n} MP_BT_MODE, *PMP_BT_MODE;\n\n\n/* definition for BT_UP_OP_BT_SET_TX_RX_PARAMETER */\ntypedef struct _BT_TXRX_PARAMETERS {\n\tu8\t\ttxrxChannel;\n\tu32\t\ttxrxTxPktCnt;\n\tu8\t\ttxrxTxPktInterval;\n\tu8\t\ttxrxPayloadType;\n\tu8\t\ttxrxPktType;\n\tu16\t\ttxrxPayloadLen;\n\tu32\t\ttxrxPktHeader;\n\tu8\t\ttxrxWhitenCoeff;\n\tu8\t\ttxrxBdaddr[6];\n\tu8\t\ttxrxTxGainIndex;\n} BT_TXRX_PARAMETERS, *PBT_TXRX_PARAMETERS;\n\n/* txrxPktType */\ntypedef enum _MP_BT_PKT_TYPE {\n\tMP_BT_PKT_DH1\t\t\t\t\t\t\t= 0,\n\tMP_BT_PKT_DH3\t\t\t\t\t\t\t= 1,\n\tMP_BT_PKT_DH5\t\t\t\t\t\t\t= 2,\n\tMP_BT_PKT_2DH1\t\t\t\t\t\t\t= 3,\n\tMP_BT_PKT_2DH3\t\t\t\t\t\t\t= 4,\n\tMP_BT_PKT_2DH5\t\t\t\t\t\t\t= 5,\n\tMP_BT_PKT_3DH1\t\t\t\t\t\t\t= 6,\n\tMP_BT_PKT_3DH3\t\t\t\t\t\t\t= 7,\n\tMP_BT_PKT_3DH5\t\t\t\t\t\t\t= 8,\n\tMP_BT_PKT_LE\t\t\t\t\t\t\t= 9,\n\tMP_BT_PKT_MAX\n} MP_BT_PKT_TYPE, *PMP_BT_PKT_TYPE;\n/* txrxPayloadType */\ntypedef enum _MP_BT_PAYLOAD_TYPE {\n\tMP_BT_PAYLOAD_01010101\t\t\t\t\t= 0,\n\tMP_BT_PAYLOAD_ALL_1\t\t\t\t\t\t= 1,\n\tMP_BT_PAYLOAD_ALL_0\t\t\t\t\t\t= 2,\n\tMP_BT_PAYLOAD_11110000\t\t\t\t\t= 3,\n\tMP_BT_PAYLOAD_PRBS9\t\t\t\t\t\t= 4,\n\tMP_BT_PAYLOAD_MAX\t\t\t\t\t\t= 8,\n} MP_BT_PAYLOAD_TYPE, *PMP_BT_PAYLOAD_TYPE;\n\n\n/* definition for BT_UP_OP_BT_TEST_CTRL */\ntypedef enum _MP_BT_TEST_CTRL {\n\tMP_BT_TEST_STOP_ALL_TESTS\t\t\t\t\t\t= 0,\n\tMP_BT_TEST_START_RX_TEST\t\t\t\t\t\t= 1,\n\tMP_BT_TEST_START_PACKET_TX_TEST\t\t\t\t\t= 2,\n\tMP_BT_TEST_START_CONTINUOUS_TX_TEST\t\t\t= 3,\n\tMP_BT_TEST_START_INQUIRY_SCAN_TEST\t\t\t\t= 4,\n\tMP_BT_TEST_START_PAGE_SCAN_TEST\t\t\t\t\t= 5,\n\tMP_BT_TEST_START_INQUIRY_PAGE_SCAN_TEST\t\t\t= 6,\n\tMP_BT_TEST_START_LEGACY_CONNECT_TEST\t\t\t= 7,\n\tMP_BT_TEST_START_LE_CONNECT_TEST_INITIATOR\t\t= 8,\n\tMP_BT_TEST_START_LE_CONNECT_TEST_ADVERTISER\t= 9,\n\tMP_BT_TEST_MAX\n} MP_BT_TEST_CTRL, *PMP_BT_TEST_CTRL;\n\n\ntypedef enum _RTL_EXT_C2H_EVT {\n\tEXT_C2H_WIFI_FW_ACTIVE_RSP = 0,\n\tEXT_C2H_TRIG_BY_BT_FW = 1,\n\tMAX_EXT_C2HEVENT\n} RTL_EXT_C2H_EVT;\n\n/* OP codes definition between the user layer and driver */\ntypedef enum _BT_CTRL_OPCODE_UPPER {\n\tBT_UP_OP_BT_READY\t\t\t\t\t\t\t\t\t\t= 0x00,\n\tBT_UP_OP_BT_SET_MODE\t\t\t\t\t\t\t\t\t= 0x01,\n\tBT_UP_OP_BT_SET_TX_RX_PARAMETER\t\t\t\t\t\t= 0x02,\n\tBT_UP_OP_BT_SET_GENERAL\t\t\t\t\t\t\t\t= 0x03,\n\tBT_UP_OP_BT_GET_GENERAL\t\t\t\t\t\t\t\t= 0x04,\n\tBT_UP_OP_BT_TEST_CTRL\t\t\t\t\t\t\t\t\t= 0x05,\n\tBT_UP_OP_TEST_BT\t\t\t\t\t\t\t\t\t\t= 0x06,\n\tBT_UP_OP_MAX\n} BT_CTRL_OPCODE_UPPER, *PBT_CTRL_OPCODE_UPPER;\n\n\ntypedef enum _BT_SET_GENERAL {\n\tBT_GSET_REG\t\t\t\t\t\t\t\t\t\t\t= 0x00,\n\tBT_GSET_RESET\t\t\t\t\t\t\t\t\t\t\t= 0x01,\n\tBT_GSET_TARGET_BD_ADDR\t\t\t\t\t\t\t\t\t= 0x02,\n\tBT_GSET_TX_PWR_FINETUNE\t\t\t\t\t\t\t\t= 0x03,\n\tBT_SET_TRACKING_INTERVAL\t\t\t\t\t\t\t\t= 0x04,\n\tBT_SET_THERMAL_METER\t\t\t\t\t\t\t\t\t= 0x05,\n\tBT_ENABLE_CFO_TRACKING\t\t\t\t\t\t\t\t\t= 0x06,\n\tBT_GSET_UPDATE_BT_PATCH\t\t\t\t\t\t\t\t= 0x07,\n\tBT_GSET_MAX\n} BT_SET_GENERAL, *PBT_SET_GENERAL;\n\ntypedef enum _BT_GET_GENERAL {\n\tBT_GGET_REG\t\t\t\t\t\t\t\t\t\t\t= 0x00,\n\tBT_GGET_STATUS\t\t\t\t\t\t\t\t\t\t\t= 0x01,\n\tBT_GGET_REPORT\t\t\t\t\t\t\t\t\t\t\t= 0x02,\n\tBT_GGET_AFH_MAP\t\t\t\t\t\t\t\t\t\t= 0x03,\n\tBT_GGET_AFH_STATUS\t\t\t\t\t\t\t\t\t\t= 0x04,\n\tBT_GGET_MAX\n} BT_GET_GENERAL, *PBT_GET_GENERAL;\n\n/* definition for BT_UP_OP_BT_SET_GENERAL */\ntypedef enum _BT_REG_TYPE {\n\tBT_REG_RF\t\t\t\t\t\t\t\t= 0,\n\tBT_REG_MODEM\t\t\t\t\t\t\t= 1,\n\tBT_REG_BLUEWIZE\t\t\t\t\t\t= 2,\n\tBT_REG_VENDOR\t\t\t\t\t\t\t= 3,\n\tBT_REG_LE\t\t\t\t\t\t\t\t= 4,\n\tBT_REG_MAX\n} BT_REG_TYPE, *PBT_REG_TYPE;\n\n/* definition for BT_LO_OP_GET_AFH_MAP */\ntypedef enum _BT_AFH_MAP_TYPE {\n\tBT_AFH_MAP_RESULT\t\t\t\t\t\t= 0,\n\tBT_AFH_MAP_WIFI_PSD_ONLY\t\t\t\t= 1,\n\tBT_AFH_MAP_WIFI_CH_BW_ONLY\t\t\t\t= 2,\n\tBT_AFH_MAP_BT_PSD_ONLY\t\t\t\t\t= 3,\n\tBT_AFH_MAP_HOST_CLASSIFICATION_ONLY\t= 4,\n\tBT_AFH_MAP_MAX\n} BT_AFH_MAP_TYPE, *PBT_AFH_MAP_TYPE;\n\n/* definition for BT_UP_OP_BT_GET_GENERAL */\ntypedef enum _BT_REPORT_TYPE {\n\tBT_REPORT_RX_PACKET_CNT\t\t\t\t= 0,\n\tBT_REPORT_RX_ERROR_BITS\t\t\t\t= 1,\n\tBT_REPORT_RSSI\t\t\t\t\t\t\t= 2,\n\tBT_REPORT_CFO_HDR_QUALITY\t\t\t\t= 3,\n\tBT_REPORT_CONNECT_TARGET_BD_ADDR\t\t= 4,\n\tBT_REPORT_MAX\n} BT_REPORT_TYPE, *PBT_REPORT_TYPE;\n\nvoid\nMPTBT_Test(\n\t\tPADAPTER\tAdapter,\n\t\tu8\t\topCode,\n\t\tu8\t\tbyte1,\n\t\tu8\t\tbyte2,\n\t\tu8\t\tbyte3\n);\n\nuint\nMPTBT_SendOidBT(\n\t\tPADAPTER\t\tpAdapter,\n\t\tvoid\t\t\t\t*InformationBuffer,\n\t\tu32\t\t\t\tInformationBufferLength,\n\t\tu32 \t\t\t\t*BytesRead,\n\t\tu32 \t\t\t\t*BytesNeeded\n);\n\nvoid\nMPTBT_FwC2hBtMpCtrl(\n\tPADAPTER\tAdapter,\n\tu8 \t\t\t*tmpBuf,\n\tu8\t\t\tlength\n);\n\nvoid MPh2c_timeout_handle(void *FunctionContext);\n\nvoid mptbt_BtControlProcess(\n\tPADAPTER\tAdapter,\n\tvoid\t\t\t*pInBuf\n);\n\n#define\tBT_H2C_MAX_RETRY\t\t\t\t\t\t\t\t1\n#define\tBT_MAX_C2H_LEN\t\t\t\t\t\t\t\t20\n\ntypedef struct _BT_REQ_CMD {\n\tu8       opCodeVer;\n\tu8       OpCode;\n\tu16      paraLength;\n\tu8       pParamStart[100];\n} BT_REQ_CMD, *PBT_REQ_CMD;\n\ntypedef struct _BT_RSP_CMD {\n\tu16      status;\n\tu16      paraLength;\n\tu8       pParamStart[100];\n} BT_RSP_CMD, *PBT_RSP_CMD;\n\n\ntypedef struct _BT_H2C {\n\tu8\topCodeVer:4;\n\tu8\treqNum:4;\n\tu8\topCode;\n\tu8\tbuf[100];\n} BT_H2C, *PBT_H2C;\n\n\n\ntypedef struct _BT_EXT_C2H {\n\tu8\textendId;\n\tu8\tstatusCode:4;\n\tu8\tretLen:4;\n\tu8\topCodeVer:4;\n\tu8\treqNum:4;\n\tu8\tbuf[100];\n} BT_EXT_C2H, *PBT_EXT_C2H;\n\n\ntypedef enum _BT_OPCODE_STATUS {\n\tBT_OP_STATUS_SUCCESS\t\t\t\t\t\t\t\t\t= 0x00, /* Success */\n\tBT_OP_STATUS_VERSION_MISMATCH\t\t\t\t\t\t\t= 0x01,\n\tBT_OP_STATUS_UNKNOWN_OPCODE\t\t\t\t\t\t\t\t= 0x02,\n\tBT_OP_STATUS_ERROR_PARAMETER\t\t\t\t\t\t\t= 0x03,\n\tBT_OP_STATUS_MAX\n} BT_OPCODE_STATUS, *PBT_OPCODE_STATUS;\n\n\n\n/* OP codes definition between driver and bt fw */\ntypedef enum _BT_CTRL_OPCODE_LOWER {\n\tBT_LO_OP_GET_BT_VERSION\t\t\t\t\t\t\t\t\t= 0x00,\n\tBT_LO_OP_RESET\t\t\t\t\t\t\t\t\t\t\t\t= 0x01,\n\tBT_LO_OP_TEST_CTRL\t\t\t\t\t\t\t\t\t\t\t= 0x02,\n\tBT_LO_OP_SET_BT_MODE\t\t\t\t\t\t\t\t\t\t= 0x03,\n\tBT_LO_OP_SET_CHNL_TX_GAIN\t\t\t\t\t\t\t\t\t= 0x04,\n\tBT_LO_OP_SET_PKT_TYPE_LEN\t\t\t\t\t\t\t\t\t= 0x05,\n\tBT_LO_OP_SET_PKT_CNT_L_PL_TYPE\t\t\t\t\t\t\t\t= 0x06,\n\tBT_LO_OP_SET_PKT_CNT_H_PKT_INTV\t\t\t\t\t\t\t= 0x07,\n\tBT_LO_OP_SET_PKT_HEADER\t\t\t\t\t\t\t\t\t= 0x08,\n\tBT_LO_OP_SET_WHITENCOEFF\t\t\t\t\t\t\t\t\t= 0x09,\n\tBT_LO_OP_SET_BD_ADDR_L\t\t\t\t\t\t\t\t\t\t= 0x0a,\n\tBT_LO_OP_SET_BD_ADDR_H\t\t\t\t\t\t\t\t\t\t= 0x0b,\n\tBT_LO_OP_WRITE_REG_ADDR\t\t\t\t\t\t\t\t\t= 0x0c,\n\tBT_LO_OP_WRITE_REG_VALUE\t\t\t\t\t\t\t\t\t= 0x0d,\n\tBT_LO_OP_GET_BT_STATUS\t\t\t\t\t\t\t\t\t\t= 0x0e,\n\tBT_LO_OP_GET_BD_ADDR_L\t\t\t\t\t\t\t\t\t\t= 0x0f,\n\tBT_LO_OP_GET_BD_ADDR_H\t\t\t\t\t\t\t\t\t\t= 0x10,\n\tBT_LO_OP_READ_REG\t\t\t\t\t\t\t\t\t\t\t= 0x11,\n\tBT_LO_OP_SET_TARGET_BD_ADDR_L\t\t\t\t\t\t\t\t= 0x12,\n\tBT_LO_OP_SET_TARGET_BD_ADDR_H\t\t\t\t\t\t\t\t= 0x13,\n\tBT_LO_OP_SET_TX_POWER_CALIBRATION\t\t\t\t\t\t\t= 0x14,\n\tBT_LO_OP_GET_RX_PKT_CNT_L\t\t\t\t\t\t\t\t\t= 0x15,\n\tBT_LO_OP_GET_RX_PKT_CNT_H\t\t\t\t\t\t\t\t\t= 0x16,\n\tBT_LO_OP_GET_RX_ERROR_BITS_L\t\t\t\t\t\t\t\t= 0x17,\n\tBT_LO_OP_GET_RX_ERROR_BITS_H\t\t\t\t\t\t\t\t= 0x18,\n\tBT_LO_OP_GET_RSSI\t\t\t\t\t\t\t\t\t\t\t= 0x19,\n\tBT_LO_OP_GET_CFO_HDR_QUALITY_L\t\t\t\t\t\t\t\t= 0x1a,\n\tBT_LO_OP_GET_CFO_HDR_QUALITY_H\t\t\t\t\t\t\t\t= 0x1b,\n\tBT_LO_OP_GET_TARGET_BD_ADDR_L\t\t\t\t\t\t\t\t= 0x1c,\n\tBT_LO_OP_GET_TARGET_BD_ADDR_H\t\t\t\t\t\t\t\t= 0x1d,\n\tBT_LO_OP_GET_AFH_MAP_L\t\t\t\t\t\t\t\t\t\t= 0x1e,\n\tBT_LO_OP_GET_AFH_MAP_M\t\t\t\t\t\t\t\t\t\t= 0x1f,\n\tBT_LO_OP_GET_AFH_MAP_H\t\t\t\t\t\t\t\t\t\t= 0x20,\n\tBT_LO_OP_GET_AFH_STATUS\t\t\t\t\t\t\t\t\t= 0x21,\n\tBT_LO_OP_SET_TRACKING_INTERVAL\t\t\t\t\t\t\t\t= 0x22,\n\tBT_LO_OP_SET_THERMAL_METER\t\t\t\t\t\t\t\t\t= 0x23,\n\tBT_LO_OP_ENABLE_CFO_TRACKING\t\t\t\t\t\t\t\t= 0x24,\n\tBT_LO_OP_MAX\n} BT_CTRL_OPCODE_LOWER, *PBT_CTRL_OPCODE_LOWER;\n\n\n\n\n#endif  /* #if(MP_DRIVER == 1) */\n\n#endif /*  #ifndef __INC_MPT_BT_H */\n"
  },
  {
    "path": "include/rtw_btcoex.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifdef CONFIG_BT_COEXIST\n\n#ifndef __RTW_BTCOEX_H__\n#define __RTW_BTCOEX_H__\n\n#include <drv_types.h>\n\n/* For H2C: H2C_BT_MP_OPER. Return status definition to the user layer */\ntypedef enum _BT_CTRL_STATUS {\n\tBT_STATUS_SUCCESS\t\t\t\t\t\t\t\t= 0x00, /* Success */\n\tBT_STATUS_BT_OP_SUCCESS\t\t\t\t\t\t\t= 0x01, /* bt fw op execution success */\n\tBT_STATUS_H2C_SUCCESS\t\t\t\t\t\t\t= 0x02, /* H2c success */\n\tBT_STATUS_H2C_FAIL\t\t\t\t\t\t\t\t= 0x03, /* H2c fail */\n\tBT_STATUS_H2C_LENGTH_EXCEEDED\t\t\t\t\t= 0x04, /* H2c command length exceeded */\n\tBT_STATUS_H2C_TIMTOUT\t\t\t\t\t\t\t= 0x05, /* H2c timeout */\n\tBT_STATUS_H2C_BT_NO_RSP\t\t\t\t\t\t\t= 0x06, /* H2c sent, bt no rsp */\n\tBT_STATUS_C2H_SUCCESS\t\t\t\t\t\t\t= 0x07, /* C2h success */\n\tBT_STATUS_C2H_REQNUM_MISMATCH\t\t\t\t\t= 0x08, /* bt fw wrong rsp */\n\tBT_STATUS_OPCODE_U_VERSION_MISMATCH\t\t\t\t= 0x08, /* Upper layer OP code version mismatch. */\n\tBT_STATUS_OPCODE_L_VERSION_MISMATCH\t\t\t\t= 0x0a, /* Lower layer OP code version mismatch. */\n\tBT_STATUS_UNKNOWN_OPCODE_U\t\t\t\t\t\t= 0x0b, /* Unknown Upper layer OP code */\n\tBT_STATUS_UNKNOWN_OPCODE_L\t\t\t\t\t\t= 0x0c, /* Unknown Lower layer OP code */\n\tBT_STATUS_PARAMETER_FORMAT_ERROR_U\t\t\t\t= 0x0d, /* Wrong parameters sent by upper layer. */\n\tBT_STATUS_PARAMETER_FORMAT_ERROR_L\t\t\t\t= 0x0e, /* bt fw parameter format is not consistency */\n\tBT_STATUS_PARAMETER_OUT_OF_RANGE_U\t\t\t\t= 0x0f, /* uppery layer parameter value is out of range */\n\tBT_STATUS_PARAMETER_OUT_OF_RANGE_L\t\t\t\t= 0x10, /* bt fw parameter value is out of range */\n\tBT_STATUS_UNKNOWN_STATUS_L\t\t\t\t\t\t= 0x11, /* bt returned an defined status code */\n\tBT_STATUS_UNKNOWN_STATUS_H\t\t\t\t\t\t= 0x12, /* driver need to do error handle or not handle-well. */\n\tBT_STATUS_WRONG_LEVEL\t\t\t\t\t\t\t= 0x13, /* should be under passive level */\n\tBT_STATUS_NOT_IMPLEMENT\t\t\t\t\t\t= 0x14, /* op code not implemented yet */\n\tBT_STATUS_BT_STACK_OP_SUCCESS\t\t\t\t\t= 0x15, /* bt stack op execution success */\n\tBT_STATUS_BT_STACK_NOT_SUPPORT\t\t\t\t\t= 0x16, /* stack version not support this. */\n\tBT_STATUS_BT_STACK_SEND_HCI_EVENT_FAIL\t\t\t= 0x17, /* send hci event fail */\n\tBT_STATUS_BT_STACK_NOT_BIND\t\t\t\t\t\t= 0x18, /* stack not bind wifi driver */\n\tBT_STATUS_BT_STACK_NO_RSP\t\t\t\t\t\t= 0x19, /* stack doesn't have any rsp. */\n\tBT_STATUS_MAX\n} BT_CTRL_STATUS, *PBT_CTRL_STATUS;\n\ntypedef enum _BTCOEX_SUSPEND_STATE {\n\tBTCOEX_SUSPEND_STATE_RESUME\t\t\t\t\t= 0x0,\n\tBTCOEX_SUSPEND_STATE_SUSPEND\t\t\t\t= 0x1,\n\tBTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT\t\t= 0x2,\n\tBTCOEX_SUSPEND_STATE_MAX\n} BTCOEX_SUSPEND_STATE, *PBTCOEX_SUSPEND_STATE;\n\n#define SET_BT_MP_OPER_RET(OpCode, StatusCode)\t\t\t\t\t\t((OpCode << 8) | StatusCode)\n#define GET_OP_CODE_FROM_BT_MP_OPER_RET(RetCode)\t\t\t\t\t((RetCode & 0xF0) >> 8)\n#define GET_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode)\t\t\t\t(RetCode & 0x0F)\n#define CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode, StatusCode)\t(GET_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode) == StatusCode)\n\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\n#define NETLINK_USER 31\n#define CONNECT_PORT 30000\n#define CONNECT_PORT_BT 30001\n#define KERNEL_SOCKET_OK 0x01\n#define NETLINK_SOCKET_OK 0x02\n\n#define OTHER 0\n#define RX_ATTEND_ACK 1\n#define RX_LEAVE_ACK 2\n#define RX_BT_LEAVE 3\n#define RX_INVITE_REQ 4\n#define RX_ATTEND_REQ 5\n#define RX_INVITE_RSP 6\n\n#define invite_req \"INVITE_REQ\"\n#define invite_rsp \"INVITE_RSP\"\n#define attend_req \"ATTEND_REQ\"\n#define attend_ack \"ATTEND_ACK\"\n#define wifi_leave \"WIFI_LEAVE\"\n#define leave_ack \"LEAVE_ACK\"\n#define bt_leave \"BT_LEAVE\"\n\n#define BT_INFO_NOTIFY_CMD 0x0106\n#define BT_INFO_LEN 8\n\ntypedef struct _HCI_LINK_INFO {\n\tu16\t\t\t\t\tConnectHandle;\n\tu8\t\t\t\t\tIncomingTrafficMode;\n\tu8\t\t\t\t\tOutgoingTrafficMode;\n\tu8\t\t\t\t\tBTProfile;\n\tu8\t\t\t\t\tBTCoreSpec;\n\ts8\t\t\t\t\tBT_RSSI;\n\tu8\t\t\t\t\tTrafficProfile;\n\tu8\t\t\t\t\tlinkRole;\n} HCI_LINK_INFO, *PHCI_LINK_INFO;\n\n#define\tMAX_BT_ACL_LINK_NUM\t\t\t\t8\n\ntypedef struct _HCI_EXT_CONFIG {\n\tHCI_LINK_INFO\t\t\t\taclLink[MAX_BT_ACL_LINK_NUM];\n\tu8\t\t\t\t\tbtOperationCode;\n\tu16\t\t\t\t\tCurrentConnectHandle;\n\tu8\t\t\t\t\tCurrentIncomingTrafficMode;\n\tu8\t\t\t\t\tCurrentOutgoingTrafficMode;\n\n\tu8\t\t\t\t\tNumberOfACL;\n\tu8\t\t\t\t\tNumberOfSCO;\n\tu8\t\t\t\t\tCurrentBTStatus;\n\tu16\t\t\t\t\tHCIExtensionVer;\n\n\tBOOLEAN\t\t\t\t\tbEnableWifiScanNotify;\n} HCI_EXT_CONFIG, *PHCI_EXT_CONFIG;\n\ntypedef struct _HCI_PHY_LINK_BSS_INFO {\n\tu16\t\t\t\t\t\tbdCap;\t\t\t/* capability information */\n\n\t/* Qos related. Added by Annie, 2005-11-01. */\n\t/* BSS_QOS\t\t\t\t\t\tBssQos;\t\t */\n\n} HCI_PHY_LINK_BSS_INFO, *PHCI_PHY_LINK_BSS_INFO;\n\ntypedef enum _BT_CONNECT_TYPE {\n\tBT_CONNECT_AUTH_REQ\t\t\t\t\t\t\t\t= 0x00,\n\tBT_CONNECT_AUTH_RSP\t\t\t\t\t\t\t\t= 0x01,\n\tBT_CONNECT_ASOC_REQ\t\t\t\t\t\t\t\t= 0x02,\n\tBT_CONNECT_ASOC_RSP\t\t\t\t\t\t\t\t= 0x03,\n\tBT_DISCONNECT\t\t\t\t\t\t\t\t\t\t= 0x04\n} BT_CONNECT_TYPE, *PBT_CONNECT_TYPE;\n\n\ntypedef struct _PACKET_IRP_HCIEVENT_DATA {\n\tu8\t\tEventCode;\n\tu8\t\tLength; /* total cmd length = extension event length+1(extension event code length) */\n\tu8\t\tData[1]; /* byte1 is extension event code */\n} rtw_HCI_event;\n\n\nstruct btinfo_8761ATV {\n\tu8 cid;\n\tu8 len;\n\n\tu8 bConnection:1;\n\tu8 bSCOeSCO:1;\n\tu8 bInQPage:1;\n\tu8 bACLBusy:1;\n\tu8 bSCOBusy:1;\n\tu8 bHID:1;\n\tu8 bA2DP:1;\n\tu8 bFTP:1;\n\n\tu8 retry_cnt:4;\n\tu8 rsvd_34:1;\n\tu8 bPage:1;\n\tu8 TRxMask:1;\n\tu8 Sniff_attempt:1;\n\n\tu8 rssi;\n\n\tu8 A2dp_rate:1;\n\tu8 ReInit:1;\n\tu8 MaxPower:1;\n\tu8 bEnIgnoreWlanAct:1;\n\tu8 TxPowerLow:1;\n\tu8 TxPowerHigh:1;\n\tu8 eSCO_SCO:1;\n\tu8 Master_Slave:1;\n\n\tu8 ACL_TRx_TP_low;\n\tu8 ACL_TRx_TP_high;\n};\n\n#define HCIOPCODE(_OCF, _OGF)     ((_OGF)<<10|(_OCF))\n#define HCIOPCODELOW(_OCF, _OGF)\t(u8)(HCIOPCODE(_OCF, _OGF) & 0x00ff)\n#define HCIOPCODEHIGHT(_OCF, _OGF) (u8)(HCIOPCODE(_OCF, _OGF)>>8)\n#define HCI_OGF(opCode)  (unsigned char)((0xFC00 & (opCode)) >> 10)\n#define HCI_OCF(opCode)  (0x3FF & (opCode))\n\n\ntypedef enum _HCI_STATUS {\n\tHCI_STATUS_SUCCESS\t\t\t\t\t\t\t\t\t\t= 0x00, /* Success */\n\tHCI_STATUS_UNKNOW_HCI_CMD\t\t\t\t\t\t\t\t= 0x01, /* Unknown HCI Command */\n\tHCI_STATUS_UNKNOW_CONNECT_ID\t\t\t\t\t\t\t= 0X02, /* Unknown Connection Identifier */\n\tHCI_STATUS_HW_FAIL\t\t\t\t\t\t\t\t\t\t= 0X03, /* Hardware Failure */\n\tHCI_STATUS_PAGE_TIMEOUT\t\t\t\t\t\t\t\t\t= 0X04, /* Page Timeout */\n\tHCI_STATUS_AUTH_FAIL\t\t\t\t\t\t\t\t\t\t= 0X05, /* Authentication Failure */\n\tHCI_STATUS_PIN_OR_KEY_MISSING\t\t\t\t\t\t\t= 0X06, /* PIN or Key Missing */\n\tHCI_STATUS_MEM_CAP_EXCEED\t\t\t\t\t\t\t\t= 0X07, /* Memory Capacity Exceeded */\n\tHCI_STATUS_CONNECT_TIMEOUT\t\t\t\t\t\t\t\t= 0X08, /* Connection Timeout */\n\tHCI_STATUS_CONNECT_LIMIT\t\t\t\t\t\t\t\t\t= 0X09, /* Connection Limit Exceeded */\n\tHCI_STATUS_SYN_CONNECT_LIMIT\t\t\t\t\t\t\t\t= 0X0a, /* Synchronous Connection Limit To A Device Exceeded */\n\tHCI_STATUS_ACL_CONNECT_EXISTS\t\t\t\t\t\t\t= 0X0b, /* ACL Connection Already Exists */\n\tHCI_STATUS_CMD_DISALLOW\t\t\t\t\t\t\t\t\t= 0X0c, /* Command Disallowed */\n\tHCI_STATUS_CONNECT_RJT_LIMIT_RESOURCE\t\t\t\t\t= 0X0d, /* Connection Rejected due to Limited Resources */\n\tHCI_STATUS_CONNECT_RJT_SEC_REASON\t\t\t\t\t\t= 0X0e, /* Connection Rejected Due To Security Reasons */\n\tHCI_STATUS_CONNECT_RJT_UNACCEPT_BD_ADDR\t\t\t\t= 0X0f, /* Connection Rejected due to Unacceptable BD_ADDR */\n\tHCI_STATUS_CONNECT_ACCEPT_TIMEOUT\t\t\t\t\t\t= 0X10, /* Connection Accept Timeout Exceeded */\n\tHCI_STATUS_UNSUPPORT_FEATURE_PARA_VALUE\t\t\t\t= 0X11, /* Unsupported Feature or Parameter Value */\n\tHCI_STATUS_INVALID_HCI_CMD_PARA_VALUE\t\t\t\t\t= 0X12, /* Invalid HCI Command Parameters */\n\tHCI_STATUS_REMOTE_USER_TERMINATE_CONNECT\t\t\t\t= 0X13, /* Remote User Terminated Connection */\n\tHCI_STATUS_REMOTE_DEV_TERMINATE_LOW_RESOURCE\t\t\t= 0X14, /* Remote Device Terminated Connection due to Low Resources */\n\tHCI_STATUS_REMOTE_DEV_TERMINATE_CONNECT_POWER_OFF\t= 0X15, /* Remote Device Terminated Connection due to Power Off */\n\tHCI_STATUS_CONNECT_TERMINATE_LOCAL_HOST\t\t\t\t= 0X16, /* Connection Terminated By Local Host */\n\tHCI_STATUS_REPEATE_ATTEMPT\t\t\t\t\t\t\t\t= 0X17, /* Repeated Attempts */\n\tHCI_STATUS_PAIR_NOT_ALLOW\t\t\t\t\t\t\t\t= 0X18, /* Pairing Not Allowed */\n\tHCI_STATUS_UNKNOW_LMP_PDU\t\t\t\t\t\t\t\t= 0X19, /* Unknown LMP PDU */\n\tHCI_STATUS_UNSUPPORT_REMOTE_LMP_FEATURE\t\t\t\t= 0X1a, /* Unsupported Remote Feature / Unsupported LMP Feature */\n\tHCI_STATUS_SOC_OFFSET_REJECT\t\t\t\t\t\t\t\t= 0X1b, /* SCO Offset Rejected */\n\tHCI_STATUS_SOC_INTERVAL_REJECT\t\t\t\t\t\t\t= 0X1c, /* SCO Interval Rejected */\n\tHCI_STATUS_SOC_AIR_MODE_REJECT\t\t\t\t\t\t\t= 0X1d, /* SCO Air Mode Rejected */\n\tHCI_STATUS_INVALID_LMP_PARA\t\t\t\t\t\t\t\t= 0X1e, /* Invalid LMP Parameters */\n\tHCI_STATUS_UNSPECIFIC_ERROR\t\t\t\t\t\t\t\t= 0X1f, /* Unspecified Error */\n\tHCI_STATUS_UNSUPPORT_LMP_PARA_VALUE\t\t\t\t\t= 0X20, /* Unsupported LMP Parameter Value */\n\tHCI_STATUS_ROLE_CHANGE_NOT_ALLOW\t\t\t\t\t\t= 0X21, /* Role Change Not Allowed */\n\tHCI_STATUS_LMP_RESPONSE_TIMEOUT\t\t\t\t\t\t\t= 0X22, /* LMP Response Timeout */\n\tHCI_STATUS_LMP_ERROR_TRANSACTION_COLLISION\t\t\t\t= 0X23, /* LMP Error Transaction Collision */\n\tHCI_STATUS_LMP_PDU_NOT_ALLOW\t\t\t\t\t\t\t= 0X24, /* LMP PDU Not Allowed */\n\tHCI_STATUS_ENCRYPTION_MODE_NOT_ALLOW\t\t\t\t\t= 0X25, /* Encryption Mode Not Acceptable */\n\tHCI_STATUS_LINK_KEY_CAN_NOT_CHANGE\t\t\t\t\t\t= 0X26, /* Link Key Can Not be Changed */\n\tHCI_STATUS_REQUEST_QOS_NOT_SUPPORT\t\t\t\t\t\t= 0X27, /* Requested QoS Not Supported */\n\tHCI_STATUS_INSTANT_PASSED\t\t\t\t\t\t\t\t= 0X28, /* Instant Passed */\n\tHCI_STATUS_PAIRING_UNIT_KEY_NOT_SUPPORT\t\t\t\t\t= 0X29, /* Pairing With Unit Key Not Supported */\n\tHCI_STATUS_DIFFERENT_TRANSACTION_COLLISION\t\t\t\t= 0X2a, /* Different Transaction Collision */\n\tHCI_STATUS_RESERVE_1\t\t\t\t\t\t\t\t\t\t= 0X2b, /* Reserved */\n\tHCI_STATUS_QOS_UNACCEPT_PARA\t\t\t\t\t\t\t= 0X2c, /* QoS Unacceptable Parameter */\n\tHCI_STATUS_QOS_REJECT\t\t\t\t\t\t\t\t\t\t= 0X2d, /* QoS Rejected */\n\tHCI_STATUS_CHNL_CLASSIFICATION_NOT_SUPPORT\t\t\t\t= 0X2e, /* Channel Classification Not Supported */\n\tHCI_STATUS_INSUFFICIENT_SECURITY\t\t\t\t\t\t\t= 0X2f, /* Insufficient Security */\n\tHCI_STATUS_PARA_OUT_OF_RANGE\t\t\t\t\t\t\t= 0x30, /* Parameter Out Of Mandatory Range */\n\tHCI_STATUS_RESERVE_2\t\t\t\t\t\t\t\t\t\t= 0X31, /* Reserved */\n\tHCI_STATUS_ROLE_SWITCH_PENDING\t\t\t\t\t\t\t= 0X32, /* Role Switch Pending */\n\tHCI_STATUS_RESERVE_3\t\t\t\t\t\t\t\t\t\t= 0X33, /* Reserved */\n\tHCI_STATUS_RESERVE_SOLT_VIOLATION\t\t\t\t\t\t= 0X34, /* Reserved Slot Violation */\n\tHCI_STATUS_ROLE_SWITCH_FAIL\t\t\t\t\t\t\t\t= 0X35, /* Role Switch Failed */\n\tHCI_STATUS_EXTEND_INQUIRY_RSP_TOO_LARGE\t\t\t\t= 0X36, /* Extended Inquiry Response Too Large */\n\tHCI_STATUS_SEC_SIMPLE_PAIRING_NOT_SUPPORT\t\t\t\t= 0X37, /* Secure Simple Pairing Not Supported By Host. */\n\tHCI_STATUS_HOST_BUSY_PAIRING\t\t\t\t\t\t\t\t= 0X38, /* Host Busy - Pairing */\n\tHCI_STATUS_CONNECT_REJ_NOT_SUIT_CHNL_FOUND\t\t\t= 0X39, /* Connection Rejected due to No Suitable Channel Found */\n\tHCI_STATUS_CONTROLLER_BUSY\t\t\t\t\t\t\t\t= 0X3a /* CONTROLLER BUSY */\n} RTW_HCI_STATUS;\n\n#define HCI_EVENT_COMMAND_COMPLETE\t\t\t\t\t0x0e\n\n#define OGF_EXTENSION\t\t\t\t\t\t\t\t\t0X3f\ntypedef enum HCI_EXTENSION_COMMANDS {\n\tHCI_SET_ACL_LINK_DATA_FLOW_MODE\t\t\t\t= 0x0010,\n\tHCI_SET_ACL_LINK_STATUS\t\t\t\t\t\t\t= 0x0020,\n\tHCI_SET_SCO_LINK_STATUS\t\t\t\t\t\t\t= 0x0030,\n\tHCI_SET_RSSI_VALUE\t\t\t\t\t\t\t\t= 0x0040,\n\tHCI_SET_CURRENT_BLUETOOTH_STATUS\t\t\t\t= 0x0041,\n\n\t/* The following is for RTK8723 */\n\tHCI_EXTENSION_VERSION_NOTIFY\t\t\t\t\t= 0x0100,\n\tHCI_LINK_STATUS_NOTIFY\t\t\t\t\t\t\t= 0x0101,\n\tHCI_BT_OPERATION_NOTIFY\t\t\t\t\t\t\t= 0x0102,\n\tHCI_ENABLE_WIFI_SCAN_NOTIFY\t\t\t\t\t\t= 0x0103,\n\tHCI_QUERY_RF_STATUS\t\t\t\t\t\t\t\t= 0x0104,\n\tHCI_BT_ABNORMAL_NOTIFY\t\t\t\t\t\t\t= 0x0105,\n\tHCI_BT_INFO_NOTIFY\t\t\t\t\t\t\t\t= 0x0106,\n\tHCI_BT_COEX_NOTIFY\t\t\t\t\t\t\t\t= 0x0107,\n\tHCI_BT_PATCH_VERSION_NOTIFY\t\t\t\t\t\t= 0x0108,\n\tHCI_BT_AFH_MAP_NOTIFY\t\t\t\t\t\t\t= 0x0109,\n\tHCI_BT_REGISTER_VALUE_NOTIFY\t\t\t\t\t= 0x010a,\n\n\t/* The following is for IVT */\n\tHCI_WIFI_CURRENT_CHANNEL\t\t\t\t\t\t= 0x0300,\n\tHCI_WIFI_CURRENT_BANDWIDTH\t\t\t\t\t\t= 0x0301,\n\tHCI_WIFI_CONNECTION_STATUS\t\t\t\t\t\t= 0x0302\n} RTW_HCI_EXT_CMD;\n\n#define HCI_EVENT_EXTENSION_RTK\t\t\t\t\t\t0xfe\ntypedef enum HCI_EXTENSION_EVENT_RTK {\n\tHCI_EVENT_EXT_WIFI_SCAN_NOTIFY\t\t\t\t\t\t\t\t= 0x01,\n\tHCI_EVENT_EXT_WIFI_RF_STATUS_NOTIFY\t\t\t\t\t\t= 0x02,\n\tHCI_EVENT_EXT_BT_INFO_CONTROL\t\t\t\t\t\t\t\t= 0x03,\n\tHCI_EVENT_EXT_BT_COEX_CONTROL\t\t\t\t\t\t\t\t= 0x04\n} RTW_HCI_EXT_EVENT;\n\ntypedef enum _BT_TRAFFIC_MODE {\n\tBT_MOTOR_EXT_BE\t\t= 0x00, /* Best Effort. Default. for HCRP, PAN, SDP, RFCOMM-based profiles like FTP,OPP, SPP, DUN, etc. */\n\tBT_MOTOR_EXT_GUL\t\t= 0x01, /* Guaranteed Latency. This type of traffic is used e.g. for HID and AVRCP. */\n\tBT_MOTOR_EXT_GUB\t\t= 0X02, /* Guaranteed Bandwidth. */\n\tBT_MOTOR_EXT_GULB\t= 0X03  /* Guaranteed Latency and Bandwidth. for A2DP and VDP. */\n} BT_TRAFFIC_MODE;\n\ntypedef enum _BT_TRAFFIC_MODE_PROFILE {\n\tBT_PROFILE_NONE,\n\tBT_PROFILE_A2DP,\n\tBT_PROFILE_PAN\t,\n\tBT_PROFILE_HID,\n\tBT_PROFILE_SCO\n} BT_TRAFFIC_MODE_PROFILE;\n\ntypedef enum _HCI_EXT_BT_OPERATION {\n\tHCI_BT_OP_NONE\t\t\t\t= 0x0,\n\tHCI_BT_OP_INQUIRY_START\t\t= 0x1,\n\tHCI_BT_OP_INQUIRY_FINISH\t\t= 0x2,\n\tHCI_BT_OP_PAGING_START\t\t= 0x3,\n\tHCI_BT_OP_PAGING_SUCCESS\t\t= 0x4,\n\tHCI_BT_OP_PAGING_UNSUCCESS\t= 0x5,\n\tHCI_BT_OP_PAIRING_START\t\t= 0x6,\n\tHCI_BT_OP_PAIRING_FINISH\t\t= 0x7,\n\tHCI_BT_OP_BT_DEV_ENABLE\t\t= 0x8,\n\tHCI_BT_OP_BT_DEV_DISABLE\t\t= 0x9,\n\tHCI_BT_OP_MAX\n} HCI_EXT_BT_OPERATION, *PHCI_EXT_BT_OPERATION;\n\ntypedef struct _BT_MGNT {\n\tBOOLEAN\t\t\t\tbBTConnectInProgress;\n\tBOOLEAN\t\t\t\tbLogLinkInProgress;\n\tBOOLEAN\t\t\t\tbPhyLinkInProgress;\n\tBOOLEAN\t\t\t\tbPhyLinkInProgressStartLL;\n\tu8\t\t\t\tBtCurrentPhyLinkhandle;\n\tu16\t\t\t\tBtCurrentLogLinkhandle;\n\tu8\t\t\t\tCurrentConnectEntryNum;\n\tu8\t\t\t\tDisconnectEntryNum;\n\tu8\t\t\t\tCurrentBTConnectionCnt;\n\tBT_CONNECT_TYPE\t\tBTCurrentConnectType;\n\tBT_CONNECT_TYPE\t\tBTReceiveConnectPkt;\n\tu8\t\t\t\tBTAuthCount;\n\tu8\t\t\t\tBTAsocCount;\n\tBOOLEAN\t\t\t\tbStartSendSupervisionPkt;\n\tBOOLEAN\t\t\t\tBtOperationOn;\n\tBOOLEAN\t\t\t\tBTNeedAMPStatusChg;\n\tBOOLEAN\t\t\t\tJoinerNeedSendAuth;\n\tHCI_PHY_LINK_BSS_INFO\tbssDesc;\n\tHCI_EXT_CONFIG\t\tExtConfig;\n\tBOOLEAN\t\t\t\tbNeedNotifyAMPNoCap;\n\tBOOLEAN\t\t\t\tbCreateSpportQos;\n\tBOOLEAN\t\t\t\tbSupportProfile;\n\tu8\t\t\t\tBTChannel;\n\tBOOLEAN\t\t\t\tCheckChnlIsSuit;\n\tBOOLEAN\t\t\t\tbBtScan;\n\tBOOLEAN\t\t\t\tbtLogoTest;\n\tBOOLEAN\t\t\t\tbRfStatusNotified;\n\tBOOLEAN\t\t\t\tbBtRsvedPageDownload;\n} BT_MGNT, *PBT_MGNT;\n\nstruct bt_coex_info {\n\t/* For Kernel Socket */\n\tstruct socket *udpsock;\n\tstruct sockaddr_in wifi_sockaddr; /*wifi socket*/\n\tstruct sockaddr_in bt_sockaddr;/* BT socket */\n\tstruct sock *sk_store;/*back up socket for UDP RX int*/\n\n\t/* store which socket is OK */\n\tu8 sock_open;\n\n\tu8 BT_attend;\n\tu8 is_exist; /* socket exist */\n\tBT_MGNT BtMgnt;\n\tstruct workqueue_struct *btcoex_wq;\n\tstruct delayed_work recvmsg_work;\n};\n#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */\n\n#define\tPACKET_NORMAL\t\t\t0\n#define\tPACKET_DHCP\t\t\t\t1\n#define\tPACKET_ARP\t\t\t\t2\n#define\tPACKET_EAPOL\t\t\t3\n\nvoid rtw_btcoex_Initialize(PADAPTER);\nvoid rtw_btcoex_PowerOnSetting(PADAPTER padapter);\nvoid rtw_btcoex_AntInfoSetting(PADAPTER padapter);\nvoid rtw_btcoex_PowerOffSetting(PADAPTER padapter);\nvoid rtw_btcoex_PreLoadFirmware(PADAPTER padapter);\nvoid rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly);\nvoid rtw_btcoex_IpsNotify(PADAPTER, u8 type);\nvoid rtw_btcoex_LpsNotify(PADAPTER, u8 type);\nvoid rtw_btcoex_ScanNotify(PADAPTER, u8 type);\nvoid rtw_btcoex_ConnectNotify(PADAPTER, u8 action);\nvoid rtw_btcoex_MediaStatusNotify(PADAPTER, u8 mediaStatus);\nvoid rtw_btcoex_SpecialPacketNotify(PADAPTER, u8 pktType);\nvoid rtw_btcoex_IQKNotify(PADAPTER padapter, u8 state);\nvoid rtw_btcoex_BtInfoNotify(PADAPTER, u8 length, u8 *tmpBuf);\nvoid rtw_btcoex_BtMpRptNotify(PADAPTER, u8 length, u8 *tmpBuf);\nvoid rtw_btcoex_SuspendNotify(PADAPTER, u8 state);\nvoid rtw_btcoex_HaltNotify(PADAPTER);\nvoid rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type);\nvoid rtw_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length);\nvoid rtw_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id);\nvoid rtw_btcoex_SwitchBtTRxMask(PADAPTER);\nvoid rtw_btcoex_Switch(PADAPTER, u8 enable);\nu8 rtw_btcoex_IsBtDisabled(PADAPTER);\nvoid rtw_btcoex_Handler(PADAPTER);\ns32 rtw_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter);\ns32 rtw_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER);\nu32 rtw_btcoex_GetAMPDUSize(PADAPTER);\nvoid rtw_btcoex_SetManualControl(PADAPTER, u8 bmanual);\nu8 rtw_btcoex_1Ant(PADAPTER);\nu8 rtw_btcoex_IsBtControlLps(PADAPTER);\nu8 rtw_btcoex_IsLpsOn(PADAPTER);\nu8 rtw_btcoex_RpwmVal(PADAPTER);\nu8 rtw_btcoex_LpsVal(PADAPTER);\nu32 rtw_btcoex_GetRaMask(PADAPTER);\nu8 rtw_btcoex_query_reduced_wl_pwr_lvl(PADAPTER padapter);\nvoid rtw_btcoex_set_reduced_wl_pwr_lvl(PADAPTER padapter, u8 val);\nvoid rtw_btcoex_do_reduce_wl_pwr_lvl(PADAPTER padapter);\nvoid rtw_btcoex_RecordPwrMode(PADAPTER, u8 *pCmdBuf, u8 cmdLen);\nvoid rtw_btcoex_DisplayBtCoexInfo(PADAPTER, u8 *pbuf, u32 bufsize);\nvoid rtw_btcoex_SetDBG(PADAPTER, u32 *pDbgModule);\nu32 rtw_btcoex_GetDBG(PADAPTER, u8 *pStrBuf, u32 bufSize);\nu8 rtw_btcoex_IncreaseScanDeviceNum(PADAPTER);\nu8 rtw_btcoex_IsBtLinkExist(PADAPTER);\nvoid rtw_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON);\n\n#ifdef CONFIG_RF4CE_COEXIST\nvoid rtw_btcoex_SetRf4ceLinkState(PADAPTER padapter, u8 state);\nu8 rtw_btcoex_GetRf4ceLinkState(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\nvoid rtw_btcoex_SetBtPatchVersion(PADAPTER padapter, u16 btHciVer, u16 btPatchVer);\nvoid rtw_btcoex_SetHciVersion(PADAPTER  padapter, u16 hciVersion);\nvoid rtw_btcoex_StackUpdateProfileInfo(void);\nvoid rtw_btcoex_init_socket(_adapter *padapter);\nvoid rtw_btcoex_close_socket(_adapter *padapter);\nvoid rtw_btcoex_dump_tx_msg(u8 *tx_msg, u8 len, u8 *msg_name);\nu8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool force);\nu8 rtw_btcoex_create_kernel_socket(_adapter *padapter);\nvoid rtw_btcoex_close_kernel_socket(_adapter *padapter);\nvoid rtw_btcoex_recvmsgbysocket(void *data);\nu16 rtw_btcoex_parse_recv_data(u8 *msg, u8 msg_size);\nu8 rtw_btcoex_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length);\nvoid rtw_btcoex_parse_hci_cmd(_adapter *padapter, u8 *cmd, u16 len);\nvoid rtw_btcoex_SendEventExtBtCoexControl(PADAPTER Adapter, u8 bNeedDbgRsp, u8 dataLen, void *pData);\nvoid rtw_btcoex_SendEventExtBtInfoControl(PADAPTER Adapter, u8 dataLen, void *pData);\nvoid rtw_btcoex_SendScanNotify(PADAPTER padapter, u8 scanType);\n#define BT_SendEventExtBtCoexControl(Adapter, bNeedDbgRsp, dataLen, pData) rtw_btcoex_SendEventExtBtCoexControl(Adapter, bNeedDbgRsp, dataLen, pData)\n#define BT_SendEventExtBtInfoControl(Adapter, dataLen, pData) rtw_btcoex_SendEventExtBtInfoControl(Adapter, dataLen, pData)\n#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */\nu16 rtw_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data);\nu16 rtw_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val);\nu8 rtw_btcoex_get_reduce_wl_txpwr(PADAPTER padapter);\nu8 rtw_btcoex_get_bt_coexist(PADAPTER padapter);\nu8 rtw_btcoex_get_chip_type(PADAPTER padapter);\nu8 rtw_btcoex_get_pg_ant_num(PADAPTER padapter);\nu8 rtw_btcoex_get_pg_single_ant_path(PADAPTER padapter);\nu8 rtw_btcoex_get_pg_rfe_type(PADAPTER padapter);\nu8 rtw_btcoex_is_tfbga_package_type(PADAPTER padapter);\nu8 rtw_btcoex_get_ant_div_cfg(PADAPTER padapter);\nu16 rtw_btcoex_btset_testmode(PADAPTER padapter, u8 type);\n\n/* ==================================================\n * Below Functions are called by BT-Coex\n * ================================================== */\nvoid rtw_btcoex_rx_ampdu_apply(PADAPTER padapter);\nvoid rtw_btcoex_LPS_Enter(PADAPTER padapter);\nu8 rtw_btcoex_LPS_Leave(PADAPTER padapter);\n\n#endif /* __RTW_BTCOEX_H__ */\n#endif /* CONFIG_BT_COEXIST */\n\nvoid rtw_btcoex_set_ant_info(PADAPTER padapter);\n\n"
  },
  {
    "path": "include/rtw_btcoex_wifionly.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_BTCOEX_WIFIONLY_H__\n#define __RTW_BTCOEX_WIFIONLY_H__\n\nvoid rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter);\nvoid rtw_btcoex_wifionly_scan_notify(PADAPTER padapter);\nvoid rtw_btcoex_wifionly_connect_notify(PADAPTER padapter);\nvoid rtw_btcoex_wifionly_hw_config(PADAPTER padapter);\nvoid rtw_btcoex_wifionly_initialize(PADAPTER padapter);\nvoid rtw_btcoex_wifionly_AntInfoSetting(PADAPTER padapter);\n#endif\n"
  },
  {
    "path": "include/rtw_byteorder.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTL871X_BYTEORDER_H_\n#define _RTL871X_BYTEORDER_H_\n\n\n#if defined(CONFIG_LITTLE_ENDIAN) && defined (CONFIG_BIG_ENDIAN)\n\t#error \"Shall be CONFIG_LITTLE_ENDIAN or CONFIG_BIG_ENDIAN, but not both!\\n\"\n#endif\n\n#if defined(CONFIG_LITTLE_ENDIAN)\n\t#ifndef CONFIG_PLATFORM_MSTAR389\n\t\t#include <byteorder/little_endian.h>\n\t#endif\n#elif defined (CONFIG_BIG_ENDIAN)\n\t#include <byteorder/big_endian.h>\n#else\n\t#  error \"Must be LITTLE/BIG Endian Host\"\n#endif\n\n#endif /* _RTL871X_BYTEORDER_H_ */\n"
  },
  {
    "path": "include/rtw_cmd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_CMD_H_\n#define __RTW_CMD_H_\n\n\n#define C2H_MEM_SZ (16*1024)\n\n#define FREE_CMDOBJ_SZ\t128\n\n#define MAX_CMDSZ\t1024\n#define MAX_RSPSZ\t512\n#define MAX_EVTSZ\t1024\n\n#define CMDBUFF_ALIGN_SZ 512\n\nstruct cmd_obj {\n\t_adapter *padapter;\n\tu16\tcmdcode;\n\tu8\tres;\n\tu8\t*parmbuf;\n\tu32\tcmdsz;\n\tu8\t*rsp;\n\tu32\trspsz;\n\tstruct submit_ctx *sctx;\n\tu8 no_io;\n\t/* _sema \tcmd_sem; */\n\t_list\tlist;\n};\n\n/* cmd flags */\nenum {\n\tRTW_CMDF_DIRECTLY = BIT0,\n\tRTW_CMDF_WAIT_ACK = BIT1,\n};\n\nstruct cmd_priv {\n\t_sema\tcmd_queue_sema;\n\t/* _sema\tcmd_done_sema; */\n\t_sema\tstart_cmdthread_sema;\n\n\t_queue\tcmd_queue;\n\tu8\tcmd_seq;\n\tu8\t*cmd_buf;\t/* shall be non-paged, and 4 bytes aligned */\n\tu8\t*cmd_allocated_buf;\n\tu8\t*rsp_buf;\t/* shall be non-paged, and 4 bytes aligned\t\t */\n\tu8\t*rsp_allocated_buf;\n\tu32\tcmd_issued_cnt;\n\tu32\tcmd_done_cnt;\n\tu32\trsp_cnt;\n\tATOMIC_T cmdthd_running;\n\t/* u8 cmdthd_running; */\n\n\t_adapter *padapter;\n\t_mutex sctx_mutex;\n};\n\n#ifdef CONFIG_EVENT_THREAD_MODE\nstruct evt_obj {\n\tu16\tevtcode;\n\tu8\tres;\n\tu8\t*parmbuf;\n\tu32\tevtsz;\n\t_list\tlist;\n};\n#endif\n\nstruct\tevt_priv {\n#ifdef CONFIG_EVENT_THREAD_MODE\n\t_sema\tevt_notify;\n\n\t_queue\tevt_queue;\n#endif\n\n#ifdef CONFIG_FW_C2H_REG\n\t#define CONFIG_C2H_WK\n#endif\n\n#ifdef CONFIG_C2H_WK\n\t_workitem c2h_wk;\n\tbool c2h_wk_alive;\n\tstruct rtw_cbuf *c2h_queue;\n\t#define C2H_QUEUE_MAX_LEN 10\n#endif\n\n#ifdef CONFIG_H2CLBK\n\t_sema\tlbkevt_done;\n\tu8\tlbkevt_limit;\n\tu8\tlbkevt_num;\n\tu8\t*cmdevt_parm;\n#endif\n\tATOMIC_T event_seq;\n\tu8\t*evt_buf;\t/* shall be non-paged, and 4 bytes aligned\t\t */\n\tu8\t*evt_allocated_buf;\n\tu32\tevt_done_cnt;\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\tu8\t*c2h_mem;\n\tu8\t*allocated_c2h_mem;\n#endif\n\n};\n\n#define init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code) \\\n\tdo {\\\n\t\t_rtw_init_listhead(&pcmd->list);\\\n\t\tpcmd->cmdcode = code;\\\n\t\tpcmd->parmbuf = (u8 *)(pparm);\\\n\t\tpcmd->cmdsz = sizeof (*pparm);\\\n\t\tpcmd->rsp = NULL;\\\n\t\tpcmd->rspsz = 0;\\\n\t} while (0)\n\n#define init_h2fwcmd_w_parm_no_parm_rsp(pcmd, code) \\\n\tdo {\\\n\t\t_rtw_init_listhead(&pcmd->list);\\\n\t\tpcmd->cmdcode = code;\\\n\t\tpcmd->parmbuf = NULL;\\\n\t\tpcmd->cmdsz = 0;\\\n\t\tpcmd->rsp = NULL;\\\n\t\tpcmd->rspsz = 0;\\\n\t} while (0)\n\nstruct P2P_PS_Offload_t {\n\tu8 Offload_En:1;\n\tu8 role:1; /* 1: Owner, 0: Client */\n\tu8 CTWindow_En:1;\n\tu8 NoA0_En:1;\n\tu8 NoA1_En:1;\n\tu8 AllStaSleep:1; /* Only valid in Owner */\n\tu8 discovery:1;\n\tu8 rsvd:1;\n#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP\n\tu8 p2p_macid:7;\n\tu8 disable_close_rf:1; /*1: not close RF but just pause p2p_macid when NoA duration*/\n#endif /* CONFIG_P2P_PS_NOA_USE_MACID_SLEEP */\n};\n\nstruct P2P_PS_CTWPeriod_t {\n\tu8 CTWPeriod;\t/* TU */\n};\n\n#ifdef CONFIG_P2P_WOWLAN\n\nstruct P2P_WoWlan_Offload_t {\n\tu8 Disconnect_Wkup_Drv:1;\n\tu8 role:2;\n\tu8 Wps_Config[2];\n};\n\n#endif /* CONFIG_P2P_WOWLAN */\n\nextern u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *obj);\nextern struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv);\nextern void rtw_free_cmd_obj(struct cmd_obj *pcmd);\n\n#ifdef CONFIG_EVENT_THREAD_MODE\nextern u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj);\nextern struct evt_obj *rtw_dequeue_evt(_queue *queue);\nextern void rtw_free_evt_obj(struct evt_obj *pcmd);\n#endif\n\nvoid rtw_stop_cmd_thread(_adapter *adapter);\nthread_return rtw_cmd_thread(thread_context context);\n\nextern u32 rtw_init_cmd_priv(struct cmd_priv *pcmdpriv);\nextern void rtw_free_cmd_priv(struct cmd_priv *pcmdpriv);\n\nextern u32 rtw_init_evt_priv(struct evt_priv *pevtpriv);\nextern void rtw_free_evt_priv(struct evt_priv *pevtpriv);\nextern void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv);\nextern void rtw_evt_notify_isr(struct evt_priv *pevtpriv);\n#ifdef CONFIG_P2P\nu8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType);\n\n#ifdef CONFIG_IOCTL_CFG80211\nstruct p2p_roch_parm {\n\tu64 cookie;\n\tstruct wireless_dev *wdev;\n\tstruct ieee80211_channel ch;\n\tenum nl80211_channel_type ch_type;\n\tunsigned int duration;\n};\n\nu8 p2p_roch_cmd(_adapter *adapter\n\t, u64 cookie, struct wireless_dev *wdev\n\t, struct ieee80211_channel *ch, enum nl80211_channel_type ch_type\n\t, unsigned int duration\n\t, u8 flags\n);\nu8 p2p_cancel_roch_cmd(_adapter *adapter, u64 cookie, struct wireless_dev *wdev, u8 flags);\n\n#endif /* CONFIG_IOCTL_CFG80211 */\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_IOCTL_CFG80211 \nu8 rtw_mgnt_tx_cmd(_adapter *adapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack, u8 flags);\nstruct mgnt_tx_parm {\n\tu8 tx_ch;\n\tu8 no_cck;\n\tconst u8 *buf;\n\tsize_t len;\n\tint wait_ack;\n};\n#endif\n\nenum rtw_drvextra_cmd_id {\n\tNONE_WK_CID,\n\tSTA_MSTATUS_RPT_WK_CID,\n\tDYNAMIC_CHK_WK_CID,\n\tDM_CTRL_WK_CID,\n\tPBC_POLLING_WK_CID,\n\tPOWER_SAVING_CTRL_WK_CID,/* IPS,AUTOSuspend */\n\tLPS_CTRL_WK_CID,\n\tANT_SELECT_WK_CID,\n\tP2P_PS_WK_CID,\n\tP2P_PROTO_WK_CID,\n\tCHECK_HIQ_WK_CID,/* for softap mode, check hi queue if empty */\n\tC2H_WK_CID,\n\tRTP_TIMER_CFG_WK_CID,\n\tRESET_SECURITYPRIV, /* add for CONFIG_IEEE80211W, none 11w also can use */\n\tFREE_ASSOC_RESOURCES, /* add for CONFIG_IEEE80211W, none 11w also can use */\n\tDM_IN_LPS_WK_CID,\n\tDM_RA_MSK_WK_CID, /* add for STA update RAMask when bandwith change. */\n\tBEAMFORMING_WK_CID,\n\tLPS_CHANGE_DTIM_CID,\n\tBTINFO_WK_CID,\n\tBTC_REDUCE_WL_TXPWR_CID,\n\tDFS_RADAR_DETECT_WK_CID,\n\tDFS_RADAR_DETECT_EN_DEC_WK_CID,\n\tSESSION_TRACKER_WK_CID,\n\tEN_HW_UPDATE_TSF_WK_CID,\n\tPERIOD_TSF_UPDATE_END_WK_CID,\n\tTEST_H2C_CID,\n\tMP_CMD_WK_CID,\n\tCUSTOMER_STR_WK_CID,\n#ifdef CONFIG_RTW_REPEATER_SON\n\tRSON_SCAN_WK_CID,\n#endif\n\tMGNT_TX_WK_CID,\n\tREQ_PER_CMD_WK_CID,\n\tSSMPS_WK_CID,\n#ifdef CONFIG_CTRL_TXSS_BY_TP\n\tTXSS_WK_CID,\n#endif\n\tMAX_WK_CID\n};\n\nenum LPS_CTRL_TYPE {\n\tLPS_CTRL_SCAN = 0,\n\tLPS_CTRL_JOINBSS = 1,\n\tLPS_CTRL_CONNECT = 2,\n\tLPS_CTRL_DISCONNECT = 3,\n\tLPS_CTRL_SPECIAL_PACKET = 4,\n\tLPS_CTRL_LEAVE = 5,\n\tLPS_CTRL_TRAFFIC_BUSY = 6,\n\tLPS_CTRL_TX_TRAFFIC_LEAVE = 7,\n\tLPS_CTRL_RX_TRAFFIC_LEAVE = 8,\n\tLPS_CTRL_ENTER = 9,\n\tLPS_CTRL_LEAVE_CFG80211_PWRMGMT = 10,\n\tLPS_CTRL_LEAVE_SET_OPTION = 11,\n};\n\nenum STAKEY_TYPE {\n\tGROUP_KEY\t\t= 0,\n\tUNICAST_KEY\t\t= 1,\n\tTDLS_KEY\t\t= 2,\n};\n\nenum RFINTFS {\n\tSWSI,\n\tHWSI,\n\tHWPI,\n};\n\n/*\nCaller Mode: Infra, Ad-HoC(C)\n\nNotes: To enter USB suspend mode\n\nCommand Mode\n\n*/\nstruct usb_suspend_parm {\n\tu32 action;/* 1: sleep, 0:resume */\n};\n\n/*\nCaller Mode: Infra, Ad-HoC\n\nNotes: To join a known BSS.\n\nCommand-Event Mode\n\n*/\n\n/*\nCaller Mode: Infra, Ad-Hoc\n\nNotes: To join the specified bss\n\nCommand Event Mode\n\n*/\nstruct joinbss_parm {\n\tWLAN_BSSID_EX network;\n};\n\n/*\nCaller Mode: Infra, Ad-HoC(C)\n\nNotes: To disconnect the current associated BSS\n\nCommand Mode\n\n*/\nstruct disconnect_parm {\n\tu32 deauth_timeout_ms;\n};\n\n/*\nCaller Mode: AP, Ad-HoC(M)\n\nNotes: To create a BSS\n\nCommand Mode\n*/\nstruct createbss_parm {\n\tbool adhoc;\n\n\t/* used by AP/Mesh mode now */\n\tu8 ifbmp;\n\tu8 excl_ifbmp;\n\ts16 req_ch;\n\ts8 req_bw;\n\ts8 req_offset;\n};\n\n#if 0\n/* Caller Mode: AP, Ad-HoC, Infra */\n/* Notes: To set the NIC mode of RTL8711 */\n/* Command Mode */\n/* The definition of mode: */\n\n#define IW_MODE_AUTO\t0\t/*  Let the driver decides which AP to join */\n#define IW_MODE_ADHOC\t1\t/*  Single cell network (Ad-Hoc Clients) */\n#define IW_MODE_INFRA\t2\t/*  Multi cell network, roaming, .. */\n#define IW_MODE_MASTER\t3\t/*  Synchronisation master or Access Point */\n#define IW_MODE_REPEAT\t4\t/*  Wireless Repeater (forwarder) */\n#define IW_MODE_SECOND\t5\t/*  Secondary master/repeater (backup) */\n#define IW_MODE_MONITOR\t6\t/*  Passive monitor (listen only) */\n#endif\n\nstruct\tsetopmode_parm {\n\tu8\tmode;\n\tu8\trsvd[3];\n};\n\n/*\nCaller Mode: AP, Ad-HoC, Infra\n\nNotes: To ask RTL8711 performing site-survey\n\nCommand-Event Mode\n\n*/\n\n#define RTW_SSID_SCAN_AMOUNT 9 /* for WEXT_CSCAN_AMOUNT 9 */\n#define RTW_CHANNEL_SCAN_AMOUNT (14+37)\nstruct sitesurvey_parm {\n\tsint scan_mode;\t/* active: 1, passive: 0 */\n\t/* sint bsslimit;\t// 1 ~ 48 */\n\tu8 ssid_num;\n\tu8 ch_num;\n\tNDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT];\n\tstruct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT];\n\n\tu32 token; \t/* 80211k use it to identify caller */\n\tu16 duration;\t/* 0: use default, otherwise: channel scan time */\n\tu8 igi;\t\t/* 0: use defalut */\n\tu8 bw;\t\t/* 0: use default */\n};\n\n/*\nCaller Mode: Any\n\nNotes: To set the auth type of RTL8711. open/shared/802.1x\n\nCommand Mode\n\n*/\nstruct setauth_parm {\n\tu8 mode;  /* 0: legacy open, 1: legacy shared 2: 802.1x */\n\tu8 _1x;   /* 0: PSK, 1: TLS */\n\tu8 rsvd[2];\n};\n\n/*\nCaller Mode: Infra\n\na. algorithm: wep40, wep104, tkip & aes\nb. keytype: grp key/unicast key\nc. key contents\n\nwhen shared key ==> keyid is the camid\nwhen 802.1x ==> keyid [0:1] ==> grp key\nwhen 802.1x ==> keyid > 2 ==> unicast key\n\n*/\nstruct setkey_parm {\n\tu8\talgorithm;\t/* encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 */\n\tu8\tkeyid;\n\tu8\tset_tx;\t\t/* 1: main tx key for wep. 0: other key. */\n\tu8\tkey[16];\t/* this could be 40 or 104 */\n};\n\n/*\nWhen in AP or Ad-Hoc mode, this is used to\nallocate an sw/hw entry for a newly associated sta.\n\nCommand\n\nwhen shared key ==> algorithm/keyid\n\n*/\nstruct set_stakey_parm {\n\tu8 addr[ETH_ALEN];\n\tu8 algorithm;\n\tu8 keyid;\n\tu8 key[16];\n\tu8 gk;\n};\n\nstruct set_stakey_rsp {\n\tu8\taddr[ETH_ALEN];\n\tu8\tkeyid;\n\tu8\trsvd;\n};\n\n/*\nCaller Ad-Hoc/AP\n\nCommand -Rsp(AID == CAMID) mode\n\nThis is to force fw to add an sta_data entry per driver's request.\n\nFW will write an cam entry associated with it.\n\n*/\nstruct set_assocsta_parm {\n\tu8\taddr[ETH_ALEN];\n};\n\nstruct set_assocsta_rsp {\n\tu8\tcam_id;\n\tu8\trsvd[3];\n};\n\n/*\n\tCaller Ad-Hoc/AP\n\tCommand mode\n\tThis is to force fw to del an sta_data entry per driver's request\n\tFW will invalidate the cam entry associated with it.\n*/\nstruct del_assocsta_parm {\n\tu8\taddr[ETH_ALEN];\n};\n\n/*\nCaller Mode: AP/Ad-HoC(M)\n\nNotes: To notify fw that given staid has changed its power state\n\nCommand Mode\n\n*/\nstruct setstapwrstate_parm {\n\tu8\tstaid;\n\tu8\tstatus;\n\tu8\thwaddr[6];\n};\n\n/*\nCaller Mode: Any\n\nNotes: To setup the basic rate of RTL8711\n\nCommand Mode\n\n*/\nstruct\tsetbasicrate_parm {\n\tu8\tbasicrates[NumRates];\n};\n\n/*\nCaller Mode: Any\n\nNotes: To read the current basic rate\n\nCommand-Rsp Mode\n\n*/\nstruct getbasicrate_parm {\n\tu32 rsvd;\n};\n\nstruct getbasicrate_rsp {\n\tu8 basicrates[NumRates];\n};\n\n/*\nCaller Mode: Any\n\nNotes: To setup the data rate of RTL8711\n\nCommand Mode\n\n*/\nstruct setdatarate_parm {\n#ifdef MP_FIRMWARE_OFFLOAD\n\tu32\tcurr_rateidx;\n#else\n\tu8\tmac_id;\n\tu8\tdatarates[NumRates];\n#endif\n};\n\n/*\nCaller Mode: Any\n\nNotes: To read the current data rate\n\nCommand-Rsp Mode\n\n*/\nstruct getdatarate_parm {\n\tu32 rsvd;\n\n};\nstruct getdatarate_rsp {\n\tu8 datarates[NumRates];\n};\n\n/*\nCaller Mode: Any\n\nNotes: To set the channel/modem/band\nThis command will be used when channel/modem/band is changed.\n\nCommand Mode\n\n*/\nstruct\tsetphy_parm {\n\tu8\trfchannel;\n\tu8\tmodem;\n};\n\n/*\nCaller Mode: Any\n\nNotes: To get the current setting of channel/modem/band\n\nCommand-Rsp Mode\n\n*/\nstruct\tgetphy_parm {\n\tu32 rsvd;\n\n};\nstruct\tgetphy_rsp {\n\tu8\trfchannel;\n\tu8\tmodem;\n};\n\nstruct readBB_parm {\n\tu8\toffset;\n};\nstruct readBB_rsp {\n\tu8\tvalue;\n};\n\nstruct readTSSI_parm {\n\tu8\toffset;\n};\nstruct readTSSI_rsp {\n\tu8\tvalue;\n};\n\nstruct readMAC_parm {\n\tu8 len;\n\tu32\taddr;\n};\n\nstruct writeBB_parm {\n\tu8\toffset;\n\tu8\tvalue;\n};\n\nstruct readRF_parm {\n\tu8\toffset;\n};\nstruct readRF_rsp {\n\tu32\tvalue;\n};\n\nstruct writeRF_parm {\n\tu32\toffset;\n\tu32\tvalue;\n};\n\nstruct getrfintfs_parm {\n\tu8\trfintfs;\n};\n\n\nstruct Tx_Beacon_param {\n\tWLAN_BSSID_EX network;\n};\n\n/*\n\tNotes: This command is used for H2C/C2H loopback testing\n\n\tmac[0] == 0\n\t==> CMD mode, return H2C_SUCCESS.\n\tThe following condition must be ture under CMD mode\n\t\tmac[1] == mac[4], mac[2] == mac[3], mac[0]=mac[5]= 0;\n\t\ts0 == 0x1234, s1 == 0xabcd, w0 == 0x78563412, w1 == 0x5aa5def7;\n\t\ts2 == (b1 << 8 | b0);\n\n\tmac[0] == 1\n\t==> CMD_RSP mode, return H2C_SUCCESS_RSP\n\n\tThe rsp layout shall be:\n\trsp:\t\t\tparm:\n\t\tmac[0]  =   mac[5];\n\t\tmac[1]  =   mac[4];\n\t\tmac[2]  =   mac[3];\n\t\tmac[3]  =   mac[2];\n\t\tmac[4]  =   mac[1];\n\t\tmac[5]  =   mac[0];\n\t\ts0\t\t=   s1;\n\t\ts1\t\t=   swap16(s0);\n\t\tw0\t\t=\tswap32(w1);\n\t\tb0\t\t=\tb1\n\t\ts2\t\t=\ts0 + s1\n\t\tb1\t\t=\tb0\n\t\tw1\t\t=\tw0\n\n\tmac[0] ==\t2\n\t==> CMD_EVENT mode, return\tH2C_SUCCESS\n\tThe event layout shall be:\n\tevent:\t\t\tparm:\n\t\tmac[0]  =   mac[5];\n\t\tmac[1]  =   mac[4];\n\t\tmac[2]  =   event's sequence number, starting from 1 to parm's marc[3]\n\t\tmac[3]  =   mac[2];\n\t\tmac[4]  =   mac[1];\n\t\tmac[5]  =   mac[0];\n\t\ts0\t\t=   swap16(s0) - event.mac[2];\n\t\ts1\t\t=   s1 + event.mac[2];\n\t\tw0\t\t=\tswap32(w0);\n\t\tb0\t\t=\tb1\n\t\ts2\t\t=\ts0 + event.mac[2]\n\t\tb1\t\t=\tb0\n\t\tw1\t\t=\tswap32(w1) - event.mac[2];\n\n\t\tparm->mac[3] is the total event counts that host requested.\n\n\n\tevent will be the same with the cmd's param.\n\n*/\n\n#ifdef CONFIG_H2CLBK\n\nstruct seth2clbk_parm {\n\tu8 mac[6];\n\tu16\ts0;\n\tu16\ts1;\n\tu32\tw0;\n\tu8\tb0;\n\tu16  s2;\n\tu8\tb1;\n\tu32\tw1;\n};\n\nstruct geth2clbk_parm {\n\tu32 rsv;\n};\n\nstruct geth2clbk_rsp {\n\tu8\tmac[6];\n\tu16\ts0;\n\tu16\ts1;\n\tu32\tw0;\n\tu8\tb0;\n\tu16\ts2;\n\tu8\tb1;\n\tu32\tw1;\n};\n\n#endif\t/* CONFIG_H2CLBK */\n\n/* CMD param Formart for driver extra cmd handler */\nstruct drvextra_cmd_parm {\n\tint ec_id; /* extra cmd id */\n\tint type; /* Can use this field as the type id or command size */\n\tint size; /* buffer size */\n\tunsigned char *pbuf;\n};\n\n/*------------------- Below are used for RF/BB tunning ---------------------*/\n\nstruct\tsetantenna_parm {\n\tu8\ttx_antset;\n\tu8\trx_antset;\n\tu8\ttx_antenna;\n\tu8\trx_antenna;\n};\n\nstruct\tenrateadaptive_parm {\n\tu32\ten;\n};\n\nstruct settxagctbl_parm {\n\tu32\ttxagc[MAX_RATES_LENGTH];\n};\n\nstruct gettxagctbl_parm {\n\tu32 rsvd;\n};\nstruct gettxagctbl_rsp {\n\tu32\ttxagc[MAX_RATES_LENGTH];\n};\n\nstruct setagcctrl_parm {\n\tu32\tagcctrl;\t\t/* 0: pure hw, 1: fw */\n};\n\n\nstruct setssup_parm\t{\n\tu32\tss_ForceUp[MAX_RATES_LENGTH];\n};\n\nstruct getssup_parm\t{\n\tu32 rsvd;\n};\nstruct getssup_rsp\t{\n\tu8\tss_ForceUp[MAX_RATES_LENGTH];\n};\n\n\nstruct setssdlevel_parm\t{\n\tu8\tss_DLevel[MAX_RATES_LENGTH];\n};\n\nstruct getssdlevel_parm\t{\n\tu32 rsvd;\n};\nstruct getssdlevel_rsp\t{\n\tu8\tss_DLevel[MAX_RATES_LENGTH];\n};\n\nstruct setssulevel_parm\t{\n\tu8\tss_ULevel[MAX_RATES_LENGTH];\n};\n\nstruct getssulevel_parm\t{\n\tu32 rsvd;\n};\nstruct getssulevel_rsp\t{\n\tu8\tss_ULevel[MAX_RATES_LENGTH];\n};\n\n\nstruct\tsetcountjudge_parm {\n\tu8\tcount_judge[MAX_RATES_LENGTH];\n};\n\nstruct\tgetcountjudge_parm {\n\tu32 rsvd;\n};\nstruct\tgetcountjudge_rsp {\n\tu8\tcount_judge[MAX_RATES_LENGTH];\n};\n\n\nstruct setratable_parm {\n\tu8 ss_ForceUp[NumRates];\n\tu8 ss_ULevel[NumRates];\n\tu8 ss_DLevel[NumRates];\n\tu8 count_judge[NumRates];\n};\n\nstruct getratable_parm {\n\tuint rsvd;\n};\nstruct getratable_rsp {\n\tu8 ss_ForceUp[NumRates];\n\tu8 ss_ULevel[NumRates];\n\tu8 ss_DLevel[NumRates];\n\tu8 count_judge[NumRates];\n};\n\n\n/* to get TX,RX retry count */\nstruct gettxretrycnt_parm {\n\tunsigned int rsvd;\n};\nstruct gettxretrycnt_rsp {\n\tunsigned long tx_retrycnt;\n};\n\nstruct getrxretrycnt_parm {\n\tunsigned int rsvd;\n};\nstruct getrxretrycnt_rsp {\n\tunsigned long rx_retrycnt;\n};\n\n/* to get BCNOK,BCNERR count */\nstruct getbcnokcnt_parm {\n\tunsigned int rsvd;\n};\nstruct getbcnokcnt_rsp {\n\tunsigned long  bcnokcnt;\n};\n\nstruct getbcnerrcnt_parm {\n\tunsigned int rsvd;\n};\nstruct getbcnerrcnt_rsp {\n\tunsigned long bcnerrcnt;\n};\n\n/* to get current TX power level */\nstruct getcurtxpwrlevel_parm {\n\tunsigned int rsvd;\n};\nstruct getcurtxpwrlevel_rsp {\n\tunsigned short tx_power;\n};\n\nstruct setprobereqextraie_parm {\n\tunsigned char e_id;\n\tunsigned char ie_len;\n\tunsigned char ie[0];\n};\n\nstruct setassocreqextraie_parm {\n\tunsigned char e_id;\n\tunsigned char ie_len;\n\tunsigned char ie[0];\n};\n\nstruct setproberspextraie_parm {\n\tunsigned char e_id;\n\tunsigned char ie_len;\n\tunsigned char ie[0];\n};\n\nstruct setassocrspextraie_parm {\n\tunsigned char e_id;\n\tunsigned char ie_len;\n\tunsigned char ie[0];\n};\n\n\nstruct addBaReq_parm {\n\tunsigned int tid;\n\tu8\taddr[ETH_ALEN];\n};\n\nstruct addBaRsp_parm {\n\tunsigned int tid;\n\tunsigned int start_seq;\n\tu8 addr[ETH_ALEN];\n\tu8 status;\n\tu8 size;\n};\n\n/*H2C Handler index: 46 */\nstruct set_ch_parm {\n\tu8 ch;\n\tu8 bw;\n\tu8 ch_offset;\n};\n\n#ifdef MP_FIRMWARE_OFFLOAD\n/*H2C Handler index: 47 */\nstruct SetTxPower_parm {\n\tu8 TxPower;\n};\n\n/*H2C Handler index: 48 */\nstruct SwitchAntenna_parm {\n\tu16 antenna_tx;\n\tu16 antenna_rx;\n\t/*\tR_ANTENNA_SELECT_CCK cck_txrx; */\n\tu8 cck_txrx;\n};\n\n/*H2C Handler index: 49 */\nstruct SetCrystalCap_parm {\n\tu32 curr_crystalcap;\n};\n\n/*H2C Handler index: 50 */\nstruct SetSingleCarrierTx_parm {\n\tu8 bStart;\n};\n\n/*H2C Handler index: 51 */\nstruct SetSingleToneTx_parm {\n\tu8 bStart;\n\tu8 curr_rfpath;\n};\n\n/*H2C Handler index: 52 */\nstruct SetCarrierSuppressionTx_parm {\n\tu8 bStart;\n\tu32 curr_rateidx;\n};\n\n/*H2C Handler index: 53 */\nstruct SetContinuousTx_parm {\n\tu8 bStart;\n\tu8 CCK_flag; /*1:CCK 2:OFDM*/\n\tu32 curr_rateidx;\n};\n\n/*H2C Handler index: 54 */\nstruct SwitchBandwidth_parm {\n\tu8 curr_bandwidth;\n};\n\n#endif\t/* MP_FIRMWARE_OFFLOAD */\n\n/*H2C Handler index: 59 */\nstruct SetChannelPlan_param {\n\tconst struct country_chplan *country_ent;\n\tu8 channel_plan;\n};\n\n/*H2C Handler index: 60 */\nstruct LedBlink_param {\n\tvoid *pLed;\n};\n\n/*H2C Handler index: 62 */\nstruct TDLSoption_param {\n\tu8 addr[ETH_ALEN];\n\tu8 option;\n};\n\n/*H2C Handler index: 64 */\nstruct RunInThread_param {\n\tvoid (*func)(void *);\n\tvoid *context;\n};\n\n\n#define GEN_CMD_CODE(cmd)\tcmd ## _CMD_\n\n\n/*\n\nResult:\n0x00: success\n0x01: sucess, and check Response.\n0x02: cmd ignored due to duplicated sequcne number\n0x03: cmd dropped due to invalid cmd code\n0x04: reserved.\n\n*/\n\n#define H2C_RSP_OFFSET\t\t\t512\n\n#define H2C_SUCCESS\t\t\t0x00\n#define H2C_SUCCESS_RSP\t\t\t0x01\n#define H2C_DUPLICATED\t\t\t0x02\n#define H2C_DROPPED\t\t\t0x03\n#define H2C_PARAMETERS_ERROR\t\t0x04\n#define H2C_REJECTED\t\t\t0x05\n#define H2C_CMD_OVERFLOW\t\t0x06\n#define H2C_RESERVED\t\t\t0x07\n#define H2C_ENQ_HEAD\t\t\t0x08\n#define H2C_ENQ_HEAD_FAIL\t\t0x09\n#define H2C_CMD_FAIL\t\t\t0x0A\n\nextern u8 rtw_setassocsta_cmd(_adapter  *padapter, u8 *mac_addr);\nextern u8 rtw_setstandby_cmd(_adapter *padapter, uint action);\nvoid rtw_init_sitesurvey_parm(_adapter *padapter, struct sitesurvey_parm *pparm);\nu8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm);\nu8 rtw_create_ibss_cmd(_adapter *adapter, int flags);\nu8 rtw_startbss_cmd(_adapter *adapter, int flags);\n\n#define REQ_CH_NONE\t\t-1\n#define REQ_BW_NONE\t\t-1\n#define REQ_BW_ORI\t\t-2\n#define REQ_OFFSET_NONE\t-1\n\nu8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags\n\t, u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset);\n\nextern u8 rtw_setphy_cmd(_adapter  *padapter, u8 modem, u8 ch);\n\nstruct sta_info;\nextern u8 rtw_setstakey_cmd(_adapter  *padapter, struct sta_info *sta, u8 key_type, bool enqueue);\nextern u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue);\n\nextern u8 rtw_joinbss_cmd(_adapter  *padapter, struct wlan_network *pnetwork);\nu8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags);\nextern u8 rtw_setopmode_cmd(_adapter  *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags);\nextern u8 rtw_setdatarate_cmd(_adapter  *padapter, u8 *rateset);\nextern u8 rtw_setbasicrate_cmd(_adapter  *padapter, u8 *rateset);\nextern u8 rtw_getmacreg_cmd(_adapter *padapter, u8 len, u32 addr);\nextern void rtw_usb_catc_trigger_cmd(_adapter *padapter, const char *caller);\nextern u8 rtw_setbbreg_cmd(_adapter *padapter, u8 offset, u8 val);\nextern u8 rtw_setrfreg_cmd(_adapter *padapter, u8 offset, u32 val);\nextern u8 rtw_getbbreg_cmd(_adapter *padapter, u8 offset, u8 *pval);\nextern u8 rtw_getrfreg_cmd(_adapter *padapter, u8 offset, u8 *pval);\nextern u8 rtw_setrfintfs_cmd(_adapter  *padapter, u8 mode);\nextern u8 rtw_setrttbl_cmd(_adapter  *padapter, struct setratable_parm *prate_table);\nextern u8 rtw_getrttbl_cmd(_adapter  *padapter, struct getratable_rsp *pval);\n\nextern u8 rtw_gettssi_cmd(_adapter  *padapter, u8 offset, u8 *pval);\nextern u8 rtw_setfwdig_cmd(_adapter *padapter, u8 type);\nextern u8 rtw_setfwra_cmd(_adapter *padapter, u8 type);\n\nextern u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr);\nextern u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u16 start_seq);\n/* add for CONFIG_IEEE80211W, none 11w also can use */\nextern u8 rtw_reset_securitypriv_cmd(_adapter *padapter);\nextern u8 rtw_free_assoc_resources_cmd(_adapter *padapter, u8 lock_scanned_queue, int flags);\nextern u8 rtw_dynamic_chk_wk_cmd(_adapter *adapter);\n\nu8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 flags);\nu8 rtw_lps_ctrl_leave_set_level_cmd(_adapter *adapter, u8 lps_level, u8 flags);\n#ifdef CONFIG_LPS_1T1R\nu8 rtw_lps_ctrl_leave_set_1t1r_cmd(_adapter *adapter, u8 lps_1t1r, u8 flags);\n#endif\nu8 rtw_dm_in_lps_wk_cmd(_adapter *padapter);\nu8 rtw_lps_change_dtim_cmd(_adapter *padapter, u8 dtim);\n\n#if (RATE_ADAPTIVE_SUPPORT == 1)\nu8 rtw_rpt_timer_cfg_cmd(_adapter *padapter, u16 minRptTime);\n#endif\n\n#ifdef CONFIG_ANTENNA_DIVERSITY\nextern  u8 rtw_antenna_select_cmd(_adapter *padapter, u8 antenna, u8 enqueue);\n#endif\n\nu8 rtw_dm_ra_mask_wk_cmd(_adapter *padapter, u8 *psta);\n\nextern u8 rtw_ps_cmd(_adapter *padapter);\n\n#ifdef CONFIG_DFS\nvoid rtw_dfs_ch_switch_hdl(struct dvobj_priv *dvobj);\n#endif\n\n#ifdef CONFIG_AP_MODE\nu8 rtw_chk_hi_queue_cmd(_adapter *padapter);\n#ifdef CONFIG_DFS_MASTER\nu8 rtw_dfs_rd_cmd(_adapter *adapter, bool enqueue);\nvoid rtw_dfs_rd_timer_hdl(void *ctx);\nvoid rtw_dfs_rd_en_decision(_adapter *adapter, u8 mlme_act, u8 excl_ifbmp);\nu8 rtw_dfs_rd_en_decision_cmd(_adapter *adapter);\n#endif /* CONFIG_DFS_MASTER */\n#endif /* CONFIG_AP_MODE */\n\n#ifdef CONFIG_BT_COEXIST\nu8 rtw_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length);\nu8 rtw_btc_reduce_wl_txpwr_cmd(_adapter *adapter, u32 val);\n#endif\n\nu8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len);\n\nu8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter);\nu8 rtw_periodic_tsf_update_end_cmd(_adapter *adapter);\n\nu8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags);\n\nu8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 swconfig);\nu8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, u8 swconfig);\n\nextern u8 rtw_led_blink_cmd(_adapter *padapter, void *pLed);\nextern u8 rtw_set_csa_cmd(_adapter *adapter);\nextern u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option);\n\nu8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags);\n\n#ifdef CONFIG_RTW_CUSTOMER_STR\nu8 rtw_customer_str_req_cmd(_adapter *adapter);\nu8 rtw_customer_str_write_cmd(_adapter *adapter, const u8 *cstr);\n#endif\n\n#ifdef CONFIG_FW_C2H_REG\nu8 rtw_c2h_reg_wk_cmd(_adapter *adapter, u8 *c2h_evt);\n#endif\n#ifdef CONFIG_FW_C2H_PKT\nu8 rtw_c2h_packet_wk_cmd(_adapter *adapter, u8 *c2h_evt, u16 length);\n#endif\n\n#ifdef CONFIG_RTW_REPEATER_SON\n#define RSON_SCAN_PROCESS\t\t10\n#define RSON_SCAN_DISABLE\t\t11\nu8 rtw_rson_scan_wk_cmd(_adapter *adapter, int op);\n#endif\n\nu8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void *), void *context);\n\nstruct ssmps_cmd_parm {\n\tstruct sta_info *sta;\n\tu8 smps;\n};\nu8 rtw_ssmps_wk_cmd(_adapter *adapter, struct sta_info *sta, u8 smps, u8 enqueue);\n\nu8 session_tracker_chk_cmd(_adapter *adapter, struct sta_info *sta);\nu8 session_tracker_add_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);\nu8 session_tracker_del_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);\n\n#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW)\nu8 rtw_req_per_cmd(_adapter * adapter);\n#endif\n\n#ifdef CONFIG_CTRL_TXSS_BY_TP\nstruct txss_cmd_parm {\n\tstruct sta_info *sta;\n\tbool tx_1ss;\n};\n\nvoid rtw_ctrl_txss_update_mimo_type(_adapter *adapter, struct sta_info *sta);\nu8 rtw_ctrl_txss(_adapter *adapter, struct sta_info *sta, bool tx_1ss);\nvoid rtw_ctrl_tx_ss_by_tp(_adapter *adapter, u8 from_timer);\n\n#ifdef DBG_CTRL_TXSS\nvoid dbg_ctrl_txss(_adapter *adapter, bool tx_1ss);\n#endif\n#endif\n\nu8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf);\n\nextern void rtw_survey_cmd_callback(_adapter  *padapter, struct cmd_obj *pcmd);\nextern void rtw_disassoc_cmd_callback(_adapter  *padapter, struct cmd_obj *pcmd);\nextern void rtw_joinbss_cmd_callback(_adapter  *padapter, struct cmd_obj *pcmd);\nvoid rtw_create_ibss_post_hdl(_adapter *padapter, int status);\nextern void rtw_getbbrfreg_cmdrsp_callback(_adapter  *padapter, struct cmd_obj *pcmd);\nextern void rtw_readtssi_cmdrsp_callback(_adapter\t*padapter,  struct cmd_obj *pcmd);\n\nextern void rtw_setstaKey_cmdrsp_callback(_adapter  *padapter,  struct cmd_obj *pcmd);\nextern void rtw_setassocsta_cmdrsp_callback(_adapter  *padapter,  struct cmd_obj *pcmd);\nextern void rtw_getrttbl_cmdrsp_callback(_adapter  *padapter,  struct cmd_obj *pcmd);\nextern void rtw_getmacreg_cmdrsp_callback(_adapter *padapter,  struct cmd_obj *pcmd);\n\n\nstruct _cmd_callback {\n\tu32\tcmd_code;\n\tvoid (*callback)(_adapter  *padapter, struct cmd_obj *cmd);\n};\n\nenum rtw_h2c_cmd {\n\tGEN_CMD_CODE(_Read_MACREG) ,\t/*0*/\n\tGEN_CMD_CODE(_Write_MACREG) ,\n\tGEN_CMD_CODE(_Read_BBREG) ,\n\tGEN_CMD_CODE(_Write_BBREG) ,\n\tGEN_CMD_CODE(_Read_RFREG) ,\n\tGEN_CMD_CODE(_Write_RFREG) , /*5*/\n\tGEN_CMD_CODE(_Read_EEPROM) ,\n\tGEN_CMD_CODE(_Write_EEPROM) ,\n\tGEN_CMD_CODE(_Read_EFUSE) ,\n\tGEN_CMD_CODE(_Write_EFUSE) ,\n\n\tGEN_CMD_CODE(_Read_CAM) ,\t/*10*/\n\tGEN_CMD_CODE(_Write_CAM) ,\n\tGEN_CMD_CODE(_setBCNITV),\n\tGEN_CMD_CODE(_setMBIDCFG),\n\tGEN_CMD_CODE(_JoinBss),   /*14*/\n\tGEN_CMD_CODE(_DisConnect) , /*15*/\n\tGEN_CMD_CODE(_CreateBss) ,\n\tGEN_CMD_CODE(_SetOpMode) ,\n\tGEN_CMD_CODE(_SiteSurvey),  /*18*/\n\tGEN_CMD_CODE(_SetAuth) ,\n\n\tGEN_CMD_CODE(_SetKey) ,\t/*20*/\n\tGEN_CMD_CODE(_SetStaKey) ,\n\tGEN_CMD_CODE(_SetAssocSta) ,\n\tGEN_CMD_CODE(_DelAssocSta) ,\n\tGEN_CMD_CODE(_SetStaPwrState) ,\n\tGEN_CMD_CODE(_SetBasicRate) , /*25*/\n\tGEN_CMD_CODE(_GetBasicRate) ,\n\tGEN_CMD_CODE(_SetDataRate) ,\n\tGEN_CMD_CODE(_GetDataRate) ,\n\tGEN_CMD_CODE(_SetPhyInfo) ,\n\n\tGEN_CMD_CODE(_GetPhyInfo) ,\t/*30*/\n\tGEN_CMD_CODE(_SetPhy) ,\n\tGEN_CMD_CODE(_GetPhy) ,\n\tGEN_CMD_CODE(_readRssi) ,\n\tGEN_CMD_CODE(_readGain) ,\n\tGEN_CMD_CODE(_SetAtim) , /*35*/\n\tGEN_CMD_CODE(_SetPwrMode) ,\n\tGEN_CMD_CODE(_JoinbssRpt),\n\tGEN_CMD_CODE(_SetRaTable) ,\n\tGEN_CMD_CODE(_GetRaTable) ,\n\n\tGEN_CMD_CODE(_GetCCXReport), /*40*/\n\tGEN_CMD_CODE(_GetDTMReport),\n\tGEN_CMD_CODE(_GetTXRateStatistics),\n\tGEN_CMD_CODE(_SetUsbSuspend),\n\tGEN_CMD_CODE(_SetH2cLbk),\n\tGEN_CMD_CODE(_AddBAReq) , /*45*/\n\tGEN_CMD_CODE(_SetChannel), /*46*/\n\tGEN_CMD_CODE(_SetTxPower),\n\tGEN_CMD_CODE(_SwitchAntenna),\n\tGEN_CMD_CODE(_SetCrystalCap),\n\tGEN_CMD_CODE(_SetSingleCarrierTx), /*50*/\n\n\tGEN_CMD_CODE(_SetSingleToneTx),/*51*/\n\tGEN_CMD_CODE(_SetCarrierSuppressionTx),\n\tGEN_CMD_CODE(_SetContinuousTx),\n\tGEN_CMD_CODE(_SwitchBandwidth), /*54*/\n\tGEN_CMD_CODE(_TX_Beacon), /*55*/\n\n\tGEN_CMD_CODE(_Set_MLME_EVT), /*56*/\n\tGEN_CMD_CODE(_Set_Drv_Extra), /*57*/\n\tGEN_CMD_CODE(_Set_H2C_MSG), /*58*/\n\n\tGEN_CMD_CODE(_SetChannelPlan), /*59*/\n\tGEN_CMD_CODE(_LedBlink), /*60*/\n\n\tGEN_CMD_CODE(_SetChannelSwitch), /*61*/\n\tGEN_CMD_CODE(_TDLS), /*62*/\n\tGEN_CMD_CODE(_ChkBMCSleepq), /*63*/\n\n\tGEN_CMD_CODE(_RunInThreadCMD), /*64*/\n\tGEN_CMD_CODE(_AddBARsp) , /*65*/\n\tGEN_CMD_CODE(_RM_POST_EVENT), /*66*/\n\n\tMAX_H2CCMD\n};\n\n#define _GetMACReg_CMD_ _Read_MACREG_CMD_\n#define _SetMACReg_CMD_ _Write_MACREG_CMD_\n#define _GetBBReg_CMD_\t\t_Read_BBREG_CMD_\n#define _SetBBReg_CMD_\t\t_Write_BBREG_CMD_\n#define _GetRFReg_CMD_\t\t_Read_RFREG_CMD_\n#define _SetRFReg_CMD_\t\t_Write_RFREG_CMD_\n\n#ifdef _RTW_CMD_C_\nstruct _cmd_callback\trtw_cmd_callback[] = {\n\t{GEN_CMD_CODE(_Read_MACREG), &rtw_getmacreg_cmdrsp_callback}, /*0*/\n\t{GEN_CMD_CODE(_Write_MACREG), NULL},\n\t{GEN_CMD_CODE(_Read_BBREG), &rtw_getbbrfreg_cmdrsp_callback},\n\t{GEN_CMD_CODE(_Write_BBREG), NULL},\n\t{GEN_CMD_CODE(_Read_RFREG), &rtw_getbbrfreg_cmdrsp_callback},\n\t{GEN_CMD_CODE(_Write_RFREG), NULL}, /*5*/\n\t{GEN_CMD_CODE(_Read_EEPROM), NULL},\n\t{GEN_CMD_CODE(_Write_EEPROM), NULL},\n\t{GEN_CMD_CODE(_Read_EFUSE), NULL},\n\t{GEN_CMD_CODE(_Write_EFUSE), NULL},\n\n\t{GEN_CMD_CODE(_Read_CAM),\tNULL},\t/*10*/\n\t{GEN_CMD_CODE(_Write_CAM),\t NULL},\n\t{GEN_CMD_CODE(_setBCNITV), NULL},\n\t{GEN_CMD_CODE(_setMBIDCFG), NULL},\n\t{GEN_CMD_CODE(_JoinBss), &rtw_joinbss_cmd_callback},  /*14*/\n\t{GEN_CMD_CODE(_DisConnect), &rtw_disassoc_cmd_callback}, /*15*/\n\t{GEN_CMD_CODE(_CreateBss), NULL},\n\t{GEN_CMD_CODE(_SetOpMode), NULL},\n\t{GEN_CMD_CODE(_SiteSurvey), &rtw_survey_cmd_callback}, /*18*/\n\t{GEN_CMD_CODE(_SetAuth), NULL},\n\n\t{GEN_CMD_CODE(_SetKey), NULL},\t/*20*/\n\t{GEN_CMD_CODE(_SetStaKey), &rtw_setstaKey_cmdrsp_callback},\n\t{GEN_CMD_CODE(_SetAssocSta), &rtw_setassocsta_cmdrsp_callback},\n\t{GEN_CMD_CODE(_DelAssocSta), NULL},\n\t{GEN_CMD_CODE(_SetStaPwrState), NULL},\n\t{GEN_CMD_CODE(_SetBasicRate), NULL}, /*25*/\n\t{GEN_CMD_CODE(_GetBasicRate), NULL},\n\t{GEN_CMD_CODE(_SetDataRate), NULL},\n\t{GEN_CMD_CODE(_GetDataRate), NULL},\n\t{GEN_CMD_CODE(_SetPhyInfo), NULL},\n\n\t{GEN_CMD_CODE(_GetPhyInfo), NULL}, /*30*/\n\t{GEN_CMD_CODE(_SetPhy), NULL},\n\t{GEN_CMD_CODE(_GetPhy), NULL},\n\t{GEN_CMD_CODE(_readRssi), NULL},\n\t{GEN_CMD_CODE(_readGain), NULL},\n\t{GEN_CMD_CODE(_SetAtim), NULL}, /*35*/\n\t{GEN_CMD_CODE(_SetPwrMode), NULL},\n\t{GEN_CMD_CODE(_JoinbssRpt), NULL},\n\t{GEN_CMD_CODE(_SetRaTable), NULL},\n\t{GEN_CMD_CODE(_GetRaTable) , NULL},\n\n\t{GEN_CMD_CODE(_GetCCXReport), NULL}, /*40*/\n\t{GEN_CMD_CODE(_GetDTMReport),\tNULL},\n\t{GEN_CMD_CODE(_GetTXRateStatistics), NULL},\n\t{GEN_CMD_CODE(_SetUsbSuspend), NULL},\n\t{GEN_CMD_CODE(_SetH2cLbk), NULL},\n\t{GEN_CMD_CODE(_AddBAReq), NULL}, /*45*/\n\t{GEN_CMD_CODE(_SetChannel), NULL},\t\t/*46*/\n\t{GEN_CMD_CODE(_SetTxPower), NULL},\n\t{GEN_CMD_CODE(_SwitchAntenna), NULL},\n\t{GEN_CMD_CODE(_SetCrystalCap), NULL},\n\t{GEN_CMD_CODE(_SetSingleCarrierTx), NULL},\t/*50*/\n\n\t{GEN_CMD_CODE(_SetSingleToneTx), NULL}, /*51*/\n\t{GEN_CMD_CODE(_SetCarrierSuppressionTx), NULL},\n\t{GEN_CMD_CODE(_SetContinuousTx), NULL},\n\t{GEN_CMD_CODE(_SwitchBandwidth), NULL},\t\t/*54*/\n\t{GEN_CMD_CODE(_TX_Beacon), NULL},/*55*/\n\n\t{GEN_CMD_CODE(_Set_MLME_EVT), NULL},/*56*/\n\t{GEN_CMD_CODE(_Set_Drv_Extra), NULL},/*57*/\n\t{GEN_CMD_CODE(_Set_H2C_MSG), NULL},/*58*/\n\t{GEN_CMD_CODE(_SetChannelPlan), NULL},/*59*/\n\t{GEN_CMD_CODE(_LedBlink), NULL},/*60*/\n\n\t{GEN_CMD_CODE(_SetChannelSwitch), NULL},/*61*/\n\t{GEN_CMD_CODE(_TDLS), NULL},/*62*/\n\t{GEN_CMD_CODE(_ChkBMCSleepq), NULL}, /*63*/\n\n\t{GEN_CMD_CODE(_RunInThreadCMD), NULL},/*64*/\n\t{GEN_CMD_CODE(_AddBARsp), NULL}, /*65*/\n\t{GEN_CMD_CODE(_RM_POST_EVENT), NULL}, /*66*/\n};\n#endif\n\n#define CMD_FMT \"cmd=%d,%d,%d\"\n#define CMD_ARG(cmd) \\\n\t(cmd)->cmdcode, \\\n\t(cmd)->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra) ? ((struct drvextra_cmd_parm *)(cmd)->parmbuf)->ec_id : ((cmd)->cmdcode == GEN_CMD_CODE(_Set_MLME_EVT) ? ((struct C2HEvent_Header *)(cmd)->parmbuf)->ID : 0), \\\n\t(cmd)->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra) ? ((struct drvextra_cmd_parm *)(cmd)->parmbuf)->type : 0\n\n#endif /* _CMD_H_ */\n"
  },
  {
    "path": "include/rtw_debug.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_DEBUG_H__\n#define __RTW_DEBUG_H__\n\n/* driver log level*/\nenum {\n\t_DRV_NONE_ = 0,\n\t_DRV_ALWAYS_ = 1,\n\t_DRV_ERR_ = 2,\n\t_DRV_WARNING_ = 3,\n\t_DRV_INFO_ = 4,\n\t_DRV_DEBUG_ = 5,\n\t_DRV_MAX_ = 6\n};\n\n#define DRIVER_PREFIX \"RTW: \"\n\n#ifdef PLATFORM_OS_CE\nextern void rtl871x_cedbg(const char *fmt, ...);\n#endif\n\n#ifdef PLATFORM_WINDOWS\n\t#define RTW_PRINT do {} while (0)\n\t#define RTW_ERR do {} while (0)\n\t#define RTW_WARN do {} while (0)\n\t#define RTW_INFO do {} while (0)\n\t#define RTW_DBG do {} while (0)\n\t#define RTW_PRINT_SEL do {} while (0)\n\t#define _RTW_PRINT do {} while (0)\n\t#define _RTW_ERR do {} while (0)\n\t#define _RTW_WARN do {} while (0)\n\t#define _RTW_INFO do {} while (0)\n\t#define _RTW_DBG do {} while (0)\n\t#define _RTW_PRINT_SEL do {} while (0)\n#else\n\t#define RTW_PRINT(x, ...) do {} while (0)\n\t#define RTW_ERR(x, ...) do {} while (0)\n\t#define RTW_WARN(x,...) do {} while (0)\n\t#define RTW_INFO(x,...) do {} while (0)\n\t#define RTW_DBG(x,...) do {} while (0)\n\t#define RTW_PRINT_SEL(x,...) do {} while (0)\n\t#define _RTW_PRINT(x, ...) do {} while (0)\n\t#define _RTW_ERR(x, ...) do {} while (0)\n\t#define _RTW_WARN(x,...) do {} while (0)\n\t#define _RTW_INFO(x,...) do {} while (0)\n\t#define _RTW_DBG(x,...) do {} while (0)\n\t#define _RTW_PRINT_SEL(x,...) do {} while (0)\n#endif\n\n#define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0)\n#define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0)\n#define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0)\n\n#define RTW_DBG_EXPR(EXPR) do {} while (0)\n\n#define RTW_DBGDUMP 0 /* 'stream' for _dbgdump */\n\n\n\n#undef _dbgdump\n#undef _seqdump\n\n#if defined(PLATFORM_WINDOWS) && defined(PLATFORM_OS_XP)\n\t#define _dbgdump DbgPrint\n\t#define KERN_CONT\n\t#define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg)\n#elif defined(PLATFORM_WINDOWS) && defined(PLATFORM_OS_CE)\n\t#define _dbgdump rtl871x_cedbg\n\t#define KERN_CONT\n\t#define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg)\n#elif defined PLATFORM_LINUX\n\t#define _dbgdump printk\n\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))\n\t#define KERN_CONT\n\t#endif\n\t#define _seqdump seq_printf\n#elif defined PLATFORM_FREEBSD\n\t#define _dbgdump printf\n\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))\n\t#define KERN_CONT\n\t#endif\n\t#define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg)\n#endif\n\nvoid RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring,\n\t\t\t\t\t\t\t\tbool _idx_show, const u8 *_hexdata, int _hexdatalen);\n\n#ifdef CONFIG_RTW_DEBUG\n\n#ifndef _OS_INTFS_C_\nextern uint rtw_drv_log_level;\n#endif\n\n#if defined(_dbgdump)\n\n/* with driver-defined prefix */\n#undef RTW_PRINT\n#define RTW_PRINT(fmt, arg...)     \\\n\tdo {\\\n\t\tif (_DRV_ALWAYS_ <= rtw_drv_log_level) {\\\n\t\t\t_dbgdump(DRIVER_PREFIX fmt, ##arg);\\\n\t\t} \\\n\t} while (0)\n\n#undef RTW_ERR\n#define RTW_ERR(fmt, arg...)     \\\n\tdo {\\\n\t\tif (_DRV_ERR_ <= rtw_drv_log_level) {\\\n\t\t\t_dbgdump(DRIVER_PREFIX\"ERROR \" fmt, ##arg);\\\n\t\t} \\\n\t} while (0)\n\n\n#undef RTW_WARN\n#define RTW_WARN(fmt, arg...)     \\\n\tdo {\\\n\t\tif (_DRV_WARNING_ <= rtw_drv_log_level) {\\\n\t\t\t_dbgdump(DRIVER_PREFIX\"WARN \" fmt, ##arg);\\\n\t\t} \\\n\t} while (0)\n\n#undef RTW_INFO\n#define RTW_INFO(fmt, arg...)     \\\n\tdo {\\\n\t\tif (_DRV_INFO_ <= rtw_drv_log_level) {\\\n\t\t\t_dbgdump(DRIVER_PREFIX fmt, ##arg);\\\n\t\t} \\\n\t} while (0)\n\n\n#undef RTW_DBG\n#define RTW_DBG(fmt, arg...)     \\\n\tdo {\\\n\t\tif (_DRV_DEBUG_ <= rtw_drv_log_level) {\\\n\t\t\t_dbgdump(DRIVER_PREFIX fmt, ##arg);\\\n\t\t} \\\n\t} while (0)\n\n#undef RTW_INFO_DUMP\n#define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen)\t\\\n\tRTW_BUF_DUMP_SEL(_DRV_INFO_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen)\n\n#undef RTW_DBG_DUMP\n#define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen)\t\\\n\tRTW_BUF_DUMP_SEL(_DRV_DEBUG_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen)\n\n\n#undef RTW_PRINT_DUMP\n#define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen)\t\\\n\tRTW_BUF_DUMP_SEL(_DRV_ALWAYS_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen)\n\n/* without driver-defined prefix */\n#undef _RTW_PRINT\n#define _RTW_PRINT(fmt, arg...)     \\\n\tdo {\\\n\t\tif (_DRV_ALWAYS_ <= rtw_drv_log_level) {\\\n\t\t\t_dbgdump(KERN_CONT fmt, ##arg);\\\n\t\t} \\\n\t} while (0)\n\n#undef _RTW_ERR\n#define _RTW_ERR(fmt, arg...)     \\\n\tdo {\\\n\t\tif (_DRV_ERR_ <= rtw_drv_log_level) {\\\n\t\t\t_dbgdump(KERN_CONT fmt, ##arg);\\\n\t\t} \\\n\t} while (0)\n\n\n#undef _RTW_WARN\n#define _RTW_WARN(fmt, arg...)     \\\n\tdo {\\\n\t\tif (_DRV_WARNING_ <= rtw_drv_log_level) {\\\n\t\t\t_dbgdump(KERN_CONT fmt, ##arg);\\\n\t\t} \\\n\t} while (0)\n\n#undef _RTW_INFO\n#define _RTW_INFO(fmt, arg...)     \\\n\tdo {\\\n\t\tif (_DRV_INFO_ <= rtw_drv_log_level) {\\\n\t\t\t_dbgdump(KERN_CONT fmt, ##arg);\\\n\t\t} \\\n\t} while (0)\n\n#undef _RTW_DBG\n#define _RTW_DBG(fmt, arg...)     \\\n\tdo {\\\n\t\tif (_DRV_DEBUG_ <= rtw_drv_log_level) {\\\n\t\t\t_dbgdump(KERN_CONT fmt, ##arg);\\\n\t\t} \\\n\t} while (0)\n\n\n/* other debug APIs */\n#undef RTW_DBG_EXPR\n#define RTW_DBG_EXPR(EXPR) do { if (_DRV_DEBUG_ <= rtw_drv_log_level) EXPR; } while (0)\n\n#endif /* defined(_dbgdump) */\n#endif /* CONFIG_RTW_DEBUG */\n\n\n#if defined(_seqdump)\n/* dump message to selected 'stream' with driver-defined prefix */\n#undef RTW_PRINT_SEL\n#define RTW_PRINT_SEL(sel, fmt, arg...) \\\n\tdo {\\\n\t\tif (sel == RTW_DBGDUMP)\\\n\t\t\tRTW_PRINT(fmt, ##arg); \\\n\t\telse {\\\n\t\t\t_seqdump(sel, fmt, ##arg) /*rtw_warn_on(1)*/; \\\n\t\t} \\\n\t} while (0)\n\n/* dump message to selected 'stream' */\n#undef _RTW_PRINT_SEL\n#define _RTW_PRINT_SEL(sel, fmt, arg...) \\\n\tdo {\\\n\t\tif (sel == RTW_DBGDUMP)\\\n\t\t\t_RTW_PRINT(fmt, ##arg); \\\n\t\telse {\\\n\t\t\t_seqdump(sel, fmt, ##arg) /*rtw_warn_on(1)*/; \\\n\t\t} \\\n\t} while (0)\n\n/* dump message to selected 'stream' */\n#undef RTW_DUMP_SEL\n#define RTW_DUMP_SEL(sel, _HexData, _HexDataLen) \\\n\tRTW_BUF_DUMP_SEL(_DRV_ALWAYS_, sel, NULL, _FALSE, _HexData, _HexDataLen)\n\n#define RTW_MAP_DUMP_SEL(sel, _TitleString, _HexData, _HexDataLen) \\\n\tRTW_BUF_DUMP_SEL(_DRV_ALWAYS_, sel, _TitleString, _TRUE, _HexData, _HexDataLen)\n#endif /* defined(_seqdump) */\n\n\n#ifdef CONFIG_DBG_COUNTER\n\t#define DBG_COUNTER(counter) counter++\n#else\n\t#define DBG_COUNTER(counter)\n#endif\n\nvoid dump_drv_version(void *sel);\nvoid dump_log_level(void *sel);\nvoid dump_drv_cfg(void *sel);\n\n#ifdef CONFIG_SDIO_HCI\nvoid sd_f0_reg_dump(void *sel, _adapter *adapter);\nvoid sdio_local_reg_dump(void *sel, _adapter *adapter);\n#ifdef CONFIG_SDIO_MONITOR\nu32 sd_monitor_sdio_clk(_adapter *adapter, u8 clk_monitor_mode);\n#endif\n#endif /* CONFIG_SDIO_HCI */\n\nvoid mac_reg_dump(void *sel, _adapter *adapter);\nvoid bb_reg_dump(void *sel, _adapter *adapter);\nvoid bb_reg_dump_ex(void *sel, _adapter *adapter);\nvoid rf_reg_dump(void *sel, _adapter *adapter);\n\nvoid rtw_sink_rtp_seq_dbg(_adapter *adapter, u8 *ehdr_pos);\n\nstruct sta_info;\nvoid sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta);\n\nstruct dvobj_priv;\nvoid dump_tx_rate_bmp(void *sel, struct dvobj_priv *dvobj);\nvoid dump_adapters_status(void *sel, struct dvobj_priv *dvobj);\n\nstruct sec_cam_ent;\nvoid dump_sec_cam_ent(void *sel, struct sec_cam_ent *ent, int id);\nvoid dump_sec_cam_ent_title(void *sel, u8 has_id);\nvoid dump_sec_cam(void *sel, _adapter *adapter);\nvoid dump_sec_cam_cache(void *sel, _adapter *adapter);\n\nbool rtw_fwdl_test_trigger_chksum_fail(void);\nbool rtw_fwdl_test_trigger_wintint_rdy_fail(void);\nbool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void);\nu32 rtw_get_wait_hiq_empty_ms(void);\nvoid rtw_sta_linking_test_set_start(void);\nbool rtw_sta_linking_test_wait_done(void);\nbool rtw_sta_linking_test_force_fail(void);\n#ifdef CONFIG_AP_MODE\nu16 rtw_ap_linking_test_force_auth_fail(void);\nu16 rtw_ap_linking_test_force_asoc_fail(void);\n#endif\n\n#ifdef CONFIG_PROC_DEBUG\nssize_t proc_set_write_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_read_reg(struct seq_file *m, void *v);\nssize_t proc_set_read_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\nint proc_get_fwstate(struct seq_file *m, void *v);\nint proc_get_sec_info(struct seq_file *m, void *v);\nint proc_get_mlmext_state(struct seq_file *m, void *v);\n#ifdef CONFIG_LAYER2_ROAMING\nint proc_get_roam_flags(struct seq_file *m, void *v);\nssize_t proc_set_roam_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_roam_param(struct seq_file *m, void *v);\nssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nssize_t proc_set_roam_tgt_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif /* CONFIG_LAYER2_ROAMING */\n#ifdef CONFIG_RTW_80211R\nint proc_get_ft_flags(struct seq_file *m, void *v);\nssize_t proc_set_ft_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif\nint proc_get_qos_option(struct seq_file *m, void *v);\nint proc_get_ht_option(struct seq_file *m, void *v);\nint proc_get_rf_info(struct seq_file *m, void *v);\nint proc_get_scan_param(struct seq_file *m, void *v);\nssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_scan_abort(struct seq_file *m, void *v);\n#ifdef CONFIG_RTW_REPEATER_SON\nint proc_get_rson_data(struct seq_file *m, void *v);\nssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif\nint proc_get_survey_info(struct seq_file *m, void *v);\nssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_ap_info(struct seq_file *m, void *v);\n#ifdef ROKU_PRIVATE\nint proc_get_infra_ap(struct seq_file *m, void *v);\n#endif /* ROKU_PRIVATE */\nssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_trx_info(struct seq_file *m, void *v);\nssize_t proc_set_tx_power_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_tx_power_offset(struct seq_file *m, void *v);\nint proc_get_rate_ctl(struct seq_file *m, void *v);\nint proc_get_wifi_spec(struct seq_file *m, void *v);\nssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_bw_ctl(struct seq_file *m, void *v);\nssize_t proc_set_bw_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#ifdef DBG_RX_COUNTER_DUMP\nint proc_get_rx_cnt_dump(struct seq_file *m, void *v);\nssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif\n\n#ifdef CONFIG_AP_MODE\nint proc_get_bmc_tx_rate(struct seq_file *m, void *v);\nssize_t proc_set_bmc_tx_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif /*CONFIG_AP_MODE*/\n\nint proc_get_ps_dbg_info(struct seq_file *m, void *v);\nssize_t proc_set_ps_dbg_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\nssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#ifdef CONFIG_AP_MODE\nssize_t proc_set_ap_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif\n\nint proc_get_rx_stat(struct seq_file *m, void *v);\nint proc_get_tx_stat(struct seq_file *m, void *v);\n#ifdef CONFIG_AP_MODE\nint proc_get_all_sta_info(struct seq_file *m, void *v);\n#endif /* CONFIG_AP_MODE */\n\n#ifdef DBG_MEMORY_LEAK\nint proc_get_malloc_cnt(struct seq_file *m, void *v);\n#endif /* DBG_MEMORY_LEAK */\n\n#ifdef CONFIG_FIND_BEST_CHANNEL\nint proc_get_best_channel(struct seq_file *m, void *v);\nssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif /* CONFIG_FIND_BEST_CHANNEL */\n\nint proc_get_trx_info_debug(struct seq_file *m, void *v);\n\n#ifdef CONFIG_HUAWEI_PROC\nint proc_get_huawei_trx_info(struct seq_file *m, void *v);\n#endif\n\nint proc_get_rx_signal(struct seq_file *m, void *v);\nssize_t proc_set_rx_signal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_hw_status(struct seq_file *m, void *v);\nssize_t proc_set_hw_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_mac_rptbuf(struct seq_file *m, void *v);\n\n#ifdef CONFIG_80211N_HT\nint proc_get_ht_enable(struct seq_file *m, void *v);\nssize_t proc_set_ht_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\nint proc_get_bw_mode(struct seq_file *m, void *v);\nssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\nint proc_get_ampdu_enable(struct seq_file *m, void *v);\nssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\nvoid dump_regsty_rx_ampdu_size_limit(void *sel, _adapter *adapter);\nint proc_get_rx_ampdu(struct seq_file *m, void *v);\nssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\nvoid rtw_dump_dft_phy_cap(void *sel, _adapter *adapter);\nvoid rtw_get_dft_phy_cap(void *sel, _adapter *adapter);\nvoid rtw_dump_drv_phy_cap(void *sel, _adapter *adapter);\n\nint proc_get_rx_stbc(struct seq_file *m, void *v);\nssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_stbc_cap(struct seq_file *m, void *v);\nssize_t proc_set_stbc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_ldpc_cap(struct seq_file *m, void *v);\nssize_t proc_set_ldpc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#ifdef CONFIG_BEAMFORMING\nint proc_get_txbf_cap(struct seq_file *m, void *v);\nssize_t proc_set_txbf_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif\nint proc_get_rx_ampdu_factor(struct seq_file *m, void *v);\nssize_t proc_set_rx_ampdu_factor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\nint proc_get_tx_max_agg_num(struct seq_file *m, void *v);\nssize_t proc_set_tx_max_agg_num(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\nint proc_get_rx_ampdu_density(struct seq_file *m, void *v);\nssize_t proc_set_rx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\nint proc_get_tx_ampdu_density(struct seq_file *m, void *v);\nssize_t proc_set_tx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\nint proc_get_tx_quick_addba_req(struct seq_file *m, void *v);\nssize_t proc_set_tx_quick_addba_req(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#ifdef CONFIG_TX_AMSDU\nint proc_get_tx_amsdu(struct seq_file *m, void *v);\nssize_t proc_set_tx_amsdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_tx_amsdu_rate(struct seq_file *m, void *v);\nssize_t proc_set_tx_amsdu_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif\n#endif /* CONFIG_80211N_HT */\n\nint proc_get_en_fwps(struct seq_file *m, void *v);\nssize_t proc_set_en_fwps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\n#if 0\nint proc_get_two_path_rssi(struct seq_file *m, void *v);\nint proc_get_rssi_disp(struct seq_file *m, void *v);\nssize_t proc_set_rssi_disp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif\n\n#ifdef CONFIG_BT_COEXIST\nint proc_get_btcoex_dbg(struct seq_file *m, void *v);\nssize_t proc_set_btcoex_dbg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_btcoex_info(struct seq_file *m, void *v);\n#ifdef CONFIG_RF4CE_COEXIST\nint proc_get_rf4ce_state(struct seq_file *m, void *v);\nssize_t proc_set_rf4ce_state(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif\n#endif /* CONFIG_BT_COEXIST */\n\n#if defined(DBG_CONFIG_ERROR_DETECT)\nint proc_get_sreset(struct seq_file *m, void *v);\nssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif /* DBG_CONFIG_ERROR_DETECT */\n\nint proc_get_odm_adaptivity(struct seq_file *m, void *v);\nssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\n#ifdef CONFIG_DBG_COUNTER\nint proc_get_rx_logs(struct seq_file *m, void *v);\nint proc_get_tx_logs(struct seq_file *m, void *v);\nint proc_get_int_logs(struct seq_file *m, void *v);\n#endif\n\n#ifdef CONFIG_PCI_HCI\nint proc_get_rx_ring(struct seq_file *m, void *v);\nint proc_get_tx_ring(struct seq_file *m, void *v);\nint proc_get_pci_aspm(struct seq_file *m, void *v);\nint proc_get_pci_conf_space(struct seq_file *m, void *v);\nssize_t proc_set_pci_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\nint proc_get_pci_bridge_conf_space(struct seq_file *m, void *v);\nssize_t proc_set_pci_bridge_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\n\n#ifdef DBG_TXBD_DESC_DUMP\nint proc_get_tx_ring_ext(struct seq_file *m, void *v);\nssize_t proc_set_tx_ring_ext(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif\n#endif\n\n#ifdef CONFIG_WOWLAN\nint proc_get_pattern_info(struct seq_file *m, void *v);\nssize_t proc_set_pattern_info(struct file *file, const char __user *buffer,\n\t\tsize_t count, loff_t *pos, void *data);\nint proc_get_wakeup_event(struct seq_file *m, void *v);\nssize_t proc_set_wakeup_event(struct file *file, const char __user *buffer,\n\t\tsize_t count, loff_t *pos, void *data);\nint proc_get_wakeup_reason(struct seq_file *m, void *v);\n#endif\n\n#ifdef CONFIG_GPIO_WAKEUP\nint proc_get_wowlan_gpio_info(struct seq_file *m, void *v);\nssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer,\n\t\tsize_t count, loff_t *pos, void *data);\n#endif /*CONFIG_GPIO_WAKEUP*/\n\n#ifdef CONFIG_P2P_WOWLAN\nint proc_get_p2p_wowlan_info(struct seq_file *m, void *v);\n#endif /* CONFIG_P2P_WOWLAN */\n\nint proc_get_new_bcn_max(struct seq_file *m, void *v);\nssize_t proc_set_new_bcn_max(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\n#ifdef CONFIG_POWER_SAVING\nint proc_get_ps_info(struct seq_file *m, void *v);\nssize_t proc_set_ps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#ifdef CONFIG_WMMPS_STA\t\nint proc_get_wmmps_info(struct seq_file *m, void *v);\nssize_t proc_set_wmmps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif /* CONFIG_WMMPS_STA */\n#endif /* CONFIG_POWER_SAVING */\n\n#ifdef CONFIG_TDLS\nint proc_get_tdls_enable(struct seq_file *m, void *v);\nssize_t proc_set_tdls_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_tdls_info(struct seq_file *m, void *v);\n#endif\n\nint proc_get_monitor(struct seq_file *m, void *v);\nssize_t proc_set_monitor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\n#ifdef DBG_XMIT_BLOCK\nint proc_get_xmit_block(struct seq_file *m, void *v);\nssize_t proc_set_xmit_block(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif\n\n#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER\nint proc_get_rtkm_info(struct seq_file *m, void *v);\n#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */\n\n#ifdef CONFIG_IEEE80211W\nssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_tx_sa_query(struct seq_file *m, void *v);\nssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_tx_deauth(struct seq_file *m, void *v);\nssize_t proc_set_tx_auth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_tx_auth(struct seq_file *m, void *v);\n#endif /* CONFIG_IEEE80211W */\n\n#endif /* CONFIG_PROC_DEBUG */\n\nint proc_get_efuse_map(struct seq_file *m, void *v);\nssize_t proc_set_efuse_map(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\n#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA\nint proc_get_pathb_phase(struct seq_file *m, void *v);\nssize_t proc_set_pathb_phase(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif\n\n#ifdef CONFIG_MCC_MODE\nint proc_get_mcc_info(struct seq_file *m, void *v);\nssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nssize_t proc_set_mcc_duration(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#ifdef CONFIG_MCC_PHYDM_OFFLOAD\nssize_t proc_set_mcc_phydm_offload_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif\nssize_t proc_set_mcc_single_tx_criteria(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nssize_t proc_set_mcc_ap_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nssize_t proc_set_mcc_ap_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nssize_t proc_set_mcc_ap_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nssize_t proc_set_mcc_sta_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nssize_t proc_set_mcc_sta_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nssize_t proc_set_mcc_sta_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_mcc_policy_table(struct seq_file *m, void *v);\n#endif /* CONFIG_MCC_MODE */\n\nint proc_get_ack_timeout(struct seq_file *m, void *v);\nssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\nint proc_get_fw_offload(struct seq_file *m, void *v);\nssize_t proc_set_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n\n#ifdef CONFIG_FW_HANDLE_TXBCN\nssize_t proc_set_fw_tbtt_rpt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_fw_tbtt_rpt(struct seq_file *m, void *v);\n#endif\n\n#ifdef CONFIG_DBG_RF_CAL\nint proc_get_iqk_info(struct seq_file *m, void *v);\nssize_t proc_set_iqk(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_lck_info(struct seq_file *m, void *v);\nssize_t proc_set_lck(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n#endif /*CONFIG_DBG_RF_CAL*/\n\n#ifdef CONFIG_CTRL_TXSS_BY_TP\nssize_t proc_set_txss_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_txss_tp(struct seq_file *m, void *v);\n#ifdef DBG_CTRL_TXSS\nssize_t proc_set_txss_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_txss_ctrl(struct seq_file *m, void *v);\n#endif\n#endif\n\n#ifdef CONFIG_LPS_CHK_BY_TP\nssize_t proc_set_lps_chk_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_lps_chk_tp(struct seq_file *m, void *v);\n#endif\n\n#ifdef CONFIG_SUPPORT_STATIC_SMPS\nssize_t proc_set_smps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\nint proc_get_smps(struct seq_file *m, void *v);\n#endif\n\n#define _drv_always_\t\t1\n#define _drv_emerg_\t\t\t2\n#define _drv_alert_\t\t\t3\n#define _drv_crit_\t\t\t4\n#define _drv_err_\t\t\t5\n#define _drv_warning_\t\t6\n#define _drv_notice_\t\t7\n#define _drv_info_\t\t\t8\n#define _drv_dump_\t\t\t9\n#define _drv_debug_\t\t\t10\n\n#define _module_rtl871x_xmit_c_\t\tBIT(0)\n#define _module_xmit_osdep_c_\t\tBIT(1)\n#define _module_rtl871x_recv_c_\t\tBIT(2)\n#define _module_recv_osdep_c_\t\tBIT(3)\n#define _module_rtl871x_mlme_c_\t\tBIT(4)\n#define _module_mlme_osdep_c_\t\tBIT(5)\n#define _module_rtl871x_sta_mgt_c_\t\tBIT(6)\n#define _module_rtl871x_cmd_c_\t\t\tBIT(7)\n#define _module_cmd_osdep_c_\t\tBIT(8)\n#define _module_rtl871x_io_c_\t\t\t\tBIT(9)\n#define _module_io_osdep_c_\t\tBIT(10)\n#define _module_os_intfs_c_\t\t\tBIT(11)\n#define _module_rtl871x_security_c_\t\tBIT(12)\n#define _module_rtl871x_eeprom_c_\t\t\tBIT(13)\n#define _module_hal_init_c_\t\tBIT(14)\n#define _module_hci_hal_init_c_\t\tBIT(15)\n#define _module_rtl871x_ioctl_c_\t\tBIT(16)\n#define _module_rtl871x_ioctl_set_c_\t\tBIT(17)\n#define _module_rtl871x_ioctl_query_c_\tBIT(18)\n#define _module_rtl871x_pwrctrl_c_\t\t\tBIT(19)\n#define _module_hci_intfs_c_\t\t\tBIT(20)\n#define _module_hci_ops_c_\t\t\tBIT(21)\n#define _module_osdep_service_c_\t\t\tBIT(22)\n#define _module_mp_\t\t\tBIT(23)\n#define _module_hci_ops_os_c_\t\t\tBIT(24)\n#define _module_rtl871x_ioctl_os_c\t\tBIT(25)\n#define _module_rtl8712_cmd_c_\t\tBIT(26)\n/* #define _module_efuse_\t\t\tBIT(27) */\n#define\t_module_rtl8192c_xmit_c_ BIT(28)\n#define _module_hal_xmit_c_\tBIT(28)\n#define _module_efuse_\t\t\tBIT(29)\n#define _module_rtl8712_recv_c_\t\tBIT(30)\n#define _module_rtl8712_led_c_\t\tBIT(31)\n\n#endif /* __RTW_DEBUG_H__ */\n"
  },
  {
    "path": "include/rtw_eeprom.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_EEPROM_H__\n#define __RTW_EEPROM_H__\n\n\n#define\tRTL8712_EEPROM_ID\t\t\t0x8712\n/* #define\tEEPROM_MAX_SIZE\t\t\t256 */\n\n#define\tHWSET_MAX_SIZE_128\t\t128\n#define\tHWSET_MAX_SIZE_256\t\t256\n#define\tHWSET_MAX_SIZE_512\t\t512\n#define HWSET_MAX_SIZE_1024\t\t1024\n\n#define\tEEPROM_MAX_SIZE\t\t\tHWSET_MAX_SIZE_1024\n\n#define\tCLOCK_RATE\t\t\t\t\t50\t\t\t/* 100us\t\t */\n\n/* - EEPROM opcodes */\n#define EEPROM_READ_OPCODE\t\t06\n#define EEPROM_WRITE_OPCODE\t\t05\n#define EEPROM_ERASE_OPCODE\t\t07\n#define EEPROM_EWEN_OPCODE\t\t19      /* Erase/write enable */\n#define EEPROM_EWDS_OPCODE\t\t16      /* Erase/write disable */\n\n/* Country codes */\n#define USA\t\t\t\t\t\t\t0x555320\n#define EUROPE\t\t\t\t\t\t0x1 /* temp, should be provided later\t */\n#define JAPAN\t\t\t\t\t\t0x2 /* temp, should be provided later */\n\n/*\n * Customer ID, note that:\n * This variable is initiailzed through EEPROM or registry,\n * however, its definition may be different with that in EEPROM for\n * EEPROM size consideration. So, we have to perform proper translation between them.\n * Besides, CustomerID of registry has precedence of that of EEPROM.\n * defined below. 060703, by rcnjko.\n *   */\ntypedef enum _RT_CUSTOMER_ID {\n\tRT_CID_DEFAULT = 0,\n\tRT_CID_8187_ALPHA0 = 1,\n\tRT_CID_8187_SERCOMM_PS = 2,\n\tRT_CID_8187_HW_LED = 3,\n\tRT_CID_8187_NETGEAR = 4,\n\tRT_CID_WHQL = 5,\n\tRT_CID_819x_CAMEO  = 6,\n\tRT_CID_819x_RUNTOP = 7,\n\tRT_CID_819x_Senao = 8,\n\tRT_CID_TOSHIBA = 9,\t/* Merge by Jacken, 2008/01/31. */\n\tRT_CID_819x_Netcore = 10,\n\tRT_CID_Nettronix = 11,\n\tRT_CID_DLINK = 12,\n\tRT_CID_PRONET = 13,\n\tRT_CID_COREGA = 14,\n\tRT_CID_CHINA_MOBILE = 15,\n\tRT_CID_819x_ALPHA = 16,\n\tRT_CID_819x_Sitecom = 17,\n\tRT_CID_CCX = 18, /* It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17. */\n\tRT_CID_819X_LENOVO = 19,\n\tRT_CID_819x_QMI = 20,\n\tRT_CID_819x_Edimax_Belkin = 21,\n\tRT_CID_819x_Sercomm_Belkin = 22,\n\tRT_CID_819x_CAMEO1 = 23,\n\tRT_CID_819x_MSI = 24,\n\tRT_CID_819X_ACER = 25,\n\tRT_CID_819x_AzWave_ASUS = 26,\n\tRT_CID_819x_AzWave = 27, /* For AzWave in PCIe, The ID is AzWave use and not only Asus */\n\tRT_CID_819x_HP = 28,\n\tRT_CID_819x_WNC_COREGA = 29,\n\tRT_CID_819x_Arcadyan_Belkin = 30,\n\tRT_CID_819x_SAMSUNG = 31,\n\tRT_CID_819x_CLEVO = 32,\n\tRT_CID_819x_DELL = 33,\n\tRT_CID_819x_PRONETS = 34,\n\tRT_CID_819x_Edimax_ASUS = 35,\n\tRT_CID_NETGEAR = 36,\n\tRT_CID_PLANEX = 37,\n\tRT_CID_CC_C = 38,\n\tRT_CID_819x_Xavi = 39,\n\tRT_CID_LENOVO_CHINA = 40,\n\tRT_CID_INTEL_CHINA = 41,\n\tRT_CID_TPLINK_HPWR = 42,\n\tRT_CID_819x_Sercomm_Netgear = 43,\n\tRT_CID_819x_ALPHA_Dlink = 44,/* add by ylb 20121012 for customer led for alpha */\n\tRT_CID_WNC_NEC = 45,/* add by page for NEC */\n\tRT_CID_DNI_BUFFALO = 46,/* add by page for NEC */\n} RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;\n\nextern void eeprom_write16(_adapter *padapter, u16 reg, u16 data);\nextern u16 eeprom_read16(_adapter *padapter, u16 reg);\nextern void read_eeprom_content(_adapter *padapter);\nextern void eeprom_read_sz(_adapter *padapter, u16 reg, u8 *data, u32 sz);\n\nextern void read_eeprom_content_by_attrib(_adapter\t*padapter);\n\n#ifdef PLATFORM_LINUX\n#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE\nextern int isAdaptorInfoFileValid(void);\nextern int storeAdaptorInfoFile(char *path, u8 *efuse_data);\nextern int retriveAdaptorInfoFile(char *path, u8 *efuse_data);\n#endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */\n#endif /* PLATFORM_LINUX */\n\n#endif /* __RTL871X_EEPROM_H__ */\n"
  },
  {
    "path": "include/rtw_efuse.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_EFUSE_H__\n#define __RTW_EFUSE_H__\n\n\n#define\tEFUSE_ERROE_HANDLE\t\t1\n\n#define\tPG_STATE_HEADER\t\t0x01\n#define\tPG_STATE_WORD_0\t\t0x02\n#define\tPG_STATE_WORD_1\t\t0x04\n#define\tPG_STATE_WORD_2\t\t0x08\n#define\tPG_STATE_WORD_3\t\t0x10\n#define\tPG_STATE_DATA\t\t\t0x20\n\n#define\tPG_SWBYTE_H\t\t\t0x01\n#define\tPG_SWBYTE_L\t\t\t0x02\n\n#define\tPGPKT_DATA_SIZE\t\t8\n\n#define\tEFUSE_WIFI\t\t\t\t0\n#define\tEFUSE_BT\t\t\t\t1\n\nenum _EFUSE_DEF_TYPE {\n\tTYPE_EFUSE_MAX_SECTION\t\t\t\t= 0,\n\tTYPE_EFUSE_REAL_CONTENT_LEN\t\t\t= 1,\n\tTYPE_AVAILABLE_EFUSE_BYTES_BANK\t\t= 2,\n\tTYPE_AVAILABLE_EFUSE_BYTES_TOTAL\t= 3,\n\tTYPE_EFUSE_MAP_LEN\t\t\t\t\t= 4,\n\tTYPE_EFUSE_PROTECT_BYTES_BANK\t\t= 5,\n\tTYPE_EFUSE_CONTENT_LEN_BANK\t\t\t= 6,\n};\n\n#define\t\tEFUSE_MAX_MAP_LEN\t\t1024\n\n#define\t\tEFUSE_MAX_HW_SIZE\t\t1024\n#define\t\tEFUSE_MAX_SECTION_BASE\t16\n#define\t\tEFUSE_MAX_SECTION_NUM\t128\n#define\t\tEFUSE_MAX_BANK_SIZE\t\t512\n\n/*RTL8822B 8821C BT EFUSE Define 1 BANK 128 size logical map 1024*/\n#ifdef RTW_HALMAC\n#define BANK_NUM\t\t1\n#define EFUSE_BT_REAL_BANK_CONTENT_LEN\t128\n#define EFUSE_BT_REAL_CONTENT_LEN\t\t(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)\n#define EFUSE_BT_MAP_LEN\t\t\t\t1024\t/* 1k bytes */\n#define EFUSE_BT_MAX_SECTION\t\t\t(EFUSE_BT_MAP_LEN / 8)\n#ifdef CONFIG_RTL8822C\n#define EFUSE_PROTECT_BYTES_BANK\t\t54\n#else\n#define EFUSE_PROTECT_BYTES_BANK\t\t16\n#endif\n#define AVAILABLE_EFUSE_ADDR(addr)\t(addr < EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK)\n#endif\n\n#define EXT_HEADER(header) ((header & 0x1F) == 0x0F)\n#define ALL_WORDS_DISABLED(wde)\t((wde & 0x0F) == 0x0F)\n#define GET_HDR_OFFSET_2_0(header) ((header & 0xE0) >> 5)\n\n#define\t\tEFUSE_REPEAT_THRESHOLD_\t\t\t3\n\n#define IS_MASKED_MP(ic, txt, offset) (EFUSE_IsAddressMasked_MP_##ic##txt(offset))\n#define IS_MASKED_TC(ic, txt, offset) (EFUSE_IsAddressMasked_TC_##ic##txt(offset))\n#define GET_MASK_ARRAY_LEN_MP(ic, txt) (EFUSE_GetArrayLen_MP_##ic##txt())\n#define GET_MASK_ARRAY_LEN_TC(ic, txt) (EFUSE_GetArrayLen_TC_##ic##txt())\n#define GET_MASK_ARRAY_MP(ic, txt, offset) (EFUSE_GetMaskArray_MP_##ic##txt(offset))\n#define GET_MASK_ARRAY_TC(ic, txt, offset) (EFUSE_GetMaskArray_TC_##ic##txt(offset))\n\n\n#define IS_MASKED(ic, txt, offset) (IS_MASKED_MP(ic, txt, offset))\n#define GET_MASK_ARRAY_LEN(ic, txt) (GET_MASK_ARRAY_LEN_MP(ic, txt))\n#define GET_MASK_ARRAY(ic, txt, out) do { GET_MASK_ARRAY_MP(ic, txt, out); } while (0)\n\n#define IS_BT_MASKED_MP(ic, txt, offset) (EFUSE_IsBTAddressMasked_MP_##ic##txt(offset))\n#define GET_BT_MASK_ARRAY_LEN_MP(ic, txt) (EFUSE_GetBTArrayLen_MP_##ic##txt())\n#define GET_BT_MASK_ARRAY_LEN_TC(ic, txt) (EFUSE_GetBTArrayLen_TC_##ic##txt())\n#define GET_BT_MASK_ARRAY_MP(ic, txt, offset) (EFUSE_GetBTMaskArray_MP_##ic##txt(offset))\n\n#define IS_BT_MASKED(ic, txt, offset) (IS_BT_MASKED_MP(ic,txt, offset))\n#define GET_BT_MASK_ARRAY(ic, txt, out) do { GET_BT_MASK_ARRAY_MP(ic,txt, out); } while(0)\n#define GET_BT_MASK_ARRAY_LEN(ic, txt) (GET_BT_MASK_ARRAY_LEN_MP(ic,txt))\n\n/* *********************************************\n *\tThe following is for BT Efuse definition\n * ********************************************* */\n#define\t\tEFUSE_BT_MAX_MAP_LEN\t\t1024\n#define\t\tEFUSE_MAX_BANK\t\t\t4\n#define\t\tEFUSE_MAX_BT_BANK\t\t(EFUSE_MAX_BANK-1)\n/* *********************************************\n *--------------------------Define Parameters-------------------------------*/\n#define\t\tEFUSE_MAX_WORD_UNIT\t\t\t4\n\n/*------------------------------Define structure----------------------------*/\ntypedef struct PG_PKT_STRUCT_A {\n\tu8 offset;\n\tu8 word_en;\n\tu8 data[8];\n\tu8 word_cnts;\n} PGPKT_STRUCT, *PPGPKT_STRUCT;\n\ntypedef enum {\n\tERR_SUCCESS = 0,\n\tERR_DRIVER_FAILURE,\n\tERR_IO_FAILURE,\n\tERR_WI_TIMEOUT,\n\tERR_WI_BUSY,\n\tERR_BAD_FORMAT,\n\tERR_INVALID_DATA,\n\tERR_NOT_ENOUGH_SPACE,\n\tERR_WRITE_PROTECT,\n\tERR_READ_BACK_FAIL,\n\tERR_OUT_OF_RANGE\n} ERROR_CODE;\n\n/*------------------------------Define structure----------------------------*/\ntypedef struct _EFUSE_HAL {\n\tu8\tfakeEfuseBank;\n\tu32\tfakeEfuseUsedBytes;\n\tu8\tfakeEfuseContent[EFUSE_MAX_HW_SIZE];\n\tu8\tfakeEfuseInitMap[EFUSE_MAX_MAP_LEN];\n\tu8\tfakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN];\n\tu32\tEfuseUsedBytes;\n\tu8\tEfuseUsedPercentage;\n\n\tu16\tBTEfuseUsedBytes;\n\tu8\tBTEfuseUsedPercentage;\n\tu8\tBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];\n\tu8\tBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN];\n\tu8\tBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN];\n\n\tu16\tfakeBTEfuseUsedBytes;\n\tu8\tfakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];\n\tu8\tfakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN];\n\tu8\tfakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN];\n\n\t/* EFUSE Configuration, initialized in HAL_CmnInitPGData(). */\n\tconst u16  MaxSecNum_WiFi;\n\tconst u16  MaxSecNum_BT;\n\tconst u16  WordUnit;\n\tconst u16  PhysicalLen_WiFi;\n\tconst u16  PhysicalLen_BT;\n\tconst u16  LogicalLen_WiFi;\n\tconst u16  LogicalLen_BT;\n\tconst u16  BankSize;\n\tconst u16  TotalBankNum;\n\tconst u16  BankNum_WiFi;\n\tconst u16  BankNum_BT;\n\tconst u16  OOBProtectBytes;\n\tconst u16  ProtectBytes;\n\tconst u16  BankAvailBytes;\n\tconst u16  TotalAvailBytes_WiFi;\n\tconst u16  TotalAvailBytes_BT;\n\tconst u16  HeaderRetry;\n\tconst u16  DataRetry;\n\n\tERROR_CODE\t  Status;\n\n} EFUSE_HAL, *PEFUSE_HAL;\n\nextern u8 maskfileBuffer[64];\nextern u8 btmaskfileBuffer[64];\n\n/*------------------------Export global variable----------------------------*/\nextern u8 fakeEfuseBank;\nextern u32 fakeEfuseUsedBytes;\nextern u8 fakeEfuseContent[];\nextern u8 fakeEfuseInitMap[];\nextern u8 fakeEfuseModifiedMap[];\n\nextern u32 BTEfuseUsedBytes;\nextern u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];\nextern u8 BTEfuseInitMap[];\nextern u8 BTEfuseModifiedMap[];\n\nextern u32 fakeBTEfuseUsedBytes;\nextern u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];\nextern u8 fakeBTEfuseInitMap[];\nextern u8 fakeBTEfuseModifiedMap[];\n/*------------------------Export global variable----------------------------*/\n#define\t\tMAX_SEGMENT_SIZE\t\t\t200\n#define\t\tMAX_SEGMENT_NUM\t\t\t200\n#define\t\tMAX_BUF_SIZE\t\t\t\t(MAX_SEGMENT_SIZE*MAX_SEGMENT_NUM)\n#define\t\tTMP_BUF_SIZE\t\t\t\t100\n#define\t\trtprintf\t\t\t\t\tdcmd_Store_Return_Buf\n\nu8\tefuse_bt_GetCurrentSize(PADAPTER padapter, u16 *size);\nu16\tefuse_bt_GetMaxSize(PADAPTER padapter);\nu16 efuse_GetavailableSize(PADAPTER adapter);\n\nu8\tefuse_GetCurrentSize(PADAPTER padapter, u16 *size);\nu16\tefuse_GetMaxSize(PADAPTER padapter);\nu8\trtw_efuse_access(PADAPTER padapter, u8 bRead, u16 start_addr, u16 cnts, u8 *data);\nu8\trtw_efuse_bt_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data);\n\nu8\trtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);\nu8\trtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);\nu8\trtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);\nu8\trtw_BT_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);\nu8\trtw_BT_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);\n\nu16\tEfuse_GetCurrentSize(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest);\nu8\tEfuse_CalculateWordCnts(u8 word_en);\nvoid\tReadEFuseByte(PADAPTER Adapter, u16 _offset, u8 *pbuf, BOOLEAN bPseudoTest) ;\nvoid\tEFUSE_GetEfuseDefinition(PADAPTER pAdapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest);\nu8\tefuse_OneByteRead(PADAPTER pAdapter, u16 addr, u8 *data, BOOLEAN\t bPseudoTest);\n#define efuse_onebyte_read(adapter, addr, data, pseudo_test) efuse_OneByteRead((adapter), (addr), (data), (pseudo_test))\n\nu8\tefuse_OneByteWrite(PADAPTER pAdapter, u16 addr, u8 data, BOOLEAN\t bPseudoTest);\n\nvoid\tBTEfuse_PowerSwitch(PADAPTER pAdapter, u8\tbWrite, u8\t PwrState);\nvoid\tEfuse_PowerSwitch(PADAPTER pAdapter, u8\tbWrite, u8\t PwrState);\nint\tEfuse_PgPacketRead(PADAPTER pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);\nint\tEfuse_PgPacketWrite(PADAPTER pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);\nvoid\tefuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata);\nu8\tEfuse_WordEnableDataWrite(PADAPTER pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);\nvoid\tEFUSE_ShadowMapUpdate(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest);\nvoid\tEFUSE_ShadowRead(PADAPTER pAdapter, u8 Type, u16 Offset, u32 *Value);\n#define efuse_logical_map_read(adapter, type, offset, value) EFUSE_ShadowRead((adapter), (type), (offset), (value))\n\nBOOLEAN rtw_file_efuse_IsMasked(PADAPTER pAdapter, u16 Offset, u8 *maskbuf);\nBOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset);\n\nvoid\thal_ReadEFuse_BT_logic_map(\n\tPADAPTER\tpadapter,\n\tu16\t\t\t_offset,\n\tu16\t\t\t_size_byte,\n\tu8\t\t\t*pbuf\n);\nu8\tEfusePgPacketWrite_BT(\n\tPADAPTER\tpAdapter,\n\tu8\t\t\toffset,\n\tu8\t\t\tword_en,\n\tu8\t\t\t*pData,\n\tu8\t\t\tbPseudoTest);\n\nu16 rtw_get_bt_efuse_mask_arraylen(PADAPTER pAdapter);\nvoid rtw_bt_efuse_mask_array(PADAPTER pAdapter, u8 *pArray);\nu16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter);\nvoid rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray);\nvoid rtw_efuse_analyze(PADAPTER\tpadapter, u8 Type, u8 Fake);\n\n#define MAC_HIDDEN_MAX_BW_NUM 8\nextern const u8 _mac_hidden_max_bw_to_hal_bw_cap[];\n#define mac_hidden_max_bw_to_hal_bw_cap(max_bw) (((max_bw) >= MAC_HIDDEN_MAX_BW_NUM) ? 0 : _mac_hidden_max_bw_to_hal_bw_cap[(max_bw)])\n\n#define MAC_HIDDEN_PROTOCOL_NUM 4\nextern const u8 _mac_hidden_proto_to_hal_proto_cap[];\n#define mac_hidden_proto_to_hal_proto_cap(proto) (((proto) >= MAC_HIDDEN_PROTOCOL_NUM) ? 0 : _mac_hidden_proto_to_hal_proto_cap[(proto)])\n\nu8 mac_hidden_wl_func_to_hal_wl_func(u8 func);\n\n#ifdef PLATFORM_LINUX\nu8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepatch, u8 *buf, u32 len);\n#ifdef CONFIG_EFUSE_CONFIG_FILE\nu32 rtw_read_efuse_from_file(const char *path, u8 *buf, int map_size);\nu32 rtw_read_macaddr_from_file(const char *path, u8 *buf);\n#endif /* CONFIG_EFUSE_CONFIG_FILE */\n#endif /* PLATFORM_LINUX */\n\n#endif\n"
  },
  {
    "path": "include/rtw_event.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTW_EVENT_H_\n#define _RTW_EVENT_H_\n\n#ifdef CONFIG_H2CLBK\n\t#include <h2clbk.h>\n#endif\n\n/*\nUsed to report a bss has been scanned\n\n*/\nstruct survey_event\t{\n\tWLAN_BSSID_EX bss;\n};\n\n/*\nUsed to report that the requested site survey has been done.\n\nbss_cnt indicates the number of bss that has been reported.\n\n\n*/\nstruct surveydone_event {\n\tunsigned int\tbss_cnt;\n\n};\n\n/*\nUsed to report the link result of joinning the given bss\n\n\njoin_res:\n-1: authentication fail\n-2: association fail\n> 0: TID\n\n*/\nstruct joinbss_event {\n\tstruct\twlan_network\tnetwork;\n};\n\n/*\nUsed to report a given STA has joinned the created BSS.\nIt is used in AP/Ad-HoC(M) mode.\n\n\n*/\nstruct stassoc_event {\n\tunsigned char macaddr[6];\n};\n\nstruct stadel_event {\n\tunsigned char macaddr[6];\n\tunsigned char rsvd[2]; /* for reason */\n\tunsigned char locally_generated;\n\tint mac_id;\n};\n\nstruct addba_event {\n\tunsigned int tid;\n};\n\nstruct wmm_event {\n\tunsigned char wmm;\n};\n\n#ifdef CONFIG_H2CLBK\nstruct c2hlbk_event {\n\tunsigned char mac[6];\n\tunsigned short\ts0;\n\tunsigned short\ts1;\n\tunsigned int\tw0;\n\tunsigned char\tb0;\n\tunsigned short  s2;\n\tunsigned char\tb1;\n\tunsigned int\tw1;\n};\n#endif/* CONFIG_H2CLBK */\n\n#define GEN_EVT_CODE(event)\tevent ## _EVT_\n\n\n\nstruct fwevent {\n\tu32\tparmsize;\n\tvoid (*event_callback)(_adapter *dev, u8 *pbuf);\n};\n\n\n#define C2HEVENT_SZ\t\t\t32\n\nstruct event_node {\n\tunsigned char *node;\n\tunsigned char evt_code;\n\tunsigned short evt_sz;\n\tvolatile int\t*caller_ff_tail;\n\tint\tcaller_ff_sz;\n};\n\nstruct c2hevent_queue {\n\tvolatile int\thead;\n\tvolatile int\ttail;\n\tstruct\tevent_node\tnodes[C2HEVENT_SZ];\n\tunsigned char\tseq;\n};\n\n#define NETWORK_QUEUE_SZ\t4\n\nstruct network_queue {\n\tvolatile int\thead;\n\tvolatile int\ttail;\n\tWLAN_BSSID_EX networks[NETWORK_QUEUE_SZ];\n};\n\n\n#endif /* _WLANEVENT_H_ */\n"
  },
  {
    "path": "include/rtw_ht.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTW_HT_H_\n#define _RTW_HT_H_\n\n#define HT_CAP_IE_LEN 26\n#define HT_OP_IE_LEN 22\n\nstruct ht_priv {\n\tu8\tht_option;\n\tu8\tampdu_enable;/* for enable Tx A-MPDU */\n\tu8\ttx_amsdu_enable;/* for enable Tx A-MSDU */\n\tu8\tbss_coexist;/* for 20/40 Bss coexist */\n\n\t/* u8\tbaddbareq_issued[16]; */\n\tu32\ttx_amsdu_maxlen; /* 1: 8k, 0:4k ; default:8k, for tx */\n\tu32\trx_ampdu_maxlen; /* for rx reordering ctrl win_sz, updated when join_callback. */\n\n\tu8\trx_ampdu_min_spacing;\n\n\tu8\tch_offset;/* PRIME_CHNL_OFFSET */\n\tu8\tsgi_20m;\n\tu8\tsgi_40m;\n\n\t/* for processing Tx A-MPDU */\n\tu8\tagg_enable_bitmap;\n\t/* u8\tADDBA_retry_count; */\n\tu8\tcandidate_tid_bitmap;\n\n\tu8\tldpc_cap;\n\tu8\tstbc_cap;\n\tu8\tbeamform_cap;\n\tu8\tsmps_cap; /*spatial multiplexing power save mode. 0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/\n\n\tu8 op_present:1; /* ht_op is present */\n\n\tstruct rtw_ieee80211_ht_cap ht_cap;\n\tu8 ht_op[HT_OP_IE_LEN];\n\n};\n\n#ifdef ROKU_PRIVATE\nstruct ht_priv_infra_ap {\n\n\t/*Infra mode, only store AP's info , not intersection of STA and AP*/\n\tu8\tchannel_width_infra_ap;\n\tu8\tsgi_20m_infra_ap;\n\tu8\tsgi_40m_infra_ap;\n\tu8\tldpc_cap_infra_ap;\n\tu8\tstbc_cap_infra_ap;\n\tu8\tMCS_set_infra_ap[16];\n\tu8\tRx_ss_infra_ap;\n\tu16\trx_highest_data_rate_infra_ap;\n};\n#endif /* ROKU_PRIVATE */\n\ntypedef enum AGGRE_SIZE {\n\tHT_AGG_SIZE_8K = 0,\n\tHT_AGG_SIZE_16K = 1,\n\tHT_AGG_SIZE_32K = 2,\n\tHT_AGG_SIZE_64K = 3,\n\tVHT_AGG_SIZE_128K = 4,\n\tVHT_AGG_SIZE_256K = 5,\n\tVHT_AGG_SIZE_512K = 6,\n\tVHT_AGG_SIZE_1024K = 7,\n} AGGRE_SIZE_E, *PAGGRE_SIZE_E;\n\n#define\tLDPC_HT_ENABLE_RX\t\t\tBIT0\n#define\tLDPC_HT_ENABLE_TX\t\t\tBIT1\n#define\tLDPC_HT_TEST_TX_ENABLE\t\tBIT2\n#define\tLDPC_HT_CAP_TX\t\t\t\tBIT3\n\n#define\tSTBC_HT_ENABLE_RX\t\t\tBIT0\n#define\tSTBC_HT_ENABLE_TX\t\t\tBIT1\n#define\tSTBC_HT_TEST_TX_ENABLE\t\tBIT2\n#define\tSTBC_HT_CAP_TX\t\t\t\tBIT3\n\n/* ------------------------------------------------------------\n * The HT Control field\n * ------------------------------------------------------------ */\n#define SET_HT_CTRL_CSI_STEERING(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+2, 6, 2, _val)\n#define SET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart, _val)\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+3, 0, 1, _val)\n#define GET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+3, 0, 1)\n\n/* 20/40 BSS Coexist */\n#define SET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart, _val)\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 1, _val)\n#define GET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 1)\n\n/* HT Capabilities Info field */\n#define HT_CAP_ELE_CAP_INFO(_pEleStart)\t\t\t\t\t((u8 *)(_pEleStart))\n#define GET_HT_CAP_ELE_LDPC_CAP(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 1)\n#define GET_HT_CAP_ELE_CHL_WIDTH(_pEleStart)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 1, 1)\n#define GET_HT_CAP_ELE_SM_PS(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 2, 2)\n#define GET_HT_CAP_ELE_GREENFIELD(_pEleStart)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 4, 1)\n#define GET_HT_CAP_ELE_SHORT_GI20M(_pEleStart)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 5, 1)\n#define GET_HT_CAP_ELE_SHORT_GI40M(_pEleStart)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 6, 1)\n#define GET_HT_CAP_ELE_TX_STBC(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 7, 1)\n#define GET_HT_CAP_ELE_RX_STBC(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 0, 2)\n#define GET_HT_CAP_ELE_DELAYED_BA(_pEleStart)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 2, 1)\n#define GET_HT_CAP_ELE_MAX_AMSDU_LENGTH(_pEleStart)\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 3, 1)\n#define GET_HT_CAP_ELE_DSSS_CCK_40M(_pEleStart)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 4, 1)\n#define GET_HT_CAP_ELE_FORTY_INTOLERANT(_pEleStart)\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 6, 1)\n#define GET_HT_CAP_ELE_LSIG_TXOP_PROTECT(_pEleStart)\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 7, 1)\n\n#define SET_HT_CAP_ELE_LDPC_CAP(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 1, _val)\n#define SET_HT_CAP_ELE_CHL_WIDTH(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 1, 1, _val)\n#define SET_HT_CAP_ELE_SM_PS(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 2, 2, _val)\n#define SET_HT_CAP_ELE_GREENFIELD(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 4, 1, _val)\n#define SET_HT_CAP_ELE_SHORT_GI20M(_pEleStart, _val)\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 5, 1, _val)\n#define SET_HT_CAP_ELE_SHORT_GI40M(_pEleStart, _val)\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 6, 1, _val)\n#define SET_HT_CAP_ELE_TX_STBC(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 7, 1, _val)\n#define SET_HT_CAP_ELE_RX_STBC(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2, _val)\n#define SET_HT_CAP_ELE_DELAYED_BA(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1, _val)\n#define SET_HT_CAP_ELE_MAX_AMSDU_LENGTH(_pEleStart, _val)\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1, _val)\n#define SET_HT_CAP_ELE_DSSS_CCK_40M(_pEleStart, _val)\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 4, 1, _val)\n#define SET_HT_CAP_ELE_FORTY_INTOLERANT(_pEleStart, _val)\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 6, 1, _val)\n#define SET_HT_CAP_ELE_LSIG_TXOP_PROTECT(_pEleStart, _val)\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 7, 1, _val)\n\n/* A-MPDU Parameters field */\n#define HT_CAP_ELE_AMPDU_PARA(_pEleStart)\t\t\t\t(((u8 *)(_pEleStart))+2)\n#define GET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(_pEleStart)\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+2, 0, 2)\n#define GET_HT_CAP_ELE_MIN_MPDU_S_SPACE(_pEleStart)\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+2, 2, 3)\n\n#define HT_AMPDU_PARA_FMT \"%02x \" \\\n\t\"MAX AMPDU len:%u bytes, MIN MPDU Start Spacing:%u\"\n\n#define HT_AMPDU_PARA_ARG(x) \\\n\t*((u8 *)(x)) \\\n\t, (1 << (13+GET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(((u8 *)x)-2)))-1 \\\n\t, GET_HT_CAP_ELE_MIN_MPDU_S_SPACE(((u8 *)x)-2)\n\n#define SET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(_pEleStart, _val)\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2, _val)\n#define SET_HT_CAP_ELE_MIN_MPDU_S_SPACE(_pEleStart, _val)\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 3, _val)\n\n/* Supported MCS Set field */\n#define HT_CAP_ELE_SUP_MCS_SET(_pEleStart)\t\t\t\t(((u8 *)(_pEleStart))+3)\n#define HT_CAP_ELE_RX_MCS_MAP(_pEleStart)\t\t\t\tHT_CAP_ELE_SUP_MCS_SET(_pEleStart)\n#define GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(_pEleStart)\tLE_BITS_TO_2BYTE(((u8 *)(_pEleStart))+13, 0, 10)\n#define GET_HT_CAP_ELE_TX_MCS_DEF(_pEleStart)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 0, 1)\n#define GET_HT_CAP_ELE_TRX_MCS_NEQ(_pEleStart)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 1, 1)\n#define GET_HT_CAP_ELE_TX_MAX_SS(_pEleStart)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 2, 2)\n#define GET_HT_CAP_ELE_TX_UEQM(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 4, 1)\n\n#define HT_RX_MCS_BMP_FMT \"%02x %02x %02x %02x %02x%02x%02x%02x%02x%02x\"\n#define HT_RX_MCS_BMP_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \\\n\t((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9]\n\n#define HT_SUP_MCS_SET_FMT HT_RX_MCS_BMP_FMT \\\n\t/* \"\\n%02x%02x%02x%02x%02x%02x\" */\\\n\t\" %uMbps %s%s%s\"\n#define HT_SUP_MCS_SET_ARG(x) HT_RX_MCS_BMP_ARG(x) \\\n\t/*,((u8 *)(x))[10], ((u8 *)(x))[11], ((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15] */\\\n\t, GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(((u8 *)x)-3) \\\n\t, GET_HT_CAP_ELE_TX_MCS_DEF(((u8 *)x)-3) ? \"TX_MCS_DEF \" : \"\" \\\n\t, GET_HT_CAP_ELE_TRX_MCS_NEQ(((u8 *)x)-3) ? \"TRX_MCS_NEQ \" : \"\" \\\n\t, GET_HT_CAP_ELE_TX_UEQM(((u8 *)x)-3) ? \"TX_UEQM \" : \"\"\n\n/* TXBF Capabilities */\n#define SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 3, 1, ((u8)_val))\n#define SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 4, 1, ((u8)_val))\n#define SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart, _val)\tSET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 10, 1, ((u8)_val))\n#define SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart, _val)\tSET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 15, 2, ((u8)_val))\n#define SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart, _val)\tSET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 23, 2, ((u8)_val))\n#define SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(_pEleStart, _val)\tSET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 27, 2, ((u8)_val))\n\n\n#define GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart)\t\t\tLE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 10, 1)\n#define GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart)\t\t\tLE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 15, 2)\n#define GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart)\t\tLE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 23, 2)\n#define GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(_pEleStart)\t\tLE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 27, 2)\n\n/* HT Operation element */\n\n#define GET_HT_OP_ELE_PRI_CHL(_pEleStart)\t\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 8)\n#define SET_HT_OP_ELE_PRI_CHL(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 8, _val)\n\n/* HT Operation Info field */\n#define HT_OP_ELE_OP_INFO(_pEleStart)\t\t\t\t\t\t(((u8 *)(_pEleStart)) + 1)\n#define GET_HT_OP_ELE_2ND_CHL_OFFSET(_pEleStart)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2)\n#define GET_HT_OP_ELE_STA_CHL_WIDTH(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1)\n#define GET_HT_OP_ELE_RIFS_MODE(_pEleStart)\t\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1)\n#define GET_HT_OP_ELE_HT_PROTECT(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2)\n#define GET_HT_OP_ELE_NON_GREEN_PRESENT(_pEleStart)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 1)\n#define GET_HT_OP_ELE_OBSS_NON_HT_PRESENT(_pEleStart)\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 4, 1)\n#define GET_HT_OP_ELE_DUAL_BEACON(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 4, 6, 1)\n#define GET_HT_OP_ELE_DUAL_CTS(_pEleStart)\t\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 4, 7, 1)\n#define GET_HT_OP_ELE_STBC_BEACON(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 0, 1)\n#define GET_HT_OP_ELE_LSIG_TXOP_PROTECT(_pEleStart)\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 1, 1)\n#define GET_HT_OP_ELE_PCO_ACTIVE(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 2, 1)\n#define GET_HT_OP_ELE_PCO_PHASE(_pEleStart)\t\t\t\t\tLE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 3, 1)\n\n#define SET_HT_OP_ELE_2ND_CHL_OFFSET(_pEleStart, _val)\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2, _val)\n#define SET_HT_OP_ELE_STA_CHL_WIDTH(_pEleStart, _val)\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1, _val)\n#define SET_HT_OP_ELE_RIFS_MODE(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1, _val)\n#define SET_HT_OP_ELE_HT_PROTECT(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2, _val)\n#define SET_HT_OP_ELE_NON_GREEN_PRESENT(_pEleStart, _val)\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 1, _val)\n#define SET_HT_OP_ELE_OBSS_NON_HT_PRESENT(_pEleStart, _val)\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 4, 1, _val)\n#define SET_HT_OP_ELE_DUAL_BEACON(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 4, 6, 1, _val)\n#define SET_HT_OP_ELE_DUAL_CTS(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 4, 7, 1, _val)\n#define SET_HT_OP_ELE_STBC_BEACON(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 0, 1, _val)\n#define SET_HT_OP_ELE_LSIG_TXOP_PROTECT(_pEleStart, _val)\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 1, 1, _val)\n#define SET_HT_OP_ELE_PCO_ACTIVE(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 2, 1, _val)\n#define SET_HT_OP_ELE_PCO_PHASE(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 3, 1, _val)\n\n#endif /* _RTL871X_HT_H_ */\n"
  },
  {
    "path": "include/rtw_io.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef _RTW_IO_H_\n#define _RTW_IO_H_\n\n#define NUM_IOREQ\t\t8\n\n#ifdef PLATFORM_LINUX\n\t#define MAX_PROT_SZ\t(64-16)\n#endif\n\n#define _IOREADY\t\t\t0\n#define _IO_WAIT_COMPLETE   1\n#define _IO_WAIT_RSP        2\n\n/* IO COMMAND TYPE */\n#define _IOSZ_MASK_\t\t(0x7F)\n#define _IO_WRITE_\t\tBIT(7)\n#define _IO_FIXED_\t\tBIT(8)\n#define _IO_BURST_\t\tBIT(9)\n#define _IO_BYTE_\t\tBIT(10)\n#define _IO_HW_\t\t\tBIT(11)\n#define _IO_WORD_\t\tBIT(12)\n#define _IO_SYNC_\t\tBIT(13)\n#define _IO_CMDMASK_\t(0x1F80)\n\n\n/*\n\tFor prompt mode accessing, caller shall free io_req\n\tOtherwise, io_handler will free io_req\n*/\n\n\n\n/* IO STATUS TYPE */\n#define _IO_ERR_\t\tBIT(2)\n#define _IO_SUCCESS_\tBIT(1)\n#define _IO_DONE_\t\tBIT(0)\n\n\n#define IO_RD32\t\t\t(_IO_SYNC_ | _IO_WORD_)\n#define IO_RD16\t\t\t(_IO_SYNC_ | _IO_HW_)\n#define IO_RD8\t\t\t(_IO_SYNC_ | _IO_BYTE_)\n\n#define IO_RD32_ASYNC\t(_IO_WORD_)\n#define IO_RD16_ASYNC\t(_IO_HW_)\n#define IO_RD8_ASYNC\t(_IO_BYTE_)\n\n#define IO_WR32\t\t\t(_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_)\n#define IO_WR16\t\t\t(_IO_WRITE_ | _IO_SYNC_ | _IO_HW_)\n#define IO_WR8\t\t\t(_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_)\n\n#define IO_WR32_ASYNC\t(_IO_WRITE_ | _IO_WORD_)\n#define IO_WR16_ASYNC\t(_IO_WRITE_ | _IO_HW_)\n#define IO_WR8_ASYNC\t(_IO_WRITE_ | _IO_BYTE_)\n\n/*\n\n\tOnly Sync. burst accessing is provided.\n\n*/\n\n#define IO_WR_BURST(x)\t\t(_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_))\n#define IO_RD_BURST(x)\t\t(_IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_))\n\n\n\n/* below is for the intf_option bit defition... */\n\n#define _INTF_ASYNC_\tBIT(0)\t/* support async io */\n\nstruct intf_priv;\nstruct intf_hdl;\nstruct io_queue;\n\nstruct _io_ops {\n\tu8(*_read8)(struct intf_hdl *pintfhdl, u32 addr);\n\tu16(*_read16)(struct intf_hdl *pintfhdl, u32 addr);\n\tu32(*_read32)(struct intf_hdl *pintfhdl, u32 addr);\n\n\tint (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);\n\tint (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);\n\tint (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);\n\tint (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);\n\n\tint (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);\n\tint (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val);\n\tint (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val);\n\n\tvoid (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);\n\tvoid (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);\n\n\tvoid (*_sync_irp_protocol_rw)(struct io_queue *pio_q);\n\n\tu32(*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);\n\n\tu32(*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);\n\tu32(*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);\n\n\tu32(*_write_scsi)(struct intf_hdl *pintfhdl, u32 cnt, u8 *pmem);\n\n\tvoid (*_read_port_cancel)(struct intf_hdl *pintfhdl);\n\tvoid (*_write_port_cancel)(struct intf_hdl *pintfhdl);\n\n#ifdef CONFIG_SDIO_HCI\n\tu8(*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr);\n#ifdef CONFIG_SDIO_INDIRECT_ACCESS\n\tu8(*_sd_iread8)(struct intf_hdl *pintfhdl, u32 addr);\n\tu16(*_sd_iread16)(struct intf_hdl *pintfhdl, u32 addr);\n\tu32(*_sd_iread32)(struct intf_hdl *pintfhdl, u32 addr);\n\tint (*_sd_iwrite8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);\n\tint (*_sd_iwrite16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);\n\tint (*_sd_iwrite32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);\n#endif /* CONFIG_SDIO_INDIRECT_ACCESS */\n#endif\n\n};\n\nstruct io_req {\n\t_list\tlist;\n\tu32\taddr;\n\tvolatile u32\tval;\n\tu32\tcommand;\n\tu32\tstatus;\n\tu8\t*pbuf;\n\t_sema\tsema;\n\tvoid (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt);\n\tu8 *cnxt;\n};\n\nstruct\tintf_hdl {\n\t_adapter *padapter;\n\tstruct dvobj_priv *pintf_dev;/*\tpointer to &(padapter->dvobjpriv); */\n\tstruct _io_ops\tio_ops;\n};\n\nstruct reg_protocol_rd {\n\n#ifdef CONFIG_LITTLE_ENDIAN\n\n\t/* DW1 */\n\tu32\t\tNumOfTrans:4;\n\tu32\t\tReserved1:4;\n\tu32\t\tReserved2:24;\n\t/* DW2 */\n\tu32\t\tByteCount:7;\n\tu32\t\tWriteEnable:1;\t\t/* 0:read, 1:write */\n\tu32\t\tFixOrContinuous:1;\t/* 0:continuous, 1: Fix */\n\tu32\t\tBurstMode:1;\n\tu32\t\tByte1Access:1;\n\tu32\t\tByte2Access:1;\n\tu32\t\tByte4Access:1;\n\tu32\t\tReserved3:3;\n\tu32\t\tReserved4:16;\n\t/* DW3 */\n\tu32\t\tBusAddress;\n\t/* DW4 */\n\t/* u32\t\tValue; */\n#else\n\n\n\t/* DW1 */\n\tu32 Reserved1:4;\n\tu32 NumOfTrans:4;\n\n\tu32 Reserved2:24;\n\n\t/* DW2 */\n\tu32 WriteEnable:1;\n\tu32 ByteCount:7;\n\n\n\tu32 Reserved3:3;\n\tu32 Byte4Access:1;\n\n\tu32 Byte2Access:1;\n\tu32 Byte1Access:1;\n\tu32 BurstMode:1;\n\tu32 FixOrContinuous:1;\n\n\tu32 Reserved4:16;\n\n\t/* DW3 */\n\tu32\t\tBusAddress;\n\n\t/* DW4 */\n\t/* u32\t\tValue; */\n\n#endif\n\n};\n\n\nstruct reg_protocol_wt {\n\n\n#ifdef CONFIG_LITTLE_ENDIAN\n\n\t/* DW1 */\n\tu32\t\tNumOfTrans:4;\n\tu32\t\tReserved1:4;\n\tu32\t\tReserved2:24;\n\t/* DW2 */\n\tu32\t\tByteCount:7;\n\tu32\t\tWriteEnable:1;\t\t/* 0:read, 1:write */\n\tu32\t\tFixOrContinuous:1;\t/* 0:continuous, 1: Fix */\n\tu32\t\tBurstMode:1;\n\tu32\t\tByte1Access:1;\n\tu32\t\tByte2Access:1;\n\tu32\t\tByte4Access:1;\n\tu32\t\tReserved3:3;\n\tu32\t\tReserved4:16;\n\t/* DW3 */\n\tu32\t\tBusAddress;\n\t/* DW4 */\n\tu32\t\tValue;\n\n#else\n\t/* DW1 */\n\tu32 Reserved1:4;\n\tu32 NumOfTrans:4;\n\n\tu32 Reserved2:24;\n\n\t/* DW2 */\n\tu32 WriteEnable:1;\n\tu32 ByteCount:7;\n\n\tu32 Reserved3:3;\n\tu32 Byte4Access:1;\n\n\tu32 Byte2Access:1;\n\tu32 Byte1Access:1;\n\tu32 BurstMode:1;\n\tu32 FixOrContinuous:1;\n\n\tu32 Reserved4:16;\n\n\t/* DW3 */\n\tu32\t\tBusAddress;\n\n\t/* DW4 */\n\tu32\t\tValue;\n\n#endif\n\n};\n#ifdef CONFIG_PCI_HCI\n#define MAX_CONTINUAL_IO_ERR 4\n#endif\n\n#ifdef CONFIG_USB_HCI\n#define MAX_CONTINUAL_IO_ERR 4\n#endif\n\n#ifdef CONFIG_SDIO_HCI\n#define SD_IO_TRY_CNT (8)\n#define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT\n#endif\n\n#ifdef CONFIG_GSPI_HCI\n#define SD_IO_TRY_CNT (8)\n#define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT\n#endif\n\n\nint rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj);\nvoid rtw_reset_continual_io_error(struct dvobj_priv *dvobj);\n\n/*\nBelow is the data structure used by _io_handler\n\n*/\n\nstruct io_queue {\n\t_lock\tlock;\n\t_list\tfree_ioreqs;\n\t_list\t\tpending;\t\t/* The io_req list that will be served in the single protocol read/write.\t */\n\t_list\t\tprocessing;\n\tu8\t*free_ioreqs_buf; /* 4-byte aligned */\n\tu8\t*pallocated_free_ioreqs_buf;\n\tstruct\tintf_hdl\tintf;\n};\n\nstruct io_priv {\n\n\t_adapter *padapter;\n\n\tstruct intf_hdl intf;\n\n};\n\nextern uint ioreq_flush(_adapter *adapter, struct io_queue *ioqueue);\nextern void sync_ioreq_enqueue(struct io_req *preq, struct io_queue *ioqueue);\nextern uint sync_ioreq_flush(_adapter *adapter, struct io_queue *ioqueue);\n\n\nextern uint free_ioreq(struct io_req *preq, struct io_queue *pio_queue);\nextern struct io_req *alloc_ioreq(struct io_queue *pio_q);\n\nextern uint register_intf_hdl(u8 *dev, struct intf_hdl *pintfhdl);\nextern void unregister_intf_hdl(struct intf_hdl *pintfhdl);\n\nextern void _rtw_attrib_read(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);\nextern void _rtw_attrib_write(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);\n\nextern u8 _rtw_read8(_adapter *adapter, u32 addr);\nextern u16 _rtw_read16(_adapter *adapter, u32 addr);\nextern u32 _rtw_read32(_adapter *adapter, u32 addr);\nextern void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);\nextern void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);\nextern void _rtw_read_port_cancel(_adapter *adapter);\n\n\nextern int _rtw_write8(_adapter *adapter, u32 addr, u8 val);\nextern int _rtw_write16(_adapter *adapter, u32 addr, u16 val);\nextern int _rtw_write32(_adapter *adapter, u32 addr, u32 val);\nextern int _rtw_writeN(_adapter *adapter, u32 addr, u32 length, u8 *pdata);\n\n#ifdef CONFIG_SDIO_HCI\nu8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr);\n#ifdef CONFIG_SDIO_INDIRECT_ACCESS\nu8 _rtw_sd_iread8(_adapter *adapter, u32 addr);\nu16 _rtw_sd_iread16(_adapter *adapter, u32 addr);\nu32 _rtw_sd_iread32(_adapter *adapter, u32 addr);\nint _rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val);\nint _rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val);\nint _rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val);\n#endif /* CONFIG_SDIO_INDIRECT_ACCESS */\n#endif /* CONFIG_SDIO_HCI */\n\nextern int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val);\nextern int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val);\nextern int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val);\n\nextern void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);\nextern u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);\nu32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms);\nextern void _rtw_write_port_cancel(_adapter *adapter);\n\n#ifdef DBG_IO\nu32 match_read_sniff(_adapter *adapter, u32 addr, u16 len, u32 val);\nu32 match_write_sniff(_adapter *adapter, u32 addr, u16 len, u32 val);\nbool match_rf_read_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask);\nbool match_rf_write_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask);\n\nextern u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line);\nextern u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line);\nextern u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line);\n\nextern int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line);\nextern int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line);\nextern int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line);\nextern int dbg_rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *data, const char *caller, const int line);\n\n#ifdef CONFIG_SDIO_HCI\nu8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line);\n#ifdef CONFIG_SDIO_INDIRECT_ACCESS\nu8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line);\nu16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line);\nu32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line);\nint dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line);\nint dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line);\nint dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line);\n#endif /* CONFIG_SDIO_INDIRECT_ACCESS */\n#endif /* CONFIG_SDIO_HCI */\n\n#define rtw_read8(adapter, addr) dbg_rtw_read8((adapter), (addr), __FUNCTION__, __LINE__)\n#define rtw_read16(adapter, addr) dbg_rtw_read16((adapter), (addr), __FUNCTION__, __LINE__)\n#define rtw_read32(adapter, addr) dbg_rtw_read32((adapter), (addr), __FUNCTION__, __LINE__)\n#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem))\n#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem))\n#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter))\n\n#define  rtw_write8(adapter, addr, val) dbg_rtw_write8((adapter), (addr), (val), __FUNCTION__, __LINE__)\n#define  rtw_write16(adapter, addr, val) dbg_rtw_write16((adapter), (addr), (val), __FUNCTION__, __LINE__)\n#define  rtw_write32(adapter, addr, val) dbg_rtw_write32((adapter), (addr), (val), __FUNCTION__, __LINE__)\n#define  rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN((adapter), (addr), (length), (data), __FUNCTION__, __LINE__)\n\n#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val))\n#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val))\n#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val))\n\n#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), addr, cnt, mem)\n#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port(adapter, addr, cnt, mem)\n#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms))\n#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel(adapter)\n\n#ifdef CONFIG_SDIO_HCI\n#define rtw_sd_f0_read8(adapter, addr) dbg_rtw_sd_f0_read8((adapter), (addr), __func__, __LINE__)\n#ifdef CONFIG_SDIO_INDIRECT_ACCESS\n#define rtw_sd_iread8(adapter, addr) dbg_rtw_sd_iread8((adapter), (addr), __func__, __LINE__)\n#define rtw_sd_iread16(adapter, addr) dbg_rtw_sd_iread16((adapter), (addr), __func__, __LINE__)\n#define rtw_sd_iread32(adapter, addr) dbg_rtw_sd_iread32((adapter), (addr), __func__, __LINE__)\n#define rtw_sd_iwrite8(adapter, addr, val) dbg_rtw_sd_iwrite8((adapter), (addr), (val), __func__, __LINE__)\n#define rtw_sd_iwrite16(adapter, addr, val) dbg_rtw_sd_iwrite16((adapter), (addr), (val), __func__, __LINE__)\n#define rtw_sd_iwrite32(adapter, addr, val) dbg_rtw_sd_iwrite32((adapter), (addr), (val), __func__, __LINE__)\n#endif /* CONFIG_SDIO_INDIRECT_ACCESS */\n#endif /* CONFIG_SDIO_HCI */\n\n#else /* DBG_IO */\n#define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr))\n#define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr))\n#define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr))\n#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem))\n#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem))\n#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter))\n\n#define  rtw_write8(adapter, addr, val) _rtw_write8((adapter), (addr), (val))\n#define  rtw_write16(adapter, addr, val) _rtw_write16((adapter), (addr), (val))\n#define  rtw_write32(adapter, addr, val) _rtw_write32((adapter), (addr), (val))\n#define  rtw_writeN(adapter, addr, length, data) _rtw_writeN((adapter), (addr), (length), (data))\n\n#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val))\n#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val))\n#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val))\n\n#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), (addr), (cnt), (mem))\n#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port((adapter), (addr), (cnt), (mem))\n#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms))\n#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel((adapter))\n\n#ifdef CONFIG_SDIO_HCI\n#define rtw_sd_f0_read8(adapter, addr) _rtw_sd_f0_read8((adapter), (addr))\n#ifdef CONFIG_SDIO_INDIRECT_ACCESS\n#define rtw_sd_iread8(adapter, addr) _rtw_sd_iread8((adapter), (addr))\n#define rtw_sd_iread16(adapter, addr) _rtw_sd_iread16((adapter), (addr))\n#define rtw_sd_iread32(adapter, addr) _rtw_sd_iread32((adapter), (addr))\n#define rtw_sd_iwrite8(adapter, addr, val) _rtw_sd_iwrite8((adapter), (addr), (val))\n#define rtw_sd_iwrite16(adapter, addr, val) _rtw_sd_iwrite16((adapter), (addr), (val))\n#define rtw_sd_iwrite32(adapter, addr, val) _rtw_sd_iwrite32((adapter), (addr), (val))\n#endif /* CONFIG_SDIO_INDIRECT_ACCESS */\n#endif /* CONFIG_SDIO_HCI */\n\n#endif /* DBG_IO */\n\nextern void rtw_write_scsi(_adapter *adapter, u32 cnt, u8 *pmem);\n\n/* ioreq */\nextern void ioreq_read8(_adapter *adapter, u32 addr, u8 *pval);\nextern void ioreq_read16(_adapter *adapter, u32 addr, u16 *pval);\nextern void ioreq_read32(_adapter *adapter, u32 addr, u32 *pval);\nextern void ioreq_write8(_adapter *adapter, u32 addr, u8 val);\nextern void ioreq_write16(_adapter *adapter, u32 addr, u16 val);\nextern void ioreq_write32(_adapter *adapter, u32 addr, u32 val);\n\n\nextern uint async_read8(_adapter *adapter, u32 addr, u8 *pbuff,\n\tvoid (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);\nextern uint async_read16(_adapter *adapter, u32 addr,  u8 *pbuff,\n\tvoid (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);\nextern uint async_read32(_adapter *adapter, u32 addr,  u8 *pbuff,\n\tvoid (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);\n\nextern void async_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);\nextern void async_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);\n\nextern void async_write8(_adapter *adapter, u32 addr, u8 val,\n\tvoid (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);\nextern void async_write16(_adapter *adapter, u32 addr, u16 val,\n\tvoid (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);\nextern void async_write32(_adapter *adapter, u32 addr, u32 val,\n\tvoid (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);\n\nextern void async_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);\nextern void async_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);\n\n\nint rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter, struct _io_ops *pops));\n\n\nextern uint alloc_io_queue(_adapter *adapter);\nextern void free_io_queue(_adapter *adapter);\nextern void async_bus_io(struct io_queue *pio_q);\nextern void bus_sync_io(struct io_queue *pio_q);\nextern u32 _ioreq2rwmem(struct io_queue *pio_q);\n\n/*\n#define RTL_R8(reg)\t\trtw_read8(padapter, reg)\n#define RTL_R16(reg)            rtw_read16(padapter, reg)\n#define RTL_R32(reg)            rtw_read32(padapter, reg)\n#define RTL_W8(reg, val8)       rtw_write8(padapter, reg, val8)\n#define RTL_W16(reg, val16)     rtw_write16(padapter, reg, val16)\n#define RTL_W32(reg, val32)     rtw_write32(padapter, reg, val32)\n*/\n\n/*\n#define RTL_W8_ASYNC(reg, val8) rtw_write32_async(padapter, reg, val8)\n#define RTL_W16_ASYNC(reg, val16) rtw_write32_async(padapter, reg, val16)\n#define RTL_W32_ASYNC(reg, val32) rtw_write32_async(padapter, reg, val32)\n\n#define RTL_WRITE_BB(reg, val32)\tphy_SetUsbBBReg(padapter, reg, val32)\n#define RTL_READ_BB(reg)\tphy_QueryUsbBBReg(padapter, reg)\n*/\n\n#define PlatformEFIOWrite1Byte(_a, _b, _c)\t\t\\\n\trtw_write8(_a, _b, _c)\n#define PlatformEFIOWrite2Byte(_a, _b, _c)\t\t\\\n\trtw_write16(_a, _b, _c)\n#define PlatformEFIOWrite4Byte(_a, _b, _c)\t\t\\\n\trtw_write32(_a, _b, _c)\n\n#define PlatformEFIORead1Byte(_a, _b)\t\t\\\n\trtw_read8(_a, _b)\n#define PlatformEFIORead2Byte(_a, _b)\t\t\\\n\trtw_read16(_a, _b)\n#define PlatformEFIORead4Byte(_a, _b)\t\t\\\n\trtw_read32(_a, _b)\n\n#endif /* _RTL8711_IO_H_ */\n"
  },
  {
    "path": "include/rtw_ioctl.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTW_IOCTL_H_\n#define _RTW_IOCTL_H_\n\nenum oid_type {\n\tQUERY_OID,\n\tSET_OID\n};\n\nstruct oid_par_priv {\n\tvoid\t\t*adapter_context;\n\tNDIS_OID\toid;\n\tvoid\t\t*information_buf;\n\tu32\t\tinformation_buf_len;\n\tu32\t\t*bytes_rw;\n\tu32\t\t*bytes_needed;\n\tenum oid_type\ttype_of_oid;\n\tu32\t\tdbg;\n};\n\n#if defined(PLATFORM_LINUX) && defined(CONFIG_WIRELESS_EXT)\nextern struct iw_handler_def  rtw_handlers_def;\n#endif\n\nextern void rtw_request_wps_pbc_event(_adapter *padapter);\n\n#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE\nextern int rtw_vendor_ie_get_raw_data(struct net_device *, u32, char *, u32);\nextern int rtw_vendor_ie_get_data(struct net_device*, int , char*);\nextern int rtw_vendor_ie_get(struct net_device *, struct iw_request_info *, union iwreq_data *, char *);\nextern int rtw_vendor_ie_set(struct net_device*, struct iw_request_info*, union iwreq_data*, char*);\n#endif\n\n#endif /*  #ifndef __INC_CEINFO_ */\n"
  },
  {
    "path": "include/rtw_ioctl_query.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTW_IOCTL_QUERY_H_\n#define _RTW_IOCTL_QUERY_H_\n\n\n#endif\n"
  },
  {
    "path": "include/rtw_ioctl_set.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_IOCTL_SET_H_\n#define __RTW_IOCTL_SET_H_\n\nu8 rtw_set_802_11_authentication_mode(_adapter *pdapter, NDIS_802_11_AUTHENTICATION_MODE authmode);\nu8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid);\nu8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep);\nu8 rtw_set_802_11_disassociate(_adapter *padapter);\nu8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm);\nu8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype);\nu8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid);\nu8 rtw_set_802_11_connect(_adapter *padapter,\n\t\t\t  u8 *bssid, NDIS_802_11_SSID *ssid, u16 ch);\n\nu8 rtw_validate_bssid(u8 *bssid);\nu8 rtw_validate_ssid(NDIS_802_11_SSID *ssid);\n\nu16 rtw_get_cur_max_rate(_adapter *adapter);\nint rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode);\nint rtw_set_channel_plan(_adapter *adapter, u8 channel_plan);\nint rtw_set_country(_adapter *adapter, const char *country_code);\nint rtw_set_band(_adapter *adapter, u8 band);\n\n#endif\n"
  },
  {
    "path": "include/rtw_iol.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_IOL_H_\n#define __RTW_IOL_H_\n\n\nstruct xmit_frame\t*rtw_IOL_accquire_xmit_frame(ADAPTER *adapter);\nint rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len);\nint rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary);\nint rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);\nbool rtw_IOL_applied(ADAPTER *adapter);\nint rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us);\nint rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms);\nint rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame);\n\n\n#ifdef CONFIG_IOL_NEW_GENERATION\n#define IOREG_CMD_END_LEN\t4\n\nstruct ioreg_cfg {\n\tu8\tlength;\n\tu8\tcmd_id;\n\tu16\taddress;\n\tu32\tdata;\n\tu32  mask;\n};\nenum ioreg_cmd {\n\tIOREG_CMD_LLT\t\t\t= 0x01,\n\tIOREG_CMD_REFUSE\t\t= 0x02,\n\tIOREG_CMD_EFUSE_PATH = 0x03,\n\tIOREG_CMD_WB_REG\t\t= 0x04,\n\tIOREG_CMD_WW_REG\t= 0x05,\n\tIOREG_CMD_WD_REG\t= 0x06,\n\tIOREG_CMD_W_RF\t\t= 0x07,\n\tIOREG_CMD_DELAY_US\t= 0x10,\n\tIOREG_CMD_DELAY_MS\t= 0x11,\n\tIOREG_CMD_END\t\t= 0xFF,\n};\nvoid read_efuse_from_txpktbuf(ADAPTER *adapter, int bcnhead, u8 *content, u16 *size);\n\nint _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask);\nint _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask);\nint _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask);\nint _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask);\n#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value, mask) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value), (mask))\n#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value, mask) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), (mask))\n#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value, mask) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), (mask))\n#define rtw_IOL_append_WRF_cmd(xmit_frame, rf_path, addr, value, mask) _rtw_IOL_append_WRF_cmd((xmit_frame), (rf_path), (addr), (value), (mask))\n\nu8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame);\nvoid  rtw_IOL_cmd_buf_dump(ADAPTER *Adapter, int buf_len, u8 *pbuf);\n\n#ifdef CONFIG_IOL_IOREG_CFG_DBG\nstruct cmd_cmp {\n\tu16 addr;\n\tu32 value;\n};\n#endif\n\n#else /* CONFIG_IOL_NEW_GENERATION */\n\ntypedef struct _io_offload_cmd {\n\tu8 rsvd0;\n\tu8 cmd;\n\tu16 address;\n\tu32 value;\n} IO_OFFLOAD_CMD, IOL_CMD;\n\n#define IOL_CMD_LLT\t\t\t0x00\n/* #define IOL_CMD_R_EFUSE\t0x01 */\n#define IOL_CMD_WB_REG\t\t0x02\n#define IOL_CMD_WW_REG\t0x03\n#define IOL_CMD_WD_REG\t\t0x04\n/* #define IOL_CMD_W_RF\t\t0x05 */\n#define IOL_CMD_DELAY_US\t0x80\n#define IOL_CMD_DELAY_MS\t0x81\n/* #define IOL_CMD_DELAY_S\t0x82 */\n#define IOL_CMD_END\t\t\t0x83\n\n/*****************************************************\nCMD\t\t\t\t\tAddress\t\t\tValue\n(B1)\t\t\t\t\t(B2/B3:H/L addr)\t(B4:B7 : MSB:LSB)\n******************************************************\nIOL_CMD_LLT\t\t\t-\t\t\t\tB7: PGBNDY\nIOL_CMD_R_EFUSE\t-\t\t\t\t-\nIOL_CMD_WB_REG\t\t0x0~0xFFFF\t\tB7\nIOL_CMD_WW_REG\t0x0~0xFFFF\t\tB6~B7\nIOL_CMD_WD_REG\t0x0~0xFFFF\t\tB4~B7\nIOL_CMD_W_RF\t\tRF Reg\t\t\tB5~B7\nIOL_CMD_DELAY_US\t-\t\t\t\tB6~B7\nIOL_CMD_DELAY_MS\t-\t\t\t\tB6~B7\nIOL_CMD_DELAY_S\t-\t\t\t\tB6~B7\nIOL_CMD_END\t\t-\t\t\t\t-\n******************************************************/\nint _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value);\nint _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value);\nint _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value);\n\n\nint rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms);\nint rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms);\n\n#ifdef DBG_IO\nint dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line);\nint dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line);\nint dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line);\n#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)\n#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)\n#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)\n#else\n#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value))\n#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value))\n#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value))\n#endif /* DBG_IO */\n#endif /* CONFIG_IOL_NEW_GENERATION */\n\n\n\n#endif /* __RTW_IOL_H_ */\n"
  },
  {
    "path": "include/rtw_mcc.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifdef CONFIG_MCC_MODE\n\n#ifndef _RTW_MCC_H_\n#define _RTW_MCC_H_\n\n#include <drv_types.h> /* PADAPTER */\n\n#define MCC_STATUS_PROCESS_MCC_START_SETTING BIT0\n#define MCC_STATUS_PROCESS_MCC_STOP_SETTING BIT1\n#define MCC_STATUS_NEED_MCC BIT2\n#define MCC_STATUS_DOING_MCC BIT3\n\n\n#define MCC_SWCH_FW_EARLY_TIME 10 /* ms */\n#define MCC_EXPIRE_TIME 50 /* ms */\n#define MCC_TOLERANCE_TIME 2 /* 2*2 = 4s */\n#define MCC_UPDATE_PARAMETER_THRESHOLD 5 /* ms */\n\n#define MCC_ROLE_STA_GC_MGMT_QUEUE_MACID 0\n#define MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID 1\n\n/* Lower for stop, Higher for start */\n#define MCC_SETCMD_STATUS_STOP_DISCONNECT 0x0\n#define MCC_SETCMD_STATUS_STOP_SCAN_START 0x1\n#define MCC_SETCMD_STATUS_START_CONNECT 0x80\n#define MCC_SETCMD_STATUS_START_SCAN_DONE 0x81\n\n/*\n* depenad platform or customer requirement(TP unit:Mbps),\n* must be provided by PM or sales or product document\n* too large value means not to limit tx bytes (current for ap mode)\n* NOTE: following values ref from test results\n*/\n#define MCC_AP_BW20_TARGET_TX_TP (300)\n#define MCC_AP_BW40_TARGET_TX_TP (300)\n#define MCC_AP_BW80_TARGET_TX_TP (300)\n#define MCC_STA_BW20_TARGET_TX_TP (35)\n#define MCC_STA_BW40_TARGET_TX_TP (70)\n#define MCC_STA_BW80_TARGET_TX_TP (140)\n#define MCC_SINGLE_TX_CRITERIA 5 /* Mbps */\n\n#define MAX_MCC_NUM 2\n#define DBG_MCC_REG_NUM 4\n#define DBG_MCC_RF_REG_NUM 1\n\n#define MCC_STOP(adapter) (adapter->mcc_adapterpriv.mcc_tx_stop)\n#define MCC_EN(adapter) (adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc)\n#define adapter_to_mccobjpriv(adapter) (&(adapter_to_dvobj(adapter)->mcc_objpriv))\n#define SET_MCC_EN_FLAG(adapter, flag)\\\n\tdo { \\\n\t\tadapter_to_dvobj(adapter)->mcc_objpriv.en_mcc = (flag); \\\n\t} while (0)\n#define SET_MCC_DURATION(adapter, val)\\\n\tdo { \\\n\t\tadapter_to_dvobj(adapter)->mcc_objpriv.duration = (val); \\\n\t} while (0)\n#define SET_MCC_RUNTIME_DURATION(adapter, flag)\\\n\tdo { \\\n\t\tadapter_to_dvobj(adapter)->mcc_objpriv.enable_runtime_duration = (flag); \\\n\t} while (0)\n\n#define SET_MCC_PHYDM_OFFLOAD(adapter, flag)\\\n\tdo { \\\n\t\tadapter_to_dvobj(adapter)->mcc_objpriv.mcc_phydm_offload = (flag); \\\n\t} while (0)\n\n#ifdef CONFIG_MCC_PHYDM_OFFLOAD\nenum mcc_cfg_phydm_ops {\n\tMCC_CFG_PHYDM_OFFLOAD = 0,\n\tMCC_CFG_PHYDM_RF_CH,\n\tMCC_CFG_PHYDM_ADD_CLIENT,\n\tMCC_CFG_PHYDM_REMOVE_CLIENT,\n\tMCC_CFG_PHYDM_START,\n\tMCC_CFG_PHYDM_STOP,\n\tMCC_CFG_PHYDM_DUMP,\n\tMCC_CFG_PHYDM_MAX,\n};\n#endif\n\nenum rtw_mcc_cmd_id {\n\tMCC_CMD_WK_CID = 0,\n\tMCC_SET_DURATION_WK_CID,\n\tMCC_GET_DBG_REG_WK_CID,\n\t#ifdef CONFIG_MCC_PHYDM_OFFLOAD\n\tMCC_SET_PHYDM_OFFLOAD_WK_CID,\n\t#endif\n};\n\n/* Represent Channel Tx Null setting */\nenum mcc_channel_tx_null {\n\tMCC_ENABLE_TX_NULL = 0,\n\tMCC_DISABLE_TX_NULL = 1,\n};\n\n/* Represent C2H Report setting */\nenum mcc_c2h_report {\n\tMCC_C2H_REPORT_DISABLE = 0,\n\tMCC_C2H_REPORT_FAIL_STATUS = 1,\n\tMCC_C2H_REPORT_ALL_STATUS = 2,\n};\n\n/* Represent Channel Scan */\nenum mcc_channel_scan {\n\tMCC_CHIDX = 0,\n\tMCC_SCANCH_RSVD_LOC = 1,\n};\n\n/* Represent FW status report of channel switch */\nenum mcc_status_rpt {\n\tMCC_RPT_SUCCESS = 0,\n\tMCC_RPT_TXNULL_FAIL = 1,\n\tMCC_RPT_STOPMCC = 2,\n\tMCC_RPT_READY = 3,\n\tMCC_RPT_SWICH_CHANNEL_NOTIFY = 7,\n\tMCC_RPT_UPDATE_NOA_START_TIME = 8,\n\tMCC_RPT_TSF = 9,\n\tMCC_RPT_MAX,\n};\n\nenum mcc_role {\n\tMCC_ROLE_STA = 0,\n\tMCC_ROLE_AP = 1,\n\tMCC_ROLE_GC = 2,\n\tMCC_ROLE_GO = 3,\n\tMCC_ROLE_MAX,\n};\n\nstruct mcc_iqk_backup {\n\tu16 TX_X;\n\tu16 TX_Y;\n\tu16 RX_X;\n\tu16 RX_Y;\n};\n\nenum mcc_duration_setting {\n\tMCC_DURATION_MAPPING = 0,\n\tMCC_DURATION_DIRECET = 1,\n};\n\nenum mcc_sched_mode {\n\tMCC_FAIR_SCHEDULE = 0,\n\tMCC_FAVOR_STA = 1,\n\tMCC_FAVOR_P2P = 2,\n};\n\n/*  mcc data for adapter */\nstruct mcc_adapter_priv {\n\tu8 order;\t\t/* FW document, softap/AP must be 0 */\n\tenum mcc_role role;\t\t\t/* MCC role(AP,STA,GO,GC) */\n\tu8 mcc_duration; /* channel stay period, UNIT:1TU */\n\n\t/* flow control */\n\tu8 mcc_tx_stop;\t\t\t\t/* check if tp stop or not */\n\tu8 mcc_tp_limit;\t\t\t\t/* check if tp limit or not */\n\tu32 mcc_target_tx_bytes_to_port;\t\t/* customer require  */\n\tu32 mcc_tx_bytes_to_port;\t/* already tx to tx fifo (write port) */\n\n\t/* data from kernel to check if enqueue data or netif stop queue */\n\tu32 mcc_tp;\n\tu64 mcc_tx_bytes_from_kernel;\n\tu64 mcc_last_tx_bytes_from_kernel;\n\n\t/* Backup IQK value for MCC */\n\tstruct mcc_iqk_backup mcc_iqk_arr[MAX_RF_PATH];\n\n\t/* mgmt queue macid to avoid RA issue */\n\tu8 mgmt_queue_macid;\n\n\t/* set macid bitmap to let fw know which macid should be tx pause */\n\t/* all interface share total 16 macid */\n\tu16 mcc_macid_bitmap;\n\n\t/* use for NoA start time (unit: mircoseconds) */\n\tu32 noa_start_time;\n\n\tu8 p2p_go_noa_ie[MAX_P2P_IE_LEN];\n\tu32 p2p_go_noa_ie_len;\n\tu64 tsf;\n#ifdef CONFIG_TDLS\n\tu8 backup_tdls_en;\n#endif /* CONFIG_TDLS */\n\n\tu8 null_early;\n\tu8 null_rty_num;\n};\n\nstruct mcc_obj_priv {\n\tu8 en_mcc; /* enable MCC or not */\n\tu8 duration; /* store duration(%) from registry, for primary adapter */\n\tu8 interval;\n\tu8 start_time;\n\tu8 mcc_c2h_status;\n\tu8 cur_mcc_success_cnt; /* used for check mcc switch channel success */\n\tu8 prev_mcc_success_cnt; /* used for check mcc switch channel success */\n\tu8 mcc_tolerance_time; /* used for detect mcc switch channel success */\n\tu8 mcc_loc_rsvd_paga[MAX_MCC_NUM];  /* mcc rsvd page */\n\tu8 mcc_status; /* mcc status stop or start .... */\n\tu8 policy_index;\n\tu8 mcc_stop_threshold;\n\tu8 current_order;\n\tu8 last_tsfdiff;\n\tsystime mcc_launch_time; /* mcc launch time, used for starting detect mcc switch channel success */\n\t_mutex mcc_mutex;\n\t_lock mcc_lock;\n\tPADAPTER iface[MAX_MCC_NUM]; /* by order, use for mcc parameter cmd */\n\tstruct submit_ctx mcc_sctx;\n\tstruct submit_ctx mcc_tsf_req_sctx;\n\t_mutex mcc_tsf_req_mutex;\n\tu8 mcc_tsf_req_sctx_order; /* record current order for mcc_tsf_req_sctx */\n#ifdef CONFIG_MCC_MODE_V2\n\tu8 mcc_iqk_value_rsvd_page[3];\n#endif /* CONFIG_MCC_MODE_V2 */\n\tu8 mcc_pwr_idx_rsvd_page[MAX_MCC_NUM];\n\tu8 enable_runtime_duration;\n\t/* for LG */\n\tu8 mchan_sched_mode;\n\n\t_mutex mcc_dbg_reg_mutex;\n\tu32 dbg_reg[DBG_MCC_REG_NUM];\n\tu32 dbg_reg_val[DBG_MCC_REG_NUM];\n\tu32 dbg_rf_reg[DBG_MCC_RF_REG_NUM];\n\tu32 dbg_rf_reg_val[DBG_MCC_RF_REG_NUM][MAX_RF_PATH];\n\tu8 mcc_phydm_offload;\n};\n\n/* backup IQK val */\nvoid rtw_hal_mcc_restore_iqk_val(PADAPTER padapter);\n\n/* check mcc status */\nu8 rtw_hal_check_mcc_status(PADAPTER padapter, u8 mcc_status);\n\n/* set mcc status */\nvoid rtw_hal_set_mcc_status(PADAPTER padapter, u8 mcc_status);\n\n/* clear mcc status */\nvoid rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status);\n\n/* dl mcc rsvd page */\nu8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index\n\t, u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num);\n\n/* handle C2H */\nvoid rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf);\n\n/* switch channel successfully or not */\nvoid rtw_hal_mcc_sw_status_check(PADAPTER padapter);\n\n/* change some scan flags under site survey */\nu8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset);\n\n/* record data kernel TX to driver to check MCC concurrent TX  */\nvoid rtw_hal_mcc_calc_tx_bytes_from_kernel(PADAPTER padapter, u32 len);\n\n/* record data to port to let driver do flow ctrl  */\nvoid rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len);\n\n/* check stop write port or not  */\nu8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter);\n\nu8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter);\n\nu8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter);\n\nu8 rtw_hal_set_mcc_setting_start_bss_network(PADAPTER padapter, u8 chbw_grouped);\n\nu8 rtw_hal_set_mcc_setting_disconnect(PADAPTER padapter);\n\nu8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter);\n\nu8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset, u8 chbw_allow);\n\nvoid rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj);\n\nvoid update_mcc_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib);\n\nu8 rtw_hal_mcc_link_status_chk(_adapter *padapter, const char *msg);\n\nvoid rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode);\n\nu8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len);\n\nvoid rtw_hal_dump_mcc_policy_table(void *sel);\n\nvoid rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add);\n\nvoid rtw_hal_mcc_process_noa(PADAPTER padapter);\n\nvoid rtw_hal_mcc_parameter_init(PADAPTER padapter);\n\nu8 rtw_mcc_cmd_hdl(PADAPTER adapter, u8 type, const u8 *val);\n\nu8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val);\n#ifdef CONFIG_MCC_PHYDM_OFFLOAD\nu8 rtw_set_mcc_phydm_offload_enable_cmd(PADAPTER adapter, u8 enable, u8 enqueue);\n#endif /* CONFIG_MCC_PHYDM_OFFLOAD */\n#endif /* _RTW_MCC_H_ */\n#endif /* CONFIG_MCC_MODE */\n"
  },
  {
    "path": "include/rtw_mem.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_MEM_H__\n#define __RTW_MEM_H__\n\n#include <drv_conf.h>\n#include <basic_types.h>\n#include <osdep_service.h>\n\n#ifdef CONFIG_PLATFORM_MSTAR_HIGH\n\t#define MAX_RTKM_RECVBUF_SZ (31744) /* 31k */\n#else\n\t#define MAX_RTKM_RECVBUF_SZ (15360) /* 15k */\n#endif /* CONFIG_PLATFORM_MSTAR_HIGH */\n#define MAX_RTKM_NR_PREALLOC_RECV_SKB 16\n\nu16 rtw_rtkm_get_buff_size(void);\nu8 rtw_rtkm_get_nr_recv_skb(void);\nstruct u8 *rtw_alloc_revcbuf_premem(void);\nstruct sk_buff *rtw_alloc_skb_premem(u16 in_size);\nint rtw_free_skb_premem(struct sk_buff *pskb);\n\n\n#endif /* __RTW_MEM_H__ */\n"
  },
  {
    "path": "include/rtw_mi.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_MI_H_\n#define __RTW_MI_H_\n\nvoid rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw);\nu8 rtw_mi_stayin_union_ch_chk(_adapter *adapter);\nu8 rtw_mi_stayin_union_band_chk(_adapter *adapter);\n\nint rtw_mi_get_ch_setting_union_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, u8 *ch, u8 *bw, u8 *offset);\nint rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset);\nint rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset);\n\nstruct mi_state {\n\tu8 sta_num;\t\t\t/* WIFI_STATION_STATE */\n\tu8 ld_sta_num;\t\t/* WIFI_STATION_STATE && _FW_LINKED */\n\tu8 lg_sta_num;\t\t/* WIFI_STATION_STATE && _FW_UNDER_LINKING */\n#ifdef CONFIG_TDLS\n\tu8 ld_tdls_num;\t\t/* adapter.tdlsinfo.link_established */\n#endif\n#ifdef CONFIG_AP_MODE\n\tu8 ap_num;\t\t\t/* WIFI_AP_STATE && _FW_LINKED */\n\tu8 starting_ap_num;\t/*WIFI_FW_AP_STATE*/\n\tu8 ld_ap_num;\t\t/* WIFI_AP_STATE && _FW_LINKED && asoc_sta_count > 2 */\n#endif\n\tu8 adhoc_num;\t\t/* (WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) && _FW_LINKED */\n\tu8 ld_adhoc_num;\t/* (WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) && _FW_LINKED && asoc_sta_count > 2 */\n#ifdef CONFIG_RTW_MESH\n\tu8 mesh_num;\t\t/* WIFI_MESH_STATE &&  _FW_LINKED */\n\tu8 ld_mesh_num;\t\t/* WIFI_MESH_STATE &&  _FW_LINKED && asoc_sta_count > 2 */\n#endif\n\tu8 scan_num;\t\t/* WIFI_SITE_MONITOR */\n\tu8 scan_enter_num;\t/* WIFI_SITE_MONITOR && !SCAN_DISABLE && !SCAN_BACK_OP */\n\tu8 uwps_num;\t\t/* WIFI_UNDER_WPS */\n#ifdef CONFIG_IOCTL_CFG80211\n\t#ifdef CONFIG_P2P\n\tu8 roch_num;\n\t#endif\n\tu8 mgmt_tx_num;\n#endif\n#ifdef CONFIG_P2P\n\tu8 p2p_device_num;\n\tu8 p2p_gc;\n\tu8 p2p_go;\n#endif\n\tu8 union_ch;\n\tu8 union_bw;\n\tu8 union_offset;\n};\n\n#define MSTATE_STA_NUM(_mstate)\t\t\t((_mstate)->sta_num)\n#define MSTATE_STA_LD_NUM(_mstate)\t\t((_mstate)->ld_sta_num)\n#define MSTATE_STA_LG_NUM(_mstate)\t\t((_mstate)->lg_sta_num)\n\n#ifdef CONFIG_TDLS\n#define MSTATE_TDLS_LD_NUM(_mstate)\t\t((_mstate)->ld_tdls_num)\n#else\n#define MSTATE_TDLS_LD_NUM(_mstate)\t\t0\n#endif\n\n#ifdef CONFIG_AP_MODE\n#define MSTATE_AP_NUM(_mstate)\t\t\t((_mstate)->ap_num)\n#define MSTATE_AP_STARTING_NUM(_mstate)\t((_mstate)->starting_ap_num)\n#define MSTATE_AP_LD_NUM(_mstate)\t\t((_mstate)->ld_ap_num)\n#else\n#define MSTATE_AP_NUM(_mstate)\t\t\t0\n#define MSTATE_AP_STARTING_NUM(_mstate) 0\n#define MSTATE_AP_LD_NUM(_mstate)\t\t0\n#endif\n\n#define MSTATE_ADHOC_NUM(_mstate)\t\t((_mstate)->adhoc_num)\n#define MSTATE_ADHOC_LD_NUM(_mstate)\t((_mstate)->ld_adhoc_num)\n\n#ifdef CONFIG_RTW_MESH\n#define MSTATE_MESH_NUM(_mstate)\t\t((_mstate)->mesh_num)\n#define MSTATE_MESH_LD_NUM(_mstate)\t\t((_mstate)->ld_mesh_num)\n#else\n#define MSTATE_MESH_NUM(_mstate)\t\t0\n#define MSTATE_MESH_LD_NUM(_mstate)\t\t0\n#endif\n\n#define MSTATE_SCAN_NUM(_mstate)\t\t((_mstate)->scan_num)\n#define MSTATE_SCAN_ENTER_NUM(_mstate)\t((_mstate)->scan_enter_num)\n#define MSTATE_WPS_NUM(_mstate)\t\t\t((_mstate)->uwps_num)\n\n#if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P)\n#define MSTATE_ROCH_NUM(_mstate)\t\t((_mstate)->roch_num)\n#else\n#define MSTATE_ROCH_NUM(_mstate)\t\t0\n#endif\n\n#ifdef CONFIG_P2P\n#define MSTATE_P2P_DV_NUM(_mstate)\t\t((_mstate)->p2p_device_num)\n#define MSTATE_P2P_GC_NUM(_mstate)\t\t((_mstate)->p2p_gc)\n#define MSTATE_P2P_GO_NUM(_mstate)\t\t((_mstate)->p2p_go)\n#else\n#define MSTATE_P2P_DV_NUM(_mstate)\t\t0\n#define MSTATE_P2P_GC_NUM(_mstate)\t\t0\n#define MSTATE_P2P_GO_NUM(_mstate)\t\t0\n#endif\n\n#if defined(CONFIG_IOCTL_CFG80211)\n#define MSTATE_MGMT_TX_NUM(_mstate)\t\t((_mstate)->mgmt_tx_num)\n#else\n#define MSTATE_MGMT_TX_NUM(_mstate)\t\t0\n#endif\n\n#define MSTATE_U_CH(_mstate)\t\t\t((_mstate)->union_ch)\n#define MSTATE_U_BW(_mstate)\t\t\t((_mstate)->union_bw)\n#define MSTATE_U_OFFSET(_mstate)\t\t((_mstate)->union_offset)\n\n#define rtw_mi_get_union_chan(adapter)\tadapter_to_dvobj(adapter)->iface_state.union_ch\n#define rtw_mi_get_union_bw(adapter)\t\tadapter_to_dvobj(adapter)->iface_state.union_bw\n#define rtw_mi_get_union_offset(adapter)\tadapter_to_dvobj(adapter)->iface_state.union_offset\n\n#define rtw_mi_get_assoced_sta_num(adapter)\tDEV_STA_LD_NUM(adapter_to_dvobj(adapter))\n#define rtw_mi_get_ap_num(adapter)\t\t\tDEV_AP_NUM(adapter_to_dvobj(adapter))\n#define rtw_mi_get_mesh_num(adapter)\t\tDEV_MESH_NUM(adapter_to_dvobj(adapter))\nu8 rtw_mi_get_assoc_if_num(_adapter *adapter);\n\n/* For now, not return union_ch/bw/offset */\nvoid rtw_mi_status_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, struct mi_state *mstate);\nvoid rtw_mi_status(_adapter *adapter, struct mi_state *mstate);\nvoid rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate);\nvoid rtw_mi_status_no_others(_adapter *adapter, struct mi_state *mstate);\n\n/* For now, not handle union_ch/bw/offset */\nvoid rtw_mi_status_merge(struct mi_state *d, struct mi_state *a);\n\nvoid rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state);\n\nu8 rtw_mi_netif_stop_queue(_adapter *padapter);\nu8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter);\n\nu8 rtw_mi_netif_wake_queue(_adapter *padapter);\nu8 rtw_mi_buddy_netif_wake_queue(_adapter *padapter);\n\nu8 rtw_mi_netif_carrier_on(_adapter *padapter);\nu8 rtw_mi_buddy_netif_carrier_on(_adapter *padapter);\nu8 rtw_mi_netif_carrier_off(_adapter *padapter);\nu8 rtw_mi_buddy_netif_carrier_off(_adapter *padapter);\n\nu8 rtw_mi_netif_caroff_qstop(_adapter *padapter);\nu8 rtw_mi_buddy_netif_caroff_qstop(_adapter *padapter);\nu8 rtw_mi_netif_caron_qstart(_adapter *padapter);\nu8 rtw_mi_buddy_netif_caron_qstart(_adapter *padapter);\n\nvoid rtw_mi_scan_abort(_adapter *adapter, bool bwait);\nvoid rtw_mi_buddy_scan_abort(_adapter *adapter, bool bwait);\nu32 rtw_mi_start_drv_threads(_adapter *adapter);\nu32 rtw_mi_buddy_start_drv_threads(_adapter *adapter);\nvoid rtw_mi_stop_drv_threads(_adapter *adapter);\nvoid rtw_mi_buddy_stop_drv_threads(_adapter *adapter);\nvoid rtw_mi_cancel_all_timer(_adapter *adapter);\nvoid rtw_mi_buddy_cancel_all_timer(_adapter *adapter);\nvoid rtw_mi_reset_drv_sw(_adapter *adapter);\nvoid rtw_mi_buddy_reset_drv_sw(_adapter *adapter);\n\nextern void rtw_intf_start(_adapter *adapter);\nextern void rtw_intf_stop(_adapter *adapter);\nvoid rtw_mi_intf_start(_adapter *adapter);\nvoid rtw_mi_buddy_intf_start(_adapter *adapter);\nvoid rtw_mi_intf_stop(_adapter *adapter);\nvoid rtw_mi_buddy_intf_stop(_adapter *adapter);\n\n#ifdef CONFIG_NEW_NETDEV_HDL\nu8 rtw_mi_hal_iface_init(_adapter *padapter);\n#endif\nvoid rtw_mi_suspend_free_assoc_resource(_adapter *adapter);\nvoid rtw_mi_buddy_suspend_free_assoc_resource(_adapter *adapter);\n\n#ifdef CONFIG_SET_SCAN_DENY_TIMER\nvoid rtw_mi_set_scan_deny(_adapter *adapter, u32 ms);\nvoid rtw_mi_buddy_set_scan_deny(_adapter *adapter, u32 ms);\n#else\n#define rtw_mi_set_scan_deny(adapter, ms) do {} while (0)\n#define rtw_mi_buddy_set_scan_deny(adapter, ms) do {} while (0)\n#endif\n\nu8 rtw_mi_is_scan_deny(_adapter *adapter);\nu8 rtw_mi_buddy_is_scan_deny(_adapter *adapter);\n\nvoid rtw_mi_beacon_update(_adapter *padapter);\nvoid rtw_mi_buddy_beacon_update(_adapter *padapter);\n\nvoid rtw_mi_hal_dump_macaddr(_adapter *padapter);\nvoid rtw_mi_buddy_hal_dump_macaddr(_adapter *padapter);\n\n#ifdef CONFIG_PCI_HCI\nvoid rtw_mi_xmit_tasklet_schedule(_adapter *padapter);\nvoid rtw_mi_buddy_xmit_tasklet_schedule(_adapter *padapter);\n#endif\n\nu8 rtw_mi_busy_traffic_check(_adapter *padapter, bool check_sc_interval);\nu8 rtw_mi_buddy_busy_traffic_check(_adapter *padapter, bool check_sc_interval);\n\nu8 rtw_mi_check_mlmeinfo_state(_adapter *padapter, u32 state);\nu8 rtw_mi_buddy_check_mlmeinfo_state(_adapter *padapter, u32 state);\n\nu8 rtw_mi_check_fwstate(_adapter *padapter, sint state);\nu8 rtw_mi_buddy_check_fwstate(_adapter *padapter, sint state);\nenum {\n\tMI_LINKED,\n\tMI_ASSOC,\n\tMI_UNDER_WPS,\n\tMI_AP_MODE,\n\tMI_AP_ASSOC,\n\tMI_ADHOC,\n\tMI_ADHOC_ASSOC,\n\tMI_MESH,\n\tMI_MESH_ASSOC,\n\tMI_STA_NOLINK, /* this is misleading, but not used now */\n\tMI_STA_LINKED,\n\tMI_STA_LINKING,\n};\nu8 rtw_mi_check_status(_adapter *adapter, u8 type);\n\nvoid dump_dvobj_mi_status(void *sel, const char *fun_name, _adapter *adapter);\n#ifdef DBG_IFACE_STATUS\n#define DBG_IFACE_STATUS_DUMP(adapter)\tdump_dvobj_mi_status(RTW_DBGDUMP, __func__, adapter)\n#endif\nvoid dump_mi_status(void *sel, struct dvobj_priv *dvobj);\n\nu8 rtw_mi_traffic_statistics(_adapter *padapter);\nu8 rtw_mi_check_miracast_enabled(_adapter *padapter);\n\n#ifdef CONFIG_XMIT_THREAD_MODE\nu8 rtw_mi_check_pending_xmitbuf(_adapter *padapter);\nu8 rtw_mi_buddy_check_pending_xmitbuf(_adapter *padapter);\n#endif\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n#ifdef CONFIG_RTL8822B\n\t#include <rtl8822b_hal.h>\n#elif defined(CONFIG_RTL8822C)\n\t#include <rtl8822c_hal.h>\n#else\n\textern s32 _dequeue_writeport(PADAPTER padapter);\n#endif\nu8 rtw_mi_dequeue_writeport(_adapter *padapter);\nu8 rtw_mi_buddy_dequeue_writeport(_adapter *padapter);\n#endif\n\nvoid rtw_mi_adapter_reset(_adapter *padapter);\nvoid rtw_mi_buddy_adapter_reset(_adapter *padapter);\n\nu8 rtw_mi_dynamic_check_timer_handlder(_adapter *padapter);\nu8 rtw_mi_buddy_dynamic_check_timer_handlder(_adapter *padapter);\n\nextern void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter);\nu8 rtw_mi_dynamic_chk_wk_hdl(_adapter *padapter);\nu8 rtw_mi_buddy_dynamic_chk_wk_hdl(_adapter *padapter);\n\nu8 rtw_mi_os_xmit_schedule(_adapter *padapter);\nu8 rtw_mi_buddy_os_xmit_schedule(_adapter *padapter);\n\nu8 rtw_mi_report_survey_event(_adapter *padapter, union recv_frame *precv_frame);\nu8 rtw_mi_buddy_report_survey_event(_adapter *padapter, union recv_frame *precv_frame);\n\nextern void sreset_start_adapter(_adapter *padapter);\nextern void sreset_stop_adapter(_adapter *padapter);\nu8 rtw_mi_sreset_adapter_hdl(_adapter *padapter, u8 bstart);\nu8 rtw_mi_buddy_sreset_adapter_hdl(_adapter *padapter, u8 bstart);\n\nu8 rtw_mi_tx_beacon_hdl(_adapter *padapter);\nu8 rtw_mi_buddy_tx_beacon_hdl(_adapter *padapter);\n\nu8 rtw_mi_set_tx_beacon_cmd(_adapter *padapter);\nu8 rtw_mi_buddy_set_tx_beacon_cmd(_adapter *padapter);\n\n#ifdef CONFIG_P2P\nu8 rtw_mi_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state);\nu8 rtw_mi_buddy_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state);\nu8 rtw_mi_stay_in_p2p_mode(_adapter *padapter);\nu8 rtw_mi_buddy_stay_in_p2p_mode(_adapter *padapter);\n#endif\n\n_adapter *rtw_get_iface_by_id(_adapter *padapter, u8 iface_id);\n_adapter *rtw_get_iface_by_macddr(_adapter *padapter, const u8 *mac_addr);\n_adapter *rtw_get_iface_by_hwport(_adapter *padapter, u8 hw_port);\n\nvoid rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvframe, u8 *pphy_status);\n\n#ifdef CONFIG_PCI_HCI\n/*API be create temporary for MI, caller is interrupt-handler, PCIE's interrupt handler cannot apply to multi-AP*/\n_adapter *rtw_mi_get_ap_adapter(_adapter *padapter);\n#endif\n\nu8 rtw_mi_get_ld_sta_ifbmp(_adapter *adapter);\nu8 rtw_mi_get_ap_mesh_ifbmp(_adapter *adapter);\nvoid rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b);\n\n#endif /*__RTW_MI_H_*/\n"
  },
  {
    "path": "include/rtw_mlme.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2019 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_MLME_H_\n#define __RTW_MLME_H_\n\n\n#define\tMAX_BSS_CNT\t128\n/* #define   MAX_JOIN_TIMEOUT\t2000 */\n/* #define   MAX_JOIN_TIMEOUT\t2500 */\n#define   MAX_JOIN_TIMEOUT\t6500\n\n/*\tCommented by Albert 20101105\n *\tIncrease the scanning timeout because of increasing the SURVEY_TO value. */\n\n\n#ifdef PALTFORM_OS_WINCE\n#define\tSCANQUEUE_LIFETIME 12000000 /* unit:us */\n#else\n#define\tSCANQUEUE_LIFETIME 20000 /* 20sec, unit:msec */\n#endif\n\n#define WIFI_NULL_STATE\t\t\t\t\t0x00000000\n#define WIFI_ASOC_STATE\t\t\t\t\t0x00000001 /* Linked */\n#define WIFI_REASOC_STATE\t\t\t\t0x00000002\n#define WIFI_SLEEP_STATE\t\t\t\t0x00000004\n#define WIFI_STATION_STATE\t\t\t\t0x00000008\n#define WIFI_AP_STATE\t\t\t\t\t0x00000010\n#define WIFI_ADHOC_STATE\t\t\t\t0x00000020\n#define WIFI_ADHOC_MASTER_STATE\t\t\t0x00000040\n#define WIFI_UNDER_LINKING\t\t\t\t0x00000080\n#define WIFI_UNDER_WPS\t\t\t\t\t0x00000100\n#define WIFI_MESH_STATE\t\t\t\t\t0x00000200\n#define WIFI_STA_ALIVE_CHK_STATE\t\t0x00000400\n#define WIFI_SITE_MONITOR\t\t\t\t0x00000800 /* under site surveying */\n#define WIFI_WDS\t\t\t\t\t\t0x00001000\n#define WIFI_WDS_RX_BEACON\t\t\t\t0x00002000 /* already rx WDS AP beacon */\n#define WIFI_AUTOCONF\t\t\t\t\t0x00004000\n#define WIFI_AUTOCONF_IND\t\t\t\t0x00008000\n#define WIFI_MP_STATE\t\t\t\t\t0x00010000\n#define WIFI_MP_CTX_BACKGROUND\t\t\t0x00020000 /* in continuous tx background */\n#define WIFI_MP_CTX_ST\t\t\t\t\t0x00040000 /* in continuous tx with single-tone */\n#define WIFI_MP_CTX_BACKGROUND_PENDING\t0x00080000 /* pending in continuous tx background due to out of skb */\n#define WIFI_MP_CTX_CCK_HW\t\t\t\t0x00100000 /* in continuous tx */\n#define WIFI_MP_CTX_CCK_CS\t\t\t\t0x00200000 /* in continuous tx with carrier suppression */\n#define WIFI_MP_LPBK_STATE\t\t\t\t0x00400000\n#define WIFI_OP_CH_SWITCHING\t\t\t0x00800000\n#define WIFI_UNDER_KEY_HANDSHAKE\t0x01000000\n/*#define WIFI_UNDEFINED_STATE\t\t\t0x02000000*/\n/*#define WIFI_UNDEFINED_STATE\t\t\t0x04000000*/\n/*#define WIFI_UNDEFINED_STATE\t\t\t0x08000000*/\n/*#define WIFI_UNDEFINED_STATE\t\t\t0x10000000*/\n/*#define WIFI_UNDEFINED_STATE\t\t\t0x20000000*/\n/*#define WIFI_UNDEFINED_STATE\t\t\t0x40000000*/\n#define WIFI_MONITOR_STATE\t\t\t\t0x80000000\n\n#define MIRACAST_DISABLED\t0\n#define MIRACAST_SOURCE\t\tBIT0\n#define MIRACAST_SINK\t\tBIT1\n\n#define MIRACAST_MODE_REVERSE(mode) \\\n\t((((mode) & MIRACAST_SOURCE) ? MIRACAST_SINK : 0) | (((mode) & MIRACAST_SINK) ? MIRACAST_SOURCE : 0))\n\nbool is_miracast_enabled(_adapter *adapter);\nbool rtw_chk_miracast_mode(_adapter *adapter, u8 mode);\nconst char *get_miracast_mode_str(int mode);\nvoid rtw_wfd_st_switch(struct sta_info *sta, bool on);\n\n#define MLME_STATE(adapter) get_fwstate(&((adapter)->mlmepriv))\n#define CHK_MLME_STATE(adapter, state) check_fwstate(&((adapter)->mlmepriv), (state))\n\n#define MLME_IS_NULL(adapter) CHK_MLME_STATE(adapter, WIFI_NULL_STATE)\n#define MLME_IS_STA(adapter) CHK_MLME_STATE(adapter, WIFI_STATION_STATE)\n#define MLME_IS_AP(adapter) CHK_MLME_STATE(adapter, WIFI_AP_STATE)\n#define MLME_IS_ADHOC(adapter) CHK_MLME_STATE(adapter, WIFI_ADHOC_STATE)\n#define MLME_IS_ADHOC_MASTER(adapter) CHK_MLME_STATE(adapter, WIFI_ADHOC_MASTER_STATE)\n#define MLME_IS_MESH(adapter) CHK_MLME_STATE(adapter, WIFI_MESH_STATE)\n#define MLME_IS_MONITOR(adapter) CHK_MLME_STATE(adapter, WIFI_MONITOR_STATE)\n#define MLME_IS_MP(adapter) CHK_MLME_STATE(adapter, WIFI_MP_STATE)\n#ifdef CONFIG_P2P\n\t#define MLME_IS_PD(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_DEVICE)\n\t#define MLME_IS_GC(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_CLIENT)\n\t#define MLME_IS_GO(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_GO)\n#else /* !CONFIG_P2P */\n\t#define MLME_IS_PD(adapter) 0\n\t#define MLME_IS_GC(adapter) 0\n\t#define MLME_IS_GO(adapter) 0\n#endif /* !CONFIG_P2P */\n\n#define MLME_IS_MSRC(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SOURCE)\n#define MLME_IS_MSINK(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SINK)\n\n#define MLME_IS_SCAN(adapter) CHK_MLME_STATE(adapter, WIFI_SITE_MONITOR)\n#define MLME_IS_LINKING(adapter) CHK_MLME_STATE(adapter, WIFI_UNDER_LINKING)\n#define MLME_IS_ASOC(adapter) CHK_MLME_STATE(adapter, WIFI_ASOC_STATE)\n#define MLME_IS_OPCH_SW(adapter) CHK_MLME_STATE(adapter, WIFI_OP_CH_SWITCHING)\n#define MLME_IS_WPS(adapter) CHK_MLME_STATE(adapter, WIFI_UNDER_WPS)\n\n#if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P)\n#define MLME_IS_ROCH(adapter) (rtw_cfg80211_get_is_roch(adapter) == _TRUE)\n#else\n#define MLME_IS_ROCH(adapter) 0\n#endif\n\n#ifdef CONFIG_IOCTL_CFG80211\n#define MLME_IS_MGMT_TX(adapter) rtw_cfg80211_get_is_mgmt_tx(adapter)\n#else\n#define MLME_IS_MGMT_TX(adapter) 0\n#endif\n\n#define MLME_STATE_FMT \"%s%s%s%s%s%s%s%s%s%s%s%s\"\n#define MLME_STATE_ARG(adapter) \\\n\tMLME_IS_STA((adapter)) ? (MLME_IS_GC((adapter)) ? \" GC\" : \" STA\") : \\\n\tMLME_IS_AP((adapter)) ? (MLME_IS_GO((adapter)) ? \" GO\" : \" AP\") : \\\n\tMLME_IS_ADHOC((adapter)) ? \" ADHOC\" : \\\n\tMLME_IS_ADHOC_MASTER((adapter)) ? \" ADHOC_M\" : \\\n\tMLME_IS_MESH((adapter)) ? \" MESH\" : \\\n\tMLME_IS_MONITOR((adapter)) ? \" MONITOR\" : \\\n\tMLME_IS_MP((adapter)) ? \" MP\" : \"\", \\\n\tMLME_IS_PD((adapter)) ? \" PD\" : \"\", \\\n\tMLME_IS_MSRC((adapter)) ? \" MSRC\" : \"\", \\\n\tMLME_IS_MSINK((adapter)) ? \" MSINK\" : \"\", \\\n\tMLME_IS_SCAN((adapter)) ? \" SCAN\" : \"\", \\\n\tMLME_IS_LINKING((adapter)) ? \" LINKING\" : \"\", \\\n\tMLME_IS_ASOC((adapter)) ? \" ASOC\" : \"\", \\\n\tMLME_IS_OPCH_SW((adapter)) ? \" OPCH_SW\" : \"\", \\\n\tMLME_IS_WPS((adapter)) ? \" WPS\" : \"\", \\\n\tMLME_IS_ROCH((adapter)) ? \" ROCH\" : \"\", \\\n\tMLME_IS_MGMT_TX((adapter)) ? \" MGMT_TX\" : \"\", \\\n\t(MLME_STATE((adapter)) & WIFI_SLEEP_STATE) ? \" SLEEP\" : \"\"\n\nenum {\n\tMLME_ACTION_UNKNOWN,\n\tMLME_ACTION_NONE,\n\tMLME_SCAN_ENABLE, /* WIFI_SITE_MONITOR */\n\tMLME_SCAN_ENTER, /* WIFI_SITE_MONITOR && !SCAN_DISABLE && !SCAN_BACK_OP */\n\tMLME_SCAN_DONE, /*  WIFI_SITE_MONITOR && (SCAN_DISABLE || SCAN_BACK_OP) */\n\tMLME_SCAN_DISABLE, /* WIFI_SITE_MONITOR is going to be cleared */\n\tMLME_STA_CONNECTING,\n\tMLME_STA_CONNECTED,\n\tMLME_STA_DISCONNECTED,\n\tMLME_TDLS_LINKED,\n\tMLME_TDLS_NOLINK,\n\tMLME_AP_STARTED,\n\tMLME_AP_STOPPED,\n\tMLME_ADHOC_STARTED,\n\tMLME_ADHOC_STOPPED,\n\tMLME_MESH_STARTED,\n\tMLME_MESH_STOPPED,\n\tMLME_OPCH_SWITCH,\n};\n\n#define _FW_UNDER_LINKING\tWIFI_UNDER_LINKING\n#define _FW_LINKED\t\t\tWIFI_ASOC_STATE\n#define _FW_UNDER_SURVEY\tWIFI_SITE_MONITOR\n\n\nenum dot11AuthAlgrthmNum {\n\tdot11AuthAlgrthm_Open = 0,\n\tdot11AuthAlgrthm_Shared,\n\tdot11AuthAlgrthm_8021X,\n\tdot11AuthAlgrthm_Auto,\n\tdot11AuthAlgrthm_WAPI,\n\tdot11AuthAlgrthm_MaxNum\n};\n\n/* Scan type including active and passive scan. */\ntypedef enum _RT_SCAN_TYPE {\n\tSCAN_PASSIVE,\n\tSCAN_ACTIVE,\n\tSCAN_MIX,\n} RT_SCAN_TYPE, *PRT_SCAN_TYPE;\n\n#define WIFI_FREQUENCY_BAND_AUTO 0\n#define WIFI_FREQUENCY_BAND_5GHZ 1\n#define WIFI_FREQUENCY_BAND_2GHZ 2\n\n#define rtw_band_valid(band) ((band) <= WIFI_FREQUENCY_BAND_2GHZ)\n\nenum DriverInterface {\n\tDRIVER_WEXT =  1,\n\tDRIVER_CFG80211 = 2\n};\n\nenum SCAN_RESULT_TYPE {\n\tSCAN_RESULT_P2P_ONLY = 0,\t\t/*\tWill return all the P2P devices. */\n\tSCAN_RESULT_ALL = 1,\t\t\t/*\tWill return all the scanned device, include AP. */\n\tSCAN_RESULT_WFD_TYPE = 2\t\t/*\tWill just return the correct WFD device. */\n\t\t\t\t\t\t\t\t\t/*\tIf this device is Miracast sink device, it will just return all the Miracast source devices. */\n};\n\n/*\n\nthere are several \"locks\" in mlme_priv,\nsince mlme_priv is a shared resource between many threads,\nlike ISR/Call-Back functions, the OID handlers, and even timer functions.\n\n\nEach _queue has its own locks, already.\nOther items are protected by mlme_priv.lock.\n\nTo avoid possible dead lock, any thread trying to modifiying mlme_priv\nSHALL not lock up more than one locks at a time!\n\n*/\n\n\n#define traffic_threshold\t10\n#define\ttraffic_scan_period\t500\n\ntypedef struct _RT_LINK_DETECT_T {\n\tu32\t\t\t\tNumTxOkInPeriod;\n\tu32\t\t\t\tNumRxOkInPeriod;\n\tu32\t\t\t\tNumRxUnicastOkInPeriod;\n\tBOOLEAN\t\t\tbBusyTraffic;\n\tBOOLEAN\t\t\tbTxBusyTraffic;\n\tBOOLEAN\t\t\tbRxBusyTraffic;\n\tBOOLEAN\t\t\tbHigherBusyTraffic; /* For interrupt migration purpose. */\n\tBOOLEAN\t\t\tbHigherBusyRxTraffic; /* We may disable Tx interrupt according as Rx traffic. */\n\tBOOLEAN\t\t\tbHigherBusyTxTraffic; /* We may disable Tx interrupt according as Tx traffic. */\n\t/* u8 TrafficBusyState; */\n\tu8 TrafficTransitionCount;\n\tu32 LowPowerTransitionCount;\n} RT_LINK_DETECT_T, *PRT_LINK_DETECT_T;\n\nstruct profile_info {\n\tu8\tssidlen;\n\tu8\tssid[WLAN_SSID_MAXLEN];\n\tu8\tpeermac[ETH_ALEN];\n};\n\nstruct tx_invite_req_info {\n\tu8\t\t\t\t\ttoken;\n\tu8\t\t\t\t\tbenable;\n\tu8\t\t\t\t\tgo_ssid[WLAN_SSID_MAXLEN];\n\tu8\t\t\t\t\tssidlen;\n\tu8\t\t\t\t\tgo_bssid[ETH_ALEN];\n\tu8\t\t\t\t\tpeer_macaddr[ETH_ALEN];\n\tu8\t\t\t\t\toperating_ch;\t/*\tThis information will be set by using the p2p_set op_ch=x */\n\tu8\t\t\t\t\tpeer_ch;\t\t/*\tThe listen channel for peer P2P device */\n\n};\n\nstruct tx_invite_resp_info {\n\tu8\t\t\t\t\ttoken;\t/*\tUsed to record the dialog token of p2p invitation request frame. */\n};\n\n#ifdef CONFIG_WFD\n\nstruct wifi_display_info {\n\tu16\t\t\t\t\t\t\twfd_enable;\t\t\t/*\tEanble/Disable the WFD function. */\n\tu16\t\t\t\t\t\t\tinit_rtsp_ctrlport;\t/* init value of rtsp_ctrlport when WFD enable */\n\tu16\t\t\t\t\t\t\trtsp_ctrlport;\t\t/* TCP port number at which the this WFD device listens for RTSP messages, 0 when WFD disable */\n\tu16\t\t\t\t\t\t\ttdls_rtsp_ctrlport;\t/* rtsp_ctrlport used by tdls, will sync when rtsp_ctrlport is changed by user */\n\tu16\t\t\t\t\t\t\tpeer_rtsp_ctrlport;\t/*\tTCP port number at which the peer WFD device listens for RTSP messages */\n\t\t\t\t\t\t\t\t\t\t\t\t\t/*\tThis filed should be filled when receiving the gropu negotiation request */\n\n\tu8\t\t\t\t\t\t\tpeer_session_avail;\t/*\tWFD session is available or not for the peer wfd device. */\n\t\t\t\t\t\t\t\t\t\t\t\t\t/*\tThis variable will be set when sending the provisioning discovery request to peer WFD device. */\n\t\t\t\t\t\t\t\t\t\t\t\t\t/*\tAnd this variable will be reset when it is read by using the iwpriv p2p_get wfd_sa command. */\n\tu8\t\t\t\t\t\t\tip_address[4];\n\tu8\t\t\t\t\t\t\tpeer_ip_address[4];\n\tu8\t\t\t\t\t\t\twfd_pc;\t\t\t\t/*\tWFD preferred connection */\n\t\t\t\t\t\t\t\t\t\t\t\t\t/*\t0 -> Prefer to use the P2P for WFD connection on peer side. */\n\t\t\t\t\t\t\t\t\t\t\t\t\t/*\t1 -> Prefer to use the TDLS for WFD connection on peer side. */\n\n\tu8\t\t\t\t\t\t\twfd_device_type;\t/*\tWFD Device Type */\n\t\t\t\t\t\t\t\t\t\t\t\t\t/*\t0 -> WFD Source Device */\n\t\t\t\t\t\t\t\t\t\t\t\t\t/*\t1 -> WFD Primary Sink Device */\n\tenum\tSCAN_RESULT_TYPE\tscan_result_type;\t/*\tUsed when P2P is enable. This parameter will impact the scan result. */\n\tu8 op_wfd_mode;\n\tu8 stack_wfd_mode;\n};\n#endif /* CONFIG_WFD */\n\nstruct tx_provdisc_req_info {\n\tu16\t\t\t\t\twps_config_method_request;\t/*\tUsed when sending the provisioning request frame */\n\tu16\t\t\t\t\tpeer_channel_num[2];\t\t/*\tThe channel number which the receiver stands. */\n\tNDIS_802_11_SSID\tssid;\n\tu8\t\t\t\t\tpeerDevAddr[ETH_ALEN];\t\t/*\tPeer device address */\n\tu8\t\t\t\t\tpeerIFAddr[ETH_ALEN];\t\t/*\tPeer interface address */\n\tu8\t\t\t\t\tbenable;\t\t\t\t\t/*\tThis provision discovery request frame is trigger to send or not */\n};\n\nstruct rx_provdisc_req_info {\t/* When peer device issue prov_disc_req first, we should store the following informations */\n\tu8\t\t\t\t\tpeerDevAddr[ETH_ALEN];\t\t/*\tPeer device address */\n\tu8\t\t\t\t\tstrconfig_method_desc_of_prov_disc_req[4];\t/*\tdescription for the config method located in the provisioning discovery request frame.\t */\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t/*\tThe UI must know this information to know which config method the remote p2p device is requiring. */\n};\n\nstruct tx_nego_req_info {\n\tu16\t\t\t\t\tpeer_channel_num[2];\t\t/*\tThe channel number which the receiver stands. */\n\tu8\t\t\t\t\tpeerDevAddr[ETH_ALEN];\t\t/*\tPeer device address */\n\tu8\t\t\t\t\tbenable;\t\t\t\t\t/*\tThis negoitation request frame is trigger to send or not */\n\tu8\t\t\t\t\tpeer_ch;\t\t\t\t\t/*\tThe listen channel for peer P2P device */\n};\n\nstruct group_id_info {\n\tu8\t\t\t\t\tgo_device_addr[ETH_ALEN];\t/*\tThe GO's device address of this P2P group */\n\tu8\t\t\t\t\tssid[WLAN_SSID_MAXLEN];\t\t/*\tThe SSID of this P2P group */\n};\n\nstruct scan_limit_info {\n\tu8\t\t\t\t\tscan_op_ch_only;\t\t\t/*\tWhen this flag is set, the driver should just scan the operation channel */\n#ifndef CONFIG_P2P_OP_CHK_SOCIAL_CH\n\tu8\t\t\t\t\toperation_ch[2];\t\t\t\t/*\tStore the operation channel of invitation request frame */\n#else\n\tu8\t\t\t\t\toperation_ch[5];\t\t\t\t/*\tStore additional channel 1,6,11  for Android 4.2 IOT & Nexus 4 */\n#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */\n};\n\n#ifdef CONFIG_IOCTL_CFG80211\nstruct cfg80211_wifidirect_info {\n\t_timer\t\t\t\t\tremain_on_ch_timer;\n\tu8\t\t\t\t\t\trestore_channel;\n\tstruct ieee80211_channel\tremain_on_ch_channel;\n\tenum nl80211_channel_type\tremain_on_ch_type;\n\tATOMIC_T ro_ch_cookie_gen;\n\tu64 remain_on_ch_cookie;\n\tbool is_ro_ch;\n\tstruct wireless_dev *ro_ch_wdev;\n\tsystime last_ro_ch_time; /* this will be updated at the beginning and end of ro_ch */\n};\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n#ifdef CONFIG_P2P_WOWLAN\n\nenum P2P_WOWLAN_RECV_FRAME_TYPE {\n\tP2P_WOWLAN_RECV_NEGO_REQ = 0,\n\tP2P_WOWLAN_RECV_INVITE_REQ = 1,\n\tP2P_WOWLAN_RECV_PROVISION_REQ = 2,\n};\n\nstruct p2p_wowlan_info {\n\n\tu8\t\t\t\t\t\tis_trigger;\n\tenum P2P_WOWLAN_RECV_FRAME_TYPE\twowlan_recv_frame_type;\n\tu8\t\t\t\t\t\twowlan_peer_addr[ETH_ALEN];\n\tu16\t\t\t\t\t\twowlan_peer_wpsconfig;\n\tu8\t\t\t\t\t\twowlan_peer_is_persistent;\n\tu8\t\t\t\t\t\twowlan_peer_invitation_type;\n};\n\n#endif /* CONFIG_P2P_WOWLAN */\n\nstruct wifidirect_info {\n\t_adapter\t\t\t\t*padapter;\n\t_timer\t\t\t\t\tfind_phase_timer;\n\t_timer\t\t\t\t\trestore_p2p_state_timer;\n\n\t/*\tUsed to do the scanning. After confirming the peer is availalble, the driver transmits the P2P frame to peer. */\n\t_timer\t\t\t\t\tpre_tx_scan_timer;\n\t_timer\t\t\t\t\treset_ch_sitesurvey;\n\t_timer\t\t\t\t\treset_ch_sitesurvey2;\t/*\tJust for resetting the scan limit function by using p2p nego */\n#ifdef CONFIG_CONCURRENT_MODE\n\t/*\tUsed to switch the channel between legacy AP and listen state. */\n\t_timer\t\t\t\t\tap_p2p_switch_timer;\n#endif\n\tstruct tx_provdisc_req_info\ttx_prov_disc_info;\n\tstruct rx_provdisc_req_info rx_prov_disc_info;\n\tstruct tx_invite_req_info\tinvitereq_info;\n\tstruct profile_info\t\t\tprofileinfo[P2P_MAX_PERSISTENT_GROUP_NUM];\t/*\tStore the profile information of persistent group */\n\tstruct tx_invite_resp_info\tinviteresp_info;\n\tstruct tx_nego_req_info\tnego_req_info;\n\tstruct group_id_info\t\tgroupid_info;\t/*\tStore the group id information when doing the group negotiation handshake. */\n\tstruct scan_limit_info\t\trx_invitereq_info;\t/*\tUsed for get the limit scan channel from the Invitation procedure */\n\tstruct scan_limit_info\t\tp2p_info;\t\t/*\tUsed for get the limit scan channel from the P2P negotiation handshake */\n#ifdef CONFIG_WFD\n\tstruct wifi_display_info\t\t*wfd_info;\n#endif\n\n#ifdef CONFIG_P2P_WOWLAN\n\tstruct p2p_wowlan_info\t\tp2p_wow_info;\n#endif /* CONFIG_P2P_WOWLAN */\n\n\tenum P2P_ROLE\t\t\trole;\n\tenum P2P_STATE\t\t\tpre_p2p_state;\n\tenum P2P_STATE\t\t\tp2p_state;\n\tu8\t\t\t\t\t\tdevice_addr[ETH_ALEN];\t/*\tThe device address should be the mac address of this device. */\n\tu8\t\t\t\t\t\tinterface_addr[ETH_ALEN];\n\tu8\t\t\t\t\t\tsocial_chan[4];\n\tu8\t\t\t\t\t\tlisten_channel;\n\tu8\t\t\t\t\t\toperating_channel;\n\tu8\t\t\t\t\t\tlisten_dwell;\t\t/*\tThis value should be between 1 and 3 */\n\tu8\t\t\t\t\t\tsupport_rate[8];\n\tu8\t\t\t\t\t\tp2p_wildcard_ssid[P2P_WILDCARD_SSID_LEN];\n\tu8\t\t\t\t\t\tintent;\t\t/*\tshould only include the intent value. */\n\tu8\t\t\t\t\t\tp2p_peer_interface_addr[ETH_ALEN];\n\tu8\t\t\t\t\t\tp2p_peer_device_addr[ETH_ALEN];\n\tu8\t\t\t\t\t\tpeer_intent;\t/*\tIncluded the intent value and tie breaker value. */\n\tu8\t\t\t\t\t\tdevice_name[WPS_MAX_DEVICE_NAME_LEN];\t/*\tDevice name for displaying on searching device screen */\n\tu16\t\t\t\t\t\tdevice_name_len;\n\tu8\t\t\t\t\t\tprofileindex;\t/*\tUsed to point to the index of profileinfo array */\n\tu8\t\t\t\t\t\tpeer_operating_ch;\n\tu8\t\t\t\t\t\tfind_phase_state_exchange_cnt;\n\tu16\t\t\t\t\t\tdevice_password_id_for_nego;\t/*\tThe device password ID for group negotation */\n\tu8\t\t\t\t\t\tnegotiation_dialog_token;\n\tu8\t\t\t\t\t\tnego_ssid[WLAN_SSID_MAXLEN];\t/*\tSSID information for group negotitation */\n\tu8\t\t\t\t\t\tnego_ssidlen;\n\tu8\t\t\t\t\t\tp2p_group_ssid[WLAN_SSID_MAXLEN];\n\tu8\t\t\t\t\t\tp2p_group_ssid_len;\n\tu8\t\t\t\t\t\tpersistent_supported;\t\t/*\tFlag to know the persistent function should be supported or not. */\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t/*\tIn the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI. */\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t/*\t0: disable */\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t/*\t1: enable */\n\tu8\t\t\t\t\t\tsession_available;\t\t\t/*\tFlag to set the WFD session available to enable or disable \"by Sigma\" */\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t/*\tIn the Sigma test, the Sigma will disable the session available by using the sta_preset CAPI. */\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t/*\t0: disable */\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t/*\t1: enable */\n\n\tu8\t\t\t\t\t\twfd_tdls_enable;\t\t\t/*\tFlag to enable or disable the TDLS by WFD Sigma */\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t/*\t0: disable */\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t/*\t1: enable */\n\tu8\t\t\t\t\t\twfd_tdls_weaksec;\t\t\t/*\tFlag to enable or disable the weak security function for TDLS by WFD Sigma */\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t/*\t0: disable */\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t/*\tIn this case, the driver can't issue the tdsl setup request frame. */\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t/*\t1: enable */\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t/*\tIn this case, the driver can issue the tdls setup request frame */\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t/*\teven the current security is weak security. */\n\n\tenum\tP2P_WPSINFO\t\tui_got_wps_info;\t\t\t/*\tThis field will store the WPS value (PIN value or PBC) that UI had got from the user. */\n\tu16\t\t\t\t\t\tsupported_wps_cm;\t\t\t/*\tThis field describes the WPS config method which this driver supported. */\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t/*\tThe value should be the combination of config method defined in page104 of WPS v2.0 spec.\t */\n\tu8\t\t\t\t\t\texternal_uuid;\t\t\t\t/* UUID flag */\n\tu8\t\t\t\t\t\tuuid[16];\t\t\t\t\t/* UUID */\n\tuint\t\t\t\t\t\tchannel_list_attr_len;\t/*\tThis field will contain the length of body of P2P Channel List attribute of group negotitation response frame. */\n\tu8\t\t\t\t\t\tchannel_list_attr[100];\t\t/*\tThis field will contain the body of P2P Channel List attribute of group negotitation response frame. */\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t/*\tWe will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame. */\n\tu8\t\t\t\t\t\tdriver_interface;\t\t\t/*\tIndicate DRIVER_WEXT or DRIVER_CFG80211 */\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tu16\t\t\t\t\t\text_listen_interval;\t/*\tThe interval to be available with legacy AP (ms) */\n\tu16\t\t\t\t\t\text_listen_period;\t/*\tThe time period to be available for P2P listen state (ms) */\n#endif\n#ifdef CONFIG_P2P_PS\n\tenum P2P_PS_MODE\t\tp2p_ps_mode; /* indicate p2p ps mode */\n\tenum P2P_PS_STATE\t\tp2p_ps_state; /* indicate p2p ps state */\n\tu8\t\t\t\t\t\tnoa_index; /* Identifies and instance of Notice of Absence timing. */\n\tu8\t\t\t\t\t\tctwindow; /* Client traffic window. A period of time in TU after TBTT. */\n\tu8\t\t\t\t\t\topp_ps; /* opportunistic power save. */\n\tu8\t\t\t\t\t\tnoa_num; /* number of NoA descriptor in P2P IE. */\n\tu8\t\t\t\t\t\tnoa_count[P2P_MAX_NOA_NUM]; /* Count for owner, Type of client. */\n\tu32\t\t\t\t\t\tnoa_duration[P2P_MAX_NOA_NUM]; /* Max duration for owner, preferred or min acceptable duration for client. */\n\tu32\t\t\t\t\t\tnoa_interval[P2P_MAX_NOA_NUM]; /* Length of interval for owner, preferred or max acceptable interval of client. */\n\tu32\t\t\t\t\t\tnoa_start_time[P2P_MAX_NOA_NUM]; /* schedule expressed in terms of the lower 4 bytes of the TSF timer. */\n#endif /* CONFIG_P2P_PS */\n};\n\nstruct tdls_ss_record {\t/* signal strength record */\n\tu8\t\tmacaddr[ETH_ALEN];\n\tu8\t\tRxPWDBAll;\n\tu8\t\tis_tdls_sta;\t/* _TRUE: direct link sta, _FALSE: else */\n};\n\nstruct tdls_temp_mgmt {\n\tu8\tinitiator;\t/* 0: None, 1: we initiate, 2: peer initiate */\n\tu8\tpeer_addr[ETH_ALEN];\n};\n\n#ifdef CONFIG_TDLS_CH_SW\nstruct tdls_ch_switch {\n\tu32\tch_sw_state;\n\tATOMIC_T\tchsw_on;\n\tu8\taddr[ETH_ALEN];\n\tu8\toff_ch_num;\n\tu8\tch_offset;\n\tu32\tcur_time;\n\tu8\tdelay_switch_back;\n\tu8\tdump_stack;\n\tstruct submit_ctx\tchsw_sctx;\n};\n#endif\n\nstruct tdls_info {\n\tu8\t\t\t\t\tap_prohibited;\n\tu8\t\t\t\t\tch_switch_prohibited;\n\tu8\t\t\t\t\tlink_established;\n\tu8\t\t\t\t\tsta_cnt;\n\tu8\t\t\t\t\tsta_maximum;\t/* 1:tdls sta is equal (NUM_STA-1), reach max direct link number; 0: else; */\n\tstruct tdls_ss_record\tss_record;\n#ifdef CONFIG_TDLS_CH_SW\n\tstruct tdls_ch_switch\tchsw_info;\n#endif\n\n\tu8\t\t\t\t\tch_sensing;\n\tu8\t\t\t\t\tcur_channel;\n\tu8\t\t\t\t\tcollect_pkt_num[MAX_CHANNEL_NUM];\n\t_lock\t\t\t\tcmd_lock;\n\t_lock\t\t\t\thdl_lock;\n\tu8\t\t\t\t\twatchdog_count;\n\tu8\t\t\t\t\tdev_discovered;\t\t/* WFD_TDLS: for sigma test */\n\n\t/* Let wpa_supplicant to setup*/\n\tu8\t\t\t\t\tdriver_setup;\n#ifdef CONFIG_WFD\n\tstruct wifi_display_info\t\t*wfd_info;\n#endif\n\n\tstruct submit_ctx\t*tdls_sctx;\n};\n\nstruct tdls_txmgmt {\n\tu8 peer[ETH_ALEN];\n\tu8 action_code;\n\tu8 dialog_token;\n\tu16 status_code;\n\tu8 *buf;\n\tsize_t len;\n};\n\n/* used for mlme_priv.roam_flags */\nenum {\n\tRTW_ROAM_ON_EXPIRED = BIT0,\n\tRTW_ROAM_ON_RESUME = BIT1,\n\tRTW_ROAM_ACTIVE = BIT2,\n};\n\nstruct beacon_keys {\n\tu8 ssid[IW_ESSID_MAX_SIZE];\n\tu32 ssid_len;\n\tu8 ch;\n\tu8 bw;\n\tu8 offset;\n\tu8 proto_cap; /* PROTO_CAP_XXX */\n\tu8 rate_set[12];\n\tu8 rate_num;\n\tint encryp_protocol;\n\tint pairwise_cipher;\n\tint group_cipher;\n\tu32 akm;\n};\n#ifdef CONFIG_RTW_80211R\n#define RTW_FT_ACTION_REQ_LMT\t4\n#define RTW_FT_MAX_IE_SZ\t256\n\nenum _rtw_ft_sta_status {\n\tRTW_FT_UNASSOCIATED_STA = 0,\n\tRTW_FT_AUTHENTICATING_STA,\n\tRTW_FT_AUTHENTICATED_STA,\n\tRTW_FT_ASSOCIATING_STA,\n\tRTW_FT_ASSOCIATED_STA,\n\tRTW_FT_REQUESTING_STA,\n\tRTW_FT_REQUESTED_STA,\n\tRTW_FT_CONFIRMED_STA,\n\tRTW_FT_UNSPECIFIED_STA\n};\n\n#define rtw_ft_chk_status(a, s) \\\n\t((a)->mlmepriv.ft_roam.ft_status == (s))\n\n#define rtw_ft_roam_status(a, s)\t\\\n\t((rtw_to_roam(a) > 0) && rtw_ft_chk_status(a, s))\n\n#define rtw_ft_authed_sta(a)\t\\\n\t((rtw_ft_chk_status(a, RTW_FT_AUTHENTICATED_STA)) ||\t\\\n\t(rtw_ft_chk_status(a, RTW_FT_ASSOCIATING_STA)) ||\t\\\n\t(rtw_ft_chk_status(a, RTW_FT_ASSOCIATED_STA)))\n\n#define rtw_ft_set_status(a, s) \\\n\tdo { \\\n\t\t((a)->mlmepriv.ft_roam.ft_status = (s)); \\\n\t} while (0)\n\n#define rtw_ft_lock_set_status(a, s, irq) \\\n\tdo { \\\n\t\t_enter_critical_bh(&(a)->mlmepriv.lock, ((_irqL *)(irq)));\t\\\n\t\t((a)->mlmepriv.ft_roam.ft_status = (s));\t\\\n\t\t_exit_critical_bh(&(a)->mlmepriv.lock, ((_irqL *)(irq)));\t\\\n\t} while (0)\n\n#define rtw_ft_reset_status(a) \\\n\tdo { \\\n\t\t((a)->mlmepriv.ft_roam.ft_status = RTW_FT_UNASSOCIATED_STA); \\\n\t} while (0)\n\nenum rtw_ft_capability {\n\tRTW_FT_EN = BIT0,\n\tRTW_FT_OTD_EN = BIT1,\n\tRTW_FT_PEER_EN = BIT2,\n\tRTW_FT_PEER_OTD_EN = BIT3,\n\tRTW_FT_BTM_ROAM = BIT4,\n};\n\n#define rtw_ft_chk_flags(a, f) \\\n\t((a)->mlmepriv.ft_roam.ft_flags & (f))\n\n#define rtw_ft_set_flags(a, f) \\\n\tdo { \\\n\t\t((a)->mlmepriv.ft_roam.ft_flags |= (f)); \\\n\t} while (0)\n\n#define rtw_ft_clr_flags(a, f) \\\n\tdo { \\\n\t\t((a)->mlmepriv.ft_roam.ft_flags &= ~(f)); \\\n\t} while (0)\n\n#define rtw_ft_roam(a)\t\\\n\t((rtw_to_roam(a) > 0) && rtw_ft_chk_flags(a, RTW_FT_PEER_EN))\n\t\n#define rtw_ft_valid_akm(a, t)\t\\\n\t((rtw_ft_chk_flags(a, RTW_FT_EN)) && \\\n\t(((t) == 3) || ((t) == 4)))\n\n#define rtw_ft_roam_expired(a, r)\t\\\n\t((rtw_chk_roam_flags(a, RTW_ROAM_ON_EXPIRED)) \\\n\t&& (r == WLAN_REASON_ACTIVE_ROAM))\n\n#define rtw_ft_otd_roam_en(a)\t\\\n\t((rtw_ft_chk_flags(a, RTW_FT_OTD_EN))\t\\\n\t&& ((a)->mlmepriv.ft_roam.ft_roam_on_expired == _FALSE)\t\\\n\t&& ((a)->mlmepriv.ft_roam.ft_cap & 0x01))\n\t\n#define rtw_ft_otd_roam(a) \\\n\trtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN)\n\n#define rtw_ft_valid_otd_candidate(a, p)\t\\\n\t((rtw_ft_chk_flags(a, RTW_FT_OTD_EN)) \t\\\n\t&& ((rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN)\t\\\n\t&& ((*((p)+4) & 0x01) == 0))\t\\\n\t|| ((rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN) == 0)\t\\\n\t&& (*((p)+4) & 0x01))))\n\nstruct ft_roam_info {\n\tu16\tmdid;\n\tu8\tft_cap;\t\n\t/*b0: FT over DS, b1: Resource Req Protocol Cap, b2~b7: Reserved*/\n\tu8\tupdated_ft_ies[RTW_FT_MAX_IE_SZ];\n\tu16\tupdated_ft_ies_len;\n\tu8\tft_action[RTW_FT_MAX_IE_SZ];\n\tu16\tft_action_len;\n\tstruct cfg80211_ft_event_params ft_event;\n\tu8\tft_roam_on_expired;\n\tu8\tft_flags;\n\tu32 ft_status;\n\tu32 ft_req_retry_cnt;\n\tbool ft_updated_bcn;\t\n};\n#endif\n\n#ifdef CONFIG_LAYER2_ROAMING\n#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)\n#define RTW_RRM_NB_RPT_EN\t\tBIT(1)\n#define RTW_MAX_NB_RPT_NUM\t8\n\n#define rtw_roam_busy_scan(a, nb)\t\\\n\t(((a)->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE) && \\\n\t(((a)->mlmepriv.ch_cnt) < ((nb)->nb_rpt_ch_list_num)))\n\n#define rtw_wnm_btm_preference_cap(a) \\\n\t((a)->mlmepriv.nb_info.preference_en == _TRUE)\n\n#define rtw_wnm_btm_diff_bss(a) \\\n\t((rtw_wnm_btm_preference_cap(a)) && \\\n\t(is_zero_mac_addr((a)->mlmepriv.nb_info.roam_target_addr) == _FALSE) && \\\n\t(_rtw_memcmp((a)->mlmepriv.nb_info.roam_target_addr,\\\n\t\t(a)->mlmepriv.cur_network.network.MacAddress, ETH_ALEN) == _FALSE))\n\n#define rtw_wnm_btm_roam_candidate(a, c) \\\n\t((rtw_wnm_btm_preference_cap(a)) && \\\n\t(is_zero_mac_addr((a)->mlmepriv.nb_info.roam_target_addr) == _FALSE) && \\\n\t(_rtw_memcmp((a)->mlmepriv.nb_info.roam_target_addr,\\\n\t\t(c)->network.MacAddress, ETH_ALEN)))\n\n#define rtw_wnm_set_ext_cap_btm(_pEleStart, _val) \\\n\tSET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+2, 3, 1, _val)\n\n#define wnm_btm_bss_term_inc(p) (*((u8 *)((p)+3)) & BSS_TERMINATION_INCLUDED)\n\n#define wnm_btm_ess_disassoc_im(p) (*((u8 *)((p)+3)) & ESS_DISASSOC_IMMINENT)\n\n#define wnm_btm_req_mode(p) (*((u8 *)((p)+3)))\n\n#define wnm_btm_disassoc_timer(p) (*((u16 *)((p)+4)))\n\n#define wnm_btm_valid_interval(p) (*((u8 *)((p)+6)))\n\n#define wnm_btm_term_duration_offset(p) ((p)+7)\n\n/*IEEE Std 80211k Figure 7-95b Neighbor Report element format*/\nstruct nb_rpt_hdr {\n\tu8 id; /*0x34: Neighbor Report Element ID*/\n\tu8 len;\n\tu8 bssid[ETH_ALEN];\n\tu32 bss_info;\n\tu8 reg_class;\n\tu8 ch_num;\n\tu8 phy_type;\t\n};\n\n/*IEEE Std 80211v, Figure 7-95e2XBSS Termination Duration subelement field format */\nstruct btm_term_duration {\n\tu8 id;\n\tu8 len;\n\tu64 tsf;\n\tu16 duration;\n};\n\n/*IEEE Std 80211v, Figure 7-101n8XBSS Transition Management Request frame body format */\nstruct btm_req_hdr {\n\tu8 req_mode;\n\tu16 disassoc_timer;\n\tu8 validity_interval;\n\tstruct btm_term_duration term_duration;\n};\n\n/*IEEE Std 80211v,  Table 7-43b Optional Subelement IDs for Neighbor Report*/\n/* BSS Transition Candidate Preference */\n#define WNM_BTM_CAND_PREF_SUBEID 0x03\n\n/* BSS Termination Duration */\n#define WNM_BTM_TERM_DUR_SUBEID\t\t0x04\n\nstruct wnm_btm_cant {\n\tstruct nb_rpt_hdr nb_rpt;\n\tu8 preference;\t/* BSS Transition Candidate Preference */\n};\n\nenum rtw_btm_req_mod {\n\tPREFERRED_CANDIDATE_LIST_INCLUDED = BIT0,\n\tABRIDGED = BIT1,\n\tDISASSOC_IMMINENT = BIT2,\n\tBSS_TERMINATION_INCLUDED = BIT3,\n\tESS_DISASSOC_IMMINENT = BIT4,\n};\n\nstruct roam_nb_info {\n\tstruct nb_rpt_hdr nb_rpt[RTW_MAX_NB_RPT_NUM];\n\tstruct rtw_ieee80211_channel nb_rpt_ch_list[RTW_MAX_NB_RPT_NUM];\n\tbool\tnb_rpt_valid;\n\tu8\tnb_rpt_ch_list_num;\n\tu8 preference_en;\n\tu8 roam_target_addr[ETH_ALEN];\n\tu32\tlast_nb_rpt_entries;\n\tbool\tnb_rpt_is_same;\n\t_timer roam_scan_timer;\n};\n#endif\t/* defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) */\n#endif\n\nstruct mlme_priv {\n\n\t_lock\tlock;\n\tsint\tfw_state;\t/* shall we protect this variable? maybe not necessarily... */\n\tu8\tto_join; /* flag */\n\tu16 join_status;\n#ifdef CONFIG_LAYER2_ROAMING\n\tu8 to_roam; /* roaming trying times */\n\tstruct wlan_network *roam_network; /* the target of active roam */\n\tu8 roam_flags;\n\tu8 roam_rssi_diff_th; /* rssi difference threshold for active scan candidate selection */\n\tu32 roam_scan_int; \t\t/* scan interval for active roam (Unit:2 second)*/\n\tu32 roam_scanr_exp_ms; /* scan result expire time in ms  for roam */\n\tu8 roam_tgt_addr[ETH_ALEN]; /* request to roam to speicific target without other consideration */\n\tu8 roam_rssi_threshold;\n\tsystime last_roaming;\n\tbool need_to_roam;\n#endif\n\n\tu8\t*nic_hdl;\n\tu32\tmax_bss_cnt;\t\t/*\tThe size of scan queue\t*/\n\t_list\t\t*pscanned;\n\t_queue\tfree_bss_pool;\n\t_queue\tscanned_queue;\n\tu8\t\t*free_bss_buf;\n\tu32\tnum_of_scanned;\n\n\tNDIS_802_11_SSID\tassoc_ssid;\n\tu8\tassoc_bssid[6];\n\tu16\tassoc_ch;\t\t/* 0 reserved for no specific channel */\n\n\tstruct wlan_network\tcur_network;\n\tstruct wlan_network *cur_network_scanned;\n\n\t/* bcn check info */\n\tstruct beacon_keys cur_beacon_keys; /* save current beacon keys */\n#ifdef CONFIG_BCN_CNT_CONFIRM_HDL\n\tstruct beacon_keys new_beacon_keys; /* save new beacon keys */\n\tu8 new_beacon_cnts; /* if new_beacon_cnts >= threshold, ap beacon is changed */\n#endif\n\n#ifdef CONFIG_ARP_KEEP_ALIVE\n\t/* for arp offload keep alive */\n\tu8 bGetGateway;\n\tu8\tGetGatewayTryCnt;\n\tu8\tgw_mac_addr[ETH_ALEN];\n\tu8\tgw_ip[4];\n#endif\n\n\t/* uint wireless_mode; no used, remove it */\n\n\tu32\tauto_scan_int_ms;\n\n\t_timer assoc_timer;\n\n\tuint assoc_by_bssid;\n\tuint assoc_by_rssi;\n\n\t_timer scan_to_timer; /* driver itself handles scan_timeout status. */\n\tsystime scan_start_time; /* used to evaluate the time spent in scanning */\n\n#ifdef CONFIG_SET_SCAN_DENY_TIMER\n\t_timer set_scan_deny_timer;\n\tATOMIC_T set_scan_deny; /* 0: allowed, 1: deny */\n#endif\n\tu8 wpa_phase;/*wpa_phase after wps finished*/\n\n\tstruct qos_priv qospriv;\n\n#ifdef CONFIG_80211N_HT\n\n\t/* Number of non-HT AP/stations */\n\tint num_sta_no_ht;\n\n\t/* Number of HT AP/stations 20 MHz */\n\t/* int num_sta_ht_20mhz; */\n\n\n\tint num_FortyMHzIntolerant;\n\n\tstruct ht_priv\thtpriv;\n\n#endif\n\n#ifdef CONFIG_80211AC_VHT\n\tstruct vht_priv\tvhtpriv;\n#ifdef ROKU_PRIVATE\n\t/*infra mode, used to store AP's info*/\n\tstruct vht_priv_infra_ap vhtpriv_infra_ap;\n#endif /* ROKU_PRIVATE */\n#endif\n\n#ifdef ROKU_PRIVATE\n\tstruct ht_priv_infra_ap htpriv_infra_ap;\n#endif /* ROKU_PRIVATE */\n\n#ifdef CONFIG_RTW_80211R\n\tstruct ft_roam_info ft_roam;\n#endif\n#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)\n\tstruct roam_nb_info nb_info;\n\tu8 ch_cnt;\n#endif\n\n\tRT_LINK_DETECT_T\tLinkDetectInfo;\n\n\tu8\tacm_mask; /* for wmm acm mask */\n\tRT_SCAN_TYPE\tscan_mode; /* active: 1, passive: 0 */\n\n\tu8 *wps_probe_req_ie;\n\tu32 wps_probe_req_ie_len;\n\n\tu8 ext_capab_ie_data[8];/*currently for ap mode only*/\n\tu8 ext_capab_ie_len;\n\n#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)\n\t/* Number of associated Non-ERP stations (i.e., stations using 802.11b\n\t * in 802.11g BSS) */\n\tint num_sta_non_erp;\n\n\t/* Number of associated stations that do not support Short Slot Time */\n\tint num_sta_no_short_slot_time;\n\n\t/* Number of associated stations that do not support Short Preamble */\n\tint num_sta_no_short_preamble;\n\n\tATOMIC_T olbc; /* Overlapping Legacy BSS Condition (Legacy b/g)*/\n\n\t/* Number of HT associated stations that do not support greenfield */\n\tint num_sta_ht_no_gf;\n\n\t/* Number of associated non-HT stations */\n\t/* int num_sta_no_ht; */\n\n\t/* Number of HT associated stations 20 MHz */\n\tint num_sta_ht_20mhz;\n\n\t/* number of associated stations 40MHz intolerant */\n\tint num_sta_40mhz_intolerant;\n\n\t/* Overlapping BSS information */\n\tATOMIC_T olbc_ht;\n\n#ifdef CONFIG_80211N_HT\n\tint ht_20mhz_width_req;\n\tint ht_intolerant_ch_reported;\n\tu16 ht_op_mode;\n\tu8 sw_to_20mhz; /*switch to 20Mhz BW*/\n#endif /* CONFIG_80211N_HT */\n\n#ifdef CONFIG_RTW_80211R\n\tu8 *auth_rsp;\n\tu32 auth_rsp_len;\n#endif\n\tu8 *assoc_req;\n\tu32 assoc_req_len;\n\n\tu8 *assoc_rsp;\n\tu32 assoc_rsp_len;\n\n\t/* u8 *wps_probe_req_ie; */\n\t/* u32 wps_probe_req_ie_len; */\n\n\tu8 *wps_beacon_ie;\n\tu32 wps_beacon_ie_len;\n\n\tu8 *wps_probe_resp_ie;\n\tu32 wps_probe_resp_ie_len;\n\n\tu8 *wps_assoc_resp_ie;\n\tu32 wps_assoc_resp_ie_len;\n\n\tu8 *p2p_beacon_ie;\n\tu32 p2p_beacon_ie_len;\n\n\tu8 *p2p_probe_req_ie;\n\tu32 p2p_probe_req_ie_len;\n\n\tu8 *p2p_probe_resp_ie;\n\tu32 p2p_probe_resp_ie_len;\n\n\tu8 *p2p_go_probe_resp_ie;\t\t/* for GO */\n\tu32 p2p_go_probe_resp_ie_len;\t/* for GO */\n\n\tu8 *p2p_assoc_req_ie;\n\tu32 p2p_assoc_req_ie_len;\n\n\tu8 *p2p_assoc_resp_ie;\n\tu32 p2p_assoc_resp_ie_len;\n\n\t_lock\tbcn_update_lock;\n\tu8\t\tupdate_bcn;\n\n\tu8 ori_ch;\n\tu8 ori_bw;\n\tu8 ori_offset;\n\t#ifdef CONFIG_80211AC_VHT\n\tu8 ori_vht_en;\n\t#endif\n#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */\n\n#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)\n\tu8 *wfd_beacon_ie;\n\tu32 wfd_beacon_ie_len;\n\n\tu8 *wfd_probe_req_ie;\n\tu32 wfd_probe_req_ie_len;\n\n\tu8 *wfd_probe_resp_ie;\n\tu32 wfd_probe_resp_ie_len;\n\n\tu8 *wfd_go_probe_resp_ie;\t\t/* for GO */\n\tu32 wfd_go_probe_resp_ie_len;\t/* for GO */\n\n\tu8 *wfd_assoc_req_ie;\n\tu32 wfd_assoc_req_ie_len;\n\n\tu8 *wfd_assoc_resp_ie;\n\tu32 wfd_assoc_resp_ie_len;\n#endif\n\n#ifdef RTK_DMP_PLATFORM\n\t/* DMP kobject_hotplug function  signal need in passive level */\n\t_workitem\tLinkup_workitem;\n\t_workitem\tLinkdown_workitem;\n#endif\n\tsystime lastscantime;\n#ifdef CONFIG_CONCURRENT_MODE\n\tu8\tscanning_via_buddy_intf;\n#endif\n\n#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE\n\tu32 vendor_ie_mask[WLAN_MAX_VENDOR_IE_NUM];\n\tu8 vendor_ie[WLAN_MAX_VENDOR_IE_NUM][WLAN_MAX_VENDOR_IE_LEN];\n\tu32 vendor_ielen[WLAN_MAX_VENDOR_IE_NUM];\n#endif\n};\n\n#define mlme_set_scan_to_timer(mlme, ms) \\\n\tdo { \\\n\t\t/* RTW_INFO(\"%s set_scan_to_timer(%p, %d)\\n\", __FUNCTION__, (mlme), (ms)); */ \\\n\t\t_set_timer(&(mlme)->scan_to_timer, (ms)); \\\n\t} while (0)\n\n#define rtw_mlme_set_auto_scan_int(adapter, ms) \\\n\tdo { \\\n\t\tadapter->mlmepriv.auto_scan_int_ms = ms; \\\n\t} while (0)\n\n#define RTW_AUTO_SCAN_REASON_UNSPECIFIED\t\t0\n#define RTW_AUTO_SCAN_REASON_2040_BSS\t\t\tBIT0\n#define RTW_AUTO_SCAN_REASON_ACS\t\t\t\tBIT1\n#define RTW_AUTO_SCAN_REASON_ROAM\t\t\t\tBIT2\n#define RTW_AUTO_SCAN_REASON_MESH_OFFCH_CAND\tBIT3\n\nvoid rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason);\n\n#ifdef CONFIG_AP_MODE\n\nstruct hostapd_priv {\n\t_adapter *padapter;\n\n#ifdef CONFIG_HOSTAPD_MLME\n\tstruct net_device *pmgnt_netdev;\n\tstruct usb_anchor anchored;\n#endif\n\n};\n\nextern int hostapd_mode_init(_adapter *padapter);\nextern void hostapd_mode_unload(_adapter *padapter);\n#endif\n\n\nextern void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status);\nextern void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf);\nextern void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf);\nextern void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf);\nextern void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf);\nextern void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf);\nvoid rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id);\nvoid rtw_sta_mstatus_report(_adapter *adapter);\nextern void rtw_atimdone_event_callback(_adapter *adapter, u8 *pbuf);\nextern void rtw_cpwm_event_callback(_adapter *adapter, u8 *pbuf);\nextern void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf);\n#ifdef CONFIG_IEEE80211W\nvoid rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf);\n#endif /* CONFIG_IEEE80211W */\n#ifdef CONFIG_RTW_80211R\nvoid rtw_ft_info_init(struct ft_roam_info *pft);\nu8 rtw_ft_chk_roaming_candidate(_adapter *padapter, \n\tstruct wlan_network *competitor);\nvoid rtw_ft_update_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork);\nvoid rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf);\n#endif\n#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)\nvoid rtw_roam_nb_info_init(_adapter *padapter);\n#endif\n\nthread_return event_thread(thread_context context);\n\nextern void rtw_free_network_queue(_adapter *adapter, u8 isfreeall);\nextern int rtw_init_mlme_priv(_adapter *adapter);/* (struct mlme_priv *pmlmepriv); */\n\nextern void rtw_free_mlme_priv(struct mlme_priv *pmlmepriv);\n\n\nextern sint rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv);\nextern sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint keyid, u8 set_tx, bool enqueue);\nextern sint rtw_set_auth(_adapter *adapter, struct security_priv *psecuritypriv);\n\n__inline static u8 *get_bssid(struct mlme_priv *pmlmepriv)\n{\n\t/* if sta_mode:pmlmepriv->cur_network.network.MacAddress=> bssid */\n\t/* if adhoc_mode:pmlmepriv->cur_network.network.MacAddress=> ibss mac address */\n\treturn pmlmepriv->cur_network.network.MacAddress;\n}\n\n__inline static sint check_fwstate(struct mlme_priv *pmlmepriv, sint state)\n{\n\tif ((state == WIFI_NULL_STATE) &&\n\t\t(pmlmepriv->fw_state == WIFI_NULL_STATE))\n\t\treturn _TRUE;\n\n\tif (pmlmepriv->fw_state & state)\n\t\treturn _TRUE;\n\n\treturn _FALSE;\n}\n\n__inline static sint get_fwstate(struct mlme_priv *pmlmepriv)\n{\n\treturn pmlmepriv->fw_state;\n}\n\n/*\n * No Limit on the calling context,\n * therefore set it to be the critical section...\n *\n * ### NOTE:#### (!!!!)\n * MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock\n */\nextern void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state);\n\nstatic inline void set_fwstate(struct mlme_priv *pmlmepriv, sint state)\n{\n\tpmlmepriv->fw_state |= state;\n\trtw_mi_update_iface_status(pmlmepriv, state);\n}\nstatic inline void init_fwstate(struct mlme_priv *pmlmepriv, sint state)\n{\n\tpmlmepriv->fw_state = state;\n\trtw_mi_update_iface_status(pmlmepriv, state);\n}\n\nstatic inline void _clr_fwstate_(struct mlme_priv *pmlmepriv, sint state)\n{\n\tpmlmepriv->fw_state &= ~state;\n\trtw_mi_update_iface_status(pmlmepriv, state);\n}\n\n/*\n * No Limit on the calling context,\n * therefore set it to be the critical section...\n */\nstatic inline void clr_fwstate(struct mlme_priv *pmlmepriv, sint state)\n{\n\t_irqL irqL;\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\t_clr_fwstate_(pmlmepriv, state);\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n}\n\nstatic inline void up_scanned_network(struct mlme_priv *pmlmepriv)\n{\n\t_irqL irqL;\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\tpmlmepriv->num_of_scanned++;\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n}\nu8 rtw_is_adapter_up(_adapter *padapter);\n\n__inline static void down_scanned_network(struct mlme_priv *pmlmepriv)\n{\n\t_irqL irqL;\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\tpmlmepriv->num_of_scanned--;\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n}\n\n__inline static void set_scanned_network_val(struct mlme_priv *pmlmepriv, sint val)\n{\n\t_irqL irqL;\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\tpmlmepriv->num_of_scanned = val;\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n}\n\nextern u16 rtw_get_capability(WLAN_BSSID_EX *bss);\nextern bool rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target);\nextern void rtw_disconnect_hdl_under_linked(_adapter *adapter, struct sta_info *psta, u8 free_assoc);\nextern void rtw_generate_random_ibss(u8 *pibss);\nstruct wlan_network *_rtw_find_network(_queue *scanned_queue, const u8 *addr);\nstruct wlan_network *rtw_find_network(_queue *scanned_queue, const u8 *addr);\nextern struct wlan_network *rtw_get_oldest_wlan_network(_queue *scanned_queue);\nstruct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network);\nstruct wlan_network *rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network);\n\nextern void rtw_free_assoc_resources(_adapter *adapter, u8 lock_scanned_queue);\nextern void rtw_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated);\nextern void rtw_indicate_connect(_adapter *adapter);\nvoid rtw_indicate_scan_done(_adapter *padapter, bool aborted);\n\nvoid rtw_drv_scan_by_self(_adapter *padapter, u8 reason);\nvoid rtw_scan_wait_completed(_adapter *adapter);\nu32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms);\nvoid rtw_scan_abort_no_wait(_adapter *adapter);\nvoid rtw_scan_abort(_adapter *adapter);\nu32 rtw_join_abort_timeout(_adapter *adapter, u32 timeout_ms);\n\nint rtw_cached_pmkid(_adapter *Adapter, u8 *bssid);\nint rtw_rsn_sync_pmkid(_adapter *adapter, u8 *ie, uint ie_len, int i_ent);\n\nextern int rtw_restruct_sec_ie(_adapter *adapter, u8 *out_ie);\n#ifdef CONFIG_WMMPS_STA\nvoid rtw_uapsd_use_default_setting(_adapter *padapter);\nbool rtw_is_wmmps_mode(_adapter *padapter);\n#endif /* CONFIG_WMMPS_STA */\nextern int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len);\nextern void rtw_init_registrypriv_dev_network(_adapter *adapter);\n\nextern void rtw_update_registrypriv_dev_network(_adapter *adapter);\n\nextern void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter);\n\nextern void rtw_join_timeout_handler(void *ctx);\nextern void rtw_scan_timeout_handler(void *ctx);\n\nextern void rtw_dynamic_check_timer_handlder(void *ctx);\nextern void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter);\n\nenum {\n\tSS_DENY_MP_MODE,\n\tSS_DENY_RSON_SCANING,\n\tSS_DENY_BLOCK_SCAN,\n\tSS_DENY_BY_DRV,\n\tSS_DENY_SELF_AP_UNDER_WPS,\n\tSS_DENY_SELF_AP_UNDER_LINKING,\n\tSS_DENY_SELF_AP_UNDER_SURVEY,\n\t/*SS_DENY_SELF_STA_UNDER_WPS,*/\n\tSS_DENY_SELF_STA_UNDER_LINKING,\n\tSS_DENY_SELF_STA_UNDER_SURVEY,\n\tSS_DENY_BUDDY_UNDER_LINK_WPS,\n\tSS_DENY_BUDDY_UNDER_SURVEY,\n\tSS_DENY_BUSY_TRAFFIC,\n\tSS_ALLOW,\n#ifdef DBG_LA_MODE\n\tSS_DENY_LA_MODE,\n#endif\n\tSS_DENY_ADAPTIVITY,\n};\n\nu8 _rtw_sitesurvey_condition_check(const char *caller, _adapter *adapter, bool check_sc_interval);\n#define rtw_sitesurvey_condition_check(adapter, check_sc_interval) _rtw_sitesurvey_condition_check(__func__, adapter, check_sc_interval)\n\n#ifdef CONFIG_SET_SCAN_DENY_TIMER\nbool rtw_is_scan_deny(_adapter *adapter);\nvoid rtw_clear_scan_deny(_adapter *adapter);\nvoid rtw_set_scan_deny_timer_hdl(void *ctx);\nvoid rtw_set_scan_deny(_adapter *adapter, u32 ms);\n#else\n#define rtw_is_scan_deny(adapter) _FALSE\n#define rtw_clear_scan_deny(adapter) do {} while (0)\n#define rtw_set_scan_deny(adapter, ms) do {} while (0)\n#endif\n\nvoid rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv);\n\n#define MLME_BEACON_IE\t\t\t0\n#define MLME_PROBE_REQ_IE\t\t1\n#define MLME_PROBE_RESP_IE\t\t2\n#define MLME_GO_PROBE_RESP_IE\t3\n#define MLME_ASSOC_REQ_IE\t\t4\n#define MLME_ASSOC_RESP_IE\t\t5\n\n#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)\nint rtw_mlme_update_wfd_ie_data(struct mlme_priv *mlme, u8 type, u8 *ie, u32 ie_len);\n#endif\n\n\n/* extern struct wlan_network* _rtw_dequeue_network(_queue *queue); */\n\nextern struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv);\n\n\nextern void _rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 isfreeall);\nextern void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork);\n\nextern void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall);\n\nextern sint rtw_if_up(_adapter *padapter);\n\nsint rtw_linked_check(_adapter *padapter);\n\nu8 *rtw_get_capability_from_ie(u8 *ie);\nu8 *rtw_get_timestampe_from_ie(u8 *ie);\nu8 *rtw_get_beacon_interval_from_ie(u8 *ie);\n\n\nvoid rtw_joinbss_reset(_adapter *padapter);\n\n#ifdef CONFIG_80211N_HT\nvoid\trtw_ht_use_default_setting(_adapter *padapter);\nvoid rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len);\nunsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel);\nvoid rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel);\nvoid rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe, u8 issue_when_busy);\nvoid rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len);\n#endif\n\nint rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork);\nint is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature);\n\n#ifdef CONFIG_LAYER2_ROAMING\n#define rtw_roam_flags(adapter) ((adapter)->mlmepriv.roam_flags)\n#define rtw_chk_roam_flags(adapter, flags) ((adapter)->mlmepriv.roam_flags & flags)\n#define rtw_clr_roam_flags(adapter, flags) \\\n\tdo { \\\n\t\t((adapter)->mlmepriv.roam_flags &= ~flags); \\\n\t} while (0)\n\n#define rtw_set_roam_flags(adapter, flags) \\\n\tdo { \\\n\t\t((adapter)->mlmepriv.roam_flags |= flags); \\\n\t} while (0)\n\n#define rtw_assign_roam_flags(adapter, flags) \\\n\tdo { \\\n\t\t((adapter)->mlmepriv.roam_flags = flags); \\\n\t} while (0)\n\nvoid _rtw_roaming(_adapter *adapter, struct wlan_network *tgt_network);\nvoid rtw_roaming(_adapter *adapter, struct wlan_network *tgt_network);\nvoid rtw_set_to_roam(_adapter *adapter, u8 to_roam);\nu8 rtw_dec_to_roam(_adapter *adapter);\nu8 rtw_to_roam(_adapter *adapter);\nint rtw_select_roaming_candidate(struct mlme_priv *pmlmepriv);\n#else\n#define rtw_roam_flags(adapter) 0\n#define rtw_chk_roam_flags(adapter, flags) 0\n#define rtw_clr_roam_flags(adapter, flags) do {} while (0)\n#define rtw_set_roam_flags(adapter, flags) do {} while (0)\n#define rtw_assign_roam_flags(adapter, flags) do {} while (0)\n#define _rtw_roaming(adapter, tgt_network) do {} while (0)\n#define rtw_roaming(adapter, tgt_network) do {} while (0)\n#define rtw_set_to_roam(adapter, to_roam) do {} while (0)\n#define rtw_dec_to_roam(adapter) 0\n#define rtw_to_roam(adapter) 0\n#define rtw_select_roaming_candidate(mlme) _FAIL\n#endif /* CONFIG_LAYER2_ROAMING */\n\nbool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset);\n\nstruct sta_media_status_rpt_cmd_parm {\n\tstruct sta_info *sta;\n\tbool connected;\n};\n\nvoid rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool connected);\nu8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected);\nvoid rtw_sta_media_status_rpt_cmd_hdl(_adapter *adapter, struct sta_media_status_rpt_cmd_parm *parm);\nvoid rtw_sta_traffic_info(void *sel, _adapter *adapter);\n\n#define GET_ARP_HTYPE(_arp)\tBE_BITS_TO_2BYTE(((u8 *)(_arp)) + 0, 0, 16)\n#define GET_ARP_PTYPE(_arp)\tBE_BITS_TO_2BYTE(((u8 *)(_arp)) + 2, 0, 16)\n#define GET_ARP_HLEN(_arp)\tBE_BITS_TO_1BYTE(((u8 *)(_arp)) + 4, 0, 8)\n#define GET_ARP_PLEN(_arp)\tBE_BITS_TO_1BYTE(((u8 *)(_arp)) + 5, 0, 8)\n#define GET_ARP_OPER(_arp)\tBE_BITS_TO_2BYTE(((u8 *)(_arp)) + 6, 0, 16)\n\n#define SET_ARP_HTYPE(_arp, _val)\tSET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 0, 0, 16, _val)\n#define SET_ARP_PTYPE(_arp, _val)\tSET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 2, 0, 16, _val)\n#define SET_ARP_HLEN(_arp, _val)\tSET_BITS_TO_BE_1BYTE(((u8 *)(_arp)) + 4, 0, 8, _val)\n#define SET_ARP_PLEN(_arp, _val)\tSET_BITS_TO_BE_1BYTE(((u8 *)(_arp)) + 5, 0, 8, _val)\n#define SET_ARP_OPER(_arp, _val)\tSET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 6, 0, 16, _val)\n\n#define ARP_SHA(_arp, _hlen, _plen)\t(((u8 *)(_arp)) + 8)\n#define ARP_SPA(_arp, _hlen, _plen)\t(((u8 *)(_arp)) + 8 + (_hlen))\n#define ARP_THA(_arp, _hlen, _plen)\t(((u8 *)(_arp)) + 8 + (_hlen) + (_plen))\n#define ARP_TPA(_arp, _hlen, _plen)\t(((u8 *)(_arp)) + 8 + 2 * (_hlen) + (_plen))\n\n#define ARP_SENDER_MAC_ADDR(_arp)\tARP_SHA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)\n#define ARP_SENDER_IP_ADDR(_arp)\tARP_SPA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)\n#define ARP_TARGET_MAC_ADDR(_arp)\tARP_THA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)\n#define ARP_TARGET_IP_ADDR(_arp)\tARP_TPA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)\n\n#define GET_ARP_SENDER_MAC_ADDR(_arp, _val)\t_rtw_memcpy(_val, ARP_SENDER_MAC_ADDR(_arp), ETH_ALEN)\n#define GET_ARP_SENDER_IP_ADDR(_arp, _val)\t_rtw_memcpy(_val, ARP_SENDER_IP_ADDR(_arp), RTW_IP_ADDR_LEN)\n#define GET_ARP_TARGET_MAC_ADDR(_arp, _val)\t_rtw_memcpy(_val, ARP_TARGET_MAC_ADDR(_arp), ETH_ALEN)\n#define GET_ARP_TARGET_IP_ADDR(_arp, _val)\t_rtw_memcpy(_val, ARP_TARGET_IP_ADDR(_arp), RTW_IP_ADDR_LEN)\n\n#define SET_ARP_SENDER_MAC_ADDR(_arp, _val)\t_rtw_memcpy(ARP_SENDER_MAC_ADDR(_arp), _val, ETH_ALEN)\n#define SET_ARP_SENDER_IP_ADDR(_arp, _val)\t_rtw_memcpy(ARP_SENDER_IP_ADDR(_arp), _val, RTW_IP_ADDR_LEN)\n#define SET_ARP_TARGET_MAC_ADDR(_arp, _val)\t_rtw_memcpy(ARP_TARGET_MAC_ADDR(_arp), _val, ETH_ALEN)\n#define SET_ARP_TARGET_IP_ADDR(_arp, _val)\t_rtw_memcpy(ARP_TARGET_IP_ADDR(_arp), _val, RTW_IP_ADDR_LEN)\n\nvoid dump_arp_pkt(void *sel, u8 *da, u8 *sa, u8 *arp, bool tx);\n\n#define IPV4_SRC(_iphdr)\t\t\t(((u8 *)(_iphdr)) + 12)\n#define IPV4_DST(_iphdr)\t\t\t(((u8 *)(_iphdr)) + 16)\n#define GET_IPV4_IHL(_iphdr)\t\tBE_BITS_TO_1BYTE(((u8 *)(_iphdr)) + 0, 0, 4)\n#define GET_IPV4_PROTOCOL(_iphdr)\tBE_BITS_TO_1BYTE(((u8 *)(_iphdr)) + 9, 0, 8)\n#define GET_IPV4_SRC(_iphdr)\t\tBE_BITS_TO_4BYTE(((u8 *)(_iphdr)) + 12, 0, 32)\n#define GET_IPV4_DST(_iphdr)\t\tBE_BITS_TO_4BYTE(((u8 *)(_iphdr)) + 16, 0, 32)\n\n#define GET_UDP_SRC(_udphdr)\t\t\tBE_BITS_TO_2BYTE(((u8 *)(_udphdr)) + 0, 0, 16)\n#define GET_UDP_DST(_udphdr)\t\t\tBE_BITS_TO_2BYTE(((u8 *)(_udphdr)) + 2, 0, 16)\n\n#define TCP_SRC(_tcphdr)\t\t\t\t(((u8 *)(_tcphdr)) + 0)\n#define TCP_DST(_tcphdr)\t\t\t\t(((u8 *)(_tcphdr)) + 2)\n#define GET_TCP_SRC(_tcphdr)\t\t\tBE_BITS_TO_2BYTE(((u8 *)(_tcphdr)) + 0, 0, 16)\n#define GET_TCP_DST(_tcphdr)\t\t\tBE_BITS_TO_2BYTE(((u8 *)(_tcphdr)) + 2, 0, 16)\n#define GET_TCP_SEQ(_tcphdr)\t\t\tBE_BITS_TO_4BYTE(((u8 *)(_tcphdr)) + 4, 0, 32)\n#define GET_TCP_ACK_SEQ(_tcphdr)\t\tBE_BITS_TO_4BYTE(((u8 *)(_tcphdr)) + 8, 0, 32)\n#define GET_TCP_DOFF(_tcphdr)\t\t\tBE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 12, 4, 4)\n#define GET_TCP_FIN(_tcphdr)\t\t\tBE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 0, 1)\n#define GET_TCP_SYN(_tcphdr)\t\t\tBE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 1, 1)\n#define GET_TCP_RST(_tcphdr)\t\t\tBE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 2, 1)\n#define GET_TCP_PSH(_tcphdr)\t\t\tBE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 3, 1)\n#define GET_TCP_ACK(_tcphdr)\t\t\tBE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 4, 1)\n#define GET_TCP_URG(_tcphdr)\t\t\tBE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 5, 1)\n#define GET_TCP_ECE(_tcphdr)\t\t\tBE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 6, 1)\n#define GET_TCP_CWR(_tcphdr)\t\t\tBE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 7, 1)\n\n#endif /* __RTL871X_MLME_H_ */\n"
  },
  {
    "path": "include/rtw_mlme_ext.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_MLME_EXT_H_\n#define __RTW_MLME_EXT_H_\n\n\n/*\tCommented by Albert 20101105\n *\tIncrease the SURVEY_TO value from 100 to 150  ( 100ms to 150ms )\n *\tThe Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request.\n *\tSo, this driver tried to extend the dwell time for each scanning channel.\n *\tThis will increase the chance to receive the probe response from SoftAP. */\n#define SURVEY_TO\t\t(100)\n\n#define REAUTH_TO\t\t(300) /* (50) */\n#define REASSOC_TO\t\t(300) /* (50) */\n/* #define DISCONNECT_TO\t(3000) */\n#define ADDBA_TO\t\t\t(2000)\n\n#define LINKED_TO (1) /* unit:2 sec, 1x2 = 2 sec */\n\n#define REAUTH_LIMIT\t(4)\n#define REASSOC_LIMIT\t(4)\n#define READDBA_LIMIT\t(2)\n\n#ifdef CONFIG_GSPI_HCI\n\t#define ROAMING_LIMIT\t5\n#else\n\t#define ROAMING_LIMIT\t8\n#endif\n/* #define\tIOCMD_REG0\t\t0x10250370 */\n/* #define\tIOCMD_REG1\t\t0x10250374 */\n/* #define\tIOCMD_REG2\t\t0x10250378 */\n\n/* #define\tFW_DYNAMIC_FUN_SWITCH\t0x10250364 */\n\n/* #define\tWRITE_BB_CMD\t\t0xF0000001 */\n/* #define\tSET_CHANNEL_CMD\t0xF3000000 */\n/* #define\tUPDATE_RA_CMD\t0xFD0000A2 */\n\n#define _HW_STATE_NOLINK_\t\t0x00\n#define _HW_STATE_ADHOC_\t\t0x01\n#define _HW_STATE_STATION_\t0x02\n#define _HW_STATE_AP_\t\t\t0x03\n#define _HW_STATE_MONITOR_ 0x04\n\n\n#define\t\t_1M_RATE_\t0\n#define\t\t_2M_RATE_\t1\n#define\t\t_5M_RATE_\t2\n#define\t\t_11M_RATE_\t3\n#define\t\t_6M_RATE_\t4\n#define\t\t_9M_RATE_\t5\n#define\t\t_12M_RATE_\t6\n#define\t\t_18M_RATE_\t7\n#define\t\t_24M_RATE_\t8\n#define\t\t_36M_RATE_\t9\n#define\t\t_48M_RATE_\t10\n#define\t\t_54M_RATE_\t11\n\n/********************************************************\nMCS rate definitions\n*********************************************************/\n#define MCS_RATE_1R\t(0x000000ff)\n#define MCS_RATE_2R\t(0x0000ffff)\n#define MCS_RATE_3R\t(0x00ffffff)\n#define MCS_RATE_4R\t(0xffffffff)\n#define MCS_RATE_2R_13TO15_OFF\t(0x00001fff)\n\n\nextern unsigned char RTW_WPA_OUI[];\nextern unsigned char WMM_OUI[];\nextern unsigned char WPS_OUI[];\nextern unsigned char WFD_OUI[];\nextern unsigned char P2P_OUI[];\n\nextern unsigned char WMM_INFO_OUI[];\nextern unsigned char WMM_PARA_OUI[];\n\ntypedef struct _RT_CHANNEL_PLAN {\n\tunsigned char\tChannel[MAX_CHANNEL_NUM];\n\tunsigned char\tLen;\n} RT_CHANNEL_PLAN, *PRT_CHANNEL_PLAN;\n\nenum Associated_AP {\n\tatherosAP\t= 0,\n\tbroadcomAP\t= 1,\n\tciscoAP\t\t= 2,\n\tmarvellAP\t= 3,\n\tralinkAP\t= 4,\n\trealtekAP\t= 5,\n\tairgocapAP\t= 6,\n\tunknownAP\t= 7,\n\tmaxAP,\n};\n\ntypedef enum _HT_IOT_PEER {\n\tHT_IOT_PEER_UNKNOWN\t\t\t= 0,\n\tHT_IOT_PEER_REALTEK\t\t\t= 1,\n\tHT_IOT_PEER_REALTEK_92SE\t\t= 2,\n\tHT_IOT_PEER_BROADCOM\t\t= 3,\n\tHT_IOT_PEER_RALINK\t\t\t= 4,\n\tHT_IOT_PEER_ATHEROS\t\t\t= 5,\n\tHT_IOT_PEER_CISCO\t\t\t\t= 6,\n\tHT_IOT_PEER_MERU\t\t\t\t= 7,\n\tHT_IOT_PEER_MARVELL\t\t\t= 8,\n\tHT_IOT_PEER_REALTEK_SOFTAP \t= 9,/* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */\n\tHT_IOT_PEER_SELF_SOFTAP \t\t= 10, /* Self is SoftAP */\n\tHT_IOT_PEER_AIRGO\t\t\t\t= 11,\n\tHT_IOT_PEER_INTEL\t\t\t\t= 12,\n\tHT_IOT_PEER_RTK_APCLIENT\t\t= 13,\n\tHT_IOT_PEER_REALTEK_81XX\t\t= 14,\n\tHT_IOT_PEER_REALTEK_WOW\t\t= 15,\n\tHT_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 16,\n\tHT_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 17,\n\tHT_IOT_PEER_MAX\t\t\t\t= 18\n} HT_IOT_PEER_E, *PHTIOT_PEER_E;\n\n\ntypedef enum _RT_HT_INF0_CAP {\n\tRT_HT_CAP_USE_TURBO_AGGR = 0x01,\n\tRT_HT_CAP_USE_LONG_PREAMBLE = 0x02,\n\tRT_HT_CAP_USE_AMPDU = 0x04,\n\tRT_HT_CAP_USE_WOW = 0x8,\n\tRT_HT_CAP_USE_SOFTAP = 0x10,\n\tRT_HT_CAP_USE_92SE = 0x20,\n\tRT_HT_CAP_USE_88C_92C = 0x40,\n\tRT_HT_CAP_USE_AP_CLIENT_MODE = 0x80,\t/* AP team request to reserve this bit, by Emily */\n} RT_HT_INF0_CAPBILITY, *PRT_HT_INF0_CAPBILITY;\n\ntypedef enum _RT_HT_INF1_CAP {\n\tRT_HT_CAP_USE_VIDEO_CLIENT = 0x01,\n\tRT_HT_CAP_USE_JAGUAR_BCUT = 0x02,\n\tRT_HT_CAP_USE_JAGUAR_CCUT = 0x04,\n} RT_HT_INF1_CAPBILITY, *PRT_HT_INF1_CAPBILITY;\n\nstruct mlme_handler {\n\tunsigned int   num;\n\tchar *str;\n\tunsigned int (*func)(_adapter *padapter, union recv_frame *precv_frame);\n};\n\nstruct action_handler {\n\tunsigned int   num;\n\tchar *str;\n\tunsigned int (*func)(_adapter *padapter, union recv_frame *precv_frame);\n};\n\nenum SCAN_STATE {\n\tSCAN_DISABLE = 0,\n\tSCAN_START = 1,\n\tSCAN_PS_ANNC_WAIT = 2,\n\tSCAN_ENTER = 3,\n\tSCAN_PROCESS = 4,\n\n\t/* backop */\n\tSCAN_BACKING_OP = 5,\n\tSCAN_BACK_OP = 6,\n\tSCAN_LEAVING_OP = 7,\n\tSCAN_LEAVE_OP = 8,\n\n\t/* SW antenna diversity (before linked) */\n\tSCAN_SW_ANTDIV_BL = 9,\n\n\t/* legacy p2p */\n\tSCAN_TO_P2P_LISTEN = 10,\n\tSCAN_P2P_LISTEN = 11,\n\n\tSCAN_COMPLETE = 12,\n\tSCAN_STATE_MAX,\n};\n\nconst char *scan_state_str(u8 state);\n\nenum ss_backop_flag {\n\tSS_BACKOP_EN = BIT0, /* backop when linked */\n\tSS_BACKOP_EN_NL = BIT1, /* backop even when no linked */\n\n\tSS_BACKOP_PS_ANNC = BIT4,\n\tSS_BACKOP_TX_RESUME = BIT5,\n};\n\nstruct ss_res {\n\tu8 state;\n\tu8 next_state; /* will set to state on next cmd hdl */\n\tint\tbss_cnt;\n\tint\tchannel_idx;\n#ifdef CONFIG_DFS\n\tu8 dfs_ch_ssid_scan;\n#endif\n\tint\tscan_mode;\n\tu16 scan_ch_ms;\n\tu32 scan_timeout_ms;\n\tu8 rx_ampdu_accept;\n\tu8 rx_ampdu_size;\n\tu8 igi_scan;\n\tu8 igi_before_scan; /* used for restoring IGI value without enable DIG & FA_CNT */\n#ifdef CONFIG_SCAN_BACKOP\n\tu8 backop_flags_sta; /* policy for station mode*/\n\t#ifdef CONFIG_AP_MODE\n\tu8 backop_flags_ap; /* policy for ap mode */\n\t#endif\n\t#ifdef CONFIG_RTW_MESH\n\tu8 backop_flags_mesh; /* policy for mesh mode */\n\t#endif\n\tu8 backop_flags; /* per backop runtime decision */\n\tu8 scan_cnt;\n\tu8 scan_cnt_max;\n\tsystime backop_time; /* the start time of backop */\n\tu16 backop_ms;\n#endif\n#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)\n\tu8 is_sw_antdiv_bl_scan;\n#endif\n\tu8 ssid_num;\n\tu8 ch_num;\n\tNDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT];\n\tstruct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT];\n\n\tu32 token; \t/* 0: use to identify caller */\n\tu16 duration;\t/* 0: use default */\n\tu8 igi;\t\t/* 0: use defalut */\n\tu8 bw;\t\t/* 0: use default */\n};\n\n/* #define AP_MODE\t\t\t\t0x0C */\n/* #define STATION_MODE\t0x08 */\n/* #define AD_HOC_MODE\t\t0x04 */\n/* #define NO_LINK_MODE\t0x00 */\n\n#define\tWIFI_FW_NULL_STATE\t\t\t_HW_STATE_NOLINK_\n#define\tWIFI_FW_STATION_STATE\t\t_HW_STATE_STATION_\n#define\tWIFI_FW_AP_STATE\t\t\t\t_HW_STATE_AP_\n#define\tWIFI_FW_ADHOC_STATE\t\t\t_HW_STATE_ADHOC_\n\n#define WIFI_FW_PRE_LINK\t\t\t0x00000800\n#define\tWIFI_FW_AUTH_NULL\t\t\t0x00000100\n#define\tWIFI_FW_AUTH_STATE\t\t\t0x00000200\n#define\tWIFI_FW_AUTH_SUCCESS\t\t\t0x00000400\n\n#define\tWIFI_FW_ASSOC_STATE\t\t\t0x00002000\n#define\tWIFI_FW_ASSOC_SUCCESS\t\t0x00004000\n\n#define\tWIFI_FW_LINKING_STATE\t\t(WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE | WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE)\n\n#ifdef CONFIG_TDLS\nenum TDLS_option {\n\tTDLS_ESTABLISHED = 1,\n\tTDLS_ISSUE_PTI,\n\tTDLS_CH_SW_RESP,\n\tTDLS_CH_SW_PREPARE,\n\tTDLS_CH_SW_START,\n\tTDLS_CH_SW_TO_OFF_CHNL,\n\tTDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED,\n\tTDLS_CH_SW_TO_BASE_CHNL,\n\tTDLS_CH_SW_END_TO_BASE_CHNL,\n\tTDLS_CH_SW_END,\n\tTDLS_RS_RCR,\n\tTDLS_TEARDOWN_STA,\n\tTDLS_TEARDOWN_STA_NO_WAIT,\n\tTDLS_TEARDOWN_STA_LOCALLY,\n\tTDLS_TEARDOWN_STA_LOCALLY_POST,\n\tmaxTDLS,\n};\n\n#endif /* CONFIG_TDLS */\n\n#if (KERNEL_VERSION(3, 8, 0) > LINUX_VERSION_CODE)\n#define NL80211_AUTHTYPE_SAE (__NL80211_AUTHTYPE_NUM + 1)\n#endif\n\n/*\n * Usage:\n * When one iface acted as AP mode and the other iface is STA mode and scanning,\n * it should switch back to AP's operating channel periodically.\n * Parameters info:\n * When the driver scanned RTW_SCAN_NUM_OF_CH channels, it would switch back to AP's operating channel for\n * RTW_BACK_OP_CH_MS milliseconds.\n * Example:\n * For chip supports 2.4G + 5GHz and AP mode is operating in channel 1,\n * RTW_SCAN_NUM_OF_CH is 8, RTW_BACK_OP_CH_MS is 300\n * When it's STA mode gets set_scan command,\n * it would\n * 1. Doing the scan on channel 1.2.3.4.5.6.7.8\n * 2. Back to channel 1 for 300 milliseconds\n * 3. Go through doing site survey on channel 9.10.11.36.40.44.48.52\n * 4. Back to channel 1 for 300 milliseconds\n * 5. ... and so on, till survey done.\n */\n#if defined(CONFIG_ATMEL_RC_PATCH)\n\t#define RTW_SCAN_NUM_OF_CH 2\n\t#define RTW_BACK_OP_CH_MS 200\n#else\n\t#define RTW_SCAN_NUM_OF_CH 3\n\t#define RTW_BACK_OP_CH_MS 400\n#endif\n\n#define RTW_IP_ADDR_LEN 4\n#define RTW_IPv6_ADDR_LEN 16\n\nstruct mlme_ext_info {\n\tu32\tstate;\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\tu8\thw_media_state;\n#endif\n\tu32\treauth_count;\n\tu32\treassoc_count;\n\tu32\tlink_count;\n\tu32\tauth_seq;\n\tu32\tauth_algo;\t/* 802.11 auth, could be open, shared, auto */\n\tu16 auth_status;\n\tu32\tauthModeToggle;\n\tu32\tenc_algo;/* encrypt algorithm; */\n\tu32\tkey_index;\t/* this is only valid for legendary wep, 0~3 for key id. */\n\tu32\tiv;\n\tu8\tchg_txt[128];\n\tu16\taid;\n\tu16\tbcn_interval;\n\tu16\tcapability;\n\tu8\tassoc_AP_vendor;\n\tu8\tslotTime;\n\tu8\tpreamble_mode;\n\tu8\tWMM_enable;\n\tu8\tERP_enable;\n\tu8\tERP_IE;\n\tu8\tHT_enable;\n\tu8\tHT_caps_enable;\n\tu8\tHT_info_enable;\n\tu8\tHT_protection;\n\tu8\tturboMode_cts2self;\n\tu8\tturboMode_rtsen;\n\tu8\tSM_PS;\n\tu8\tagg_enable_bitmap;\n\tu8\tADDBA_retry_count;\n\tu8\tcandidate_tid_bitmap;\n\tu8\tdialogToken;\n\t/* Accept ADDBA Request */\n\tBOOLEAN bAcceptAddbaReq;\n\tu8\tbwmode_updated;\n\tu8\thidden_ssid_mode;\n\tu8\tVHT_enable;\n\n\tu8 ip_addr[RTW_IP_ADDR_LEN];\n\tu8 ip6_addr[RTW_IPv6_ADDR_LEN];\n\n\tstruct ADDBA_request\t\tADDBA_req;\n\tstruct WMM_para_element\tWMM_param;\n\tstruct HT_caps_element\tHT_caps;\n\tstruct HT_info_element\t\tHT_info;\n\tWLAN_BSSID_EX\t\t\tnetwork;/* join network or bss_network, if in ap mode, it is the same to cur_network.network */\n#ifdef ROKU_PRIVATE\n\t/*infra mode, store supported rates from AssocRsp*/\n\tNDIS_802_11_RATES_EX\tSupportedRates_infra_ap;\n\tu8 ht_vht_received;/*ht_vht_received used to show debug msg BIT(0):HT BIT(1):VHT */\n#endif /* ROKU_PRIVATE */\n};\n\n/* The channel information about this channel including joining, scanning, and power constraints. */\ntypedef struct _RT_CHANNEL_INFO {\n\tu8\t\t\t\tChannelNum;\t\t/* The channel number. */\n\tRT_SCAN_TYPE\tScanType;\t\t/* Scan type such as passive or active scan. */\n\t/* u16\t\t\t\tScanPeriod;\t\t */ /* Listen time in millisecond in this channel. */\n\t/* s32\t\t\t\tMaxTxPwrDbm;\t */ /* Max allowed tx power. */\n\t/* u32\t\t\t\tExInfo;\t\t\t */ /* Extended Information for this channel. */\n#ifdef CONFIG_FIND_BEST_CHANNEL\n\tu32\t\t\t\trx_count;\n#endif\n#ifdef CONFIG_DFS\n\t#ifdef CONFIG_DFS_MASTER\n\tsystime non_ocp_end_time;\n\t#endif\n\tu8 hidden_bss_cnt; /* per scan count */\n#endif\n} RT_CHANNEL_INFO, *PRT_CHANNEL_INFO;\n\n#define CAC_TIME_MS (60*1000)\n#define CAC_TIME_CE_MS (10*60*1000)\n#define NON_OCP_TIME_MS (30*60*1000)\n\n#if CONFIG_TXPWR_LIMIT\nvoid rtw_txpwr_init_regd(struct rf_ctl_t *rfctl);\n#endif\nvoid rtw_rfctl_init(_adapter *adapter);\nvoid rtw_rfctl_deinit(_adapter *adapter);\n\n#ifdef CONFIG_DFS_MASTER\nstruct rf_ctl_t;\n#define CH_IS_NON_OCP(rt_ch_info) (rtw_time_after((rt_ch_info)->non_ocp_end_time, rtw_get_current_time()))\nbool rtw_is_cac_reset_needed(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset);\nbool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset);\nbool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl);\nbool rtw_rfctl_is_tx_blocked_by_ch_waiting(struct rf_ctl_t *rfctl);\nbool rtw_chset_is_chbw_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset);\nbool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch);\nvoid rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset);\nvoid rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms);\nu32 rtw_get_ch_waiting_ms(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms);\nvoid rtw_reset_cac(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset);\nu32 rtw_force_stop_cac(struct rf_ctl_t *rfctl, u32 timeout_ms);\n#else\n#define CH_IS_NON_OCP(rt_ch_info) 0\n#define rtw_chset_is_chbw_non_ocp(ch_set, ch, bw, offset) _FALSE\n#define rtw_chset_is_ch_non_ocp(ch_set, ch) _FALSE\n#define rtw_rfctl_is_tx_blocked_by_ch_waiting(rfctl) _FALSE\n#endif\n\nenum {\n\tRTW_CHF_2G = BIT0,\n\tRTW_CHF_5G = BIT1,\n\tRTW_CHF_DFS = BIT2,\n\tRTW_CHF_LONG_CAC = BIT3,\n\tRTW_CHF_NON_DFS = BIT4,\n\tRTW_CHF_NON_LONG_CAC = BIT5,\n\tRTW_CHF_NON_OCP = BIT6,\n};\n\nbool rtw_choose_shortest_waiting_ch(struct rf_ctl_t *rfctl, u8 sel_ch, u8 max_bw\n\t, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset\n\t, u8 d_flags, u8 cur_ch, u8 same_band_prefer, u8 mesh_only);\n\nvoid dump_chset(void *sel, RT_CHANNEL_INFO *ch_set);\nvoid dump_cur_chset(void *sel, struct rf_ctl_t *rfctl);\n\nint rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch);\nu8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset);\nvoid rtw_chset_sync_chbw(RT_CHANNEL_INFO *ch_set, u8 *req_ch, u8 *req_bw, u8 *req_offset\n\t, u8 *g_ch, u8 *g_bw, u8 *g_offset);\n\nbool rtw_mlme_band_check(_adapter *adapter, const u32 ch);\n\n\nenum {\n\tBAND_24G = BIT0,\n\tBAND_5G = BIT1,\n};\nvoid RTW_SET_SCAN_BAND_SKIP(_adapter *padapter, int skip_band);\nvoid RTW_CLR_SCAN_BAND_SKIP(_adapter *padapter, int skip_band);\nint RTW_GET_SCAN_BAND_SKIP(_adapter *padapter);\n\nbool rtw_mlme_ignore_chan(_adapter *adapter, const u32 ch);\n\n/* P2P_MAX_REG_CLASSES - Maximum number of regulatory classes */\n#define P2P_MAX_REG_CLASSES 10\n\n/* P2P_MAX_REG_CLASS_CHANNELS - Maximum number of channels per regulatory class */\n#define P2P_MAX_REG_CLASS_CHANNELS 20\n\n/* struct p2p_channels - List of supported channels */\nstruct p2p_channels {\n\t/* struct p2p_reg_class - Supported regulatory class */\n\tstruct p2p_reg_class {\n\t\t/* reg_class - Regulatory class (IEEE 802.11-2007, Annex J) */\n\t\tu8 reg_class;\n\n\t\t/* channel - Supported channels */\n\t\tu8 channel[P2P_MAX_REG_CLASS_CHANNELS];\n\n\t\t/* channels - Number of channel entries in use */\n\t\tsize_t channels;\n\t} reg_class[P2P_MAX_REG_CLASSES];\n\n\t/* reg_classes - Number of reg_class entries in use */\n\tsize_t reg_classes;\n};\n\nstruct p2p_oper_class_map {\n\tenum hw_mode {IEEE80211G, IEEE80211A} mode;\n\tu8 op_class;\n\tu8 min_chan;\n\tu8 max_chan;\n\tu8 inc;\n\tenum { BW20, BW40PLUS, BW40MINUS } bw;\n};\n\nstruct mlme_ext_priv {\n\t_adapter\t*padapter;\n\tu8\tmlmeext_init;\n\tATOMIC_T\t\tevent_seq;\n\tu16\tmgnt_seq;\n#ifdef CONFIG_IEEE80211W\n\tu16\tsa_query_seq;\n#endif\n\t/* struct fw_priv \tfwpriv; */\n\n\tunsigned char\tcur_channel;\n\tunsigned char\tcur_bwmode;\n\tunsigned char\tcur_ch_offset;/* PRIME_CHNL_OFFSET */\n\tunsigned char\tcur_wireless_mode;\t/* NETWORK_TYPE */\n\n\tunsigned char\tbasicrate[NumRates];\n\tunsigned char\tdatarate[NumRates];\n#ifdef CONFIG_80211N_HT\n\tunsigned char default_supported_mcs_set[16];\n#endif\n\n\tstruct ss_res\t\tsitesurvey_res;\n\tstruct mlme_ext_info\tmlmext_info;/* for sta/adhoc mode, including current scanning/connecting/connected related info.\n                                                      * for ap mode, network includes ap's cap_info */\n\t_timer\t\tsurvey_timer;\n\t_timer\t\tlink_timer;\n\n#ifdef CONFIG_RTW_REPEATER_SON\n\t_timer\t\trson_scan_timer;\n#endif\n#ifdef CONFIG_RTW_80211R\n\t_timer\t\tft_link_timer;\n\t_timer\t\tft_roam_timer;\n#endif\n\n\tsystime last_scan_time;\n\tu8\tscan_abort;\n\tu8 join_abort;\n\tu8\ttx_rate; /* TXRATE when USERATE is set. */\n\n\tu32\tretry; /* retry for issue probereq */\n\n\tu64 TSFValue;\n\tu32 bcn_cnt;\n\tu32 last_bcn_cnt;\n\tu8 cur_bcn_cnt;/*2s*/\n\tu8 dtim;/*DTIM Period*/\n#ifdef DBG_RX_BCN\n\tu8 tim[4];\n#endif\n#ifdef CONFIG_BCN_RECV_TIME\n\tu16 bcn_rx_time;\n#endif\n#ifdef CONFIG_AP_MODE\n\tunsigned char bstart_bss;\n#endif\n\n#ifdef CONFIG_80211D\n\tu8 update_channel_plan_by_ap_done;\n#endif\n\t/* recv_decache check for Action_public frame */\n\tu8 action_public_dialog_token;\n\tu16\t action_public_rxseq;\n\n\t/* #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK */\n\tu8 active_keep_alive_check;\n\t/* #endif */\n#ifdef DBG_FIXED_CHAN\n\tu8 fixed_chan;\n#endif\n\n\tu8 tsf_update_required:1;\n\tu8 en_hw_update_tsf:1; /* set hw sync bcn tsf register or not */\n\tsystime tsf_update_pause_stime;\n\tu8 tsf_update_pause_factor; /* num of bcn intervals to stay TSF update pause status */\n\tu8 tsf_update_restore_factor; /* num of bcn interval to stay TSF update restore status */\n#ifdef CONFIG_SUPPORT_STATIC_SMPS\n\tu8 ssmps_en;\n\tu16 ssmps_tx_tp_th;/*Mbps*/\n\tu16 ssmps_rx_tp_th;/*Mbps*/\n\t#ifdef DBG_STATIC_SMPS\n\tu8 ssmps_test;\n\tu8 ssmps_test_en;\n\t#endif\n#endif\n#ifdef CONFIG_CTRL_TXSS_BY_TP\n\tu8 txss_ctrl_en;\n\tu16 txss_tp_th;/*Mbps*/\n\tu8 txss_tp_chk_cnt;/*unit 2s*/\n\tbool txss_1ss;\n\tu8 txss_momi_type_bk;\n#endif\n};\n\nstruct support_rate_handler {\n\tu8 rate;\n\tbool basic;\n\tbool existence;\n};\n\nstatic inline u8 check_mlmeinfo_state(struct mlme_ext_priv *plmeext, sint state)\n{\n\tif ((plmeext->mlmext_info.state & 0x03) == state)\n\t\treturn _TRUE;\n\n\treturn _FALSE;\n}\n\nvoid sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state);\n\n#define mlmeext_msr(mlmeext) ((mlmeext)->mlmext_info.state & 0x03)\n#define mlmeext_scan_state(mlmeext) ((mlmeext)->sitesurvey_res.state)\n#define mlmeext_scan_state_str(mlmeext) scan_state_str((mlmeext)->sitesurvey_res.state)\n#define mlmeext_chk_scan_state(mlmeext, _state) ((mlmeext)->sitesurvey_res.state == (_state))\n#define mlmeext_set_scan_state(mlmeext, _state) \\\n\tdo { \\\n\t\t((mlmeext)->sitesurvey_res.state = (_state)); \\\n\t\t((mlmeext)->sitesurvey_res.next_state = (_state)); \\\n\t\trtw_mi_update_iface_status(&((container_of(mlmeext, _adapter, mlmeextpriv)->mlmepriv)), 0); \\\n\t\t/* RTW_INFO(\"set_scan_state:%s\\n\", scan_state_str(_state)); */ \\\n\t\tsitesurvey_set_offch_state(container_of(mlmeext, _adapter, mlmeextpriv), _state); \\\n\t} while (0)\n\n#define mlmeext_scan_next_state(mlmeext) ((mlmeext)->sitesurvey_res.next_state)\n#define mlmeext_set_scan_next_state(mlmeext, _state) \\\n\tdo { \\\n\t\t((mlmeext)->sitesurvey_res.next_state = (_state)); \\\n\t\t/* RTW_INFO(\"set_scan_next_state:%s\\n\", scan_state_str(_state)); */ \\\n\t} while (0)\n\n#ifdef CONFIG_SCAN_BACKOP\n#define mlmeext_scan_backop_flags(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags)\n#define mlmeext_chk_scan_backop_flags(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags & (flags))\n#define mlmeext_assign_scan_backop_flags(mlmeext, flags) \\\n\tdo { \\\n\t\t((mlmeext)->sitesurvey_res.backop_flags = (flags)); \\\n\t\tRTW_INFO(\"assign_scan_backop_flags:0x%02x\\n\", (mlmeext)->sitesurvey_res.backop_flags); \\\n\t} while (0)\n\n#define mlmeext_scan_backop_flags_sta(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_sta)\n#define mlmeext_chk_scan_backop_flags_sta(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_sta & (flags))\n#define mlmeext_assign_scan_backop_flags_sta(mlmeext, flags) \\\n\tdo { \\\n\t\t((mlmeext)->sitesurvey_res.backop_flags_sta = (flags)); \\\n\t} while (0)\n#else\n#define mlmeext_scan_backop_flags(mlmeext) (0)\n#define mlmeext_chk_scan_backop_flags(mlmeext, flags) (0)\n#define mlmeext_assign_scan_backop_flags(mlmeext, flags) do {} while (0)\n\n#define mlmeext_scan_backop_flags_sta(mlmeext) (0)\n#define mlmeext_chk_scan_backop_flags_sta(mlmeext, flags) (0)\n#define mlmeext_assign_scan_backop_flags_sta(mlmeext, flags) do {} while (0)\n#endif /* CONFIG_SCAN_BACKOP */\n\n#if defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE)\n#define mlmeext_scan_backop_flags_ap(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_ap)\n#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_ap & (flags))\n#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) \\\n\tdo { \\\n\t\t((mlmeext)->sitesurvey_res.backop_flags_ap = (flags)); \\\n\t} while (0)\n#else\n#define mlmeext_scan_backop_flags_ap(mlmeext) (0)\n#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) (0)\n#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) do {} while (0)\n#endif /* defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE) */\n\n#if defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_RTW_MESH)\n#define mlmeext_scan_backop_flags_mesh(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_mesh)\n#define mlmeext_chk_scan_backop_flags_mesh(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_mesh & (flags))\n#define mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags) \\\n\tdo { \\\n\t\t((mlmeext)->sitesurvey_res.backop_flags_mesh = (flags)); \\\n\t} while (0)\n#else\n#define mlmeext_scan_backop_flags_mesh(mlmeext) (0)\n#define mlmeext_chk_scan_backop_flags_mesh(mlmeext, flags) (0)\n#define mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags) do {} while (0)\n#endif /* defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_RTW_MESH) */\n\nu32 rtw_scan_timeout_decision(_adapter *padapter);\n\nvoid init_mlme_default_rate_set(_adapter *padapter);\nint init_mlme_ext_priv(_adapter *padapter);\nint init_hw_mlme_ext(_adapter *padapter);\nvoid free_mlme_ext_priv(struct mlme_ext_priv *pmlmeext);\nextern struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv);\nstruct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv);\n\n/* void fill_fwpriv(_adapter * padapter, struct fw_priv *pfwpriv); */\nu8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen);\nvoid get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len);\nvoid set_mcs_rate_by_mask(u8 *mcs_set, u32 mask);\nvoid UpdateBrateTbl(_adapter *padapter, u8 *mBratesOS);\nvoid UpdateBrateTblForSoftAP(u8 *bssrateset, u32 bssratelen);\nvoid change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch);\n\nvoid Set_MSR(_adapter *padapter, u8 type);\n\nvoid rtw_set_external_auth_status(_adapter *padapter, const void *data, int len);\n\nu8 rtw_get_oper_ch(_adapter *adapter);\nvoid rtw_set_oper_ch(_adapter *adapter, u8 ch);\nu8 rtw_get_oper_bw(_adapter *adapter);\nvoid rtw_set_oper_bw(_adapter *adapter, u8 bw);\nu8 rtw_get_oper_choffset(_adapter *adapter);\nvoid rtw_set_oper_choffset(_adapter *adapter, u8 offset);\nu8\trtw_get_center_ch(u8 channel, u8 chnl_bw, u8 chnl_offset);\nsystime rtw_get_on_oper_ch_time(_adapter *adapter);\nsystime rtw_get_on_cur_ch_time(_adapter *adapter);\n\nu8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset);\n\nvoid set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode);\n\nunsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval);\n\nvoid _clear_cam_entry(_adapter *padapter, u8 entry);\nvoid write_cam_from_cache(_adapter *adapter, u8 id);\nvoid rtw_sec_cam_swap(_adapter *adapter, u8 cam_id_a, u8 cam_id_b);\nvoid rtw_clean_dk_section(_adapter *adapter);\nvoid rtw_clean_hw_dk_cam(_adapter *adapter);\n\n/* modify both HW and cache */\nvoid write_cam(_adapter *padapter, u8 id, u16 ctrl, u8 *mac, u8 *key);\nvoid clear_cam_entry(_adapter *padapter, u8 id);\n\n/* modify cache only */\nvoid write_cam_cache(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key);\nvoid clear_cam_cache(_adapter *adapter, u8 id);\n\nvoid invalidate_cam_all(_adapter *padapter);\n\nvoid flush_all_cam_entry(_adapter *padapter);\n\nBOOLEAN IsLegal5GChannel(PADAPTER Adapter, u8 channel);\n\nvoid site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType);\nu8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid);\nvoid update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, _adapter *padapter, bool update_ie);\n\nu8 *get_my_bssid(WLAN_BSSID_EX *pnetwork);\nu16 get_beacon_interval(WLAN_BSSID_EX *bss);\n\nint is_client_associated_to_ap(_adapter *padapter);\nint is_client_associated_to_ibss(_adapter *padapter);\nint is_IBSS_empty(_adapter *padapter);\n\nunsigned char check_assoc_AP(u8 *pframe, uint len);\nvoid get_assoc_AP_Vendor(char *vendor, u8 assoc_AP_vendor);\n#ifdef CONFIG_RTS_FULL_BW\nvoid rtw_parse_sta_vendor_ie_8812(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len);\n#endif/*CONFIG_RTS_FULL_BW*/\n#ifdef CONFIG_80211AC_VHT\nunsigned char get_vht_mu_bfer_cap(u8 *pframe, uint len);\n#endif\n\nint WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs\tpIE);\n#ifdef CONFIG_WFD\nvoid rtw_process_wfd_ie(_adapter *adapter, u8 *ie, u8 ie_len, const char *tag);\nvoid rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag);\n#endif\nvoid WMMOnAssocRsp(_adapter *padapter);\n\nvoid HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);\n#ifdef ROKU_PRIVATE\nvoid HT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);\n#endif\nvoid HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);\nvoid HTOnAssocRsp(_adapter *padapter);\n\n#ifdef ROKU_PRIVATE\nvoid Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);\nvoid Extended_Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);\n#endif\n\nvoid ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);\nvoid VCS_update(_adapter *padapter, struct sta_info *psta);\nvoid\tupdate_ldpc_stbc_cap(struct sta_info *psta);\n\nbool rtw_validate_value(u16 EID, u8 *p, u16 len);\nbool is_hidden_ssid(char *ssid, int len);\nbool hidden_ssid_ap(WLAN_BSSID_EX *snetwork);\nvoid rtw_absorb_ssid_ifneed(_adapter *padapter, WLAN_BSSID_EX *bssid, u8 *pframe);\nint rtw_get_bcn_keys(ADAPTER *Adapter, u8 *pframe, u32 packet_len,\n\t\tstruct beacon_keys *recv_beacon);\nint validate_beacon_len(u8 *pframe, uint len);\nvoid rtw_dump_bcn_keys(void *sel, struct beacon_keys *recv_beacon);\nint rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len);\nvoid update_beacon_info(_adapter *padapter, u8 *pframe, uint len, struct sta_info *psta);\n#ifdef CONFIG_DFS\nvoid process_csa_ie(_adapter *padapter, u8 *ies, uint ies_len);\n#endif /* CONFIG_DFS */\nvoid update_capinfo(PADAPTER Adapter, u16 updateCap);\nvoid update_wireless_mode(_adapter *padapter);\nvoid update_tx_basic_rate(_adapter *padapter, u8 modulation);\nvoid update_sta_basic_rate(struct sta_info *psta, u8 wireless_mode);\nint rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num);\n\n/* for sta/adhoc mode */\nvoid update_sta_info(_adapter *padapter, struct sta_info *psta);\nunsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz);\nunsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz);\nvoid Update_RA_Entry(_adapter *padapter, struct sta_info *psta);\nvoid set_sta_rate(_adapter *padapter, struct sta_info *psta);\n\nunsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, u8 locally_generated);\n\nunsigned char get_highest_rate_idx(u64 mask);\nunsigned char get_lowest_rate_idx_ex(u64 mask, int start_bit);\n#define get_lowest_rate_idx(mask) get_lowest_rate_idx_ex(mask, 0)\n\nint support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode);\nunsigned int is_ap_in_tkip(_adapter *padapter);\nunsigned int is_ap_in_wep(_adapter *padapter);\nunsigned int should_forbid_n_rate(_adapter *padapter);\n\nvoid parsing_eapol_packet(_adapter *padapter, u8 *key_payload, struct sta_info *psta, u8 trx_type);\n\nbool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap);\nvoid _rtw_camctl_set_flags(_adapter *adapter, u32 flags);\nvoid rtw_camctl_set_flags(_adapter *adapter, u32 flags);\nvoid _rtw_camctl_clr_flags(_adapter *adapter, u32 flags);\nvoid rtw_camctl_clr_flags(_adapter *adapter, u32 flags);\nbool _rtw_camctl_chk_flags(_adapter *adapter, u32 flags);\n\nstruct sec_cam_bmp;\nvoid dump_sec_cam_map(void *sel, struct sec_cam_bmp *map, u8 max_num);\nvoid rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map);\n\nbool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id);\nbool rtw_camid_is_gk(_adapter *adapter, u8 cam_id);\ns16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk);\ns16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, u8 gk, bool *used);\nvoid rtw_camid_free(_adapter *adapter, u8 cam_id);\nu8 rtw_get_sec_camid(_adapter *adapter, u8 max_bk_key_num, u8 *sec_key_id);\n\nstruct macid_bmp;\nstruct macid_ctl_t;\nvoid dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num);\nbool rtw_macid_is_set(struct macid_bmp *map, u8 id);\nvoid rtw_macid_map_clr(struct macid_bmp *map, u8 id);\nbool rtw_macid_is_used(struct macid_ctl_t *macid_ctl, u8 id);\nbool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id);\nu8 rtw_macid_get_iface_bmp(struct macid_ctl_t *macid_ctl, u8 id);\nbool rtw_macid_is_iface_shared(struct macid_ctl_t *macid_ctl, u8 id);\nbool rtw_macid_is_iface_specific(struct macid_ctl_t *macid_ctl, u8 id, _adapter *adapter);\ns8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id);\nvoid rtw_alloc_macid(_adapter *padapter, struct sta_info *psta);\nvoid rtw_release_macid(_adapter *padapter, struct sta_info *psta);\nu8 rtw_search_max_mac_id(_adapter *padapter);\nu8 rtw_macid_ctl_set_h2c_msr(struct macid_ctl_t *macid_ctl, u8 id, u8 h2c_msr);\nvoid rtw_macid_ctl_set_bw(struct macid_ctl_t *macid_ctl, u8 id, u8 bw);\nvoid rtw_macid_ctl_set_vht_en(struct macid_ctl_t *macid_ctl, u8 id, u8 en);\nvoid rtw_macid_ctl_set_rate_bmp0(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp);\nvoid rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp);\nvoid rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3);\nvoid rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl);\nvoid rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl);\nu8 rtw_iface_bcmc_id_get(_adapter *padapter);\nvoid rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id);\n\nbool rtw_bmp_is_set(const u8 *bmp, u8 bmp_len, u8 id);\nvoid rtw_bmp_set(u8 *bmp, u8 bmp_len, u8 id);\nvoid rtw_bmp_clear(u8 *bmp, u8 bmp_len, u8 id);\nbool rtw_bmp_not_empty(const u8 *bmp, u8 bmp_len);\nbool rtw_bmp_not_empty_exclude_bit0(const u8 *bmp, u8 bmp_len);\n\n#ifdef CONFIG_AP_MODE\nbool rtw_tim_map_is_set(_adapter *padapter, const u8 *map, u8 id);\nvoid rtw_tim_map_set(_adapter *padapter, u8 *map, u8 id);\nvoid rtw_tim_map_clear(_adapter *padapter, u8 *map, u8 id);\nbool rtw_tim_map_anyone_be_set(_adapter *padapter, const u8 *map);\nbool rtw_tim_map_anyone_be_set_exclude_aid0(_adapter *padapter, const u8 *map);\n#endif /* CONFIG_AP_MODE */\n\nu32 report_join_res(_adapter *padapter, int aid_res, u16 status);\nvoid report_survey_event(_adapter *padapter, union recv_frame *precv_frame);\nvoid report_surveydone_event(_adapter *padapter);\nu32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, bool enqueue, u8 locally_generated);\nvoid report_add_sta_event(_adapter *padapter, unsigned char *MacAddr);\nbool rtw_port_switch_chk(_adapter *adapter);\nvoid report_wmm_edca_update(_adapter *padapter);\n\nvoid beacon_timing_control(_adapter *padapter);\nu8 chk_bmc_sleepq_cmd(_adapter *padapter);\nextern u8 set_tx_beacon_cmd(_adapter *padapter, u8 flags);\nunsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame);\nvoid update_mgnt_tx_rate(_adapter *padapter, u8 rate);\nvoid update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib);\nvoid update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib);\nvoid update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntframe);\nvoid dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe);\ns32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms);\ns32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntframe);\ns32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms);\n\n#ifdef CONFIG_P2P\nint get_reg_classes_full_count(struct p2p_channels *channel_list);\nvoid issue_probersp_p2p(_adapter *padapter, unsigned char *da);\nvoid issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8 *pdev_raddr);\nvoid issue_p2p_GO_request(_adapter *padapter, u8 *raddr);\nvoid issue_probereq_p2p(_adapter *padapter, u8 *da);\nint issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms);\nvoid issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken, u8 success);\nvoid issue_p2p_invitation_request(_adapter *padapter, u8 *raddr);\n#endif /* CONFIG_P2P */\nvoid issue_beacon(_adapter *padapter, int timeout_ms);\nvoid issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq);\nvoid _issue_assocreq(_adapter *padapter, u8 is_assoc);\nvoid issue_assocreq(_adapter *padapter);\nvoid issue_reassocreq(_adapter *padapter);\nvoid issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type);\nvoid issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status);\nvoid issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da);\ns32 issue_probereq_ex(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int try_cnt, int wait_ms);\nint issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms);\nint issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int try_cnt, int wait_ms);\nint issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason);\nint issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt, int wait_ms);\nvoid issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset);\nvoid issue_addba_req(_adapter *adapter, unsigned char *ra, u8 tid);\nvoid issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size);\nu8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size, int try_cnt, int wait_ms);\nvoid issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator);\nint issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator, int try_cnt, int wait_ms);\nvoid issue_action_BSSCoexistPacket(_adapter *padapter);\n\n#ifdef CONFIG_IEEE80211W\nvoid issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid, u8 key_type);\nint issue_deauth_11w(_adapter *padapter, unsigned char *da, unsigned short reason, u8 key_type);\n#endif /* CONFIG_IEEE80211W */\nint issue_action_SM_PS(_adapter *padapter ,  unsigned char *raddr , u8 NewMimoPsMode);\nint issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 NewMimoPsMode, int try_cnt, int wait_ms);\n\nunsigned int send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid, u8 force);\nunsigned int send_delba_sta_tid_wait_ack(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid, u8 force);\n\nunsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr);\nunsigned int send_beacon(_adapter *padapter);\n\nvoid start_clnt_assoc(_adapter *padapter);\nvoid start_clnt_auth(_adapter *padapter);\nvoid start_clnt_join(_adapter *padapter);\nvoid start_create_ibss(_adapter *padapter);\n\nunsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame);\n\nunsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame);\n#ifdef CONFIG_RTW_WNM\nunsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe);\n#endif\n\n#define RX_AMPDU_ACCEPT_INVALID 0xFF\n#define RX_AMPDU_SIZE_INVALID 0xFF\n\nenum rx_ampdu_reason {\n\tRX_AMPDU_DRV_FIXED = 1,\n\tRX_AMPDU_BTCOEX = 2, /* not used, because BTCOEX has its own variable management */\n\tRX_AMPDU_DRV_SCAN = 3,\n};\nu8 rtw_rx_ampdu_size(_adapter *adapter);\nbool rtw_rx_ampdu_is_accept(_adapter *adapter);\nbool rtw_rx_ampdu_set_size(_adapter *adapter, u8 size, u8 reason);\nbool rtw_rx_ampdu_set_accept(_adapter *adapter, u8 accept, u8 reason);\nu8 rx_ampdu_apply_sta_tid(_adapter *adapter, struct sta_info *sta, u8 tid, u8 accept, u8 size);\nu8 rx_ampdu_size_sta_limit(_adapter *adapter, struct sta_info *sta);\nu8 rx_ampdu_apply_sta(_adapter *adapter, struct sta_info *sta, u8 accept, u8 size);\nu16 rtw_rx_ampdu_apply(_adapter *adapter);\n\nunsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame);\n#ifdef CONFIG_IEEE80211W\nunsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame);\n#endif /* CONFIG_IEEE80211W */\nunsigned int on_action_rm(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame);\nunsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame);\n\n#ifdef CONFIG_RTW_80211R\nvoid rtw_ft_update_bcn(_adapter *padapter, union recv_frame *precv_frame);\nvoid rtw_ft_start_clnt_join(_adapter *padapter);\nu8 rtw_ft_update_rsnie(_adapter *padapter, u8 bwrite, \n\tstruct pkt_attrib *pattrib, u8 **pframe);\nvoid rtw_ft_build_auth_req_ies(_adapter *padapter, \n\tstruct pkt_attrib *pattrib, u8 **pframe);\nvoid rtw_ft_build_assoc_req_ies(_adapter *padapter, \n\tu8 is_reassoc, struct pkt_attrib *pattrib, u8 **pframe);\nu8 rtw_ft_update_auth_rsp_ies(_adapter *padapter, u8 *pframe, u32 len);\nvoid rtw_ft_start_roam(_adapter *padapter, u8 *pTargetAddr);\nvoid rtw_ft_issue_action_req(_adapter *padapter, u8 *pTargetAddr);\nvoid rtw_ft_report_evt(_adapter *padapter);\nvoid rtw_ft_report_reassoc_evt(_adapter *padapter, u8 *pMacAddr);\nvoid rtw_ft_link_timer_hdl(void *ctx);\nvoid rtw_ft_roam_timer_hdl(void *ctx);\nvoid rtw_ft_roam_status_reset(_adapter *padapter);\n#endif\n#ifdef CONFIG_RTW_WNM\nvoid rtw_wnm_roam_scan_hdl(void *ctx);\nvoid rtw_wnm_process_btm_req(_adapter *padapter,  u8* pframe, u32 frame_len);\nvoid rtw_wnm_reset_btm_candidate(struct roam_nb_info *pnb);\nvoid rtw_wnm_reset_btm_state(_adapter *padapter);\nvoid rtw_wnm_issue_action(_adapter *padapter, u8 action, u8 reason);\n#endif\n#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)\nu32 rtw_wnm_btm_candidates_survey(_adapter *padapter, u8* pframe, u32 elem_len, u8 is_preference);\n#endif\nvoid mlmeext_joinbss_event_callback(_adapter *padapter, int join_res);\nvoid mlmeext_sta_del_event_callback(_adapter *padapter);\nvoid mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta);\n\nint rtw_get_rx_chk_limit(_adapter *adapter);\nvoid rtw_set_rx_chk_limit(_adapter *adapter, int limit);\nvoid linked_status_chk(_adapter *padapter, u8 from_timer);\n\n#define rtw_get_bcn_cnt(adapter)\t(adapter->mlmeextpriv.cur_bcn_cnt)\n#define rtw_get_bcn_dtim_period(adapter)\t(adapter->mlmeextpriv.dtim)\nvoid rtw_collect_bcn_info(_adapter *adapter);\n\nvoid _linked_info_dump(_adapter *padapter);\n\nvoid survey_timer_hdl(void *ctx);\n#ifdef CONFIG_RTW_REPEATER_SON\nvoid rson_timer_hdl(void *ctx);\n#endif\nvoid link_timer_hdl(void *ctx);\nvoid addba_timer_hdl(void *ctx);\n#ifdef CONFIG_IEEE80211W\nvoid sa_query_timer_hdl(void *ctx);\n#endif /* CONFIG_IEEE80211W */\n#if 0\nvoid reauth_timer_hdl(_adapter *padapter);\nvoid reassoc_timer_hdl(_adapter *padapter);\n#endif\n\n#define set_survey_timer(mlmeext, ms) \\\n\tdo { \\\n\t\t/*RTW_INFO(\"%s set_survey_timer(%p, %d)\\n\", __FUNCTION__, (mlmeext), (ms));*/ \\\n\t\t_set_timer(&(mlmeext)->survey_timer, (ms)); \\\n\t} while (0)\n\n#define set_link_timer(mlmeext, ms) \\\n\tdo { \\\n\t\t/*RTW_INFO(\"%s set_link_timer(%p, %d)\\n\", __FUNCTION__, (mlmeext), (ms));*/ \\\n\t\t_set_timer(&(mlmeext)->link_timer, (ms)); \\\n\t} while (0)\n\nbool rtw_is_cck_rate(u8 rate);\nbool rtw_is_ofdm_rate(u8 rate);\nbool rtw_is_basic_rate_cck(u8 rate);\nbool rtw_is_basic_rate_ofdm(u8 rate);\nbool rtw_is_basic_rate_mix(u8 rate);\n\nextern int cckrates_included(unsigned char *rate, int ratelen);\nextern int cckratesonly_included(unsigned char *rate, int ratelen);\n\nextern void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr);\n\nextern void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len);\nextern void correct_TSF(_adapter *padapter, u8 mlme_state);\n#ifdef CONFIG_BCN_RECV_TIME\nvoid rtw_rx_bcn_time_update(_adapter *adapter, uint bcn_len, u8 data_rate);\n#endif\nextern u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer);\n\nvoid rtw_process_bar_frame(_adapter *padapter, union recv_frame *precv_frame);\nvoid rtw_join_done_chk_ch(_adapter *padapter, int join_res);\n\nint rtw_chk_start_clnt_join(_adapter *padapter, u8 *ch, u8 *bw, u8 *offset);\n\n#ifdef CONFIG_PLATFORM_ARM_SUN8I\n\t#define BUSY_TRAFFIC_SCAN_DENY_PERIOD\t8000\n#else\n\t#define BUSY_TRAFFIC_SCAN_DENY_PERIOD\t12000\n#endif\n\nstruct cmd_hdl {\n\tuint\tparmsize;\n\tu8(*h2cfuns)(struct _ADAPTER *padapter, u8 *pbuf);\n};\n\nvoid rtw_leave_opch(_adapter *adapter);\nvoid rtw_back_opch(_adapter *adapter);\n\nu8 read_macreg_hdl(_adapter *padapter, u8 *pbuf);\nu8 write_macreg_hdl(_adapter *padapter, u8 *pbuf);\nu8 read_bbreg_hdl(_adapter *padapter, u8 *pbuf);\nu8 write_bbreg_hdl(_adapter *padapter, u8 *pbuf);\nu8 read_rfreg_hdl(_adapter *padapter, u8 *pbuf);\nu8 write_rfreg_hdl(_adapter *padapter, u8 *pbuf);\n\n\nu8 NULL_hdl(_adapter *padapter, u8 *pbuf);\nu8 join_cmd_hdl(_adapter *padapter, u8 *pbuf);\nu8 disconnect_hdl(_adapter *padapter, u8 *pbuf);\nu8 createbss_hdl(_adapter *padapter, u8 *pbuf);\nu8 setopmode_hdl(_adapter *padapter, u8 *pbuf);\nu8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf);\nu8 setauth_hdl(_adapter *padapter, u8 *pbuf);\nu8 setkey_hdl(_adapter *padapter, u8 *pbuf);\nu8 set_stakey_hdl(_adapter *padapter, u8 *pbuf);\nu8 set_assocsta_hdl(_adapter *padapter, u8 *pbuf);\nu8 del_assocsta_hdl(_adapter *padapter, u8 *pbuf);\nu8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf);\nu8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf);\n\nvoid rtw_ap_wep_pk_setting(_adapter *adapter, struct sta_info *psta);\n\nu8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf);\nu8 h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf);\nu8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf);\nu8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf);\nu8 rtw_set_chbw_hdl(_adapter *padapter, u8 *pbuf);\nu8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf);\nu8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf);\nu8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf);\t/* Kurt: Handling DFS channel switch announcement ie. */\nu8 tdls_hdl(_adapter *padapter, unsigned char *pbuf);\nu8 run_in_thread_hdl(_adapter *padapter, u8 *pbuf);\nu8 rtw_getmacreg_hdl(_adapter *padapter, u8 *pbuf);\n\nint rtw_sae_preprocess(_adapter *adapter, const u8 *buf, u32 len, u8 tx);\n\n#define GEN_DRV_CMD_HANDLER(size, cmd)\t{size, &cmd ## _hdl},\n#define GEN_MLME_EXT_HANDLER(size, cmd)\t{size, cmd},\n\n#ifdef _RTW_CMD_C_\n\nstruct cmd_hdl wlancmds[] = {\n\tGEN_DRV_CMD_HANDLER(sizeof(struct readMAC_parm), rtw_getmacreg) /*0*/\n\tGEN_DRV_CMD_HANDLER(0, NULL)\n\tGEN_DRV_CMD_HANDLER(0, NULL)\n\tGEN_DRV_CMD_HANDLER(0, NULL)\n\tGEN_DRV_CMD_HANDLER(0, NULL)\n\tGEN_DRV_CMD_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL) /*10*/\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(sizeof(struct joinbss_parm), join_cmd_hdl)  /*14*/\n\tGEN_MLME_EXT_HANDLER(sizeof(struct disconnect_parm), disconnect_hdl)\n\tGEN_MLME_EXT_HANDLER(sizeof(struct createbss_parm), createbss_hdl)\n\tGEN_MLME_EXT_HANDLER(sizeof(struct setopmode_parm), setopmode_hdl)\n\tGEN_MLME_EXT_HANDLER(sizeof(struct sitesurvey_parm), sitesurvey_cmd_hdl)  /*18*/\n\tGEN_MLME_EXT_HANDLER(sizeof(struct setauth_parm), setauth_hdl)\n\tGEN_MLME_EXT_HANDLER(sizeof(struct setkey_parm), setkey_hdl)  /*20*/\n\tGEN_MLME_EXT_HANDLER(sizeof(struct set_stakey_parm), set_stakey_hdl)\n\tGEN_MLME_EXT_HANDLER(sizeof(struct set_assocsta_parm), NULL)\n\tGEN_MLME_EXT_HANDLER(sizeof(struct del_assocsta_parm), NULL)\n\tGEN_MLME_EXT_HANDLER(sizeof(struct setstapwrstate_parm), NULL)\n\tGEN_MLME_EXT_HANDLER(sizeof(struct setbasicrate_parm), NULL)\n\tGEN_MLME_EXT_HANDLER(sizeof(struct getbasicrate_parm), NULL)\n\tGEN_MLME_EXT_HANDLER(sizeof(struct setdatarate_parm), NULL)\n\tGEN_MLME_EXT_HANDLER(sizeof(struct getdatarate_parm), NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)   /*30*/\n\tGEN_MLME_EXT_HANDLER(sizeof(struct setphy_parm), NULL)\n\tGEN_MLME_EXT_HANDLER(sizeof(struct getphy_parm), NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\t/*40*/\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(sizeof(struct addBaReq_parm), add_ba_hdl)\n\tGEN_MLME_EXT_HANDLER(sizeof(struct set_ch_parm), rtw_set_chbw_hdl) /* 46 */\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL) /*50*/\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(0, NULL)\n\tGEN_MLME_EXT_HANDLER(sizeof(struct Tx_Beacon_param), tx_beacon_hdl) /*55*/\n\n\tGEN_MLME_EXT_HANDLER(0, mlme_evt_hdl) /*56*/\n\tGEN_MLME_EXT_HANDLER(0, rtw_drvextra_cmd_hdl) /*57*/\n\n\tGEN_MLME_EXT_HANDLER(0, h2c_msg_hdl) /*58*/\n\tGEN_MLME_EXT_HANDLER(sizeof(struct SetChannelPlan_param), set_chplan_hdl) /*59*/\n\tGEN_MLME_EXT_HANDLER(sizeof(struct LedBlink_param), led_blink_hdl) /*60*/\n\n\tGEN_MLME_EXT_HANDLER(0, set_csa_hdl) /*61*/\n\tGEN_MLME_EXT_HANDLER(sizeof(struct TDLSoption_param), tdls_hdl) /*62*/\n\tGEN_MLME_EXT_HANDLER(0, chk_bmc_sleepq_hdl) /*63*/\n\tGEN_MLME_EXT_HANDLER(sizeof(struct RunInThread_param), run_in_thread_hdl) /*64*/\n\tGEN_MLME_EXT_HANDLER(sizeof(struct addBaRsp_parm), add_ba_rsp_hdl) /* 65 */\n\tGEN_MLME_EXT_HANDLER(sizeof(struct rm_event), rm_post_event_hdl) /* 66 */\n};\n\n#endif\n\nstruct C2HEvent_Header {\n\n#ifdef CONFIG_LITTLE_ENDIAN\n\n\tunsigned int len:16;\n\tunsigned int ID:8;\n\tunsigned int seq:8;\n\n#elif defined(CONFIG_BIG_ENDIAN)\n\n\tunsigned int seq:8;\n\tunsigned int ID:8;\n\tunsigned int len:16;\n\n#else\n\n#  error \"Must be LITTLE or BIG Endian\"\n\n#endif\n\n\tunsigned int rsvd;\n\n};\n\nvoid rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf);\nvoid rtw_fwdbg_event_callback(_adapter *adapter , u8 *pbuf);\n\nenum rtw_c2h_event {\n\tGEN_EVT_CODE(_Read_MACREG) = 0, /*0*/\n\tGEN_EVT_CODE(_Read_BBREG),\n\tGEN_EVT_CODE(_Read_RFREG),\n\tGEN_EVT_CODE(_Read_EEPROM),\n\tGEN_EVT_CODE(_Read_EFUSE),\n\tGEN_EVT_CODE(_Read_CAM),\t\t\t/*5*/\n\tGEN_EVT_CODE(_Get_BasicRate),\n\tGEN_EVT_CODE(_Get_DataRate),\n\tGEN_EVT_CODE(_Survey),\t /*8*/\n\tGEN_EVT_CODE(_SurveyDone),\t /*9*/\n\n\tGEN_EVT_CODE(_JoinBss) , /*10*/\n\tGEN_EVT_CODE(_AddSTA),\n\tGEN_EVT_CODE(_DelSTA),\n\tGEN_EVT_CODE(_AtimDone) ,\n\tGEN_EVT_CODE(_TX_Report),\n\tGEN_EVT_CODE(_CCX_Report),\t\t\t/*15*/\n\tGEN_EVT_CODE(_DTM_Report),\n\tGEN_EVT_CODE(_TX_Rate_Statistics),\n\tGEN_EVT_CODE(_C2HLBK),\n\tGEN_EVT_CODE(_FWDBG),\n\tGEN_EVT_CODE(_C2HFEEDBACK),               /*20*/\n\tGEN_EVT_CODE(_ADDBA),\n\tGEN_EVT_CODE(_C2HBCN),\n\tGEN_EVT_CODE(_ReportPwrState),\t\t/* filen: only for PCIE, USB\t */\n\tGEN_EVT_CODE(_CloseRF),\t\t\t\t/* filen: only for PCIE, work around ASPM */\n\tGEN_EVT_CODE(_WMM),\t\t\t\t\t/*25*/\n#ifdef CONFIG_IEEE80211W\n\tGEN_EVT_CODE(_TimeoutSTA),\n#endif /* CONFIG_IEEE80211W */\n#ifdef CONFIG_RTW_80211R\n\tGEN_EVT_CODE(_FT_REASSOC),\n#endif\n\tMAX_C2HEVT\n};\n\n\n#ifdef _RTW_MLME_EXT_C_\n\nstatic struct fwevent wlanevents[] = {\n\t{0, rtw_dummy_event_callback},\t/*0*/\n\t{0, NULL},\n\t{0, NULL},\n\t{0, NULL},\n\t{0, NULL},\n\t{0, NULL},\n\t{0, NULL},\n\t{0, NULL},\n\t{0, &rtw_survey_event_callback},\t\t/*8*/\n\t{sizeof(struct surveydone_event), &rtw_surveydone_event_callback},\t/*9*/\n\n\t{0, &rtw_joinbss_event_callback},\t\t/*10*/\n\t{sizeof(struct stassoc_event), &rtw_stassoc_event_callback},\n\t{sizeof(struct stadel_event), &rtw_stadel_event_callback},\n\t{0, &rtw_atimdone_event_callback},\n\t{0, rtw_dummy_event_callback},\n\t{0, NULL},\t/*15*/\n\t{0, NULL},\n\t{0, NULL},\n\t{0, NULL},\n\t{0, rtw_fwdbg_event_callback},\n\t{0, NULL},\t /*20*/\n\t{0, NULL},\n\t{0, NULL},\n\t{0, &rtw_cpwm_event_callback},\n\t{0, NULL},\n\t{0, &rtw_wmm_event_callback}, /*25*/\n#ifdef CONFIG_IEEE80211W\n\t{sizeof(struct stadel_event), &rtw_sta_timeout_event_callback},\n#endif /* CONFIG_IEEE80211W */\n#ifdef CONFIG_RTW_80211R\n\t{sizeof(struct stassoc_event), &rtw_ft_reassoc_event_callback},\n#endif\n};\n\n#endif/* _RTW_MLME_EXT_C_ */\n\n#endif\n"
  },
  {
    "path": "include/rtw_mp.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTW_MP_H_\n#define _RTW_MP_H_\n\n#define RTWPRIV_VER_INFO\t1\n\n#define MAX_MP_XMITBUF_SZ\t2048\n#define NR_MP_XMITFRAME\t\t8\n#define MP_READ_REG_MAX_OFFSET 0x4FFF\n\nstruct mp_xmit_frame {\n\t_list\tlist;\n\n\tstruct pkt_attrib attrib;\n\n\t_pkt *pkt;\n\n\tint frame_tag;\n\n\t_adapter *padapter;\n\n#ifdef CONFIG_USB_HCI\n\n\t/* insert urb, irp, and irpcnt info below... */\n\t/* max frag_cnt = 8 */\n\tu8 *mem_addr;\n\tu32 sz[8];\n\tu8 bpending[8];\n\tsint ac_tag[8];\n\tsint last[8];\n\tuint irpcnt;\n\tuint fragcnt;\n#endif /* CONFIG_USB_HCI */\n\n\tuint mem[(MAX_MP_XMITBUF_SZ >> 2)];\n};\n\nstruct mp_wiparam {\n\tu32 bcompleted;\n\tu32 act_type;\n\tu32 io_offset;\n\tu32 io_value;\n};\n\ntypedef void(*wi_act_func)(void *padapter);\n\nstruct mp_tx {\n\tu8 stop;\n\tu32 count, sended;\n\tu8 payload;\n\tstruct pkt_attrib attrib;\n\t/* struct tx_desc desc; */\n\t/* u8 resvdtx[7]; */\n\tu8 desc[TXDESC_SIZE];\n\tu8 *pallocated_buf;\n\tu8 *buf;\n\tu32 buf_size, write_size;\n\t_thread_hdl_ PktTxThread;\n};\n\n#define MP_MAX_LINES\t\t1000\n#define MP_MAX_LINES_BYTES\t256\n\n\ntypedef struct _RT_PMAC_PKT_INFO {\n\tu8\t\t\tMCS;\n\tu8\t\t\tNss;\n\tu8\t\t\tNsts;\n\tu32\t\t\tN_sym;\n\tu8\t\t\tSIGA2B3;\n} RT_PMAC_PKT_INFO, *PRT_PMAC_PKT_INFO;\n\ntypedef struct _RT_PMAC_TX_INFO {\n\tu8\t\t\tbEnPMacTx:1;\t\t/* 0: Disable PMac 1: Enable PMac */\n\tu8\t\t\tMode:3;\t\t\t\t/* 0: Packet TX 3:Continuous TX */\n\tu8\t\t\tNtx:4;\t\t\t\t/* 0-7 */\n\tu8\t\t\tTX_RATE;\t\t\t/* MPT_RATE_E */\n\tu8\t\t\tTX_RATE_HEX;\n\tu8\t\t\tTX_SC;\n\tu8\t\t\tbSGI:1;\n\tu8\t\t\tbSPreamble:1;\n\tu8\t\t\tbSTBC:1;\n\tu8\t\t\tbLDPC:1;\n\tu8\t\t\tNDP_sound:1;\n\tu8\t\t\tBandWidth:3;\t\t/* 0: 20 1:40 2:80Mhz */\n\tu8\t\t\tm_STBC;\t\t\t/* bSTBC + 1 */\n\tu16\t\t\tPacketPeriod;\n\tu32\t\tPacketCount;\n\tu32\t\tPacketLength;\n\tu8\t\t\tPacketPattern;\n\tu16\t\t\tSFD;\n\tu8\t\t\tSignalField;\n\tu8\t\t\tServiceField;\n\tu16\t\t\tLENGTH;\n\tu8\t\t\tCRC16[2];\n\tu8\t\t\tLSIG[3];\n\tu8\t\t\tHT_SIG[6];\n\tu8\t\t\tVHT_SIG_A[6];\n\tu8\t\t\tVHT_SIG_B[4];\n\tu8\t\t\tVHT_SIG_B_CRC;\n\tu8\t\t\tVHT_Delimiter[4];\n\tu8\t\t\tMacAddress[6];\n} RT_PMAC_TX_INFO, *PRT_PMAC_TX_INFO;\n\n\ntypedef void (*MPT_WORK_ITEM_HANDLER)(void *Adapter);\ntypedef struct _MPT_CONTEXT {\n\t/* Indicate if we have started Mass Production Test. */\n\tBOOLEAN\t\t\tbMassProdTest;\n\n\t/* Indicate if the driver is unloading or unloaded. */\n\tBOOLEAN\t\t\tbMptDrvUnload;\n\n\t_sema\t\t\tMPh2c_Sema;\n\t_timer\t\t\tMPh2c_timeout_timer;\n\t/* Event used to sync H2c for BT control */\n\n\tBOOLEAN\t\tMptH2cRspEvent;\n\tBOOLEAN\t\tMptBtC2hEvent;\n\tBOOLEAN\t\tbMPh2c_timeout;\n\n\t/* 8190 PCI does not support NDIS_WORK_ITEM. */\n\t/* Work Item for Mass Production Test. */\n\t/* NDIS_WORK_ITEM\tMptWorkItem;\n\t*\tRT_WORK_ITEM\t\tMptWorkItem; */\n\t/* Event used to sync the case unloading driver and MptWorkItem is still in progress.\n\t*\tNDIS_EVENT\t\tMptWorkItemEvent; */\n\t/* To protect the following variables.\n\t*\tNDIS_SPIN_LOCK\t\tMptWorkItemSpinLock; */\n\t/* Indicate a MptWorkItem is scheduled and not yet finished. */\n\tBOOLEAN\t\t\tbMptWorkItemInProgress;\n\t/* An instance which implements function and context of MptWorkItem. */\n\tMPT_WORK_ITEM_HANDLER\tCurrMptAct;\n\n\t/* 1=Start, 0=Stop from UI. */\n\tu32\t\t\tMptTestStart;\n\t/* _TEST_MODE, defined in MPT_Req2.h */\n\tu32\t\t\tMptTestItem;\n\t/* Variable needed in each implementation of CurrMptAct. */\n\tu32\t\t\tMptActType;\t/* Type of action performed in CurrMptAct. */\n\t/* The Offset of IO operation is depend of MptActType. */\n\tu32\t\t\tMptIoOffset;\n\t/* The Value of IO operation is depend of MptActType. */\n\tu32\t\t\tMptIoValue;\n\t/* The RfPath of IO operation is depend of MptActType. */\n\n\tu32\t\t\tmpt_rf_path;\n\n\n\tWIRELESS_MODE\t\tMptWirelessModeToSw;\t/* Wireless mode to switch. */\n\tu8\t\t\tMptChannelToSw;\t/* Channel to switch. */\n\tu8\t\t\tMptInitGainToSet;\t/* Initial gain to set. */\n\t/* u32\t\t\tbMptAntennaA;\t\t */ /* TRUE if we want to use antenna A. */\n\tu32\t\t\tMptBandWidth;\t\t/* bandwidth to switch. */\n\n\tu32\t\t\tmpt_rate_index;/* rate index. */\n\n\t/* Register value kept for Single Carrier Tx test. */\n\tu8\t\t\tbtMpCckTxPower;\n\t/* Register value kept for Single Carrier Tx test. */\n\tu8\t\t\tbtMpOfdmTxPower;\n\t/* For MP Tx Power index */\n\tu8\t\t\tTxPwrLevel[4];\t/* rf-A, rf-B*/\n\tu32\t\t\tRegTxPwrLimit;\n\t/* Content of RCR Regsiter for Mass Production Test. */\n\tu32\t\t\tMptRCR;\n\t/* TRUE if we only receive packets with specific pattern. */\n\tBOOLEAN\t\t\tbMptFilterPattern;\n\t/* Rx OK count, statistics used in Mass Production Test. */\n\tu32\t\t\tMptRxOkCnt;\n\t/* Rx CRC32 error count, statistics used in Mass Production Test. */\n\tu32\t\t\tMptRxCrcErrCnt;\n\n\tBOOLEAN\t\t\tbCckContTx;\t/* TRUE if we are in CCK Continuous Tx test. */\n\tBOOLEAN\t\t\tbOfdmContTx;\t/* TRUE if we are in OFDM Continuous Tx test. */\n\t\t/* TRUE if we have start Continuous Tx test. */\n\tBOOLEAN\t\t\tis_start_cont_tx;\n\n\t/* TRUE if we are in Single Carrier Tx test. */\n\tBOOLEAN\t\t\tbSingleCarrier;\n\t/* TRUE if we are in Carrier Suppression Tx Test. */\n\n\tBOOLEAN\t\t\tis_carrier_suppression;\n\n\t/* TRUE if we are in Single Tone Tx test. */\n\n\tBOOLEAN\t\t\tis_single_tone;\n\n\n\t/* ACK counter asked by K.Y.. */\n\tBOOLEAN\t\t\tbMptEnableAckCounter;\n\tu32\t\t\tMptAckCounter;\n\n\t/* SD3 Willis For 8192S to save 1T/2T RF table for ACUT\tOnly fro ACUT delete later ~~~! */\n\t/* s8\t\tBufOfLines[2][MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; */\n\t/* s8\t\t\tBufOfLines[2][MP_MAX_LINES][MP_MAX_LINES_BYTES]; */\n\t/* s32\t\t\tRfReadLine[2]; */\n\n\tu8\t\tAPK_bound[2];\t/* for APK\tpath A/path B */\n\tBOOLEAN\t\tbMptIndexEven;\n\n\tu8\t\tbackup0xc50;\n\tu8\t\tbackup0xc58;\n\tu8\t\tbackup0xc30;\n\tu8\t\tbackup0x52_RF_A;\n\tu8\t\tbackup0x52_RF_B;\n\n\tu32\t\t\tbackup0x58_RF_A;\n\tu32\t\t\tbackup0x58_RF_B;\n\n\tu8\t\t\th2cReqNum;\n\tu8\t\t\tc2hBuf[32];\n\n\tu8          btInBuf[100];\n\tu32\t\t\tmptOutLen;\n\tu8          mptOutBuf[100];\n\tRT_PMAC_TX_INFO\tPMacTxInfo;\n\tRT_PMAC_PKT_INFO\tPMacPktInfo;\n\tu8 HWTxmode;\n\n\tBOOLEAN\t\t\tbldpc;\n\tBOOLEAN\t\t\tbstbc;\n} MPT_CONTEXT, *PMPT_CONTEXT;\n/* #endif */\n\n\n/* #define RTPRIV_IOCTL_MP\t\t\t\t\t( SIOCIWFIRSTPRIV + 0x17) */\nenum {\n\tWRITE_REG = 1,\n\tREAD_REG,\n\tWRITE_RF,\n\tREAD_RF,\n\tMP_START,\n\tMP_STOP,\n\tMP_RATE,\n\tMP_CHANNEL,\n\tMP_CHL_OFFSET,\n\tMP_BANDWIDTH,\n\tMP_TXPOWER,\n\tMP_ANT_TX,\n\tMP_ANT_RX,\n\tMP_CTX,\n\tMP_QUERY,\n\tMP_ARX,\n\tMP_PSD,\n\tMP_PWRTRK,\n\tMP_THER,\n\tMP_IOCTL,\n\tEFUSE_GET,\n\tEFUSE_SET,\n\tMP_RESET_STATS,\n\tMP_DUMP,\n\tMP_PHYPARA,\n\tMP_SetRFPathSwh,\n\tMP_QueryDrvStats,\n\tCTA_TEST,\n\tMP_DISABLE_BT_COEXIST,\n\tMP_PwrCtlDM,\n\tMP_GETVER,\n\tMP_MON,\n\tEFUSE_BT_MASK,\n\tEFUSE_MASK,\n\tEFUSE_FILE,\n\tMP_TX,\n\tMP_RX,\n\tMP_IQK,\n\tMP_LCK,\n\tMP_HW_TX_MODE,\n\tMP_GET_TXPOWER_INX,\n\tMP_CUSTOMER_STR,\n\tMP_PWRLMT,\n\tMP_PWRBYRATE,\n\tBT_EFUSE_FILE,\n\tMP_SetBT,\n\tMP_SWRFPath,\n\tMP_LINK,\n\tMP_DPK_TRK,\n\tMP_DPK,\n\tMP_NULL,\n#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE\n\tVENDOR_IE_SET ,\n\tVENDOR_IE_GET ,\n#endif\n#ifdef CONFIG_WOWLAN\n\tMP_WOW_ENABLE,\n\tMP_WOW_SET_PATTERN,\n#endif\n#ifdef CONFIG_AP_WOWLAN\n\tMP_AP_WOW_ENABLE,\n#endif\n\tMP_SD_IREAD,\n\tMP_SD_IWRITE,\n};\n\nstruct mp_priv {\n\t_adapter *papdater;\n\n\t/* Testing Flag */\n\tu32 mode;/* 0 for normal type packet, 1 for loopback packet (16bytes TXCMD) */\n\n\tu32 prev_fw_state;\n\n\t/* OID cmd handler */\n\tstruct mp_wiparam workparam;\n\t/*\tu8 act_in_progress; */\n\n\t/* Tx Section */\n\tu8 TID;\n\tu32 tx_pktcount;\n\tu32 pktInterval;\n\tu32 pktLength;\n\tstruct mp_tx tx;\n\n\t/* Rx Section */\n\tu32 rx_bssidpktcount;\n\tu32 rx_pktcount;\n\tu32 rx_pktcount_filter_out;\n\tu32 rx_crcerrpktcount;\n\tu32 rx_pktloss;\n\tBOOLEAN  rx_bindicatePkt;\n\tstruct recv_stat rxstat;\n\tBOOLEAN brx_filter_beacon;\n\n\t/* RF/BB relative */\n\tu8 channel;\n\tu8 bandwidth;\n\tu8 prime_channel_offset;\n\tu8 txpoweridx;\n\tu8 rateidx;\n\tu32 preamble;\n\t/*\tu8 modem; */\n\tu32 CrystalCap;\n\t/*\tu32 curr_crystalcap; */\n\n\tu16 antenna_tx;\n\tu16 antenna_rx;\n\t/*\tu8 curr_rfpath; */\n\n\tu8 check_mp_pkt;\n\n\tu8 bSetTxPower;\n\t/*\tuint ForcedDataRate; */\n\tu8 mp_dm;\n\tu8 mac_filter[ETH_ALEN];\n\tu8 bmac_filter;\n\n\t/* RF PATH Setting for WLG WLA BTG BT */\n\tu8 rf_path_cfg;\n\n\tstruct wlan_network mp_network;\n\tNDIS_802_11_MAC_ADDRESS network_macaddr;\n\n\tu8 *pallocated_mp_xmitframe_buf;\n\tu8 *pmp_xmtframe_buf;\n\t_queue free_mp_xmitqueue;\n\tu32 free_mp_xmitframe_cnt;\n\tBOOLEAN bSetRxBssid;\n\tBOOLEAN bTxBufCkFail;\n\tBOOLEAN bRTWSmbCfg;\n\tBOOLEAN bloopback;\n\tBOOLEAN bloadefusemap;\n\tBOOLEAN bloadBTefusemap;\n\tBOOLEAN bprocess_mp_mode;\n\n\tMPT_CONTEXT\tmpt_ctx;\n\n\tu8\t\t*TXradomBuffer;\n\tu8\t\tCureFuseBTCoex;\n    u8\t\tmplink_buf[2048];\n    u32\t\tmplink_rx_len;\n\tBOOLEAN mplink_brx;\n\tBOOLEAN mplink_btx;\n\n};\n\ntypedef struct _IOCMD_STRUCT_ {\n\tu8\tcmdclass;\n\tu16\tvalue;\n\tu8\tindex;\n} IOCMD_STRUCT;\n\nstruct rf_reg_param {\n\tu32 path;\n\tu32 offset;\n\tu32 value;\n};\n\nstruct bb_reg_param {\n\tu32 offset;\n\tu32 value;\n};\n\ntypedef struct _MP_FIRMWARE {\n\tFIRMWARE_SOURCE eFWSource;\n#ifdef CONFIG_EMBEDDED_FWIMG\n\tu8\t\t*szFwBuffer;\n#else\n\tu8\t\t\tszFwBuffer[0x8000];\n#endif\n\tu32\t\tulFwLength;\n} RT_MP_FIRMWARE, *PRT_MP_FIRMWARE;\n\n\n\n\n/* *********************************************************************** */\n\n#define LOWER\t_TRUE\n#define RAISE\t_FALSE\n\n/* Hardware Registers */\n#if 0\n#if 0\n#define IOCMD_CTRL_REG\t\t\t0x102502C0\n#define IOCMD_DATA_REG\t\t\t0x102502C4\n#else\n#define IOCMD_CTRL_REG\t\t\t0x10250370\n#define IOCMD_DATA_REG\t\t\t0x10250374\n#endif\n\n#define IOCMD_GET_THERMAL_METER\t\t0xFD000028\n\n#define IOCMD_CLASS_BB_RF\t\t0xF0\n#define IOCMD_BB_READ_IDX\t\t0x00\n#define IOCMD_BB_WRITE_IDX\t\t0x01\n#define IOCMD_RF_READ_IDX\t\t0x02\n#define IOCMD_RF_WRIT_IDX\t\t0x03\n#endif\n#define BB_REG_BASE_ADDR\t\t0x800\n\n/* MP variables */\n#if 0\n#define _2MAC_MODE_\t0\n#define _LOOPBOOK_MODE_\t1\n#endif\ntypedef enum _MP_MODE_ {\n\tMP_OFF,\n\tMP_ON,\n\tMP_ERR,\n\tMP_CONTINUOUS_TX,\n\tMP_SINGLE_CARRIER_TX,\n\tMP_CARRIER_SUPPRISSION_TX,\n\tMP_SINGLE_TONE_TX,\n\tMP_PACKET_TX,\n\tMP_PACKET_RX\n} MP_MODE;\n\ntypedef enum _TEST_MODE {\n\tTEST_NONE                 ,\n\tPACKETS_TX                ,\n\tPACKETS_RX                ,\n\tCONTINUOUS_TX             ,\n\tOFDM_Single_Tone_TX       ,\n\tCCK_Carrier_Suppression_TX\n} TEST_MODE;\n\n\ntypedef enum _MPT_BANDWIDTH {\n\tMPT_BW_20MHZ = 0,\n\tMPT_BW_40MHZ_DUPLICATE = 1,\n\tMPT_BW_40MHZ_ABOVE = 2,\n\tMPT_BW_40MHZ_BELOW = 3,\n\tMPT_BW_40MHZ = 4,\n\tMPT_BW_80MHZ = 5,\n\tMPT_BW_80MHZ_20_ABOVE = 6,\n\tMPT_BW_80MHZ_20_BELOW = 7,\n\tMPT_BW_80MHZ_20_BOTTOM = 8,\n\tMPT_BW_80MHZ_20_TOP = 9,\n\tMPT_BW_80MHZ_40_ABOVE = 10,\n\tMPT_BW_80MHZ_40_BELOW = 11,\n} MPT_BANDWIDTHE, *PMPT_BANDWIDTH;\n\n#define MAX_RF_PATH_NUMS\tRF_PATH_MAX\n\n\nextern u8 mpdatarate[NumRates];\n\n/* MP set force data rate base on the definition. */\ntypedef enum _MPT_RATE_INDEX {\n\t/* CCK rate. */\n\tMPT_RATE_1M = 1 ,\t/* 0 */\n\tMPT_RATE_2M,\n\tMPT_RATE_55M,\n\tMPT_RATE_11M,\t/* 3 */\n\n\t/* OFDM rate. */\n\tMPT_RATE_6M,\t/* 4 */\n\tMPT_RATE_9M,\n\tMPT_RATE_12M,\n\tMPT_RATE_18M,\n\tMPT_RATE_24M,\n\tMPT_RATE_36M,\n\tMPT_RATE_48M,\n\tMPT_RATE_54M,\t/* 11 */\n\n\t/* HT rate. */\n\tMPT_RATE_MCS0,\t/* 12 */\n\tMPT_RATE_MCS1,\n\tMPT_RATE_MCS2,\n\tMPT_RATE_MCS3,\n\tMPT_RATE_MCS4,\n\tMPT_RATE_MCS5,\n\tMPT_RATE_MCS6,\n\tMPT_RATE_MCS7,\t/* 19 */\n\tMPT_RATE_MCS8,\n\tMPT_RATE_MCS9,\n\tMPT_RATE_MCS10,\n\tMPT_RATE_MCS11,\n\tMPT_RATE_MCS12,\n\tMPT_RATE_MCS13,\n\tMPT_RATE_MCS14,\n\tMPT_RATE_MCS15,\t/* 27 */\n\tMPT_RATE_MCS16,\n\tMPT_RATE_MCS17, /*  #29 */\n\tMPT_RATE_MCS18,\n\tMPT_RATE_MCS19,\n\tMPT_RATE_MCS20,\n\tMPT_RATE_MCS21,\n\tMPT_RATE_MCS22, /*  #34 */\n\tMPT_RATE_MCS23,\n\tMPT_RATE_MCS24,\n\tMPT_RATE_MCS25,\n\tMPT_RATE_MCS26,\n\tMPT_RATE_MCS27, /*  #39 */\n\tMPT_RATE_MCS28, /*  #40 */\n\tMPT_RATE_MCS29, /*  #41 */\n\tMPT_RATE_MCS30, /*  #42 */\n\tMPT_RATE_MCS31, /*  #43 */\n\t/* VHT rate. Total: 20*/\n\tMPT_RATE_VHT1SS_MCS0 = 100,/*  #44*/\n\tMPT_RATE_VHT1SS_MCS1, /*  # */\n\tMPT_RATE_VHT1SS_MCS2,\n\tMPT_RATE_VHT1SS_MCS3,\n\tMPT_RATE_VHT1SS_MCS4,\n\tMPT_RATE_VHT1SS_MCS5,\n\tMPT_RATE_VHT1SS_MCS6, /*  # */\n\tMPT_RATE_VHT1SS_MCS7,\n\tMPT_RATE_VHT1SS_MCS8,\n\tMPT_RATE_VHT1SS_MCS9, /* #53 */\n\tMPT_RATE_VHT2SS_MCS0, /* #54 */\n\tMPT_RATE_VHT2SS_MCS1,\n\tMPT_RATE_VHT2SS_MCS2,\n\tMPT_RATE_VHT2SS_MCS3,\n\tMPT_RATE_VHT2SS_MCS4,\n\tMPT_RATE_VHT2SS_MCS5,\n\tMPT_RATE_VHT2SS_MCS6,\n\tMPT_RATE_VHT2SS_MCS7,\n\tMPT_RATE_VHT2SS_MCS8,\n\tMPT_RATE_VHT2SS_MCS9, /* #63 */\n\tMPT_RATE_VHT3SS_MCS0,\n\tMPT_RATE_VHT3SS_MCS1,\n\tMPT_RATE_VHT3SS_MCS2,\n\tMPT_RATE_VHT3SS_MCS3,\n\tMPT_RATE_VHT3SS_MCS4,\n\tMPT_RATE_VHT3SS_MCS5,\n\tMPT_RATE_VHT3SS_MCS6, /*  #126 */\n\tMPT_RATE_VHT3SS_MCS7,\n\tMPT_RATE_VHT3SS_MCS8,\n\tMPT_RATE_VHT3SS_MCS9,\n\tMPT_RATE_VHT4SS_MCS0,\n\tMPT_RATE_VHT4SS_MCS1, /*  #131 */\n\tMPT_RATE_VHT4SS_MCS2,\n\tMPT_RATE_VHT4SS_MCS3,\n\tMPT_RATE_VHT4SS_MCS4,\n\tMPT_RATE_VHT4SS_MCS5,\n\tMPT_RATE_VHT4SS_MCS6, /*  #136 */\n\tMPT_RATE_VHT4SS_MCS7,\n\tMPT_RATE_VHT4SS_MCS8,\n\tMPT_RATE_VHT4SS_MCS9,\n\tMPT_RATE_LAST\n} MPT_RATE_E, *PMPT_RATE_E;\n\n#define MAX_TX_PWR_INDEX_N_MODE 64\t/* 0x3F */\n\n#define MPT_IS_CCK_RATE(_value)\t\t(MPT_RATE_1M <= _value && _value <= MPT_RATE_11M)\n#define MPT_IS_OFDM_RATE(_value)\t(MPT_RATE_6M <= _value && _value <= MPT_RATE_54M)\n#define MPT_IS_HT_RATE(_value)\t\t(MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS31)\n#define MPT_IS_HT_1S_RATE(_value)\t(MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS7)\n#define MPT_IS_HT_2S_RATE(_value)\t(MPT_RATE_MCS8 <= _value && _value <= MPT_RATE_MCS15)\n#define MPT_IS_HT_3S_RATE(_value)\t(MPT_RATE_MCS16 <= _value && _value <= MPT_RATE_MCS23)\n#define MPT_IS_HT_4S_RATE(_value)\t(MPT_RATE_MCS24 <= _value && _value <= MPT_RATE_MCS31)\n\n#define MPT_IS_VHT_RATE(_value)\t\t(MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9)\n#define MPT_IS_VHT_1S_RATE(_value)\t(MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT1SS_MCS9)\n#define MPT_IS_VHT_2S_RATE(_value)\t(MPT_RATE_VHT2SS_MCS0 <= _value && _value <= MPT_RATE_VHT2SS_MCS9)\n#define MPT_IS_VHT_3S_RATE(_value)\t(MPT_RATE_VHT3SS_MCS0 <= _value && _value <= MPT_RATE_VHT3SS_MCS9)\n#define MPT_IS_VHT_4S_RATE(_value)\t(MPT_RATE_VHT4SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9)\n\n#define MPT_IS_2SS_RATE(_rate) ((MPT_RATE_MCS8 <= _rate && _rate <= MPT_RATE_MCS15) || \\\n\t(MPT_RATE_VHT2SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT2SS_MCS9))\n#define MPT_IS_3SS_RATE(_rate) ((MPT_RATE_MCS16 <= _rate && _rate <= MPT_RATE_MCS23) || \\\n\t(MPT_RATE_VHT3SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT3SS_MCS9))\n#define MPT_IS_4SS_RATE(_rate) ((MPT_RATE_MCS24 <= _rate && _rate <= MPT_RATE_MCS31) || \\\n\t(MPT_RATE_VHT4SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT4SS_MCS9))\n\ntypedef enum _POWER_MODE_ {\n\tPOWER_LOW = 0,\n\tPOWER_NORMAL\n} POWER_MODE;\n\n/* The following enumeration is used to define the value of Reg0xD00[30:28] or JaguarReg0x914[18:16]. */\ntypedef enum _OFDM_TX_MODE {\n\tOFDM_ALL_OFF\t\t= 0,\n\tOFDM_ContinuousTx\t= 1,\n\tOFDM_SingleCarrier\t= 2,\n\tOFDM_SingleTone\t= 4,\n} OFDM_TX_MODE;\n\n\n#define RX_PKT_BROADCAST\t1\n#define RX_PKT_DEST_ADDR\t2\n#define RX_PKT_PHY_MATCH\t3\n\ntypedef enum _ENCRY_CTRL_STATE_ {\n\tHW_CONTROL,\t\t/* hw encryption& decryption */\n\tSW_CONTROL,\t\t/* sw encryption& decryption */\n\tHW_ENCRY_SW_DECRY,\t/* hw encryption & sw decryption */\n\tSW_ENCRY_HW_DECRY\t/* sw encryption & hw decryption */\n} ENCRY_CTRL_STATE;\n\ntypedef enum\t_MPT_TXPWR_DEF {\n\tMPT_CCK,\n\tMPT_OFDM, /* L and HT OFDM */\n\tMPT_OFDM_AND_HT,\n\tMPT_HT,\n\tMPT_VHT\n} MPT_TXPWR_DEF;\n\n\n#define IS_MPT_HT_RATE(_rate)\t\t\t(_rate >= MPT_RATE_MCS0 && _rate <= MPT_RATE_MCS31)\n#define IS_MPT_VHT_RATE(_rate)\t\t\t(_rate >= MPT_RATE_VHT1SS_MCS0 && _rate <= MPT_RATE_VHT4SS_MCS9)\n#define IS_MPT_CCK_RATE(_rate)\t\t\t(_rate >= MPT_RATE_1M && _rate <= MPT_RATE_11M)\n#define IS_MPT_OFDM_RATE(_rate)\t\t\t(_rate >= MPT_RATE_6M && _rate <= MPT_RATE_54M)\n/*************************************************************************/\n#if 0\nextern struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv);\nextern int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe);\n#endif\n\nextern s32 init_mp_priv(PADAPTER padapter);\nextern void free_mp_priv(struct mp_priv *pmp_priv);\nextern s32 MPT_InitializeAdapter(PADAPTER padapter, u8 Channel);\nextern void MPT_DeInitAdapter(PADAPTER padapter);\nextern s32 mp_start_test(PADAPTER padapter);\nextern void mp_stop_test(PADAPTER padapter);\n\nextern u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask);\nextern void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val);\n\nextern u32 read_macreg(_adapter *padapter, u32 addr, u32 sz);\nextern void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz);\nextern u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask);\nextern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val);\nextern u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr);\nextern void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val);\n#ifdef CONFIG_ANTENNA_DIVERSITY\nu8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain);\n#endif\nvoid\tSetChannel(PADAPTER pAdapter);\nvoid\tSetBandwidth(PADAPTER pAdapter);\nint\tSetTxPower(PADAPTER pAdapter);\nvoid\tSetAntenna(PADAPTER pAdapter);\nvoid\tSetDataRate(PADAPTER pAdapter);\nvoid\tSetAntenna(PADAPTER pAdapter);\ns32\tSetThermalMeter(PADAPTER pAdapter, u8 target_ther);\nvoid\tGetThermalMeter(PADAPTER pAdapter, u8 rfpath ,u8 *value);\nvoid\tSetContinuousTx(PADAPTER pAdapter, u8 bStart);\nvoid\tSetSingleCarrierTx(PADAPTER pAdapter, u8 bStart);\nvoid\tSetSingleToneTx(PADAPTER pAdapter, u8 bStart);\nvoid\tSetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart);\nvoid\tPhySetTxPowerLevel(PADAPTER pAdapter);\nvoid\tfill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc);\nvoid\tSetPacketTx(PADAPTER padapter);\nvoid\tSetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB);\nvoid\tResetPhyRxPktCount(PADAPTER pAdapter);\nu32\tGetPhyRxPktReceived(PADAPTER pAdapter);\nu32\tGetPhyRxPktCRC32Error(PADAPTER pAdapter);\ns32\tSetPowerTracking(PADAPTER padapter, u8 enable);\nvoid\tGetPowerTracking(PADAPTER padapter, u8 *enable);\nu32\tmp_query_psd(PADAPTER pAdapter, u8 *data);\nvoid\trtw_mp_trigger_iqk(PADAPTER padapter);\nvoid\trtw_mp_trigger_lck(PADAPTER padapter);\nvoid\trtw_mp_trigger_dpk(PADAPTER padapter);\nu8 rtw_mp_mode_check(PADAPTER padapter);\n\n\nvoid hal_mpt_SwitchRfSetting(PADAPTER pAdapter);\ns32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable);\nvoid hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable);\nvoid hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14);\nvoid hal_mpt_SetChannel(PADAPTER pAdapter);\nvoid hal_mpt_SetBandwidth(PADAPTER pAdapter);\nvoid hal_mpt_SetTxPower(PADAPTER pAdapter);\nvoid hal_mpt_SetDataRate(PADAPTER pAdapter);\nvoid hal_mpt_SetAntenna(PADAPTER pAdapter);\ns32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther);\nvoid hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter);\nu8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path);\nvoid hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value);\nvoid hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart);\nvoid hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart);\nvoid hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart);\nvoid hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart);\nvoid mpt_ProSetPMacTx(PADAPTER\tAdapter);\nvoid MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain);\nvoid mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate);\nu8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter);\nu32 mpt_ProQueryCalTxPower(PADAPTER\tpAdapter, u8 RfPath);\nvoid MPT_PwrCtlDM(PADAPTER padapter, u32 bstart);\nu8 mpt_to_mgnt_rate(u32\tMptRateIdx);\nu8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr);\nu32 mp_join(PADAPTER padapter, u8 mode);\nu32 hal_mpt_query_phytxok(PADAPTER\tpAdapter);\n\nvoid\nPMAC_Get_Pkt_Param(\n\tPRT_PMAC_TX_INFO\tpPMacTxInfo,\n\tPRT_PMAC_PKT_INFO\tpPMacPktInfo\n);\nvoid\nCCK_generator(\n\tPRT_PMAC_TX_INFO\tpPMacTxInfo,\n\tPRT_PMAC_PKT_INFO\tpPMacPktInfo\n);\nvoid\nPMAC_Nsym_generator(\n\tPRT_PMAC_TX_INFO\tpPMacTxInfo,\n\tPRT_PMAC_PKT_INFO\tpPMacPktInfo\n);\nvoid\nL_SIG_generator(\n\tu32\tN_SYM,\t\t/* Max: 750*/\n\tPRT_PMAC_TX_INFO\tpPMacTxInfo,\n\tPRT_PMAC_PKT_INFO\tpPMacPktInfo\n);\n\nvoid HT_SIG_generator(\n\tPRT_PMAC_TX_INFO\tpPMacTxInfo,\n\tPRT_PMAC_PKT_INFO\tpPMacPktInfo);\n\nvoid VHT_SIG_A_generator(\n\tPRT_PMAC_TX_INFO\tpPMacTxInfo,\n\tPRT_PMAC_PKT_INFO\tpPMacPktInfo);\n\nvoid VHT_SIG_B_generator(\n\tPRT_PMAC_TX_INFO\tpPMacTxInfo);\n\nvoid VHT_Delimiter_generator(\n\tPRT_PMAC_TX_INFO\tpPMacTxInfo);\n\n\nint rtw_mp_write_reg(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_read_reg(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_write_rf(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_read_rf(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_start(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_stop(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_rate(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_channel(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_ch_offset(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_bandwidth(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_txpower_index(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_txpower(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_txpower(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_ant_tx(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_ant_rx(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_set_ctx_destAddr(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_ctx(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_disable_bt_coexist(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra);\nint rtw_mp_disable_bt_coexist(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra);\nint rtw_mp_arx(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_trx_query(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_pwrtrk(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_psd(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_thermal(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_reset_stats(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_dump(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_phypara(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_SetRFPath(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_switch_rf_path(struct net_device *dev,\n\t\t\tstruct iw_request_info *info,\n\t\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_link(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_QueryDrv(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra);\nint rtw_mp_PwrCtlDM(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\nint rtw_mp_getver(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra);\nint rtw_mp_mon(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra);\nint rtw_mp_pwrlmt(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra);\nint rtw_mp_pwrbyrate(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra);\nint rtw_mp_dpk_track(struct net_device *dev,\n\t\t\tstruct iw_request_info *info,\n\t\t\tunion iwreq_data *wrqu, char *extra);\nint rtw_mp_dpk(struct net_device *dev,\n\t\t\tstruct iw_request_info *info,\n\t\t\tunion iwreq_data *wrqu, char *extra);\nint rtw_efuse_mask_file(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra);\nint rtw_bt_efuse_mask_file(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra);\nint rtw_efuse_file_map(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra);\nint rtw_bt_efuse_file_map(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra);\nint rtw_mp_SetBT(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra);\nint rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra);\nint rtw_mp_tx(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra);\nint rtw_mp_rx(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra);\nint rtw_mp_hwtx(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra);\nu8 HwRateToMPTRate(u8 rate);\nint rtw_mp_iqk(struct net_device *dev,\n\t\t struct iw_request_info *info,\n\t\t struct iw_point *wrqu, char *extra);\nint rtw_mp_lck(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra);\n#endif /* _RTW_MP_H_ */\n"
  },
  {
    "path": "include/rtw_mp_phy_regdef.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n/*****************************************************************************\n *\n * Module:\t__RTW_MP_PHY_REGDEF_H_\n *\n *\n * Note:\t1. Define PMAC/BB register map\n *\t\t\t2. Define RF register map\n *\t\t\t3. PMAC/BB register bit mask.\n *\t\t\t4. RF reg bit mask.\n *\t\t\t5. Other BB/RF relative definition.\n *\n *\n * Export:\tConstants, macro, functions(API), global variables(None).\n *\n * Abbrev:\n *\n * History:\n *\tData\t\t\tWho\t\tRemark\n *\t08/07/2007\tMHC\t\t1. Porting from 9x series PHYCFG.h.\n *\t\t\t\t\t\t2. Reorganize code architecture.\n *\t09/25/2008\tMH\t\t1. Add RL6052 register definition\n *\n *****************************************************************************/\n#ifndef __RTW_MP_PHY_REGDEF_H_\n#define __RTW_MP_PHY_REGDEF_H_\n\n\n/*--------------------------Define Parameters-------------------------------*/\n\n/* ************************************************************\n * 8192S Regsiter offset definition\n * ************************************************************ */\n\n/*\n * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00\n * 3. RF register 0x00-2E\n * 4. Bit Mask for BB/RF register\n * 5. Other defintion for BB/RF R/W\n *   */\n\n\n/*\n * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF\n * 1. Page1(0x100)\n *   */\n#define\t\trPMAC_Reset\t\t\t\t\t0x100\n#define\t\trPMAC_TxStart\t\t\t\t\t0x104\n#define\t\trPMAC_TxLegacySIG\t\t\t\t0x108\n#define\t\trPMAC_TxHTSIG1\t\t\t\t0x10c\n#define\t\trPMAC_TxHTSIG2\t\t\t\t0x110\n#define\t\trPMAC_PHYDebug\t\t\t\t0x114\n#define\t\trPMAC_TxPacketNum\t\t\t\t0x118\n#define\t\trPMAC_TxIdle\t\t\t\t\t0x11c\n#define\t\trPMAC_TxMACHeader0\t\t\t0x120\n#define\t\trPMAC_TxMACHeader1\t\t\t0x124\n#define\t\trPMAC_TxMACHeader2\t\t\t0x128\n#define\t\trPMAC_TxMACHeader3\t\t\t0x12c\n#define\t\trPMAC_TxMACHeader4\t\t\t0x130\n#define\t\trPMAC_TxMACHeader5\t\t\t0x134\n#define\t\trPMAC_TxDataType\t\t\t\t0x138\n#define\t\trPMAC_TxRandomSeed\t\t\t0x13c\n#define\t\trPMAC_CCKPLCPPreamble\t\t\t0x140\n#define\t\trPMAC_CCKPLCPHeader\t\t\t0x144\n#define\t\trPMAC_CCKCRC16\t\t\t\t0x148\n#define\t\trPMAC_OFDMRxCRC32OK\t\t\t0x170\n#define\t\trPMAC_OFDMRxCRC32Er\t\t\t0x174\n#define\t\trPMAC_OFDMRxParityEr\t\t\t0x178\n#define\t\trPMAC_OFDMRxCRC8Er\t\t\t0x17c\n#define\t\trPMAC_CCKCRxRC16Er\t\t\t0x180\n#define\t\trPMAC_CCKCRxRC32Er\t\t\t0x184\n#define\t\trPMAC_CCKCRxRC32OK\t\t\t0x188\n#define\t\trPMAC_TxStatus\t\t\t\t\t0x18c\n\n/*\n * 2. Page2(0x200)\n *\n * The following two definition are only used for USB interface.\n * #define\t\tRF_BB_CMD_ADDR\t\t\t\t0x02c0 */\t/* RF/BB read/write command address.\n * #define\t\tRF_BB_CMD_DATA\t\t\t\t0x02c4 */\t/* RF/BB read/write command data. */\n\n/*\n * 3. Page8(0x800)\n *   */\n#define\t\trFPGA0_RFMOD\t\t\t\t0x800\t/* RF mode & CCK TxSC */ /* RF BW Setting?? */\n\n#define\t\trFPGA0_TxInfo\t\t\t\t0x804\t/* Status report?? */\n#define\t\trFPGA0_PSDFunction\t\t\t0x808\n\n#define\t\trFPGA0_TxGainStage\t\t\t0x80c\t/* Set TX PWR init gain? */\n\n#define\t\trFPGA0_RFTiming1\t\t\t0x810\t/* Useless now */\n#define\t\trFPGA0_RFTiming2\t\t\t0x814\n/* #define rFPGA0_XC_RFTiming\t\t0x818 */\n/* #define rFPGA0_XD_RFTiming\t\t0x81c */\n\n#define\t\trFPGA0_XA_HSSIParameter1\t\t0x820\t/* RF 3 wire register */\n#define\t\trFPGA0_XA_HSSIParameter2\t\t0x824\n#define\t\trFPGA0_XB_HSSIParameter1\t\t0x828\n#define\t\trFPGA0_XB_HSSIParameter2\t\t0x82c\n#define\t\trFPGA0_XC_HSSIParameter1\t\t0x830\n#define\t\trFPGA0_XC_HSSIParameter2\t\t0x834\n#define\t\trFPGA0_XD_HSSIParameter1\t\t0x838\n#define\t\trFPGA0_XD_HSSIParameter2\t\t0x83c\n#define\t\trFPGA0_XA_LSSIParameter\t\t0x840\n#define\t\trFPGA0_XB_LSSIParameter\t\t0x844\n#define\t\trFPGA0_XC_LSSIParameter\t\t0x848\n#define\t\trFPGA0_XD_LSSIParameter\t\t0x84c\n\n#define\t\trFPGA0_RFWakeUpParameter\t\t0x850\t/* Useless now */\n#define\t\trFPGA0_RFSleepUpParameter\t\t0x854\n\n#define\t\trFPGA0_XAB_SwitchControl\t\t0x858\t/* RF Channel switch */\n#define\t\trFPGA0_XCD_SwitchControl\t\t0x85c\n\n#define\t\trFPGA0_XA_RFInterfaceOE\t\t0x860\t/* RF Channel switch */\n#define\t\trFPGA0_XB_RFInterfaceOE\t\t0x864\n#define\t\trFPGA0_XC_RFInterfaceOE\t\t0x868\n#define\t\trFPGA0_XD_RFInterfaceOE\t\t0x86c\n\n#define\t\trFPGA0_XAB_RFInterfaceSW\t\t0x870\t/* RF Interface Software Control */\n#define\t\trFPGA0_XCD_RFInterfaceSW\t\t0x874\n\n#define\t\trFPGA0_XAB_RFParameter\t\t0x878\t/* RF Parameter */\n#define\t\trFPGA0_XCD_RFParameter\t\t0x87c\n\n#define\t\trFPGA0_AnalogParameter1\t\t0x880\t/* Crystal cap setting RF-R/W protection for parameter4?? */\n#define\t\trFPGA0_AnalogParameter2\t\t0x884\n#define\t\trFPGA0_AnalogParameter3\t\t0x888\t/* Useless now */\n#define\t\trFPGA0_AnalogParameter4\t\t0x88c\n\n#define\t\trFPGA0_XA_LSSIReadBack\t\t0x8a0\t/* Tranceiver LSSI Readback */\n#define\t\trFPGA0_XB_LSSIReadBack\t\t0x8a4\n#define\t\trFPGA0_XC_LSSIReadBack\t\t0x8a8\n#define\t\trFPGA0_XD_LSSIReadBack\t\t0x8ac\n\n#define\t\trFPGA0_PSDReport\t\t\t\t0x8b4\t/* Useless now */\n#define\t\trFPGA0_XAB_RFInterfaceRB\t\t0x8e0\t/* Useless now */ /* RF Interface Readback Value */\n#define\t\trFPGA0_XCD_RFInterfaceRB\t\t0x8e4\t/* Useless now */\n\n/*\n * 4. Page9(0x900)\n *   */\n#define\t\trFPGA1_RFMOD\t\t\t\t0x900\t/* RF mode & OFDM TxSC */ /* RF BW Setting?? */\n\n#define\t\trFPGA1_TxBlock\t\t\t\t0x904\t/* Useless now */\n#define\t\trFPGA1_DebugSelect\t\t\t0x908\t/* Useless now */\n#define\t\trFPGA1_TxInfo\t\t\t\t0x90c\t/* Useless now */ /* Status report?? */\n#define\trS0S1_PathSwitch\t\t\t0x948\n\n/*\n * 5. PageA(0xA00)\n *\n * Set Control channel to upper or lower. These settings are required only for 40MHz */\n#define\t\trCCK0_System\t\t\t\t0xa00\n\n#define\t\trCCK0_AFESetting\t\t\t0xa04\t/* Disable init gain now */ /* Select RX path by RSSI */\n#define\t\trCCK0_CCA\t\t\t\t\t0xa08\t/* Disable init gain now */ /* Init gain */\n\n#define\t\trCCK0_RxAGC1\t\t\t\t0xa0c\t/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */\n#define\t\trCCK0_RxAGC2\t\t\t\t0xa10\t/* AGC & DAGC */\n\n#define\t\trCCK0_RxHP\t\t\t\t\t0xa14\n\n#define\t\trCCK0_DSPParameter1\t\t0xa18\t/* Timing recovery & Channel estimation threshold */\n#define\t\trCCK0_DSPParameter2\t\t0xa1c\t/* SQ threshold */\n\n#define\t\trCCK0_TxFilter1\t\t\t\t0xa20\n#define\t\trCCK0_TxFilter2\t\t\t\t0xa24\n#define\t\trCCK0_DebugPort\t\t\t0xa28\t/* debug port and Tx filter3 */\n#define\t\trCCK0_FalseAlarmReport\t\t0xa2c\t/* 0xa2d\tuseless now 0xa30-a4f channel report */\n#define\t\trCCK0_TRSSIReport\t\t0xa50\n#define\t\trCCK0_RxReport            \t\t0xa54  /* 0xa57 */\n#define\t\trCCK0_FACounterLower      \t0xa5c  /* 0xa5b */\n#define\t\trCCK0_FACounterUpper      \t0xa58  /* 0xa5c */\n\n/*\n * 6. PageC(0xC00)\n *   */\n#define\t\trOFDM0_LSTF\t\t\t\t0xc00\n\n#define\t\trOFDM0_TRxPathEnable\t\t0xc04\n#define\t\trOFDM0_TRMuxPar\t\t\t0xc08\n#define\t\trOFDM0_TRSWIsolation\t\t0xc0c\n\n#define\t\trOFDM0_XARxAFE\t\t\t0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */\n#define\t\trOFDM0_XARxIQImbalance    \t0xc14  /* RxIQ imblance matrix */\n#define\t\trOFDM0_XBRxAFE\t\t0xc18\n#define\t\trOFDM0_XBRxIQImbalance\t0xc1c\n#define\t\trOFDM0_XCRxAFE\t\t0xc20\n#define\t\trOFDM0_XCRxIQImbalance\t0xc24\n#define\t\trOFDM0_XDRxAFE\t\t0xc28\n#define\t\trOFDM0_XDRxIQImbalance\t0xc2c\n\n#define\t\trOFDM0_RxDetector1\t\t\t0xc30  /* PD, BW & SBD\t */ /* DM tune init gain */\n#define\t\trOFDM0_RxDetector2\t\t\t0xc34  /* SBD & Fame Sync. */\n#define\t\trOFDM0_RxDetector3\t\t\t0xc38  /* Frame Sync. */\n#define\t\trOFDM0_RxDetector4\t\t\t0xc3c  /* PD, SBD, Frame Sync & Short-GI */\n\n#define\t\trOFDM0_RxDSP\t\t\t\t0xc40  /* Rx Sync Path */\n#define\t\trOFDM0_CFOandDAGC\t\t0xc44  /* CFO & DAGC */\n#define\t\trOFDM0_CCADropThreshold\t0xc48 /* CCA Drop threshold */\n#define\t\trOFDM0_ECCAThreshold\t\t0xc4c /* energy CCA */\n\n#define\t\trOFDM0_XAAGCCore1\t\t\t0xc50\t/* DIG  */\n#define\t\trOFDM0_XAAGCCore2\t\t\t0xc54\n#define\t\trOFDM0_XBAGCCore1\t\t\t0xc58\n#define\t\trOFDM0_XBAGCCore2\t\t\t0xc5c\n#define\t\trOFDM0_XCAGCCore1\t\t\t0xc60\n#define\t\trOFDM0_XCAGCCore2\t\t\t0xc64\n#define\t\trOFDM0_XDAGCCore1\t\t\t0xc68\n#define\t\trOFDM0_XDAGCCore2\t\t\t0xc6c\n\n#define\t\trOFDM0_AGCParameter1\t\t\t0xc70\n#define\t\trOFDM0_AGCParameter2\t\t\t0xc74\n#define\t\trOFDM0_AGCRSSITable\t\t\t0xc78\n#define\t\trOFDM0_HTSTFAGC\t\t\t\t0xc7c\n\n#define\t\trOFDM0_XATxIQImbalance\t\t0xc80\t/* TX PWR TRACK and DIG */\n#define\t\trOFDM0_XATxAFE\t\t\t\t0xc84\n#define\t\trOFDM0_XBTxIQImbalance\t\t0xc88\n#define\t\trOFDM0_XBTxAFE\t\t\t\t0xc8c\n#define\t\trOFDM0_XCTxIQImbalance\t\t0xc90\n#define\t\trOFDM0_XCTxAFE\t\t\t0xc94\n#define\t\trOFDM0_XDTxIQImbalance\t\t0xc98\n#define\t\trOFDM0_XDTxAFE\t\t\t\t0xc9c\n#define\t\trOFDM0_RxIQExtAnta\t\t\t0xca0\n\n#define\t\trOFDM0_RxHPParameter\t\t\t0xce0\n#define\t\trOFDM0_TxPseudoNoiseWgt\t\t0xce4\n#define\t\trOFDM0_FrameSync\t\t\t\t0xcf0\n#define\t\trOFDM0_DFSReport\t\t\t\t0xcf4\n#define\t\trOFDM0_TxCoeff1\t\t\t\t0xca4\n#define\t\trOFDM0_TxCoeff2\t\t\t\t0xca8\n#define\t\trOFDM0_TxCoeff3\t\t\t\t0xcac\n#define\t\trOFDM0_TxCoeff4\t\t\t\t0xcb0\n#define\t\trOFDM0_TxCoeff5\t\t\t\t0xcb4\n#define\t\trOFDM0_TxCoeff6\t\t\t\t0xcb8\n\n\n/*\n * 7. PageD(0xD00)\n *   */\n#define\t\trOFDM1_LSTF\t\t\t\t\t0xd00\n#define\t\trOFDM1_TRxPathEnable\t\t\t0xd04\n\n#define\t\trOFDM1_CFO\t\t\t\t\t\t0xd08\t/* No setting now */\n#define\t\trOFDM1_CSI1\t\t\t\t\t0xd10\n#define\t\trOFDM1_SBD\t\t\t\t\t\t0xd14\n#define\t\trOFDM1_CSI2\t\t\t\t\t0xd18\n#define\t\trOFDM1_CFOTracking\t\t\t0xd2c\n#define\t\trOFDM1_TRxMesaure1\t\t\t0xd34\n#define\t\trOFDM1_IntfDet\t\t\t\t\t0xd3c\n#define\t\trOFDM1_PseudoNoiseStateAB\t\t0xd50\n#define\t\trOFDM1_PseudoNoiseStateCD\t\t0xd54\n#define\t\trOFDM1_RxPseudoNoiseWgt\t\t0xd58\n\n#define\t\trOFDM_PHYCounter1\t\t\t\t0xda0  /* cca, parity fail */\n#define\t\trOFDM_PHYCounter2\t\t\t\t0xda4  /* rate illegal, crc8 fail */\n#define\t\trOFDM_PHYCounter3\t\t\t\t0xda8  /* MCS not support */\n\n#define\t\trOFDM_ShortCFOAB\t\t\t\t0xdac\t/* No setting now */\n#define\t\trOFDM_ShortCFOCD\t\t\t\t0xdb0\n#define\t\trOFDM_LongCFOAB\t\t\t\t0xdb4\n#define\t\trOFDM_LongCFOCD\t\t\t\t0xdb8\n#define\t\trOFDM_TailCFOAB\t\t\t\t0xdbc\n#define\t\trOFDM_TailCFOCD\t\t\t\t0xdc0\n#define\t\trOFDM_PWMeasure1\t\t0xdc4\n#define\t\trOFDM_PWMeasure2\t\t0xdc8\n#define\t\trOFDM_BWReport\t\t\t\t0xdcc\n#define\t\trOFDM_AGCReport\t\t\t\t0xdd0\n#define\t\trOFDM_RxSNR\t\t\t\t\t0xdd4\n#define\t\trOFDM_RxEVMCSI\t\t\t\t0xdd8\n#define\t\trOFDM_SIGReport\t\t\t\t0xddc\n\n\n/*\n * 8. PageE(0xE00)\n *   */\n#define\t\trTxAGC_Rate18_06\t\t\t\t0xe00\n#define\t\trTxAGC_Rate54_24\t\t\t\t0xe04\n#define\t\trTxAGC_CCK_Mcs32\t\t\t\t0xe08\n#define\t\trTxAGC_Mcs03_Mcs00\t\t\t0xe10\n#define\t\trTxAGC_Mcs07_Mcs04\t\t\t0xe14\n#define\t\trTxAGC_Mcs11_Mcs08\t\t\t0xe18\n#define\t\trTxAGC_Mcs15_Mcs12\t\t\t0xe1c\n\n/* Analog- control in RX_WAIT_CCA : REG: EE0 [Analog- Power & Control Register] */\n#define\t\trRx_Wait_CCCA\t\t\t\t\t0xe70\n#define\t\trAnapar_Ctrl_BB\t\t\t\t\t0xee0\n\n/*\n * 7. RF Register 0x00-0x2E (RF 8256)\n * RF-0222D 0x00-3F\n *\n * Zebra1 */\n#define RTL92SE_FPGA_VERIFY 0\n#define\t\trZebra1_HSSIEnable\t\t\t\t0x0\t/* Useless now */\n#define\t\trZebra1_TRxEnable1\t\t\t\t0x1\n#define\t\trZebra1_TRxEnable2\t\t\t\t0x2\n#define\t\trZebra1_AGC\t\t\t\t\t0x4\n#define\t\trZebra1_ChargePump\t\t\t0x5\n/* #if (RTL92SE_FPGA_VERIFY == 1) */\n#define\t\trZebra1_Channel\t\t\t\t0x7\t/* RF channel switch\n * #else */\n\n/* #endif */\n#define\t\trZebra1_TxGain\t\t\t\t\t0x8\t/* Useless now */\n#define\t\trZebra1_TxLPF\t\t\t\t\t0x9\n#define\t\trZebra1_RxLPF\t\t\t\t\t0xb\n#define\t\trZebra1_RxHPFCorner\t\t\t0xc\n\n/* Zebra4 */\n#define\t\trGlobalCtrl\t\t\t\t\t\t0\t/* Useless now */\n#define\t\trRTL8256_TxLPF\t\t\t\t\t19\n#define\t\trRTL8256_RxLPF\t\t\t\t\t11\n\n/* RTL8258 */\n#define\t\trRTL8258_TxLPF\t\t\t\t\t0x11\t/* Useless now */\n#define\t\trRTL8258_RxLPF\t\t\t\t\t0x13\n#define\t\trRTL8258_RSSILPF\t\t\t\t0xa\n\n/*\n * RL6052 Register definition\n *   */\n#define\t\tRF_AC\t\t\t\t\t\t0x00\t/*  */\n\n#define\t\tRF_IQADJ_G1\t\t\t\t0x01\t/*  */\n#define\t\tRF_IQADJ_G2\t\t\t\t0x02\t/*  */\n#define\t\tRF_POW_TRSW\t\t\t\t0x05\t/*  */\n\n#define\t\tRF_GAIN_RX\t\t\t\t\t0x06\t/*  */\n#define\t\tRF_GAIN_TX\t\t\t\t\t0x07\t/*  */\n\n#define\t\tRF_TXM_IDAC\t\t\t\t0x08\t/*  */\n#define\t\tRF_BS_IQGEN\t\t\t\t0x0F\t/*  */\n\n#define\t\tRF_MODE1\t\t\t\t\t0x10\t/*  */\n#define\t\tRF_MODE2\t\t\t\t\t0x11\t/*  */\n\n#define\t\tRF_RX_AGC_HP\t\t\t\t0x12\t/*  */\n#define\t\tRF_TX_AGC\t\t\t\t\t0x13\t/*  */\n#define\t\tRF_BIAS\t\t\t\t\t\t0x14\t/*  */\n#define\t\tRF_IPA\t\t\t\t\t\t0x15\t/*  */\n#define\t\tRF_TXBIAS\t\t\t\t\t0x16\n#define\t\tRF_POW_ABILITY\t\t\t0x17\t/*  */\n#define\t\tRF_MODE_AG\t\t\t\t0x18\t/*  */\n#define\t\trRfChannel\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define\t\tRF_CHNLBW\t\t\t\t\t0x18\t/* RF channel and BW switch */\n#define\t\tRF_TOP\t\t\t\t\t\t0x19\t/*  */\n\n#define\t\tRF_RX_G1\t\t\t\t\t0x1A\t/*  */\n#define\t\tRF_RX_G2\t\t\t\t\t0x1B\t/*  */\n\n#define\t\tRF_RX_BB2\t\t\t\t\t0x1C\t/*  */\n#define\t\tRF_RX_BB1\t\t\t\t\t0x1D\t/*  */\n\n#define\t\tRF_RCK1\t\t\t\t\t0x1E\t/*  */\n#define\t\tRF_RCK2\t\t\t\t\t0x1F\t/*  */\n\n#define\t\tRF_TX_G1\t\t\t\t\t0x20\t/*  */\n#define\t\tRF_TX_G2\t\t\t\t\t0x21\t/*  */\n#define\t\tRF_TX_G3\t\t\t\t\t0x22\t/*  */\n\n#define\t\tRF_TX_BB1\t\t\t\t\t0x23\t/*  */\n\n#define\t\tRF_T_METER\t\t\t\t\t0x24\t/*  */\n\n#define\t\tRF_SYN_G1\t\t\t\t\t0x25\t/* RF TX Power control */\n#define\t\tRF_SYN_G2\t\t\t\t\t0x26\t/* RF TX Power control */\n#define\t\tRF_SYN_G3\t\t\t\t\t0x27\t/* RF TX Power control */\n#define\t\tRF_SYN_G4\t\t\t\t\t0x28\t/* RF TX Power control */\n#define\t\tRF_SYN_G5\t\t\t\t\t0x29\t/* RF TX Power control */\n#define\t\tRF_SYN_G6\t\t\t\t\t0x2A\t/* RF TX Power control */\n#define\t\tRF_SYN_G7\t\t\t\t\t0x2B\t/* RF TX Power control */\n#define\t\tRF_SYN_G8\t\t\t\t\t0x2C\t/* RF TX Power control */\n\n#define\t\tRF_RCK_OS\t\t\t\t\t0x30\t/* RF TX PA control */\n\n#define\t\tRF_TXPA_G1\t\t\t\t\t0x31\t/* RF TX PA control */\n#define\t\tRF_TXPA_G2\t\t\t\t\t0x32\t/* RF TX PA control */\n#define\t\tRF_TXPA_G3\t\t\t\t\t0x33\t/* RF TX PA control */\n\n/*\n * Bit Mask\n *\n * 1. Page1(0x100) */\n#define\t\tbBBResetB\t\t\t\t\t\t0x100\t/* Useless now? */\n#define\t\tbGlobalResetB\t\t\t\t\t0x200\n#define\t\tbOFDMTxStart\t\t\t\t\t0x4\n#define\t\tbCCKTxStart\t\t\t\t\t\t0x8\n#define\t\tbCRC32Debug\t\t\t\t\t0x100\n#define\t\tbPMACLoopback\t\t\t\t\t0x10\n#define\t\tbTxLSIG\t\t\t\t\t\t\t0xffffff\n#define\t\tbOFDMTxRate\t\t\t\t\t0xf\n#define\t\tbOFDMTxReserved\t\t\t\t0x10\n#define\t\tbOFDMTxLength\t\t\t\t\t0x1ffe0\n#define\t\tbOFDMTxParity\t\t\t\t\t0x20000\n#define\t\tbTxHTSIG1\t\t\t\t\t\t0xffffff\n#define\t\tbTxHTMCSRate\t\t\t\t\t0x7f\n#define\t\tbTxHTBW\t\t\t\t\t\t0x80\n#define\t\tbTxHTLength\t\t\t\t\t0xffff00\n#define\t\tbTxHTSIG2\t\t\t\t\t\t0xffffff\n#define\t\tbTxHTSmoothing\t\t\t\t\t0x1\n#define\t\tbTxHTSounding\t\t\t\t\t0x2\n#define\t\tbTxHTReserved\t\t\t\t\t0x4\n#define\t\tbTxHTAggreation\t\t\t\t0x8\n#define\t\tbTxHTSTBC\t\t\t\t\t\t0x30\n#define\t\tbTxHTAdvanceCoding\t\t\t0x40\n#define\t\tbTxHTShortGI\t\t\t\t\t0x80\n#define\t\tbTxHTNumberHT_LTF\t\t\t0x300\n#define\t\tbTxHTCRC8\t\t\t\t\t\t0x3fc00\n#define\t\tbCounterReset\t\t\t\t\t0x10000\n#define\t\tbNumOfOFDMTx\t\t\t\t\t0xffff\n#define\t\tbNumOfCCKTx\t\t\t\t\t0xffff0000\n#define\t\tbTxIdleInterval\t\t\t\t\t0xffff\n#define\t\tbOFDMService\t\t\t\t\t0xffff0000\n#define\t\tbTxMACHeader\t\t\t\t\t0xffffffff\n#define\t\tbTxDataInit\t\t\t\t\t\t0xff\n#define\t\tbTxHTMode\t\t\t\t\t\t0x100\n#define\t\tbTxDataType\t\t\t\t\t0x30000\n#define\t\tbTxRandomSeed\t\t\t\t\t0xffffffff\n#define\t\tbCCKTxPreamble\t\t\t\t\t0x1\n#define\t\tbCCKTxSFD\t\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxSIG\t\t\t\t\t\t0xff\n#define\t\tbCCKTxService\t\t\t\t\t0xff00\n#define\t\tbCCKLengthExt\t\t\t\t\t0x8000\n#define\t\tbCCKTxLength\t\t\t\t\t0xffff0000\n#define\t\tbCCKTxCRC16\t\t\t\t\t0xffff\n#define\t\tbCCKTxStatus\t\t\t\t\t0x1\n#define\t\tbOFDMTxStatus\t\t\t\t\t0x2\n\n#define\t\tIS_BB_REG_OFFSET_92S(_Offset)\t\t((_Offset >= 0x800) && (_Offset <= 0xfff))\n\n/* 2. Page8(0x800) */\n#define\t\tbRFMOD\t\t\t\t\t\t\t0x1\t/* Reg 0x800 rFPGA0_RFMOD */\n#define\t\tbJapanMode\t\t\t\t\t\t0x2\n#define\t\tbCCKTxSC\t\t\t\t\t\t0x30\n#define\t\tbCCKEn\t\t\t\t\t\t\t0x1000000\n#define\t\tbOFDMEn\t\t\t\t\t\t0x2000000\n\n#define\t\tbOFDMRxADCPhase           \t\t0x10000\t/* Useless now */\n#define\t\tbOFDMTxDACPhase\t\t0x40000\n#define\t\tbXATxAGC\t\t\t0x3f\n\n#define\t\tbXBTxAGC                  \t\t\t0xf00\t/* Reg 80c rFPGA0_TxGainStage */\n#define\t\tbXCTxAGC\t\t\t0xf000\n#define\t\tbXDTxAGC\t\t\t0xf0000\n\n#define\t\tbPAStart                  \t\t\t0xf0000000\t/* Useless now */\n#define\t\tbTRStart\t\t\t0x00f00000\n#define\t\tbRFStart\t\t\t0x0000f000\n#define\t\tbBBStart\t\t\t0x000000f0\n#define\t\tbBBCCKStart\t\t0x0000000f\n#define\t\tbPAEnd                    \t\t\t0xf          /* Reg0x814 */\n#define\t\tbTREnd\t\t\t0x0f000000\n#define\t\tbRFEnd\t\t\t0x000f0000\n#define\t\tbCCAMask                  \t\t\t0x000000f0   /* T2R */\n#define\t\tbR2RCCAMask\t\t0x00000f00\n#define\t\tbHSSI_R2TDelay\t\t0xf8000000\n#define\t\tbHSSI_T2RDelay\t\t0xf80000\n#define\t\tbContTxHSSI               \t\t0x400     /* chane gain at continue Tx */\n#define\t\tbIGFromCCK\t\t0x200\n#define\t\tbAGCAddress\t\t0x3f\n#define\t\tbRxHPTx\t\t\t0x7000\n#define\t\tbRxHPT2R\t\t\t0x38000\n#define\t\tbRxHPCCKIni\t\t0xc0000\n#define\t\tbAGCTxCode\t\t0xc00000\n#define\t\tbAGCRxCode\t\t0x300000\n\n#define\t\tb3WireDataLength          \t\t0x800\t/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */\n#define\t\tb3WireAddressLength\t\t0x400\n\n#define\t\tb3WireRFPowerDown         \t\t0x1\t/* Useless now\n * #define bHWSISelect\t\t0x8 */\n#define\t\tb5GPAPEPolarity\t\t0x40000000\n#define\t\tb2GPAPEPolarity\t\t0x80000000\n#define\t\tbRFSW_TxDefaultAnt\t\t0x3\n#define\t\tbRFSW_TxOptionAnt\t\t0x30\n#define\t\tbRFSW_RxDefaultAnt\t\t0x300\n#define\t\tbRFSW_RxOptionAnt\t\t0x3000\n#define\t\tbRFSI_3WireData\t\t0x1\n#define\t\tbRFSI_3WireClock\t\t0x2\n#define\t\tbRFSI_3WireLoad\t\t0x4\n#define\t\tbRFSI_3WireRW\t\t0x8\n#define\t\tbRFSI_3Wire\t\t\t0xf\n\n#define\t\tbRFSI_RFENV               \t\t0x10\t/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */\n\n#define\t\tbRFSI_TRSW                \t\t0x20\t/* Useless now */\n#define\t\tbRFSI_TRSWB\t\t0x40\n#define\t\tbRFSI_ANTSW\t\t0x100\n#define\t\tbRFSI_ANTSWB\t\t0x200\n#define\t\tbRFSI_PAPE\t\t\t0x400\n#define\t\tbRFSI_PAPE5G\t\t0x800\n#define\t\tbBandSelect\t\t\t0x1\n#define\t\tbHTSIG2_GI\t\t\t0x80\n#define\t\tbHTSIG2_Smoothing\t\t0x01\n#define\t\tbHTSIG2_Sounding\t\t0x02\n#define\t\tbHTSIG2_Aggreaton\t\t0x08\n#define\t\tbHTSIG2_STBC\t\t0x30\n#define\t\tbHTSIG2_AdvCoding\t\t0x40\n#define\t\tbHTSIG2_NumOfHTLTF\t0x300\n#define\t\tbHTSIG2_CRC8\t\t0x3fc\n#define\t\tbHTSIG1_MCS\t\t0x7f\n#define\t\tbHTSIG1_BandWidth\t\t0x80\n#define\t\tbHTSIG1_HTLength\t\t0xffff\n#define\t\tbLSIG_Rate\t\t\t0xf\n#define\t\tbLSIG_Reserved\t\t0x10\n#define\t\tbLSIG_Length\t\t0x1fffe\n#define\t\tbLSIG_Parity\t\t\t0x20\n#define\t\tbCCKRxPhase\t\t0x4\n#if (RTL92SE_FPGA_VERIFY == 1)\n\t#define\t\tbLSSIReadAddress          \t\t0x3f000000   /* LSSI \"Read\" Address\t */ /* Reg 0x824 rFPGA0_XA_HSSIParameter2 */\n#else\n\t#define\t\tbLSSIReadAddress          \t\t0x7f800000   /* T65 RF */\n#endif\n#define\t\tbLSSIReadEdge             \t\t0x80000000   /* LSSI \"Read\" edge signal */\n#if (RTL92SE_FPGA_VERIFY == 1)\n\t#define\t\tbLSSIReadBackData         \t\t0xfff\t\t/* Reg 0x8a0 rFPGA0_XA_LSSIReadBack */\n#else\n\t#define\t\tbLSSIReadBackData         \t\t0xfffff\t\t/* T65 RF */\n#endif\n#define\t\tbLSSIReadOKFlag           \t\t0x1000\t/* Useless now */\n#define\t\tbCCKSampleRate            \t\t0x8       /* 0: 44MHz, 1:88MHz      \t\t */\n#define\t\tbRegulator0Standby\t\t0x1\n#define\t\tbRegulatorPLLStandby\t\t0x2\n#define\t\tbRegulator1Standby\t\t0x4\n#define\t\tbPLLPowerUp\t\t0x8\n#define\t\tbDPLLPowerUp\t\t0x10\n#define\t\tbDA10PowerUp\t\t0x20\n#define\t\tbAD7PowerUp\t\t0x200\n#define\t\tbDA6PowerUp\t\t0x2000\n#define\t\tbXtalPowerUp\t\t0x4000\n#define\t\tb40MDClkPowerUP\t\t0x8000\n#define\t\tbDA6DebugMode\t\t0x20000\n#define\t\tbDA6Swing\t\t\t0x380000\n\n#define\t\tbADClkPhase               \t\t0x4000000\t/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */\n\n#define\t\tb80MClkDelay              \t\t0x18000000\t/* Useless */\n#define\t\tbAFEWatchDogEnable\t\t0x20000000\n\n#define\t\tbXtalCap01                \t\t\t0xc0000000\t/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */\n#define\t\tbXtalCap23\t\t\t0x3\n#define\t\tbXtalCap92x\t\t\t\t\t0x0f000000\n#define\t\tbXtalCap\t\t\t0x0f000000\n\n#define\t\tbIntDifClkEnable          \t\t0x400\t/* Useless */\n#define\t\tbExtSigClkEnable\t\t0x800\n#define\t\tbBandgapMbiasPowerUp\t0x10000\n#define\t\tbAD11SHGain\t\t0xc0000\n#define\t\tbAD11InputRange\t\t0x700000\n#define\t\tbAD11OPCurrent\t\t0x3800000\n#define\t\tbIPathLoopback\t\t0x4000000\n#define\t\tbQPathLoopback\t\t0x8000000\n#define\t\tbAFELoopback\t\t0x10000000\n#define\t\tbDA10Swing\t\t0x7e0\n#define\t\tbDA10Reverse\t\t0x800\n#define\t\tbDAClkSource\t\t0x1000\n#define\t\tbAD7InputRange\t\t0x6000\n#define\t\tbAD7Gain\t\t\t0x38000\n#define\t\tbAD7OutputCMMode\t\t0x40000\n#define\t\tbAD7InputCMMode\t\t0x380000\n#define\t\tbAD7Current\t\t\t0xc00000\n#define\t\tbRegulatorAdjust\t\t0x7000000\n#define\t\tbAD11PowerUpAtTx\t\t0x1\n#define\t\tbDA10PSAtTx\t\t0x10\n#define\t\tbAD11PowerUpAtRx\t\t0x100\n#define\t\tbDA10PSAtRx\t\t0x1000\n#define\t\tbCCKRxAGCFormat\t\t0x200\n#define\t\tbPSDFFTSamplepPoint\t\t0xc000\n#define\t\tbPSDAverageNum\t\t0x3000\n#define\t\tbIQPathControl\t\t0xc00\n#define\t\tbPSDFreq\t\t\t0x3ff\n#define\t\tbPSDAntennaPath\t\t0x30\n#define\t\tbPSDIQSwitch\t\t0x40\n#define\t\tbPSDRxTrigger\t\t0x400000\n#define\t\tbPSDTxTrigger\t\t0x80000000\n#define\t\tbPSDSineToneScale\t\t0x7f000000\n#define\t\tbPSDReport\t\t\t0xffff\n\n/* 3. Page9(0x900) */\n#define\t\tbOFDMTxSC                 \t\t0x30000000\t/* Useless */\n#define\t\tbCCKTxOn\t\t\t0x1\n#define\t\tbOFDMTxOn\t\t0x2\n#define\t\tbDebugPage                \t\t0xfff  /* reset debug page and also HWord, LWord */\n#define\t\tbDebugItem                \t\t0xff   /* reset debug page and LWord */\n#define\t\tbAntL\t\t\t0x10\n#define\t\tbAntNonHT\t\t\t\t0x100\n#define\t\tbAntHT1\t\t\t0x1000\n#define\t\tbAntHT2\t\t\t0x10000\n#define\t\tbAntHT1S1\t\t\t0x100000\n#define\t\tbAntNonHTS1\t\t0x1000000\n\n/* 4. PageA(0xA00) */\n#define\t\tbCCKBBMode                \t\t0x3\t/* Useless */\n#define\t\tbCCKTxPowerSaving\t\t0x80\n#define\t\tbCCKRxPowerSaving\t\t0x40\n\n#define\t\tbCCKSideBand              \t\t0x10\t/* Reg 0xa00 rCCK0_System 20/40 switch */\n\n#define\t\tbCCKScramble              \t\t0x8\t/* Useless */\n#define\t\tbCCKAntDiversity\t\t\t0x8000\n#define\t\tbCCKCarrierRecovery\t\t0x4000\n#define\t\tbCCKTxRate\t\t\t0x3000\n#define\t\tbCCKDCCancel\t\t0x0800\n#define\t\tbCCKISICancel\t\t0x0400\n#define\t\tbCCKMatchFilter\t\t0x0200\n#define\t\tbCCKEqualizer\t\t0x0100\n#define\t\tbCCKPreambleDetect\t\t0x800000\n#define\t\tbCCKFastFalseCCA\t\t0x400000\n#define\t\tbCCKChEstStart\t\t0x300000\n#define\t\tbCCKCCACount\t\t0x080000\n#define\t\tbCCKcs_lim\t\t\t0x070000\n#define\t\tbCCKBistMode\t\t0x80000000\n#define\t\tbCCKCCAMask\t\t0x40000000\n#define\t\tbCCKTxDACPhase\t\t0x4\n#define\t\tbCCKRxADCPhase         \t   \t0x20000000   /* r_rx_clk */\n#define\t\tbCCKr_cp_mode0\t\t0x0100\n#define\t\tbCCKTxDCOffset\t\t0xf0\n#define\t\tbCCKRxDCOffset\t\t0xf\n#define\t\tbCCKCCAMode\t\t0xc000\n#define\t\tbCCKFalseCS_lim\t\t0x3f00\n#define\t\tbCCKCS_ratio\t\t0xc00000\n#define\t\tbCCKCorgBit_sel\t\t0x300000\n#define\t\tbCCKPD_lim\t\t\t0x0f0000\n#define\t\tbCCKNewCCA\t\t0x80000000\n#define\t\tbCCKRxHPofIG\t\t0x8000\n#define\t\tbCCKRxIG\t\t\t0x7f00\n#define\t\tbCCKLNAPolarity\t\t0x800000\n#define\t\tbCCKRx1stGain\t\t0x7f0000\n#define\t\tbCCKRFExtend              \t\t0x20000000 /* CCK Rx Iinital gain polarity */\n#define\t\tbCCKRxAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKRxAGCSatCount\t\t0xe0\n#define\t\tbCCKRxRFSettle            \t\t0x1f       /* AGCsamp_dly */\n#define\t\tbCCKFixedRxAGC\t\t0x8000\n/* #define bCCKRxAGCFormat\t\t0x4000 */   /* remove to HSSI register 0x824 */\n#define\t\tbCCKAntennaPolarity\t\t0x2000\n#define\t\tbCCKTxFilterType\t\t0x0c00\n#define\t\tbCCKRxAGCReportType\t\t0x0300\n#define\t\tbCCKRxDAGCEn\t\t0x80000000\n#define\t\tbCCKRxDAGCPeriod\t\t0x20000000\n#define\t\tbCCKRxDAGCSatLevel\t\t0x1f000000\n#define\t\tbCCKTimingRecovery\t\t0x800000\n#define\t\tbCCKTxC0\t\t\t0x3f0000\n#define\t\tbCCKTxC1\t\t\t0x3f000000\n#define\t\tbCCKTxC2\t\t\t0x3f\n#define\t\tbCCKTxC3\t\t\t0x3f00\n#define\t\tbCCKTxC4\t\t\t0x3f0000\n#define\t\tbCCKTxC5\t\t\t0x3f000000\n#define\t\tbCCKTxC6\t\t\t0x3f\n#define\t\tbCCKTxC7\t\t\t0x3f00\n#define\t\tbCCKDebugPort\t\t0xff0000\n#define\t\tbCCKDACDebug\t\t0x0f000000\n#define\t\tbCCKFalseAlarmEnable\t\t0x8000\n#define\t\tbCCKFalseAlarmRead\t\t0x4000\n#define\t\tbCCKTRSSI\t\t\t0x7f\n#define\t\tbCCKRxAGCReport\t\t0xfe\n#define\t\tbCCKRxReport_AntSel\t\t0x80000000\n#define\t\tbCCKRxReport_MFOff\t\t0x40000000\n#define\t\tbCCKRxRxReport_SQLoss\t0x20000000\n#define\t\tbCCKRxReport_Pktloss\t\t0x10000000\n#define\t\tbCCKRxReport_Lockedbit\t0x08000000\n#define\t\tbCCKRxReport_RateError\t0x04000000\n#define\t\tbCCKRxReport_RxRate\t\t0x03000000\n#define\t\tbCCKRxFACounterLower\t0xff\n#define\t\tbCCKRxFACounterUpper\t0xff000000\n#define\t\tbCCKRxHPAGCStart\t\t0xe000\n#define\t\tbCCKRxHPAGCFinal\t\t0x1c00\n#define\t\tbCCKRxFalseAlarmEnable\t0x8000\n#define\t\tbCCKFACounterFreeze\t\t0x4000\n#define\t\tbCCKTxPathSel\t\t0x10000000\n#define\t\tbCCKDefaultRxPath\t\t0xc000000\n#define\t\tbCCKOptionRxPath\t\t0x3000000\n\n/* 5. PageC(0xC00) */\n#define\t\tbNumOfSTF                \t\t\t0x3\t/* Useless */\n#define\t\tbShift_L\t\t\t0xc0\n#define\t\tbGI_TH\t\t\t0xc\n#define\t\tbRxPathA\t\t\t0x1\n#define\t\tbRxPathB\t\t\t0x2\n#define\t\tbRxPathC\t\t\t0x4\n#define\t\tbRxPathD\t\t\t0x8\n#define\t\tbTxPathA\t\t\t0x1\n#define\t\tbTxPathB\t\t\t0x2\n#define\t\tbTxPathC\t\t\t0x4\n#define\t\tbTxPathD\t\t\t0x8\n#define\t\tbTRSSIFreq\t\t\t0x200\n#define\t\tbADCBackoff\t\t\t0x3000\n#define\t\tbDFIRBackoff\t\t\t0xc000\n#define\t\tbTRSSILatchPhase\t\t0x10000\n#define\t\tbRxIDCOffset\t\t\t0xff\n#define\t\tbRxQDCOffset\t\t\t0xff00\n#define\t\tbRxDFIRMode\t\t0x1800000\n#define\t\tbRxDCNFType\t\t0xe000000\n#define\t\tbRXIQImb_A\t\t\t0x3ff\n#define\t\tbRXIQImb_B\t\t\t0xfc00\n#define\t\tbRXIQImb_C\t\t\t0x3f0000\n#define\t\tbRXIQImb_D\t\t\t0xffc00000\n#define\t\tbDC_dc_Notch\t\t0x60000\n#define\t\tbRxNBINotch\t\t\t0x1f000000\n#define\t\tbPD_TH\t\t\t0xf\n#define\t\tbPD_TH_Opt2\t\t0xc000\n#define\t\tbPWED_TH\t\t\t0x700\n#define\t\tbIfMF_Win_L\t\t\t0x800\n#define\t\tbPD_Option\t\t\t0x1000\n#define\t\tbMF_Win_L\t\t\t0xe000\n#define\t\tbBW_Search_L\t\t0x30000\n#define\t\tbwin_enh_L\t\t\t0xc0000\n#define\t\tbBW_TH\t\t\t0x700000\n#define\t\tbED_TH2\t\t\t0x3800000\n#define\t\tbBW_option\t\t\t0x4000000\n#define\t\tbRatio_TH\t\t\t0x18000000\n#define\t\tbWindow_L\t\t\t0xe0000000\n#define\t\tbSBD_Option\t\t\t0x1\n#define\t\tbFrame_TH\t\t\t0x1c\n#define\t\tbFS_Option\t\t\t0x60\n#define\t\tbDC_Slope_check\t\t0x80\n#define\t\tbFGuard_Counter_DC_L\t\t0xe00\n#define\t\tbFrame_Weight_Short\t\t0x7000\n#define\t\tbSub_Tune\t\t\t0xe00000\n#define\t\tbFrame_DC_Length\t\t0xe000000\n#define\t\tbSBD_start_offset\t\t0x30000000\n#define\t\tbFrame_TH_2\t\t0x7\n#define\t\tbFrame_GI2_TH\t\t0x38\n#define\t\tbGI2_Sync_en\t\t0x40\n#define\t\tbSarch_Short_Early\t\t0x300\n#define\t\tbSarch_Short_Late\t\t0xc00\n#define\t\tbSarch_GI2_Late\t\t0x70000\n#define\t\tbCFOAntSum\t\t0x1\n#define\t\tbCFOAcc\t\t\t0x2\n#define\t\tbCFOStartOffset\t\t0xc\n#define\t\tbCFOLookBack\t\t0x70\n#define\t\tbCFOSumWeight\t\t0x80\n#define\t\tbDAGCEnable\t\t\t0x10000\n#define\t\tbTXIQImb_A\t\t\t0x3ff\n#define\t\tbTXIQImb_B\t\t\t0xfc00\n#define\t\tbTXIQImb_C\t\t\t0x3f0000\n#define\t\tbTXIQImb_D\t\t\t0xffc00000\n#define\t\tbTxIDCOffset\t\t\t0xff\n#define\t\tbTxQDCOffset\t\t\t0xff00\n#define\t\tbTxDFIRMode\t\t0x10000\n#define\t\tbTxPesudoNoiseOn\t\t0x4000000\n#define\t\tbTxPesudoNoise_A\t\t0xff\n#define\t\tbTxPesudoNoise_B\t\t0xff00\n#define\t\tbTxPesudoNoise_C\t\t0xff0000\n#define\t\tbTxPesudoNoise_D\t\t0xff000000\n#define\t\tbCCADropOption\t\t0x20000\n#define\t\tbCCADropThres\t\t0xfff00000\n#define\t\tbEDCCA_H\t\t\t0xf\n#define\t\tbEDCCA_L\t\t\t0xf0\n#define\t\tbLambda_ED               0x300\n#define\t\tbRxInitialGain           0x7f\n#define\t\tbRxAntDivEn              0x80\n#define\t\tbRxAGCAddressForLNA      0x7f00\n#define\t\tbRxHighPowerFlow         0x8000\n#define\t\tbRxAGCFreezeThres        0xc0000\n#define\t\tbRxFreezeStep_AGC1       0x300000\n#define\t\tbRxFreezeStep_AGC2       0xc00000\n#define\t\tbRxFreezeStep_AGC3       0x3000000\n#define\t\tbRxFreezeStep_AGC0       0xc000000\n#define\t\tbRxRssi_Cmp_En           0x10000000\n#define\t\tbRxQuickAGCEn            0x20000000\n#define\t\tbRxAGCFreezeThresMode    0x40000000\n#define\t\tbRxOverFlowCheckType     0x80000000\n#define\t\tbRxAGCShift              0x7f\n#define\t\tbTRSW_Tri_Only           0x80\n#define\t\tbPowerThres              0x300\n#define\t\tbRxAGCEn                 0x1\n#define\t\tbRxAGCTogetherEn         0x2\n#define\t\tbRxAGCMin                0x4\n#define\t\tbRxHP_Ini                0x7\n#define\t\tbRxHP_TRLNA              0x70\n#define\t\tbRxHP_RSSI               0x700\n#define\t\tbRxHP_BBP1               0x7000\n#define\t\tbRxHP_BBP2               0x70000\n#define\t\tbRxHP_BBP3               0x700000\n#define\t\tbRSSI_H                  0x7f0000     /* the threshold for high power */\n#define\t\tbRSSI_Gen                0x7f000000   /* the threshold for ant diversity */\n#define\t\tbRxSettle_TRSW           0x7\n#define\t\tbRxSettle_LNA            0x38\n#define\t\tbRxSettle_RSSI           0x1c0\n#define\t\tbRxSettle_BBP            0xe00\n#define\t\tbRxSettle_RxHP           0x7000\n#define\t\tbRxSettle_AntSW_RSSI     0x38000\n#define\t\tbRxSettle_AntSW          0xc0000\n#define\t\tbRxProcessTime_DAGC      0x300000\n#define\t\tbRxSettle_HSSI           0x400000\n#define\t\tbRxProcessTime_BBPPW     0x800000\n#define\t\tbRxAntennaPowerShift     0x3000000\n#define\t\tbRSSITableSelect         0xc000000\n#define\t\tbRxHP_Final              0x7000000\n#define\t\tbRxHTSettle_BBP          0x7\n#define\t\tbRxHTSettle_HSSI         0x8\n#define\t\tbRxHTSettle_RxHP         0x70\n#define\t\tbRxHTSettle_BBPPW        0x80\n#define\t\tbRxHTSettle_Idle         0x300\n#define\t\tbRxHTSettle_Reserved     0x1c00\n#define\t\tbRxHTRxHPEn              0x8000\n#define\t\tbRxHTAGCFreezeThres      0x30000\n#define\t\tbRxHTAGCTogetherEn       0x40000\n#define\t\tbRxHTAGCMin              0x80000\n#define\t\tbRxHTAGCEn               0x100000\n#define\t\tbRxHTDAGCEn              0x200000\n#define\t\tbRxHTRxHP_BBP            0x1c00000\n#define\t\tbRxHTRxHP_Final          0xe0000000\n#define\t\tbRxPWRatioTH             0x3\n#define\t\tbRxPWRatioEn             0x4\n#define\t\tbRxMFHold                0x3800\n#define\t\tbRxPD_Delay_TH1          0x38\n#define\t\tbRxPD_Delay_TH2          0x1c0\n#define\t\tbRxPD_DC_COUNT_MAX       0x600\n/* #define bRxMF_Hold               0x3800 */\n#define\t\tbRxPD_Delay_TH           0x8000\n#define\t\tbRxProcess_Delay         0xf0000\n#define\t\tbRxSearchrange_GI2_Early 0x700000\n#define\t\tbRxFrame_Guard_Counter_L 0x3800000\n#define\t\tbRxSGI_Guard_L           0xc000000\n#define\t\tbRxSGI_Search_L          0x30000000\n#define\t\tbRxSGI_TH                0xc0000000\n#define\t\tbDFSCnt0                 0xff\n#define\t\tbDFSCnt1                 0xff00\n#define\t\tbDFSFlag                 0xf0000\n#define\t\tbMFWeightSum             0x300000\n#define\t\tbMinIdxTH                0x7f000000\n#define\t\tbDAFormat                0x40000\n#define\t\tbTxChEmuEnable           0x01000000\n#define\t\tbTRSWIsolation_A         0x7f\n#define\t\tbTRSWIsolation_B         0x7f00\n#define\t\tbTRSWIsolation_C         0x7f0000\n#define\t\tbTRSWIsolation_D         0x7f000000\n#define\t\tbExtLNAGain              0x7c00\n\n/* 6. PageE(0xE00) */\n#define\t\tbSTBCEn                  0x4\t/* Useless */\n#define\t\tbAntennaMapping          0x10\n#define\t\tbNss                     0x20\n#define\t\tbCFOAntSumD              0x200\n#define\t\tbPHYCounterReset         0x8000000\n#define\t\tbCFOReportGet            0x4000000\n#define\t\tbOFDMContinueTx          0x10000000\n#define\t\tbOFDMSingleCarrier       0x20000000\n#define\t\tbOFDMSingleTone          0x40000000\n/* #define bRxPath1                 0x01 */\n/* #define bRxPath2                 0x02 */\n/* #define bRxPath3                 0x04 */\n/* #define bRxPath4                 0x08 */\n/* #define bTxPath1                 0x10 */\n/* #define bTxPath2                 0x20 */\n#define\t\tbHTDetect                0x100\n#define\t\tbCFOEn                   0x10000\n#define\t\tbCFOValue                0xfff00000\n#define\t\tbSigTone_Re              0x3f\n#define\t\tbSigTone_Im              0x7f00\n#define\t\tbCounter_CCA             0xffff\n#define\t\tbCounter_ParityFail      0xffff0000\n#define\t\tbCounter_RateIllegal     0xffff\n#define\t\tbCounter_CRC8Fail        0xffff0000\n#define\t\tbCounter_MCSNoSupport    0xffff\n#define\t\tbCounter_FastSync        0xffff\n#define\t\tbShortCFO                0xfff\n#define\t\tbShortCFOTLength         12   /* total */\n#define\t\tbShortCFOFLength         11   /* fraction */\n#define\t\tbLongCFO                 0x7ff\n#define\t\tbLongCFOTLength          11\n#define\t\tbLongCFOFLength          11\n#define\t\tbTailCFO                 0x1fff\n#define\t\tbTailCFOTLength          13\n#define\t\tbTailCFOFLength          12\n#define\t\tbmax_en_pwdB             0xffff\n#define\t\tbCC_power_dB             0xffff0000\n#define\t\tbnoise_pwdB              0xffff\n#define\t\tbPowerMeasTLength        10\n#define\t\tbPowerMeasFLength        3\n#define\t\tbRx_HT_BW                0x1\n#define\t\tbRxSC                    0x6\n#define\t\tbRx_HT                   0x8\n#define\t\tbNB_intf_det_on          0x1\n#define\t\tbIntf_win_len_cfg        0x30\n#define\t\tbNB_Intf_TH_cfg          0x1c0\n#define\t\tbRFGain                  0x3f\n#define\t\tbTableSel                0x40\n#define\t\tbTRSW                    0x80\n#define\t\tbRxSNR_A                 0xff\n#define\t\tbRxSNR_B                 0xff00\n#define\t\tbRxSNR_C                 0xff0000\n#define\t\tbRxSNR_D                 0xff000000\n#define\t\tbSNREVMTLength           8\n#define\t\tbSNREVMFLength           1\n#define\t\tbCSI1st                  0xff\n#define\t\tbCSI2nd                  0xff00\n#define\t\tbRxEVM1st                0xff0000\n#define\t\tbRxEVM2nd                0xff000000\n#define\t\tbSIGEVM                  0xff\n#define\t\tbPWDB                    0xff00\n#define\t\tbSGIEN                   0x10000\n\n#define\t\tbSFactorQAM1             0xf\t/* Useless */\n#define\t\tbSFactorQAM2             0xf0\n#define\t\tbSFactorQAM3             0xf00\n#define\t\tbSFactorQAM4             0xf000\n#define\t\tbSFactorQAM5             0xf0000\n#define\t\tbSFactorQAM6             0xf0000\n#define\t\tbSFactorQAM7             0xf00000\n#define\t\tbSFactorQAM8             0xf000000\n#define\t\tbSFactorQAM9             0xf0000000\n#define\t\tbCSIScheme               0x100000\n\n#define\t\tbNoiseLvlTopSet          0x3\t/* Useless */\n#define\t\tbChSmooth                0x4\n#define\t\tbChSmoothCfg1            0x38\n#define\t\tbChSmoothCfg2            0x1c0\n#define\t\tbChSmoothCfg3            0xe00\n#define\t\tbChSmoothCfg4            0x7000\n#define\t\tbMRCMode                 0x800000\n#define\t\tbTHEVMCfg                0x7000000\n\n#define\t\tbLoopFitType             0x1\t/* Useless */\n#define\t\tbUpdCFO                  0x40\n#define\t\tbUpdCFOOffData           0x80\n#define\t\tbAdvUpdCFO               0x100\n#define\t\tbAdvTimeCtrl             0x800\n#define\t\tbUpdClko                 0x1000\n#define\t\tbFC                      0x6000\n#define\t\tbTrackingMode            0x8000\n#define\t\tbPhCmpEnable             0x10000\n#define\t\tbUpdClkoLTF              0x20000\n#define\t\tbComChCFO                0x40000\n#define\t\tbCSIEstiMode             0x80000\n#define\t\tbAdvUpdEqz               0x100000\n#define\t\tbUChCfg                  0x7000000\n#define\t\tbUpdEqz                  0x8000000\n\n#define\t\tbTxAGCRate18_06\t\t\t0x7f7f7f7f\t/* Useless */\n#define\t\tbTxAGCRate54_24\t\t\t0x7f7f7f7f\n#define\t\tbTxAGCRateMCS32\t\t\t0x7f\n#define\t\tbTxAGCRateCCK\t\t\t0x7f00\n#define\t\tbTxAGCRateMCS3_MCS0\t\t0x7f7f7f7f\n#define\t\tbTxAGCRateMCS7_MCS4\t\t0x7f7f7f7f\n#define\t\tbTxAGCRateMCS11_MCS8\t0x7f7f7f7f\n#define\t\tbTxAGCRateMCS15_MCS12\t0x7f7f7f7f\n\n/* Rx Pseduo noise */\n#define\t\tbRxPesudoNoiseOn         0x20000000\t/* Useless */\n#define\t\tbRxPesudoNoise_A         0xff\n#define\t\tbRxPesudoNoise_B         0xff00\n#define\t\tbRxPesudoNoise_C         0xff0000\n#define\t\tbRxPesudoNoise_D         0xff000000\n#define\t\tbPesudoNoiseState_A      0xffff\n#define\t\tbPesudoNoiseState_B      0xffff0000\n#define\t\tbPesudoNoiseState_C      0xffff\n#define\t\tbPesudoNoiseState_D      0xffff0000\n\n/* 7. RF Register\n * Zebra1 */\n#define\t\tbZebra1_HSSIEnable        0x8\t\t/* Useless */\n#define\t\tbZebra1_TRxControl        0xc00\n#define\t\tbZebra1_TRxGainSetting    0x07f\n#define\t\tbZebra1_RxCorner          0xc00\n#define\t\tbZebra1_TxChargePump      0x38\n#define\t\tbZebra1_RxChargePump      0x7\n#define\t\tbZebra1_ChannelNum        0xf80\n#define\t\tbZebra1_TxLPFBW           0x400\n#define\t\tbZebra1_RxLPFBW           0x600\n\n/* Zebra4 */\n#define\t\tbRTL8256RegModeCtrl1      0x100\t/* Useless */\n#define\t\tbRTL8256RegModeCtrl0      0x40\n#define\t\tbRTL8256_TxLPFBW          0x18\n#define\t\tbRTL8256_RxLPFBW          0x600\n\n/* RTL8258 */\n#define\t\tbRTL8258_TxLPFBW          0xc\t/* Useless */\n#define\t\tbRTL8258_RxLPFBW          0xc00\n#define\t\tbRTL8258_RSSILPFBW        0xc0\n\n\n/*\n * Other Definition\n *   */\n\n/* byte endable for sb_write */\n#define\t\tbByte0                    0x1\t/* Useless */\n#define\t\tbByte1                    0x2\n#define\t\tbByte2                    0x4\n#define\t\tbByte3                    0x8\n#define\t\tbWord0                    0x3\n#define\t\tbWord1                    0xc\n#define\t\tbDWord                    0xf\n\n/* for PutRegsetting & GetRegSetting BitMask */\n#define\t\tbMaskByte0\t\t0xff\t/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */\n#define\t\tbMaskByte1\t\t0xff00\n#define\t\tbMaskByte2\t\t0xff0000\n#define\t\tbMaskByte3\t\t0xff000000\n#define\t\tbMaskHWord\t0xffff0000\n#define\t\tbMaskLWord\t\t0x0000ffff\n#define\t\tbMaskDWord\t0xffffffff\n#define\t\tbMaskH4Bits\t\t0xf0000000\n#define\t\tbMaskH3Bytes\t0xffffff00\n#define\t\tbMaskOFDM_D\t0xffc00000\n#define\t\tbMaskCCK\t\t0x3f3f3f3f\n#define\t\tbMask12Bits\t\t0xfff\n\n/* for PutRFRegsetting & GetRFRegSetting BitMask */\n#if (RTL92SE_FPGA_VERIFY == 1)\n/* #define\t\tbMask12Bits               0xfff */\t/* RF Reg mask bits */\n/* #define\t\tbMask20Bits               0xfff */\t/* RF Reg mask bits T65 RF */\n#define\t\tbRFRegOffsetMask\t0xfff\n#else\n/* #define\t\tbMask12Bits               0xfffff */\t/* RF Reg mask bits */\n/* #define\t\tbMask20Bits               0xfffff */\t/* RF Reg mask bits T65 RF */\n#define\t\tbRFRegOffsetMask\t0xfffff\n#endif\n#define\t\tbEnable                   0x1\t/* Useless */\n#define\t\tbDisable                  0x0\n\n#define\t\tLeftAntenna               0x0\t/* Useless */\n#define\t\tRightAntenna              0x1\n\n#define\t\ttCheckTxStatus            500   /* 500ms */ /* Useless */\n#define\t\ttUpdateRxCounter          100   /* 100ms */\n\n#define\t\trateCCK     0\t/* Useless */\n#define\t\trateOFDM    1\n#define\t\trateHT      2\n\n/* define Register-End */\n#define\t\tbPMAC_End                 0x1ff\t/* Useless */\n#define\t\tbFPGAPHY0_End             0x8ff\n#define\t\tbFPGAPHY1_End             0x9ff\n#define\t\tbCCKPHY0_End              0xaff\n#define\t\tbOFDMPHY0_End             0xcff\n#define\t\tbOFDMPHY1_End             0xdff\n\n/* define max debug item in each debug page\n * #define bMaxItem_FPGA_PHY0        0x9\n * #define bMaxItem_FPGA_PHY1        0x3\n * #define bMaxItem_PHY_11B          0x16\n * #define bMaxItem_OFDM_PHY0        0x29\n * #define bMaxItem_OFDM_PHY1        0x0 */\n\n#define\t\tbPMACControl\t0x0\t\t/* Useless */\n#define\t\tbWMACControl\t0x1\n#define\t\tbWNICControl\t0x2\n\n#if 0\n#define\t\tANTENNA_A\t0x1\t/* Useless */\n#define\t\tANTENNA_B\t0x2\n#define\t\tANTENNA_AB\t0x3\t/* ANTENNA_A | ANTENNA_B */\n\n#define\t\tANTENNA_C\t0x4\n#define\t\tANTENNA_D\t0x8\n#endif\n\n#define RCR_AAP\t\t\tBIT(0)\t\t\t\t/* accept all physical address */\n#define RCR_APM\t\t\tBIT(1)\t\t\t\t/* accept physical match */\n#define RCR_AM\t\t\tBIT(2)\t\t\t\t/* accept multicast */\n#define RCR_AB\t\t\tBIT(3)\t\t\t\t/* accept broadcast */\n#define RCR_ACRC32\t\tBIT(5)\t\t\t\t/* accept error packet */\n#define RCR_9356SEL\t\tBIT(6)\n#define RCR_AICV\t\tBIT(9)\t\t\t\t/* Accept ICV error packet */\n#define RCR_RXFTH0\t\t(BIT(13) | BIT(14) | BIT(15))\t/* Rx FIFO threshold */\n#define RCR_ADF\t\t\tBIT(18)\t\t\t\t/* Accept Data(frame type) frame */\n#define RCR_ACF\t\t\tBIT(19)\t\t\t\t/* Accept control frame */\n#define RCR_AMF\t\t\tBIT(20)\t\t\t\t/* Accept management frame */\n#define RCR_ADD3\t\tBIT(21)\n#define RCR_APWRMGT\t\tBIT(22)\t\t\t\t/* Accept power management packet */\n#define RCR_CBSSID\t\tBIT(23)\t\t\t\t/* Accept BSSID match packet */\n#define RCR_ENMARP\t\tBIT(28)\t\t\t\t/* enable mac auto reset phy */\n#define RCR_EnCS1\t\tBIT(29)\t\t\t\t/* enable carrier sense method 1 */\n#define RCR_EnCS2\t\tBIT(30)\t\t\t\t/* enable carrier sense method 2 */\n#define RCR_OnlyErlPkt\t\tBIT(31)\t\t\t\t/* Rx Early mode is performed for packet size greater than 1536 */\n\n/*--------------------------Define Parameters-------------------------------*/\n\n\n#endif /* __INC_HAL8192SPHYREG_H */\n"
  },
  {
    "path": "include/rtw_odm.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_ODM_H__\n#define __RTW_ODM_H__\n\n#include <drv_types.h>\n#include \"../hal/phydm/phydm_types.h\"\n/*\n* This file provides utilities/wrappers for rtw driver to use ODM\n*/\ntypedef enum _HAL_PHYDM_OPS {\n\tHAL_PHYDM_DIS_ALL_FUNC,\n\tHAL_PHYDM_FUNC_SET,\n\tHAL_PHYDM_FUNC_CLR,\n\tHAL_PHYDM_ABILITY_BK,\n\tHAL_PHYDM_ABILITY_RESTORE,\n\tHAL_PHYDM_ABILITY_SET,\n\tHAL_PHYDM_ABILITY_GET,\n} HAL_PHYDM_OPS;\n\n\n#define DYNAMIC_FUNC_DISABLE\t\t(0x0)\n\tu32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability);\n\n#define rtw_phydm_func_disable_all(adapter)\t\\\n\t\trtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0)\n\n#ifdef CONFIG_RTW_ACS\n#define rtw_phydm_func_for_offchannel(adapter) \\\n\t\tdo { \\\n\t\t\trtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \\\n\t\t\tif (rtw_odm_adaptivity_needed(adapter)) \\\n\t\t\t\trtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \\\n\t\t\tif (IS_ACS_ENABLE(adapter))\\\n\t\t\t\trtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ENV_MONITOR); \\\n\t\t} while (0)\n#else\n#define rtw_phydm_func_for_offchannel(adapter) \\\n\t\tdo { \\\n\t\t\trtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \\\n\t\t\tif (rtw_odm_adaptivity_needed(adapter)) \\\n\t\t\t\trtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \\\n\t\t} while (0)\n#endif\n\n#define rtw_phydm_func_clr(adapter, ability)\t\\\n\t\trtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_CLR, ability)\n\n#define rtw_phydm_ability_backup(adapter)\t\\\n\t\trtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_BK, 0)\n\n#define rtw_phydm_ability_restore(adapter)\t\\\n\t\trtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_RESTORE, 0)\n\n\nstatic inline u32 rtw_phydm_ability_get(_adapter *adapter)\n{\n\treturn rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_GET, 0);\n}\n\n\nvoid rtw_odm_init_ic_type(_adapter *adapter);\n\nvoid rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter);\n\nbool rtw_odm_adaptivity_needed(_adapter *adapter);\nvoid rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter);\nvoid rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff);\nvoid rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter);\nvoid rtw_odm_acquirespinlock(_adapter *adapter,\tenum rt_spinlock_type type);\nvoid rtw_odm_releasespinlock(_adapter *adapter,\tenum rt_spinlock_type type);\n\nu8 rtw_odm_get_dfs_domain(struct dvobj_priv *dvobj);\nu8 rtw_odm_dfs_domain_unknown(struct dvobj_priv *dvobj);\n#ifdef CONFIG_DFS_MASTER\nvoid rtw_odm_radar_detect_reset(_adapter *adapter);\nvoid rtw_odm_radar_detect_disable(_adapter *adapter);\nvoid rtw_odm_radar_detect_enable(_adapter *adapter);\nBOOLEAN rtw_odm_radar_detect(_adapter *adapter);\nu8 rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv *dvobj);\n#endif /* CONFIG_DFS_MASTER */\n\nvoid rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys);\n\n#if defined(CONFIG_RTL8822C) && defined(CONFIG_LPS_PG)\nvoid odm_lps_pg_debug_8822c(void *dm_void);\n#endif\n\n#endif /* __RTW_ODM_H__ */\n"
  },
  {
    "path": "include/rtw_p2p.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_P2P_H_\n#define __RTW_P2P_H_\n\n\nu32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);\nu32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);\nu32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 *pssid, u8 ussidlen, u8 *pdev_raddr);\nu32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code);\nu32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);\n#ifdef CONFIG_WFD\nint rtw_init_wifi_display_info(_adapter *padapter);\nvoid rtw_wfd_enable(_adapter *adapter, bool on);\nvoid rtw_wfd_set_ctrl_port(_adapter *adapter, u16 port);\nvoid rtw_tdls_wfd_enable(_adapter *adapter, bool on);\n\nu32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);\nu32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled);\nu32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);\nu32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);\nu32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);\nu32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);\nu32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);\nu32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);\nu32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);\nu32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);\nu32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);\nu32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);\n\nu32 rtw_append_beacon_wfd_ie(_adapter *adapter, u8 *pbuf);\nu32 rtw_append_probe_req_wfd_ie(_adapter *adapter, u8 *pbuf);\nu32 rtw_append_probe_resp_wfd_ie(_adapter *adapter, u8 *pbuf);\nu32 rtw_append_assoc_req_wfd_ie(_adapter *adapter, u8 *pbuf);\nu32 rtw_append_assoc_resp_wfd_ie(_adapter *adapter, u8 *pbuf);\n#endif /*CONFIG_WFD */\n\nvoid rtw_xframe_chk_wfd_ie(struct xmit_frame *xframe);\n\nu32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);\nu32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta);\nu32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);\nu32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);\nu8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo,  u8 *pframe, uint len);\nu8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo,  u8 *pframe);\nu8 process_p2p_group_negotation_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);\nu8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);\nu8 process_p2p_group_negotation_confirm(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);\nu8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);\nint process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength);\n\ns32 p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf);\n\n#ifdef CONFIG_P2P_PS\nvoid\tprocess_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength);\nvoid\tp2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state);\nu8\tp2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue);\n#endif /* CONFIG_P2P_PS */\n\n#ifdef CONFIG_IOCTL_CFG80211\nu8 roch_stay_in_cur_chan(_adapter *padapter);\nvoid rtw_init_cfg80211_wifidirect_info(_adapter\t*padapter);\nint rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx);\n#endif /* CONFIG_IOCTL_CFG80211 */\n\nvoid reset_global_wifidirect_info(_adapter *padapter);\nvoid rtw_init_wifidirect_timers(_adapter *padapter);\nvoid rtw_init_wifidirect_addrs(_adapter *padapter, u8 *dev_addr, u8 *iface_addr);\nvoid init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role);\nint rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role);\n\nstatic inline void _rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)\n{\n\tif (wdinfo->p2p_state != state) {\n\t\t/* wdinfo->pre_p2p_state = wdinfo->p2p_state; */\n\t\twdinfo->p2p_state = state;\n\t}\n}\nstatic inline void _rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)\n{\n\tif (wdinfo->pre_p2p_state != state)\n\t\twdinfo->pre_p2p_state = state;\n}\n#if 0\nstatic inline void _rtw_p2p_restore_state(struct wifidirect_info *wdinfo)\n{\n\tif (wdinfo->pre_p2p_state != -1) {\n\t\twdinfo->p2p_state = wdinfo->pre_p2p_state;\n\t\twdinfo->pre_p2p_state = -1;\n\t}\n}\n#endif\nvoid _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role);\n\nstatic inline int _rtw_p2p_state(struct wifidirect_info *wdinfo)\n{\n\treturn wdinfo->p2p_state;\n}\nstatic inline int _rtw_p2p_pre_state(struct wifidirect_info *wdinfo)\n{\n\treturn wdinfo->pre_p2p_state;\n}\nstatic inline int _rtw_p2p_role(struct wifidirect_info *wdinfo)\n{\n\treturn wdinfo->role;\n}\nstatic inline bool _rtw_p2p_chk_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)\n{\n\treturn wdinfo->p2p_state == state;\n}\nstatic inline bool _rtw_p2p_chk_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role)\n{\n\treturn wdinfo->role == role;\n}\n\n#ifdef CONFIG_DBG_P2P\nvoid dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line);\nvoid dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line);\n/* void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line); */\nvoid dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line);\n#define rtw_p2p_set_state(wdinfo, state) dbg_rtw_p2p_set_state(wdinfo, state, __FUNCTION__, __LINE__)\n#define rtw_p2p_set_pre_state(wdinfo, state) dbg_rtw_p2p_set_pre_state(wdinfo, state, __FUNCTION__, __LINE__)\n#define rtw_p2p_set_role(wdinfo, role) dbg_rtw_p2p_set_role(wdinfo, role, __FUNCTION__, __LINE__)\n/* #define rtw_p2p_restore_state(wdinfo) dbg_rtw_p2p_restore_state(wdinfo, __FUNCTION__, __LINE__) */\n#else /* CONFIG_DBG_P2P */\n#define rtw_p2p_set_state(wdinfo, state) _rtw_p2p_set_state(wdinfo, state)\n#define rtw_p2p_set_pre_state(wdinfo, state) _rtw_p2p_set_pre_state(wdinfo, state)\n#define rtw_p2p_set_role(wdinfo, role) _rtw_p2p_set_role(wdinfo, role)\n/* #define rtw_p2p_restore_state(wdinfo) _rtw_p2p_restore_state(wdinfo) */\n#endif /* CONFIG_DBG_P2P */\n\n#define rtw_p2p_state(wdinfo) _rtw_p2p_state(wdinfo)\n#define rtw_p2p_pre_state(wdinfo) _rtw_p2p_pre_state(wdinfo)\n#define rtw_p2p_role(wdinfo) _rtw_p2p_role(wdinfo)\n#define rtw_p2p_chk_state(wdinfo, state) _rtw_p2p_chk_state(wdinfo, state)\n#define rtw_p2p_chk_role(wdinfo, role) _rtw_p2p_chk_role(wdinfo, role)\n\n#define rtw_p2p_findphase_ex_set(wdinfo, value) \\\n\t(wdinfo)->find_phase_state_exchange_cnt = (value)\n\n#ifdef CONFIG_P2P\n/* is this find phase exchange for social channel scan? */\n#define rtw_p2p_findphase_ex_is_social(wdinfo)   \\\n\t(wdinfo)->find_phase_state_exchange_cnt >= P2P_FINDPHASE_EX_SOCIAL_FIRST\n\n/* should we need find phase exchange anymore? */\n#define rtw_p2p_findphase_ex_is_needed(wdinfo) \\\n\t((wdinfo)->find_phase_state_exchange_cnt < P2P_FINDPHASE_EX_MAX && \\\n\t (wdinfo)->find_phase_state_exchange_cnt != P2P_FINDPHASE_EX_NONE && \\\n\t !(wdinfo)->rx_invitereq_info.scan_op_ch_only && \\\n\t !(wdinfo)->p2p_info.scan_op_ch_only)\n#else\n#define rtw_p2p_findphase_ex_is_social(wdinfo) 0\n#define rtw_p2p_findphase_ex_is_needed(wdinfo) 0\n#endif /* CONFIG_P2P */\n\n#endif\n"
  },
  {
    "path": "include/rtw_pwrctrl.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_PWRCTRL_H_\n#define __RTW_PWRCTRL_H_\n\n\n#define FW_PWR0\t0\n#define FW_PWR1\t1\n#define FW_PWR2\t2\n#define FW_PWR3\t3\n\n\n#define HW_PWR0\t7\n#define HW_PWR1\t6\n#define HW_PWR2\t2\n#define HW_PWR3\t0\n#define HW_PWR4\t8\n\n#define FW_PWRMSK\t0x7\n\n\n#define XMIT_ALIVE\tBIT(0)\n#define RECV_ALIVE\tBIT(1)\n#define CMD_ALIVE\tBIT(2)\n#define EVT_ALIVE\tBIT(3)\n#ifdef CONFIG_BT_COEXIST\n#define BTCOEX_ALIVE\tBIT(4)\n#endif /* CONFIG_BT_COEXIST */\n\n#ifdef CONFIG_WOWLAN\n\t#ifdef CONFIG_PLATFORM_ANDROID_INTEL_X86\n\t\t/* TCP/ICMP/UDP multicast with specific IP addr */\n\t\t#define DEFAULT_PATTERN_NUM 4\n\t#else\n\t\t/* TCP/ICMP */\n\t\t#define DEFAULT_PATTERN_NUM 3\n\t#endif\n\n#ifdef CONFIG_WOW_PATTERN_HW_CAM\t/* Frame Mask Cam number for pattern match */\n#define MAX_WKFM_CAM_NUM\t12\n#else\n#define MAX_WKFM_CAM_NUM\t16\n#endif\n\n#define MAX_WKFM_SIZE\t16 /* (16 bytes for WKFM bit mask, 16*8 = 128 bits) */\n#define MAX_WKFM_PATTERN_SIZE\t128\n#define WKFMCAM_ADDR_NUM 6\n#define WKFMCAM_SIZE 24 /* each entry need 6*4 bytes */\nenum pattern_type {\n\tPATTERN_BROADCAST = 0,\n\tPATTERN_MULTICAST,\n\tPATTERN_UNICAST,\n\tPATTERN_VALID,\n\tPATTERN_INVALID,\n};\n\ntypedef struct rtl_priv_pattern {\n\tint len;\n\tchar content[MAX_WKFM_PATTERN_SIZE];\n\tchar mask[MAX_WKFM_SIZE];\n} rtl_priv_pattern_t;\n\n#endif /* CONFIG_WOWLAN */\n\nenum Power_Mgnt {\n\tPS_MODE_ACTIVE\t= 0\t,\n\tPS_MODE_MIN\t\t\t,\n\tPS_MODE_MAX\t\t\t,\n\tPS_MODE_DTIM\t\t\t,\t/* PS_MODE_SELF_DEFINED */\n\tPS_MODE_VOIP\t\t\t,\n\tPS_MODE_UAPSD_WMM\t,\n\tPS_MODE_UAPSD\t\t\t,\n\tPS_MODE_IBSS\t\t\t,\n\tPS_MODE_WWLAN\t\t,\n\tPM_Radio_Off\t\t\t,\n\tPM_Card_Disable\t\t,\n\tPS_MODE_NUM,\n};\n\nenum lps_level {\n\tLPS_NORMAL = 0,\n\tLPS_LCLK,\n\tLPS_PG,\n\tLPS_LEVEL_MAX,\n};\n\n#ifdef CONFIG_PNO_SUPPORT\n#define MAX_PNO_LIST_COUNT 16\n#define MAX_SCAN_LIST_COUNT 14\t/* 2.4G only */\n#define MAX_HIDDEN_AP 8\t\t/* 8 hidden AP */\n#endif\n\n/*\n\tBIT[2:0] = HW state\n\tBIT[3] = Protocol PS state,   0: register active state , 1: register sleep state\n\tBIT[4] = sub-state\n*/\n\n#define PS_DPS\t\t\t\tBIT(0)\n#define PS_LCLK\t\t\t\t(PS_DPS)\n#define PS_RF_OFF\t\t\tBIT(1)\n#define PS_ALL_ON\t\t\tBIT(2)\n#define PS_ST_ACTIVE\t\tBIT(3)\n\n#define PS_ISR_ENABLE\t\tBIT(4)\n#define PS_IMR_ENABLE\t\tBIT(5)\n#define PS_ACK\t\t\t\tBIT(6)\n#define PS_TOGGLE\t\t\tBIT(7)\n\n#define PS_STATE_MASK\t\t(0x0F)\n#define PS_STATE_HW_MASK\t(0x07)\n#define PS_SEQ_MASK\t\t\t(0xc0)\n\n#define PS_STATE(x)\t\t(PS_STATE_MASK & (x))\n#define PS_STATE_HW(x)\t(PS_STATE_HW_MASK & (x))\n#define PS_SEQ(x)\t\t(PS_SEQ_MASK & (x))\n\n#define PS_STATE_S0\t\t(PS_DPS)\n#define PS_STATE_S1\t\t(PS_LCLK)\n#define PS_STATE_S2\t\t(PS_RF_OFF)\n#define PS_STATE_S3\t\t(PS_ALL_ON)\n#define PS_STATE_S4\t\t((PS_ST_ACTIVE) | (PS_ALL_ON))\n\n\n#define PS_IS_RF_ON(x)\t((x) & (PS_ALL_ON))\n#define PS_IS_ACTIVE(x)\t((x) & (PS_ST_ACTIVE))\n#define CLR_PS_STATE(x)\t((x) = ((x) & (0xF0)))\n\n\nstruct reportpwrstate_parm {\n\tunsigned char mode;\n\tunsigned char state; /* the CPWM value */\n\tunsigned short rsvd;\n};\n\n\ntypedef _sema _pwrlock;\n\n\n__inline static void _init_pwrlock(_pwrlock *plock)\n{\n\t_rtw_init_sema(plock, 1);\n}\n\n__inline static void _free_pwrlock(_pwrlock *plock)\n{\n\t_rtw_free_sema(plock);\n}\n\n\n__inline static void _enter_pwrlock(_pwrlock *plock)\n{\n\t_rtw_down_sema(plock);\n}\n\n\n__inline static void _exit_pwrlock(_pwrlock *plock)\n{\n\t_rtw_up_sema(plock);\n}\n\n#define LPS_DELAY_MS\t1000 /* 1 sec */\n\n#define EXE_PWR_NONE\t0x01\n#define EXE_PWR_IPS\t\t0x02\n#define EXE_PWR_LPS\t\t0x04\n\n/* RF state. */\ntypedef enum _rt_rf_power_state {\n\trf_on,\t\t/* RF is on after RFSleep or RFOff */\n\trf_sleep,\t/* 802.11 Power Save mode */\n\trf_off,\t\t/* HW/SW Radio OFF or Inactive Power Save */\n\t/* =====Add the new RF state above this line===== */\n\trf_max\n} rt_rf_power_state;\n\n/* RF Off Level for IPS or HW/SW radio off */\n#define\tRT_RF_OFF_LEVL_ASPM\t\t\tBIT(0)\t/* PCI ASPM */\n#define\tRT_RF_OFF_LEVL_CLK_REQ\t\tBIT(1)\t/* PCI clock request */\n#define\tRT_RF_OFF_LEVL_PCI_D3\t\t\tBIT(2)\t/* PCI D3 mode */\n#define\tRT_RF_OFF_LEVL_HALT_NIC\t\tBIT(3)\t/* NIC halt, re-initialize hw parameters */\n#define\tRT_RF_OFF_LEVL_FREE_FW\t\tBIT(4)\t/* FW free, re-download the FW */\n#define\tRT_RF_OFF_LEVL_FW_32K\t\tBIT(5)\t/* FW in 32k */\n#define\tRT_RF_PS_LEVEL_ALWAYS_ASPM\tBIT(6)\t/* Always enable ASPM and Clock Req in initialization. */\n#define\tRT_RF_LPS_DISALBE_2R\t\t\tBIT(30)\t/* When LPS is on, disable 2R if no packet is received or transmittd. */\n#define\tRT_RF_LPS_LEVEL_ASPM\t\t\tBIT(31)\t/* LPS with ASPM */\n\n#define\tRT_IN_PS_LEVEL(ppsc, _PS_FLAG)\t\t((ppsc->cur_ps_level & _PS_FLAG) ? _TRUE : _FALSE)\n#define\tRT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG)\t(ppsc->cur_ps_level &= (~(_PS_FLAG)))\n#define\tRT_SET_PS_LEVEL(ppsc, _PS_FLAG)\t\t(ppsc->cur_ps_level |= _PS_FLAG)\n\n/* ASPM OSC Control bit, added by Roger, 2013.03.29. */\n#define\tRT_PCI_ASPM_OSC_IGNORE\t\t0\t /* PCI ASPM ignore OSC control in default */\n#define\tRT_PCI_ASPM_OSC_ENABLE\t\tBIT0 /* PCI ASPM controlled by OS according to ACPI Spec 5.0 */\n#define\tRT_PCI_ASPM_OSC_DISABLE\t\tBIT1 /* PCI ASPM controlled by driver or BIOS, i.e., force enable ASPM */\n\n\nenum _PS_BBRegBackup_ {\n\tPSBBREG_RF0 = 0,\n\tPSBBREG_RF1,\n\tPSBBREG_RF2,\n\tPSBBREG_AFE0,\n\tPSBBREG_TOTALCNT\n};\n\nenum { /* for ips_mode */\n\tIPS_NONE = 0,\n\tIPS_NORMAL,\n\tIPS_LEVEL_2,\n\tIPS_NUM\n};\n\n/* Design for pwrctrl_priv.ips_deny, 32 bits for 32 reasons at most */\ntypedef enum _PS_DENY_REASON {\n\tPS_DENY_DRV_INITIAL = 0,\n\tPS_DENY_SCAN,\n\tPS_DENY_JOIN,\n\tPS_DENY_DISCONNECT,\n\tPS_DENY_SUSPEND,\n\tPS_DENY_IOCTL,\n\tPS_DENY_MGNT_TX,\n\tPS_DENY_MONITOR_MODE,\n\tPS_DENY_BEAMFORMING,\t\t/* Beamforming */\n\tPS_DENY_DRV_REMOVE = 30,\n\tPS_DENY_OTHERS = 31\n} PS_DENY_REASON;\n\n#ifdef CONFIG_PNO_SUPPORT\ntypedef struct pno_nlo_info {\n\tu32 fast_scan_period;\t\t\t\t/* Fast scan period */\n\tu8\tssid_num;\t\t\t\t/* number of entry */\n\tu8\thidden_ssid_num;\n\tu32\tslow_scan_period;\t\t\t/* slow scan period */\n\tu32\tfast_scan_iterations;\t\t\t/* Fast scan iterations */\n\tu8\tssid_length[MAX_PNO_LIST_COUNT];\t/* SSID Length Array */\n\tu8\tssid_cipher_info[MAX_PNO_LIST_COUNT];\t/* Cipher information for security */\n\tu8\tssid_channel_info[MAX_PNO_LIST_COUNT];\t/* channel information */\n\tu8\tloc_probe_req[MAX_HIDDEN_AP];\t\t/* loc_probeReq */\n} pno_nlo_info_t;\n\ntypedef struct pno_ssid {\n\tu32\t\tSSID_len;\n\tu8\t\tSSID[32];\n} pno_ssid_t;\n\ntypedef struct pno_ssid_list {\n\tpno_ssid_t\tnode[MAX_PNO_LIST_COUNT];\n} pno_ssid_list_t;\n\ntypedef struct pno_scan_channel_info {\n\tu8\tchannel;\n\tu8\ttx_power;\n\tu8\ttimeout;\n\tu8\tactive;\t\t\t\t/* set 1 means active scan, or pasivite scan. */\n} pno_scan_channel_info_t;\n\ntypedef struct pno_scan_info {\n\tu8\tenableRFE;\t\t\t/* Enable RFE */\n\tu8\tperiod_scan_time;\t\t/* exclusive with fast_scan_period and slow_scan_period */\n\tu8\tperiodScan;\t\t\t/* exclusive with fast_scan_period and slow_scan_period */\n\tu8\torig_80_offset;\t\t\t/* original channel 80 offset */\n\tu8\torig_40_offset;\t\t\t/* original channel 40 offset */\n\tu8\torig_bw;\t\t\t/* original bandwidth */\n\tu8\torig_ch;\t\t\t/* original channel */\n\tu8\tchannel_num;\t\t\t/* number of channel */\n\tu64\trfe_type;\t\t\t/* rfe_type && 0x00000000000000ff */\n\tpno_scan_channel_info_t ssid_channel_info[MAX_SCAN_LIST_COUNT];\n} pno_scan_info_t;\n#endif /* CONFIG_PNO_SUPPORT */\n\n#ifdef CONFIG_LPS_POFF\n/* Driver context for LPS 32K Close IO Power */\ntypedef struct lps_poff_info {\n\tbool\tbEn;\n\tu8\t*pStaticFile;\n\tu8\t*pDynamicFile;\n\tu32\tConfFileOffset;\n\tu32\ttx_bndy_static;\n\tu32\ttx_bndy_dynamic;\n\tu16\tConfLenForPTK;\n\tu16\tConfLenForGTK;\n\tATOMIC_T bEnterPOFF;\n\tATOMIC_T bTxBoundInProgress;\n\tATOMIC_T bSetPOFFParm;\n} lps_poff_info_t;\n#endif /*CONFIG_LPS_POFF*/\n\nstruct aoac_report {\n\tu8 iv[8];\n\tu8 replay_counter_eapol_key[8];\n\tu8 group_key[32];\n\tu8 key_index;\n\tu8 security_type;\n\tu8 wow_pattern_idx;\n\tu8 version_info;\n\tu8 rekey_ok:1;\n\tu8 dummy:7;\n\tu8 reserved[3];\n\tu8 rxptk_iv[8];\n\tu8 rxgtk_iv[4][8];\n};\n\nstruct rsvd_page_cache_t;\n\nstruct pwrctrl_priv {\n\t_pwrlock\tlock;\n\t_pwrlock\tcheck_32k_lock;\n\tvolatile u8 rpwm; /* requested power state for fw */\n\tvolatile u8 cpwm; /* fw current power state. updated when 1. read from HCPWM 2. driver lowers power level */\n\tvolatile u8 tog; /* toggling */\n\tvolatile u8 cpwm_tog; /* toggling */\n\tu8 rpwm_retry;\n\n\tu8\tpwr_mode;\n\tu8\tsmart_ps;\n\tu8\tbcn_ant_mode;\n\tu8\tdtim;\n#ifdef CONFIG_LPS_CHK_BY_TP\n\tu8\tlps_chk_by_tp;\n\tu16\tlps_tx_tp_th;/*Mbps*/\n\tu16\tlps_rx_tp_th;/*Mbps*/\n\tu16\tlps_bi_tp_th;/*Mbps*//*TRX TP*/\n\tint\tlps_chk_cnt_th;\n\tint\tlps_chk_cnt;\n\tu32\tlps_tx_pkts;\n\tu32\tlps_rx_pkts;\n\n#endif\n\n#ifdef CONFIG_WMMPS_STA\n\tu8 wmm_smart_ps;\n#endif /* CONFIG_WMMPS_STA */\t\n\n\tu32\talives;\n\t_workitem cpwm_event;\n\t_workitem dma_event; /*for handle un-synchronized tx dma*/\n#ifdef CONFIG_LPS_RPWM_TIMER\n\tu8 brpwmtimeout;\n\t_workitem rpwmtimeoutwi;\n\t_timer pwr_rpwm_timer;\n#endif /* CONFIG_LPS_RPWM_TIMER */\n\tu8\tbpower_saving; /* for LPS/IPS */\n\n\tu8\tb_hw_radio_off;\n\tu8\treg_rfoff;\n\tu8\treg_pdnmode; /* powerdown mode */\n\tu32\trfoff_reason;\n\n\t/* RF OFF Level */\n\tu32\tcur_ps_level;\n\tu32\treg_rfps_level;\n\n\tuint\tips_enter_cnts;\n\tuint\tips_leave_cnts;\n\tuint\tlps_enter_cnts;\n\tuint\tlps_leave_cnts;\n\n\tu8\tips_mode;\n\tu8\tips_org_mode;\n\tu8\tips_mode_req; /* used to accept the mode setting request, will update to ipsmode later */\n\tuint bips_processing;\n\tsystime ips_deny_time; /* will deny IPS when system time is smaller than this */\n\tu8 pre_ips_type;/* 0: default flow, 1: carddisbale flow */\n\n\t/* ps_deny: if 0, power save is free to go; otherwise deny all kinds of power save. */\n\t/* Use PS_DENY_REASON to decide reason. */\n\t/* Don't access this variable directly without control function, */\n\t/* and this variable should be protected by lock. */\n\tu32 ps_deny;\n\n\tu8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */\n\n\tu8 fw_psmode_iface_id;\n\tu8\tbLeisurePs;\n\tu8\tLpsIdleCount;\n\tu8\tpower_mgnt;\n\tu8\torg_power_mgnt;\n\tu8\tbFwCurrentInPSMode;\n\tsystime\tlps_deny_time; /* will deny LPS when system time is smaller than this */\n\ts32\t\tpnp_current_pwr_state;\n\tu8\t\tpnp_bstop_trx;\n\n\t#ifdef CONFIG_AUTOSUSPEND\n\tint\t\tps_flag; /* used by autosuspend */\n\tu8\t\tbInternalAutoSuspend;\n\t#endif\n\tu8\t\tbInSuspend;\n#ifdef CONFIG_BT_COEXIST\n\tu8\t\tbAutoResume;\n\tu8\t\tautopm_cnt;\n#endif\n\tu8\t\tbSupportRemoteWakeup;\n\tu8\t\twowlan_wake_reason;\n\tu8\t\twowlan_last_wake_reason;\n\tu8\t\twowlan_ap_mode;\n\tu8\t\twowlan_mode;\n\tu8\t\twowlan_p2p_mode;\n\tu8\t\twowlan_pno_enable;\n\tu8\t\twowlan_in_resume;\n\n#ifdef CONFIG_GPIO_WAKEUP\n\tu8\t\tis_high_active;\n#endif /* CONFIG_GPIO_WAKEUP */\n\tu8\t\thst2dev_high_active;\n#ifdef CONFIG_WOWLAN\n\tbool\t\tdefault_patterns_en;\n#ifdef CONFIG_IPV6\n\tu8\t\twowlan_ns_offload_en;\n#endif /*CONFIG_IPV6*/\n\tu8\t\twowlan_txpause_status;\n\tu8\t\twowlan_pattern_idx;\n\tu64\t\twowlan_fw_iv;\n\tstruct rtl_priv_pattern\tpatterns[MAX_WKFM_CAM_NUM];\n#ifdef CONFIG_PNO_SUPPORT\n\tu8\t\tpno_inited;\n\tpno_nlo_info_t\t*pnlo_info;\n\tpno_scan_info_t\t*pscan_info;\n\tpno_ssid_list_t\t*pno_ssid_list;\n#endif /* CONFIG_PNO_SUPPORT */\n#ifdef CONFIG_WOW_PATTERN_HW_CAM\n\t_mutex\twowlan_pattern_cam_mutex;\n#endif\n\tu8\t\twowlan_aoac_rpt_loc;\n\tstruct aoac_report wowlan_aoac_rpt;\n\tu8\t\twowlan_power_mgmt;\n\tu8\t\twowlan_lps_level;\n\t#ifdef CONFIG_LPS_1T1R\n\tu8\t\twowlan_lps_1t1r;\n\t#endif\n#endif /* CONFIG_WOWLAN */\n\t_timer\tpwr_state_check_timer;\n\tint\t\tpwr_state_check_interval;\n\tu8\t\tpwr_state_check_cnts;\n\n\n\trt_rf_power_state\trf_pwrstate;/* cur power state, only for IPS */\n\t/* rt_rf_power_state\tcurrent_rfpwrstate; */\n\trt_rf_power_state\tchange_rfpwrstate;\n\n\tu8\t\tbHWPowerdown; /* power down mode selection. 0:radio off, 1:power down */\n\tu8\t\tbHWPwrPindetect; /* come from registrypriv.hwpwrp_detect. enable power down function. 0:disable, 1:enable */\n\tu8\t\tbkeepfwalive;\n\tu8\t\tbrfoffbyhw;\n\tunsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];\n\n#ifdef CONFIG_RESUME_IN_WORKQUEUE\n\tstruct workqueue_struct *rtw_workqueue;\n\t_workitem resume_work;\n#endif\n\n#ifdef CONFIG_HAS_EARLYSUSPEND\n\tstruct early_suspend early_suspend;\n\tu8 do_late_resume;\n#endif /* CONFIG_HAS_EARLYSUSPEND */\n\n#ifdef CONFIG_ANDROID_POWER\n\tandroid_early_suspend_t early_suspend;\n\tu8 do_late_resume;\n#endif\n\n#ifdef CONFIG_LPS_POFF\n\tlps_poff_info_t\t*plps_poff_info;\n#endif\n\tu8 lps_level_bk;\n\tu8 lps_level; /*LPS_NORMAL,LPA_CG,LPS_PG*/\n#ifdef CONFIG_LPS_1T1R\n\tu8 lps_1t1r_bk;\n\tu8 lps_1t1r;\n#endif\n#ifdef CONFIG_LPS_PG\n\tstruct rsvd_page_cache_t lpspg_info;\n#ifdef CONFIG_RTL8822C\n\tstruct rsvd_page_cache_t lpspg_dpk_info;\n\tstruct rsvd_page_cache_t lpspg_iqk_info;\n#endif\n#endif\n\tu8 current_lps_hw_port_id;\n\n#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS\n\tsystime radio_on_start_time;\n\tsystime pwr_saving_start_time;\n\tu32 pwr_saving_time;\n\tu32 on_time;\n\tu32 tx_time;\n\tu32 rx_time;\n#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */\n\n};\n\n#define rtw_get_ips_mode_req(pwrctl) \\\n\t(pwrctl)->ips_mode_req\n\n#define rtw_ips_mode_req(pwrctl, ips_mode) \\\n\t(pwrctl)->ips_mode_req = (ips_mode)\n\n#define RTW_PWR_STATE_CHK_INTERVAL 2000\n\n#define _rtw_set_pwr_state_check_timer(pwrctl, ms) \\\n\tdo { \\\n\t\t/*RTW_INFO(\"%s _rtw_set_pwr_state_check_timer(%p, %d)\\n\", __FUNCTION__, (pwrctl), (ms));*/ \\\n\t\t_set_timer(&(pwrctl)->pwr_state_check_timer, (ms)); \\\n\t} while (0)\n\n#define rtw_set_pwr_state_check_timer(pwrctl) \\\n\t_rtw_set_pwr_state_check_timer((pwrctl), (pwrctl)->pwr_state_check_interval)\n\nextern void rtw_init_pwrctrl_priv(_adapter *adapter);\nextern void rtw_free_pwrctrl_priv(_adapter *adapter);\n\n#ifdef CONFIG_LPS_LCLK\ns32 rtw_register_task_alive(PADAPTER, u32 task);\nvoid rtw_unregister_task_alive(PADAPTER, u32 task);\nextern s32 rtw_register_tx_alive(PADAPTER padapter);\nextern void rtw_unregister_tx_alive(PADAPTER padapter);\nextern s32 rtw_register_rx_alive(PADAPTER padapter);\nextern void rtw_unregister_rx_alive(PADAPTER padapter);\nextern s32 rtw_register_cmd_alive(PADAPTER padapter);\nextern void rtw_unregister_cmd_alive(PADAPTER padapter);\nextern s32 rtw_register_evt_alive(PADAPTER padapter);\nextern void rtw_unregister_evt_alive(PADAPTER padapter);\nextern void cpwm_int_hdl(PADAPTER padapter, struct reportpwrstate_parm *preportpwrstate);\nextern void LPS_Leave_check(PADAPTER padapter);\n#endif\n\nextern void LeaveAllPowerSaveMode(PADAPTER Adapter);\nextern void LeaveAllPowerSaveModeDirect(PADAPTER Adapter);\n#ifdef CONFIG_IPS\nvoid _ips_enter(_adapter *padapter);\nvoid ips_enter(_adapter *padapter);\nint _ips_leave(_adapter *padapter);\nint ips_leave(_adapter *padapter);\n#endif\n\nvoid rtw_ps_processor(_adapter *padapter);\n\n#ifdef CONFIG_AUTOSUSPEND\nint autoresume_enter(_adapter *padapter);\n#endif\n#ifdef SUPPORT_HW_RFOFF_DETECTED\nrt_rf_power_state RfOnOffDetect(PADAPTER pAdapter);\n#endif\n\n\n#ifdef DBG_CHECK_FW_PS_STATE\nint rtw_fw_ps_state(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_LPS\nvoid LPS_Enter(PADAPTER padapter, const char *msg);\nvoid LPS_Leave(PADAPTER padapter, const char *msg);\n#ifdef CONFIG_CHECK_LEAVE_LPS\n#ifdef CONFIG_LPS_CHK_BY_TP\nvoid traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info *sta);\n#endif\nvoid traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets);\n#endif /*CONFIG_CHECK_LEAVE_LPS*/\nvoid rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg);\nvoid rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable);\nu8 rtw_set_rpwm(_adapter *padapter, u8 val8);\n#ifdef CONFIG_WOWLAN\nvoid rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en);\n#endif /* CONFIG_WOWLAN */\n#endif /* CONFIG_LPS */\n\n#ifdef CONFIG_RESUME_IN_WORKQUEUE\nvoid rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv);\n#endif /* CONFIG_RESUME_IN_WORKQUEUE */\n\n#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)\nbool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv);\nbool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv);\nvoid rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable);\nvoid rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv);\nvoid rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv);\n#else\n#define rtw_is_earlysuspend_registered(pwrpriv) _FALSE\n#define rtw_is_do_late_resume(pwrpriv) _FALSE\n#define rtw_set_do_late_resume(pwrpriv, enable) do {} while (0)\n#define rtw_register_early_suspend(pwrpriv) do {} while (0)\n#define rtw_unregister_early_suspend(pwrpriv) do {} while (0)\n#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */\n\nu8 rtw_interface_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);\nvoid rtw_set_ips_deny(_adapter *padapter, u32 ms);\nint _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller);\n#define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__)\n#define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) _rtw_pwr_wakeup(adapter, ips_deffer_ms, __FUNCTION__)\nint rtw_pm_set_ips(_adapter *padapter, u8 mode);\nint rtw_pm_set_lps(_adapter *padapter, u8 mode);\nint rtw_pm_set_lps_level(_adapter *padapter, u8 level);\n#ifdef CONFIG_LPS_1T1R\nint rtw_pm_set_lps_1t1r(_adapter *padapter, u8 en);\n#endif\nvoid rtw_set_lps_deny(_adapter *adapter, u32 ms);\n#ifdef CONFIG_WOWLAN\nint rtw_pm_set_wow_lps(_adapter *padapter, u8 mode);\nint rtw_pm_set_wow_lps_level(_adapter *padapter, u8 level);\n#ifdef CONFIG_LPS_1T1R\nint rtw_pm_set_wow_lps_1t1r(_adapter *padapter, u8 en);\n#endif\n#endif /* CONFIG_WOWLAN */\n\nvoid rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason);\nvoid rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason);\nu32 rtw_ps_deny_get(PADAPTER padapter);\n\n#if defined(CONFIG_WOWLAN)\nvoid rtw_get_current_ip_address(PADAPTER padapter, u8 *pcurrentip);\nvoid rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr);\nbool rtw_check_pattern_valid(u8 *input, u8 len);\nbool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern,\n\t\t\t\tint *pattern_len, char *bit_mask);\nvoid rtw_wow_pattern_sw_reset(_adapter *adapter);\nu8 rtw_set_default_pattern(_adapter *adapter);\nvoid rtw_wow_pattern_sw_dump(_adapter *adapter);\n#endif /* CONFIG_WOWLAN */\nvoid rtw_ssmps_enter(_adapter *adapter, struct sta_info *sta);\nvoid rtw_ssmps_leave(_adapter *adapter, struct sta_info *sta);\n#endif /* __RTL871X_PWRCTRL_H_ */\n"
  },
  {
    "path": "include/rtw_qos.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n\n#ifndef _RTW_QOS_H_\n#define _RTW_QOS_H_\n\n#define DRV_CFG_UAPSD_VO \tBIT0\n#define DRV_CFG_UAPSD_VI \tBIT1\n#define DRV_CFG_UAPSD_BK \tBIT2\n#define DRV_CFG_UAPSD_BE \tBIT3\n\n#define WMM_IE_UAPSD_VO \tBIT0\n#define WMM_IE_UAPSD_VI \tBIT1\n#define WMM_IE_UAPSD_BK \tBIT2\n#define WMM_IE_UAPSD_BE \tBIT3\n\n#define WMM_TID0 \tBIT0\n#define WMM_TID1 \tBIT1\n#define WMM_TID2 \tBIT2\n#define WMM_TID3 \tBIT3\n#define WMM_TID4 \tBIT4\n#define WMM_TID5 \tBIT5\n#define WMM_TID6 \tBIT6\n#define WMM_TID7 \tBIT7\n\n#define AP_SUPPORTED_UAPSD BIT7\n/* TC = Traffic Category,  TID0~7 represents TC */\n#define BIT_MASK_TID_TC 0xff\n/* TS = Traffic Stream,  TID8~15 represents TS */\n#define BIT_MASK_TID_TS 0xff00\n#define ALL_TID_TC_SUPPORTED_UAPSD 0xff\n\nstruct\tqos_priv\t{\n\n\tunsigned int\t  qos_option;\t/* bit mask option: u-apsd, s-apsd, ts, block ack...\t\t */\n\n#ifdef CONFIG_WMMPS_STA\n\t/* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */\n\tu8 uapsd_max_sp_len;\n\t/* declare uapsd_tid as a bitmap for the uapsd setting of TID 0~15 */\n\tu16 uapsd_tid;\n\t/* declare uapsd_tid_delivery_enabled as a bitmap for the delivery-enabled setting of TID 0~7 */\n\tu8 uapsd_tid_delivery_enabled;\n\t/* declare uapsd_tid_trigger_enabled as a bitmap for the trigger-enabled setting of TID 0~7 */\n\tu8 uapsd_tid_trigger_enabled;\n\t/* declare uapsd_ap_supported to record whether the connected ap  supports uapsd or not */\n\tu8 uapsd_ap_supported;\n#endif /* CONFIG_WMMPS_STA */\t\n\n};\n\n\n#endif /* _RTL871X_QOS_H_ */"
  },
  {
    "path": "include/rtw_recv.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTW_RECV_H_\n#define _RTW_RECV_H_\n\n#define RTW_RX_MSDU_ACT_NONE\t\t0\n#define RTW_RX_MSDU_ACT_INDICATE\tBIT0\n#define RTW_RX_MSDU_ACT_FORWARD\t\tBIT1\n\n#ifdef CONFIG_SINGLE_RECV_BUF\n\t#define NR_RECVBUFF (1)\n#else\n\t#if defined(CONFIG_GSPI_HCI)\n\t\t#define NR_RECVBUFF (32)\n\t#elif defined(CONFIG_SDIO_HCI)\n\t\t#define NR_RECVBUFF (8)\n\t#else\n\t\t#define NR_RECVBUFF (8)\n\t#endif\n#endif /* CONFIG_SINGLE_RECV_BUF */\n#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER\n\t#define NR_PREALLOC_RECV_SKB (rtw_rtkm_get_nr_recv_skb()>>1)\n#else /*!CONFIG_PREALLOC_RX_SKB_BUFFER */\n\t#define NR_PREALLOC_RECV_SKB 8\n#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */\n\n#ifdef CONFIG_RTW_NAPI\n\t#define RTL_NAPI_WEIGHT (32)\n#endif\n\n\n#if defined(CONFIG_RTL8821C) && defined(CONFIG_SDIO_HCI) && defined(CONFIG_RECV_THREAD_MODE)\n\t#ifdef NR_RECVBUFF\n\t#undef NR_RECVBUFF\n\t#define NR_RECVBUFF (32)\n\t#endif\n#endif\n\n#define NR_RECVFRAME 256\n\n#define RXFRAME_ALIGN\t8\n#define RXFRAME_ALIGN_SZ\t(1<<RXFRAME_ALIGN)\n\n#define DRVINFO_SZ\t4 /* unit is 8bytes */\n\n#define MAX_RXFRAME_CNT\t512\n#define MAX_RX_NUMBLKS\t\t(32)\n#define RECVFRAME_HDR_ALIGN 128\n#define MAX_CONTINUAL_NORXPACKET_COUNT 4    /*  In MAX_CONTINUAL_NORXPACKET_COUNT*2 sec  , no rx traffict would issue DELBA*/\n\n#define PHY_RSSI_SLID_WIN_MAX\t\t\t\t100\n#define PHY_LINKQUALITY_SLID_WIN_MAX\t\t20\n\n\n#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)\n\n#define RX_MPDU_QUEUE\t\t\t\t0\n#define RX_CMD_QUEUE\t\t\t\t1\n#define RX_MAX_QUEUE\t\t\t\t2\n\n#define MAX_SUBFRAME_COUNT\t64\n/* Bridge-Tunnel header (for EtherTypes ETH_P_AARP and ETH_P_IPX) */\nextern u8 rtw_bridge_tunnel_header[];\nextern u8 rtw_rfc1042_header[];\n\nenum addba_rsp_ack_state {\n\tRTW_RECV_ACK_OR_TIMEOUT,\n};\n\n/* for Rx reordering buffer control */\nstruct recv_reorder_ctrl {\n\t_adapter\t*padapter;\n\tu8 tid;\n\tu8 enable;\n\tu16 indicate_seq;/* =wstart_b, init_value=0xffff */\n\tu16 wend_b;\n\tu8 wsize_b;\n\tu8 ampdu_size;\n\t_queue pending_recvframe_queue;\n\t_timer reordering_ctrl_timer;\n\tu8 bReorderWaiting;\n\tunsigned long rec_abba_rsp_ack;\n};\n\nstruct\tstainfo_rxcache\t{\n\tu16\ttid_rxseq[16];\n\tu8 iv[16][8];\n\tu8 last_tid;\n#if 0\n\tunsigned short\ttid0_rxseq;\n\tunsigned short\ttid1_rxseq;\n\tunsigned short\ttid2_rxseq;\n\tunsigned short\ttid3_rxseq;\n\tunsigned short\ttid4_rxseq;\n\tunsigned short\ttid5_rxseq;\n\tunsigned short\ttid6_rxseq;\n\tunsigned short\ttid7_rxseq;\n\tunsigned short\ttid8_rxseq;\n\tunsigned short\ttid9_rxseq;\n\tunsigned short\ttid10_rxseq;\n\tunsigned short\ttid11_rxseq;\n\tunsigned short\ttid12_rxseq;\n\tunsigned short\ttid13_rxseq;\n\tunsigned short\ttid14_rxseq;\n\tunsigned short\ttid15_rxseq;\n#endif\n};\n\n\nstruct smooth_rssi_data {\n\tu32\telements[100];\t/* array to store values */\n\tu32\tindex;\t\t\t/* index to current array to store */\n\tu32\ttotal_num;\t\t/* num of valid elements */\n\tu32\ttotal_val;\t\t/* sum of valid elements */\n};\n\nstruct signal_stat {\n\tu8\tupdate_req;\t\t/* used to indicate */\n\tu8\tavg_val;\t\t/* avg of valid elements */\n\tu32\ttotal_num;\t\t/* num of valid elements */\n\tu32\ttotal_val;\t\t/* sum of valid elements\t */\n};\n\nstruct rx_raw_rssi {\n\tu8 data_rate;\n\tu8 pwdball;\n\ts8 pwr_all;\n\n\tu8 mimo_signal_strength[4];/* in 0~100 index */\n\tu8 mimo_signal_quality[4];\n\n\ts8 ofdm_pwr[4];\n\tu8 ofdm_snr[4];\n};\n\n\n#include \"cmn_info/rtw_sta_info.h\"\n\nstruct rx_pkt_attrib\t{\n\tu16\tpkt_len;\n\tu8\tphyst;\n\tu8\tdrvinfo_sz;\n\tu8\tshift_sz;\n\tu8\thdrlen; /* the WLAN Header Len */\n\tu8\tto_fr_ds;\n\tu8\tamsdu;\n\tu8\tqos;\n\tu8\tpriority;\n\tu8\tpw_save;\n\tu8\tmdata;\n\tu16\tseq_num;\n\tu8\tfrag_num;\n\tu8\tmfrag;\n\tu8\torder;\n\tu8\tprivacy; /* in frame_ctrl field */\n\tu8\tbdecrypted;\n\tu8\tencrypt; /* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */\n\tu8\tiv_len;\n\tu8\ticv_len;\n\tu8\tcrc_err;\n\tu8\ticv_err;\n\n\tu16\teth_type;\n\n\tu8\tdst[ETH_ALEN];\n\tu8\tsrc[ETH_ALEN];\n\tu8\tta[ETH_ALEN];\n\tu8\tra[ETH_ALEN];\n\tu8\tbssid[ETH_ALEN];\n#ifdef CONFIG_RTW_MESH\n\tu8\tmsa[ETH_ALEN]; /* mesh sa */\n\tu8\tmda[ETH_ALEN]; /* mesh da */\n\tu8 mesh_ctrl_present;\n\tu8\tmesh_ctrl_len; /* length of mesh control field */\n#endif\n\n\tu8\tack_policy;\n\n\tu8\tkey_index;\n\n\tu8\tdata_rate;\n\tu8 ch; /* RX channel */\n\tu8\tbw;\n\tu8\tstbc;\n\tu8\tldpc;\n\tu8\tsgi;\n\tu8\tpkt_rpt_type;\n\tu32 tsfl;\n\tu32\tMacIDValidEntry[2];\t/* 64 bits present 64 entry. */\n\tu8\tppdu_cnt;\n\tu32 \tfree_cnt;\t\t/* free run counter */\n\tstruct phydm_phyinfo_struct phy_info;\n\n#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX\n\t/* checksum offload realted varaiables */\n\tu8 csum_valid;\t\t/* Checksum valid, 0: not check, 1: checked */\n\tu8 csum_err;\t\t/* Checksum Error occurs */\n#endif /* CONFIG_TCP_CSUM_OFFLOAD_RX */\n};\n\n#ifdef CONFIG_RTW_MESH\n#define RATTRIB_GET_MCTRL_LEN(rattrib) ((rattrib)->mesh_ctrl_len)\n#else\n#define RATTRIB_GET_MCTRL_LEN(rattrib) 0\n#endif\n\n/* These definition is used for Rx packet reordering. */\n#define SN_LESS(a, b)\t\t(((a-b) & 0x800) != 0)\n#define SN_EQUAL(a, b)\t(a == b)\n/* #define REORDER_WIN_SIZE\t128 */\n/* #define REORDER_ENTRY_NUM\t128 */\n#define REORDER_WAIT_TIME\t(50) /* (ms) */\n\n#if defined(CONFIG_PLATFORM_RTK390X) && defined(CONFIG_USB_HCI)\n\t#define RECVBUFF_ALIGN_SZ 32\n#else\n\t#define RECVBUFF_ALIGN_SZ 8\n#endif\n\n#ifdef CONFIG_TRX_BD_ARCH\n\t#define RX_WIFI_INFO_SIZE\t24\n#elif (defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)) && defined(CONFIG_PCI_HCI)\n\t#define RXBD_SIZE\tsizeof(struct recv_stat)\n#endif\n\n#define RXDESC_SIZE\t24\n#define RXDESC_OFFSET RXDESC_SIZE\n\n#ifdef CONFIG_TRX_BD_ARCH\nstruct rx_buf_desc {\n\t/* RX has exactly one segment */\n#ifdef CONFIG_64BIT_DMA\n\tunsigned int dword[4];\n#else\n\tunsigned int dword[2];\n#endif\n};\n\nstruct recv_stat {\n\tunsigned int rxdw[8];\n};\n#else\nstruct recv_stat {\n\tunsigned int rxdw0;\n\n\tunsigned int rxdw1;\n\n#if !((defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)) && defined(CONFIG_PCI_HCI))  /* exclude 8192ee, 8814ae, 8822be, 8821ce */\n\tunsigned int rxdw2;\n\n\tunsigned int rxdw3;\n#endif\n\n#ifndef BUF_DESC_ARCH\n\tunsigned int rxdw4;\n\n\tunsigned int rxdw5;\n\n#ifdef CONFIG_PCI_HCI\n\tunsigned int rxdw6;\n\n\tunsigned int rxdw7;\n#endif\n#endif /* if BUF_DESC_ARCH is defined, rx_buf_desc occupy 4 double words */\n};\n#endif\n\n#define EOR BIT(30)\n\n#ifdef CONFIG_PCI_HCI\n#define PCI_MAX_RX_QUEUE\t\t1/* MSDU packet queue, Rx Command Queue */\n#define PCI_MAX_RX_COUNT\t\t128\n#ifdef CONFIG_TRX_BD_ARCH\n#define RX_BD_NUM\t\t\t\tPCI_MAX_RX_COUNT\t/* alias */\n#endif\n\nstruct rtw_rx_ring {\n#ifdef CONFIG_TRX_BD_ARCH\n\tstruct rx_buf_desc\t*buf_desc;\n#else\n\tstruct recv_stat\t*desc;\n#endif\n\tdma_addr_t\t\tdma;\n\tunsigned int\t\tidx;\n\tstruct sk_buff\t*rx_buf[PCI_MAX_RX_COUNT];\n};\n#endif\n\n\n\n/*\naccesser of recv_priv: rtw_recv_entry(dispatch / passive level); recv_thread(passive) ; returnpkt(dispatch)\n; halt(passive) ;\n\nusing enter_critical section to protect\n*/\n\n#ifndef DBG_RX_BH_TRACKING\n#define DBG_RX_BH_TRACKING 0\n#endif\n\nstruct recv_priv {\n\t_lock\tlock;\n\n#ifdef CONFIG_RECV_THREAD_MODE\n\t_sema\trecv_sema;\n\n#endif\n\n\t/* _queue\tblk_strms[MAX_RX_NUMBLKS];    */ /* keeping the block ack frame until return ack */\n\t_queue\tfree_recv_queue;\n\t_queue\trecv_pending_queue;\n\t_queue\tuc_swdec_pending_queue;\n\n\n\tu8 *pallocated_frame_buf;\n\tu8 *precv_frame_buf;\n\n\tuint free_recvframe_cnt;\n\n\t#if DBG_RX_BH_TRACKING\n\tu32 rx_bh_stage;\n\tu32 rx_bh_buf_dq_cnt;\n\tvoid *rx_bh_lbuf;\n\tvoid *rx_bh_cbuf;\n\tvoid *rx_bh_cbuf_data;\n\tu32 rx_bh_cbuf_dlen;\n\tu32 rx_bh_cbuf_pos;\n\tvoid *rx_bh_cframe;\n\t#endif\n\n\t_adapter\t*adapter;\n\n\tu32 is_any_non_be_pkts;\n\n\tu64\trx_bytes;\n\tu64\trx_pkts;\n\tu64\trx_drop;\n\n\tu64 dbg_rx_drop_count;\n\tu64 dbg_rx_ampdu_drop_count;\n\tu64 dbg_rx_ampdu_forced_indicate_count;\n\tu64 dbg_rx_ampdu_loss_count;\n\tu64 dbg_rx_dup_mgt_frame_drop_count;\n\tu64 dbg_rx_ampdu_window_shift_cnt;\n\tu64 dbg_rx_conflic_mac_addr_cnt;\n\n\tuint  rx_icv_err;\n\tuint  rx_largepacket_crcerr;\n\tuint  rx_smallpacket_crcerr;\n\tuint  rx_middlepacket_crcerr;\n\n#ifdef CONFIG_USB_HCI\n\t/* u8 *pallocated_urb_buf; */\n\t_sema allrxreturnevt;\n\tuint\tff_hwaddr;\n\tATOMIC_T\trx_pending_cnt;\n\n#ifdef CONFIG_USB_INTERRUPT_IN_PIPE\n#ifdef PLATFORM_LINUX\n\tPURB\tint_in_urb;\n#endif\n\n\tu8\t*int_in_buf;\n#endif /* CONFIG_USB_INTERRUPT_IN_PIPE */\n\n#endif\n#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)\n\t_tasklet irq_prepare_beacon_tasklet;\n\t_tasklet recv_tasklet;\n\n\tstruct sk_buff_head free_recv_skb_queue;\n\tstruct sk_buff_head rx_skb_queue;\n#ifdef CONFIG_RTW_NAPI\n\t\tstruct sk_buff_head rx_napi_skb_queue;\n#endif \n#ifdef CONFIG_RX_INDICATE_QUEUE\n\t_tasklet rx_indicate_tasklet;\n\tstruct ifqueue rx_indicate_queue;\n#endif /* CONFIG_RX_INDICATE_QUEUE */\n\n#endif /* defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD) */\n\n\tu8 *pallocated_recv_buf;\n\tu8 *precv_buf;    /* 4 alignment */\n\t_queue\tfree_recv_buf_queue;\n\tu32\tfree_recv_buf_queue_cnt;\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_USB_HCI)\n\t_queue\trecv_buf_pending_queue;\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\t/* Rx */\n\tstruct rtw_rx_ring\trx_ring[PCI_MAX_RX_QUEUE];\n\tint rxringcount;\t/* size should be PCI_MAX_RX_QUEUE */\n\tu32\trxbuffersize;\n#endif\n\n\t/* For display the phy informatiom */\n\tu8 is_signal_dbg;\t/* for debug */\n\tu8 signal_strength_dbg;\t/* for debug */\n\n\tu8 signal_strength;\n\tu8 signal_qual;\n\ts8 rssi;\t/* translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength); */\n\tstruct rx_raw_rssi raw_rssi_info;\n\t/* s8 rxpwdb;\t */\n\t/* int RxSNRdB[2]; */\n\t/* s8 RxRssi[2]; */\n\t/* int FalseAlmCnt_all; */\n\n\n#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS\n\t_timer signal_stat_timer;\n\tu32 signal_stat_sampling_interval;\n\t/* u32 signal_stat_converging_constant; */\n\tstruct signal_stat signal_qual_data;\n\tstruct signal_stat signal_strength_data;\n#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */\n\tstruct smooth_rssi_data signal_qual_data;\n\tstruct smooth_rssi_data signal_strength_data;\n#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */\n\tu16 sink_udpport, pre_rtp_rxseq, cur_rtp_rxseq;\n\n\tBOOLEAN store_law_data_flag;\n};\n\n#define RX_BH_STG_UNKNOWN\t\t0\n#define RX_BH_STG_HDL_ENTER\t\t1\n#define RX_BH_STG_HDL_EXIT\t\t2\n#define RX_BH_STG_NEW_BUF\t\t3\n#define RX_BH_STG_NEW_FRAME\t\t4\n#define RX_BH_STG_NORMAL_RX\t\t5\n#define RX_BH_STG_NORMAL_RX_END\t6\n#define RX_BH_STG_C2H\t\t\t7\n#define RX_BH_STG_C2H_END\t\t8\n\n#if DBG_RX_BH_TRACKING\nvoid rx_bh_tk_set_stage(struct recv_priv *recv, u32 s);\nvoid rx_bh_tk_set_buf(struct recv_priv *recv, void *buf, void *data, u32 dlen);\nvoid rx_bh_tk_set_buf_pos(struct recv_priv *recv, void *pos);\nvoid rx_bh_tk_set_frame(struct recv_priv *recv, void *frame);\nvoid dump_rx_bh_tk(void *sel, struct recv_priv *recv);\n#else\n#define rx_bh_tk_set_stage(recv, s) do {} while (0)\n#define rx_bh_tk_set_buf(recv, buf, data, dlen) do {} while (0)\n#define rx_bh_tk_set_buf_pos(recv, pos) do {} while (0)\n#define rx_bh_tk_set_frame(recv, frame) do {} while (0)\n#define dump_rx_bh_tk(sel, recv) do {} while (0)\n#endif\n\n#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS\n#define rtw_set_signal_stat_timer(recvpriv) _set_timer(&(recvpriv)->signal_stat_timer, (recvpriv)->signal_stat_sampling_interval)\n#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */\n\nstruct sta_recv_priv {\n\n\t_lock\tlock;\n\tsint\toption;\n\n\t/* _queue\tblk_strms[MAX_RX_NUMBLKS]; */\n\t_queue defrag_q;\t /* keeping the fragment frame until defrag */\n\n\tstruct\tstainfo_rxcache rxcache;\n\tu16\tbmc_tid_rxseq[16];\n\tu16\tnonqos_rxseq;\n\tu16\tnonqos_bmc_rxseq;\n\n\t/* uint\tsta_rx_bytes; */\n\t/* uint\tsta_rx_pkts; */\n\t/* uint\tsta_rx_fail; */\n\n};\n\n\nstruct recv_buf {\n\t_list list;\n\n\t_lock recvbuf_lock;\n\n\tu32\tref_cnt;\n\n\tPADAPTER adapter;\n\n\tu8\t*pbuf;\n\tu8\t*pallocated_buf;\n\n\tu32\tlen;\n\tu8\t*phead;\n\tu8\t*pdata;\n\tu8\t*ptail;\n\tu8\t*pend;\n\n#ifdef CONFIG_USB_HCI\n\tPURB\tpurb;\n\tdma_addr_t dma_transfer_addr;\t/* (in) dma addr for transfer_buffer */\n\tu32 alloc_sz;\n\n\tu8  irp_pending;\n\tint  transfer_len;\n#endif\n\n#if defined(PLATFORM_LINUX)\n\t_pkt *pskb;\n#elif defined(PLATFORM_FREEBSD) /* skb solution */\n\tstruct sk_buff *pskb;\n#endif\n};\n\n\n/*\n\thead  ----->\n\n\t\tdata  ----->\n\n\t\t\tpayload\n\n\t\ttail  ----->\n\n\n\tend   ----->\n\n\tlen = (unsigned int )(tail - data);\n\n*/\nstruct recv_frame_hdr {\n\t_list\tlist;\n\t_pkt *pkt;\n\n\t_adapter  *adapter;\n\n\tu8 fragcnt;\n\n\tint frame_tag;\n\n\tstruct rx_pkt_attrib attrib;\n\n\tuint  len;\n\tu8 *rx_head;\n\tu8 *rx_data;\n\tu8 *rx_tail;\n\tu8 *rx_end;\n\n\tvoid *precvbuf;\n\n\n\t/*  */\n\tstruct sta_info *psta;\n\n\t/* for A-MPDU Rx reordering buffer control */\n\tstruct recv_reorder_ctrl *preorder_ctrl;\n\n#ifdef CONFIG_WAPI_SUPPORT\n\tu8 UserPriority;\n\tu8 WapiTempPN[16];\n\tu8 WapiSrcAddr[6];\n\tu8 bWapiCheckPNInDecrypt;\n\tu8 bIsWaiPacket;\n#endif\n\n};\n\n\nunion recv_frame {\n\n\tunion {\n\t\t_list list;\n\t\tstruct recv_frame_hdr hdr;\n\t\tuint mem[RECVFRAME_HDR_ALIGN >> 2];\n\t} u;\n\n\t/* uint mem[MAX_RXSZ>>2]; */\n\n};\n\nbool rtw_rframe_del_wfd_ie(union recv_frame *rframe, u8 ies_offset);\n\ntypedef enum _RX_PACKET_TYPE {\n\tNORMAL_RX,/* Normal rx packet */\n\tTX_REPORT1,/* CCX */\n\tTX_REPORT2,/* TX RPT */\n\tHIS_REPORT,/* USB HISR RPT */\n\tC2H_PACKET\n} RX_PACKET_TYPE, *PRX_PACKET_TYPE;\n\nextern union recv_frame *_rtw_alloc_recvframe(_queue *pfree_recv_queue);   /* get a free recv_frame from pfree_recv_queue */\nextern union recv_frame *rtw_alloc_recvframe(_queue *pfree_recv_queue);   /* get a free recv_frame from pfree_recv_queue */\nextern void rtw_init_recvframe(union recv_frame *precvframe , struct recv_priv *precvpriv);\nextern int\t rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue);\n\n#define rtw_dequeue_recvframe(queue) rtw_alloc_recvframe(queue)\nextern int _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue);\nextern int rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue);\n\nextern void rtw_free_recvframe_queue(_queue *pframequeue,  _queue *pfree_recv_queue);\nu32 rtw_free_uc_swdec_pending_queue(_adapter *adapter);\n\nsint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue);\nsint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue);\nstruct recv_buf *rtw_dequeue_recvbuf(_queue *queue);\n\n#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)\nvoid rtw_reordering_ctrl_timeout_handler(void *pcontext);\n#endif\n\nvoid rx_query_phy_status(union recv_frame *rframe, u8 *phy_stat);\nint rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index);\nvoid rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index);\n\n#ifdef CONFIG_RECV_THREAD_MODE\nthread_return rtw_recv_thread(thread_context context);\n#endif\n\n__inline static u8 *get_rxmem(union recv_frame *precvframe)\n{\n\t/* always return rx_head... */\n\tif (precvframe == NULL)\n\t\treturn NULL;\n\n\treturn precvframe->u.hdr.rx_head;\n}\n\n__inline static u8 *get_rx_status(union recv_frame *precvframe)\n{\n\n\treturn get_rxmem(precvframe);\n\n}\n\n__inline static u8 *get_recvframe_data(union recv_frame *precvframe)\n{\n\n\t/* alwasy return rx_data */\n\tif (precvframe == NULL)\n\t\treturn NULL;\n\n\treturn precvframe->u.hdr.rx_data;\n\n}\n\n__inline static u8 *recvframe_push(union recv_frame *precvframe, sint sz)\n{\n\t/* append data before rx_data */\n\n\t/* add data to the start of recv_frame\n\t*\n\t*      This function extends the used data area of the recv_frame at the buffer\n\t*      start. rx_data must be still larger than rx_head, after pushing.\n\t*/\n\n\tif (precvframe == NULL)\n\t\treturn NULL;\n\n\n\tprecvframe->u.hdr.rx_data -= sz ;\n\tif (precvframe->u.hdr.rx_data < precvframe->u.hdr.rx_head) {\n\t\tprecvframe->u.hdr.rx_data += sz ;\n\t\treturn NULL;\n\t}\n\n\tprecvframe->u.hdr.len += sz;\n\n\treturn precvframe->u.hdr.rx_data;\n\n}\n\n\n__inline static u8 *recvframe_pull(union recv_frame *precvframe, sint sz)\n{\n\t/* rx_data += sz; move rx_data sz bytes  hereafter */\n\n\t/* used for extract sz bytes from rx_data, update rx_data and return the updated rx_data to the caller */\n\n\n\tif (precvframe == NULL)\n\t\treturn NULL;\n\n\n\tprecvframe->u.hdr.rx_data += sz;\n\n\tif (precvframe->u.hdr.rx_data > precvframe->u.hdr.rx_tail) {\n\t\tprecvframe->u.hdr.rx_data -= sz;\n\t\treturn NULL;\n\t}\n\n\tprecvframe->u.hdr.len -= sz;\n\n\treturn precvframe->u.hdr.rx_data;\n\n}\n\n__inline static u8 *recvframe_put(union recv_frame *precvframe, sint sz)\n{\n\t/* rx_tai += sz; move rx_tail sz bytes  hereafter */\n\n\t/* used for append sz bytes from ptr to rx_tail, update rx_tail and return the updated rx_tail to the caller */\n\t/* after putting, rx_tail must be still larger than rx_end. */\n\tunsigned char *prev_rx_tail;\n\n\t/* RTW_INFO(\"recvframe_put: len=%d\\n\", sz); */\n\n\tif (precvframe == NULL)\n\t\treturn NULL;\n\n\tprev_rx_tail = precvframe->u.hdr.rx_tail;\n\n\tprecvframe->u.hdr.rx_tail += sz;\n\n\tif (precvframe->u.hdr.rx_tail > precvframe->u.hdr.rx_end) {\n\t\tprecvframe->u.hdr.rx_tail -= sz;\n\t\treturn NULL;\n\t}\n\n\tprecvframe->u.hdr.len += sz;\n\n\treturn precvframe->u.hdr.rx_tail;\n\n}\n\n\n\n__inline static u8 *recvframe_pull_tail(union recv_frame *precvframe, sint sz)\n{\n\t/* rmv data from rx_tail (by yitsen) */\n\n\t/* used for extract sz bytes from rx_end, update rx_end and return the updated rx_end to the caller */\n\t/* after pulling, rx_end must be still larger than rx_data. */\n\n\tif (precvframe == NULL)\n\t\treturn NULL;\n\n\tprecvframe->u.hdr.rx_tail -= sz;\n\n\tif (precvframe->u.hdr.rx_tail < precvframe->u.hdr.rx_data) {\n\t\tprecvframe->u.hdr.rx_tail += sz;\n\t\treturn NULL;\n\t}\n\n\tprecvframe->u.hdr.len -= sz;\n\n\treturn precvframe->u.hdr.rx_tail;\n\n}\n\n__inline static union recv_frame *rxmem_to_recvframe(u8 *rxmem)\n{\n\t/* due to the design of 2048 bytes alignment of recv_frame, we can reference the union recv_frame */\n\t/* from any given member of recv_frame. */\n\t/* rxmem indicates the any member/address in recv_frame */\n\n\treturn (union recv_frame *)(((SIZE_PTR)rxmem >> RXFRAME_ALIGN) << RXFRAME_ALIGN);\n\n}\n\n__inline static union recv_frame *pkt_to_recvframe(_pkt *pkt)\n{\n\n\tu8 *buf_star;\n\tunion recv_frame *precv_frame;\n\tprecv_frame = rxmem_to_recvframe((unsigned char *)buf_star);\n\n\treturn precv_frame;\n}\n\n__inline static u8 *pkt_to_recvmem(_pkt *pkt)\n{\n\t/* return the rx_head */\n\n\tunion recv_frame *precv_frame = pkt_to_recvframe(pkt);\n\n\treturn\tprecv_frame->u.hdr.rx_head;\n\n}\n\n__inline static u8 *pkt_to_recvdata(_pkt *pkt)\n{\n\t/* return the rx_data */\n\n\tunion recv_frame *precv_frame = pkt_to_recvframe(pkt);\n\n\treturn\tprecv_frame->u.hdr.rx_data;\n\n}\n\n\n__inline static sint get_recvframe_len(union recv_frame *precvframe)\n{\n\treturn precvframe->u.hdr.len;\n}\n\n\n__inline static s32 translate_percentage_to_dbm(u32 SignalStrengthIndex)\n{\n\ts32\tSignalPower; /* in dBm. */\n\n\t/* Translate to dBm (x=y-100) */\n\tSignalPower = SignalStrengthIndex - 100;\n\treturn SignalPower;\n}\n\nstruct sta_info;\n\nextern void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv);\n\nextern void  mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame);\n\nu8 adapter_allow_bmc_data_rx(_adapter *adapter);\ns32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status);\nvoid count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta);\n\n#endif\n"
  },
  {
    "path": "include/rtw_rf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef\t__RTW_RF_H_\n#define __RTW_RF_H_\n\n#define NumRates\t(13)\n#define\tB_MODE_RATE_NUM\t(4)\n#define\tG_MODE_RATE_NUM\t(8)\n#define\tG_MODE_BASIC_RATE_NUM\t(3)\n/* slot time for 11g */\n#define SHORT_SLOT_TIME\t\t\t\t\t9\n#define NON_SHORT_SLOT_TIME\t\t\t\t20\n\n#define CENTER_CH_2G_40M_NUM\t9\n#define CENTER_CH_2G_NUM\t\t14\n#define CENTER_CH_5G_20M_NUM\t28\t/* 20M center channels */\n#define CENTER_CH_5G_40M_NUM\t14\t/* 40M center channels */\n#define CENTER_CH_5G_80M_NUM\t7\t/* 80M center channels */\n#define CENTER_CH_5G_160M_NUM\t3\t/* 160M center channels */\n#define CENTER_CH_5G_ALL_NUM\t(CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM + CENTER_CH_5G_80M_NUM)\n\n#define\tMAX_CHANNEL_NUM_2G\tCENTER_CH_2G_NUM\n#define\tMAX_CHANNEL_NUM_5G\tCENTER_CH_5G_20M_NUM\n#define\tMAX_CHANNEL_NUM\t\t(MAX_CHANNEL_NUM_2G + MAX_CHANNEL_NUM_5G)\n\nextern u8 center_ch_2g[CENTER_CH_2G_NUM];\nextern u8 center_ch_2g_40m[CENTER_CH_2G_40M_NUM];\n\nu8 center_chs_2g_num(u8 bw);\nu8 center_chs_2g(u8 bw, u8 id);\n\nextern u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM];\nextern u8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM];\nextern u8 center_ch_5g_20m_40m[CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM];\nextern u8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM];\nextern u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM];\n\nu8 center_chs_5g_num(u8 bw);\nu8 center_chs_5g(u8 bw, u8 id);\n\nu8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset);\n\nu8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num);\n\nu8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group);\n\ntypedef enum _CAPABILITY {\n\tcESS\t\t\t= 0x0001,\n\tcIBSS\t\t\t= 0x0002,\n\tcPollable\t\t= 0x0004,\n\tcPollReq\t\t\t= 0x0008,\n\tcPrivacy\t\t= 0x0010,\n\tcShortPreamble\t= 0x0020,\n\tcPBCC\t\t\t= 0x0040,\n\tcChannelAgility\t= 0x0080,\n\tcSpectrumMgnt\t= 0x0100,\n\tcQos\t\t\t= 0x0200,\t/* For HCCA, use with CF-Pollable and CF-PollReq */\n\tcShortSlotTime\t= 0x0400,\n\tcAPSD\t\t\t= 0x0800,\n\tcRM\t\t\t\t= 0x1000,\t/* RRM (Radio Request Measurement) */\n\tcDSSS_OFDM\t= 0x2000,\n\tcDelayedBA\t\t= 0x4000,\n\tcImmediateBA\t= 0x8000,\n} CAPABILITY, *PCAPABILITY;\n\nenum\t_REG_PREAMBLE_MODE {\n\tPREAMBLE_LONG\t= 1,\n\tPREAMBLE_AUTO\t= 2,\n\tPREAMBLE_SHORT\t= 3,\n};\n\n#define rf_path_char(path) (((path) >= RF_PATH_MAX) ? 'X' : 'A' + (path))\n\n/* Bandwidth Offset */\n#define HAL_PRIME_CHNL_OFFSET_DONT_CARE\t0\n#define HAL_PRIME_CHNL_OFFSET_LOWER\t1\n#define HAL_PRIME_CHNL_OFFSET_UPPER\t2\n\ntypedef enum _BAND_TYPE {\n\tBAND_ON_2_4G = 0,\n\tBAND_ON_5G = 1,\n\tBAND_ON_BOTH = 2,\n\tBAND_MAX = 3,\n} BAND_TYPE, *PBAND_TYPE;\n\nextern const char *const _band_str[];\n#define band_str(band) (((band) >= BAND_MAX) ? _band_str[BAND_MAX] : _band_str[(band)])\n\nextern const u8 _band_to_band_cap[];\n#define band_to_band_cap(band) (((band) >= BAND_MAX) ? _band_to_band_cap[BAND_MAX] : _band_to_band_cap[(band)])\n\n\nextern const char *const _ch_width_str[];\n#define ch_width_str(bw) (((bw) < CHANNEL_WIDTH_MAX) ? _ch_width_str[(bw)] : \"CHANNEL_WIDTH_MAX\")\n\nextern const u8 _ch_width_to_bw_cap[];\n#define ch_width_to_bw_cap(bw) (((bw) < CHANNEL_WIDTH_MAX) ? _ch_width_to_bw_cap[(bw)] : 0)\n\n/*\n * Represent Extention Channel Offset in HT Capabilities\n * This is available only in 40Mhz mode.\n *   */\ntypedef enum _EXTCHNL_OFFSET {\n\tEXTCHNL_OFFSET_NO_EXT = 0,\n\tEXTCHNL_OFFSET_UPPER = 1,\n\tEXTCHNL_OFFSET_NO_DEF = 2,\n\tEXTCHNL_OFFSET_LOWER = 3,\n} EXTCHNL_OFFSET, *PEXTCHNL_OFFSET;\n\ntypedef enum _VHT_DATA_SC {\n\tVHT_DATA_SC_DONOT_CARE = 0,\n\tVHT_DATA_SC_20_UPPER_OF_80MHZ = 1,\n\tVHT_DATA_SC_20_LOWER_OF_80MHZ = 2,\n\tVHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,\n\tVHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,\n\tVHT_DATA_SC_20_RECV1 = 5,\n\tVHT_DATA_SC_20_RECV2 = 6,\n\tVHT_DATA_SC_20_RECV3 = 7,\n\tVHT_DATA_SC_20_RECV4 = 8,\n\tVHT_DATA_SC_40_UPPER_OF_80MHZ = 9,\n\tVHT_DATA_SC_40_LOWER_OF_80MHZ = 10,\n} VHT_DATA_SC, *PVHT_DATA_SC_E;\n\ntypedef enum _PROTECTION_MODE {\n\tPROTECTION_MODE_AUTO = 0,\n\tPROTECTION_MODE_FORCE_ENABLE = 1,\n\tPROTECTION_MODE_FORCE_DISABLE = 2,\n} PROTECTION_MODE, *PPROTECTION_MODE;\n\n#define RF_TYPE_VALID(rf_type) (rf_type < RF_TYPE_MAX)\n\nextern const u8 _rf_type_to_rf_tx_cnt[];\n#define rf_type_to_rf_tx_cnt(rf_type) (RF_TYPE_VALID(rf_type) ? _rf_type_to_rf_tx_cnt[rf_type] : 0)\n\nextern const u8 _rf_type_to_rf_rx_cnt[];\n#define rf_type_to_rf_rx_cnt(rf_type) (RF_TYPE_VALID(rf_type) ? _rf_type_to_rf_rx_cnt[rf_type] : 0)\n\nint rtw_ch2freq(int chan);\nint rtw_freq2ch(int freq);\nbool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo);\n\nstruct rf_ctl_t;\n\ntypedef enum _REGULATION_TXPWR_LMT {\n\tTXPWR_LMT_NONE = 0, /* no limit */\n\tTXPWR_LMT_FCC = 1,\n\tTXPWR_LMT_MKK = 2,\n\tTXPWR_LMT_ETSI = 3,\n\tTXPWR_LMT_IC = 4,\n\tTXPWR_LMT_KCC = 5,\n\tTXPWR_LMT_ACMA = 6,\n\tTXPWR_LMT_CHILE = 7,\n\tTXPWR_LMT_MEXICO = 8,\n\tTXPWR_LMT_WW = 9, /* smallest of all available limit, keep last */\n} REGULATION_TXPWR_LMT;\n\nextern const char *const _regd_str[];\n#define regd_str(regd) (((regd) > TXPWR_LMT_WW) ? _regd_str[TXPWR_LMT_WW] : _regd_str[(regd)])\n\n#if CONFIG_TXPWR_LIMIT\nstruct regd_exc_ent {\n\t_list list;\n\tchar country[2];\n\tu8 domain;\n\tchar regd_name[0];\n};\n\nvoid dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl);\nvoid rtw_regd_exc_add_with_nlen(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name, u32 nlen);\nvoid rtw_regd_exc_add(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name);\nstruct regd_exc_ent *_rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain);\nstruct regd_exc_ent *rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain);\nvoid rtw_regd_exc_list_free(struct rf_ctl_t *rfctl);\n\nvoid dump_txpwr_lmt(void *sel, _adapter *adapter);\nvoid rtw_txpwr_lmt_add_with_nlen(struct rf_ctl_t *rfctl, const char *regd_name, u32 nlen\n\t, u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt);\nvoid rtw_txpwr_lmt_add(struct rf_ctl_t *rfctl, const char *regd_name\n\t, u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt);\nstruct txpwr_lmt_ent *_rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name);\nstruct txpwr_lmt_ent *rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name);\nvoid rtw_txpwr_lmt_list_free(struct rf_ctl_t *rfctl);\n#endif /* CONFIG_TXPWR_LIMIT */\n\n#define BB_GAIN_2G 0\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n#define BB_GAIN_5GLB1 1\n#define BB_GAIN_5GLB2 2\n#define BB_GAIN_5GMB1 3\n#define BB_GAIN_5GMB2 4\n#define BB_GAIN_5GHB 5\n#endif\n\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n#define BB_GAIN_NUM 6\n#else\n#define BB_GAIN_NUM 1\n#endif\n\nint rtw_ch_to_bb_gain_sel(int ch);\nvoid rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset);\nvoid rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch);\n\n/* only check channel ranges */\n#define rtw_is_2g_ch(ch) (ch >= 1 && ch <= 14)\n#define rtw_is_5g_ch(ch) ((ch) >= 36 && (ch) <= 177)\n#define rtw_is_same_band(a, b) \\\n\t((rtw_is_2g_ch(a) && rtw_is_2g_ch(b)) \\\n\t|| (rtw_is_5g_ch(a) && rtw_is_5g_ch(b)))\n\n#define rtw_is_5g_band1(ch) ((ch) >= 36 && (ch) <= 48)\n#define rtw_is_5g_band2(ch) ((ch) >= 52 && (ch) <= 64)\n#define rtw_is_5g_band3(ch) ((ch) >= 100 && (ch) <= 144)\n#define rtw_is_5g_band4(ch) ((ch) >= 149 && (ch) <= 177)\n#define rtw_is_same_5g_band(a, b) \\\n\t((rtw_is_5g_band1(a) && rtw_is_5g_band1(b)) \\\n\t|| (rtw_is_5g_band2(a) && rtw_is_5g_band2(b)) \\\n\t|| (rtw_is_5g_band3(a) && rtw_is_5g_band3(b)) \\\n\t|| (rtw_is_5g_band4(a) && rtw_is_5g_band4(b)))\n\nu8 rtw_is_dfs_range(u32 hi, u32 lo);\nu8 rtw_is_dfs_ch(u8 ch);\nu8 rtw_is_dfs_chbw(u8 ch, u8 bw, u8 offset);\nbool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region);\nbool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region);\n\n#endif /* _RTL8711_RF_H_ */\n"
  },
  {
    "path": "include/rtw_rm.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef __RTW_RM_H_\n#define __RTW_RM_H_\n\nu8 rm_post_event_hdl(_adapter *padapter, u8 *pbuf);\n\n#define RM_TIMER_NUM \t\t32\n#define RM_ALL_MEAS\t\tBIT(1)\n#define RM_ID_FOR_ALL(aid)\t((aid<<16)|RM_ALL_MEAS)\n\n#define RM_CAP_ARG(x) ((u8 *)(x))[4], ((u8 *)(x))[3], ((u8 *)(x))[2], ((u8 *)(x))[1], ((u8 *)(x))[0]\n#define RM_CAP_FMT \"%02x %02x%02x %02x%02x\"\n\n/* remember to modify rm_event_name() when adding new event */\nenum RM_EV_ID {\n\tRM_EV_state_in,\n\tRM_EV_busy_timer_expire,\n\tRM_EV_delay_timer_expire,\n\tRM_EV_meas_timer_expire,\n\tRM_EV_retry_timer_expire,\n\tRM_EV_repeat_delay_expire,\n\tRM_EV_request_timer_expire,\n\tRM_EV_wait_report,\n\tRM_EV_start_meas,\n\tRM_EV_survey_done,\n\tRM_EV_recv_rep,\n\tRM_EV_cancel,\n\tRM_EV_state_out,\n\tRM_EV_max\n};\n\nstruct rm_event {\n\tu32 rmid;\n\tenum RM_EV_ID evid;\n\t_list list;\n};\n\n#ifdef CONFIG_RTW_80211K\n\nstruct rm_clock {\n\tstruct rm_obj *prm;\n\tATOMIC_T counter;\n\tenum RM_EV_ID evid;\n};\n\nstruct rm_priv {\n\tu8 enable;\n\t_queue ev_queue;\n\t_queue rm_queue;\n\t_timer rm_timer;\n\n\tstruct rm_clock clock[RM_TIMER_NUM];\n\tu8 rm_en_cap_def[5];\n\tu8 rm_en_cap_assoc[5];\n\n\t/* rm debug */\n\tvoid *prm_sel;\n};\n\nint rtw_init_rm(_adapter *padapter);\nint rtw_free_rm_priv(_adapter *padapter);\n\nunsigned int rm_on_action(_adapter *padapter, union recv_frame *precv_frame);\nvoid RM_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);\nvoid rtw_ap_parse_sta_rm_en_cap(_adapter *padapter,\n\tstruct sta_info *psta, struct rtw_ieee802_11_elems *elems);\n\nint rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid);\nvoid rm_handler(_adapter *padapter, struct rm_event *pev);\n\nu8 rm_add_nb_req(_adapter *padapter, struct sta_info *psta);\n\n#endif /*CONFIG_RTW_80211K */\n#endif /* __RTW_RM_H_ */\n"
  },
  {
    "path": "include/rtw_rm_fsm.h",
    "content": "\n/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef __RTW_RM_FSM_H_\n#define __RTW_RM_FSM_H_\n\n#ifdef CONFIG_RTW_80211K\n\n#define RM_SUPPORT_IWPRIV_DBG\t1\n#define RM_MORE_DBG_MSG\t\t0\n\n#define DBG_BCN_REQ_DETAIL\t0\n#define DBG_BCN_REQ_WILDCARD\t0\n#define DBG_BCN_REQ_SSID\t0\n#define DBG_BCN_REQ_SSID_NAME\t\"RealKungFu\"\n\n#define RM_REQ_TIMEOUT\t\t10000\t/* 10 seconds */\n#define RM_MEAS_TIMEOUT\t\t10000\t/* 10 seconds */\n#define RM_REPT_SCAN_INTVL\t5000\t/*  5 seconds */\n#define RM_REPT_POLL_INTVL\t2000\t/*  2 seconds */\n#define RM_COND_INTVL\t\t2000\t/*  2 seconds */\n#define RM_SCAN_DENY_TIMES\t10\n#define RM_BUSY_TRAFFIC_TIMES\t10\n#define RM_WAIT_BUSY_TIMEOUT\t1000\t/*  1 seconds */\n\n#define MEAS_REQ_MOD_PARALLEL\tBIT(0)\n#define MEAS_REQ_MOD_ENABLE\tBIT(1)\n#define MEAS_REQ_MOD_REQUEST\tBIT(2)\n#define MEAS_REQ_MOD_REPORT\tBIT(3)\n#define MEAS_REQ_MOD_DUR_MAND\tBIT(4)\n\n#define MEAS_REP_MOD_LATE\tBIT(0)\n#define MEAS_REP_MOD_INCAP\tBIT(1)\n#define MEAS_REP_MOD_REFUSE\tBIT(2)\n\n#define RM_MASTER\t\tBIT(0)\t/* STA who issue meas_req */\n#define RM_SLAVE\t\t0\t/* STA who do measurement */\n\n#define CLOCK_UNIT\t\t10\t/* ms */\n#define RTW_MAX_NB_RPT_IE_NUM\t16\n\n#define RM_GET_AID(rmid)\t((rmid&0xffff0000)>>16)\n#define RM_IS_ID_FOR_ALL(rmid)\t(rmid&RM_ALL_MEAS)\n\n/*\n * define the following channels as the max channels in each channel plan.\n * 2G, total 14 chnls\n * {1,2,3,4,5,6,7,8,9,10,11,12,13,14}\n * 5G, total 25 chnls\n * {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,144,149,153,157,161,165}\n */\n#define\tMAX_OP_CHANNEL_SET_NUM\t11\ntypedef struct _RT_OPERATING_CLASS {\n\tint\tglobal_op_class;\n\tint\tLen;\n\tu16\tChannel[MAX_OP_CHANNEL_SET_NUM];\n} RT_OPERATING_CLASS, *PRT_OPERATING_CLASS;\n\n/* IEEE 802.11-2012 Table 8-59 Measurement Type definitions\n*  for measurement request\n*  modify rm_meas_type_req_name() when adding new type\n*/\nenum meas_type_of_req {\n\tbasic_req,\t/* spectrum measurement */\n\tcca_req,\n\trpi_histo_req,\n\tch_load_req,\n\tnoise_histo_req,\n\tbcn_req,\n\tframe_req,\n\tsta_statis_req,\n\tlci_req,\n\tmeas_type_req_max,\n};\n\n/* IEEE 802.11-2012 Table 8-81 Measurement Type definitions\n*  for measurement report\n*  modify rm_type_rep_name() when adding new type\n*/\nenum meas_type_of_rep {\n\tbasic_rep,\t/* spectrum measurement */\n\tcca_rep,\n\trpi_histo_rep,\n\tch_load_rep,\t/* radio measurement */\n\tnoise_histo_rep,\n\tbcn_rep,\n\tframe_rep,\n\tsta_statis_rep,\t/* Radio measurement and WNM */\n\tlci_rep,\n\tmeas_type_rep_max\n};\n\n/*\n* Beacon request\n*/\n/* IEEE 802.11-2012 Table 8-64 Measurement mode for Beacon Request element */\nenum bcn_req_meas_mode {\n\tbcn_req_passive,\n\tbcn_req_active,\n\tbcn_req_bcn_table\n};\n\n/* IEEE 802.11-2012 Table 8-65 optional subelement IDs for Beacon Request */\nenum bcn_req_opt_sub_id{\n\tbcn_req_ssid = 0,\t\t/* len 0-32 */\n\tbcn_req_rep_info = 1,\t\t/* len 2 */\n\tbcn_req_rep_detail = 2,\t\t/* len 1 */\n\tbcn_req_req = 10,\t\t/* len 0-237 */\n\tbcn_req_ac_ch_rep = 51\t\t/* len 1-237 */\n};\n\n/* IEEE 802.11-2012 Table 8-66 Reporting condition of Beacon Report */\nenum bcn_rep_cound_id{\n\tbcn_rep_cond_immediately,\t/* default */\n\tbcn_req_cond_rcpi_greater,\n\tbcn_req_cond_rcpi_less,\n\tbcn_req_cond_rsni_greater,\n\tbcn_req_cond_rsni_less,\n\tbcn_req_cond_max\n};\n\nstruct opt_rep_info {\n\tu8 cond;\n\tu8 threshold;\n};\n\n#define BCN_REQ_OPT_MAX_NUM\t\t16\nstruct bcn_req_opt {\n\t/* all req cmd id */\n\tu8 opt_id[BCN_REQ_OPT_MAX_NUM];\n\tu8 opt_id_num;\n\tu8 rep_detail;\n\tNDIS_802_11_SSID ssid;\n\n\t/* bcn report condition */\n\tstruct opt_rep_info rep_cond;\n\n\t/* 0:default(Report to be issued after each measurement) */\n\tu8 *req_start;\t/*id : 10 request;start  */\n\tu8 req_len;\t/*id : 10 request;length */\n};\n\n/*\n* channel load\n*/\n/* IEEE 802.11-2012 Table 8-60 optional subelement IDs for channel load request */\nenum ch_load_opt_sub_id{\n\tch_load_rsvd,\n\tch_load_rep_info\n};\n\n/* IEEE 802.11-2012 Table 8-61 Reporting condition for channel load Report */\nenum ch_load_cound_id{\n\tch_load_cond_immediately,\t/* default */\n\tch_load_cond_anpi_equal_greater,\n\tch_load_cond_anpi_equal_less,\n\tch_load_cond_max\n};\n\n/*\n* Noise histogram\n*/\n/* IEEE 802.11-2012 Table 8-62 optional subelement IDs for noise histogram */\nenum noise_histo_opt_sub_id{\n\tnoise_histo_rsvd,\n\tnoise_histo_rep_info\n};\n\n/* IEEE 802.11-2012 Table 8-63 Reporting condition for noise historgarm Report */\nenum noise_histo_cound_id{\n\tnoise_histo_cond_immediately,\t/* default */\n\tnoise_histo_cond_anpi_equal_greater,\n\tnoise_histo_cond_anpi_equal_less,\n\tnoise_histo_cond_max\n};\n\nstruct meas_req_opt {\n\t/* report condition */\n\tstruct opt_rep_info rep_cond;\n};\n\n/*\n* State machine\n*/\n\nenum RM_STATE {\n\tRM_ST_IDLE,\n\tRM_ST_DO_MEAS,\n\tRM_ST_WAIT_MEAS,\n\tRM_ST_SEND_REPORT,\n\tRM_ST_RECV_REPORT,\n\tRM_ST_END,\n\tRM_ST_MAX\n};\n\nstruct rm_meas_req {\n\tu8 category;\n\tu8 action_code;\t\t/* T8-206  */\n\tu8 diag_token;\n\tu16 rpt;\n\n\tu8 e_id;\n\tu8 len;\n\tu8 m_token;\n\tu8 m_mode;\t\t/* req:F8-105, rep:F8-141 */\n\tu8 m_type;\t\t/* T8-59 */\n\tu8 op_class;\n\tu8 ch_num;\n\tu16 rand_intvl;\t\t/* units of TU */\n\tu16 meas_dur;\t\t/* units of TU */\n\n\tu8 bssid[6];\t\t/* for bcn_req */\n\n\tu8 *pssid;\n\tu8 *opt_s_elem_start;\n\tint opt_s_elem_len;\n\n\tunion {\n\t\tstruct bcn_req_opt bcn;\n\t\tstruct meas_req_opt clm;\n\t\tstruct meas_req_opt nhm;\n\t}opt;\n\n\tstruct rtw_ieee80211_channel ch_set[MAX_OP_CHANNEL_SET_NUM];\n\tu8 ch_set_ch_amount;\n};\n\nstruct rm_meas_rep {\n\tu8 category;\n\tu8 action_code;\t\t/* T8-206  */\n\tu8 diag_token;\n\n\tu8 e_id;\t\t/* T8-54, 38 request; 39 report */\n\tu8 len;\n\tu8 m_token;\n\tu8 m_mode;\t\t/* req:F8-105, rep:F8-141 */\n\tu8 m_type;\t\t/* T8-59 */\n\tu8 op_class;\n\tu8 ch_num;\n\n\tu8 ch_load;\n\tu8 anpi;\n\tu8 ipi[11];\n\n\tu16 rpt;\n\tu8 bssid[6];\t\t/* for bcn_req */\n};\n\n#define MAX_BUF_NUM\t128\nstruct data_buf {\n\tu8 *pbuf;\n\tu16 len;\n};\n\nstruct rm_obj {\n\n\t/* aid << 16 \n\t\t|diag_token << 8\n\t\t|B(1) 1/0:All_AID/UNIC\n\t\t|B(0) 1/0:RM_MASTER/RM_SLAVE */\n\tu32 rmid;\n\n\tenum RM_STATE state;\n\tstruct rm_meas_req q;\n\tstruct rm_meas_rep p;\n\tstruct sta_info *psta;\n\tstruct rm_clock *pclock;\n\n\t/* meas report */\n\tu64 meas_start_time;\n\tu64 meas_end_time;\n\tint wait_busy;\n\tu8 poll_mode;\n\n\tstruct data_buf buf[MAX_BUF_NUM];\n\n\t_list list;\n};\n\n/*\n* Measurement\n*/\nstruct opt_subelement {\n\tu8 id;\n\tu8 length;\n\tu8 *data;\n};\n\n/* 802.11-2012 Table 8-206 Radio Measurment Action field */\nenum rm_action_code {\n\tRM_ACT_RADIO_MEAS_REQ,\n\tRM_ACT_RADIO_MEAS_REP,\n\tRM_ACT_LINK_MEAS_REQ,\n\tRM_ACT_LINK_MEAS_REP,\n\tRM_ACT_NB_REP_REQ,\t/* 4 */\n\tRM_ACT_NB_REP_RESP,\n\tRM_ACT_RESV,\n\tRM_ACT_MAX\n};\n\n/* 802.11-2012 Table 8-119 RM Enabled Capabilities definition */\nenum rm_cap_en {\n\tRM_LINK_MEAS_CAP_EN,\n\tRM_NB_REP_CAP_EN,\t\t/* neighbor report */\n\tRM_PARAL_MEAS_CAP_EN,\t\t/* parallel report */\n\tRM_REPEAT_MEAS_CAP_EN,\n\tRM_BCN_PASSIVE_MEAS_CAP_EN,\n\tRM_BCN_ACTIVE_MEAS_CAP_EN,\n\tRM_BCN_TABLE_MEAS_CAP_EN,\n\tRM_BCN_MEAS_REP_COND_CAP_EN,\t/* conditions */\n\n\tRM_FRAME_MEAS_CAP_EN,\n\tRM_CH_LOAD_CAP_EN,\n\tRM_NOISE_HISTO_CAP_EN,\t\t/* noise historgram */\n\tRM_STATIS_MEAS_CAP_EN,\t\t/* statistics */\n\tRM_LCI_MEAS_CAP_EN,\t\t/* 12 */\n\tRM_LCI_AMIMUTH_CAP_EN,\n\tRM_TRANS_STREAM_CAT_MEAS_CAP_EN,\n\tRM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN,\n\n\tRM_AP_CH_REP_CAP_EN,\n\tRM_RM_MIB_CAP_EN,\n\tRM_OP_CH_MAX_MEAS_DUR0,\t\t/* 18-20 */\n\tRM_OP_CH_MAX_MEAS_DUR1,\n\tRM_OP_CH_MAX_MEAS_DUR2,\n\tRM_NONOP_CH_MAX_MEAS_DUR0,\t/* 21-23 */\n\tRM_NONOP_CH_MAX_MEAS_DUR1,\n\tRM_NONOP_CH_MAX_MEAS_DUR2,\n\n\tRM_MEAS_PILOT_CAP0,\t\t/* 24-26 */\n\tRM_MEAS_PILOT_CAP1,\n\tRM_MEAS_PILOT_CAP2,\n\tRM_MEAS_PILOT_TRANS_INFO_CAP_EN,\n\tRM_NB_REP_TSF_OFFSET_CAP_EN,\n\tRM_RCPI_MEAS_CAP_EN,\t\t/* 29 */\n\tRM_RSNI_MEAS_CAP_EN,\n\tRM_BSS_AVG_ACCESS_DELAY_CAP_EN,\n\n\tRM_AVALB_ADMIS_CAPACITY_CAP_EN,\n\tRM_ANT_CAP_EN,\n\tRM_RSVD,\t\t\t/* 34-39 */\n\tRM_MAX\n};\n\nchar *rm_state_name(enum RM_STATE state);\nchar *rm_event_name(enum RM_EV_ID evid);\nchar *rm_type_req_name(u8 meas_type);\nint _rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid);\nint rm_enqueue_rmobj(_adapter *padapter, struct rm_obj *obj, bool to_head);\n\nvoid rm_free_rmobj(struct rm_obj *prm);\nstruct rm_obj *rm_alloc_rmobj(_adapter *padapter);\nstruct rm_obj *rm_get_rmobj(_adapter *padapter, u32 rmid);\nstruct sta_info *rm_get_psta(_adapter *padapter, u32 rmid);\n\nint retrieve_radio_meas_result(struct rm_obj *prm);\nint rm_radio_meas_report_cond(struct rm_obj *prm);\nint rm_recv_radio_mens_req(_adapter *padapter,\n\tunion recv_frame *precv_frame,struct sta_info *psta);\nint rm_recv_radio_mens_rep(_adapter *padapter,\n\tunion recv_frame *precv_frame, struct sta_info *psta);\nint rm_radio_mens_nb_rep(_adapter *padapter,\n\tunion recv_frame *precv_frame, struct sta_info *psta);\nint issue_null_reply(struct rm_obj *prm);\nint issue_beacon_rep(struct rm_obj *prm);\nint issue_nb_req(struct rm_obj *prm);\nint issue_radio_meas_req(struct rm_obj *prm);\nint issue_radio_meas_rep(struct rm_obj *prm);\n\nvoid rm_set_rep_mode(struct rm_obj *prm, u8 mode);\n\nint ready_for_scan(struct rm_obj *prm);\nint rm_sitesurvey(struct rm_obj *prm);\n\n#endif /*CONFIG_RTW_80211K*/\n#endif /*__RTW_RM_FSM_H_*/\n"
  },
  {
    "path": "include/rtw_rson.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along with\n * this program; if not, write to the Free Software Foundation, Inc.,\n * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\n *\n *\n ******************************************************************************/\n#ifndef __RTW_RSON_H_\n#define __RTW_RSON_H_\n\n\n#define RTW_RSON_VER\t\t\t\t\t\t1\n\n#define RTW_RSON_SCORE_NOTSUP\t\t\t0x0\n#define RTW_RSON_SCORE_NOTCNNT\t\t\t0x1\n#define RTW_RSON_SCORE_MAX\t\t\t\t0xFF\n#define RTW_RSON_HC_NOTREADY\t\t\t0xFF\n#define RTW_RSON_HC_ROOT\t\t\t\t0x0\n#define RTW_RSON_ALLOWCONNECT\t\t\t0x1\n#define RTW_RSON_DENYCONNECT\t\t\t0x0\n\n\n\n/*\tfor rtw self-origanization spec 1\t*/\nstruct rtw_rson_struct {\n\tu8 ver;\n\tu32 id;\n\tu8 hopcnt;\n\tu8 connectible;\n\tu8 loading;\n\tu8 res[16];\n} __attribute__((__packed__));\n\nvoid init_rtw_rson_data(struct dvobj_priv *dvobj);\nvoid rtw_rson_get_property_str(_adapter *padapter, char *rson_data_str);\nint rtw_rson_set_property(_adapter *padapter, char *field, char *value);\nint rtw_rson_choose(struct wlan_network **candidate, struct wlan_network *competitor);\nint rtw_get_rson_struct(WLAN_BSSID_EX *bssid, struct  rtw_rson_struct *rson_data);\nu8 rtw_cal_rson_score(struct rtw_rson_struct *cand_rson_data, NDIS_802_11_RSSI  Rssi);\nvoid rtw_rson_handle_ie(WLAN_BSSID_EX *bssid, u8 ie_offset);\nu32 rtw_rson_append_ie(_adapter *padapter, unsigned char *pframe, u32 *len);\nvoid rtw_rson_do_disconnect(_adapter *padapter);\nvoid rtw_rson_join_done(_adapter *padapter);\nint rtw_rson_isupdate_roamcan(struct mlme_priv *mlme, struct wlan_network **candidate, struct wlan_network *competitor);\nvoid rtw_rson_show_survey_info(struct seq_file *m, _list *plist, _list *phead);\nu8 rtw_rson_ap_check_sta(_adapter *padapter, u8 *pframe, uint pkt_len, unsigned short ie_offset);\nu8 rtw_rson_scan_wk_cmd(_adapter *padapter, int op);\nvoid rtw_rson_scan_cmd_hdl(_adapter *padapter, int op);\n#endif /* __RTW_RSON_H_ */\n"
  },
  {
    "path": "include/rtw_sdio.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2015 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTW_SDIO_H_\n#define _RTW_SDIO_H_\n\n#include <drv_types.h>\t\t/* struct dvobj_priv and etc. */\n\nu8 rtw_sdio_read_cmd52(struct dvobj_priv *, u32 addr, void *buf, size_t len);\nu8 rtw_sdio_read_cmd53(struct dvobj_priv *, u32 addr, void *buf, size_t len);\nu8 rtw_sdio_write_cmd52(struct dvobj_priv *, u32 addr, void *buf, size_t len);\nu8 rtw_sdio_write_cmd53(struct dvobj_priv *, u32 addr, void *buf, size_t len);\nu8 rtw_sdio_f0_read(struct dvobj_priv *, u32 addr, void *buf, size_t len);\n\n#endif /* _RTW_SDIO_H_ */\n"
  },
  {
    "path": "include/rtw_security.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_SECURITY_H_\n#define __RTW_SECURITY_H_\n\n\n#define _NO_PRIVACY_\t\t0x0\n#define _WEP40_\t\t\t\t0x1\n#define _TKIP_\t\t\t\t0x2\n#define _TKIP_WTMIC_\t\t0x3\n#define _AES_\t\t\t\t0x4\n#define _WEP104_\t\t\t0x5\n#define _SMS4_\t\t\t\t0x06\n#define _WEP_WPA_MIXED_\t\t0x07 /* WEP + WPA */\n#define _BIP_\t\t\t\t0x8\n\n/* 802.11W use wrong key */\n#define IEEE80211W_RIGHT_KEY\t0x0\n#define IEEE80211W_WRONG_KEY\t0x1\n#define IEEE80211W_NO_KEY\t\t0x2\n\n#define CCMPH_2_PN(ch)\t((ch) & 0x000000000000ffff) \\\n\t\t\t| (((ch) & 0xffffffff00000000) >> 16)\n\n#define is_wep_enc(alg) (((alg) == _WEP40_) || ((alg) == _WEP104_))\n\nconst char *security_type_str(u8 value);\n\n#define _WPA_IE_ID_\t0xdd\n#define _WPA2_IE_ID_\t0x30\n\n#define SHA256_MAC_LEN 32\n#define AES_BLOCK_SIZE 16\n#define AES_PRIV_SIZE (4 * 44)\n\n#define RTW_KEK_LEN 16\n#define RTW_KCK_LEN 16\n#define RTW_TKIP_MIC_LEN 8\n#define RTW_REPLAY_CTR_LEN 8\n\n#define INVALID_SEC_MAC_CAM_ID\t0xFF\n\ntypedef enum {\n\tENCRYP_PROTOCOL_OPENSYS,   /* open system */\n\tENCRYP_PROTOCOL_WEP,       /* WEP */\n\tENCRYP_PROTOCOL_WPA,       /* WPA */\n\tENCRYP_PROTOCOL_WPA2,      /* WPA2 */\n\tENCRYP_PROTOCOL_WAPI,      /* WAPI: Not support in this version */\n\tENCRYP_PROTOCOL_MAX\n} ENCRYP_PROTOCOL_E;\n\n\n#ifndef Ndis802_11AuthModeWPA2\n#define Ndis802_11AuthModeWPA2 (Ndis802_11AuthModeWPANone + 1)\n#endif\n\n#ifndef Ndis802_11AuthModeWPA2PSK\n#define Ndis802_11AuthModeWPA2PSK (Ndis802_11AuthModeWPANone + 2)\n#endif\n\nunion pn48\t{\n\n\tu64\tval;\n\n#ifdef CONFIG_LITTLE_ENDIAN\n\nstruct {\n\tu8 TSC0;\n\tu8 TSC1;\n\tu8 TSC2;\n\tu8 TSC3;\n\tu8 TSC4;\n\tu8 TSC5;\n\tu8 TSC6;\n\tu8 TSC7;\n} _byte_;\n\n#elif defined(CONFIG_BIG_ENDIAN)\n\nstruct {\n\tu8 TSC7;\n\tu8 TSC6;\n\tu8 TSC5;\n\tu8 TSC4;\n\tu8 TSC3;\n\tu8 TSC2;\n\tu8 TSC1;\n\tu8 TSC0;\n} _byte_;\n\n#endif\n\n};\n\nunion Keytype {\n\tu8   skey[16];\n\tu32    lkey[4];\n};\n\n\ntypedef struct _RT_PMKID_LIST {\n\tu8\t\t\t\t\t\tbUsed;\n\tu8\t\t\t\t\t\tBssid[6];\n\tu8\t\t\t\t\t\tPMKID[16];\n\tu8\t\t\t\t\t\tSsidBuf[33];\n\tu8\t\t\t\t\t\t*ssid_octet;\n\tu16\t\t\t\t\t\tssid_length;\n} RT_PMKID_LIST, *PRT_PMKID_LIST;\n\n\nstruct security_priv {\n\tu32\t  dot11AuthAlgrthm;\t\t/* 802.11 auth, could be open, shared, 8021x and authswitch */\n\tu32\t  dot11PrivacyAlgrthm;\t/* This specify the privacy for shared auth. algorithm. */\n\n\t/* WEP */\n\tu32\t  dot11PrivacyKeyIndex;\t/* this is only valid for legendary wep, 0~3 for key id. (tx key index) */\n\tunion Keytype dot11DefKey[6];\t\t\t/* this is only valid for def. key\t */\n\tu32\tdot11DefKeylen[6];\n\tu8\tdot11Def_camid[6];\n\tu8 \tkey_mask; /* use to restore wep key after hal_init */\n\n\tu32 dot118021XGrpPrivacy;\t/* This specify the privacy algthm. used for Grp key */\n\tu32\tdot118021XGrpKeyid;\t\t/* key id used for Grp Key ( tx key index) */\n\tunion Keytype\tdot118021XGrpKey[6];\t/* 802.1x Group Key, for inx0 and inx1\t */\n\tunion Keytype\tdot118021XGrptxmickey[6];\n\tunion Keytype\tdot118021XGrprxmickey[6];\n\tunion pn48\t\tdot11Grptxpn;\t\t\t/* PN48 used for Grp Key xmit. */\n\tunion pn48\t\tdot11Grprxpn;\t\t\t/* PN48 used for Grp Key recv. */\n\tu8\t\t\t\tiv_seq[4][8];\n#ifdef CONFIG_IEEE80211W\n\tu32\tdot11wBIPKeyid;\t\t\t\t\t\t/* key id used for BIP Key ( tx key index) */\n\tunion Keytype\tdot11wBIPKey[6];\t\t/* BIP Key, for index4 and index5 */\n\tunion pn48\t\tdot11wBIPtxpn;\t\t\t/* PN48 used for BIP xmit. */\n\tunion pn48\t\tdot11wBIPrxpn;\t\t\t/* PN48 used for BIP recv. */\n#endif /* CONFIG_IEEE80211W */\n#ifdef CONFIG_AP_MODE\n\t/* extend security capabilities for AP_MODE */\n\tunsigned int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */\n\tunsigned int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */\n\tunsigned int wpa_group_cipher;\n\tunsigned int wpa2_group_cipher;\n\tunsigned int wpa_pairwise_cipher;\n\tunsigned int wpa2_pairwise_cipher;\n\tu8 mfp_opt;\n#endif\n#ifdef CONFIG_CONCURRENT_MODE\n\tu8\tdot118021x_bmc_cam_id;\n#endif\n\t/*IEEE802.11-2012 Std. Table 8-101 AKM Suite Selectors*/\n\tu32\trsn_akm_suite_type;\n\n\tu8 wps_ie[MAX_WPS_IE_LEN];/* added in assoc req */\n\tint wps_ie_len;\n\n\n\tu8\tbinstallGrpkey;\n#ifdef CONFIG_GTK_OL\n\tu8\tbinstallKCK_KEK;\n#endif /* CONFIG_GTK_OL */\n#ifdef CONFIG_IEEE80211W\n\tu8\tbinstallBIPkey;\n#endif /* CONFIG_IEEE80211W */\n\tu8\tbusetkipkey;\n\tu8\tbcheck_grpkey;\n\tu8\tbgrpkey_handshake;\n\n\tu8\tauth_alg;\n\tu8\tauth_type;\n\tu8\textauth_status;\n\t/* u8\tpacket_cnt; */ /* unused, removed */\n\n\ts32\tsw_encrypt;/* from registry_priv */\n\ts32\tsw_decrypt;/* from registry_priv */\n\n\ts32 \thw_decrypted;/* if the rx packets is hw_decrypted==_FALSE, it means the hw has not been ready. */\n\n\n\t/* keeps the auth_type & enc_status from upper layer ioctl(wpa_supplicant or wzc) */\n\tu32 ndisauthtype;\t/* NDIS_802_11_AUTHENTICATION_MODE */\n\tu32 ndisencryptstatus;\t/* NDIS_802_11_ENCRYPTION_STATUS */\n\n\tNDIS_802_11_WEP ndiswep;\n\n\tu8 assoc_info[600];\n\tu8 szofcapability[256]; /* for wpa2 usage */\n\tu8 oidassociation[512]; /* for wpa/wpa2 usage */\n\tu8 authenticator_ie[256];  /* store ap security information element */\n\tu8 supplicant_ie[256];  /* store sta security information element */\n\n\n\t/* for tkip countermeasure */\n\tsystime last_mic_err_time;\n\tu8\tbtkip_countermeasure;\n\tu8\tbtkip_wait_report;\n\tsystime btkip_countermeasure_time;\n\n\t/* --------------------------------------------------------------------------- */\n\t/* For WPA2 Pre-Authentication. */\n\t/* --------------------------------------------------------------------------- */\n\t/* u8\t\t\t\tRegEnablePreAuth;\t\t\t\t */ /* Default value: Pre-Authentication enabled or not, from registry \"EnablePreAuth\". Added by Annie, 2005-11-01. */\n\t/* u8\t\t\t\tEnablePreAuthentication;\t\t\t */ /* Current Value: Pre-Authentication enabled or not. */\n\tRT_PMKID_LIST\t\tPMKIDList[NUM_PMKID_CACHE];\t/* Renamed from PreAuthKey[NUM_PRE_AUTH_KEY]. Annie, 2006-10-13. */\n\tu8\t\t\t\tPMKIDIndex;\n\t/* u32\t\t\t\tPMKIDCount;\t\t\t\t\t\t */ /* Added by Annie, 2006-10-13. */\n\t/* u8\t\t\t\tszCapability[256];\t\t\t\t */ /* For WPA2-PSK using zero-config, by Annie, 2005-09-20. */\n\n\tu8 bWepDefaultKeyIdxSet;\n\n#define DBG_SW_SEC_CNT\n#ifdef DBG_SW_SEC_CNT\n\tu64 wep_sw_enc_cnt_bc;\n\tu64 wep_sw_enc_cnt_mc;\n\tu64 wep_sw_enc_cnt_uc;\n\tu64 wep_sw_dec_cnt_bc;\n\tu64 wep_sw_dec_cnt_mc;\n\tu64 wep_sw_dec_cnt_uc;\n\n\tu64 tkip_sw_enc_cnt_bc;\n\tu64 tkip_sw_enc_cnt_mc;\n\tu64 tkip_sw_enc_cnt_uc;\n\tu64 tkip_sw_dec_cnt_bc;\n\tu64 tkip_sw_dec_cnt_mc;\n\tu64 tkip_sw_dec_cnt_uc;\n\n\tu64 aes_sw_enc_cnt_bc;\n\tu64 aes_sw_enc_cnt_mc;\n\tu64 aes_sw_enc_cnt_uc;\n\tu64 aes_sw_dec_cnt_bc;\n\tu64 aes_sw_dec_cnt_mc;\n\tu64 aes_sw_dec_cnt_uc;\n#endif /* DBG_SW_SEC_CNT */\n};\n\n#ifdef CONFIG_IEEE80211W\n#define SEC_IS_BIP_KEY_INSTALLED(sec) ((sec)->binstallBIPkey)\n#else\n#define SEC_IS_BIP_KEY_INSTALLED(sec) _FALSE\n#endif\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))\nstruct sha256_state {\n\tu64 length;\n\tu32 state[8], curlen;\n\tu8 buf[64];\n};\n#endif\n\n#define GET_ENCRY_ALGO(psecuritypriv, psta, encry_algo, bmcst)\\\n\tdo {\\\n\t\tswitch (psecuritypriv->dot11AuthAlgrthm) {\\\n\t\tcase dot11AuthAlgrthm_Open:\\\n\t\tcase dot11AuthAlgrthm_Shared:\\\n\t\tcase dot11AuthAlgrthm_Auto:\\\n\t\t\tencry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\\\n\t\t\tbreak;\\\n\t\tcase dot11AuthAlgrthm_8021X:\\\n\t\t\tif (bmcst)\\\n\t\t\t\tencry_algo = (u8)psecuritypriv->dot118021XGrpPrivacy;\\\n\t\t\telse\\\n\t\t\t\tencry_algo = (u8) psta->dot118021XPrivacy;\\\n\t\t\tbreak;\\\n\t\tcase dot11AuthAlgrthm_WAPI:\\\n\t\t\tencry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\\\n\t\t\tbreak;\\\n\t\t} \\\n\t} while (0)\n\n#define _AES_IV_LEN_ 8\n\n#define SET_ICE_IV_LEN(iv_len, icv_len, encrypt)\\\n\tdo {\\\n\t\tswitch (encrypt) {\\\n\t\tcase _WEP40_:\\\n\t\tcase _WEP104_:\\\n\t\t\tiv_len = 4;\\\n\t\t\ticv_len = 4;\\\n\t\t\tbreak;\\\n\t\tcase _TKIP_:\\\n\t\t\tiv_len = 8;\\\n\t\t\ticv_len = 4;\\\n\t\t\tbreak;\\\n\t\tcase _AES_:\\\n\t\t\tiv_len = 8;\\\n\t\t\ticv_len = 8;\\\n\t\t\tbreak;\\\n\t\tcase _SMS4_:\\\n\t\t\tiv_len = 18;\\\n\t\t\ticv_len = 16;\\\n\t\t\tbreak;\\\n\t\tdefault:\\\n\t\t\tiv_len = 0;\\\n\t\t\ticv_len = 0;\\\n\t\t\tbreak;\\\n\t\t} \\\n\t} while (0)\n\n\n#define GET_TKIP_PN(iv, dot11txpn)\\\n\tdo {\\\n\t\tdot11txpn._byte_.TSC0 = iv[2];\\\n\t\tdot11txpn._byte_.TSC1 = iv[0];\\\n\t\tdot11txpn._byte_.TSC2 = iv[4];\\\n\t\tdot11txpn._byte_.TSC3 = iv[5];\\\n\t\tdot11txpn._byte_.TSC4 = iv[6];\\\n\t\tdot11txpn._byte_.TSC5 = iv[7];\\\n\t} while (0)\n\n\n#define ROL32(A, n)\t(((A) << (n)) | (((A)>>(32-(n)))  & ((1UL << (n)) - 1)))\n#define ROR32(A, n)\tROL32((A), 32-(n))\n\nstruct mic_data {\n\tu32  K0, K1;         /* Key */\n\tu32  L, R;           /* Current state */\n\tu32  M;              /* Message accumulator (single word) */\n\tu32     nBytesInM;      /*  # bytes in M */\n};\n\nextern const u32 Te0[256];\nextern const u32 Te1[256];\nextern const u32 Te2[256];\nextern const u32 Te3[256];\nextern const u32 Te4[256];\nextern const u32 Td0[256];\nextern const u32 Td1[256];\nextern const u32 Td2[256];\nextern const u32 Td3[256];\nextern const u32 Td4[256];\nextern const u32 rcon[10];\nextern const u8 Td4s[256];\nextern const u8 rcons[10];\n\n#define RCON(i) (rcons[(i)] << 24)\n\nstatic inline u32 rotr(u32 val, int bits)\n{\n\treturn (val >> bits) | (val << (32 - bits));\n}\n\n#define TE0(i) Te0[((i) >> 24) & 0xff]\n#define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8)\n#define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16)\n#define TE3(i) rotr(Te0[(i) & 0xff], 24)\n#define TE41(i) ((Te0[((i) >> 24) & 0xff] << 8) & 0xff000000)\n#define TE42(i) (Te0[((i) >> 16) & 0xff] & 0x00ff0000)\n#define TE43(i) (Te0[((i) >> 8) & 0xff] & 0x0000ff00)\n#define TE44(i) ((Te0[(i) & 0xff] >> 8) & 0x000000ff)\n#define TE421(i) ((Te0[((i) >> 16) & 0xff] << 8) & 0xff000000)\n#define TE432(i) (Te0[((i) >> 8) & 0xff] & 0x00ff0000)\n#define TE443(i) (Te0[(i) & 0xff] & 0x0000ff00)\n#define TE414(i) ((Te0[((i) >> 24) & 0xff] >> 8) & 0x000000ff)\n#define TE4(i) ((Te0[(i)] >> 8) & 0x000000ff)\n\n#define TD0(i) Td0[((i) >> 24) & 0xff]\n#define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8)\n#define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16)\n#define TD3(i) rotr(Td0[(i) & 0xff], 24)\n#define TD41(i) (Td4s[((i) >> 24) & 0xff] << 24)\n#define TD42(i) (Td4s[((i) >> 16) & 0xff] << 16)\n#define TD43(i) (Td4s[((i) >> 8) & 0xff] << 8)\n#define TD44(i) (Td4s[(i) & 0xff])\n#define TD0_(i) Td0[(i) & 0xff]\n#define TD1_(i) rotr(Td0[(i) & 0xff], 8)\n#define TD2_(i) rotr(Td0[(i) & 0xff], 16)\n#define TD3_(i) rotr(Td0[(i) & 0xff], 24)\n\n#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ \\\n\t\t\t((u32)(pt)[2] <<  8) ^ ((u32)(pt)[3]))\n\n#define PUTU32(ct, st) { \\\n\t\t(ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); \\\n\t\t(ct)[2] = (u8)((st) >>  8); (ct)[3] = (u8)(st); }\n\n#define WPA_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \\\n\t\t\t (((u32) (a)[2]) << 8) | ((u32) (a)[3]))\n\n#define WPA_PUT_LE16(a, val)\t\t\t\\\n\tdo {\t\t\t\t\t\\\n\t\t(a)[1] = ((u16) (val)) >> 8;\t\\\n\t\t(a)[0] = ((u16) (val)) & 0xff;\t\\\n\t} while (0)\n\n#define WPA_PUT_BE32(a, val)\t\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\t(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff);\t\\\n\t\t(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff);\t\\\n\t\t(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff);\t\\\n\t\t(a)[3] = (u8) (((u32) (val)) & 0xff);\t\t\\\n\t} while (0)\n\n#define WPA_PUT_BE64(a, val)\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\\\n\t\t(a)[0] = (u8) (((u64) (val)) >> 56);\t\\\n\t\t(a)[1] = (u8) (((u64) (val)) >> 48);\t\\\n\t\t(a)[2] = (u8) (((u64) (val)) >> 40);\t\\\n\t\t(a)[3] = (u8) (((u64) (val)) >> 32);\t\\\n\t\t(a)[4] = (u8) (((u64) (val)) >> 24);\t\\\n\t\t(a)[5] = (u8) (((u64) (val)) >> 16);\t\\\n\t\t(a)[6] = (u8) (((u64) (val)) >> 8);\t\\\n\t\t(a)[7] = (u8) (((u64) (val)) & 0xff);\t\\\n\t} while (0)\n\n/* the K array */\nstatic const unsigned long K[64] = {\n\t0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL,\n\t0x59f111f1UL, 0x923f82a4UL, 0xab1c5ed5UL, 0xd807aa98UL, 0x12835b01UL,\n\t0x243185beUL, 0x550c7dc3UL, 0x72be5d74UL, 0x80deb1feUL, 0x9bdc06a7UL,\n\t0xc19bf174UL, 0xe49b69c1UL, 0xefbe4786UL, 0x0fc19dc6UL, 0x240ca1ccUL,\n\t0x2de92c6fUL, 0x4a7484aaUL, 0x5cb0a9dcUL, 0x76f988daUL, 0x983e5152UL,\n\t0xa831c66dUL, 0xb00327c8UL, 0xbf597fc7UL, 0xc6e00bf3UL, 0xd5a79147UL,\n\t0x06ca6351UL, 0x14292967UL, 0x27b70a85UL, 0x2e1b2138UL, 0x4d2c6dfcUL,\n\t0x53380d13UL, 0x650a7354UL, 0x766a0abbUL, 0x81c2c92eUL, 0x92722c85UL,\n\t0xa2bfe8a1UL, 0xa81a664bUL, 0xc24b8b70UL, 0xc76c51a3UL, 0xd192e819UL,\n\t0xd6990624UL, 0xf40e3585UL, 0x106aa070UL, 0x19a4c116UL, 0x1e376c08UL,\n\t0x2748774cUL, 0x34b0bcb5UL, 0x391c0cb3UL, 0x4ed8aa4aUL, 0x5b9cca4fUL,\n\t0x682e6ff3UL, 0x748f82eeUL, 0x78a5636fUL, 0x84c87814UL, 0x8cc70208UL,\n\t0x90befffaUL, 0xa4506cebUL, 0xbef9a3f7UL, 0xc67178f2UL\n};\n\n\n/* Various logical functions */\n#define RORc(x, y) \\\n\t(((((unsigned long) (x) & 0xFFFFFFFFUL) >> (unsigned long) ((y) & 31)) | \\\n\t  ((unsigned long) (x) << (unsigned long) (32 - ((y) & 31)))) & 0xFFFFFFFFUL)\n#define Ch(x, y, z)       (z ^ (x & (y ^ z)))\n#define Maj(x, y, z)      (((x | y) & z) | (x & y))\n#define S(x, n)         RORc((x), (n))\n#define R(x, n)         (((x) & 0xFFFFFFFFUL)>>(n))\n#define Sigma0(x)       (S(x, 2) ^ S(x, 13) ^ S(x, 22))\n#define Sigma1(x)       (S(x, 6) ^ S(x, 11) ^ S(x, 25))\n#define Gamma0(x)       (S(x, 7) ^ S(x, 18) ^ R(x, 3))\n#define Gamma1(x)       (S(x, 17) ^ S(x, 19) ^ R(x, 10))\n#ifndef MIN\n#define MIN(x, y) (((x) < (y)) ? (x) : (y))\n#endif\n#ifdef CONFIG_IEEE80211W\nint omac1_aes_128(const u8 *key, const u8 *data, size_t data_len, u8 *mac);\n#endif /* CONFIG_IEEE80211W */\n#ifdef CONFIG_RTW_MESH_AEK\nint aes_siv_encrypt(const u8 *key, const u8 *pw, size_t pwlen\n\t, size_t num_elem, const u8 *addr[], const size_t *len, u8 *out);\nint aes_siv_decrypt(const u8 *key, const u8 *iv_crypt, size_t iv_c_len\n\t, size_t num_elem, const u8 *addr[], const size_t *len, u8 *out);\n#endif\nvoid rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key);\nvoid rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b);\nvoid rtw_secmicappend(struct mic_data *pmicdata, u8 *src, u32 nBytes);\nvoid rtw_secgetmic(struct mic_data *pmicdata, u8 *dst);\n\nvoid rtw_seccalctkipmic(\n\tu8 *key,\n\tu8 *header,\n\tu8 *data,\n\tu32 data_len,\n\tu8 *Miccode,\n\tu8   priority);\n\nu32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe);\nu32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe);\nvoid rtw_wep_encrypt(_adapter *padapter, u8  *pxmitframe);\n\nu32 rtw_aes_decrypt(_adapter *padapter, u8  *precvframe);\nu32 rtw_tkip_decrypt(_adapter *padapter, u8  *precvframe);\nvoid rtw_wep_decrypt(_adapter *padapter, u8  *precvframe);\n#ifdef CONFIG_IEEE80211W\nu32\trtw_BIP_verify(_adapter *padapter, u8 *whdr_pos, sint flen\n\t, const u8 *key, u16 id, u64* ipn);\n#endif\n#ifdef CONFIG_TDLS\nvoid wpa_tdls_generate_tpk(_adapter *padapter, void *sta);\nint wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq,\n\t\t\tu8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie,\n\t\t\tu8 *mic);\nint wpa_tdls_teardown_ftie_mic(u8 *kck, u8 *lnkid, u16 reason,\n\t\t\tu8 dialog_token, u8 trans_seq, u8 *ftie, u8 *mic);\nint tdls_verify_mic(u8 *kck, u8 trans_seq,\n\t\t\tu8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie);\n#endif /* CONFIG_TDLS */\n\nvoid rtw_sec_restore_wep_key(_adapter *adapter);\nu8 rtw_handle_tkip_countermeasure(_adapter *adapter, const char *caller);\n\n#ifdef CONFIG_WOWLAN\nu16 rtw_calc_crc(u8  *pdata, int length);\n#endif /*CONFIG_WOWLAN*/\n\n#define rtw_sec_chk_auth_alg(a, s) \\\n\t((a)->securitypriv.auth_alg == (s))\n\n#define rtw_sec_chk_auth_type(a, s) \\\n\t((a)->securitypriv.auth_type == (s))\n\n#endif /* __RTL871X_SECURITY_H_ */\n"
  },
  {
    "path": "include/rtw_sreset.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTW_SRESET_H_\n#define _RTW_SRESET_H_\n\n/* #include <drv_types.h> */\n\nenum {\n\tSRESET_TGP_NULL = 0,\n\tSRESET_TGP_XMIT_STATUS = 1,\n\tSRESET_TGP_LINK_STATUS = 2,\n\tSRESET_TGP_INFO = 99,\n};\n\nstruct sreset_priv {\n\t_mutex\tsilentreset_mutex;\n\tu8\tsilent_reset_inprogress;\n\tu8\tWifi_Error_Status;\n\tsystime last_tx_time;\n\tsystime last_tx_complete_time;\n\n\ts32 dbg_trigger_point;\n\tu64 self_dect_tx_cnt;\n\tu64 self_dect_rx_cnt;\n\tu64 self_dect_fw_cnt;\n\tu64 tx_dma_status_cnt;\n\tu64 rx_dma_status_cnt;\n\tu8 rx_cnt;\n\tu8 self_dect_fw;\n\tu8 self_dect_case;\n\tu16 last_mac_rxff_ptr;\n\tu8 dbg_sreset_ctrl;\n};\n\n\n\n#define\tWIFI_STATUS_SUCCESS\t\t0\n#define\tUSB_VEN_REQ_CMD_FAIL\tBIT0\n#define\tUSB_READ_PORT_FAIL\t\tBIT1\n#define\tUSB_WRITE_PORT_FAIL\t\tBIT2\n#define\tWIFI_MAC_TXDMA_ERROR\tBIT3\n#define   WIFI_TX_HANG\t\t\t\tBIT4\n#define\tWIFI_RX_HANG\t\t\t\tBIT5\n#define\tWIFI_IF_NOT_EXIST\t\t\tBIT6\n\nvoid sreset_init_value(_adapter *padapter);\nvoid sreset_reset_value(_adapter *padapter);\nu8 sreset_get_wifi_status(_adapter *padapter);\nvoid sreset_set_wifi_error_status(_adapter *padapter, u32 status);\nvoid sreset_set_trigger_point(_adapter *padapter, s32 tgp);\nbool sreset_inprogress(_adapter *padapter);\nvoid sreset_reset(_adapter *padapter);\n\n#endif\n"
  },
  {
    "path": "include/rtw_tdls.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_TDLS_H_\n#define __RTW_TDLS_H_\n\n\n#ifdef CONFIG_TDLS\n/* TDLS STA state */\n\n\n/* TDLS Diect Link Establishment */\n#define\tTDLS_STATE_NONE\t\t\t\t0x00000000\t\t/* Default state */\n#define\tTDLS_INITIATOR_STATE\t\tBIT(28)\t\t\t/* 0x10000000 */\n#define\tTDLS_RESPONDER_STATE\t\tBIT(29)\t\t\t/* 0x20000000 */\n#define\tTDLS_LINKED_STATE\t\t\tBIT(30)\t\t\t/* 0x40000000 */\n/* TDLS PU Buffer STA */\n#define\tTDLS_WAIT_PTR_STATE\t\t\tBIT(24)\t\t\t/* 0x01000000 */\t/* Waiting peer's TDLS_PEER_TRAFFIC_RESPONSE frame */\n/* TDLS Check ALive */\n#define\tTDLS_ALIVE_STATE\t\t\tBIT(20)\t\t\t/* 0x00100000 */\t/* Check if peer sta is alived. */\n/* TDLS Channel Switch */\n#define\tTDLS_CH_SWITCH_PREPARE_STATE\tBIT(15)\t\t\t/* 0x00008000 */\n#define\tTDLS_CH_SWITCH_ON_STATE\t\t\tBIT(16)\t\t\t/* 0x00010000 */\n#define\tTDLS_PEER_AT_OFF_STATE\t\t\tBIT(17)\t\t\t/* 0x00020000 */\t/* Could send pkt on target ch */\n#define\tTDLS_CH_SW_INITIATOR_STATE\t\tBIT(18)\t\t\t/* 0x00040000 */\t/* Avoid duplicated or unconditional ch. switch rsp. */\n#define\tTDLS_WAIT_CH_RSP_STATE\t\t\tBIT(19)\t\t\t/* 0x00080000 */\t/* Wait Ch. response as we are TDLS channel switch initiator */\n\n\n#define\tTDLS_TPK_RESEND_COUNT\t\t\t86400\t/*Unit: seconds */\n#define\tTDLS_CH_SWITCH_TIME\t\t\t\t15\n#define\tTDLS_CH_SWITCH_TIMEOUT\t\t\t30\n#define\tTDLS_CH_SWITCH_OPER_OFFLOAD_TIMEOUT\t10\n#define\tTDLS_SIGNAL_THRESH\t\t\t0x20\n#define\tTDLS_WATCHDOG_PERIOD\t\t10\t/* Periodically sending tdls discovery request in TDLS_WATCHDOG_PERIOD * 2 sec */\n#define\tTDLS_HANDSHAKE_TIME\t\t\t3000\n#define\tTDLS_PTI_TIME\t\t\t\t7000\n\n#define TDLS_CH_SW_STAY_ON_BASE_CHNL_TIMEOUT\t20\t\t/* ms */\n#define TDLS_CH_SW_MONITOR_TIMEOUT\t\t\t\t2000\t/*ms */\n\n#define TDLS_MIC_LEN 16\n#define WPA_NONCE_LEN 32\n#define TDLS_TIMEOUT_LEN 4\n\nenum TDLS_CH_SW_CHNL {\n\tTDLS_CH_SW_BASE_CHNL = 0,\n\tTDLS_CH_SW_OFF_CHNL\n};\n\n#define TDLS_MIC_CTRL_LEN 2\n#define TDLS_FTIE_DATA_LEN (TDLS_MIC_CTRL_LEN + TDLS_MIC_LEN + \\\n\t\t\t\t\t\t\tWPA_NONCE_LEN + WPA_NONCE_LEN)\nstruct wpa_tdls_ftie {\n\tu8 ie_type; /* FTIE */\n\tu8 ie_len;\n\tunion {\n\t\tstruct {\n\t\t\tu8 mic_ctrl[TDLS_MIC_CTRL_LEN];\n\t\t\tu8 mic[TDLS_MIC_LEN];\n\t\t\tu8 Anonce[WPA_NONCE_LEN]; /* Responder Nonce in TDLS */\n\t\t\tu8 Snonce[WPA_NONCE_LEN]; /* Initiator Nonce in TDLS */\n\t\t};\n\t\tstruct {\n\t\t\tu8 data[TDLS_FTIE_DATA_LEN];\n\t\t};\n\t};\n\t/* followed by optional elements */\n} ;\n\nstruct wpa_tdls_lnkid {\n\tu8 ie_type; /* Link Identifier IE */\n\tu8 ie_len;\n\tu8 bssid[ETH_ALEN];\n\tu8 init_sta[ETH_ALEN];\n\tu8 resp_sta[ETH_ALEN];\n} ;\n\nstatic u8 TDLS_RSNIE[20] = {\t0x01, 0x00,\t/* Version shall be set to 1 */\n\t\t\t\t0x00, 0x0f, 0xac, 0x07,\t/* Group sipher suite */\n\t\t\t\t0x01, 0x00,\t/* Pairwise cipher suite count */\n\t0x00, 0x0f, 0xac, 0x04,\t/* Pairwise cipher suite list; CCMP only */\n\t\t\t\t0x01, 0x00,\t/* AKM suite count */\n\t\t\t\t0x00, 0x0f, 0xac, 0x07,\t/* TPK Handshake */\n\t\t\t\t0x0c, 0x02,\n\t\t\t\t/* PMKID shall not be present */\n\t\t\t   };\n\nstatic u8 TDLS_WMMIE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00};\t/* Qos info all set zero */\n\nstatic u8 TDLS_WMM_PARAM_IE[] = {0x00, 0x00, 0x03, 0xa4, 0x00, 0x00, 0x27, 0xa4, 0x00, 0x00, 0x42, 0x43, 0x5e, 0x00, 0x62, 0x32, 0x2f, 0x00};\n\nstatic u8 TDLS_EXT_CAPIE[] = {0x00, 0x00, 0x00, 0x50, 0x20, 0x00, 0x00, 0x00};\t/* bit(28), bit(30), bit(37) */\n\n/* SRC: Supported Regulatory Classes */\nstatic u8 TDLS_SRC[] = { 0x01, 0x01, 0x02, 0x03, 0x04, 0x0c, 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1d, 0x1e, 0x20, 0x21 };\n\nint check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len);\nint check_ap_tdls_ch_switching_prohibited(u8 *pframe, u8 pkt_len);\n\nvoid rtw_set_tdls_enable(_adapter *padapter, u8 enable);\nu8 rtw_is_tdls_enabled(_adapter *padapter);\nu8 rtw_is_tdls_sta_existed(_adapter *padapter);\nu8 rtw_tdls_is_setup_allowed(_adapter *padapter);\n#ifdef CONFIG_TDLS_CH_SW\nu8 rtw_tdls_is_chsw_allowed(_adapter *padapter);\n#endif\n\nvoid rtw_tdls_set_link_established(_adapter *adapter, bool en);\nvoid rtw_reset_tdls_info(_adapter *padapter);\nint rtw_init_tdls_info(_adapter *padapter);\nvoid rtw_free_tdls_info(struct tdls_info *ptdlsinfo);\nvoid rtw_free_all_tdls_sta(_adapter *padapter, u8 enqueue_cmd);\nvoid rtw_enable_tdls_func(_adapter *padapter);\nvoid rtw_disable_tdls_func(_adapter *padapter, u8 enqueue_cmd);\nint issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms);\nvoid rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta);\nvoid\trtw_cancel_tdls_timer(struct sta_info *psta);\nvoid rtw_tdls_teardown_pre_hdl(_adapter *padapter, struct sta_info *psta);\nvoid rtw_tdls_teardown_post_hdl(_adapter *padapter, struct sta_info *psta, u8 enqueue_cmd);\n\n#ifdef CONFIG_TDLS_CH_SW\nvoid rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable);\nvoid rtw_tdls_ch_sw_back_to_base_chnl(_adapter *padapter);\ns32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_type, u8 channel, u8 channel_offset, u16 bwmode, u16 ch_switch_time);\nvoid rtw_tdls_chsw_oper_done(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_WFD\nint issue_tunneled_probe_req(_adapter *padapter);\nint issue_tunneled_probe_rsp(_adapter *padapter, union recv_frame *precv_frame);\n#endif /* CONFIG_WFD */\nint issue_tdls_dis_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt);\nint issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack);\nint issue_tdls_setup_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt);\nint issue_tdls_setup_cfm(_adapter *padapter, struct tdls_txmgmt *ptxmgmt);\nint issue_tdls_dis_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 privacy);\nint issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait_ack);\nint issue_tdls_peer_traffic_rsp(_adapter *padapter, struct sta_info *psta, struct tdls_txmgmt *ptxmgmt);\nint issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *psta);\n#ifdef CONFIG_TDLS_CH_SW\nint issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta);\nint issue_tdls_ch_switch_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack);\n#endif\nsint On_TDLS_Dis_Rsp(_adapter *adapter, union recv_frame *precv_frame);\nsint On_TDLS_Setup_Req(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);\nint On_TDLS_Setup_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);\nint On_TDLS_Setup_Cfm(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);\nint On_TDLS_Dis_Req(_adapter *adapter, union recv_frame *precv_frame);\nint On_TDLS_Teardown(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);\nint On_TDLS_Peer_Traffic_Indication(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);\nint On_TDLS_Peer_Traffic_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);\n#ifdef CONFIG_TDLS_CH_SW\nsint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);\nsint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);\nvoid rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);\nvoid rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);\n#endif\nvoid rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);\nvoid rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);\nvoid rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);\nvoid rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);\nvoid rtw_build_tdls_dis_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt);\nvoid rtw_build_tdls_dis_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, u8 privacy);\nvoid rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);\nvoid rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);\nvoid rtw_build_tunneled_probe_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe);\nvoid rtw_build_tunneled_probe_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe);\n\nint rtw_tdls_is_driver_setup(_adapter *padapter);\nvoid rtw_tdls_set_key(_adapter *padapter, struct sta_info *ptdls_sta);\nconst char *rtw_tdls_action_txt(enum TDLS_ACTION_FIELD action);\n#endif /* CONFIG_TDLS */\n\n#endif\n"
  },
  {
    "path": "include/rtw_version.h",
    "content": "#define DRIVERVERSION\t\"v5.7.3_35403.20240103\"\n#define BTCOEXVERSION\t\"COEX20190318-00\"\n"
  },
  {
    "path": "include/rtw_vht.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTW_VHT_H_\n#define _RTW_VHT_H_\n\n#define VHT_CAP_IE_LEN 12\n#define VHT_OP_IE_LEN 5\n\n#define\tLDPC_VHT_ENABLE_RX\t\t\tBIT0\n#define\tLDPC_VHT_ENABLE_TX\t\t\tBIT1\n#define\tLDPC_VHT_TEST_TX_ENABLE\t\tBIT2\n#define\tLDPC_VHT_CAP_TX\t\t\t\tBIT3\n\n#define\tSTBC_VHT_ENABLE_RX\t\t\tBIT0\n#define\tSTBC_VHT_ENABLE_TX\t\t\tBIT1\n#define\tSTBC_VHT_TEST_TX_ENABLE\t\tBIT2\n#define\tSTBC_VHT_CAP_TX\t\t\t\tBIT3\n\n/* VHT capability info */\n#define SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val)\n#define SET_VHT_CAPABILITY_ELE_CHL_WIDTH(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(_pEleStart, 2, 2, _val)\n#define SET_VHT_CAPABILITY_ELE_RX_LDPC(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(_pEleStart, 4, 1, _val)\n#define SET_VHT_CAPABILITY_ELE_SHORT_GI80M(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE(_pEleStart, 5, 1, _val)\n#define SET_VHT_CAPABILITY_ELE_SHORT_GI160M(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE(_pEleStart, 6, 1, _val)\n#define SET_VHT_CAPABILITY_ELE_TX_STBC(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE(_pEleStart, 7, 1, _val)\n#define SET_VHT_CAPABILITY_ELE_RX_STBC(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE((_pEleStart)+1, 0, 3, _val)\n#define SET_VHT_CAPABILITY_ELE_SU_BFER(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE((_pEleStart)+1, 3, 1, _val)\n#define SET_VHT_CAPABILITY_ELE_SU_BFEE(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE((_pEleStart)+1, 4, 1, _val)\n#define SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE((_pEleStart)+1, 5, 3, _val)\n#define SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE((_pEleStart)+2, 0, 3, _val)\n\n#define SET_VHT_CAPABILITY_ELE_MU_BFER(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE((_pEleStart)+2, 3, 1, _val)\n#define SET_VHT_CAPABILITY_ELE_MU_BFEE(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE((_pEleStart)+2, 4, 1, _val)\n#define SET_VHT_CAPABILITY_ELE_TXOP_PS(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE((_pEleStart)+2, 5, 1, _val)\n#define SET_VHT_CAPABILITY_ELE_HTC_VHT(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE((_pEleStart)+2, 6, 1, _val)\n#define SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(_pEleStart, _val)\t\tSET_BITS_TO_LE_2BYTE((_pEleStart)+2, 7, 3, _val) /* B23~B25 */\n#define SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_1BYTE((_pEleStart)+2, 2, 2, _val)\n#define SET_VHT_CAPABILITY_ELE_MCS_RX_MAP(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_2BYTE((_pEleStart)+4, 0, 16, _val)   /* B0~B15 indicate Rx MCS MAP, we write 0 to indicate MCS0~7. by page */\n#define SET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_2BYTE((_pEleStart)+6, 0, 13, _val)\n#define SET_VHT_CAPABILITY_ELE_MCS_TX_MAP(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_2BYTE((_pEleStart)+8, 0, 16, _val)   /* B0~B15 indicate Tx MCS MAP, we write 0 to indicate MCS0~7. by page */\n#define SET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(_pEleStart, _val)\t\t\t\tSET_BITS_TO_LE_2BYTE((_pEleStart)+10, 0, 13, _val)\n\n\n#define GET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(_pEleStart)\t\t\tLE_BITS_TO_1BYTE(_pEleStart, 0, 2)\n#define GET_VHT_CAPABILITY_ELE_CHL_WIDTH(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE(_pEleStart, 2, 2)\n#define GET_VHT_CAPABILITY_ELE_RX_LDPC(_pEleStart)\t\t\tLE_BITS_TO_1BYTE(_pEleStart, 4, 1)\n#define GET_VHT_CAPABILITY_ELE_SHORT_GI80M(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE(_pEleStart, 5, 1)\n#define GET_VHT_CAPABILITY_ELE_SHORT_GI160M(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE(_pEleStart, 6, 1)\n#define GET_VHT_CAPABILITY_ELE_TX_STBC(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE(_pEleStart, 7, 1)\n#define GET_VHT_CAPABILITY_ELE_RX_STBC(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE((_pEleStart)+1, 0, 3)\n#define GET_VHT_CAPABILITY_ELE_SU_BFER(_pEleStart)\t\t\t\t\tLE_BITS_TO_1BYTE((_pEleStart)+1, 3, 1)\n#define GET_VHT_CAPABILITY_ELE_SU_BFEE(_pEleStart)\t\t\t\t\tLE_BITS_TO_1BYTE((_pEleStart)+1, 4, 1)\n/*phydm-beamforming*/\n#define GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(_pEleStart)\tLE_BITS_TO_2BYTE((_pEleStart)+1, 5, 3)\n#define GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(_pEleStart)\tLE_BITS_TO_2BYTE((_pEleStart)+2, 0, 3)\n#define GET_VHT_CAPABILITY_ELE_MU_BFER(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE((_pEleStart)+2, 3, 1)\n#define GET_VHT_CAPABILITY_ELE_MU_BFEE(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE((_pEleStart)+2, 4, 1)\n#define GET_VHT_CAPABILITY_ELE_TXOP_PS(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE((_pEleStart)+2, 5, 1)\n#define GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(_pEleStart)\tLE_BITS_TO_2BYTE((_pEleStart)+2, 7, 3)\n#define GET_VHT_CAPABILITY_ELE_RX_MCS(_pEleStart)\t\t\t\t\t       ((_pEleStart)+4)\n#define GET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(_pEleStart)\t\t\tLE_BITS_TO_2BYTE((_pEleStart)+6, 0, 13)\n#define GET_VHT_CAPABILITY_ELE_TX_MCS(_pEleStart)\t\t\t\t\t       ((_pEleStart)+8)\n#define GET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(_pEleStart)\t\t\tLE_BITS_TO_2BYTE((_pEleStart)+10, 0, 13)\n\n\n/* VHT Operation Information Element */\n#define SET_VHT_OPERATION_ELE_CHL_WIDTH(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(_pEleStart, 0, 8, _val)\n#define SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(_pEleStart+1, 0, 8, _val)\n#define SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(_pEleStart+2, 0, 8, _val)\n#define SET_VHT_OPERATION_ELE_BASIC_MCS_SET(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_2BYTE((_pEleStart)+3, 0, 16, _val)\n\n#define GET_VHT_OPERATION_ELE_CHL_WIDTH(_pEleStart)\t\tLE_BITS_TO_1BYTE(_pEleStart, 0, 8)\n#define GET_VHT_OPERATION_ELE_CENTER_FREQ1(_pEleStart)\tLE_BITS_TO_1BYTE((_pEleStart)+1, 0, 8)\n#define GET_VHT_OPERATION_ELE_CENTER_FREQ2(_pEleStart)     LE_BITS_TO_1BYTE((_pEleStart)+2, 0, 8)\n\n/* VHT Operating Mode */\n#define SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(_pEleStart, _val)\t\tSET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val)\n#define SET_VHT_OPERATING_MODE_FIELD_RX_NSS(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE(_pEleStart, 4, 3, _val)\n#define SET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(_pEleStart, _val)\tSET_BITS_TO_LE_1BYTE(_pEleStart, 7, 1, _val)\n#define GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(_pEleStart)\t\t\tLE_BITS_TO_1BYTE(_pEleStart, 0, 2)\n#define GET_VHT_OPERATING_MODE_FIELD_RX_NSS(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE(_pEleStart, 4, 3)\n#define GET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(_pEleStart)\t\tLE_BITS_TO_1BYTE(_pEleStart, 7, 1)\n\n#define SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(_pEleStart, _val)\t\t\tSET_BITS_TO_LE_1BYTE((_pEleStart)+7, 6, 1, _val)\n#define GET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(_pEleStart)\t\t\t\tLE_BITS_TO_1BYTE((_pEleStart)+7, 6, 1)\n\n#define VHT_MAX_MPDU_LEN_MAX 3\nextern const u16 _vht_max_mpdu_len[];\n#define vht_max_mpdu_len(val) (((val) >= VHT_MAX_MPDU_LEN_MAX) ? _vht_max_mpdu_len[VHT_MAX_MPDU_LEN_MAX] : _vht_max_mpdu_len[(val)])\n\n#define VHT_SUP_CH_WIDTH_SET_MAX 3\nextern const u8 _vht_sup_ch_width_set_to_bw_cap[];\n#define vht_sup_ch_width_set_to_bw_cap(set) (((set) >= VHT_SUP_CH_WIDTH_SET_MAX) ? _vht_sup_ch_width_set_to_bw_cap[VHT_SUP_CH_WIDTH_SET_MAX] : _vht_sup_ch_width_set_to_bw_cap[(set)])\nextern const char *const _vht_sup_ch_width_set_str[];\n#define vht_sup_ch_width_set_str(set) (((set) >= VHT_SUP_CH_WIDTH_SET_MAX) ? _vht_sup_ch_width_set_str[VHT_SUP_CH_WIDTH_SET_MAX] : _vht_sup_ch_width_set_str[(set)])\n\n#define VHT_MAX_AMPDU_LEN(f) ((1 << (13 + f)) - 1)\nvoid dump_vht_cap_ie(void *sel, const u8 *ie, u32 ie_len);\n\n#define VHT_OP_CH_WIDTH_MAX 4\nextern const char *const _vht_op_ch_width_str[];\n#define vht_op_ch_width_str(ch_width) (((ch_width) >= VHT_OP_CH_WIDTH_MAX) ? _vht_op_ch_width_str[VHT_OP_CH_WIDTH_MAX] : _vht_op_ch_width_str[(ch_width)])\n\nvoid dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len);\n\nstruct vht_priv {\n\tu8\tvht_option;\n\n\tu8\tldpc_cap;\n\tu8\tstbc_cap;\n\tu16\tbeamform_cap;\n\tu8\tap_is_mu_bfer;\n\n\tu8\tsgi_80m;/* short GI */\n\tu8\tampdu_len;\n\n\tu8\tvht_highest_rate;\n\tu8\tvht_mcs_map[2];\n\n\tu8 op_present:1; /* vht_op is present */\n\tu8 notify_present:1; /* vht_op_mode_notify is present */\n\n\tu8 vht_cap[32];\n\tu8 vht_op[VHT_OP_IE_LEN];\n\tu8 vht_op_mode_notify;\n};\n\n#ifdef ROKU_PRIVATE\nstruct vht_priv_infra_ap {\n\n\t/* Infra mode, only store for AP's info, not intersection of STA and AP*/\n\tu8\tldpc_cap_infra_ap;\n\tu8\tstbc_cap_infra_ap;\n\tu16\tbeamform_cap_infra_ap;\n\tu8\tvht_mcs_map_infra_ap[2];\n\tu8\tvht_mcs_map_tx_infra_ap[2];\n\tu8\tchannel_width_infra_ap;\n\tu8\tnumber_of_streams_infra_ap;\n};\n#endif /* ROKU_PRIVATE */\n\nu8\trtw_get_vht_highest_rate(u8 *pvht_mcs_map);\nu16\trtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate);\nu64\trtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss);\nvoid\trtw_vht_use_default_setting(_adapter *padapter);\nu32\trtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel);\nu32\trtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw);\nu32\trtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf);\nvoid\tupdate_sta_vht_info_apmode(_adapter *padapter, void *psta);\nvoid\tupdate_hw_vht_param(_adapter *padapter);\nvoid\tVHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);\n#ifdef ROKU_PRIVATE\nvoid\tVHT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);\n#endif /* ROKU_PRIVATE */\nvoid\tVHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);\nvoid\trtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, void *sta);\nu32\trtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len);\nvoid\tVHTOnAssocRsp(_adapter *padapter);\nu8\trtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map);\nvoid rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map);\nvoid rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pcur_network);\nvoid rtw_vht_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pcur_network);\nvoid rtw_check_for_vht20(_adapter *adapter, u8 *ies, int ies_len);\n#endif /* _RTW_VHT_H_ */\n"
  },
  {
    "path": "include/rtw_wapi.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __INC_WAPI_H\n#define __INC_WAPI_H\n\n\n#define CONFIG_WAPI_SW_SMS4\n#define WAPI_DEBUG\n\n#define SMS4_MIC_LEN                16\n#define WAPI_EXT_LEN                18\n#define MAX_WAPI_IE_LEN\t\t    256\n#define sMacHdrLng\t\t\t\t24\t\t/* octets in data header, no WEP */\n\n#ifdef WAPI_DEBUG\n\n/* WAPI trace debug */\nextern u32 wapi_debug_component;\n\nstatic inline void dump_buf(u8 *buf, u32 len)\n{\n\tu32 i;\n\tprintk(\"-----------------Len %d----------------\\n\", len);\n\tfor (i = 0; i < len; i++)\n\t\tprintk(\"%2.2x-\", *(buf + i));\n\tprintk(\"\\n\");\n}\n\n#define WAPI_TRACE(component, x, args...) \\\n\tdo { if (wapi_debug_component & (component)) \\\n\t\t\tprintk(KERN_DEBUG \"WAPI\" \":\" x \"\" , \\\n\t\t\t       ##args);\\\n\t} while (0);\n\n#define WAPI_DATA(component, x, buf, len) \\\n\tdo { if (wapi_debug_component & (component)) { \\\n\t\t\tprintk(\"%s:\\n\", x);\\\n\t\t\tdump_buf((buf), (len)); } \\\n\t} while (0);\n\n#define RT_ASSERT_RET(_Exp)\t\t\t\t\t\t\t\t\\\n\tif (!(_Exp)) {\t\t\t\t\t\t\t\t\t\\\n\t\tprintk(\"RTWLAN: \");\t\t\t\t\t\\\n\t\tprintk(\"Assertion failed! %s,%s, line=%d\\n\", \\\n\t\t       #_Exp, __FUNCTION__, __LINE__);          \\\n\t\treturn;\t\t\t\t\t\t\\\n\t}\n#define RT_ASSERT_RET_VALUE(_Exp, Ret)\t\t\t\t\t\t\t\t\\\n\tif (!(_Exp)) {\t\t\t\t\t\t\t\t\t\\\n\t\tprintk(\"RTWLAN: \");\t\t\t\t\t\\\n\t\tprintk(\"Assertion failed! %s,%s, line=%d\\n\", \\\n\t\t       #_Exp, __FUNCTION__, __LINE__);          \\\n\t\treturn Ret;\t\t\t\t\t\t\\\n\t}\n\n#else\n#define RT_ASSERT_RET(_Exp) do {} while (0)\n#define RT_ASSERT_RET_VALUE(_Exp, Ret) do {} while (0)\n#define WAPI_TRACE(component, x, args...) do {} while (0)\n#define WAPI_DATA(component, x, buf, len) do {} while (0)\n#endif\n\n\nenum WAPI_DEBUG {\n\tWAPI_INIT\t\t\t\t= 1,\n\tWAPI_API\t\t\t\t= 1 << 1,\n\tWAPI_TX\t\t\t\t= 1 << 2,\n\tWAPI_RX\t\t\t\t= 1 << 3,\n\tWAPI_MLME\t\t\t\t= 1 << 4,\n\tWAPI_IOCTL\t\t\t\t= 1 << 5,\n\tWAPI_ERR\t\t\t= 1 << 31\n};\n\n#define\t\t\tWAPI_MAX_BKID_NUM\t\t\t\t4\n#define\t\t\tWAPI_MAX_STAINFO_NUM\t\t\t4\n#define\t\t\tWAPI_CAM_ENTRY_NUM\t\t\t14\t/* 28/2 = 14 */\n\ntypedef struct  _RT_WAPI_BKID {\n\tstruct list_head\tlist;\n\tu8\t\t\t\tbkid[16];\n} RT_WAPI_BKID, *PRT_WAPI_BKID;\n\ntypedef struct  _RT_WAPI_KEY {\n\tu8\t\t\tdataKey[16];\n\tu8\t\t\tmicKey[16];\n\tu8\t\t\tkeyId;\n\tbool\t\t\tbSet;\n\tbool             bTxEnable;\n} RT_WAPI_KEY, *PRT_WAPI_KEY;\n\ntypedef enum _RT_WAPI_PACKET_TYPE {\n\tWAPI_NONE = 0,\n\tWAPI_PREAUTHENTICATE = 1,\n\tWAPI_STAKEY_REQUEST = 2,\n\tWAPI_AUTHENTICATE_ACTIVE = 3,\n\tWAPI_ACCESS_AUTHENTICATE_REQUEST = 4,\n\tWAPI_ACCESS_AUTHENTICATE_RESPONSE = 5,\n\tWAPI_CERTIFICATE_AUTHENTICATE_REQUEST = 6,\n\tWAPI_CERTIFICATE_AUTHENTICATE_RESPONSE = 7,\n\tWAPI_USK_REQUEST = 8,\n\tWAPI_USK_RESPONSE = 9,\n\tWAPI_USK_CONFIRM = 10,\n\tWAPI_MSK_NOTIFICATION = 11,\n\tWAPI_MSK_RESPONSE = 12\n} RT_WAPI_PACKET_TYPE;\n\ntypedef struct\t_RT_WAPI_STA_INFO {\n\tstruct list_head\t\tlist;\n\tu8\t\t\t\t\tPeerMacAddr[6];\n\tRT_WAPI_KEY\t\t      wapiUsk;\n\tRT_WAPI_KEY\t\t      wapiUskUpdate;\n\tRT_WAPI_KEY\t\t      wapiMsk;\n\tRT_WAPI_KEY\t\t      wapiMskUpdate;\n\tu8\t\t\t\t\tlastRxUnicastPN[16];\n\tu8\t\t\t\t\tlastTxUnicastPN[16];\n\tu8\t\t\t\t\tlastRxMulticastPN[16];\n\tu8\t\t\t\t\tlastRxUnicastPNBEQueue[16];\n\tu8\t\t\t\t\tlastRxUnicastPNBKQueue[16];\n\tu8\t\t\t\t\tlastRxUnicastPNVIQueue[16];\n\tu8\t\t\t\t\tlastRxUnicastPNVOQueue[16];\n\tbool\t\t\t\t\tbSetkeyOk;\n\tbool\t\t\t\t\tbAuthenticateInProgress;\n\tbool\t\t\t\t\tbAuthenticatorInUpdata;\n} RT_WAPI_STA_INFO, *PRT_WAPI_STA_INFO;\n\n/* Added for HW wapi en/decryption */\ntypedef struct _RT_WAPI_CAM_ENTRY {\n\t/* RT_LIST_ENTRY\t\tlist; */\n\tu8\t\t\tIsUsed;\n\tu8\t\t\tentry_idx;/* for cam entry */\n\tu8\t\t\tkeyidx;\t/* 0 or 1,new or old key */\n\tu8\t\t\tPeerMacAddr[6];\n\tu8\t\t\ttype;\t/* should be 110,wapi */\n} RT_WAPI_CAM_ENTRY, *PRT_WAPI_CAM_ENTRY;\n\ntypedef struct _RT_WAPI_T {\n\t/* BKID */\n\tRT_WAPI_BKID\t\twapiBKID[WAPI_MAX_BKID_NUM];\n\tstruct list_head\t\twapiBKIDIdleList;\n\tstruct list_head\t\twapiBKIDStoreList;\n\t/* Key for Tx Multicast/Broadcast */\n\tRT_WAPI_KEY\t\t      wapiTxMsk;\n\n\t/* sec related */\n\tu8\t\t\t\tlastTxMulticastPN[16];\n\t/* STA list */\n\tRT_WAPI_STA_INFO\twapiSta[WAPI_MAX_STAINFO_NUM];\n\tstruct list_head\t\twapiSTAIdleList;\n\tstruct list_head\t\twapiSTAUsedList;\n\t/*  */\n\tbool\t\t\t\tbWapiEnable;\n\n\t/* store WAPI IE */\n\tu8\t\t\t\twapiIE[256];\n\tu8\t\t\t\twapiIELength;\n\tbool\t\t\t\tbWapiPSK;\n\t/* last sequece number for wai packet */\n\tu16\t\t\t\twapiSeqnumAndFragNum;\n\tint extra_prefix_len;\n\tint extra_postfix_len;\n\n\tRT_WAPI_CAM_ENTRY\twapiCamEntry[WAPI_CAM_ENTRY_NUM];\n} RT_WAPI_T, *PRT_WAPI_T;\n\ntypedef struct _WLAN_HEADER_WAPI_EXTENSION {\n\tu8      KeyIdx;\n\tu8      Reserved;\n\tu8      PN[16];\n} WLAN_HEADER_WAPI_EXTENSION, *PWLAN_HEADER_WAPI_EXTENSION;\n\nu32 WapiComparePN(u8 *PN1, u8 *PN2);\n\n\nvoid rtw_wapi_init(_adapter *padapter);\n\nvoid rtw_wapi_free(_adapter *padapter);\n\nvoid rtw_wapi_disable_tx(_adapter *padapter);\n\nu8 rtw_wapi_is_wai_packet(_adapter *padapter, u8 *pkt_data);\n\nvoid rtw_wapi_update_info(_adapter *padapter, union recv_frame *precv_frame);\n\nu8 rtw_wapi_check_for_drop(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_ops);\n\nvoid rtw_build_probe_resp_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib);\n\nvoid rtw_build_beacon_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib);\n\nvoid rtw_build_assoc_req_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib);\n\nvoid rtw_wapi_on_assoc_ok(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);\n\nvoid rtw_wapi_return_one_sta_info(_adapter *padapter, u8 *MacAddr);\n\nvoid rtw_wapi_return_all_sta_info(_adapter *padapter);\n\nvoid rtw_wapi_clear_cam_entry(_adapter *padapter, u8 *pMacAddr);\n\nvoid rtw_wapi_clear_all_cam_entry(_adapter *padapter);\n\nvoid rtw_wapi_set_key(_adapter *padapter, RT_WAPI_KEY *pWapiKey, RT_WAPI_STA_INFO *pWapiSta, u8 bGroupKey, u8 bUseDefaultKey);\n\nint rtw_wapi_create_event_send(_adapter *padapter, u8 EventId, u8 *MacAddr, u8 *Buff, u16 BufLen);\n\nu32\trtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe);\n\nu32\trtw_sms4_decrypt(_adapter *padapter, u8 *precvframe);\n\nvoid rtw_wapi_get_iv(_adapter *padapter, u8 *pRA, u8 *IV);\n\nu8 WapiIncreasePN(u8 *PN, u8 AddCount);\n\nbool rtw_wapi_drop_for_key_absent(_adapter *padapter, u8 *pRA);\n\nvoid rtw_wapi_set_set_encryption(_adapter *padapter, struct ieee_param *param);\n\n#endif\n"
  },
  {
    "path": "include/rtw_wifi_regd.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2009-2010 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef __RTW_WIFI_REGD_H__\n#define __RTW_WIFI_REGD_H__\n\nstruct country_code_to_enum_rd {\n\tu16 countrycode;\n\tconst char *iso_name;\n};\n\nenum country_code_type_t {\n\tCOUNTRY_CODE_USER = 0,\n\n\t/*add new channel plan above this line */\n\tCOUNTRY_CODE_MAX\n};\n\nvoid rtw_regd_apply_flags(struct wiphy *wiphy);\nint rtw_regd_init(struct wiphy *wiphy);\n\n#endif /* __RTW_WIFI_REGD_H__ */\n"
  },
  {
    "path": "include/rtw_xmit.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2019 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _RTW_XMIT_H_\n#define _RTW_XMIT_H_\n\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t#ifdef CONFIG_TX_AGGREGATION\n\t\t#ifdef CONFIG_RTL8822C\n\t\t\t#ifdef CONFIG_SDIO_TX_FORMAT_DUMMY_AUTO\n\t\t\t\t#define MAX_XMITBUF_SZ\t(51200)\n\t\t\t#else\n\t\t\t\t#define MAX_XMITBUF_SZ\t(32764)\n\t\t\t#endif\n\t\t#else\n\t\t\t#define MAX_XMITBUF_SZ\t(20480)\t/* 20k */\n\t\t#endif\n\t\t/* #define SDIO_TX_AGG_MAX\t5 */\n\t#else\n\t\t#define MAX_XMITBUF_SZ (1664)\n\t\t#define SDIO_TX_AGG_MAX\t1\n\t#endif\n\n\t#if defined CONFIG_SDIO_HCI\n\t\t#define NR_XMITBUFF\t(16)\n\t\t#define SDIO_TX_DIV_NUM (2)\n\t#endif\n\t#if defined(CONFIG_GSPI_HCI)\n\t\t#define NR_XMITBUFF\t(128)\n\t#endif\n\n#elif defined (CONFIG_USB_HCI)\n\n\t#ifdef CONFIG_USB_TX_AGGREGATION\n\t\t#if defined(CONFIG_PLATFORM_ARM_SUNxI) || defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) || defined(CONFIG_PLATFORM_ARM_SUN8I) || defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)\n\t\t\t#define MAX_XMITBUF_SZ (12288)  /* 12k 1536*8 */\n\t\t#elif defined (CONFIG_PLATFORM_MSTAR)\n\t\t\t#define MAX_XMITBUF_SZ\t7680\t/* 7.5k */\n\t\t#else\n\t\t\t#define MAX_XMITBUF_SZ\t(20480)\t/* 20k */\n\t\t#endif\n\t#else\n\t\t#define MAX_XMITBUF_SZ\t(2048)\n\t#endif\n\n\t#ifdef CONFIG_SINGLE_XMIT_BUF\n\t\t#define NR_XMITBUFF\t(1)\n\t#else\n\t\t#define NR_XMITBUFF\t(4)\n\t#endif /* CONFIG_SINGLE_XMIT_BUF */\n#elif defined (CONFIG_PCI_HCI)\n#ifdef CONFIG_TX_AMSDU\n\t#define MAX_XMITBUF_SZ\t(3500)\n#else\n\t#define MAX_XMITBUF_SZ\t(1664)\n#endif\n#if defined (CONFIG_PCI_TX_POLLING) && !defined (CONFIG_PCI_TX_POLLING_V2)\n\t#define NR_XMITBUFF\t(256)\n#else\n\t#define NR_XMITBUFF\t(128)\n#endif\n#endif\n\n\n#ifdef CONFIG_PCI_HCI\n\t#define XMITBUF_ALIGN_SZ 4\n#else\n\t#ifdef USB_XMITBUF_ALIGN_SZ\n\t\t#define XMITBUF_ALIGN_SZ (USB_XMITBUF_ALIGN_SZ)\n\t#else\n\t\t#define XMITBUF_ALIGN_SZ 512\n\t#endif\n#endif\n\n\n/* xmit extension buff defination */\n#define MAX_XMIT_EXTBUF_SZ\t(1536)\n\n#ifdef CONFIG_SINGLE_XMIT_BUF\n\t#define NR_XMIT_EXTBUFF\t(1)\n#else\n\t#define NR_XMIT_EXTBUFF\t(32)\n#endif\n\n#ifdef CONFIG_RTL8812A\n\t#define MAX_CMDBUF_SZ\t(512 * 18)\n#elif defined(CONFIG_RTL8723D) && defined(CONFIG_LPS_POFF)\n\t#define MAX_CMDBUF_SZ\t(128*70) /*(8960)*/\n#else\n\t#define MAX_CMDBUF_SZ\t(5120)\t/* (4096) */\n#endif\n\n#define MAX_BEACON_LEN\t512\n\n#define MAX_NUMBLKS\t\t(1)\n\n#define XMIT_VO_QUEUE (0)\n#define XMIT_VI_QUEUE (1)\n#define XMIT_BE_QUEUE (2)\n#define XMIT_BK_QUEUE (3)\n\n#define VO_QUEUE_INX\t\t0\n#define VI_QUEUE_INX\t\t1\n#define BE_QUEUE_INX\t\t2\n#define BK_QUEUE_INX\t\t3\n#define BCN_QUEUE_INX\t\t4\n#define MGT_QUEUE_INX\t\t5\n#define HIGH_QUEUE_INX\t\t6\n#define TXCMD_QUEUE_INX\t7\n\n#define HW_QUEUE_ENTRY\t8\n\n#ifdef CONFIG_PCI_HCI\n\t#ifdef CONFIG_TRX_BD_ARCH\n\t\t#define TX_BD_NUM\t\t\t(128+1)\t/* +1 result from ring buffer */\n\t#else\n\t\t#define TXDESC_NUM\t\t\t128\n\t#endif\n#endif\n\n#define WEP_IV(pattrib_iv, dot11txpn, keyidx)\\\n\tdo {\\\n\t\tdot11txpn.val = (dot11txpn.val == 0xffffff) ? 0 : (dot11txpn.val + 1);\\\n\t\tpattrib_iv[0] = dot11txpn._byte_.TSC0;\\\n\t\tpattrib_iv[1] = dot11txpn._byte_.TSC1;\\\n\t\tpattrib_iv[2] = dot11txpn._byte_.TSC2;\\\n\t\tpattrib_iv[3] = ((keyidx & 0x3)<<6);\\\n\t} while (0)\n\n\n#define TKIP_IV(pattrib_iv, dot11txpn, keyidx)\\\n\tdo {\\\n\t\tdot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\\\n\t\tpattrib_iv[0] = dot11txpn._byte_.TSC1;\\\n\t\tpattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\\\n\t\tpattrib_iv[2] = dot11txpn._byte_.TSC0;\\\n\t\tpattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\\\n\t\tpattrib_iv[4] = dot11txpn._byte_.TSC2;\\\n\t\tpattrib_iv[5] = dot11txpn._byte_.TSC3;\\\n\t\tpattrib_iv[6] = dot11txpn._byte_.TSC4;\\\n\t\tpattrib_iv[7] = dot11txpn._byte_.TSC5;\\\n\t} while (0)\n\n#define AES_IV(pattrib_iv, dot11txpn, keyidx)\\\n\tdo {\\\n\t\tdot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\\\n\t\tpattrib_iv[0] = dot11txpn._byte_.TSC0;\\\n\t\tpattrib_iv[1] = dot11txpn._byte_.TSC1;\\\n\t\tpattrib_iv[2] = 0;\\\n\t\tpattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\\\n\t\tpattrib_iv[4] = dot11txpn._byte_.TSC2;\\\n\t\tpattrib_iv[5] = dot11txpn._byte_.TSC3;\\\n\t\tpattrib_iv[6] = dot11txpn._byte_.TSC4;\\\n\t\tpattrib_iv[7] = dot11txpn._byte_.TSC5;\\\n\t} while (0)\n\n/* Check if AMPDU Tx is supported or not. If it is supported,\n* it need to check \"amsdu in ampdu\" is supported or not.\n* (ampdu_en, amsdu_ampdu_en) =\n* (0, x) : AMPDU is not enable, but AMSDU is valid to send.\n* (1, 0) : AMPDU is enable, AMSDU in AMPDU is not enable. So, AMSDU is not valid to send.\n* (1, 1) : AMPDU and AMSDU in AMPDU are enable. So, AMSDU is valid to send.\n*/\n#define IS_AMSDU_AMPDU_NOT_VALID(pattrib)\\\n\t ((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE))\n\n#define IS_AMSDU_AMPDU_VALID(pattrib)\\\n\t !((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE))\n\n#define HWXMIT_ENTRY\t4\n\n/* For Buffer Descriptor ring architecture */\n#if defined(BUF_DESC_ARCH) || defined(CONFIG_TRX_BD_ARCH)\n\t#if defined(CONFIG_RTL8192E)\n\t\t#define TX_BUFFER_SEG_NUM\t1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */\n\t#elif defined(CONFIG_RTL8814A)\n\t\t#define TX_BUFFER_SEG_NUM\t1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */\n\t#else\n\t\t#define TX_BUFFER_SEG_NUM\t1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */\n\t#endif\n#endif\n\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) ||\\\n\tdefined(CONFIG_RTL8723B) || defined(CONFIG_RTL8192E) ||\\\n\tdefined(CONFIG_RTL8814A) || defined(CONFIG_RTL8703B) ||\\\n\tdefined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) ||\\\n\tdefined(CONFIG_RTL8710B) || defined(CONFIG_RTL8192F)\n\t#define TXDESC_SIZE 40\n#elif defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)\n\t#define TXDESC_SIZE 48\t\t/* HALMAC_TX_DESC_SIZE_8822B */\n#elif defined(CONFIG_RTL8821C)\n\t#define TXDESC_SIZE 48\t\t/* HALMAC_TX_DESC_SIZE_8821C */\n#else\n\t#define TXDESC_SIZE 32 /* old IC (ex: 8188E) */\n#endif\n\n#ifdef CONFIG_TX_EARLY_MODE\n\t#define EARLY_MODE_INFO_SIZE\t8\n#endif\n\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t#define TXDESC_OFFSET TXDESC_SIZE\n#endif\n\n#ifdef CONFIG_USB_HCI\n\t#ifdef USB_PACKET_OFFSET_SZ\n\t\t#define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ)\n\t#else\n\t\t#define PACKET_OFFSET_SZ (8)\n\t#endif\n\t#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\t#if defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_TRX_BD_ARCH)\n\t\t/* this section is defined for buffer descriptor ring architecture */\n\t\t#define TX_WIFI_INFO_SIZE (TXDESC_SIZE) /* it may add 802.11 hdr or others... */\n\t\t/* tx desc and payload are in the same buf */\n\t\t#define TXDESC_OFFSET (TX_WIFI_INFO_SIZE)\n\t#else\n\t\t/* tx desc and payload are NOT in the same buf */\n\t\t#define TXDESC_OFFSET (0)\n\t\t/* 8188ee/8723be/8812ae/8821ae has extra PCI DMA info in tx desc */\n\t\t#define TX_DESC_NEXT_DESC_OFFSET\t(TXDESC_SIZE + 8)\n\t#endif\n#endif /* CONFIG_PCI_HCI */\n\nenum TXDESC_SC {\n\tSC_DONT_CARE = 0x00,\n\tSC_UPPER = 0x01,\n\tSC_LOWER = 0x02,\n\tSC_DUPLICATE = 0x03\n};\n\n#ifdef CONFIG_PCI_HCI\n\t#ifndef CONFIG_TRX_BD_ARCH\t/* CONFIG_TRX_BD_ARCH doesn't need this */\n\t\t#define TXDESC_64_BYTES\n\t#endif\n#elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8723B) \\\n\t|| defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) \\\n\t|| defined(CONFIG_RTL8192F)\n\t#define TXDESC_40_BYTES\n#endif\n\n#ifdef CONFIG_TRX_BD_ARCH\nstruct tx_buf_desc {\n#ifdef CONFIG_64BIT_DMA\n#define TX_BUFFER_SEG_SIZE\t4\t/* in unit of DWORD */\n#else\n#define TX_BUFFER_SEG_SIZE\t2\t/* in unit of DWORD */\n#endif\n\tunsigned int dword[TX_BUFFER_SEG_SIZE * (2 << TX_BUFFER_SEG_NUM)];\n} __packed;\n#elif (defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)) && defined(CONFIG_PCI_HCI) /* 8192ee or 8814ae */\n/* 8192EE_TODO */\nstruct tx_desc {\n\tunsigned int txdw0;\n\tunsigned int txdw1;\n\tunsigned int txdw2;\n\tunsigned int txdw3;\n\tunsigned int txdw4;\n\tunsigned int txdw5;\n\tunsigned int txdw6;\n\tunsigned int txdw7;\n};\n#else\nstruct tx_desc {\n\tunsigned int txdw0;\n\tunsigned int txdw1;\n\tunsigned int txdw2;\n\tunsigned int txdw3;\n\tunsigned int txdw4;\n\tunsigned int txdw5;\n\tunsigned int txdw6;\n\tunsigned int txdw7;\n\n#if defined(TXDESC_40_BYTES) || defined(TXDESC_64_BYTES)\n\tunsigned int txdw8;\n\tunsigned int txdw9;\n#endif /* TXDESC_40_BYTES */\n\n#ifdef TXDESC_64_BYTES\n\tunsigned int txdw10;\n\tunsigned int txdw11;\n\n\t/* 2008/05/15 MH Because PCIE HW memory R/W 4K limit. And now,  our descriptor */\n\t/* size is 40 bytes. If you use more than 102 descriptor( 103*40>4096), HW will execute */\n\t/* memoryR/W CRC error. And then all DMA fetch will fail. We must decrease descriptor */\n\t/* number or enlarge descriptor size as 64 bytes. */\n\tunsigned int txdw12;\n\tunsigned int txdw13;\n\tunsigned int txdw14;\n\tunsigned int txdw15;\n#endif\n};\n#endif\n\n#ifndef CONFIG_TRX_BD_ARCH\nunion txdesc {\n\tstruct tx_desc txdesc;\n\tunsigned int value[TXDESC_SIZE >> 2];\n};\n#endif\n\n#ifdef CONFIG_PCI_HCI\n#define PCI_MAX_TX_QUEUE_COUNT\t8\t/* == HW_QUEUE_ENTRY */\n\nstruct rtw_tx_ring {\n\tunsigned char\tqid;\n#ifdef CONFIG_TRX_BD_ARCH\n\tstruct tx_buf_desc\t*buf_desc;\n#else\n\tstruct tx_desc\t*desc;\n#endif\n\tdma_addr_t\tdma;\n\tunsigned int\tidx;\n\tunsigned int\tentries;\n\t_queue\t\tqueue;\n\tu32\t\tqlen;\n#ifdef CONFIG_TRX_BD_ARCH\n\tu16\t\thw_rp_cache;\n#endif\n};\n\n#ifdef DBG_TXBD_DESC_DUMP\n\n#define TX_BAK_FRMAE_CNT\t10\n#define TX_BAK_DESC_LEN\t48\t/* byte */\n#define TX_BAK_DATA_LEN\t\t30\t/* byte */\n\nstruct rtw_tx_desc_backup {\n\tint tx_bak_rp;\n\tint tx_bak_wp;\n\tu8 tx_bak_desc[TX_BAK_DESC_LEN];\n\tu8 tx_bak_data_hdr[TX_BAK_DATA_LEN];\n\tu8 tx_desc_size;\n};\n#endif\n#endif\n\nstruct\thw_xmit\t{\n\t/* _lock xmit_lock; */\n\t/* _list\tpending; */\n\t_queue *sta_queue;\n\t/* struct hw_txqueue *phwtxqueue; */\n\t/* sint\ttxcmdcnt; */\n\tint\taccnt;\n};\n\n#if 0\nstruct pkt_attrib {\n\tu8\ttype;\n\tu8\tsubtype;\n\tu8\tbswenc;\n\tu8\tdhcp_pkt;\n\tu16\tether_type;\n\tint\tpktlen;\t\t/* the original 802.3 pkt raw_data len (not include ether_hdr data) */\n\tint\tpkt_hdrlen;\t/* the original 802.3 pkt header len */\n\tint\thdrlen;\t\t/* the WLAN Header Len */\n\tint\tnr_frags;\n\tint\tlast_txcmdsz;\n\tint\tencrypt;\t/* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */\n\tu8\tiv[8];\n\tint\tiv_len;\n\tu8\ticv[8];\n\tint\ticv_len;\n\tint\tpriority;\n\tint\tack_policy;\n\tint\tmac_id;\n\tint\tvcs_mode;\t/* virtual carrier sense method */\n\n\tu8\tdst[ETH_ALEN];\n\tu8\tsrc[ETH_ALEN];\n\tu8\tta[ETH_ALEN];\n\tu8\tra[ETH_ALEN];\n\n\tu8\tkey_idx;\n\n\tu8\tqos_en;\n\tu8\tht_en;\n\tu8\traid;/* rate adpative id */\n\tu8\tbwmode;\n\tu8\tch_offset;/* PRIME_CHNL_OFFSET */\n\tu8\tsgi;/* short GI */\n\tu8\tampdu_en;/* tx ampdu enable */\n\tu8\tmdata;/* more data bit */\n\tu8\teosp;\n\n\tu8\ttriggered;/* for ap mode handling Power Saving sta */\n\n\tu32\tqsel;\n\tu16\tseqnum;\n\n\tstruct sta_info *psta;\n};\n#else\n/* reduce size */\nstruct pkt_attrib {\n\tu8\ttype;\n\tu8\tsubtype;\n\tu8\tbswenc;\n\tu8\tdhcp_pkt;\n\tu16\tether_type;\n\tu16\tseqnum;\n\tu8\thw_ssn_sel;\t/* for HW_SEQ0,1,2,3 */\n\tu16\tpkt_hdrlen;\t/* the original 802.3 pkt header len */\n\tu16\thdrlen;\t\t/* the WLAN Header Len */\n\tu32\tpktlen;\t\t/* the original 802.3 pkt raw_data len (not include ether_hdr data) */\n\tu32\tlast_txcmdsz;\n\tu8\tnr_frags;\n\tu8\tencrypt;\t/* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */\n#if defined(CONFIG_CONCURRENT_MODE)\n\tu8\tbmc_camid;\n#endif\n\tu8\tiv_len;\n\tu8\ticv_len;\n\tu8\tiv[18];\n\tu8\ticv[16];\n\tu8\tpriority;\n\tu8\tack_policy;\n\tu8\tmac_id;\n\tu8\tvcs_mode;\t/* virtual carrier sense method */\n\tu8\tdst[ETH_ALEN];\n\tu8\tsrc[ETH_ALEN];\n\tu8\tta[ETH_ALEN];\n\tu8\tra[ETH_ALEN];\n#ifdef CONFIG_RTW_MESH\n\tu8\tmda[ETH_ALEN];\t/* mesh da */\n\tu8\tmsa[ETH_ALEN];\t/* mesh sa */\n\tu8\tmeshctrl_len;\t/* Length of Mesh Control field */\n\tu8\tmesh_frame_mode;\n\t#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\tu8 mb2u;\n\t#endif\n\tu8 mfwd_ttl;\n\tu32 mseq;\n#endif\n#ifdef CONFIG_TX_CSUM_OFFLOAD\n\tu8\thw_csum;\n#endif\n\tu8\tkey_idx;\n\tu8\tqos_en;\n\tu8\tht_en;\n\tu8\traid;/* rate adpative id */\n\tu8\tbwmode;\n\tu8\tch_offset;/* PRIME_CHNL_OFFSET */\n\tu8\tsgi;/* short GI */\n\tu8\tampdu_en;/* tx ampdu enable */\n\tu8\tampdu_spacing; /* ampdu_min_spacing for peer sta's rx */\n\tu8\tamsdu;\n\tu8\tamsdu_ampdu_en;/* tx amsdu in ampdu enable */\n\tu8\tmdata;/* more data bit */\n\tu8\tpctrl;/* per packet txdesc control enable */\n\tu8\ttriggered;/* for ap mode handling Power Saving sta */\n\tu8\tqsel;\n\tu8\torder;/* order bit */\n\tu8\teosp;\n\tu8\trate;\n\tu8\tintel_proxim;\n\tu8\tretry_ctrl;\n\tu8   mbssid;\n\tu8\tldpc;\n\tu8\tstbc;\n#ifdef CONFIG_WMMPS_STA\n\tu8\ttrigger_frame;\n#endif /* CONFIG_WMMPS_STA */\n\t\n\tstruct sta_info *psta;\n\n\tu8 rtsen;\n\tu8 cts2self;\n\tunion Keytype\tdot11tkiptxmickey;\n\t/* union Keytype\tdot11tkiprxmickey; */\n\tunion Keytype\tdot118021x_UncstKey;\n\n#ifdef CONFIG_TDLS\n\tu8 direct_link;\n\tstruct sta_info *ptdls_sta;\n#endif /* CONFIG_TDLS */\n\tu8 key_type;\n\n\tu8 icmp_pkt;\n\n#ifdef CONFIG_BEAMFORMING\n\tu16 txbf_p_aid;/*beamforming Partial_AID*/\n\tu16 txbf_g_id;/*beamforming Group ID*/\n\n\t/*\n\t * 2'b00: Unicast NDPA\n\t * 2'b01: Broadcast NDPA\n\t * 2'b10: Beamforming Report Poll\n\t * 2'b11: Final Beamforming Report Poll\n\t */\n\tu8 bf_pkt_type;\n#endif\n\n};\n#endif\n\n#ifdef CONFIG_RTW_MESH\n#define XATTRIB_GET_MCTRL_LEN(xattrib) ((xattrib)->meshctrl_len)\n#else\n#define XATTRIB_GET_MCTRL_LEN(xattrib) 0\n#endif\n\n#ifdef CONFIG_TX_AMSDU\nenum {\n\tRTW_AMSDU_TIMER_UNSET = 0,\n\tRTW_AMSDU_TIMER_SETTING,\n\tRTW_AMSDU_TIMER_TIMEOUT,\n};\n#endif\n\n#define WLANHDR_OFFSET\t64\n\n#define NULL_FRAMETAG\t\t(0x0)\n#define DATA_FRAMETAG\t\t0x01\n#define L2_FRAMETAG\t\t0x02\n#define MGNT_FRAMETAG\t\t0x03\n#define AMSDU_FRAMETAG\t0x04\n\n#define EII_FRAMETAG\t\t0x05\n#define IEEE8023_FRAMETAG  0x06\n\n#define MP_FRAMETAG\t\t0x07\n\n#define TXAGG_FRAMETAG\t0x08\n\nenum {\n\tXMITBUF_DATA = 0,\n\tXMITBUF_MGNT = 1,\n\tXMITBUF_CMD = 2,\n};\n\nbool rtw_xmit_ac_blocked(_adapter *adapter);\n\nstruct  submit_ctx {\n\tsystime submit_time; /* */\n\tu32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */\n\tint status; /* status for operation */\n#ifdef PLATFORM_LINUX\n\tstruct completion done;\n#endif\n};\n\nenum {\n\tRTW_SCTX_SUBMITTED = -1,\n\tRTW_SCTX_DONE_SUCCESS = 0,\n\tRTW_SCTX_DONE_UNKNOWN,\n\tRTW_SCTX_DONE_TIMEOUT,\n\tRTW_SCTX_DONE_BUF_ALLOC,\n\tRTW_SCTX_DONE_BUF_FREE,\n\tRTW_SCTX_DONE_WRITE_PORT_ERR,\n\tRTW_SCTX_DONE_TX_DESC_NA,\n\tRTW_SCTX_DONE_TX_DENY,\n\tRTW_SCTX_DONE_CCX_PKT_FAIL,\n\tRTW_SCTX_DONE_DRV_STOP,\n\tRTW_SCTX_DONE_DEV_REMOVE,\n\tRTW_SCTX_DONE_CMD_ERROR,\n\tRTW_SCTX_DONE_CMD_DROP,\n\tRTX_SCTX_CSTR_WAIT_RPT2,\n};\n\n\nvoid rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms);\nint rtw_sctx_wait(struct submit_ctx *sctx, const char *msg);\nvoid rtw_sctx_done_err(struct submit_ctx **sctx, int status);\nvoid rtw_sctx_done(struct submit_ctx **sctx);\n\nstruct xmit_buf {\n\t_list\tlist;\n\n\t_adapter *padapter;\n\n\tu8 *pallocated_buf;\n\n\tu8 *pbuf;\n\n\tvoid *priv_data;\n\n\tu16 buf_tag; /* 0: Normal xmitbuf, 1: extension xmitbuf, 2:cmd xmitbuf */\n\tu16 flags;\n\tu32 alloc_sz;\n\n\tu32  len;\n\n\tstruct submit_ctx *sctx;\n\n#ifdef CONFIG_USB_HCI\n\n\t/* u32 sz[8]; */\n\tu32\tff_hwaddr;\n#ifdef RTW_HALMAC\n\tu8 bulkout_id; /* for halmac */\n#endif /* RTW_HALMAC */\n\n\tPURB\tpxmit_urb[8];\n\tdma_addr_t dma_transfer_addr;\t/* (in) dma addr for transfer_buffer */\n\n\tu8 bpending[8];\n\n\tsint last[8];\n\n#endif\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\tu8 *phead;\n\tu8 *pdata;\n\tu8 *ptail;\n\tu8 *pend;\n\tu32 ff_hwaddr;\n\tu8\tpg_num;\n\tu8\tagg_num;\n#endif\n\n#ifdef CONFIG_PCI_HCI\n#ifdef CONFIG_TRX_BD_ARCH\n\t/*struct tx_buf_desc *buf_desc;*/\n#else\n\tstruct tx_desc *desc;\n#endif\n#endif\n\n#if defined(DBG_XMIT_BUF) || defined(DBG_XMIT_BUF_EXT)\n\tu8 no;\n#endif\n\n};\n\n\nstruct xmit_frame {\n\t_list\tlist;\n\n\tstruct pkt_attrib attrib;\n\n\t_pkt *pkt;\n\n\tint\tframe_tag;\n\n\t_adapter *padapter;\n\n\tu8\t*buf_addr;\n\n\tstruct xmit_buf *pxmitbuf;\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\tu8\tpg_num;\n\tu8\tagg_num;\n#endif\n\n#ifdef CONFIG_USB_HCI\n#ifdef CONFIG_USB_TX_AGGREGATION\n\tu8\tagg_num;\n#endif\n\ts8\tpkt_offset;\n#endif\n\n#ifdef CONFIG_XMIT_ACK\n\tu8 ack_report;\n#endif\n\n\tu8 *alloc_addr; /* the actual address this xmitframe allocated */\n\tu8 ext_tag; /* 0:data, 1:mgmt */\n\n};\n\nstruct tx_servq {\n\t_list\ttx_pending;\n\t_queue\tsta_pending;\n\tint qcnt;\n};\n\n\nstruct sta_xmit_priv {\n\t_lock\tlock;\n\tsint\toption;\n\tsint\tapsd_setting;\t/* When bit mask is on, the associated edca queue supports APSD. */\n\n\n\t/* struct tx_servq blk_q[MAX_NUMBLKS]; */\n\tstruct tx_servq\tbe_q;\t\t\t/* priority == 0,3 */\n\tstruct tx_servq\tbk_q;\t\t\t/* priority == 1,2 */\n\tstruct tx_servq\tvi_q;\t\t\t/* priority == 4,5 */\n\tstruct tx_servq\tvo_q;\t\t\t/* priority == 6,7 */\n\t_list\tlegacy_dz;\n\t_list  apsd;\n\n\tu16 txseq_tid[16];\n\n\t/* uint\tsta_tx_bytes; */\n\t/* u64\tsta_tx_pkts; */\n\t/* uint\tsta_tx_fail; */\n\n\n};\n\n\nstruct\thw_txqueue\t{\n\tvolatile sint\thead;\n\tvolatile sint\ttail;\n\tvolatile sint \tfree_sz;\t/* in units of 64 bytes */\n\tvolatile sint      free_cmdsz;\n\tvolatile sint\t txsz[8];\n\tuint\tff_hwaddr;\n\tuint\tcmd_hwaddr;\n\tsint\tac_tag;\n};\n\nstruct agg_pkt_info {\n\tu16 offset;\n\tu16 pkt_len;\n};\n\nenum cmdbuf_type {\n\tCMDBUF_BEACON = 0x00,\n\tCMDBUF_RSVD,\n\tCMDBUF_MAX\n};\n\nu8 rtw_get_hwseq_no(_adapter *padapter);\n\nstruct\txmit_priv\t{\n\n\t_lock\tlock;\n\n\t_sema\txmit_sema;\n\n\t/* _queue\tblk_strms[MAX_NUMBLKS]; */\n\t_queue\tbe_pending;\n\t_queue\tbk_pending;\n\t_queue\tvi_pending;\n\t_queue\tvo_pending;\n\t_queue\tbm_pending;\n\n\t/* _queue\tlegacy_dz_queue; */\n\t/* _queue\tapsd_queue; */\n\n\tu8 *pallocated_frame_buf;\n\tu8 *pxmit_frame_buf;\n\tuint free_xmitframe_cnt;\n\t_queue\tfree_xmit_queue;\n\n\t/* uint mapping_addr; */\n\t/* uint pkt_sz; */\n\n\tu8 *xframe_ext_alloc_addr;\n\tu8 *xframe_ext;\n\tuint free_xframe_ext_cnt;\n\t_queue free_xframe_ext_queue;\n\n\t/* struct\thw_txqueue\tbe_txqueue; */\n\t/* struct\thw_txqueue\tbk_txqueue; */\n\t/* struct\thw_txqueue\tvi_txqueue; */\n\t/* struct\thw_txqueue\tvo_txqueue; */\n\t/* struct\thw_txqueue\tbmc_txqueue; */\n\n\tuint\tfrag_len;\n\n\t_adapter\t*adapter;\n\n\tu8   vcs_setting;\n\tu8\tvcs;\n\tu8\tvcs_type;\n\t/* u16  rts_thresh; */\n\n\tu64\ttx_bytes;\n\tu64\ttx_pkts;\n\tu64\ttx_drop;\n\tu64\tlast_tx_pkts;\n\n\tstruct hw_xmit *hwxmits;\n\tu8\thwxmit_entry;\n\n\tu8\twmm_para_seq[4];/* sequence for wmm ac parameter strength from large to small. it's value is 0->vo, 1->vi, 2->be, 3->bk. */\n\n#ifdef CONFIG_USB_HCI\n\t_sema\ttx_retevt;/* all tx return event; */\n\tu8\t\ttxirp_cnt;\n\n\t_tasklet xmit_tasklet;\n\n\t/* per AC pending irp */\n\tint beq_cnt;\n\tint bkq_cnt;\n\tint viq_cnt;\n\tint voq_cnt;\n\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\t/* Tx */\n\tstruct rtw_tx_ring\ttx_ring[PCI_MAX_TX_QUEUE_COUNT];\n\tint\ttxringcount[PCI_MAX_TX_QUEUE_COUNT];\n\tu8 \tbeaconDMAing;\t\t/* flag of indicating beacon is transmiting to HW by DMA */\n\t_tasklet xmit_tasklet;\n#endif\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n#ifdef CONFIG_SDIO_TX_TASKLET\n\t_tasklet xmit_tasklet;\n#else\n\t_thread_hdl_\tSdioXmitThread;\n\t_sema\t\tSdioXmitSema;\n#endif /* CONFIG_SDIO_TX_TASKLET */\n#endif /* CONFIG_SDIO_HCI */\n\n\t_queue free_xmitbuf_queue;\n\t_queue pending_xmitbuf_queue;\n\tu8 *pallocated_xmitbuf;\n\tu8 *pxmitbuf;\n\tuint free_xmitbuf_cnt;\n\n\t_queue free_xmit_extbuf_queue;\n\tu8 *pallocated_xmit_extbuf;\n\tu8 *pxmit_extbuf;\n\tuint free_xmit_extbuf_cnt;\n\n\tstruct xmit_buf\tpcmd_xmitbuf[CMDBUF_MAX];\n\tu8   hw_ssn_seq_no;/* mapping to REG_HW_SEQ 0,1,2,3 */\n\tu16\tnqos_ssn;\n#ifdef CONFIG_TX_EARLY_MODE\n\n#ifdef CONFIG_SDIO_HCI\n#define MAX_AGG_PKT_NUM 20\n#else\n#define MAX_AGG_PKT_NUM 256 /* Max tx ampdu coounts\t\t */\n#endif\n\n\tstruct agg_pkt_info agg_pkt[MAX_AGG_PKT_NUM];\n#endif\n\n#ifdef CONFIG_XMIT_ACK\n\tint\tack_tx;\n\t_mutex ack_tx_mutex;\n\tstruct submit_ctx ack_tx_ops;\n\tu8 seq_no;\n#endif\n\n#ifdef CONFIG_TX_AMSDU\n\t_timer amsdu_vo_timer;\n\tu8 amsdu_vo_timeout;\n\n\t_timer amsdu_vi_timer;\n\tu8 amsdu_vi_timeout;\n\n\t_timer amsdu_be_timer;\n\tu8 amsdu_be_timeout;\n\n\t_timer amsdu_bk_timer;\n\tu8 amsdu_bk_timeout;\n\n\tu32 amsdu_debug_set_timer;\n\tu32 amsdu_debug_timeout;\n\tu32 amsdu_debug_coalesce_one;\n\tu32 amsdu_debug_coalesce_two;\n\n#endif\n#ifdef DBG_TXBD_DESC_DUMP\n\tBOOLEAN\t dump_txbd_desc;\n#endif\n#ifdef CONFIG_PCI_TX_POLLING\n\t_timer tx_poll_timer;\n#endif\n\t_lock lock_sctx;\n\n};\n\nextern struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv,\n\t\tenum cmdbuf_type buf_type);\n#define rtw_alloc_cmdxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_RSVD)\n#if defined(CONFIG_RTL8192E) && defined(CONFIG_PCI_HCI)\nextern struct xmit_frame *__rtw_alloc_cmdxmitframe_8192ee(struct xmit_priv *pxmitpriv,\n\t\tenum cmdbuf_type buf_type);\n#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8192ee(p, CMDBUF_BEACON)\n#elif defined(CONFIG_RTL8822B) && defined(CONFIG_PCI_HCI)\nextern struct xmit_frame *__rtw_alloc_cmdxmitframe_8822be(struct xmit_priv *pxmitpriv,\n\t\tenum cmdbuf_type buf_type);\n#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8822be(p, CMDBUF_BEACON)\n#elif defined(CONFIG_RTL8822C) && defined(CONFIG_PCI_HCI)\nextern struct xmit_frame *__rtw_alloc_cmdxmitframe_8822ce(struct xmit_priv *pxmitpriv,\n\t\tenum cmdbuf_type buf_type);\n#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8822ce(p, CMDBUF_BEACON)\n#elif defined(CONFIG_RTL8821C) && defined(CONFIG_PCI_HCI)\nextern struct xmit_frame *__rtw_alloc_cmdxmitframe_8821ce(struct xmit_priv *pxmitpriv,\n\t\tenum cmdbuf_type buf_type);\n#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8821ce(p, CMDBUF_BEACON)\n#elif defined(CONFIG_RTL8192F) && defined(CONFIG_PCI_HCI)\nextern struct xmit_frame *__rtw_alloc_cmdxmitframe_8192fe(struct xmit_priv *pxmitpriv,\n\t\tenum cmdbuf_type buf_type);\n#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8192fe(p, CMDBUF_BEACON)\n#elif defined(CONFIG_RTL8812A) && defined(CONFIG_PCI_HCI)\nextern struct xmit_frame *__rtw_alloc_cmdxmitframe_8812ae(struct xmit_priv *pxmitpriv,\n\t\tenum cmdbuf_type buf_type);\n#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8812ae(p, CMDBUF_BEACON)\n#elif defined(CONFIG_RTL8723D) && defined(CONFIG_PCI_HCI)\nextern struct xmit_frame *__rtw_alloc_cmdxmitframe_8723de(struct xmit_priv *pxmitpriv,\n\t\tenum cmdbuf_type buf_type);\n#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8723de(p, CMDBUF_BEACON)\n#elif defined(CONFIG_RTL8723B) && defined(CONFIG_PCI_HCI)\nextern struct xmit_frame *__rtw_alloc_cmdxmitframe_8723be(struct xmit_priv *pxmitpriv,\n\t\tenum cmdbuf_type buf_type);\n#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8723be(p, CMDBUF_BEACON)\n#elif defined(CONFIG_RTL8814A) && defined(CONFIG_PCI_HCI)\nextern struct xmit_frame *__rtw_alloc_cmdxmitframe_8814ae(struct xmit_priv *pxmitpriv,\n\t\tenum cmdbuf_type buf_type);\n#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8814ae(p, CMDBUF_BEACON)\n#else\n#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_BEACON)\n#endif\n\nextern struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv);\nextern s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\n\nextern struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv);\nextern s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\n\nvoid rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz);\nextern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len);\n\nextern s32 rtw_make_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib);\nextern s32 rtw_put_snap(u8 *data, u16 h_proto);\n\nextern struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv);\nstruct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv);\nstruct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv);\nextern s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe);\nextern void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue);\nstruct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac);\nextern s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);\nextern struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry);\n\nextern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe);\nextern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib);\n#define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue(&f->attrib)\nextern s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe);\n#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)\nextern s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe);\n#endif\n#ifdef CONFIG_TDLS\nextern struct tdls_txmgmt *ptxmgmt;\ns32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt);\ns32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib);\n#endif\ns32 _rtw_init_hw_txqueue(struct hw_txqueue *phw_txqueue, u8 ac_tag);\nvoid _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv);\n\n\ns32 rtw_txframes_pending(_adapter *padapter);\ns32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib);\nvoid rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry);\n\n\ns32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter);\nvoid _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv);\n\n\nvoid rtw_alloc_hwxmits(_adapter *padapter);\nvoid rtw_free_hwxmits(_adapter *padapter);\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))\ns32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev);\n#endif\nvoid rtw_xmit_dequeue_callback(_workitem *work);\nvoid rtw_xmit_queue_set(struct sta_info *sta);\nvoid rtw_xmit_queue_clear(struct sta_info *sta);\ns32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, _pkt *pkt);\ns32 rtw_xmit(_adapter *padapter, _pkt **pkt);\nbool xmitframe_hiq_filter(struct xmit_frame *xmitframe);\n#if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS)\nsint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe);\nvoid stop_sta_xmit(_adapter *padapter, struct sta_info *psta);\nvoid wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta);\nvoid xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta);\n#endif\n\nu8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta);\n\nvoid rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u32 *r_bmp_vht);\nvoid rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj);\nu16 rtw_get_tx_rate_bmp_cck_ofdm(struct dvobj_priv *dvobj);\nu32 rtw_get_tx_rate_bmp_ht_by_bw(struct dvobj_priv *dvobj, u8 bw);\nu32 rtw_get_tx_rate_bmp_vht_by_bw(struct dvobj_priv *dvobj, u8 bw);\nu8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw);\nu8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw);\n\nu8 query_ra_short_GI(struct sta_info *psta, u8 bw);\n\nu8\tqos_acm(u8 acm_mask, u8 priority);\n\n#ifdef CONFIG_XMIT_THREAD_MODE\nvoid\tenqueue_pending_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\nvoid enqueue_pending_xmitbuf_to_head(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);\nstruct xmit_buf\t*dequeue_pending_xmitbuf(struct xmit_priv *pxmitpriv);\nstruct xmit_buf\t*select_and_dequeue_pending_xmitbuf(_adapter *padapter);\nsint\tcheck_pending_xmitbuf(struct xmit_priv *pxmitpriv);\nthread_return\trtw_xmit_thread(thread_context context);\n#endif\n\n#ifdef CONFIG_TX_AMSDU\nextern void rtw_amsdu_vo_timeout_handler(void *FunctionContext);\nextern void rtw_amsdu_vi_timeout_handler(void *FunctionContext);\nextern void rtw_amsdu_be_timeout_handler(void *FunctionContext);\nextern void rtw_amsdu_bk_timeout_handler(void *FunctionContext);\n\nextern u8 rtw_amsdu_get_timer_status(_adapter *padapter, u8 priority);\nextern void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status);\nextern void rtw_amsdu_set_timer(_adapter *padapter, u8 priority);\nextern void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority);\n\nextern s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue);\t\nextern s32 check_amsdu(struct xmit_frame *pxmitframe);\nextern s32 check_amsdu_tx_support(_adapter *padapter);\nextern struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame);\n#endif\n\n#ifdef DBG_TXBD_DESC_DUMP\nvoid rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 desc_size, u8 hwq);\nvoid rtw_tx_desc_backup_reset(void);\nu8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup **pbak);\n#endif\n\n#ifdef CONFIG_PCI_TX_POLLING\nvoid rtw_tx_poll_init(_adapter *padapter);\nvoid rtw_tx_poll_timeout_handler(void *FunctionContext);\nvoid rtw_tx_poll_timer_set(_adapter *padapter, u32 delay);\nvoid rtw_tx_poll_timer_cancel(_adapter *padapter);\n#endif\n\nu32\trtw_get_ff_hwaddr(struct xmit_frame\t*pxmitframe);\n\n#ifdef CONFIG_XMIT_ACK\nint rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms);\nvoid rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status);\n#endif /* CONFIG_XMIT_ACK */\n\nenum XMIT_BLOCK_REASON {\n\tXMIT_BLOCK_NONE = 0,\n\tXMIT_BLOCK_REDLMEM = BIT0, /*LPS-PG*/\n\tXMIT_BLOCK_SUSPEND = BIT1, /*WOW*/\n\tXMIT_BLOCK_MAX = 0xFF,\n};\nvoid rtw_init_xmit_block(_adapter *padapter);\nvoid rtw_deinit_xmit_block(_adapter *padapter);\n\n#ifdef DBG_XMIT_BLOCK\nvoid dump_xmit_block(void *sel, _adapter *padapter);\n#endif\nvoid rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason);\nvoid rtw_clr_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason);\nbool rtw_is_xmit_blocked(_adapter *padapter);\n\n/* include after declaring struct xmit_buf, in order to avoid warning */\n#include <xmit_osdep.h>\n\n#endif /* _RTL871X_XMIT_H_ */\n"
  },
  {
    "path": "include/sdio_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __SDIO_HAL_H__\n#define __SDIO_HAL_H__\n\nvoid sd_int_dpc(PADAPTER padapter);\nu8 rtw_set_hal_ops(_adapter *padapter);\n\n#ifdef CONFIG_RTL8188E\nvoid rtl8188es_set_hal_ops(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_RTL8723B\nvoid rtl8723bs_set_hal_ops(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_RTL8821A\nvoid rtl8821as_set_hal_ops(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_RTL8192E\nvoid rtl8192es_set_hal_ops(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_RTL8703B\nvoid rtl8703bs_set_hal_ops(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_RTL8723D\nvoid rtl8723ds_set_hal_ops(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_RTL8188F\nvoid rtl8188fs_set_hal_ops(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_RTL8188GTV\nvoid rtl8188gtvs_set_hal_ops(PADAPTER padapter);\n#endif\n\n#ifdef CONFIG_RTL8192F\nvoid rtl8192fs_set_hal_ops(PADAPTER padapter);\n#endif\n\n#endif /* __SDIO_HAL_H__ */\n"
  },
  {
    "path": "include/sdio_ops.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __SDIO_OPS_H__\n#define __SDIO_OPS_H__\n\n\n/* Follow mac team suggestion, default I/O fail return value is 0xFF */\n#define SDIO_ERR_VAL8\t0xFF\n#define SDIO_ERR_VAL16\t0xFFFF\n#define SDIO_ERR_VAL32\t0xFFFFFFFF\n\n#ifdef PLATFORM_LINUX\n#include <sdio_ops_linux.h>\n#endif\n\nextern void sdio_set_intf_ops(_adapter *padapter, struct _io_ops *pops);\nvoid dump_sdio_card_info(void *sel, struct dvobj_priv *dvobj);\n\nu32 sdio_init(struct dvobj_priv *dvobj);\nvoid sdio_deinit(struct dvobj_priv *dvobj);\nint sdio_alloc_irq(struct dvobj_priv *dvobj);\nvoid sdio_free_irq(struct dvobj_priv *dvobj);\nu8 sdio_get_num_of_func(struct dvobj_priv *dvobj);\n\n#if 0\nextern void sdio_func1cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem);\nextern void sdio_func1cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem);\n#endif\nextern u8 SdioLocalCmd52Read1Byte(PADAPTER padapter, u32 addr);\nextern void SdioLocalCmd52Write1Byte(PADAPTER padapter, u32 addr, u8 v);\nextern s32 _sdio_local_read(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf);\nextern s32 sdio_local_read(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf);\nextern s32 _sdio_local_write(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf);\nextern s32 sdio_local_write(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf);\n\nu32 _sdio_read32(PADAPTER padapter, u32 addr);\ns32 _sdio_write32(PADAPTER padapter, u32 addr, u32 val);\n\nextern void sd_int_hdl(PADAPTER padapter);\nextern u8 CheckIPSStatus(PADAPTER padapter);\n\n#ifdef CONFIG_RTL8188E\nextern void InitInterrupt8188ESdio(PADAPTER padapter);\nextern void EnableInterrupt8188ESdio(PADAPTER padapter);\nextern void DisableInterrupt8188ESdio(PADAPTER padapter);\nextern void UpdateInterruptMask8188ESdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);\nextern u8 HalQueryTxBufferStatus8189ESdio(PADAPTER padapter);\nextern u8 HalQueryTxOQTBufferStatus8189ESdio(PADAPTER padapter);\nextern void ClearInterrupt8188ESdio(PADAPTER padapter);\n#endif /* CONFIG_RTL8188E */\n\n#ifdef CONFIG_RTL8821A\nextern void InitInterrupt8821AS(PADAPTER padapter);\nextern void EnableInterrupt8821AS(PADAPTER padapter);\nextern void DisableInterrupt8821AS(PADAPTER padapter);\nextern u8 HalQueryTxBufferStatus8821AS(PADAPTER padapter);\nextern u8 HalQueryTxOQTBufferStatus8821ASdio(PADAPTER padapter);\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\nvoid ClearInterrupt8821AS(PADAPTER padapter);\n#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */\n#endif /* CONFIG_RTL8821A */\n\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\n#if defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)\nu8 rtw_hal_enable_cpwm2(_adapter *adapter);\n#endif\nextern u8 RecvOnePkt(PADAPTER padapter);\n#endif /* CONFIG_WOWLAN */\n#ifdef CONFIG_RTL8723B\nextern void InitInterrupt8723BSdio(PADAPTER padapter);\nextern void InitSysInterrupt8723BSdio(PADAPTER padapter);\nextern void EnableInterrupt8723BSdio(PADAPTER padapter);\nextern void DisableInterrupt8723BSdio(PADAPTER padapter);\nextern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter);\nextern u8 HalQueryTxOQTBufferStatus8723BSdio(PADAPTER padapter);\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\nextern void DisableInterruptButCpwm28723BSdio(PADAPTER padapter);\nextern void ClearInterrupt8723BSdio(PADAPTER padapter);\n#endif /* CONFIG_WOWLAN */\n#endif\n\n\n#ifdef CONFIG_RTL8192E\nextern void InitInterrupt8192ESdio(PADAPTER padapter);\nextern void EnableInterrupt8192ESdio(PADAPTER padapter);\nextern void DisableInterrupt8192ESdio(PADAPTER padapter);\nextern void UpdateInterruptMask8192ESdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);\nextern u8 HalQueryTxBufferStatus8192ESdio(PADAPTER padapter);\nextern u8 HalQueryTxOQTBufferStatus8192ESdio(PADAPTER padapter);\nextern void ClearInterrupt8192ESdio(PADAPTER padapter);\n#endif /* CONFIG_RTL8192E */\n\n#ifdef CONFIG_RTL8703B\nextern void InitInterrupt8703BSdio(PADAPTER padapter);\nextern void InitSysInterrupt8703BSdio(PADAPTER padapter);\nextern void EnableInterrupt8703BSdio(PADAPTER padapter);\nextern void DisableInterrupt8703BSdio(PADAPTER padapter);\nextern u8 HalQueryTxBufferStatus8703BSdio(PADAPTER padapter);\nextern u8 HalQueryTxOQTBufferStatus8703BSdio(PADAPTER padapter);\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\nextern void DisableInterruptButCpwm28703BSdio(PADAPTER padapter);\nextern void ClearInterrupt8703BSdio(PADAPTER padapter);\n#endif /* CONFIG_WOWLAN */\n#endif\n\n#ifdef CONFIG_RTL8723D\nextern void InitInterrupt8723DSdio(PADAPTER padapter);\nextern void InitSysInterrupt8723DSdio(PADAPTER padapter);\nextern void EnableInterrupt8723DSdio(PADAPTER padapter);\nextern void DisableInterrupt8723DSdio(PADAPTER padapter);\nextern u8 HalQueryTxBufferStatus8723DSdio(PADAPTER padapter);\nextern u8 HalQueryTxOQTBufferStatus8723DSdio(PADAPTER padapter);\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\nextern void DisableInterruptButCpwm28723dSdio(PADAPTER padapter);\nextern void ClearInterrupt8723DSdio(PADAPTER padapter);\n#endif /* CONFIG_WOWLAN */\n#endif\n\n#ifdef CONFIG_RTL8192F\nextern void InitInterrupt8192FSdio(PADAPTER padapter);\nextern void InitSysInterrupt8192FSdio(PADAPTER padapter);\nextern void EnableInterrupt8192FSdio(PADAPTER padapter);\nextern void DisableInterrupt8192FSdio(PADAPTER padapter);\nextern void UpdateInterruptMask8192FSdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);\nextern u8 HalQueryTxBufferStatus8192FSdio(PADAPTER padapter);\nextern u8 HalQueryTxOQTBufferStatus8192FSdio(PADAPTER padapter);\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\nextern void DisableInterruptButCpwm2192fSdio(PADAPTER padapter);\nextern void ClearInterrupt8192FSdio(PADAPTER padapter);\n#endif /* CONFIG_WOWLAN */\n#endif\n\n#ifdef CONFIG_RTL8188F\nextern void InitInterrupt8188FSdio(PADAPTER padapter);\nextern void InitSysInterrupt8188FSdio(PADAPTER padapter);\nextern void EnableInterrupt8188FSdio(PADAPTER padapter);\nextern void DisableInterrupt8188FSdio(PADAPTER padapter);\nextern u8 HalQueryTxBufferStatus8188FSdio(PADAPTER padapter);\nextern u8 HalQueryTxOQTBufferStatus8188FSdio(PADAPTER padapter);\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\nextern void DisableInterruptButCpwm28188FSdio(PADAPTER padapter);\nextern void ClearInterrupt8188FSdio(PADAPTER padapter);\n#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */\n#endif\n\n#ifdef CONFIG_RTL8188GTV\nextern void InitInterrupt8188GTVSdio(PADAPTER padapter);\nextern void InitSysInterrupt8188GTVSdio(PADAPTER padapter);\nextern void EnableInterrupt8188GTVSdio(PADAPTER padapter);\nextern void DisableInterrupt8188GTVSdio(PADAPTER padapter);\nextern u8 HalQueryTxBufferStatus8188GTVSdio(PADAPTER padapter);\nextern u8 HalQueryTxOQTBufferStatus8188GTVSdio(PADAPTER padapter);\n#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)\nextern void DisableInterruptButCpwm28188GTVSdio(PADAPTER padapter);\nextern void ClearInterrupt8188GTVSdio(PADAPTER padapter);\n#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */\n#endif\n\n/**\n * rtw_sdio_get_block_size() - Get block size of SDIO transfer\n * @d\t\tstruct dvobj_priv*\n *\n * The unit of return value is byte.\n */\nstatic inline u32 rtw_sdio_get_block_size(struct dvobj_priv *d)\n{\n\treturn d->intf_data.block_transfer_len;\n}\n\n/**\n * rtw_sdio_cmd53_align_size() - Align size to one CMD53 could complete\n * @d\t\tstruct dvobj_priv*\n * @len\t\tlength to align\n *\n * Adjust len to align block size, and the new size could be transfered by one\n * CMD53.\n * If len < block size, it would keep original value, otherwise the value\n * would be rounded up by block size.\n *\n * Return adjusted length.\n */\nstatic inline size_t rtw_sdio_cmd53_align_size(struct dvobj_priv *d, size_t len)\n{\n\tu32 blk_sz;\n\n\n\tblk_sz = rtw_sdio_get_block_size(d);\n\tif (len <= blk_sz)\n\t\treturn len;\n\n\treturn _RND(len, blk_sz);\n}\n\n#endif /* !__SDIO_OPS_H__ */\n"
  },
  {
    "path": "include/sdio_ops_ce.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _SDIO_OPS_WINCE_H_\n#define _SDIO_OPS_WINCE_H_\n\n#include <drv_conf.h>\n#include <osdep_service.h>\n#include <drv_types.h>\n#include <osdep_intf.h>\n\n\n#ifdef PLATFORM_OS_CE\n\n\nextern u8 sdbus_cmd52r_ce(struct intf_priv *pintfpriv, u32 addr);\n\n\nextern void sdbus_cmd52w_ce(struct intf_priv *pintfpriv, u32 addr, u8 val8);\n\n\nuint sdbus_read_blocks_to_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);\n\nextern uint sdbus_read_bytes_to_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);\n\n\nextern uint sdbus_write_blocks_from_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf, u8 async);\n\nextern uint sdbus_write_bytes_from_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);\nextern u8 sdbus_func1cmd52r_ce(struct intf_priv *pintfpriv, u32 addr);\nextern void sdbus_func1cmd52w_ce(struct intf_priv *pintfpriv, u32 addr, u8 val8);\nextern uint sdbus_read_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata);\nextern uint sdbus_write_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata);\nextern void sdio_read_int(_adapter *padapter, u32 addr, u8 sz, void *pdata);\n\n#endif\n\n#endif\n"
  },
  {
    "path": "include/sdio_ops_linux.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __SDIO_OPS_LINUX_H__\n#define __SDIO_OPS_LINUX_H__\n\n#ifndef RTW_HALMAC\nu8 sd_f0_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err);\nvoid sd_f0_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err);\n\ns32 _sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata);\ns32 _sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata);\ns32 sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata);\ns32 sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata);\n\nu8 _sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err);\nu8 sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err);\nu16 sd_read16(struct intf_hdl *pintfhdl, u32 addr, s32 *err);\nu32 _sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err);\nu32 sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err);\nvoid sd_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err);\nvoid sd_write16(struct intf_hdl *pintfhdl, u32 addr, u16 v, s32 *err);\nvoid _sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err);\nvoid sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err);\n#endif /* RTW_HALMAC */\n\nbool rtw_is_sdio30(_adapter *adapter);\n\n/* The unit of return value is Hz */\nstatic inline u32 rtw_sdio_get_clock(struct dvobj_priv *d)\n{\n\treturn d->intf_data.clock;\n}\n\ns32 _sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata);\ns32 sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata);\ns32 _sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata);\ns32 sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata);\n\nvoid rtw_sdio_set_irq_thd(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl);\nint __must_check rtw_sdio_raw_read(struct dvobj_priv *d, unsigned int addr,\n\t\t\t\tvoid *buf, size_t len, bool fixed);\nint __must_check rtw_sdio_raw_write(struct dvobj_priv *d, unsigned int addr,\n\t\t\t\tvoid *buf, size_t len, bool fixed);\n\n#endif /* __SDIO_OPS_LINUX_H__ */\n\n"
  },
  {
    "path": "include/sdio_ops_xp.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _SDIO_OPS_XP_H_\n#define _SDIO_OPS_XP_H_\n\n#include <drv_conf.h>\n#include <osdep_service.h>\n#include <drv_types.h>\n#include <osdep_intf.h>\n\n\n#ifdef PLATFORM_OS_XP\n\n\nextern u8 sdbus_cmd52r_xp(struct intf_priv *pintfpriv, u32 addr);\n\n\nextern void sdbus_cmd52w_xp(struct intf_priv *pintfpriv, u32 addr, u8 val8);\n\n\nuint sdbus_read_blocks_to_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);\n\nextern uint sdbus_read_bytes_to_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);\n\n\nextern uint sdbus_write_blocks_from_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf, u8 async);\n\nextern uint sdbus_write_bytes_from_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);\nextern u8 sdbus_func1cmd52r_xp(struct intf_priv *pintfpriv, u32 addr);\nextern void sdbus_func1cmd52w_xp(struct intf_priv *pintfpriv, u32 addr, u8 val8);\nextern uint sdbus_read_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata);\nextern uint sdbus_write_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata);\nextern void sdio_read_int(_adapter *padapter, u32 addr, u8 sz, void *pdata);\n\n#endif\n\n#endif\n"
  },
  {
    "path": "include/sdio_osintf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __SDIO_OSINTF_H__\n#define __SDIO_OSINTF_H__\n\n\n#endif\n"
  },
  {
    "path": "include/sta_info.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2019 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __STA_INFO_H_\n#define __STA_INFO_H_\n\n#include <cmn_info/rtw_sta_info.h>\n\n#define IBSS_START_MAC_ID\t2\n#define NUM_STA MACID_NUM_SW_LIMIT\n\n#ifndef CONFIG_RTW_MACADDR_ACL\n\t#define CONFIG_RTW_MACADDR_ACL 1\n#endif\n\n#ifndef CONFIG_RTW_PRE_LINK_STA\n\t#define CONFIG_RTW_PRE_LINK_STA 0\n#endif\n\n#define NUM_ACL 16\n\n#define RTW_ACL_PERIOD_DEV 0\n#define RTW_ACL_PERIOD_BSS 1\n#define RTW_ACL_PERIOD_NUM 2\n\n#define RTW_ACL_MODE_DISABLED\t\t\t\t0\n#define RTW_ACL_MODE_ACCEPT_UNLESS_LISTED\t1\n#define RTW_ACL_MODE_DENY_UNLESS_LISTED\t\t2\n#define RTW_ACL_MODE_MAX\t\t\t\t\t3\n\n#if CONFIG_RTW_MACADDR_ACL\nextern const char *const _acl_period_str[RTW_ACL_PERIOD_NUM];\n#define acl_period_str(mode) (((mode) >= RTW_ACL_PERIOD_NUM) ? \"INVALID\" : _acl_period_str[(mode)])\nextern const char *const _acl_mode_str[RTW_ACL_MODE_MAX];\n#define acl_mode_str(mode) (((mode) >= RTW_ACL_MODE_MAX) ? \"INVALID\" : _acl_mode_str[(mode)])\n#endif\n\n#ifndef RTW_PRE_LINK_STA_NUM\n\t#define RTW_PRE_LINK_STA_NUM 8\n#endif\n\nstruct pre_link_sta_node_t {\n\tu8 valid;\n\tu8 addr[ETH_ALEN];\n};\n\nstruct pre_link_sta_ctl_t {\n\t_lock lock;\n\tu8 num;\n\tstruct pre_link_sta_node_t node[RTW_PRE_LINK_STA_NUM];\n};\n\n#ifdef CONFIG_TDLS\n#define MAX_ALLOWED_TDLS_STA_NUM\t4\n#endif\n\nenum sta_info_update_type {\n\tSTA_INFO_UPDATE_NONE = 0,\n\tSTA_INFO_UPDATE_BW = BIT(0),\n\tSTA_INFO_UPDATE_RATE = BIT(1),\n\tSTA_INFO_UPDATE_PROTECTION_MODE = BIT(2),\n\tSTA_INFO_UPDATE_CAP = BIT(3),\n\tSTA_INFO_UPDATE_HT_CAP = BIT(4),\n\tSTA_INFO_UPDATE_VHT_CAP = BIT(5),\n\tSTA_INFO_UPDATE_ALL = STA_INFO_UPDATE_BW\n\t\t\t      | STA_INFO_UPDATE_RATE\n\t\t\t      | STA_INFO_UPDATE_PROTECTION_MODE\n\t\t\t      | STA_INFO_UPDATE_CAP\n\t\t\t      | STA_INFO_UPDATE_HT_CAP\n\t\t\t      | STA_INFO_UPDATE_VHT_CAP,\n\tSTA_INFO_UPDATE_MAX\n};\n\nstruct rtw_wlan_acl_node {\n\t_list\t\t        list;\n\tu8       addr[ETH_ALEN];\n\tu8       valid;\n};\n\nstruct wlan_acl_pool {\n\tint mode;\n\tint num;\n\tstruct rtw_wlan_acl_node aclnode[NUM_ACL];\n\t_queue\tacl_node_q;\n};\n\nstruct\tstainfo_stats\t{\n\tsystime last_rx_time;\n\n\tu64 rx_mgnt_pkts;\n\tu64 rx_beacon_pkts;\n\tu64 rx_probereq_pkts;\n\tu64 rx_probersp_pkts; /* unicast to self */\n\tu64 rx_probersp_bm_pkts;\n\tu64 rx_probersp_uo_pkts; /* unicast to others */\n\tu64 rx_ctrl_pkts;\n\tu64 rx_data_pkts;\n\tu64 rx_data_bc_pkts;\n\tu64 rx_data_mc_pkts;\n\tu64 rx_data_qos_pkts[TID_NUM]; /* unicast only */\n\n\tu64\tlast_rx_mgnt_pkts;\n\tu64 last_rx_beacon_pkts;\n\tu64 last_rx_probereq_pkts;\n\tu64 last_rx_probersp_pkts; /* unicast to self */\n\tu64 last_rx_probersp_bm_pkts;\n\tu64 last_rx_probersp_uo_pkts; /* unicast to others */\n\tu64\tlast_rx_ctrl_pkts;\n\tu64\tlast_rx_data_pkts;\n\tu64 last_rx_data_bc_pkts;\n\tu64 last_rx_data_mc_pkts;\n\tu64 last_rx_data_qos_pkts[TID_NUM]; /* unicast only */\n\n#ifdef CONFIG_TDLS\n\tu64 rx_tdls_disc_rsp_pkts;\n\tu64 last_rx_tdls_disc_rsp_pkts;\n#endif\n\n\tu64\trx_bytes;\n\tu64\trx_bc_bytes;\n\tu64\trx_mc_bytes;\n\tu64\tlast_rx_bytes;\n\tu64 last_rx_bc_bytes;\n\tu64 last_rx_mc_bytes;\n\tu64\trx_drops; /* TBD */\n\tu32 rx_tp_kbits;\n\tu32 smooth_rx_tp_kbits;\n\n\tu64\ttx_pkts;\n\tu64\tlast_tx_pkts;\n\n\tu64\ttx_bytes;\n\tu64\tlast_tx_bytes;\n\tu64 tx_drops; /* TBD */\n\tu32 tx_tp_kbits;\n\tu32 smooth_tx_tp_kbits;\n\n#ifdef CONFIG_LPS_CHK_BY_TP\n\tu64 acc_tx_bytes;\n\tu64 acc_rx_bytes;\n#endif\n\n\t/* unicast only */\n\tu64 last_rx_data_uc_pkts; /* For Read & Clear requirement in proc_get_rx_stat() */\n\tu32 duplicate_cnt;\t/* Read & Clear, in proc_get_rx_stat() */\n\tu32 rxratecnt[128];\t/* Read & Clear, in proc_get_rx_stat() */\n\tu32 tx_ok_cnt;\t\t/* Read & Clear, in proc_get_tx_stat() */\n\tu32 tx_fail_cnt;\t/* Read & Clear, in proc_get_tx_stat() */\n\tu32 tx_retry_cnt;\t/* Read & Clear, in proc_get_tx_stat() */\n#ifdef CONFIG_RTW_MESH\n\tu32 rx_hwmp_pkts;\n\tu32 last_rx_hwmp_pkts;\n#endif\n};\n\n#ifndef DBG_SESSION_TRACKER\n#define DBG_SESSION_TRACKER 0\n#endif\n\n/* session tracker status */\n#define ST_STATUS_NONE\t\t0\n#define ST_STATUS_CHECK\t\tBIT0\n#define ST_STATUS_ESTABLISH\tBIT1\n#define ST_STATUS_EXPIRE\tBIT2\n\n#define ST_EXPIRE_MS (10 * 1000)\n\nstruct session_tracker {\n\t_list list; /* session_tracker_queue */\n\tu32 local_naddr;\n\tu16 local_port;\n\tu32 remote_naddr;\n\tu16 remote_port;\n\tsystime set_time;\n\tu8 status;\n};\n\n/* session tracker cmd */\n#define ST_CMD_ADD 0\n#define ST_CMD_DEL 1\n#define ST_CMD_CHK 2\n\nstruct st_cmd_parm {\n\tu8 cmd;\n\tstruct sta_info *sta;\n\tu32 local_naddr; /* TODO: IPV6 */\n\tu16 local_port;\n\tu32 remote_naddr; /* TODO: IPV6 */\n\tu16 remote_port;\n};\n\ntypedef bool (*st_match_rule)(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);\n\nstruct st_register {\n\tu8 s_proto;\n\tst_match_rule rule;\n};\n\n#define SESSION_TRACKER_REG_ID_WFD 0\n#define SESSION_TRACKER_REG_ID_NUM 1\n\nstruct st_ctl_t {\n\tstruct st_register reg[SESSION_TRACKER_REG_ID_NUM];\n\t_queue tracker_q;\n};\n\nvoid rtw_st_ctl_init(struct st_ctl_t *st_ctl);\nvoid rtw_st_ctl_deinit(struct st_ctl_t *st_ctl);\nvoid rtw_st_ctl_register(struct st_ctl_t *st_ctl, u8 st_reg_id, struct st_register *reg);\nvoid rtw_st_ctl_unregister(struct st_ctl_t *st_ctl, u8 st_reg_id);\nbool rtw_st_ctl_chk_reg_s_proto(struct st_ctl_t *st_ctl, u8 s_proto);\nbool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);\nvoid rtw_st_ctl_rx(struct sta_info *sta, u8 *ehdr_pos);\nvoid dump_st_ctl(void *sel, struct st_ctl_t *st_ctl);\n\n#ifdef CONFIG_TDLS\nstruct TDLS_PeerKey {\n\tu8 kck[16]; /* TPK-KCK */\n\tu8 tk[16]; /* TPK-TK; only CCMP will be used */\n} ;\n#endif /* CONFIG_TDLS */\n\n#ifdef DBG_RX_DFRAME_RAW_DATA\nstruct sta_recv_dframe_info {\n\n\tu8 sta_data_rate;\n\tu8 sta_sgi;\n\tu8 sta_bw_mode;\n\ts8 sta_mimo_signal_strength[4];\n\ts8 sta_RxPwr[4];\n\tu8 sta_ofdm_snr[4];\n};\n#endif\n\n#ifdef CONFIG_RTW_MESH\nstruct mesh_plink_ent;\nstruct rtw_ewma_err_rate {\n\tunsigned long internal;\n};\n\n/* Mesh airtime link metrics parameters */\nstruct rtw_atlm_param {\n\tstruct rtw_ewma_err_rate err_rate; /* Now is PACKET error rate */\n\tu16 data_rate; /* The unit is 100Kbps */\n\tu16 total_pkt;\n\tu16 overhead; /* Channel access overhead */\n};\n#endif\n\nstruct sta_info {\n\n\t_lock\tlock;\n\t_list\tlist; /* free_sta_queue */\n\t_list\thash_list; /* sta_hash */\n\t/* _list asoc_list; */ /* 20061114 */\n\t/* _list sleep_list; */ /* sleep_q */\n\t/* _list wakeup_list; */ /* wakeup_q */\n\t_adapter *padapter;\n\tstruct cmn_sta_info cmn;\n\n\tstruct sta_xmit_priv sta_xmitpriv;\n\tstruct sta_recv_priv sta_recvpriv;\n\n#ifdef DBG_RX_DFRAME_RAW_DATA\n\tstruct sta_recv_dframe_info  sta_dframe_info;\n\tstruct sta_recv_dframe_info  sta_dframe_info_bmc;\n#endif\n\t_queue sleep_q;\n\tunsigned int sleepq_len;\n\n\tuint state;\n\tuint qos_option;\n\tu16 hwseq;\n\n#ifdef CONFIG_RTW_80211K\n\tu8 rm_en_cap[5];\n\tu8 rm_diag_token;\n#endif /* CONFIG_RTW_80211K */\n\n\tuint\tieee8021x_blocked;\t/* 0: allowed, 1:blocked */\n\tuint\tdot118021XPrivacy; /* aes, tkip... */\n\tunion Keytype\tdot11tkiptxmickey;\n\tunion Keytype\tdot11tkiprxmickey;\n\tunion Keytype\tdot118021x_UncstKey;\n\tunion pn48\t\tdot11txpn;\t\t\t/* PN48 used for Unicast xmit */\n\tunion pn48\t\tdot11rxpn;\t\t\t/* PN48 used for Unicast recv. */\n#ifdef CONFIG_RTW_MESH\n\t/* peer's GTK, RX only */\n\tu8 group_privacy;\n\tu8 gtk_bmp;\n\tunion Keytype gtk;\n\tunion pn48 gtk_pn;\n\t#ifdef CONFIG_IEEE80211W\n\t/* peer's IGTK, RX only */\n\tu8 igtk_bmp;\n\tu8 igtk_id;\n\tunion Keytype igtk;\n\tunion pn48 igtk_pn;\n\t#endif /* CONFIG_IEEE80211W */\n#endif /* CONFIG_RTW_MESH */\n#ifdef CONFIG_GTK_OL\n\tu8 kek[RTW_KEK_LEN];\n\tu8 kck[RTW_KCK_LEN];\n\tu8 replay_ctr[RTW_REPLAY_CTR_LEN];\n#endif /* CONFIG_GTK_OL */\n#ifdef CONFIG_IEEE80211W\n\t_timer dot11w_expire_timer;\n#endif /* CONFIG_IEEE80211W */\n\n\tu8\tbssrateset[16];\n\tu32\tbssratelen;\n\n\tu8\tcts2self;\n\tu8\trtsen;\n\n\tu8\tinit_rate;\n\tu8\twireless_mode;\t/* NETWORK_TYPE */\n\n\tstruct stainfo_stats sta_stats;\n\n#ifdef CONFIG_TDLS\n\tu32\ttdls_sta_state;\n\tu8\tSNonce[32];\n\tu8\tANonce[32];\n\tu32\tTDLS_PeerKey_Lifetime;\n\tu32\tTPK_count;\n\t_timer\tTPK_timer;\n\tstruct TDLS_PeerKey\ttpk;\n#ifdef CONFIG_TDLS_CH_SW\n\tu16\tch_switch_time;\n\tu16\tch_switch_timeout;\n\t/* u8\toption; */\n\t_timer\tch_sw_timer;\n\t_timer\tdelay_timer;\n\t_timer\tstay_on_base_chnl_timer;\n\t_timer\tch_sw_monitor_timer;\n#endif\n\t_timer handshake_timer;\n\tu8 alive_count;\n\t_timer\tpti_timer;\n\tu8\tTDLS_RSNIE[20];\t/* Save peer's RSNIE, used for sending TDLS_SETUP_RSP */\n#endif /* CONFIG_TDLS */\n\n\t/* for A-MPDU TX, ADDBA timeout check\t */\n\t_timer addba_retry_timer;\n\n\t/* for A-MPDU Rx reordering buffer control */\n\tstruct recv_reorder_ctrl recvreorder_ctrl[TID_NUM];\n\tATOMIC_T continual_no_rx_packet[TID_NUM];\n\t/* for A-MPDU Tx */\n\t/* unsigned char\t\tampdu_txen_bitmap; */\n\tu16\tBA_starting_seqctrl[16];\n\n\n#ifdef CONFIG_80211N_HT\n\tstruct ht_priv\thtpriv;\n#endif\n\n#ifdef CONFIG_80211AC_VHT\n\tstruct vht_priv\tvhtpriv;\n#endif\n\n\t/* Notes:\t */\n\t/* STA_Mode: */\n\t/* curr_network(mlme_priv/security_priv/qos/ht) + sta_info: (STA & AP) CAP/INFO\t */\n\t/* scan_q: AP CAP/INFO */\n\n\t/* AP_Mode: */\n\t/* curr_network(mlme_priv/security_priv/qos/ht) : AP CAP/INFO */\n\t/* sta_info: (AP & STA) CAP/INFO */\n\n\tunsigned int expire_to;\n\n#ifdef CONFIG_AP_MODE\n\n\t_list asoc_list;\n\t_list auth_list;\n\n\tunsigned int auth_seq;\n\tunsigned int authalg;\n\tunsigned char chg_txt[128];\n\n\tu16 capability;\n\tint flags;\n\n\tint dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */\n\tint wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */\n\tint wpa_group_cipher;\n\tint wpa2_group_cipher;\n\tint wpa_pairwise_cipher;\n\tint wpa2_pairwise_cipher;\n\n\tu32 akm_suite_type;\n\n\tu8 bpairwise_key_installed;\n#ifdef CONFIG_RTW_80211R\n\tu8 ft_pairwise_key_installed;\n#endif\n\n#ifdef CONFIG_NATIVEAP_MLME\n\tu8 wpa_ie[32];\n\n\tu8 nonerp_set;\n\tu8 no_short_slot_time_set;\n\tu8 no_short_preamble_set;\n\tu8 no_ht_gf_set;\n\tu8 no_ht_set;\n\tu8 ht_20mhz_set;\n\tu8 ht_40mhz_intolerant;\n#endif /* CONFIG_NATIVEAP_MLME */\n\n#ifdef CONFIG_ATMEL_RC_PATCH\n\tu8 flag_atmel_rc;\n#endif\n\n\tu8 qos_info;\n\n\tu8 max_sp_len;\n\tu8 uapsd_bk;/* BIT(0): Delivery enabled, BIT(1): Trigger enabled */\n\tu8 uapsd_be;\n\tu8 uapsd_vi;\n\tu8 uapsd_vo;\n\n\tu8 has_legacy_ac;\n\tunsigned int sleepq_ac_len;\n\n#ifdef CONFIG_P2P\n\t/* p2p priv data */\n\tu8 is_p2p_device;\n\tu8 p2p_status_code;\n\n\t/* p2p client info */\n\tu8 dev_addr[ETH_ALEN];\n\t/* u8 iface_addr[ETH_ALEN]; */ /* = hwaddr[ETH_ALEN] */\n\tu8 dev_cap;\n\tu16 config_methods;\n\tu8 primary_dev_type[8];\n\tu8 num_of_secdev_type;\n\tu8 secdev_types_list[32];/* 32/8 == 4; */\n\tu16 dev_name_len;\n\tu8 dev_name[32];\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_WFD\n\tu8 op_wfd_mode;\n#endif\n\n#ifdef CONFIG_TX_MCAST2UNI\n\tu8 under_exist_checking;\n#endif /* CONFIG_TX_MCAST2UNI */\n\n\tu8 keep_alive_trycnt;\n\n#ifdef CONFIG_AUTO_AP_MODE\n\tu8 isrc; /* this device is rc */\n\tu16 pid; /* pairing id */\n#endif\n\n#endif /* CONFIG_AP_MODE\t */\n\n#ifdef CONFIG_RTW_MESH\n\tstruct mesh_plink_ent *plink;\n\n\tu8 local_mps;\n\tu8 peer_mps;\n\tu8 nonpeer_mps;\n\n\tstruct rtw_atlm_param metrics;\n\t/* The reference for nexthop_lookup */\n\tBOOLEAN alive;\n#endif\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tu8 *pauth_frame;\n\tu32 auth_len;\n\tu8 *passoc_req;\n\tu32 assoc_req_len;\n#endif\n\n\tu8\t\tIOTPeer;\t\t\t/* Enum value.\tHT_IOT_PEER_E */\n#ifdef CONFIG_LPS_PG\n\tu8\t\tlps_pg_rssi_lv;\n#endif\n\n\t/* To store the sequence number of received management frame */\n\tu16 RxMgmtFrameSeqNum;\n\n\tstruct st_ctl_t st_ctl;\n\tu8 max_agg_num_minimal_record; /*keep minimal tx desc max_agg_num setting*/\n\tu8 curr_rx_rate;\n\tu8 curr_rx_rate_bmc;\n#ifdef CONFIG_RTS_FULL_BW\n\tbool vendor_8812;\n#endif\n\n\t/*\n\t * Vaiables for queuing TX pkt a short period of time\n\t * to wait something ready.\n\t */\n\tu8 tx_q_enable;\n\tstruct __queue tx_queue;\n\t_workitem tx_q_work;\n};\n\n#ifdef CONFIG_RTW_MESH\n#define STA_SET_MESH_PLINK(sta, link) (sta)->plink = link\n#else\n#define STA_SET_MESH_PLINK(sta, link) do {} while (0)\n#endif\n\n#define sta_tx_pkts(sta) \\\n\t(sta->sta_stats.tx_pkts)\n\n#define sta_last_tx_pkts(sta) \\\n\t(sta->sta_stats.last_tx_pkts)\n\n#define sta_rx_pkts(sta) \\\n\t(sta->sta_stats.rx_mgnt_pkts \\\n\t + sta->sta_stats.rx_ctrl_pkts \\\n\t + sta->sta_stats.rx_data_pkts)\n\n#define sta_last_rx_pkts(sta) \\\n\t(sta->sta_stats.last_rx_mgnt_pkts \\\n\t + sta->sta_stats.last_rx_ctrl_pkts \\\n\t + sta->sta_stats.last_rx_data_pkts)\n\n#define sta_rx_data_pkts(sta) (sta->sta_stats.rx_data_pkts)\n#define sta_last_rx_data_pkts(sta) (sta->sta_stats.last_rx_data_pkts)\n\n#define sta_rx_data_uc_pkts(sta) (sta->sta_stats.rx_data_pkts - sta->sta_stats.rx_data_bc_pkts - sta->sta_stats.rx_data_mc_pkts)\n#define sta_last_rx_data_uc_pkts(sta) (sta->sta_stats.last_rx_data_pkts - sta->sta_stats.last_rx_data_bc_pkts - sta->sta_stats.last_rx_data_mc_pkts)\n\n#define sta_rx_data_qos_pkts(sta, i) \\\n\t(sta->sta_stats.rx_data_qos_pkts[i])\n\n#define sta_last_rx_data_qos_pkts(sta, i) \\\n\t(sta->sta_stats.last_rx_data_qos_pkts[i])\n\n#define sta_rx_mgnt_pkts(sta) \\\n\t(sta->sta_stats.rx_mgnt_pkts)\n\n#define sta_last_rx_mgnt_pkts(sta) \\\n\t(sta->sta_stats.last_rx_mgnt_pkts)\n\n#define sta_rx_beacon_pkts(sta) \\\n\t(sta->sta_stats.rx_beacon_pkts)\n\n#define sta_last_rx_beacon_pkts(sta) \\\n\t(sta->sta_stats.last_rx_beacon_pkts)\n\n#define sta_rx_probereq_pkts(sta) \\\n\t(sta->sta_stats.rx_probereq_pkts)\n\n#define sta_last_rx_probereq_pkts(sta) \\\n\t(sta->sta_stats.last_rx_probereq_pkts)\n\n#define sta_rx_probersp_pkts(sta) \\\n\t(sta->sta_stats.rx_probersp_pkts)\n\n#define sta_last_rx_probersp_pkts(sta) \\\n\t(sta->sta_stats.last_rx_probersp_pkts)\n\n#define sta_rx_probersp_bm_pkts(sta) \\\n\t(sta->sta_stats.rx_probersp_bm_pkts)\n\n#define sta_last_rx_probersp_bm_pkts(sta) \\\n\t(sta->sta_stats.last_rx_probersp_bm_pkts)\n\n#define sta_rx_probersp_uo_pkts(sta) \\\n\t(sta->sta_stats.rx_probersp_uo_pkts)\n\n#define sta_last_rx_probersp_uo_pkts(sta) \\\n\t(sta->sta_stats.last_rx_probersp_uo_pkts)\n\n#ifdef CONFIG_RTW_MESH\n#define update_last_rx_hwmp_pkts(sta) \\\n\tdo { \\\n\t\tsta->sta_stats.last_rx_hwmp_pkts = sta->sta_stats.rx_hwmp_pkts; \\\n\t} while(0)\n#else\n#define update_last_rx_hwmp_pkts(sta) do {} while(0)\n#endif\n\n#define sta_update_last_rx_pkts(sta) \\\n\tdo { \\\n\t\tint __i; \\\n\t\t\\\n\t\tsta->sta_stats.last_rx_mgnt_pkts = sta->sta_stats.rx_mgnt_pkts; \\\n\t\tsta->sta_stats.last_rx_beacon_pkts = sta->sta_stats.rx_beacon_pkts; \\\n\t\tsta->sta_stats.last_rx_probereq_pkts = sta->sta_stats.rx_probereq_pkts; \\\n\t\tsta->sta_stats.last_rx_probersp_pkts = sta->sta_stats.rx_probersp_pkts; \\\n\t\tsta->sta_stats.last_rx_probersp_bm_pkts = sta->sta_stats.rx_probersp_bm_pkts; \\\n\t\tsta->sta_stats.last_rx_probersp_uo_pkts = sta->sta_stats.rx_probersp_uo_pkts; \\\n\t\tsta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \\\n\t\tupdate_last_rx_hwmp_pkts(sta); \\\n\t\t\\\n\t\tsta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \\\n\t\tsta->sta_stats.last_rx_data_bc_pkts = sta->sta_stats.rx_data_bc_pkts; \\\n\t\tsta->sta_stats.last_rx_data_mc_pkts = sta->sta_stats.rx_data_mc_pkts; \\\n\t\tfor (__i = 0; __i < TID_NUM; __i++) \\\n\t\t\tsta->sta_stats.last_rx_data_qos_pkts[__i] = sta->sta_stats.rx_data_qos_pkts[__i]; \\\n\t} while (0)\n\n#define STA_RX_PKTS_ARG(sta) \\\n\tsta->sta_stats.rx_mgnt_pkts \\\n\t, sta->sta_stats.rx_ctrl_pkts \\\n\t, sta->sta_stats.rx_data_pkts\n\n#define STA_LAST_RX_PKTS_ARG(sta) \\\n\tsta->sta_stats.last_rx_mgnt_pkts \\\n\t, sta->sta_stats.last_rx_ctrl_pkts \\\n\t, sta->sta_stats.last_rx_data_pkts\n\n#define STA_RX_PKTS_DIFF_ARG(sta) \\\n\tsta->sta_stats.rx_mgnt_pkts - sta->sta_stats.last_rx_mgnt_pkts \\\n\t, sta->sta_stats.rx_ctrl_pkts - sta->sta_stats.last_rx_ctrl_pkts \\\n\t, sta->sta_stats.rx_data_pkts - sta->sta_stats.last_rx_data_pkts\n\n#define STA_PKTS_FMT \"(m:%llu, c:%llu, d:%llu)\"\n\n#define sta_rx_uc_bytes(sta) (sta->sta_stats.rx_bytes - sta->sta_stats.rx_bc_bytes - sta->sta_stats.rx_mc_bytes)\n#define sta_last_rx_uc_bytes(sta) (sta->sta_stats.last_rx_bytes - sta->sta_stats.last_rx_bc_bytes - sta->sta_stats.last_rx_mc_bytes)\n\n#ifdef CONFIG_WFD\n#define STA_OP_WFD_MODE(sta) (sta)->op_wfd_mode\n#define STA_SET_OP_WFD_MODE(sta, mode) (sta)->op_wfd_mode = (mode)\n#else\n#define STA_OP_WFD_MODE(sta) 0\n#define STA_SET_OP_WFD_MODE(sta, mode) do {} while (0)\n#endif\n\n#define AID_BMP_LEN(max_aid) ((max_aid + 1) / 8 + (((max_aid + 1) % 8) ? 1 : 0))\n\nstruct\tsta_priv {\n\n\tu8 *pallocated_stainfo_buf;\n\tu8 *pstainfo_buf;\n\t_queue\tfree_sta_queue;\n\n\t_lock sta_hash_lock;\n\t_list   sta_hash[NUM_STA];\n\tint asoc_sta_count;\n\t_queue sleep_q;\n\t_queue wakeup_q;\n\n\t_adapter *padapter;\n\n\tu32 adhoc_expire_to;\n\n\tint rx_chk_limit;\n\n#ifdef CONFIG_AP_MODE\n\t_list asoc_list;\n\t_list auth_list;\n\t_lock asoc_list_lock;\n\t_lock auth_list_lock;\n\tu8 asoc_list_cnt;\n\tu8 auth_list_cnt;\n\n\tunsigned int auth_to;  /* sec, time to expire in authenticating. */\n\tunsigned int assoc_to; /* sec, time to expire before associating. */\n\tunsigned int expire_to; /* sec , time to expire after associated. */\n\n\t/*\n\t* pointers to STA info; based on allocated AID or NULL if AID free\n\t* AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1\n\t*/\n\tstruct sta_info **sta_aid;\n\tu16 max_aid;\n\tu16 started_aid; /* started AID for allocation search */\n\tbool rr_aid; /* round robin AID allocation, will modify started_aid */\n\tu8 aid_bmp_len; /* in byte */\n\tu8 *sta_dz_bitmap;\n\tu8 *tim_bitmap;\n\n\tu16 max_num_sta;\n\n#if CONFIG_RTW_MACADDR_ACL\n\tstruct wlan_acl_pool acl_list[RTW_ACL_PERIOD_NUM];\n#endif\n\n\t#if CONFIG_RTW_PRE_LINK_STA\n\tstruct pre_link_sta_ctl_t pre_link_sta_ctl;\n\t#endif\n\n#endif /* CONFIG_AP_MODE */\n\n#ifdef CONFIG_ATMEL_RC_PATCH\n\tu8 atmel_rc_pattern[6];\n#endif\n\tu8 c2h_sta_mac[ETH_ALEN];\n\tu8 c2h_adapter_id;\n\tstruct submit_ctx *gotc2h;\n};\n\n\n__inline static u32 wifi_mac_hash(const u8 *mac)\n{\n\tu32 x;\n\n\tx = mac[0];\n\tx = (x << 2) ^ mac[1];\n\tx = (x << 2) ^ mac[2];\n\tx = (x << 2) ^ mac[3];\n\tx = (x << 2) ^ mac[4];\n\tx = (x << 2) ^ mac[5];\n\n\tx ^= x >> 8;\n\tx  = x & (NUM_STA - 1);\n\n\treturn x;\n}\n\n\nextern u32\t_rtw_init_sta_priv(struct sta_priv *pstapriv);\nextern u32\t_rtw_free_sta_priv(struct sta_priv *pstapriv);\n\n#define stainfo_offset_valid(offset) (offset < NUM_STA && offset >= 0)\nint rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta);\nstruct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset);\n\nextern struct sta_info *rtw_alloc_stainfo(struct\tsta_priv *pstapriv, const u8 *hwaddr);\nextern u32\trtw_free_stainfo(_adapter *padapter , struct sta_info *psta);\nextern void rtw_free_all_stainfo(_adapter *padapter);\nextern struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr);\nextern u32 rtw_init_bcmc_stainfo(_adapter *padapter);\nextern struct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter);\n\n#ifdef CONFIG_AP_MODE\nu16 rtw_aid_alloc(_adapter *adapter, struct sta_info *sta);\nvoid dump_aid_status(void *sel, _adapter *adapter);\n#endif\n\n#if CONFIG_RTW_MACADDR_ACL\nextern u8 rtw_access_ctrl(_adapter *adapter, const u8 *mac_addr);\nvoid dump_macaddr_acl(void *sel, _adapter *adapter);\n#endif\n\nbool rtw_is_pre_link_sta(struct sta_priv *stapriv, u8 *addr);\n#if CONFIG_RTW_PRE_LINK_STA\nstruct sta_info *rtw_pre_link_sta_add(struct sta_priv *stapriv, u8 *hwaddr);\nvoid rtw_pre_link_sta_del(struct sta_priv *stapriv, u8 *hwaddr);\nvoid rtw_pre_link_sta_ctl_reset(struct sta_priv *stapriv);\nvoid rtw_pre_link_sta_ctl_init(struct sta_priv *stapriv);\nvoid rtw_pre_link_sta_ctl_deinit(struct sta_priv *stapriv);\nvoid dump_pre_link_sta_ctl(void *sel, struct sta_priv *stapriv);\n#endif /* CONFIG_RTW_PRE_LINK_STA */\n\n#endif /* _STA_INFO_H_ */\n"
  },
  {
    "path": "include/usb_hal.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __USB_HAL_H__\n#define __USB_HAL_H__\n\nint usb_init_recv_priv(_adapter *padapter, u16 ini_in_buf_sz);\nvoid usb_free_recv_priv(_adapter *padapter, u16 ini_in_buf_sz);\n#ifdef CONFIG_FW_C2H_REG\nvoid usb_c2h_hisr_hdl(_adapter *adapter, u8 *buf);\n#endif\n\nu8 rtw_set_hal_ops(_adapter *padapter);\n\n#ifdef CONFIG_RTL8188E\nvoid rtl8188eu_set_hal_ops(_adapter *padapter);\n#endif\n\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\nvoid rtl8812au_set_hal_ops(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_RTL8192E\nvoid rtl8192eu_set_hal_ops(_adapter *padapter);\n#endif\n\n\n#ifdef CONFIG_RTL8723B\nvoid rtl8723bu_set_hal_ops(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_RTL8814A\nvoid rtl8814au_set_hal_ops(_adapter *padapter);\n#endif /* CONFIG_RTL8814A */\n\n#ifdef CONFIG_RTL8188F\nvoid rtl8188fu_set_hal_ops(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_RTL8188GTV\nvoid rtl8188gtvu_set_hal_ops(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_RTL8703B\nvoid rtl8703bu_set_hal_ops(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_RTL8723D\nvoid rtl8723du_set_hal_ops(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_RTL8710B\nvoid rtl8710bu_set_hal_ops(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_RTL8192F\nvoid rtl8192fu_set_hal_ops(_adapter *padapter);\n#endif /* CONFIG_RTL8192F */\n\n#endif /* __USB_HAL_H__ */\n"
  },
  {
    "path": "include/usb_ops.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __USB_OPS_H_\n#define __USB_OPS_H_\n\n\n#define REALTEK_USB_VENQT_READ\t\t0xC0\n#define REALTEK_USB_VENQT_WRITE\t0x40\n#define REALTEK_USB_VENQT_CMD_REQ\t0x05\n#define REALTEK_USB_VENQT_CMD_IDX\t0x00\n#define REALTEK_USB_IN_INT_EP_IDX\t1\n\nenum {\n\tVENDOR_WRITE = 0x00,\n\tVENDOR_READ = 0x01,\n};\n#define ALIGNMENT_UNIT\t\t\t\t16\n#define MAX_VENDOR_REQ_CMD_SIZE\t254\t\t/* 8188cu SIE Support */\n#define MAX_USB_IO_CTL_SIZE\t\t(MAX_VENDOR_REQ_CMD_SIZE + ALIGNMENT_UNIT)\n\n#ifdef PLATFORM_LINUX\n#include <usb_ops_linux.h>\n#endif /* PLATFORM_LINUX */\n\n#ifdef CONFIG_RTL8188E\nvoid rtl8188eu_set_hw_type(struct dvobj_priv *pdvobj);\n#ifdef CONFIG_SUPPORT_USB_INT\nvoid interrupt_handler_8188eu(_adapter *padapter, u16 pkt_len, u8 *pbuf);\n#endif\n#endif\n\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\nvoid rtl8812au_set_hw_type(struct dvobj_priv *pdvobj);\n#ifdef CONFIG_SUPPORT_USB_INT\nvoid interrupt_handler_8812au(_adapter *padapter, u16 pkt_len, u8 *pbuf);\n#endif\n#endif\n\n#ifdef CONFIG_RTL8814A\nvoid rtl8814au_set_hw_type(struct dvobj_priv *pdvobj);\n#ifdef CONFIG_SUPPORT_USB_INT\nvoid interrupt_handler_8814au(_adapter *padapter, u16 pkt_len, u8 *pbuf);\n#endif\n#endif /* CONFIG_RTL8814 */\n\n#ifdef CONFIG_RTL8192E\nvoid rtl8192eu_set_hw_type(struct dvobj_priv *pdvobj);\n#ifdef CONFIG_SUPPORT_USB_INT\nvoid interrupt_handler_8192eu(_adapter *padapter, u16 pkt_len, u8 *pbuf);\n#endif\n\n#endif\n\n#ifdef CONFIG_RTL8188F\nvoid rtl8188fu_set_hw_type(struct dvobj_priv *pdvobj);\n#ifdef CONFIG_SUPPORT_USB_INT\nvoid interrupt_handler_8188fu(_adapter *padapter, u16 pkt_len, u8 *pbuf);\n#endif\n#endif\n\n#ifdef CONFIG_RTL8188GTV\nvoid rtl8188gtvu_set_hw_type(struct dvobj_priv *pdvobj);\n#ifdef CONFIG_SUPPORT_USB_INT\nvoid interrupt_handler_8188gtvu(_adapter *padapter, u16 pkt_len, u8 *pbuf);\n#endif\n#endif\n\n#ifdef CONFIG_RTL8723B\nvoid rtl8723bu_set_hw_type(struct dvobj_priv *pdvobj);\n#ifdef CONFIG_SUPPORT_USB_INT\nvoid interrupt_handler_8723bu(_adapter *padapter, u16 pkt_len, u8 *pbuf);\n#endif\n#endif\n\n#ifdef CONFIG_RTL8703B\nvoid rtl8703bu_set_hw_type(struct dvobj_priv *pdvobj);\n#ifdef CONFIG_SUPPORT_USB_INT\nvoid interrupt_handler_8703bu(_adapter *padapter, u16 pkt_len, u8 *pbuf);\n#endif /* CONFIG_SUPPORT_USB_INT */\n#endif /* CONFIG_RTL8703B */\n\nvoid usb_set_intf_ops(_adapter *padapter, struct _io_ops *pops);\n\n#ifdef CONFIG_RTL8723D\nvoid rtl8723du_set_hw_type(struct dvobj_priv *pdvobj);\nvoid rtl8723du_set_intf_ops(struct _io_ops *pops);\nvoid rtl8723du_recv_tasklet(void *priv);\nvoid rtl8723du_xmit_tasklet(void *priv);\n#ifdef CONFIG_SUPPORT_USB_INT\nvoid interrupt_handler_8723du(_adapter *padapter, u16 pkt_len, u8 *pbuf);\n#endif /* CONFIG_SUPPORT_USB_INT */\n#endif /* CONFIG_RTL8723D */\n\n#ifdef CONFIG_RTL8710B\nvoid rtl8710bu_set_hw_type(struct dvobj_priv *pdvobj);\nvoid rtl8710bu_set_intf_ops(struct _io_ops *pops);\nvoid rtl8710bu_recv_tasklet(void *priv);\nvoid rtl8710bu_xmit_tasklet(void *priv);\n#ifdef CONFIG_SUPPORT_USB_INT\nvoid interrupt_handler_8710bu(_adapter *padapter, u16 pkt_len, u8 *pbuf);\n#endif /* CONFIG_SUPPORT_USB_INT */\n#endif /* CONFIG_RTL8710B */\n\n#ifdef CONFIG_RTL8192F\nvoid rtl8192fu_set_hw_type(struct dvobj_priv *pdvobj);\nvoid rtl8192fu_xmit_tasklet(void *priv);\n#ifdef CONFIG_SUPPORT_USB_INT\nvoid rtl8192fu_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf);\n#endif /* CONFIG_SUPPORT_USB_INT */\n#endif /* CONFIG_RTL8192F */\n\nenum RTW_USB_SPEED {\n\tRTW_USB_SPEED_UNKNOWN\t= 0,\n\tRTW_USB_SPEED_1_1\t= 1,\n\tRTW_USB_SPEED_2\t\t= 2,\n\tRTW_USB_SPEED_3\t\t= 3,\n};\n\n#define IS_FULL_SPEED_USB(Adapter)\t(adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_1_1)\n#define IS_HIGH_SPEED_USB(Adapter)\t(adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_2)\n#define IS_SUPER_SPEED_USB(Adapter)\t(adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_3)\n\n#define USB_SUPER_SPEED_BULK_SIZE\t1024\t/* usb 3.0 */\n#define USB_HIGH_SPEED_BULK_SIZE\t512\t\t/* usb 2.0 */\n#define USB_FULL_SPEED_BULK_SIZE\t64\t\t/* usb 1.1 */\n\nstatic inline u8 rtw_usb_bulk_size_boundary(_adapter *padapter, int buf_len)\n{\n\tu8 rst = _TRUE;\n\n\tif (IS_SUPER_SPEED_USB(padapter))\n\t\trst = (0 == (buf_len) % USB_SUPER_SPEED_BULK_SIZE) ? _TRUE : _FALSE;\n\telse if (IS_HIGH_SPEED_USB(padapter))\n\t\trst = (0 == (buf_len) % USB_HIGH_SPEED_BULK_SIZE) ? _TRUE : _FALSE;\n\telse\n\t\trst = (0 == (buf_len) % USB_FULL_SPEED_BULK_SIZE) ? _TRUE : _FALSE;\n\treturn rst;\n}\n\n\n#endif /* __USB_OPS_H_ */\n"
  },
  {
    "path": "include/usb_ops_linux.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __USB_OPS_LINUX_H__\n#define __USB_OPS_LINUX_H__\n\n#define VENDOR_CMD_MAX_DATA_LEN\t254\n#define FW_START_ADDRESS\t0x1000\n\n#define RTW_USB_CONTROL_MSG_TIMEOUT_TEST\t10/* ms */\n#define RTW_USB_CONTROL_MSG_TIMEOUT\t500/* ms */\n\n#define RECV_BULK_IN_ADDR\t\t0x80/* assign by drv, not real address */\n#define RECV_INT_IN_ADDR\t\t0x81/* assign by drv, not real address */\n\n#define INTERRUPT_MSG_FORMAT_LEN 60\n\n#if defined(CONFIG_VENDOR_REQ_RETRY) && defined(CONFIG_USB_VENDOR_REQ_MUTEX)\n\t/* vendor req retry should be in the situation when each vendor req is atomically submitted from others */\n\t#define MAX_USBCTRL_VENDORREQ_TIMES\t10\n#else\n\t#define MAX_USBCTRL_VENDORREQ_TIMES\t1\n#endif\n\n#define RTW_USB_BULKOUT_TIMEOUT\t5000/* ms */\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18))\n#define _usbctrl_vendorreq_async_callback(urb, regs)\t_usbctrl_vendorreq_async_callback(urb)\n#define usb_bulkout_zero_complete(purb, regs)\tusb_bulkout_zero_complete(purb)\n#define usb_write_mem_complete(purb, regs)\tusb_write_mem_complete(purb)\n#define usb_write_port_complete(purb, regs)\tusb_write_port_complete(purb)\n#define usb_read_port_complete(purb, regs)\tusb_read_port_complete(purb)\n#define usb_read_interrupt_complete(purb, regs)\tusb_read_interrupt_complete(purb)\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 12))\n#define rtw_usb_control_msg(dev, pipe, request, requesttype, value, index, data, size, timeout_ms) \\\n\tusb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), (data), (size), (timeout_ms))\n#define rtw_usb_bulk_msg(usb_dev, pipe, data, len, actual_length, timeout_ms) \\\n\tusb_bulk_msg((usb_dev), (pipe), (data), (len), (actual_length), (timeout_ms))\n#else\n#define rtw_usb_control_msg(dev, pipe, request, requesttype, value, index, data, size, timeout_ms) \\\n\tusb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), (data), (size), \\\n\t\t((timeout_ms) == 0) || ((timeout_ms) * HZ / 1000 > 0) ? ((timeout_ms) * HZ / 1000) : 1)\n#define rtw_usb_bulk_msg(usb_dev, pipe, data, len, actual_length, timeout_ms) \\\n\tusb_bulk_msg((usb_dev), (pipe), (data), (len), (actual_length), \\\n\t\t((timeout_ms) == 0) || ((timeout_ms) * HZ / 1000 > 0) ? ((timeout_ms) * HZ / 1000) : 1)\n#endif\n\n\n#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ\nint usb_async_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val);\nint usb_async_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val);\nint usb_async_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val);\n#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */\n\nunsigned int ffaddr2pipehdl(struct dvobj_priv *pdvobj, u32 addr);\n\nvoid usb_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem);\nvoid usb_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem);\n\nvoid usb_read_port_cancel(struct intf_hdl *pintfhdl);\n\nu32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem);\nvoid usb_write_port_cancel(struct intf_hdl *pintfhdl);\n\nint usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype);\n#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ\nint _usbctrl_vendorreq_async_write(struct usb_device *udev, u8 request,\n\t\tu16 value, u16 index, void *pdata, u16 len, u8 requesttype);\n#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */\n\nu8 usb_read8(struct intf_hdl *pintfhdl, u32 addr);\nu16 usb_read16(struct intf_hdl *pintfhdl, u32 addr);\nu32 usb_read32(struct intf_hdl *pintfhdl, u32 addr);\nint usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val);\nint usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val);\nint usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val);\nint usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);\nu32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem);\nvoid usb_recv_tasklet(void *priv);\n\n#ifdef CONFIG_USB_INTERRUPT_IN_PIPE\nvoid usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs);\nu32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr);\n#endif\n#endif\n"
  },
  {
    "path": "include/usb_osintf.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __USB_OSINTF_H\n#define __USB_OSINTF_H\n\n#include <usb_vendor_req.h>\n\n#define USBD_HALTED(Status) ((u32)(Status) >> 30 == 3)\n\n\nu8 usbvendorrequest(struct dvobj_priv *pdvobjpriv, RT_USB_BREQUEST brequest, RT_USB_WVALUE wvalue, u8 windex, void *data, u8 datalen, u8 isdirectionin);\n\n\n#endif\n"
  },
  {
    "path": "include/usb_vendor_req.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _USB_VENDOR_REQUEST_H_\n#define _USB_VENDOR_REQUEST_H_\n\n/* 4\tSet/Get Register related wIndex/Data */\n#define\tRT_USB_RESET_MASK_OFF\t\t0\n#define\tRT_USB_RESET_MASK_ON\t\t1\n#define\tRT_USB_SLEEP_MASK_OFF\t\t0\n#define\tRT_USB_SLEEP_MASK_ON\t\t1\n#define\tRT_USB_LDO_ON\t\t\t\t1\n#define\tRT_USB_LDO_OFF\t\t\t\t0\n\n/* 4\tSet/Get SYSCLK related\twValue or Data */\n#define\tRT_USB_SYSCLK_32KHZ\t\t0\n#define\tRT_USB_SYSCLK_40MHZ\t\t1\n#define\tRT_USB_SYSCLK_60MHZ\t\t2\n\n\ntypedef enum _RT_USB_BREQUEST {\n\tRT_USB_SET_REGISTER\t\t= 1,\n\tRT_USB_SET_SYSCLK\t\t= 2,\n\tRT_USB_GET_SYSCLK\t\t= 3,\n\tRT_USB_GET_REGISTER\t\t= 4\n} RT_USB_BREQUEST;\n\n\ntypedef enum _RT_USB_WVALUE {\n\tRT_USB_RESET_MASK\t=\t1,\n\tRT_USB_SLEEP_MASK\t=\t2,\n\tRT_USB_USB_HRCPWM\t=\t3,\n\tRT_USB_LDO\t\t\t=\t4,\n\tRT_USB_BOOT_TYPE\t=\t5\n} RT_USB_WVALUE;\n\n\n#if 0\nBOOLEAN usbvendorrequest(PCE_USB_DEVICE\tCEdevice, RT_USB_BREQUEST bRequest, RT_USB_WVALUE wValue, u8 wIndex, void *Data, u8 DataLength, BOOLEAN isDirectionIn);\nBOOLEAN CEusbGetStatusRequest(PCE_USB_DEVICE CEdevice, u16 Op, u16 Index, void *Data);\nBOOLEAN CEusbFeatureRequest(PCE_USB_DEVICE CEdevice, u16 Op, u16 FeatureSelector, u16 Index);\nBOOLEAN CEusbGetDescriptorRequest(PCE_USB_DEVICE CEdevice, short urbLength, u8 DescriptorType, u8 Index, u16 LanguageId, void *TransferBuffer, u32 TransferBufferLength);\n#endif\n\n#endif\n"
  },
  {
    "path": "include/wifi.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef _WIFI_H_\n#define _WIFI_H_\n\n\n#ifndef BIT\n#define BIT(x)\t(1 << (x))\n#endif\n\n\n#define WLAN_ETHHDR_LEN\t\t14\n#define WLAN_ETHADDR_LEN\t6\n#define WLAN_IEEE_OUI_LEN\t3\n#define WLAN_ADDR_LEN\t\t6\n#define WLAN_CRC_LEN\t\t4\n#define WLAN_BSSID_LEN\t\t6\n#define WLAN_BSS_TS_LEN\t\t8\n#define WLAN_HDR_A3_LEN\t\t24\n#define WLAN_HDR_A4_LEN\t\t30\n#define WLAN_HDR_A3_QOS_LEN\t26\n#define WLAN_HDR_A4_QOS_LEN\t32\n#define WLAN_SSID_MAXLEN\t32\n#define WLAN_DATA_MAXLEN\t2312\n\n#define WLAN_A3_PN_OFFSET\t24\n#define WLAN_A4_PN_OFFSET\t30\n\n#define WLAN_MIN_ETHFRM_LEN\t60\n#define WLAN_MAX_ETHFRM_LEN\t1514\n#define WLAN_ETHHDR_LEN\t\t14\n#define WLAN_WMM_LEN\t\t24\n#define VENDOR_NAME_LEN\t\t20\n\n#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE\n#define WLAN_MAX_VENDOR_IE_LEN 255\n#define WLAN_MAX_VENDOR_IE_NUM 5\n#define WIFI_BEACON_VENDOR_IE_BIT BIT(0)\n#define WIFI_PROBEREQ_VENDOR_IE_BIT BIT(1)\n#define WIFI_PROBERESP_VENDOR_IE_BIT BIT(2)\n#define WIFI_ASSOCREQ_VENDOR_IE_BIT BIT(3)\n#define WIFI_ASSOCRESP_VENDOR_IE_BIT BIT(4)\n#ifdef CONFIG_P2P\n#define WIFI_P2P_PROBEREQ_VENDOR_IE_BIT BIT(5)\n#define WIFI_P2P_PROBERESP_VENDOR_IE_BIT BIT(6)\n#define WLAN_MAX_VENDOR_IE_MASK_MAX 7\n#else\n#define WLAN_MAX_VENDOR_IE_MASK_MAX 5\n#endif\n#endif\n\n#define P80211CAPTURE_VERSION\t0x80211001\n\n/* This value is tested by WiFi 11n Test Plan 5.2.3.\n * This test verifies the WLAN NIC can update the NAV through sending the CTS with large duration. */\n#define\tWiFiNavUpperUs\t\t\t\t30000\t/* 30 ms */\n\n#ifdef GREEN_HILL\n#pragma pack(1)\n#endif\n\nenum WIFI_FRAME_TYPE {\n\tWIFI_MGT_TYPE  =\t(0),\n\tWIFI_CTRL_TYPE =\t(BIT(2)),\n\tWIFI_DATA_TYPE =\t(BIT(3)),\n\tWIFI_QOS_DATA_TYPE\t= (BIT(7) | BIT(3)),\t/* !< QoS Data\t */\n};\n\nenum WIFI_FRAME_SUBTYPE {\n\n\t/* below is for mgt frame */\n\tWIFI_ASSOCREQ       = (0 | WIFI_MGT_TYPE),\n\tWIFI_ASSOCRSP       = (BIT(4) | WIFI_MGT_TYPE),\n\tWIFI_REASSOCREQ     = (BIT(5) | WIFI_MGT_TYPE),\n\tWIFI_REASSOCRSP     = (BIT(5) | BIT(4) | WIFI_MGT_TYPE),\n\tWIFI_PROBEREQ       = (BIT(6) | WIFI_MGT_TYPE),\n\tWIFI_PROBERSP       = (BIT(6) | BIT(4) | WIFI_MGT_TYPE),\n\tWIFI_BEACON         = (BIT(7) | WIFI_MGT_TYPE),\n\tWIFI_ATIM           = (BIT(7) | BIT(4) | WIFI_MGT_TYPE),\n\tWIFI_DISASSOC       = (BIT(7) | BIT(5) | WIFI_MGT_TYPE),\n\tWIFI_AUTH           = (BIT(7) | BIT(5) | BIT(4) | WIFI_MGT_TYPE),\n\tWIFI_DEAUTH         = (BIT(7) | BIT(6) | WIFI_MGT_TYPE),\n\tWIFI_ACTION         = (BIT(7) | BIT(6) | BIT(4) | WIFI_MGT_TYPE),\n\tWIFI_ACTION_NOACK = (BIT(7) | BIT(6) | BIT(5) | WIFI_MGT_TYPE),\n\n\t/* below is for control frame */\n\tWIFI_BF_REPORT_POLL = (BIT(6) | WIFI_CTRL_TYPE),\n\tWIFI_NDPA         = (BIT(6) | BIT(4) | WIFI_CTRL_TYPE),\n\tWIFI_BAR            = (BIT(7) | WIFI_CTRL_TYPE),\n\tWIFI_PSPOLL         = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE),\n\tWIFI_RTS            = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE),\n\tWIFI_CTS            = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE),\n\tWIFI_ACK            = (BIT(7) | BIT(6) | BIT(4) | WIFI_CTRL_TYPE),\n\tWIFI_CFEND          = (BIT(7) | BIT(6) | BIT(5) | WIFI_CTRL_TYPE),\n\tWIFI_CFEND_CFACK    = (BIT(7) | BIT(6) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE),\n\n\t/* below is for data frame */\n\tWIFI_DATA           = (0 | WIFI_DATA_TYPE),\n\tWIFI_DATA_CFACK     = (BIT(4) | WIFI_DATA_TYPE),\n\tWIFI_DATA_CFPOLL    = (BIT(5) | WIFI_DATA_TYPE),\n\tWIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | WIFI_DATA_TYPE),\n\tWIFI_DATA_NULL      = (BIT(6) | WIFI_DATA_TYPE),\n\tWIFI_CF_ACK         = (BIT(6) | BIT(4) | WIFI_DATA_TYPE),\n\tWIFI_CF_POLL        = (BIT(6) | BIT(5) | WIFI_DATA_TYPE),\n\tWIFI_CF_ACKPOLL     = (BIT(6) | BIT(5) | BIT(4) | WIFI_DATA_TYPE),\n\tWIFI_QOS_DATA_NULL\t= (BIT(6) | WIFI_QOS_DATA_TYPE),\n};\n\nenum WIFI_REASON_CODE\t{\n\t_RSON_RESERVED_\t\t\t\t\t= 0,\n\t_RSON_UNSPECIFIED_\t\t\t\t= 1,\n\t_RSON_AUTH_NO_LONGER_VALID_\t\t= 2,\n\t_RSON_DEAUTH_STA_LEAVING_\t\t= 3,\n\t_RSON_INACTIVITY_\t\t\t\t= 4,\n\t_RSON_UNABLE_HANDLE_\t\t\t= 5,\n\t_RSON_CLS2_\t\t\t\t\t\t= 6,\n\t_RSON_CLS3_\t\t\t\t\t\t= 7,\n\t_RSON_DISAOC_STA_LEAVING_\t\t= 8,\n\t_RSON_ASOC_NOT_AUTH_\t\t\t= 9,\n\n\t/* WPA reason */\n\t_RSON_INVALID_IE_\t\t\t\t= 13,\n\t_RSON_MIC_FAILURE_\t\t\t\t= 14,\n\t_RSON_4WAY_HNDSHK_TIMEOUT_\t\t= 15,\n\t_RSON_GROUP_KEY_UPDATE_TIMEOUT_\t= 16,\n\t_RSON_DIFF_IE_\t\t\t\t\t= 17,\n\t_RSON_MLTCST_CIPHER_NOT_VALID_\t= 18,\n\t_RSON_UNICST_CIPHER_NOT_VALID_\t= 19,\n\t_RSON_AKMP_NOT_VALID_\t\t\t= 20,\n\t_RSON_UNSUPPORT_RSNE_VER_\t\t= 21,\n\t_RSON_INVALID_RSNE_CAP_\t\t\t= 22,\n\t_RSON_IEEE_802DOT1X_AUTH_FAIL_\t= 23,\n\n\t/* belowing are Realtek definition */\n\t_RSON_PMK_NOT_AVAILABLE_\t\t= 24,\n\t_RSON_TDLS_TEAR_TOOFAR_\t\t\t= 25,\n\t_RSON_TDLS_TEAR_UN_RSN_\t\t\t= 26,\n};\n\n/* Reason codes (IEEE 802.11-2007, 7.3.1.7, Table 7-22) */\n#if 0\n#define WLAN_REASON_UNSPECIFIED 1\n#define WLAN_REASON_PREV_AUTH_NOT_VALID 2\n#define WLAN_REASON_DEAUTH_LEAVING 3\n#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4\n#define WLAN_REASON_DISASSOC_AP_BUSY 5\n#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6\n#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7\n#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8\n#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9\n#endif\n/* IEEE 802.11h */\n#define WLAN_REASON_PWR_CAPABILITY_NOT_VALID 10\n#define WLAN_REASON_SUPPORTED_CHANNEL_NOT_VALID 11\n#if 0\n/* IEEE 802.11i */\n#define WLAN_REASON_INVALID_IE 13\n#define WLAN_REASON_MICHAEL_MIC_FAILURE 14\n#define WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT 15\n#define WLAN_REASON_GROUP_KEY_UPDATE_TIMEOUT 16\n#define WLAN_REASON_IE_IN_4WAY_DIFFERS 17\n#define WLAN_REASON_GROUP_CIPHER_NOT_VALID 18\n#define WLAN_REASON_PAIRWISE_CIPHER_NOT_VALID 19\n#define WLAN_REASON_AKMP_NOT_VALID 20\n#define WLAN_REASON_UNSUPPORTED_RSN_IE_VERSION 21\n#define WLAN_REASON_INVALID_RSN_IE_CAPAB 22\n#define WLAN_REASON_IEEE_802_1X_AUTH_FAILED 23\n#define WLAN_REASON_CIPHER_SUITE_REJECTED 24\n#endif\n\nenum WIFI_STATUS_CODE {\n\t_STATS_SUCCESSFUL_\t\t\t= 0,\n\t_STATS_FAILURE_\t\t\t\t= 1,\n\t_STATS_SEC_DISABLED_\t\t\t= 5,\n\t_STATS_NOT_IN_SAME_BSS_\t\t= 7,\n\t_STATS_CAP_FAIL_\t\t\t= 10,\n\t_STATS_NO_ASOC_\t\t\t\t= 11,\n\t_STATS_OTHER_\t\t\t\t= 12,\n\t_STATS_NO_SUPP_ALG_\t\t\t= 13,\n\t_STATS_OUT_OF_AUTH_SEQ_\t\t= 14,\n\t_STATS_CHALLENGE_FAIL_\t\t= 15,\n\t_STATS_AUTH_TIMEOUT_\t\t= 16,\n\t_STATS_UNABLE_HANDLE_STA_\t= 17,\n\t_STATS_RATE_FAIL_\t\t\t= 18,\n\t_STATS_REFUSED_TEMPORARILY_ = 30,\n\t_STATS_DECLINE_REQ_\t\t\t= 37,\n\t_STATS_INVALID_PARAMETERS_\t= 38,\n\t_STATS_INVALID_RSNIE_\t\t\t= 72,\n};\n\n/* Status codes (IEEE 802.11-2007, 7.3.1.9, Table 7-23) */\n#if 0\n#define WLAN_STATUS_SUCCESS 0\n#define WLAN_STATUS_UNSPECIFIED_FAILURE 1\n#define WLAN_STATUS_CAPS_UNSUPPORTED 10\n#define WLAN_STATUS_REASSOC_NO_ASSOC 11\n#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12\n#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13\n#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14\n#define WLAN_STATUS_CHALLENGE_FAIL 15\n#define WLAN_STATUS_AUTH_TIMEOUT 16\n#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17\n#define WLAN_STATUS_ASSOC_DENIED_RATES 18\n#endif\n/* entended */\n/* IEEE 802.11b */\n#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19\n#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20\n#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21\n/* IEEE 802.11h */\n#define WLAN_STATUS_SPEC_MGMT_REQUIRED 22\n#define WLAN_STATUS_PWR_CAPABILITY_NOT_VALID 23\n#define WLAN_STATUS_SUPPORTED_CHANNEL_NOT_VALID 24\n/* IEEE 802.11g */\n#define WLAN_STATUS_ASSOC_DENIED_NO_SHORT_SLOT_TIME 25\n#define WLAN_STATUS_ASSOC_DENIED_NO_ER_PBCC 26\n#define WLAN_STATUS_ASSOC_DENIED_NO_DSSS_OFDM 27\n/* IEEE 802.11w */\n#define WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY 30\n#define WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION 31\n/* IEEE 802.11i */\n#define WLAN_STATUS_INVALID_IE 40\n#define WLAN_STATUS_GROUP_CIPHER_NOT_VALID 41\n#define WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID 42\n#define WLAN_STATUS_AKMP_NOT_VALID 43\n#define WLAN_STATUS_UNSUPPORTED_RSN_IE_VERSION 44\n#define WLAN_STATUS_INVALID_RSN_IE_CAPAB 45\n#define WLAN_STATUS_CIPHER_REJECTED_PER_POLICY 46\n#define WLAN_STATUS_TS_NOT_CREATED 47\n#define WLAN_STATUS_DIRECT_LINK_NOT_ALLOWED 48\n#define WLAN_STATUS_DEST_STA_NOT_PRESENT 49\n#define WLAN_STATUS_DEST_STA_NOT_QOS_STA 50\n#define WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE 51\n/* IEEE 802.11r */\n#define WLAN_STATUS_INVALID_FT_ACTION_FRAME_COUNT 52\n#define WLAN_STATUS_INVALID_PMKID 53\n#define WLAN_STATUS_INVALID_MDIE 54\n#define WLAN_STATUS_INVALID_FTIE 55\n\n\nenum WIFI_REG_DOMAIN {\n\tDOMAIN_FCC\t\t= 1,\n\tDOMAIN_IC\t\t= 2,\n\tDOMAIN_ETSI\t\t= 3,\n\tDOMAIN_SPAIN\t= 4,\n\tDOMAIN_FRANCE\t= 5,\n\tDOMAIN_MKK\t\t= 6,\n\tDOMAIN_ISRAEL\t= 7,\n\tDOMAIN_MKK1\t\t= 8,\n\tDOMAIN_MKK2\t\t= 9,\n\tDOMAIN_MKK3\t\t= 10,\n\tDOMAIN_MAX\n};\n\n#define _TO_DS_\t\tBIT(8)\n#define _FROM_DS_\tBIT(9)\n#define _MORE_FRAG_\tBIT(10)\n#define _RETRY_\t\tBIT(11)\n#define _PWRMGT_\tBIT(12)\n#define _MORE_DATA_\tBIT(13)\n#define _PRIVACY_\tBIT(14)\n#define _ORDER_\t\t\tBIT(15)\n\n#define SetToDs(pbuf)\t\\\n\tdo\t{\t\\\n\t\t*(unsigned short *)(pbuf) |= cpu_to_le16(_TO_DS_); \\\n\t} while (0)\n\n#define GetToDs(pbuf)\t(((*(unsigned short *)(pbuf)) & le16_to_cpu(_TO_DS_)) != 0)\n\n#define ClearToDs(pbuf)\t\\\n\tdo\t{\t\\\n\t\t*(unsigned short *)(pbuf) &= (~cpu_to_le16(_TO_DS_)); \\\n\t} while (0)\n\n#define SetFrDs(pbuf)\t\\\n\tdo\t{\t\\\n\t\t*(unsigned short *)(pbuf) |= cpu_to_le16(_FROM_DS_); \\\n\t} while (0)\n\n#define GetFrDs(pbuf)\t(((*(unsigned short *)(pbuf)) & le16_to_cpu(_FROM_DS_)) != 0)\n\n#define ClearFrDs(pbuf)\t\\\n\tdo\t{\t\\\n\t\t*(unsigned short *)(pbuf) &= (~cpu_to_le16(_FROM_DS_)); \\\n\t} while (0)\n\n#define get_tofr_ds(pframe)\t((GetToDs(pframe) << 1) | GetFrDs(pframe))\n\n\n#define SetMFrag(pbuf)\t\\\n\tdo\t{\t\\\n\t\t*(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_FRAG_); \\\n\t} while (0)\n\n#define GetMFrag(pbuf)\t(((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_FRAG_)) != 0)\n\n#define ClearMFrag(pbuf)\t\\\n\tdo\t{\t\\\n\t\t*(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_FRAG_)); \\\n\t} while (0)\n\n#define SetRetry(pbuf)\t\\\n\tdo\t{\t\\\n\t\t*(unsigned short *)(pbuf) |= cpu_to_le16(_RETRY_); \\\n\t} while (0)\n\n#define GetRetry(pbuf)\t(((*(unsigned short *)(pbuf)) & le16_to_cpu(_RETRY_)) != 0)\n\n#define ClearRetry(pbuf)\t\\\n\tdo\t{\t\\\n\t\t*(unsigned short *)(pbuf) &= (~cpu_to_le16(_RETRY_)); \\\n\t} while (0)\n\n#define SetPwrMgt(pbuf)\t\\\n\tdo\t{\t\\\n\t\t*(unsigned short *)(pbuf) |= cpu_to_le16(_PWRMGT_); \\\n\t} while (0)\n\n#define GetPwrMgt(pbuf)\t(((*(unsigned short *)(pbuf)) & le16_to_cpu(_PWRMGT_)) != 0)\n\n#define ClearPwrMgt(pbuf)\t\\\n\tdo\t{\t\\\n\t\t*(unsigned short *)(pbuf) &= (~cpu_to_le16(_PWRMGT_)); \\\n\t} while (0)\n\n#define SetMData(pbuf)\t\\\n\tdo\t{\t\\\n\t\t*(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_DATA_); \\\n\t} while (0)\n\n#define GetMData(pbuf)\t(((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_DATA_)) != 0)\n\n#define ClearMData(pbuf)\t\\\n\tdo\t{\t\\\n\t\t*(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_DATA_)); \\\n\t} while (0)\n\n#define SetPrivacy(pbuf)\t\\\n\tdo\t{\t\\\n\t\t*(unsigned short *)(pbuf) |= cpu_to_le16(_PRIVACY_); \\\n\t} while (0)\n\n#define GetPrivacy(pbuf)\t(((*(unsigned short *)(pbuf)) & le16_to_cpu(_PRIVACY_)) != 0)\n\n#define ClearPrivacy(pbuf)\t\\\n\tdo\t{\t\\\n\t\t*(unsigned short *)(pbuf) &= (~cpu_to_le16(_PRIVACY_)); \\\n\t} while (0)\n\n\n#define GetOrder(pbuf)\t(((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0)\n\n#define GetFrameType(pbuf)\t(le16_to_cpu(*(unsigned short *)(pbuf)) & (BIT(3) | BIT(2)))\n\n#define SetFrameType(pbuf, type)\t\\\n\tdo {\t\\\n\t\t*(unsigned short *)(pbuf) &= __constant_cpu_to_le16(~(BIT(3) | BIT(2))); \\\n\t\t*(unsigned short *)(pbuf) |= __constant_cpu_to_le16(type); \\\n\t} while (0)\n\n#define get_frame_sub_type(pbuf)\t(cpu_to_le16(*(unsigned short *)(pbuf)) & (BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2)))\n\n\n#define set_frame_sub_type(pbuf, type) \\\n\tdo {    \\\n\t\t*(unsigned short *)(pbuf) &= cpu_to_le16(~(BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))); \\\n\t\t*(unsigned short *)(pbuf) |= cpu_to_le16(type); \\\n\t} while (0)\n\n\n#define GetSequence(pbuf)\t(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) >> 4)\n\n#define GetFragNum(pbuf)\t(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & 0x0f)\n\n#define GetTupleCache(pbuf)\t(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)))\n\n#define SetFragNum(pbuf, num) \\\n\tdo {    \\\n\t\t*(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \\\n\t\t\t((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu(~(0x000f))) | \\\n\t\t\t\tcpu_to_le16(0x0f & (num));     \\\n\t} while (0)\n\n#define SetSeqNum(pbuf, num) \\\n\tdo {    \\\n\t\t*(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \\\n\t\t\t((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu((unsigned short)~0xfff0)) | \\\n\t\t\tle16_to_cpu((unsigned short)(0xfff0 & (num << 4))); \\\n\t} while (0)\n\n#define set_duration(pbuf, dur) \\\n\tdo {    \\\n\t\t*(unsigned short *)((SIZE_PTR)(pbuf) + 2) = cpu_to_le16(0xffff & (dur)); \\\n\t} while (0)\n\n\n/* QoS control field */\n#define SetPriority(qc, tid)\tSET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 0, 4, tid)\n#define SetEOSP(qc, eosp)\t\tSET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 4, 1, eosp)\n#define SetAckpolicy(qc, ack)\tSET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 5, 2, ack)\n#define SetAMsdu(qc, amsdu)\t\tSET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 7, 1, amsdu)\n\n#define GetPriority(qc)\t\tLE_BITS_TO_2BYTE(((u8 *)(qc)), 0, 4)\n#define GetEOSP(qc)\t\t\tLE_BITS_TO_2BYTE(((u8 *)(qc)), 4, 1)\n#define GetAckpolicy(qc)\tLE_BITS_TO_2BYTE(((u8 *)(qc)), 5, 2)\n#define GetAMsdu(qc)\t\tLE_BITS_TO_2BYTE(((u8 *)(qc)), 7, 1)\n\n/* QoS control field (MSTA only) */\n#define set_mctrl_present(qc, p)\tSET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 8, 1, p)\n#define set_mps_lv(qc, lv)\t\t\tSET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 9, 1, lv)\n#define set_rspi(qc, rspi)\t\t\tSET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 10, 1, rspi)\n\n#define get_mctrl_present(qc)\tLE_BITS_TO_2BYTE(((u8 *)(qc)), 8, 1)\n#define get_mps_lv(qc)\t\t\tLE_BITS_TO_2BYTE(((u8 *)(qc)), 9, 1)\n#define get_rspi(qc)\t\t\tLE_BITS_TO_2BYTE(((u8 *)(qc)), 10, 1)\n\n\n#define GetAid(pbuf)\t(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 2)) & 0x3fff)\n\n#define GetTid(pbuf)\t(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + (((GetToDs(pbuf)<<1) | GetFrDs(pbuf)) == 3 ? 30 : 24))) & 0x000f)\n\n#define GetAddr1Ptr(pbuf)\t((unsigned char *)((SIZE_PTR)(pbuf) + 4))\n\n#define get_addr2_ptr(pbuf)\t((unsigned char *)((SIZE_PTR)(pbuf) + 10))\n\n#define GetAddr3Ptr(pbuf)\t((unsigned char *)((SIZE_PTR)(pbuf) + 16))\n\n#define GetAddr4Ptr(pbuf)\t((unsigned char *)((SIZE_PTR)(pbuf) + 24))\n\n\n#define MacAddr_isBcst(addr) \\\n\t(\\\n\t ((addr[0] == 0xff) && (addr[1] == 0xff) && \\\n\t  (addr[2] == 0xff) && (addr[3] == 0xff) && \\\n\t  (addr[4] == 0xff) && (addr[5] == 0xff)) ? _TRUE : _FALSE \\\n\t)\n\n__inline static int IS_MCAST(const u8 *da)\n{\n\tif ((*da) & 0x01)\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\n\n__inline static unsigned char *get_ra(unsigned char *pframe)\n{\n\tunsigned char\t*ra;\n\tra = GetAddr1Ptr(pframe);\n\treturn ra;\n}\n__inline static unsigned char *get_ta(unsigned char *pframe)\n{\n\tunsigned char\t*ta;\n\tta = get_addr2_ptr(pframe);\n\treturn ta;\n}\n\n/* can't apply to mesh mode */\n__inline static unsigned char *get_da(unsigned char *pframe)\n{\n\tunsigned char\t*da;\n\tunsigned int\tto_fr_ds\t= (GetToDs(pframe) << 1) | GetFrDs(pframe);\n\n\tswitch (to_fr_ds) {\n\tcase 0x00:\t/* ToDs=0, FromDs=0 */\n\t\tda = GetAddr1Ptr(pframe);\n\t\tbreak;\n\tcase 0x01:\t/* ToDs=0, FromDs=1 */\n\t\tda = GetAddr1Ptr(pframe);\n\t\tbreak;\n\tcase 0x02:\t/* ToDs=1, FromDs=0 */\n\t\tda = GetAddr3Ptr(pframe);\n\t\tbreak;\n\tdefault:\t/* ToDs=1, FromDs=1 */\n\t\tda = GetAddr3Ptr(pframe);\n\t\tbreak;\n\t}\n\n\treturn da;\n}\n\n/* can't apply to mesh mode */\n__inline static unsigned char *get_sa(unsigned char *pframe)\n{\n\tunsigned char\t*sa;\n\tunsigned int\tto_fr_ds\t= (GetToDs(pframe) << 1) | GetFrDs(pframe);\n\n\tswitch (to_fr_ds) {\n\tcase 0x00:\t/* ToDs=0, FromDs=0 */\n\t\tsa = get_addr2_ptr(pframe);\n\t\tbreak;\n\tcase 0x01:\t/* ToDs=0, FromDs=1 */\n\t\tsa = GetAddr3Ptr(pframe);\n\t\tbreak;\n\tcase 0x02:\t/* ToDs=1, FromDs=0 */\n\t\tsa = get_addr2_ptr(pframe);\n\t\tbreak;\n\tdefault:\t/* ToDs=1, FromDs=1 */\n\t\tsa = GetAddr4Ptr(pframe);\n\t\tbreak;\n\t}\n\n\treturn sa;\n}\n\n/* can't apply to mesh mode */\n__inline static unsigned char *get_hdr_bssid(unsigned char *pframe)\n{\n\tunsigned char\t*sa = NULL;\n\tunsigned int\tto_fr_ds\t= (GetToDs(pframe) << 1) | GetFrDs(pframe);\n\n\tswitch (to_fr_ds) {\n\tcase 0x00:\t/* ToDs=0, FromDs=0 */\n\t\tsa = GetAddr3Ptr(pframe);\n\t\tbreak;\n\tcase 0x01:\t/* ToDs=0, FromDs=1 */\n\t\tsa = get_addr2_ptr(pframe);\n\t\tbreak;\n\tcase 0x02:\t/* ToDs=1, FromDs=0 */\n\t\tsa = GetAddr1Ptr(pframe);\n\t\tbreak;\n\tcase 0x03:\t/* ToDs=1, FromDs=1 */\n\t\tsa = GetAddr1Ptr(pframe);\n\t\tbreak;\n\t}\n\n\treturn sa;\n}\n\n\n__inline static int IsFrameTypeCtrl(unsigned char *pframe)\n{\n\tif (WIFI_CTRL_TYPE == GetFrameType(pframe))\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\nstatic inline int IsFrameTypeMgnt(unsigned char *pframe)\n{\n\tif (GetFrameType(pframe) == WIFI_MGT_TYPE)\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\nstatic inline int IsFrameTypeData(unsigned char *pframe)\n{\n\tif (GetFrameType(pframe) == WIFI_DATA_TYPE)\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\n\n\n/*-----------------------------------------------------------------------------\n\t\t\tBelow is for the security related definition\n------------------------------------------------------------------------------*/\n#define _RESERVED_FRAME_TYPE_\t0\n#define _SKB_FRAME_TYPE_\t\t2\n#define _PRE_ALLOCMEM_\t\t\t1\n#define _PRE_ALLOCHDR_\t\t\t3\n#define _PRE_ALLOCLLCHDR_\t\t4\n#define _PRE_ALLOCICVHDR_\t\t5\n#define _PRE_ALLOCMICHDR_\t\t6\n\n#define _SIFSTIME_\t\t\t\t((priv->pmib->dot11BssType.net_work_type&WIRELESS_11A) ? 16 : 10)\n#define _ACKCTSLNG_\t\t\t\t14\t/* 14 bytes long, including crclng */\n#define _CRCLNG_\t\t\t\t4\n\n#define _ASOCREQ_IE_OFFSET_\t\t4\t/* excluding wlan_hdr */\n#define\t_ASOCRSP_IE_OFFSET_\t\t6\n#define _REASOCREQ_IE_OFFSET_\t10\n#define _REASOCRSP_IE_OFFSET_\t6\n#define _PROBEREQ_IE_OFFSET_\t0\n#define\t_PROBERSP_IE_OFFSET_\t12\n#define _AUTH_IE_OFFSET_\t\t6\n#define _DEAUTH_IE_OFFSET_\t\t0\n#define _BEACON_IE_OFFSET_\t\t12\n#define _PUBLIC_ACTION_IE_OFFSET_\t8\n\n#define _FIXED_IE_LENGTH_\t\t\t_BEACON_IE_OFFSET_\n\n#define _SSID_IE_\t\t\t\t0\n#define _SUPPORTEDRATES_IE_\t1\n#define _DSSET_IE_\t\t\t\t3\n#define _TIM_IE_\t\t\t\t\t5\n#define _IBSS_PARA_IE_\t\t\t6\n#define _COUNTRY_IE_\t\t\t7\n#define _CHLGETXT_IE_\t\t\t16\n#define _SUPPORTED_CH_IE_\t\t36\n#define _CH_SWTICH_ANNOUNCE_\t37\t/* Secondary Channel Offset */\n#define\t_MEAS_REQ_IE_\t\t38\n#define\t_MEAS_RSP_IE_\t\t39\n#define _RSN_IE_2_\t\t\t\t48\n#define _SSN_IE_1_\t\t\t\t\t221\n#define _ERPINFO_IE_\t\t\t42\n#define _EXT_SUPPORTEDRATES_IE_\t50\n\n#define _HT_CAPABILITY_IE_\t\t\t45\n#define _MDIE_\t\t\t\t\t54\n#define _FTIE_\t\t\t\t\t55\n#define _TIMEOUT_ITVL_IE_\t\t\t56\n#define _SRC_IE_\t\t\t\t59\n#define _HT_EXTRA_INFO_IE_\t\t\t61\n#define _HT_ADD_INFO_IE_\t\t\t61 /* _HT_EXTRA_INFO_IE_ */\n#define _WAPI_IE_\t\t\t\t68\n#define _EID_RRM_EN_CAP_IE_\t\t\t70\n\n\n/* #define EID_BSSCoexistence\t\t\t72 */ /* 20/40 BSS Coexistence\n * #define EID_BSSIntolerantChlReport\t73 */\n#define _RIC_Descriptor_IE_\t\t\t75\n#ifdef CONFIG_IEEE80211W\n#define _MME_IE_\t\t\t\t\t76 /* 802.11w Management MIC element */\n#endif /* CONFIG_IEEE80211W */\n#define _LINK_ID_IE_\t\t\t\t\t101\n#define _CH_SWITCH_TIMING_\t\t104\n#define _PTI_BUFFER_STATUS_\t\t106\n#define _EXT_CAP_IE_\t\t\t\t127\n#define _VENDOR_SPECIFIC_IE_\t\t221\n\n#define\t_RESERVED47_\t\t\t\t47\n\ntypedef\tenum _ELEMENT_ID {\n\tEID_SsId\t\t\t\t\t= 0, /* service set identifier (0:32) */\n\tEID_SupRates\t\t\t\t= 1, /* supported rates (1:8) */\n\tEID_FHParms\t\t\t\t= 2, /* FH parameter set (5) */\n\tEID_DSParms\t\t\t\t= 3, /* DS parameter set (1) */\n\tEID_CFParms\t\t\t\t= 4, /* CF parameter set (6) */\n\tEID_Tim\t\t\t\t\t\t= 5, /* Traffic Information Map (4:254) */\n\tEID_IbssParms\t\t\t\t= 6, /* IBSS parameter set (2) */\n\tEID_Country\t\t\t\t\t= 7, /* */\n\n\t/* Form 7.3.2: Information elements in 802.11E/D13.0, page 46. */\n\tEID_QBSSLoad\t\t\t\t= 11,\n\tEID_EDCAParms\t\t\t\t= 12,\n\tEID_TSpec\t\t\t\t\t= 13,\n\tEID_TClass\t\t\t\t\t= 14,\n\tEID_Schedule\t\t\t\t= 15,\n\t/*  */\n\n\tEID_Ctext\t\t\t\t\t= 16, /* challenge text*/\n\tEID_POWER_CONSTRAINT\t\t= 32, /* Power Constraint*/\n\n\t/* vivi for WIFITest, 802.11h AP, 20100427 */\n\t/* 2010/12/26 MH The definition we can declare always!! */\n\tEID_PowerCap\t\t\t\t= 33,\n\tEID_SupportedChannels\t\t= 36,\n\tEID_ChlSwitchAnnounce\t\t= 37,\n\n\tEID_MeasureRequest\t\t\t= 38, /* Measurement Request */\n\tEID_MeasureReport\t\t\t= 39, /* Measurement Report */\n\n\tEID_ERPInfo\t\t\t\t= 42,\n\n\t/* Form 7.3.2: Information elements in 802.11E/D13.0, page 46. */\n\tEID_TSDelay\t\t\t\t= 43,\n\tEID_TCLASProc\t\t\t\t= 44,\n\tEID_HTCapability\t\t\t= 45,\n\tEID_QoSCap\t\t\t\t\t= 46,\n\t/*  */\n\n\tEID_WPA2\t\t\t\t\t= 48,\n\tEID_ExtSupRates\t\t\t= 50,\n\n\tEID_FTIE\t\t\t\t\t= 55, /* Defined in 802.11r */\n\tEID_Timeout\t\t\t\t= 56, /* Defined in 802.11r */\n\n\tEID_SupRegulatory\t\t\t= 59, /* Supported Requlatory Classes 802.11y */\n\tEID_HTInfo\t\t\t\t\t= 61,\n\tEID_SecondaryChnlOffset\t\t= 62,\n\n\tEID_BSSCoexistence\t\t\t= 72, /* 20/40 BSS Coexistence */\n\tEID_BSSIntolerantChlReport\t= 73,\n\tEID_OBSS\t\t\t\t\t= 74, /* Overlapping BSS Scan Parameters */\n\n\tEID_LinkIdentifier\t\t\t= 101, /* Defined in 802.11z */\n\tEID_WakeupSchedule\t\t= 102, /* Defined in 802.11z */\n\tEID_ChnlSwitchTimeing\t\t= 104, /* Defined in 802.11z */\n\tEID_PTIControl\t\t\t\t= 105, /* Defined in 802.11z */\n\tEID_PUBufferStatus\t\t\t= 106, /* Defined in 802.11z */\n\n\tEID_EXTCapability\t\t\t= 127, /* Extended Capabilities */\n\t/* From S19:Aironet IE and S21:AP IP address IE in CCX v1.13, p16 and p18. */\n\tEID_Aironet\t\t\t\t\t= 133, /* 0x85: Aironet Element for Cisco CCX */\n\tEID_CiscoIP\t\t\t\t\t= 149, /* 0x95: IP Address IE for Cisco CCX */\n\n\tEID_CellPwr\t\t\t\t\t= 150, /* 0x96: Cell Power Limit IE. Ref. 0x96. */\n\n\tEID_CCKM\t\t\t\t\t= 156,\n\n\tEID_Vendor\t\t\t\t\t= 221, /* 0xDD: Vendor Specific */\n\n\tEID_WAPI\t\t\t\t\t= 68,\n\tEID_VHTCapability \t\t\t= 191, /* Based on 802.11ac D2.0 */\n\tEID_VHTOperation \t\t\t= 192, /* Based on 802.11ac D2.0 */\n\tEID_AID\t\t\t\t\t\t= 197, /* Based on 802.11ac D4.0 */\n\tEID_OpModeNotification\t\t= 199, /* Based on 802.11ac D3.0 */\n} ELEMENT_ID, *PELEMENT_ID;\n\n/* ---------------------------------------------------------------------------\n\t\t\t\t\tBelow is the fixed elements...\n-----------------------------------------------------------------------------*/\n#define _AUTH_ALGM_NUM_\t\t\t2\n#define _AUTH_SEQ_NUM_\t\t\t2\n#define _BEACON_ITERVAL_\t\t2\n#define _CAPABILITY_\t\t\t2\n#define _CURRENT_APADDR_\t\t6\n#define _LISTEN_INTERVAL_\t\t2\n#define _RSON_CODE_\t\t\t\t2\n#define _ASOC_ID_\t\t\t\t2\n#define _STATUS_CODE_\t\t\t2\n#define _TIMESTAMP_\t\t\t\t8\n\n#define AUTH_ODD_TO\t\t\t\t0\n#define AUTH_EVEN_TO\t\t\t1\n\n#define WLAN_ETHCONV_ENCAP\t\t1\n#define WLAN_ETHCONV_RFC1042\t2\n#define WLAN_ETHCONV_8021h\t\t3\n\n#define cap_ESS BIT(0)\n#define cap_IBSS BIT(1)\n#define cap_CFPollable BIT(2)\n#define cap_CFRequest BIT(3)\n#define cap_Privacy BIT(4)\n#define cap_ShortPremble BIT(5)\n#define cap_PBCC\tBIT(6)\n#define cap_ChAgility\tBIT(7)\n#define cap_SpecMgmt\tBIT(8)\n#define cap_QoS\tBIT(9)\n#define cap_ShortSlot\tBIT(10)\n\n/*-----------------------------------------------------------------------------\n\t\t\t\tBelow is the definition for 802.11i / 802.1x\n------------------------------------------------------------------------------*/\n#define _IEEE8021X_MGT_\t\t\t1\t\t/* WPA */\n#define _IEEE8021X_PSK_\t\t\t2\t\t/* WPA with pre-shared key */\n\n#if 0\n#define _NO_PRIVACY_\t\t\t0\n#define _WEP_40_PRIVACY_\t\t1\n#define _TKIP_PRIVACY_\t\t\t2\n#define _WRAP_PRIVACY_\t\t\t3\n#define _CCMP_PRIVACY_\t\t\t4\n#define _WEP_104_PRIVACY_\t\t5\n#define _WEP_WPA_MIXED_PRIVACY_ 6\t/*  WEP + WPA */\n#endif\n\n#define _MME_IE_LENGTH_  18\n\n/*-----------------------------------------------------------------------------\n\t\t\t\tBelow is the definition for WMM\n------------------------------------------------------------------------------*/\n#define _WMM_IE_Length_\t\t\t\t7  /* for WMM STA */\n\n\n/*-----------------------------------------------------------------------------\n\t\t\t\tBelow is the definition for 802.11n\n------------------------------------------------------------------------------*/\n\n/* #ifdef CONFIG_80211N_HT */\n\n#define set_order_bit(pbuf)\t\\\n\t\tdo\t{\t\\\n\t\t\t*(unsigned short *)(pbuf) |= cpu_to_le16(_ORDER_); \\\n\t\t} while (0)\n\n\n\n#define GetOrderBit(pbuf)\t(((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0)\n\n#define ACT_CAT_VENDOR\t\t\t\t0x7F/* 127 */\n\n/**\n * struct rtw_ieee80211_bar - HT Block Ack Request\n *\n * This structure refers to \"HT BlockAckReq\" as\n * described in 802.11n draft section 7.2.1.7.1\n */\n#if defined(PLATFORM_LINUX)\nstruct rtw_ieee80211_bar {\n\tunsigned short frame_control;\n\tunsigned short duration;\n\tunsigned char ra[6];\n\tunsigned char ta[6];\n\tunsigned short control;\n\tunsigned short start_seq_num;\n} __attribute__((packed));\n#endif\n\n/* 802.11 BAR control masks */\n#define IEEE80211_BAR_CTRL_ACK_POLICY_NORMAL     0x0000\n#define IEEE80211_BAR_CTRL_CBMTID_COMPRESSED_BA  0x0004\n\n\n#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)\n\n\n\n/**\n* struct rtw_ieee80211_ht_cap - HT capabilities\n*\n* This structure refers to \"HT capabilities element\" as\n* described in 802.11n draft section 7.3.2.52\n*/\n\nstruct rtw_ieee80211_ht_cap {\n\tunsigned short\tcap_info;\n\tunsigned char\tampdu_params_info;\n\tunsigned char\tsupp_mcs_set[16];\n\tunsigned short\textended_ht_cap_info;\n\tunsigned int\t\ttx_BF_cap_info;\n\tunsigned char\t       antenna_selection_info;\n} __attribute__((packed));\n\n/**\n * struct rtw_ieee80211_ht_cap - HT additional information\n *\n * This structure refers to \"HT information element\" as\n * described in 802.11n draft section 7.3.2.53\n */\n#ifndef CONFIG_IEEE80211_HT_ADDT_INFO\nstruct ieee80211_ht_addt_info {\n\tunsigned char\tcontrol_chan;\n\tunsigned char\t\tht_param;\n\tunsigned short\toperation_mode;\n\tunsigned short\tstbc_param;\n\tunsigned char\t\tbasic_set[16];\n} __attribute__((packed));\n#endif\n\nstruct HT_caps_element {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned short\tHT_caps_info;\n\t\t\tunsigned char\tAMPDU_para;\n\t\t\tunsigned char\tMCS_rate[16];\n\t\t\tunsigned short\tHT_ext_caps;\n\t\t\tunsigned int\tBeamforming_caps;\n\t\t\tunsigned char\tASEL_caps;\n\t\t} HT_cap_element;\n\t\tunsigned char HT_cap[26];\n\t} u;\n} __attribute__((packed));\n\nstruct HT_info_element {\n\tunsigned char\tprimary_channel;\n\tunsigned char\tinfos[5];\n\tunsigned char\tMCS_rate[16];\n}  __attribute__((packed));\n\nstruct AC_param {\n\tunsigned char\t\tACI_AIFSN;\n\tunsigned char\t\tCW;\n\tunsigned short\tTXOP_limit;\n}  __attribute__((packed));\n\nstruct WMM_para_element {\n\tunsigned char\t\tQoS_info;\n\tunsigned char\t\treserved;\n\tstruct AC_param\tac_param[4];\n}  __attribute__((packed));\n\nstruct ADDBA_request {\n\tunsigned char\t\tdialog_token;\n\tunsigned short\tBA_para_set;\n\tunsigned short\tBA_timeout_value;\n\tunsigned short\tBA_starting_seqctrl;\n}  __attribute__((packed));\n\n\n\n#endif\n\n\ntypedef enum _HT_CAP_AMPDU_FACTOR {\n\tMAX_AMPDU_FACTOR_8K\t\t= 0,\n\tMAX_AMPDU_FACTOR_16K\t= 1,\n\tMAX_AMPDU_FACTOR_32K\t= 2,\n\tMAX_AMPDU_FACTOR_64K\t= 3,\n} HT_CAP_AMPDU_FACTOR;\n\ntypedef enum _VHT_CAP_AMPDU_FACTOR {\n\tMAX_AMPDU_FACTOR_128K = 4,\n\tMAX_AMPDU_FACTOR_256K = 5,\n\tMAX_AMPDU_FACTOR_512K = 6,\n\tMAX_AMPDU_FACTOR_1M = 7,\n} VHT_CAP_AMPDU_FACTOR;\n\n\ntypedef enum _HT_CAP_AMPDU_DENSITY {\n\tAMPDU_DENSITY_VALUE_0 = 0 , /* For no restriction */\n\tAMPDU_DENSITY_VALUE_1 = 1 , /* For 1/4 us */\n\tAMPDU_DENSITY_VALUE_2 = 2 , /* For 1/2 us */\n\tAMPDU_DENSITY_VALUE_3 = 3 , /* For 1 us */\n\tAMPDU_DENSITY_VALUE_4 = 4 , /* For 2 us */\n\tAMPDU_DENSITY_VALUE_5 = 5 , /* For 4 us */\n\tAMPDU_DENSITY_VALUE_6 = 6 , /* For 8 us */\n\tAMPDU_DENSITY_VALUE_7 = 7 , /* For 16 us */\n} HT_CAP_AMPDU_DENSITY;\n\n/* 802.11n HT capabilities masks */\n#define IEEE80211_HT_CAP_LDPC_CODING\t\t0x0001\n#define IEEE80211_HT_CAP_SUP_WIDTH\t\t0x0002\n#define IEEE80211_HT_CAP_SM_PS\t\t\t0x000C\n#define IEEE80211_HT_CAP_GRN_FLD\t\t0x0010\n#define IEEE80211_HT_CAP_SGI_20\t\t\t0x0020\n#define IEEE80211_HT_CAP_SGI_40\t\t\t0x0040\n#define IEEE80211_HT_CAP_TX_STBC\t\t\t0x0080\n#define IEEE80211_HT_CAP_RX_STBC_1R\t\t0x0100\n#define IEEE80211_HT_CAP_RX_STBC_2R\t\t0x0200\n#define IEEE80211_HT_CAP_RX_STBC_3R\t\t0x0300\n#define IEEE80211_HT_CAP_DELAY_BA\t\t0x0400\n#define IEEE80211_HT_CAP_MAX_AMSDU\t\t0x0800\n#define IEEE80211_HT_CAP_DSSSCCK40\t\t0x1000\n#define RTW_IEEE80211_HT_CAP_40MHZ_INTOLERANT\t((u16) BIT(14))\n/* 802.11n HT capability AMPDU settings */\n#define IEEE80211_HT_CAP_AMPDU_FACTOR\t\t0x03\n#define IEEE80211_HT_CAP_AMPDU_DENSITY\t\t0x1C\n/* 802.11n HT capability MSC set */\n#define IEEE80211_SUPP_MCS_SET_UEQM\t\t4\n#define IEEE80211_HT_CAP_MAX_STREAMS\t\t4\n#define IEEE80211_SUPP_MCS_SET_LEN\t\t10\n/* maximum streams the spec allows */\n#define IEEE80211_HT_CAP_MCS_TX_DEFINED\t\t0x01\n#define IEEE80211_HT_CAP_MCS_TX_RX_DIFF\t\t0x02\n#define IEEE80211_HT_CAP_MCS_TX_STREAMS\t\t0x0C\n#define IEEE80211_HT_CAP_MCS_TX_UEQM\t\t0x10\n/* 802.11n HT capability TXBF capability */\n#define IEEE80211_HT_CAP_TXBF_RX_NDP\t\t0x00000008\n#define IEEE80211_HT_CAP_TXBF_TX_NDP\t\t0x00000010\n#define IEEE80211_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP\t0x00000400\n\n/* 802.11n HT IE masks */\n#define IEEE80211_HT_IE_CHA_SEC_OFFSET\t\t0x03\n#define IEEE80211_HT_IE_CHA_SEC_NONE\t\t0x00\n#define IEEE80211_HT_IE_CHA_SEC_ABOVE\t\t0x01\n#define IEEE80211_HT_IE_CHA_SEC_BELOW\t\t0x03\n#define IEEE80211_HT_IE_CHA_WIDTH\t\t0x04\n#define IEEE80211_HT_IE_HT_PROTECTION\t\t0x0003\n#define IEEE80211_HT_IE_NON_GF_STA_PRSNT\t0x0004\n#define IEEE80211_HT_IE_NON_HT_STA_PRSNT\t0x0010\n\n/* block-ack parameters */\n#define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002\n#define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C\n#define RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFC0\n#define IEEE80211_DELBA_PARAM_TID_MASK 0xF000\n#define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800\n\n/*\n * A-PMDU buffer sizes\n * According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2)\n */\n#define IEEE80211_MIN_AMPDU_BUF 0x8\n#define IEEE80211_MAX_AMPDU_BUF_HT 0x40\n\n\n/* Spatial Multiplexing Power Save Modes */\n#define WLAN_HT_CAP_SM_PS_STATIC\t\t0\n#define WLAN_HT_CAP_SM_PS_DYNAMIC\t1\n#define WLAN_HT_CAP_SM_PS_INVALID\t2\n#define WLAN_HT_CAP_SM_PS_DISABLED\t3\n\n\n#define OP_MODE_PURE                    0\n#define OP_MODE_MAY_BE_LEGACY_STAS      1\n#define OP_MODE_20MHZ_HT_STA_ASSOCED    2\n#define OP_MODE_MIXED                   3\n\n#define HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK\t((u8) BIT(0) | BIT(1))\n#define HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE\t\t((u8) BIT(0))\n#define HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW\t\t((u8) BIT(0) | BIT(1))\n#define HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH\t\t((u8) BIT(2))\n#define HT_INFO_HT_PARAM_RIFS_MODE\t\t\t((u8) BIT(3))\n#define HT_INFO_HT_PARAM_CTRL_ACCESS_ONLY\t\t((u8) BIT(4))\n#define HT_INFO_HT_PARAM_SRV_INTERVAL_GRANULARITY\t((u8) BIT(5))\n\n#define HT_INFO_OPERATION_MODE_OP_MODE_MASK\t\\\n\t((u16) (0x0001 | 0x0002))\n#define HT_INFO_OPERATION_MODE_OP_MODE_OFFSET\t\t0\n#define HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT\t((u8) BIT(2))\n#define HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT\t((u8) BIT(3))\n#define HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT\t((u8) BIT(4))\n\n#define HT_INFO_STBC_PARAM_DUAL_BEACON\t\t\t((u16) BIT(6))\n#define HT_INFO_STBC_PARAM_DUAL_STBC_PROTECT\t\t((u16) BIT(7))\n#define HT_INFO_STBC_PARAM_SECONDARY_BCN\t\t((u16) BIT(8))\n#define HT_INFO_STBC_PARAM_LSIG_TXOP_PROTECT_ALLOWED\t((u16) BIT(9))\n#define HT_INFO_STBC_PARAM_PCO_ACTIVE\t\t\t((u16) BIT(10))\n#define HT_INFO_STBC_PARAM_PCO_PHASE\t\t\t((u16) BIT(11))\n\n\n\n/* #endif */\n\n/*\t===============WPS Section=============== */\n/*\tFor WPSv1.0 */\n#define WPSOUI\t\t\t\t\t\t\t0x0050f204\n/*\tWPS attribute ID */\n#define WPS_ATTR_VER1\t\t\t\t\t0x104A\n#define WPS_ATTR_SIMPLE_CONF_STATE\t0x1044\n#define WPS_ATTR_RESP_TYPE\t\t\t0x103B\n#define WPS_ATTR_UUID_E\t\t\t\t0x1047\n#define WPS_ATTR_MANUFACTURER\t\t0x1021\n#define WPS_ATTR_MODEL_NAME\t\t\t0x1023\n#define WPS_ATTR_MODEL_NUMBER\t\t0x1024\n#define WPS_ATTR_SERIAL_NUMBER\t\t0x1042\n#define WPS_ATTR_PRIMARY_DEV_TYPE\t0x1054\n#define WPS_ATTR_SEC_DEV_TYPE_LIST\t0x1055\n#define WPS_ATTR_DEVICE_NAME\t\t\t0x1011\n#define WPS_ATTR_CONF_METHOD\t\t\t0x1008\n#define WPS_ATTR_RF_BANDS\t\t\t\t0x103C\n#define WPS_ATTR_DEVICE_PWID\t\t\t0x1012\n#define WPS_ATTR_REQUEST_TYPE\t\t\t0x103A\n#define WPS_ATTR_ASSOCIATION_STATE\t0x1002\n#define WPS_ATTR_CONFIG_ERROR\t\t\t0x1009\n#define WPS_ATTR_VENDOR_EXT\t\t\t0x1049\n#define WPS_ATTR_SELECTED_REGISTRAR\t0x1041\n\n/*\tValue of WPS attribute \"WPS_ATTR_DEVICE_NAME */\n#define WPS_MAX_DEVICE_NAME_LEN\t\t32\n\n/*\tValue of WPS Request Type Attribute */\n#define WPS_REQ_TYPE_ENROLLEE_INFO_ONLY\t\t\t0x00\n#define WPS_REQ_TYPE_ENROLLEE_OPEN_8021X\t\t0x01\n#define WPS_REQ_TYPE_REGISTRAR\t\t\t\t\t0x02\n#define WPS_REQ_TYPE_WLAN_MANAGER_REGISTRAR\t0x03\n\n/*\tValue of WPS Response Type Attribute */\n#define WPS_RESPONSE_TYPE_INFO_ONLY\t0x00\n#define WPS_RESPONSE_TYPE_8021X\t\t0x01\n#define WPS_RESPONSE_TYPE_REGISTRAR\t0x02\n#define WPS_RESPONSE_TYPE_AP\t\t\t0x03\n\n/*\tValue of WPS WiFi Simple Configuration State Attribute */\n#define WPS_WSC_STATE_NOT_CONFIG\t0x01\n#define WPS_WSC_STATE_CONFIG\t\t\t0x02\n\n/*\tValue of WPS Version Attribute */\n#define WPS_VERSION_1\t\t\t\t\t0x10\n\n/*\tValue of WPS Configuration Method Attribute */\n#define WPS_CONFIG_METHOD_FLASH\t\t0x0001\n#define WPS_CONFIG_METHOD_ETHERNET\t0x0002\n#define WPS_CONFIG_METHOD_LABEL\t\t0x0004\n#define WPS_CONFIG_METHOD_DISPLAY\t0x0008\n#define WPS_CONFIG_METHOD_E_NFC\t\t0x0010\n#define WPS_CONFIG_METHOD_I_NFC\t\t0x0020\n#define WPS_CONFIG_METHOD_NFC\t\t0x0040\n#define WPS_CONFIG_METHOD_PBC\t\t0x0080\n#define WPS_CONFIG_METHOD_KEYPAD\t0x0100\n#define WPS_CONFIG_METHOD_VPBC\t\t0x0280\n#define WPS_CONFIG_METHOD_PPBC\t\t0x0480\n#define WPS_CONFIG_METHOD_VDISPLAY\t0x2008\n#define WPS_CONFIG_METHOD_PDISPLAY\t0x4008\n\n/*\tValue of Category ID of WPS Primary Device Type Attribute */\n#define WPS_PDT_CID_DISPLAYS\t\t\t0x0007\n#define WPS_PDT_CID_MULIT_MEDIA\t\t0x0008\n#define WPS_PDT_CID_RTK_WIDI\t\t\tWPS_PDT_CID_MULIT_MEDIA\n\n/*\tValue of Sub Category ID of WPS Primary Device Type Attribute */\n#define WPS_PDT_SCID_MEDIA_SERVER\t0x0005\n#define WPS_PDT_SCID_RTK_DMP\t\t\tWPS_PDT_SCID_MEDIA_SERVER\n\n/*\tValue of Device Password ID */\n#define WPS_DPID_PIN\t\t\t\t\t0x0000\n#define WPS_DPID_USER_SPEC\t\t\t0x0001\n#define WPS_DPID_MACHINE_SPEC\t\t\t0x0002\n#define WPS_DPID_REKEY\t\t\t\t\t0x0003\n#define WPS_DPID_PBC\t\t\t\t\t0x0004\n#define WPS_DPID_REGISTRAR_SPEC\t\t0x0005\n\n/*\tValue of WPS RF Bands Attribute */\n#define WPS_RF_BANDS_2_4_GHZ\t\t0x01\n#define WPS_RF_BANDS_5_GHZ\t\t0x02\n\n/*\tValue of WPS Association State Attribute */\n#define WPS_ASSOC_STATE_NOT_ASSOCIATED\t\t\t0x00\n#define WPS_ASSOC_STATE_CONNECTION_SUCCESS\t\t0x01\n#define WPS_ASSOC_STATE_CONFIGURATION_FAILURE\t0x02\n#define WPS_ASSOC_STATE_ASSOCIATION_FAILURE\t\t0x03\n#define WPS_ASSOC_STATE_IP_FAILURE\t\t\t\t0x04\n\n/*\t=====================P2P Section===================== */\n/*\tFor P2P */\n#define\tP2POUI\t\t\t\t\t\t\t0x506F9A09\n\n/*\tP2P Attribute ID */\n#define\tP2P_ATTR_STATUS\t\t\t\t\t0x00\n#define\tP2P_ATTR_MINOR_REASON_CODE\t\t0x01\n#define\tP2P_ATTR_CAPABILITY\t\t\t\t0x02\n#define\tP2P_ATTR_DEVICE_ID\t\t\t\t0x03\n#define\tP2P_ATTR_GO_INTENT\t\t\t\t0x04\n#define\tP2P_ATTR_CONF_TIMEOUT\t\t\t0x05\n#define\tP2P_ATTR_LISTEN_CH\t\t\t\t0x06\n#define\tP2P_ATTR_GROUP_BSSID\t\t\t\t0x07\n#define\tP2P_ATTR_EX_LISTEN_TIMING\t\t0x08\n#define\tP2P_ATTR_INTENDED_IF_ADDR\t\t0x09\n#define\tP2P_ATTR_MANAGEABILITY\t\t\t0x0A\n#define\tP2P_ATTR_CH_LIST\t\t\t\t\t0x0B\n#define\tP2P_ATTR_NOA\t\t\t\t\t\t0x0C\n#define\tP2P_ATTR_DEVICE_INFO\t\t\t\t0x0D\n#define\tP2P_ATTR_GROUP_INFO\t\t\t\t0x0E\n#define\tP2P_ATTR_GROUP_ID\t\t\t\t\t0x0F\n#define\tP2P_ATTR_INTERFACE\t\t\t\t0x10\n#define\tP2P_ATTR_OPERATING_CH\t\t\t0x11\n#define\tP2P_ATTR_INVITATION_FLAGS\t\t0x12\n\n/*\tValue of Status Attribute */\n#define\tP2P_STATUS_SUCCESS\t\t\t\t\t\t0x00\n#define\tP2P_STATUS_FAIL_INFO_UNAVAILABLE\t\t0x01\n#define\tP2P_STATUS_FAIL_INCOMPATIBLE_PARAM\t\t0x02\n#define\tP2P_STATUS_FAIL_LIMIT_REACHED\t\t\t0x03\n#define\tP2P_STATUS_FAIL_INVALID_PARAM\t\t\t0x04\n#define\tP2P_STATUS_FAIL_REQUEST_UNABLE\t\t\t0x05\n#define\tP2P_STATUS_FAIL_PREVOUS_PROTO_ERR\t\t0x06\n#define\tP2P_STATUS_FAIL_NO_COMMON_CH\t\t\t0x07\n#define\tP2P_STATUS_FAIL_UNKNOWN_P2PGROUP\t\t0x08\n#define\tP2P_STATUS_FAIL_BOTH_GOINTENT_15\t\t0x09\n#define\tP2P_STATUS_FAIL_INCOMPATIBLE_PROVSION\t0x0A\n#define\tP2P_STATUS_FAIL_USER_REJECT\t\t\t\t0x0B\n\n/*\tValue of Inviation Flags Attribute */\n#define\tP2P_INVITATION_FLAGS_PERSISTENT\t\t\tBIT(0)\n\n#define\tDMP_P2P_DEVCAP_SUPPORT\t(P2P_DEVCAP_SERVICE_DISCOVERY | \\\n\t\t\t\t P2P_DEVCAP_CLIENT_DISCOVERABILITY | \\\n\t\t\t\t P2P_DEVCAP_CONCURRENT_OPERATION | \\\n\t\t\t\t P2P_DEVCAP_INVITATION_PROC)\n\n#define\tDMP_P2P_GRPCAP_SUPPORT\t(P2P_GRPCAP_INTRABSS)\n\n/*\tValue of Device Capability Bitmap */\n#define\tP2P_DEVCAP_SERVICE_DISCOVERY\t\tBIT(0)\n#define\tP2P_DEVCAP_CLIENT_DISCOVERABILITY\tBIT(1)\n#define\tP2P_DEVCAP_CONCURRENT_OPERATION\tBIT(2)\n#define\tP2P_DEVCAP_INFRA_MANAGED\t\t\tBIT(3)\n#define\tP2P_DEVCAP_DEVICE_LIMIT\t\t\t\tBIT(4)\n#define\tP2P_DEVCAP_INVITATION_PROC\t\t\tBIT(5)\n\n/*\tValue of Group Capability Bitmap */\n#define\tP2P_GRPCAP_GO\t\t\t\t\t\t\tBIT(0)\n#define\tP2P_GRPCAP_PERSISTENT_GROUP\t\t\tBIT(1)\n#define\tP2P_GRPCAP_GROUP_LIMIT\t\t\t\tBIT(2)\n#define\tP2P_GRPCAP_INTRABSS\t\t\t\t\tBIT(3)\n#define\tP2P_GRPCAP_CROSS_CONN\t\t\t\tBIT(4)\n#define\tP2P_GRPCAP_PERSISTENT_RECONN\t\tBIT(5)\n#define\tP2P_GRPCAP_GROUP_FORMATION\t\t\tBIT(6)\n\n/*\tP2P Public Action Frame ( Management Frame ) */\n#define\tP2P_PUB_ACTION_ACTION\t\t\t\t0x09\n\n/*\tP2P Public Action Frame Type */\n#define\tP2P_GO_NEGO_REQ\t\t\t\t\t\t0\n#define\tP2P_GO_NEGO_RESP\t\t\t\t\t\t1\n#define\tP2P_GO_NEGO_CONF\t\t\t\t\t\t2\n#define\tP2P_INVIT_REQ\t\t\t\t\t\t\t3\n#define\tP2P_INVIT_RESP\t\t\t\t\t\t\t4\n#define\tP2P_DEVDISC_REQ\t\t\t\t\t\t5\n#define\tP2P_DEVDISC_RESP\t\t\t\t\t\t6\n#define\tP2P_PROVISION_DISC_REQ\t\t\t\t7\n#define\tP2P_PROVISION_DISC_RESP\t\t\t\t8\n\n/*\tP2P Action Frame Type */\n#define\tP2P_NOTICE_OF_ABSENCE\t0\n#define\tP2P_PRESENCE_REQUEST\t\t1\n#define\tP2P_PRESENCE_RESPONSE\t2\n#define\tP2P_GO_DISC_REQUEST\t\t3\n\n\n#define\tP2P_MAX_PERSISTENT_GROUP_NUM\t\t10\n\n#define\tP2P_PROVISIONING_SCAN_CNT\t\t\t3\n\n#define\tP2P_WILDCARD_SSID_LEN\t\t\t\t7\n\n#define\tP2P_FINDPHASE_EX_NONE\t\t\t\t0\t/* default value, used when: (1)p2p disabed or (2)p2p enabled but only do 1 scan phase */\n#define\tP2P_FINDPHASE_EX_FULL\t\t\t\t1\t/* used when p2p enabled and want to do 1 scan phase and P2P_FINDPHASE_EX_MAX-1 find phase */\n#define\tP2P_FINDPHASE_EX_SOCIAL_FIRST\t\t(P2P_FINDPHASE_EX_FULL+1)\n#define\tP2P_FINDPHASE_EX_MAX\t\t\t\t\t4\n#define\tP2P_FINDPHASE_EX_SOCIAL_LAST\t\tP2P_FINDPHASE_EX_MAX\n\n#define\tP2P_PROVISION_TIMEOUT\t\t\t\t5000\t/*\t5 seconds timeout for sending the provision discovery request */\n#define\tP2P_CONCURRENT_PROVISION_TIMEOUT\t3000\t/*\t3 seconds timeout for sending the provision discovery request under concurrent mode */\n#define\tP2P_GO_NEGO_TIMEOUT\t\t\t\t\t5000\t/*\t5 seconds timeout for receiving the group negotation response */\n#define\tP2P_CONCURRENT_GO_NEGO_TIMEOUT\t\t3000\t/*\t3 seconds timeout for sending the negotiation request under concurrent mode */\n#define\tP2P_TX_PRESCAN_TIMEOUT\t\t\t\t100\t\t/*\t100ms */\n#define\tP2P_INVITE_TIMEOUT\t\t\t\t\t5000\t/*\t5 seconds timeout for sending the invitation request */\n#define\tP2P_CONCURRENT_INVITE_TIMEOUT\t\t3000\t/*\t3 seconds timeout for sending the invitation request under concurrent mode */\n#define\tP2P_RESET_SCAN_CH\t\t\t\t\t\t25000\t/*\t25 seconds timeout to reset the scan channel (based on channel plan) */\n#define\tP2P_MAX_INTENT\t\t\t\t\t\t15\n\n#define\tP2P_MAX_NOA_NUM\t\t\t\t\t\t2\n\n/*\tWPS Configuration Method */\n#define\tWPS_CM_NONE\t\t\t\t\t\t\t0x0000\n#define\tWPS_CM_LABEL\t\t\t\t\t\t\t0x0004\n#define\tWPS_CM_DISPLYA\t\t\t\t\t\t0x0008\n#define\tWPS_CM_EXTERNAL_NFC_TOKEN\t\t\t0x0010\n#define\tWPS_CM_INTEGRATED_NFC_TOKEN\t\t0x0020\n#define\tWPS_CM_NFC_INTERFACE\t\t\t\t\t0x0040\n#define\tWPS_CM_PUSH_BUTTON\t\t\t\t\t0x0080\n#define\tWPS_CM_KEYPAD\t\t\t\t\t\t0x0100\n#define\tWPS_CM_SW_PUHS_BUTTON\t\t\t\t0x0280\n#define\tWPS_CM_HW_PUHS_BUTTON\t\t\t\t0x0480\n#define\tWPS_CM_SW_DISPLAY_PIN\t\t\t\t0x2008\n#define\tWPS_CM_LCD_DISPLAY_PIN\t\t\t\t0x4008\n\nenum P2P_ROLE {\n\tP2P_ROLE_DISABLE = 0,\n\tP2P_ROLE_DEVICE = 1,\n\tP2P_ROLE_CLIENT = 2,\n\tP2P_ROLE_GO = 3\n};\n\nenum P2P_STATE {\n\tP2P_STATE_NONE = 0,\t\t\t\t\t\t\t/*\tP2P disable */\n\tP2P_STATE_IDLE = 1,\t\t\t\t\t\t\t\t/*\tP2P had enabled and do nothing ,  buddy adapters is linked */\n\tP2P_STATE_LISTEN = 2,\t\t\t\t\t\t\t/*\tIn pure listen state */\n\tP2P_STATE_SCAN = 3,\t\t\t\t\t\t\t/*\tIn scan phase */\n\tP2P_STATE_FIND_PHASE_LISTEN = 4,\t\t\t\t/*\tIn the listen state of find phase */\n\tP2P_STATE_FIND_PHASE_SEARCH = 5,\t\t\t\t/*\tIn the search state of find phase */\n\tP2P_STATE_TX_PROVISION_DIS_REQ = 6,\t\t\t/*\tIn P2P provisioning discovery */\n\tP2P_STATE_RX_PROVISION_DIS_RSP = 7,\n\tP2P_STATE_RX_PROVISION_DIS_REQ = 8,\n\tP2P_STATE_GONEGO_ING = 9,\t\t\t\t\t\t/*\tDoing the group owner negoitation handshake */\n\tP2P_STATE_GONEGO_OK = 10,\t\t\t\t\t\t/*\tfinish the group negoitation handshake with success */\n\tP2P_STATE_GONEGO_FAIL = 11,\t\t\t\t\t/*\tfinish the group negoitation handshake with failure */\n\tP2P_STATE_RECV_INVITE_REQ_MATCH = 12,\t\t/*\treceiving the P2P Inviation request and match with the profile. */\n\tP2P_STATE_PROVISIONING_ING = 13,\t\t\t\t/*\tDoing the P2P WPS */\n\tP2P_STATE_PROVISIONING_DONE = 14,\t\t\t/*\tFinish the P2P WPS */\n\tP2P_STATE_TX_INVITE_REQ = 15,\t\t\t\t\t/*\tTransmit the P2P Invitation request */\n\tP2P_STATE_RX_INVITE_RESP_OK = 16,\t\t\t\t/*\tReceiving the P2P Invitation response */\n\tP2P_STATE_RECV_INVITE_REQ_DISMATCH = 17,\t/*\treceiving the P2P Inviation request and dismatch with the profile. */\n\tP2P_STATE_RECV_INVITE_REQ_GO = 18,\t\t\t/*\treceiving the P2P Inviation request and this wifi is GO. */\n\tP2P_STATE_RECV_INVITE_REQ_JOIN = 19,\t\t\t/*\treceiving the P2P Inviation request to join an existing P2P Group. */\n\tP2P_STATE_RX_INVITE_RESP_FAIL = 20,\t\t\t/*\trecveing the P2P Inviation response with failure */\n\tP2P_STATE_RX_INFOR_NOREADY = 21,\t\t\t/* receiving p2p negoitation response with information is not available */\n\tP2P_STATE_TX_INFOR_NOREADY = 22,\t\t\t/* sending p2p negoitation response with information is not available */\n};\n\nenum P2P_WPSINFO {\n\tP2P_NO_WPSINFO\t\t\t\t\t\t= 0,\n\tP2P_GOT_WPSINFO_PEER_DISPLAY_PIN\t= 1,\n\tP2P_GOT_WPSINFO_SELF_DISPLAY_PIN\t= 2,\n\tP2P_GOT_WPSINFO_PBC\t\t\t\t\t= 3,\n};\n\n#define\tP2P_PRIVATE_IOCTL_SET_LEN\t\t64\n\nenum P2P_PROTO_WK_ID {\n\tP2P_FIND_PHASE_WK = 0,\n\tP2P_RESTORE_STATE_WK = 1,\n\tP2P_PRE_TX_PROVDISC_PROCESS_WK = 2,\n\tP2P_PRE_TX_NEGOREQ_PROCESS_WK = 3,\n\tP2P_PRE_TX_INVITEREQ_PROCESS_WK = 4,\n\tP2P_AP_P2P_CH_SWITCH_PROCESS_WK = 5,\n\tP2P_RO_CH_WK = 6,\n\tP2P_CANCEL_RO_CH_WK = 7,\n};\n\n#ifdef CONFIG_P2P_PS\nenum P2P_PS_STATE {\n\tP2P_PS_DISABLE = 0,\n\tP2P_PS_ENABLE = 1,\n\tP2P_PS_SCAN = 2,\n\tP2P_PS_SCAN_DONE = 3,\n\tP2P_PS_ALLSTASLEEP = 4, /* for P2P GO */\n};\n\nenum P2P_PS_MODE {\n\tP2P_PS_NONE = 0,\n\tP2P_PS_CTWINDOW = 1,\n\tP2P_PS_NOA\t = 2,\n\tP2P_PS_MIX = 3, /* CTWindow and NoA */\n};\n#endif /* CONFIG_P2P_PS */\n\n/*\t=====================WFD Section=====================\n *\tFor Wi-Fi Display */\n#define\tWFD_ATTR_DEVICE_INFO\t\t\t0x00\n#define\tWFD_ATTR_ASSOC_BSSID\t\t\t0x01\n#define\tWFD_ATTR_COUPLED_SINK_INFO\t0x06\n#define\tWFD_ATTR_LOCAL_IP_ADDR\t\t0x08\n#define\tWFD_ATTR_SESSION_INFO\t\t0x09\n#define\tWFD_ATTR_ALTER_MAC\t\t\t0x0a\n\n/*\tFor WFD Device Information Attribute */\n#define\tWFD_DEVINFO_SOURCE\t\t\t\t\t0x0000\n#define\tWFD_DEVINFO_PSINK\t\t\t\t\t0x0001\n#define\tWFD_DEVINFO_SSINK\t\t\t\t\t0x0002\n#define\tWFD_DEVINFO_DUAL\t\t\t\t\t0x0003\n\n#define\tWFD_DEVINFO_SESSION_AVAIL\t\t\t0x0010\n#define\tWFD_DEVINFO_WSD\t\t\t\t\t\t0x0040\n#define\tWFD_DEVINFO_PC_TDLS\t\t\t\t\t0x0080\n#define\tWFD_DEVINFO_HDCP_SUPPORT\t\t\t0x0100\n\n#define IP_MCAST_MAC(mac)\t\t((mac[0] == 0x01) && (mac[1] == 0x00) && (mac[2] == 0x5e))\n#define ICMPV6_MCAST_MAC(mac)\t((mac[0] == 0x33) && (mac[1] == 0x33) && (mac[2] != 0xff))\n\n#ifdef CONFIG_IOCTL_CFG80211\n/* Regulatroy Domain */\nstruct regd_pair_mapping {\n\tu16 reg_dmnenum;\n\tu16 reg_5ghz_ctl;\n\tu16 reg_2ghz_ctl;\n};\n\nstruct rtw_regulatory {\n\tchar alpha2[2];\n\tu16 country_code;\n\tu16 max_power_level;\n\tu32 tp_scale;\n\tu16 current_rd;\n\tu16 current_rd_ext;\n\tint16_t power_limit;\n\tstruct regd_pair_mapping *regpair;\n};\n#endif\n\n#ifdef CONFIG_WAPI_SUPPORT\n#ifndef IW_AUTH_WAPI_VERSION_1\n#define IW_AUTH_WAPI_VERSION_1\t\t0x00000008\n#endif\n#ifndef IW_AUTH_KEY_MGMT_WAPI_PSK\n#define IW_AUTH_KEY_MGMT_WAPI_PSK\t0x04\n#endif\n#ifndef IW_AUTH_WAPI_ENABLED\n#define IW_AUTH_WAPI_ENABLED\t\t0x20\n#endif\n#ifndef IW_ENCODE_ALG_SM4\n#define IW_ENCODE_ALG_SM4\t\t\t0x20\n#endif\n#endif\n\n#endif /* _WIFI_H_ */\n"
  },
  {
    "path": "include/wlan_bssdef.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __WLAN_BSSDEF_H__\n#define __WLAN_BSSDEF_H__\n\n\n#define MAX_IE_SZ\t768\n\n\n#ifdef PLATFORM_LINUX\n\n#define NDIS_802_11_LENGTH_SSID         32\n#define NDIS_802_11_LENGTH_RATES        8\n#define NDIS_802_11_LENGTH_RATES_EX     16\n\ntypedef unsigned char   NDIS_802_11_MAC_ADDRESS[ETH_ALEN];\ntypedef long    \t\tNDIS_802_11_RSSI;           /* in dBm */\ntypedef unsigned char   NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES];        /* Set of 8 data rates */\ntypedef unsigned char   NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX];  /* Set of 16 data rates */\n\ntypedef struct _NDIS_802_11_SSID {\n\tu32  SsidLength;\n\tu8  Ssid[32];\n} NDIS_802_11_SSID, *PNDIS_802_11_SSID;\n\n/*\n\tFW will only save the channel number in DSConfig.\n\tODI Handler will convert the channel number to freq. number.\n*/\ntypedef struct _NDIS_802_11_CONFIGURATION {\n\tu32           Length;             /* Length of structure */\n\tu32           BeaconPeriod;       /* units are Kusec */\n\tu32           ATIMWindow;         /* units are Kusec */\n\tu32           DSConfig;           /* channel number */\n} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION;\n\ntypedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE {\n\tNdis802_11IBSS,\n\tNdis802_11Infrastructure,\n\tNdis802_11AutoUnknown,\n\tNdis802_11InfrastructureMax,     /* Not a real value, defined as upper bound */\n\tNdis802_11APMode,\n\tNdis802_11Monitor,\n\tNdis802_11_mesh,\n} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE;\n\ntypedef struct _NDIS_802_11_FIXED_IEs {\n\tu8  Timestamp[8];\n\tu16  BeaconInterval;\n\tu16  Capabilities;\n} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs;\n\ntypedef struct _NDIS_802_11_VARIABLE_IEs {\n\tu8  ElementID;\n\tu8  Length;\n\tu8  data[1];\n} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs;\n\ntypedef enum _NDIS_802_11_AUTHENTICATION_MODE {\n\tNdis802_11AuthModeOpen,\n\tNdis802_11AuthModeShared,\n\tNdis802_11AuthModeAutoSwitch,\n\tNdis802_11AuthModeWPA,\n\tNdis802_11AuthModeWPAPSK,\n\tNdis802_11AuthModeWPANone,\n\tNdis802_11AuthModeWAPI,\n\tNdis802_11AuthModeMax               /* Not a real mode, defined as upper bound */\n} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE;\n\ntypedef enum _NDIS_802_11_WEP_STATUS {\n\tNdis802_11WEPEnabled,\n\tNdis802_11Encryption1Enabled = Ndis802_11WEPEnabled,\n\tNdis802_11WEPDisabled,\n\tNdis802_11EncryptionDisabled = Ndis802_11WEPDisabled,\n\tNdis802_11WEPKeyAbsent,\n\tNdis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent,\n\tNdis802_11WEPNotSupported,\n\tNdis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported,\n\tNdis802_11Encryption2Enabled,\n\tNdis802_11Encryption2KeyAbsent,\n\tNdis802_11Encryption3Enabled,\n\tNdis802_11Encryption3KeyAbsent,\n\tNdis802_11_EncrypteionWAPI\n} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS,\nNDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS;\n\ntypedef struct _NDIS_802_11_WEP {\n\tu32     Length;        /* Length of this structure */\n\tu32     KeyIndex;      /* 0 is the per-client key, 1-N are the global keys */\n\tu32     KeyLength;     /* length of key in bytes */\n\tu8     KeyMaterial[16];/* variable length depending on above field */\n} NDIS_802_11_WEP, *PNDIS_802_11_WEP;\n\n#endif /* end of #ifdef PLATFORM_LINUX */\n\n#ifdef PLATFORM_FREEBSD\n\n#define NDIS_802_11_LENGTH_SSID         32\n#define NDIS_802_11_LENGTH_RATES        8\n#define NDIS_802_11_LENGTH_RATES_EX     16\n\ntypedef unsigned char   NDIS_802_11_MAC_ADDRESS[ETH_ALEN];\ntypedef long    \t\tNDIS_802_11_RSSI;           /* in dBm */\ntypedef unsigned char   NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES];        /* Set of 8 data rates */\ntypedef unsigned char   NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX];  /* Set of 16 data rates */\n\n\ntypedef struct _NDIS_802_11_SSID {\n\tu32  SsidLength;\n\tu8  Ssid[32];\n} NDIS_802_11_SSID, *PNDIS_802_11_SSID;\n\n/*\n\tFW will only save the channel number in DSConfig.\n\tODI Handler will convert the channel number to freq. number.\n*/\ntypedef struct _NDIS_802_11_CONFIGURATION {\n\tu32           Length;             /* Length of structure */\n\tu32           BeaconPeriod;       /* units are Kusec */\n\tu32           ATIMWindow;         /* units are Kusec */\n\tu32           DSConfig;           /* channel number */\n} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION;\n\ntypedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE {\n\tNdis802_11IBSS,\n\tNdis802_11Infrastructure,\n\tNdis802_11AutoUnknown,\n\tNdis802_11InfrastructureMax,     /* Not a real value, defined as upper bound */\n\tNdis802_11APMode\n} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE;\n\ntypedef struct _NDIS_802_11_FIXED_IEs {\n\tu8  Timestamp[8];\n\tu16  BeaconInterval;\n\tu16  Capabilities;\n} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs;\n\ntypedef struct _NDIS_802_11_VARIABLE_IEs {\n\tu8  ElementID;\n\tu8  Length;\n\tu8  data[1];\n} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs;\n\ntypedef enum _NDIS_802_11_AUTHENTICATION_MODE {\n\tNdis802_11AuthModeOpen,\n\tNdis802_11AuthModeShared,\n\tNdis802_11AuthModeAutoSwitch,\n\tNdis802_11AuthModeWPA,\n\tNdis802_11AuthModeWPAPSK,\n\tNdis802_11AuthModeWPANone,\n\tNdis802_11AuthModeMax               /* Not a real mode, defined as upper bound */\n} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE;\n\ntypedef enum _NDIS_802_11_WEP_STATUS {\n\tNdis802_11WEPEnabled,\n\tNdis802_11Encryption1Enabled = Ndis802_11WEPEnabled,\n\tNdis802_11WEPDisabled,\n\tNdis802_11EncryptionDisabled = Ndis802_11WEPDisabled,\n\tNdis802_11WEPKeyAbsent,\n\tNdis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent,\n\tNdis802_11WEPNotSupported,\n\tNdis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported,\n\tNdis802_11Encryption2Enabled,\n\tNdis802_11Encryption2KeyAbsent,\n\tNdis802_11Encryption3Enabled,\n\tNdis802_11Encryption3KeyAbsent\n} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS,\nNDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS;\n\n\ntypedef struct _NDIS_802_11_WEP {\n\tu32     Length;        /* Length of this structure */\n\tu32     KeyIndex;      /* 0 is the per-client key, 1-N are the global keys */\n\tu32     KeyLength;     /* length of key in bytes */\n\tu8     KeyMaterial[16];/* variable length depending on above field */\n} NDIS_802_11_WEP, *PNDIS_802_11_WEP;\n\n#endif /* PLATFORM_FREEBSD */\n\n#ifndef Ndis802_11APMode\n#define Ndis802_11APMode (Ndis802_11InfrastructureMax+1)\n#endif\n\ntypedef struct _WLAN_PHY_INFO {\n\tu8\tSignalStrength;/* (in percentage) */\n\tu8\tSignalQuality;/* (in percentage) */\n\tu8\tOptimum_antenna;  /* for Antenna diversity */\n\tu8\tis_cck_rate;\t/* 1:cck_rate */\n\ts8\trx_snr[4];\n#ifdef CONFIG_RTW_80211K\n\tu32\tfree_cnt; \t/* freerun counter */\n\tu8\trm_en_cap[5];\n#endif\n} WLAN_PHY_INFO, *PWLAN_PHY_INFO;\n\ntypedef struct _WLAN_BCN_INFO {\n\t/* these infor get from rtw_get_encrypt_info when\n\t *\t * translate scan to UI */\n\tu8 encryp_protocol;/* ENCRYP_PROTOCOL_E: OPEN/WEP/WPA/WPA2/WAPI */\n\tint group_cipher; /* WPA/WPA2 group cipher */\n\tint pairwise_cipher;/* //WPA/WPA2/WEP pairwise cipher */\n\tint is_8021x;\n\n\t/* bwmode 20/40 and ch_offset UP/LOW */\n\tunsigned short\tht_cap_info;\n\tunsigned char\tht_info_infos_0;\n} WLAN_BCN_INFO, *PWLAN_BCN_INFO;\n\nenum bss_type {\n\tBSS_TYPE_UNDEF,\n\tBSS_TYPE_BCN = 1,\n\tBSS_TYPE_PROB_REQ = 2,\n\tBSS_TYPE_PROB_RSP = 3,\n};\n\n/* temporally add #pragma pack for structure alignment issue of\n*   WLAN_BSSID_EX and get_WLAN_BSSID_EX_sz()\n*/\ntypedef struct _WLAN_BSSID_EX {\n\tu32  Length;\n\tNDIS_802_11_MAC_ADDRESS  MacAddress;\n\tu8  Reserved[2];/* [0]: IS beacon frame , bss_type*/\n\tNDIS_802_11_SSID  Ssid;\n\tNDIS_802_11_SSID  mesh_id;\n\tu32  Privacy;\n\tNDIS_802_11_RSSI  Rssi;/* (in dBM,raw data ,get from PHY) */\n\tNDIS_802_11_CONFIGURATION  Configuration;\n\tNDIS_802_11_NETWORK_INFRASTRUCTURE  InfrastructureMode;\n\tNDIS_802_11_RATES_EX  SupportedRates;\n\tWLAN_PHY_INFO\tPhyInfo;\n\tu32  IELength;\n\tu8  IEs[MAX_IE_SZ];\t/* (timestamp, beacon interval, and capability information) */\n}\n__attribute__((packed)) WLAN_BSSID_EX, *PWLAN_BSSID_EX;\n\n#define BSS_EX_IES(bss_ex) ((bss_ex)->IEs)\n#define BSS_EX_IES_LEN(bss_ex) ((bss_ex)->IELength)\n#define BSS_EX_FIXED_IE_OFFSET(bss_ex) ((bss_ex)->Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12)\n#define BSS_EX_TLV_IES(bss_ex) (BSS_EX_IES((bss_ex)) + BSS_EX_FIXED_IE_OFFSET((bss_ex)))\n#define BSS_EX_TLV_IES_LEN(bss_ex) (BSS_EX_IES_LEN((bss_ex)) - BSS_EX_FIXED_IE_OFFSET((bss_ex)))\n\n__inline  static uint get_WLAN_BSSID_EX_sz(WLAN_BSSID_EX *bss)\n{\n\treturn sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + bss->IELength;\n}\n\nstruct\twlan_network {\n\t_list\tlist;\n\tint\tnetwork_type;\t/* refer to ieee80211.h for WIRELESS_11A/B/G */\n\tint\tfixed;\t\t\t/* set to fixed when not to be removed as site-surveying */\n\tsystime last_scanned; /* timestamp for the network */\n#ifdef CONFIG_RTW_MESH\n#if CONFIG_RTW_MESH_ACNODE_PREVENT\n\tsystime acnode_stime;\n\tsystime acnode_notify_etime;\n#endif\n#endif\n\tint\taid;\t\t\t/* will only be valid when a BSS is joinned. */\n\tint\tjoin_res;\n\tWLAN_BSSID_EX\tnetwork; /* must be the last item */\n};\n\nenum VRTL_CARRIER_SENSE {\n\tDISABLE_VCS,\n\tENABLE_VCS,\n\tAUTO_VCS\n};\n\nenum VCS_TYPE {\n\tNONE_VCS,\n\tRTS_CTS,\n\tCTS_TO_SELF\n};\n\n\n\n\n#define PWR_CAM 0\n#define PWR_MINPS 1\n#define PWR_MAXPS 2\n#define PWR_UAPSD 3\n#define PWR_VOIP 4\n\n\nenum UAPSD_MAX_SP {\n\tNO_LIMIT,\n\tTWO_MSDU,\n\tFOUR_MSDU,\n\tSIX_MSDU\n};\n\n\n/* john */\n#define NUM_PRE_AUTH_KEY 16\n#define NUM_PMKID_CACHE NUM_PRE_AUTH_KEY\n\n#endif /* #ifndef WLAN_BSSDEF_H_ */\n"
  },
  {
    "path": "include/xmit_osdep.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __XMIT_OSDEP_H_\n#define __XMIT_OSDEP_H_\n\n\nstruct pkt_file {\n\t_pkt *pkt;\n\tSIZE_T pkt_len;\t /* the remainder length of the open_file */\n\t_buffer *cur_buffer;\n\tu8 *buf_start;\n\tu8 *cur_addr;\n\tSIZE_T buf_len;\n};\n\n#ifdef PLATFORM_WINDOWS\n\n#ifdef PLATFORM_OS_XP\n#ifdef CONFIG_USB_HCI\n#include <usb.h>\n#include <usbdlib.h>\n#include <usbioctl.h>\n#endif\n#endif\n\n#ifdef CONFIG_GSPI_HCI\n\t#define NR_XMITFRAME     64\n#else\n\t#define NR_XMITFRAME     128\n#endif\n\n#define ETH_ALEN\t6\n\nextern NDIS_STATUS rtw_xmit_entry(\n\t_nic_hdl\t\tcnxt,\n\tNDIS_PACKET\t\t*pkt,\n\tu32\t\t\t\tflags\n);\n\n#endif /* PLATFORM_WINDOWS */\n\n#ifdef PLATFORM_FREEBSD\n#define NR_XMITFRAME\t256\nextern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev);\nextern void rtw_xmit_entry_wrap(struct ifnet *pifp);\n#endif /* PLATFORM_FREEBSD */\n\n#ifdef PLATFORM_LINUX\n\n#define NR_XMITFRAME\t256\n\nstruct xmit_priv;\nstruct pkt_attrib;\nstruct sta_xmit_priv;\nstruct xmit_frame;\nstruct xmit_buf;\n\nextern int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev);\nextern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev);\n\n#endif /* PLATFORM_LINUX */\n\nvoid rtw_os_xmit_schedule(_adapter *padapter);\n\nint rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 alloc_sz, u8 flag);\nvoid rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 free_sz, u8 flag);\n\nextern void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib);\n\nextern uint rtw_remainder_len(struct pkt_file *pfile);\nextern void _rtw_open_pktfile(_pkt *pkt, struct pkt_file *pfile);\nextern uint _rtw_pktfile_read(struct pkt_file *pfile, u8 *rmem, uint rlen);\nextern sint rtw_endofpktfile(struct pkt_file *pfile);\n\nextern void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt);\nextern void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe);\n\nvoid rtw_os_wake_queue_at_free_stainfo(_adapter *padapter, int *qcnt_freed);\n\nvoid dump_os_queue(void *sel, _adapter *padapter);\n\n#endif /* __XMIT_OSDEP_H_ */\n"
  },
  {
    "path": "os_dep/linux/.rtw_proc.o.d",
    "content": "rtw_proc.o: /home/juanro/Desktop/rtl88x2ce-35403/os_dep/linux/rtw_proc.c \\\n include/linux/kconfig.h include/generated/autoconf.h \\\n include/linux/compiler_types.h include/linux/compiler_attributes.h \\\n include/linux/compiler-gcc.h include/linux/ctype.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/drv_types.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/drv_conf.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/autoconf.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/hal_ic_cfg.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/basic_types.h \\\n include/generated/uapi/linux/version.h include/linux/types.h \\\n include/uapi/linux/types.h arch/x86/include/generated/uapi/asm/types.h \\\n include/uapi/asm-generic/types.h include/asm-generic/int-ll64.h \\\n include/uapi/asm-generic/int-ll64.h \\\n arch/x86/include/uapi/asm/bitsperlong.h \\\n include/asm-generic/bitsperlong.h include/uapi/asm-generic/bitsperlong.h \\\n include/uapi/linux/posix_types.h include/linux/stddef.h \\\n include/uapi/linux/stddef.h include/linux/compiler_types.h \\\n arch/x86/include/asm/posix_types.h \\\n arch/x86/include/uapi/asm/posix_types_64.h \\\n include/uapi/asm-generic/posix_types.h include/linux/module.h \\\n include/linux/list.h include/linux/poison.h include/linux/const.h \\\n include/uapi/linux/const.h include/linux/kernel.h \\\n /usr/lib/gcc/x86_64-linux-gnu/10/include/stdarg.h include/linux/limits.h \\\n include/uapi/linux/limits.h include/linux/linkage.h \\\n include/linux/stringify.h include/linux/export.h \\\n include/linux/compiler.h arch/x86/include/asm/barrier.h \\\n arch/x86/include/asm/alternative.h arch/x86/include/asm/asm.h \\\n arch/x86/include/asm/nops.h include/asm-generic/barrier.h \\\n include/linux/kasan-checks.h arch/x86/include/asm/linkage.h \\\n include/linux/bitops.h include/linux/bits.h \\\n arch/x86/include/asm/bitops.h arch/x86/include/asm/rmwcc.h \\\n include/asm-generic/bitops/find.h include/asm-generic/bitops/sched.h \\\n arch/x86/include/asm/arch_hweight.h arch/x86/include/asm/cpufeatures.h \\\n arch/x86/include/asm/required-features.h \\\n arch/x86/include/asm/disabled-features.h \\\n include/asm-generic/bitops/const_hweight.h \\\n include/asm-generic/bitops/instrumented-atomic.h \\\n include/asm-generic/bitops/instrumented-non-atomic.h \\\n include/asm-generic/bitops/instrumented-lock.h \\\n include/asm-generic/bitops/le.h arch/x86/include/uapi/asm/byteorder.h \\\n include/linux/byteorder/little_endian.h \\\n include/uapi/linux/byteorder/little_endian.h include/linux/swab.h \\\n include/uapi/linux/swab.h arch/x86/include/uapi/asm/swab.h \\\n include/linux/byteorder/generic.h \\\n include/asm-generic/bitops/ext2-atomic-setbit.h include/linux/log2.h \\\n include/linux/typecheck.h include/linux/printk.h include/linux/init.h \\\n include/linux/kern_levels.h include/linux/cache.h \\\n include/uapi/linux/kernel.h include/uapi/linux/sysinfo.h \\\n arch/x86/include/asm/cache.h include/linux/dynamic_debug.h \\\n include/linux/jump_label.h arch/x86/include/asm/jump_label.h \\\n include/linux/build_bug.h arch/x86/include/asm/div64.h \\\n include/asm-generic/div64.h include/linux/stat.h \\\n arch/x86/include/uapi/asm/stat.h include/uapi/linux/stat.h \\\n include/linux/time.h include/linux/seqlock.h include/linux/spinlock.h \\\n include/linux/preempt.h arch/x86/include/asm/preempt.h \\\n arch/x86/include/asm/percpu.h include/asm-generic/percpu.h \\\n include/linux/threads.h include/linux/percpu-defs.h \\\n include/linux/thread_info.h include/linux/bug.h \\\n arch/x86/include/asm/bug.h include/asm-generic/bug.h \\\n include/linux/restart_block.h include/linux/time64.h \\\n include/linux/math64.h include/uapi/linux/time.h \\\n include/uapi/linux/time_types.h arch/x86/include/asm/current.h \\\n arch/x86/include/asm/thread_info.h arch/x86/include/asm/page.h \\\n arch/x86/include/asm/page_types.h include/linux/mem_encrypt.h \\\n arch/x86/include/asm/mem_encrypt.h arch/x86/include/uapi/asm/bootparam.h \\\n include/linux/screen_info.h include/uapi/linux/screen_info.h \\\n include/linux/apm_bios.h include/uapi/linux/apm_bios.h \\\n include/uapi/linux/ioctl.h arch/x86/include/generated/uapi/asm/ioctl.h \\\n include/asm-generic/ioctl.h include/uapi/asm-generic/ioctl.h \\\n include/linux/edd.h include/uapi/linux/edd.h arch/x86/include/asm/ist.h \\\n arch/x86/include/uapi/asm/ist.h include/video/edid.h \\\n include/uapi/video/edid.h arch/x86/include/asm/page_64_types.h \\\n arch/x86/include/asm/kaslr.h arch/x86/include/asm/page_64.h \\\n include/linux/range.h include/asm-generic/memory_model.h \\\n include/linux/pfn.h include/asm-generic/getorder.h \\\n arch/x86/include/asm/cpufeature.h arch/x86/include/asm/processor.h \\\n arch/x86/include/asm/processor-flags.h \\\n arch/x86/include/uapi/asm/processor-flags.h \\\n arch/x86/include/asm/math_emu.h arch/x86/include/asm/ptrace.h \\\n arch/x86/include/asm/segment.h arch/x86/include/uapi/asm/ptrace.h \\\n arch/x86/include/uapi/asm/ptrace-abi.h \\\n arch/x86/include/asm/paravirt_types.h arch/x86/include/asm/desc_defs.h \\\n arch/x86/include/asm/kmap_types.h include/asm-generic/kmap_types.h \\\n arch/x86/include/asm/pgtable_types.h \\\n arch/x86/include/asm/pgtable_64_types.h arch/x86/include/asm/sparsemem.h \\\n include/asm-generic/pgtable-nop4d.h arch/x86/include/asm/nospec-branch.h \\\n include/linux/static_key.h arch/x86/include/asm/alternative-asm.h \\\n arch/x86/include/asm/msr-index.h arch/x86/include/asm/spinlock_types.h \\\n include/asm-generic/qspinlock_types.h \\\n include/asm-generic/qrwlock_types.h \\\n arch/x86/include/uapi/asm/sigcontext.h arch/x86/include/asm/msr.h \\\n arch/x86/include/asm/msr-index.h \\\n arch/x86/include/generated/uapi/asm/errno.h \\\n include/uapi/asm-generic/errno.h include/uapi/asm-generic/errno-base.h \\\n arch/x86/include/asm/cpumask.h include/linux/cpumask.h \\\n include/linux/bitmap.h include/linux/string.h \\\n include/uapi/linux/string.h arch/x86/include/asm/string.h \\\n arch/x86/include/asm/string_64.h include/linux/atomic.h \\\n arch/x86/include/asm/atomic.h arch/x86/include/asm/cmpxchg.h \\\n arch/x86/include/asm/cmpxchg_64.h arch/x86/include/asm/atomic64_64.h \\\n include/asm-generic/atomic-instrumented.h \\\n include/linux/atomic-fallback.h include/asm-generic/atomic-long.h \\\n arch/x86/include/uapi/asm/msr.h include/linux/tracepoint-defs.h \\\n arch/x86/include/asm/paravirt.h arch/x86/include/asm/frame.h \\\n arch/x86/include/asm/special_insns.h arch/x86/include/asm/fpu/types.h \\\n arch/x86/include/asm/unwind_hints.h arch/x86/include/asm/orc_types.h \\\n arch/x86/include/asm/vmxfeatures.h include/linux/personality.h \\\n include/uapi/linux/personality.h include/linux/err.h \\\n include/linux/irqflags.h arch/x86/include/asm/irqflags.h \\\n include/linux/bottom_half.h arch/x86/include/generated/asm/mmiowb.h \\\n include/asm-generic/mmiowb.h include/linux/spinlock_types.h \\\n include/linux/lockdep.h include/linux/rwlock_types.h \\\n arch/x86/include/asm/spinlock.h arch/x86/include/asm/qspinlock.h \\\n include/asm-generic/qspinlock.h arch/x86/include/asm/qrwlock.h \\\n include/asm-generic/qrwlock.h include/linux/rwlock.h \\\n include/linux/spinlock_api_smp.h include/linux/rwlock_api_smp.h \\\n include/linux/time32.h include/linux/timex.h include/uapi/linux/timex.h \\\n include/uapi/linux/param.h arch/x86/include/generated/uapi/asm/param.h \\\n include/asm-generic/param.h include/uapi/asm-generic/param.h \\\n arch/x86/include/asm/timex.h arch/x86/include/asm/tsc.h \\\n include/linux/uidgid.h include/linux/highuid.h include/linux/kmod.h \\\n include/linux/umh.h include/linux/gfp.h include/linux/mmdebug.h \\\n include/linux/mmzone.h include/linux/wait.h include/uapi/linux/wait.h \\\n include/linux/numa.h include/linux/nodemask.h \\\n include/linux/pageblock-flags.h include/linux/page-flags-layout.h \\\n include/generated/bounds.h include/linux/mm_types.h \\\n include/linux/mm_types_task.h arch/x86/include/asm/tlbbatch.h \\\n include/linux/auxvec.h include/uapi/linux/auxvec.h \\\n arch/x86/include/uapi/asm/auxvec.h include/linux/rbtree.h \\\n include/linux/rcupdate.h include/linux/rcutree.h include/linux/rwsem.h \\\n include/linux/osq_lock.h include/linux/completion.h \\\n include/linux/uprobes.h include/linux/errno.h include/uapi/linux/errno.h \\\n arch/x86/include/asm/uprobes.h include/linux/notifier.h \\\n include/linux/mutex.h include/linux/debug_locks.h include/linux/srcu.h \\\n include/linux/workqueue.h include/linux/timer.h include/linux/ktime.h \\\n include/linux/jiffies.h include/generated/timeconst.h \\\n include/linux/timekeeping.h include/linux/timekeeping32.h \\\n include/linux/debugobjects.h include/linux/rcu_segcblist.h \\\n include/linux/srcutree.h include/linux/rcu_node_tree.h \\\n arch/x86/include/asm/mmu.h include/linux/page-flags.h \\\n include/linux/memory_hotplug.h arch/x86/include/asm/mmzone.h \\\n arch/x86/include/asm/mmzone_64.h arch/x86/include/asm/smp.h \\\n arch/x86/include/asm/mpspec.h arch/x86/include/asm/mpspec_def.h \\\n arch/x86/include/asm/x86_init.h arch/x86/include/asm/apicdef.h \\\n arch/x86/include/asm/apic.h arch/x86/include/asm/fixmap.h \\\n arch/x86/include/asm/acpi.h include/acpi/pdc_intel.h \\\n arch/x86/include/asm/numa.h arch/x86/include/asm/topology.h \\\n include/asm-generic/topology.h arch/x86/include/uapi/asm/vsyscall.h \\\n include/asm-generic/fixmap.h arch/x86/include/asm/hardirq.h \\\n arch/x86/include/asm/io_apic.h arch/x86/include/asm/irq_vectors.h \\\n include/linux/topology.h include/linux/arch_topology.h \\\n include/linux/percpu.h include/linux/smp.h include/linux/llist.h \\\n include/linux/sysctl.h include/uapi/linux/sysctl.h include/linux/elf.h \\\n arch/x86/include/asm/elf.h arch/x86/include/asm/user.h \\\n arch/x86/include/asm/user_64.h arch/x86/include/asm/fsgsbase.h \\\n arch/x86/include/asm/vdso.h include/uapi/linux/elf.h \\\n include/uapi/linux/elf-em.h include/linux/kobject.h \\\n include/linux/sysfs.h include/linux/kernfs.h include/linux/idr.h \\\n include/linux/radix-tree.h include/linux/xarray.h \\\n include/linux/kconfig.h include/linux/kobject_ns.h include/linux/kref.h \\\n include/linux/refcount.h include/linux/moduleparam.h \\\n include/linux/rbtree_latch.h include/linux/error-injection.h \\\n include/asm-generic/error-injection.h arch/x86/include/asm/module.h \\\n include/asm-generic/module.h arch/x86/include/asm/orc_types.h \\\n include/linux/utsname.h include/linux/sched.h include/uapi/linux/sched.h \\\n include/linux/pid.h include/linux/rculist.h include/linux/sem.h \\\n include/uapi/linux/sem.h include/linux/ipc.h \\\n include/linux/rhashtable-types.h include/uapi/linux/ipc.h \\\n arch/x86/include/generated/uapi/asm/ipcbuf.h \\\n include/uapi/asm-generic/ipcbuf.h arch/x86/include/uapi/asm/sembuf.h \\\n include/linux/shm.h include/uapi/linux/shm.h \\\n include/uapi/asm-generic/hugetlb_encode.h \\\n arch/x86/include/uapi/asm/shmbuf.h include/uapi/asm-generic/shmbuf.h \\\n arch/x86/include/asm/shmparam.h include/linux/kcov.h \\\n include/uapi/linux/kcov.h include/linux/plist.h include/linux/hrtimer.h \\\n include/linux/hrtimer_defs.h include/linux/timerqueue.h \\\n include/linux/seccomp.h include/uapi/linux/seccomp.h \\\n arch/x86/include/asm/seccomp.h arch/x86/include/asm/unistd.h \\\n arch/x86/include/uapi/asm/unistd.h \\\n arch/x86/include/generated/uapi/asm/unistd_64.h \\\n arch/x86/include/generated/asm/unistd_64_x32.h \\\n arch/x86/include/asm/ia32_unistd.h \\\n arch/x86/include/generated/asm/unistd_32_ia32.h \\\n include/asm-generic/seccomp.h include/uapi/linux/unistd.h \\\n include/linux/resource.h include/uapi/linux/resource.h \\\n arch/x86/include/generated/uapi/asm/resource.h \\\n include/asm-generic/resource.h include/uapi/asm-generic/resource.h \\\n include/linux/latencytop.h include/linux/sched/prio.h \\\n include/linux/sched/types.h include/linux/signal_types.h \\\n include/uapi/linux/signal.h arch/x86/include/asm/signal.h \\\n arch/x86/include/uapi/asm/signal.h \\\n include/uapi/asm-generic/signal-defs.h \\\n arch/x86/include/uapi/asm/siginfo.h include/uapi/asm-generic/siginfo.h \\\n include/linux/task_io_accounting.h include/linux/posix-timers.h \\\n include/linux/alarmtimer.h include/uapi/linux/rseq.h \\\n include/linux/nsproxy.h include/linux/ns_common.h \\\n include/uapi/linux/utsname.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/osdep_service.h \\\n include/linux/sched/signal.h include/linux/signal.h \\\n include/linux/sched/jobctl.h include/linux/sched/task.h \\\n include/linux/uaccess.h arch/x86/include/asm/uaccess.h \\\n arch/x86/include/asm/smap.h arch/x86/include/asm/extable.h \\\n arch/x86/include/asm/uaccess_64.h include/linux/cred.h \\\n include/linux/capability.h include/uapi/linux/capability.h \\\n include/linux/key.h include/linux/assoc_array.h \\\n include/linux/sched/user.h include/linux/ratelimit.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/osdep_service_linux.h \\\n include/linux/slab.h include/linux/overflow.h \\\n include/linux/percpu-refcount.h include/linux/kasan.h \\\n include/linux/netdevice.h include/linux/delay.h \\\n arch/x86/include/asm/delay.h include/asm-generic/delay.h \\\n include/linux/prefetch.h include/linux/dynamic_queue_limits.h \\\n include/linux/ethtool.h include/linux/compat.h include/linux/socket.h \\\n arch/x86/include/generated/uapi/asm/socket.h \\\n include/uapi/asm-generic/socket.h \\\n arch/x86/include/generated/uapi/asm/sockios.h \\\n include/uapi/asm-generic/sockios.h include/uapi/linux/sockios.h \\\n include/linux/uio.h include/crypto/hash.h include/linux/crypto.h \\\n include/uapi/linux/uio.h include/uapi/linux/socket.h \\\n include/uapi/linux/if.h include/uapi/linux/libc-compat.h \\\n include/uapi/linux/hdlc/ioctl.h include/linux/fs.h \\\n include/linux/wait_bit.h include/linux/kdev_t.h \\\n include/uapi/linux/kdev_t.h include/linux/dcache.h \\\n include/linux/rculist_bl.h include/linux/list_bl.h \\\n include/linux/bit_spinlock.h include/linux/lockref.h \\\n include/linux/stringhash.h include/linux/hash.h include/linux/path.h \\\n include/linux/list_lru.h include/linux/shrinker.h \\\n include/linux/semaphore.h include/linux/fcntl.h \\\n include/uapi/linux/fcntl.h arch/x86/include/generated/uapi/asm/fcntl.h \\\n include/uapi/asm-generic/fcntl.h include/uapi/linux/openat2.h \\\n include/uapi/linux/fiemap.h include/linux/migrate_mode.h \\\n include/linux/percpu-rwsem.h include/linux/rcuwait.h \\\n include/linux/rcu_sync.h include/linux/delayed_call.h \\\n include/linux/uuid.h include/uapi/linux/uuid.h include/linux/errseq.h \\\n include/linux/ioprio.h include/linux/sched/rt.h \\\n include/linux/iocontext.h include/linux/fs_types.h \\\n include/uapi/linux/fs.h include/linux/quota.h \\\n include/linux/percpu_counter.h include/uapi/linux/dqblk_xfs.h \\\n include/linux/dqblk_v1.h include/linux/dqblk_v2.h \\\n include/linux/dqblk_qtree.h include/linux/projid.h \\\n include/uapi/linux/quota.h include/linux/nfs_fs_i.h \\\n include/uapi/linux/aio_abi.h arch/x86/include/asm/compat.h \\\n include/linux/sched/task_stack.h include/uapi/linux/magic.h \\\n arch/x86/include/asm/user32.h include/asm-generic/compat.h \\\n arch/x86/include/asm/syscall_wrapper.h include/uapi/linux/ethtool.h \\\n include/linux/if_ether.h include/linux/skbuff.h include/linux/bvec.h \\\n include/linux/mm.h include/linux/page_ext.h include/linux/stacktrace.h \\\n include/linux/stackdepot.h include/linux/page_ref.h \\\n include/linux/memremap.h include/linux/ioport.h include/linux/sizes.h \\\n arch/x86/include/asm/pgtable.h arch/x86/include/asm/fpu/xstate.h \\\n arch/x86/include/asm/fpu/api.h arch/x86/include/asm/pgtable_64.h \\\n arch/x86/include/asm/pgtable-invert.h include/asm-generic/pgtable.h \\\n include/linux/huge_mm.h include/linux/sched/coredump.h \\\n include/linux/vmstat.h include/linux/vm_event_item.h include/linux/net.h \\\n include/linux/random.h include/linux/once.h include/uapi/linux/random.h \\\n include/linux/irqnr.h include/uapi/linux/irqnr.h \\\n arch/x86/include/asm/archrandom.h include/uapi/linux/net.h \\\n include/linux/textsearch.h include/net/checksum.h \\\n arch/x86/include/asm/checksum.h arch/x86/include/asm/checksum_64.h \\\n include/linux/dma-mapping.h include/linux/device.h \\\n include/linux/dev_printk.h include/linux/klist.h include/linux/pm.h \\\n include/linux/device/bus.h include/linux/device/class.h \\\n include/linux/device/driver.h arch/x86/include/asm/device.h \\\n include/linux/pm_wakeup.h include/linux/dma-debug.h \\\n include/linux/dma-direction.h include/linux/scatterlist.h \\\n arch/x86/include/asm/io.h arch/x86/include/generated/asm/early_ioremap.h \\\n include/asm-generic/early_ioremap.h include/asm-generic/iomap.h \\\n include/asm-generic/pci_iomap.h include/asm-generic/io.h \\\n include/linux/logic_pio.h include/linux/fwnode.h include/linux/vmalloc.h \\\n arch/x86/include/asm/vmalloc.h arch/x86/include/asm/pgtable_areas.h \\\n arch/x86/include/asm/dma-mapping.h arch/x86/include/asm/swiotlb.h \\\n include/linux/swiotlb.h include/linux/dma-contiguous.h \\\n include/linux/netdev_features.h include/linux/sched/clock.h \\\n include/net/flow_dissector.h include/linux/in6.h \\\n include/uapi/linux/in6.h include/linux/siphash.h \\\n include/uapi/linux/if_ether.h include/linux/splice.h \\\n include/linux/pipe_fs_i.h include/uapi/linux/if_packet.h \\\n include/net/flow.h include/linux/netfilter/nf_conntrack_common.h \\\n include/uapi/linux/netfilter/nf_conntrack_common.h \\\n include/net/net_namespace.h include/net/netns/core.h \\\n include/net/netns/mib.h include/net/snmp.h include/uapi/linux/snmp.h \\\n include/linux/u64_stats_sync.h arch/x86/include/asm/local64.h \\\n include/asm-generic/local64.h arch/x86/include/asm/local.h \\\n include/net/netns/unix.h include/net/netns/packet.h \\\n include/net/netns/ipv4.h include/net/inet_frag.h \\\n include/net/netns/ipv6.h include/net/dst_ops.h \\\n include/uapi/linux/icmpv6.h include/net/netns/nexthop.h \\\n include/net/netns/ieee802154_6lowpan.h include/net/netns/sctp.h \\\n include/net/netns/dccp.h include/net/netns/netfilter.h \\\n include/linux/netfilter_defs.h include/uapi/linux/netfilter.h \\\n include/linux/in.h include/uapi/linux/in.h include/net/netns/x_tables.h \\\n include/net/netns/conntrack.h include/linux/list_nulls.h \\\n include/linux/netfilter/nf_conntrack_tcp.h \\\n include/uapi/linux/netfilter/nf_conntrack_tcp.h \\\n include/linux/netfilter/nf_conntrack_dccp.h \\\n include/uapi/linux/netfilter/nf_conntrack_tuple_common.h \\\n include/linux/netfilter/nf_conntrack_sctp.h \\\n include/uapi/linux/netfilter/nf_conntrack_sctp.h \\\n include/net/netns/nftables.h include/net/netns/xfrm.h \\\n include/uapi/linux/xfrm.h include/net/netns/mpls.h \\\n include/net/netns/can.h include/net/netns/xdp.h \\\n include/linux/seq_file_net.h include/linux/seq_file.h \\\n include/net/dcbnl.h include/uapi/linux/dcbnl.h \\\n include/net/netprio_cgroup.h include/linux/cgroup.h \\\n include/uapi/linux/cgroupstats.h include/uapi/linux/taskstats.h \\\n include/linux/user_namespace.h include/linux/kernel_stat.h \\\n include/linux/interrupt.h include/linux/irqreturn.h \\\n include/linux/hardirq.h include/linux/ftrace_irq.h include/linux/vtime.h \\\n include/linux/context_tracking_state.h arch/x86/include/asm/irq.h \\\n arch/x86/include/asm/sections.h include/asm-generic/sections.h \\\n include/linux/cgroup-defs.h include/linux/bpf-cgroup.h \\\n include/linux/bpf.h include/uapi/linux/bpf.h \\\n include/uapi/linux/bpf_common.h include/linux/file.h \\\n include/linux/bpf_types.h include/linux/psi_types.h \\\n include/linux/kthread.h include/linux/cgroup_subsys.h include/net/xdp.h \\\n include/uapi/linux/neighbour.h include/linux/netlink.h include/net/scm.h \\\n include/linux/security.h include/uapi/linux/netlink.h \\\n include/uapi/linux/netdevice.h include/linux/if_link.h \\\n include/uapi/linux/if_link.h include/uapi/linux/if_bonding.h \\\n include/uapi/linux/pkt_cls.h include/uapi/linux/pkt_sched.h \\\n include/linux/hashtable.h include/linux/inetdevice.h include/linux/ip.h \\\n include/uapi/linux/ip.h include/linux/rtnetlink.h \\\n include/uapi/linux/rtnetlink.h include/uapi/linux/if_addr.h \\\n include/linux/circ_buf.h include/linux/etherdevice.h \\\n arch/x86/include/asm/unaligned.h include/linux/unaligned/access_ok.h \\\n include/linux/unaligned/generic.h include/linux/wireless.h \\\n include/uapi/linux/wireless.h include/net/iw_handler.h \\\n include/net/addrconf.h include/linux/ipv6.h include/uapi/linux/ipv6.h \\\n include/linux/icmpv6.h include/linux/tcp.h include/linux/win_minmax.h \\\n include/net/sock.h include/linux/page_counter.h \\\n include/linux/memcontrol.h include/linux/vmpressure.h \\\n include/linux/eventfd.h include/linux/writeback.h \\\n include/linux/flex_proportions.h include/linux/backing-dev-defs.h \\\n include/linux/blk_types.h include/linux/blk-cgroup.h \\\n include/linux/blkdev.h include/uapi/linux/major.h include/linux/genhd.h \\\n include/linux/pagemap.h include/linux/highmem.h \\\n arch/x86/include/asm/cacheflush.h include/asm-generic/cacheflush.h \\\n include/linux/hugetlb_inline.h include/linux/mempool.h \\\n include/linux/bio.h include/linux/bsg.h include/uapi/linux/bsg.h \\\n include/uapi/linux/blkzoned.h include/linux/elevator.h \\\n include/linux/filter.h include/linux/cryptohash.h \\\n include/linux/set_memory.h arch/x86/include/asm/set_memory.h \\\n include/asm-generic/set_memory.h include/linux/kallsyms.h \\\n include/linux/if_vlan.h include/uapi/linux/if_vlan.h \\\n include/net/sch_generic.h include/uapi/linux/pkt_cls.h \\\n include/net/gen_stats.h include/uapi/linux/gen_stats.h \\\n include/net/rtnetlink.h include/net/netlink.h include/net/flow_offload.h \\\n include/linux/rhashtable.h include/linux/jhash.h \\\n include/linux/unaligned/packed_struct.h include/uapi/linux/filter.h \\\n include/linux/rculist_nulls.h include/linux/poll.h \\\n include/uapi/linux/poll.h arch/x86/include/generated/uapi/asm/poll.h \\\n include/uapi/asm-generic/poll.h include/uapi/linux/eventpoll.h \\\n include/net/dst.h include/net/neighbour.h include/net/tcp_states.h \\\n include/uapi/linux/net_tstamp.h include/net/l3mdev.h \\\n include/net/fib_rules.h include/uapi/linux/fib_rules.h \\\n include/net/fib_notifier.h include/net/inet_connection_sock.h \\\n include/net/inet_sock.h include/net/request_sock.h \\\n include/net/netns/hash.h include/net/inet_timewait_sock.h \\\n include/net/timewait_sock.h include/uapi/linux/tcp.h include/linux/udp.h \\\n include/uapi/linux/udp.h include/net/if_inet6.h include/net/ipv6.h \\\n include/linux/jump_label_ratelimit.h include/net/ndisc.h \\\n include/net/ipv6_stubs.h include/linux/if_arp.h \\\n include/uapi/linux/if_arp.h include/net/ieee80211_radiotap.h \\\n include/linux/ieee80211.h include/net/cfg80211.h include/linux/debugfs.h \\\n include/uapi/linux/nl80211.h include/net/regulatory.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../os_dep/linux/rtw_rhashtable.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/drv_types_linux.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_byteorder.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/byteorder/little_endian.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/wlan_bssdef.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/wifi.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/ieee80211.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_debug.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/cmn_info/rtw_sta_info.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_rf.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../core/rtw_chplan.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_ht.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_vht.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_cmd.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/cmd_osdep.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_security.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_xmit.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/xmit_osdep.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_recv.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/cmn_info/rtw_sta_info.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_rm.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_beamforming.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/recv_osdep.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_efuse.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_sreset.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/hal_intf.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/hal_com.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/HalVerDef.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/hal_pg.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/hal_phy.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/hal_phy_reg.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/hal_com_reg.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/hal_com_phycfg.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/hal_com_c2h.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/hal_com_h2c.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/hal_com_led.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/hal_dm.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_qos.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_pwrctrl.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_mlme.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/mlme_osdep.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_io.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_ioctl.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_ioctl_set.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_ioctl_query.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/osdep_intf.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../os_dep/linux/rtw_proc.h \\\n include/linux/proc_fs.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../os_dep/linux/ioctl_cfg80211.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../os_dep/linux/rtw_cfgvendor.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_eeprom.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/sta_info.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_event.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_mlme_ext.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_mi.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_ap.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_version.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_odm.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_types.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_p2p.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_mp.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_br_ext.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/ip.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/if_ether.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/ethernet.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/circ_buf.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_android.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_btcoex_wifionly.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtw_btcoex.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/drv_types_pci.h \\\n include/linux/pci.h include/linux/mod_devicetable.h include/linux/io.h \\\n include/linux/resource_ext.h include/uapi/linux/pci.h \\\n include/uapi/linux/pci_regs.h include/linux/pci_ids.h \\\n include/linux/dmapool.h arch/x86/include/asm/pci.h \\\n arch/x86/include/asm/memtype.h include/asm-generic/pci.h \\\n include/linux/pci-dma-compat.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/pci_osintf.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/pci_ops.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/pci_hal.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/hal_data.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_precomp.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_types.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/halrf/halrf_features.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_pre_define.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_features.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_features_ce.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_dig.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_pathdiv.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_soml.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_rainfo.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_cfotracking.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_adaptivity.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_dfs.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_ccx.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/txbf/phydm_hal_txbf_api.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_adc_sampling.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_psd.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_cck_pd.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_rssi_monitor.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_auto_dbg.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_math_lib.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_noisemonitor.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_api.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_pmac_tx_setting.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_mp.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_beamforming.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/txbf/halcomtxbf.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/txbf/haltxbfjaguar.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/txbf/haltxbf8192e.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/txbf/haltxbf8814a.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/txbf/haltxbf8822b.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/txbf/haltxbfinterface.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_regtable.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/halrf/halrf_iqk.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/halrf/halrf_dpk.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/halrf/halrf.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/hal/phydm/halrf/halrf_psd.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/hal/phydm/halrf/rtl8822c/halrf_rfk_init_8822c.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/hal/phydm/halrf/rtl8822c/halrf_iqk_8822c.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/hal/phydm/halrf/rtl8822c/halrf_tssi_8822c.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/hal/phydm/halrf/rtl8822c/halrf_dpk_8822c.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/halrf/halrf_powertracking.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/halrf/halphyrf_ce.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/hal/phydm/halrf/halrf_kfree.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/hal/phydm/halrf/halrf_powertracking_ce.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_hwconfig.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_phystatus.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_debug.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_regdefine11ac.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_regdefine11n.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_interface.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/phydm_reg.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/halrf/halrf_debug.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/rtl8822c/halhwimg8822c_bb.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/rtl8822c/phydm_regconfig8822c.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/rtl8822c/phydm_hal_api8822c.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/rtl8822c/version_rtl8822c.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/rtl8822c/phydm_rtl8822c.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/halrf/rtl8822c/halrf_8822c.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/halrf/rtl8822c/halhwimg8822c_rf.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/phydm/halrf/rtl8822c/version_rtl8822c_rf.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtl8822c_hal.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_api.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_2_platform.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_type.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_hw_cfg.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_fw_info.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_intf_phy_cmd.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_state_machine.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_usb_reg.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_sdio_reg.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_pcie_reg.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_bit2.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_reg2.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_reg_8822c.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_bit_8822c.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_tx_desc_nic.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_tx_desc_buffer_nic.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_tx_desc_ie_nic.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_rx_desc_nic.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_tx_bd_nic.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_rx_bd_nic.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_fw_offload_c2h_nic.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_fw_offload_h2c_nic.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_h2c_extra_info_nic.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_original_c2h_nic.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_original_h2c_nic.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_tx_desc_chip.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_rx_desc_chip.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_tx_desc_buffer_chip.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/../hal/halmac/halmac_tx_desc_ie_chip.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/rtl8822ce_hal.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/hal_btcoex.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/include/hal_btcoex_wifionly.h \\\n /home/juanro/Desktop/rtl88x2ce-35403/os_dep/linux/rtw_proc.h\n"
  },
  {
    "path": "os_dep/linux/custom_gpio_linux.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#include \"drv_types.h\"\n\n#ifdef CONFIG_PLATFORM_SPRD\n\n/* gspi func & GPIO define */\n#include <mach/gpio.h>/* 0915 */\n#include <mach/board.h>\n\n#if !(defined ANDROID_2X)\n\n#ifdef CONFIG_RTL8188E\n#include <mach/regulator.h>\n#include <linux/regulator/consumer.h>\n#endif /* CONFIG_RTL8188E */\n\n#ifndef GPIO_WIFI_POWER\n#define GPIO_WIFI_POWER -1\n#endif /* !GPIO_WIFI_POWER */\n\n#ifndef GPIO_WIFI_RESET\n#define GPIO_WIFI_RESET -1\n#endif /* !GPIO_WIFI_RESET */\n\n#ifndef GPIO_WIFI_PWDN\n#define GPIO_WIFI_PWDN -1\n#endif /* !GPIO_WIFI_RESET */\n#ifdef CONFIG_GSPI_HCI\nextern unsigned int oob_irq;\n#endif /* CONFIG_GSPI_HCI */\n\n#ifdef CONFIG_SDIO_HCI\nextern int rtw_mp_mode;\n#else /* !CONFIG_SDIO_HCI */\n#endif /* !CONFIG_SDIO_HCI */\n\nint rtw_wifi_gpio_init(void)\n{\n#ifdef CONFIG_GSPI_HCI\n\tif (GPIO_WIFI_IRQ > 0) {\n\t\tgpio_request(GPIO_WIFI_IRQ, \"oob_irq\");\n\t\tgpio_direction_input(GPIO_WIFI_IRQ);\n\n\t\toob_irq = gpio_to_irq(GPIO_WIFI_IRQ);\n\n\t\tRTW_INFO(\"%s oob_irq:%d\\n\", __func__, oob_irq);\n\t}\n#endif\n\tif (GPIO_WIFI_RESET > 0)\n\t\tgpio_request(GPIO_WIFI_RESET , \"wifi_rst\");\n\tif (GPIO_WIFI_POWER > 0)\n\t\tgpio_request(GPIO_WIFI_POWER, \"wifi_power\");\n\n#ifdef CONFIG_SDIO_HCI\n#if (defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1)\n\tif (rtw_mp_mode == 1) {\n\t\tRTW_INFO(\"%s GPIO_BT_RESET pin special for mp_test\\n\", __func__);\n\t\tif (GPIO_BT_RESET > 0)\n\t\t\tgpio_request(GPIO_BT_RESET , \"bt_rst\");\n\t}\n#endif\n#endif\n\treturn 0;\n}\n\nint rtw_wifi_gpio_deinit(void)\n{\n#ifdef CONFIG_GSPI_HCI\n\tif (GPIO_WIFI_IRQ > 0)\n\t\tgpio_free(GPIO_WIFI_IRQ);\n#endif\n\tif (GPIO_WIFI_RESET > 0)\n\t\tgpio_free(GPIO_WIFI_RESET);\n\tif (GPIO_WIFI_POWER > 0)\n\t\tgpio_free(GPIO_WIFI_POWER);\n\n#ifdef CONFIG_SDIO_HCI\n#if (defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1)\n\tif (rtw_mp_mode == 1) {\n\t\tRTW_INFO(\"%s GPIO_BT_RESET pin special for mp_test\\n\", __func__);\n\t\tif (GPIO_BT_RESET > 0)\n\t\t\tgpio_free(GPIO_BT_RESET);\n\t}\n#endif\n#endif\n\treturn 0;\n}\n\n/* Customer function to control hw specific wlan gpios */\nvoid rtw_wifi_gpio_wlan_ctrl(int onoff)\n{\n\tswitch (onoff) {\n\tcase WLAN_PWDN_OFF:\n\t\tRTW_INFO(\"%s: call customer specific GPIO(%d) to set wifi power down pin to 0\\n\",\n\t\t\t __FUNCTION__, GPIO_WIFI_RESET);\n\n#ifndef CONFIG_DONT_BUS_SCAN\n\t\tif (GPIO_WIFI_RESET > 0)\n\t\t\tgpio_direction_output(GPIO_WIFI_RESET , 0);\n#endif\n\t\tbreak;\n\n\tcase WLAN_PWDN_ON:\n\t\tRTW_INFO(\"%s: callc customer specific GPIO(%d) to set wifi power down pin to 1\\n\",\n\t\t\t __FUNCTION__, GPIO_WIFI_RESET);\n\n\t\tif (GPIO_WIFI_RESET > 0)\n\t\t\tgpio_direction_output(GPIO_WIFI_RESET , 1);\n\t\tbreak;\n\n\tcase WLAN_POWER_OFF:\n\t\tbreak;\n\n\tcase WLAN_POWER_ON:\n\t\tbreak;\n#ifdef CONFIG_SDIO_HCI\n#if (defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1)\n\tcase WLAN_BT_PWDN_OFF:\n\t\tif (rtw_mp_mode == 1) {\n\t\t\tRTW_INFO(\"%s: call customer specific GPIO to set wifi power down pin to 0\\n\",\n\t\t\t\t __FUNCTION__);\n\t\t\tif (GPIO_BT_RESET > 0)\n\t\t\t\tgpio_direction_output(GPIO_BT_RESET , 0);\n\t\t}\n\t\tbreak;\n\n\tcase WLAN_BT_PWDN_ON:\n\t\tif (rtw_mp_mode == 1) {\n\t\t\tRTW_INFO(\"%s: callc customer specific GPIO to set wifi power down pin to 1 %x\\n\",\n\t\t\t\t __FUNCTION__, GPIO_BT_RESET);\n\n\t\t\tif (GPIO_BT_RESET > 0)\n\t\t\t\tgpio_direction_output(GPIO_BT_RESET , 1);\n\t\t}\n\t\tbreak;\n#endif\n#endif\n\t}\n}\n\n#else /* ANDROID_2X */\n\n#include <mach/ldo.h>\n\n#ifdef CONFIG_RTL8188E\nextern int sprd_3rdparty_gpio_wifi_power;\n#endif\nextern int sprd_3rdparty_gpio_wifi_pwd;\n#if  defined(CONFIG_RTL8723B)\nextern int sprd_3rdparty_gpio_bt_reset;\n#endif\n\nint rtw_wifi_gpio_init(void)\n{\n#if defined(CONFIG_RTL8723B)\n\tif (sprd_3rdparty_gpio_bt_reset > 0)\n\t\tgpio_direction_output(sprd_3rdparty_gpio_bt_reset, 1);\n#endif\n\n\treturn 0;\n}\n\nint rtw_wifi_gpio_deinit(void)\n{\n\treturn 0;\n}\n\n/* Customer function to control hw specific wlan gpios */\nvoid rtw_wifi_gpio_wlan_ctrl(int onoff)\n{\n\tswitch (onoff) {\n\tcase WLAN_PWDN_OFF:\n\t\tRTW_INFO(\"%s: call customer specific GPIO to set wifi power down pin to 0\\n\",\n\t\t\t __FUNCTION__);\n\t\tif (sprd_3rdparty_gpio_wifi_pwd > 0)\n\t\t\tgpio_set_value(sprd_3rdparty_gpio_wifi_pwd, 0);\n\n\t\tif (sprd_3rdparty_gpio_wifi_pwd == 60) {\n\t\t\tRTW_INFO(\"%s: turn off VSIM2 2.8V\\n\", __func__);\n\t\t\tLDO_TurnOffLDO(LDO_LDO_SIM2);\n\t\t}\n\t\tbreak;\n\n\tcase WLAN_PWDN_ON:\n\t\tRTW_INFO(\"%s: callc customer specific GPIO to set wifi power down pin to 1\\n\",\n\t\t\t __FUNCTION__);\n\t\tif (sprd_3rdparty_gpio_wifi_pwd == 60) {\n\t\t\tRTW_INFO(\"%s: turn on VSIM2 2.8V\\n\", __func__);\n\t\t\tLDO_SetVoltLevel(LDO_LDO_SIM2, LDO_VOLT_LEVEL0);\n\t\t\tLDO_TurnOnLDO(LDO_LDO_SIM2);\n\t\t}\n\t\tif (sprd_3rdparty_gpio_wifi_pwd > 0)\n\t\t\tgpio_set_value(sprd_3rdparty_gpio_wifi_pwd, 1);\n\t\tbreak;\n\n\tcase WLAN_POWER_OFF:\n#ifdef CONFIG_RTL8188E\n#ifdef CONFIG_WIF1_LDO\n\t\tRTW_INFO(\"%s: turn off VDD-WIFI0 1.2V\\n\", __FUNCTION__);\n\t\tLDO_TurnOffLDO(LDO_LDO_WIF1);\n#endif /* CONFIG_WIF1_LDO */\n\n\t\tRTW_INFO(\"%s: turn off VDD-WIFI0 3.3V\\n\", __FUNCTION__);\n\t\tLDO_TurnOffLDO(LDO_LDO_WIF0);\n\n\t\tRTW_INFO(\"%s: call customer specific GPIO(%d) to turn off wifi power\\n\",\n\t\t\t __FUNCTION__, sprd_3rdparty_gpio_wifi_power);\n\t\tif (sprd_3rdparty_gpio_wifi_power != 65535)\n\t\t\tgpio_set_value(sprd_3rdparty_gpio_wifi_power, 0);\n#endif\n\t\tbreak;\n\n\tcase WLAN_POWER_ON:\n#ifdef CONFIG_RTL8188E\n\t\tRTW_INFO(\"%s: call customer specific GPIO(%d) to turn on wifi power\\n\",\n\t\t\t __FUNCTION__, sprd_3rdparty_gpio_wifi_power);\n\t\tif (sprd_3rdparty_gpio_wifi_power != 65535)\n\t\t\tgpio_set_value(sprd_3rdparty_gpio_wifi_power, 1);\n\n\t\tRTW_INFO(\"%s: turn on VDD-WIFI0 3.3V\\n\", __FUNCTION__);\n\t\tLDO_TurnOnLDO(LDO_LDO_WIF0);\n\t\tLDO_SetVoltLevel(LDO_LDO_WIF0, LDO_VOLT_LEVEL1);\n\n#ifdef CONFIG_WIF1_LDO\n\t\tRTW_INFO(\"%s: turn on VDD-WIFI1 1.2V\\n\", __func__);\n\t\tLDO_TurnOnLDO(LDO_LDO_WIF1);\n\t\tLDO_SetVoltLevel(LDO_LDO_WIF1, LDO_VOLT_LEVEL3);\n#endif /* CONFIG_WIF1_LDO */\n#endif\n\t\tbreak;\n\n\tcase WLAN_BT_PWDN_OFF:\n\t\tRTW_INFO(\"%s: call customer specific GPIO to set bt power down pin to 0\\n\",\n\t\t\t __FUNCTION__);\n#if defined(CONFIG_RTL8723B)\n\t\tif (sprd_3rdparty_gpio_bt_reset > 0)\n\t\t\tgpio_set_value(sprd_3rdparty_gpio_bt_reset, 0);\n#endif\n\t\tbreak;\n\n\tcase WLAN_BT_PWDN_ON:\n\t\tRTW_INFO(\"%s: callc customer specific GPIO to set bt power down pin to 1\\n\",\n\t\t\t __FUNCTION__);\n#if defined(CONFIG_RTL8723B)\n\t\tif (sprd_3rdparty_gpio_bt_reset > 0)\n\t\t\tgpio_set_value(sprd_3rdparty_gpio_bt_reset, 1);\n#endif\n\t\tbreak;\n\t}\n}\n#endif /* ANDROID_2X */\n\n#elif defined(CONFIG_PLATFORM_ARM_RK3066)\n#include <mach/iomux.h>\n\n#define GPIO_WIFI_IRQ\t\tRK30_PIN2_PC2\nextern unsigned int oob_irq;\nint rtw_wifi_gpio_init(void)\n{\n#ifdef CONFIG_GSPI_HCI\n\tif (GPIO_WIFI_IRQ > 0) {\n\t\trk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME, GPIO2C_GPIO2C2);/* jacky_test */\n\t\tgpio_request(GPIO_WIFI_IRQ, \"oob_irq\");\n\t\tgpio_direction_input(GPIO_WIFI_IRQ);\n\n\t\toob_irq = gpio_to_irq(GPIO_WIFI_IRQ);\n\n\t\tRTW_INFO(\"%s oob_irq:%d\\n\", __func__, oob_irq);\n\t}\n#endif\n\treturn 0;\n}\n\n\nint rtw_wifi_gpio_deinit(void)\n{\n#ifdef CONFIG_GSPI_HCI\n\tif (GPIO_WIFI_IRQ > 0)\n\t\tgpio_free(GPIO_WIFI_IRQ);\n#endif\n\treturn 0;\n}\n\nvoid rtw_wifi_gpio_wlan_ctrl(int onoff)\n{\n}\n\n#ifdef CONFIG_GPIO_API\n/* this is a demo for extending GPIO pin[7] as interrupt mode */\nstruct net_device *rtl_net;\nextern int rtw_register_gpio_interrupt(struct net_device *netdev, int gpio_num, void(*callback)(u8 level));\nextern int rtw_disable_gpio_interrupt(struct net_device *netdev, int gpio_num);\nvoid gpio_int(u8 is_high)\n{\n\tRTW_INFO(\"%s level=%d\\n\", __func__, is_high);\n}\nint register_net_gpio_init(void)\n{\n\trtl_net = dev_get_by_name(&init_net, \"wlan0\");\n\tif (!rtl_net) {\n\t\tRTW_PRINT(\"rtl_net init fail!\\n\");\n\t\treturn -1;\n\t}\n\treturn rtw_register_gpio_interrupt(rtl_net, 7, gpio_int);\n}\nint unregister_net_gpio_init(void)\n{\n\trtl_net = dev_get_by_name(&init_net, \"wlan0\");\n\tif (!rtl_net) {\n\t\tRTW_PRINT(\"rtl_net init fail!\\n\");\n\t\treturn -1;\n\t}\n\treturn rtw_disable_gpio_interrupt(rtl_net, 7);\n}\n#endif\n\n#else\n\nint rtw_wifi_gpio_init(void)\n{\n\treturn 0;\n}\n\nvoid rtw_wifi_gpio_wlan_ctrl(int onoff)\n{\n}\n#endif /* CONFIG_PLATFORM_SPRD */\n"
  },
  {
    "path": "os_dep/linux/ioctl_cfg80211.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2019 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define  _IOCTL_CFG80211_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\n#ifdef CONFIG_IOCTL_CFG80211\n\n#ifndef DBG_RTW_CFG80211_STA_PARAM\n#define DBG_RTW_CFG80211_STA_PARAM 0\n#endif\n\n#ifndef DBG_RTW_CFG80211_MESH_CONF\n#define DBG_RTW_CFG80211_MESH_CONF 0\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))\n#define STATION_INFO_INACTIVE_TIME\tBIT(NL80211_STA_INFO_INACTIVE_TIME)\n#define STATION_INFO_LLID\t\t\tBIT(NL80211_STA_INFO_LLID)\n#define STATION_INFO_PLID\t\t\tBIT(NL80211_STA_INFO_PLID)\n#define STATION_INFO_PLINK_STATE\tBIT(NL80211_STA_INFO_PLINK_STATE)\n#define STATION_INFO_SIGNAL\t\t\tBIT(NL80211_STA_INFO_SIGNAL)\n#define STATION_INFO_TX_BITRATE\t\tBIT(NL80211_STA_INFO_TX_BITRATE)\n#define STATION_INFO_RX_PACKETS\t\tBIT(NL80211_STA_INFO_RX_PACKETS)\n#define STATION_INFO_TX_PACKETS\t\tBIT(NL80211_STA_INFO_TX_PACKETS)\n#define STATION_INFO_TX_FAILED\t\tBIT(NL80211_STA_INFO_TX_FAILED)\n#define STATION_INFO_LOCAL_PM\t\tBIT(NL80211_STA_INFO_LOCAL_PM)\n#define STATION_INFO_PEER_PM\t\tBIT(NL80211_STA_INFO_PEER_PM)\n#define STATION_INFO_NONPEER_PM\t\tBIT(NL80211_STA_INFO_NONPEER_PM)\n#define STATION_INFO_ASSOC_REQ_IES\t0\n#endif /* Linux kernel >= 4.0.0 */\n\n#include <rtw_wifi_regd.h>\n\n#define RTW_MAX_MGMT_TX_CNT (8)\n#define RTW_MAX_MGMT_TX_MS_GAS (500)\n\n#define RTW_SCAN_IE_LEN_MAX      2304\n#define RTW_MAX_REMAIN_ON_CHANNEL_DURATION 5000 /* ms */\n#define RTW_MAX_NUM_PMKIDS 4\n\n#define RTW_CH_MAX_2G_CHANNEL               14      /* Max channel in 2G band */\n\n#ifdef CONFIG_WAPI_SUPPORT\n\n#ifndef WLAN_CIPHER_SUITE_SMS4\n#define WLAN_CIPHER_SUITE_SMS4          0x00147201\n#endif\n\n#ifndef WLAN_AKM_SUITE_WAPI_PSK\n#define WLAN_AKM_SUITE_WAPI_PSK         0x000FAC04\n#endif\n\n#ifndef WLAN_AKM_SUITE_WAPI_CERT\n#define WLAN_AKM_SUITE_WAPI_CERT        0x000FAC12\n#endif\n\n#ifndef NL80211_WAPI_VERSION_1\n#define NL80211_WAPI_VERSION_1          (1 << 2)\n#endif\n\n#endif /* CONFIG_WAPI_SUPPORT */\n\n#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 11, 12))\n#ifdef CONFIG_RTW_80211R\n#define WLAN_AKM_SUITE_FT_8021X\t\t0x000FAC03\n#define WLAN_AKM_SUITE_FT_PSK\t\t\t0x000FAC04\n#endif\n#endif\n\n/*\n * In the current design of Wi-Fi driver, it will return success to the system (e.g. supplicant) \n * when Wi-Fi driver decides to abort the scan request in the scan flow by default.\n * Defining this flag makes Wi-Fi driver to return -EBUSY to the system if Wi-Fi driver is too busy to do the scan.\n */\n#ifndef CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY\n\t#define CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY 0\n#endif\n\nstatic const u32 rtw_cipher_suites[] = {\n\tWLAN_CIPHER_SUITE_WEP40,\n\tWLAN_CIPHER_SUITE_WEP104,\n\tWLAN_CIPHER_SUITE_TKIP,\n\tWLAN_CIPHER_SUITE_CCMP,\n#ifdef CONFIG_WAPI_SUPPORT\n\tWLAN_CIPHER_SUITE_SMS4,\n#endif /* CONFIG_WAPI_SUPPORT */\n#ifdef CONFIG_IEEE80211W\n\tWLAN_CIPHER_SUITE_AES_CMAC,\n#endif /* CONFIG_IEEE80211W */\n};\n\n#define RATETAB_ENT(_rate, _rateid, _flags) \\\n\t{\t\t\t\t\t\t\t\t\\\n\t\t.bitrate\t= (_rate),\t\t\t\t\\\n\t\t.hw_value\t= (_rateid),\t\t\t\t\\\n\t\t.flags\t\t= (_flags),\t\t\t\t\\\n\t}\n\n#define CHAN2G(_channel, _freq, _flags) {\t\t\t\\\n\t\t.band\t\t\t= NL80211_BAND_2GHZ,\t\t\\\n\t\t.center_freq\t\t= (_freq),\t\t\t\\\n\t\t.hw_value\t\t= (_channel),\t\t\t\\\n\t\t.flags\t\t\t= (_flags),\t\t\t\\\n\t\t.max_antenna_gain\t= 0,\t\t\t\t\\\n\t\t.max_power\t\t= 30,\t\t\t\t\\\n\t}\n\n#define CHAN5G(_channel, _flags) {\t\t\t\t\\\n\t\t.band\t\t\t= NL80211_BAND_5GHZ,\t\t\\\n\t\t.center_freq\t\t= 5000 + (5 * (_channel)),\t\\\n\t\t.hw_value\t\t= (_channel),\t\t\t\\\n\t\t.flags\t\t\t= (_flags),\t\t\t\\\n\t\t.max_antenna_gain\t= 0,\t\t\t\t\\\n\t\t.max_power\t\t= 30,\t\t\t\t\\\n\t}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))\n/* if wowlan is not supported, kernel generate a disconnect at each suspend\n * cf: /net/wireless/sysfs.c, so register a stub wowlan.\n * Moreover wowlan has to be enabled via a the nl80211_set_wowlan callback.\n * (from user space, e.g. iw phy0 wowlan enable)\n */\nstatic const struct wiphy_wowlan_support wowlan_stub = {\n\t.flags = WIPHY_WOWLAN_ANY,\n\t.n_patterns = 0,\n\t.pattern_max_len = 0,\n\t.pattern_min_len = 0,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))\n\t.max_pkt_offset = 0,\n#endif\n};\n#endif\n\nstatic struct ieee80211_rate rtw_rates[] = {\n\tRATETAB_ENT(10,  0x1,   0),\n\tRATETAB_ENT(20,  0x2,   0),\n\tRATETAB_ENT(55,  0x4,   0),\n\tRATETAB_ENT(110, 0x8,   0),\n\tRATETAB_ENT(60,  0x10,  0),\n\tRATETAB_ENT(90,  0x20,  0),\n\tRATETAB_ENT(120, 0x40,  0),\n\tRATETAB_ENT(180, 0x80,  0),\n\tRATETAB_ENT(240, 0x100, 0),\n\tRATETAB_ENT(360, 0x200, 0),\n\tRATETAB_ENT(480, 0x400, 0),\n\tRATETAB_ENT(540, 0x800, 0),\n};\n\n#define rtw_a_rates\t\t(rtw_rates + 4)\n#define RTW_A_RATES_NUM\t8\n#define rtw_g_rates\t\t(rtw_rates + 0)\n#define RTW_G_RATES_NUM\t12\n\n/* from center_ch_2g */\nstatic struct ieee80211_channel rtw_2ghz_channels[MAX_CHANNEL_NUM_2G] = {\n\tCHAN2G(1, 2412, 0),\n\tCHAN2G(2, 2417, 0),\n\tCHAN2G(3, 2422, 0),\n\tCHAN2G(4, 2427, 0),\n\tCHAN2G(5, 2432, 0),\n\tCHAN2G(6, 2437, 0),\n\tCHAN2G(7, 2442, 0),\n\tCHAN2G(8, 2447, 0),\n\tCHAN2G(9, 2452, 0),\n\tCHAN2G(10, 2457, 0),\n\tCHAN2G(11, 2462, 0),\n\tCHAN2G(12, 2467, 0),\n\tCHAN2G(13, 2472, 0),\n\tCHAN2G(14, 2484, 0),\n};\n\n/* from center_ch_5g_20m */\nstatic struct ieee80211_channel rtw_5ghz_a_channels[MAX_CHANNEL_NUM_5G] = {\n\tCHAN5G(36, 0),\tCHAN5G(40, 0),\tCHAN5G(44, 0),\tCHAN5G(48, 0),\n\n\tCHAN5G(52, 0),\tCHAN5G(56, 0),\tCHAN5G(60, 0),\tCHAN5G(64, 0),\n\n\tCHAN5G(100, 0),\tCHAN5G(104, 0),\tCHAN5G(108, 0),\tCHAN5G(112, 0),\n\tCHAN5G(116, 0),\tCHAN5G(120, 0),\tCHAN5G(124, 0),\tCHAN5G(128, 0),\n\tCHAN5G(132, 0),\tCHAN5G(136, 0),\tCHAN5G(140, 0),\tCHAN5G(144, 0),\n\n\tCHAN5G(149, 0),\tCHAN5G(153, 0),\tCHAN5G(157, 0),\tCHAN5G(161, 0),\n\tCHAN5G(165, 0),\tCHAN5G(169, 0),\tCHAN5G(173, 0),\tCHAN5G(177, 0),\n};\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))\nstatic u8 rtw_chbw_to_cfg80211_chan_def(struct wiphy *wiphy, struct cfg80211_chan_def *chdef, u8 ch, u8 bw, u8 offset, u8 ht)\n{\n\tint freq, cfreq;\n\tstruct ieee80211_channel *chan;\n\tu8 ret = _FAIL;\n\n\tfreq = rtw_ch2freq(ch);\n\tif (!freq)\n\t\tgoto exit;\n\n\tcfreq = rtw_get_center_ch(ch, bw, offset);\n\tif (!cfreq)\n\t\tgoto exit;\n\tcfreq = rtw_ch2freq(cfreq);\n\tif (!cfreq)\n\t\tgoto exit;\n\n\tchan = ieee80211_get_channel(wiphy, freq);\n\tif (!chan)\n\t\tgoto exit;\n\n\tif (bw == CHANNEL_WIDTH_20) \n\t\tchdef->width = ht ? NL80211_CHAN_WIDTH_20 : NL80211_CHAN_WIDTH_20_NOHT;\n\telse if (bw == CHANNEL_WIDTH_40)\n\t\tchdef->width = NL80211_CHAN_WIDTH_40;\n\telse if (bw == CHANNEL_WIDTH_80)\n\t\tchdef->width = NL80211_CHAN_WIDTH_80;\n\telse if (bw == CHANNEL_WIDTH_160)\n\t\tchdef->width = NL80211_CHAN_WIDTH_160;\n\telse {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tchdef->chan = chan;\n\tchdef->center_freq1 = cfreq;\n\tchdef->center_freq2 = 0;\n\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n\n#ifdef CONFIG_RTW_MESH\nstatic const char *nl80211_chan_width_str(enum nl80211_chan_width cwidth)\n{\n\tswitch (cwidth) {\n\tcase NL80211_CHAN_WIDTH_20_NOHT:\n\t\treturn \"20_NOHT\";\n\tcase NL80211_CHAN_WIDTH_20:\n\t\treturn \"20\";\n\tcase NL80211_CHAN_WIDTH_40:\n\t\treturn \"40\";\n\tcase NL80211_CHAN_WIDTH_80:\n\t\treturn \"80\";\n\tcase NL80211_CHAN_WIDTH_80P80:\n\t\treturn \"80+80\";\n\tcase NL80211_CHAN_WIDTH_160:\n\t\treturn \"160\";\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))\n\tcase NL80211_CHAN_WIDTH_5:\n\t\treturn \"5\";\n\tcase NL80211_CHAN_WIDTH_10:\n\t\treturn \"10\";\n#endif\n\tdefault:\n\t\treturn \"INVALID\";\n\t};\n}\n\nstatic void rtw_get_chbw_from_cfg80211_chan_def(struct cfg80211_chan_def *chdef, u8 *ht, u8 *ch, u8 *bw, u8 *offset)\n{\n\tint pri_freq;\n\tstruct ieee80211_channel *chan = chdef->chan;\n\n\tpri_freq = rtw_ch2freq(chan->hw_value);\n\tif (!pri_freq) {\n\t\tRTW_INFO(\"invalid channel:%d\\n\", chan->hw_value);\n\t\trtw_warn_on(1);\n\t\t*ch = 0;\n\t\treturn;\n\t}\t\t\n\n\tswitch (chdef->width) {\n\tcase NL80211_CHAN_WIDTH_20_NOHT:\n\t\t*ht = 0;\n\t\t*bw = CHANNEL_WIDTH_20;\n\t\t*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t*ch = chan->hw_value;\n\t\tbreak;\n\tcase NL80211_CHAN_WIDTH_20:\n\t\t*ht = 1;\n\t\t*bw = CHANNEL_WIDTH_20;\n\t\t*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t*ch = chan->hw_value;\n\t\tbreak;\n\tcase NL80211_CHAN_WIDTH_40:\n\t\t*ht = 1;\n\t\t*bw = CHANNEL_WIDTH_40;\n\t\t*offset = pri_freq > chdef->center_freq1 ? HAL_PRIME_CHNL_OFFSET_UPPER : HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\tif (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset))\n\t\t\t*ch = chan->hw_value;\n\t\tbreak;\n\tcase NL80211_CHAN_WIDTH_80:\n\t\t*ht = 1;\n\t\t*bw = CHANNEL_WIDTH_80;\n\t\tif (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset))\n\t\t\t*ch = chan->hw_value;\n\t\tbreak;\n\tcase NL80211_CHAN_WIDTH_160:\n\t\t*ht = 1;\n\t\t*bw = CHANNEL_WIDTH_160;\n\t\tif (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset))\n\t\t\t*ch = chan->hw_value;\n\t\tbreak;\n\tcase NL80211_CHAN_WIDTH_80P80:\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))\n\tcase NL80211_CHAN_WIDTH_5:\n\tcase NL80211_CHAN_WIDTH_10:\n\t#endif\n\tdefault:\n\t\t*ht = 0;\n\t\t*bw = CHANNEL_WIDTH_20;\n\t\t*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tRTW_INFO(\"unsupported cwidth:%s\\n\", nl80211_chan_width_str(chdef->width));\n\t\trtw_warn_on(1);\n\t};\n}\n#endif /* CONFIG_RTW_MESH */\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))\nstatic const char *nl80211_channel_type_str(enum nl80211_channel_type ctype)\n{\n\tswitch (ctype) {\n\tcase NL80211_CHAN_NO_HT:\n\t\treturn \"NO_HT\";\n\tcase NL80211_CHAN_HT20:\n\t\treturn \"HT20\";\n\tcase NL80211_CHAN_HT40MINUS:\n\t\treturn \"HT40-\";\n\tcase NL80211_CHAN_HT40PLUS:\n\t\treturn \"HT40+\";\n\tdefault:\n\t\treturn \"INVALID\";\n\t};\n}\n\nstatic enum nl80211_channel_type rtw_chbw_to_nl80211_channel_type(u8 ch, u8 bw, u8 offset, u8 ht)\n{\n\trtw_warn_on(!ht && (bw >= CHANNEL_WIDTH_40 || offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE));\n\n\tif (!ht)\n\t\treturn NL80211_CHAN_NO_HT;\n\tif (bw >= CHANNEL_WIDTH_40) {\n\t\tif (offset == HAL_PRIME_CHNL_OFFSET_UPPER)\n\t\t\treturn NL80211_CHAN_HT40MINUS;\n\t\telse if (offset == HAL_PRIME_CHNL_OFFSET_LOWER)\n\t\t\treturn NL80211_CHAN_HT40PLUS;\n\t\telse\n\t\t\trtw_warn_on(1);\n\t}\n\treturn NL80211_CHAN_HT20;\n}\n\nstatic void rtw_get_chbw_from_nl80211_channel_type(struct ieee80211_channel *chan, enum nl80211_channel_type ctype, u8 *ht, u8 *ch, u8 *bw, u8 *offset)\n{\n\tint pri_freq;\n\n\tpri_freq = rtw_ch2freq(chan->hw_value);\n\tif (!pri_freq) {\n\t\tRTW_INFO(\"invalid channel:%d\\n\", chan->hw_value);\n\t\trtw_warn_on(1);\n\t\t*ch = 0;\n\t\treturn;\n\t}\n\t*ch = chan->hw_value;\n\n\tswitch (ctype) {\n\tcase NL80211_CHAN_NO_HT:\n\t\t*ht = 0;\n\t\t*bw = CHANNEL_WIDTH_20;\n\t\t*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tbreak;\n\tcase NL80211_CHAN_HT20:\n\t\t*ht = 1;\n\t\t*bw = CHANNEL_WIDTH_20;\n\t\t*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tbreak;\n\tcase NL80211_CHAN_HT40MINUS:\n\t\t*ht = 1;\n\t\t*bw = CHANNEL_WIDTH_40;\n\t\t*offset = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\tbreak;\n\tcase NL80211_CHAN_HT40PLUS:\n\t\t*ht = 1;\n\t\t*bw = CHANNEL_WIDTH_40;\n\t\t*offset = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\tbreak;\n\tdefault:\n\t\t*ht = 0;\n\t\t*bw = CHANNEL_WIDTH_20;\n\t\t*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tRTW_INFO(\"unsupported ctype:%s\\n\", nl80211_channel_type_str(ctype));\n\t\trtw_warn_on(1);\n\t};\n}\n#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) */\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))\nbool rtw_cfg80211_allow_ch_switch_notify(_adapter *adapter)\n{\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0))\n\tif ((!MLME_IS_AP(adapter))\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0))\n\t\t&& (!MLME_IS_ADHOC(adapter))\n\t\t&& (!MLME_IS_ADHOC_MASTER(adapter))\n\t\t&& (!MLME_IS_MESH(adapter))\n#elif defined(CONFIG_RTW_MESH)\n\t\t&& (!MLME_IS_MESH(adapter))\n#endif\n\t\t)\n\t\treturn 0;\n#endif\n\treturn 1;\n}\n\nu8 rtw_cfg80211_ch_switch_notify(_adapter *adapter, u8 ch, u8 bw, u8 offset, u8 ht)\n{\n\tstruct wiphy *wiphy = adapter_to_wiphy(adapter);\n\tu8 ret = _SUCCESS;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))\n\tstruct cfg80211_chan_def chdef;\n\n\tif (!rtw_cfg80211_allow_ch_switch_notify(adapter))\n\t\tgoto exit;\n\n\tret = rtw_chbw_to_cfg80211_chan_def(wiphy, &chdef, ch, bw, offset, ht);\n\tif (ret != _SUCCESS)\n\t\tgoto exit;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 2) && LINUX_VERSION_CODE < KERNEL_VERSION(6, 9, 0))\n\tcfg80211_ch_switch_notify(adapter->pnetdev, &chdef, 0, 0);\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 9, 0))\n\tcfg80211_ch_switch_notify(adapter->pnetdev, &chdef, 0);\n#else\n\tcfg80211_ch_switch_notify(adapter->pnetdev, &chdef);\n#endif\n\n#else\n\tint freq = rtw_ch2freq(ch);\n\tenum nl80211_channel_type ctype;\n\n\tif (!rtw_cfg80211_allow_ch_switch_notify(adapter))\n\t\tgoto exit;\n\n\tif (!freq) {\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tctype = rtw_chbw_to_nl80211_channel_type(ch, bw, offset, ht);\n\tcfg80211_ch_switch_notify(adapter->pnetdev, freq, ctype);\n#endif\n\nexit:\n\treturn ret;\n}\n#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) */\n\nvoid rtw_2g_channels_init(struct ieee80211_channel *channels)\n{\n\t_rtw_memcpy((void *)channels, (void *)rtw_2ghz_channels, sizeof(rtw_2ghz_channels));\n}\n\nvoid rtw_5g_channels_init(struct ieee80211_channel *channels)\n{\n\t_rtw_memcpy((void *)channels, (void *)rtw_5ghz_a_channels, sizeof(rtw_5ghz_a_channels));\n}\n\nvoid rtw_2g_rates_init(struct ieee80211_rate *rates)\n{\n\t_rtw_memcpy(rates, rtw_g_rates,\n\t\tsizeof(struct ieee80211_rate) * RTW_G_RATES_NUM\n\t);\n}\n\nvoid rtw_5g_rates_init(struct ieee80211_rate *rates)\n{\n\t_rtw_memcpy(rates, rtw_a_rates,\n\t\tsizeof(struct ieee80211_rate) * RTW_A_RATES_NUM\n\t);\n}\n\nstruct ieee80211_supported_band *rtw_spt_band_alloc(BAND_TYPE band)\n{\n\tstruct ieee80211_supported_band *spt_band = NULL;\n\tint n_channels, n_bitrates;\n\n\tif (band == BAND_ON_2_4G) {\n\t\tn_channels = MAX_CHANNEL_NUM_2G;\n\t\tn_bitrates = RTW_G_RATES_NUM;\n\t} else if (band == BAND_ON_5G) {\n\t\tn_channels = MAX_CHANNEL_NUM_5G;\n\t\tn_bitrates = RTW_A_RATES_NUM;\n\t} else\n\t\tgoto exit;\n\n\tspt_band = (struct ieee80211_supported_band *)rtw_zmalloc(\n\t\tsizeof(struct ieee80211_supported_band)\n\t\t+ sizeof(struct ieee80211_channel) * n_channels\n\t\t+ sizeof(struct ieee80211_rate) * n_bitrates\n\t);\n\tif (!spt_band)\n\t\tgoto exit;\n\n\tspt_band->channels = (struct ieee80211_channel *)(((u8 *)spt_band) + sizeof(struct ieee80211_supported_band));\n\tspt_band->bitrates = (struct ieee80211_rate *)(((u8 *)spt_band->channels) + sizeof(struct ieee80211_channel) * n_channels);\n\tspt_band->band = rtw_band_to_nl80211_band(band);\n\tspt_band->n_channels = n_channels;\n\tspt_band->n_bitrates = n_bitrates;\n\n\tif (band == BAND_ON_2_4G) {\n\t\trtw_2g_channels_init(spt_band->channels);\n\t\trtw_2g_rates_init(spt_band->bitrates);\n\t} else if (band == BAND_ON_5G) {\n\t\trtw_5g_channels_init(spt_band->channels);\n\t\trtw_5g_rates_init(spt_band->bitrates);\n\t}\n\n\t/* spt_band.ht_cap */\n\nexit:\n\n\treturn spt_band;\n}\n\nvoid rtw_spt_band_free(struct ieee80211_supported_band *spt_band)\n{\n\tu32 size = 0;\n\n\tif (!spt_band)\n\t\treturn;\n\n\tif (spt_band->band == NL80211_BAND_2GHZ) {\n\t\tsize = sizeof(struct ieee80211_supported_band)\n\t\t\t+ sizeof(struct ieee80211_channel) * MAX_CHANNEL_NUM_2G\n\t\t\t+ sizeof(struct ieee80211_rate) * RTW_G_RATES_NUM;\n\t} else if (spt_band->band == NL80211_BAND_5GHZ) {\n\t\tsize = sizeof(struct ieee80211_supported_band)\n\t\t\t+ sizeof(struct ieee80211_channel) * MAX_CHANNEL_NUM_5G\n\t\t\t+ sizeof(struct ieee80211_rate) * RTW_A_RATES_NUM;\n\t} else {\n\n\t}\n\trtw_mfree((u8 *)spt_band, size);\n}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\nstatic const struct ieee80211_txrx_stypes\n\trtw_cfg80211_default_mgmt_stypes[NUM_NL80211_IFTYPES] = {\n\t[NL80211_IFTYPE_ADHOC] = {\n\t\t.tx = 0xffff,\n\t\t.rx = BIT(IEEE80211_STYPE_ACTION >> 4)\n\t},\n\t[NL80211_IFTYPE_STATION] = {\n\t\t.tx = 0xffff,\n\t\t.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |\n\t\tBIT(IEEE80211_STYPE_AUTH >> 4) |\n\t\tBIT(IEEE80211_STYPE_PROBE_REQ >> 4)\n\t},\n\t[NL80211_IFTYPE_AP] = {\n\t\t.tx = 0xffff,\n\t\t.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |\n\t\tBIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |\n\t\tBIT(IEEE80211_STYPE_PROBE_REQ >> 4) |\n\t\tBIT(IEEE80211_STYPE_DISASSOC >> 4) |\n\t\tBIT(IEEE80211_STYPE_AUTH >> 4) |\n\t\tBIT(IEEE80211_STYPE_DEAUTH >> 4) |\n\t\tBIT(IEEE80211_STYPE_ACTION >> 4)\n\t},\n\t[NL80211_IFTYPE_AP_VLAN] = {\n\t\t/* copy AP */\n\t\t.tx = 0xffff,\n\t\t.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |\n\t\tBIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |\n\t\tBIT(IEEE80211_STYPE_PROBE_REQ >> 4) |\n\t\tBIT(IEEE80211_STYPE_DISASSOC >> 4) |\n\t\tBIT(IEEE80211_STYPE_AUTH >> 4) |\n\t\tBIT(IEEE80211_STYPE_DEAUTH >> 4) |\n\t\tBIT(IEEE80211_STYPE_ACTION >> 4)\n\t},\n\t[NL80211_IFTYPE_P2P_CLIENT] = {\n\t\t.tx = 0xffff,\n\t\t.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |\n\t\tBIT(IEEE80211_STYPE_PROBE_REQ >> 4)\n\t},\n\t[NL80211_IFTYPE_P2P_GO] = {\n\t\t.tx = 0xffff,\n\t\t.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |\n\t\tBIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |\n\t\tBIT(IEEE80211_STYPE_PROBE_REQ >> 4) |\n\t\tBIT(IEEE80211_STYPE_DISASSOC >> 4) |\n\t\tBIT(IEEE80211_STYPE_AUTH >> 4) |\n\t\tBIT(IEEE80211_STYPE_DEAUTH >> 4) |\n\t\tBIT(IEEE80211_STYPE_ACTION >> 4)\n\t},\n#if defined(RTW_DEDICATED_P2P_DEVICE)\n\t[NL80211_IFTYPE_P2P_DEVICE] = {\n\t\t.tx = 0xffff,\n\t\t.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |\n\t\t\tBIT(IEEE80211_STYPE_PROBE_REQ >> 4)\n\t},\n#endif\n#if defined(CONFIG_RTW_MESH)\n\t[NL80211_IFTYPE_MESH_POINT] = {\n\t\t.tx = 0xffff,\n\t\t.rx = BIT(IEEE80211_STYPE_ACTION >> 4)\n\t\t\t| BIT(IEEE80211_STYPE_AUTH >> 4)\n\t},\n#endif\n\n};\n#endif\n\nNDIS_802_11_NETWORK_INFRASTRUCTURE nl80211_iftype_to_rtw_network_type(enum nl80211_iftype type)\n{\n\tswitch (type) {\n\tcase NL80211_IFTYPE_ADHOC:\n\t\treturn Ndis802_11IBSS;\n\n\t#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))\n\tcase NL80211_IFTYPE_P2P_CLIENT:\n\t#endif\n\tcase NL80211_IFTYPE_STATION:\n\t\treturn Ndis802_11Infrastructure;\n\n#ifdef CONFIG_AP_MODE\n\t#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))\n\tcase NL80211_IFTYPE_P2P_GO:\n\t#endif\n\tcase NL80211_IFTYPE_AP:\n\t\treturn Ndis802_11APMode;\n#endif\n\n#ifdef CONFIG_RTW_MESH\n\tcase NL80211_IFTYPE_MESH_POINT:\n\t\treturn Ndis802_11_mesh;\n#endif\n\n\tcase NL80211_IFTYPE_MONITOR:\n\t\treturn Ndis802_11Monitor;\n\n\tdefault:\n\t\treturn Ndis802_11InfrastructureMax;\n\t}\n}\n\nu32 nl80211_iftype_to_rtw_mlme_state(enum nl80211_iftype type)\n{\n\tswitch (type) {\n\tcase NL80211_IFTYPE_ADHOC:\n\t\treturn WIFI_ADHOC_STATE;\n\n\t#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))\n\tcase NL80211_IFTYPE_P2P_CLIENT:\n\t#endif\n\tcase NL80211_IFTYPE_STATION:\n\t\treturn WIFI_STATION_STATE;\n\n#ifdef CONFIG_AP_MODE\n\t#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))\n\tcase NL80211_IFTYPE_P2P_GO:\n\t#endif\n\tcase NL80211_IFTYPE_AP:\n\t\treturn WIFI_AP_STATE;\n#endif\n\n#ifdef CONFIG_RTW_MESH\n\tcase NL80211_IFTYPE_MESH_POINT:\n\t\treturn WIFI_MESH_STATE;\n#endif\n\n\tcase NL80211_IFTYPE_MONITOR:\n\t\treturn WIFI_MONITOR_STATE;\n\n\tdefault:\n\t\treturn WIFI_NULL_STATE;\n\t}\n}\n\nstatic int rtw_cfg80211_sync_iftype(_adapter *adapter)\n{\n\tstruct wireless_dev *rtw_wdev = adapter->rtw_wdev;\n\n\tif (!(nl80211_iftype_to_rtw_mlme_state(rtw_wdev->iftype) & MLME_STATE(adapter))) {\n\t\t/* iftype and mlme state is not syc */\n\t\tNDIS_802_11_NETWORK_INFRASTRUCTURE network_type;\n\n\t\tnetwork_type = nl80211_iftype_to_rtw_network_type(rtw_wdev->iftype);\n\t\tif (network_type != Ndis802_11InfrastructureMax) {\n\t\t\tif (rtw_pwr_wakeup(adapter) == _FAIL) {\n\t\t\t\tRTW_WARN(FUNC_ADPT_FMT\" call rtw_pwr_wakeup fail\\n\", FUNC_ADPT_ARG(adapter));\n\t\t\t\treturn _FAIL;\n\t\t\t}\n\n\t\t\trtw_set_802_11_infrastructure_mode(adapter, network_type);\n\t\t\trtw_setopmode_cmd(adapter, network_type, RTW_CMDF_WAIT_ACK);\n\t\t} else {\n\t\t\trtw_warn_on(1);\n\t\t\tRTW_WARN(FUNC_ADPT_FMT\" iftype:%u is not support\\n\", FUNC_ADPT_ARG(adapter), rtw_wdev->iftype);\n\t\t\treturn _FAIL;\n\t\t}\n\t}\n\n\treturn _SUCCESS;\n}\n\nstatic u64 rtw_get_systime_us(void)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0))\n\treturn ktime_to_us(ktime_get_boottime());\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39))\n\tstruct timespec ts;\n\tget_monotonic_boottime(&ts);\n\treturn ((u64)ts.tv_sec * 1000000) + ts.tv_nsec / 1000;\n#else\n\tstruct timeval tv;\n\tdo_gettimeofday(&tv);\n\treturn ((u64)tv.tv_sec * 1000000) + tv.tv_usec;\n#endif\n}\n\n/* Try to remove non target BSS's SR to reduce PBC overlap rate */\nstatic int rtw_cfg80211_clear_wps_sr_of_non_target_bss(_adapter *padapter, struct wlan_network *pnetwork, struct cfg80211_ssid *req_ssid)\n{\n\tint ret = 0;\n\tu8 *psr = NULL, sr = 0;\n\tNDIS_802_11_SSID *pssid = &pnetwork->network.Ssid;\n\tu32 wpsielen = 0;\n\tu8 *wpsie = NULL;\n\n\tif (pssid->SsidLength == req_ssid->ssid_len\n\t\t&& _rtw_memcmp(pssid->Ssid, req_ssid->ssid, req_ssid->ssid_len) == _TRUE)\n\t\tgoto exit;\n\n\twpsie = rtw_get_wps_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_\n\t\t, pnetwork->network.IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen);\n\tif (wpsie && wpsielen > 0)\n\t\tpsr = rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_SELECTED_REGISTRAR, &sr, NULL);\n\n\tif (psr && sr) {\n\t\tif (0)\n\t\t\tRTW_INFO(\"clear sr of non target bss:%s(\"MAC_FMT\")\\n\"\n\t\t\t\t, pssid->Ssid, MAC_ARG(pnetwork->network.MacAddress));\n\t\t*psr = 0; /* clear sr */\n\t\tret = 1;\n\t}\n\nexit:\n\treturn ret;\n}\n\n#define MAX_BSSINFO_LEN 1000\nstruct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork)\n{\n\tstruct ieee80211_channel *notify_channel;\n\tstruct cfg80211_bss *bss = NULL;\n\t/* struct ieee80211_supported_band *band;       */\n\tu16 channel;\n\tu32 freq;\n\tu64 notify_timestamp;\n\tu16 notify_capability;\n\tu16 notify_interval;\n\tu8 *notify_ie;\n\tsize_t notify_ielen;\n\ts32 notify_signal;\n\t/* u8 buf[MAX_BSSINFO_LEN]; */\n\n\tu8 *pbuf;\n\tsize_t buf_size = MAX_BSSINFO_LEN;\n\tsize_t len, bssinf_len = 0;\n\tstruct rtw_ieee80211_hdr *pwlanhdr;\n\tunsigned short *fctrl;\n\tu8\tbc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\n\tstruct wireless_dev *wdev = padapter->rtw_wdev;\n\tstruct wiphy *wiphy = wdev->wiphy;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\tpbuf = rtw_zmalloc(buf_size);\n\tif (pbuf == NULL) {\n\t\tRTW_INFO(\"%s pbuf allocate failed  !!\\n\", __FUNCTION__);\n\t\treturn bss;\n\t}\n\n\t/* RTW_INFO(\"%s\\n\", __func__); */\n\n\tbssinf_len = pnetwork->network.IELength + sizeof(struct rtw_ieee80211_hdr_3addr);\n\tif (bssinf_len > buf_size) {\n\t\tRTW_INFO(\"%s IE Length too long > %zu byte\\n\", __FUNCTION__, buf_size);\n\t\tgoto exit;\n\t}\n\n#ifndef CONFIG_WAPI_SUPPORT\n\t{\n\t\tu16 wapi_len = 0;\n\n\t\tif (rtw_get_wapi_ie(pnetwork->network.IEs, pnetwork->network.IELength, NULL, &wapi_len) > 0) {\n\t\t\tif (wapi_len > 0) {\n\t\t\t\tRTW_INFO(\"%s, no support wapi!\\n\", __FUNCTION__);\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\t}\n#endif /* !CONFIG_WAPI_SUPPORT */\n\n\tchannel = pnetwork->network.Configuration.DSConfig;\n\tfreq = rtw_ch2freq(channel);\n\tnotify_channel = ieee80211_get_channel(wiphy, freq);\n\n\tif (0)\n\t\tnotify_timestamp = le64_to_cpu(*(u64 *)rtw_get_timestampe_from_ie(pnetwork->network.IEs));\n\telse\n\t\tnotify_timestamp = rtw_get_systime_us();\n\n\tnotify_interval = le16_to_cpu(*(u16 *)rtw_get_beacon_interval_from_ie(pnetwork->network.IEs));\n\tnotify_capability = le16_to_cpu(*(u16 *)rtw_get_capability_from_ie(pnetwork->network.IEs));\n\n\tnotify_ie = pnetwork->network.IEs + _FIXED_IE_LENGTH_;\n\tnotify_ielen = pnetwork->network.IELength - _FIXED_IE_LENGTH_;\n\n\t/* We've set wiphy's signal_type as CFG80211_SIGNAL_TYPE_MBM: signal strength in mBm (100*dBm) */\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE &&\n\t\tis_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) {\n\t\tnotify_signal = 100 * translate_percentage_to_dbm(padapter->recvpriv.signal_strength); /* dbm */\n\t} else {\n\t\tnotify_signal = 100 * translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength); /* dbm */\n\t}\n\n#if 0\n\tRTW_INFO(\"bssid: \"MAC_FMT\"\\n\", MAC_ARG(pnetwork->network.MacAddress));\n\tRTW_INFO(\"Channel: %d(%d)\\n\", channel, freq);\n\tRTW_INFO(\"Capability: %X\\n\", notify_capability);\n\tRTW_INFO(\"Beacon interval: %d\\n\", notify_interval);\n\tRTW_INFO(\"Signal: %d\\n\", notify_signal);\n\tRTW_INFO(\"notify_timestamp: %llu\\n\", notify_timestamp);\n#endif\n\n\t/* pbuf = buf; */\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pbuf;\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\tSetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);\n\t/* pmlmeext->mgnt_seq++; */\n\n\tif (pnetwork->network.Reserved[0] == BSS_TYPE_BCN) { /* WIFI_BEACON */\n\t\t_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);\n\t\tset_frame_sub_type(pbuf, WIFI_BEACON);\n\t} else {\n\t\t_rtw_memcpy(pwlanhdr->addr1, adapter_mac_addr(padapter), ETH_ALEN);\n\t\tset_frame_sub_type(pbuf, WIFI_PROBERSP);\n\t}\n\n\t_rtw_memcpy(pwlanhdr->addr2, pnetwork->network.MacAddress, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, pnetwork->network.MacAddress, ETH_ALEN);\n\n\n\t/* pbuf += sizeof(struct rtw_ieee80211_hdr_3addr); */\n\tlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\t_rtw_memcpy((pbuf + len), pnetwork->network.IEs, pnetwork->network.IELength);\n\t*((u64 *)(pbuf + len)) = cpu_to_le64(notify_timestamp);\n\n\tlen += pnetwork->network.IELength;\n\n\t#if defined(CONFIG_P2P) && 0\n\tif(rtw_get_p2p_ie(pnetwork->network.IEs+12, pnetwork->network.IELength-12, NULL, NULL))\n\t\tRTW_INFO(\"%s, got p2p_ie\\n\", __func__);\n\t#endif\n\n#if 1\n\tbss = cfg80211_inform_bss_frame(wiphy, notify_channel, (struct ieee80211_mgmt *)pbuf,\n\t\t\t\t\tlen, notify_signal, GFP_ATOMIC);\n#else\n\n\tbss = cfg80211_inform_bss(wiphy, notify_channel, (const u8 *)pnetwork->network.MacAddress,\n\t\tnotify_timestamp, notify_capability, notify_interval, notify_ie,\n\t\tnotify_ielen, notify_signal, GFP_ATOMIC/*GFP_KERNEL*/);\n#endif\n\n\tif (unlikely(!bss)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" bss NULL\\n\", FUNC_ADPT_ARG(padapter));\n\t\tgoto exit;\n\t}\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 38))\n#ifndef COMPAT_KERNEL_RELEASE\n\t/* patch for cfg80211, update beacon ies to information_elements */\n\tif (pnetwork->network.Reserved[0] == BSS_TYPE_BCN) { /* WIFI_BEACON */\n\n\t\tif (bss->len_information_elements != bss->len_beacon_ies) {\n\t\t\tbss->information_elements = bss->beacon_ies;\n\t\t\tbss->len_information_elements =  bss->len_beacon_ies;\n\t\t}\n\t}\n#endif /* COMPAT_KERNEL_RELEASE */\n#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 38) */\n\n#if 0\n\t{\n\t\tif (bss->information_elements == bss->proberesp_ies) {\n\t\t\tif (bss->len_information_elements !=  bss->len_proberesp_ies)\n\t\t\t\tRTW_INFO(\"error!, len_information_elements != bss->len_proberesp_ies\\n\");\n\t\t} else if (bss->len_information_elements <  bss->len_beacon_ies) {\n\t\t\tbss->information_elements = bss->beacon_ies;\n\t\t\tbss->len_information_elements =  bss->len_beacon_ies;\n\t\t}\n\t}\n#endif\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)\n\tcfg80211_put_bss(wiphy, bss);\n#else\n\tcfg80211_put_bss(bss);\n#endif\n\nexit:\n\tif (pbuf)\n\t\trtw_mfree(pbuf, buf_size);\n\treturn bss;\n\n}\n\n/*\n\tCheck the given bss is valid by kernel API cfg80211_get_bss()\n\t@padapter : the given adapter\n\n\treturn _TRUE if bss is valid,  _FALSE for not found.\n*/\nint rtw_cfg80211_check_bss(_adapter *padapter)\n{\n\tWLAN_BSSID_EX  *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network);\n\tstruct cfg80211_bss *bss = NULL;\n\tstruct ieee80211_channel *notify_channel = NULL;\n\tu32 freq;\n\n\tif (!(pnetwork) || !(padapter->rtw_wdev))\n\t\treturn _FALSE;\n\n\tfreq = rtw_ch2freq(pnetwork->Configuration.DSConfig);\n\tnotify_channel = ieee80211_get_channel(padapter->rtw_wdev->wiphy, freq);\n\tbss = cfg80211_get_bss(padapter->rtw_wdev->wiphy, notify_channel,\n\t\t\tpnetwork->MacAddress, pnetwork->Ssid.Ssid,\n\t\t\tpnetwork->Ssid.SsidLength,\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)\n\t\t\tpnetwork->InfrastructureMode == Ndis802_11Infrastructure?IEEE80211_BSS_TYPE_ESS:IEEE80211_BSS_TYPE_IBSS,\n\t\t\tIEEE80211_PRIVACY(pnetwork->Privacy));\n#else\n\t\t\tpnetwork->InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS, pnetwork->InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS);\n#endif\n\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)\n\tcfg80211_put_bss(padapter->rtw_wdev->wiphy, bss);\n#else\n\tcfg80211_put_bss(bss);\n#endif\n\n\treturn bss != NULL;\n}\n\nvoid rtw_cfg80211_ibss_indicate_connect(_adapter *padapter)\n{\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct wlan_network  *cur_network = &(pmlmepriv->cur_network);\n\tstruct wireless_dev *pwdev = padapter->rtw_wdev;\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))\n\tstruct wiphy *wiphy = pwdev->wiphy;\n\tint freq = 2412;\n\tstruct ieee80211_channel *notify_channel;\n#endif\n\n\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n\n\tif (pwdev->iftype != NL80211_IFTYPE_ADHOC)\n\t\treturn;\n\n\tif (!rtw_cfg80211_check_bss(padapter)) {\n\t\tWLAN_BSSID_EX  *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network);\n\t\tstruct wlan_network *scanned = pmlmepriv->cur_network_scanned;\n\n\t\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) {\n\n\t\t\t_rtw_memcpy(&cur_network->network, pnetwork, sizeof(WLAN_BSSID_EX));\n\t\t\tif (cur_network) {\n\t\t\t\tif (!rtw_cfg80211_inform_bss(padapter, cur_network))\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" inform fail !!\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\t\telse\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" inform success !!\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\t} else {\n\t\t\t\tRTW_INFO(\"cur_network is not exist!!!\\n\");\n\t\t\t\treturn ;\n\t\t\t}\n\t\t} else {\n\t\t\tif (scanned == NULL)\n\t\t\t\trtw_warn_on(1);\n\n\t\t\tif (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE\n\t\t\t\t&& _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE\n\t\t\t) {\n\t\t\t\tif (!rtw_cfg80211_inform_bss(padapter, scanned))\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" inform fail !!\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\t\telse {\n\t\t\t\t\t/* RTW_INFO(FUNC_ADPT_FMT\" inform success !!\\n\", FUNC_ADPT_ARG(padapter)); */\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tRTW_INFO(\"scanned & pnetwork compare fail\\n\");\n\t\t\t\trtw_warn_on(1);\n\t\t\t}\n\t\t}\n\n\t\tif (!rtw_cfg80211_check_bss(padapter))\n\t\t\tRTW_PRINT(FUNC_ADPT_FMT\" BSS not found !!\\n\", FUNC_ADPT_ARG(padapter));\n\t}\n\t/* notify cfg80211 that device joined an IBSS */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))\n\tfreq = rtw_ch2freq(cur_network->network.Configuration.DSConfig);\n\tif (1)\n\t\tRTW_INFO(\"chan: %d, freq: %d\\n\", cur_network->network.Configuration.DSConfig, freq);\n\tnotify_channel = ieee80211_get_channel(wiphy, freq);\n\tcfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, notify_channel, GFP_ATOMIC);\n#else\n\tcfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, GFP_ATOMIC);\n#endif\n}\n\nvoid rtw_cfg80211_indicate_connect(_adapter *padapter)\n{\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct wlan_network  *cur_network = &(pmlmepriv->cur_network);\n\tstruct wireless_dev *pwdev = padapter->rtw_wdev;\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n\t_irqL irqL;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n#endif\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)\n\tstruct cfg80211_roam_info roam_info ={};\n#endif\n\n\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n\tif (pwdev->iftype != NL80211_IFTYPE_STATION\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\t\t&& pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT\n\t\t#endif\n\t)\n\t\treturn;\n\n\tif (!MLME_IS_STA(padapter))\n\t\treturn;\n\n#ifdef CONFIG_P2P\n\tif (pwdinfo->driver_interface == DRIVER_CFG80211) {\n\t\t#if !RTW_P2P_GROUP_INTERFACE\n\t\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {\n\t\t\trtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));\n\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);\n\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);\n\t\t\tRTW_INFO(\"%s, role=%d, p2p_state=%d, pre_p2p_state=%d\\n\", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo));\n\t\t}\n\t\t#endif\n\t}\n#endif /* CONFIG_P2P */\n\n\tif (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE) {\n\t\tWLAN_BSSID_EX  *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network);\n\t\tstruct wlan_network *scanned = pmlmepriv->cur_network_scanned;\n\n\t\t/* RTW_INFO(FUNC_ADPT_FMT\" BSS not found\\n\", FUNC_ADPT_ARG(padapter)); */\n\n\t\tif (scanned == NULL) {\n\t\t\trtw_warn_on(1);\n\t\t\tgoto check_bss;\n\t\t}\n\n\t\tif (_rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE\n\t\t\t&& _rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE\n\t\t) {\n\t\t\tif (!rtw_cfg80211_inform_bss(padapter, scanned))\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" inform fail !!\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\telse {\n\t\t\t\t/* RTW_INFO(FUNC_ADPT_FMT\" inform success !!\\n\", FUNC_ADPT_ARG(padapter)); */\n\t\t\t}\n\t\t} else {\n\t\t\tRTW_INFO(\"scanned: %s(\"MAC_FMT\"), cur: %s(\"MAC_FMT\")\\n\",\n\t\t\t\tscanned->network.Ssid.Ssid, MAC_ARG(scanned->network.MacAddress),\n\t\t\t\tpnetwork->Ssid.Ssid, MAC_ARG(pnetwork->MacAddress)\n\t\t\t);\n\t\t\trtw_warn_on(1);\n\t\t}\n\t}\n\ncheck_bss:\n\tif (!rtw_cfg80211_check_bss(padapter))\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" BSS not found !!\\n\", FUNC_ADPT_ARG(padapter));\n\n\t_enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL);\n\n\tif (rtw_to_roam(padapter) > 0) {\n\t\t#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE)\n\t\tstruct wiphy *wiphy = pwdev->wiphy;\n\t\tstruct ieee80211_channel *notify_channel;\n\t\tu32 freq;\n\t\tu16 channel = cur_network->network.Configuration.DSConfig;\n\n\t\tfreq = rtw_ch2freq(channel);\n\t\tnotify_channel = ieee80211_get_channel(wiphy, freq);\n\t\t#endif\n\n\t\t#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0))\n\t\troam_info.links[0].bssid = cur_network->network.MacAddress;\n\t\t#else\n\t\troam_info.bssid = cur_network->network.MacAddress;\n\t\t#endif\n\t\troam_info.req_ie = pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2;\n\t\troam_info.req_ie_len = pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2;\n\t\troam_info.resp_ie = pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6;\n\t\troam_info.resp_ie_len = pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6;\n\n\t\tcfg80211_roamed(padapter->pnetdev, &roam_info, GFP_ATOMIC);\n\t\t#else\n\t\tcfg80211_roamed(padapter->pnetdev\n\t\t\t#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE)\n\t\t\t, notify_channel\n\t\t\t#endif\n\t\t\t, cur_network->network.MacAddress\n\t\t\t, pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2\n\t\t\t, pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2\n\t\t\t, pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6\n\t\t\t, pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6\n\t\t\t, GFP_ATOMIC);\n\t\t#endif /*LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)*/\n\n\t\tRTW_INFO(FUNC_ADPT_FMT\" call cfg80211_roamed\\n\", FUNC_ADPT_ARG(padapter));\n\n#ifdef CONFIG_RTW_80211R\n\t\tif (rtw_ft_roam(padapter))\n\t\t\trtw_ft_set_status(padapter, RTW_FT_ASSOCIATED_STA);\n#endif\n\t} else {\n\t\t#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE)\n\t\tRTW_INFO(\"pwdev->sme_state(b)=%d\\n\", pwdev->sme_state);\n\t\t#endif\n\n\t\tif (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE)\n\t\t\trtw_cfg80211_connect_result(pwdev, cur_network->network.MacAddress\n\t\t\t\t, pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2\n\t\t\t\t, pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2\n\t\t\t\t, pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6\n\t\t\t\t, pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6\n\t\t\t\t, WLAN_STATUS_SUCCESS, GFP_ATOMIC);\n\t\t#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE)\n\t\tRTW_INFO(\"pwdev->sme_state(a)=%d\\n\", pwdev->sme_state);\n\t\t#endif\n\t}\n\n\trtw_wdev_free_connect_req(pwdev_priv);\n\n\t_exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL);\n}\n\nvoid rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated)\n{\n\tstruct wireless_dev *pwdev = padapter->rtw_wdev;\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n\t_irqL irqL;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n#endif\n\n\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n\n\t/*always replace privated definitions with wifi reserved value 0*/\n\tif (WLAN_REASON_IS_PRIVATE(reason))\n\t\treason = 0;\n\n\tif (pwdev->iftype != NL80211_IFTYPE_STATION\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\t\t&& pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT\n\t\t#endif\n\t)\n\t\treturn;\n\n\tif (!MLME_IS_STA(padapter))\n\t\treturn;\n\n#ifdef CONFIG_P2P\n\tif (pwdinfo->driver_interface == DRIVER_CFG80211) {\n\t\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {\n\t\t\trtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));\n\n\t\t\t#if RTW_P2P_GROUP_INTERFACE\n\t\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\t\t\tif (pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT)\n\t\t\t#endif\n\t\t\t#endif\n\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);\n\n\t\t\tRTW_INFO(\"%s, role=%d, p2p_state=%d, pre_p2p_state=%d\\n\", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo));\n\t\t}\n\t}\n#endif /* CONFIG_P2P */\n\n\t_enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL);\n\n\tif (padapter->ndev_unregistering || !rtw_wdev_not_indic_disco(pwdev_priv)) {\n\t\t#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE)\n\t\tRTW_INFO(\"pwdev->sme_state(b)=%d\\n\", pwdev->sme_state);\n\n\t\tif (pwdev->sme_state == CFG80211_SME_CONNECTING) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" call cfg80211_connect_result\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\trtw_cfg80211_connect_result(pwdev, NULL, NULL, 0, NULL, 0,\n\t\t\t\treason?reason:WLAN_STATUS_UNSPECIFIED_FAILURE,\n\t\t\t\tGFP_ATOMIC);\n\t\t} else if (pwdev->sme_state == CFG80211_SME_CONNECTED) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" call cfg80211_disconnected\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\trtw_cfg80211_disconnected(pwdev, reason, NULL, 0, locally_generated, GFP_ATOMIC);\n\t\t}\n\n\t\tRTW_INFO(\"pwdev->sme_state(a)=%d\\n\", pwdev->sme_state);\n\t\t#else\n\t\tif (pwdev_priv->connect_req) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" call cfg80211_connect_result\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\trtw_cfg80211_connect_result(pwdev, NULL, NULL, 0, NULL, 0,\n\t\t\t\treason?reason:WLAN_STATUS_UNSPECIFIED_FAILURE,\n\t\t\t\tGFP_ATOMIC);\n\t\t} else {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" call cfg80211_disconnected\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\trtw_cfg80211_disconnected(pwdev, reason, NULL, 0, locally_generated, GFP_ATOMIC);\n\t\t}\n\t\t#endif\n\t}\n\n\trtw_wdev_free_connect_req(pwdev_priv);\n\n\t_exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL);\n}\n\n\n#ifdef CONFIG_AP_MODE\nstatic int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_param *param)\n{\n\tint ret = 0;\n\tu32 wep_key_idx, wep_key_len;\n\tstruct sta_info *psta = NULL, *pbcmc_sta = NULL;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct security_priv *psecuritypriv = &(padapter->securitypriv);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\tparam->u.crypt.err = 0;\n\tparam->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\\0';\n\n\tif (is_broadcast_mac_addr(param->sta_addr)) {\n\t\tif (param->u.crypt.idx >= WEP_KEYS\n\t\t\t#ifdef CONFIG_IEEE80211W\n\t\t\t&& param->u.crypt.idx > BIP_MAX_KEYID\n\t\t\t#endif\n\t\t) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t} else {\n\t\tpsta = rtw_get_stainfo(pstapriv, param->sta_addr);\n\t\tif (!psta) {\n\t\t\tret = -EINVAL;\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\", sta \"MAC_FMT\" not found\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(param->sta_addr));\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\tif (strcmp(param->u.crypt.alg, \"none\") == 0 && (psta == NULL)) {\n\t\t/* todo:clear default encryption keys */\n\n\t\tRTW_INFO(\"clear default encryption keys, keyid=%d\\n\", param->u.crypt.idx);\n\n\t\tgoto exit;\n\t}\n\n\n\tif (strcmp(param->u.crypt.alg, \"WEP\") == 0 && (psta == NULL)) {\n\t\tRTW_INFO(\"r871x_set_encryption, crypt.alg = WEP\\n\");\n\n\t\twep_key_idx = param->u.crypt.idx;\n\t\twep_key_len = param->u.crypt.key_len;\n\n\t\tRTW_INFO(\"r871x_set_encryption, wep_key_idx=%d, len=%d\\n\", wep_key_idx, wep_key_len);\n\n\t\tif ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (wep_key_len > 0)\n\t\t\twep_key_len = wep_key_len <= 5 ? 5 : 13;\n\n\t\tif (psecuritypriv->bWepDefaultKeyIdxSet == 0) {\n\t\t\t/* wep default key has not been set, so use this key index as default key. */\n\n\t\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;\n\t\t\tpsecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;\n\t\t\tpsecuritypriv->dot11PrivacyAlgrthm = _WEP40_;\n\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _WEP40_;\n\n\t\t\tif (wep_key_len == 13) {\n\t\t\t\tpsecuritypriv->dot11PrivacyAlgrthm = _WEP104_;\n\t\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _WEP104_;\n\t\t\t}\n\n\t\t\tpsecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;\n\t\t}\n\n\t\t_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len);\n\n\t\tpsecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len;\n\n\t\trtw_ap_set_wep_key(padapter, param->u.crypt.key, wep_key_len, wep_key_idx, 1);\n\n\t\tgoto exit;\n\n\t}\n\n\tif (!psta) { /* group key */\n\t\tif (param->u.crypt.set_tx == 0) { /* group key, TX only */\n\t\t\tif (strcmp(param->u.crypt.alg, \"WEP\") == 0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set WEP TX GTK idx:%u, len:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\t_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\t\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _WEP40_;\n\t\t\t\tif (param->u.crypt.key_len == 13)\n\t\t\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _WEP104_;\n\n\t\t\t} else if (strcmp(param->u.crypt.alg, \"TKIP\") == 0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set TKIP TX GTK idx:%u, len:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _TKIP_;\n\t\t\t\t_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\t\t\t\t/* set mic key */\n\t\t\t\t_rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);\n\t\t\t\t_rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);\n\t\t\t\tpsecuritypriv->busetkipkey = _TRUE;\n\n\t\t\t} else if (strcmp(param->u.crypt.alg, \"CCMP\") == 0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set CCMP TX GTK idx:%u, len:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _AES_;\n\t\t\t\t_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\n\t\t\t#ifdef CONFIG_IEEE80211W\n\t\t\t} else if (strcmp(param->u.crypt.alg, \"BIP\") == 0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set TX IGTK idx:%u, len:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\t_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\t\t\t\tpadapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx;\n\t\t\t\tpsecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq);\n\t\t\t\tpadapter->securitypriv.binstallBIPkey = _TRUE;\n\t\t\t\tgoto exit;\n\t\t\t#endif /* CONFIG_IEEE80211W */\n\n\t\t\t} else if (strcmp(param->u.crypt.alg, \"none\") == 0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" clear group key, idx:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), param->u.crypt.idx);\n\t\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;\n\t\t\t} else {\n\t\t\t\tRTW_WARN(FUNC_ADPT_FMT\" set group key, not support\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter));\n\t\t\t\tgoto exit;\n\t\t\t}\n\n\t\t\tpsecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx;\n\t\t\tpbcmc_sta = rtw_get_bcmc_stainfo(padapter);\n\t\t\tif (pbcmc_sta) {\n\t\t\t\tpbcmc_sta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);\n\t\t\t\tpbcmc_sta->ieee8021x_blocked = _FALSE;\n\t\t\t\tpbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy\t\t\t */\n\t\t\t}\n\t\t\tpsecuritypriv->binstallGrpkey = _TRUE;\n\t\t\tpsecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */\n\n\t\t\trtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx);\n\t\t}\n\n\t\tgoto exit;\n\n\t}\n\n\tif (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) { /* psk/802_1x */\n\t\tif (param->u.crypt.set_tx == 1) {\n\t\t\t/* pairwise key */\n\t\t\t_rtw_memcpy(psta->dot118021x_UncstKey.skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\n\t\t\tif (strcmp(param->u.crypt.alg, \"WEP\") == 0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set WEP PTK of \"MAC_FMT\" idx:%u, len:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)\n\t\t\t\t\t, param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\tpsta->dot118021XPrivacy = _WEP40_;\n\t\t\t\tif (param->u.crypt.key_len == 13)\n\t\t\t\t\tpsta->dot118021XPrivacy = _WEP104_;\n\n\t\t\t} else if (strcmp(param->u.crypt.alg, \"TKIP\") == 0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set TKIP PTK of \"MAC_FMT\" idx:%u, len:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)\n\t\t\t\t\t, param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\tpsta->dot118021XPrivacy = _TKIP_;\n\t\t\t\t/* set mic key */\n\t\t\t\t_rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);\n\t\t\t\t_rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);\n\t\t\t\tpsecuritypriv->busetkipkey = _TRUE;\n\n\t\t\t} else if (strcmp(param->u.crypt.alg, \"CCMP\") == 0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set CCMP PTK of \"MAC_FMT\" idx:%u, len:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)\n\t\t\t\t\t, param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\tpsta->dot118021XPrivacy = _AES_;\n\n\t\t\t} else if (strcmp(param->u.crypt.alg, \"none\") == 0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" clear pairwise key of \"MAC_FMT\" idx:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)\n\t\t\t\t\t, param->u.crypt.idx);\n\t\t\t\tpsta->dot118021XPrivacy = _NO_PRIVACY_;\n\t\t\t} else {\n\t\t\t\tRTW_WARN(FUNC_ADPT_FMT\" set pairwise key of \"MAC_FMT\", not support\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));\n\t\t\t\tgoto exit;\n\t\t\t}\n\n\t\t\tpsta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);\n\t\t\tpsta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq);\n\t\t\tpsta->ieee8021x_blocked = _FALSE;\n\n\t\t\tif (psta->dot118021XPrivacy != _NO_PRIVACY_) {\n\t\t\t\tpsta->bpairwise_key_installed = _TRUE;\n\n\t\t\t\t/* WPA2 key-handshake has completed */\n\t\t\t\tif (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK)\n\t\t\t\t\tpsta->state &= (~WIFI_UNDER_KEY_HANDSHAKE);\n\t\t\t}\n\n\t\t\trtw_ap_set_pairwise_key(padapter, psta);\n\t\t} else {\n\t\t\t/* peer's group key, RX only */\n\t\t\t#ifdef CONFIG_RTW_MESH\n\t\t\tif (strcmp(param->u.crypt.alg, \"CCMP\") == 0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set CCMP GTK of \"MAC_FMT\", idx:%u, len:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)\n\t\t\t\t\t, param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\tpsta->group_privacy = _AES_;\n\t\t\t\t_rtw_memcpy(psta->gtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\t\t\t\tpsta->gtk_bmp |= BIT(param->u.crypt.idx);\n\t\t\t\tpsta->gtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);\n\n\t\t\t#ifdef CONFIG_IEEE80211W\n\t\t\t} else if (strcmp(param->u.crypt.alg, \"BIP\") == 0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set IGTK of \"MAC_FMT\", idx:%u, len:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)\n\t\t\t\t\t, param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\t_rtw_memcpy(psta->igtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\t\t\t\tpsta->igtk_bmp |= BIT(param->u.crypt.idx);\n\t\t\t\tpsta->igtk_id = param->u.crypt.idx;\n\t\t\t\tpsta->igtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);\n\t\t\t\tgoto exit;\n\t\t\t#endif /* CONFIG_IEEE80211W */\n\n\t\t\t} else if (strcmp(param->u.crypt.alg, \"none\") == 0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" clear group key of \"MAC_FMT\", idx:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)\n\t\t\t\t\t, param->u.crypt.idx);\n\t\t\t\tpsta->group_privacy = _NO_PRIVACY_;\n\t\t\t\tpsta->gtk_bmp &= ~BIT(param->u.crypt.idx);\n\t\t\t} else\n\t\t\t#endif /* CONFIG_RTW_MESH */\n\t\t\t{\n\t\t\t\tRTW_WARN(FUNC_ADPT_FMT\" set group key of \"MAC_FMT\", not support\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));\n\t\t\t\tgoto exit;\n\t\t\t}\n\n\t\t\t#ifdef CONFIG_RTW_MESH\n\t\t\trtw_ap_set_sta_key(padapter, psta->cmn.mac_addr, psta->group_privacy\n\t\t\t\t, param->u.crypt.key, param->u.crypt.idx, 1);\n\t\t\t#endif\n\t\t}\n\n\t}\n\nexit:\n\treturn ret;\n}\n#endif /* CONFIG_AP_MODE */\n__attribute__((no_sanitize(\"bounds\")))\nstatic int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param *param)\n{\n\tint ret = 0;\n\tu32 wep_key_idx, wep_key_len;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *pwdinfo = &padapter->wdinfo;\n#endif /* CONFIG_P2P */\n\n\tRTW_INFO(\"%s\\n\", __func__);\n\n\tparam->u.crypt.err = 0;\n\tparam->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\\0';\n\n\tif (is_broadcast_mac_addr(param->sta_addr)) {\n\t\tif (param->u.crypt.idx >= WEP_KEYS\n\t\t\t#ifdef CONFIG_IEEE80211W\n\t\t\t&& param->u.crypt.idx > BIP_MAX_KEYID\n\t\t\t#endif\n\t\t) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t} else {\n#ifdef CONFIG_WAPI_SUPPORT\n\t\tif (strcmp(param->u.crypt.alg, \"SMS4\"))\n#endif\n\t\t{\n\t\t\tret = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\tif (strcmp(param->u.crypt.alg, \"WEP\") == 0) {\n\t\tRTW_INFO(\"wpa_set_encryption, crypt.alg = WEP\\n\");\n\n\t\twep_key_idx = param->u.crypt.idx;\n\t\twep_key_len = param->u.crypt.key_len;\n\n\t\tif ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (psecuritypriv->bWepDefaultKeyIdxSet == 0) {\n\t\t\t/* wep default key has not been set, so use this key index as default key. */\n\n\t\t\twep_key_len = wep_key_len <= 5 ? 5 : 13;\n\n\t\t\tpsecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;\n\t\t\tpsecuritypriv->dot11PrivacyAlgrthm = _WEP40_;\n\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _WEP40_;\n\n\t\t\tif (wep_key_len == 13) {\n\t\t\t\tpsecuritypriv->dot11PrivacyAlgrthm = _WEP104_;\n\t\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _WEP104_;\n\t\t\t}\n\n\t\t\tpsecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;\n\t\t}\n\n\t\t_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len);\n\n\t\tpsecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len;\n\n\t\trtw_set_key(padapter, psecuritypriv, wep_key_idx, 0, _TRUE);\n\n\t\tgoto exit;\n\t}\n\n\tif (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { /* 802_1x */\n\t\tstruct sta_info *psta, *pbcmc_sta;\n\t\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\t\t/* RTW_INFO(\"%s, : dot11AuthAlgrthm == dot11AuthAlgrthm_8021X\\n\", __func__); */\n\n\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) { /* sta mode */\n#ifdef CONFIG_RTW_80211R\n\t\t\tif (rtw_ft_roam(padapter))\n\t\t\t\tpsta = rtw_get_stainfo(pstapriv, pmlmepriv->assoc_bssid);\n\t\t\telse\n#endif\n\t\t\t\tpsta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));\n\t\t\tif (psta == NULL) {\n\t\t\t\t/* DEBUG_ERR( (\"Set wpa_set_encryption: Obtain Sta_info fail\\n\")); */\n\t\t\t\tRTW_INFO(\"%s, : Obtain Sta_info fail\\n\", __func__);\n\t\t\t} else {\n\t\t\t\t/* Jeff: don't disable ieee8021x_blocked while clearing key */\n\t\t\t\tif (strcmp(param->u.crypt.alg, \"none\") != 0)\n\t\t\t\t\tpsta->ieee8021x_blocked = _FALSE;\n\n\t\t\t\tif ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) ||\n\t\t\t\t    (padapter->securitypriv.ndisencryptstatus ==  Ndis802_11Encryption3Enabled))\n\t\t\t\t\tpsta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;\n\n\t\t\t\tif (param->u.crypt.set_tx == 1) { /* pairwise key */\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set %s PTK idx:%u, len:%u\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\t\t_rtw_memcpy(psta->dot118021x_UncstKey.skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\t\t\t\t\tif (strcmp(param->u.crypt.alg, \"TKIP\") == 0) { /* set mic key */\n\t\t\t\t\t\t_rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);\n\t\t\t\t\t\t_rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);\n\t\t\t\t\t\tpadapter->securitypriv.busetkipkey = _FALSE;\n\t\t\t\t\t}\n\t\t\t\t\tpsta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);\n\t\t\t\t\tpsta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq);\n\t\t\t\t\tpsta->bpairwise_key_installed = _TRUE;\n\t\t\t\t\t#ifdef CONFIG_RTW_80211R\n\t\t\t\t\tpsta->ft_pairwise_key_installed = _TRUE;\n\t\t\t\t\t#endif\n\t\t\t\t\trtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _TRUE);\n\n\t\t\t\t} else { /* group key */\n\t\t\t\t\tif (strcmp(param->u.crypt.alg, \"TKIP\") == 0 || strcmp(param->u.crypt.alg, \"CCMP\") == 0) {\n\t\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set %s GTK idx:%u, len:%u\\n\"\n\t\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\t\t\t_rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key,\n\t\t\t\t\t\t\t(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\t\t\t\t\t\t_rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);\n\t\t\t\t\t\t_rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);\n\t\t\t\t\t\tpadapter->securitypriv.binstallGrpkey = _TRUE;\n\t\t\t\t\t\tif (param->u.crypt.idx < 4) \n\t\t\t\t\t\t\t_rtw_memcpy(padapter->securitypriv.iv_seq[param->u.crypt.idx], param->u.crypt.seq, 8);\t\t\t\t\t\t\t\n\t\t\t\t\t\tpadapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx;\n\t\t\t\t\t\trtw_set_key(padapter, &padapter->securitypriv, param->u.crypt.idx, 1, _TRUE);\n\n\t\t\t\t\t#ifdef CONFIG_IEEE80211W\n\t\t\t\t\t} else if (strcmp(param->u.crypt.alg, \"BIP\") == 0) {\n\t\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set IGTK idx:%u, len:%u\\n\"\n\t\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\t\t\t_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey,  param->u.crypt.key,\n\t\t\t\t\t\t\t(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\t\t\t\t\t\tpsecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;\n\t\t\t\t\t\tpsecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq);\n\t\t\t\t\t\tpsecuritypriv->binstallBIPkey = _TRUE;\n\t\t\t\t\t#endif /* CONFIG_IEEE80211W */\n\n\t\t\t\t\t}\n\n#ifdef CONFIG_P2P\n\t\t\t\t\tif (pwdinfo->driver_interface == DRIVER_CFG80211) {\n\t\t\t\t\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))\n\t\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE);\n\t\t\t\t\t}\n#endif /* CONFIG_P2P */\n\n\t\t\t\t\t/* WPA/WPA2 key-handshake has completed */\n\t\t\t\t\tclr_fwstate(pmlmepriv, WIFI_UNDER_KEY_HANDSHAKE);\n\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tpbcmc_sta = rtw_get_bcmc_stainfo(padapter);\n\t\t\tif (pbcmc_sta == NULL) {\n\t\t\t\t/* DEBUG_ERR( (\"Set OID_802_11_ADD_KEY: bcmc stainfo is null\\n\")); */\n\t\t\t} else {\n\t\t\t\t/* Jeff: don't disable ieee8021x_blocked while clearing key */\n\t\t\t\tif (strcmp(param->u.crypt.alg, \"none\") != 0)\n\t\t\t\t\tpbcmc_sta->ieee8021x_blocked = _FALSE;\n\n\t\t\t\tif ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) ||\n\t\t\t\t    (padapter->securitypriv.ndisencryptstatus ==  Ndis802_11Encryption3Enabled))\n\t\t\t\t\tpbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;\n\t\t\t}\n\t\t} else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) { /* adhoc mode */\n\t\t}\n\t}\n\n\t#ifdef CONFIG_WAPI_SUPPORT\n\tif (strcmp(param->u.crypt.alg, \"SMS4\") == 0)\n\t\trtw_wapi_set_set_encryption(padapter, param);\n\t#endif\n\nexit:\n\n\tRTW_INFO(\"%s, ret=%d\\n\", __func__, ret);\n\n\n\treturn ret;\n}\n\nstatic int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0))\n        , int link_id\n#endif\n\t, u8 key_index\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\t, bool pairwise\n#endif\n\t, const u8 *mac_addr, struct key_params *params)\n{\n\tchar *alg_name;\n\tu32 param_len;\n\tstruct ieee_param *param = NULL;\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct wireless_dev *rtw_wdev = padapter->rtw_wdev;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n#ifdef CONFIG_TDLS\n\tstruct sta_info *ptdls_sta;\n#endif /* CONFIG_TDLS */\n\n\tif (mac_addr)\n\t\tRTW_INFO(FUNC_NDEV_FMT\" adding key for %pM\\n\", FUNC_NDEV_ARG(ndev), mac_addr);\n\tRTW_INFO(FUNC_NDEV_FMT\" cipher=0x%x\\n\", FUNC_NDEV_ARG(ndev), params->cipher);\n\tRTW_INFO(FUNC_NDEV_FMT\" key_len=%d, key_index=%d\\n\", FUNC_NDEV_ARG(ndev), params->key_len, key_index);\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\tRTW_INFO(FUNC_NDEV_FMT\" pairwise=%d\\n\", FUNC_NDEV_ARG(ndev), pairwise);\n#endif\n\n\tif (rtw_cfg80211_sync_iftype(padapter) != _SUCCESS) {\n\t\tret = -ENOTSUPP;\n\t\tgoto addkey_end;\n\t}\n\n\tparam_len = sizeof(struct ieee_param) + params->key_len;\n\tparam = rtw_malloc(param_len);\n\tif (param == NULL)\n\t\treturn -1;\n\n\t_rtw_memset(param, 0, param_len);\n\n\tparam->cmd = IEEE_CMD_SET_ENCRYPTION;\n\t_rtw_memset(param->sta_addr, 0xff, ETH_ALEN);\n\n\tswitch (params->cipher) {\n\tcase IW_AUTH_CIPHER_NONE:\n\t\t/* todo: remove key */\n\t\t/* remove = 1;\t */\n\t\talg_name = \"none\";\n\t\tbreak;\n\tcase WLAN_CIPHER_SUITE_WEP40:\n\tcase WLAN_CIPHER_SUITE_WEP104:\n\t\talg_name = \"WEP\";\n\t\tbreak;\n\tcase WLAN_CIPHER_SUITE_TKIP:\n\t\talg_name = \"TKIP\";\n\t\tbreak;\n\tcase WLAN_CIPHER_SUITE_CCMP:\n\t\talg_name = \"CCMP\";\n\t\tbreak;\n#ifdef CONFIG_IEEE80211W\n\tcase WLAN_CIPHER_SUITE_AES_CMAC:\n\t\talg_name = \"BIP\";\n\t\tbreak;\n#endif /* CONFIG_IEEE80211W */\n#ifdef CONFIG_WAPI_SUPPORT\n\tcase WLAN_CIPHER_SUITE_SMS4:\n\t\talg_name = \"SMS4\";\n\t\tif (pairwise == NL80211_KEYTYPE_PAIRWISE) {\n\t\t\tif (key_index != 0 && key_index != 1) {\n\t\t\t\tret = -ENOTSUPP;\n\t\t\t\tgoto addkey_end;\n\t\t\t}\n\t\t\t_rtw_memcpy((void *)param->sta_addr, (void *)mac_addr, ETH_ALEN);\n\t\t} else\n\t\t\tRTW_INFO(\"mac_addr is null\\n\");\n\t\tRTW_INFO(\"rtw_wx_set_enc_ext: SMS4 case\\n\");\n\t\tbreak;\n#endif\n\n\tdefault:\n\t\tret = -ENOTSUPP;\n\t\tgoto addkey_end;\n\t}\n\n\tstrncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN);\n\n\n\tif (!mac_addr || is_broadcast_ether_addr(mac_addr)\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\t\t|| !pairwise\n\t\t#endif\n\t) {\n\t\tparam->u.crypt.set_tx = 0; /* for wpa/wpa2 group key */\n\t} else {\n\t\tparam->u.crypt.set_tx = 1; /* for wpa/wpa2 pairwise key */\n\t}\n\n\tparam->u.crypt.idx = key_index;\n\n\tif (params->seq_len && params->seq) {\n\t\t_rtw_memcpy(param->u.crypt.seq, (u8 *)params->seq, params->seq_len);\n\t\tRTW_INFO(FUNC_NDEV_FMT\" seq_len:%u, seq:0x%llx\\n\", FUNC_NDEV_ARG(ndev)\n\t\t\t, params->seq_len, RTW_GET_LE64(param->u.crypt.seq));\n\t}\n\n\tif (params->key_len && params->key) {\n\t\tparam->u.crypt.key_len = params->key_len;\n\t\t_rtw_memcpy(param->u.crypt.key, (u8 *)params->key, params->key_len);\n\t}\n\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {\n#ifdef CONFIG_TDLS\n\t\tif (rtw_tdls_is_driver_setup(padapter) == _FALSE && mac_addr) {\n\t\t\tptdls_sta = rtw_get_stainfo(&padapter->stapriv, (void *)mac_addr);\n\t\t\tif (ptdls_sta != NULL && ptdls_sta->tdls_sta_state) {\n\t\t\t\t_rtw_memcpy(ptdls_sta->tpk.tk, params->key, params->key_len);\n\t\t\t\trtw_tdls_set_key(padapter, ptdls_sta);\n\t\t\t\tgoto addkey_end;\n\t\t\t}\n\t\t}\n#endif /* CONFIG_TDLS */\n\t\tret = rtw_cfg80211_set_encryption(ndev, param);\n\t} else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {\n#ifdef CONFIG_AP_MODE\n\t\tif (mac_addr)\n\t\t\t_rtw_memcpy(param->sta_addr, (void *)mac_addr, ETH_ALEN);\n\n\t\tret = rtw_cfg80211_ap_set_encryption(ndev, param);\n#endif\n\t} else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE\n\t\t|| check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE\n\t) {\n\t\t/* RTW_INFO(\"@@@@@@@@@@ fw_state=0x%x, iftype=%d\\n\", pmlmepriv->fw_state, rtw_wdev->iftype); */\n\t\tret = rtw_cfg80211_set_encryption(ndev, param);\n\t} else\n\t\tRTW_INFO(\"error! fw_state=0x%x, iftype=%d\\n\", pmlmepriv->fw_state, rtw_wdev->iftype);\n\n\naddkey_end:\n\tif (param)\n\t\trtw_mfree(param, param_len);\n\n\treturn ret;\n\n}\n\nstatic int cfg80211_rtw_get_key(struct wiphy *wiphy, struct net_device *ndev\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0))\n        , int link_id\n#endif\n\t, u8 keyid\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\t, bool pairwise\n#endif\n\t, const u8 *mac_addr, void *cookie\n\t, void (*callback)(void *cookie, struct key_params *))\n{\n#define GET_KEY_PARAM_FMT_S \" keyid=%d\"\n#define GET_KEY_PARAM_ARG_S , keyid\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\t#define GET_KEY_PARAM_FMT_2_6_37 \", pairwise=%d\"\n\t#define GET_KEY_PARAM_ARG_2_6_37 , pairwise\n#else\n\t#define GET_KEY_PARAM_FMT_2_6_37 \"\"\n\t#define GET_KEY_PARAM_ARG_2_6_37\n#endif\n#define GET_KEY_PARAM_FMT_E \", addr=%pM\"\n#define GET_KEY_PARAM_ARG_E , mac_addr\n\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct security_priv *sec = &adapter->securitypriv;\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct sta_info *sta = NULL;\n\tu32 cipher = _NO_PRIVACY_;\n\tunion Keytype *key = NULL;\n\tu8 key_len = 0;\n\tu64 *pn = NULL;\n\tu8 pn_len = 0;\n\tu8 pn_val[8] = {0};\n\n\tstruct key_params params;\n\tint ret = -ENOENT;\n\n\tif (keyid >= WEP_KEYS\n\t\t#ifdef CONFIG_IEEE80211W\n\t\t&& keyid > BIP_MAX_KEYID\n\t\t#endif\n\t)\n\t\tgoto exit;\n\n\tif (!mac_addr || is_broadcast_ether_addr(mac_addr)\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\t\t|| (MLME_IS_STA(adapter) && !pairwise)\n\t\t#endif\n\t) {\t\n\t\t/* WEP key, TX GTK/IGTK, RX GTK/IGTK(for STA mode) */\n\t\tif (is_wep_enc(sec->dot118021XGrpPrivacy)) {\n\t\t\tif (keyid >= WEP_KEYS)\n\t\t\t\tgoto exit;\n\t\t\tif (!(sec->key_mask & BIT(keyid)))\n\t\t\t\tgoto exit;\n\t\t\tcipher = sec->dot118021XGrpPrivacy;\n\t\t\tkey = &sec->dot11DefKey[keyid];\n\t\t} else {\n\t\t\tif (keyid < WEP_KEYS) {\n\t\t\t\tif (sec->binstallGrpkey != _TRUE)\n\t\t\t\t\tgoto exit;\n\t\t\t\tcipher = sec->dot118021XGrpPrivacy;\n\t\t\t\tkey = &sec->dot118021XGrpKey[keyid];\n\t\t\t\tsta = rtw_get_bcmc_stainfo(adapter);\n\t\t\t\tif (sta)\n\t\t\t\t\tpn = &sta->dot11txpn.val;\n\t\t\t#ifdef CONFIG_IEEE80211W\n\t\t\t} else if (keyid <= BIP_MAX_KEYID) {\n\t\t\t\tif (SEC_IS_BIP_KEY_INSTALLED(sec) != _TRUE)\n\t\t\t\t\tgoto exit;\n\t\t\t\tcipher = _BIP_;\n\t\t\t\tkey = &sec->dot11wBIPKey[keyid];\n\t\t\t\tpn = &sec->dot11wBIPtxpn.val;\n\t\t\t#endif\n\t\t\t}\n\t\t}\n\t} else {\n\t\t/* Pairwise key, RX GTK/IGTK for specific peer */\n\t\tsta = rtw_get_stainfo(stapriv, mac_addr);\n\t\tif (!sta)\n\t\t\tgoto exit;\n\n\t\tif (keyid < WEP_KEYS && pairwise) {\n\t\t\tif (sta->bpairwise_key_installed != _TRUE)\n\t\t\t\tgoto exit;\n\t\t\tcipher = sta->dot118021XPrivacy;\n\t\t\tkey = &sta->dot118021x_UncstKey;\n\t\t#ifdef CONFIG_RTW_MESH\n\t\t} else if (keyid < WEP_KEYS && !pairwise) {\n\t\t\tif (!(sta->gtk_bmp & BIT(keyid)))\n\t\t\t\tgoto exit;\n\t\t\tcipher = sta->group_privacy;\n\t\t\tkey = &sta->gtk;\n\t\t#ifdef CONFIG_IEEE80211W\n\t\t} else if (keyid <= BIP_MAX_KEYID && !pairwise) {\n\t\t\tif (!(sta->igtk_bmp & BIT(keyid)))\n\t\t\t\tgoto exit;\n\t\t\tcipher = _BIP_;\n\t\t\tkey = &sta->igtk;\n\t\t\tpn = &sta->igtk_pn.val;\n\t\t#endif\n\t\t#endif /* CONFIG_RTW_MESH */\n\t\t}\n\t}\n\n\tif (!key)\n\t\tgoto exit;\n\n\tif (cipher == _WEP40_) {\n\t\tcipher = WLAN_CIPHER_SUITE_WEP40;\n\t\tkey_len = sec->dot11DefKeylen[keyid];\n\t} else if (cipher == _WEP104_) {\n\t\tcipher = WLAN_CIPHER_SUITE_WEP104;\n\t\tkey_len = sec->dot11DefKeylen[keyid];\n\t} else if (cipher == _TKIP_) {\n\t\tcipher = WLAN_CIPHER_SUITE_TKIP;\n\t\tkey_len = 16;\n\t} else if (cipher == _AES_) {\n\t\tcipher = WLAN_CIPHER_SUITE_CCMP;\n\t\tkey_len = 16;\n\t#ifdef CONFIG_IEEE80211W\n\t} else if (cipher == _BIP_) {\n\t\tcipher = WLAN_CIPHER_SUITE_AES_CMAC;\n\t\tkey_len = 16;\n\t#endif\n\t} else {\n\t\tRTW_WARN(FUNC_NDEV_FMT\" unknown cipher:%u\\n\", FUNC_NDEV_ARG(ndev), cipher);\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (pn) {\n\t\t*((u64 *)pn_val) = cpu_to_le64(*pn);\n\t\tpn_len = 6;\n\t}\n\n\tret = 0;\n\t\nexit:\n\tRTW_INFO(FUNC_NDEV_FMT\n\t\tGET_KEY_PARAM_FMT_S\n\t\tGET_KEY_PARAM_FMT_2_6_37\n\t\tGET_KEY_PARAM_FMT_E\n\t\t\" ret %d\\n\", FUNC_NDEV_ARG(ndev)\n\t\tGET_KEY_PARAM_ARG_S\n\t\tGET_KEY_PARAM_ARG_2_6_37\n\t\tGET_KEY_PARAM_ARG_E\n\t\t, ret);\n\tif (pn)\n\t\tRTW_INFO(FUNC_NDEV_FMT \" seq:0x%llx\\n\", FUNC_NDEV_ARG(ndev), *pn);\n\n\tif (ret == 0) {\n\t\t_rtw_memset(&params, 0, sizeof(params));\n\n\t\tparams.cipher = cipher;\n\t\tparams.key = key->skey;\n\t\tparams.key_len = key_len;\n\t\tif (pn) {\n\t\t\tparams.seq = pn_val;\n\t\t\tparams.seq_len = pn_len;\n\t\t}\n\n\t\tcallback(cookie, &params);\n\t}\n\n\treturn ret;\n}\n\nstatic int cfg80211_rtw_del_key(struct wiphy *wiphy, struct net_device *ndev,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0))\n        int link_id,\n#endif\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\t\t\t\tu8 key_index, bool pairwise, const u8 *mac_addr)\n#else\t/* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */\n\t\t\t\tu8 key_index, const u8 *mac_addr)\n#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\n\tRTW_INFO(FUNC_NDEV_FMT\" key_index=%d, addr=%pM\\n\", FUNC_NDEV_ARG(ndev), key_index, mac_addr);\n\n\tif (key_index == psecuritypriv->dot11PrivacyKeyIndex) {\n\t\t/* clear the flag of wep default key set. */\n\t\tpsecuritypriv->bWepDefaultKeyIdxSet = 0;\n\t}\n\n\treturn 0;\n}\n\nstatic int cfg80211_rtw_set_default_key(struct wiphy *wiphy,\n\tstruct net_device *ndev,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0))\n        int link_id,\n#endif\n\tu8 key_index\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)\n\t, bool unicast, bool multicast\n\t#endif\n)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\n#define SET_DEF_KEY_PARAM_FMT \" key_index=%d\"\n#define SET_DEF_KEY_PARAM_ARG , key_index\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)\n\t#define SET_DEF_KEY_PARAM_FMT_2_6_38 \", unicast=%d, multicast=%d\"\n\t#define SET_DEF_KEY_PARAM_ARG_2_6_38 , unicast, multicast\n#else\n\t#define SET_DEF_KEY_PARAM_FMT_2_6_38 \"\"\n\t#define SET_DEF_KEY_PARAM_ARG_2_6_38\n#endif\n\n\tRTW_INFO(FUNC_NDEV_FMT\n\t\tSET_DEF_KEY_PARAM_FMT\n\t\tSET_DEF_KEY_PARAM_FMT_2_6_38\n\t\t\"\\n\", FUNC_NDEV_ARG(ndev)\n\t\tSET_DEF_KEY_PARAM_ARG\n\t\tSET_DEF_KEY_PARAM_ARG_2_6_38\n\t);\n\n\tif ((key_index < WEP_KEYS) && ((psecuritypriv->dot11PrivacyAlgrthm == _WEP40_) || (psecuritypriv->dot11PrivacyAlgrthm == _WEP104_))) { /* set wep default key */\n\t\tpsecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;\n\n\t\tpsecuritypriv->dot11PrivacyKeyIndex = key_index;\n\n\t\tpsecuritypriv->dot11PrivacyAlgrthm = _WEP40_;\n\t\tpsecuritypriv->dot118021XGrpPrivacy = _WEP40_;\n\t\tif (psecuritypriv->dot11DefKeylen[key_index] == 13) {\n\t\t\tpsecuritypriv->dot11PrivacyAlgrthm = _WEP104_;\n\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _WEP104_;\n\t\t}\n\n\t\tpsecuritypriv->bWepDefaultKeyIdxSet = 1; /* set the flag to represent that wep default key has been set */\n\t}\n\n\treturn 0;\n\n}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30))\nint cfg80211_rtw_set_default_mgmt_key(struct wiphy *wiphy,\n\tstruct net_device *ndev,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0))\n        int link_id,\n#endif\n\t\tu8 key_index)\n{\n#define SET_DEF_KEY_PARAM_FMT \" key_index=%d\"\n#define SET_DEF_KEY_PARAM_ARG , key_index\n\n\tRTW_INFO(FUNC_NDEV_FMT\n\t\tSET_DEF_KEY_PARAM_FMT\n\t\t\"\\n\", FUNC_NDEV_ARG(ndev)\n\t\tSET_DEF_KEY_PARAM_ARG\n\t);\n\n\treturn 0;\n}\n#endif\n\n#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))\nstatic int cfg80211_rtw_set_rekey_data(struct wiphy *wiphy,\n\tstruct net_device *ndev,\n\tstruct cfg80211_gtk_rekey_data *data)\n{\n\t/*int i;*/\n\tstruct sta_info *psta;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct mlme_priv   *pmlmepriv = &padapter->mlmepriv;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct security_priv *psecuritypriv = &(padapter->securitypriv);\n\n\tpsta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));\n\tif (psta == NULL) {\n\t\tRTW_INFO(\"%s, : Obtain Sta_info fail\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\t_rtw_memcpy(psta->kek, data->kek, NL80211_KEK_LEN);\n\t/*printk(\"\\ncfg80211_rtw_set_rekey_data KEK:\");\n\tfor(i=0;i<NL80211_KEK_LEN; i++)\n\t\tprintk(\" %02x \", psta->kek[i]);*/\n\t_rtw_memcpy(psta->kck, data->kck, NL80211_KCK_LEN);\n\t/*printk(\"\\ncfg80211_rtw_set_rekey_data KCK:\");\n\tfor(i=0;i<NL80211_KCK_LEN; i++)\n\t\tprintk(\" %02x \", psta->kck[i]);*/\n\t_rtw_memcpy(psta->replay_ctr, data->replay_ctr, NL80211_REPLAY_CTR_LEN);\n\tpsecuritypriv->binstallKCK_KEK = _TRUE;\n\t/*printk(\"\\nREPLAY_CTR: \");\n\tfor(i=0;i<RTW_REPLAY_CTR_LEN; i++)\n\t\tprintk(\" %02x \", psta->replay_ctr[i]);*/\n\n\treturn 0;\n}\n#endif /*CONFIG_GTK_OL*/\n\n#ifdef CONFIG_RTW_MESH\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))\nstatic enum nl80211_mesh_power_mode rtw_mesh_ps_to_nl80211_mesh_power_mode(u8 ps)\n{\n\tif (ps == RTW_MESH_PS_UNKNOWN)\n\t\treturn NL80211_MESH_POWER_UNKNOWN;\n\tif (ps == RTW_MESH_PS_ACTIVE)\n\t\treturn NL80211_MESH_POWER_ACTIVE;\n\tif (ps == RTW_MESH_PS_LSLEEP)\n\t\treturn NL80211_MESH_POWER_LIGHT_SLEEP;\n\tif (ps == RTW_MESH_PS_DSLEEP)\n\t\treturn NL80211_MESH_POWER_DEEP_SLEEP;\n\n\trtw_warn_on(1);\n\treturn NL80211_MESH_POWER_UNKNOWN;\n}\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))\nenum nl80211_plink_state rtw_plink_state_to_nl80211_plink_state(u8 plink_state)\n{\n\tif (plink_state == RTW_MESH_PLINK_UNKNOWN)\n\t\treturn NUM_NL80211_PLINK_STATES;\n\tif (plink_state == RTW_MESH_PLINK_LISTEN)\n\t\treturn NL80211_PLINK_LISTEN;\n\tif (plink_state == RTW_MESH_PLINK_OPN_SNT)\n\t\treturn NL80211_PLINK_OPN_SNT;\n\tif (plink_state == RTW_MESH_PLINK_OPN_RCVD)\n\t\treturn NL80211_PLINK_OPN_RCVD;\n\tif (plink_state == RTW_MESH_PLINK_CNF_RCVD)\n\t\treturn NL80211_PLINK_CNF_RCVD;\n\tif (plink_state == RTW_MESH_PLINK_ESTAB)\n\t\treturn NL80211_PLINK_ESTAB;\n\tif (plink_state == RTW_MESH_PLINK_HOLDING)\n\t\treturn NL80211_PLINK_HOLDING;\n\tif (plink_state == RTW_MESH_PLINK_BLOCKED)\n\t\treturn NL80211_PLINK_BLOCKED;\n\n\trtw_warn_on(1);\n\treturn NUM_NL80211_PLINK_STATES;\n}\n\nu8 nl80211_plink_state_to_rtw_plink_state(enum nl80211_plink_state plink_state)\n{\n\tif (plink_state == NL80211_PLINK_LISTEN)\n\t\treturn RTW_MESH_PLINK_LISTEN;\n\tif (plink_state == NL80211_PLINK_OPN_SNT)\n\t\treturn RTW_MESH_PLINK_OPN_SNT;\n\tif (plink_state == NL80211_PLINK_OPN_RCVD)\n\t\treturn RTW_MESH_PLINK_OPN_RCVD;\n\tif (plink_state == NL80211_PLINK_CNF_RCVD)\n\t\treturn RTW_MESH_PLINK_CNF_RCVD;\n\tif (plink_state == NL80211_PLINK_ESTAB)\n\t\treturn RTW_MESH_PLINK_ESTAB;\n\tif (plink_state == NL80211_PLINK_HOLDING)\n\t\treturn RTW_MESH_PLINK_HOLDING;\n\tif (plink_state == NL80211_PLINK_BLOCKED)\n\t\treturn RTW_MESH_PLINK_BLOCKED;\n\n\trtw_warn_on(1);\n\treturn RTW_MESH_PLINK_UNKNOWN;\n}\n#endif\n\nstatic void rtw_cfg80211_fill_mesh_only_sta_info(struct mesh_plink_ent *plink, struct sta_info *sta, struct station_info *sinfo)\n{\n\tsinfo->filled |= STATION_INFO_LLID;\n\tsinfo->llid = plink->llid;\n\tsinfo->filled |= STATION_INFO_PLID;\n\tsinfo->plid = plink->plid;\n\tsinfo->filled |= STATION_INFO_PLINK_STATE;\n\tsinfo->plink_state = rtw_plink_state_to_nl80211_plink_state(plink->plink_state);\n\tif (!sta && plink->scanned) {\n\t\tsinfo->filled |= STATION_INFO_SIGNAL;\n\t\tsinfo->signal = translate_percentage_to_dbm(plink->scanned->network.PhyInfo.SignalStrength);\n\t\tsinfo->filled |= STATION_INFO_INACTIVE_TIME;\n\t\tif (plink->plink_state == RTW_MESH_PLINK_UNKNOWN)\n\t\t\tsinfo->inactive_time = 0 - 1;\n\t\telse\n\t\t\tsinfo->inactive_time = rtw_get_passing_time_ms(plink->scanned->last_scanned);\n\t}\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))\n\tif (sta) {\n\t\tsinfo->filled |= STATION_INFO_LOCAL_PM;\n\t\tsinfo->local_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->local_mps);\n\t\tsinfo->filled |= STATION_INFO_PEER_PM;\n\t\tsinfo->peer_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->peer_mps);\n\t\tsinfo->filled |= STATION_INFO_NONPEER_PM;\n\t\tsinfo->nonpeer_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->nonpeer_mps);\n\t}\n#endif\n}\n#endif /* CONFIG_RTW_MESH */\n\nstatic int cfg80211_rtw_get_station(struct wiphy *wiphy,\n\tstruct net_device *ndev,\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))\n\tu8 *mac,\n#else\n\tconst u8 *mac,\n#endif\n\tstruct station_info *sinfo)\n{\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct sta_info *psta = NULL;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n#ifdef CONFIG_RTW_MESH\n\tstruct mesh_plink_ent *plink = NULL;\n#endif\n\n\tsinfo->filled = 0;\n\n\tif (!mac) {\n\t\tRTW_INFO(FUNC_NDEV_FMT\" mac==%p\\n\", FUNC_NDEV_ARG(ndev), mac);\n\t\tret = -ENOENT;\n\t\tgoto exit;\n\t}\n\n\tpsta = rtw_get_stainfo(pstapriv, mac);\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(padapter)) {\n\t\tif (psta)\n\t\t\tplink = psta->plink;\n\t\tif (!plink)\n\t\t\tplink = rtw_mesh_plink_get(padapter, mac);\n\t}\n#endif /* CONFIG_RTW_MESH */\n\n\tif ((!MLME_IS_MESH(padapter) && !psta)\n\t\t#ifdef CONFIG_RTW_MESH\n\t\t|| (MLME_IS_MESH(padapter) && !plink)\n\t\t#endif\n\t) {\n\t\tRTW_INFO(FUNC_NDEV_FMT\" no sta info for mac=\"MAC_FMT\"\\n\"\n\t\t\t, FUNC_NDEV_ARG(ndev), MAC_ARG(mac));\n\t\tret = -ENOENT;\n\t\tgoto exit;\n\t}\n\n#ifdef CONFIG_DEBUG_CFG80211\n\tRTW_INFO(FUNC_NDEV_FMT\" mac=\"MAC_FMT\"\\n\", FUNC_NDEV_ARG(ndev), MAC_ARG(mac));\n#endif\n\n\t/* for infra./P2PClient mode */\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE)\n\t\t&& check_fwstate(pmlmepriv, _FW_LINKED)\n\t) {\n\t\tstruct wlan_network  *cur_network = &(pmlmepriv->cur_network);\n\n\t\tif (_rtw_memcmp((u8 *)mac, cur_network->network.MacAddress, ETH_ALEN) == _FALSE) {\n\t\t\tRTW_INFO(\"%s, mismatch bssid=\"MAC_FMT\"\\n\", __func__, MAC_ARG(cur_network->network.MacAddress));\n\t\t\tret = -ENOENT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tsinfo->filled |= STATION_INFO_SIGNAL;\n\t\tsinfo->signal = translate_percentage_to_dbm(padapter->recvpriv.signal_strength);\n\n\t\tsinfo->filled |= STATION_INFO_TX_BITRATE;\n\t\tsinfo->txrate.legacy = rtw_get_cur_max_rate(padapter);\n\t}\n\n\tif (psta) {\n\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE\n\t\t\t|| check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE\n\t\t) {\n\t\t\tsinfo->filled |= STATION_INFO_SIGNAL;\n\t\t\tsinfo->signal = translate_percentage_to_dbm(psta->cmn.rssi_stat.rssi);\n\t\t}\n\t\tsinfo->filled |= STATION_INFO_INACTIVE_TIME;\n\t\tsinfo->inactive_time = rtw_get_passing_time_ms(psta->sta_stats.last_rx_time);\n\t\tsinfo->filled |= STATION_INFO_RX_PACKETS;\n\t\tsinfo->rx_packets = sta_rx_data_pkts(psta);\n\t\tsinfo->filled |= STATION_INFO_TX_PACKETS;\n\t\tsinfo->tx_packets = psta->sta_stats.tx_pkts;\n\t\tsinfo->filled |= STATION_INFO_TX_FAILED;\n\t\tsinfo->tx_failed = psta->sta_stats.tx_fail_cnt;\n\t}\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(padapter))\n\t\trtw_cfg80211_fill_mesh_only_sta_info(plink, psta, sinfo);\n#endif\n\nexit:\n\treturn ret;\n}\n\nextern int netdev_open(struct net_device *pnetdev);\n\n#if 0\nenum nl80211_iftype {\n\tNL80211_IFTYPE_UNSPECIFIED,\n\tNL80211_IFTYPE_ADHOC, /* 1 */\n\tNL80211_IFTYPE_STATION, /* 2 */\n\tNL80211_IFTYPE_AP, /* 3 */\n\tNL80211_IFTYPE_AP_VLAN,\n\tNL80211_IFTYPE_WDS,\n\tNL80211_IFTYPE_MONITOR, /* 6 */\n\tNL80211_IFTYPE_MESH_POINT,\n\tNL80211_IFTYPE_P2P_CLIENT, /* 8 */\n\tNL80211_IFTYPE_P2P_GO, /* 9 */\n\t/* keep last */\n\tNUM_NL80211_IFTYPES,\n\tNL80211_IFTYPE_MAX = NUM_NL80211_IFTYPES - 1\n};\n#endif\nstatic int cfg80211_rtw_change_iface(struct wiphy *wiphy,\n\t\t\t\t     struct net_device *ndev,\n\t\t\t\t     enum nl80211_iftype type,\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))\n\t\t\t\t     u32 *flags,\n#endif\n\t\t\t\t     struct vif_params *params)\n{\n\tenum nl80211_iftype old_type;\n\tNDIS_802_11_NETWORK_INFRASTRUCTURE networkType;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct wireless_dev *rtw_wdev = padapter->rtw_wdev;\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n\tu8 is_p2p = _FALSE;\n#endif\n#ifdef CONFIG_MONITOR_MODE_XMIT\n\tstruct mlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n#endif\n\tint ret = 0;\n\tu8 change = _FALSE;\n\n\tRTW_INFO(FUNC_NDEV_FMT\" type=%d, hw_port:%d\\n\", FUNC_NDEV_ARG(ndev), type, padapter->hw_port);\n\n\tif (adapter_to_dvobj(padapter)->processing_dev_remove == _TRUE) {\n\t\tret = -EPERM;\n\t\tgoto exit;\n\t}\n\n\n\tRTW_INFO(FUNC_NDEV_FMT\" call netdev_open\\n\", FUNC_NDEV_ARG(ndev));\n\tif (netdev_open(ndev) != 0) {\n\t\tRTW_INFO(FUNC_NDEV_FMT\" call netdev_open fail\\n\", FUNC_NDEV_ARG(ndev));\n\t\tret = -EPERM;\n\t\tgoto exit;\n\t}\n\n\n\tif (_FAIL == rtw_pwr_wakeup(padapter)) {\n\t\tRTW_INFO(FUNC_NDEV_FMT\" call rtw_pwr_wakeup fail\\n\", FUNC_NDEV_ARG(ndev));\n\t\tret = -EPERM;\n\t\tgoto exit;\n\t}\n\n\told_type = rtw_wdev->iftype;\n\tRTW_INFO(FUNC_NDEV_FMT\" old_iftype=%d, new_iftype=%d\\n\",\n\t\tFUNC_NDEV_ARG(ndev), old_type, type);\n\n\tif (old_type != type) {\n\t\tchange = _TRUE;\n\t\tpmlmeext->action_public_rxseq = 0xffff;\n\t\tpmlmeext->action_public_dialog_token = 0xff;\n\t}\n\n\t/* initial default type */\n\tndev->type = ARPHRD_ETHER;\n\n\t/*\n\t * Disable Power Save in moniter mode,\n\t * and enable it after leaving moniter mode.\n\t */\n\tif (type == NL80211_IFTYPE_MONITOR) {\n\t\trtw_ps_deny(padapter, PS_DENY_MONITOR_MODE);\n\t\tLeaveAllPowerSaveMode(padapter);\n\t} else if (old_type == NL80211_IFTYPE_MONITOR) {\n\t\t/* driver in moniter mode in last time */\n\t\trtw_ps_deny_cancel(padapter, PS_DENY_MONITOR_MODE);\n\t}\n\n\tswitch (type) {\n\tcase NL80211_IFTYPE_ADHOC:\n\t\tnetworkType = Ndis802_11IBSS;\n\t\tbreak;\n\n\t#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))\n\tcase NL80211_IFTYPE_P2P_CLIENT:\n\t\tis_p2p = _TRUE;\n\t#endif\n\tcase NL80211_IFTYPE_STATION:\n\t\tnetworkType = Ndis802_11Infrastructure;\n\n\t\t#ifdef CONFIG_P2P\n\t\tif (change && pwdinfo->driver_interface == DRIVER_CFG80211) {\n\t\t\tif (is_p2p == _TRUE)\n\t\t\t\trtw_p2p_enable(padapter, P2P_ROLE_CLIENT);\n\t\t\t#if !RTW_P2P_GROUP_INTERFACE\n\t\t\telse if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)\n\t\t\t\t\t|| rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)\n\t\t\t) {\n\t\t\t\t/* it means remove GC/GO and change mode from GC/GO to station(P2P DEVICE) */\n\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);\n\t\t\t}\n\t\t\t#endif\n\t\t}\n\t\t#endif /* CONFIG_P2P */\n\n\t\tbreak;\n\n\t#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))\n\tcase NL80211_IFTYPE_P2P_GO:\n\t\tis_p2p = _TRUE;\n\t#endif\n\tcase NL80211_IFTYPE_AP:\n\t\tnetworkType = Ndis802_11APMode;\n\n\t\t#ifdef CONFIG_P2P\n\t\tif (change && pwdinfo->driver_interface == DRIVER_CFG80211) {\n\t\t\tif (is_p2p == _TRUE)\n\t\t\t\trtw_p2p_enable(padapter, P2P_ROLE_GO);\n\t\t\t#if !RTW_P2P_GROUP_INTERFACE\n\t\t\telse if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {\n\t\t\t\t/* it means P2P Group created, we will be GO and change mode from  P2P DEVICE to AP(GO) */\n\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);\n\t\t\t}\n\t\t\t#endif\n\t\t}\n\t\t#endif /* CONFIG_P2P */\n\n\t\tbreak;\n\n#ifdef CONFIG_RTW_MESH\n\tcase NL80211_IFTYPE_MESH_POINT:\n\t\tnetworkType = Ndis802_11_mesh;\n\t\tbreak;\n#endif\n\n\tcase NL80211_IFTYPE_MONITOR:\n\t\tnetworkType = Ndis802_11Monitor;\n#if 0\n\t\tndev->type = ARPHRD_IEEE80211; /* IEEE 802.11 : 801 */\n#endif\n\t\tndev->type = ARPHRD_IEEE80211_RADIOTAP; /* IEEE 802.11 + radiotap header : 803 */\n\t\tbreak;\n\tdefault:\n\t\tret = -EOPNOTSUPP;\n\t\tgoto exit;\n\t}\n\n\trtw_wdev->iftype = type;\n\n\tif (rtw_set_802_11_infrastructure_mode(padapter, networkType) == _FALSE) {\n\t\trtw_wdev->iftype = old_type;\n\t\tret = -EPERM;\n\t\tgoto exit;\n\t}\n\n\trtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK);\n#ifdef CONFIG_MONITOR_MODE_XMIT\n\tif (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE)\n\t\trtw_indicate_connect(padapter);\n#endif\nexit:\n\n\tRTW_INFO(FUNC_NDEV_FMT\" ret:%d\\n\", FUNC_NDEV_ARG(ndev), ret);\n\treturn ret;\n}\n\nvoid rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted)\n{\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);\n\t_irqL\tirqL;\n\n#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE)\n\tstruct cfg80211_scan_info info;\n\n\tmemset(&info, 0, sizeof(info));\n\tinfo.aborted = aborted;\n#endif\n\n\t_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);\n\tif (pwdev_priv->scan_request != NULL) {\n\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\tRTW_INFO(\"%s with scan req\\n\", __FUNCTION__);\n\t\t#endif\n\n\t\t/* avoid WARN_ON(request != wiphy_to_dev(request->wiphy)->scan_req); */\n\t\tif (pwdev_priv->scan_request->wiphy != pwdev_priv->rtw_wdev->wiphy)\n\t\t\tRTW_INFO(\"error wiphy compare\\n\");\n\t\telse\n#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE)\n\t\t\tcfg80211_scan_done(pwdev_priv->scan_request, &info);\n#else\n\t\t\tcfg80211_scan_done(pwdev_priv->scan_request, aborted);\n#endif\n\n\t\tpwdev_priv->scan_request = NULL;\n\t} else {\n\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\tRTW_INFO(\"%s without scan req\\n\", __FUNCTION__);\n\t\t#endif\n\t}\n\t_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);\n}\n\nu32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms)\n{\n\tstruct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter);\n\tu8 empty = _FALSE;\n\tsystime start;\n\tu32 pass_ms;\n\n\tstart = rtw_get_current_time();\n\n\twhile (rtw_get_passing_time_ms(start) <= timeout_ms) {\n\n\t\tif (RTW_CANNOT_RUN(adapter))\n\t\t\tbreak;\n\n\t\tif (!wdev_priv->scan_request) {\n\t\t\tempty = _TRUE;\n\t\t\tbreak;\n\t\t}\n\n\t\trtw_msleep_os(10);\n\t}\n\n\tpass_ms = rtw_get_passing_time_ms(start);\n\n\tif (empty == _FALSE && pass_ms > timeout_ms)\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" pass_ms:%u, timeout\\n\"\n\t\t\t, FUNC_ADPT_ARG(adapter), pass_ms);\n\n\treturn pass_ms;\n}\n\nvoid rtw_cfg80211_unlink_bss(_adapter *padapter, struct wlan_network *pnetwork)\n{\n\tstruct wireless_dev *pwdev = padapter->rtw_wdev;\n\tstruct wiphy *wiphy = pwdev->wiphy;\n\tstruct cfg80211_bss *bss = NULL;\n\tWLAN_BSSID_EX select_network = pnetwork->network;\n\n\tbss = cfg80211_get_bss(wiphy, NULL/*notify_channel*/,\n\t\tselect_network.MacAddress, select_network.Ssid.Ssid,\n\t\tselect_network.Ssid.SsidLength,\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)\n\t\tselect_network.InfrastructureMode == Ndis802_11Infrastructure?IEEE80211_BSS_TYPE_ESS:IEEE80211_BSS_TYPE_IBSS,\n\t\tIEEE80211_PRIVACY(select_network.Privacy));\n#else\n\t\tselect_network.InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS,\n\t\tselect_network.InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS);\n#endif\n\n\tif (bss) {\n\t\tcfg80211_unlink_bss(wiphy, bss);\n\t\tRTW_INFO(\"%s(): cfg80211_unlink %s!!\\n\", __func__, select_network.Ssid.Ssid);\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)\n\t\tcfg80211_put_bss(padapter->rtw_wdev->wiphy, bss);\n#else\n\t\tcfg80211_put_bss(bss);\n#endif\n\t}\n\treturn;\n}\n\n/* if target wps scan ongoing, target_ssid is filled */\nint rtw_cfg80211_is_target_wps_scan(struct cfg80211_scan_request *scan_req, struct cfg80211_ssid *target_ssid)\n{\n\tint ret = 0;\n\n\tif (scan_req->n_ssids != 1\n\t\t|| scan_req->ssids[0].ssid_len == 0\n\t\t|| scan_req->n_channels != 1\n\t)\n\t\tgoto exit;\n\n\t/* under target WPS scan */\n\t_rtw_memcpy(target_ssid, scan_req->ssids, sizeof(struct cfg80211_ssid));\n\tret = 1;\n\nexit:\n\treturn ret;\n}\n\nstatic void _rtw_cfg80211_surveydone_event_callback(_adapter *padapter, struct cfg80211_scan_request *scan_req)\n{\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tRT_CHANNEL_INFO *chset = rfctl->channel_set;\n\t_irqL\tirqL;\n\t_list\t\t\t\t\t*plist, *phead;\n\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\t_queue\t\t\t\t*queue\t= &(pmlmepriv->scanned_queue);\n\tstruct\twlan_network\t*pnetwork = NULL;\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n\tstruct cfg80211_ssid target_ssid;\n\tu8 target_wps_scan = 0;\n\tu8 ch;\n\n#ifdef CONFIG_DEBUG_CFG80211\n\tRTW_INFO(\"%s\\n\", __func__);\n#endif\n\n\tif (scan_req)\n\t\ttarget_wps_scan = rtw_cfg80211_is_target_wps_scan(scan_req, &target_ssid);\n\telse {\n\t\t_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);\n\t\tif (pwdev_priv->scan_request != NULL)\n\t\t\ttarget_wps_scan = rtw_cfg80211_is_target_wps_scan(pwdev_priv->scan_request, &target_ssid);\n\t\t_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);\n\t}\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\n\twhile (1) {\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\t\tch = pnetwork->network.Configuration.DSConfig;\n\n\t\t/* report network only if the current channel set contains the channel to which this network belongs */\n\t\tif (rtw_chset_search_ch(chset, ch) >= 0\n\t\t\t&& rtw_mlme_band_check(padapter, ch) == _TRUE\n\t\t\t&& _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))\n\t\t\t&& (!IS_DFS_SLAVE_WITH_RD(rfctl)\n\t\t\t\t|| rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))\n\t\t\t\t|| !rtw_chset_is_ch_non_ocp(chset, ch))\n\t\t) {\n\t\t\tif (target_wps_scan)\n\t\t\t\trtw_cfg80211_clear_wps_sr_of_non_target_bss(padapter, pnetwork, &target_ssid);\n\t\t\trtw_cfg80211_inform_bss(padapter, pnetwork);\n\t\t}\n#if 0\n\t\t/* check ralink testbed RSN IE length */\n\t\t{\n\t\t\tif (_rtw_memcmp(pnetwork->network.Ssid.Ssid, \"Ralink_11n_AP\", 13)) {\n\t\t\t\tuint ie_len = 0;\n\t\t\t\tu8 *p = NULL;\n\t\t\t\tp = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_));\n\t\t\t\tRTW_INFO(\"ie_len=%d\\n\", ie_len);\n\t\t\t}\n\t\t}\n#endif\n\t\tplist = get_next(plist);\n\n\t}\n\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n}\n\ninline void rtw_cfg80211_surveydone_event_callback(_adapter *padapter)\n{\n\t_rtw_cfg80211_surveydone_event_callback(padapter, NULL);\n}\n\nstatic int rtw_cfg80211_set_probe_req_wpsp2pie(_adapter *padapter, char *buf, int len)\n{\n\tint ret = 0;\n\tuint wps_ielen = 0;\n\tu8 *wps_ie;\n\tu32\tp2p_ielen = 0;\n\tu8 *p2p_ie;\n\tu32\twfd_ielen = 0;\n\tu8 *wfd_ie;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n#ifdef CONFIG_DEBUG_CFG80211\n\tRTW_INFO(\"%s, ielen=%d\\n\", __func__, len);\n#endif\n\n\tif (len > 0) {\n\t\twps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen);\n\t\tif (wps_ie) {\n\t\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\t\tRTW_INFO(\"probe_req_wps_ielen=%d\\n\", wps_ielen);\n\t\t\t#endif\n\n\t\t\tif (pmlmepriv->wps_probe_req_ie) {\n\t\t\t\tu32 free_len = pmlmepriv->wps_probe_req_ie_len;\n\t\t\t\tpmlmepriv->wps_probe_req_ie_len = 0;\n\t\t\t\trtw_mfree(pmlmepriv->wps_probe_req_ie, free_len);\n\t\t\t\tpmlmepriv->wps_probe_req_ie = NULL;\n\t\t\t}\n\n\t\t\tpmlmepriv->wps_probe_req_ie = rtw_malloc(wps_ielen);\n\t\t\tif (pmlmepriv->wps_probe_req_ie == NULL) {\n\t\t\t\tRTW_INFO(\"%s()-%d: rtw_malloc() ERROR!\\n\", __FUNCTION__, __LINE__);\n\t\t\t\treturn -EINVAL;\n\n\t\t\t}\n\t\t\t_rtw_memcpy(pmlmepriv->wps_probe_req_ie, wps_ie, wps_ielen);\n\t\t\tpmlmepriv->wps_probe_req_ie_len = wps_ielen;\n\t\t}\n\n\t\t/* buf += wps_ielen; */\n\t\t/* len -= wps_ielen; */\n\n\t\t#ifdef CONFIG_P2P\n\t\tp2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen);\n\t\tif (p2p_ie) {\n\t\t\tstruct wifidirect_info *wdinfo = &padapter->wdinfo;\n\t\t\tu32 attr_contentlen = 0;\n\t\t\tu8 listen_ch_attr[5];\n\n\t\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\t\tRTW_INFO(\"probe_req_p2p_ielen=%d\\n\", p2p_ielen);\n\t\t\t#endif\n\n\t\t\tif (pmlmepriv->p2p_probe_req_ie) {\n\t\t\t\tu32 free_len = pmlmepriv->p2p_probe_req_ie_len;\n\t\t\t\tpmlmepriv->p2p_probe_req_ie_len = 0;\n\t\t\t\trtw_mfree(pmlmepriv->p2p_probe_req_ie, free_len);\n\t\t\t\tpmlmepriv->p2p_probe_req_ie = NULL;\n\t\t\t}\n\n\t\t\tpmlmepriv->p2p_probe_req_ie = rtw_malloc(p2p_ielen);\n\t\t\tif (pmlmepriv->p2p_probe_req_ie == NULL) {\n\t\t\t\tRTW_INFO(\"%s()-%d: rtw_malloc() ERROR!\\n\", __FUNCTION__, __LINE__);\n\t\t\t\treturn -EINVAL;\n\n\t\t\t}\n\t\t\t_rtw_memcpy(pmlmepriv->p2p_probe_req_ie, p2p_ie, p2p_ielen);\n\t\t\tpmlmepriv->p2p_probe_req_ie_len = p2p_ielen;\n\n\t\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, (u8 *)listen_ch_attr, (uint *) &attr_contentlen)\n\t\t\t\t&& attr_contentlen == 5) {\n\t\t\t\tif (wdinfo->listen_channel !=  listen_ch_attr[4]) {\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" listen channel - country:%c%c%c, class:%u, ch:%u\\n\",\n\t\t\t\t\t\tFUNC_ADPT_ARG(padapter), listen_ch_attr[0], listen_ch_attr[1], listen_ch_attr[2],\n\t\t\t\t\t\tlisten_ch_attr[3], listen_ch_attr[4]);\n\t\t\t\t\twdinfo->listen_channel = listen_ch_attr[4];\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\t#endif /* CONFIG_P2P */\n\n\t\t#ifdef CONFIG_WFD\n\t\twfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen);\n\t\tif (wfd_ie) {\n\t\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\t\tRTW_INFO(\"probe_req_wfd_ielen=%d\\n\", wfd_ielen);\n\t\t\t#endif\n\n\t\t\tif (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_PROBE_REQ_IE, wfd_ie, wfd_ielen) != _SUCCESS)\n\t\t\t\treturn -EINVAL;\n\t\t}\n\t\t#endif /* CONFIG_WFD */\n\t}\n\n\treturn ret;\n\n}\n\n#ifdef CONFIG_CONCURRENT_MODE\nu8 rtw_cfg80211_scan_via_buddy(_adapter *padapter, struct cfg80211_scan_request *request)\n{\n\tint i;\n\tu8 ret = _FALSE;\n\t_adapter *iface = NULL;\n\t_irqL\tirqL;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tstruct mlme_priv *buddy_mlmepriv;\n\t\tstruct rtw_wdev_priv *buddy_wdev_priv;\n\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface == NULL)\n\t\t\tcontinue;\n\n\t\tif (iface == padapter)\n\t\t\tcontinue;\n\n\t\tif (rtw_is_adapter_up(iface) == _FALSE)\n\t\t\tcontinue;\n\n\t\tbuddy_mlmepriv = &iface->mlmepriv;\n\t\tif (!check_fwstate(buddy_mlmepriv, _FW_UNDER_SURVEY))\n\t\t\tcontinue;\n\n\t\tbuddy_wdev_priv = adapter_wdev_data(iface);\n\t\t_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);\n\t\t_enter_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL);\n\t\tif (buddy_wdev_priv->scan_request) {\n\t\t\tpmlmepriv->scanning_via_buddy_intf = _TRUE;\n\t\t\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\t\t\tset_fwstate(pmlmepriv, _FW_UNDER_SURVEY);\n\t\t\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\t\t\tpwdev_priv->scan_request = request;\n\t\t\tret = _TRUE;\n\t\t}\n\t\t_exit_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL);\n\t\t_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);\n\n\t\tif (ret == _TRUE)\n\t\t\tgoto exit;\n\t}\n\nexit:\n\treturn ret;\n}\n\nvoid rtw_cfg80211_indicate_scan_done_for_buddy(_adapter *padapter, bool bscan_aborted)\n{\n\tint i;\n\tu8 ret = 0;\n\t_adapter *iface = NULL;\n\t_irqL\tirqL;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct mlme_priv *mlmepriv;\n\tstruct rtw_wdev_priv *wdev_priv;\n\tbool indicate_buddy_scan;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif ((iface) && rtw_is_adapter_up(iface)) {\n\n\t\t\tif (iface == padapter)\n\t\t\t\tcontinue;\n\n\t\t\tmlmepriv = &(iface->mlmepriv);\n\t\t\twdev_priv = adapter_wdev_data(iface);\n\n\t\t\tindicate_buddy_scan = _FALSE;\n\t\t\t_enter_critical_bh(&wdev_priv->scan_req_lock, &irqL);\n\t\t\tif (mlmepriv->scanning_via_buddy_intf == _TRUE) {\n\t\t\t\tmlmepriv->scanning_via_buddy_intf = _FALSE;\n\t\t\t\tclr_fwstate(mlmepriv, _FW_UNDER_SURVEY);\n\t\t\t\tif (wdev_priv->scan_request)\n\t\t\t\t\tindicate_buddy_scan = _TRUE;\n\t\t\t}\n\t\t\t_exit_critical_bh(&wdev_priv->scan_req_lock, &irqL);\n\n\t\t\tif (indicate_buddy_scan == _TRUE) {\n\t\t\t\trtw_cfg80211_surveydone_event_callback(iface);\n\t\t\t\trtw_indicate_scan_done(iface, bscan_aborted);\n\t\t\t}\n\n\t\t}\n\t}\n}\n#endif /* CONFIG_CONCURRENT_MODE */\n\nstatic int cfg80211_rtw_scan(struct wiphy *wiphy\n\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))\n\t, struct net_device *ndev\n\t#endif\n\t, struct cfg80211_scan_request *request)\n{\n\tint i;\n\tu8 _status = _FALSE;\n\tint ret = 0;\n\tstruct sitesurvey_parm parm;\n\t_irqL\tirqL;\n\tu8 survey_times = 3;\n\tu8 survey_times_for_one_ch = 6;\n\tstruct cfg80211_ssid *ssids = request->ssids;\n\tint social_channel = 0, j = 0;\n\tbool need_indicate_scan_done = _FALSE;\n\tbool ps_denied = _FALSE;\n\tu8 ssc_chk;\n\t_adapter *padapter;\n\tstruct wireless_dev *wdev;\n\tstruct rtw_wdev_priv *pwdev_priv;\n\tstruct mlme_priv *pmlmepriv = NULL;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *pwdinfo;\n#endif /* CONFIG_P2P */\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\twdev = request->wdev;\n\t#if defined(RTW_DEDICATED_P2P_DEVICE)\n\tif (wdev == wiphy_to_pd_wdev(wiphy))\n\t\tpadapter = wiphy_to_adapter(wiphy);\n\telse\n\t#endif\n\tif (wdev_to_ndev(wdev))\n\t\tpadapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));\n\telse {\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n#else\n\tif (ndev == NULL) {\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\tpadapter = (_adapter *)rtw_netdev_priv(ndev);\n\twdev = ndev_to_wdev(ndev);\n#endif\n\n\tpwdev_priv = adapter_wdev_data(padapter);\n\tpmlmepriv = &padapter->mlmepriv;\n#ifdef CONFIG_P2P\n\tpwdinfo = &(padapter->wdinfo);\n#endif /* CONFIG_P2P */\n\n\tRTW_INFO(FUNC_ADPT_FMT\"%s\\n\", FUNC_ADPT_ARG(padapter)\n\t\t, wdev == wiphy_to_pd_wdev(wiphy) ? \" PD\" : \"\");\n\n#if 1\n\tssc_chk = rtw_sitesurvey_condition_check(padapter, _TRUE);\n\n\tif (ssc_chk == SS_DENY_MP_MODE)\n\t\tgoto bypass_p2p_chk;\n#ifdef DBG_LA_MODE\n\tif (ssc_chk == SS_DENY_LA_MODE)\n\t\tgoto bypass_p2p_chk;\n#endif\n#ifdef CONFIG_P2P\n\tif (pwdinfo->driver_interface == DRIVER_CFG80211) {\n\t\tif (request->n_ssids && ssids\n\t\t\t&& _rtw_memcmp(ssids[0].ssid, \"DIRECT-\", 7)\n\t\t\t&& rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL)\n\t\t) {\n\t\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))\n\t\t\t\trtw_p2p_enable(padapter, P2P_ROLE_DEVICE);\n\t\t\telse {\n\t\t\t\trtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));\n\t\t\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\t\t\tRTW_INFO(\"%s, role=%d, p2p_state=%d\\n\", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));\n\t\t\t\t#endif\n\t\t\t}\n\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);\n\n\t\t\tif (request->n_channels == 3 &&\n\t\t\t\trequest->channels[0]->hw_value == 1 &&\n\t\t\t\trequest->channels[1]->hw_value == 6 &&\n\t\t\t\trequest->channels[2]->hw_value == 11\n\t\t\t)\n\t\t\t\tsocial_channel = 1;\n\t\t}\n\t}\n#endif /*CONFIG_P2P*/\n\n\tif (request->ie && request->ie_len > 0)\n\t\trtw_cfg80211_set_probe_req_wpsp2pie(padapter, (u8 *)request->ie, request->ie_len);\n\nbypass_p2p_chk:\n\n\tswitch (ssc_chk) {\n\t\tcase SS_ALLOW :\n\t\t\tbreak;\n\n\t\tcase SS_DENY_MP_MODE:\n\t\t\tret = -EPERM;\n\t\t\tgoto exit;\n\t\t#ifdef DBG_LA_MODE\n\t\tcase SS_DENY_LA_MODE:\n\t\t\tret = -EPERM;\n\t\t\tgoto exit;\n\t\t#endif\n\t\t#ifdef CONFIG_RTW_REPEATER_SON\n\t\tcase SS_DENY_RSON_SCANING :\n\t\t#endif\n\t\tcase SS_DENY_BLOCK_SCAN :\n\t\tcase SS_DENY_SELF_AP_UNDER_WPS :\n\t\tcase SS_DENY_SELF_AP_UNDER_LINKING :\n\t\tcase SS_DENY_SELF_AP_UNDER_SURVEY :\n\t\tcase SS_DENY_SELF_STA_UNDER_SURVEY :\n\t\t#ifdef CONFIG_CONCURRENT_MODE\n\t\tcase SS_DENY_BUDDY_UNDER_LINK_WPS :\n\t\t#endif\n\t\tcase SS_DENY_BUSY_TRAFFIC :\n\t\tcase SS_DENY_ADAPTIVITY:\n\t\t\tneed_indicate_scan_done = _TRUE;\n\t\t\tgoto check_need_indicate_scan_done;\n\n\t\tcase SS_DENY_BY_DRV :\n\t\t\t#if CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY\n\t\t\tret = -EBUSY;\n\t\t\tgoto exit;\n\t\t\t#else\n\t\t\tneed_indicate_scan_done = _TRUE;\n\t\t\tgoto check_need_indicate_scan_done;\n\t\t\t#endif\n\t\t\tbreak;\n\n\t\tcase SS_DENY_SELF_STA_UNDER_LINKING :\n\t\t\tret = -EBUSY;\n\t\t\tgoto check_need_indicate_scan_done;\n\n\t\t#ifdef CONFIG_CONCURRENT_MODE\n\t\tcase SS_DENY_BUDDY_UNDER_SURVEY :\n\t\t\t{\n\t\t\t\tbool scan_via_buddy = rtw_cfg80211_scan_via_buddy(padapter, request);\n\n\t\t\t\tif (scan_via_buddy == _FALSE)\n\t\t\t\t\tneed_indicate_scan_done = _TRUE;\n\n\t\t\t\tgoto check_need_indicate_scan_done;\n\t\t\t}\n\t\t#endif\n\n\t\tdefault :\n\t\t\tRTW_ERR(\"site survey check code (%d) unknown\\n\", ssc_chk);\n\t\t\tneed_indicate_scan_done = _TRUE;\n\t\t\tgoto check_need_indicate_scan_done;\n\t}\n\n\trtw_ps_deny(padapter, PS_DENY_SCAN);\n\tps_denied = _TRUE;\n\tif (_FAIL == rtw_pwr_wakeup(padapter)) {\n\t\tneed_indicate_scan_done = _TRUE;\n\t\tgoto check_need_indicate_scan_done;\n\t}\n\n#else\n\n\n#ifdef CONFIG_MP_INCLUDED\n\tif (rtw_mp_mode_check(padapter)) {\n\t\tRTW_INFO(\"MP mode block Scan request\\n\");\n\t\tret = -EPERM;\n\t\tgoto exit;\n\t}\n#endif\n\n#ifdef CONFIG_P2P\n\tif (pwdinfo->driver_interface == DRIVER_CFG80211) {\n\t\tif (request->n_ssids && ssids\n\t\t\t&& _rtw_memcmp(ssids[0].ssid, \"DIRECT-\", 7)\n\t\t\t&& rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL)\n\t\t) {\n\t\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))\n\t\t\t\trtw_p2p_enable(padapter, P2P_ROLE_DEVICE);\n\t\t\telse {\n\t\t\t\trtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));\n\t\t\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\t\t\tRTW_INFO(\"%s, role=%d, p2p_state=%d\\n\", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));\n\t\t\t\t#endif\n\t\t\t}\n\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);\n\n\t\t\tif (request->n_channels == 3 &&\n\t\t\t\trequest->channels[0]->hw_value == 1 &&\n\t\t\t\trequest->channels[1]->hw_value == 6 &&\n\t\t\t\trequest->channels[2]->hw_value == 11\n\t\t\t)\n\t\t\t\tsocial_channel = 1;\n\t\t}\n\t}\n#endif /*CONFIG_P2P*/\n\n\tif (request->ie && request->ie_len > 0)\n\t\trtw_cfg80211_set_probe_req_wpsp2pie(padapter, (u8 *)request->ie, request->ie_len);\n\n#ifdef CONFIG_RTW_REPEATER_SON\n\tif (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" blocking scan for under rson scanning process\\n\", FUNC_ADPT_ARG(padapter));\n\t\tneed_indicate_scan_done = _TRUE;\n\t\tgoto check_need_indicate_scan_done;\n\t}\n#endif\n\n\tif (adapter_wdev_data(padapter)->block_scan == _TRUE) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" wdev_priv.block_scan is set\\n\", FUNC_ADPT_ARG(padapter));\n\t\tneed_indicate_scan_done = _TRUE;\n\t\tgoto check_need_indicate_scan_done;\n\t}\n\n\trtw_ps_deny(padapter, PS_DENY_SCAN);\n\tps_denied = _TRUE;\n\tif (_FAIL == rtw_pwr_wakeup(padapter)) {\n\t\tneed_indicate_scan_done = _TRUE;\n\t\tgoto check_need_indicate_scan_done;\n\t}\n\n\tif (rtw_is_scan_deny(padapter)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\t\": scan deny\\n\", FUNC_ADPT_ARG(padapter));\n#if CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY\n\t\tret = -EBUSY;\n\t\tgoto exit;\n#else\n\t\tneed_indicate_scan_done = _TRUE;\n\t\tgoto check_need_indicate_scan_done;\n#endif\n\t}\n\n\t/* check fw state*/\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {\n\n#ifdef CONFIG_DEBUG_CFG80211\n\t\tRTW_INFO(FUNC_ADPT_FMT\" under WIFI_AP_STATE\\n\", FUNC_ADPT_ARG(padapter));\n#endif\n\n\t\tif (check_fwstate(pmlmepriv, WIFI_UNDER_WPS | _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) {\n\t\t\tRTW_INFO(\"%s, fwstate=0x%x\\n\", __func__, pmlmepriv->fw_state);\n\n\t\t\tif (check_fwstate(pmlmepriv, WIFI_UNDER_WPS))\n\t\t\t\tRTW_INFO(\"AP mode process WPS\\n\");\n\n\t\t\tneed_indicate_scan_done = _TRUE;\n\t\t\tgoto check_need_indicate_scan_done;\n\t\t}\n\t}\n\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) {\n\t\tRTW_INFO(\"%s, fwstate=0x%x\\n\", __func__, pmlmepriv->fw_state);\n\t\tneed_indicate_scan_done = _TRUE;\n\t\tgoto check_need_indicate_scan_done;\n\t} else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) {\n\t\tRTW_INFO(\"%s, fwstate=0x%x\\n\", __func__, pmlmepriv->fw_state);\n\t\tret = -EBUSY;\n\t\tgoto check_need_indicate_scan_done;\n\t}\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_LINKING | WIFI_UNDER_WPS)) {\n\t\tRTW_INFO(\"%s exit due to buddy_intf's mlme state under linking or wps\\n\", __func__);\n\t\tneed_indicate_scan_done = _TRUE;\n\t\tgoto check_need_indicate_scan_done;\n\n\t} else if (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_SURVEY)) {\n\t\tbool scan_via_buddy = rtw_cfg80211_scan_via_buddy(padapter, request);\n\n\t\tif (scan_via_buddy == _FALSE)\n\t\t\tneed_indicate_scan_done = _TRUE;\n\n\t\tgoto check_need_indicate_scan_done;\n\t}\n#endif /* CONFIG_CONCURRENT_MODE */\n\n\t/* busy traffic check*/\n\tif (rtw_mi_busy_traffic_check(padapter, _TRUE)) {\n\t\tneed_indicate_scan_done = _TRUE;\n\t\tgoto check_need_indicate_scan_done;\n\t}\n#endif\n\n#ifdef CONFIG_P2P\n\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) {\n\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);\n\n\t\tif (social_channel == 0)\n\t\t\trtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);\n\t\telse\n\t\t\trtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_SOCIAL_LAST);\n\t}\n#endif /* CONFIG_P2P */\n\n\trtw_init_sitesurvey_parm(padapter, &parm);\n\n\t/* parsing request ssids, n_ssids */\n\tfor (i = 0; i < request->n_ssids && ssids && i < RTW_SSID_SCAN_AMOUNT; i++) {\n\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\tRTW_INFO(\"ssid=%s, len=%d\\n\", ssids[i].ssid, ssids[i].ssid_len);\n\t\t#endif\n\t\t_rtw_memcpy(&parm.ssid[i].Ssid, ssids[i].ssid, ssids[i].ssid_len);\n\t\tparm.ssid[i].SsidLength = ssids[i].ssid_len;\n\t}\n\tparm.ssid_num = i;\n\n\t/* parsing channels, n_channels */\n\tfor (i = 0; i < request->n_channels && i < RTW_CHANNEL_SCAN_AMOUNT; i++) {\n\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\tRTW_INFO(FUNC_ADPT_FMT CHAN_FMT\"\\n\", FUNC_ADPT_ARG(padapter), CHAN_ARG(request->channels[i]));\n\t\t#endif\n\t\tparm.ch[i].hw_value = request->channels[i]->hw_value;\n\t\tparm.ch[i].flags = request->channels[i]->flags;\n\t}\n\tparm.ch_num = i;\n\n\tif (request->n_channels == 1) {\n\t\tfor (i = 1; i < survey_times_for_one_ch; i++)\n\t\t\t_rtw_memcpy(&parm.ch[i], &parm.ch[0], sizeof(struct rtw_ieee80211_channel));\n\t\tparm.ch_num = survey_times_for_one_ch;\n\t} else if (request->n_channels <= 4) {\n\t\tfor (j = request->n_channels - 1; j >= 0; j--)\n\t\t\tfor (i = 0; i < survey_times; i++)\n\t\t\t\t_rtw_memcpy(&parm.ch[j * survey_times + i], &parm.ch[j], sizeof(struct rtw_ieee80211_channel));\n\t\tparm.ch_num = survey_times * request->n_channels;\n\t}\n\n\t_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\t_status = rtw_sitesurvey_cmd(padapter, &parm);\n\tif (_status == _SUCCESS)\n\t\tpwdev_priv->scan_request = request;\n\telse\n\t\tret = -1;\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\t_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);\n\ncheck_need_indicate_scan_done:\n\tif (_TRUE == need_indicate_scan_done) {\n#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE)\n\t\tstruct cfg80211_scan_info info;\n\n\t\tmemset(&info, 0, sizeof(info));\n\t\tinfo.aborted = 0;\n#endif\n\n\t\t_rtw_cfg80211_surveydone_event_callback(padapter, request);\n#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE)\n\t\tcfg80211_scan_done(request, &info);\n#else\n\t\tcfg80211_scan_done(request, 0);\n#endif\n\t}\n\n\tif (ps_denied == _TRUE)\n\t\trtw_ps_deny_cancel(padapter, PS_DENY_SCAN);\n\nexit:\n\tif (pmlmepriv)\n\t\tpmlmepriv->lastscantime = rtw_get_current_time();\n\n\treturn ret;\n}\n\nstatic int cfg80211_rtw_set_wiphy_params(struct wiphy *wiphy, u32 changed)\n{\n#if 0\n\tstruct iwm_priv *iwm = wiphy_to_iwm(wiphy);\n\n\tif (changed & WIPHY_PARAM_RTS_THRESHOLD &&\n\t    (iwm->conf.rts_threshold != wiphy->rts_threshold)) {\n\t\tint ret;\n\n\t\tiwm->conf.rts_threshold = wiphy->rts_threshold;\n\n\t\tret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX,\n\t\t\t\tCFG_RTS_THRESHOLD,\n\t\t\t\tiwm->conf.rts_threshold);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t}\n\n\tif (changed & WIPHY_PARAM_FRAG_THRESHOLD &&\n\t    (iwm->conf.frag_threshold != wiphy->frag_threshold)) {\n\t\tint ret;\n\n\t\tiwm->conf.frag_threshold = wiphy->frag_threshold;\n\n\t\tret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_FA_CFG_FIX,\n\t\t\t\tCFG_FRAG_THRESHOLD,\n\t\t\t\tiwm->conf.frag_threshold);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t}\n#endif\n\tRTW_INFO(\"%s\\n\", __func__);\n\treturn 0;\n}\n\n\n\nstatic int rtw_cfg80211_set_wpa_version(struct security_priv *psecuritypriv, u32 wpa_version)\n{\n\tRTW_INFO(\"%s, wpa_version=%d\\n\", __func__, wpa_version);\n\n\tif (!wpa_version) {\n\t\tpsecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;\n\t\treturn 0;\n\t}\n\n\n\tif (wpa_version & (NL80211_WPA_VERSION_1 | NL80211_WPA_VERSION_2))\n\t\tpsecuritypriv->ndisauthtype = Ndis802_11AuthModeWPAPSK;\n\n#if 0\n\tif (wpa_version & NL80211_WPA_VERSION_2)\n\t\tpsecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK;\n#endif\n\n\t#ifdef CONFIG_WAPI_SUPPORT\n\tif (wpa_version & NL80211_WAPI_VERSION_1)\n\t\tpsecuritypriv->ndisauthtype = Ndis802_11AuthModeWAPI;\n\t#endif\n\n\treturn 0;\n\n}\n\nstatic int rtw_cfg80211_set_auth_type(struct security_priv *psecuritypriv,\n\t\tenum nl80211_auth_type sme_auth_type)\n{\n\tRTW_INFO(\"%s, nl80211_auth_type=%d\\n\", __func__, sme_auth_type);\n\n\tpsecuritypriv->auth_type = sme_auth_type;\n\n\tif (sme_auth_type == NL80211_AUTHTYPE_SAE) {\n\t\tpsecuritypriv->auth_alg = WLAN_AUTH_SAE;\n\t\treturn 0;\n\t}\n\n\tswitch (sme_auth_type) {\n\tcase NL80211_AUTHTYPE_AUTOMATIC:\n\n\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;\n\n\t\tbreak;\n\tcase NL80211_AUTHTYPE_OPEN_SYSTEM:\n\n\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open;\n\n\t\tif (psecuritypriv->ndisauthtype > Ndis802_11AuthModeWPA)\n\t\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;\n\n#ifdef CONFIG_WAPI_SUPPORT\n\t\tif (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWAPI)\n\t\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;\n#endif\n\n\t\tbreak;\n\tcase NL80211_AUTHTYPE_SHARED_KEY:\n\n\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Shared;\n\n\t\tpsecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;\n\n\n\t\tbreak;\n\tdefault:\n\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open;\n\t\t/* return -ENOTSUPP; */\n\t}\n\n\treturn 0;\n\n}\n\nstatic int rtw_cfg80211_set_cipher(struct security_priv *psecuritypriv, u32 cipher, bool ucast)\n{\n\tu32 ndisencryptstatus = Ndis802_11EncryptionDisabled;\n\n\tu32 *profile_cipher = ucast ? &psecuritypriv->dot11PrivacyAlgrthm :\n\t\t&psecuritypriv->dot118021XGrpPrivacy;\n\n\tRTW_INFO(\"%s, ucast=%d, cipher=0x%x\\n\", __func__, ucast, cipher);\n\n\n\tif (!cipher) {\n\t\t*profile_cipher = _NO_PRIVACY_;\n\t\tpsecuritypriv->ndisencryptstatus = ndisencryptstatus;\n\t\treturn 0;\n\t}\n\n\tswitch (cipher) {\n\tcase IW_AUTH_CIPHER_NONE:\n\t\t*profile_cipher = _NO_PRIVACY_;\n\t\tndisencryptstatus = Ndis802_11EncryptionDisabled;\n#ifdef CONFIG_WAPI_SUPPORT\n\t\tif (psecuritypriv->dot11PrivacyAlgrthm == _SMS4_)\n\t\t\t*profile_cipher = _SMS4_;\n#endif\n\t\tbreak;\n\tcase WLAN_CIPHER_SUITE_WEP40:\n\t\t*profile_cipher = _WEP40_;\n\t\tndisencryptstatus = Ndis802_11Encryption1Enabled;\n\t\tbreak;\n\tcase WLAN_CIPHER_SUITE_WEP104:\n\t\t*profile_cipher = _WEP104_;\n\t\tndisencryptstatus = Ndis802_11Encryption1Enabled;\n\t\tbreak;\n\tcase WLAN_CIPHER_SUITE_TKIP:\n\t\t*profile_cipher = _TKIP_;\n\t\tndisencryptstatus = Ndis802_11Encryption2Enabled;\n\t\tbreak;\n\tcase WLAN_CIPHER_SUITE_CCMP:\n\t\t*profile_cipher = _AES_;\n\t\tndisencryptstatus = Ndis802_11Encryption3Enabled;\n\t\tbreak;\n#ifdef CONFIG_WAPI_SUPPORT\n\tcase WLAN_CIPHER_SUITE_SMS4:\n\t\t*profile_cipher = _SMS4_;\n\t\tndisencryptstatus = Ndis802_11_EncrypteionWAPI;\n\t\tbreak;\n#endif\n\tdefault:\n\t\tRTW_INFO(\"Unsupported cipher: 0x%x\\n\", cipher);\n\t\treturn -ENOTSUPP;\n\t}\n\n\tif (ucast) {\n\t\tpsecuritypriv->ndisencryptstatus = ndisencryptstatus;\n\n\t\t/* if(psecuritypriv->dot11PrivacyAlgrthm >= _AES_) */\n\t\t/*\tpsecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK; */\n\t}\n\n\treturn 0;\n}\n\nstatic int rtw_cfg80211_set_key_mgt(struct security_priv *psecuritypriv, u32 key_mgt)\n{\n\tRTW_INFO(\"%s, key_mgt=0x%x\\n\", __func__, key_mgt);\n\n\tif (key_mgt == WLAN_AKM_SUITE_8021X) {\n\t\t/* *auth_type = UMAC_AUTH_TYPE_8021X; */\n\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;\n\t\tpsecuritypriv->rsn_akm_suite_type = 1;\n\t} else if (key_mgt == WLAN_AKM_SUITE_PSK) {\n\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;\n\t\tpsecuritypriv->rsn_akm_suite_type = 2;\n\t}\n#ifdef CONFIG_WAPI_SUPPORT\n\telse if (key_mgt == WLAN_AKM_SUITE_WAPI_PSK)\n\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;\n\telse if (key_mgt == WLAN_AKM_SUITE_WAPI_CERT)\n\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;\n#endif\n#ifdef CONFIG_RTW_80211R\n\telse if (key_mgt == WLAN_AKM_SUITE_FT_8021X) {\n\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;\n\t\tpsecuritypriv->rsn_akm_suite_type = 3;\n\t} else if (key_mgt == WLAN_AKM_SUITE_FT_PSK) {\n\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;\n\t\tpsecuritypriv->rsn_akm_suite_type = 4;\n\t}\n#endif\n\telse if (key_mgt == WLAN_AKM_SUITE_SAE) { \n\t\tpsecuritypriv->rsn_akm_suite_type = 8; \n\t} else {\n\t\tRTW_INFO(\"Invalid key mgt: 0x%x\\n\", key_mgt);\n\t\t/* return -EINVAL; */\n\t}\n\n\treturn 0;\n}\n\nstatic int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen)\n{\n\tu8 *buf = NULL, *pos = NULL;\n\tint group_cipher = 0, pairwise_cipher = 0;\n\tu8 mfp_opt = MFP_NO;\n\tint ret = 0;\n\tint wpa_ielen = 0;\n\tint wpa2_ielen = 0;\n\tu8 *pwpa, *pwpa2;\n\tu8 null_addr[] = {0, 0, 0, 0, 0, 0};\n\n\tif (pie == NULL || !ielen) {\n\t\t/* Treat this as normal case, but need to clear WIFI_UNDER_WPS */\n\t\t_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);\n\t\tgoto exit;\n\t}\n\n\tif (ielen > MAX_WPA_IE_LEN + MAX_WPS_IE_LEN + MAX_P2P_IE_LEN) {\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\n\tbuf = rtw_zmalloc(ielen);\n\tif (buf == NULL) {\n\t\tret =  -ENOMEM;\n\t\tgoto exit;\n\t}\n\n\t_rtw_memcpy(buf, pie , ielen);\n\n\tRTW_INFO(\"set wpa_ie(length:%zu):\\n\", ielen);\n\tRTW_INFO_DUMP(NULL, buf, ielen);\n\n\tpos = buf;\n\tif (ielen < RSN_HEADER_LEN) {\n\t\tret  = -1;\n\t\tgoto exit;\n\t}\n\n\tpwpa = rtw_get_wpa_ie(buf, &wpa_ielen, ielen);\n\tif (pwpa && wpa_ielen > 0) {\n\t\tif (rtw_parse_wpa_ie(pwpa, wpa_ielen + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {\n\t\t\tpadapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;\n\t\t\tpadapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK;\n\t\t\t_rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa[0], wpa_ielen + 2);\n\n\t\t\tRTW_INFO(\"got wpa_ie, wpa_ielen:%u\\n\", wpa_ielen);\n\t\t}\n\t}\n\n\tpwpa2 = rtw_get_wpa2_ie(buf, &wpa2_ielen, ielen);\n\tif (pwpa2 && wpa2_ielen > 0) {\n\t\tif (rtw_parse_wpa2_ie(pwpa2, wpa2_ielen + 2, &group_cipher, &pairwise_cipher, NULL, &mfp_opt) == _SUCCESS) {\n\t\t\tpadapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;\n\t\t\tpadapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK;\n\t\t\t_rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa2[0], wpa2_ielen + 2);\n\n\t\t\tRTW_INFO(\"got wpa2_ie, wpa2_ielen:%u\\n\", wpa2_ielen);\n\t\t}\n\t}\n\n\tif (group_cipher == 0)\n\t\tgroup_cipher = WPA_CIPHER_NONE;\n\tif (pairwise_cipher == 0)\n\t\tpairwise_cipher = WPA_CIPHER_NONE;\n\n\tswitch (group_cipher) {\n\tcase WPA_CIPHER_NONE:\n\t\tpadapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;\n\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;\n\t\tbreak;\n\tcase WPA_CIPHER_WEP40:\n\t\tpadapter->securitypriv.dot118021XGrpPrivacy = _WEP40_;\n\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;\n\t\tbreak;\n\tcase WPA_CIPHER_TKIP:\n\t\tpadapter->securitypriv.dot118021XGrpPrivacy = _TKIP_;\n\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;\n\t\tbreak;\n\tcase WPA_CIPHER_CCMP:\n\t\tpadapter->securitypriv.dot118021XGrpPrivacy = _AES_;\n\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;\n\t\tbreak;\n\tcase WPA_CIPHER_WEP104:\n\t\tpadapter->securitypriv.dot118021XGrpPrivacy = _WEP104_;\n\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;\n\t\tbreak;\n\t}\n\n\tswitch (pairwise_cipher) {\n\tcase WPA_CIPHER_NONE:\n\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;\n\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;\n\t\tbreak;\n\tcase WPA_CIPHER_WEP40:\n\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_;\n\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;\n\t\tbreak;\n\tcase WPA_CIPHER_TKIP:\n\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _TKIP_;\n\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;\n\t\tbreak;\n\tcase WPA_CIPHER_CCMP:\n\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _AES_;\n\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;\n\t\tbreak;\n\tcase WPA_CIPHER_WEP104:\n\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;\n\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;\n\t\tbreak;\n\t}\n\n\tif (mfp_opt == MFP_INVALID) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" invalid MFP setting\\n\", FUNC_ADPT_ARG(padapter));\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\tpadapter->securitypriv.mfp_opt = mfp_opt;\n\n\t{/* handle wps_ie */\n\t\tuint wps_ielen;\n\t\tu8 *wps_ie;\n\n\t\twps_ie = rtw_get_wps_ie(buf, ielen, NULL, &wps_ielen);\n\t\tif (wps_ie && wps_ielen > 0) {\n\t\t\tRTW_INFO(\"got wps_ie, wps_ielen:%u\\n\", wps_ielen);\n\t\t\tpadapter->securitypriv.wps_ie_len = wps_ielen < MAX_WPS_IE_LEN ? wps_ielen : MAX_WPS_IE_LEN;\n\t\t\t_rtw_memcpy(padapter->securitypriv.wps_ie, wps_ie, padapter->securitypriv.wps_ie_len);\n\t\t\tset_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS);\n\t\t} else\n\t\t\t_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);\n\t}\n\n\t#ifdef CONFIG_P2P\n\t{/* check p2p_ie for assoc req; */\n\t\tuint p2p_ielen = 0;\n\t\tu8 *p2p_ie;\n\t\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\t\tp2p_ie = rtw_get_p2p_ie(buf, ielen, NULL, &p2p_ielen);\n\t\tif (p2p_ie) {\n\t\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\t\tRTW_INFO(\"%s p2p_assoc_req_ielen=%d\\n\", __FUNCTION__, p2p_ielen);\n\t\t\t#endif\n\n\t\t\tif (pmlmepriv->p2p_assoc_req_ie) {\n\t\t\t\tu32 free_len = pmlmepriv->p2p_assoc_req_ie_len;\n\t\t\t\tpmlmepriv->p2p_assoc_req_ie_len = 0;\n\t\t\t\trtw_mfree(pmlmepriv->p2p_assoc_req_ie, free_len);\n\t\t\t\tpmlmepriv->p2p_assoc_req_ie = NULL;\n\t\t\t}\n\n\t\t\tpmlmepriv->p2p_assoc_req_ie = rtw_malloc(p2p_ielen);\n\t\t\tif (pmlmepriv->p2p_assoc_req_ie == NULL) {\n\t\t\t\tRTW_INFO(\"%s()-%d: rtw_malloc() ERROR!\\n\", __FUNCTION__, __LINE__);\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\t_rtw_memcpy(pmlmepriv->p2p_assoc_req_ie, p2p_ie, p2p_ielen);\n\t\t\tpmlmepriv->p2p_assoc_req_ie_len = p2p_ielen;\n\t\t}\n\t}\n\t#endif /* CONFIG_P2P */\n\n\t#ifdef CONFIG_WFD\n\t{\n\t\tuint wfd_ielen = 0;\n\t\tu8 *wfd_ie;\n\t\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\t\twfd_ie = rtw_get_wfd_ie(buf, ielen, NULL, &wfd_ielen);\n\t\tif (wfd_ie) {\n\t\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\t\tRTW_INFO(\"%s wfd_assoc_req_ielen=%d\\n\", __FUNCTION__, wfd_ielen);\n\t\t\t#endif\n\n\t\t\tif (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_ASSOC_REQ_IE, wfd_ie, wfd_ielen) != _SUCCESS)\n\t\t\t\tgoto exit;\n\t\t}\n\t}\n\t#endif /* CONFIG_WFD */\n\n\t/* TKIP and AES disallow multicast packets until installing group key */\n\tif (padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_\n\t\t|| padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_\n\t\t|| padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)\n\t\t/* WPS open need to enable multicast */\n\t\t/* || check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE) */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr);\n\n\nexit:\n\tif (buf)\n\t\trtw_mfree(buf, ielen);\n\tif (ret)\n\t\t_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);\n\n\treturn ret;\n}\n\nstatic int cfg80211_rtw_join_ibss(struct wiphy *wiphy, struct net_device *ndev,\n\t\t\t\t  struct cfg80211_ibss_params *params)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tNDIS_802_11_SSID ndis_ssid;\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tstruct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))\n\tstruct cfg80211_chan_def *pch_def;\n#endif\n\tstruct ieee80211_channel *pch;\n\tint ret = 0;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))\n\tpch_def = (struct cfg80211_chan_def *)(&params->chandef);\n\tpch = (struct ieee80211_channel *) pch_def->chan;\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))\n\tpch = (struct ieee80211_channel *)(params->channel);\n#endif\n\n\tif (!params->ssid || !params->ssid_len) {\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\n\tif (params->ssid_len > IW_ESSID_MAX_SIZE) {\n\t\tret = -E2BIG;\n\t\tgoto exit;\n\t}\n\n\trtw_ps_deny(padapter, PS_DENY_JOIN);\n\tif (_FAIL == rtw_pwr_wakeup(padapter)) {\n\t\tret = -EPERM;\n\t\tgoto cancel_ps_deny;\n\t}\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_LINKING)) {\n\t\tRTW_INFO(\"%s, but buddy_intf is under linking\\n\", __FUNCTION__);\n\t\tret = -EINVAL;\n\t\tgoto cancel_ps_deny;\n\t}\n\trtw_mi_buddy_scan_abort(padapter, _TRUE); /* OR rtw_mi_scan_abort(padapter, _TRUE);*/\n#endif /*CONFIG_CONCURRENT_MODE*/\n\n\n\t_rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID));\n\tndis_ssid.SsidLength = params->ssid_len;\n\t_rtw_memcpy(ndis_ssid.Ssid, (u8 *)params->ssid, params->ssid_len);\n\n\t/* RTW_INFO(\"ssid=%s, len=%zu\\n\", ndis_ssid.Ssid, params->ssid_len); */\n\n\tpsecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled;\n\tpsecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;\n\tpsecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;\n\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */\n\tpsecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;\n\n\tret = rtw_cfg80211_set_auth_type(psecuritypriv, NL80211_AUTHTYPE_OPEN_SYSTEM);\n\trtw_set_802_11_authentication_mode(padapter, psecuritypriv->ndisauthtype);\n\n\tRTW_INFO(\"%s: center_freq = %d\\n\", __func__, pch->center_freq);\n\tpmlmeext->cur_channel = rtw_freq2ch(pch->center_freq);\n\n\tif (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) {\n\t\tret = -1;\n\t\tgoto cancel_ps_deny;\n\t}\n\ncancel_ps_deny:\n\trtw_ps_deny_cancel(padapter, PS_DENY_JOIN);\nexit:\n\treturn ret;\n}\n\nstatic int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *ndev)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct wireless_dev *rtw_wdev = padapter->rtw_wdev;\n\tenum nl80211_iftype old_type;\n\tint ret = 0;\n\n\tRTW_INFO(FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(ndev));\n\n#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)\n\trtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 1);\n#endif\n\n\told_type = rtw_wdev->iftype;\n\n\trtw_set_to_roam(padapter, 0);\n\n\tif (check_fwstate(&padapter->mlmepriv, _FW_LINKED)) {\n\t\trtw_scan_abort(padapter);\n\t\tLeaveAllPowerSaveMode(padapter);\n\n\t\trtw_wdev->iftype = NL80211_IFTYPE_STATION;\n\n\t\tif (rtw_set_802_11_infrastructure_mode(padapter, Ndis802_11Infrastructure) == _FALSE) {\n\t\t\trtw_wdev->iftype = old_type;\n\t\t\tret = -EPERM;\n\t\t\tgoto leave_ibss;\n\t\t}\n\t\trtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK);\n\t}\n\nleave_ibss:\n#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)\n\trtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 0);\n#endif\n\n\treturn 0;\n}\n\nbool rtw_cfg80211_is_connect_requested(_adapter *adapter)\n{\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);\n\t_irqL irqL;\n\tbool requested;\n\n\t_enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL);\n\trequested = pwdev_priv->connect_req ? 1 : 0;\n\t_exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL);\n\n\treturn requested;\n}\n\nstatic int _rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\n\n\t/* if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)) */\n\t{\n\t\trtw_scan_abort(padapter);\n\t\trtw_join_abort_timeout(padapter, 300);\n\t\tLeaveAllPowerSaveMode(padapter);\n\t\trtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK);\n#ifdef CONFIG_RTW_REPEATER_SON\n\t\trtw_rson_do_disconnect(padapter);\n#endif\n\t\tRTW_INFO(\"%s...call rtw_indicate_disconnect\\n\", __func__);\n\n\t\trtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK);\n\n\t\t/* indicate locally_generated = 0 when suspend */\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0))\n\t\trtw_indicate_disconnect(padapter, 0, wiphy->dev.power.is_prepared ? _FALSE : _TRUE);\n\t\t#else\n\t\t/*\n\t\t* for kernel < 4.2, DISCONNECT event is hardcoded with\n\t\t* NL80211_ATTR_DISCONNECTED_BY_AP=1 in NL80211 layer\n\t\t* no need to judge if under suspend\n\t\t*/\n\t\trtw_indicate_disconnect(padapter, 0, _TRUE);\n\t\t#endif\n\n\t\trtw_pwr_wakeup(padapter);\n\t}\n\treturn 0;\n}\n\n#if (KERNEL_VERSION(4, 17, 0) > LINUX_VERSION_CODE)\nstatic bool rtw_check_connect_sae_compat(struct cfg80211_connect_params *sme)\n{\n\tstruct rtw_ieee802_11_elems elems;\n\tstruct rsne_info info;\n\tu8 AKM_SUITE_SAE[] = { 0x00, 0x0f, 0xac, 8 };\n\tint i;\n\n\tif (sme->auth_type != 1)\n\t\treturn false;\n\n\tif (rtw_ieee802_11_parse_elems((u8 *)sme->ie, sme->ie_len, &elems, 0)\n\t    == ParseFailed)\n\t\treturn false;\n\n\tif (!elems.rsn_ie)\n\t\treturn false;\n\n\tif (rtw_rsne_info_parse(elems.rsn_ie - 2, elems.rsn_ie_len + 2, &info) == _FAIL)\n\t\treturn false;\n\n\tfor (i = 0; i < info.akm_cnt; i++)\n\t\tif (memcmp(info.akm_list + i * RSN_SELECTOR_LEN,\n\t\t\t   AKM_SUITE_SAE, RSN_SELECTOR_LEN) == 0)\n\t\t\treturn true;\n\n\treturn false;\n}\n#else\n#define rtw_check_connect_sae_compat(sme)\tfalse\n#endif\n\nstatic int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev,\n\t\t\t\tstruct cfg80211_connect_params *sme)\n{\n\tint ret = 0;\n\tNDIS_802_11_AUTHENTICATION_MODE authmode;\n\tNDIS_802_11_SSID ndis_ssid;\n\t/* u8 matched_by_bssid=_FALSE; */\n\t/* u8 matched_by_ssid=_FALSE; */\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\t_irqL irqL;\n\n#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT)\n\trtw_wdev_set_not_indic_disco(pwdev_priv, 1);\n#endif\n\n\tRTW_INFO(\"=>\"FUNC_NDEV_FMT\" - Start to Connection\\n\", FUNC_NDEV_ARG(ndev));\n\tRTW_INFO(\"privacy=%d, key=%p, key_len=%d, key_idx=%d, auth_type=%d\\n\",\n\t\tsme->privacy, sme->key, sme->key_len, sme->key_idx, sme->auth_type);\n\n\tif (rtw_check_connect_sae_compat(sme)) {\n\t\tsme->auth_type = NL80211_AUTHTYPE_SAE;\n\t\tRTW_INFO(\"%s set sme->auth_type=%d for SAE compat\\n\", __FUNCTION__,\n\t\t\t NL80211_AUTHTYPE_SAE);\n\t}\n\n\tif (pwdev_priv->block == _TRUE) {\n\t\tret = -EBUSY;\n\t\tRTW_INFO(\"%s wdev_priv.block is set\\n\", __FUNCTION__);\n\t\tgoto exit;\n\t}\n\n       if (check_fwstate(pmlmepriv, _FW_LINKED | _FW_UNDER_LINKING) == _TRUE) {\n\n\t\t_rtw_disconnect(wiphy, ndev);\n\t\tRTW_INFO(\"%s disconnect before connecting! fw_state=0x%x\\n\",\n\t\t\t__FUNCTION__, pmlmepriv->fw_state);\n\t}\n\n#ifdef CONFIG_PLATFORM_MSTAR_SCAN_BEFORE_CONNECT\n\tprintk(\"MStar Android!\\n\");\n\tif (pwdev_priv->bandroid_scan == _FALSE) {\n#ifdef CONFIG_P2P\n\t\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))\n#endif /* CONFIG_P2P */\n\t\t{\n\t\t\tret = -EBUSY;\n\t\t\tprintk(\"Android hasn't attached yet!\\n\");\n\t\t\tgoto exit;\n\t\t}\n\t}\n#endif\n\n\tif (!sme->ssid || !sme->ssid_len) {\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\n\tif (sme->ssid_len > IW_ESSID_MAX_SIZE) {\n\t\tret = -E2BIG;\n\t\tgoto exit;\n\t}\n\n\trtw_ps_deny(padapter, PS_DENY_JOIN);\n\tif (_FAIL == rtw_pwr_wakeup(padapter)) {\n\t\tret = -EPERM;\n\t\tgoto cancel_ps_deny;\n\t}\n\n\trtw_mi_scan_abort(padapter, _TRUE);\n\n\trtw_join_abort_timeout(padapter, 300);\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_LINKING)) {\n\t\tret = -EINVAL;\n\t\tgoto cancel_ps_deny;\n\t}\n#endif\n\n\t_rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID));\n\tndis_ssid.SsidLength = sme->ssid_len;\n\t_rtw_memcpy(ndis_ssid.Ssid, (u8 *)sme->ssid, sme->ssid_len);\n\n\tRTW_INFO(\"ssid=%s, len=%zu\\n\", ndis_ssid.Ssid, sme->ssid_len);\n\n\n\tif (sme->bssid)\n\t\tRTW_INFO(\"bssid=\"MAC_FMT\"\\n\", MAC_ARG(sme->bssid));\n\n\n\tpsecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled;\n\tpsecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;\n\tpsecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;\n\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */\n\tpsecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;\n\tpsecuritypriv->auth_alg = WLAN_AUTH_OPEN;\n\tpsecuritypriv->extauth_status = WLAN_STATUS_UNSPECIFIED_FAILURE;\n\n#ifdef CONFIG_WAPI_SUPPORT\n\tpadapter->wapiInfo.bWapiEnable = false;\n#endif\n\n\tret = rtw_cfg80211_set_wpa_version(psecuritypriv, sme->crypto.wpa_versions);\n\tif (ret < 0)\n\t\tgoto cancel_ps_deny;\n\n#ifdef CONFIG_WAPI_SUPPORT\n\tif (sme->crypto.wpa_versions & NL80211_WAPI_VERSION_1) {\n\t\tpadapter->wapiInfo.bWapiEnable = true;\n\t\tpadapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN;\n\t\tpadapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN;\n\t}\n#endif\n\n\tret = rtw_cfg80211_set_auth_type(psecuritypriv, sme->auth_type);\n\n#ifdef CONFIG_WAPI_SUPPORT\n\tif (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_WAPI)\n\t\tpadapter->mlmeextpriv.mlmext_info.auth_algo = psecuritypriv->dot11AuthAlgrthm;\n#endif\n\n\n\tif (ret < 0)\n\t\tgoto cancel_ps_deny;\n\n\tRTW_INFO(\"%s, ie_len=%zu\\n\", __func__, sme->ie_len);\n\n\tret = rtw_cfg80211_set_wpa_ie(padapter, (u8 *)sme->ie, sme->ie_len);\n\tif (ret < 0)\n\t\tgoto cancel_ps_deny;\n\n\tif (sme->crypto.n_ciphers_pairwise) {\n\t\tret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.ciphers_pairwise[0], _TRUE);\n\t\tif (ret < 0)\n\t\t\tgoto cancel_ps_deny;\n\t}\n\n\t/* For WEP Shared auth */\n\tif (sme->key_len > 0 && sme->key) {\n\t\tu32 wep_key_idx, wep_key_len, wep_total_len;\n\t\tNDIS_802_11_WEP\t*pwep = NULL;\n\t\tRTW_INFO(\"%s(): Shared/Auto WEP\\n\", __FUNCTION__);\n\n\t\twep_key_idx = sme->key_idx;\n\t\twep_key_len = sme->key_len;\n\n\t\tif (sme->key_idx > WEP_KEYS) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto cancel_ps_deny;\n\t\t}\n\n\t\tif (wep_key_len > 0) {\n\t\t\twep_key_len = wep_key_len <= 5 ? 5 : 13;\n\t\t\twep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial);\n\t\t\tpwep = (NDIS_802_11_WEP *) rtw_malloc(wep_total_len);\n\t\t\tif (pwep == NULL) {\n\t\t\t\tRTW_INFO(\" wpa_set_encryption: pwep allocate fail !!!\\n\");\n\t\t\t\tret = -ENOMEM;\n\t\t\t\tgoto cancel_ps_deny;\n\t\t\t}\n\n\t\t\t_rtw_memset(pwep, 0, wep_total_len);\n\n\t\t\tpwep->KeyLength = wep_key_len;\n\t\t\tpwep->Length = wep_total_len;\n\n\t\t\tif (wep_key_len == 13) {\n\t\t\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;\n\t\t\t\tpadapter->securitypriv.dot118021XGrpPrivacy = _WEP104_;\n\t\t\t}\n\t\t} else {\n\t\t\tret = -EINVAL;\n\t\t\tgoto cancel_ps_deny;\n\t\t}\n\n\t\tpwep->KeyIndex = wep_key_idx;\n\t\tpwep->KeyIndex |= 0x80000000;\n\n\t\t_rtw_memcpy(pwep->KeyMaterial, (void *)sme->key, pwep->KeyLength);\n\n\t\tif (rtw_set_802_11_add_wep(padapter, pwep) == (u8)_FAIL)\n\t\t\tret = -EOPNOTSUPP ;\n\n\t\tif (pwep)\n\t\t\trtw_mfree((u8 *)pwep, wep_total_len);\n\n\t\tif (ret < 0)\n\t\t\tgoto cancel_ps_deny;\n\t}\n\n\tret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.cipher_group, _FALSE);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tif (sme->crypto.n_akm_suites) {\n\t\tret = rtw_cfg80211_set_key_mgt(psecuritypriv, sme->crypto.akm_suites[0]);\n\t\tif (ret < 0)\n\t\t\tgoto cancel_ps_deny;\n\t}\n#ifdef CONFIG_8011R\n\telse {\n\t\t/*It could be a connection without RSN IEs*/\n\t\tpsecuritypriv->rsn_akm_suite_type = 0;\n\t}\n#endif\n\n#ifdef CONFIG_WAPI_SUPPORT\n\tif (sme->crypto.akm_suites[0] == WLAN_AKM_SUITE_WAPI_PSK)\n\t\tpadapter->wapiInfo.bWapiPSK = true;\n\telse if (sme->crypto.akm_suites[0] == WLAN_AKM_SUITE_WAPI_CERT)\n\t\tpadapter->wapiInfo.bWapiPSK = false;\n#endif\n\n\tauthmode = psecuritypriv->ndisauthtype;\n\trtw_set_802_11_authentication_mode(padapter, authmode);\n\n\t/* rtw_set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */\n\n\tif (rtw_set_802_11_connect(padapter, (u8 *)sme->bssid, &ndis_ssid, \\\n\t\t\tsme->channel ? sme->channel->hw_value : 0) == _FALSE) {\n\t\tret = -1;\n\t\tgoto cancel_ps_deny;\n\t}\n\n\n\t_enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL);\n\n\tif (pwdev_priv->connect_req) {\n\t\trtw_wdev_free_connect_req(pwdev_priv);\n\t\tRTW_INFO(FUNC_NDEV_FMT\" free existing connect_req\\n\", FUNC_NDEV_ARG(ndev));\n\t}\n\n\tpwdev_priv->connect_req = (struct cfg80211_connect_params *)rtw_malloc(sizeof(*pwdev_priv->connect_req));\n\tif (pwdev_priv->connect_req)\n\t\t_rtw_memcpy(pwdev_priv->connect_req, sme, sizeof(*pwdev_priv->connect_req));\n\telse\n\t\tRTW_WARN(FUNC_NDEV_FMT\" alloc connect_req fail\\n\", FUNC_NDEV_ARG(ndev));\n\n\t_exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL);\n\n\tRTW_INFO(\"set ssid:dot11AuthAlgrthm=%d, dot11PrivacyAlgrthm=%d, dot118021XGrpPrivacy=%d\\n\", psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm,\n\t\tpsecuritypriv->dot118021XGrpPrivacy);\n\ncancel_ps_deny:\n\trtw_ps_deny_cancel(padapter, PS_DENY_JOIN);\n\nexit:\n\tRTW_INFO(\"<=%s, ret %d\\n\", __FUNCTION__, ret);\n\n#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT)\n\trtw_wdev_set_not_indic_disco(pwdev_priv, 0);\n#endif\n\n\treturn ret;\n}\n\nstatic int cfg80211_rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev,\n\t\t\t\t   u16 reason_code)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\n\tRTW_INFO(FUNC_NDEV_FMT\" - Start to Disconnect\\n\", FUNC_NDEV_ARG(ndev));\n\n#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))\n\tif (!wiphy->dev.power.is_prepared)\n\t#endif\n\t\trtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 1);\n#endif\n\n\trtw_set_to_roam(padapter, 0);\n\n\t/* if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)) */\n\t{\n\t\t_rtw_disconnect(wiphy, ndev);\n\t}\n\n#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)\n\trtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 0);\n#endif\n\n\tRTW_INFO(FUNC_NDEV_FMT\" return 0\\n\", FUNC_NDEV_ARG(ndev));\n\treturn 0;\n}\n\nstatic int cfg80211_rtw_set_txpower(struct wiphy *wiphy,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))\n\tstruct wireless_dev *wdev,\n#endif\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) || defined(COMPAT_KERNEL_RELEASE)\n\tenum nl80211_tx_power_setting type, int mbm)\n#else\n\tenum tx_power_setting type, int dbm)\n#endif\n{\n#if 0\n\tstruct iwm_priv *iwm = wiphy_to_iwm(wiphy);\n\tint ret;\n\n\tswitch (type) {\n\tcase NL80211_TX_POWER_AUTOMATIC:\n\t\treturn 0;\n\tcase NL80211_TX_POWER_FIXED:\n\t\tif (mbm < 0 || (mbm % 100))\n\t\t\treturn -EOPNOTSUPP;\n\n\t\tif (!test_bit(IWM_STATUS_READY, &iwm->status))\n\t\t\treturn 0;\n\n\t\tret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX,\n\t\t\t\t\t      CFG_TX_PWR_LIMIT_USR,\n\t\t\t\t\t      MBM_TO_DBM(mbm) * 2);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\n\t\treturn iwm_tx_power_trigger(iwm);\n\tdefault:\n\t\tIWM_ERR(iwm, \"Unsupported power type: %d\\n\", type);\n\t\treturn -EOPNOTSUPP;\n\t}\n#endif\n\tRTW_INFO(\"%s\\n\", __func__);\n\treturn 0;\n}\n\nstatic int cfg80211_rtw_get_txpower(struct wiphy *wiphy,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))\n\tstruct wireless_dev *wdev,\n#endif\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 14, 0))\n\tunsigned int link_id,\n#endif\n\tint *dbm)\n{\n\tRTW_INFO(\"%s\\n\", __func__);\n\n\t*dbm = (12);\n\n\treturn 0;\n}\n\ninline bool rtw_cfg80211_pwr_mgmt(_adapter *adapter)\n{\n\tstruct rtw_wdev_priv *rtw_wdev_priv = adapter_wdev_data(adapter);\n\treturn rtw_wdev_priv->power_mgmt;\n}\n\nstatic int cfg80211_rtw_set_power_mgmt(struct wiphy *wiphy,\n\t\t\t\t       struct net_device *ndev,\n\t\t\t\t       bool enabled, int timeout)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct rtw_wdev_priv *rtw_wdev_priv = adapter_wdev_data(padapter);\n\n\tRTW_INFO(FUNC_NDEV_FMT\" enabled:%u, timeout:%d\\n\", FUNC_NDEV_ARG(ndev),\n\t\tenabled, timeout);\n\n\trtw_wdev_priv->power_mgmt = enabled;\n\n#ifdef CONFIG_LPS\n\tif (!enabled)\n\t\trtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE_CFG80211_PWRMGMT, 0);\n#endif\n\n\treturn 0;\n}\n\nstatic void _rtw_set_pmksa(struct net_device *ndev,\n\tu8 *bssid, u8 *pmkid)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tu8 index, blInserted = _FALSE;\n\n\t/* overwrite PMKID */\n\tfor (index = 0 ; index < NUM_PMKID_CACHE; index++) {\n\t\tif (_rtw_memcmp(psecuritypriv->PMKIDList[index].Bssid, bssid, ETH_ALEN) == _TRUE) {\n\t\t\t/* BSSID is matched, the same AP => rewrite with new PMKID. */\n\t\t\tRTW_INFO(\"BSSID(\"MAC_FMT\") exists in the PMKList.\\n\", MAC_ARG(bssid));\n\n\t\t\t_rtw_memcpy(psecuritypriv->PMKIDList[index].PMKID, pmkid, WLAN_PMKID_LEN);\n\t\t\tpsecuritypriv->PMKIDList[index].bUsed = _TRUE;\n\t\t\tpsecuritypriv->PMKIDIndex = index + 1;\n\t\t\tblInserted = _TRUE;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!blInserted) {\n\t\t/* Find a new entry */\n\t\tRTW_INFO(\"Use the new entry index = %d for this PMKID.\\n\",\n\t\t\tpsecuritypriv->PMKIDIndex);\n\n\t\t_rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, bssid, ETH_ALEN);\n\t\t_rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, pmkid, WLAN_PMKID_LEN);\n\n\t\tpsecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].bUsed = _TRUE;\n\t\tpsecuritypriv->PMKIDIndex++ ;\n\t\tif (psecuritypriv->PMKIDIndex == 16)\n\t\t\tpsecuritypriv->PMKIDIndex = 0;\n\t}\n}\n\nstatic int cfg80211_rtw_set_pmksa(struct wiphy *wiphy,\n\t\t\t\t  struct net_device *ndev,\n\t\t\t\t  struct cfg80211_pmksa *pmksa)\n{\n\tu8\tindex, blInserted = _FALSE;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct mlme_priv *mlme = &padapter->mlmepriv;\n\tstruct security_priv\t*psecuritypriv = &padapter->securitypriv;\n\tu8\tstrZeroMacAddress[ETH_ALEN] = { 0x00 };\n\tbool sae_auth = rtw_sec_chk_auth_type(padapter, NL80211_AUTHTYPE_SAE);\n\n\tRTW_INFO(FUNC_NDEV_FMT\" \"MAC_FMT\" \"KEY_FMT\"\\n\", FUNC_NDEV_ARG(ndev)\n\t\t, MAC_ARG(pmksa->bssid), KEY_ARG(pmksa->pmkid));\n\n\tif (_rtw_memcmp((u8 *)pmksa->bssid, strZeroMacAddress, ETH_ALEN) == _TRUE)\n\t\treturn -EINVAL;\n\n\tif (check_fwstate(mlme, _FW_LINKED) == _FALSE && !sae_auth) {\n\t\tRTW_INFO(FUNC_NDEV_FMT\" not set pmksa cause not in linked state\\n\", FUNC_NDEV_ARG(ndev));\n\t\treturn -EINVAL;\n\t}\n\n\t_rtw_set_pmksa(ndev, (u8 *)pmksa->bssid, (u8 *)pmksa->pmkid);\n\n\tif (sae_auth &&\n\t\t(psecuritypriv->extauth_status == WLAN_STATUS_SUCCESS)) {\n\t\tRTW_PRINT(\"SAE: auth success, start assoc\\n\");\n\t\tstart_clnt_assoc(padapter);\n\t}\n\n\treturn 0;\n}\n\nstatic int cfg80211_rtw_del_pmksa(struct wiphy *wiphy,\n\t\t\t\t  struct net_device *ndev,\n\t\t\t\t  struct cfg80211_pmksa *pmksa)\n{\n\tu8\tindex, bMatched = _FALSE;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct security_priv\t*psecuritypriv = &padapter->securitypriv;\n\n\tRTW_INFO(FUNC_NDEV_FMT\" \"MAC_FMT\" \"KEY_FMT\"\\n\", FUNC_NDEV_ARG(ndev)\n\t\t, MAC_ARG(pmksa->bssid), KEY_ARG(pmksa->pmkid));\n\n\tfor (index = 0 ; index < NUM_PMKID_CACHE; index++) {\n\t\tif (_rtw_memcmp(psecuritypriv->PMKIDList[index].Bssid, (u8 *)pmksa->bssid, ETH_ALEN) == _TRUE) {\n\t\t\t/* BSSID is matched, the same AP => Remove this PMKID information and reset it. */\n\t\t\t_rtw_memset(psecuritypriv->PMKIDList[index].Bssid, 0x00, ETH_ALEN);\n\t\t\t_rtw_memset(psecuritypriv->PMKIDList[index].PMKID, 0x00, WLAN_PMKID_LEN);\n\t\t\tpsecuritypriv->PMKIDList[index].bUsed = _FALSE;\n\t\t\tbMatched = _TRUE;\n\t\t\tRTW_INFO(FUNC_NDEV_FMT\" clear id:%hhu\\n\", FUNC_NDEV_ARG(ndev), index);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (_FALSE == bMatched) {\n\t\tRTW_INFO(FUNC_NDEV_FMT\" do not have matched BSSID\\n\"\n\t\t\t, FUNC_NDEV_ARG(ndev));\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic int cfg80211_rtw_flush_pmksa(struct wiphy *wiphy,\n\t\t\t\t    struct net_device *ndev)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct security_priv\t*psecuritypriv = &padapter->securitypriv;\n\n\tRTW_INFO(FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(ndev));\n\n\t_rtw_memset(&psecuritypriv->PMKIDList[0], 0x00, sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);\n\tpsecuritypriv->PMKIDIndex = 0;\n\n\treturn 0;\n}\n\n#ifdef CONFIG_AP_MODE\nvoid rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len)\n{\n#if !defined(RTW_USE_CFG80211_STA_EVENT) && !defined(COMPAT_KERNEL_RELEASE)\n\ts32 freq;\n\tint channel;\n\tstruct wireless_dev *pwdev = padapter->rtw_wdev;\n\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n#endif\n\tstruct net_device *ndev = padapter->pnetdev;\n\n\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n\n#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE)\n\t{\n\t\tstruct station_info sinfo;\n\t\tu8 ie_offset;\n\t\tif (get_frame_sub_type(pmgmt_frame) == WIFI_ASSOCREQ)\n\t\t\tie_offset = _ASOCREQ_IE_OFFSET_;\n\t\telse /* WIFI_REASSOCREQ */\n\t\t\tie_offset = _REASOCREQ_IE_OFFSET_;\n\n\t\tmemset(&sinfo, 0, sizeof(sinfo));\n\t\tsinfo.filled = STATION_INFO_ASSOC_REQ_IES;\n\t\tsinfo.assoc_req_ies = pmgmt_frame + WLAN_HDR_A3_LEN + ie_offset;\n\t\tsinfo.assoc_req_ies_len = frame_len - WLAN_HDR_A3_LEN - ie_offset;\n\t\tcfg80211_new_sta(ndev, get_addr2_ptr(pmgmt_frame), &sinfo, GFP_ATOMIC);\n\t}\n#else /* defined(RTW_USE_CFG80211_STA_EVENT) */\n\tchannel = pmlmeext->cur_channel;\n\tfreq = rtw_ch2freq(channel);\n\n\t#ifdef COMPAT_KERNEL_RELEASE\n\trtw_cfg80211_rx_mgmt(pwdev, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC);\n\t#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)\n\trtw_cfg80211_rx_mgmt(pwdev, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC);\n\t#else /* COMPAT_KERNEL_RELEASE */\n\t{\n\t\t/* to avoid WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION)  when calling cfg80211_send_rx_assoc() */\n\t\t#ifndef CONFIG_PLATFORM_MSTAR\n\t\tpwdev->iftype = NL80211_IFTYPE_STATION;\n\t\t#endif /* CONFIG_PLATFORM_MSTAR */\n\t\tRTW_INFO(\"iftype=%d before call cfg80211_send_rx_assoc()\\n\", pwdev->iftype);\n\t\trtw_cfg80211_send_rx_assoc(padapter, NULL, pmgmt_frame, frame_len);\n\t\tRTW_INFO(\"iftype=%d after call cfg80211_send_rx_assoc()\\n\", pwdev->iftype);\n\t\tpwdev->iftype = NL80211_IFTYPE_AP;\n\t\t/* cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); */\n\t}\n\t#endif /* COMPAT_KERNEL_RELEASE */\n#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */\n\n}\n\nvoid rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, const u8 *da, unsigned short reason)\n{\n#if !defined(RTW_USE_CFG80211_STA_EVENT) && !defined(COMPAT_KERNEL_RELEASE)\n\ts32 freq;\n\tint channel;\n\tu8 *pmgmt_frame;\n\tuint frame_len;\n\tstruct rtw_ieee80211_hdr *pwlanhdr;\n\tunsigned short *fctrl;\n\tu8 mgmt_buf[128] = {0};\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct wireless_dev *wdev = padapter->rtw_wdev;\n#endif\n\tstruct net_device *ndev = padapter->pnetdev;\n\n\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n\n#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE)\n\tcfg80211_del_sta(ndev, da, GFP_ATOMIC);\n#else /* defined(RTW_USE_CFG80211_STA_EVENT) */\n\tchannel = pmlmeext->cur_channel;\n\tfreq = rtw_ch2freq(channel);\n\n\tpmgmt_frame = mgmt_buf;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pmgmt_frame;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, da, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pmgmt_frame, WIFI_DEAUTH);\n\n\tpmgmt_frame += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tframe_len = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\treason = cpu_to_le16(reason);\n\tpmgmt_frame = rtw_set_fixed_ie(pmgmt_frame, _RSON_CODE_ , (unsigned char *)&reason, &frame_len);\n\n\t#ifdef COMPAT_KERNEL_RELEASE\n\trtw_cfg80211_rx_mgmt(wdev, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC);\n\t#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)\n\trtw_cfg80211_rx_mgmt(wdev, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC);\n\t#else /* COMPAT_KERNEL_RELEASE */\n\tcfg80211_send_disassoc(padapter->pnetdev, mgmt_buf, frame_len);\n\t/* cfg80211_rx_action(padapter->pnetdev, freq, mgmt_buf, frame_len, GFP_ATOMIC); */\n\t#endif /* COMPAT_KERNEL_RELEASE */\n#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */\n}\n\nstatic int rtw_cfg80211_monitor_if_open(struct net_device *ndev)\n{\n\tint ret = 0;\n\n\tRTW_INFO(\"%s\\n\", __func__);\n\n\treturn ret;\n}\n\nstatic int rtw_cfg80211_monitor_if_close(struct net_device *ndev)\n{\n\tint ret = 0;\n\n\tRTW_INFO(\"%s\\n\", __func__);\n\n\treturn ret;\n}\n\nstatic int rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struct net_device *ndev)\n{\n\tint ret = 0;\n\tint rtap_len;\n\tint qos_len = 0;\n\tint dot11_hdr_len = 24;\n\tint snap_len = 6;\n\tunsigned char *pdata;\n\tu16 frame_ctl;\n\tunsigned char src_mac_addr[ETH_ALEN];\n\tunsigned char dst_mac_addr[ETH_ALEN];\n\tstruct rtw_ieee80211_hdr *dot11_hdr;\n\tstruct ieee80211_radiotap_header *rtap_hdr;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n#ifdef CONFIG_DFS_MASTER\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n#endif\n\n\tRTW_INFO(FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(ndev));\n\n\tif (skb)\n\t\trtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize);\n\n\tif (IS_CH_WAITING(rfctl)) {\n\t\t#ifdef CONFIG_DFS_MASTER\n\t\tif (rtw_rfctl_overlap_radar_detect_ch(rfctl))\n\t\t\tgoto fail;\n\t\t#endif\n\t}\n\n\tif (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header)))\n\t\tgoto fail;\n\n\trtap_hdr = (struct ieee80211_radiotap_header *)skb->data;\n\tif (unlikely(rtap_hdr->it_version))\n\t\tgoto fail;\n\n\trtap_len = ieee80211_get_radiotap_len(skb->data);\n\tif (unlikely(skb->len < rtap_len))\n\t\tgoto fail;\n\n\tif (rtap_len != 14) {\n\t\tRTW_INFO(\"radiotap len (should be 14): %d\\n\", rtap_len);\n\t\tgoto fail;\n\t}\n\n\t/* Skip the ratio tap header */\n\tskb_pull(skb, rtap_len);\n\n\tdot11_hdr = (struct rtw_ieee80211_hdr *)skb->data;\n\tframe_ctl = le16_to_cpu(dot11_hdr->frame_ctl);\n\t/* Check if the QoS bit is set */\n\tif ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) {\n\t\t/* Check if this ia a Wireless Distribution System (WDS) frame\n\t\t * which has 4 MAC addresses\n\t\t */\n\t\tif (dot11_hdr->frame_ctl & 0x0080)\n\t\t\tqos_len = 2;\n\t\tif ((dot11_hdr->frame_ctl & 0x0300) == 0x0300)\n\t\t\tdot11_hdr_len += 6;\n\n\t\tmemcpy(dst_mac_addr, dot11_hdr->addr1, sizeof(dst_mac_addr));\n\t\tmemcpy(src_mac_addr, dot11_hdr->addr2, sizeof(src_mac_addr));\n\n\t\t/* Skip the 802.11 header, QoS (if any) and SNAP, but leave spaces for\n\t\t * for two MAC addresses\n\t\t */\n\t\tskb_pull(skb, dot11_hdr_len + qos_len + snap_len - sizeof(src_mac_addr) * 2);\n\t\tpdata = (unsigned char *)skb->data;\n\t\tmemcpy(pdata, dst_mac_addr, sizeof(dst_mac_addr));\n\t\tmemcpy(pdata + sizeof(dst_mac_addr), src_mac_addr, sizeof(src_mac_addr));\n\n\t\tRTW_INFO(\"should be eapol packet\\n\");\n\n\t\t/* Use the real net device to transmit the packet */\n\t\tret = _rtw_xmit_entry(skb, padapter->pnetdev);\n\n\t\treturn ret;\n\n\t} else if ((frame_ctl & (RTW_IEEE80211_FCTL_FTYPE | RTW_IEEE80211_FCTL_STYPE))\n\t\t== (RTW_IEEE80211_FTYPE_MGMT | RTW_IEEE80211_STYPE_ACTION)\n\t) {\n\t\t/* only for action frames */\n\t\tstruct xmit_frame\t\t*pmgntframe;\n\t\tstruct pkt_attrib\t*pattrib;\n\t\tunsigned char\t*pframe;\n\t\t/* u8 category, action, OUI_Subtype, dialogToken=0; */\n\t\t/* unsigned char\t*frame_body; */\n\t\tstruct rtw_ieee80211_hdr *pwlanhdr;\n\t\tstruct xmit_priv\t*pxmitpriv = &(padapter->xmitpriv);\n\t\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\t\tu8 *buf = skb->data;\n\t\tu32 len = skb->len;\n\t\tu8 category, action;\n\t\tint type = -1;\n\n\t\tif (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) {\n\t\t\tRTW_INFO(FUNC_NDEV_FMT\" frame_control:0x%x\\n\", FUNC_NDEV_ARG(ndev),\n\t\t\t\tle16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl));\n\t\t\tgoto fail;\n\t\t}\n\n\t\tRTW_INFO(\"RTW_Tx:da=\"MAC_FMT\" via \"FUNC_NDEV_FMT\"\\n\",\n\t\t\tMAC_ARG(GetAddr1Ptr(buf)), FUNC_NDEV_ARG(ndev));\n\t\t#ifdef CONFIG_P2P\n\t\ttype = rtw_p2p_check_frames(padapter, buf, len, _TRUE);\n\t\tif (type >= 0)\n\t\t\tgoto dump;\n\t\t#endif\n\t\tif (category == RTW_WLAN_CATEGORY_PUBLIC)\n\t\t\tRTW_INFO(\"RTW_Tx:%s\\n\", action_public_str(action));\n\t\telse\n\t\t\tRTW_INFO(\"RTW_Tx:category(%u), action(%u)\\n\", category, action);\n#ifdef CONFIG_P2P\ndump:\n#endif\n\t\t/* starting alloc mgmt frame to dump it */\n\t\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\t\tif (pmgntframe == NULL)\n\t\t\tgoto fail;\n\n\t\t/* update attribute */\n\t\tpattrib = &pmgntframe->attrib;\n\t\tupdate_mgntframe_attrib(padapter, pattrib);\n\t\tpattrib->retry_ctrl = _FALSE;\n\n\t\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\t\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\n\t\t_rtw_memcpy(pframe, (void *)buf, len);\n\t\tpattrib->pktlen = len;\n\n#ifdef CONFIG_P2P\n\t\tif (type >= 0)\n\t\t\trtw_xframe_chk_wfd_ie(pmgntframe);\n#endif /* CONFIG_P2P */\n\n\t\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\t\t/* update seq number */\n\t\tpmlmeext->mgnt_seq = GetSequence(pwlanhdr);\n\t\tpattrib->seqnum = pmlmeext->mgnt_seq;\n\t\tpmlmeext->mgnt_seq++;\n\n\n\t\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\t\tdump_mgntframe(padapter, pmgntframe);\n\n\t} else\n\t\tRTW_INFO(\"frame_ctl=0x%x\\n\", frame_ctl & (RTW_IEEE80211_FCTL_FTYPE | RTW_IEEE80211_FCTL_STYPE));\n\n\nfail:\n\n\trtw_skb_free(skb);\n\n\treturn 0;\n\n}\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0))\nstatic void rtw_cfg80211_monitor_if_set_multicast_list(struct net_device *ndev)\n{\n\tRTW_INFO(\"%s\\n\", __func__);\n}\n#endif\nstatic int rtw_cfg80211_monitor_if_set_mac_address(struct net_device *ndev, void *addr)\n{\n\tint ret = 0;\n\n\tRTW_INFO(\"%s\\n\", __func__);\n\n\treturn ret;\n}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))\nstatic const struct net_device_ops rtw_cfg80211_monitor_if_ops = {\n\t.ndo_open = rtw_cfg80211_monitor_if_open,\n\t.ndo_stop = rtw_cfg80211_monitor_if_close,\n\t.ndo_start_xmit = rtw_cfg80211_monitor_if_xmit_entry,\n\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0))\n\t.ndo_set_multicast_list = rtw_cfg80211_monitor_if_set_multicast_list,\n\t#endif\n\t.ndo_set_mac_address = rtw_cfg80211_monitor_if_set_mac_address,\n};\n#endif\n\nstatic int rtw_cfg80211_add_monitor_if(_adapter *padapter, char *name, struct net_device **ndev)\n{\n\tint ret = 0;\n\tstruct net_device *mon_ndev = NULL;\n\tstruct wireless_dev *mon_wdev = NULL;\n\tstruct rtw_netdev_priv_indicator *pnpi;\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n\n\tif (!name) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" without specific name\\n\", FUNC_ADPT_ARG(padapter));\n\t\tret = -EINVAL;\n\t\tgoto out;\n\t}\n\n\tif (pwdev_priv->pmon_ndev) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" monitor interface exist: \"NDEV_FMT\"\\n\",\n\t\t\tFUNC_ADPT_ARG(padapter), NDEV_ARG(pwdev_priv->pmon_ndev));\n\t\tret = -EBUSY;\n\t\tgoto out;\n\t}\n\n\tmon_ndev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator));\n\tif (!mon_ndev) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" allocate ndev fail\\n\", FUNC_ADPT_ARG(padapter));\n\t\tret = -ENOMEM;\n\t\tgoto out;\n\t}\n\n\tmon_ndev->type = ARPHRD_IEEE80211_RADIOTAP;\n\tstrncpy(mon_ndev->name, name, IFNAMSIZ);\n\tmon_ndev->name[IFNAMSIZ - 1] = 0;\n#if (LINUX_VERSION_CODE > KERNEL_VERSION(4, 11, 8))\n\tmon_ndev->priv_destructor = rtw_ndev_destructor;\n#else\n\tmon_ndev->destructor = rtw_ndev_destructor;\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))\n\tmon_ndev->netdev_ops = &rtw_cfg80211_monitor_if_ops;\n#else\n\tmon_ndev->open = rtw_cfg80211_monitor_if_open;\n\tmon_ndev->stop = rtw_cfg80211_monitor_if_close;\n\tmon_ndev->hard_start_xmit = rtw_cfg80211_monitor_if_xmit_entry;\n\tmon_ndev->set_mac_address = rtw_cfg80211_monitor_if_set_mac_address;\n#endif\n\n\tpnpi = netdev_priv(mon_ndev);\n\tpnpi->priv = padapter;\n\tpnpi->sizeof_priv = sizeof(_adapter);\n\n\t/*  wdev */\n\tmon_wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev));\n\tif (!mon_wdev) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" allocate mon_wdev fail\\n\", FUNC_ADPT_ARG(padapter));\n\t\tret = -ENOMEM;\n\t\tgoto out;\n\t}\n\n\tmon_wdev->wiphy = padapter->rtw_wdev->wiphy;\n\tmon_wdev->netdev = mon_ndev;\n\tmon_wdev->iftype = NL80211_IFTYPE_MONITOR;\n\tmon_ndev->ieee80211_ptr = mon_wdev;\n\n\tret = register_netdevice(mon_ndev);\n\tif (ret)\n\t\tgoto out;\n\n\t*ndev = pwdev_priv->pmon_ndev = mon_ndev;\n\t_rtw_memcpy(pwdev_priv->ifname_mon, name, IFNAMSIZ + 1);\n\nout:\n\tif (ret && mon_wdev) {\n\t\trtw_mfree((u8 *)mon_wdev, sizeof(struct wireless_dev));\n\t\tmon_wdev = NULL;\n\t}\n\n\tif (ret && mon_ndev) {\n\t\tfree_netdev(mon_ndev);\n\t\t*ndev = mon_ndev = NULL;\n\t}\n\n\treturn ret;\n}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\nstatic struct wireless_dev *\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)\nstatic struct net_device *\n#else\nstatic int\n#endif\n\tcfg80211_rtw_add_virtual_intf(\n\t\tstruct wiphy *wiphy,\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))\n\t\tconst char *name,\n\t\t#else\n\t\tchar *name,\n\t\t#endif\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))\n\t\tunsigned char name_assign_type,\n\t\t#endif\n\t\tenum nl80211_iftype type,\n\t\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))\n\t\tu32 *flags,\n\t\t#endif\n\t\tstruct vif_params *params)\n{\n\tint ret = 0;\n\tstruct wireless_dev *wdev = NULL;\n\tstruct net_device *ndev = NULL;\n\t_adapter *padapter;\n\tstruct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);\n\n\trtw_set_rtnl_lock_holder(dvobj, current);\n\n\tRTW_INFO(FUNC_WIPHY_FMT\" name:%s, type:%d\\n\", FUNC_WIPHY_ARG(wiphy), name, type);\n\n\tswitch (type) {\n\tcase NL80211_IFTYPE_MONITOR:\n\t\tpadapter = wiphy_to_adapter(wiphy); /* TODO: get ap iface ? */\n\t\tret = rtw_cfg80211_add_monitor_if(padapter, (char *)name, &ndev);\n\t\tif (ret == 0)\n\t\t\twdev = ndev->ieee80211_ptr;\n\t\tbreak;\n\n#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))\n\tcase NL80211_IFTYPE_P2P_CLIENT:\n\tcase NL80211_IFTYPE_P2P_GO:\n#endif\n\tcase NL80211_IFTYPE_STATION:\n\tcase NL80211_IFTYPE_AP:\n#ifdef CONFIG_RTW_MESH\n\tcase NL80211_IFTYPE_MESH_POINT:\n#endif\n\t\tpadapter = dvobj_get_unregisterd_adapter(dvobj);\n\t\tif (!padapter) {\n\t\t\tRTW_WARN(\"adapter pool empty!\\n\");\n\t\t\tret = -ENODEV;\n\t\t\tbreak;\n\t\t}\n\t\tif (rtw_os_ndev_init(padapter, name) != _SUCCESS) {\n\t\t\tRTW_WARN(\"ndev init fail!\\n\");\n\t\t\tret = -ENODEV;\n\t\t\tbreak;\n\t\t}\n\t\t#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))\n\t\tif (type == NL80211_IFTYPE_P2P_CLIENT || type == NL80211_IFTYPE_P2P_GO)\n\t\t\trtw_p2p_enable(padapter, P2P_ROLE_DEVICE);\n\t\t#endif\n\t\tndev = padapter->pnetdev;\n\t\twdev = ndev->ieee80211_ptr;\n\t\tbreak;\n\n#if defined(CONFIG_P2P) && defined(RTW_DEDICATED_P2P_DEVICE)\n\tcase NL80211_IFTYPE_P2P_DEVICE:\n\t\tret = rtw_pd_iface_alloc(wiphy, name, &wdev);\n\t\tbreak;\n#endif\n\n\tcase NL80211_IFTYPE_ADHOC:\n\tcase NL80211_IFTYPE_AP_VLAN:\n\tcase NL80211_IFTYPE_WDS:\n\tdefault:\n\t\tret = -ENODEV;\n\t\tRTW_INFO(\"Unsupported interface type\\n\");\n\t\tbreak;\n\t}\n\n\tif (ndev)\n\t\tRTW_INFO(FUNC_WIPHY_FMT\" ndev:%p, ret:%d\\n\", FUNC_WIPHY_ARG(wiphy), ndev, ret);\n\telse\n\t\tRTW_INFO(FUNC_WIPHY_FMT\" wdev:%p, ret:%d\\n\", FUNC_WIPHY_ARG(wiphy), wdev, ret);\n\n\trtw_set_rtnl_lock_holder(dvobj, NULL);\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\treturn wdev ? wdev : ERR_PTR(ret);\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)\n\treturn ndev ? ndev : ERR_PTR(ret);\n#else\n\treturn ret;\n#endif\n}\n\nstatic int cfg80211_rtw_del_virtual_intf(struct wiphy *wiphy,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\tstruct wireless_dev *wdev\n#else\n\tstruct net_device *ndev\n#endif\n)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\tstruct net_device *ndev = wdev_to_ndev(wdev);\n#endif\n\tint ret = 0;\n\tstruct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);\n\t_adapter *adapter;\n\tstruct rtw_wdev_priv *pwdev_priv;\n\n\trtw_set_rtnl_lock_holder(dvobj, current);\n\n\tif (ndev) {\n\t\tadapter = (_adapter *)rtw_netdev_priv(ndev);\n\t\tpwdev_priv = adapter_wdev_data(adapter);\n\n\t\tif (ndev == pwdev_priv->pmon_ndev) {\n\t\t\tunregister_netdevice(ndev);\n\t\t\tpwdev_priv->pmon_ndev = NULL;\n\t\t\tpwdev_priv->ifname_mon[0] = '\\0';\n\t\t\tRTW_INFO(FUNC_NDEV_FMT\" remove monitor ndev\\n\", FUNC_NDEV_ARG(ndev));\n\t\t} else {\n\t\t\tRTW_INFO(FUNC_NDEV_FMT\" unregister ndev\\n\", FUNC_NDEV_ARG(ndev));\n\t\t\trtw_os_ndev_unregister(adapter);\n\t\t}\n\t} else\n#if defined(CONFIG_P2P) && defined(RTW_DEDICATED_P2P_DEVICE)\n\tif (wdev->iftype == NL80211_IFTYPE_P2P_DEVICE) {\n\t\tif (wdev == wiphy_to_pd_wdev(wiphy))\n\t\t\trtw_pd_iface_free(wiphy);\n\t\telse {\n\t\t\tRTW_ERR(FUNC_WIPHY_FMT\" unknown P2P Device wdev:%p\\n\", FUNC_WIPHY_ARG(wiphy), wdev);\n\t\t\trtw_warn_on(1);\n\t\t}\n\t} else\n#endif\n\t{\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\nexit:\n\trtw_set_rtnl_lock_holder(dvobj, NULL);\n\treturn ret;\n}\n\nstatic int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, const u8 *tail, size_t tail_len)\n{\n\tint ret = 0;\n\tu8 *pbuf = NULL;\n\tuint len, wps_ielen = 0;\n\tuint p2p_ielen = 0;\n\tu8 got_p2p_ie = _FALSE;\n\tstruct mlme_priv *pmlmepriv = &(adapter->mlmepriv);\n\t/* struct sta_priv *pstapriv = &padapter->stapriv; */\n\n\n\tRTW_INFO(\"%s beacon_head_len=%zu, beacon_tail_len=%zu\\n\", __FUNCTION__, head_len, tail_len);\n\n\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)\n\t\treturn -EINVAL;\n\n\tif (head_len < 24)\n\t\treturn -EINVAL;\n\n\t#ifdef CONFIG_FW_HANDLE_TXBCN\n\tif (!rtw_ap_nums_check(adapter)) {\n\t\tRTW_ERR(FUNC_ADPT_FMT\"failed, con't support over %d BCN\\n\", FUNC_ADPT_ARG(adapter), CONFIG_LIMITED_AP_NUM);\n\t\treturn -EINVAL;\n\t}\n\t#endif /*CONFIG_FW_HANDLE_TXBCN*/\n\n\tpbuf = rtw_zmalloc(head_len + tail_len);\n\tif (!pbuf)\n\t\treturn -ENOMEM;\n\n\n\t/* _rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2); */\n\n\t/* if((pstapriv->max_num_sta>NUM_STA) || (pstapriv->max_num_sta<=0)) */\n\t/*\tpstapriv->max_num_sta = NUM_STA; */\n\n\n\t_rtw_memcpy(pbuf, (void *)head + 24, head_len - 24); /* 24=beacon header len. */\n\t_rtw_memcpy(pbuf + head_len - 24, (void *)tail, tail_len);\n\n\tlen = head_len + tail_len - 24;\n\n\t/* check wps ie if inclued */\n\tif (rtw_get_wps_ie(pbuf + _FIXED_IE_LENGTH_, len - _FIXED_IE_LENGTH_, NULL, &wps_ielen))\n\t\tRTW_INFO(\"add bcn, wps_ielen=%d\\n\", wps_ielen);\n\n#ifdef CONFIG_P2P\n\tif (adapter->wdinfo.driver_interface == DRIVER_CFG80211) {\n\t\t/* check p2p if enable */\n\t\tif (rtw_get_p2p_ie(pbuf + _FIXED_IE_LENGTH_, len - _FIXED_IE_LENGTH_, NULL, &p2p_ielen)) {\n\t\t\tstruct wifidirect_info *pwdinfo = &(adapter->wdinfo);\n\n\t\t\tRTW_INFO(\"got p2p_ie, len=%d\\n\", p2p_ielen);\n\n\t\t\tgot_p2p_ie = _TRUE;\n\n\t\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {\n\t\t\t\tRTW_INFO(\"Enable P2P function for the first time\\n\");\n\t\t\t\trtw_p2p_enable(adapter, P2P_ROLE_GO);\n\n\t\t\t\tadapter->stapriv.expire_to = 3; /* 3x2 = 6 sec in p2p mode */\n\t\t\t} else {\n\t\t\t\tRTW_INFO(\"enter GO Mode, p2p_ielen=%d\\n\", p2p_ielen);\n\n\t\t\t\trtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);\n\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);\n\t\t\t\tpwdinfo->intent = 15;\n\t\t\t}\n\t\t}\n\t}\n#endif /* CONFIG_P2P */\n\n\t/* pbss_network->IEs will not include p2p_ie, wfd ie */\n\trtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, P2P_OUI, 4);\n\trtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, WFD_OUI, 4);\n\n\tif (rtw_check_beacon_data(adapter, pbuf,  len) == _SUCCESS) {\n#ifdef CONFIG_P2P\n\t\t/* check p2p if enable */\n\t\tif (got_p2p_ie == _TRUE) {\n\t\t\tstruct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;\n\t\t\tstruct wifidirect_info *pwdinfo = &(adapter->wdinfo);\n\t\t\tpwdinfo->operating_channel = pmlmeext->cur_channel;\n\t\t}\n#endif /* CONFIG_P2P */\n\t\tret = 0;\n\t} else\n\t\tret = -EINVAL;\n\n\n\trtw_mfree(pbuf, head_len + tail_len);\n\n\treturn ret;\n}\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE)\nstatic int cfg80211_rtw_add_beacon(struct wiphy *wiphy, struct net_device *ndev,\n\t\tstruct beacon_parameters *info)\n{\n\tint ret = 0;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);\n\n\tRTW_INFO(FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(ndev));\n\n\tif (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) {\n\t\tret = -ENOTSUPP;\n\t\tgoto exit;\n\t}\n\trtw_mi_scan_abort(adapter, _TRUE);\n\trtw_mi_buddy_set_scan_deny(adapter, 300);\n\tret = rtw_add_beacon(adapter, info->head, info->head_len, info->tail, info->tail_len);\n\nexit:\n\treturn ret;\n}\n\nstatic int cfg80211_rtw_set_beacon(struct wiphy *wiphy, struct net_device *ndev,\n\t\tstruct beacon_parameters *info)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);\n\n\tRTW_INFO(FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(ndev));\n\n\tpmlmeext->bstart_bss = _TRUE;\n\n\tcfg80211_rtw_add_beacon(wiphy, ndev, info);\n\n\treturn 0;\n}\n\nstatic int\tcfg80211_rtw_del_beacon(struct wiphy *wiphy, struct net_device *ndev)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);\n\n\tRTW_INFO(FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(ndev));\n\n\trtw_set_802_11_infrastructure_mode(adapter, Ndis802_11Infrastructure);\n\trtw_setopmode_cmd(adapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK);\n\n\treturn 0;\n}\n#else\nstatic int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev,\n\t\tstruct cfg80211_ap_settings *settings)\n{\n\tint ret = 0;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);\n\n\tRTW_INFO(FUNC_NDEV_FMT\" hidden_ssid:%d, auth_type:%d\\n\", FUNC_NDEV_ARG(ndev),\n\t\tsettings->hidden_ssid, settings->auth_type);\n\n\tif (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) {\n\t\tret = -ENOTSUPP;\n\t\tgoto exit;\n\t}\n\n\t/*\n\tKernel < v5.1, the auth_type set as NL80211_AUTHTYPE_AUTOMATIC.\n\tif the AKM SAE in the RSN IE, we have to update the auth_type for SAE\n\tin rtw_check_beacon_data().\n\t*/\n\trtw_cfg80211_set_auth_type(&adapter->securitypriv, settings->auth_type);\n\n\trtw_mi_scan_abort(adapter, _TRUE);\n\trtw_mi_buddy_set_scan_deny(adapter, 300);\n\tret = rtw_add_beacon(adapter, settings->beacon.head, settings->beacon.head_len,\n\t\tsettings->beacon.tail, settings->beacon.tail_len);\n\n\tadapter->mlmeextpriv.mlmext_info.hidden_ssid_mode = settings->hidden_ssid;\n\n\tif (settings->ssid && settings->ssid_len) {\n\t\tWLAN_BSSID_EX *pbss_network = &adapter->mlmepriv.cur_network.network;\n\t\tWLAN_BSSID_EX *pbss_network_ext = &adapter->mlmeextpriv.mlmext_info.network;\n\n\t\tif (0)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" ssid:(%s,%zu), from ie:(%s,%d)\\n\", FUNC_ADPT_ARG(adapter),\n\t\t\t\tsettings->ssid, settings->ssid_len,\n\t\t\t\tpbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength);\n\n\t\t_rtw_memcpy(pbss_network->Ssid.Ssid, (void *)settings->ssid, settings->ssid_len);\n\t\tpbss_network->Ssid.SsidLength = settings->ssid_len;\n\t\t_rtw_memcpy(pbss_network_ext->Ssid.Ssid, (void *)settings->ssid, settings->ssid_len);\n\t\tpbss_network_ext->Ssid.SsidLength = settings->ssid_len;\n\n\t\tif (0)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" after ssid:(%s,%d), (%s,%d)\\n\", FUNC_ADPT_ARG(adapter),\n\t\t\t\tpbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength,\n\t\t\t\tpbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength);\n\t}\n\nexit:\n\treturn ret;\n}\n\nstatic int cfg80211_rtw_change_beacon(struct wiphy *wiphy, struct net_device *ndev,\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 7, 0))\n\t\tstruct cfg80211_beacon_data *info)\n#else\n\t\tstruct cfg80211_ap_update *info)\n#endif\n{\n\tint ret = 0;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);\n\n\tRTW_INFO(FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(ndev));\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 7, 0))\n\tret = rtw_add_beacon(adapter, info->head, info->head_len, info->tail, info->tail_len);\n#else\n\tret = rtw_add_beacon(adapter, info->beacon.head, info->beacon.head_len, info->beacon.tail, info->beacon.tail_len);\n#endif\n\n\treturn ret;\n}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0))\nstatic int cfg80211_rtw_stop_ap(struct wiphy *wiphy, struct net_device *ndev, unsigned int link_id)\n#else\nstatic int cfg80211_rtw_stop_ap(struct wiphy *wiphy, struct net_device *ndev)\n#endif\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);\n\n\tRTW_INFO(FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(ndev));\n\n\trtw_set_802_11_infrastructure_mode(adapter, Ndis802_11Infrastructure);\n\trtw_setopmode_cmd(adapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK);\n\n\treturn 0;\n}\n#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) */\n\n#if CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))\nstatic int cfg80211_rtw_set_mac_acl(struct wiphy *wiphy, struct net_device *ndev,\n\t\tconst struct cfg80211_acl_data *params)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);\n\tu8 acl_mode = RTW_ACL_MODE_DISABLED;\n\tint ret = -1;\n\tint i;\n\n\tif (!params) {\n\t\tRTW_WARN(FUNC_ADPT_FMT\" params NULL\\n\", FUNC_ADPT_ARG(adapter));\n\t\trtw_macaddr_acl_clear(adapter, RTW_ACL_PERIOD_BSS);\n\t\tgoto exit;\n\t}\n\n\tRTW_INFO(FUNC_ADPT_FMT\" acl_policy:%d, entry_num:%d\\n\"\n\t\t, FUNC_ADPT_ARG(adapter), params->acl_policy, params->n_acl_entries);\n\n\tif (params->acl_policy == NL80211_ACL_POLICY_ACCEPT_UNLESS_LISTED)\n\t\tacl_mode = RTW_ACL_MODE_ACCEPT_UNLESS_LISTED;\n\telse if (params->acl_policy == NL80211_ACL_POLICY_DENY_UNLESS_LISTED)\n\t\tacl_mode = RTW_ACL_MODE_DENY_UNLESS_LISTED;\n\n\trtw_macaddr_acl_clear(adapter, RTW_ACL_PERIOD_BSS);\n\n\trtw_set_macaddr_acl(adapter, RTW_ACL_PERIOD_BSS, acl_mode);\n\n\tfor (i = 0; i < params->n_acl_entries; i++)\n\t\trtw_acl_add_sta(adapter, RTW_ACL_PERIOD_BSS, params->mac_addrs[i].addr);\n\n\tret = 0;\n\nexit:\n\treturn ret;\n}\n#endif /* CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) */\n\nconst char *_nl80211_sta_flags_str[] = {\n\t\"INVALID\",\n\t\"AUTHORIZED\",\n\t\"SHORT_PREAMBLE\",\n\t\"WME\",\n\t\"MFP\",\n\t\"AUTHENTICATED\",\n\t\"TDLS_PEER\",\n\t\"ASSOCIATED\",\n};\n\n#define nl80211_sta_flags_str(_f) ((_f <= NL80211_STA_FLAG_MAX) ? _nl80211_sta_flags_str[_f] : _nl80211_sta_flags_str[0])\n\nconst char *_nl80211_plink_state_str[] = {\n\t\"LISTEN\",\n\t\"OPN_SNT\",\n\t\"OPN_RCVD\",\n\t\"CNF_RCVD\",\n\t\"ESTAB\",\n\t\"HOLDING\",\n\t\"BLOCKED\",\n\t\"UNKNOWN\",\n};\n\n#define nl80211_plink_state_str(_s) ((_s < NUM_NL80211_PLINK_STATES) ? _nl80211_plink_state_str[_s] : _nl80211_plink_state_str[NUM_NL80211_PLINK_STATES])\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))\n#define NL80211_PLINK_ACTION_NO_ACTION PLINK_ACTION_INVALID\n#define NL80211_PLINK_ACTION_OPEN PLINK_ACTION_OPEN\n#define NL80211_PLINK_ACTION_BLOCK PLINK_ACTION_BLOCK\n#define NUM_NL80211_PLINK_ACTIONS 3\n#endif\n\nconst char *_nl80211_plink_actions_str[] = {\n\t\"NO_ACTION\",\n\t\"OPEN\",\n\t\"BLOCK\",\n\t\"UNKNOWN\",\n};\n\n#define nl80211_plink_actions_str(_a) ((_a < NUM_NL80211_PLINK_ACTIONS) ? _nl80211_plink_actions_str[_a] : _nl80211_plink_actions_str[NUM_NL80211_PLINK_ACTIONS])\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))\nconst char *_nl80211_mesh_power_mode_str[] = {\n\t\"UNKNOWN\",\n\t\"ACTIVE\",\n\t\"LIGHT_SLEEP\",\n\t\"DEEP_SLEEP\",\n};\n\n#define nl80211_mesh_power_mode_str(_p) ((_p <= NL80211_MESH_POWER_MAX) ? _nl80211_mesh_power_mode_str[_p] : _nl80211_mesh_power_mode_str[0])\n#endif\n\nvoid dump_station_parameters(void *sel, struct wiphy *wiphy, const struct station_parameters *params)\n{\n#if DBG_RTW_CFG80211_STA_PARAM\n\tif (params->supported_rates_len) {\n\t\t#define SUPP_RATES_BUF_LEN (3 * RTW_G_RATES_NUM + 1)\n\t\tint i;\n\t\tchar supp_rates_buf[SUPP_RATES_BUF_LEN] = {0};\n\t\tu8 cnt = 0;\n\n\t\trtw_warn_on(params->supported_rates_len > RTW_G_RATES_NUM);\n\n\t\tfor (i = 0; i < params->supported_rates_len; i++) {\n\t\t\tif (i >= RTW_G_RATES_NUM)\n\t\t\t\tbreak;\n\t\t\tcnt += snprintf(supp_rates_buf + cnt, SUPP_RATES_BUF_LEN - cnt -1\n\t\t\t\t, \"%02X \", params->supported_rates[i]);\n\t\t\tif (cnt >= SUPP_RATES_BUF_LEN - 1)\n\t\t\t\tbreak;\n\t\t}\n\n\t\tRTW_PRINT_SEL(sel, \"supported_rates:%s\\n\", supp_rates_buf);\n\t}\n\n\tif (params->vlan)\n\t\tRTW_PRINT_SEL(sel, \"vlan:\"NDEV_FMT\"\\n\", NDEV_ARG(params->vlan));\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))\n\tif (params->sta_flags_mask) {\n\t\t#define STA_FLAGS_BUF_LEN 128\n\t\tint i = 0;\n\t\tchar sta_flags_buf[STA_FLAGS_BUF_LEN] = {0};\n\t\tu8 cnt = 0;\n\n\t\tfor (i = 1; i <= NL80211_STA_FLAG_MAX; i++) {\n\t\t\tif (params->sta_flags_mask & BIT(i)) {\n\t\t\t\tcnt += snprintf(sta_flags_buf + cnt, STA_FLAGS_BUF_LEN - cnt -1, \"%s=%u \"\n\t\t\t\t\t, nl80211_sta_flags_str(i), (params->sta_flags_set & BIT(i)) ? 1 : 0);\n\t\t\t\tif (cnt >= STA_FLAGS_BUF_LEN - 1)\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tRTW_PRINT_SEL(sel, \"sta_flags:%s\\n\", sta_flags_buf);\n\t}\n#else\n\tu32 station_flags;\n\t#error \"TBD\\n\"\n#endif\n\n\tif (params->listen_interval != -1)\n\t\tRTW_PRINT_SEL(sel, \"listen_interval:%d\\n\", params->listen_interval);\n\n\tif (params->aid)\n\t\tRTW_PRINT_SEL(sel, \"aid:%u\\n\", params->aid);\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))\n\tif (params->peer_aid)\n\t\tRTW_PRINT_SEL(sel, \"peer_aid:%u\\n\", params->peer_aid);\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26))\n\tif (params->plink_action != NL80211_PLINK_ACTION_NO_ACTION)\n\t\tRTW_PRINT_SEL(sel, \"plink_action:%s\\n\", nl80211_plink_actions_str(params->plink_action));\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))\n\tif (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE)\n\t#endif\n\t\tRTW_PRINT_SEL(sel, \"plink_state:%s\\n\"\n\t\t\t, nl80211_plink_state_str(params->plink_state));\n#endif\n\n#if 0 /* TODO */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28))\n\tconst struct ieee80211_ht_cap *ht_capa;\n#endif\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))\n\tconst struct ieee80211_vht_cap *vht_capa;\n#endif\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))\n\tif (params->sta_modify_mask & STATION_PARAM_APPLY_UAPSD)\n\t\tRTW_PRINT_SEL(sel, \"uapsd_queues:0x%02x\\n\", params->uapsd_queues);\n\tif (params->max_sp)\n\t\tRTW_PRINT_SEL(sel, \"max_sp:%u\\n\", params->max_sp);\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))\n\tif (params->local_pm != NL80211_MESH_POWER_UNKNOWN) {\n\t\tRTW_PRINT_SEL(sel, \"local_pm:%s\\n\"\n\t\t\t, nl80211_mesh_power_mode_str(params->local_pm));\n\t}\n\n\tif (params->sta_modify_mask & STATION_PARAM_APPLY_CAPABILITY)\n\t\tRTW_PRINT_SEL(sel, \"capability:0x%04x\\n\", params->capability);\n\n#if 0 /* TODO */\n\tconst u8 *ext_capab;\n\tu8 ext_capab_len;\n#endif\n#endif\n\n#if 0 /* TODO */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0))\n\tconst u8 *supported_channels;\n\tu8 supported_channels_len;\n\tconst u8 *supported_oper_classes;\n\tu8 supported_oper_classes_len;\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))\n\tu8 opmode_notif;\n\tbool opmode_notif_used;\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))\n\tint support_p2p_ps;\n#endif\n#endif\n#endif /* DBG_RTW_CFG80211_STA_PARAM */\n}\n\nstatic int\tcfg80211_rtw_add_station(struct wiphy *wiphy, struct net_device *ndev,\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))\n\tu8 *mac,\n#else\n\tconst u8 *mac,\n#endif\n\tstruct station_parameters *params)\n{\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n#if defined(CONFIG_TDLS) || defined(CONFIG_RTW_MESH)\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n#endif\n#ifdef CONFIG_TDLS\n\tstruct sta_info *psta;\n#endif /* CONFIG_TDLS */\n\n\tRTW_INFO(FUNC_NDEV_FMT\" mac:\"MAC_FMT\"\\n\", FUNC_NDEV_ARG(ndev), MAC_ARG(mac));\n\n#if CONFIG_RTW_MACADDR_ACL\n\tif (rtw_access_ctrl(padapter, mac) == _FALSE) {\n\t\tRTW_INFO(FUNC_NDEV_FMT\" deny by macaddr ACL\\n\", FUNC_NDEV_ARG(ndev));\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n#endif\n\n\tdump_station_parameters(RTW_DBGDUMP, wiphy, params);\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(padapter)) {\n\t\tstruct rtw_mesh_cfg *mcfg = &padapter->mesh_cfg;\n\t\tstruct rtw_mesh_info *minfo = &padapter->mesh_info;\n\t\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\t\tstruct mesh_plink_ent *plink = NULL;\n\t\tstruct wlan_network *scanned = NULL;\n\t\tbool acnode = 0;\n\t\tu8 add_new_sta = 0, probe_req = 0;\n\t\t_irqL irqL;\n\n\t\tif (params->plink_state != NL80211_PLINK_LISTEN) {\n\t\t\tRTW_WARN(FUNC_NDEV_FMT\" %s\\n\", FUNC_NDEV_ARG(ndev), nl80211_plink_state_str(params->plink_state));\n\t\t\trtw_warn_on(1);\n\t\t}\n\t\tif (!params->aid || params->aid > pstapriv->max_aid) {\n\t\t\tRTW_WARN(FUNC_NDEV_FMT\" invalid aid:%u\\n\", FUNC_NDEV_ARG(ndev), params->aid);\n\t\t\trtw_warn_on(1);\n\t\t\tret = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t_enter_critical_bh(&(plink_ctl->lock), &irqL);\n\n\t\tplink = _rtw_mesh_plink_get(padapter, mac);\n\t\tif (plink)\n\t\t\tgoto release_plink_ctl;\n\n\t\t#if CONFIG_RTW_MESH_PEER_BLACKLIST\n\t\tif (rtw_mesh_peer_blacklist_search(padapter, mac)) {\n\t\t\tRTW_INFO(FUNC_NDEV_FMT\" deny by peer blacklist\\n\"\n\t\t\t\t, FUNC_NDEV_ARG(ndev));\n\t\t\tret = -EINVAL;\n\t\t\tgoto release_plink_ctl;\n\t\t}\n\t\t#endif\n\n\t\tscanned = rtw_find_network(&padapter->mlmepriv.scanned_queue, mac);\n\t\tif (!scanned\n\t\t\t|| rtw_get_passing_time_ms(scanned->last_scanned) >= mcfg->peer_sel_policy.scanr_exp_ms\n\t\t) {\n\t\t\tif (!scanned)\n\t\t\t\tRTW_INFO(FUNC_NDEV_FMT\" corresponding network not found\\n\", FUNC_NDEV_ARG(ndev));\n\t\t\telse\n\t\t\t\tRTW_INFO(FUNC_NDEV_FMT\" corresponding network too old\\n\", FUNC_NDEV_ARG(ndev));\n\n\t\t\tif (adapter_to_rfctl(padapter)->offch_state == OFFCHS_NONE)\n\t\t\t\tprobe_req = 1;\n\n\t\t\tret = -EINVAL;\n\t\t\tgoto release_plink_ctl;\n\t\t}\n\n\t\t#if CONFIG_RTW_MESH_ACNODE_PREVENT\n\t\tif (plink_ctl->acnode_rsvd)\n\t\t\tacnode = rtw_mesh_scanned_is_acnode_confirmed(padapter, scanned);\n\t\t#endif\n\n\t\t/* wpa_supplicant's auto peer will initiate peering when candidate peer is reported without max_peer_links consideration */\n\t\tif (plink_ctl->num >= mcfg->max_peer_links + acnode ? 1 : 0) {\n\t\t\tRTW_INFO(FUNC_NDEV_FMT\" exceed max_peer_links:%u%s\\n\"\n\t\t\t\t, FUNC_NDEV_ARG(ndev), mcfg->max_peer_links, acnode ? \" acn\" : \"\");\n\t\t\tret = -EINVAL;\n\t\t\tgoto release_plink_ctl;\n\t\t}\n\n\t\tif (!rtw_bss_is_candidate_mesh_peer(&padapter->mlmepriv.cur_network.network, &scanned->network, 1, 1)) {\n\t\t\tRTW_WARN(FUNC_NDEV_FMT\" corresponding network is not candidate with same ch\\n\"\n\t\t\t\t, FUNC_NDEV_ARG(ndev));\n\t\t\tret = -EINVAL;\n\t\t\tgoto release_plink_ctl;\n\t\t}\n\n\t\t#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\t\tif (!rtw_mesh_cto_mgate_network_filter(padapter, scanned)) {\n\t\t\tRTW_INFO(FUNC_NDEV_FMT\" peer filtered out by cto_mgate check\\n\"\n\t\t\t\t, FUNC_NDEV_ARG(ndev));\n\t\t\tret = -EINVAL;\n\t\t\tgoto release_plink_ctl;\n\t\t}\n\t\t#endif\n\n\t\tif (_rtw_mesh_plink_add(padapter, mac) == _SUCCESS) {\n\t\t\t/* hook corresponding network in scan queue */\n\t\t\tplink = _rtw_mesh_plink_get(padapter, mac);\n\t\t\tplink->aid = params->aid;\n\t\t\tplink->scanned = scanned;\n\n\t\t\t#if CONFIG_RTW_MESH_ACNODE_PREVENT\n\t\t\tif (acnode) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" acnode \"MAC_FMT\"\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(scanned->network.MacAddress));\n\t\t\t}\n\t\t\t#endif\n\n\t\t\tadd_new_sta = 1;\n\t\t} else {\n\t\t\tRTW_WARN(FUNC_NDEV_FMT\" rtw_mesh_plink_add not success\\n\"\n\t\t\t\t, FUNC_NDEV_ARG(ndev));\n\t\t\tret = -EINVAL;\n\t\t}\nrelease_plink_ctl:\n\t\t_exit_critical_bh(&(plink_ctl->lock), &irqL);\n\n\t\tif (probe_req)\n\t\t\tissue_probereq(padapter, &padapter->mlmepriv.cur_network.network.mesh_id, mac);\n\n\t\tif (add_new_sta) {\n\t\t\tstruct station_info sinfo;\n\n\t\t\t#ifdef CONFIG_DFS_MASTER\n\t\t\tif (IS_UNDER_CAC(adapter_to_rfctl(padapter)))\n\t\t\t\trtw_force_stop_cac(adapter_to_rfctl(padapter), 300);\n\t\t\t#endif\n\n\t\t\t/* indicate new sta */\n\t\t\t_rtw_memset(&sinfo, 0, sizeof(sinfo));\n\t\t\tcfg80211_new_sta(ndev, mac, &sinfo, GFP_ATOMIC);\n\t\t}\n\t\tgoto exit;\n\t}\n#endif /* CONFIG_RTW_MESH */\n\n#ifdef CONFIG_TDLS\n\tpsta = rtw_get_stainfo(pstapriv, (u8 *)mac);\n\tif (psta == NULL) {\n\t\tpsta = rtw_alloc_stainfo(pstapriv, (u8 *)mac);\n\t\tif (psta == NULL) {\n\t\t\tRTW_INFO(\"[%s] Alloc station for \"MAC_FMT\" fail\\n\", __FUNCTION__, MAC_ARG(mac));\n\t\t\tret = -EOPNOTSUPP;\n\t\t\tgoto exit;\n\t\t}\n\t}\n#endif /* CONFIG_TDLS */\n\nexit:\n\treturn ret;\n}\n\nstatic int\tcfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev,\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))\n\tu8 *mac\n#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0))\n\tconst u8 *mac\n#else\n\tstruct station_del_parameters *params\n#endif\n)\n{\n\tint ret = 0;\n\t_irqL irqL;\n\t_list\t*phead, *plist;\n\tu8 updated = _FALSE;\n\tconst u8 *target_mac;\n\tstruct sta_info *psta = NULL;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0))\n\ttarget_mac = mac;\n#else\n\ttarget_mac = params->mac;\n#endif\n\n\tRTW_INFO(\"+\"FUNC_NDEV_FMT\" mac=%pM\\n\", FUNC_NDEV_ARG(ndev), target_mac);\n\n\tif (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE | WIFI_MESH_STATE)) != _TRUE) {\n\t\tRTW_INFO(\"%s, fw_state != FW_LINKED|WIFI_AP_STATE|WIFI_MESH_STATE\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\n\tif (!target_mac) {\n\t\tRTW_INFO(\"flush all sta, and cam_entry\\n\");\n\n\t\tflush_all_cam_entry(padapter);\t/* clear CAM */\n\n#ifdef CONFIG_AP_MODE\n\t\tret = rtw_sta_flush(padapter, _TRUE);\n#endif\n\t\treturn ret;\n\t}\n\n\n\tRTW_INFO(\"free sta macaddr =\" MAC_FMT \"\\n\", MAC_ARG(target_mac));\n\n\tif (target_mac[0] == 0xff && target_mac[1] == 0xff &&\n\t    target_mac[2] == 0xff && target_mac[3] == 0xff &&\n\t    target_mac[4] == 0xff && target_mac[5] == 0xff)\n\t\treturn -EINVAL;\n\n\n\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\tphead = &pstapriv->asoc_list;\n\tplist = get_next(phead);\n\n\t/* check asoc_queue */\n\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);\n\n\t\tplist = get_next(plist);\n\n\t\tif (_rtw_memcmp((u8 *)target_mac, psta->cmn.mac_addr, ETH_ALEN)) {\n\t\t\tif (psta->dot8021xalg == 1 && psta->bpairwise_key_installed == _FALSE)\n\t\t\t\tRTW_INFO(\"%s, sta's dot8021xalg = 1 and key_installed = _FALSE\\n\", __func__);\n\t\t\telse {\n\t\t\t\tRTW_INFO(\"free psta=%p, aid=%d\\n\", psta, psta->cmn.aid);\n\n\t\t\t\trtw_list_delete(&psta->asoc_list);\n\t\t\t\tpstapriv->asoc_list_cnt--;\n\t\t\t\tSTA_SET_MESH_PLINK(psta, NULL);\n\n\t\t\t\t/* _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); */\n\t\t\t\tif (MLME_IS_AP(padapter))\n\t\t\t\t\tupdated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE);\n\t\t\t\telse\n\t\t\t\t\tupdated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _TRUE);\n\t\t\t\t/* _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); */\n\n\t\t\t\tpsta = NULL;\n\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t}\n\n\t}\n\n\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\tassociated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(padapter))\n\t\trtw_mesh_plink_del(padapter, target_mac);\n#endif\n\n\tRTW_INFO(\"-\"FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(ndev));\n\n\treturn ret;\n\n}\n\nstatic int\tcfg80211_rtw_change_station(struct wiphy *wiphy, struct net_device *ndev,\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))\n\tu8 *mac,\n#else\n\tconst u8 *mac,\n#endif\n\tstruct station_parameters *params)\n{\n#ifdef CONFIG_RTW_MESH\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct sta_info *sta = NULL;\n\t_irqL irqL;\n#endif\n\tint ret = 0;\n\n\tRTW_INFO(FUNC_NDEV_FMT\" mac:\"MAC_FMT\"\\n\", FUNC_NDEV_ARG(ndev), MAC_ARG(mac));\n\n\tdump_station_parameters(RTW_DBGDUMP, wiphy, params);\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(adapter)) {\n\t\tenum cfg80211_station_type sta_type = CFG80211_STA_MESH_PEER_USER;\n\t\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\t\tstruct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;\n\t\tstruct mesh_plink_ent *plink = NULL;\n\t\t_irqL irqL2;\n\t\tstruct sta_info *del_sta = NULL;\n\n\t\tret = cfg80211_check_station_change(wiphy, params, sta_type);\n\t\tif (ret) {\n\t\t\tRTW_INFO(\"cfg80211_check_station_change return %d\\n\", ret);\n\t\t\tgoto exit;\n\t\t}\n\n\t\t_enter_critical_bh(&(plink_ctl->lock), &irqL2);\n\n\t\tplink = _rtw_mesh_plink_get(adapter, mac);\n\t\tif (!plink) {\n\t\t\tret = -ENOENT;\n\t\t\tgoto release_plink_ctl;\n\t\t}\n\n\t\tplink->plink_state = nl80211_plink_state_to_rtw_plink_state(params->plink_state);\n\n\t\t#if CONFIG_RTW_MESH_ACNODE_PREVENT\n\t\tif (params->plink_state == NL80211_PLINK_OPN_SNT\n\t\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))\n\t\t\t&& (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE)\n\t\t\t#endif\n\t\t) {\n\t\t\tif (rtw_mesh_scanned_is_acnode_confirmed(adapter, plink->scanned)\n\t\t\t\t&& rtw_mesh_acnode_prevent_allow_sacrifice(adapter)\n\t\t\t) {\n\t\t\t\tstruct sta_info *sac = rtw_mesh_acnode_prevent_pick_sacrifice(adapter);\n\n\t\t\t\tif (sac) {\n\t\t\t\t\tdel_sta = sac;\n\t\t\t\t\t_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);\n\t\t\t\t\tif (!rtw_is_list_empty(&del_sta->asoc_list)) {\n\t\t\t\t\t\trtw_list_delete(&del_sta->asoc_list);\n\t\t\t\t\t\tstapriv->asoc_list_cnt--;\n\t\t\t\t\t\tSTA_SET_MESH_PLINK(del_sta, NULL);\n\t\t\t\t\t}\n\t\t\t\t\t_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" sacrifice \"MAC_FMT\" for acnode\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(adapter), MAC_ARG(del_sta->cmn.mac_addr));\n\t\t\t\t}\n\t\t\t}\n\t\t} else\n\t\t#endif\n\t\tif ((params->plink_state == NL80211_PLINK_OPN_RCVD\n\t\t\t\t|| params->plink_state == NL80211_PLINK_CNF_RCVD\n\t\t\t\t|| params->plink_state == NL80211_PLINK_ESTAB)\n\t\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))\n\t\t\t&& (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE)\n\t\t\t#endif\n\t\t) {\n\t\t\tsta = rtw_get_stainfo(stapriv, mac);\n\t\t\tif (!sta) {\n\t\t\t\tsta = rtw_alloc_stainfo(stapriv, mac);\n\t\t\t\tif (!sta)\n\t\t\t\t\tgoto release_plink_ctl;\n\t\t\t}\n\n\t\t\tif (params->plink_state == NL80211_PLINK_ESTAB) {\n\t\t\t\tif (rtw_mesh_peer_establish(adapter, plink, sta) != _SUCCESS) {\n\t\t\t\t\trtw_free_stainfo(adapter, sta);\n\t\t\t\t\tret = -ENOENT;\n\t\t\t\t\tgoto release_plink_ctl;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse if (params->plink_state == NL80211_PLINK_HOLDING\n\t\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))\n\t\t\t&& (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE)\n\t\t\t#endif\n\t\t) {\n\t\t\tdel_sta = rtw_get_stainfo(stapriv, mac);\n\t\t\tif (!del_sta)\n\t\t\t\tgoto release_plink_ctl;\n\n\t\t\t_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);\n\t\t\tif (!rtw_is_list_empty(&del_sta->asoc_list)) {\n\t\t\t\trtw_list_delete(&del_sta->asoc_list);\n\t\t\t\tstapriv->asoc_list_cnt--;\n\t\t\t\tSTA_SET_MESH_PLINK(del_sta, NULL);\n\t\t\t}\n\t\t\t_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);\n\t\t}\n\nrelease_plink_ctl:\n\t\t_exit_critical_bh(&(plink_ctl->lock), &irqL2);\n\n\t\tif (del_sta) {\n\t\t\tu8 sta_addr[ETH_ALEN];\n\t\t\tu8 updated = _FALSE;\n\t\t\t\n\t\t\t_rtw_memcpy(sta_addr, del_sta->cmn.mac_addr, ETH_ALEN);\n\t\t\tupdated = ap_free_sta(adapter, del_sta, 0, 0, 1);\n\t\t\trtw_mesh_expire_peer(stapriv->padapter, sta_addr);\n\n\t\t\tassociated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL);\n\t\t}\n\t}\n\nexit:\n#endif /* CONFIG_RTW_MESH */\n\n\treturn ret;\n}\n\nstruct sta_info *rtw_sta_info_get_by_idx(struct sta_priv *pstapriv, const int idx, u8 *asoc_list_num)\n{\n\t_list\t*phead, *plist;\n\tstruct sta_info *psta = NULL;\n\tint i = 0;\n\n\tphead = &pstapriv->asoc_list;\n\tplist = get_next(phead);\n\n\t/* check asoc_queue */\n\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\tif (idx == i)\n\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);\n\t\tplist = get_next(plist);\n\t\ti++;\n\t}\n\n\tif (asoc_list_num)\n\t\t*asoc_list_num = i;\n\n\treturn psta;\n}\n\nstatic int\tcfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *ndev,\n\t\tint idx, u8 *mac, struct station_info *sinfo)\n{\n#define DBG_DUMP_STATION 0\n\n\tint ret = 0;\n\t_irqL irqL;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct sta_info *psta = NULL;\n#ifdef CONFIG_RTW_MESH\n\tstruct mesh_plink_ent *plink = NULL;\n#endif\n\tu8 asoc_list_num;\n\n\tif (DBG_DUMP_STATION)\n\t\tRTW_INFO(FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(ndev));\n\n\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\tpsta = rtw_sta_info_get_by_idx(pstapriv, idx, &asoc_list_num);\n\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(padapter)) {\n\t\tif (psta)\n\t\t\tplink = psta->plink;\n\t\tif (!plink)\n\t\t\tplink = rtw_mesh_plink_get_no_estab_by_idx(padapter, idx - asoc_list_num);\n\t}\n#endif /* CONFIG_RTW_MESH */\n\n\tif ((!MLME_IS_MESH(padapter) && !psta)\n\t\t#ifdef CONFIG_RTW_MESH\n\t\t|| (MLME_IS_MESH(padapter) && !plink)\n\t\t#endif\n\t) {\n\t\tif (DBG_DUMP_STATION)\n\t\t\tRTW_INFO(FUNC_NDEV_FMT\" end with idx:%d\\n\", FUNC_NDEV_ARG(ndev), idx);\n\t\tret = -ENOENT;\n\t\tgoto exit;\n\t}\n\n\tif (psta)\n\t\t_rtw_memcpy(mac, psta->cmn.mac_addr, ETH_ALEN);\n\t#ifdef CONFIG_RTW_MESH\n\telse\n\t\t_rtw_memcpy(mac, plink->addr, ETH_ALEN);\n\t#endif\n\t\n\tsinfo->filled = 0;\n\n\tif (psta) {\n\t\tsinfo->filled |= STATION_INFO_SIGNAL;\n\t\tsinfo->signal = translate_percentage_to_dbm(psta->cmn.rssi_stat.rssi);\n\t\tsinfo->filled |= STATION_INFO_INACTIVE_TIME;\n\t\tsinfo->inactive_time = rtw_get_passing_time_ms(psta->sta_stats.last_rx_time);\n\t}\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(padapter))\n\t\trtw_cfg80211_fill_mesh_only_sta_info(plink, psta, sinfo);\n#endif\n\nexit:\n\treturn ret;\n}\n\nstatic int\tcfg80211_rtw_change_bss(struct wiphy *wiphy, struct net_device *ndev,\n\t\tstruct bss_parameters *params)\n{\n\tRTW_INFO(FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(ndev));\n/*\n\tRTW_INFO(\"use_cts_prot=%d\\n\", params->use_cts_prot);\n\tRTW_INFO(\"use_short_preamble=%d\\n\", params->use_short_preamble);\n\tRTW_INFO(\"use_short_slot_time=%d\\n\", params->use_short_slot_time);\n\tRTW_INFO(\"ap_isolate=%d\\n\", params->ap_isolate);\n\n\tRTW_INFO(\"basic_rates_len=%d\\n\", params->basic_rates_len);\n\tfor(i = 0; i < params->basic_rates_len; i++)\n\t\tRTW_INFO(\"basic_rates=%d\\n\", params->basic_rates[i]);\n*/\n\treturn 0;\n\n}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))\nstatic int\tcfg80211_rtw_set_txq_params(struct wiphy *wiphy\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))\n\t, struct net_device *ndev\n#endif\n\t, struct ieee80211_txq_params *params)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))\n\t_adapter *padapter = rtw_netdev_priv(ndev);\n#else\n\t_adapter *padapter = wiphy_to_adapter(wiphy);\n#endif\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tu8\tac, AIFS, ECWMin, ECWMax, aSifsTime;\n\tu16\tTXOP;\n\tu8\tshift_count = 0;\n\tu32\tacParm;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))\n\tac = params->ac;\n#else\n\tac = params->queue;\n#endif\n\n#if 0\n\tRTW_INFO(\"ac=%d\\n\", ac);\n\tRTW_INFO(\"txop=%u\\n\", params->txop);\n\tRTW_INFO(\"cwmin=%u\\n\", params->cwmin);\n\tRTW_INFO(\"cwmax=%u\\n\", params->cwmax);\n\tRTW_INFO(\"aifs=%u\\n\", params->aifs);\n#endif\n\n\tif (is_supported_5g(pmlmeext->cur_wireless_mode) ||\n\t    (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))\n\t\taSifsTime = 16;\n\telse\n\t\taSifsTime = 10;\n\n\tAIFS = params->aifs * pmlmeinfo->slotTime + aSifsTime;\n\n\twhile ((params->cwmin + 1) >> shift_count != 1) {\n\t\tshift_count++;\n\t\tif (shift_count == 15)\n\t\t\tbreak;\n\t}\n\n\tECWMin = shift_count;\n\n\tshift_count = 0;\n\twhile ((params->cwmax + 1) >> shift_count != 1) {\n\t\tshift_count++;\n\t\tif (shift_count == 15)\n\t\t\tbreak;\n\t}\n\n\tECWMax = shift_count;\n\n\tTXOP = le16_to_cpu(params->txop);\n\n\tacParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);\n\n\tswitch (ac) {\n\tcase NL80211_TXQ_Q_VO:\n\t\tRTW_INFO(FUNC_NDEV_FMT\" AC_VO = 0x%08x\\n\", FUNC_ADPT_ARG(padapter), acParm);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));\n\t\tbreak;\n\n\tcase NL80211_TXQ_Q_VI:\n\t\tRTW_INFO(FUNC_NDEV_FMT\" AC_VI = 0x%08x\\n\", FUNC_ADPT_ARG(padapter), acParm);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));\n\t\tbreak;\n\n\tcase NL80211_TXQ_Q_BE:\n\t\tRTW_INFO(FUNC_NDEV_FMT\" AC_BE = 0x%08x\\n\", FUNC_ADPT_ARG(padapter), acParm);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));\n\t\tbreak;\n\n\tcase NL80211_TXQ_Q_BK:\n\t\tRTW_INFO(FUNC_NDEV_FMT\" AC_BK = 0x%08x\\n\", FUNC_ADPT_ARG(padapter), acParm);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn 0;\n}\n#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) */\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))\nstatic int\tcfg80211_rtw_set_channel(struct wiphy *wiphy\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\t, struct net_device *ndev\n\t#endif\n\t, struct ieee80211_channel *chan, enum nl80211_channel_type channel_type)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n#else\n\t_adapter *padapter = wiphy_to_adapter(wiphy);\n#endif\n\tint chan_target = (u8) ieee80211_frequency_to_channel(chan->center_freq);\n\tint chan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\tint chan_width = CHANNEL_WIDTH_20;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\tRTW_INFO(FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(ndev));\n#endif\n\n\tswitch (channel_type) {\n\tcase NL80211_CHAN_NO_HT:\n\tcase NL80211_CHAN_HT20:\n\t\tchan_width = CHANNEL_WIDTH_20;\n\t\tchan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tbreak;\n\tcase NL80211_CHAN_HT40MINUS:\n\t\tchan_width = CHANNEL_WIDTH_40;\n\t\tchan_offset = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\tbreak;\n\tcase NL80211_CHAN_HT40PLUS:\n\t\tchan_width = CHANNEL_WIDTH_40;\n\t\tchan_offset = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\tbreak;\n\tdefault:\n\t\tchan_width = CHANNEL_WIDTH_20;\n\t\tchan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tbreak;\n\t}\n\n\tRTW_INFO(FUNC_ADPT_FMT\" ch:%d bw:%d, offset:%d\\n\"\n\t\t, FUNC_ADPT_ARG(padapter), chan_target, chan_width, chan_offset);\n\n\trtw_set_chbw_cmd(padapter, chan_target, chan_width, chan_offset, RTW_CMDF_WAIT_ACK);\n\n\treturn 0;\n}\n#endif /*#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))*/\n\nstatic int cfg80211_rtw_set_monitor_channel(struct wiphy *wiphy\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))\n  #if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 13, 0))\n        , struct net_device *netdev\n  #endif\n        , struct cfg80211_chan_def *chandef\n#else\n\t, struct ieee80211_channel *chan\n\t, enum nl80211_channel_type channel_type\n#endif\n)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))\n\tstruct ieee80211_channel *chan = chandef->chan;\n#endif\n\n\t_adapter *padapter = wiphy_to_adapter(wiphy);\n\tint target_channal = chan->hw_value;\n\tint target_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\tint target_width = CHANNEL_WIDTH_20;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))\n#ifdef CONFIG_DEBUG_CFG80211\n\tRTW_INFO(\"center_freq %u Mhz ch %u width %u freq1 %u freq2 %u\\n\"\n\t\t, chan->center_freq\n\t\t, chan->hw_value\n\t\t, chandef->width\n\t\t, chandef->center_freq1\n\t\t, chandef->center_freq2);\n#endif /* CONFIG_DEBUG_CFG80211 */\n\n\tswitch (chandef->width) {\n\tcase NL80211_CHAN_WIDTH_20_NOHT:\n\tcase NL80211_CHAN_WIDTH_20:\n\t\ttarget_width = CHANNEL_WIDTH_20;\n\t\ttarget_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tbreak;\n\tcase NL80211_CHAN_WIDTH_40:\n\t\ttarget_width = CHANNEL_WIDTH_40;\n\t\tif (chandef->center_freq1 > chan->center_freq)\n\t\t\ttarget_offset = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\telse\n\t\t\ttarget_offset = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\tbreak;\n\tcase NL80211_CHAN_WIDTH_80:\n\t\ttarget_width = CHANNEL_WIDTH_80;\n\t\ttarget_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tbreak;\n\tcase NL80211_CHAN_WIDTH_80P80:\n\t\ttarget_width = CHANNEL_WIDTH_80_80;\n\t\ttarget_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tbreak;\n\tcase NL80211_CHAN_WIDTH_160:\n\t\ttarget_width = CHANNEL_WIDTH_160;\n\t\ttarget_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tbreak;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))\n\tcase NL80211_CHAN_WIDTH_5:\n\tcase NL80211_CHAN_WIDTH_10:\n#endif\n\tdefault:\n\t\ttarget_width = CHANNEL_WIDTH_20;\n\t\ttarget_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tbreak;\n\t}\n#else\n#ifdef CONFIG_DEBUG_CFG80211\n\tRTW_INFO(\"center_freq %u Mhz ch %u channel_type %u\\n\"\n\t\t, chan->center_freq\n\t\t, chan->hw_value\n\t\t, channel_type);\n#endif /* CONFIG_DEBUG_CFG80211 */\n\n\tswitch (channel_type) {\n\tcase NL80211_CHAN_NO_HT:\n\tcase NL80211_CHAN_HT20:\n\t\ttarget_width = CHANNEL_WIDTH_20;\n\t\ttarget_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tbreak;\n\tcase NL80211_CHAN_HT40MINUS:\n\t\ttarget_width = CHANNEL_WIDTH_40;\n\t\ttarget_offset = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\tbreak;\n\tcase NL80211_CHAN_HT40PLUS:\n\t\ttarget_width = CHANNEL_WIDTH_40;\n\t\ttarget_offset = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\tbreak;\n\tdefault:\n\t\ttarget_width = CHANNEL_WIDTH_20;\n\t\ttarget_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tbreak;\n\t}\n#endif\n\tRTW_INFO(FUNC_ADPT_FMT\" ch:%d bw:%d, offset:%d\\n\"\n\t\t, FUNC_ADPT_ARG(padapter), target_channal, target_width, target_offset);\n\n\trtw_set_chbw_cmd(padapter, target_channal, target_width, target_offset, RTW_CMDF_WAIT_ACK);\n\n\treturn 0;\n}\n/*\nstatic int\tcfg80211_rtw_auth(struct wiphy *wiphy, struct net_device *ndev,\n\t\tstruct cfg80211_auth_request *req)\n{\n\tRTW_INFO(FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(ndev));\n\n\treturn 0;\n}\n\nstatic int\tcfg80211_rtw_assoc(struct wiphy *wiphy, struct net_device *ndev,\n\t\tstruct cfg80211_assoc_request *req)\n{\n\tRTW_INFO(FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(ndev));\n\n\treturn 0;\n}\n*/\n#endif /* CONFIG_AP_MODE */\n\nvoid rtw_cfg80211_rx_probe_request(_adapter *adapter, union recv_frame *rframe)\n{\n\tstruct wireless_dev *wdev = adapter->rtw_wdev;\n\tu8 *frame = get_recvframe_data(rframe);\n\tuint frame_len = rframe->u.hdr.len;\n\ts32 freq;\n\tu8 ch, sch = rtw_get_oper_ch(adapter);\n\n\tch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;\n\tfreq = rtw_ch2freq(ch);\n\n#ifdef CONFIG_DEBUG_CFG80211\n\tRTW_INFO(\"RTW_Rx: probe request, ch=%d(%d), ta=\"MAC_FMT\"\\n\"\n\t\t, ch, sch, MAC_ARG(get_addr2_ptr(frame)));\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)\n\trtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);\n#else\n\tcfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);\n#endif\n}\n\nvoid rtw_cfg80211_rx_action_p2p(_adapter *adapter, union recv_frame *rframe)\n{\n\tstruct wireless_dev *wdev = adapter->rtw_wdev;\n\tu8 *frame = get_recvframe_data(rframe);\n\tuint frame_len = rframe->u.hdr.len;\n\ts32 freq;\n\tu8 ch, sch = rtw_get_oper_ch(adapter);\n\tu8 category, action;\n\tint type;\n\n\tch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;\n\tfreq = rtw_ch2freq(ch);\n\n\tRTW_INFO(\"RTW_Rx:ch=%d(%d), ta=\"MAC_FMT\"\\n\"\n\t\t, ch, sch, MAC_ARG(get_addr2_ptr(frame)));\n#ifdef CONFIG_P2P\n\ttype = rtw_p2p_check_frames(adapter, frame, frame_len, _FALSE);\n\tif (type >= 0)\n\t\tgoto indicate;\n#endif\n\trtw_action_frame_parse(frame, frame_len, &category, &action);\n\tRTW_INFO(\"RTW_Rx:category(%u), action(%u)\\n\", category, action);\n#ifdef CONFIG_P2P\nindicate:\n#endif\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\trtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);\n#else\n\tcfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);\n#endif\n}\n\nvoid rtw_cfg80211_rx_p2p_action_public(_adapter *adapter, union recv_frame *rframe)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct wireless_dev *wdev = adapter->rtw_wdev;\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);\n\tu8 *frame = get_recvframe_data(rframe);\n\tuint frame_len = rframe->u.hdr.len;\n\ts32 freq;\n\tu8 ch, sch = rtw_get_oper_ch(adapter);\n\tu8 category, action;\n\tint type;\n\n\tch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;\n\tfreq = rtw_ch2freq(ch);\n\n\tRTW_INFO(\"RTW_Rx:ch=%d(%d), ta=\"MAC_FMT\"\\n\"\n\t\t, ch, sch, MAC_ARG(get_addr2_ptr(frame)));\n\t#ifdef CONFIG_P2P\n\ttype = rtw_p2p_check_frames(adapter, frame, frame_len, _FALSE);\n\tif (type >= 0) {\n\t\tswitch (type) {\n\t\tcase P2P_GO_NEGO_CONF:\n\t\t\tif (0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" Nego confirm. state=%u, status=%u, iaddr=\"MAC_FMT\"\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(adapter), pwdev_priv->nego_info.state, pwdev_priv->nego_info.status\n\t\t\t\t\t, MAC_ARG(pwdev_priv->nego_info.iface_addr));\n\t\t\t}\n\t\t\tif (pwdev_priv->nego_info.state == 2\n\t\t\t\t&& pwdev_priv->nego_info.status == 0\n\t\t\t\t&& rtw_check_invalid_mac_address(pwdev_priv->nego_info.iface_addr, _FALSE) == _FALSE\n\t\t\t) {\n\t\t\t\t_adapter *intended_iface = dvobj_get_adapter_by_addr(dvobj, pwdev_priv->nego_info.iface_addr);\n\n\t\t\t\tif (intended_iface) {\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" Nego confirm. Allow only \"ADPT_FMT\" to scan for 2000 ms\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(adapter), ADPT_ARG(intended_iface));\n\t\t\t\t\t/* allow only intended_iface to do scan for 2000 ms */\n\t\t\t\t\trtw_mi_set_scan_deny(adapter, 2000);\n\t\t\t\t\trtw_clear_scan_deny(intended_iface);\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\tcase P2P_PROVISION_DISC_RESP:\n\t\tcase P2P_INVIT_RESP:\n\t\t\trtw_clear_scan_deny(adapter);\n\t\t\t#if !RTW_P2P_GROUP_INTERFACE\n\t\t\trtw_mi_buddy_set_scan_deny(adapter, 2000);\n\t\t\t#endif\n\t\t\tbreak;\n\t\t}\n\t\tgoto indicate;\n\t}\n\t#endif\n\trtw_action_frame_parse(frame, frame_len, &category, &action);\n\tRTW_INFO(\"RTW_Rx:category(%u), action(%u)\\n\", category, action);\n#ifdef CONFIG_P2P\nindicate:\n#endif\n\t#if defined(RTW_DEDICATED_P2P_DEVICE)\n\tif (rtw_cfg80211_redirect_pd_wdev(dvobj_to_wiphy(dvobj), get_ra(frame), &wdev))\n\t\tif (0)\n\t\t\tRTW_INFO(\"redirect to pd_wdev:%p\\n\", wdev);\n\t#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\trtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);\n#else\n\tcfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);\n#endif\n}\n\nvoid rtw_cfg80211_rx_action(_adapter *adapter, union recv_frame *rframe, const char *msg)\n{\n\tstruct wireless_dev *wdev = adapter->rtw_wdev;\n\tu8 *frame = get_recvframe_data(rframe);\n\tuint frame_len = rframe->u.hdr.len;\n\ts32 freq;\n\tu8 ch, sch = rtw_get_oper_ch(adapter);\n\tu8 category, action;\n\tint type = -1;\n\n\tch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;\n\tfreq = rtw_ch2freq(ch);\n\n\tRTW_INFO(\"RTW_Rx:ch=%d(%d), ta=\"MAC_FMT\"\\n\"\n\t\t, ch, sch, MAC_ARG(get_addr2_ptr(frame)));\n\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(adapter)) {\n\t\ttype = rtw_mesh_check_frames_rx(adapter, frame, frame_len);\n\t\tif (type >= 0)\n\t\t\tgoto indicate;\n\t}\n#endif\n\trtw_action_frame_parse(frame, frame_len, &category, &action);\n\tif (category == RTW_WLAN_CATEGORY_PUBLIC) {\n\t\tif (action == ACT_PUBLIC_GAS_INITIAL_REQ) {\n\t\t\trtw_mi_set_scan_deny(adapter, 200);\n\t\t\trtw_mi_scan_abort(adapter, _FALSE); /*rtw_scan_abort_no_wait*/\n\t\t}\n\t}\n#ifdef CONFIG_RTW_MESH\nindicate:\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\trtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);\n#else\n\tcfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);\n#endif\n\n\tif (type == -1) {\n\t\tif (msg)\n\t\t\tRTW_INFO(\"RTW_Rx:%s\\n\", msg);\n\t\telse\n\t\t\tRTW_INFO(\"RTW_Rx:category(%u), action(%u)\\n\", category, action);\n\t}\n}\n\n#ifdef CONFIG_RTW_80211K\nvoid rtw_cfg80211_rx_rrm_action(_adapter *adapter, union recv_frame *rframe)\n{\n\tstruct wireless_dev *wdev = adapter->rtw_wdev;\n\tu8 *frame = get_recvframe_data(rframe);\n\tuint frame_len = rframe->u.hdr.len;\n\ts32 freq;\n\tu8 ch, sch = rtw_get_oper_ch(adapter);\n\n\tch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;\n\tfreq = rtw_ch2freq(ch);\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\trtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);\n#else\n\tcfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);\n#endif\n\tRTW_INFO(\"RTW_Rx:ch=%d(%d), ta=\"MAC_FMT\"\\n\"\n\t\t, ch, sch, MAC_ARG(get_addr2_ptr(frame)));\n}\n#endif /* CONFIG_RTW_80211K */\n\nvoid rtw_cfg80211_rx_mframe(_adapter *adapter, union recv_frame *rframe, const char *msg)\n{\n\tstruct wireless_dev *wdev = adapter->rtw_wdev;\n\tu8 *frame = get_recvframe_data(rframe);\n\tuint frame_len = rframe->u.hdr.len;\n\ts32 freq;\n\tu8 ch, sch = rtw_get_oper_ch(adapter);\n\n\tch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;\n\tfreq = rtw_ch2freq(ch);\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\trtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);\n#else\n\tcfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);\n#endif\n\n\tRTW_INFO(\"RTW_Rx:ch=%d(%d), ta=\"MAC_FMT\"\\n\", ch, sch, MAC_ARG(get_addr2_ptr(frame)));\n\tif (!rtw_sae_preprocess(adapter, frame, frame_len, _FALSE)) {\n\t\tif (msg)\n\t\t\tRTW_INFO(\"RTW_Rx:%s\\n\", msg);\n\t\telse\n\t\t\tRTW_INFO(\"RTW_Rx:frame_control:0x%02x\\n\", le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)rframe)->frame_ctl));\n\t}\n}\n\n#ifdef CONFIG_P2P\nvoid rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len)\n{\n\tu16\twps_devicepassword_id = 0x0000;\n\tuint\twps_devicepassword_id_len = 0;\n\tu8\t\t\twpsie[255] = { 0x00 }, p2p_ie[255] = { 0x00 };\n\tuint\t\t\tp2p_ielen = 0;\n\tuint\t\t\twpsielen = 0;\n\tu32\tdevinfo_contentlen = 0;\n\tu8\tdevinfo_content[64] = { 0x00 };\n\tu16\tcapability = 0;\n\tuint capability_len = 0;\n\n\tunsigned char category = RTW_WLAN_CATEGORY_PUBLIC;\n\tu8\t\t\taction = P2P_PUB_ACTION_ACTION;\n\tu8\t\t\tdialogToken = 1;\n\tu32\t\t\tp2poui = cpu_to_be32(P2POUI);\n\tu8\t\t\toui_subtype = P2P_PROVISION_DISC_REQ;\n\tu32\t\t\tp2pielen = 0;\n#ifdef CONFIG_WFD\n\tu32\t\t\t\t\twfdielen = 0;\n#endif\n\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct rtw_ieee80211_hdr\t*pwlanhdr;\n\tunsigned short\t\t\t\t*fctrl;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n\tu8 *frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr));\n\tsize_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\n\tRTW_INFO(\"[%s] In\\n\", __FUNCTION__);\n\n\t/* prepare for building provision_request frame\t */\n\t_rtw_memcpy(pwdinfo->tx_prov_disc_info.peerIFAddr, GetAddr1Ptr(buf), ETH_ALEN);\n\t_rtw_memcpy(pwdinfo->tx_prov_disc_info.peerDevAddr, GetAddr1Ptr(buf), ETH_ALEN);\n\n\tpwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON;\n\n\trtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen);\n\trtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8 *) &wps_devicepassword_id, &wps_devicepassword_id_len);\n\twps_devicepassword_id = be16_to_cpu(wps_devicepassword_id);\n\n\tswitch (wps_devicepassword_id) {\n\tcase WPS_DPID_PIN:\n\t\tpwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL;\n\t\tbreak;\n\tcase WPS_DPID_USER_SPEC:\n\t\tpwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA;\n\t\tbreak;\n\tcase WPS_DPID_MACHINE_SPEC:\n\t\tbreak;\n\tcase WPS_DPID_REKEY:\n\t\tbreak;\n\tcase WPS_DPID_PBC:\n\t\tpwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON;\n\t\tbreak;\n\tcase WPS_DPID_REGISTRAR_SPEC:\n\t\tpwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\n\tif (rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, p2p_ie, &p2p_ielen)) {\n\n\t\trtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, devinfo_content, &devinfo_contentlen);\n\t\trtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&capability, &capability_len);\n\n\t}\n\n\n\t/* start to build provision_request frame\t */\n\t_rtw_memset(wpsie, 0, sizeof(wpsie));\n\t_rtw_memset(p2p_ie, 0, sizeof(p2p_ie));\n\tp2p_ielen = 0;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL)\n\t\treturn;\n\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\n\tfctrl = &(pwlanhdr->frame_ctl);\n\t*(fctrl) = 0;\n\n\t_rtw_memcpy(pwlanhdr->addr1, pwdinfo->tx_prov_disc_info.peerDevAddr, ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pwlanhdr->addr3, pwdinfo->tx_prov_disc_info.peerDevAddr, ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tset_frame_sub_type(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct rtw_ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));\n\tpframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));\n\n\n\t/* build_prov_disc_request_p2p_ie\t */\n\t/*\tP2P OUI */\n\tp2pielen = 0;\n\tp2p_ie[p2pielen++] = 0x50;\n\tp2p_ie[p2pielen++] = 0x6F;\n\tp2p_ie[p2pielen++] = 0x9A;\n\tp2p_ie[p2pielen++] = 0x09;\t/*\tWFA P2P v1.0 */\n\n\t/*\tCommented by Albert 20110301 */\n\t/*\tAccording to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes */\n\t/*\t1. P2P Capability */\n\t/*\t2. Device Info */\n\t/*\t3. Group ID ( When joining an operating P2P Group ) */\n\n\t/*\tP2P Capability ATTR */\n\t/*\tType:\t */\n\tp2p_ie[p2pielen++] = P2P_ATTR_CAPABILITY;\n\n\t/*\tLength: */\n\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); */\n\tRTW_PUT_LE16(p2p_ie + p2pielen, 0x0002);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tDevice Capability Bitmap, 1 byte */\n\t/*\tGroup Capability Bitmap, 1 byte */\n\t_rtw_memcpy(p2p_ie + p2pielen, &capability, 2);\n\tp2pielen += 2;\n\n\n\t/*\tDevice Info ATTR */\n\t/*\tType: */\n\tp2p_ie[p2pielen++] = P2P_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\t21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */\n\t/*\t+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */\n\t/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); */\n\tRTW_PUT_LE16(p2p_ie + p2pielen, devinfo_contentlen);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t_rtw_memcpy(p2p_ie + p2pielen, devinfo_content, devinfo_contentlen);\n\tp2pielen += devinfo_contentlen;\n\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2p_ie, &p2p_ielen);\n\t/* p2pielen = build_prov_disc_request_p2p_ie( pwdinfo, pframe, NULL, 0, pwdinfo->tx_prov_disc_info.peerDevAddr); */\n\t/* pframe += p2pielen; */\n\tpattrib->pktlen += p2p_ielen;\n\n\twpsielen = 0;\n\t/*\tWPS OUI */\n\t*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);\n\twpsielen += 4;\n\n\t/*\tWPS version */\n\t/*\tType: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);\n\twpsielen += 2;\n\n\t/*\tLength: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);\n\twpsielen += 2;\n\n\t/*\tValue: */\n\twpsie[wpsielen++] = WPS_VERSION_1;\t/*\tVersion 1.0 */\n\n\t/*\tConfig Method */\n\t/*\tType: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);\n\twpsielen += 2;\n\n\t/*\tLength: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);\n\twpsielen += 2;\n\n\t/*\tValue: */\n\t*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->tx_prov_disc_info.wps_config_method_request);\n\twpsielen += 2;\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);\n\n\n#ifdef CONFIG_WFD\n\twfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe);\n\tpframe += wfdielen;\n\tpattrib->pktlen += wfdielen;\n#endif\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\t/* dump_mgntframe(padapter, pmgntframe); */\n\tif (dump_mgntframe_and_wait_ack(padapter, pmgntframe) != _SUCCESS)\n\t\tRTW_INFO(\"%s, ack to\\n\", __func__);\n\n\t#if 0\n\tif(wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC) {\n\t\tRTW_INFO(\"waiting for p2p peer key-in PIN CODE\\n\");\n\t\trtw_msleep_os(15000); /* 15 sec for key in PIN CODE, workaround for GS2 before issuing Nego Req. */\n\t}\n\t#endif\n\n}\n\n#ifdef CONFIG_RTW_80211R\nstatic s32 cfg80211_rtw_update_ft_ies(struct wiphy *wiphy,\n\tstruct net_device *ndev,\n\tstruct cfg80211_update_ft_ies_params *ftie)\n{\n\t_adapter *padapter = NULL;\n\tstruct mlme_priv *pmlmepriv = NULL;\n\tstruct ft_roam_info *pft_roam = NULL;\n\t_irqL irqL;\n\tu8 *p;\n\tu8 *pie = NULL;\n\tu32 ie_len = 0;\n\n\tif (ndev == NULL)\n\t\treturn  -EINVAL;\n\n\tpadapter = (_adapter *)rtw_netdev_priv(ndev);\n\tpmlmepriv = &(padapter->mlmepriv);\n\tpft_roam = &(pmlmepriv->ft_roam);\n\n\tp = (u8 *)ftie->ie;\n\tif (ftie->ie_len <= sizeof(pft_roam->updated_ft_ies)) {\n\t\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\t\t_rtw_memcpy(pft_roam->updated_ft_ies, ftie->ie, ftie->ie_len);\n\t\tpft_roam->updated_ft_ies_len = ftie->ie_len;\n\t\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\t} else {\n\t\tRTW_ERR(\"FTIEs parsing fail!\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (rtw_ft_roam_status(padapter, RTW_FT_AUTHENTICATED_STA)) {\n\t\tRTW_PRINT(\"auth success, start reassoc\\n\");\n\t\trtw_ft_lock_set_status(padapter, RTW_FT_ASSOCIATING_STA, &irqL);\n\t\tstart_clnt_assoc(padapter);\n\t}\n\n\treturn 0;\n}\n#endif\n\nvoid rtw_cfg80211_external_auth_request(_adapter *padapter, union recv_frame *rframe)\n{\n\tstruct rtw_external_auth_params params;\n\tstruct wireless_dev *wdev = padapter->rtw_wdev;\n\tstruct net_device *netdev = wdev_to_ndev(wdev);\n\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n\tstruct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);\n\n\tu8 frame[256] = { 0 };\n\tuint frame_len = 24;\n\ts32 freq = 0;\n\n\t/* rframe, in this case is null point */\n\n\tfreq = rtw_ch2freq(pmlmeext->cur_channel);\n\n#ifdef CONFIG_DEBUG_CFG80211\n\tRTW_INFO(FUNC_ADPT_FMT\": freq(%d, %d)\\n\", FUNC_ADPT_ARG(padapter), freq);\n#endif\n\n#if (KERNEL_VERSION(4, 17, 0) <= LINUX_VERSION_CODE)\n\tparams.action = EXTERNAL_AUTH_START;\n\t_rtw_memcpy(params.bssid, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);\n\tparams.ssid.ssid_len = pmlmeinfo->network.Ssid.SsidLength;\n\t_rtw_memcpy(params.ssid.ssid, pmlmeinfo->network.Ssid.Ssid,\n\t\tpmlmeinfo->network.Ssid.SsidLength);\n\tparams.key_mgmt_suite = 0x8ac0f00;\n\n\tcfg80211_external_auth_request(netdev,\n\t\t(struct cfg80211_external_auth_params *)&params, GFP_ATOMIC);\n#elif (KERNEL_VERSION(2, 6, 37) <= LINUX_VERSION_CODE)\n\tset_frame_sub_type(frame, WIFI_AUTH);\n\n\t_rtw_memcpy(frame + 4, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);\n\t_rtw_memcpy(frame + 10, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(frame + 16, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);\n\tRTW_PUT_LE32((frame + 18), 0x8ac0f00);\n\n\tif (pmlmeinfo->network.Ssid.SsidLength) {\n\t\t*(frame + 23) = pmlmeinfo->network.Ssid.SsidLength;\n\t\t_rtw_memcpy(frame + 24, pmlmeinfo->network.Ssid.Ssid,\n\t\t\tpmlmeinfo->network.Ssid.SsidLength);\n\t\tframe_len = 24 + pmlmeinfo->network.Ssid.SsidLength;\n\t}\n\trtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);\n#endif\n}\n\ninline void rtw_cfg80211_set_is_roch(_adapter *adapter, bool val)\n{\n\tadapter->cfg80211_wdinfo.is_ro_ch = val;\n\trtw_mi_update_iface_status(&(adapter->mlmepriv), 0);\n}\n\ninline bool rtw_cfg80211_get_is_roch(_adapter *adapter)\n{\n\treturn adapter->cfg80211_wdinfo.is_ro_ch;\n}\n\ninline bool rtw_cfg80211_is_ro_ch_once(_adapter *adapter)\n{\n\treturn adapter->cfg80211_wdinfo.last_ro_ch_time ? 1 : 0;\n}\n\ninline void rtw_cfg80211_set_last_ro_ch_time(_adapter *adapter)\n{\n\tadapter->cfg80211_wdinfo.last_ro_ch_time = rtw_get_current_time();\n\n\tif (!adapter->cfg80211_wdinfo.last_ro_ch_time)\n\t\tadapter->cfg80211_wdinfo.last_ro_ch_time++;\n}\n\ninline s32 rtw_cfg80211_get_last_ro_ch_passing_ms(_adapter *adapter)\n{\n\treturn rtw_get_passing_time_ms(adapter->cfg80211_wdinfo.last_ro_ch_time);\n}\n\nstatic s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\tstruct wireless_dev *wdev,\n#else\n\tstruct net_device *ndev,\n#endif\n\tstruct ieee80211_channel *channel,\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))\n\tenum nl80211_channel_type channel_type,\n#endif\n\tunsigned int duration, u64 *cookie)\n{\n\ts32 err = 0;\n\tu8 remain_ch = (u8) ieee80211_frequency_to_channel(channel->center_freq);\n\t_adapter *padapter = NULL;\n\tstruct rtw_wdev_priv *pwdev_priv;\n\tstruct wifidirect_info *pwdinfo;\n\tstruct cfg80211_wifidirect_info *pcfg80211_wdinfo;\n#ifdef CONFIG_CONCURRENT_MODE\n\tu8 is_p2p_find = _FALSE;\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\t#if defined(RTW_DEDICATED_P2P_DEVICE)\n\tif (wdev == wiphy_to_pd_wdev(wiphy))\n\t\tpadapter = wiphy_to_adapter(wiphy);\n\telse\n\t#endif\n\tif (wdev_to_ndev(wdev))\n\t\tpadapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));\n\telse {\n\t\terr = -EINVAL;\n\t\tgoto exit;\n\t}\n#else\n\tstruct wireless_dev *wdev;\n\n\tif (ndev == NULL) {\n\t\terr = -EINVAL;\n\t\tgoto exit;\n\t}\n\tpadapter = (_adapter *)rtw_netdev_priv(ndev);\n\twdev = ndev_to_wdev(ndev);\n#endif\n\n\tpwdev_priv = adapter_wdev_data(padapter);\n\tpwdinfo = &padapter->wdinfo;\n\tpcfg80211_wdinfo = &padapter->cfg80211_wdinfo;\n#ifdef CONFIG_CONCURRENT_MODE\n\tis_p2p_find = (duration < (pwdinfo->ext_listen_interval)) ? _TRUE : _FALSE;\n#endif\n\n\t*cookie = ATOMIC_INC_RETURN(&pcfg80211_wdinfo->ro_ch_cookie_gen);\n\n\tRTW_INFO(FUNC_ADPT_FMT\"%s ch:%u duration:%d, cookie:0x%llx\\n\"\n\t\t, FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? \" PD\" : \"\"\n\t\t, remain_ch, duration, *cookie);\n\n\tif (rtw_chset_search_ch(adapter_to_chset(padapter), remain_ch) < 0) {\n\t\tRTW_WARN(FUNC_ADPT_FMT\" invalid ch:%u\\n\", FUNC_ADPT_ARG(padapter), remain_ch);\n\t\terr = -EFAULT;\n\t\tgoto exit;\n\t}\n\n#ifdef CONFIG_MP_INCLUDED\n\tif (rtw_mp_mode_check(padapter)) {\n\t\tRTW_INFO(\"MP mode block remain_on_channel request\\n\");\n\t\terr = -EFAULT;\n\t\tgoto exit;\n\t}\n#endif\n\n\tif (_FAIL == rtw_pwr_wakeup(padapter)) {\n\t\terr = -EFAULT;\n\t\tgoto exit;\n\t}\n\n\trtw_scan_abort(padapter);\n#ifdef CONFIG_CONCURRENT_MODE\n\t/*don't scan_abort during p2p_listen.*/\n\tif (is_p2p_find)\n\t\trtw_mi_buddy_scan_abort(padapter, _TRUE);\n#endif /*CONFIG_CONCURRENT_MODE*/\n\n\tif (rtw_cfg80211_get_is_roch(padapter) == _TRUE) {\n\t\t_cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer);\n\t\tp2p_cancel_roch_cmd(padapter, 0, NULL, RTW_CMDF_WAIT_ACK);\n\t}\n\n\t/* if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) */\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)\n\t\t#if defined(CONFIG_ANDROID) && !defined(RTW_SINGLE_WIPHY)\n\t\t&& (!is_primary_adapter(padapter))\n\t\t/*wlan0 can't be p2p device in CONFIG_ANDROID */\n\t\t#endif\n\t){\n\t\trtw_p2p_enable(padapter, P2P_ROLE_DEVICE);\n\t\tpadapter->wdinfo.listen_channel = remain_ch;\n\t\tRTW_INFO(FUNC_ADPT_FMT\" init listen_channel %u\\n\"\n\t\t\t, FUNC_ADPT_ARG(padapter), padapter->wdinfo.listen_channel);\n\t} else if (rtw_p2p_chk_state(pwdinfo , P2P_STATE_LISTEN)\n\t\t&& (time_after_eq(rtw_get_current_time(), pwdev_priv->probe_resp_ie_update_time)\n\t\t\t&& rtw_get_passing_time_ms(pwdev_priv->probe_resp_ie_update_time) < 50)\n\t) {\n\t\tif (padapter->wdinfo.listen_channel != remain_ch) {\n\t\t\tpadapter->wdinfo.listen_channel = remain_ch;\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" update listen_channel %u\\n\"\n\t\t\t\t, FUNC_ADPT_ARG(padapter), padapter->wdinfo.listen_channel);\n\t\t}\n\t} else {\n\t\trtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));\n#ifdef CONFIG_DEBUG_CFG80211\n\t\tRTW_INFO(\"%s, role=%d, p2p_state=%d\\n\", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));\n#endif\n\t}\n\n\trtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);\n\n\t#ifdef RTW_ROCH_DURATION_ENLARGE\n\tif (duration < 400)\n\t\tduration = duration * 3; /* extend from exper */\n\t#endif\n\n#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE)\n\tif (rtw_mi_check_status(padapter, MI_LINKED)) {\n\t\tif (is_p2p_find) /* p2p_find , duration<1000 */\n\t\t\tduration = duration + pwdinfo->ext_listen_interval;\n\t\telse /* p2p_listen, duration=5000 */\n\t\t\tduration = pwdinfo->ext_listen_interval + (pwdinfo->ext_listen_interval / 4);\n\t}\n#endif /*defined (RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE) */\n\n\trtw_cfg80211_set_is_roch(padapter, _TRUE);\n\tpcfg80211_wdinfo->ro_ch_wdev = wdev;\n\tpcfg80211_wdinfo->remain_on_ch_cookie = *cookie;\n\trtw_cfg80211_set_last_ro_ch_time(padapter);\n\t_rtw_memcpy(&pcfg80211_wdinfo->remain_on_ch_channel, channel, sizeof(struct ieee80211_channel));\n\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))\n\tpcfg80211_wdinfo->remain_on_ch_type = channel_type;\n\t#endif\n\tpcfg80211_wdinfo->restore_channel = rtw_get_oper_ch(padapter);\n\n\tp2p_roch_cmd(padapter, *cookie, wdev, channel, pcfg80211_wdinfo->remain_on_ch_type,\n\t\tduration, RTW_CMDF_WAIT_ACK);\n\n\trtw_cfg80211_ready_on_channel(wdev, *cookie, channel, channel_type, duration, GFP_KERNEL);\nexit:\n\treturn err;\n}\n\nstatic s32 cfg80211_rtw_cancel_remain_on_channel(struct wiphy *wiphy,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\tstruct wireless_dev *wdev,\n#else\n\tstruct net_device *ndev,\n#endif\n\tu64 cookie)\n{\n\ts32 err = 0;\n\t_adapter *padapter;\n\tstruct rtw_wdev_priv *pwdev_priv;\n\tstruct wifidirect_info *pwdinfo;\n\tstruct cfg80211_wifidirect_info *pcfg80211_wdinfo;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\t#if defined(RTW_DEDICATED_P2P_DEVICE)\n\tif (wdev == wiphy_to_pd_wdev(wiphy))\n\t\tpadapter = wiphy_to_adapter(wiphy);\n\telse\n\t#endif\n\tif (wdev_to_ndev(wdev))\n\t\tpadapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));\n\telse {\n\t\terr = -EINVAL;\n\t\tgoto exit;\n\t}\n#else\n\tstruct wireless_dev *wdev;\n\n\tif (ndev == NULL) {\n\t\terr = -EINVAL;\n\t\tgoto exit;\n\t}\n\tpadapter = (_adapter *)rtw_netdev_priv(ndev);\n\twdev = ndev_to_wdev(ndev);\n#endif\n\n\tpwdev_priv = adapter_wdev_data(padapter);\n\tpwdinfo = &padapter->wdinfo;\n\tpcfg80211_wdinfo = &padapter->cfg80211_wdinfo;\n\n\tRTW_INFO(FUNC_ADPT_FMT\"%s cookie:0x%llx\\n\"\n\t\t, FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? \" PD\" : \"\"\n\t\t, cookie);\n\n\tif (rtw_cfg80211_get_is_roch(padapter) == _TRUE) {\n\t\t_cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer);\n\t\tp2p_cancel_roch_cmd(padapter, cookie, wdev, RTW_CMDF_WAIT_ACK);\n\t}\n\nexit:\n\treturn err;\n}\n\ninline int rtw_cfg80211_iface_has_p2p_group_cap(_adapter *adapter)\n{\n#if RTW_P2P_GROUP_INTERFACE\n\tif (is_primary_adapter(adapter))\n\t\treturn 0;\n#endif\n\treturn 1;\n}\n\ninline int rtw_cfg80211_is_p2p_scan(_adapter *adapter)\n{\n#if RTW_P2P_GROUP_INTERFACE\n\tif (rtw_cfg80211_iface_has_p2p_group_cap(adapter))\n#endif\n\t{\n\t\tstruct wifidirect_info *wdinfo = &adapter->wdinfo;\n\n\t\treturn rtw_p2p_chk_state(wdinfo, P2P_STATE_SCAN)\n\t\t\t|| rtw_p2p_chk_state(wdinfo, P2P_STATE_FIND_PHASE_SEARCH);\n\t}\n\n#if RTW_P2P_GROUP_INTERFACE\n\t#if defined(RTW_DEDICATED_P2P_DEVICE)\n\tif (wiphy_to_pd_wdev(adapter_to_wiphy(adapter))) /* pd_wdev exist */\n\t\treturn rtw_cfg80211_is_scan_by_pd_wdev(adapter);\n\t#endif\n\t{\n\t\t/*\n\t\t* For 2 RTW_P2P_GROUP_INTERFACE cases:\n\t\t* 1. RTW_DEDICATED_P2P_DEVICE defined but upper layer don't use pd_wdev or\n\t\t* 2. RTW_DEDICATED_P2P_DEVICE not defined\n\t\t*/\n\t\tstruct rtw_wdev_priv *wdev_data = adapter_wdev_data(adapter);\n\t\t_irqL irqL;\n\t\tint is_p2p_scan = 0;\n\n\t\t_enter_critical_bh(&wdev_data->scan_req_lock, &irqL);\n\t\tif (wdev_data->scan_request\n\t\t\t&& wdev_data->scan_request->n_ssids\n\t\t\t&& wdev_data->scan_request->ssids\n\t\t\t&& wdev_data->scan_request->ie\n\t\t) {\n\t\t\tif (_rtw_memcmp(wdev_data->scan_request->ssids[0].ssid, \"DIRECT-\", 7)\n\t\t\t\t&& rtw_get_p2p_ie((u8 *)wdev_data->scan_request->ie, wdev_data->scan_request->ie_len, NULL, NULL))\n\t\t\t\tis_p2p_scan = 1;\n\t\t}\n\t\t_exit_critical_bh(&wdev_data->scan_req_lock, &irqL);\n\n\t\treturn is_p2p_scan;\n\t}\n#endif\n}\n\n#if defined(RTW_DEDICATED_P2P_DEVICE)\nint rtw_pd_iface_alloc(struct wiphy *wiphy, const char *name, struct wireless_dev **pd_wdev)\n{\n\tstruct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy);\n\tstruct wireless_dev *wdev = NULL;\n\tstruct rtw_netdev_priv_indicator *npi;\n\t_adapter *primary_adpt = wiphy_to_adapter(wiphy);\n\tint ret = 0;\n\n\tif (wiphy_data->pd_wdev) {\n\t\tRTW_WARN(FUNC_WIPHY_FMT\" pd_wdev already exists\\n\", FUNC_WIPHY_ARG(wiphy));\n\t\tret = -EBUSY;\n\t\tgoto exit;\n\t}\n\n\twdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev));\n\tif (!wdev) {\n\t\tRTW_WARN(FUNC_WIPHY_FMT\" allocate wdev fail\\n\", FUNC_WIPHY_ARG(wiphy));\n\t\tret = -ENOMEM;\n\t\tgoto exit;\n\t}\n\n\twdev->wiphy = wiphy;\n\twdev->iftype = NL80211_IFTYPE_P2P_DEVICE;\n\t_rtw_memcpy(wdev->address, adapter_mac_addr(primary_adpt), ETH_ALEN);\n\n\twiphy_data->pd_wdev = wdev;\n\t*pd_wdev = wdev;\n\n\tRTW_INFO(FUNC_WIPHY_FMT\" pd_wdev:%p, addr=\"MAC_FMT\" added\\n\"\n\t\t, FUNC_WIPHY_ARG(wiphy), wdev, MAC_ARG(wdev_address(wdev)));\n\nexit:\n\tif (ret && wdev) {\n\t\trtw_mfree((u8 *)wdev, sizeof(struct wireless_dev));\n\t\twdev = NULL;\n\t}\n\n\treturn ret;\n}\n\nvoid rtw_pd_iface_free(struct wiphy *wiphy)\n{\n\tstruct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);\n\tstruct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy);\n\tu8 rtnl_lock_needed;\n\n\tif (!wiphy_data->pd_wdev)\n\t\tgoto exit;\n\n\tRTW_INFO(FUNC_WIPHY_FMT\" pd_wdev:%p, addr=\"MAC_FMT\"\\n\"\n\t\t, FUNC_WIPHY_ARG(wiphy), wiphy_data->pd_wdev\n\t\t, MAC_ARG(wdev_address(wiphy_data->pd_wdev)));\n\n\trtnl_lock_needed = rtw_rtnl_lock_needed(dvobj);\n\tif (rtnl_lock_needed)\n\t\trtnl_lock();\n\tcfg80211_unregister_wdev(wiphy_data->pd_wdev);\n\tif (rtnl_lock_needed)\n\t\trtnl_unlock();\n\n\trtw_mfree((u8 *)wiphy_data->pd_wdev, sizeof(struct wireless_dev));\n\twiphy_data->pd_wdev = NULL;\n\nexit:\n\treturn;\n}\n\nstatic int cfg80211_rtw_start_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev)\n{\n\t_adapter *adapter = wiphy_to_adapter(wiphy);\n\n\tRTW_INFO(FUNC_WIPHY_FMT\" wdev=%p\\n\", FUNC_WIPHY_ARG(wiphy), wdev);\n\n\trtw_p2p_enable(adapter, P2P_ROLE_DEVICE);\n\treturn 0;\n}\n\nstatic void cfg80211_rtw_stop_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev)\n{\n\t_adapter *adapter = wiphy_to_adapter(wiphy);\n\n\tRTW_INFO(FUNC_WIPHY_FMT\" wdev=%p\\n\", FUNC_WIPHY_ARG(wiphy), wdev);\n\n\tif (rtw_cfg80211_is_p2p_scan(adapter))\n\t\trtw_scan_abort(adapter);\n\n\trtw_p2p_enable(adapter, P2P_ROLE_DISABLE);\n}\n\ninline int rtw_cfg80211_redirect_pd_wdev(struct wiphy *wiphy, u8 *ra, struct wireless_dev **wdev)\n{\n\tstruct wireless_dev *pd_wdev = wiphy_to_pd_wdev(wiphy);\n\n\tif (pd_wdev && pd_wdev != *wdev\n\t\t&& _rtw_memcmp(wdev_address(pd_wdev), ra, ETH_ALEN) == _TRUE\n\t) {\n\t\t*wdev = pd_wdev;\n\t\treturn 1;\n\t}\n\treturn 0;\n}\n\ninline int rtw_cfg80211_is_scan_by_pd_wdev(_adapter *adapter)\n{\n\tstruct wiphy *wiphy = adapter_to_wiphy(adapter);\n\tstruct rtw_wdev_priv *wdev_data = adapter_wdev_data(adapter);\n\tstruct wireless_dev *wdev = NULL;\n\t_irqL irqL;\n\n\t_enter_critical_bh(&wdev_data->scan_req_lock, &irqL);\n\tif (wdev_data->scan_request)\n\t\twdev = wdev_data->scan_request->wdev;\n\t_exit_critical_bh(&wdev_data->scan_req_lock, &irqL);\n\n\tif (wdev && wdev == wiphy_to_pd_wdev(wiphy))\n\t\treturn 1;\n\n\treturn 0;\n}\n#endif /* RTW_DEDICATED_P2P_DEVICE */\n#endif /* CONFIG_P2P */\n\ninline void rtw_cfg80211_set_is_mgmt_tx(_adapter *adapter, u8 val)\n{\n\tstruct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter);\n\n\twdev_priv->is_mgmt_tx = val;\n\trtw_mi_update_iface_status(&(adapter->mlmepriv), 0);\n}\n\ninline u8 rtw_cfg80211_get_is_mgmt_tx(_adapter *adapter)\n{\n\tstruct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter);\n\n\treturn wdev_priv->is_mgmt_tx;\n}\n\nstatic int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack)\n{\n\tstruct xmit_frame\t*pmgntframe;\n\tstruct pkt_attrib\t*pattrib;\n\tunsigned char\t*pframe;\n\tint ret = _FAIL;\n\tbool ack = _TRUE;\n\tstruct rtw_ieee80211_hdr *pwlanhdr;\n#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n#endif\n\tstruct xmit_priv\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tu8 u_ch = rtw_mi_get_union_chan(padapter);\n\tu8 leave_op = 0;\n#ifdef CONFIG_P2P\n\tstruct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;\n\t#ifdef CONFIG_CONCURRENT_MODE\n\tstruct wifidirect_info *pwdinfo = &padapter->wdinfo;\n\t#endif\n#endif\n\n\trtw_cfg80211_set_is_mgmt_tx(padapter, 1);\n\n#ifdef CONFIG_BT_COEXIST\n\trtw_btcoex_ScanNotify(padapter, _TRUE);\n#endif\n\n#ifdef CONFIG_P2P\n\tif (rtw_cfg80211_get_is_roch(padapter) == _TRUE) {\n\t\t#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) {\n\t\t\tRTW_INFO(\"%s, extend ro ch time\\n\", __func__);\n\t\t\t_set_timer(&padapter->cfg80211_wdinfo.remain_on_ch_timer, pwdinfo->ext_listen_period);\n\t\t}\n\t\t#endif /* CONFIG_CONCURRENT_MODE */\n\t}\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_MCC_MODE\n\tif (MCC_EN(padapter)) {\n\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))\n\t\t\t/* don't set channel, issue frame directly */\n\t\t\tgoto issue_mgmt_frame;\n\t}\n#endif /* CONFIG_MCC_MODE */\n\n\tif (rtw_mi_check_status(padapter, MI_LINKED)\n\t\t&& tx_ch != u_ch\n\t) {\n\t\trtw_leave_opch(padapter);\n\t\tleave_op = 1;\n\n\t\t#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)\n\t\tif (rtw_cfg80211_get_is_roch(padapter)\n\t\t\t&& ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1\n\t\t) {\n\t\t\tu16 ext_listen_period;\n\n\t\t\tif (check_fwstate(&padapter->mlmepriv, _FW_LINKED))\n\t\t\t\text_listen_period = 500;\n\t\t\telse\n\t\t\t\text_listen_period = pwdinfo->ext_listen_period;\n\t\t\tATOMIC_SET(&pwdev_priv->switch_ch_to, 0);\n\t\t\t_set_timer(&pwdinfo->ap_p2p_switch_timer, ext_listen_period);\n\t\t\tRTW_INFO(\"%s, set switch ch timer, period=%d\\n\", __func__, ext_listen_period);\n\t\t}\n\t\t#endif /* RTW_ROCH_BACK_OP && CONFIG_P2P && CONFIG_CONCURRENT_MODE */\n\t}\n\n\tif (tx_ch != rtw_get_oper_ch(padapter))\n\t\tset_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n#ifdef CONFIG_MCC_MODE\nissue_mgmt_frame:\n#endif\n\t/* starting alloc mgmt frame to dump it */\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (pmgntframe == NULL) {\n\t\t/* ret = -ENOMEM; */\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\tif (no_cck && IS_CCK_RATE(pattrib->rate)) {\n\t\t/* force OFDM 6M rate*/\n\t\tpattrib->rate = MGN_6M;\n\t\tpattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G);\n\t}\n\n\tpattrib->retry_ctrl = _FALSE;\n\n\t_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\n\t_rtw_memcpy(pframe, (void *)buf, len);\n\tpattrib->pktlen = len;\n\n\tpwlanhdr = (struct rtw_ieee80211_hdr *)pframe;\n\t/* update seq number */\n\tpmlmeext->mgnt_seq = GetSequence(pwlanhdr);\n\tpattrib->seqnum = pmlmeext->mgnt_seq;\n\tpmlmeext->mgnt_seq++;\n\n#ifdef CONFIG_P2P\n\trtw_xframe_chk_wfd_ie(pmgntframe);\n#endif /* CONFIG_P2P */\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tif (wait_ack) {\n\t\tif (dump_mgntframe_and_wait_ack(padapter, pmgntframe) != _SUCCESS) {\n\t\t\tack = _FALSE;\n\t\t\tret = _FAIL;\n\n#ifdef CONFIG_DEBUG_CFG80211\n\t\t\tRTW_INFO(\"%s, ack == _FAIL\\n\", __func__);\n#endif\n\t\t} else {\n\n#ifdef CONFIG_XMIT_ACK\n\t\t\tif (!MLME_IS_MESH(padapter)) /* TODO: remove this sleep for all mode */\n\t\t\t\trtw_msleep_os(50);\n#endif\n#ifdef CONFIG_DEBUG_CFG80211\n\t\t\tRTW_INFO(\"%s, ack=%d, ok!\\n\", __func__, ack);\n#endif\n\t\t\tret = _SUCCESS;\n\t\t}\n\t} else {\n\t\tdump_mgntframe(padapter, pmgntframe);\n\t\tret = _SUCCESS;\n\t}\n\nexit:\n\t#ifdef CONFIG_P2P\n\tif (rtw_cfg80211_get_is_roch(padapter)\n\t\t&& !roch_stay_in_cur_chan(padapter)\n\t\t&& pcfg80211_wdinfo->remain_on_ch_channel.hw_value != u_ch\n\t) {\n\t\t/* roch is ongoing, switch back to rch */\n\t\tif (pcfg80211_wdinfo->remain_on_ch_channel.hw_value != tx_ch)\n\t\t\tset_channel_bwmode(padapter, pcfg80211_wdinfo->remain_on_ch_channel.hw_value\n\t\t\t\t, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n\t} else\n\t#endif\n\tif (leave_op) {\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED)) {\n\t\t\tu8 u_bw = rtw_mi_get_union_bw(padapter);\n\t\t\tu8 u_offset = rtw_mi_get_union_offset(padapter);\n\n\t\t\tset_channel_bwmode(padapter, u_ch, u_offset, u_bw);\n\t\t}\n\t\trtw_back_opch(padapter);\n\t}\n\n\trtw_cfg80211_set_is_mgmt_tx(padapter, 0);\n\n#ifdef CONFIG_BT_COEXIST\n\trtw_btcoex_ScanNotify(padapter, _FALSE);\n#endif\n\n#ifdef CONFIG_DEBUG_CFG80211\n\tRTW_INFO(\"%s, ret=%d\\n\", __func__, ret);\n#endif\n\n\treturn ret;\n\n}\n\nu8 rtw_mgnt_tx_handler(_adapter *adapter, u8 *buf)\n{\n\tu8 rst = H2C_CMD_FAIL;\n\tstruct mgnt_tx_parm *mgnt_parm = (struct mgnt_tx_parm *)buf;\n\n\tif (_cfg80211_rtw_mgmt_tx(adapter, mgnt_parm->tx_ch, mgnt_parm->no_cck,\n\t\tmgnt_parm->buf, mgnt_parm->len, mgnt_parm->wait_ack) == _SUCCESS)\n\t\trst = H2C_SUCCESS;\n\n\treturn rst;\n}\n\nstatic int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\tstruct wireless_dev *wdev,\n#else\n\tstruct net_device *ndev,\n#endif\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) || defined(COMPAT_KERNEL_RELEASE)\n\tstruct ieee80211_channel *chan,\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)\n\tbool offchan,\n\t#endif\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))\n\tenum nl80211_channel_type channel_type,\n\t#endif\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))\n\tbool channel_type_valid,\n\t#endif\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)\n\tunsigned int wait,\n\t#endif\n\tconst u8 *buf, size_t len,\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))\n\tbool no_cck,\n\t#endif\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))\n\tbool dont_wait_for_ack,\n\t#endif\n#else\n\tstruct cfg80211_mgmt_tx_params *params,\n#endif\n\tu64 *cookie)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(COMPAT_KERNEL_RELEASE)\n\tstruct ieee80211_channel *chan = params->chan;\n\tconst u8 *buf = params->buf;\n\tsize_t len = params->len;\n\tbool no_cck = params->no_cck;\n#endif\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0))\n\tbool no_cck = 0;\n#endif\n\tint ret = 0;\n\tu8 tx_ret;\n\tint wait_ack = 1;\n\tconst u8 *dump_buf = buf;\n\tsize_t dump_len = len;\n\tu32 dump_limit = RTW_MAX_MGMT_TX_CNT;\n\tu32 dump_cnt = 0;\n\tu32 sleep_ms = 0;\n\tu32 retry_guarantee_ms = 0;\n\tbool ack = _TRUE;\n\tu8 tx_ch;\n\tu8 category, action;\n\tu8 frame_styp;\n#ifdef CONFIG_P2P\n\tu8 is_p2p = 0;\n#endif\n\tint type = (-1);\n\tsystime start = rtw_get_current_time();\n\t_adapter *padapter;\n\tstruct dvobj_priv *dvobj;\n\tstruct rtw_wdev_priv *pwdev_priv;\n\tstruct rf_ctl_t *rfctl;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\t#if defined(RTW_DEDICATED_P2P_DEVICE)\n\tif (wdev == wiphy_to_pd_wdev(wiphy))\n\t\tpadapter = wiphy_to_adapter(wiphy);\n\telse\n\t#endif\n\tif (wdev_to_ndev(wdev))\n\t\tpadapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));\n\telse {\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n#else\n\tstruct wireless_dev *wdev;\n\n\tif (ndev == NULL) {\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\tpadapter = (_adapter *)rtw_netdev_priv(ndev);\n\twdev = ndev_to_wdev(ndev);\n#endif\n\n\tif (chan == NULL) {\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\n\trfctl = adapter_to_rfctl(padapter);\n\ttx_ch = (u8)ieee80211_frequency_to_channel(chan->center_freq);\n\tif (IS_CH_WAITING(rfctl)) {\n\t\t#ifdef CONFIG_DFS_MASTER\n\t\tif (_rtw_rfctl_overlap_radar_detect_ch(rfctl, tx_ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE)) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\t#endif\n\t}\n\n\tdvobj = adapter_to_dvobj(padapter);\n\tpwdev_priv = adapter_wdev_data(padapter);\n\n\t/* cookie generation */\n\t*cookie = pwdev_priv->mgmt_tx_cookie++;\n\n#ifdef CONFIG_DEBUG_CFG80211\n\tRTW_INFO(FUNC_ADPT_FMT\"%s len=%zu, ch=%d\"\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))\n\t\t\", ch_type=%d\"\n\t\t#endif\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))\n\t\t\", channel_type_valid=%d\"\n\t\t#endif\n\t\t\"\\n\", FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? \" PD\" : \"\"\n\t\t, len, tx_ch\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))\n\t\t, channel_type\n\t\t#endif\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))\n\t\t, channel_type_valid\n\t\t#endif\n\t);\n#endif /* CONFIG_DEBUG_CFG80211 */\n\n\t/* indicate ack before issue frame to avoid racing with rsp frame */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\trtw_cfg80211_mgmt_tx_status(wdev, *cookie, buf, len, ack, GFP_KERNEL);\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 36))\n\tcfg80211_action_tx_status(ndev, *cookie, buf, len, ack, GFP_KERNEL);\n#endif\n\n\tframe_styp = le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl) & IEEE80211_FCTL_STYPE;\n\tif (IEEE80211_STYPE_PROBE_RESP == frame_styp) {\n#ifdef CONFIG_DEBUG_CFG80211\n\t\tRTW_INFO(\"RTW_Tx: probe_resp tx_ch=%d, no_cck=%u, da=\"MAC_FMT\"\\n\", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf)));\n#endif /* CONFIG_DEBUG_CFG80211 */\n\t\twait_ack = 0;\n\t\tgoto dump;\n\t}\n\telse if (frame_styp == RTW_IEEE80211_STYPE_AUTH) {\n\t\tint retval = 0;\n\n\t\tRTW_INFO(\"RTW_Tx:tx_ch=%d, no_cck=%u, da=\"MAC_FMT\"\\n\", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf)));\n\n\t\tretval = rtw_sae_preprocess(padapter, buf, len, _TRUE);\n\t\tif (retval == 2)\n\t\t\tgoto exit;\n\t\tif (retval == 0)\n\t\t\tRTW_INFO(\"RTW_Tx:AUTH\\n\");\n\t\tdump_limit = 1;\n\t\tgoto dump;\n\t}\n\n\tif (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" frame_control:0x%02x\\n\", FUNC_ADPT_ARG(padapter),\n\t\t\tle16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl));\n\t\tgoto exit;\n\t}\n\n\tRTW_INFO(\"RTW_Tx:tx_ch=%d, no_cck=%u, da=\"MAC_FMT\"\\n\", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf)));\n#ifdef CONFIG_P2P\n\ttype = rtw_p2p_check_frames(padapter, buf, len, _TRUE);\n\tif (type >= 0) {\n\t\tis_p2p = 1;\n\t\tno_cck = 1; /* force no CCK for P2P frames */\n\t\tgoto dump;\n\t}\n#endif\n#ifdef CONFIG_RTW_MESH\n\tif (MLME_IS_MESH(padapter)) {\n\t\ttype = rtw_mesh_check_frames_tx(padapter, &dump_buf, &dump_len);\n\t\tif (type >= 0) {\n\t\t\tdump_limit = 1;\n\t\t\tgoto dump;\n\t\t}\n\t}\n#endif\n\tif (category == RTW_WLAN_CATEGORY_PUBLIC) {\n\t\tRTW_INFO(\"RTW_Tx:%s\\n\", action_public_str(action));\n\t\tswitch (action) {\n\t\tcase ACT_PUBLIC_GAS_INITIAL_REQ:\n\t\tcase ACT_PUBLIC_GAS_INITIAL_RSP:\n\t\t\tsleep_ms = 50;\n\t\t\tretry_guarantee_ms = RTW_MAX_MGMT_TX_MS_GAS;\n\t\t\tbreak;\n\t\t}\n\t}\n#ifdef CONFIG_RTW_80211K\n\telse if (category == RTW_WLAN_CATEGORY_RADIO_MEAS)\n\t\tRTW_INFO(\"RTW_Tx: RRM Action\\n\");\n#endif\n\telse\n\t\tRTW_INFO(\"RTW_Tx:category(%u), action(%u)\\n\", category, action);\n\ndump:\n\n\trtw_ps_deny(padapter, PS_DENY_MGNT_TX);\n\tif (_FAIL == rtw_pwr_wakeup(padapter)) {\n\t\tret = -EFAULT;\n\t\tgoto cancel_ps_deny;\n\t}\n\n\twhile (1) {\n\t\tdump_cnt++;\n\n\t\trtw_mi_set_scan_deny(padapter, 1000);\n\t\trtw_mi_scan_abort(padapter, _TRUE);\n\t\ttx_ret = rtw_mgnt_tx_cmd(padapter, tx_ch, no_cck, dump_buf, dump_len, wait_ack, RTW_CMDF_WAIT_ACK);\n\t\tif (tx_ret == _SUCCESS\n\t\t\t|| (dump_cnt >= dump_limit && rtw_get_passing_time_ms(start) >= retry_guarantee_ms))\n\t\t\tbreak;\n\n\t\tif (sleep_ms > 0)\n\t\t\trtw_msleep_os(sleep_ms);\n\t}\n\n\tif (tx_ret != _SUCCESS || dump_cnt > 1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" %s (%d/%d) in %d ms\\n\", FUNC_ADPT_ARG(padapter),\n\t\t\ttx_ret == _SUCCESS ? \"OK\" : \"FAIL\", dump_cnt, dump_limit, rtw_get_passing_time_ms(start));\n\t}\n\n#ifdef CONFIG_P2P\n\tif (is_p2p) {\n\t\tswitch (type) {\n\t\tcase P2P_GO_NEGO_CONF:\n\t\t\tif (0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" Nego confirm. state=%u, status=%u, iaddr=\"MAC_FMT\"\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), pwdev_priv->nego_info.state, pwdev_priv->nego_info.status\n\t\t\t\t\t, MAC_ARG(pwdev_priv->nego_info.iface_addr));\n\t\t\t}\n\t\t\tif (pwdev_priv->nego_info.state == 2\n\t\t\t\t&& pwdev_priv->nego_info.status == 0\n\t\t\t\t&& rtw_check_invalid_mac_address(pwdev_priv->nego_info.iface_addr, _FALSE) == _FALSE\n\t\t\t) {\n\t\t\t\t_adapter *intended_iface = dvobj_get_adapter_by_addr(dvobj, pwdev_priv->nego_info.iface_addr);\n\n\t\t\t\tif (intended_iface) {\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" Nego confirm. Allow only \"ADPT_FMT\" to scan for 2000 ms\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter), ADPT_ARG(intended_iface));\n\t\t\t\t\t/* allow only intended_iface to do scan for 2000 ms */\n\t\t\t\t\trtw_mi_set_scan_deny(padapter, 2000);\n\t\t\t\t\trtw_clear_scan_deny(intended_iface);\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\tcase P2P_INVIT_RESP:\n\t\t\tif (pwdev_priv->invit_info.flags & BIT(0)\n\t\t\t\t&& pwdev_priv->invit_info.status == 0\n\t\t\t) {\n\t\t\t\trtw_clear_scan_deny(padapter);\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" agree with invitation of persistent group\\n\",\n\t\t\t\t\tFUNC_ADPT_ARG(padapter));\n\t\t\t\t#if !RTW_P2P_GROUP_INTERFACE\n\t\t\t\trtw_mi_buddy_set_scan_deny(padapter, 5000);\n\t\t\t\t#endif\n\t\t\t\trtw_pwr_wakeup_ex(padapter, 5000);\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t}\n#endif /* CONFIG_P2P */\n\ncancel_ps_deny:\n\trtw_ps_deny_cancel(padapter, PS_DENY_MGNT_TX);\n\n\tif (dump_buf != buf)\n\t\trtw_mfree((u8 *)dump_buf, dump_len);\nexit:\n\treturn ret;\n}\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))\nstatic void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\tstruct wireless_dev *wdev,\n#else\n\tstruct net_device *ndev,\n#endif\n\tu16 frame_type, bool reg)\n#else\nstatic void cfg80211_rtw_update_mgmt_frame_register(struct wiphy *wiphy,\n\t\t\t\t\t\t    struct wireless_dev *wdev,\n\t\t\t\t\t\t    struct mgmt_frame_regs *upd)\n#endif\n\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0))\n\tu32 rtw_mask = BIT(IEEE80211_STYPE_PROBE_REQ >> 4);\n#endif\n    \n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\tstruct net_device *ndev = wdev_to_ndev(wdev);\n#endif\n\t_adapter *adapter;\n\n\tstruct rtw_wdev_priv *pwdev_priv;\n\n\tif (ndev == NULL)\n\t\tgoto exit;\n\n\tadapter = (_adapter *)rtw_netdev_priv(ndev);\n\tpwdev_priv = adapter_wdev_data(adapter);\n\n#ifdef CONFIG_DEBUG_CFG80211\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))\n\tRTW_INFO(FUNC_ADPT_FMT\" frame_type:%x, reg:%d\\n\", FUNC_ADPT_ARG(adapter),\n\t\tframe_type, reg);\n#else\n\tRTW_INFO(FUNC_ADPT_FMT \" old_regs:%x new_regs:%x\\n\",\n\t\t FUNC_ADPT_ARG(adapter), pwdev_priv->mgmt_mask, upd->interface_stypes);\n#endif    \n#endif\n\n\t/* Wait QC Verify */\n\treturn;\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))\n\tswitch (frame_type) {\n\tcase IEEE80211_STYPE_AUTH: /* 0x00B0 */\n\t\tif (reg > 0)\n\t\t\tSET_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_AUTH, reg);\n\t\telse\n\t\t\tCLR_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_AUTH, reg);\n\t\tbreak;\n\tcase IEEE80211_STYPE_PROBE_REQ: /* 0x0040 */\n\t\tif (reg > 0)\n\t\t\tSET_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_PROBE_REQ, reg);\n\t\telse\n\t\t\tCLR_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_PROBE_REQ, reg);\n\t\tbreak;\n\tcase IEEE80211_STYPE_ACTION: /* 0x00D0 */\n\t\tif (reg > 0)\n\t\t\tSET_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_ACTION, reg);\n\t\telse\n\t\t\tCLR_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_ACTION, reg);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n#else\n\tif ((upd->interface_stypes & rtw_mask) == (pwdev_priv->mgmt_mask & rtw_mask))\n \t\treturn;\n\n\tpwdev_priv->mgmt_mask = upd->interface_stypes;\n#endif\n\t\nexit:\n\treturn;\n}\n\n#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))\nstatic int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy,\n\tstruct net_device *ndev,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))\n\tconst u8 *peer,\n#else\n\tu8 *peer,\n#endif\n\tu8 action_code,\n\tu8 dialog_token,\n\tu16 status_code,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))\n\tu32 peer_capability,\n#endif\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0))\n\tbool initiator,\n#endif\n\tconst u8 *buf,\n\tsize_t len)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &pmlmeext->mlmext_info;\n\tint ret = 0;\n\tstruct tdls_txmgmt txmgmt;\n\n\tif (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) {\n\t\tRTW_INFO(\"Discard tdls action:%d, since hal doesn't support tdls\\n\", action_code);\n\t\tgoto discard;\n\t}\n\n\tif (rtw_is_tdls_enabled(padapter) == _FALSE) {\n\t\tRTW_INFO(\"TDLS is not enabled\\n\");\n\t\tgoto discard;\n\t}\n\n\tif (rtw_tdls_is_driver_setup(padapter)) {\n\t\tRTW_INFO(\"Discard tdls action:%d, let driver to set up direct link\\n\", action_code);\n\t\tgoto discard;\n\t}\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\t_rtw_memcpy(txmgmt.peer, peer, ETH_ALEN);\n\ttxmgmt.action_code = action_code;\n\ttxmgmt.dialog_token = dialog_token;\n\ttxmgmt.status_code = status_code;\n\ttxmgmt.len = len;\n\ttxmgmt.buf = (u8 *)rtw_malloc(txmgmt.len);\n\tif (txmgmt.buf == NULL) {\n\t\tret = -ENOMEM;\n\t\tgoto bad;\n\t}\n\t_rtw_memcpy(txmgmt.buf, (void *)buf, txmgmt.len);\n\n\t/* Debug purpose */\n#if 1\n\tRTW_INFO(\"%s %d\\n\", __FUNCTION__, __LINE__);\n\tRTW_INFO(\"peer:\"MAC_FMT\", action code:%d, dialog:%d, status code:%d\\n\",\n\t\tMAC_ARG(txmgmt.peer), txmgmt.action_code,\n\t\ttxmgmt.dialog_token, txmgmt.status_code);\n\tif (txmgmt.len > 0) {\n\t\tint i = 0;\n\t\tfor (; i < len; i++)\n\t\t\tprintk(\"%02x \", *(txmgmt.buf + i));\n\t\tRTW_INFO(\"len:%d\\n\", (u32)txmgmt.len);\n\t}\n#endif\n\n\tswitch (txmgmt.action_code) {\n\tcase TDLS_SETUP_REQUEST:\n\t\tissue_tdls_setup_req(padapter, &txmgmt, _TRUE);\n\t\tbreak;\n\tcase TDLS_SETUP_RESPONSE:\n\t\tissue_tdls_setup_rsp(padapter, &txmgmt);\n\t\tbreak;\n\tcase TDLS_SETUP_CONFIRM:\n\t\tissue_tdls_setup_cfm(padapter, &txmgmt);\n\t\tbreak;\n\tcase TDLS_TEARDOWN:\n\t\tissue_tdls_teardown(padapter, &txmgmt, _TRUE);\n\t\tbreak;\n\tcase TDLS_DISCOVERY_REQUEST:\n\t\tissue_tdls_dis_req(padapter, &txmgmt);\n\t\tbreak;\n\tcase TDLS_DISCOVERY_RESPONSE:\n\t\tissue_tdls_dis_rsp(padapter, &txmgmt, pmlmeinfo->enc_algo ? _TRUE : _FALSE);\n\t\tbreak;\n\t}\n\nbad:\n\tif (txmgmt.buf)\n\t\trtw_mfree(txmgmt.buf, txmgmt.len);\n\ndiscard:\n\treturn ret;\n}\n\nstatic int cfg80211_rtw_tdls_oper(struct wiphy *wiphy,\n\tstruct net_device *ndev,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))\n\tconst u8 *peer,\n#else\n\tu8 *peer,\n#endif\n\tenum nl80211_tdls_operation oper)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\tstruct tdls_txmgmt\ttxmgmt;\n\tstruct sta_info *ptdls_sta = NULL;\n\n\tRTW_INFO(FUNC_NDEV_FMT\", nl80211_tdls_operation:%d\\n\", FUNC_NDEV_ARG(ndev), oper);\n\n\tif (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) {\n\t\tRTW_INFO(\"Discard tdls oper:%d, since hal doesn't support tdls\\n\", oper);\n\t\treturn 0;\n\t}\n\n\tif (rtw_is_tdls_enabled(padapter) == _FALSE) {\n\t\tRTW_INFO(\"TDLS is not enabled\\n\");\n\t\treturn 0;\n\t}\n\n#ifdef CONFIG_LPS\n\trtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0);\n#endif /* CONFIG_LPS */\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\tif (peer)\n\t\t_rtw_memcpy(txmgmt.peer, peer, ETH_ALEN);\n\n\tif (rtw_tdls_is_driver_setup(padapter)) {\n\t\t/* these two cases are done by driver itself */\n\t\tif (oper == NL80211_TDLS_ENABLE_LINK || oper == NL80211_TDLS_DISABLE_LINK)\n\t\t\treturn 0;\n\t}\n\n\tswitch (oper) {\n\tcase NL80211_TDLS_DISCOVERY_REQ:\n\t\tissue_tdls_dis_req(padapter, &txmgmt);\n\t\tbreak;\n\tcase NL80211_TDLS_SETUP:\n#ifdef CONFIG_WFD\n\t\tif (_AES_ != padapter->securitypriv.dot11PrivacyAlgrthm) {\n\t\t\tif (padapter->wdinfo.wfd_tdls_weaksec == _TRUE)\n\t\t\t\tissue_tdls_setup_req(padapter, &txmgmt, _TRUE);\n\t\t\telse\n\t\t\t\tRTW_INFO(\"[%s] Current link is not AES, SKIP sending the tdls setup request!!\\n\", __FUNCTION__);\n\t\t} else\n#endif /* CONFIG_WFD */\n\t\t{\n\t\t\tissue_tdls_setup_req(padapter, &txmgmt, _TRUE);\n\t\t}\n\t\tbreak;\n\tcase NL80211_TDLS_TEARDOWN:\n\t\tptdls_sta = rtw_get_stainfo(&(padapter->stapriv), txmgmt.peer);\n\t\tif (ptdls_sta != NULL) {\n\t\t\ttxmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;\n\t\t\tissue_tdls_teardown(padapter, &txmgmt, _TRUE);\n\t\t} else\n\t\t\tRTW_INFO(\"TDLS peer not found\\n\");\n\t\tbreak;\n\tcase NL80211_TDLS_ENABLE_LINK:\n\t\tRTW_INFO(FUNC_NDEV_FMT\", NL80211_TDLS_ENABLE_LINK;mac:\"MAC_FMT\"\\n\", FUNC_NDEV_ARG(ndev), MAC_ARG(peer));\n\t\tptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer);\n\t\tif (ptdls_sta != NULL) {\n\t\t\trtw_tdls_set_link_established(padapter, _TRUE);\n\t\t\tptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE;\n\t\t\tptdls_sta->state |= _FW_LINKED;\n\t\t\trtw_tdls_cmd(padapter, txmgmt.peer, TDLS_ESTABLISHED);\n\t\t}\n\t\tbreak;\n\tcase NL80211_TDLS_DISABLE_LINK:\n\t\tRTW_INFO(FUNC_NDEV_FMT\", NL80211_TDLS_DISABLE_LINK;mac:\"MAC_FMT\"\\n\", FUNC_NDEV_ARG(ndev), MAC_ARG(peer));\n\t\tptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer);\n\t\tif (ptdls_sta != NULL) {\n\t\t\trtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);\n\t\t\trtw_tdls_cmd(padapter, (u8 *)peer, TDLS_TEARDOWN_STA_LOCALLY_POST);\n\t\t}\n\t\tbreak;\n\t}\n\treturn 0;\n}\n#endif /* CONFIG_TDLS */\n\n#if defined(CONFIG_RTW_MESH) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))\n\n#if DBG_RTW_CFG80211_MESH_CONF\n#define LEGACY_RATES_STR_LEN (RTW_G_RATES_NUM * 5 + 1)\nint get_legacy_rates_str(struct wiphy *wiphy, enum nl80211_band band, u32 mask, char *buf)\n{\n\tint i;\n\tint cnt = 0;\n\n\tfor (i = 0; i < wiphy->bands[band]->n_bitrates; i++) {\n\t\tif (mask & BIT(i)) {\n\t\t\tcnt += snprintf(buf + cnt, LEGACY_RATES_STR_LEN - cnt -1, \"%d.%d \"\n\t\t\t\t, wiphy->bands[band]->bitrates[i].bitrate / 10\n\t\t\t\t, wiphy->bands[band]->bitrates[i].bitrate % 10);\n\t\t\tif (cnt >= LEGACY_RATES_STR_LEN - 1)\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn cnt;\n}\n\nvoid dump_mesh_setup(void *sel, struct wiphy *wiphy, const struct mesh_setup *setup)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))\n\tstruct cfg80211_chan_def *chdef = (struct cfg80211_chan_def *)(&setup->chandef);\n#endif\n\tstruct ieee80211_channel *chan;\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))\n\tchan = (struct ieee80211_channel *)chdef->chan;\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\tchan = (struct ieee80211_channel *)setup->channel;\n#endif\n\n\tRTW_PRINT_SEL(sel, \"mesh_id:\\\"%s\\\", len:%u\\n\", setup->mesh_id, setup->mesh_id_len);\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))\n\tRTW_PRINT_SEL(sel, \"sync_method:%u\\n\", setup->sync_method);\n#endif\n\tRTW_PRINT_SEL(sel, \"path_sel_proto:%u, path_metric:%u\\n\", setup->path_sel_proto, setup->path_metric);\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))\n\tRTW_PRINT_SEL(sel, \"auth_id:%u\\n\", setup->auth_id);\n#endif\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))\n\tif (setup->ie && setup->ie_len) {\n\t\tRTW_PRINT_SEL(sel, \"ie:%p, len:%u\\n\", setup->ie, setup->ie_len);\n\t\tdump_ies(RTW_DBGDUMP, setup->ie, setup->ie_len);\n\t}\n#else\n\tif (setup->vendor_ie && setup->vendor_ie_len) {\n\t\tRTW_PRINT_SEL(sel, \"ie:%p, len:%u\\n\", setup->vendor_ie, setup->vendor_ie_len);\n\t\tdump_ies(RTW_DBGDUMP, setup->vendor_ie, setup->vendor_ie_len);\n\t}\n#endif\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))\n\tRTW_PRINT_SEL(sel, \"is_authenticated:%d, is_secure:%d\\n\", setup->is_authenticated, setup->is_secure);\n#endif\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))\n\tRTW_PRINT_SEL(sel, \"user_mpm:%d\\n\", setup->user_mpm);\n#endif\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))\n\tRTW_PRINT_SEL(sel, \"dtim_period:%u, beacon_interval:%u\\n\", setup->dtim_period, setup->beacon_interval);\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))\n\tRTW_PRINT_SEL(sel, \"center_freq:%u, ch:%u, width:%s, cfreq1:%u, cfreq2:%u\\n\"\n\t\t, chan->center_freq, chan->hw_value, nl80211_chan_width_str(chdef->width), chdef->center_freq1, chdef->center_freq2);\n#else\n\tRTW_PRINT_SEL(sel, \"center_freq:%u, ch:%u, channel_type:%s\\n\"\n\t\t, chan->center_freq, chan->hw_value, nl80211_channel_type_str(setup->channel_type));\n#endif\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))\n\tif (setup->mcast_rate[chan->band]) {\n\t\tRTW_PRINT_SEL(sel, \"mcast_rate:%d.%d\\n\"\n\t\t\t, wiphy->bands[chan->band]->bitrates[setup->mcast_rate[chan->band] - 1].bitrate / 10\n\t\t\t, wiphy->bands[chan->band]->bitrates[setup->mcast_rate[chan->band] - 1].bitrate % 10\n\t\t);\n\t}\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))\n\tif (setup->basic_rates) {\n\t\tchar buf[LEGACY_RATES_STR_LEN] = {0};\n\n\t\tget_legacy_rates_str(wiphy, chan->band, setup->basic_rates, buf);\n\t\tRTW_PRINT_SEL(sel, \"basic_rates:%s\\n\", buf);\n\t}\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0))\n\tif (setup->beacon_rate.control[chan->band].legacy) {\n\t\tchar buf[LEGACY_RATES_STR_LEN] = {0};\n\n\t\tget_legacy_rates_str(wiphy, chan->band, setup->beacon_rate.control[chan->band].legacy, buf);\n\t\tRTW_PRINT_SEL(sel, \"beacon_rate.legacy:%s\\n\", buf);\n\t}\n\tif (*((u32 *)&(setup->beacon_rate.control[chan->band].ht_mcs[0]))\n\t\t|| *((u32 *)&(setup->beacon_rate.control[chan->band].ht_mcs[4]))\n\t\t|| *((u16 *)&(setup->beacon_rate.control[chan->band].ht_mcs[8]))\n\t) {\n\t\tRTW_PRINT_SEL(sel, \"beacon_rate.ht_mcs:\"HT_RX_MCS_BMP_FMT\"\\n\"\n\t\t\t, HT_RX_MCS_BMP_ARG(setup->beacon_rate.control[chan->band].ht_mcs));\n\t}\n\n\tif (setup->beacon_rate.control[chan->band].vht_mcs[0]\n\t\t|| setup->beacon_rate.control[chan->band].vht_mcs[1]\n\t\t|| setup->beacon_rate.control[chan->band].vht_mcs[2]\n\t\t|| setup->beacon_rate.control[chan->band].vht_mcs[3]\n\t) {\n\t\tint i;\n\n\t\tfor (i = 0; i < 4; i++) {/* parsing up to 4SS */\n\t\t\tu16 mcs_mask = setup->beacon_rate.control[chan->band].vht_mcs[i];\n\n\t\t\tRTW_PRINT_SEL(sel, \"beacon_rate.vht_mcs[%d]:%s\\n\", i\n\t\t\t\t, mcs_mask == 0x00FF ? \"0~7\" : mcs_mask == 0x01FF ? \"0~8\" : mcs_mask == 0x03FF ? \"0~9\" : \"invalid\");\n\t\t}\n\t}\n\n\tif (setup->beacon_rate.control[chan->band].gi) {\n\t\tRTW_PRINT_SEL(sel, \"beacon_rate.gi:%s\\n\"\n\t\t\t, setup->beacon_rate.control[chan->band].gi == NL80211_TXRATE_FORCE_SGI ? \"SGI\" :\n\t\t\t\tsetup->beacon_rate.control[chan->band].gi == NL80211_TXRATE_FORCE_LGI ? \"LGI\" : \"invalid\"\n\t\t);\n\t}\n#endif\n}\n\nvoid dump_mesh_config(void *sel, const struct mesh_config *conf)\n{\n\tRTW_PRINT_SEL(sel, \"dot11MeshRetryTimeout:%u\\n\", conf->dot11MeshRetryTimeout);\n\tRTW_PRINT_SEL(sel, \"dot11MeshConfirmTimeout:%u\\n\", conf->dot11MeshConfirmTimeout);\n\tRTW_PRINT_SEL(sel, \"dot11MeshHoldingTimeout:%u\\n\", conf->dot11MeshHoldingTimeout);\n\tRTW_PRINT_SEL(sel, \"dot11MeshMaxPeerLinks:%u\\n\", conf->dot11MeshMaxPeerLinks);\n\tRTW_PRINT_SEL(sel, \"dot11MeshMaxRetries:%u\\n\", conf->dot11MeshMaxRetries);\n\tRTW_PRINT_SEL(sel, \"dot11MeshTTL:%u\\n\", conf->dot11MeshTTL);\n\tRTW_PRINT_SEL(sel, \"element_ttl:%u\\n\", conf->element_ttl);\n\tRTW_PRINT_SEL(sel, \"auto_open_plinks:%d\\n\", conf->auto_open_plinks);\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))\n\tRTW_PRINT_SEL(sel, \"dot11MeshNbrOffsetMaxNeighbor:%u\\n\", conf->dot11MeshNbrOffsetMaxNeighbor);\n#endif\n\n\tRTW_PRINT_SEL(sel, \"dot11MeshHWMPmaxPREQretries:%u\\n\", conf->dot11MeshHWMPmaxPREQretries);\n\tRTW_PRINT_SEL(sel, \"path_refresh_time:%u\\n\", conf->path_refresh_time);\n\tRTW_PRINT_SEL(sel, \"min_discovery_timeout:%u\\n\", conf->min_discovery_timeout);\n\tRTW_PRINT_SEL(sel, \"dot11MeshHWMPactivePathTimeout:%u\\n\", conf->dot11MeshHWMPactivePathTimeout);\n\tRTW_PRINT_SEL(sel, \"dot11MeshHWMPpreqMinInterval:%u\\n\", conf->dot11MeshHWMPpreqMinInterval);\t\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))\n\tRTW_PRINT_SEL(sel, \"dot11MeshHWMPperrMinInterval:%u\\n\", conf->dot11MeshHWMPperrMinInterval);\n#endif\n\tRTW_PRINT_SEL(sel, \"dot11MeshHWMPnetDiameterTraversalTime:%u\\n\", conf->dot11MeshHWMPnetDiameterTraversalTime);\n\tRTW_PRINT_SEL(sel, \"dot11MeshHWMPRootMode:%u\\n\", conf->dot11MeshHWMPRootMode);\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))\n\tRTW_PRINT_SEL(sel, \"dot11MeshHWMPRannInterval:%u\\n\", conf->dot11MeshHWMPRannInterval);\n\tRTW_PRINT_SEL(sel, \"dot11MeshGateAnnouncementProtocol:%d\\n\", conf->dot11MeshGateAnnouncementProtocol);\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))\n\tRTW_PRINT_SEL(sel, \"dot11MeshForwarding:%d\\n\", conf->dot11MeshForwarding);\n\tRTW_PRINT_SEL(sel, \"rssi_threshold:%d\\n\", conf->rssi_threshold);\n#endif\n\t\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))\n\tRTW_PRINT_SEL(sel, \"ht_opmode:0x%04x\\n\", conf->ht_opmode);\n#endif\n\t\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\tRTW_PRINT_SEL(sel, \"dot11MeshHWMPactivePathToRootTimeout:%u\\n\", conf->dot11MeshHWMPactivePathToRootTimeout);\n\tRTW_PRINT_SEL(sel, \"dot11MeshHWMProotInterval:%u\\n\", conf->dot11MeshHWMProotInterval);\n\tRTW_PRINT_SEL(sel, \"dot11MeshHWMPconfirmationInterval:%u\\n\", conf->dot11MeshHWMPconfirmationInterval);\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))\n\tRTW_PRINT_SEL(sel, \"power_mode:%s\\n\", nl80211_mesh_power_mode_str(conf->power_mode));\n\tRTW_PRINT_SEL(sel, \"dot11MeshAwakeWindowDuration:%u\\n\", conf->dot11MeshAwakeWindowDuration);\n#endif\n\t\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))\n\tRTW_PRINT_SEL(sel, \"plink_timeout:%u\\n\", conf->plink_timeout);\n#endif\n}\n#endif /* DBG_RTW_CFG80211_MESH_CONF */\n\nstatic void rtw_cfg80211_mesh_info_set_profile(struct rtw_mesh_info *minfo, const struct mesh_setup *setup)\n{\n\t_rtw_memcpy(minfo->mesh_id, setup->mesh_id, setup->mesh_id_len);\n\tminfo->mesh_id_len = setup->mesh_id_len;\n\tminfo->mesh_pp_id = setup->path_sel_proto;\n\tminfo->mesh_pm_id = setup->path_metric;\n\tminfo->mesh_cc_id = 0;\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))\n\tminfo->mesh_sp_id = setup->sync_method;\n#endif\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))\n\tminfo->mesh_auth_id = setup->auth_id;\n#else\n\tif (setup->is_authenticated) {\n\t\tu8 *rsn_ie;\n\t\tsint rsn_ie_len;\n\t\tstruct rsne_info info;\n\t\tu8 *akm;\n\t\tu8 AKM_SUITE_SAE[4] = {0x00, 0x0F, 0xAC, 0x08};\n\n\t\trsn_ie = rtw_get_ie(setup->ie, WLAN_EID_RSN, &rsn_ie_len, setup->ie_len);\n\t\tif (!rsn_ie || !rsn_ie_len) {\n\t\t\trtw_warn_on(1);\n\t\t\treturn;\n\t\t}\n\n\t\tif (rtw_rsne_info_parse(rsn_ie, rsn_ie_len + 2, &info) != _SUCCESS) {\n\t\t\trtw_warn_on(1);\n\t\t\treturn;\n\t\t}\n\n\t\tif (!info.akm_list || !info.akm_cnt) {\n\t\t\trtw_warn_on(1);\n\t\t\treturn;\n\t\t}\n\n\t\takm = info.akm_list;\n\t\twhile (akm < info.akm_list + info.akm_cnt * 4) {\n\t\t\tif (_rtw_memcmp(akm, AKM_SUITE_SAE, 4) == _TRUE) {\n\t\t\t\tminfo->mesh_auth_id = 0x01;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tif (!minfo->mesh_auth_id) {\n\t\t\trtw_warn_on(1);\n\t\t\treturn;\n\t\t}\n\t}\n#endif\n}\n\nstatic inline bool chk_mesh_attr(enum nl80211_meshconf_params parm, u32 mask)\n{\n\treturn (mask >> (parm - 1)) & 0x1;\n}\n\nstatic void rtw_cfg80211_mesh_cfg_set(_adapter *adapter, const struct mesh_config *conf, u32 mask)\n{\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\n#if 0 /* driver MPM */\n\tif (chk_mesh_attr(NL80211_MESHCONF_RETRY_TIMEOUT, mask));\n\tif (chk_mesh_attr(NL80211_MESHCONF_CONFIRM_TIMEOUT, mask));\n\tif (chk_mesh_attr(NL80211_MESHCONF_HOLDING_TIMEOUT, mask));\n\tif (chk_mesh_attr(NL80211_MESHCONF_MAX_PEER_LINKS, mask));\n\tif (chk_mesh_attr(NL80211_MESHCONF_MAX_RETRIES, mask));\n#endif\n\n\tif (chk_mesh_attr(NL80211_MESHCONF_TTL, mask))\n\t\tmcfg->dot11MeshTTL = conf->dot11MeshTTL;\n\tif (chk_mesh_attr(NL80211_MESHCONF_ELEMENT_TTL, mask))\n\t\tmcfg->element_ttl = conf->element_ttl;\n\n#if 0 /* driver MPM */\n\tif (chk_mesh_attr(NL80211_MESHCONF_AUTO_OPEN_PLINKS, mask));\n#endif\n\n#if 0 /* TBD: synchronization */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))\n\tif (chk_mesh_attr(NL80211_MESHCONF_SYNC_OFFSET_MAX_NEIGHBOR, mask));\n#endif\n#endif\n\n\tif (chk_mesh_attr(NL80211_MESHCONF_HWMP_MAX_PREQ_RETRIES, mask))\n\t\tmcfg->dot11MeshHWMPmaxPREQretries = conf->dot11MeshHWMPmaxPREQretries;\n\tif (chk_mesh_attr(NL80211_MESHCONF_PATH_REFRESH_TIME, mask))\n\t\tmcfg->path_refresh_time = conf->path_refresh_time;\n\tif (chk_mesh_attr(NL80211_MESHCONF_MIN_DISCOVERY_TIMEOUT, mask))\n\t\tmcfg->min_discovery_timeout = conf->min_discovery_timeout;\n\tif (chk_mesh_attr(NL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT, mask))\n\t\tmcfg->dot11MeshHWMPactivePathTimeout = conf->dot11MeshHWMPactivePathTimeout;\n\tif (chk_mesh_attr(NL80211_MESHCONF_HWMP_PREQ_MIN_INTERVAL, mask))\n\t\tmcfg->dot11MeshHWMPpreqMinInterval = conf->dot11MeshHWMPpreqMinInterval;\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))\n\tif (chk_mesh_attr(NL80211_MESHCONF_HWMP_PERR_MIN_INTERVAL, mask))\n\t\tmcfg->dot11MeshHWMPperrMinInterval = conf->dot11MeshHWMPperrMinInterval;\n#endif\n\tif (chk_mesh_attr(NL80211_MESHCONF_HWMP_NET_DIAM_TRVS_TIME, mask))\n\t\tmcfg->dot11MeshHWMPnetDiameterTraversalTime = conf->dot11MeshHWMPnetDiameterTraversalTime;\n\n\tif (chk_mesh_attr(NL80211_MESHCONF_HWMP_ROOTMODE, mask))\n\t\tmcfg->dot11MeshHWMPRootMode = conf->dot11MeshHWMPRootMode;\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))\n\tif (chk_mesh_attr(NL80211_MESHCONF_GATE_ANNOUNCEMENTS, mask))\n\t\tmcfg->dot11MeshGateAnnouncementProtocol = conf->dot11MeshGateAnnouncementProtocol;\n\t/* our current gate annc implementation rides on root annc with gate annc bit in PREQ flags */\n\tif (mcfg->dot11MeshGateAnnouncementProtocol\n\t\t&& mcfg->dot11MeshHWMPRootMode <= RTW_IEEE80211_ROOTMODE_ROOT\n\t) {\n\t\tmcfg->dot11MeshHWMPRootMode = RTW_IEEE80211_PROACTIVE_RANN;\n\t\tRTW_INFO(ADPT_FMT\" enable PROACTIVE_RANN becaue gate annc is needed\\n\", ADPT_ARG(adapter));\n\t}\n\tif (chk_mesh_attr(NL80211_MESHCONF_HWMP_RANN_INTERVAL, mask))\n\t\tmcfg->dot11MeshHWMPRannInterval = conf->dot11MeshHWMPRannInterval;\n#endif\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))\n\tif (chk_mesh_attr(NL80211_MESHCONF_FORWARDING, mask))\n\t\tmcfg->dot11MeshForwarding = conf->dot11MeshForwarding;\n\n\tif (chk_mesh_attr(NL80211_MESHCONF_RSSI_THRESHOLD, mask))\n\t\tmcfg->rssi_threshold = conf->rssi_threshold;\n#endif\n\n#if 0 /* controlled by driver */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))\n\tif (chk_mesh_attr(NL80211_MESHCONF_HT_OPMODE, mask));\n#endif\n#endif\n\t\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\tif (chk_mesh_attr(NL80211_MESHCONF_HWMP_PATH_TO_ROOT_TIMEOUT, mask))\n\t\tmcfg->dot11MeshHWMPactivePathToRootTimeout = conf->dot11MeshHWMPactivePathToRootTimeout;\n\tif (chk_mesh_attr(NL80211_MESHCONF_HWMP_ROOT_INTERVAL, mask))\n\t\tmcfg->dot11MeshHWMProotInterval = conf->dot11MeshHWMProotInterval;\n\tif (chk_mesh_attr(NL80211_MESHCONF_HWMP_CONFIRMATION_INTERVAL, mask))\n\t\tmcfg->dot11MeshHWMPconfirmationInterval = conf->dot11MeshHWMPconfirmationInterval;\t\n#endif\n\n#if 0 /* TBD */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))\n\tif (chk_mesh_attr(NL80211_MESHCONF_POWER_MODE, mask));\n\tif (chk_mesh_attr(NL80211_MESHCONF_AWAKE_WINDOW, mask));\n#endif\n#endif\n\n#if 0 /* driver MPM */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))\n\tif (chk_mesh_attr(NL80211_MESHCONF_PLINK_TIMEOUT, mask));\n#endif\n#endif\n}\n\nu8 *rtw_cfg80211_construct_mesh_beacon_ies(struct wiphy *wiphy, _adapter *adapter\n\t, const struct mesh_config *conf, const struct mesh_setup *setup\n\t, uint *ies_len)\n{\n\tstruct rtw_mesh_info *minfo = &adapter->mesh_info;\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))\n\tstruct cfg80211_chan_def *chdef = (struct cfg80211_chan_def *)(&setup->chandef);\n#endif\n\tstruct ieee80211_channel *chan;\n\tu8 ch, bw, offset;\n#endif\n\tuint len;\n\tu8 n_bitrates;\n\tu8 ht = 0;\n\tu8 vht = 0;\n\tu8 *rsn_ie = NULL;\n\tsint rsn_ie_len = 0;\n\tu8 *ies = NULL, *c;\n\tu8 supported_rates[RTW_G_RATES_NUM] = {0};\n\tint i;\n\n\t*ies_len = 0;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))\n\tchan = (struct ieee80211_channel *)chdef->chan;\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\tchan = (struct ieee80211_channel *)setup->channel;\n#endif\n\n\tn_bitrates = wiphy->bands[chan->band]->n_bitrates;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))\n\trtw_get_chbw_from_cfg80211_chan_def(chdef, &ht, &ch, &bw, &offset);\n#else\n\trtw_get_chbw_from_nl80211_channel_type(chan, setup->channel_type, &ht, &ch, &bw, &offset);\n#endif\n\tif (!ch)\n\t\tgoto exit;\n\t\n#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\tvht = ht && ch > 14 && bw >= CHANNEL_WIDTH_80; /* VHT40/VHT20? */\n#endif\n\n\tRTW_INFO(FUNC_ADPT_FMT\" => ch:%u,%u,%u, ht:%u, vht:%u\\n\"\n\t\t, FUNC_ADPT_ARG(adapter), ch, bw, offset, ht, vht);\n#endif\n\n\trsn_ie = rtw_get_ie(setup->ie, WLAN_EID_RSN, &rsn_ie_len, setup->ie_len);\n\tif (rsn_ie && !rsn_ie_len) {\n\t\trtw_warn_on(1);\n\t\trsn_ie = NULL;\n\t}\n\n\tlen = _BEACON_IE_OFFSET_\n\t\t+ 2 /* 0-length SSID */\n\t\t+ (n_bitrates >= 8 ? 8 : n_bitrates) + 2 /* Supported Rates */\n\t\t+ 3 /* DS parameter set */\n\t\t+ 6 /* TIM  */\n\t\t+ (n_bitrates > 8 ? n_bitrates - 8 + 2 : 0) /* Extended Supported Rates */\n\t\t+ (rsn_ie ? rsn_ie_len + 2 : 0) /* RSN */\n\t\t#if defined(CONFIG_80211N_HT)\n\t\t+ (ht ? HT_CAP_IE_LEN + 2 + HT_OP_IE_LEN + 2 : 0) /* HT */\n\t\t#endif\n\t\t#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\t\t+ (vht ? VHT_CAP_IE_LEN + 2 + VHT_OP_IE_LEN + 2 : 0) /* VHT */\n\t\t#endif\n\t\t+ minfo->mesh_id_len + 2 /* Mesh ID */\n\t\t+ 9 /* Mesh configuration */\n\t\t;\n\n\ties = rtw_zmalloc(len);\n\tif (!ies)\n\t\tgoto exit;\n\n\t/* timestamp */\n\tc = ies + 8;\n\n\t/* beacon interval */\n\tRTW_PUT_LE16(c , setup->beacon_interval);\n\tc += 2;\n\n\t/* capability */\n\tif (rsn_ie)\n\t\t*((u16 *)c) |= cpu_to_le16(cap_Privacy);\n\tc += 2;\n\n\t/* SSID */\n\tc = rtw_set_ie(c, WLAN_EID_SSID, 0, NULL, NULL);\n\n\t/* Supported Rates */\n\tfor (i = 0; i < n_bitrates; i++) {\n\t\tsupported_rates[i] = wiphy->bands[chan->band]->bitrates[i].bitrate / 5;\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))\n\t\tif (setup->basic_rates & BIT(i))\n\t\t#else\n\t\tif (rtw_is_basic_rate_mix(supported_rates[i]))\n\t\t#endif\n\t\t\tsupported_rates[i] |= IEEE80211_BASIC_RATE_MASK;\n\t}\n\tc = rtw_set_ie(c, WLAN_EID_SUPP_RATES, (n_bitrates >= 8 ? 8 : n_bitrates), supported_rates, NULL);\n\n\t/* DS parameter set */\n\tc = rtw_set_ie(c, WLAN_EID_DS_PARAMS, 1, &ch, NULL);\n\n\t/* TIM */\n\t*c = WLAN_EID_TIM;\n\t*(c + 1) = 4;\n\tc += 6;\n\t//c = rtw_set_ie(c, _TIM_IE_, 4, NULL, NULL);\n\n\t/* Extended Supported Rates */\n\tif (n_bitrates > 8)\n\t\tc = rtw_set_ie(c, WLAN_EID_EXT_SUPP_RATES, n_bitrates - 8, supported_rates + 8, NULL);\n\n\t/* RSN */\n\tif (rsn_ie)\n\t\tc = rtw_set_ie(c, WLAN_EID_RSN, rsn_ie_len, rsn_ie + 2, NULL);\n\n#if defined(CONFIG_80211N_HT)\n\tif (ht) {\n\t\tstruct ieee80211_sta_ht_cap *sta_ht_cap = &wiphy->bands[chan->band]->ht_cap;\n\t\tu8 ht_cap[HT_CAP_IE_LEN];\n\t\tu8 ht_op[HT_OP_IE_LEN];\n\n\t\t_rtw_memset(ht_cap, 0, HT_CAP_IE_LEN);\n\t\t_rtw_memset(ht_op, 0, HT_OP_IE_LEN);\n\n\t\t/* WLAN_EID_HT_CAP */\n\t\tRTW_PUT_LE16(HT_CAP_ELE_CAP_INFO(ht_cap), sta_ht_cap->cap);\n\t\tSET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(ht_cap, sta_ht_cap->ampdu_factor);\n\t\tSET_HT_CAP_ELE_MIN_MPDU_S_SPACE(ht_cap, sta_ht_cap->ampdu_density);\n\t\t_rtw_memcpy(HT_CAP_ELE_SUP_MCS_SET(ht_cap), &sta_ht_cap->mcs, 16);\n\t\tc = rtw_set_ie(c, WLAN_EID_HT_CAP, HT_CAP_IE_LEN, ht_cap, NULL);\n\n\t\t/* WLAN_EID_HT_OPERATION */\n\t\tSET_HT_OP_ELE_PRI_CHL(ht_op, ch);\n\t\tswitch (offset) {\n\t\tcase HAL_PRIME_CHNL_OFFSET_LOWER:\n\t\t\tSET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCA);\n\t\t\tbreak;\n\t\tcase HAL_PRIME_CHNL_OFFSET_UPPER:\n\t\t\tSET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCB);\n\t\t\tbreak;\n\t\tcase HAL_PRIME_CHNL_OFFSET_DONT_CARE:\n\t\tdefault:\n\t\t\tSET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCN);\n\t\t\tbreak;\n\t\t}\n\t\tif (bw >= CHANNEL_WIDTH_40)\n\t\t\tSET_HT_OP_ELE_STA_CHL_WIDTH(ht_op, 1);\n\t\telse\n\t\t\tSET_HT_OP_ELE_STA_CHL_WIDTH(ht_op, 0);\n\t\tc = rtw_set_ie(c, WLAN_EID_HT_OPERATION, HT_OP_IE_LEN, ht_op, NULL);\n\t}\n#endif /* defined(CONFIG_80211N_HT) */\n\n#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\tif (vht) {\n\t\tstruct ieee80211_sta_vht_cap *sta_vht_cap = &wiphy->bands[chan->band]->vht_cap;\n\t\tu8 vht_cap[VHT_CAP_IE_LEN];\n\t\tu8 vht_op[VHT_OP_IE_LEN];\n\t\tu8 cch = rtw_get_center_ch(ch, bw, offset);\n\n\t\t_rtw_memset(vht_op, 0, VHT_OP_IE_LEN);\n\n\t\t/* WLAN_EID_VHT_CAPABILITY */\n\t\t_rtw_memcpy(vht_cap, &sta_vht_cap->cap, 4);\n\t\t_rtw_memcpy(vht_cap + 4, &sta_vht_cap->vht_mcs, 8);\n\t\tc = rtw_set_ie(c, WLAN_EID_VHT_CAPABILITY, VHT_CAP_IE_LEN, vht_cap, NULL);\n\n\t\t/* WLAN_EID_VHT_OPERATION */\n\t\tif (bw < CHANNEL_WIDTH_80) {\n\t\t\tSET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op, 0);\n\t\t\tSET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op, 0);\n\t\t\tSET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op, 0);\n\t\t} else if (bw == CHANNEL_WIDTH_80) {\n\t\t\tSET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op, 1);\n\t\t\tSET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op, cch);\n\t\t\tSET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op, 0);\n\t\t} else {\n\t\t\tRTW_ERR(FUNC_ADPT_FMT\" unsupported BW:%u\\n\", FUNC_ADPT_ARG(adapter), bw);\n\t\t\trtw_warn_on(1);\n\t\t\trtw_mfree(ies, len);\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* Hard code 1 stream, MCS0-7 is a min Basic VHT MCS rates */\n\t\tvht_op[3] = 0xfc;\n\t\tvht_op[4] = 0xff;\n\t\tc = rtw_set_ie(c, WLAN_EID_VHT_OPERATION, VHT_OP_IE_LEN, vht_op, NULL);\n\t}\n#endif /* defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) */\n\n\t/* Mesh ID */\n\tc = rtw_set_ie_mesh_id(c, NULL, minfo->mesh_id, minfo->mesh_id_len);\n\n\t/* Mesh configuration */\n\tc = rtw_set_ie_mesh_config(c, NULL\n\t\t, minfo->mesh_pp_id\n\t\t, minfo->mesh_pm_id\n\t\t, minfo->mesh_cc_id\n\t\t, minfo->mesh_sp_id\n\t\t, minfo->mesh_auth_id\n\t\t, 0, 0, 0\n\t\t, 1\n\t\t, 0, 0\n\t\t, mcfg->dot11MeshForwarding\n\t\t, 0, 0, 0\n\t);\n\n#if DBG_RTW_CFG80211_MESH_CONF\n\tRTW_INFO(FUNC_ADPT_FMT\" ies_len:%u\\n\", FUNC_ADPT_ARG(adapter), len);\n\tdump_ies(RTW_DBGDUMP, ies + _BEACON_IE_OFFSET_, len - _BEACON_IE_OFFSET_);\n#endif\n\nexit:\n\tif (ies)\n\t\t*ies_len = len;\n\treturn ies;\n}\n\nstatic int cfg80211_rtw_get_mesh_config(struct wiphy *wiphy, struct net_device *dev\n\t, struct mesh_config *conf)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rtw_mesh_cfg *mesh_cfg = &adapter->mesh_cfg;\n\tint ret = 0;\n\n\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(adapter));\n\n\t/* driver MPM */\n\tconf->dot11MeshRetryTimeout = 0;\n\tconf->dot11MeshConfirmTimeout = 0;\n\tconf->dot11MeshHoldingTimeout = 0;\n\tconf->dot11MeshMaxPeerLinks = mesh_cfg->max_peer_links;\n\tconf->dot11MeshMaxRetries = 0;\n\n\tconf->dot11MeshTTL = mesh_cfg->dot11MeshTTL;\n\tconf->element_ttl = mesh_cfg->element_ttl;\n\n\t/* driver MPM */\n\tconf->auto_open_plinks = 0;\n\n\t/* TBD: synchronization */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))\n\tconf->dot11MeshNbrOffsetMaxNeighbor = 0;\n#endif\n\n\tconf->dot11MeshHWMPmaxPREQretries = mesh_cfg->dot11MeshHWMPmaxPREQretries;\n\tconf->path_refresh_time = mesh_cfg->path_refresh_time;\n\tconf->min_discovery_timeout = mesh_cfg->min_discovery_timeout;\n\tconf->dot11MeshHWMPactivePathTimeout = mesh_cfg->dot11MeshHWMPactivePathTimeout;\n\tconf->dot11MeshHWMPpreqMinInterval = mesh_cfg->dot11MeshHWMPpreqMinInterval;\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))\n\tconf->dot11MeshHWMPperrMinInterval = mesh_cfg->dot11MeshHWMPperrMinInterval;\n#endif\n\tconf->dot11MeshHWMPnetDiameterTraversalTime = mesh_cfg->dot11MeshHWMPnetDiameterTraversalTime;\n\tconf->dot11MeshHWMPRootMode = mesh_cfg->dot11MeshHWMPRootMode;\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))\n\tconf->dot11MeshHWMPRannInterval = mesh_cfg->dot11MeshHWMPRannInterval;\n#endif\n\tconf->dot11MeshGateAnnouncementProtocol = mesh_cfg->dot11MeshGateAnnouncementProtocol;\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))\n\tconf->dot11MeshForwarding = mesh_cfg->dot11MeshForwarding;\n\tconf->rssi_threshold = mesh_cfg->rssi_threshold;\n#endif\n\n\t/* TBD */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))\n\tconf->ht_opmode = 0xffff;\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\tconf->dot11MeshHWMPactivePathToRootTimeout = mesh_cfg->dot11MeshHWMPactivePathToRootTimeout;\n\tconf->dot11MeshHWMProotInterval = mesh_cfg->dot11MeshHWMProotInterval;\n\tconf->dot11MeshHWMPconfirmationInterval = mesh_cfg->dot11MeshHWMPconfirmationInterval;\n#endif\n\n\t/* TBD: power save */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))\n\tconf->power_mode = NL80211_MESH_POWER_ACTIVE;\n\tconf->dot11MeshAwakeWindowDuration = 0;\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))\n\tconf->plink_timeout = mesh_cfg->plink_timeout;\n#endif\n\n\treturn ret;\n}\n\nstatic void rtw_mbss_info_change_notify(_adapter *adapter, bool minfo_changed, bool need_work)\n{\n\tif (need_work)\n\t\trtw_mesh_work(&adapter->mesh_work);\n}\n\nstatic int cfg80211_rtw_update_mesh_config(struct wiphy *wiphy, struct net_device *dev\n\t, u32 mask, const struct mesh_config *nconf)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tint ret = 0;\n\tbool minfo_changed = _FALSE, need_work = _FALSE;\n\n\tRTW_INFO(FUNC_ADPT_FMT\" mask:0x%08x\\n\", FUNC_ADPT_ARG(adapter), mask);\n\n\trtw_cfg80211_mesh_cfg_set(adapter, nconf, mask);\n\tupdate_beacon(adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE, 0);\n#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER\n\tif (rtw_mesh_cto_mgate_required(adapter))\n\t\trtw_netif_carrier_off(adapter->pnetdev);\n\telse\n\t\trtw_netif_carrier_on(adapter->pnetdev);\n#endif\n\tneed_work = rtw_ieee80211_mesh_root_setup(adapter);\n\n\trtw_mbss_info_change_notify(adapter, minfo_changed, need_work);\n\n\treturn ret;\n}\n\nstatic int cfg80211_rtw_join_mesh(struct wiphy *wiphy, struct net_device *dev,\n\tconst struct mesh_config *conf, const struct mesh_setup *setup)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8 *ies = NULL;\n\tuint ies_len;\n\tint ret = 0;\n\n\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(adapter));\n\n#if DBG_RTW_CFG80211_MESH_CONF\n\tRTW_INFO(FUNC_ADPT_FMT\" mesh_setup:\\n\", FUNC_ADPT_ARG(adapter));\n\tdump_mesh_setup(RTW_DBGDUMP, wiphy, setup);\n\tRTW_INFO(FUNC_ADPT_FMT\" mesh_config:\\n\", FUNC_ADPT_ARG(adapter));\n\tdump_mesh_config(RTW_DBGDUMP, conf);\n#endif\n\n\tif (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) {\n\t\tret = -ENOTSUPP;\n\t\tgoto exit;\n\t}\n\n\t/* initialization */\n\trtw_mesh_init_mesh_info(adapter);\n\n\t/* apply cfg80211 settings*/\n\trtw_cfg80211_mesh_info_set_profile(&adapter->mesh_info, setup);\n\trtw_cfg80211_mesh_cfg_set(adapter, conf, 0xFFFFFFFF);\n\n\t/* apply cfg80211 settings (join only) */\n\trtw_mesh_cfg_init_max_peer_links(adapter, conf->dot11MeshMaxPeerLinks);\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))\n\trtw_mesh_cfg_init_plink_timeout(adapter, conf->plink_timeout);\n\t#endif\n\n\trtw_ieee80211_mesh_root_setup(adapter);\n\n\ties = rtw_cfg80211_construct_mesh_beacon_ies(wiphy, adapter, conf, setup, &ies_len);\n\tif (!ies) {\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\n\t/* start mbss */\n\tif (rtw_check_beacon_data(adapter, ies,  ies_len) != _SUCCESS) {\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\t\n\trtw_mesh_work(&adapter->mesh_work);\n\nexit:\n\tif (ies)\n\t\trtw_mfree(ies, ies_len);\n\tif (ret)\n\t\trtw_mesh_deinit_mesh_info(adapter);\n\n\treturn ret;\n}\n\nstatic int cfg80211_rtw_leave_mesh(struct wiphy *wiphy, struct net_device *dev)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tint ret = 0;\n\n\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(adapter));\n\n\trtw_mesh_deinit_mesh_info(adapter);\n\n\trtw_set_802_11_infrastructure_mode(adapter, Ndis802_11Infrastructure);\n\trtw_setopmode_cmd(adapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK);\n\n\treturn ret;\n}\n\nstatic int cfg80211_rtw_add_mpath(struct wiphy *wiphy, struct net_device *dev\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))\n\t, const u8 *dst, const u8 *next_hop\n\t#else\n\t, u8 *dst, u8 *next_hop\n\t#endif\n)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct sta_info *sta;\n\tstruct rtw_mesh_path *mpath;\n\tint ret = 0;\n\n\trtw_rcu_read_lock();\n\n\tsta = rtw_get_stainfo(stapriv, next_hop);\n\tif (!sta) {\n\t\tret = -ENOENT;\n\t\tgoto exit;\n\t}\n\n\tmpath = rtw_mesh_path_add(adapter, dst);\n\tif (!mpath) {\n\t\tret = -ENOENT;\n\t\tgoto exit;\n\t}\n\n\trtw_mesh_path_fix_nexthop(mpath, sta);\n\nexit:\n\trtw_rcu_read_unlock();\n\n\treturn ret;\n}\n\nstatic int cfg80211_rtw_del_mpath(struct wiphy *wiphy, struct net_device *dev\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))\n\t, const u8 *dst\n\t#else\n\t, u8 *dst\n\t#endif\n)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tint ret = 0;\n\n\tif (dst) {\n\t\tif (rtw_mesh_path_del(adapter, dst)) {\n\t\t\tret = -ENOENT;\n\t\t\tgoto exit;\n\t\t}\n\t} else {\n\t\trtw_mesh_path_flush_by_iface(adapter);\n\t}\t\n\nexit:\n\treturn ret;\n}\n\nstatic int cfg80211_rtw_change_mpath(struct wiphy *wiphy, struct net_device *dev\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))\n\t, const u8 *dst, const u8 *next_hop\n\t#else\n\t, u8 *dst, u8 *next_hop\n\t#endif\n)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\tstruct sta_info *sta;\n\tstruct rtw_mesh_path *mpath;\n\tint ret = 0;\n\n\trtw_rcu_read_lock();\n\n\tsta = rtw_get_stainfo(stapriv, next_hop);\n\tif (!sta) {\n\t\tret = -ENOENT;\n\t\tgoto exit;\n\t}\n\n\tmpath = rtw_mesh_path_lookup(adapter, dst);\n\tif (!mpath) {\n\t\tret = -ENOENT;\n\t\tgoto exit;\n\t}\n\n\trtw_mesh_path_fix_nexthop(mpath, sta);\n\nexit:\n\trtw_rcu_read_unlock();\n\n\treturn ret;\n}\n\nstatic void rtw_cfg80211_mpath_set_pinfo(struct rtw_mesh_path *mpath, u8 *next_hop, struct mpath_info *pinfo)\n{\n\tstruct sta_info *next_hop_sta = rtw_rcu_dereference(mpath->next_hop);\n\n\tif (next_hop_sta)\n\t\t_rtw_memcpy(next_hop, next_hop_sta->cmn.mac_addr, ETH_ALEN);\n\telse\n\t\t_rtw_memset(next_hop, 0, ETH_ALEN);\n\n\t_rtw_memset(pinfo, 0, sizeof(*pinfo));\n\n\tpinfo->generation = mpath->adapter->mesh_info.mesh_paths_generation;\n\n\tpinfo->filled = 0\n\t\t| MPATH_INFO_FRAME_QLEN\n\t\t| MPATH_INFO_SN\n\t\t| MPATH_INFO_METRIC\n\t\t| MPATH_INFO_EXPTIME\n\t\t| MPATH_INFO_DISCOVERY_TIMEOUT\n\t\t| MPATH_INFO_DISCOVERY_RETRIES\n\t\t| MPATH_INFO_FLAGS\n\t\t;\n\n\tpinfo->frame_qlen = mpath->frame_queue_len;\n\tpinfo->sn = mpath->sn;\n\tpinfo->metric = mpath->metric;\n\tif (rtw_time_after(mpath->exp_time, rtw_get_current_time()))\n\t\tpinfo->exptime = rtw_get_remaining_time_ms(mpath->exp_time);\n\tpinfo->discovery_timeout = rtw_systime_to_ms(mpath->discovery_timeout);\n\tpinfo->discovery_retries = mpath->discovery_retries;\n\tif (mpath->flags & RTW_MESH_PATH_ACTIVE)\n\t\tpinfo->flags |= NL80211_MPATH_FLAG_ACTIVE;\n\tif (mpath->flags & RTW_MESH_PATH_RESOLVING)\n\t\tpinfo->flags |= NL80211_MPATH_FLAG_RESOLVING;\n\tif (mpath->flags & RTW_MESH_PATH_SN_VALID)\n\t\tpinfo->flags |= NL80211_MPATH_FLAG_SN_VALID;\n\tif (mpath->flags & RTW_MESH_PATH_FIXED)\n\t\tpinfo->flags |= NL80211_MPATH_FLAG_FIXED;\n\tif (mpath->flags & RTW_MESH_PATH_RESOLVED)\n\t\tpinfo->flags |= NL80211_MPATH_FLAG_RESOLVED;\n}\n\nstatic int cfg80211_rtw_get_mpath(struct wiphy *wiphy, struct net_device *dev, u8 *dst, u8 *next_hop, struct mpath_info *pinfo)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rtw_mesh_path *mpath;\n\tint ret = 0;\n\n\trtw_rcu_read_lock();\n\n\tmpath = rtw_mesh_path_lookup(adapter, dst);\n\tif (!mpath) {\n\t\tret = -ENOENT;\n\t\tgoto exit;\n\t}\n\n\trtw_cfg80211_mpath_set_pinfo(mpath, next_hop, pinfo);\n\nexit:\n\trtw_rcu_read_unlock();\n\n\treturn ret;\n}\n\nstatic int cfg80211_rtw_dump_mpath(struct wiphy *wiphy, struct net_device *dev, int idx, u8 *dst, u8 *next_hop, struct mpath_info *pinfo)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rtw_mesh_path *mpath;\n\tint ret = 0;\n\n\trtw_rcu_read_lock();\n\n\tmpath = rtw_mesh_path_lookup_by_idx(adapter, idx);\n\tif (!mpath) {\n\t\tret = -ENOENT;\n\t\tgoto exit;\n\t}\n\n\t_rtw_memcpy(dst, mpath->dst, ETH_ALEN);\n\trtw_cfg80211_mpath_set_pinfo(mpath, next_hop, pinfo);\n\nexit:\n\trtw_rcu_read_unlock();\n\n\treturn ret;\n}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))\nstatic void rtw_cfg80211_mpp_set_pinfo(struct rtw_mesh_path *mpath, u8 *mpp, struct mpath_info *pinfo)\n{\n\t_rtw_memcpy(mpp, mpath->mpp, ETH_ALEN);\n\n\t_rtw_memset(pinfo, 0, sizeof(*pinfo));\n\tpinfo->generation = mpath->adapter->mesh_info.mpp_paths_generation;\n}\n\nstatic int cfg80211_rtw_get_mpp(struct wiphy *wiphy, struct net_device *dev, u8 *dst, u8 *mpp, struct mpath_info *pinfo)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rtw_mesh_path *mpath;\n\tint ret = 0;\n\n\trtw_rcu_read_lock();\n\n\tmpath = rtw_mpp_path_lookup(adapter, dst);\n\tif (!mpath) {\n\t\tret = -ENOENT;\n\t\tgoto exit;\n\t}\n\n\trtw_cfg80211_mpp_set_pinfo(mpath, mpp, pinfo);\n\nexit:\n\trtw_rcu_read_unlock();\n\n\treturn ret;\n}\n\nstatic int cfg80211_rtw_dump_mpp(struct wiphy *wiphy, struct net_device *dev, int idx, u8 *dst, u8 *mpp, struct mpath_info *pinfo)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rtw_mesh_path *mpath;\n\tint ret = 0;\n\n\trtw_rcu_read_lock();\n\n\tmpath = rtw_mpp_path_lookup_by_idx(adapter, idx);\n\tif (!mpath) {\n\t\tret = -ENOENT;\n\t\tgoto exit;\n\t}\n\n\t_rtw_memcpy(dst, mpath->dst, ETH_ALEN);\n\trtw_cfg80211_mpp_set_pinfo(mpath, mpp, pinfo);\n\nexit:\n\trtw_rcu_read_unlock();\n\n\treturn ret;\n}\n#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) */\n\n#endif /* defined(CONFIG_RTW_MESH) */\n\n#if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))\nstatic int cfg80211_rtw_sched_scan_start(struct wiphy *wiphy,\n\t\tstruct net_device *dev,\n\t\tstruct cfg80211_sched_scan_request *request)\n{\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tstruct cfg80211_ssid *ssids;\n\tint n_ssids = 0;\n\tint interval = 0;\n\tint i = 0;\n\tu8 ret;\n\n\tif (padapter->bup == _FALSE) {\n\t\tRTW_INFO(\"%s: net device is down.\\n\", __func__);\n\t\treturn -EIO;\n\t}\n\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE ||\n\t\tcheck_fwstate(pmlmepriv, _FW_LINKED) == _TRUE  ||\n\t\tcheck_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) {\n\t\tRTW_INFO(\"%s: device is busy.\\n\", __func__);\n\t\trtw_scan_abort(padapter);\n\t}\n\n\tif (request == NULL) {\n\t\tRTW_INFO(\"%s: invalid cfg80211_requests parameters.\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)\n\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)\n\tinterval = request->scan_plans->interval;\n#else\n\tinterval = request->interval;\n#endif\n\tn_ssids = request->n_match_sets;\n\tssids = (struct cfg80211_ssid *)rtw_zmalloc(n_ssids * sizeof(struct cfg80211_ssid));\n\tif(ssids == NULL) {\n\t\tRTW_ERR(\"Fail to allocate ssids for PNO\\n\");\n\t\treturn -ENOMEM;\n\t}\n\tfor (i=0;i<request->n_match_sets;i++) {\n\t\t\tssids[i].ssid_len = request->match_sets[i].ssid.ssid_len;\n\t\t\tmemcpy(ssids[i].ssid, request->match_sets[i].ssid.ssid,\n\t\t\t\t\trequest->match_sets[i].ssid.ssid_len);\n\t}\n#else\n\tinterval = request->interval;\n\tn_ssids = request->n_ssids;\n\tssids = request->ssids;\n#endif\nret = rtw_android_cfg80211_pno_setup(dev, ssids,\n\t\t\tn_ssids, interval);\n\tif (ret < 0) {\n\t\tRTW_INFO(\"%s ret: %d\\n\", __func__, ret);\n\t\tgoto exit;\n\t}\n\n\tret = rtw_android_pno_enable(dev, _TRUE);\n\tif (ret < 0) {\n\t\tRTW_INFO(\"%s ret: %d\\n\", __func__, ret);\n\t\tgoto exit;\n\t}\nexit:\n\treturn ret;\n}\n\nstatic int cfg80211_rtw_sched_scan_stop(struct wiphy *wiphy,\n\t\tstruct net_device *dev)\n{\n\treturn rtw_android_pno_enable(dev, _FALSE);\n}\n\nint\tcfg80211_rtw_suspend(struct wiphy *wiphy, struct cfg80211_wowlan *wow) {\n\tRTW_DBG(\"==> %s\\n\",__func__);\n\tRTW_DBG(\"<== %s\\n\",__func__);\n\treturn 0;\n}\n\nint\tcfg80211_rtw_resume(struct wiphy *wiphy) {\n\n\t_adapter *padapter;\n\tstruct pwrctrl_priv *pwrpriv;\n\tstruct mlme_priv *pmlmepriv;\n\tpadapter = wiphy_to_adapter(wiphy);\n\tpwrpriv = adapter_to_pwrctl(padapter);\n\tpmlmepriv = &padapter->mlmepriv;\n\tstruct sitesurvey_parm parm;\n\tint i, len;\n\n\n\tRTW_DBG(\"==> %s\\n\",__func__);\n\tif (pwrpriv->wowlan_last_wake_reason == RX_PNO) {\n\n\t\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n\t\t_irqL irqL;\n\t\tint PNOWakeupScanWaitCnt = 0;\n\n\t\trtw_cfg80211_disconnected(padapter->rtw_wdev, 0, NULL, 0, 1, GFP_ATOMIC);\n\n\t\trtw_init_sitesurvey_parm(padapter, &parm);\n\t\tfor (i=0;i<pwrpriv->pnlo_info->ssid_num && i < RTW_SSID_SCAN_AMOUNT; i++) {\n\t\t\tlen = pwrpriv->pno_ssid_list->node[i].SSID_len;\n\t\t\t_rtw_memcpy(&parm.ssid[i].Ssid, pwrpriv->pno_ssid_list->node[i].SSID, len);\n\t\t\tparm.ssid[i].SsidLength = len;\n\t\t}\n\t\tparm.ssid_num = pwrpriv->pnlo_info->ssid_num;\n\n\t\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\t\t//This modification fix PNO wakeup reconnect issue with hidden SSID AP.\n\t\t//rtw_sitesurvey_cmd(padapter, NULL);\n\t\trtw_sitesurvey_cmd(padapter, &parm);\n\t\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\t\t\n\t\tfor (PNOWakeupScanWaitCnt = 0; PNOWakeupScanWaitCnt < 10; PNOWakeupScanWaitCnt++) {\n\t\t\tif(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _FALSE)\n\t\t\t\tbreak;\n\t\t\trtw_msleep_os(1000);\n\t\t}\n\t\t\n\t\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\t\tcfg80211_sched_scan_results(padapter->rtw_wdev->wiphy);\n\t\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\n\t}\n\tRTW_DBG(\"<== %s\\n\",__func__);\n\treturn 0;\n\t\n}\n#endif /* CONFIG_PNO_SUPPORT */\n\nstatic int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *ndev, char *buf, int len)\n{\n\tint ret = 0;\n\tuint wps_ielen = 0;\n\tu8 *wps_ie;\n\tu32\tp2p_ielen = 0;\n\tu8 wps_oui[8] = {0x0, 0x50, 0xf2, 0x04};\n\tu8 *p2p_ie;\n\tu32\twfd_ielen = 0;\n\tu8 *wfd_ie;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n\n\tRTW_INFO(FUNC_NDEV_FMT\" ielen=%d\\n\", FUNC_NDEV_ARG(ndev), len);\n\n\tif (len > 0) {\n\t\twps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen);\n\t\tif (wps_ie) {\n\t\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\t\tRTW_INFO(\"bcn_wps_ielen=%d\\n\", wps_ielen);\n\t\t\t#endif\n\n\t\t\tif (pmlmepriv->wps_beacon_ie) {\n\t\t\t\tu32 free_len = pmlmepriv->wps_beacon_ie_len;\n\t\t\t\tpmlmepriv->wps_beacon_ie_len = 0;\n\t\t\t\trtw_mfree(pmlmepriv->wps_beacon_ie, free_len);\n\t\t\t\tpmlmepriv->wps_beacon_ie = NULL;\n\t\t\t}\n\n\t\t\tpmlmepriv->wps_beacon_ie = rtw_malloc(wps_ielen);\n\t\t\tif (pmlmepriv->wps_beacon_ie == NULL) {\n\t\t\t\tRTW_INFO(\"%s()-%d: rtw_malloc() ERROR!\\n\", __FUNCTION__, __LINE__);\n\t\t\t\treturn -EINVAL;\n\n\t\t\t}\n\n\t\t\t_rtw_memcpy(pmlmepriv->wps_beacon_ie, wps_ie, wps_ielen);\n\t\t\tpmlmepriv->wps_beacon_ie_len = wps_ielen;\n\n\t\t\tupdate_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE, RTW_CMDF_WAIT_ACK);\n\n\t\t}\n\n\t\t/* buf += wps_ielen; */\n\t\t/* len -= wps_ielen; */\n\n\t\t#ifdef CONFIG_P2P\n\t\tp2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen);\n\t\tif (p2p_ie) {\n\t\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\t\tRTW_INFO(\"bcn_p2p_ielen=%d\\n\", p2p_ielen);\n\t\t\t#endif\n\n\t\t\tif (pmlmepriv->p2p_beacon_ie) {\n\t\t\t\tu32 free_len = pmlmepriv->p2p_beacon_ie_len;\n\t\t\t\tpmlmepriv->p2p_beacon_ie_len = 0;\n\t\t\t\trtw_mfree(pmlmepriv->p2p_beacon_ie, free_len);\n\t\t\t\tpmlmepriv->p2p_beacon_ie = NULL;\n\t\t\t}\n\n\t\t\tpmlmepriv->p2p_beacon_ie = rtw_malloc(p2p_ielen);\n\t\t\tif (pmlmepriv->p2p_beacon_ie == NULL) {\n\t\t\t\tRTW_INFO(\"%s()-%d: rtw_malloc() ERROR!\\n\", __FUNCTION__, __LINE__);\n\t\t\t\treturn -EINVAL;\n\n\t\t\t}\n\n\t\t\t_rtw_memcpy(pmlmepriv->p2p_beacon_ie, p2p_ie, p2p_ielen);\n\t\t\tpmlmepriv->p2p_beacon_ie_len = p2p_ielen;\n\n\t\t}\n\t\t#endif /* CONFIG_P2P */\n\n\n\t\t#ifdef CONFIG_WFD\n\t\twfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen);\n\t\tif (wfd_ie) {\n\t\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\t\tRTW_INFO(\"bcn_wfd_ielen=%d\\n\", wfd_ielen);\n\t\t\t#endif\n\n\t\t\tif (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_BEACON_IE, wfd_ie, wfd_ielen) != _SUCCESS)\n\t\t\t\treturn -EINVAL;\n\t\t}\n\t\t#endif /* CONFIG_WFD */\n\n\t\tpmlmeext->bstart_bss = _TRUE;\n\n\t}\n\n\treturn ret;\n\n}\n\nstatic int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *buf, int len)\n{\n\tint ret = 0;\n\tuint wps_ielen = 0;\n\tu8 *wps_ie;\n\tu32\tp2p_ielen = 0;\n\tu8 *p2p_ie;\n\tu32\twfd_ielen = 0;\n\tu8 *wfd_ie;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(net);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n#ifdef CONFIG_DEBUG_CFG80211\n\tRTW_INFO(\"%s, ielen=%d\\n\", __func__, len);\n#endif\n\n\tif (len > 0) {\n\t\twps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen);\n\t\tif (wps_ie) {\n\t\t\tuint\tattr_contentlen = 0;\n\t\t\tu16\tuconfig_method, *puconfig_method = NULL;\n\n\t\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\t\tRTW_INFO(\"probe_resp_wps_ielen=%d\\n\", wps_ielen);\n\t\t\t#endif\n\n\t\t\tif (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {\n\t\t\t\tu8 sr = 0;\n\t\t\t\trtw_get_wps_attr_content(wps_ie,  wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);\n\n\t\t\t\tif (sr != 0)\n\t\t\t\t\tRTW_INFO(\"%s, got sr\\n\", __func__);\n\t\t\t\telse {\n\t\t\t\t\tRTW_INFO(\"GO mode process WPS under site-survey,  sr no set\\n\");\n\t\t\t\t\treturn ret;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (pmlmepriv->wps_probe_resp_ie) {\n\t\t\t\tu32 free_len = pmlmepriv->wps_probe_resp_ie_len;\n\t\t\t\tpmlmepriv->wps_probe_resp_ie_len = 0;\n\t\t\t\trtw_mfree(pmlmepriv->wps_probe_resp_ie, free_len);\n\t\t\t\tpmlmepriv->wps_probe_resp_ie = NULL;\n\t\t\t}\n\n\t\t\tpmlmepriv->wps_probe_resp_ie = rtw_malloc(wps_ielen);\n\t\t\tif (pmlmepriv->wps_probe_resp_ie == NULL) {\n\t\t\t\tRTW_INFO(\"%s()-%d: rtw_malloc() ERROR!\\n\", __FUNCTION__, __LINE__);\n\t\t\t\treturn -EINVAL;\n\n\t\t\t}\n\n\t\t\t/* add PUSH_BUTTON config_method by driver self in wpsie of probe_resp at GO Mode */\n\t\t\tpuconfig_method = (u16 *)rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_CONF_METHOD , NULL, &attr_contentlen);\n\t\t\tif (puconfig_method != NULL) {\n\t\t\t\t/* struct registry_priv *pregistrypriv = &padapter->registrypriv; */\n\t\t\t\tstruct wireless_dev *wdev = padapter->rtw_wdev;\n\n\t\t\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\t\t\t/* printk(\"config_method in wpsie of probe_resp = 0x%x\\n\", be16_to_cpu(*puconfig_method)); */\n\t\t\t\t#endif\n\n\t\t\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\t\t\t\t/* for WIFI-DIRECT LOGO 4.2.2, AUTO GO can't set PUSH_BUTTON flags */\n\t\t\t\tif (wdev->iftype == NL80211_IFTYPE_P2P_GO) {\n\t\t\t\t\tuconfig_method = WPS_CM_PUSH_BUTTON;\n\t\t\t\t\tuconfig_method = cpu_to_be16(uconfig_method);\n\n\t\t\t\t\t*puconfig_method &= ~uconfig_method;\n\t\t\t\t}\n\t\t\t\t#endif\n\t\t\t}\n\n\t\t\t_rtw_memcpy(pmlmepriv->wps_probe_resp_ie, wps_ie, wps_ielen);\n\t\t\tpmlmepriv->wps_probe_resp_ie_len = wps_ielen;\n\n\t\t}\n\n\t\t/* buf += wps_ielen; */\n\t\t/* len -= wps_ielen; */\n\n\t\t#ifdef CONFIG_P2P\n\t\tp2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen);\n\t\tif (p2p_ie) {\n\t\t\tu8 is_GO = _FALSE;\n\t\t\tu32 attr_contentlen = 0;\n\t\t\tu16 cap_attr = 0;\n\n\t\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\t\tRTW_INFO(\"probe_resp_p2p_ielen=%d\\n\", p2p_ielen);\n\t\t\t#endif\n\n\t\t\t/* Check P2P Capability ATTR */\n\t\t\tif (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *) &attr_contentlen)) {\n\t\t\t\tu8 grp_cap = 0;\n\t\t\t\t/* RTW_INFO( \"[%s] Got P2P Capability Attr!!\\n\", __FUNCTION__ ); */\n\t\t\t\tcap_attr = le16_to_cpu(cap_attr);\n\t\t\t\tgrp_cap = (u8)((cap_attr >> 8) & 0xff);\n\n\t\t\t\tis_GO = (grp_cap & BIT(0)) ? _TRUE : _FALSE;\n\n\t\t\t\tif (is_GO)\n\t\t\t\t\tRTW_INFO(\"Got P2P Capability Attr, grp_cap=0x%x, is_GO\\n\", grp_cap);\n\t\t\t}\n\n\n\t\t\tif (is_GO == _FALSE) {\n\t\t\t\tif (pmlmepriv->p2p_probe_resp_ie) {\n\t\t\t\t\tu32 free_len = pmlmepriv->p2p_probe_resp_ie_len;\n\t\t\t\t\tpmlmepriv->p2p_probe_resp_ie_len = 0;\n\t\t\t\t\trtw_mfree(pmlmepriv->p2p_probe_resp_ie, free_len);\n\t\t\t\t\tpmlmepriv->p2p_probe_resp_ie = NULL;\n\t\t\t\t}\n\n\t\t\t\tpmlmepriv->p2p_probe_resp_ie = rtw_malloc(p2p_ielen);\n\t\t\t\tif (pmlmepriv->p2p_probe_resp_ie == NULL) {\n\t\t\t\t\tRTW_INFO(\"%s()-%d: rtw_malloc() ERROR!\\n\", __FUNCTION__, __LINE__);\n\t\t\t\t\treturn -EINVAL;\n\n\t\t\t\t}\n\t\t\t\t_rtw_memcpy(pmlmepriv->p2p_probe_resp_ie, p2p_ie, p2p_ielen);\n\t\t\t\tpmlmepriv->p2p_probe_resp_ie_len = p2p_ielen;\n\t\t\t} else {\n\t\t\t\tif (pmlmepriv->p2p_go_probe_resp_ie) {\n\t\t\t\t\tu32 free_len = pmlmepriv->p2p_go_probe_resp_ie_len;\n\t\t\t\t\tpmlmepriv->p2p_go_probe_resp_ie_len = 0;\n\t\t\t\t\trtw_mfree(pmlmepriv->p2p_go_probe_resp_ie, free_len);\n\t\t\t\t\tpmlmepriv->p2p_go_probe_resp_ie = NULL;\n\t\t\t\t}\n\n\t\t\t\tpmlmepriv->p2p_go_probe_resp_ie = rtw_malloc(p2p_ielen);\n\t\t\t\tif (pmlmepriv->p2p_go_probe_resp_ie == NULL) {\n\t\t\t\t\tRTW_INFO(\"%s()-%d: rtw_malloc() ERROR!\\n\", __FUNCTION__, __LINE__);\n\t\t\t\t\treturn -EINVAL;\n\n\t\t\t\t}\n\t\t\t\t_rtw_memcpy(pmlmepriv->p2p_go_probe_resp_ie, p2p_ie, p2p_ielen);\n\t\t\t\tpmlmepriv->p2p_go_probe_resp_ie_len = p2p_ielen;\n\t\t\t}\n\n\t\t}\n\t\t#endif /* CONFIG_P2P */\n\n\n\t\t#ifdef CONFIG_WFD\n\t\twfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen);\n\t\tif (wfd_ie) {\n\t\t\t#ifdef CONFIG_DEBUG_CFG80211\n\t\t\tRTW_INFO(\"probe_resp_wfd_ielen=%d\\n\", wfd_ielen);\n\t\t\t#endif\n\n\t\t\tif (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_PROBE_RESP_IE, wfd_ie, wfd_ielen) != _SUCCESS)\n\t\t\t\treturn -EINVAL;\n\t\t}\n\t\t#endif /* CONFIG_WFD */\n\n\t}\n\n\treturn ret;\n\n}\n\nstatic int rtw_cfg80211_set_assoc_resp_wpsp2pie(struct net_device *net, char *buf, int len)\n{\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(net);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tu8 *ie;\n\tu32 ie_len;\n\n\tRTW_INFO(\"%s, ielen=%d\\n\", __func__, len);\n\n\tif (len <= 0)\n\t\tgoto exit;\n\n\tie = rtw_get_wps_ie(buf, len, NULL, &ie_len);\n\tif (ie && ie_len) {\n\t\tif (pmlmepriv->wps_assoc_resp_ie) {\n\t\t\tu32 free_len = pmlmepriv->wps_assoc_resp_ie_len;\n\n\t\t\tpmlmepriv->wps_assoc_resp_ie_len = 0;\n\t\t\trtw_mfree(pmlmepriv->wps_assoc_resp_ie, free_len);\n\t\t\tpmlmepriv->wps_assoc_resp_ie = NULL;\n\t\t}\n\n\t\tpmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len);\n\t\tif (pmlmepriv->wps_assoc_resp_ie == NULL) {\n\t\t\tRTW_INFO(\"%s()-%d: rtw_malloc() ERROR!\\n\", __FUNCTION__, __LINE__);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\t_rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, ie, ie_len);\n\t\tpmlmepriv->wps_assoc_resp_ie_len = ie_len;\n\t}\n\n\tie = rtw_get_p2p_ie(buf, len, NULL, &ie_len);\n\tif (ie && ie_len) {\n\t\tif (pmlmepriv->p2p_assoc_resp_ie) {\n\t\t\tu32 free_len = pmlmepriv->p2p_assoc_resp_ie_len;\n\n\t\t\tpmlmepriv->p2p_assoc_resp_ie_len = 0;\n\t\t\trtw_mfree(pmlmepriv->p2p_assoc_resp_ie, free_len);\n\t\t\tpmlmepriv->p2p_assoc_resp_ie = NULL;\n\t\t}\n\n\t\tpmlmepriv->p2p_assoc_resp_ie = rtw_malloc(ie_len);\n\t\tif (pmlmepriv->p2p_assoc_resp_ie == NULL) {\n\t\t\tRTW_INFO(\"%s()-%d: rtw_malloc() ERROR!\\n\", __FUNCTION__, __LINE__);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\t_rtw_memcpy(pmlmepriv->p2p_assoc_resp_ie, ie, ie_len);\n\t\tpmlmepriv->p2p_assoc_resp_ie_len = ie_len;\n\t}\n\n#ifdef CONFIG_WFD\n\tie = rtw_get_wfd_ie(buf, len, NULL, &ie_len);\n\tif (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_ASSOC_RESP_IE, ie, ie_len) != _SUCCESS)\n\t\treturn -EINVAL;\n#endif\n\nexit:\n\treturn ret;\n}\n\nint rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len,\n\tint type)\n{\n\tint ret = 0;\n\tuint wps_ielen = 0;\n\tu32\tp2p_ielen = 0;\n\n#ifdef CONFIG_DEBUG_CFG80211\n\tRTW_INFO(\"%s, ielen=%d\\n\", __func__, len);\n#endif\n\n\tif ((rtw_get_wps_ie(buf, len, NULL, &wps_ielen) && (wps_ielen > 0))\n\t\t#ifdef CONFIG_P2P\n\t\t|| (rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen) && (p2p_ielen > 0))\n\t\t#endif\n\t) {\n\t\tif (net != NULL) {\n\t\t\tswitch (type) {\n\t\t\tcase 0x1: /* BEACON */\n\t\t\t\tret = rtw_cfg80211_set_beacon_wpsp2pie(net, buf, len);\n\t\t\t\tbreak;\n\t\t\tcase 0x2: /* PROBE_RESP */\n\t\t\t\tret = rtw_cfg80211_set_probe_resp_wpsp2pie(net, buf, len);\n\t\t\t\t#ifdef CONFIG_P2P\n\t\t\t\tif (ret == 0)\n\t\t\t\t\tadapter_wdev_data((_adapter *)rtw_netdev_priv(net))->probe_resp_ie_update_time = rtw_get_current_time();\n\t\t\t\t#endif\n\t\t\t\tbreak;\n\t\t\tcase 0x4: /* ASSOC_RESP */\n\t\t\t\tret = rtw_cfg80211_set_assoc_resp_wpsp2pie(net, buf, len);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn ret;\n\n}\n\n#ifdef CONFIG_80211N_HT\nstatic void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter\n\t, struct ieee80211_sta_ht_cap *ht_cap, BAND_TYPE band, u8 rf_type)\n{\n\tstruct registry_priv *pregistrypriv = &padapter->registrypriv;\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct ht_priv\t\t*phtpriv = &pmlmepriv->htpriv;\n\tu8 stbc_rx_enable = _FALSE;\n\n\trtw_ht_use_default_setting(padapter);\n\n\t/* RX LDPC */\n\tif (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX))\n\t\tht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;\n\n\t/* TX STBC */\n\tif (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX))\n\t\tht_cap->cap |= IEEE80211_HT_CAP_TX_STBC;\n\n\t/* RX STBC */\n\tif (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) {\n\t\t/*rtw_rx_stbc 0: disable, bit(0):enable 2.4g, bit(1):enable 5g*/\n\t\tif (band == BAND_ON_2_4G)\n\t\t\tstbc_rx_enable = (pregistrypriv->rx_stbc & BIT(0)) ? _TRUE : _FALSE;\n\t\tif (band == BAND_ON_5G)\n\t\t\tstbc_rx_enable = (pregistrypriv->rx_stbc & BIT(1)) ? _TRUE : _FALSE;\n\n\t\tif (stbc_rx_enable) {\n\t\t\tswitch (rf_type) {\n\t\t\tcase RF_1T1R:\n\t\t\t\tht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/*RX STBC One spatial stream*/\n\t\t\t\tbreak;\n\n\t\t\tcase RF_2T2R:\n\t\t\tcase RF_1T2R:\n\t\t\t\tht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/* Only one spatial-stream STBC RX is supported */\n\t\t\t\tbreak;\n\t\t\tcase RF_3T3R:\n\t\t\tcase RF_3T4R:\n\t\t\tcase RF_4T4R:\n\t\t\t\tht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/* Only one spatial-stream STBC RX is supported */\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tRTW_INFO(\"[warning] rf_type %d is not expected\\n\", rf_type);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic void rtw_cfg80211_init_ht_capab(_adapter *padapter\n\t, struct ieee80211_sta_ht_cap *ht_cap, BAND_TYPE band, u8 rf_type)\n{\n\tstruct registry_priv *regsty = &padapter->registrypriv;\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);\n\tu8 rx_nss = 0;\n\n\tif (!regsty->ht_enable || !is_supported_ht(regsty->wireless_mode))\n\t\treturn;\n\n\tht_cap->ht_supported = 1;\n\n\tht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |\n\t\t\t\tIEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20 |\n\t\t\t\tIEEE80211_HT_CAP_DSSSCCK40 | IEEE80211_HT_CAP_MAX_AMSDU;\n\trtw_cfg80211_init_ht_capab_ex(padapter, ht_cap, band, rf_type);\n\n\t/*\n\t *Maximum length of AMPDU that the STA can receive.\n\t *Length = 2 ^ (13 + max_ampdu_length_exp) - 1 (octets)\n\t */\n\tht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;\n\n\t/*Minimum MPDU start spacing , */\n\tht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;\n\n\tht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;\n\n\trx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num);\n\tswitch (rx_nss) {\n\tcase 1:\n\t\tht_cap->mcs.rx_mask[0] = 0xFF;\n\t\tbreak;\n\tcase 2:\n\t\tht_cap->mcs.rx_mask[0] = 0xFF;\n\t\tht_cap->mcs.rx_mask[1] = 0xFF;\n\t\tbreak;\n\tcase 3:\n\t\tht_cap->mcs.rx_mask[0] = 0xFF;\n\t\tht_cap->mcs.rx_mask[1] = 0xFF;\n\t\tht_cap->mcs.rx_mask[2] = 0xFF;\n\t\tbreak;\n\tcase 4:\n\t\tht_cap->mcs.rx_mask[0] = 0xFF;\n\t\tht_cap->mcs.rx_mask[1] = 0xFF;\n\t\tht_cap->mcs.rx_mask[2] = 0xFF;\n\t\tht_cap->mcs.rx_mask[3] = 0xFF;\n\t\tbreak;\n\tdefault:\n\t\trtw_warn_on(1);\n\t\tRTW_INFO(\"%s, error rf_type=%d\\n\", __func__, rf_type);\n\t};\n\n\tht_cap->mcs.rx_highest = cpu_to_le16(\n\t\trtw_mcs_rate(rf_type\n\t\t\t, hal_is_bw_support(padapter, CHANNEL_WIDTH_40)\n\t\t\t, hal_is_bw_support(padapter, CHANNEL_WIDTH_40) ? ht_cap->cap & IEEE80211_HT_CAP_SGI_40 : ht_cap->cap & IEEE80211_HT_CAP_SGI_20\n\t\t\t, ht_cap->mcs.rx_mask) / 10);\n}\n#endif /* CONFIG_80211N_HT */\n\n#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\nstatic void rtw_cfg80211_init_vht_capab(_adapter *padapter\n\t, struct ieee80211_sta_vht_cap *sta_vht_cap, BAND_TYPE band, u8 rf_type)\n{\n\tstruct registry_priv *regsty = &padapter->registrypriv;\n\tu8 vht_cap_ie[2 + 12] = {0};\n\n\tif (!REGSTY_IS_11AC_ENABLE(regsty) || !is_supported_vht(regsty->wireless_mode))\n\t\treturn;\n\n\trtw_vht_use_default_setting(padapter);\n\trtw_build_vht_cap_ie(padapter, vht_cap_ie);\n\n\tsta_vht_cap->vht_supported = 1;\n\n\t_rtw_memcpy(&sta_vht_cap->cap, vht_cap_ie + 2, 4);\n\t_rtw_memcpy(&sta_vht_cap->vht_mcs, vht_cap_ie + 2 + 4, 8);\n}\n#endif /* defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) */\n\nvoid rtw_cfg80211_init_wdev_data(_adapter *padapter)\n{\n#ifdef CONFIG_CONCURRENT_MODE\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n\n\tATOMIC_SET(&pwdev_priv->switch_ch_to, 1);\n#endif\n}\n\nvoid rtw_cfg80211_init_wiphy(_adapter *padapter)\n{\n\tu8 rf_type;\n\tstruct ieee80211_supported_band *band;\n\tstruct wireless_dev *pwdev = padapter->rtw_wdev;\n\tstruct wiphy *wiphy = pwdev->wiphy;\n\n\trtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));\n\n\tRTW_INFO(\"%s:rf_type=%d\\n\", __func__, rf_type);\n\n\tif (IsSupported24G(padapter->registrypriv.wireless_mode)) {\n\t\tband = wiphy->bands[NL80211_BAND_2GHZ];\n\t\tif (band) {\n\t\t\t#if defined(CONFIG_80211N_HT)\n\t\t\trtw_cfg80211_init_ht_capab(padapter, &band->ht_cap, BAND_ON_2_4G, rf_type);\n\t\t\t#endif\n\t\t}\n\t}\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\tif (is_supported_5g(padapter->registrypriv.wireless_mode)) {\n\t\tband = wiphy->bands[NL80211_BAND_5GHZ];\n\t\tif (band) {\n\t\t\t#if defined(CONFIG_80211N_HT)\n\t\t\trtw_cfg80211_init_ht_capab(padapter, &band->ht_cap, BAND_ON_5G, rf_type);\n\t\t\t#endif\n\t\t\t#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\t\t\trtw_cfg80211_init_vht_capab(padapter, &band->vht_cap, BAND_ON_5G, rf_type);\n\t\t\t#endif\n\t\t}\n\t}\n#endif\n\n\t/* copy mac_addr to wiphy */\n\t_rtw_memcpy(wiphy->perm_addr, adapter_mac_addr(padapter), ETH_ALEN);\n\n}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))\nstruct ieee80211_iface_limit rtw_limits[] = {\n\t{\n\t\t.max = 2,\n\t\t.types = BIT(NL80211_IFTYPE_STATION)\n\t\t\t#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))\n\t\t\t| BIT(NL80211_IFTYPE_P2P_CLIENT)\n\t\t\t#endif\n\t},\n\t#ifdef CONFIG_AP_MODE\n\t{\n\t\t.max = 1,\n\t\t.types = BIT(NL80211_IFTYPE_AP)\n\t\t\t#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))\n\t\t\t| BIT(NL80211_IFTYPE_P2P_GO)\n\t\t\t#endif\n\t},\n\t#endif\n\t#if defined(RTW_DEDICATED_P2P_DEVICE)\n\t{\n\t\t.max = 1,\n\t\t.types = BIT(NL80211_IFTYPE_P2P_DEVICE)\n\t},\n\t#endif\n\t#if defined(CONFIG_RTW_MESH)\n\t{\n\t\t.max = 1,\n\t\t.types = BIT(NL80211_IFTYPE_MESH_POINT)\n\t},\n\t#endif\n};\n\nstruct ieee80211_iface_combination rtw_combinations[] = {\n\t{\n\t\t.limits = rtw_limits,\n\t\t.n_limits = ARRAY_SIZE(rtw_limits),\n\t\t#if defined(RTW_DEDICATED_P2P_DEVICE)\n\t\t.max_interfaces = 3,\n\t\t#else\n\t\t.max_interfaces = 2,\n\t\t#endif\n\t\t.num_different_channels = 1,\n\t},\n};\n#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) */\n\nstatic void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct registry_priv *regsty = dvobj_to_regsty(dvobj);\n\n\twiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;\n\n\twiphy->max_scan_ssids = RTW_SSID_SCAN_AMOUNT;\n\twiphy->max_scan_ie_len = RTW_SCAN_IE_LEN_MAX;\n\twiphy->max_num_pmkids = RTW_MAX_NUM_PMKIDS;\n\n#if CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))\n\twiphy->max_acl_mac_addrs = NUM_ACL;\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)\n\twiphy->max_remain_on_channel_duration = RTW_MAX_REMAIN_ON_CHANNEL_DURATION;\n#endif\n\n\twiphy->interface_modes =\tBIT(NL80211_IFTYPE_STATION)\n\t\t\t\t\t\t\t\t| BIT(NL80211_IFTYPE_ADHOC)\n#ifdef CONFIG_AP_MODE\n\t\t\t\t\t\t\t\t| BIT(NL80211_IFTYPE_AP)\n\t\t\t\t\t\t\t\t#ifdef CONFIG_WIFI_MONITOR\n\t\t\t\t\t\t\t\t| BIT(NL80211_IFTYPE_MONITOR)\n\t\t\t\t\t\t\t\t#endif\n#endif\n#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))\n\t\t\t\t\t\t\t\t| BIT(NL80211_IFTYPE_P2P_CLIENT)\n\t\t\t\t\t\t\t\t| BIT(NL80211_IFTYPE_P2P_GO)\n\t\t\t\t\t\t\t\t#if defined(RTW_DEDICATED_P2P_DEVICE)\n\t\t\t\t\t\t\t\t| BIT(NL80211_IFTYPE_P2P_DEVICE)\n\t\t\t\t\t\t\t\t#endif\n#endif\n#ifdef CONFIG_RTW_MESH\n\t\t\t\t\t\t\t\t| BIT(NL80211_IFTYPE_MESH_POINT) /* 2.6.26 */\n#endif\n\t\t\t\t\t\t\t\t;\n\n#if defined(CONFIG_ANDROID) && !defined(RTW_SINGLE_WIPHY)\n        if (is_primary_adapter(adapter)) {\n                wiphy->interface_modes &= ~(BIT(NL80211_IFTYPE_P2P_GO) | BIT(NL80211_IFTYPE_P2P_CLIENT));\n                RTW_INFO(\"%s primary- don't set p2p capability\\n\", __func__);\n        }\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n#ifdef CONFIG_AP_MODE\n\twiphy->mgmt_stypes = rtw_cfg80211_default_mgmt_stypes;\n#endif /* CONFIG_AP_MODE */\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))\n\t#ifdef CONFIG_WIFI_MONITOR\n\twiphy->software_iftypes |= BIT(NL80211_IFTYPE_MONITOR);\n\t#endif\n#endif\n\n#if defined(RTW_SINGLE_WIPHY) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))\n\twiphy->iface_combinations = rtw_combinations;\n\twiphy->n_iface_combinations = ARRAY_SIZE(rtw_combinations);\n#endif\n\n\twiphy->cipher_suites = rtw_cipher_suites;\n\twiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites);\n\n\tif (IsSupported24G(adapter->registrypriv.wireless_mode))\n\t\twiphy->bands[NL80211_BAND_2GHZ] = rtw_spt_band_alloc(BAND_ON_2_4G);\n\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\tif (is_supported_5g(adapter->registrypriv.wireless_mode))\n\t\twiphy->bands[NL80211_BAND_5GHZ] = rtw_spt_band_alloc(BAND_ON_5G);\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38) && LINUX_VERSION_CODE < KERNEL_VERSION(3, 0, 0))\n\twiphy->flags |= WIPHY_FLAG_SUPPORTS_SEPARATE_DEFAULT_KEYS;\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))\n\twiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;\n\twiphy->flags |= WIPHY_FLAG_HAVE_AP_SME;\n\t/* remove WIPHY_FLAG_OFFCHAN_TX, because we not support this feature */\n\t/* wiphy->flags |= WIPHY_FLAG_OFFCHAN_TX | WIPHY_FLAG_HAVE_AP_SME; */\n#endif\n\n#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) && \\\n\t\t\t   LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))\n\twiphy->flags |= WIPHY_FLAG_SUPPORTS_SCHED_SCAN;\n#ifdef CONFIG_PNO_SUPPORT\n\twiphy->max_sched_scan_ssids = MAX_PNO_LIST_COUNT;\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)\n\twiphy->max_match_sets = MAX_PNO_LIST_COUNT;\n#endif\n#endif\n#endif\n\n#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0))\n\twiphy->wowlan = wowlan_stub;\n#else\n\twiphy->wowlan = &wowlan_stub;\n#endif\n#endif\n\n#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))\n\twiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;\n#ifndef CONFIG_TDLS_DRIVER_SETUP\n\twiphy->flags |= WIPHY_FLAG_TDLS_EXTERNAL_SETUP;\t/* Driver handles key exchange */\n\twiphy->flags |= NL80211_ATTR_HT_CAPABILITY;\n#endif /* CONFIG_TDLS_DRIVER_SETUP */\n#endif /* CONFIG_TDLS */\n\n\tif (regsty->power_mgnt != PS_MODE_ACTIVE)\n\t\twiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT;\n\telse\n\t\twiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))\n\t/* wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM; */\n#endif\n\n#ifdef CONFIG_RTW_MESH\n\twiphy->flags |= 0\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))\n\t\t| WIPHY_FLAG_IBSS_RSN\n\t\t#endif\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))\n\t\t| WIPHY_FLAG_MESH_AUTH\n\t\t#endif\n\t\t;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))\n\twiphy->features |= 0\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))\n\t\t| NL80211_FEATURE_USERSPACE_MPM\n\t\t#endif\n\t\t;\n#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) */\n#endif /* CONFIG_RTW_MESH */\n\n#if (KERNEL_VERSION(3, 8, 0) <= LINUX_VERSION_CODE)\n\twiphy->features |= NL80211_FEATURE_SAE;\n#endif\n}\n\n#ifdef CONFIG_RFKILL_POLL\nvoid rtw_cfg80211_init_rfkill(struct wiphy *wiphy)\n{\n\twiphy_rfkill_set_hw_state(wiphy, 0);\n\twiphy_rfkill_start_polling(wiphy);\n}\n\nvoid rtw_cfg80211_deinit_rfkill(struct wiphy *wiphy)\n{\n\twiphy_rfkill_stop_polling(wiphy);\n}\n\nstatic void cfg80211_rtw_rfkill_poll(struct wiphy *wiphy)\n{\n\t_adapter *padapter = NULL;\n\tbool blocked = _FALSE;\n\tu8 valid = 0;\n\n\tpadapter = wiphy_to_adapter(wiphy);\n\n\tif (adapter_to_dvobj(padapter)->processing_dev_remove == _TRUE) {\n\t\t/*RTW_INFO(\"cfg80211_rtw_rfkill_poll: device is removed!\\n\");*/\n\t\treturn;\n\t}\n\n\tblocked = rtw_hal_rfkill_poll(padapter, &valid);\n\t/*RTW_INFO(\"cfg80211_rtw_rfkill_poll: valid=%d, blocked=%d\\n\",\n\t\t\tvalid, blocked);*/\n\n\tif (valid)\n\t\twiphy_rfkill_set_hw_state(wiphy, blocked);\n}\n#endif\n\n#if defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33))\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))\n#define SURVEY_INFO_TIME\t\t\tSURVEY_INFO_CHANNEL_TIME\n#define SURVEY_INFO_TIME_BUSY\t\tSURVEY_INFO_CHANNEL_TIME_BUSY\n#define SURVEY_INFO_TIME_EXT_BUSY\tSURVEY_INFO_CHANNEL_TIME_EXT_BUSY\n#define SURVEY_INFO_TIME_RX\t\t\tSURVEY_INFO_CHANNEL_TIME_RX\n#define SURVEY_INFO_TIME_TX\t\t\tSURVEY_INFO_CHANNEL_TIME_TX\n#endif\n\n#ifdef CONFIG_FIND_BEST_CHANNEL\nstatic void rtw_cfg80211_set_survey_info_with_find_best_channel(struct wiphy *wiphy\n\t, struct net_device *netdev, int idx, struct survey_info *info)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tRT_CHANNEL_INFO *ch_set = rfctl->channel_set;\n\tu8 ch_num = rfctl->max_chan_nums;\n\tu32 total_rx_cnt = 0;\n\tint i;\n\n\ts8 noise = -50;\t\t/*channel noise in dBm. This and all following fields are optional */\n\tu64 time = 100;\t\t/*amount of time in ms the radio was turn on (on the channel)*/\n\tu64 time_busy = 0;\t/*amount of time the primary channel was sensed busy*/\n\n\tinfo->filled  = SURVEY_INFO_NOISE_DBM\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))\n\t\t| SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY\n\t\t#endif\n\t\t;\n\n\tfor (i = 0; i < ch_num; i++)\n\t\ttotal_rx_cnt += ch_set[i].rx_count;\n\n\ttime_busy = ch_set[idx].rx_count * time / total_rx_cnt;\n\tnoise += ch_set[idx].rx_count * 50 / total_rx_cnt;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))\n\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))\n\tinfo->channel_time = time;\n\tinfo->channel_time_busy = time_busy;\n\t#else\n\tinfo->time = time;\n\tinfo->time_busy = time_busy;\n\t#endif\n#endif\n\tinfo->noise = noise;\n\n\t/* reset if final channel is got */\n\tif (idx == ch_num - 1) {\n\t\tfor (i = 0; i < ch_num; i++)\n\t\t\tch_set[i].rx_count = 0;\n\t}\n}\n#endif /* CONFIG_FIND_BEST_CHANNEL */\n\n#if defined(CONFIG_RTW_ACS) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)\nstatic void rtw_cfg80211_set_survey_info_with_clm(PADAPTER padapter, int idx, struct survey_info *pinfo)\n{\n\ts8 noise = -50;\t\t\t/*channel noise in dBm. This and all following fields are optional */\n\tu64 time = SURVEY_TO;\t/*amount of time in ms the radio was turn on (on the channel)*/\n\tu64 time_busy = 0;\t\t/*amount of time the primary channel was sensed busy*/\n\tu8 chan = (u8)idx;\n\n\tif ((idx < 0) || (pinfo == NULL))\n\t\treturn;\n\n\tpinfo->filled  = SURVEY_INFO_NOISE_DBM\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))\n\t\t| SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY\n\t\t#endif\n\t\t;\n\n\ttime_busy = rtw_acs_get_clm_ratio_by_ch_idx(padapter, chan);\n\tnoise = rtw_noise_query_by_chan_idx(padapter, chan);\n\t/* RTW_INFO(\"%s: ch-idx:%d time=%llu(ms), time_busy=%llu(ms), noise=%d(dbm)\\n\", __func__, idx, time, time_busy, noise); */\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))\n\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))\n\tpinfo->channel_time = time;\n\tpinfo->channel_time_busy = time_busy;\n\t#else\n\tpinfo->time = time;\n\tpinfo->time_busy = time_busy;\n\t#endif\n#endif\n\tpinfo->noise = noise;\n}\n#endif\n\nint rtw_hostapd_acs_dump_survey(struct wiphy *wiphy, struct net_device *netdev, int idx, struct survey_info *info)\n{\n\tPADAPTER padapter = (_adapter *)rtw_netdev_priv(netdev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tRT_CHANNEL_INFO *pch_set = rfctl->channel_set;\n\tu8 max_chan_nums = rfctl->max_chan_nums;\n\tu32 freq = 0;\n\tu8 ret = 0;\n\tu16 channel = 0;\n\n\tif (!netdev || !info) {\n\t\tRTW_INFO(\"%s: invial parameters.\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t_rtw_memset(info, 0, sizeof(struct survey_info));\n\tif (padapter->bup == _FALSE) {\n\t\tRTW_INFO(\"%s: net device is down.\\n\", __func__);\n\t\treturn -EIO;\n\t}\n\n\tif (idx >= max_chan_nums)\n\t\treturn -ENOENT;\n\n\tchannel = pch_set[idx].ChannelNum;\n\tfreq = rtw_ch2freq(channel);\n\tinfo->channel = ieee80211_get_channel(wiphy, freq);\n\t/* RTW_INFO(\"%s: channel %d, freq %d\\n\", __func__, channel, freq); */\n\n\tif (!info->channel)\n\t\treturn -EINVAL;\n\n\tif (info->channel->flags == IEEE80211_CHAN_DISABLED)\n\t\treturn ret;\n\n#ifdef CONFIG_FIND_BEST_CHANNEL\n\trtw_cfg80211_set_survey_info_with_find_best_channel(wiphy, netdev, idx, info);\n#elif defined(CONFIG_RTW_ACS) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)\n\trtw_cfg80211_set_survey_info_with_clm(padapter, idx, info);\n#else\n\tRTW_ERR(\"%s: unknown acs operation!\\n\", __func__); \n#endif\n\n\treturn ret;\n}\n#endif /* defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33)) */\n\n#if (KERNEL_VERSION(4, 17, 0) <= LINUX_VERSION_CODE)\nint cfg80211_rtw_external_auth(struct wiphy *wiphy, struct net_device *dev,\n\tstruct cfg80211_external_auth_params *params)\n{\n\tPADAPTER padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_INFO(FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(dev));\n\n\trtw_cfg80211_external_auth_status(wiphy, dev,\n\t\t(struct rtw_external_auth_params *)params);\n\n\treturn 0;\n}\n#endif\n\nvoid rtw_cfg80211_external_auth_status(struct wiphy *wiphy, struct net_device *dev,\n\tstruct rtw_external_auth_params *params)\n{\n\tPADAPTER padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct sta_info\t*psta = NULL;\n\tu8 *buf = NULL;\n\tu32 len = 0;\n\t_irqL irqL;\n\n\tRTW_INFO(FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(dev));\n\n\tRTW_INFO(\"SAE: action: %u, status: %u\\n\", params->action, params->status);\n\tif (params->status == WLAN_STATUS_SUCCESS) {\n\t\tRTW_INFO(\"bssid: \"MAC_FMT\"\\n\", MAC_ARG(params->bssid));\n\t\tRTW_INFO(\"SSID: [%s]\\n\",\n\t\t\t((params->ssid.ssid_len == 0) ? \"\" : (char *)params->ssid.ssid));\n\t\tRTW_INFO(\"suite: 0x%08x\\n\", params->key_mgmt_suite);\n\t}\n\n\tpsta = rtw_get_stainfo(pstapriv, params->bssid);\n\tif (psta && (params->status == WLAN_STATUS_SUCCESS)) {\n\t\t/* AP mode */\n\t\tRTW_INFO(\"station match\\n\");\n\n\t\tpsta->state &= ~WIFI_FW_AUTH_NULL;\n\t\tpsta->state |= WIFI_FW_AUTH_SUCCESS;\n\t\tpsta->expire_to = padapter->stapriv.assoc_to;\n\n\t\tif (params->pmkid != NULL) {\n\t\t\t/* RTW_INFO_DUMP(\"PMKID:\", params->pmkid, PMKID_LEN); */\n\t\t\t_rtw_set_pmksa(dev, params->bssid, params->pmkid);\n\t\t}\n\n\t\t_enter_critical_bh(&psta->lock, &irqL);\n\t\tif ((psta->auth_len != 0) && (psta->pauth_frame != NULL)) {\n\t\t\tbuf =  rtw_zmalloc(psta->auth_len);\n\t\t\tif (buf) {\n\t\t\t\t_rtw_memcpy(buf, psta->pauth_frame, psta->auth_len);\n\t\t\t\tlen = psta->auth_len;\n\t\t\t}\n\n\t\t\trtw_mfree(psta->pauth_frame, psta->auth_len);\n\t\t\tpsta->pauth_frame = NULL;\n\t\t\tpsta->auth_len = 0;\n\t\t}\n\t\t_exit_critical_bh(&psta->lock, &irqL);\n\n\t\tif (buf) {\n\t\t\tstruct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);\n\t\t\t/* send the SAE auth Confirm */\n\n\t\t\trtw_ps_deny(padapter, PS_DENY_MGNT_TX);\n\t\t\tif (_SUCCESS == rtw_pwr_wakeup(padapter)) {\n\t\t\t\trtw_mi_set_scan_deny(padapter, 1000);\n\t\t\t\trtw_mi_scan_abort(padapter, _TRUE);\n\n\t\t\t\tRTW_INFO(\"SAE: Tx auth Confirm\\n\");\n\t\t\t\trtw_mgnt_tx_cmd(padapter, pmlmeext->cur_channel, 1, buf, len, 0, RTW_CMDF_DIRECTLY);\n\n\t\t\t\trtw_mfree(buf, len);\n\t\t\t\tbuf = NULL;\n\t\t\t\tlen = 0;\n\t\t\t}\n\t\t\trtw_ps_deny_cancel(padapter, PS_DENY_MGNT_TX);\n\t\t}\n\t} else {\n\t\t/* STA mode */\n\t\tpsecuritypriv->extauth_status = params->status;\n\t}\n}\n\nstatic struct cfg80211_ops rtw_cfg80211_ops = {\n\t.change_virtual_intf = cfg80211_rtw_change_iface,\n\t.add_key = cfg80211_rtw_add_key,\n\t.get_key = cfg80211_rtw_get_key,\n\t.del_key = cfg80211_rtw_del_key,\n\t.set_default_key = cfg80211_rtw_set_default_key,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30))\n\t.set_default_mgmt_key = cfg80211_rtw_set_default_mgmt_key,\n#endif\n#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))\n\t.set_rekey_data = cfg80211_rtw_set_rekey_data,\n#endif /*CONFIG_GTK_OL*/\n\t.get_station = cfg80211_rtw_get_station,\n\t.scan = cfg80211_rtw_scan,\n\t.set_wiphy_params = cfg80211_rtw_set_wiphy_params,\n\t.connect = cfg80211_rtw_connect,\n\t.disconnect = cfg80211_rtw_disconnect,\n\t.join_ibss = cfg80211_rtw_join_ibss,\n\t.leave_ibss = cfg80211_rtw_leave_ibss,\n\t.set_tx_power = cfg80211_rtw_set_txpower,\n\t.get_tx_power = cfg80211_rtw_get_txpower,\n\t.set_power_mgmt = cfg80211_rtw_set_power_mgmt,\n\t.set_pmksa = cfg80211_rtw_set_pmksa,\n\t.del_pmksa = cfg80211_rtw_del_pmksa,\n\t.flush_pmksa = cfg80211_rtw_flush_pmksa,\n\n#ifdef CONFIG_AP_MODE\n\t.add_virtual_intf = cfg80211_rtw_add_virtual_intf,\n\t.del_virtual_intf = cfg80211_rtw_del_virtual_intf,\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE)\n\t.add_beacon = cfg80211_rtw_add_beacon,\n\t.set_beacon = cfg80211_rtw_set_beacon,\n\t.del_beacon = cfg80211_rtw_del_beacon,\n#else\n\t.start_ap = cfg80211_rtw_start_ap,\n\t.change_beacon = cfg80211_rtw_change_beacon,\n\t.stop_ap = cfg80211_rtw_stop_ap,\n#endif\n\n#if CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))\n\t.set_mac_acl = cfg80211_rtw_set_mac_acl,\n#endif\n\n\t.add_station = cfg80211_rtw_add_station,\n\t.del_station = cfg80211_rtw_del_station,\n\t.change_station = cfg80211_rtw_change_station,\n\t.dump_station = cfg80211_rtw_dump_station,\n\t.change_bss = cfg80211_rtw_change_bss,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))\n\t.set_txq_params = cfg80211_rtw_set_txq_params,\n#endif\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))\n\t.set_channel = cfg80211_rtw_set_channel,\n#endif\n\t/* .auth = cfg80211_rtw_auth, */\n\t/* .assoc = cfg80211_rtw_assoc,\t */\n#endif /* CONFIG_AP_MODE */\n\n#if defined(CONFIG_RTW_MESH) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))\n\t.get_mesh_config = cfg80211_rtw_get_mesh_config,\n\t.update_mesh_config = cfg80211_rtw_update_mesh_config,\n\t.join_mesh = cfg80211_rtw_join_mesh,\n\t.leave_mesh = cfg80211_rtw_leave_mesh,\n\t.add_mpath = cfg80211_rtw_add_mpath,\n\t.del_mpath = cfg80211_rtw_del_mpath,\n\t.change_mpath = cfg80211_rtw_change_mpath,\n\t.get_mpath = cfg80211_rtw_get_mpath,\n\t.dump_mpath = cfg80211_rtw_dump_mpath,\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))\n\t.get_mpp = cfg80211_rtw_get_mpp,\n\t.dump_mpp = cfg80211_rtw_dump_mpp,\n\t#endif\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n\t.set_monitor_channel = cfg80211_rtw_set_monitor_channel,\n#endif\n\n#ifdef CONFIG_P2P\n\t.remain_on_channel = cfg80211_rtw_remain_on_channel,\n\t.cancel_remain_on_channel = cfg80211_rtw_cancel_remain_on_channel,\n\t#if defined(RTW_DEDICATED_P2P_DEVICE)\n\t.start_p2p_device = cfg80211_rtw_start_p2p_device,\n\t.stop_p2p_device = cfg80211_rtw_stop_p2p_device,\n\t#endif\n#endif /* CONFIG_P2P */\n\n#ifdef CONFIG_RTW_80211R\n\t.update_ft_ies = cfg80211_rtw_update_ft_ies,\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)\n\t.mgmt_tx = cfg80211_rtw_mgmt_tx,\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))\t\n\t.mgmt_frame_register = cfg80211_rtw_mgmt_frame_register,\n#else\n\t.update_mgmt_frame_registrations = cfg80211_rtw_update_mgmt_frame_register,\n#endif\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))\n\t.action = cfg80211_rtw_mgmt_tx,\n#endif\n\n#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))\n\t.tdls_mgmt = cfg80211_rtw_tdls_mgmt,\n\t.tdls_oper = cfg80211_rtw_tdls_oper,\n#endif /* CONFIG_TDLS */\n\n#if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))\n\t.sched_scan_start = cfg80211_rtw_sched_scan_start,\n\t.sched_scan_stop = cfg80211_rtw_sched_scan_stop,\n\t.suspend = cfg80211_rtw_suspend,\n\t.resume = cfg80211_rtw_resume,\n#endif /* CONFIG_PNO_SUPPORT */\n#ifdef CONFIG_RFKILL_POLL\n\t.rfkill_poll = cfg80211_rtw_rfkill_poll,\n#endif\n#if defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33))\n\t.dump_survey = rtw_hostapd_acs_dump_survey,\n#endif\n#if (KERNEL_VERSION(4, 17, 0) <= LINUX_VERSION_CODE)\n\t.external_auth = cfg80211_rtw_external_auth,\n#endif\n};\n\nstruct wiphy *rtw_wiphy_alloc(_adapter *padapter, struct device *dev)\n{\n\tstruct wiphy *wiphy;\n\tstruct rtw_wiphy_data *wiphy_data;\n\n\t/* wiphy */\n\twiphy = wiphy_new(&rtw_cfg80211_ops, sizeof(struct rtw_wiphy_data));\n\tif (!wiphy) {\n\t\tRTW_INFO(\"Couldn't allocate wiphy device\\n\");\n\t\tgoto exit;\n\t}\n\tset_wiphy_dev(wiphy, dev);\n\n\t/* wiphy_data */\n\twiphy_data = rtw_wiphy_priv(wiphy);\n\twiphy_data->dvobj = adapter_to_dvobj(padapter);\n#ifndef RTW_SINGLE_WIPHY\n\twiphy_data->adapter = padapter;\n#endif\n\n\trtw_cfg80211_preinit_wiphy(padapter, wiphy);\n\n\tRTW_INFO(FUNC_WIPHY_FMT\"\\n\", FUNC_WIPHY_ARG(wiphy));\n\nexit:\n\treturn wiphy;\n}\n\nvoid rtw_wiphy_free(struct wiphy *wiphy)\n{\n\tif (!wiphy)\n\t\treturn;\n\n\tRTW_INFO(FUNC_WIPHY_FMT\"\\n\", FUNC_WIPHY_ARG(wiphy));\n\n\tif (wiphy->bands[NL80211_BAND_2GHZ]) {\n\t\trtw_spt_band_free(wiphy->bands[NL80211_BAND_2GHZ]);\n\t\twiphy->bands[NL80211_BAND_2GHZ] = NULL;\n\t}\n\tif (wiphy->bands[NL80211_BAND_5GHZ]) {\n\t\trtw_spt_band_free(wiphy->bands[NL80211_BAND_5GHZ]);\n\t\twiphy->bands[NL80211_BAND_5GHZ] = NULL;\n\t}\n\n\twiphy_free(wiphy);\n}\n\nint rtw_wiphy_register(struct wiphy *wiphy)\n{\n\tRTW_INFO(FUNC_WIPHY_FMT\"\\n\", FUNC_WIPHY_ARG(wiphy));\n\n#if ( ((LINUX_VERSION_CODE < KERNEL_VERSION(5, 3, 0)) &&  \\\n        LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) \\\n     || defined(RTW_VENDOR_EXT_SUPPORT) )\n\trtw_cfgvendor_attach(wiphy);\n#endif\n\n\trtw_regd_init(wiphy);\n\n\treturn wiphy_register(wiphy);\n}\n\nvoid rtw_wiphy_unregister(struct wiphy *wiphy)\n{\n\tRTW_INFO(FUNC_WIPHY_FMT\"\\n\", FUNC_WIPHY_ARG(wiphy));\n\n#if ( ((LINUX_VERSION_CODE < KERNEL_VERSION(5, 3, 0)) &&  \\\n        LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) \\\n     || defined(RTW_VENDOR_EXT_SUPPORT) )\n\trtw_cfgvendor_detach(wiphy);\n#endif\n\n\t#if defined(RTW_DEDICATED_P2P_DEVICE)\n\trtw_pd_iface_free(wiphy);\n\t#endif\n\n\treturn wiphy_unregister(wiphy);\n}\n\nint rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy)\n{\n\tint ret = 0;\n\tstruct net_device *pnetdev = padapter->pnetdev;\n\tstruct wireless_dev *wdev;\n\tstruct rtw_wdev_priv *pwdev_priv;\n\n\tRTW_INFO(\"%s(padapter=%p)\\n\", __func__, padapter);\n\n\t/*  wdev */\n\twdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev));\n\tif (!wdev) {\n\t\tRTW_INFO(\"Couldn't allocate wireless device\\n\");\n\t\tret = -ENOMEM;\n\t\tgoto exit;\n\t}\n\twdev->wiphy = wiphy;\n\twdev->netdev = pnetdev;\n\twdev->iftype = NL80211_IFTYPE_STATION;\n\tpadapter->rtw_wdev = wdev;\n\tpnetdev->ieee80211_ptr = wdev;\n\n\t/* init pwdev_priv */\n\tpwdev_priv = adapter_wdev_data(padapter);\n\tpwdev_priv->rtw_wdev = wdev;\n\tpwdev_priv->pmon_ndev = NULL;\n\tpwdev_priv->ifname_mon[0] = '\\0';\n\tpwdev_priv->padapter = padapter;\n\tpwdev_priv->scan_request = NULL;\n\t_rtw_spinlock_init(&pwdev_priv->scan_req_lock);\n\tpwdev_priv->connect_req = NULL;\n\t_rtw_spinlock_init(&pwdev_priv->connect_req_lock);\n\n\tpwdev_priv->p2p_enabled = _FALSE;\n\tpwdev_priv->probe_resp_ie_update_time = rtw_get_current_time();\n\tpwdev_priv->provdisc_req_issued = _FALSE;\n\trtw_wdev_invit_info_init(&pwdev_priv->invit_info);\n\trtw_wdev_nego_info_init(&pwdev_priv->nego_info);\n\n\tpwdev_priv->bandroid_scan = _FALSE;\n\n\tif (padapter->registrypriv.power_mgnt != PS_MODE_ACTIVE)\n\t\tpwdev_priv->power_mgmt = _TRUE;\n\telse\n\t\tpwdev_priv->power_mgmt = _FALSE;\n\n\t_rtw_mutex_init(&pwdev_priv->roch_mutex);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tATOMIC_SET(&pwdev_priv->switch_ch_to, 1);\n#endif\n\n#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR\n        pwdev_priv->rssi_monitor_enable = 0;\n        pwdev_priv->rssi_monitor_max = 0;\n        pwdev_priv->rssi_monitor_min = 0;\n#endif\n\n\nexit:\n\treturn ret;\n}\n\nvoid rtw_wdev_free(struct wireless_dev *wdev)\n{\n\tif (!wdev)\n\t\treturn;\n\n\tRTW_INFO(\"%s(wdev=%p)\\n\", __func__, wdev);\n\n\tif (wdev_to_ndev(wdev)) {\n\t\t_adapter *adapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));\n\t\tstruct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter);\n\t\t_irqL irqL;\n\n\t\t_rtw_spinlock_free(&wdev_priv->scan_req_lock);\n\n\t\t_enter_critical_bh(&wdev_priv->connect_req_lock, &irqL);\n\t\trtw_wdev_free_connect_req(wdev_priv);\n\t\t_exit_critical_bh(&wdev_priv->connect_req_lock, &irqL);\n\t\t_rtw_spinlock_free(&wdev_priv->connect_req_lock);\n\n\t\t_rtw_mutex_free(&wdev_priv->roch_mutex);\n\t}\n\n\trtw_mfree((u8 *)wdev, sizeof(struct wireless_dev));\n}\n\nvoid rtw_wdev_unregister(struct wireless_dev *wdev)\n{\n\tstruct net_device *ndev;\n\t_adapter *adapter;\n\tstruct rtw_wdev_priv *pwdev_priv;\n\n\tif (!wdev)\n\t\treturn;\n\n\tRTW_INFO(\"%s(wdev=%p)\\n\", __func__, wdev);\n\n\tndev = wdev_to_ndev(wdev);\n\tif (!ndev)\n\t\treturn;\n\n\tadapter = (_adapter *)rtw_netdev_priv(ndev);\n\tpwdev_priv = adapter_wdev_data(adapter);\n\n\trtw_cfg80211_indicate_scan_done(adapter, _TRUE);\n\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) || defined(COMPAT_KERNEL_RELEASE)\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0))\n\tif (wdev->connected) {\n\t#else\n\tif (wdev->current_bss) {\n\t#endif\n\t\tRTW_INFO(FUNC_ADPT_FMT\" clear current_bss by cfg80211_disconnected\\n\", FUNC_ADPT_ARG(adapter));\n\t\trtw_cfg80211_indicate_disconnect(adapter, 0, 1);\n\t}\n\t#endif\n\n\tif (pwdev_priv->pmon_ndev) {\n\t\tRTW_INFO(\"%s, unregister monitor interface\\n\", __func__);\n\t\tunregister_netdev(pwdev_priv->pmon_ndev);\n\t}\n}\n\nint rtw_cfg80211_ndev_res_alloc(_adapter *adapter)\n{\n\tint ret = _FAIL;\n\n#if !defined(RTW_SINGLE_WIPHY)\n\tstruct wiphy *wiphy;\n\tstruct device *dev = dvobj_to_dev(adapter_to_dvobj(adapter));\n\n\twiphy = rtw_wiphy_alloc(adapter, dev);\n\tif (wiphy == NULL)\n\t\tgoto exit;\n\n\tadapter->wiphy = wiphy;\n#endif\n\n\tif (rtw_wdev_alloc(adapter, adapter_to_wiphy(adapter)) == 0)\n\t\tret = _SUCCESS;\n\n#if !defined(RTW_SINGLE_WIPHY)\n\tif (ret != _SUCCESS) {\n\t\trtw_wiphy_free(wiphy);\n\t\tadapter->wiphy = NULL;\n\t}\n#endif\n\nexit:\n\treturn ret;\n}\n\nvoid rtw_cfg80211_ndev_res_free(_adapter *adapter)\n{\n\trtw_wdev_free(adapter->rtw_wdev);\n\tadapter->rtw_wdev = NULL;\n#if !defined(RTW_SINGLE_WIPHY)\n\trtw_wiphy_free(adapter_to_wiphy(adapter));\n\tadapter->wiphy = NULL;\n#endif\n}\n\nint rtw_cfg80211_ndev_res_register(_adapter *adapter)\n{\n\tint ret = _FAIL;\n\n#if !defined(RTW_SINGLE_WIPHY)\n\tif (rtw_wiphy_register(adapter_to_wiphy(adapter)) < 0) {\n\t\tRTW_INFO(\"%s rtw_wiphy_register fail for if%d\\n\", __func__, (adapter->iface_id + 1));\n\t\tgoto exit;\n\t}\n\n#ifdef CONFIG_RFKILL_POLL\n\trtw_cfg80211_init_rfkill(adapter_to_wiphy(adapter));\n#endif\n#endif\n\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n\nvoid rtw_cfg80211_ndev_res_unregister(_adapter *adapter)\n{\n\trtw_wdev_unregister(adapter->rtw_wdev);\n}\n\nint rtw_cfg80211_dev_res_alloc(struct dvobj_priv *dvobj)\n{\n\tint ret = _FAIL;\n\n#if defined(RTW_SINGLE_WIPHY)\n\tstruct wiphy *wiphy;\n\tstruct device *dev = dvobj_to_dev(dvobj);\n\n\twiphy = rtw_wiphy_alloc(dvobj_get_primary_adapter(dvobj), dev);\n\tif (wiphy == NULL)\n\t\treturn ret;\n\n\tdvobj->wiphy = wiphy;\n#endif\n\n\tret = _SUCCESS;\n\treturn ret;\n}\n\nvoid rtw_cfg80211_dev_res_free(struct dvobj_priv *dvobj)\n{\n#if defined(RTW_SINGLE_WIPHY)\n\trtw_wiphy_free(dvobj_to_wiphy(dvobj));\n\tdvobj->wiphy = NULL;\n#endif\n}\n\nint rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj)\n{\n\tint ret = _FAIL;\n\n#if defined(RTW_SINGLE_WIPHY)\n\tif (rtw_wiphy_register(dvobj_to_wiphy(dvobj)) != 0)\n\t\treturn ret;\n\n#ifdef CONFIG_RFKILL_POLL\n\trtw_cfg80211_init_rfkill(dvobj_to_wiphy(dvobj));\n#endif\n#endif\n\n\tret = _SUCCESS;\n\n\treturn ret;\n}\n\nvoid rtw_cfg80211_dev_res_unregister(struct dvobj_priv *dvobj)\n{\n#if defined(RTW_SINGLE_WIPHY)\n#ifdef CONFIG_RFKILL_POLL\n\trtw_cfg80211_deinit_rfkill(dvobj_to_wiphy(dvobj));\n#endif\n\trtw_wiphy_unregister(dvobj_to_wiphy(dvobj));\n#endif\n}\n\n#endif /* CONFIG_IOCTL_CFG80211 */\n"
  },
  {
    "path": "os_dep/linux/ioctl_cfg80211.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __IOCTL_CFG80211_H__\n#define __IOCTL_CFG80211_H__\n\n#define RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT\t\tBIT0\n#define RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT\tBIT1\n\n#ifndef RTW_CFG80211_BLOCK_STA_DISCON_EVENT\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0))\n#define RTW_CFG80211_BLOCK_STA_DISCON_EVENT (RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT)\n#else\n#define RTW_CFG80211_BLOCK_STA_DISCON_EVENT (RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT | RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)\n#endif\n#endif\n\n#if defined(RTW_USE_CFG80211_STA_EVENT)\n\t#undef CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER\n#endif\n\n#ifndef RTW_P2P_GROUP_INTERFACE\n\t#define RTW_P2P_GROUP_INTERFACE 0\n#endif\n\n/*\n* (RTW_P2P_GROUP_INTERFACE, RTW_DEDICATED_P2P_DEVICE)\n* (0, 0): wlan0 + p2p0(PD+PG)\n* (1, 0): wlan0(with PD) + dynamic PGs\n* (1, 1): wlan0 (with dynamic PD wdev) + dynamic PGs\n*/\n\n#if RTW_P2P_GROUP_INTERFACE\n\t#ifndef CONFIG_RTW_DYNAMIC_NDEV\n\t\t#define CONFIG_RTW_DYNAMIC_NDEV\n\t#endif\n\t#ifndef RTW_SINGLE_WIPHY\n\t\t#define RTW_SINGLE_WIPHY\n\t#endif\n\t#ifndef CONFIG_RADIO_WORK\n\t\t#define CONFIG_RADIO_WORK\n\t#endif\n\t#ifndef RTW_DEDICATED_P2P_DEVICE\n\t\t#define RTW_DEDICATED_P2P_DEVICE\n\t#endif\n#endif\n\n#ifndef CONFIG_RADIO_WORK\n#define RTW_ROCH_DURATION_ENLARGE\n#define RTW_ROCH_BACK_OP\n#endif\n\n#if !defined(CONFIG_P2P) && RTW_P2P_GROUP_INTERFACE\n\t#error \"RTW_P2P_GROUP_INTERFACE can't be enabled when CONFIG_P2P is disabled\\n\"\n#endif\n\n#if !RTW_P2P_GROUP_INTERFACE && defined(RTW_DEDICATED_P2P_DEVICE)\n\t#error \"RTW_DEDICATED_P2P_DEVICE can't be enabled when RTW_P2P_GROUP_INTERFACE is disabled\\n\"\n#endif\n\n#if defined(RTW_DEDICATED_P2P_DEVICE) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0))\n\t#error \"RTW_DEDICATED_P2P_DEVICE can't be enabled when kernel < 3.7.0\\n\"\n#endif\n\n#ifdef CONFIG_RTW_MESH\n\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))\n\t\t#error \"CONFIG_RTW_MESH can't be enabled when kernel < 3.10.0\\n\"\n\t#endif\n#endif\n\nstruct rtw_wdev_invit_info {\n\tu8 state; /* 0: req, 1:rep */\n\tu8 peer_mac[ETH_ALEN];\n\tu8 group_bssid[ETH_ALEN];\n\tu8 active;\n\tu8 token;\n\tu8 flags;\n\tu8 status;\n\tu8 req_op_ch;\n\tu8 rsp_op_ch;\n};\n\n#define rtw_wdev_invit_info_init(invit_info) \\\n\tdo { \\\n\t\t(invit_info)->state = 0xff; \\\n\t\t_rtw_memset((invit_info)->peer_mac, 0, ETH_ALEN); \\\n\t\t_rtw_memset((invit_info)->group_bssid, 0, ETH_ALEN); \\\n\t\t(invit_info)->active = 0xff; \\\n\t\t(invit_info)->token = 0; \\\n\t\t(invit_info)->flags = 0x00; \\\n\t\t(invit_info)->status = 0xff; \\\n\t\t(invit_info)->req_op_ch = 0; \\\n\t\t(invit_info)->rsp_op_ch = 0; \\\n\t} while (0)\n\nstruct rtw_wdev_nego_info {\n\tu8 state; /* 0: req, 1:rep, 2:conf */\n\tu8 iface_addr[ETH_ALEN];\n\tu8 peer_mac[ETH_ALEN];\n\tu8 peer_iface_addr[ETH_ALEN];\n\tu8 active;\n\tu8 token;\n\tu8 status;\n\tu8 req_intent;\n\tu8 req_op_ch;\n\tu8 req_listen_ch;\n\tu8 rsp_intent;\n\tu8 rsp_op_ch;\n\tu8 conf_op_ch;\n};\n\n#define rtw_wdev_nego_info_init(nego_info) \\\n\tdo { \\\n\t\t(nego_info)->state = 0xff; \\\n\t\t_rtw_memset((nego_info)->iface_addr, 0, ETH_ALEN); \\\n\t\t_rtw_memset((nego_info)->peer_mac, 0, ETH_ALEN); \\\n\t\t_rtw_memset((nego_info)->peer_iface_addr, 0, ETH_ALEN); \\\n\t\t(nego_info)->active = 0xff; \\\n\t\t(nego_info)->token = 0; \\\n\t\t(nego_info)->status = 0xff; \\\n\t\t(nego_info)->req_intent = 0xff; \\\n\t\t(nego_info)->req_op_ch = 0; \\\n\t\t(nego_info)->req_listen_ch = 0; \\\n\t\t(nego_info)->rsp_intent = 0xff; \\\n\t\t(nego_info)->rsp_op_ch = 0; \\\n\t\t(nego_info)->conf_op_ch = 0; \\\n\t} while (0)\n\nstruct rtw_wdev_priv {\n\tstruct wireless_dev *rtw_wdev;\n\n\t_adapter *padapter;\n\n\t#if RTW_CFG80211_BLOCK_STA_DISCON_EVENT\n\tu8 not_indic_disco;\n\t#endif\n\n\tstruct cfg80211_scan_request *scan_request;\n\t_lock scan_req_lock;\n\n\tstruct cfg80211_connect_params *connect_req;\n\t_lock connect_req_lock;\n\n\tstruct net_device *pmon_ndev;/* for monitor interface */\n\tchar ifname_mon[IFNAMSIZ + 1]; /* interface name for monitor interface */\n\n\tu8 p2p_enabled;\n\tsystime probe_resp_ie_update_time;\n\n\tu8 provdisc_req_issued;\n\n\tstruct rtw_wdev_invit_info invit_info;\n\tstruct rtw_wdev_nego_info nego_info;\n\n\tu8 bandroid_scan;\n\tbool block;\n\tbool block_scan;\n\tbool power_mgmt;\n    \n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)\n\tu32 mgmt_mask;\n\t#endif\n\n\t/* report mgmt_frame registered */\n\tu16 report_mgmt;\n\n\tu8 is_mgmt_tx;\n\tu16 mgmt_tx_cookie;\n\n\t_mutex roch_mutex;\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tATOMIC_T switch_ch_to;\n#endif\n\n#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI\n\tu8 pno_mac_addr[ETH_ALEN];\n\tu16 pno_scan_seq_num;\n#endif\n\n#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR\n        s8 rssi_monitor_max;\n        s8 rssi_monitor_min;\n        u8 rssi_monitor_enable;\n#endif\n\n};\n\nenum external_auth_action {\n\tEXTERNAL_AUTH_START,\n\tEXTERNAL_AUTH_ABORT,\n};\n\nstruct rtw_external_auth_params {\n\tenum external_auth_action action;\n\tu8 bssid[ETH_ALEN]__aligned(2);\n\tstruct cfg80211_ssid ssid;\n\tunsigned int key_mgmt_suite;\n\tu16 status;\n\tu8 pmkid[PMKID_LEN];\n};\n\nbool rtw_cfg80211_is_connect_requested(_adapter *adapter);\n\n#if RTW_CFG80211_BLOCK_STA_DISCON_EVENT\n#define rtw_wdev_not_indic_disco(rtw_wdev_data) ((rtw_wdev_data)->not_indic_disco)\n#define rtw_wdev_set_not_indic_disco(rtw_wdev_data, val) do { (rtw_wdev_data)->not_indic_disco = (val); } while (0)\n#else\n#define rtw_wdev_not_indic_disco(rtw_wdev_data) 0\n#define rtw_wdev_set_not_indic_disco(rtw_wdev_data, val) do {} while (0)\n#endif\n\n#define rtw_wdev_free_connect_req(rtw_wdev_data) \\\n\tdo { \\\n\t\tif ((rtw_wdev_data)->connect_req) { \\\n\t\t\trtw_mfree((u8 *)(rtw_wdev_data)->connect_req, sizeof(*(rtw_wdev_data)->connect_req)); \\\n\t\t\t(rtw_wdev_data)->connect_req = NULL; \\\n\t\t} \\\n\t} while (0)\n\n#define wdev_to_ndev(w) ((w)->netdev)\n#define wdev_to_wiphy(w) ((w)->wiphy)\n#define ndev_to_wdev(n) ((n)->ieee80211_ptr)\n\nstruct rtw_wiphy_data {\n\tstruct dvobj_priv *dvobj;\n\n#ifndef RTW_SINGLE_WIPHY\n\t_adapter *adapter;\n#endif\n\n#if defined(RTW_DEDICATED_P2P_DEVICE)\n\tstruct wireless_dev *pd_wdev; /* P2P device wdev */\n#endif\n};\n\n#define rtw_wiphy_priv(wiphy) ((struct rtw_wiphy_data *)wiphy_priv(wiphy))\n#define wiphy_to_dvobj(wiphy) (((struct rtw_wiphy_data *)wiphy_priv(wiphy))->dvobj)\n#ifdef RTW_SINGLE_WIPHY\n#define wiphy_to_adapter(wiphy) (dvobj_get_primary_adapter(wiphy_to_dvobj(wiphy)))\n#else\n#define wiphy_to_adapter(wiphy) (((struct rtw_wiphy_data *)wiphy_priv(wiphy))->adapter)\n#endif\n\n#if defined(RTW_DEDICATED_P2P_DEVICE)\n#define wiphy_to_pd_wdev(wiphy) (rtw_wiphy_priv(wiphy)->pd_wdev)\n#else\n#define wiphy_to_pd_wdev(wiphy) NULL\n#endif\n\n#define WIPHY_FMT \"%s\"\n#define WIPHY_ARG(wiphy) wiphy_name(wiphy)\n#define FUNC_WIPHY_FMT \"%s(\"WIPHY_FMT\")\"\n#define FUNC_WIPHY_ARG(wiphy) __func__, WIPHY_ARG(wiphy)\n\n#define SET_CFG80211_REPORT_MGMT(w, t, v) (w->report_mgmt |= BIT(t >> 4))\n#define CLR_CFG80211_REPORT_MGMT(w, t, v) (w->report_mgmt &= (~BIT(t >> 4)))\n#define GET_CFG80211_REPORT_MGMT(w, t) ((w->report_mgmt & BIT(t >> 4)) > 0)\n\nstruct wiphy *rtw_wiphy_alloc(_adapter *padapter, struct device *dev);\nvoid rtw_wiphy_free(struct wiphy *wiphy);\nint rtw_wiphy_register(struct wiphy *wiphy);\nvoid rtw_wiphy_unregister(struct wiphy *wiphy);\n\nint rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy);\nvoid rtw_wdev_free(struct wireless_dev *wdev);\nvoid rtw_wdev_unregister(struct wireless_dev *wdev);\n\nint rtw_cfg80211_ndev_res_alloc(_adapter *adapter);\nvoid rtw_cfg80211_ndev_res_free(_adapter *adapter);\nint rtw_cfg80211_ndev_res_register(_adapter *adapter);\nvoid rtw_cfg80211_ndev_res_unregister(_adapter *adapter);\n\nint rtw_cfg80211_dev_res_alloc(struct dvobj_priv *dvobj);\nvoid rtw_cfg80211_dev_res_free(struct dvobj_priv *dvobj);\nint rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj);\nvoid rtw_cfg80211_dev_res_unregister(struct dvobj_priv *dvobj);\n\nvoid rtw_cfg80211_init_wdev_data(_adapter *padapter);\nvoid rtw_cfg80211_init_wiphy(_adapter *padapter);\n\nvoid rtw_cfg80211_unlink_bss(_adapter *padapter, struct wlan_network *pnetwork);\nvoid rtw_cfg80211_surveydone_event_callback(_adapter *padapter);\nstruct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork);\nint rtw_cfg80211_check_bss(_adapter *padapter);\nvoid rtw_cfg80211_ibss_indicate_connect(_adapter *padapter);\nvoid rtw_cfg80211_indicate_connect(_adapter *padapter);\nvoid rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated);\nvoid rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted);\nu32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms);\n\n#ifdef CONFIG_CONCURRENT_MODE\nu8 rtw_cfg80211_scan_via_buddy(_adapter *padapter, struct cfg80211_scan_request *request);\nvoid rtw_cfg80211_indicate_scan_done_for_buddy(_adapter *padapter, bool bscan_aborted);\n#endif\n\n#ifdef CONFIG_AP_MODE\nvoid rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);\nvoid rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, const u8 *da, unsigned short reason);\n#endif /* CONFIG_AP_MODE */\n\n#ifdef CONFIG_P2P\nvoid rtw_cfg80211_set_is_roch(_adapter *adapter, bool val);\nbool rtw_cfg80211_get_is_roch(_adapter *adapter);\nbool rtw_cfg80211_is_ro_ch_once(_adapter *adapter);\nvoid rtw_cfg80211_set_last_ro_ch_time(_adapter *adapter);\ns32 rtw_cfg80211_get_last_ro_ch_passing_ms(_adapter *adapter);\n\nint rtw_cfg80211_iface_has_p2p_group_cap(_adapter *adapter);\nint rtw_cfg80211_is_p2p_scan(_adapter *adapter);\n#if defined(RTW_DEDICATED_P2P_DEVICE)\nint rtw_cfg80211_redirect_pd_wdev(struct wiphy *wiphy, u8 *ra, struct wireless_dev **wdev);\nint rtw_cfg80211_is_scan_by_pd_wdev(_adapter *adapter);\nint rtw_pd_iface_alloc(struct wiphy *wiphy, const char *name, struct wireless_dev **pd_wdev);\nvoid rtw_pd_iface_free(struct wiphy *wiphy);\n#endif\n#endif /* CONFIG_P2P */\n\nvoid rtw_cfg80211_set_is_mgmt_tx(_adapter *adapter, u8 val);\nu8 rtw_cfg80211_get_is_mgmt_tx(_adapter *adapter);\nu8 rtw_mgnt_tx_handler(_adapter *adapter, u8 *buf);\n\nvoid rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len);\n\nvoid rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, union recv_frame *rframe);\nvoid rtw_cfg80211_rx_action_p2p(_adapter *padapter, union recv_frame *rframe);\nvoid rtw_cfg80211_rx_action(_adapter *adapter, union recv_frame *rframe, const char *msg);\nvoid rtw_cfg80211_rx_mframe(_adapter *adapter, union recv_frame *rframe, const char *msg);\nvoid rtw_cfg80211_rx_probe_request(_adapter *padapter, union recv_frame *rframe);\n\nvoid rtw_cfg80211_external_auth_request(_adapter *padapter, union recv_frame *rframe);\nvoid rtw_cfg80211_external_auth_status(struct wiphy *wiphy, struct net_device *dev,\n\tstruct rtw_external_auth_params *params);\n\nint rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type);\n\nbool rtw_cfg80211_pwr_mgmt(_adapter *adapter);\n#ifdef CONFIG_RTW_80211K\nvoid rtw_cfg80211_rx_rrm_action(_adapter *adapter, union recv_frame *rframe);\n#endif\n\n#ifdef CONFIG_RFKILL_POLL\nvoid rtw_cfg80211_init_rfkill(struct wiphy *wiphy);\nvoid rtw_cfg80211_deinit_rfkill(struct wiphy *wiphy);\n#endif\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0))  && !defined(COMPAT_KERNEL_RELEASE)\n#define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev_to_ndev(wdev), freq, buf, len, gfp)\n#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))\n#define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev_to_ndev(wdev), freq, sig_dbm, buf, len, gfp)\n#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 12, 0))\n#define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp)\n#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3 , 18 , 0))\n#define rtw_cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , gfp) cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , 0 , gfp)\n#else\n#define rtw_cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , gfp) cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , 0)\n#endif\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0))  && !defined(COMPAT_KERNEL_RELEASE)\n#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, buf, len)\n#else\n#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, bss, buf, len)\n#endif\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))\n#define rtw_cfg80211_mgmt_tx_status(wdev, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status(wdev_to_ndev(wdev), cookie, buf, len, ack, gfp)\n#else\n#define rtw_cfg80211_mgmt_tx_status(wdev, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status(wdev, cookie, buf, len, ack, gfp)\n#endif\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))\n#define rtw_cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp)  cfg80211_ready_on_channel(wdev_to_ndev(wdev), cookie, chan, channel_type, duration, gfp)\n#define rtw_cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired(wdev_to_ndev(wdev), cookie, chan, chan_type, gfp)\n#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))\n#define rtw_cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp)  cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp)\n#define rtw_cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp)\n#else\n#define rtw_cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp)  cfg80211_ready_on_channel(wdev, cookie, chan, duration, gfp)\n#define rtw_cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired(wdev, cookie, chan, gfp)\n#endif\n\n#define rtw_cfg80211_connect_result(wdev, bssid, req_ie, req_ie_len, resp_ie, resp_ie_len, status, gfp) cfg80211_connect_result(wdev_to_ndev(wdev), bssid, req_ie, req_ie_len, resp_ie, resp_ie_len, status, gfp)\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0))\n#define rtw_cfg80211_disconnected(wdev, reason, ie, ie_len, locally_generated, gfp) cfg80211_disconnected(wdev_to_ndev(wdev), reason, ie, ie_len, gfp)\n#else\n#define rtw_cfg80211_disconnected(wdev, reason, ie, ie_len, locally_generated, gfp) cfg80211_disconnected(wdev_to_ndev(wdev), reason, ie, ie_len, locally_generated, gfp)\n#endif\n\n#ifdef CONFIG_RTW_80211R\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))\n#define rtw_cfg80211_ft_event(adapter, parm)  cfg80211_ft_event((adapter)->pnetdev, parm)\n#else\n\t#error \"Cannot support FT for KERNEL_VERSION < 3.10\\n\"\n#endif\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0))\n#define rtw_cfg80211_notify_new_peer_candidate(wdev, addr, ie, ie_len, sig_dbm, gfp) cfg80211_notify_new_peer_candidate(wdev_to_ndev(wdev), addr, ie, ie_len, sig_dbm, gfp)\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))\n#define rtw_cfg80211_notify_new_peer_candidate(wdev, addr, ie, ie_len, sig_dbm, gfp) cfg80211_notify_new_peer_candidate(wdev_to_ndev(wdev), addr, ie, ie_len, gfp)\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))\nu8 rtw_cfg80211_ch_switch_notify(_adapter *adapter, u8 ch, u8 bw, u8 offset, u8 ht);\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0))\n#define NL80211_BAND_2GHZ IEEE80211_BAND_2GHZ\n#define NL80211_BAND_5GHZ IEEE80211_BAND_5GHZ\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))\n#define NL80211_BAND_60GHZ IEEE80211_BAND_60GHZ\n#endif\n#define NUM_NL80211_BANDS IEEE80211_NUM_BANDS\n#endif\n\n#define rtw_band_to_nl80211_band(band) \\\n\t(band == BAND_ON_2_4G) ? NL80211_BAND_2GHZ : \\\n\t(band == BAND_ON_5G) ? NL80211_BAND_5GHZ : NUM_NL80211_BANDS\n\n#include \"rtw_cfgvendor.h\"\n\n#endif /* __IOCTL_CFG80211_H__ */\n"
  },
  {
    "path": "os_dep/linux/ioctl_linux.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _IOCTL_LINUX_C_\n\n#include <drv_types.h>\n#include <rtw_mp.h>\n#include \"../../hal/phydm/phydm_precomp.h\"\n#ifdef RTW_HALMAC\n#include \"../../hal/hal_halmac.h\"\n#endif\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27))\n#define  iwe_stream_add_event(a, b, c, d, e)  iwe_stream_add_event(b, c, d, e)\n#define  iwe_stream_add_point(a, b, c, d, e)  iwe_stream_add_point(b, c, d, e)\n#endif\n\n#ifdef CONFIG_80211N_HT\nextern int rtw_ht_enable;\n#endif\n\n\n#define RTL_IOCTL_WPA_SUPPLICANT\t(SIOCIWFIRSTPRIV+30)\n\n#define SCAN_ITEM_SIZE 768\n#define MAX_CUSTOM_LEN 64\n#define RATE_COUNT 4\n#define MAX_SCAN_BUFFER_LEN 65535\n\n#ifdef CONFIG_GLOBAL_UI_PID\nextern int ui_pid[3];\n#endif\n\n/* combo scan */\n#define WEXT_CSCAN_AMOUNT 9\n#define WEXT_CSCAN_BUF_LEN\t\t360\n#define WEXT_CSCAN_HEADER\t\t\"CSCAN S\\x01\\x00\\x00S\\x00\"\n#define WEXT_CSCAN_HEADER_SIZE\t\t12\n#define WEXT_CSCAN_SSID_SECTION\t\t'S'\n#define WEXT_CSCAN_CHANNEL_SECTION\t'C'\n#define WEXT_CSCAN_NPROBE_SECTION\t'N'\n#define WEXT_CSCAN_ACTV_DWELL_SECTION\t'A'\n#define WEXT_CSCAN_PASV_DWELL_SECTION\t'P'\n#define WEXT_CSCAN_HOME_DWELL_SECTION\t'H'\n#define WEXT_CSCAN_TYPE_SECTION\t\t'T'\n\n\nextern u8 key_2char2num(u8 hch, u8 lch);\nextern u8 str_2char2num(u8 hch, u8 lch);\nextern void macstr2num(u8 *dst, u8 *src);\nextern u8 convert_ip_addr(u8 hch, u8 mch, u8 lch);\n\nu32 rtw_rates[] = {1000000, 2000000, 5500000, 11000000,\n\t6000000, 9000000, 12000000, 18000000, 24000000, 36000000, 48000000, 54000000};\n\nstatic const char *const iw_operation_mode[] = {\n\t\"Auto\", \"Ad-Hoc\", \"Managed\",  \"Master\", \"Repeater\", \"Secondary\", \"Monitor\"\n};\n\n/**\n * hwaddr_aton - Convert ASCII string to MAC address\n * @txt: MAC address as a string (e.g., \"00:11:22:33:44:55\")\n * @addr: Buffer for the MAC address (ETH_ALEN = 6 bytes)\n * Returns: 0 on success, -1 on failure (e.g., string not a MAC address)\n */\nstatic int hwaddr_aton_i(const char *txt, u8 *addr)\n{\n\tint i;\n\n\tfor (i = 0; i < 6; i++) {\n\t\tint a, b;\n\n\t\ta = hex2num_i(*txt++);\n\t\tif (a < 0)\n\t\t\treturn -1;\n\t\tb = hex2num_i(*txt++);\n\t\tif (b < 0)\n\t\t\treturn -1;\n\t\t*addr++ = (a << 4) | b;\n\t\tif (i < 5 && *txt++ != ':')\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n#ifdef CONFIG_ANDROID\nstatic void indicate_wx_custom_event(_adapter *padapter, char *msg)\n{\n\tu8 *buff;\n\tunion iwreq_data wrqu;\n\n\tif (strlen(msg) > IW_CUSTOM_MAX) {\n\t\tRTW_INFO(\"%s strlen(msg):%zu > IW_CUSTOM_MAX:%u\\n\", __FUNCTION__ , strlen(msg), IW_CUSTOM_MAX);\n\t\treturn;\n\t}\n\n\tbuff = rtw_zmalloc(IW_CUSTOM_MAX + 1);\n\tif (!buff)\n\t\treturn;\n\n\t_rtw_memcpy(buff, msg, strlen(msg));\n\n\t_rtw_memset(&wrqu, 0, sizeof(wrqu));\n\twrqu.data.length = strlen(msg);\n\n\tRTW_INFO(\"%s %s\\n\", __FUNCTION__, buff);\n#ifndef CONFIG_IOCTL_CFG80211\n\twireless_send_event(padapter->pnetdev, IWEVCUSTOM, &wrqu, buff);\n#endif\n\n\trtw_mfree(buff, IW_CUSTOM_MAX + 1);\n\n}\n#endif\n\n#if 0\nstatic void request_wps_pbc_event(_adapter *padapter)\n{\n\tu8 *buff, *p;\n\tunion iwreq_data wrqu;\n\n\n\tbuff = rtw_malloc(IW_CUSTOM_MAX);\n\tif (!buff)\n\t\treturn;\n\n\t_rtw_memset(buff, 0, IW_CUSTOM_MAX);\n\n\tp = buff;\n\n\tp += sprintf(p, \"WPS_PBC_START.request=TRUE\");\n\n\t_rtw_memset(&wrqu, 0, sizeof(wrqu));\n\n\twrqu.data.length = p - buff;\n\n\twrqu.data.length = (wrqu.data.length < IW_CUSTOM_MAX) ? wrqu.data.length : IW_CUSTOM_MAX;\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n#ifndef CONFIG_IOCTL_CFG80211\n\twireless_send_event(padapter->pnetdev, IWEVCUSTOM, &wrqu, buff);\n#endif\n\n\tif (buff)\n\t\trtw_mfree(buff, IW_CUSTOM_MAX);\n\n}\n#endif\n\n#ifdef CONFIG_SUPPORT_HW_WPS_PBC\nvoid rtw_request_wps_pbc_event(_adapter *padapter)\n{\n#ifdef RTK_DMP_PLATFORM\n#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12))\n\tkobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_NET_PBC);\n#else\n\tkobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_NET_PBC);\n#endif\n#else\n\n\tif (padapter->pid[0] == 0) {\n\t\t/*\t0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver. */\n\t\treturn;\n\t}\n\n\trtw_signal_process(padapter->pid[0], SIGUSR1);\n\n#endif\n\n\trtw_led_control(padapter, LED_CTL_START_WPS_BOTTON);\n}\n#endif/* #ifdef CONFIG_SUPPORT_HW_WPS_PBC */\n\nvoid indicate_wx_scan_complete_event(_adapter *padapter)\n{\n\tunion iwreq_data wrqu;\n\n\t_rtw_memset(&wrqu, 0, sizeof(union iwreq_data));\n\n\t/* RTW_INFO(\"+rtw_indicate_wx_scan_complete_event\\n\"); */\n#ifndef CONFIG_IOCTL_CFG80211\n\twireless_send_event(padapter->pnetdev, SIOCGIWSCAN, &wrqu, NULL);\n#endif\n}\n\n\nvoid rtw_indicate_wx_assoc_event(_adapter *padapter)\n{\n\tunion iwreq_data wrqu;\n\tstruct\tmlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tWLAN_BSSID_EX\t\t*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));\n\n\t_rtw_memset(&wrqu, 0, sizeof(union iwreq_data));\n\n\twrqu.ap_addr.sa_family = ARPHRD_ETHER;\n\n\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)\n\t\t_rtw_memcpy(wrqu.ap_addr.sa_data, pnetwork->MacAddress, ETH_ALEN);\n\telse\n\t\t_rtw_memcpy(wrqu.ap_addr.sa_data, pmlmepriv->cur_network.network.MacAddress, ETH_ALEN);\n\n\tRTW_PRINT(\"assoc success\\n\");\n#ifndef CONFIG_IOCTL_CFG80211\n\twireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL);\n#endif\n}\n\nvoid rtw_indicate_wx_disassoc_event(_adapter *padapter)\n{\n\tunion iwreq_data wrqu;\n\n\t_rtw_memset(&wrqu, 0, sizeof(union iwreq_data));\n\n\twrqu.ap_addr.sa_family = ARPHRD_ETHER;\n\t_rtw_memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN);\n\n#ifndef CONFIG_IOCTL_CFG80211\n\tRTW_PRINT(\"indicate disassoc\\n\");\n\twireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL);\n#endif\n}\n\n/*\nuint\trtw_is_cckrates_included(u8 *rate)\n{\n\t\tu32\ti = 0;\n\n\t\twhile(rate[i]!=0)\n\t\t{\n\t\t\tif  (  (((rate[i]) & 0x7f) == 2)\t|| (((rate[i]) & 0x7f) == 4) ||\n\t\t\t(((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) == 22) )\n\t\t\treturn _TRUE;\n\t\t\ti++;\n\t\t}\n\n\t\treturn _FALSE;\n}\n\nuint\trtw_is_cckratesonly_included(u8 *rate)\n{\n\tu32 i = 0;\n\n\twhile(rate[i]!=0)\n\t{\n\t\t\tif  (  (((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) &&\n\t\t\t\t(((rate[i]) & 0x7f) != 11)  && (((rate[i]) & 0x7f) != 22) )\n\t\t\treturn _FALSE;\n\t\t\ti++;\n\t}\n\n\treturn _TRUE;\n}\n*/\n\nstatic int search_p2p_wfd_ie(_adapter *padapter,\n\t\tstruct iw_request_info *info, struct wlan_network *pnetwork,\n\t\tchar *start, char *stop)\n{\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info\t*pwdinfo = &padapter->wdinfo;\n#ifdef CONFIG_WFD\n\tif (SCAN_RESULT_ALL == pwdinfo->wfd_info->scan_result_type) {\n\n\t} else if ((SCAN_RESULT_P2P_ONLY == pwdinfo->wfd_info->scan_result_type) ||\n\t\t(SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type))\n#endif /* CONFIG_WFD */\n\t{\n\t\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {\n\t\t\tu32\tblnGotP2PIE = _FALSE;\n\n\t\t\t/*\tUser is doing the P2P device discovery */\n\t\t\t/*\tThe prefix of SSID should be \"DIRECT-\" and the IE should contains the P2P IE. */\n\t\t\t/*\tIf not, the driver should ignore this AP and go to the next AP. */\n\n\t\t\t/*\tVerifying the SSID */\n\t\t\tif (_rtw_memcmp(pnetwork->network.Ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN)) {\n\t\t\t\tu32\tp2pielen = 0;\n\n\t\t\t\t/*\tVerifying the P2P IE */\n\t\t\t\tif (rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen))\n\t\t\t\t\tblnGotP2PIE = _TRUE;\n\t\t\t}\n\n\t\t\tif (blnGotP2PIE == _FALSE)\n\t\t\t\treturn _FALSE;\n\n\t\t}\n\t}\n\n#ifdef CONFIG_WFD\n\tif (SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type) {\n\t\tu32\tblnGotWFD = _FALSE;\n\t\tu8 *wfd_ie;\n\t\tuint wfd_ielen = 0;\n\n\t\twfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen);\n\t\tif (wfd_ie) {\n\t\t\tu8 *wfd_devinfo;\n\t\t\tuint wfd_devlen;\n\n\t\t\twfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen);\n\t\t\tif (wfd_devinfo) {\n\t\t\t\tif (pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_PSINK) {\n\t\t\t\t\t/*\tthe first two bits will indicate the WFD device type */\n\t\t\t\t\tif ((wfd_devinfo[1] & 0x03) == WFD_DEVINFO_SOURCE) {\n\t\t\t\t\t\t/*\tIf this device is Miracast PSink device, the scan reuslt should just provide the Miracast source. */\n\t\t\t\t\t\tblnGotWFD = _TRUE;\n\t\t\t\t\t}\n\t\t\t\t} else if (pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_SOURCE) {\n\t\t\t\t\t/*\tthe first two bits will indicate the WFD device type */\n\t\t\t\t\tif ((wfd_devinfo[1] & 0x03) == WFD_DEVINFO_PSINK) {\n\t\t\t\t\t\t/*\tIf this device is Miracast source device, the scan reuslt should just provide the Miracast PSink. */\n\t\t\t\t\t\t/*\tTodo: How about the SSink?! */\n\t\t\t\t\t\tblnGotWFD = _TRUE;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif (blnGotWFD == _FALSE)\n\t\t\treturn _FALSE;\n\t}\n#endif /* CONFIG_WFD */\n\n#endif /* CONFIG_P2P */\n\treturn _TRUE;\n}\nstatic inline char *iwe_stream_mac_addr_proess(_adapter *padapter,\n\t\tstruct iw_request_info *info, struct wlan_network *pnetwork,\n\t\tchar *start, char *stop, struct iw_event *iwe)\n{\n\t/*  AP MAC address */\n\tiwe->cmd = SIOCGIWAP;\n\tiwe->u.ap_addr.sa_family = ARPHRD_ETHER;\n\n\t_rtw_memcpy(iwe->u.ap_addr.sa_data, pnetwork->network.MacAddress, ETH_ALEN);\n\tstart = iwe_stream_add_event(info, start, stop, iwe, IW_EV_ADDR_LEN);\n\treturn start;\n}\nstatic inline char *iwe_stream_essid_proess(_adapter *padapter,\n\t\tstruct iw_request_info *info, struct wlan_network *pnetwork,\n\t\tchar *start, char *stop, struct iw_event *iwe)\n{\n\n\t/* Add the ESSID */\n\tiwe->cmd = SIOCGIWESSID;\n\tiwe->u.data.flags = 1;\n\tiwe->u.data.length = min((u16)pnetwork->network.Ssid.SsidLength, (u16)32);\n\tstart = iwe_stream_add_point(info, start, stop, iwe, pnetwork->network.Ssid.Ssid);\n\treturn start;\n}\n\nstatic inline char *iwe_stream_chan_process(_adapter *padapter,\n\t\tstruct iw_request_info *info, struct wlan_network *pnetwork,\n\t\tchar *start, char *stop, struct iw_event *iwe)\n{\n\tif (pnetwork->network.Configuration.DSConfig < 1 /*|| pnetwork->network.Configuration.DSConfig>14*/)\n\t\tpnetwork->network.Configuration.DSConfig = 1;\n\n\t/* Add frequency/channel */\n\tiwe->cmd = SIOCGIWFREQ;\n\tiwe->u.freq.m = rtw_ch2freq(pnetwork->network.Configuration.DSConfig) * 100000;\n\tiwe->u.freq.e = 1;\n\tiwe->u.freq.i = pnetwork->network.Configuration.DSConfig;\n\tstart = iwe_stream_add_event(info, start, stop, iwe, IW_EV_FREQ_LEN);\n\treturn start;\n}\nstatic inline char *iwe_stream_mode_process(_adapter *padapter,\n\t\tstruct iw_request_info *info, struct wlan_network *pnetwork,\n\t\tchar *start, char *stop, struct iw_event *iwe, u16 cap)\n{\n\t/* Add mode */\n\tif (cap & (WLAN_CAPABILITY_IBSS | WLAN_CAPABILITY_BSS)) {\n\t\tiwe->cmd = SIOCGIWMODE;\n\t\tif (cap & WLAN_CAPABILITY_BSS)\n\t\t\tiwe->u.mode = IW_MODE_MASTER;\n\t\telse\n\t\t\tiwe->u.mode = IW_MODE_ADHOC;\n\n\t\tstart = iwe_stream_add_event(info, start, stop, iwe, IW_EV_UINT_LEN);\n\t}\n\treturn start;\n}\nstatic inline char *iwe_stream_encryption_process(_adapter *padapter,\n\t\tstruct iw_request_info *info, struct wlan_network *pnetwork,\n\t\tchar *start, char *stop, struct iw_event *iwe, u16 cap)\n{\n\n\t/* Add encryption capability */\n\tiwe->cmd = SIOCGIWENCODE;\n\tif (cap & WLAN_CAPABILITY_PRIVACY)\n\t\tiwe->u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;\n\telse\n\t\tiwe->u.data.flags = IW_ENCODE_DISABLED;\n\tiwe->u.data.length = 0;\n\tstart = iwe_stream_add_point(info, start, stop, iwe, pnetwork->network.Ssid.Ssid);\n\treturn start;\n\n}\n\nstatic inline char *iwe_stream_protocol_process(_adapter *padapter,\n\t\tstruct iw_request_info *info, struct wlan_network *pnetwork,\n\t\tchar *start, char *stop, struct iw_event *iwe)\n{\n\tu16 ht_cap = _FALSE, vht_cap = _FALSE;\n\tu32 ht_ielen = 0, vht_ielen = 0;\n\tchar *p;\n\tu8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); /* Probe Request\t */\n\n#ifdef CONFIG_80211N_HT\n\t/* parsing HT_CAP_IE\t */\n\tif(padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode)) {\n\t\tp = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - ie_offset);\n\t\tif (p && ht_ielen > 0)\n\t\t\tht_cap = _TRUE;\n\t}\n#endif\n\n#ifdef CONFIG_80211AC_VHT\n\t/* parsing VHT_CAP_IE */\n\tif(padapter->registrypriv.wireless_mode & WIRELESS_11AC) {\n\t\tp = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset);\n\t\tif (p && vht_ielen > 0)\n\t\t\tvht_cap = _TRUE;\n\t}\n#endif\n\t/* Add the protocol name */\n\tiwe->cmd = SIOCGIWNAME;\n\tif ((rtw_is_cckratesonly_included((u8 *)&pnetwork->network.SupportedRates)) == _TRUE) {\n\t\tif (ht_cap == _TRUE)\n\t\t\tsnprintf(iwe->u.name, IFNAMSIZ, \"IEEE 802.11bn\");\n\t\telse\n\t\t\tsnprintf(iwe->u.name, IFNAMSIZ, \"IEEE 802.11b\");\n\t} else if ((rtw_is_cckrates_included((u8 *)&pnetwork->network.SupportedRates)) == _TRUE) {\n\t\tif (ht_cap == _TRUE)\n\t\t\tsnprintf(iwe->u.name, IFNAMSIZ, \"IEEE 802.11bgn\");\n\t\telse\n\t\t\tsnprintf(iwe->u.name, IFNAMSIZ, \"IEEE 802.11bg\");\n\t} else {\n\t\tif (pnetwork->network.Configuration.DSConfig > 14) {\n\t\t\t#ifdef CONFIG_80211AC_VHT\n\t\t\tif (vht_cap == _TRUE)\n\t\t\t\tsnprintf(iwe->u.name, IFNAMSIZ, \"IEEE 802.11AC\");\n\t\t\telse\n\t\t\t#endif\n\t\t\t{\n\t\t\t\tif (ht_cap == _TRUE)\n\t\t\t\t\tsnprintf(iwe->u.name, IFNAMSIZ, \"IEEE 802.11an\");\n\t\t\t\telse\n\t\t\t\t\tsnprintf(iwe->u.name, IFNAMSIZ, \"IEEE 802.11a\");\n\t\t\t}\n\t\t} else {\n\t\t\tif (ht_cap == _TRUE)\n\t\t\t\tsnprintf(iwe->u.name, IFNAMSIZ, \"IEEE 802.11gn\");\n\t\t\telse\n\t\t\t\tsnprintf(iwe->u.name, IFNAMSIZ, \"IEEE 802.11g\");\n\t\t}\n\t}\n\tstart = iwe_stream_add_event(info, start, stop, iwe, IW_EV_CHAR_LEN);\n\treturn start;\n}\n\nstatic inline char *iwe_stream_rate_process(_adapter *padapter,\n\t\tstruct iw_request_info *info, struct wlan_network *pnetwork,\n\t\tchar *start, char *stop, struct iw_event *iwe)\n{\n\tu32 ht_ielen = 0, vht_ielen = 0;\n\tchar *p;\n\tu16 max_rate = 0, rate, ht_cap = _FALSE, vht_cap = _FALSE;\n\tu32 i = 0;\n\tu8 bw_40MHz = 0, short_GI = 0, bw_160MHz = 0, vht_highest_rate = 0;\n\tu16 mcs_rate = 0, vht_data_rate = 0;\n\tchar custom[MAX_CUSTOM_LEN] = {0};\n\tu8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); /* Probe Request\t */\n\n\t/* parsing HT_CAP_IE\t */\n\tif(is_supported_ht(padapter->registrypriv.wireless_mode)) {\n\t\tp = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - ie_offset);\n\t\tif (p && ht_ielen > 0) {\n\t\t\tstruct rtw_ieee80211_ht_cap *pht_capie;\n\t\t\tht_cap = _TRUE;\n\t\t\tpht_capie = (struct rtw_ieee80211_ht_cap *)(p + 2);\n\t\t\t_rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2);\n\t\t\tbw_40MHz = (pht_capie->cap_info & IEEE80211_HT_CAP_SUP_WIDTH) ? 1 : 0;\n\t\t\tshort_GI = (pht_capie->cap_info & (IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40)) ? 1 : 0;\n\t\t}\n\t}\n#ifdef CONFIG_80211AC_VHT\n\t/* parsing VHT_CAP_IE */\n\tif(padapter->registrypriv.wireless_mode & WIRELESS_11AC){\n\t\tp = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset);\n\t\tif (p && vht_ielen > 0) {\n\t\t\tu8\tmcs_map[2];\n\n\t\t\tvht_cap = _TRUE;\n\t\t\tbw_160MHz = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p + 2);\n\t\t\tif (bw_160MHz)\n\t\t\t\tshort_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI160M(p + 2);\n\t\t\telse\n\t\t\t\tshort_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI80M(p + 2);\n\n\t\t\t_rtw_memcpy(mcs_map, GET_VHT_CAPABILITY_ELE_TX_MCS(p + 2), 2);\n\n\t\t\tvht_highest_rate = rtw_get_vht_highest_rate(mcs_map);\n\t\t\tvht_data_rate = rtw_vht_mcs_to_data_rate(CHANNEL_WIDTH_80, short_GI, vht_highest_rate);\n\t\t}\n\t}\n#endif\n\n\t/*Add basic and extended rates */\n\tp = custom;\n\tp += snprintf(p, MAX_CUSTOM_LEN - (p - custom), \" Rates (Mb/s): \");\n\twhile (pnetwork->network.SupportedRates[i] != 0) {\n\t\trate = pnetwork->network.SupportedRates[i] & 0x7F;\n\t\tif (rate > max_rate)\n\t\t\tmax_rate = rate;\n\t\tp += snprintf(p, MAX_CUSTOM_LEN - (p - custom),\n\t\t\t      \"%d%s \", rate >> 1, (rate & 1) ? \".5\" : \"\");\n\t\ti++;\n\t}\n#ifdef CONFIG_80211AC_VHT\n\tif (vht_cap == _TRUE)\n\t\tmax_rate = vht_data_rate;\n\telse\n#endif\n\t\tif (ht_cap == _TRUE) {\n\t\t\tif (mcs_rate & 0x8000) /* MCS15 */\n\t\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 300 : 270) : ((short_GI) ? 144 : 130);\n\n\t\t\telse if (mcs_rate & 0x0080) /* MCS7 */\n\t\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65);\n\t\t\telse { /* default MCS7 */\n\t\t\t\t/* RTW_INFO(\"wx_get_scan, mcs_rate_bitmap=0x%x\\n\", mcs_rate); */\n\t\t\t\tmax_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65);\n\t\t\t}\n\n\t\t\tmax_rate = max_rate * 2; /* Mbps/2;\t\t */\n\t\t}\n\n\tiwe->cmd = SIOCGIWRATE;\n\tiwe->u.bitrate.fixed = iwe->u.bitrate.disabled = 0;\n\tiwe->u.bitrate.value = max_rate * 500000;\n\tstart = iwe_stream_add_event(info, start, stop, iwe, IW_EV_PARAM_LEN);\n\treturn start ;\n}\n\nstatic inline char *iwe_stream_wpa_wpa2_process(_adapter *padapter,\n\t\tstruct iw_request_info *info, struct wlan_network *pnetwork,\n\t\tchar *start, char *stop, struct iw_event *iwe)\n{\n\tint buf_size = MAX_WPA_IE_LEN * 2;\n\t/* u8 pbuf[buf_size]={0};\t */\n\tu8 *pbuf = rtw_zmalloc(buf_size);\n\n\tu8 wpa_ie[255] = {0}, rsn_ie[255] = {0};\n\tu16 i, wpa_len = 0, rsn_len = 0;\n\tu8 *p;\n\tsint out_len = 0;\n\n\n\tif (pbuf) {\n\t\tp = pbuf;\n\n\t\t/* parsing WPA/WPA2 IE */\n\t\tif (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ) { /* Probe Request */\n\t\t\tout_len = rtw_get_sec_ie(pnetwork->network.IEs , pnetwork->network.IELength, rsn_ie, &rsn_len, wpa_ie, &wpa_len);\n\n\t\t\tif (wpa_len > 0) {\n\n\t\t\t\t_rtw_memset(pbuf, 0, buf_size);\n\t\t\t\tp += sprintf(p, \"wpa_ie=\");\n\t\t\t\tfor (i = 0; i < wpa_len; i++)\n\t\t\t\t\tp += sprintf(p, \"%02x\", wpa_ie[i]);\n\n\t\t\t\tif (wpa_len > 100) {\n\t\t\t\t\tprintk(\"-----------------Len %d----------------\\n\", wpa_len);\n\t\t\t\t\tfor (i = 0; i < wpa_len; i++)\n\t\t\t\t\t\tprintk(\"%02x \", wpa_ie[i]);\n\t\t\t\t\tprintk(\"\\n\");\n\t\t\t\t\tprintk(\"-----------------Len %d----------------\\n\", wpa_len);\n\t\t\t\t}\n\n\t\t\t\t_rtw_memset(iwe, 0, sizeof(*iwe));\n\t\t\t\tiwe->cmd = IWEVCUSTOM;\n\t\t\t\tiwe->u.data.length = strlen(pbuf);\n\t\t\t\tstart = iwe_stream_add_point(info, start, stop, iwe, pbuf);\n\n\t\t\t\t_rtw_memset(iwe, 0, sizeof(*iwe));\n\t\t\t\tiwe->cmd = IWEVGENIE;\n\t\t\t\tiwe->u.data.length = wpa_len;\n\t\t\t\tstart = iwe_stream_add_point(info, start, stop, iwe, wpa_ie);\n\t\t\t}\n\t\t\tif (rsn_len > 0) {\n\n\t\t\t\t_rtw_memset(pbuf, 0, buf_size);\n\t\t\t\tp += sprintf(p, \"rsn_ie=\");\n\t\t\t\tfor (i = 0; i < rsn_len; i++)\n\t\t\t\t\tp += sprintf(p, \"%02x\", rsn_ie[i]);\n\t\t\t\t_rtw_memset(iwe, 0, sizeof(*iwe));\n\t\t\t\tiwe->cmd = IWEVCUSTOM;\n\t\t\t\tiwe->u.data.length = strlen(pbuf);\n\t\t\t\tstart = iwe_stream_add_point(info, start, stop, iwe, pbuf);\n\n\t\t\t\t_rtw_memset(iwe, 0, sizeof(*iwe));\n\t\t\t\tiwe->cmd = IWEVGENIE;\n\t\t\t\tiwe->u.data.length = rsn_len;\n\t\t\t\tstart = iwe_stream_add_point(info, start, stop, iwe, rsn_ie);\n\t\t\t}\n\t\t}\n\n\t\trtw_mfree(pbuf, buf_size);\n\t}\n\treturn start;\n}\n\nstatic inline char *iwe_stream_wps_process(_adapter *padapter,\n\t\tstruct iw_request_info *info, struct wlan_network *pnetwork,\n\t\tchar *start, char *stop, struct iw_event *iwe)\n{\n\t/* parsing WPS IE */\n\tuint cnt = 0, total_ielen;\n\tu8 *wpsie_ptr = NULL;\n\tuint wps_ielen = 0;\n\tu8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12);\n\n\tu8 *ie_ptr = pnetwork->network.IEs + ie_offset;\n\ttotal_ielen = pnetwork->network.IELength - ie_offset;\n\n\tif (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ) { /* Probe Request */\n\t\tie_ptr = pnetwork->network.IEs;\n\t\ttotal_ielen = pnetwork->network.IELength;\n\t} else { /* Beacon or Probe Respones */\n\t\tie_ptr = pnetwork->network.IEs + _FIXED_IE_LENGTH_;\n\t\ttotal_ielen = pnetwork->network.IELength - _FIXED_IE_LENGTH_;\n\t}\n\twhile (cnt < total_ielen) {\n\t\tif (rtw_is_wps_ie(&ie_ptr[cnt], &wps_ielen) && (wps_ielen > 2)) {\n\t\t\twpsie_ptr = &ie_ptr[cnt];\n\t\t\tiwe->cmd = IWEVGENIE;\n\t\t\tiwe->u.data.length = (u16)wps_ielen;\n\t\t\tstart = iwe_stream_add_point(info, start, stop, iwe, wpsie_ptr);\n\t\t}\n\t\tcnt += ie_ptr[cnt + 1] + 2; /* goto next */\n\t}\n\treturn start;\n}\n\nstatic inline char *iwe_stream_wapi_process(_adapter *padapter,\n\t\tstruct iw_request_info *info, struct wlan_network *pnetwork,\n\t\tchar *start, char *stop, struct iw_event *iwe)\n{\n#ifdef CONFIG_WAPI_SUPPORT\n\tchar *p;\n\n\tif (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ) { /* Probe Request */\n\t\tsint out_len_wapi = 0;\n\t\t/* here use static for stack size */\n\t\tstatic u8 buf_wapi[MAX_WAPI_IE_LEN * 2] = {0};\n\t\tstatic u8 wapi_ie[MAX_WAPI_IE_LEN] = {0};\n\t\tu16 wapi_len = 0;\n\t\tu16  i;\n\n\t\tout_len_wapi = rtw_get_wapi_ie(pnetwork->network.IEs , pnetwork->network.IELength, wapi_ie, &wapi_len);\n\n\t\tRTW_INFO(\"rtw_wx_get_scan: %s \", pnetwork->network.Ssid.Ssid);\n\t\tRTW_INFO(\"rtw_wx_get_scan: ssid = %d \", wapi_len);\n\n\n\t\tif (wapi_len > 0) {\n\t\t\tp = buf_wapi;\n\t\t\t/* _rtw_memset(buf_wapi, 0, MAX_WAPI_IE_LEN*2); */\n\t\t\tp += sprintf(p, \"wapi_ie=\");\n\t\t\tfor (i = 0; i < wapi_len; i++)\n\t\t\t\tp += sprintf(p, \"%02x\", wapi_ie[i]);\n\n\t\t\t_rtw_memset(iwe, 0, sizeof(*iwe));\n\t\t\tiwe->cmd = IWEVCUSTOM;\n\t\t\tiwe->u.data.length = strlen(buf_wapi);\n\t\t\tstart = iwe_stream_add_point(info, start, stop, iwe, buf_wapi);\n\n\t\t\t_rtw_memset(iwe, 0, sizeof(*iwe));\n\t\t\tiwe->cmd = IWEVGENIE;\n\t\t\tiwe->u.data.length = wapi_len;\n\t\t\tstart = iwe_stream_add_point(info, start, stop, iwe, wapi_ie);\n\t\t}\n\t}\n#endif/* #ifdef CONFIG_WAPI_SUPPORT */\n\treturn start;\n}\n\nstatic inline char   *iwe_stream_rssi_process(_adapter *padapter,\n\t\tstruct iw_request_info *info, struct wlan_network *pnetwork,\n\t\tchar *start, char *stop, struct iw_event *iwe)\n{\n\tu8 ss, sq;\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n#ifdef CONFIG_BACKGROUND_NOISE_MONITOR\n\ts16 noise = 0;\n#endif\n\n\t/* Add quality statistics */\n\tiwe->cmd = IWEVQUAL;\n\tiwe->u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED\n#ifdef CONFIG_BACKGROUND_NOISE_MONITOR\n\t\t\t      | IW_QUAL_NOISE_UPDATED\n#else\n\t\t\t      | IW_QUAL_NOISE_INVALID\n#endif\n#ifdef CONFIG_SIGNAL_DISPLAY_DBM\n\t\t\t      | IW_QUAL_DBM\n#endif\n\t\t\t      ;\n\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE &&\n\t    is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) {\n\t\tss = padapter->recvpriv.signal_strength;\n\t\tsq = padapter->recvpriv.signal_qual;\n\t} else {\n\t\tss = pnetwork->network.PhyInfo.SignalStrength;\n\t\tsq = pnetwork->network.PhyInfo.SignalQuality;\n\t}\n\n\n#ifdef CONFIG_SIGNAL_DISPLAY_DBM\n\tiwe->u.qual.level = (u8) translate_percentage_to_dbm(ss); /* dbm */\n#else\n\tiwe->u.qual.level = (u8)ss; /* % */\n#endif\n\n\tiwe->u.qual.qual = (u8)sq;   /* signal quality */\n\n#ifdef CONFIG_PLATFORM_ROCKCHIPS\n\tiwe->u.qual.noise = -100; /* noise level suggest by zhf@rockchips */\n#else\n#ifdef CONFIG_BACKGROUND_NOISE_MONITOR\n\tif (IS_NM_ENABLE(padapter)) {\n\t\tnoise = rtw_noise_query_by_chan_num(padapter, pnetwork->network.Configuration.DSConfig);\n\t\t#ifndef CONFIG_SIGNAL_DISPLAY_DBM\n\t\tnoise = translate_dbm_to_percentage(noise);/*percentage*/\n\t\t#endif\n\t\tiwe->u.qual.noise = noise;\n\t}\n#else\n\tiwe->u.qual.noise = 0; /* noise level */\n#endif\n#endif /* CONFIG_PLATFORM_ROCKCHIPS */\n\n\t/* RTW_INFO(\"iqual=%d, ilevel=%d, inoise=%d, iupdated=%d\\n\", iwe.u.qual.qual, iwe.u.qual.level , iwe.u.qual.noise, iwe.u.qual.updated); */\n\n\tstart = iwe_stream_add_event(info, start, stop, iwe, IW_EV_QUAL_LEN);\n\treturn start;\n}\n\nstatic inline char   *iwe_stream_net_rsv_process(_adapter *padapter,\n\t\tstruct iw_request_info *info, struct wlan_network *pnetwork,\n\t\tchar *start, char *stop, struct iw_event *iwe)\n{\n\tu8 buf[32] = {0};\n\tu8 *p, *pos;\n\tp = buf;\n\tpos = pnetwork->network.Reserved;\n\n\tp += sprintf(p, \"fm=%02X%02X\", pos[1], pos[0]);\n\t_rtw_memset(iwe, 0, sizeof(*iwe));\n\tiwe->cmd = IWEVCUSTOM;\n\tiwe->u.data.length = strlen(buf);\n\tstart = iwe_stream_add_point(info, start, stop, iwe, buf);\n\treturn start;\n}\n\nstatic char *translate_scan(_adapter *padapter,\n\t\tstruct iw_request_info *info, struct wlan_network *pnetwork,\n\t\tchar *start, char *stop)\n{\n\tstruct iw_event iwe;\n\tu16 cap = 0;\n\t_rtw_memset(&iwe, 0, sizeof(iwe));\n\n\tif (_FALSE == search_p2p_wfd_ie(padapter, info, pnetwork, start, stop))\n\t\treturn start;\n\n\tstart = iwe_stream_mac_addr_proess(padapter, info, pnetwork, start, stop, &iwe);\n\tstart = iwe_stream_essid_proess(padapter, info, pnetwork, start, stop, &iwe);\n\tstart = iwe_stream_protocol_process(padapter, info, pnetwork, start, stop, &iwe);\n\tif (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ) /* Probe Request */\n\t\tcap = 0;\n\telse {\n\t\t_rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2);\n\t\tcap = le16_to_cpu(cap);\n\t}\n\n\tstart = iwe_stream_mode_process(padapter, info, pnetwork, start, stop, &iwe, cap);\n\tstart = iwe_stream_chan_process(padapter, info, pnetwork, start, stop, &iwe);\n\tstart = iwe_stream_encryption_process(padapter, info, pnetwork, start, stop, &iwe, cap);\n\tstart = iwe_stream_rate_process(padapter, info, pnetwork, start, stop, &iwe);\n\tstart = iwe_stream_wpa_wpa2_process(padapter, info, pnetwork, start, stop, &iwe);\n\tstart = iwe_stream_wps_process(padapter, info, pnetwork, start, stop, &iwe);\n\tstart = iwe_stream_wapi_process(padapter, info, pnetwork, start, stop, &iwe);\n\tstart = iwe_stream_rssi_process(padapter, info, pnetwork, start, stop, &iwe);\n\tstart = iwe_stream_net_rsv_process(padapter, info, pnetwork, start, stop, &iwe);\n\n\treturn start;\n}\n\nstatic int wpa_set_auth_algs(struct net_device *dev, u32 value)\n{\n\t_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);\n\tint ret = 0;\n\n\tif ((value & AUTH_ALG_SHARED_KEY) && (value & AUTH_ALG_OPEN_SYSTEM)) {\n\t\tRTW_INFO(\"wpa_set_auth_algs, AUTH_ALG_SHARED_KEY and  AUTH_ALG_OPEN_SYSTEM [value:0x%x]\\n\", value);\n\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;\n\t\tpadapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch;\n\t\tpadapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;\n\t} else if (value & AUTH_ALG_SHARED_KEY) {\n\t\tRTW_INFO(\"wpa_set_auth_algs, AUTH_ALG_SHARED_KEY  [value:0x%x]\\n\", value);\n\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;\n\n#ifdef CONFIG_PLATFORM_MT53XX\n\t\tpadapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch;\n\t\tpadapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;\n#else\n\t\tpadapter->securitypriv.ndisauthtype = Ndis802_11AuthModeShared;\n\t\tpadapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Shared;\n#endif\n\t} else if (value & AUTH_ALG_OPEN_SYSTEM) {\n\t\tRTW_INFO(\"wpa_set_auth_algs, AUTH_ALG_OPEN_SYSTEM\\n\");\n\t\t/* padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; */\n\t\tif (padapter->securitypriv.ndisauthtype < Ndis802_11AuthModeWPAPSK) {\n#ifdef CONFIG_PLATFORM_MT53XX\n\t\t\tpadapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch;\n\t\t\tpadapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;\n#else\n\t\t\tpadapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;\n\t\t\tpadapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open;\n#endif\n\t\t}\n\n\t} else if (value & AUTH_ALG_LEAP)\n\t\tRTW_INFO(\"wpa_set_auth_algs, AUTH_ALG_LEAP\\n\");\n\telse {\n\t\tRTW_INFO(\"wpa_set_auth_algs, error!\\n\");\n\t\tret = -EINVAL;\n\t}\n\n\treturn ret;\n\n}\n\nstatic int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len)\n{\n\tint ret = 0;\n\tu32 wep_key_idx, wep_key_len;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *pwdinfo = &padapter->wdinfo;\n#endif /* CONFIG_P2P */\n\n\n\tparam->u.crypt.err = 0;\n\tparam->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\\0';\n\n\tif (param_len < (u32)((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) {\n\t\tret =  -EINVAL;\n\t\tgoto exit;\n\t}\n\n\tif (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&\n\t    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&\n\t    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) {\n\n\t\tif (param->u.crypt.idx >= WEP_KEYS\n#ifdef CONFIG_IEEE80211W\n\t\t    && param->u.crypt.idx > BIP_MAX_KEYID\n#endif /* CONFIG_IEEE80211W */\n\t\t   ) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t} else {\n#ifdef CONFIG_WAPI_SUPPORT\n\t\tif (strcmp(param->u.crypt.alg, \"SMS4\"))\n#endif\n\t\t{\n\t\t\tret = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\tif (strcmp(param->u.crypt.alg, \"WEP\") == 0) {\n\t\tRTW_INFO(\"wpa_set_encryption, crypt.alg = WEP\\n\");\n\n\t\twep_key_idx = param->u.crypt.idx;\n\t\twep_key_len = param->u.crypt.key_len;\n\n\t\tif ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (psecuritypriv->bWepDefaultKeyIdxSet == 0) {\n\t\t\t/* wep default key has not been set, so use this key index as default key.*/\n\n\t\t\twep_key_len = wep_key_len <= 5 ? 5 : 13;\n\n\t\t\tpsecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;\n\t\t\tpsecuritypriv->dot11PrivacyAlgrthm = _WEP40_;\n\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _WEP40_;\n\n\t\t\tif (wep_key_len == 13) {\n\t\t\t\tpsecuritypriv->dot11PrivacyAlgrthm = _WEP104_;\n\t\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _WEP104_;\n\t\t\t}\n\n\t\t\tpsecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;\n\t\t}\n\n\t\t_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len);\n\n\t\tpsecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len;\n\n\t\tpsecuritypriv->key_mask |= BIT(wep_key_idx);\n\n\t\tpadapter->mlmeextpriv.mlmext_info.key_index = wep_key_idx;\n\t\tgoto exit;\n\t}\n\n\tif (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { /* 802_1x */\n\t\tstruct sta_info *psta, *pbcmc_sta;\n\t\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) { /* sta mode */\n\t\t\tpsta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));\n\t\t\tif (psta == NULL) {\n\t\t\t\t/* DEBUG_ERR( (\"Set wpa_set_encryption: Obtain Sta_info fail\\n\")); */\n\t\t\t} else {\n\t\t\t\t/* Jeff: don't disable ieee8021x_blocked while clearing key */\n\t\t\t\tif (strcmp(param->u.crypt.alg, \"none\") != 0)\n\t\t\t\t\tpsta->ieee8021x_blocked = _FALSE;\n\n\t\t\t\tif ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) ||\n\t\t\t\t    (padapter->securitypriv.ndisencryptstatus ==  Ndis802_11Encryption3Enabled))\n\t\t\t\t\tpsta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;\n\n\t\t\t\tif (param->u.crypt.set_tx == 1) { /* pairwise key */\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set %s PTK idx:%u, len:%u\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\t\t_rtw_memcpy(psta->dot118021x_UncstKey.skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\t\t\t\t\tif (strcmp(param->u.crypt.alg, \"TKIP\") == 0) { /* set mic key */\n\t\t\t\t\t\t_rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);\n\t\t\t\t\t\t_rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);\n\t\t\t\t\t\tpadapter->securitypriv.busetkipkey = _FALSE;\n\t\t\t\t\t}\n\t\t\t\t\tpsta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);\n\t\t\t\t\tpsta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq);\n\t\t\t\t\tpsta->bpairwise_key_installed = _TRUE;\n\t\t\t\t\trtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _TRUE);\n\n\t\t\t\t} else { /* group key */\n\t\t\t\t\tif (strcmp(param->u.crypt.alg, \"TKIP\") == 0 || strcmp(param->u.crypt.alg, \"CCMP\") == 0) {\n\t\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set %s GTK idx:%u, len:%u\\n\"\n\t\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\t\t\t_rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key,\n\t\t\t\t\t\t\t(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\t\t\t\t\t\t/* only TKIP group key need to install this */\n\t\t\t\t\t\tif (param->u.crypt.key_len > 16) {\n\t\t\t\t\t\t\t_rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);\n\t\t\t\t\t\t\t_rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);\n\t\t\t\t\t\t}\n\t\t\t\t\t\tpadapter->securitypriv.binstallGrpkey = _TRUE;\n\t\t\t\t\t\tif (param->u.crypt.idx < 4)\n\t\t\t\t\t\t\t_rtw_memcpy(padapter->securitypriv.iv_seq[param->u.crypt.idx], param->u.crypt.seq, 8);\n\t\t\t\t\t\tpadapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx;\n\t\t\t\t\t\trtw_set_key(padapter, &padapter->securitypriv, param->u.crypt.idx, 1, _TRUE);\n\n\t\t\t\t\t#ifdef CONFIG_IEEE80211W\n\t\t\t\t\t} else if (strcmp(param->u.crypt.alg, \"BIP\") == 0) {\n\t\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set IGTK idx:%u, len:%u\\n\"\n\t\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\t\t\t_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey,  param->u.crypt.key,\n\t\t\t\t\t\t\t(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\t\t\t\t\t\tpsecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;\n\t\t\t\t\t\tpsecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq);\n\t\t\t\t\t\tpsecuritypriv->binstallBIPkey = _TRUE;\n\t\t\t\t\t#endif /* CONFIG_IEEE80211W */\n\n\t\t\t\t\t}\n\n#ifdef CONFIG_P2P\n\t\t\t\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))\n\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE);\n#endif /* CONFIG_P2P */\n\n\t\t\t\t\t/* WPA/WPA2 key-handshake has completed */\n\t\t\t\t\tclr_fwstate(pmlmepriv, WIFI_UNDER_KEY_HANDSHAKE);\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tpbcmc_sta = rtw_get_bcmc_stainfo(padapter);\n\t\t\tif (pbcmc_sta == NULL) {\n\t\t\t\t/* DEBUG_ERR( (\"Set OID_802_11_ADD_KEY: bcmc stainfo is null\\n\")); */\n\t\t\t} else {\n\t\t\t\t/* Jeff: don't disable ieee8021x_blocked while clearing key */\n\t\t\t\tif (strcmp(param->u.crypt.alg, \"none\") != 0)\n\t\t\t\t\tpbcmc_sta->ieee8021x_blocked = _FALSE;\n\n\t\t\t\tif ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) ||\n\t\t\t\t    (padapter->securitypriv.ndisencryptstatus ==  Ndis802_11Encryption3Enabled))\n\t\t\t\t\tpbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;\n\t\t\t}\n\t\t} else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) { /* adhoc mode */\n\t\t}\n\t}\n\n#ifdef CONFIG_WAPI_SUPPORT\n\tif (strcmp(param->u.crypt.alg, \"SMS4\") == 0)\n\t\trtw_wapi_set_set_encryption(padapter, param);\n#endif\n\nexit:\n\n\n\treturn ret;\n}\n\nstatic int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen)\n{\n\tu8 *buf = NULL, *pos = NULL;\n\tint group_cipher = 0, pairwise_cipher = 0;\n\tu8 mfp_opt = MFP_NO;\n\tint ret = 0;\n\tu8 null_addr[] = {0, 0, 0, 0, 0, 0};\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *pwdinfo = &padapter->wdinfo;\n#endif /* CONFIG_P2P */\n\n\tif ((ielen > MAX_WPA_IE_LEN) || (pie == NULL)) {\n\t\t_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);\n\t\tif (pie == NULL)\n\t\t\treturn ret;\n\t\telse\n\t\t\treturn -EINVAL;\n\t}\n\n\tif (ielen) {\n\t\tbuf = rtw_zmalloc(ielen);\n\t\tif (buf == NULL) {\n\t\t\tret =  -ENOMEM;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t_rtw_memcpy(buf, pie , ielen);\n\n\t\t/* dump */\n\t\t{\n\t\t\tint i;\n\t\t\tRTW_INFO(\"\\n wpa_ie(length:%d):\\n\", ielen);\n\t\t\tfor (i = 0; i < ielen; i = i + 8)\n\t\t\t\tRTW_INFO(\"0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x\\n\", buf[i], buf[i + 1], buf[i + 2], buf[i + 3], buf[i + 4], buf[i + 5], buf[i + 6], buf[i + 7]);\n\t\t}\n\n\t\tpos = buf;\n\t\tif (ielen < RSN_HEADER_LEN) {\n\t\t\tret  = -1;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (rtw_parse_wpa_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {\n\t\t\tpadapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;\n\t\t\tpadapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK;\n\t\t\t_rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen);\n\t\t}\n\n\t\tif (rtw_parse_wpa2_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL, &mfp_opt) == _SUCCESS) {\n\t\t\tpadapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;\n\t\t\tpadapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK;\n\t\t\t_rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen);\n\t\t}\n\n\t\tif (group_cipher == 0)\n\t\t\tgroup_cipher = WPA_CIPHER_NONE;\n\t\tif (pairwise_cipher == 0)\n\t\t\tpairwise_cipher = WPA_CIPHER_NONE;\n\n\t\tswitch (group_cipher) {\n\t\tcase WPA_CIPHER_NONE:\n\t\t\tpadapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;\n\t\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;\n\t\t\tbreak;\n\t\tcase WPA_CIPHER_WEP40:\n\t\t\tpadapter->securitypriv.dot118021XGrpPrivacy = _WEP40_;\n\t\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;\n\t\t\tbreak;\n\t\tcase WPA_CIPHER_TKIP:\n\t\t\tpadapter->securitypriv.dot118021XGrpPrivacy = _TKIP_;\n\t\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;\n\t\t\tbreak;\n\t\tcase WPA_CIPHER_CCMP:\n\t\t\tpadapter->securitypriv.dot118021XGrpPrivacy = _AES_;\n\t\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;\n\t\t\tbreak;\n\t\tcase WPA_CIPHER_WEP104:\n\t\t\tpadapter->securitypriv.dot118021XGrpPrivacy = _WEP104_;\n\t\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;\n\t\t\tbreak;\n\t\t}\n\n\t\tswitch (pairwise_cipher) {\n\t\tcase WPA_CIPHER_NONE:\n\t\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;\n\t\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;\n\t\t\tbreak;\n\t\tcase WPA_CIPHER_WEP40:\n\t\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_;\n\t\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;\n\t\t\tbreak;\n\t\tcase WPA_CIPHER_TKIP:\n\t\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _TKIP_;\n\t\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;\n\t\t\tbreak;\n\t\tcase WPA_CIPHER_CCMP:\n\t\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _AES_;\n\t\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;\n\t\t\tbreak;\n\t\tcase WPA_CIPHER_WEP104:\n\t\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;\n\t\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (mfp_opt == MFP_INVALID) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" invalid MFP setting\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\tret = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tpadapter->securitypriv.mfp_opt = mfp_opt;\n\n\t\t_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);\n\t\t{/* set wps_ie\t */\n\t\t\tu16 cnt = 0;\n\t\t\tu8 eid, wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};\n\n\t\t\twhile (cnt < ielen) {\n\t\t\t\teid = buf[cnt];\n\n\t\t\t\tif ((eid == _VENDOR_SPECIFIC_IE_) && (_rtw_memcmp(&buf[cnt + 2], wps_oui, 4) == _TRUE)) {\n\t\t\t\t\tRTW_INFO(\"SET WPS_IE\\n\");\n\n\t\t\t\t\tpadapter->securitypriv.wps_ie_len = ((buf[cnt + 1] + 2) < MAX_WPS_IE_LEN) ? (buf[cnt + 1] + 2) : MAX_WPS_IE_LEN;\n\n\t\t\t\t\t_rtw_memcpy(padapter->securitypriv.wps_ie, &buf[cnt], padapter->securitypriv.wps_ie_len);\n\n\t\t\t\t\tset_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS);\n\n#ifdef CONFIG_P2P\n\t\t\t\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK))\n\t\t\t\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_ING);\n#endif /* CONFIG_P2P */\n\t\t\t\t\tcnt += buf[cnt + 1] + 2;\n\n\t\t\t\t\tbreak;\n\t\t\t\t} else {\n\t\t\t\t\tcnt += buf[cnt + 1] + 2; /* goto next\t */\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t/* TKIP and AES disallow multicast packets until installing group key */\n\tif (padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_\n\t    || padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_\n\t    || padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)\n\t\t/* WPS open need to enable multicast\n\t\t * || check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE) */\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr);\n\n\nexit:\n\n\tif (buf)\n\t\trtw_mfree(buf, ielen);\n\n\treturn ret;\n}\n\nstatic int rtw_wx_get_name(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu32 ht_ielen = 0;\n\tchar *p;\n\tu8 ht_cap = _FALSE, vht_cap = _FALSE;\n\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tWLAN_BSSID_EX  *pcur_bss = &pmlmepriv->cur_network.network;\n\tNDIS_802_11_RATES_EX *prates = NULL;\n\n\n\n\tif (check_fwstate(pmlmepriv, _FW_LINKED | WIFI_ADHOC_MASTER_STATE) == _TRUE) {\n\t\t/* parsing HT_CAP_IE */\n\t\tif( is_supported_ht(padapter->registrypriv.wireless_mode)&&(padapter->registrypriv.ht_enable)) {\n\t\t\tp = rtw_get_ie(&pcur_bss->IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pcur_bss->IELength - 12);\n\t\t\tif (p && ht_ielen > 0 )\n\t\t\t\tht_cap = _TRUE;\n\t\t}\n#ifdef CONFIG_80211AC_VHT\n\t\tif ((padapter->registrypriv.wireless_mode & WIRELESS_11AC) &&\n\t\t\t(pmlmepriv->vhtpriv.vht_option == _TRUE))\n\t\t\tvht_cap = _TRUE;\n#endif\n\n\t\tprates = &pcur_bss->SupportedRates;\n\t\tif (rtw_is_cckratesonly_included((u8 *)prates) == _TRUE) {\n\t\t\tif (ht_cap == _TRUE)\n\t\t\t\tsnprintf(wrqu->name, IFNAMSIZ, \"IEEE 802.11bn\");\n\t\t\telse\n\t\t\t\tsnprintf(wrqu->name, IFNAMSIZ, \"IEEE 802.11b\");\n\t\t} else if ((rtw_is_cckrates_included((u8 *)prates)) == _TRUE) {\n\t\t\tif (ht_cap == _TRUE)\n\t\t\t\tsnprintf(wrqu->name, IFNAMSIZ, \"IEEE 802.11bgn\");\n\t\t\telse {\n\t\t\t\tif(padapter->registrypriv.wireless_mode & WIRELESS_11G)\n\t\t\t\t\tsnprintf(wrqu->name, IFNAMSIZ, \"IEEE 802.11bg\");\n\t\t\t\telse\n\t\t\t\t\tsnprintf(wrqu->name, IFNAMSIZ, \"IEEE 802.11b\");\n\t\t\t}\n\t\t} else {\n\t\t\tif (pcur_bss->Configuration.DSConfig > 14) {\n#ifdef CONFIG_80211AC_VHT\n\t\t\t\tif (vht_cap == _TRUE)\n\t\t\t\t\tsnprintf(wrqu->name, IFNAMSIZ, \"IEEE 802.11AC\");\n\t\t\t\telse\n#endif\n\t\t\t\t{\n\t\t\t\t\tif (ht_cap == _TRUE)\n\t\t\t\t\t\tsnprintf(wrqu->name, IFNAMSIZ, \"IEEE 802.11an\");\n\t\t\t\t\telse\n\t\t\t\t\t\tsnprintf(wrqu->name, IFNAMSIZ, \"IEEE 802.11a\");\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif (ht_cap == _TRUE)\n\t\t\t\t\tsnprintf(wrqu->name, IFNAMSIZ, \"IEEE 802.11gn\");\n\t\t\t\telse\n\t\t\t\t\tsnprintf(wrqu->name, IFNAMSIZ, \"IEEE 802.11g\");\n\t\t\t}\n\t\t}\n\t} else {\n\t\t/* prates = &padapter->registrypriv.dev_network.SupportedRates; */\n\t\t/* snprintf(wrqu->name, IFNAMSIZ, \"IEEE 802.11g\"); */\n\t\tsnprintf(wrqu->name, IFNAMSIZ, \"unassociated\");\n\t}\n\n\n\treturn 0;\n}\n\nstatic int rtw_wx_set_freq(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tint exp = 1, freq = 0, div = 0;\n\n\trtw_ps_deny(padapter, PS_DENY_IOCTL);\n\tif (rtw_pwr_wakeup(padapter) == _FALSE)\n\t\tgoto exit;\n\tif (wrqu->freq.m <= 1000) {\n\t\tif (wrqu->freq.flags == IW_FREQ_AUTO) {\n\t\t\tif (rtw_chset_search_ch(adapter_to_chset(padapter), wrqu->freq.m) > 0) {\n\t\t\t\tpadapter->mlmeextpriv.cur_channel = wrqu->freq.m;\n\t\t\t\tRTW_INFO(\"%s: channel is auto, set to channel %d\\n\", __func__, wrqu->freq.m);\n\t\t\t} else {\n\t\t\t\tpadapter->mlmeextpriv.cur_channel = 1;\n\t\t\t\tRTW_INFO(\"%s: channel is auto, Channel Plan don't match just set to channel 1\\n\", __func__);\n\t\t\t}\n\t\t} else {\n\t\t\tpadapter->mlmeextpriv.cur_channel = wrqu->freq.m;\n\t\t\tRTW_INFO(\"%s: set to channel %d\\n\", __func__, padapter->mlmeextpriv.cur_channel);\n\t\t}\n\t} else {\n\t\twhile (wrqu->freq.e) {\n\t\t\texp *= 10;\n\t\t\twrqu->freq.e--;\n\t\t}\n\n\t\tfreq = wrqu->freq.m;\n\n\t\twhile (!(freq % 10)) {\n\t\t\tfreq /= 10;\n\t\t\texp *= 10;\n\t\t}\n\n\t\t/* freq unit is MHz here */\n\t\tdiv = 1000000 / exp;\n\n\t\tif (div)\n\t\t\tfreq /= div;\n\t\telse {\n\t\t\tdiv = exp / 1000000;\n\t\t\tfreq *= div;\n\t\t}\n\n\t\t/* If freq is invalid, rtw_freq2ch() will return channel 1 */\n\t\tpadapter->mlmeextpriv.cur_channel = rtw_freq2ch(freq);\n\t\tRTW_INFO(\"%s: set to channel %d\\n\", __func__, padapter->mlmeextpriv.cur_channel);\n\t}\n\tset_channel_bwmode(padapter, padapter->mlmeextpriv.cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\nexit:\n\trtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);\n\n\treturn 0;\n}\n\nstatic int rtw_wx_get_freq(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tWLAN_BSSID_EX  *pcur_bss = &pmlmepriv->cur_network.network;\n\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE && check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE) {\n\n\t\twrqu->freq.m = rtw_ch2freq(pcur_bss->Configuration.DSConfig) * 100000;\n\t\twrqu->freq.e = 1;\n\t\twrqu->freq.i = pcur_bss->Configuration.DSConfig;\n\n\t} else {\n\t\twrqu->freq.m = rtw_ch2freq(padapter->mlmeextpriv.cur_channel) * 100000;\n\t\twrqu->freq.e = 1;\n\t\twrqu->freq.i = padapter->mlmeextpriv.cur_channel;\n\t}\n\n\treturn 0;\n}\n\nstatic int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a,\n\t\t\t   union iwreq_data *wrqu, char *b)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tNDIS_802_11_NETWORK_INFRASTRUCTURE networkType ;\n\tint ret = 0;\n\n\n\tif (_FAIL == rtw_pwr_wakeup(padapter)) {\n\t\tret = -EPERM;\n\t\tgoto exit;\n\t}\n\n\tif (!rtw_is_hw_init_completed(padapter)) {\n\t\tret = -EPERM;\n\t\tgoto exit;\n\t}\n\n\t/* initial default type */\n\tdev->type = ARPHRD_ETHER;\n\n\tif (wrqu->mode == IW_MODE_MONITOR) {\n\t\trtw_ps_deny(padapter, PS_DENY_MONITOR_MODE);\n\t\tLeaveAllPowerSaveMode(padapter);\n\t} else {\n\t\trtw_ps_deny_cancel(padapter, PS_DENY_MONITOR_MODE);\n\t}\n\n\tswitch (wrqu->mode) {\n\tcase IW_MODE_MONITOR:\n\t\tnetworkType = Ndis802_11Monitor;\n#if 0\n\t\tdev->type = ARPHRD_IEEE80211; /* IEEE 802.11 : 801 */\n#endif\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))\n\t\tdev->type = ARPHRD_IEEE80211_RADIOTAP; /* IEEE 802.11 + radiotap header : 803 */\n\t\tRTW_INFO(\"set_mode = IW_MODE_MONITOR\\n\");\n#else\n\t\tRTW_INFO(\"kernel version < 2.6.24 not support IW_MODE_MONITOR\\n\");\n#endif\n\t\tbreak;\n\n\tcase IW_MODE_AUTO:\n\t\tnetworkType = Ndis802_11AutoUnknown;\n\t\tRTW_INFO(\"set_mode = IW_MODE_AUTO\\n\");\n\t\tbreak;\n\tcase IW_MODE_ADHOC:\n\t\tnetworkType = Ndis802_11IBSS;\n\t\tRTW_INFO(\"set_mode = IW_MODE_ADHOC\\n\");\n\t\tbreak;\n\tcase IW_MODE_MASTER:\n\t\tnetworkType = Ndis802_11APMode;\n\t\tRTW_INFO(\"set_mode = IW_MODE_MASTER\\n\");\n\t\tbreak;\n\tcase IW_MODE_INFRA:\n\t\tnetworkType = Ndis802_11Infrastructure;\n\t\tRTW_INFO(\"set_mode = IW_MODE_INFRA\\n\");\n\t\tbreak;\n\n\tdefault:\n\t\tret = -EINVAL;;\n\t\tgoto exit;\n\t}\n\n\tif (rtw_set_802_11_infrastructure_mode(padapter, networkType) == _FALSE) {\n\n\t\tret = -EPERM;\n\t\tgoto exit;\n\n\t}\n\n\trtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK);\n\n\tif (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE)\n\t\trtw_indicate_connect(padapter);\n\nexit:\n\n\n\treturn ret;\n\n}\n\nstatic int rtw_wx_get_mode(struct net_device *dev, struct iw_request_info *a,\n\t\t\t   union iwreq_data *wrqu, char *b)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\n\n\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)\n\t\twrqu->mode = IW_MODE_INFRA;\n\telse if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||\n\t\t (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))\n\n\t\twrqu->mode = IW_MODE_ADHOC;\n\telse if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)\n\t\twrqu->mode = IW_MODE_MASTER;\n\telse if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE)\n\t\twrqu->mode = IW_MODE_MONITOR;\n\telse\n\t\twrqu->mode = IW_MODE_AUTO;\n\n\n\treturn 0;\n\n}\n\n\nstatic int rtw_wx_set_pmkid(struct net_device *dev,\n\t\t\t    struct iw_request_info *a,\n\t\t\t    union iwreq_data *wrqu, char *extra)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8          j, blInserted = _FALSE;\n\tint         intReturn = _FALSE;\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tstruct iw_pmksa  *pPMK = (struct iw_pmksa *) extra;\n\tu8     strZeroMacAddress[ETH_ALEN] = { 0x00 };\n\tu8     strIssueBssid[ETH_ALEN] = { 0x00 };\n\n#if 0\n\tstruct iw_pmksa {\n\t\t__u32   cmd;\n\t\tstruct sockaddr bssid;\n\t\t__u8    pmkid[IW_PMKID_LEN];   /* IW_PMKID_LEN=16 */\n\t}\n\tThere are the BSSID information in the bssid.sa_data array.\n\tIf cmd is IW_PMKSA_FLUSH, it means the wpa_suppplicant wants to clear all the PMKID information.\n\tIf cmd is IW_PMKSA_ADD, it means the wpa_supplicant wants to add a PMKID / BSSID to driver.\n\tIf cmd is IW_PMKSA_REMOVE, it means the wpa_supplicant wants to remove a PMKID / BSSID from driver.\n#endif\n\n\t_rtw_memcpy(strIssueBssid, pPMK->bssid.sa_data, ETH_ALEN);\n\tif (pPMK->cmd == IW_PMKSA_ADD) {\n\t\tRTW_INFO(\"[rtw_wx_set_pmkid] IW_PMKSA_ADD!\\n\");\n\t\tif (_rtw_memcmp(strIssueBssid, strZeroMacAddress, ETH_ALEN) == _TRUE)\n\t\t\treturn intReturn ;\n\t\telse\n\t\t\tintReturn = _TRUE;\n\t\tblInserted = _FALSE;\n\n\t\t/* overwrite PMKID */\n\t\tfor (j = 0 ; j < NUM_PMKID_CACHE; j++) {\n\t\t\tif (_rtw_memcmp(psecuritypriv->PMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) == _TRUE) {\n\t\t\t\t/* BSSID is matched, the same AP => rewrite with new PMKID. */\n\n\t\t\t\tRTW_INFO(\"[rtw_wx_set_pmkid] BSSID exists in the PMKList.\\n\");\n\n\t\t\t\t_rtw_memcpy(psecuritypriv->PMKIDList[j].PMKID, pPMK->pmkid, IW_PMKID_LEN);\n\t\t\t\tpsecuritypriv->PMKIDList[j].bUsed = _TRUE;\n\t\t\t\tpsecuritypriv->PMKIDIndex = j + 1;\n\t\t\t\tblInserted = _TRUE;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tif (!blInserted) {\n\t\t\t/* Find a new entry */\n\t\t\tRTW_INFO(\"[rtw_wx_set_pmkid] Use the new entry index = %d for this PMKID.\\n\",\n\t\t\t\t psecuritypriv->PMKIDIndex);\n\n\t\t\t_rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, strIssueBssid, ETH_ALEN);\n\t\t\t_rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, pPMK->pmkid, IW_PMKID_LEN);\n\n\t\t\tpsecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].bUsed = _TRUE;\n\t\t\tpsecuritypriv->PMKIDIndex++ ;\n\t\t\tif (psecuritypriv->PMKIDIndex == 16)\n\t\t\t\tpsecuritypriv->PMKIDIndex = 0;\n\t\t}\n\t} else if (pPMK->cmd == IW_PMKSA_REMOVE) {\n\t\tRTW_INFO(\"[rtw_wx_set_pmkid] IW_PMKSA_REMOVE!\\n\");\n\t\tintReturn = _TRUE;\n\t\tfor (j = 0 ; j < NUM_PMKID_CACHE; j++) {\n\t\t\tif (_rtw_memcmp(psecuritypriv->PMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) == _TRUE) {\n\t\t\t\t/* BSSID is matched, the same AP => Remove this PMKID information and reset it. */\n\t\t\t\t_rtw_memset(psecuritypriv->PMKIDList[j].Bssid, 0x00, ETH_ALEN);\n\t\t\t\tpsecuritypriv->PMKIDList[j].bUsed = _FALSE;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t} else if (pPMK->cmd == IW_PMKSA_FLUSH) {\n\t\tRTW_INFO(\"[rtw_wx_set_pmkid] IW_PMKSA_FLUSH!\\n\");\n\t\t_rtw_memset(&psecuritypriv->PMKIDList[0], 0x00, sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);\n\t\tpsecuritypriv->PMKIDIndex = 0;\n\t\tintReturn = _TRUE;\n\t}\n\treturn intReturn ;\n}\n\nstatic int rtw_wx_get_sens(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n#ifdef CONFIG_PLATFORM_ROCKCHIPS\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\t/*\n\t*  20110311 Commented by Jeff\n\t*  For rockchip platform's wpa_driver_wext_get_rssi\n\t*/\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {\n\t\t/* wrqu->sens.value=-padapter->recvpriv.signal_strength; */\n\t\twrqu->sens.value = -padapter->recvpriv.rssi;\n\t\t/* RTW_INFO(\"%s: %d\\n\", __FUNCTION__, wrqu->sens.value); */\n\t\twrqu->sens.fixed = 0; /* no auto select */\n\t} else\n#endif\n\t{\n\t\twrqu->sens.value = 0;\n\t\twrqu->sens.fixed = 0;\t/* no auto select */\n\t\twrqu->sens.disabled = 1;\n\t}\n\treturn 0;\n}\n\nstatic int rtw_wx_get_range(struct net_device *dev,\n\t\t\t    struct iw_request_info *info,\n\t\t\t    union iwreq_data *wrqu, char *extra)\n{\n\tstruct iw_range *range = (struct iw_range *)extra;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tu16 val;\n\tint i;\n\n\n\n\twrqu->data.length = sizeof(*range);\n\t_rtw_memset(range, 0, sizeof(*range));\n\n\t/* Let's try to keep this struct in the same order as in\n\t * linux/include/wireless.h\n\t */\n\n\t/* TODO: See what values we can set, and remove the ones we can't\n\t * set, or fill them with some default data.\n\t */\n\n\t/* ~5 Mb/s real (802.11b) */\n\trange->throughput = 5 * 1000 * 1000;\n\n\t/* TODO: Not used in 802.11b?\n\t*\trange->min_nwid;\t Minimal NWID we are able to set  */\n\t/* TODO: Not used in 802.11b?\n\t*\trange->max_nwid;\t Maximal NWID we are able to set  */\n\n\t/* Old Frequency (backward compat - moved lower ) */\n\t/*\trange->old_num_channels;\n\t *\trange->old_num_frequency;\n\t * \trange->old_freq[6];  Filler to keep \"version\" at the same offset  */\n\n\t/* signal level threshold range */\n\n\t/* Quality of link & SNR stuff */\n\t/* Quality range (link, level, noise)\n\t * If the quality is absolute, it will be in the range [0 ; max_qual],\n\t * if the quality is dBm, it will be in the range [max_qual ; 0].\n\t * Don't forget that we use 8 bit arithmetics...\n\t *\n\t * If percentage range is 0~100\n\t * Signal strength dbm range logical is -100 ~ 0\n\t * but usually value is -90 ~ -20\n\t */\n\trange->max_qual.qual = 100;\n#ifdef CONFIG_SIGNAL_DISPLAY_DBM\n\trange->max_qual.level = (u8)-100;\n\trange->max_qual.noise = (u8)-100;\n\trange->max_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */\n\trange->max_qual.updated |= IW_QUAL_DBM;\n#else /* !CONFIG_SIGNAL_DISPLAY_DBM */\n\t/* percent values between 0 and 100. */\n\trange->max_qual.level = 100;\n\trange->max_qual.noise = 100;\n\trange->max_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */\n#endif /* !CONFIG_SIGNAL_DISPLAY_DBM */\n\n\t/* This should contain the average/typical values of the quality\n\t * indicator. This should be the threshold between a \"good\" and\n\t * a \"bad\" link (example : monitor going from green to orange).\n\t * Currently, user space apps like quality monitors don't have any\n\t * way to calibrate the measurement. With this, they can split\n\t * the range between 0 and max_qual in different quality level\n\t * (using a geometric subdivision centered on the average).\n\t * I expect that people doing the user space apps will feedback\n\t * us on which value we need to put in each driver... */\n\trange->avg_qual.qual = 92; /* > 8% missed beacons is 'bad' */\n#ifdef CONFIG_SIGNAL_DISPLAY_DBM\n\t/* TODO: Find real 'good' to 'bad' threshold value for RSSI */\n\trange->avg_qual.level = (u8)-70;\n\trange->avg_qual.noise = 0;\n\trange->avg_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */\n\trange->avg_qual.updated |= IW_QUAL_DBM;\n#else /* !CONFIG_SIGNAL_DISPLAY_DBM */\n\t/* TODO: Find real 'good' to 'bad' threshol value for RSSI */\n\trange->avg_qual.level = 30;\n\trange->avg_qual.noise = 100;\n\trange->avg_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */\n#endif /* !CONFIG_SIGNAL_DISPLAY_DBM */\n\n\trange->num_bitrates = RATE_COUNT;\n\n\tfor (i = 0; i < RATE_COUNT && i < IW_MAX_BITRATES; i++)\n\t\trange->bitrate[i] = rtw_rates[i];\n\n\trange->min_frag = MIN_FRAG_THRESHOLD;\n\trange->max_frag = MAX_FRAG_THRESHOLD;\n\n\trange->pm_capa = 0;\n\n\trange->we_version_compiled = WIRELESS_EXT;\n\trange->we_version_source = 16;\n\n\t/*\trange->retry_capa;\t What retry options are supported\n\t *\trange->retry_flags;\t How to decode max/min retry limit\n\t *\trange->r_time_flags;\t How to decode max/min retry life\n\t *\trange->min_retry;\t Minimal number of retries\n\t *\trange->max_retry;\t Maximal number of retries\n\t *\trange->min_r_time;\t Minimal retry lifetime\n\t *\trange->max_r_time;\t Maximal retry lifetime  */\n\n\tfor (i = 0, val = 0; i < rfctl->max_chan_nums; i++) {\n\n\t\t/* Include only legal frequencies for some countries */\n\t\tif (rfctl->channel_set[i].ChannelNum != 0) {\n\t\t\trange->freq[val].i = rfctl->channel_set[i].ChannelNum;\n\t\t\trange->freq[val].m = rtw_ch2freq(rfctl->channel_set[i].ChannelNum) * 100000;\n\t\t\trange->freq[val].e = 1;\n\t\t\tval++;\n\t\t}\n\n\t\tif (val == IW_MAX_FREQUENCIES)\n\t\t\tbreak;\n\t}\n\n\trange->num_channels = val;\n\trange->num_frequency = val;\n\n\t/* Commented by Albert 2009/10/13\n\t * The following code will proivde the security capability to network manager.\n\t * If the driver doesn't provide this capability to network manager,\n\t * the WPA/WPA2 routers can't be choosen in the network manager. */\n\n\t/*\n\t#define IW_SCAN_CAPA_NONE\t\t0x00\n\t#define IW_SCAN_CAPA_ESSID\t\t0x01\n\t#define IW_SCAN_CAPA_BSSID\t\t0x02\n\t#define IW_SCAN_CAPA_CHANNEL\t0x04\n\t#define IW_SCAN_CAPA_MODE\t\t0x08\n\t#define IW_SCAN_CAPA_RATE\t\t0x10\n\t#define IW_SCAN_CAPA_TYPE\t\t0x20\n\t#define IW_SCAN_CAPA_TIME\t\t0x40\n\t*/\n\n#if WIRELESS_EXT > 17\n\trange->enc_capa = IW_ENC_CAPA_WPA | IW_ENC_CAPA_WPA2 |\n\t\t\t  IW_ENC_CAPA_CIPHER_TKIP | IW_ENC_CAPA_CIPHER_CCMP;\n#endif\n\n#ifdef IW_SCAN_CAPA_ESSID /* WIRELESS_EXT > 21 */\n\trange->scan_capa = IW_SCAN_CAPA_ESSID | IW_SCAN_CAPA_TYPE | IW_SCAN_CAPA_BSSID |\n\t\t   IW_SCAN_CAPA_CHANNEL | IW_SCAN_CAPA_MODE | IW_SCAN_CAPA_RATE;\n#endif\n\n\n\n\treturn 0;\n\n}\n\n/* set bssid flow\n * s1. rtw_set_802_11_infrastructure_mode()\n * s2. rtw_set_802_11_authentication_mode()\n * s3. set_802_11_encryption_mode()\n * s4. rtw_set_802_11_bssid() */\nstatic int rtw_wx_set_wap(struct net_device *dev,\n\t\t\t  struct iw_request_info *info,\n\t\t\t  union iwreq_data *awrq,\n\t\t\t  char *extra)\n{\n\t_irqL\tirqL;\n\tuint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct sockaddr *temp = (struct sockaddr *)awrq;\n\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\t_list\t*phead;\n\tu8 *dst_bssid, *src_bssid;\n\t_queue\t*queue\t= &(pmlmepriv->scanned_queue);\n\tstruct\twlan_network\t*pnetwork = NULL;\n\tNDIS_802_11_AUTHENTICATION_MODE\tauthmode;\n\n\t/*\n\t#ifdef CONFIG_CONCURRENT_MODE\n\t\tif(padapter->adapter_type > PRIMARY_IFACE)\n\t\t{\n\t\t\tret = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t#endif\n\t*/\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) {\n\t\tRTW_INFO(\"set bssid, but buddy_intf is under scanning or linking\\n\");\n\n\t\tret = -EINVAL;\n\n\t\tgoto exit;\n\t}\n#endif\n\n\trtw_ps_deny(padapter, PS_DENY_JOIN);\n\tif (_FAIL == rtw_pwr_wakeup(padapter)) {\n\t\tret = -1;\n\t\tgoto cancel_ps_deny;\n\t}\n\n\tif (!padapter->bup) {\n\t\tret = -1;\n\t\tgoto cancel_ps_deny;\n\t}\n\n\n\tif (temp->sa_family != ARPHRD_ETHER) {\n\t\tret = -EINVAL;\n\t\tgoto cancel_ps_deny;\n\t}\n\n\tauthmode = padapter->securitypriv.ndisauthtype;\n\t_enter_critical_bh(&queue->lock, &irqL);\n\tphead = get_list_head(queue);\n\tpmlmepriv->pscanned = get_next(phead);\n\n\twhile (1) {\n\n\t\tif ((rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) == _TRUE) {\n#if 0\n\t\t\tret = -EINVAL;\n\t\t\tgoto cancel_ps_deny;\n\n\t\t\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {\n\t\t\t\trtw_set_802_11_bssid(padapter, temp->sa_data);\n\t\t\t\tgoto cancel_ps_deny;\n\t\t\t} else {\n\t\t\t\tret = -EINVAL;\n\t\t\t\tgoto cancel_ps_deny;\n\t\t\t}\n#endif\n\n\t\t\tbreak;\n\t\t}\n\n\t\tpnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);\n\n\t\tpmlmepriv->pscanned = get_next(pmlmepriv->pscanned);\n\n\t\tdst_bssid = pnetwork->network.MacAddress;\n\n\t\tsrc_bssid = temp->sa_data;\n\n\t\tif ((_rtw_memcmp(dst_bssid, src_bssid, ETH_ALEN)) == _TRUE) {\n\t\t\tif (!rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode)) {\n\t\t\t\tret = -1;\n\t\t\t\t_exit_critical_bh(&queue->lock, &irqL);\n\t\t\t\tgoto cancel_ps_deny;\n\t\t\t}\n\n\t\t\tbreak;\n\t\t}\n\n\t}\n\t_exit_critical_bh(&queue->lock, &irqL);\n\n\trtw_set_802_11_authentication_mode(padapter, authmode);\n\t/* set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */\n\tif (rtw_set_802_11_bssid(padapter, temp->sa_data) == _FALSE) {\n\t\tret = -1;\n\t\tgoto cancel_ps_deny;\n\t}\n\ncancel_ps_deny:\n\trtw_ps_deny_cancel(padapter, PS_DENY_JOIN);\n\n#ifdef CONFIG_CONCURRENT_MODE\nexit:\n#endif\n\treturn ret;\n}\n\nstatic int rtw_wx_get_wap(struct net_device *dev,\n\t\t\t  struct iw_request_info *info,\n\t\t\t  union iwreq_data *wrqu, char *extra)\n{\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tWLAN_BSSID_EX  *pcur_bss = &pmlmepriv->cur_network.network;\n\n\twrqu->ap_addr.sa_family = ARPHRD_ETHER;\n\n\t_rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN);\n\n\n\n\tif (((check_fwstate(pmlmepriv, _FW_LINKED)) == _TRUE) ||\n\t    ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) ||\n\t    ((check_fwstate(pmlmepriv, WIFI_AP_STATE)) == _TRUE))\n\n\t\t_rtw_memcpy(wrqu->ap_addr.sa_data, pcur_bss->MacAddress, ETH_ALEN);\n\telse\n\t\t_rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN);\n\n\n\treturn 0;\n\n}\n\nstatic int rtw_wx_set_mlme(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n#if 0\n\t/* SIOCSIWMLME data */\n\tstruct\tiw_mlme {\n\t\t__u16\t\tcmd; /* IW_MLME_* */\n\t\t__u16\t\treason_code;\n\t\tstruct sockaddr\taddr;\n\t};\n#endif\n\n\tint ret = 0;\n\tu16 reason;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct iw_mlme *mlme = (struct iw_mlme *) extra;\n\n\n\tif (mlme == NULL)\n\t\treturn -1;\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\treason = cpu_to_le16(mlme->reason_code);\n\n\n\tRTW_INFO(\"%s, cmd=%d, reason=%d\\n\", __FUNCTION__, mlme->cmd, reason);\n\n\n\tswitch (mlme->cmd) {\n\tcase IW_MLME_DEAUTH:\n\t\tif (!rtw_set_802_11_disassociate(padapter))\n\t\t\tret = -1;\n\t\tbreak;\n\n\tcase IW_MLME_DISASSOC:\n\t\tif (!rtw_set_802_11_disassociate(padapter))\n\t\t\tret = -1;\n\n\t\tbreak;\n\n\tdefault:\n\t\treturn -EOPNOTSUPP;\n\t}\n#ifdef CONFIG_RTW_REPEATER_SON\n\trtw_rson_do_disconnect(padapter);\n#endif\n\treturn ret;\n}\n\nstatic int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\tu8 _status = _FALSE;\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\t/*struct mlme_priv *pmlmepriv = &padapter->mlmepriv;*/\n\tstruct sitesurvey_parm parm;\n\tu8 ssc_chk;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n#endif /* CONFIG_P2P */\n\n#ifdef DBG_IOCTL\n\tRTW_INFO(\"DBG_IOCTL %s:%d\\n\", __FUNCTION__, __LINE__);\n#endif\n\n#if 1\n\tssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);\n\n\t#ifdef CONFIG_DOSCAN_IN_BUSYTRAFFIC\n\tif ((ssc_chk != SS_ALLOW) && (ssc_chk != SS_DENY_BUSY_TRAFFIC))\n\t#else\n\t/* When Busy Traffic, driver do not site survey. So driver return success. */\n\t/* wpa_supplicant will not issue SIOCSIWSCAN cmd again after scan timeout. */\n\t/* modify by thomas 2011-02-22. */\n\tif (ssc_chk != SS_ALLOW)\n\t#endif\n\t{\n\t\tif (ssc_chk == SS_DENY_MP_MODE)\n\t\t\tret = -EPERM;\n\t\t#ifdef DBG_LA_MODE\n\t\telse if (ssc_chk == SS_DENY_LA_MODE)\n\t\t\tret = -EPERM;\n\t\t#endif\n\t\telse\n\t\t\tindicate_wx_scan_complete_event(padapter);\n\n\t\tgoto exit;\n\t} else\n\t\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n\n\trtw_ps_deny(padapter, PS_DENY_SCAN);\n\tif (_FAIL == rtw_pwr_wakeup(padapter)) {\n\t\tret = -1;\n\t\tgoto cancel_ps_deny;\n\t}\n\tif (!rtw_is_adapter_up(padapter)) {\n\t\tret = -1;\n\t\tgoto cancel_ps_deny;\n\t}\n#else\n\n#ifdef CONFIG_MP_INCLUDED\n\tif (rtw_mp_mode_check(padapter)) {\n\t\tRTW_INFO(\"MP mode block Scan request\\n\");\n\t\tret = -EPERM;\n\t\tgoto exit;\n\t}\n#endif\n\tif (rtw_is_scan_deny(padapter)) {\n\t\tindicate_wx_scan_complete_event(padapter);\n\t\tgoto exit;\n\t}\n\n\trtw_ps_deny(padapter, PS_DENY_SCAN);\n\tif (_FAIL == rtw_pwr_wakeup(padapter)) {\n\t\tret = -1;\n\t\tgoto cancel_ps_deny;\n\t}\n\n\tif (!rtw_is_adapter_up(padapter)) {\n\t\tret = -1;\n\t\tgoto cancel_ps_deny;\n\t}\n\n#ifndef CONFIG_DOSCAN_IN_BUSYTRAFFIC\n\t/* When Busy Traffic, driver do not site survey. So driver return success. */\n\t/* wpa_supplicant will not issue SIOCSIWSCAN cmd again after scan timeout. */\n\t/* modify by thomas 2011-02-22. */\n\tif (rtw_mi_busy_traffic_check(padapter, _FALSE)) {\n\t\tindicate_wx_scan_complete_event(padapter);\n\t\tgoto cancel_ps_deny;\n\t}\n#endif\n#ifdef CONFIG_RTW_REPEATER_SON\n\tif (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" blocking scan for under rson scanning process\\n\", FUNC_ADPT_ARG(padapter));\n\t\tindicate_wx_scan_complete_event(padapter);\n\t\tgoto cancel_ps_deny;\n\t}\n#endif\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {\n\t\tRTW_INFO(\"AP mode process WPS\\n\");\n\t\tindicate_wx_scan_complete_event(padapter);\n\t\tgoto cancel_ps_deny;\n\t}\n\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) {\n\t\tindicate_wx_scan_complete_event(padapter);\n\t\tgoto cancel_ps_deny;\n\t}\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_buddy_check_fwstate(padapter,\n\t\t       _FW_UNDER_SURVEY | _FW_UNDER_LINKING | WIFI_UNDER_WPS)) {\n\n\t\tindicate_wx_scan_complete_event(padapter);\n\t\tgoto cancel_ps_deny;\n\t}\n#endif\n#endif\n\n#ifdef CONFIG_P2P\n\tif (pwdinfo->p2p_state != P2P_STATE_NONE) {\n\t\trtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));\n\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);\n\t\trtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_FULL);\n\t\trtw_free_network_queue(padapter, _TRUE);\n\t}\n#endif /* CONFIG_P2P */\n\n#if WIRELESS_EXT >= 17\n\tif (wrqu->data.length == sizeof(struct iw_scan_req)) {\n\t\tstruct iw_scan_req *req = (struct iw_scan_req *)extra;\n\n\t\tif (wrqu->data.flags & IW_SCAN_THIS_ESSID) {\n\t\t\tint len = min((int)req->essid_len, IW_ESSID_MAX_SIZE);\n\n\t\t\trtw_init_sitesurvey_parm(padapter, &parm);\n\t\t\t_rtw_memcpy(&parm.ssid[0].Ssid, &req->essid, len);\n\t\t\tparm.ssid[0].SsidLength = len;\n\t\t\tparm.ssid_num = 1;\n\n\t\t\tRTW_INFO(\"IW_SCAN_THIS_ESSID, ssid=%s, len=%d\\n\", req->essid, req->essid_len);\n\n\t\t\t_status = rtw_set_802_11_bssid_list_scan(padapter, &parm);\n\n\t\t} else if (req->scan_type == IW_SCAN_TYPE_PASSIVE)\n\t\t\tRTW_INFO(\"rtw_wx_set_scan, req->scan_type == IW_SCAN_TYPE_PASSIVE\\n\");\n\n\t} else\n#endif\n\n\t\tif (wrqu->data.length >= WEXT_CSCAN_HEADER_SIZE\n\t\t    && _rtw_memcmp(extra, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE\n\t\t   ) {\n\t\t\tint len = wrqu->data.length - WEXT_CSCAN_HEADER_SIZE;\n\t\t\tchar *pos = extra + WEXT_CSCAN_HEADER_SIZE;\n\t\t\tchar section;\n\t\t\tchar sec_len;\n\t\t\tint ssid_index = 0;\n\n\t\t\t/* RTW_INFO(\"%s COMBO_SCAN header is recognized\\n\", __FUNCTION__); */\n\t\t\trtw_init_sitesurvey_parm(padapter, &parm);\n\n\t\t\twhile (len >= 1) {\n\t\t\t\tsection = *(pos++);\n\t\t\t\tlen -= 1;\n\n\t\t\t\tswitch (section) {\n\t\t\t\tcase WEXT_CSCAN_SSID_SECTION:\n\t\t\t\t\t/* RTW_INFO(\"WEXT_CSCAN_SSID_SECTION\\n\"); */\n\t\t\t\t\tif (len < 1) {\n\t\t\t\t\t\tlen = 0;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\n\t\t\t\t\tsec_len = *(pos++);\n\t\t\t\t\tlen -= 1;\n\n\t\t\t\t\tif (sec_len > 0 && sec_len <= len) {\n\n\t\t\t\t\t\tparm.ssid[ssid_index].SsidLength = sec_len;\n\t\t\t\t\t\t_rtw_memcpy(&parm.ssid[ssid_index].Ssid, pos, sec_len);\n\n\t\t\t\t\t\t/* RTW_INFO(\"%s COMBO_SCAN with specific parm.ssid:%s, %d\\n\", __FUNCTION__ */\n\t\t\t\t\t\t/*\t, parm.ssid[ssid_index].Ssid, parm.ssid[ssid_index].SsidLength); */\n\t\t\t\t\t\tssid_index++;\n\t\t\t\t\t}\n\n\t\t\t\t\tpos += sec_len;\n\t\t\t\t\tlen -= sec_len;\n\t\t\t\t\tbreak;\n\n\n\t\t\t\tcase WEXT_CSCAN_CHANNEL_SECTION:\n\t\t\t\t\t/* RTW_INFO(\"WEXT_CSCAN_CHANNEL_SECTION\\n\"); */\n\t\t\t\t\tpos += 1;\n\t\t\t\t\tlen -= 1;\n\t\t\t\t\tbreak;\n\t\t\t\tcase WEXT_CSCAN_ACTV_DWELL_SECTION:\n\t\t\t\t\t/* RTW_INFO(\"WEXT_CSCAN_ACTV_DWELL_SECTION\\n\"); */\n\t\t\t\t\tpos += 2;\n\t\t\t\t\tlen -= 2;\n\t\t\t\t\tbreak;\n\t\t\t\tcase WEXT_CSCAN_PASV_DWELL_SECTION:\n\t\t\t\t\t/* RTW_INFO(\"WEXT_CSCAN_PASV_DWELL_SECTION\\n\"); */\n\t\t\t\t\tpos += 2;\n\t\t\t\t\tlen -= 2;\n\t\t\t\t\tbreak;\n\t\t\t\tcase WEXT_CSCAN_HOME_DWELL_SECTION:\n\t\t\t\t\t/* RTW_INFO(\"WEXT_CSCAN_HOME_DWELL_SECTION\\n\"); */\n\t\t\t\t\tpos += 2;\n\t\t\t\t\tlen -= 2;\n\t\t\t\t\tbreak;\n\t\t\t\tcase WEXT_CSCAN_TYPE_SECTION:\n\t\t\t\t\t/* RTW_INFO(\"WEXT_CSCAN_TYPE_SECTION\\n\"); */\n\t\t\t\t\tpos += 1;\n\t\t\t\t\tlen -= 1;\n\t\t\t\t\tbreak;\n#if 0\n\t\t\t\tcase WEXT_CSCAN_NPROBE_SECTION:\n\t\t\t\t\tRTW_INFO(\"WEXT_CSCAN_NPROBE_SECTION\\n\");\n\t\t\t\t\tbreak;\n#endif\n\n\t\t\t\tdefault:\n\t\t\t\t\t/* RTW_INFO(\"Unknown CSCAN section %c\\n\", section); */\n\t\t\t\t\tlen = 0; /* stop parsing */\n\t\t\t\t}\n\t\t\t\t/* RTW_INFO(\"len:%d\\n\", len); */\n\n\t\t\t}\n\t\t\tparm.ssid_num = ssid_index;\n\n\t\t\t/* jeff: it has still some scan paramater to parse, we only do this now... */\n\t\t\t_status = rtw_set_802_11_bssid_list_scan(padapter, &parm);\n\n\t\t} else\n\n\t\t\t_status = rtw_set_802_11_bssid_list_scan(padapter, NULL);\n\n\tif (_status == _FALSE)\n\t\tret = -1;\n\ncancel_ps_deny:\n\trtw_ps_deny_cancel(padapter, PS_DENY_SCAN);\n\nexit:\n#ifdef DBG_IOCTL\n\tRTW_INFO(\"DBG_IOCTL %s:%d return %d\\n\", __FUNCTION__, __LINE__, ret);\n#endif\n\n\treturn ret;\n}\n\nstatic int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\t_irqL\tirqL;\n\t_list\t\t\t\t\t*plist, *phead;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tRT_CHANNEL_INFO *chset = rfctl->channel_set;\n\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\t_queue\t\t\t\t*queue\t= &(pmlmepriv->scanned_queue);\n\tstruct\twlan_network\t*pnetwork = NULL;\n\tchar *ev = extra;\n\tchar *stop = ev + wrqu->data.length;\n\tu32 ret = 0;\n\tu32 wait_for_surveydone;\n\tsint wait_status;\n\tu8 ch;\n\n#ifdef CONFIG_P2P\n\tstruct\twifidirect_info\t*pwdinfo = &padapter->wdinfo;\n#endif /* CONFIG_P2P */\n\n\n#ifdef DBG_IOCTL\n\tRTW_INFO(\"DBG_IOCTL %s:%d\\n\", __FUNCTION__, __LINE__);\n#endif\n\n\tif (adapter_to_pwrctl(padapter)->brfoffbyhw && rtw_is_drv_stopped(padapter)) {\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\n#ifdef CONFIG_P2P\n\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))\n\t\twait_for_surveydone = 200;\n\telse {\n\t\t/*\tP2P is disabled */\n\t\twait_for_surveydone = 100;\n\t}\n#else\n\t{\n\t\twait_for_surveydone = 100;\n\t}\n#endif /* CONFIG_P2P */\n\n#if 1 /* Wireless Extension use EAGAIN to try */\n\twait_status = _FW_UNDER_SURVEY\n#ifndef CONFIG_ANDROID\n\t\t      | _FW_UNDER_LINKING\n#endif\n\t\t      ;\n\n\twhile (check_fwstate(pmlmepriv, wait_status) == _TRUE)\n\t\treturn -EAGAIN;\n#else\n\twait_status = _FW_UNDER_SURVEY\n#ifndef CONFIG_ANDROID\n\t\t      | _FW_UNDER_LINKING\n#endif\n\t\t      ;\n\n\twhile (check_fwstate(pmlmepriv, wait_status) == _TRUE) {\n\t\trtw_msleep_os(30);\n\t\tcnt++;\n\t\tif (cnt > wait_for_surveydone)\n\t\t\tbreak;\n\t}\n#endif\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\n\twhile (1) {\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tif ((stop - ev) < SCAN_ITEM_SIZE) {\n\t\t\tif(wrqu->data.length == MAX_SCAN_BUFFER_LEN){ /*max buffer len defined by iwlist*/\n\t\t\t\tret = 0;\n\t\t\t\tRTW_INFO(\"%s: Scan results incomplete\\n\", __FUNCTION__);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tret = -E2BIG;\n\t\t\tbreak;\n\t\t}\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\t\tch = pnetwork->network.Configuration.DSConfig;\n\n\t\t/* report network only if the current channel set contains the channel to which this network belongs */\n\t\tif (rtw_chset_search_ch(chset, ch) >= 0\n\t\t\t&& rtw_mlme_band_check(padapter, ch) == _TRUE\n\t\t\t&& _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))\n\t\t\t&& (!IS_DFS_SLAVE_WITH_RD(rfctl)\n\t\t\t\t|| rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))\n\t\t\t\t|| !rtw_chset_is_ch_non_ocp(chset, ch))\n\t\t)\n\t\t\tev = translate_scan(padapter, a, pnetwork, ev, stop);\n\n\t\tplist = get_next(plist);\n\n\t}\n\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\twrqu->data.length = ev - extra;\n\twrqu->data.flags = 0;\n\nexit:\n\n\n#ifdef DBG_IOCTL\n\tRTW_INFO(\"DBG_IOCTL %s:%d return %d\\n\", __FUNCTION__, __LINE__, ret);\n#endif\n\n\treturn ret ;\n\n}\n\n/* set ssid flow\n * s1. rtw_set_802_11_infrastructure_mode()\n * s2. set_802_11_authenticaion_mode()\n * s3. set_802_11_encryption_mode()\n * s4. rtw_set_802_11_ssid() */\nstatic int rtw_wx_set_essid(struct net_device *dev,\n\t\t\t    struct iw_request_info *a,\n\t\t\t    union iwreq_data *wrqu, char *extra)\n{\n\t_irqL irqL;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\t_queue *queue = &pmlmepriv->scanned_queue;\n\t_list *phead;\n\tstruct wlan_network *pnetwork = NULL;\n\tNDIS_802_11_AUTHENTICATION_MODE authmode;\n\tNDIS_802_11_SSID ndis_ssid;\n\tu8 *dst_ssid, *src_ssid;\n\n\tuint ret = 0, len;\n\n\n#ifdef DBG_IOCTL\n\tRTW_INFO(\"DBG_IOCTL %s:%d\\n\", __FUNCTION__, __LINE__);\n#endif\n#ifdef CONFIG_WEXT_DONT_JOIN_BYSSID\n\tRTW_INFO(\"%s: CONFIG_WEXT_DONT_JOIN_BYSSID be defined!! only allow bssid joining\\n\", __func__);\n\treturn -EPERM;\n#endif\n\n#if WIRELESS_EXT <= 20\n\tif ((wrqu->essid.length - 1) > IW_ESSID_MAX_SIZE) {\n#else\n\tif (wrqu->essid.length > IW_ESSID_MAX_SIZE) {\n#endif\n\t\tret = -E2BIG;\n\t\tgoto exit;\n\t}\n\n\n\n\trtw_ps_deny(padapter, PS_DENY_JOIN);\n\tif (_FAIL == rtw_pwr_wakeup(padapter)) {\n\t\tret = -1;\n\t\tgoto cancel_ps_deny;\n\t}\n\n\tif (!padapter->bup) {\n\t\tret = -1;\n\t\tgoto cancel_ps_deny;\n\t}\n\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {\n\t\tret = -1;\n\t\tgoto cancel_ps_deny;\n\t}\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_SURVEY | _FW_UNDER_LINKING)) {\n\t\tRTW_INFO(\"set ssid, but buddy_intf is under scanning or linking\\n\");\n\t\tret = -EINVAL;\n\t\tgoto cancel_ps_deny;\n\t}\n#endif\n\tauthmode = padapter->securitypriv.ndisauthtype;\n\tRTW_INFO(\"=>%s\\n\", __FUNCTION__);\n\tif (wrqu->essid.flags && wrqu->essid.length) {\n\t\t/* Commented by Albert 20100519 */\n\t\t/* We got the codes in \"set_info\" function of iwconfig source code. */\n\t\t/*\t========================================= */\n\t\t/*\twrq.u.essid.length = strlen(essid) + 1; */\n\t\t/*\tif(we_kernel_version > 20) */\n\t\t/*\t\twrq.u.essid.length--; */\n\t\t/*\t========================================= */\n\t\t/*\tThat means, if the WIRELESS_EXT less than or equal to 20, the correct ssid len should subtract 1. */\n#if WIRELESS_EXT <= 20\n\t\tlen = ((wrqu->essid.length - 1) < IW_ESSID_MAX_SIZE) ? (wrqu->essid.length - 1) : IW_ESSID_MAX_SIZE;\n#else\n\t\tlen = (wrqu->essid.length < IW_ESSID_MAX_SIZE) ? wrqu->essid.length : IW_ESSID_MAX_SIZE;\n#endif\n\n\t\tif (wrqu->essid.length != 33)\n\t\t\tRTW_INFO(\"ssid=%s, len=%d\\n\", extra, wrqu->essid.length);\n\n\t\t_rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID));\n\t\tndis_ssid.SsidLength = len;\n\t\t_rtw_memcpy(ndis_ssid.Ssid, extra, len);\n\t\tsrc_ssid = ndis_ssid.Ssid;\n\n\t\t_enter_critical_bh(&queue->lock, &irqL);\n\t\tphead = get_list_head(queue);\n\t\tpmlmepriv->pscanned = get_next(phead);\n\n\t\twhile (1) {\n\t\t\tif (rtw_end_of_queue_search(phead, pmlmepriv->pscanned) == _TRUE) {\n#if 0\n\t\t\t\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {\n\t\t\t\t\trtw_set_802_11_ssid(padapter, &ndis_ssid);\n\n\t\t\t\t\tgoto cancel_ps_deny;\n\t\t\t\t} else {\n\t\t\t\t\tret = -EINVAL;\n\t\t\t\t\tgoto cancel_ps_deny;\n\t\t\t\t}\n#endif\n\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tpnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);\n\n\t\t\tpmlmepriv->pscanned = get_next(pmlmepriv->pscanned);\n\n\t\t\tdst_ssid = pnetwork->network.Ssid.Ssid;\n\n\n\t\t\tif ((_rtw_memcmp(dst_ssid, src_ssid, ndis_ssid.SsidLength) == _TRUE) &&\n\t\t\t    (pnetwork->network.Ssid.SsidLength == ndis_ssid.SsidLength)) {\n\n\t\t\t\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {\n\t\t\t\t\tif (pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\tif (rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode) == _FALSE) {\n\t\t\t\t\tret = -1;\n\t\t\t\t\t_exit_critical_bh(&queue->lock, &irqL);\n\t\t\t\t\tgoto cancel_ps_deny;\n\t\t\t\t}\n\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t_exit_critical_bh(&queue->lock, &irqL);\n\t\trtw_set_802_11_authentication_mode(padapter, authmode);\n\t\t/* set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */\n\t\tif (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) {\n\t\t\tret = -1;\n\t\t\tgoto cancel_ps_deny;\n\t\t}\n\t}\n\ncancel_ps_deny:\n\trtw_ps_deny_cancel(padapter, PS_DENY_JOIN);\n\nexit:\n\tRTW_INFO(\"<=%s, ret %d\\n\", __FUNCTION__, ret);\n\n#ifdef DBG_IOCTL\n\tRTW_INFO(\"DBG_IOCTL %s:%d return %d\\n\", __FUNCTION__, __LINE__, ret);\n#endif\n\n\n\treturn ret;\n}\n\nstatic int rtw_wx_get_essid(struct net_device *dev,\n\t\t\t    struct iw_request_info *a,\n\t\t\t    union iwreq_data *wrqu, char *extra)\n{\n\tu32 len, ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tWLAN_BSSID_EX  *pcur_bss = &pmlmepriv->cur_network.network;\n\n\n\n\tif ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ||\n\t    (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {\n\t\tlen = pcur_bss->Ssid.SsidLength;\n\n\t\twrqu->essid.length = len;\n\n\t\t_rtw_memcpy(extra, pcur_bss->Ssid.Ssid, len);\n\n\t\twrqu->essid.flags = 1;\n\t} else {\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\nexit:\n\n\n\treturn ret;\n\n}\n\nstatic int rtw_wx_set_rate(struct net_device *dev,\n\t\t\t   struct iw_request_info *a,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\tint\ti, ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8\tdatarates[NumRates];\n\tu32\ttarget_rate = wrqu->bitrate.value;\n\tu32\tfixed = wrqu->bitrate.fixed;\n\tu32\tratevalue = 0;\n\tu8 mpdatarate[NumRates] = {11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0xff};\n\n\n\n\tif (target_rate == -1) {\n\t\tratevalue = 11;\n\t\tgoto set_rate;\n\t}\n\ttarget_rate = target_rate / 100000;\n\n\tswitch (target_rate) {\n\tcase 10:\n\t\tratevalue = 0;\n\t\tbreak;\n\tcase 20:\n\t\tratevalue = 1;\n\t\tbreak;\n\tcase 55:\n\t\tratevalue = 2;\n\t\tbreak;\n\tcase 60:\n\t\tratevalue = 3;\n\t\tbreak;\n\tcase 90:\n\t\tratevalue = 4;\n\t\tbreak;\n\tcase 110:\n\t\tratevalue = 5;\n\t\tbreak;\n\tcase 120:\n\t\tratevalue = 6;\n\t\tbreak;\n\tcase 180:\n\t\tratevalue = 7;\n\t\tbreak;\n\tcase 240:\n\t\tratevalue = 8;\n\t\tbreak;\n\tcase 360:\n\t\tratevalue = 9;\n\t\tbreak;\n\tcase 480:\n\t\tratevalue = 10;\n\t\tbreak;\n\tcase 540:\n\t\tratevalue = 11;\n\t\tbreak;\n\tdefault:\n\t\tratevalue = 11;\n\t\tbreak;\n\t}\n\nset_rate:\n\n\tfor (i = 0; i < NumRates; i++) {\n\t\tif (ratevalue == mpdatarate[i]) {\n\t\t\tdatarates[i] = mpdatarate[i];\n\t\t\tif (fixed == 0)\n\t\t\t\tbreak;\n\t\t} else\n\t\t\tdatarates[i] = 0xff;\n\n\t}\n\n\tif (rtw_setdatarate_cmd(padapter, datarates) != _SUCCESS) {\n\t\tret = -1;\n\t}\n\n\n\treturn ret;\n}\n\nstatic int rtw_wx_get_rate(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\tu16 max_rate = 0;\n\n\tmax_rate = rtw_get_cur_max_rate((_adapter *)rtw_netdev_priv(dev));\n\n\tif (max_rate == 0)\n\t\treturn -EPERM;\n\n\twrqu->bitrate.fixed = 0;\t/* no auto select */\n\twrqu->bitrate.value = max_rate * 100000;\n\n\treturn 0;\n}\n\nstatic int rtw_wx_set_rts(struct net_device *dev,\n\t\t\t  struct iw_request_info *info,\n\t\t\t  union iwreq_data *wrqu, char *extra)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\n\tif (wrqu->rts.disabled)\n\t\tpadapter->registrypriv.rts_thresh = 2347;\n\telse {\n\t\tif (wrqu->rts.value < 0 ||\n\t\t    wrqu->rts.value > 2347)\n\t\t\treturn -EINVAL;\n\n\t\tpadapter->registrypriv.rts_thresh = wrqu->rts.value;\n\t}\n\n\tRTW_INFO(\"%s, rts_thresh=%d\\n\", __func__, padapter->registrypriv.rts_thresh);\n\n\n\treturn 0;\n\n}\n\nstatic int rtw_wx_get_rts(struct net_device *dev,\n\t\t\t  struct iw_request_info *info,\n\t\t\t  union iwreq_data *wrqu, char *extra)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\n\tRTW_INFO(\"%s, rts_thresh=%d\\n\", __func__, padapter->registrypriv.rts_thresh);\n\n\twrqu->rts.value = padapter->registrypriv.rts_thresh;\n\twrqu->rts.fixed = 0;\t/* no auto select */\n\t/* wrqu->rts.disabled = (wrqu->rts.value == DEFAULT_RTS_THRESHOLD); */\n\n\n\treturn 0;\n}\n\nstatic int rtw_wx_set_frag(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\n\tif (wrqu->frag.disabled)\n\t\tpadapter->xmitpriv.frag_len = MAX_FRAG_THRESHOLD;\n\telse {\n\t\tif (wrqu->frag.value < MIN_FRAG_THRESHOLD ||\n\t\t    wrqu->frag.value > MAX_FRAG_THRESHOLD)\n\t\t\treturn -EINVAL;\n\n\t\tpadapter->xmitpriv.frag_len = wrqu->frag.value & ~0x1;\n\t}\n\n\tRTW_INFO(\"%s, frag_len=%d\\n\", __func__, padapter->xmitpriv.frag_len);\n\n\n\treturn 0;\n\n}\n\nstatic int rtw_wx_get_frag(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\n\tRTW_INFO(\"%s, frag_len=%d\\n\", __func__, padapter->xmitpriv.frag_len);\n\n\twrqu->frag.value = padapter->xmitpriv.frag_len;\n\twrqu->frag.fixed = 0;\t/* no auto select */\n\t/* wrqu->frag.disabled = (wrqu->frag.value == DEFAULT_FRAG_THRESHOLD); */\n\n\n\treturn 0;\n}\n\nstatic int rtw_wx_get_retry(struct net_device *dev,\n\t\t\t    struct iw_request_info *info,\n\t\t\t    union iwreq_data *wrqu, char *extra)\n{\n\t/* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */\n\n\n\twrqu->retry.value = 7;\n\twrqu->retry.fixed = 0;\t/* no auto select */\n\twrqu->retry.disabled = 1;\n\n\treturn 0;\n\n}\n\n#if 0\n\t#define IW_ENCODE_INDEX\t\t0x00FF\t/* Token index (if needed) */\n\t#define IW_ENCODE_FLAGS\t\t0xFF00\t/* Flags defined below */\n\t#define IW_ENCODE_MODE\t\t0xF000\t/* Modes defined below */\n\t#define IW_ENCODE_DISABLED\t0x8000\t/* Encoding disabled */\n\t#define IW_ENCODE_ENABLED\t0x0000\t/* Encoding enabled */\n\t#define IW_ENCODE_RESTRICTED\t0x4000\t/* Refuse non-encoded packets */\n\t#define IW_ENCODE_OPEN\t\t0x2000\t/* Accept non-encoded packets */\n\t#define IW_ENCODE_NOKEY\t\t0x0800  /* Key is write only, so not present */\n\t#define IW_ENCODE_TEMP\t\t0x0400  /* Temporary key */\n\t/*\n\tiwconfig wlan0 key on->flags = 0x6001->maybe it means auto\n\tiwconfig wlan0 key off->flags = 0x8800\n\tiwconfig wlan0 key open->flags = 0x2800\n\tiwconfig wlan0 key open 1234567890->flags = 0x2000\n\tiwconfig wlan0 key restricted->flags = 0x4800\n\tiwconfig wlan0 key open [3] 1234567890->flags = 0x2003\n\tiwconfig wlan0 key restricted [2] 1234567890->flags = 0x4002\n\tiwconfig wlan0 key open [3] -> flags = 0x2803\n\tiwconfig wlan0 key restricted [2] -> flags = 0x4802\n\t*/\n#endif\n\nstatic int rtw_wx_set_enc(struct net_device *dev,\n\t\t\t  struct iw_request_info *info,\n\t\t\t  union iwreq_data *wrqu, char *keybuf)\n{\n\tu32 key, ret = 0;\n\tu32 keyindex_provided;\n\tNDIS_802_11_WEP\t wep;\n\tNDIS_802_11_AUTHENTICATION_MODE authmode;\n\n\tstruct iw_point *erq = &(wrqu->encoding);\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tRTW_INFO(\"+rtw_wx_set_enc, flags=0x%x\\n\", erq->flags);\n\n\t_rtw_memset(&wep, 0, sizeof(NDIS_802_11_WEP));\n\n\tkey = erq->flags & IW_ENCODE_INDEX;\n\n\n\tif (erq->flags & IW_ENCODE_DISABLED) {\n\t\tRTW_INFO(\"EncryptionDisabled\\n\");\n\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;\n\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;\n\t\tpadapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;\n\t\tpadapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */\n\t\tauthmode = Ndis802_11AuthModeOpen;\n\t\tpadapter->securitypriv.ndisauthtype = authmode;\n\n\t\tgoto exit;\n\t}\n\n\tif (key) {\n\t\tif (key > WEP_KEYS)\n\t\t\treturn -EINVAL;\n\t\tkey--;\n\t\tkeyindex_provided = 1;\n\t} else {\n\t\tkeyindex_provided = 0;\n\t\tkey = padapter->securitypriv.dot11PrivacyKeyIndex;\n\t\tRTW_INFO(\"rtw_wx_set_enc, key=%d\\n\", key);\n\t}\n\n\t/* set authentication mode\t */\n\tif (erq->flags & IW_ENCODE_OPEN) {\n\t\tRTW_INFO(\"rtw_wx_set_enc():IW_ENCODE_OPEN\\n\");\n\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;/* Ndis802_11EncryptionDisabled; */\n\n#ifdef CONFIG_PLATFORM_MT53XX\n\t\tpadapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;\n#else\n\t\tpadapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open;\n#endif\n\n\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;\n\t\tpadapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;\n\t\tauthmode = Ndis802_11AuthModeOpen;\n\t\tpadapter->securitypriv.ndisauthtype = authmode;\n\t} else if (erq->flags & IW_ENCODE_RESTRICTED) {\n\t\tRTW_INFO(\"rtw_wx_set_enc():IW_ENCODE_RESTRICTED\\n\");\n\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;\n\n#ifdef CONFIG_PLATFORM_MT53XX\n\t\tpadapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;\n#else\n\t\tpadapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Shared;\n#endif\n\n\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_;\n\t\tpadapter->securitypriv.dot118021XGrpPrivacy = _WEP40_;\n\t\tauthmode = Ndis802_11AuthModeShared;\n\t\tpadapter->securitypriv.ndisauthtype = authmode;\n\t} else {\n\t\tRTW_INFO(\"rtw_wx_set_enc():erq->flags=0x%x\\n\", erq->flags);\n\n\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;/* Ndis802_11EncryptionDisabled; */\n\t\tpadapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */\n\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;\n\t\tpadapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;\n\t\tauthmode = Ndis802_11AuthModeOpen;\n\t\tpadapter->securitypriv.ndisauthtype = authmode;\n\t}\n\n\twep.KeyIndex = key;\n\tif (erq->length > 0) {\n\t\twep.KeyLength = erq->length <= 5 ? 5 : 13;\n\n\t\twep.Length = wep.KeyLength + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial);\n\t} else {\n\t\twep.KeyLength = 0 ;\n\n\t\tif (keyindex_provided == 1) { /* set key_id only, no given KeyMaterial(erq->length==0). */\n\t\t\tpadapter->securitypriv.dot11PrivacyKeyIndex = key;\n\n\t\t\tRTW_INFO(\"(keyindex_provided == 1), keyid=%d, key_len=%d\\n\", key, padapter->securitypriv.dot11DefKeylen[key]);\n\n\t\t\tswitch (padapter->securitypriv.dot11DefKeylen[key]) {\n\t\t\tcase 5:\n\t\t\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_;\n\t\t\t\tbreak;\n\t\t\tcase 13:\n\t\t\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tgoto exit;\n\n\t\t}\n\n\t}\n\n\twep.KeyIndex |= 0x80000000;\n\n\t_rtw_memcpy(wep.KeyMaterial, keybuf, wep.KeyLength);\n\n\tif (rtw_set_802_11_add_wep(padapter, &wep) == _FALSE) {\n\t\tif (rf_on == pwrpriv->rf_pwrstate)\n\t\t\tret = -EOPNOTSUPP;\n\t\tgoto exit;\n\t}\n\nexit:\n\n\n\treturn ret;\n\n}\n\nstatic int rtw_wx_get_enc(struct net_device *dev,\n\t\t\t  struct iw_request_info *info,\n\t\t\t  union iwreq_data *wrqu, char *keybuf)\n{\n\tuint key, ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct iw_point *erq = &(wrqu->encoding);\n\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\n\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) {\n\t\tif (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE) {\n\t\t\terq->length = 0;\n\t\t\terq->flags |= IW_ENCODE_DISABLED;\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\n\tkey = erq->flags & IW_ENCODE_INDEX;\n\n\tif (key) {\n\t\tif (key > WEP_KEYS)\n\t\t\treturn -EINVAL;\n\t\tkey--;\n\t} else\n\t\tkey = padapter->securitypriv.dot11PrivacyKeyIndex;\n\n\terq->flags = key + 1;\n\n\t/* if(padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen) */\n\t/* { */\n\t/* erq->flags |= IW_ENCODE_OPEN; */\n\t/* }\t  */\n\n\tswitch (padapter->securitypriv.ndisencryptstatus) {\n\tcase Ndis802_11EncryptionNotSupported:\n\tcase Ndis802_11EncryptionDisabled:\n\n\t\terq->length = 0;\n\t\terq->flags |= IW_ENCODE_DISABLED;\n\n\t\tbreak;\n\n\tcase Ndis802_11Encryption1Enabled:\n\n\t\terq->length = padapter->securitypriv.dot11DefKeylen[key];\n\n\t\tif (erq->length) {\n\t\t\t_rtw_memcpy(keybuf, padapter->securitypriv.dot11DefKey[key].skey, padapter->securitypriv.dot11DefKeylen[key]);\n\n\t\t\terq->flags |= IW_ENCODE_ENABLED;\n\n\t\t\tif (padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen)\n\t\t\t\terq->flags |= IW_ENCODE_OPEN;\n\t\t\telse if (padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeShared)\n\t\t\t\terq->flags |= IW_ENCODE_RESTRICTED;\n\t\t} else {\n\t\t\terq->length = 0;\n\t\t\terq->flags |= IW_ENCODE_DISABLED;\n\t\t}\n\n\t\tbreak;\n\n\tcase Ndis802_11Encryption2Enabled:\n\tcase Ndis802_11Encryption3Enabled:\n\n\t\terq->length = 16;\n\t\terq->flags |= (IW_ENCODE_ENABLED | IW_ENCODE_OPEN | IW_ENCODE_NOKEY);\n\n\t\tbreak;\n\n\tdefault:\n\t\terq->length = 0;\n\t\terq->flags |= IW_ENCODE_DISABLED;\n\n\t\tbreak;\n\n\t}\n\n\n\treturn ret;\n\n}\n\nstatic int rtw_wx_get_power(struct net_device *dev,\n\t\t\t    struct iw_request_info *info,\n\t\t\t    union iwreq_data *wrqu, char *extra)\n{\n\t/* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */\n\n\twrqu->power.value = 0;\n\twrqu->power.fixed = 0;\t/* no auto select */\n\twrqu->power.disabled = 1;\n\n\treturn 0;\n\n}\n\nstatic int rtw_wx_set_gen_ie(struct net_device *dev,\n\t\t\t     struct iw_request_info *info,\n\t\t\t     union iwreq_data *wrqu, char *extra)\n{\n\tint ret;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tret = rtw_set_wpa_ie(padapter, extra, wrqu->data.length);\n\n\treturn ret;\n}\n\nstatic int rtw_wx_set_auth(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct iw_param *param = (struct iw_param *)&(wrqu->param);\n#ifdef CONFIG_WAPI_SUPPORT\n#ifndef CONFIG_IOCTL_CFG80211\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tu32 value = param->value;\n#endif\n#endif\n\tint ret = 0;\n\n\tswitch (param->flags & IW_AUTH_INDEX) {\n\n\tcase IW_AUTH_WPA_VERSION:\n#ifdef CONFIG_WAPI_SUPPORT\n#ifndef CONFIG_IOCTL_CFG80211\n\t\tpadapter->wapiInfo.bWapiEnable = false;\n\t\tif (value == IW_AUTH_WAPI_VERSION_1) {\n\t\t\tpadapter->wapiInfo.bWapiEnable = true;\n\t\t\tpsecuritypriv->dot11PrivacyAlgrthm = _SMS4_;\n\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _SMS4_;\n\t\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;\n\t\t\tpmlmeinfo->auth_algo = psecuritypriv->dot11AuthAlgrthm;\n\t\t\tpadapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN;\n\t\t\tpadapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN;\n\t\t}\n#endif\n#endif\n\t\tbreak;\n\tcase IW_AUTH_CIPHER_PAIRWISE:\n\n\t\tbreak;\n\tcase IW_AUTH_CIPHER_GROUP:\n\n\t\tbreak;\n\tcase IW_AUTH_KEY_MGMT:\n#ifdef CONFIG_WAPI_SUPPORT\n#ifndef CONFIG_IOCTL_CFG80211\n\t\tRTW_INFO(\"rtw_wx_set_auth: IW_AUTH_KEY_MGMT case\\n\");\n\t\tif (value == IW_AUTH_KEY_MGMT_WAPI_PSK)\n\t\t\tpadapter->wapiInfo.bWapiPSK = true;\n\t\telse\n\t\t\tpadapter->wapiInfo.bWapiPSK = false;\n\t\tRTW_INFO(\"rtw_wx_set_auth: IW_AUTH_KEY_MGMT bwapipsk %d\\n\", padapter->wapiInfo.bWapiPSK);\n#endif\n#endif\n\t\t/*\n\t\t *  ??? does not use these parameters\n\t\t */\n\t\tbreak;\n\n\tcase IW_AUTH_TKIP_COUNTERMEASURES: {\n\t\tif (param->value) {\n\t\t\t/* wpa_supplicant is enabling the tkip countermeasure. */\n\t\t\tpadapter->securitypriv.btkip_countermeasure = _TRUE;\n\t\t} else {\n\t\t\t/* wpa_supplicant is disabling the tkip countermeasure. */\n\t\t\tpadapter->securitypriv.btkip_countermeasure = _FALSE;\n\t\t}\n\t\tbreak;\n\t}\n\tcase IW_AUTH_DROP_UNENCRYPTED: {\n\t\t/* HACK:\n\t\t *\n\t\t * wpa_supplicant calls set_wpa_enabled when the driver\n\t\t * is loaded and unloaded, regardless of if WPA is being\n\t\t * used.  No other calls are made which can be used to\n\t\t * determine if encryption will be used or not prior to\n\t\t * association being expected.  If encryption is not being\n\t\t * used, drop_unencrypted is set to false, else true -- we\n\t\t * can use this to determine if the CAP_PRIVACY_ON bit should\n\t\t * be set.\n\t\t */\n\n\t\tif (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption1Enabled) {\n\t\t\tbreak;/* it means init value, or using wep, ndisencryptstatus = Ndis802_11Encryption1Enabled, */\n\t\t\t/* then it needn't reset it; */\n\t\t}\n\n\t\tif (param->value) {\n\t\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;\n\t\t\tpadapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;\n\t\t\tpadapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;\n\t\t\tpadapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */\n\t\t\tpadapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;\n\t\t}\n\n\t\tbreak;\n\t}\n\n\tcase IW_AUTH_80211_AUTH_ALG:\n\n#if defined(CONFIG_ANDROID) || 1\n\t\t/*\n\t\t *  It's the starting point of a link layer connection using wpa_supplicant\n\t\t*/\n\t\tif (check_fwstate(&padapter->mlmepriv, _FW_LINKED)) {\n\t\t\tLeaveAllPowerSaveMode(padapter);\n\t\t\trtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK);\n\t\t\tRTW_INFO(\"%s...call rtw_indicate_disconnect\\n \", __FUNCTION__);\n\t\t\trtw_indicate_disconnect(padapter, 0, _FALSE);\n\t\t\trtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK);\n\t\t}\n#endif\n\n\n\t\tret = wpa_set_auth_algs(dev, (u32)param->value);\n\n\t\tbreak;\n\n\tcase IW_AUTH_WPA_ENABLED:\n\n\t\t/* if(param->value) */\n\t\t/* padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; */ /* 802.1x */\n\t\t/* else */\n\t\t/* padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; */ /* open system */\n\n\t\t/* _disassociate(priv); */\n\n\t\tbreak;\n\n\tcase IW_AUTH_RX_UNENCRYPTED_EAPOL:\n\t\t/* ieee->ieee802_1x = param->value; */\n\t\tbreak;\n\n\tcase IW_AUTH_PRIVACY_INVOKED:\n\t\t/* ieee->privacy_invoked = param->value; */\n\t\tbreak;\n\n#ifdef CONFIG_WAPI_SUPPORT\n#ifndef CONFIG_IOCTL_CFG80211\n\tcase IW_AUTH_WAPI_ENABLED:\n\t\tbreak;\n#endif\n#endif\n\n\tdefault:\n\t\treturn -EOPNOTSUPP;\n\n\t}\n\n\treturn ret;\n\n}\n\nstatic int rtw_wx_set_enc_ext(struct net_device *dev,\n\t\t\t      struct iw_request_info *info,\n\t\t\t      union iwreq_data *wrqu, char *extra)\n{\n\tchar *alg_name;\n\tu32 param_len;\n\tstruct ieee_param *param = NULL;\n\tstruct iw_point *pencoding = &wrqu->encoding;\n\tstruct iw_encode_ext *pext = (struct iw_encode_ext *)extra;\n\tint ret = 0;\n\n\tparam_len = sizeof(struct ieee_param) + pext->key_len;\n\tparam = (struct ieee_param *)rtw_malloc(param_len);\n\tif (param == NULL)\n\t\treturn -1;\n\n\t_rtw_memset(param, 0, param_len);\n\n\tparam->cmd = IEEE_CMD_SET_ENCRYPTION;\n\t_rtw_memset(param->sta_addr, 0xff, ETH_ALEN);\n\n\n\tswitch (pext->alg) {\n\tcase IW_ENCODE_ALG_NONE:\n\t\t/* todo: remove key */\n\t\t/* remove = 1;\t */\n\t\talg_name = \"none\";\n\t\tbreak;\n\tcase IW_ENCODE_ALG_WEP:\n\t\talg_name = \"WEP\";\n\t\tbreak;\n\tcase IW_ENCODE_ALG_TKIP:\n\t\talg_name = \"TKIP\";\n\t\tbreak;\n\tcase IW_ENCODE_ALG_CCMP:\n\t\talg_name = \"CCMP\";\n\t\tbreak;\n#ifdef CONFIG_IEEE80211W\n\tcase IW_ENCODE_ALG_AES_CMAC:\n\t\talg_name = \"BIP\";\n\t\tbreak;\n#endif /* CONFIG_IEEE80211W */\n#ifdef CONFIG_WAPI_SUPPORT\n#ifndef CONFIG_IOCTL_CFG80211\n\tcase IW_ENCODE_ALG_SM4:\n\t\talg_name = \"SMS4\";\n\t\t_rtw_memcpy(param->sta_addr, pext->addr.sa_data, ETH_ALEN);\n\t\tRTW_INFO(\"rtw_wx_set_enc_ext: SMS4 case\\n\");\n\t\tbreak;\n#endif\n#endif\n\tdefault:\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\n\tstrncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN);\n\n\tif (pext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY)\n\t\tparam->u.crypt.set_tx = 1;\n\n\t/* cliW: WEP does not have group key\n\t * just not checking GROUP key setting\n\t */\n\tif ((pext->alg != IW_ENCODE_ALG_WEP) &&\n\t    ((pext->ext_flags & IW_ENCODE_EXT_GROUP_KEY)\n#ifdef CONFIG_IEEE80211W\n\t     || (pext->ext_flags & IW_ENCODE_ALG_AES_CMAC)\n#endif /* CONFIG_IEEE80211W */\n\t    ))\n\t\tparam->u.crypt.set_tx = 0;\n\n\tparam->u.crypt.idx = (pencoding->flags & 0x00FF) - 1 ;\n\n\tif (pext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) {\n#ifdef CONFIG_WAPI_SUPPORT\n#ifndef CONFIG_IOCTL_CFG80211\n\t\tif (pext->alg == IW_ENCODE_ALG_SM4)\n\t\t\t_rtw_memcpy(param->u.crypt.seq, pext->rx_seq, 16);\n\t\telse\n#endif /* CONFIG_IOCTL_CFG80211 */\n#endif /* CONFIG_WAPI_SUPPORT */\n\t\t\t_rtw_memcpy(param->u.crypt.seq, pext->rx_seq, 8);\n\t}\n\n\tif (pext->key_len) {\n\t\tparam->u.crypt.key_len = pext->key_len;\n\t\t/* _rtw_memcpy(param + 1, pext + 1, pext->key_len); */\n\t\t_rtw_memcpy(param->u.crypt.key, pext + 1, pext->key_len);\n\t}\n\n\tif (pencoding->flags & IW_ENCODE_DISABLED) {\n\t\t/* todo: remove key */\n\t\t/* remove = 1; */\n\t}\n\n\tret =  wpa_set_encryption(dev, param, param_len);\n\nexit:\n\tif (param)\n\t\trtw_mfree((u8 *)param, param_len);\n\n\treturn ret;\n}\n\n\nstatic int rtw_wx_get_nick(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\t/* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */\n\t/* struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); */\n\t/* struct security_priv *psecuritypriv = &padapter->securitypriv; */\n\n\tif (extra) {\n\t\twrqu->data.length = 14;\n\t\twrqu->data.flags = 1;\n\t\t_rtw_memcpy(extra, \"<WIFI@REALTEK>\", 14);\n\t}\n\n\t/* rtw_signal_process(pid, SIGUSR1); */ /* for test */\n\n\t/* dump debug info here\t */\n#if 0\n\tu32 dot11AuthAlgrthm;\t\t/*  802.11 auth, could be open, shared, and 8021x */\n\tu32 dot11PrivacyAlgrthm;\t/*  This specify the privacy for shared auth. algorithm. */\n\tu32 dot118021XGrpPrivacy;\t/*  This specify the privacy algthm. used for Grp key */\n\tu32 ndisauthtype;\n\tu32 ndisencryptstatus;\n#endif\n\n\t/* RTW_INFO(\"auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\\n\",  */\n\t/*\t\tpsecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, */\n\t/*\t\tpsecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); */\n\n\t/* RTW_INFO(\"enc_alg=0x%x\\n\", psecuritypriv->dot11PrivacyAlgrthm); */\n\t/* RTW_INFO(\"auth_type=0x%x\\n\", psecuritypriv->ndisauthtype); */\n\t/* RTW_INFO(\"enc_type=0x%x\\n\", psecuritypriv->ndisencryptstatus); */\n\n#if 0\n\tRTW_INFO(\"dbg(0x210)=0x%x\\n\", rtw_read32(padapter, 0x210));\n\tRTW_INFO(\"dbg(0x608)=0x%x\\n\", rtw_read32(padapter, 0x608));\n\tRTW_INFO(\"dbg(0x280)=0x%x\\n\", rtw_read32(padapter, 0x280));\n\tRTW_INFO(\"dbg(0x284)=0x%x\\n\", rtw_read32(padapter, 0x284));\n\tRTW_INFO(\"dbg(0x288)=0x%x\\n\", rtw_read32(padapter, 0x288));\n\n\tRTW_INFO(\"dbg(0x664)=0x%x\\n\", rtw_read32(padapter, 0x664));\n\n\n\tRTW_INFO(\"\\n\");\n\n\tRTW_INFO(\"dbg(0x430)=0x%x\\n\", rtw_read32(padapter, 0x430));\n\tRTW_INFO(\"dbg(0x438)=0x%x\\n\", rtw_read32(padapter, 0x438));\n\n\tRTW_INFO(\"dbg(0x440)=0x%x\\n\", rtw_read32(padapter, 0x440));\n\n\tRTW_INFO(\"dbg(0x458)=0x%x\\n\", rtw_read32(padapter, 0x458));\n\n\tRTW_INFO(\"dbg(0x484)=0x%x\\n\", rtw_read32(padapter, 0x484));\n\tRTW_INFO(\"dbg(0x488)=0x%x\\n\", rtw_read32(padapter, 0x488));\n\n\tRTW_INFO(\"dbg(0x444)=0x%x\\n\", rtw_read32(padapter, 0x444));\n\tRTW_INFO(\"dbg(0x448)=0x%x\\n\", rtw_read32(padapter, 0x448));\n\tRTW_INFO(\"dbg(0x44c)=0x%x\\n\", rtw_read32(padapter, 0x44c));\n\tRTW_INFO(\"dbg(0x450)=0x%x\\n\", rtw_read32(padapter, 0x450));\n#endif\n\n\treturn 0;\n\n}\n\nstatic int rtw_wx_read32(struct net_device *dev,\n\t\t\t struct iw_request_info *info,\n\t\t\t union iwreq_data *wrqu, char *extra)\n{\n\tPADAPTER padapter;\n\tstruct iw_point *p;\n\tu16 len;\n\tu32 addr;\n\tu32 data32;\n\tu32 bytes;\n\tu8 *ptmp;\n\tint ret;\n\n\n\tret = 0;\n\tpadapter = (PADAPTER)rtw_netdev_priv(dev);\n\tp = &wrqu->data;\n\tlen = p->length;\n\tif (0 == len)\n\t\treturn -EINVAL;\n\n\tptmp = (u8 *)rtw_malloc(len);\n\tif (NULL == ptmp)\n\t\treturn -ENOMEM;\n\n\tif (copy_from_user(ptmp, p->pointer, len)) {\n\t\tret = -EFAULT;\n\t\tgoto exit;\n\t}\n\n\tbytes = 0;\n\taddr = 0;\n\tsscanf(ptmp, \"%d,%x\", &bytes, &addr);\n\n\tswitch (bytes) {\n\tcase 1:\n\t\tdata32 = rtw_read8(padapter, addr);\n\t\tsprintf(extra, \"0x%02X\", data32);\n\t\tbreak;\n\tcase 2:\n\t\tdata32 = rtw_read16(padapter, addr);\n\t\tsprintf(extra, \"0x%04X\", data32);\n\t\tbreak;\n\tcase 4:\n\t\tdata32 = rtw_read32(padapter, addr);\n\t\tsprintf(extra, \"0x%08X\", data32);\n\t\tbreak;\n\n\t#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_SDIO_INDIRECT_ACCESS) && defined(DBG_SDIO_INDIRECT_ACCESS)\n\tcase 11:\n\t\tdata32 = rtw_sd_iread8(padapter, addr);\n\t\tsprintf(extra, \"0x%02X\", data32);\n\t\tbreak;\n\tcase 12:\n\t\tdata32 = rtw_sd_iread16(padapter, addr);\n\t\tsprintf(extra, \"0x%04X\", data32);\n\t\tbreak;\n\tcase 14:\n\t\tdata32 = rtw_sd_iread32(padapter, addr);\n\t\tsprintf(extra, \"0x%08X\", data32);\n\t\tbreak;\n\t#endif\n\tdefault:\n\t\tRTW_INFO(\"%s: usage> read [bytes],[address(hex)]\\n\", __func__);\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\tRTW_INFO(\"%s: addr=0x%08X data=%s\\n\", __func__, addr, extra);\n\nexit:\n\trtw_mfree(ptmp, len);\n\n\treturn 0;\n}\n\nstatic int rtw_wx_write32(struct net_device *dev,\n\t\t\t  struct iw_request_info *info,\n\t\t\t  union iwreq_data *wrqu, char *extra)\n{\n\tPADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev);\n\n\tu32 addr;\n\tu32 data32;\n\tu32 bytes;\n\n\n\tbytes = 0;\n\taddr = 0;\n\tdata32 = 0;\n\tsscanf(extra, \"%d,%x,%x\", &bytes, &addr, &data32);\n\n\tswitch (bytes) {\n\tcase 1:\n\t\trtw_write8(padapter, addr, (u8)data32);\n\t\tRTW_INFO(\"%s: addr=0x%08X data=0x%02X\\n\", __func__, addr, (u8)data32);\n\t\tbreak;\n\tcase 2:\n\t\trtw_write16(padapter, addr, (u16)data32);\n\t\tRTW_INFO(\"%s: addr=0x%08X data=0x%04X\\n\", __func__, addr, (u16)data32);\n\t\tbreak;\n\tcase 4:\n\t\trtw_write32(padapter, addr, data32);\n\t\tRTW_INFO(\"%s: addr=0x%08X data=0x%08X\\n\", __func__, addr, data32);\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(\"%s: usage> write [bytes],[address(hex)],[data(hex)]\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic int rtw_wx_read_rf(struct net_device *dev,\n\t\t\t  struct iw_request_info *info,\n\t\t\t  union iwreq_data *wrqu, char *extra)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu32 path, addr, data32;\n\n\n\tpath = *(u32 *)extra;\n\taddr = *((u32 *)extra + 1);\n\tdata32 = rtw_hal_read_rfreg(padapter, path, addr, 0xFFFFF);\n\t/*\tRTW_INFO(\"%s: path=%d addr=0x%02x data=0x%05x\\n\", __func__, path, addr, data32); */\n\t/*\n\t * IMPORTANT!!\n\t * Only when wireless private ioctl is at odd order,\n\t * \"extra\" would be copied to user space.\n\t */\n\tsprintf(extra, \"0x%05x\", data32);\n\n\treturn 0;\n}\n\nstatic int rtw_wx_write_rf(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu32 path, addr, data32;\n\n\n\tpath = *(u32 *)extra;\n\taddr = *((u32 *)extra + 1);\n\tdata32 = *((u32 *)extra + 2);\n\t/*\tRTW_INFO(\"%s: path=%d addr=0x%02x data=0x%05x\\n\", __func__, path, addr, data32); */\n\trtw_hal_write_rfreg(padapter, path, addr, 0xFFFFF, data32);\n\n\treturn 0;\n}\n\nstatic int rtw_wx_priv_null(struct net_device *dev, struct iw_request_info *a,\n\t\t\t    union iwreq_data *wrqu, char *b)\n{\n\treturn -1;\n}\n\n#ifdef CONFIG_RTW_80211K\nextern void rm_dbg_cmd(_adapter *padapter, char *s);\nstatic int rtw_wx_priv_rrm(struct net_device *dev, struct iw_request_info *a,\n\t\t\t    union iwreq_data *wrqu, char *b)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu32 path, addr, data32;\n\n\n\trm_dbg_cmd(padapter, b);\n\twrqu->data.length = strlen(b);\n\n\treturn 0;\n}\n#endif\n\nstatic int dummy(struct net_device *dev, struct iw_request_info *a,\n\t\t union iwreq_data *wrqu, char *b)\n{\n\t/* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\t */\n\t/* struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); */\n\n\t/* RTW_INFO(\"cmd_code=%x, fwstate=0x%x\\n\", a->cmd, get_fwstate(pmlmepriv)); */\n\n\treturn -1;\n\n}\n\nstatic int rtw_wx_set_channel_plan(struct net_device *dev,\n\t\t\t\t   struct iw_request_info *info,\n\t\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8 channel_plan_req = (u8)(*((int *)wrqu));\n\n\tif (_SUCCESS != rtw_set_channel_plan(padapter, channel_plan_req))\n\t\treturn -EPERM;\n\n\treturn 0;\n}\n\nstatic int rtw_wx_set_mtk_wps_probe_ie(struct net_device *dev,\n\t\t\t\t       struct iw_request_info *a,\n\t\t\t\t       union iwreq_data *wrqu, char *b)\n{\n#ifdef CONFIG_PLATFORM_MT53XX\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n#endif\n\treturn 0;\n}\n\nstatic int rtw_wx_get_sensitivity(struct net_device *dev,\n\t\t\t\t  struct iw_request_info *info,\n\t\t\t\t  union iwreq_data *wrqu, char *buf)\n{\n#ifdef CONFIG_PLATFORM_MT53XX\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\t/*\tModified by Albert 20110914 */\n\t/*\tThis is in dbm format for MTK platform. */\n\twrqu->qual.level = padapter->recvpriv.rssi;\n\tRTW_INFO(\" level = %u\\n\",  wrqu->qual.level);\n#endif\n\treturn 0;\n}\n\nstatic int rtw_wx_set_mtk_wps_ie(struct net_device *dev,\n\t\t\t\t struct iw_request_info *info,\n\t\t\t\t union iwreq_data *wrqu, char *extra)\n{\n#ifdef CONFIG_PLATFORM_MT53XX\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\treturn rtw_set_wpa_ie(padapter, wrqu->data.pointer, wrqu->data.length);\n#else\n\treturn 0;\n#endif\n}\n\n#ifdef MP_IOCTL_HDL\nstatic void rtw_dbg_mode_hdl(_adapter *padapter, u32 id, u8 *pdata, u32 len)\n{\n\tpRW_Reg\tRegRWStruct;\n\tstruct rf_reg_param *prfreg;\n\tu8 path;\n\tu8 offset;\n\tu32 value;\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\tswitch (id) {\n\tcase GEN_MP_IOCTL_SUBCODE(MP_START):\n\t\tRTW_INFO(\"871x_driver is only for normal mode, can't enter mp mode\\n\");\n\t\tbreak;\n\tcase GEN_MP_IOCTL_SUBCODE(READ_REG):\n\t\tRegRWStruct = (pRW_Reg)pdata;\n\t\tswitch (RegRWStruct->width) {\n\t\tcase 1:\n\t\t\tRegRWStruct->value = rtw_read8(padapter, RegRWStruct->offset);\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tRegRWStruct->value = rtw_read16(padapter, RegRWStruct->offset);\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\tRegRWStruct->value = rtw_read32(padapter, RegRWStruct->offset);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tbreak;\n\tcase GEN_MP_IOCTL_SUBCODE(WRITE_REG):\n\t\tRegRWStruct = (pRW_Reg)pdata;\n\t\tswitch (RegRWStruct->width) {\n\t\tcase 1:\n\t\t\trtw_write8(padapter, RegRWStruct->offset, (u8)RegRWStruct->value);\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\trtw_write16(padapter, RegRWStruct->offset, (u16)RegRWStruct->value);\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\trtw_write32(padapter, RegRWStruct->offset, (u32)RegRWStruct->value);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tbreak;\n\tcase GEN_MP_IOCTL_SUBCODE(READ_RF_REG):\n\n\t\tprfreg = (struct rf_reg_param *)pdata;\n\n\t\tpath = (u8)prfreg->path;\n\t\toffset = (u8)prfreg->offset;\n\n\t\tvalue = rtw_hal_read_rfreg(padapter, path, offset, 0xffffffff);\n\n\t\tprfreg->value = value;\n\n\t\tbreak;\n\tcase GEN_MP_IOCTL_SUBCODE(WRITE_RF_REG):\n\n\t\tprfreg = (struct rf_reg_param *)pdata;\n\n\t\tpath = (u8)prfreg->path;\n\t\toffset = (u8)prfreg->offset;\n\t\tvalue = prfreg->value;\n\n\t\trtw_hal_write_rfreg(padapter, path, offset, 0xffffffff, value);\n\n\t\tbreak;\n\tcase GEN_MP_IOCTL_SUBCODE(TRIGGER_GPIO):\n\t\tRTW_INFO(\"==> trigger gpio 0\\n\");\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_TRIGGER_GPIO_0, 0);\n\t\tbreak;\n#ifdef CONFIG_BT_COEXIST\n\tcase GEN_MP_IOCTL_SUBCODE(SET_DM_BT):\n\t\tRTW_INFO(\"==> set dm_bt_coexist:%x\\n\", *(u8 *)pdata);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_BT_SET_COEXIST, pdata);\n\t\tbreak;\n\tcase GEN_MP_IOCTL_SUBCODE(DEL_BA):\n\t\tRTW_INFO(\"==> delete ba:%x\\n\", *(u8 *)pdata);\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_BT_ISSUE_DELBA, pdata);\n\t\tbreak;\n#endif\n#ifdef DBG_CONFIG_ERROR_DETECT\n\tcase GEN_MP_IOCTL_SUBCODE(GET_WIFI_STATUS):\n\t\t*pdata = rtw_hal_sreset_get_wifi_status(padapter);\n\t\tbreak;\n#endif\n\n\tdefault:\n\t\tbreak;\n\t}\n\n}\nstatic int rtw_mp_ioctl_hdl(struct net_device *dev, struct iw_request_info *info,\n\t\t\t    union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\tu32 BytesRead, BytesWritten, BytesNeeded;\n\tstruct oid_par_priv\toid_par;\n\tstruct mp_ioctl_handler\t*phandler;\n\tstruct mp_ioctl_param\t*poidparam;\n\tuint status = 0;\n\tu16 len;\n\tu8 *pparmbuf = NULL, bset;\n\tPADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev);\n\tstruct iw_point *p = &wrqu->data;\n\n\t/* RTW_INFO(\"+rtw_mp_ioctl_hdl\\n\"); */\n\n\t/* mutex_lock(&ioctl_mutex); */\n\n\tif ((!p->length) || (!p->pointer)) {\n\t\tret = -EINVAL;\n\t\tgoto _rtw_mp_ioctl_hdl_exit;\n\t}\n\n\tpparmbuf = NULL;\n\tbset = (u8)(p->flags & 0xFFFF);\n\tlen = p->length;\n\tpparmbuf = (u8 *)rtw_malloc(len);\n\tif (pparmbuf == NULL) {\n\t\tret = -ENOMEM;\n\t\tgoto _rtw_mp_ioctl_hdl_exit;\n\t}\n\n\tif (copy_from_user(pparmbuf, p->pointer, len)) {\n\t\tret = -EFAULT;\n\t\tgoto _rtw_mp_ioctl_hdl_exit;\n\t}\n\n\tpoidparam = (struct mp_ioctl_param *)pparmbuf;\n\n\tif (poidparam->subcode >= MAX_MP_IOCTL_SUBCODE) {\n\t\tret = -EINVAL;\n\t\tgoto _rtw_mp_ioctl_hdl_exit;\n\t}\n\n\t/* RTW_INFO(\"%s: %d\\n\", __func__, poidparam->subcode); */\n#ifdef CONFIG_MP_INCLUDED\n\tif (padapter->registrypriv.mp_mode == 1) {\n\t\tphandler = mp_ioctl_hdl + poidparam->subcode;\n\n\t\tif ((phandler->paramsize != 0) && (poidparam->len < phandler->paramsize)) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto _rtw_mp_ioctl_hdl_exit;\n\t\t}\n\n\t\tif (phandler->handler) {\n\t\t\toid_par.adapter_context = padapter;\n\t\t\toid_par.oid = phandler->oid;\n\t\t\toid_par.information_buf = poidparam->data;\n\t\t\toid_par.information_buf_len = poidparam->len;\n\t\t\toid_par.dbg = 0;\n\n\t\t\tBytesWritten = 0;\n\t\t\tBytesNeeded = 0;\n\n\t\t\tif (bset) {\n\t\t\t\toid_par.bytes_rw = &BytesRead;\n\t\t\t\toid_par.bytes_needed = &BytesNeeded;\n\t\t\t\toid_par.type_of_oid = SET_OID;\n\t\t\t} else {\n\t\t\t\toid_par.bytes_rw = &BytesWritten;\n\t\t\t\toid_par.bytes_needed = &BytesNeeded;\n\t\t\t\toid_par.type_of_oid = QUERY_OID;\n\t\t\t}\n\n\t\t\tstatus = phandler->handler(&oid_par);\n\n\t\t\t/* todo:check status, BytesNeeded, etc. */\n\t\t} else {\n\t\t\tRTW_INFO(\"rtw_mp_ioctl_hdl(): err!, subcode=%d, oid=%d, handler=%p\\n\",\n\t\t\t\tpoidparam->subcode, phandler->oid, phandler->handler);\n\t\t\tret = -EFAULT;\n\t\t\tgoto _rtw_mp_ioctl_hdl_exit;\n\t\t}\n\t} else\n#endif\n\t{\n\t\trtw_dbg_mode_hdl(padapter, poidparam->subcode, poidparam->data, poidparam->len);\n\t}\n\n\tif (bset == 0x00) {/* query info */\n\t\tif (copy_to_user(p->pointer, pparmbuf, len))\n\t\t\tret = -EFAULT;\n\t}\n\n\tif (status) {\n\t\tret = -EFAULT;\n\t\tgoto _rtw_mp_ioctl_hdl_exit;\n\t}\n\n_rtw_mp_ioctl_hdl_exit:\n\n\tif (pparmbuf)\n\t\trtw_mfree(pparmbuf, len);\n\n\t/* mutex_unlock(&ioctl_mutex); */\n\n\treturn ret;\n}\n#endif /*MP_IOCTL_HDL*/\nstatic int rtw_get_ap_info(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\tu32 cnt = 0, wpa_ielen;\n\t_irqL\tirqL;\n\t_list\t*plist, *phead;\n\tunsigned char *pbuf;\n\tu8 bssid[ETH_ALEN];\n\tchar data[32];\n\tstruct wlan_network *pnetwork = NULL;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\t_queue *queue = &(pmlmepriv->scanned_queue);\n\tstruct iw_point *pdata = &wrqu->data;\n\n\tRTW_INFO(\"+rtw_get_aplist_info\\n\");\n\n\tif (rtw_is_drv_stopped(padapter) || (pdata == NULL)) {\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\n\twhile ((check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY | _FW_UNDER_LINKING))) == _TRUE) {\n\t\trtw_msleep_os(30);\n\t\tcnt++;\n\t\tif (cnt > 100)\n\t\t\tbreak;\n\t}\n\n\n\t/* pdata->length = 0; */ /* ?\t */\n\tpdata->flags = 0;\n\tif (pdata->length >= 32) {\n\t\tif (copy_from_user(data, pdata->pointer, 32)) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t} else {\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\n\twhile (1) {\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\n\t\t/* if(hwaddr_aton_i(pdata->pointer, bssid)) */\n\t\tif (hwaddr_aton_i(data, bssid)) {\n\t\t\tRTW_INFO(\"Invalid BSSID '%s'.\\n\", (u8 *)data);\n\t\t\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\t\t\treturn -EINVAL;\n\t\t}\n\n\n\t\tif (_rtw_memcmp(bssid, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE) { /* BSSID match, then check if supporting wpa/wpa2 */\n\t\t\tRTW_INFO(\"BSSID:\" MAC_FMT \"\\n\", MAC_ARG(bssid));\n\n\t\t\tpbuf = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12);\n\t\t\tif (pbuf && (wpa_ielen > 0)) {\n\t\t\t\tpdata->flags = 1;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tpbuf = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12);\n\t\t\tif (pbuf && (wpa_ielen > 0)) {\n\t\t\t\tpdata->flags = 2;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t}\n\n\t\tplist = get_next(plist);\n\n\t}\n\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tif (pdata->length >= 34) {\n\t\tif (copy_to_user((u8 *)pdata->pointer + 32, (u8 *)&pdata->flags, 1)) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t}\n\nexit:\n\n\treturn ret;\n\n}\n\nstatic int rtw_set_pid(struct net_device *dev,\n\t\t       struct iw_request_info *info,\n\t\t       union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = rtw_netdev_priv(dev);\n\tint *pdata = (int *)wrqu;\n\tint selector;\n\n\tif (rtw_is_drv_stopped(padapter) || (pdata == NULL)) {\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\n\tselector = *pdata;\n\tif (selector < 3 && selector >= 0) {\n\t\tpadapter->pid[selector] = *(pdata + 1);\n#ifdef CONFIG_GLOBAL_UI_PID\n\t\tui_pid[selector] = *(pdata + 1);\n#endif\n\t\tRTW_INFO(\"%s set pid[%d]=%d\\n\", __FUNCTION__, selector , padapter->pid[selector]);\n\t} else\n\t\tRTW_INFO(\"%s selector %d error\\n\", __FUNCTION__, selector);\n\nexit:\n\n\treturn ret;\n\n}\n\nstatic int rtw_wps_start(struct net_device *dev,\n\t\t\t struct iw_request_info *info,\n\t\t\t union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct iw_point *pdata = &wrqu->data;\n\tu32   u32wps_start = 0;\n\tunsigned int uintRet = 0;\n\n\tif (RTW_CANNOT_RUN(padapter) || (NULL == pdata)) {\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\n\tuintRet = copy_from_user((void *) &u32wps_start, pdata->pointer, 4);\n\tif (u32wps_start == 0)\n\t\tu32wps_start = *extra;\n\n\tRTW_INFO(\"[%s] wps_start = %d\\n\", __FUNCTION__, u32wps_start);\n\n\tif (u32wps_start == 1)   /* WPS Start */\n\t\trtw_led_control(padapter, LED_CTL_START_WPS);\n\telse if (u32wps_start == 2)   /* WPS Stop because of wps success */\n\t\trtw_led_control(padapter, LED_CTL_STOP_WPS);\n\telse if (u32wps_start == 3)   /* WPS Stop because of wps fail */\n\t\trtw_led_control(padapter, LED_CTL_STOP_WPS_FAIL);\n\nexit:\n\n\treturn ret;\n\n}\n\n#ifdef CONFIG_P2P\nstatic int rtw_wext_p2p_enable(struct net_device *dev,\n\t\t\t       struct iw_request_info *info,\n\t\t\t       union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tenum P2P_ROLE init_role = P2P_ROLE_DISABLE;\n\n\tif (*extra == '0')\n\t\tinit_role = P2P_ROLE_DISABLE;\n\telse if (*extra == '1')\n\t\tinit_role = P2P_ROLE_DEVICE;\n\telse if (*extra == '2')\n\t\tinit_role = P2P_ROLE_CLIENT;\n\telse if (*extra == '3')\n\t\tinit_role = P2P_ROLE_GO;\n\n\tif (_FAIL == rtw_p2p_enable(padapter, init_role)) {\n\t\tret = -EFAULT;\n\t\tgoto exit;\n\t}\n\n\t/* set channel/bandwidth */\n\tif (init_role != P2P_ROLE_DISABLE) {\n\t\tu8 channel, ch_offset;\n\t\tu16 bwmode;\n\n\t\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN)) {\n\t\t\t/*\tStay at the listen state and wait for discovery. */\n\t\t\tchannel = pwdinfo->listen_channel;\n\t\t\tpwdinfo->operating_channel = pwdinfo->listen_channel;\n\t\t\tch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\t\tbwmode = CHANNEL_WIDTH_20;\n\t\t}\n#ifdef CONFIG_CONCURRENT_MODE\n\t\telse if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) {\n\n\t\t\t_set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_interval);\n\n\t\t\tchannel = rtw_mi_get_union_chan(padapter);\n\t\t\tch_offset = rtw_mi_get_union_offset(padapter);\n\t\t\tbwmode = rtw_mi_get_union_bw(padapter);\n\n\t\t\tpwdinfo->operating_channel = channel;\n\t\t}\n#endif\n\t\telse {\n\t\t\tpwdinfo->operating_channel = pmlmeext->cur_channel;\n\n\t\t\tchannel = pwdinfo->operating_channel;\n\t\t\tch_offset = pmlmeext->cur_ch_offset;\n\t\t\tbwmode = pmlmeext->cur_bwmode;\n\t\t}\n\n\t\tset_channel_bwmode(padapter, channel, ch_offset, bwmode);\n\t}\n\nexit:\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_set_go_nego_ssid(struct net_device *dev,\n\t\t\t\t    struct iw_request_info *info,\n\t\t\t\t    union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n\n\tRTW_INFO(\"[%s] ssid = %s, len = %zu\\n\", __FUNCTION__, extra, strlen(extra));\n\t_rtw_memcpy(pwdinfo->nego_ssid, extra, strlen(extra));\n\tpwdinfo->nego_ssidlen = strlen(extra);\n\n\treturn ret;\n\n}\n\n\nstatic int rtw_p2p_set_intent(struct net_device *dev,\n\t\t\t      struct iw_request_info *info,\n\t\t\t      union iwreq_data *wrqu, char *extra)\n{\n\tint\t\t\t\t\t\t\tret = 0;\n\t_adapter\t\t\t\t\t\t*padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t\t\t*pwdinfo = &(padapter->wdinfo);\n\tu8\t\t\t\t\t\t\tintent = pwdinfo->intent;\n\n\textra[wrqu->data.length] = 0x00;\n\n\tintent = rtw_atoi(extra);\n\n\tif (intent <= 15)\n\t\tpwdinfo->intent = intent;\n\telse\n\t\tret = -1;\n\n\tRTW_INFO(\"[%s] intent = %d\\n\", __FUNCTION__, intent);\n\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_set_listen_ch(struct net_device *dev,\n\t\t\t\t struct iw_request_info *info,\n\t\t\t\t union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n\tu8\tlisten_ch = pwdinfo->listen_channel;\t/*\tListen channel number */\n\n\textra[wrqu->data.length] = 0x00;\n\tlisten_ch = rtw_atoi(extra);\n\n\tif ((listen_ch == 1) || (listen_ch == 6) || (listen_ch == 11)) {\n\t\tpwdinfo->listen_channel = listen_ch;\n\t\tset_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n\t} else\n\t\tret = -1;\n\n\tRTW_INFO(\"[%s] listen_ch = %d\\n\", __FUNCTION__, pwdinfo->listen_channel);\n\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_set_op_ch(struct net_device *dev,\n\t\t\t     struct iw_request_info *info,\n\t\t\t     union iwreq_data *wrqu, char *extra)\n{\n\t/*\tCommented by Albert 20110524\n\t *\tThis function is used to set the operating channel if the driver will become the group owner */\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n\tu8\top_ch = pwdinfo->operating_channel;\t/*\tOperating channel number */\n\n\textra[wrqu->data.length] = 0x00;\n\n\top_ch = (u8) rtw_atoi(extra);\n\tif (op_ch > 0)\n\t\tpwdinfo->operating_channel = op_ch;\n\telse\n\t\tret = -1;\n\n\tRTW_INFO(\"[%s] op_ch = %d\\n\", __FUNCTION__, pwdinfo->operating_channel);\n\n\treturn ret;\n\n}\n\n\nstatic int rtw_p2p_profilefound(struct net_device *dev,\n\t\t\t\tstruct iw_request_info *info,\n\t\t\t\tunion iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n\n\t/*\tComment by Albert 2010/10/13 */\n\t/*\tInput data format: */\n\t/*\tEx:  0 */\n\t/*\tEx:  1XX:XX:XX:XX:XX:XXYYSSID */\n\t/*\t0 => Reflush the profile record list. */\n\t/*\t1 => Add the profile list */\n\t/*\tXX:XX:XX:XX:XX:XX => peer's MAC Address ( ex: 00:E0:4C:00:00:01 ) */\n\t/*\tYY => SSID Length */\n\t/*\tSSID => SSID for persistence group */\n\n\tRTW_INFO(\"[%s] In value = %s, len = %d\\n\", __FUNCTION__, extra, wrqu->data.length - 1);\n\n\n\t/*\tThe upper application should pass the SSID to driver by using this rtw_p2p_profilefound function. */\n\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {\n\t\tif (extra[0] == '0') {\n\t\t\t/*\tRemove all the profile information of wifidirect_info structure. */\n\t\t\t_rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM);\n\t\t\tpwdinfo->profileindex = 0;\n\t\t} else {\n\t\t\tif (pwdinfo->profileindex >= P2P_MAX_PERSISTENT_GROUP_NUM)\n\t\t\t\tret = -1;\n\t\t\telse {\n\t\t\t\tint jj, kk;\n\n\t\t\t\t/*\tAdd this profile information into pwdinfo->profileinfo */\n\t\t\t\t/*\tEx:  1XX:XX:XX:XX:XX:XXYYSSID */\n\t\t\t\tfor (jj = 0, kk = 1; jj < ETH_ALEN; jj++, kk += 3)\n\t\t\t\t\tpwdinfo->profileinfo[pwdinfo->profileindex].peermac[jj] = key_2char2num(extra[kk], extra[kk + 1]);\n\n\t\t\t\t/* pwdinfo->profileinfo[pwdinfo->profileindex].ssidlen = ( extra[18] - '0' ) * 10 + ( extra[19] - '0' ); */\n\t\t\t\t/* _rtw_memcpy( pwdinfo->profileinfo[pwdinfo->profileindex].ssid, &extra[20], pwdinfo->profileinfo[pwdinfo->profileindex].ssidlen ); */\n\t\t\t\tpwdinfo->profileindex++;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_setDN(struct net_device *dev,\n\t\t\t struct iw_request_info *info,\n\t\t\t union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n\n\n\tRTW_INFO(\"[%s] %s %d\\n\", __FUNCTION__, extra, wrqu->data.length - 1);\n\t_rtw_memset(pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN);\n\t_rtw_memcpy(pwdinfo->device_name, extra, wrqu->data.length - 1);\n\tpwdinfo->device_name_len = wrqu->data.length - 1;\n\n\treturn ret;\n\n}\n\n\nstatic int rtw_p2p_get_status(struct net_device *dev,\n\t\t\t      struct iw_request_info *info,\n\t\t\t      union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\tif (padapter->bShowGetP2PState) {\n\t\tRTW_INFO(\"[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\\n\", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),\n\t\t\tpwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2],\n\t\t\tpwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);\n\t}\n\n\t/*\tCommented by Albert 2010/10/12 */\n\t/*\tBecause of the output size limitation, I had removed the \"Role\" information. */\n\t/*\tAbout the \"Role\" information, we will use the new private IOCTL to get the \"Role\" information. */\n\tsprintf(extra, \"\\n\\nStatus=%.2d\\n\", rtw_p2p_state(pwdinfo));\n\twrqu->data.length = strlen(extra);\n\n\treturn ret;\n\n}\n\n/*\tCommented by Albert 20110520\n *\tThis function will return the config method description\n *\tThis config method description will show us which config method the remote P2P device is intented to use\n *\tby sending the provisioning discovery request frame. */\n\nstatic int rtw_p2p_get_req_cm(struct net_device *dev,\n\t\t\t      struct iw_request_info *info,\n\t\t\t      union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\tsprintf(extra, \"\\n\\nCM=%s\\n\", pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req);\n\twrqu->data.length = strlen(extra);\n\treturn ret;\n\n}\n\n\nstatic int rtw_p2p_get_role(struct net_device *dev,\n\t\t\t    struct iw_request_info *info,\n\t\t\t    union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\tRTW_INFO(\"[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\\n\", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),\n\t\tpwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2],\n\t\tpwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);\n\n\tsprintf(extra, \"\\n\\nRole=%.2d\\n\", rtw_p2p_role(pwdinfo));\n\twrqu->data.length = strlen(extra);\n\treturn ret;\n\n}\n\n\nstatic int rtw_p2p_get_peer_ifaddr(struct net_device *dev,\n\t\t\t\t   struct iw_request_info *info,\n\t\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\n\tRTW_INFO(\"[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\\n\", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),\n\t\tpwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2],\n\t\tpwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);\n\n\tsprintf(extra, \"\\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\",\n\t\tpwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2],\n\t\tpwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);\n\twrqu->data.length = strlen(extra);\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_get_peer_devaddr(struct net_device *dev,\n\t\t\t\t    struct iw_request_info *info,\n\t\t\t\t    union iwreq_data *wrqu, char *extra)\n\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\tRTW_INFO(\"[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\\n\", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),\n\t\tpwdinfo->rx_prov_disc_info.peerDevAddr[0], pwdinfo->rx_prov_disc_info.peerDevAddr[1],\n\t\tpwdinfo->rx_prov_disc_info.peerDevAddr[2], pwdinfo->rx_prov_disc_info.peerDevAddr[3],\n\t\tpwdinfo->rx_prov_disc_info.peerDevAddr[4], pwdinfo->rx_prov_disc_info.peerDevAddr[5]);\n\tsprintf(extra, \"\\n%.2X%.2X%.2X%.2X%.2X%.2X\",\n\t\tpwdinfo->rx_prov_disc_info.peerDevAddr[0], pwdinfo->rx_prov_disc_info.peerDevAddr[1],\n\t\tpwdinfo->rx_prov_disc_info.peerDevAddr[2], pwdinfo->rx_prov_disc_info.peerDevAddr[3],\n\t\tpwdinfo->rx_prov_disc_info.peerDevAddr[4], pwdinfo->rx_prov_disc_info.peerDevAddr[5]);\n\twrqu->data.length = strlen(extra);\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_get_peer_devaddr_by_invitation(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra)\n\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\tRTW_INFO(\"[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\\n\", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),\n\t\tpwdinfo->p2p_peer_device_addr[0], pwdinfo->p2p_peer_device_addr[1],\n\t\tpwdinfo->p2p_peer_device_addr[2], pwdinfo->p2p_peer_device_addr[3],\n\t\tpwdinfo->p2p_peer_device_addr[4], pwdinfo->p2p_peer_device_addr[5]);\n\tsprintf(extra, \"\\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\",\n\t\tpwdinfo->p2p_peer_device_addr[0], pwdinfo->p2p_peer_device_addr[1],\n\t\tpwdinfo->p2p_peer_device_addr[2], pwdinfo->p2p_peer_device_addr[3],\n\t\tpwdinfo->p2p_peer_device_addr[4], pwdinfo->p2p_peer_device_addr[5]);\n\twrqu->data.length = strlen(extra);\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_get_groupid(struct net_device *dev,\n\t\t\t       struct iw_request_info *info,\n\t\t\t       union iwreq_data *wrqu, char *extra)\n\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\tsprintf(extra, \"\\n%.2X:%.2X:%.2X:%.2X:%.2X:%.2X %s\",\n\t\tpwdinfo->groupid_info.go_device_addr[0], pwdinfo->groupid_info.go_device_addr[1],\n\t\tpwdinfo->groupid_info.go_device_addr[2], pwdinfo->groupid_info.go_device_addr[3],\n\t\tpwdinfo->groupid_info.go_device_addr[4], pwdinfo->groupid_info.go_device_addr[5],\n\t\tpwdinfo->groupid_info.ssid);\n\twrqu->data.length = strlen(extra);\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_get_op_ch(struct net_device *dev,\n\t\t\t     struct iw_request_info *info,\n\t\t\t     union iwreq_data *wrqu, char *extra)\n\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\n\tRTW_INFO(\"[%s] Op_ch = %02x\\n\", __FUNCTION__, pwdinfo->operating_channel);\n\n\tsprintf(extra, \"\\n\\nOp_ch=%.2d\\n\", pwdinfo->operating_channel);\n\twrqu->data.length = strlen(extra);\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_get_wps_configmethod(struct net_device *dev,\n\t\t\t\t\tstruct iw_request_info *info,\n\t\t\tunion iwreq_data *wrqu, char *extra, char *subcmd)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8 peerMAC[ETH_ALEN] = { 0x00 };\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\t_irqL irqL;\n\t_list *plist, *phead;\n\t_queue *queue = &(pmlmepriv->scanned_queue);\n\tstruct wlan_network *pnetwork = NULL;\n\tu8 blnMatch = 0;\n\tu16\tattr_content = 0;\n\tuint attr_contentlen = 0;\n\tu8\tattr_content_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };\n\n\t/*\tCommented by Albert 20110727 */\n\t/*\tThe input data is the MAC address which the application wants to know its WPS config method. */\n\t/*\tAfter knowing its WPS config method, the application can decide the config method for provisioning discovery. */\n\t/*\tFormat: iwpriv wlanx p2p_get_wpsCM 00:E0:4C:00:00:05 */\n\n\tRTW_INFO(\"[%s] data = %s\\n\", __FUNCTION__, subcmd);\n\n\tmacstr2num(peerMAC, subcmd);\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\n\twhile (1) {\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\t\tif (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {\n\t\t\tu8 *wpsie;\n\t\t\tuint\twpsie_len = 0;\n\n\t\t\t/*\tThe mac address is matched. */\n\n\t\t\twpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]);\n\t\t\tif (wpsie) {\n\t\t\t\trtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_CONF_METHOD, (u8 *)&attr_content, &attr_contentlen);\n\t\t\t\tif (attr_contentlen) {\n\t\t\t\t\tattr_content = be16_to_cpu(attr_content);\n\t\t\t\t\tsprintf(attr_content_str, \"\\n\\nM=%.4d\", attr_content);\n\t\t\t\t\tblnMatch = 1;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tbreak;\n\t\t}\n\n\t\tplist = get_next(plist);\n\n\t}\n\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tif (!blnMatch)\n\t\tsprintf(attr_content_str, \"\\n\\nM=0000\");\n\n\twrqu->data.length = strlen(attr_content_str);\n\t_rtw_memcpy(extra, attr_content_str, wrqu->data.length);\n\n\treturn ret;\n\n}\n\n#ifdef CONFIG_WFD\nstatic int rtw_p2p_get_peer_wfd_port(struct net_device *dev,\n\t\t\t\t     struct iw_request_info *info,\n\t\t\t\t     union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\tRTW_INFO(\"[%s] p2p_state = %d\\n\", __FUNCTION__, rtw_p2p_state(pwdinfo));\n\n\tsprintf(extra, \"\\n\\nPort=%d\\n\", pwdinfo->wfd_info->peer_rtsp_ctrlport);\n\tRTW_INFO(\"[%s] remote port = %d\\n\", __FUNCTION__, pwdinfo->wfd_info->peer_rtsp_ctrlport);\n\n\twrqu->data.length = strlen(extra);\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_get_peer_wfd_preferred_connection(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\tsprintf(extra, \"\\n\\nwfd_pc=%d\\n\", pwdinfo->wfd_info->wfd_pc);\n\tRTW_INFO(\"[%s] wfd_pc = %d\\n\", __FUNCTION__, pwdinfo->wfd_info->wfd_pc);\n\n\twrqu->data.length = strlen(extra);\n\tpwdinfo->wfd_info->wfd_pc = _FALSE;\t/*\tReset the WFD preferred connection to P2P */\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_get_peer_wfd_session_available(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\tsprintf(extra, \"\\n\\nwfd_sa=%d\\n\", pwdinfo->wfd_info->peer_session_avail);\n\tRTW_INFO(\"[%s] wfd_sa = %d\\n\", __FUNCTION__, pwdinfo->wfd_info->peer_session_avail);\n\n\twrqu->data.length = strlen(extra);\n\tpwdinfo->wfd_info->peer_session_avail = _TRUE;\t/*\tReset the WFD session available */\n\treturn ret;\n\n}\n#endif /* CONFIG_WFD */\n\nstatic int rtw_p2p_get_go_device_address(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra, char *subcmd)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8 peerMAC[ETH_ALEN] = { 0x00 };\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\t_irqL irqL;\n\t_list *plist, *phead;\n\t_queue *queue\t= &(pmlmepriv->scanned_queue);\n\tstruct wlan_network *pnetwork = NULL;\n\tu8 blnMatch = 0;\n\tu8 *p2pie;\n\tuint p2pielen = 0, attr_contentlen = 0;\n\tu8 attr_content[100] = { 0x00 };\n\tu8 go_devadd_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };\n\n\t/*\tCommented by Albert 20121209 */\n\t/*\tThe input data is the GO's interface address which the application wants to know its device address. */\n\t/*\tFormat: iwpriv wlanx p2p_get2 go_devadd=00:E0:4C:00:00:05 */\n\n\tRTW_INFO(\"[%s] data = %s\\n\", __FUNCTION__, subcmd);\n\n\tmacstr2num(peerMAC, subcmd);\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\n\twhile (1) {\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\t\tif (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {\n\t\t\t/*\tCommented by Albert 2011/05/18 */\n\t\t\t/*\tMatch the device address located in the P2P IE */\n\t\t\t/*\tThis is for the case that the P2P device address is not the same as the P2P interface address. */\n\n\t\t\tp2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);\n\t\t\tif (p2pie) {\n\t\t\t\twhile (p2pie) {\n\t\t\t\t\t/*\tThe P2P Device ID attribute is included in the Beacon frame. */\n\t\t\t\t\t/*\tThe P2P Device Info attribute is included in the probe response frame. */\n\n\t\t\t\t\t_rtw_memset(attr_content, 0x00, 100);\n\t\t\t\t\tif (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) {\n\t\t\t\t\t\t/*\tHandle the P2P Device ID attribute of Beacon first */\n\t\t\t\t\t\tblnMatch = 1;\n\t\t\t\t\t\tbreak;\n\n\t\t\t\t\t} else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) {\n\t\t\t\t\t\t/*\tHandle the P2P Device Info attribute of probe response */\n\t\t\t\t\t\tblnMatch = 1;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\n\t\t\t\t\t/* Get the next P2P IE */\n\t\t\t\t\tp2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tplist = get_next(plist);\n\n\t}\n\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tif (!blnMatch)\n\t\tsprintf(go_devadd_str, \"\\n\\ndev_add=NULL\");\n\telse {\n\t\tsprintf(go_devadd_str, \"\\n\\ndev_add=%.2X:%.2X:%.2X:%.2X:%.2X:%.2X\",\n\t\t\tattr_content[0], attr_content[1], attr_content[2], attr_content[3], attr_content[4], attr_content[5]);\n\t}\n\n\twrqu->data.length = strlen(go_devadd_str);\n\t_rtw_memcpy(extra, go_devadd_str, wrqu->data.length);\n\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_get_device_type(struct net_device *dev,\n\t\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra, char *subcmd)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8 peerMAC[ETH_ALEN] = { 0x00 };\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\t_irqL irqL;\n\t_list *plist, *phead;\n\t_queue *queue = &(pmlmepriv->scanned_queue);\n\tstruct wlan_network *pnetwork = NULL;\n\tu8 blnMatch = 0;\n\tu8 dev_type[8] = { 0x00 };\n\tuint dev_type_len = 0;\n\tu8 dev_type_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };    /* +9 is for the str \"dev_type=\", we have to clear it at wrqu->data.pointer */\n\n\t/*\tCommented by Albert 20121209 */\n\t/*\tThe input data is the MAC address which the application wants to know its device type. */\n\t/*\tSuch user interface could know the device type. */\n\t/*\tFormat: iwpriv wlanx p2p_get2 dev_type=00:E0:4C:00:00:05 */\n\n\tRTW_INFO(\"[%s] data = %s\\n\", __FUNCTION__, subcmd);\n\n\tmacstr2num(peerMAC, subcmd);\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\n\twhile (1) {\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\t\tif (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {\n\t\t\tu8 *wpsie;\n\t\t\tuint\twpsie_len = 0;\n\n\t\t\t/*\tThe mac address is matched. */\n\n\t\t\twpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]);\n\t\t\tif (wpsie) {\n\t\t\t\trtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_PRIMARY_DEV_TYPE, dev_type, &dev_type_len);\n\t\t\t\tif (dev_type_len) {\n\t\t\t\t\tu16\ttype = 0;\n\n\t\t\t\t\t_rtw_memcpy(&type, dev_type, 2);\n\t\t\t\t\ttype = be16_to_cpu(type);\n\t\t\t\t\tsprintf(dev_type_str, \"\\n\\nN=%.2d\", type);\n\t\t\t\t\tblnMatch = 1;\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\n\t\tplist = get_next(plist);\n\n\t}\n\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tif (!blnMatch)\n\t\tsprintf(dev_type_str, \"\\n\\nN=00\");\n\n\twrqu->data.length = strlen(dev_type_str);\n\t_rtw_memcpy(extra, dev_type_str, wrqu->data.length);\n\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_get_device_name(struct net_device *dev,\n\t\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra, char *subcmd)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8 peerMAC[ETH_ALEN] = { 0x00 };\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\t_irqL irqL;\n\t_list *plist, *phead;\n\t_queue *queue = &(pmlmepriv->scanned_queue);\n\tstruct wlan_network *pnetwork = NULL;\n\tu8 blnMatch = 0;\n\tu8 dev_name[WPS_MAX_DEVICE_NAME_LEN] = { 0x00 };\n\tuint dev_len = 0;\n\tu8 dev_name_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };\n\n\t/*\tCommented by Albert 20121225 */\n\t/*\tThe input data is the MAC address which the application wants to know its device name. */\n\t/*\tSuch user interface could show peer device's device name instead of ssid. */\n\t/*\tFormat: iwpriv wlanx p2p_get2 devN=00:E0:4C:00:00:05 */\n\n\tRTW_INFO(\"[%s] data = %s\\n\", __FUNCTION__, subcmd);\n\n\tmacstr2num(peerMAC, subcmd);\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\n\twhile (1) {\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\t\tif (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {\n\t\t\tu8 *wpsie;\n\t\t\tuint\twpsie_len = 0;\n\n\t\t\t/*\tThe mac address is matched. */\n\n\t\t\twpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]);\n\t\t\tif (wpsie) {\n\t\t\t\trtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_DEVICE_NAME, dev_name, &dev_len);\n\t\t\t\tif (dev_len) {\n\t\t\t\t\tsprintf(dev_name_str, \"\\n\\nN=%s\", dev_name);\n\t\t\t\t\tblnMatch = 1;\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\n\t\tplist = get_next(plist);\n\n\t}\n\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tif (!blnMatch)\n\t\tsprintf(dev_name_str, \"\\n\\nN=0000\");\n\n\twrqu->data.length = strlen(dev_name_str);\n\t_rtw_memcpy(extra, dev_name_str, wrqu->data.length);\n\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_get_invitation_procedure(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra, char *subcmd)\n{\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8 peerMAC[ETH_ALEN] = { 0x00 };\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\t_irqL irqL;\n\t_list *plist, *phead;\n\t_queue *queue\t= &(pmlmepriv->scanned_queue);\n\tstruct wlan_network *pnetwork = NULL;\n\tu8 blnMatch = 0;\n\tu8 *p2pie;\n\tuint p2pielen = 0, attr_contentlen = 0;\n\tu8 attr_content[2] = { 0x00 };\n\tu8 inv_proc_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };\n\n\t/*\tCommented by Ouden 20121226 */\n\t/*\tThe application wants to know P2P initation procedure is support or not. */\n\t/*\tFormat: iwpriv wlanx p2p_get2 InvProc=00:E0:4C:00:00:05 */\n\n\tRTW_INFO(\"[%s] data = %s\\n\", __FUNCTION__, subcmd);\n\n\tmacstr2num(peerMAC, subcmd);\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\n\twhile (1) {\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\t\tif (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {\n\t\t\t/*\tCommented by Albert 20121226 */\n\t\t\t/*\tMatch the device address located in the P2P IE */\n\t\t\t/*\tThis is for the case that the P2P device address is not the same as the P2P interface address. */\n\n\t\t\tp2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);\n\t\t\tif (p2pie) {\n\t\t\t\twhile (p2pie) {\n\t\t\t\t\t/* _rtw_memset( attr_content, 0x00, 2); */\n\t\t\t\t\tif (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_CAPABILITY, attr_content, &attr_contentlen)) {\n\t\t\t\t\t\t/*\tHandle the P2P capability attribute */\n\t\t\t\t\t\tblnMatch = 1;\n\t\t\t\t\t\tbreak;\n\n\t\t\t\t\t}\n\n\t\t\t\t\t/* Get the next P2P IE */\n\t\t\t\t\tp2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tplist = get_next(plist);\n\n\t}\n\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tif (!blnMatch)\n\t\tsprintf(inv_proc_str, \"\\nIP=-1\");\n\telse {\n\t\tif ((attr_content[0] & 0x20) == 0x20)\n\t\t\tsprintf(inv_proc_str, \"\\nIP=1\");\n\t\telse\n\t\t\tsprintf(inv_proc_str, \"\\nIP=0\");\n\t}\n\n\twrqu->data.length = strlen(inv_proc_str);\n\t_rtw_memcpy(extra, inv_proc_str, wrqu->data.length);\n\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_connect(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter\t\t\t\t*padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\tu8\t\t\t\t\tpeerMAC[ETH_ALEN] = { 0x00 };\n\tint\t\t\t\t\tjj, kk;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\t_irqL\t\t\t\tirqL;\n\t_list\t\t\t\t\t*plist, *phead;\n\t_queue\t\t\t\t*queue\t= &(pmlmepriv->scanned_queue);\n\tstruct\twlan_network\t*pnetwork = NULL;\n\tuint\t\t\t\t\tuintPeerChannel = 0;\n\n\t/*\tCommented by Albert 20110304 */\n\t/*\tThe input data contains two informations. */\n\t/*\t1. First information is the MAC address which wants to formate with */\n\t/*\t2. Second information is the WPS PINCode or \"pbc\" string for push button method */\n\t/*\tFormat: 00:E0:4C:00:00:05 */\n\t/*\tFormat: 00:E0:4C:00:00:05 */\n\n\tRTW_INFO(\"[%s] data = %s\\n\", __FUNCTION__, extra);\n\n\tif (pwdinfo->p2p_state == P2P_STATE_NONE) {\n\t\tRTW_INFO(\"[%s] WiFi Direct is disable!\\n\", __FUNCTION__);\n\t\treturn ret;\n\t}\n\n\tif (pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO)\n\t\treturn -1;\n\n\tfor (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)\n\t\tpeerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]);\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\n\twhile (1) {\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\t\tif (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {\n\t\t\tif (pnetwork->network.Configuration.DSConfig != 0)\n\t\t\t\tuintPeerChannel = pnetwork->network.Configuration.DSConfig;\n\t\t\telse if (pwdinfo->nego_req_info.peer_ch != 0)\n\t\t\t\tuintPeerChannel = pnetwork->network.Configuration.DSConfig = pwdinfo->nego_req_info.peer_ch;\n\t\t\telse {\n\t\t\t\t/* Unexpected case */\n\t\t\t\tuintPeerChannel = 0;\n\t\t\t\tRTW_INFO(\"%s  uintPeerChannel = 0\\n\", __func__);\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\n\t\tplist = get_next(plist);\n\n\t}\n\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tif (uintPeerChannel) {\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED))\n\t\t\t_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);\n#endif /* CONFIG_CONCURRENT_MODE */\n\n\t\t_rtw_memset(&pwdinfo->nego_req_info, 0x00, sizeof(struct tx_nego_req_info));\n\t\t_rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info));\n\n\t\tpwdinfo->nego_req_info.peer_channel_num[0] = uintPeerChannel;\n\t\t_rtw_memcpy(pwdinfo->nego_req_info.peerDevAddr, pnetwork->network.MacAddress, ETH_ALEN);\n\t\tpwdinfo->nego_req_info.benable = _TRUE;\n\n\t\t_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);\n\t\tif (rtw_p2p_state(pwdinfo) != P2P_STATE_GONEGO_OK) {\n\t\t\t/*\tRestore to the listen state if the current p2p state is not nego OK */\n\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);\n\t\t}\n\n\t\trtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));\n\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED)) {\n\t\t\tu8 union_ch = rtw_mi_get_union_chan(padapter);\n\t\t\tu8 union_bw = rtw_mi_get_union_bw(padapter);\n\t\t\tu8 union_offset = rtw_mi_get_union_offset(padapter);\n\n\t\t\tset_channel_bwmode(padapter, union_ch, union_offset, union_bw);\n\t\t\trtw_leave_opch(padapter);\n\t\t}\n#endif /* CONFIG_CONCURRENT_MODE */\n\n\t\tRTW_INFO(\"[%s] Start PreTx Procedure!\\n\", __FUNCTION__);\n\t\t_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED))\n\t\t\t_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_GO_NEGO_TIMEOUT);\n\t\telse\n\t\t\t_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT);\n#else\n\t\t_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT);\n#endif /* CONFIG_CONCURRENT_MODE\t\t */\n\n\t} else {\n\t\tRTW_INFO(\"[%s] Not Found in Scanning Queue~\\n\", __FUNCTION__);\n\t\tret = -1;\n\t}\n\n\treturn ret;\n}\n\nstatic int rtw_p2p_invite_req(struct net_device *dev,\n\t\t\t      struct iw_request_info *info,\n\t\t\t      union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter\t\t\t\t\t*padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t\t*pwdinfo = &(padapter->wdinfo);\n\tint\t\t\t\t\t\tjj, kk;\n\tstruct mlme_priv\t\t\t*pmlmepriv = &padapter->mlmepriv;\n\t_list\t\t\t\t\t\t*plist, *phead;\n\t_queue\t\t\t\t\t*queue\t= &(pmlmepriv->scanned_queue);\n\tstruct\twlan_network\t\t*pnetwork = NULL;\n\tuint\t\t\t\t\t\tuintPeerChannel = 0;\n\tu8\t\t\t\t\t\tattr_content[50] = { 0x00 };\n\tu8\t\t\t\t\t\t*p2pie;\n\tuint\t\t\t\t\t\tp2pielen = 0, attr_contentlen = 0;\n\t_irqL\t\t\t\t\tirqL;\n\tstruct tx_invite_req_info\t*pinvite_req_info = &pwdinfo->invitereq_info;\n\n\t/*\tCommented by Albert 20120321 */\n\t/*\tThe input data contains two informations. */\n\t/*\t1. First information is the P2P device address which you want to send to.\t */\n\t/*\t2. Second information is the group id which combines with GO's mac address, space and GO's ssid. */\n\t/*\tCommand line sample: iwpriv wlan0 p2p_set invite=\"00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy\" */\n\t/*\tFormat: 00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy */\n\n\tRTW_INFO(\"[%s] data = %s\\n\", __FUNCTION__, extra);\n\n\tif (wrqu->data.length <=  37) {\n\t\tRTW_INFO(\"[%s] Wrong format!\\n\", __FUNCTION__);\n\t\treturn ret;\n\t}\n\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {\n\t\tRTW_INFO(\"[%s] WiFi Direct is disable!\\n\", __FUNCTION__);\n\t\treturn ret;\n\t} else {\n\t\t/*\tReset the content of struct tx_invite_req_info */\n\t\tpinvite_req_info->benable = _FALSE;\n\t\t_rtw_memset(pinvite_req_info->go_bssid, 0x00, ETH_ALEN);\n\t\t_rtw_memset(pinvite_req_info->go_ssid, 0x00, WLAN_SSID_MAXLEN);\n\t\tpinvite_req_info->ssidlen = 0x00;\n\t\tpinvite_req_info->operating_ch = pwdinfo->operating_channel;\n\t\t_rtw_memset(pinvite_req_info->peer_macaddr, 0x00, ETH_ALEN);\n\t\tpinvite_req_info->token = 3;\n\t}\n\n\tfor (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)\n\t\tpinvite_req_info->peer_macaddr[jj] = key_2char2num(extra[kk], extra[kk + 1]);\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\n\twhile (1) {\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\n\t\t/*\tCommented by Albert 2011/05/18 */\n\t\t/*\tMatch the device address located in the P2P IE */\n\t\t/*\tThis is for the case that the P2P device address is not the same as the P2P interface address. */\n\n\t\tp2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);\n\t\tif (p2pie) {\n\t\t\t/*\tThe P2P Device ID attribute is included in the Beacon frame. */\n\t\t\t/*\tThe P2P Device Info attribute is included in the probe response frame. */\n\n\t\t\tif (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) {\n\t\t\t\t/*\tHandle the P2P Device ID attribute of Beacon first */\n\t\t\t\tif (_rtw_memcmp(attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN)) {\n\t\t\t\t\tuintPeerChannel = pnetwork->network.Configuration.DSConfig;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t} else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) {\n\t\t\t\t/*\tHandle the P2P Device Info attribute of probe response */\n\t\t\t\tif (_rtw_memcmp(attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN)) {\n\t\t\t\t\tuintPeerChannel = pnetwork->network.Configuration.DSConfig;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t}\n\n\t\tplist = get_next(plist);\n\n\t}\n\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n#ifdef CONFIG_WFD\n\tif (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST) && uintPeerChannel) {\n\t\tstruct wifi_display_info *pwfd_info = pwdinfo->wfd_info;\n\t\tu8 *wfd_ie;\n\t\tuint wfd_ielen = 0;\n\n\t\twfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen);\n\t\tif (wfd_ie) {\n\t\t\tu8 *wfd_devinfo;\n\t\t\tuint wfd_devlen;\n\n\t\t\tRTW_INFO(\"[%s] Found WFD IE!\\n\", __FUNCTION__);\n\t\t\twfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen);\n\t\t\tif (wfd_devinfo) {\n\t\t\t\tu16\twfd_devinfo_field = 0;\n\n\t\t\t\t/*\tCommented by Albert 20120319 */\n\t\t\t\t/*\tThe first two bytes are the WFD device information field of WFD device information subelement. */\n\t\t\t\t/*\tIn big endian format. */\n\t\t\t\twfd_devinfo_field = RTW_GET_BE16(wfd_devinfo);\n\t\t\t\tif (wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL)\n\t\t\t\t\tpwfd_info->peer_session_avail = _TRUE;\n\t\t\t\telse\n\t\t\t\t\tpwfd_info->peer_session_avail = _FALSE;\n\t\t\t}\n\t\t}\n\n\t\tif (_FALSE == pwfd_info->peer_session_avail) {\n\t\t\tRTW_INFO(\"[%s] WFD Session not avaiable!\\n\", __FUNCTION__);\n\t\t\tgoto exit;\n\t\t}\n\t}\n#endif /* CONFIG_WFD */\n\n\tif (uintPeerChannel) {\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED))\n\t\t\t_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);\n#endif /* CONFIG_CONCURRENT_MODE */\n\n\t\t/*\tStore the GO's bssid */\n\t\tfor (jj = 0, kk = 18; jj < ETH_ALEN; jj++, kk += 3)\n\t\t\tpinvite_req_info->go_bssid[jj] = key_2char2num(extra[kk], extra[kk + 1]);\n\n\t\t/*\tStore the GO's ssid */\n\t\tpinvite_req_info->ssidlen = wrqu->data.length - 36;\n\t\t_rtw_memcpy(pinvite_req_info->go_ssid, &extra[36], (u32) pinvite_req_info->ssidlen);\n\t\tpinvite_req_info->benable = _TRUE;\n\t\tpinvite_req_info->peer_ch = uintPeerChannel;\n\n\t\trtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));\n\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INVITE_REQ);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED)) {\n\t\t\tu8 union_ch = rtw_mi_get_union_chan(padapter);\n\t\t\tu8 union_bw = rtw_mi_get_union_bw(padapter);\n\t\t\tu8 union_offset = rtw_mi_get_union_offset(padapter);\n\n\t\t\tset_channel_bwmode(padapter, union_ch, union_offset, union_bw);\n\t\t\trtw_leave_opch(padapter);\n\n\t\t} else\n\t\t\tset_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n#else\n\t\tset_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n#endif/*CONFIG_CONCURRENT_MODE*/\n\n\t\t_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED))\n\t\t\t_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_INVITE_TIMEOUT);\n\t\telse\n\t\t\t_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_INVITE_TIMEOUT);\n#else\n\t\t_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_INVITE_TIMEOUT);\n#endif /* CONFIG_CONCURRENT_MODE\t\t */\n\n\n\t} else\n\t\tRTW_INFO(\"[%s] NOT Found in the Scanning Queue!\\n\", __FUNCTION__);\nexit:\n\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_set_persistent(struct net_device *dev,\n\t\t\t\t  struct iw_request_info *info,\n\t\t\t\t  union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter\t\t\t\t\t*padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t\t*pwdinfo = &(padapter->wdinfo);\n\n\t/*\tCommented by Albert 20120328 */\n\t/*\tThe input data is 0 or 1 */\n\t/*\t0: disable persistent group functionality */\n\t/*\t1: enable persistent group founctionality */\n\n\tRTW_INFO(\"[%s] data = %s\\n\", __FUNCTION__, extra);\n\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {\n\t\tRTW_INFO(\"[%s] WiFi Direct is disable!\\n\", __FUNCTION__);\n\t\treturn ret;\n\t} else {\n\t\tif (extra[0] == '0')\t/*\tDisable the persistent group function. */\n\t\t\tpwdinfo->persistent_supported = _FALSE;\n\t\telse if (extra[0] == '1')\t/*\tEnable the persistent group function. */\n\t\t\tpwdinfo->persistent_supported = _TRUE;\n\t\telse\n\t\t\tpwdinfo->persistent_supported = _FALSE;\n\t}\n\tprintk(\"[%s] persistent_supported = %d\\n\", __FUNCTION__, pwdinfo->persistent_supported);\n\n\treturn ret;\n\n}\n\nstatic int uuid_str2bin(const char *str, u8 *bin)\n{\n\tconst char *pos;\n\tu8 *opos;\n\n\tpos = str;\n\topos = bin;\n\n\tif (hexstr2bin(pos, opos, 4))\n\t\treturn -1;\n\tpos += 8;\n\topos += 4;\n\n\tif (*pos++ != '-' || hexstr2bin(pos, opos, 2))\n\t\treturn -1;\n\tpos += 4;\n\topos += 2;\n\n\tif (*pos++ != '-' || hexstr2bin(pos, opos, 2))\n\t\treturn -1;\n\tpos += 4;\n\topos += 2;\n\n\tif (*pos++ != '-' || hexstr2bin(pos, opos, 2))\n\t\treturn -1;\n\tpos += 4;\n\topos += 2;\n\n\tif (*pos++ != '-' || hexstr2bin(pos, opos, 6))\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic int rtw_p2p_set_wps_uuid(struct net_device *dev,\n\t\t\t\tstruct iw_request_info *info,\n\t\t\t\tunion iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter\t\t\t\t*padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t\t\t*pwdinfo = &(padapter->wdinfo);\n\n\tRTW_INFO(\"[%s] data = %s\\n\", __FUNCTION__, extra);\n\n\tif ((36 == strlen(extra)) && (uuid_str2bin(extra, pwdinfo->uuid) == 0))\n\t\tpwdinfo->external_uuid = 1;\n\telse {\n\t\tpwdinfo->external_uuid = 0;\n\t\tret = -EINVAL;\n\t}\n\n\treturn ret;\n\n}\n#ifdef CONFIG_WFD\nstatic int rtw_p2p_set_pc(struct net_device *dev,\n\t\t\t  struct iw_request_info *info,\n\t\t\t  union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter\t\t\t\t*padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\tu8\t\t\t\t\tpeerMAC[ETH_ALEN] = { 0x00 };\n\tint\t\t\t\t\tjj, kk;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\t_list\t\t\t\t\t*plist, *phead;\n\t_queue\t\t\t\t*queue\t= &(pmlmepriv->scanned_queue);\n\tstruct\twlan_network\t*pnetwork = NULL;\n\tu8\t\t\t\t\tattr_content[50] = { 0x00 };\n\tu8 *p2pie;\n\tuint\t\t\t\t\tp2pielen = 0, attr_contentlen = 0;\n\t_irqL\t\t\t\tirqL;\n\tuint\t\t\t\t\tuintPeerChannel = 0;\n\n\tstruct wifi_display_info\t*pwfd_info = pwdinfo->wfd_info;\n\n\t/*\tCommented by Albert 20120512 */\n\t/*\t1. Input information is the MAC address which wants to know the Preferred Connection bit (PC bit) */\n\t/*\tFormat: 00:E0:4C:00:00:05 */\n\n\tRTW_INFO(\"[%s] data = %s\\n\", __FUNCTION__, extra);\n\n\tif (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {\n\t\tRTW_INFO(\"[%s] WiFi Direct is disable!\\n\", __FUNCTION__);\n\t\treturn ret;\n\t}\n\n\tfor (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)\n\t\tpeerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]);\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\n\twhile (1) {\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\n\t\t/*\tCommented by Albert 2011/05/18 */\n\t\t/*\tMatch the device address located in the P2P IE */\n\t\t/*\tThis is for the case that the P2P device address is not the same as the P2P interface address. */\n\n\t\tp2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);\n\t\tif (p2pie) {\n\t\t\t/*\tThe P2P Device ID attribute is included in the Beacon frame. */\n\t\t\t/*\tThe P2P Device Info attribute is included in the probe response frame. */\n\t\t\tprintk(\"[%s] Got P2P IE\\n\", __FUNCTION__);\n\t\t\tif (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) {\n\t\t\t\t/*\tHandle the P2P Device ID attribute of Beacon first */\n\t\t\t\tprintk(\"[%s] P2P_ATTR_DEVICE_ID\\n\", __FUNCTION__);\n\t\t\t\tif (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) {\n\t\t\t\t\tuintPeerChannel = pnetwork->network.Configuration.DSConfig;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t} else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) {\n\t\t\t\t/*\tHandle the P2P Device Info attribute of probe response */\n\t\t\t\tprintk(\"[%s] P2P_ATTR_DEVICE_INFO\\n\", __FUNCTION__);\n\t\t\t\tif (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) {\n\t\t\t\t\tuintPeerChannel = pnetwork->network.Configuration.DSConfig;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t}\n\n\t\tplist = get_next(plist);\n\n\t}\n\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\tprintk(\"[%s] channel = %d\\n\", __FUNCTION__, uintPeerChannel);\n\n\tif (uintPeerChannel) {\n\t\tu8 *wfd_ie;\n\t\tuint wfd_ielen = 0;\n\n\t\twfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen);\n\t\tif (wfd_ie) {\n\t\t\tu8 *wfd_devinfo;\n\t\t\tuint wfd_devlen;\n\n\t\t\tRTW_INFO(\"[%s] Found WFD IE!\\n\", __FUNCTION__);\n\t\t\twfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen);\n\t\t\tif (wfd_devinfo) {\n\t\t\t\tu16\twfd_devinfo_field = 0;\n\n\t\t\t\t/*\tCommented by Albert 20120319 */\n\t\t\t\t/*\tThe first two bytes are the WFD device information field of WFD device information subelement. */\n\t\t\t\t/*\tIn big endian format. */\n\t\t\t\twfd_devinfo_field = RTW_GET_BE16(wfd_devinfo);\n\t\t\t\tif (wfd_devinfo_field & WFD_DEVINFO_PC_TDLS)\n\t\t\t\t\tpwfd_info->wfd_pc = _TRUE;\n\t\t\t\telse\n\t\t\t\t\tpwfd_info->wfd_pc = _FALSE;\n\t\t\t}\n\t\t}\n\t} else\n\t\tRTW_INFO(\"[%s] NOT Found in the Scanning Queue!\\n\", __FUNCTION__);\n\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_set_wfd_device_type(struct net_device *dev,\n\t\t\t\t       struct iw_request_info *info,\n\t\t\t\t       union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter\t\t\t\t\t*padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t\t*pwdinfo = &(padapter->wdinfo);\n\tstruct wifi_display_info\t\t*pwfd_info = pwdinfo->wfd_info;\n\n\t/*\tCommented by Albert 20120328 */\n\t/*\tThe input data is 0 or 1 */\n\t/*\t0: specify to Miracast source device */\n\t/*\t1 or others: specify to Miracast sink device (display device) */\n\n\tRTW_INFO(\"[%s] data = %s\\n\", __FUNCTION__, extra);\n\n\tif (extra[0] == '0')\t/*\tSet to Miracast source device. */\n\t\tpwfd_info->wfd_device_type = WFD_DEVINFO_SOURCE;\n\telse\t\t\t\t\t/*\tSet to Miracast sink device. */\n\t\tpwfd_info->wfd_device_type = WFD_DEVINFO_PSINK;\n\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_set_wfd_enable(struct net_device *dev,\n\t\t\t\t  struct iw_request_info *info,\n\t\t\t\t  union iwreq_data *wrqu, char *extra)\n{\n\t/*\tCommented by Kurt 20121206\n\t *\tThis function is used to set wfd enabled */\n\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n\n\tif (*extra == '0')\n\t\trtw_wfd_enable(padapter, 0);\n\telse if (*extra == '1')\n\t\trtw_wfd_enable(padapter, 1);\n\n\tRTW_INFO(\"[%s] wfd_enable = %d\\n\", __FUNCTION__, pwdinfo->wfd_info->wfd_enable);\n\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_set_driver_iface(struct net_device *dev,\n\t\t\t\t    struct iw_request_info *info,\n\t\t\t\t    union iwreq_data *wrqu, char *extra)\n{\n\t/*\tCommented by Kurt 20121206\n\t *\tThis function is used to set driver iface is WEXT or CFG80211 */\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n\n\tif (*extra == '1') {\n\t\tpwdinfo->driver_interface = DRIVER_WEXT;\n\t\tRTW_INFO(\"[%s] driver_interface = WEXT\\n\", __FUNCTION__);\n\t} else if (*extra == '2') {\n\t\tpwdinfo->driver_interface = DRIVER_CFG80211;\n\t\tRTW_INFO(\"[%s] driver_interface = CFG80211\\n\", __FUNCTION__);\n\t}\n\n\treturn ret;\n\n}\n\n/*\tTo set the WFD session available to enable or disable */\nstatic int rtw_p2p_set_sa(struct net_device *dev,\n\t\t\t  struct iw_request_info *info,\n\t\t\t  union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter\t\t\t\t\t*padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t\t*pwdinfo = &(padapter->wdinfo);\n\n\tRTW_INFO(\"[%s] data = %s\\n\", __FUNCTION__, extra);\n\n\tif (0) {\n\t\tRTW_INFO(\"[%s] WiFi Direct is disable!\\n\", __FUNCTION__);\n\t\treturn ret;\n\t} else {\n\t\tif (extra[0] == '0')\t/*\tDisable the session available. */\n\t\t\tpwdinfo->session_available = _FALSE;\n\t\telse if (extra[0] == '1')\t/*\tEnable the session available. */\n\t\t\tpwdinfo->session_available = _TRUE;\n\t\telse\n\t\t\tpwdinfo->session_available = _FALSE;\n\t}\n\tprintk(\"[%s] session available = %d\\n\", __FUNCTION__, pwdinfo->session_available);\n\n\treturn ret;\n\n}\n#endif /* CONFIG_WFD */\n\nstatic int rtw_p2p_prov_disc(struct net_device *dev,\n\t\t\t     struct iw_request_info *info,\n\t\t\t     union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\t_adapter\t\t\t\t*padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\tu8\t\t\t\t\tpeerMAC[ETH_ALEN] = { 0x00 };\n\tint\t\t\t\t\tjj, kk;\n\tstruct mlme_priv\t\t*pmlmepriv = &padapter->mlmepriv;\n\t_list\t\t\t\t\t*plist, *phead;\n\t_queue\t\t\t\t*queue\t= &(pmlmepriv->scanned_queue);\n\tstruct\twlan_network\t*pnetwork = NULL;\n\tuint\t\t\t\t\tuintPeerChannel = 0;\n\tu8\t\t\t\t\tattr_content[100] = { 0x00 };\n\tu8 *p2pie;\n\tuint\t\t\t\t\tp2pielen = 0, attr_contentlen = 0;\n\t_irqL\t\t\t\tirqL;\n\n\t/*\tCommented by Albert 20110301 */\n\t/*\tThe input data contains two informations. */\n\t/*\t1. First information is the MAC address which wants to issue the provisioning discovery request frame. */\n\t/*\t2. Second information is the WPS configuration method which wants to discovery */\n\t/*\tFormat: 00:E0:4C:00:00:05_display */\n\t/*\tFormat: 00:E0:4C:00:00:05_keypad */\n\t/*\tFormat: 00:E0:4C:00:00:05_pbc */\n\t/*\tFormat: 00:E0:4C:00:00:05_label */\n\n\tRTW_INFO(\"[%s] data = %s\\n\", __FUNCTION__, extra);\n\n\tif (pwdinfo->p2p_state == P2P_STATE_NONE) {\n\t\tRTW_INFO(\"[%s] WiFi Direct is disable!\\n\", __FUNCTION__);\n\t\treturn ret;\n\t} else {\n\t\t/*\tReset the content of struct tx_provdisc_req_info excluded the wps_config_method_request. */\n\t\t_rtw_memset(pwdinfo->tx_prov_disc_info.peerDevAddr, 0x00, ETH_ALEN);\n\t\t_rtw_memset(pwdinfo->tx_prov_disc_info.peerIFAddr, 0x00, ETH_ALEN);\n\t\t_rtw_memset(&pwdinfo->tx_prov_disc_info.ssid, 0x00, sizeof(NDIS_802_11_SSID));\n\t\tpwdinfo->tx_prov_disc_info.peer_channel_num[0] = 0;\n\t\tpwdinfo->tx_prov_disc_info.peer_channel_num[1] = 0;\n\t\tpwdinfo->tx_prov_disc_info.benable = _FALSE;\n\t}\n\n\tfor (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)\n\t\tpeerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]);\n\n\tif (_rtw_memcmp(&extra[18], \"display\", 7))\n\t\tpwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA;\n\telse if (_rtw_memcmp(&extra[18], \"keypad\", 7))\n\t\tpwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD;\n\telse if (_rtw_memcmp(&extra[18], \"pbc\", 3))\n\t\tpwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON;\n\telse if (_rtw_memcmp(&extra[18], \"label\", 5))\n\t\tpwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL;\n\telse {\n\t\tRTW_INFO(\"[%s] Unknown WPS config methodn\", __FUNCTION__);\n\t\treturn ret ;\n\t}\n\n\t_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tphead = get_list_head(queue);\n\tplist = get_next(phead);\n\n\twhile (1) {\n\t\tif (rtw_end_of_queue_search(phead, plist) == _TRUE)\n\t\t\tbreak;\n\n\t\tif (uintPeerChannel != 0)\n\t\t\tbreak;\n\n\t\tpnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);\n\n\t\t/*\tCommented by Albert 2011/05/18 */\n\t\t/*\tMatch the device address located in the P2P IE */\n\t\t/*\tThis is for the case that the P2P device address is not the same as the P2P interface address. */\n\n\t\tp2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);\n\t\tif (p2pie) {\n\t\t\twhile (p2pie) {\n\t\t\t\t/*\tThe P2P Device ID attribute is included in the Beacon frame. */\n\t\t\t\t/*\tThe P2P Device Info attribute is included in the probe response frame. */\n\n\t\t\t\tif (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) {\n\t\t\t\t\t/*\tHandle the P2P Device ID attribute of Beacon first */\n\t\t\t\t\tif (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) {\n\t\t\t\t\t\tuintPeerChannel = pnetwork->network.Configuration.DSConfig;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t} else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) {\n\t\t\t\t\t/*\tHandle the P2P Device Info attribute of probe response */\n\t\t\t\t\tif (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) {\n\t\t\t\t\t\tuintPeerChannel = pnetwork->network.Configuration.DSConfig;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\t/* Get the next P2P IE */\n\t\t\t\tp2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen);\n\t\t\t}\n\n\t\t}\n\n\t\tplist = get_next(plist);\n\n\t}\n\n\t_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);\n\n\tif (uintPeerChannel) {\n#ifdef CONFIG_WFD\n\t\tif (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {\n\t\t\tstruct wifi_display_info *pwfd_info = pwdinfo->wfd_info;\n\t\t\tu8 *wfd_ie;\n\t\t\tuint wfd_ielen = 0;\n\n\t\t\twfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen);\n\t\t\tif (wfd_ie) {\n\t\t\t\tu8 *wfd_devinfo;\n\t\t\t\tuint wfd_devlen;\n\n\t\t\t\tRTW_INFO(\"[%s] Found WFD IE!\\n\", __FUNCTION__);\n\t\t\t\twfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen);\n\t\t\t\tif (wfd_devinfo) {\n\t\t\t\t\tu16\twfd_devinfo_field = 0;\n\n\t\t\t\t\t/*\tCommented by Albert 20120319 */\n\t\t\t\t\t/*\tThe first two bytes are the WFD device information field of WFD device information subelement. */\n\t\t\t\t\t/*\tIn big endian format. */\n\t\t\t\t\twfd_devinfo_field = RTW_GET_BE16(wfd_devinfo);\n\t\t\t\t\tif (wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL)\n\t\t\t\t\t\tpwfd_info->peer_session_avail = _TRUE;\n\t\t\t\t\telse\n\t\t\t\t\t\tpwfd_info->peer_session_avail = _FALSE;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (_FALSE == pwfd_info->peer_session_avail) {\n\t\t\t\tRTW_INFO(\"[%s] WFD Session not avaiable!\\n\", __FUNCTION__);\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n#endif /* CONFIG_WFD */\n\n\t\tRTW_INFO(\"[%s] peer channel: %d!\\n\", __FUNCTION__, uintPeerChannel);\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED))\n\t\t\t_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);\n#endif /* CONFIG_CONCURRENT_MODE */\n\t\t_rtw_memcpy(pwdinfo->tx_prov_disc_info.peerIFAddr, pnetwork->network.MacAddress, ETH_ALEN);\n\t\t_rtw_memcpy(pwdinfo->tx_prov_disc_info.peerDevAddr, peerMAC, ETH_ALEN);\n\t\tpwdinfo->tx_prov_disc_info.peer_channel_num[0] = (u16) uintPeerChannel;\n\t\tpwdinfo->tx_prov_disc_info.benable = _TRUE;\n\t\trtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));\n\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ);\n\n\t\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT))\n\t\t\t_rtw_memcpy(&pwdinfo->tx_prov_disc_info.ssid, &pnetwork->network.Ssid, sizeof(NDIS_802_11_SSID));\n\t\telse if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\t\t_rtw_memcpy(pwdinfo->tx_prov_disc_info.ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN);\n\t\t\tpwdinfo->tx_prov_disc_info.ssid.SsidLength = P2P_WILDCARD_SSID_LEN;\n\t\t}\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED)) {\n\t\t\tu8 union_ch = rtw_mi_get_union_chan(padapter);\n\t\t\tu8 union_bw = rtw_mi_get_union_bw(padapter);\n\t\t\tu8 union_offset = rtw_mi_get_union_offset(padapter);\n\n\t\t\tset_channel_bwmode(padapter, union_ch, union_offset, union_bw);\n\t\t\trtw_leave_opch(padapter);\n\n\t\t} else\n\t\t\tset_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n#else\n\t\tset_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);\n#endif\n\n\t\t_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED))\n\t\t\t_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_PROVISION_TIMEOUT);\n\t\telse\n\t\t\t_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT);\n#else\n\t\t_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT);\n#endif /* CONFIG_CONCURRENT_MODE\t\t */\n\n\t} else {\n\t\tRTW_INFO(\"[%s] NOT Found in the Scanning Queue!\\n\", __FUNCTION__);\n\t}\nexit:\n\n\treturn ret;\n\n}\n\n/*\tAdded by Albert 20110328\n *\tThis function is used to inform the driver the user had specified the pin code value or pbc\n *\tto application. */\n\nstatic int rtw_p2p_got_wpsinfo(struct net_device *dev,\n\t\t\t       struct iw_request_info *info,\n\t\t\t       union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\t_adapter\t\t\t\t*padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wifidirect_info\t*pwdinfo = &(padapter->wdinfo);\n\n\n\tRTW_INFO(\"[%s] data = %s\\n\", __FUNCTION__, extra);\n\t/*\tAdded by Albert 20110328 */\n\t/*\tif the input data is P2P_NO_WPSINFO -> reset the wpsinfo */\n\t/*\tif the input data is P2P_GOT_WPSINFO_PEER_DISPLAY_PIN -> the utility just input the PIN code got from the peer P2P device. */\n\t/*\tif the input data is P2P_GOT_WPSINFO_SELF_DISPLAY_PIN -> the utility just got the PIN code from itself. */\n\t/*\tif the input data is P2P_GOT_WPSINFO_PBC -> the utility just determine to use the PBC */\n\n\tif (*extra == '0')\n\t\tpwdinfo->ui_got_wps_info = P2P_NO_WPSINFO;\n\telse if (*extra == '1')\n\t\tpwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PEER_DISPLAY_PIN;\n\telse if (*extra == '2')\n\t\tpwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_SELF_DISPLAY_PIN;\n\telse if (*extra == '3')\n\t\tpwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PBC;\n\telse\n\t\tpwdinfo->ui_got_wps_info = P2P_NO_WPSINFO;\n\n\treturn ret;\n\n}\n\n#endif /* CONFIG_P2P */\n\nstatic int rtw_p2p_set(struct net_device *dev,\n\t\t       struct iw_request_info *info,\n\t\t       union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n#ifdef CONFIG_P2P\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_INFO(\"[%s] extra = %s\\n\", __FUNCTION__, extra);\n\n\tif (_rtw_memcmp(extra, \"enable=\", 7))\n\t\trtw_wext_p2p_enable(dev, info, wrqu, &extra[7]);\n\telse if (_rtw_memcmp(extra, \"setDN=\", 6)) {\n\t\twrqu->data.length -= 6;\n\t\trtw_p2p_setDN(dev, info, wrqu, &extra[6]);\n\t} else if (_rtw_memcmp(extra, \"profilefound=\", 13)) {\n\t\twrqu->data.length -= 13;\n\t\trtw_p2p_profilefound(dev, info, wrqu, &extra[13]);\n\t} else if (_rtw_memcmp(extra, \"prov_disc=\", 10)) {\n\t\twrqu->data.length -= 10;\n\t\trtw_p2p_prov_disc(dev, info, wrqu, &extra[10]);\n\t} else if (_rtw_memcmp(extra, \"nego=\", 5)) {\n\t\twrqu->data.length -= 5;\n\t\trtw_p2p_connect(dev, info, wrqu, &extra[5]);\n\t} else if (_rtw_memcmp(extra, \"intent=\", 7)) {\n\t\t/*\tCommented by Albert 2011/03/23 */\n\t\t/*\tThe wrqu->data.length will include the null character */\n\t\t/*\tSo, we will decrease 7 + 1 */\n\t\twrqu->data.length -= 8;\n\t\trtw_p2p_set_intent(dev, info, wrqu, &extra[7]);\n\t} else if (_rtw_memcmp(extra, \"ssid=\", 5)) {\n\t\twrqu->data.length -= 5;\n\t\trtw_p2p_set_go_nego_ssid(dev, info, wrqu, &extra[5]);\n\t} else if (_rtw_memcmp(extra, \"got_wpsinfo=\", 12)) {\n\t\twrqu->data.length -= 12;\n\t\trtw_p2p_got_wpsinfo(dev, info, wrqu, &extra[12]);\n\t} else if (_rtw_memcmp(extra, \"listen_ch=\", 10)) {\n\t\t/*\tCommented by Albert 2011/05/24 */\n\t\t/*\tThe wrqu->data.length will include the null character */\n\t\t/*\tSo, we will decrease (10 + 1)\t */\n\t\twrqu->data.length -= 11;\n\t\trtw_p2p_set_listen_ch(dev, info, wrqu, &extra[10]);\n\t} else if (_rtw_memcmp(extra, \"op_ch=\", 6)) {\n\t\t/*\tCommented by Albert 2011/05/24 */\n\t\t/*\tThe wrqu->data.length will include the null character */\n\t\t/*\tSo, we will decrease (6 + 1)\t */\n\t\twrqu->data.length -= 7;\n\t\trtw_p2p_set_op_ch(dev, info, wrqu, &extra[6]);\n\t} else if (_rtw_memcmp(extra, \"invite=\", 7)) {\n\t\twrqu->data.length -= 8;\n\t\trtw_p2p_invite_req(dev, info, wrqu, &extra[7]);\n\t} else if (_rtw_memcmp(extra, \"persistent=\", 11)) {\n\t\twrqu->data.length -= 11;\n\t\trtw_p2p_set_persistent(dev, info, wrqu, &extra[11]);\n\t} else if (_rtw_memcmp(extra, \"uuid=\", 5)) {\n\t\twrqu->data.length -= 5;\n\t\tret = rtw_p2p_set_wps_uuid(dev, info, wrqu, &extra[5]);\n\t}\n\n#ifdef CONFIG_WFD\n\tif (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {\n\t\tif (_rtw_memcmp(extra, \"sa=\", 3)) {\n\t\t\t/* sa: WFD Session Available information */\n\t\t\twrqu->data.length -= 3;\n\t\t\trtw_p2p_set_sa(dev, info, wrqu, &extra[3]);\n\t\t} else if (_rtw_memcmp(extra, \"pc=\", 3)) {\n\t\t\t/* pc: WFD Preferred Connection */\n\t\t\twrqu->data.length -= 3;\n\t\t\trtw_p2p_set_pc(dev, info, wrqu, &extra[3]);\n\t\t} else if (_rtw_memcmp(extra, \"wfd_type=\", 9)) {\n\t\t\twrqu->data.length -= 9;\n\t\t\trtw_p2p_set_wfd_device_type(dev, info, wrqu, &extra[9]);\n\t\t} else if (_rtw_memcmp(extra, \"wfd_enable=\", 11)) {\n\t\t\twrqu->data.length -= 11;\n\t\t\trtw_p2p_set_wfd_enable(dev, info, wrqu, &extra[11]);\n\t\t} else if (_rtw_memcmp(extra, \"driver_iface=\", 13)) {\n\t\t\twrqu->data.length -= 13;\n\t\t\trtw_p2p_set_driver_iface(dev, info, wrqu, &extra[13]);\n\t\t}\n\t}\n#endif /* CONFIG_WFD */\n\n#endif /* CONFIG_P2P */\n\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_get(struct net_device *dev,\n\t\t       struct iw_request_info *info,\n\t\t       union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n#ifdef CONFIG_P2P\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (padapter->bShowGetP2PState)\n\t\tRTW_INFO(\"[%s] extra = %s\\n\", __FUNCTION__, (char *) wrqu->data.pointer);\n\n\tif (_rtw_memcmp(wrqu->data.pointer, \"status\", 6))\n\t\trtw_p2p_get_status(dev, info, wrqu, extra);\n\telse if (_rtw_memcmp(wrqu->data.pointer, \"role\", 4))\n\t\trtw_p2p_get_role(dev, info, wrqu, extra);\n\telse if (_rtw_memcmp(wrqu->data.pointer, \"peer_ifa\", 8))\n\t\trtw_p2p_get_peer_ifaddr(dev, info, wrqu, extra);\n\telse if (_rtw_memcmp(wrqu->data.pointer, \"req_cm\", 6))\n\t\trtw_p2p_get_req_cm(dev, info, wrqu, extra);\n\telse if (_rtw_memcmp(wrqu->data.pointer, \"peer_deva\", 9)) {\n\t\t/*\tGet the P2P device address when receiving the provision discovery request frame. */\n\t\trtw_p2p_get_peer_devaddr(dev, info, wrqu, extra);\n\t} else if (_rtw_memcmp(wrqu->data.pointer, \"group_id\", 8))\n\t\trtw_p2p_get_groupid(dev, info, wrqu, extra);\n\telse if (_rtw_memcmp(wrqu->data.pointer, \"inv_peer_deva\", 13)) {\n\t\t/*\tGet the P2P device address when receiving the P2P Invitation request frame. */\n\t\trtw_p2p_get_peer_devaddr_by_invitation(dev, info, wrqu, extra);\n\t} else if (_rtw_memcmp(wrqu->data.pointer, \"op_ch\", 5))\n\t\trtw_p2p_get_op_ch(dev, info, wrqu, extra);\n\n#ifdef CONFIG_WFD\n\tif (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {\n\t\tif (_rtw_memcmp(wrqu->data.pointer, \"peer_port\", 9))\n\t\t\trtw_p2p_get_peer_wfd_port(dev, info, wrqu, extra);\n\t\telse if (_rtw_memcmp(wrqu->data.pointer, \"wfd_sa\", 6))\n\t\t\trtw_p2p_get_peer_wfd_session_available(dev, info, wrqu, extra);\n\t\telse if (_rtw_memcmp(wrqu->data.pointer, \"wfd_pc\", 6))\n\t\t\trtw_p2p_get_peer_wfd_preferred_connection(dev, info, wrqu, extra);\n\t}\n#endif /* CONFIG_WFD */\n\n#endif /* CONFIG_P2P */\n\n\treturn ret;\n\n}\n\nstatic int rtw_p2p_get2(struct net_device *dev,\n\t\t\tstruct iw_request_info *info,\n\t\t\tunion iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\n#ifdef CONFIG_P2P\n\n\tint length = wrqu->data.length;\n\tchar *buffer = (u8 *)rtw_malloc(length);\n\n\tif (buffer == NULL) {\n\t\tret = -ENOMEM;\n\t\tgoto bad;\n\t}\n\n\tif (copy_from_user(buffer, wrqu->data.pointer, wrqu->data.length)) {\n\t\tret = -EFAULT;\n\t\tgoto bad;\n\t}\n\n\tRTW_INFO(\"[%s] buffer = %s\\n\", __FUNCTION__, buffer);\n\n\tif (_rtw_memcmp(buffer, \"wpsCM=\", 6))\n\t\tret = rtw_p2p_get_wps_configmethod(dev, info, wrqu, extra, &buffer[6]);\n\telse if (_rtw_memcmp(buffer, \"devN=\", 5))\n\t\tret = rtw_p2p_get_device_name(dev, info, wrqu, extra, &buffer[5]);\n\telse if (_rtw_memcmp(buffer, \"dev_type=\", 9))\n\t\tret = rtw_p2p_get_device_type(dev, info, wrqu, extra, &buffer[9]);\n\telse if (_rtw_memcmp(buffer, \"go_devadd=\", 10))\n\t\tret = rtw_p2p_get_go_device_address(dev, info, wrqu, extra, &buffer[10]);\n\telse if (_rtw_memcmp(buffer, \"InvProc=\", 8))\n\t\tret = rtw_p2p_get_invitation_procedure(dev, info, wrqu, extra, &buffer[8]);\n\telse {\n\t\tsnprintf(extra, sizeof(\"Command not found.\"), \"Command not found.\");\n\t\twrqu->data.length = strlen(extra);\n\t}\n\nbad:\n\tif (buffer)\n\t\trtw_mfree(buffer, length);\n\n#endif /* CONFIG_P2P */\n\n\treturn ret;\n\n}\n\n#ifdef CONFIG_MP_INCLUDED\nstatic int rtw_cta_test_start(struct net_device *dev,\n\t\t\t      struct iw_request_info *info,\n\t\t\t      union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\t_adapter\t*padapter = (_adapter *)rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);\n\n\tRTW_INFO(\"%s %s\\n\", __func__, extra);\n\tif (!strcmp(extra, \"1\"))\n\t\thal_data->in_cta_test = 1;\n\telse\n\t\thal_data->in_cta_test = 0;\n\n\trtw_hal_rcr_set_chk_bssid(padapter, MLME_ACTION_NONE);\n\n\treturn ret;\n}\n#endif\nextern int rtw_change_ifname(_adapter *padapter, const char *ifname);\nstatic int rtw_rereg_nd_name(struct net_device *dev,\n\t\t\t     struct iw_request_info *info,\n\t\t\t     union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\t_adapter *padapter = rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\tstruct rereg_nd_name_data *rereg_priv = &padapter->rereg_nd_name_priv;\n\tchar new_ifname[IFNAMSIZ];\n\n\tif (rereg_priv->old_ifname[0] == 0) {\n\t\tchar *reg_ifname;\n#ifdef CONFIG_CONCURRENT_MODE\n\t\tif (padapter->isprimary)\n\t\t\treg_ifname = padapter->registrypriv.ifname;\n\t\telse\n#endif\n\t\t\treg_ifname = padapter->registrypriv.if2name;\n\n\t\tstrncpy(rereg_priv->old_ifname, reg_ifname, IFNAMSIZ);\n\t\trereg_priv->old_ifname[IFNAMSIZ - 1] = 0;\n\t}\n\n\t/* RTW_INFO(\"%s wrqu->data.length:%d\\n\", __FUNCTION__, wrqu->data.length); */\n\tif (wrqu->data.length > IFNAMSIZ)\n\t\treturn -EFAULT;\n\n\tif (copy_from_user(new_ifname, wrqu->data.pointer, IFNAMSIZ))\n\t\treturn -EFAULT;\n\n\tif (0 == strcmp(rereg_priv->old_ifname, new_ifname))\n\t\treturn ret;\n\n\tRTW_INFO(\"%s new_ifname:%s\\n\", __FUNCTION__, new_ifname);\n\trtw_set_rtnl_lock_holder(dvobj, current);\n\tret = rtw_change_ifname(padapter, new_ifname);\n\trtw_set_rtnl_lock_holder(dvobj, NULL);\n\tif (0 != ret)\n\t\tgoto exit;\n\n\tif (_rtw_memcmp(rereg_priv->old_ifname, \"disable%d\", 9) == _TRUE) {\n\t\t/* rtw_ips_mode_req(&padapter->pwrctrlpriv, rereg_priv->old_ips_mode); */\n\t}\n\n\tstrncpy(rereg_priv->old_ifname, new_ifname, IFNAMSIZ);\n\trereg_priv->old_ifname[IFNAMSIZ - 1] = 0;\n\n\tif (_rtw_memcmp(new_ifname, \"disable%d\", 9) == _TRUE) {\n\n\t\tRTW_INFO(\"%s disable\\n\", __FUNCTION__);\n\t\t/* free network queue for Android's timming issue */\n\t\trtw_free_network_queue(padapter, _TRUE);\n\n\t\t/* the interface is being \"disabled\", we can do deeper IPS */\n\t\t/* rereg_priv->old_ips_mode = rtw_get_ips_mode_req(&padapter->pwrctrlpriv); */\n\t\t/* rtw_ips_mode_req(&padapter->pwrctrlpriv, IPS_NORMAL); */\n\t}\nexit:\n\treturn ret;\n\n}\n\n#ifdef CONFIG_IOL\n#include <rtw_iol.h>\n#endif\n#ifdef CONFIG_BACKGROUND_NOISE_MONITOR\n#include \"../../hal/hal_dm_acs.h\"\n#endif\n#ifdef DBG_CMD_QUEUE\nu8 dump_cmd_id = 0;\n#endif\n\nstatic int rtw_dbg_port(struct net_device *dev,\n\t\t\tstruct iw_request_info *info,\n\t\t\tunion iwreq_data *wrqu, char *extra)\n{\n\t_irqL irqL;\n\tint ret = 0;\n\tu8 major_cmd, minor_cmd;\n\tu16 arg;\n\tu32 extra_arg, *pdata, val32;\n\tstruct sta_info *psta;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\tstruct wlan_network *cur_network = &(pmlmepriv->cur_network);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\n\tpdata = (u32 *)&wrqu->data;\n\n\tval32 = *pdata;\n\targ = (u16)(val32 & 0x0000ffff);\n\tmajor_cmd = (u8)(val32 >> 24);\n\tminor_cmd = (u8)((val32 >> 16) & 0x00ff);\n\n\textra_arg = *(pdata + 1);\n\n\tswitch (major_cmd) {\n\tcase 0x70: /* read_reg */\n\t\tswitch (minor_cmd) {\n\t\tcase 1:\n\t\t\tRTW_INFO(\"rtw_read8(0x%x)=0x%02x\\n\", arg, rtw_read8(padapter, arg));\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tRTW_INFO(\"rtw_read16(0x%x)=0x%04x\\n\", arg, rtw_read16(padapter, arg));\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\tRTW_INFO(\"rtw_read32(0x%x)=0x%08x\\n\", arg, rtw_read32(padapter, arg));\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase 0x71: /* write_reg */\n\t\tswitch (minor_cmd) {\n\t\tcase 1:\n\t\t\trtw_write8(padapter, arg, extra_arg);\n\t\t\tRTW_INFO(\"rtw_write8(0x%x)=0x%02x\\n\", arg, rtw_read8(padapter, arg));\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\trtw_write16(padapter, arg, extra_arg);\n\t\t\tRTW_INFO(\"rtw_write16(0x%x)=0x%04x\\n\", arg, rtw_read16(padapter, arg));\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\trtw_write32(padapter, arg, extra_arg);\n\t\t\tRTW_INFO(\"rtw_write32(0x%x)=0x%08x\\n\", arg, rtw_read32(padapter, arg));\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase 0x72: /* read_bb */\n\t\tRTW_INFO(\"read_bbreg(0x%x)=0x%x\\n\", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff));\n\t\tbreak;\n\tcase 0x73: /* write_bb */\n\t\trtw_hal_write_bbreg(padapter, arg, 0xffffffff, extra_arg);\n\t\tRTW_INFO(\"write_bbreg(0x%x)=0x%x\\n\", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff));\n\t\tbreak;\n\tcase 0x74: /* read_rf */\n\t\tRTW_INFO(\"read RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\\n\", minor_cmd, arg, rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff));\n\t\tbreak;\n\tcase 0x75: /* write_rf */\n\t\trtw_hal_write_rfreg(padapter, minor_cmd, arg, 0xffffffff, extra_arg);\n\t\tRTW_INFO(\"write RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\\n\", minor_cmd, arg, rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff));\n\t\tbreak;\n\n\tcase 0x76:\n\t\tswitch (minor_cmd) {\n\t\tcase 0x00: /* normal mode, */\n\t\t\tpadapter->recvpriv.is_signal_dbg = 0;\n\t\t\tbreak;\n\t\tcase 0x01: /* dbg mode */\n\t\t\tpadapter->recvpriv.is_signal_dbg = 1;\n\t\t\textra_arg = extra_arg > 100 ? 100 : extra_arg;\n\t\t\tpadapter->recvpriv.signal_strength_dbg = extra_arg;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase 0x78: /* IOL test */\n\t\tswitch (minor_cmd) {\n\t\t#ifdef CONFIG_IOL\n\t\tcase 0x04: { /* LLT table initialization test */\n\t\t\tu8 page_boundary = 0xf9;\n\t\t\t{\n\t\t\t\tstruct xmit_frame\t*xmit_frame;\n\n\t\t\t\txmit_frame = rtw_IOL_accquire_xmit_frame(padapter);\n\t\t\t\tif (xmit_frame == NULL) {\n\t\t\t\t\tret = -ENOMEM;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\trtw_IOL_append_LLT_cmd(xmit_frame, page_boundary);\n\n\n\t\t\t\tif (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 500, 0))\n\t\t\t\t\tret = -EPERM;\n\t\t\t}\n\t\t}\n\t\t\tbreak;\n\t\tcase 0x05: { /* blink LED test */\n\t\t\tu16 reg = 0x4c;\n\t\t\tu32 blink_num = 50;\n\t\t\tu32 blink_delay_ms = 200;\n\t\t\tint i;\n\n\t\t\t{\n\t\t\t\tstruct xmit_frame\t*xmit_frame;\n\n\t\t\t\txmit_frame = rtw_IOL_accquire_xmit_frame(padapter);\n\t\t\t\tif (xmit_frame == NULL) {\n\t\t\t\t\tret = -ENOMEM;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\tfor (i = 0; i < blink_num; i++) {\n\t\t\t\t\t#ifdef CONFIG_IOL_NEW_GENERATION\n\t\t\t\t\trtw_IOL_append_WB_cmd(xmit_frame, reg, 0x00, 0xff);\n\t\t\t\t\trtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);\n\t\t\t\t\trtw_IOL_append_WB_cmd(xmit_frame, reg, 0x08, 0xff);\n\t\t\t\t\trtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);\n\t\t\t\t\t#else\n\t\t\t\t\trtw_IOL_append_WB_cmd(xmit_frame, reg, 0x00);\n\t\t\t\t\trtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);\n\t\t\t\t\trtw_IOL_append_WB_cmd(xmit_frame, reg, 0x08);\n\t\t\t\t\trtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);\n\t\t\t\t\t#endif\n\t\t\t\t}\n\t\t\t\tif (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, (blink_delay_ms * blink_num * 2) + 200, 0))\n\t\t\t\t\tret = -EPERM;\n\t\t\t}\n\t\t}\n\t\t\tbreak;\n\n\t\tcase 0x06: { /* continuous wirte byte test */\n\t\t\tu16 reg = arg;\n\t\t\tu16 start_value = 0;\n\t\t\tu32 write_num = extra_arg;\n\t\t\tint i;\n\t\t\tu8 final;\n\n\t\t\t{\n\t\t\t\tstruct xmit_frame\t*xmit_frame;\n\n\t\t\t\txmit_frame = rtw_IOL_accquire_xmit_frame(padapter);\n\t\t\t\tif (xmit_frame == NULL) {\n\t\t\t\t\tret = -ENOMEM;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\tfor (i = 0; i < write_num; i++) {\n\t\t\t\t\t#ifdef CONFIG_IOL_NEW_GENERATION\n\t\t\t\t\trtw_IOL_append_WB_cmd(xmit_frame, reg, i + start_value, 0xFF);\n\t\t\t\t\t#else\n\t\t\t\t\trtw_IOL_append_WB_cmd(xmit_frame, reg, i + start_value);\n\t\t\t\t\t#endif\n\t\t\t\t}\n\t\t\t\tif (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0))\n\t\t\t\t\tret = -EPERM;\n\t\t\t}\n\n\t\t\tfinal = rtw_read8(padapter, reg);\n\t\t\tif (start_value + write_num - 1 == final)\n\t\t\t\tRTW_INFO(\"continuous IOL_CMD_WB_REG to 0x%x %u times Success, start:%u, final:%u\\n\", reg, write_num, start_value, final);\n\t\t\telse\n\t\t\t\tRTW_INFO(\"continuous IOL_CMD_WB_REG to 0x%x %u times Fail, start:%u, final:%u\\n\", reg, write_num, start_value, final);\n\t\t}\n\t\t\tbreak;\n\n\t\tcase 0x07: { /* continuous wirte word test */\n\t\t\tu16 reg = arg;\n\t\t\tu16 start_value = 200;\n\t\t\tu32 write_num = extra_arg;\n\n\t\t\tint i;\n\t\t\tu16 final;\n\n\t\t\t{\n\t\t\t\tstruct xmit_frame\t*xmit_frame;\n\n\t\t\t\txmit_frame = rtw_IOL_accquire_xmit_frame(padapter);\n\t\t\t\tif (xmit_frame == NULL) {\n\t\t\t\t\tret = -ENOMEM;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\tfor (i = 0; i < write_num; i++) {\n\t\t\t\t\t#ifdef CONFIG_IOL_NEW_GENERATION\n\t\t\t\t\trtw_IOL_append_WW_cmd(xmit_frame, reg, i + start_value, 0xFFFF);\n\t\t\t\t\t#else\n\t\t\t\t\trtw_IOL_append_WW_cmd(xmit_frame, reg, i + start_value);\n\t\t\t\t\t#endif\n\t\t\t\t}\n\t\t\t\tif (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0))\n\t\t\t\t\tret = -EPERM;\n\t\t\t}\n\n\t\t\tfinal = rtw_read16(padapter, reg);\n\t\t\tif (start_value + write_num - 1 == final)\n\t\t\t\tRTW_INFO(\"continuous IOL_CMD_WW_REG to 0x%x %u times Success, start:%u, final:%u\\n\", reg, write_num, start_value, final);\n\t\t\telse\n\t\t\t\tRTW_INFO(\"continuous IOL_CMD_WW_REG to 0x%x %u times Fail, start:%u, final:%u\\n\", reg, write_num, start_value, final);\n\t\t}\n\t\t\tbreak;\n\n\t\tcase 0x08: { /* continuous wirte dword test */\n\t\t\tu16 reg = arg;\n\t\t\tu32 start_value = 0x110000c7;\n\t\t\tu32 write_num = extra_arg;\n\n\t\t\tint i;\n\t\t\tu32 final;\n\n\t\t\t{\n\t\t\t\tstruct xmit_frame\t*xmit_frame;\n\n\t\t\t\txmit_frame = rtw_IOL_accquire_xmit_frame(padapter);\n\t\t\t\tif (xmit_frame == NULL) {\n\t\t\t\t\tret = -ENOMEM;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\tfor (i = 0; i < write_num; i++) {\n\t\t\t\t\t#ifdef CONFIG_IOL_NEW_GENERATION\n\t\t\t\t\trtw_IOL_append_WD_cmd(xmit_frame, reg, i + start_value, 0xFFFFFFFF);\n\t\t\t\t\t#else\n\t\t\t\t\trtw_IOL_append_WD_cmd(xmit_frame, reg, i + start_value);\n\t\t\t\t\t#endif\n\t\t\t\t}\n\t\t\t\tif (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0))\n\t\t\t\t\tret = -EPERM;\n\n\t\t\t}\n\n\t\t\tfinal = rtw_read32(padapter, reg);\n\t\t\tif (start_value + write_num - 1 == final)\n\t\t\t\tRTW_INFO(\"continuous IOL_CMD_WD_REG to 0x%x %u times Success, start:%u, final:%u\\n\", reg, write_num, start_value, final);\n\t\t\telse\n\t\t\t\tRTW_INFO(\"continuous IOL_CMD_WD_REG to 0x%x %u times Fail, start:%u, final:%u\\n\", reg, write_num, start_value, final);\n\t\t}\n\t\t\tbreak;\n\t\t#endif /* CONFIG_IOL */\n\t\t}\n\t\tbreak;\n\tcase 0x79: {\n\t\t/*\n\t\t* dbg 0x79000000 [value], set RESP_TXAGC to + value, value:0~15\n\t\t* dbg 0x79010000 [value], set RESP_TXAGC to - value, value:0~15\n\t\t*/\n\t\tu8 value =  extra_arg & 0x0f;\n\t\tu8 sign = minor_cmd;\n\t\tu16 write_value = 0;\n\n\t\tRTW_INFO(\"%s set RESP_TXAGC to %s %u\\n\", __func__, sign ? \"minus\" : \"plus\", value);\n\n\t\tif (sign)\n\t\t\tvalue = value | 0x10;\n\n\t\twrite_value = value | (value << 5);\n\t\trtw_write16(padapter, 0x6d9, write_value);\n\t}\n\t\tbreak;\n\tcase 0x7a:\n\t\treceive_disconnect(padapter, pmlmeinfo->network.MacAddress\n\t\t\t\t   , WLAN_REASON_EXPIRATION_CHK, _FALSE);\n\t\tbreak;\n\tcase 0x7F:\n\t\tswitch (minor_cmd) {\n\t\tcase 0x0:\n\t\t\tRTW_INFO(\"fwstate=0x%x\\n\", get_fwstate(pmlmepriv));\n\t\t\tbreak;\n\t\tcase 0x01:\n\t\t\tRTW_INFO(\"auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\\n\",\n\t\t\t\tpsecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm,\n\t\t\t\tpsecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus);\n\t\t\tbreak;\n\t\tcase 0x03:\n\t\t\tRTW_INFO(\"qos_option=%d\\n\", pmlmepriv->qospriv.qos_option);\n#ifdef CONFIG_80211N_HT\n\t\t\tRTW_INFO(\"ht_option=%d\\n\", pmlmepriv->htpriv.ht_option);\n#endif /* CONFIG_80211N_HT */\n\t\t\tbreak;\n\t\tcase 0x04:\n\t\t\tRTW_INFO(\"cur_ch=%d\\n\", pmlmeext->cur_channel);\n\t\t\tRTW_INFO(\"cur_bw=%d\\n\", pmlmeext->cur_bwmode);\n\t\t\tRTW_INFO(\"cur_ch_off=%d\\n\", pmlmeext->cur_ch_offset);\n\n\t\t\tRTW_INFO(\"oper_ch=%d\\n\", rtw_get_oper_ch(padapter));\n\t\t\tRTW_INFO(\"oper_bw=%d\\n\", rtw_get_oper_bw(padapter));\n\t\t\tRTW_INFO(\"oper_ch_offet=%d\\n\", rtw_get_oper_choffset(padapter));\n\n\t\t\tbreak;\n\t\tcase 0x05:\n\t\t\tpsta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);\n\t\t\tif (psta) {\n\t\t\t\tRTW_INFO(\"SSID=%s\\n\", cur_network->network.Ssid.Ssid);\n\t\t\t\tRTW_INFO(\"sta's macaddr:\" MAC_FMT \"\\n\", MAC_ARG(psta->cmn.mac_addr));\n\t\t\t\tRTW_INFO(\"cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\\n\", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);\n\t\t\t\tRTW_INFO(\"rtsen=%d, cts2slef=%d\\n\", psta->rtsen, psta->cts2self);\n\t\t\t\tRTW_INFO(\"state=0x%x, aid=%d, macid=%d, raid=%d\\n\",\n\t\t\t\t\tpsta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);\n#ifdef CONFIG_80211N_HT\n\t\t\t\tRTW_INFO(\"qos_en=%d, ht_en=%d, init_rate=%d\\n\", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);\n\t\t\t\tRTW_INFO(\"bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\\n\"\n\t\t\t\t\t, psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m);\n\t\t\t\tRTW_INFO(\"ampdu_enable = %d\\n\", psta->htpriv.ampdu_enable);\n\t\t\t\tRTW_INFO(\"agg_enable_bitmap=%x, candidate_tid_bitmap=%x\\n\", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);\n#endif /* CONFIG_80211N_HT */\n\n\t\t\t\tsta_rx_reorder_ctl_dump(RTW_DBGDUMP, psta);\n\t\t\t} else\n\t\t\t\tRTW_INFO(\"can't get sta's macaddr, cur_network's macaddr:\" MAC_FMT \"\\n\", MAC_ARG(cur_network->network.MacAddress));\n\t\t\tbreak;\n\t\tcase 0x06: {\n\t\t\t\tu64 tsf = 0;\n\n\t\t\t\ttsf = rtw_hal_get_tsftr_by_port(padapter, extra_arg);\n\t\t\t\tRTW_INFO(\" PORT-%d TSF :%21lld\\n\", extra_arg, tsf);\n\t\t}\n\t\t\tbreak;\n\t\tcase 0x07:\n\t\t\tRTW_INFO(\"bSurpriseRemoved=%s, bDriverStopped=%s\\n\"\n\t\t\t\t, rtw_is_surprise_removed(padapter) ? \"True\" : \"False\"\n\t\t\t\t, rtw_is_drv_stopped(padapter) ? \"True\" : \"False\");\n\t\t\tbreak;\n\t\tcase 0x08: {\n\t\t\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\t\t\tstruct recv_priv  *precvpriv = &padapter->recvpriv;\n\n\t\t\tRTW_INFO(\"free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d\"\n\t\t\t\t\", free_xmit_extbuf_cnt=%d, free_xframe_ext_cnt=%d\"\n\t\t\t\t \", free_recvframe_cnt=%d\\n\",\n\t\t\t\tpxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt,\n\t\t\t\tpxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt,\n\t\t\t\t precvpriv->free_recvframe_cnt);\n#ifdef CONFIG_USB_HCI\n\t\t\tRTW_INFO(\"rx_urb_pending_cn=%d\\n\", ATOMIC_READ(&(precvpriv->rx_pending_cnt)));\n#endif\n\t\t}\n\t\t\tbreak;\n\t\tcase 0x09: {\n\t\t\tint i;\n\t\t\t_list\t*plist, *phead;\n\n#ifdef CONFIG_AP_MODE\n\t\t\tRTW_INFO_DUMP(\"sta_dz_bitmap:\", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);\n\t\t\tRTW_INFO_DUMP(\"tim_bitmap:\", pstapriv->tim_bitmap, pstapriv->aid_bmp_len);\n#endif\n\t\t\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\t\t\tfor (i = 0; i < NUM_STA; i++) {\n\t\t\t\tphead = &(pstapriv->sta_hash[i]);\n\t\t\t\tplist = get_next(phead);\n\n\t\t\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\t\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\n\t\t\t\t\tplist = get_next(plist);\n\n\t\t\t\t\tif (extra_arg == psta->cmn.aid) {\n\t\t\t\t\t\tRTW_INFO(\"sta's macaddr:\" MAC_FMT \"\\n\", MAC_ARG(psta->cmn.mac_addr));\n\t\t\t\t\t\tRTW_INFO(\"rtsen=%d, cts2slef=%d\\n\", psta->rtsen, psta->cts2self);\n\t\t\t\t\t\tRTW_INFO(\"state=0x%x, aid=%d, macid=%d, raid=%d\\n\",\n\t\t\t\t\t\t\tpsta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);\n#ifdef CONFIG_80211N_HT\n\t\t\t\t\t\tRTW_INFO(\"qos_en=%d, ht_en=%d, init_rate=%d\\n\", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);\n\t\t\t\t\t\tRTW_INFO(\"bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\\n\",\n\t\t\t\t\t\t\tpsta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m,\n\t\t\t\t\t\t\tpsta->htpriv.sgi_40m);\n\t\t\t\t\t\tRTW_INFO(\"ampdu_enable = %d\\n\", psta->htpriv.ampdu_enable);\n\t\t\t\t\t\tRTW_INFO(\"agg_enable_bitmap=%x, candidate_tid_bitmap=%x\\n\", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);\n#endif /* CONFIG_80211N_HT */\n\n#ifdef CONFIG_AP_MODE\n\t\t\t\t\t\tRTW_INFO(\"capability=0x%x\\n\", psta->capability);\n\t\t\t\t\t\tRTW_INFO(\"flags=0x%x\\n\", psta->flags);\n\t\t\t\t\t\tRTW_INFO(\"wpa_psk=0x%x\\n\", psta->wpa_psk);\n\t\t\t\t\t\tRTW_INFO(\"wpa2_group_cipher=0x%x\\n\", psta->wpa2_group_cipher);\n\t\t\t\t\t\tRTW_INFO(\"wpa2_pairwise_cipher=0x%x\\n\", psta->wpa2_pairwise_cipher);\n\t\t\t\t\t\tRTW_INFO(\"qos_info=0x%x\\n\", psta->qos_info);\n#endif\n\t\t\t\t\t\tRTW_INFO(\"dot118021XPrivacy=0x%x\\n\", psta->dot118021XPrivacy);\n\n\t\t\t\t\t\tsta_rx_reorder_ctl_dump(RTW_DBGDUMP, psta);\n\t\t\t\t\t}\n\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\t\t}\n\t\t\tbreak;\n\n\t\tcase 0x0b: { /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */\n\t\t\t/* u8 driver_vcs_en; */ /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */\n\t\t\t/* u8 driver_vcs_type; */ /* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */\n\n\t\t\tif (arg == 0) {\n\t\t\t\tRTW_INFO(\"disable driver ctrl vcs\\n\");\n\t\t\t\tpadapter->driver_vcs_en = 0;\n\t\t\t} else if (arg == 1) {\n\t\t\t\tRTW_INFO(\"enable driver ctrl vcs = %d\\n\", extra_arg);\n\t\t\t\tpadapter->driver_vcs_en = 1;\n\n\t\t\t\tif (extra_arg > 2)\n\t\t\t\t\tpadapter->driver_vcs_type = 1;\n\t\t\t\telse\n\t\t\t\t\tpadapter->driver_vcs_type = extra_arg;\n\t\t\t}\n\t\t}\n\t\t\tbreak;\n\t\tcase 0x0c: { /* dump rx/tx packet */\n\t\t\tif (arg == 0) {\n\t\t\t\tRTW_INFO(\"dump rx packet (%d)\\n\", extra_arg);\n\t\t\t\t/* pHalData->bDumpRxPkt =extra_arg;\t\t\t\t\t\t */\n\t\t\t\trtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_RXPKT, &(extra_arg));\n\t\t\t} else if (arg == 1) {\n\t\t\t\tRTW_INFO(\"dump tx packet (%d)\\n\", extra_arg);\n\t\t\t\trtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(extra_arg));\n\t\t\t}\n\t\t}\n\t\t\tbreak;\n\t\tcase 0x0e: {\n\t\t\tif (arg == 0) {\n\t\t\t\tRTW_INFO(\"disable driver ctrl rx_ampdu_factor\\n\");\n\t\t\t\tpadapter->driver_rx_ampdu_factor = 0xFF;\n\t\t\t} else if (arg == 1) {\n\n\t\t\t\tRTW_INFO(\"enable driver ctrl rx_ampdu_factor = %d\\n\", extra_arg);\n\n\t\t\t\tif (extra_arg > 0x03)\n\t\t\t\t\tpadapter->driver_rx_ampdu_factor = 0xFF;\n\t\t\t\telse\n\t\t\t\t\tpadapter->driver_rx_ampdu_factor = extra_arg;\n\t\t\t}\n\t\t}\n\t\t\tbreak;\n\t\t#ifdef DBG_CONFIG_ERROR_DETECT\n\t\tcase 0x0f: {\n\t\t\tif (extra_arg == 0) {\n\t\t\t\tRTW_INFO(\"###### silent reset test.......#####\\n\");\n\t\t\t\trtw_hal_sreset_reset(padapter);\n\t\t\t} else {\n\t\t\t\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\t\t\t\tstruct sreset_priv *psrtpriv = &pHalData->srestpriv;\n\t\t\t\tpsrtpriv->dbg_trigger_point = extra_arg;\n\t\t\t}\n\n\t\t}\n\t\t\tbreak;\n\t\tcase 0x15: {\n\t\t\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\t\t\tRTW_INFO(\"==>silent resete cnts:%d\\n\", pwrpriv->ips_enter_cnts);\n\t\t}\n\t\t\tbreak;\n\n\t\t#endif\n\n\t\tcase 0x10: /* driver version display */\n\t\t\tdump_drv_version(RTW_DBGDUMP);\n\t\t\tbreak;\n\t\tcase 0x11: { /* dump linked status */\n\t\t\tint pre_mode;\n\t\t\tpre_mode = padapter->bLinkInfoDump;\n\t\t\t/* linked_info_dump(padapter,extra_arg); */\n\t\t\tif (extra_arg == 1 || (extra_arg == 0 && pre_mode == 1)) /* not consider pwr_saving 0: */\n\t\t\t\tpadapter->bLinkInfoDump = extra_arg;\n\n\t\t\telse if ((extra_arg == 2) || (extra_arg == 0 && pre_mode == 2)) { /* consider power_saving */\n\t\t\t\t/* RTW_INFO(\"linked_info_dump =%s\\n\", (padapter->bLinkInfoDump)?\"enable\":\"disable\") */\n\t\t\t\tlinked_info_dump(padapter, extra_arg);\n\t\t\t}\n\n\n\n\t\t}\n\t\t\tbreak;\n#ifdef CONFIG_80211N_HT\n\t\tcase 0x12: { /* set rx_stbc */\n\t\t\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\t\t\t/* 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, 0x3: enable both 2.4g and 5g */\n\t\t\t/* default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ */\n\t\t\tif (pregpriv && (extra_arg == 0 || extra_arg == 1 || extra_arg == 2 || extra_arg == 3)) {\n\t\t\t\tpregpriv->rx_stbc = extra_arg;\n\t\t\t\tRTW_INFO(\"set rx_stbc=%d\\n\", pregpriv->rx_stbc);\n\t\t\t} else\n\t\t\t\tRTW_INFO(\"get rx_stbc=%d\\n\", pregpriv->rx_stbc);\n\n\t\t}\n\t\t\tbreak;\n\t\tcase 0x13: { /* set ampdu_enable */\n\t\t\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\t\t\t/* 0: disable, 0x1:enable */\n\t\t\tif (pregpriv && extra_arg < 2) {\n\t\t\t\tpregpriv->ampdu_enable = extra_arg;\n\t\t\t\tRTW_INFO(\"set ampdu_enable=%d\\n\", pregpriv->ampdu_enable);\n\t\t\t} else\n\t\t\t\tRTW_INFO(\"get ampdu_enable=%d\\n\", pregpriv->ampdu_enable);\n\n\t\t}\n\t\t\tbreak;\n#endif\n\t\tcase 0x14: { /* get wifi_spec */\n\t\t\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\t\t\tRTW_INFO(\"get wifi_spec=%d\\n\", pregpriv->wifi_spec);\n\n\t\t}\n\t\t\tbreak;\n\n#ifdef DBG_FIXED_CHAN\n\t\tcase 0x17: {\n\t\t\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\t\t\tprintk(\"===>  Fixed channel to %d\\n\", extra_arg);\n\t\t\tpmlmeext->fixed_chan = extra_arg;\n\n\t\t}\n\t\t\tbreak;\n#endif\n#ifdef CONFIG_80211N_HT\n\t\tcase 0x19: {\n\t\t\tstruct registry_priv\t*pregistrypriv = &padapter->registrypriv;\n\t\t\t/* extra_arg : */\n\t\t\t/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, */\n\t\t\t/* BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */\n\t\t\tif (arg == 0) {\n\t\t\t\tRTW_INFO(\"driver disable LDPC\\n\");\n\t\t\t\tpregistrypriv->ldpc_cap = 0x00;\n\t\t\t} else if (arg == 1) {\n\t\t\t\tRTW_INFO(\"driver set LDPC cap = 0x%x\\n\", extra_arg);\n\t\t\t\tpregistrypriv->ldpc_cap = (u8)(extra_arg & 0x33);\n\t\t\t}\n\t\t}\n\t\t\tbreak;\n\t\tcase 0x1a: {\n\t\t\tstruct registry_priv\t*pregistrypriv = &padapter->registrypriv;\n\t\t\t/* extra_arg : */\n\t\t\t/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, */\n\t\t\t/* BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */\n\t\t\tif (arg == 0) {\n\t\t\t\tRTW_INFO(\"driver disable STBC\\n\");\n\t\t\t\tpregistrypriv->stbc_cap = 0x00;\n\t\t\t} else if (arg == 1) {\n\t\t\t\tRTW_INFO(\"driver set STBC cap = 0x%x\\n\", extra_arg);\n\t\t\t\tpregistrypriv->stbc_cap = (u8)(extra_arg & 0x33);\n\t\t\t}\n\t\t}\n\t\t\tbreak;\n#endif /* CONFIG_80211N_HT */\n\t\tcase 0x1b: {\n\t\t\tstruct registry_priv\t*pregistrypriv = &padapter->registrypriv;\n\n\t\t\tif (arg == 0) {\n\t\t\t\tRTW_INFO(\"disable driver ctrl max_rx_rate, reset to default_rate_set\\n\");\n\t\t\t\tinit_mlme_default_rate_set(padapter);\n#ifdef CONFIG_80211N_HT\n\t\t\t\tpregistrypriv->ht_enable = (u8)rtw_ht_enable;\n#endif /* CONFIG_80211N_HT */\n\t\t\t} else if (arg == 1) {\n\n\t\t\t\tint i;\n\t\t\t\tu8 max_rx_rate;\n\n\t\t\t\tRTW_INFO(\"enable driver ctrl max_rx_rate = 0x%x\\n\", extra_arg);\n\n\t\t\t\tmax_rx_rate = (u8)extra_arg;\n\n\t\t\t\tif (max_rx_rate < 0xc) { /* max_rx_rate < MSC0->B or G -> disable HT */\n#ifdef CONFIG_80211N_HT\n\t\t\t\t\tpregistrypriv->ht_enable = 0;\n#endif /* CONFIG_80211N_HT */\n\t\t\t\t\tfor (i = 0; i < NumRates; i++) {\n\t\t\t\t\t\tif (pmlmeext->datarate[i] > max_rx_rate)\n\t\t\t\t\t\t\tpmlmeext->datarate[i] = 0xff;\n\t\t\t\t\t}\n\n\t\t\t\t}\n#ifdef CONFIG_80211N_HT\n\t\t\t\telse if (max_rx_rate < 0x1c) { /* mcs0~mcs15 */\n\t\t\t\t\tu32 mcs_bitmap = 0x0;\n\n\t\t\t\t\tfor (i = 0; i < ((max_rx_rate + 1) - 0xc); i++)\n\t\t\t\t\t\tmcs_bitmap |= BIT(i);\n\n\t\t\t\t\tset_mcs_rate_by_mask(pmlmeext->default_supported_mcs_set, mcs_bitmap);\n\t\t\t\t}\n#endif /* CONFIG_80211N_HT\t\t\t\t\t\t\t */\n\t\t\t}\n\t\t}\n\t\t\tbreak;\n\t\tcase 0x1c: { /* enable/disable driver control AMPDU Density for peer sta's rx */\n\t\t\tif (arg == 0) {\n\t\t\t\tRTW_INFO(\"disable driver ctrl ampdu density\\n\");\n\t\t\t\tpadapter->driver_ampdu_spacing = 0xFF;\n\t\t\t} else if (arg == 1) {\n\n\t\t\t\tRTW_INFO(\"enable driver ctrl ampdu density = %d\\n\", extra_arg);\n\n\t\t\t\tif (extra_arg > 0x07)\n\t\t\t\t\tpadapter->driver_ampdu_spacing = 0xFF;\n\t\t\t\telse\n\t\t\t\t\tpadapter->driver_ampdu_spacing = extra_arg;\n\t\t\t}\n\t\t}\n\t\t\tbreak;\n#ifdef CONFIG_BACKGROUND_NOISE_MONITOR\n\t\tcase 0x1e: {\n\t\t\tRTW_INFO(\"===========================================\\n\");\n\t\t\trtw_noise_measure_curchan(padapter);\n\t\t\tRTW_INFO(\"===========================================\\n\");\n\t\t}\n\t\t\tbreak;\n#endif\n\n\n#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_SDIO_INDIRECT_ACCESS) && defined(DBG_SDIO_INDIRECT_ACCESS)\n\t\tcase 0x1f:\n\t\t\t{\n\t\t\t\tint i, j = 0, test_cnts = 0;\n\t\t\t\tstatic u8 test_code = 0x5A;\n\t\t\t\tstatic u32 data_misatch_cnt = 0, d_acc_err_cnt = 0;\n\n\t\t\t\tu32 d_data, i_data;\n\t\t\t\tu32 imr;\n\n\t\t\t\ttest_cnts = extra_arg;\n\t\t\t\tfor (i = 0; i < test_cnts; i++) {\n\t\t\t\t\tif (RTW_CANNOT_IO(padapter))\n\t\t\t\t\t\tbreak;\n\n\t\t\t\t\trtw_write8(padapter, 0x07, test_code);\n\n\t\t\t\t\td_data = rtw_read32(padapter, 0x04);\n\t\t\t\t\timr =  rtw_read32(padapter, 0x10250014);\n\t\t\t\t\trtw_write32(padapter, 0x10250014, 0);\n\t\t\t\t\trtw_msleep_os(50);\n\n\t\t\t\t\ti_data = rtw_sd_iread32(padapter, 0x04);\n\n\t\t\t\t\trtw_write32(padapter, 0x10250014, imr);\n\n\t\t\t\t\tif (d_data != i_data) {\n\t\t\t\t\t\tdata_misatch_cnt++;\n\t\t\t\t\t\tRTW_ERR(\"d_data :0x%08x, i_data : 0x%08x\\n\", d_data, i_data);\n\t\t\t\t\t}\n\n\t\t\t\t\tif (test_code != (i_data >> 24)) {\n\t\t\t\t\t\td_acc_err_cnt++;\n\t\t\t\t\t\trtw_write8(padapter, 0x07, 0xAA);\n\t\t\t\t\t\tRTW_ERR(\"test_code :0x%02x, i_data : 0x%08x\\n\", test_code, i_data);\n\t\t\t\t\t}\n\t\t\t\t\tif ((j++) == 100) {\n\t\t\t\t\t\trtw_msleep_os(2000);\n\t\t\t\t\t\tRTW_INFO(\" Indirect access testing..........%d/%d\\n\", i, test_cnts);\n\t\t\t\t\t\tj = 0;\n\t\t\t\t\t}\n\n\t\t\t\t\ttest_code = ~test_code;\n\t\t\t\t\trtw_msleep_os(50);\n\t\t\t\t}\n\t\t\t\tRTW_INFO(\"========Indirect access test=========\\n\");\n\t\t\t\tRTW_INFO(\" test_cnts = %d\\n\", test_cnts);\n\t\t\t\tRTW_INFO(\" direct & indirect read32 data missatch cnts = %d\\n\", data_misatch_cnt);\n\t\t\t\tRTW_INFO(\" indirect rdata is not equal to wdata cnts = %d\\n\", d_acc_err_cnt);\n\t\t\t\tRTW_INFO(\"========Indirect access test=========\\n\\n\");\n\t\t\t\tdata_misatch_cnt = d_acc_err_cnt = 0;\n\n\t\t\t}\n\t\t\tbreak;\n#endif\n\t\tcase 0x20:\n\t\t\t{\n\t\t\t\tif (arg == 0xAA) {\n\t\t\t\t\tu8 page_offset, page_num;\n\n\t\t\t\t\tpage_offset = (u8)(extra_arg >> 16);\n\t\t\t\t\tpage_num = (u8)(extra_arg & 0xFF);\n\t\t\t\t\trtw_dump_rsvd_page(RTW_DBGDUMP, padapter, page_offset, page_num);\n\t\t\t\t}\n#ifdef CONFIG_SUPPORT_FIFO_DUMP\n\t\t\t\telse {\n\t\t\t\t\tu8 fifo_sel;\n\t\t\t\t\tu32 addr, size;\n\n\t\t\t\t\tfifo_sel = (u8)(arg & 0x0F);\n\t\t\t\t\taddr = (extra_arg >> 16) & 0xFFFF;\n\t\t\t\t\tsize = extra_arg & 0xFFFF;\n\t\t\t\t\trtw_dump_fifo(RTW_DBGDUMP, padapter, fifo_sel, addr, size);\n\t\t\t\t}\n#endif\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase 0x23: {\n\t\t\tRTW_INFO(\"turn %s the bNotifyChannelChange Variable\\n\", (extra_arg == 1) ? \"on\" : \"off\");\n\t\t\tpadapter->bNotifyChannelChange = extra_arg;\n\t\t\tbreak;\n\t\t}\n\t\tcase 0x24: {\n#ifdef CONFIG_P2P\n\t\t\tRTW_INFO(\"turn %s the bShowGetP2PState Variable\\n\", (extra_arg == 1) ? \"on\" : \"off\");\n\t\t\tpadapter->bShowGetP2PState = extra_arg;\n#endif /* CONFIG_P2P */\n\t\t\tbreak;\n\t\t}\n#ifdef CONFIG_GPIO_API\n\t\tcase 0x25: { /* Get GPIO register */\n\t\t\t/*\n\t\t\t* dbg 0x7f250000 [gpio_num], Get gpio value, gpio_num:0~7\n\t\t\t*/\n\n\t\t\tu8 value;\n\t\t\tRTW_INFO(\"Read GPIO Value  extra_arg = %d\\n\", extra_arg);\n\t\t\tvalue = rtw_hal_get_gpio(padapter, extra_arg);\n\t\t\tRTW_INFO(\"Read GPIO Value = %d\\n\", value);\n\t\t\tbreak;\n\t\t}\n\t\tcase 0x26: { /* Set GPIO direction */\n\n\t\t\t/* dbg 0x7f26000x [y], Set gpio direction,\n\t\t\t* x: gpio_num,4~7  y: indicate direction, 0~1\n\t\t\t*/\n\n\t\t\tint value;\n\t\t\tRTW_INFO(\"Set GPIO Direction! arg = %d ,extra_arg=%d\\n\", arg , extra_arg);\n\t\t\tvalue = rtw_hal_config_gpio(padapter, arg, extra_arg);\n\t\t\tRTW_INFO(\"Set GPIO Direction %s\\n\", (value == -1) ? \"Fail!!!\" : \"Success\");\n\t\t\tbreak;\n\t\t}\n\t\tcase 0x27: { /* Set GPIO output direction value */\n\t\t\t/*\n\t\t\t* dbg 0x7f27000x [y], Set gpio output direction value,\n\t\t\t* x: gpio_num,4~7  y: indicate direction, 0~1\n\t\t\t*/\n\n\t\t\tint value;\n\t\t\tRTW_INFO(\"Set GPIO Value! arg = %d ,extra_arg=%d\\n\", arg , extra_arg);\n\t\t\tvalue = rtw_hal_set_gpio_output_value(padapter, arg, extra_arg);\n\t\t\tRTW_INFO(\"Set GPIO Value %s\\n\", (value == -1) ? \"Fail!!!\" : \"Success\");\n\t\t\tbreak;\n\t\t}\n#endif\n#ifdef DBG_CMD_QUEUE\n\t\tcase 0x28: {\n\t\t\tdump_cmd_id = extra_arg;\n\t\t\tRTW_INFO(\"dump_cmd_id:%d\\n\", dump_cmd_id);\n\t\t}\n\t\t\tbreak;\n#endif /* DBG_CMD_QUEUE */\n\t\tcase 0xaa: {\n\t\t\tif ((extra_arg & 0x7F) > 0x3F)\n\t\t\t\textra_arg = 0xFF;\n\t\t\tRTW_INFO(\"chang data rate to :0x%02x\\n\", extra_arg);\n\t\t\tpadapter->fix_rate = extra_arg;\n\t\t}\n\t\t\tbreak;\n\t\tcase 0xdd: { /* registers dump , 0 for mac reg,1 for bb reg, 2 for rf reg */\n\t\t\tif (extra_arg == 0)\n\t\t\t\tmac_reg_dump(RTW_DBGDUMP, padapter);\n\t\t\telse if (extra_arg == 1)\n\t\t\t\tbb_reg_dump(RTW_DBGDUMP, padapter);\n\t\t\telse if (extra_arg == 2)\n\t\t\t\trf_reg_dump(RTW_DBGDUMP, padapter);\n\t\t\telse if (extra_arg == 11)\n\t\t\t\tbb_reg_dump_ex(RTW_DBGDUMP, padapter);\n\t\t}\n\t\t\tbreak;\n\n\t\tcase 0xee: {\n\t\t\tRTW_INFO(\" === please control /proc  to trun on/off PHYDM func ===\\n\");\n\t\t}\n\t\t\tbreak;\n\n\t\tcase 0xfd:\n\t\t\trtw_write8(padapter, 0xc50, arg);\n\t\t\tRTW_INFO(\"wr(0xc50)=0x%x\\n\", rtw_read8(padapter, 0xc50));\n\t\t\trtw_write8(padapter, 0xc58, arg);\n\t\t\tRTW_INFO(\"wr(0xc58)=0x%x\\n\", rtw_read8(padapter, 0xc58));\n\t\t\tbreak;\n\t\tcase 0xfe:\n\t\t\tRTW_INFO(\"rd(0xc50)=0x%x\\n\", rtw_read8(padapter, 0xc50));\n\t\t\tRTW_INFO(\"rd(0xc58)=0x%x\\n\", rtw_read8(padapter, 0xc58));\n\t\t\tbreak;\n\t\tcase 0xff: {\n\t\t\tRTW_INFO(\"dbg(0x210)=0x%x\\n\", rtw_read32(padapter, 0x210));\n\t\t\tRTW_INFO(\"dbg(0x608)=0x%x\\n\", rtw_read32(padapter, 0x608));\n\t\t\tRTW_INFO(\"dbg(0x280)=0x%x\\n\", rtw_read32(padapter, 0x280));\n\t\t\tRTW_INFO(\"dbg(0x284)=0x%x\\n\", rtw_read32(padapter, 0x284));\n\t\t\tRTW_INFO(\"dbg(0x288)=0x%x\\n\", rtw_read32(padapter, 0x288));\n\n\t\t\tRTW_INFO(\"dbg(0x664)=0x%x\\n\", rtw_read32(padapter, 0x664));\n\n\n\t\t\tRTW_INFO(\"\\n\");\n\n\t\t\tRTW_INFO(\"dbg(0x430)=0x%x\\n\", rtw_read32(padapter, 0x430));\n\t\t\tRTW_INFO(\"dbg(0x438)=0x%x\\n\", rtw_read32(padapter, 0x438));\n\n\t\t\tRTW_INFO(\"dbg(0x440)=0x%x\\n\", rtw_read32(padapter, 0x440));\n\n\t\t\tRTW_INFO(\"dbg(0x458)=0x%x\\n\", rtw_read32(padapter, 0x458));\n\n\t\t\tRTW_INFO(\"dbg(0x484)=0x%x\\n\", rtw_read32(padapter, 0x484));\n\t\t\tRTW_INFO(\"dbg(0x488)=0x%x\\n\", rtw_read32(padapter, 0x488));\n\n\t\t\tRTW_INFO(\"dbg(0x444)=0x%x\\n\", rtw_read32(padapter, 0x444));\n\t\t\tRTW_INFO(\"dbg(0x448)=0x%x\\n\", rtw_read32(padapter, 0x448));\n\t\t\tRTW_INFO(\"dbg(0x44c)=0x%x\\n\", rtw_read32(padapter, 0x44c));\n\t\t\tRTW_INFO(\"dbg(0x450)=0x%x\\n\", rtw_read32(padapter, 0x450));\n\t\t}\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tRTW_INFO(\"error dbg cmd!\\n\");\n\t\tbreak;\n\t}\n\n\n\treturn ret;\n\n}\n\nstatic int wpa_set_param(struct net_device *dev, u8 name, u32 value)\n{\n\tuint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tswitch (name) {\n\tcase IEEE_PARAM_WPA_ENABLED:\n\n\t\tpadapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; /* 802.1x */\n\n\t\t/* ret = ieee80211_wpa_enable(ieee, value); */\n\n\t\tswitch ((value) & 0xff) {\n\t\tcase 1: /* WPA */\n\t\t\tpadapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK; /* WPA_PSK */\n\t\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;\n\t\t\tbreak;\n\t\tcase 2: /* WPA2 */\n\t\t\tpadapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK; /* WPA2_PSK */\n\t\t\tpadapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;\n\t\t\tbreak;\n\t\t}\n\n\n\t\tbreak;\n\n\tcase IEEE_PARAM_TKIP_COUNTERMEASURES:\n\t\t/* ieee->tkip_countermeasures=value; */\n\t\tbreak;\n\n\tcase IEEE_PARAM_DROP_UNENCRYPTED: {\n\t\t/* HACK:\n\t\t *\n\t\t * wpa_supplicant calls set_wpa_enabled when the driver\n\t\t * is loaded and unloaded, regardless of if WPA is being\n\t\t * used.  No other calls are made which can be used to\n\t\t * determine if encryption will be used or not prior to\n\t\t * association being expected.  If encryption is not being\n\t\t * used, drop_unencrypted is set to false, else true -- we\n\t\t * can use this to determine if the CAP_PRIVACY_ON bit should\n\t\t * be set.\n\t\t */\n\n#if 0\n\t\tstruct ieee80211_security sec = {\n\t\t\t.flags = SEC_ENABLED,\n\t\t\t.enabled = value,\n\t\t};\n\t\tieee->drop_unencrypted = value;\n\t\t/* We only change SEC_LEVEL for open mode. Others\n\t\t * are set by ipw_wpa_set_encryption.\n\t\t */\n\t\tif (!value) {\n\t\t\tsec.flags |= SEC_LEVEL;\n\t\t\tsec.level = SEC_LEVEL_0;\n\t\t} else {\n\t\t\tsec.flags |= SEC_LEVEL;\n\t\t\tsec.level = SEC_LEVEL_1;\n\t\t}\n\t\tif (ieee->set_security)\n\t\t\tieee->set_security(ieee->dev, &sec);\n#endif\n\t\tbreak;\n\n\t}\n\tcase IEEE_PARAM_PRIVACY_INVOKED:\n\n\t\t/* ieee->privacy_invoked=value; */\n\n\t\tbreak;\n\n\tcase IEEE_PARAM_AUTH_ALGS:\n\n\t\tret = wpa_set_auth_algs(dev, value);\n\n\t\tbreak;\n\n\tcase IEEE_PARAM_IEEE_802_1X:\n\n\t\t/* ieee->ieee802_1x=value;\t\t */\n\n\t\tbreak;\n\n\tcase IEEE_PARAM_WPAX_SELECT:\n\n\t\t/* added for WPA2 mixed mode */\n\t\t/*RTW_WARN(\"------------------------>wpax value = %x\\n\", value);*/\n\t\t/*\n\t\tspin_lock_irqsave(&ieee->wpax_suitlist_lock,flags);\n\t\tieee->wpax_type_set = 1;\n\t\tieee->wpax_type_notify = value;\n\t\tspin_unlock_irqrestore(&ieee->wpax_suitlist_lock,flags);\n\t\t*/\n\n\t\tbreak;\n\n\tdefault:\n\n\n\n\t\tret = -EOPNOTSUPP;\n\n\n\t\tbreak;\n\n\t}\n\n\treturn ret;\n\n}\n\nstatic int wpa_mlme(struct net_device *dev, u32 command, u32 reason)\n{\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tswitch (command) {\n\tcase IEEE_MLME_STA_DEAUTH:\n\n\t\tif (!rtw_set_802_11_disassociate(padapter))\n\t\t\tret = -1;\n\n\t\tbreak;\n\n\tcase IEEE_MLME_STA_DISASSOC:\n\n\t\tif (!rtw_set_802_11_disassociate(padapter))\n\t\t\tret = -1;\n\n\t\tbreak;\n\n\tdefault:\n\t\tret = -EOPNOTSUPP;\n\t\tbreak;\n\t}\n#ifdef CONFIG_RTW_REPEATER_SON\n\trtw_rson_do_disconnect(padapter);\n#endif\n\treturn ret;\n\n}\n\nstatic int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p)\n{\n\tstruct ieee_param *param;\n\tuint ret = 0;\n\n\t/* down(&ieee->wx_sem);\t */\n\n\tif (p->length < sizeof(struct ieee_param) || !p->pointer) {\n\t\tret = -EINVAL;\n\t\tgoto out;\n\t}\n\n\tparam = (struct ieee_param *)rtw_malloc(p->length);\n\tif (param == NULL) {\n\t\tret = -ENOMEM;\n\t\tgoto out;\n\t}\n\n\tif (copy_from_user(param, p->pointer, p->length)) {\n\t\trtw_mfree((u8 *)param, p->length);\n\t\tret = -EFAULT;\n\t\tgoto out;\n\t}\n\n\tswitch (param->cmd) {\n\n\tcase IEEE_CMD_SET_WPA_PARAM:\n\t\tret = wpa_set_param(dev, param->u.wpa_param.name, param->u.wpa_param.value);\n\t\tbreak;\n\n\tcase IEEE_CMD_SET_WPA_IE:\n\t\t/* ret = wpa_set_wpa_ie(dev, param, p->length); */\n\t\tret =  rtw_set_wpa_ie((_adapter *)rtw_netdev_priv(dev), (char *)param->u.wpa_ie.data, (u16)param->u.wpa_ie.len);\n\t\tbreak;\n\n\tcase IEEE_CMD_SET_ENCRYPTION:\n\t\tret = wpa_set_encryption(dev, param, p->length);\n\t\tbreak;\n\n\tcase IEEE_CMD_MLME:\n\t\tret = wpa_mlme(dev, param->u.mlme.command, param->u.mlme.reason_code);\n\t\tbreak;\n\n\tdefault:\n\t\tRTW_INFO(\"Unknown WPA supplicant request: %d\\n\", param->cmd);\n\t\tret = -EOPNOTSUPP;\n\t\tbreak;\n\n\t}\n\n\tif (ret == 0 && copy_to_user(p->pointer, param, p->length))\n\t\tret = -EFAULT;\n\n\trtw_mfree((u8 *)param, p->length);\n\nout:\n\n\t/* up(&ieee->wx_sem); */\n\n\treturn ret;\n\n}\n\n#ifdef CONFIG_AP_MODE\nstatic int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len)\n{\n\tint ret = 0;\n\tu32 wep_key_idx, wep_key_len, wep_total_len;\n\tNDIS_802_11_WEP\t*pwep = NULL;\n\tstruct sta_info *psta = NULL, *pbcmc_sta = NULL;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct security_priv *psecuritypriv = &(padapter->securitypriv);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\tparam->u.crypt.err = 0;\n\tparam->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\\0';\n\n\t/* sizeof(struct ieee_param) = 64 bytes; */\n\t/* if (param_len !=  (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) */\n\tif (param_len !=  sizeof(struct ieee_param) + param->u.crypt.key_len) {\n\t\tret =  -EINVAL;\n\t\tgoto exit;\n\t}\n\n\tif (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&\n\t    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&\n\t    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) {\n\t\tif (param->u.crypt.idx >= WEP_KEYS\n#ifdef CONFIG_IEEE80211W\n\t\t    && param->u.crypt.idx > BIP_MAX_KEYID\n#endif /* CONFIG_IEEE80211W */\n\t\t   ) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t} else {\n\t\tpsta = rtw_get_stainfo(pstapriv, param->sta_addr);\n\t\tif (!psta) {\n\t\t\t/* ret = -EINVAL; */\n\t\t\tRTW_INFO(\"rtw_set_encryption(), sta has already been removed or never been added\\n\");\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\tif (strcmp(param->u.crypt.alg, \"none\") == 0 && (psta == NULL)) {\n\t\t/* todo:clear default encryption keys */\n\n\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open;\n\t\tpsecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled;\n\t\tpsecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;\n\t\tpsecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;\n\n\t\tRTW_INFO(\"clear default encryption keys, keyid=%d\\n\", param->u.crypt.idx);\n\n\t\tgoto exit;\n\t}\n\n\n\tif (strcmp(param->u.crypt.alg, \"WEP\") == 0 && (psta == NULL)) {\n\t\tRTW_INFO(\"r871x_set_encryption, crypt.alg = WEP\\n\");\n\n\t\twep_key_idx = param->u.crypt.idx;\n\t\twep_key_len = param->u.crypt.key_len;\n\n\t\tRTW_INFO(\"r871x_set_encryption, wep_key_idx=%d, len=%d\\n\", wep_key_idx, wep_key_len);\n\n\t\tif ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\n\t\tif (wep_key_len > 0) {\n\t\t\twep_key_len = wep_key_len <= 5 ? 5 : 13;\n\t\t\twep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial);\n\t\t\tpwep = (NDIS_802_11_WEP *)rtw_malloc(wep_total_len);\n\t\t\tif (pwep == NULL) {\n\t\t\t\tRTW_INFO(\" r871x_set_encryption: pwep allocate fail !!!\\n\");\n\t\t\t\tgoto exit;\n\t\t\t}\n\n\t\t\t_rtw_memset(pwep, 0, wep_total_len);\n\n\t\t\tpwep->KeyLength = wep_key_len;\n\t\t\tpwep->Length = wep_total_len;\n\n\t\t}\n\n\t\tpwep->KeyIndex = wep_key_idx;\n\n\t\t_rtw_memcpy(pwep->KeyMaterial,  param->u.crypt.key, pwep->KeyLength);\n\n\t\tif (param->u.crypt.set_tx) {\n\t\t\tRTW_INFO(\"wep, set_tx=1\\n\");\n\n\t\t\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;\n\t\t\tpsecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;\n\t\t\tpsecuritypriv->dot11PrivacyAlgrthm = _WEP40_;\n\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _WEP40_;\n\n\t\t\tif (pwep->KeyLength == 13) {\n\t\t\t\tpsecuritypriv->dot11PrivacyAlgrthm = _WEP104_;\n\t\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _WEP104_;\n\t\t\t}\n\n\n\t\t\tpsecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;\n\n\t\t\t_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength);\n\n\t\t\tpsecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength;\n\n\t\t\trtw_ap_set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx, 1);\n\t\t} else {\n\t\t\tRTW_INFO(\"wep, set_tx=0\\n\");\n\n\t\t\t/* don't update \"psecuritypriv->dot11PrivacyAlgrthm\" and  */\n\t\t\t/* \"psecuritypriv->dot11PrivacyKeyIndex=keyid\", but can rtw_set_key to cam */\n\n\t\t\t_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength);\n\n\t\t\tpsecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength;\n\n\t\t\trtw_ap_set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx, 0);\n\t\t}\n\n\t\tgoto exit;\n\n\t}\n\n\n\tif (!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) /*  */ { /* group key */\n\t\tif (param->u.crypt.set_tx == 1) {\n\t\t\tif (strcmp(param->u.crypt.alg, \"WEP\") == 0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set WEP TX GTK idx:%u, len:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\t_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\t\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _WEP40_;\n\t\t\t\tif (param->u.crypt.key_len == 13)\n\t\t\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _WEP104_;\n\n\t\t\t} else if (strcmp(param->u.crypt.alg, \"TKIP\") == 0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set TKIP TX GTK idx:%u, len:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _TKIP_;\n\t\t\t\t_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\t\t\t\t/* set mic key */\n\t\t\t\t_rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);\n\t\t\t\t_rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);\n\t\t\t\tpsecuritypriv->busetkipkey = _TRUE;\n\n\t\t\t} else if (strcmp(param->u.crypt.alg, \"CCMP\") == 0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set CCMP TX GTK idx:%u, len:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _AES_;\n\t\t\t\t_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\n\t\t\t#ifdef CONFIG_IEEE80211W\n\t\t\t} else if (strcmp(param->u.crypt.alg, \"BIP\") == 0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set TX IGTK idx:%u, len:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\t_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\t\t\t\tpsecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;\n\t\t\t\tpsecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq);\n\t\t\t\tpsecuritypriv->binstallBIPkey = _TRUE;\n\t\t\t\tgoto exit;\n\t\t\t#endif /* CONFIG_IEEE80211W */\n\n\t\t\t} else if (strcmp(param->u.crypt.alg, \"none\") == 0) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" clear group key, idx:%u\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), param->u.crypt.idx);\n\t\t\t\tpsecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;\n\t\t\t} else {\n\t\t\t\tRTW_WARN(FUNC_ADPT_FMT\" set group key, not support\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter));\n\t\t\t\tgoto exit;\n\t\t\t}\n\n\t\t\tpsecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx;\n\t\t\tpbcmc_sta = rtw_get_bcmc_stainfo(padapter);\n\t\t\tif (pbcmc_sta) {\n\t\t\t\tpbcmc_sta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);\n\t\t\t\tpbcmc_sta->ieee8021x_blocked = _FALSE;\n\t\t\t\tpbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy\t\t\t */\n\t\t\t}\n\t\t\tpsecuritypriv->binstallGrpkey = _TRUE;\n\t\t\tpsecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */\n\n\t\t\trtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx);\n\t\t}\n\n\t\tgoto exit;\n\n\t}\n\n\tif (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) { /* psk/802_1x */\n\t\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {\n\t\t\tif (param->u.crypt.set_tx == 1) {\n\t\t\t\t_rtw_memcpy(psta->dot118021x_UncstKey.skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));\n\n\t\t\t\tif (strcmp(param->u.crypt.alg, \"WEP\") == 0) {\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set WEP PTK of \"MAC_FMT\" idx:%u, len:%u\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)\n\t\t\t\t\t\t, param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\t\tpsta->dot118021XPrivacy = _WEP40_;\n\t\t\t\t\tif (param->u.crypt.key_len == 13)\n\t\t\t\t\t\tpsta->dot118021XPrivacy = _WEP104_;\n\n\t\t\t\t} else if (strcmp(param->u.crypt.alg, \"TKIP\") == 0) {\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set TKIP PTK of \"MAC_FMT\" idx:%u, len:%u\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)\n\t\t\t\t\t\t, param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\t\tpsta->dot118021XPrivacy = _TKIP_;\n\t\t\t\t\t/* set mic key */\n\t\t\t\t\t_rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);\n\t\t\t\t\t_rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);\n\t\t\t\t\tpsecuritypriv->busetkipkey = _TRUE;\n\n\t\t\t\t} else if (strcmp(param->u.crypt.alg, \"CCMP\") == 0) {\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" set CCMP PTK of \"MAC_FMT\" idx:%u, len:%u\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)\n\t\t\t\t\t\t, param->u.crypt.idx, param->u.crypt.key_len);\n\t\t\t\t\tpsta->dot118021XPrivacy = _AES_;\n\n\t\t\t\t} else if (strcmp(param->u.crypt.alg, \"none\") == 0) {\n\t\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" clear pairwise key of \"MAC_FMT\" idx:%u\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)\n\t\t\t\t\t\t, param->u.crypt.idx);\n\t\t\t\t\tpsta->dot118021XPrivacy = _NO_PRIVACY_;\n\n\t\t\t\t} else {\n\t\t\t\t\tRTW_WARN(FUNC_ADPT_FMT\" set pairwise key of \"MAC_FMT\", not support\\n\"\n\t\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\n\t\t\t\tpsta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);\n\t\t\t\tpsta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq);\n\t\t\t\tpsta->ieee8021x_blocked = _FALSE;\n\n\t\t\t\tif (psta->dot118021XPrivacy != _NO_PRIVACY_) {\n\t\t\t\t\tpsta->bpairwise_key_installed = _TRUE;\n\n\t\t\t\t\t/* WPA2 key-handshake has completed */\n\t\t\t\t\tif (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK)\n\t\t\t\t\t\tpsta->state &= (~WIFI_UNDER_KEY_HANDSHAKE);\n\t\t\t\t}\n\n\t\t\t\trtw_ap_set_pairwise_key(padapter, psta);\n\t\t\t} else {\n\t\t\t\tRTW_WARN(FUNC_ADPT_FMT\" set group key of \"MAC_FMT\", not support\\n\"\n\t\t\t\t\t, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));\n\t\t\t\tgoto exit;\n\t\t\t}\n\n\t\t}\n\n\t}\n\nexit:\n\n\tif (pwep)\n\t\trtw_mfree((u8 *)pwep, wep_total_len);\n\n\treturn ret;\n\n}\n\nstatic int rtw_set_beacon(struct net_device *dev, struct ieee_param *param, int len)\n{\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tunsigned char *pbuf = param->u.bcn_ie.buf;\n\n\n\tRTW_INFO(\"%s, len=%d\\n\", __FUNCTION__, len);\n\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)\n\t\treturn -EINVAL;\n\n\t_rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2);\n\n\tif ((pstapriv->max_num_sta > NUM_STA) || (pstapriv->max_num_sta <= 0))\n\t\tpstapriv->max_num_sta = NUM_STA;\n\n\n\tif (rtw_check_beacon_data(padapter, pbuf, (len - 12 - 2)) == _SUCCESS) /* 12 = param header, 2:no packed */\n\t\tret = 0;\n\telse\n\t\tret = -EINVAL;\n\n\n\treturn ret;\n\n}\n\nstatic int rtw_hostapd_sta_flush(struct net_device *dev)\n{\n\t/* _irqL irqL; */\n\t/* _list\t*phead, *plist; */\n\tint ret = 0;\n\t/* struct sta_info *psta = NULL; */\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\t/* struct sta_priv *pstapriv = &padapter->stapriv; */\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\tflush_all_cam_entry(padapter);\t/* clear CAM */\n#ifdef CONFIG_AP_MODE\n\tret = rtw_sta_flush(padapter, _TRUE);\n#endif\n\treturn ret;\n\n}\n\nstatic int rtw_add_sta(struct net_device *dev, struct ieee_param *param)\n{\n\tint ret = 0;\n\tstruct sta_info *psta = NULL;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\tRTW_INFO(\"rtw_add_sta(aid=%d)=\" MAC_FMT \"\\n\", param->u.add_sta.aid, MAC_ARG(param->sta_addr));\n\n\tif (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE)) != _TRUE)\n\t\treturn -EINVAL;\n\n\tif (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&\n\t    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&\n\t    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)\n\t\treturn -EINVAL;\n\n#if 0\n\tpsta = rtw_get_stainfo(pstapriv, param->sta_addr);\n\tif (psta) {\n\t\tRTW_INFO(\"rtw_add_sta(), free has been added psta=%p\\n\", psta);\n\t\t/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\t\t */\n\t\trtw_free_stainfo(padapter,  psta);\n\t\t/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */\n\n\t\tpsta = NULL;\n\t}\n#endif\n\t/* psta = rtw_alloc_stainfo(pstapriv, param->sta_addr); */\n\tpsta = rtw_get_stainfo(pstapriv, param->sta_addr);\n\tif (psta) {\n\t\tint flags = param->u.add_sta.flags;\n\n\t\t/* RTW_INFO(\"rtw_add_sta(), init sta's variables, psta=%p\\n\", psta); */\n\n\t\tpsta->cmn.aid = param->u.add_sta.aid;/* aid=1~2007 */\n\n\t\t_rtw_memcpy(psta->bssrateset, param->u.add_sta.tx_supp_rates, 16);\n\n\n\t\t/* check wmm cap. */\n\t\tif (WLAN_STA_WME & flags)\n\t\t\tpsta->qos_option = 1;\n\t\telse\n\t\t\tpsta->qos_option = 0;\n\n\t\tif (pmlmepriv->qospriv.qos_option == 0)\n\t\t\tpsta->qos_option = 0;\n\n\n#ifdef CONFIG_80211N_HT\n\t\t/* chec 802.11n ht cap. */\n\t\tif (padapter->registrypriv.ht_enable &&\n\t\t\tis_supported_ht(padapter->registrypriv.wireless_mode) &&\n\t\t\t(WLAN_STA_HT & flags)) {\n\t\t\tpsta->htpriv.ht_option = _TRUE;\n\t\t\tpsta->qos_option = 1;\n\t\t\t_rtw_memcpy((void *)&psta->htpriv.ht_cap, (void *)&param->u.add_sta.ht_cap, sizeof(struct rtw_ieee80211_ht_cap));\n\t\t} else\n\t\t\tpsta->htpriv.ht_option = _FALSE;\n\n\t\tif (pmlmepriv->htpriv.ht_option == _FALSE)\n\t\t\tpsta->htpriv.ht_option = _FALSE;\n\n#endif\n\n\n\t\tupdate_sta_info_apmode(padapter, psta);\n\n\n\t} else\n\t\tret = -ENOMEM;\n\n\treturn ret;\n\n}\n\nstatic int rtw_del_sta(struct net_device *dev, struct ieee_param *param)\n{\n\t_irqL irqL;\n\tint ret = 0;\n\tstruct sta_info *psta = NULL;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\tRTW_INFO(\"rtw_del_sta=\" MAC_FMT \"\\n\", MAC_ARG(param->sta_addr));\n\n\tif (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE)) != _TRUE)\n\t\treturn -EINVAL;\n\n\tif (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&\n\t    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&\n\t    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)\n\t\treturn -EINVAL;\n\n\tpsta = rtw_get_stainfo(pstapriv, param->sta_addr);\n\tif (psta) {\n\t\tu8 updated = _FALSE;\n\n\t\t/* RTW_INFO(\"free psta=%p, aid=%d\\n\", psta, psta->cmn.aid); */\n\n\t\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\t\tif (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {\n\t\t\trtw_list_delete(&psta->asoc_list);\n\t\t\tpstapriv->asoc_list_cnt--;\n\t\t\tupdated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _TRUE);\n\n\t\t}\n\t\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\t\tassociated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);\n\n\t\tpsta = NULL;\n\n\t} else {\n\t\tRTW_INFO(\"rtw_del_sta(), sta has already been removed or never been added\\n\");\n\n\t\t/* ret = -1; */\n\t}\n\n\n\treturn ret;\n\n}\n\nstatic int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *param, int len)\n{\n\tint ret = 0;\n\tstruct sta_info *psta = NULL;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct ieee_param_ex *param_ex = (struct ieee_param_ex *)param;\n\tstruct sta_data *psta_data = (struct sta_data *)param_ex->data;\n\n\tRTW_INFO(\"rtw_ioctl_get_sta_info, sta_addr: \" MAC_FMT \"\\n\", MAC_ARG(param_ex->sta_addr));\n\n\tif (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE)) != _TRUE)\n\t\treturn -EINVAL;\n\n\tif (param_ex->sta_addr[0] == 0xff && param_ex->sta_addr[1] == 0xff &&\n\t    param_ex->sta_addr[2] == 0xff && param_ex->sta_addr[3] == 0xff &&\n\t    param_ex->sta_addr[4] == 0xff && param_ex->sta_addr[5] == 0xff)\n\t\treturn -EINVAL;\n\n\tpsta = rtw_get_stainfo(pstapriv, param_ex->sta_addr);\n\tif (psta) {\n#if 0\n\t\tstruct {\n\t\t\tu16 aid;\n\t\t\tu16 capability;\n\t\t\tint flags;\n\t\t\tu32 sta_set;\n\t\t\tu8 tx_supp_rates[16];\n\t\t\tu32 tx_supp_rates_len;\n\t\t\tstruct rtw_ieee80211_ht_cap ht_cap;\n\t\t\tu64\trx_pkts;\n\t\t\tu64\trx_bytes;\n\t\t\tu64\trx_drops;\n\t\t\tu64\ttx_pkts;\n\t\t\tu64\ttx_bytes;\n\t\t\tu64\ttx_drops;\n\t\t} get_sta;\n#endif\n\t\tpsta_data->aid = (u16)psta->cmn.aid;\n\t\tpsta_data->capability = psta->capability;\n\t\tpsta_data->flags = psta->flags;\n\n\t\t/*\n\t\t\t\tnonerp_set : BIT(0)\n\t\t\t\tno_short_slot_time_set : BIT(1)\n\t\t\t\tno_short_preamble_set : BIT(2)\n\t\t\t\tno_ht_gf_set : BIT(3)\n\t\t\t\tno_ht_set : BIT(4)\n\t\t\t\tht_20mhz_set : BIT(5)\n\t\t*/\n\n\t\tpsta_data->sta_set = ((psta->nonerp_set) |\n\t\t\t\t      (psta->no_short_slot_time_set << 1) |\n\t\t\t\t      (psta->no_short_preamble_set << 2) |\n\t\t\t\t      (psta->no_ht_gf_set << 3) |\n\t\t\t\t      (psta->no_ht_set << 4) |\n\t\t\t\t      (psta->ht_20mhz_set << 5));\n\n\t\tpsta_data->tx_supp_rates_len =  psta->bssratelen;\n\t\t_rtw_memcpy(psta_data->tx_supp_rates, psta->bssrateset, psta->bssratelen);\n#ifdef CONFIG_80211N_HT\n\t\tif(padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode))\n\t\t\t_rtw_memcpy(&psta_data->ht_cap, &psta->htpriv.ht_cap, sizeof(struct rtw_ieee80211_ht_cap));\n#endif /* CONFIG_80211N_HT */\n\t\tpsta_data->rx_pkts = psta->sta_stats.rx_data_pkts;\n\t\tpsta_data->rx_bytes = psta->sta_stats.rx_bytes;\n\t\tpsta_data->rx_drops = psta->sta_stats.rx_drops;\n\n\t\tpsta_data->tx_pkts = psta->sta_stats.tx_pkts;\n\t\tpsta_data->tx_bytes = psta->sta_stats.tx_bytes;\n\t\tpsta_data->tx_drops = psta->sta_stats.tx_drops;\n\n\n\t} else\n\t\tret = -1;\n\n\treturn ret;\n\n}\n\nstatic int rtw_get_sta_wpaie(struct net_device *dev, struct ieee_param *param)\n{\n\tint ret = 0;\n\tstruct sta_info *psta = NULL;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\tRTW_INFO(\"rtw_get_sta_wpaie, sta_addr: \" MAC_FMT \"\\n\", MAC_ARG(param->sta_addr));\n\n\tif (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE)) != _TRUE)\n\t\treturn -EINVAL;\n\n\tif (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&\n\t    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&\n\t    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)\n\t\treturn -EINVAL;\n\n\tpsta = rtw_get_stainfo(pstapriv, param->sta_addr);\n\tif (psta) {\n\t\tif ((psta->wpa_ie[0] == WLAN_EID_RSN) || (psta->wpa_ie[0] == WLAN_EID_GENERIC)) {\n\t\t\tint wpa_ie_len;\n\t\t\tint copy_len;\n\n\t\t\twpa_ie_len = psta->wpa_ie[1];\n\n\t\t\tcopy_len = ((wpa_ie_len + 2) > sizeof(psta->wpa_ie)) ? (sizeof(psta->wpa_ie)) : (wpa_ie_len + 2);\n\n\t\t\tparam->u.wpa_ie.len = copy_len;\n\n\t\t\t_rtw_memcpy(param->u.wpa_ie.reserved, psta->wpa_ie, copy_len);\n\t\t} else {\n\t\t\t/* ret = -1; */\n\t\t\tRTW_INFO(\"sta's wpa_ie is NONE\\n\");\n\t\t}\n\t} else\n\t\tret = -1;\n\n\treturn ret;\n\n}\n\nstatic int rtw_set_wps_beacon(struct net_device *dev, struct ieee_param *param, int len)\n{\n\tint ret = 0;\n\tunsigned char wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct mlme_ext_priv\t*pmlmeext = &(padapter->mlmeextpriv);\n\tint ie_len;\n\n\tRTW_INFO(\"%s, len=%d\\n\", __FUNCTION__, len);\n\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)\n\t\treturn -EINVAL;\n\n\tie_len = len - 12 - 2; /* 12 = param header, 2:no packed */\n\n\n\tif (pmlmepriv->wps_beacon_ie) {\n\t\trtw_mfree(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len);\n\t\tpmlmepriv->wps_beacon_ie = NULL;\n\t}\n\n\tif (ie_len > 0) {\n\t\tpmlmepriv->wps_beacon_ie = rtw_malloc(ie_len);\n\t\tpmlmepriv->wps_beacon_ie_len = ie_len;\n\t\tif (pmlmepriv->wps_beacon_ie == NULL) {\n\t\t\tRTW_INFO(\"%s()-%d: rtw_malloc() ERROR!\\n\", __FUNCTION__, __LINE__);\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\t_rtw_memcpy(pmlmepriv->wps_beacon_ie, param->u.bcn_ie.buf, ie_len);\n\n\t\tupdate_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE, 0);\n\n\t\tpmlmeext->bstart_bss = _TRUE;\n\n\t}\n\n\n\treturn ret;\n\n}\n\nstatic int rtw_set_wps_probe_resp(struct net_device *dev, struct ieee_param *param, int len)\n{\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tint ie_len;\n\n\tRTW_INFO(\"%s, len=%d\\n\", __FUNCTION__, len);\n\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)\n\t\treturn -EINVAL;\n\n\tie_len = len - 12 - 2; /* 12 = param header, 2:no packed */\n\n\n\tif (pmlmepriv->wps_probe_resp_ie) {\n\t\trtw_mfree(pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len);\n\t\tpmlmepriv->wps_probe_resp_ie = NULL;\n\t}\n\n\tif (ie_len > 0) {\n\t\tpmlmepriv->wps_probe_resp_ie = rtw_malloc(ie_len);\n\t\tpmlmepriv->wps_probe_resp_ie_len = ie_len;\n\t\tif (pmlmepriv->wps_probe_resp_ie == NULL) {\n\t\t\tRTW_INFO(\"%s()-%d: rtw_malloc() ERROR!\\n\", __FUNCTION__, __LINE__);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\t_rtw_memcpy(pmlmepriv->wps_probe_resp_ie, param->u.bcn_ie.buf, ie_len);\n\t}\n\n\n\treturn ret;\n\n}\n\nstatic int rtw_set_wps_assoc_resp(struct net_device *dev, struct ieee_param *param, int len)\n{\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tint ie_len;\n\n\tRTW_INFO(\"%s, len=%d\\n\", __FUNCTION__, len);\n\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)\n\t\treturn -EINVAL;\n\n\tie_len = len - 12 - 2; /* 12 = param header, 2:no packed */\n\n\n\tif (pmlmepriv->wps_assoc_resp_ie) {\n\t\trtw_mfree(pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len);\n\t\tpmlmepriv->wps_assoc_resp_ie = NULL;\n\t}\n\n\tif (ie_len > 0) {\n\t\tpmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len);\n\t\tpmlmepriv->wps_assoc_resp_ie_len = ie_len;\n\t\tif (pmlmepriv->wps_assoc_resp_ie == NULL) {\n\t\t\tRTW_INFO(\"%s()-%d: rtw_malloc() ERROR!\\n\", __FUNCTION__, __LINE__);\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\t_rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, param->u.bcn_ie.buf, ie_len);\n\t}\n\n\n\treturn ret;\n\n}\n\nstatic int rtw_set_hidden_ssid(struct net_device *dev, struct ieee_param *param, int len)\n{\n\tint ret = 0;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *mlmepriv = &(adapter->mlmepriv);\n\tstruct mlme_ext_priv\t*mlmeext = &(adapter->mlmeextpriv);\n\tstruct mlme_ext_info\t*mlmeinfo = &(mlmeext->mlmext_info);\n\tint ie_len;\n\tu8 *ssid_ie;\n\tchar ssid[NDIS_802_11_LENGTH_SSID + 1];\n\tsint ssid_len = 0;\n\tu8 ignore_broadcast_ssid;\n\n\tif (check_fwstate(mlmepriv, WIFI_AP_STATE) != _TRUE)\n\t\treturn -EPERM;\n\n\tif (param->u.bcn_ie.reserved[0] != 0xea)\n\t\treturn -EINVAL;\n\n\tmlmeinfo->hidden_ssid_mode = ignore_broadcast_ssid = param->u.bcn_ie.reserved[1];\n\n\tie_len = len - 12 - 2; /* 12 = param header, 2:no packed */\n\tssid_ie = rtw_get_ie(param->u.bcn_ie.buf,  WLAN_EID_SSID, &ssid_len, ie_len);\n\n\tif (ssid_ie && ssid_len > 0 && ssid_len <= NDIS_802_11_LENGTH_SSID) {\n\t\tWLAN_BSSID_EX *pbss_network = &mlmepriv->cur_network.network;\n\t\tWLAN_BSSID_EX *pbss_network_ext = &mlmeinfo->network;\n\n\t\t_rtw_memcpy(ssid, ssid_ie + 2, ssid_len);\n\t\tssid[ssid_len] = 0x0;\n\n\t\tif (0)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" ssid:(%s,%d), from ie:(%s,%d), (%s,%d)\\n\", FUNC_ADPT_ARG(adapter),\n\t\t\t\tssid, ssid_len,\n\t\t\t\tpbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength,\n\t\t\t\tpbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength);\n\n\t\t_rtw_memcpy(pbss_network->Ssid.Ssid, (void *)ssid, ssid_len);\n\t\tpbss_network->Ssid.SsidLength = ssid_len;\n\t\t_rtw_memcpy(pbss_network_ext->Ssid.Ssid, (void *)ssid, ssid_len);\n\t\tpbss_network_ext->Ssid.SsidLength = ssid_len;\n\n\t\tif (0)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" after ssid:(%s,%d), (%s,%d)\\n\", FUNC_ADPT_ARG(adapter),\n\t\t\t\tpbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength,\n\t\t\t\tpbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength);\n\t}\n\n\tRTW_INFO(FUNC_ADPT_FMT\" ignore_broadcast_ssid:%d, %s,%d\\n\", FUNC_ADPT_ARG(adapter),\n\t\tignore_broadcast_ssid, ssid, ssid_len);\n\n\treturn ret;\n}\n\n#if CONFIG_RTW_MACADDR_ACL\nstatic int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *param, int len)\n{\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)\n\t\treturn -EINVAL;\n\n\tif (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&\n\t    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&\n\t    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)\n\t\treturn -EINVAL;\n\n\tret = rtw_acl_remove_sta(padapter, RTW_ACL_PERIOD_BSS, param->sta_addr);\n\n\treturn ret;\n\n}\n\nstatic int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *param, int len)\n{\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)\n\t\treturn -EINVAL;\n\n\tif (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&\n\t    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&\n\t    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)\n\t\treturn -EINVAL;\n\n\tret = rtw_acl_add_sta(padapter, RTW_ACL_PERIOD_BSS, param->sta_addr);\n\n\treturn ret;\n\n}\n\nstatic int rtw_ioctl_set_macaddr_acl(struct net_device *dev, struct ieee_param *param, int len)\n{\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\n\tif (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)\n\t\treturn -EINVAL;\n\n\trtw_set_macaddr_acl(padapter, RTW_ACL_PERIOD_BSS, param->u.mlme.command);\n\n\treturn ret;\n}\n#endif /* CONFIG_RTW_MACADDR_ACL */\n\nstatic int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p)\n{\n\tstruct ieee_param *param;\n\tint ret = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\t/* RTW_INFO(\"%s\\n\", __FUNCTION__); */\n\n\t/*\n\t* this function is expect to call in master mode, which allows no power saving\n\t* so, we just check hw_init_completed\n\t*/\n\n\tif (!rtw_is_hw_init_completed(padapter)) {\n\t\tret = -EPERM;\n\t\tgoto out;\n\t}\n\n\n\t/* if (p->length < sizeof(struct ieee_param) || !p->pointer){ */\n\tif (!p->pointer) {\n\t\tret = -EINVAL;\n\t\tgoto out;\n\t}\n\n\tparam = (struct ieee_param *)rtw_malloc(p->length);\n\tif (param == NULL) {\n\t\tret = -ENOMEM;\n\t\tgoto out;\n\t}\n\n\tif (copy_from_user(param, p->pointer, p->length)) {\n\t\trtw_mfree((u8 *)param, p->length);\n\t\tret = -EFAULT;\n\t\tgoto out;\n\t}\n\n\t/* RTW_INFO(\"%s, cmd=%d\\n\", __FUNCTION__, param->cmd); */\n\n\tswitch (param->cmd) {\n\tcase RTL871X_HOSTAPD_FLUSH:\n\n\t\tret = rtw_hostapd_sta_flush(dev);\n\n\t\tbreak;\n\n\tcase RTL871X_HOSTAPD_ADD_STA:\n\n\t\tret = rtw_add_sta(dev, param);\n\n\t\tbreak;\n\n\tcase RTL871X_HOSTAPD_REMOVE_STA:\n\n\t\tret = rtw_del_sta(dev, param);\n\n\t\tbreak;\n\n\tcase RTL871X_HOSTAPD_SET_BEACON:\n\n\t\tret = rtw_set_beacon(dev, param, p->length);\n\n\t\tbreak;\n\n\tcase RTL871X_SET_ENCRYPTION:\n\n\t\tret = rtw_set_encryption(dev, param, p->length);\n\n\t\tbreak;\n\n\tcase RTL871X_HOSTAPD_GET_WPAIE_STA:\n\n\t\tret = rtw_get_sta_wpaie(dev, param);\n\n\t\tbreak;\n\n\tcase RTL871X_HOSTAPD_SET_WPS_BEACON:\n\n\t\tret = rtw_set_wps_beacon(dev, param, p->length);\n\n\t\tbreak;\n\n\tcase RTL871X_HOSTAPD_SET_WPS_PROBE_RESP:\n\n\t\tret = rtw_set_wps_probe_resp(dev, param, p->length);\n\n\t\tbreak;\n\n\tcase RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP:\n\n\t\tret = rtw_set_wps_assoc_resp(dev, param, p->length);\n\n\t\tbreak;\n\n\tcase RTL871X_HOSTAPD_SET_HIDDEN_SSID:\n\n\t\tret = rtw_set_hidden_ssid(dev, param, p->length);\n\n\t\tbreak;\n\n\tcase RTL871X_HOSTAPD_GET_INFO_STA:\n\n\t\tret = rtw_ioctl_get_sta_data(dev, param, p->length);\n\n\t\tbreak;\n\n#if CONFIG_RTW_MACADDR_ACL\n\tcase RTL871X_HOSTAPD_SET_MACADDR_ACL:\n\t\tret = rtw_ioctl_set_macaddr_acl(dev, param, p->length);\n\t\tbreak;\n\tcase RTL871X_HOSTAPD_ACL_ADD_STA:\n\t\tret = rtw_ioctl_acl_add_sta(dev, param, p->length);\n\t\tbreak;\n\tcase RTL871X_HOSTAPD_ACL_REMOVE_STA:\n\t\tret = rtw_ioctl_acl_remove_sta(dev, param, p->length);\n\t\tbreak;\n#endif /* CONFIG_RTW_MACADDR_ACL */\n\n\tdefault:\n\t\tRTW_INFO(\"Unknown hostapd request: %d\\n\", param->cmd);\n\t\tret = -EOPNOTSUPP;\n\t\tbreak;\n\n\t}\n\n\tif (ret == 0 && copy_to_user(p->pointer, param, p->length))\n\t\tret = -EFAULT;\n\n\n\trtw_mfree((u8 *)param, p->length);\n\nout:\n\n\treturn ret;\n\n}\n#endif\n\nstatic int rtw_wx_set_priv(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *awrq,\n\t\t\t   char *extra)\n{\n\n#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV\n\tchar *ext_dbg;\n#endif\n\n\tint ret = 0;\n\tint len = 0;\n\tchar *ext;\n#ifdef CONFIG_ANDROID\n\tint i;\n#endif\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct iw_point *dwrq = (struct iw_point *)awrq;\n\n\tif (dwrq->length == 0)\n\t\treturn -EFAULT;\n\n\tlen = dwrq->length;\n\text = rtw_vmalloc(len);\n\tif (!ext)\n\t\treturn -ENOMEM;\n\n\tif (copy_from_user(ext, dwrq->pointer, len)) {\n\t\trtw_vmfree(ext, len);\n\t\treturn -EFAULT;\n\t}\n\n\n\n#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV\n\text_dbg = rtw_vmalloc(len);\n\tif (!ext_dbg) {\n\t\trtw_vmfree(ext, len);\n\t\treturn -ENOMEM;\n\t}\n\n\t_rtw_memcpy(ext_dbg, ext, len);\n#endif\n\n\t/* added for wps2.0 @20110524 */\n\tif (dwrq->flags == 0x8766 && len > 8) {\n\t\tu32 cp_sz;\n\t\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\t\tu8 *probereq_wpsie = ext;\n\t\tint probereq_wpsie_len = len;\n\t\tu8 wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};\n\n\t\tif ((_VENDOR_SPECIFIC_IE_ == probereq_wpsie[0]) &&\n\t\t    (_rtw_memcmp(&probereq_wpsie[2], wps_oui, 4) == _TRUE)) {\n\t\t\tcp_sz = probereq_wpsie_len > MAX_WPS_IE_LEN ? MAX_WPS_IE_LEN : probereq_wpsie_len;\n\n\t\t\tif (pmlmepriv->wps_probe_req_ie) {\n\t\t\t\tu32 free_len = pmlmepriv->wps_probe_req_ie_len;\n\t\t\t\tpmlmepriv->wps_probe_req_ie_len = 0;\n\t\t\t\trtw_mfree(pmlmepriv->wps_probe_req_ie, free_len);\n\t\t\t\tpmlmepriv->wps_probe_req_ie = NULL;\n\t\t\t}\n\n\t\t\tpmlmepriv->wps_probe_req_ie = rtw_malloc(cp_sz);\n\t\t\tif (pmlmepriv->wps_probe_req_ie == NULL) {\n\t\t\t\tprintk(\"%s()-%d: rtw_malloc() ERROR!\\n\", __FUNCTION__, __LINE__);\n\t\t\t\tret =  -EINVAL;\n\t\t\t\tgoto FREE_EXT;\n\n\t\t\t}\n\n\t\t\t_rtw_memcpy(pmlmepriv->wps_probe_req_ie, probereq_wpsie, cp_sz);\n\t\t\tpmlmepriv->wps_probe_req_ie_len = cp_sz;\n\n\t\t}\n\n\t\tgoto FREE_EXT;\n\n\t}\n\n\tif (len >= WEXT_CSCAN_HEADER_SIZE\n\t\t&& _rtw_memcmp(ext, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE\n\t) {\n\t\tret = rtw_wx_set_scan(dev, info, awrq, ext);\n\t\tgoto FREE_EXT;\n\t}\n\n#ifdef CONFIG_ANDROID\n\t/* RTW_INFO(\"rtw_wx_set_priv: %s req=%s\\n\", dev->name, ext); */\n\n\ti = rtw_android_cmdstr_to_num(ext);\n\n\tswitch (i) {\n\tcase ANDROID_WIFI_CMD_START:\n\t\tindicate_wx_custom_event(padapter, \"START\");\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_STOP:\n\t\tindicate_wx_custom_event(padapter, \"STOP\");\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_RSSI: {\n\t\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\t\tstruct\twlan_network\t*pcur_network = &pmlmepriv->cur_network;\n\n\t\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)\n\t\t\tsprintf(ext, \"%s rssi %d\", pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi);\n\t\telse\n\t\t\tsprintf(ext, \"OK\");\n\t}\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_LINKSPEED: {\n\t\tu16 mbps = rtw_get_cur_max_rate(padapter) / 10;\n\t\tsprintf(ext, \"LINKSPEED %d\", mbps);\n\t}\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_MACADDR:\n\t\tsprintf(ext, \"MACADDR = \" MAC_FMT, MAC_ARG(dev->dev_addr));\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_SCAN_ACTIVE: {\n\t\t/* rtw_set_scan_mode(padapter, SCAN_ACTIVE); */\n\t\tsprintf(ext, \"OK\");\n\t}\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_SCAN_PASSIVE: {\n\t\t/* rtw_set_scan_mode(padapter, SCAN_PASSIVE); */\n\t\tsprintf(ext, \"OK\");\n\t}\n\t\tbreak;\n\n\tcase ANDROID_WIFI_CMD_COUNTRY: {\n\t\tchar country_code[10];\n\t\tsscanf(ext, \"%*s %s\", country_code);\n\t\trtw_set_country(padapter, country_code);\n\t\tsprintf(ext, \"OK\");\n\t}\n\t\tbreak;\n\tdefault:\n\t\t#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV\n\t\tRTW_INFO(\"%s: %s unknowned req=%s\\n\", __FUNCTION__,\n\t\t\tdev->name, ext_dbg);\n\t\t#endif\n\n\t\tsprintf(ext, \"OK\");\n\n\t}\n\n\tif (copy_to_user(dwrq->pointer, ext, min(dwrq->length, (u16)(strlen(ext) + 1))))\n\t\tret = -EFAULT;\n\n#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV\n\tRTW_INFO(\"%s: %s req=%s rep=%s dwrq->length=%d, strlen(ext)+1=%d\\n\", __FUNCTION__,\n\t\tdev->name, ext_dbg , ext, dwrq->length, (u16)(strlen(ext) + 1));\n#endif\n#endif /* end of CONFIG_ANDROID */\n\n\nFREE_EXT:\n\n\trtw_vmfree(ext, len);\n\t#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV\n\trtw_vmfree(ext_dbg, len);\n\t#endif\n\n\t/* RTW_INFO(\"rtw_wx_set_priv: (SIOCSIWPRIV) %s ret=%d\\n\",  */\n\t/*\t\tdev->name, ret); */\n\n\treturn ret;\n\n}\n#ifdef CONFIG_WOWLAN\nstatic int rtw_wowlan_ctrl(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wowlan_ioctl_param poidparam;\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct sta_info\t*psta = NULL;\n\tint ret = 0;\n\tsystime start_time = rtw_get_current_time();\n\tpoidparam.subcode = 0;\n\n\tRTW_INFO(\"+rtw_wowlan_ctrl: %s\\n\", extra);\n\n\tif (!check_fwstate(pmlmepriv, _FW_LINKED) &&\n\t\tcheck_fwstate(pmlmepriv, WIFI_STATION_STATE) &&\n\t\t!WOWLAN_IS_STA_MIX_MODE(padapter)) {\n#ifdef CONFIG_PNO_SUPPORT\n\t\tpwrctrlpriv->wowlan_pno_enable = _TRUE;\n#else\n\t\tRTW_INFO(\"[%s] WARNING: Please Connect With AP First!!\\n\", __func__);\n\t\tgoto _rtw_wowlan_ctrl_exit_free;\n#endif /* CONFIG_PNO_SUPPORT */\n\t}\n\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))\n\t\trtw_scan_abort(padapter);\n\n\tif (_rtw_memcmp(extra, \"enable\", 6))\n\n\n\t\trtw_suspend_common(padapter);\n\n\telse if (_rtw_memcmp(extra, \"disable\", 7)) {\n#ifdef CONFIG_USB_HCI\n\t\tRTW_ENABLE_FUNC(padapter, DF_RX_BIT);\n\t\tRTW_ENABLE_FUNC(padapter, DF_TX_BIT);\n#endif\n\t\trtw_resume_common(padapter);\n\n#ifdef CONFIG_PNO_SUPPORT\n\t\tpwrctrlpriv->wowlan_pno_enable = _FALSE;\n#endif /* CONFIG_PNO_SUPPORT */\n\n\t} else {\n\t\tRTW_INFO(\"[%s] Invalid Parameter.\\n\", __func__);\n\t\tgoto _rtw_wowlan_ctrl_exit_free;\n\t}\n\t/* mutex_lock(&ioctl_mutex); */\n_rtw_wowlan_ctrl_exit_free:\n\tRTW_INFO(\"-rtw_wowlan_ctrl( subcode = %d)\\n\", poidparam.subcode);\n\tRTW_PRINT(\"%s in %d ms\\n\", __func__,\n\t\t  rtw_get_passing_time_ms(start_time));\n\treturn ret;\n}\n\n/*\n * IP filter This pattern if for a frame containing a ip packet:\n * AA:AA:AA:AA:AA:AA:BB:BB:BB:BB:BB:BB:CC:CC:DD:-:-:-:-:-:-:-:-:EE:-:-:FF:FF:FF:FF:GG:GG:GG:GG:HH:HH:II:II\n *\n * A: Ethernet destination address\n * B: Ethernet source address\n * C: Ethernet protocol type\n * D: IP header VER+Hlen, use: 0x45 (4 is for ver 4, 5 is for len 20)\n * E: IP protocol\n * F: IP source address ( 192.168.0.4: C0:A8:00:2C )\n * G: IP destination address ( 192.168.0.4: C0:A8:00:2C )\n * H: Source port (1024: 04:00)\n * I: Destination port (1024: 04:00)\n */\n\nstatic int rtw_wowlan_set_pattern(struct net_device *dev,\n\t\t\t\t  struct iw_request_info *info,\n\t\t\t\t  union iwreq_data *wrqu, char *extra)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct wowlan_ioctl_param poidparam;\n\tint ret = 0, len = 0, i = 0;\n\tsystime start_time = rtw_get_current_time();\n\tu8 input[wrqu->data.length];\n\tu8 index = 0;\n\n\tpoidparam.subcode = 0;\n\n\tif (!check_fwstate(pmlmepriv, _FW_LINKED) &&\n\t    check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {\n\t\tret = -EFAULT;\n\t\tRTW_INFO(\"Please Connect With AP First!!\\n\");\n\t\tgoto _rtw_wowlan_set_pattern_exit;\n\t}\n\n\tif (wrqu->data.length <= 0) {\n\t\tret = -EFAULT;\n\t\tRTW_INFO(\"ERROR: parameter length <= 0\\n\");\n\t\tgoto _rtw_wowlan_set_pattern_exit;\n\t} else {\n\t\t/* set pattern */\n\t\tif (copy_from_user(input,\n\t\t\t\t   wrqu->data.pointer, wrqu->data.length))\n\t\t\treturn -EFAULT;\n\t\t/* leave PS first */\n\t\trtw_ps_deny(padapter, PS_DENY_IOCTL);\n\t\tLeaveAllPowerSaveModeDirect(padapter);\n\t\tif (strncmp(input, \"pattern=\", 8) == 0) {\n\t\t\tif (pwrpriv->wowlan_pattern_idx >= MAX_WKFM_CAM_NUM) {\n\t\t\t\tRTW_INFO(\"WARNING: priv-pattern is full(idx: %d)\\n\",\n\t\t\t\t\t pwrpriv->wowlan_pattern_idx);\n\t\t\t\tRTW_INFO(\"WARNING: please clean priv-pattern first\\n\");\n\t\t\t\tret = -EINVAL;\n\t\t\t\tgoto _rtw_wowlan_set_pattern_exit;\n\t\t\t} else {\n\t\t\t\tindex = pwrpriv->wowlan_pattern_idx;\n\t\t\t\tret = rtw_wowlan_parser_pattern_cmd(input,\n\t\t\t\t\t    pwrpriv->patterns[index].content,\n\t\t\t\t\t    &pwrpriv->patterns[index].len,\n\t\t\t\t\t    pwrpriv->patterns[index].mask);\n\n\t\t\t\tif (ret == _TRUE)\n\t\t\t\t\tpwrpriv->wowlan_pattern_idx++;\n\t\t\t}\n\t\t} else if (strncmp(input, \"clean\", 5) == 0) {\n\t\t\tpoidparam.subcode = WOWLAN_PATTERN_CLEAN;\n\t\t\trtw_hal_set_hwreg(padapter,\n\t\t\t\t\t  HW_VAR_WOWLAN, (u8 *)&poidparam);\n\t\t} else if (strncmp(input, \"show\", 4) == 0) {\n\t\t\trtw_wow_pattern_cam_dump(padapter);\n\t\t\trtw_wow_pattern_sw_dump(padapter);\n\t\t} else {\n\t\t\tRTW_INFO(\"ERROR: incorrect parameter!\\n\");\n\t\t\tret = -EINVAL;\n\t\t}\n\t\trtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);\n\t}\n_rtw_wowlan_set_pattern_exit:\n\treturn ret;\n}\n#endif /* CONFIG_WOWLAN */\n\n#ifdef CONFIG_AP_WOWLAN\nstatic int rtw_ap_wowlan_ctrl(struct net_device *dev,\n\t\t\t      struct iw_request_info *info,\n\t\t\t      union iwreq_data *wrqu, char *extra)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct wowlan_ioctl_param poidparam;\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct sta_info\t*psta = NULL;\n\tint ret = 0;\n\tsystime start_time = rtw_get_current_time();\n\tpoidparam.subcode = 0;\n\n\tRTW_INFO(\"+rtw_ap_wowlan_ctrl: %s\\n\", extra);\n\n\tif (!check_fwstate(pmlmepriv, WIFI_AP_STATE)) {\n\t\tRTW_INFO(\"[%s] It is not AP mode!!\\n\", __func__);\n\t\tgoto _rtw_ap_wowlan_ctrl_exit_free;\n\t}\n\n\tif (_rtw_memcmp(extra, \"enable\", 6)) {\n\n\t\tpwrctrlpriv->wowlan_ap_mode = _TRUE;\n\n\t\trtw_suspend_common(padapter);\n\t} else if (_rtw_memcmp(extra, \"disable\", 7)) {\n#ifdef CONFIG_USB_HCI\n\t\tRTW_ENABLE_FUNC(padapter, DF_RX_BIT);\n\t\tRTW_ENABLE_FUNC(padapter, DF_TX_BIT);\n#endif\n\t\trtw_resume_common(padapter);\n\t} else {\n\t\tRTW_INFO(\"[%s] Invalid Parameter.\\n\", __func__);\n\t\tgoto _rtw_ap_wowlan_ctrl_exit_free;\n\t}\n\t/* mutex_lock(&ioctl_mutex); */\n_rtw_ap_wowlan_ctrl_exit_free:\n\tRTW_INFO(\"-rtw_ap_wowlan_ctrl( subcode = %d)\\n\", poidparam.subcode);\n\tRTW_PRINT(\"%s in %d ms\\n\", __func__,\n\t\t  rtw_get_passing_time_ms(start_time));\n_rtw_ap_wowlan_ctrl_exit:\n\treturn ret;\n}\n#endif /* CONFIG_AP_WOWLAN */\n\nstatic int rtw_pm_set(struct net_device *dev,\n\t\t      struct iw_request_info *info,\n\t\t      union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\tunsigned\tmode = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_INFO(\"[%s] extra = %s\\n\", __FUNCTION__, extra);\n\n\tif (_rtw_memcmp(extra, \"lps=\", 4)) {\n\t\tsscanf(extra + 4, \"%u\", &mode);\n\t\tret = rtw_pm_set_lps(padapter, mode);\n\t} else if (_rtw_memcmp(extra, \"ips=\", 4)) {\n\t\tsscanf(extra + 4, \"%u\", &mode);\n\t\tret = rtw_pm_set_ips(padapter, mode);\n\t} else if (_rtw_memcmp(extra, \"lps_level=\", 10)) {\n\t\tif (sscanf(extra + 10, \"%u\", &mode) > 0)\n\t\t\tret = rtw_pm_set_lps_level(padapter, mode);\n#ifdef CONFIG_LPS_1T1R\n\t} else if (_rtw_memcmp(extra, \"lps_1t1r=\", 9)) {\n\t\tif (sscanf(extra + 9, \"%u\", &mode) > 0)\n\t\t\tret = rtw_pm_set_lps_1t1r(padapter, mode);\n#endif\n\t} \n#ifdef CONFIG_WOWLAN\n\telse if (_rtw_memcmp(extra, \"wow_lps=\", 8)) {\n\t\tsscanf(extra + 8, \"%u\", &mode);\n\t\tret = rtw_pm_set_wow_lps(padapter, mode);\n\t} else if (_rtw_memcmp(extra, \"wow_lps_level=\", 14)) {\n\t\tif (sscanf(extra + 14, \"%u\", &mode) > 0)\n\t\t\tret = rtw_pm_set_wow_lps_level(padapter, mode);\n\t#ifdef CONFIG_LPS_1T1R\n\t} else if (_rtw_memcmp(extra, \"wow_lps_1t1r=\", 13)) {\n\t\tif (sscanf(extra + 13, \"%u\", &mode) > 0)\n\t\t\tret = rtw_pm_set_wow_lps_1t1r(padapter, mode);\n\t#endif\n\t}\n#endif /* CONFIG_WOWLAN */\n\telse\n\t\tret = -EINVAL;\n\n\treturn ret;\n}\n#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE\n\nint rtw_vendor_ie_get_raw_data(struct net_device *dev, u32 vendor_ie_num,\n\t\t\t\t\t\t\t   char *extra, u32 length)\n{\n\tint j;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tu32 vendor_ie_mask = 0;\n\tchar *pstring;\n\n\tif (vendor_ie_num >= WLAN_MAX_VENDOR_IE_NUM) {\n\t\tRTW_INFO(\"[%s] only support %d vendor ie\\n\", __func__ ,\n\t\t\t\t WLAN_MAX_VENDOR_IE_NUM);\n\t\treturn -EFAULT;\n\t}\n\n\tif (pmlmepriv->vendor_ielen[vendor_ie_num] == 0) {\n\t\tRTW_INFO(\"[%s]  Fail, vendor_ie_num: %d is not set\\n\", __func__,\n\t\t\t\t vendor_ie_num);\n\t\treturn -EFAULT;\n\t}\n\n\tif (length < 2 * pmlmepriv->vendor_ielen[vendor_ie_num] + 5) {\n\t\tRTW_INFO(\"[%s]  Fail, buffer size is too small\\n\", __func__);\n\t\treturn -EFAULT;\n\t}\n\n\tvendor_ie_mask = pmlmepriv->vendor_ie_mask[vendor_ie_num];\n\t_rtw_memset(extra, 0, length);\n\n\tpstring = extra;\n\tpstring += sprintf(pstring, \"%d,%x,\", vendor_ie_num, vendor_ie_mask);\n\n\tfor (j = 0; j < pmlmepriv->vendor_ielen[vendor_ie_num]; j++)\n\t\tpstring += sprintf(pstring, \"%02x\", pmlmepriv->vendor_ie[vendor_ie_num][j]);\n\n\tlength = pstring - extra;\n\treturn length;\n}\n\nint rtw_vendor_ie_get_data(struct net_device *dev, int vendor_ie_num, char *extra)\n{\n\tint j;\n\tchar *pstring;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tu32 vendor_ie_mask = 0;\n\t__u16 length = 0;\n\n\tvendor_ie_mask = pmlmepriv->vendor_ie_mask[vendor_ie_num];\n\tpstring = extra;\n\tpstring += sprintf(pstring , \"\\nVendor IE num %d , Mask:%x \" , vendor_ie_num , vendor_ie_mask);\n\n\tif (vendor_ie_mask & WIFI_BEACON_VENDOR_IE_BIT)\n\t\tpstring += sprintf(pstring , \"[Beacon]\");\n\tif (vendor_ie_mask & WIFI_PROBEREQ_VENDOR_IE_BIT)\n\t\tpstring += sprintf(pstring , \"[Probe Req]\");\n\tif (vendor_ie_mask & WIFI_PROBERESP_VENDOR_IE_BIT)\n\t\tpstring += sprintf(pstring , \"[Probe Resp]\");\n\tif (vendor_ie_mask & WIFI_ASSOCREQ_VENDOR_IE_BIT)\n\t\tpstring += sprintf(pstring , \"[Assoc Req]\");\n\tif (vendor_ie_mask & WIFI_ASSOCRESP_VENDOR_IE_BIT)\n\t\tpstring += sprintf(pstring , \"[Assoc Resp]\");\n#ifdef CONFIG_P2P\n\tif (vendor_ie_mask & WIFI_P2P_PROBEREQ_VENDOR_IE_BIT)\n\t\tpstring += sprintf(pstring , \"[P2P_Probe Req]\");\n\tif (vendor_ie_mask & WIFI_P2P_PROBERESP_VENDOR_IE_BIT)\n\t\tpstring += sprintf(pstring , \"[P2P_Probe Resp]\");\n#endif\n\n\tpstring += sprintf(pstring , \"\\nVendor IE:\\n\");\n\tfor (j = 0 ; j < pmlmepriv->vendor_ielen[vendor_ie_num]  ; j++)\n\t\tpstring += sprintf(pstring , \"%02x\" , pmlmepriv->vendor_ie[vendor_ie_num][j]);\n\n\tlength = pstring - extra;\n\treturn length;\n\n}\n\nint rtw_vendor_ie_get(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0, vendor_ie_num = 0, cmdlen;\n\tstruct iw_point *p;\n\tu8 *ptmp;\n\n\tp = &wrqu->data;\n\tcmdlen = p->length;\n\tif (0 == cmdlen)\n\t\treturn -EINVAL;\n\n\tptmp = (u8 *)rtw_malloc(cmdlen);\n\tif (NULL == ptmp)\n\t\treturn -ENOMEM;\n\n\tif (copy_from_user(ptmp, p->pointer, cmdlen)) {\n\t\tret = -EFAULT;\n\t\tgoto exit;\n\t}\n\tret = sscanf(ptmp , \"%d\", &vendor_ie_num);\n\tif (vendor_ie_num > WLAN_MAX_VENDOR_IE_NUM - 1) {\n\t\tret = -EFAULT;\n\t\tgoto exit;\n\t}\n\n\twrqu->data.length = rtw_vendor_ie_get_data(dev, vendor_ie_num, extra);\n\nexit:\n\trtw_mfree(ptmp, cmdlen);\n\n\treturn 0;\n}\n\nint rtw_vendor_ie_set(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0, i , len = 0 , totoal_ie_len = 0 , total_ie_len_byte = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tu32 vendor_ie_mask = 0;\n\tu32 vendor_ie_num = 0;\n\tu32 vendor_ie_mask_max = BIT(WLAN_MAX_VENDOR_IE_MASK_MAX) - 1;\n\tu32 id, elen;\n\n\tret = sscanf(extra, \"%d,%x,%*s\", &vendor_ie_num , &vendor_ie_mask);\n\tif (strrchr(extra , ','))\n\t\textra = strrchr(extra , ',') + 1;\n\telse\n\t\treturn -EINVAL;\n\ttotoal_ie_len = strlen(extra);\n\tRTW_INFO(\"[%s] vendor_ie_num = %d , vendor_ie_mask = 0x%x , vendor_ie = %s , len = %d\\n\", __func__ , vendor_ie_num , vendor_ie_mask , extra  , totoal_ie_len);\n\n\tif (vendor_ie_num  > WLAN_MAX_VENDOR_IE_NUM - 1) {\n\t\tRTW_INFO(\"[%s] Fail, only support %d vendor ie\\n\", __func__ , WLAN_MAX_VENDOR_IE_NUM);\n\t\treturn -EFAULT;\n\t}\n\n\tif (totoal_ie_len > WLAN_MAX_VENDOR_IE_LEN) {\n\t\tRTW_INFO(\"[%s] Fail , not support ie length extend %d\\n\", __func__ , WLAN_MAX_VENDOR_IE_LEN);\n\t\treturn -EFAULT;\n\t}\n\n\tif (vendor_ie_mask > vendor_ie_mask_max) {\n\t\tRTW_INFO(\"[%s] Fail, not support vendor_ie_mask more than 0x%x\\n\", __func__ , vendor_ie_mask_max);\n\t\treturn -EFAULT;\n\t}\n\n\tif (vendor_ie_mask == 0) {\n\t\tRTW_INFO(\"[%s] Clear vendor_ie_num %d group\\n\", __func__ , vendor_ie_num);\n\t\tgoto _clear_path;\n\t}\n\n\tif (totoal_ie_len % 2 != 0) {\n\t\tRTW_INFO(\"[%s]  Fail , IE length = %zu is odd\\n\" , __func__ , strlen(extra));\n\t\treturn -EFAULT;\n\t}\n\n\tif (totoal_ie_len > 0) {\n\t\tfor (i = 0  ; i < strlen(extra) ; i += 2) {\n\t\t\tpmlmepriv->vendor_ie[vendor_ie_num][len] = key_2char2num(extra[i] , extra[i + 1]);\n\t\t\tif (len == 0) {\n\t\t\t\tid = pmlmepriv->vendor_ie[vendor_ie_num][len];\n\t\t\t\tif (id != WLAN_EID_VENDOR_SPECIFIC) {\n\t\t\t\t\tRTW_INFO(\"[%s] Fail , VENDOR SPECIFIC IE ID \\\"%x\\\" was not correct\\n\", __func__ , id);\n\t\t\t\t\tgoto _clear_path;\n\t\t\t\t}\n\t\t\t} else if (len == 1) {\n\t\t\t\ttotal_ie_len_byte = (totoal_ie_len / 2) - 2;\n\t\t\t\telen = pmlmepriv->vendor_ie[vendor_ie_num][len];\n\t\t\t\tif (elen != total_ie_len_byte) {\n\t\t\t\t\tRTW_INFO(\"[%s] Fail , Input IE length = \\\"%d\\\"(hex:%x) bytes , not match input total IE context length \\\"%d\\\" bytes\\n\", __func__ , elen , elen ,\n\t\t\t\t\t\t total_ie_len_byte);\n\t\t\t\t\tgoto _clear_path;\n\t\t\t\t}\n\t\t\t}\n\t\t\tlen++;\n\t\t}\n\t\tpmlmepriv->vendor_ielen[vendor_ie_num] = len;\n\t} else\n\t\tpmlmepriv->vendor_ielen[vendor_ie_num] = 0;\n\n\n\n\tif (vendor_ie_mask & WIFI_BEACON_VENDOR_IE_BIT)\n\t\tRTW_INFO(\"[%s] Beacon append vendor ie\\n\", __func__);\n\tif (vendor_ie_mask & WIFI_PROBEREQ_VENDOR_IE_BIT)\n\t\tRTW_INFO(\"[%s] Probe Req append vendor ie\\n\", __func__);\n\tif (vendor_ie_mask & WIFI_PROBERESP_VENDOR_IE_BIT)\n\t\tRTW_INFO(\"[%s] Probe Resp append vendor ie\\n\", __func__);\n\tif (vendor_ie_mask & WIFI_ASSOCREQ_VENDOR_IE_BIT)\n\t\tRTW_INFO(\"[%s] Assoc Req append vendor ie\\n\", __func__);\n\tif (vendor_ie_mask & WIFI_ASSOCRESP_VENDOR_IE_BIT)\n\t\tRTW_INFO(\"[%s] Assoc Resp append vendor ie\\n\", __func__);\n#ifdef CONFIG_P2P\n\tif (vendor_ie_mask & WIFI_P2P_PROBEREQ_VENDOR_IE_BIT)\n\t\tRTW_INFO(\"[%s] P2P Probe Req append vendor ie\\n\", __func__);\n\tif (vendor_ie_mask & WIFI_P2P_PROBERESP_VENDOR_IE_BIT)\n\t\tRTW_INFO(\"[%s] P2P Probe Resp append vendor ie\\n\", __func__);\n#endif\n\n\tpmlmepriv->vendor_ie_mask[vendor_ie_num] = vendor_ie_mask;\n\n\treturn ret;\n\n_clear_path:\n\t_rtw_memset(pmlmepriv->vendor_ie[vendor_ie_num] , 0 , sizeof(u32) * WLAN_MAX_VENDOR_IE_LEN);\n\tpmlmepriv->vendor_ielen[vendor_ie_num] = 0;\n\tpmlmepriv->vendor_ie_mask[vendor_ie_num] = 0;\n\treturn -EFAULT;\n}\n#endif\n\nstatic int rtw_mp_efuse_get(struct net_device *dev,\n\t\t\t    struct iw_request_info *info,\n\t\t\t    union iwreq_data *wdata, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n\tPEFUSE_HAL pEfuseHal;\n\tstruct iw_point *wrqu;\n\n\tu8 ips_mode = IPS_NUM; /* init invalid value */\n\tu8 lps_mode = PS_MODE_NUM; /* init invalid value */\n\tstruct pwrctrl_priv *pwrctrlpriv ;\n\tu8 *data = NULL;\n\tu8 *rawdata = NULL;\n\tchar *pch, *ptmp, *token, *tmp[3] = {0x00, 0x00, 0x00};\n\tu16 i = 0, j = 0, mapLen = 0, addr = 0, cnts = 0;\n\tu16 max_available_len = 0, raw_cursize = 0, raw_maxsize = 0;\n\tu16 mask_len;\n\tu8 mask_buf[64] = \"\";\n\tint err;\n\tchar *pextra = NULL;\n#ifdef CONFIG_IOL\n\tu8 org_fw_iol = padapter->registrypriv.fw_iol;/* 0:Disable, 1:enable, 2:by usb speed */\n#endif\n\n\twrqu = (struct iw_point *)wdata;\n\tpwrctrlpriv = adapter_to_pwrctl(padapter);\n\tpEfuseHal = &pHalData->EfuseHal;\n\n\terr = 0;\n\tdata = rtw_zmalloc(EFUSE_BT_MAX_MAP_LEN);\n\tif (data == NULL) {\n\t\terr = -ENOMEM;\n\t\tgoto exit;\n\t}\n\trawdata = rtw_zmalloc(EFUSE_BT_MAX_MAP_LEN);\n\tif (rawdata == NULL) {\n\t\terr = -ENOMEM;\n\t\tgoto exit;\n\t}\n\n\tif (copy_from_user(extra, wrqu->pointer, wrqu->length)) {\n\t\terr = -EFAULT;\n\t\tgoto exit;\n\t}\n\n\t*(extra + wrqu->length) = '\\0';\n\n#ifdef CONFIG_LPS\n\tlps_mode = pwrctrlpriv->power_mgnt;/* keep org value */\n\trtw_pm_set_lps(padapter, PS_MODE_ACTIVE);\n#endif\n\n#ifdef CONFIG_IPS\n\tips_mode = pwrctrlpriv->ips_mode;/* keep org value */\n\trtw_pm_set_ips(padapter, IPS_NONE);\n#endif\n\n\tpch = extra;\n\tRTW_INFO(\"%s: in=%s\\n\", __FUNCTION__, extra);\n\n\ti = 0;\n\t/* mac 16 \"00e04c871200\" rmap,00,2 */\n\twhile ((token = strsep(&pch, \",\")) != NULL) {\n\t\tif (i > 2)\n\t\t\tbreak;\n\t\ttmp[i] = token;\n\t\ti++;\n\t}\n#ifdef CONFIG_IOL\n\tpadapter->registrypriv.fw_iol = 0;/* 0:Disable, 1:enable, 2:by usb speed */\n#endif\n\n\tif (strcmp(tmp[0], \"status\") == 0) {\n\t\tsprintf(extra, \"Load File efuse=%s,Load File MAC=%s\"\n\t\t\t, pHalData->efuse_file_status == EFUSE_FILE_FAILED ? \"FAIL\" : \"OK\"\n\t\t\t, pHalData->macaddr_file_status == MACADDR_FILE_FAILED ? \"FAIL\" : \"OK\"\n\t\t       );\n\t\tgoto exit;\n\t} else if (strcmp(tmp[0], \"drvmap\") == 0) {\n\t\tstatic u8 drvmaporder = 0;\n\t\tu8 *efuse;\n\t\tu32 shift, cnt;\n\t\tu32 blksz = 0x200; /* The size of one time show, default 512 */\n\t\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);\n\n\t\tefuse = pHalData->efuse_eeprom_data;\n\n\t\tshift = blksz * drvmaporder;\n\t\tefuse += shift;\n\t\tcnt = mapLen - shift;\n\n\t\tif (cnt > blksz) {\n\t\t\tcnt = blksz;\n\t\t\tdrvmaporder++;\n\t\t} else\n\t\t\tdrvmaporder = 0;\n\n\t\tsprintf(extra, \"\\n\");\n\t\tfor (i = 0; i < cnt; i += 16) {\n\t\t\tpextra = extra + strlen(extra);\n\t\t\tpextra += sprintf(pextra, \"0x%02x\\t\", shift + i);\n\t\t\tfor (j = 0; j < 8; j++)\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", efuse[i + j]);\n\t\t\tpextra += sprintf(pextra, \"\\t\");\n\t\t\tfor (; j < 16; j++)\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", efuse[i + j]);\n\t\t\tpextra += sprintf(pextra, \"\\n\");\n\t\t}\n\t\tif ((shift + cnt) < mapLen)\n\t\t\tpextra += sprintf(pextra, \"\\t...more (left:%d/%d)\\n\", mapLen-(shift + cnt), mapLen);\n\n\t} else if (strcmp(tmp[0], \"realmap\") == 0) {\n\t\tstatic u8 order = 0;\n\t\tu8 *efuse;\n\t\tu32 shift, cnt;\n\t\tu32 blksz = 0x200; /* The size of one time show, default 512 */\n\n\t\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapLen, _FALSE);\n\t\tefuse = pEfuseHal->fakeEfuseInitMap;\n\t\tif (rtw_efuse_mask_map_read(padapter, 0, mapLen, efuse) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: read realmap Fail!!\\n\", __FUNCTION__);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n#if 0\n\t\tRTW_INFO(\"OFFSET\\tVALUE(hex)\\n\");\n\t\tfor (i = 0; i < mapLen; i += 16) {\n\t\t\tRTW_INFO(\"0x%02x\\t\", i);\n\t\t\tfor (j = 0; j < 8; j++)\n\t\t\t\tRTW_INFO(\"%02X \", efuse[i + j]);\n\t\t\tRTW_INFO(\"\\t\");\n\t\t\tfor (; j < 16; j++)\n\t\t\t\tRTW_INFO(\"%02X \", efuse[i + j]);\n\t\t\tRTW_INFO(\"\\n\");\n\t\t}\n\t\tRTW_INFO(\"\\n\");\n#endif\n\n\t\tshift = blksz * order;\n\t\tefuse += shift;\n\t\tcnt = mapLen - shift;\n\t\tif (cnt > blksz) {\n\t\t\tcnt = blksz;\n\t\t\torder++;\n\t\t} else\n\t\t\torder = 0;\n\n\t\tsprintf(extra, \"\\n\");\n\t\tfor (i = 0; i < cnt; i += 16) {\n\t\t\tpextra = extra + strlen(extra);\n\t\t\tpextra += sprintf(pextra, \"0x%02x\\t\", shift + i);\n\t\t\tfor (j = 0; j < 8; j++)\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", efuse[i + j]);\n\t\t\tpextra += sprintf(pextra, \"\\t\");\n\t\t\tfor (; j < 16; j++)\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", efuse[i + j]);\n\t\t\tpextra += sprintf(pextra, \"\\n\");\n\t\t}\n\t\tif ((shift + cnt) < mapLen)\n\t\t\tpextra += sprintf(pextra, \"\\t...more (left:%d/%d)\\n\", mapLen-(shift + cnt), mapLen);\n\t} else if (strcmp(tmp[0], \"rmap\") == 0) {\n\t\tif ((tmp[1] == NULL) || (tmp[2] == NULL)) {\n\t\t\tRTW_INFO(\"%s: rmap Fail!! Parameters error!\\n\", __FUNCTION__);\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* rmap addr cnts */\n\t\taddr = simple_strtoul(tmp[1], &ptmp, 16);\n\t\tRTW_INFO(\"%s: addr=%x\\n\", __FUNCTION__, addr);\n\n\t\tcnts = simple_strtoul(tmp[2], &ptmp, 10);\n\t\tif (cnts == 0) {\n\t\t\tRTW_INFO(\"%s: rmap Fail!! cnts error!\\n\", __FUNCTION__);\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tRTW_INFO(\"%s: cnts=%d\\n\", __FUNCTION__, cnts);\n\n\t\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&max_available_len, _FALSE);\n\t\tif ((addr + cnts) > max_available_len) {\n\t\t\tRTW_INFO(\"%s: addr(0x%X)+cnts(%d) parameter error!\\n\", __FUNCTION__, addr, cnts);\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_efuse_mask_map_read error!\\n\", __func__);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/*\t\tRTW_INFO(\"%s: data={\", __FUNCTION__); */\n\t\t*extra = 0;\n\t\tpextra = extra;\n\t\tfor (i = 0; i < cnts; i++) {\n\t\t\t/*\t\t\tRTW_INFO(\"0x%02x \", data[i]); */\n\t\t\tpextra += sprintf(pextra, \"0x%02X \", data[i]);\n\t\t}\n\t\t/*\t\tRTW_INFO(\"}\\n\"); */\n\t} else if (strcmp(tmp[0], \"realraw\") == 0) {\n\t\tstatic u8 raw_order = 0;\n\t\tu32 shift, cnt;\n\t\tu32 blksz = 0x200; /* The size of one time show, default 512 */\n\n\t\taddr = 0;\n\t\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN , (void *)&mapLen, _FALSE);\n\t\tRTW_INFO(\"Real content len = %d\\n\",mapLen );\n\n\t\tif (rtw_efuse_access(padapter, _FALSE, addr, mapLen, rawdata) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_efuse_access Fail!!\\n\", __func__);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t_rtw_memset(extra, '\\0', strlen(extra));\n\n\t\tshift = blksz * raw_order;\n\t\trawdata += shift;\n\t\tcnt = mapLen - shift;\n\t\tif (cnt > blksz) {\n\t\t\tcnt = blksz;\n\t\t\traw_order++;\n\t\t} else\n\t\t\traw_order = 0;\n\n\t\tsprintf(extra, \"\\n\");\n\t\tfor (i = 0; i < cnt; i += 16) {\n\t\t\tpextra = extra + strlen(extra);\n\t\t\tpextra += sprintf(pextra, \"0x%02x\\t\", shift + i);\n\t\t\tfor (j = 0; j < 8; j++)\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", rawdata[i + j]);\n\t\t\tpextra += sprintf(pextra, \"\\t\");\n\t\t\tfor (; j < 16; j++)\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", rawdata[i + j]);\n\t\t\tpextra += sprintf(pextra, \"\\n\");\n\t\t}\n\t\tif ((shift + cnt) < mapLen)\n\t\t\tpextra += sprintf(pextra, \"\\t...more (left:%d/%d)\\n\", mapLen-(shift + cnt), mapLen);\n\n\t} else if (strcmp(tmp[0], \"btrealraw\") == 0) {\n\t\tstatic u8 bt_raw_order = 0;\n\t\tu32 shift, cnt;\n\t\tu32 blksz = 0x200; /* The size of one time show, default 512 */\n\n\t\taddr = 0;\n\t\tEFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_REAL_CONTENT_LEN, (void *)&mapLen, _FALSE);\n\t\tRTW_INFO(\"Real content len = %d\\n\", mapLen);\n#ifdef RTW_HALMAC\n\t\tif (rtw_efuse_bt_access(padapter, _FALSE, 0, mapLen, rawdata) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_efuse_access Fail!!\\n\", __func__);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n#else\n\t\trtw_write8(padapter, 0x35, 0x1);\n\n\t\tif (rtw_efuse_access(padapter, _FALSE, addr, mapLen, rawdata) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_efuse_access Fail!!\\n\", __func__);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n#endif\n\t\t_rtw_memset(extra, '\\0', strlen(extra));\n\n\t\tshift = blksz * bt_raw_order;\n\t\trawdata += shift;\n\t\tcnt = mapLen - shift;\n\t\tif (cnt > blksz) {\n\t\t\tcnt = blksz;\n\t\t\tbt_raw_order++;\n\t\t} else\n\t\t\tbt_raw_order = 0;\n\n\t\tsprintf(extra, \"\\n\");\n\t\tfor (i = 0; i < cnt; i += 16) {\n\t\t\tpextra = extra + strlen(extra);\n\t\t\tpextra += sprintf(pextra, \"0x%02x\\t\", shift + i);\n\t\t\tfor (j = 0; j < 8; j++)\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", rawdata[i + j]);\n\t\t\tpextra += sprintf(pextra, \"\\t\");\n\t\t\tfor (; j < 16; j++)\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", rawdata[i + j]);\n\t\t\tpextra += sprintf(pextra, \"\\n\");\n\t\t}\n\t\tif ((shift + cnt) < mapLen)\n\t\t\tpextra += sprintf(pextra, \"\\t...more (left:%d/%d)\\n\", mapLen-(shift + cnt), mapLen);\n\n\t} else if (strcmp(tmp[0], \"mac\") == 0) {\n\t\tif (hal_efuse_macaddr_offset(padapter) == -1) {\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\taddr = hal_efuse_macaddr_offset(padapter);\n\t\tcnts = 6;\n\n\t\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);\n\t\tif ((addr + cnts) > max_available_len) {\n\t\t\tRTW_INFO(\"%s: addr(0x%02x)+cnts(%d) parameter error!\\n\", __FUNCTION__, addr, cnts);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_efuse_mask_map_read error!\\n\", __func__);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/*\t\tRTW_INFO(\"%s: MAC address={\", __FUNCTION__); */\n\t\t*extra = 0;\n\t\tpextra = extra;\n\t\tfor (i = 0; i < cnts; i++) {\n\t\t\t/*\t\t\tRTW_INFO(\"%02X\", data[i]); */\n\t\t\tpextra += sprintf(pextra, \"%02X\", data[i]);\n\t\t\tif (i != (cnts - 1)) {\n\t\t\t\t/*\t\t\t\tRTW_INFO(\":\"); */\n\t\t\t\tpextra += sprintf(pextra, \":\");\n\t\t\t}\n\t\t}\n\t\t/*\t\tRTW_INFO(\"}\\n\"); */\n\t} else if (strcmp(tmp[0], \"vidpid\") == 0) {\n#ifdef CONFIG_RTL8188E\n#ifdef CONFIG_USB_HCI\n\t\taddr = EEPROM_VID_88EU;\n#endif\n#ifdef CONFIG_PCI_HCI\n\t\taddr = EEPROM_VID_88EE;\n#endif\n#endif /* CONFIG_RTL8188E */\n\n#ifdef CONFIG_RTL8192E\n#ifdef CONFIG_USB_HCI\n\t\taddr = EEPROM_VID_8192EU;\n#endif\n#ifdef CONFIG_PCI_HCI\n\t\taddr = EEPROM_VID_8192EE;\n#endif\n#endif /* CONFIG_RTL8192E */\n#ifdef CONFIG_RTL8723B\n\t\taddr = EEPROM_VID_8723BU;\n#endif /* CONFIG_RTL8192E */\n\n#ifdef CONFIG_RTL8188F\n\t\taddr = EEPROM_VID_8188FU;\n#endif /* CONFIG_RTL8188F */\n\n#ifdef CONFIG_RTL8188GTV\n\t\taddr = EEPROM_VID_8188GTVU;\n#endif\n\n#ifdef CONFIG_RTL8703B\n#ifdef CONFIG_USB_HCI\n\t\taddr = EEPROM_VID_8703BU;\n#endif\n#endif /* CONFIG_RTL8703B */\n\n#ifdef CONFIG_RTL8723D\n#ifdef CONFIG_USB_HCI\n\t\taddr = EEPROM_VID_8723DU;\n#endif /* CONFIG_USB_HCI */\n#endif /* CONFIG_RTL8723D */\n\n\t\tcnts = 4;\n\n\t\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);\n\t\tif ((addr + cnts) > max_available_len) {\n\t\t\tRTW_INFO(\"%s: addr(0x%02x)+cnts(%d) parameter error!\\n\", __FUNCTION__, addr, cnts);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\t\tif (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_efuse_access error!!\\n\", __FUNCTION__);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/*\t\tRTW_INFO(\"%s: {VID,PID}={\", __FUNCTION__); */\n\t\t*extra = 0;\n\t\tpextra = extra;\n\t\tfor (i = 0; i < cnts; i++) {\n\t\t\t/*\t\t\tRTW_INFO(\"0x%02x\", data[i]); */\n\t\t\tpextra += sprintf(pextra, \"0x%02X\", data[i]);\n\t\t\tif (i != (cnts - 1)) {\n\t\t\t\t/*\t\t\t\tRTW_INFO(\",\"); */\n\t\t\t\tpextra += sprintf(pextra, \",\");\n\t\t\t}\n\t\t}\n\t\t/*\t\tRTW_INFO(\"}\\n\"); */\n\t} else if (strcmp(tmp[0], \"ableraw\") == 0) {\n#ifdef RTW_HALMAC\n\t\traw_maxsize = efuse_GetavailableSize(padapter);\n#else\n\t\tefuse_GetCurrentSize(padapter, &raw_cursize);\n\t\traw_maxsize = efuse_GetMaxSize(padapter);\n#endif\n\t\tsprintf(extra, \"[available raw size]= %d bytes\\n\", raw_maxsize - raw_cursize);\n\t} else if (strcmp(tmp[0], \"btableraw\") == 0) {\n\t\tefuse_bt_GetCurrentSize(padapter, &raw_cursize);\n\t\traw_maxsize = efuse_bt_GetMaxSize(padapter);\n\t\tsprintf(extra, \"[available raw size]= %d bytes\\n\", raw_maxsize - raw_cursize);\n\t} else if (strcmp(tmp[0], \"btfmap\") == 0) {\n\n\t\tBTEfuse_PowerSwitch(padapter, 1, _TRUE);\n\n\t\tmapLen = EFUSE_BT_MAX_MAP_LEN;\n\t\tif (rtw_BT_efuse_map_read(padapter, 0, mapLen, pEfuseHal->BTEfuseInitMap) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_BT_efuse_map_read Fail!!\\n\", __FUNCTION__);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/*\t\tRTW_INFO(\"OFFSET\\tVALUE(hex)\\n\"); */\n\t\tsprintf(extra, \"\\n\");\n\t\tfor (i = 0; i < 512; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */\n\t\t\t/*\t\t\tRTW_INFO(\"0x%03x\\t\", i); */\n\t\t\tpextra = extra + strlen(extra);\n\t\t\tpextra += sprintf(pextra, \"0x%03x\\t\", i);\n\t\t\tfor (j = 0; j < 8; j++) {\n\t\t\t\t/*\t\t\t\tRTW_INFO(\"%02X \", pEfuseHal->BTEfuseInitMap[i+j]); */\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", pEfuseHal->BTEfuseInitMap[i+j]);\n\t\t\t}\n\t\t\t/*\t\t\tRTW_INFO(\"\\t\"); */\n\t\t\tpextra += sprintf(pextra, \"\\t\");\n\t\t\tfor (; j < 16; j++) {\n\t\t\t\t/*\t\t\t\tRTW_INFO(\"%02X \", pEfuseHal->BTEfuseInitMap[i+j]); */\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", pEfuseHal->BTEfuseInitMap[i+j]);\n\t\t\t}\n\t\t\t/*\t\t\tRTW_INFO(\"\\n\"); */\n\t\t\tpextra += sprintf(pextra, \"\\n\");\n\t\t}\n\t\t/*\t\tRTW_INFO(\"\\n\"); */\n\t} else if (strcmp(tmp[0], \"btbmap\") == 0) {\n\t\tBTEfuse_PowerSwitch(padapter, 1, _TRUE);\n\n\t\tmapLen = EFUSE_BT_MAX_MAP_LEN;\n\t\tif (rtw_BT_efuse_map_read(padapter, 0, mapLen, pEfuseHal->BTEfuseInitMap) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_BT_efuse_map_read Fail!!\\n\", __FUNCTION__);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/*\t\tRTW_INFO(\"OFFSET\\tVALUE(hex)\\n\"); */\n\t\tsprintf(extra, \"\\n\");\n\t\tfor (i = 512; i < 1024 ; i += 16) {\n\t\t\t/*\t\t\tRTW_INFO(\"0x%03x\\t\", i); */\n\t\t\tpextra = extra + strlen(extra);\n\t\t\tpextra += sprintf(pextra, \"0x%03x\\t\", i);\n\t\t\tfor (j = 0; j < 8; j++) {\n\t\t\t\t/*\t\t\t\tRTW_INFO(\"%02X \", data[i+j]); */\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", pEfuseHal->BTEfuseInitMap[i+j]);\n\t\t\t}\n\t\t\t/*\t\t\tRTW_INFO(\"\\t\"); */\n\t\t\tpextra += sprintf(pextra, \"\\t\");\n\t\t\tfor (; j < 16; j++) {\n\t\t\t\t/*\t\t\t\tRTW_INFO(\"%02X \", data[i+j]); */\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", pEfuseHal->BTEfuseInitMap[i+j]);\n\t\t\t}\n\t\t\t/*\t\t\tRTW_INFO(\"\\n\"); */\n\t\t\tpextra += sprintf(pextra, \"\\n\");\n\t\t}\n\t\t/*\t\tRTW_INFO(\"\\n\"); */\n\t} else if (strcmp(tmp[0], \"btrmap\") == 0) {\n\t\tu8 BTStatus;\n\n\t\trtw_write8(padapter, 0xa3, 0x05); /* For 8723AB ,8821S ? */\n\t\tBTStatus = rtw_read8(padapter, 0xa0);\n\n\t\tRTW_INFO(\"%s: Check 0xa0 BT Status =0x%x\\n\", __FUNCTION__, BTStatus);\n\t\tif (BTStatus != 0x04) {\n\t\t\tsprintf(extra, \"BT Status not Active ,can't to read BT eFuse\\n\");\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif ((tmp[1] == NULL) || (tmp[2] == NULL)) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tBTEfuse_PowerSwitch(padapter, 1, _TRUE);\n\n\t\t/* rmap addr cnts */\n\t\taddr = simple_strtoul(tmp[1], &ptmp, 16);\n\t\tRTW_INFO(\"%s: addr=0x%X\\n\", __FUNCTION__, addr);\n\n\t\tcnts = simple_strtoul(tmp[2], &ptmp, 10);\n\t\tif (cnts == 0) {\n\t\t\tRTW_INFO(\"%s: btrmap Fail!! cnts error!\\n\", __FUNCTION__);\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tRTW_INFO(\"%s: cnts=%d\\n\", __FUNCTION__, cnts);\n#ifndef RTW_HALMAC\n\t\tEFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);\n\t\tif ((addr + cnts) > max_available_len) {\n\t\t\tRTW_INFO(\"%s: addr(0x%X)+cnts(%d) parameter error!\\n\", __FUNCTION__, addr, cnts);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n#endif\n\t\tif (rtw_BT_efuse_map_read(padapter, addr, cnts, data) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_BT_efuse_map_read error!!\\n\", __FUNCTION__);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t*extra = 0;\n\t\tpextra = extra;\n\t\t/*\t\tRTW_INFO(\"%s: bt efuse data={\", __FUNCTION__); */\n\t\tfor (i = 0; i < cnts; i++) {\n\t\t\t/*\t\t\tRTW_INFO(\"0x%02x \", data[i]); */\n\t\t\tpextra += sprintf(pextra, \" 0x%02X \", data[i]);\n\t\t}\n\t\t/*\t\tRTW_INFO(\"}\\n\"); */\n\t\tRTW_INFO(FUNC_ADPT_FMT \": BT MAC=[%s]\\n\", FUNC_ADPT_ARG(padapter), extra);\n\t} else if (strcmp(tmp[0], \"btffake\") == 0) {\n\t\t/*\t\tRTW_INFO(\"OFFSET\\tVALUE(hex)\\n\"); */\n\t\tsprintf(extra, \"\\n\");\n\t\tfor (i = 0; i < 512; i += 16) {\n\t\t\t/*\t\t\tRTW_INFO(\"0x%03x\\t\", i); */\n\t\t\tpextra = extra + strlen(extra);\n\t\t\tpextra += sprintf(pextra, \"0x%03x\\t\", i);\n\t\t\tfor (j = 0; j < 8; j++) {\n\t\t\t\t/*\t\t\t\tRTW_INFO(\"%02X \", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", pEfuseHal->fakeBTEfuseModifiedMap[i+j]);\n\t\t\t}\n\t\t\t/*\t\t\tRTW_INFO(\"\\t\"); */\n\t\t\tpextra += sprintf(pextra, \"\\t\");\n\t\t\tfor (; j < 16; j++) {\n\t\t\t\t/*\t\t\t\tRTW_INFO(\"%02X \", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", pEfuseHal->fakeBTEfuseModifiedMap[i+j]);\n\t\t\t}\n\t\t\t/*\t\t\tRTW_INFO(\"\\n\"); */\n\t\t\tpextra += sprintf(pextra, \"\\n\");\n\t\t}\n\t\t/*\t\tRTW_INFO(\"\\n\"); */\n\t} else if (strcmp(tmp[0], \"btbfake\") == 0) {\n\t\t/*\t\tRTW_INFO(\"OFFSET\\tVALUE(hex)\\n\"); */\n\t\tsprintf(extra, \"\\n\");\n\t\tfor (i = 512; i < 1024; i += 16) {\n\t\t\t/*\t\t\tRTW_INFO(\"0x%03x\\t\", i); */\n\t\t\tpextra = extra + strlen(extra);\n\t\t\tpextra += sprintf(pextra, \"0x%03x\\t\", i);\n\t\t\tfor (j = 0; j < 8; j++) {\n\t\t\t\t/*\t\t\t\tRTW_INFO(\"%02X \", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", pEfuseHal->fakeBTEfuseModifiedMap[i+j]);\n\t\t\t}\n\t\t\t/*\t\t\tRTW_INFO(\"\\t\"); */\n\t\t\tpextra += sprintf(pextra, \"\\t\");\n\t\t\tfor (; j < 16; j++) {\n\t\t\t\t/*\t\t\t\tRTW_INFO(\"%02X \", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", pEfuseHal->fakeBTEfuseModifiedMap[i+j]);\n\t\t\t}\n\t\t\t/*\t\t\tRTW_INFO(\"\\n\"); */\n\t\t\tpextra += sprintf(pextra, \"\\n\");\n\t\t}\n\t\t/*\t\tRTW_INFO(\"\\n\"); */\n\t} else if (strcmp(tmp[0], \"wlrfkmap\") == 0) {\n\t\tstatic u8 fk_order = 0;\n\t\tu8 *efuse;\n\t\tu32 shift, cnt;\n\t\tu32 blksz = 0x200; /* The size of one time show, default 512 */\n\n\t\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapLen, _FALSE);\n\t\tefuse = pEfuseHal->fakeEfuseModifiedMap;\n\n\t\tshift = blksz * fk_order;\n\t\tefuse += shift;\n\t\tcnt = mapLen - shift;\n\t\tif (cnt > blksz) {\n\t\t\tcnt = blksz;\n\t\t\tfk_order++;\n\t\t} else\n\t\t\tfk_order = 0;\n\n\t\tsprintf(extra, \"\\n\");\n\t\tfor (i = 0; i < cnt; i += 16) {\n\t\t\tpextra = extra + strlen(extra);\n\t\t\tpextra += sprintf(pextra, \"0x%02x\\t\", shift + i);\n\t\t\tfor (j = 0; j < 8; j++)\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", efuse[i + j]);\n\t\t\tpextra += sprintf(pextra, \"\\t\");\n\t\t\tfor (; j < 16; j++)\n\t\t\t\tpextra += sprintf(pextra, \"%02X \", efuse[i + j]);\n\t\t\tpextra += sprintf(pextra, \"\\n\");\n\t\t}\n\t\tif ((shift + cnt) < mapLen)\n\t\t\tpextra += sprintf(pextra, \"\\t...more\\n\");\n\n\t} else if (strcmp(tmp[0], \"wlrfkrmap\") == 0) {\n\t\tif ((tmp[1] == NULL) || (tmp[2] == NULL)) {\n\t\t\tRTW_INFO(\"%s: rmap Fail!! Parameters error!\\n\", __FUNCTION__);\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\t/* rmap addr cnts */\n\t\taddr = simple_strtoul(tmp[1], &ptmp, 16);\n\t\tRTW_INFO(\"%s: addr=%x\\n\", __FUNCTION__, addr);\n\n\t\tcnts = simple_strtoul(tmp[2], &ptmp, 10);\n\t\tif (cnts == 0) {\n\t\t\tRTW_INFO(\"%s: rmap Fail!! cnts error!\\n\", __FUNCTION__);\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tRTW_INFO(\"%s: cnts=%d\\n\", __FUNCTION__, cnts);\n\n\t\t/*\t\tRTW_INFO(\"%s: data={\", __FUNCTION__); */\n\t\t*extra = 0;\n\t\tpextra = extra;\n\t\tfor (i = 0; i < cnts; i++) {\n\t\t\tRTW_INFO(\"wlrfkrmap = 0x%02x\\n\", pEfuseHal->fakeEfuseModifiedMap[addr + i]);\n\t\t\tpextra += sprintf(pextra, \"0x%02X \", pEfuseHal->fakeEfuseModifiedMap[addr+i]);\n\t\t}\n\t} else if (strcmp(tmp[0], \"btrfkrmap\") == 0) {\n\t\tif ((tmp[1] == NULL) || (tmp[2] == NULL)) {\n\t\t\tRTW_INFO(\"%s: rmap Fail!! Parameters error!\\n\", __FUNCTION__);\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\t/* rmap addr cnts */\n\t\taddr = simple_strtoul(tmp[1], &ptmp, 16);\n\t\tRTW_INFO(\"%s: addr=%x\\n\", __FUNCTION__, addr);\n\n\t\tcnts = simple_strtoul(tmp[2], &ptmp, 10);\n\t\tif (cnts == 0) {\n\t\t\tRTW_INFO(\"%s: rmap Fail!! cnts error!\\n\", __FUNCTION__);\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tRTW_INFO(\"%s: cnts=%d\\n\", __FUNCTION__, cnts);\n\n\t\t/*\t\tRTW_INFO(\"%s: data={\", __FUNCTION__); */\n\t\t*extra = 0;\n\t\tpextra = extra;\n\t\tfor (i = 0; i < cnts; i++) {\n\t\t\tRTW_INFO(\"wlrfkrmap = 0x%02x\\n\", pEfuseHal->fakeBTEfuseModifiedMap[addr + i]);\n\t\t\tpextra += sprintf(pextra, \"0x%02X \", pEfuseHal->fakeBTEfuseModifiedMap[addr+i]);\n\t\t}\n\t} else if (strcmp(tmp[0], \"mask\") == 0) {\n\t\t*extra = 0;\n\t\tmask_len = sizeof(u8) * rtw_get_efuse_mask_arraylen(padapter);\n\t\trtw_efuse_mask_array(padapter, mask_buf);\n\n\t\tif (padapter->registrypriv.bFileMaskEfuse == _TRUE)\n\t\t\t_rtw_memcpy(mask_buf, maskfileBuffer, mask_len);\n\n\t\tsprintf(extra, \"\\n\");\n\t\tpextra = extra + strlen(extra);\n\t\tfor (i = 0; i < mask_len; i++)\n\t\t\tpextra += sprintf(pextra, \"0x%02X\\n\", mask_buf[i]);\n\n\t} else if (strcmp(tmp[0], \"btmask\") == 0) {\n\t\t*extra = 0;\n\t\tmask_len = sizeof(u8) * rtw_get_bt_efuse_mask_arraylen(padapter);\n\t\trtw_bt_efuse_mask_array(padapter, mask_buf);\n\n\t\tif (padapter->registrypriv.bBTFileMaskEfuse == _TRUE)\n\t\t\t_rtw_memcpy(mask_buf, btmaskfileBuffer, mask_len);\n\n\t\tsprintf(extra, \"\\n\");\n\t\tpextra = extra + strlen(extra);\n\t\tfor (i = 0; i < mask_len; i++)\n\t\t\tpextra += sprintf(pextra, \"0x%02X\\n\", mask_buf[i]);\n\n\t} else\n\t\tsprintf(extra, \"Command not found!\");\n\nexit:\n\tif (data)\n\t\trtw_mfree(data, EFUSE_BT_MAX_MAP_LEN);\n\tif (rawdata)\n\t\trtw_mfree(rawdata, EFUSE_BT_MAX_MAP_LEN);\n\tif (!err)\n\t\twrqu->length = strlen(extra);\n\n\tif (padapter->registrypriv.mp_mode == 0) {\n#ifdef CONFIG_IPS\n\t\trtw_pm_set_ips(padapter, ips_mode);\n#endif /* CONFIG_IPS */\n\n#ifdef CONFIG_LPS\n\t\trtw_pm_set_lps(padapter, lps_mode);\n#endif /* CONFIG_LPS */\n\t}\n\n#ifdef CONFIG_IOL\n\tpadapter->registrypriv.fw_iol = org_fw_iol;/* 0:Disable, 1:enable, 2:by usb speed */\n#endif\n\treturn err;\n}\n\n\n#ifdef CONFIG_MP_INCLUDED\nstatic int rtw_mp_efuse_set(struct net_device *dev,\n\t\t\t    struct iw_request_info *info,\n\t\t\t    union iwreq_data *wdata, char *extra)\n{\n\tstruct iw_point *wrqu;\n\tPADAPTER padapter;\n\tstruct pwrctrl_priv *pwrctrlpriv ;\n\tPHAL_DATA_TYPE pHalData;\n\tPEFUSE_HAL pEfuseHal;\n\tstruct hal_ops *pHalFunc;\n\tstruct mp_priv *pmp_priv;\n\n\tu8 ips_mode = IPS_NUM; /* init invalid value */\n\tu8 lps_mode = PS_MODE_NUM; /* init invalid value */\n\tu32 i = 0, j = 0, jj, kk;\n\tu8 *setdata = NULL;\n\tu8 *ShadowMapBT = NULL;\n\tu8 *ShadowMapWiFi = NULL;\n\tu8 *setrawdata = NULL;\n\tchar *pch, *ptmp, *token, *tmp[3] = {0x00, 0x00, 0x00};\n\tu16 addr = 0xFF, cnts = 0, BTStatus = 0 , max_available_len = 0;\n\tu16 wifimaplen;\n\tint err;\n\tboolean bcmpchk = _TRUE;\n\n\n\twrqu = (struct iw_point *)wdata;\n\tpadapter = rtw_netdev_priv(dev);\n\tpwrctrlpriv = adapter_to_pwrctl(padapter);\n\tpHalData = GET_HAL_DATA(padapter);\n\tpEfuseHal = &pHalData->EfuseHal;\n\tpHalFunc = &padapter->hal_func;\n\tpmp_priv = &padapter->mppriv;\n\n\terr = 0;\n\n\tif (copy_from_user(extra, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\t*(extra + wrqu->length) = '\\0';\n\n\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&wifimaplen, _FALSE);\n\n\tsetdata = rtw_zmalloc(1024);\n\tif (setdata == NULL) {\n\t\terr = -ENOMEM;\n\t\tgoto exit;\n\t}\n\tShadowMapBT = rtw_malloc(EFUSE_BT_MAX_MAP_LEN);\n\tif (ShadowMapBT == NULL) {\n\t\terr = -ENOMEM;\n\t\tgoto exit;\n\t}\n\tShadowMapWiFi = rtw_malloc(wifimaplen);\n\tif (ShadowMapWiFi == NULL) {\n\t\terr = -ENOMEM;\n\t\tgoto exit;\n\t}\n\tsetrawdata = rtw_malloc(EFUSE_MAX_SIZE);\n\tif (setrawdata == NULL) {\n\t\terr = -ENOMEM;\n\t\tgoto exit;\n\t}\n\n#ifdef CONFIG_LPS\n\tlps_mode = pwrctrlpriv->power_mgnt;/* keep org value */\n\trtw_pm_set_lps(padapter, PS_MODE_ACTIVE);\n#endif\n\n#ifdef CONFIG_IPS\n\tips_mode = pwrctrlpriv->ips_mode;/* keep org value */\n\trtw_pm_set_ips(padapter, IPS_NONE);\n#endif\n\n\tpch = extra;\n\tRTW_INFO(\"%s: in=%s\\n\", __FUNCTION__, extra);\n\n\ti = 0;\n\twhile ((token = strsep(&pch, \",\")) != NULL) {\n\t\tif (i > 2)\n\t\t\tbreak;\n\t\ttmp[i] = token;\n\t\ti++;\n\t}\n\n\t/* tmp[0],[1],[2] */\n\t/* wmap,addr,00e04c871200 */\n\tif (strcmp(tmp[0], \"wmap\") == 0) {\n\t\tif ((tmp[1] == NULL) || (tmp[2] == NULL)) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n#ifndef RTW_HALMAC\n\t\t/* unknown bug workaround, need to fix later */\n\t\taddr = 0x1ff;\n\t\trtw_write8(padapter, EFUSE_CTRL + 1, (addr & 0xff));\n\t\trtw_msleep_os(10);\n\t\trtw_write8(padapter, EFUSE_CTRL + 2, ((addr >> 8) & 0x03));\n\t\trtw_msleep_os(10);\n\t\trtw_write8(padapter, EFUSE_CTRL + 3, 0x72);\n\t\trtw_msleep_os(10);\n\t\trtw_read8(padapter, EFUSE_CTRL);\n#endif /* RTW_HALMAC */\n\n\t\taddr = simple_strtoul(tmp[1], &ptmp, 16);\n\t\taddr &= 0xFFF;\n\n\t\tcnts = strlen(tmp[2]);\n\t\tif (cnts % 2) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tcnts /= 2;\n\t\tif (cnts == 0) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tRTW_INFO(\"%s: addr=0x%X\\n\", __FUNCTION__, addr);\n\t\tRTW_INFO(\"%s: cnts=%d\\n\", __FUNCTION__, cnts);\n\t\tRTW_INFO(\"%s: map data=%s\\n\", __FUNCTION__, tmp[2]);\n\n\t\tfor (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)\n\t\t\tsetdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);\n\n\t\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);\n\n\t\tif ((addr + cnts) > max_available_len) {\n\t\t\tRTW_INFO(\"%s: addr(0x%X)+cnts(%d) parameter error!\\n\", __FUNCTION__, addr, cnts);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_efuse_map_write error!!\\n\", __FUNCTION__);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\t\t*extra = 0;\n\t\tRTW_INFO(\"%s: after rtw_efuse_map_write to _rtw_memcmp\\n\", __func__);\n\t\tif (rtw_efuse_mask_map_read(padapter, addr, cnts, ShadowMapWiFi) == _SUCCESS) {\n\t\t\tif (_rtw_memcmp((void *)ShadowMapWiFi , (void *)setdata, cnts)) {\n\t\t\t\tRTW_INFO(\"%s: WiFi write map afterf compare success\\n\", __FUNCTION__);\n\t\t\t\tsprintf(extra, \"WiFi write map compare OK\\n\");\n\t\t\t\terr = 0;\n\t\t\t\tgoto exit;\n\t\t\t} else {\n\t\t\t\tsprintf(extra, \"WiFi write map compare FAIL\\n\");\n\t\t\t\tRTW_INFO(\"%s: WiFi write map compare Fail\\n\", __FUNCTION__);\n\t\t\t\terr = 0;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\t} else if (strcmp(tmp[0], \"wraw\") == 0) {\n\t\tif ((tmp[1] == NULL) || (tmp[2] == NULL)) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\taddr = simple_strtoul(tmp[1], &ptmp, 16);\n\t\taddr &= 0xFFF;\n\n\t\tcnts = strlen(tmp[2]);\n\t\tif (cnts % 2) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tcnts /= 2;\n\t\tif (cnts == 0) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tRTW_INFO(\"%s: addr=0x%X\\n\", __FUNCTION__, addr);\n\t\tRTW_INFO(\"%s: cnts=%d\\n\", __FUNCTION__, cnts);\n\t\tRTW_INFO(\"%s: raw data=%s\\n\", __FUNCTION__, tmp[2]);\n\n\t\tfor (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)\n\t\t\tsetrawdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);\n\n\t\tif (rtw_efuse_access(padapter, _TRUE, addr, cnts, setrawdata) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_efuse_access error!!\\n\", __FUNCTION__);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\t} else if (strcmp(tmp[0], \"btwraw\") == 0) {\n\t\tif ((tmp[1] == NULL) || (tmp[2] == NULL)) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\taddr = simple_strtoul(tmp[1], &ptmp, 16);\n\t\taddr &= 0xFFF;\n\n\t\tcnts = strlen(tmp[2]);\n\t\tif (cnts % 2) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tcnts /= 2;\n\t\tif (cnts == 0) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tRTW_INFO(\"%s: addr=0x%X\\n\", __FUNCTION__, addr);\n\t\tRTW_INFO(\"%s: cnts=%d\\n\", __FUNCTION__, cnts);\n\t\tRTW_INFO(\"%s: raw data=%s\\n\", __FUNCTION__, tmp[2]);\n\n\t\tfor (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)\n\t\t\tsetrawdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);\n#ifdef RTW_HALMAC\n\t\tif (rtw_efuse_bt_access(padapter, _TRUE, addr, cnts, setrawdata) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_efuse_access error!!\\n\", __FUNCTION__);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n#else\n\t\trtw_write8(padapter, 0x35, 1); /* switch bank 1 (BT)*/\n\t\tif (rtw_efuse_access(padapter, _TRUE, addr, cnts, setrawdata) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_efuse_access error!!\\n\", __FUNCTION__);\n\t\t\trtw_write8(padapter, 0x35, 0); /* switch bank 0 (WiFi)*/\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\t\trtw_write8(padapter, 0x35, 0); /* switch bank 0 (WiFi)*/\n#endif\n\t} else if (strcmp(tmp[0], \"mac\") == 0) {\n\t\tif (tmp[1] == NULL) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* mac,00e04c871200 */\n\n\t\tif (hal_efuse_macaddr_offset(padapter) == -1) {\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\taddr = hal_efuse_macaddr_offset(padapter);\n\t\tcnts = strlen(tmp[1]);\n\t\tif (cnts % 2) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tcnts /= 2;\n\t\tif (cnts == 0) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tif (cnts > 6) {\n\t\t\tRTW_INFO(\"%s: error data for mac addr=\\\"%s\\\"\\n\", __FUNCTION__, tmp[1]);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tRTW_INFO(\"%s: addr=0x%X\\n\", __FUNCTION__, addr);\n\t\tRTW_INFO(\"%s: cnts=%d\\n\", __FUNCTION__, cnts);\n\t\tRTW_INFO(\"%s: MAC address=%s\\n\", __FUNCTION__, tmp[1]);\n\n\t\tfor (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)\n\t\t\tsetdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);\n\n\t\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);\n\n\t\tif ((addr + cnts) > max_available_len) {\n\t\t\tRTW_INFO(\"%s: addr(0x%X)+cnts(%d) parameter error!\\n\", __FUNCTION__, addr, cnts);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_efuse_map_write error!!\\n\", __FUNCTION__);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\t} else if (strcmp(tmp[0], \"vidpid\") == 0) {\n\t\tif (tmp[1] == NULL) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* pidvid,da0b7881\t\t */\n#ifdef CONFIG_RTL8188E\n#ifdef CONFIG_USB_HCI\n\t\taddr = EEPROM_VID_88EU;\n#endif\n#ifdef CONFIG_PCI_HCI\n\t\taddr = EEPROM_VID_88EE;\n#endif\n#endif /* CONFIG_RTL8188E */\n\n#ifdef CONFIG_RTL8192E\n#ifdef CONFIG_USB_HCI\n\t\taddr = EEPROM_VID_8192EU;\n#endif\n#ifdef CONFIG_PCI_HCI\n\t\taddr = EEPROM_VID_8192EE;\n#endif\n#endif /* CONFIG_RTL8188E */\n\n#ifdef CONFIG_RTL8723B\n\t\taddr = EEPROM_VID_8723BU;\n#endif\n\n#ifdef CONFIG_RTL8188F\n\t\taddr = EEPROM_VID_8188FU;\n#endif\n\n#ifdef CONFIG_RTL8188GTV\n\t\taddr = EEPROM_VID_8188GTVU;\n#endif\n\n#ifdef CONFIG_RTL8703B\n#ifdef CONFIG_USB_HCI\n\t\taddr = EEPROM_VID_8703BU;\n#endif /* CONFIG_USB_HCI */\n#endif /* CONFIG_RTL8703B */\n\n#ifdef CONFIG_RTL8723D\n#ifdef CONFIG_USB_HCI\n\t\taddr = EEPROM_VID_8723DU;\n#endif /* CONFIG_USB_HCI */\n#endif /* CONFIG_RTL8723D */\n\n\t\tcnts = strlen(tmp[1]);\n\t\tif (cnts % 2) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tcnts /= 2;\n\t\tif (cnts == 0) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tRTW_INFO(\"%s: addr=0x%X\\n\", __FUNCTION__, addr);\n\t\tRTW_INFO(\"%s: cnts=%d\\n\", __FUNCTION__, cnts);\n\t\tRTW_INFO(\"%s: VID/PID=%s\\n\", __FUNCTION__, tmp[1]);\n\n\t\tfor (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)\n\t\t\tsetdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);\n\n\t\tEFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);\n\t\tif ((addr + cnts) > max_available_len) {\n\t\t\tRTW_INFO(\"%s: addr(0x%X)+cnts(%d) parameter error!\\n\", __FUNCTION__, addr, cnts);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_efuse_map_write error!!\\n\", __FUNCTION__);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\t} else if (strcmp(tmp[0], \"wldumpfake\") == 0) {\n\t\tif (wifimaplen > EFUSE_MAX_MAP_LEN)\n\t\t\tcnts = EFUSE_MAX_MAP_LEN;\n\t\telse\n\t\t\tcnts = wifimaplen;\n\t\tif (rtw_efuse_mask_map_read(padapter, 0, cnts, pEfuseHal->fakeEfuseModifiedMap) == _SUCCESS)\n\t\t\tRTW_INFO(\"%s: WiFi hw efuse dump to Fake map success\\n\", __func__);\n\t\telse {\n\t\t\tRTW_INFO(\"%s: WiFi hw efuse dump to Fake map Fail\\n\", __func__);\n\t\t\terr = -EFAULT;\n\t\t}\n\t} else if (strcmp(tmp[0], \"btwmap\") == 0) {\n\t\trtw_write8(padapter, 0xa3, 0x05); /* For 8723AB ,8821S ? */\n\t\tBTStatus = rtw_read8(padapter, 0xa0);\n\t\tRTW_INFO(\"%s: btwmap before read 0xa0 BT Status =0x%x\\n\", __FUNCTION__, BTStatus);\n\t\tif (BTStatus != 0x04) {\n\t\t\tsprintf(extra, \"BT Status not Active ,can't do Write\\n\");\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif ((tmp[1] == NULL) || (tmp[2] == NULL)) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n#ifndef RTW_HALMAC\n\t\tBTEfuse_PowerSwitch(padapter, 1, _TRUE);\n\t\taddr = 0x1ff;\n\t\trtw_write8(padapter, EFUSE_CTRL + 1, (addr & 0xff));\n\t\trtw_msleep_os(10);\n\t\trtw_write8(padapter, EFUSE_CTRL + 2, ((addr >> 8) & 0x03));\n\t\trtw_msleep_os(10);\n\t\trtw_write8(padapter, EFUSE_CTRL + 3, 0x72);\n\t\trtw_msleep_os(10);\n\t\trtw_read8(padapter, EFUSE_CTRL);\n\t\tBTEfuse_PowerSwitch(padapter, 1, _FALSE);\n#endif /* RTW_HALMAC */\n\n\t\taddr = simple_strtoul(tmp[1], &ptmp, 16);\n\t\taddr &= 0xFFF;\n\n\t\tcnts = strlen(tmp[2]);\n\t\tif (cnts % 2) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tcnts /= 2;\n\t\tif (cnts == 0) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tRTW_INFO(\"%s: addr=0x%X\\n\", __FUNCTION__, addr);\n\t\tRTW_INFO(\"%s: cnts=%d\\n\", __FUNCTION__, cnts);\n\t\tRTW_INFO(\"%s: BT data=%s\\n\", __FUNCTION__, tmp[2]);\n\n\t\tfor (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)\n\t\t\tsetdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);\n#ifndef RTW_HALMAC\n\t\tEFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);\n\t\tif ((addr + cnts) > max_available_len) {\n\t\t\tRTW_INFO(\"%s: addr(0x%X)+cnts(%d) parameter error!\\n\", __FUNCTION__, addr, cnts);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n#endif\n\t\tif (rtw_BT_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_BT_efuse_map_write error!!\\n\", __FUNCTION__);\n\t\t\tsprintf(extra, \"BT write FAIL !!!\\n\");\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\t\t*extra = 0;\n\t\tRTW_INFO(\"%s: after rtw_BT_efuse_map_write to _rtw_memcmp\\n\", __FUNCTION__);\n\t\tif ((rtw_BT_efuse_map_read(padapter, addr, cnts, ShadowMapBT) == _SUCCESS)) {\n\t\t\tif (_rtw_memcmp((void *)ShadowMapBT , (void *)setdata, cnts)) {\n\t\t\t\tRTW_INFO(\"%s: BT write map compare OK BTStatus=0x%x\\n\", __FUNCTION__, BTStatus);\n\t\t\t\tsprintf(extra, \"BT write map compare OK\");\n\t\t\t\terr = 0;\n\t\t\t\tgoto exit;\n\t\t\t} else {\n\t\t\t\tsprintf(extra, \"BT write map compare FAIL\");\n\t\t\t\tRTW_INFO(\"%s: BT write map compare FAIL BTStatus=0x%x\\n\", __FUNCTION__, BTStatus);\n\t\t\t\terr = 0;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\t} else if (strcmp(tmp[0], \"btwfake\") == 0) {\n\t\tif ((tmp[1] == NULL) || (tmp[2] == NULL)) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tif (pmp_priv->bprocess_mp_mode != _TRUE) {\n\t\t\tRTW_INFO(\"%s: btwfake not to be exec, please first to mp_start\\n\", __FUNCTION__);\n\t\t\tsprintf(extra, \"Error, btwfake cant to be exec, please first to mp_start !!!!\\n\");\n\t\t\terr = 0;\n\t\t\tgoto exit;\n\t\t}\n\t\taddr = simple_strtoul(tmp[1], &ptmp, 16);\n\t\taddr &= 0xFFF;\n\n\t\tcnts = strlen(tmp[2]);\n\t\tif (cnts % 2) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tcnts /= 2;\n\t\tif (cnts == 0) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tRTW_INFO(\"%s: addr=0x%X\\n\", __FUNCTION__, addr);\n\t\tRTW_INFO(\"%s: cnts=%d\\n\", __FUNCTION__, cnts);\n\t\tRTW_INFO(\"%s: BT tmp data=%s\\n\", __FUNCTION__, tmp[2]);\n\n\t\tfor (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)\n\t\t\tpEfuseHal->fakeBTEfuseModifiedMap[addr + jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);\n\t} else if (strcmp(tmp[0], \"btdumpfake\") == 0) {\n\t\tif (rtw_BT_efuse_map_read(padapter, 0, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _SUCCESS)\n\t\t\tRTW_INFO(\"%s: BT read all map success\\n\", __FUNCTION__);\n\t\telse {\n\t\t\tRTW_INFO(\"%s: BT read all map Fail!\\n\", __FUNCTION__);\n\t\t\terr = -EFAULT;\n\t\t}\n\t} else if (strcmp(tmp[0], \"btfk2map\") == 0) {\n\n\t\tif (padapter->registrypriv.bBTFileMaskEfuse != _TRUE && pmp_priv->bloadBTefusemap == _TRUE) {\n\t\t\tRTW_INFO(\"%s: File BT eFuse mask file not to be loaded\\n\", __FUNCTION__);\n\t\t\tsprintf(extra, \"Not load BT eFuse mask file yet, Please advance to use [ efuse_bt_mask ], now remove the Adapter.!!!!\\n\");\n\t\t\trtw_set_surprise_removed(padapter);\n\t\t\terr = 0;\n\t\t\tgoto exit;\n\t\t}\n\t\n\t\trtw_write8(padapter, 0xa3, 0x05);\n\t\tBTStatus = rtw_read8(padapter, 0xa0);\n\t\tRTW_INFO(\"%s: btwmap before read 0xa0 BT Status =0x%x\\n\", __FUNCTION__, BTStatus);\n\t\tif (BTStatus != 0x04) {\n\t\t\tsprintf(extra, \"BT Status not Active Write FAIL\\n\");\n\t\t\tgoto exit;\n\t\t}\n\t\tif (pmp_priv->bprocess_mp_mode != _TRUE) {\n\t\t\tRTW_INFO(\"%s: btfk2map not to be exec, please first to mp_start\\n\", __FUNCTION__);\n\t\t\tsprintf(extra, \"Error, btfk2map cant to be exec, please first to mp_start !!!!\\n\");\n\t\t\terr = 0;\n\t\t\tgoto exit;\n\t\t}\n#ifndef RTW_HALMAC\n\t\tBTEfuse_PowerSwitch(padapter, 1, _TRUE);\n\t\taddr = 0x1ff;\n\t\trtw_write8(padapter, EFUSE_CTRL + 1, (addr & 0xff));\n\t\trtw_msleep_os(10);\n\t\trtw_write8(padapter, EFUSE_CTRL + 2, ((addr >> 8) & 0x03));\n\t\trtw_msleep_os(10);\n\t\trtw_write8(padapter, EFUSE_CTRL + 3, 0x72);\n\t\trtw_msleep_os(10);\n\t\trtw_read8(padapter, EFUSE_CTRL);\n\t\tBTEfuse_PowerSwitch(padapter, 1, _FALSE);\n#endif /* RTW_HALMAC */\n\t\t_rtw_memcpy(pEfuseHal->BTEfuseModifiedMap, pEfuseHal->fakeBTEfuseModifiedMap, EFUSE_BT_MAX_MAP_LEN);\n\n\t\tif (rtw_BT_efuse_map_write(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_BT_efuse_map_write error!\\n\", __FUNCTION__);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tRTW_INFO(\"pEfuseHal->fakeBTEfuseModifiedMap OFFSET\\tVALUE(hex)\\n\");\n\t\tfor (i = 0; i < EFUSE_BT_MAX_MAP_LEN; i += 16) {\n\t\t\tprintk(\"0x%02x\\t\", i);\n\t\t\tfor (j = 0; j < 8; j++)\n\t\t\t\tprintk(\"%02X \", pEfuseHal->fakeBTEfuseModifiedMap[i + j]);\n\t\t\tprintk(\"\\t\");\n\n\t\t\tfor (; j < 16; j++)\n\t\t\t\tprintk(\"%02X \", pEfuseHal->fakeBTEfuseModifiedMap[i + j]);\n\t\t\tprintk(\"\\n\");\n\t\t}\n\t\tprintk(\"\\n\");\n#if 1\n\t\terr = -EFAULT;\n\t\tRTW_INFO(\"%s: rtw_BT_efuse_map_read _rtw_memcmp\\n\", __FUNCTION__);\n\t\tif ((rtw_BT_efuse_map_read(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseInitMap) == _SUCCESS)) {\n\t\t\tif (_rtw_memcmp((void *)pEfuseHal->fakeBTEfuseModifiedMap, (void *)pEfuseHal->fakeBTEfuseInitMap, EFUSE_BT_MAX_MAP_LEN)) {\n\t\t\t\tsprintf(extra, \"BT write map compare OK\");\n\t\t\t\tRTW_INFO(\"%s: BT write map afterf compare success BTStatus=0x%x\\n\", __FUNCTION__, BTStatus);\n\t\t\t\terr = 0;\n\t\t\t\tgoto exit;\n\t\t\t} else {\n\t\t\t\tsprintf(extra, \"BT write map compare FAIL\");\n\t\t\t\tif (rtw_BT_efuse_map_write(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _FAIL)\n\t\t\t\t\tRTW_INFO(\"%s: rtw_BT_efuse_map_write compare error,retry = %d!\\n\", __FUNCTION__, i);\n\n\t\t\t\tif (rtw_BT_efuse_map_read(padapter, EFUSE_BT, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseInitMap) == _SUCCESS) {\n\t\t\t\t\tRTW_INFO(\"pEfuseHal->fakeBTEfuseInitMap OFFSET\\tVALUE(hex)\\n\");\n\n\t\t\t\t\tfor (i = 0; i < EFUSE_BT_MAX_MAP_LEN; i += 16) {\n\t\t\t\t\t\tprintk(\"0x%02x\\t\", i);\n\t\t\t\t\t\tfor (j = 0; j < 8; j++)\n\t\t\t\t\t\t\tprintk(\"%02X \", pEfuseHal->fakeBTEfuseInitMap[i + j]);\n\t\t\t\t\t\tprintk(\"\\t\");\n\t\t\t\t\t\tfor (; j < 16; j++)\n\t\t\t\t\t\t\tprintk(\"%02X \", pEfuseHal->fakeBTEfuseInitMap[i + j]);\n\t\t\t\t\t\tprintk(\"\\n\");\n\t\t\t\t\t}\n\t\t\t\t\tprintk(\"\\n\");\n\t\t\t\t}\n\t\t\t\tRTW_INFO(\"%s: BT write map afterf compare not match to write efuse try write Map again , BTStatus=0x%x\\n\", __FUNCTION__, BTStatus);\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n#endif\n\n\t} else if (strcmp(tmp[0], \"wlfk2map\") == 0) {\n\t\t*extra = 0;\n\n\t\tif (padapter->registrypriv.bFileMaskEfuse != _TRUE && pmp_priv->bloadefusemap == _TRUE) {\n\t\t\tRTW_INFO(\"%s: File eFuse mask file not to be loaded\\n\", __FUNCTION__);\n\t\t\tsprintf(extra, \"Not load eFuse mask file yet, Please use the efuse_mask CMD, now remove the interface !!!!\\n\");\n\t\t\trtw_set_surprise_removed(padapter);\n\t\t\terr = 0;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (pmp_priv->bprocess_mp_mode != _TRUE) {\n\t\t\tRTW_INFO(\"%s: wlfk2map not to be exec, please first to mp_start\\n\", __FUNCTION__);\n\t\t\tsprintf(extra, \"Error, wlfk2map cant to be exec, please first to mp_start !!!!\\n\");\n\t\t\terr = 0;\n\t\t\tgoto exit;\n\t\t}\n\t\tif (wifimaplen > EFUSE_MAX_MAP_LEN)\n\t\t\tcnts = EFUSE_MAX_MAP_LEN;\n\t\telse\n\t\t\tcnts = wifimaplen;\n\t\tif (rtw_efuse_map_write(padapter, 0x00, cnts, pEfuseHal->fakeEfuseModifiedMap) == _FAIL) {\n\t\t\tRTW_INFO(\"%s: rtw_efuse_map_write fakeEfuseModifiedMap error!\\n\", __FUNCTION__);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (rtw_efuse_mask_map_read(padapter, 0x00, wifimaplen, ShadowMapWiFi) == _SUCCESS) {\n\t\t\taddr = 0x00;\n\t\t\terr = _TRUE;\n\n\t\t\tfor (i = 0; i < cnts; i++) {\n\t\t\t\tif (padapter->registrypriv.boffefusemask == 0) {\n\t\t\t\t\tif (padapter->registrypriv.bFileMaskEfuse == _TRUE) {\n\t\t\t\t\t\tif (rtw_file_efuse_IsMasked(padapter, addr + i, maskfileBuffer) == _TRUE)\t/*use file efuse mask. */\n\t\t\t\t\t\t\tbcmpchk = _FALSE;\n\t\t\t\t\t} else {\n\t\t\t\t\t\tif (efuse_IsMasked(padapter, addr + i) == _TRUE)\n\t\t\t\t\t\t\tbcmpchk = _FALSE;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif (bcmpchk == _TRUE) {\n\t\t\t\t\tRTW_INFO(\"compare readMapWiFi[0x%02x] = %x, ModifiedMap = %x\\n\", addr + i, ShadowMapWiFi[ addr + i], pEfuseHal->fakeEfuseModifiedMap[addr + i]);\n\t\t\t\t\tif (_rtw_memcmp((void *) &ShadowMapWiFi[addr + i], (void *)&pEfuseHal->fakeEfuseModifiedMap[addr + i], 1) == _FALSE){\n\t\t\t\t\t\terr = _FALSE;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tbcmpchk = _TRUE;\n\t\t\t}\n\t\t}\n\n\t\tif (err) {\n\t\t\tRTW_INFO(\"%s: WiFi write map afterf compare OK\\n\", __FUNCTION__);\n\t\t\tsprintf(extra, \"WiFi write map compare OK\\n\");\n\t\t\terr = 0;\n\t\t\tgoto exit;\n\t\t} else {\n\t\t\tsprintf(extra, \"WiFi write map compare FAIL\\n\");\n\t\t\tRTW_INFO(\"%s: WiFi write map compare Fail\\n\", __FUNCTION__);\n\t\t\terr = 0;\n\t\t\tgoto exit;\n\t\t}\n\t} else if (strcmp(tmp[0], \"wlwfake\") == 0) {\n\t\tif ((tmp[1] == NULL) || (tmp[2] == NULL)) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tif (pmp_priv->bprocess_mp_mode != _TRUE) {\n\t\t\tRTW_INFO(\"%s: wlwfake not to be exec, please first to mp_start\\n\", __FUNCTION__);\n\t\t\tsprintf(extra, \"Error, wlwfake cant to be exec, please first to mp_start !!!!\\n\");\n\t\t\terr = 0;\n\t\t\tgoto exit;\n\t\t}\n\t\taddr = simple_strtoul(tmp[1], &ptmp, 16);\n\t\taddr &= 0xFFF;\n\n\t\tcnts = strlen(tmp[2]);\n\t\tif (cnts % 2) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tcnts /= 2;\n\t\tif (cnts == 0) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tRTW_INFO(\"%s: addr=0x%X\\n\", __FUNCTION__, addr);\n\t\tRTW_INFO(\"%s: cnts=%d\\n\", __FUNCTION__, cnts);\n\t\tRTW_INFO(\"%s: map tmp data=%s\\n\", __FUNCTION__, tmp[2]);\n\n\t\tfor (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)\n\t\t\tpEfuseHal->fakeEfuseModifiedMap[addr + jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);\n\t\t_rtw_memset(extra, '\\0', strlen(extra));\n\t\tsprintf(extra, \"wlwfake OK\\n\");\n\n\t}\n\telse if (strcmp(tmp[0], \"wfakemac\") == 0) {\n\t\tif (tmp[1] == NULL) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tif (pmp_priv->bprocess_mp_mode != _TRUE) {\n\t\t\tRTW_INFO(\"%s: wfakemac not to be exec, please first to mp_start\\n\", __FUNCTION__);\n\t\t\tsprintf(extra, \"Error, wfakemac cant to be exec, please first to mp_start !!!!\\n\");\n\t\t\terr = 0;\n\t\t\tgoto exit;\n\t\t}\n\t\t/* wfakemac,00e04c871200 */\n\t\tif (hal_efuse_macaddr_offset(padapter) == -1) {\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\taddr = hal_efuse_macaddr_offset(padapter);\n\t\tcnts = strlen(tmp[1]);\n\t\tif (cnts % 2) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tcnts /= 2;\n\t\tif (cnts == 0) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tif (cnts > 6) {\n\t\t\tRTW_INFO(\"%s: error data for mac addr=\\\"%s\\\"\\n\", __FUNCTION__, tmp[1]);\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tRTW_INFO(\"%s: addr=0x%X\\n\", __FUNCTION__, addr);\n\t\tRTW_INFO(\"%s: cnts=%d\\n\", __FUNCTION__, cnts);\n\t\tRTW_INFO(\"%s: MAC address=%s\\n\", __FUNCTION__, tmp[1]);\n\n\t\tfor (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)\n\t\t\tpEfuseHal->fakeEfuseModifiedMap[addr + jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);\n\n\t\t_rtw_memset(extra, '\\0', strlen(extra));\n\t\tsprintf(extra, \"write mac addr to fake map OK\\n\");\n\t} else if(strcmp(tmp[0], \"update\") == 0) {\n\t\tRTW_INFO(\"To Use new eFuse map\\n\");\n\t\t/*step read efuse/eeprom data and get mac_addr*/\n\t\trtw_hal_read_chip_info(padapter);\n\t\t/* set mac addr*/\n\t\trtw_macaddr_cfg(adapter_mac_addr(padapter), get_hal_mac_addr(padapter));\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0)\n\t\t_rtw_memcpy(padapter->pnetdev->dev_addr, get_hal_mac_addr(padapter), ETH_ALEN); /* set mac addr to net_device */\n#else\n\t\tdev_addr_set(padapter->pnetdev, get_hal_mac_addr(padapter)); /* set mac addr to net_device */\n#endif\n\n#ifdef CONFIG_P2P\n\t\trtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));\n#endif\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\t\trtw_hal_change_macaddr_mbid(padapter, adapter_mac_addr(padapter));\n#else\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */\n#endif\n\t\t/*pHalFunc->hal_deinit(padapter);*/\n\t\tif (pHalFunc->hal_init(padapter) == _FAIL) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\t_rtw_memset(extra, '\\0', strlen(extra));\n\t\tsprintf(extra, \"eFuse Update OK\\n\");\n\t} else if (strcmp(tmp[0], \"analyze\") == 0) {\n\n\t\trtw_efuse_analyze(padapter, EFUSE_WIFI, 0);\n\t\t_rtw_memset(extra, '\\0', strlen(extra));\n\t\tsprintf(extra, \"eFuse Analyze OK,please to check kernel log\\n\");\n\t}\nexit:\n\tif (setdata)\n\t\trtw_mfree(setdata, 1024);\n\tif (ShadowMapBT)\n\t\trtw_mfree(ShadowMapBT, EFUSE_BT_MAX_MAP_LEN);\n\tif (ShadowMapWiFi)\n\t\trtw_mfree(ShadowMapWiFi, wifimaplen);\n\tif (setrawdata)\n\t\trtw_mfree(setrawdata, EFUSE_MAX_SIZE);\n\n\twrqu->length = strlen(extra);\n\n\tif (padapter->registrypriv.mp_mode == 0) {\n#ifdef CONFIG_IPS\n\t\trtw_pm_set_ips(padapter, ips_mode);\n#endif /* CONFIG_IPS */\n\n#ifdef CONFIG_LPS\n\t\trtw_pm_set_lps(padapter, lps_mode);\n#endif /* CONFIG_LPS */\n\t}\n\n\treturn err;\n}\n\n#ifdef CONFIG_RTW_CUSTOMER_STR\nstatic int rtw_mp_customer_str(\n\tstruct net_device *dev,\n\tstruct iw_request_info *info,\n\tunion iwreq_data *wrqu, char *extra)\n{\n\t_adapter *adapter = rtw_netdev_priv(dev);\n\tu32 len;\n\tu8 *pbuf = NULL, *pch;\n\tchar *ptmp;\n\tu8 param[RTW_CUSTOMER_STR_LEN];\n\tu8 count = 0;\n\tu8 tmp;\n\tu8 i;\n\tu32 pos;\n\tu8 ret;\n\tu8 read = 0;\n\n\tif (adapter->registrypriv.mp_mode != 1\n\t\t|| !adapter->registrypriv.mp_customer_str)\n\t\treturn -EFAULT;\n\n\tlen = wrqu->data.length + 1;\n\n\tpbuf = (u8 *)rtw_zmalloc(len);\n\tif (pbuf == NULL) {\n\t\tRTW_WARN(\"%s: no memory!\\n\", __func__);\n\t\treturn -ENOMEM;\n\t}\n\n\tif (copy_from_user(pbuf, wrqu->data.pointer, wrqu->data.length)) {\n\t\trtw_mfree(pbuf, len);\n\t\tRTW_WARN(\"%s: copy from user fail!\\n\", __func__);\n\t\treturn -EFAULT;\n\t}\n\tRTW_INFO(\"%s: string=\\\"%s\\\"\\n\", __func__, pbuf);\n\n\tptmp = (char *)pbuf;\n\tpch = strsep(&ptmp, \",\");\n\tif ((pch == NULL) || (strlen(pch) == 0)) {\n\t\trtw_mfree(pbuf, len);\n\t\tRTW_INFO(\"%s: parameter error(no cmd)!\\n\", __func__);\n\t\treturn -EFAULT;\n\t}\n\n\t_rtw_memset(param, 0xFF, RTW_CUSTOMER_STR_LEN);\n\n\tif (strcmp(pch, \"read\") == 0) {\n\t\tread = 1;\n\t\tret = rtw_hal_customer_str_read(adapter, param);\n\n\t} else if (strcmp(pch, \"write\") == 0) {\n\t\tdo {\n\t\t\tpch = strsep(&ptmp, \":\");\n\t\t\tif ((pch == NULL) || (strlen(pch) == 0))\n\t\t\t\tbreak;\n\t\t\tif (strlen(pch) != 2\n\t\t\t\t|| IsHexDigit(*pch) == _FALSE\n\t\t\t\t|| IsHexDigit(*(pch + 1)) == _FALSE\n\t\t\t\t|| sscanf(pch, \"%hhx\", &tmp) != 1\n\t\t\t) {\n\t\t\t\tRTW_WARN(\"%s: invalid 8-bit hex!\\n\", __func__);\n\t\t\t\trtw_mfree(pbuf, len);\n\t\t\t\treturn -EFAULT;\n\t\t\t}\n\n\t\t\tparam[count++] = tmp;\n\n\t\t} while (count < RTW_CUSTOMER_STR_LEN);\n\n\t\tif (count == 0) {\n\t\t\trtw_mfree(pbuf, len);\n\t\t\tRTW_WARN(\"%s: no input!\\n\", __func__);\n\t\t\treturn -EFAULT;\n\t\t}\n\t\tret = rtw_hal_customer_str_write(adapter, param);\n\t} else {\n\t\trtw_mfree(pbuf, len);\n\t\tRTW_INFO(\"%s: parameter error(unknown cmd)!\\n\", __func__);\n\t\treturn -EFAULT;\n\t}\n\n\tpos = sprintf(extra, \"%s: \", read ? \"read\" : \"write\");\n\tif (read == 0 || ret == _SUCCESS) {\n\t\tfor (i = 0; i < RTW_CUSTOMER_STR_LEN; i++)\n\t\t\tpos += sprintf(extra + pos, \"%02x:\", param[i]);\n\t\textra[pos] = 0;\n\t\tpos--;\n\t}\n\tpos += sprintf(extra + pos, \" %s\", ret == _SUCCESS ? \"OK\" : \"FAIL\");\n\n\twrqu->data.length = strlen(extra) + 1;\n\n\trtw_mfree(pbuf, len);\n\treturn 0;\n}\n#endif /* CONFIG_RTW_CUSTOMER_STR */\n\nstatic int rtw_priv_mp_set(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wdata, char *extra)\n{\n\n\tstruct iw_point *wrqu = (struct iw_point *)wdata;\n\tu32 subcmd = wrqu->flags;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tint status = 0;\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (!is_primary_adapter(padapter)) {\n\t\tRTW_INFO(\"MP mode only primary Adapter support\\n\");\n\t\treturn -EIO;\n\t}\n#endif\n\n\tRTW_INFO(\"%s mutx in %d\\n\", __func__, subcmd);\n\t_enter_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL);\n\tswitch (subcmd) {\n\tcase CTA_TEST:\n\t\tRTW_INFO(\"set CTA_TEST\\n\");\n\t\tstatus = rtw_cta_test_start(dev, info, wdata, extra);\n\t\tbreak;\n\tcase MP_DISABLE_BT_COEXIST:\n\t\tRTW_INFO(\"set case MP_DISABLE_BT_COEXIST\\n\");\n\t\tstatus = rtw_mp_disable_bt_coexist(dev, info, wdata, extra);\n\t\tbreak;\n\tcase MP_IQK:\n\t\tRTW_INFO(\"set MP_IQK\\n\");\n\t\tstatus = rtw_mp_iqk(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_LCK:\n\t\tRTW_INFO(\"set MP_LCK\\n\");\n\t\tstatus = rtw_mp_lck(dev, info, wrqu, extra);\n\tbreak;\n\n\tdefault:\n\t\tstatus = -EIO;\n\t}\n\t_exit_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL);\n\tRTW_INFO(\"%s mutx done %d\\n\", __func__, subcmd);\n\n\treturn status;\n}\n\nstatic int rtw_priv_mp_get(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wdata, char *extra)\n{\n\n\tstruct iw_point *wrqu = (struct iw_point *)wdata;\n\tu32 subcmd = wrqu->flags;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tint status = 0;\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (!is_primary_adapter(padapter)) {\n\t\tRTW_INFO(\"MP mode only primary Adapter support\\n\");\n\t\treturn -EIO;\n\t}\n#endif\n\n\tRTW_INFO(\"%s mutx in %d\\n\", __func__, subcmd);\n\t_enter_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL);\n\n\tswitch (subcmd) {\n\tcase MP_START:\n\t\tRTW_INFO(\"set case mp_start\\n\");\n\t\tstatus = rtw_mp_start(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_STOP:\n\t\tRTW_INFO(\"set case mp_stop\\n\");\n\t\tstatus = rtw_mp_stop(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_BANDWIDTH:\n\t\tRTW_INFO(\"set case mp_bandwidth\\n\");\n\t\tstatus = rtw_mp_bandwidth(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_RESET_STATS:\n\t\tRTW_INFO(\"set case MP_RESET_STATS\\n\");\n\t\tstatus = rtw_mp_reset_stats(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_SetRFPathSwh:\n\t\tRTW_INFO(\"set MP_SetRFPathSwitch\\n\");\n\t\tstatus = rtw_mp_SetRFPath(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase WRITE_REG:\n\t\tstatus = rtw_mp_write_reg(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase WRITE_RF:\n\t\tstatus = rtw_mp_write_rf(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_PHYPARA:\n\t\tRTW_INFO(\"mp_get  MP_PHYPARA\\n\");\n\t\tstatus = rtw_mp_phypara(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_CHANNEL:\n\t\tRTW_INFO(\"set case mp_channel\\n\");\n\t\tstatus = rtw_mp_channel(dev , info, wrqu, extra);\n\t\tbreak;\n\tcase  MP_CHL_OFFSET:\n\t\tRTW_INFO(\"set case mp_ch_offset\\n\");\n\t\tstatus = rtw_mp_ch_offset(dev , info, wrqu, extra);\n\t\tbreak;\n\tcase READ_REG:\n\t\tRTW_INFO(\"mp_get  READ_REG\\n\");\n\t\tstatus = rtw_mp_read_reg(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase READ_RF:\n\t\tRTW_INFO(\"mp_get  READ_RF\\n\");\n\t\tstatus = rtw_mp_read_rf(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_RATE:\n\t\tRTW_INFO(\"set case mp_rate\\n\");\n\t\tstatus = rtw_mp_rate(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_TXPOWER:\n\t\tRTW_INFO(\"set case MP_TXPOWER\\n\");\n\t\tstatus = rtw_mp_txpower(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_ANT_TX:\n\t\tRTW_INFO(\"set case MP_ANT_TX\\n\");\n\t\tstatus = rtw_mp_ant_tx(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_ANT_RX:\n\t\tRTW_INFO(\"set case MP_ANT_RX\\n\");\n\t\tstatus = rtw_mp_ant_rx(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_QUERY:\n\t\tstatus = rtw_mp_trx_query(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_CTX:\n\t\tRTW_INFO(\"set case MP_CTX\\n\");\n\t\tstatus = rtw_mp_ctx(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_ARX:\n\t\tRTW_INFO(\"set case MP_ARX\\n\");\n\t\tstatus = rtw_mp_arx(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_DUMP:\n\t\tRTW_INFO(\"set case MP_DUMP\\n\");\n\t\tstatus = rtw_mp_dump(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_PSD:\n\t\tRTW_INFO(\"set case MP_PSD\\n\");\n\t\tstatus = rtw_mp_psd(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_THER:\n\t\tRTW_INFO(\"set case MP_THER\\n\");\n\t\tstatus = rtw_mp_thermal(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_PwrCtlDM:\n\t\tRTW_INFO(\"set MP_PwrCtlDM\\n\");\n\t\tstatus = rtw_mp_PwrCtlDM(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_QueryDrvStats:\n\t\tRTW_INFO(\"mp_get MP_QueryDrvStats\\n\");\n\t\tstatus = rtw_mp_QueryDrv(dev, info, wdata, extra);\n\t\tbreak;\n\tcase MP_PWRTRK:\n\t\tRTW_INFO(\"set case MP_PWRTRK\\n\");\n\t\tstatus = rtw_mp_pwrtrk(dev, info, wrqu, extra);\n\t\tbreak;\n#ifdef CONFIG_MP_INCLUDED\n\tcase EFUSE_SET:\n\t\tRTW_INFO(\"set case efuse set\\n\");\n\t\tstatus = rtw_mp_efuse_set(dev, info, wdata, extra);\n\t\tbreak;\n#endif\n\tcase EFUSE_GET:\n\t\tRTW_INFO(\"efuse get EFUSE_GET\\n\");\n\t\tstatus = rtw_mp_efuse_get(dev, info, wdata, extra);\n\t\tbreak;\n\tcase MP_GET_TXPOWER_INX:\n\t\tRTW_INFO(\"mp_get MP_GET_TXPOWER_INX\\n\");\n\t\tstatus = rtw_mp_txpower_index(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_GETVER:\n\t\tRTW_INFO(\"mp_get MP_GETVER\\n\");\n\t\tstatus = rtw_mp_getver(dev, info, wdata, extra);\n\t\tbreak;\n\tcase MP_MON:\n\t\tRTW_INFO(\"mp_get MP_MON\\n\");\n\t\tstatus = rtw_mp_mon(dev, info, wdata, extra);\n\t\tbreak;\n\tcase EFUSE_BT_MASK:\n\t\tRTW_INFO(\"mp_get EFUSE_BT_MASK\\n\");\n\t\tstatus = rtw_bt_efuse_mask_file(dev, info, wdata, extra);\n\t\tbreak;\n\tcase EFUSE_MASK:\n\t\tRTW_INFO(\"mp_get EFUSE_MASK\\n\");\n\t\tstatus = rtw_efuse_mask_file(dev, info, wdata, extra);\n\t\tbreak;\n\tcase  EFUSE_FILE:\n\t\tRTW_INFO(\"mp_get EFUSE_FILE\\n\");\n\t\tstatus = rtw_efuse_file_map(dev, info, wdata, extra);\n\t\tbreak;\n\tcase  MP_TX:\n\t\tRTW_INFO(\"mp_get MP_TX\\n\");\n\t\tstatus = rtw_mp_tx(dev, info, wdata, extra);\n\t\tbreak;\n\tcase  MP_RX:\n\t\tRTW_INFO(\"mp_get MP_RX\\n\");\n\t\tstatus = rtw_mp_rx(dev, info, wdata, extra);\n\t\tbreak;\n\tcase MP_HW_TX_MODE:\n\t\tRTW_INFO(\"mp_get MP_HW_TX_MODE\\n\");\n\t\tstatus = rtw_mp_hwtx(dev, info, wdata, extra);\n\t\tbreak;\n#ifdef CONFIG_RTW_CUSTOMER_STR\n\tcase MP_CUSTOMER_STR:\n\t\tRTW_INFO(\"customer str\\n\");\n\t\tstatus = rtw_mp_customer_str(dev, info, wdata, extra);\n\t\tbreak;\n#endif\n\tcase MP_PWRLMT:\n\t\tRTW_INFO(\"mp_get MP_SETPWRLMT\\n\");\n\t\tstatus = rtw_mp_pwrlmt(dev, info, wdata, extra);\n\t\tbreak;\n\tcase MP_PWRBYRATE:\n\t\tRTW_INFO(\"mp_get MP_SETPWRBYRATE\\n\");\n\t\tstatus = rtw_mp_pwrbyrate(dev, info, wdata, extra);\n\t\tbreak;\n\tcase  BT_EFUSE_FILE:\n\t\tRTW_INFO(\"mp_get BT EFUSE_FILE\\n\");\n\t\tstatus = rtw_bt_efuse_file_map(dev, info, wdata, extra);\n\t\tbreak;\n\tcase MP_SWRFPath:\n\t\tRTW_INFO(\"mp_get MP_SWRFPath\\n\");\n\t\tstatus = rtw_mp_switch_rf_path(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_LINK:\n\t\tRTW_INFO(\"mp_get MP_LINK\\n\");\n\t\tstatus = rtw_mp_link(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_DPK_TRK:\n\t\tRTW_INFO(\"mp_get MP_DPK_TRK\\n\");\n\t\tstatus = rtw_mp_dpk_track(dev, info, wdata, extra);\n\t\tbreak;\n\tcase MP_DPK:\n\t\tRTW_INFO(\"set MP_DPK\\n\");\n\t\tstatus = rtw_mp_dpk(dev, info, wdata, extra);\n\tdefault:\n\t\tstatus = -EIO;\n\t}\n\n\t_exit_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL);\n\tRTW_INFO(\"%s mutx done_%d\\n\", __func__, subcmd);\n\n\treturn status;\n}\n#endif /*#if defined(CONFIG_MP_INCLUDED)*/\n\n\n#ifdef CONFIG_SDIO_INDIRECT_ACCESS\n#define DBG_MP_SDIO_INDIRECT_ACCESS 1\nstatic int rtw_mp_sd_iread(struct net_device *dev\n\t\t\t   , struct iw_request_info *info\n\t\t\t   , struct iw_point *wrqu\n\t\t\t   , char *extra)\n{\n\tchar input[16];\n\tu8 width;\n\tunsigned long addr;\n\tu32 ret = 0;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\n\tif (wrqu->length > 16) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" wrqu->length:%d\\n\", FUNC_ADPT_ARG(padapter), wrqu->length);\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" copy_from_user fail\\n\", FUNC_ADPT_ARG(padapter));\n\t\tret = -EFAULT;\n\t\tgoto exit;\n\t}\n\n\t_rtw_memset(extra, 0, wrqu->length);\n\n\tif (sscanf(input, \"%hhu,%lx\", &width, &addr) != 2) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" sscanf fail\\n\", FUNC_ADPT_ARG(padapter));\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\n\tif (addr > 0x3FFF) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" addr:0x%lx\\n\", FUNC_ADPT_ARG(padapter), addr);\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\n\tif (DBG_MP_SDIO_INDIRECT_ACCESS)\n\t\tRTW_INFO(FUNC_ADPT_FMT\" width:%u, addr:0x%lx\\n\", FUNC_ADPT_ARG(padapter), width, addr);\n\n\tswitch (width) {\n\tcase 1:\n\t\tsprintf(extra, \"0x%02x\", rtw_sd_iread8(padapter, addr));\n\t\twrqu->length = strlen(extra);\n\t\tbreak;\n\tcase 2:\n\t\tsprintf(extra, \"0x%04x\", rtw_sd_iread16(padapter, addr));\n\t\twrqu->length = strlen(extra);\n\t\tbreak;\n\tcase 4:\n\t\tsprintf(extra, \"0x%08x\", rtw_sd_iread32(padapter, addr));\n\t\twrqu->length = strlen(extra);\n\t\tbreak;\n\tdefault:\n\t\twrqu->length = 0;\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\nexit:\n\treturn ret;\n}\n\nstatic int rtw_mp_sd_iwrite(struct net_device *dev\n\t\t\t    , struct iw_request_info *info\n\t\t\t    , struct iw_point *wrqu\n\t\t\t    , char *extra)\n{\n\tchar width;\n\tunsigned long addr, data;\n\tint ret = 0;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tchar input[32];\n\n\tif (wrqu->length > 32) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" wrqu->length:%d\\n\", FUNC_ADPT_ARG(padapter), wrqu->length);\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" copy_from_user fail\\n\", FUNC_ADPT_ARG(padapter));\n\t\tret = -EFAULT;\n\t\tgoto exit;\n\t}\n\n\t_rtw_memset(extra, 0, wrqu->length);\n\n\tif (sscanf(input, \"%hhu,%lx,%lx\", &width, &addr, &data) != 3) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" sscanf fail\\n\", FUNC_ADPT_ARG(padapter));\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\n\tif (addr > 0x3FFF) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" addr:0x%lx\\n\", FUNC_ADPT_ARG(padapter), addr);\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\n\tif (DBG_MP_SDIO_INDIRECT_ACCESS)\n\t\tRTW_INFO(FUNC_ADPT_FMT\" width:%u, addr:0x%lx, data:0x%lx\\n\", FUNC_ADPT_ARG(padapter), width, addr, data);\n\n\tswitch (width) {\n\tcase 1:\n\t\tif (data > 0xFF) {\n\t\t\tret = -EINVAL;\n\t\t\tbreak;\n\t\t}\n\t\trtw_sd_iwrite8(padapter, addr, data);\n\t\tbreak;\n\tcase 2:\n\t\tif (data > 0xFFFF) {\n\t\t\tret = -EINVAL;\n\t\t\tbreak;\n\t\t}\n\t\trtw_sd_iwrite16(padapter, addr, data);\n\t\tbreak;\n\tcase 4:\n\t\trtw_sd_iwrite32(padapter, addr, data);\n\t\tbreak;\n\tdefault:\n\t\twrqu->length = 0;\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\nexit:\n\treturn ret;\n}\n#endif /* CONFIG_SDIO_INDIRECT_ACCESS */\n\nstatic int rtw_priv_set(struct net_device *dev,\n\t\t\tstruct iw_request_info *info,\n\t\t\tunion iwreq_data *wdata, char *extra)\n{\n\tstruct iw_point *wrqu = (struct iw_point *)wdata;\n\tu32 subcmd = wrqu->flags;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\n\tif (padapter == NULL)\n\t\treturn -ENETDOWN;\n\n\tif (padapter->bup == _FALSE) {\n\t\tRTW_INFO(\" %s fail =>(padapter->bup == _FALSE )\\n\", __FUNCTION__);\n\t\treturn -ENETDOWN;\n\t}\n\n\tif (RTW_CANNOT_RUN(padapter)) {\n\t\tRTW_INFO(\"%s fail =>(bSurpriseRemoved == _TRUE) || ( bDriverStopped == _TRUE)\\n\", __func__);\n\t\treturn -ENETDOWN;\n\t}\n\n\tif (extra == NULL) {\n\t\twrqu->length = 0;\n\t\treturn -EIO;\n\t}\n\n\tif (subcmd < MP_NULL) {\n#ifdef CONFIG_MP_INCLUDED\n\t\trtw_priv_mp_set(dev, info, wdata, extra);\n#endif\n\t\treturn 0;\n\t}\n\n\tswitch (subcmd) {\n#ifdef CONFIG_WOWLAN\n\tcase MP_WOW_ENABLE:\n\t\tRTW_INFO(\"set case MP_WOW_ENABLE: %s\\n\", extra);\n\n\t\trtw_wowlan_ctrl(dev, info, wdata, extra);\n\t\tbreak;\n\tcase MP_WOW_SET_PATTERN:\n\t\tRTW_INFO(\"set case MP_WOW_SET_PATTERN: %s\\n\", extra);\n\t\trtw_wowlan_set_pattern(dev, info, wdata, extra);\n\t\tbreak;\n#endif\n#ifdef CONFIG_AP_WOWLAN\n\tcase MP_AP_WOW_ENABLE:\n\t\tRTW_INFO(\"set case MP_AP_WOW_ENABLE: %s\\n\", extra);\n\t\trtw_ap_wowlan_ctrl(dev, info, wdata, extra);\n\t\tbreak;\n#endif\n#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE\n\tcase VENDOR_IE_SET:\n\t\tRTW_INFO(\"set case VENDOR_IE_SET\\n\");\n\t\trtw_vendor_ie_set(dev , info , wdata , extra);\n\t\tbreak;\n#endif\n\tdefault:\n\t\treturn -EIO;\n\t}\n\n\treturn 0;\n}\n\n\nstatic int rtw_priv_get(struct net_device *dev,\n\t\t\tstruct iw_request_info *info,\n\t\t\tunion iwreq_data *wdata, char *extra)\n{\n\tstruct iw_point *wrqu = (struct iw_point *)wdata;\n\tu32 subcmd = wrqu->flags;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct dm_struct\t*p_dm = &pHalData->odmpriv;\n\tstruct dm_rf_calibration_struct\t*p_rf_calibrate_info = &(p_dm->rf_calibrate_info);\n\tstruct dm_iqk_info\t*p_iqk_info = &p_dm->IQK_info;\n\tu32 i = 100;\n\n\tif (padapter == NULL)\n\t\treturn -ENETDOWN;\n\n\tif (padapter->bup == _FALSE) {\n\t\tRTW_INFO(\" %s fail =>(padapter->bup == _FALSE )\\n\", __FUNCTION__);\n\t\treturn -ENETDOWN;\n\t}\n\n\tif (RTW_CANNOT_RUN(padapter)) {\n\t\tRTW_INFO(\"%s fail =>(padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)\\n\", __func__);\n\t\treturn -ENETDOWN;\n\t}\n\n\tif (extra == NULL) {\n\t\twrqu->length = 0;\n\t\treturn -EIO;\n\t}\n\n\tif (subcmd < MP_NULL) {\n#ifdef CONFIG_MP_INCLUDED\n\t\twhile (i > 1) {\n\t\t\tif (p_rf_calibrate_info->is_iqk_in_progress) {\n\t\t\t\trtw_msleep_os(10);\n\t\t\t} else {\n\t\t\t\tp_iqk_info->rfk_forbidden = _TRUE;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\ti--;\n\t\t}\n\t\tif (subcmd == MP_CHANNEL || subcmd == MP_BANDWIDTH || subcmd == MP_START)\n\t\t\tp_iqk_info->rfk_forbidden = _FALSE;\n\t\trtw_priv_mp_get(dev, info, wdata, extra);\n\t\tp_iqk_info->rfk_forbidden = _FALSE;\n#endif\n\t\treturn 0;\n\t}\n\n\tswitch (subcmd) {\n#if defined(CONFIG_RTL8723B)\n\tcase MP_SetBT:\n\t\tRTW_INFO(\"set MP_SetBT\\n\");\n\t\trtw_mp_SetBT(dev, info, wdata, extra);\n\t\tbreak;\n#endif\n#ifdef CONFIG_SDIO_INDIRECT_ACCESS\n\tcase MP_SD_IREAD:\n\t\trtw_mp_sd_iread(dev, info, wrqu, extra);\n\t\tbreak;\n\tcase MP_SD_IWRITE:\n\t\trtw_mp_sd_iwrite(dev, info, wrqu, extra);\n\t\tbreak;\n#endif\n#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE\n\tcase VENDOR_IE_GET:\n\t\tRTW_INFO(\"get case VENDOR_IE_GET\\n\");\n\t\trtw_vendor_ie_get(dev , info , wdata , extra);\n\t\tbreak;\n#endif\n\tdefault:\n\t\treturn -EIO;\n\t}\n\n\trtw_msleep_os(10); /* delay 5ms for sending pkt before exit adb shell operation */\n\treturn 0;\n}\n\n\n#ifdef CONFIG_TDLS\nstatic int rtw_wx_tdls_wfd_enable(struct net_device *dev,\n\t\t\t\t  struct iw_request_info *info,\n\t\t\t\t  union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_WFD\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_INFO(\"[%s] %s %d\\n\", __FUNCTION__, extra, wrqu->data.length - 1);\n\n\tif (extra[0] == '0')\n\t\trtw_tdls_wfd_enable(padapter, 0);\n\telse\n\t\trtw_tdls_wfd_enable(padapter, 1);\n\n#endif /* CONFIG_WFD */\n\n\treturn ret;\n}\n\nstatic int rtw_tdls_weaksec(struct net_device *dev,\n\t\t\t    struct iw_request_info *info,\n\t\t\t    union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n\n\tu8 i, j;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_INFO(\"[%s] %s %d\\n\", __FUNCTION__, extra, wrqu->data.length - 1);\n\n\tif (extra[0] == '0')\n\t\tpadapter->wdinfo.wfd_tdls_weaksec = 0;\n\telse\n\t\tpadapter->wdinfo.wfd_tdls_weaksec = 1;\n\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n}\n\n\nstatic int rtw_tdls_enable(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_INFO(\"[%s] %s %d\\n\", __FUNCTION__, extra, wrqu->data.length - 1);\n\n\tif (extra[0] == '0')\n\t\trtw_disable_tdls_func(padapter, _TRUE);\n\telse if (extra[0] == '1')\n\t\trtw_enable_tdls_func(padapter);\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n}\n\nstatic int rtw_tdls_setup(struct net_device *dev,\n\t\t\t  struct iw_request_info *info,\n\t\t\t  union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n#ifdef CONFIG_TDLS\n\tu8 i, j;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct tdls_txmgmt txmgmt;\n#ifdef CONFIG_WFD\n\tstruct wifidirect_info *pwdinfo = &(padapter->wdinfo);\n#endif /* CONFIG_WFD */\n\n\tRTW_INFO(\"[%s] %s %d\\n\", __FUNCTION__, extra, wrqu->data.length - 1);\n\n\tif (wrqu->data.length - 1 != 17) {\n\t\tRTW_INFO(\"[%s] length:%d != 17\\n\", __FUNCTION__, (wrqu->data.length - 1));\n\t\treturn ret;\n\t}\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\tfor (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)\n\t\ttxmgmt.peer[i] = key_2char2num(*(extra + j), *(extra + j + 1));\n\n#ifdef CONFIG_WFD\n\tif (_AES_ != padapter->securitypriv.dot11PrivacyAlgrthm) {\n\t\t/* Weak Security situation with AP. */\n\t\tif (0 == pwdinfo->wfd_tdls_weaksec)\t{\n\t\t\t/* Can't send the tdls setup request out!! */\n\t\t\tRTW_INFO(\"[%s] Current link is not AES, \"\n\t\t\t\t\"SKIP sending the tdls setup request!!\\n\", __FUNCTION__);\n\t\t} else\n\t\t\tissue_tdls_setup_req(padapter, &txmgmt, _TRUE);\n\t} else\n#endif /* CONFIG_WFD */\n\t{\n\t\tissue_tdls_setup_req(padapter, &txmgmt, _TRUE);\n\t}\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n}\n\nstatic int rtw_tdls_teardown(struct net_device *dev,\n\t\t\t     struct iw_request_info *info,\n\t\t\t     union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n\n\tu8 i, j;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct sta_info *ptdls_sta = NULL;\n\tstruct tdls_txmgmt txmgmt;\n\n\tRTW_INFO(\"[%s] %s %d\\n\", __FUNCTION__, extra, wrqu->data.length - 1);\n\n\tif (wrqu->data.length - 1 != 17 && wrqu->data.length - 1 != 19) {\n\t\tRTW_INFO(\"[%s] length:%d != 17 or 19\\n\",\n\t\t\t __FUNCTION__, (wrqu->data.length - 1));\n\t\treturn ret;\n\t}\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\tfor (i = 0, j = 0; i < ETH_ALEN; i++, j += 3)\n\t\ttxmgmt.peer[i] = key_2char2num(*(extra + j), *(extra + j + 1));\n\n\tptdls_sta = rtw_get_stainfo(&(padapter->stapriv), txmgmt.peer);\n\n\tif (ptdls_sta != NULL) {\n\t\ttxmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;\n\t\tif (wrqu->data.length - 1 == 19)\n\t\t\tissue_tdls_teardown(padapter, &txmgmt, _FALSE);\n\t\telse\n\t\t\tissue_tdls_teardown(padapter, &txmgmt, _TRUE);\n\t} else\n\t\tRTW_INFO(\"TDLS peer not found\\n\");\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n}\n\nstatic int rtw_tdls_discovery(struct net_device *dev,\n\t\t\t      struct iw_request_info *info,\n\t\t\t      union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct tdls_txmgmt\ttxmgmt;\n\tint i = 0, j = 0;\n\n\tRTW_INFO(\"[%s] %s %d\\n\", __FUNCTION__, extra, wrqu->data.length - 1);\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\tfor (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)\n\t\ttxmgmt.peer[i] = key_2char2num(*(extra + j), *(extra + j + 1));\n\n\tissue_tdls_dis_req(padapter, &txmgmt);\n\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n}\n\nstatic int rtw_tdls_ch_switch(struct net_device *dev,\n\t\t\t      struct iw_request_info *info,\n\t\t\t      union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;\n\tu8 i, j;\n\tstruct sta_info *ptdls_sta = NULL;\n\tu8 take_care_iqk;\n\n\tRTW_INFO(\"[%s] %s %d\\n\", __FUNCTION__, extra, wrqu->data.length - 1);\n\n\tif (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {\n\t\tRTW_INFO(\"TDLS channel switch is not allowed\\n\");\n\t\treturn ret;\n\t}\n\n\tfor (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)\n\t\tpchsw_info->addr[i] = key_2char2num(*(extra + j), *(extra + j + 1));\n\n\tptdls_sta = rtw_get_stainfo(&padapter->stapriv, pchsw_info->addr);\n\tif (ptdls_sta == NULL)\n\t\treturn ret;\n\n\tpchsw_info->ch_sw_state |= TDLS_CH_SW_INITIATOR_STATE;\n\n\tif (ptdls_sta != NULL) {\n\t\tif (pchsw_info->off_ch_num == 0)\n\t\t\tpchsw_info->off_ch_num = 11;\n\t} else\n\t\tRTW_INFO(\"TDLS peer not found\\n\");\n\n\trtw_pm_set_lps(padapter, PS_MODE_ACTIVE);\n\n\trtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);\n\tif (take_care_iqk == _TRUE) {\n\t\tu8 central_chnl;\n\t\tu8 bw_mode;\n\n\t\tbw_mode = (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20;\n\t\tcentral_chnl = rtw_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset);\n\t\tif (rtw_hal_ch_sw_iqk_info_search(padapter, central_chnl, bw_mode) >= 0)\n\t\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);\n\t\telse\n\t\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_PREPARE);\n\t} else\n\t\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);\n\n\t/* issue_tdls_ch_switch_req(padapter, ptdls_sta); */\n\t/* RTW_INFO(\"issue tdls ch switch req\\n\"); */\n\n#endif /* CONFIG_TDLS_CH_SW */\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n}\n\nstatic int rtw_tdls_ch_switch_off(struct net_device *dev,\n\t\t\t\t  struct iw_request_info *info,\n\t\t\t\t  union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;\n\tu8 i, j, mac_addr[ETH_ALEN];\n\tstruct sta_info *ptdls_sta = NULL;\n\tstruct tdls_txmgmt txmgmt;\n\n\t_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));\n\n\tRTW_INFO(\"[%s] %s %d\\n\", __FUNCTION__, extra, wrqu->data.length - 1);\n\n\tif (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {\n\t\tRTW_INFO(\"TDLS channel switch is not allowed\\n\");\n\t\treturn ret;\n\t}\n\n\tif (wrqu->data.length >= 17) {\n\t\tfor (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)\n\t\t\tmac_addr[i] = key_2char2num(*(extra + j), *(extra + j + 1));\n\t\tptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr);\n\t}\n\n\tif (ptdls_sta == NULL)\n\t\treturn ret;\n\n\trtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL);\n\n\tpchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE |\n\t\t\t\t     TDLS_CH_SWITCH_ON_STATE |\n\t\t\t\t     TDLS_PEER_AT_OFF_STATE);\n\t_rtw_memset(pchsw_info->addr, 0x00, ETH_ALEN);\n\n\tptdls_sta->ch_switch_time = 0;\n\tptdls_sta->ch_switch_timeout = 0;\n\t_cancel_timer_ex(&ptdls_sta->ch_sw_timer);\n\t_cancel_timer_ex(&ptdls_sta->delay_timer);\n\t_cancel_timer_ex(&ptdls_sta->stay_on_base_chnl_timer);\n\t_cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer);\n\n\trtw_pm_set_lps(padapter, PS_MODE_MAX);\n#endif /* CONFIG_TDLS_CH_SW */\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n}\n\nstatic int rtw_tdls_dump_ch(struct net_device *dev,\n\t\t\t    struct iw_request_info *info,\n\t\t\t    union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\n\tRTW_INFO(\"[%s] dump_stack:%s\\n\", __FUNCTION__, extra);\n\n\textra[wrqu->data.length] = 0x00;\n\tptdlsinfo->chsw_info.dump_stack = rtw_atoi(extra);\n\n\treturn ret;\n\n#endif\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n}\n\nstatic int rtw_tdls_off_ch_num(struct net_device *dev,\n\t\t\t       struct iw_request_info *info,\n\t\t\t       union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\n\tRTW_INFO(\"[%s] off_ch_num:%s\\n\", __FUNCTION__, extra);\n\n\textra[wrqu->data.length] = 0x00;\n\tptdlsinfo->chsw_info.off_ch_num = rtw_atoi(extra);\n\n\treturn ret;\n\n#endif\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n}\n\nstatic int rtw_tdls_ch_offset(struct net_device *dev,\n\t\t\t      struct iw_request_info *info,\n\t\t\t      union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_TDLS_CH_SW\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\n\tRTW_INFO(\"[%s] ch_offset:%s\\n\", __FUNCTION__, extra);\n\n\textra[wrqu->data.length] = 0x00;\n\tswitch (rtw_atoi(extra)) {\n\tcase SCA:\n\t\tptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;\n\t\tbreak;\n\n\tcase SCB:\n\t\tptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;\n\t\tbreak;\n\n\tdefault:\n\t\tptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\t\tbreak;\n\t}\n\n\treturn ret;\n\n#endif\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n}\n\nstatic int rtw_tdls_pson(struct net_device *dev,\n\t\t\t struct iw_request_info *info,\n\t\t\t union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8 i, j, mac_addr[ETH_ALEN];\n\tstruct sta_info *ptdls_sta = NULL;\n\n\tRTW_INFO(\"[%s] %s %d\\n\", __FUNCTION__, extra, wrqu->data.length - 1);\n\n\tfor (i = 0, j = 0; i < ETH_ALEN; i++, j += 3)\n\t\tmac_addr[i] = key_2char2num(*(extra + j), *(extra + j + 1));\n\n\tptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr);\n\n\tissue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 1, 3, 500);\n\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n}\n\nstatic int rtw_tdls_psoff(struct net_device *dev,\n\t\t\t  struct iw_request_info *info,\n\t\t\t  union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8 i, j, mac_addr[ETH_ALEN];\n\tstruct sta_info *ptdls_sta = NULL;\n\n\tRTW_INFO(\"[%s] %s %d\\n\", __FUNCTION__, extra, wrqu->data.length - 1);\n\n\tfor (i = 0, j = 0; i < ETH_ALEN; i++, j += 3)\n\t\tmac_addr[i] = key_2char2num(*(extra + j), *(extra + j + 1));\n\n\tptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr);\n\n\tif (ptdls_sta)\n\t\tissue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 3, 500);\n\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n}\n\nstatic int rtw_tdls_setip(struct net_device *dev,\n\t\t\t  struct iw_request_info *info,\n\t\t\t  union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_WFD\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\tstruct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info;\n\tu8 i = 0, j = 0, k = 0, tag = 0;\n\n\tRTW_INFO(\"[%s] %s %d\\n\", __FUNCTION__, extra, wrqu->data.length - 1);\n\n\twhile (i < 4) {\n\t\tfor (j = 0; j < 4; j++) {\n\t\t\tif (*(extra + j + tag) == '.' || *(extra + j + tag) == '\\0') {\n\t\t\t\tif (j == 1)\n\t\t\t\t\tpwfd_info->ip_address[i] = convert_ip_addr('0', '0', *(extra + (j - 1) + tag));\n\t\t\t\tif (j == 2)\n\t\t\t\t\tpwfd_info->ip_address[i] = convert_ip_addr('0', *(extra + (j - 2) + tag), *(extra + (j - 1) + tag));\n\t\t\t\tif (j == 3)\n\t\t\t\t\tpwfd_info->ip_address[i] = convert_ip_addr(*(extra + (j - 3) + tag), *(extra + (j - 2) + tag), *(extra + (j - 1) + tag));\n\n\t\t\t\ttag += j + 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\ti++;\n\t}\n\n\tRTW_INFO(\"[%s] Set IP = %u.%u.%u.%u\\n\", __FUNCTION__,\n\t\t ptdlsinfo->wfd_info->ip_address[0],\n\t\t ptdlsinfo->wfd_info->ip_address[1],\n\t\t ptdlsinfo->wfd_info->ip_address[2],\n\t\t ptdlsinfo->wfd_info->ip_address[3]);\n\n#endif /* CONFIG_WFD */\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n}\n\nstatic int rtw_tdls_getip(struct net_device *dev,\n\t\t\t  struct iw_request_info *info,\n\t\t\t  union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_WFD\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\tstruct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info;\n\n\tRTW_INFO(\"[%s]\\n\", __FUNCTION__);\n\n\tsprintf(extra, \"\\n\\n%u.%u.%u.%u\\n\",\n\t\tpwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1],\n\t\tpwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3]);\n\n\tRTW_INFO(\"[%s] IP=%u.%u.%u.%u\\n\", __FUNCTION__,\n\t\t pwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1],\n\t\t pwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3]);\n\n\twrqu->data.length = strlen(extra);\n\n#endif /* CONFIG_WFD */\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n}\n\nstatic int rtw_tdls_getport(struct net_device *dev,\n\t\t\t    struct iw_request_info *info,\n\t\t\t    union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_WFD\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\tstruct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info;\n\n\tRTW_INFO(\"[%s]\\n\", __FUNCTION__);\n\n\tsprintf(extra, \"\\n\\n%d\\n\", pwfd_info->peer_rtsp_ctrlport);\n\tRTW_INFO(\"[%s] remote port = %d\\n\",\n\t\t __FUNCTION__, pwfd_info->peer_rtsp_ctrlport);\n\n\twrqu->data.length = strlen(extra);\n\n#endif /* CONFIG_WFD */\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n\n}\n\n/* WFDTDLS, for sigma test */\nstatic int rtw_tdls_dis_result(struct net_device *dev,\n\t\t\t       struct iw_request_info *info,\n\t\t\t       union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n#ifdef CONFIG_WFD\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\n\tRTW_INFO(\"[%s]\\n\", __FUNCTION__);\n\n\tif (ptdlsinfo->dev_discovered == _TRUE) {\n\t\tsprintf(extra, \"\\n\\nDis=1\\n\");\n\t\tptdlsinfo->dev_discovered = _FALSE;\n\t}\n\n\twrqu->data.length = strlen(extra);\n\n#endif /* CONFIG_WFD */\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n\n}\n\n/* WFDTDLS, for sigma test */\nstatic int rtw_wfd_tdls_status(struct net_device *dev,\n\t\t\t       struct iw_request_info *info,\n\t\t\t       union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct tdls_info *ptdlsinfo = &padapter->tdlsinfo;\n\n\tRTW_INFO(\"[%s]\\n\", __FUNCTION__);\n\n\tsprintf(extra, \"\\nlink_established:%d\\n\"\n\t\t\"sta_cnt:%d\\n\"\n\t\t\"sta_maximum:%d\\n\"\n\t\t\"cur_channel:%d\\n\"\n\t\t\"tdls_enable:%d\"\n#ifdef CONFIG_TDLS_CH_SW\n\t\t\"ch_sw_state:%08x\\n\"\n\t\t\"chsw_on:%d\\n\"\n\t\t\"off_ch_num:%d\\n\"\n\t\t\"cur_time:%d\\n\"\n\t\t\"ch_offset:%d\\n\"\n\t\t\"delay_swtich_back:%d\"\n#endif\n\t\t,\n\t\tptdlsinfo->link_established, ptdlsinfo->sta_cnt,\n\t\tptdlsinfo->sta_maximum, ptdlsinfo->cur_channel,\n\t\trtw_is_tdls_enabled(padapter)\n#ifdef CONFIG_TDLS_CH_SW\n\t\t,\n\t\tptdlsinfo->chsw_info.ch_sw_state,\n\t\tATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on),\n\t\tptdlsinfo->chsw_info.off_ch_num,\n\t\tptdlsinfo->chsw_info.cur_time,\n\t\tptdlsinfo->chsw_info.ch_offset,\n\t\tptdlsinfo->chsw_info.delay_switch_back\n#endif\n\t       );\n\n\twrqu->data.length = strlen(extra);\n\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n\n}\n\nstatic int rtw_tdls_getsta(struct net_device *dev,\n\t\t\t   struct iw_request_info *info,\n\t\t\t   union iwreq_data *wrqu, char *extra)\n{\n\n\tint ret = 0;\n#ifdef CONFIG_TDLS\n\tu8 i, j;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8 addr[ETH_ALEN] = {0};\n\tchar charmac[17];\n\tstruct sta_info *ptdls_sta = NULL;\n\n\tRTW_INFO(\"[%s] %s %d\\n\", __FUNCTION__,\n\t\t (char *)wrqu->data.pointer, wrqu->data.length - 1);\n\n\tif (copy_from_user(charmac, wrqu->data.pointer + 9, 17)) {\n\t\tret = -EFAULT;\n\t\tgoto exit;\n\t}\n\n\tRTW_INFO(\"[%s] %d, charmac:%s\\n\", __FUNCTION__, __LINE__, charmac);\n\tfor (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)\n\t\taddr[i] = key_2char2num(*(charmac + j), *(charmac + j + 1));\n\n\tRTW_INFO(\"[%s] %d, charmac:%s, addr:\"MAC_FMT\"\\n\",\n\t\t __FUNCTION__, __LINE__, charmac, MAC_ARG(addr));\n\tptdls_sta = rtw_get_stainfo(&padapter->stapriv, addr);\n\tif (ptdls_sta) {\n\t\tsprintf(extra, \"\\n\\ntdls_sta_state=0x%08x\\n\", ptdls_sta->tdls_sta_state);\n\t\tRTW_INFO(\"\\n\\ntdls_sta_state=%d\\n\", ptdls_sta->tdls_sta_state);\n\t} else {\n\t\tsprintf(extra, \"\\n\\nNot found this sta\\n\");\n\t\tRTW_INFO(\"\\n\\nNot found this sta\\n\");\n\t}\n\twrqu->data.length = strlen(extra);\n\nexit:\n#endif /* CONFIG_TDLS */\n\treturn ret;\n\n}\n\nstatic int rtw_tdls_get_best_ch(struct net_device *dev,\n\t\t\t\tstruct iw_request_info *info,\n\t\t\t\tunion iwreq_data *wrqu, char *extra)\n{\n#ifdef CONFIG_FIND_BEST_CHANNEL\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);\n\tu32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0;\n\n\tfor (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {\n\t\tif (rfctl->channel_set[i].ChannelNum == 1)\n\t\t\tindex_24G = i;\n\t\tif (rfctl->channel_set[i].ChannelNum == 36)\n\t\t\tindex_5G = i;\n\t}\n\n\tfor (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {\n\t\t/* 2.4G */\n\t\tif (rfctl->channel_set[i].ChannelNum == 6 || rfctl->channel_set[i].ChannelNum == 11) {\n\t\t\tif (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_24G].rx_count) {\n\t\t\t\tindex_24G = i;\n\t\t\t\tbest_channel_24G = rfctl->channel_set[i].ChannelNum;\n\t\t\t}\n\t\t}\n\n\t\t/* 5G */\n\t\tif (rfctl->channel_set[i].ChannelNum >= 36\n\t\t    && rfctl->channel_set[i].ChannelNum < 140) {\n\t\t\t/* Find primary channel */\n\t\t\tif (((rfctl->channel_set[i].ChannelNum - 36) % 8 == 0)\n\t\t\t    && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {\n\t\t\t\tindex_5G = i;\n\t\t\t\tbest_channel_5G = rfctl->channel_set[i].ChannelNum;\n\t\t\t}\n\t\t}\n\n\t\tif (rfctl->channel_set[i].ChannelNum >= 149\n\t\t    && rfctl->channel_set[i].ChannelNum < 165) {\n\t\t\t/* Find primary channel */\n\t\t\tif (((rfctl->channel_set[i].ChannelNum - 149) % 8 == 0)\n\t\t\t    && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {\n\t\t\t\tindex_5G = i;\n\t\t\t\tbest_channel_5G = rfctl->channel_set[i].ChannelNum;\n\t\t\t}\n\t\t}\n#if 1 /* debug */\n\t\tRTW_INFO(\"The rx cnt of channel %3d = %d\\n\",\n\t\t\t rfctl->channel_set[i].ChannelNum,\n\t\t\t rfctl->channel_set[i].rx_count);\n#endif\n\t}\n\n\tsprintf(extra, \"\\nbest_channel_24G = %d\\n\", best_channel_24G);\n\tRTW_INFO(\"best_channel_24G = %d\\n\", best_channel_24G);\n\n\tif (index_5G != 0) {\n\t\tsprintf(extra, \"best_channel_5G = %d\\n\", best_channel_5G);\n\t\tRTW_INFO(\"best_channel_5G = %d\\n\", best_channel_5G);\n\t}\n\n\twrqu->data.length = strlen(extra);\n\n#endif\n\n\treturn 0;\n\n}\n#endif /*#ifdef CONFIG_TDLS*/\nstatic int rtw_tdls(struct net_device *dev,\n\t\t    struct iw_request_info *info,\n\t\t    union iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_INFO(\"[%s] extra = %s\\n\", __FUNCTION__, extra);\n\n\tif (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) {\n\t\tRTW_INFO(\"Discard tdls oper since hal doesn't support tdls\\n\");\n\t\treturn 0;\n\t}\n\n\tif (rtw_is_tdls_enabled(padapter) == _FALSE) {\n\t\tRTW_INFO(\"TDLS is not enabled\\n\");\n\t\treturn 0;\n\t}\n\n\t/* WFD Sigma will use the tdls enable command to let the driver know we want to test the tdls now! */\n\n\tif (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {\n\t\tif (_rtw_memcmp(extra, \"wfdenable=\", 10)) {\n\t\t\twrqu->data.length -= 10;\n\t\t\trtw_wx_tdls_wfd_enable(dev, info, wrqu, &extra[10]);\n\t\t\treturn ret;\n\t\t}\n\t}\n\n\tif (_rtw_memcmp(extra, \"weaksec=\", 8)) {\n\t\twrqu->data.length -= 8;\n\t\trtw_tdls_weaksec(dev, info, wrqu, &extra[8]);\n\t\treturn ret;\n\t} else if (_rtw_memcmp(extra, \"tdlsenable=\", 11)) {\n\t\twrqu->data.length -= 11;\n\t\trtw_tdls_enable(dev, info, wrqu, &extra[11]);\n\t\treturn ret;\n\t}\n\n\tif (_rtw_memcmp(extra, \"setup=\", 6)) {\n\t\twrqu->data.length -= 6;\n\t\trtw_tdls_setup(dev, info, wrqu, &extra[6]);\n\t} else if (_rtw_memcmp(extra, \"tear=\", 5)) {\n\t\twrqu->data.length -= 5;\n\t\trtw_tdls_teardown(dev, info, wrqu, &extra[5]);\n\t} else if (_rtw_memcmp(extra, \"dis=\", 4)) {\n\t\twrqu->data.length -= 4;\n\t\trtw_tdls_discovery(dev, info, wrqu, &extra[4]);\n\t} else if (_rtw_memcmp(extra, \"swoff=\", 6)) {\n\t\twrqu->data.length -= 6;\n\t\trtw_tdls_ch_switch_off(dev, info, wrqu, &extra[6]);\n\t} else if (_rtw_memcmp(extra, \"sw=\", 3)) {\n\t\twrqu->data.length -= 3;\n\t\trtw_tdls_ch_switch(dev, info, wrqu, &extra[3]);\n\t} else if (_rtw_memcmp(extra, \"dumpstack=\", 10)) {\n\t\twrqu->data.length -= 10;\n\t\trtw_tdls_dump_ch(dev, info, wrqu, &extra[10]);\n\t} else if (_rtw_memcmp(extra, \"offchnum=\", 9)) {\n\t\twrqu->data.length -= 9;\n\t\trtw_tdls_off_ch_num(dev, info, wrqu, &extra[9]);\n\t} else if (_rtw_memcmp(extra, \"choffset=\", 9)) {\n\t\twrqu->data.length -= 9;\n\t\trtw_tdls_ch_offset(dev, info, wrqu, &extra[9]);\n\t} else if (_rtw_memcmp(extra, \"pson=\", 5)) {\n\t\twrqu->data.length -= 5;\n\t\trtw_tdls_pson(dev, info, wrqu, &extra[5]);\n\t} else if (_rtw_memcmp(extra, \"psoff=\", 6)) {\n\t\twrqu->data.length -= 6;\n\t\trtw_tdls_psoff(dev, info, wrqu, &extra[6]);\n\t}\n\n#ifdef CONFIG_WFD\n\tif (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {\n\t\tif (_rtw_memcmp(extra, \"setip=\", 6)) {\n\t\t\twrqu->data.length -= 6;\n\t\t\trtw_tdls_setip(dev, info, wrqu, &extra[6]);\n\t\t} else if (_rtw_memcmp(extra, \"tprobe=\", 6))\n\t\t\tissue_tunneled_probe_req((_adapter *)rtw_netdev_priv(dev));\n\t}\n#endif /* CONFIG_WFD */\n\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n}\n\n\nstatic int rtw_tdls_get(struct net_device *dev,\n\t\t\tstruct iw_request_info *info,\n\t\t\tunion iwreq_data *wrqu, char *extra)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_TDLS\n\n\tRTW_INFO(\"[%s] extra = %s\\n\", __FUNCTION__, (char *) wrqu->data.pointer);\n\n\tif (_rtw_memcmp(wrqu->data.pointer, \"ip\", 2))\n\t\trtw_tdls_getip(dev, info, wrqu, extra);\n\telse if (_rtw_memcmp(wrqu->data.pointer, \"port\", 4))\n\t\trtw_tdls_getport(dev, info, wrqu, extra);\n\t/* WFDTDLS, for sigma test */\n\telse if (_rtw_memcmp(wrqu->data.pointer, \"dis\", 3))\n\t\trtw_tdls_dis_result(dev, info, wrqu, extra);\n\telse if (_rtw_memcmp(wrqu->data.pointer, \"status\", 6))\n\t\trtw_wfd_tdls_status(dev, info, wrqu, extra);\n\telse if (_rtw_memcmp(wrqu->data.pointer, \"tdls_sta=\", 9))\n\t\trtw_tdls_getsta(dev, info, wrqu, extra);\n\telse if (_rtw_memcmp(wrqu->data.pointer, \"best_ch\", 7))\n\t\trtw_tdls_get_best_ch(dev, info, wrqu, extra);\n#endif /* CONFIG_TDLS */\n\n\treturn ret;\n}\n\n#ifdef CONFIG_MAC_LOOPBACK_DRIVER\n\n#if defined(CONFIG_RTL8188E)\n#include <rtl8188e_hal.h>\nextern void rtl8188e_cal_txdesc_chksum(struct tx_desc *ptxdesc);\n#define cal_txdesc_chksum rtl8188e_cal_txdesc_chksum\n#ifdef CONFIG_SDIO_HCI || defined(CONFIG_GSPI_HCI)\nextern void rtl8188es_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf);\n#define fill_default_txdesc rtl8188es_fill_default_txdesc\n#endif /* CONFIG_SDIO_HCI */\n#endif /* CONFIG_RTL8188E */\n#if defined(CONFIG_RTL8723B)\nextern void rtl8723b_cal_txdesc_chksum(struct tx_desc *ptxdesc);\n#define cal_txdesc_chksum rtl8723b_cal_txdesc_chksum\nextern void rtl8723b_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf);\n#define fill_default_txdesc rtl8723b_fill_default_txdesc\n#endif /* CONFIG_RTL8723B */\n\n#if defined(CONFIG_RTL8703B)\n/* extern void rtl8703b_cal_txdesc_chksum(struct tx_desc *ptxdesc); */\n#define cal_txdesc_chksum rtl8703b_cal_txdesc_chksum\n/* extern void rtl8703b_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); */\n#define fill_default_txdesc rtl8703b_fill_default_txdesc\n#endif /* CONFIG_RTL8703B */\n\n#if defined(CONFIG_RTL8723D)\n/* extern void rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc); */\n#define cal_txdesc_chksum rtl8723d_cal_txdesc_chksum\n/* extern void rtl8723d_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); */\n#define fill_default_txdesc rtl8723d_fill_default_txdesc\n#endif /* CONFIG_RTL8723D */\n\n#if defined(CONFIG_RTL8710B)\n#define cal_txdesc_chksum rtl8710b_cal_txdesc_chksum\n#define fill_default_txdesc rtl8710b_fill_default_txdesc\n#endif /* CONFIG_RTL8710B */\n\n#if defined(CONFIG_RTL8192E)\nextern void rtl8192e_cal_txdesc_chksum(struct tx_desc *ptxdesc);\n#define cal_txdesc_chksum rtl8192e_cal_txdesc_chksum\n#ifdef CONFIG_SDIO_HCI || defined(CONFIG_GSPI_HCI)\nextern void rtl8192es_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf);\n#define fill_default_txdesc rtl8192es_fill_default_txdesc\n#endif /* CONFIG_SDIO_HCI */\n#endif /* CONFIG_RTL8192E */\n\n#if defined(CONFIG_RTL8192F)\n/* extern void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc); */\n#define cal_txdesc_chksum rtl8192f_cal_txdesc_chksum\n/* extern void rtl8192f_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); */\n#define fill_default_txdesc rtl8192f_fill_default_txdesc\n#endif /* CONFIG_RTL8192F */\n\nstatic s32 initLoopback(PADAPTER padapter)\n{\n\tPLOOPBACKDATA ploopback;\n\n\n\tif (padapter->ploopback == NULL) {\n\t\tploopback = (PLOOPBACKDATA)rtw_zmalloc(sizeof(LOOPBACKDATA));\n\t\tif (ploopback == NULL)\n\t\t\treturn -ENOMEM;\n\n\t\t_rtw_init_sema(&ploopback->sema, 0);\n\t\tploopback->bstop = _TRUE;\n\t\tploopback->cnt = 0;\n\t\tploopback->size = 300;\n\t\t_rtw_memset(ploopback->msg, 0, sizeof(ploopback->msg));\n\n\t\tpadapter->ploopback = ploopback;\n\t}\n\n\treturn 0;\n}\n\nstatic void freeLoopback(PADAPTER padapter)\n{\n\tPLOOPBACKDATA ploopback;\n\n\n\tploopback = padapter->ploopback;\n\tif (ploopback) {\n\t\trtw_mfree((u8 *)ploopback, sizeof(LOOPBACKDATA));\n\t\tpadapter->ploopback = NULL;\n\t}\n}\n\nstatic s32 initpseudoadhoc(PADAPTER padapter)\n{\n\tNDIS_802_11_NETWORK_INFRASTRUCTURE networkType;\n\ts32 err;\n\n\tnetworkType = Ndis802_11IBSS;\n\terr = rtw_set_802_11_infrastructure_mode(padapter, networkType);\n\tif (err == _FALSE)\n\t\treturn _FAIL;\n\n\terr = rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK);\n\tif (err == _FAIL)\n\t\treturn _FAIL;\n\n\treturn _SUCCESS;\n}\n\nstatic s32 createpseudoadhoc(PADAPTER padapter)\n{\n\tNDIS_802_11_AUTHENTICATION_MODE authmode;\n\tstruct mlme_priv *pmlmepriv;\n\tNDIS_802_11_SSID *passoc_ssid;\n\tWLAN_BSSID_EX *pdev_network;\n\tu8 *pibss;\n\tu8 ssid[] = \"pseduo_ad-hoc\";\n\ts32 err;\n\t_irqL irqL;\n\n\n\tpmlmepriv = &padapter->mlmepriv;\n\n\tauthmode = Ndis802_11AuthModeOpen;\n\terr = rtw_set_802_11_authentication_mode(padapter, authmode);\n\tif (err == _FALSE)\n\t\treturn _FAIL;\n\n\tpassoc_ssid = &pmlmepriv->assoc_ssid;\n\t_rtw_memset(passoc_ssid, 0, sizeof(NDIS_802_11_SSID));\n\tpassoc_ssid->SsidLength = sizeof(ssid) - 1;\n\t_rtw_memcpy(passoc_ssid->Ssid, ssid, passoc_ssid->SsidLength);\n\n\tpdev_network = &padapter->registrypriv.dev_network;\n\tpibss = padapter->registrypriv.dev_network.MacAddress;\n\t_rtw_memcpy(&pdev_network->Ssid, passoc_ssid, sizeof(NDIS_802_11_SSID));\n\n\trtw_update_registrypriv_dev_network(padapter);\n\trtw_generate_random_ibss(pibss);\n\n\t_enter_critical_bh(&pmlmepriv->lock, &irqL);\n\t/*pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;*/\n\tinit_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);\n\n\t_exit_critical_bh(&pmlmepriv->lock, &irqL);\n\n#if 0\n\terr = rtw_create_ibss_cmd(padapter, 0);\n\tif (err == _FAIL)\n\t\treturn _FAIL;\n#else\n\t{\n\t\tstruct wlan_network *pcur_network;\n\t\tstruct sta_info *psta;\n\n\t\t/* 3  create a new psta */\n\t\tpcur_network = &pmlmepriv->cur_network;\n\n\t\t/* clear psta in the cur_network, if any */\n\t\tpsta = rtw_get_stainfo(&padapter->stapriv, pcur_network->network.MacAddress);\n\t\tif (psta)\n\t\t\trtw_free_stainfo(padapter, psta);\n\n\t\tpsta = rtw_alloc_stainfo(&padapter->stapriv, pibss);\n\t\tif (psta == NULL)\n\t\t\treturn _FAIL;\n\n\t\t/* 3  join psudo AdHoc */\n\t\tpcur_network->join_res = 1;\n\t\tpcur_network->aid = psta->cmn.aid = 1;\n\t\t_rtw_memcpy(&pcur_network->network, pdev_network, get_WLAN_BSSID_EX_sz(pdev_network));\n\n\t\t/* set msr to WIFI_FW_ADHOC_STATE */\n\t\tpadapter->hw_port = HW_PORT0;\n\t\tSet_MSR(padapter, WIFI_FW_ADHOC_STATE);\n\n\t}\n#endif\n\n\treturn _SUCCESS;\n}\n\nstatic struct xmit_frame *createloopbackpkt(PADAPTER padapter, u32 size)\n{\n\tstruct xmit_priv *pxmitpriv;\n\tstruct xmit_frame *pframe;\n\tstruct xmit_buf *pxmitbuf;\n\tstruct pkt_attrib *pattrib;\n\tstruct tx_desc *desc;\n\tu8 *pkt_start, *pkt_end, *ptr;\n\tstruct rtw_ieee80211_hdr *hdr;\n\ts32 bmcast;\n\t_irqL irqL;\n\n\n\tif ((TXDESC_SIZE + WLANHDR_OFFSET + size) > MAX_XMITBUF_SZ)\n\t\treturn NULL;\n\n\tpxmitpriv = &padapter->xmitpriv;\n\tpframe = NULL;\n\n\t/* 2 1. allocate xmit frame */\n\tpframe = rtw_alloc_xmitframe(pxmitpriv);\n\tif (pframe == NULL)\n\t\treturn NULL;\n\tpframe->padapter = padapter;\n\n\t/* 2 2. allocate xmit buffer */\n\t_enter_critical_bh(&pxmitpriv->lock, &irqL);\n\tpxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);\n\t_exit_critical_bh(&pxmitpriv->lock, &irqL);\n\tif (pxmitbuf == NULL) {\n\t\trtw_free_xmitframe(pxmitpriv, pframe);\n\t\treturn NULL;\n\t}\n\n\tpframe->pxmitbuf = pxmitbuf;\n\tpframe->buf_addr = pxmitbuf->pbuf;\n\tpxmitbuf->priv_data = pframe;\n\n\t/* 2 3. update_attrib() */\n\tpattrib = &pframe->attrib;\n\n\t/* init xmitframe attribute */\n\t_rtw_memset(pattrib, 0, sizeof(struct pkt_attrib));\n\n\tpattrib->ether_type = 0x8723;\n\t_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);\n\t_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);\n\t_rtw_memset(pattrib->dst, 0xFF, ETH_ALEN);\n\t_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);\n\n\t/*\tpattrib->dhcp_pkt = 0;\n\t *\tpattrib->pktlen = 0; */\n\tpattrib->ack_policy = 0;\n\t/*\tpattrib->pkt_hdrlen = ETH_HLEN; */\n\tpattrib->hdrlen = WLAN_HDR_A3_LEN;\n\tpattrib->subtype = WIFI_DATA;\n\tpattrib->priority = 0;\n\tpattrib->qsel = pattrib->priority;\n\t/*\tdo_queue_select(padapter, pattrib); */\n\tpattrib->nr_frags = 1;\n\tpattrib->encrypt = 0;\n\tpattrib->bswenc = _FALSE;\n\tpattrib->qos_en = _FALSE;\n\n\tbmcast = IS_MCAST(pattrib->ra);\n\tif (bmcast)\n\t\tpattrib->psta = rtw_get_bcmc_stainfo(padapter);\n\telse\n\t\tpattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));\n\n\tpattrib->mac_id = pattrib->psta->cmn.mac_id;\n\tpattrib->pktlen = size;\n\tpattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen;\n\n\t/* 2 4. fill TX descriptor */\n\tdesc = (struct tx_desc *)pframe->buf_addr;\n\t_rtw_memset(desc, 0, TXDESC_SIZE);\n\n\tfill_default_txdesc(pframe, (u8 *)desc);\n\n\t/* Hw set sequence number */\n\t((PTXDESC)desc)->hwseq_en = 0; /* HWSEQ_EN, 0:disable, 1:enable\n * ((PTXDESC)desc)->hwseq_sel = 0;  */ /* HWSEQ_SEL */\n\n\t((PTXDESC)desc)->disdatafb = 1;\n\n\t/* convert to little endian */\n\tdesc->txdw0 = cpu_to_le32(desc->txdw0);\n\tdesc->txdw1 = cpu_to_le32(desc->txdw1);\n\tdesc->txdw2 = cpu_to_le32(desc->txdw2);\n\tdesc->txdw3 = cpu_to_le32(desc->txdw3);\n\tdesc->txdw4 = cpu_to_le32(desc->txdw4);\n\tdesc->txdw5 = cpu_to_le32(desc->txdw5);\n\tdesc->txdw6 = cpu_to_le32(desc->txdw6);\n\tdesc->txdw7 = cpu_to_le32(desc->txdw7);\n#ifdef CONFIG_PCI_HCI\n\tdesc->txdw8 = cpu_to_le32(desc->txdw8);\n\tdesc->txdw9 = cpu_to_le32(desc->txdw9);\n\tdesc->txdw10 = cpu_to_le32(desc->txdw10);\n\tdesc->txdw11 = cpu_to_le32(desc->txdw11);\n\tdesc->txdw12 = cpu_to_le32(desc->txdw12);\n\tdesc->txdw13 = cpu_to_le32(desc->txdw13);\n\tdesc->txdw14 = cpu_to_le32(desc->txdw14);\n\tdesc->txdw15 = cpu_to_le32(desc->txdw15);\n#endif\n\n\tcal_txdesc_chksum(desc);\n\n\t/* 2 5. coalesce */\n\tpkt_start = pframe->buf_addr + TXDESC_SIZE;\n\tpkt_end = pkt_start + pattrib->last_txcmdsz;\n\n\t/* 3 5.1. make wlan header, make_wlanhdr() */\n\thdr = (struct rtw_ieee80211_hdr *)pkt_start;\n\tset_frame_sub_type(&hdr->frame_ctl, pattrib->subtype);\n\t_rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); /* DA */\n\t_rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); /* SA */\n\t_rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); /* RA, BSSID */\n\n\t/* 3 5.2. make payload */\n\tptr = pkt_start + pattrib->hdrlen;\n\tget_random_bytes(ptr, pkt_end - ptr);\n\n\tpxmitbuf->len = TXDESC_SIZE + pattrib->last_txcmdsz;\n\tpxmitbuf->ptail += pxmitbuf->len;\n\n\treturn pframe;\n}\n\nstatic void freeloopbackpkt(PADAPTER padapter, struct xmit_frame *pframe)\n{\n\tstruct xmit_priv *pxmitpriv;\n\tstruct xmit_buf *pxmitbuf;\n\n\n\tpxmitpriv = &padapter->xmitpriv;\n\tpxmitbuf = pframe->pxmitbuf;\n\n\trtw_free_xmitframe(pxmitpriv, pframe);\n\trtw_free_xmitbuf(pxmitpriv, pxmitbuf);\n}\n\nstatic void printdata(u8 *pbuf, u32 len)\n{\n\tu32 i, val;\n\n\n\tfor (i = 0; (i + 4) <= len; i += 4) {\n\t\tprintk(\"%08X\", *(u32 *)(pbuf + i));\n\t\tif ((i + 4) & 0x1F)\n\t\t\tprintk(\" \");\n\t\telse\n\t\t\tprintk(\"\\n\");\n\t}\n\n\tif (i < len) {\n#ifdef CONFIG_BIG_ENDIAN\n\t\tfor (; i < len, i++)\n\t\t\tprintk(\"%02X\", pbuf + i);\n#else /* CONFIG_LITTLE_ENDIAN */\n#if 0\n\t\tval = 0;\n\t\t_rtw_memcpy(&val, pbuf + i, len - i);\n\t\tprintk(\"%8X\", val);\n#else\n\t\tu8 str[9];\n\t\tu8 n;\n\t\tval = 0;\n\t\tn = len - i;\n\t\t_rtw_memcpy(&val, pbuf + i, n);\n\t\tsprintf(str, \"%08X\", val);\n\t\tn = (4 - n) * 2;\n\t\tprintk(\"%8s\", str + n);\n#endif\n#endif /* CONFIG_LITTLE_ENDIAN */\n\t}\n\tprintk(\"\\n\");\n}\n\nstatic u8 pktcmp(PADAPTER padapter, u8 *txbuf, u32 txsz, u8 *rxbuf, u32 rxsz)\n{\n\tPHAL_DATA_TYPE phal;\n\tstruct recv_stat *prxstat;\n\tstruct recv_stat report;\n\tPRXREPORT prxreport;\n\tu32 drvinfosize;\n\tu32 rxpktsize;\n\tu8 fcssize;\n\tu8 ret = _FALSE;\n\n\tprxstat = (struct recv_stat *)rxbuf;\n\treport.rxdw0 = le32_to_cpu(prxstat->rxdw0);\n\treport.rxdw1 = le32_to_cpu(prxstat->rxdw1);\n\treport.rxdw2 = le32_to_cpu(prxstat->rxdw2);\n\treport.rxdw3 = le32_to_cpu(prxstat->rxdw3);\n\treport.rxdw4 = le32_to_cpu(prxstat->rxdw4);\n\treport.rxdw5 = le32_to_cpu(prxstat->rxdw5);\n\n\tprxreport = (PRXREPORT)&report;\n\tdrvinfosize = prxreport->drvinfosize << 3;\n\trxpktsize = prxreport->pktlen;\n\n\tphal = GET_HAL_DATA(padapter);\n\tif (rtw_hal_rcr_check(padapter, RCR_APPFCS))\n\t\tfcssize = IEEE80211_FCS_LEN;\n\telse\n\t\tfcssize = 0;\n\n\tif ((txsz - TXDESC_SIZE) != (rxpktsize - fcssize)) {\n\t\tRTW_INFO(\"%s: ERROR! size not match tx/rx=%d/%d !\\n\",\n\t\t\t __func__, txsz - TXDESC_SIZE, rxpktsize - fcssize);\n\t\tret = _FALSE;\n\t} else {\n\t\tret = _rtw_memcmp(txbuf + TXDESC_SIZE, \\\n\t\t\t\t  rxbuf + RXDESC_SIZE + drvinfosize, \\\n\t\t\t\t  txsz - TXDESC_SIZE);\n\t\tif (ret == _FALSE)\n\t\t\tRTW_INFO(\"%s: ERROR! pkt content mismatch!\\n\", __func__);\n\t}\n\n\tif (ret == _FALSE) {\n\t\tRTW_INFO(\"\\n%s: TX PKT total=%d, desc=%d, content=%d\\n\",\n\t\t\t __func__, txsz, TXDESC_SIZE, txsz - TXDESC_SIZE);\n\t\tRTW_INFO(\"%s: TX DESC size=%d\\n\", __func__, TXDESC_SIZE);\n\t\tprintdata(txbuf, TXDESC_SIZE);\n\t\tRTW_INFO(\"%s: TX content size=%d\\n\", __func__, txsz - TXDESC_SIZE);\n\t\tprintdata(txbuf + TXDESC_SIZE, txsz - TXDESC_SIZE);\n\n\t\tRTW_INFO(\"\\n%s: RX PKT read=%d offset=%d(%d,%d) content=%d\\n\",\n\t\t\t__func__, rxsz, RXDESC_SIZE + drvinfosize, RXDESC_SIZE, drvinfosize, rxpktsize);\n\t\tif (rxpktsize != 0) {\n\t\t\tRTW_INFO(\"%s: RX DESC size=%d\\n\", __func__, RXDESC_SIZE);\n\t\t\tprintdata(rxbuf, RXDESC_SIZE);\n\t\t\tRTW_INFO(\"%s: RX drvinfo size=%d\\n\", __func__, drvinfosize);\n\t\t\tprintdata(rxbuf + RXDESC_SIZE, drvinfosize);\n\t\t\tRTW_INFO(\"%s: RX content size=%d\\n\", __func__, rxpktsize);\n\t\t\tprintdata(rxbuf + RXDESC_SIZE + drvinfosize, rxpktsize);\n\t\t} else {\n\t\t\tRTW_INFO(\"%s: RX data size=%d\\n\", __func__, rxsz);\n\t\t\tprintdata(rxbuf, rxsz);\n\t\t}\n\t}\n\n\treturn ret;\n}\n\nthread_return lbk_thread(thread_context context)\n{\n\ts32 err;\n\tPADAPTER padapter;\n\tPLOOPBACKDATA ploopback;\n\tstruct xmit_frame *pxmitframe;\n\tu32 cnt, ok, fail, headerlen;\n\tu32 pktsize;\n\tu32 ff_hwaddr;\n\n\n\tpadapter = (PADAPTER)context;\n\tploopback = padapter->ploopback;\n\tif (ploopback == NULL)\n\t\treturn -1;\n\tcnt = 0;\n\tok = 0;\n\tfail = 0;\n\n\tdaemonize(\"%s\", \"RTW_LBK_THREAD\");\n\tallow_signal(SIGTERM);\n\n\tdo {\n\t\tif (ploopback->size == 0) {\n\t\t\tget_random_bytes(&pktsize, 4);\n\t\t\tpktsize = (pktsize % 1535) + 1; /* 1~1535 */\n\t\t} else\n\t\t\tpktsize = ploopback->size;\n\n\t\tpxmitframe = createloopbackpkt(padapter, pktsize);\n\t\tif (pxmitframe == NULL) {\n\t\t\tsprintf(ploopback->msg, \"loopback FAIL! 3. create Packet FAIL!\");\n\t\t\tbreak;\n\t\t}\n\n\t\tploopback->txsize = TXDESC_SIZE + pxmitframe->attrib.last_txcmdsz;\n\t\t_rtw_memcpy(ploopback->txbuf, pxmitframe->buf_addr, ploopback->txsize);\n\t\tff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);\n\t\tcnt++;\n\t\tRTW_INFO(\"%s: wirte port cnt=%d size=%d\\n\", __func__, cnt, ploopback->txsize);\n\t\tpxmitframe->pxmitbuf->pdata = ploopback->txbuf;\n\t\trtw_write_port(padapter, ff_hwaddr, ploopback->txsize, (u8 *)pxmitframe->pxmitbuf);\n\n\t\t/* wait for rx pkt */\n\t\t_rtw_down_sema(&ploopback->sema);\n\n\t\terr = pktcmp(padapter, ploopback->txbuf, ploopback->txsize, ploopback->rxbuf, ploopback->rxsize);\n\t\tif (err == _TRUE)\n\t\t\tok++;\n\t\telse\n\t\t\tfail++;\n\n\t\tploopback->txsize = 0;\n\t\t_rtw_memset(ploopback->txbuf, 0, 0x8000);\n\t\tploopback->rxsize = 0;\n\t\t_rtw_memset(ploopback->rxbuf, 0, 0x8000);\n\n\t\tfreeloopbackpkt(padapter, pxmitframe);\n\t\tpxmitframe = NULL;\n\n\t\tflush_signals_thread();\n\n\t\tif ((ploopback->bstop == _TRUE) ||\n\t\t    ((ploopback->cnt != 0) && (ploopback->cnt == cnt))) {\n\t\t\tu32 ok_rate, fail_rate, all;\n\t\t\tall = cnt;\n\t\t\tok_rate = (ok * 100) / all;\n\t\t\tfail_rate = (fail * 100) / all;\n\t\t\tsprintf(ploopback->msg, \\\n\t\t\t\t\"loopback result: ok=%d%%(%d/%d),error=%d%%(%d/%d)\", \\\n\t\t\t\tok_rate, ok, all, fail_rate, fail, all);\n\t\t\tbreak;\n\t\t}\n\t} while (1);\n\n\tploopback->bstop = _TRUE;\n\n\tthread_exit(NULL);\n\treturn 0;\n}\n\nstatic void loopbackTest(PADAPTER padapter, u32 cnt, u32 size, u8 *pmsg)\n{\n\tPLOOPBACKDATA ploopback;\n\tu32 len;\n\ts32 err;\n\n\n\tploopback = padapter->ploopback;\n\n\tif (ploopback) {\n\t\tif (ploopback->bstop == _FALSE) {\n\t\t\tploopback->bstop = _TRUE;\n\t\t\t_rtw_up_sema(&ploopback->sema);\n\t\t}\n\t\tlen = 0;\n\t\tdo {\n\t\t\tlen = strlen(ploopback->msg);\n\t\t\tif (len)\n\t\t\t\tbreak;\n\t\t\trtw_msleep_os(1);\n\t\t} while (1);\n\t\t_rtw_memcpy(pmsg, ploopback->msg, len + 1);\n\t\tfreeLoopback(padapter);\n\n\t\treturn;\n\t}\n\n\t/* disable dynamic algorithm\t */\n\trtw_phydm_ability_backup(padapter);\n\trtw_phydm_func_disable_all(padapter);\n\n\t/* create pseudo ad-hoc connection */\n\terr = initpseudoadhoc(padapter);\n\tif (err == _FAIL) {\n\t\tsprintf(pmsg, \"loopback FAIL! 1.1 init ad-hoc FAIL!\");\n\t\treturn;\n\t}\n\n\terr = createpseudoadhoc(padapter);\n\tif (err == _FAIL) {\n\t\tsprintf(pmsg, \"loopback FAIL! 1.2 create ad-hoc master FAIL!\");\n\t\treturn;\n\t}\n\n\terr = initLoopback(padapter);\n\tif (err) {\n\t\tsprintf(pmsg, \"loopback FAIL! 2. init FAIL! error code=%d\", err);\n\t\treturn;\n\t}\n\n\tploopback = padapter->ploopback;\n\n\tploopback->bstop = _FALSE;\n\tploopback->cnt = cnt;\n\tploopback->size = size;\n\tploopback->lbkthread = kthread_run(lbk_thread, padapter, \"RTW_LBK_THREAD\");\n\tif (IS_ERR(padapter->lbkthread)) {\n\t\tfreeLoopback(padapter);\n\t\tploopback->lbkthread = NULL;\n\t\tsprintf(pmsg, \"loopback start FAIL! cnt=%d\", cnt);\n\t\treturn;\n\t}\n\n\tsprintf(pmsg, \"loopback start! cnt=%d\", cnt);\n}\n#endif /* CONFIG_MAC_LOOPBACK_DRIVER */\n\nstatic int rtw_test(\n\tstruct net_device *dev,\n\tstruct iw_request_info *info,\n\tunion iwreq_data *wrqu, char *extra)\n{\n\tu32 len;\n\tu8 *pbuf, *pch;\n\tchar *ptmp;\n\tu8 *delim = \",\";\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\n\n\tRTW_INFO(\"+%s\\n\", __func__);\n\tlen = wrqu->data.length;\n\n\tpbuf = (u8 *)rtw_zmalloc(len + 1);\n\tif (pbuf == NULL) {\n\t\tRTW_INFO(\"%s: no memory!\\n\", __func__);\n\t\treturn -ENOMEM;\n\t}\n\n\tif (copy_from_user(pbuf, wrqu->data.pointer, len)) {\n\t\trtw_mfree(pbuf, len + 1);\n\t\tRTW_INFO(\"%s: copy from user fail!\\n\", __func__);\n\t\treturn -EFAULT;\n\t}\n\n\tpbuf[len] = '\\0';\n\n\tRTW_INFO(\"%s: string=\\\"%s\\\"\\n\", __func__, pbuf);\n\n\tptmp = (char *)pbuf;\n\tpch = strsep(&ptmp, delim);\n\tif ((pch == NULL) || (strlen(pch) == 0)) {\n\t\trtw_mfree(pbuf, len);\n\t\tRTW_INFO(\"%s: parameter error(level 1)!\\n\", __func__);\n\t\treturn -EFAULT;\n\t}\n\n#ifdef CONFIG_MAC_LOOPBACK_DRIVER\n\tif (strcmp(pch, \"loopback\") == 0) {\n\t\ts32 cnt = 0;\n\t\tu32 size = 64;\n\n\t\tpch = strsep(&ptmp, delim);\n\t\tif ((pch == NULL) || (strlen(pch) == 0)) {\n\t\t\trtw_mfree(pbuf, len);\n\t\t\tRTW_INFO(\"%s: parameter error(level 2)!\\n\", __func__);\n\t\t\treturn -EFAULT;\n\t\t}\n\n\t\tsscanf(pch, \"%d\", &cnt);\n\t\tRTW_INFO(\"%s: loopback cnt=%d\\n\", __func__, cnt);\n\n\t\tpch = strsep(&ptmp, delim);\n\t\tif ((pch == NULL) || (strlen(pch) == 0)) {\n\t\t\trtw_mfree(pbuf, len);\n\t\t\tRTW_INFO(\"%s: parameter error(level 2)!\\n\", __func__);\n\t\t\treturn -EFAULT;\n\t\t}\n\n\t\tsscanf(pch, \"%d\", &size);\n\t\tRTW_INFO(\"%s: loopback size=%d\\n\", __func__, size);\n\n\t\tloopbackTest(padapter, cnt, size, extra);\n\t\twrqu->data.length = strlen(extra) + 1;\n\n\t\tgoto free_buf;\n\t}\n#endif\n\n\n#ifdef CONFIG_BT_COEXIST\n\tif (strcmp(pch, \"bton\") == 0) {\n\t\trtw_btcoex_SetManualControl(padapter, _FALSE);\n\t\tgoto free_buf;\n\t} else if (strcmp(pch, \"btoff\") == 0) {\n\t\trtw_btcoex_SetManualControl(padapter, _TRUE);\n\t\tgoto free_buf;\n\t}\n#endif\n\n\tif (strcmp(pch, \"h2c\") == 0) {\n\t\tu8 param[8];\n\t\tu8 count = 0;\n\t\tu32 tmp;\n\t\tu8 i;\n\t\tu32 pos;\n\t\tu8 ret;\n\n\t\tdo {\n\t\t\tpch = strsep(&ptmp, delim);\n\t\t\tif ((pch == NULL) || (strlen(pch) == 0))\n\t\t\t\tbreak;\n\n\t\t\tsscanf(pch, \"%x\", &tmp);\n\t\t\tparam[count++] = (u8)tmp;\n\t\t} while (count < 8);\n\n\t\tif (count == 0) {\n\t\t\trtw_mfree(pbuf, len);\n\t\t\tRTW_INFO(\"%s: parameter error(level 2)!\\n\", __func__);\n\t\t\treturn -EFAULT;\n\t\t}\n\n\t\tret = rtw_test_h2c_cmd(padapter, param, count);\n\n\t\tpos = sprintf(extra, \"H2C ID=0x%02x content=\", param[0]);\n\t\tfor (i = 1; i < count; i++)\n\t\t\tpos += sprintf(extra + pos, \"%02x,\", param[i]);\n\t\textra[pos] = 0;\n\t\tpos--;\n\t\tpos += sprintf(extra + pos, \" %s\", ret == _FAIL ? \"FAIL\" : \"OK\");\n\n\t\twrqu->data.length = strlen(extra) + 1;\n\n\t\tgoto free_buf;\n\t}\n\nfree_buf:\n\trtw_mfree(pbuf, len);\n\treturn 0;\n}\n\nstatic iw_handler rtw_handlers[] = {\n\tNULL,\t\t\t\t\t/* SIOCSIWCOMMIT */\n\trtw_wx_get_name,\t\t/* SIOCGIWNAME */\n\tdummy,\t\t\t\t\t/* SIOCSIWNWID */\n\tdummy,\t\t\t\t\t/* SIOCGIWNWID */\n\trtw_wx_set_freq,\t\t/* SIOCSIWFREQ */\n\trtw_wx_get_freq,\t\t/* SIOCGIWFREQ */\n\trtw_wx_set_mode,\t\t/* SIOCSIWMODE */\n\trtw_wx_get_mode,\t\t/* SIOCGIWMODE */\n\tdummy,\t\t\t\t\t/* SIOCSIWSENS */\n\trtw_wx_get_sens,\t\t/* SIOCGIWSENS */\n\tNULL,\t\t\t\t\t/* SIOCSIWRANGE */\n\trtw_wx_get_range,\t\t/* SIOCGIWRANGE */\n\trtw_wx_set_priv,\t\t/* SIOCSIWPRIV */\n\tNULL,\t\t\t\t\t/* SIOCGIWPRIV */\n\tNULL,\t\t\t\t\t/* SIOCSIWSTATS */\n\tNULL,\t\t\t\t\t/* SIOCGIWSTATS */\n\tdummy,\t\t\t\t\t/* SIOCSIWSPY */\n\tdummy,\t\t\t\t\t/* SIOCGIWSPY */\n\tNULL,\t\t\t\t\t/* SIOCGIWTHRSPY */\n\tNULL,\t\t\t\t\t/* SIOCWIWTHRSPY */\n\trtw_wx_set_wap,\t\t/* SIOCSIWAP */\n\trtw_wx_get_wap,\t\t/* SIOCGIWAP */\n\trtw_wx_set_mlme,\t\t/* request MLME operation; uses struct iw_mlme */\n\tdummy,\t\t\t\t\t/* SIOCGIWAPLIST -- depricated */\n\trtw_wx_set_scan,\t\t/* SIOCSIWSCAN */\n\trtw_wx_get_scan,\t\t/* SIOCGIWSCAN */\n\trtw_wx_set_essid,\t\t/* SIOCSIWESSID */\n\trtw_wx_get_essid,\t\t/* SIOCGIWESSID */\n\tdummy,\t\t\t\t\t/* SIOCSIWNICKN */\n\trtw_wx_get_nick,\t\t/* SIOCGIWNICKN */\n\tNULL,\t\t\t\t\t/* -- hole -- */\n\tNULL,\t\t\t\t\t/* -- hole -- */\n\trtw_wx_set_rate,\t\t/* SIOCSIWRATE */\n\trtw_wx_get_rate,\t\t/* SIOCGIWRATE */\n\trtw_wx_set_rts,\t\t\t/* SIOCSIWRTS */\n\trtw_wx_get_rts,\t\t\t/* SIOCGIWRTS */\n\trtw_wx_set_frag,\t\t/* SIOCSIWFRAG */\n\trtw_wx_get_frag,\t\t/* SIOCGIWFRAG */\n\tdummy,\t\t\t\t\t/* SIOCSIWTXPOW */\n\tdummy,\t\t\t\t\t/* SIOCGIWTXPOW */\n\tdummy,\t\t\t\t\t/* SIOCSIWRETRY */\n\trtw_wx_get_retry,\t\t/* SIOCGIWRETRY */\n\trtw_wx_set_enc,\t\t\t/* SIOCSIWENCODE */\n\trtw_wx_get_enc,\t\t\t/* SIOCGIWENCODE */\n\tdummy,\t\t\t\t\t/* SIOCSIWPOWER */\n\trtw_wx_get_power,\t\t/* SIOCGIWPOWER */\n\tNULL,\t\t\t\t\t/*---hole---*/\n\tNULL,\t\t\t\t\t/*---hole---*/\n\trtw_wx_set_gen_ie,\t\t/* SIOCSIWGENIE */\n\tNULL,\t\t\t\t\t/* SIOCGWGENIE */\n\trtw_wx_set_auth,\t\t/* SIOCSIWAUTH */\n\tNULL,\t\t\t\t\t/* SIOCGIWAUTH */\n\trtw_wx_set_enc_ext,\t\t/* SIOCSIWENCODEEXT */\n\tNULL,\t\t\t\t\t/* SIOCGIWENCODEEXT */\n\trtw_wx_set_pmkid,\t\t/* SIOCSIWPMKSA */\n\tNULL,\t\t\t\t\t/*---hole---*/\n};\n\n\nstatic const struct iw_priv_args rtw_private_args[] = {\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x0,\n\t\tIW_PRIV_TYPE_CHAR | 0x7FF, 0, \"write\"\n\t},\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x1,\n\t\tIW_PRIV_TYPE_CHAR | 0x7FF,\n\t\tIW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, \"read\"\n\t},\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x2, 0, 0, \"driver_ext\"\n\t},\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x3, 0, 0, \"mp_ioctl\"\n\t},\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x4,\n\t\tIW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, \"apinfo\"\n\t},\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x5,\n\t\tIW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, \"setpid\"\n\t},\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x6,\n\t\tIW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, \"wps_start\"\n\t},\n\t/* for PLATFORM_MT53XX\t */\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x7,\n\t\tIW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, \"get_sensitivity\"\n\t},\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x8,\n\t\tIW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, \"wps_prob_req_ie\"\n\t},\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x9,\n\t\tIW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, \"wps_assoc_req_ie\"\n\t},\n\n\t/* for RTK_DMP_PLATFORM\t */\n\t{\n\t\tSIOCIWFIRSTPRIV + 0xA,\n\t\tIW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, \"channel_plan\"\n\t},\n\n\t{\n\t\tSIOCIWFIRSTPRIV + 0xB,\n\t\tIW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, \"dbg\"\n\t},\n\t{\n\t\tSIOCIWFIRSTPRIV + 0xC,\n\t\tIW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 3, 0, \"rfw\"\n\t},\n\t{\n\t\tSIOCIWFIRSTPRIV + 0xD,\n\t\tIW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, \"rfr\"\n\t},\n#if 0\n\t{\n\t\tSIOCIWFIRSTPRIV + 0xE, 0, 0, \"wowlan_ctrl\"\n\t},\n#endif\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x10,\n\t\tIW_PRIV_TYPE_CHAR | 1024, 0, \"p2p_set\"\n\t},\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x11,\n\t\tIW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , \"p2p_get\"\n\t},\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x12, 0, 0, \"NULL\"\n\t},\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x13,\n\t\tIW_PRIV_TYPE_CHAR | 64, IW_PRIV_TYPE_CHAR | 64 , \"p2p_get2\"\n\t},\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x14,\n\t\tIW_PRIV_TYPE_CHAR  | 64, 0, \"tdls\"\n\t},\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x15,\n\t\tIW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | 1024 , \"tdls_get\"\n\t},\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x16,\n\t\tIW_PRIV_TYPE_CHAR | 64, 0, \"pm_set\"\n\t},\n#ifdef CONFIG_RTW_80211K\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x17,\n\t\tIW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | 1024 , \"rrm\"\n\t},\n#else\n\t{SIOCIWFIRSTPRIV + 0x17, IW_PRIV_TYPE_CHAR | 1024 , 0 , \"NULL\"},\n#endif\n\t{SIOCIWFIRSTPRIV + 0x18, IW_PRIV_TYPE_CHAR | IFNAMSIZ , 0 , \"rereg_nd_name\"},\n#ifdef CONFIG_MP_INCLUDED\n\t{SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0,  \"NULL\"},\n\t{SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"NULL\"},\n#else\n\t{SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0,  \"NULL\"},\n\t{SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"efuse_get\"},\n#endif\n\t{\n\t\tSIOCIWFIRSTPRIV + 0x1D,\n\t\tIW_PRIV_TYPE_CHAR | 40, IW_PRIV_TYPE_CHAR | 0x7FF, \"test\"\n\t},\n\n\t{ SIOCIWFIRSTPRIV + 0x0E, IW_PRIV_TYPE_CHAR | 1024, 0 , \"\"},  /* set  */\n\t{ SIOCIWFIRSTPRIV + 0x0F, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , \"\"},/* get\n * --- sub-ioctls definitions --- */\n\n#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE\n\t{ VENDOR_IE_SET, IW_PRIV_TYPE_CHAR | 1024 , 0 , \"vendor_ie_set\" },\n\t{ VENDOR_IE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"vendor_ie_get\" },\n#endif\n#if defined(CONFIG_RTL8723B)\n\t{ MP_SetBT, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_setbt\" },\n\t{ MP_DISABLE_BT_COEXIST, IW_PRIV_TYPE_CHAR | 1024, 0, \"mp_disa_btcoex\"},\n#endif\n#ifdef CONFIG_WOWLAN\n\t{ MP_WOW_ENABLE , IW_PRIV_TYPE_CHAR | 1024, 0, \"wow_mode\" },\n\t{ MP_WOW_SET_PATTERN , IW_PRIV_TYPE_CHAR | 1024, 0, \"wow_set_pattern\" },\n#endif\n#ifdef CONFIG_AP_WOWLAN\n\t{ MP_AP_WOW_ENABLE , IW_PRIV_TYPE_CHAR | 1024, 0, \"ap_wow_mode\" }, /* set  */\n#endif\n#ifdef CONFIG_SDIO_INDIRECT_ACCESS\n\t{ MP_SD_IREAD, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"sd_iread\" },\n\t{ MP_SD_IWRITE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"sd_iwrite\" },\n#endif\n};\n\n\nstatic const struct iw_priv_args rtw_mp_private_args[] = {\n\t/* --- sub-ioctls definitions --- */\n#ifdef CONFIG_MP_INCLUDED\n\t{ MP_START , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_start\" },\n\t{ MP_PHYPARA, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_phypara\" },\n\t{ MP_STOP , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_stop\" },\n\t{ MP_CHANNEL , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_channel\" },\n\t{ MP_CHL_OFFSET , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_ch_offset\" },\n\t{ MP_BANDWIDTH , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_bandwidth\"},\n\t{ MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_rate\" },\n\t{ MP_RESET_STATS , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_reset_stats\"},\n\t{ MP_QUERY , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , \"mp_query\"},\n\t{ READ_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"read_reg\" },\n\t{ MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_rate\" },\n\t{ READ_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"read_rf\" },\n\t{ MP_PSD , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_psd\"},\n\t{ MP_DUMP, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_dump\" },\n\t{ MP_TXPOWER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_txpower\"},\n\t{ MP_ANT_TX , IW_PRIV_TYPE_CHAR | 1024,  IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_ant_tx\"},\n\t{ MP_ANT_RX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_ant_rx\"},\n\t{ WRITE_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"write_reg\" },\n\t{ WRITE_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"write_rf\" },\n\t{ MP_CTX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_ctx\"},\n\t{ MP_ARX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_arx\"},\n\t{ MP_THER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_ther\"},\n\t{ EFUSE_SET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"efuse_set\" },\n\t{ EFUSE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"efuse_get\" },\n\t{ MP_PWRTRK , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_pwrtrk\"},\n\t{ MP_QueryDrvStats, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_drvquery\" },\n\t{ MP_IOCTL, IW_PRIV_TYPE_CHAR | 1024, 0, \"mp_ioctl\"},\n\t{ MP_SetRFPathSwh, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_setrfpath\" },\n\t{ MP_PwrCtlDM, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_pwrctldm\" },\n\t{ MP_GET_TXPOWER_INX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_get_txpower\" },\n\t{ MP_GETVER, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_priv_ver\" },\n\t{ MP_MON, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_mon\" },\n\t{ EFUSE_BT_MASK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"efuse_bt_mask\" },\n\t{ EFUSE_MASK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"efuse_mask\" },\n\t{ EFUSE_FILE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"efuse_file\" },\n\t{ MP_TX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_tx\" },\n\t{ MP_RX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_rx\" },\n\t{ MP_HW_TX_MODE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_hxtx\" },\n\t{ MP_PWRLMT, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_pwrlmt\" },\n\t{ MP_PWRBYRATE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_pwrbyrate\" },\n\t{ CTA_TEST, IW_PRIV_TYPE_CHAR | 1024, 0, \"cta_test\"},\n\t{ MP_IQK, IW_PRIV_TYPE_CHAR | 1024, 0, \"mp_iqk\"},\n\t{ MP_LCK, IW_PRIV_TYPE_CHAR | 1024, 0, \"mp_lck\"},\n\t{ BT_EFUSE_FILE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"bt_efuse_file\" },\n\t{ MP_SWRFPath, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_swrfpath\" },\n\t{ MP_LINK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_link\" },\n\t{ MP_DPK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_dpk\"},\n\t{ MP_DPK_TRK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"mp_dpk_trk\" },\n#ifdef CONFIG_RTW_CUSTOMER_STR\n\t{ MP_CUSTOMER_STR, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, \"customer_str\" },\n#endif\n\n#endif /* CONFIG_MP_INCLUDED */\n};\n\nstatic iw_handler rtw_private_handler[] = {\n\trtw_wx_write32,\t\t\t\t\t/* 0x00 */\n\trtw_wx_read32,\t\t\t\t\t/* 0x01 */\n\tNULL,\t\t\t\t\t/* 0x02 */\n#ifdef MP_IOCTL_HDL\n\trtw_mp_ioctl_hdl,\t\t\t\t/* 0x03 */\n#else\n\trtw_wx_priv_null,\n#endif\n\t/* for MM DTV platform */\n\trtw_get_ap_info,\t\t\t\t\t/* 0x04 */\n\n\trtw_set_pid,\t\t\t\t\t\t/* 0x05 */\n\trtw_wps_start,\t\t\t\t\t/* 0x06 */\n\n\t/* for PLATFORM_MT53XX */\n\trtw_wx_get_sensitivity,\t\t\t/* 0x07 */\n\trtw_wx_set_mtk_wps_probe_ie,\t/* 0x08 */\n\trtw_wx_set_mtk_wps_ie,\t\t\t/* 0x09 */\n\n\t/* for RTK_DMP_PLATFORM\n\t * Set Channel depend on the country code */\n\trtw_wx_set_channel_plan,\t\t/* 0x0A */\n\n\trtw_dbg_port,\t\t\t\t\t/* 0x0B */\n\trtw_wx_write_rf,\t\t\t\t\t/* 0x0C */\n\trtw_wx_read_rf,\t\t\t\t\t/* 0x0D */\n\n\trtw_priv_set,\t\t\t\t\t/*0x0E*/\n\trtw_priv_get,\t\t\t\t\t/*0x0F*/\n\n\trtw_p2p_set,\t\t\t\t\t/* 0x10 */\n\trtw_p2p_get,\t\t\t\t\t/* 0x11 */\n\tNULL,\t\t\t\t\t\t\t/* 0x12 */\n\trtw_p2p_get2,\t\t\t\t\t/* 0x13 */\n\n\trtw_tdls,\t\t\t\t\t\t/* 0x14 */\n\trtw_tdls_get,\t\t\t\t\t/* 0x15 */\n\n\trtw_pm_set,\t\t\t\t\t\t/* 0x16 */\n#ifdef CONFIG_RTW_80211K\n\trtw_wx_priv_rrm,\t\t\t\t/* 0x17 */\n#else\n\trtw_wx_priv_null,\t\t\t\t/* 0x17 */\n#endif\n\trtw_rereg_nd_name,\t\t\t\t/* 0x18 */\n\trtw_wx_priv_null,\t\t\t\t/* 0x19 */\n#ifdef CONFIG_MP_INCLUDED\n\trtw_wx_priv_null,\t\t\t\t/* 0x1A */\n\trtw_wx_priv_null,\t\t\t\t/* 0x1B */\n#else\n\trtw_wx_priv_null,\t\t\t\t/* 0x1A */\n\trtw_mp_efuse_get,\t\t\t\t/* 0x1B */\n#endif\n\tNULL,\t\t\t\t\t\t\t/* 0x1C is reserved for hostapd */\n\trtw_test,\t\t\t\t\t\t/* 0x1D */\n};\n\n#if WIRELESS_EXT >= 17\nstatic struct iw_statistics *rtw_get_wireless_stats(struct net_device *dev)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct iw_statistics *piwstats = &padapter->iwstats;\n\tint tmp_level = 0;\n\tint tmp_qual = 0;\n\tint tmp_noise = 0;\n\n\tif (check_fwstate(&padapter->mlmepriv, _FW_LINKED) != _TRUE) {\n\t\tpiwstats->qual.qual = 0;\n\t\tpiwstats->qual.level = 0;\n\t\tpiwstats->qual.noise = 0;\n\t\t/* RTW_INFO(\"No link  level:%d, qual:%d, noise:%d\\n\", tmp_level, tmp_qual, tmp_noise); */\n\t} else {\n#ifdef CONFIG_SIGNAL_DISPLAY_DBM\n\t\ttmp_level = translate_percentage_to_dbm(padapter->recvpriv.signal_strength);\n#else\n\t\ttmp_level = padapter->recvpriv.signal_strength;\n#endif\n\n\t\ttmp_qual = padapter->recvpriv.signal_qual;\n\t\t#ifdef CONFIG_BACKGROUND_NOISE_MONITOR\n\t\tif (IS_NM_ENABLE(padapter)) {\n\t\t\ttmp_noise = rtw_noise_measure_curchan(padapter);\n\t\t\t#ifndef CONFIG_SIGNAL_DISPLAY_DBM\n\t\t\ttmp_noise = translate_dbm_to_percentage(tmp_noise);/*percentage*/\n\t\t\t#endif\n\t\t}\n\t\t#endif\n\t\t/* RTW_INFO(\"level:%d, qual:%d, noise:%d, rssi (%d)\\n\", tmp_level, tmp_qual, tmp_noise,padapter->recvpriv.rssi); */\n\n\t\tpiwstats->qual.level = tmp_level;\n\t\tpiwstats->qual.qual = tmp_qual;\n\t\tpiwstats->qual.noise = tmp_noise;\n\t}\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 14))\n\tpiwstats->qual.updated = IW_QUAL_ALL_UPDATED ;/* |IW_QUAL_DBM; */\n#else\n#ifdef RTK_DMP_PLATFORM\n\t/* IW_QUAL_DBM= 0x8, if driver use this flag, wireless extension will show value of dbm. */\n\t/* remove this flag for show percentage 0~100 */\n\tpiwstats->qual.updated = 0x07;\n#else\n\tpiwstats->qual.updated = 0x0f;\n#endif\n#endif\n\n#ifdef CONFIG_SIGNAL_DISPLAY_DBM\n\tpiwstats->qual.updated = piwstats->qual.updated | IW_QUAL_DBM;\n#endif\n\n\treturn &padapter->iwstats;\n}\n#endif\n\n#ifdef CONFIG_WIRELESS_EXT\nstruct iw_handler_def rtw_handlers_def = {\n\t.standard = rtw_handlers,\n\t.num_standard = sizeof(rtw_handlers) / sizeof(iw_handler),\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33)) || defined(CONFIG_WEXT_PRIV)\n\t.private = rtw_private_handler,\n\t.private_args = (struct iw_priv_args *)rtw_private_args,\n\t.num_private = sizeof(rtw_private_handler) / sizeof(iw_handler),\n\t.num_private_args = sizeof(rtw_private_args) / sizeof(struct iw_priv_args),\n#endif\n#if WIRELESS_EXT >= 17\n\t.get_wireless_stats = rtw_get_wireless_stats,\n#endif\n};\n#endif\n\n/* copy from net/wireless/wext.c start\n * ----------------------------------------------------------------\n *\n * Calculate size of private arguments\n */\nstatic const char iw_priv_type_size[] = {\n\t0,                              /* IW_PRIV_TYPE_NONE */\n\t1,                              /* IW_PRIV_TYPE_BYTE */\n\t1,                              /* IW_PRIV_TYPE_CHAR */\n\t0,                              /* Not defined */\n\tsizeof(__u32),                  /* IW_PRIV_TYPE_INT */\n\tsizeof(struct iw_freq),         /* IW_PRIV_TYPE_FLOAT */\n\tsizeof(struct sockaddr),        /* IW_PRIV_TYPE_ADDR */\n\t0,                              /* Not defined */\n};\n\nstatic int get_priv_size(__u16 args)\n{\n\tint num = args & IW_PRIV_SIZE_MASK;\n\tint type = (args & IW_PRIV_TYPE_MASK) >> 12;\n\n\treturn num * iw_priv_type_size[type];\n}\n/* copy from net/wireless/wext.c end */\n\n\nstatic int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq_data)\n{\n\tint err = 0;\n\tu8 *input = NULL;\n\tu32 input_len = 0;\n\tconst char delim[] = \" \";\n\tu8 *output = NULL;\n\tu32 output_len = 0;\n\tu32 count = 0;\n\tu8 *buffer = NULL;\n\tu32 buffer_len = 0;\n\tchar *ptr = NULL;\n\tu8 cmdname[17] = {0}; /* IFNAMSIZ+1 */\n\tu32 cmdlen;\n\ts32 len;\n\tu8 *extra = NULL;\n\tu32 extra_size = 0;\n\n\ts32 k;\n\tconst iw_handler *priv;\t\t/* Private ioctl */\n\tconst struct iw_priv_args *priv_args;\t/* Private ioctl description */\n\tconst struct iw_priv_args *mp_priv_args;\t/*MP Private ioctl description */\n\tconst struct iw_priv_args *sel_priv_args;\t/*Selected Private ioctl description */\n\tu32 num_priv;\t\t\t\t/* Number of ioctl */\n\tu32 num_priv_args;\t\t\t/* Number of descriptions */\n\tu32 num_mp_priv_args;\t\t\t/*Number of MP descriptions */\n\tu32 num_sel_priv_args;\t\t\t/*Number of Selected descriptions */\n\tiw_handler handler;\n\tint temp;\n\tint subcmd = 0;\t\t\t\t/* sub-ioctl index */\n\tint offset = 0;\t\t\t\t/* Space for sub-ioctl index */\n\n\tunion iwreq_data wdata;\n\n\t_rtw_memcpy(&wdata, wrq_data, sizeof(wdata));\n\n\tinput_len = wdata.data.length;\n\tif (!input_len)\n\t\treturn -EINVAL;\n\tinput = rtw_zmalloc(input_len);\n\tif (NULL == input)\n\t\treturn -ENOMEM;\n\tif (copy_from_user(input, wdata.data.pointer, input_len)) {\n\t\terr = -EFAULT;\n\t\tgoto exit;\n\t}\n\tinput[input_len - 1] = '\\0';\n\tptr = input;\n\tlen = input_len;\n\n\tif (ptr == NULL) {\n\t\terr = -EOPNOTSUPP;\n\t\tgoto exit;\n\t}\n\n\tsscanf(ptr, \"%16s\", cmdname);\n\tcmdlen = strlen(cmdname);\n\tRTW_DBG(\"%s: cmd=%s\\n\", __func__, cmdname);\n\n\t/* skip command string */\n\tif (cmdlen > 0)\n\t\tcmdlen += 1; /* skip one space */\n\tptr += cmdlen;\n\tlen -= cmdlen;\n\tRTW_DBG(\"%s: parameters=%s\\n\", __func__, ptr);\n\n\tpriv = rtw_private_handler;\n\tpriv_args = rtw_private_args;\n\tmp_priv_args = rtw_mp_private_args;\n\tnum_priv = sizeof(rtw_private_handler) / sizeof(iw_handler);\n\tnum_priv_args = sizeof(rtw_private_args) / sizeof(struct iw_priv_args);\n\tnum_mp_priv_args = sizeof(rtw_mp_private_args) / sizeof(struct iw_priv_args);\n\n\tif (num_priv_args == 0) {\n\t\terr = -EOPNOTSUPP;\n\t\tgoto exit;\n\t}\n\n\t/* Search the correct ioctl */\n\tk = -1;\n\tsel_priv_args = priv_args;\n\tnum_sel_priv_args = num_priv_args;\n\twhile\n\t((++k < num_sel_priv_args) && strcmp(sel_priv_args[k].name, cmdname))\n\t\t;\n\n\t/* If not found... */\n\tif (k == num_sel_priv_args) {\n\t\tk = -1;\n\t\tsel_priv_args = mp_priv_args;\n\t\tnum_sel_priv_args = num_mp_priv_args;\n\t\twhile\n\t\t((++k < num_sel_priv_args) && strcmp(sel_priv_args[k].name, cmdname))\n\t\t\t;\n\n\t\tif (k == num_sel_priv_args) {\n\t\t\terr = -EOPNOTSUPP;\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\t/* Watch out for sub-ioctls ! */\n\tif (sel_priv_args[k].cmd < SIOCDEVPRIVATE) {\n\t\tint j = -1;\n\n\t\t/* Find the matching *real* ioctl */\n\t\twhile ((++j < num_priv_args) && ((priv_args[j].name[0] != '\\0') ||\n\t\t\t (priv_args[j].set_args != sel_priv_args[k].set_args) ||\n\t\t\t (priv_args[j].get_args != sel_priv_args[k].get_args)))\n\t\t\t;\n\n\t\t/* If not found... */\n\t\tif (j == num_priv_args) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* Save sub-ioctl number */\n\t\tsubcmd = sel_priv_args[k].cmd;\n\t\t/* Reserve one int (simplify alignment issues) */\n\t\toffset = sizeof(__u32);\n\t\t/* Use real ioctl definition from now on */\n\t\tk = j;\n\t}\n\n\tbuffer = rtw_zmalloc(4096);\n\tif (NULL == buffer) {\n\t\terr = -ENOMEM;\n\t\tgoto exit;\n\t}\n\n\tif (k >= num_priv_args) {\n\t\terr = -EINVAL;\n\t\tgoto exit;\n\t}\n\n\t/* If we have to set some data */\n\tif ((priv_args[k].set_args & IW_PRIV_TYPE_MASK) &&\n\t    (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) {\n\t\tu8 *str;\n\n\t\tswitch (priv_args[k].set_args & IW_PRIV_TYPE_MASK) {\n\t\tcase IW_PRIV_TYPE_BYTE:\n\t\t\t/* Fetch args */\n\t\t\tcount = 0;\n\t\t\tdo {\n\t\t\t\tstr = strsep(&ptr, delim);\n\t\t\t\tif (NULL == str)\n\t\t\t\t\tbreak;\n\t\t\t\tsscanf(str, \"%i\", &temp);\n\t\t\t\tbuffer[count++] = (u8)temp;\n\t\t\t} while (1);\n\t\t\tbuffer_len = count;\n\n\t\t\t/* Number of args to fetch */\n\t\t\twdata.data.length = count;\n\t\t\tif (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK))\n\t\t\t\twdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK;\n\n\t\t\tbreak;\n\n\t\tcase IW_PRIV_TYPE_INT:\n\t\t\t/* Fetch args */\n\t\t\tcount = 0;\n\t\t\tdo {\n\t\t\t\tstr = strsep(&ptr, delim);\n\t\t\t\tif (NULL == str)\n\t\t\t\t\tbreak;\n\t\t\t\tsscanf(str, \"%i\", &temp);\n\t\t\t\t((s32 *)buffer)[count++] = (s32)temp;\n\t\t\t} while (1);\n\t\t\tbuffer_len = count * sizeof(s32);\n\n\t\t\t/* Number of args to fetch */\n\t\t\twdata.data.length = count;\n\t\t\tif (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK))\n\t\t\t\twdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK;\n\n\t\t\tbreak;\n\n\t\tcase IW_PRIV_TYPE_CHAR:\n\t\t\tif (len > 0) {\n\t\t\t\t/* Size of the string to fetch */\n\t\t\t\twdata.data.length = len;\n\t\t\t\tif (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK))\n\t\t\t\t\twdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK;\n\n\t\t\t\t/* Fetch string */\n\t\t\t\t_rtw_memcpy(buffer, ptr, wdata.data.length);\n\t\t\t} else {\n\t\t\t\twdata.data.length = 1;\n\t\t\t\tbuffer[0] = '\\0';\n\t\t\t}\n\t\t\tbuffer_len = wdata.data.length;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tRTW_INFO(\"%s: Not yet implemented...\\n\", __func__);\n\t\t\terr = -1;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) &&\n\t\t    (wdata.data.length != (priv_args[k].set_args & IW_PRIV_SIZE_MASK))) {\n\t\t\tRTW_INFO(\"%s: The command %s needs exactly %d argument(s)...\\n\",\n\t\t\t\t__func__, cmdname, priv_args[k].set_args & IW_PRIV_SIZE_MASK);\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t}   /* if args to set */\n\telse\n\t\twdata.data.length = 0L;\n\n\t/* Those two tests are important. They define how the driver\n\t* will have to handle the data */\n\tif ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) &&\n\t    ((get_priv_size(priv_args[k].set_args) + offset) <= IFNAMSIZ)) {\n\t\t/* First case : all SET args fit within wrq */\n\t\tif (offset)\n\t\t\twdata.mode = subcmd;\n\t\t_rtw_memcpy(wdata.name + offset, buffer, IFNAMSIZ - offset);\n\t} else {\n\t\tif ((priv_args[k].set_args == 0) &&\n\t\t    (priv_args[k].get_args & IW_PRIV_SIZE_FIXED) &&\n\t\t    (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ)) {\n\t\t\t/* Second case : no SET args, GET args fit within wrq */\n\t\t\tif (offset)\n\t\t\t\twdata.mode = subcmd;\n\t\t} else {\n\t\t\t/* Third case : args won't fit in wrq, or variable number of args */\n\t\t\tif (copy_to_user(wdata.data.pointer, buffer, buffer_len)) {\n\t\t\t\terr = -EFAULT;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\twdata.data.flags = subcmd;\n\t\t}\n\t}\n\n\trtw_mfree(input, input_len);\n\tinput = NULL;\n\n\textra_size = 0;\n\tif (IW_IS_SET(priv_args[k].cmd)) {\n\t\t/* Size of set arguments */\n\t\textra_size = get_priv_size(priv_args[k].set_args);\n\n\t\t/* Does it fits in iwr ? */\n\t\tif ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) &&\n\t\t    ((extra_size + offset) <= IFNAMSIZ))\n\t\t\textra_size = 0;\n\t} else {\n\t\t/* Size of get arguments */\n\t\textra_size = get_priv_size(priv_args[k].get_args);\n\n\t\t/* Does it fits in iwr ? */\n\t\tif ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) &&\n\t\t    (extra_size <= IFNAMSIZ))\n\t\t\textra_size = 0;\n\t}\n\n\tif (extra_size == 0) {\n\t\textra = (u8 *)&wdata;\n\t\trtw_mfree(buffer, 4096);\n\t\tbuffer = NULL;\n\t} else\n\t\textra = buffer;\n\n\thandler = priv[priv_args[k].cmd - SIOCIWFIRSTPRIV];\n\terr = handler(dev, NULL, &wdata, extra);\n\n\t/* If we have to get some data */\n\tif ((priv_args[k].get_args & IW_PRIV_TYPE_MASK) &&\n\t    (priv_args[k].get_args & IW_PRIV_SIZE_MASK)) {\n\t\tint j;\n\t\tint n = 0;\t/* number of args */\n\t\tu8 str[20] = {0};\n\n\t\t/* Check where is the returned data */\n\t\tif ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) &&\n\t\t    (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ))\n\t\t\tn = priv_args[k].get_args & IW_PRIV_SIZE_MASK;\n\t\telse\n\t\t\tn = wdata.data.length;\n\n\t\toutput = rtw_zmalloc(4096);\n\t\tif (NULL == output) {\n\t\t\terr =  -ENOMEM;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tswitch (priv_args[k].get_args & IW_PRIV_TYPE_MASK) {\n\t\tcase IW_PRIV_TYPE_BYTE:\n\t\t\t/* Display args */\n\t\t\tfor (j = 0; j < n; j++) {\n\t\t\t\tsprintf(str, \"%d  \", extra[j]);\n\t\t\t\tlen = strlen(str);\n\t\t\t\toutput_len = strlen(output);\n\t\t\t\tif ((output_len + len + 1) > 4096) {\n\t\t\t\t\terr = -E2BIG;\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t\t_rtw_memcpy(output + output_len, str, len);\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase IW_PRIV_TYPE_INT:\n\t\t\t/* Display args */\n\t\t\tfor (j = 0; j < n; j++) {\n\t\t\t\tsprintf(str, \"%d  \", ((__s32 *)extra)[j]);\n\t\t\t\tlen = strlen(str);\n\t\t\t\toutput_len = strlen(output);\n\t\t\t\tif ((output_len + len + 1) > 4096) {\n\t\t\t\t\terr = -E2BIG;\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t\t_rtw_memcpy(output + output_len, str, len);\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase IW_PRIV_TYPE_CHAR:\n\t\t\t/* Display args */\n\t\t\t_rtw_memcpy(output, extra, n);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tRTW_INFO(\"%s: Not yet implemented...\\n\", __func__);\n\t\t\terr = -1;\n\t\t\tgoto exit;\n\t\t}\n\n\t\toutput_len = strlen(output) + 1;\n\t\twrq_data->data.length = output_len;\n\t\tif (copy_to_user(wrq_data->data.pointer, output, output_len)) {\n\t\t\terr = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\t}   /* if args to set */\n\telse\n\t\twrq_data->data.length = 0;\n\nexit:\n\tif (input)\n\t\trtw_mfree(input, input_len);\n\tif (buffer)\n\t\trtw_mfree(buffer, 4096);\n\tif (output)\n\t\trtw_mfree(output, 4096);\n\n\treturn err;\n}\n\n#ifdef CONFIG_COMPAT\nstatic int rtw_ioctl_compat_wext_private(struct net_device *dev, struct ifreq *rq)\n{\n\tstruct compat_iw_point iwp_compat;\n\tunion iwreq_data wrq_data;\n\tint err = 0;\n\tRTW_DBG(\"%s:...\\n\", __func__);\n\tif (copy_from_user(&iwp_compat, rq->ifr_ifru.ifru_data, sizeof(struct compat_iw_point)))\n\t\treturn -EFAULT;\n\n\twrq_data.data.pointer = compat_ptr(iwp_compat.pointer);\n\twrq_data.data.length = iwp_compat.length;\n\twrq_data.data.flags = iwp_compat.flags;\n\n\terr = _rtw_ioctl_wext_private(dev, &wrq_data);\n\n\tiwp_compat.pointer = ptr_to_compat(wrq_data.data.pointer);\n\tiwp_compat.length = wrq_data.data.length;\n\tiwp_compat.flags = wrq_data.data.flags;\n\tif (copy_to_user(rq->ifr_ifru.ifru_data, &iwp_compat, sizeof(struct compat_iw_point)))\n\t\treturn -EFAULT;\n\n\treturn err;\n}\n#endif /* CONFIG_COMPAT */\n\nstatic int rtw_ioctl_standard_wext_private(struct net_device *dev, struct ifreq *rq)\n{\n\tstruct iw_point *iwp;\n\tunion iwreq_data wrq_data;\n\tint err = 0;\n\tiwp = &wrq_data.data;\n\tRTW_DBG(\"%s:...\\n\", __func__);\n\tif (copy_from_user(iwp, rq->ifr_ifru.ifru_data, sizeof(struct iw_point)))\n\t\treturn -EFAULT;\n\n\terr = _rtw_ioctl_wext_private(dev, &wrq_data);\n\n\tif (copy_to_user(rq->ifr_ifru.ifru_data, iwp, sizeof(struct iw_point)))\n\t\treturn -EFAULT;\n\n\treturn err;\n}\n\nstatic int rtw_ioctl_wext_private(struct net_device *dev, struct ifreq *rq)\n{\n#ifdef CONFIG_COMPAT\n#if (KERNEL_VERSION(4, 6, 0) > LINUX_VERSION_CODE)\n\tif (is_compat_task())\n#else\n\tif (in_compat_syscall())\n#endif\n\t\treturn rtw_ioctl_compat_wext_private(dev, rq);\n\telse\n#endif /* CONFIG_COMPAT */\n\t\treturn rtw_ioctl_standard_wext_private(dev, rq);\n}\n\nint rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)\n{\n\tstruct iwreq *wrq = (struct iwreq *)rq;\n\tint ret = 0;\n\n\tswitch (cmd) {\n\tcase RTL_IOCTL_WPA_SUPPLICANT:\n\t\tret = wpa_supplicant_ioctl(dev, &wrq->u.data);\n\t\tbreak;\n#ifdef CONFIG_AP_MODE\n\tcase RTL_IOCTL_HOSTAPD:\n\t\tret = rtw_hostapd_ioctl(dev, &wrq->u.data);\n\t\tbreak;\n#ifdef CONFIG_WIRELESS_EXT\n\tcase SIOCSIWMODE:\n\t\tret = rtw_wx_set_mode(dev, NULL, &wrq->u, NULL);\n\t\tbreak;\n#endif\n#endif /* CONFIG_AP_MODE */\n\tcase SIOCDEVPRIVATE:\n\t\tret = rtw_ioctl_wext_private(dev, rq);\n\t\tbreak;\n\tcase (SIOCDEVPRIVATE+1):\n\t\tret = rtw_android_priv_cmd(dev, rq, cmd);\n\t\tbreak;\n\tdefault:\n\t\tret = -EOPNOTSUPP;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n"
  },
  {
    "path": "os_dep/linux/ioctl_mp.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#if defined(CONFIG_MP_INCLUDED)\n\n#include <drv_types.h>\n#include <rtw_mp.h>\n#include \"../../hal/phydm/phydm_precomp.h\"\n\n\n#if defined(CONFIG_RTL8723B)\n\t#include <rtw_bt_mp.h>\n#endif\n\n/*\n * Input Format: %s,%d,%d\n *\t%s is width, could be\n *\t\t\"b\" for 1 byte\n *\t\t\"w\" for WORD (2 bytes)\n *\t\t\"dw\" for DWORD (4 bytes)\n *\t1st %d is address(offset)\n *\t2st %d is data to write\n */\nint rtw_mp_write_reg(struct net_device *dev,\n\t\t     struct iw_request_info *info,\n\t\t     struct iw_point *wrqu, char *extra)\n{\n\tchar *pch, *pnext;\n\tchar *width_str;\n\tchar width;\n\tu32 addr, data;\n\tint ret;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tchar input[wrqu->length + 1];\n\n\t_rtw_memset(input, 0, sizeof(input));\n\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tinput[wrqu->length] = '\\0';\n\n\t_rtw_memset(extra, 0, wrqu->length);\n\n\tpch = input;\n\n\tpnext = strpbrk(pch, \" ,.-\");\n\tif (pnext == NULL)\n\t\treturn -EINVAL;\n\t*pnext = 0;\n\twidth_str = pch;\n\n\tpch = pnext + 1;\n\tpnext = strpbrk(pch, \" ,.-\");\n\tif (pnext == NULL)\n\t\treturn -EINVAL;\n\t*pnext = 0;\n\t/*addr = simple_strtoul(pch, &ptmp, 16);\n\t_rtw_memset(buf, '\\0', sizeof(buf));\n\t_rtw_memcpy(buf, pch, pnext-pch);\n\tret = kstrtoul(buf, 16, &addr);*/\n\tret = sscanf(pch, \"%x\", &addr);\n\tif (addr > MP_READ_REG_MAX_OFFSET)\n\t\treturn -EINVAL;\n\n\tpch = pnext + 1;\n\tpnext = strpbrk(pch, \" ,.-\");\n\tif ((pch - input) >= wrqu->length)\n\t\treturn -EINVAL;\n\t/*data = simple_strtoul(pch, &ptmp, 16);*/\n\tret = sscanf(pch, \"%x\", &data);\n\tRTW_INFO(\"data=%x,addr=%x\\n\", (u32)data, (u32)addr);\n\tret = 0;\n\twidth = width_str[0];\n\tswitch (width) {\n\tcase 'b':\n\t\t/* 1 byte*/\n\t\tif (data > 0xFF) {\n\t\t\tret = -EINVAL;\n\t\t\tbreak;\n\t\t}\n\t\trtw_write8(padapter, addr, data);\n\t\tbreak;\n\tcase 'w':\n\t\t/* 2 bytes*/\n\t\tif (data > 0xFFFF) {\n\t\t\tret = -EINVAL;\n\t\t\tbreak;\n\t\t}\n\t\trtw_write16(padapter, addr, data);\n\t\tbreak;\n\tcase 'd':\n\t\t/* 4 bytes*/\n\t\trtw_write32(padapter, addr, data);\n\t\tbreak;\n\tdefault:\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\n\n/*\n * Input Format: %s,%d\n *\t%s is width, could be\n *\t\t\"b\" for 1 byte\n *\t\t\"w\" for WORD (2 bytes)\n *\t\t\"dw\" for DWORD (4 bytes)\n *\t%d is address(offset)\n *\n * Return:\n *\t%d for data readed\n */\nint rtw_mp_read_reg(struct net_device *dev,\n\t\t    struct iw_request_info *info,\n\t\t    struct iw_point *wrqu, char *extra)\n{\n\tchar input[wrqu->length + 1];\n\tchar *pch, *pnext;\n\tchar *width_str;\n\tchar width;\n\tchar data[20], tmp[20];\n\tu32 addr = 0, strtout = 0;\n\tu32 i = 0, j = 0, ret = 0, data32 = 0;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tchar *pextra = extra;\n\n\tif (wrqu->length > 128)\n\t\treturn -EFAULT;\n\n\t_rtw_memset(input, 0, sizeof(input));\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tinput[wrqu->length] = '\\0';\n\t_rtw_memset(extra, 0, wrqu->length);\n\t_rtw_memset(data, '\\0', sizeof(data));\n\t_rtw_memset(tmp, '\\0', sizeof(tmp));\n\tpch = input;\n\tpnext = strpbrk(pch, \" ,.-\");\n\tif (pnext == NULL)\n\t\treturn -EINVAL;\n\t*pnext = 0;\n\twidth_str = pch;\n\n\tpch = pnext + 1;\n\n\tret = sscanf(pch, \"%x\", &addr);\n\tif (addr > MP_READ_REG_MAX_OFFSET)\n\t\treturn -EINVAL;\n\n\tret = 0;\n\twidth = width_str[0];\n\n\tswitch (width) {\n\tcase 'b':\n\t\tdata32 = rtw_read8(padapter, addr);\n\t\tRTW_INFO(\"%x\\n\", data32);\n\t\tsprintf(extra, \"%d\", data32);\n\t\twrqu->length = strlen(extra);\n\t\tbreak;\n\tcase 'w':\n\t\t/* 2 bytes*/\n\t\tsprintf(data, \"%04x\\n\", rtw_read16(padapter, addr));\n\n\t\tfor (i = 0 ; i <= strlen(data) ; i++) {\n\t\t\tif (i % 2 == 0) {\n\t\t\t\ttmp[j] = ' ';\n\t\t\t\tj++;\n\t\t\t}\n\t\t\tif (data[i] != '\\0')\n\t\t\t\ttmp[j] = data[i];\n\n\t\t\tj++;\n\t\t}\n\t\tpch = tmp;\n\t\tRTW_INFO(\"pch=%s\", pch);\n\n\t\twhile (*pch != '\\0') {\n\t\t\tpnext = strpbrk(pch, \" \");\n\t\t\tif (!pnext || ((pnext - tmp) > 4))\n\t\t\t\tbreak;\n\n\t\t\tpnext++;\n\t\t\tif (*pnext != '\\0') {\n\t\t\t\t/*strtout = simple_strtoul(pnext , &ptmp, 16);*/\n\t\t\t\tret = sscanf(pnext, \"%x\", &strtout);\n\t\t\t\tpextra += sprintf(pextra, \" %d\", strtout);\n\t\t\t} else\n\t\t\t\tbreak;\n\t\t\tpch = pnext;\n\t\t}\n\t\twrqu->length = strlen(extra);\n\t\tbreak;\n\tcase 'd':\n\t\t/* 4 bytes */\n\t\tsprintf(data, \"%08x\", rtw_read32(padapter, addr));\n\t\t/*add read data format blank*/\n\t\tfor (i = 0 ; i <= strlen(data) ; i++) {\n\t\t\tif (i % 2 == 0) {\n\t\t\t\ttmp[j] = ' ';\n\t\t\t\tj++;\n\t\t\t}\n\t\t\tif (data[i] != '\\0')\n\t\t\t\ttmp[j] = data[i];\n\n\t\t\tj++;\n\t\t}\n\t\tpch = tmp;\n\t\tRTW_INFO(\"pch=%s\", pch);\n\n\t\twhile (*pch != '\\0') {\n\t\t\tpnext = strpbrk(pch, \" \");\n\t\t\tif (!pnext)\n\t\t\t\tbreak;\n\n\t\t\tpnext++;\n\t\t\tif (*pnext != '\\0') {\n\t\t\t\tret = sscanf(pnext, \"%x\", &strtout);\n\t\t\t\tpextra += sprintf(pextra, \" %d\", strtout);\n\t\t\t} else\n\t\t\t\tbreak;\n\t\t\tpch = pnext;\n\t\t}\n\t\twrqu->length = strlen(extra);\n\t\tbreak;\n\n\tdefault:\n\t\twrqu->length = 0;\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\n\n/*\n * Input Format: %d,%x,%x\n *\t%d is RF path, should be smaller than MAX_RF_PATH_NUMS\n *\t1st %x is address(offset)\n *\t2st %x is data to write\n */\nint rtw_mp_write_rf(struct net_device *dev,\n\t\t    struct iw_request_info *info,\n\t\t    struct iw_point *wrqu, char *extra)\n{\n\n\tu32 path, addr, data;\n\tint ret;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tchar input[wrqu->length];\n\n\n\t_rtw_memset(input, 0, wrqu->length);\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\n\tret = sscanf(input, \"%d,%x,%x\", &path, &addr, &data);\n\tif (ret < 3)\n\t\treturn -EINVAL;\n\n\tif (path >= GET_HAL_RFPATH_NUM(padapter))\n\t\treturn -EINVAL;\n\tif (addr > 0xFF)\n\t\treturn -EINVAL;\n\tif (data > 0xFFFFF)\n\t\treturn -EINVAL;\n\n\t_rtw_memset(extra, 0, wrqu->length);\n\n\twrite_rfreg(padapter, path, addr, data);\n\n\tsprintf(extra, \"write_rf completed\\n\");\n\twrqu->length = strlen(extra);\n\n\treturn 0;\n}\n\n\n/*\n * Input Format: %d,%x\n *\t%d is RF path, should be smaller than MAX_RF_PATH_NUMS\n *\t%x is address(offset)\n *\n * Return:\n *\t%d for data readed\n */\nint rtw_mp_read_rf(struct net_device *dev,\n\t\t   struct iw_request_info *info,\n\t\t   struct iw_point *wrqu, char *extra)\n{\n\tchar input[wrqu->length];\n\tchar *pch, *pnext;\n\tchar data[20], tmp[20];\n\tu32 path, addr, strtou;\n\tu32 ret, i = 0 , j = 0;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tchar *pextra = extra;\n\n\tif (wrqu->length > 128)\n\t\treturn -EFAULT;\n\t_rtw_memset(input, 0, wrqu->length);\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tret = sscanf(input, \"%d,%x\", &path, &addr);\n\tif (ret < 2)\n\t\treturn -EINVAL;\n\n\tif (path >= GET_HAL_RFPATH_NUM(padapter))\n\t\treturn -EINVAL;\n\tif (addr > 0xFF)\n\t\treturn -EINVAL;\n\n\t_rtw_memset(extra, 0, wrqu->length);\n\n\tsprintf(data, \"%08x\", read_rfreg(padapter, path, addr));\n\t/*add read data format blank*/\n\tfor (i = 0 ; i <= strlen(data) ; i++) {\n\t\tif (i % 2 == 0) {\n\t\t\ttmp[j] = ' ';\n\t\t\tj++;\n\t\t}\n\t\ttmp[j] = data[i];\n\t\tj++;\n\t}\n\tpch = tmp;\n\tRTW_INFO(\"pch=%s\", pch);\n\n\twhile (*pch != '\\0') {\n\t\tpnext = strpbrk(pch, \" \");\n\t\tif (!pnext)\n\t\t\tbreak;\n\t\tpnext++;\n\t\tif (*pnext != '\\0') {\n\t\t\t/*strtou =simple_strtoul(pnext , &ptmp, 16);*/\n\t\t\tret = sscanf(pnext, \"%x\", &strtou);\n\t\t\tpextra += sprintf(pextra, \" %d\", strtou);\n\t\t} else\n\t\t\tbreak;\n\t\tpch = pnext;\n\t}\n\twrqu->length = strlen(extra);\n\n\treturn 0;\n}\n\n\nint rtw_mp_start(struct net_device *dev,\n\t\t struct iw_request_info *info,\n\t\t struct iw_point *wrqu, char *extra)\n{\n\tint ret = 0;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tstruct mp_priv *pmppriv = &padapter->mppriv;\n\n\trtw_pm_set_ips(padapter, IPS_NONE);\n\tLeaveAllPowerSaveMode(padapter);\n\n\tpmppriv->bprocess_mp_mode = _TRUE;\n\n\tif (rtw_mi_check_fwstate(padapter, _FW_UNDER_SURVEY)) {\n\t\trtw_mi_buddy_set_scan_deny(padapter, 5000);\n\t\trtw_mi_scan_abort(padapter, _TRUE);\n\t}\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);\n\n\tif (rtw_mp_cmd(padapter, MP_START, RTW_CMDF_WAIT_ACK) != _SUCCESS)\n\t\tret = -EPERM;\n\n\t_rtw_memset(extra, 0, wrqu->length);\n\tsprintf(extra, \"mp_start %s\\n\", ret == 0 ? \"ok\" : \"fail\");\n\twrqu->length = strlen(extra);\n\n\treturn ret;\n}\n\n\n\nint rtw_mp_stop(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra)\n{\n\tint ret = 0;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tstruct mp_priv *pmppriv = &padapter->mppriv;\n\n\tif (pmppriv->mode != MP_ON)\n\t\treturn -EPERM;\n\n\tif (rtw_mp_cmd(padapter, MP_STOP, RTW_CMDF_WAIT_ACK) != _SUCCESS)\n\t\tret = -EPERM;\n\n\tpmppriv->bprocess_mp_mode = _FALSE;\n\t_rtw_memset(extra, 0, wrqu->length);\n\tsprintf(extra, \"mp_stop %s\\n\", ret == 0 ? \"ok\" : \"fail\");\n\twrqu->length = strlen(extra);\n\n\treturn ret;\n}\n\n\nint rtw_mp_rate(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra)\n{\n\tu32 rate = MPT_RATE_1M;\n\tu8\t\tinput[wrqu->length + 1];\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tPMPT_CONTEXT\t\tpMptCtx = &(padapter->mppriv.mpt_ctx);\n\n\t_rtw_memset(input, 0, sizeof(input));\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tinput[wrqu->length] = '\\0';\n\trate = rtw_mpRateParseFunc(padapter, input);\n\tpadapter->mppriv.rateidx = rate;\n\n\tif (rate == 0 && strcmp(input, \"1M\") != 0) {\n\t\trate = rtw_atoi(input);\n\t\tpadapter->mppriv.rateidx = MRateToHwRate(rate);\n\t\t/*if (rate <= 0x7f)\n\t\t\trate = wifirate2_ratetbl_inx((u8)rate);\n\t\telse if (rate < 0xC8)\n\t\t\trate = (rate - 0x79 + MPT_RATE_MCS0);\n\t\tHT  rate 0x80(MCS0)  ~ 0x8F(MCS15) ~ 0x9F(MCS31) 128~159\n\t\tVHT1SS~2SS rate 0xA0 (VHT1SS_MCS0 44) ~ 0xB3 (VHT2SS_MCS9 #63) 160~179\n\t\tVHT rate 0xB4 (VHT3SS_MCS0 64) ~ 0xC7 (VHT2SS_MCS9 #83) 180~199\n\t\telse\n\t\tVHT rate 0x90(VHT1SS_MCS0) ~ 0x99(VHT1SS_MCS9) 144~153\n\t\trate =(rate - MPT_RATE_VHT1SS_MCS0);\n\t\t*/\n\t}\n\t_rtw_memset(extra, 0, wrqu->length);\n\n\tsprintf(extra, \"Set data rate to %s index %d\" , input, padapter->mppriv.rateidx);\n\tRTW_INFO(\"%s: %s rate index=%d\\n\", __func__, input, padapter->mppriv.rateidx);\n\n\tif (padapter->mppriv.rateidx >= DESC_RATEVHTSS4MCS9)\n\t\treturn -EINVAL;\n\n\tpMptCtx->mpt_rate_index = HwRateToMPTRate(padapter->mppriv.rateidx);\n\tSetDataRate(padapter);\n\n\twrqu->length = strlen(extra);\n\treturn 0;\n}\n\n\nint rtw_mp_channel(struct net_device *dev,\n\t\t   struct iw_request_info *info,\n\t\t   struct iw_point *wrqu, char *extra)\n{\n\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE\t*pHalData\t= GET_HAL_DATA(padapter);\n\tu8\t\tinput[wrqu->length + 1];\n\tu32\tchannel = 1;\n\n\t_rtw_memset(input, 0, sizeof(input));\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tinput[wrqu->length] = '\\0';\n\tchannel = rtw_atoi(input);\n\t/*RTW_INFO(\"%s: channel=%d\\n\", __func__, channel);*/\n\t_rtw_memset(extra, 0, wrqu->length);\n\tsprintf(extra, \"Change channel %d to channel %d\", padapter->mppriv.channel , channel);\n\tpadapter->mppriv.channel = channel;\n\trtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);\n\tSetChannel(padapter);\n\tpHalData->current_channel = channel;\n\n\twrqu->length = strlen(extra);\n\treturn 0;\n}\n\n\nint rtw_mp_ch_offset(struct net_device *dev,\n\t\t   struct iw_request_info *info,\n\t\t   struct iw_point *wrqu, char *extra)\n{\n\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tu8\t\tinput[wrqu->length + 1];\n\tu32\tch_offset = 0;\n\n\t_rtw_memset(input, 0, sizeof(input));\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tinput[wrqu->length] = '\\0';\n\tch_offset = rtw_atoi(input);\n\t/*RTW_INFO(\"%s: channel=%d\\n\", __func__, channel);*/\n\t_rtw_memset(extra, 0, wrqu->length);\n\tsprintf(extra, \"Change prime channel offset %d to %d\", padapter->mppriv.prime_channel_offset , ch_offset);\n\tpadapter->mppriv.prime_channel_offset = ch_offset;\n\tSetChannel(padapter);\n\n\twrqu->length = strlen(extra);\n\treturn 0;\n}\n\n\nint rtw_mp_bandwidth(struct net_device *dev,\n\t\t     struct iw_request_info *info,\n\t\t     struct iw_point *wrqu, char *extra)\n{\n\tu32 bandwidth = 0, sg = 0;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE\t*pHalData\t= GET_HAL_DATA(padapter);\n\tu8\t\tinput[wrqu->length];\n\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tif (sscanf(input, \"40M=%d,shortGI=%d\", &bandwidth, &sg) > 0)\n\t\tRTW_INFO(\"%s: bw=%d sg=%d\\n\", __func__, bandwidth , sg);\n\n\tif (bandwidth == 1)\n\t\tbandwidth = CHANNEL_WIDTH_40;\n\telse if (bandwidth == 2)\n\t\tbandwidth = CHANNEL_WIDTH_80;\n\n\tpadapter->mppriv.bandwidth = (u8)bandwidth;\n\tpadapter->mppriv.preamble = sg;\n\t_rtw_memset(extra, 0, wrqu->length);\n\tsprintf(extra, \"Change BW %d to BW %d\\n\", pHalData->current_channel_bw , bandwidth);\n\trtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);\n\tSetBandwidth(padapter);\n\tpHalData->current_channel_bw = bandwidth;\n\n\twrqu->length = strlen(extra);\n\n\treturn 0;\n}\n\n\nint rtw_mp_txpower_index(struct net_device *dev,\n\t\t\t struct iw_request_info *info,\n\t\t\t struct iw_point *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n \tHAL_DATA_TYPE\t*phal_data\t= GET_HAL_DATA(padapter);\n\tchar input[wrqu->length + 1];\n\tu32 rfpath;\n\tu32 txpower_inx;\n\n\tif (wrqu->length > 128)\n\t\treturn -EFAULT;\n\n\t_rtw_memset(input, 0, sizeof(input));\n\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tinput[wrqu->length] = '\\0';\n\n\tif (wrqu->length == 2) {\n\t\trfpath = rtw_atoi(input);\n\t\ttxpower_inx = mpt_ProQueryCalTxPower(padapter, rfpath);\n\t\tsprintf(extra, \" %d\", txpower_inx);\n\t} else {\n\t\ttxpower_inx = mpt_ProQueryCalTxPower(padapter, 0);\n\t\tsprintf(extra, \"patha=%d\", txpower_inx);\n\t\tif (phal_data->rf_type > RF_1T2R) {\n\t\t\ttxpower_inx = mpt_ProQueryCalTxPower(padapter, 1);\n\t\t\tsprintf(extra, \"%s,pathb=%d\", extra, txpower_inx);\n\t\t}\n\t\tif (phal_data->rf_type > RF_2T4R) {\n\t\t\ttxpower_inx = mpt_ProQueryCalTxPower(padapter, 2);\n\t\t\tsprintf(extra, \"%s,pathc=%d\", extra, txpower_inx);\n\t\t}\n\t\tif (phal_data->rf_type > RF_3T4R) {\n\t\t\ttxpower_inx = mpt_ProQueryCalTxPower(padapter, 3);\n\t\t\tsprintf(extra, \"%s,pathd=%d\", extra, txpower_inx);\n\t\t}\n\t}\n\twrqu->length = strlen(extra);\n\n\treturn 0;\n}\n\n\nint rtw_mp_txpower(struct net_device *dev,\n\t\t   struct iw_request_info *info,\n\t\t   struct iw_point *wrqu, char *extra)\n{\n\tu32 idx_a = 0, idx_b = 0, idx_c = 0, idx_d = 0;\n\tint MsetPower = 1;\n\tu8\t\tinput[wrqu->length];\n\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tPMPT_CONTEXT\t\tpMptCtx = &(padapter->mppriv.mpt_ctx);\n\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tMsetPower = strncmp(input, \"off\", 3);\n\tif (MsetPower == 0) {\n\t\tpadapter->mppriv.bSetTxPower = 0;\n\t\tsprintf(extra, \"MP Set power off\");\n\t} else {\n\t\tif (sscanf(input, \"patha=%d,pathb=%d,pathc=%d,pathd=%d\", &idx_a, &idx_b, &idx_c, &idx_d) < 3)\n\t\t\tRTW_INFO(\"Invalid format on line %s ,patha=%d,pathb=%d,pathc=%d,pathd=%d\\n\", input , idx_a , idx_b , idx_c , idx_d);\n\n\t\tsprintf(extra, \"Set power level path_A:%d path_B:%d path_C:%d path_D:%d\", idx_a , idx_b , idx_c , idx_d);\n\t\tpadapter->mppriv.txpoweridx = (u8)idx_a;\n\n\t\tpMptCtx->TxPwrLevel[RF_PATH_A] = (u8)idx_a;\n\t\tpMptCtx->TxPwrLevel[RF_PATH_B] = (u8)idx_b;\n\t\tpMptCtx->TxPwrLevel[RF_PATH_C] = (u8)idx_c;\n\t\tpMptCtx->TxPwrLevel[RF_PATH_D]  = (u8)idx_d;\n\t\tpadapter->mppriv.bSetTxPower = 1;\n\n\t\tSetTxPower(padapter);\n\t}\n\n\twrqu->length = strlen(extra);\n\treturn 0;\n}\n\n\nint rtw_mp_ant_tx(struct net_device *dev,\n\t\t  struct iw_request_info *info,\n\t\t  struct iw_point *wrqu, char *extra)\n{\n\tu8 i;\n\tu8\t\tinput[wrqu->length + 1];\n\tu16 antenna = 0;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n\t_rtw_memset(input, 0, sizeof(input));\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tinput[wrqu->length] = '\\0';\n\tsprintf(extra, \"switch Tx antenna to %s\", input);\n\n\tfor (i = 0; i < strlen(input); i++) {\n\t\tswitch (input[i]) {\n\t\tcase 'a':\n\t\t\tantenna |= ANTENNA_A;\n\t\t\tbreak;\n\t\tcase 'b':\n\t\t\tantenna |= ANTENNA_B;\n\t\t\tbreak;\n\t\tcase 'c':\n\t\t\tantenna |= ANTENNA_C;\n\t\t\tbreak;\n\t\tcase 'd':\n\t\t\tantenna |= ANTENNA_D;\n\t\t\tbreak;\n\t\t}\n\t}\n\t/*antenna |= BIT(extra[i]-'a');*/\n\tRTW_INFO(\"%s: antenna=0x%x\\n\", __func__, antenna);\n\tpadapter->mppriv.antenna_tx = antenna;\n\n\t/*RTW_INFO(\"%s:mppriv.antenna_rx=%d\\n\", __func__, padapter->mppriv.antenna_tx);*/\n\tpHalData->antenna_tx_path = antenna;\n\tif (IS_HARDWARE_TYPE_8822C(padapter) && padapter->mppriv.antenna_tx == ANTENNA_B) {\n\t\tif (padapter->mppriv.antenna_rx == ANTENNA_A || padapter->mppriv.antenna_rx == ANTENNA_B) {\n\t\t\tpadapter->mppriv.antenna_rx = ANTENNA_AB;\n\t\t\tpHalData->AntennaRxPath = ANTENNA_AB;\n\t\t\tRTW_INFO(\"%s:8822C Tx-B Rx Ant to AB\\n\", __func__);\n\t\t}\n\t}\n\tSetAntenna(padapter);\n\n\twrqu->length = strlen(extra);\n\treturn 0;\n}\n\n\nint rtw_mp_ant_rx(struct net_device *dev,\n\t\t  struct iw_request_info *info,\n\t\t  struct iw_point *wrqu, char *extra)\n{\n\tu8 i;\n\tu16 antenna = 0;\n\tu8\t\tinput[wrqu->length + 1];\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n\t_rtw_memset(input, 0, sizeof(input));\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tinput[wrqu->length] = '\\0';\n\t/*RTW_INFO(\"%s: input=%s\\n\", __func__, input);*/\n\t_rtw_memset(extra, 0, wrqu->length);\n\n\tsprintf(extra, \"switch Rx antenna to %s\", input);\n\n\tfor (i = 0; i < strlen(input); i++) {\n\t\tswitch (input[i]) {\n\t\tcase 'a':\n\t\t\tantenna |= ANTENNA_A;\n\t\t\tbreak;\n\t\tcase 'b':\n\t\t\tantenna |= ANTENNA_B;\n\t\t\tbreak;\n\t\tcase 'c':\n\t\t\tantenna |= ANTENNA_C;\n\t\t\tbreak;\n\t\tcase 'd':\n\t\t\tantenna |= ANTENNA_D;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tRTW_INFO(\"%s: antenna=0x%x\\n\", __func__, antenna);\n\n\tpadapter->mppriv.antenna_rx = antenna;\n\tpHalData->AntennaRxPath = antenna;\n\t/*RTW_INFO(\"%s:mppriv.antenna_rx=%d\\n\", __func__, padapter->mppriv.antenna_rx);*/\n\tSetAntenna(padapter);\n\twrqu->length = strlen(extra);\n\n\treturn 0;\n}\n\n\nint rtw_set_ctx_destAddr(struct net_device *dev,\n\t\t\t struct iw_request_info *info,\n\t\t\t struct iw_point *wrqu, char *extra)\n{\n\tint jj, kk = 0;\n\n\tstruct pkt_attrib *pattrib;\n\tstruct mp_priv *pmp_priv;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\n\tpmp_priv = &padapter->mppriv;\n\tpattrib = &pmp_priv->tx.attrib;\n\n\tif (strlen(extra) < 5)\n\t\treturn _FAIL;\n\n\tRTW_INFO(\"%s: in=%s\\n\", __func__, extra);\n\tfor (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)\n\t\tpattrib->dst[jj] = key_2char2num(extra[kk], extra[kk + 1]);\n\n\tRTW_INFO(\"pattrib->dst:%x %x %x %x %x %x\\n\", pattrib->dst[0], pattrib->dst[1], pattrib->dst[2], pattrib->dst[3], pattrib->dst[4], pattrib->dst[5]);\n\treturn 0;\n}\n\n\n\nint rtw_mp_ctx(struct net_device *dev,\n\t       struct iw_request_info *info,\n\t       struct iw_point *wrqu, char *extra)\n{\n\tu32 pkTx = 1;\n\tint countPkTx = 1, cotuTx = 1, CarrSprTx = 1, scTx = 1, sgleTx = 1, stop = 1;\n\tu32 bStartTest = 1;\n\tu32 count = 0, pktinterval = 0, pktlen = 0;\n\tu8 status;\n\tstruct mp_priv *pmp_priv;\n\tstruct pkt_attrib *pattrib;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n\tpmp_priv = &padapter->mppriv;\n\tpattrib = &pmp_priv->tx.attrib;\n\t\n\tif (padapter->registrypriv.mp_mode != 1 ) {\n\t\tsprintf(extra, \"Error: can't tx ,not in MP mode. \\n\");\n\t\twrqu->length = strlen(extra);\n\t\treturn 0;\n\t}\n\n\tif (copy_from_user(extra, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\t*(extra + wrqu->length) = '\\0';\n\tRTW_INFO(\"%s: in=%s\\n\", __func__, extra);\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (!is_primary_adapter(padapter)) {\n\t\tsprintf(extra, \"Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\\n\");\n\t\twrqu->length = strlen(extra);\n\t\treturn 0;\n\t}\n#endif\n\tcountPkTx = strncmp(extra, \"count=\", 5); /* strncmp TRUE is 0*/\n\tcotuTx = strncmp(extra, \"background\", 20);\n\tCarrSprTx = strncmp(extra, \"background,cs\", 20);\n\tscTx = strncmp(extra, \"background,sc\", 20);\n\tsgleTx = strncmp(extra, \"background,stone\", 20);\n\tpkTx = strncmp(extra, \"background,pkt\", 20);\n\tstop = strncmp(extra, \"stop\", 4);\n\tif (sscanf(extra, \"count=%d,pkt\", &count) > 0)\n\t\tRTW_INFO(\"count= %d\\n\", count);\n\tif (sscanf(extra, \"pktinterval=%d\", &pktinterval) > 0)\n\t\tRTW_INFO(\"pktinterval= %d\\n\", pktinterval);\n\n\tif (sscanf(extra, \"pktlen=%d\", &pktlen) > 0)\n\t\tRTW_INFO(\"pktlen= %d\\n\", pktlen);\n\n\tif (_rtw_memcmp(extra, \"destmac=\", 8)) {\n\t\twrqu->length -= 8;\n\t\trtw_set_ctx_destAddr(dev, info, wrqu, &extra[8]);\n\t\tsprintf(extra, \"Set dest mac OK !\\n\");\n\t\treturn 0;\n\t}\n\n\t/*RTW_INFO(\"%s: count=%d countPkTx=%d cotuTx=%d CarrSprTx=%d scTx=%d sgleTx=%d pkTx=%d stop=%d\\n\", __func__, count, countPkTx, cotuTx, CarrSprTx, pkTx, sgleTx, scTx, stop);*/\n\t_rtw_memset(extra, '\\0', strlen(extra));\n\n\tif (pktinterval != 0) {\n\t\tsprintf(extra, \"Pkt Interval = %d\", pktinterval);\n\t\tpadapter->mppriv.pktInterval = pktinterval;\n\t\twrqu->length = strlen(extra);\n\t\treturn 0;\n\t}\n\tif (pktlen != 0) {\n\t\tsprintf(extra, \"Pkt len = %d\", pktlen);\n\t\tpattrib->pktlen = pktlen;\n\t\twrqu->length = strlen(extra);\n\t\treturn 0;\n\t}\n\tif (stop == 0) {\n\t\tstruct xmit_priv\t*pxmitpriv = &(padapter->xmitpriv);\n\t\t_queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue;\n\t\t_queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue;\n\n\t\tu32 i = 0;\n\t\tbStartTest = 0; /* To set Stop*/\n\t\tpmp_priv->tx.stop = 1;\n\t\tsprintf(extra, \"Stop continuous Tx\");\n\t\todm_write_dig(&pHalData->odmpriv, 0x20);\n\t\tdo {\n\t\t\tif (pxmitpriv->free_xmitframe_cnt == NR_XMITFRAME && pxmitpriv->free_xmitbuf_cnt == NR_XMITBUFF)\n\t\t\t\tbreak;\n\t\t\telse {\n\t\t\t\ti++;\n\t\t\t\tRTW_INFO(\"%s:wait queue_empty %d!!\\n\", __func__, i);\n\t\t\t\trtw_msleep_os(10);\n\t\t\t}\n\t\t} while (i < 1000);\n\t} else {\n\t\tbStartTest = 1;\n\t\todm_write_dig(&pHalData->odmpriv, 0x3f);\n\t\tif (IS_HARDWARE_TYPE_8822C(padapter) && pmp_priv->antenna_tx == ANTENNA_B) {\n\t\t\tif (pmp_priv->antenna_rx == ANTENNA_A || pmp_priv->antenna_rx == ANTENNA_B) {\n\t\t\t\tpmp_priv->antenna_rx = ANTENNA_AB;\n\t\t\t\tpHalData->AntennaRxPath = ANTENNA_AB;\n\t\t\t\tRTW_INFO(\"%s:8822C Tx-B Rx Ant to AB\\n\", __func__);\n\t\t\t\tSetAntenna(padapter);\n\t\t\t}\n\t\t}\n\t\tif (pmp_priv->mode != MP_ON) {\n\t\t\tif (pmp_priv->tx.stop != 1) {\n\t\t\t\tRTW_INFO(\"%s:Error MP_MODE %d != ON\\n\", __func__, pmp_priv->mode);\n\t\t\t\treturn\t-EFAULT;\n\t\t\t}\n\t\t}\n\t}\n\n\tpmp_priv->tx.count = count;\n\n\tif (pkTx == 0 || countPkTx == 0)\n\t\tpmp_priv->mode = MP_PACKET_TX;\n\tif (sgleTx == 0)\n\t\tpmp_priv->mode = MP_SINGLE_TONE_TX;\n\tif (cotuTx == 0)\n\t\tpmp_priv->mode = MP_CONTINUOUS_TX;\n\tif (CarrSprTx == 0)\n\t\tpmp_priv->mode = MP_CARRIER_SUPPRISSION_TX;\n\tif (scTx == 0)\n\t\tpmp_priv->mode = MP_SINGLE_CARRIER_TX;\n\n\tstatus = rtw_mp_pretx_proc(padapter, bStartTest, extra);\n\n\tif (stop == 0)\n\t\tpmp_priv->mode = MP_ON;\n\n\twrqu->length = strlen(extra);\n\treturn status;\n}\n\n\n\nint rtw_mp_disable_bt_coexist(struct net_device *dev,\n\t\t\t      struct iw_request_info *info,\n\t\t\t      union iwreq_data *wrqu, char *extra)\n{\n#ifdef CONFIG_BT_COEXIST\n\tPADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev);\n\n#endif\n\tu8 input[wrqu->data.length + 1];\n\tu32 bt_coexist;\n\n\t_rtw_memset(input, 0, sizeof(input));\n\n\tif (copy_from_user(input, wrqu->data.pointer, wrqu->data.length))\n\t\treturn -EFAULT;\n\n\tinput[wrqu->data.length] = '\\0';\n\n\tbt_coexist = rtw_atoi(input);\n\n\tif (bt_coexist == 0) {\n\t\tRTW_INFO(\"Set OID_RT_SET_DISABLE_BT_COEXIST: disable BT_COEXIST\\n\");\n#ifdef CONFIG_BT_COEXIST\n\t\trtw_btcoex_HaltNotify(padapter);\n\t\trtw_btcoex_SetManualControl(padapter, _TRUE);\n\t\t/* Force to switch Antenna to WiFi*/\n\t\trtw_write16(padapter, 0x870, 0x300);\n\t\trtw_write16(padapter, 0x860, 0x110);\n#endif\n\t\t/* CONFIG_BT_COEXIST */\n\t} else {\n#ifdef CONFIG_BT_COEXIST\n\t\trtw_btcoex_SetManualControl(padapter, _FALSE);\n#endif\n\t}\n\n\treturn 0;\n}\n\n\nint rtw_mp_arx(struct net_device *dev,\n\t       struct iw_request_info *info,\n\t       struct iw_point *wrqu, char *extra)\n{\n\tint bStartRx = 0, bStopRx = 0, bQueryPhy = 0, bQueryMac = 0, bSetBssid = 0, bSetRxframe = 0;\n\tint bmac_filter = 0, bmon = 0, bSmpCfg = 0;\n\tu8\t\tinput[wrqu->length];\n\tchar *pch, *token, *tmp[2] = {0x00, 0x00};\n\tu32 i = 0, jj = 0, kk = 0, cnts = 0, ret;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tstruct mp_priv *pmppriv = &padapter->mppriv;\n\tstruct dbg_rx_counter rx_counter;\n\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tRTW_INFO(\"%s: %s\\n\", __func__, input);\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (!is_primary_adapter(padapter)) {\n\t\tsprintf(extra, \"Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\\n\");\n\t\twrqu->length = strlen(extra);\n\t\treturn 0;\n\t}\n#endif\n\tbStartRx = (strncmp(input, \"start\", 5) == 0) ? 1 : 0; /* strncmp TRUE is 0*/\n\tbStopRx = (strncmp(input, \"stop\", 5) == 0) ? 1 : 0; /* strncmp TRUE is 0*/\n\tbQueryPhy = (strncmp(input, \"phy\", 3) == 0) ? 1 : 0; /* strncmp TRUE is 0*/\n\tbQueryMac = (strncmp(input, \"mac\", 3) == 0) ? 1 : 0; /* strncmp TRUE is 0*/\n\tbSetBssid = (strncmp(input, \"setbssid=\", 8) == 0) ? 1 : 0; /* strncmp TRUE is 0*/\n\tbSetRxframe = (strncmp(input, \"frametype\", 9) == 0) ? 1 : 0;\n\t/*bfilter_init = (strncmp(input, \"filter_init\",11)==0)?1:0;*/\n\tbmac_filter = (strncmp(input, \"accept_mac\", 10) == 0) ? 1 : 0;\n\tbmon = (strncmp(input, \"mon=\", 4) == 0) ? 1 : 0;\n\tbSmpCfg = (strncmp(input , \"smpcfg=\" , 7) == 0) ? 1 : 0;\n\tpmppriv->bloopback = (strncmp(input, \"loopbk\", 6) == 0) ? 1 : 0; /* strncmp TRUE is 0*/\n\n\tif (bSetBssid == 1) {\n\t\tpch = input;\n\t\twhile ((token = strsep(&pch, \"=\")) != NULL) {\n\t\t\tif (i > 1)\n\t\t\t\tbreak;\n\t\t\ttmp[i] = token;\n\t\t\ti++;\n\t\t}\n\t\tif ((tmp[0] != NULL) && (tmp[1] != NULL)) {\n\t\t\tcnts = strlen(tmp[1]) / 2;\n\t\t\tif (cnts < 1)\n\t\t\t\treturn -EFAULT;\n\t\t\tRTW_INFO(\"%s: cnts=%d\\n\", __func__, cnts);\n\t\t\tRTW_INFO(\"%s: data=%s\\n\", __func__, tmp[1]);\n\t\t\tfor (jj = 0, kk = 0; jj < cnts ; jj++, kk += 2) {\n\t\t\t\tpmppriv->network_macaddr[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);\n\t\t\t\tRTW_INFO(\"network_macaddr[%d]=%x\\n\", jj, pmppriv->network_macaddr[jj]);\n\t\t\t}\n\t\t} else\n\t\t\treturn -EFAULT;\n\n\t\tpmppriv->bSetRxBssid = _TRUE;\n\t}\n\tif (bSetRxframe) {\n\t\tif (strncmp(input, \"frametype beacon\", 16) == 0)\n\t\t\tpmppriv->brx_filter_beacon = _TRUE;\n\t\telse\n\t\t\tpmppriv->brx_filter_beacon = _FALSE;\n\t}\n\n\tif (bmac_filter) {\n\t\tpmppriv->bmac_filter = bmac_filter;\n\t\tpch = input;\n\t\twhile ((token = strsep(&pch, \"=\")) != NULL) {\n\t\t\tif (i > 1)\n\t\t\t\tbreak;\n\t\t\ttmp[i] = token;\n\t\t\ti++;\n\t\t}\n\t\tif ((tmp[0] != NULL) && (tmp[1] != NULL)) {\n\t\t\tcnts = strlen(tmp[1]) / 2;\n\t\t\tif (cnts < 1)\n\t\t\t\treturn -EFAULT;\n\t\t\tRTW_INFO(\"%s: cnts=%d\\n\", __func__, cnts);\n\t\t\tRTW_INFO(\"%s: data=%s\\n\", __func__, tmp[1]);\n\t\t\tfor (jj = 0, kk = 0; jj < cnts ; jj++, kk += 2) {\n\t\t\t\tpmppriv->mac_filter[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);\n\t\t\t\tRTW_INFO(\"%s mac_filter[%d]=%x\\n\", __func__, jj, pmppriv->mac_filter[jj]);\n\t\t\t}\n\t\t} else\n\t\t\treturn -EFAULT;\n\n\t}\n\n\tif (bStartRx) {\n\t\tsprintf(extra, \"start\");\n\t\tSetPacketRx(padapter, bStartRx, _FALSE);\n\t} else if (bStopRx) {\n\t\tSetPacketRx(padapter, bStartRx, _FALSE);\n\t\tpmppriv->bmac_filter = _FALSE;\n\t\tpmppriv->bSetRxBssid = _FALSE;\n\t\tsprintf(extra, \"Received packet OK:%d CRC error:%d ,Filter out:%d\", padapter->mppriv.rx_pktcount, padapter->mppriv.rx_crcerrpktcount, padapter->mppriv.rx_pktcount_filter_out);\n\t} else if (bQueryPhy) {\n\t\t_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));\n\t\trtw_dump_phy_rx_counters(padapter, &rx_counter);\n\n\t\tRTW_INFO(\"%s: OFDM_FA =%d\\n\", __func__, rx_counter.rx_ofdm_fa);\n\t\tRTW_INFO(\"%s: CCK_FA =%d\\n\", __func__, rx_counter.rx_cck_fa);\n\t\tsprintf(extra, \"Phy Received packet OK:%d CRC error:%d FA Counter: %d\", rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_cck_fa + rx_counter.rx_ofdm_fa);\n\n\n\t} else if (bQueryMac) {\n\t\t_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));\n\t\trtw_dump_mac_rx_counters(padapter, &rx_counter);\n\t\tsprintf(extra, \"Mac Received packet OK: %d , CRC error: %d , Drop Packets: %d\\n\",\n\t\t\trx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_pkt_drop);\n\n\t}\n\n\tif (bmon == 1) {\n\t\tret = sscanf(input, \"mon=%d\", &bmon);\n\n\t\tif (bmon == 1) {\n\t\t\tpmppriv->rx_bindicatePkt = _TRUE;\n\t\t\tsprintf(extra, \"Indicating Receive Packet to network start\\n\");\n\t\t} else {\n\t\t\tpmppriv->rx_bindicatePkt = _FALSE;\n\t\t\tsprintf(extra, \"Indicating Receive Packet to network Stop\\n\");\n\t\t}\n\t}\n\tif (bSmpCfg == 1) {\n\t\tret = sscanf(input, \"smpcfg=%d\", &bSmpCfg);\n\n\t\tif (bSmpCfg == 1) {\n\t\t\tpmppriv->bRTWSmbCfg = _TRUE;\n\t\t\tsprintf(extra , \"Indicate By Simple Config Format\\n\");\n\t\t\tSetPacketRx(padapter, _TRUE, _TRUE);\n\t\t} else {\n\t\t\tpmppriv->bRTWSmbCfg = _FALSE;\n\t\t\tsprintf(extra , \"Indicate By Normal Format\\n\");\n\t\t\tSetPacketRx(padapter, _TRUE, _FALSE);\n\t\t}\n\t}\n\n\tif (pmppriv->bloopback == _TRUE) {\n\t\tsprintf(extra , \"Enter MAC LoopBack mode\\n\");\n\t\t_rtw_write32(padapter, 0x100, 0xB0106FF);\n\t\tRTW_INFO(\"0x100 :0x%x\" , _rtw_read32(padapter, 0x100));\n\t\t_rtw_write16(padapter, 0x608, 0x30c);\n\t\tRTW_INFO(\"0x100 :0x%x\" , _rtw_read32(padapter, 0x608));\n\t}\n\n\twrqu->length = strlen(extra) + 1;\n\n\treturn 0;\n}\n\n\nint rtw_mp_trx_query(struct net_device *dev,\n\t\t     struct iw_request_info *info,\n\t\t     struct iw_point *wrqu, char *extra)\n{\n\tu32 txok, txfail, rxok, rxfail, rxfilterout;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tPMPT_CONTEXT\tpMptCtx\t\t=\t&(padapter->mppriv.mpt_ctx);\n\tRT_PMAC_TX_INFO\tPMacTxInfo\t=\tpMptCtx->PMacTxInfo;\n\n\tif (PMacTxInfo.bEnPMacTx == TRUE)\n\t\ttxok = hal_mpt_query_phytxok(padapter);\n\telse\n\t\ttxok = padapter->mppriv.tx.sended;\n\n\ttxfail = 0;\n\trxok = padapter->mppriv.rx_pktcount;\n\trxfail = padapter->mppriv.rx_crcerrpktcount;\n\trxfilterout = padapter->mppriv.rx_pktcount_filter_out;\n\n\t_rtw_memset(extra, '\\0', 128);\n\n\tsprintf(extra, \"Tx OK:%d, Tx Fail:%d, Rx OK:%d, CRC error:%d ,Rx Filter out:%d\\n\", txok, txfail, rxok, rxfail, rxfilterout);\n\n\twrqu->length = strlen(extra) + 1;\n\n\treturn 0;\n}\n\n\nint rtw_mp_pwrtrk(struct net_device *dev,\n\t\t  struct iw_request_info *info,\n\t\t  struct iw_point *wrqu, char *extra)\n{\n\tu8 enable;\n\tu32 thermal;\n\ts32 ret;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tu8\t\tinput[wrqu->length];\n\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\t_rtw_memset(extra, 0, wrqu->length);\n\n\tenable = 1;\n\tif (wrqu->length > 1) {\n\t\t/* not empty string*/\n\t\tif (strncmp(input, \"stop\", 4) == 0) {\n\t\t\tenable = 0;\n\t\t\tsprintf(extra, \"mp tx power tracking stop\");\n\t\t} else if (sscanf(input, \"ther=%d\", &thermal) == 1) {\n\t\t\tret = SetThermalMeter(padapter, (u8)thermal);\n\t\t\tif (ret == _FAIL)\n\t\t\t\treturn -EPERM;\n\t\t\tsprintf(extra, \"mp tx power tracking start,target value=%d ok\", thermal);\n\t\t} else\n\t\t\treturn -EINVAL;\n\t}\n\n\tret = SetPowerTracking(padapter, enable);\n\tif (ret == _FAIL)\n\t\treturn -EPERM;\n\n\twrqu->length = strlen(extra);\n\n\treturn 0;\n}\n\n\n\nint rtw_mp_psd(struct net_device *dev,\n\t       struct iw_request_info *info,\n\t       struct iw_point *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tu8\t\tinput[wrqu->length + 1];\n\n\t_rtw_memset(input, 0, sizeof(input));\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tinput[wrqu->length] = '\\0';\n\tstrcpy(extra, input);\n\n\twrqu->length = mp_query_psd(padapter, extra);\n\n\treturn 0;\n}\n\n\nint rtw_mp_thermal(struct net_device *dev,\n\t\t   struct iw_request_info *info,\n\t\t   struct iw_point *wrqu, char *extra)\n{\n\tu8 val[4] = {0};\n\tu8 ret = 0;\n\tu16 ther_path_addr[4] = {0};\n\tu16 cnt = 1;\n\tu16 max_available_size = 0;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tint rfpath = RF_PATH_A;\n\n#ifdef CONFIG_RTL8188E\n\tther_path_addr[0] = EEPROM_THERMAL_METER_88E;\n#endif\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)\n\tther_path_addr[0] = EEPROM_THERMAL_METER_8812;\n#endif\n#ifdef CONFIG_RTL8192E\n\tther_path_addr[0] = EEPROM_THERMAL_METER_8192E;\n#endif\n#ifdef CONFIG_RTL8192F\n\tther_path_addr[0] = EEPROM_THERMAL_METER_8192F;\n#endif\n#ifdef CONFIG_RTL8723B\n\tther_path_addr[0] = EEPROM_THERMAL_METER_8723B;\n#endif\n#ifdef CONFIG_RTL8703B\n\tther_path_addr[0] = EEPROM_THERMAL_METER_8703B;\n#endif\n#ifdef CONFIG_RTL8723D\n\tther_path_addr[0] = EEPROM_THERMAL_METER_8723D;\n#endif\n#ifdef CONFIG_RTL8188F\n\tther_path_addr[0] = EEPROM_THERMAL_METER_8188F;\n#endif\n#ifdef CONFIG_RTL8188GTV\n\tther_path_addr[0] = EEPROM_THERMAL_METER_8188GTV;\n#endif\n#ifdef CONFIG_RTL8822B\n\tther_path_addr[0] = EEPROM_THERMAL_METER_8822B;\n#endif\n#ifdef CONFIG_RTL8821C\n\tther_path_addr[0] = EEPROM_THERMAL_METER_8821C;\n#endif\n#ifdef CONFIG_RTL8710B\n\tther_path_addr[0] = EEPROM_THERMAL_METER_8710B;\n#endif\n#ifdef CONFIG_RTL8822C\n\tther_path_addr[0]  = EEPROM_THERMAL_METER_A_8822C;\n\tther_path_addr[1]  = EEPROM_THERMAL_METER_B_8822C;\n#endif\n\n\tif (copy_from_user(extra, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tif ((strncmp(extra, \"write\", 6) == 0)) {\n\t\tint i;\n\t\tu16 raw_cursize = 0, raw_maxsize = 0;\n#ifdef RTW_HALMAC\n\t\traw_maxsize = efuse_GetavailableSize(padapter);\n#else\n\t\tefuse_GetCurrentSize(padapter, &raw_cursize);\n\t\traw_maxsize = efuse_GetMaxSize(padapter);\n#endif\n\t\tRTW_INFO(\"[eFuse available raw size]= %d bytes\\n\", raw_maxsize - raw_cursize);\n\t\tif (2 > raw_maxsize - raw_cursize) {\n\t\t\tRTW_INFO(\"no available efuse!\\n\");\n\t\t\treturn -EFAULT;\n\t\t}\n\n\t\tfor (i = 0; i < GET_HAL_RFPATH_NUM(padapter); i++) {\n\t\t\t\tGetThermalMeter(padapter, i , &val[i]);\n\t\t\t\tif (ther_path_addr[i] != 0 && val[i] != 0) {\n\t\t\t\t\tif (rtw_efuse_map_write(padapter, ther_path_addr[i], cnt, &val[i]) == _FAIL) {\n\t\t\t\t\t\tRTW_INFO(\"Error efuse write thermal addr 0x%x ,val = 0x%x\\n\", ther_path_addr[i], val[i]);\n\t\t\t\t\t\treturn -EFAULT;\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\t\tRTW_INFO(\"Error efuse write thermal Null addr,val \\n\");\n\t\t\t\t\t\treturn -EFAULT;\n\t\t\t\t}\n\t\t}\n\t\t_rtw_memset(extra, 0, wrqu->length);\n\t\tsprintf(extra, \" efuse write ok :%d\", val[0]);\n\t} else {\n\t\tret = sscanf(extra, \"%d\", &rfpath);\n\t\tif (ret < 1) {\n\t\t\trfpath = RF_PATH_A;\n\t\t\tRTW_INFO(\"default thermal of path(%d)\\n\", rfpath);\n\t\t}\n\t\tif (rfpath >= GET_HAL_RFPATH_NUM(padapter))\n\t\t\treturn -EINVAL;\n\n\t\tRTW_INFO(\"read thermal of path(%d)\\n\", rfpath);\n\t\tGetThermalMeter(padapter, rfpath, &val[0]);\n\n\t\t_rtw_memset(extra, 0, wrqu->length);\n\t\tsprintf(extra, \"%d\", val[0]);\n\t}\n\twrqu->length = strlen(extra);\n\n\treturn 0;\n}\n\n\n\nint rtw_mp_reset_stats(struct net_device *dev,\n\t\t       struct iw_request_info *info,\n\t\t       struct iw_point *wrqu, char *extra)\n{\n\tstruct mp_priv *pmp_priv;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\n\tpmp_priv = &padapter->mppriv;\n\n\tpmp_priv->tx.sended = 0;\n\tpmp_priv->tx_pktcount = 0;\n\tpmp_priv->rx_pktcount = 0;\n\tpmp_priv->rx_pktcount_filter_out = 0;\n\tpmp_priv->rx_crcerrpktcount = 0;\n\n\trtw_reset_phy_rx_counters(padapter);\n\trtw_reset_mac_rx_counters(padapter);\n\n\t_rtw_memset(extra, 0, wrqu->length);\n\tsprintf(extra, \"mp_reset_stats ok\\n\");\n\twrqu->length = strlen(extra);\n\n\treturn 0;\n}\n\n\nint rtw_mp_dump(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tstruct iw_point *wrqu, char *extra)\n{\n\tstruct mp_priv *pmp_priv;\n\tu8\t\tinput[wrqu->length];\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\n\tpmp_priv = &padapter->mppriv;\n\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tif (strncmp(input, \"all\", 4) == 0) {\n\t\tmac_reg_dump(RTW_DBGDUMP, padapter);\n\t\tbb_reg_dump(RTW_DBGDUMP, padapter);\n\t\trf_reg_dump(RTW_DBGDUMP, padapter);\n\t}\n\treturn 0;\n}\n\n\nint rtw_mp_phypara(struct net_device *dev,\n\t\t   struct iw_request_info *info,\n\t\t   struct iw_point *wrqu, char *extra)\n{\n\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE\t*pHalData\t= GET_HAL_DATA(padapter);\n\tchar\tinput[wrqu->length];\n\tu32\t\tinvalxcap = 0, ret = 0, bwrite_xcap = 0, hwxtaladdr = 0;\n\tu16\t\tpgval;\n\n\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tRTW_INFO(\"%s:priv in=%s\\n\", __func__, input);\n\tbwrite_xcap = (strncmp(input, \"write_xcap=\", 11) == 0) ? 1 : 0;\n\n\tif (bwrite_xcap == 1) {\n\t\tret = sscanf(input, \"write_xcap=%d\", &invalxcap);\n\t\tinvalxcap = invalxcap & 0x7f; /* xtal bit 0 ~6 */\n\t\tRTW_INFO(\"get crystal_cap %d\\n\", invalxcap);\n\n\t\tif (IS_HARDWARE_TYPE_8822C(padapter) && ret == 1) {\n\t\t\thwxtaladdr = 0x110;\n\t\t\tpgval = invalxcap | 0x80; /* reserved default bit7 on */\n\t\t\tpgval = pgval | pgval << 8; /* xtal xi/xo efuse 0x110 0x111 */\n\n\t\t\tRTW_INFO(\"Get crystal_cap 0x%x\\n\", pgval);\n\t\t\tif (rtw_efuse_map_write(padapter, hwxtaladdr, 2, (u8*)&pgval) == _FAIL) {\n\t\t\t\t\tRTW_INFO(\"%s: rtw_efuse_map_write xcap error!!\\n\", __func__);\n\t\t\t\t\tsprintf(extra, \"write xcap pgdata fail\");\n\t\t\t\t\tret = -EFAULT;\n\t\t\t} else\n\t\t\t\t\tsprintf(extra, \"write xcap pgdata ok\");\n\n\t\t}\n\t} else {\n\t\tret = sscanf(input, \"xcap=%d\", &invalxcap);\n\n\t\tif (ret == 1) {\n\t\t\tpHalData->crystal_cap = (u8)invalxcap;\n\t\t\tRTW_INFO(\"%s:crystal_cap=%d\\n\", __func__, pHalData->crystal_cap);\n\n\t\t\tif (rtw_phydm_set_crystal_cap(padapter, pHalData->crystal_cap) == _FALSE) {\n\t\t\t\tRTW_ERR(\"set crystal_cap failed\\n\");\n\t\t\t\trtw_warn_on(1);\n\t\t\t}\n\t\t\tsprintf(extra, \"Set xcap=%d\", invalxcap);\n\t\t}\n\t}\n\n\twrqu->length = strlen(extra) + 1;\n\treturn ret;\n}\n\n\nint rtw_mp_SetRFPath(struct net_device *dev,\n\t\t     struct iw_request_info *info,\n\t\t     struct iw_point *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tchar\tinput[wrqu->length];\n\tint\t\tbMain = 1, bTurnoff = 1;\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\tu8 ret = _TRUE;\n#endif\n\n\tRTW_INFO(\"%s:iwpriv in=%s\\n\", __func__, input);\n\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tbMain = strncmp(input, \"1\", 2); /* strncmp TRUE is 0*/\n\tbTurnoff = strncmp(input, \"0\", 3); /* strncmp TRUE is 0*/\n\n\t_rtw_memset(extra, 0, wrqu->length);\n#ifdef CONFIG_ANTENNA_DIVERSITY\n\tif (bMain == 0)\n\t\tret = rtw_mp_set_antdiv(padapter, _TRUE);\n\telse\n\t\tret = rtw_mp_set_antdiv(padapter, _FALSE);\n\tif (ret == _FALSE)\n\t\tRTW_INFO(\"%s:ANTENNA_DIVERSITY FAIL\\n\", __func__);\n#endif\n\n\tif (bMain == 0) {\n\t\tMP_PHY_SetRFPathSwitch(padapter, _TRUE);\n\t\tRTW_INFO(\"%s:PHY_SetRFPathSwitch=TRUE\\n\", __func__);\n\t\tsprintf(extra, \"mp_setrfpath Main\\n\");\n\n\t} else if (bTurnoff == 0) {\n\t\tMP_PHY_SetRFPathSwitch(padapter, _FALSE);\n\t\tRTW_INFO(\"%s:PHY_SetRFPathSwitch=FALSE\\n\", __func__);\n\t\tsprintf(extra, \"mp_setrfpath Aux\\n\");\n\t} else {\n\t\tbMain = MP_PHY_QueryRFPathSwitch(padapter);\n\t\tRTW_INFO(\"%s:PHY_SetRFPathSwitch = %s\\n\", __func__, (bMain ? \"Main\":\"Aux\"));\n\t\tsprintf(extra, \"mp_setrfpath %s\\n\" , (bMain ? \"Main\":\"Aux\"));\n\t}\n\n\twrqu->length = strlen(extra);\n\n\treturn 0;\n}\n\n\nint rtw_mp_switch_rf_path(struct net_device *dev,\n\t\t\tstruct iw_request_info *info,\n\t\t\tstruct iw_point *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tstruct mp_priv *pmp_priv;\n\tchar\tinput[wrqu->length];\n\tint\t\tbwlg = 1, bwla = 1, btg = 1, bbt=1;\n\tu8 ret = 0;\n\n\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tpmp_priv = &padapter->mppriv;\n\n\tRTW_INFO(\"%s: in=%s\\n\", __func__, input);\n\n\tbwlg = strncmp(input, \"WLG\", 3); /* strncmp TRUE is 0*/\n\tbwla = strncmp(input, \"WLA\", 3); /* strncmp TRUE is 0*/\n\tbtg = strncmp(input, \"BTG\", 3); /* strncmp TRUE is 0*/\n\tbbt = strncmp(input, \"BT\", 3); /* strncmp TRUE is 0*/\n\n\t_rtw_memset(extra, 0, wrqu->length);\n#ifdef CONFIG_RTL8821C /* only support for 8821c wlg/wla/btg/bt RF switch path */\n\tif (bwlg == 0) {\n\t\tpmp_priv->rf_path_cfg = SWITCH_TO_WLG;\n\t\tsprintf(extra, \"switch rf path WLG\\n\");\n\t} else if (bwla == 0) {\n\t\tpmp_priv->rf_path_cfg = SWITCH_TO_WLA;\n\t\tsprintf(extra, \"switch rf path WLA\\n\");\n\t} else if (btg == 0) {\n\t\tpmp_priv->rf_path_cfg = SWITCH_TO_BTG;\n\t\tsprintf(extra, \"switch rf path BTG\\n\");\n\t} else if (bbt == 0) {\n\t\tpmp_priv->rf_path_cfg = SWITCH_TO_BT;\n\t\tsprintf(extra, \"switch rf path BG\\n\");\n\t} else {\n\t\tsprintf(extra, \"Error set %s\\n\", __func__);\n\t\treturn -EFAULT;\n\t}\n\n\tmp_phy_switch_rf_path_set(padapter, &pmp_priv->rf_path_cfg);\n#endif\n\n\twrqu->length = strlen(extra);\n\n\treturn ret;\n\n}\nint rtw_mp_QueryDrv(struct net_device *dev,\n\t\t    struct iw_request_info *info,\n\t\t    union iwreq_data *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tchar\tinput[wrqu->data.length];\n\tint\tqAutoLoad = 1;\n\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);\n\n\tif (copy_from_user(input, wrqu->data.pointer, wrqu->data.length))\n\t\treturn -EFAULT;\n\tRTW_INFO(\"%s:iwpriv in=%s\\n\", __func__, input);\n\n\tqAutoLoad = strncmp(input, \"autoload\", 8); /* strncmp TRUE is 0*/\n\n\tif (qAutoLoad == 0) {\n\t\tRTW_INFO(\"%s:qAutoLoad\\n\", __func__);\n\n\t\tif (pHalData->bautoload_fail_flag)\n\t\t\tsprintf(extra, \"fail\");\n\t\telse\n\t\t\tsprintf(extra, \"ok\");\n\t}\n\twrqu->data.length = strlen(extra) + 1;\n\treturn 0;\n}\n\n\nint rtw_mp_PwrCtlDM(struct net_device *dev,\n\t\t    struct iw_request_info *info,\n\t\t    struct iw_point *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tu8\t\tinput[wrqu->length];\n\tint\t\tbstart = 1;\n\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\tbstart = strncmp(input, \"start\", 5); /* strncmp TRUE is 0*/\n\tif (bstart == 0) {\n\t\tsprintf(extra, \"PwrCtlDM start\\n\");\n\t\tMPT_PwrCtlDM(padapter, 1);\n\t} else {\n\t\tsprintf(extra, \"PwrCtlDM stop\\n\");\n\t\tMPT_PwrCtlDM(padapter, 0);\n\t}\n\twrqu->length = strlen(extra);\n\n\treturn 0;\n}\n\nint rtw_mp_iqk(struct net_device *dev,\n\t\t struct iw_request_info *info,\n\t\t struct iw_point *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\n\trtw_mp_trigger_iqk(padapter);\n\n\treturn 0;\n}\n\nint rtw_mp_lck(struct net_device *dev,\n\t\t struct iw_request_info *info,\n\t\t struct iw_point *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\n\trtw_mp_trigger_lck(padapter);\n\n\treturn 0;\n}\n\nint rtw_mp_dpk(struct net_device *dev,\n\t\t\tstruct iw_request_info *info,\n\t\t\tunion iwreq_data *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct dm_struct\t\t*pDM_Odm = &pHalData->odmpriv;\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n\n\tu8 bdpk = 0;\n\tu8 ips_mode = IPS_NUM; /* init invalid value */\n\tu8 lps_mode = PS_MODE_NUM; /* init invalid value */\n\n\tif (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))\n\t\treturn -EFAULT;\n\n\t*(extra + wrqu->data.length) = '\\0';\n\n\tif (strncmp(extra, \"off\", 3) == 0 && strlen(extra) < 4) {\n\t\t\tpDM_Odm->dpk_info.is_dpk_enable = 0;\n\t\t\thalrf_dpk_enable_disable(pDM_Odm);\n\t\t\tsprintf(extra, \"set dpk off\\n\");\n\n\t} else if (strncmp(extra, \"on\", 2) == 0 && strlen(extra) < 3) {\n\t\t\tpDM_Odm->dpk_info.is_dpk_enable = 1;\n\t\t\thalrf_dpk_enable_disable(pDM_Odm);\n\t\t\tsprintf(extra, \"set dpk on\\n\");\n\t} else\t{\n#ifdef CONFIG_LPS\n\t\t\tlps_mode = pwrctrlpriv->power_mgnt;/* keep org value */\n\t\t\trtw_pm_set_lps(padapter, PS_MODE_ACTIVE);\n#endif\n#ifdef CONFIG_IPS\n\t\t\tips_mode = pwrctrlpriv->ips_mode;/* keep org value */\n\t\t\trtw_pm_set_ips(padapter, IPS_NONE);\n#endif\n\t\t\trtw_mp_trigger_dpk(padapter);\n\tif (padapter->registrypriv.mp_mode == 0) {\n#ifdef CONFIG_IPS\n\t\t\trtw_pm_set_ips(padapter, ips_mode);\n#endif /* CONFIG_IPS */\n\n#ifdef CONFIG_LPS\n\t\t\trtw_pm_set_lps(padapter, lps_mode);\n#endif /* CONFIG_LPS */\n\t}\n\t\t\tsprintf(extra, \"set dpk trigger\\n\");\n\t}\n\n\twrqu->data.length = strlen(extra);\n\n\treturn 0;\n}\n\nint rtw_mp_getver(struct net_device *dev,\n\t\t  struct iw_request_info *info,\n\t\t  union iwreq_data *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tstruct mp_priv *pmp_priv;\n\n\tpmp_priv = &padapter->mppriv;\n\n\tif (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))\n\t\treturn -EFAULT;\n\n\tsprintf(extra, \"rtwpriv=%d\\n\", RTWPRIV_VER_INFO);\n\twrqu->data.length = strlen(extra);\n\treturn 0;\n}\n\n\nint rtw_mp_mon(struct net_device *dev,\n\t       struct iw_request_info *info,\n\t       union iwreq_data *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct hal_ops *pHalFunc = &padapter->hal_func;\n\tNDIS_802_11_NETWORK_INFRASTRUCTURE networkType;\n\tint bstart = 1, bstop = 1;\n\n\tnetworkType = Ndis802_11Infrastructure;\n\tif (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))\n\t\treturn -EFAULT;\n\n\t*(extra + wrqu->data.length) = '\\0';\n\trtw_pm_set_ips(padapter, IPS_NONE);\n\tLeaveAllPowerSaveMode(padapter);\n\n#ifdef CONFIG_MP_INCLUDED\n\tif (init_mp_priv(padapter) == _FAIL)\n\t\tRTW_INFO(\"%s: initialize MP private data Fail!\\n\", __func__);\n\tpadapter->mppriv.channel = 6;\n\n\tbstart = strncmp(extra, \"start\", 5); /* strncmp TRUE is 0*/\n\tbstop = strncmp(extra, \"stop\", 4); /* strncmp TRUE is 0*/\n\tif (bstart == 0) {\n\t\tmp_join(padapter, WIFI_FW_ADHOC_STATE);\n\t\tSetPacketRx(padapter, _TRUE, _FALSE);\n\t\tSetChannel(padapter);\n\t\tpmp_priv->rx_bindicatePkt = _TRUE;\n\t\tpmp_priv->bRTWSmbCfg = _TRUE;\n\t\tsprintf(extra, \"monitor mode start\\n\");\n\t} else if (bstop == 0) {\n\t\tSetPacketRx(padapter, _FALSE, _FALSE);\n\t\tpmp_priv->rx_bindicatePkt = _FALSE;\n\t\tpmp_priv->bRTWSmbCfg = _FALSE;\n\t\tpadapter->registrypriv.mp_mode = 1;\n\t\tpHalFunc->hal_deinit(padapter);\n\t\tpadapter->registrypriv.mp_mode = 0;\n\t\tpHalFunc->hal_init(padapter);\n\t\t/*rtw_disassoc_cmd(padapter, 0, 0);*/\n\t\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {\n\t\t\trtw_disassoc_cmd(padapter, 500, 0);\n\t\t\trtw_indicate_disconnect(padapter, 0, _FALSE);\n\t\t\t/*rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);*/\n\t\t}\n\t\trtw_pm_set_ips(padapter, IPS_NORMAL);\n\t\tsprintf(extra, \"monitor mode Stop\\n\");\n\t}\n#endif\n\twrqu->data.length = strlen(extra);\n\treturn 0;\n}\n\nint rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra)\n{\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\tchar *pextra = extra;\n\n\tswitch (pmp_priv->mode) {\n\n\tcase MP_PACKET_TX:\n\t\tif (bStartTest == 0) {\n\t\t\tpmp_priv->tx.stop = 1;\n\t\t\tpmp_priv->mode = MP_ON;\n\t\t\t#ifdef CONFIG_RTL8822B\n\t\t\trtw_write8(padapter, 0x838, 0x61);\n\t\t\t#endif\n\t\t\tsprintf(extra, \"Stop continuous Tx\");\n\t\t} else if (pmp_priv->tx.stop == 1) {\n\t\t\tpextra = extra + strlen(extra);\n\t\t\tpextra += sprintf(pextra, \"\\nStart continuous DA=ffffffffffff len=1500 count=%u\\n\", pmp_priv->tx.count);\n\t\t\tpmp_priv->tx.stop = 0;\n\t\t\t#ifdef CONFIG_RTL8822B\n\t\t\trtw_write8(padapter, 0x838, 0x6d);\n\t\t\t#endif\n\t\t\tSetPacketTx(padapter);\n\t\t} else\n\t\t\treturn -EFAULT;\n\t\treturn 0;\n\tcase MP_SINGLE_TONE_TX:\n\t\tif (bStartTest != 0)\n\t\t\tstrcat(extra, \"\\nStart continuous DA=ffffffffffff len=1500\\n infinite=yes.\");\n\t\tSetSingleToneTx(padapter, (u8)bStartTest);\n\t\tbreak;\n\tcase MP_CONTINUOUS_TX:\n\t\tif (bStartTest != 0)\n\t\t\tstrcat(extra, \"\\nStart continuous DA=ffffffffffff len=1500\\n infinite=yes.\");\n\t\tSetContinuousTx(padapter, (u8)bStartTest);\n\t\tbreak;\n\tcase MP_CARRIER_SUPPRISSION_TX:\n\t\tif (bStartTest != 0) {\n\t\t\tif (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_11M)\n\t\t\t\tstrcat(extra, \"\\nStart continuous DA=ffffffffffff len=1500\\n infinite=yes.\");\n\t\t\telse\n\t\t\t\tstrcat(extra, \"\\nSpecify carrier suppression but not CCK rate\");\n\t\t}\n\t\tSetCarrierSuppressionTx(padapter, (u8)bStartTest);\n\t\tbreak;\n\tcase MP_SINGLE_CARRIER_TX:\n\t\tif (bStartTest != 0)\n\t\t\tstrcat(extra, \"\\nStart continuous DA=ffffffffffff len=1500\\n infinite=yes.\");\n\t\tSetSingleCarrierTx(padapter, (u8)bStartTest);\n\t\tbreak;\n\n\tdefault:\n\t\tsprintf(extra, \"Error! Continuous-Tx is not on-going.\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (bStartTest == 1 && pmp_priv->mode != MP_ON) {\n\t\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\n\t\tif (pmp_priv->tx.stop == 0) {\n\t\t\tpmp_priv->tx.stop = 1;\n\t\t\trtw_msleep_os(5);\n\t\t}\n#ifdef CONFIG_80211N_HT\n\t\tif(padapter->registrypriv.ht_enable &&\n\t\t\tis_supported_ht(padapter->registrypriv.wireless_mode))\n\t\t\tpmp_priv->tx.attrib.ht_en = 1;\n#endif\n\t\tpmp_priv->tx.stop = 0;\n\t\tpmp_priv->tx.count = 1;\n\t\tSetPacketTx(padapter);\n\t} else\n\t\tpmp_priv->mode = MP_ON;\n\n#if defined(CONFIG_RTL8812A)\n\tif (IS_HARDWARE_TYPE_8812AU(padapter)) {\n\t\t/* <20130425, Kordan> Turn off OFDM Rx to prevent from CCA causing Tx hang.*/\n\t\tif (pmp_priv->mode == MP_PACKET_TX)\n\t\t\tphy_set_bb_reg(padapter, rCCAonSec_Jaguar, BIT3, 1);\n\t\telse\n\t\t\tphy_set_bb_reg(padapter, rCCAonSec_Jaguar, BIT3, 0);\n\t}\n#endif\n\n\treturn 0;\n}\n\n\nint rtw_mp_tx(struct net_device *dev,\n\t      struct iw_request_info *info,\n\t      union iwreq_data *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE\t*pHalData\t= GET_HAL_DATA(padapter);\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\tPMPT_CONTEXT\t\tpMptCtx = &(padapter->mppriv.mpt_ctx);\n\tchar *pextra = extra;\n\tu32 bandwidth = 0, sg = 0, channel = 6, txpower = 40, rate = 108, ant = 0, txmode = 1, count = 0;\n\tu8 bStartTest = 1, status = 0;\n#ifdef CONFIG_MP_VHT_HW_TX_MODE\n\tu8 Idx = 0, tmpU1B;\n#endif\n\tu16 antenna = 0;\n\n\tif (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))\n\t\treturn -EFAULT;\n\tRTW_INFO(\"extra = %s\\n\", extra);\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (!is_primary_adapter(padapter)) {\n\t\tsprintf(extra, \"Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\\n\");\n\t\twrqu->data.length = strlen(extra);\n\t\treturn 0;\n\t}\n#endif\n\n\tif (strncmp(extra, \"stop\", 3) == 0) {\n\t\tbStartTest = 0; /* To set Stop*/\n\t\tpmp_priv->tx.stop = 1;\n\t\tsprintf(extra, \"Stop continuous Tx\");\n\t\tstatus = rtw_mp_pretx_proc(padapter, bStartTest, extra);\n\t\twrqu->data.length = strlen(extra);\n\t\treturn status;\n\t} else if (strncmp(extra, \"count\", 5) == 0) {\n\t\tif (sscanf(extra, \"count=%d\", &count) < 1)\n\t\t\tRTW_INFO(\"Got Count=%d]\\n\", count);\n\t\tpmp_priv->tx.count = count;\n\t\treturn 0;\n\t} else if (strncmp(extra, \"setting\", 7) == 0) {\n\t\t_rtw_memset(extra, 0, wrqu->data.length);\n\t\tpextra += sprintf(pextra, \"Current Setting :\\n Channel:%d\", pmp_priv->channel);\n\t\tpextra += sprintf(pextra, \"\\n Bandwidth:%d\", pmp_priv->bandwidth);\n\t\tpextra += sprintf(pextra, \"\\n Rate index:%d\", pmp_priv->rateidx);\n\t\tpextra += sprintf(pextra, \"\\n TxPower index:%d\", pmp_priv->txpoweridx);\n\t\tpextra += sprintf(pextra, \"\\n Antenna TxPath:%d\", pmp_priv->antenna_tx);\n\t\tpextra += sprintf(pextra, \"\\n Antenna RxPath:%d\", pmp_priv->antenna_rx);\n\t\tpextra += sprintf(pextra, \"\\n MP Mode:%d\", pmp_priv->mode);\n\t\twrqu->data.length = strlen(extra);\n\t\treturn 0;\n#ifdef CONFIG_MP_VHT_HW_TX_MODE\n\t} else if (strncmp(extra, \"pmact\", 5) == 0) {\n\t\tif (strncmp(extra, \"pmact=\", 6) == 0) {\n\t\t\t_rtw_memset(&pMptCtx->PMacTxInfo, 0, sizeof(pMptCtx->PMacTxInfo));\n\t\t\tif (strncmp(extra, \"pmact=start\", 11) == 0) {\n\t\t\t\tpMptCtx->PMacTxInfo.bEnPMacTx = _TRUE;\n\t\t\t\tsprintf(extra, \"Set PMac Tx Mode start\\n\");\n\t\t\t} else {\n\t\t\t\tpMptCtx->PMacTxInfo.bEnPMacTx = _FALSE;\n\t\t\t\tsprintf(extra, \"Set PMac Tx Mode Stop\\n\");\n\t\t\t}\n\t\t\tif (pMptCtx->bldpc == TRUE)\n\t\t\t\tpMptCtx->PMacTxInfo.bLDPC = _TRUE;\n\n\t\t\tif (pMptCtx->bstbc == TRUE)\n\t\t\t\tpMptCtx->PMacTxInfo.bSTBC = _TRUE;\n\n\t\t\tpMptCtx->PMacTxInfo.bSPreamble = pmp_priv->preamble;\n\t\t\tpMptCtx->PMacTxInfo.bSGI = pmp_priv->preamble;\n\t\t\tpMptCtx->PMacTxInfo.BandWidth = pmp_priv->bandwidth;\n\t\t\tpMptCtx->PMacTxInfo.TX_RATE = HwRateToMPTRate(pmp_priv->rateidx);\n\n\t\t\tpMptCtx->PMacTxInfo.Mode = pMptCtx->HWTxmode;\n\n\t\t\tpMptCtx->PMacTxInfo.NDP_sound = FALSE;/*(Adapter.PacketType == NDP_PKT)?TRUE:FALSE;*/\n\n\t\t\tif (padapter->mppriv.pktInterval == 0)\n\t\t\t\tpMptCtx->PMacTxInfo.PacketPeriod = 100;\n\t\t\telse\n\t\t\t\tpMptCtx->PMacTxInfo.PacketPeriod = padapter->mppriv.pktInterval;\n\n\t\t\tif (padapter->mppriv.pktLength < 1000)\n\t\t\t\tpMptCtx->PMacTxInfo.PacketLength = 1000;\n\t\t\telse\n\t\t\t\tpMptCtx->PMacTxInfo.PacketLength = padapter->mppriv.pktLength;\n\n\t\t\tpMptCtx->PMacTxInfo.PacketPattern  = rtw_random32() % 0xFF;\n\n\t\t\tif (padapter->mppriv.tx_pktcount != 0)\n\t\t\t\tpMptCtx->PMacTxInfo.PacketCount = padapter->mppriv.tx_pktcount;\n\n\t\t\tpMptCtx->PMacTxInfo.Ntx = 0;\n\t\t\tfor (Idx = 16; Idx < 20; Idx++) {\n\t\t\t\ttmpU1B = (padapter->mppriv.antenna_tx >> Idx) & 1;\n\t\t\t\tif (tmpU1B)\n\t\t\t\t\tpMptCtx->PMacTxInfo.Ntx++;\n\t\t\t}\n\n\t\t\t_rtw_memset(pMptCtx->PMacTxInfo.MacAddress, 0xFF, ETH_ALEN);\n\n\t\t\tPMAC_Get_Pkt_Param(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);\n\n\t\t\tif (MPT_IS_CCK_RATE(pMptCtx->PMacTxInfo.TX_RATE))\n\n\t\t\t\tCCK_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);\n\t\t\telse {\n\t\t\t\tPMAC_Nsym_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);\n\t\t\t\t/* 24 BIT*/\n\t\t\t\tL_SIG_generator(pMptCtx->PMacPktInfo.N_sym, &pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);\n\t\t\t}\n\t\t\t/*\t48BIT*/\n\t\t\tif (MPT_IS_HT_RATE(pMptCtx->PMacTxInfo.TX_RATE))\n\t\t\t\tHT_SIG_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);\n\t\t\telse if (MPT_IS_VHT_RATE(pMptCtx->PMacTxInfo.TX_RATE)) {\n\t\t\t\t/*\t48BIT*/\n\t\t\t\tVHT_SIG_A_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);\n\n\t\t\t\t/*\t26/27/29 BIT  & CRC 8 BIT*/\n\t\t\t\tVHT_SIG_B_generator(&pMptCtx->PMacTxInfo);\n\n\t\t\t\t/* 32 BIT*/\n\t\t\t\tVHT_Delimiter_generator(&pMptCtx->PMacTxInfo);\n\t\t\t}\n\n\t\t\tmpt_ProSetPMacTx(padapter);\n\n\t\t} else if (strncmp(extra, \"pmact,mode=\", 11) == 0) {\n\t\t\tint txmode = 0;\n\n\t\t\tif (sscanf(extra, \"pmact,mode=%d\", &txmode) > 0) {\n\t\t\t\tif (txmode == 1) {\n\t\t\t\t\tpMptCtx->HWTxmode = CONTINUOUS_TX;\n\t\t\t\t\tsprintf(extra, \"\\t Config HW Tx mode = CONTINUOUS_TX\\n\");\n\t\t\t\t} else if (txmode == 2) {\n\t\t\t\t\tpMptCtx->HWTxmode = OFDM_Single_Tone_TX;\n\t\t\t\t\tsprintf(extra, \"\\t Config HW Tx mode = OFDM_Single_Tone_TX\\n\");\n\t\t\t\t} else {\n\t\t\t\t\tpMptCtx->HWTxmode = PACKETS_TX;\n\t\t\t\t\tsprintf(extra, \"\\t Config HW Tx mode = PACKETS_TX\\n\");\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tpMptCtx->HWTxmode = PACKETS_TX;\n\t\t\t\tsprintf(extra, \"\\t Config HW Tx mode=\\n 0 = PACKETS_TX\\n 1 = CONTINUOUS_TX\\n 2 = OFDM_Single_Tone_TX\");\n\t\t\t}\n\t\t} else if (strncmp(extra, \"pmact,\", 6) == 0) {\n\t\t\tint PacketPeriod = 0, PacketLength = 0, PacketCout = 0;\n\t\t\tint bldpc = 0, bstbc = 0;\n\n\t\t\tif (sscanf(extra, \"pmact,period=%d\", &PacketPeriod) > 0) {\n\t\t\t\tpadapter->mppriv.pktInterval = PacketPeriod;\n\t\t\t\tRTW_INFO(\"PacketPeriod=%d\\n\", padapter->mppriv.pktInterval);\n\t\t\t\tsprintf(extra, \"PacketPeriod [1~255]= %d\\n\", padapter->mppriv.pktInterval);\n\n\t\t\t} else if (sscanf(extra, \"pmact,length=%d\", &PacketLength) > 0) {\n\t\t\t\tpadapter->mppriv.pktLength = PacketLength;\n\t\t\t\tRTW_INFO(\"PacketPeriod=%d\\n\", padapter->mppriv.pktLength);\n\t\t\t\tsprintf(extra, \"PacketLength[~65535]=%d\\n\", padapter->mppriv.pktLength);\n\n\t\t\t} else if (sscanf(extra, \"pmact,count=%d\", &PacketCout) > 0) {\n\t\t\t\tpadapter->mppriv.tx_pktcount = PacketCout;\n\t\t\t\tRTW_INFO(\"Packet Cout =%d\\n\", padapter->mppriv.tx_pktcount);\n\t\t\t\tsprintf(extra, \"Packet Cout =%d\\n\", padapter->mppriv.tx_pktcount);\n\n\t\t\t} else if (sscanf(extra, \"pmact,ldpc=%d\", &bldpc) > 0) {\n\t\t\t\tpMptCtx->bldpc = bldpc;\n\t\t\t\tRTW_INFO(\"Set LDPC =%d\\n\", pMptCtx->bldpc);\n\t\t\t\tsprintf(extra, \"Set LDPC =%d\\n\", pMptCtx->bldpc);\n\n\t\t\t} else if (sscanf(extra, \"pmact,stbc=%d\", &bstbc) > 0) {\n\t\t\t\tpMptCtx->bstbc = bstbc;\n\t\t\t\tRTW_INFO(\"Set STBC =%d\\n\", pMptCtx->bstbc);\n\t\t\t\tsprintf(extra, \"Set STBC =%d\\n\", pMptCtx->bstbc);\n\t\t\t} else\n\t\t\t\tsprintf(extra, \"\\n period={1~255}\\n length={1000~65535}\\n count={0~}\\n ldpc={0/1}\\n stbc={0/1}\");\n\n\t\t}\n\n\t\twrqu->data.length = strlen(extra);\n\t\treturn 0;\n#endif\n\t} else {\n\n\t\tif (sscanf(extra, \"ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d\", &channel, &bandwidth, &rate, &txpower, &ant, &txmode) < 6) {\n\t\t\tRTW_INFO(\"Invalid format [ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d]\\n\", channel, bandwidth, rate, txpower, ant, txmode);\n\t\t\t_rtw_memset(extra, 0, wrqu->data.length);\n\t\t\tpextra += sprintf(pextra, \"\\n Please input correct format as bleow:\\n\");\n\t\t\tpextra += sprintf(pextra, \"\\t ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d\\n\", channel, bandwidth, rate, txpower, ant, txmode);\n\t\t\tpextra += sprintf(pextra, \"\\n [ ch : BGN = <1~14> , A or AC = <36~165> ]\");\n\t\t\tpextra += sprintf(pextra, \"\\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]\");\n\t\t\tpextra += sprintf(pextra, \"\\n [ rate :\tCCK: 1 2 5.5 11M X 2 = < 2 4 11 22 >]\");\n\t\t\tpextra += sprintf(pextra, \"\\n [\t\tOFDM: 6 9 12 18 24 36 48 54M X 2 = < 12 18 24 36 48 72 96 108>\");\n\t\t\tpextra += sprintf(pextra, \"\\n [\t\tHT 1S2SS MCS0 ~ MCS15 : < [MCS0]=128 ~ [MCS7]=135 ~ [MCS15]=143 >\");\n\t\t\tpextra += sprintf(pextra, \"\\n [\t\tHT 3SS MCS16 ~ MCS32 : < [MCS16]=144 ~ [MCS23]=151 ~ [MCS32]=159 >\");\n\t\t\tpextra += sprintf(pextra, \"\\n [\t\tVHT 1SS MCS0 ~ MCS9 : < [MCS0]=160 ~ [MCS9]=169 >\");\n\t\t\tpextra += sprintf(pextra, \"\\n [ txpower : 1~63 power index\");\n\t\t\tpextra += sprintf(pextra, \"\\n [ ant : <A = 1, B = 2, C = 4, D = 8> ,2T ex: AB=3 BC=6 CD=12\");\n\t\t\tpextra += sprintf(pextra, \"\\n [ txmode : < 0 = CONTINUOUS_TX, 1 = PACKET_TX, 2 = SINGLE_TONE_TX, 3 = CARRIER_SUPPRISSION_TX, 4 = SINGLE_CARRIER_TX>\\n\");\n\t\t\twrqu->data.length = strlen(extra);\n\t\t\treturn status;\n\n\t\t} else {\n\t\t\tchar *pextra = extra;\n\t\t\tRTW_INFO(\"Got format [ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d]\\n\", channel, bandwidth, rate, txpower, ant, txmode);\n\t\t\t_rtw_memset(extra, 0, wrqu->data.length);\n\t\t\tsprintf(extra, \"Change Current channel %d to channel %d\", padapter->mppriv.channel , channel);\n\t\t\tpadapter->mppriv.channel = channel;\n\t\t\tSetChannel(padapter);\n\t\t\tpHalData->current_channel = channel;\n\n\t\t\tif (bandwidth == 1)\n\t\t\t\tbandwidth = CHANNEL_WIDTH_40;\n\t\t\telse if (bandwidth == 2)\n\t\t\t\tbandwidth = CHANNEL_WIDTH_80;\n\t\t\tpextra = extra + strlen(pextra);\n\t\t\tpextra += sprintf(pextra, \"\\nChange Current Bandwidth %d to Bandwidth %d\", padapter->mppriv.bandwidth, bandwidth);\n\t\t\tpadapter->mppriv.bandwidth = (u8)bandwidth;\n\t\t\tpadapter->mppriv.preamble = sg;\n\t\t\tSetBandwidth(padapter);\n\t\t\tpHalData->current_channel_bw = bandwidth;\n\n\t\t\tpextra += sprintf(pextra, \"\\nSet power level :%d\", txpower);\n\t\t\tpadapter->mppriv.txpoweridx = (u8)txpower;\n\t\t\tpMptCtx->TxPwrLevel[RF_PATH_A] = (u8)txpower;\n\t\t\tpMptCtx->TxPwrLevel[RF_PATH_B] = (u8)txpower;\n\t\t\tpMptCtx->TxPwrLevel[RF_PATH_C] = (u8)txpower;\n\t\t\tpMptCtx->TxPwrLevel[RF_PATH_D]  = (u8)txpower;\n\t\t\tSetTxPower(padapter);\n\n\t\t\tRTW_INFO(\"%s: bw=%d sg=%d\\n\", __func__, bandwidth, sg);\n\n\t\t\tif (rate <= 0x7f)\n\t\t\t\trate = wifirate2_ratetbl_inx((u8)rate);\n\t\t\telse if (rate < 0xC8)\n\t\t\t\trate = (rate - 0x80 + MPT_RATE_MCS0);\n\t\t\t/*HT  rate 0x80(MCS0)  ~ 0x8F(MCS15) ~ 0x9F(MCS31) 128~159\n\t\t\tVHT1SS~2SS rate 0xA0 (VHT1SS_MCS0 44) ~ 0xB3 (VHT2SS_MCS9 #63) 160~179\n\t\t\tVHT rate 0xB4 (VHT3SS_MCS0 64) ~ 0xC7 (VHT2SS_MCS9 #83) 180~199\n\t\t\telse\n\t\t\tVHT rate 0x90(VHT1SS_MCS0) ~ 0x99(VHT1SS_MCS9) 144~153\n\t\t\trate =(rate - MPT_RATE_VHT1SS_MCS0);\n\t\t\t*/\n\t\t\tRTW_INFO(\"%s: rate index=%d\\n\", __func__, rate);\n\t\t\tif (rate >= MPT_RATE_LAST)\n\t\t\t\treturn -EINVAL;\n\t\t\tpextra += sprintf(pextra, \"\\nSet data rate to %d index %d\", padapter->mppriv.rateidx, rate);\n\n\t\t\tpadapter->mppriv.rateidx = rate;\n\t\t\tpMptCtx->mpt_rate_index = rate;\n\t\t\tSetDataRate(padapter);\n\n\t\t\tpextra += sprintf(pextra, \"\\nSet Antenna Path :%d\", ant);\n\t\t\tswitch (ant) {\n\t\t\tcase 1:\n\t\t\t\tantenna = ANTENNA_A;\n\t\t\t\tbreak;\n\t\t\tcase 2:\n\t\t\t\tantenna = ANTENNA_B;\n\t\t\t\tbreak;\n\t\t\tcase 4:\n\t\t\t\tantenna = ANTENNA_C;\n\t\t\t\tbreak;\n\t\t\tcase 8:\n\t\t\t\tantenna = ANTENNA_D;\n\t\t\t\tbreak;\n\t\t\tcase 3:\n\t\t\t\tantenna = ANTENNA_AB;\n\t\t\t\tbreak;\n\t\t\tcase 5:\n\t\t\t\tantenna = ANTENNA_AC;\n\t\t\t\tbreak;\n\t\t\tcase 9:\n\t\t\t\tantenna = ANTENNA_AD;\n\t\t\t\tbreak;\n\t\t\tcase 6:\n\t\t\t\tantenna = ANTENNA_BC;\n\t\t\t\tbreak;\n\t\t\tcase 10:\n\t\t\t\tantenna = ANTENNA_BD;\n\t\t\t\tbreak;\n\t\t\tcase 12:\n\t\t\t\tantenna = ANTENNA_CD;\n\t\t\t\tbreak;\n\t\t\tcase 7:\n\t\t\t\tantenna = ANTENNA_ABC;\n\t\t\t\tbreak;\n\t\t\tcase 14:\n\t\t\t\tantenna = ANTENNA_BCD;\n\t\t\t\tbreak;\n\t\t\tcase 11:\n\t\t\t\tantenna = ANTENNA_ABD;\n\t\t\t\tbreak;\n\t\t\tcase 15:\n\t\t\t\tantenna = ANTENNA_ABCD;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tRTW_INFO(\"%s: antenna=0x%x\\n\", __func__, antenna);\n\t\t\tpadapter->mppriv.antenna_tx = antenna;\n\t\t\tpadapter->mppriv.antenna_rx = antenna;\n\t\t\tpHalData->antenna_tx_path = antenna;\n\t\t\tSetAntenna(padapter);\n\n\t\t\tif (txmode == 0)\n\t\t\t\tpmp_priv->mode = MP_CONTINUOUS_TX;\n\t\t\telse if (txmode == 1) {\n\t\t\t\tpmp_priv->mode = MP_PACKET_TX;\n\t\t\t\tpmp_priv->tx.count = count;\n\t\t\t} else if (txmode == 2)\n\t\t\t\tpmp_priv->mode = MP_SINGLE_TONE_TX;\n\t\t\telse if (txmode == 3)\n\t\t\t\tpmp_priv->mode = MP_CARRIER_SUPPRISSION_TX;\n\t\t\telse if (txmode == 4)\n\t\t\t\tpmp_priv->mode = MP_SINGLE_CARRIER_TX;\n\n\t\t\tstatus = rtw_mp_pretx_proc(padapter, bStartTest, extra);\n\t\t}\n\n\t}\n\n\twrqu->data.length = strlen(extra);\n\treturn status;\n}\n\n\nint rtw_mp_rx(struct net_device *dev,\n\t      struct iw_request_info *info,\n\t      union iwreq_data *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE\t*pHalData\t= GET_HAL_DATA(padapter);\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\tchar *pextra = extra;\n\tu32 bandwidth = 0, sg = 0, channel = 6, ant = 0;\n\tu16 antenna = 0;\n\tu8 bStartRx = 0;\n\n\tif (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))\n\t\treturn -EFAULT;\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (!is_primary_adapter(padapter)) {\n\t\tsprintf(extra, \"Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\\n\");\n\t\twrqu->data.length = strlen(extra);\n\t\treturn 0;\n\t}\n#endif\n\n\tif (strncmp(extra, \"stop\", 4) == 0) {\n\t\t_rtw_memset(extra, 0, wrqu->data.length);\n\t\tSetPacketRx(padapter, bStartRx, _FALSE);\n\t\tpmp_priv->bmac_filter = _FALSE;\n\t\tsprintf(extra, \"Received packet OK:%d CRC error:%d ,Filter out:%d\", padapter->mppriv.rx_pktcount, padapter->mppriv.rx_crcerrpktcount, padapter->mppriv.rx_pktcount_filter_out);\n\t\twrqu->data.length = strlen(extra);\n\t\treturn 0;\n\n\t} else if (sscanf(extra, \"ch=%d,bw=%d,ant=%d\", &channel, &bandwidth, &ant) < 3) {\n\t\tRTW_INFO(\"Invalid format [ch=%d,bw=%d,ant=%d]\\n\", channel, bandwidth, ant);\n\t\t_rtw_memset(extra, 0, wrqu->data.length);\n\t\tpextra += sprintf(pextra, \"\\n Please input correct format as bleow:\\n\");\n\t\tpextra += sprintf(pextra, \"\\t ch=%d,bw=%d,ant=%d\\n\", channel, bandwidth, ant);\n\t\tpextra += sprintf(pextra, \"\\n [ ch : BGN = <1~14> , A or AC = <36~165> ]\");\n\t\tpextra += sprintf(pextra, \"\\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]\");\n\t\tpextra += sprintf(pextra, \"\\n [ ant : <A = 1, B = 2, C = 4, D = 8> ,2T ex: AB=3 BC=6 CD=12\");\n\t\twrqu->data.length = strlen(extra);\n\t\treturn 0;\n\n\t} else {\n\t\tchar *pextra = extra;\n\t\tbStartRx = 1;\n\t\tRTW_INFO(\"Got format [ch=%d,bw=%d,ant=%d]\\n\", channel, bandwidth, ant);\n\t\t_rtw_memset(extra, 0, wrqu->data.length);\n\t\tsprintf(extra, \"Change Current channel %d to channel %d\", padapter->mppriv.channel , channel);\n\t\tpadapter->mppriv.channel = channel;\n\t\tSetChannel(padapter);\n\t\tpHalData->current_channel = channel;\n\n\t\tif (bandwidth == 1)\n\t\t\tbandwidth = CHANNEL_WIDTH_40;\n\t\telse if (bandwidth == 2)\n\t\t\tbandwidth = CHANNEL_WIDTH_80;\n\t\tpextra = extra + strlen(extra);\n\t\tpextra += sprintf(pextra, \"\\nChange Current Bandwidth %d to Bandwidth %d\", padapter->mppriv.bandwidth, bandwidth);\n\t\tpadapter->mppriv.bandwidth = (u8)bandwidth;\n\t\tpadapter->mppriv.preamble = sg;\n\t\tSetBandwidth(padapter);\n\t\tpHalData->current_channel_bw = bandwidth;\n\n\t\tpextra += sprintf(pextra, \"\\nSet Antenna Path :%d\", ant);\n\t\tswitch (ant) {\n\t\tcase 1:\n\t\t\tantenna = ANTENNA_A;\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tantenna = ANTENNA_B;\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\tantenna = ANTENNA_C;\n\t\t\tbreak;\n\t\tcase 8:\n\t\t\tantenna = ANTENNA_D;\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\tantenna = ANTENNA_AB;\n\t\t\tbreak;\n\t\tcase 5:\n\t\t\tantenna = ANTENNA_AC;\n\t\t\tbreak;\n\t\tcase 9:\n\t\t\tantenna = ANTENNA_AD;\n\t\t\tbreak;\n\t\tcase 6:\n\t\t\tantenna = ANTENNA_BC;\n\t\t\tbreak;\n\t\tcase 10:\n\t\t\tantenna = ANTENNA_BD;\n\t\t\tbreak;\n\t\tcase 12:\n\t\t\tantenna = ANTENNA_CD;\n\t\t\tbreak;\n\t\tcase 7:\n\t\t\tantenna = ANTENNA_ABC;\n\t\t\tbreak;\n\t\tcase 14:\n\t\t\tantenna = ANTENNA_BCD;\n\t\t\tbreak;\n\t\tcase 11:\n\t\t\tantenna = ANTENNA_ABD;\n\t\t\tbreak;\n\t\tcase 15:\n\t\t\tantenna = ANTENNA_ABCD;\n\t\t\tbreak;\n\t\t}\n\t\tRTW_INFO(\"%s: antenna=0x%x\\n\", __func__, antenna);\n\t\tpadapter->mppriv.antenna_tx = antenna;\n\t\tpadapter->mppriv.antenna_rx = antenna;\n\t\tpHalData->antenna_tx_path = antenna;\n\t\tSetAntenna(padapter);\n\n\t\tstrcat(extra, \"\\nstart Rx\");\n\t\tSetPacketRx(padapter, bStartRx, _FALSE);\n\t}\n\twrqu->data.length = strlen(extra);\n\treturn 0;\n}\n\n\nint rtw_mp_hwtx(struct net_device *dev,\n\t\tstruct iw_request_info *info,\n\t\tunion iwreq_data *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\tPMPT_CONTEXT\t\tpMptCtx = &(padapter->mppriv.mpt_ctx);\n\n#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)\n\tif (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))\n\t\treturn -EFAULT;\n\t*(extra + wrqu->data.length) = '\\0';\n\n\t_rtw_memset(&pMptCtx->PMacTxInfo, 0, sizeof(RT_PMAC_TX_INFO));\n\t_rtw_memcpy((void *)&pMptCtx->PMacTxInfo, (void *)extra, sizeof(RT_PMAC_TX_INFO));\n\t_rtw_memset(extra, 0, wrqu->data.length);\n\n\tif (pMptCtx->PMacTxInfo.bEnPMacTx == 1 && pmp_priv->mode != MP_ON) {\n\t\tsprintf(extra, \"MP Tx Running, Please Set PMac Tx Mode Stop\\n\");\n\t\tRTW_INFO(\"Error !!! MP Tx Running, Please Set PMac Tx Mode Stop\\n\");\n\t} else {\n\t\tRTW_INFO(\"To set MAC Tx mode\\n\");\n\t\tmpt_ProSetPMacTx(padapter);\n\t\tsprintf(extra, \"Set PMac Tx Mode OK\\n\");\n\t}\n\twrqu->data.length = strlen(extra);\n#endif\n\treturn 0;\n\n}\n\nint rtw_mp_pwrlmt(struct net_device *dev,\n\t\t\tstruct iw_request_info *info,\n\t\t\tunion iwreq_data *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tstruct registry_priv  *registry_par = &padapter->registrypriv;\n\tu8 pwrlimtstat = 0;\n\n\tif (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))\n\t\treturn -EFAULT;\n\n\t*(extra + wrqu->data.length) = '\\0';\n#if CONFIG_TXPWR_LIMIT\n\tpwrlimtstat = registry_par->RegEnableTxPowerLimit;\n\tif (strncmp(extra, \"off\", 3) == 0 && strlen(extra) < 4) {\n\t\tpadapter->registrypriv.RegEnableTxPowerLimit = 0;\n\t\tsprintf(extra, \"Turn off Power Limit\\n\");\n\n\t} else if (strncmp(extra, \"on\", 2) == 0 && strlen(extra) < 3) {\n\t\tpadapter->registrypriv.RegEnableTxPowerLimit = 1;\n\t\tsprintf(extra, \"Turn on Power Limit\\n\");\n\n\t} else\n#endif\n\t\tsprintf(extra, \"Get Power Limit Status:%s\\n\", (pwrlimtstat == 1) ? \"ON\" : \"OFF\");\n\n\n\twrqu->data.length = strlen(extra);\n\treturn 0;\n}\n\nint rtw_mp_pwrbyrate(struct net_device *dev,\n\t\t\tstruct iw_request_info *info,\n\t\t\tunion iwreq_data *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\n\tif (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))\n\t\treturn -EFAULT;\n\n\t*(extra + wrqu->data.length) = '\\0';\n\tif (strncmp(extra, \"off\", 3) == 0 && strlen(extra) < 4) {\n\t\tpadapter->registrypriv.RegEnableTxPowerByRate = 0;\n\t\tsprintf(extra, \"Turn off Tx Power by Rate\\n\");\n\n\t} else if (strncmp(extra, \"on\", 2) == 0 && strlen(extra) < 3) {\n\t\tpadapter->registrypriv.RegEnableTxPowerByRate = 1;\n\t\tsprintf(extra, \"Turn On Tx Power by Rate\\n\");\n\n\t} else {\n\t\tsprintf(extra, \"Get Power by Rate Status:%s\\n\", (padapter->registrypriv.RegEnableTxPowerByRate == 1) ? \"ON\" : \"OFF\");\n\t}\n\n\twrqu->data.length = strlen(extra);\n\treturn 0;\n}\n\n\nint rtw_mp_dpk_track(struct net_device *dev,\n\t\t\tstruct iw_request_info *info,\n\t\t\tunion iwreq_data *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct dm_struct\t\t*pDM_Odm = &pHalData->odmpriv;\n\n\tu8 dpk_track_state = 0;\n\n\tif (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))\n\t\treturn -EFAULT;\n\n\t*(extra + wrqu->data.length) = '\\0';\n\n\tif (strncmp(extra, \"off\", 3) == 0 && strlen(extra) < 4) {\n\t\thalrf_set_dpk_track(pDM_Odm, FALSE);\n\t\tsprintf(extra, \"set dpk track off\\n\");\n\n\t} else if (strncmp(extra, \"on\", 2) == 0 && strlen(extra) < 3) {\n\t\thalrf_set_dpk_track(pDM_Odm, TRUE);\n\t\tsprintf(extra, \"set dpk track on\\n\");\n\t}\n\n\twrqu->data.length = strlen(extra);\n\treturn 0;\n}\n\n\nint rtw_bt_efuse_mask_file(struct net_device *dev,\n\t\t\tstruct iw_request_info *info,\n\t\t\tunion iwreq_data *wrqu, char *extra)\n{\n\tchar *rtw_efuse_mask_file_path;\n\tu8 Status;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\n\t_rtw_memset(btmaskfileBuffer, 0x00, sizeof(btmaskfileBuffer));\n\n\tif (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))\n\t\treturn -EFAULT;\n\n\t*(extra + wrqu->data.length) = '\\0';\n\n\tif (strncmp(extra, \"data,\", 5) == 0) {\n\t\tu8\t*pch;\n\t\tchar\t*ptmp, tmp;\n\t\tu8\tcount = 0;\n\t\tu8\ti = 0;\n\n\t\tptmp = extra;\n\t\tpch = strsep(&ptmp, \",\");\n\n\t\tif ((pch == NULL) || (strlen(pch) == 0)) {\n\t\t\tRTW_INFO(\"%s: parameter error(no cmd)!\\n\", __func__);\n\t\t\treturn -EFAULT;\n\t\t}\n\n\t\tdo {\n\t\t\tpch = strsep(&ptmp, \":\");\n\t\t\tif ((pch == NULL) || (strlen(pch) == 0))\n\t\t\t\tbreak;\n\t\t\tif (strlen(pch) != 2\n\t\t\t\t|| IsHexDigit(*pch) == _FALSE\n\t\t\t\t|| IsHexDigit(*(pch + 1)) == _FALSE\n\t\t\t\t|| sscanf(pch, \"%hhx\", &tmp) != 1\n\t\t\t) {\n\t\t\t\tRTW_INFO(\"%s: invalid 8-bit hex! input format: data,01:23:45:67:89:ab:cd:ef...\\n\", __func__);\n\t\t\t\treturn -EFAULT;\n\t\t\t}\n\t\t\tbtmaskfileBuffer[count++] = tmp;\n\n\t\t } while (count < 64);\n\n\t\tfor (i = 0; i < count; i++)\n\t\t\tsprintf(extra, \"%s:%02x\", extra, btmaskfileBuffer[i]);\n\n\t\tpadapter->registrypriv.bBTFileMaskEfuse = _TRUE;\n\n\t\tsprintf(extra, \"%s\\nLoad BT Efuse Mask data %d hex ok\\n\", extra, count);\n\t\twrqu->data.length = strlen(extra);\n\t\treturn 0;\n\t}\n\trtw_efuse_mask_file_path = extra;\n\n\tif (rtw_is_file_readable(rtw_efuse_mask_file_path) == _TRUE) {\n\t\tRTW_INFO(\"%s do rtw_is_file_readable = %s! ,sizeof BT maskfileBuffer %zu\\n\", __func__, rtw_efuse_mask_file_path, sizeof(btmaskfileBuffer));\n\t\tStatus = rtw_efuse_file_read(padapter, rtw_efuse_mask_file_path, btmaskfileBuffer, sizeof(btmaskfileBuffer));\n\t\tif (Status == _TRUE) {\n\t\t\tpadapter->registrypriv.bBTFileMaskEfuse = _TRUE;\n\t\t\tsprintf(extra, \"BT efuse mask file read OK\\n\");\n\t\t} else {\n\t\t\tpadapter->registrypriv.bBTFileMaskEfuse = _FALSE;\n\t\t\tsprintf(extra, \"read BT efuse mask file FAIL\\n\");\n\t\t\tRTW_INFO(\"%s rtw_efuse_file_read BT mask fail!\\n\", __func__);\n\t\t}\n\t} else {\n\t\tpadapter->registrypriv.bBTFileMaskEfuse = _FALSE;\n\t\tsprintf(extra, \"BT efuse mask file readable FAIL\\n\");\n\t\tRTW_INFO(\"%s rtw_is_file_readable BT Mask file fail!\\n\", __func__);\n\t}\n\twrqu->data.length = strlen(extra);\n\treturn 0;\n}\n\n\nint rtw_efuse_mask_file(struct net_device *dev,\n\t\t\tstruct iw_request_info *info,\n\t\t\tunion iwreq_data *wrqu, char *extra)\n{\n\tchar *rtw_efuse_mask_file_path;\n\tu8 Status;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\n\t_rtw_memset(maskfileBuffer, 0x00, sizeof(maskfileBuffer));\n\n\tif (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))\n\t\treturn -EFAULT;\n\n\t*(extra + wrqu->data.length) = '\\0';\n\tif (strncmp(extra, \"off\", 3) == 0 && strlen(extra) < 4) {\n\t\tpadapter->registrypriv.boffefusemask = 1;\n\t\tsprintf(extra, \"Turn off Efuse Mask\\n\");\n\t\twrqu->data.length = strlen(extra);\n\t\treturn 0;\n\t}\n\tif (strncmp(extra, \"on\", 2) == 0 && strlen(extra) < 3) {\n\t\tpadapter->registrypriv.boffefusemask = 0;\n\t\tsprintf(extra, \"Turn on Efuse Mask\\n\");\n\t\twrqu->data.length = strlen(extra);\n\t\treturn 0;\n\t}\n\tif (strncmp(extra, \"data,\", 5) == 0) {\n\t\tu8\t*pch;\n\t\tchar\t*ptmp, tmp;\n\t\tu8\tcount = 0;\n\t\tu8\ti = 0;\n\n\t\tptmp = extra;\n\t\tpch = strsep(&ptmp, \",\");\n\n\t\tif ((pch == NULL) || (strlen(pch) == 0)) {\n\t\t\tRTW_INFO(\"%s: parameter error(no cmd)!\\n\", __func__);\n\t\t\treturn -EFAULT;\n\t\t}\n\n\t\tdo {\n\t\t\tpch = strsep(&ptmp, \":\");\n\t\t\tif ((pch == NULL) || (strlen(pch) == 0))\n\t\t\t\tbreak;\n\t\t\tif (strlen(pch) != 2\n\t\t\t\t|| IsHexDigit(*pch) == _FALSE\n\t\t\t\t|| IsHexDigit(*(pch + 1)) == _FALSE\n\t\t\t\t|| sscanf(pch, \"%hhx\", &tmp) != 1\n\t\t\t) {\n\t\t\t\tRTW_INFO(\"%s: invalid 8-bit hex! input format: data,01:23:45:67:89:ab:cd:ef...\\n\", __func__);\n\t\t\t\treturn -EFAULT;\n\t\t\t}\n\t\t\tmaskfileBuffer[count++] = tmp;\n\n\t\t } while (count < 64);\n\n\t\tfor (i = 0; i < count; i++)\n\t\t\tsprintf(extra, \"%s:%02x\", extra, maskfileBuffer[i]);\n\n\t\tpadapter->registrypriv.bFileMaskEfuse = _TRUE;\n\n\t\tsprintf(extra, \"%s\\nLoad Efuse Mask data %d hex ok\\n\", extra, count);\n\t\twrqu->data.length = strlen(extra);\n\t\treturn 0;\n\t}\n\trtw_efuse_mask_file_path = extra;\n\n\tif (rtw_is_file_readable(rtw_efuse_mask_file_path) == _TRUE) {\n\t\tRTW_INFO(\"%s do rtw_efuse_mask_file_read = %s! ,sizeof maskfileBuffer %zu\\n\", __func__, rtw_efuse_mask_file_path, sizeof(maskfileBuffer));\n\t\tStatus = rtw_efuse_file_read(padapter, rtw_efuse_mask_file_path, maskfileBuffer, sizeof(maskfileBuffer));\n\t\tif (Status == _TRUE) {\n\t\t\tpadapter->registrypriv.bFileMaskEfuse = _TRUE;\n\t\t\tsprintf(extra, \"efuse mask file read OK\\n\");\n\t\t} else {\n\t\t\tpadapter->registrypriv.bFileMaskEfuse = _FALSE;\n\t\t\tsprintf(extra, \"read efuse mask file FAIL\\n\");\n\t\t\tRTW_INFO(\"%s rtw_efuse_file_read mask fail!\\n\", __func__);\n\t\t}\n\t} else {\n\t\tpadapter->registrypriv.bFileMaskEfuse = _FALSE;\n\t\tsprintf(extra, \"efuse mask file readable FAIL\\n\");\n\t\tRTW_INFO(\"%s rtw_is_file_readable fail!\\n\", __func__);\n\t}\n\twrqu->data.length = strlen(extra);\n\treturn 0;\n}\n\n\nint rtw_efuse_file_map(struct net_device *dev,\n\t\t       struct iw_request_info *info,\n\t\t       union iwreq_data *wrqu, char *extra)\n{\n\tchar *rtw_efuse_file_map_path;\n\tu8 Status;\n\tPEFUSE_HAL pEfuseHal;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\n\tpEfuseHal = &pHalData->EfuseHal;\n\tif (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))\n\t\treturn -EFAULT;\n\n\trtw_efuse_file_map_path = extra;\n\n\t_rtw_memset(pEfuseHal->fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);\n\n\tif (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) {\n\t\tRTW_INFO(\"%s do rtw_efuse_mask_file_read = %s!\\n\", __func__, rtw_efuse_file_map_path);\n\t\tStatus = rtw_efuse_file_read(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeEfuseModifiedMap, sizeof(pEfuseHal->fakeEfuseModifiedMap));\n\t\tif (Status == _TRUE) {\n\t\t\tpmp_priv->bloadefusemap = _TRUE;\n\t\t\tsprintf(extra, \"efuse file file_read OK\\n\");\n\t\t} else {\n\t\t\tpmp_priv->bloadefusemap = _FALSE;\n\t\t\tsprintf(extra, \"efuse file file_read FAIL\\n\");\n\t\t}\n\t} else {\n\t\tsprintf(extra, \"efuse file readable FAIL\\n\");\n\t\tRTW_INFO(\"%s rtw_is_file_readable fail!\\n\", __func__);\n\t}\n\twrqu->data.length = strlen(extra);\n\treturn 0;\n}\n\nint rtw_bt_efuse_file_map(struct net_device *dev,\n\t\t\t\tstruct iw_request_info *info,\n\t\t\t\tunion iwreq_data *wrqu, char *extra)\n{\n\tchar *rtw_efuse_file_map_path;\n\tu8 Status;\n\tPEFUSE_HAL pEfuseHal;\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct mp_priv *pmp_priv = &padapter->mppriv;\n\n\tpEfuseHal = &pHalData->EfuseHal;\n\tif (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))\n\t\treturn -EFAULT;\n\n\trtw_efuse_file_map_path = extra;\n\n\t_rtw_memset(pEfuseHal->fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);\n\n\tif (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) {\n\t\tRTW_INFO(\"%s do rtw_efuse_mask_file_read = %s!\\n\", __func__, rtw_efuse_file_map_path);\n\t\tStatus = rtw_efuse_file_read(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeBTEfuseModifiedMap, sizeof(pEfuseHal->fakeBTEfuseModifiedMap));\n\t\tif (Status == _TRUE) {\n\t\t\tpmp_priv->bloadBTefusemap = _TRUE;\n\t\t\tsprintf(extra, \"BT efuse file file_read OK\\n\");\n\t\t} else {\n\t\t\tpmp_priv->bloadBTefusemap = _FALSE;\n\t\t\tsprintf(extra, \"BT efuse file file_read FAIL\\n\");\n\t\t}\n\t} else {\n\t\tsprintf(extra, \"BT efuse file readable FAIL\\n\");\n\t\tRTW_INFO(\"%s rtw_is_file_readable fail!\\n\", __func__);\n\t}\n\twrqu->data.length = strlen(extra);\n\treturn 0;\n}\n\n\nstatic inline void dump_buf(u8 *buf, u32 len)\n{\n\tu32 i;\n\n\tRTW_INFO(\"-----------------Len %d----------------\\n\", len);\n\tfor (i = 0; i < len; i++)\n\t\tRTW_INFO(\"%2.2x-\", *(buf + i));\n\tRTW_INFO(\"\\n\");\n}\n\nint rtw_mp_link(struct net_device *dev,\n\t\t\tstruct iw_request_info *info,\n\t\t\tstruct iw_point *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tstruct mp_priv *pmp_priv;\n\tchar\tinput[wrqu->length];\n\tint\t\tbgetrxdata = 0, btxdata = 0, bsetbt = 0;\n\tu8 err = 0 , num;\n\tu32 i = 0, datalen = 0, j = 0, jj, kk, waittime = 0, n = 0, btdata;\n\tu16 addr = 0xff, cnts = 0, bttypen = 0, val = 0x00, ret = 0;\n\tchar *pextra = NULL;\n\tu8 *setdata = NULL;\n\tchar *pch, *ptmp, *token, *tmp[4] = {0x00, 0x00, 0x00};\n\n\tpmp_priv = &padapter->mppriv;\n\n\tif (copy_from_user(input, wrqu->pointer, wrqu->length))\n\t\treturn -EFAULT;\n\n\t_rtw_memset(extra, 0, wrqu->length);\n\n\tRTW_INFO(\"%s: in=%s\\n\", __func__, input);\n\n\tbgetrxdata =  (strncmp(input, \"rxdata\", 6) == 0) ? 1 : 0; /* strncmp TRUE is 0*/\n\tbtxdata =  (strncmp(input, \"txdata\", 6) == 0) ? 1 : 0; /* strncmp TRUE is 0*/\n\tbsetbt =  (strncmp(input, \"setbt\", 5) == 0) ? 1 : 0; /* strncmp TRUE is 0*/\n\n\tif (bgetrxdata) {\n\t\tRTW_INFO(\"%s: in= 1 \\n\", __func__);\n\t\tif (pmp_priv->mplink_brx == _TRUE) {\n\n\t\t\t\twhile (waittime < 100 && pmp_priv->mplink_brx == _FALSE) {\n\t\t\t\t\t\tif (pmp_priv->mplink_brx == _FALSE)\n\t\t\t\t\t\t\trtw_msleep_os(10);\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\twaittime++;\n\t\t\t\t}\n\t\t\t\tif (pmp_priv->mplink_brx == _TRUE) {\n\t\t\t\t\tsprintf(extra, \"\\n\");\n\t\t\t\t\tpextra = extra + strlen(extra);\n\t\t\t\t\tfor (i = 0; i < pmp_priv->mplink_rx_len; i ++) {\n\t\t\t\t\t\tpextra += sprintf(pextra, \"%02x:\", pmp_priv->mplink_buf[i]);\n\t\t\t\t\t}\n\t\t\t\t\t_rtw_memset(pmp_priv->mplink_buf, '\\0' , sizeof(pmp_priv->mplink_buf));\n\t\t\t\t\tpmp_priv->mplink_brx = _FALSE;\n\t\t\t\t}\n\t\t}\n\t} else if (btxdata) {\n\t\tstruct pkt_attrib *pattrib;\n\n\t\tpch = input;\n\t\tsetdata = rtw_zmalloc(1024);\n\t\tif (setdata == NULL) {\n\t\t\terr = -ENOMEM;\n\t\t\tgoto exit;\n\t\t}\n\n\t\ti = 0;\n\t\twhile ((token = strsep(&pch, \",\")) != NULL) {\n\t\t\tif (i > 2)\n\t\t\t\tbreak;\n\t\t\ttmp[i] = token;\n\t\t\ti++;\n\t\t}\n\n\t\t/* tmp[0],[1],[2] */\n\t\t/* txdata,00e04c871200........... */\n\t\tif (strcmp(tmp[0], \"txdata\") == 0) {\n\t\t\tif ((tmp[1] == NULL)) {\n\t\t\t\terr = -EINVAL;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\n\t\tdatalen = strlen(tmp[1]);\n\t\tif (datalen % 2) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t\tdatalen /= 2;\n\t\tif (datalen == 0) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tRTW_INFO(\"%s: data len=%d\\n\", __FUNCTION__, datalen);\n\t\tRTW_INFO(\"%s: tx data=%s\\n\", __FUNCTION__, tmp[1]);\n\n\t\tfor (jj = 0, kk = 0; jj < datalen; jj++, kk += 2)\n\t\t\tsetdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);\n\n\t\tdump_buf(setdata, datalen);\n\t\t_rtw_memset(pmp_priv->mplink_buf, '\\0' , sizeof(pmp_priv->mplink_buf));\n\t\t_rtw_memcpy(pmp_priv->mplink_buf, setdata, datalen);\n\n\t\tpattrib = &pmp_priv->tx.attrib;\n\t\tpattrib->pktlen = datalen;\n\t\tpmp_priv->tx.count = 1;\n\t\tpmp_priv->tx.stop = 0;\n\t\tpmp_priv->mplink_btx = _TRUE;\n\t\tSetPacketTx(padapter);\n\t\tpmp_priv->mode = MP_PACKET_TX;\n\n\t} else if (bsetbt) {\n\n#ifdef CONFIG_BT_COEXIST\n\t\tpch = input;\n\t\ti = 0;\n\n\t\twhile ((token = strsep(&pch, \",\")) != NULL) {\n\t\t\tif (i > 3)\n\t\t\t\tbreak;\n\t\t\ttmp[i] = token;\n\t\t\ti++;\n\t\t}\n\n\t\tif (tmp[1] == NULL) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (strcmp(tmp[1], \"scbd\") == 0) {\n\t\t\tu16 org_val = 0x8002, pre_val, read_score_board_val;\n\t\t\tu8 state;\n\n\t\t\tpre_val = (rtw_read16(padapter,(0xaa))) & 0x7fff;\n\n\t\t\tif (tmp[2] != NULL) {\n\t\t\t\tstate = simple_strtoul(tmp[2], &ptmp, 10);\n\n\t\t\t\tif (state)\n\t\t\t\t\t\torg_val = org_val | BIT6;\n\t\t\t\telse\n\t\t\t\t\t\torg_val = org_val & (~BIT6);\n\n\t\t\t\tif (org_val != pre_val) {\n\t\t\t\t\tpre_val = org_val;\n\t\t\t\t\trtw_write16(padapter, 0xaa, org_val);\n\t\t\t\t\tRTW_INFO(\"%s,setbt scbd write org_val = 0x%x , pre_val = 0x%x\\n\", __func__, org_val, pre_val);\n\t\t\t\t} else {\n\t\t\t\t\tRTW_INFO(\"%s,setbt scbd org_val = 0x%x ,pre_val = 0x%x\\n\", __func__, org_val, pre_val);\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\t\tread_score_board_val = (rtw_read16(padapter,(0xaa))) & 0x7fff;\n\t\t\t\t\tRTW_INFO(\"%s,read_score_board_val = 0x%x\\n\", __func__, read_score_board_val);\n\t\t\t}\n\t\t\tgoto exit;\n\n\t\t} else if (strcmp(tmp[1], \"testmode\") == 0) {\n\n\t\t\tif (tmp[2] == NULL) {\n\t\t\t\terr = -EINVAL;\n\t\t\t\tgoto exit;\n\t\t\t}\n\n\t\t\tval = simple_strtoul(tmp[2], &ptmp, 16);\n\t\t\tRTW_INFO(\"get tmp, type  %s, val =0x%x!\\n\", tmp[1], val);\n\n\t\t\tif (tmp[2] != NULL) {\n\t\t\t\t_rtw_memset(extra, 0, wrqu->length);\n\t\t\t\tret = rtw_btcoex_btset_testmode(padapter, val);\n\t\t\t\tif (!CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS)) {\n\t\t\t\t\tRTW_INFO(\"%s: BT_OP fail = 0x%x!\\n\", __FUNCTION__, val);\n\t\t\t\t\tsprintf(extra, \"BT_OP fail  0x%x!\\n\", val);\n\t\t\t\t} else\n\t\t\t\t\tsprintf(extra, \"Set BT_OP 0x%x done!\\n\", val);\n\t\t\t}\n\n\t\t}\n#endif /* CONFIG_BT_COEXIST */\n\t}\n\nexit:\n\tif (setdata)\n\t\trtw_mfree(setdata, 1024);\n\n\twrqu->length = strlen(extra);\n\treturn err;\n\n}\n\n#if defined(CONFIG_RTL8723B)\nint rtw_mp_SetBT(struct net_device *dev,\n\t\t struct iw_request_info *info,\n\t\t union iwreq_data *wrqu, char *extra)\n{\n\tPADAPTER padapter = rtw_netdev_priv(dev);\n\tstruct hal_ops *pHalFunc = &padapter->hal_func;\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n\tBT_REQ_CMD\tBtReq;\n\tPMPT_CONTEXT\tpMptCtx = &(padapter->mppriv.mpt_ctx);\n\tPBT_RSP_CMD\tpBtRsp = (PBT_RSP_CMD)&pMptCtx->mptOutBuf[0];\n\tchar\tinput[128];\n\tchar *pch, *ptmp, *token, *tmp[2] = {0x00, 0x00};\n\tu8 setdata[100];\n\tu8 resetbt = 0x00;\n\tu8 tempval, BTStatus;\n\tu8 H2cSetbtmac[6];\n\tu8 u1H2CBtMpOperParm[4] = {0x01};\n\tint testmode = 1, ready = 1, trxparam = 1, setgen = 1, getgen = 1, testctrl = 1, testbt = 1, readtherm = 1, setbtmac = 1;\n\tu32 i = 0, ii = 0, jj = 0, kk = 0, cnts = 0, status = 0;\n\tPRT_MP_FIRMWARE pBTFirmware = NULL;\n\n\tif (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))\n\t\treturn -EFAULT;\n\n\t*(extra + wrqu->data.length) = '\\0';\n\n\tif (strlen(extra) < 1)\n\t\treturn -EFAULT;\n\n\tRTW_INFO(\"%s:iwpriv in=%s\\n\", __func__, extra);\n\tready = strncmp(extra, \"ready\", 5);\n\ttestmode = strncmp(extra, \"testmode\", 8); /* strncmp TRUE is 0*/\n\ttrxparam = strncmp(extra, \"trxparam\", 8);\n\tsetgen = strncmp(extra, \"setgen\", 6);\n\tgetgen = strncmp(extra, \"getgen\", 6);\n\ttestctrl = strncmp(extra, \"testctrl\", 8);\n\ttestbt = strncmp(extra, \"testbt\", 6);\n\treadtherm = strncmp(extra, \"readtherm\", 9);\n\tsetbtmac = strncmp(extra, \"setbtmac\", 8);\n\n\tif (strncmp(extra, \"dlbt\", 4) == 0) {\n\t\tpHalData->LastHMEBoxNum = 0;\n\t\tpHalData->bBTFWReady = _FALSE;\n\t\trtw_write8(padapter, 0xa3, 0x05);\n\t\tBTStatus = rtw_read8(padapter, 0xa0);\n\t\tRTW_INFO(\"%s: btwmap before read 0xa0 BT Status =0x%x\\n\", __func__, BTStatus);\n\t\tif (BTStatus != 0x04) {\n\t\t\tsprintf(extra, \"BT Status not Active DLFW FAIL\\n\");\n\t\t\tgoto exit;\n\t\t}\n\n\t\ttempval = rtw_read8(padapter, 0x6B);\n\t\ttempval |= BIT7;\n\t\trtw_write8(padapter, 0x6B, tempval);\n\n\t\t/* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay*/\n\t\t/* So don't write 0x6A[14]=1 and 0x6A[15]=0 together!*/\n\t\trtw_usleep_os(100);\n\t\t/* disable BT power cut*/\n\t\t/* 0x6A[14] = 0*/\n\t\ttempval = rtw_read8(padapter, 0x6B);\n\t\ttempval &= ~BIT6;\n\t\trtw_write8(padapter, 0x6B, tempval);\n\t\trtw_usleep_os(100);\n\t\tMPT_PwrCtlDM(padapter, 0);\n\t\trtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004));\n\t\trtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF));\n\t\trtw_msleep_os(600);\n\t\trtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010));\n\t\trtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB));\n\t\trtw_msleep_os(1200);\n\t\tpBTFirmware = (PRT_MP_FIRMWARE)rtw_zmalloc(sizeof(RT_MP_FIRMWARE));\n\t\tif (pBTFirmware == NULL)\n\t\t\tgoto exit;\n\t\tpHalData->bBTFWReady = _FALSE;\n\t\tFirmwareDownloadBT(padapter, pBTFirmware);\n\t\tif (pBTFirmware)\n\t\t\trtw_mfree((u8 *)pBTFirmware, sizeof(RT_MP_FIRMWARE));\n\n\t\tRTW_INFO(\"Wait for FirmwareDownloadBT fw boot!\\n\");\n\t\trtw_msleep_os(2000);\n\t\t_rtw_memset(extra, '\\0', wrqu->data.length);\n\t\tBtReq.opCodeVer = 1;\n\t\tBtReq.OpCode = 0;\n\t\tBtReq.paraLength = 0;\n\t\tmptbt_BtControlProcess(padapter, &BtReq);\n\t\trtw_msleep_os(100);\n\n\t\tRTW_INFO(\"FirmwareDownloadBT ready = 0x%x 0x%x\", pMptCtx->mptOutBuf[4], pMptCtx->mptOutBuf[5]);\n\t\tif ((pMptCtx->mptOutBuf[4] == 0x00) && (pMptCtx->mptOutBuf[5] == 0x00)) {\n\n\t\t\tif (padapter->mppriv.bTxBufCkFail == _TRUE)\n\t\t\t\tsprintf(extra, \"check TxBuf Fail.\\n\");\n\t\t\telse\n\t\t\t\tsprintf(extra, \"download FW Fail.\\n\");\n\t\t} else {\n\t\t\tsprintf(extra, \"download FW OK.\\n\");\n\t\t\tgoto exit;\n\t\t}\n\t\tgoto exit;\n\t}\n\tif (strncmp(extra, \"dlfw\", 4) == 0) {\n\t\tpHalData->LastHMEBoxNum = 0;\n\t\tpHalData->bBTFWReady = _FALSE;\n\t\trtw_write8(padapter, 0xa3, 0x05);\n\t\tBTStatus = rtw_read8(padapter, 0xa0);\n\t\tRTW_INFO(\"%s: btwmap before read 0xa0 BT Status =0x%x\\n\", __func__, BTStatus);\n\t\tif (BTStatus != 0x04) {\n\t\t\tsprintf(extra, \"BT Status not Active DLFW FAIL\\n\");\n\t\t\tgoto exit;\n\t\t}\n\n\t\ttempval = rtw_read8(padapter, 0x6B);\n\t\ttempval |= BIT7;\n\t\trtw_write8(padapter, 0x6B, tempval);\n\n\t\t/* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay*/\n\t\t/* So don't write 0x6A[14]=1 and 0x6A[15]=0 together!*/\n\t\trtw_usleep_os(100);\n\t\t/* disable BT power cut*/\n\t\t/* 0x6A[14] = 0*/\n\t\ttempval = rtw_read8(padapter, 0x6B);\n\t\ttempval &= ~BIT6;\n\t\trtw_write8(padapter, 0x6B, tempval);\n\t\trtw_usleep_os(100);\n\n\t\tMPT_PwrCtlDM(padapter, 0);\n\t\trtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004));\n\t\trtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF));\n\t\trtw_msleep_os(600);\n\t\trtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010));\n\t\trtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB));\n\t\trtw_msleep_os(1200);\n\n#if defined(CONFIG_PLATFORM_SPRD) && (MP_DRIVER == 1)\n\t\t/* Pull up BT reset pin.*/\n\t\tRTW_INFO(\"%s: pull up BT reset pin when bt start mp test\\n\", __func__);\n\t\trtw_wifi_gpio_wlan_ctrl(WLAN_BT_PWDN_ON);\n#endif\n\t\tRTW_INFO(\" FirmwareDownload!\\n\");\n\n#if defined(CONFIG_RTL8723B)\n\t\tstatus = rtl8723b_FirmwareDownload(padapter, _FALSE);\n#endif\n\t\tRTW_INFO(\"Wait for FirmwareDownloadBT fw boot!\\n\");\n\t\trtw_msleep_os(1000);\n#ifdef CONFIG_BT_COEXIST\n\t\trtw_btcoex_HaltNotify(padapter);\n\t\tRTW_INFO(\"SetBT btcoex HaltNotify !\\n\");\n\t\t/*hal_btcoex1ant_SetAntPath(padapter);*/\n\t\trtw_btcoex_SetManualControl(padapter, _TRUE);\n#endif\n\t\t_rtw_memset(extra, '\\0', wrqu->data.length);\n\t\tBtReq.opCodeVer = 1;\n\t\tBtReq.OpCode = 0;\n\t\tBtReq.paraLength = 0;\n\t\tmptbt_BtControlProcess(padapter, &BtReq);\n\t\trtw_msleep_os(200);\n\n\t\tRTW_INFO(\"FirmwareDownloadBT ready = 0x%x 0x%x\", pMptCtx->mptOutBuf[4], pMptCtx->mptOutBuf[5]);\n\t\tif ((pMptCtx->mptOutBuf[4] == 0x00) && (pMptCtx->mptOutBuf[5] == 0x00)) {\n\t\t\tif (padapter->mppriv.bTxBufCkFail == _TRUE)\n\t\t\t\tsprintf(extra, \"check TxBuf Fail.\\n\");\n\t\t\telse\n\t\t\t\tsprintf(extra, \"download FW Fail.\\n\");\n\t\t} else {\n#ifdef CONFIG_BT_COEXIST\n\t\t\trtw_btcoex_SwitchBtTRxMask(padapter);\n#endif\n\t\t\trtw_msleep_os(200);\n\t\t\tsprintf(extra, \"download FW OK.\\n\");\n\t\t\tgoto exit;\n\t\t}\n\t\tgoto exit;\n\t}\n\n\tif (strncmp(extra, \"down\", 4) == 0) {\n\t\tRTW_INFO(\"SetBT down for to hal_init !\\n\");\n#ifdef CONFIG_BT_COEXIST\n\t\trtw_btcoex_SetManualControl(padapter, _FALSE);\n\t\trtw_btcoex_Initialize(padapter);\n#endif\n\t\tpHalFunc->read_adapter_info(padapter);\n\t\tpHalFunc->hal_deinit(padapter);\n\t\tpHalFunc->hal_init(padapter);\n\t\trtw_pm_set_ips(padapter, IPS_NONE);\n\t\tLeaveAllPowerSaveMode(padapter);\n\t\tMPT_PwrCtlDM(padapter, 0);\n\t\trtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004));\n\t\trtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF));\n\t\trtw_msleep_os(600);\n\t\t/*rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a)& 0xFFFFFFFE));*/\n\t\trtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010));\n\t\trtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB));\n\t\trtw_msleep_os(1200);\n\t\tgoto exit;\n\t}\n\tif (strncmp(extra, \"disable\", 7) == 0) {\n\t\tRTW_INFO(\"SetBT disable !\\n\");\n\t\trtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a) & 0xFFFFFFFB));\n\t\trtw_msleep_os(500);\n\t\tgoto exit;\n\t}\n\tif (strncmp(extra, \"enable\", 6) == 0) {\n\t\tRTW_INFO(\"SetBT enable !\\n\");\n\t\trtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a) | 0x00000004));\n\t\trtw_msleep_os(500);\n\t\tgoto exit;\n\t}\n\tif (strncmp(extra, \"h2c\", 3) == 0) {\n\t\tRTW_INFO(\"SetBT h2c !\\n\");\n\t\tpHalData->bBTFWReady = _TRUE;\n\t\trtw_hal_fill_h2c_cmd(padapter, 0x63, 1, u1H2CBtMpOperParm);\n\t\tgoto exit;\n\t}\n\tif (strncmp(extra, \"2ant\", 4) == 0) {\n\t\tRTW_INFO(\"Set BT 2ant use!\\n\");\n\t\tphy_set_mac_reg(padapter, 0x67, BIT5, 0x1);\n\t\trtw_write32(padapter, 0x948, 0000);\n\n\t\tgoto exit;\n\t}\n\n\tif (ready != 0 && testmode != 0 && trxparam != 0 && setgen != 0 && getgen != 0 && testctrl != 0 && testbt != 0 && readtherm != 0 && setbtmac != 0)\n\t\treturn -EFAULT;\n\n\tif (testbt == 0) {\n\t\tBtReq.opCodeVer = 1;\n\t\tBtReq.OpCode = 6;\n\t\tBtReq.paraLength = cnts / 2;\n\t\tgoto todo;\n\t}\n\tif (ready == 0) {\n\t\tBtReq.opCodeVer = 1;\n\t\tBtReq.OpCode = 0;\n\t\tBtReq.paraLength = 0;\n\t\tgoto todo;\n\t}\n\n\tpch = extra;\n\ti = 0;\n\twhile ((token = strsep(&pch, \",\")) != NULL) {\n\t\tif (i > 1)\n\t\t\tbreak;\n\t\ttmp[i] = token;\n\t\ti++;\n\t}\n\n\tif ((tmp[0] != NULL) && (tmp[1] != NULL)) {\n\t\tcnts = strlen(tmp[1]);\n\t\tif (cnts < 1)\n\t\t\treturn -EFAULT;\n\n\t\tRTW_INFO(\"%s: cnts=%d\\n\", __func__, cnts);\n\t\tRTW_INFO(\"%s: data=%s\\n\", __func__, tmp[1]);\n\n\t\tfor (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) {\n\t\t\tBtReq.pParamStart[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);\n\t\t\t/*\t\t\tRTW_INFO(\"BtReq.pParamStart[%d]=0x%02x\\n\", jj, BtReq.pParamStart[jj]);*/\n\t\t}\n\t} else\n\t\treturn -EFAULT;\n\n\tif (testmode == 0) {\n\t\tBtReq.opCodeVer = 1;\n\t\tBtReq.OpCode = 1;\n\t\tBtReq.paraLength = 1;\n\t}\n\tif (trxparam == 0) {\n\t\tBtReq.opCodeVer = 1;\n\t\tBtReq.OpCode = 2;\n\t\tBtReq.paraLength = cnts / 2;\n\t}\n\tif (setgen == 0) {\n\t\tRTW_INFO(\"%s: BT_SET_GENERAL\\n\", __func__);\n\t\tBtReq.opCodeVer = 1;\n\t\tBtReq.OpCode = 3;/*BT_SET_GENERAL\t3*/\n\t\tBtReq.paraLength = cnts / 2;\n\t}\n\tif (getgen == 0) {\n\t\tRTW_INFO(\"%s: BT_GET_GENERAL\\n\", __func__);\n\t\tBtReq.opCodeVer = 1;\n\t\tBtReq.OpCode = 4;/*BT_GET_GENERAL\t4*/\n\t\tBtReq.paraLength = cnts / 2;\n\t}\n\tif (readtherm == 0) {\n\t\tRTW_INFO(\"%s: BT_GET_GENERAL\\n\", __func__);\n\t\tBtReq.opCodeVer = 1;\n\t\tBtReq.OpCode = 4;/*BT_GET_GENERAL\t4*/\n\t\tBtReq.paraLength = cnts / 2;\n\t}\n\n\tif (testctrl == 0) {\n\t\tRTW_INFO(\"%s: BT_TEST_CTRL\\n\", __func__);\n\t\tBtReq.opCodeVer = 1;\n\t\tBtReq.OpCode = 5;/*BT_TEST_CTRL\t5*/\n\t\tBtReq.paraLength = cnts / 2;\n\t}\n\n\tRTW_INFO(\"%s: Req opCodeVer=%d OpCode=%d paraLength=%d\\n\",\n\t\t __func__, BtReq.opCodeVer, BtReq.OpCode, BtReq.paraLength);\n\n\tif (BtReq.paraLength < 1)\n\t\tgoto todo;\n\tfor (i = 0; i < BtReq.paraLength; i++) {\n\t\tRTW_INFO(\"%s: BtReq.pParamStart[%d] = 0x%02x\\n\",\n\t\t\t __func__, i, BtReq.pParamStart[i]);\n\t}\n\ntodo:\n\t_rtw_memset(extra, '\\0', wrqu->data.length);\n\n\tif (pHalData->bBTFWReady == _FALSE) {\n\t\tsprintf(extra, \"BTFWReady = FALSE.\\n\");\n\t\tgoto exit;\n\t}\n\n\tmptbt_BtControlProcess(padapter, &BtReq);\n\n\tif (readtherm == 0) {\n\t\tsprintf(extra, \"BT thermal=\");\n\t\tfor (i = 4; i < pMptCtx->mptOutLen; i++) {\n\t\t\tif ((pMptCtx->mptOutBuf[i] == 0x00) && (pMptCtx->mptOutBuf[i + 1] == 0x00))\n\t\t\t\tgoto exit;\n\n\t\t\tsprintf(extra, \"%s %d \", extra, (pMptCtx->mptOutBuf[i] & 0x1f));\n\t\t}\n\t} else {\n\t\tfor (i = 4; i < pMptCtx->mptOutLen; i++)\n\t\t\tsprintf(extra, \"%s 0x%x \", extra, pMptCtx->mptOutBuf[i]);\n\t}\n\nexit:\n\twrqu->data.length = strlen(extra) + 1;\n\tRTW_INFO(\"-%s: output len=%d data=%s\\n\", __func__, wrqu->data.length, extra);\n\n\treturn status;\n}\n\n#endif /*#ifdef CONFIG_RTL8723B*/\n\n#endif\n"
  },
  {
    "path": "os_dep/linux/mlme_linux.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n\n#define _MLME_OSDEP_C_\n\n#include <drv_types.h>\n\n\n#ifdef RTK_DMP_PLATFORM\nvoid Linkup_workitem_callback(struct work_struct *work)\n{\n\tstruct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkup_workitem);\n\t_adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv);\n\n\n\n#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12))\n\tkobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKUP);\n#else\n\tkobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKUP);\n#endif\n\n}\n\nvoid Linkdown_workitem_callback(struct work_struct *work)\n{\n\tstruct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkdown_workitem);\n\t_adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv);\n\n\n\n#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12))\n\tkobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKDOWN);\n#else\n\tkobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKDOWN);\n#endif\n\n}\n#endif\n\nextern void rtw_indicate_wx_assoc_event(_adapter *padapter);\nextern void rtw_indicate_wx_disassoc_event(_adapter *padapter);\n\nvoid rtw_os_indicate_connect(_adapter *adapter)\n{\n\tstruct mlme_priv *pmlmepriv = &(adapter->mlmepriv);\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||\n\t    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))\n\t\trtw_cfg80211_ibss_indicate_connect(adapter);\n\telse\n\t\trtw_cfg80211_indicate_connect(adapter);\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n\trtw_indicate_wx_assoc_event(adapter);\n\n#ifdef CONFIG_RTW_MESH\n#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER\n\tif (!rtw_mesh_cto_mgate_required(adapter))\n#endif\n#endif\n\t\trtw_netif_carrier_on(adapter->pnetdev);\n\n\tif (adapter->pid[2] != 0)\n\t\trtw_signal_process(adapter->pid[2], SIGALRM);\n\n#ifdef RTK_DMP_PLATFORM\n\t_set_workitem(&adapter->mlmepriv.Linkup_workitem);\n#endif\n\n\n}\n\nextern void indicate_wx_scan_complete_event(_adapter *padapter);\nvoid rtw_os_indicate_scan_done(_adapter *padapter, bool aborted)\n{\n#ifdef CONFIG_IOCTL_CFG80211\n\trtw_cfg80211_indicate_scan_done(padapter, aborted);\n#endif\n\tindicate_wx_scan_complete_event(padapter);\n}\n\nstatic RT_PMKID_LIST   backupPMKIDList[NUM_PMKID_CACHE];\nvoid rtw_reset_securitypriv(_adapter *adapter)\n{\n\tu8\tbackupPMKIDIndex = 0;\n\tu8\tbackupTKIPCountermeasure = 0x00;\n\tu32\tbackupTKIPcountermeasure_time = 0;\n\t/* add for CONFIG_IEEE80211W, none 11w also can use */\n\t_irqL irqL;\n\n\t_enter_critical_bh(&adapter->security_key_mutex, &irqL);\n\n\tif (adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { /* 802.1x */\n\t\t/* Added by Albert 2009/02/18 */\n\t\t/* We have to backup the PMK information for WiFi PMK Caching test item. */\n\t\t/*  */\n\t\t/* Backup the btkip_countermeasure information. */\n\t\t/* When the countermeasure is trigger, the driver have to disconnect with AP for 60 seconds. */\n\n\t\t_rtw_memset(&backupPMKIDList[0], 0x00, sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);\n\n\t\t_rtw_memcpy(&backupPMKIDList[0], &adapter->securitypriv.PMKIDList[0], sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);\n\t\tbackupPMKIDIndex = adapter->securitypriv.PMKIDIndex;\n\t\tbackupTKIPCountermeasure = adapter->securitypriv.btkip_countermeasure;\n\t\tbackupTKIPcountermeasure_time = adapter->securitypriv.btkip_countermeasure_time;\n\t\t_rtw_memset((unsigned char *)&adapter->securitypriv, 0, sizeof(struct security_priv));\n\n\t\t/* Added by Albert 2009/02/18 */\n\t\t/* Restore the PMK information to securitypriv structure for the following connection. */\n\t\t_rtw_memcpy(&adapter->securitypriv.PMKIDList[0], &backupPMKIDList[0], sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);\n\t\tadapter->securitypriv.PMKIDIndex = backupPMKIDIndex;\n\t\tadapter->securitypriv.btkip_countermeasure = backupTKIPCountermeasure;\n\t\tadapter->securitypriv.btkip_countermeasure_time = backupTKIPcountermeasure_time;\n\n\t\tadapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;\n\t\tadapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled;\n\n\t\tadapter->securitypriv.extauth_status = WLAN_STATUS_UNSPECIFIED_FAILURE;\n\n\t} else { /* reset values in securitypriv */\n\t\t/* if(adapter->mlmepriv.fw_state & WIFI_STATION_STATE) */\n\t\t/* { */\n\t\tstruct security_priv *psec_priv = &adapter->securitypriv;\n\n\t\tpsec_priv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */\n\t\tpsec_priv->dot11PrivacyAlgrthm = _NO_PRIVACY_;\n\t\tpsec_priv->dot11PrivacyKeyIndex = 0;\n\n\t\tpsec_priv->dot118021XGrpPrivacy = _NO_PRIVACY_;\n\t\tpsec_priv->dot118021XGrpKeyid = 1;\n\n\t\tpsec_priv->ndisauthtype = Ndis802_11AuthModeOpen;\n\t\tpsec_priv->ndisencryptstatus = Ndis802_11WEPDisabled;\n\t\t/* } */\n\n\t\tpsec_priv->extauth_status = WLAN_STATUS_UNSPECIFIED_FAILURE;\n\t}\n\t/* add for CONFIG_IEEE80211W, none 11w also can use */\n\t_exit_critical_bh(&adapter->security_key_mutex, &irqL);\n\n\tRTW_INFO(FUNC_ADPT_FMT\" - End to Disconnect\\n\", FUNC_ADPT_ARG(adapter));\n}\n\nvoid rtw_os_indicate_disconnect(_adapter *adapter,  u16 reason, u8 locally_generated)\n{\n\t/* RT_PMKID_LIST   backupPMKIDList[NUM_PMKID_CACHE]; */\n\n\n\trtw_netif_carrier_off(adapter->pnetdev); /* Do it first for tx broadcast pkt after disconnection issue! */\n\n#ifdef CONFIG_IOCTL_CFG80211\n\trtw_cfg80211_indicate_disconnect(adapter,  reason, locally_generated);\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n\trtw_indicate_wx_disassoc_event(adapter);\n\n#ifdef RTK_DMP_PLATFORM\n\t_set_workitem(&adapter->mlmepriv.Linkdown_workitem);\n#endif\n\t/* modify for CONFIG_IEEE80211W, none 11w also can use the same command */\n\trtw_reset_securitypriv_cmd(adapter);\n\n\n}\n\nvoid rtw_report_sec_ie(_adapter *adapter, u8 authmode, u8 *sec_ie)\n{\n\tuint\tlen;\n\tu8\t*buff, *p, i;\n\tunion iwreq_data wrqu;\n\n\n\n\tbuff = NULL;\n\tif (authmode == _WPA_IE_ID_) {\n\n\t\tbuff = rtw_zmalloc(IW_CUSTOM_MAX);\n\t\tif (NULL == buff) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": alloc memory FAIL!!\\n\",\n\t\t\t\t FUNC_ADPT_ARG(adapter));\n\t\t\treturn;\n\t\t}\n\t\tp = buff;\n\n\t\tp += sprintf(p, \"ASSOCINFO(ReqIEs=\");\n\n\t\tlen = sec_ie[1] + 2;\n\t\tlen = (len < IW_CUSTOM_MAX) ? len : IW_CUSTOM_MAX;\n\n\t\tfor (i = 0; i < len; i++)\n\t\t\tp += sprintf(p, \"%02x\", sec_ie[i]);\n\n\t\tp += sprintf(p, \")\");\n\n\t\t_rtw_memset(&wrqu, 0, sizeof(wrqu));\n\n\t\twrqu.data.length = p - buff;\n\n\t\twrqu.data.length = (wrqu.data.length < IW_CUSTOM_MAX) ? wrqu.data.length : IW_CUSTOM_MAX;\n\n#ifndef CONFIG_IOCTL_CFG80211\n\t\twireless_send_event(adapter->pnetdev, IWEVCUSTOM, &wrqu, buff);\n#endif\n\n\t\trtw_mfree(buff, IW_CUSTOM_MAX);\n\t}\n\n\n}\n\n#ifdef CONFIG_AP_MODE\n\nvoid rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta)\n{\n\tunion iwreq_data wrqu;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\tif (psta == NULL)\n\t\treturn;\n\n\tif (psta->cmn.aid > pstapriv->max_aid)\n\t\treturn;\n\n\tif (pstapriv->sta_aid[psta->cmn.aid - 1] != psta)\n\t\treturn;\n\n\n\twrqu.addr.sa_family = ARPHRD_ETHER;\n\n\t_rtw_memcpy(wrqu.addr.sa_data, psta->cmn.mac_addr, ETH_ALEN);\n\n\tRTW_INFO(\"+rtw_indicate_sta_assoc_event\\n\");\n\n#ifndef CONFIG_IOCTL_CFG80211\n\twireless_send_event(padapter->pnetdev, IWEVREGISTERED, &wrqu, NULL);\n#endif\n\n}\n\nvoid rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta)\n{\n\tunion iwreq_data wrqu;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\n\tif (psta == NULL)\n\t\treturn;\n\n\tif (psta->cmn.aid > pstapriv->max_aid)\n\t\treturn;\n\n\tif (pstapriv->sta_aid[psta->cmn.aid - 1] != psta)\n\t\treturn;\n\n\n\twrqu.addr.sa_family = ARPHRD_ETHER;\n\n\t_rtw_memcpy(wrqu.addr.sa_data, psta->cmn.mac_addr, ETH_ALEN);\n\n\tRTW_INFO(\"+rtw_indicate_sta_disassoc_event\\n\");\n\n#ifndef CONFIG_IOCTL_CFG80211\n\twireless_send_event(padapter->pnetdev, IWEVEXPIRED, &wrqu, NULL);\n#endif\n\n}\n\n\n#ifdef CONFIG_HOSTAPD_MLME\n\nstatic int mgnt_xmit_entry(struct sk_buff *skb, struct net_device *pnetdev)\n{\n\tstruct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev);\n\t_adapter *padapter = (_adapter *)phostapdpriv->padapter;\n\n\t/* RTW_INFO(\"%s\\n\", __FUNCTION__); */\n\n\treturn rtw_hal_hostap_mgnt_xmit_entry(padapter, skb);\n}\n\nstatic int mgnt_netdev_open(struct net_device *pnetdev)\n{\n\tstruct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev);\n\n\tRTW_INFO(\"mgnt_netdev_open: MAC Address:\" MAC_FMT \"\\n\", MAC_ARG(pnetdev->dev_addr));\n\n\n\tinit_usb_anchor(&phostapdpriv->anchored);\n\n\trtw_netif_wake_queue(pnetdev);\n\n\trtw_netif_carrier_on(pnetdev);\n\n\t/* rtw_write16(phostapdpriv->padapter, 0x0116, 0x0100); */ /* only excluding beacon */\n\n\treturn 0;\n}\nstatic int mgnt_netdev_close(struct net_device *pnetdev)\n{\n\tstruct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev);\n\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\n\tusb_kill_anchored_urbs(&phostapdpriv->anchored);\n\n\trtw_netif_carrier_off(pnetdev);\n\n\trtw_netif_stop_queue(pnetdev);\n\n\t/* rtw_write16(phostapdpriv->padapter, 0x0116, 0x3f3f); */\n\n\treturn 0;\n}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))\nstatic const struct net_device_ops rtl871x_mgnt_netdev_ops = {\n\t.ndo_open = mgnt_netdev_open,\n\t.ndo_stop = mgnt_netdev_close,\n\t.ndo_start_xmit = mgnt_xmit_entry,\n\t#if 0\n\t.ndo_set_mac_address = r871x_net_set_mac_address,\n\t.ndo_get_stats = r871x_net_get_stats,\n\t.ndo_do_ioctl = r871x_mp_ioctl,\n\t#endif\n};\n#endif\n\nint hostapd_mode_init(_adapter *padapter)\n{\n\tunsigned char mac[ETH_ALEN];\n\tstruct hostapd_priv *phostapdpriv;\n\tstruct net_device *pnetdev;\n\n\tpnetdev = rtw_alloc_etherdev(sizeof(struct hostapd_priv));\n\tif (!pnetdev)\n\t\treturn -ENOMEM;\n\n\t/* SET_MODULE_OWNER(pnetdev); */\n\tether_setup(pnetdev);\n\n\t/* pnetdev->type = ARPHRD_IEEE80211; */\n\n\tphostapdpriv = rtw_netdev_priv(pnetdev);\n\tphostapdpriv->pmgnt_netdev = pnetdev;\n\tphostapdpriv->padapter = padapter;\n\tpadapter->phostapdpriv = phostapdpriv;\n\n\t/* pnetdev->init = NULL; */\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))\n\n\tRTW_INFO(\"register rtl871x_mgnt_netdev_ops to netdev_ops\\n\");\n\n\tpnetdev->netdev_ops = &rtl871x_mgnt_netdev_ops;\n\n#else\n\n\tpnetdev->open = mgnt_netdev_open;\n\n\tpnetdev->stop = mgnt_netdev_close;\n\n\tpnetdev->hard_start_xmit = mgnt_xmit_entry;\n\n\t/* pnetdev->set_mac_address = r871x_net_set_mac_address; */\n\n\t/* pnetdev->get_stats = r871x_net_get_stats; */\n\n\t/* pnetdev->do_ioctl = r871x_mp_ioctl; */\n\n#endif\n\n\tpnetdev->watchdog_timeo = HZ; /* 1 second timeout */\n\n\t/* pnetdev->wireless_handlers = NULL; */\n\n\n\n\n\tif (dev_alloc_name(pnetdev, \"mgnt.wlan%d\") < 0)\n\t\tRTW_INFO(\"hostapd_mode_init(): dev_alloc_name, fail!\\n\");\n\n\n\t/* SET_NETDEV_DEV(pnetdev, pintfpriv->udev); */\n\n\n\tmac[0] = 0x00;\n\tmac[1] = 0xe0;\n\tmac[2] = 0x4c;\n\tmac[3] = 0x87;\n\tmac[4] = 0x11;\n\tmac[5] = 0x12;\n\n\t_rtw_memcpy(pnetdev->dev_addr, mac, ETH_ALEN);\n\n\n\trtw_netif_carrier_off(pnetdev);\n\n\n\t/* Tell the network stack we exist */\n\tif (register_netdev(pnetdev) != 0) {\n\t\tRTW_INFO(\"hostapd_mode_init(): register_netdev fail!\\n\");\n\n\t\tif (pnetdev)\n\t\t\trtw_free_netdev(pnetdev);\n\t}\n\n\treturn 0;\n\n}\n\nvoid hostapd_mode_unload(_adapter *padapter)\n{\n\tstruct hostapd_priv *phostapdpriv = padapter->phostapdpriv;\n\tstruct net_device *pnetdev = phostapdpriv->pmgnt_netdev;\n\n\tunregister_netdev(pnetdev);\n\trtw_free_netdev(pnetdev);\n\n}\n\n#endif\n#endif\n"
  },
  {
    "path": "os_dep/linux/os_intfs.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _OS_INTFS_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\nMODULE_LICENSE(\"GPL\");\nMODULE_DESCRIPTION(\"Realtek Wireless Lan Driver\");\nMODULE_AUTHOR(\"Realtek Semiconductor Corp.\");\nMODULE_VERSION(DRIVERVERSION);\n\n/* module param defaults */\nint rtw_chip_version = 0x00;\nint rtw_rfintfs = HWPI;\nint rtw_lbkmode = 0;/* RTL8712_AIR_TRX; */\n#ifdef DBG_LA_MODE\nint rtw_la_mode_en=0;\nmodule_param(rtw_la_mode_en, int, 0644);\n#endif\nint rtw_network_mode = Ndis802_11IBSS;/* Ndis802_11Infrastructure; */ /* infra, ad-hoc, auto */\n/* NDIS_802_11_SSID\tssid; */\nint rtw_channel = 1;/* ad-hoc support requirement */\nint rtw_wireless_mode = WIRELESS_MODE_MAX;\nmodule_param(rtw_wireless_mode, int, 0644);\nint rtw_vrtl_carrier_sense = AUTO_VCS;\nint rtw_vcs_type = RTS_CTS;\nint rtw_rts_thresh = 2347;\nint rtw_frag_thresh = 2346;\nint rtw_preamble = PREAMBLE_LONG;/* long, short, auto */\nint rtw_scan_mode = 1;/* active, passive */\n/* int smart_ps = 1; */\n#ifdef CONFIG_POWER_SAVING\n\t/* IPS configuration */\n\tint rtw_ips_mode = RTW_IPS_MODE;\n\n\t/* LPS configuration */\n/* RTW_LPS_MODE=0:disable, 1:LPS , 2:LPS with clock gating, 3: power gating */\n#if (RTW_LPS_MODE > 0)\n\tint rtw_power_mgnt = PS_MODE_MAX;\n\n\t#ifdef CONFIG_USB_HCI\n\t\tint rtw_lps_level = LPS_NORMAL; /*USB default LPS level*/\n\t#else /*SDIO,PCIE*/\n\t\tint rtw_lps_level = (RTW_LPS_MODE - 1);\n\t#endif/*CONFIG_USB_HCI*/\n#else\n\tint rtw_power_mgnt = PS_MODE_ACTIVE;\n\tint rtw_lps_level = LPS_NORMAL;\n#endif\n\n\tint rtw_lps_chk_by_tp = 1;\n\n\t/* WOW LPS configuration */\n#ifdef CONFIG_WOWLAN\n/* RTW_WOW_LPS_MODE=0:disable, 1:LPS , 2:LPS with clock gating, 3: power gating */\n#if (RTW_WOW_LPS_MODE > 0)\n\tint rtw_wow_power_mgnt = PS_MODE_MAX;\n\tint rtw_wow_lps_level = (RTW_WOW_LPS_MODE - 1);\n#else\n\tint rtw_wow_power_mgnt = PS_MODE_ACTIVE;\n\tint rtw_wow_lps_level = LPS_NORMAL;\n#endif\t\n#endif /* CONFIG_WOWLAN */\n\n#else /* !CONFIG_POWER_SAVING */\n\tint rtw_ips_mode = IPS_NONE;\n\tint rtw_power_mgnt = PS_MODE_ACTIVE;\n\tint rtw_lps_level = LPS_NORMAL;\n\tint rtw_lps_chk_by_tp = 0;\n#ifdef CONFIG_WOWLAN\n\tint rtw_wow_power_mgnt = PS_MODE_ACTIVE;\n\tint rtw_wow_lps_level = LPS_NORMAL;\n#endif /* CONFIG_WOWLAN */\n#endif /* CONFIG_POWER_SAVING */\n\n\nmodule_param(rtw_ips_mode, int, 0644);\nMODULE_PARM_DESC(rtw_ips_mode, \"The default IPS mode\");\n\nmodule_param(rtw_lps_level, int, 0644);\nMODULE_PARM_DESC(rtw_lps_level, \"The default LPS level\");\n\n#ifdef CONFIG_LPS_1T1R\nint rtw_lps_1t1r = RTW_LPS_1T1R;\nmodule_param(rtw_lps_1t1r, int, 0644);\nMODULE_PARM_DESC(rtw_lps_1t1r, \"The default LPS 1T1R setting\");\n#endif\n\nmodule_param(rtw_lps_chk_by_tp, int, 0644);\n\n#ifdef CONFIG_WOWLAN\nmodule_param(rtw_wow_power_mgnt, int, 0644);\nMODULE_PARM_DESC(rtw_wow_power_mgnt, \"The default WOW LPS mode\");\nmodule_param(rtw_wow_lps_level, int, 0644);\nMODULE_PARM_DESC(rtw_wow_lps_level, \"The default WOW LPS level\");\n#ifdef CONFIG_LPS_1T1R\nint rtw_wow_lps_1t1r = RTW_WOW_LPS_1T1R;\nmodule_param(rtw_wow_lps_1t1r, int, 0644);\nMODULE_PARM_DESC(rtw_wow_lps_1t1r, \"The default WOW LPS 1T1R setting\");\n#endif\n#endif /* CONFIG_WOWLAN */\n\n/* LPS: \n * rtw_smart_ps = 0 => TX: pwr bit = 1, RX: PS_Poll\n * rtw_smart_ps = 1 => TX: pwr bit = 0, RX: PS_Poll\n * rtw_smart_ps = 2 => TX: pwr bit = 0, RX: NullData with pwr bit = 0\n*/\nint rtw_smart_ps = 2;\n\nint rtw_max_bss_cnt = 0;\nmodule_param(rtw_max_bss_cnt, int, 0644);\n#ifdef CONFIG_WMMPS_STA\t\n/* WMMPS: \n * rtw_smart_ps = 0 => Only for fw test\n * rtw_smart_ps = 1 => Refer to Beacon's TIM Bitmap\n * rtw_smart_ps = 2 => Don't refer to Beacon's TIM Bitmap\n*/\nint rtw_wmm_smart_ps = 2;\n#endif /* CONFIG_WMMPS_STA */\n\nint rtw_check_fw_ps = 1;\n\n#ifdef CONFIG_TX_EARLY_MODE\nint rtw_early_mode = 1;\n#endif\n\nint rtw_usb_rxagg_mode = 2;/* RX_AGG_DMA=1, RX_AGG_USB=2 */\nmodule_param(rtw_usb_rxagg_mode, int, 0644);\n\nint rtw_dynamic_agg_enable = 1;\nmodule_param(rtw_dynamic_agg_enable, int, 0644);\n\n/* set log level when inserting driver module, default log level is _DRV_INFO_ = 4,\n* please refer to \"How_to_set_driver_debug_log_level.doc\" to set the available level.\n*/\n#ifdef CONFIG_RTW_DEBUG\n#ifdef RTW_LOG_LEVEL\n\tuint rtw_drv_log_level = (uint)RTW_LOG_LEVEL; /* from Makefile */\n#else\n\tuint rtw_drv_log_level = _DRV_INFO_;\n#endif\nmodule_param(rtw_drv_log_level, uint, 0644);\nMODULE_PARM_DESC(rtw_drv_log_level, \"set log level when insert driver module, default log level is _DRV_INFO_ = 4\");\n#endif\nint rtw_radio_enable = 1;\nint rtw_long_retry_lmt = 7;\nint rtw_short_retry_lmt = 7;\nint rtw_busy_thresh = 40;\n/* int qos_enable = 0; */ /* * */\nint rtw_ack_policy = NORMAL_ACK;\n\nint rtw_mp_mode = 0;\n\n#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)\nuint rtw_mp_customer_str = 0;\nmodule_param(rtw_mp_customer_str, uint, 0644);\nMODULE_PARM_DESC(rtw_mp_customer_str, \"Whether or not to enable customer str support on MP mode\");\n#endif\n\nint rtw_software_encrypt = 0;\nint rtw_software_decrypt = 0;\n\nint rtw_acm_method = 0;/* 0:By SW 1:By HW. */\n\nint rtw_wmm_enable = 1;/* default is set to enable the wmm. */\n\n#ifdef CONFIG_WMMPS_STA\n/* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */\n/* 0: NO_LIMIT, 1: TWO_MSDU, 2: FOUR_MSDU, 3: SIX_MSDU */\nint rtw_uapsd_max_sp = NO_LIMIT;\n/* BIT0: AC_VO UAPSD, BIT1: AC_VI UAPSD, BIT2: AC_BK UAPSD, BIT3: AC_BE UAPSD */\nint rtw_uapsd_ac_enable = 0x0;\n#endif /* CONFIG_WMMPS_STA */\n\n#if defined(CONFIG_RTL8814A)\n\tint rtw_pwrtrim_enable = 2; /* disable kfree , rename to power trim disable */\n#elif defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)\n\t/*PHYDM API, must enable by default*/\n\tint rtw_pwrtrim_enable = 1;\n#else\n\tint rtw_pwrtrim_enable = 0; /* Default Enalbe  power trim by efuse config */\n#endif\n\n#if CONFIG_TX_AC_LIFETIME\nuint rtw_tx_aclt_flags = CONFIG_TX_ACLT_FLAGS;\nmodule_param(rtw_tx_aclt_flags, uint, 0644);\nMODULE_PARM_DESC(rtw_tx_aclt_flags, \"device TX AC queue packet lifetime control flags\");\n\nstatic uint rtw_tx_aclt_conf_default[3] = CONFIG_TX_ACLT_CONF_DEFAULT;\nstatic uint rtw_tx_aclt_conf_default_num = 0;\nmodule_param_array(rtw_tx_aclt_conf_default, uint, &rtw_tx_aclt_conf_default_num, 0644);\nMODULE_PARM_DESC(rtw_tx_aclt_conf_default, \"device TX AC queue lifetime config for default status\");\n\n#ifdef CONFIG_TX_MCAST2UNI\nstatic uint rtw_tx_aclt_conf_ap_m2u[3] = CONFIG_TX_ACLT_CONF_AP_M2U;\nstatic uint rtw_tx_aclt_conf_ap_m2u_num = 0;\nmodule_param_array(rtw_tx_aclt_conf_ap_m2u, uint, &rtw_tx_aclt_conf_ap_m2u_num, 0644);\nMODULE_PARM_DESC(rtw_tx_aclt_conf_ap_m2u, \"device TX AC queue lifetime config for AP mode M2U status\");\n#endif\n\n#ifdef CONFIG_RTW_MESH\nstatic uint rtw_tx_aclt_conf_mesh[3] = CONFIG_TX_ACLT_CONF_MESH;\nstatic uint rtw_tx_aclt_conf_mesh_num = 0;\nmodule_param_array(rtw_tx_aclt_conf_mesh, uint, &rtw_tx_aclt_conf_mesh_num, 0644);\nMODULE_PARM_DESC(rtw_tx_aclt_conf_mesh, \"device TX AC queue lifetime config for MESH status\");\n#endif\n#endif /* CONFIG_TX_AC_LIFETIME */\n\nuint rtw_tx_bw_mode = 0x21;\nmodule_param(rtw_tx_bw_mode, uint, 0644);\nMODULE_PARM_DESC(rtw_tx_bw_mode, \"The max tx bw for 2.4G and 5G. format is the same as rtw_bw_mode\");\n\n#ifdef CONFIG_FW_HANDLE_TXBCN\nuint rtw_tbtt_rpt = 0;\t/*ROOT AP - BIT0, VAP1 - BIT1, VAP2 - BIT2, VAP3 - VAP3, FW report TBTT INT by C2H*/\nmodule_param(rtw_tbtt_rpt, uint, 0644);\n#endif\n\n#ifdef CONFIG_80211N_HT\nint rtw_ht_enable = 1;\n/* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz, 4: 80+80MHz\n* 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7\n* 0x21 means enable 2.4G 40MHz & 5G 80MHz */\n#ifdef CONFIG_RTW_CUSTOMIZE_BWMODE\nint rtw_bw_mode = CONFIG_RTW_CUSTOMIZE_BWMODE;\n#else\nint rtw_bw_mode = 0x21;\n#endif\nint rtw_ampdu_enable = 1;/* for enable tx_ampdu , */ /* 0: disable, 0x1:enable */\nint rtw_rx_stbc = 1;/* 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ */\n#if (defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)) && defined(CONFIG_PCI_HCI)\nint rtw_rx_ampdu_amsdu = 2;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */\n#elif ((defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)) && defined(CONFIG_SDIO_HCI))\nint rtw_rx_ampdu_amsdu = 1;\n#else\nint rtw_rx_ampdu_amsdu;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */\n#endif\n/*\n* 2: Follow the AMSDU filed in ADDBA Resp. (Deault)\n* 0: Force the AMSDU filed in ADDBA Resp. to be disabled.\n* 1: Force the AMSDU filed in ADDBA Resp. to be enabled.\n*/\nint rtw_tx_ampdu_amsdu = 2;\n\nint rtw_quick_addba_req = 0;\n\nstatic uint rtw_rx_ampdu_sz_limit_1ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS;\nstatic uint rtw_rx_ampdu_sz_limit_1ss_num = 0;\nmodule_param_array(rtw_rx_ampdu_sz_limit_1ss, uint, &rtw_rx_ampdu_sz_limit_1ss_num, 0644);\nMODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_1ss, \"RX AMPDU size limit for 1SS link of each BW, 0xFF: no limitation\");\n\nstatic uint rtw_rx_ampdu_sz_limit_2ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS;\nstatic uint rtw_rx_ampdu_sz_limit_2ss_num = 0;\nmodule_param_array(rtw_rx_ampdu_sz_limit_2ss, uint, &rtw_rx_ampdu_sz_limit_2ss_num, 0644);\nMODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_2ss, \"RX AMPDU size limit for 2SS link of each BW, 0xFF: no limitation\");\n\nstatic uint rtw_rx_ampdu_sz_limit_3ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS;\nstatic uint rtw_rx_ampdu_sz_limit_3ss_num = 0;\nmodule_param_array(rtw_rx_ampdu_sz_limit_3ss, uint, &rtw_rx_ampdu_sz_limit_3ss_num, 0644);\nMODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_3ss, \"RX AMPDU size limit for 3SS link of each BW, 0xFF: no limitation\");\n\nstatic uint rtw_rx_ampdu_sz_limit_4ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS;\nstatic uint rtw_rx_ampdu_sz_limit_4ss_num = 0;\nmodule_param_array(rtw_rx_ampdu_sz_limit_4ss, uint, &rtw_rx_ampdu_sz_limit_4ss_num, 0644);\nMODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_4ss, \"RX AMPDU size limit for 4SS link of each BW, 0xFF: no limitation\");\n\n/* Short GI support Bit Map\n* BIT0 - 20MHz, 0: non-support, 1: support\n* BIT1 - 40MHz, 0: non-support, 1: support\n* BIT2 - 80MHz, 0: non-support, 1: support\n* BIT3 - 160MHz, 0: non-support, 1: support */\nint rtw_short_gi = 0xf;\n/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */\nint rtw_ldpc_cap = 0x33;\n/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */\nint rtw_stbc_cap = 0x13;\n\n/*\n* BIT0: Enable VHT SU Beamformer\n* BIT1: Enable VHT SU Beamformee\n* BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer\n* BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee\n* BIT4: Enable HT Beamformer\n* BIT5: Enable HT Beamformee\n*/\nint rtw_beamform_cap = BIT(1) | BIT(3);\nint rtw_bfer_rf_number = 0; /*BeamformerCapRfNum Rf path number, 0 for auto, others for manual*/\nint rtw_bfee_rf_number = 0; /*BeamformeeCapRfNum  Rf path number, 0 for auto, others for manual*/\n\n#endif /* CONFIG_80211N_HT */\n\n#ifdef CONFIG_80211AC_VHT\nint rtw_vht_enable = 1; /* 0:disable, 1:enable, 2:force auto enable */\nmodule_param(rtw_vht_enable, int, 0644);\n\nint rtw_ampdu_factor = 7;\n\nuint rtw_vht_rx_mcs_map = 0xaaaa;\nmodule_param(rtw_vht_rx_mcs_map, uint, 0644);\nMODULE_PARM_DESC(rtw_vht_rx_mcs_map, \"VHT RX MCS map\");\n#endif /* CONFIG_80211AC_VHT */\n\nint rtw_lowrate_two_xmit = 1;/* Use 2 path Tx to transmit MCS0~7 and legacy mode */\n\nint rtw_rf_config = RF_TYPE_MAX;\nmodule_param(rtw_rf_config, int, 0644);\n\n/* 0: not check in watch dog, 1: check in watch dog  */\nint rtw_check_hw_status = 0;\n\nint rtw_low_power = 0;\nint rtw_wifi_spec = 0;\n\nint rtw_special_rf_path = 0; /* 0: 2T2R ,1: only turn on path A 1T1R */\n\nchar rtw_country_unspecified[] = {0xFF, 0xFF, 0x00};\nchar *rtw_country_code = rtw_country_unspecified;\nmodule_param(rtw_country_code, charp, 0644);\nMODULE_PARM_DESC(rtw_country_code, \"The default country code (in alpha2)\");\n\nint rtw_channel_plan = CONFIG_RTW_CHPLAN;\nmodule_param(rtw_channel_plan, int, 0644);\nMODULE_PARM_DESC(rtw_channel_plan, \"The default chplan ID when rtw_alpha2 is not specified or valid\");\n\nstatic uint rtw_excl_chs[MAX_CHANNEL_NUM] = CONFIG_RTW_EXCL_CHS;\nstatic int rtw_excl_chs_num = 0;\nmodule_param_array(rtw_excl_chs, uint, &rtw_excl_chs_num, 0644);\nMODULE_PARM_DESC(rtw_excl_chs, \"exclusive channel array\");\n\n/*if concurrent softap + p2p(GO) is needed, this param lets p2p response full channel list.\nBut Softap must be SHUT DOWN once P2P decide to set up connection and become a GO.*/\n#ifdef CONFIG_FULL_CH_IN_P2P_HANDSHAKE\n\tint rtw_full_ch_in_p2p_handshake = 1; /* reply full channel list*/\n#else\n\tint rtw_full_ch_in_p2p_handshake = 0; /* reply only softap channel*/\n#endif\n\n#ifdef CONFIG_BT_COEXIST\nint rtw_btcoex_enable = 2;\nmodule_param(rtw_btcoex_enable, int, 0644);\nMODULE_PARM_DESC(rtw_btcoex_enable, \"BT co-existence on/off, 0:off, 1:on, 2:by efuse\");\n\nint rtw_ant_num = 0;\nmodule_param(rtw_ant_num, int, 0644);\nMODULE_PARM_DESC(rtw_ant_num, \"Antenna number setting, 0:by efuse\");\n\nint rtw_bt_iso = 2;/* 0:Low, 1:High, 2:From Efuse */\nint rtw_bt_sco = 3;/* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy, 5.OtherBusy */\nint rtw_bt_ampdu = 1 ; /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */\n#endif /* CONFIG_BT_COEXIST */\n\nint rtw_AcceptAddbaReq = _TRUE;/* 0:Reject AP's Add BA req, 1:Accept AP's Add BA req. */\n\nint rtw_antdiv_cfg = 2; /* 0:OFF , 1:ON, 2:decide by Efuse config */\nint rtw_antdiv_type = 0\n\t; /* 0:decide by efuse  1: for 88EE, 1Tx and 1RxCG are diversity.(2 Ant with SPDT), 2:  for 88EE, 1Tx and 2Rx are diversity.( 2 Ant, Tx and RxCG are both on aux port, RxCS is on main port ), 3: for 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */\n\nint rtw_drv_ant_band_switch = 1; /* 0:OFF , 1:ON, Driver control antenna band switch*/\n\nint rtw_single_ant_path; /*0:main ant , 1:aux ant , Fixed single antenna path, default main ant*/\n\n/* 0: doesn't switch, 1: switch from usb2.0 to usb 3.0 2: switch from usb3.0 to usb 2.0 */\nint rtw_switch_usb_mode = 0;\n\n#ifdef CONFIG_USB_AUTOSUSPEND\nint rtw_enusbss = 1;/* 0:disable,1:enable */\n#else\nint rtw_enusbss = 0;/* 0:disable,1:enable */\n#endif\n\nint rtw_hwpdn_mode = 2; /* 0:disable,1:enable,2: by EFUSE config */\n\n#ifdef CONFIG_HW_PWRP_DETECTION\nint rtw_hwpwrp_detect = 1;\n#else\nint rtw_hwpwrp_detect = 0; /* HW power  ping detect 0:disable , 1:enable */\n#endif\n\n#ifdef CONFIG_USB_HCI\nint rtw_hw_wps_pbc = 1;\n#else\nint rtw_hw_wps_pbc = 0;\n#endif\n\n#ifdef CONFIG_TX_MCAST2UNI\nint rtw_mc2u_disable = 0;\n#endif /* CONFIG_TX_MCAST2UNI */\n\n#ifdef CONFIG_80211D\nint rtw_80211d = 0;\n#endif\n\n#ifdef CONFIG_PCI_ASPM\n/* CLK_REQ:BIT0 L0s:BIT1 ASPM_L1:BIT2 L1Off:BIT3*/\nint\trtw_pci_aspm_enable = 0x5;\n#else\nint\trtw_pci_aspm_enable;\n#endif\n\n#ifdef CONFIG_QOS_OPTIMIZATION\nint rtw_qos_opt_enable = 1; /* 0: disable,1:enable */\n#else\nint rtw_qos_opt_enable = 0; /* 0: disable,1:enable */\n#endif\nmodule_param(rtw_qos_opt_enable, int, 0644);\n\n#ifdef CONFIG_RTW_ACS\nint rtw_acs_auto_scan = 0; /*0:disable, 1:enable*/\nmodule_param(rtw_acs_auto_scan, int, 0644);\n\nint rtw_acs = 1;\nmodule_param(rtw_acs, int, 0644);\n#endif\n\n#ifdef CONFIG_BACKGROUND_NOISE_MONITOR\nint rtw_nm = 1;/*noise monitor*/\nmodule_param(rtw_nm, int, 0644);\n#endif\n\nchar *ifname = \"wlan%d\";\nmodule_param(ifname, charp, 0644);\nMODULE_PARM_DESC(ifname, \"The default name to allocate for first interface\");\n\n#ifdef CONFIG_PLATFORM_ANDROID\n\tchar *if2name = \"p2p%d\";\n#else /* CONFIG_PLATFORM_ANDROID */\n\tchar *if2name = \"wlan%d\";\n#endif /* CONFIG_PLATFORM_ANDROID */\nmodule_param(if2name, charp, 0644);\nMODULE_PARM_DESC(if2name, \"The default name to allocate for second interface\");\n\nchar *rtw_initmac = 0;  /* temp mac address if users want to use instead of the mac address in Efuse */\n\n#ifdef CONFIG_CONCURRENT_MODE\n\n\t#if (CONFIG_IFACE_NUMBER > 2)\n\t\tint rtw_virtual_iface_num = CONFIG_IFACE_NUMBER - 1;\n\t\tmodule_param(rtw_virtual_iface_num, int, 0644);\n\t#else\n\t\tint rtw_virtual_iface_num = 1;\n\t#endif\n\n#endif\n#ifdef CONFIG_AP_MODE\nu8 rtw_bmc_tx_rate = MGN_UNKNOWN;\n#endif\n#ifdef RTW_WOW_STA_MIX\nint rtw_wowlan_sta_mix_mode = 1;\n#else\nint rtw_wowlan_sta_mix_mode = 0;\n#endif\nmodule_param(rtw_wowlan_sta_mix_mode, int, 0644);\nmodule_param(rtw_pwrtrim_enable, int, 0644);\nmodule_param(rtw_initmac, charp, 0644);\nmodule_param(rtw_special_rf_path, int, 0644);\nmodule_param(rtw_chip_version, int, 0644);\nmodule_param(rtw_rfintfs, int, 0644);\nmodule_param(rtw_lbkmode, int, 0644);\nmodule_param(rtw_network_mode, int, 0644);\nmodule_param(rtw_channel, int, 0644);\nmodule_param(rtw_mp_mode, int, 0644);\nmodule_param(rtw_wmm_enable, int, 0644);\n#ifdef CONFIG_WMMPS_STA\nmodule_param(rtw_uapsd_max_sp, int, 0644);\nmodule_param(rtw_uapsd_ac_enable, int, 0644);\nmodule_param(rtw_wmm_smart_ps, int, 0644);\n#endif /* CONFIG_WMMPS_STA */\nmodule_param(rtw_vrtl_carrier_sense, int, 0644);\nmodule_param(rtw_vcs_type, int, 0644);\nmodule_param(rtw_busy_thresh, int, 0644);\n\n#ifdef CONFIG_80211N_HT\nmodule_param(rtw_ht_enable, int, 0644);\nmodule_param(rtw_bw_mode, int, 0644);\nmodule_param(rtw_ampdu_enable, int, 0644);\nmodule_param(rtw_rx_stbc, int, 0644);\nmodule_param(rtw_rx_ampdu_amsdu, int, 0644);\nmodule_param(rtw_tx_ampdu_amsdu, int, 0644);\nmodule_param(rtw_quick_addba_req, int, 0644);\n#endif /* CONFIG_80211N_HT */\n\n#ifdef CONFIG_BEAMFORMING\nmodule_param(rtw_beamform_cap, int, 0644);\n#endif\nmodule_param(rtw_lowrate_two_xmit, int, 0644);\n\nmodule_param(rtw_power_mgnt, int, 0644);\nmodule_param(rtw_smart_ps, int, 0644);\nmodule_param(rtw_low_power, int, 0644);\nmodule_param(rtw_wifi_spec, int, 0644);\n\nmodule_param(rtw_full_ch_in_p2p_handshake, int, 0644);\nmodule_param(rtw_antdiv_cfg, int, 0644);\nmodule_param(rtw_antdiv_type, int, 0644);\n\nmodule_param(rtw_drv_ant_band_switch, int, 0644);\nmodule_param(rtw_single_ant_path, int, 0644);\n\nmodule_param(rtw_switch_usb_mode, int, 0644);\n\nmodule_param(rtw_enusbss, int, 0644);\nmodule_param(rtw_hwpdn_mode, int, 0644);\nmodule_param(rtw_hwpwrp_detect, int, 0644);\n\nmodule_param(rtw_hw_wps_pbc, int, 0644);\nmodule_param(rtw_check_hw_status, int, 0644);\n\n#ifdef CONFIG_PCI_HCI\nmodule_param(rtw_pci_aspm_enable, int, 0644);\n#endif\n\n#ifdef CONFIG_TX_EARLY_MODE\nmodule_param(rtw_early_mode, int, 0644);\n#endif\n#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE\nchar *rtw_adaptor_info_caching_file_path = \"/data/misc/wifi/rtw_cache\";\nmodule_param(rtw_adaptor_info_caching_file_path, charp, 0644);\nMODULE_PARM_DESC(rtw_adaptor_info_caching_file_path, \"The path of adapter info cache file\");\n#endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */\n\n#ifdef CONFIG_LAYER2_ROAMING\nuint rtw_max_roaming_times = 2;\nmodule_param(rtw_max_roaming_times, uint, 0644);\nMODULE_PARM_DESC(rtw_max_roaming_times, \"The max roaming times to try\");\n#endif /* CONFIG_LAYER2_ROAMING */\n\n#ifdef CONFIG_IOL\nint rtw_fw_iol = 1;\nmodule_param(rtw_fw_iol, int, 0644);\nMODULE_PARM_DESC(rtw_fw_iol, \"FW IOL. 0:Disable, 1:enable, 2:by usb speed\");\n#endif /* CONFIG_IOL */\n\n#ifdef CONFIG_FILE_FWIMG\nchar *rtw_fw_file_path = \"/system/etc/firmware/rtlwifi/FW_NIC.BIN\";\nmodule_param(rtw_fw_file_path, charp, 0644);\nMODULE_PARM_DESC(rtw_fw_file_path, \"The path of fw image\");\n\nchar *rtw_fw_wow_file_path = \"/system/etc/firmware/rtlwifi/FW_WoWLAN.BIN\";\nmodule_param(rtw_fw_wow_file_path, charp, 0644);\nMODULE_PARM_DESC(rtw_fw_wow_file_path, \"The path of fw for Wake on Wireless image\");\n\n#ifdef CONFIG_MP_INCLUDED\nchar *rtw_fw_mp_bt_file_path = \"\";\nmodule_param(rtw_fw_mp_bt_file_path, charp, 0644);\nMODULE_PARM_DESC(rtw_fw_mp_bt_file_path, \"The path of fw for MP-BT image\");\n#endif /* CONFIG_MP_INCLUDED */\n#endif /* CONFIG_FILE_FWIMG */\n\n#ifdef CONFIG_TX_MCAST2UNI\nmodule_param(rtw_mc2u_disable, int, 0644);\n#endif /* CONFIG_TX_MCAST2UNI */\n\n#ifdef CONFIG_80211D\nmodule_param(rtw_80211d, int, 0644);\nMODULE_PARM_DESC(rtw_80211d, \"Enable 802.11d mechanism\");\n#endif\n\n#ifdef CONFIG_ADVANCE_OTA\n/*\tBIT(0): OTA continuous rotated test within low RSSI,1R CCA in path B\n\tBIT(1) & BIT(2): OTA continuous rotated test with low high RSSI */\n/* Experimental environment: shielding room with half of absorber and 2~3 rotation per minute */\nint rtw_advnace_ota;\nmodule_param(rtw_advnace_ota, int, 0644);\n#endif\n\nuint rtw_notch_filter = RTW_NOTCH_FILTER;\nmodule_param(rtw_notch_filter, uint, 0644);\nMODULE_PARM_DESC(rtw_notch_filter, \"0:Disable, 1:Enable, 2:Enable only for P2P\");\n\nuint rtw_hiq_filter = CONFIG_RTW_HIQ_FILTER;\nmodule_param(rtw_hiq_filter, uint, 0644);\nMODULE_PARM_DESC(rtw_hiq_filter, \"0:allow all, 1:allow special, 2:deny all\");\n\nuint rtw_adaptivity_en = CONFIG_RTW_ADAPTIVITY_EN;\nmodule_param(rtw_adaptivity_en, uint, 0644);\nMODULE_PARM_DESC(rtw_adaptivity_en, \"0:disable, 1:enable\");\n\nuint rtw_adaptivity_mode = CONFIG_RTW_ADAPTIVITY_MODE;\nmodule_param(rtw_adaptivity_mode, uint, 0644);\nMODULE_PARM_DESC(rtw_adaptivity_mode, \"0:normal, 1:carrier sense\");\n\nint rtw_adaptivity_th_l2h_ini = CONFIG_RTW_ADAPTIVITY_TH_L2H_INI;\nmodule_param(rtw_adaptivity_th_l2h_ini, int, 0644);\nMODULE_PARM_DESC(rtw_adaptivity_th_l2h_ini, \"th_l2h_ini for Adaptivity\");\n\nint rtw_adaptivity_th_edcca_hl_diff = CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF;\nmodule_param(rtw_adaptivity_th_edcca_hl_diff, int, 0644);\nMODULE_PARM_DESC(rtw_adaptivity_th_edcca_hl_diff, \"th_edcca_hl_diff for Adaptivity\");\n\n#ifdef CONFIG_DFS_MASTER\nuint rtw_dfs_region_domain = CONFIG_RTW_DFS_REGION_DOMAIN;\nmodule_param(rtw_dfs_region_domain, uint, 0644);\nMODULE_PARM_DESC(rtw_dfs_region_domain, \"0:UNKNOWN, 1:FCC, 2:MKK, 3:ETSI\");\n#endif\n\nuint rtw_amplifier_type_2g = CONFIG_RTW_AMPLIFIER_TYPE_2G;\nmodule_param(rtw_amplifier_type_2g, uint, 0644);\nMODULE_PARM_DESC(rtw_amplifier_type_2g, \"BIT3:2G ext-PA, BIT4:2G ext-LNA\");\n\nuint rtw_amplifier_type_5g = CONFIG_RTW_AMPLIFIER_TYPE_5G;\nmodule_param(rtw_amplifier_type_5g, uint, 0644);\nMODULE_PARM_DESC(rtw_amplifier_type_5g, \"BIT6:5G ext-PA, BIT7:5G ext-LNA\");\n\nuint rtw_RFE_type = CONFIG_RTW_RFE_TYPE;\nmodule_param(rtw_RFE_type, uint, 0644);\nMODULE_PARM_DESC(rtw_RFE_type, \"default init value:64\");\n\nuint rtw_powertracking_type = 64;\nmodule_param(rtw_powertracking_type, uint, 0644);\nMODULE_PARM_DESC(rtw_powertracking_type, \"default init value:64\");\n\nuint rtw_GLNA_type = CONFIG_RTW_GLNA_TYPE;\nmodule_param(rtw_GLNA_type, uint, 0644);\nMODULE_PARM_DESC(rtw_GLNA_type, \"default init value:0\");\n\nuint rtw_TxBBSwing_2G = 0xFF;\nmodule_param(rtw_TxBBSwing_2G, uint, 0644);\nMODULE_PARM_DESC(rtw_TxBBSwing_2G, \"default init value:0xFF\");\n\nuint rtw_TxBBSwing_5G = 0xFF;\nmodule_param(rtw_TxBBSwing_5G, uint, 0644);\nMODULE_PARM_DESC(rtw_TxBBSwing_5G, \"default init value:0xFF\");\n\nuint rtw_OffEfuseMask = 0;\nmodule_param(rtw_OffEfuseMask, uint, 0644);\nMODULE_PARM_DESC(rtw_OffEfuseMask, \"default open Efuse Mask value:0\");\n\nuint rtw_FileMaskEfuse = 0;\nmodule_param(rtw_FileMaskEfuse, uint, 0644);\nMODULE_PARM_DESC(rtw_FileMaskEfuse, \"default drv Mask Efuse value:0\");\n\nuint rtw_rxgain_offset_2g = 0;\nmodule_param(rtw_rxgain_offset_2g, uint, 0644);\nMODULE_PARM_DESC(rtw_rxgain_offset_2g, \"default RF Gain 2G Offset value:0\");\n\nuint rtw_rxgain_offset_5gl = 0;\nmodule_param(rtw_rxgain_offset_5gl, uint, 0644);\nMODULE_PARM_DESC(rtw_rxgain_offset_5gl, \"default RF Gain 5GL Offset value:0\");\n\nuint rtw_rxgain_offset_5gm = 0;\nmodule_param(rtw_rxgain_offset_5gm, uint, 0644);\nMODULE_PARM_DESC(rtw_rxgain_offset_5gm, \"default RF Gain 5GM Offset value:0\");\n\nuint rtw_rxgain_offset_5gh = 0;\nmodule_param(rtw_rxgain_offset_5gh, uint, 0644);\nMODULE_PARM_DESC(rtw_rxgain_offset_5gm, \"default RF Gain 5GL Offset value:0\");\n\nuint rtw_pll_ref_clk_sel = CONFIG_RTW_PLL_REF_CLK_SEL;\nmodule_param(rtw_pll_ref_clk_sel, uint, 0644);\nMODULE_PARM_DESC(rtw_pll_ref_clk_sel, \"force pll_ref_clk_sel, 0xF:use autoload value\");\n\nint rtw_tx_pwr_by_rate = CONFIG_TXPWR_BY_RATE_EN;\nmodule_param(rtw_tx_pwr_by_rate, int, 0644);\nMODULE_PARM_DESC(rtw_tx_pwr_by_rate, \"0:Disable, 1:Enable, 2: Depend on efuse\");\n\n#if CONFIG_TXPWR_LIMIT\nint rtw_tx_pwr_lmt_enable = CONFIG_TXPWR_LIMIT_EN;\nmodule_param(rtw_tx_pwr_lmt_enable, int, 0644);\nMODULE_PARM_DESC(rtw_tx_pwr_lmt_enable, \"0:Disable, 1:Enable, 2: Depend on efuse\");\n#endif\n\nstatic int rtw_target_tx_pwr_2g_a[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_A;\nstatic int rtw_target_tx_pwr_2g_a_num = 0;\nmodule_param_array(rtw_target_tx_pwr_2g_a, int, &rtw_target_tx_pwr_2g_a_num, 0644);\nMODULE_PARM_DESC(rtw_target_tx_pwr_2g_a, \"2.4G target tx power (unit:dBm) of RF path A for each rate section, should match the real calibrate power, -1: undefined\");\n\nstatic int rtw_target_tx_pwr_2g_b[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_B;\nstatic int rtw_target_tx_pwr_2g_b_num = 0;\nmodule_param_array(rtw_target_tx_pwr_2g_b, int, &rtw_target_tx_pwr_2g_b_num, 0644);\nMODULE_PARM_DESC(rtw_target_tx_pwr_2g_b, \"2.4G target tx power (unit:dBm) of RF path B for each rate section, should match the real calibrate power, -1: undefined\");\n\nstatic int rtw_target_tx_pwr_2g_c[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_C;\nstatic int rtw_target_tx_pwr_2g_c_num = 0;\nmodule_param_array(rtw_target_tx_pwr_2g_c, int, &rtw_target_tx_pwr_2g_c_num, 0644);\nMODULE_PARM_DESC(rtw_target_tx_pwr_2g_c, \"2.4G target tx power (unit:dBm) of RF path C for each rate section, should match the real calibrate power, -1: undefined\");\n\nstatic int rtw_target_tx_pwr_2g_d[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_D;\nstatic int rtw_target_tx_pwr_2g_d_num = 0;\nmodule_param_array(rtw_target_tx_pwr_2g_d, int, &rtw_target_tx_pwr_2g_d_num, 0644);\nMODULE_PARM_DESC(rtw_target_tx_pwr_2g_d, \"2.4G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined\");\n\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\nstatic int rtw_target_tx_pwr_5g_a[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_A;\nstatic int rtw_target_tx_pwr_5g_a_num = 0;\nmodule_param_array(rtw_target_tx_pwr_5g_a, int, &rtw_target_tx_pwr_5g_a_num, 0644);\nMODULE_PARM_DESC(rtw_target_tx_pwr_5g_a, \"5G target tx power (unit:dBm) of RF path A for each rate section, should match the real calibrate power, -1: undefined\");\n\nstatic int rtw_target_tx_pwr_5g_b[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_B;\nstatic int rtw_target_tx_pwr_5g_b_num = 0;\nmodule_param_array(rtw_target_tx_pwr_5g_b, int, &rtw_target_tx_pwr_5g_b_num, 0644);\nMODULE_PARM_DESC(rtw_target_tx_pwr_5g_b, \"5G target tx power (unit:dBm) of RF path B for each rate section, should match the real calibrate power, -1: undefined\");\n\nstatic int rtw_target_tx_pwr_5g_c[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_C;\nstatic int rtw_target_tx_pwr_5g_c_num = 0;\nmodule_param_array(rtw_target_tx_pwr_5g_c, int, &rtw_target_tx_pwr_5g_c_num, 0644);\nMODULE_PARM_DESC(rtw_target_tx_pwr_5g_c, \"5G target tx power (unit:dBm) of RF path C for each rate section, should match the real calibrate power, -1: undefined\");\n\nstatic int rtw_target_tx_pwr_5g_d[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_D;\nstatic int rtw_target_tx_pwr_5g_d_num = 0;\nmodule_param_array(rtw_target_tx_pwr_5g_d, int, &rtw_target_tx_pwr_5g_d_num, 0644);\nMODULE_PARM_DESC(rtw_target_tx_pwr_5g_d, \"5G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined\");\n#endif /* CONFIG_IEEE80211_BAND_5GHZ */\n\nint rtw_tsf_update_pause_factor = CONFIG_TSF_UPDATE_PAUSE_FACTOR;\nmodule_param(rtw_tsf_update_pause_factor, int, 0644);\nMODULE_PARM_DESC(rtw_tsf_update_pause_factor, \"num of bcn intervals to stay TSF update pause status\");\n\nint rtw_tsf_update_restore_factor = CONFIG_TSF_UPDATE_RESTORE_FACTOR;\nmodule_param(rtw_tsf_update_restore_factor, int, 0644);\nMODULE_PARM_DESC(rtw_tsf_update_restore_factor, \"num of bcn intervals to stay TSF update restore status\");\n\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\nchar *rtw_phy_file_path = REALTEK_CONFIG_PATH;\nmodule_param(rtw_phy_file_path, charp, 0644);\nMODULE_PARM_DESC(rtw_phy_file_path, \"The path of phy parameter\");\n/* PHY FILE Bit Map\n* BIT0 - MAC,\t\t\t\t0: non-support, 1: support\n* BIT1 - BB,\t\t\t\t\t0: non-support, 1: support\n* BIT2 - BB_PG,\t\t\t\t0: non-support, 1: support\n* BIT3 - BB_MP,\t\t\t\t0: non-support, 1: support\n* BIT4 - RF,\t\t\t\t\t0: non-support, 1: support\n* BIT5 - RF_TXPWR_TRACK,\t0: non-support, 1: support\n* BIT6 - RF_TXPWR_LMT,\t\t0: non-support, 1: support */\nint rtw_load_phy_file = (BIT2 | BIT6);\nmodule_param(rtw_load_phy_file, int, 0644);\nMODULE_PARM_DESC(rtw_load_phy_file, \"PHY File Bit Map\");\nint rtw_decrypt_phy_file = 0;\nmodule_param(rtw_decrypt_phy_file, int, 0644);\nMODULE_PARM_DESC(rtw_decrypt_phy_file, \"Enable Decrypt PHY File\");\n#endif\n\n#ifdef CONFIG_SUPPORT_TRX_SHARED\n#ifdef DFT_TRX_SHARE_MODE\nint rtw_trx_share_mode = DFT_TRX_SHARE_MODE;\n#else\nint rtw_trx_share_mode = 0;\n#endif\nmodule_param(rtw_trx_share_mode, int, 0644);\nMODULE_PARM_DESC(rtw_trx_share_mode, \"TRx FIFO Shared\");\n#endif\n\n#ifdef CONFIG_DYNAMIC_SOML\nuint rtw_dynamic_soml_en = 1;\nmodule_param(rtw_dynamic_soml_en, int, 0644);\nMODULE_PARM_DESC(rtw_dynamic_soml_en, \"0: disable, 1: enable with default param, 2: enable with specified param.\");\n\nuint rtw_dynamic_soml_train_num = 0;\nmodule_param(rtw_dynamic_soml_train_num, int, 0644);\nMODULE_PARM_DESC(rtw_dynamic_soml_train_num, \"SOML training number\");\n\nuint rtw_dynamic_soml_interval = 0;\nmodule_param(rtw_dynamic_soml_interval, int, 0644);\nMODULE_PARM_DESC(rtw_dynamic_soml_interval, \"SOML training interval\");\n\nuint rtw_dynamic_soml_period = 0;\nmodule_param(rtw_dynamic_soml_period, int, 0644);\nMODULE_PARM_DESC(rtw_dynamic_soml_period, \"SOML training period\");\n\nuint rtw_dynamic_soml_delay = 0;\nmodule_param(rtw_dynamic_soml_delay, int, 0644);\nMODULE_PARM_DESC(rtw_dynamic_soml_delay, \"SOML training delay\");\n#endif\n\nuint rtw_phydm_ability = 0xffffffff;\nmodule_param(rtw_phydm_ability, uint, 0644);\n\nuint rtw_halrf_ability = 0xffffffff;\nmodule_param(rtw_halrf_ability, uint, 0644);\n\n#ifdef CONFIG_RTW_MESH\nuint rtw_peer_alive_based_preq = 1;\nmodule_param(rtw_peer_alive_based_preq, uint, 0644);\nMODULE_PARM_DESC(rtw_peer_alive_based_preq,\n\t\"On demand PREQ will reference peer alive status. 0: Off, 1: On\");\n#endif\n\nint _netdev_open(struct net_device *pnetdev);\nint netdev_open(struct net_device *pnetdev);\nstatic int netdev_close(struct net_device *pnetdev);\n#ifdef CONFIG_PLATFORM_INTEL_BYT\nextern int rtw_sdio_set_power(int on);\n#endif /* CONFIG_PLATFORM_INTEL_BYT */\n\n#ifdef CONFIG_MCC_MODE\n/* enable MCC mode or not */\nint rtw_en_mcc = 1;\n/* can referece following value before insmod driver */\nint rtw_mcc_ap_bw20_target_tx_tp = MCC_AP_BW20_TARGET_TX_TP;\nint rtw_mcc_ap_bw40_target_tx_tp = MCC_AP_BW40_TARGET_TX_TP;\nint rtw_mcc_ap_bw80_target_tx_tp = MCC_AP_BW80_TARGET_TX_TP;\nint rtw_mcc_sta_bw20_target_tx_tp = MCC_STA_BW20_TARGET_TX_TP;\nint rtw_mcc_sta_bw40_target_tx_tp = MCC_STA_BW40_TARGET_TX_TP;\nint rtw_mcc_sta_bw80_target_tx_tp = MCC_STA_BW80_TARGET_TX_TP;\nint rtw_mcc_single_tx_cri = MCC_SINGLE_TX_CRITERIA;\nint rtw_mcc_policy_table_idx = 0;\nint rtw_mcc_duration = 0;\nint rtw_mcc_enable_runtime_duration = 1;\n#ifdef CONFIG_MCC_PHYDM_OFFLOAD\nint rtw_mcc_phydm_offload = 1;\n#else\nint rtw_mcc_phydm_offload = 0;\n#endif\nmodule_param(rtw_en_mcc, int, 0644);\nmodule_param(rtw_mcc_single_tx_cri, int, 0644);\nmodule_param(rtw_mcc_ap_bw20_target_tx_tp, int, 0644);\nmodule_param(rtw_mcc_ap_bw40_target_tx_tp, int, 0644);\nmodule_param(rtw_mcc_ap_bw80_target_tx_tp, int, 0644);\nmodule_param(rtw_mcc_sta_bw20_target_tx_tp, int, 0644);\nmodule_param(rtw_mcc_sta_bw40_target_tx_tp, int, 0644);\nmodule_param(rtw_mcc_sta_bw80_target_tx_tp, int, 0644);\nmodule_param(rtw_mcc_policy_table_idx, int, 0644);\nmodule_param(rtw_mcc_duration, int, 0644);\nmodule_param(rtw_mcc_phydm_offload, int, 0644);\n#endif /*CONFIG_MCC_MODE */\n\n#ifdef CONFIG_RTW_NAPI\n/*following setting should define NAPI in Makefile\nenable napi only = 1, disable napi = 0*/\nint rtw_en_napi = 1;\nmodule_param(rtw_en_napi, int, 0644);\n#ifdef CONFIG_RTW_NAPI_DYNAMIC\nint rtw_napi_threshold = 100; /* unit: Mbps */\nmodule_param(rtw_napi_threshold, int, 0644);\n#endif /* CONFIG_RTW_NAPI_DYNAMIC */\n#ifdef CONFIG_RTW_GRO\n/*following setting should define GRO in Makefile\nenable gro = 1, disable gro = 0*/\nint rtw_en_gro = 1;\nmodule_param(rtw_en_gro, int, 0644);\n#endif /* CONFIG_RTW_GRO */\n#endif /* CONFIG_RTW_NAPI */\n\n#ifdef RTW_IQK_FW_OFFLOAD\nint rtw_iqk_fw_offload = 1;\n#else\nint rtw_iqk_fw_offload;\n#endif /* RTW_IQK_FW_OFFLOAD */\nmodule_param(rtw_iqk_fw_offload, int, 0644);\n\n#ifdef RTW_CHANNEL_SWITCH_OFFLOAD\nint rtw_ch_switch_offload = 0;\n#else\nint rtw_ch_switch_offload;\n#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */\nmodule_param(rtw_ch_switch_offload, int, 0644);\n\n#ifdef CONFIG_TDLS\nint rtw_en_tdls = 1;\nmodule_param(rtw_en_tdls, int, 0644);\n#endif\n\n#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT\nint rtw_fw_param_init = 1;\nmodule_param(rtw_fw_param_init, int, 0644);\n#endif\n\n#ifdef CONFIG_TDMADIG\nint rtw_tdmadig_en = 1;\n/*\n1:MODE_PERFORMANCE\n2:MODE_COVERAGE\n*/\nint rtw_tdmadig_mode = 1;\nint rtw_dynamic_tdmadig = 0;\nmodule_param(rtw_tdmadig_en, int, 0644);\nmodule_param(rtw_tdmadig_mode, int, 0644);\nmodule_param(rtw_dynamic_tdmadig, int, 0644);\n#endif/*CONFIG_TDMADIG*/\n\n#ifdef CONFIG_WOWLAN\n/*\n * bit[0]: magic packet wake up\n * bit[1]: unucast packet(HW/FW unuicast)\n * bit[2]: deauth wake up\n */\nuint rtw_wakeup_event = RTW_WAKEUP_EVENT;\nmodule_param(rtw_wakeup_event, uint, 0644);\n/*\n * 0: common WOWLAN\n * bit[0]: disable BB RF\n * bit[1]: For wireless remote controller with or without connection\n */\nuint rtw_suspend_type = RTW_SUSPEND_TYPE;\nmodule_param(rtw_suspend_type, uint, 0644);\n#endif\n\n#ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY\nuint rtw_8822c_xcap_overwrite = 1;\nmodule_param(rtw_8822c_xcap_overwrite, uint, 0644);\n#endif\n\n#if CONFIG_TX_AC_LIFETIME\nstatic void rtw_regsty_load_tx_ac_lifetime(struct registry_priv *regsty)\n{\n\tint i, j;\n\tstruct tx_aclt_conf_t *conf;\n\tuint *parm;\n\n\tregsty->tx_aclt_flags = (u8)rtw_tx_aclt_flags;\n\n\tfor (i = 0; i < TX_ACLT_CONF_NUM; i++) {\n\t\tconf = &regsty->tx_aclt_confs[i];\n\t\tif (i == TX_ACLT_CONF_DEFAULT)\n\t\t\tparm = rtw_tx_aclt_conf_default;\n\t\t#ifdef CONFIG_TX_MCAST2UNI\n\t\telse if (i == TX_ACLT_CONF_AP_M2U)\n\t\t\tparm = rtw_tx_aclt_conf_ap_m2u;\n\t\t#endif\n\t\t#ifdef CONFIG_RTW_MESH\n\t\telse if (i == TX_ACLT_CONF_MESH)\n\t\t\tparm = rtw_tx_aclt_conf_mesh;\n\t\t#endif\n\t\telse\n\t\t\tparm = NULL;\n\n\t\tif (parm) {\n\t\t\tconf->en = parm[0] & 0xF;\n\t\t\tconf->vo_vi = parm[1];\n\t\t\tconf->be_bk = parm[2];\n\t\t}\t\n\t}\n}\n#endif\n\nvoid rtw_regsty_load_target_tx_power(struct registry_priv *regsty)\n{\n\tint path, rs;\n\tint *target_tx_pwr;\n\n\tfor (path = RF_PATH_A; path < RF_PATH_MAX; path++) {\n\t\tif (path == RF_PATH_A)\n\t\t\ttarget_tx_pwr = rtw_target_tx_pwr_2g_a;\n\t\telse if (path == RF_PATH_B)\n\t\t\ttarget_tx_pwr = rtw_target_tx_pwr_2g_b;\n\t\telse if (path == RF_PATH_C)\n\t\t\ttarget_tx_pwr = rtw_target_tx_pwr_2g_c;\n\t\telse if (path == RF_PATH_D)\n\t\t\ttarget_tx_pwr = rtw_target_tx_pwr_2g_d;\n\n\t\tfor (rs = CCK; rs < RATE_SECTION_NUM; rs++)\n\t\t\tregsty->target_tx_pwr_2g[path][rs] = target_tx_pwr[rs];\n\t}\n\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\tfor (path = RF_PATH_A; path < RF_PATH_MAX; path++) {\n\t\tif (path == RF_PATH_A)\n\t\t\ttarget_tx_pwr = rtw_target_tx_pwr_5g_a;\n\t\telse if (path == RF_PATH_B)\n\t\t\ttarget_tx_pwr = rtw_target_tx_pwr_5g_b;\n\t\telse if (path == RF_PATH_C)\n\t\t\ttarget_tx_pwr = rtw_target_tx_pwr_5g_c;\n\t\telse if (path == RF_PATH_D)\n\t\t\ttarget_tx_pwr = rtw_target_tx_pwr_5g_d;\n\n\t\tfor (rs = OFDM; rs < RATE_SECTION_NUM; rs++)\n\t\t\tregsty->target_tx_pwr_5g[path][rs - 1] = target_tx_pwr[rs - 1];\n\t}\n#endif /* CONFIG_IEEE80211_BAND_5GHZ */\n}\n\ninline void rtw_regsty_load_excl_chs(struct registry_priv *regsty)\n{\n\tint i;\n\tint ch_num = 0;\n\n\tfor (i = 0; i < MAX_CHANNEL_NUM; i++)\n\t\tif (((u8)rtw_excl_chs[i]) != 0)\n\t\t\tregsty->excl_chs[ch_num++] = (u8)rtw_excl_chs[i];\n\n\tif (ch_num < MAX_CHANNEL_NUM)\n\t\tregsty->excl_chs[ch_num] = 0;\n}\n\n#ifdef CONFIG_80211N_HT\ninline void rtw_regsty_init_rx_ampdu_sz_limit(struct registry_priv *regsty)\n{\n\tint i, j;\n\tuint *sz_limit;\n\n\tfor (i = 0; i < 4; i++) {\n\t\tif (i == 0)\n\t\t\tsz_limit = rtw_rx_ampdu_sz_limit_1ss;\n\t\telse if (i == 1)\n\t\t\tsz_limit = rtw_rx_ampdu_sz_limit_2ss;\n\t\telse if (i == 2)\n\t\t\tsz_limit = rtw_rx_ampdu_sz_limit_3ss;\n\t\telse if (i == 3)\n\t\t\tsz_limit = rtw_rx_ampdu_sz_limit_4ss;\n\n\t\tfor (j = 0; j < 4; j++)\n\t\t\tregsty->rx_ampdu_sz_limit_by_nss_bw[i][j] = sz_limit[j];\n\t}\n}\n#endif /* CONFIG_80211N_HT */\n\nuint loadparam(_adapter *padapter)\n{\n\tuint status = _SUCCESS;\n\tstruct registry_priv  *registry_par = &padapter->registrypriv;\n\n\n#ifdef CONFIG_RTW_DEBUG\n\tif (rtw_drv_log_level >= _DRV_MAX_)\n\t\trtw_drv_log_level = _DRV_DEBUG_;\n#endif\n\n\tregistry_par->chip_version = (u8)rtw_chip_version;\n\tregistry_par->rfintfs = (u8)rtw_rfintfs;\n\tregistry_par->lbkmode = (u8)rtw_lbkmode;\n\t/* registry_par->hci = (u8)hci; */\n\tregistry_par->network_mode  = (u8)rtw_network_mode;\n\n\t_rtw_memcpy(registry_par->ssid.Ssid, \"ANY\", 3);\n\tregistry_par->ssid.SsidLength = 3;\n\n\tregistry_par->channel = (u8)rtw_channel;\n\tregistry_par->wireless_mode = (u8)rtw_wireless_mode;\n\n\tif (IsSupported24G(registry_par->wireless_mode) && (!is_supported_5g(registry_par->wireless_mode))\n\t    && (registry_par->channel > 14))\n\t\tregistry_par->channel = 1;\n\telse if (is_supported_5g(registry_par->wireless_mode) && (!IsSupported24G(registry_par->wireless_mode))\n\t\t && (registry_par->channel <= 14))\n\t\tregistry_par->channel = 36;\n\n\tregistry_par->vrtl_carrier_sense = (u8)rtw_vrtl_carrier_sense ;\n\tregistry_par->vcs_type = (u8)rtw_vcs_type;\n\tregistry_par->rts_thresh = (u16)rtw_rts_thresh;\n\tregistry_par->frag_thresh = (u16)rtw_frag_thresh;\n\tregistry_par->preamble = (u8)rtw_preamble;\n\tregistry_par->scan_mode = (u8)rtw_scan_mode;\n\tregistry_par->smart_ps = (u8)rtw_smart_ps;\n\tregistry_par->check_fw_ps = (u8)rtw_check_fw_ps;\n\t#ifdef CONFIG_TDMADIG\n\t\tregistry_par->tdmadig_en = (u8)rtw_tdmadig_en;\n\t\tregistry_par->tdmadig_mode = (u8)rtw_tdmadig_mode;\n\t\tregistry_par->tdmadig_dynamic = (u8) rtw_dynamic_tdmadig;\n\t\tregistry_par->power_mgnt = PS_MODE_ACTIVE;\n\t\tregistry_par->ips_mode = IPS_NONE;\n\t#else\n\t\tregistry_par->power_mgnt = (u8)rtw_power_mgnt;\n\t\tregistry_par->ips_mode = (u8)rtw_ips_mode;\n\t#endif/*CONFIG_TDMADIG*/\n\tregistry_par->lps_level = (u8)rtw_lps_level;\n#ifdef CONFIG_LPS_1T1R\n\tregistry_par->lps_1t1r = (u8)(rtw_lps_1t1r ? 1 : 0);\n#endif\n\tregistry_par->lps_chk_by_tp = (u8)rtw_lps_chk_by_tp;\n#ifdef CONFIG_WOWLAN\n\tregistry_par->wow_power_mgnt = (u8)rtw_wow_power_mgnt;\n\tregistry_par->wow_lps_level = (u8)rtw_wow_lps_level;\n\t#ifdef CONFIG_LPS_1T1R\n\tregistry_par->wow_lps_1t1r = (u8)(rtw_wow_lps_1t1r ? 1 : 0);\n\t#endif\n#endif /* CONFIG_WOWLAN */\n\tregistry_par->radio_enable = (u8)rtw_radio_enable;\n\tregistry_par->long_retry_lmt = (u8)rtw_long_retry_lmt;\n\tregistry_par->short_retry_lmt = (u8)rtw_short_retry_lmt;\n\tregistry_par->busy_thresh = (u16)rtw_busy_thresh;\n\tregistry_par->max_bss_cnt = (u16)rtw_max_bss_cnt;\n\t/* registry_par->qos_enable = (u8)rtw_qos_enable; */\n\tregistry_par->ack_policy = (u8)rtw_ack_policy;\n\tregistry_par->mp_mode = (u8)rtw_mp_mode;\n#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)\n\tregistry_par->mp_customer_str = (u8)rtw_mp_customer_str;\n#endif\n\tregistry_par->software_encrypt = (u8)rtw_software_encrypt;\n\tregistry_par->software_decrypt = (u8)rtw_software_decrypt;\n\n\tregistry_par->acm_method = (u8)rtw_acm_method;\n\tregistry_par->usb_rxagg_mode = (u8)rtw_usb_rxagg_mode;\n\tregistry_par->dynamic_agg_enable = (u8)rtw_dynamic_agg_enable;\n\n\t/* WMM */\n\tregistry_par->wmm_enable = (u8)rtw_wmm_enable;\n\n#ifdef CONFIG_WMMPS_STA\n\t/* UAPSD */\n\tregistry_par->uapsd_max_sp_len= (u8)rtw_uapsd_max_sp;\n\tregistry_par->uapsd_ac_enable = (u8)rtw_uapsd_ac_enable;\n\tregistry_par->wmm_smart_ps = (u8)rtw_wmm_smart_ps;\n#endif /* CONFIG_WMMPS_STA */\n\n\tregistry_par->RegPwrTrimEnable = (u8)rtw_pwrtrim_enable;\n\n#if CONFIG_TX_AC_LIFETIME\n\trtw_regsty_load_tx_ac_lifetime(registry_par);\n#endif\n\n\tregistry_par->tx_bw_mode = (u8)rtw_tx_bw_mode;\n\n#ifdef CONFIG_80211N_HT\n\tregistry_par->ht_enable = (u8)rtw_ht_enable;\n\tif (registry_par->ht_enable && is_supported_ht(registry_par->wireless_mode)) {\n\t\tregistry_par->bw_mode = (u8)rtw_bw_mode;\n\t\tregistry_par->ampdu_enable = (u8)rtw_ampdu_enable;\n\t\tregistry_par->rx_stbc = (u8)rtw_rx_stbc;\n\t\tregistry_par->rx_ampdu_amsdu = (u8)rtw_rx_ampdu_amsdu;\n\t\tregistry_par->tx_ampdu_amsdu = (u8)rtw_tx_ampdu_amsdu;\n\t\tregistry_par->tx_quick_addba_req = (u8)rtw_quick_addba_req;\n\t\tregistry_par->short_gi = (u8)rtw_short_gi;\n\t\tregistry_par->ldpc_cap = (u8)rtw_ldpc_cap;\n#if defined(CONFIG_CUSTOMER01_SMART_ANTENNA)\n\t\trtw_stbc_cap = 0x0;\n#elif defined(CONFIG_RTW_TX_2PATH_EN)\n\t\trtw_stbc_cap &= ~(BIT1|BIT5);\n#endif\n\t\tregistry_par->stbc_cap = (u8)rtw_stbc_cap;\n#if defined(CONFIG_RTW_TX_2PATH_EN)\n\t\trtw_beamform_cap &= ~(BIT0|BIT2|BIT4);\n#endif\n\t\tregistry_par->beamform_cap = (u8)rtw_beamform_cap;\n\t\tregistry_par->beamformer_rf_num = (u8)rtw_bfer_rf_number;\n\t\tregistry_par->beamformee_rf_num = (u8)rtw_bfee_rf_number;\n\t\trtw_regsty_init_rx_ampdu_sz_limit(registry_par);\n\t}\n#endif\n#ifdef DBG_LA_MODE\n\tregistry_par->la_mode_en = (u8)rtw_la_mode_en;\n#endif\n#ifdef CONFIG_80211AC_VHT\n\tregistry_par->vht_enable = (u8)rtw_vht_enable;\n\tregistry_par->ampdu_factor = (u8)rtw_ampdu_factor;\n\tregistry_par->vht_rx_mcs_map[0] = (u8)(rtw_vht_rx_mcs_map & 0xFF);\n\tregistry_par->vht_rx_mcs_map[1] = (u8)((rtw_vht_rx_mcs_map & 0xFF00) >> 8);\n#endif\n\n#ifdef CONFIG_TX_EARLY_MODE\n\tregistry_par->early_mode = (u8)rtw_early_mode;\n#endif\n\tregistry_par->lowrate_two_xmit = (u8)rtw_lowrate_two_xmit;\n\tregistry_par->rf_config = (u8)rtw_rf_config;\n\tregistry_par->low_power = (u8)rtw_low_power;\n\n\tregistry_par->check_hw_status = (u8)rtw_check_hw_status;\n\n\tregistry_par->wifi_spec = (u8)rtw_wifi_spec;\n\n\tif (strlen(rtw_country_code) != 2\n\t\t|| is_alpha(rtw_country_code[0]) == _FALSE\n\t\t|| is_alpha(rtw_country_code[1]) == _FALSE\n\t) {\n\t\tif (rtw_country_code != rtw_country_unspecified)\n\t\t\tRTW_ERR(\"%s discard rtw_country_code not in alpha2\\n\", __func__);\n\t\t_rtw_memset(registry_par->alpha2, 0xFF, 2);\n\t} else\n\t\t_rtw_memcpy(registry_par->alpha2, rtw_country_code, 2);\n\n\tregistry_par->channel_plan = (u8)rtw_channel_plan;\n\trtw_regsty_load_excl_chs(registry_par);\n\n\tregistry_par->special_rf_path = (u8)rtw_special_rf_path;\n\n\tregistry_par->full_ch_in_p2p_handshake = (u8)rtw_full_ch_in_p2p_handshake;\n#ifdef CONFIG_BT_COEXIST\n\tregistry_par->btcoex = (u8)rtw_btcoex_enable;\n\tregistry_par->bt_iso = (u8)rtw_bt_iso;\n\tregistry_par->bt_sco = (u8)rtw_bt_sco;\n\tregistry_par->bt_ampdu = (u8)rtw_bt_ampdu;\n\tregistry_par->ant_num = (u8)rtw_ant_num;\n\tregistry_par->single_ant_path = (u8) rtw_single_ant_path;\n#endif\n\n\tregistry_par->bAcceptAddbaReq = (u8)rtw_AcceptAddbaReq;\n\n\tregistry_par->antdiv_cfg = (u8)rtw_antdiv_cfg;\n\tregistry_par->antdiv_type = (u8)rtw_antdiv_type;\n\n\tregistry_par->drv_ant_band_switch = (u8) rtw_drv_ant_band_switch;\n\n\tregistry_par->switch_usb_mode = (u8)rtw_switch_usb_mode;\n\n#ifdef CONFIG_AUTOSUSPEND\n\tregistry_par->usbss_enable = (u8)rtw_enusbss;/* 0:disable,1:enable */\n#endif\n#ifdef SUPPORT_HW_RFOFF_DETECTED\n\tregistry_par->hwpdn_mode = (u8)rtw_hwpdn_mode;/* 0:disable,1:enable,2:by EFUSE config */\n\tregistry_par->hwpwrp_detect = (u8)rtw_hwpwrp_detect;/* 0:disable,1:enable */\n#endif\n\n\tregistry_par->hw_wps_pbc = (u8)rtw_hw_wps_pbc;\n\n#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE\n\tsnprintf(registry_par->adaptor_info_caching_file_path, PATH_LENGTH_MAX, \"%s\", rtw_adaptor_info_caching_file_path);\n\tregistry_par->adaptor_info_caching_file_path[PATH_LENGTH_MAX - 1] = 0;\n#endif\n\n#ifdef CONFIG_LAYER2_ROAMING\n\tregistry_par->max_roaming_times = (u8)rtw_max_roaming_times;\n#endif\n\n#ifdef CONFIG_IOL\n\tregistry_par->fw_iol = rtw_fw_iol;\n#endif\n\n#ifdef CONFIG_80211D\n\tregistry_par->enable80211d = (u8)rtw_80211d;\n#endif\n\n\tsnprintf(registry_par->ifname, 16, \"%s\", ifname);\n\tsnprintf(registry_par->if2name, 16, \"%s\", if2name);\n\n\tregistry_par->notch_filter = (u8)rtw_notch_filter;\n\n#ifdef CONFIG_CONCURRENT_MODE\n\tregistry_par->virtual_iface_num = (u8)rtw_virtual_iface_num;\n#endif\n\tregistry_par->pll_ref_clk_sel = (u8)rtw_pll_ref_clk_sel;\n\n#if CONFIG_TXPWR_LIMIT\n\tregistry_par->RegEnableTxPowerLimit = (u8)rtw_tx_pwr_lmt_enable;\n#endif\n\tregistry_par->RegEnableTxPowerByRate = (u8)rtw_tx_pwr_by_rate;\n\n\trtw_regsty_load_target_tx_power(registry_par);\n\n\tregistry_par->tsf_update_pause_factor = (u8)rtw_tsf_update_pause_factor;\n\tregistry_par->tsf_update_restore_factor = (u8)rtw_tsf_update_restore_factor;\n\n\tregistry_par->TxBBSwing_2G = (s8)rtw_TxBBSwing_2G;\n\tregistry_par->TxBBSwing_5G = (s8)rtw_TxBBSwing_5G;\n\tregistry_par->bEn_RFE = 1;\n\tregistry_par->RFE_Type = (u8)rtw_RFE_type;\n\tregistry_par->PowerTracking_Type = (u8)rtw_powertracking_type;\n\tregistry_par->AmplifierType_2G = (u8)rtw_amplifier_type_2g;\n\tregistry_par->AmplifierType_5G = (u8)rtw_amplifier_type_5g;\n\tregistry_par->GLNA_Type = (u8)rtw_GLNA_type;\n#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\tregistry_par->load_phy_file = (u8)rtw_load_phy_file;\n\tregistry_par->RegDecryptCustomFile = (u8)rtw_decrypt_phy_file;\n#endif\n\tregistry_par->qos_opt_enable = (u8)rtw_qos_opt_enable;\n\n\tregistry_par->hiq_filter = (u8)rtw_hiq_filter;\n\n\tregistry_par->adaptivity_en = (u8)rtw_adaptivity_en;\n\tregistry_par->adaptivity_mode = (u8)rtw_adaptivity_mode;\n\tregistry_par->adaptivity_th_l2h_ini = (s8)rtw_adaptivity_th_l2h_ini;\n\tregistry_par->adaptivity_th_edcca_hl_diff = (s8)rtw_adaptivity_th_edcca_hl_diff;\n\n#ifdef CONFIG_DYNAMIC_SOML\n\tregistry_par->dyn_soml_en = (u8)rtw_dynamic_soml_en;\n\tregistry_par->dyn_soml_train_num = (u8)rtw_dynamic_soml_train_num;\n\tregistry_par->dyn_soml_interval = (u8)rtw_dynamic_soml_interval;\n\tregistry_par->dyn_soml_period = (u8)rtw_dynamic_soml_period;\n\tregistry_par->dyn_soml_delay = (u8)rtw_dynamic_soml_delay;\n#endif\n\n\tregistry_par->boffefusemask = (u8)rtw_OffEfuseMask;\n\tregistry_par->bFileMaskEfuse = (u8)rtw_FileMaskEfuse;\n\tregistry_par->bBTFileMaskEfuse = (u8)rtw_FileMaskEfuse;\n\n#ifdef CONFIG_RTW_ACS\n\tregistry_par->acs_mode = (u8)rtw_acs;\n\tregistry_par->acs_auto_scan = (u8)rtw_acs_auto_scan;\n#endif\n#ifdef CONFIG_BACKGROUND_NOISE_MONITOR\n\tregistry_par->nm_mode = (u8)rtw_nm;\n#endif\n\tregistry_par->reg_rxgain_offset_2g = (u32) rtw_rxgain_offset_2g;\n\tregistry_par->reg_rxgain_offset_5gl = (u32) rtw_rxgain_offset_5gl;\n\tregistry_par->reg_rxgain_offset_5gm = (u32) rtw_rxgain_offset_5gm;\n\tregistry_par->reg_rxgain_offset_5gh = (u32) rtw_rxgain_offset_5gh;\n\n#ifdef CONFIG_DFS_MASTER\n\tregistry_par->dfs_region_domain = (u8)rtw_dfs_region_domain;\n#endif\n\n#ifdef CONFIG_MCC_MODE\n\tregistry_par->en_mcc = (u8)rtw_en_mcc;\n\tregistry_par->rtw_mcc_ap_bw20_target_tx_tp = (u32)rtw_mcc_ap_bw20_target_tx_tp;\n\tregistry_par->rtw_mcc_ap_bw40_target_tx_tp = (u32)rtw_mcc_ap_bw40_target_tx_tp;\n\tregistry_par->rtw_mcc_ap_bw80_target_tx_tp = (u32)rtw_mcc_ap_bw80_target_tx_tp;\n\tregistry_par->rtw_mcc_sta_bw20_target_tx_tp = (u32)rtw_mcc_sta_bw20_target_tx_tp;\n\tregistry_par->rtw_mcc_sta_bw40_target_tx_tp = (u32)rtw_mcc_sta_bw40_target_tx_tp;\n\tregistry_par->rtw_mcc_sta_bw80_target_tx_tp = (u32)rtw_mcc_sta_bw80_target_tx_tp;\n\tregistry_par->rtw_mcc_single_tx_cri = (u32)rtw_mcc_single_tx_cri;\n\tregistry_par->rtw_mcc_policy_table_idx = rtw_mcc_policy_table_idx;\n\tregistry_par->rtw_mcc_duration = (u8)rtw_mcc_duration;\n\tregistry_par->rtw_mcc_enable_runtime_duration = rtw_mcc_enable_runtime_duration;\n\tregistry_par->rtw_mcc_phydm_offload = rtw_mcc_phydm_offload;\n#endif /*CONFIG_MCC_MODE */\n\n#ifdef CONFIG_WOWLAN\n\tregistry_par->wakeup_event = rtw_wakeup_event;\n\tregistry_par->suspend_type = rtw_suspend_type;\n#endif\n\n#ifdef CONFIG_SUPPORT_TRX_SHARED\n\tregistry_par->trx_share_mode = rtw_trx_share_mode;\n#endif\n\tregistry_par->wowlan_sta_mix_mode = rtw_wowlan_sta_mix_mode;\n\n#ifdef CONFIG_PCI_HCI\n\tregistry_par->pci_aspm_config = rtw_pci_aspm_enable;\n#endif\n\n#ifdef CONFIG_RTW_NAPI\n\tregistry_par->en_napi = (u8)rtw_en_napi;\n#ifdef CONFIG_RTW_NAPI_DYNAMIC\n\tregistry_par->napi_threshold = (u32)rtw_napi_threshold;\n#endif /* CONFIG_RTW_NAPI_DYNAMIC */\n#ifdef CONFIG_RTW_GRO\n\tregistry_par->en_gro = (u8)rtw_en_gro;\n\tif (!registry_par->en_napi && registry_par->en_gro) {\n\t\tregistry_par->en_gro = 0;\n\t\tRTW_WARN(\"Disable GRO because NAPI is not enabled\\n\");\n\t}\n#endif /* CONFIG_RTW_GRO */\n#endif /* CONFIG_RTW_NAPI */\n\n\tregistry_par->iqk_fw_offload = (u8)rtw_iqk_fw_offload;\n\tregistry_par->ch_switch_offload = (u8)rtw_ch_switch_offload;\n\n#ifdef CONFIG_TDLS\n\tregistry_par->en_tdls = rtw_en_tdls;\n#endif\n\n#ifdef CONFIG_ADVANCE_OTA\n\tregistry_par->adv_ota = rtw_advnace_ota;\n#endif\n#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT\n\tregistry_par->fw_param_init = rtw_fw_param_init;\n#endif\n#ifdef CONFIG_AP_MODE\n\tregistry_par->bmc_tx_rate = rtw_bmc_tx_rate;\n#endif\n#ifdef CONFIG_FW_HANDLE_TXBCN\n\tregistry_par->fw_tbtt_rpt = rtw_tbtt_rpt;\n#endif\n\tregistry_par->phydm_ability = rtw_phydm_ability;\n\tregistry_par->halrf_ability = rtw_halrf_ability;\n#ifdef CONFIG_RTW_MESH\n\tregistry_par->peer_alive_based_preq = rtw_peer_alive_based_preq;\n#endif\n\n#ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY\n\tregistry_par->rtw_8822c_xcap_overwrite = (u8)rtw_8822c_xcap_overwrite;\n#endif\n\n\treturn status;\n}\n\n/**\n * rtw_net_set_mac_address\n * This callback function is used for the Media Access Control address\n * of each net_device needs to be changed.\n *\n * Arguments:\n * @pnetdev: net_device pointer.\n * @addr: new MAC address.\n *\n * Return:\n * ret = 0: Permit to change net_device's MAC address.\n * ret = -1 (Default): Operation not permitted.\n *\n * Auther: Arvin Liu\n * Date: 2015/05/29\n */\nstatic int rtw_net_set_mac_address(struct net_device *pnetdev, void *addr)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct sockaddr *sa = (struct sockaddr *)addr;\n\tint ret = -1;\n\n\t/* only the net_device is in down state to permit modifying mac addr */\n\tif ((pnetdev->flags & IFF_UP) == _TRUE) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\": The net_device's is not in down state\\n\"\n\t\t\t , FUNC_ADPT_ARG(padapter));\n\n\t\treturn ret;\n\t}\n\n\t/* if the net_device is linked, it's not permit to modify mac addr */\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) ||\n\t    check_fwstate(pmlmepriv, _FW_LINKED) ||\n\t    check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\": The net_device's is not idle currently\\n\"\n\t\t\t , FUNC_ADPT_ARG(padapter));\n\n\t\treturn ret;\n\t}\n\n\t/* check whether the input mac address is valid to permit modifying mac addr */\n\tif (rtw_check_invalid_mac_address(sa->sa_data, _FALSE) == _TRUE) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\": Invalid Mac Addr for \"MAC_FMT\"\\n\"\n\t\t\t , FUNC_ADPT_ARG(padapter), MAC_ARG(sa->sa_data));\n\n\t\treturn ret;\n\t}\n\n\t_rtw_memcpy(adapter_mac_addr(padapter), sa->sa_data, ETH_ALEN); /* set mac addr to adapter */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0))\n\teth_hw_addr_set(pnetdev, sa->sa_data);\n#else\n\t_rtw_memcpy(pnetdev->dev_addr, sa->sa_data, ETH_ALEN); /* set mac addr to net_device */\n#endif\n\n#if 0\n\tif (rtw_is_hw_init_completed(padapter)) {\n\t\trtw_ps_deny(padapter, PS_DENY_IOCTL);\n\t\tLeaveAllPowerSaveModeDirect(padapter); /* leave PS mode for guaranteeing to access hw register successfully */\n\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\t\trtw_hal_change_macaddr_mbid(padapter, sa->sa_data);\n#else\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, sa->sa_data); /* set mac addr to mac register */\n#endif\n\n\t\trtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);\n\t}\n#else\n\trtw_ps_deny(padapter, PS_DENY_IOCTL);\n\tLeaveAllPowerSaveModeDirect(padapter); /* leave PS mode for guaranteeing to access hw register successfully */\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\trtw_hal_change_macaddr_mbid(padapter, sa->sa_data);\n#else\n\trtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, sa->sa_data); /* set mac addr to mac register */\n#endif\n\trtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);\n#endif\n\n\tRTW_INFO(FUNC_ADPT_FMT\": Set Mac Addr to \"MAC_FMT\" Successfully\\n\"\n\t\t , FUNC_ADPT_ARG(padapter), MAC_ARG(sa->sa_data));\n\n\tret = 0;\n\n\treturn ret;\n}\n\nstatic struct net_device_stats *rtw_net_get_stats(struct net_device *pnetdev)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);\n\tstruct xmit_priv *pxmitpriv = &(padapter->xmitpriv);\n\tstruct recv_priv *precvpriv = &(padapter->recvpriv);\n\n\tpadapter->stats.tx_packets = pxmitpriv->tx_pkts;/* pxmitpriv->tx_pkts++; */\n\tpadapter->stats.rx_packets = precvpriv->rx_pkts;/* precvpriv->rx_pkts++; */\n\tpadapter->stats.tx_dropped = pxmitpriv->tx_drop;\n\tpadapter->stats.rx_dropped = precvpriv->rx_drop;\n\tpadapter->stats.tx_bytes = pxmitpriv->tx_bytes;\n\tpadapter->stats.rx_bytes = precvpriv->rx_bytes;\n\n\treturn &padapter->stats;\n}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n/*\n * AC to queue mapping\n *\n * AC_VO -> queue 0\n * AC_VI -> queue 1\n * AC_BE -> queue 2\n * AC_BK -> queue 3\n */\nstatic const u16 rtw_1d_to_queue[8] = { 2, 3, 3, 2, 1, 1, 0, 0 };\n\n/* Given a data frame determine the 802.1p/1d tag to use. */\nunsigned int rtw_classify8021d(struct sk_buff *skb)\n{\n\tunsigned int dscp;\n\n\t/* skb->priority values from 256->263 are magic values to\n\t * directly indicate a specific 802.1d priority.  This is used\n\t * to allow 802.1d priority to be passed directly in from VLAN\n\t * tags, etc.\n\t */\n\tif (skb->priority >= 256 && skb->priority <= 263)\n\t\treturn skb->priority - 256;\n\n\tswitch (skb->protocol) {\n\tcase htons(ETH_P_IP):\n\t\tdscp = ip_hdr(skb)->tos & 0xfc;\n\t\tbreak;\n\tdefault:\n\t\treturn 0;\n\t}\n\n\treturn dscp >> 5;\n}\n\n\nstatic u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)\n\t#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0)\n\t, struct net_device *sb_dev\n\t#else\n\t, void *accel_priv\n\t#endif\n\t#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0)))\n\t, select_queue_fallback_t fallback\n\t#endif\n#endif\n)\n{\n\t_adapter\t*padapter = rtw_netdev_priv(dev);\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n\tskb->priority = rtw_classify8021d(skb);\n\n\tif (pmlmepriv->acm_mask != 0)\n\t\tskb->priority = qos_acm(pmlmepriv->acm_mask, skb->priority);\n\n\treturn rtw_1d_to_queue[skb->priority];\n}\n\nu16 rtw_recv_select_queue(struct sk_buff *skb)\n{\n\tstruct iphdr *piphdr;\n\tunsigned int dscp;\n\tu16\teth_type;\n\tu32 priority;\n\tu8 *pdata = skb->data;\n\n\t_rtw_memcpy(&eth_type, pdata + (ETH_ALEN << 1), 2);\n\n\tswitch (eth_type) {\n\tcase htons(ETH_P_IP):\n\n\t\tpiphdr = (struct iphdr *)(pdata + ETH_HLEN);\n\n\t\tdscp = piphdr->tos & 0xfc;\n\n\t\tpriority = dscp >> 5;\n\n\t\tbreak;\n\tdefault:\n\t\tpriority = 0;\n\t}\n\n\treturn rtw_1d_to_queue[priority];\n\n}\n\n#endif\n\nstatic u8 is_rtw_ndev(struct net_device *ndev)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))\n\treturn ndev->netdev_ops\n\t\t&& ndev->netdev_ops->ndo_do_ioctl\n\t\t&& ndev->netdev_ops->ndo_do_ioctl == rtw_ioctl;\n#else\n\treturn ndev->do_ioctl\n\t\t&& ndev->do_ioctl == rtw_ioctl;\n#endif\n}\n\nstatic int rtw_ndev_notifier_call(struct notifier_block *nb, unsigned long state, void *ptr)\n{\n\tstruct net_device *ndev;\n\n\tif (ptr == NULL)\n\t\treturn NOTIFY_DONE;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))\n\tndev = netdev_notifier_info_to_dev(ptr);\n#else\n\tndev = ptr;\n#endif\n\n\tif (ndev == NULL)\n\t\treturn NOTIFY_DONE;\n\n\tif (!is_rtw_ndev(ndev))\n\t\treturn NOTIFY_DONE;\n\n\tRTW_INFO(FUNC_NDEV_FMT\" state:%lu\\n\", FUNC_NDEV_ARG(ndev), state);\n\n\tswitch (state) {\n\tcase NETDEV_CHANGENAME:\n\t\trtw_adapter_proc_replace(ndev);\n\t\tbreak;\n\t#ifdef CONFIG_NEW_NETDEV_HDL\n\tcase NETDEV_PRE_UP :\n\t\t{\n\t\t\t_adapter *adapter = rtw_netdev_priv(ndev);\n\n\t\t\trtw_pwr_wakeup(adapter);\n\t\t}\n\t\tbreak;\n\t#endif\n\t}\n\n\treturn NOTIFY_DONE;\n}\n\nstatic struct notifier_block rtw_ndev_notifier = {\n\t.notifier_call = rtw_ndev_notifier_call,\n};\n\nint rtw_ndev_notifier_register(void)\n{\n\treturn register_netdevice_notifier(&rtw_ndev_notifier);\n}\n\nvoid rtw_ndev_notifier_unregister(void)\n{\n\tunregister_netdevice_notifier(&rtw_ndev_notifier);\n}\n\nint rtw_ndev_init(struct net_device *dev)\n{\n\t_adapter *adapter = rtw_netdev_priv(dev);\n\n\tRTW_PRINT(FUNC_ADPT_FMT\" if%d mac_addr=\"MAC_FMT\"\\n\"\n\t\t, FUNC_ADPT_ARG(adapter), (adapter->iface_id + 1), MAC_ARG(dev->dev_addr));\n\tstrncpy(adapter->old_ifname, dev->name, IFNAMSIZ);\n\tadapter->old_ifname[IFNAMSIZ - 1] = '\\0';\n\trtw_adapter_proc_init(dev);\n\n\treturn 0;\n}\n\nvoid rtw_ndev_uninit(struct net_device *dev)\n{\n\t_adapter *adapter = rtw_netdev_priv(dev);\n\n\tRTW_PRINT(FUNC_ADPT_FMT\" if%d\\n\"\n\t\t  , FUNC_ADPT_ARG(adapter), (adapter->iface_id + 1));\n\trtw_adapter_proc_deinit(dev);\n}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))\nstatic const struct net_device_ops rtw_netdev_ops = {\n\t.ndo_init = rtw_ndev_init,\n\t.ndo_uninit = rtw_ndev_uninit,\n\t.ndo_open = netdev_open,\n\t.ndo_stop = netdev_close,\n\t.ndo_start_xmit = rtw_xmit_entry,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\t.ndo_select_queue\t= rtw_select_queue,\n#endif\n\t.ndo_set_mac_address = rtw_net_set_mac_address,\n\t.ndo_get_stats = rtw_net_get_stats,\n\t.ndo_do_ioctl = rtw_ioctl,\n};\n#endif\n\nint rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname)\n{\n#ifdef CONFIG_EASY_REPLACEMENT\n\t_adapter *padapter = rtw_netdev_priv(pnetdev);\n\tstruct net_device\t*TargetNetdev = NULL;\n\t_adapter\t\t\t*TargetAdapter = NULL;\n\n\tif (padapter->bDongle == 1) {\n\t\tTargetNetdev = rtw_get_same_net_ndev_by_name(pnetdev, \"wlan0\");\n\t\tif (TargetNetdev) {\n\t\t\tRTW_INFO(\"Force onboard module driver disappear !!!\\n\");\n\t\t\tTargetAdapter = rtw_netdev_priv(TargetNetdev);\n\t\t\tTargetAdapter->DriverState = DRIVER_DISAPPEAR;\n\n\t\t\tpadapter->pid[0] = TargetAdapter->pid[0];\n\t\t\tpadapter->pid[1] = TargetAdapter->pid[1];\n\t\t\tpadapter->pid[2] = TargetAdapter->pid[2];\n\n\t\t\tdev_put(TargetNetdev);\n\t\t\tunregister_netdev(TargetNetdev);\n\n\t\t\tpadapter->DriverState = DRIVER_REPLACE_DONGLE;\n\t\t}\n\t}\n#endif /* CONFIG_EASY_REPLACEMENT */\n\n\tif (dev_alloc_name(pnetdev, ifname) < 0)\n\t\tRTW_ERR(\"dev_alloc_name, fail!\\n\");\n\n\trtw_netif_carrier_off(pnetdev);\n\t/* rtw_netif_stop_queue(pnetdev); */\n\n\treturn 0;\n}\n\nvoid rtw_hook_if_ops(struct net_device *ndev)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))\n\tndev->netdev_ops = &rtw_netdev_ops;\n#else\n\tndev->init = rtw_ndev_init;\n\tndev->uninit = rtw_ndev_uninit;\n\tndev->open = netdev_open;\n\tndev->stop = netdev_close;\n\tndev->hard_start_xmit = rtw_xmit_entry;\n\tndev->set_mac_address = rtw_net_set_mac_address;\n\tndev->get_stats = rtw_net_get_stats;\n\tndev->do_ioctl = rtw_ioctl;\n#endif\n}\n\n#ifdef CONFIG_CONCURRENT_MODE\nstatic void rtw_hook_vir_if_ops(struct net_device *ndev);\n#endif\nstruct net_device *rtw_init_netdev(_adapter *old_padapter)\n{\n\t_adapter *padapter;\n\tstruct net_device *pnetdev;\n\n\tif (old_padapter != NULL) {\n\t\trtw_os_ndev_free(old_padapter);\n\t\tpnetdev = rtw_alloc_etherdev_with_old_priv(sizeof(_adapter), (void *)old_padapter);\n\t} else\n\t\tpnetdev = rtw_alloc_etherdev(sizeof(_adapter));\n\n\tif (!pnetdev)\n\t\treturn NULL;\n\n\tpadapter = rtw_netdev_priv(pnetdev);\n\tpadapter->pnetdev = pnetdev;\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)\n\tSET_MODULE_OWNER(pnetdev);\n#endif\n\n\trtw_hook_if_ops(pnetdev);\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (!is_primary_adapter(padapter))\n\t\trtw_hook_vir_if_ops(pnetdev);\n#endif /* CONFIG_CONCURRENT_MODE */\n\n\n#ifdef CONFIG_TX_CSUM_OFFLOAD\n        pnetdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)\n        pnetdev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);\n#endif\n#endif\n\n#ifdef CONFIG_RTW_NETIF_SG\n        pnetdev->features |= NETIF_F_SG;\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)\n        pnetdev->hw_features |= NETIF_F_SG;\n#endif\n#endif\n\n\tif ((pnetdev->features & NETIF_F_SG) && (pnetdev->features & NETIF_F_IP_CSUM)) {\n\t\tpnetdev->features |= (NETIF_F_TSO | NETIF_F_GSO);\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)\n\t\tpnetdev->hw_features |= (NETIF_F_TSO | NETIF_F_GSO);\n#endif\n\t}\n\t/* pnetdev->tx_timeout = NULL; */\n\tpnetdev->watchdog_timeo = HZ * 3; /* 3 second timeout */\n\n#ifdef CONFIG_WIRELESS_EXT\n\tpnetdev->wireless_handlers = (struct iw_handler_def *)&rtw_handlers_def;\n#endif\n\n#ifdef WIRELESS_SPY\n\t/* priv->wireless_data.spy_data = &priv->spy_data; */\n\t/* pnetdev->wireless_data = &priv->wireless_data; */\n#endif\n\n\treturn pnetdev;\n}\n\nint rtw_os_ndev_alloc(_adapter *adapter)\n{\n\tint ret = _FAIL;\n\tstruct net_device *ndev = NULL;\n\n\tndev = rtw_init_netdev(adapter);\n\tif (ndev == NULL) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)\n\tSET_NETDEV_DEV(ndev, dvobj_to_dev(adapter_to_dvobj(adapter)));\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\tif (adapter_to_dvobj(adapter)->bdma64)\n\t\tndev->features |= NETIF_F_HIGHDMA;\n\tndev->irq = adapter_to_dvobj(adapter)->irq;\n#endif\n\n#if defined(CONFIG_IOCTL_CFG80211)\n\tif (rtw_cfg80211_ndev_res_alloc(adapter) != _SUCCESS) {\n\t\trtw_warn_on(1);\n\t\tgoto free_ndev;\n\t}\n#endif\n\n\tret = _SUCCESS;\n\nfree_ndev:\n\tif (ret != _SUCCESS && ndev)\n\t\trtw_free_netdev(ndev);\nexit:\n\treturn ret;\n}\n\nvoid rtw_os_ndev_free(_adapter *adapter)\n{\n#if defined(CONFIG_IOCTL_CFG80211)\n\trtw_cfg80211_ndev_res_free(adapter);\n#endif\n\n\t/* free the old_pnetdev */\n\tif (adapter->rereg_nd_name_priv.old_pnetdev) {\n\t\trtw_free_netdev(adapter->rereg_nd_name_priv.old_pnetdev);\n\t\tadapter->rereg_nd_name_priv.old_pnetdev = NULL;\n\t}\n\n\tif (adapter->pnetdev) {\n\t\trtw_free_netdev(adapter->pnetdev);\n\t\tadapter->pnetdev = NULL;\n\t}\n}\n\nint rtw_os_ndev_register(_adapter *adapter, const char *name)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tint ret = _SUCCESS;\n\tstruct net_device *ndev = adapter->pnetdev;\n\tu8 rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj);\n\n#ifdef CONFIG_RTW_NAPI\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0))\n\tnetif_napi_add_weight(ndev, &adapter->napi, rtw_recv_napi_poll, RTL_NAPI_WEIGHT);\n#else\n\tnetif_napi_add(ndev, &adapter->napi, rtw_recv_napi_poll, RTL_NAPI_WEIGHT);\n#endif\n#endif /* CONFIG_RTW_NAPI */\n\n#if defined(CONFIG_IOCTL_CFG80211)\n\tif (rtw_cfg80211_ndev_res_register(adapter) != _SUCCESS) {\n\t\trtw_warn_on(1);\n\t\tret = _FAIL;\n\t\tgoto exit;\n\t}\n#endif\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) && defined(CONFIG_PCI_HCI)\n\tndev->gro_flush_timeout = 100000;\n#endif\n\t/* alloc netdev name */\n\trtw_init_netdev_name(ndev, name);\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0))\n\teth_hw_addr_set(ndev, adapter_mac_addr(adapter));\n#else\n\t_rtw_memcpy(ndev->dev_addr, adapter_mac_addr(adapter), ETH_ALEN);\n#endif\n\n\t/* Tell the network stack we exist */\n\n\tif (rtnl_lock_needed)\n\t\tret = (register_netdev(ndev) == 0) ? _SUCCESS : _FAIL;\n\telse\n\t\tret = (register_netdevice(ndev) == 0) ? _SUCCESS : _FAIL;\n\n\tif (ret == _SUCCESS)\n\t\tadapter->registered = 1;\n\telse\n\t\tRTW_INFO(FUNC_NDEV_FMT\" if%d Failed!\\n\", FUNC_NDEV_ARG(ndev), (adapter->iface_id + 1));\n\n#if defined(CONFIG_IOCTL_CFG80211)\n\tif (ret != _SUCCESS) {\n\t\trtw_cfg80211_ndev_res_unregister(adapter);\n\t\t#if !defined(RTW_SINGLE_WIPHY)\n\t\trtw_wiphy_unregister(adapter_to_wiphy(adapter));\n\t\t#endif\n\t}\n#endif\n\nexit:\n#ifdef CONFIG_RTW_NAPI\n\tif (ret != _SUCCESS)\n\t\tnetif_napi_del(&adapter->napi);\n#endif /* CONFIG_RTW_NAPI */\n\n\treturn ret;\n}\n\nvoid rtw_os_ndev_unregister(_adapter *adapter)\n{\n\tstruct net_device *netdev = NULL;\n\n\tif (adapter == NULL || adapter->registered == 0)\n\t\treturn;\n\n\tadapter->ndev_unregistering = 1;\n\n\tnetdev = adapter->pnetdev;\n\n#if defined(CONFIG_IOCTL_CFG80211)\n\trtw_cfg80211_ndev_res_unregister(adapter);\n#endif\n\n\tif ((adapter->DriverState != DRIVER_DISAPPEAR) && netdev) {\n\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\t\tu8 rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj);\n\n\t\tif (rtnl_lock_needed)\n\t\t\tunregister_netdev(netdev);\n\t\telse\n\t\t\tunregister_netdevice(netdev);\n\t}\n\n#if defined(CONFIG_IOCTL_CFG80211) && !defined(RTW_SINGLE_WIPHY)\n#ifdef CONFIG_RFKILL_POLL\n\trtw_cfg80211_deinit_rfkill(adapter_to_wiphy(adapter));\n#endif\n\trtw_wiphy_unregister(adapter_to_wiphy(adapter));\n#endif\n\n#ifdef CONFIG_RTW_NAPI\n\tif (adapter->napi_state == NAPI_ENABLE) {\n\t\tnapi_disable(&adapter->napi);\n\t\tadapter->napi_state = NAPI_DISABLE;\n\t}\n\tnetif_napi_del(&adapter->napi);\n#endif /* CONFIG_RTW_NAPI */\n\n\tadapter->registered = 0;\n\tadapter->ndev_unregistering = 0;\n}\n\n/**\n * rtw_os_ndev_init - Allocate and register OS layer net device and relating structures for @adapter\n * @adapter: the adapter on which this function applies\n * @name: the requesting net device name\n *\n * Returns:\n * _SUCCESS or _FAIL\n */\nint rtw_os_ndev_init(_adapter *adapter, const char *name)\n{\n\tint ret = _FAIL;\n\n\tif (rtw_os_ndev_alloc(adapter) != _SUCCESS)\n\t\tgoto exit;\n\n\tif (rtw_os_ndev_register(adapter, name) != _SUCCESS)\n\t\tgoto os_ndev_free;\n\n\tret = _SUCCESS;\n\nos_ndev_free:\n\tif (ret != _SUCCESS)\n\t\trtw_os_ndev_free(adapter);\nexit:\n\treturn ret;\n}\n\n/**\n * rtw_os_ndev_deinit - Unregister and free OS layer net device and relating structures for @adapter\n * @adapter: the adapter on which this function applies\n */\nvoid rtw_os_ndev_deinit(_adapter *adapter)\n{\n\trtw_os_ndev_unregister(adapter);\n\trtw_os_ndev_free(adapter);\n}\n\nint rtw_os_ndevs_alloc(struct dvobj_priv *dvobj)\n{\n\tint i, status = _SUCCESS;\n\t_adapter *adapter;\n\n#if defined(CONFIG_IOCTL_CFG80211)\n\tif (rtw_cfg80211_dev_res_alloc(dvobj) != _SUCCESS) {\n\t\trtw_warn_on(1);\n\t\tstatus = _FAIL;\n\t\tgoto exit;\n\t}\n#endif\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\n\t\tif (i >= CONFIG_IFACE_NUMBER) {\n\t\t\tRTW_ERR(\"%s %d >= CONFIG_IFACE_NUMBER(%d)\\n\", __func__, i, CONFIG_IFACE_NUMBER);\n\t\t\trtw_warn_on(1);\n\t\t\tcontinue;\n\t\t}\n\n\t\tadapter = dvobj->padapters[i];\n\t\tif (adapter && !adapter->pnetdev) {\n\n\t\t\t#ifdef CONFIG_RTW_DYNAMIC_NDEV\n\t\t\tif (!is_primary_adapter(adapter))\n\t\t\t\tcontinue;\n\t\t\t#endif\n\n\t\t\tstatus = rtw_os_ndev_alloc(adapter);\n\t\t\tif (status != _SUCCESS) {\n\t\t\t\trtw_warn_on(1);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (status != _SUCCESS) {\n\t\tfor (; i >= 0; i--) {\n\t\t\tadapter = dvobj->padapters[i];\n\t\t\tif (adapter && adapter->pnetdev)\n\t\t\t\trtw_os_ndev_free(adapter);\n\t\t}\n\t}\n\n#if defined(CONFIG_IOCTL_CFG80211)\n\tif (status != _SUCCESS)\n\t\trtw_cfg80211_dev_res_free(dvobj);\n#endif\nexit:\n\treturn status;\n}\n\nvoid rtw_os_ndevs_free(struct dvobj_priv *dvobj)\n{\n\tint i;\n\t_adapter *adapter = NULL;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\n\t\tif (i >= CONFIG_IFACE_NUMBER) {\n\t\t\tRTW_ERR(\"%s %d >= CONFIG_IFACE_NUMBER(%d)\\n\", __func__, i, CONFIG_IFACE_NUMBER);\n\t\t\trtw_warn_on(1);\n\t\t\tcontinue;\n\t\t}\n\n\t\tadapter = dvobj->padapters[i];\n\n\t\tif (adapter == NULL)\n\t\t\tcontinue;\n\n\t\trtw_os_ndev_free(adapter);\n\t}\n\n#if defined(CONFIG_IOCTL_CFG80211)\n\trtw_cfg80211_dev_res_free(dvobj);\n#endif\n}\n\nu32 rtw_start_drv_threads(_adapter *padapter)\n{\n\tu32 _status = _SUCCESS;\n\n\tRTW_INFO(FUNC_ADPT_FMT\" enter\\n\", FUNC_ADPT_ARG(padapter));\n\n#ifdef CONFIG_XMIT_THREAD_MODE\n#if defined(CONFIG_SDIO_HCI)\n\tif (is_primary_adapter(padapter))\n#endif\n\t{\n\t\tif (padapter->xmitThread == NULL) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \" start RTW_XMIT_THREAD\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\tpadapter->xmitThread = kthread_run(rtw_xmit_thread, padapter, \"RTW_XMIT_THREAD\");\n\t\t\tif (IS_ERR(padapter->xmitThread)) {\n\t\t\t\tpadapter->xmitThread = NULL;\n\t\t\t\t_status = _FAIL;\n\t\t\t}\n\t\t}\n\t}\n#endif /* #ifdef CONFIG_XMIT_THREAD_MODE */\n\n#ifdef CONFIG_RECV_THREAD_MODE\n\tif (is_primary_adapter(padapter)) {\n\t\tif (padapter->recvThread == NULL) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \" start RTW_RECV_THREAD\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\tpadapter->recvThread = kthread_run(rtw_recv_thread, padapter, \"RTW_RECV_THREAD\");\n\t\t\tif (IS_ERR(padapter->recvThread)) {\n\t\t\t\tpadapter->recvThread = NULL;\n\t\t\t\t_status = _FAIL;\n\t\t\t}\n\t\t}\n\t}\n#endif\n\n\tif (is_primary_adapter(padapter)) {\n\t\tif (padapter->cmdThread == NULL) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \" start RTW_CMD_THREAD\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\tpadapter->cmdThread = kthread_run(rtw_cmd_thread, padapter, \"RTW_CMD_THREAD\");\n\t\t\tif (IS_ERR(padapter->cmdThread)) {\n\t\t\t\tpadapter->cmdThread = NULL;\n\t\t\t\t_status = _FAIL;\n\t\t\t}\n\t\t\telse\n\t\t\t\t_rtw_down_sema(&padapter->cmdpriv.start_cmdthread_sema); /* wait for cmd_thread to run */\n\t\t}\n\t}\n\n\n#ifdef CONFIG_EVENT_THREAD_MODE\n\tif (padapter->evtThread == NULL) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \" start RTW_EVENT_THREAD\\n\", FUNC_ADPT_ARG(padapter));\n\t\tpadapter->evtThread = kthread_run(event_thread, padapter, \"RTW_EVENT_THREAD\");\n\t\tif (IS_ERR(padapter->evtThread)) {\n\t\t\tpadapter->evtThread = NULL;\n\t\t\t_status = _FAIL;\n\t\t}\n\t}\n#endif\n\n\trtw_hal_start_thread(padapter);\n\treturn _status;\n\n}\n\nvoid rtw_stop_drv_threads(_adapter *padapter)\n{\n\tRTW_INFO(FUNC_ADPT_FMT\" enter\\n\", FUNC_ADPT_ARG(padapter));\n\tif (is_primary_adapter(padapter))\n\t\trtw_stop_cmd_thread(padapter);\n\n#ifdef CONFIG_EVENT_THREAD_MODE\n\tif (padapter->evtThread) {\n\t\t_rtw_up_sema(&padapter->evtpriv.evt_notify);\n\t\trtw_thread_stop(padapter->evtThread);\n\t\tpadapter->evtThread = NULL;\n\t}\n#endif\n\n#ifdef CONFIG_XMIT_THREAD_MODE\n\t/* Below is to termindate tx_thread... */\n#if defined(CONFIG_SDIO_HCI)\n\t/* Only wake-up primary adapter */\n\tif (is_primary_adapter(padapter))\n#endif  /*SDIO_HCI */\n\t{\n\t\tif (padapter->xmitThread) {\n\t\t\t_rtw_up_sema(&padapter->xmitpriv.xmit_sema);\n\t\t\trtw_thread_stop(padapter->xmitThread);\n\t\t\tpadapter->xmitThread = NULL;\n\t\t}\n\t}\n#endif\n\n#ifdef CONFIG_RECV_THREAD_MODE\n\tif (is_primary_adapter(padapter) && padapter->recvThread) {\n\t\t/* Below is to termindate rx_thread... */\n\t\t_rtw_up_sema(&padapter->recvpriv.recv_sema);\n\t\trtw_thread_stop(padapter->recvThread);\n\t\tpadapter->recvThread = NULL;\n\t}\n#endif\n\n\trtw_hal_stop_thread(padapter);\n}\n\nu8 rtw_init_default_value(_adapter *padapter)\n{\n\tu8 ret  = _SUCCESS;\n\tstruct registry_priv *pregistrypriv = &padapter->registrypriv;\n\tstruct xmit_priv\t*pxmitpriv = &padapter->xmitpriv;\n\tstruct security_priv *psecuritypriv = &padapter->securitypriv;\n\n\t/* xmit_priv */\n\tpxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense;\n\tpxmitpriv->vcs = pregistrypriv->vcs_type;\n\tpxmitpriv->vcs_type = pregistrypriv->vcs_type;\n\t/* pxmitpriv->rts_thresh = pregistrypriv->rts_thresh; */\n\tpxmitpriv->frag_len = pregistrypriv->frag_thresh;\n\n\t/* security_priv */\n\t/* rtw_get_encrypt_decrypt_from_registrypriv(padapter); */\n\tpsecuritypriv->binstallGrpkey = _FAIL;\n#ifdef CONFIG_GTK_OL\n\tpsecuritypriv->binstallKCK_KEK = _FAIL;\n#endif /* CONFIG_GTK_OL */\n\tpsecuritypriv->sw_encrypt = pregistrypriv->software_encrypt;\n\tpsecuritypriv->sw_decrypt = pregistrypriv->software_decrypt;\n\n\tpsecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */\n\tpsecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;\n\n\tpsecuritypriv->dot11PrivacyKeyIndex = 0;\n\n\tpsecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;\n\tpsecuritypriv->dot118021XGrpKeyid = 1;\n\n\tpsecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;\n\tpsecuritypriv->ndisencryptstatus = Ndis802_11WEPDisabled;\n#ifdef CONFIG_CONCURRENT_MODE\n\tpsecuritypriv->dot118021x_bmc_cam_id = INVALID_SEC_MAC_CAM_ID;\n#endif\n\n\n\t/* pwrctrl_priv */\n\n\n\t/* registry_priv */\n\trtw_init_registrypriv_dev_network(padapter);\n\trtw_update_registrypriv_dev_network(padapter);\n\n\n\t/* hal_priv */\n\trtw_hal_def_value_init(padapter);\n\n#ifdef CONFIG_MCC_MODE\n\t/* MCC parameter */\n\trtw_hal_mcc_parameter_init(padapter);\n#endif /* CONFIG_MCC_MODE */\n\n\t/* misc. */\n\tRTW_ENABLE_FUNC(padapter, DF_RX_BIT);\n\tRTW_ENABLE_FUNC(padapter, DF_TX_BIT);\n\tpadapter->bLinkInfoDump = 0;\n\tpadapter->bNotifyChannelChange = _FALSE;\n#ifdef CONFIG_P2P\n\tpadapter->bShowGetP2PState = 1;\n#endif\n\n\t/* for debug purpose */\n\tpadapter->fix_rate = 0xFF;\n\tpadapter->data_fb = 0;\n\tpadapter->fix_bw = 0xFF;\n\tpadapter->power_offset = 0;\n\tpadapter->rsvd_page_offset = 0;\n\tpadapter->rsvd_page_num = 0;\n#ifdef CONFIG_AP_MODE\n\tpadapter->bmc_tx_rate = pregistrypriv->bmc_tx_rate;\n#endif\n\tpadapter->driver_tx_bw_mode = pregistrypriv->tx_bw_mode;\n\n\tpadapter->driver_ampdu_spacing = 0xFF;\n\tpadapter->driver_rx_ampdu_factor =  0xFF;\n\tpadapter->driver_rx_ampdu_spacing = 0xFF;\n\tpadapter->fix_rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID;\n\tpadapter->fix_rx_ampdu_size = RX_AMPDU_SIZE_INVALID;\n#ifdef CONFIG_TX_AMSDU\n\tpadapter->tx_amsdu = 2;\n\tpadapter->tx_amsdu_rate = 400;\n#endif\n\tpadapter->driver_tx_max_agg_num = 0xFF;\n#ifdef DBG_RX_COUNTER_DUMP\n\tpadapter->dump_rx_cnt_mode = 0;\n\tpadapter->drv_rx_cnt_ok = 0;\n\tpadapter->drv_rx_cnt_crcerror = 0;\n\tpadapter->drv_rx_cnt_drop = 0;\n#endif\n#ifdef CONFIG_RTW_NAPI\n\tpadapter->napi_state = NAPI_DISABLE;\n#endif\n\n#ifdef CONFIG_RTW_ACS\n\tif (pregistrypriv->acs_mode)\n\t\trtw_acs_start(padapter);\n\telse\n\t\trtw_acs_stop(padapter);\n#endif\n#ifdef CONFIG_BACKGROUND_NOISE_MONITOR\n\tif (pregistrypriv->nm_mode)\n\t\trtw_nm_enable(padapter);\n\telse\n\t\trtw_nm_disable(padapter);\n#endif\n\treturn ret;\n}\n#ifdef CONFIG_CLIENT_PORT_CFG\nextern void rtw_clt_port_init(struct clt_port_t  *cltp);\nextern void rtw_clt_port_deinit(struct clt_port_t  *cltp);\n#endif\n\nstruct dvobj_priv *devobj_init(void)\n{\n\tstruct dvobj_priv *pdvobj = NULL;\n\n\tpdvobj = (struct dvobj_priv *)rtw_zmalloc(sizeof(*pdvobj));\n\tif (pdvobj == NULL)\n\t\treturn NULL;\n\n\t_rtw_mutex_init(&pdvobj->hw_init_mutex);\n\t_rtw_mutex_init(&pdvobj->h2c_fwcmd_mutex);\n\t_rtw_mutex_init(&pdvobj->setch_mutex);\n\t_rtw_mutex_init(&pdvobj->setbw_mutex);\n\t_rtw_mutex_init(&pdvobj->rf_read_reg_mutex);\n\t_rtw_mutex_init(&pdvobj->ioctrl_mutex);\n#ifdef CONFIG_SDIO_INDIRECT_ACCESS\n\t_rtw_mutex_init(&pdvobj->sd_indirect_access_mutex);\n#endif\n#ifdef CONFIG_SYSON_INDIRECT_ACCESS\n\t_rtw_mutex_init(&pdvobj->syson_indirect_access_mutex);\n#endif\n#ifdef CONFIG_RTW_CUSTOMER_STR\n\t_rtw_mutex_init(&pdvobj->customer_str_mutex);\n\t_rtw_memset(pdvobj->customer_str, 0xFF, RTW_CUSTOMER_STR_LEN);\n#endif\n\n\tpdvobj->processing_dev_remove = _FALSE;\n\n\tATOMIC_SET(&pdvobj->disable_func, 0);\n\n\trtw_macid_ctl_init(&pdvobj->macid_ctl);\n#ifdef CONFIG_CLIENT_PORT_CFG\n\trtw_clt_port_init(&pdvobj->clt_port);\n#endif\n\t_rtw_spinlock_init(&pdvobj->cam_ctl.lock);\n\t_rtw_mutex_init(&pdvobj->cam_ctl.sec_cam_access_mutex);\n#if defined(RTK_129X_PLATFORM) && defined(CONFIG_PCI_HCI)\n\t_rtw_spinlock_init(&pdvobj->io_reg_lock);\n#endif\n#ifdef CONFIG_MBSSID_CAM\n\trtw_mbid_cam_init(pdvobj);\n#endif\n\n#ifdef CONFIG_AP_MODE\n\t#ifdef CONFIG_SUPPORT_MULTI_BCN\n\tpdvobj->nr_ap_if = 0;\n\tpdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL; /* default value is equal to the default beacon_interval (100ms) */\n\t_rtw_init_queue(&pdvobj->ap_if_q);\n\tpdvobj->vap_map = 0;\n\t#endif /*CONFIG_SUPPORT_MULTI_BCN*/\n\t#ifdef CONFIG_SWTIMER_BASED_TXBCN\n\trtw_init_timer(&(pdvobj->txbcn_timer), NULL, tx_beacon_timer_handlder, pdvobj);\n\t#endif\n#endif\n\n\trtw_init_timer(&(pdvobj->dynamic_chk_timer), NULL, rtw_dynamic_check_timer_handlder, pdvobj);\n\trtw_init_timer(&(pdvobj->periodic_tsf_update_end_timer), NULL, rtw_hal_periodic_tsf_update_end_timer_hdl, pdvobj);\n\n#ifdef CONFIG_MCC_MODE\n\t_rtw_mutex_init(&(pdvobj->mcc_objpriv.mcc_mutex));\n\t_rtw_mutex_init(&(pdvobj->mcc_objpriv.mcc_tsf_req_mutex));\n\t_rtw_mutex_init(&(pdvobj->mcc_objpriv.mcc_dbg_reg_mutex));\n\t_rtw_spinlock_init(&pdvobj->mcc_objpriv.mcc_lock);\n#endif /* CONFIG_MCC_MODE */\n\n#ifdef CONFIG_RTW_NAPI_DYNAMIC\n\tpdvobj->en_napi_dynamic = 0;\n#endif /* CONFIG_RTW_NAPI_DYNAMIC */\n\n\n#ifdef CONFIG_RTW_TPT_MODE\n\tpdvobj->tpt_mode = 0;\n\tpdvobj->edca_be_ul = 0x5ea42b;\n\tpdvobj->edca_be_dl = 0x00a42b;\n#endif \n\tpdvobj->scan_deny = _FALSE;\n\n\treturn pdvobj;\n\n}\n\nvoid devobj_deinit(struct dvobj_priv *pdvobj)\n{\n\tif (!pdvobj)\n\t\treturn;\n\n\t/* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */\n#if defined(CONFIG_IOCTL_CFG80211)\n\trtw_cfg80211_dev_res_free(pdvobj);\n#endif\n\n#ifdef CONFIG_MCC_MODE\n\t_rtw_mutex_free(&(pdvobj->mcc_objpriv.mcc_mutex));\n\t_rtw_mutex_free(&(pdvobj->mcc_objpriv.mcc_tsf_req_mutex));\n\t_rtw_mutex_free(&(pdvobj->mcc_objpriv.mcc_dbg_reg_mutex));\n\t_rtw_spinlock_free(&pdvobj->mcc_objpriv.mcc_lock);\n#endif /* CONFIG_MCC_MODE */\n\n\t_rtw_mutex_free(&pdvobj->hw_init_mutex);\n\t_rtw_mutex_free(&pdvobj->h2c_fwcmd_mutex);\n\n#ifdef CONFIG_RTW_CUSTOMER_STR\n\t_rtw_mutex_free(&pdvobj->customer_str_mutex);\n#endif\n\n\t_rtw_mutex_free(&pdvobj->setch_mutex);\n\t_rtw_mutex_free(&pdvobj->setbw_mutex);\n\t_rtw_mutex_free(&pdvobj->rf_read_reg_mutex);\n\t_rtw_mutex_free(&pdvobj->ioctrl_mutex);\n#ifdef CONFIG_SDIO_INDIRECT_ACCESS\n\t_rtw_mutex_free(&pdvobj->sd_indirect_access_mutex);\n#endif\n#ifdef CONFIG_SYSON_INDIRECT_ACCESS\n\t_rtw_mutex_free(&pdvobj->syson_indirect_access_mutex);\n#endif\n\n\trtw_macid_ctl_deinit(&pdvobj->macid_ctl);\n#ifdef CONFIG_CLIENT_PORT_CFG\n\trtw_clt_port_deinit(&pdvobj->clt_port);\n#endif\n\n\t_rtw_spinlock_free(&pdvobj->cam_ctl.lock);\n\t_rtw_mutex_free(&pdvobj->cam_ctl.sec_cam_access_mutex);\n\n#if defined(RTK_129X_PLATFORM) && defined(CONFIG_PCI_HCI)\n\t_rtw_spinlock_free(&pdvobj->io_reg_lock);\n#endif\n#ifdef CONFIG_MBSSID_CAM\n\trtw_mbid_cam_deinit(pdvobj);\n#endif\n#ifdef CONFIG_SUPPORT_MULTI_BCN\n\t_rtw_spinlock_free(&(pdvobj->ap_if_q.lock));\n#endif\n\trtw_mfree((u8 *)pdvobj, sizeof(*pdvobj));\n}\n\ninline u8 rtw_rtnl_lock_needed(struct dvobj_priv *dvobj)\n{\n\tif (dvobj->rtnl_lock_holder && dvobj->rtnl_lock_holder == current)\n\t\treturn 0;\n\treturn 1;\n}\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))\nstatic inline int rtnl_is_locked(void)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 17))\n\tif (unlikely(rtnl_trylock())) {\n\t\trtnl_unlock();\n#else\n\tif (unlikely(down_trylock(&rtnl_sem) == 0)) {\n\t\tup(&rtnl_sem);\n#endif\n\t\treturn 0;\n\t}\n\treturn 1;\n}\n#endif\n\ninline void rtw_set_rtnl_lock_holder(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl)\n{\n\trtw_warn_on(!rtnl_is_locked());\n\n\tif (!thd_hdl || rtnl_is_locked())\n\t\tdvobj->rtnl_lock_holder = thd_hdl;\n\n\tif (dvobj->rtnl_lock_holder && 0)\n\t\tRTW_INFO(\"rtnl_lock_holder: %s:%d\\n\", current->comm, current->pid);\n}\n\nu8 rtw_reset_drv_sw(_adapter *padapter)\n{\n\tu8\tret8 = _SUCCESS;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n\n\t/* hal_priv */\n\trtw_hal_def_value_init(padapter);\n\n\tRTW_ENABLE_FUNC(padapter, DF_RX_BIT);\n\tRTW_ENABLE_FUNC(padapter, DF_TX_BIT);\n\n\tpadapter->bLinkInfoDump = 0;\n\n\tpadapter->xmitpriv.tx_pkts = 0;\n\tpadapter->recvpriv.rx_pkts = 0;\n\n\tpmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;\n\n\t/* pmlmepriv->LinkDetectInfo.TrafficBusyState = _FALSE; */\n\tpmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0;\n\tpmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0;\n\n\t_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING);\n\n#ifdef CONFIG_AUTOSUSPEND\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 34))\n\tadapter_to_dvobj(padapter)->pusbdev->autosuspend_disabled = 1;/* autosuspend disabled by the user */\n#endif\n#endif\n\n#ifdef DBG_CONFIG_ERROR_DETECT\n\tif (is_primary_adapter(padapter))\n\t\trtw_hal_sreset_reset_value(padapter);\n#endif\n\tpwrctrlpriv->pwr_state_check_cnts = 0;\n\n\t/* mlmeextpriv */\n\tmlmeext_set_scan_state(&padapter->mlmeextpriv, SCAN_DISABLE);\n\n#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS\n\trtw_set_signal_stat_timer(&padapter->recvpriv);\n#endif\n\n\treturn ret8;\n}\n\n\nu8 rtw_init_drv_sw(_adapter *padapter)\n{\n\tu8\tret8 = _SUCCESS;\n\n#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n#endif\n\n\t#if defined(CONFIG_AP_MODE) && defined(CONFIG_SUPPORT_MULTI_BCN)\n\t_rtw_init_listhead(&padapter->list);\n\t#ifdef CONFIG_FW_HANDLE_TXBCN\n\tpadapter->vap_id = CONFIG_LIMITED_AP_NUM;\n\tif (is_primary_adapter(padapter))\n\t\tadapter_to_dvobj(padapter)->vap_tbtt_rpt_map = adapter_to_regsty(padapter)->fw_tbtt_rpt;\n\t#endif\n\t#endif\n\n\t#ifdef CONFIG_CLIENT_PORT_CFG\n\tpadapter->client_id = MAX_CLIENT_PORT_NUM;\n\tpadapter->client_port = CLT_PORT_INVALID;\n\t#endif\n\n\tif (is_primary_adapter(padapter)) {\n\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\t\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);\n\n\t\tdvobj->macid_ctl.num = rtw_min(hal_spec->macid_num, MACID_NUM_SW_LIMIT);\n\n\t\tdvobj->cam_ctl.sec_cap = hal_spec->sec_cap;\n\t\tdvobj->cam_ctl.num = rtw_min(hal_spec->sec_cam_ent_num, SEC_CAM_ENT_NUM_SW_LIMIT);\n\n\t\t#if CONFIG_TX_AC_LIFETIME\n\t\t{\n\t\t\tstruct registry_priv *regsty = adapter_to_regsty(padapter);\n\t\t\tint i;\n\n\t\t\tdvobj->tx_aclt_flags = regsty->tx_aclt_flags;\n\t\t\tfor (i = 0; i < TX_ACLT_CONF_NUM; i++) {\n\t\t\t\tdvobj->tx_aclt_confs[i].en = regsty->tx_aclt_confs[i].en;\n\t\t\t\tdvobj->tx_aclt_confs[i].vo_vi\n\t\t\t\t\t= regsty->tx_aclt_confs[i].vo_vi / (hal_spec->tx_aclt_unit_factor * 32);\n\t\t\t\tif (dvobj->tx_aclt_confs[i].vo_vi > 0xFFFF)\n\t\t\t\t\tdvobj->tx_aclt_confs[i].vo_vi = 0xFFFF;\n\t\t\t\tdvobj->tx_aclt_confs[i].be_bk\n\t\t\t\t\t= regsty->tx_aclt_confs[i].be_bk / (hal_spec->tx_aclt_unit_factor * 32);\n\t\t\t\tif (dvobj->tx_aclt_confs[i].be_bk > 0xFFFF)\n\t\t\t\t\tdvobj->tx_aclt_confs[i].be_bk = 0xFFFF;\n\t\t\t}\n\n\t\t\tdvobj->tx_aclt_force_val.en = 0xFF;\n\t\t}\n\t\t#endif\n\t}\n\n\tret8 = rtw_init_default_value(padapter);\n\n\tif ((rtw_init_cmd_priv(&padapter->cmdpriv)) == _FAIL) {\n\t\tret8 = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpadapter->cmdpriv.padapter = padapter;\n\n\tif ((rtw_init_evt_priv(&padapter->evtpriv)) == _FAIL) {\n\t\tret8 = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tif (is_primary_adapter(padapter))\n\t\trtw_rfctl_init(padapter);\n\n\tif (rtw_init_mlme_priv(padapter) == _FAIL) {\n\t\tret8 = _FAIL;\n\t\tgoto exit;\n\t}\n\n#ifdef CONFIG_P2P\n\trtw_init_wifidirect_timers(padapter);\n\tinit_wifidirect_info(padapter, P2P_ROLE_DISABLE);\n\treset_global_wifidirect_info(padapter);\n\t#ifdef CONFIG_IOCTL_CFG80211\n\trtw_init_cfg80211_wifidirect_info(padapter);\n\t#endif\n#ifdef CONFIG_WFD\n\tif (rtw_init_wifi_display_info(padapter) == _FAIL)\n\t\tRTW_ERR(\"Can't init init_wifi_display_info\\n\");\n#endif\n#endif /* CONFIG_P2P */\n\n\tif (init_mlme_ext_priv(padapter) == _FAIL) {\n\t\tret8 = _FAIL;\n\t\tgoto exit;\n\t}\n\n#ifdef CONFIG_TDLS\n\tif (rtw_init_tdls_info(padapter) == _FAIL) {\n\t\tRTW_INFO(\"Can't rtw_init_tdls_info\\n\");\n\t\tret8 = _FAIL;\n\t\tgoto exit;\n\t}\n#endif /* CONFIG_TDLS */\n\n#ifdef CONFIG_RTW_MESH\n\trtw_mesh_cfg_init(padapter);\n#endif\n\n\tif (_rtw_init_xmit_priv(&padapter->xmitpriv, padapter) == _FAIL) {\n\t\tRTW_INFO(\"Can't _rtw_init_xmit_priv\\n\");\n\t\tret8 = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tif (_rtw_init_recv_priv(&padapter->recvpriv, padapter) == _FAIL) {\n\t\tRTW_INFO(\"Can't _rtw_init_recv_priv\\n\");\n\t\tret8 = _FAIL;\n\t\tgoto exit;\n\t}\n\t/* add for CONFIG_IEEE80211W, none 11w also can use */\n\t_rtw_spinlock_init(&padapter->security_key_mutex);\n\n\t/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */\n\t/* _rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof (struct security_priv)); */\n\n\tif (_rtw_init_sta_priv(&padapter->stapriv) == _FAIL) {\n\t\tRTW_INFO(\"Can't _rtw_init_sta_priv\\n\");\n\t\tret8 = _FAIL;\n\t\tgoto exit;\n\t}\n\n\tpadapter->setband = WIFI_FREQUENCY_BAND_AUTO;\n\tpadapter->fix_rate = 0xFF;\n\tpadapter->power_offset = 0;\n\tpadapter->rsvd_page_offset = 0;\n\tpadapter->rsvd_page_num = 0;\n\n\tpadapter->data_fb = 0;\n\tpadapter->fix_rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID;\n\tpadapter->fix_rx_ampdu_size = RX_AMPDU_SIZE_INVALID;\n#ifdef DBG_RX_COUNTER_DUMP\n\tpadapter->dump_rx_cnt_mode = 0;\n\tpadapter->drv_rx_cnt_ok = 0;\n\tpadapter->drv_rx_cnt_crcerror = 0;\n\tpadapter->drv_rx_cnt_drop = 0;\n#endif\n\trtw_init_bcmc_stainfo(padapter);\n\n\trtw_init_pwrctrl_priv(padapter);\n\n\t/* _rtw_memset((u8 *)&padapter->qospriv, 0, sizeof (struct qos_priv)); */ /* move to mlme_priv */\n\n#ifdef CONFIG_MP_INCLUDED\n\tif (init_mp_priv(padapter) == _FAIL)\n\t\tRTW_INFO(\"%s: initialize MP private data Fail!\\n\", __func__);\n#endif\n\n\trtw_hal_dm_init(padapter);\n#ifdef CONFIG_RTW_SW_LED\n\trtw_hal_sw_led_init(padapter);\n#endif\n#ifdef DBG_CONFIG_ERROR_DETECT\n\trtw_hal_sreset_init(padapter);\n#endif\n\n#ifdef CONFIG_WAPI_SUPPORT\n\tpadapter->WapiSupport = true; /* set true temp, will revise according to Efuse or Registry value later. */\n\trtw_wapi_init(padapter);\n#endif\n\n#ifdef CONFIG_BR_EXT\n\t_rtw_spinlock_init(&padapter->br_ext_lock);\n#endif /* CONFIG_BR_EXT */\n\n#ifdef CONFIG_BEAMFORMING\n#ifdef RTW_BEAMFORMING_VERSION_2\n\trtw_bf_init(padapter);\n#endif /* RTW_BEAMFORMING_VERSION_2 */\n#endif /* CONFIG_BEAMFORMING */\n\n#ifdef CONFIG_RTW_REPEATER_SON\n\tinit_rtw_rson_data(adapter_to_dvobj(padapter));\n#endif\n\n#ifdef CONFIG_RTW_80211K\n\trtw_init_rm(padapter);\n#endif\n\n#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI\n\tmemset(pwdev_priv->pno_mac_addr, 0xFF, ETH_ALEN);\n#endif\n\nexit:\n\n\n\n\treturn ret8;\n\n}\n\n#ifdef CONFIG_WOWLAN\nvoid rtw_cancel_dynamic_chk_timer(_adapter *padapter)\n{\n\t_cancel_timer_ex(&adapter_to_dvobj(padapter)->dynamic_chk_timer);\n}\n#endif\n\nvoid rtw_cancel_all_timer(_adapter *padapter)\n{\n\n\t_cancel_timer_ex(&padapter->mlmepriv.assoc_timer);\n\n\t_cancel_timer_ex(&padapter->mlmepriv.scan_to_timer);\n\n#ifdef CONFIG_DFS_MASTER\n\t_cancel_timer_ex(&adapter_to_rfctl(padapter)->radar_detect_timer);\n#endif\n\n\t_cancel_timer_ex(&adapter_to_dvobj(padapter)->dynamic_chk_timer);\n\t_cancel_timer_ex(&adapter_to_dvobj(padapter)->periodic_tsf_update_end_timer);\n#ifdef CONFIG_RTW_SW_LED\n\t/* cancel sw led timer */\n\trtw_hal_sw_led_deinit(padapter);\n#endif\n\t_cancel_timer_ex(&(adapter_to_pwrctl(padapter)->pwr_state_check_timer));\n\n#ifdef CONFIG_TX_AMSDU\n\t_cancel_timer_ex(&padapter->xmitpriv.amsdu_bk_timer);\n\t_cancel_timer_ex(&padapter->xmitpriv.amsdu_be_timer);\n\t_cancel_timer_ex(&padapter->xmitpriv.amsdu_vo_timer);\n\t_cancel_timer_ex(&padapter->xmitpriv.amsdu_vi_timer);\n#endif\n\n#ifdef CONFIG_IOCTL_CFG80211\n#ifdef CONFIG_P2P\n\t_cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer);\n#endif /* CONFIG_P2P */\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n#ifdef CONFIG_SET_SCAN_DENY_TIMER\n\t_cancel_timer_ex(&padapter->mlmepriv.set_scan_deny_timer);\n\trtw_clear_scan_deny(padapter);\n#endif\n\n#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS\n\t_cancel_timer_ex(&padapter->recvpriv.signal_stat_timer);\n#endif\n\n#ifdef CONFIG_LPS_RPWM_TIMER\n\t_cancel_timer_ex(&(adapter_to_pwrctl(padapter)->pwr_rpwm_timer));\n#endif /* CONFIG_LPS_RPWM_TIMER */\n\n\t/* cancel dm timer */\n\trtw_hal_dm_deinit(padapter);\n\n#ifdef CONFIG_PLATFORM_FS_MX61\n\tmsleep(50);\n#endif\n}\n\nu8 rtw_free_drv_sw(_adapter *padapter)\n{\n\n#ifdef CONFIG_WAPI_SUPPORT\n\trtw_wapi_free(padapter);\n#endif\n\n\t/* we can call rtw_p2p_enable here, but: */\n\t/* 1. rtw_p2p_enable may have IO operation */\n\t/* 2. rtw_p2p_enable is bundled with wext interface */\n\t#ifdef CONFIG_P2P\n\t{\n\t\tstruct wifidirect_info *pwdinfo = &padapter->wdinfo;\n\t\tif (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {\n\t\t\t_cancel_timer_ex(&pwdinfo->find_phase_timer);\n\t\t\t_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);\n\t\t\t_cancel_timer_ex(&pwdinfo->pre_tx_scan_timer);\n\t\t\t#ifdef CONFIG_CONCURRENT_MODE\n\t\t\t_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);\n\t\t\t#endif /* CONFIG_CONCURRENT_MODE */\n\t\t\trtw_p2p_set_state(pwdinfo, P2P_STATE_NONE);\n\t\t}\n\t}\n\t#endif\n\t/* add for CONFIG_IEEE80211W, none 11w also can use */\n\t_rtw_spinlock_free(&padapter->security_key_mutex);\n\n#ifdef CONFIG_BR_EXT\n\t_rtw_spinlock_free(&padapter->br_ext_lock);\n#endif /* CONFIG_BR_EXT */\n\n\tfree_mlme_ext_priv(&padapter->mlmeextpriv);\n\n#ifdef CONFIG_TDLS\n\t/* rtw_free_tdls_info(&padapter->tdlsinfo); */\n#endif /* CONFIG_TDLS */\n\n#ifdef CONFIG_RTW_80211K\n\trtw_free_rm_priv(padapter);\n#endif\n\n\trtw_free_cmd_priv(&padapter->cmdpriv);\n\n\trtw_free_evt_priv(&padapter->evtpriv);\n\n\trtw_free_mlme_priv(&padapter->mlmepriv);\n\n\tif (is_primary_adapter(padapter))\n\t\trtw_rfctl_deinit(padapter);\n\n\t/* free_io_queue(padapter); */\n\n\t_rtw_free_xmit_priv(&padapter->xmitpriv);\n\n\t_rtw_free_sta_priv(&padapter->stapriv); /* will free bcmc_stainfo here */\n\n\t_rtw_free_recv_priv(&padapter->recvpriv);\n\n\trtw_free_pwrctrl_priv(padapter);\n\n\t/* rtw_mfree((void *)padapter, sizeof (padapter)); */\n\n\trtw_hal_free_data(padapter);\n\n\treturn _SUCCESS;\n\n}\nvoid rtw_intf_start(_adapter *adapter)\n{\n\tif (adapter->intf_start)\n\t\tadapter->intf_start(adapter);\n}\nvoid rtw_intf_stop(_adapter *adapter)\n{\n\tif (adapter->intf_stop)\n\t\tadapter->intf_stop(adapter);\n}\n\n#ifdef CONFIG_CONCURRENT_MODE\n#ifndef CONFIG_NEW_NETDEV_HDL\nint _netdev_vir_if_open(struct net_device *pnetdev)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);\n\t_adapter *primary_padapter = GET_PRIMARY_ADAPTER(padapter);\n\n\tRTW_INFO(FUNC_NDEV_FMT\" , bup=%d\\n\", FUNC_NDEV_ARG(pnetdev), padapter->bup);\n\n\tif (!primary_padapter)\n\t\tgoto _netdev_virtual_iface_open_error;\n\n#ifdef CONFIG_PLATFORM_INTEL_BYT\n\tif (padapter->bup == _FALSE) {\n\t\tu8 mac[ETH_ALEN];\n\n\t\t/* get mac address from primary_padapter */\n\t\tif (primary_padapter->bup == _FALSE)\n\t\t\trtw_macaddr_cfg(adapter_mac_addr(primary_padapter), get_hal_mac_addr(primary_padapter));\n\n\t\t_rtw_memcpy(mac, adapter_mac_addr(primary_padapter), ETH_ALEN);\n\n\t\t/*\n\t\t* If the BIT1 is 0, the address is universally administered.\n\t\t* If it is 1, the address is locally administered\n\t\t*/\n\t\tmac[0] |= BIT(1);\n\n\t\t_rtw_memcpy(adapter_mac_addr(padapter), mac, ETH_ALEN);\n\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\t\trtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter));\n#endif\n\t\trtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));\n\t\t_rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN);\n\t}\n#endif /*CONFIG_PLATFORM_INTEL_BYT*/\n\n\tif (primary_padapter->bup == _FALSE || !rtw_is_hw_init_completed(primary_padapter))\n\t\t_netdev_open(primary_padapter->pnetdev);\n\n\tif (padapter->bup == _FALSE && primary_padapter->bup == _TRUE &&\n\t    rtw_is_hw_init_completed(primary_padapter)) {\n#if 0 /*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */\n#endif\n\n\t}\n\n\tif (padapter->bup == _FALSE) {\n\t\tif (rtw_start_drv_threads(padapter) == _FAIL)\n\t\t\tgoto _netdev_virtual_iface_open_error;\n\t}\n\n#ifdef CONFIG_RTW_NAPI\n\tif (padapter->napi_state == NAPI_DISABLE) {\n\t\tnapi_enable(&padapter->napi);\n\t\tpadapter->napi_state = NAPI_ENABLE;\n\t}\n#endif\n\n#ifdef CONFIG_IOCTL_CFG80211\n\trtw_cfg80211_init_wiphy(padapter);\n\trtw_cfg80211_init_wdev_data(padapter);\n#endif\n\n\tpadapter->bup = _TRUE;\n\n\tpadapter->net_closed = _FALSE;\n\n\trtw_netif_wake_queue(pnetdev);\n\n\tRTW_INFO(FUNC_NDEV_FMT\" (bup=%d) exit\\n\", FUNC_NDEV_ARG(pnetdev), padapter->bup);\n\n\treturn 0;\n\n_netdev_virtual_iface_open_error:\n\n\tpadapter->bup = _FALSE;\n\n#ifdef CONFIG_RTW_NAPI\n\tif(padapter->napi_state == NAPI_ENABLE) {\n\t\tnapi_disable(&padapter->napi);\n\t\tpadapter->napi_state = NAPI_DISABLE;\n\t}\n#endif\n\n\trtw_netif_carrier_off(pnetdev);\n\trtw_netif_stop_queue(pnetdev);\n\n\treturn -1;\n\n}\n\nint netdev_vir_if_open(struct net_device *pnetdev)\n{\n\tint ret;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);\n\n\t_enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);\n\tret = _netdev_vir_if_open(pnetdev);\n\t_exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);\n\n#ifdef CONFIG_AUTO_AP_MODE\n\t/* if(padapter->iface_id == 2) */\n\t/*\trtw_start_auto_ap(padapter); */\n#endif\n\n\treturn ret;\n}\n\nstatic int netdev_vir_if_close(struct net_device *pnetdev)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\n\tRTW_INFO(FUNC_NDEV_FMT\" , bup=%d\\n\", FUNC_NDEV_ARG(pnetdev), padapter->bup);\n\tpadapter->net_closed = _TRUE;\n\tpmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;\n\n\tif (pnetdev)\n\t\trtw_netif_stop_queue(pnetdev);\n\n#ifdef CONFIG_P2P\n\tif (!rtw_p2p_chk_role(&padapter->wdinfo, P2P_ROLE_DISABLE))\n\t\trtw_p2p_enable(padapter, P2P_ROLE_DISABLE);\n#endif\n\n#ifdef CONFIG_IOCTL_CFG80211\n\trtw_scan_abort(padapter);\n\trtw_cfg80211_wait_scan_req_empty(padapter, 200);\n\tadapter_wdev_data(padapter)->bandroid_scan = _FALSE;\n#endif\n\n\treturn 0;\n}\n#endif /*#ifndef CONFIG_NEW_NETDEV_HDL*/\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))\nstatic const struct net_device_ops rtw_netdev_vir_if_ops = {\n\t.ndo_init = rtw_ndev_init,\n\t.ndo_uninit = rtw_ndev_uninit,\n\t#ifdef CONFIG_NEW_NETDEV_HDL\n\t.ndo_open = netdev_open,\n\t.ndo_stop = netdev_close,\n\t#else\n\t.ndo_open = netdev_vir_if_open,\n\t.ndo_stop = netdev_vir_if_close,\n\t#endif\n\t.ndo_start_xmit = rtw_xmit_entry,\n\t.ndo_set_mac_address = rtw_net_set_mac_address,\n\t.ndo_get_stats = rtw_net_get_stats,\n\t.ndo_do_ioctl = rtw_ioctl,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\t.ndo_select_queue\t= rtw_select_queue,\n#endif\n};\n#endif\n\nstatic void rtw_hook_vir_if_ops(struct net_device *ndev)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))\n\tndev->netdev_ops = &rtw_netdev_vir_if_ops;\n#else\n\tndev->init = rtw_ndev_init;\n\tndev->uninit = rtw_ndev_uninit;\n\t#ifdef CONFIG_NEW_NETDEV_HDL\n\tndev->open = netdev_open;\n\tndev->stop = netdev_close;\n\t#else\n\tndev->open = netdev_vir_if_open;\n\tndev->stop = netdev_vir_if_close;\n\t#endif\n\n\tndev->set_mac_address = rtw_net_set_mac_address;\n#endif\n}\n_adapter *rtw_drv_add_vir_if(_adapter *primary_padapter,\n\tvoid (*set_intf_ops)(_adapter *primary_padapter, struct _io_ops *pops))\n{\n\tint res = _FAIL;\n\t_adapter *padapter = NULL;\n\tstruct dvobj_priv *pdvobjpriv;\n\tu8 mac[ETH_ALEN];\n\n\t/****** init adapter ******/\n\tpadapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter));\n\tif (padapter == NULL)\n\t\tgoto exit;\n\n\tif (loadparam(padapter) != _SUCCESS)\n\t\tgoto free_adapter;\n\n\t_rtw_memcpy(padapter, primary_padapter, sizeof(_adapter));\n\n\t/*  */\n\tpadapter->bup = _FALSE;\n\tpadapter->net_closed = _TRUE;\n\tpadapter->dir_dev = NULL;\n\tpadapter->dir_odm = NULL;\n\n\t/*set adapter_type/iface type*/\n\tpadapter->isprimary = _FALSE;\n\tpadapter->adapter_type = VIRTUAL_ADAPTER;\n\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\tpadapter->hw_port = HW_PORT0;\n#else\n\tpadapter->hw_port = HW_PORT1;\n#endif\n\n\n\t/****** hook vir if into dvobj ******/\n\tpdvobjpriv = adapter_to_dvobj(padapter);\n\tpadapter->iface_id = pdvobjpriv->iface_nums;\n\tpdvobjpriv->padapters[pdvobjpriv->iface_nums++] = padapter;\n\n\tpadapter->intf_start = primary_padapter->intf_start;\n\tpadapter->intf_stop = primary_padapter->intf_stop;\n\n\t/* step init_io_priv */\n\tif ((rtw_init_io_priv(padapter, set_intf_ops)) == _FAIL) {\n\t\tgoto free_adapter;\n\t}\n\n\t/*init drv data*/\n\tif (rtw_init_drv_sw(padapter) != _SUCCESS)\n\t\tgoto free_drv_sw;\n\n\n\t/*get mac address from primary_padapter*/\n\t_rtw_memcpy(mac, adapter_mac_addr(primary_padapter), ETH_ALEN);\n\n\t/*\n\t* If the BIT1 is 0, the address is universally administered.\n\t* If it is 1, the address is locally administered\n\t*/\n\tmac[0] |= BIT(1);\n\tif (padapter->iface_id > IFACE_ID1)\n\t\tmac[4] ^= BIT(padapter->iface_id);\n\n\t_rtw_memcpy(adapter_mac_addr(padapter), mac, ETH_ALEN);\n\t/* update mac-address to mbsid-cam cache*/\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\trtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter));\n#endif\n\tRTW_INFO(\"%s if%d mac_addr : \"MAC_FMT\"\\n\", __func__, padapter->iface_id + 1, MAC_ARG(adapter_mac_addr(padapter)));\n#ifdef CONFIG_P2P\n\trtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));\n#endif\n\n\trtw_led_set_ctl_en_mask_virtual(padapter);\n\trtw_led_set_iface_en(padapter, 1);\n\n\tres = _SUCCESS;\n\nfree_drv_sw:\n\tif (res != _SUCCESS && padapter)\n\t\trtw_free_drv_sw(padapter);\nfree_adapter:\n\tif (res != _SUCCESS && padapter) {\n\t\trtw_vmfree((u8 *)padapter, sizeof(*padapter));\n\t\tpadapter = NULL;\n\t}\nexit:\n\treturn padapter;\n}\n\nvoid rtw_drv_stop_vir_if(_adapter *padapter)\n{\n\tstruct net_device *pnetdev = NULL;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n\tif (padapter == NULL)\n\t\treturn;\n\tRTW_INFO(FUNC_ADPT_FMT\" enter\\n\", FUNC_ADPT_ARG(padapter));\n\n\tpnetdev = padapter->pnetdev;\n\n\tif (check_fwstate(pmlmepriv, _FW_LINKED))\n\t\trtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY);\n\n#ifdef CONFIG_AP_MODE\n\tif (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {\n\t\tfree_mlme_ap_info(padapter);\n\t\t#ifdef CONFIG_HOSTAPD_MLME\n\t\thostapd_mode_unload(padapter);\n\t\t#endif\n\t}\n#endif\n\n\tif (padapter->bup == _TRUE) {\n\t\t#ifdef CONFIG_XMIT_ACK\n\t\tif (padapter->xmitpriv.ack_tx)\n\t\t\trtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP);\n\t\t#endif\n\n\t\trtw_intf_stop(padapter);\n\t#ifndef CONFIG_NEW_NETDEV_HDL\n\t\trtw_stop_drv_threads(padapter);\n\t#endif\n\t\tpadapter->bup = _FALSE;\n\t}\n\t#ifdef CONFIG_NEW_NETDEV_HDL\n\trtw_stop_drv_threads(padapter);\n\t#endif\n\t/* cancel timer after thread stop */\n\trtw_cancel_all_timer(padapter);\n}\n\nvoid rtw_drv_free_vir_if(_adapter *padapter)\n{\n\tif (padapter == NULL)\n\t\treturn;\n\n\tRTW_INFO(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n\trtw_free_drv_sw(padapter);\n\n\t/* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */\n\trtw_os_ndev_free(padapter);\n\n\trtw_vmfree((u8 *)padapter, sizeof(_adapter));\n}\n\n\nvoid rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj)\n{\n\tint i;\n\n\tfor (i = VIF_START_ID; i < dvobj->iface_nums; i++)\n\t\trtw_drv_stop_vir_if(dvobj->padapters[i]);\n}\n\nvoid rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj)\n{\n\tint i;\n\n\tfor (i = VIF_START_ID; i < dvobj->iface_nums; i++)\n\t\trtw_drv_free_vir_if(dvobj->padapters[i]);\n}\n\n\n#endif /*end of CONFIG_CONCURRENT_MODE*/\n\n/* IPv4, IPv6 IP addr notifier */\nstatic int rtw_inetaddr_notifier_call(struct notifier_block *nb,\n\t\t\t\t      unsigned long action, void *data)\n{\n\tstruct in_ifaddr *ifa = (struct in_ifaddr *)data;\n\tstruct net_device *ndev;\n\tstruct mlme_ext_priv *pmlmeext = NULL;\n\tstruct mlme_ext_info *pmlmeinfo = NULL;\n\t_adapter *adapter = NULL;\n\n\tif (!ifa || !ifa->ifa_dev || !ifa->ifa_dev->dev)\n\t\treturn NOTIFY_DONE;\n\n\tndev = ifa->ifa_dev->dev;\n\n\tif (!is_rtw_ndev(ndev))\n\t\treturn NOTIFY_DONE;\n\n\tadapter = (_adapter *)rtw_netdev_priv(ifa->ifa_dev->dev);\n\n\tif (adapter == NULL)\n\t\treturn NOTIFY_DONE;\n\n\tpmlmeext = &adapter->mlmeextpriv;\n\tpmlmeinfo = &pmlmeext->mlmext_info;\n\n\tswitch (action) {\n\tcase NETDEV_UP:\n\t\t_rtw_memcpy(pmlmeinfo->ip_addr, &ifa->ifa_address,\n\t\t\t\t\tRTW_IP_ADDR_LEN);\n\t\tRTW_DBG(\"%s[%s]: up IP: %pI4\\n\", __func__,\n\t\t\t\t\tifa->ifa_label, pmlmeinfo->ip_addr);\n\tbreak;\n\tcase NETDEV_DOWN:\n\t\t_rtw_memset(pmlmeinfo->ip_addr, 0, RTW_IP_ADDR_LEN);\n\t\tRTW_DBG(\"%s[%s]: down IP: %pI4\\n\", __func__,\n\t\t\t\t\tifa->ifa_label, pmlmeinfo->ip_addr);\n\tbreak;\n\tdefault:\n\t\tRTW_DBG(\"%s: default action\\n\", __func__);\n\tbreak;\n\t}\n\treturn NOTIFY_DONE;\n}\n\n#ifdef CONFIG_IPV6\nstatic int rtw_inet6addr_notifier_call(struct notifier_block *nb,\n\t\t\t\t       unsigned long action, void *data)\n{\n\tstruct inet6_ifaddr *inet6_ifa = data;\n\tstruct net_device *ndev;\n\tstruct pwrctrl_priv *pwrctl = NULL;\n\tstruct mlme_ext_priv *pmlmeext = NULL;\n\tstruct mlme_ext_info *pmlmeinfo = NULL;\n\t_adapter *adapter = NULL;\n\n\tif (!inet6_ifa || !inet6_ifa->idev || !inet6_ifa->idev->dev)\n\t\treturn NOTIFY_DONE;\n\n\tndev = inet6_ifa->idev->dev;\n\n\tif (!is_rtw_ndev(ndev))\n\t\treturn NOTIFY_DONE;\n\n\tadapter = (_adapter *)rtw_netdev_priv(inet6_ifa->idev->dev);\n\n\tif (adapter == NULL)\n\t\treturn NOTIFY_DONE;\n\n\tpmlmeext =  &adapter->mlmeextpriv;\n\tpmlmeinfo = &pmlmeext->mlmext_info;\n\tpwrctl = adapter_to_pwrctl(adapter);\n\n\tpmlmeext = &adapter->mlmeextpriv;\n\tpmlmeinfo = &pmlmeext->mlmext_info;\n\n\tswitch (action) {\n\tcase NETDEV_UP:\n#ifdef CONFIG_WOWLAN\n\t\tpwrctl->wowlan_ns_offload_en = _TRUE;\n#endif\n\t\t_rtw_memcpy(pmlmeinfo->ip6_addr, &inet6_ifa->addr,\n\t\t\t\t\tRTW_IPv6_ADDR_LEN);\n\t\tRTW_DBG(\"%s: up IPv6 addrs: %pI6\\n\", __func__,\n\t\t\t\t\tpmlmeinfo->ip6_addr);\n\t\t\tbreak;\n\tcase NETDEV_DOWN:\n#ifdef CONFIG_WOWLAN\n\t\tpwrctl->wowlan_ns_offload_en = _FALSE;\n#endif\n\t\t_rtw_memset(pmlmeinfo->ip6_addr, 0, RTW_IPv6_ADDR_LEN);\n\t\tRTW_DBG(\"%s: down IPv6 addrs: %pI6\\n\", __func__,\n\t\t\t\t\tpmlmeinfo->ip6_addr);\n\t\tbreak;\n\tdefault:\n\t\tRTW_DBG(\"%s: default action\\n\", __func__);\n\t\tbreak;\n\t}\n\treturn NOTIFY_DONE;\n}\n#endif\n\nstatic struct notifier_block rtw_inetaddr_notifier = {\n\t.notifier_call = rtw_inetaddr_notifier_call\n};\n\n#ifdef CONFIG_IPV6\nstatic struct notifier_block rtw_inet6addr_notifier = {\n\t.notifier_call = rtw_inet6addr_notifier_call\n};\n#endif\n\nvoid rtw_inetaddr_notifier_register(void)\n{\n\tRTW_INFO(\"%s\\n\", __func__);\n\tregister_inetaddr_notifier(&rtw_inetaddr_notifier);\n#ifdef CONFIG_IPV6\n\tregister_inet6addr_notifier(&rtw_inet6addr_notifier);\n#endif\n}\n\nvoid rtw_inetaddr_notifier_unregister(void)\n{\n\tRTW_INFO(\"%s\\n\", __func__);\n\tunregister_inetaddr_notifier(&rtw_inetaddr_notifier);\n#ifdef CONFIG_IPV6\n\tunregister_inet6addr_notifier(&rtw_inet6addr_notifier);\n#endif\n}\n\nint rtw_os_ndevs_register(struct dvobj_priv *dvobj)\n{\n\tint i, status = _SUCCESS;\n\tstruct registry_priv *regsty = dvobj_to_regsty(dvobj);\n\t_adapter *adapter;\n\n#if defined(CONFIG_IOCTL_CFG80211)\n\tif (rtw_cfg80211_dev_res_register(dvobj) != _SUCCESS) {\n\t\trtw_warn_on(1);\n\t\tstatus = _FAIL;\n\t\tgoto exit;\n\t}\n#endif\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\n\t\tif (i >= CONFIG_IFACE_NUMBER) {\n\t\t\tRTW_ERR(\"%s %d >= CONFIG_IFACE_NUMBER(%d)\\n\", __func__, i, CONFIG_IFACE_NUMBER);\n\t\t\trtw_warn_on(1);\n\t\t\tcontinue;\n\t\t}\n\n\t\tadapter = dvobj->padapters[i];\n\t\tif (adapter) {\n\t\t\tchar *name;\n\n\t\t\t#ifdef CONFIG_RTW_DYNAMIC_NDEV\n\t\t\tif (!is_primary_adapter(adapter))\n\t\t\t\tcontinue;\n\t\t\t#endif\n\n\t\t\tif (adapter->iface_id == IFACE_ID0)\n\t\t\t\tname = regsty->ifname;\n\t\t\telse if (adapter->iface_id == IFACE_ID1)\n\t\t\t\tname = regsty->if2name;\n\t\t\telse\n\t\t\t\tname = \"wlan%d\";\n\n\t\t\tstatus = rtw_os_ndev_register(adapter, name);\n\n\t\t\tif (status != _SUCCESS) {\n\t\t\t\trtw_warn_on(1);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (status != _SUCCESS) {\n\t\tfor (; i >= 0; i--) {\n\t\t\tadapter = dvobj->padapters[i];\n\t\t\tif (adapter)\n\t\t\t\trtw_os_ndev_unregister(adapter);\n\t\t}\n\t}\n\n#if defined(CONFIG_IOCTL_CFG80211)\n\tif (status != _SUCCESS)\n\t\trtw_cfg80211_dev_res_unregister(dvobj);\n#endif\nexit:\n\treturn status;\n}\n\nvoid rtw_os_ndevs_unregister(struct dvobj_priv *dvobj)\n{\n\tint i;\n\t_adapter *adapter = NULL;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tadapter = dvobj->padapters[i];\n\n\t\tif (adapter == NULL)\n\t\t\tcontinue;\n\n\t\trtw_os_ndev_unregister(adapter);\n\t}\n\n#if defined(CONFIG_IOCTL_CFG80211)\n\trtw_cfg80211_dev_res_unregister(dvobj);\n#endif\n}\n\n/**\n * rtw_os_ndevs_init - Allocate and register OS layer net devices and relating structures for @dvobj\n * @dvobj: the dvobj on which this function applies\n *\n * Returns:\n * _SUCCESS or _FAIL\n */\nint rtw_os_ndevs_init(struct dvobj_priv *dvobj)\n{\n\tint ret = _FAIL;\n\n\tif (rtw_os_ndevs_alloc(dvobj) != _SUCCESS)\n\t\tgoto exit;\n\n\tif (rtw_os_ndevs_register(dvobj) != _SUCCESS)\n\t\tgoto os_ndevs_free;\n\n\tret = _SUCCESS;\n\nos_ndevs_free:\n\tif (ret != _SUCCESS)\n\t\trtw_os_ndevs_free(dvobj);\nexit:\n\treturn ret;\n}\n\n/**\n * rtw_os_ndevs_deinit - Unregister and free OS layer net devices and relating structures for @dvobj\n * @dvobj: the dvobj on which this function applies\n */\nvoid rtw_os_ndevs_deinit(struct dvobj_priv *dvobj)\n{\n\trtw_os_ndevs_unregister(dvobj);\n\trtw_os_ndevs_free(dvobj);\n}\n\n#ifdef CONFIG_BR_EXT\nvoid netdev_br_init(struct net_device *netdev)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);\n\n#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))\n\trcu_read_lock();\n#endif\n\n\t/* if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) */\n\t{\n\t\t/* struct net_bridge\t*br = netdev->br_port->br; */ /* ->dev->dev_addr; */\n\t\t#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))\n\t\tif (netdev->br_port)\n\t\t#else\n\t\tif (rcu_dereference(adapter->pnetdev->rx_handler_data))\n\t\t#endif\n\t\t{\n\t\t\tstruct net_device *br_netdev;\n\n\t\t\tbr_netdev = rtw_get_bridge_ndev_by_name(CONFIG_BR_EXT_BRNAME);\n\t\t\tif (br_netdev) {\n\t\t\t\tmemcpy(adapter->br_mac, br_netdev->dev_addr, ETH_ALEN);\n\t\t\t\tdev_put(br_netdev);\n\t\t\t\tRTW_INFO(FUNC_NDEV_FMT\" bind bridge dev \"NDEV_FMT\"(\"MAC_FMT\")\\n\"\n\t\t\t\t\t, FUNC_NDEV_ARG(netdev), NDEV_ARG(br_netdev), MAC_ARG(br_netdev->dev_addr));\n\t\t\t} else {\n\t\t\t\tRTW_INFO(FUNC_NDEV_FMT\" can't get bridge dev by name \\\"%s\\\"\\n\"\n\t\t\t\t\t, FUNC_NDEV_ARG(netdev), CONFIG_BR_EXT_BRNAME);\n\t\t\t}\n\t\t}\n\n\t\tadapter->ethBrExtInfo.addPPPoETag = 1;\n\t}\n\n#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))\n\trcu_read_unlock();\n#endif\n}\n#endif /* CONFIG_BR_EXT */\n\n#ifdef CONFIG_NEW_NETDEV_HDL\nint _netdev_open(struct net_device *pnetdev)\n{\n\tuint status;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n\n\tRTW_INFO(FUNC_NDEV_FMT\" start\\n\", FUNC_NDEV_ARG(pnetdev));\n\n\t#ifdef CONFIG_AUTOSUSPEND\n\tif (pwrctrlpriv->ps_flag == _TRUE) {\n\t\tpadapter->net_closed = _FALSE;\n\t\tgoto netdev_open_normal_process;\n\t}\n\t#endif /*CONFIG_AUTOSUSPEND*/\n\n\tif (!rtw_is_hw_init_completed(padapter)) { // ips \n\t\trtw_clr_surprise_removed(padapter);\n\t\trtw_clr_drv_stopped(padapter);\n\t\tRTW_ENABLE_FUNC(padapter, DF_RX_BIT);\n\t\tRTW_ENABLE_FUNC(padapter, DF_TX_BIT);\n\t\tstatus = rtw_hal_init(padapter);\n\t\tif (status == _FAIL)\n\t\t\tgoto netdev_open_error;\n\t\trtw_led_control(padapter, LED_CTL_NO_LINK);\n\t\t#ifndef RTW_HALMAC\n\t\tstatus = rtw_mi_start_drv_threads(padapter);\n\t\tif (status == _FAIL) {\n\t\t\tRTW_ERR(FUNC_NDEV_FMT \"Initialize driver thread failed!\\n\", FUNC_NDEV_ARG(pnetdev));\n\t\t\tgoto netdev_open_error;\n\t\t}\n\n\t\trtw_intf_start(GET_PRIMARY_ADAPTER(padapter));\n\t\t#endif /* !RTW_HALMAC */\n\n\t\t{\n\t#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\t\t\t_adapter *prim_adpt = GET_PRIMARY_ADAPTER(padapter);\n\t\t\n\t\t\tif (prim_adpt && (_TRUE == prim_adpt->EEPROMBluetoothCoexist)) {\n\t\t\t\trtw_btcoex_init_socket(prim_adpt);\n\t\t\t\tprim_adpt->coex_info.BtMgnt.ExtConfig.HCIExtensionVer = 0x04;\n\t\t\t\trtw_btcoex_SetHciVersion(prim_adpt, 0x04);\n\t\t\t}\n\t#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */\n\n\t\t\t_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);\n\n\t#ifndef CONFIG_IPS_CHECK_IN_WD\n\t\t\trtw_set_pwr_state_check_timer(pwrctrlpriv);\n\t#endif /*CONFIG_IPS_CHECK_IN_WD*/\n\t\t}\n\n\t}\n\n\t/*if (padapter->bup == _FALSE) */\n\t{\n\t\trtw_hal_iface_init(padapter);\n\n\t\t#ifdef CONFIG_RTW_NAPI\n\t\tif(padapter->napi_state == NAPI_DISABLE) {\n\t\t\tnapi_enable(&padapter->napi);\n\t\t\tpadapter->napi_state = NAPI_ENABLE;\n\t\t}\n\t\t#endif\n\n\t\t#ifdef CONFIG_IOCTL_CFG80211\n\t\trtw_cfg80211_init_wiphy(padapter);\n\t\trtw_cfg80211_init_wdev_data(padapter);\n\t\t#endif\n\t\t/* rtw_netif_carrier_on(pnetdev); */ /* call this func when rtw_joinbss_event_callback return success */\n\t\trtw_netif_wake_queue(pnetdev);\n\n\t\t#ifdef CONFIG_BR_EXT\n\t\tif (is_primary_adapter(padapter))\n\t\t\tnetdev_br_init(pnetdev);\n\t\t#endif /* CONFIG_BR_EXT */\n\n\n\t\tpadapter->bup = _TRUE;\n\t\tpadapter->net_closed = _FALSE;\n\t\tpadapter->netif_up = _TRUE;\n\t\tpwrctrlpriv->bips_processing = _FALSE;\n\t}\n\n#ifdef CONFIG_AUTOSUSPEND\nnetdev_open_normal_process:\n#endif\n\tRTW_INFO(FUNC_NDEV_FMT\" Success (bup=%d)\\n\", FUNC_NDEV_ARG(pnetdev), padapter->bup);\n\treturn 0;\n\nnetdev_open_error:\n\tpadapter->bup = _FALSE;\n\n\t#ifdef CONFIG_RTW_NAPI\n\tif(padapter->napi_state == NAPI_ENABLE) {\n\t\tnapi_disable(&padapter->napi);\n\t\tpadapter->napi_state = NAPI_DISABLE;\n\t}\n\t#endif\n\n\trtw_netif_carrier_off(pnetdev);\n\trtw_netif_stop_queue(pnetdev);\n\n\tRTW_ERR(FUNC_NDEV_FMT\" Failed!! (bup=%d)\\n\", FUNC_NDEV_ARG(pnetdev), padapter->bup);\n\n\treturn -1;\n\n}\n\n#else\nint _netdev_open(struct net_device *pnetdev)\n{\n\tuint status;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\tHAL_DATA_TYPE\t\t*pHalData = GET_HAL_DATA(padapter);\n#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */\n\n\n\tRTW_INFO(FUNC_NDEV_FMT\" , bup=%d\\n\", FUNC_NDEV_ARG(pnetdev), padapter->bup);\n\n\tpadapter->netif_up = _TRUE;\n\n#ifdef CONFIG_PLATFORM_INTEL_BYT\n\trtw_sdio_set_power(1);\n#endif /* CONFIG_PLATFORM_INTEL_BYT */\n\n\t#ifdef CONFIG_AUTOSUSPEND\n\tif (pwrctrlpriv->ps_flag == _TRUE) {\n\t\tpadapter->net_closed = _FALSE;\n\t\tgoto netdev_open_normal_process;\n\t}\n\t#endif\n\n\tif (padapter->bup == _FALSE) {\n#ifdef CONFIG_PLATFORM_INTEL_BYT\n\t\trtw_macaddr_cfg(adapter_mac_addr(padapter),  get_hal_mac_addr(padapter));\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\t\trtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter));\n#endif\n\t\trtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));\n\t\t_rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN);\n#endif /* CONFIG_PLATFORM_INTEL_BYT */\n\n\t\trtw_clr_surprise_removed(padapter);\n\t\trtw_clr_drv_stopped(padapter);\n\n\t\tstatus = rtw_hal_init(padapter);\n\t\tif (status == _FAIL) {\n\t\t\tgoto netdev_open_error;\n\t\t}\n#if 0/*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */\n#endif\n\n\t\tRTW_INFO(\"MAC Address = \"MAC_FMT\"\\n\", MAC_ARG(pnetdev->dev_addr));\n\n#ifndef RTW_HALMAC\n\t\tstatus = rtw_start_drv_threads(padapter);\n\t\tif (status == _FAIL) {\n\t\t\tRTW_INFO(\"Initialize driver software resource Failed!\\n\");\n\t\t\tgoto netdev_open_error;\n\t\t}\n#endif /* !RTW_HALMAC */\n\n#ifdef CONFIG_RTW_NAPI\n\t\tif(padapter->napi_state == NAPI_DISABLE) {\n\t\t\tnapi_enable(&padapter->napi);\n\t\t\tpadapter->napi_state = NAPI_ENABLE;\n\t\t}\n#endif\n\n#ifndef RTW_HALMAC\n\t\trtw_intf_start(padapter);\n#endif /* !RTW_HALMAC */\n\n#ifdef CONFIG_IOCTL_CFG80211\n\t\trtw_cfg80211_init_wiphy(padapter);\n\t\trtw_cfg80211_init_wdev_data(padapter);\n#endif\n\n\t\trtw_led_control(padapter, LED_CTL_NO_LINK);\n\n\t\tpadapter->bup = _TRUE;\n\t\tpwrctrlpriv->bips_processing = _FALSE;\n\n#ifdef CONFIG_PLATFORM_INTEL_BYT\n#ifdef CONFIG_BT_COEXIST\n\t\trtw_btcoex_IpsNotify(padapter, IPS_NONE);\n#endif /* CONFIG_BT_COEXIST */\n#endif /* CONFIG_PLATFORM_INTEL_BYT\t\t */\n\t}\n\tpadapter->net_closed = _FALSE;\n\n\t_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);\n\n#ifndef CONFIG_IPS_CHECK_IN_WD\n\trtw_set_pwr_state_check_timer(pwrctrlpriv);\n#endif\n\n\t/* rtw_netif_carrier_on(pnetdev); */ /* call this func when rtw_joinbss_event_callback return success */\n\trtw_netif_wake_queue(pnetdev);\n\n#ifdef CONFIG_BR_EXT\n\tnetdev_br_init(pnetdev);\n#endif /* CONFIG_BR_EXT */\n\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\tif (is_primary_adapter(padapter) && (_TRUE == pHalData->EEPROMBluetoothCoexist)) {\n\t\trtw_btcoex_init_socket(padapter);\n\t\tpadapter->coex_info.BtMgnt.ExtConfig.HCIExtensionVer = 0x04;\n\t\trtw_btcoex_SetHciVersion(padapter, 0x04);\n\t} else\n\t\tRTW_INFO(\"CONFIG_BT_COEXIST: VIRTUAL_ADAPTER\\n\");\n#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */\n\n#ifdef CONFIG_AUTOSUSPEND\nnetdev_open_normal_process:\n#endif\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t{\n\t\t_adapter *sec_adapter = adapter_to_dvobj(padapter)->padapters[IFACE_ID1];\n\n\t\t#ifndef CONFIG_RTW_DYNAMIC_NDEV\n\t\tif (sec_adapter && (sec_adapter->bup == _FALSE))\n\t\t\t_netdev_vir_if_open(sec_adapter->pnetdev);\n\t\t#endif\n\t}\n#endif\n\n#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS\n\tpwrctrlpriv->radio_on_start_time = rtw_get_current_time();\n\tpwrctrlpriv->pwr_saving_start_time = rtw_get_current_time();\n\tpwrctrlpriv->pwr_saving_time = 0;\n\tpwrctrlpriv->on_time = 0;\n\tpwrctrlpriv->tx_time = 0;\n\tpwrctrlpriv->rx_time = 0;\n#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */\n\n\tRTW_INFO(\"-871x_drv - drv_open, bup=%d\\n\", padapter->bup);\n\n\treturn 0;\n\nnetdev_open_error:\n\n\tpadapter->bup = _FALSE;\n\n#ifdef CONFIG_RTW_NAPI\n\tif(padapter->napi_state == NAPI_ENABLE) {\n\t\tnapi_disable(&padapter->napi);\n\t\tpadapter->napi_state = NAPI_DISABLE;\n\t}\n#endif\n\n\trtw_netif_carrier_off(pnetdev);\n\trtw_netif_stop_queue(pnetdev);\n\n\tRTW_INFO(\"-871x_drv - drv_open fail, bup=%d\\n\", padapter->bup);\n\n\treturn -1;\n\n}\n#endif\nint netdev_open(struct net_device *pnetdev)\n{\n\tint ret = _FALSE;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n\n\tif (pwrctrlpriv->bInSuspend == _TRUE) {\n\t\tRTW_INFO(\" [WARN] \"ADPT_FMT\" %s  failed, bInSuspend=%d\\n\", ADPT_ARG(padapter), __func__, pwrctrlpriv->bInSuspend);\n\t\treturn 0;\n\t}\n\n\t_enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);\n#ifdef CONFIG_NEW_NETDEV_HDL\n\tret = _netdev_open(pnetdev);\n#else\n\tif (is_primary_adapter(padapter))\n\t\tret = _netdev_open(pnetdev);\n#ifdef CONFIG_CONCURRENT_MODE\n\telse\n\t\tret = _netdev_vir_if_open(pnetdev);\n#endif\n#endif\n\t_exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);\n\n\n#ifdef CONFIG_AUTO_AP_MODE\n\tif (padapter->iface_id == IFACE_ID2)\n\t\trtw_start_auto_ap(padapter);\n#endif\n\n\treturn ret;\n}\n\n#ifdef CONFIG_IPS\nint  ips_netdrv_open(_adapter *padapter)\n{\n\tint status = _SUCCESS;\n\t/* struct pwrctrl_priv\t*pwrpriv = adapter_to_pwrctl(padapter); */\n\n\tpadapter->net_closed = _FALSE;\n\n\tRTW_INFO(\"===> %s.........\\n\", __FUNCTION__);\n\n\n\trtw_clr_drv_stopped(padapter);\n\t/* padapter->bup = _TRUE; */\n#ifdef CONFIG_NEW_NETDEV_HDL\n\tif (!rtw_is_hw_init_completed(padapter)) {\n\t\tstatus = rtw_hal_init(padapter);\n\t\tif (status == _FAIL) {\n\t\t\tgoto netdev_open_error;\n\t\t}\n\t\trtw_mi_hal_iface_init(padapter);\n\t}\n#else\n\tstatus = rtw_hal_init(padapter);\n\tif (status == _FAIL) {\n\t\tgoto netdev_open_error;\n\t}\n#endif\n#if 0\n\trtw_mi_set_mac_addr(padapter);\n#endif\n#ifndef RTW_HALMAC\n\trtw_intf_start(padapter);\n#endif /* !RTW_HALMAC */\n\n#ifndef CONFIG_IPS_CHECK_IN_WD\n\trtw_set_pwr_state_check_timer(adapter_to_pwrctl(padapter));\n#endif\n\t_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);\n\n\treturn _SUCCESS;\n\nnetdev_open_error:\n\t/* padapter->bup = _FALSE; */\n\tRTW_INFO(\"-ips_netdrv_open - drv_open failure, bup=%d\\n\", padapter->bup);\n\n\treturn _FAIL;\n}\n\nint rtw_ips_pwr_up(_adapter *padapter)\n{\n\tint result;\n#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS)\n#ifdef DBG_CONFIG_ERROR_DETECT\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);\n\tstruct sreset_priv *psrtpriv = &pHalData->srestpriv;\n#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */\n#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */\n\tsystime start_time = rtw_get_current_time();\n\tRTW_INFO(\"===>  rtw_ips_pwr_up..............\\n\");\n\n#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS)\n#ifdef DBG_CONFIG_ERROR_DETECT\n\tif (psrtpriv->silent_reset_inprogress == _TRUE)\n#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */\n#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */\n\t\trtw_reset_drv_sw(padapter);\n\n\tresult = ips_netdrv_open(padapter);\n\n\trtw_led_control(padapter, LED_CTL_NO_LINK);\n\n\tRTW_INFO(\"<===  rtw_ips_pwr_up.............. in %dms\\n\", rtw_get_passing_time_ms(start_time));\n\treturn result;\n\n}\n\nvoid rtw_ips_pwr_down(_adapter *padapter)\n{\n\tsystime start_time = rtw_get_current_time();\n\tRTW_INFO(\"===> rtw_ips_pwr_down...................\\n\");\n\n\tpadapter->net_closed = _TRUE;\n\n\trtw_ips_dev_unload(padapter);\n\tRTW_INFO(\"<=== rtw_ips_pwr_down..................... in %dms\\n\", rtw_get_passing_time_ms(start_time));\n}\n#endif\nvoid rtw_ips_dev_unload(_adapter *padapter)\n{\n#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS)\n#ifdef DBG_CONFIG_ERROR_DETECT\n\tPHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);\n\tstruct sreset_priv *psrtpriv = &pHalData->srestpriv;\n#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */\n#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */\n\tRTW_INFO(\"====> %s...\\n\", __FUNCTION__);\n\n\n#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS)\n#ifdef DBG_CONFIG_ERROR_DETECT\n\tif (psrtpriv->silent_reset_inprogress == _TRUE)\n#endif /* #ifdef DBG_CONFIG_ERROR_DETECT */\n#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */\n\t{\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_FIFO_CLEARN_UP, 0);\n\t\trtw_intf_stop(padapter);\n\t}\n\n\tif (!rtw_is_surprise_removed(padapter))\n\t\trtw_hal_deinit(padapter);\n\n}\n#ifdef CONFIG_NEW_NETDEV_HDL\nint _pm_netdev_open(_adapter *padapter)\n{\n\tuint status;\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);\n\tstruct net_device *pnetdev = padapter->pnetdev;\n\n\tRTW_INFO(FUNC_NDEV_FMT\" start\\n\", FUNC_NDEV_ARG(pnetdev));\n\n\t#ifdef CONFIG_AUTOSUSPEND\n\tif (pwrctrlpriv->ps_flag == _TRUE) {\n\t\tpadapter->net_closed = _FALSE;\n\t\tgoto netdev_open_normal_process;\n\t}\n\t#endif /*CONFIG_AUTOSUSPEND*/\n\n\tif (!rtw_is_hw_init_completed(padapter)) { // ips \n\t\trtw_clr_surprise_removed(padapter);\n\t\trtw_clr_drv_stopped(padapter);\n\t\tstatus = rtw_hal_init(padapter);\n\t\tif (status == _FAIL)\n\t\t\tgoto netdev_open_error;\n\t\trtw_led_control(padapter, LED_CTL_NO_LINK);\n\t\t#ifndef RTW_HALMAC\n\t\tstatus = rtw_mi_start_drv_threads(padapter);\n\t\tif (status == _FAIL) {\n\t\t\tRTW_ERR(FUNC_NDEV_FMT \"Initialize driver thread failed!\\n\", FUNC_NDEV_ARG(pnetdev));\n\t\t\tgoto netdev_open_error;\n\t\t}\n\n\t\trtw_intf_start(GET_PRIMARY_ADAPTER(padapter));\n\t\t#endif /* !RTW_HALMAC */\n\n\t\t{\n\t\t\t_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);\n\n\t#ifndef CONFIG_IPS_CHECK_IN_WD\n\t\t\trtw_set_pwr_state_check_timer(pwrctrlpriv);\n\t#endif /*CONFIG_IPS_CHECK_IN_WD*/\n\t\t}\n\n\t}\n\n\t/*if (padapter->bup == _FALSE) */\n\t{\n\t\trtw_hal_iface_init(padapter);\n\n\t\tpadapter->bup = _TRUE;\n\t\tpadapter->net_closed = _FALSE;\n\t\tpadapter->netif_up = _TRUE;\n\t\tpwrctrlpriv->bips_processing = _FALSE;\n\t}\n\n#ifdef CONFIG_AUTOSUSPEND\nnetdev_open_normal_process:\n#endif\n\tRTW_INFO(FUNC_NDEV_FMT\" Success (bup=%d)\\n\", FUNC_NDEV_ARG(pnetdev), padapter->bup);\n\treturn 0;\n\nnetdev_open_error:\n\tpadapter->bup = _FALSE;\n\n\trtw_netif_carrier_off(pnetdev);\n\trtw_netif_stop_queue(pnetdev);\n\n\tRTW_ERR(FUNC_NDEV_FMT\" Failed!! (bup=%d)\\n\", FUNC_NDEV_ARG(pnetdev), padapter->bup);\n\n\treturn -1;\n\n}\nint _mi_pm_netdev_open(struct net_device *pnetdev)\n{\n\tint i;\n\tint status = 0;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);\n\t_adapter *iface;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface->netif_up) {\n\t\t\tstatus = _pm_netdev_open(iface);\n\t\t\tif (status == -1) {\n\t\t\t\tRTW_ERR(\"%s failled\\n\", __func__);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn status;\n}\n#endif /*CONFIG_NEW_NETDEV_HDL*/\nint pm_netdev_open(struct net_device *pnetdev, u8 bnormal)\n{\n\tint status = 0;\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);\n\n\tif (_TRUE == bnormal) {\n\t\t_enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);\n\t\t#ifdef CONFIG_NEW_NETDEV_HDL\n\t\tstatus = _mi_pm_netdev_open(pnetdev);\n\t\t#else\n\t\tstatus = _netdev_open(pnetdev);\n\t\t#endif\n\t\t_exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);\n\t}\n#ifdef CONFIG_IPS\n\telse\n\t\tstatus = (_SUCCESS == ips_netdrv_open(padapter)) ? (0) : (-1);\n#endif\n\n\treturn status;\n}\n#ifdef CONFIG_CLIENT_PORT_CFG\nextern void rtw_hw_client_port_release(_adapter *adapter);\n#endif\nstatic int netdev_close(struct net_device *pnetdev)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\tHAL_DATA_TYPE\t\t*pHalData = GET_HAL_DATA(padapter);\n#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */\n\n\tRTW_INFO(FUNC_NDEV_FMT\" , bup=%d\\n\", FUNC_NDEV_ARG(pnetdev), padapter->bup);\n#ifndef CONFIG_PLATFORM_INTEL_BYT\n\t#ifdef CONFIG_AUTOSUSPEND\n\tif (pwrctl->bInternalAutoSuspend == _TRUE) {\n\t\t/* rtw_pwr_wakeup(padapter); */\n\t\tif (pwrctl->rf_pwrstate == rf_off)\n\t\t\tpwrctl->ps_flag = _TRUE;\n\t}\n\t#endif\n\tpadapter->net_closed = _TRUE;\n\tpadapter->netif_up = _FALSE;\n\tpmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;\n\n#ifdef CONFIG_CLIENT_PORT_CFG\n\tif (MLME_IS_STA(padapter))\n\t\trtw_hw_client_port_release(padapter);\n#endif\n\t/*\tif (!rtw_is_hw_init_completed(padapter)) {\n\t\t\tRTW_INFO(\"(1)871x_drv - drv_close, bup=%d, hw_init_completed=%s\\n\", padapter->bup, rtw_is_hw_init_completed(padapter)?\"_TRUE\":\"_FALSE\");\n\n\t\t\trtw_set_drv_stopped(padapter);\n\n\t\t\trtw_dev_unload(padapter);\n\t\t}\n\t\telse*/\n\tif (pwrctl->rf_pwrstate == rf_on) {\n\t\tRTW_INFO(\"(2)871x_drv - drv_close, bup=%d, hw_init_completed=%s\\n\", padapter->bup, rtw_is_hw_init_completed(padapter) ? \"_TRUE\" : \"_FALSE\");\n\n\t\t/* s1. */\n\t\tif (pnetdev)\n\t\t\trtw_netif_stop_queue(pnetdev);\n\n#ifndef CONFIG_ANDROID\n\t\t/* s2. */\n\t\tLeaveAllPowerSaveMode(padapter);\n\t\trtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK);\n\t\t/* s2-2.  indicate disconnect to os */\n\t\trtw_indicate_disconnect(padapter, 0, _FALSE);\n\t\t/* s2-3. */\n\t\trtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK);\n\t\t/* s2-4. */\n\t\trtw_free_network_queue(padapter, _TRUE);\n#endif\n\t}\n\n#ifdef CONFIG_BR_EXT\n\t/* if (OPMODE & (WIFI_STATION_STATE | WIFI_ADHOC_STATE)) */\n\t{\n\t\t/* void nat25_db_cleanup(_adapter *priv); */\n\t\tnat25_db_cleanup(padapter);\n\t}\n#endif /* CONFIG_BR_EXT */\n\n#ifdef CONFIG_P2P\n\tif (!rtw_p2p_chk_role(&padapter->wdinfo, P2P_ROLE_DISABLE))\n\t\trtw_p2p_enable(padapter, P2P_ROLE_DISABLE);\n#endif /* CONFIG_P2P */\n\n\trtw_scan_abort(padapter); /* stop scanning process before wifi is going to down */\n#ifdef CONFIG_IOCTL_CFG80211\n\trtw_cfg80211_wait_scan_req_empty(padapter, 200);\n\tadapter_wdev_data(padapter)->bandroid_scan = _FALSE;\n\t/* padapter->rtw_wdev->iftype = NL80211_IFTYPE_MONITOR; */ /* set this at the end */\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n#ifdef CONFIG_WAPI_SUPPORT\n\trtw_wapi_disable_tx(padapter);\n#endif\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\tif (is_primary_adapter(padapter) && (_TRUE == pHalData->EEPROMBluetoothCoexist))\n\t\trtw_btcoex_close_socket(padapter);\n\telse\n\t\tRTW_INFO(\"CONFIG_BT_COEXIST: VIRTUAL_ADAPTER\\n\");\n#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */\n#else /* !CONFIG_PLATFORM_INTEL_BYT */\n\n\tif (pwrctl->bInSuspend == _TRUE) {\n\t\tRTW_INFO(\"+871x_drv - drv_close, bInSuspend=%d\\n\", pwrctl->bInSuspend);\n\t\treturn 0;\n\t}\n\n\trtw_scan_abort(padapter); /* stop scanning process before wifi is going to down */\n#ifdef CONFIG_IOCTL_CFG80211\n\trtw_cfg80211_wait_scan_req_empty(padapter, 200);\n#endif\n\n\tRTW_INFO(\"netdev_close, bips_processing=%d\\n\", pwrctl->bips_processing);\n\twhile (pwrctl->bips_processing == _TRUE) /* waiting for ips_processing done before call rtw_dev_unload() */\n\t\trtw_msleep_os(1);\n\n\trtw_dev_unload(padapter);\n\trtw_sdio_set_power(0);\n\n#endif /* !CONFIG_PLATFORM_INTEL_BYT */\n\n\tRTW_INFO(\"-871x_drv - drv_close, bup=%d\\n\", padapter->bup);\n\n\treturn 0;\n\n}\n\nint pm_netdev_close(struct net_device *pnetdev, u8 bnormal)\n{\n\tint status = 0;\n\n\tstatus = netdev_close(pnetdev);\n\n\treturn status;\n}\n\nvoid rtw_ndev_destructor(struct net_device *ndev)\n{\n\tRTW_INFO(FUNC_NDEV_FMT\"\\n\", FUNC_NDEV_ARG(ndev));\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (ndev->ieee80211_ptr)\n\t\trtw_mfree((u8 *)ndev->ieee80211_ptr, sizeof(struct wireless_dev));\n#endif\n\tfree_netdev(ndev);\n}\n\n#ifdef CONFIG_ARP_KEEP_ALIVE\nstruct route_info {\n\tstruct in_addr dst_addr;\n\tstruct in_addr src_addr;\n\tstruct in_addr gateway;\n\tunsigned int dev_index;\n};\n\nstatic void parse_routes(struct nlmsghdr *nl_hdr, struct route_info *rt_info)\n{\n\tstruct rtmsg *rt_msg;\n\tstruct rtattr *rt_attr;\n\tint rt_len;\n\n\trt_msg = (struct rtmsg *) NLMSG_DATA(nl_hdr);\n\tif ((rt_msg->rtm_family != AF_INET) || (rt_msg->rtm_table != RT_TABLE_MAIN))\n\t\treturn;\n\n\trt_attr = (struct rtattr *) RTM_RTA(rt_msg);\n\trt_len = RTM_PAYLOAD(nl_hdr);\n\n\tfor (; RTA_OK(rt_attr, rt_len); rt_attr = RTA_NEXT(rt_attr, rt_len)) {\n\t\tswitch (rt_attr->rta_type) {\n\t\tcase RTA_OIF:\n\t\t\trt_info->dev_index = *(int *) RTA_DATA(rt_attr);\n\t\t\tbreak;\n\t\tcase RTA_GATEWAY:\n\t\t\trt_info->gateway.s_addr = *(u_int *) RTA_DATA(rt_attr);\n\t\t\tbreak;\n\t\tcase RTA_PREFSRC:\n\t\t\trt_info->src_addr.s_addr = *(u_int *) RTA_DATA(rt_attr);\n\t\t\tbreak;\n\t\tcase RTA_DST:\n\t\t\trt_info->dst_addr.s_addr = *(u_int *) RTA_DATA(rt_attr);\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\nstatic int route_dump(u32 *gw_addr , int *gw_index)\n{\n\tint err = 0;\n\tstruct socket *sock;\n\tstruct {\n\t\tstruct nlmsghdr nlh;\n\t\tstruct rtgenmsg g;\n\t} req;\n\tstruct msghdr msg;\n\tstruct iovec iov;\n\tstruct sockaddr_nl nladdr;\n\tmm_segment_t oldfs;\n\tchar *pg;\n\tint size = 0;\n\n\terr = sock_create(AF_NETLINK, SOCK_DGRAM, NETLINK_ROUTE, &sock);\n\tif (err) {\n\t\tprintk(\": Could not create a datagram socket, error = %d\\n\", -ENXIO);\n\t\treturn err;\n\t}\n\n\tmemset(&nladdr, 0, sizeof(nladdr));\n\tnladdr.nl_family = AF_NETLINK;\n\n\treq.nlh.nlmsg_len = sizeof(req);\n\treq.nlh.nlmsg_type = RTM_GETROUTE;\n\treq.nlh.nlmsg_flags = NLM_F_ROOT | NLM_F_MATCH | NLM_F_REQUEST;\n\treq.nlh.nlmsg_pid = 0;\n\treq.g.rtgen_family = AF_INET;\n\n\tiov.iov_base = &req;\n\tiov.iov_len = sizeof(req);\n\n\tmsg.msg_name = &nladdr;\n\tmsg.msg_namelen = sizeof(nladdr);\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))\n\t/* referece:sock_xmit in kernel code\n\t * WRITE for sock_sendmsg, READ for sock_recvmsg\n\t * third parameter for msg_iovlen\n\t * last parameter for iov_len\n\t */\n\tiov_iter_init(&msg.msg_iter, WRITE, &iov, 1, sizeof(req));\n#else\n\tmsg.msg_iov = &iov;\n\tmsg.msg_iovlen = 1;\n#endif\n\tmsg.msg_control = NULL;\n\tmsg.msg_controllen = 0;\n\tmsg.msg_flags = MSG_DONTWAIT;\n\n\toldfs = get_fs();\n\tset_fs(KERNEL_DS);\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))\n\terr = sock_sendmsg(sock, &msg);\n#else\n\terr = sock_sendmsg(sock, &msg, sizeof(req));\n#endif\n\tset_fs(oldfs);\n\n\tif (err < 0)\n\t\tgoto out_sock;\n\n\tpg = (char *) __get_free_page(GFP_KERNEL);\n\tif (pg == NULL) {\n\t\terr = -ENOMEM;\n\t\tgoto out_sock;\n\t}\n\n#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)\nrestart:\n#endif\n\n\tfor (;;) {\n\t\tstruct nlmsghdr *h;\n\n\t\tiov.iov_base = pg;\n\t\tiov.iov_len = PAGE_SIZE;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))\n\t\tiov_iter_init(&msg.msg_iter, READ, &iov, 1, PAGE_SIZE);\n#endif\n\n\t\toldfs = get_fs();\n\t\tset_fs(KERNEL_DS);\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))\n\t\terr = sock_recvmsg(sock, &msg, MSG_DONTWAIT);\n#else\n\t\terr = sock_recvmsg(sock, &msg, PAGE_SIZE, MSG_DONTWAIT);\n#endif\n\t\tset_fs(oldfs);\n\n\t\tif (err < 0)\n\t\t\tgoto out_sock_pg;\n\n\t\tif (msg.msg_flags & MSG_TRUNC) {\n\t\t\terr = -ENOBUFS;\n\t\t\tgoto out_sock_pg;\n\t\t}\n\n\t\th = (struct nlmsghdr *) pg;\n\n\t\twhile (NLMSG_OK(h, err)) {\n\t\t\tstruct route_info rt_info;\n\t\t\tif (h->nlmsg_type == NLMSG_DONE) {\n\t\t\t\terr = 0;\n\t\t\t\tgoto done;\n\t\t\t}\n\n\t\t\tif (h->nlmsg_type == NLMSG_ERROR) {\n\t\t\t\tstruct nlmsgerr *errm = (struct nlmsgerr *) NLMSG_DATA(h);\n\t\t\t\terr = errm->error;\n\t\t\t\tprintk(\"NLMSG error: %d\\n\", errm->error);\n\t\t\t\tgoto done;\n\t\t\t}\n\n\t\t\tif (h->nlmsg_type == RTM_GETROUTE)\n\t\t\t\tprintk(\"RTM_GETROUTE: NLMSG: %d\\n\", h->nlmsg_type);\n\t\t\tif (h->nlmsg_type != RTM_NEWROUTE) {\n\t\t\t\tprintk(\"NLMSG: %d\\n\", h->nlmsg_type);\n\t\t\t\terr = -EINVAL;\n\t\t\t\tgoto done;\n\t\t\t}\n\n\t\t\tmemset(&rt_info, 0, sizeof(struct route_info));\n\t\t\tparse_routes(h, &rt_info);\n\t\t\tif (!rt_info.dst_addr.s_addr && rt_info.gateway.s_addr && rt_info.dev_index) {\n\t\t\t\t*gw_addr = rt_info.gateway.s_addr;\n\t\t\t\t*gw_index = rt_info.dev_index;\n\n\t\t\t}\n\t\t\th = NLMSG_NEXT(h, err);\n\t\t}\n\n\t\tif (err) {\n\t\t\tprintk(\"!!!Remnant of size %d %d %d\\n\", err, h->nlmsg_len, h->nlmsg_type);\n\t\t\terr = -EINVAL;\n\t\t\tbreak;\n\t\t}\n\t}\n\ndone:\n#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)\n\tif (!err && req.g.rtgen_family == AF_INET) {\n\t\treq.g.rtgen_family = AF_INET6;\n\n\t\tiov.iov_base = &req;\n\t\tiov.iov_len = sizeof(req);\n\n\t\tmsg.msg_name = &nladdr;\n\t\tmsg.msg_namelen = sizeof(nladdr);\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))\n\t\tiov_iter_init(&msg.msg_iter, WRITE, &iov, 1, sizeof(req));\n#else\n\t\tmsg.msg_iov = &iov;\n\t\tmsg.msg_iovlen = 1;\n#endif\n\t\tmsg.msg_control = NULL;\n\t\tmsg.msg_controllen = 0;\n\t\tmsg.msg_flags = MSG_DONTWAIT;\n\n\t\toldfs = get_fs();\n\t\tset_fs(KERNEL_DS);\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))\n\t\terr = sock_sendmsg(sock, &msg);\n#else\n\t\terr = sock_sendmsg(sock, &msg, sizeof(req));\n#endif\n\t\tset_fs(oldfs);\n\n\t\tif (err > 0)\n\t\t\tgoto restart;\n\t}\n#endif\n\nout_sock_pg:\n\tfree_page((unsigned long) pg);\n\nout_sock:\n\tsock_release(sock);\n\treturn err;\n}\n\nstatic int arp_query(unsigned char *haddr, u32 paddr,\n\t\t     struct net_device *dev)\n{\n\tstruct neighbour *neighbor_entry;\n\tint\tret = 0;\n\n\tneighbor_entry = neigh_lookup(&arp_tbl, &paddr, dev);\n\n\tif (neighbor_entry != NULL) {\n\t\tneighbor_entry->used = jiffies;\n\t\tif (neighbor_entry->nud_state & NUD_VALID) {\n\t\t\t_rtw_memcpy(haddr, neighbor_entry->ha, dev->addr_len);\n\t\t\tret = 1;\n\t\t}\n\t\tneigh_release(neighbor_entry);\n\t}\n\treturn ret;\n}\n\nstatic int get_defaultgw(u32 *ip_addr , char mac[])\n{\n\tint gw_index = 0; /* oif device index */\n\tstruct net_device *gw_dev = NULL; /* oif device */\n\n\troute_dump(ip_addr, &gw_index);\n\n\tif (!(*ip_addr) || !gw_index) {\n\t\t/* RTW_INFO(\"No default GW\\n\"); */\n\t\treturn -1;\n\t}\n\n\tgw_dev = dev_get_by_index(&init_net, gw_index);\n\n\tif (gw_dev == NULL) {\n\t\t/* RTW_INFO(\"get Oif Device Fail\\n\"); */\n\t\treturn -1;\n\t}\n\n\tif (!arp_query(mac, *ip_addr, gw_dev)) {\n\t\t/* RTW_INFO( \"arp query failed\\n\"); */\n\t\tdev_put(gw_dev);\n\t\treturn -1;\n\n\t}\n\tdev_put(gw_dev);\n\n\treturn 0;\n}\n\nint\trtw_gw_addr_query(_adapter *padapter)\n{\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);\n\tu32 gw_addr = 0; /* default gw address */\n\tunsigned char gw_mac[32] = {0}; /* default gw mac */\n\tint i;\n\tint res;\n\n\tres = get_defaultgw(&gw_addr, gw_mac);\n\tif (!res) {\n\t\tpmlmepriv->gw_ip[0] = gw_addr & 0xff;\n\t\tpmlmepriv->gw_ip[1] = (gw_addr & 0xff00) >> 8;\n\t\tpmlmepriv->gw_ip[2] = (gw_addr & 0xff0000) >> 16;\n\t\tpmlmepriv->gw_ip[3] = (gw_addr & 0xff000000) >> 24;\n\t\t_rtw_memcpy(pmlmepriv->gw_mac_addr, gw_mac, ETH_ALEN);\n\t\tRTW_INFO(\"%s Gateway Mac:\\t\" MAC_FMT \"\\n\", __FUNCTION__, MAC_ARG(pmlmepriv->gw_mac_addr));\n\t\tRTW_INFO(\"%s Gateway IP:\\t\" IP_FMT \"\\n\", __FUNCTION__, IP_ARG(pmlmepriv->gw_ip));\n\t} else\n\t\tRTW_INFO(\"Get Gateway IP/MAC fail!\\n\");\n\n\treturn res;\n}\n#endif\n\nvoid rtw_dev_unload(PADAPTER padapter)\n{\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);\n\tstruct dvobj_priv *pobjpriv = padapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &pobjpriv->drv_dbg;\n\tstruct cmd_priv *pcmdpriv = &padapter->cmdpriv;\n\n\tif (padapter->bup == _TRUE) {\n\t\tRTW_INFO(\"==> \"FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n\n#ifdef CONFIG_WOWLAN\n#ifdef CONFIG_GPIO_WAKEUP\n\t\t/*default wake up pin change to BT*/\n\t\tRTW_INFO(\"%s:default wake up pin change to BT\\n\", __FUNCTION__);\n\t\trtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _FALSE);\n#endif /* CONFIG_GPIO_WAKEUP */\n#endif /* CONFIG_WOWLAN */\n\n\t\trtw_set_drv_stopped(padapter);\n#ifdef CONFIG_XMIT_ACK\n\t\tif (padapter->xmitpriv.ack_tx)\n\t\t\trtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP);\n#endif\n\n\t\trtw_intf_stop(padapter);\n\n\t\t#ifdef CONFIG_AUTOSUSPEND\n\t\tif (!pwrctl->bInternalAutoSuspend)\n\t\t#endif\n\t\t{\n\t\t\trtw_stop_drv_threads(padapter);\n\n\t\t\tif (ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _TRUE) {\n\t\t\t\tRTW_ERR(\"cmd_thread not stop !!\\n\");\n\t\t\t\trtw_warn_on(1);\n\t\t\t}\n\t\t}\n\t\t/* check the status of IPS */\n\t\tif (rtw_hal_check_ips_status(padapter) == _TRUE || pwrctl->rf_pwrstate == rf_off) { /* check HW status and SW state */\n\t\t\tRTW_PRINT(\"%s: driver in IPS-FWLPS\\n\", __func__);\n\t\t\tpdbgpriv->dbg_dev_unload_inIPS_cnt++;\n\t\t} else\n\t\t\tRTW_PRINT(\"%s: driver not in IPS\\n\", __func__);\n\n\t\tif (!rtw_is_surprise_removed(padapter)) {\n#ifdef CONFIG_BT_COEXIST\n\t\t\trtw_btcoex_IpsNotify(padapter, pwrctl->ips_mode_req);\n#endif\n#ifdef CONFIG_WOWLAN\n\t\t\tif (pwrctl->bSupportRemoteWakeup == _TRUE &&\n\t\t\t    pwrctl->wowlan_mode == _TRUE)\n\t\t\t\tRTW_PRINT(\"%s bSupportRemoteWakeup==_TRUE  do not run rtw_hal_deinit()\\n\", __FUNCTION__);\n\t\t\telse\n#endif\n\t\t\t{\n\t\t\t\t/* amy modify 20120221 for power seq is different between driver open and ips */\n\t\t\t\trtw_hal_deinit(padapter);\n\t\t\t}\n\t\t\trtw_set_surprise_removed(padapter);\n\t\t}\n\n\t\tpadapter->bup = _FALSE;\n\n\t\tRTW_INFO(\"<== \"FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(padapter));\n\t} else {\n\t\tRTW_INFO(\"%s: bup==_FALSE\\n\", __FUNCTION__);\n\t}\n\trtw_cancel_all_timer(padapter);\n}\n\nint rtw_suspend_free_assoc_resource(_adapter *padapter)\n{\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n#ifdef CONFIG_P2P\n\tstruct wifidirect_info\t*pwdinfo = &padapter->wdinfo;\n#endif /* CONFIG_P2P */\n\n\tRTW_INFO(\"==> \"FUNC_ADPT_FMT\" entry....\\n\", FUNC_ADPT_ARG(padapter));\n\n\tif (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) {\n\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE)\n\t\t\t&& check_fwstate(pmlmepriv, _FW_LINKED)\n\t\t\t#ifdef CONFIG_P2P\n\t\t\t&& (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)\n\t\t\t\t#if defined(CONFIG_IOCTL_CFG80211) && RTW_P2P_GROUP_INTERFACE\n\t\t\t\t|| rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)\n\t\t\t\t#endif\n\t\t\t\t)\n\t\t\t#endif /* CONFIG_P2P */\n\t\t) {\n\t\t\tRTW_INFO(\"%s %s(\" MAC_FMT \"), length:%d assoc_ssid.length:%d\\n\", __FUNCTION__,\n\t\t\t\tpmlmepriv->cur_network.network.Ssid.Ssid,\n\t\t\t\tMAC_ARG(pmlmepriv->cur_network.network.MacAddress),\n\t\t\t\tpmlmepriv->cur_network.network.Ssid.SsidLength,\n\t\t\t\tpmlmepriv->assoc_ssid.SsidLength);\n\t\t\trtw_set_to_roam(padapter, 1);\n\t\t}\n\t}\n\n\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED)) {\n\t\trtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY);\n\t\t/* s2-2.  indicate disconnect to os */\n\t\trtw_indicate_disconnect(padapter, 0, _FALSE);\n\t}\n#ifdef CONFIG_AP_MODE\n\telse if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter))\n\t\trtw_sta_flush(padapter, _TRUE);\n#endif\n\n\t/* s2-3. */\n\trtw_free_assoc_resources(padapter, _TRUE);\n\n\t/* s2-4. */\n#ifdef CONFIG_AUTOSUSPEND\n\tif (is_primary_adapter(padapter) && (!adapter_to_pwrctl(padapter)->bInternalAutoSuspend))\n#endif\n\t\trtw_free_network_queue(padapter, _TRUE);\n\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) {\n\t\tRTW_PRINT(\"%s: fw_under_survey\\n\", __func__);\n\t\trtw_indicate_scan_done(padapter, 1);\n\t\tclr_fwstate(pmlmepriv, _FW_UNDER_SURVEY);\n\t}\n\n\tif (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) {\n\t\tRTW_PRINT(\"%s: fw_under_linking\\n\", __FUNCTION__);\n\t\trtw_indicate_disconnect(padapter, 0, _FALSE);\n\t}\n\n\tRTW_INFO(\"<== \"FUNC_ADPT_FMT\" exit....\\n\", FUNC_ADPT_ARG(padapter));\n\treturn _SUCCESS;\n}\n\n#ifdef CONFIG_WOWLAN\nint rtw_suspend_wow(_adapter *padapter)\n{\n\tu8 ch, bw, offset;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tstruct wowlan_ioctl_param poidparam;\n\tu8 ps_mode;\n\tint ret = _SUCCESS;\n\n\tRTW_INFO(\"==> \"FUNC_ADPT_FMT\" entry....\\n\", FUNC_ADPT_ARG(padapter));\n\n\n\tRTW_INFO(\"wowlan_mode: %d\\n\", pwrpriv->wowlan_mode);\n\tRTW_INFO(\"wowlan_pno_enable: %d\\n\", pwrpriv->wowlan_pno_enable);\n#ifdef CONFIG_P2P_WOWLAN\n\tRTW_INFO(\"wowlan_p2p_enable: %d\\n\", pwrpriv->wowlan_p2p_enable);\n#endif\n\n\tif (pwrpriv->wowlan_mode == _TRUE) {\n\t\trtw_mi_netif_stop_queue(padapter);\n\t\t#ifdef CONFIG_CONCURRENT_MODE\n\t\trtw_mi_buddy_netif_carrier_off(padapter);\n\t\t#endif\n\n\t\t/* 0. Power off LED */\n\t\trtw_led_control(padapter, LED_CTL_POWER_OFF);\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t\t/* 2.only for SDIO disable interrupt */\n\t\trtw_intf_stop(padapter);\n\n\t\t/* 2.1 clean interrupt */\n\t\trtw_hal_clear_interrupt(padapter);\n#endif /* CONFIG_SDIO_HCI */\n\n\t\t/* 1. stop thread */\n\t\trtw_set_drv_stopped(padapter);\t/*for stop thread*/\n\t\trtw_mi_stop_drv_threads(padapter);\n\n\t\trtw_clr_drv_stopped(padapter);\t/*for 32k command*/\n\n\t\t/* #ifdef CONFIG_LPS */\n\t\t/* rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, \"WOWLAN\"); */\n\t\t/* #endif */\n\n\t\t#ifdef CONFIG_SDIO_HCI\n\t\t/* 2.2 free irq */\n\t\t#if !(CONFIG_RTW_SDIO_KEEP_IRQ)\n\t\tsdio_free_irq(adapter_to_dvobj(padapter));\n\t\t#endif\n\t\t#endif/*CONFIG_SDIO_HCI*/\n\n#ifdef CONFIG_RUNTIME_PORT_SWITCH\n\t\tif (rtw_port_switch_chk(padapter)) {\n\t\t\tRTW_INFO(\" ### PORT SWITCH ###\\n\");\n\t\t\trtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);\n\t\t}\n#endif\n\n\t\trtw_wow_lps_level_decide(padapter, _TRUE);\n\t\tpoidparam.subcode = WOWLAN_ENABLE;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam);\n\t\tif (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) {\n\t\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE)\n\t\t\t    && check_fwstate(pmlmepriv, _FW_LINKED)) {\n\t\t\t\tRTW_INFO(\"%s %s(\" MAC_FMT \"), length:%d assoc_ssid.length:%d\\n\", __FUNCTION__,\n\t\t\t\t\tpmlmepriv->cur_network.network.Ssid.Ssid,\n\t\t\t\t\tMAC_ARG(pmlmepriv->cur_network.network.MacAddress),\n\t\t\t\t\tpmlmepriv->cur_network.network.Ssid.SsidLength,\n\t\t\t\t\t pmlmepriv->assoc_ssid.SsidLength);\n\n\t\t\t\trtw_set_to_roam(padapter, 0);\n\t\t\t}\n\t\t}\n\n\t\tRTW_PRINT(\"%s: wowmode suspending\\n\", __func__);\n\n\t\tif (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) {\n\t\t\tRTW_PRINT(\"%s: fw_under_survey\\n\", __func__);\n\t\t\trtw_indicate_scan_done(padapter, 1);\n\t\t\tclr_fwstate(pmlmepriv, _FW_UNDER_SURVEY);\n\t\t}\n\n#if 1\n\t\tif (rtw_mi_check_status(padapter, MI_LINKED)) {\n\t\t\tch =  rtw_mi_get_union_chan(padapter);\n\t\t\tbw = rtw_mi_get_union_bw(padapter);\n\t\t\toffset = rtw_mi_get_union_offset(padapter);\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" back to linked/linking union - ch:%u, bw:%u, offset:%u\\n\",\n\t\t\t\t FUNC_ADPT_ARG(padapter), ch, bw, offset);\n\t\t\tset_channel_bwmode(padapter, ch, offset, bw);\n\t\t}\n#else\n\t\tif (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\" back to linked/linking union - ch:%u, bw:%u, offset:%u\\n\",\n\t\t\t\t FUNC_ADPT_ARG(padapter), ch, bw, offset);\n\t\t\tset_channel_bwmode(padapter, ch, offset, bw);\n\t\t\trtw_mi_update_union_chan_inf(padapter, ch, offset, bw);\n\t\t}\n#endif\n#ifdef CONFIG_CONCURRENT_MODE\n\t\trtw_mi_buddy_suspend_free_assoc_resource(padapter);\n#endif\n\n#ifdef CONFIG_BT_COEXIST\n\t\trtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT);\n#endif\n\n\t\tif (pwrpriv->wowlan_pno_enable) {\n\t\t\tRTW_PRINT(\"%s: pno: %d\\n\", __func__,\n\t\t\t\t  pwrpriv->wowlan_pno_enable);\n#ifdef CONFIG_FWLPS_IN_IPS\n\t\t\trtw_set_fw_in_ips_mode(padapter, _TRUE);\n#endif\n\t\t}\n#ifdef CONFIG_LPS\n\t\telse {\n\t\t\tif(pwrpriv->wowlan_power_mgmt != PS_MODE_ACTIVE) {\n\t\t\t\trtw_set_ps_mode(padapter, pwrpriv->wowlan_power_mgmt, 0, 0, \"WOWLAN\");\n\t\t\t}\n\t\t}\n#endif /* #ifdef CONFIG_LPS */\n\n\t} else\n\t\tRTW_PRINT(\"%s: ### ERROR ### wowlan_mode=%d\\n\", __FUNCTION__, pwrpriv->wowlan_mode);\n\tRTW_INFO(\"<== \"FUNC_ADPT_FMT\" exit....\\n\", FUNC_ADPT_ARG(padapter));\n\treturn ret;\n}\n#endif /* #ifdef CONFIG_WOWLAN */\n\n#ifdef CONFIG_AP_WOWLAN\nint rtw_suspend_ap_wow(_adapter *padapter)\n{\n\tu8 ch, bw, offset;\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tstruct wowlan_ioctl_param poidparam;\n\tu8 ps_mode;\n\tint ret = _SUCCESS;\n\n\tRTW_INFO(\"==> \"FUNC_ADPT_FMT\" entry....\\n\", FUNC_ADPT_ARG(padapter));\n\n\tpwrpriv->wowlan_ap_mode = _TRUE;\n\n\tRTW_INFO(\"wowlan_ap_mode: %d\\n\", pwrpriv->wowlan_ap_mode);\n\n\trtw_mi_netif_stop_queue(padapter);\n\n\t/* 0. Power off LED */\n\trtw_led_control(padapter, LED_CTL_POWER_OFF);\n#ifdef CONFIG_SDIO_HCI\n\t/* 2.only for SDIO disable interrupt*/\n\trtw_intf_stop(padapter);\n\n\t/* 2.1 clean interrupt */\n\trtw_hal_clear_interrupt(padapter);\n#endif /* CONFIG_SDIO_HCI */\n\n\t/* 1. stop thread */\n\trtw_set_drv_stopped(padapter);\t/*for stop thread*/\n\trtw_mi_stop_drv_threads(padapter);\n\trtw_clr_drv_stopped(padapter);\t/*for 32k command*/\n\n\t#ifdef CONFIG_SDIO_HCI\n\t/* 2.2 free irq */\n\t#if !(CONFIG_RTW_SDIO_KEEP_IRQ)\n\tsdio_free_irq(adapter_to_dvobj(padapter));\n\t#endif\n\t#endif/*CONFIG_SDIO_HCI*/\n\n#ifdef CONFIG_RUNTIME_PORT_SWITCH\n\tif (rtw_port_switch_chk(padapter)) {\n\t\tRTW_INFO(\" ### PORT SWITCH ###\\n\");\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);\n\t}\n#endif\n\n\trtw_wow_lps_level_decide(padapter, _TRUE);\n\tpoidparam.subcode = WOWLAN_AP_ENABLE;\n\trtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam);\n\n\tRTW_PRINT(\"%s: wowmode suspending\\n\", __func__);\n#if 1\n\tif (rtw_mi_check_status(padapter, MI_LINKED)) {\n\t\tch =  rtw_mi_get_union_chan(padapter);\n\t\tbw = rtw_mi_get_union_bw(padapter);\n\t\toffset = rtw_mi_get_union_offset(padapter);\n\t\tRTW_INFO(\"back to linked/linking union - ch:%u, bw:%u, offset:%u\\n\", ch, bw, offset);\n\t\tset_channel_bwmode(padapter, ch, offset, bw);\n\t}\n#else\n\tif (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) {\n\t\tRTW_INFO(\"back to linked/linking union - ch:%u, bw:%u, offset:%u\\n\", ch, bw, offset);\n\t\tset_channel_bwmode(padapter, ch, offset, bw);\n\t\trtw_mi_update_union_chan_inf(padapter, ch, offset, bw);\n\t}\n#endif\n\n\t/*FOR ONE AP - TODO :Multi-AP*/\n\t{\n\t\tint i;\n\t\t_adapter *iface;\n\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tif ((iface) && rtw_is_adapter_up(iface)) {\n\t\t\t\tif (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE) == _FALSE)\n\t\t\t\t\trtw_suspend_free_assoc_resource(iface);\n\t\t\t}\n\t\t}\n\n\t}\n\n#ifdef CONFIG_BT_COEXIST\n\trtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT);\n#endif\n\n#ifdef CONFIG_LPS\n\tif(pwrpriv->wowlan_power_mgmt != PS_MODE_ACTIVE) {\n\t\trtw_set_ps_mode(padapter, pwrpriv->wowlan_power_mgmt, 0, 0, \"AP-WOWLAN\");\n\t}\n#endif\n\n\tRTW_INFO(\"<== \"FUNC_ADPT_FMT\" exit....\\n\", FUNC_ADPT_ARG(padapter));\n\treturn ret;\n}\n#endif /* #ifdef CONFIG_AP_WOWLAN */\n\n\nint rtw_suspend_normal(_adapter *padapter)\n{\n\tint ret = _SUCCESS;\n\n\tRTW_INFO(\"==> \"FUNC_ADPT_FMT\" entry....\\n\", FUNC_ADPT_ARG(padapter));\n\n#ifdef CONFIG_BT_COEXIST\n\trtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND);\n#endif\n\trtw_mi_netif_caroff_qstop(padapter);\n\n\trtw_mi_suspend_free_assoc_resource(padapter);\n\n\trtw_led_control(padapter, LED_CTL_POWER_OFF);\n\n\tif ((rtw_hal_check_ips_status(padapter) == _TRUE)\n\t    || (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off))\n\t\tRTW_PRINT(\"%s: ### ERROR #### driver in IPS ####ERROR###!!!\\n\", __FUNCTION__);\n\n\n#ifdef CONFIG_CONCURRENT_MODE\n\trtw_set_drv_stopped(padapter);\t/*for stop thread*/\n\trtw_stop_cmd_thread(padapter);\n\trtw_drv_stop_vir_ifaces(adapter_to_dvobj(padapter));\n#endif\n\trtw_dev_unload(padapter);\n\n\t#ifdef CONFIG_SDIO_HCI\n\tsdio_deinit(adapter_to_dvobj(padapter));\n\n\t#if !(CONFIG_RTW_SDIO_KEEP_IRQ)\n\tsdio_free_irq(adapter_to_dvobj(padapter));\n\t#endif\n\t#endif /*CONFIG_SDIO_HCI*/\n\n\tRTW_INFO(\"<== \"FUNC_ADPT_FMT\" exit....\\n\", FUNC_ADPT_ARG(padapter));\n\treturn ret;\n}\n\nint rtw_suspend_common(_adapter *padapter)\n{\n\tstruct dvobj_priv *dvobj = padapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &dvobj->drv_dbg;\n\tstruct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);\n#ifdef CONFIG_WOWLAN\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n#endif\n\n\tint ret = 0;\n\tsystime start_time = rtw_get_current_time();\n\n\tRTW_PRINT(\" suspend start\\n\");\n\tRTW_INFO(\"==> %s (%s:%d)\\n\", __FUNCTION__, current->comm, current->pid);\n\n\tpdbgpriv->dbg_suspend_cnt++;\n\n\tpwrpriv->bInSuspend = _TRUE;\n\n\twhile (pwrpriv->bips_processing == _TRUE)\n\t\trtw_msleep_os(1);\n\n#ifdef CONFIG_IOL_READ_EFUSE_MAP\n\tif (!padapter->bup) {\n\t\tu8 bMacPwrCtrlOn = _FALSE;\n\t\trtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);\n\t\tif (bMacPwrCtrlOn)\n\t\t\trtw_hal_power_off(padapter);\n\t}\n#endif\n\n\tif ((!padapter->bup) || RTW_CANNOT_RUN(padapter)) {\n\t\tRTW_INFO(\"%s bup=%d bDriverStopped=%s bSurpriseRemoved = %s\\n\", __func__\n\t\t\t , padapter->bup\n\t\t\t , rtw_is_drv_stopped(padapter) ? \"True\" : \"False\"\n\t\t\t, rtw_is_surprise_removed(padapter) ? \"True\" : \"False\");\n\t\tpdbgpriv->dbg_suspend_error_cnt++;\n\t\tgoto exit;\n\t}\n\trtw_ps_deny(padapter, PS_DENY_SUSPEND);\n\n\trtw_mi_cancel_all_timer(padapter);\n\tLeaveAllPowerSaveModeDirect(padapter);\n\n\trtw_ps_deny_cancel(padapter, PS_DENY_SUSPEND);\n\n\tif (rtw_mi_check_status(padapter, MI_AP_MODE) == _FALSE) {\n#ifdef CONFIG_WOWLAN\n\t\tif (check_fwstate(pmlmepriv, _FW_LINKED) || WOWLAN_IS_STA_MIX_MODE(padapter))\n\t\t\tpwrpriv->wowlan_mode = _TRUE;\n\t\telse if (pwrpriv->wowlan_pno_enable == _TRUE)\n\t\t\tpwrpriv->wowlan_mode |= pwrpriv->wowlan_pno_enable;\n\n#ifdef CONFIG_P2P_WOWLAN\n\t\tif (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE) || P2P_ROLE_DISABLE != padapter->wdinfo.role)\n\t\t\tpwrpriv->wowlan_p2p_mode = _TRUE;\n\t\tif (_TRUE == pwrpriv->wowlan_p2p_mode)\n\t\t\tpwrpriv->wowlan_mode |= pwrpriv->wowlan_p2p_mode;\n#endif /* CONFIG_P2P_WOWLAN */\n\n\t\tif (pwrpriv->wowlan_mode == _TRUE)\n\t\t\trtw_suspend_wow(padapter);\n\t\telse\n#endif /* CONFIG_WOWLAN */\n\t\t\trtw_suspend_normal(padapter);\n\t} else if (rtw_mi_check_status(padapter, MI_AP_MODE)) {\n#ifdef CONFIG_AP_WOWLAN\n\t\trtw_suspend_ap_wow(padapter);\n#else\n\t\trtw_suspend_normal(padapter);\n#endif /*CONFIG_AP_WOWLAN*/\n\t}\n\n\n\tRTW_PRINT(\"rtw suspend success in %d ms\\n\",\n\t\t  rtw_get_passing_time_ms(start_time));\n\nexit:\n\tRTW_INFO(\"<===  %s return %d.............. in %dms\\n\", __FUNCTION__\n\t\t , ret, rtw_get_passing_time_ms(start_time));\n\n\treturn ret;\n}\n\n#ifdef CONFIG_WOWLAN\nint rtw_resume_process_wow(_adapter *padapter)\n{\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct mlme_ext_info\t*pmlmeinfo = &(pmlmeext->mlmext_info);\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tstruct dvobj_priv *psdpriv = padapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &psdpriv->drv_dbg;\n\tstruct wowlan_ioctl_param poidparam;\n\tstruct sta_info\t*psta = NULL;\n\tstruct registry_priv  *registry_par = &padapter->registrypriv;\n\tint ret = _SUCCESS;\n\n\tRTW_INFO(\"==> \"FUNC_ADPT_FMT\" entry....\\n\", FUNC_ADPT_ARG(padapter));\n\n\tif (padapter) {\n\t\tpwrpriv = adapter_to_pwrctl(padapter);\n\t} else {\n\t\tpdbgpriv->dbg_resume_error_cnt++;\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\n\tif (RTW_CANNOT_RUN(padapter)) {\n\t\tRTW_INFO(\"%s pdapter %p bDriverStopped %s bSurpriseRemoved %s\\n\"\n\t\t\t , __func__, padapter\n\t\t\t , rtw_is_drv_stopped(padapter) ? \"True\" : \"False\"\n\t\t\t, rtw_is_surprise_removed(padapter) ? \"True\" : \"False\");\n\t\tgoto exit;\n\t}\n\n\tpwrpriv->wowlan_in_resume = _TRUE;\n#ifdef CONFIG_PNO_SUPPORT\n#ifdef CONFIG_FWLPS_IN_IPS\n\tif (pwrpriv->wowlan_pno_enable)\n\t\trtw_set_fw_in_ips_mode(padapter, _FALSE);\n#endif /* CONFIG_FWLPS_IN_IPS */\n#endif/* CONFIG_PNO_SUPPORT */\n\n\tif (pwrpriv->wowlan_mode == _TRUE) {\n#ifdef CONFIG_LPS\n\t\tif(pwrpriv->wowlan_power_mgmt != PS_MODE_ACTIVE) {\n\t\t\trtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, \"WOWLAN\");\n\t\t\trtw_wow_lps_level_decide(padapter, _FALSE);\n\t\t}\n#endif /* CONFIG_LPS */\n\n\t\tpwrpriv->bFwCurrentInPSMode = _FALSE;\n\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_PCI_HCI)\n\t\trtw_mi_intf_stop(padapter);\n\t\trtw_hal_clear_interrupt(padapter);\n#endif\n\n\t\t#ifdef CONFIG_SDIO_HCI\n\t\t#if !(CONFIG_RTW_SDIO_KEEP_IRQ)\n\t\tif (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) {\n\t\t\tret = -1;\n\t\t\tgoto exit;\n\t\t}\n\t\t#endif\n\t\t#endif/*CONFIG_SDIO_HCI*/\n\n\t\t/* Disable WOW, set H2C command */\n\t\tpoidparam.subcode = WOWLAN_DISABLE;\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t\trtw_mi_buddy_reset_drv_sw(padapter);\n#endif\n\n\t\tpsta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));\n\t\tif (psta)\n\t\t\tset_sta_rate(padapter, psta);\n\n\n\t\trtw_clr_drv_stopped(padapter);\n\t\tRTW_INFO(\"%s: wowmode resuming, DriverStopped:%s\\n\", __func__, rtw_is_drv_stopped(padapter) ? \"True\" : \"False\");\n\n\t\trtw_mi_start_drv_threads(padapter);\n\n\t\trtw_mi_intf_start(padapter);\n\t\t\n\t\tif(registry_par->suspend_type == FW_IPS_DISABLE_BBRF && !check_fwstate(pmlmepriv, _FW_LINKED)) {\n\t\t\tif (!rtw_is_surprise_removed(padapter)) {\n\t\t\t\trtw_hal_deinit(padapter);\n\t\t\t\trtw_hal_init(padapter);\n\t\t\t}\n\t\t\tRTW_INFO(\"FW_IPS_DISABLE_BBRF hal deinit, hal init \\n\");\n\t\t}\n\n#ifdef CONFIG_CONCURRENT_MODE\n\t\trtw_mi_buddy_netif_carrier_on(padapter);\n#endif\n\n\t\t/* start netif queue */\n\t\trtw_mi_netif_wake_queue(padapter);\n\n\t} else\n\n\t\tRTW_PRINT(\"%s: ### ERROR ### wowlan_mode=%d\\n\", __FUNCTION__, pwrpriv->wowlan_mode);\n\n\tif (padapter->pid[1] != 0) {\n\t\tRTW_INFO(\"pid[1]:%d\\n\", padapter->pid[1]);\n\t\trtw_signal_process(padapter->pid[1], SIGUSR2);\n\t}\n\n\tif (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) {\n\t\tif (pwrpriv->wowlan_wake_reason == FW_DECISION_DISCONNECT ||\n\t\t    pwrpriv->wowlan_wake_reason == RX_DISASSOC||\n\t\t    pwrpriv->wowlan_wake_reason == RX_DEAUTH) {\n\n\t\t\tRTW_INFO(\"%s: disconnect reason: %02x\\n\", __func__,\n\t\t\t\t pwrpriv->wowlan_wake_reason);\n\t\t\trtw_indicate_disconnect(padapter, 0, _FALSE);\n\n\t\t\trtw_sta_media_status_rpt(padapter,\n\t\t\t\t\t rtw_get_stainfo(&padapter->stapriv,\n\t\t\t\t\t get_bssid(&padapter->mlmepriv)), 0);\n\n\t\t\trtw_free_assoc_resources(padapter, _TRUE);\n\t\t\tpmlmeinfo->state = WIFI_FW_NULL_STATE;\n\n\t\t} else {\n\t\t\tRTW_INFO(\"%s: do roaming\\n\", __func__);\n\t\t\trtw_roaming(padapter, NULL);\n\t\t}\n\t}\n\n\tif (pwrpriv->wowlan_mode == _TRUE) {\n\t\tpwrpriv->bips_processing = _FALSE;\n\t\t_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);\n#ifndef CONFIG_IPS_CHECK_IN_WD\n\t\trtw_set_pwr_state_check_timer(pwrpriv);\n#endif\n\t} else\n\t\tRTW_PRINT(\"do not reset timer\\n\");\n\n\tpwrpriv->wowlan_mode = _FALSE;\n\n\t/* Power On LED */\n#ifdef CONFIG_RTW_SW_LED\n\n\tif (pwrpriv->wowlan_wake_reason == RX_DISASSOC||\n\t    pwrpriv->wowlan_wake_reason == RX_DEAUTH||\n\t    pwrpriv->wowlan_wake_reason == FW_DECISION_DISCONNECT)\n\t\trtw_led_control(padapter, LED_CTL_NO_LINK);\n\telse\n\t\trtw_led_control(padapter, LED_CTL_LINK);\n#endif\n\t/* clean driver side wake up reason. */\n\tpwrpriv->wowlan_last_wake_reason = pwrpriv->wowlan_wake_reason;\n\tpwrpriv->wowlan_wake_reason = 0;\n\n#ifdef CONFIG_BT_COEXIST\n\trtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME);\n#endif /* CONFIG_BT_COEXIST */\n\nexit:\n\tRTW_INFO(\"<== \"FUNC_ADPT_FMT\" exit....\\n\", FUNC_ADPT_ARG(padapter));\n\treturn ret;\n}\n#endif /* #ifdef CONFIG_WOWLAN */\n\n#ifdef CONFIG_AP_WOWLAN\nint rtw_resume_process_ap_wow(_adapter *padapter)\n{\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tstruct dvobj_priv *psdpriv = padapter->dvobj;\n\tstruct debug_priv *pdbgpriv = &psdpriv->drv_dbg;\n\tstruct wowlan_ioctl_param poidparam;\n\tstruct sta_info\t*psta = NULL;\n\tint ret = _SUCCESS;\n\tu8 ch, bw, offset;\n\n\tRTW_INFO(\"==> \"FUNC_ADPT_FMT\" entry....\\n\", FUNC_ADPT_ARG(padapter));\n\n\tif (padapter) {\n\t\tpwrpriv = adapter_to_pwrctl(padapter);\n\t} else {\n\t\tpdbgpriv->dbg_resume_error_cnt++;\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\n\n#ifdef CONFIG_LPS\n\tif(pwrpriv->wowlan_power_mgmt != PS_MODE_ACTIVE) {\n\t\trtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, \"AP-WOWLAN\");\n\t\trtw_wow_lps_level_decide(padapter, _FALSE);\n\t}\n#endif /* CONFIG_LPS */\n\n\tpwrpriv->bFwCurrentInPSMode = _FALSE;\n\n\trtw_hal_disable_interrupt(padapter);\n\n\trtw_hal_clear_interrupt(padapter);\n\n\t#ifdef CONFIG_SDIO_HCI\n\t#if !(CONFIG_RTW_SDIO_KEEP_IRQ)\n\tif (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) {\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\t#endif\n\t#endif/*CONFIG_SDIO_HCI*/\n\t/* Disable WOW, set H2C command */\n\tpoidparam.subcode = WOWLAN_AP_DISABLE;\n\trtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam);\n\tpwrpriv->wowlan_ap_mode = _FALSE;\n\n\trtw_clr_drv_stopped(padapter);\n\tRTW_INFO(\"%s: wowmode resuming, DriverStopped:%s\\n\", __func__, rtw_is_drv_stopped(padapter) ? \"True\" : \"False\");\n\n\trtw_mi_start_drv_threads(padapter);\n\n#if 1\n\tif (rtw_mi_check_status(padapter, MI_LINKED)) {\n\t\tch =  rtw_mi_get_union_chan(padapter);\n\t\tbw = rtw_mi_get_union_bw(padapter);\n\t\toffset = rtw_mi_get_union_offset(padapter);\n\t\tRTW_INFO(FUNC_ADPT_FMT\" back to linked/linking union - ch:%u, bw:%u, offset:%u\\n\", FUNC_ADPT_ARG(padapter), ch, bw, offset);\n\t\tset_channel_bwmode(padapter, ch, offset, bw);\n\t}\n#else\n\tif (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) {\n\t\tRTW_INFO(FUNC_ADPT_FMT\" back to linked/linking union - ch:%u, bw:%u, offset:%u\\n\", FUNC_ADPT_ARG(padapter), ch, bw, offset);\n\t\tset_channel_bwmode(padapter, ch, offset, bw);\n\t\trtw_mi_update_union_chan_inf(padapter, ch, offset, bw);\n\t}\n#endif\n\n\t/*FOR ONE AP - TODO :Multi-AP*/\n\t{\n\t\tint i;\n\t\t_adapter *iface;\n\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tif ((iface) && rtw_is_adapter_up(iface)) {\n\t\t\t\tif (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE | _FW_LINKED))\n\t\t\t\t\trtw_reset_drv_sw(iface);\n\t\t\t}\n\t\t}\n\n\t}\n\trtw_mi_intf_start(padapter);\n\n\t/* start netif queue */\n\trtw_mi_netif_wake_queue(padapter);\n\n\tif (padapter->pid[1] != 0) {\n\t\tRTW_INFO(\"pid[1]:%d\\n\", padapter->pid[1]);\n\t\trtw_signal_process(padapter->pid[1], SIGUSR2);\n\t}\n\n#ifdef CONFIG_RESUME_IN_WORKQUEUE\n\t/* rtw_unlock_suspend(); */\n#endif /* CONFIG_RESUME_IN_WORKQUEUE */\n\n\tpwrpriv->bips_processing = _FALSE;\n\t_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);\n#ifndef CONFIG_IPS_CHECK_IN_WD\n\trtw_set_pwr_state_check_timer(pwrpriv);\n#endif\n\t/* clean driver side wake up reason. */\n\tpwrpriv->wowlan_wake_reason = 0;\n\n#ifdef CONFIG_BT_COEXIST\n\trtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME);\n#endif /* CONFIG_BT_COEXIST */\n\n\t/* Power On LED */\n#ifdef CONFIG_RTW_SW_LED\n\n\trtw_led_control(padapter, LED_CTL_LINK);\n#endif\nexit:\n\tRTW_INFO(\"<== \"FUNC_ADPT_FMT\" exit....\\n\", FUNC_ADPT_ARG(padapter));\n\treturn ret;\n}\n#endif /* #ifdef CONFIG_APWOWLAN */\n\nvoid rtw_mi_resume_process_normal(_adapter *padapter)\n{\n\tint i;\n\t_adapter *iface;\n\tstruct mlme_priv *pmlmepriv;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif ((iface) && rtw_is_adapter_up(iface)) {\n\t\t\tpmlmepriv = &iface->mlmepriv;\n\n\t\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" fwstate:0x%08x - WIFI_STATION_STATE\\n\", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv));\n\n\t\t\t\tif (rtw_chk_roam_flags(iface, RTW_ROAM_ON_RESUME))\n\t\t\t\t\trtw_roaming(iface, NULL);\n\n\t\t\t} else if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) {\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" %s\\n\", FUNC_ADPT_ARG(iface), MLME_IS_AP(iface) ? \"AP\" : \"MESH\");\n\t\t\t\trtw_ap_restore_network(iface);\n\t\t\t} else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE))\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" fwstate:0x%08x - WIFI_ADHOC_STATE\\n\", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv));\n\t\t\telse\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\" fwstate:0x%08x - ???\\n\", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv));\n\t\t}\n\t}\n}\n\nint rtw_resume_process_normal(_adapter *padapter)\n{\n\tstruct net_device *pnetdev;\n\tstruct pwrctrl_priv *pwrpriv;\n\tstruct dvobj_priv *psdpriv;\n\tstruct debug_priv *pdbgpriv;\n\n\tint ret = _SUCCESS;\n\n\tif (!padapter) {\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\n\tpnetdev = padapter->pnetdev;\n\tpwrpriv = adapter_to_pwrctl(padapter);\n\tpsdpriv = padapter->dvobj;\n\tpdbgpriv = &psdpriv->drv_dbg;\n\n\tRTW_INFO(\"==> \"FUNC_ADPT_FMT\" entry....\\n\", FUNC_ADPT_ARG(padapter));\n\n\t#ifdef CONFIG_SDIO_HCI\n\t/* interface init */\n\tif (sdio_init(adapter_to_dvobj(padapter)) != _SUCCESS) {\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\t#endif/*CONFIG_SDIO_HCI*/\n\n\trtw_clr_surprise_removed(padapter);\n\trtw_hal_disable_interrupt(padapter);\n\n\t#ifdef CONFIG_SDIO_HCI\n\t#if !(CONFIG_RTW_SDIO_KEEP_IRQ)\n\tif (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) {\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\t#endif\n\t#endif/*CONFIG_SDIO_HCI*/\n\n\trtw_mi_reset_drv_sw(padapter);\n\n\tpwrpriv->bkeepfwalive = _FALSE;\n\n\tRTW_INFO(\"bkeepfwalive(%x)\\n\", pwrpriv->bkeepfwalive);\n\tif (pm_netdev_open(pnetdev, _TRUE) != 0) {\n\t\tret = -1;\n\t\tpdbgpriv->dbg_resume_error_cnt++;\n\t\tgoto exit;\n\t}\n\n\trtw_mi_netif_caron_qstart(padapter);\n\n\tif (padapter->pid[1] != 0) {\n\t\tRTW_INFO(\"pid[1]:%d\\n\", padapter->pid[1]);\n\t\trtw_signal_process(padapter->pid[1], SIGUSR2);\n\t}\n\n#ifdef CONFIG_BT_COEXIST\n\trtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME);\n#endif /* CONFIG_BT_COEXIST */\n\n\trtw_mi_resume_process_normal(padapter);\n\n#ifdef CONFIG_RESUME_IN_WORKQUEUE\n\t/* rtw_unlock_suspend(); */\n#endif /* CONFIG_RESUME_IN_WORKQUEUE */\n\tRTW_INFO(\"<== \"FUNC_ADPT_FMT\" exit....\\n\", FUNC_ADPT_ARG(padapter));\n\nexit:\n\treturn ret;\n}\n\nint rtw_resume_common(_adapter *padapter)\n{\n\tint ret = 0;\n\tsystime start_time = rtw_get_current_time();\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\n\tif (pwrpriv->bInSuspend == _FALSE)\n\t\treturn 0;\n\n\tRTW_PRINT(\"resume start\\n\");\n\tRTW_INFO(\"==> %s (%s:%d)\\n\", __FUNCTION__, current->comm, current->pid);\n\n\tif (rtw_mi_check_status(padapter, MI_AP_MODE) == _FALSE) {\n#ifdef CONFIG_WOWLAN\n\t\tif (pwrpriv->wowlan_mode == _TRUE)\n\t\t\trtw_resume_process_wow(padapter);\n\t\telse\n#endif\n\t\t\trtw_resume_process_normal(padapter);\n\n\t} else if (rtw_mi_check_status(padapter, MI_AP_MODE)) {\n#ifdef CONFIG_AP_WOWLAN\n\t\trtw_resume_process_ap_wow(padapter);\n#else\n\t\trtw_resume_process_normal(padapter);\n#endif /* CONFIG_AP_WOWLAN */\n\t}\n\n\tif (pwrpriv) {\n\t\tpwrpriv->bInSuspend = _FALSE;\n\t\tpwrpriv->wowlan_in_resume = _FALSE;\n\t}\n\tRTW_PRINT(\"%s:%d in %d ms\\n\", __FUNCTION__ , ret,\n\t\t  rtw_get_passing_time_ms(start_time));\n\n\n\treturn ret;\n}\n\n#ifdef CONFIG_GPIO_API\nu8 rtw_get_gpio(struct net_device *netdev, u8 gpio_num)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);\n\treturn rtw_hal_get_gpio(adapter, gpio_num);\n}\nEXPORT_SYMBOL(rtw_get_gpio);\n\nint  rtw_set_gpio_output_value(struct net_device *netdev, u8 gpio_num, bool isHigh)\n{\n\tu8 direction = 0;\n\tu8 res = -1;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);\n\treturn rtw_hal_set_gpio_output_value(adapter, gpio_num, isHigh);\n}\nEXPORT_SYMBOL(rtw_set_gpio_output_value);\n\nint rtw_config_gpio(struct net_device *netdev, u8 gpio_num, bool isOutput)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);\n\treturn rtw_hal_config_gpio(adapter, gpio_num, isOutput);\n}\nEXPORT_SYMBOL(rtw_config_gpio);\nint rtw_register_gpio_interrupt(struct net_device *netdev, int gpio_num, void(*callback)(u8 level))\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);\n\treturn rtw_hal_register_gpio_interrupt(adapter, gpio_num, callback);\n}\nEXPORT_SYMBOL(rtw_register_gpio_interrupt);\n\nint rtw_disable_gpio_interrupt(struct net_device *netdev, int gpio_num)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);\n\treturn rtw_hal_disable_gpio_interrupt(adapter, gpio_num);\n}\nEXPORT_SYMBOL(rtw_disable_gpio_interrupt);\n\n#endif /* #ifdef CONFIG_GPIO_API */\n\n#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE\n\nint rtw_vendor_ie_get_api(struct net_device *dev, int ie_num, char *extra,\n\t\tu16 extra_len)\n{\n\tint ret = 0;\n\n\tret = rtw_vendor_ie_get_raw_data(dev, ie_num, extra, extra_len);\n\treturn ret;\n}\nEXPORT_SYMBOL(rtw_vendor_ie_get_api);\n\nint rtw_vendor_ie_set_api(struct net_device *dev, char *extra)\n{\n\treturn rtw_vendor_ie_set(dev, NULL, NULL, extra);\n}\nEXPORT_SYMBOL(rtw_vendor_ie_set_api);\n\n#endif\n\t\n"
  },
  {
    "path": "os_dep/linux/pci_intf.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _HCI_INTF_C_\n\n#include <drv_types.h>\n#include <hal_data.h>\n\n#include <linux/pci_regs.h>\n\n#ifndef CONFIG_PCI_HCI\n\n\t#error \"CONFIG_PCI_HCI shall be on!\\n\"\n\n#endif\n\n\n#ifdef CONFIG_80211N_HT\n\textern int rtw_ht_enable;\n\textern int rtw_bw_mode;\n\textern int rtw_ampdu_enable;/* for enable tx_ampdu */\n#endif\n\n#ifdef CONFIG_GLOBAL_UI_PID\nint ui_pid[3] = {0, 0, 0};\n#endif\n\nextern int pm_netdev_open(struct net_device *pnetdev, u8 bnormal);\nint rtw_resume_process(_adapter *padapter);\n\n#ifdef CONFIG_PM\n\tstatic int rtw_pci_suspend(struct pci_dev *pdev, pm_message_t state);\n\tstatic int rtw_pci_resume(struct pci_dev *pdev);\n#endif\n\nstatic int rtw_drv_init(struct pci_dev *pdev, const struct pci_device_id *pdid);\nstatic void rtw_dev_remove(struct pci_dev *pdev);\nstatic void rtw_dev_shutdown(struct pci_dev *pdev);\n\nstatic struct specific_device_id specific_device_id_tbl[] = {\n\t{.idVendor = 0x0b05, .idProduct = 0x1791, .flags = SPEC_DEV_ID_DISABLE_HT},\n\t{.idVendor = 0x13D3, .idProduct = 0x3311, .flags = SPEC_DEV_ID_DISABLE_HT},\n\t{}\n};\n\nstruct pci_device_id rtw_pci_id_tbl[] = {\n#ifdef CONFIG_RTL8188E\n\t{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8179), .driver_data = RTL8188E},\n#endif\n#ifdef CONFIG_RTL8812A\n\t{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8812), .driver_data = RTL8812},\n#endif\n#ifdef CONFIG_RTL8821A\n\t{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8821), .driver_data = RTL8821},\n#endif\n#ifdef CONFIG_RTL8192E\n\t{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x818B), .driver_data = RTL8192E},\n#endif\n#ifdef CONFIG_RTL8192F\n\t{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xf192), .driver_data = RTL8192F},\n#endif\n#ifdef CONFIG_RTL8723B\n\t{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xb723), .driver_data = RTL8723B},\n#endif\n#ifdef CONFIG_RTL8723D\n\t{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xd723), .driver_data = RTL8723D},\n#endif\n#ifdef CONFIG_RTL8814A\n\t{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8813), .driver_data = RTL8814A},\n#endif\n#ifdef CONFIG_RTL8822B\n\t{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xB822), .driver_data = RTL8822B},\n#endif\n#ifdef CONFIG_RTL8821C\n\t{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xC821), .driver_data = RTL8821C},\n\t{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xC82A), .driver_data = RTL8821C},\n\t{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xC82B), .driver_data = RTL8821C},\n#endif\n#ifdef CONFIG_RTL8822C\n\t{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xC822), .driver_data = RTL8822C},\n\t{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xC82F), .driver_data = RTL8822C},\n#endif\n\t{},\n};\n\nstruct pci_drv_priv {\n\tstruct pci_driver rtw_pci_drv;\n\tint drv_registered;\n};\n\n\nstatic struct pci_drv_priv pci_drvpriv = {\n\t.rtw_pci_drv.name = (char *)DRV_NAME,\n\t.rtw_pci_drv.probe = rtw_drv_init,\n\t.rtw_pci_drv.remove = rtw_dev_remove,\n\t.rtw_pci_drv.shutdown = rtw_dev_shutdown,\n\t.rtw_pci_drv.id_table = rtw_pci_id_tbl,\n#ifdef CONFIG_PM\n\t.rtw_pci_drv.suspend = rtw_pci_suspend,\n\t.rtw_pci_drv.resume = rtw_pci_resume,\n#endif\n};\n\n\nMODULE_DEVICE_TABLE(pci, rtw_pci_id_tbl);\n\n\nstatic u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {\n\tINTEL_VENDOR_ID,\n\tATI_VENDOR_ID,\n\tAMD_VENDOR_ID,\n\tSIS_VENDOR_ID\n};\n\n#define PCI_PM_CAP_ID\t\t0x01\t/* The Capability ID for PME function */\nvoid\tPlatformClearPciPMEStatus(PADAPTER Adapter)\n{\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(Adapter);\n\tstruct pci_dev\t*pdev = pdvobjpriv->ppcidev;\n\tBOOLEAN\t\tPCIClkReq = _FALSE;\n\tu8\tCapId = 0xff;\n\tu8\tCapPointer = 0;\n\t/* u16\tCapHdr; */\n\tRT_PCI_CAPABILITIES_HEADER CapHdr;\n\tu8\tPMCSReg;\n\tint\tresult;\n\n\t/* Get the Capability pointer first, */\n\t/* the Capability Pointer is located at offset 0x34 from the Function Header */\n\n\tresult = pci_read_config_byte(pdev, 0x34, &CapPointer);\n\tif (result != 0)\n\t\tRTW_INFO(\"%s() pci_read_config_byte 0x34 Failed!\\n\", __func__);\n\telse {\n\t\tRTW_INFO(\"PlatformClearPciPMEStatus(): PCI configration 0x34 = 0x%2x\\n\", CapPointer);\n\t\tdo {\n\t\t\t/* end of pci capability */\n\t\t\tif (CapPointer == 0x00) {\n\t\t\t\tCapId = 0xff;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* result = pci_read_config_word(pdev, CapPointer, &CapHdr); */\n\t\t\tresult = pci_read_config_byte(pdev, CapPointer, &CapHdr.CapabilityID);\n\t\t\tif (result != 0) {\n\t\t\t\tRTW_INFO(\"%s() pci_read_config_byte %x Failed!\\n\", __func__, CapPointer);\n\t\t\t\tCapId = 0xff;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tresult = pci_read_config_byte(pdev, CapPointer + 1, &CapHdr.Next);\n\t\t\tif (result != 0) {\n\t\t\t\tRTW_INFO(\"%s() pci_read_config_byte %x Failed!\\n\", __func__, CapPointer);\n\t\t\t\tCapId = 0xff;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* CapId = CapHdr & 0xFF; */\n\t\t\tCapId = CapHdr.CapabilityID;\n\n\t\t\tRTW_INFO(\"PlatformClearPciPMEStatus(): in pci configration1, CapPointer%x = %x\\n\", CapPointer, CapId);\n\n\t\t\tif (CapId == PCI_PM_CAP_ID)\n\t\t\t\tbreak;\n\t\t\telse {\n\t\t\t\t/* point to next Capability */\n\t\t\t\t/* CapPointer = (CapHdr >> 8) & 0xFF; */\n\t\t\t\tCapPointer = CapHdr.Next;\n\t\t\t}\n\t\t} while (_TRUE);\n\n\t\tif (CapId == PCI_PM_CAP_ID) {\n\t\t\t/* Get the PM CSR (Control/Status Register), */\n\t\t\t/* The PME_Status is located at PM Capatibility offset 5, bit 7 */\n\t\t\tresult = pci_read_config_byte(pdev, CapPointer + 5, &PMCSReg);\n\t\t\tif (PMCSReg & BIT7) {\n\t\t\t\t/* PME event occured, clear the PM_Status by write 1 */\n\t\t\t\tPMCSReg = PMCSReg | BIT7;\n\n\t\t\t\tpci_write_config_byte(pdev, CapPointer + 5, PMCSReg);\n\t\t\t\tPCIClkReq = _TRUE;\n\t\t\t\t/* Read it back to check */\n\t\t\t\tpci_read_config_byte(pdev, CapPointer + 5, &PMCSReg);\n\t\t\t\tRTW_INFO(\"PlatformClearPciPMEStatus(): Clear PME status 0x%2x to 0x%2x\\n\", CapPointer + 5, PMCSReg);\n\t\t\t} else\n\t\t\t\tRTW_INFO(\"PlatformClearPciPMEStatus(): PME status(0x%2x) = 0x%2x\\n\", CapPointer + 5, PMCSReg);\n\t\t} else\n\t\t\tRTW_INFO(\"PlatformClearPciPMEStatus(): Cannot find PME Capability\\n\");\n\t}\n\n\tRTW_INFO(\"PME, value_offset = %x, PME EN = %x\\n\", CapPointer + 5, PCIClkReq);\n}\n\nvoid rtw_pci_aspm_config_clkreql0sl1(_adapter *padapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tu8 tmp8 = 0;\n\tu16 tmp16 = 0;\n\n\t/* 0x70f Bit7 for L0s */\n\ttmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f);\n\n\tif (pHalData->pci_backdoor_ctrl & PCI_BC_ASPM_L0s)\n\t\ttmp8 |= BIT7;\n\telse\n\t\ttmp8 &= (~BIT7);\n\n\t/* Default set L1 entrance latency to 16us */\n\t/* L0s: b[0-2], L1: b[3-5]*/\n\tif (pHalData->pci_backdoor_ctrl & PCI_BC_ASPM_L1) {\n\t\ttmp8 &= (~0x38);\n\t\ttmp8 |= 0x20;\n#ifdef CONFIG_PCI_DYNAMIC_ASPM\n\t\tpHalData->bAspmL1LastIdle = 1;\n#endif\n\t}\n\n\trtw_hal_pci_dbi_write(padapter, 0x70f, tmp8);\n\n\n\t/* 0x719 Bit 3 for L1 ,  Bit4 for clock req */\n\ttmp8 = rtw_hal_pci_dbi_read(padapter, 0x719);\n\n\tif (pHalData->pci_backdoor_ctrl & PCI_BC_ASPM_L1)\n\t\ttmp8 |= BIT3;\n\telse\n\t\ttmp8 &= (~BIT3);\n\n\tif (pHalData->pci_backdoor_ctrl & PCI_BC_CLK_REQ)\n\t\ttmp8 |= BIT4;\n\telse\n\t\ttmp8 &= (~BIT4);\n\n\trtw_hal_pci_dbi_write(padapter, 0x719, tmp8);\n\n\tif (pHalData->pci_backdoor_ctrl & PCI_BC_CLK_REQ) {\n\t\ttmp16 = rtw_hal_pci_mdio_read(padapter, 0x10);\n\t\trtw_hal_pci_mdio_write(padapter, 0x10, (tmp16 | BIT2));\n\t}\n}\n\nvoid rtw_pci_aspm_config_l1off(_adapter *padapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n\tu8 enable_l1off = _FALSE;\n\n\tif (pHalData->pci_backdoor_ctrl & PCI_BC_ASPM_L1Off)\n\t\tenable_l1off = rtw_hal_pci_l1off_nic_support(padapter);\n\n\tpadapter->hal_func.hal_set_l1ssbackdoor_handler(padapter, enable_l1off);\n\n}\n\nvoid rtw_pci_aspm_config_l1off_general(_adapter *padapter, u8 enablel1off)\n{\n\n\tu8 tmp8;\n\tu16 tmp16;\n\n\tif (enablel1off) {\n\t\t/* 0x718 Bit5 for L1SS */\n\t\ttmp8 = rtw_hal_pci_dbi_read(padapter, 0x718);\n\t\trtw_hal_pci_dbi_write(padapter, 0x718, (tmp8 | BIT5));\n\n\t\ttmp16 = rtw_hal_pci_mdio_read(padapter, 0x1b);\n\t\trtw_hal_pci_mdio_write(padapter, 0x1b, (tmp16 | BIT4));\n\t} else {\n\t\ttmp8 = rtw_hal_pci_dbi_read(padapter, 0x718);\n\t\trtw_hal_pci_dbi_write(padapter, 0x718, (tmp8 & (~BIT5)));\n\t}\n\n}\n\n#ifdef CONFIG_PCI_DYNAMIC_ASPM\nvoid rtw_pci_aspm_config_dynamic_l1_ilde_time(_adapter *padapter)\n{\n\tBOOLEAN\t bCurrentIdle = 1;\t/* Default idle 4us (0x70F = 0x17)*/\n\tHAL_DATA_TYPE *pHalData\t= GET_HAL_DATA(padapter);\n\tstruct mlme_priv *pmlmepriv = &(padapter->mlmepriv);\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);\n\tint current_tx_tp = pdvobjpriv->traffic_stat.cur_tx_tp;\n\tint current_rx_tp = pdvobjpriv->traffic_stat.cur_rx_tp;\n\tint current_tp = current_tx_tp + current_rx_tp;\n\tu8 tmp8 = 0;\n\n\tif (padapter->registrypriv.wifi_spec)\n\t\treturn;\n\n\tif (!(pHalData->pci_backdoor_ctrl & PCI_BC_ASPM_L1))\n\t\treturn;\n\n#if 0\n\tRTW_INFO(\"current_tx_tp = %d\\n\", current_tx_tp);\n\tRTW_INFO(\"current_rx_tp = %d\\n\", current_rx_tp);\n\tRTW_INFO(\"current_tp = %d\\n\", current_tp);\n#endif\n\n\tif ((rtw_linked_check(padapter) == _TRUE) && \n\t\t((current_tx_tp >= 50)||\n\t\t(current_rx_tp >= 50)))\n\t\t/*(current_rx_tp >= 10))*/\n\t\t/*(current_tp >= 10))*/\n\t{\n\t\tbCurrentIdle = 0;\n\t}\t\n\telse\n\t{\n\t\tbCurrentIdle = 1;\n\t}\n\n\tif(bCurrentIdle != pHalData->bAspmL1LastIdle)\n\t{\n\t\tpHalData->bAspmL1LastIdle = bCurrentIdle;\n\n\t\ttmp8 = rtw_hal_pci_dbi_read(padapter, 0x70F);\n\t\ttmp8 &= (~0x38);\n\n\t\tif(bCurrentIdle) {\n\t\t\t/*tmp8 |= 0x10; *//*L1 entrance latency: 4us*/\n\t\t\t/*tmp8 |= 0x18; *//*L1 entrance latency: 8us*/\n\t\t\ttmp8 |= 0x20; /*L1 entrance latency: 16us*/\n\t\t\trtw_hal_pci_dbi_write(padapter, 0x70F, tmp8 );\n\t\t}\n\t\telse {\n\t\t\ttmp8 |= 0x28; /*L1 entrance latency: 32us*/\n\t\t\trtw_hal_pci_dbi_write(padapter, 0x70F, tmp8 );\n\t\t}\n\t}\n\n}\n#endif\n\nvoid rtw_pci_dump_aspm_info(_adapter *padapter)\n{\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct pci_priv\t*pcipriv = &(pdvobjpriv->pcipriv);\n\tu8 tmp8 = 0;\n\tu16 tmp16 = 0;\n\tu32 tmp32 = 0;\n\tu8 l1_idle = 0;\n\n\n\tRTW_INFO(\"***** ASPM Capability *****\\n\");\n\n\tpci_read_config_dword(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCAP, &tmp32);\n\n\tRTW_INFO(\"CLK REQ:\t%s\\n\", (tmp32&PCI_EXP_LNKCAP_CLKPM) ? \"Enable\" : \"Disable\");\n\n\tRTW_INFO(\"ASPM L0s:\t%s\\n\", (tmp32&BIT10) ? \"Enable\" : \"Disable\");\n\tRTW_INFO(\"ASPM L1:\t%s\\n\", (tmp32&BIT11) ? \"Enable\" : \"Disable\");\n\n\ttmp8 = rtw_hal_pci_l1off_capability(padapter);\n\tRTW_INFO(\"ASPM L1OFF:%s\\n\", tmp8 ? \"Enable\" : \"Disable\");\n\n\tRTW_INFO(\"***** ASPM CTRL Reg *****\\n\");\n\n\tpci_read_config_word(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCTL, &tmp16);\n\n\tRTW_INFO(\"CLK REQ:\t%s\\n\", (tmp16&PCI_EXP_LNKCTL_CLKREQ_EN) ? \"Enable\" : \"Disable\");\n\tRTW_INFO(\"ASPM L0s:\t%s\\n\", (tmp16&BIT0) ? \"Enable\" : \"Disable\");\n\tRTW_INFO(\"ASPM L1:\t%s\\n\", (tmp16&BIT1) ? \"Enable\" : \"Disable\");\n\n\ttmp8 = rtw_hal_pci_l1off_nic_support(padapter);\n\tRTW_INFO(\"ASPM L1OFF:%s\\n\", tmp8 ? \"Enable\" : \"Disable\");\n\n\tRTW_INFO(\"***** ASPM Backdoor *****\\n\");\n\n\ttmp8 = rtw_hal_pci_dbi_read(padapter, 0x719);\n\tRTW_INFO(\"CLK REQ:\t%s\\n\", (tmp8 & BIT4) ? \"Enable\" : \"Disable\");\n\n\ttmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f);\n\tl1_idle = tmp8 & 0x38;\n\tRTW_INFO(\"ASPM L0s:\t%s\\n\", (tmp8&BIT7) ? \"Enable\" : \"Disable\");\n\n\ttmp8 = rtw_hal_pci_dbi_read(padapter, 0x719);\n\tRTW_INFO(\"ASPM L1:\t%s\\n\", (tmp8 & BIT3) ? \"Enable\" : \"Disable\");\n\n\ttmp8 = rtw_hal_pci_dbi_read(padapter, 0x718);\n\tRTW_INFO(\"ASPM L1OFF:%s\\n\", (tmp8 & BIT5) ? \"Enable\" : \"Disable\");\n\t\n\tRTW_INFO(\"********* MISC **********\\n\");\n\tRTW_INFO(\"ASPM L1 Idel Time: 0x%x\\n\", l1_idle>>3);\n\tRTW_INFO(\"*************************\\n\");\n}\n\nvoid rtw_pci_aspm_config(_adapter *padapter)\n{\n\trtw_pci_aspm_config_clkreql0sl1(padapter);\n\trtw_pci_aspm_config_l1off(padapter);\n\trtw_pci_dump_aspm_info(padapter);\n}\n\nstatic u8 rtw_pci_platform_switch_device_pci_aspm(_adapter *padapter, u8 value)\n{\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct pci_priv\t*pcipriv = &(pdvobjpriv->pcipriv);\n\tBOOLEAN\t\tbResult = _FALSE;\n\tint\tResult = 0;\n\tint\terror;\n\n\tResult = pci_write_config_byte(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + 0x10, value);\t/* enable I/O space */\n\tRTW_INFO(\"PlatformSwitchDevicePciASPM(0x%x) = 0x%x\\n\", pcipriv->pciehdr_offset + 0x10, value);\n\tif (Result != 0) {\n\t\tRTW_INFO(\"PlatformSwitchDevicePciASPM() Failed!\\n\");\n\t\tbResult = _FALSE;\n\t} else\n\t\tbResult = _TRUE;\n\n\treturn bResult;\n}\n\n/*\n * When we set 0x01 to enable clk request. Set 0x0 to disable clk req.\n */\nstatic u8 rtw_pci_switch_clk_req(_adapter *padapter, u8 value)\n{\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\tu8\tbuffer, bResult = _FALSE;\n\tint\terror;\n\n\tbuffer = value;\n\n\tif (!rtw_is_hw_init_completed(padapter))\n\t\treturn bResult;\n\n\t/* the clock request is located at offset 0x81, suppose the PCIE Capability register is located at offset 0x70 */\n\t/* the correct code should be: search the PCIE capability register first and then the clock request is located offset 0x11 */\n\terror = pci_write_config_byte(pdvobjpriv->ppcidev, 0x81, buffer);\n\tif (error != 0)\n\t\tRTW_INFO(\"rtw_pci_switch_clk_req error (%d)\\n\", error);\n\telse\n\t\tbResult = _TRUE;\n\n\treturn bResult;\n}\n\n/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/\nvoid rtw_pci_disable_aspm(_adapter *padapter)\n{\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct pwrctrl_priv\t*pwrpriv = dvobj_to_pwrctl(pdvobjpriv);\n\tstruct pci_dev\t*pdev = pdvobjpriv->ppcidev;\n\tstruct pci_dev\t*bridge_pdev = pdev->bus->self;\n\tstruct pci_priv\t*pcipriv = &(pdvobjpriv->pcipriv);\n\tu8\tlinkctrl_reg;\n\tu8\tpcibridge_linkctrlreg, aspmlevel = 0;\n\n\n\t/* We shall check RF Off Level for ASPM function instead of registry settings, revised by Roger, 2013.03.29. */\n\tif (!(pwrpriv->reg_rfps_level & (RT_RF_LPS_LEVEL_ASPM | RT_RF_PS_LEVEL_ALWAYS_ASPM)))\n\t\treturn;\n\n\tif (!rtw_is_hw_init_completed(padapter))\n\t\treturn;\n\n\tif (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN)\n\t\treturn;\n\n\tlinkctrl_reg = pcipriv->linkctrl_reg;\n\tpcibridge_linkctrlreg = pcipriv->pcibridge_linkctrlreg;\n\n\t/* Set corresponding value. */\n\taspmlevel |= BIT(0) | BIT(1);\n\tlinkctrl_reg &= ~aspmlevel;\n\tpcibridge_linkctrlreg &= ~aspmlevel;\n\n\t/*  */\n\t/* 09/08/21 MH From Sd1 suggestion. we need to adjust ASPM enable sequence */\n\t/* CLK_REQ ==> delay 50us ==> Device ==> Host ==> delay 50us */\n\t/*  */\n\n\tif (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {\n\t\tRT_CLEAR_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ);\n\t\trtw_pci_switch_clk_req(padapter, 0x0);\n\t}\n\n\t{\n\t\t/*for promising device will in L0 state after an I/O.*/\n\t\tu8 tmp_u1b;\n\n\t\tpci_read_config_byte(pdev, (pcipriv->pciehdr_offset + 0x10), &tmp_u1b);\n\t}\n\n\trtw_pci_platform_switch_device_pci_aspm(padapter, linkctrl_reg);\n\n\trtw_udelay_os(50);\n\n\t/* When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff, */\n\t/* we do not execute any action and return. Added by tynli. */\n\tif ((pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) ||\n\t    (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff)) {\n\t\t/* Do Nothing!! */\n\t} else {\n\t\t/* 4  */ /* Disable Pci Bridge ASPM */\n\t\tpci_write_config_byte(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset + 0x10), pcibridge_linkctrlreg);\n\t\tRTW_INFO(\"PlatformDisableASPM():PciBridge Write reg[%x] = %x\\n\",\n\t\t\t(pcipriv->pcibridge_pciehdr_offset + 0x10), pcibridge_linkctrlreg);\n\t\trtw_udelay_os(50);\n\t}\n\n}\n\n/*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for\n * power saving We should follow the sequence to enable\n * RTL8192SE first then enable Pci Bridge ASPM\n * or the system will show bluescreen.\n*/\nvoid rtw_pci_enable_aspm(_adapter *padapter)\n{\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct pwrctrl_priv\t*pwrpriv = dvobj_to_pwrctl(pdvobjpriv);\n\tstruct pci_dev\t*pdev = pdvobjpriv->ppcidev;\n\tstruct pci_dev\t*bridge_pdev = pdev->bus->self;\n\tstruct pci_priv\t*pcipriv = &(pdvobjpriv->pcipriv);\n\tu16\taspmlevel = 0;\n\tu8\tu_pcibridge_aspmsetting = 0;\n\tu8\tu_device_aspmsetting = 0;\n\tu32\tu_device_aspmsupportsetting = 0;\n\n\n\t/* We shall check RF Off Level for ASPM function instead of registry settings, revised by Roger, 2013.03.29. */\n\tif (!(pwrpriv->reg_rfps_level & (RT_RF_LPS_LEVEL_ASPM | RT_RF_PS_LEVEL_ALWAYS_ASPM)))\n\t\treturn;\n\n\t/* When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff, */\n\t/* we do not execute any action and return. Added by tynli. */\n\tif ((pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) ||\n\t    (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff)) {\n\t\tRTW_INFO(\"rtw_pci_enable_aspm(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\\n\");\n\t\treturn;\n\t}\n\n\t/* Get Bridge ASPM Support\n\t * not to enable bridge aspm if bridge does not support\n\t * Added by sherry 20100803\n\t*/\n\t{\n\t\t/* Get the Link Capability, it ls located at offset 0x0c from the PCIE Capability */\n\t\tpci_read_config_dword(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset + 0x0C), &u_device_aspmsupportsetting);\n\n\t\tRTW_INFO(\"rtw_pci_enable_aspm(): Bridge ASPM support %x\\n\", u_device_aspmsupportsetting);\n\t\tif (((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) || ((u_device_aspmsupportsetting & BIT(10)) != BIT(10))) {\n\t\t\tif (pdvobjpriv->const_devicepci_aspm_setting == 3) {\n\t\t\t\tRTW_INFO(\"rtw_pci_enable_aspm(): Bridge not support L0S or L1\\n\");\n\t\t\t\treturn;\n\t\t\t} else if (pdvobjpriv->const_devicepci_aspm_setting == 2) {\n\t\t\t\tif ((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) {\n\t\t\t\t\tRTW_INFO(\"rtw_pci_enable_aspm(): Bridge not support L1\\n\");\n\t\t\t\t\treturn;\n\t\t\t\t}\n\t\t\t} else if (pdvobjpriv->const_devicepci_aspm_setting == 1) {\n\t\t\t\tif ((u_device_aspmsupportsetting & BIT(10)) != BIT(10)) {\n\t\t\t\t\tRTW_INFO(\"rtw_pci_enable_aspm(): Bridge not support L0s\\n\");\n\t\t\t\t\treturn;\n\t\t\t\t}\n\n\t\t\t}\n\t\t} else\n\t\t\tRTW_INFO(\"rtw_pci_enable_aspm(): Bridge support L0s and L1\\n\");\n\t}\n\n\t/*\n\t* Skip following settings if ASPM has already enabled, added by Roger, 2013.03.15.\n\t*/\n\tif ((pcipriv->pcibridge_linkctrlreg & (BIT0 | BIT1)) &&\n\t    (pcipriv->linkctrl_reg & (BIT0 | BIT1))) {\n\t\t/* BIT0: L0S, BIT1:L1 */\n\n\t\tRTW_INFO(\"PlatformEnableASPM(): ASPM is already enabled, skip incoming settings!!\\n\");\n\t\treturn;\n\t}\n\n\t/* 4 Enable Pci Bridge ASPM */\n\t/* Write PCI bridge PCIE-capability Link Control Register */\n\t/* Justin: Can we change the ASPM Control register ? */\n\t/* The system BIOS should set this register with a correct value */\n\t/* If we change the force enable the ASPM L1/L0s, this may cause the system hang */\n\tu_pcibridge_aspmsetting = pcipriv->pcibridge_linkctrlreg;\n\tu_pcibridge_aspmsetting |= pdvobjpriv->const_hostpci_aspm_setting;\n\n\tif (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL ||\n\t    pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_SIS)\n\t\tu_pcibridge_aspmsetting &= ~BIT(0); /* for intel host 42 device 43 */\n\n\tpci_write_config_byte(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset + 0x10), u_pcibridge_aspmsetting);\n\tRTW_INFO(\"PlatformEnableASPM():PciBridge Write reg[%x] = %x\\n\",\n\t\t (pcipriv->pcibridge_pciehdr_offset + 0x10),\n\t\t u_pcibridge_aspmsetting);\n\n\trtw_udelay_os(50);\n\n\t/*Get ASPM level (with/without Clock Req)*/\n\taspmlevel |= pdvobjpriv->const_devicepci_aspm_setting;\n\tu_device_aspmsetting = pcipriv->linkctrl_reg;\n\tu_device_aspmsetting |= aspmlevel; /* device 43 */\n\n\trtw_pci_platform_switch_device_pci_aspm(padapter, u_device_aspmsetting);\n\n\tif (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {\n\t\trtw_pci_switch_clk_req(padapter, (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);\n\t\tRT_SET_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ);\n\t}\n\n\trtw_udelay_os(50);\n}\n\nstatic u8 rtw_pci_get_amd_l1_patch(struct dvobj_priv *pdvobjpriv, struct pci_dev *pdev)\n{\n\tu8\tstatus = _FALSE;\n\tu8\toffset_e0;\n\tu32\toffset_e4;\n\n\tpci_write_config_byte(pdev, 0xE0, 0xA0);\n\tpci_read_config_byte(pdev, 0xE0, &offset_e0);\n\n\tif (offset_e0 == 0xA0) {\n\t\tpci_read_config_dword(pdev, 0xE4, &offset_e4);\n\t\tif (offset_e4 & BIT(23))\n\t\t\tstatus = _TRUE;\n\t}\n\n\treturn status;\n}\n\nstatic s32\trtw_pci_get_linkcontrol_reg(struct pci_dev *pdev, u8 *LinkCtrlReg, u8 *HdrOffset)\n{\n\tu8 CapabilityPointer;\n\tRT_PCI_CAPABILITIES_HEADER\tCapabilityHdr;\n\ts32 status = _FAIL;\n\n\t/* get CapabilityOffset */\n\tpci_read_config_byte(pdev, 0x34, &CapabilityPointer);\t/* the capability pointer is located offset 0x34 */\n\n\t/* Loop through the capabilities in search of the power management capability. */\n\t/* The list is NULL-terminated, so the last offset will always be zero. */\n\n\twhile (CapabilityPointer != 0) {\n\t\t/* Read the header of the capability at  this offset. If the retrieved capability is not */\n\t\t/* the power management capability that we are looking for, follow the link to the  */\n\t\t/* next capability and continue looping. */\n\n\t\t/* 4 get CapabilityHdr */\n\t\t/* pci_read_config_word(pdev, CapabilityPointer, (u16 *)&CapabilityHdr); */\n\t\tpci_read_config_byte(pdev, CapabilityPointer, (u8 *)&CapabilityHdr.CapabilityID);\n\t\tpci_read_config_byte(pdev, CapabilityPointer + 1, (u8 *)&CapabilityHdr.Next);\n\n\t\t/* Found the PCI express capability */\n\t\tif (CapabilityHdr.CapabilityID == PCI_CAPABILITY_ID_PCI_EXPRESS)\n\t\t\tbreak;\n\t\telse {\n\t\t\t/* This is some other capability. Keep looking for the PCI express capability. */\n\t\t\tCapabilityPointer = CapabilityHdr.Next;\n\t\t}\n\t}\n\n\t/* Get the Link Control Register, it located at offset 0x10 from the Capability Header */\n\tif (CapabilityHdr.CapabilityID == PCI_CAPABILITY_ID_PCI_EXPRESS) {\n\t\t*HdrOffset = CapabilityPointer;\n\t\tpci_read_config_byte(pdev, CapabilityPointer + 0x10, LinkCtrlReg);\n\n\t\tstatus = _SUCCESS;\n\t} else {\n\t\t/* We didn't find a PCIe capability. */\n\t\tRTW_INFO(\"GetPciLinkCtrlReg(): Cannot Find PCIe Capability\\n\");\n\t}\n\n\treturn status;\n}\n\nstatic s32\trtw_set_pci_cache_line_size(struct pci_dev *pdev, u8 CacheLineSizeToSet)\n{\n\tu8\tucPciCacheLineSize;\n\ts32\tResult;\n\n\t/* ucPciCacheLineSize  = pPciConfig->CacheLineSize; */\n\tpci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &ucPciCacheLineSize);\n\n\tif (ucPciCacheLineSize < 8 || ucPciCacheLineSize > 16) {\n\t\tRTW_INFO(\"Driver Sets default Cache Line Size...\\n\");\n\n\t\tucPciCacheLineSize = CacheLineSizeToSet;\n\n\t\tResult = pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, ucPciCacheLineSize);\n\n\t\tif (Result != 0) {\n\t\t\tRTW_INFO(\"pci_write_config_byte (CacheLineSize) Result=%d\\n\", Result);\n\t\t\tgoto _SET_CACHELINE_SIZE_FAIL;\n\t\t}\n\n\t\tResult = pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &ucPciCacheLineSize);\n\t\tif (Result != 0) {\n\t\t\tRTW_INFO(\"pci_read_config_byte (PciCacheLineSize) Result=%d\\n\", Result);\n\t\t\tgoto _SET_CACHELINE_SIZE_FAIL;\n\t\t}\n\n\t\tif (ucPciCacheLineSize != CacheLineSizeToSet) {\n\t\t\tRTW_INFO(\"Failed to set Cache Line Size to 0x%x! ucPciCacheLineSize=%x\\n\", CacheLineSizeToSet, ucPciCacheLineSize);\n\t\t\tgoto _SET_CACHELINE_SIZE_FAIL;\n\t\t}\n\t}\n\n\treturn _SUCCESS;\n\n_SET_CACHELINE_SIZE_FAIL:\n\n\treturn _FAIL;\n}\n\n\n#define PCI_CMD_ENABLE_BUS_MASTER\t\tBIT(2)\n#define PCI_CMD_DISABLE_INTERRUPT\t\tBIT(10)\n#define CMD_BUS_MASTER\t\t\t\tBIT(2)\n\nstatic s32 rtw_pci_parse_configuration(struct pci_dev *pdev, struct dvobj_priv *pdvobjpriv)\n{\n\tstruct pci_priv\t*pcipriv = &(pdvobjpriv->pcipriv);\n\t/* PPCI_COMMON_CONFIG pPciConfig = (PPCI_COMMON_CONFIG) pucBuffer; */\n\t/* u16\tusPciCommand = pPciConfig->Command; */\n\tu16\tusPciCommand = 0;\n\tint\tResult, ret = _FAIL;\n\tu8\tCapabilityOffset;\n\tRT_PCI_CAPABILITIES_HEADER CapabilityHdr;\n\tu8\tPCIeCap;\n\tu8\tLinkCtrlReg;\n\tu8\tClkReqReg;\n\n\t/* RTW_INFO(\"%s==>\\n\", __func__); */\n\n\tpci_read_config_word(pdev, PCI_COMMAND, &usPciCommand);\n\n\tdo {\n\t\t/* 3 Enable bus matering if it isn't enabled by the BIOS */\n\t\tif (!(usPciCommand & PCI_CMD_ENABLE_BUS_MASTER)) {\n\t\t\tRTW_INFO(\"Bus master is not enabled by BIOS! usPciCommand=%x\\n\", usPciCommand);\n\n\t\t\tusPciCommand |= CMD_BUS_MASTER;\n\n\t\t\tResult = pci_write_config_word(pdev, PCI_COMMAND, usPciCommand);\n\t\t\tif (Result != 0) {\n\t\t\t\tRTW_INFO(\"pci_write_config_word (Command) Result=%d\\n\", Result);\n\t\t\t\tret = _FAIL;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tResult = pci_read_config_word(pdev, PCI_COMMAND, &usPciCommand);\n\t\t\tif (Result != 0) {\n\t\t\t\tRTW_INFO(\"pci_read_config_word (Command) Result=%d\\n\", Result);\n\t\t\t\tret = _FAIL;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif (!(usPciCommand & PCI_CMD_ENABLE_BUS_MASTER)) {\n\t\t\t\tRTW_INFO(\"Failed to enable bus master! usPciCommand=%x\\n\", usPciCommand);\n\t\t\t\tret = _FAIL;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tRTW_INFO(\"Bus master is enabled. usPciCommand=%x\\n\", usPciCommand);\n\n\t\t/* 3 Enable interrupt */\n\t\tif ((usPciCommand & PCI_CMD_DISABLE_INTERRUPT)) {\n\t\t\tRTW_INFO(\"INTDIS==1 usPciCommand=%x\\n\", usPciCommand);\n\n\t\t\tusPciCommand &= (~PCI_CMD_DISABLE_INTERRUPT);\n\n\t\t\tResult = pci_write_config_word(pdev, PCI_COMMAND, usPciCommand);\n\t\t\tif (Result != 0) {\n\t\t\t\tRTW_INFO(\"pci_write_config_word (Command) Result=%d\\n\", Result);\n\t\t\t\tret = _FAIL;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tResult = pci_read_config_word(pdev, PCI_COMMAND, &usPciCommand);\n\t\t\tif (Result != 0) {\n\t\t\t\tRTW_INFO(\"pci_read_config_word (Command) Result=%d\\n\", Result);\n\t\t\t\tret = _FAIL;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif ((usPciCommand & PCI_CMD_DISABLE_INTERRUPT)) {\n\t\t\t\tRTW_INFO(\"Failed to set INTDIS to 0! usPciCommand=%x\\n\", usPciCommand);\n\t\t\t\tret = _FAIL;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\t/*  */\n\t\t/* Description: Find PCI express capability offset. Porting from 818xB by tynli 2008.12.19 */\n\t\t/*  */\n\t\t/* ------------------------------------------------------------- */\n\n\t\t/* 3 PCIeCap */\n\t\t/* The device supports capability lists. Find the capabilities. */\n\n\t\t/* CapabilityOffset = pPciConfig->u.type0.CapabilitiesPtr; */\n\t\tpci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &CapabilityOffset);\n\n\t\t/* Loop through the capabilities in search of the power management capability. */\n\t\t/* The list is NULL-terminated, so the last offset will always be zero. */\n\n\t\twhile (CapabilityOffset != 0) {\n\t\t\t/* Read the header of the capability at  this offset. If the retrieved capability is not */\n\t\t\t/* the power management capability that we are looking for, follow the link to the */\n\t\t\t/* next capability and continue looping. */\n\n\t\t\t/* Result = pci_read_config_word(pdev, CapabilityOffset, (u16 *)&CapabilityHdr); */\n\t\t\tResult = pci_read_config_byte(pdev, CapabilityOffset, (u8 *)&CapabilityHdr.CapabilityID);\n\t\t\tif (Result != 0)\n\t\t\t\tbreak;\n\n\t\t\tResult = pci_read_config_byte(pdev, CapabilityOffset + 1, (u8 *)&CapabilityHdr.Next);\n\t\t\tif (Result != 0)\n\t\t\t\tbreak;\n\n\t\t\t/* Found the PCI express capability */\n\t\t\tif (CapabilityHdr.CapabilityID == PCI_CAPABILITY_ID_PCI_EXPRESS)\n\t\t\t\tbreak;\n\t\t\telse {\n\t\t\t\t/* This is some other capability. Keep looking for the PCI express capability. */\n\t\t\t\tCapabilityOffset = CapabilityHdr.Next;\n\t\t\t}\n\t\t}\n\n\t\tif (Result != 0) {\n\t\t\tRTW_INFO(\"pci_read_config_word (RT_PCI_CAPABILITIES_HEADER) Result=%d\\n\", Result);\n\t\t\tbreak;\n\t\t}\n\n\t\tif (CapabilityHdr.CapabilityID == PCI_CAPABILITY_ID_PCI_EXPRESS) {\n\t\t\tpcipriv->pciehdr_offset = CapabilityOffset;\n\t\t\tRTW_INFO(\"PCIe Header Offset =%x\\n\", CapabilityOffset);\n\n\t\t\t/* Skip past the capabilities header and read the PCI express capability */\n\t\t\t/* Justin: The PCI-e capability size should be 2 bytes, why we just get 1 byte */\n\t\t\t/* Beside, this PCIeCap seems no one reference it in the driver code */\n\t\t\tResult = pci_read_config_byte(pdev, CapabilityOffset + 2, &PCIeCap);\n\n\t\t\tif (Result != 0) {\n\t\t\t\tRTW_INFO(\"pci_read_config_byte (PCIE Capability) Result=%d\\n\", Result);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tpcipriv->pcie_cap = PCIeCap;\n\t\t\tRTW_INFO(\"PCIe Capability =%x\\n\", PCIeCap);\n\n\t\t\t/* 3 Link Control Register */\n\t\t\t/* Read \"Link Control Register\" Field (80h ~81h) */\n\t\t\tResult = pci_read_config_byte(pdev, CapabilityOffset + 0x10, &LinkCtrlReg);\n\t\t\tif (Result != 0) {\n\t\t\t\tRTW_INFO(\"pci_read_config_byte (Link Control Register) Result=%d\\n\", Result);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tpcipriv->linkctrl_reg = LinkCtrlReg;\n\t\t\tRTW_INFO(\"Link Control Register =%x\\n\", LinkCtrlReg);\n\n\t\t\t/* 3 Get Capability of PCI Clock Request */\n\t\t\t/* The clock request setting is located at 0x81[0] */\n\t\t\tResult = pci_read_config_byte(pdev, CapabilityOffset + 0x11, &ClkReqReg);\n\t\t\tif (Result != 0) {\n\t\t\t\tpcipriv->pci_clk_req = _FALSE;\n\t\t\t\tRTW_INFO(\"pci_read_config_byte (Clock Request Register) Result=%d\\n\", Result);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (ClkReqReg & BIT(0))\n\t\t\t\tpcipriv->pci_clk_req = _TRUE;\n\t\t\telse\n\t\t\t\tpcipriv->pci_clk_req = _FALSE;\n\t\t\tRTW_INFO(\"Clock Request =%x\\n\", pcipriv->pci_clk_req);\n\t\t} else {\n\t\t\t/* We didn't find a PCIe capability. */\n\t\t\tRTW_INFO(\"Didn't Find PCIe Capability\\n\");\n\t\t\tbreak;\n\t\t}\n\n\t\t/* 3 Fill Cacheline */\n\t\tret = rtw_set_pci_cache_line_size(pdev, 8);\n\t\tif (ret != _SUCCESS) {\n\t\t\tRTW_INFO(\"rtw_set_pci_cache_line_size fail\\n\");\n\t\t\tbreak;\n\t\t}\n\n\t\t/* Include 92C suggested by SD1. Added by tynli. 2009.11.25.\n\t\t * Enable the Backdoor\n\t\t */\n\t\t{\n\t\t\tu8\ttmp;\n\n\t\t\tResult = pci_read_config_byte(pdev, 0x98, &tmp);\n\n\t\t\ttmp |= BIT4;\n\n\t\t\tResult = pci_write_config_byte(pdev, 0x98, tmp);\n\n\t\t}\n\t\tret = _SUCCESS;\n\t} while (_FALSE);\n\n\treturn ret;\n}\n\n/*\n * Update PCI dependent default settings.\n *\n */\nstatic void rtw_pci_update_default_setting(_adapter *padapter)\n{\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct pci_priv\t*pcipriv = &(pdvobjpriv->pcipriv);\n\tstruct pwrctrl_priv\t*pwrpriv = dvobj_to_pwrctl(pdvobjpriv);\n\tHAL_DATA_TYPE\t*pHalData = GET_HAL_DATA(padapter);\n\n\t/* reset pPSC->reg_rfps_level & priv->b_support_aspm */\n\tpwrpriv->reg_rfps_level = 0;\n\n\t/* Update PCI ASPM setting */\n\t/* pwrpriv->const_amdpci_aspm = pdvobjpriv->const_amdpci_aspm; */\n\tswitch (pdvobjpriv->const_pci_aspm) {\n\tcase 0:\t\t/* No ASPM */\n\t\tbreak;\n\n\tcase 1:\t\t/* ASPM dynamically enabled/disable. */\n\t\tpwrpriv->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;\n\t\tbreak;\n\n\tcase 2:\t\t/* ASPM with Clock Req dynamically enabled/disable. */\n\t\tpwrpriv->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ);\n\t\tbreak;\n\n\tcase 3:\t\t/* Always enable ASPM and Clock Req from initialization to halt. */\n\t\tpwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);\n\t\tpwrpriv->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | RT_RF_OFF_LEVL_CLK_REQ);\n\t\tbreak;\n\n\tcase 4:\t\t/* Always enable ASPM without Clock Req from initialization to halt. */\n\t\tpwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ);\n\t\tpwrpriv->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;\n\t\tbreak;\n\n\tcase 5: /* Linux do not support ASPM OSC, added by Roger, 2013.03.27.\t */\n\t\tbreak;\n\t}\n\n\tpwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;\n\n\t/* Update Radio OFF setting */\n\tswitch (pdvobjpriv->const_hwsw_rfoff_d3) {\n\tcase 1:\n\t\tif (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)\n\t\t\tpwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;\n\t\tbreak;\n\n\tcase 2:\n\t\tif (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)\n\t\t\tpwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;\n\t\tpwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;\n\t\tbreak;\n\n\tcase 3:\n\t\tpwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;\n\t\tbreak;\n\t}\n\n\t/* Update Rx 2R setting */\n\t/* pPSC->reg_rfps_level |= ((pDevice->RegLPS2RDisable) ? RT_RF_LPS_DISALBE_2R : 0); */\n\n\t/*  */\n\t/* Set HW definition to determine if it supports ASPM. */\n\t/*  */\n\tswitch (pdvobjpriv->const_support_pciaspm) {\n\tcase 1: {\t/* Support ASPM. */\n\t\tu8\tb_support_backdoor = _TRUE;\n\t\tu8\tb_support_l1_on_amd = _FALSE;\n\n\t\trtw_hal_get_def_var(padapter, HAL_DEF_PCI_AMD_L1_SUPPORT, &b_support_l1_on_amd);\n\n\t\tif (pHalData->CustomerID == RT_CID_TOSHIBA &&\n\t\t    pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD &&\n\t\t    !pcipriv->amd_l1_patch && !b_support_l1_on_amd) {\n\t\t\tRTW_INFO(\"%s(): Disable L1 Backdoor!!\\n\", __func__);\n\t\t\tb_support_backdoor = _FALSE;\n\t\t}\n\t\trtw_hal_set_def_var(padapter, HAL_DEF_PCI_SUUPORT_L1_BACKDOOR, &b_support_backdoor);\n\t}\n\tbreak;\n\n\tdefault:\n\t\t/* Do nothing. Set when finding the chipset. */\n\t\tbreak;\n\t}\n}\n\nstatic void rtw_pci_initialize_adapter_common(_adapter *padapter)\n{\n\tstruct pwrctrl_priv\t*pwrpriv = adapter_to_pwrctl(padapter);\n\n\trtw_pci_update_default_setting(padapter);\n\n\tif (pwrpriv->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {\n\t\t/* Always enable ASPM & Clock Req. */\n\t\trtw_pci_enable_aspm(padapter);\n\t\tRT_SET_PS_LEVEL(pwrpriv, RT_RF_PS_LEVEL_ALWAYS_ASPM);\n\t}\n\n}\n\n/*\n * 2009/10/28 MH Enable rtl8192ce DMA64 function. We need to enable 0x719 BIT5\n *   */\n#ifdef CONFIG_64BIT_DMA\nu8 PlatformEnableDMA64(PADAPTER Adapter)\n{\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(Adapter);\n\tstruct pci_dev\t*pdev = pdvobjpriv->ppcidev;\n\tu8\tbResult = _TRUE;\n\tu8\tvalue;\n\n\tpci_read_config_byte(pdev, 0x719, &value);\n\n\t/* 0x719 Bit5 is DMA64 bit fetch. */\n\tvalue |= (BIT5);\n\n\tpci_write_config_byte(pdev, 0x719, value);\n\n\treturn bResult;\n}\n#endif\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18))\n\t#define rtw_pci_interrupt(x, y, z) rtw_pci_interrupt(x, y)\n#endif\n\nstatic irqreturn_t rtw_pci_interrupt(int irq, void *priv, struct pt_regs *regs)\n{\n\tstruct dvobj_priv *dvobj = (struct dvobj_priv *)priv;\n\t_adapter *adapter = dvobj_get_primary_adapter(dvobj);\n\n\tif (dvobj->irq_enabled == 0)\n\t\treturn IRQ_HANDLED;\n\n\tif (rtw_hal_interrupt_handler(adapter) == _FAIL)\n\t\treturn IRQ_HANDLED;\n\t/* return IRQ_NONE; */\n\n\treturn IRQ_HANDLED;\n}\n\n#if defined(RTK_DMP_PLATFORM) || defined(CONFIG_PLATFORM_RTL8197D)\n\t#define pci_iounmap(x, y) iounmap(y)\n#endif\n\nint pci_alloc_irq(struct dvobj_priv *dvobj)\n{\n\tint err;\n\tstruct pci_dev *pdev = dvobj->ppcidev;\n\tint ret;\n\n#ifndef CONFIG_RTW_PCI_MSI_DISABLE\n\tret = pci_enable_msi(pdev);\n\n\tRTW_INFO(\"pci_enable_msi ret=%d\\n\", ret);\n#endif\n\n#if defined(IRQF_SHARED)\n\terr = request_irq(pdev->irq, &rtw_pci_interrupt, IRQF_SHARED, DRV_NAME, dvobj);\n#else\n\terr = request_irq(pdev->irq, &rtw_pci_interrupt, SA_SHIRQ, DRV_NAME, dvobj);\n#endif\n\tif (err)\n\t\tRTW_INFO(\"Error allocating IRQ %d\", pdev->irq);\n\telse {\n\t\tdvobj->irq_alloc = 1;\n\t\tdvobj->irq = pdev->irq;\n\t\tRTW_INFO(\"Request_irq OK, IRQ %d\\n\", pdev->irq);\n\t}\n\n\treturn err ? _FAIL : _SUCCESS;\n}\n\nstatic void rtw_decide_chip_type_by_pci_driver_data(struct dvobj_priv *pdvobj, const struct pci_device_id *pdid)\n{\n\tpdvobj->chip_type = pdid->driver_data;\n\n#ifdef CONFIG_RTL8188E\n\tif (pdvobj->chip_type == RTL8188E) {\n\t\tpdvobj->HardwareType = HARDWARE_TYPE_RTL8188EE;\n\t\tRTW_INFO(\"CHIP TYPE: RTL8188E\\n\");\n\t}\n#endif\n\n#ifdef CONFIG_RTL8812A\n\tif (pdvobj->chip_type == RTL8812) {\n\t\tpdvobj->HardwareType = HARDWARE_TYPE_RTL8812E;\n\t\tRTW_INFO(\"CHIP TYPE: RTL8812AE\\n\");\n\t}\n#endif\n\n#ifdef CONFIG_RTL8821A\n\tif (pdvobj->chip_type == RTL8821) {\n\t\tpdvobj->HardwareType = HARDWARE_TYPE_RTL8821E;\n\t\tRTW_INFO(\"CHIP TYPE: RTL8821AE\\n\");\n\t}\n#endif\n\n#ifdef CONFIG_RTL8723B\n\tif (pdvobj->chip_type == RTL8723B) {\n\t\tpdvobj->HardwareType = HARDWARE_TYPE_RTL8723BE;\n\t\tRTW_INFO(\"CHIP TYPE: RTL8723BE\\n\");\n\t}\n#endif\n#ifdef CONFIG_RTL8723D\n\tif (pdvobj->chip_type == RTL8723D) {\n\t\tpdvobj->HardwareType = HARDWARE_TYPE_RTL8723DE;\n\t\tRTW_INFO(\"CHIP TYPE: RTL8723DE\\n\");\n\t}\n#endif\n#ifdef CONFIG_RTL8192E\n\tif (pdvobj->chip_type == RTL8192E) {\n\t\tpdvobj->HardwareType = HARDWARE_TYPE_RTL8192EE;\n\t\tRTW_INFO(\"CHIP TYPE: RTL8192EE\\n\");\n\t}\n#endif\n\n#ifdef CONFIG_RTL8192F\n\tif (pdvobj->chip_type == RTL8192F) {\n\t\tpdvobj->HardwareType = HARDWARE_TYPE_RTL8192FE;\n\t\tRTW_INFO(\"CHIP TYPE: RTL8192FE\\n\");\n\t}\n#endif\n#ifdef CONFIG_RTL8814A\n\tif (pdvobj->chip_type == RTL8814A) {\n\t\tpdvobj->HardwareType = HARDWARE_TYPE_RTL8814AE;\n\t\tRTW_INFO(\"CHIP TYPE: RTL8814AE\\n\");\n\t}\n#endif\n\n#if defined(CONFIG_RTL8822B)\n\tif (pdvobj->chip_type == RTL8822B) {\n\t\tpdvobj->HardwareType = HARDWARE_TYPE_RTL8822BE;\n\t\tRTW_INFO(\"CHIP TYPE: RTL8822BE\\n\");\n\t}\n#endif\n\n#if defined(CONFIG_RTL8821C)\n\tif (pdvobj->chip_type == RTL8821C) {\n\t\tpdvobj->HardwareType = HARDWARE_TYPE_RTL8821CE;\n\t\tRTW_INFO(\"CHIP TYPE: RTL8821CE\\n\");\n\t}\n#endif\n\n#if defined(CONFIG_RTL8822C)\n\tif (pdvobj->chip_type == RTL8822C) {\n\t\tpdvobj->HardwareType = HARDWARE_TYPE_RTL8822CE;\n\t\tRTW_INFO(\"CHIP TYPE: RTL8822CE\\n\");\n\t}\n#endif\n\n}\n\nstatic struct dvobj_priv\t*pci_dvobj_init(struct pci_dev *pdev, const struct pci_device_id *pdid)\n{\n\tint err;\n\tu32\tstatus = _FAIL;\n\tstruct dvobj_priv\t*dvobj = NULL;\n\tstruct pci_priv\t*pcipriv = NULL;\n\tstruct pci_dev\t*bridge_pdev = pdev->bus->self;\n\t/* u32\tpci_cfg_space[16]; */\n\tunsigned long pmem_start, pmem_len, pmem_flags;\n\tu8\ttmp;\n\tu8\tPciBgVIdIdx;\n\tint\ti;\n\n\n\tdvobj = devobj_init();\n\tif (dvobj == NULL)\n\t\tgoto exit;\n\n\n\tdvobj->ppcidev = pdev;\n\tpcipriv = &(dvobj->pcipriv);\n\tpci_set_drvdata(pdev, dvobj);\n\n\n\terr = pci_enable_device(pdev);\n\tif (err != 0) {\n\t\tRTW_ERR(\"%s : Cannot enable new PCI device\\n\", pci_name(pdev));\n\t\tgoto free_dvobj;\n\t}\n\n#ifdef CONFIG_64BIT_DMA\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\tif (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {\n\t\tRTW_INFO(\"RTL819xCE: Using 64bit DMA\\n\");\n\t\terr = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));\n#else\n\tif (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {\n\t\tRTW_INFO(\"RTL819xCE: Using 64bit DMA\\n\");\n\t\terr = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));\n#endif\n\t\tif (err != 0) {\n\t\t\tRTW_ERR(\"Unable to obtain 64bit DMA for consistent allocations\\n\");\n\t\t\tgoto disable_picdev;\n\t\t}\n\t\tdvobj->bdma64 = _TRUE;\n\t} else\n#endif\n\t{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0))\n\t\tif (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {\n\t\t\terr = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));\n#else\n\t\tif (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {\n\t\t\terr = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));\n#endif\n\t\t\tif (err != 0) {\n\t\t\t\tRTW_ERR(\"Unable to obtain 32bit DMA for consistent allocations\\n\");\n\t\t\t\tgoto disable_picdev;\n\t\t\t}\n\t\t}\n\t}\n\n\tpci_set_master(pdev);\n\n\terr = pci_request_regions(pdev, DRV_NAME);\n\tif (err != 0) {\n\t\tRTW_ERR(\"Can't obtain PCI resources\\n\");\n\t\tgoto disable_picdev;\n\t}\n\n#ifdef RTK_129X_PLATFORM\n\tif (pdev->bus->number == 0x00) {\n\t\tpmem_start = PCIE_SLOT1_MEM_START;\n\t\tpmem_len   = PCIE_SLOT1_MEM_LEN;\n\t\tpmem_flags = 0;\n\t\tRTW_PRINT(\"RTD129X: PCIE SLOT1\\n\");\n\t} else if (pdev->bus->number == 0x01) {\n\t\tpmem_start = PCIE_SLOT2_MEM_START;\n\t\tpmem_len   = PCIE_SLOT2_MEM_LEN;\n\t\tpmem_flags = 0;\n\t\tRTW_PRINT(\"RTD129X: PCIE SLOT2\\n\");\n\t} else {\n\t\tRTW_ERR(KERN_ERR \"RTD129X: Wrong Slot Num\\n\");\n\t\tgoto release_regions;\n\t}\n#else\n\t/* Search for memory map resource (index 0~5) */\n\tfor (i = 0 ; i < 6 ; i++) {\n\t\tpmem_start = pci_resource_start(pdev, i);\n\t\tpmem_len = pci_resource_len(pdev, i);\n\t\tpmem_flags = pci_resource_flags(pdev, i);\n\n\t\tif (pmem_flags & IORESOURCE_MEM)\n\t\t\tbreak;\n\t}\n\n\tif (i == 6) {\n\t\tRTW_ERR(\"%s: No MMIO resource found, abort!\\n\", __func__);\n\t\tgoto release_regions;\n\t}\n#endif /* RTK_DMP_PLATFORM */\n\n#ifdef RTK_DMP_PLATFORM\n\tdvobj->pci_mem_start = (unsigned long)ioremap_nocache(pmem_start, pmem_len);\n#elif defined(RTK_129X_PLATFORM)\n\tif (pdev->bus->number == 0x00)\n\t\tdvobj->ctrl_start =\n\t\t\t(unsigned long)ioremap(PCIE_SLOT1_CTRL_START, 0x200);\n\telse if (pdev->bus->number == 0x01)\n\t\tdvobj->ctrl_start =\n\t\t\t(unsigned long)ioremap(PCIE_SLOT2_CTRL_START, 0x200);\n\n\tif (dvobj->ctrl_start == 0) {\n\t\tRTW_ERR(\"RTD129X: Can't map CTRL mem\\n\");\n\t\tgoto release_regions;\n\t}\n\n\tdvobj->mask_addr = dvobj->ctrl_start + PCIE_MASK_OFFSET;\n\tdvobj->tran_addr = dvobj->ctrl_start + PCIE_TRANSLATE_OFFSET;\n\n\tdvobj->pci_mem_start =\n\t\t(unsigned long)ioremap_nocache(pmem_start, pmem_len);\n#else\n\t/* shared mem start */\n\tdvobj->pci_mem_start = (unsigned long)pci_iomap(pdev, i, pmem_len);\n#endif\n\tif (dvobj->pci_mem_start == 0) {\n\t\tRTW_ERR(\"Can't map PCI mem\\n\");\n\t\tgoto release_regions;\n\t}\n\n\tRTW_INFO(\"Memory mapped space start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\\n\",\n\t\t pmem_start, pmem_len, pmem_flags, dvobj->pci_mem_start);\n\n\t/*find bus info*/\n\tpcipriv->busnumber = pdev->bus->number;\n\tpcipriv->devnumber = PCI_SLOT(pdev->devfn);\n\tpcipriv->funcnumber = PCI_FUNC(pdev->devfn);\n\n\t/*find bridge info*/\n\tif (bridge_pdev) {\n\t\tpcipriv->pcibridge_busnum = bridge_pdev->bus->number;\n\t\tpcipriv->pcibridge_devnum = PCI_SLOT(bridge_pdev->devfn);\n\t\tpcipriv->pcibridge_funcnum = PCI_FUNC(bridge_pdev->devfn);\n\t\tpcipriv->pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;\n\t\tpcipriv->pcibridge_vendorid = bridge_pdev->vendor;\n\t\tpcipriv->pcibridge_deviceid = bridge_pdev->device;\n\t}\n\n#if 0\n\t/* Read PCI configuration Space Header */\n\tfor (i = 0; i < 16; i++)\n\t\tpci_read_config_dword(pdev, (i << 2), &pci_cfg_space[i]);\n#endif\n\n\t/*step 1-1., decide the chip_type via device info*/\n\tdvobj->interface_type = RTW_PCIE;\n\trtw_decide_chip_type_by_pci_driver_data(dvobj, pdid);\n\n\n\t/* rtw_pci_parse_configuration(pdev, dvobj, (u8 *)&pci_cfg_space); */\n\trtw_pci_parse_configuration(pdev, dvobj);\n\n\tfor (PciBgVIdIdx = 0; PciBgVIdIdx < PCI_BRIDGE_VENDOR_MAX; PciBgVIdIdx++) {\n\t\tif (pcipriv->pcibridge_vendorid == pcibridge_vendors[PciBgVIdIdx]) {\n\t\t\tpcipriv->pcibridge_vendor = PciBgVIdIdx;\n\t\t\tRTW_INFO(\"Pci Bridge Vendor is found: VID=0x%x, VendorIdx=%d\\n\", pcipriv->pcibridge_vendorid, PciBgVIdIdx);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (pcipriv->pcibridge_vendor != PCI_BRIDGE_VENDOR_UNKNOWN) {\n\t\trtw_pci_get_linkcontrol_reg(bridge_pdev, &pcipriv->pcibridge_linkctrlreg, &pcipriv->pcibridge_pciehdr_offset);\n\n\t\tif (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD)\n\t\t\tpcipriv->amd_l1_patch = rtw_pci_get_amd_l1_patch(dvobj, bridge_pdev);\n\t}\n\n\tstatus = _SUCCESS;\n\n\tif (status != _SUCCESS && dvobj->pci_mem_start != 0) {\n#if 1/* def RTK_DMP_PLATFORM */\n\t\tpci_iounmap(pdev, (void *)dvobj->pci_mem_start);\n#endif\n\t\tdvobj->pci_mem_start = 0;\n\t}\n\n#ifdef RTK_129X_PLATFORM\n\tif (status != _SUCCESS && dvobj->ctrl_start != 0) {\n\t\tpci_iounmap(pdev, (void *)dvobj->ctrl_start);\n\t\tdvobj->ctrl_start = 0;\n\t}\n#endif\n\nrelease_regions:\n\tif (status != _SUCCESS)\n\t\tpci_release_regions(pdev);\ndisable_picdev:\n\tif (status != _SUCCESS)\n\t\tpci_disable_device(pdev);\nfree_dvobj:\n\tif (status != _SUCCESS && dvobj) {\n\t\tpci_set_drvdata(pdev, NULL);\n\t\tdevobj_deinit(dvobj);\n\t\tdvobj = NULL;\n\t}\nexit:\n\treturn dvobj;\n}\n\n\nstatic void pci_dvobj_deinit(struct pci_dev *pdev)\n{\n\tstruct dvobj_priv *dvobj = pci_get_drvdata(pdev);\n\n\tpci_set_drvdata(pdev, NULL);\n\tif (dvobj) {\n\t\tif (dvobj->irq_alloc) {\n\t\t\tfree_irq(pdev->irq, dvobj);\n#ifndef CONFIG_RTW_PCI_MSI_DISABLE\n\t\t\tpci_disable_msi(pdev);\n#endif\n\t\t\tdvobj->irq_alloc = 0;\n\t\t}\n\n\t\tif (dvobj->pci_mem_start != 0) {\n#if 1/* def RTK_DMP_PLATFORM */\n\t\t\tpci_iounmap(pdev, (void *)dvobj->pci_mem_start);\n#endif\n\t\t\tdvobj->pci_mem_start = 0;\n\t\t}\n\n#ifdef RTK_129X_PLATFORM\n\t\tif (dvobj->ctrl_start != 0) {\n\t\t\tpci_iounmap(pdev, (void *)dvobj->ctrl_start);\n\t\t\tdvobj->ctrl_start = 0;\n\t\t}\n#endif\n\t\tdevobj_deinit(dvobj);\n\t}\n\n\tpci_release_regions(pdev);\n\tpci_disable_device(pdev);\n\n}\n\n\nu8 rtw_set_hal_ops(_adapter *padapter)\n{\n\t/* alloc memory for HAL DATA */\n\tif (rtw_hal_data_init(padapter) == _FAIL)\n\t\treturn _FAIL;\n\n#ifdef CONFIG_RTL8188E\n\tif (rtw_get_chip_type(padapter) == RTL8188E)\n\t\trtl8188ee_set_hal_ops(padapter);\n#endif\n\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\n\tif ((rtw_get_chip_type(padapter) == RTL8812) || (rtw_get_chip_type(padapter) == RTL8821))\n\t\trtl8812ae_set_hal_ops(padapter);\n#endif\n\n#ifdef CONFIG_RTL8723B\n\tif (rtw_get_chip_type(padapter) == RTL8723B)\n\t\trtl8723be_set_hal_ops(padapter);\n#endif\n\n#ifdef CONFIG_RTL8723D\n\tif (rtw_get_chip_type(padapter) == RTL8723D)\n\t\trtl8723de_set_hal_ops(padapter);\n#endif\n\n#ifdef CONFIG_RTL8192E\n\tif (rtw_get_chip_type(padapter) == RTL8192E)\n\t\trtl8192ee_set_hal_ops(padapter);\n#endif\n\n#ifdef CONFIG_RTL8192F\n\tif (rtw_get_chip_type(padapter) == RTL8192F)\n\t\trtl8192fe_set_hal_ops(padapter);\n#endif\n\n#ifdef CONFIG_RTL8814A\n\tif (rtw_get_chip_type(padapter) == RTL8814A)\n\t\trtl8814ae_set_hal_ops(padapter);\n#endif\n\n#if defined(CONFIG_RTL8822B)\n\tif (rtw_get_chip_type(padapter) == RTL8822B)\n\t\trtl8822be_set_hal_ops(padapter);\n#endif\n#if defined(CONFIG_RTL8821C)\n\tif (rtw_get_chip_type(padapter) == RTL8821C)\n\t\trtl8821ce_set_hal_ops(padapter);\n#endif\n\n#if defined(CONFIG_RTL8822C)\n\tif (rtw_get_chip_type(padapter) == RTL8822C)\n\t\trtl8822ce_set_hal_ops(padapter);\n#endif\n\n\tif (rtw_hal_ops_check(padapter) == _FAIL)\n\t\treturn _FAIL;\n\n\tif (hal_spec_init(padapter) == _FAIL)\n\t\treturn _FAIL;\n\n\treturn _SUCCESS;\n}\n\nvoid pci_set_intf_ops(_adapter *padapter, struct _io_ops *pops)\n{\n#ifdef CONFIG_RTL8188E\n\tif (rtw_get_chip_type(padapter) == RTL8188E)\n\t\trtl8188ee_set_intf_ops(pops);\n#endif\n\n#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)\n\tif ((rtw_get_chip_type(padapter) == RTL8812) || (rtw_get_chip_type(padapter) == RTL8821))\n\t\trtl8812ae_set_intf_ops(pops);\n#endif\n\n#ifdef CONFIG_RTL8723B\n\tif (rtw_get_chip_type(padapter) == RTL8723B)\n\t\trtl8723be_set_intf_ops(pops);\n#endif\n\n#ifdef CONFIG_RTL8723D\n\tif (rtw_get_chip_type(padapter) == RTL8723D)\n\t\trtl8723de_set_intf_ops(pops);\n#endif\n\n#ifdef CONFIG_RTL8192E\n\tif (rtw_get_chip_type(padapter) == RTL8192E)\n\t\trtl8192ee_set_intf_ops(pops);\n#endif\n\n#ifdef CONFIG_RTL8192F\n\tif (rtw_get_chip_type(padapter) == RTL8192F)\n\t\trtl8192fe_set_intf_ops(pops);\n#endif\n\n#ifdef CONFIG_RTL8814A\n\tif (rtw_get_chip_type(padapter) == RTL8814A)\n\t\trtl8814ae_set_intf_ops(pops);\n#endif\n\n#if defined(CONFIG_RTL8822B)\n\tif (rtw_get_chip_type(padapter) == RTL8822B)\n\t\trtl8822be_set_intf_ops(pops);\n#endif\n\n#if defined(CONFIG_RTL8821C)\n\tif (rtw_get_chip_type(padapter) == RTL8821C)\n\t\trtl8821ce_set_intf_ops(pops);\n#endif\n\n#if defined(CONFIG_RTL8822C)\n\tif (rtw_get_chip_type(padapter) == RTL8822C)\n\t\trtl8822ce_set_intf_ops(pops);\n#endif\n\n}\n\nstatic void pci_intf_start(_adapter *padapter)\n{\n\tu8 en_sw_bcn = _TRUE;\n\n\tRTW_INFO(\"+pci_intf_start\\n\");\n\n\t/* Enable hw interrupt */\n\trtw_hal_enable_interrupt(padapter);\n\trtw_hal_set_hwreg(padapter, HW_VAR_ENSWBCN, &en_sw_bcn);\n\n#ifdef CONFIG_PCI_TX_POLLING\n\trtw_tx_poll_init(padapter);\n#endif\n\n\tRTW_INFO(\"-pci_intf_start\\n\");\n}\nstatic void rtw_mi_pci_tasklets_kill(_adapter *padapter)\n{\n\tint i;\n\t_adapter *iface;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif ((iface) && rtw_is_adapter_up(iface)) {\n\t\t\ttasklet_kill(&(padapter->recvpriv.recv_tasklet));\n\t\t\ttasklet_kill(&(padapter->recvpriv.irq_prepare_beacon_tasklet));\n\t\t\ttasklet_kill(&(padapter->xmitpriv.xmit_tasklet));\n\t\t}\n\t}\n}\n\nstatic void pci_intf_stop(_adapter *padapter)\n{\n\n\n\t/* Disable hw interrupt */\n\tif (!rtw_is_surprise_removed(padapter)) {\n\t\t/* device still exists, so driver can do i/o operation */\n\t\trtw_hal_disable_interrupt(padapter);\n\t\trtw_mi_pci_tasklets_kill(padapter);\n\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_PCIE_STOP_TX_DMA, 0);\n\n\t\trtw_hal_irp_reset(padapter);\n\n\t} else {\n\t\t/* Clear irq_enabled to prevent handle interrupt function. */\n\t\tadapter_to_dvobj(padapter)->irq_enabled = 0;\n\t}\n\n#ifdef CONFIG_PCI_TX_POLLING\n\trtw_tx_poll_timer_cancel(padapter);\n#endif\n\n}\n\nstatic void disable_ht_for_spec_devid(const struct pci_device_id *pdid)\n{\n#ifdef CONFIG_80211N_HT\n\tu16 vid, pid;\n\tu32 flags;\n\tint i;\n\tint num = sizeof(specific_device_id_tbl) / sizeof(struct specific_device_id);\n\n\tfor (i = 0; i < num; i++) {\n\t\tvid = specific_device_id_tbl[i].idVendor;\n\t\tpid = specific_device_id_tbl[i].idProduct;\n\t\tflags = specific_device_id_tbl[i].flags;\n\n\t\tif ((pdid->vendor == vid) && (pdid->device == pid) && (flags & SPEC_DEV_ID_DISABLE_HT)) {\n\t\t\trtw_ht_enable = 0;\n\t\t\trtw_bw_mode = 0;\n\t\t\trtw_ampdu_enable = 0;\n\t\t}\n\n\t}\n#endif\n}\n\n#ifdef CONFIG_PM\nstatic int rtw_pci_suspend(struct pci_dev *pdev, pm_message_t state)\n{\n\tint ret = 0;\n\tstruct dvobj_priv *dvobj = pci_get_drvdata(pdev);\n\t_adapter *padapter = dvobj_get_primary_adapter(dvobj);\n\n\tret = rtw_suspend_common(padapter);\n\tret = pci_save_state(pdev);\n\tif (ret != 0) {\n\t\tRTW_INFO(\"%s Failed on pci_save_state (%d)\\n\", __func__, ret);\n\t\tgoto exit;\n\t}\n\n#ifdef CONFIG_WOWLAN\n\tdevice_set_wakeup_enable(&pdev->dev, true);\n#endif\n\tpci_disable_device(pdev);\n\n#ifdef CONFIG_WOWLAN\n\tret = pci_enable_wake(pdev, pci_choose_state(pdev, state), true);\n\tif (ret != 0)\n\t\tRTW_INFO(\"%s Failed on pci_enable_wake (%d)\\n\", __func__, ret);\n#endif\n\tret = pci_set_power_state(pdev, pci_choose_state(pdev, state));\n\tif (ret != 0)\n\t\tRTW_INFO(\"%s Failed on pci_set_power_state (%d)\\n\", __func__, ret);\n\nexit:\n\treturn ret;\n\n}\n\nint rtw_resume_process(_adapter *padapter)\n{\n\treturn rtw_resume_common(padapter);\n}\n\nstatic int rtw_pci_resume(struct pci_dev *pdev)\n{\n\tstruct dvobj_priv *dvobj = pci_get_drvdata(pdev);\n\t_adapter *padapter = dvobj_get_primary_adapter(dvobj);\n\tstruct net_device *pnetdev = padapter->pnetdev;\n\tstruct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);\n\tint\terr = 0;\n\n\terr = pci_set_power_state(pdev, PCI_D0);\n\tif (err != 0) {\n\t\tRTW_INFO(\"%s Failed on pci_set_power_state (%d)\\n\", __func__, err);\n\t\tgoto exit;\n\t}\n\n\terr = pci_enable_device(pdev);\n\tif (err != 0) {\n\t\tRTW_INFO(\"%s Failed on pci_enable_device (%d)\\n\", __func__, err);\n\t\tgoto exit;\n\t}\n\n\n#ifdef CONFIG_WOWLAN\n\terr =  pci_enable_wake(pdev, PCI_D0, 0);\n\tif (err != 0) {\n\t\tRTW_INFO(\"%s Failed on pci_enable_wake (%d)\\n\", __func__, err);\n\t\tgoto exit;\n\t}\n#endif\n#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 37))\n\tpci_restore_state(pdev);\n#else\n\terr = pci_restore_state(pdev);\n\tif (err != 0) {\n\t\tRTW_INFO(\"%s Failed on pci_restore_state (%d)\\n\", __func__, err);\n\t\tgoto exit;\n\t}\n#endif\n\n#ifdef CONFIG_WOWLAN\n\tdevice_set_wakeup_enable(&pdev->dev, false);\n#endif\n\n\tif (pwrpriv->wowlan_mode || pwrpriv->wowlan_ap_mode) {\n\t\trtw_resume_lock_suspend();\n\t\terr = rtw_resume_process(padapter);\n\t\trtw_resume_unlock_suspend();\n\t} else {\n#ifdef CONFIG_RESUME_IN_WORKQUEUE\n\t\trtw_resume_in_workqueue(pwrpriv);\n#else\n\t\tif (rtw_is_earlysuspend_registered(pwrpriv)) {\n\t\t\t/* jeff: bypass resume here, do in late_resume */\n\t\t\trtw_set_do_late_resume(pwrpriv, _TRUE);\n\t\t} else {\n\t\t\trtw_resume_lock_suspend();\n\t\t\terr = rtw_resume_process(padapter);\n\t\t\trtw_resume_unlock_suspend();\n\t\t}\n#endif\n\t}\n\nexit:\n\n\treturn err;\n}\n#endif/* CONFIG_PM */\n\n_adapter *rtw_pci_primary_adapter_init(struct dvobj_priv *dvobj, struct pci_dev *pdev)\n{\n\t_adapter *padapter = NULL;\n\tint status = _FAIL;\n\n\tpadapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter));\n\tif (padapter == NULL)\n\t\tgoto exit;\n\n\tif (loadparam(padapter) != _SUCCESS)\n\t\tgoto free_adapter;\n\n\tpadapter->dvobj = dvobj;\n\n\trtw_set_drv_stopped(padapter);/*init*/\n\n\tdvobj->padapters[dvobj->iface_nums++] = padapter;\n\tpadapter->iface_id = IFACE_ID0;\n\n\t/* set adapter_type/iface type for primary padapter */\n\tpadapter->isprimary = _TRUE;\n\tpadapter->adapter_type = PRIMARY_ADAPTER;\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\tpadapter->hw_port = HW_PORT0;\n#else\n\tpadapter->hw_port = HW_PORT0;\n#endif\n\n\tif (rtw_init_io_priv(padapter, pci_set_intf_ops) == _FAIL)\n\t\tgoto free_adapter;\n\n\t/* step 2.\thook HalFunc, allocate HalData */\n\t/* hal_set_hal_ops(padapter); */\n\tif (rtw_set_hal_ops(padapter) == _FAIL)\n\t\tgoto free_hal_data;\n\n\t/* step 3. */\n\tpadapter->intf_start = &pci_intf_start;\n\tpadapter->intf_stop = &pci_intf_stop;\n\n\t/* .3 */\n\trtw_hal_read_chip_version(padapter);\n\n\t/* .4 */\n\trtw_hal_chip_configure(padapter);\n\n#ifdef CONFIG_BT_COEXIST\n\trtw_btcoex_Initialize(padapter);\n#endif\n\trtw_btcoex_wifionly_initialize(padapter);\n\n\t/* step 4. read efuse/eeprom data and get mac_addr */\n\tif (rtw_hal_read_chip_info(padapter) == _FAIL)\n\t\tgoto free_hal_data;\n\n\t/* step 5. */\n\tif (rtw_init_drv_sw(padapter) == _FAIL)\n\t\tgoto free_hal_data;\n\n\tif (rtw_hal_inirp_init(padapter) == _FAIL)\n\t\tgoto free_hal_data;\n\n\trtw_macaddr_cfg(adapter_mac_addr(padapter),  get_hal_mac_addr(padapter));\n\n#ifdef CONFIG_MI_WITH_MBSSID_CAM\n\trtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter));\n#endif\n#ifdef CONFIG_P2P\n\trtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));\n#endif /* CONFIG_P2P */\n\n\trtw_hal_disable_interrupt(padapter);\n\n\t/* step 6. Init pci related configuration */\n\trtw_pci_initialize_adapter_common(padapter);\n\n\tRTW_INFO(\"bDriverStopped:%s, bSurpriseRemoved:%s, bup:%d, hw_init_completed:%s\\n\"\n\t\t , rtw_is_drv_stopped(padapter) ? \"True\" : \"False\"\n\t\t , rtw_is_surprise_removed(padapter) ? \"True\" : \"False\"\n\t\t , padapter->bup\n\t\t , rtw_is_hw_init_completed(padapter) ? \"True\" : \"False\"\n\t\t);\n\n\tstatus = _SUCCESS;\n\nfree_hal_data:\n\tif (status != _SUCCESS && padapter->HalData)\n\t\trtw_hal_free_data(padapter);\n\nfree_adapter:\n\tif (status != _SUCCESS && padapter) {\n\t\t#ifdef RTW_HALMAC\n\t\trtw_halmac_deinit_adapter(dvobj);\n\t\t#endif\n\t\trtw_vmfree((u8 *)padapter, sizeof(*padapter));\n\t\tpadapter = NULL;\n\t}\nexit:\n\treturn padapter;\n}\n\nstatic void rtw_pci_primary_adapter_deinit(_adapter *padapter)\n{\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\n\t/*\tpadapter->intf_stop(padapter); */\n\n\tif (check_fwstate(pmlmepriv, _FW_LINKED))\n\t\trtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY);\n\n#ifdef CONFIG_AP_MODE\n\tif (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {\n\t\tfree_mlme_ap_info(padapter);\n#ifdef CONFIG_HOSTAPD_MLME\n\t\thostapd_mode_unload(padapter);\n#endif\n\t}\n#endif\n\n\t/*rtw_cancel_all_timer(padapte);*/\n#ifdef CONFIG_WOWLAN\n\tadapter_to_pwrctl(padapter)->wowlan_mode = _FALSE;\n#endif /* CONFIG_WOWLAN */\n\trtw_dev_unload(padapter);\n\n\tRTW_INFO(\"%s, hw_init_completed=%s\\n\", __func__, rtw_is_hw_init_completed(padapter) ? \"_TRUE\" : \"_FALSE\");\n\n\trtw_hal_inirp_deinit(padapter);\n\trtw_free_drv_sw(padapter);\n\n\t/* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */\n\trtw_os_ndev_free(padapter);\n\n#ifdef RTW_HALMAC\n\trtw_halmac_deinit_adapter(adapter_to_dvobj(padapter));\n#endif /* RTW_HALMAC */\n\n\trtw_vmfree((u8 *)padapter, sizeof(_adapter));\n\n#ifdef CONFIG_PLATFORM_RTD2880B\n\tRTW_INFO(\"wlan link down\\n\");\n\trtd2885_wlan_netlink_sendMsg(\"linkdown\", \"8712\");\n#endif\n}\n\n/*\n * drv_init() - a device potentially for us\n *\n * notes: drv_init() is called when the bus driver has located a card for us to support.\n *        We accept the new device by returning 0.\n*/\nstatic int rtw_drv_init(struct pci_dev *pdev, const struct pci_device_id *pdid)\n{\n\tint i, err = -ENODEV;\n\n\tint status = _FAIL;\n\t_adapter *padapter = NULL;\n\tstruct dvobj_priv *dvobj;\n\tstruct net_device *pnetdev;\n\n\t/* RTW_INFO(\"+rtw_drv_init\\n\"); */\n\n\t/* step 0. */\n\tdisable_ht_for_spec_devid(pdid);\n\n\t/* Initialize dvobj_priv */\n\tdvobj = pci_dvobj_init(pdev, pdid);\n\tif (dvobj == NULL)\n\t\tgoto exit;\n\n\t/* Initialize primary adapter */\n\tpadapter = rtw_pci_primary_adapter_init(dvobj, pdev);\n\tif (padapter == NULL) {\n\t\tRTW_INFO(\"rtw_pci_primary_adapter_init Failed!\\n\");\n\t\tgoto free_dvobj;\n\t}\n\n\t/* Initialize virtual interface */\n#ifdef CONFIG_CONCURRENT_MODE\n\tif (padapter->registrypriv.virtual_iface_num > (CONFIG_IFACE_NUMBER - 1))\n\t\tpadapter->registrypriv.virtual_iface_num = (CONFIG_IFACE_NUMBER - 1);\n\n\tfor (i = 0; i < padapter->registrypriv.virtual_iface_num; i++) {\n\t\tif (rtw_drv_add_vir_if(padapter, pci_set_intf_ops) == NULL) {\n\t\t\tRTW_INFO(\"rtw_drv_add_iface failed! (%d)\\n\", i);\n\t\t\tgoto free_if_vir;\n\t\t}\n\t}\n#endif\n\n#ifdef CONFIG_GLOBAL_UI_PID\n\tif (ui_pid[1] != 0) {\n\t\tRTW_INFO(\"ui_pid[1]:%d\\n\", ui_pid[1]);\n\t\trtw_signal_process(ui_pid[1], SIGUSR2);\n\t}\n#endif\n\n\t/* dev_alloc_name && register_netdev */\n\tif (rtw_os_ndevs_init(dvobj) != _SUCCESS)\n\t\tgoto free_if_vir;\n\n#ifdef CONFIG_HOSTAPD_MLME\n\thostapd_mode_init(padapter);\n#endif\n\n#ifdef CONFIG_PLATFORM_RTD2880B\n\tRTW_INFO(\"wlan link up\\n\");\n\trtd2885_wlan_netlink_sendMsg(\"linkup\", \"8712\");\n#endif\n\n\t/* alloc irq */\n\tif (pci_alloc_irq(dvobj) != _SUCCESS)\n\t\tgoto os_ndevs_deinit;\n\n\t/* RTW_INFO(\"-871x_drv - drv_init, success!\\n\"); */\n\n\tstatus = _SUCCESS;\n\nos_ndevs_deinit:\n\tif (status != _SUCCESS)\n\t\trtw_os_ndevs_deinit(dvobj);\nfree_if_vir:\n\tif (status != _SUCCESS) {\n#ifdef CONFIG_CONCURRENT_MODE\n\t\trtw_drv_stop_vir_ifaces(dvobj);\n\t\trtw_drv_free_vir_ifaces(dvobj);\n#endif\n\t}\n\n\tif (status != _SUCCESS && padapter)\n\t\trtw_pci_primary_adapter_deinit(padapter);\n\nfree_dvobj:\n\tif (status != _SUCCESS)\n\t\tpci_dvobj_deinit(pdev);\nexit:\n\treturn status == _SUCCESS ? 0 : -ENODEV;\n}\n\n/*\n * dev_remove() - our device is being removed\n*/\n/* rmmod module & unplug(SurpriseRemoved) will call r871xu_dev_remove() => how to recognize both */\nstatic void rtw_dev_remove(struct pci_dev *pdev)\n{\n\tstruct dvobj_priv *pdvobjpriv = pci_get_drvdata(pdev);\n\t_adapter *padapter = dvobj_get_primary_adapter(pdvobjpriv);\n\tstruct net_device *pnetdev = padapter->pnetdev;\n\n\tif (pdvobjpriv->processing_dev_remove == _TRUE) {\n\t\tRTW_WARN(\"%s-line%d: Warning! device has been removed!\\n\", __func__, __LINE__);\n\t\treturn;\n\t}\n\n\tRTW_INFO(\"+rtw_dev_remove\\n\");\n\n\tpdvobjpriv->processing_dev_remove = _TRUE;\n\n\tif (unlikely(!padapter))\n\t\treturn;\n\n\t/* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */\n\trtw_os_ndevs_unregister(pdvobjpriv);\n\n#if 0\n#ifdef RTK_DMP_PLATFORM\n\trtw_clr_surprise_removed(padapter);\t/* always trate as device exists*/\n\t/* this will let the driver to disable it's interrupt */\n#else\n\tif (pci_drvpriv.drv_registered == _TRUE) {\n\t\t/* RTW_INFO(\"r871xu_dev_remove():padapter->bSurpriseRemoved == _TRUE\\n\"); */\n\t\trtw_set_surprise_removed(padapter);\n\t}\n\t/*else\n\t{\n\n\t\trtw_set_hw_init_completed(padapter, _FALSE);\n\n\t}*/\n#endif\n#endif\n\n#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)\n\trtw_unregister_early_suspend(dvobj_to_pwrctl(pdvobjpriv));\n#endif\n\n\tif (GET_HAL_DATA(padapter)->bFWReady == _TRUE) {\n\t\trtw_pm_set_ips(padapter, IPS_NONE);\n\t\trtw_pm_set_lps(padapter, PS_MODE_ACTIVE);\n\n\t\tLeaveAllPowerSaveMode(padapter);\n\t}\n\n\trtw_set_drv_stopped(padapter);\t/*for stop thread*/\n\trtw_stop_cmd_thread(padapter);\n#ifdef CONFIG_CONCURRENT_MODE\n\trtw_drv_stop_vir_ifaces(pdvobjpriv);\n#endif\n\n#ifdef CONFIG_BT_COEXIST\n#ifdef CONFIG_BT_COEXIST_SOCKET_TRX\n\tif (GET_HAL_DATA(padapter)->EEPROMBluetoothCoexist)\n\t\trtw_btcoex_close_socket(padapter);\n#endif\n\trtw_btcoex_HaltNotify(padapter);\n#endif\n\n\trtw_pci_primary_adapter_deinit(padapter);\n\n#ifdef CONFIG_CONCURRENT_MODE\n\trtw_drv_free_vir_ifaces(pdvobjpriv);\n#endif\n\n\tpci_dvobj_deinit(pdev);\n\n\tRTW_INFO(\"-r871xu_dev_remove, done\\n\");\n\n\treturn;\n}\n\nstatic void rtw_dev_shutdown(struct pci_dev *pdev)\n{\n\tstruct dvobj_priv *pdvobjpriv = pci_get_drvdata(pdev);\n\t_adapter *padapter = dvobj_get_primary_adapter(pdvobjpriv);\n\tstruct net_device *pnetdev = padapter->pnetdev;\n\n#ifdef CONFIG_RTL8723D\n\tif (IS_HARDWARE_TYPE_8723DE(padapter)) {\n\t\tu8 u1Tmp;\n\n\t\tu1Tmp = PlatformEFIORead1Byte(padapter, 0x75 /*REG_HCI_OPT_CTRL_8723D+1*/);\n\t\tPlatformEFIOWrite1Byte(padapter, 0x75 /*REG_HCI_OPT_CTRL_8723D+1*/, (u1Tmp|BIT0));/*Disable USB Suspend Signal*/\n\t}\n#endif\n\n\trtw_dev_remove(pdev);\n}\n\nstatic int __init rtw_drv_entry(void)\n{\n\tint ret = 0;\n\n\tRTW_PRINT(\"module init start\\n\");\n\tdump_drv_version(RTW_DBGDUMP);\n#ifdef BTCOEXVERSION\n\tRTW_PRINT(DRV_NAME\" BT-Coex version = %s\\n\", BTCOEXVERSION);\n#endif /* BTCOEXVERSION */\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))\n\t/* console_suspend_enabled=0; */\n#endif\n\n\tpci_drvpriv.drv_registered = _TRUE;\n\trtw_suspend_lock_init();\n\trtw_drv_proc_init();\n\trtw_ndev_notifier_register();\n\trtw_inetaddr_notifier_register();\n\n\tret = pci_register_driver(&pci_drvpriv.rtw_pci_drv);\n\n\tif (ret != 0) {\n\t\tpci_drvpriv.drv_registered = _FALSE;\n\t\trtw_suspend_lock_uninit();\n\t\trtw_drv_proc_deinit();\n\t\trtw_ndev_notifier_unregister();\n\t\trtw_inetaddr_notifier_unregister();\n\t\tgoto exit;\n\t}\n\nexit:\n\tRTW_PRINT(\"module init ret=%d\\n\", ret);\n\treturn ret;\n}\n\nstatic void __exit rtw_drv_halt(void)\n{\n\tRTW_PRINT(\"module exit start\\n\");\n\n\tpci_drvpriv.drv_registered = _FALSE;\n\n\tpci_unregister_driver(&pci_drvpriv.rtw_pci_drv);\n\n\trtw_suspend_lock_uninit();\n\trtw_drv_proc_deinit();\n\trtw_ndev_notifier_unregister();\n\trtw_inetaddr_notifier_unregister();\n\n\tRTW_PRINT(\"module exit success\\n\");\n\n\trtw_mstat_dump(RTW_DBGDUMP);\n}\n\n\nmodule_init(rtw_drv_entry);\nmodule_exit(rtw_drv_halt);\n"
  },
  {
    "path": "os_dep/linux/pci_ops_linux.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _PCI_OPS_LINUX_C_\n\n#include <drv_types.h>\n"
  },
  {
    "path": "os_dep/linux/recv_linux.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _RECV_OSDEP_C_\n\n#include <drv_types.h>\n\nint rtw_os_recvframe_duplicate_skb(_adapter *padapter, union recv_frame *pcloneframe, _pkt *pskb)\n{\n\tint res = _SUCCESS;\n\t_pkt\t*pkt_copy = NULL;\n\n\tif (pskb == NULL) {\n\t\tRTW_INFO(\"%s [WARN] skb == NULL, drop frag frame\\n\", __func__);\n\t\treturn _FAIL;\n\t}\n#if 1\n\tpkt_copy = rtw_skb_copy(pskb);\n\n\tif (pkt_copy == NULL) {\n\t\tRTW_INFO(\"%s [WARN] rtw_skb_copy fail , drop frag frame\\n\", __func__);\n\t\treturn _FAIL;\n\t}\n#else\n\tpkt_copy = rtw_skb_clone(pskb);\n\n\tif (pkt_copy == NULL) {\n\t\tRTW_INFO(\"%s [WARN] rtw_skb_clone fail , drop frag frame\\n\", __func__);\n\t\treturn _FAIL;\n\t}\n#endif\n\tpkt_copy->dev = padapter->pnetdev;\n\n\tpcloneframe->u.hdr.pkt = pkt_copy;\n\tpcloneframe->u.hdr.rx_head = pkt_copy->head;\n\tpcloneframe->u.hdr.rx_data = pkt_copy->data;\n\tpcloneframe->u.hdr.rx_end = skb_end_pointer(pkt_copy);\n\tpcloneframe->u.hdr.rx_tail = skb_tail_pointer(pkt_copy);\n\tpcloneframe->u.hdr.len = pkt_copy->len;\n\n\treturn res;\n}\n\nint rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 *pdata, _pkt *pskb)\n{\n\tint res = _SUCCESS;\n\tu8\tshift_sz = 0;\n\tu32\tskb_len, alloc_sz;\n\t_pkt\t*pkt_copy = NULL;\n\tstruct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;\n\n\n\tif (pdata == NULL) {\n\t\tprecvframe->u.hdr.pkt = NULL;\n\t\tres = _FAIL;\n\t\treturn res;\n\t}\n\n\n\t/*\tModified by Albert 20101213 */\n\t/*\tFor 8 bytes IP header alignment. */\n\tshift_sz = pattrib->qos ? 6 : 0; /*\tQos data, wireless lan header length is 26 */\n\n\tskb_len = pattrib->pkt_len;\n\n\t/* for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. */\n\t/* modify alloc_sz for recvive crc error packet by thomas 2011-06-02 */\n\tif ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) {\n\t\t/* alloc_sz = 1664;\t */ /* 1664 is 128 alignment. */\n\t\talloc_sz = (skb_len <= 1650) ? 1664 : (skb_len + 14);\n\t} else {\n\t\talloc_sz = skb_len;\n\t\t/*\t6 is for IP header 8 bytes alignment in QoS packet case. */\n\t\t/*\t8 is for skb->data 4 bytes alignment. */\n\t\talloc_sz += 14;\n\t}\n\n\tpkt_copy = rtw_skb_alloc(alloc_sz);\n\n\tif (pkt_copy) {\n\t\tpkt_copy->dev = padapter->pnetdev;\n\t\tpkt_copy->len = skb_len;\n\t\tprecvframe->u.hdr.pkt = pkt_copy;\n\t\tprecvframe->u.hdr.rx_head = pkt_copy->head;\n\t\tprecvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz;\n\t\tskb_reserve(pkt_copy, 8 - ((SIZE_PTR)(pkt_copy->data) & 7));  /* force pkt_copy->data at 8-byte alignment address */\n\t\tskb_reserve(pkt_copy, shift_sz);/* force ip_hdr at 8-byte alignment address according to shift_sz. */\n\t\t_rtw_memcpy(pkt_copy->data, pdata, skb_len);\n\t\tprecvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data;\n\t} else {\n#if 0\n\t\t{\n\t\t\trtw_free_recvframe(precvframe_if2, &precvpriv->free_recv_queue);\n\t\t\trtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);\n\n\t\t\t/* The case of can't allocate skb is serious and may never be recovered,\n\t\t\t once bDriverStopped is enable, this task should be stopped.*/\n\t\t\tif (!rtw_is_drv_stopped(secondary_padapter))\n#ifdef PLATFORM_LINUX\n\t\t\t\ttasklet_schedule(&precvpriv->recv_tasklet);\n#endif\n\t\t\treturn ret;\n\t\t}\n\n#endif\n\n#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX\n\t\tRTW_INFO(\"%s:can not allocate memory for skb copy\\n\", __func__);\n\n\t\tprecvframe->u.hdr.pkt = NULL;\n\n\t\t/* rtw_free_recvframe(precvframe, pfree_recv_queue); */\n\t\t/*exit_rtw_os_recv_resource_alloc;*/\n\n\t\tres = _FAIL;\n#else\n\t\tif ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) {\n\t\t\tRTW_INFO(\"%s: alloc_skb fail , drop frag frame\\n\", __FUNCTION__);\n\t\t\t/* rtw_free_recvframe(precvframe, pfree_recv_queue); */\n\t\t\tres = _FAIL;\n\t\t\tgoto exit_rtw_os_recv_resource_alloc;\n\t\t}\n\n\t\tif (pskb == NULL) {\n\t\t\tres = _FAIL;\n\t\t\tgoto exit_rtw_os_recv_resource_alloc;\n\t\t}\n\n\t\tprecvframe->u.hdr.pkt = rtw_skb_clone(pskb);\n\t\tif (precvframe->u.hdr.pkt) {\n\t\t\tprecvframe->u.hdr.pkt->dev = padapter->pnetdev;\n\t\t\tprecvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pdata;\n\t\t\tprecvframe->u.hdr.rx_end =  pdata + alloc_sz;\n\t\t} else {\n\t\t\tRTW_INFO(\"%s: rtw_skb_clone fail\\n\", __FUNCTION__);\n\t\t\t/* rtw_free_recvframe(precvframe, pfree_recv_queue); */\n\t\t\t/*exit_rtw_os_recv_resource_alloc;*/\n\t\t\tres = _FAIL;\n\t\t}\n#endif\n\t}\n\nexit_rtw_os_recv_resource_alloc:\n\n\treturn res;\n\n}\n\nvoid rtw_os_free_recvframe(union recv_frame *precvframe)\n{\n\tif (precvframe->u.hdr.pkt) {\n\t\trtw_os_pkt_free(precvframe->u.hdr.pkt);\n\t\tprecvframe->u.hdr.pkt = NULL;\n\t}\n}\n\n/* init os related resource in struct recv_priv */\nint rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter)\n{\n\tint\tres = _SUCCESS;\n\n\n#ifdef CONFIG_RTW_NAPI\n\tskb_queue_head_init(&precvpriv->rx_napi_skb_queue);\n#endif /* CONFIG_RTW_NAPI */\n\n\treturn res;\n}\n\n/* alloc os related resource in union recv_frame */\nint rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe)\n{\n\tint\tres = _SUCCESS;\n\n\tprecvframe->u.hdr.pkt = NULL;\n\n\treturn res;\n}\n\n/* free os related resource in union recv_frame */\nvoid rtw_os_recv_resource_free(struct recv_priv *precvpriv)\n{\n\tsint i;\n\tunion recv_frame *precvframe;\n\tprecvframe = (union recv_frame *) precvpriv->precv_frame_buf;\n\n\n#ifdef CONFIG_RTW_NAPI\n\tif (skb_queue_len(&precvpriv->rx_napi_skb_queue))\n\t\tRTW_WARN(\"rx_napi_skb_queue not empty\\n\");\n\trtw_skb_queue_purge(&precvpriv->rx_napi_skb_queue);\n#endif /* CONFIG_RTW_NAPI */\n\n\tfor (i = 0; i < NR_RECVFRAME; i++) {\n\t\trtw_os_free_recvframe(precvframe);\n\t\tprecvframe++;\n\t}\n}\n\n/* alloc os related resource in struct recv_buf */\nint rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf)\n{\n\tint res = _SUCCESS;\n\n#ifdef CONFIG_USB_HCI\n#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct usb_device\t*pusbd = pdvobjpriv->pusbdev;\n#endif\n\n\tprecvbuf->irp_pending = _FALSE;\n\tprecvbuf->purb = usb_alloc_urb(0, GFP_KERNEL);\n\tif (precvbuf->purb == NULL)\n\t\tres = _FAIL;\n\n\tprecvbuf->pskb = NULL;\n\n\tprecvbuf->pallocated_buf  = precvbuf->pbuf = NULL;\n\n\tprecvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pend = NULL;\n\n\tprecvbuf->transfer_len = 0;\n\n\tprecvbuf->len = 0;\n\n#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX\n\tprecvbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)precvbuf->alloc_sz, &precvbuf->dma_transfer_addr);\n\tprecvbuf->pbuf = precvbuf->pallocated_buf;\n\tif (precvbuf->pallocated_buf == NULL)\n\t\treturn _FAIL;\n#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */\n\n#endif /* CONFIG_USB_HCI */\n\n\treturn res;\n}\n\n/* free os related resource in struct recv_buf */\nint rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf)\n{\n\tint ret = _SUCCESS;\n\n#ifdef CONFIG_USB_HCI\n\n#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX\n\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\tstruct usb_device\t*pusbd = pdvobjpriv->pusbdev;\n\n\trtw_usb_buffer_free(pusbd, (size_t)precvbuf->alloc_sz, precvbuf->pallocated_buf, precvbuf->dma_transfer_addr);\n\tprecvbuf->pallocated_buf =  NULL;\n\tprecvbuf->dma_transfer_addr = 0;\n\n#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */\n\n\tif (precvbuf->purb) {\n\t\t/* usb_kill_urb(precvbuf->purb); */\n\t\tusb_free_urb(precvbuf->purb);\n\t}\n\n#endif /* CONFIG_USB_HCI */\n\n\n\tif (precvbuf->pskb) {\n#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER\n\t\tif (rtw_free_skb_premem(precvbuf->pskb) != 0)\n#endif\n\t\t\trtw_skb_free(precvbuf->pskb);\n\t}\n\treturn ret;\n\n}\n\n_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, const u8 *da, const u8 *sa, u8 *msdu ,u16 msdu_len)\n{\n\tu16\teth_type;\n\tu8\t*data_ptr;\n\t_pkt *sub_skb;\n\tstruct rx_pkt_attrib *pattrib;\n\n\tpattrib = &prframe->u.hdr.attrib;\n\n#ifdef CONFIG_SKB_COPY\n\tsub_skb = rtw_skb_alloc(msdu_len + 14);\n\tif (sub_skb) {\n\t\tskb_reserve(sub_skb, 14);\n\t\tdata_ptr = (u8 *)skb_put(sub_skb, msdu_len);\n\t\t_rtw_memcpy(data_ptr, msdu, msdu_len);\n\t} else\n#endif /* CONFIG_SKB_COPY */\n\t{\n\t\tsub_skb = rtw_skb_clone(prframe->u.hdr.pkt);\n\t\tif (sub_skb) {\n\t\t\tsub_skb->data = msdu;\n\t\t\tsub_skb->len = msdu_len;\n\t\t\tskb_set_tail_pointer(sub_skb, msdu_len);\n\t\t} else {\n\t\t\tRTW_INFO(\"%s(): rtw_skb_clone() Fail!!!\\n\", __FUNCTION__);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\teth_type = RTW_GET_BE16(&sub_skb->data[6]);\n\n\tif (sub_skb->len >= 8\n\t\t&& ((_rtw_memcmp(sub_skb->data, rtw_rfc1042_header, SNAP_SIZE)\n\t\t\t\t&& eth_type != ETH_P_AARP && eth_type != ETH_P_IPX)\n\t\t\t|| _rtw_memcmp(sub_skb->data, rtw_bridge_tunnel_header, SNAP_SIZE))\n\t) {\n\t\t/* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */\n\t\tskb_pull(sub_skb, SNAP_SIZE);\n\t\t_rtw_memcpy(skb_push(sub_skb, ETH_ALEN), sa, ETH_ALEN);\n\t\t_rtw_memcpy(skb_push(sub_skb, ETH_ALEN), da, ETH_ALEN);\n\t} else {\n\t\t/* Leave Ethernet header part of hdr and full payload */\n\t\tu16 len;\n\n\t\tlen = htons(sub_skb->len);\n\t\t_rtw_memcpy(skb_push(sub_skb, 2), &len, 2);\n\t\t_rtw_memcpy(skb_push(sub_skb, ETH_ALEN), sa, ETH_ALEN);\n\t\t_rtw_memcpy(skb_push(sub_skb, ETH_ALEN), da, ETH_ALEN);\n\t}\n\n\treturn sub_skb;\n}\n\n#ifdef CONFIG_RTW_NAPI\nstatic int napi_recv(_adapter *padapter, int budget)\n{\n\t_pkt *pskb;\n\tstruct recv_priv *precvpriv = &padapter->recvpriv;\n\tint work_done = 0;\n\tstruct registry_priv *pregistrypriv = &padapter->registrypriv;\n\tu8 rx_ok;\n\n\n\twhile ((work_done < budget) &&\n\t       (!skb_queue_empty(&precvpriv->rx_napi_skb_queue))) {\n\t\tpskb = skb_dequeue(&precvpriv->rx_napi_skb_queue);\n\t\tif (!pskb)\n\t\t\tbreak;\n\n\t\trx_ok = _FALSE;\n\n#ifdef CONFIG_RTW_GRO\n\t\tif (pregistrypriv->en_gro) {\n\t\t\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0))\n\t\t\t\tif (rtw_napi_gro_receive(&padapter->napi, pskb) != GRO_DROP)\n\t\t\t#else\n\t\t\t\tif (rtw_napi_gro_receive(&padapter->napi, pskb) != GRO_MERGED_FREE)\n\t\t\t#endif\n\t\t\t\trx_ok = _TRUE;\n\t\t\tgoto next;\n\t\t}\n#endif /* CONFIG_RTW_GRO */\n\n\t\tif (rtw_netif_receive_skb(padapter->pnetdev, pskb) == NET_RX_SUCCESS)\n\t\t\trx_ok = _TRUE;\n\nnext:\n\t\tif (rx_ok == _TRUE) {\n\t\t\twork_done++;\n\t\t\tDBG_COUNTER(padapter->rx_logs.os_netif_ok);\n\t\t} else {\n\t\t\tDBG_COUNTER(padapter->rx_logs.os_netif_err);\n\t\t}\n\t}\n\n\treturn work_done;\n}\n\nint rtw_recv_napi_poll(struct napi_struct *napi, int budget)\n{\n\t_adapter *padapter = container_of(napi, _adapter, napi);\n\tint work_done = 0;\n\tstruct recv_priv *precvpriv = &padapter->recvpriv;\n\n\n\twork_done = napi_recv(padapter, budget);\n\tif (work_done < budget) {\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) && defined(CONFIG_PCI_HCI)\n\t\tnapi_complete_done(napi, work_done);\n#else\n\t\tnapi_complete(napi);\n#endif\n\t\tif (!skb_queue_empty(&precvpriv->rx_napi_skb_queue))\n\t\t\tnapi_schedule(napi);\n\t}\n\n\treturn work_done;\n}\n\n#ifdef CONFIG_RTW_NAPI_DYNAMIC\nvoid dynamic_napi_th_chk (_adapter *adapter)\n{\n\n\tif (adapter->registrypriv.en_napi) {\n\t\tstruct dvobj_priv *dvobj;\n\t\tstruct registry_priv *registry;\n\t\n\t\tdvobj = adapter_to_dvobj(adapter);\n\t\tregistry = &adapter->registrypriv;\n\t\tif (dvobj->traffic_stat.cur_rx_tp > registry->napi_threshold)\n\t\t\tdvobj->en_napi_dynamic = 1;\n\t\telse\n\t\t\tdvobj->en_napi_dynamic = 0;\n\t}\n\n}\n#endif /* CONFIG_RTW_NAPI_DYNAMIC */\n#endif /* CONFIG_RTW_NAPI */\n\nvoid rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, union recv_frame *rframe)\n{\n\tstruct mlme_priv *pmlmepriv = &padapter->mlmepriv;\n\tstruct recv_priv *precvpriv = &(padapter->recvpriv);\n\tstruct registry_priv\t*pregistrypriv = &padapter->registrypriv;\n#ifdef CONFIG_BR_EXT\n\tvoid *br_port = NULL;\n#endif\n\tint ret;\n\n\t/* Indicat the packets to upper layer */\n\tif (pkt) {\n\t\tstruct ethhdr *ehdr = (struct ethhdr *)pkt->data;\n\n\t\tDBG_COUNTER(padapter->rx_logs.os_indicate);\n\n\t\tif (MLME_IS_AP(padapter)) {\n\t\t\t_pkt *pskb2 = NULL;\n\t\t\tstruct sta_info *psta = NULL;\n\t\t\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\t\t\tint bmcast = IS_MCAST(ehdr->h_dest);\n\n\t\t\t/* RTW_INFO(\"bmcast=%d\\n\", bmcast); */\n\n\t\t\tif (_rtw_memcmp(ehdr->h_dest, adapter_mac_addr(padapter), ETH_ALEN) == _FALSE) {\n\t\t\t\t/* RTW_INFO(\"not ap psta=%p, addr=%pM\\n\", psta, ehdr->h_dest); */\n\n\t\t\t\tif (bmcast) {\n\t\t\t\t\tpsta = rtw_get_bcmc_stainfo(padapter);\n\t\t\t\t\tpskb2 = rtw_skb_clone(pkt);\n\t\t\t\t} else\n\t\t\t\t\tpsta = rtw_get_stainfo(pstapriv, ehdr->h_dest);\n\n\t\t\t\tif (psta) {\n\t\t\t\t\tstruct net_device *pnetdev = (struct net_device *)padapter->pnetdev;\n\n\t\t\t\t\t/* RTW_INFO(\"directly forwarding to the rtw_xmit_entry\\n\"); */\n\n\t\t\t\t\t/* skb->ip_summed = CHECKSUM_NONE; */\n\t\t\t\t\tpkt->dev = pnetdev;\n\t\t\t\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\t\t\t\t\tskb_set_queue_mapping(pkt, rtw_recv_select_queue(pkt));\n\t\t\t\t\t#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) */\n\n\t\t\t\t\t_rtw_xmit_entry(pkt, pnetdev);\n\n\t\t\t\t\tif (bmcast && (pskb2 != NULL)) {\n\t\t\t\t\t\tpkt = pskb2;\n\t\t\t\t\t\tDBG_COUNTER(padapter->rx_logs.os_indicate_ap_mcast);\n\t\t\t\t\t} else {\n\t\t\t\t\t\tDBG_COUNTER(padapter->rx_logs.os_indicate_ap_forward);\n\t\t\t\t\t\treturn;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else { /* to APself */\n\t\t\t\t/* RTW_INFO(\"to APSelf\\n\"); */\n\t\t\t\tDBG_COUNTER(padapter->rx_logs.os_indicate_ap_self);\n\t\t\t}\n\t\t}\n\n#ifdef CONFIG_BR_EXT\n\t\tif (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) {\n\t\t\t/* Insert NAT2.5 RX here! */\n\t\t\t#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))\n\t\t\tbr_port = padapter->pnetdev->br_port;\n\t\t\t#else\n\t\t\trcu_read_lock();\n\t\t\tbr_port = rcu_dereference(padapter->pnetdev->rx_handler_data);\n\t\t\trcu_read_unlock();\n\t\t\t#endif\n\n\t\t\tif (br_port) {\n\t\t\t\tint nat25_handle_frame(_adapter *priv, struct sk_buff *skb);\n\n\t\t\t\tif (nat25_handle_frame(padapter, pkt) == -1) {\n\t\t\t\t\t/* priv->ext_stats.rx_data_drops++; */\n\t\t\t\t\t/* DEBUG_ERR(\"RX DROP: nat25_handle_frame fail!\\n\"); */\n\t\t\t\t\t/* return FAIL; */\n\n\t\t\t\t\t#if 1\n\t\t\t\t\t/* bypass this frame to upper layer!! */\n\t\t\t\t\t#else\n\t\t\t\t\trtw_skb_free(sub_skb);\n\t\t\t\t\tcontinue;\n\t\t\t\t\t#endif\n\t\t\t\t}\n\t\t\t}\n\t\t}\n#endif /* CONFIG_BR_EXT */\n\n\t\t/* After eth_type_trans process , pkt->data pointer will move from ethrnet header to ip header */\n\t\tpkt->protocol = eth_type_trans(pkt, padapter->pnetdev);\n\t\tpkt->dev = padapter->pnetdev;\n\t\tpkt->ip_summed = CHECKSUM_NONE; /* CONFIG_TCP_CSUM_OFFLOAD_RX */\n#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX\n\t\tif ((rframe->u.hdr.attrib.csum_valid == 1)\n\t\t    && (rframe->u.hdr.attrib.csum_err == 0))\n\t\t\tpkt->ip_summed = CHECKSUM_UNNECESSARY;\n#endif /* CONFIG_TCP_CSUM_OFFLOAD_RX */\n\n#ifdef CONFIG_RTW_NAPI\n#ifdef CONFIG_RTW_NAPI_DYNAMIC\n\t\tif (!skb_queue_empty(&precvpriv->rx_napi_skb_queue)\n\t\t\t&& !adapter_to_dvobj(padapter)->en_napi_dynamic\t\t\t\n\t\t\t)\n\t\t\tnapi_recv(padapter, RTL_NAPI_WEIGHT);\n#endif\n\n\t\tif (pregistrypriv->en_napi\n\t\t\t#ifdef CONFIG_RTW_NAPI_DYNAMIC\n\t\t\t&& adapter_to_dvobj(padapter)->en_napi_dynamic\n\t\t\t#endif\n\t\t) {\n\t\t\tskb_queue_tail(&precvpriv->rx_napi_skb_queue, pkt);\n\t\t\t#ifndef CONFIG_RTW_NAPI_V2\n\t\t\tnapi_schedule(&padapter->napi);\n\t\t\t#endif\n\t\t\treturn;\n\t\t}\n#endif /* CONFIG_RTW_NAPI */\n\n\t\tret = rtw_netif_rx(padapter->pnetdev, pkt);\n\t\tif (ret == NET_RX_SUCCESS)\n\t\t\tDBG_COUNTER(padapter->rx_logs.os_netif_ok);\n\t\telse\n\t\t\tDBG_COUNTER(padapter->rx_logs.os_netif_err);\n\t}\n}\n\nvoid rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup)\n{\n#ifdef CONFIG_IOCTL_CFG80211\n\tenum nl80211_key_type key_type = 0;\n#endif\n\tunion iwreq_data wrqu;\n\tstruct iw_michaelmicfailure    ev;\n\tstruct security_priv\t*psecuritypriv = &padapter->securitypriv;\n\tsystime cur_time = 0;\n\n\tif (psecuritypriv->last_mic_err_time == 0)\n\t\tpsecuritypriv->last_mic_err_time = rtw_get_current_time();\n\telse {\n\t\tcur_time = rtw_get_current_time();\n\n\t\tif (cur_time - psecuritypriv->last_mic_err_time < 60 * HZ) {\n\t\t\tpsecuritypriv->btkip_countermeasure = _TRUE;\n\t\t\tpsecuritypriv->last_mic_err_time = 0;\n\t\t\tpsecuritypriv->btkip_countermeasure_time = cur_time;\n\t\t} else\n\t\t\tpsecuritypriv->last_mic_err_time = rtw_get_current_time();\n\t}\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tif (bgroup)\n\t\tkey_type |= NL80211_KEYTYPE_GROUP;\n\telse\n\t\tkey_type |= NL80211_KEYTYPE_PAIRWISE;\n\n\tcfg80211_michael_mic_failure(padapter->pnetdev, sta->cmn.mac_addr, key_type, -1, NULL, GFP_ATOMIC);\n#endif\n\n\t_rtw_memset(&ev, 0x00, sizeof(ev));\n\tif (bgroup)\n\t\tev.flags |= IW_MICFAILURE_GROUP;\n\telse\n\t\tev.flags |= IW_MICFAILURE_PAIRWISE;\n\n\tev.src_addr.sa_family = ARPHRD_ETHER;\n\t_rtw_memcpy(ev.src_addr.sa_data, sta->cmn.mac_addr, ETH_ALEN);\n\n\t_rtw_memset(&wrqu, 0x00, sizeof(wrqu));\n\twrqu.data.length = sizeof(ev);\n\n#ifndef CONFIG_IOCTL_CFG80211\n\twireless_send_event(padapter->pnetdev, IWEVMICHAELMICFAILURE, &wrqu, (char *) &ev);\n#endif\n}\n\n#ifdef CONFIG_HOSTAPD_MLME\nvoid rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame)\n{\n\t_pkt *skb;\n\tstruct hostapd_priv *phostapdpriv  = padapter->phostapdpriv;\n\tstruct net_device *pmgnt_netdev = phostapdpriv->pmgnt_netdev;\n\n\n\tskb = precv_frame->u.hdr.pkt;\n\n\tif (skb == NULL)\n\t\treturn;\n\n\tskb->data = precv_frame->u.hdr.rx_data;\n\tskb->tail = precv_frame->u.hdr.rx_tail;\n\tskb->len = precv_frame->u.hdr.len;\n\n\t/* pskb_copy = rtw_skb_copy(skb);\n\t*\tif(skb == NULL) goto _exit; */\n\n\tskb->dev = pmgnt_netdev;\n\tskb->ip_summed = CHECKSUM_NONE;\n\tskb->pkt_type = PACKET_OTHERHOST;\n\t/* skb->protocol = __constant_htons(0x0019); ETH_P_80211_RAW */\n\tskb->protocol = __constant_htons(0x0003); /*ETH_P_80211_RAW*/\n\n\t/* RTW_INFO(\"(1)data=0x%x, head=0x%x, tail=0x%x, mac_header=0x%x, len=%d\\n\", skb->data, skb->head, skb->tail, skb->mac_header, skb->len); */\n\n\t/* skb->mac.raw = skb->data; */\n\tskb_reset_mac_header(skb);\n\n\t/* skb_pull(skb, 24); */\n\t_rtw_memset(skb->cb, 0, sizeof(skb->cb));\n\n\trtw_netif_rx(pmgnt_netdev, skb);\n\n\tprecv_frame->u.hdr.pkt = NULL; /* set pointer to NULL before rtw_free_recvframe() if call rtw_netif_rx() */\n}\n#endif /* CONFIG_HOSTAPD_MLME */\n\nint rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tint ret = _FAIL;\n\tstruct recv_priv *precvpriv;\n\t_queue\t*pfree_recv_queue;\n\t_pkt *skb;\n\tstruct rx_pkt_attrib *pattrib;\n\n\tif (NULL == precv_frame)\n\t\tgoto _recv_drop;\n\n\tpattrib = &precv_frame->u.hdr.attrib;\n\tprecvpriv = &(padapter->recvpriv);\n\tpfree_recv_queue = &(precvpriv->free_recv_queue);\n\n\tskb = precv_frame->u.hdr.pkt;\n\tif (skb == NULL) {\n\t\tRTW_INFO(\"%s :skb==NULL something wrong!!!!\\n\", __func__);\n\t\tgoto _recv_drop;\n\t}\n\n\tskb->data = precv_frame->u.hdr.rx_data;\n\tskb_set_tail_pointer(skb, precv_frame->u.hdr.len);\n\tskb->len = precv_frame->u.hdr.len;\n\tskb->ip_summed = CHECKSUM_NONE;\n\tskb->pkt_type = PACKET_OTHERHOST;\n\tskb->protocol = htons(0x0019); /* ETH_P_80211_RAW */\n\n\trtw_netif_rx(padapter->pnetdev, skb);\n\n\t/* pointers to NULL before rtw_free_recvframe() */\n\tprecv_frame->u.hdr.pkt = NULL;\n\n\tret = _SUCCESS;\n\n_recv_drop:\n\n\t/* enqueue back to free_recv_queue */\n\tif (precv_frame)\n\t\trtw_free_recvframe(precv_frame, pfree_recv_queue);\n\n\treturn ret;\n\n}\n\ninline void rtw_rframe_set_os_pkt(union recv_frame *rframe)\n{\n\t_pkt *skb = rframe->u.hdr.pkt;\n\n\tskb->data = rframe->u.hdr.rx_data;\n\tskb_set_tail_pointer(skb, rframe->u.hdr.len);\n\tskb->len = rframe->u.hdr.len;\n}\n\nint rtw_recv_indicatepkt(_adapter *padapter, union recv_frame *precv_frame)\n{\n\tstruct recv_priv *precvpriv;\n\t_queue\t*pfree_recv_queue;\n\n\tprecvpriv = &(padapter->recvpriv);\n\tpfree_recv_queue = &(precvpriv->free_recv_queue);\n\n\tif (precv_frame->u.hdr.pkt == NULL)\n\t\tgoto _recv_indicatepkt_drop;\n\n\trtw_os_recv_indicate_pkt(padapter, precv_frame->u.hdr.pkt, precv_frame);\n\n\tprecv_frame->u.hdr.pkt = NULL;\n\trtw_free_recvframe(precv_frame, pfree_recv_queue);\n\treturn _SUCCESS;\n\n_recv_indicatepkt_drop:\n\trtw_free_recvframe(precv_frame, pfree_recv_queue);\n\tDBG_COUNTER(padapter->rx_logs.os_indicate_err);\n\treturn _FAIL;\n}\n\nvoid rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf)\n{\n\tstruct recv_priv *precvpriv = &padapter->recvpriv;\n\n#ifdef CONFIG_USB_HCI\n\n\tprecvbuf->ref_cnt--;\n\n\t/* free skb in recv_buf */\n\trtw_skb_free(precvbuf->pskb);\n\n\tprecvbuf->pskb = NULL;\n\n\tif (precvbuf->irp_pending == _FALSE)\n\t\trtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);\n\n\n#endif\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\tprecvbuf->pskb = NULL;\n#endif\n\n}\n\n"
  },
  {
    "path": "os_dep/linux/rhashtable.c",
    "content": "/*\r\n * Resizable, Scalable, Concurrent Hash Table\r\n *\r\n * Copyright (c) 2015 Herbert Xu <herbert@gondor.apana.org.au>\r\n * Copyright (c) 2014-2015 Thomas Graf <tgraf@suug.ch>\r\n * Copyright (c) 2008-2014 Patrick McHardy <kaber@trash.net>\r\n *\r\n * Code partially derived from nft_hash\r\n * Rewritten with rehash code from br_multicast plus single list\r\n * pointer as suggested by Josh Triplett\r\n *\r\n * This program is free software; you can redistribute it and/or modify\r\n * it under the terms of the GNU General Public License version 2 as\r\n * published by the Free Software Foundation.\r\n */\r\n\r\n#include <linux/atomic.h>\r\n#include <linux/kernel.h>\r\n#include <linux/init.h>\r\n#include <linux/log2.h>\r\n#include <linux/sched.h>\r\n#include <linux/slab.h>\r\n#include <linux/vmalloc.h>\r\n#include <linux/mm.h>\r\n#include <linux/jhash.h>\r\n#include <linux/random.h>\r\n#include <linux/err.h>\r\n#include <linux/export.h>\r\n\r\n#define HASH_DEFAULT_SIZE\t64UL\r\n#define HASH_MIN_SIZE\t\t4U\r\n#define BUCKET_LOCKS_PER_CPU   128UL\r\n\r\nstatic u32 head_hashfn(struct rhashtable *ht,\r\n\t\t       const struct bucket_table *tbl,\r\n\t\t       const struct rhash_head *he)\r\n{\r\n\treturn rht_head_hashfn(ht, tbl, he, ht->p);\r\n}\r\n\r\n#ifdef CONFIG_PROVE_LOCKING\r\n#define ASSERT_RHT_MUTEX(HT) BUG_ON(!lockdep_rht_mutex_is_held(HT))\r\n\r\nint lockdep_rht_mutex_is_held(struct rhashtable *ht)\r\n{\r\n\treturn (debug_locks) ? lockdep_is_held(&ht->mutex) : 1;\r\n}\r\n\r\nint lockdep_rht_bucket_is_held(const struct bucket_table *tbl, u32 hash)\r\n{\r\n\tspinlock_t *lock = rht_bucket_lock(tbl, hash);\r\n\r\n\treturn (debug_locks) ? lockdep_is_held(lock) : 1;\r\n}\r\n#else\r\n#define ASSERT_RHT_MUTEX(HT)\r\n#endif\r\n\r\n\r\nstatic int alloc_bucket_locks(struct rhashtable *ht, struct bucket_table *tbl,\r\n\t\t\t      gfp_t gfp)\r\n{\r\n\tunsigned int i, size;\r\n#if defined(CONFIG_PROVE_LOCKING)\r\n\tunsigned int nr_pcpus = 2;\r\n#else\r\n\tunsigned int nr_pcpus = num_possible_cpus();\r\n#endif\r\n\r\n\tnr_pcpus = min_t(unsigned int, nr_pcpus, 32UL);\r\n\tsize = roundup_pow_of_two(nr_pcpus * ht->p.locks_mul);\r\n\r\n\t/* Never allocate more than 0.5 locks per bucket */\r\n\tsize = min_t(unsigned int, size, tbl->size >> 1);\r\n\r\n\tif (sizeof(spinlock_t) != 0) {\r\n#ifdef CONFIG_NUMA\r\n\t\tif (size * sizeof(spinlock_t) > PAGE_SIZE &&\r\n\t\t    gfp == GFP_KERNEL)\r\n\t\t\ttbl->locks = vmalloc(size * sizeof(spinlock_t));\r\n\t\telse\r\n#endif\r\n\t\ttbl->locks = kmalloc_array(size, sizeof(spinlock_t),\r\n\t\t\t\t\t   gfp);\r\n\t\tif (!tbl->locks)\r\n\t\t\treturn -ENOMEM;\r\n\t\tfor (i = 0; i < size; i++)\r\n\t\t\tspin_lock_init(&tbl->locks[i]);\r\n\t}\r\n\ttbl->locks_mask = size - 1;\r\n\r\n\treturn 0;\r\n}\r\n\r\nstatic void bucket_table_free(const struct bucket_table *tbl)\r\n{\r\n\tif (tbl)\r\n\t\tkvfree(tbl->locks);\r\n\r\n\tkvfree(tbl);\r\n}\r\n\r\nstatic void bucket_table_free_rcu(struct rcu_head *head)\r\n{\r\n\tbucket_table_free(container_of(head, struct bucket_table, rcu));\r\n}\r\n\r\nstatic struct bucket_table *bucket_table_alloc(struct rhashtable *ht,\r\n\t\t\t\t\t       size_t nbuckets,\r\n\t\t\t\t\t       gfp_t gfp)\r\n{\r\n\tstruct bucket_table *tbl = NULL;\r\n\tsize_t size;\r\n\tint i;\r\n\r\n\tsize = sizeof(*tbl) + nbuckets * sizeof(tbl->buckets[0]);\r\n\tif (size <= (PAGE_SIZE << PAGE_ALLOC_COSTLY_ORDER) ||\r\n\t    gfp != GFP_KERNEL)\r\n\t\ttbl = kzalloc(size, gfp | __GFP_NOWARN | __GFP_NORETRY);\r\n\tif (tbl == NULL && gfp == GFP_KERNEL)\r\n\t\ttbl = vzalloc(size);\r\n\tif (tbl == NULL)\r\n\t\treturn NULL;\r\n\r\n\ttbl->size = nbuckets;\r\n\r\n\tif (alloc_bucket_locks(ht, tbl, gfp) < 0) {\r\n\t\tbucket_table_free(tbl);\r\n\t\treturn NULL;\r\n\t}\r\n\r\n\tINIT_LIST_HEAD(&tbl->walkers);\r\n\r\n\tget_random_bytes(&tbl->hash_rnd, sizeof(tbl->hash_rnd));\r\n\r\n\tfor (i = 0; i < nbuckets; i++)\r\n\t\tINIT_RHT_NULLS_HEAD(tbl->buckets[i], ht, i);\r\n\r\n\treturn tbl;\r\n}\r\n\r\nstatic struct bucket_table *rhashtable_last_table(struct rhashtable *ht,\r\n\t\t\t\t\t\t  struct bucket_table *tbl)\r\n{\r\n\tstruct bucket_table *new_tbl;\r\n\r\n\tdo {\r\n\t\tnew_tbl = tbl;\r\n\t\ttbl = rht_dereference_rcu(tbl->future_tbl, ht);\r\n\t} while (tbl);\r\n\r\n\treturn new_tbl;\r\n}\r\n\r\nstatic int rhashtable_rehash_one(struct rhashtable *ht, unsigned int old_hash)\r\n{\r\n\tstruct bucket_table *old_tbl = rht_dereference(ht->tbl, ht);\r\n\tstruct bucket_table *new_tbl = rhashtable_last_table(ht,\r\n\t\trht_dereference_rcu(old_tbl->future_tbl, ht));\r\n\tstruct rhash_head __rcu **pprev = &old_tbl->buckets[old_hash];\r\n\tint err = -ENOENT;\r\n\tstruct rhash_head *head, *next, *entry;\r\n\tspinlock_t *new_bucket_lock;\r\n\tunsigned int new_hash;\r\n\r\n\trht_for_each(entry, old_tbl, old_hash) {\r\n\t\terr = 0;\r\n\t\tnext = rht_dereference_bucket(entry->next, old_tbl, old_hash);\r\n\r\n\t\tif (rht_is_a_nulls(next))\r\n\t\t\tbreak;\r\n\r\n\t\tpprev = &entry->next;\r\n\t}\r\n\r\n\tif (err)\r\n\t\tgoto out;\r\n\r\n\tnew_hash = head_hashfn(ht, new_tbl, entry);\r\n\r\n\tnew_bucket_lock = rht_bucket_lock(new_tbl, new_hash);\r\n\r\n\tspin_lock_nested(new_bucket_lock, SINGLE_DEPTH_NESTING);\r\n\thead = rht_dereference_bucket(new_tbl->buckets[new_hash],\r\n\t\t\t\t      new_tbl, new_hash);\r\n\r\n\tRCU_INIT_POINTER(entry->next, head);\r\n\r\n\trcu_assign_pointer(new_tbl->buckets[new_hash], entry);\r\n\tspin_unlock(new_bucket_lock);\r\n\r\n\trcu_assign_pointer(*pprev, next);\r\n\r\nout:\r\n\treturn err;\r\n}\r\n\r\nstatic void rhashtable_rehash_chain(struct rhashtable *ht,\r\n\t\t\t\t    unsigned int old_hash)\r\n{\r\n\tstruct bucket_table *old_tbl = rht_dereference(ht->tbl, ht);\r\n\tspinlock_t *old_bucket_lock;\r\n\r\n\told_bucket_lock = rht_bucket_lock(old_tbl, old_hash);\r\n\r\n\tspin_lock_bh(old_bucket_lock);\r\n\twhile (!rhashtable_rehash_one(ht, old_hash))\r\n\t\t;\r\n\told_tbl->rehash++;\r\n\tspin_unlock_bh(old_bucket_lock);\r\n}\r\n\r\nstatic int rhashtable_rehash_attach(struct rhashtable *ht,\r\n\t\t\t\t    struct bucket_table *old_tbl,\r\n\t\t\t\t    struct bucket_table *new_tbl)\r\n{\r\n\t/* Protect future_tbl using the first bucket lock. */\r\n\tspin_lock_bh(old_tbl->locks);\r\n\r\n\t/* Did somebody beat us to it? */\r\n\tif (rcu_access_pointer(old_tbl->future_tbl)) {\r\n\t\tspin_unlock_bh(old_tbl->locks);\r\n\t\treturn -EEXIST;\r\n\t}\r\n\r\n\t/* Make insertions go into the new, empty table right away. Deletions\r\n\t * and lookups will be attempted in both tables until we synchronize.\r\n\t */\r\n\trcu_assign_pointer(old_tbl->future_tbl, new_tbl);\r\n\r\n\t/* Ensure the new table is visible to readers. */\r\n\tsmp_wmb();\r\n\r\n\tspin_unlock_bh(old_tbl->locks);\r\n\r\n\treturn 0;\r\n}\r\n\r\nstatic int rhashtable_rehash_table(struct rhashtable *ht)\r\n{\r\n\tstruct bucket_table *old_tbl = rht_dereference(ht->tbl, ht);\r\n\tstruct bucket_table *new_tbl;\r\n\tstruct rhashtable_walker *walker;\r\n\tunsigned int old_hash;\r\n\r\n\tnew_tbl = rht_dereference(old_tbl->future_tbl, ht);\r\n\tif (!new_tbl)\r\n\t\treturn 0;\r\n\r\n\tfor (old_hash = 0; old_hash < old_tbl->size; old_hash++)\r\n\t\trhashtable_rehash_chain(ht, old_hash);\r\n\r\n\t/* Publish the new table pointer. */\r\n\trcu_assign_pointer(ht->tbl, new_tbl);\r\n\r\n\tspin_lock(&ht->lock);\r\n\tlist_for_each_entry(walker, &old_tbl->walkers, list)\r\n\t\twalker->tbl = NULL;\r\n\tspin_unlock(&ht->lock);\r\n\r\n\t/* Wait for readers. All new readers will see the new\r\n\t * table, and thus no references to the old table will\r\n\t * remain.\r\n\t */\r\n\tcall_rcu(&old_tbl->rcu, bucket_table_free_rcu);\r\n\r\n\treturn rht_dereference(new_tbl->future_tbl, ht) ? -EAGAIN : 0;\r\n}\r\n\r\n/**\r\n * rhashtable_expand - Expand hash table while allowing concurrent lookups\r\n * @ht:\t\tthe hash table to expand\r\n *\r\n * A secondary bucket array is allocated and the hash entries are migrated.\r\n *\r\n * This function may only be called in a context where it is safe to call\r\n * synchronize_rcu(), e.g. not within a rcu_read_lock() section.\r\n *\r\n * The caller must ensure that no concurrent resizing occurs by holding\r\n * ht->mutex.\r\n *\r\n * It is valid to have concurrent insertions and deletions protected by per\r\n * bucket locks or concurrent RCU protected lookups and traversals.\r\n */\r\nstatic int rhashtable_expand(struct rhashtable *ht)\r\n{\r\n\tstruct bucket_table *new_tbl, *old_tbl = rht_dereference(ht->tbl, ht);\r\n\tint err;\r\n\r\n\tASSERT_RHT_MUTEX(ht);\r\n\r\n\told_tbl = rhashtable_last_table(ht, old_tbl);\r\n\r\n\tnew_tbl = bucket_table_alloc(ht, old_tbl->size * 2, GFP_KERNEL);\r\n\tif (new_tbl == NULL)\r\n\t\treturn -ENOMEM;\r\n\r\n\terr = rhashtable_rehash_attach(ht, old_tbl, new_tbl);\r\n\tif (err)\r\n\t\tbucket_table_free(new_tbl);\r\n\r\n\treturn err;\r\n}\r\n\r\n/**\r\n * rhashtable_shrink - Shrink hash table while allowing concurrent lookups\r\n * @ht:\t\tthe hash table to shrink\r\n *\r\n * This function shrinks the hash table to fit, i.e., the smallest\r\n * size would not cause it to expand right away automatically.\r\n *\r\n * The caller must ensure that no concurrent resizing occurs by holding\r\n * ht->mutex.\r\n *\r\n * The caller must ensure that no concurrent table mutations take place.\r\n * It is however valid to have concurrent lookups if they are RCU protected.\r\n *\r\n * It is valid to have concurrent insertions and deletions protected by per\r\n * bucket locks or concurrent RCU protected lookups and traversals.\r\n */\r\nstatic int rhashtable_shrink(struct rhashtable *ht)\r\n{\r\n\tstruct bucket_table *new_tbl, *old_tbl = rht_dereference(ht->tbl, ht);\r\n\tunsigned int size;\r\n\tint err;\r\n\r\n\tASSERT_RHT_MUTEX(ht);\r\n\r\n\tsize = roundup_pow_of_two(atomic_read(&ht->nelems) * 3 / 2);\r\n\tif (size < ht->p.min_size)\r\n\t\tsize = ht->p.min_size;\r\n\r\n\tif (old_tbl->size <= size)\r\n\t\treturn 0;\r\n\r\n\tif (rht_dereference(old_tbl->future_tbl, ht))\r\n\t\treturn -EEXIST;\r\n\r\n\tnew_tbl = bucket_table_alloc(ht, size, GFP_KERNEL);\r\n\tif (new_tbl == NULL)\r\n\t\treturn -ENOMEM;\r\n\r\n\terr = rhashtable_rehash_attach(ht, old_tbl, new_tbl);\r\n\tif (err)\r\n\t\tbucket_table_free(new_tbl);\r\n\r\n\treturn err;\r\n}\r\n\r\nstatic void rht_deferred_worker(struct work_struct *work)\r\n{\r\n\tstruct rhashtable *ht;\r\n\tstruct bucket_table *tbl;\r\n\tint err = 0;\r\n\r\n\tht = container_of(work, struct rhashtable, run_work);\r\n\tmutex_lock(&ht->mutex);\r\n\r\n\ttbl = rht_dereference(ht->tbl, ht);\r\n\ttbl = rhashtable_last_table(ht, tbl);\r\n\r\n\tif (rht_grow_above_75(ht, tbl))\r\n\t\trhashtable_expand(ht);\r\n\telse if (ht->p.automatic_shrinking && rht_shrink_below_30(ht, tbl))\r\n\t\trhashtable_shrink(ht);\r\n\r\n\terr = rhashtable_rehash_table(ht);\r\n\r\n\tmutex_unlock(&ht->mutex);\r\n\r\n\tif (err)\r\n\t\tschedule_work(&ht->run_work);\r\n}\r\n\r\nstatic bool rhashtable_check_elasticity(struct rhashtable *ht,\r\n\t\t\t\t\tstruct bucket_table *tbl,\r\n\t\t\t\t\tunsigned int hash)\r\n{\r\n\tunsigned int elasticity = ht->elasticity;\r\n\tstruct rhash_head *head;\r\n\r\n\trht_for_each(head, tbl, hash)\r\n\t\tif (!--elasticity)\r\n\t\t\treturn true;\r\n\r\n\treturn false;\r\n}\r\n\r\nint rhashtable_insert_rehash(struct rhashtable *ht,\r\n\t\t\t     struct bucket_table *tbl)\r\n{\r\n\tstruct bucket_table *old_tbl;\r\n\tstruct bucket_table *new_tbl;\r\n\tunsigned int size;\r\n\tint err;\r\n\r\n\told_tbl = rht_dereference_rcu(ht->tbl, ht);\r\n\r\n\tsize = tbl->size;\r\n\r\n\terr = -EBUSY;\r\n\r\n\tif (rht_grow_above_75(ht, tbl))\r\n\t\tsize *= 2;\r\n\t/* Do not schedule more than one rehash */\r\n\telse if (old_tbl != tbl)\r\n\t\tgoto fail;\r\n\r\n\terr = -ENOMEM;\r\n\r\n\tnew_tbl = bucket_table_alloc(ht, size, GFP_ATOMIC);\r\n\tif (new_tbl == NULL)\r\n\t\tgoto fail;\r\n\r\n\terr = rhashtable_rehash_attach(ht, tbl, new_tbl);\r\n\tif (err) {\r\n\t\tbucket_table_free(new_tbl);\r\n\t\tif (err == -EEXIST)\r\n\t\t\terr = 0;\r\n\t} else\r\n\t\tschedule_work(&ht->run_work);\r\n\r\n\treturn err;\r\n\r\nfail:\r\n\t/* Do not fail the insert if someone else did a rehash. */\r\n\tif (likely(rcu_dereference_raw(tbl->future_tbl)))\r\n\t\treturn 0;\r\n\r\n\t/* Schedule async rehash to retry allocation in process context. */\r\n\tif (err == -ENOMEM)\r\n\t\tschedule_work(&ht->run_work);\r\n\r\n\treturn err;\r\n}\r\n\r\nstruct bucket_table *rhashtable_insert_slow(struct rhashtable *ht,\r\n\t\t\t\t\t    const void *key,\r\n\t\t\t\t\t    struct rhash_head *obj,\r\n\t\t\t\t\t    struct bucket_table *tbl)\r\n{\r\n\tstruct rhash_head *head;\r\n\tunsigned int hash;\r\n\tint err;\r\n\r\n\ttbl = rhashtable_last_table(ht, tbl);\r\n\thash = head_hashfn(ht, tbl, obj);\r\n\tspin_lock_nested(rht_bucket_lock(tbl, hash), SINGLE_DEPTH_NESTING);\r\n\r\n\terr = -EEXIST;\r\n\tif (key && rhashtable_lookup_fast(ht, key, ht->p))\r\n\t\tgoto exit;\r\n\r\n\terr = -E2BIG;\r\n\tif (unlikely(rht_grow_above_max(ht, tbl)))\r\n\t\tgoto exit;\r\n\r\n\terr = -EAGAIN;\r\n\tif (rhashtable_check_elasticity(ht, tbl, hash) ||\r\n\t    rht_grow_above_100(ht, tbl))\r\n\t\tgoto exit;\r\n\r\n\terr = 0;\r\n\r\n\thead = rht_dereference_bucket(tbl->buckets[hash], tbl, hash);\r\n\r\n\tRCU_INIT_POINTER(obj->next, head);\r\n\r\n\trcu_assign_pointer(tbl->buckets[hash], obj);\r\n\r\n\tatomic_inc(&ht->nelems);\r\n\r\nexit:\r\n\tspin_unlock(rht_bucket_lock(tbl, hash));\r\n\r\n\tif (err == 0)\r\n\t\treturn NULL;\r\n\telse if (err == -EAGAIN)\r\n\t\treturn tbl;\r\n\telse\r\n\t\treturn ERR_PTR(err);\r\n}\r\n\r\n/**\r\n * rhashtable_walk_init - Initialise an iterator\r\n * @ht:\t\tTable to walk over\r\n * @iter:\tHash table Iterator\r\n *\r\n * This function prepares a hash table walk.\r\n *\r\n * Note that if you restart a walk after rhashtable_walk_stop you\r\n * may see the same object twice.  Also, you may miss objects if\r\n * there are removals in between rhashtable_walk_stop and the next\r\n * call to rhashtable_walk_start.\r\n *\r\n * For a completely stable walk you should construct your own data\r\n * structure outside the hash table.\r\n *\r\n * This function may sleep so you must not call it from interrupt\r\n * context or with spin locks held.\r\n *\r\n * You must call rhashtable_walk_exit if this function returns\r\n * successfully.\r\n */\r\nint rhashtable_walk_init(struct rhashtable *ht, struct rhashtable_iter *iter)\r\n{\r\n\titer->ht = ht;\r\n\titer->p = NULL;\r\n\titer->slot = 0;\r\n\titer->skip = 0;\r\n\r\n\titer->walker = kmalloc(sizeof(*iter->walker), GFP_KERNEL);\r\n\tif (!iter->walker)\r\n\t\treturn -ENOMEM;\r\n\r\n\tspin_lock(&ht->lock);\r\n\titer->walker->tbl =\r\n\t\trcu_dereference_protected(ht->tbl, lockdep_is_held(&ht->lock));\r\n\tlist_add(&iter->walker->list, &iter->walker->tbl->walkers);\r\n\tspin_unlock(&ht->lock);\r\n\r\n\treturn 0;\r\n}\r\n\r\n/**\r\n * rhashtable_walk_exit - Free an iterator\r\n * @iter:\tHash table Iterator\r\n *\r\n * This function frees resources allocated by rhashtable_walk_init.\r\n */\r\nvoid rhashtable_walk_exit(struct rhashtable_iter *iter)\r\n{\r\n\tspin_lock(&iter->ht->lock);\r\n\tif (iter->walker->tbl)\r\n\t\tlist_del(&iter->walker->list);\r\n\tspin_unlock(&iter->ht->lock);\r\n\tkfree(iter->walker);\r\n}\r\n\r\n/**\r\n * rhashtable_walk_start - Start a hash table walk\r\n * @iter:\tHash table iterator\r\n *\r\n * Start a hash table walk.  Note that we take the RCU lock in all\r\n * cases including when we return an error.  So you must always call\r\n * rhashtable_walk_stop to clean up.\r\n *\r\n * Returns zero if successful.\r\n *\r\n * Returns -EAGAIN if resize event occured.  Note that the iterator\r\n * will rewind back to the beginning and you may use it immediately\r\n * by calling rhashtable_walk_next.\r\n */\r\nint rhashtable_walk_start(struct rhashtable_iter *iter)\r\n\t__acquires(RCU)\r\n{\r\n\tstruct rhashtable *ht = iter->ht;\r\n\r\n\trcu_read_lock();\r\n\r\n\tspin_lock(&ht->lock);\r\n\tif (iter->walker->tbl)\r\n\t\tlist_del(&iter->walker->list);\r\n\tspin_unlock(&ht->lock);\r\n\r\n\tif (!iter->walker->tbl) {\r\n\t\titer->walker->tbl = rht_dereference_rcu(ht->tbl, ht);\r\n\t\treturn -EAGAIN;\r\n\t}\r\n\r\n\treturn 0;\r\n}\r\n\r\n/**\r\n * rhashtable_walk_next - Return the next object and advance the iterator\r\n * @iter:\tHash table iterator\r\n *\r\n * Note that you must call rhashtable_walk_stop when you are finished\r\n * with the walk.\r\n *\r\n * Returns the next object or NULL when the end of the table is reached.\r\n *\r\n * Returns -EAGAIN if resize event occured.  Note that the iterator\r\n * will rewind back to the beginning and you may continue to use it.\r\n */\r\nvoid *rhashtable_walk_next(struct rhashtable_iter *iter)\r\n{\r\n\tstruct bucket_table *tbl = iter->walker->tbl;\r\n\tstruct rhashtable *ht = iter->ht;\r\n\tstruct rhash_head *p = iter->p;\r\n\r\n\tif (p) {\r\n\t\tp = rht_dereference_bucket_rcu(p->next, tbl, iter->slot);\r\n\t\tgoto next;\r\n\t}\r\n\r\n\tfor (; iter->slot < tbl->size; iter->slot++) {\r\n\t\tint skip = iter->skip;\r\n\r\n\t\trht_for_each_rcu(p, tbl, iter->slot) {\r\n\t\t\tif (!skip)\r\n\t\t\t\tbreak;\r\n\t\t\tskip--;\r\n\t\t}\r\n\r\nnext:\r\n\t\tif (!rht_is_a_nulls(p)) {\r\n\t\t\titer->skip++;\r\n\t\t\titer->p = p;\r\n\t\t\treturn rht_obj(ht, p);\r\n\t\t}\r\n\r\n\t\titer->skip = 0;\r\n\t}\r\n\r\n\titer->p = NULL;\r\n\r\n\t/* Ensure we see any new tables. */\r\n\tsmp_rmb();\r\n\r\n\titer->walker->tbl = rht_dereference_rcu(tbl->future_tbl, ht);\r\n\tif (iter->walker->tbl) {\r\n\t\titer->slot = 0;\r\n\t\titer->skip = 0;\r\n\t\treturn ERR_PTR(-EAGAIN);\r\n\t}\r\n\r\n\treturn NULL;\r\n}\r\n\r\n/**\r\n * rhashtable_walk_stop - Finish a hash table walk\r\n * @iter:\tHash table iterator\r\n *\r\n * Finish a hash table walk.\r\n */\r\nvoid rhashtable_walk_stop(struct rhashtable_iter *iter)\r\n\t__releases(RCU)\r\n{\r\n\tstruct rhashtable *ht;\r\n\tstruct bucket_table *tbl = iter->walker->tbl;\r\n\r\n\tif (!tbl)\r\n\t\tgoto out;\r\n\r\n\tht = iter->ht;\r\n\r\n\tspin_lock(&ht->lock);\r\n\tif (tbl->rehash < tbl->size)\r\n\t\tlist_add(&iter->walker->list, &tbl->walkers);\r\n\telse\r\n\t\titer->walker->tbl = NULL;\r\n\tspin_unlock(&ht->lock);\r\n\r\n\titer->p = NULL;\r\n\r\nout:\r\n\trcu_read_unlock();\r\n}\r\n\r\nstatic size_t rounded_hashtable_size(const struct rhashtable_params *params)\r\n{\r\n\treturn max(roundup_pow_of_two(params->nelem_hint * 4 / 3),\r\n\t\t   (unsigned long)params->min_size);\r\n}\r\n\r\nstatic u32 rhashtable_jhash2(const void *key, u32 length, u32 seed)\r\n{\r\n\treturn jhash2(key, length, seed);\r\n}\r\n\r\n/**\r\n * rhashtable_init - initialize a new hash table\r\n * @ht:\t\thash table to be initialized\r\n * @params:\tconfiguration parameters\r\n *\r\n * Initializes a new hash table based on the provided configuration\r\n * parameters. A table can be configured either with a variable or\r\n * fixed length key:\r\n *\r\n * Configuration Example 1: Fixed length keys\r\n * struct test_obj {\r\n *\tint\t\t\tkey;\r\n *\tvoid *\t\t\tmy_member;\r\n *\tstruct rhash_head\tnode;\r\n * };\r\n *\r\n * struct rhashtable_params params = {\r\n *\t.head_offset = offsetof(struct test_obj, node),\r\n *\t.key_offset = offsetof(struct test_obj, key),\r\n *\t.key_len = sizeof(int),\r\n *\t.hashfn = jhash,\r\n *\t.nulls_base = (1U << RHT_BASE_SHIFT),\r\n * };\r\n *\r\n * Configuration Example 2: Variable length keys\r\n * struct test_obj {\r\n *\t[...]\r\n *\tstruct rhash_head\tnode;\r\n * };\r\n *\r\n * u32 my_hash_fn(const void *data, u32 len, u32 seed)\r\n * {\r\n *\tstruct test_obj *obj = data;\r\n *\r\n *\treturn [... hash ...];\r\n * }\r\n *\r\n * struct rhashtable_params params = {\r\n *\t.head_offset = offsetof(struct test_obj, node),\r\n *\t.hashfn = jhash,\r\n *\t.obj_hashfn = my_hash_fn,\r\n * };\r\n */\r\nint rhashtable_init(struct rhashtable *ht,\r\n\t\t    const struct rhashtable_params *params)\r\n{\r\n\tstruct bucket_table *tbl;\r\n\tsize_t size;\r\n\r\n\tsize = HASH_DEFAULT_SIZE;\r\n\r\n\tif ((!params->key_len && !params->obj_hashfn) ||\r\n\t    (params->obj_hashfn && !params->obj_cmpfn))\r\n\t\treturn -EINVAL;\r\n\r\n\tif (params->nulls_base && params->nulls_base < (1U << RHT_BASE_SHIFT))\r\n\t\treturn -EINVAL;\r\n\r\n\tmemset(ht, 0, sizeof(*ht));\r\n\tmutex_init(&ht->mutex);\r\n\tspin_lock_init(&ht->lock);\r\n\tmemcpy(&ht->p, params, sizeof(*params));\r\n\r\n\tif (params->min_size)\r\n\t\tht->p.min_size = roundup_pow_of_two(params->min_size);\r\n\r\n\tif (params->max_size)\r\n\t\tht->p.max_size = rounddown_pow_of_two(params->max_size);\r\n\r\n\tif (params->insecure_max_entries)\r\n\t\tht->p.insecure_max_entries =\r\n\t\t\trounddown_pow_of_two(params->insecure_max_entries);\r\n\telse\r\n\t\tht->p.insecure_max_entries = ht->p.max_size * 2;\r\n\r\n\tht->p.min_size = max(ht->p.min_size, HASH_MIN_SIZE);\r\n\r\n\tif (params->nelem_hint)\r\n\t\tsize = rounded_hashtable_size(&ht->p);\r\n\r\n\t/* The maximum (not average) chain length grows with the\r\n\t * size of the hash table, at a rate of (log N)/(log log N).\r\n\t * The value of 16 is selected so that even if the hash\r\n\t * table grew to 2^32 you would not expect the maximum\r\n\t * chain length to exceed it unless we are under attack\r\n\t * (or extremely unlucky).\r\n\t *\r\n\t * As this limit is only to detect attacks, we don't need\r\n\t * to set it to a lower value as you'd need the chain\r\n\t * length to vastly exceed 16 to have any real effect\r\n\t * on the system.\r\n\t */\r\n\tif (!params->insecure_elasticity)\r\n\t\tht->elasticity = 16;\r\n\r\n\tif (params->locks_mul)\r\n\t\tht->p.locks_mul = roundup_pow_of_two(params->locks_mul);\r\n\telse\r\n\t\tht->p.locks_mul = BUCKET_LOCKS_PER_CPU;\r\n\r\n\tht->key_len = ht->p.key_len;\r\n\tif (!params->hashfn) {\r\n\t\tht->p.hashfn = jhash;\r\n\r\n\t\tif (!(ht->key_len & (sizeof(u32) - 1))) {\r\n\t\t\tht->key_len /= sizeof(u32);\r\n\t\t\tht->p.hashfn = rhashtable_jhash2;\r\n\t\t}\r\n\t}\r\n\r\n\ttbl = bucket_table_alloc(ht, size, GFP_KERNEL);\r\n\tif (tbl == NULL)\r\n\t\treturn -ENOMEM;\r\n\r\n\tatomic_set(&ht->nelems, 0);\r\n\r\n\tRCU_INIT_POINTER(ht->tbl, tbl);\r\n\r\n\tINIT_WORK(&ht->run_work, rht_deferred_worker);\r\n\r\n\treturn 0;\r\n}\r\n\r\n/**\r\n * rhashtable_free_and_destroy - free elements and destroy hash table\r\n * @ht:\t\tthe hash table to destroy\r\n * @free_fn:\tcallback to release resources of element\r\n * @arg:\tpointer passed to free_fn\r\n *\r\n * Stops an eventual async resize. If defined, invokes free_fn for each\r\n * element to releasal resources. Please note that RCU protected\r\n * readers may still be accessing the elements. Releasing of resources\r\n * must occur in a compatible manner. Then frees the bucket array.\r\n *\r\n * This function will eventually sleep to wait for an async resize\r\n * to complete. The caller is responsible that no further write operations\r\n * occurs in parallel.\r\n */\r\nvoid rhashtable_free_and_destroy(struct rhashtable *ht,\r\n\t\t\t\t void (*free_fn)(void *ptr, void *arg),\r\n\t\t\t\t void *arg)\r\n{\r\n\tconst struct bucket_table *tbl;\r\n\tunsigned int i;\r\n\r\n\tcancel_work_sync(&ht->run_work);\r\n\r\n\tmutex_lock(&ht->mutex);\r\n\ttbl = rht_dereference(ht->tbl, ht);\r\n\tif (free_fn) {\r\n\t\tfor (i = 0; i < tbl->size; i++) {\r\n\t\t\tstruct rhash_head *pos, *next;\r\n\r\n\t\t\tfor (pos = rht_dereference(tbl->buckets[i], ht),\r\n\t\t\t     next = !rht_is_a_nulls(pos) ?\r\n\t\t\t\t\trht_dereference(pos->next, ht) : NULL;\r\n\t\t\t     !rht_is_a_nulls(pos);\r\n\t\t\t     pos = next,\r\n\t\t\t     next = !rht_is_a_nulls(pos) ?\r\n\t\t\t\t\trht_dereference(pos->next, ht) : NULL)\r\n\t\t\t\tfree_fn(rht_obj(ht, pos), arg);\r\n\t\t}\r\n\t}\r\n\r\n\tbucket_table_free(tbl);\r\n\tmutex_unlock(&ht->mutex);\r\n}\r\n\r\nvoid rhashtable_destroy(struct rhashtable *ht)\r\n{\r\n\treturn rhashtable_free_and_destroy(ht, NULL, NULL);\r\n}\r\n\r\n"
  },
  {
    "path": "os_dep/linux/rhashtable.h",
    "content": "/*\r\n * Resizable, Scalable, Concurrent Hash Table\r\n *\r\n * Copyright (c) 2015 Herbert Xu <herbert@gondor.apana.org.au>\r\n * Copyright (c) 2014-2015 Thomas Graf <tgraf@suug.ch>\r\n * Copyright (c) 2008-2014 Patrick McHardy <kaber@trash.net>\r\n *\r\n * Code partially derived from nft_hash\r\n * Rewritten with rehash code from br_multicast plus single list\r\n * pointer as suggested by Josh Triplett\r\n *\r\n * This program is free software; you can redistribute it and/or modify\r\n * it under the terms of the GNU General Public License version 2 as\r\n * published by the Free Software Foundation.\r\n */\r\n\r\n#ifndef _LINUX_RHASHTABLE_H\r\n#define _LINUX_RHASHTABLE_H\r\n\r\n#include <linux/atomic.h>\r\n#include <linux/compiler.h>\r\n#include <linux/err.h>\r\n#include <linux/errno.h>\r\n#include <linux/jhash.h>\r\n#include <linux/list_nulls.h>\r\n#include <linux/workqueue.h>\r\n#include <linux/mutex.h>\r\n#include <linux/rcupdate.h>\r\n\r\n/*\r\n * The end of the chain is marked with a special nulls marks which has\r\n * the following format:\r\n *\r\n * +-------+-----------------------------------------------------+-+\r\n * | Base  |                      Hash                           |1|\r\n * +-------+-----------------------------------------------------+-+\r\n *\r\n * Base (4 bits) : Reserved to distinguish between multiple tables.\r\n *                 Specified via &struct rhashtable_params.nulls_base.\r\n * Hash (27 bits): Full hash (unmasked) of first element added to bucket\r\n * 1 (1 bit)     : Nulls marker (always set)\r\n *\r\n * The remaining bits of the next pointer remain unused for now.\r\n */\r\n#define RHT_BASE_BITS\t\t4\r\n#define RHT_HASH_BITS\t\t27\r\n#define RHT_BASE_SHIFT\t\tRHT_HASH_BITS\r\n\r\n/* Base bits plus 1 bit for nulls marker */\r\n#define RHT_HASH_RESERVED_SPACE\t(RHT_BASE_BITS + 1)\r\n\r\nstruct rhash_head {\r\n\tstruct rhash_head __rcu\t\t*next;\r\n};\r\n\r\n/**\r\n * struct bucket_table - Table of hash buckets\r\n * @size: Number of hash buckets\r\n * @rehash: Current bucket being rehashed\r\n * @hash_rnd: Random seed to fold into hash\r\n * @locks_mask: Mask to apply before accessing locks[]\r\n * @locks: Array of spinlocks protecting individual buckets\r\n * @walkers: List of active walkers\r\n * @rcu: RCU structure for freeing the table\r\n * @future_tbl: Table under construction during rehashing\r\n * @buckets: size * hash buckets\r\n */\r\nstruct bucket_table {\r\n\tunsigned int\t\tsize;\r\n\tunsigned int\t\trehash;\r\n\tu32\t\t\thash_rnd;\r\n\tunsigned int\t\tlocks_mask;\r\n\tspinlock_t\t\t*locks;\r\n\tstruct list_head\twalkers;\r\n\tstruct rcu_head\t\trcu;\r\n\r\n\tstruct bucket_table __rcu *future_tbl;\r\n\r\n\tstruct rhash_head __rcu\t*buckets[] ____cacheline_aligned_in_smp;\r\n};\r\n\r\n/**\r\n * struct rhashtable_compare_arg - Key for the function rhashtable_compare\r\n * @ht: Hash table\r\n * @key: Key to compare against\r\n */\r\nstruct rhashtable_compare_arg {\r\n\tstruct rhashtable *ht;\r\n\tconst void *key;\r\n};\r\n\r\ntypedef u32 (*rht_hashfn_t)(const void *data, u32 len, u32 seed);\r\ntypedef u32 (*rht_obj_hashfn_t)(const void *data, u32 len, u32 seed);\r\ntypedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *arg,\r\n\t\t\t       const void *obj);\r\n\r\nstruct rhashtable;\r\n\r\n/**\r\n * struct rhashtable_params - Hash table construction parameters\r\n * @nelem_hint: Hint on number of elements, should be 75% of desired size\r\n * @key_len: Length of key\r\n * @key_offset: Offset of key in struct to be hashed\r\n * @head_offset: Offset of rhash_head in struct to be hashed\r\n * @insecure_max_entries: Maximum number of entries (may be exceeded)\r\n * @max_size: Maximum size while expanding\r\n * @min_size: Minimum size while shrinking\r\n * @nulls_base: Base value to generate nulls marker\r\n * @insecure_elasticity: Set to true to disable chain length checks\r\n * @automatic_shrinking: Enable automatic shrinking of tables\r\n * @locks_mul: Number of bucket locks to allocate per cpu (default: 128)\r\n * @hashfn: Hash function (default: jhash2 if !(key_len % 4), or jhash)\r\n * @obj_hashfn: Function to hash object\r\n * @obj_cmpfn: Function to compare key with object\r\n */\r\nstruct rhashtable_params {\r\n\tsize_t\t\t\tnelem_hint;\r\n\tsize_t\t\t\tkey_len;\r\n\tsize_t\t\t\tkey_offset;\r\n\tsize_t\t\t\thead_offset;\r\n\tunsigned int\t\tinsecure_max_entries;\r\n\tunsigned int\t\tmax_size;\r\n\tunsigned int\t\tmin_size;\r\n\tu32\t\t\tnulls_base;\r\n\tbool\t\t\tinsecure_elasticity;\r\n\tbool\t\t\tautomatic_shrinking;\r\n\tsize_t\t\t\tlocks_mul;\r\n\trht_hashfn_t\t\thashfn;\r\n\trht_obj_hashfn_t\tobj_hashfn;\r\n\trht_obj_cmpfn_t\t\tobj_cmpfn;\r\n};\r\n\r\n/**\r\n * struct rhashtable - Hash table handle\r\n * @tbl: Bucket table\r\n * @nelems: Number of elements in table\r\n * @key_len: Key length for hashfn\r\n * @elasticity: Maximum chain length before rehash\r\n * @p: Configuration parameters\r\n * @run_work: Deferred worker to expand/shrink asynchronously\r\n * @mutex: Mutex to protect current/future table swapping\r\n * @lock: Spin lock to protect walker list\r\n */\r\nstruct rhashtable {\r\n\tstruct bucket_table __rcu\t*tbl;\r\n\tatomic_t\t\t\tnelems;\r\n\tunsigned int\t\t\tkey_len;\r\n\tunsigned int\t\t\telasticity;\r\n\tstruct rhashtable_params\tp;\r\n\tstruct work_struct\t\trun_work;\r\n\tstruct mutex                    mutex;\r\n\tspinlock_t\t\t\tlock;\r\n};\r\n\r\n/**\r\n * struct rhashtable_walker - Hash table walker\r\n * @list: List entry on list of walkers\r\n * @tbl: The table that we were walking over\r\n */\r\nstruct rhashtable_walker {\r\n\tstruct list_head list;\r\n\tstruct bucket_table *tbl;\r\n};\r\n\r\n/**\r\n * struct rhashtable_iter - Hash table iterator, fits into netlink cb\r\n * @ht: Table to iterate through\r\n * @p: Current pointer\r\n * @walker: Associated rhashtable walker\r\n * @slot: Current slot\r\n * @skip: Number of entries to skip in slot\r\n */\r\nstruct rhashtable_iter {\r\n\tstruct rhashtable *ht;\r\n\tstruct rhash_head *p;\r\n\tstruct rhashtable_walker *walker;\r\n\tunsigned int slot;\r\n\tunsigned int skip;\r\n};\r\n\r\nstatic inline unsigned long rht_marker(const struct rhashtable *ht, u32 hash)\r\n{\r\n\treturn NULLS_MARKER(ht->p.nulls_base + hash);\r\n}\r\n\r\n#define INIT_RHT_NULLS_HEAD(ptr, ht, hash) \\\r\n\t((ptr) = (typeof(ptr)) rht_marker(ht, hash))\r\n\r\nstatic inline bool rht_is_a_nulls(const struct rhash_head *ptr)\r\n{\r\n\treturn ((unsigned long) ptr & 1);\r\n}\r\n\r\nstatic inline unsigned long rht_get_nulls_value(const struct rhash_head *ptr)\r\n{\r\n\treturn ((unsigned long) ptr) >> 1;\r\n}\r\n\r\nstatic inline void *rht_obj(const struct rhashtable *ht,\r\n\t\t\t    const struct rhash_head *he)\r\n{\r\n\treturn (char *)he - ht->p.head_offset;\r\n}\r\n\r\nstatic inline unsigned int rht_bucket_index(const struct bucket_table *tbl,\r\n\t\t\t\t\t    unsigned int hash)\r\n{\r\n\treturn (hash >> RHT_HASH_RESERVED_SPACE) & (tbl->size - 1);\r\n}\r\n\r\nstatic inline unsigned int rht_key_hashfn(\r\n\tstruct rhashtable *ht, const struct bucket_table *tbl,\r\n\tconst void *key, const struct rhashtable_params params)\r\n{\r\n\tunsigned int hash;\r\n\r\n\t/* params must be equal to ht->p if it isn't constant. */\r\n\tif (!__builtin_constant_p(params.key_len))\r\n\t\thash = ht->p.hashfn(key, ht->key_len, tbl->hash_rnd);\r\n\telse if (params.key_len) {\r\n\t\tunsigned int key_len = params.key_len;\r\n\r\n\t\tif (params.hashfn)\r\n\t\t\thash = params.hashfn(key, key_len, tbl->hash_rnd);\r\n\t\telse if (key_len & (sizeof(u32) - 1))\r\n\t\t\thash = jhash(key, key_len, tbl->hash_rnd);\r\n\t\telse\r\n\t\t\thash = jhash2(key, key_len / sizeof(u32),\r\n\t\t\t\t      tbl->hash_rnd);\r\n\t} else {\r\n\t\tunsigned int key_len = ht->p.key_len;\r\n\r\n\t\tif (params.hashfn)\r\n\t\t\thash = params.hashfn(key, key_len, tbl->hash_rnd);\r\n\t\telse\r\n\t\t\thash = jhash(key, key_len, tbl->hash_rnd);\r\n\t}\r\n\r\n\treturn rht_bucket_index(tbl, hash);\r\n}\r\n\r\nstatic inline unsigned int rht_head_hashfn(\r\n\tstruct rhashtable *ht, const struct bucket_table *tbl,\r\n\tconst struct rhash_head *he, const struct rhashtable_params params)\r\n{\r\n\tconst char *ptr = rht_obj(ht, he);\r\n\r\n\treturn likely(params.obj_hashfn) ?\r\n\t       rht_bucket_index(tbl, params.obj_hashfn(ptr, params.key_len ?:\r\n\t\t\t\t\t\t\t    ht->p.key_len,\r\n\t\t\t\t\t\t       tbl->hash_rnd)) :\r\n\t       rht_key_hashfn(ht, tbl, ptr + params.key_offset, params);\r\n}\r\n\r\n/**\r\n * rht_grow_above_75 - returns true if nelems > 0.75 * table-size\r\n * @ht:\t\thash table\r\n * @tbl:\tcurrent table\r\n */\r\nstatic inline bool rht_grow_above_75(const struct rhashtable *ht,\r\n\t\t\t\t     const struct bucket_table *tbl)\r\n{\r\n\t/* Expand table when exceeding 75% load */\r\n\treturn atomic_read(&ht->nelems) > (tbl->size / 4 * 3) &&\r\n\t       (!ht->p.max_size || tbl->size < ht->p.max_size);\r\n}\r\n\r\n/**\r\n * rht_shrink_below_30 - returns true if nelems < 0.3 * table-size\r\n * @ht:\t\thash table\r\n * @tbl:\tcurrent table\r\n */\r\nstatic inline bool rht_shrink_below_30(const struct rhashtable *ht,\r\n\t\t\t\t       const struct bucket_table *tbl)\r\n{\r\n\t/* Shrink table beneath 30% load */\r\n\treturn atomic_read(&ht->nelems) < (tbl->size * 3 / 10) &&\r\n\t       tbl->size > ht->p.min_size;\r\n}\r\n\r\n/**\r\n * rht_grow_above_100 - returns true if nelems > table-size\r\n * @ht:\t\thash table\r\n * @tbl:\tcurrent table\r\n */\r\nstatic inline bool rht_grow_above_100(const struct rhashtable *ht,\r\n\t\t\t\t      const struct bucket_table *tbl)\r\n{\r\n\treturn atomic_read(&ht->nelems) > tbl->size &&\r\n\t\t(!ht->p.max_size || tbl->size < ht->p.max_size);\r\n}\r\n\r\n/**\r\n * rht_grow_above_max - returns true if table is above maximum\r\n * @ht:\t\thash table\r\n * @tbl:\tcurrent table\r\n */\r\nstatic inline bool rht_grow_above_max(const struct rhashtable *ht,\r\n\t\t\t\t      const struct bucket_table *tbl)\r\n{\r\n\treturn ht->p.insecure_max_entries &&\r\n\t       atomic_read(&ht->nelems) >= ht->p.insecure_max_entries;\r\n}\r\n\r\n/* The bucket lock is selected based on the hash and protects mutations\r\n * on a group of hash buckets.\r\n *\r\n * A maximum of tbl->size/2 bucket locks is allocated. This ensures that\r\n * a single lock always covers both buckets which may both contains\r\n * entries which link to the same bucket of the old table during resizing.\r\n * This allows to simplify the locking as locking the bucket in both\r\n * tables during resize always guarantee protection.\r\n *\r\n * IMPORTANT: When holding the bucket lock of both the old and new table\r\n * during expansions and shrinking, the old bucket lock must always be\r\n * acquired first.\r\n */\r\nstatic inline spinlock_t *rht_bucket_lock(const struct bucket_table *tbl,\r\n\t\t\t\t\t  unsigned int hash)\r\n{\r\n\treturn &tbl->locks[hash & tbl->locks_mask];\r\n}\r\n\r\n#ifdef CONFIG_PROVE_LOCKING\r\nint lockdep_rht_mutex_is_held(struct rhashtable *ht);\r\nint lockdep_rht_bucket_is_held(const struct bucket_table *tbl, u32 hash);\r\n#else\r\nstatic inline int lockdep_rht_mutex_is_held(struct rhashtable *ht)\r\n{\r\n\treturn 1;\r\n}\r\n\r\nstatic inline int lockdep_rht_bucket_is_held(const struct bucket_table *tbl,\r\n\t\t\t\t\t     u32 hash)\r\n{\r\n\treturn 1;\r\n}\r\n#endif /* CONFIG_PROVE_LOCKING */\r\n\r\nint rhashtable_init(struct rhashtable *ht,\r\n\t\t    const struct rhashtable_params *params);\r\n\r\nstruct bucket_table *rhashtable_insert_slow(struct rhashtable *ht,\r\n\t\t\t\t\t    const void *key,\r\n\t\t\t\t\t    struct rhash_head *obj,\r\n\t\t\t\t\t    struct bucket_table *old_tbl);\r\nint rhashtable_insert_rehash(struct rhashtable *ht, struct bucket_table *tbl);\r\n\r\nint rhashtable_walk_init(struct rhashtable *ht, struct rhashtable_iter *iter);\r\nvoid rhashtable_walk_exit(struct rhashtable_iter *iter);\r\nint rhashtable_walk_start(struct rhashtable_iter *iter) __acquires(RCU);\r\nvoid *rhashtable_walk_next(struct rhashtable_iter *iter);\r\nvoid rhashtable_walk_stop(struct rhashtable_iter *iter) __releases(RCU);\r\n\r\nvoid rhashtable_free_and_destroy(struct rhashtable *ht,\r\n\t\t\t\t void (*free_fn)(void *ptr, void *arg),\r\n\t\t\t\t void *arg);\r\nvoid rhashtable_destroy(struct rhashtable *ht);\r\n\r\n#define rht_dereference(p, ht) \\\r\n\trcu_dereference_protected(p, lockdep_rht_mutex_is_held(ht))\r\n\r\n#define rht_dereference_rcu(p, ht) \\\r\n\trcu_dereference_check(p, lockdep_rht_mutex_is_held(ht))\r\n\r\n#define rht_dereference_bucket(p, tbl, hash) \\\r\n\trcu_dereference_protected(p, lockdep_rht_bucket_is_held(tbl, hash))\r\n\r\n#define rht_dereference_bucket_rcu(p, tbl, hash) \\\r\n\trcu_dereference_check(p, lockdep_rht_bucket_is_held(tbl, hash))\r\n\r\n#define rht_entry(tpos, pos, member) \\\r\n\t({ tpos = container_of(pos, typeof(*tpos), member); 1; })\r\n\r\n/**\r\n * rht_for_each_continue - continue iterating over hash chain\r\n * @pos:\tthe &struct rhash_head to use as a loop cursor.\r\n * @head:\tthe previous &struct rhash_head to continue from\r\n * @tbl:\tthe &struct bucket_table\r\n * @hash:\tthe hash value / bucket index\r\n */\r\n#define rht_for_each_continue(pos, head, tbl, hash) \\\r\n\tfor (pos = rht_dereference_bucket(head, tbl, hash); \\\r\n\t     !rht_is_a_nulls(pos); \\\r\n\t     pos = rht_dereference_bucket((pos)->next, tbl, hash))\r\n\r\n/**\r\n * rht_for_each - iterate over hash chain\r\n * @pos:\tthe &struct rhash_head to use as a loop cursor.\r\n * @tbl:\tthe &struct bucket_table\r\n * @hash:\tthe hash value / bucket index\r\n */\r\n#define rht_for_each(pos, tbl, hash) \\\r\n\trht_for_each_continue(pos, (tbl)->buckets[hash], tbl, hash)\r\n\r\n/**\r\n * rht_for_each_entry_continue - continue iterating over hash chain\r\n * @tpos:\tthe type * to use as a loop cursor.\r\n * @pos:\tthe &struct rhash_head to use as a loop cursor.\r\n * @head:\tthe previous &struct rhash_head to continue from\r\n * @tbl:\tthe &struct bucket_table\r\n * @hash:\tthe hash value / bucket index\r\n * @member:\tname of the &struct rhash_head within the hashable struct.\r\n */\r\n#define rht_for_each_entry_continue(tpos, pos, head, tbl, hash, member)\t\\\r\n\tfor (pos = rht_dereference_bucket(head, tbl, hash);\t\t\\\r\n\t     (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member);\t\\\r\n\t     pos = rht_dereference_bucket((pos)->next, tbl, hash))\r\n\r\n/**\r\n * rht_for_each_entry - iterate over hash chain of given type\r\n * @tpos:\tthe type * to use as a loop cursor.\r\n * @pos:\tthe &struct rhash_head to use as a loop cursor.\r\n * @tbl:\tthe &struct bucket_table\r\n * @hash:\tthe hash value / bucket index\r\n * @member:\tname of the &struct rhash_head within the hashable struct.\r\n */\r\n#define rht_for_each_entry(tpos, pos, tbl, hash, member)\t\t\\\r\n\trht_for_each_entry_continue(tpos, pos, (tbl)->buckets[hash],\t\\\r\n\t\t\t\t    tbl, hash, member)\r\n\r\n/**\r\n * rht_for_each_entry_safe - safely iterate over hash chain of given type\r\n * @tpos:\tthe type * to use as a loop cursor.\r\n * @pos:\tthe &struct rhash_head to use as a loop cursor.\r\n * @next:\tthe &struct rhash_head to use as next in loop cursor.\r\n * @tbl:\tthe &struct bucket_table\r\n * @hash:\tthe hash value / bucket index\r\n * @member:\tname of the &struct rhash_head within the hashable struct.\r\n *\r\n * This hash chain list-traversal primitive allows for the looped code to\r\n * remove the loop cursor from the list.\r\n */\r\n#define rht_for_each_entry_safe(tpos, pos, next, tbl, hash, member)\t    \\\r\n\tfor (pos = rht_dereference_bucket((tbl)->buckets[hash], tbl, hash), \\\r\n\t     next = !rht_is_a_nulls(pos) ?\t\t\t\t    \\\r\n\t\t       rht_dereference_bucket(pos->next, tbl, hash) : NULL; \\\r\n\t     (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member);\t    \\\r\n\t     pos = next,\t\t\t\t\t\t    \\\r\n\t     next = !rht_is_a_nulls(pos) ?\t\t\t\t    \\\r\n\t\t       rht_dereference_bucket(pos->next, tbl, hash) : NULL)\r\n\r\n/**\r\n * rht_for_each_rcu_continue - continue iterating over rcu hash chain\r\n * @pos:\tthe &struct rhash_head to use as a loop cursor.\r\n * @head:\tthe previous &struct rhash_head to continue from\r\n * @tbl:\tthe &struct bucket_table\r\n * @hash:\tthe hash value / bucket index\r\n *\r\n * This hash chain list-traversal primitive may safely run concurrently with\r\n * the _rcu mutation primitives such as rhashtable_insert() as long as the\r\n * traversal is guarded by rcu_read_lock().\r\n */\r\n#define rht_for_each_rcu_continue(pos, head, tbl, hash)\t\t\t\\\r\n\tfor (({barrier(); }),\t\t\t\t\t\t\\\r\n\t     pos = rht_dereference_bucket_rcu(head, tbl, hash);\t\t\\\r\n\t     !rht_is_a_nulls(pos);\t\t\t\t\t\\\r\n\t     pos = rcu_dereference_raw(pos->next))\r\n\r\n/**\r\n * rht_for_each_rcu - iterate over rcu hash chain\r\n * @pos:\tthe &struct rhash_head to use as a loop cursor.\r\n * @tbl:\tthe &struct bucket_table\r\n * @hash:\tthe hash value / bucket index\r\n *\r\n * This hash chain list-traversal primitive may safely run concurrently with\r\n * the _rcu mutation primitives such as rhashtable_insert() as long as the\r\n * traversal is guarded by rcu_read_lock().\r\n */\r\n#define rht_for_each_rcu(pos, tbl, hash)\t\t\t\t\\\r\n\trht_for_each_rcu_continue(pos, (tbl)->buckets[hash], tbl, hash)\r\n\r\n/**\r\n * rht_for_each_entry_rcu_continue - continue iterating over rcu hash chain\r\n * @tpos:\tthe type * to use as a loop cursor.\r\n * @pos:\tthe &struct rhash_head to use as a loop cursor.\r\n * @head:\tthe previous &struct rhash_head to continue from\r\n * @tbl:\tthe &struct bucket_table\r\n * @hash:\tthe hash value / bucket index\r\n * @member:\tname of the &struct rhash_head within the hashable struct.\r\n *\r\n * This hash chain list-traversal primitive may safely run concurrently with\r\n * the _rcu mutation primitives such as rhashtable_insert() as long as the\r\n * traversal is guarded by rcu_read_lock().\r\n */\r\n#define rht_for_each_entry_rcu_continue(tpos, pos, head, tbl, hash, member) \\\r\n\tfor (({barrier(); }),\t\t\t\t\t\t    \\\r\n\t     pos = rht_dereference_bucket_rcu(head, tbl, hash);\t\t    \\\r\n\t     (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member);\t    \\\r\n\t     pos = rht_dereference_bucket_rcu(pos->next, tbl, hash))\r\n\r\n/**\r\n * rht_for_each_entry_rcu - iterate over rcu hash chain of given type\r\n * @tpos:\tthe type * to use as a loop cursor.\r\n * @pos:\tthe &struct rhash_head to use as a loop cursor.\r\n * @tbl:\tthe &struct bucket_table\r\n * @hash:\tthe hash value / bucket index\r\n * @member:\tname of the &struct rhash_head within the hashable struct.\r\n *\r\n * This hash chain list-traversal primitive may safely run concurrently with\r\n * the _rcu mutation primitives such as rhashtable_insert() as long as the\r\n * traversal is guarded by rcu_read_lock().\r\n */\r\n#define rht_for_each_entry_rcu(tpos, pos, tbl, hash, member)\t\t\\\r\n\trht_for_each_entry_rcu_continue(tpos, pos, (tbl)->buckets[hash],\\\r\n\t\t\t\t\ttbl, hash, member)\r\n\r\nstatic inline int rhashtable_compare(struct rhashtable_compare_arg *arg,\r\n\t\t\t\t     const void *obj)\r\n{\r\n\tstruct rhashtable *ht = arg->ht;\r\n\tconst char *ptr = obj;\r\n\r\n\treturn memcmp(ptr + ht->p.key_offset, arg->key, ht->p.key_len);\r\n}\r\n\r\n/**\r\n * rhashtable_lookup_fast - search hash table, inlined version\r\n * @ht:\t\thash table\r\n * @key:\tthe pointer to the key\r\n * @params:\thash table parameters\r\n *\r\n * Computes the hash value for the key and traverses the bucket chain looking\r\n * for a entry with an identical key. The first matching entry is returned.\r\n *\r\n * Returns the first entry on which the compare function returned true.\r\n */\r\nstatic inline void *rhashtable_lookup_fast(\r\n\tstruct rhashtable *ht, const void *key,\r\n\tconst struct rhashtable_params params)\r\n{\r\n\tstruct rhashtable_compare_arg arg = {\r\n\t\t.ht = ht,\r\n\t\t.key = key,\r\n\t};\r\n\tconst struct bucket_table *tbl;\r\n\tstruct rhash_head *he;\r\n\tunsigned int hash;\r\n\r\n\trcu_read_lock();\r\n\r\n\ttbl = rht_dereference_rcu(ht->tbl, ht);\r\nrestart:\r\n\thash = rht_key_hashfn(ht, tbl, key, params);\r\n\trht_for_each_rcu(he, tbl, hash) {\r\n\t\tif (params.obj_cmpfn ?\r\n\t\t    params.obj_cmpfn(&arg, rht_obj(ht, he)) :\r\n\t\t    rhashtable_compare(&arg, rht_obj(ht, he)))\r\n\t\t\tcontinue;\r\n\t\trcu_read_unlock();\r\n\t\treturn rht_obj(ht, he);\r\n\t}\r\n\r\n\t/* Ensure we see any new tables. */\r\n\tsmp_rmb();\r\n\r\n\ttbl = rht_dereference_rcu(tbl->future_tbl, ht);\r\n\tif (unlikely(tbl))\r\n\t\tgoto restart;\r\n\trcu_read_unlock();\r\n\r\n\treturn NULL;\r\n}\r\n\r\n/* Internal function, please use rhashtable_insert_fast() instead */\r\nstatic inline int __rhashtable_insert_fast(\r\n\tstruct rhashtable *ht, const void *key, struct rhash_head *obj,\r\n\tconst struct rhashtable_params params)\r\n{\r\n\tstruct rhashtable_compare_arg arg = {\r\n\t\t.ht = ht,\r\n\t\t.key = key,\r\n\t};\r\n\tstruct bucket_table *tbl, *new_tbl;\r\n\tstruct rhash_head *head;\r\n\tspinlock_t *lock;\r\n\tunsigned int elasticity;\r\n\tunsigned int hash;\r\n\tint err;\r\n\r\nrestart:\r\n\trcu_read_lock();\r\n\r\n\ttbl = rht_dereference_rcu(ht->tbl, ht);\r\n\r\n\t/* All insertions must grab the oldest table containing\r\n\t * the hashed bucket that is yet to be rehashed.\r\n\t */\r\n\tfor (;;) {\r\n\t\thash = rht_head_hashfn(ht, tbl, obj, params);\r\n\t\tlock = rht_bucket_lock(tbl, hash);\r\n\t\tspin_lock_bh(lock);\r\n\r\n\t\tif (tbl->rehash <= hash)\r\n\t\t\tbreak;\r\n\r\n\t\tspin_unlock_bh(lock);\r\n\t\ttbl = rht_dereference_rcu(tbl->future_tbl, ht);\r\n\t}\r\n\r\n\tnew_tbl = rht_dereference_rcu(tbl->future_tbl, ht);\r\n\tif (unlikely(new_tbl)) {\r\n\t\ttbl = rhashtable_insert_slow(ht, key, obj, new_tbl);\r\n\t\tif (!IS_ERR_OR_NULL(tbl))\r\n\t\t\tgoto slow_path;\r\n\r\n\t\terr = PTR_ERR(tbl);\r\n\t\tgoto out;\r\n\t}\r\n\r\n\terr = -E2BIG;\r\n\tif (unlikely(rht_grow_above_max(ht, tbl)))\r\n\t\tgoto out;\r\n\r\n\tif (unlikely(rht_grow_above_100(ht, tbl))) {\r\nslow_path:\r\n\t\tspin_unlock_bh(lock);\r\n\t\terr = rhashtable_insert_rehash(ht, tbl);\r\n\t\trcu_read_unlock();\r\n\t\tif (err)\r\n\t\t\treturn err;\r\n\r\n\t\tgoto restart;\r\n\t}\r\n\r\n\terr = -EEXIST;\r\n\telasticity = ht->elasticity;\r\n\trht_for_each(head, tbl, hash) {\r\n\t\tif (key &&\r\n\t\t    unlikely(!(params.obj_cmpfn ?\r\n\t\t\t       params.obj_cmpfn(&arg, rht_obj(ht, head)) :\r\n\t\t\t       rhashtable_compare(&arg, rht_obj(ht, head)))))\r\n\t\t\tgoto out;\r\n\t\tif (!--elasticity)\r\n\t\t\tgoto slow_path;\r\n\t}\r\n\r\n\terr = 0;\r\n\r\n\thead = rht_dereference_bucket(tbl->buckets[hash], tbl, hash);\r\n\r\n\tRCU_INIT_POINTER(obj->next, head);\r\n\r\n\trcu_assign_pointer(tbl->buckets[hash], obj);\r\n\r\n\tatomic_inc(&ht->nelems);\r\n\tif (rht_grow_above_75(ht, tbl))\r\n\t\tschedule_work(&ht->run_work);\r\n\r\nout:\r\n\tspin_unlock_bh(lock);\r\n\trcu_read_unlock();\r\n\r\n\treturn err;\r\n}\r\n\r\n/**\r\n * rhashtable_insert_fast - insert object into hash table\r\n * @ht:\t\thash table\r\n * @obj:\tpointer to hash head inside object\r\n * @params:\thash table parameters\r\n *\r\n * Will take a per bucket spinlock to protect against mutual mutations\r\n * on the same bucket. Multiple insertions may occur in parallel unless\r\n * they map to the same bucket lock.\r\n *\r\n * It is safe to call this function from atomic context.\r\n *\r\n * Will trigger an automatic deferred table resizing if the size grows\r\n * beyond the watermark indicated by grow_decision() which can be passed\r\n * to rhashtable_init().\r\n */\r\nstatic inline int rhashtable_insert_fast(\r\n\tstruct rhashtable *ht, struct rhash_head *obj,\r\n\tconst struct rhashtable_params params)\r\n{\r\n\treturn __rhashtable_insert_fast(ht, NULL, obj, params);\r\n}\r\n\r\n/**\r\n * rhashtable_lookup_insert_fast - lookup and insert object into hash table\r\n * @ht:\t\thash table\r\n * @obj:\tpointer to hash head inside object\r\n * @params:\thash table parameters\r\n *\r\n * Locks down the bucket chain in both the old and new table if a resize\r\n * is in progress to ensure that writers can't remove from the old table\r\n * and can't insert to the new table during the atomic operation of search\r\n * and insertion. Searches for duplicates in both the old and new table if\r\n * a resize is in progress.\r\n *\r\n * This lookup function may only be used for fixed key hash table (key_len\r\n * parameter set). It will BUG() if used inappropriately.\r\n *\r\n * It is safe to call this function from atomic context.\r\n *\r\n * Will trigger an automatic deferred table resizing if the size grows\r\n * beyond the watermark indicated by grow_decision() which can be passed\r\n * to rhashtable_init().\r\n */\r\nstatic inline int rhashtable_lookup_insert_fast(\r\n\tstruct rhashtable *ht, struct rhash_head *obj,\r\n\tconst struct rhashtable_params params)\r\n{\r\n\tconst char *key = rht_obj(ht, obj);\r\n\r\n\tBUG_ON(ht->p.obj_hashfn);\r\n\r\n\treturn __rhashtable_insert_fast(ht, key + ht->p.key_offset, obj,\r\n\t\t\t\t\tparams);\r\n}\r\n\r\n/**\r\n * rhashtable_lookup_insert_key - search and insert object to hash table\r\n *\t\t\t\t  with explicit key\r\n * @ht:\t\thash table\r\n * @key:\tkey\r\n * @obj:\tpointer to hash head inside object\r\n * @params:\thash table parameters\r\n *\r\n * Locks down the bucket chain in both the old and new table if a resize\r\n * is in progress to ensure that writers can't remove from the old table\r\n * and can't insert to the new table during the atomic operation of search\r\n * and insertion. Searches for duplicates in both the old and new table if\r\n * a resize is in progress.\r\n *\r\n * Lookups may occur in parallel with hashtable mutations and resizing.\r\n *\r\n * Will trigger an automatic deferred table resizing if the size grows\r\n * beyond the watermark indicated by grow_decision() which can be passed\r\n * to rhashtable_init().\r\n *\r\n * Returns zero on success.\r\n */\r\nstatic inline int rhashtable_lookup_insert_key(\r\n\tstruct rhashtable *ht, const void *key, struct rhash_head *obj,\r\n\tconst struct rhashtable_params params)\r\n{\r\n\tBUG_ON(!ht->p.obj_hashfn || !key);\r\n\r\n\treturn __rhashtable_insert_fast(ht, key, obj, params);\r\n}\r\n\r\n/* Internal function, please use rhashtable_remove_fast() instead */\r\nstatic inline int __rhashtable_remove_fast(\r\n\tstruct rhashtable *ht, struct bucket_table *tbl,\r\n\tstruct rhash_head *obj, const struct rhashtable_params params)\r\n{\r\n\tstruct rhash_head __rcu **pprev;\r\n\tstruct rhash_head *he;\r\n\tspinlock_t * lock;\r\n\tunsigned int hash;\r\n\tint err = -ENOENT;\r\n\r\n\thash = rht_head_hashfn(ht, tbl, obj, params);\r\n\tlock = rht_bucket_lock(tbl, hash);\r\n\r\n\tspin_lock_bh(lock);\r\n\r\n\tpprev = &tbl->buckets[hash];\r\n\trht_for_each(he, tbl, hash) {\r\n\t\tif (he != obj) {\r\n\t\t\tpprev = &he->next;\r\n\t\t\tcontinue;\r\n\t\t}\r\n\r\n\t\trcu_assign_pointer(*pprev, obj->next);\r\n\t\terr = 0;\r\n\t\tbreak;\r\n\t}\r\n\r\n\tspin_unlock_bh(lock);\r\n\r\n\treturn err;\r\n}\r\n\r\n/**\r\n * rhashtable_remove_fast - remove object from hash table\r\n * @ht:\t\thash table\r\n * @obj:\tpointer to hash head inside object\r\n * @params:\thash table parameters\r\n *\r\n * Since the hash chain is single linked, the removal operation needs to\r\n * walk the bucket chain upon removal. The removal operation is thus\r\n * considerable slow if the hash table is not correctly sized.\r\n *\r\n * Will automatically shrink the table via rhashtable_expand() if the\r\n * shrink_decision function specified at rhashtable_init() returns true.\r\n *\r\n * Returns zero on success, -ENOENT if the entry could not be found.\r\n */\r\nstatic inline int rhashtable_remove_fast(\r\n\tstruct rhashtable *ht, struct rhash_head *obj,\r\n\tconst struct rhashtable_params params)\r\n{\r\n\tstruct bucket_table *tbl;\r\n\tint err;\r\n\r\n\trcu_read_lock();\r\n\r\n\ttbl = rht_dereference_rcu(ht->tbl, ht);\r\n\r\n\t/* Because we have already taken (and released) the bucket\r\n\t * lock in old_tbl, if we find that future_tbl is not yet\r\n\t * visible then that guarantees the entry to still be in\r\n\t * the old tbl if it exists.\r\n\t */\r\n\twhile ((err = __rhashtable_remove_fast(ht, tbl, obj, params)) &&\r\n\t       (tbl = rht_dereference_rcu(tbl->future_tbl, ht)))\r\n\t\t;\r\n\r\n\tif (err)\r\n\t\tgoto out;\r\n\r\n\tatomic_dec(&ht->nelems);\r\n\tif (unlikely(ht->p.automatic_shrinking &&\r\n\t\t     rht_shrink_below_30(ht, tbl)))\r\n\t\tschedule_work(&ht->run_work);\r\n\r\nout:\r\n\trcu_read_unlock();\r\n\r\n\treturn err;\r\n}\r\n\r\n#endif /* _LINUX_RHASHTABLE_H */\r\n\r\n"
  },
  {
    "path": "os_dep/linux/rtw_android.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifdef CONFIG_GPIO_WAKEUP\n#include <linux/gpio.h>\n#endif\n\n#include <drv_types.h>\n\n#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC)\n#include <linux/platform_device.h>\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\t#include <linux/wlan_plat.h>\n#else\n\t#include <linux/wifi_tiwlan.h>\n#endif\n#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))\n#define strnicmp\tstrncasecmp\n#endif /* Linux kernel >= 4.0.0 */\n\n#ifdef CONFIG_GPIO_WAKEUP\n#include <linux/interrupt.h>\n#include <linux/irq.h>\n#endif\n\n#include \"rtw_version.h\"\n\nextern void macstr2num(u8 *dst, u8 *src);\n\nconst char *android_wifi_cmd_str[ANDROID_WIFI_CMD_MAX] = {\n\t\"START\",\n\t\"STOP\",\n\t\"SCAN-ACTIVE\",\n\t\"SCAN-PASSIVE\",\n\t\"RSSI\",\n\t\"LINKSPEED\",\n\t\"RXFILTER-START\",\n\t\"RXFILTER-STOP\",\n\t\"RXFILTER-ADD\",\n\t\"RXFILTER-REMOVE\",\n\t\"BTCOEXSCAN-START\",\n\t\"BTCOEXSCAN-STOP\",\n\t\"BTCOEXMODE\",\n\t\"SETSUSPENDMODE\",\n\t\"SETSUSPENDOPT\",\n\t\"P2P_DEV_ADDR\",\n\t\"SETFWPATH\",\n\t\"SETBAND\",\n\t\"GETBAND\",\n\t\"COUNTRY\",\n\t\"P2P_SET_NOA\",\n\t\"P2P_GET_NOA\",\n\t\"P2P_SET_PS\",\n\t\"SET_AP_WPS_P2P_IE\",\n\n\t\"MIRACAST\",\n\n#ifdef CONFIG_PNO_SUPPORT\n\t\"PNOSSIDCLR\",\n\t\"PNOSETUP\",\n\t\"PNOFORCE\",\n\t\"PNODEBUG\",\n#endif\n\n\t\"MACADDR\",\n\n\t\"BLOCK_SCAN\",\n\t\"BLOCK\",\n\t\"WFD-ENABLE\",\n\t\"WFD-DISABLE\",\n\t\"WFD-SET-TCPPORT\",\n\t\"WFD-SET-MAXTPUT\",\n\t\"WFD-SET-DEVTYPE\",\n\t\"SET_DTIM\",\n\t\"HOSTAPD_SET_MACADDR_ACL\",\n\t\"HOSTAPD_ACL_ADD_STA\",\n\t\"HOSTAPD_ACL_REMOVE_STA\",\n#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))\n\t\"GTK_REKEY_OFFLOAD\",\n#endif /* CONFIG_GTK_OL */\n/*\tPrivate command for\tP2P disable*/\n\t\"P2P_DISABLE\",\n\t\"SET_AEK\",\n\t\"EXT_AUTH_STATUS\",\n\t\"DRIVER_VERSION\"\n};\n\n#ifdef CONFIG_PNO_SUPPORT\n#define PNO_TLV_PREFIX\t\t\t'S'\n#define PNO_TLV_VERSION\t\t\t'1'\n#define PNO_TLV_SUBVERSION\t\t'2'\n#define PNO_TLV_RESERVED\t\t'0'\n#define PNO_TLV_TYPE_SSID_IE\t'S'\n#define PNO_TLV_TYPE_TIME\t\t'T'\n#define PNO_TLV_FREQ_REPEAT\t\t'R'\n#define PNO_TLV_FREQ_EXPO_MAX\t'M'\n\ntypedef struct cmd_tlv {\n\tchar prefix;\n\tchar version;\n\tchar subver;\n\tchar reserved;\n} cmd_tlv_t;\n\n#ifdef CONFIG_PNO_SET_DEBUG\nchar pno_in_example[] = {\n\t'P', 'N', 'O', 'S', 'E', 'T', 'U', 'P', ' ',\n\t'S', '1', '2', '0',\n\t'S',\t/* 1 */\n\t0x05,\n\t'd', 'l', 'i', 'n', 'k',\n\t'S',\t/* 2 */\n\t0x06,\n\t'B', 'U', 'F', 'B', 'U', 'F',\n\t'S',\t/* 3 */\n\t0x20,\n\t'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', '!', '@', '#', '$', '%', '^',\n\t'S',\t/* 4 */\n\t0x0a,\n\t'!', '@', '#', '$', '%', '^', '&', '*', '(', ')',\n\t'T',\n\t'0', '5',\n\t'R',\n\t'2',\n\t'M',\n\t'2',\n\t0x00\n};\n#endif /* CONFIG_PNO_SET_DEBUG */\n#endif /* PNO_SUPPORT */\n\ntypedef struct android_wifi_priv_cmd {\n\tchar *buf;\n\tint used_len;\n\tint total_len;\n} android_wifi_priv_cmd;\n\n#ifdef CONFIG_COMPAT\ntypedef struct compat_android_wifi_priv_cmd {\n\tcompat_uptr_t buf;\n\tint used_len;\n\tint total_len;\n} compat_android_wifi_priv_cmd;\n#endif /* CONFIG_COMPAT */\n\n/**\n * Local (static) functions and variables\n */\n\n/* Initialize g_wifi_on to 1 so dhd_bus_start will be called for the first\n * time (only) in dhd_open, subsequential wifi on will be handled by\n * wl_android_wifi_on\n */\nstatic int g_wifi_on = _TRUE;\n\nunsigned int oob_irq = 0;\nunsigned int oob_gpio = 0;\n\n#ifdef CONFIG_PNO_SUPPORT\n/*\n * rtw_android_pno_setup\n * Description:\n * This is used for private command.\n *\n * Parameter:\n * net: net_device\n * command: parameters from private command\n * total_len: the length of the command.\n *\n * */\nstatic int rtw_android_pno_setup(struct net_device *net, char *command, int total_len)\n{\n\tpno_ssid_t pno_ssids_local[MAX_PNO_LIST_COUNT];\n\tint res = -1;\n\tint nssid = 0;\n\tcmd_tlv_t *cmd_tlv_temp;\n\tchar *str_ptr;\n\tint tlv_size_left;\n\tint pno_time = 0;\n\tint pno_repeat = 0;\n\tint pno_freq_expo_max = 0;\n\tint cmdlen = strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_PNOSETUP_SET]) + 1;\n\n#ifdef CONFIG_PNO_SET_DEBUG\n\tint i;\n\tchar *p;\n\tp = pno_in_example;\n\n\ttotal_len = sizeof(pno_in_example);\n\tstr_ptr = p + cmdlen;\n#else\n\tstr_ptr = command + cmdlen;\n#endif\n\n\tif (total_len < (cmdlen + sizeof(cmd_tlv_t))) {\n\t\tRTW_INFO(\"%s argument=%d less min size\\n\", __func__, total_len);\n\t\tgoto exit_proc;\n\t}\n\n\ttlv_size_left = total_len - cmdlen;\n\n\tcmd_tlv_temp = (cmd_tlv_t *)str_ptr;\n\tmemset(pno_ssids_local, 0, sizeof(pno_ssids_local));\n\n\tif ((cmd_tlv_temp->prefix == PNO_TLV_PREFIX) &&\n\t    (cmd_tlv_temp->version == PNO_TLV_VERSION) &&\n\t    (cmd_tlv_temp->subver == PNO_TLV_SUBVERSION)) {\n\n\t\tstr_ptr += sizeof(cmd_tlv_t);\n\t\ttlv_size_left -= sizeof(cmd_tlv_t);\n\n\t\tnssid = rtw_parse_ssid_list_tlv(&str_ptr, pno_ssids_local,\n\t\t\t     MAX_PNO_LIST_COUNT, &tlv_size_left);\n\t\tif (nssid <= 0) {\n\t\t\tRTW_INFO(\"SSID is not presented or corrupted ret=%d\\n\", nssid);\n\t\t\tgoto exit_proc;\n\t\t} else {\n\t\t\tif ((str_ptr[0] != PNO_TLV_TYPE_TIME) || (tlv_size_left <= 1)) {\n\t\t\t\tRTW_INFO(\"%s scan duration corrupted field size %d\\n\",\n\t\t\t\t\t __func__, tlv_size_left);\n\t\t\t\tgoto exit_proc;\n\t\t\t}\n\t\t\tstr_ptr++;\n\t\t\tpno_time = simple_strtoul(str_ptr, &str_ptr, 16);\n\t\t\tRTW_INFO(\"%s: pno_time=%d\\n\", __func__, pno_time);\n\n\t\t\tif (str_ptr[0] != 0) {\n\t\t\t\tif ((str_ptr[0] != PNO_TLV_FREQ_REPEAT)) {\n\t\t\t\t\tRTW_INFO(\"%s pno repeat : corrupted field\\n\",\n\t\t\t\t\t\t __func__);\n\t\t\t\t\tgoto exit_proc;\n\t\t\t\t}\n\t\t\t\tstr_ptr++;\n\t\t\t\tpno_repeat = simple_strtoul(str_ptr, &str_ptr, 16);\n\t\t\t\tRTW_INFO(\"%s :got pno_repeat=%d\\n\", __FUNCTION__, pno_repeat);\n\t\t\t\tif (str_ptr[0] != PNO_TLV_FREQ_EXPO_MAX) {\n\t\t\t\t\tRTW_INFO(\"%s FREQ_EXPO_MAX corrupted field size\\n\",\n\t\t\t\t\t\t __func__);\n\t\t\t\t\tgoto exit_proc;\n\t\t\t\t}\n\t\t\t\tstr_ptr++;\n\t\t\t\tpno_freq_expo_max = simple_strtoul(str_ptr, &str_ptr, 16);\n\t\t\t\tRTW_INFO(\"%s: pno_freq_expo_max=%d\\n\",\n\t\t\t\t\t __func__, pno_freq_expo_max);\n\t\t\t}\n\t\t}\n\t} else {\n\t\tRTW_INFO(\"%s get wrong TLV command\\n\", __FUNCTION__);\n\t\tgoto exit_proc;\n\t}\n\n\tres = rtw_dev_pno_set(net, pno_ssids_local, nssid, pno_time, pno_repeat, pno_freq_expo_max);\n\n#ifdef CONFIG_PNO_SET_DEBUG\n\trtw_dev_pno_debug(net);\n#endif\n\nexit_proc:\n\treturn res;\n}\n\n/*\n * rtw_android_cfg80211_pno_setup\n * Description:\n * This is used for cfg80211 sched_scan.\n *\n * Parameter:\n * net: net_device\n * request: cfg80211_request\n * */\n\nint rtw_android_cfg80211_pno_setup(struct net_device *net,\n\t\t   struct cfg80211_ssid *ssids, int n_ssids, int interval)\n{\n\tint res = -1;\n\tint nssid = 0;\n\tint pno_time = 0;\n\tint pno_repeat = 0;\n\tint pno_freq_expo_max = 0;\n\tint index = 0;\n\tpno_ssid_t pno_ssids_local[MAX_PNO_LIST_COUNT];\n\n\tif (n_ssids > MAX_PNO_LIST_COUNT || n_ssids < 0) {\n\t\tRTW_INFO(\"%s: nssids(%d) is invalid.\\n\", __func__, n_ssids);\n\t\treturn -EINVAL;\n\t}\n\n\tmemset(pno_ssids_local, 0, sizeof(pno_ssids_local));\n\n\tnssid = n_ssids;\n\n\tfor (index = 0 ; index < nssid ; index++) {\n\t\tpno_ssids_local[index].SSID_len = ssids[index].ssid_len;\n\t\tmemcpy(pno_ssids_local[index].SSID, ssids[index].ssid,\n\t\t       ssids[index].ssid_len);\n\t}\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)\n\tif(ssids)\n\t\trtw_mfree((u8 *)ssids, (n_ssids * sizeof(struct cfg80211_ssid)));\n#endif\n\tpno_time = (interval / 1000);\n\n\tRTW_INFO(\"%s: nssids: %d, pno_time=%d\\n\", __func__, nssid, pno_time);\n\n\tres = rtw_dev_pno_set(net, pno_ssids_local, nssid, pno_time,\n\t\t\t      pno_repeat, pno_freq_expo_max);\n\n#ifdef CONFIG_PNO_SET_DEBUG\n\trtw_dev_pno_debug(net);\n#endif\nexit_proc:\n\treturn res;\n}\n\nint rtw_android_pno_enable(struct net_device *net, int pno_enable)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(net);\n\tstruct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);\n\n\tif (pwrctl) {\n\t\tpwrctl->wowlan_pno_enable = pno_enable;\n\t\tRTW_INFO(\"%s: wowlan_pno_enable: %d\\n\", __func__, pwrctl->wowlan_pno_enable);\n\t\tif (pwrctl->wowlan_pno_enable == 0) {\n\t\t\tif (pwrctl->pnlo_info != NULL) {\n\t\t\t\trtw_mfree((u8 *)pwrctl->pnlo_info, sizeof(pno_nlo_info_t));\n\t\t\t\tpwrctl->pnlo_info = NULL;\n\t\t\t}\n\t\t\tif (pwrctl->pno_ssid_list != NULL) {\n\t\t\t\trtw_mfree((u8 *)pwrctl->pno_ssid_list, sizeof(pno_ssid_list_t));\n\t\t\t\tpwrctl->pno_ssid_list = NULL;\n\t\t\t}\n\t\t\tif (pwrctl->pscan_info != NULL) {\n\t\t\t\trtw_mfree((u8 *)pwrctl->pscan_info, sizeof(pno_scan_info_t));\n\t\t\t\tpwrctl->pscan_info = NULL;\n\t\t\t}\n\t\t}\n\t\treturn 0;\n\t} else\n\t\treturn -1;\n}\n#endif /* CONFIG_PNO_SUPPORT */\n\nint rtw_android_cmdstr_to_num(char *cmdstr)\n{\n\tint cmd_num;\n\tfor (cmd_num = 0 ; cmd_num < ANDROID_WIFI_CMD_MAX; cmd_num++)\n\t\tif (0 == strnicmp(cmdstr , android_wifi_cmd_str[cmd_num], strlen(android_wifi_cmd_str[cmd_num])))\n\t\t\tbreak;\n\n\treturn cmd_num;\n}\n\nint rtw_android_get_rssi(struct net_device *net, char *command, int total_len)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(net);\n\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tstruct\twlan_network\t*pcur_network = &pmlmepriv->cur_network;\n\tint bytes_written = 0;\n\n\tif (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {\n\t\tbytes_written += snprintf(&command[bytes_written], total_len, \"%s rssi %d\",\n\t\t\tpcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi);\n\t}\n\n\treturn bytes_written;\n}\n\nint rtw_android_get_link_speed(struct net_device *net, char *command, int total_len)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(net);\n\tint bytes_written = 0;\n\tu16 link_speed = 0;\n\n\tlink_speed = rtw_get_cur_max_rate(padapter) / 10;\n\tbytes_written = snprintf(command, total_len, \"LinkSpeed %d\", link_speed);\n\n\treturn bytes_written;\n}\n\nint rtw_android_get_macaddr(struct net_device *net, char *command, int total_len)\n{\n\tint bytes_written = 0;\n\n\tbytes_written = snprintf(command, total_len, \"Macaddr = \"MAC_FMT, MAC_ARG(net->dev_addr));\n\treturn bytes_written;\n}\n\nint rtw_android_set_country(struct net_device *net, char *command, int total_len)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(net);\n\tchar *country_code = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_COUNTRY]) + 1;\n\tint ret = _FAIL;\n\n\tret = rtw_set_country(adapter, country_code);\n\n\treturn (ret == _SUCCESS) ? 0 : -1;\n}\n\nint rtw_android_get_p2p_dev_addr(struct net_device *net, char *command, int total_len)\n{\n\tint bytes_written = 0;\n\n\t/* We use the same address as our HW MAC address */\n\t_rtw_memcpy(command, net->dev_addr, ETH_ALEN);\n\n\tbytes_written = ETH_ALEN;\n\treturn bytes_written;\n}\n\nint rtw_android_set_block_scan(struct net_device *net, char *command, int total_len)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(net);\n\tchar *block_value = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_BLOCK_SCAN]) + 1;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tadapter_wdev_data(adapter)->block_scan = (*block_value == '0') ? _FALSE : _TRUE;\n#endif\n\n\treturn 0;\n}\n\nint rtw_android_set_block(struct net_device *net, char *command, int total_len)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(net);\n\tchar *block_value = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_BLOCK]) + 1;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tadapter_wdev_data(adapter)->block = (*block_value == '0') ? _FALSE : _TRUE;\n#endif\n\n\treturn 0;\n}\n\nint rtw_android_setband(struct net_device *net, char *command, int total_len)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(net);\n\tchar *arg = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SETBAND]) + 1;\n\tu32 band = WIFI_FREQUENCY_BAND_AUTO;\n\tint ret = _FAIL;\n\n\tif (sscanf(arg, \"%u\", &band) >= 1)\n\t\tret = rtw_set_band(adapter, band);\n\n\treturn (ret == _SUCCESS) ? 0 : -1;\n}\n\nint rtw_android_getband(struct net_device *net, char *command, int total_len)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(net);\n\tint bytes_written = 0;\n\n\tbytes_written = snprintf(command, total_len, \"%u\", adapter->setband);\n\n\treturn bytes_written;\n}\n\n#ifdef CONFIG_WFD\nint rtw_android_set_miracast_mode(struct net_device *net, char *command, int total_len)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(net);\n\tstruct wifi_display_info *wfd_info = &adapter->wfd_info;\n\tchar *arg = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_MIRACAST]) + 1;\n\tu8 mode;\n\tint num;\n\tint ret = _FAIL;\n\n\tnum = sscanf(arg, \"%hhu\", &mode);\n\n\tif (num < 1)\n\t\tgoto exit;\n\n\tswitch (mode) {\n\tcase 1: /* soruce */\n\t\tmode = MIRACAST_SOURCE;\n\t\tbreak;\n\tcase 2: /* sink */\n\t\tmode = MIRACAST_SINK;\n\t\tbreak;\n\tcase 0: /* disabled */\n\tdefault:\n\t\tmode = MIRACAST_DISABLED;\n\t\tbreak;\n\t}\n\twfd_info->stack_wfd_mode = mode;\n\tRTW_INFO(\"stack miracast mode: %s\\n\", get_miracast_mode_str(wfd_info->stack_wfd_mode));\n\n\tret = _SUCCESS;\n\nexit:\n\treturn (ret == _SUCCESS) ? 0 : -1;\n}\n#endif /* CONFIG_WFD */\n\nint get_int_from_command(char *pcmd)\n{\n\tint i = 0;\n\n\tfor (i = 0; i < strlen(pcmd); i++) {\n\t\tif (pcmd[i] == '=') {\n\t\t\t/*\tSkip the '=' and space characters. */\n\t\t\ti += 2;\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn rtw_atoi(pcmd + i) ;\n}\n\n#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))\nint rtw_gtk_offload(struct net_device *net, u8 *cmd_ptr)\n{\n\tint i;\n\t/* u8 *cmd_ptr = priv_cmd.buf; */\n\tstruct sta_info *psta;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(net);\n\tstruct mlme_priv\t*pmlmepriv = &padapter->mlmepriv;\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tstruct security_priv *psecuritypriv = &(padapter->securitypriv);\n\tpsta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));\n\n\n\tif (psta == NULL)\n\t\tRTW_INFO(\"%s, : Obtain Sta_info fail\\n\", __func__);\n\telse {\n\t\t/* string command length of \"GTK_REKEY_OFFLOAD\" */\n\t\tcmd_ptr += 18;\n\n\t\t_rtw_memcpy(psta->kek, cmd_ptr, RTW_KEK_LEN);\n\t\tcmd_ptr += RTW_KEK_LEN;\n\t\t/*\n\t\tprintk(\"supplicant KEK: \");\n\t\tfor(i=0;i<RTW_KEK_LEN; i++)\n\t\t\tprintk(\" %02x \", psta->kek[i]);\n\t\tprintk(\"\\n supplicant KCK: \");\n\t\t*/\n\t\t_rtw_memcpy(psta->kck, cmd_ptr, RTW_KCK_LEN);\n\t\tcmd_ptr += RTW_KCK_LEN;\n\t\t/*\n\t\tfor(i=0;i<RTW_KEK_LEN; i++)\n\t\t\tprintk(\" %02x \", psta->kck[i]);\n\t\t*/\n\t\t_rtw_memcpy(psta->replay_ctr, cmd_ptr, RTW_REPLAY_CTR_LEN);\n\t\tpsecuritypriv->binstallKCK_KEK = _TRUE;\n\n\t\t/* printk(\"\\nREPLAY_CTR: \"); */\n\t\t/* for(i=0;i<RTW_REPLAY_CTR_LEN; i++) */\n\t\t/* printk(\" %02x \", psta->replay_ctr[i]); */\n\t}\n\n\treturn _SUCCESS;\n}\n#endif /* CONFIG_GTK_OL */\n\n#ifdef CONFIG_RTW_MESH_AEK\nstatic int rtw_android_set_aek(struct net_device *ndev, char *command, int total_len)\n{\n#define SET_AEK_DATA_LEN (ETH_ALEN + 32)\n\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);\n\tu8 *addr;\n\tu8 *aek;\n\tint err = 0;\n\n\tif (total_len - strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AEK]) - 1 != SET_AEK_DATA_LEN) {\n\t\terr = -EINVAL;\n\t\tgoto exit;\n\t}\n\n\taddr = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AEK]) + 1;\n\taek = addr + ETH_ALEN;\n\n\tRTW_PRINT(FUNC_NDEV_FMT\" addr=\"MAC_FMT\"\\n\"\n\t\t, FUNC_NDEV_ARG(ndev), MAC_ARG(addr));\n\tif (0)\n\t\tRTW_PRINT(FUNC_NDEV_FMT\" aek=\"KEY_FMT KEY_FMT\"\\n\"\n\t\t\t, FUNC_NDEV_ARG(ndev), KEY_ARG(aek), KEY_ARG(aek + 16));\n\n\tif (rtw_mesh_plink_set_aek(adapter, addr, aek) != _SUCCESS)\n\t\terr = -ENOENT;\n\nexit:\n\treturn err;\n}\n#endif /* CONFIG_RTW_MESH_AEK */\n\nint rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd)\n{\n\t#define PRIVATE_COMMAND_MAX_LEN        8192\n\tint ret = 0;\n\tchar *command = NULL;\n\tint cmd_num;\n\tint bytes_written = 0;\n#ifdef CONFIG_PNO_SUPPORT\n\tuint cmdlen = 0;\n\tuint pno_enable = 0;\n#endif\n\tandroid_wifi_priv_cmd priv_cmd;\n\t_adapter\t*padapter = (_adapter *) rtw_netdev_priv(net);\n#ifdef CONFIG_WFD\n\tstruct wifi_display_info\t\t*pwfd_info;\n#endif\n\n\trtw_lock_suspend();\n\n\tif (!ifr->ifr_data) {\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n\tif (padapter->registrypriv.mp_mode == 1) {\n\t\tret = -EINVAL;\n\t\tgoto exit;\n\t}\n#ifdef CONFIG_COMPAT\n#if (KERNEL_VERSION(4, 6, 0) > LINUX_VERSION_CODE)\n\tif (is_compat_task()) {\n#else\n\tif (in_compat_syscall()) {\n#endif\n\t\t/* User space is 32-bit, use compat ioctl */\n\t\tcompat_android_wifi_priv_cmd compat_priv_cmd;\n\n\t\tif (copy_from_user(&compat_priv_cmd, ifr->ifr_data, sizeof(compat_android_wifi_priv_cmd))) {\n\t\t\tret = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\t\tpriv_cmd.buf = compat_ptr(compat_priv_cmd.buf);\n\t\tpriv_cmd.used_len = compat_priv_cmd.used_len;\n\t\tpriv_cmd.total_len = compat_priv_cmd.total_len;\n\t} else\n#endif /* CONFIG_COMPAT */\n\t\tif (copy_from_user(&priv_cmd, ifr->ifr_data, sizeof(android_wifi_priv_cmd))) {\n\t\t\tret = -EFAULT;\n\t\t\tgoto exit;\n\t\t}\n\tif (padapter->registrypriv.mp_mode == 1) {\n\t\tret = -EFAULT;\n\t\tgoto exit;\n\t}\n\t/*RTW_INFO(\"%s priv_cmd.buf=%p priv_cmd.total_len=%d  priv_cmd.used_len=%d\\n\",__func__,priv_cmd.buf,priv_cmd.total_len,priv_cmd.used_len);*/\n\tif (priv_cmd.total_len > PRIVATE_COMMAND_MAX_LEN || priv_cmd.total_len < 0) {\n\t\tRTW_WARN(\"%s: invalid private command (%d)\\n\", __FUNCTION__,\n\t\t\tpriv_cmd.total_len);\n\t\tret = -EFAULT;\n\t\tgoto exit;\n\t}\n\t\n\tcommand = rtw_zmalloc(priv_cmd.total_len+1);\n\tif (!command) {\n\t\tRTW_INFO(\"%s: failed to allocate memory\\n\", __FUNCTION__);\n\t\tret = -ENOMEM;\n\t\tgoto exit;\n\t}\n\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0))\n\tif (!access_ok(priv_cmd.buf, priv_cmd.total_len)) {\n\t#else\n\tif (!access_ok(VERIFY_READ, priv_cmd.buf, priv_cmd.total_len)) {\n\t#endif\n\t\tRTW_INFO(\"%s: failed to access memory\\n\", __FUNCTION__);\n\t\tret = -EFAULT;\n\t\tgoto exit;\n\t}\n\tif (copy_from_user(command, (void *)priv_cmd.buf, priv_cmd.total_len)) {\n\t\tret = -EFAULT;\n\t\tgoto exit;\n\t}\n\tcommand[priv_cmd.total_len] = '\\0';\n\tRTW_INFO(\"%s: Android private cmd \\\"%s\\\" on %s\\n\"\n\t\t , __FUNCTION__, command, ifr->ifr_name);\n\n\tcmd_num = rtw_android_cmdstr_to_num(command);\n\n\tswitch (cmd_num) {\n\tcase ANDROID_WIFI_CMD_START:\n\t\t/* bytes_written = wl_android_wifi_on(net); */\n\t\tgoto response;\n\tcase ANDROID_WIFI_CMD_SETFWPATH:\n\t\tgoto response;\n\t}\n\n\tif (!g_wifi_on) {\n\t\tRTW_INFO(\"%s: Ignore private cmd \\\"%s\\\" - iface %s is down\\n\"\n\t\t\t , __FUNCTION__, command, ifr->ifr_name);\n\t\tret = 0;\n\t\tgoto exit;\n\t}\n\n\tif (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {\n\t\tswitch (cmd_num) {\n\t\tcase ANDROID_WIFI_CMD_WFD_ENABLE:\n\t\tcase ANDROID_WIFI_CMD_WFD_DISABLE:\n\t\tcase ANDROID_WIFI_CMD_WFD_SET_TCPPORT:\n\t\tcase ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT:\n\t\tcase ANDROID_WIFI_CMD_WFD_SET_DEVTYPE:\n\t\t\tgoto response;\n\t\t}\n\t}\n\n\tswitch (cmd_num) {\n\n\tcase ANDROID_WIFI_CMD_STOP:\n\t\t/* bytes_written = wl_android_wifi_off(net); */\n\t\tbreak;\n\n\tcase ANDROID_WIFI_CMD_SCAN_ACTIVE:\n\t\t/* rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_ACTIVE); */\n#ifdef CONFIG_PLATFORM_MSTAR\n#ifdef CONFIG_IOCTL_CFG80211\n\t\tadapter_wdev_data((_adapter *)rtw_netdev_priv(net))->bandroid_scan = _TRUE;\n#endif /* CONFIG_IOCTL_CFG80211 */\n#endif /* CONFIG_PLATFORM_MSTAR */\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_SCAN_PASSIVE:\n\t\t/* rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_PASSIVE); */\n\t\tbreak;\n\n\tcase ANDROID_WIFI_CMD_RSSI:\n\t\tbytes_written = rtw_android_get_rssi(net, command, priv_cmd.total_len);\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_LINKSPEED:\n\t\tbytes_written = rtw_android_get_link_speed(net, command, priv_cmd.total_len);\n\t\tbreak;\n\n\tcase ANDROID_WIFI_CMD_MACADDR:\n\t\tbytes_written = rtw_android_get_macaddr(net, command, priv_cmd.total_len);\n\t\tbreak;\n\n\tcase ANDROID_WIFI_CMD_BLOCK_SCAN:\n\t\tbytes_written = rtw_android_set_block_scan(net, command, priv_cmd.total_len);\n\t\tbreak;\n\n\tcase ANDROID_WIFI_CMD_BLOCK:\n\t\tbytes_written = rtw_android_set_block(net, command, priv_cmd.total_len);\n\t\tbreak;\n\n\tcase ANDROID_WIFI_CMD_RXFILTER_START:\n\t\t/* bytes_written = net_os_set_packet_filter(net, 1); */\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_RXFILTER_STOP:\n\t\t/* bytes_written = net_os_set_packet_filter(net, 0); */\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_RXFILTER_ADD:\n\t\t/* int filter_num = *(command + strlen(CMD_RXFILTER_ADD) + 1) - '0'; */\n\t\t/* bytes_written = net_os_rxfilter_add_remove(net, TRUE, filter_num); */\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_RXFILTER_REMOVE:\n\t\t/* int filter_num = *(command + strlen(CMD_RXFILTER_REMOVE) + 1) - '0'; */\n\t\t/* bytes_written = net_os_rxfilter_add_remove(net, FALSE, filter_num); */\n\t\tbreak;\n\n\tcase ANDROID_WIFI_CMD_BTCOEXSCAN_START:\n\t\t/* TBD: BTCOEXSCAN-START */\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_BTCOEXSCAN_STOP:\n\t\t/* TBD: BTCOEXSCAN-STOP */\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_BTCOEXMODE:\n#if 0\n\t\tuint mode = *(command + strlen(CMD_BTCOEXMODE) + 1) - '0';\n\t\tif (mode == 1)\n\t\t\tnet_os_set_packet_filter(net, 0); /* DHCP starts */\n\t\telse\n\t\t\tnet_os_set_packet_filter(net, 1); /* DHCP ends */\n#ifdef WL_CFG80211\n\t\tbytes_written = wl_cfg80211_set_btcoex_dhcp(net, command);\n#endif\n#endif\n\t\tbreak;\n\n\tcase ANDROID_WIFI_CMD_SETSUSPENDMODE:\n\t\tbreak;\n\n\tcase ANDROID_WIFI_CMD_SETSUSPENDOPT:\n\t\t/* bytes_written = wl_android_set_suspendopt(net, command, priv_cmd.total_len); */\n\t\tbreak;\n\n\tcase ANDROID_WIFI_CMD_SETBAND:\n\t\tbytes_written = rtw_android_setband(net, command, priv_cmd.total_len);\n\t\tbreak;\n\n\tcase ANDROID_WIFI_CMD_GETBAND:\n\t\tbytes_written = rtw_android_getband(net, command, priv_cmd.total_len);\n\t\tbreak;\n\n\tcase ANDROID_WIFI_CMD_COUNTRY:\n\t\tbytes_written = rtw_android_set_country(net, command, priv_cmd.total_len);\n\t\tbreak;\n\n#ifdef CONFIG_PNO_SUPPORT\n\tcase ANDROID_WIFI_CMD_PNOSSIDCLR_SET:\n\t\t/* bytes_written = dhd_dev_pno_reset(net); */\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_PNOSETUP_SET:\n\t\tbytes_written = rtw_android_pno_setup(net, command, priv_cmd.total_len);\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_PNOENABLE_SET:\n\t\tcmdlen = strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_PNOENABLE_SET]);\n\t\tpno_enable = *(command + cmdlen + 1) - '0';\n\t\tbytes_written = rtw_android_pno_enable(net, pno_enable);\n\t\tbreak;\n#endif\n\n\tcase ANDROID_WIFI_CMD_P2P_DEV_ADDR:\n\t\tbytes_written = rtw_android_get_p2p_dev_addr(net, command, priv_cmd.total_len);\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_P2P_SET_NOA:\n\t\t/* int skip = strlen(CMD_P2P_SET_NOA) + 1; */\n\t\t/* bytes_written = wl_cfg80211_set_p2p_noa(net, command + skip, priv_cmd.total_len - skip); */\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_P2P_GET_NOA:\n\t\t/* bytes_written = wl_cfg80211_get_p2p_noa(net, command, priv_cmd.total_len); */\n\t\tbreak;\n\tcase ANDROID_WIFI_CMD_P2P_SET_PS:\n\t\t/* int skip = strlen(CMD_P2P_SET_PS) + 1; */\n\t\t/* bytes_written = wl_cfg80211_set_p2p_ps(net, command + skip, priv_cmd.total_len - skip); */\n\t\tbreak;\n\n#ifdef CONFIG_IOCTL_CFG80211\n\tcase ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE: {\n\t\tint skip = strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE]) + 3;\n\t\tbytes_written = rtw_cfg80211_set_mgnt_wpsp2pie(net, command + skip, priv_cmd.total_len - skip, *(command + skip - 2) - '0');\n\t\tbreak;\n\t}\n#endif /* CONFIG_IOCTL_CFG80211 */\n\n#ifdef CONFIG_WFD\n\n\tcase ANDROID_WIFI_CMD_MIRACAST:\n\t\tbytes_written = rtw_android_set_miracast_mode(net, command, priv_cmd.total_len);\n\t\tbreak;\n\n\tcase ANDROID_WIFI_CMD_WFD_ENABLE: {\n\t\t/*\tCommented by Albert 2012/07/24 */\n\t\t/*\tWe can enable the WFD function by using the following command: */\n\t\t/*\twpa_cli driver wfd-enable */\n\n\t\tif (padapter->wdinfo.driver_interface == DRIVER_CFG80211)\n\t\t\trtw_wfd_enable(padapter, 1);\n\t\tbreak;\n\t}\n\n\tcase ANDROID_WIFI_CMD_WFD_DISABLE: {\n\t\t/*\tCommented by Albert 2012/07/24 */\n\t\t/*\tWe can disable the WFD function by using the following command: */\n\t\t/*\twpa_cli driver wfd-disable */\n\n\t\tif (padapter->wdinfo.driver_interface == DRIVER_CFG80211)\n\t\t\trtw_wfd_enable(padapter, 0);\n\t\tbreak;\n\t}\n\tcase ANDROID_WIFI_CMD_WFD_SET_TCPPORT: {\n\t\t/*\tCommented by Albert 2012/07/24 */\n\t\t/*\tWe can set the tcp port number by using the following command: */\n\t\t/*\twpa_cli driver wfd-set-tcpport = 554 */\n\n\t\tif (padapter->wdinfo.driver_interface == DRIVER_CFG80211)\n\t\t\trtw_wfd_set_ctrl_port(padapter, (u16)get_int_from_command(command));\n\t\tbreak;\n\t}\n\tcase ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT: {\n\t\tbreak;\n\t}\n\tcase ANDROID_WIFI_CMD_WFD_SET_DEVTYPE: {\n\t\t/*\tCommented by Albert 2012/08/28 */\n\t\t/*\tSpecify the WFD device type ( WFD source/primary sink ) */\n\n\t\tpwfd_info = &padapter->wfd_info;\n\t\tif (padapter->wdinfo.driver_interface == DRIVER_CFG80211) {\n\t\t\tpwfd_info->wfd_device_type = (u8) get_int_from_command(command);\n\t\t\tpwfd_info->wfd_device_type &= WFD_DEVINFO_DUAL;\n\t\t}\n\t\tbreak;\n\t}\n#endif\n\tcase ANDROID_WIFI_CMD_CHANGE_DTIM: {\n#ifdef CONFIG_LPS\n\t\tu8 dtim;\n\t\tu8 *ptr = (u8 *) command;\n\n\t\tptr += 9;/* string command length of  \"SET_DTIM\"; */\n\n\t\tdtim = rtw_atoi(ptr);\n\n\t\tRTW_INFO(\"DTIM=%d\\n\", dtim);\n\n\t\trtw_lps_change_dtim_cmd(padapter, dtim);\n#endif\n\t}\n\tbreak;\n\n#if CONFIG_RTW_MACADDR_ACL\n\tcase ANDROID_WIFI_CMD_HOSTAPD_SET_MACADDR_ACL: {\n\t\trtw_set_macaddr_acl(padapter, RTW_ACL_PERIOD_BSS, get_int_from_command(command));\n\t\tbreak;\n\t}\n\tcase ANDROID_WIFI_CMD_HOSTAPD_ACL_ADD_STA: {\n\t\tu8 addr[ETH_ALEN] = {0x00};\n\t\tmacstr2num(addr, command + strlen(\"HOSTAPD_ACL_ADD_STA\") + 3);\t/* 3 is space bar + \"=\" + space bar these 3 chars */\n\t\trtw_acl_add_sta(padapter, RTW_ACL_PERIOD_BSS, addr);\n\t\tbreak;\n\t}\n\tcase ANDROID_WIFI_CMD_HOSTAPD_ACL_REMOVE_STA: {\n\t\tu8 addr[ETH_ALEN] = {0x00};\n\t\tmacstr2num(addr, command + strlen(\"HOSTAPD_ACL_REMOVE_STA\") + 3);\t/* 3 is space bar + \"=\" + space bar these 3 chars */\n\t\trtw_acl_remove_sta(padapter, RTW_ACL_PERIOD_BSS, addr);\n\t\tbreak;\n\t}\n#endif /* CONFIG_RTW_MACADDR_ACL */\n#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))\n\tcase ANDROID_WIFI_CMD_GTK_REKEY_OFFLOAD:\n\t\trtw_gtk_offload(net, (u8 *)command);\n\t\tbreak;\n#endif /* CONFIG_GTK_OL\t\t */\n\tcase ANDROID_WIFI_CMD_P2P_DISABLE: {\n#ifdef CONFIG_P2P\n\t\trtw_p2p_enable(padapter, P2P_ROLE_DISABLE);\n#endif /* CONFIG_P2P */\n\t\tbreak;\n\t}\n\n#ifdef CONFIG_RTW_MESH_AEK\n\tcase ANDROID_WIFI_CMD_SET_AEK:\n\t\tbytes_written = rtw_android_set_aek(net, command, priv_cmd.total_len);\n\t\tbreak;\n#endif\n\t\n\tcase ANDROID_WIFI_CMD_EXT_AUTH_STATUS: {\n\t\trtw_set_external_auth_status(padapter,\n\t\t\tcommand + strlen(\"EXT_AUTH_STATUS \"),\n\t\t\tpriv_cmd.total_len - strlen(\"EXT_AUTH_STATUS \"));\n\t\tbreak;\n\t}\n\tcase ANDROID_WIFI_CMD_DRIVERVERSION: {\n\t\tbytes_written = strlen(DRIVERVERSION);\n\t\tsnprintf(command, bytes_written + 1, DRIVERVERSION);\n\t\tbreak;\n\t}\n\tdefault:\n\t\tRTW_INFO(\"Unknown PRIVATE command %s - ignored\\n\", command);\n\t\tsnprintf(command, 3, \"OK\");\n\t\tbytes_written = strlen(\"OK\");\n\t}\n\nresponse:\n\tif (bytes_written >= 0) {\n\t\tif ((bytes_written == 0) && (priv_cmd.total_len > 0))\n\t\t\tcommand[0] = '\\0';\n\t\tif (bytes_written >= priv_cmd.total_len) {\n\t\t\tRTW_INFO(\"%s: bytes_written = %d\\n\", __FUNCTION__, bytes_written);\n\t\t\tbytes_written = priv_cmd.total_len;\n\t\t} else\n\t\t\tbytes_written++;\n\t\tpriv_cmd.used_len = bytes_written;\n\t\tif (copy_to_user((void *)priv_cmd.buf, command, bytes_written)) {\n\t\t\tRTW_INFO(\"%s: failed to copy data to user buffer\\n\", __FUNCTION__);\n\t\t\tret = -EFAULT;\n\t\t}\n\t} else\n\t\tret = bytes_written;\n\nexit:\n\trtw_unlock_suspend();\n\tif (command)\n\t\trtw_mfree(command, priv_cmd.total_len + 1);\n\n\treturn ret;\n}\n\n\n/**\n * Functions for Android WiFi card detection\n */\n#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC)\n\nstatic int g_wifidev_registered = 0;\nstatic struct semaphore wifi_control_sem;\nstatic struct wifi_platform_data *wifi_control_data = NULL;\nstatic struct resource *wifi_irqres = NULL;\n\nstatic int wifi_add_dev(void);\nstatic void wifi_del_dev(void);\n\nint rtw_android_wifictrl_func_add(void)\n{\n\tint ret = 0;\n\tsema_init(&wifi_control_sem, 0);\n\n\tret = wifi_add_dev();\n\tif (ret) {\n\t\tRTW_INFO(\"%s: platform_driver_register failed\\n\", __FUNCTION__);\n\t\treturn ret;\n\t}\n\tg_wifidev_registered = 1;\n\n\t/* Waiting callback after platform_driver_register is done or exit with error */\n\tif (down_timeout(&wifi_control_sem,  msecs_to_jiffies(1000)) != 0) {\n\t\tret = -EINVAL;\n\t\tRTW_INFO(\"%s: platform_driver_register timeout\\n\", __FUNCTION__);\n\t}\n\n\treturn ret;\n}\n\nvoid rtw_android_wifictrl_func_del(void)\n{\n\tif (g_wifidev_registered) {\n\t\twifi_del_dev();\n\t\tg_wifidev_registered = 0;\n\t}\n}\n\nvoid *wl_android_prealloc(int section, unsigned long size)\n{\n\tvoid *alloc_ptr = NULL;\n\tif (wifi_control_data && wifi_control_data->mem_prealloc) {\n\t\talloc_ptr = wifi_control_data->mem_prealloc(section, size);\n\t\tif (alloc_ptr) {\n\t\t\tRTW_INFO(\"success alloc section %d\\n\", section);\n\t\t\tif (size != 0L)\n\t\t\t\tmemset(alloc_ptr, 0, size);\n\t\t\treturn alloc_ptr;\n\t\t}\n\t}\n\n\tRTW_INFO(\"can't alloc section %d\\n\", section);\n\treturn NULL;\n}\n\nint wifi_get_irq_number(unsigned long *irq_flags_ptr)\n{\n\tif (wifi_irqres) {\n\t\t*irq_flags_ptr = wifi_irqres->flags & IRQF_TRIGGER_MASK;\n\t\treturn (int)wifi_irqres->start;\n\t}\n#ifdef CUSTOM_OOB_GPIO_NUM\n\treturn CUSTOM_OOB_GPIO_NUM;\n#else\n\treturn -1;\n#endif\n}\n\nint wifi_set_power(int on, unsigned long msec)\n{\n\tRTW_INFO(\"%s = %d\\n\", __FUNCTION__, on);\n\tif (wifi_control_data && wifi_control_data->set_power)\n\t\twifi_control_data->set_power(on);\n\tif (msec)\n\t\tmsleep(msec);\n\treturn 0;\n}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\nint wifi_get_mac_addr(unsigned char *buf)\n{\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\tif (!buf)\n\t\treturn -EINVAL;\n\tif (wifi_control_data && wifi_control_data->get_mac_addr)\n\t\treturn wifi_control_data->get_mac_addr(buf);\n\treturn -EOPNOTSUPP;\n}\n#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) */\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) || defined(COMPAT_KERNEL_RELEASE)\nvoid *wifi_get_country_code(char *ccode)\n{\n\tRTW_INFO(\"%s\\n\", __FUNCTION__);\n\tif (!ccode)\n\t\treturn NULL;\n\tif (wifi_control_data && wifi_control_data->get_country_code)\n\t\treturn wifi_control_data->get_country_code(ccode);\n\treturn NULL;\n}\n#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) */\n\nstatic int wifi_set_carddetect(int on)\n{\n\tRTW_INFO(\"%s = %d\\n\", __FUNCTION__, on);\n\tif (wifi_control_data && wifi_control_data->set_carddetect)\n\t\twifi_control_data->set_carddetect(on);\n\treturn 0;\n}\n\nstatic int wifi_probe(struct platform_device *pdev)\n{\n\tstruct wifi_platform_data *wifi_ctrl =\n\t\t(struct wifi_platform_data *)(pdev->dev.platform_data);\n\tint wifi_wake_gpio = 0;\n\n\tRTW_INFO(\"## %s\\n\", __FUNCTION__);\n\twifi_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, \"bcmdhd_wlan_irq\");\n\n\tif (wifi_irqres == NULL)\n\t\twifi_irqres = platform_get_resource_byname(pdev,\n\t\t\t\tIORESOURCE_IRQ, \"bcm4329_wlan_irq\");\n\telse\n\t\twifi_wake_gpio = wifi_irqres->start;\n\n#ifdef CONFIG_GPIO_WAKEUP\n\tRTW_INFO(\"%s: gpio:%d wifi_wake_gpio:%d\\n\", __func__,\n\t       (int)wifi_irqres->start, wifi_wake_gpio);\n\n\tif (wifi_wake_gpio > 0) {\n#ifdef CONFIG_PLATFORM_INTEL_BYT\n\t\twifi_configure_gpio();\n#else /* CONFIG_PLATFORM_INTEL_BYT */\n\t\tgpio_request(wifi_wake_gpio, \"oob_irq\");\n\t\tgpio_direction_input(wifi_wake_gpio);\n\t\toob_irq = gpio_to_irq(wifi_wake_gpio);\n#endif /* CONFIG_PLATFORM_INTEL_BYT */\n\t\tRTW_INFO(\"%s oob_irq:%d\\n\", __func__, oob_irq);\n\t} else if (wifi_irqres) {\n\t\toob_irq = wifi_irqres->start;\n\t\tRTW_INFO(\"%s oob_irq:%d\\n\", __func__, oob_irq);\n\t}\n#endif\n\twifi_control_data = wifi_ctrl;\n\n\twifi_set_power(1, 0);\t/* Power On */\n\twifi_set_carddetect(1);\t/* CardDetect (0->1) */\n\n\tup(&wifi_control_sem);\n\treturn 0;\n}\n\n#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN\nextern PADAPTER g_test_adapter;\n\nstatic void shutdown_card(void)\n{\n\tu32 addr;\n\tu8 tmp8, cnt = 0;\n\n\tif (NULL == g_test_adapter) {\n\t\tRTW_INFO(\"%s: padapter==NULL\\n\", __FUNCTION__);\n\t\treturn;\n\t}\n\n#ifdef CONFIG_FWLPS_IN_IPS\n\tLeaveAllPowerSaveMode(g_test_adapter);\n#endif /* CONFIG_FWLPS_IN_IPS */\n\n#ifdef CONFIG_WOWLAN\n#ifdef CONFIG_GPIO_WAKEUP\n\t/*default wake up pin change to BT*/\n\tRTW_INFO(\"%s:default wake up pin change to BT\\n\", __FUNCTION__);\n\trtw_hal_switch_gpio_wl_ctrl(g_test_adapter, WAKEUP_GPIO_IDX, _FALSE);\n#endif /* CONFIG_GPIO_WAKEUP */\n#endif /* CONFIG_WOWLAN */\n\n\t/* Leave SDIO HCI Suspend */\n\taddr = 0x10250086;\n\trtw_write8(g_test_adapter, addr, 0);\n\tdo {\n\t\ttmp8 = rtw_read8(g_test_adapter, addr);\n\t\tcnt++;\n\t\tRTW_INFO(FUNC_ADPT_FMT \": polling SDIO_HSUS_CTRL(0x%x)=0x%x, cnt=%d\\n\",\n\t\t\t FUNC_ADPT_ARG(g_test_adapter), addr, tmp8, cnt);\n\n\t\tif (tmp8 & BIT(1))\n\t\t\tbreak;\n\n\t\tif (cnt >= 100) {\n\t\t\tRTW_INFO(FUNC_ADPT_FMT \": polling 0x%x[1]==1 FAIL!!\\n\",\n\t\t\t\t FUNC_ADPT_ARG(g_test_adapter), addr);\n\t\t\tbreak;\n\t\t}\n\n\t\trtw_mdelay_os(10);\n\t} while (1);\n\n\t/* unlock register I/O */\n\trtw_write8(g_test_adapter, 0x1C, 0);\n\n\t/* enable power down function */\n\t/* 0x04[4] = 1 */\n\t/* 0x05[7] = 1 */\n\taddr = 0x04;\n\ttmp8 = rtw_read8(g_test_adapter, addr);\n\ttmp8 |= BIT(4);\n\trtw_write8(g_test_adapter, addr, tmp8);\n\tRTW_INFO(FUNC_ADPT_FMT \": read after write 0x%x=0x%x\\n\",\n\t\tFUNC_ADPT_ARG(g_test_adapter), addr, rtw_read8(g_test_adapter, addr));\n\n\taddr = 0x05;\n\ttmp8 = rtw_read8(g_test_adapter, addr);\n\ttmp8 |= BIT(7);\n\trtw_write8(g_test_adapter, addr, tmp8);\n\tRTW_INFO(FUNC_ADPT_FMT \": read after write 0x%x=0x%x\\n\",\n\t\tFUNC_ADPT_ARG(g_test_adapter), addr, rtw_read8(g_test_adapter, addr));\n\n\t/* lock register page0 0x0~0xB read/write */\n\trtw_write8(g_test_adapter, 0x1C, 0x0E);\n\n\trtw_set_surprise_removed(g_test_adapter);\n\tRTW_INFO(FUNC_ADPT_FMT \": bSurpriseRemoved=%s\\n\",\n\t\tFUNC_ADPT_ARG(g_test_adapter), rtw_is_surprise_removed(g_test_adapter) ? \"True\" : \"False\");\n}\n#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */\n\nstatic int wifi_remove(struct platform_device *pdev)\n{\n\tstruct wifi_platform_data *wifi_ctrl =\n\t\t(struct wifi_platform_data *)(pdev->dev.platform_data);\n\n\tRTW_INFO(\"## %s\\n\", __FUNCTION__);\n\twifi_control_data = wifi_ctrl;\n\n\twifi_set_power(0, 0);\t/* Power Off */\n\twifi_set_carddetect(0);\t/* CardDetect (1->0) */\n\n\tup(&wifi_control_sem);\n\treturn 0;\n}\n\n#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN\nstatic void wifi_shutdown(struct platform_device *pdev)\n{\n\tstruct wifi_platform_data *wifi_ctrl =\n\t\t(struct wifi_platform_data *)(pdev->dev.platform_data);\n\n\n\tRTW_INFO(\"## %s\\n\", __FUNCTION__);\n\n\twifi_control_data = wifi_ctrl;\n\n\tshutdown_card();\n\twifi_set_power(0, 0);\t/* Power Off */\n\twifi_set_carddetect(0);\t/* CardDetect (1->0) */\n}\n#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */\n\nstatic int wifi_suspend(struct platform_device *pdev, pm_message_t state)\n{\n\tRTW_INFO(\"##> %s\\n\", __FUNCTION__);\n#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY)\n\tbcmsdh_oob_intr_set(0);\n#endif\n\treturn 0;\n}\n\nstatic int wifi_resume(struct platform_device *pdev)\n{\n\tRTW_INFO(\"##> %s\\n\", __FUNCTION__);\n#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY)\n\tif (dhd_os_check_if_up(bcmsdh_get_drvdata()))\n\t\tbcmsdh_oob_intr_set(1);\n#endif\n\treturn 0;\n}\n\n/* temporarily use these two */\nstatic struct platform_driver wifi_device = {\n\t.probe          = wifi_probe,\n\t.remove         = wifi_remove,\n\t.suspend        = wifi_suspend,\n\t.resume         = wifi_resume,\n#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN\n\t.shutdown       = wifi_shutdown,\n#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */\n\t.driver         = {\n\t\t.name   = \"bcmdhd_wlan\",\n\t}\n};\n\nstatic struct platform_driver wifi_device_legacy = {\n\t.probe          = wifi_probe,\n\t.remove         = wifi_remove,\n\t.suspend        = wifi_suspend,\n\t.resume         = wifi_resume,\n\t.driver         = {\n\t\t.name   = \"bcm4329_wlan\",\n\t}\n};\n\nstatic int wifi_add_dev(void)\n{\n\tRTW_INFO(\"## Calling platform_driver_register\\n\");\n\tplatform_driver_register(&wifi_device);\n\tplatform_driver_register(&wifi_device_legacy);\n\treturn 0;\n}\n\nstatic void wifi_del_dev(void)\n{\n\tRTW_INFO(\"## Unregister platform_driver_register\\n\");\n\tplatform_driver_unregister(&wifi_device);\n\tplatform_driver_unregister(&wifi_device_legacy);\n}\n#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */\n\n#ifdef CONFIG_GPIO_WAKEUP\n#ifdef CONFIG_PLATFORM_INTEL_BYT\nint wifi_configure_gpio(void)\n{\n\tif (gpio_request(oob_gpio, \"oob_irq\")) {\n\t\tRTW_INFO(\"## %s Cannot request GPIO\\n\", __FUNCTION__);\n\t\treturn -1;\n\t}\n\tgpio_export(oob_gpio, 0);\n\tif (gpio_direction_input(oob_gpio)) {\n\t\tRTW_INFO(\"## %s Cannot set GPIO direction input\\n\", __FUNCTION__);\n\t\treturn -1;\n\t}\n\toob_irq = gpio_to_irq(oob_gpio);\n\tif (oob_irq < 0) {\n\t\tRTW_INFO(\"## %s Cannot convert GPIO to IRQ\\n\", __FUNCTION__);\n\t\treturn -1;\n\t}\n\n\tRTW_INFO(\"## %s OOB_IRQ=%d\\n\", __FUNCTION__, oob_irq);\n\n\treturn 0;\n}\n#endif /* CONFIG_PLATFORM_INTEL_BYT */\nvoid wifi_free_gpio(unsigned int gpio)\n{\n#ifdef CONFIG_PLATFORM_INTEL_BYT\n\tif (gpio)\n\t\tgpio_free(gpio);\n#endif /* CONFIG_PLATFORM_INTEL_BYT */\n}\n#endif /* CONFIG_GPIO_WAKEUP */\n"
  },
  {
    "path": "os_dep/linux/rtw_cfgvendor.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include <drv_types.h>\n\n#ifdef CONFIG_IOCTL_CFG80211\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT)\n\n/*\n#include <linux/kernel.h>\n#include <linux/if_arp.h>\n#include <asm/uaccess.h>\n\n#include <linux/kernel.h>\n#include <linux/kthread.h>\n#include <linux/netdevice.h>\n#include <linux/sched.h>\n#include <linux/etherdevice.h>\n#include <linux/wireless.h>\n#include <linux/ieee80211.h>\n#include <linux/wait.h>\n#include <net/cfg80211.h>\n*/\n\n#include <net/rtnetlink.h>\n\n#ifdef DBG_MEM_ALLOC\nextern bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size);\nstruct sk_buff *dbg_rtw_cfg80211_vendor_event_alloc(struct wiphy *wiphy, struct wireless_dev *wdev, int len, int event_id, gfp_t gfp\n\t\t, const enum mstat_f flags, const char *func, const int line)\n{\n\tstruct sk_buff *skb;\n\tunsigned int truesize = 0;\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0))\n\tskb = cfg80211_vendor_event_alloc(wiphy, len, event_id, gfp);\n#else\n\tskb = cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp);\n#endif\n\n\tif (skb)\n\t\ttruesize = skb->truesize;\n\n\tif (!skb || truesize < len || match_mstat_sniff_rules(flags, truesize))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\\n\", func, line, __FUNCTION__, len, skb, truesize);\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL\n\t\t, truesize\n\t);\n\n\treturn skb;\n}\n\nvoid dbg_rtw_cfg80211_vendor_event(struct sk_buff *skb, gfp_t gfp\n\t\t   , const enum mstat_f flags, const char *func, const int line)\n{\n\tunsigned int truesize = skb->truesize;\n\n\tif (match_mstat_sniff_rules(flags, truesize))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s, truesize=%u\\n\", func, line, __FUNCTION__, truesize);\n\n\tcfg80211_vendor_event(skb, gfp);\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, MSTAT_FREE\n\t\t, truesize\n\t);\n}\n\nstruct sk_buff *dbg_rtw_cfg80211_vendor_cmd_alloc_reply_skb(struct wiphy *wiphy, int len\n\t\t, const enum mstat_f flags, const char *func, const int line)\n{\n\tstruct sk_buff *skb;\n\tunsigned int truesize = 0;\n\n\tskb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len);\n\n\tif (skb)\n\t\ttruesize = skb->truesize;\n\n\tif (!skb || truesize < len || match_mstat_sniff_rules(flags, truesize))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\\n\", func, line, __FUNCTION__, len, skb, truesize);\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL\n\t\t, truesize\n\t);\n\n\treturn skb;\n}\n\nint dbg_rtw_cfg80211_vendor_cmd_reply(struct sk_buff *skb\n\t      , const enum mstat_f flags, const char *func, const int line)\n{\n\tunsigned int truesize = skb->truesize;\n\tint ret;\n\n\tif (match_mstat_sniff_rules(flags, truesize))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s, truesize=%u\\n\", func, line, __FUNCTION__, truesize);\n\n\tret = cfg80211_vendor_cmd_reply(skb);\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, MSTAT_FREE\n\t\t, truesize\n\t);\n\n\treturn ret;\n}\n\n#define rtw_cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp) \\\n\tdbg_rtw_cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)\n\n#define rtw_cfg80211_vendor_event(skb, gfp) \\\n\tdbg_rtw_cfg80211_vendor_event(skb, gfp, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)\n\n#define rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len) \\\n\tdbg_rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)\n\n#define rtw_cfg80211_vendor_cmd_reply(skb) \\\n\tdbg_rtw_cfg80211_vendor_cmd_reply(skb, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)\n#else\n\nstruct sk_buff *rtw_cfg80211_vendor_event_alloc(\n\tstruct wiphy *wiphy, struct wireless_dev *wdev, int len, int event_id, gfp_t gfp)\n{\n\tstruct sk_buff *skb;\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0))\n\tskb = cfg80211_vendor_event_alloc(wiphy, len, event_id, gfp);\n#else\n\tskb = cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp);\n#endif\n\treturn skb;\n}\n\n#define rtw_cfg80211_vendor_event(skb, gfp) \\\n\tcfg80211_vendor_event(skb, gfp)\n\n#define rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len) \\\n\tcfg80211_vendor_cmd_alloc_reply_skb(wiphy, len)\n\n#define rtw_cfg80211_vendor_cmd_reply(skb) \\\n\tcfg80211_vendor_cmd_reply(skb)\n#endif /* DBG_MEM_ALLOC */\n\n/*\n * This API is to be used for asynchronous vendor events. This\n * shouldn't be used in response to a vendor command from its\n * do_it handler context (instead rtw_cfgvendor_send_cmd_reply should\n * be used).\n */\nint rtw_cfgvendor_send_async_event(struct wiphy *wiphy,\n\t   struct net_device *dev, int event_id, const void  *data, int len)\n{\n\tu16 kflags;\n\tstruct sk_buff *skb;\n\n\tkflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;\n\n\t/* Alloc the SKB for vendor_event */\n\tskb = rtw_cfg80211_vendor_event_alloc(wiphy, ndev_to_wdev(dev), len, event_id, kflags);\n\tif (!skb) {\n\t\tRTW_ERR(FUNC_NDEV_FMT\" skb alloc failed\", FUNC_NDEV_ARG(dev));\n\t\treturn -ENOMEM;\n\t}\n\n\t/* Push the data to the skb */\n\tnla_put_nohdr(skb, len, data);\n\n\trtw_cfg80211_vendor_event(skb, kflags);\n\n\treturn 0;\n}\n\nstatic int rtw_cfgvendor_send_cmd_reply(struct wiphy *wiphy,\n\t\t\tstruct net_device *dev, const void  *data, int len)\n{\n\tstruct sk_buff *skb;\n\n\t/* Alloc the SKB for vendor_event */\n\tskb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len);\n\tif (unlikely(!skb)) {\n\t\tRTW_ERR(FUNC_NDEV_FMT\" skb alloc failed\", FUNC_NDEV_ARG(dev));\n\t\treturn -ENOMEM;\n\t}\n\n\t/* Push the data to the skb */\n\tnla_put_nohdr(skb, len, data);\n\n\treturn rtw_cfg80211_vendor_cmd_reply(skb);\n}\n\n/* Feature enums */\n#define WIFI_FEATURE_INFRA              0x0001      // Basic infrastructure mode\n#define WIFI_FEATURE_INFRA_5G           0x0002      // Support for 5 GHz Band\n#define WIFI_FEATURE_HOTSPOT            0x0004      // Support for GAS/ANQP\n#define WIFI_FEATURE_P2P                0x0008      // Wifi-Direct\n#define WIFI_FEATURE_SOFT_AP            0x0010      // Soft AP\n#define WIFI_FEATURE_GSCAN              0x0020      // Google-Scan APIs\n#define WIFI_FEATURE_NAN                0x0040      // Neighbor Awareness Networking\n#define WIFI_FEATURE_D2D_RTT            0x0080      // Device-to-device RTT\n#define WIFI_FEATURE_D2AP_RTT           0x0100      // Device-to-AP RTT\n#define WIFI_FEATURE_BATCH_SCAN         0x0200      // Batched Scan (legacy)\n#define WIFI_FEATURE_PNO                0x0400      // Preferred network offload\n#define WIFI_FEATURE_ADDITIONAL_STA     0x0800      // Support for two STAs\n#define WIFI_FEATURE_TDLS               0x1000      // Tunnel directed link setup\n#define WIFI_FEATURE_TDLS_OFFCHANNEL    0x2000      // Support for TDLS off channel\n#define WIFI_FEATURE_EPR                0x4000      // Enhanced power reporting\n#define WIFI_FEATURE_AP_STA             0x8000      // Support for AP STA Concurrency\n#define WIFI_FEATURE_LINK_LAYER_STATS   0x10000     // Link layer stats collection\n#define WIFI_FEATURE_LOGGER             0x20000     // WiFi Logger\n#define WIFI_FEATURE_HAL_EPNO           0x40000     // WiFi PNO enhanced\n#define WIFI_FEATURE_RSSI_MONITOR       0x80000     // RSSI Monitor\n#define WIFI_FEATURE_MKEEP_ALIVE        0x100000    // WiFi mkeep_alive\n#define WIFI_FEATURE_CONFIG_NDO         0x200000    // ND offload configure\n#define WIFI_FEATURE_TX_TRANSMIT_POWER  0x400000    // Capture Tx transmit power levels\n#define WIFI_FEATURE_CONTROL_ROAMING    0x800000    // Enable/Disable firmware roaming\n#define WIFI_FEATURE_IE_WHITELIST       0x1000000   // Support Probe IE white listing\n#define WIFI_FEATURE_SCAN_RAND          0x2000000   // Support MAC & Probe Sequence Number randomization\n// Add more features here\n\n#define MAX_FEATURE_SET_CONCURRRENT_GROUPS  3\n\n#include <hal_data.h>\nint rtw_dev_get_feature_set(struct net_device *dev)\n{\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);\n\tHAL_VERSION *hal_ver = &HalData->version_id;\n\n\tint feature_set = 0;\n\n\tfeature_set |= WIFI_FEATURE_INFRA;\n\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\tif (is_supported_5g(adapter_to_regsty(adapter)->wireless_mode))\n\t\tfeature_set |= WIFI_FEATURE_INFRA_5G;\n#endif\n\n\tfeature_set |= WIFI_FEATURE_P2P;\n\tfeature_set |= WIFI_FEATURE_SOFT_AP;\n\n\tfeature_set |= WIFI_FEATURE_ADDITIONAL_STA;\n#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS\n\tfeature_set |= WIFI_FEATURE_LINK_LAYER_STATS;\n#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */\n\n#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR\n        feature_set |= WIFI_FEATURE_RSSI_MONITOR;\n#endif\n\n#ifdef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER\n\tfeature_set |= WIFI_FEATURE_LOGGER;\n#endif\n\n#ifdef CONFIG_RTW_WIFI_HAL\n\tfeature_set |= WIFI_FEATURE_CONFIG_NDO;\n\tfeature_set |= WIFI_FEATURE_SCAN_RAND;\n#endif\n\n\treturn feature_set;\n}\n\nint *rtw_dev_get_feature_set_matrix(struct net_device *dev, int *num)\n{\n\tint feature_set_full, mem_needed;\n\tint *ret;\n\n\t*num = 0;\n\tmem_needed = sizeof(int) * MAX_FEATURE_SET_CONCURRRENT_GROUPS;\n\tret = (int *)rtw_malloc(mem_needed);\n\n\tif (!ret) {\n\t\tRTW_ERR(FUNC_NDEV_FMT\" failed to allocate %d bytes\\n\"\n\t\t\t, FUNC_NDEV_ARG(dev), mem_needed);\n\t\treturn ret;\n\t}\n\n\tfeature_set_full = rtw_dev_get_feature_set(dev);\n\n\tret[0] = (feature_set_full & WIFI_FEATURE_INFRA) |\n\t\t (feature_set_full & WIFI_FEATURE_INFRA_5G) |\n\t\t (feature_set_full & WIFI_FEATURE_NAN) |\n\t\t (feature_set_full & WIFI_FEATURE_D2D_RTT) |\n\t\t (feature_set_full & WIFI_FEATURE_D2AP_RTT) |\n\t\t (feature_set_full & WIFI_FEATURE_PNO) |\n\t\t (feature_set_full & WIFI_FEATURE_BATCH_SCAN) |\n\t\t (feature_set_full & WIFI_FEATURE_GSCAN) |\n\t\t (feature_set_full & WIFI_FEATURE_HOTSPOT) |\n\t\t (feature_set_full & WIFI_FEATURE_ADDITIONAL_STA) |\n\t\t (feature_set_full & WIFI_FEATURE_EPR);\n\n\tret[1] = (feature_set_full & WIFI_FEATURE_INFRA) |\n\t\t (feature_set_full & WIFI_FEATURE_INFRA_5G) |\n\t\t /* Not yet verified NAN with P2P */\n\t\t /* (feature_set_full & WIFI_FEATURE_NAN) | */\n\t\t (feature_set_full & WIFI_FEATURE_P2P) |\n\t\t (feature_set_full & WIFI_FEATURE_D2AP_RTT) |\n\t\t (feature_set_full & WIFI_FEATURE_D2D_RTT) |\n\t\t (feature_set_full & WIFI_FEATURE_EPR);\n\n\tret[2] = (feature_set_full & WIFI_FEATURE_INFRA) |\n\t\t (feature_set_full & WIFI_FEATURE_INFRA_5G) |\n\t\t (feature_set_full & WIFI_FEATURE_NAN) |\n\t\t (feature_set_full & WIFI_FEATURE_D2D_RTT) |\n\t\t (feature_set_full & WIFI_FEATURE_D2AP_RTT) |\n\t\t (feature_set_full & WIFI_FEATURE_TDLS) |\n\t\t (feature_set_full & WIFI_FEATURE_TDLS_OFFCHANNEL) |\n\t\t (feature_set_full & WIFI_FEATURE_EPR);\n\t*num = MAX_FEATURE_SET_CONCURRRENT_GROUPS;\n\n\treturn ret;\n}\n\nstatic int rtw_cfgvendor_get_feature_set(struct wiphy *wiphy,\n\t\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint err = 0;\n\tint reply;\n\n\treply = rtw_dev_get_feature_set(wdev_to_ndev(wdev));\n\n\terr =  rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), &reply, sizeof(int));\n\n\tif (unlikely(err))\n\t\tRTW_ERR(FUNC_NDEV_FMT\" Vendor Command reply failed ret:%d\\n\"\n\t\t\t, FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err);\n\n\treturn err;\n}\n\nstatic int rtw_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy,\n\t\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint err = 0;\n\tstruct sk_buff *skb;\n\tint *reply;\n\tint num, mem_needed, i;\n\n\treply = rtw_dev_get_feature_set_matrix(wdev_to_ndev(wdev), &num);\n\n\tif (!reply) {\n\t\tRTW_ERR(FUNC_NDEV_FMT\" Could not get feature list matrix\\n\"\n\t\t\t, FUNC_NDEV_ARG(wdev_to_ndev(wdev)));\n\t\terr = -EINVAL;\n\t\treturn err;\n\t}\n\n\tmem_needed = VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * num) +\n\t\t     ATTRIBUTE_U32_LEN;\n\n\t/* Alloc the SKB for vendor_event */\n\tskb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);\n\tif (unlikely(!skb)) {\n\t\tRTW_ERR(FUNC_NDEV_FMT\" skb alloc failed\", FUNC_NDEV_ARG(wdev_to_ndev(wdev)));\n\t\terr = -ENOMEM;\n\t\tgoto exit;\n\t}\n\n\tnla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET, num);\n\tfor (i = 0; i < num; i++)\n\t\tnla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_FEATURE_SET, reply[i]);\n\n\terr =  rtw_cfg80211_vendor_cmd_reply(skb);\n\n\tif (unlikely(err))\n\t\tRTW_ERR(FUNC_NDEV_FMT\" Vendor Command reply failed ret:%d\\n\"\n\t\t\t, FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err);\nexit:\n\trtw_mfree((u8 *)reply, sizeof(int) * num);\n\treturn err;\n}\n\n#if defined(GSCAN_SUPPORT) && 0\nint rtw_cfgvendor_send_hotlist_event(struct wiphy *wiphy,\n\tstruct net_device *dev, void  *data, int len, rtw_vendor_event_t event)\n{\n\tu16 kflags;\n\tconst void *ptr;\n\tstruct sk_buff *skb;\n\tint malloc_len, total, iter_cnt_to_send, cnt;\n\tgscan_results_cache_t *cache = (gscan_results_cache_t *)data;\n\n\ttotal = len / sizeof(wifi_gscan_result_t);\n\twhile (total > 0) {\n\t\tmalloc_len = (total * sizeof(wifi_gscan_result_t)) + VENDOR_DATA_OVERHEAD;\n\t\tif (malloc_len > NLMSG_DEFAULT_SIZE)\n\t\t\tmalloc_len = NLMSG_DEFAULT_SIZE;\n\t\titer_cnt_to_send =\n\t\t\t(malloc_len - VENDOR_DATA_OVERHEAD) / sizeof(wifi_gscan_result_t);\n\t\ttotal = total - iter_cnt_to_send;\n\n\t\tkflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;\n\n\t\t/* Alloc the SKB for vendor_event */\n\t\tskb = rtw_cfg80211_vendor_event_alloc(wiphy, ndev_to_wdev(dev), malloc_len, event, kflags);\n\t\tif (!skb) {\n\t\t\tWL_ERR((\"skb alloc failed\"));\n\t\t\treturn -ENOMEM;\n\t\t}\n\n\t\twhile (cache && iter_cnt_to_send) {\n\t\t\tptr = (const void *) &cache->results[cache->tot_consumed];\n\n\t\t\tif (iter_cnt_to_send < (cache->tot_count - cache->tot_consumed))\n\t\t\t\tcnt = iter_cnt_to_send;\n\t\t\telse\n\t\t\t\tcnt = (cache->tot_count - cache->tot_consumed);\n\n\t\t\titer_cnt_to_send -= cnt;\n\t\t\tcache->tot_consumed += cnt;\n\t\t\t/* Push the data to the skb */\n\t\t\tnla_append(skb, cnt * sizeof(wifi_gscan_result_t), ptr);\n\t\t\tif (cache->tot_consumed == cache->tot_count)\n\t\t\t\tcache = cache->next;\n\n\t\t}\n\n\t\trtw_cfg80211_vendor_event(skb, kflags);\n\t}\n\n\treturn 0;\n}\n\n\nstatic int rtw_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy,\n\t\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint err = 0;\n\tstruct bcm_cfg80211 *cfg = wiphy_priv(wiphy);\n\tdhd_pno_gscan_capabilities_t *reply = NULL;\n\tuint32 reply_len = 0;\n\n\n\treply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),\n\t\t\t      DHD_PNO_GET_CAPABILITIES, NULL, &reply_len);\n\tif (!reply) {\n\t\tWL_ERR((\"Could not get capabilities\\n\"));\n\t\terr = -EINVAL;\n\t\treturn err;\n\t}\n\n\terr =  rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),\n\t\t\t\t\t    reply, reply_len);\n\n\tif (unlikely(err))\n\t\tWL_ERR((\"Vendor Command reply failed ret:%d\\n\", err));\n\n\tkfree(reply);\n\treturn err;\n}\n\nstatic int rtw_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy,\n\t\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint err = 0, type, band;\n\tstruct bcm_cfg80211 *cfg = wiphy_priv(wiphy);\n\tuint16 *reply = NULL;\n\tuint32 reply_len = 0, num_channels, mem_needed;\n\tstruct sk_buff *skb;\n\n\ttype = nla_type(data);\n\n\tif (type == GSCAN_ATTRIBUTE_BAND)\n\t\tband = nla_get_u32(data);\n\telse\n\t\treturn -1;\n\n\treply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),\n\t\t\t      DHD_PNO_GET_CHANNEL_LIST, &band, &reply_len);\n\n\tif (!reply) {\n\t\tWL_ERR((\"Could not get channel list\\n\"));\n\t\terr = -EINVAL;\n\t\treturn err;\n\t}\n\tnum_channels =  reply_len / sizeof(uint32);\n\tmem_needed = reply_len + VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * 2);\n\n\t/* Alloc the SKB for vendor_event */\n\tskb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);\n\tif (unlikely(!skb)) {\n\t\tWL_ERR((\"skb alloc failed\"));\n\t\terr = -ENOMEM;\n\t\tgoto exit;\n\t}\n\n\tnla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_CHANNELS, num_channels);\n\tnla_put(skb, GSCAN_ATTRIBUTE_CHANNEL_LIST, reply_len, reply);\n\n\terr =  rtw_cfg80211_vendor_cmd_reply(skb);\n\n\tif (unlikely(err))\n\t\tWL_ERR((\"Vendor Command reply failed ret:%d\\n\", err));\nexit:\n\tkfree(reply);\n\treturn err;\n}\n\nstatic int rtw_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy,\n\t\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint err = 0;\n\tstruct bcm_cfg80211 *cfg = wiphy_priv(wiphy);\n\tgscan_results_cache_t *results, *iter;\n\tuint32 reply_len, complete = 0, num_results_iter;\n\tint32 mem_needed;\n\twifi_gscan_result_t *ptr;\n\tuint16 num_scan_ids, num_results;\n\tstruct sk_buff *skb;\n\tstruct nlattr *scan_hdr;\n\n\tdhd_dev_wait_batch_results_complete(bcmcfg_to_prmry_ndev(cfg));\n\tdhd_dev_pno_lock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));\n\tresults = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),\n\t\t\t\tDHD_PNO_GET_BATCH_RESULTS, NULL, &reply_len);\n\n\tif (!results) {\n\t\tWL_ERR((\"No results to send %d\\n\", err));\n\t\terr =  rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),\n\t\t\t\t\t\t    results, 0);\n\n\t\tif (unlikely(err))\n\t\t\tWL_ERR((\"Vendor Command reply failed ret:%d\\n\", err));\n\t\tdhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));\n\t\treturn err;\n\t}\n\tnum_scan_ids = reply_len & 0xFFFF;\n\tnum_results = (reply_len & 0xFFFF0000) >> 16;\n\tmem_needed = (num_results * sizeof(wifi_gscan_result_t)) +\n\t\t     (num_scan_ids * GSCAN_BATCH_RESULT_HDR_LEN) +\n\t\t     VENDOR_REPLY_OVERHEAD + SCAN_RESULTS_COMPLETE_FLAG_LEN;\n\n\tif (mem_needed > (int32)NLMSG_DEFAULT_SIZE) {\n\t\tmem_needed = (int32)NLMSG_DEFAULT_SIZE;\n\t\tcomplete = 0;\n\t} else\n\t\tcomplete = 1;\n\n\tWL_TRACE((\"complete %d mem_needed %d max_mem %d\\n\", complete, mem_needed,\n\t\t  (int)NLMSG_DEFAULT_SIZE));\n\t/* Alloc the SKB for vendor_event */\n\tskb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);\n\tif (unlikely(!skb)) {\n\t\tWL_ERR((\"skb alloc failed\"));\n\t\tdhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));\n\t\treturn -ENOMEM;\n\t}\n\titer = results;\n\n\tnla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE, complete);\n\n\tmem_needed = mem_needed - (SCAN_RESULTS_COMPLETE_FLAG_LEN + VENDOR_REPLY_OVERHEAD);\n\n\twhile (iter && ((mem_needed - GSCAN_BATCH_RESULT_HDR_LEN)  > 0)) {\n\t\tscan_hdr = nla_nest_start(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS);\n\t\tnla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_ID, iter->scan_id);\n\t\tnla_put_u8(skb, GSCAN_ATTRIBUTE_SCAN_FLAGS, iter->flag);\n\t\tnum_results_iter =\n\t\t\t(mem_needed - GSCAN_BATCH_RESULT_HDR_LEN) / sizeof(wifi_gscan_result_t);\n\n\t\tif ((iter->tot_count - iter->tot_consumed) < num_results_iter)\n\t\t\tnum_results_iter = iter->tot_count - iter->tot_consumed;\n\n\t\tnla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_OF_RESULTS, num_results_iter);\n\t\tif (num_results_iter) {\n\t\t\tptr = &iter->results[iter->tot_consumed];\n\t\t\titer->tot_consumed += num_results_iter;\n\t\t\tnla_put(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS,\n\t\t\t\tnum_results_iter * sizeof(wifi_gscan_result_t), ptr);\n\t\t}\n\t\tnla_nest_end(skb, scan_hdr);\n\t\tmem_needed -= GSCAN_BATCH_RESULT_HDR_LEN +\n\t\t\t      (num_results_iter * sizeof(wifi_gscan_result_t));\n\t\titer = iter->next;\n\t}\n\n\tdhd_dev_gscan_batch_cache_cleanup(bcmcfg_to_prmry_ndev(cfg));\n\tdhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));\n\n\treturn rtw_cfg80211_vendor_cmd_reply(skb);\n}\n\nstatic int rtw_cfgvendor_initiate_gscan(struct wiphy *wiphy,\n\t\t       struct wireless_dev *wdev, const void  *data, int len)\n{\n\tint err = 0;\n\tstruct bcm_cfg80211 *cfg = wiphy_priv(wiphy);\n\tint type, tmp = len;\n\tint run = 0xFF;\n\tint flush = 0;\n\tconst struct nlattr *iter;\n\n\tnla_for_each_attr(iter, data, len, tmp) {\n\t\ttype = nla_type(iter);\n\t\tif (type == GSCAN_ATTRIBUTE_ENABLE_FEATURE)\n\t\t\trun = nla_get_u32(iter);\n\t\telse if (type == GSCAN_ATTRIBUTE_FLUSH_FEATURE)\n\t\t\tflush = nla_get_u32(iter);\n\t}\n\n\tif (run != 0xFF) {\n\t\terr = dhd_dev_pno_run_gscan(bcmcfg_to_prmry_ndev(cfg), run, flush);\n\n\t\tif (unlikely(err))\n\t\t\tWL_ERR((\"Could not run gscan:%d\\n\", err));\n\t\treturn err;\n\t} else\n\t\treturn -1;\n\n\n}\n\nstatic int rtw_cfgvendor_enable_full_scan_result(struct wiphy *wiphy,\n\t\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint err = 0;\n\tstruct bcm_cfg80211 *cfg = wiphy_priv(wiphy);\n\tint type;\n\tbool real_time = FALSE;\n\n\ttype = nla_type(data);\n\n\tif (type == GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS) {\n\t\treal_time = nla_get_u32(data);\n\n\t\terr = dhd_dev_pno_enable_full_scan_result(bcmcfg_to_prmry_ndev(cfg), real_time);\n\n\t\tif (unlikely(err))\n\t\t\tWL_ERR((\"Could not run gscan:%d\\n\", err));\n\n\t} else\n\t\terr = -1;\n\n\treturn err;\n}\n\nstatic int rtw_cfgvendor_set_scan_cfg(struct wiphy *wiphy,\n\t\t     struct wireless_dev *wdev, const void  *data, int len)\n{\n\tint err = 0;\n\tstruct bcm_cfg80211 *cfg = wiphy_priv(wiphy);\n\tgscan_scan_params_t *scan_param;\n\tint j = 0;\n\tint type, tmp, tmp1, tmp2, k = 0;\n\tconst struct nlattr *iter, *iter1, *iter2;\n\tstruct dhd_pno_gscan_channel_bucket  *ch_bucket;\n\n\tscan_param = kzalloc(sizeof(gscan_scan_params_t), GFP_KERNEL);\n\tif (!scan_param) {\n\t\tWL_ERR((\"Could not set GSCAN scan cfg, mem alloc failure\\n\"));\n\t\terr = -EINVAL;\n\t\treturn err;\n\n\t}\n\n\tscan_param->scan_fr = PNO_SCAN_MIN_FW_SEC;\n\tnla_for_each_attr(iter, data, len, tmp) {\n\t\ttype = nla_type(iter);\n\n\t\tif (j >= GSCAN_MAX_CH_BUCKETS)\n\t\t\tbreak;\n\n\t\tswitch (type) {\n\t\tcase GSCAN_ATTRIBUTE_BASE_PERIOD:\n\t\t\tscan_param->scan_fr = nla_get_u32(iter) / 1000;\n\t\t\tbreak;\n\t\tcase GSCAN_ATTRIBUTE_NUM_BUCKETS:\n\t\t\tscan_param->nchannel_buckets = nla_get_u32(iter);\n\t\t\tbreak;\n\t\tcase GSCAN_ATTRIBUTE_CH_BUCKET_1:\n\t\tcase GSCAN_ATTRIBUTE_CH_BUCKET_2:\n\t\tcase GSCAN_ATTRIBUTE_CH_BUCKET_3:\n\t\tcase GSCAN_ATTRIBUTE_CH_BUCKET_4:\n\t\tcase GSCAN_ATTRIBUTE_CH_BUCKET_5:\n\t\tcase GSCAN_ATTRIBUTE_CH_BUCKET_6:\n\t\tcase GSCAN_ATTRIBUTE_CH_BUCKET_7:\n\t\t\tnla_for_each_nested(iter1, iter, tmp1) {\n\t\t\t\ttype = nla_type(iter1);\n\t\t\t\tch_bucket =\n\t\t\t\t\tscan_param->channel_bucket;\n\n\t\t\t\tswitch (type) {\n\t\t\t\tcase GSCAN_ATTRIBUTE_BUCKET_ID:\n\t\t\t\t\tbreak;\n\t\t\t\tcase GSCAN_ATTRIBUTE_BUCKET_PERIOD:\n\t\t\t\t\tch_bucket[j].bucket_freq_multiple =\n\t\t\t\t\t\tnla_get_u32(iter1) / 1000;\n\t\t\t\t\tbreak;\n\t\t\t\tcase GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS:\n\t\t\t\t\tch_bucket[j].num_channels =\n\t\t\t\t\t\tnla_get_u32(iter1);\n\t\t\t\t\tbreak;\n\t\t\t\tcase GSCAN_ATTRIBUTE_BUCKET_CHANNELS:\n\t\t\t\t\tnla_for_each_nested(iter2, iter1, tmp2) {\n\t\t\t\t\t\tif (k >= PFN_SWC_RSSI_WINDOW_MAX)\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tch_bucket[j].chan_list[k] =\n\t\t\t\t\t\t\tnla_get_u32(iter2);\n\t\t\t\t\t\tk++;\n\t\t\t\t\t}\n\t\t\t\t\tk = 0;\n\t\t\t\t\tbreak;\n\t\t\t\tcase GSCAN_ATTRIBUTE_BUCKETS_BAND:\n\t\t\t\t\tch_bucket[j].band = (uint16)\n\t\t\t\t\t\t\t    nla_get_u32(iter1);\n\t\t\t\t\tbreak;\n\t\t\t\tcase GSCAN_ATTRIBUTE_REPORT_EVENTS:\n\t\t\t\t\tch_bucket[j].report_flag = (uint8)\n\t\t\t\t\t\t\t   nla_get_u32(iter1);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\tj++;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),\n\t\t\t\t      DHD_PNO_SCAN_CFG_ID, scan_param, 0) < 0) {\n\t\tWL_ERR((\"Could not set GSCAN scan cfg\\n\"));\n\t\terr = -EINVAL;\n\t}\n\n\tkfree(scan_param);\n\treturn err;\n\n}\n\nstatic int rtw_cfgvendor_hotlist_cfg(struct wiphy *wiphy,\n\t\t    struct wireless_dev *wdev, const void  *data, int len)\n{\n\tint err = 0;\n\tstruct bcm_cfg80211 *cfg = wiphy_priv(wiphy);\n\tgscan_hotlist_scan_params_t *hotlist_params;\n\tint tmp, tmp1, tmp2, type, j = 0, dummy;\n\tconst struct nlattr *outer, *inner, *iter;\n\tuint8 flush = 0;\n\tstruct bssid_t *pbssid;\n\n\thotlist_params = (gscan_hotlist_scan_params_t *)kzalloc(len, GFP_KERNEL);\n\tif (!hotlist_params) {\n\t\tWL_ERR((\"Cannot Malloc mem to parse config commands size - %d bytes\\n\", len));\n\t\treturn -1;\n\t}\n\n\thotlist_params->lost_ap_window = GSCAN_LOST_AP_WINDOW_DEFAULT;\n\n\tnla_for_each_attr(iter, data, len, tmp2) {\n\t\ttype = nla_type(iter);\n\t\tswitch (type) {\n\t\tcase GSCAN_ATTRIBUTE_HOTLIST_BSSIDS:\n\t\t\tpbssid = hotlist_params->bssid;\n\t\t\tnla_for_each_nested(outer, iter, tmp) {\n\t\t\t\tnla_for_each_nested(inner, outer, tmp1) {\n\t\t\t\t\ttype = nla_type(inner);\n\n\t\t\t\t\tswitch (type) {\n\t\t\t\t\tcase GSCAN_ATTRIBUTE_BSSID:\n\t\t\t\t\t\tmemcpy(&(pbssid[j].macaddr),\n\t\t\t\t\t\t       nla_data(inner), ETHER_ADDR_LEN);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase GSCAN_ATTRIBUTE_RSSI_LOW:\n\t\t\t\t\t\tpbssid[j].rssi_reporting_threshold =\n\t\t\t\t\t\t\t(int8) nla_get_u8(inner);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase GSCAN_ATTRIBUTE_RSSI_HIGH:\n\t\t\t\t\t\tdummy = (int8) nla_get_u8(inner);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tj++;\n\t\t\t}\n\t\t\thotlist_params->nbssid = j;\n\t\t\tbreak;\n\t\tcase GSCAN_ATTRIBUTE_HOTLIST_FLUSH:\n\t\t\tflush = nla_get_u8(iter);\n\t\t\tbreak;\n\t\tcase GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:\n\t\t\thotlist_params->lost_ap_window = nla_get_u32(iter);\n\t\t\tbreak;\n\t\t}\n\n\t}\n\n\tif (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),\n\t\tDHD_PNO_GEOFENCE_SCAN_CFG_ID, hotlist_params, flush) < 0) {\n\t\tWL_ERR((\"Could not set GSCAN HOTLIST cfg\\n\"));\n\t\terr = -EINVAL;\n\t\tgoto exit;\n\t}\nexit:\n\tkfree(hotlist_params);\n\treturn err;\n}\nstatic int rtw_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy,\n\t\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint err = 0, tmp, type;\n\tstruct bcm_cfg80211 *cfg = wiphy_priv(wiphy);\n\tgscan_batch_params_t batch_param;\n\tconst struct nlattr *iter;\n\n\tbatch_param.mscan = batch_param.bestn = 0;\n\tbatch_param.buffer_threshold = GSCAN_BATCH_NO_THR_SET;\n\n\tnla_for_each_attr(iter, data, len, tmp) {\n\t\ttype = nla_type(iter);\n\n\t\tswitch (type) {\n\t\tcase GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN:\n\t\t\tbatch_param.bestn = nla_get_u32(iter);\n\t\t\tbreak;\n\t\tcase GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE:\n\t\t\tbatch_param.mscan = nla_get_u32(iter);\n\t\t\tbreak;\n\t\tcase GSCAN_ATTRIBUTE_REPORT_THRESHOLD:\n\t\t\tbatch_param.buffer_threshold = nla_get_u32(iter);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),\n\t\t\t      DHD_PNO_BATCH_SCAN_CFG_ID, &batch_param, 0) < 0) {\n\t\tWL_ERR((\"Could not set batch cfg\\n\"));\n\t\terr = -EINVAL;\n\t\treturn err;\n\t}\n\n\treturn err;\n}\n\nstatic int rtw_cfgvendor_significant_change_cfg(struct wiphy *wiphy,\n\t\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint err = 0;\n\tstruct bcm_cfg80211 *cfg = wiphy_priv(wiphy);\n\tgscan_swc_params_t *significant_params;\n\tint tmp, tmp1, tmp2, type, j = 0;\n\tconst struct nlattr *outer, *inner, *iter;\n\tuint8 flush = 0;\n\twl_pfn_significant_bssid_t *pbssid;\n\n\tsignificant_params = (gscan_swc_params_t *) kzalloc(len, GFP_KERNEL);\n\tif (!significant_params) {\n\t\tWL_ERR((\"Cannot Malloc mem to parse config commands size - %d bytes\\n\", len));\n\t\treturn -1;\n\t}\n\n\n\tnla_for_each_attr(iter, data, len, tmp2) {\n\t\ttype = nla_type(iter);\n\n\t\tswitch (type) {\n\t\tcase GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH:\n\t\t\tflush = nla_get_u8(iter);\n\t\t\tbreak;\n\t\tcase GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE:\n\t\t\tsignificant_params->rssi_window = nla_get_u16(iter);\n\t\t\tbreak;\n\t\tcase GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:\n\t\t\tsignificant_params->lost_ap_window = nla_get_u16(iter);\n\t\t\tbreak;\n\t\tcase GSCAN_ATTRIBUTE_MIN_BREACHING:\n\t\t\tsignificant_params->swc_threshold = nla_get_u16(iter);\n\t\t\tbreak;\n\t\tcase GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS:\n\t\t\tpbssid = significant_params->bssid_elem_list;\n\t\t\tnla_for_each_nested(outer, iter, tmp) {\n\t\t\t\tnla_for_each_nested(inner, outer, tmp1) {\n\t\t\t\t\tswitch (nla_type(inner)) {\n\t\t\t\t\tcase GSCAN_ATTRIBUTE_BSSID:\n\t\t\t\t\t\tmemcpy(&(pbssid[j].macaddr),\n\t\t\t\t\t\t       nla_data(inner),\n\t\t\t\t\t\t       ETHER_ADDR_LEN);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase GSCAN_ATTRIBUTE_RSSI_HIGH:\n\t\t\t\t\t\tpbssid[j].rssi_high_threshold =\n\t\t\t\t\t\t\t(int8) nla_get_u8(inner);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase GSCAN_ATTRIBUTE_RSSI_LOW:\n\t\t\t\t\t\tpbssid[j].rssi_low_threshold =\n\t\t\t\t\t\t\t(int8) nla_get_u8(inner);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tj++;\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t}\n\tsignificant_params->nbssid = j;\n\n\tif (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),\n\t\tDHD_PNO_SIGNIFICANT_SCAN_CFG_ID, significant_params, flush) < 0) {\n\t\tWL_ERR((\"Could not set GSCAN significant cfg\\n\"));\n\t\terr = -EINVAL;\n\t\tgoto exit;\n\t}\nexit:\n\tkfree(significant_params);\n\treturn err;\n}\n#endif /* GSCAN_SUPPORT */\n\n#if defined(RTT_SUPPORT) && 0\nvoid rtw_cfgvendor_rtt_evt(void *ctx, void *rtt_data)\n{\n\tstruct wireless_dev *wdev = (struct wireless_dev *)ctx;\n\tstruct wiphy *wiphy;\n\tstruct sk_buff *skb;\n\tuint32 tot_len = NLMSG_DEFAULT_SIZE, entry_len = 0;\n\tgfp_t kflags;\n\trtt_report_t *rtt_report = NULL;\n\trtt_result_t *rtt_result = NULL;\n\tstruct list_head *rtt_list;\n\twiphy = wdev->wiphy;\n\n\tWL_DBG((\"In\\n\"));\n\t/* Push the data to the skb */\n\tif (!rtt_data) {\n\t\tWL_ERR((\"rtt_data is NULL\\n\"));\n\t\tgoto exit;\n\t}\n\trtt_list = (struct list_head *)rtt_data;\n\tkflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;\n\t/* Alloc the SKB for vendor_event */\n\tskb = rtw_cfg80211_vendor_event_alloc(wiphy, wdev, tot_len, GOOGLE_RTT_COMPLETE_EVENT, kflags);\n\tif (!skb) {\n\t\tWL_ERR((\"skb alloc failed\"));\n\t\tgoto exit;\n\t}\n\t/* fill in the rtt results on each entry */\n\tlist_for_each_entry(rtt_result, rtt_list, list) {\n\t\tentry_len = 0;\n\t\tif (rtt_result->TOF_type == TOF_TYPE_ONE_WAY) {\n\t\t\tentry_len = sizeof(rtt_report_t);\n\t\t\trtt_report = kzalloc(entry_len, kflags);\n\t\t\tif (!rtt_report) {\n\t\t\t\tWL_ERR((\"rtt_report alloc failed\"));\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\trtt_report->addr = rtt_result->peer_mac;\n\t\t\trtt_report->num_measurement = 1; /* ONE SHOT */\n\t\t\trtt_report->status = rtt_result->err_code;\n\t\t\trtt_report->type = (rtt_result->TOF_type == TOF_TYPE_ONE_WAY) ? RTT_ONE_WAY : RTT_TWO_WAY;\n\t\t\trtt_report->peer = rtt_result->target_info->peer;\n\t\t\trtt_report->channel = rtt_result->target_info->channel;\n\t\t\trtt_report->rssi = rtt_result->avg_rssi;\n\t\t\t/* tx_rate */\n\t\t\trtt_report->tx_rate = rtt_result->tx_rate;\n\t\t\t/* RTT */\n\t\t\trtt_report->rtt = rtt_result->meanrtt;\n\t\t\trtt_report->rtt_sd = rtt_result->sdrtt;\n\t\t\t/* convert to centi meter */\n\t\t\tif (rtt_result->distance != 0xffffffff)\n\t\t\t\trtt_report->distance = (rtt_result->distance >> 2) * 25;\n\t\t\telse /* invalid distance */\n\t\t\t\trtt_report->distance = -1;\n\n\t\t\trtt_report->ts = rtt_result->ts;\n\t\t\tnla_append(skb, entry_len, rtt_report);\n\t\t\tkfree(rtt_report);\n\t\t}\n\t}\n\trtw_cfg80211_vendor_event(skb, kflags);\nexit:\n\treturn;\n}\n\nstatic int rtw_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev *wdev,\n\t\t\t\t       const void *data, int len)\n{\n\tint err = 0, rem, rem1, rem2, type;\n\trtt_config_params_t rtt_param;\n\trtt_target_info_t *rtt_target = NULL;\n\tconst struct nlattr *iter, *iter1, *iter2;\n\tint8 eabuf[ETHER_ADDR_STR_LEN];\n\tint8 chanbuf[CHANSPEC_STR_LEN];\n\tstruct bcm_cfg80211 *cfg = wiphy_priv(wiphy);\n\n\tWL_DBG((\"In\\n\"));\n\terr = dhd_dev_rtt_register_noti_callback(wdev->netdev, wdev, wl_cfgvendor_rtt_evt);\n\tif (err < 0) {\n\t\tWL_ERR((\"failed to register rtt_noti_callback\\n\"));\n\t\tgoto exit;\n\t}\n\tmemset(&rtt_param, 0, sizeof(rtt_param));\n\tnla_for_each_attr(iter, data, len, rem) {\n\t\ttype = nla_type(iter);\n\t\tswitch (type) {\n\t\tcase RTT_ATTRIBUTE_TARGET_CNT:\n\t\t\trtt_param.rtt_target_cnt = nla_get_u8(iter);\n\t\t\tif (rtt_param.rtt_target_cnt > RTT_MAX_TARGET_CNT) {\n\t\t\t\tWL_ERR((\"exceed max target count : %d\\n\",\n\t\t\t\t\trtt_param.rtt_target_cnt));\n\t\t\t\terr = BCME_RANGE;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase RTT_ATTRIBUTE_TARGET_INFO:\n\t\t\trtt_target = rtt_param.target_info;\n\t\t\tnla_for_each_nested(iter1, iter, rem1) {\n\t\t\t\tnla_for_each_nested(iter2, iter1, rem2) {\n\t\t\t\t\ttype = nla_type(iter2);\n\t\t\t\t\tswitch (type) {\n\t\t\t\t\tcase RTT_ATTRIBUTE_TARGET_MAC:\n\t\t\t\t\t\tmemcpy(&rtt_target->addr, nla_data(iter2), ETHER_ADDR_LEN);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase RTT_ATTRIBUTE_TARGET_TYPE:\n\t\t\t\t\t\trtt_target->type = nla_get_u8(iter2);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase RTT_ATTRIBUTE_TARGET_PEER:\n\t\t\t\t\t\trtt_target->peer = nla_get_u8(iter2);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase RTT_ATTRIBUTE_TARGET_CHAN:\n\t\t\t\t\t\tmemcpy(&rtt_target->channel, nla_data(iter2),\n\t\t\t\t\t\t       sizeof(rtt_target->channel));\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase RTT_ATTRIBUTE_TARGET_MODE:\n\t\t\t\t\t\trtt_target->continuous = nla_get_u8(iter2);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase RTT_ATTRIBUTE_TARGET_INTERVAL:\n\t\t\t\t\t\trtt_target->interval = nla_get_u32(iter2);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT:\n\t\t\t\t\t\trtt_target->measure_cnt = nla_get_u32(iter2);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase RTT_ATTRIBUTE_TARGET_NUM_PKT:\n\t\t\t\t\t\trtt_target->ftm_cnt = nla_get_u32(iter2);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase RTT_ATTRIBUTE_TARGET_NUM_RETRY:\n\t\t\t\t\t\trtt_target->retry_cnt = nla_get_u32(iter2);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t/* convert to chanspec value */\n\t\t\t\trtt_target->chanspec = dhd_rtt_convert_to_chspec(rtt_target->channel);\n\t\t\t\tif (rtt_target->chanspec == 0) {\n\t\t\t\t\tWL_ERR((\"Channel is not valid\\n\"));\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t\tWL_INFORM((\"Target addr %s, Channel : %s for RTT\\n\",\n\t\t\t\t\tbcm_ether_ntoa((const struct ether_addr *)&rtt_target->addr, eabuf),\n\t\t\t\t\twf_chspec_ntoa(rtt_target->chanspec, chanbuf)));\n\t\t\t\trtt_target++;\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t}\n\tWL_DBG((\"leave :target_cnt : %d\\n\", rtt_param.rtt_target_cnt));\n\tif (dhd_dev_rtt_set_cfg(bcmcfg_to_prmry_ndev(cfg), &rtt_param) < 0) {\n\t\tWL_ERR((\"Could not set RTT configuration\\n\"));\n\t\terr = -EINVAL;\n\t}\nexit:\n\treturn err;\n}\n\nstatic int rtw_cfgvendor_rtt_cancel_config(struct wiphy *wiphy, struct wireless_dev *wdev,\n\t\tconst void *data, int len)\n{\n\tint err = 0, rem, type, target_cnt = 0;\n\tconst struct nlattr *iter;\n\tstruct ether_addr *mac_list = NULL, *mac_addr = NULL;\n\tstruct bcm_cfg80211 *cfg = wiphy_priv(wiphy);\n\n\tnla_for_each_attr(iter, data, len, rem) {\n\t\ttype = nla_type(iter);\n\t\tswitch (type) {\n\t\tcase RTT_ATTRIBUTE_TARGET_CNT:\n\t\t\ttarget_cnt = nla_get_u8(iter);\n\t\t\tmac_list = (struct ether_addr *)kzalloc(target_cnt * ETHER_ADDR_LEN , GFP_KERNEL);\n\t\t\tif (mac_list == NULL) {\n\t\t\t\tWL_ERR((\"failed to allocate mem for mac list\\n\"));\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tmac_addr = &mac_list[0];\n\t\t\tbreak;\n\t\tcase RTT_ATTRIBUTE_TARGET_MAC:\n\t\t\tif (mac_addr)\n\t\t\t\tmemcpy(mac_addr++, nla_data(iter), ETHER_ADDR_LEN);\n\t\t\telse {\n\t\t\t\tWL_ERR((\"mac_list is NULL\\n\"));\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t\tif (dhd_dev_rtt_cancel_cfg(bcmcfg_to_prmry_ndev(cfg), mac_list, target_cnt) < 0) {\n\t\t\tWL_ERR((\"Could not cancel RTT configuration\\n\"));\n\t\t\terr = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t}\nexit:\n\tif (mac_list)\n\t\tkfree(mac_list);\n\treturn err;\n}\nstatic int rtw_cfgvendor_rtt_get_capability(struct wiphy *wiphy, struct wireless_dev *wdev,\n\t\tconst void *data, int len)\n{\n\tint err = 0;\n\tstruct bcm_cfg80211 *cfg = wiphy_priv(wiphy);\n\trtt_capabilities_t capability;\n\n\terr = dhd_dev_rtt_capability(bcmcfg_to_prmry_ndev(cfg), &capability);\n\tif (unlikely(err)) {\n\t\tWL_ERR((\"Vendor Command reply failed ret:%d\\n\", err));\n\t\tgoto exit;\n\t}\n\terr =  rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),\n\t\t\t\t\t    &capability, sizeof(capability));\n\n\tif (unlikely(err))\n\t\tWL_ERR((\"Vendor Command reply failed ret:%d\\n\", err));\nexit:\n\treturn err;\n}\n\n#endif /* RTT_SUPPORT */\n\n#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS\nenum {\n    LSTATS_SUBCMD_GET_INFO = ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START,\n\tLSTATS_SUBCMD_SET_INFO,\n\tLSTATS_SUBCMD_CLEAR_INFO,\n};\nstatic void LinkLayerStats(_adapter *padapter)\n{\n\tstruct xmit_priv\t\t*pxmitpriv = &(padapter->xmitpriv);\n\tstruct recv_priv\t\t*precvpriv = &(padapter->recvpriv);\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\tu32 ps_time, trx_total_time;\n\tu64 tx_bytes, rx_bytes, trx_total_bytes = 0;\n\tu64 tmp = 0;\n\t\n\tRTW_DBG(\"%s adapter type : %u\\n\", __func__, padapter->adapter_type);\n\n\ttx_bytes = 0;\n\trx_bytes = 0;\n\tps_time = 0;\n\ttrx_total_time = 0;\n\n\tif ( padapter->netif_up == _TRUE ) {\n\n\t\tpwrpriv->on_time = rtw_get_passing_time_ms(pwrpriv->radio_on_start_time);\n\n\t\tif (rtw_mi_check_fwstate(padapter, _FW_LINKED)) {\n\t\t\tif ( pwrpriv->bpower_saving == _TRUE ) {\n\t\t\t\tpwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);\n\t\t\t\tpwrpriv->pwr_saving_start_time = rtw_get_current_time();\n\t\t\t}\n\t\t} else {\t\t\n#ifdef CONFIG_IPS\n\t\t\tif ( pwrpriv->bpower_saving == _TRUE ) {\n\t\t\t\tpwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);\n\t\t\t\tpwrpriv->pwr_saving_start_time = rtw_get_current_time();\n\t\t\t}\n#else\n\t\t\tpwrpriv->pwr_saving_time = pwrpriv->on_time;\n#endif\n\t\t}\n\n\t\tps_time = pwrpriv->pwr_saving_time;\n\n\t\t/* Deviation caused by caculation start time */\n\t\tif ( ps_time > pwrpriv->on_time )\n\t\t\tps_time = pwrpriv->on_time;\n\n\t\ttx_bytes = pdvobjpriv->traffic_stat.last_tx_bytes;\n\t\trx_bytes = pdvobjpriv->traffic_stat.last_rx_bytes;\t\t\n\t\ttrx_total_bytes = tx_bytes + rx_bytes;\n\n\t\ttrx_total_time = pwrpriv->on_time - ps_time;\n\n\t\tif ( trx_total_bytes == 0) {\n\t\t\tpwrpriv->tx_time = 0;\n\t\t\tpwrpriv->rx_time = 0;\n\t\t} else {\n\n\t\t\t/* tx_time = (trx_total_time * tx_total_bytes) / trx_total_bytes; */\n\t\t\t/* rx_time = (trx_total_time * rx_total_bytes) / trx_total_bytes; */\n\n\t\t\ttmp = (tx_bytes * trx_total_time);\n\t\t\ttmp = rtw_division64(tmp, trx_total_bytes);\n\t\t\tpwrpriv->tx_time = tmp;\n\n\t\t\ttmp = (rx_bytes * trx_total_time);\n\t\t\ttmp = rtw_division64(tmp, trx_total_bytes);\n\t\t\tpwrpriv->rx_time = tmp;\t\t\n\n\t\t}\n\t\n\t}\n\telse {\n\t\t\tpwrpriv->on_time = 0;\n\t\t\tpwrpriv->tx_time = 0;\n\t\t\tpwrpriv->rx_time = 0;\t\n\t}\n\n#ifdef CONFIG_RTW_WIFI_HAL_DEBUG\n\tRTW_INFO(\"- tx_bytes : %llu rx_bytes : %llu total bytes : %llu\\n\", tx_bytes, rx_bytes, trx_total_bytes);\n\tRTW_INFO(\"- netif_up = %s, on_time : %u ms\\n\", padapter->netif_up ? \"1\":\"0\", pwrpriv->on_time);\n\tRTW_INFO(\"- pwr_saving_time : %u (%u) ms\\n\", pwrpriv->pwr_saving_time, ps_time);\n\tRTW_INFO(\"- trx_total_time : %u ms\\n\", trx_total_time);\t\t\n\tRTW_INFO(\"- tx_time : %u ms\\n\", pwrpriv->tx_time);\n\tRTW_INFO(\"- rx_time : %u ms\\n\", pwrpriv->rx_time);\t\n#endif /* CONFIG_RTW_WIFI_HAL_DEBUG */\n\n}\n\n#define DUMMY_TIME_STATICS 99\nstatic int rtw_cfgvendor_lstats_get_info(struct wiphy *wiphy,\t\n\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint err = 0;\n\t_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\twifi_radio_stat_internal *radio;\n\twifi_iface_stat *iface;\n\tchar *output;\n\n\toutput = rtw_malloc(sizeof(wifi_radio_stat_internal) + sizeof(wifi_iface_stat));\n\tif (output == NULL) {\n\t\tRTW_DBG(\"Allocate lstats info buffer fail!\\n\");\n\t}\n\n\tradio = (wifi_radio_stat_internal *)output;\n\n\tradio->num_channels = 0;\n\tradio->radio = 1;\n\n\t/* to get on_time, tx_time, rx_time */\n\tLinkLayerStats(padapter); \n\t\n\tradio->on_time = pwrpriv->on_time;\n\tradio->tx_time = pwrpriv->tx_time;\n\tradio->rx_time = pwrpriv->rx_time;\n\tradio->on_time_scan = 0;\n\tradio->on_time_nbd = 0;\n\tradio->on_time_gscan = 0;\n\tradio->on_time_pno_scan = 0;\n\tradio->on_time_hs20 = 0;\n\t#ifdef CONFIG_RTW_WIFI_HAL_DEBUG\n\tRTW_INFO(\"==== %s ====\\n\", __func__);\n\tRTW_INFO(\"radio->radio : %d\\n\", (radio->radio));\n\tRTW_INFO(\"pwrpriv->on_time : %u ms\\n\", (pwrpriv->on_time));\n\tRTW_INFO(\"pwrpriv->tx_time :  %u ms\\n\", (pwrpriv->tx_time));\n\tRTW_INFO(\"pwrpriv->rx_time :  %u ms\\n\", (pwrpriv->rx_time));\n\tRTW_INFO(\"radio->on_time :  %u ms\\n\", (radio->on_time));\n\tRTW_INFO(\"radio->tx_time :  %u ms\\n\", (radio->tx_time));\n\tRTW_INFO(\"radio->rx_time :  %u ms\\n\", (radio->rx_time));\n\t#endif /* CONFIG_RTW_WIFI_HAL_DEBUG */\n\t\n\tRTW_DBG(FUNC_NDEV_FMT\" %s\\n\", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);\n\terr =  rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), \n\t\toutput, sizeof(wifi_iface_stat) + sizeof(wifi_radio_stat_internal));\n\tif (unlikely(err))\n\t\tRTW_ERR(FUNC_NDEV_FMT\"Vendor Command reply failed ret:%d \\n\"\n\t\t\t, FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err);\n\trtw_mfree(output, sizeof(wifi_iface_stat) + sizeof(wifi_radio_stat_internal));\n\treturn err;\n}\nstatic int rtw_cfgvendor_lstats_set_info(struct wiphy *wiphy,\t\n\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint err = 0;\n\tRTW_INFO(\"%s\\n\", __func__);\n\treturn err;\n}\nstatic int rtw_cfgvendor_lstats_clear_info(struct wiphy *wiphy,\t\n\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint err = 0;\n\tRTW_INFO(\"%s\\n\", __func__);\n\treturn err;\n}\n#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */\n#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR\nstatic int rtw_cfgvendor_set_rssi_monitor(struct wiphy *wiphy,\n\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n        _adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));\n        struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n\n        struct recv_priv *precvpriv = &padapter->recvpriv;\n\tint err = 0, rem, type;\n        const struct nlattr *iter;\n\n        RTW_DBG(FUNC_NDEV_FMT\" %s\\n\", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);\n\n\tnla_for_each_attr(iter, data, len, rem) {\n\t\ttype = nla_type(iter);\n\n\t\tswitch (type) {\n        \t\tcase RSSI_MONITOR_ATTRIBUTE_MAX_RSSI:\n                                pwdev_priv->rssi_monitor_max = (s8)nla_get_u32(iter);;\n\t        \t\tbreak;\n\t\t        case RSSI_MONITOR_ATTRIBUTE_MIN_RSSI:\n                                pwdev_priv->rssi_monitor_min = (s8)nla_get_u32(iter);\n\t\t\t        break;\n        \t\tcase RSSI_MONITOR_ATTRIBUTE_START:\n                                pwdev_priv->rssi_monitor_enable = (u8)nla_get_u32(iter);\n\t        \t\tbreak;\n\t\t}\n\t}\n\n\treturn err;\n}\n\nvoid rtw_cfgvendor_rssi_monitor_evt(_adapter *padapter) {\n\tstruct wireless_dev *wdev =  padapter->rtw_wdev;\n\tstruct wiphy *wiphy= wdev->wiphy;\n        struct recv_priv *precvpriv = &padapter->recvpriv;\n\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tstruct\twlan_network\t*pcur_network = &pmlmepriv->cur_network;\n        struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);\n\tstruct sk_buff *skb;\n\tu32 tot_len = NLMSG_DEFAULT_SIZE;\n\tgfp_t kflags;\n        rssi_monitor_evt data ;\n        s8 rssi = precvpriv->rssi;\n\n        if (pwdev_priv->rssi_monitor_enable == 0 || check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE)\n                return;\n\n        if (rssi < pwdev_priv->rssi_monitor_max || rssi > pwdev_priv->rssi_monitor_min)\n                return;\n\n\tkflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;\n\n\t/* Alloc the SKB for vendor_event */\n\tskb = rtw_cfg80211_vendor_event_alloc(wiphy, wdev, tot_len, GOOGLE_RSSI_MONITOR_EVENT, kflags);\n\tif (!skb) {\n\t\tgoto exit;\n\t}\n\n        _rtw_memset(&data, 0, sizeof(data));\n\n        data.version = RSSI_MONITOR_EVT_VERSION;\n        data.cur_rssi = rssi;\n        _rtw_memcpy(data.BSSID, pcur_network->network.MacAddress, sizeof(mac_addr));\n\n        nla_append(skb, sizeof(data), &data);\n\n\trtw_cfg80211_vendor_event(skb, kflags);\nexit:\n\treturn;\n}\n#endif /* CONFIG_RTW_CFGVEDNOR_RSSIMONITR */\n\n#ifdef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER\nstatic int rtw_cfgvendor_logger_start_logging(struct wiphy *wiphy,\n\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint ret = 0, rem, type;\n\tchar ring_name[32] = {0};\n\tint log_level = 0, flags = 0, time_intval = 0, threshold = 0;\n\tconst struct nlattr *iter;\n\n\tnla_for_each_attr(iter, data, len, rem) {\n\t\ttype = nla_type(iter);\n\t\tswitch (type) {\n\t\t\tcase LOGGER_ATTRIBUTE_RING_NAME:\n\t\t\t\tstrncpy(ring_name, nla_data(iter),\n\t\t\t\t\tMIN(sizeof(ring_name) -1, nla_len(iter)));\n\t\t\t\tbreak;\n\t\t\tcase LOGGER_ATTRIBUTE_LOG_LEVEL:\n\t\t\t\tlog_level = nla_get_u32(iter);\n\t\t\t\tbreak;\n\t\t\tcase LOGGER_ATTRIBUTE_RING_FLAGS:\n\t\t\t\tflags = nla_get_u32(iter);\n\t\t\t\tbreak;\n\t\t\tcase LOGGER_ATTRIBUTE_LOG_TIME_INTVAL:\n\t\t\t\ttime_intval = nla_get_u32(iter);\n\t\t\t\tbreak;\n\t\t\tcase LOGGER_ATTRIBUTE_LOG_MIN_DATA_SIZE:\n\t\t\t\tthreshold = nla_get_u32(iter);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tRTW_ERR(\"Unknown type: %d\\n\", type);\n\t\t\t\tret = WIFI_ERROR_INVALID_ARGS;\n\t\t\t\tgoto exit;\n\t\t}\n\t}\n\nexit:\n\treturn ret;\n}\nstatic int rtw_cfgvendor_logger_get_feature(struct wiphy *wiphy,\n\tstruct wireless_dev *wdev, const void *data, int len)\n{\n\tint err = 0;\n\tu32 supported_features = 0;\n\n\terr =  rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), &supported_features, sizeof(supported_features));\n\n\tif (unlikely(err))\n\t\tRTW_ERR(FUNC_NDEV_FMT\" Vendor Command reply failed ret:%d\\n\"\n\t\t\t, FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err);\n\n\treturn err;\n}\nstatic int rtw_cfgvendor_logger_get_version(struct wiphy *wiphy,\n\tstruct wireless_dev *wdev, const void *data, int len)\n{\n\t_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));\n\tHAL_DATA_TYPE *hal = GET_HAL_DATA(padapter);\n\tint ret = 0, rem, type;\n\tint buf_len = 1024;\n\tchar *buf_ptr;\n\tconst struct nlattr *iter;\n\tgfp_t kflags;\n\n\tkflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;\n\tbuf_ptr = kzalloc(buf_len, kflags);\n\tif (!buf_ptr) {\n\t\tRTW_ERR(\"failed to allocate the buffer for version n\");\n\t\tret = -ENOMEM;\n\t\tgoto exit;\n\t}\n\tnla_for_each_attr(iter, data, len, rem) {\n\t\ttype = nla_type(iter);\n\t\tswitch (type) {\n\t\t\tcase LOGGER_ATTRIBUTE_GET_DRIVER:\n\t\t\t\tmemcpy(buf_ptr, DRIVERVERSION, strlen(DRIVERVERSION)+1);\n\t\t\t\tbreak;\n\t\t\tcase LOGGER_ATTRIBUTE_GET_FW:\n\t\t\t\tsprintf(buf_ptr, \"v%d.%d\", hal->firmware_version, hal->firmware_sub_version);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tRTW_ERR(\"Unknown type: %d\\n\", type);\n\t\t\t\tret = -EINVAL;\n\t\t\t\tgoto exit;\n\t\t}\n\t}\n\tif (ret < 0) {\n\t\tRTW_ERR(\"failed to get the version %d\\n\", ret);\n\t\tgoto exit;\n\t}\n\n\n\tret =  rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), buf_ptr, strlen(buf_ptr));\nexit:\n\tkfree(buf_ptr);\n\treturn ret;\n}\n\nstatic int rtw_cfgvendor_logger_get_ring_status(struct wiphy *wiphy,\n\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint ret = 0;\n\tint ring_id;\n\tchar ring_buf_name[] = \"RTW_RING_BUFFER\";\n\n\tstruct sk_buff *skb;\n\twifi_ring_buffer_status ring_status;\n\n\n\t_rtw_memcpy(ring_status.name, ring_buf_name, strlen(ring_buf_name)+1);\n\tring_status.ring_id = 1;\n\t/* Alloc the SKB for vendor_event */\n\tskb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy,\n\t\tsizeof(wifi_ring_buffer_status));\n\tif (!skb) {\n\t\tRTW_ERR(\"skb allocation is failed\\n\");\n\t\tret = FAIL;\n\t\tgoto exit;\n\t}\n\n\tnla_put_u32(skb, LOGGER_ATTRIBUTE_RING_NUM, 1);\n\tnla_put(skb, LOGGER_ATTRIBUTE_RING_STATUS, sizeof(wifi_ring_buffer_status),\n\t\t\t\t&ring_status);\n\tret = cfg80211_vendor_cmd_reply(skb);\n\n\tif (ret) {\n\t\tRTW_ERR(\"Vendor Command reply failed ret:%d \\n\", ret);\n\t}\nexit:\n\treturn ret;\n}\n\nstatic int rtw_cfgvendor_logger_get_ring_data(struct wiphy *wiphy,\n\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint ret = 0, rem, type;\n\tchar ring_name[32] = {0};\n\tconst struct nlattr *iter;\n\n\tnla_for_each_attr(iter, data, len, rem) {\n\t\ttype = nla_type(iter);\n\t\tswitch (type) {\n\t\t\tcase LOGGER_ATTRIBUTE_RING_NAME:\n\t\t\t\tstrncpy(ring_name, nla_data(iter),\n\t\t\t\t\tMIN(sizeof(ring_name) -1, nla_len(iter)));\n\t\t\t\tRTW_INFO(\" %s LOGGER_ATTRIBUTE_RING_NAME : %s\\n\", __func__, ring_name);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tRTW_ERR(\"Unknown type: %d\\n\", type);\n\t\t\t\treturn ret;\n\t\t}\n\t}\n\n\n\treturn ret;\n}\n\nstatic int rtw_cfgvendor_logger_get_firmware_memory_dump(struct wiphy *wiphy,\n\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint ret = WIFI_ERROR_NOT_SUPPORTED;\n\n\treturn ret;\n}\n\nstatic int rtw_cfgvendor_logger_start_pkt_fate_monitoring(struct wiphy *wiphy,\n\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint ret = WIFI_SUCCESS;\n\n\treturn ret;\n}\n\nstatic int rtw_cfgvendor_logger_get_tx_pkt_fates(struct wiphy *wiphy,\n\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint ret = WIFI_SUCCESS;\n\n\treturn ret;\n}\n\nstatic int rtw_cfgvendor_logger_get_rx_pkt_fates(struct wiphy *wiphy,\n\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint ret = WIFI_SUCCESS;\n\n\treturn ret;\n}\n\n#endif /* CONFIG_RTW_CFGVENDOR_WIFI_LOGGER */\n#ifdef CONFIG_RTW_WIFI_HAL\n#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI\n\n#ifndef ETHER_ISMULTI\n#define ETHER_ISMULTI(ea) (((const u8 *)(ea))[0] & 1)\n#endif\n\n\nstatic u8 null_addr[ETH_ALEN] = {0};\nstatic void rtw_hal_random_gen_mac_addr(u8 *mac_addr)\n{\n\tdo {\n\t\tget_random_bytes(&mac_addr[3], ETH_ALEN-3);\n\t\tif (memcmp(mac_addr, null_addr, ETH_ALEN) != 0)\n\t\t\tbreak;\n\t} while(1);\n}\n\nvoid rtw_hal_pno_random_gen_mac_addr(PADAPTER adapter)\n{\n\tu8 mac_addr[ETH_ALEN];\n\tstruct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);\n\n\tmemcpy(mac_addr, pwdev_priv->pno_mac_addr, ETH_ALEN);\n\tif (mac_addr[0] == 0xFF) return;\n\trtw_hal_random_gen_mac_addr(mac_addr);\n\tmemcpy(pwdev_priv->pno_mac_addr, mac_addr, ETH_ALEN);\n#ifdef CONFIG_RTW_DEBUG\n\tprint_hex_dump(KERN_DEBUG, \"pno_mac_addr: \",\n\t\t       DUMP_PREFIX_OFFSET, 16, 1, pwdev_priv->pno_mac_addr,\n\t\t       ETH_ALEN, 1);\n#endif\n}\n\nvoid rtw_hal_set_hw_mac_addr(PADAPTER adapter, u8 *mac_addr)\n{\n\trtw_ps_deny(adapter, PS_DENY_IOCTL);\n\tLeaveAllPowerSaveModeDirect(adapter);\n\n\trtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, mac_addr);\n#ifdef CONFIG_RTW_DEBUG\n\trtw_hal_dump_macaddr(RTW_DBGDUMP, adapter);\n#endif\n\trtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);\n}\n\nstatic int rtw_cfgvendor_set_rand_mac_oui(struct wiphy *wiphy,\n\t\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n\tint err = 0;\n\tPADAPTER adapter;\n\tvoid *devaddr;\n\tstruct net_device *netdev;\n\tint type, mac_len;\n\tu8 pno_random_mac_oui[3];\n\tu8 mac_addr[ETH_ALEN] = {0};\n\tstruct pwrctrl_priv *pwrctl;\n\tstruct rtw_wdev_priv *pwdev_priv;\n\n\ttype = nla_type(data);\n\tmac_len = nla_len(data);\n\tif (mac_len != 3) {\n\t\tRTW_ERR(\"%s oui len error %d != 3\\n\", __func__, mac_len);\n\t\treturn -1;\n\t}\n\n\tif (type == ANDR_WIFI_ATTRIBUTE_RANDOM_MAC_OUI) {\n\t\tmemcpy(pno_random_mac_oui, nla_data(data), 3);\n\t\tprint_hex_dump(KERN_DEBUG, \"pno_random_mac_oui: \",\n\t\t\t       DUMP_PREFIX_OFFSET, 16, 1, pno_random_mac_oui,\n\t\t\t       3, 1);\n\n\t\tif (ETHER_ISMULTI(pno_random_mac_oui)) {\n\t\t\tpr_err(\"%s: oui is multicast address\\n\", __func__);\n\t\t\treturn -1;\n\t\t}\n\n\t\tadapter = wiphy_to_adapter(wiphy);\n\t\tif (adapter == NULL) {\n\t\t\tpr_err(\"%s: wiphy_to_adapter == NULL\\n\", __func__);\n\t\t\treturn -1;\n\t\t}\n\n\t\tpwdev_priv = adapter_wdev_data(adapter);\n\n\t\tmemcpy(mac_addr, pno_random_mac_oui, 3);\n\t\trtw_hal_random_gen_mac_addr(mac_addr);\n\t\tmemcpy(pwdev_priv->pno_mac_addr, mac_addr, ETH_ALEN);\n#ifdef CONFIG_RTW_DEBUG\n\t\tprint_hex_dump(KERN_DEBUG, \"pno_mac_addr: \",\n\t\t\t       DUMP_PREFIX_OFFSET, 16, 1, pwdev_priv->pno_mac_addr,\n\t\t\t       ETH_ALEN, 1);\n#endif\n\t} else {\n\t\tRTW_ERR(\"%s oui type error %x != 0x2\\n\", __func__, type);\n\t\terr = -1;\n\t}\n\n\n\treturn err;\n}\n\n#endif\n\n\nstatic int rtw_cfgvendor_set_nodfs_flag(struct wiphy *wiphy,\n\tstruct wireless_dev *wdev, const void *data, int len)\n{\n\tint err = 0;\t\n\tint type;\n\tu32 nodfs = 0;\n\t_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));\n\n\tRTW_DBG(FUNC_NDEV_FMT\" %s\\n\", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);\n\n\ttype = nla_type(data);\n\tif (type == ANDR_WIFI_ATTRIBUTE_NODFS_SET) {\n\t\tnodfs = nla_get_u32(data);\n\t\tadapter_to_dvobj(padapter)->nodfs = nodfs;\n\t} else {\n\t\terr = -EINVAL;\n\t}\n\n\tRTW_INFO(\"%s nodfs=%d, err=%d\\n\", __func__, nodfs, err);\n\t\n\treturn err;\n}\n\nstatic int rtw_cfgvendor_set_country(struct wiphy *wiphy,\n\tstruct wireless_dev *wdev, const void  *data, int len)\n{\n#define CNTRY_BUF_SZ\t4\t/* Country string is 3 bytes + NUL */\n\tint err = 0, rem, type;\n\tchar country_code[CNTRY_BUF_SZ] = {0};\n\tconst struct nlattr *iter;\n\t_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));\n\n\tRTW_DBG(FUNC_NDEV_FMT\" %s\\n\", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);\n\n\tnla_for_each_attr(iter, data, len, rem) {\n\t\ttype = nla_type(iter);\n\t\tswitch (type) {\n\t\t\tcase ANDR_WIFI_ATTRIBUTE_COUNTRY:\n\t\t\t\t_rtw_memcpy(country_code, nla_data(iter),\n\t\t\t\t\tMIN(nla_len(iter), CNTRY_BUF_SZ));\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tRTW_ERR(\"Unknown type: %d\\n\", type);\n\t\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\tRTW_INFO(\"%s country_code:\\\"%c%c\\\" \\n\", __func__, country_code[0], country_code[1]);\n\n\trtw_set_country(padapter, country_code);\n\n\treturn err;\n}\n\nstatic int rtw_cfgvendor_set_nd_offload(struct wiphy *wiphy,\n\tstruct wireless_dev *wdev, const void *data, int len)\n{\n\tint err = 0;\t\n\tint type;\n\tu8 nd_en = 0;\n\t_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));\n\n\tRTW_DBG(FUNC_NDEV_FMT\" %s\\n\", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);\n\n\ttype = nla_type(data);\n\tif (type == ANDR_WIFI_ATTRIBUTE_ND_OFFLOAD_VALUE) {\n\t\tnd_en = nla_get_u8(data);\n\t\t/* ND has been enabled when wow is enabled */\n\t} else {\n\t\terr = -EINVAL;\n\t}\n\n\tRTW_INFO(\"%s nd_en=%d, err=%d\\n\", __func__, nd_en, err);\n\t\n\treturn err;\n}\n#endif /* CONFIG_RTW_WIFI_HAL */\n\nstatic const struct wiphy_vendor_command rtw_vendor_cmds[] = {\n#if defined(GSCAN_SUPPORT) && 0\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = GSCAN_SUBCMD_GET_CAPABILITIES\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_gscan_get_capabilities\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = GSCAN_SUBCMD_SET_CONFIG\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_set_scan_cfg\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_set_batch_scan_cfg\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = GSCAN_SUBCMD_ENABLE_GSCAN\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_initiate_gscan\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_enable_full_scan_result\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = GSCAN_SUBCMD_SET_HOTLIST\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_hotlist_cfg\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_significant_change_cfg\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_gscan_get_batch_results\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_gscan_get_channel_list\n\t},\n#endif /* GSCAN_SUPPORT */\n#if defined(RTT_SUPPORT) && 0\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = RTT_SUBCMD_SET_CONFIG\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_rtt_set_config\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = RTT_SUBCMD_CANCEL_CONFIG\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_rtt_cancel_config\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = RTT_SUBCMD_GETCAPABILITY\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_rtt_get_capability\n\t},\n#endif /* RTT_SUPPORT */\n#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = LSTATS_SUBCMD_GET_INFO\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_lstats_get_info\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = LSTATS_SUBCMD_SET_INFO\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_lstats_set_info\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = LSTATS_SUBCMD_CLEAR_INFO\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_lstats_clear_info\n\t},\n#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */\n#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR\n        {\n                {\n                        .vendor_id = OUI_GOOGLE,\n                        .subcmd = WIFI_SUBCMD_SET_RSSI_MONITOR\n                },\n                .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n                .doit = rtw_cfgvendor_set_rssi_monitor\n        },\n#endif /* CONFIG_RTW_CFGVEDNOR_RSSIMONITOR */\n#ifdef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = LOGGER_START_LOGGING\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_logger_start_logging\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = LOGGER_GET_FEATURE\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_logger_get_feature\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = LOGGER_GET_VER\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_logger_get_version\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = LOGGER_GET_RING_STATUS\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_logger_get_ring_status\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = LOGGER_GET_RING_DATA\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_logger_get_ring_data\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = LOGGER_TRIGGER_MEM_DUMP\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_logger_get_firmware_memory_dump\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = LOGGER_START_PKT_FATE_MONITORING\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_logger_start_pkt_fate_monitoring\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = LOGGER_GET_TX_PKT_FATES\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_logger_get_tx_pkt_fates\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = LOGGER_GET_RX_PKT_FATES\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_logger_get_rx_pkt_fates\n\t},\t\n#endif /* CONFIG_RTW_CFGVENDOR_WIFI_LOGGER */\n#ifdef CONFIG_RTW_WIFI_HAL\n#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = WIFI_SUBCMD_SET_PNO_RANDOM_MAC_OUI\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_set_rand_mac_oui\n\t},\n#endif\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = WIFI_SUBCMD_NODFS_SET\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_set_nodfs_flag\n\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = WIFI_SUBCMD_SET_COUNTRY_CODE\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_set_country\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = WIFI_SUBCMD_CONFIG_ND_OFFLOAD\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_set_nd_offload\n\t},\n#endif /* CONFIG_RTW_WIFI_HAL */\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = WIFI_SUBCMD_GET_FEATURE_SET\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_get_feature_set\n\t},\n\t{\n\t\t{\n\t\t\t.vendor_id = OUI_GOOGLE,\n\t\t\t.subcmd = WIFI_SUBCMD_GET_FEATURE_SET_MATRIX\n\t\t},\n\t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n\t\t.doit = rtw_cfgvendor_get_feature_set_matrix\n\t}\n};\n\nstatic const struct  nl80211_vendor_cmd_info rtw_vendor_events[] = {\n#if defined(GSCAN_SUPPORT) && 0\n\t{ OUI_GOOGLE, GSCAN_EVENT_SIGNIFICANT_CHANGE_RESULTS },\n\t{ OUI_GOOGLE, GSCAN_EVENT_HOTLIST_RESULTS_FOUND },\n\t{ OUI_GOOGLE, GSCAN_EVENT_SCAN_RESULTS_AVAILABLE },\n\t{ OUI_GOOGLE, GSCAN_EVENT_FULL_SCAN_RESULTS },\n#endif /* GSCAN_SUPPORT */\n#if defined(RTT_SUPPORT) && 0\n\t{ OUI_GOOGLE, RTT_EVENT_COMPLETE },\n#endif /* RTT_SUPPORT */\n\n#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR\n\t{ OUI_GOOGLE, GOOGLE_RSSI_MONITOR_EVENT },\n#endif /* RTW_CFGVEDNOR_RSSIMONITR */\n\n#if defined(GSCAN_SUPPORT) && 0\n\t{ OUI_GOOGLE, GSCAN_EVENT_COMPLETE_SCAN },\n\t{ OUI_GOOGLE, GSCAN_EVENT_HOTLIST_RESULTS_LOST }\n#endif /* GSCAN_SUPPORT */\n};\n\nint rtw_cfgvendor_attach(struct wiphy *wiphy)\n{\n\n\tRTW_INFO(\"Register RTW cfg80211 vendor cmd(0x%x) interface\\n\", NL80211_CMD_VENDOR);\n\n\twiphy->vendor_commands\t= rtw_vendor_cmds;\n\twiphy->n_vendor_commands = ARRAY_SIZE(rtw_vendor_cmds);\n\twiphy->vendor_events\t= rtw_vendor_events;\n\twiphy->n_vendor_events\t= ARRAY_SIZE(rtw_vendor_events);\n\n\treturn 0;\n}\n\nint rtw_cfgvendor_detach(struct wiphy *wiphy)\n{\n\tRTW_INFO(\"Vendor: Unregister RTW cfg80211 vendor interface\\n\");\n\n\twiphy->vendor_commands  = NULL;\n\twiphy->vendor_events    = NULL;\n\twiphy->n_vendor_commands = 0;\n\twiphy->n_vendor_events  = 0;\n\n\treturn 0;\n}\n#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */\n\n#endif /* CONFIG_IOCTL_CFG80211 */\n"
  },
  {
    "path": "os_dep/linux/rtw_cfgvendor.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifndef _RTW_CFGVENDOR_H_\n#define _RTW_CFGVENDOR_H_\n\n#define OUI_GOOGLE  0x001A11\n#define ATTRIBUTE_U32_LEN                  (NLA_HDRLEN  + 4)\n#define VENDOR_ID_OVERHEAD                 ATTRIBUTE_U32_LEN\n#define VENDOR_SUBCMD_OVERHEAD             ATTRIBUTE_U32_LEN\n#define VENDOR_DATA_OVERHEAD               (NLA_HDRLEN)\n\n#define SCAN_RESULTS_COMPLETE_FLAG_LEN       ATTRIBUTE_U32_LEN\n#define SCAN_INDEX_HDR_LEN                   (NLA_HDRLEN)\n#define SCAN_ID_HDR_LEN                      ATTRIBUTE_U32_LEN\n#define SCAN_FLAGS_HDR_LEN                   ATTRIBUTE_U32_LEN\n#define GSCAN_NUM_RESULTS_HDR_LEN            ATTRIBUTE_U32_LEN\n#define GSCAN_RESULTS_HDR_LEN                (NLA_HDRLEN)\n#define GSCAN_BATCH_RESULT_HDR_LEN  (SCAN_INDEX_HDR_LEN + SCAN_ID_HDR_LEN + \\\n\t\t\t\t     SCAN_FLAGS_HDR_LEN + \\\n\t\t\t\t     GSCAN_NUM_RESULTS_HDR_LEN + \\\n\t\t\t\t     GSCAN_RESULTS_HDR_LEN)\n\n#define VENDOR_REPLY_OVERHEAD       (VENDOR_ID_OVERHEAD + \\\n\t\t\t\t     VENDOR_SUBCMD_OVERHEAD + \\\n\t\t\t\t     VENDOR_DATA_OVERHEAD)\ntypedef enum {\n    /* don't use 0 as a valid subcommand */\n    VENDOR_NL80211_SUBCMD_UNSPECIFIED,\n\n    /* define all vendor startup commands between 0x0 and 0x0FFF */\n    VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001,\n    VENDOR_NL80211_SUBCMD_RANGE_END   = 0x0FFF,\n\n    /* define all GScan related commands between 0x1000 and 0x10FF */\n    ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000,\n    ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END   = 0x10FF,\n\n    /* define all NearbyDiscovery related commands between 0x1100 and 0x11FF */\n    ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1100,\n    ANDROID_NL80211_SUBCMD_NBD_RANGE_END   = 0x11FF,\n\n    /* define all RTT related commands between 0x1100 and 0x11FF */\n    ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100,\n    ANDROID_NL80211_SUBCMD_RTT_RANGE_END   = 0x11FF,\n\n    ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200,\n    ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END   = 0x12FF,\n\n    /* define all Logger related commands between 0x1400 and 0x14FF */\n    ANDROID_NL80211_SUBCMD_DEBUG_RANGE_START = 0x1400,\n    ANDROID_NL80211_SUBCMD_DEBUG_RANGE_END   = 0x14FF,\n\n    /* define all wifi offload related commands between 0x1600 and 0x16FF */\n    ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_START = 0x1600,\n    ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_END   = 0x16FF,\n\n    /* define all NAN related commands between 0x1700 and 0x17FF */\n    ANDROID_NL80211_SUBCMD_NAN_RANGE_START = 0x1700,\n    ANDROID_NL80211_SUBCMD_NAN_RANGE_END   = 0x17FF,\n\n    /* define all Android Packet Filter related commands between 0x1800 and 0x18FF */\n    ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_START = 0x1800,\n    ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_END   = 0x18FF,\n\n    /* This is reserved for future usage */\n\n} ANDROID_VENDOR_SUB_COMMAND;\n\nenum rtw_vendor_subcmd {\n    GSCAN_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START,\n\n    GSCAN_SUBCMD_SET_CONFIG,                            /* 0x1001 */\n\n    GSCAN_SUBCMD_SET_SCAN_CONFIG,                       /* 0x1002 */\n    GSCAN_SUBCMD_ENABLE_GSCAN,                          /* 0x1003 */\n    GSCAN_SUBCMD_GET_SCAN_RESULTS,                      /* 0x1004 */\n    GSCAN_SUBCMD_SCAN_RESULTS,                          /* 0x1005 */\n\n    GSCAN_SUBCMD_SET_HOTLIST,                           /* 0x1006 */\n\n    GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG,         /* 0x1007 */\n    GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS,              /* 0x1008 */\n    GSCAN_SUBCMD_GET_CHANNEL_LIST,                       /* 0x1009 */\n\n    WIFI_SUBCMD_GET_FEATURE_SET,                         /* 0x100A */\n    WIFI_SUBCMD_GET_FEATURE_SET_MATRIX,                  /* 0x100B */\n    WIFI_SUBCMD_SET_PNO_RANDOM_MAC_OUI,                  /* 0x100C */\n    WIFI_SUBCMD_NODFS_SET,                               /* 0x100D */\n    WIFI_SUBCMD_SET_COUNTRY_CODE,                             /* 0x100E */\n    /* Add more sub commands here */\n    GSCAN_SUBCMD_SET_EPNO_SSID,                          /* 0x100F */\n\n    WIFI_SUBCMD_SET_SSID_WHITE_LIST,                    /* 0x1010 */\n    WIFI_SUBCMD_SET_ROAM_PARAMS,                        /* 0x1011 */\n    WIFI_SUBCMD_ENABLE_LAZY_ROAM,                       /* 0x1012 */\n    WIFI_SUBCMD_SET_BSSID_PREF,                         /* 0x1013 */\n    WIFI_SUBCMD_SET_BSSID_BLACKLIST,                     /* 0x1014 */\n\n    GSCAN_SUBCMD_ANQPO_CONFIG,                          /* 0x1015 */\n    WIFI_SUBCMD_SET_RSSI_MONITOR,                       /* 0x1016 */\n    WIFI_SUBCMD_CONFIG_ND_OFFLOAD,                      /* 0x1017 */\n    /* Add more sub commands here */\n\n    GSCAN_SUBCMD_MAX,\n\n\tRTT_SUBCMD_SET_CONFIG = ANDROID_NL80211_SUBCMD_RTT_RANGE_START,\n\tRTT_SUBCMD_CANCEL_CONFIG,\n\tRTT_SUBCMD_GETCAPABILITY,\n\n    APF_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_START,\n    APF_SUBCMD_SET_FILTER,\n    \n    LOGGER_START_LOGGING = ANDROID_NL80211_SUBCMD_DEBUG_RANGE_START,\n    LOGGER_TRIGGER_MEM_DUMP,\n    LOGGER_GET_MEM_DUMP,\n    LOGGER_GET_VER,\n    LOGGER_GET_RING_STATUS,\n    LOGGER_GET_RING_DATA,\n    LOGGER_GET_FEATURE,\n    LOGGER_RESET_LOGGING,\n    LOGGER_TRIGGER_DRIVER_MEM_DUMP,\n    LOGGER_GET_DRIVER_MEM_DUMP,\n    LOGGER_START_PKT_FATE_MONITORING,\n    LOGGER_GET_TX_PKT_FATES,\n    LOGGER_GET_RX_PKT_FATES,\n\n\tVENDOR_SUBCMD_MAX\n};\n\nenum gscan_attributes {\n\tGSCAN_ATTRIBUTE_NUM_BUCKETS = 10,\n\tGSCAN_ATTRIBUTE_BASE_PERIOD,\n\tGSCAN_ATTRIBUTE_BUCKETS_BAND,\n\tGSCAN_ATTRIBUTE_BUCKET_ID,\n\tGSCAN_ATTRIBUTE_BUCKET_PERIOD,\n\tGSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS,\n\tGSCAN_ATTRIBUTE_BUCKET_CHANNELS,\n\tGSCAN_ATTRIBUTE_NUM_AP_PER_SCAN,\n\tGSCAN_ATTRIBUTE_REPORT_THRESHOLD,\n\tGSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE,\n\tGSCAN_ATTRIBUTE_BAND = GSCAN_ATTRIBUTE_BUCKETS_BAND,\n\n\tGSCAN_ATTRIBUTE_ENABLE_FEATURE = 20,\n\tGSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE,\n\tGSCAN_ATTRIBUTE_FLUSH_FEATURE,\n\tGSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS,\n\tGSCAN_ATTRIBUTE_REPORT_EVENTS,\n\t/* remaining reserved for additional attributes */\n\tGSCAN_ATTRIBUTE_NUM_OF_RESULTS = 30,\n\tGSCAN_ATTRIBUTE_FLUSH_RESULTS,\n\tGSCAN_ATTRIBUTE_SCAN_RESULTS,                       /* flat array of wifi_scan_result */\n\tGSCAN_ATTRIBUTE_SCAN_ID,                            /* indicates scan number */\n\tGSCAN_ATTRIBUTE_SCAN_FLAGS,                         /* indicates if scan was aborted */\n\tGSCAN_ATTRIBUTE_AP_FLAGS,                           /* flags on significant change event */\n\tGSCAN_ATTRIBUTE_NUM_CHANNELS,\n\tGSCAN_ATTRIBUTE_CHANNEL_LIST,\n\n\t/* remaining reserved for additional attributes */\n\n\tGSCAN_ATTRIBUTE_SSID = 40,\n\tGSCAN_ATTRIBUTE_BSSID,\n\tGSCAN_ATTRIBUTE_CHANNEL,\n\tGSCAN_ATTRIBUTE_RSSI,\n\tGSCAN_ATTRIBUTE_TIMESTAMP,\n\tGSCAN_ATTRIBUTE_RTT,\n\tGSCAN_ATTRIBUTE_RTTSD,\n\n\t/* remaining reserved for additional attributes */\n\n\tGSCAN_ATTRIBUTE_HOTLIST_BSSIDS = 50,\n\tGSCAN_ATTRIBUTE_RSSI_LOW,\n\tGSCAN_ATTRIBUTE_RSSI_HIGH,\n\tGSCAN_ATTRIBUTE_HOSTLIST_BSSID_ELEM,\n\tGSCAN_ATTRIBUTE_HOTLIST_FLUSH,\n\n\t/* remaining reserved for additional attributes */\n\tGSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE = 60,\n\tGSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE,\n\tGSCAN_ATTRIBUTE_MIN_BREACHING,\n\tGSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS,\n\tGSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH,\n\tGSCAN_ATTRIBUTE_MAX\n};\n\nenum gscan_bucket_attributes {\n\tGSCAN_ATTRIBUTE_CH_BUCKET_1,\n\tGSCAN_ATTRIBUTE_CH_BUCKET_2,\n\tGSCAN_ATTRIBUTE_CH_BUCKET_3,\n\tGSCAN_ATTRIBUTE_CH_BUCKET_4,\n\tGSCAN_ATTRIBUTE_CH_BUCKET_5,\n\tGSCAN_ATTRIBUTE_CH_BUCKET_6,\n\tGSCAN_ATTRIBUTE_CH_BUCKET_7\n};\n\nenum gscan_ch_attributes {\n\tGSCAN_ATTRIBUTE_CH_ID_1,\n\tGSCAN_ATTRIBUTE_CH_ID_2,\n\tGSCAN_ATTRIBUTE_CH_ID_3,\n\tGSCAN_ATTRIBUTE_CH_ID_4,\n\tGSCAN_ATTRIBUTE_CH_ID_5,\n\tGSCAN_ATTRIBUTE_CH_ID_6,\n\tGSCAN_ATTRIBUTE_CH_ID_7\n};\n\nenum wifi_rssi_monitor_attr {\n        RSSI_MONITOR_ATTRIBUTE_MAX_RSSI,\n        RSSI_MONITOR_ATTRIBUTE_MIN_RSSI,\n        RSSI_MONITOR_ATTRIBUTE_START,\n};\n\n\nenum rtt_attributes {\n\tRTT_ATTRIBUTE_TARGET_CNT,\n\tRTT_ATTRIBUTE_TARGET_INFO,\n\tRTT_ATTRIBUTE_TARGET_MAC,\n\tRTT_ATTRIBUTE_TARGET_TYPE,\n\tRTT_ATTRIBUTE_TARGET_PEER,\n\tRTT_ATTRIBUTE_TARGET_CHAN,\n\tRTT_ATTRIBUTE_TARGET_MODE,\n\tRTT_ATTRIBUTE_TARGET_INTERVAL,\n\tRTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT,\n\tRTT_ATTRIBUTE_TARGET_NUM_PKT,\n\tRTT_ATTRIBUTE_TARGET_NUM_RETRY\n};\n\nenum logger_attributes {\n\tLOGGER_ATTRIBUTE_GET_DRIVER,\n\tLOGGER_ATTRIBUTE_GET_FW,\n\tLOGGER_ATTRIBUTE_RING_ID,\n\tLOGGER_ATTRIBUTE_RING_NAME,\n\tLOGGER_ATTRIBUTE_RING_FLAGS,\n\tLOGGER_ATTRIBUTE_LOG_LEVEL,\n\tLOGGER_ATTRIBUTE_LOG_TIME_INTVAL,\n\tLOGGER_ATTRIBUTE_LOG_MIN_DATA_SIZE,\n\tLOGGER_ATTRIBUTE_FW_DUMP_LEN,\n\tLOGGER_ATTRIBUTE_FW_DUMP_DATA,\n\tLOGGERG_ATTRIBUTE_RING_DATA,\n\tLOGGER_ATTRIBUTE_RING_STATUS,\n\tLOGGER_ATTRIBUTE_RING_NUM\n};\ntypedef enum rtw_vendor_event {\n    RTK_RESERVED1,\n    RTK_RESERVED2,\n    GSCAN_EVENT_SIGNIFICANT_CHANGE_RESULTS ,\n    GSCAN_EVENT_HOTLIST_RESULTS_FOUND,\n    GSCAN_EVENT_SCAN_RESULTS_AVAILABLE,\n    GSCAN_EVENT_FULL_SCAN_RESULTS,\n    RTT_EVENT_COMPLETE,\n    GSCAN_EVENT_COMPLETE_SCAN,\n    GSCAN_EVENT_HOTLIST_RESULTS_LOST,\n    GSCAN_EVENT_EPNO_EVENT,\n    GOOGLE_DEBUG_RING_EVENT,\n    GOOGLE_DEBUG_MEM_DUMP_EVENT,\n    GSCAN_EVENT_ANQPO_HOTSPOT_MATCH,\n    GOOGLE_RSSI_MONITOR_EVENT\n} rtw_vendor_event_t;\n\nenum andr_wifi_feature_set_attr {\n\tANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET,\n\tANDR_WIFI_ATTRIBUTE_FEATURE_SET,\n\tANDR_WIFI_ATTRIBUTE_RANDOM_MAC_OUI,\n\tANDR_WIFI_ATTRIBUTE_NODFS_SET,\n\tANDR_WIFI_ATTRIBUTE_COUNTRY,\n\tANDR_WIFI_ATTRIBUTE_ND_OFFLOAD_VALUE\n\t// Add more attribute here\n};\n\ntypedef enum rtw_vendor_gscan_attribute {\n\tATTR_START_GSCAN,\n\tATTR_STOP_GSCAN,\n\tATTR_SET_SCAN_BATCH_CFG_ID, /* set batch scan params */\n\tATTR_SET_SCAN_GEOFENCE_CFG_ID, /* set list of bssids to track */\n\tATTR_SET_SCAN_SIGNIFICANT_CFG_ID, /* set list of bssids, rssi threshold etc.. */\n\tATTR_SET_SCAN_CFG_ID, /* set common scan config params here */\n\tATTR_GET_GSCAN_CAPABILITIES_ID,\n\t/* Add more sub commands here */\n\tATTR_GSCAN_MAX\n} rtw_vendor_gscan_attribute_t;\n\ntypedef enum gscan_batch_attribute {\n\tATTR_GSCAN_BATCH_BESTN,\n\tATTR_GSCAN_BATCH_MSCAN,\n\tATTR_GSCAN_BATCH_BUFFER_THRESHOLD\n} gscan_batch_attribute_t;\n\ntypedef enum gscan_geofence_attribute {\n\tATTR_GSCAN_NUM_HOTLIST_BSSID,\n\tATTR_GSCAN_HOTLIST_BSSID\n} gscan_geofence_attribute_t;\n\ntypedef enum gscan_complete_event {\n\tWIFI_SCAN_BUFFER_FULL,\n\tWIFI_SCAN_COMPLETE\n} gscan_complete_event_t;\n/* wifi_hal.h */\n/* WiFi Common definitions */\ntypedef unsigned char byte;\ntypedef int wifi_request_id;\ntypedef int wifi_channel;                       // indicates channel frequency in MHz\ntypedef int wifi_rssi;\ntypedef byte mac_addr[6];\ntypedef byte oui[3];\ntypedef int64_t wifi_timestamp;                 // In microseconds (us)\ntypedef int64_t wifi_timespan;                  // In picoseconds  (ps)\n\nstruct wifi_info;\nstruct wifi_interface_info;\ntypedef struct wifi_info *wifi_handle;\ntypedef struct wifi_interface_info *wifi_interface_handle;\n\n/* channel operating width */\ntypedef enum {\n    WIFI_CHAN_WIDTH_20    = 0,\n    WIFI_CHAN_WIDTH_40    = 1,\n    WIFI_CHAN_WIDTH_80    = 2,\n    WIFI_CHAN_WIDTH_160   = 3,\n    WIFI_CHAN_WIDTH_80P80 = 4,\n    WIFI_CHAN_WIDTH_5     = 5,\n    WIFI_CHAN_WIDTH_10    = 6,\n    WIFI_CHAN_WIDTH_INVALID = -1\n} wifi_channel_width;\n\ntypedef int wifi_radio;\n\ntypedef struct {\n    wifi_channel_width width;\n    int center_frequency0;\n    int center_frequency1;\n    int primary_frequency;\n} wifi_channel_spec;\n\ntypedef enum {\n    WIFI_SUCCESS = 0,\n    WIFI_ERROR_NONE = 0,\n    WIFI_ERROR_UNKNOWN = -1,\n    WIFI_ERROR_UNINITIALIZED = -2,\n    WIFI_ERROR_NOT_SUPPORTED = -3,\n    WIFI_ERROR_NOT_AVAILABLE = -4,              // Not available right now, but try later\n    WIFI_ERROR_INVALID_ARGS = -5,\n    WIFI_ERROR_INVALID_REQUEST_ID = -6,\n    WIFI_ERROR_TIMED_OUT = -7,\n    WIFI_ERROR_TOO_MANY_REQUESTS = -8,          // Too many instances of this request\n    WIFI_ERROR_OUT_OF_MEMORY = -9,\n    WIFI_ERROR_BUSY = -10,\n} wifi_error;\n\ntypedef int wifi_ring_buffer_id;\n/* ring buffer params */\n/**\n * written_bytes and read_bytes implement a producer consumer API\n *     hence written_bytes >= read_bytes\n * a modulo arithmetic of the buffer size has to be applied to those counters:\n * actual offset into ring buffer = written_bytes % ring_buffer_byte_size\n *\n */\ntypedef struct {\n    u8 name[32];\n    u32 flags;\n    wifi_ring_buffer_id ring_id; // unique integer representing the ring\n    u32 ring_buffer_byte_size;   // total memory size allocated for the buffer\n    u32 verbose_level;           // verbose level for ring buffer\n    u32 written_bytes;           // number of bytes that was written to the buffer by driver,\n                                 // monotonously increasing integer\n    u32 read_bytes;              // number of bytes that was read from the buffer by user land,\n                                 // monotonously increasing integer\n    u32 written_records;         // number of records that was written to the buffer by driver,\n                                 // monotonously increasing integer\n} wifi_ring_buffer_status;\n\n#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS\n#define STATS_MAJOR_VERSION      1\n#define STATS_MINOR_VERSION      0\n#define STATS_MICRO_VERSION      0\n\ntypedef enum {\n    WIFI_DISCONNECTED = 0,\n    WIFI_AUTHENTICATING = 1,\n    WIFI_ASSOCIATING = 2,\n    WIFI_ASSOCIATED = 3,\n    WIFI_EAPOL_STARTED = 4,   // if done by firmware/driver\n    WIFI_EAPOL_COMPLETED = 5, // if done by firmware/driver\n} wifi_connection_state;\n\ntypedef enum {\n    WIFI_ROAMING_IDLE = 0,\n    WIFI_ROAMING_ACTIVE = 1,\n} wifi_roam_state;\n\ntypedef enum {\n    WIFI_INTERFACE_STA = 0,\n    WIFI_INTERFACE_SOFTAP = 1,\n    WIFI_INTERFACE_IBSS = 2,\n    WIFI_INTERFACE_P2P_CLIENT = 3,\n    WIFI_INTERFACE_P2P_GO = 4,\n    WIFI_INTERFACE_NAN = 5,\n    WIFI_INTERFACE_MESH = 6,\n    WIFI_INTERFACE_UNKNOWN = -1\n } wifi_interface_mode;\n\n#define WIFI_CAPABILITY_QOS          0x00000001     // set for QOS association\n#define WIFI_CAPABILITY_PROTECTED    0x00000002     // set for protected association (802.11 beacon frame control protected bit set)\n#define WIFI_CAPABILITY_INTERWORKING 0x00000004     // set if 802.11 Extended Capabilities element interworking bit is set\n#define WIFI_CAPABILITY_HS20         0x00000008     // set for HS20 association\n#define WIFI_CAPABILITY_SSID_UTF8    0x00000010     // set is 802.11 Extended Capabilities element UTF-8 SSID bit is set\n#define WIFI_CAPABILITY_COUNTRY      0x00000020     // set is 802.11 Country Element is present\n\ntypedef struct {\n   wifi_interface_mode mode;     // interface mode\n   u8 mac_addr[6];               // interface mac address (self)\n   wifi_connection_state state;  // connection state (valid for STA, CLI only)\n   wifi_roam_state roaming;      // roaming state\n   u32 capabilities;             // WIFI_CAPABILITY_XXX (self)\n   u8 ssid[33];                  // null terminated SSID\n   u8 bssid[6];                  // bssid\n   u8 ap_country_str[3];         // country string advertised by AP\n   u8 country_str[3];            // country string for this association\n} wifi_interface_link_layer_info;\n\n/* channel information */\ntypedef struct {\n   wifi_channel_width width;   // channel width (20, 40, 80, 80+80, 160)\n   wifi_channel center_freq;   // primary 20 MHz channel\n   wifi_channel center_freq0;  // center frequency (MHz) first segment\n   wifi_channel center_freq1;  // center frequency (MHz) second segment\n} wifi_channel_info;\n\n/* wifi rate */\ntypedef struct {\n   u32 preamble   :3;   // 0: OFDM, 1:CCK, 2:HT 3:VHT 4..7 reserved\n   u32 nss        :2;   // 0:1x1, 1:2x2, 3:3x3, 4:4x4\n   u32 bw         :3;   // 0:20MHz, 1:40Mhz, 2:80Mhz, 3:160Mhz\n   u32 rateMcsIdx :8;   // OFDM/CCK rate code would be as per ieee std in the units of 0.5mbps\n                        // HT/VHT it would be mcs index\n   u32 reserved  :16;   // reserved\n   u32 bitrate;         // units of 100 Kbps\n} wifi_rate;\n\n/* channel statistics */\ntypedef struct {\n   wifi_channel_info channel;  // channel\n   u32 on_time;                // msecs the radio is awake (32 bits number accruing over time)\n   u32 cca_busy_time;          // msecs the CCA register is busy (32 bits number accruing over time)\n} wifi_channel_stat;\n\n// Max number of tx power levels. The actual number vary per device and is specified by |num_tx_levels|\n#define RADIO_STAT_MAX_TX_LEVELS 256\n\n/* Internal radio statistics structure in the driver */\ntypedef struct {\n   wifi_radio radio;                      // wifi radio (if multiple radio supported)\n   u32 on_time;                           // msecs the radio is awake (32 bits number accruing over time)\n   u32 tx_time;                           // msecs the radio is transmitting (32 bits number accruing over time)\n   u32 rx_time;                           // msecs the radio is in active receive (32 bits number accruing over time)\n   u32 on_time_scan;                      // msecs the radio is awake due to all scan (32 bits number accruing over time)\n   u32 on_time_nbd;                       // msecs the radio is awake due to NAN (32 bits number accruing over time)\n   u32 on_time_gscan;                     // msecs the radio is awake due to G?scan (32 bits number accruing over time)\n   u32 on_time_roam_scan;                 // msecs the radio is awake due to roam?scan (32 bits number accruing over time)\n   u32 on_time_pno_scan;                  // msecs the radio is awake due to PNO scan (32 bits number accruing over time)\n   u32 on_time_hs20;                      // msecs the radio is awake due to HS2.0 scans and GAS exchange (32 bits number accruing over time)\n   u32 num_channels;                      // number of channels\n   wifi_channel_stat channels[];          // channel statistics\n} wifi_radio_stat_internal;\n\n/**\n * Packet statistics reporting by firmware is performed on MPDU basi (i.e. counters increase by 1 for each MPDU)\n * As well, \"data packet\" in associated comments, shall be interpreted as 802.11 data packet,\n * that is, 802.11 frame control subtype == 2 and excluding management and control frames.\n *\n * As an example, in the case of transmission of an MSDU fragmented in 16 MPDUs which are transmitted\n * OTA in a 16 units long a-mpdu, for which a block ack is received with 5 bits set:\n *          tx_mpdu : shall increase by 5\n *          retries : shall increase by 16\n *          tx_ampdu : shall increase by 1\n * data packet counters shall not increase regardless of the number of BAR potentially sent by device for this a-mpdu\n * data packet counters shall not increase regardless of the number of BA received by device for this a-mpdu\n *\n * For each subsequent retransmission of the 11 remaining non ACK'ed mpdus\n * (regardless of the fact that they are transmitted in a-mpdu or not)\n *          retries : shall increase by 1\n *\n * If no subsequent BA or ACK are received from AP, until packet lifetime expires for those 11 packet that were not ACK'ed\n *          mpdu_lost : shall increase by 11\n */\n\n/* per rate statistics */\ntypedef struct {\n   wifi_rate rate;     // rate information\n   u32 tx_mpdu;        // number of successfully transmitted data pkts (ACK rcvd)\n   u32 rx_mpdu;        // number of received data pkts\n   u32 mpdu_lost;      // number of data packet losses (no ACK)\n   u32 retries;        // total number of data pkt retries\n   u32 retries_short;  // number of short data pkt retries\n   u32 retries_long;   // number of long data pkt retries\n} wifi_rate_stat;\n\n/* access categories */\ntypedef enum {\n   WIFI_AC_VO  = 0,\n   WIFI_AC_VI  = 1,\n   WIFI_AC_BE  = 2,\n   WIFI_AC_BK  = 3,\n   WIFI_AC_MAX = 4,\n} wifi_traffic_ac;\n\n/* wifi peer type */\ntypedef enum\n{\n   WIFI_PEER_STA,\n   WIFI_PEER_AP,\n   WIFI_PEER_P2P_GO,\n   WIFI_PEER_P2P_CLIENT,\n   WIFI_PEER_NAN,\n   WIFI_PEER_TDLS,\n   WIFI_PEER_INVALID,\n} wifi_peer_type;\n\n/* per peer statistics */\ntypedef struct {\n   wifi_peer_type type;           // peer type (AP, TDLS, GO etc.)\n   u8 peer_mac_address[6];        // mac address\n   u32 capabilities;              // peer WIFI_CAPABILITY_XXX\n   u32 num_rate;                  // number of rates\n   wifi_rate_stat rate_stats[];   // per rate statistics, number of entries  = num_rate\n} wifi_peer_info;\n\n/* Per access category statistics */\ntypedef struct {\n   wifi_traffic_ac ac;             // access category (VI, VO, BE, BK)\n   u32 tx_mpdu;                    // number of successfully transmitted unicast data pkts (ACK rcvd)\n   u32 rx_mpdu;                    // number of received unicast data packets\n   u32 tx_mcast;                   // number of succesfully transmitted multicast data packets\n                                   // STA case: implies ACK received from AP for the unicast packet in which mcast pkt was sent\n   u32 rx_mcast;                   // number of received multicast data packets\n   u32 rx_ampdu;                   // number of received unicast a-mpdus; support of this counter is optional\n   u32 tx_ampdu;                   // number of transmitted unicast a-mpdus; support of this counter is optional\n   u32 mpdu_lost;                  // number of data pkt losses (no ACK)\n   u32 retries;                    // total number of data pkt retries\n   u32 retries_short;              // number of short data pkt retries\n   u32 retries_long;               // number of long data pkt retries\n   u32 contention_time_min;        // data pkt min contention time (usecs)\n   u32 contention_time_max;        // data pkt max contention time (usecs)\n   u32 contention_time_avg;        // data pkt avg contention time (usecs)\n   u32 contention_num_samples;     // num of data pkts used for contention statistics\n} wifi_wmm_ac_stat;\n\n/* interface statistics */\ntypedef struct {\n   wifi_interface_handle iface;          // wifi interface\n   wifi_interface_link_layer_info info;  // current state of the interface\n   u32 beacon_rx;                        // access point beacon received count from connected AP\n   u64 average_tsf_offset;               // average beacon offset encountered (beacon_TSF - TBTT)\n                                         // The average_tsf_offset field is used so as to calculate the\n                                         // typical beacon contention time on the channel as well may be\n                                         // used to debug beacon synchronization and related power consumption issue\n   u32 leaky_ap_detected;                // indicate that this AP typically leaks packets beyond the driver guard time.\n   u32 leaky_ap_avg_num_frames_leaked;  // average number of frame leaked by AP after frame with PM bit set was ACK'ed by AP\n   u32 leaky_ap_guard_time;              // guard time currently in force (when implementing IEEE power management based on\n                                         // frame control PM bit), How long driver waits before shutting down the radio and\n                                         // after receiving an ACK for a data frame with PM bit set)\n   u32 mgmt_rx;                          // access point mgmt frames received count from connected AP (including Beacon)\n   u32 mgmt_action_rx;                   // action frames received count\n   u32 mgmt_action_tx;                   // action frames transmit count\n   wifi_rssi rssi_mgmt;                  // access Point Beacon and Management frames RSSI (averaged)\n   wifi_rssi rssi_data;                  // access Point Data Frames RSSI (averaged) from connected AP\n   wifi_rssi rssi_ack;                   // access Point ACK RSSI (averaged) from connected AP\n   wifi_wmm_ac_stat ac[WIFI_AC_MAX];     // per ac data packet statistics\n   u32 num_peers;                        // number of peers\n   wifi_peer_info peer_info[];           // per peer statistics\n} wifi_iface_stat;\n\n/* configuration params */\ntypedef struct {\n   u32 mpdu_size_threshold;             // threshold to classify the pkts as short or long\n                                        // packet size < mpdu_size_threshold => short\n   u32 aggressive_statistics_gathering; // set for field debug mode. Driver should collect all statistics regardless of performance impact.\n} wifi_link_layer_params;\n\n#define RSSI_MONITOR_EVT_VERSION   1\ntypedef struct {\n    u8 version;\n    s8 cur_rssi;\n    mac_addr BSSID;\n} rssi_monitor_evt;\n\n\n/* wifi statistics bitmap  */\n#define WIFI_STATS_RADIO              0x00000001      // all radio statistics\n#define WIFI_STATS_RADIO_CCA          0x00000002      // cca_busy_time (within radio statistics)\n#define WIFI_STATS_RADIO_CHANNELS     0x00000004      // all channel statistics (within radio statistics)\n#define WIFI_STATS_RADIO_SCAN         0x00000008      // all scan statistics (within radio statistics)\n#define WIFI_STATS_IFACE              0x00000010      // all interface statistics\n#define WIFI_STATS_IFACE_TXRATE       0x00000020      // all tx rate statistics (within interface statistics)\n#define WIFI_STATS_IFACE_AC           0x00000040      // all ac statistics (within interface statistics)\n#define WIFI_STATS_IFACE_CONTENTION   0x00000080      // all contention (min, max, avg) statistics (within ac statisctics)\n\n#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */\n\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT)\nextern int rtw_cfgvendor_attach(struct wiphy *wiphy);\nextern int rtw_cfgvendor_detach(struct wiphy *wiphy);\nextern int rtw_cfgvendor_send_async_event(struct wiphy *wiphy,\n\tstruct net_device *dev, int event_id, const void  *data, int len);\n#if defined(GSCAN_SUPPORT) && 0\nextern int rtw_cfgvendor_send_hotlist_event(struct wiphy *wiphy,\n\tstruct net_device *dev, void  *data, int len, rtw_vendor_event_t event);\n#endif\n#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */\n\n#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR\nvoid rtw_cfgvendor_rssi_monitor_evt(_adapter *padapter);\n#endif\n\n#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI\nvoid rtw_hal_pno_random_gen_mac_addr(PADAPTER adapter);\nvoid rtw_hal_set_hw_mac_addr(PADAPTER adapter, u8 *mac_addr);\n#endif\n\n\n#endif /* _RTW_CFGVENDOR_H_ */\n"
  },
  {
    "path": "os_dep/linux/rtw_proc.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include <linux/ctype.h>\t/* tolower() */\n#include <drv_types.h>\n#include <hal_data.h>\n#include \"rtw_proc.h\"\n#include <rtw_btcoex.h>\n\n#ifdef CONFIG_PROC_DEBUG\n\nstatic struct proc_dir_entry *rtw_proc = NULL;\n\ninline struct proc_dir_entry *get_rtw_drv_proc(void)\n{\n\treturn rtw_proc;\n}\n\n#define RTW_PROC_NAME DRV_NAME\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))\n#define file_inode(file) ((file)->f_dentry->d_inode)\n#endif\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))\n#define PDE_DATA(inode) PDE((inode))->data\n#define proc_get_parent_data(inode) PDE((inode))->parent->data\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0))\n#define PDE_DATA(inode) pde_data(inode)\n#endif\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))\n#define get_proc_net proc_net\n#else\n#define get_proc_net init_net.proc_net\n#endif\n\ninline struct proc_dir_entry *rtw_proc_create_dir(const char *name, struct proc_dir_entry *parent, void *data)\n{\n\tstruct proc_dir_entry *entry;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))\n\tentry = proc_mkdir_data(name, S_IRUGO | S_IXUGO, parent, data);\n#else\n\t/* entry = proc_mkdir_mode(name, S_IRUGO|S_IXUGO, parent); */\n\tentry = proc_mkdir(name, parent);\n\tif (entry)\n\t\tentry->data = data;\n#endif\n\n\treturn entry;\n}\n\ninline struct proc_dir_entry *rtw_proc_create_entry(const char *name, struct proc_dir_entry *parent,\n\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0))\n\tconst struct file_operations *fops,\n\t#else\n\tconst struct proc_ops *fops,\n\t#endif\n\tvoid * data\n\t)\n{\n\tstruct proc_dir_entry *entry;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26))\n\tentry = proc_create_data(name,  S_IFREG | S_IRUGO | S_IWUGO, parent, fops, data);\n#else\n\tentry = create_proc_entry(name, S_IFREG | S_IRUGO | S_IWUGO, parent);\n\tif (entry) {\n\t\tentry->data = data;\n\t\tentry->proc_fops = fops;\n\t}\n#endif\n\n\treturn entry;\n}\n\nstatic int proc_get_dummy(struct seq_file *m, void *v)\n{\n\treturn 0;\n}\n\nstatic int proc_get_drv_version(struct seq_file *m, void *v)\n{\n\tdump_drv_version(m);\n\treturn 0;\n}\n\nstatic int proc_get_log_level(struct seq_file *m, void *v)\n{\n\tdump_log_level(m);\n\treturn 0;\n}\n\nstatic int proc_get_drv_cfg(struct seq_file *m, void *v)\n{\n\tdump_drv_cfg(m);\n\treturn 0;\n}\n\nstatic ssize_t proc_set_log_level(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tchar tmp[32];\n\tint log_level;\n\n\tif (count < 1)\n\t\treturn -EINVAL;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n#ifdef CONFIG_RTW_DEBUG\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d \", &log_level);\n\n\t\tif (num == 1 &&\n\t\t    log_level >= _DRV_NONE_ && log_level <= _DRV_MAX_) {\n\t\t\trtw_drv_log_level = log_level;\n\t\t\tprintk(\"rtw_drv_log_level:%d\\n\", rtw_drv_log_level);\n\t\t}\n\t} else\n\t\treturn -EFAULT;\n#else\n\tprintk(\"CONFIG_RTW_DEBUG is disabled\\n\");\n#endif\n\n\treturn count;\n}\n\n#ifdef DBG_MEM_ALLOC\nstatic int proc_get_mstat(struct seq_file *m, void *v)\n{\n\trtw_mstat_dump(m);\n\treturn 0;\n}\n#endif /* DBG_MEM_ALLOC */\n\nstatic int proc_get_country_chplan_map(struct seq_file *m, void *v)\n{\n\tdump_country_chplan_map(m);\n\treturn 0;\n}\n\nstatic int proc_get_chplan_id_list(struct seq_file *m, void *v)\n{\n\tdump_chplan_id_list(m);\n\treturn 0;\n}\n\nstatic int proc_get_chplan_test(struct seq_file *m, void *v)\n{\n\tdump_chplan_test(m);\n\treturn 0;\n}\n\nstatic int proc_get_chplan_ver(struct seq_file *m, void *v)\n{\n\tdump_chplan_ver(m);\n\treturn 0;\n}\n\n#ifdef RTW_HALMAC\nextern void rtw_halmac_get_version(char *str, u32 len);\n\nstatic int proc_get_halmac_info(struct seq_file *m, void *v)\n{\n\tchar ver[30] = {0};\n\n\n\trtw_halmac_get_version(ver, 30);\n\tRTW_PRINT_SEL(m, \"version: %s\\n\", ver);\n\n\treturn 0;\n}\n#endif\n\n/*\n* rtw_drv_proc:\n* init/deinit when register/unregister driver\n*/\nconst struct rtw_proc_hdl drv_proc_hdls[] = {\n\tRTW_PROC_HDL_SSEQ(\"ver_info\", proc_get_drv_version, NULL),\n\tRTW_PROC_HDL_SSEQ(\"log_level\", proc_get_log_level, proc_set_log_level),\n\tRTW_PROC_HDL_SSEQ(\"drv_cfg\", proc_get_drv_cfg, NULL),\n#ifdef DBG_MEM_ALLOC\n\tRTW_PROC_HDL_SSEQ(\"mstat\", proc_get_mstat, NULL),\n#endif /* DBG_MEM_ALLOC */\n\tRTW_PROC_HDL_SSEQ(\"country_chplan_map\", proc_get_country_chplan_map, NULL),\n\tRTW_PROC_HDL_SSEQ(\"chplan_id_list\", proc_get_chplan_id_list, NULL),\n\tRTW_PROC_HDL_SSEQ(\"chplan_test\", proc_get_chplan_test, NULL),\n\tRTW_PROC_HDL_SSEQ(\"chplan_ver\", proc_get_chplan_ver, NULL),\n#ifdef RTW_HALMAC\n\tRTW_PROC_HDL_SSEQ(\"halmac_info\", proc_get_halmac_info, NULL),\n#endif /* RTW_HALMAC */\n};\n\nconst int drv_proc_hdls_num = sizeof(drv_proc_hdls) / sizeof(struct rtw_proc_hdl);\n\nstatic int rtw_drv_proc_open(struct inode *inode, struct file *file)\n{\n\t/* struct net_device *dev = proc_get_parent_data(inode); */\n\tssize_t index = (ssize_t)PDE_DATA(inode);\n\tconst struct rtw_proc_hdl *hdl = drv_proc_hdls + index;\n\tvoid *private = NULL;\n\n\tif (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {\n\t\tint res = seq_open(file, hdl->u.seq_op);\n\n\t\tif (res == 0)\n\t\t\t((struct seq_file *)file->private_data)->private = private;\n\n\t\treturn res;\n\t} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {\n\t\tint (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;\n\n\t\treturn single_open(file, show, private);\n\t} else {\n\t\treturn -EROFS;\n\t}\n}\n\nstatic ssize_t rtw_drv_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)\n{\n\tssize_t index = (ssize_t)PDE_DATA(file_inode(file));\n\tconst struct rtw_proc_hdl *hdl = drv_proc_hdls + index;\n\tssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;\n\n\tif (write)\n\t\treturn write(file, buffer, count, pos, NULL);\n\n\treturn -EROFS;\n}\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0))\nstatic const struct file_operations rtw_drv_proc_seq_fops = {\n\t.owner = THIS_MODULE,\n\t.open = rtw_drv_proc_open,\n\t.read = seq_read,\n\t.llseek = seq_lseek,\n\t.release = seq_release,\n\t.write = rtw_drv_proc_write,\n};\n\nstatic const struct file_operations rtw_drv_proc_sseq_fops = {\n\t.owner = THIS_MODULE,\n\t.open = rtw_drv_proc_open,\n\t.read = seq_read,\n\t.llseek = seq_lseek,\n\t.release = single_release,\n\t.write = rtw_drv_proc_write,\n};\n#else\nstatic const struct proc_ops rtw_drv_proc_seq_fops = {\n\t.proc_open = rtw_drv_proc_open,\n\t.proc_read = seq_read,\n\t.proc_lseek = seq_lseek,\n\t.proc_release = seq_release,\n\t.proc_write = rtw_drv_proc_write,\n};\n\nstatic const struct proc_ops rtw_drv_proc_sseq_fops = {\n\t.proc_open = rtw_drv_proc_open,\n\t.proc_read = seq_read,\n\t.proc_lseek = seq_lseek,\n\t.proc_release = single_release,\n\t.proc_write = rtw_drv_proc_write,\n};\n#endif\n\nint rtw_drv_proc_init(void)\n{\n\tint ret = _FAIL;\n\tssize_t i;\n\tstruct proc_dir_entry *entry = NULL;\n\n\tif (rtw_proc != NULL) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\trtw_proc = rtw_proc_create_dir(RTW_PROC_NAME, get_proc_net, NULL);\n\n\tif (rtw_proc == NULL) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tfor (i = 0; i < drv_proc_hdls_num; i++) {\n\t\tif (drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)\n\t\t\tentry = rtw_proc_create_entry(drv_proc_hdls[i].name, rtw_proc, &rtw_drv_proc_seq_fops, (void *)i);\n\t\telse if (drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ)\n\t\t\tentry = rtw_proc_create_entry(drv_proc_hdls[i].name, rtw_proc, &rtw_drv_proc_sseq_fops, (void *)i);\n\t\telse\n\t\t\tentry = NULL;\n\n\t\tif (!entry) {\n\t\t\trtw_warn_on(1);\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\tret = _SUCCESS;\n\nexit:\n\treturn ret;\n}\n\nvoid rtw_drv_proc_deinit(void)\n{\n\tint i;\n\n\tif (rtw_proc == NULL)\n\t\treturn;\n\n\tfor (i = 0; i < drv_proc_hdls_num; i++)\n\t\tremove_proc_entry(drv_proc_hdls[i].name, rtw_proc);\n\n\tremove_proc_entry(RTW_PROC_NAME, get_proc_net);\n\trtw_proc = NULL;\n}\n\n#ifndef RTW_SEQ_FILE_TEST\n#define RTW_SEQ_FILE_TEST 0\n#endif\n\n#if RTW_SEQ_FILE_TEST\n#define RTW_SEQ_FILE_TEST_SHOW_LIMIT 300\nstatic void *proc_start_seq_file_test(struct seq_file *m, loff_t *pos)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_PRINT(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(adapter));\n\tif (*pos >= RTW_SEQ_FILE_TEST_SHOW_LIMIT) {\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" pos:%llu, out of range return\\n\", FUNC_ADPT_ARG(adapter), *pos);\n\t\treturn NULL;\n\t}\n\n\tRTW_PRINT(FUNC_ADPT_FMT\" return pos:%lld\\n\", FUNC_ADPT_ARG(adapter), *pos);\n\treturn pos;\n}\nvoid proc_stop_seq_file_test(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_PRINT(FUNC_ADPT_FMT\"\\n\", FUNC_ADPT_ARG(adapter));\n}\n\nvoid *proc_next_seq_file_test(struct seq_file *m, void *v, loff_t *pos)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\t(*pos)++;\n\tif (*pos >= RTW_SEQ_FILE_TEST_SHOW_LIMIT) {\n\t\tRTW_PRINT(FUNC_ADPT_FMT\" pos:%lld, out of range return\\n\", FUNC_ADPT_ARG(adapter), *pos);\n\t\treturn NULL;\n\t}\n\n\tRTW_PRINT(FUNC_ADPT_FMT\" return pos:%lld\\n\", FUNC_ADPT_ARG(adapter), *pos);\n\treturn pos;\n}\n\nstatic int proc_get_seq_file_test(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tu32 pos = *((loff_t *)(v));\n\tRTW_PRINT(FUNC_ADPT_FMT\" pos:%d\\n\", FUNC_ADPT_ARG(adapter), pos);\n\tRTW_PRINT_SEL(m, FUNC_ADPT_FMT\" pos:%d\\n\", FUNC_ADPT_ARG(adapter), pos);\n\treturn 0;\n}\n\nstruct seq_operations seq_file_test = {\n\t.start = proc_start_seq_file_test,\n\t.stop  = proc_stop_seq_file_test,\n\t.next  = proc_next_seq_file_test,\n\t.show  = proc_get_seq_file_test,\n};\n#endif /* RTW_SEQ_FILE_TEST */\n\n#ifdef CONFIG_SDIO_HCI\nstatic int proc_get_sd_f0_reg_dump(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tsd_f0_reg_dump(m, adapter);\n\n\treturn 0;\n}\n\nstatic int proc_get_sdio_local_reg_dump(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tsdio_local_reg_dump(m, adapter);\n\n\treturn 0;\n}\nstatic int proc_get_sdio_card_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_sdio_card_info(m, adapter_to_dvobj(adapter));\n\n\treturn 0;\n}\n\n#ifdef DBG_SDIO\nstatic int proc_get_sdio_dbg(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev;\n\tstruct _ADAPTER *a;\n\tstruct dvobj_priv *d;\n\tstruct sdio_data *sdio;\n\n\n\tdev = m->private;\n\ta = (struct _ADAPTER *)rtw_netdev_priv(dev);\n\td = adapter_to_dvobj(a);\n\tsdio = &d->intf_data;\n\n\tdump_sdio_card_info(m, d);\n\n\tRTW_PRINT_SEL(m, \"CMD52 error cnt: %d\\n\", sdio->cmd52_err_cnt);\n\tRTW_PRINT_SEL(m, \"CMD53 error cnt: %d\\n\", sdio->cmd53_err_cnt);\n\n#if (DBG_SDIO >= 3)\n\tRTW_PRINT_SEL(m, \"dbg: %s\\n\", sdio->dbg_enable?\"enable\":\"disable\");\n\tRTW_PRINT_SEL(m, \"err_stop: %s\\n\", sdio->err_stop?\"enable\":\"disable\");\n\tRTW_PRINT_SEL(m, \"err_test: %s\\n\", sdio->err_test?\"enable\":\"disable\");\n\tRTW_PRINT_SEL(m, \"err_test_triggered: %s\\n\",\n\t\t      sdio->err_test_triggered?\"yes\":\"no\");\n#endif /* DBG_SDIO >= 3 */\n\n#if (DBG_SDIO >= 2)\n\tRTW_PRINT_SEL(m, \"I/O error dump mark: %d\\n\", sdio->reg_dump_mark);\n\tif (sdio->reg_dump_mark) {\n\t\tif (sdio->dbg_msg)\n\t\t\tRTW_PRINT_SEL(m, \"debug messages: %s\\n\", sdio->dbg_msg);\n\t\tif (sdio->reg_mac)\n\t\t\tRTW_BUF_DUMP_SEL(_DRV_ALWAYS_, m, \"MAC register:\",\n\t\t\t\t\t _TRUE, sdio->reg_mac, 0x800);\n\t\tif (sdio->reg_mac_ext)\n\t\t\tRTW_BUF_DUMP_SEL(_DRV_ALWAYS_, m, \"MAC EXT register:\",\n\t\t\t\t\t _TRUE, sdio->reg_mac_ext, 0x800);\n\t\tif (sdio->reg_local)\n\t\t\tRTW_BUF_DUMP_SEL(_DRV_ALWAYS_, m, \"SDIO Local register:\",\n\t\t\t\t\t _TRUE, sdio->reg_local, 0x100);\n\t\tif (sdio->reg_cia)\n\t\t\tRTW_BUF_DUMP_SEL(_DRV_ALWAYS_, m, \"SDIO CIA register:\",\n\t\t\t\t\t _TRUE, sdio->reg_cia, 0x200);\n\t}\n#endif /* DBG_SDIO >= 2 */\n\n\treturn 0;\n}\n\n#if (DBG_SDIO >= 2)\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))\n#define strnicmp\tstrncasecmp\n#endif /* Linux kernel >= 4.0.0 */\nvoid rtw_sdio_dbg_reg_free(struct dvobj_priv *d);\n#endif /* DBG_SDIO >= 2 */\n\nssize_t proc_set_sdio_dbg(struct file *file, const char __user *buffer,\n\t\t\t  size_t count, loff_t *pos, void *data)\n{\n#if (DBG_SDIO >= 2)\n\tstruct net_device *dev = data;\n\tstruct dvobj_priv *d;\n\tstruct _ADAPTER *a;\n\tstruct sdio_data *sdio;\n\tchar tmp[32], cmd[32] = {0};\n\tint num;\n\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\ta = (struct _ADAPTER *)rtw_netdev_priv(dev);\n\td = adapter_to_dvobj(a);\n\tsdio = &d->intf_data;\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tnum = sscanf(tmp, \"%s\", cmd);\n\n\t\tif (num >= 1) {\n\t\t\tif (strnicmp(cmd, \"reg_reset\", 10) == 0) {\n\t\t\t\tsdio->reg_dump_mark = 0;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tif (strnicmp(cmd, \"reg_free\", 9) == 0) {\n\t\t\t\trtw_sdio_dbg_reg_free(d);\n\t\t\t\tsdio->reg_dump_mark = 0;\n\t\t\t\tgoto exit;\n\t\t\t}\n#if (DBG_SDIO >= 3)\n\t\t\tif (strnicmp(cmd, \"dbg_enable\", 11) == 0) {\n\t\t\t\tsdio->dbg_enable = 1;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tif (strnicmp(cmd, \"dbg_disable\", 12) == 0) {\n\t\t\t\tsdio->dbg_enable = 0;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tif (strnicmp(cmd, \"err_stop\", 9) == 0) {\n\t\t\t\tsdio->err_stop = 1;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tif (strnicmp(cmd, \"err_stop_disable\", 16) == 0) {\n\t\t\t\tsdio->err_stop = 0;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tif (strnicmp(cmd, \"err_test\", 9) == 0) {\n\t\t\t\tsdio->err_test_triggered = 0;\n\t\t\t\tsdio->err_test = 1;\n\t\t\t\tgoto exit;\n\t\t\t}\n#endif /* DBG_SDIO >= 3 */\n\t\t}\n\n\t\treturn -EINVAL;\n\t}\n\nexit:\n#endif /* DBG_SDIO >= 2 */\n\treturn count;\n}\n#endif /* DBG_SDIO */\n\n#ifdef CONFIG_SDIO_MONITOR\nstatic int proc_get_sdio_monitor(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tconst char *const sdio_monitor_mode_str[] = {\n\t\t\"SDIO_MONITOR_MODE_DISABLE\",\n\t\t\"SDIO_MONITOR_MODE_INT_LAT\",\n\t\t\"SDIO_MONITOR_MODE_CMD53W_INTVL\",\n\t\t\"SDIO_MONITOR_MODE_SDIO_CLK_5US\",\n\t\t\"SDIO_MONITOR_MODE_SDIO_CLK_50US\",\n\t\t\"SDIO_MONITOR_MODE_SDIO_CLK_9MS\"\n\t};\n\n\tRTW_PRINT_SEL(m, \"sdio monitor mode is set to %s !\\n\", sdio_monitor_mode_str[hal_data->sdio_monitor_enable]);\n\n\tif (hal_data->sdio_monitor_enable == SDIO_MONITOR_MODE_DISABLE)\n\t\treturn 0;\n\n\tif ((hal_data->sdio_monitor_enable == SDIO_MONITOR_MODE_INT_LAT) || (hal_data->sdio_monitor_enable == SDIO_MONITOR_MODE_CMD53W_INTVL)) {\n\t\tu32 i = 0, tmp_data = 0;\n\t\tu32 sample_num = hal_data->sdio_monitor_sample_num;\n\t\tu32 sample_data_avg = 0;\n\n\t\tif (sample_num > 0) {\n\t\t\tfor (i = 0; i < sample_num; i++)\n\t\t\t\ttmp_data += hal_data->sdio_monitor_sample_data[i];\n\n\t\t\tsample_data_avg = tmp_data / sample_num;\n\n\t\t\tif (hal_data->sdio_monitor_enable == SDIO_MONITOR_MODE_INT_LAT)\n\t\t\t\tRTW_PRINT_SEL(m, \"average INT latency is %d us in %d samples !\\n\", sample_data_avg, sample_num);\n\t\t\telse\n\t\t\t\tRTW_PRINT_SEL(m, \"average CMD53 write interval between CMD and DATA is %d SDIO_CLK cycle in %d samples !\\n\", sample_data_avg, sample_num);\n\n\t\t\t_rtw_memset(hal_data->sdio_monitor_sample_data, 0x00, sizeof(hal_data->sdio_monitor_sample_data));\n\t\t\thal_data->sdio_monitor_sample_num = 0;\n\t\t}\n\t\telse\n\t\t\tRTW_PRINT_SEL(m, \"sdio int lat num is 0 !\\n\");\n\t}\n\telse if (hal_data->sdio_monitor_enable >= SDIO_MONITOR_MODE_SDIO_CLK_5US) {\n\t\tu32 clk_cnt = 0;\n\t\tu32 clk_rate = 0;\n\t\t\n\t\tclk_cnt = sd_monitor_sdio_clk(adapter, hal_data->sdio_monitor_enable);\n\t\tif (clk_cnt == 0)\n\t\t\tRTW_PRINT_SEL(m, \" polling timeout for SDIO CLK cnt  !\\n\");\n\t\telse {\n\t\t\tswitch (hal_data->sdio_monitor_enable) {\n\t\t\tcase SDIO_MONITOR_MODE_SDIO_CLK_5US:\n\t\t\t\t/* clk_rate = (clk_cnt * 200 * 1000) / (1000 * 1000) = (clk_cnt / 5) MHz */\n\t\t\t\tclk_rate = clk_cnt / 5; \n\t\t\t\tbreak;\n\t\t\tcase SDIO_MONITOR_MODE_SDIO_CLK_50US:\n\t\t\t\t/* clk_rate = (clk_cnt * 20 * 1000) / (1000 * 1000) = (clk_cnt / 50) MHz */\n\t\t\t\tclk_rate = clk_cnt / 50; \n\t\t\t\tbreak;\n\t\t\tcase SDIO_MONITOR_MODE_SDIO_CLK_9MS:\n\t\t\t\t/* clk_rate ~= (clk_cnt * 111) / (1000 * 1000) ~= (clk_cnt / 9009) MHz */\n\t\t\t\tclk_rate = clk_cnt / 9009; \n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* to compensate the 8822C timing */\n\t\t\tclk_rate *= 2;\n\t\t\t\n\t\t\tRTW_PRINT_SEL(m, \" SDIO CLK is %d MHz by HW measurement !\\n\", clk_rate);\n\t\t}\n\t}\n\t\t\n\treturn 0;\n}\n\nstatic ssize_t proc_set_sdio_monitor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);\n\tchar tmp[32] = {0};\n\tint sdio_monitor_enable = 0;\n\n\tif (!padapter)\n\t\treturn -EFAULT;\n\n\tif (count < 1) {\n\t\tRTW_INFO(\"argument size is less than 1\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%d\", &sdio_monitor_enable);\n\n\t\tif (num == 1) {\n\t\t\tif ((sdio_monitor_enable < SDIO_MONITOR_MODE_DISABLE) || (sdio_monitor_enable >= SDIO_MONITOR_MODE_MAX)) {\n\t\t\t\tRTW_INFO(\"invalid value for sdio monitor mode !\\n\");\n\t\t\t\treturn -EFAULT;\n\t\t\t}\n\n\t\t\tif (sdio_monitor_enable != hal_data->sdio_monitor_enable) {\n\t\t\t\thal_data->sdio_monitor_enable = sdio_monitor_enable;\n\t\t\t\t_rtw_memset(hal_data->sdio_monitor_sample_data, 0x00, sizeof(hal_data->sdio_monitor_sample_data));\n\t\t\t\thal_data->sdio_monitor_sample_num = 0;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn count;\n}\n#endif\n#endif /* CONFIG_SDIO_HCI */\n\nstatic int proc_get_fw_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\trtw_dump_fw_info(m, adapter);\n\treturn 0;\n}\nstatic int proc_get_mac_reg_dump(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tmac_reg_dump(m, adapter);\n\n\treturn 0;\n}\n\nstatic int proc_get_bb_reg_dump(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tbb_reg_dump(m, adapter);\n\n\treturn 0;\n}\n\nstatic int proc_get_bb_reg_dump_ex(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tbb_reg_dump_ex(m, adapter);\n\n\treturn 0;\n}\n\nstatic int proc_get_rf_reg_dump(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\trf_reg_dump(m, adapter);\n\n\treturn 0;\n}\n\n#ifdef CONFIG_RTW_LED\nint proc_get_led_config(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_led_config(m, adapter);\n\n\treturn 0;\n}\n\nssize_t proc_set_led_config(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tchar tmp[32];\n\tu8 strategy;\n\tu8 iface_en_mask;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhu %hhx\", &strategy, &iface_en_mask);\n\n\t\tif (num >= 1)\n\t\t\trtw_led_set_strategy(adapter, strategy);\n\t\tif (num >= 2)\n\t\t\trtw_led_set_iface_en_mask(adapter, iface_en_mask);\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_RTW_LED */\n\n#ifdef CONFIG_AP_MODE\nint proc_get_aid_status(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_aid_status(m, adapter);\n\n\treturn 0;\n}\n\nssize_t proc_set_aid_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct sta_priv *stapriv = &adapter->stapriv;\n\n\tchar tmp[32];\n\tu8 rr;\n\tu16 started_aid;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhu %hu\", &rr, &started_aid);\n\n\t\tif (num >= 1)\n\t\t\tstapriv->rr_aid = rr ? 1 : 0;\n\t\tif (num >= 2) {\n\t\t\tstarted_aid = started_aid % (stapriv->max_aid + 1);\n\t\t\tstapriv->started_aid = started_aid ? started_aid : 1;\n\t\t}\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_AP_MODE */\n\nstatic int proc_get_dump_tx_rate_bmp(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_tx_rate_bmp(m, adapter_to_dvobj(adapter));\n\n\treturn 0;\n}\n\nstatic int proc_get_dump_adapters_status(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_adapters_status(m, adapter_to_dvobj(adapter));\n\n\treturn 0;\n}\n\n#ifdef CONFIG_RTW_CUSTOMER_STR\nstatic int proc_get_customer_str(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tu8 cstr[RTW_CUSTOMER_STR_LEN];\n\n\trtw_ps_deny(adapter, PS_DENY_IOCTL);\n\tif (rtw_pwr_wakeup(adapter) == _FAIL)\n\t\tgoto exit;\n\n\tif (rtw_hal_customer_str_read(adapter, cstr) != _SUCCESS)\n\t\tgoto exit;\n\n\tRTW_PRINT_SEL(m, RTW_CUSTOMER_STR_FMT\"\\n\", RTW_CUSTOMER_STR_ARG(cstr));\n\nexit:\n\trtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);\n\treturn 0;\n}\n#endif /* CONFIG_RTW_CUSTOMER_STR */\n\n#ifdef CONFIG_SCAN_BACKOP\nstatic int proc_get_backop_flags_sta(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\n\tRTW_PRINT_SEL(m, \"0x%02x\\n\", mlmeext_scan_backop_flags_sta(mlmeext));\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_backop_flags_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\n\tchar tmp[32];\n\tu8 flags;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhx\", &flags);\n\n\t\tif (num == 1)\n\t\t\tmlmeext_assign_scan_backop_flags_sta(mlmeext, flags);\n\t}\n\n\treturn count;\n}\n\n#ifdef CONFIG_AP_MODE\nstatic int proc_get_backop_flags_ap(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\n\tRTW_PRINT_SEL(m, \"0x%02x\\n\", mlmeext_scan_backop_flags_ap(mlmeext));\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_backop_flags_ap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\n\tchar tmp[32];\n\tu8 flags;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhx\", &flags);\n\n\t\tif (num == 1)\n\t\t\tmlmeext_assign_scan_backop_flags_ap(mlmeext, flags);\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_AP_MODE */\n\n#ifdef CONFIG_RTW_MESH\nstatic int proc_get_backop_flags_mesh(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\n\tRTW_PRINT_SEL(m, \"0x%02x\\n\", mlmeext_scan_backop_flags_mesh(mlmeext));\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_backop_flags_mesh(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\n\tchar tmp[32];\n\tu8 flags;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhx\", &flags);\n\n\t\tif (num == 1)\n\t\t\tmlmeext_assign_scan_backop_flags_mesh(mlmeext, flags);\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_RTW_MESH */\n\n#endif /* CONFIG_SCAN_BACKOP */\n\n#if defined(CONFIG_LPS_PG) && defined(CONFIG_RTL8822C)\nstatic int proc_get_lps_pg_debug(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = rtw_netdev_priv(dev);\n\tstruct dm_struct *dm = adapter_to_phydm(adapter);\n\n\trtw_run_in_thread_cmd(adapter, ((void *)(odm_lps_pg_debug_8822c)), dm);\n\n\treturn 0;\n}\n#endif\n\n/* gpio setting */\n#ifdef CONFIG_GPIO_API\nstatic ssize_t proc_set_config_gpio(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32] = {0};\n\tint num = 0, gpio_pin = 0, gpio_mode = 0; /* gpio_mode:0 input  1:output; */\n\n\tif (count < 2)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tnum\t= sscanf(tmp, \"%d %d\", &gpio_pin, &gpio_mode);\n\t\tRTW_INFO(\"num=%d gpio_pin=%d mode=%d\\n\", num, gpio_pin, gpio_mode);\n\t\tpadapter->pre_gpio_pin = gpio_pin;\n\n\t\tif (gpio_mode == 0 || gpio_mode == 1)\n\t\t\trtw_hal_config_gpio(padapter, gpio_pin, gpio_mode);\n\t}\n\treturn count;\n\n}\nstatic ssize_t proc_set_gpio_output_value(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32] = {0};\n\tint num = 0, gpio_pin = 0, pin_mode = 0; /* pin_mode: 1 high         0:low */\n\n\tif (count < 2)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tnum\t= sscanf(tmp, \"%d %d\", &gpio_pin, &pin_mode);\n\t\tRTW_INFO(\"num=%d gpio_pin=%d pin_high=%d\\n\", num, gpio_pin, pin_mode);\n\t\tpadapter->pre_gpio_pin = gpio_pin;\n\n\t\tif (pin_mode == 0 || pin_mode == 1)\n\t\t\trtw_hal_set_gpio_output_value(padapter, gpio_pin, pin_mode);\n\t}\n\treturn count;\n}\nstatic int proc_get_gpio(struct seq_file *m, void *v)\n{\n\tu8 gpioreturnvalue = 0;\n\tstruct net_device *dev = m->private;\n\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tif (!padapter)\n\t\treturn -EFAULT;\n\tgpioreturnvalue = rtw_hal_get_gpio(padapter, padapter->pre_gpio_pin);\n\tRTW_PRINT_SEL(m, \"get_gpio %d:%d\\n\", padapter->pre_gpio_pin, gpioreturnvalue);\n\n\treturn 0;\n\n}\nstatic ssize_t proc_set_gpio(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32] = {0};\n\tint num = 0, gpio_pin = 0;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tnum\t= sscanf(tmp, \"%d\", &gpio_pin);\n\t\tRTW_INFO(\"num=%d gpio_pin=%d\\n\", num, gpio_pin);\n\t\tpadapter->pre_gpio_pin = gpio_pin;\n\n\t}\n\treturn count;\n}\n#endif\n\nstatic ssize_t proc_set_rx_info_msg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct recv_priv *precvpriv = &(padapter->recvpriv);\n\tchar tmp[32] = {0};\n\tint phy_info_flag = 0;\n\n\tif (!padapter)\n\t\treturn -EFAULT;\n\n\tif (count < 1) {\n\t\tRTW_INFO(\"argument size is less than 1\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%d\", &phy_info_flag);\n\n\t\tif (num == 1)\n\t\t\tprecvpriv->store_law_data_flag = (BOOLEAN) phy_info_flag;\n\n\t\t/*RTW_INFO(\"precvpriv->store_law_data_flag = %d\\n\",( BOOLEAN )(precvpriv->store_law_data_flag));*/\n\t}\n\treturn count;\n}\nstatic int proc_get_rx_info_msg(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\trtw_hal_set_odm_var(padapter, HAL_ODM_RX_Dframe_INFO, m, _FALSE);\n\treturn 0;\n}\nstatic int proc_get_tx_info_msg(struct seq_file *m, void *v)\n{\n\t_irqL irqL;\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct sta_info *psta;\n\tu8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tu8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct sta_priv *pstapriv = &padapter->stapriv;\n\tint i;\n\t_list\t*plist, *phead;\n\tu8 current_rate_id = 0, current_sgi = 0;\n\n\tchar *BW, *status;\n\n\t_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\tif (MLME_IS_STA(padapter))\n\t\tstatus = \"station mode\";\n\telse if (MLME_IS_AP(padapter))\n\t\tstatus = \"AP mode\";\n\telse if (MLME_IS_MESH(padapter))\n\t\tstatus = \"mesh mode\";\n\telse\n\t\tstatus = \" \";\n\t_RTW_PRINT_SEL(m, \"status=%s\\n\", status);\n\tfor (i = 0; i < NUM_STA; i++) {\n\t\tphead = &(pstapriv->sta_hash[i]);\n\t\tplist = get_next(phead);\n\n\t\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\n\t\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, hash_list);\n\n\t\t\tplist = get_next(plist);\n\n\t\t\tif ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)  !=  _TRUE)\n\t\t\t\t&& (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE)\n\t\t\t\t&& (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN) != _TRUE)) {\n\n\t\t\t\tswitch (psta->cmn.bw_mode) {\n\n\t\t\t\tcase CHANNEL_WIDTH_20:\n\t\t\t\t\tBW = \"20M\";\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase CHANNEL_WIDTH_40:\n\t\t\t\t\tBW = \"40M\";\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase CHANNEL_WIDTH_80:\n\t\t\t\t\tBW = \"80M\";\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase CHANNEL_WIDTH_160:\n\t\t\t\t\tBW = \"160M\";\n\t\t\t\t\tbreak;\n\n\t\t\t\tdefault:\n\t\t\t\t\tBW = \"\";\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tcurrent_rate_id = rtw_get_current_tx_rate(adapter, psta);\n\t\t\t\tcurrent_sgi = rtw_get_current_tx_sgi(adapter, psta);\n\n\t\t\t\tRTW_PRINT_SEL(m, \"==============================\\n\");\n\t\t\t\t_RTW_PRINT_SEL(m, \"macaddr=\" MAC_FMT\"\\n\", MAC_ARG(psta->cmn.mac_addr));\n\t\t\t\t_RTW_PRINT_SEL(m, \"Tx_Data_Rate=%s\\n\", HDATA_RATE(current_rate_id));\n\t\t\t\t_RTW_PRINT_SEL(m, \"BW=%s,sgi=%u\\n\", BW, current_sgi);\n\n\t\t\t}\n\t\t}\n\t}\n\n\t_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);\n\n\treturn 0;\n\n}\n\n\nstatic int proc_get_linked_info_dump(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tif (padapter)\n\t\tRTW_PRINT_SEL(m, \"linked_info_dump :%s\\n\", (padapter->bLinkInfoDump) ? \"enable\" : \"disable\");\n\n\treturn 0;\n}\n\n\nstatic ssize_t proc_set_linked_info_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tchar tmp[32] = {0};\n\tint mode = 0, pre_mode = 0;\n\tint num = 0;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tpre_mode = padapter->bLinkInfoDump;\n\tRTW_INFO(\"pre_mode=%d\\n\", pre_mode);\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tnum\t= sscanf(tmp, \"%d \", &mode);\n\t\tRTW_INFO(\"num=%d mode=%d\\n\", num, mode);\n\n\t\tif (num != 1) {\n\t\t\tRTW_INFO(\"argument number is wrong\\n\");\n\t\t\treturn -EFAULT;\n\t\t}\n\n\t\tif (mode == 1 || (mode == 0 && pre_mode == 1)) /* not consider pwr_saving 0: */\n\t\t\tpadapter->bLinkInfoDump = mode;\n\n\t\telse if ((mode == 2) || (mode == 0 && pre_mode == 2)) { /* consider power_saving */\n\t\t\t/* RTW_INFO(\"linked_info_dump =%s\\n\", (padapter->bLinkInfoDump)?\"enable\":\"disable\") */\n\t\t\tlinked_info_dump(padapter, mode);\n\t\t}\n\t}\n\treturn count;\n}\n\n\nstatic int proc_get_sta_tp_dump(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (padapter)\n\t\tRTW_PRINT_SEL(m, \"sta_tp_dump :%s\\n\", (padapter->bsta_tp_dump) ? \"enable\" : \"disable\");\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_sta_tp_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tchar tmp[32] = {0};\n\tint mode = 0;\n\tint num = 0;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tnum\t= sscanf(tmp, \"%d \", &mode);\n\n\t\tif (num != 1) {\n\t\t\tRTW_INFO(\"argument number is wrong\\n\");\n\t\t\treturn -EFAULT;\n\t\t}\n\t\tif (padapter)\n\t\t\tpadapter->bsta_tp_dump = mode;\n\t}\n\treturn count;\n}\n\nstatic int proc_get_sta_tp_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (padapter)\n\t\trtw_sta_traffic_info(m, padapter);\n\n\treturn 0;\n}\n\nstatic int proc_get_turboedca_ctrl(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);\n\n\tif (hal_data) {\n\n\t\tu32 edca_param;\n\n\t\tif (hal_data->dis_turboedca == 0)\n\t\t\tRTW_PRINT_SEL(m, \"Turbo-EDCA : %s\\n\", \"Enable\"); \n\t\telse \t\t\n\t\t\tRTW_PRINT_SEL(m, \"Turbo-EDCA : %s, mode=%d, edca_param_mode=0x%x\\n\", \"Disable\", hal_data->dis_turboedca, hal_data->edca_param_mode);\n\n\n\t\trtw_hal_get_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));\n\n\t\t_RTW_PRINT_SEL(m, \"PARAM_BE:0x%x\\n\", edca_param);\n\t\t\n\t}\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_turboedca_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);\n\tchar tmp[32] = {0};\n\tint mode = 0, num = 0;\n\tu32 param_mode = 0;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp))\n\t\treturn -EFAULT;\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tnum = sscanf(tmp, \"%d %x\", &mode, &param_mode);\n\n\t\tif (num < 1 || num > 2) {\n\t\t\tRTW_INFO(\"argument number is wrong\\n\");\n\t\t\treturn -EFAULT;\n\t\t}\n\n\t\t/*  0: enable turboedca,\n\t\t\t1: disable turboedca, \n\t\t\t2: disable turboedca and setting EDCA parameter based on the input parameter\n\t\t\t> 2 : currently reset to 0 */ \n\t\t\t\n\t\tif (mode > 2) \n\t\t\tmode = 0;\n\n\t\thal_data->dis_turboedca = mode;\n\t\t\n\t\thal_data->edca_param_mode = 0; /* init. value */\n\n\t\tRTW_INFO(\"dis_turboedca mode = 0x%x\\n\", hal_data->dis_turboedca);\n\t\t\n\t\tif (num == 2) {\n\n\t\t\thal_data->edca_param_mode = param_mode;\t\t\t\n\n\t\t\tRTW_INFO(\"param_mode = 0x%x\\n\", param_mode);\n\t\t}\n\t\t\n\t}\n\t\n\treturn count;\n\n}\n\nstatic int proc_get_mac_qinfo(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\trtw_hal_get_hwreg(adapter, HW_VAR_DUMP_MAC_QUEUE_INFO, (u8 *)m);\n\n\treturn 0;\n}\n\nint proc_get_wifi_spec(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv\t*pregpriv = &padapter->registrypriv;\n\n\tRTW_PRINT_SEL(m, \"wifi_spec=%d\\n\", pregpriv->wifi_spec);\n\treturn 0;\n}\n\nstatic int proc_get_chan_plan(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_cur_chset(m, adapter_to_rfctl(adapter));\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_chan_plan(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu8 chan_plan = RTW_CHPLAN_UNSPECIFIED;\n\n\tif (!padapter)\n\t\treturn -EFAULT;\n\n\tif (count < 1) {\n\t\tRTW_INFO(\"argument size is less than 1\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%hhx\", &chan_plan);\n\t\tif (num !=  1)\n\t\t\treturn count;\n\t}\n\n\trtw_set_channel_plan(padapter, chan_plan);\n\n\treturn count;\n}\n\nstatic int proc_get_country_code(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\n\tif (rfctl->country_ent)\n\t\tdump_country_chplan(m, rfctl->country_ent);\n\telse\n\t\tRTW_PRINT_SEL(m, \"unspecified\\n\");\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_country_code(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tchar alpha2[2];\n\tint num;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (!buffer || copy_from_user(tmp, buffer, count))\n\t\tgoto exit;\n\n\tnum = sscanf(tmp, \"%c%c\", &alpha2[0], &alpha2[1]);\n\tif (num !=\t2)\n\t\treturn count;\n\n\trtw_set_country(padapter, alpha2);\n\nexit:\n\treturn count;\n}\n\n#if CONFIG_RTW_MACADDR_ACL\nstatic int proc_get_macaddr_acl(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_macaddr_acl(m, adapter);\n\treturn 0;\n}\n\nssize_t proc_set_macaddr_acl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[17 * NUM_ACL + 32] = {0};\n\tu8 period;\n\tchar cmd[32];\n\tu8 mode;\n\tu8 addr[ETH_ALEN];\n\n#define MAC_ACL_CMD_MODE\t0\n#define MAC_ACL_CMD_ADD\t\t1\n#define MAC_ACL_CMD_DEL\t\t2\n#define MAC_ACL_CMD_CLR\t\t3\n#define MAC_ACL_CMD_NUM\t\t4\n\t\n\tstatic const char * const mac_acl_cmd_str[] = {\n\t\t\"mode\",\n\t\t\"add\",\n\t\t\"del\",\n\t\t\"clr\",\n\t};\n\tu8 cmd_id = MAC_ACL_CMD_NUM;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\t/*\n\t\t* <period> mode <mode> <macaddr> [<macaddr>]\n\t\t* <period> mode <mode>\n\t\t* <period> add <macaddr> [<macaddr>]\n\t\t* <period> del <macaddr> [<macaddr>]\n\t\t* <period> clr\n\t\t*/\n\t\tchar *c, *next;\n\t\tint i;\n\t\tu8 is_bcast;\n\n\t\tnext = tmp;\n\t\tc = strsep(&next, \" \\t\");\n\t\tif (!c || sscanf(c, \"%hhu\", &period) != 1)\n\t\t\tgoto exit;\n\n\t\tif (period >= RTW_ACL_PERIOD_NUM) {\n\t\t\tRTW_WARN(FUNC_ADPT_FMT\" invalid period:%u\", FUNC_ADPT_ARG(adapter), period);\n\t\t\tgoto exit;\n\t\t}\n\n\t\tc = strsep(&next, \" \\t\");\n\t\tif (!c || sscanf(c, \"%s\", cmd) != 1)\n\t\t\tgoto exit;\n\n\t\tfor (i = 0; i < MAC_ACL_CMD_NUM; i++)\n\t\t\tif (strcmp(mac_acl_cmd_str[i], cmd) == 0)\n\t\t\t\tcmd_id = i;\n\n\t\tswitch (cmd_id) {\n\t\tcase MAC_ACL_CMD_MODE:\n\t\t\tc = strsep(&next, \" \\t\");\n\t\t\tif (!c || sscanf(c, \"%hhu\", &mode) != 1)\n\t\t\t\tgoto exit;\n\n\t\t\tif (mode >= RTW_ACL_MODE_MAX) {\n\t\t\t\tRTW_WARN(FUNC_ADPT_FMT\" invalid mode:%u\", FUNC_ADPT_ARG(adapter), mode);\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase MAC_ACL_CMD_ADD:\n\t\tcase MAC_ACL_CMD_DEL:\n\t\t\tbreak;\n\n\t\tcase MAC_ACL_CMD_CLR:\n\t\t\t/* clear settings */\n\t\t\trtw_macaddr_acl_clear(adapter, period);\n\t\t\tgoto exit;\n\n\t\tdefault:\n\t\t\tRTW_WARN(FUNC_ADPT_FMT\" invalid cmd:\\\"%s\\\"\", FUNC_ADPT_ARG(adapter), cmd);\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* check for macaddr list */\n\t\tc = strsep(&next, \" \\t\");\n\t\tif (!c && cmd_id == MAC_ACL_CMD_MODE) {\n\t\t\t/* set mode only  */\n\t\t\trtw_set_macaddr_acl(adapter, period, mode);\n\t\t\tgoto exit;\n\t\t}\n\n\t\tif (cmd_id == MAC_ACL_CMD_MODE) {\n\t\t\t/* set mode and entire macaddr list */\n\t\t\trtw_macaddr_acl_clear(adapter, period);\n\t\t\trtw_set_macaddr_acl(adapter, period, mode);\n\t\t}\n\n\t\twhile (c != NULL) {\n\t\t\tif (sscanf(c, MAC_SFMT, MAC_SARG(addr)) != 6)\n\t\t\t\tbreak;\n\n\t\t\tis_bcast = is_broadcast_mac_addr(addr);\n\t\t\tif (is_bcast\n\t\t\t\t|| rtw_check_invalid_mac_address(addr, 0) == _FALSE\n\t\t\t) {\n\t\t\t\tif (cmd_id == MAC_ACL_CMD_DEL) {\n\t\t\t\t\trtw_acl_remove_sta(adapter, period, addr);\n\t\t\t\t\tif (is_bcast)\n\t\t\t\t\t\tbreak;\n\t\t\t\t } else if (!is_bcast)\n\t\t\t\t\trtw_acl_add_sta(adapter, period, addr);\n\t\t\t}\n\t\t\n\t\t\tc = strsep(&next, \" \\t\");\n\t\t}\n\t}\n\nexit:\n\treturn count;\n}\n#endif /* CONFIG_RTW_MACADDR_ACL */\n\n#if CONFIG_RTW_PRE_LINK_STA\nstatic int proc_get_pre_link_sta(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_pre_link_sta_ctl(m, &adapter->stapriv);\n\treturn 0;\n}\n\nssize_t proc_set_pre_link_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\tstruct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;\n\tchar tmp[17 * RTW_PRE_LINK_STA_NUM + 32] = {0};\n\tchar arg0[16] = {0};\n\tu8 addr[ETH_ALEN];\n\n#define PRE_LINK_STA_CMD_RESET\t0\n#define PRE_LINK_STA_CMD_ADD\t1\n#define PRE_LINK_STA_CMD_DEL\t2\n#define PRE_LINK_STA_CMD_NUM\t3\n\n\tstatic const char * const pre_link_sta_cmd_str[] = {\n\t\t\"reset\",\n\t\t\"add\",\n\t\t\"del\"\n\t};\n\tu8 cmd_id = PRE_LINK_STA_CMD_NUM;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\t/* cmd [<macaddr>] */\n\t\tchar *c, *next;\n\t\tint i;\n\n\t\tnext = tmp;\n\t\tc = strsep(&next, \" \\t\");\n\n\t\tif (sscanf(c, \"%s\", arg0) != 1)\n\t\t\tgoto exit;\n\n\t\tfor (i = 0; i < PRE_LINK_STA_CMD_NUM; i++)\n\t\t\tif (strcmp(pre_link_sta_cmd_str[i], arg0) == 0)\n\t\t\t\tcmd_id = i;\n\n\t\tswitch (cmd_id) {\n\t\tcase PRE_LINK_STA_CMD_RESET:\n\t\t\trtw_pre_link_sta_ctl_reset(&adapter->stapriv);\n\t\t\tgoto exit;\n\t\tcase PRE_LINK_STA_CMD_ADD:\n\t\tcase PRE_LINK_STA_CMD_DEL:\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* macaddr list */\n\t\tc = strsep(&next, \" \\t\");\n\t\twhile (c != NULL) {\n\t\t\tif (sscanf(c, MAC_SFMT, MAC_SARG(addr)) != 6)\n\t\t\t\tbreak;\n\n\t\t\tif (rtw_check_invalid_mac_address(addr, 0) == _FALSE) {\n\t\t\t\tif (cmd_id == PRE_LINK_STA_CMD_ADD)\n\t\t\t\t\trtw_pre_link_sta_add(&adapter->stapriv, addr);\n\t\t\t\telse\n\t\t\t\t\trtw_pre_link_sta_del(&adapter->stapriv, addr);\n\t\t\t}\n\n\t\t\tc = strsep(&next, \" \\t\");\n\t\t}\n\t}\n\nexit:\n\treturn count;\n}\n#endif /* CONFIG_RTW_PRE_LINK_STA */\n\nstatic int proc_get_ch_sel_policy(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\n\tRTW_PRINT_SEL(m, \"%-16s\\n\", \"same_band_prefer\");\n\n\tRTW_PRINT_SEL(m, \"%16u\\n\", rfctl->ch_sel_same_band_prefer);\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_ch_sel_policy(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tchar tmp[32];\n\tu8 sb_prefer;\n\tint num;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (!buffer || copy_from_user(tmp, buffer, count))\n\t\tgoto exit;\n\n\tnum = sscanf(tmp, \"%hhu\", &sb_prefer);\n\tif (num >=\t1)\n\t\trfctl->ch_sel_same_band_prefer = sb_prefer;\n\nexit:\n\treturn count;\n}\n\n#ifdef CONFIG_DFS_MASTER\nstatic int proc_get_dfs_test_case(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\n\tRTW_PRINT_SEL(m, \"%-24s %-19s\\n\", \"radar_detect_trigger_non\", \"choose_dfs_ch_first\");\n\tRTW_PRINT_SEL(m, \"%24hhu %19hhu\\n\"\n\t\t, rfctl->dbg_dfs_radar_detect_trigger_non\n\t\t, rfctl->dbg_dfs_choose_dfs_ch_first\n\t);\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_dfs_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tchar tmp[32];\n\tu8 radar_detect_trigger_non;\n\tu8 choose_dfs_ch_first;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%hhu %hhu\", &radar_detect_trigger_non, &choose_dfs_ch_first);\n\n\t\tif (num >= 1)\n\t\t\trfctl->dbg_dfs_radar_detect_trigger_non = radar_detect_trigger_non;\n\t\tif (num >= 2)\n\t\t\trfctl->dbg_dfs_choose_dfs_ch_first = choose_dfs_ch_first;\n\t}\n\n\treturn count;\n}\n\nssize_t proc_set_update_non_ocp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tchar tmp[32];\n\tu8 ch, bw = CHANNEL_WIDTH_20, offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\n\tint ms = -1;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhu %hhu %hhu %d\", &ch, &bw, &offset, &ms);\n\n\t\tif (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3))\n\t\t\tgoto exit;\n\n\t\tif (bw == CHANNEL_WIDTH_20)\n\t\t\trtw_chset_update_non_ocp_ms(rfctl->channel_set\n\t\t\t\t, ch, bw, HAL_PRIME_CHNL_OFFSET_DONT_CARE, ms);\n\t\telse\n\t\t\trtw_chset_update_non_ocp_ms(rfctl->channel_set\n\t\t\t\t, ch, bw, offset, ms);\n\t}\n\nexit:\n\treturn count;\n}\n\nssize_t proc_set_radar_detect(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tchar tmp[32];\n\tu8 fake_radar_detect_cnt = 0;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhu\", &fake_radar_detect_cnt);\n\n\t\tif (num < 1)\n\t\t\tgoto exit;\n\n\t\trfctl->dbg_dfs_fake_radar_detect_cnt = fake_radar_detect_cnt;\n\t}\n\nexit:\n\treturn count;\n}\n\nstatic int proc_get_dfs_ch_sel_d_flags(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\n\tRTW_PRINT_SEL(m, \"0x%02x\\n\", rfctl->dfs_ch_sel_d_flags);\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_dfs_ch_sel_d_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tchar tmp[32];\n\tu8 d_flags;\n\tint num;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (!buffer || copy_from_user(tmp, buffer, count))\n\t\tgoto exit;\n\n\tnum = sscanf(tmp, \"%hhx\", &d_flags);\n\tif (num != 1)\n\t\tgoto exit;\n\n\trfctl->dfs_ch_sel_d_flags = d_flags;\n\nexit:\n\treturn count;\n}\n\n#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT\nstatic int proc_get_dfs_slave_with_rd(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\n\tRTW_PRINT_SEL(m, \"%u\\n\", rfctl->dfs_slave_with_rd);\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_dfs_slave_with_rd(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);\n\tchar tmp[32];\n\tu8 rd;\n\tint num;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (!buffer || copy_from_user(tmp, buffer, count))\n\t\tgoto exit;\n\n\tnum = sscanf(tmp, \"%hhu\", &rd);\n\tif (num != 1)\n\t\tgoto exit;\n\n\trd = rd ? 1 : 0;\n\n\tif (rfctl->dfs_slave_with_rd != rd) {\n\t\trfctl->dfs_slave_with_rd = rd;\n\t\trtw_dfs_rd_en_decision_cmd(adapter);\n\t}\n\nexit:\n\treturn count;\n}\n#endif /* CONFIG_DFS_SLAVE_WITH_RADAR_DETECT */\n#endif /* CONFIG_DFS_MASTER */\n\n#ifdef CONFIG_80211N_HT\nint proc_get_rx_ampdu_size_limit(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_regsty_rx_ampdu_size_limit(m, adapter);\n\n\treturn 0;\n}\n\nssize_t proc_set_rx_ampdu_size_limit(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv *regsty = adapter_to_regsty(adapter);\n\tchar tmp[32];\n\tu8 nss;\n\tu8 limit_by_bw[4] = {0xFF};\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint i;\n\t\tint num = sscanf(tmp, \"%hhu %hhu %hhu %hhu %hhu\"\n\t\t\t, &nss, &limit_by_bw[0], &limit_by_bw[1], &limit_by_bw[2], &limit_by_bw[3]);\n\n\t\tif (num < 2)\n\t\t\tgoto exit;\n\t\tif (nss == 0 || nss > 4)\n\t\t\tgoto exit;\n\n\t\tfor (i = 0; i < num - 1; i++)\n\t\t\tregsty->rx_ampdu_sz_limit_by_nss_bw[nss - 1][i] = limit_by_bw[i];\n\n\t\trtw_rx_ampdu_apply(adapter);\n\t}\n\nexit:\n\treturn count;\n}\n#endif /* CONFIG_80211N_HT */\n\nstatic int proc_get_rx_chk_limit(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_PRINT_SEL(m, \"Rx chk limit : %d\\n\", rtw_get_rx_chk_limit(padapter));\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_rx_chk_limit(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tchar tmp[32];\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tint rx_chk_limit;\n\n\tif (count < 1) {\n\t\tRTW_INFO(\"argument size is less than 1\\n\");\n\t\treturn -EFAULT;\n\t}\n\t\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%d\", &rx_chk_limit);\n\n\t\trtw_set_rx_chk_limit(padapter, rx_chk_limit);\n\t}\n\n\treturn count;\n}\n\nstatic int proc_get_udpport(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct recv_priv *precvpriv = &(padapter->recvpriv);\n\n\tRTW_PRINT_SEL(m, \"%d\\n\", precvpriv->sink_udpport);\n\treturn 0;\n}\nstatic ssize_t proc_set_udpport(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct recv_priv *precvpriv = &(padapter->recvpriv);\n\tint sink_udpport = 0;\n\tchar tmp[32];\n\n\n\tif (!padapter)\n\t\treturn -EFAULT;\n\n\tif (count < 1) {\n\t\tRTW_INFO(\"argument size is less than 1\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%d\", &sink_udpport);\n\n\t\tif (num !=  1) {\n\t\t\tRTW_INFO(\"invalid input parameter number!\\n\");\n\t\t\treturn count;\n\t\t}\n\n\t}\n\tprecvpriv->sink_udpport = sink_udpport;\n\n\treturn count;\n\n}\n\nstatic int proc_get_mi_ap_bc_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\tu8 i;\n\n\tfor (i = 0; i < dvobj->iface_nums; i++)\n\t\tRTW_PRINT_SEL(m, \"iface_id:%d, mac_id && sec_cam_id = %d\\n\", i, macid_ctl->iface_bmc[i]);\n\n\treturn 0;\n}\nstatic int proc_get_macid_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\tu8 i;\n\tu8 null_addr[ETH_ALEN] = {0};\n\tu8 *macaddr;\n\n\tRTW_PRINT_SEL(m, \"max_num:%u\\n\", macid_ctl->num);\n\tRTW_PRINT_SEL(m, \"\\n\");\n\n\tRTW_PRINT_SEL(m, \"used:\\n\");\n\tdump_macid_map(m, &macid_ctl->used, macid_ctl->num);\n\tRTW_PRINT_SEL(m, \"\\n\");\n\n\tRTW_PRINT_SEL(m, \"%-3s %-3s %-5s %-4s %-17s %-6s %-3s\"\n\t\t, \"id\", \"bmc\", \"ifbmp\", \"ch_g\", \"macaddr\", \"bw\", \"vht\");\n\n\tif (hal_spec->tx_nss_num > 2)\n\t\t_RTW_PRINT_SEL(m, \" %-10s\", \"rate_bmp1\");\n\n\t_RTW_PRINT_SEL(m, \" %-10s %s\\n\", \"rate_bmp0\", \"status\");\n\n\tfor (i = 0; i < macid_ctl->num; i++) {\n\t\tif (rtw_macid_is_used(macid_ctl, i)\n\t\t\t|| macid_ctl->h2c_msr[i]\n\t\t) {\n\t\t\tif (macid_ctl->sta[i])\n\t\t\t\tmacaddr = macid_ctl->sta[i]->cmn.mac_addr;\n\t\t\telse\n\t\t\t\tmacaddr = null_addr;\n\n\t\t\tRTW_PRINT_SEL(m, \"%3u %3u  0x%02x %4d \"MAC_FMT\" %6s %3u\"\n\t\t\t\t, i\n\t\t\t\t, rtw_macid_is_bmc(macid_ctl, i)\n\t\t\t\t, rtw_macid_get_iface_bmp(macid_ctl, i)\n\t\t\t\t, rtw_macid_get_ch_g(macid_ctl, i)\n\t\t\t\t, MAC_ARG(macaddr)\n\t\t\t\t, ch_width_str(macid_ctl->bw[i])\n\t\t\t\t, macid_ctl->vht_en[i]\n\t\t\t);\n\n\t\t\tif (hal_spec->tx_nss_num > 2)\n\t\t\t\t_RTW_PRINT_SEL(m, \" 0x%08X\", macid_ctl->rate_bmp1[i]);\n\n\t\t\t_RTW_PRINT_SEL(m, \" 0x%08X \"H2C_MSR_FMT\" %s\\n\"\n\t\t\t\t, macid_ctl->rate_bmp0[i]\n\t\t\t\t, H2C_MSR_ARG(&macid_ctl->h2c_msr[i])\n\t\t\t\t, rtw_macid_is_used(macid_ctl, i) ? \"\" : \"[unused]\"\n\t\t\t);\n\t\t}\n\t}\n\tRTW_PRINT_SEL(m, \"\\n\");\n\n\tfor (i = 0; i < H2C_MSR_ROLE_MAX; i++) {\n\t\tif (macid_ctl->op_num[i]) {\n\t\t\tRTW_PRINT_SEL(m, \"%-5s op_num:%u\\n\"\n\t\t\t\t, h2c_msr_role_str(i), macid_ctl->op_num[i]);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int proc_get_sec_cam(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\n\tRTW_PRINT_SEL(m, \"sec_cap:0x%02x\\n\", cam_ctl->sec_cap);\n\tRTW_PRINT_SEL(m, \"flags:0x%08x\\n\", cam_ctl->flags);\n\tRTW_PRINT_SEL(m, \"\\n\");\n\n\tRTW_PRINT_SEL(m, \"max_num:%u\\n\", cam_ctl->num);\n\tRTW_PRINT_SEL(m, \"used:\\n\");\n\tdump_sec_cam_map(m, &cam_ctl->used, cam_ctl->num);\n\tRTW_PRINT_SEL(m, \"\\n\");\n\n\tRTW_PRINT_SEL(m, \"reg_scr:0x%04x\\n\", rtw_read16(adapter, 0x680));\n\tRTW_PRINT_SEL(m, \"\\n\");\n\n\tdump_sec_cam(m, adapter);\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_sec_cam(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;\n\tchar tmp[32] = {0};\n\tchar cmd[4];\n\tu8 id_1 = 0, id_2 = 0;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\t/* c <id_1>: clear specific cam entry */\n\t\t/* wfc <id_1>: write specific cam entry from cam cache */\n\t\t/* sw <id_1> <id_2>: sec_cam 1/2 swap */\n\n\t\tint num = sscanf(tmp, \"%s %hhu %hhu\", cmd, &id_1, &id_2);\n\n\t\tif (num < 2)\n\t\t\treturn count;\n\n\t\tif ((id_1 >= cam_ctl->num) || (id_2 >= cam_ctl->num)) {\n\t\t\tRTW_ERR(FUNC_ADPT_FMT\" invalid id_1:%u id_2:%u\\n\", FUNC_ADPT_ARG(adapter), id_1, id_2);\n\t\t\treturn count;\n\t\t}\n\n\t\tif (strcmp(\"c\", cmd) == 0) {\n\t\t\t_clear_cam_entry(adapter, id_1);\n\t\t\tadapter->securitypriv.hw_decrypted = _FALSE; /* temporarily set this for TX path to use SW enc */\n\t\t} else if (strcmp(\"wfc\", cmd) == 0)\n\t\t\twrite_cam_from_cache(adapter, id_1);\n\t\telse if (strcmp(\"sw\", cmd) == 0)\n\t\t\trtw_sec_cam_swap(adapter, id_1, id_2);\n\t\telse if (strcmp(\"cdk\", cmd) == 0)\n\t\t\trtw_clean_dk_section(adapter);\n#ifdef DBG_SEC_CAM_MOVE\n\t\telse if (strcmp(\"sgd\", cmd) == 0)\n\t\t\trtw_hal_move_sta_gk_to_dk(adapter);\n\t\telse if (strcmp(\"rsd\", cmd) == 0)\n\t\t\trtw_hal_read_sta_dk_key(adapter, id_1);\n#endif\n\t}\n\n\treturn count;\n}\n\nstatic int proc_get_sec_cam_cache(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_sec_cam_cache(m, adapter);\n\treturn 0;\n}\n\nstatic ssize_t proc_set_change_bss_chbw(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tint i;\n\tchar tmp[32];\n\ts16 ch;\n\ts8 bw = REQ_BW_NONE, offset = REQ_OFFSET_NONE;\n\tu8 ifbmp = 0;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hd %hhd %hhd %hhx\", &ch, &bw, &offset, &ifbmp);\n\n\t\tif (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3))\n\t\t\tgoto exit;\n\n\t\tif (num < 4)\n\t\t\tifbmp = BIT(adapter->iface_id);\n\t\telse\n\t\t\tifbmp &= (1 << dvobj->iface_nums) - 1;\n\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tif (!(ifbmp & BIT(i)) || !dvobj->padapters[i])\n\t\t\t\tcontinue;\n\n\t\t\tif (!CHK_MLME_STATE(dvobj->padapters[i], WIFI_AP_STATE | WIFI_MESH_STATE)\n\t\t\t\t|| !MLME_IS_ASOC(dvobj->padapters[i]))\n\t\t\t\tifbmp &= ~BIT(i);\n\t\t}\n\n\t\tif (ifbmp)\n\t\t\trtw_change_bss_chbw_cmd(adapter, RTW_CMDF_WAIT_ACK, ifbmp, 0, ch, bw, offset);\n\t}\n\nexit:\n\treturn count;\n}\n\n#if CONFIG_TX_AC_LIFETIME\nstatic int proc_get_tx_aclt_force_val(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\n\tdump_tx_aclt_force_val(m, dvobj);\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_tx_aclt_force_val(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = rtw_netdev_priv(dev);\n\tchar tmp[32] = {0};\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\t\tstruct tx_aclt_conf_t input;\n\t\tint num = sscanf(tmp, \"%hhx %u %u\", &input.en, &input.vo_vi, &input.be_bk);\n\n\t\tif (num < 1)\n\t\t\treturn count;\n\n\t\trtw_hal_set_tx_aclt_force_val(adapter, &input, num);\n\t\trtw_run_in_thread_cmd(adapter, ((void *)(rtw_hal_update_tx_aclt)), adapter);\n\t}\n\n\treturn count;\n}\n\nstatic int proc_get_tx_aclt_flags(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\n\tRTW_PRINT_SEL(m, \"0x%02x\\n\", dvobj->tx_aclt_flags);\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_tx_aclt_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = rtw_netdev_priv(dev);\n\tchar tmp[32] = {0};\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\t\tu8 flags;\n\t\tint num = sscanf(tmp, \"%hhx\", &flags);\n\n\t\tif (num < 1)\n\t\t\treturn count;\n\n\t\tif (dvobj->tx_aclt_flags == flags)\n\t\t\treturn count;\n\n\t\tdvobj->tx_aclt_flags = flags;\n\n\t\trtw_run_in_thread_cmd(adapter, ((void *)(rtw_hal_update_tx_aclt)), adapter);\n\t}\n\n\treturn count;\n}\n\nstatic int proc_get_tx_aclt_confs(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\n\tRTW_PRINT_SEL(m, \"flags:0x%02x\\n\", dvobj->tx_aclt_flags);\n\tdump_tx_aclt_confs(m, dvobj);\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_tx_aclt_confs(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = rtw_netdev_priv(dev);\n\tchar tmp[32] = {0};\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\t\tu8 id;\n\t\tstruct tx_aclt_conf_t input;\n\t\tint num = sscanf(tmp, \"%hhu %hhx %u %u\", &id, &input.en, &input.vo_vi, &input.be_bk);\n\n\t\tif (num < 2)\n\t\t\treturn count;\n\n\t\trtw_hal_set_tx_aclt_conf(adapter, id, &input, num - 1);\n\t\trtw_run_in_thread_cmd(adapter, ((void *)(rtw_hal_update_tx_aclt)), adapter);\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_TX_AC_LIFETIME */\n\nstatic int proc_get_tx_bw_mode(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tRTW_PRINT_SEL(m, \"0x%02x\\n\", adapter->driver_tx_bw_mode);\n\tRTW_PRINT_SEL(m, \"2.4G:%s\\n\", ch_width_str(ADAPTER_TX_BW_2G(adapter)));\n\tRTW_PRINT_SEL(m, \"5G:%s\\n\", ch_width_str(ADAPTER_TX_BW_5G(adapter)));\n\n\treturn 0;\n}\n\nstatic void rtw_set_tx_bw_mode(struct _ADAPTER *adapter, u8 bw_mode)\n{\n\tstruct mlme_priv *mlme = &(adapter->mlmepriv);\n\tstruct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv);\n\tstruct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;\n\tu8 update = _FALSE;\n\n\tif ((MLME_STATE(adapter) & WIFI_ASOC_STATE)\n\t\t&& ((mlmeext->cur_channel <= 14 && BW_MODE_2G(bw_mode) != ADAPTER_TX_BW_2G(adapter))\n\t\t\t|| (mlmeext->cur_channel >= 36 && BW_MODE_5G(bw_mode) != ADAPTER_TX_BW_5G(adapter)))\n\t) {\n\t\t/* RA mask update needed */\n\t\tupdate = _TRUE;\n\t}\t\t\n\tadapter->driver_tx_bw_mode = bw_mode;\n\n\tif (update == _TRUE) {\n\t\tstruct sta_info *sta;\n\t\tint i;\n\n\t\tfor (i = 0; i < MACID_NUM_SW_LIMIT; i++) {\n\t\t\tsta = macid_ctl->sta[i];\n\t\t\tif (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr))\n\t\t\t\trtw_dm_ra_mask_wk_cmd(adapter, (u8 *)sta);\n\t\t}\n\t}\n}\n\nstatic ssize_t proc_set_tx_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu8 bw_mode;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhx\", &bw_mode);\n\n\t\tif (num < 1 || bw_mode == adapter->driver_tx_bw_mode)\n\t\t\tgoto exit;\n\n\t\trtw_set_tx_bw_mode(adapter, bw_mode);\n\t}\n\nexit:\n\treturn count;\n}\n\nstatic int proc_get_hal_txpwr_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);\n\n\tif (hal_is_band_support(adapter, BAND_ON_2_4G))\n\t\tdump_hal_txpwr_info_2g(m, adapter, hal_spec->rfpath_num_2g, hal_spec->max_tx_cnt);\n\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\tif (hal_is_band_support(adapter, BAND_ON_5G))\n\t\tdump_hal_txpwr_info_5g(m, adapter, hal_spec->rfpath_num_5g, hal_spec->max_tx_cnt);\n#endif\n\n\treturn 0;\n}\n\nstatic int proc_get_target_tx_power(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_target_tx_power(m, adapter);\n\n\treturn 0;\n}\n\nstatic int proc_get_tx_power_by_rate(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_tx_power_by_rate(m, adapter);\n\n\treturn 0;\n}\n\n#if CONFIG_TXPWR_LIMIT\nstatic int proc_get_tx_power_limit(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_txpwr_lmt(m, adapter);\n\n\treturn 0;\n}\n#endif /* CONFIG_TXPWR_LIMIT */\n\nstatic int proc_get_tx_power_ext_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_tx_power_ext_info(m, adapter);\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_tx_power_ext_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tchar tmp[32] = {0};\n\tchar cmd[16] = {0};\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%s\", cmd);\n\n\t\tif (num < 1)\n\t\t\treturn count;\n\n\t\t#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\n\t\tphy_free_filebuf_mask(adapter, LOAD_BB_PG_PARA_FILE | LOAD_RF_TXPWR_LMT_PARA_FILE);\n\t\t#endif\n\n\t\trtw_ps_deny(adapter, PS_DENY_IOCTL);\n\t\tif (rtw_pwr_wakeup(adapter) == _FALSE)\n\t\t\tgoto clear_ps_deny;\n\n\t\tif (strcmp(\"default\", cmd) == 0)\n\t\t\trtw_run_in_thread_cmd(adapter, ((void *)(phy_reload_default_tx_power_ext_info)), adapter);\n\t\telse\n\t\t\trtw_run_in_thread_cmd(adapter, ((void *)(phy_reload_tx_power_ext_info)), adapter);\n\nclear_ps_deny:\n\t\trtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);\n\t}\n\n\treturn count;\n}\n\nstatic void *proc_start_tx_power_idx(struct seq_file *m, loff_t *pos)\n{\n\tu8 path = ((*pos) & 0xFF00) >> 8;\n\n\tif (path >= RF_PATH_MAX)\n\t\treturn NULL;\n\n\treturn pos;\n}\nstatic void proc_stop_tx_power_idx(struct seq_file *m, void *v)\n{\n}\n\nstatic void *proc_next_tx_power_idx(struct seq_file *m, void *v, loff_t *pos)\n{\n\tu8 path = ((*pos) & 0xFF00) >> 8;\n\tu8 rs = *pos & 0xFF;\n\n\trs++;\n\tif (rs >= RATE_SECTION_NUM) {\n\t\trs = 0;\n\t\tpath++;\n\t}\n\n\tif (path >= RF_PATH_MAX)\n\t\treturn NULL;\n\n\t*pos = (path << 8) | rs;\n\n\treturn pos;\n}\n\nstatic int proc_get_tx_power_idx(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tu32 pos = *((loff_t *)(v));\n\tu8 path = (pos & 0xFF00) >> 8;\n\tu8 rs = pos & 0xFF;\n\n\tif (0)\n\t\tRTW_INFO(\"%s path=%u, rs=%u\\n\", __func__, path, rs);\n\n\tif (path == RF_PATH_A && rs == CCK)\n\t\tdump_tx_power_idx_title(m, adapter);\n\tdump_tx_power_idx_by_path_rs(m, adapter, path, rs);\n\n\treturn 0;\n}\n\nstatic struct seq_operations seq_ops_tx_power_idx = {\n\t.start = proc_start_tx_power_idx,\n\t.stop  = proc_stop_tx_power_idx,\n\t.next  = proc_next_tx_power_idx,\n\t.show  = proc_get_tx_power_idx,\n};\n\n#ifdef CONFIG_RF_POWER_TRIM\nstatic int proc_get_kfree_flag(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);\n\n\tRTW_PRINT_SEL(m, \"0x%02x\\n\", kfree_data->flag);\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_kfree_flag(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);\n\tchar tmp[32] = {0};\n\tu8 flag;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhx\", &flag);\n\n\t\tif (num < 1)\n\t\t\treturn count;\n\n\t\tkfree_data->flag = flag;\n\t}\n\n\treturn count;\n}\n\nstatic int proc_get_kfree_bb_gain(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tHAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);\n\tstruct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);\n\tu8 i, j;\n\n\tfor (i = 0; i < BB_GAIN_NUM; i++) {\n\t\tif (i == 0)\n\t\t\t_RTW_PRINT_SEL(m, \"2G: \");\n\t\telse if (i == 1)\n\t\t\t_RTW_PRINT_SEL(m, \"5GLB1: \");\n\t\telse if (i == 2)\n\t\t\t_RTW_PRINT_SEL(m, \"5GLB2: \");\n\t\telse if (i == 3)\n\t\t\t_RTW_PRINT_SEL(m, \"5GMB1: \");\n\t\telse if (i == 4)\n\t\t\t_RTW_PRINT_SEL(m, \"5GMB2: \");\n\t\telse if (i == 5)\n\t\t\t_RTW_PRINT_SEL(m, \"5GHB: \");\n\n\t\tfor (j = 0; j < hal_data->NumTotalRFPath; j++)\n\t\t\t_RTW_PRINT_SEL(m, \"%d \", kfree_data->bb_gain[i][j]);\n\t\t_RTW_PRINT_SEL(m, \"\\n\");\n\t}\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_kfree_bb_gain(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);\n\tchar tmp[BB_GAIN_NUM * RF_PATH_MAX] = {0};\n\tu8 chidx;\n\ts8 bb_gain[BB_GAIN_NUM];\n\tchar ch_band_Group[6];\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tchar *c, *next;\n\t\tint i = 0;\n\n\t\tnext = tmp;\n\t\tc = strsep(&next, \" \\t\");\n\n\t\tif (sscanf(c, \"%s\", ch_band_Group) != 1) {\n\t\t\tRTW_INFO(\"Error Head Format, channel Group select\\n,Please input:\\t 2G , 5GLB1 , 5GLB2 , 5GMB1 , 5GMB2 , 5GHB\\n\");\n\t\t\treturn count;\n\t\t}\n\t\tif (strcmp(\"2G\", ch_band_Group) == 0)\n\t\t\tchidx = BB_GAIN_2G;\n#ifdef CONFIG_IEEE80211_BAND_5GHZ\n\t\telse if (strcmp(\"5GLB1\", ch_band_Group) == 0)\n\t\t\tchidx = BB_GAIN_5GLB1;\n\t\telse if (strcmp(\"5GLB2\", ch_band_Group) == 0)\n\t\t\tchidx = BB_GAIN_5GLB2;\n\t\telse if (strcmp(\"5GMB1\", ch_band_Group) == 0)\n\t\t\tchidx = BB_GAIN_5GMB1;\n\t\telse if (strcmp(\"5GMB2\", ch_band_Group) == 0)\n\t\t\tchidx = BB_GAIN_5GMB2;\n\t\telse if (strcmp(\"5GHB\", ch_band_Group) == 0)\n\t\t\tchidx = BB_GAIN_5GHB;\n#endif /*CONFIG_IEEE80211_BAND_5GHZ*/\n\t\telse {\n\t\t\tRTW_INFO(\"Error Head Format, channel Group select\\n,Please input:\\t 2G , 5GLB1 , 5GLB2 , 5GMB1 , 5GMB2 , 5GHB\\n\");\n\t\t\treturn count;\n\t\t}\n\t\tc = strsep(&next, \" \\t\");\n\n\t\twhile (c != NULL) {\n\t\t\tif (sscanf(c, \"%hhx\", &bb_gain[i]) != 1)\n\t\t\t\tbreak;\n\n\t\t\tkfree_data->bb_gain[chidx][i] = bb_gain[i];\n\t\t\tRTW_INFO(\"%s,kfree_data->bb_gain[%d][%d]=%x\\n\", __func__, chidx, i, kfree_data->bb_gain[chidx][i]);\n\n\t\t\tc = strsep(&next, \" \\t\");\n\t\t\ti++;\n\t\t}\n\n\t}\n\n\treturn count;\n\n}\n\nstatic int proc_get_kfree_thermal(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);\n\n\t_RTW_PRINT_SEL(m, \"%d\\n\", kfree_data->thermal);\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_kfree_thermal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);\n\tchar tmp[32] = {0};\n\ts8 thermal;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhd\", &thermal);\n\n\t\tif (num < 1)\n\t\t\treturn count;\n\n\t\tkfree_data->thermal = thermal;\n\t}\n\n\treturn count;\n}\n\nstatic ssize_t proc_set_tx_gain_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter;\n\tchar tmp[32] = {0};\n\tu8 rf_path;\n\ts8 offset;\n\n\tadapter = (_adapter *)rtw_netdev_priv(dev);\n\tif (!adapter)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = sscanf(tmp, \"%hhu %hhd\", &rf_path, &offset);\n\n\t\tif (num < 2)\n\t\t\treturn count;\n\n\t\tRTW_INFO(\"write rf_path:%u tx gain offset:%d\\n\", rf_path, offset);\n\t\trtw_rf_set_tx_gain_offset(adapter, rf_path, offset);\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_RF_POWER_TRIM */\n\n#ifdef CONFIG_BT_COEXIST\nssize_t proc_set_btinfo_evt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu8 btinfo[8];\n\n\tif (count < 6)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tint num = 0;\n\n\t\t_rtw_memset(btinfo, 0, 8);\n\n\t\tnum = sscanf(tmp, \"%hhx %hhx %hhx %hhx %hhx %hhx %hhx %hhx\"\n\t\t\t, &btinfo[0], &btinfo[1], &btinfo[2], &btinfo[3]\n\t\t\t, &btinfo[4], &btinfo[5], &btinfo[6], &btinfo[7]);\n\n\t\tif (num < 6)\n\t\t\treturn -EINVAL;\n\n\t\tbtinfo[1] = num - 2;\n\n\t\trtw_btinfo_cmd(padapter, btinfo, btinfo[1] + 2);\n\t}\n\n\treturn count;\n}\n\nstatic u8 btreg_read_type = 0;\nstatic u16 btreg_read_addr = 0;\nstatic int btreg_read_error = 0;\nstatic u8 btreg_write_type = 0;\nstatic u16 btreg_write_addr = 0;\nstatic int btreg_write_error = 0;\n\nstatic u8 *btreg_type[] = {\n\t\"rf\",\n\t\"modem\",\n\t\"bluewize\",\n\t\"vendor\",\n\t\"le\"\n};\n\nstatic int btreg_parse_str(char const *input, u8 *type, u16 *addr, u16 *val)\n{\n\tu32 num;\n\tu8 str[80] = {0};\n\tu8 t = 0;\n\tu32 a, v;\n\tu8 i, n;\n\tu8 *p;\n\n\n\tnum = sscanf(input, \"%s %x %x\", str, &a, &v);\n\tif (num < 2) {\n\t\tRTW_INFO(\"%s: INVALID input!(%s)\\n\", __FUNCTION__, input);\n\t\treturn -EINVAL;\n\t}\n\tif ((num < 3) && val) {\n\t\tRTW_INFO(\"%s: INVALID input!(%s)\\n\", __FUNCTION__, input);\n\t\treturn -EINVAL;\n\t}\n\n\t/* convert to lower case for following type compare */\n\tp = str;\n\tfor (; *p; ++p)\n\t\t*p = tolower(*p);\n\tn = sizeof(btreg_type) / sizeof(btreg_type[0]);\n\tfor (i = 0; i < n; i++) {\n\t\tif (!strcmp(str, btreg_type[i])) {\n\t\t\tt = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (i == n) {\n\t\tRTW_INFO(\"%s: unknown type(%s)!\\n\", __FUNCTION__, str);\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (t) {\n\tcase 0:\n\t\t/* RF */\n\t\tif (a & 0xFFFFFF80) {\n\t\t\tRTW_INFO(\"%s: INVALID address(0x%X) for type %s(%d)!\\n\",\n\t\t\t\t __FUNCTION__, a, btreg_type[t], t);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tbreak;\n\tcase 1:\n\t\t/* Modem */\n\t\tif (a & 0xFFFFFE00) {\n\t\t\tRTW_INFO(\"%s: INVALID address(0x%X) for type %s(%d)!\\n\",\n\t\t\t\t __FUNCTION__, a, btreg_type[t], t);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\t/* Others(Bluewize, Vendor, LE) */\n\t\tif (a & 0xFFFFF000) {\n\t\t\tRTW_INFO(\"%s: INVALID address(0x%X) for type %s(%d)!\\n\",\n\t\t\t\t __FUNCTION__, a, btreg_type[t], t);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tbreak;\n\t}\n\n\tif (val) {\n\t\tif (v & 0xFFFF0000) {\n\t\t\tRTW_INFO(\"%s: INVALID value(0x%x)!\\n\", __FUNCTION__, v);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\t*val = (u16)v;\n\t}\n\n\t*type = (u8)t;\n\t*addr = (u16)a;\n\n\treturn 0;\n}\n\nint proc_get_btreg_read(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev;\n\tPADAPTER padapter;\n\tu16 ret;\n\tu32 data;\n\n\n\tif (btreg_read_error)\n\t\treturn btreg_read_error;\n\n\tdev = m->private;\n\tpadapter = (PADAPTER)rtw_netdev_priv(dev);\n\n\tret = rtw_btcoex_btreg_read(padapter, btreg_read_type, btreg_read_addr, &data);\n\tif (CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS))\n\t\tRTW_PRINT_SEL(m, \"BTREG read: (%s)0x%04X = 0x%08x\\n\", btreg_type[btreg_read_type], btreg_read_addr, data);\n\telse\n\t\tRTW_PRINT_SEL(m, \"BTREG read: (%s)0x%04X read fail. error code = 0x%04x.\\n\", btreg_type[btreg_read_type], btreg_read_addr, ret);\n\n\treturn 0;\n}\n\nssize_t proc_set_btreg_read(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\tPADAPTER padapter;\n\tu8 tmp[80] = {0};\n\tu32 num;\n\tint err;\n\n\n\tpadapter = (PADAPTER)rtw_netdev_priv(dev);\n\n\tif (NULL == buffer) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input buffer is NULL!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter));\n\t\terr = -EFAULT;\n\t\tgoto exit;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is 0!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter));\n\t\terr = -EFAULT;\n\t\tgoto exit;\n\t}\n\n\tnum = count;\n\tif (num > (sizeof(tmp) - 1))\n\t\tnum = (sizeof(tmp) - 1);\n\n\tif (copy_from_user(tmp, buffer, num)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": copy buffer from user space FAIL!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter));\n\t\terr = -EFAULT;\n\t\tgoto exit;\n\t}\n\t/* [Coverity] sure tmp end with '\\0'(string terminal) */\n\ttmp[sizeof(tmp) - 1] = 0;\n\n\terr = btreg_parse_str(tmp, &btreg_read_type, &btreg_read_addr, NULL);\n\tif (err)\n\t\tgoto exit;\n\n\tRTW_INFO(FUNC_ADPT_FMT \": addr=(%s)0x%X\\n\",\n\t\tFUNC_ADPT_ARG(padapter), btreg_type[btreg_read_type], btreg_read_addr);\n\nexit:\n\tbtreg_read_error = err;\n\n\treturn count;\n}\n\nint proc_get_btreg_write(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev;\n\tPADAPTER padapter;\n\tu16 ret;\n\tu32 data;\n\n\n\tif (btreg_write_error < 0)\n\t\treturn btreg_write_error;\n\telse if (btreg_write_error > 0) {\n\t\tRTW_PRINT_SEL(m, \"BTREG write: (%s)0x%04X write fail. error code = 0x%04x.\\n\", btreg_type[btreg_write_type], btreg_write_addr, btreg_write_error);\n\t\treturn 0;\n\t}\n\n\tdev = m->private;\n\tpadapter = (PADAPTER)rtw_netdev_priv(dev);\n\n\tret = rtw_btcoex_btreg_read(padapter, btreg_write_type, btreg_write_addr, &data);\n\tif (CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS))\n\t\tRTW_PRINT_SEL(m, \"BTREG read: (%s)0x%04X = 0x%08x\\n\", btreg_type[btreg_write_type], btreg_write_addr, data);\n\telse\n\t\tRTW_PRINT_SEL(m, \"BTREG read: (%s)0x%04X read fail. error code = 0x%04x.\\n\", btreg_type[btreg_write_type], btreg_write_addr, ret);\n\n\treturn 0;\n}\n\nssize_t proc_set_btreg_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\tPADAPTER padapter;\n\tu8 tmp[80] = {0};\n\tu32 num;\n\tu16 val;\n\tu16 ret;\n\tint err;\n\n\n\tpadapter = (PADAPTER)rtw_netdev_priv(dev);\n\n\tif (NULL == buffer) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input buffer is NULL!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter));\n\t\terr = -EFAULT;\n\t\tgoto exit;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is 0!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter));\n\t\terr = -EFAULT;\n\t\tgoto exit;\n\t}\n\n\tnum = count;\n\tif (num > (sizeof(tmp) - 1))\n\t\tnum = (sizeof(tmp) - 1);\n\n\tif (copy_from_user(tmp, buffer, num)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": copy buffer from user space FAIL!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter));\n\t\terr = -EFAULT;\n\t\tgoto exit;\n\t}\n\n\terr = btreg_parse_str(tmp, &btreg_write_type, &btreg_write_addr, &val);\n\tif (err)\n\t\tgoto exit;\n\n\tRTW_INFO(FUNC_ADPT_FMT \": Set (%s)0x%X = 0x%x\\n\",\n\t\tFUNC_ADPT_ARG(padapter), btreg_type[btreg_write_type], btreg_write_addr, val);\n\n\tret = rtw_btcoex_btreg_write(padapter, btreg_write_type, btreg_write_addr, val);\n\tif (!CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS))\n\t\terr = ret;\n\nexit:\n\tbtreg_write_error = err;\n\n\treturn count;\n}\n\nint proc_get_btc_reduce_wl_txpwr(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev;\n\tPADAPTER padapter;\n\tu8 data;\n\n\tdev = m->private;\n\tpadapter = (PADAPTER)rtw_netdev_priv(dev);\n\n\tdata = rtw_btcoex_get_reduce_wl_txpwr(padapter);\n\tRTW_PRINT_SEL(m, \"BTC reduce WL TxPwr = %d dB\\n\", data);\n\n\treturn 0;\n}\n\nssize_t proc_set_btc_reduce_wl_txpwr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\tPADAPTER padapter;\n\tHAL_DATA_TYPE *hal_data;\n\tu8 tmp[80] = {0};\n\tu32 val = 0;\n\tu32 num;\n\n\tpadapter = (PADAPTER)rtw_netdev_priv(dev);\n\thal_data = GET_HAL_DATA(padapter);\n\n\t/*\tRTW_INFO(\"+\" FUNC_ADPT_FMT \"\\n\", FUNC_ADPT_ARG(padapter)); */\n\n\tif (NULL == buffer) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input buffer is NULL!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter));\n\n\t\treturn -EFAULT;\n\t}\n\n\tif (count < 1) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": input length is 0!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter));\n\n\t\treturn -EFAULT;\n\t}\n\n\tnum = count;\n\tif (num > (sizeof(tmp) - 1))\n\t\tnum = (sizeof(tmp) - 1);\n\n\tif (copy_from_user(tmp, buffer, num)) {\n\t\tRTW_INFO(FUNC_ADPT_FMT \": copy buffer from user space FAIL!\\n\",\n\t\t\t FUNC_ADPT_ARG(padapter));\n\n\t\treturn -EFAULT;\n\t}\n\n\tnum = sscanf(tmp, \"%d\", &val);\n\n\tif ((IS_HARDWARE_TYPE_8822C(padapter)) && (hal_data->EEPROMBluetoothCoexist == _TRUE))\n\t\trtw_btc_reduce_wl_txpwr_cmd(padapter, val);\n\n\treturn count;\n}\n\n#endif /* CONFIG_BT_COEXIST */\n\n#ifdef CONFIG_MBSSID_CAM\nint proc_get_mbid_cam_cache(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\trtw_mbid_cam_cache_dump(m, __func__, adapter);\n\trtw_mbid_cam_dump(m, __func__, adapter);\n\treturn 0;\n}\n#endif /* CONFIG_MBSSID_CAM */\n\nint proc_get_mac_addr(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\trtw_hal_dump_macaddr(m, adapter);\n\treturn 0;\n}\n\nstatic int proc_get_skip_band(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tint bandskip;\n\n\tbandskip = RTW_GET_SCAN_BAND_SKIP(adapter);\n\tRTW_PRINT_SEL(m, \"bandskip:0x%02x\\n\", bandskip);\n\treturn 0;\n}\n\nstatic ssize_t proc_set_skip_band(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[6];\n\tu8 skip_band;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhu\", &skip_band);\n\n\t\tif (num < 1)\n\t\t\treturn -EINVAL;\n\n\t\tif (1 == skip_band)\n\t\t\tRTW_SET_SCAN_BAND_SKIP(padapter, BAND_24G);\n\t\telse if (2 == skip_band)\n\t\t\tRTW_SET_SCAN_BAND_SKIP(padapter, BAND_5G);\n\t\telse if (3 == skip_band)\n\t\t\tRTW_CLR_SCAN_BAND_SKIP(padapter, BAND_24G);\n\t\telse if (4 == skip_band)\n\t\t\tRTW_CLR_SCAN_BAND_SKIP(padapter, BAND_5G);\n\t}\n\treturn count;\n\n}\n\n#ifdef CONFIG_RTW_ACS\nstatic int proc_get_chan_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\trtw_acs_chan_info_dump(m, adapter);\n\treturn 0;\n}\n\nstatic int proc_get_best_chan(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (IS_ACS_ENABLE(adapter))\n\t\trtw_acs_info_dump(m, adapter);\n\telse\n\t\t_RTW_PRINT_SEL(m,\"ACS disabled\\n\");\n\treturn 0;\n}\n\nstatic ssize_t proc_set_acs(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n#ifdef CONFIG_RTW_ACS_DBG\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu8 acs_state = 0;\n\tu16 scan_ch_ms= 0, acs_scan_ch_ms = 0;\n\tu8 scan_type = SCAN_ACTIVE, igi= 0, bw = 0;\n\tu8 acs_scan_type = SCAN_ACTIVE, acs_igi= 0, acs_bw = 0;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhu %hhu %hu %hhx %hhu\",\n\t\t\t&acs_state, &scan_type, &scan_ch_ms, &igi, &bw);\n\n\t\tif (num < 1)\n\t\t\treturn -EINVAL;\n\n\t\tif (acs_state)\n\t\t\trtw_acs_start(padapter);\n\t\telse\n\t\t\trtw_acs_stop(padapter);\n\t\tnum = num -1;\n\n\t\tif(num) {\n\t\t\tif (num-- > 0)\n\t\t\t\tacs_scan_type = scan_type;\n\t\t\tif (num-- > 0)\n\t\t\t\tacs_scan_ch_ms = scan_ch_ms;\n\t\t\tif (num-- > 0)\n\t\t\t\tacs_igi = igi;\n\t\t\tif (num-- > 0)\n\t\t\t\tacs_bw = bw;\n\t\t\trtw_acs_adv_setting(padapter, acs_scan_type, acs_scan_ch_ms, acs_igi, acs_bw);\n\t\t}\n\t}\n#endif /*CONFIG_RTW_ACS_DBG*/\n\treturn count;\n}\n#endif /*CONFIG_RTW_ACS*/\n\n#ifdef CONFIG_BACKGROUND_NOISE_MONITOR\nstatic int proc_get_nm(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\trtw_noise_info_dump(m, adapter);\n\treturn 0;\n}\n\nstatic ssize_t proc_set_nm(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu8 nm_state = 0;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhu\", &nm_state);\n\n\t\tif (num < 1)\n\t\t\treturn -EINVAL;\n\n\t\tif (nm_state)\n\t\t\trtw_nm_enable(padapter);\n\t\telse\n\t\t\trtw_nm_disable(padapter);\n\n\t}\n\treturn count;\n}\n#endif /*CONFIG_RTW_ACS*/\n\nstatic int proc_get_hal_spec(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_hal_spec(m, adapter);\n\treturn 0;\n}\n\nstatic int proc_get_phy_cap(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\trtw_dump_phy_cap(m, adapter);\n#ifdef CONFIG_80211N_HT\n\trtw_dump_drv_phy_cap(m, adapter);\n\trtw_get_dft_phy_cap(m, adapter);\n#endif /* CONFIG_80211N_HT */\n\treturn 0;\n}\n\n#ifdef CONFIG_SUPPORT_TRX_SHARED\n#include \"../../hal/hal_halmac.h\"\nstatic int proc_get_trx_share_mode(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_trx_share_mode(m, adapter);\n\treturn 0;\n}\n#endif\n\nstatic int proc_dump_rsvd_page(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\trtw_dump_rsvd_page(m, adapter, adapter->rsvd_page_offset, adapter->rsvd_page_num);\n\treturn 0;\n}\nstatic ssize_t proc_set_rsvd_page_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu8 page_offset, page_num;\n\n\tif (count < 2)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhu %hhu\", &page_offset, &page_num);\n\n\t\tif (num < 2)\n\t\t\treturn -EINVAL;\n\t\tpadapter->rsvd_page_offset = page_offset;\n\t\tpadapter->rsvd_page_num = page_num;\n\t}\n\treturn count;\n}\n\n#ifdef CONFIG_SUPPORT_FIFO_DUMP\nstatic int proc_dump_fifo(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\trtw_dump_fifo(m, adapter, adapter->fifo_sel, adapter->fifo_addr, adapter->fifo_size);\n\treturn 0;\n}\nstatic ssize_t proc_set_fifo_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu8 fifo_sel = 0;\n\tu32 fifo_addr = 0;\n\tu32 fifo_size = 0;\n\n\tif (count < 3)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%hhu %x %d\", &fifo_sel, &fifo_addr, &fifo_size);\n\n\t\tif (num < 3)\n\t\t\treturn -EINVAL;\n\n\t\tpadapter->fifo_sel = fifo_sel;\n\t\tpadapter->fifo_addr = fifo_addr;\n\t\tpadapter->fifo_size = fifo_size;\n\t}\n\treturn count;\n}\n#endif\n\n#ifdef CONFIG_WOW_PATTERN_HW_CAM\nint proc_dump_pattern_cam(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);\n\tint i;\n\tstruct  rtl_wow_pattern context;\n\n\tfor (i = 0 ; i < pwrpriv->wowlan_pattern_idx; i++) {\n\t\trtw_wow_pattern_read_cam_ent(padapter, i, &context);\n\t\trtw_dump_wow_pattern(m, &context, i);\n\t}\n\n\treturn 0;\n}\n#endif\n\nstatic int proc_get_napi_info(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv *pregistrypriv = &adapter->registrypriv;\n\tu8 napi = 0, gro = 0;\n\tu32 weight = 0;\n\tstruct dvobj_priv *d;\n\td = adapter_to_dvobj(adapter);\n\n\n#ifdef CONFIG_RTW_NAPI\n\tif (pregistrypriv->en_napi) {\n\t\tnapi = 1;\n\t\tweight = RTL_NAPI_WEIGHT;\n\t}\n\n#ifdef CONFIG_RTW_GRO\n\tif (pregistrypriv->en_gro)\n\t\tgro = 1;\n#endif /* CONFIG_RTW_GRO */\n#endif /* CONFIG_RTW_NAPI */\n\n\tif (napi) {\n\t\tRTW_PRINT_SEL(m, \"NAPI enable, weight=%d\\n\", weight);\n#ifdef CONFIG_RTW_NAPI_DYNAMIC\n\t\tRTW_PRINT_SEL(m, \"Dynamaic NAPI mechanism is on, current NAPI %s\\n\",\n\t\t\t      d->en_napi_dynamic ? \"enable\" : \"disable\");\n\t\tRTW_PRINT_SEL(m, \"Dynamaic NAPI info:\\n\"\n\t\t\t\t \"\\ttcp_rx_threshold = %d Mbps\\n\"\n\t\t\t\t \"\\tcur_rx_tp = %d Mbps\\n\",\n\t\t\t      pregistrypriv->napi_threshold,\n\t\t\t      d->traffic_stat.cur_rx_tp);\n#endif /* CONFIG_RTW_NAPI_DYNAMIC */\n\t} else {\n\t\tRTW_PRINT_SEL(m, \"NAPI disable\\n\");\n\t}\n\tRTW_PRINT_SEL(m, \"GRO %s\\n\", gro?\"enable\":\"disable\");\n\n\treturn 0;\n\n}\n\n#ifdef CONFIG_RTW_NAPI_DYNAMIC\nstatic ssize_t proc_set_napi_th(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\tstruct _ADAPTER *adapter = (struct _ADAPTER *)rtw_netdev_priv(dev);\n\tstruct registry_priv *registry = &adapter->registrypriv;\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tPADAPTER iface = NULL;\n\tchar tmp[32] = {0};\n\tint thrshld = 0;\n\tint num = 0, i = 0;\n\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tRTW_INFO(\"%s: Last threshold = %d Mbps\\n\", __FUNCTION__, registry->napi_threshold);\n\n\n\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\tiface = dvobj->padapters[i];\n\t\tif (iface) {\t\n\t\t\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\t\t\tregistry = &iface->registrypriv;\n\t\t\t\tnum = sscanf(tmp, \"%d\", &thrshld);\n\t\t\t\tif (num > 0) {\n\t\t\t\t\tif (thrshld > 0)\n\t\t\t\t\t\tregistry->napi_threshold = thrshld;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\tRTW_INFO(\"%s: New threshold = %d Mbps\\n\", __FUNCTION__, registry->napi_threshold);\n\tRTW_INFO(\"%s: Current RX throughput = %d Mbps\\n\",\n\t\t __FUNCTION__, adapter_to_dvobj(adapter)->traffic_stat.cur_rx_tp);\n\n\treturn count;\n}\n#endif /* CONFIG_RTW_NAPI_DYNAMIC */\n\n\nssize_t proc_set_dynamic_agg_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tint enable = 0, i = 0;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tstruct dvobj_priv *dvobj = adapter_to_dvobj(padapter);\n\t\tPADAPTER iface = NULL;\n\t\tint num = sscanf(tmp, \"%d\", &enable);\n\n\t\tif (num !=  1) {\n\t\t\tRTW_INFO(\"invalid parameter!\\n\");\n\t\t\treturn count;\n\t\t}\n\n\t\tRTW_INFO(\"dynamic_agg_enable:%d\\n\", enable);\n\n\t\tfor (i = 0; i < dvobj->iface_nums; i++) {\n\t\t\tiface = dvobj->padapters[i];\n\t\t\tif (iface)\n\t\t\t\tiface->registrypriv.dynamic_agg_enable = enable;\n\t\t}\n\n\t}\n\n\treturn count;\n\n}\n\nstatic int proc_get_dynamic_agg_enable(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv *pregistrypriv = &adapter->registrypriv;\n\n\tRTW_PRINT_SEL(m, \"dynamic_agg_enable:%d\\n\", pregistrypriv->dynamic_agg_enable);\n\n\treturn 0;\n}\n\n#ifdef CONFIG_RTW_MESH\nstatic int proc_get_mesh_peer_sel_policy(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_mesh_peer_sel_policy(m, adapter);\n\n\treturn 0;\n}\n\n#if CONFIG_RTW_MESH_ACNODE_PREVENT\nstatic int proc_get_mesh_acnode_prevent(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (MLME_IS_MESH(adapter))\n\t\tdump_mesh_acnode_prevent_settings(m, adapter);\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_mesh_acnode_prevent(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tstruct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;\n\t\tu8 enable;\n\t\tu32 conf_timeout_ms;\n\t\tu32 notify_timeout_ms;\n\t\tint num = sscanf(tmp, \"%hhu %u %u\", &enable, &conf_timeout_ms, &notify_timeout_ms);\n\n\t\tif (num >= 1)\n\t\t\tpeer_sel_policy->acnode_prevent = enable;\n\t\tif (num >= 2)\n\t\t\tpeer_sel_policy->acnode_conf_timeout_ms = conf_timeout_ms;\n\t\tif (num >= 3)\n\t\t\tpeer_sel_policy->acnode_notify_timeout_ms = notify_timeout_ms;\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_RTW_MESH_ACNODE_PREVENT */\n\n#if CONFIG_RTW_MESH_OFFCH_CAND\nstatic int proc_get_mesh_offch_cand(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (MLME_IS_MESH(adapter))\n\t\tdump_mesh_offch_cand_settings(m, adapter);\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_mesh_offch_cand(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tstruct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;\n\t\tu8 enable;\n\t\tu32 find_int_ms;\n\t\tint num = sscanf(tmp, \"%hhu %u\", &enable, &find_int_ms);\n\n\t\tif (num >= 1)\n\t\t\tpeer_sel_policy->offch_cand = enable;\n\t\tif (num >= 2)\n\t\t\tpeer_sel_policy->offch_find_int_ms = find_int_ms;\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_RTW_MESH_OFFCH_CAND */\n\n#if CONFIG_RTW_MESH_PEER_BLACKLIST\nstatic int proc_get_mesh_peer_blacklist(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (MLME_IS_MESH(adapter)) {\n\t\tdump_mesh_peer_blacklist_settings(m, adapter);\n\t\tif (MLME_IS_ASOC(adapter))\n\t\t\tdump_mesh_peer_blacklist(m, adapter);\n\t}\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_mesh_peer_blacklist(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tstruct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;\n\t\tu32 conf_timeout_ms;\n\t\tu32 blacklist_timeout_ms;\n\t\tint num = sscanf(tmp, \"%u %u\", &conf_timeout_ms, &blacklist_timeout_ms);\n\n\t\tif (num >= 1)\n\t\t\tpeer_sel_policy->peer_conf_timeout_ms = conf_timeout_ms;\n\t\tif (num >= 2)\n\t\t\tpeer_sel_policy->peer_blacklist_timeout_ms = blacklist_timeout_ms;\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */\n\n#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\nstatic int proc_get_mesh_cto_mgate_require(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (MLME_IS_MESH(adapter))\n\t\tRTW_PRINT_SEL(m, \"%u\\n\", adapter->mesh_cfg.peer_sel_policy.cto_mgate_require);\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_mesh_cto_mgate_require(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tstruct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;\n\t\tu8 require;\n\t\tint num = sscanf(tmp, \"%hhu\", &require);\n\n\t\tif (num >= 1) {\n\t\t\tpeer_sel_policy->cto_mgate_require = require;\n\t\t\t#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER\n\t\t\tif (rtw_mesh_cto_mgate_required(adapter))\n\t\t\t\trtw_netif_carrier_off(adapter->pnetdev);\n\t\t\telse\n\t\t\t\trtw_netif_carrier_on(adapter->pnetdev);\n\t\t\t#endif\n\t\t}\n\t}\n\n\treturn count;\n}\n\nstatic int proc_get_mesh_cto_mgate_blacklist(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (MLME_IS_MESH(adapter)) {\n\t\tdump_mesh_cto_mgate_blacklist_settings(m, adapter);\n\t\tif (MLME_IS_ASOC(adapter))\n\t\t\tdump_mesh_cto_mgate_blacklist(m, adapter);\n\t}\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_mesh_cto_mgate_blacklist(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tstruct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;\n\t\tu32 conf_timeout_ms;\n\t\tu32 blacklist_timeout_ms;\n\t\tint num = sscanf(tmp, \"%u %u\", &conf_timeout_ms, &blacklist_timeout_ms);\n\n\t\tif (num >= 1)\n\t\t\tpeer_sel_policy->cto_mgate_conf_timeout_ms = conf_timeout_ms;\n\t\tif (num >= 2)\n\t\t\tpeer_sel_policy->cto_mgate_blacklist_timeout_ms = blacklist_timeout_ms;\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */\n\nstatic int proc_get_mesh_networks(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tdump_mesh_networks(m, adapter);\n\n\treturn 0;\n}\n\nstatic int proc_get_mesh_plink_ctl(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (MLME_IS_MESH(adapter))\n\t\tdump_mesh_plink_ctl(m, adapter);\n\n\treturn 0;\n}\n\nstatic int proc_get_mesh_mpath(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter))\n\t\tdump_mpath(m, adapter);\n\n\treturn 0;\n}\n\nstatic int proc_get_mesh_mpp(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter))\n\t\tdump_mpp(m, adapter);\n\n\treturn 0;\n}\n\nstatic int proc_get_mesh_known_gates(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (MLME_IS_MESH(adapter))\n\t\tdump_known_gates(m, adapter);\n\n\treturn 0;\n}\n\n#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\nstatic int proc_get_mesh_b2u_flags(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (MLME_IS_MESH(adapter))\n\t\tdump_mesh_b2u_flags(m, adapter);\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_mesh_b2u_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\t\tu8 msrc, mfwd;\n\t\tint num = sscanf(tmp, \"%hhx %hhx\", &msrc, &mfwd);\n\n\t\tif (num >= 1)\n\t\t\tmcfg->b2u_flags_msrc = msrc;\n\t\tif (num >= 2)\n\t\t\tmcfg->b2u_flags_mfwd = mfwd;\n\t}\n\n\treturn count;\n}\n#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */\n\nstatic int proc_get_mesh_stats(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (MLME_IS_MESH(adapter))\n\t\tdump_mesh_stats(m, adapter);\n\n\treturn 0;\n}\n\nstatic int proc_get_mesh_gate_timeout(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\n\tif (MLME_IS_MESH(adapter))\n\t\tRTW_PRINT_SEL(m, \"%u factor\\n\",\n\t\t\t       adapter->mesh_cfg.path_gate_timeout_factor);\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_mesh_gate_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\t\tu32 timeout;\n\t\tint num = sscanf(tmp, \"%u\", &timeout);\n\n\t\tif (num < 1)\n\t\t\tgoto exit;\n\n\t\tmcfg->path_gate_timeout_factor = timeout;\n\t}\n\nexit:\n\treturn count;\n}\n\nstatic int proc_get_mesh_gate_state(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;\n\tu8 cto_mgate = 0;\n\n\tif (MLME_IS_MESH(adapter)) {\n\t\tif (rtw_mesh_is_primary_gate(adapter))\n\t\t\tRTW_PRINT_SEL(m, \"PG\\n\");\n\t\telse if (mcfg->dot11MeshGateAnnouncementProtocol)\n\t\t\tRTW_PRINT_SEL(m, \"G\\n\");\n\t\telse if (rtw_mesh_gate_num(adapter))\n\t\t\tRTW_PRINT_SEL(m, \"C\\n\");\n\t\telse\n\t\t\tRTW_PRINT_SEL(m, \"N\\n\");\n\t}\n\n\treturn 0;\n}\n\nstatic int proc_get_peer_alive_based_preq(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\tstruct _ADAPTER *adapter= (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv  *rp = &adapter->registrypriv;\n\n\tRTW_PRINT_SEL(m, \"peer_alive_based_preq = %u\\n\",\n\t\t      rp->peer_alive_based_preq);\n\n\treturn 0;\n}\n\nstatic ssize_t \nproc_set_peer_alive_based_preq(struct file *file, const char __user *buffer,\n\t\t\t       size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\tstruct _ADAPTER *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct registry_priv  *rp = &adapter->registrypriv;\n\tchar tmp[8];\n\tint num = 0;\n\tu8 enable = 0;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (!buffer || copy_from_user(tmp, buffer, count))\n\t\tgoto exit;\n\n\tnum = sscanf(tmp, \"%hhu\", &enable);\n\tif (num !=  1) {\n\t\tRTW_ERR(\"%s: invalid parameter!\\n\", __FUNCTION__);\n\t\tgoto exit;\n\t}\n\n\tif (enable > 1) {\n\t\tRTW_ERR(\"%s: invalid value!\\n\", __FUNCTION__);\n\t\tgoto exit;\n\t}\n\trp->peer_alive_based_preq = enable;\n\nexit:\n\treturn count;\n}\n#endif /* CONFIG_RTW_MESH */\n\nstatic int proc_get_scan_deny(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\tstruct _ADAPTER *adapter= (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\n\tRTW_PRINT_SEL(m, \"scan_deny is %s\\n\", (dvobj->scan_deny == _TRUE) ? \"enable\":\"disable\");\n\n\treturn 0;\n}\n\nstatic ssize_t proc_set_scan_deny(struct file *file, const char __user *buffer,\n\t\t\t\tsize_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\tstruct _ADAPTER *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tchar tmp[8];\n\tint num = 0;\n\tint enable = 0;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (!buffer || copy_from_user(tmp, buffer, count))\n\t\tgoto exit;\n\n\tnum = sscanf(tmp, \"%d\", &enable);\n\tif (num !=  1) {\n\t\tRTW_ERR(\"%s: invalid parameter!\\n\", __FUNCTION__);\n\t\tgoto exit;\n\t}\n\n\tdvobj->scan_deny = enable ? _TRUE : _FALSE;\n\n\tRTW_PRINT(\"%s: scan_deny is %s\\n\",\n\t\t  __FUNCTION__, (dvobj->scan_deny == _TRUE) ? \"enable\":\"disable\");\n\nexit:\n\treturn count;\n}\n\n#ifdef CONFIG_RTW_TPT_MODE\nstatic int proc_get_tpt_mode(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\tstruct _ADAPTER *adapter= (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\n\tRTW_PRINT_SEL(m, \"current tpt_mode = %d\\n\", dvobj->tpt_mode);\n\n\treturn 0;\n}\n\nstatic void tpt_mode_default(struct _ADAPTER *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\n\t/* 1. disable scan deny */\n\tdvobj->scan_deny = _FALSE;\n\n\t/* 2. back to original LPS mode */\n#ifdef CONFIG_LPS\t\t\n\trtw_pm_set_lps(adapter, adapter->registrypriv.power_mgnt);\n#endif\n\n\t/* 3. back to original 2.4 tx bw mode */\n\trtw_set_tx_bw_mode(adapter, adapter->registrypriv.tx_bw_mode);\n}\n\nstatic void rtw_tpt_mode(struct _ADAPTER *adapter)\n{\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter);\n\n\tif (dvobj->tpt_mode > 0) {\n\n\t\t/* when enable each tpt mode \n\t\t\t1. scan deny\n\t\t\t2. disable LPS */\n\t\t\t\n\t\tdvobj->scan_deny = _TRUE;\n\n#ifdef CONFIG_LPS\t\t\n\t\trtw_pm_set_lps(adapter, PS_MODE_ACTIVE);\n#endif\n\n\t}\n\n\tswitch (dvobj->tpt_mode) {\n\t\tcase 0: /* default mode */\n\t\t\ttpt_mode_default(adapter);\n\t\t\tbreak;\n\t\tcase 1: /* High TP*/\n\t\t\t/*tpt_mode1(adapter);*/\t\t\t \n\t\t\tdvobj->edca_be_ul = 0x5e431c;\n\t\t\tdvobj->edca_be_dl = 0x00431c;\t\t\t \n\t\t\tbreak;\n\t\tcase 2: /* noise */\n\t\t\t/* tpt_mode2(adapter); */\n\t\t\tdvobj->edca_be_ul = 0x00431c;\n\t\t\tdvobj->edca_be_dl = 0x00431c;\n\n\t\t\trtw_set_tx_bw_mode(adapter, 0x20); /* for 2.4g, fixed tx_bw_mode to 20Mhz */\n\t\t\tbreak;\n\t\tcase 3: /* long distance */\n\t\t\t/* tpt_mode3(adapter); */\n\t\t\tdvobj->edca_be_ul = 0x00431c;\n\t\t\tdvobj->edca_be_dl = 0x00431c;\n\n\t\t\trtw_set_tx_bw_mode(adapter, 0x20); /* for 2.4g, fixed tx_bw_mode to 20Mhz */\n\t\t\tbreak;\n\t\tcase 4: /* noise + long distance */\n\t\t\t/* tpt_mode4(adapter); */\n\t\t\tdvobj->edca_be_ul = 0x00431c;\n\t\t\tdvobj->edca_be_dl = 0x00431c;\n\n\t\t\trtw_set_tx_bw_mode(adapter, 0x20); /* for 2.4g, fixed tx_bw_mode to 20Mhz */\n\t\t\tbreak;\n\t\tdefault: /* default mode */\n\t\t\ttpt_mode_default(adapter);\t\t\n\t\t\tbreak;\n\t}\n\n}\n\nstatic ssize_t proc_set_tpt_mode(struct file *file, const char __user *buffer,\n\t\t\t\tsize_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\tstruct _ADAPTER *adapter = (_adapter *)rtw_netdev_priv(dev);\n\tstruct dvobj_priv *dvobj = adapter_to_dvobj(adapter);\n\tchar tmp[32];\n\tint num = 0;\n\tint mode = 0;\n\n#define MAX_TPT_MODE_NUM 4\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (!buffer || copy_from_user(tmp, buffer, count))\n\t\tgoto exit;\n\n\tnum = sscanf(tmp, \"%d\", &mode);\n\tif (num !=  1) {\n\t\tRTW_ERR(\"%s: invalid parameter!\\n\", __FUNCTION__);\n\t\tgoto exit;\n\t}\n\n\tif (mode > MAX_TPT_MODE_NUM )\n\t\tmode = 0;\t\n\n\tRTW_PRINT(\"%s: previous mode =  %d\\n\",\n\t\t  __FUNCTION__, dvobj->tpt_mode);\n\n\tRTW_PRINT(\"%s: enabled mode = %d\\n\",\n\t\t  __FUNCTION__, mode);\n\n\tdvobj->tpt_mode = mode;\n\n\trtw_tpt_mode(adapter);\n\nexit:\n\treturn count;\n\n}\n#endif /* CONFIG_RTW_TPT_MODE */\n\nint proc_get_cur_beacon_keys(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *adapter = rtw_netdev_priv(dev);\n\tstruct mlme_priv *mlme = &adapter->mlmepriv;\n\n\trtw_dump_bcn_keys(m, &mlme->cur_beacon_keys);\n\n\treturn 0;\n}\n\n/*\n* rtw_adapter_proc:\n* init/deinit when register/unregister net_device\n*/\nconst struct rtw_proc_hdl adapter_proc_hdls[] = {\n#if RTW_SEQ_FILE_TEST\n\tRTW_PROC_HDL_SEQ(\"seq_file_test\", &seq_file_test, NULL),\n#endif\n\tRTW_PROC_HDL_SSEQ(\"write_reg\", NULL, proc_set_write_reg),\n\tRTW_PROC_HDL_SSEQ(\"read_reg\", proc_get_read_reg, proc_set_read_reg),\n\tRTW_PROC_HDL_SSEQ(\"tx_rate_bmp\", proc_get_dump_tx_rate_bmp, NULL),\n\tRTW_PROC_HDL_SSEQ(\"adapters_status\", proc_get_dump_adapters_status, NULL),\n#ifdef CONFIG_RTW_CUSTOMER_STR\n\tRTW_PROC_HDL_SSEQ(\"customer_str\", proc_get_customer_str, NULL),\n#endif\n\tRTW_PROC_HDL_SSEQ(\"fwstate\", proc_get_fwstate, NULL),\n\tRTW_PROC_HDL_SSEQ(\"sec_info\", proc_get_sec_info, NULL),\n\tRTW_PROC_HDL_SSEQ(\"mlmext_state\", proc_get_mlmext_state, NULL),\n\tRTW_PROC_HDL_SSEQ(\"qos_option\", proc_get_qos_option, NULL),\n\tRTW_PROC_HDL_SSEQ(\"ht_option\", proc_get_ht_option, NULL),\n\tRTW_PROC_HDL_SSEQ(\"rf_info\", proc_get_rf_info, NULL),\n\tRTW_PROC_HDL_SSEQ(\"scan_param\", proc_get_scan_param, proc_set_scan_param),\n\tRTW_PROC_HDL_SSEQ(\"scan_abort\", proc_get_scan_abort, NULL),\n#ifdef CONFIG_SCAN_BACKOP\n\tRTW_PROC_HDL_SSEQ(\"backop_flags_sta\", proc_get_backop_flags_sta, proc_set_backop_flags_sta),\n\t#ifdef CONFIG_AP_MODE\n\tRTW_PROC_HDL_SSEQ(\"backop_flags_ap\", proc_get_backop_flags_ap, proc_set_backop_flags_ap),\n\t#endif\n\t#ifdef CONFIG_RTW_MESH\n\tRTW_PROC_HDL_SSEQ(\"backop_flags_mesh\", proc_get_backop_flags_mesh, proc_set_backop_flags_mesh),\n\t#endif\n#endif\n#ifdef CONFIG_RTW_REPEATER_SON\n\tRTW_PROC_HDL_SSEQ(\"rson_data\", proc_get_rson_data, proc_set_rson_data),\n#endif\n\tRTW_PROC_HDL_SSEQ(\"survey_info\", proc_get_survey_info, proc_set_survey_info),\n\tRTW_PROC_HDL_SSEQ(\"ap_info\", proc_get_ap_info, NULL),\n#ifdef ROKU_PRIVATE\n\tRTW_PROC_HDL_SSEQ(\"infra_ap\", proc_get_infra_ap, NULL),\n#endif /* ROKU_PRIVATE */\n\tRTW_PROC_HDL_SSEQ(\"trx_info\", proc_get_trx_info, proc_reset_trx_info),\n\tRTW_PROC_HDL_SSEQ(\"tx_power_offset\", proc_get_tx_power_offset, proc_set_tx_power_offset),\n\tRTW_PROC_HDL_SSEQ(\"rate_ctl\", proc_get_rate_ctl, proc_set_rate_ctl),\n\tRTW_PROC_HDL_SSEQ(\"bw_ctl\", proc_get_bw_ctl, proc_set_bw_ctl),\n\tRTW_PROC_HDL_SSEQ(\"mac_qinfo\", proc_get_mac_qinfo, NULL),\n\tRTW_PROC_HDL_SSEQ(\"macid_info\", proc_get_macid_info, NULL),\n\tRTW_PROC_HDL_SSEQ(\"bcmc_info\", proc_get_mi_ap_bc_info, NULL),\n\tRTW_PROC_HDL_SSEQ(\"sec_cam\", proc_get_sec_cam, proc_set_sec_cam),\n\tRTW_PROC_HDL_SSEQ(\"sec_cam_cache\", proc_get_sec_cam_cache, NULL),\n\tRTW_PROC_HDL_SSEQ(\"ps_dbg_info\", proc_get_ps_dbg_info, proc_set_ps_dbg_info),\n\tRTW_PROC_HDL_SSEQ(\"wifi_spec\", proc_get_wifi_spec, NULL),\n#ifdef CONFIG_LAYER2_ROAMING\n\tRTW_PROC_HDL_SSEQ(\"roam_flags\", proc_get_roam_flags, proc_set_roam_flags),\n\tRTW_PROC_HDL_SSEQ(\"roam_param\", proc_get_roam_param, proc_set_roam_param),\n\tRTW_PROC_HDL_SSEQ(\"roam_tgt_addr\", NULL, proc_set_roam_tgt_addr),\n#endif /* CONFIG_LAYER2_ROAMING */\n\n#ifdef CONFIG_RTW_80211R\n\tRTW_PROC_HDL_SSEQ(\"ft_flags\", proc_get_ft_flags, proc_set_ft_flags),\n#endif\n\n#ifdef CONFIG_SDIO_HCI\n\tRTW_PROC_HDL_SSEQ(\"sd_f0_reg_dump\", proc_get_sd_f0_reg_dump, NULL),\n\tRTW_PROC_HDL_SSEQ(\"sdio_local_reg_dump\", proc_get_sdio_local_reg_dump, NULL),\n\tRTW_PROC_HDL_SSEQ(\"sdio_card_info\", proc_get_sdio_card_info, NULL),\n#ifdef DBG_SDIO\n\tRTW_PROC_HDL_SSEQ(\"sdio_dbg\", proc_get_sdio_dbg, proc_set_sdio_dbg),\n#endif /* DBG_SDIO */\n#ifdef CONFIG_SDIO_MONITOR\n\tRTW_PROC_HDL_SSEQ(\"sdio_monitor\", proc_get_sdio_monitor, proc_set_sdio_monitor),\n#endif\n#endif /* CONFIG_SDIO_HCI */\n\n\tRTW_PROC_HDL_SSEQ(\"fwdl_test_case\", NULL, proc_set_fwdl_test_case),\n\tRTW_PROC_HDL_SSEQ(\"del_rx_ampdu_test_case\", NULL, proc_set_del_rx_ampdu_test_case),\n\tRTW_PROC_HDL_SSEQ(\"wait_hiq_empty\", NULL, proc_set_wait_hiq_empty),\n\tRTW_PROC_HDL_SSEQ(\"sta_linking_test\", NULL, proc_set_sta_linking_test),\n#ifdef CONFIG_AP_MODE\n\tRTW_PROC_HDL_SSEQ(\"ap_linking_test\", NULL, proc_set_ap_linking_test),\n#endif\n\n\tRTW_PROC_HDL_SSEQ(\"mac_reg_dump\", proc_get_mac_reg_dump, NULL),\n\tRTW_PROC_HDL_SSEQ(\"bb_reg_dump\", proc_get_bb_reg_dump, NULL),\n\tRTW_PROC_HDL_SSEQ(\"bb_reg_dump_ex\", proc_get_bb_reg_dump_ex, NULL),\n\tRTW_PROC_HDL_SSEQ(\"rf_reg_dump\", proc_get_rf_reg_dump, NULL),\n\n#ifdef CONFIG_RTW_LED\n\tRTW_PROC_HDL_SSEQ(\"led_config\", proc_get_led_config, proc_set_led_config),\n#endif\n\n#ifdef CONFIG_AP_MODE\n\tRTW_PROC_HDL_SSEQ(\"aid_status\", proc_get_aid_status, proc_set_aid_status),\n\tRTW_PROC_HDL_SSEQ(\"all_sta_info\", proc_get_all_sta_info, NULL),\n\tRTW_PROC_HDL_SSEQ(\"bmc_tx_rate\", proc_get_bmc_tx_rate, proc_set_bmc_tx_rate),\n#endif /* CONFIG_AP_MODE */\n\n#ifdef DBG_MEMORY_LEAK\n\tRTW_PROC_HDL_SSEQ(\"_malloc_cnt\", proc_get_malloc_cnt, NULL),\n#endif /* DBG_MEMORY_LEAK */\n\n#ifdef CONFIG_FIND_BEST_CHANNEL\n\tRTW_PROC_HDL_SSEQ(\"best_channel\", proc_get_best_channel, proc_set_best_channel),\n#endif\n\n\tRTW_PROC_HDL_SSEQ(\"rx_signal\", proc_get_rx_signal, proc_set_rx_signal),\n\tRTW_PROC_HDL_SSEQ(\"rx_chk_limit\", proc_get_rx_chk_limit, proc_set_rx_chk_limit),\n\tRTW_PROC_HDL_SSEQ(\"hw_info\", proc_get_hw_status, proc_set_hw_status),\n\tRTW_PROC_HDL_SSEQ(\"mac_rptbuf\", proc_get_mac_rptbuf, NULL),\n#ifdef CONFIG_80211N_HT\n\tRTW_PROC_HDL_SSEQ(\"ht_enable\", proc_get_ht_enable, proc_set_ht_enable),\n\tRTW_PROC_HDL_SSEQ(\"bw_mode\", proc_get_bw_mode, proc_set_bw_mode),\n\tRTW_PROC_HDL_SSEQ(\"ampdu_enable\", proc_get_ampdu_enable, proc_set_ampdu_enable),\n\tRTW_PROC_HDL_SSEQ(\"rx_ampdu\", proc_get_rx_ampdu, proc_set_rx_ampdu),\n\tRTW_PROC_HDL_SSEQ(\"rx_ampdu_size_limit\", proc_get_rx_ampdu_size_limit, proc_set_rx_ampdu_size_limit),\n\tRTW_PROC_HDL_SSEQ(\"rx_ampdu_factor\", proc_get_rx_ampdu_factor, proc_set_rx_ampdu_factor),\n\tRTW_PROC_HDL_SSEQ(\"rx_ampdu_density\", proc_get_rx_ampdu_density, proc_set_rx_ampdu_density),\n\tRTW_PROC_HDL_SSEQ(\"tx_ampdu_density\", proc_get_tx_ampdu_density, proc_set_tx_ampdu_density),\n\tRTW_PROC_HDL_SSEQ(\"tx_max_agg_num\", proc_get_tx_max_agg_num, proc_set_tx_max_agg_num),\n\tRTW_PROC_HDL_SSEQ(\"tx_quick_addba_req\", proc_get_tx_quick_addba_req, proc_set_tx_quick_addba_req),\n#ifdef CONFIG_TX_AMSDU\n\tRTW_PROC_HDL_SSEQ(\"tx_amsdu\", proc_get_tx_amsdu, proc_set_tx_amsdu),\n\tRTW_PROC_HDL_SSEQ(\"tx_amsdu_rate\", proc_get_tx_amsdu_rate, proc_set_tx_amsdu_rate),\n#endif\n#endif /* CONFIG_80211N_HT */\n\n\tRTW_PROC_HDL_SSEQ(\"en_fwps\", proc_get_en_fwps, proc_set_en_fwps),\n\n\t/* RTW_PROC_HDL_SSEQ(\"path_rssi\", proc_get_two_path_rssi, NULL),\n\t* \tRTW_PROC_HDL_SSEQ(\"rssi_disp\",proc_get_rssi_disp, proc_set_rssi_disp), */\n\n#ifdef CONFIG_BT_COEXIST\n\tRTW_PROC_HDL_SSEQ(\"btcoex_dbg\", proc_get_btcoex_dbg, proc_set_btcoex_dbg),\n\tRTW_PROC_HDL_SSEQ(\"btcoex\", proc_get_btcoex_info, NULL),\n\tRTW_PROC_HDL_SSEQ(\"btinfo_evt\", NULL, proc_set_btinfo_evt),\n\tRTW_PROC_HDL_SSEQ(\"btreg_read\", proc_get_btreg_read, proc_set_btreg_read),\n\tRTW_PROC_HDL_SSEQ(\"btreg_write\", proc_get_btreg_write, proc_set_btreg_write),\n\tRTW_PROC_HDL_SSEQ(\"btc_reduce_wl_txpwr\", proc_get_btc_reduce_wl_txpwr, proc_set_btc_reduce_wl_txpwr),\n#ifdef CONFIG_RF4CE_COEXIST\n\tRTW_PROC_HDL_SSEQ(\"rf4ce_state\", proc_get_rf4ce_state, proc_set_rf4ce_state),\n#endif\n#endif /* CONFIG_BT_COEXIST */\n\n#if defined(DBG_CONFIG_ERROR_DETECT)\n\tRTW_PROC_HDL_SSEQ(\"sreset\", proc_get_sreset, proc_set_sreset),\n#endif /* DBG_CONFIG_ERROR_DETECT */\n\tRTW_PROC_HDL_SSEQ(\"trx_info_debug\", proc_get_trx_info_debug, NULL),\n\n#ifdef CONFIG_HUAWEI_PROC\n\tRTW_PROC_HDL_SSEQ(\"huawei_trx_info\", proc_get_huawei_trx_info, NULL),\n#endif\n\tRTW_PROC_HDL_SSEQ(\"linked_info_dump\", proc_get_linked_info_dump, proc_set_linked_info_dump),\n\tRTW_PROC_HDL_SSEQ(\"sta_tp_dump\", proc_get_sta_tp_dump, proc_set_sta_tp_dump),\n\tRTW_PROC_HDL_SSEQ(\"sta_tp_info\", proc_get_sta_tp_info, NULL),\n\tRTW_PROC_HDL_SSEQ(\"dis_turboedca\", proc_get_turboedca_ctrl, proc_set_turboedca_ctrl),\n\tRTW_PROC_HDL_SSEQ(\"tx_info_msg\", proc_get_tx_info_msg, NULL),\n\tRTW_PROC_HDL_SSEQ(\"rx_info_msg\", proc_get_rx_info_msg, proc_set_rx_info_msg),\n\n#if defined(CONFIG_LPS_PG) && defined(CONFIG_RTL8822C)\n\tRTW_PROC_HDL_SSEQ(\"lps_pg_debug\", proc_get_lps_pg_debug, NULL),\n#endif\n\n#ifdef CONFIG_GPIO_API\n\tRTW_PROC_HDL_SSEQ(\"gpio_info\", proc_get_gpio, proc_set_gpio),\n\tRTW_PROC_HDL_SSEQ(\"gpio_set_output_value\", NULL, proc_set_gpio_output_value),\n\tRTW_PROC_HDL_SSEQ(\"gpio_set_direction\", NULL, proc_set_config_gpio),\n#endif\n\n#ifdef CONFIG_DBG_COUNTER\n\tRTW_PROC_HDL_SSEQ(\"rx_logs\", proc_get_rx_logs, NULL),\n\tRTW_PROC_HDL_SSEQ(\"tx_logs\", proc_get_tx_logs, NULL),\n\tRTW_PROC_HDL_SSEQ(\"int_logs\", proc_get_int_logs, NULL),\n#endif\n\n#ifdef CONFIG_DBG_RF_CAL\n\tRTW_PROC_HDL_SSEQ(\"iqk\", proc_get_iqk_info, proc_set_iqk),\n\tRTW_PROC_HDL_SSEQ(\"lck\", proc_get_lck_info, proc_set_lck),\n#endif\n\n#ifdef CONFIG_PCI_HCI\n\tRTW_PROC_HDL_SSEQ(\"rx_ring\", proc_get_rx_ring, NULL),\n\tRTW_PROC_HDL_SSEQ(\"tx_ring\", proc_get_tx_ring, NULL),\n#ifdef DBG_TXBD_DESC_DUMP\n\tRTW_PROC_HDL_SSEQ(\"tx_ring_ext\", proc_get_tx_ring_ext, proc_set_tx_ring_ext),\n#endif\n\tRTW_PROC_HDL_SSEQ(\"pci_aspm\", proc_get_pci_aspm, NULL),\n\n\tRTW_PROC_HDL_SSEQ(\"pci_conf_space\", proc_get_pci_conf_space, proc_set_pci_conf_space),\n\n\tRTW_PROC_HDL_SSEQ(\"pci_bridge_conf_space\", proc_get_pci_bridge_conf_space, proc_set_pci_bridge_conf_space),\n\n#endif\n\n#ifdef CONFIG_WOWLAN\n\tRTW_PROC_HDL_SSEQ(\"wow_pattern_info\", proc_get_pattern_info, proc_set_pattern_info),\n\tRTW_PROC_HDL_SSEQ(\"wow_wakeup_event\", proc_get_wakeup_event,\n\t\t\t  proc_set_wakeup_event),\n\tRTW_PROC_HDL_SSEQ(\"wowlan_last_wake_reason\", proc_get_wakeup_reason, NULL),\n#ifdef CONFIG_WOW_PATTERN_HW_CAM\n\tRTW_PROC_HDL_SSEQ(\"wow_pattern_cam\", proc_dump_pattern_cam, NULL),\n#endif\n#endif\n\n#ifdef CONFIG_GPIO_WAKEUP\n\tRTW_PROC_HDL_SSEQ(\"wowlan_gpio_info\", proc_get_wowlan_gpio_info, proc_set_wowlan_gpio_info),\n#endif\n#ifdef CONFIG_P2P_WOWLAN\n\tRTW_PROC_HDL_SSEQ(\"p2p_wowlan_info\", proc_get_p2p_wowlan_info, NULL),\n#endif\n\tRTW_PROC_HDL_SSEQ(\"country_code\", proc_get_country_code, proc_set_country_code),\n\tRTW_PROC_HDL_SSEQ(\"chan_plan\", proc_get_chan_plan, proc_set_chan_plan),\n#if CONFIG_RTW_MACADDR_ACL\n\tRTW_PROC_HDL_SSEQ(\"macaddr_acl\", proc_get_macaddr_acl, proc_set_macaddr_acl),\n#endif\n#if CONFIG_RTW_PRE_LINK_STA\n\tRTW_PROC_HDL_SSEQ(\"pre_link_sta\", proc_get_pre_link_sta, proc_set_pre_link_sta),\n#endif\n\tRTW_PROC_HDL_SSEQ(\"ch_sel_policy\", proc_get_ch_sel_policy, proc_set_ch_sel_policy),\n#ifdef CONFIG_DFS_MASTER\n\tRTW_PROC_HDL_SSEQ(\"dfs_test_case\", proc_get_dfs_test_case, proc_set_dfs_test_case),\n\tRTW_PROC_HDL_SSEQ(\"update_non_ocp\", NULL, proc_set_update_non_ocp),\n\tRTW_PROC_HDL_SSEQ(\"radar_detect\", NULL, proc_set_radar_detect),\n\tRTW_PROC_HDL_SSEQ(\"dfs_ch_sel_d_flags\", proc_get_dfs_ch_sel_d_flags, proc_set_dfs_ch_sel_d_flags),\n\t#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT\n\tRTW_PROC_HDL_SSEQ(\"dfs_slave_with_rd\", proc_get_dfs_slave_with_rd, proc_set_dfs_slave_with_rd),\n\t#endif\n#endif\n#ifdef CONFIG_BCN_CNT_CONFIRM_HDL\n\tRTW_PROC_HDL_SSEQ(\"new_bcn_max\", proc_get_new_bcn_max, proc_set_new_bcn_max),\n#endif\n\tRTW_PROC_HDL_SSEQ(\"sink_udpport\", proc_get_udpport, proc_set_udpport),\n#ifdef DBG_RX_COUNTER_DUMP\n\tRTW_PROC_HDL_SSEQ(\"dump_rx_cnt_mode\", proc_get_rx_cnt_dump, proc_set_rx_cnt_dump),\n#endif\n\tRTW_PROC_HDL_SSEQ(\"change_bss_chbw\", NULL, proc_set_change_bss_chbw),\n#if CONFIG_TX_AC_LIFETIME\n\tRTW_PROC_HDL_SSEQ(\"tx_aclt_force_val\", proc_get_tx_aclt_force_val, proc_set_tx_aclt_force_val),\n\tRTW_PROC_HDL_SSEQ(\"tx_aclt_flags\", proc_get_tx_aclt_flags, proc_set_tx_aclt_flags),\n\tRTW_PROC_HDL_SSEQ(\"tx_aclt_confs\", proc_get_tx_aclt_confs, proc_set_tx_aclt_confs),\n#endif\n\tRTW_PROC_HDL_SSEQ(\"tx_bw_mode\", proc_get_tx_bw_mode, proc_set_tx_bw_mode),\n\tRTW_PROC_HDL_SSEQ(\"hal_txpwr_info\", proc_get_hal_txpwr_info, NULL),\n\tRTW_PROC_HDL_SSEQ(\"target_tx_power\", proc_get_target_tx_power, NULL),\n\tRTW_PROC_HDL_SSEQ(\"tx_power_by_rate\", proc_get_tx_power_by_rate, NULL),\n#if CONFIG_TXPWR_LIMIT\n\tRTW_PROC_HDL_SSEQ(\"tx_power_limit\", proc_get_tx_power_limit, NULL),\n#endif\n\tRTW_PROC_HDL_SSEQ(\"tx_power_ext_info\", proc_get_tx_power_ext_info, proc_set_tx_power_ext_info),\n\tRTW_PROC_HDL_SEQ(\"tx_power_idx\", &seq_ops_tx_power_idx, NULL),\n#ifdef CONFIG_RF_POWER_TRIM\n\tRTW_PROC_HDL_SSEQ(\"tx_gain_offset\", NULL, proc_set_tx_gain_offset),\n\tRTW_PROC_HDL_SSEQ(\"kfree_flag\", proc_get_kfree_flag, proc_set_kfree_flag),\n\tRTW_PROC_HDL_SSEQ(\"kfree_bb_gain\", proc_get_kfree_bb_gain, proc_set_kfree_bb_gain),\n\tRTW_PROC_HDL_SSEQ(\"kfree_thermal\", proc_get_kfree_thermal, proc_set_kfree_thermal),\n#endif\n#ifdef CONFIG_POWER_SAVING\n\tRTW_PROC_HDL_SSEQ(\"ps_info\", proc_get_ps_info, proc_set_ps_info),\n#ifdef CONFIG_WMMPS_STA\n\tRTW_PROC_HDL_SSEQ(\"wmmps_info\", proc_get_wmmps_info, proc_set_wmmps_info),\n#endif /* CONFIG_WMMPS_STA */\t\n#endif\n#ifdef CONFIG_TDLS\n\tRTW_PROC_HDL_SSEQ(\"tdls_info\", proc_get_tdls_info, NULL),\n\tRTW_PROC_HDL_SSEQ(\"tdls_enable\", proc_get_tdls_enable, proc_set_tdls_enable),\n#endif\n\tRTW_PROC_HDL_SSEQ(\"monitor\", proc_get_monitor, proc_set_monitor),\n\n#ifdef CONFIG_RTW_ACS\n\tRTW_PROC_HDL_SSEQ(\"acs\", proc_get_best_chan, proc_set_acs),\n\tRTW_PROC_HDL_SSEQ(\"chan_info\", proc_get_chan_info, NULL),\n#endif\n\n#ifdef CONFIG_BACKGROUND_NOISE_MONITOR\n\tRTW_PROC_HDL_SSEQ(\"noise_monitor\", proc_get_nm, proc_set_nm),\n#endif\n\n#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER\n\tRTW_PROC_HDL_SSEQ(\"rtkm_info\", proc_get_rtkm_info, NULL),\n#endif\n\tRTW_PROC_HDL_SSEQ(\"efuse_map\", proc_get_efuse_map, NULL),\n#ifdef CONFIG_IEEE80211W\n\tRTW_PROC_HDL_SSEQ(\"11w_tx_sa_query\", proc_get_tx_sa_query, proc_set_tx_sa_query),\n\tRTW_PROC_HDL_SSEQ(\"11w_tx_deauth\", proc_get_tx_deauth, proc_set_tx_deauth),\n\tRTW_PROC_HDL_SSEQ(\"11w_tx_auth\", proc_get_tx_auth, proc_set_tx_auth),\n#endif /* CONFIG_IEEE80211W */\n\n#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA\n\tRTW_PROC_HDL_SSEQ(\"pathb_phase\", proc_get_pathb_phase, proc_set_pathb_phase),\n#endif\n\n#ifdef CONFIG_MBSSID_CAM\n\tRTW_PROC_HDL_SSEQ(\"mbid_cam\", proc_get_mbid_cam_cache, NULL),\n#endif\n\tRTW_PROC_HDL_SSEQ(\"mac_addr\", proc_get_mac_addr, NULL),\n\tRTW_PROC_HDL_SSEQ(\"skip_band\", proc_get_skip_band, proc_set_skip_band),\n\tRTW_PROC_HDL_SSEQ(\"hal_spec\", proc_get_hal_spec, NULL),\n\n\tRTW_PROC_HDL_SSEQ(\"rx_stat\", proc_get_rx_stat, NULL),\n\n\tRTW_PROC_HDL_SSEQ(\"tx_stat\", proc_get_tx_stat, NULL),\n\t/**** PHY Capability ****/\n\tRTW_PROC_HDL_SSEQ(\"phy_cap\", proc_get_phy_cap, NULL),\n#ifdef CONFIG_80211N_HT\n\tRTW_PROC_HDL_SSEQ(\"rx_stbc\", proc_get_rx_stbc, proc_set_rx_stbc),\n\tRTW_PROC_HDL_SSEQ(\"stbc_cap\", proc_get_stbc_cap, proc_set_stbc_cap),\n\tRTW_PROC_HDL_SSEQ(\"ldpc_cap\", proc_get_ldpc_cap, proc_set_ldpc_cap),\n#endif /* CONFIG_80211N_HT */\n#ifdef CONFIG_BEAMFORMING\n\tRTW_PROC_HDL_SSEQ(\"txbf_cap\", proc_get_txbf_cap, proc_set_txbf_cap),\n#endif\n\n#ifdef CONFIG_SUPPORT_TRX_SHARED\n\tRTW_PROC_HDL_SSEQ(\"trx_share_mode\", proc_get_trx_share_mode, NULL),\n#endif\n\tRTW_PROC_HDL_SSEQ(\"napi_info\", proc_get_napi_info, NULL),\n#ifdef CONFIG_RTW_NAPI_DYNAMIC\n\tRTW_PROC_HDL_SSEQ(\"napi_th\", proc_get_napi_info, proc_set_napi_th),\n#endif /* CONFIG_RTW_NAPI_DYNAMIC */\n\n\tRTW_PROC_HDL_SSEQ(\"rsvd_page\", proc_dump_rsvd_page, proc_set_rsvd_page_info),\n\n#ifdef CONFIG_SUPPORT_FIFO_DUMP\n\tRTW_PROC_HDL_SSEQ(\"fifo_dump\", proc_dump_fifo, proc_set_fifo_info),\n#endif\n\tRTW_PROC_HDL_SSEQ(\"fw_info\", proc_get_fw_info, NULL),\n\n#ifdef DBG_XMIT_BLOCK\n\tRTW_PROC_HDL_SSEQ(\"xmit_block\", proc_get_xmit_block, proc_set_xmit_block),\n#endif\n\n\tRTW_PROC_HDL_SSEQ(\"ack_timeout\", proc_get_ack_timeout, proc_set_ack_timeout),\n\n\tRTW_PROC_HDL_SSEQ(\"dynamic_agg_enable\", proc_get_dynamic_agg_enable, proc_set_dynamic_agg_enable),\n\tRTW_PROC_HDL_SSEQ(\"fw_offload\", proc_get_fw_offload, proc_set_fw_offload),\n\n#ifdef CONFIG_RTW_MESH\n\t#if CONFIG_RTW_MESH_ACNODE_PREVENT\n\tRTW_PROC_HDL_SSEQ(\"mesh_acnode_prevent\", proc_get_mesh_acnode_prevent, proc_set_mesh_acnode_prevent),\n\t#endif\n\t#if CONFIG_RTW_MESH_OFFCH_CAND\n\tRTW_PROC_HDL_SSEQ(\"mesh_offch_cand\", proc_get_mesh_offch_cand, proc_set_mesh_offch_cand),\n\t#endif\n\t#if CONFIG_RTW_MESH_PEER_BLACKLIST\n\tRTW_PROC_HDL_SSEQ(\"mesh_peer_blacklist\", proc_get_mesh_peer_blacklist, proc_set_mesh_peer_blacklist),\n\t#endif\n\t#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST\n\tRTW_PROC_HDL_SSEQ(\"mesh_cto_mgate_require\", proc_get_mesh_cto_mgate_require, proc_set_mesh_cto_mgate_require),\n\tRTW_PROC_HDL_SSEQ(\"mesh_cto_mgate_blacklist\", proc_get_mesh_cto_mgate_blacklist, proc_set_mesh_cto_mgate_blacklist),\n\t#endif\n\tRTW_PROC_HDL_SSEQ(\"mesh_peer_sel_policy\", proc_get_mesh_peer_sel_policy, NULL),\n\tRTW_PROC_HDL_SSEQ(\"mesh_networks\", proc_get_mesh_networks, NULL),\n\tRTW_PROC_HDL_SSEQ(\"mesh_plink_ctl\", proc_get_mesh_plink_ctl, NULL),\n\tRTW_PROC_HDL_SSEQ(\"mesh_mpath\", proc_get_mesh_mpath, NULL),\n\tRTW_PROC_HDL_SSEQ(\"mesh_mpp\", proc_get_mesh_mpp, NULL),\n\tRTW_PROC_HDL_SSEQ(\"mesh_known_gates\", proc_get_mesh_known_gates, NULL),\n\t#if CONFIG_RTW_MESH_DATA_BMC_TO_UC\n\tRTW_PROC_HDL_SSEQ(\"mesh_b2u_flags\", proc_get_mesh_b2u_flags, proc_set_mesh_b2u_flags),\n\t#endif\n\tRTW_PROC_HDL_SSEQ(\"mesh_stats\", proc_get_mesh_stats, NULL),\n\tRTW_PROC_HDL_SSEQ(\"mesh_gate_timeout_factor\", proc_get_mesh_gate_timeout, proc_set_mesh_gate_timeout),\n\tRTW_PROC_HDL_SSEQ(\"mesh_gate_state\", proc_get_mesh_gate_state, NULL),\n\tRTW_PROC_HDL_SSEQ(\"mesh_peer_alive_based_preq\", proc_get_peer_alive_based_preq, proc_set_peer_alive_based_preq),\n#endif\n#ifdef CONFIG_FW_HANDLE_TXBCN\n\tRTW_PROC_HDL_SSEQ(\"fw_tbtt_rpt\", proc_get_fw_tbtt_rpt, proc_set_fw_tbtt_rpt),\n#endif\n#ifdef CONFIG_LPS_CHK_BY_TP\n\tRTW_PROC_HDL_SSEQ(\"lps_chk_tp\", proc_get_lps_chk_tp, proc_set_lps_chk_tp),\n#endif\n#ifdef CONFIG_SUPPORT_STATIC_SMPS\n\tRTW_PROC_HDL_SSEQ(\"smps\", proc_get_smps, proc_set_smps),\n#endif\n\n\tRTW_PROC_HDL_SSEQ(\"scan_deny\", proc_get_scan_deny, proc_set_scan_deny),\n#ifdef CONFIG_RTW_TPT_MODE\n\tRTW_PROC_HDL_SSEQ(\"tpt_mode\", proc_get_tpt_mode, proc_set_tpt_mode),\n#endif\n\n#ifdef CONFIG_CTRL_TXSS_BY_TP\n\tRTW_PROC_HDL_SSEQ(\"txss_tp\", proc_get_txss_tp, proc_set_txss_tp),\n\t#ifdef DBG_CTRL_TXSS\n\tRTW_PROC_HDL_SSEQ(\"txss_ctrl\", proc_get_txss_ctrl, proc_set_txss_ctrl),\n\t#endif\n#endif\n\n\tRTW_PROC_HDL_SSEQ(\"cur_beacon_keys\", proc_get_cur_beacon_keys, NULL),\n};\n\nconst int adapter_proc_hdls_num = sizeof(adapter_proc_hdls) / sizeof(struct rtw_proc_hdl);\n\nstatic int rtw_adapter_proc_open(struct inode *inode, struct file *file)\n{\n\tssize_t index = (ssize_t)PDE_DATA(inode);\n\tconst struct rtw_proc_hdl *hdl = adapter_proc_hdls + index;\n\tvoid *private = proc_get_parent_data(inode);\n\n\tif (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {\n\t\tint res = seq_open(file, hdl->u.seq_op);\n\n\t\tif (res == 0)\n\t\t\t((struct seq_file *)file->private_data)->private = private;\n\n\t\treturn res;\n\t} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {\n\t\tint (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;\n\n\t\treturn single_open(file, show, private);\n\t} else {\n\t\treturn -EROFS;\n\t}\n}\n\nstatic ssize_t rtw_adapter_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)\n{\n\tssize_t index = (ssize_t)PDE_DATA(file_inode(file));\n\tconst struct rtw_proc_hdl *hdl = adapter_proc_hdls + index;\n\tssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;\n\n\tif (write)\n\t\treturn write(file, buffer, count, pos, ((struct seq_file *)file->private_data)->private);\n\n\treturn -EROFS;\n}\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0))\nstatic const struct file_operations rtw_adapter_proc_seq_fops = {\n\t.owner = THIS_MODULE,\n\t.open = rtw_adapter_proc_open,\n\t.read = seq_read,\n\t.llseek = seq_lseek,\n\t.release = seq_release,\n\t.write = rtw_adapter_proc_write,\n};\n\nstatic const struct file_operations rtw_adapter_proc_sseq_fops = {\n\t.owner = THIS_MODULE,\n\t.open = rtw_adapter_proc_open,\n\t.read = seq_read,\n\t.llseek = seq_lseek,\n\t.release = single_release,\n\t.write = rtw_adapter_proc_write,\n};\n#else\nstatic const struct proc_ops rtw_adapter_proc_seq_fops = {\n\t.proc_open = rtw_adapter_proc_open,\n\t.proc_read = seq_read,\n\t.proc_lseek = seq_lseek,\n\t.proc_release = seq_release,\n\t.proc_write = rtw_adapter_proc_write,\n};\n\nstatic const struct proc_ops rtw_adapter_proc_sseq_fops = {\n\t.proc_open = rtw_adapter_proc_open,\n\t.proc_read = seq_read,\n\t.proc_lseek = seq_lseek,\n\t.proc_release = single_release,\n\t.proc_write = rtw_adapter_proc_write,\n};\n#endif\n\nint proc_get_odm_adaptivity(struct seq_file *m, void *v)\n{\n\tstruct net_device *dev = m->private;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\n\trtw_odm_adaptivity_parm_msg(m, padapter);\n\n\treturn 0;\n}\n\nssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *dev = data;\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);\n\tchar tmp[32];\n\tu32 th_l2h_ini;\n\ts8 th_edcca_hl_diff;\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp)) {\n\t\trtw_warn_on(1);\n\t\treturn -EFAULT;\n\t}\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\n\t\tint num = sscanf(tmp, \"%x %hhd\", &th_l2h_ini, &th_edcca_hl_diff);\n\n\t\tif (num != 2)\n\t\t\treturn count;\n\n\t\trtw_odm_adaptivity_parm_set(padapter, (s8)th_l2h_ini, th_edcca_hl_diff);\n\t}\n\n\treturn count;\n}\n\nstatic char *phydm_msg = NULL;\n#define PHYDM_MSG_LEN\t80*24\n\nint proc_get_phydm_cmd(struct seq_file *m, void *v)\n{\n\tstruct net_device *netdev;\n\tPADAPTER padapter;\n\tstruct dm_struct *phydm;\n\n\n\tnetdev = m->private;\n\tpadapter = (PADAPTER)rtw_netdev_priv(netdev);\n\tphydm = adapter_to_phydm(padapter);\n\n\tif (NULL == phydm_msg) {\n\t\tphydm_msg = rtw_zmalloc(PHYDM_MSG_LEN);\n\t\tif (NULL == phydm_msg)\n\t\t\treturn -ENOMEM;\n\n\t\tphydm_cmd(phydm, NULL, 0, 0, phydm_msg, PHYDM_MSG_LEN);\n\t}\n\n\t_RTW_PRINT_SEL(m, \"%s\\n\", phydm_msg);\n\n\trtw_mfree(phydm_msg, PHYDM_MSG_LEN);\n\tphydm_msg = NULL;\n\n\treturn 0;\n}\n\nssize_t proc_set_phydm_cmd(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)\n{\n\tstruct net_device *netdev;\n\tPADAPTER padapter;\n\tstruct dm_struct *phydm;\n\tchar tmp[64] = {0};\n\n\n\tnetdev = (struct net_device *)data;\n\tpadapter = (PADAPTER)rtw_netdev_priv(netdev);\n\tphydm = adapter_to_phydm(padapter);\n\n\tif (count < 1)\n\t\treturn -EFAULT;\n\n\tif (count > sizeof(tmp))\n\t\treturn -EFAULT;\n\n\tif (buffer && !copy_from_user(tmp, buffer, count)) {\n\t\tif (NULL == phydm_msg) {\n\t\t\tphydm_msg = rtw_zmalloc(PHYDM_MSG_LEN);\n\t\t\tif (NULL == phydm_msg)\n\t\t\t\treturn -ENOMEM;\n\t\t} else\n\t\t\t_rtw_memset(phydm_msg, 0, PHYDM_MSG_LEN);\n\n\t\tphydm_cmd(phydm, tmp, count, 1, phydm_msg, PHYDM_MSG_LEN);\n\n\t\tif (strlen(phydm_msg) == 0) {\n\t\t\trtw_mfree(phydm_msg, PHYDM_MSG_LEN);\n\t\t\tphydm_msg = NULL;\n\t\t}\n\t}\n\n\treturn count;\n}\n\n/*\n* rtw_odm_proc:\n* init/deinit when register/unregister net_device, along with rtw_adapter_proc\n*/\nconst struct rtw_proc_hdl odm_proc_hdls[] = {\n\tRTW_PROC_HDL_SSEQ(\"adaptivity\", proc_get_odm_adaptivity, proc_set_odm_adaptivity),\n\tRTW_PROC_HDL_SSEQ(\"cmd\", proc_get_phydm_cmd, proc_set_phydm_cmd),\n};\n\nconst int odm_proc_hdls_num = sizeof(odm_proc_hdls) / sizeof(struct rtw_proc_hdl);\n\nstatic int rtw_odm_proc_open(struct inode *inode, struct file *file)\n{\n\tssize_t index = (ssize_t)PDE_DATA(inode);\n\tconst struct rtw_proc_hdl *hdl = odm_proc_hdls + index;\n\tvoid *private = proc_get_parent_data(inode);\n\n\tif (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {\n\t\tint res = seq_open(file, hdl->u.seq_op);\n\n\t\tif (res == 0)\n\t\t\t((struct seq_file *)file->private_data)->private = private;\n\n\t\treturn res;\n\t} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {\n\t\tint (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;\n\n\t\treturn single_open(file, show, private);\n\t} else {\n\t\treturn -EROFS;\n\t}\n}\n\nstatic ssize_t rtw_odm_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)\n{\n\tssize_t index = (ssize_t)PDE_DATA(file_inode(file));\n\tconst struct rtw_proc_hdl *hdl = odm_proc_hdls + index;\n\tssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;\n\n\tif (write)\n\t\treturn write(file, buffer, count, pos, ((struct seq_file *)file->private_data)->private);\n\n\treturn -EROFS;\n}\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0))\nstatic const struct file_operations rtw_odm_proc_seq_fops = {\n\t.owner = THIS_MODULE,\n\t.open = rtw_odm_proc_open,\n\t.read = seq_read,\n\t.llseek = seq_lseek,\n\t.release = seq_release,\n\t.write = rtw_odm_proc_write,\n};\n\nstatic const struct file_operations rtw_odm_proc_sseq_fops = {\n\t.owner = THIS_MODULE,\n\t.open = rtw_odm_proc_open,\n\t.read = seq_read,\n\t.llseek = seq_lseek,\n\t.release = single_release,\n\t.write = rtw_odm_proc_write,\n};\n#else\nstatic const struct proc_ops rtw_odm_proc_seq_fops = {\n\t.proc_open = rtw_odm_proc_open,\n\t.proc_read = seq_read,\n\t.proc_lseek = seq_lseek,\n\t.proc_release = seq_release,\n\t.proc_write = rtw_odm_proc_write,\n};\n\nstatic const struct proc_ops rtw_odm_proc_sseq_fops = {\n\t.proc_open = rtw_odm_proc_open,\n\t.proc_read = seq_read,\n\t.proc_lseek = seq_lseek,\n\t.proc_release = single_release,\n\t.proc_write = rtw_odm_proc_write,\n};\n#endif\n\nstruct proc_dir_entry *rtw_odm_proc_init(struct net_device *dev)\n{\n\tstruct proc_dir_entry *dir_odm = NULL;\n\tstruct proc_dir_entry *entry = NULL;\n\t_adapter\t*adapter = rtw_netdev_priv(dev);\n\tssize_t i;\n\n\tif (adapter->dir_dev == NULL) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (adapter->dir_odm != NULL) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tdir_odm = rtw_proc_create_dir(\"odm\", adapter->dir_dev, dev);\n\tif (dir_odm == NULL) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tadapter->dir_odm = dir_odm;\n\n\tfor (i = 0; i < odm_proc_hdls_num; i++) {\n\t\tif (odm_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)\n\t\t\tentry = rtw_proc_create_entry(odm_proc_hdls[i].name, dir_odm, &rtw_odm_proc_seq_fops, (void *)i);\n\t\telse if (odm_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ)\n\t\t\tentry = rtw_proc_create_entry(odm_proc_hdls[i].name, dir_odm, &rtw_odm_proc_sseq_fops, (void *)i);\n\t\telse\n\t\t\tentry = NULL;\n\n\t\tif (!entry) {\n\t\t\trtw_warn_on(1);\n\t\t\tgoto exit;\n\t\t}\n\t}\n\nexit:\n\treturn dir_odm;\n}\n\nvoid rtw_odm_proc_deinit(_adapter\t*adapter)\n{\n\tstruct proc_dir_entry *dir_odm = NULL;\n\tint i;\n\n\tdir_odm = adapter->dir_odm;\n\n\tif (dir_odm == NULL) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tfor (i = 0; i < odm_proc_hdls_num; i++)\n\t\tremove_proc_entry(odm_proc_hdls[i].name, dir_odm);\n\n\tremove_proc_entry(\"odm\", adapter->dir_dev);\n\n\tadapter->dir_odm = NULL;\n\n\tif (phydm_msg) {\n\t\trtw_mfree(phydm_msg, PHYDM_MSG_LEN);\n\t\tphydm_msg = NULL;\n\t}\n}\n\n#ifdef CONFIG_MCC_MODE\n/*\n* rtw_mcc_proc:\n* init/deinit when register/unregister net_device, along with rtw_adapter_proc\n*/\nconst struct rtw_proc_hdl mcc_proc_hdls[] = {\n\tRTW_PROC_HDL_SSEQ(\"mcc_info\", proc_get_mcc_info, NULL),\n\tRTW_PROC_HDL_SSEQ(\"mcc_enable\", proc_get_mcc_info, proc_set_mcc_enable),\n\tRTW_PROC_HDL_SSEQ(\"mcc_duration\", proc_get_mcc_info, proc_set_mcc_duration),\n\t#ifdef CONFIG_MCC_PHYDM_OFFLOAD\n\tRTW_PROC_HDL_SSEQ(\"mcc_phydm_offload\", proc_get_mcc_info, proc_set_mcc_phydm_offload_enable),\n\t#endif\n\tRTW_PROC_HDL_SSEQ(\"mcc_single_tx_criteria\", proc_get_mcc_info, proc_set_mcc_single_tx_criteria),\n\tRTW_PROC_HDL_SSEQ(\"mcc_ap_bw20_target_tp\", proc_get_mcc_info, proc_set_mcc_ap_bw20_target_tp),\n\tRTW_PROC_HDL_SSEQ(\"mcc_ap_bw40_target_tp\", proc_get_mcc_info, proc_set_mcc_ap_bw40_target_tp),\n\tRTW_PROC_HDL_SSEQ(\"mcc_ap_bw80_target_tp\", proc_get_mcc_info, proc_set_mcc_ap_bw80_target_tp),\n\tRTW_PROC_HDL_SSEQ(\"mcc_sta_bw20_target_tp\", proc_get_mcc_info, proc_set_mcc_sta_bw20_target_tp),\n\tRTW_PROC_HDL_SSEQ(\"mcc_sta_bw40_target_tp\", proc_get_mcc_info, proc_set_mcc_sta_bw40_target_tp),\n\tRTW_PROC_HDL_SSEQ(\"mcc_sta_bw80_target_tp\", proc_get_mcc_info, proc_set_mcc_sta_bw80_target_tp),\n\tRTW_PROC_HDL_SSEQ(\"mcc_policy_table\", proc_get_mcc_policy_table, NULL),\n};\n\nconst int mcc_proc_hdls_num = sizeof(mcc_proc_hdls) / sizeof(struct rtw_proc_hdl);\n\nstatic int rtw_mcc_proc_open(struct inode *inode, struct file *file)\n{\n\tssize_t index = (ssize_t)PDE_DATA(inode);\n\tconst struct rtw_proc_hdl *hdl = mcc_proc_hdls + index;\n\tvoid *private = proc_get_parent_data(inode);\n\n\tif (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {\n\t\tint res = seq_open(file, hdl->u.seq_op);\n\n\t\tif (res == 0)\n\t\t\t((struct seq_file *)file->private_data)->private = private;\n\n\t\treturn res;\n\t} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {\n\t\tint (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;\n\n\t\treturn single_open(file, show, private);\n\t} else {\n\t\treturn -EROFS;\n\t}\n}\n\nstatic ssize_t rtw_mcc_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)\n{\n\tssize_t index = (ssize_t)PDE_DATA(file_inode(file));\n\tconst struct rtw_proc_hdl *hdl = mcc_proc_hdls + index;\n\tssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;\n\n\tif (write)\n\t\treturn write(file, buffer, count, pos, ((struct seq_file *)file->private_data)->private);\n\n\treturn -EROFS;\n}\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0))\nstatic const struct file_operations rtw_mcc_proc_seq_fops = {\n\t.owner = THIS_MODULE,\n\t.open = rtw_mcc_proc_open,\n\t.read = seq_read,\n\t.llseek = seq_lseek,\n\t.release = seq_release,\n\t.write = rtw_mcc_proc_write,\n};\n\nstatic const struct file_operations rtw_mcc_proc_sseq_fops = {\n\t.owner = THIS_MODULE,\n\t.open = rtw_mcc_proc_open,\n\t.read = seq_read,\n\t.llseek = seq_lseek,\n\t.release = single_release,\n\t.write = rtw_mcc_proc_write,\n};\n#else\nstatic const struct proc_ops rtw_mcc_proc_seq_fops = {\n\t.proc_owner = THIS_MODULE,\n\t.proc_open = rtw_mcc_proc_open,\n\t.proc_read = seq_read,\n\t.proc_lseek = seq_lseek,\n\t.proc_release = seq_release,\n\t.proc_write = rtw_mcc_proc_write,\n};\n\nstatic const struct proc_ops rtw_mcc_proc_sseq_fops = {\n\t.proc_owner = THIS_MODULE,\n\t.proc_open = rtw_mcc_proc_open,\n\t.proc_read = seq_read,\n\t.proc_lseek = seq_lseek,\n\t.proc_release = single_release,\n\t.proc_write = rtw_mcc_proc_write,\n};\n#endif\n\nstruct proc_dir_entry *rtw_mcc_proc_init(struct net_device *dev)\n{\n\tstruct proc_dir_entry *dir_mcc = NULL;\n\tstruct proc_dir_entry *entry = NULL;\n\t_adapter\t*adapter = rtw_netdev_priv(dev);\n\tssize_t i;\n\n\tif (adapter->dir_dev == NULL) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (adapter->dir_mcc != NULL) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tdir_mcc = rtw_proc_create_dir(\"mcc\", adapter->dir_dev, dev);\n\tif (dir_mcc == NULL) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tadapter->dir_mcc = dir_mcc;\n\n\tfor (i = 0; i < mcc_proc_hdls_num; i++) {\n\t\tif (mcc_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)\n\t\t\tentry = rtw_proc_create_entry(mcc_proc_hdls[i].name, dir_mcc, &rtw_mcc_proc_seq_fops, (void *)i);\n\t\telse if (mcc_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ)\n\t\t\tentry = rtw_proc_create_entry(mcc_proc_hdls[i].name, dir_mcc, &rtw_mcc_proc_sseq_fops, (void *)i);\n\t\telse\n\t\t\tentry = NULL;\n\n\t\tif (!entry) {\n\t\t\trtw_warn_on(1);\n\t\t\tgoto exit;\n\t\t}\n\t}\n\nexit:\n\treturn dir_mcc;\n}\n\nvoid rtw_mcc_proc_deinit(_adapter\t*adapter)\n{\n\tstruct proc_dir_entry *dir_mcc = NULL;\n\tint i;\n\n\tdir_mcc = adapter->dir_mcc;\n\n\tif (dir_mcc == NULL) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tfor (i = 0; i < mcc_proc_hdls_num; i++)\n\t\tremove_proc_entry(mcc_proc_hdls[i].name, dir_mcc);\n\n\tremove_proc_entry(\"mcc\", adapter->dir_dev);\n\n\tadapter->dir_mcc = NULL;\n}\n#endif /* CONFIG_MCC_MODE */\n\nstruct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev)\n{\n\tstruct proc_dir_entry *drv_proc = get_rtw_drv_proc();\n\tstruct proc_dir_entry *dir_dev = NULL;\n\tstruct proc_dir_entry *entry = NULL;\n\t_adapter *adapter = rtw_netdev_priv(dev);\n\tssize_t i;\n\n\tif (drv_proc == NULL) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (adapter->dir_dev != NULL) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tdir_dev = rtw_proc_create_dir(dev->name, drv_proc, dev);\n\tif (dir_dev == NULL) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tadapter->dir_dev = dir_dev;\n\n\tfor (i = 0; i < adapter_proc_hdls_num; i++) {\n\t\tif (adapter_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)\n\t\t\tentry = rtw_proc_create_entry(adapter_proc_hdls[i].name, dir_dev, &rtw_adapter_proc_seq_fops, (void *)i);\n\t\telse if (adapter_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ)\n\t\t\tentry = rtw_proc_create_entry(adapter_proc_hdls[i].name, dir_dev, &rtw_adapter_proc_sseq_fops, (void *)i);\n\t\telse\n\t\t\tentry = NULL;\n\n\t\tif (!entry) {\n\t\t\trtw_warn_on(1);\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\trtw_odm_proc_init(dev);\n\n#ifdef CONFIG_MCC_MODE\n\trtw_mcc_proc_init(dev);\n#endif /* CONFIG_MCC_MODE */\n\nexit:\n\treturn dir_dev;\n}\n\nvoid rtw_adapter_proc_deinit(struct net_device *dev)\n{\n\tstruct proc_dir_entry *drv_proc = get_rtw_drv_proc();\n\tstruct proc_dir_entry *dir_dev = NULL;\n\t_adapter *adapter = rtw_netdev_priv(dev);\n\tint i;\n\n\tdir_dev = adapter->dir_dev;\n\n\tif (dir_dev == NULL) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tfor (i = 0; i < adapter_proc_hdls_num; i++)\n\t\tremove_proc_entry(adapter_proc_hdls[i].name, dir_dev);\n\n\trtw_odm_proc_deinit(adapter);\n\n#ifdef CONFIG_MCC_MODE\n\trtw_mcc_proc_deinit(adapter);\n#endif /* CONFIG_MCC_MODE */\n\n\tremove_proc_entry(dev->name, drv_proc);\n\n\tadapter->dir_dev = NULL;\n}\n\nvoid rtw_adapter_proc_replace(struct net_device *dev)\n{\n\tstruct proc_dir_entry *drv_proc = get_rtw_drv_proc();\n\tstruct proc_dir_entry *dir_dev = NULL;\n\t_adapter *adapter = rtw_netdev_priv(dev);\n\tint i;\n\n\tdir_dev = adapter->dir_dev;\n\n\tif (dir_dev == NULL) {\n\t\trtw_warn_on(1);\n\t\treturn;\n\t}\n\n\tfor (i = 0; i < adapter_proc_hdls_num; i++)\n\t\tremove_proc_entry(adapter_proc_hdls[i].name, dir_dev);\n\n\trtw_odm_proc_deinit(adapter);\n\n#ifdef CONFIG_MCC_MODE\n\trtw_mcc_proc_deinit(adapter);\n#endif /* CONIG_MCC_MODE */\n\n\tremove_proc_entry(adapter->old_ifname, drv_proc);\n\n\tadapter->dir_dev = NULL;\n\n\trtw_adapter_proc_init(dev);\n\n}\n\n#endif /* CONFIG_PROC_DEBUG */\n"
  },
  {
    "path": "os_dep/linux/rtw_proc.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_PROC_H__\n#define __RTW_PROC_H__\n\n#include <linux/proc_fs.h>\n#include <linux/seq_file.h>\n\n#define RTW_PROC_HDL_TYPE_SEQ\t0\n#define RTW_PROC_HDL_TYPE_SSEQ\t1\n\nstruct rtw_proc_hdl {\n\tchar *name;\n\tu8 type;\n\tunion {\n\t\tint (*show)(struct seq_file *, void *);\n\t\tstruct seq_operations *seq_op;\n\t} u;\n\tssize_t (*write)(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);\n};\n\n#define RTW_PROC_HDL_SEQ(_name, _seq_op, _write) \\\n\t{ .name = _name, .type = RTW_PROC_HDL_TYPE_SEQ, .u.seq_op = _seq_op, .write = _write}\n\n#define RTW_PROC_HDL_SSEQ(_name, _show, _write) \\\n\t{ .name = _name, .type = RTW_PROC_HDL_TYPE_SSEQ, .u.show = _show, .write = _write}\n\n#ifdef CONFIG_PROC_DEBUG\n\nint rtw_drv_proc_init(void);\nvoid rtw_drv_proc_deinit(void);\nstruct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev);\nvoid rtw_adapter_proc_deinit(struct net_device *dev);\nvoid rtw_adapter_proc_replace(struct net_device *dev);\n\n#else /* !CONFIG_PROC_DEBUG */\n\nstatic inline int rtw_drv_proc_init(void) {return _FAIL;}\n#define rtw_drv_proc_deinit() do {} while (0)\nstatic inline struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev) {return NULL;}\n#define rtw_adapter_proc_deinit(dev) do {} while (0)\n#define rtw_adapter_proc_replace(dev) do {} while (0)\n\n#endif /* !CONFIG_PROC_DEBUG */\n\n#endif /* __RTW_PROC_H__ */\n"
  },
  {
    "path": "os_dep/linux/rtw_rhashtable.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#ifdef CONFIG_RTW_MESH /* for now, only promised for kernel versions we support mesh */\n\n#include <drv_types.h>\n\nint rtw_rhashtable_walk_enter(rtw_rhashtable *ht, rtw_rhashtable_iter *iter)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0))\n\trhashtable_walk_enter((ht), (iter));\n\treturn 0;\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))\n\treturn rhashtable_walk_init((ht), (iter), GFP_ATOMIC);\n#else\n\t/* kernel >= 4.4.0 rhashtable_walk_init use GFP_KERNEL to alloc, spin_lock for assignment */\n\titer->ht = ht;\n\titer->p = NULL;\n\titer->slot = 0;\n\titer->skip = 0;\n\n\titer->walker = kmalloc(sizeof(*iter->walker), GFP_ATOMIC);\n\tif (!iter->walker)\n\t\treturn -ENOMEM;\n\n\tspin_lock(&ht->lock);\n\titer->walker->tbl =\n\t\trcu_dereference_protected(ht->tbl, lockdep_is_held(&ht->lock));\n\tlist_add(&iter->walker->list, &iter->walker->tbl->walkers);\n\tspin_unlock(&ht->lock);\n\n\treturn 0;\n#endif\n}\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0))\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25))\nstatic inline int is_vmalloc_addr(const void *x)\n{\n#ifdef CONFIG_MMU\n\tunsigned long addr = (unsigned long)x;\n\n\treturn addr >= VMALLOC_START && addr < VMALLOC_END;\n#else\n\treturn 0;\n#endif\n}\n#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25)) */\n\nvoid kvfree(const void *addr)\n{\n\tif (is_vmalloc_addr(addr))\n\t\tvfree(addr);\n\telse\n\t\tkfree(addr);\n}\n#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)) */\n\n#include \"rhashtable.c\"\n\n#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) */\n\n#endif /* CONFIG_RTW_MESH */\n\n"
  },
  {
    "path": "os_dep/linux/rtw_rhashtable.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __RTW_RHASHTABLE_H__\n#define __RTW_RHASHTABLE_H__\n\n#ifdef CONFIG_RTW_MESH /* for now, only promised for kernel versions we support mesh */\n\n/* directly reference rhashtable in kernel */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))\n#include <linux/rhashtable.h>\n#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) */\n\n/* Use rhashtable from kernel 4.4 */\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))\n#define NULLS_MARKER(value) (1UL | (((long)value) << 1))\n#endif\n#include \"rhashtable.h\"\n#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) */\n\ntypedef struct rhashtable rtw_rhashtable;\ntypedef struct rhash_head rtw_rhash_head;\ntypedef struct rhashtable_params rtw_rhashtable_params;\n\n#define rtw_rhashtable_init(ht, params) rhashtable_init(ht, params)\n\ntypedef struct rhashtable_iter rtw_rhashtable_iter;\n\nint rtw_rhashtable_walk_enter(rtw_rhashtable *ht, rtw_rhashtable_iter *iter);\n#define rtw_rhashtable_walk_exit(iter) rhashtable_walk_exit(iter)\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 16, 0))\n#define rtw_rhashtable_walk_start(iter) rhashtable_walk_start_check(iter)\n#else\n#define rtw_rhashtable_walk_start(iter) rhashtable_walk_start(iter)\n#endif\n#define rtw_rhashtable_walk_next(iter) rhashtable_walk_next(iter)\n#define rtw_rhashtable_walk_stop(iter) rhashtable_walk_stop(iter)\n\n#define rtw_rhashtable_free_and_destroy(ht, free_fn, arg) rhashtable_free_and_destroy((ht), (free_fn), (arg))\n#define rtw_rhashtable_lookup_fast(ht, key, params) rhashtable_lookup_fast((ht), (key), (params))\n#define rtw_rhashtable_lookup_insert_fast(ht, obj, params) rhashtable_lookup_insert_fast((ht), (obj), (params))\n#define rtw_rhashtable_remove_fast(ht, obj, params) rhashtable_remove_fast((ht), (obj), (params))\n\n#endif /* CONFIG_RTW_MESH */\n\n#endif /* __RTW_RHASHTABLE_H__ */\n\n"
  },
  {
    "path": "os_dep/linux/wifi_regd.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2009-2010 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#include <drv_types.h>\n\n#ifdef CONFIG_IOCTL_CFG80211\n\n#include <rtw_wifi_regd.h>\n\nstatic struct country_code_to_enum_rd allCountries[] = {\n\t{COUNTRY_CODE_USER, \"RD\"},\n};\n\n/*\n * REG_RULE(freq start, freq end, bandwidth, max gain, eirp, reg_flags)\n */\n\n/*\n *Only these channels all allow active\n *scan on all world regulatory domains\n */\n\n/* 2G chan 01 - chan 11 */\n#define RTW_2GHZ_CH01_11\t\\\n\tREG_RULE(2412-10, 2462+10, 40, 0, 20, 0)\n\n/*\n *We enable active scan on these a case\n *by case basis by regulatory domain\n */\n\n/* 2G chan 12 - chan 13, PASSIV SCAN */\n#define RTW_2GHZ_CH12_13\t\\\n\tREG_RULE(2467-10, 2472+10, 40, 0, 20,\t\\\n\t\t NL80211_RRF_PASSIVE_SCAN)\n\n/* 2G chan 14, PASSIVS SCAN, NO OFDM (B only) */\n#define RTW_2GHZ_CH14\t\\\n\tREG_RULE(2484-10, 2484+10, 40, 0, 20,\t\\\n\t\t NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_OFDM)\n\n/* 5G chan 36 - chan 64 */\n#define RTW_5GHZ_5150_5350\t\\\n\tREG_RULE(5150-10, 5350+10, 40, 0, 30,\t\\\n\t\t NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)\n\n/* 5G chan 100 - chan 165 */\n#define RTW_5GHZ_5470_5850\t\\\n\tREG_RULE(5470-10, 5850+10, 40, 0, 30, \\\n\t\t NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)\n\n/* 5G chan 149 - chan 165 */\n#define RTW_5GHZ_5725_5850\t\\\n\tREG_RULE(5725-10, 5850+10, 40, 0, 30, \\\n\t\t NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)\n\n/* 5G chan 36 - chan 165 */\n#define RTW_5GHZ_5150_5850\t\\\n\tREG_RULE(5150-10, 5850+10, 40, 0, 30,\t\\\n\t\t NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)\n\nstatic const struct ieee80211_regdomain rtw_regdom_rd = {\n\t.n_reg_rules = 3,\n\t.alpha2 = \"99\",\n\t.reg_rules = {\n\t\tRTW_2GHZ_CH01_11,\n\t\tRTW_2GHZ_CH12_13,\n\t\tRTW_5GHZ_5150_5850,\n\t}\n};\n\nstatic const struct ieee80211_regdomain rtw_regdom_11 = {\n\t.n_reg_rules = 1,\n\t.alpha2 = \"99\",\n\t.reg_rules = {\n\t\tRTW_2GHZ_CH01_11,\n\t}\n};\n\nstatic const struct ieee80211_regdomain rtw_regdom_12_13 = {\n\t.n_reg_rules = 2,\n\t.alpha2 = \"99\",\n\t.reg_rules = {\n\t\tRTW_2GHZ_CH01_11,\n\t\tRTW_2GHZ_CH12_13,\n\t}\n};\n\nstatic const struct ieee80211_regdomain rtw_regdom_no_midband = {\n\t.n_reg_rules = 3,\n\t.alpha2 = \"99\",\n\t.reg_rules = {\n\t\tRTW_2GHZ_CH01_11,\n\t\tRTW_5GHZ_5150_5350,\n\t\tRTW_5GHZ_5725_5850,\n\t}\n};\n\nstatic const struct ieee80211_regdomain rtw_regdom_60_64 = {\n\t.n_reg_rules = 3,\n\t.alpha2 = \"99\",\n\t.reg_rules = {\n\t\tRTW_2GHZ_CH01_11,\n\t\tRTW_2GHZ_CH12_13,\n\t\tRTW_5GHZ_5725_5850,\n\t}\n};\n\nstatic const struct ieee80211_regdomain rtw_regdom_14_60_64 = {\n\t.n_reg_rules = 4,\n\t.alpha2 = \"99\",\n\t.reg_rules = {\n\t\tRTW_2GHZ_CH01_11,\n\t\tRTW_2GHZ_CH12_13,\n\t\tRTW_2GHZ_CH14,\n\t\tRTW_5GHZ_5725_5850,\n\t}\n};\n\nstatic const struct ieee80211_regdomain rtw_regdom_14 = {\n\t.n_reg_rules = 3,\n\t.alpha2 = \"99\",\n\t.reg_rules = {\n\t\tRTW_2GHZ_CH01_11,\n\t\tRTW_2GHZ_CH12_13,\n\t\tRTW_2GHZ_CH14,\n\t}\n};\n\n#if 0\nstatic struct rtw_regulatory *rtw_regd;\n#endif\n\n#if 0 /* not_yet */\nstatic void _rtw_reg_apply_beaconing_flags(struct wiphy *wiphy,\n\t\tenum nl80211_reg_initiator initiator)\n{\n\tenum nl80211_band band;\n\tstruct ieee80211_supported_band *sband;\n\tconst struct ieee80211_reg_rule *reg_rule;\n\tstruct ieee80211_channel *ch;\n\tunsigned int i;\n\tu32 bandwidth = 0;\n\tint r;\n\n\tfor (band = 0; band < NUM_NL80211_BANDS; band++) {\n\n\t\tif (!wiphy->bands[band])\n\t\t\tcontinue;\n\n\t\tsband = wiphy->bands[band];\n\n\t\tfor (i = 0; i < sband->n_channels; i++) {\n\t\t\tch = &sband->channels[i];\n\t\t\tif (rtw_is_dfs_ch(ch->hw_value) ||\n\t\t\t    (ch->flags & IEEE80211_CHAN_RADAR))\n\t\t\t\tcontinue;\n\t\t\tif (initiator == NL80211_REGDOM_SET_BY_COUNTRY_IE) {\n\t\t\t\tr = freq_reg_info(wiphy, ch->center_freq,\n\t\t\t\t\t\t  bandwidth, &reg_rule);\n\t\t\t\tif (r)\n\t\t\t\t\tcontinue;\n\n\t\t\t\t/*\n\t\t\t\t *If 11d had a rule for this channel ensure\n\t\t\t\t *we enable adhoc/beaconing if it allows us to\n\t\t\t\t *use it. Note that we would have disabled it\n\t\t\t\t *by applying our static world regdomain by\n\t\t\t\t *default during init, prior to calling our\n\t\t\t\t *regulatory_hint().\n\t\t\t\t */\n\n\t\t\t\tif (!(reg_rule->flags & NL80211_RRF_NO_IBSS))\n\t\t\t\t\tch->flags &= ~IEEE80211_CHAN_NO_IBSS;\n\t\t\t\tif (!\n\t\t\t\t    (reg_rule->flags &\n\t\t\t\t     NL80211_RRF_PASSIVE_SCAN))\n\t\t\t\t\tch->flags &=\n\t\t\t\t\t\t~IEEE80211_CHAN_PASSIVE_SCAN;\n\t\t\t} else {\n\t\t\t\tif (ch->beacon_found)\n\t\t\t\t\tch->flags &= ~(IEEE80211_CHAN_NO_IBSS |\n\t\t\t\t\t\tIEEE80211_CHAN_PASSIVE_SCAN);\n\t\t\t}\n\t\t}\n\t}\n}\n\n/* Allows active scan scan on Ch 12 and 13 */\nstatic void _rtw_reg_apply_active_scan_flags(struct wiphy *wiphy,\n\t\tenum nl80211_reg_initiator\n\t\tinitiator)\n{\n\tstruct ieee80211_supported_band *sband;\n\tstruct ieee80211_channel *ch;\n\tconst struct ieee80211_reg_rule *reg_rule;\n\tu32 bandwidth = 0;\n\tint r;\n\n\tif (!wiphy->bands[NL80211_BAND_2GHZ])\n\t\treturn;\n\tsband = wiphy->bands[NL80211_BAND_2GHZ];\n\n\t/*\n\t * If no country IE has been received always enable active scan\n\t * on these channels. This is only done for specific regulatory SKUs\n\t */\n\tif (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {\n\t\tch = &sband->channels[11];\t/* CH 12 */\n\t\tif (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)\n\t\t\tch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;\n\t\tch = &sband->channels[12];\t/* CH 13 */\n\t\tif (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)\n\t\t\tch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;\n\t\treturn;\n\t}\n\n\t/*\n\t * If a country IE has been received check its rule for this\n\t * channel first before enabling active scan. The passive scan\n\t * would have been enforced by the initial processing of our\n\t * custom regulatory domain.\n\t */\n\n\tch = &sband->channels[11];\t/* CH 12 */\n\tr = freq_reg_info(wiphy, ch->center_freq, bandwidth, &reg_rule);\n\tif (!r) {\n\t\tif (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))\n\t\t\tif (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)\n\t\t\t\tch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;\n\t}\n\n\tch = &sband->channels[12];\t/* CH 13 */\n\tr = freq_reg_info(wiphy, ch->center_freq, bandwidth, &reg_rule);\n\tif (!r) {\n\t\tif (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))\n\t\t\tif (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)\n\t\t\t\tch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;\n\t}\n}\n#endif\n\nvoid rtw_regd_apply_flags(struct wiphy *wiphy)\n{\n\tstruct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);\n\tstruct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);\n\tRT_CHANNEL_INFO *channel_set = rfctl->channel_set;\n\tu8 max_chan_nums = rfctl->max_chan_nums;\n\n\tstruct ieee80211_supported_band *sband;\n\tstruct ieee80211_channel *ch;\n\tunsigned int i, j;\n\tu16 channel;\n\tu32 freq;\n\n\t/* all channels disable */\n\tfor (i = 0; i < NUM_NL80211_BANDS; i++) {\n\t\tsband = wiphy->bands[i];\n\n\t\tif (sband) {\n\t\t\tfor (j = 0; j < sband->n_channels; j++) {\n\t\t\t\tch = &sband->channels[j];\n\n\t\t\t\tif (ch)\n\t\t\t\t\tch->flags = IEEE80211_CHAN_DISABLED;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* channels apply by channel plans. */\n\tfor (i = 0; i < max_chan_nums; i++) {\n\t\tchannel = channel_set[i].ChannelNum;\n\t\tfreq = rtw_ch2freq(channel);\n\n\t\tch = ieee80211_get_channel(wiphy, freq);\n\t\tif (!ch)\n\t\t\tcontinue;\n\n\t\tif (channel_set[i].ScanType == SCAN_PASSIVE\n\t\t\t#if defined(CONFIG_DFS_MASTER)\n\t\t\t&& rtw_odm_dfs_domain_unknown(dvobj)\n\t\t\t#endif\n\t\t) {\n\t\t\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))\n\t\t\tch->flags = (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN);\n\t\t\t#else\n\t\t\tch->flags = IEEE80211_CHAN_NO_IR;\n\t\t\t#endif\n\t\t} else\n\t\t\tch->flags = 0;\n\n\t\t#ifdef CONFIG_DFS\n\t\tif (rtw_is_dfs_ch(ch->hw_value)\n\t\t\t#if defined(CONFIG_DFS_MASTER)\n\t\t\t&& rtw_odm_dfs_domain_unknown(dvobj)\n\t\t\t#endif\n\t\t) {\n\t\t\tch->flags |= IEEE80211_CHAN_RADAR;\n\t\t\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))\n\t\t\tch->flags |= (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN);\n\t\t\t#else\n\t\t\tch->flags |= IEEE80211_CHAN_NO_IR;\n\t\t\t#endif\n\t\t}\n\t\t#endif /* CONFIG_DFS */\n\t}\n}\n\nstatic const struct ieee80211_regdomain *_rtw_regdomain_select(struct\n\t\trtw_regulatory\n\t\t*reg)\n{\n#if 0\n\tswitch (reg->country_code) {\n\tcase COUNTRY_CODE_USER:\n\tdefault:\n\t\treturn &rtw_regdom_rd;\n\t}\n#else\n\treturn &rtw_regdom_rd;\n#endif\n}\n\nstatic void rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)\n{\n\tswitch (request->initiator) {\n\tcase NL80211_REGDOM_SET_BY_DRIVER:\n\t\tRTW_INFO(\"%s: %s\\n\", __func__, \"NL80211_REGDOM_SET_BY_DRIVER\");\n\t\tbreak;\n\tcase NL80211_REGDOM_SET_BY_CORE:\n\t\tRTW_INFO(\"%s: %s\\n\", __func__, \"NL80211_REGDOM_SET_BY_CORE\");\n\t\tbreak;\n\tcase NL80211_REGDOM_SET_BY_USER:\n\t\tRTW_INFO(\"%s: %s alpha2:%c%c\\n\", __func__, \"NL80211_REGDOM_SET_BY_USER\"\n\t\t\t, request->alpha2[0], request->alpha2[1]);\n\t\trtw_set_country(wiphy_to_adapter(wiphy), request->alpha2);\n\t\tbreak;\n\tcase NL80211_REGDOM_SET_BY_COUNTRY_IE:\n\t\tRTW_INFO(\"%s: %s\\n\", __func__, \"NL80211_REGDOM_SET_BY_COUNTRY_IE\");\n\t\tbreak;\n\t}\n\n\trtw_regd_apply_flags(wiphy);\n}\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))\nstatic int rtw_reg_notifier_return(struct wiphy *wiphy, struct regulatory_request *request)\n{\n\trtw_reg_notifier(wiphy, request);\n\treturn 0;\n}\n#endif\n\nstatic void _rtw_regd_init_wiphy(struct rtw_regulatory *reg, struct wiphy *wiphy)\n{\n\tconst struct ieee80211_regdomain *regd;\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))\n\twiphy->reg_notifier = rtw_reg_notifier_return;\n#else\n\twiphy->reg_notifier = rtw_reg_notifier;\n#endif\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))\n\twiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY;\n\twiphy->flags &= ~WIPHY_FLAG_STRICT_REGULATORY;\n\twiphy->flags &= ~WIPHY_FLAG_DISABLE_BEACON_HINTS;\n#else\n\twiphy->regulatory_flags |= REGULATORY_CUSTOM_REG;\n\twiphy->regulatory_flags &= ~REGULATORY_STRICT_REG;\n\twiphy->regulatory_flags &= ~REGULATORY_DISABLE_BEACON_HINTS;\n#endif\n\n\tregd = _rtw_regdomain_select(reg);\n\twiphy_apply_custom_regulatory(wiphy, regd);\n\n\trtw_regd_apply_flags(wiphy);\n}\n\nint rtw_regd_init(struct wiphy *wiphy)\n{\n#if 0\n\tif (rtw_regd == NULL) {\n\t\trtw_regd = (struct rtw_regulatory *)\n\t\t\t   rtw_malloc(sizeof(struct rtw_regulatory));\n\n\t\trtw_regd->alpha2[0] = '9';\n\t\trtw_regd->alpha2[1] = '9';\n\n\t\trtw_regd->country_code = COUNTRY_CODE_USER;\n\t}\n\n\tRTW_INFO(\"%s: Country alpha2 being used: %c%c\\n\",\n\t\t __func__, rtw_regd->alpha2[0], rtw_regd->alpha2[1]);\n#endif\n\n\t_rtw_regd_init_wiphy(NULL, wiphy);\n\n\treturn 0;\n}\n#endif /* CONFIG_IOCTL_CFG80211 */\n"
  },
  {
    "path": "os_dep/linux/xmit_linux.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#define _XMIT_OSDEP_C_\n\n#include <drv_types.h>\n\n#define DBG_DUMP_OS_QUEUE_CTL 0\n\nuint rtw_remainder_len(struct pkt_file *pfile)\n{\n\treturn pfile->buf_len - ((SIZE_PTR)(pfile->cur_addr) - (SIZE_PTR)(pfile->buf_start));\n}\n\nvoid _rtw_open_pktfile(_pkt *pktptr, struct pkt_file *pfile)\n{\n\n\tpfile->pkt = pktptr;\n\tpfile->cur_addr = pfile->buf_start = pktptr->data;\n\tpfile->pkt_len = pfile->buf_len = pktptr->len;\n\n\tpfile->cur_buffer = pfile->buf_start ;\n\n}\n\nuint _rtw_pktfile_read(struct pkt_file *pfile, u8 *rmem, uint rlen)\n{\n\tuint\tlen = 0;\n\n\n\tlen =  rtw_remainder_len(pfile);\n\tlen = (rlen > len) ? len : rlen;\n\n\tif (rmem)\n\t\tskb_copy_bits(pfile->pkt, pfile->buf_len - pfile->pkt_len, rmem, len);\n\n\tpfile->cur_addr += len;\n\tpfile->pkt_len -= len;\n\n\n\treturn len;\n}\n\nsint rtw_endofpktfile(struct pkt_file *pfile)\n{\n\n\tif (pfile->pkt_len == 0) {\n\t\treturn _TRUE;\n\t}\n\n\n\treturn _FALSE;\n}\n\nvoid rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib)\n{\n#ifdef CONFIG_TX_CSUM_OFFLOAD\t\n\tstruct sk_buff *skb = (struct sk_buff *)pkt;\n\tstruct iphdr *iph = NULL;\n\tstruct ipv6hdr *i6ph = NULL;\n\tstruct udphdr *uh = NULL;\n\tstruct tcphdr *th = NULL;\n\tu8 \tprotocol = 0xFF;\n\n\tif (skb->protocol == htons(ETH_P_IP)) {\n\t\tiph = (struct iphdr *)skb_network_header(skb);\n\t\tprotocol = iph->protocol;\n\t} else if (skb->protocol == htons(ETH_P_IPV6)) {\n\t\ti6ph = (struct ipv6hdr *)skb_network_header(skb);\n\t\tprotocol = i6ph->nexthdr;\n\t} else\n\t\t{}\n\n\t/*\tHW unable to compute CSUM if header & payload was be encrypted by SW(cause TXDMA error) */\n\tif (pattrib->bswenc == _TRUE) {\n\t\tif (skb->ip_summed == CHECKSUM_PARTIAL)\n\t\t\tskb_checksum_help(skb);\n\t\treturn;\n\t}\n\n\t/*\tFor HW rule, clear ipv4_csum & UDP/TCP_csum if it is UDP/TCP packet\t*/\n\tswitch (protocol) {\n\tcase IPPROTO_UDP:\n\t\tuh = (struct udphdr *)skb_transport_header(skb);\n\t\tuh->check = 0;\n\t\tif (iph)\n\t\t\tiph->check = 0;\n\t\tpattrib->hw_csum = _TRUE;\n\t\tbreak;\n\tcase IPPROTO_TCP:\n\t\tth = (struct tcphdr *)skb_transport_header(skb);\n\t\tth->check = 0;\n\t\tif (iph)\n\t\t\tiph->check = 0;\n\t\tpattrib->hw_csum = _TRUE;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n#endif\n\n}\n\nint rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 alloc_sz, u8 flag)\n{\n\tif (alloc_sz > 0) {\n#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX\n\t\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\t\tstruct usb_device\t*pusbd = pdvobjpriv->pusbdev;\n\n\t\tpxmitbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)alloc_sz, &pxmitbuf->dma_transfer_addr);\n\t\tpxmitbuf->pbuf = pxmitbuf->pallocated_buf;\n\t\tif (pxmitbuf->pallocated_buf == NULL)\n\t\t\treturn _FAIL;\n#else /* CONFIG_USE_USB_BUFFER_ALLOC_TX */\n\n\t\tpxmitbuf->pallocated_buf = rtw_zmalloc(alloc_sz);\n\t\tif (pxmitbuf->pallocated_buf == NULL)\n\t\t\treturn _FAIL;\n\n\t\tpxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ);\n\n#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */\n\t}\n\n\tif (flag) {\n#ifdef CONFIG_USB_HCI\n\t\tint i;\n\t\tfor (i = 0; i < 8; i++) {\n\t\t\tpxmitbuf->pxmit_urb[i] = usb_alloc_urb(0, GFP_KERNEL);\n\t\t\tif (pxmitbuf->pxmit_urb[i] == NULL) {\n\t\t\t\tRTW_INFO(\"pxmitbuf->pxmit_urb[i]==NULL\");\n\t\t\t\treturn _FAIL;\n\t\t\t}\n\t\t}\n#endif\n\t}\n\n\treturn _SUCCESS;\n}\n\nvoid rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 free_sz, u8 flag)\n{\n\tif (flag) {\n#ifdef CONFIG_USB_HCI\n\t\tint i;\n\n\t\tfor (i = 0; i < 8; i++) {\n\t\t\tif (pxmitbuf->pxmit_urb[i]) {\n\t\t\t\t/* usb_kill_urb(pxmitbuf->pxmit_urb[i]); */\n\t\t\t\tusb_free_urb(pxmitbuf->pxmit_urb[i]);\n\t\t\t}\n\t\t}\n#endif\n\t}\n\n\tif (free_sz > 0) {\n#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX\n\t\tstruct dvobj_priv\t*pdvobjpriv = adapter_to_dvobj(padapter);\n\t\tstruct usb_device\t*pusbd = pdvobjpriv->pusbdev;\n\n\t\trtw_usb_buffer_free(pusbd, (size_t)free_sz, pxmitbuf->pallocated_buf, pxmitbuf->dma_transfer_addr);\n\t\tpxmitbuf->pallocated_buf =  NULL;\n\t\tpxmitbuf->dma_transfer_addr = 0;\n#else\t/* CONFIG_USE_USB_BUFFER_ALLOC_TX */\n\t\tif (pxmitbuf->pallocated_buf)\n\t\t\trtw_mfree(pxmitbuf->pallocated_buf, free_sz);\n#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */\n\t}\n}\n\nvoid dump_os_queue(void *sel, _adapter *padapter)\n{\n\tstruct net_device *ndev = padapter->pnetdev;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\tint i;\n\n\tfor (i = 0; i < 4; i++) {\n\t\tRTW_PRINT_SEL(sel, \"os_queue[%d]:%s\\n\"\n\t\t\t, i, __netif_subqueue_stopped(ndev, i) ? \"stopped\" : \"waked\");\n\t}\n#else\n\tRTW_PRINT_SEL(sel, \"os_queue:%s\\n\"\n\t\t      , netif_queue_stopped(ndev) ? \"stopped\" : \"waked\");\n#endif\n}\n\n#define WMM_XMIT_THRESHOLD\t(NR_XMITFRAME*2/5)\n\nstatic inline bool rtw_os_need_wake_queue(_adapter *padapter, u16 qidx)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\n\tif (padapter->registrypriv.wifi_spec) {\n\t\tif (pxmitpriv->hwxmits[qidx].accnt < WMM_XMIT_THRESHOLD)\n\t\t\treturn _TRUE;\n#ifdef DBG_CONFIG_ERROR_DETECT\n#ifdef DBG_CONFIG_ERROR_RESET\n\t} else if (rtw_hal_sreset_inprogress(padapter) == _TRUE) {\n\t\treturn _FALSE;\n#endif/* #ifdef DBG_CONFIG_ERROR_RESET */\n#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */\n\t} else {\n#ifdef CONFIG_MCC_MODE\n\t\tif (MCC_EN(padapter)) {\n\t\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)\n\t\t\t    && MCC_STOP(padapter))\n\t\t\t\treturn _FALSE;\n\t\t}\n#endif /* CONFIG_MCC_MODE */\n\t\treturn _TRUE;\n\t}\n\treturn _FALSE;\n#else\n#ifdef CONFIG_MCC_MODE\n\tif (MCC_EN(padapter)) {\n\t\tif (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)\n\t\t    && MCC_STOP(padapter))\n\t\t\treturn _FALSE;\n\t}\n#endif /* CONFIG_MCC_MODE */\n\treturn _TRUE;\n#endif\n}\n\nstatic inline bool rtw_os_need_stop_queue(_adapter *padapter, u16 qidx)\n{\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\tif (padapter->registrypriv.wifi_spec) {\n\t\t/* No free space for Tx, tx_worker is too slow */\n\t\tif (pxmitpriv->hwxmits[qidx].accnt > WMM_XMIT_THRESHOLD)\n\t\t\treturn _TRUE;\n\t} else {\n\t\tif (pxmitpriv->free_xmitframe_cnt <= 4)\n\t\t\treturn _TRUE;\n\t}\n#else\n\tif (pxmitpriv->free_xmitframe_cnt <= 4)\n\t\treturn _TRUE;\n#endif\n\treturn _FALSE;\n}\n\nvoid rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\tu16\tqidx;\n\n\tqidx = skb_get_queue_mapping(pkt);\n\tif (rtw_os_need_wake_queue(padapter, qidx)) {\n\t\tif (DBG_DUMP_OS_QUEUE_CTL)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\": netif_wake_subqueue[%d]\\n\", FUNC_ADPT_ARG(padapter), qidx);\n\t\tnetif_wake_subqueue(padapter->pnetdev, qidx);\n\t}\n#else\n\tif (rtw_os_need_wake_queue(padapter, 0)) {\n\t\tif (DBG_DUMP_OS_QUEUE_CTL)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\": netif_wake_queue\\n\", FUNC_ADPT_ARG(padapter));\n\t\tnetif_wake_queue(padapter->pnetdev);\n\t}\n#endif\n\n\trtw_skb_free(pkt);\n}\n\nvoid rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe)\n{\n\tif (pxframe->pkt)\n\t\trtw_os_pkt_complete(padapter, pxframe->pkt);\n\n\tpxframe->pkt = NULL;\n}\n\nvoid rtw_os_xmit_schedule(_adapter *padapter)\n{\n#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)\n\t_adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter);\n\n\tif (!padapter)\n\t\treturn;\n\n\tif (_rtw_queue_empty(&padapter->xmitpriv.pending_xmitbuf_queue) == _FALSE)\n\t\t_rtw_up_sema(&pri_adapter->xmitpriv.xmit_sema);\n\n\n#else\n\t_irqL  irqL;\n\tstruct xmit_priv *pxmitpriv;\n\n\tif (!padapter)\n\t\treturn;\n\n\tpxmitpriv = &padapter->xmitpriv;\n\n\t_enter_critical_bh(&pxmitpriv->lock, &irqL);\n\n\tif (rtw_txframes_pending(padapter))\n\t\ttasklet_hi_schedule(&pxmitpriv->xmit_tasklet);\n\n\t_exit_critical_bh(&pxmitpriv->lock, &irqL);\n\t\n#if defined(CONFIG_PCI_HCI) && defined(CONFIG_XMIT_THREAD_MODE)\n\tif (_rtw_queue_empty(&padapter->xmitpriv.pending_xmitbuf_queue) == _FALSE)\n\t\t_rtw_up_sema(&padapter->xmitpriv.xmit_sema);\n#endif\n\t\n\n#endif\n}\n\nstatic bool rtw_check_xmit_resource(_adapter *padapter, _pkt *pkt)\n{\n\tbool busy = _FALSE;\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\tu16\tqidx;\n\n\tqidx = skb_get_queue_mapping(pkt);\n\tif (rtw_os_need_stop_queue(padapter, qidx)) {\n\t\tif (DBG_DUMP_OS_QUEUE_CTL)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\": netif_stop_subqueue[%d]\\n\", FUNC_ADPT_ARG(padapter), qidx);\n\t\tnetif_stop_subqueue(padapter->pnetdev, qidx);\n\t\tbusy = _TRUE;\n\t}\n#else\n\tif (rtw_os_need_stop_queue(padapter, 0)) {\n\t\tif (DBG_DUMP_OS_QUEUE_CTL)\n\t\t\tRTW_INFO(FUNC_ADPT_FMT\": netif_stop_queue\\n\", FUNC_ADPT_ARG(padapter));\n\t\trtw_netif_stop_queue(padapter->pnetdev);\n\t\tbusy = _TRUE;\n\t}\n#endif\n\treturn busy;\n}\n\nvoid rtw_os_wake_queue_at_free_stainfo(_adapter *padapter, int *qcnt_freed)\n{\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\tint i;\n\n\tfor (i = 0; i < 4; i++) {\n\t\tif (qcnt_freed[i] == 0)\n\t\t\tcontinue;\n\n\t\tif (rtw_os_need_wake_queue(padapter, i)) {\n\t\t\tif (DBG_DUMP_OS_QUEUE_CTL)\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\": netif_wake_subqueue[%d]\\n\", FUNC_ADPT_ARG(padapter), i);\n\t\t\tnetif_wake_subqueue(padapter->pnetdev, i);\n\t\t}\n\t}\n#else\n\tif (qcnt_freed[0] || qcnt_freed[1] || qcnt_freed[2] || qcnt_freed[3]) {\n\t\tif (rtw_os_need_wake_queue(padapter, 0)) {\n\t\t\tif (DBG_DUMP_OS_QUEUE_CTL)\n\t\t\t\tRTW_INFO(FUNC_ADPT_FMT\": netif_wake_queue\\n\", FUNC_ADPT_ARG(padapter));\n\t\t\tnetif_wake_queue(padapter->pnetdev);\n\t\t}\n\t}\n#endif\n}\n\n#ifdef CONFIG_TX_MCAST2UNI\nint rtw_mlcst2unicst(_adapter *padapter, struct sk_buff *skb)\n{\n\tstruct\tsta_priv *pstapriv = &padapter->stapriv;\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n\t_irqL\tirqL;\n\t_list\t*phead, *plist;\n\tstruct sk_buff *newskb;\n\tstruct sta_info *psta = NULL;\n\tu8 chk_alive_num = 0;\n\tchar chk_alive_list[NUM_STA];\n\tu8 bc_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n\tu8 null_addr[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};\n\n\tint i;\n\ts32\tres;\n\n\tDBG_COUNTER(padapter->tx_logs.os_tx_m2u);\n\n\t_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\tphead = &pstapriv->asoc_list;\n\tplist = get_next(phead);\n\n\t/* free sta asoc_queue */\n\twhile ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {\n\t\tint stainfo_offset;\n\t\tpsta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);\n\t\tplist = get_next(plist);\n\n\t\tstainfo_offset = rtw_stainfo_offset(pstapriv, psta);\n\t\tif (stainfo_offset_valid(stainfo_offset))\n\t\t\tchk_alive_list[chk_alive_num++] = stainfo_offset;\n\t}\n\t_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\n\n\tfor (i = 0; i < chk_alive_num; i++) {\n\t\tpsta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]);\n\t\tif (!(psta->state & _FW_LINKED)) {\n\t\t\tDBG_COUNTER(padapter->tx_logs.os_tx_m2u_ignore_fw_linked);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* avoid come from STA1 and send back STA1 */\n\t\tif (_rtw_memcmp(psta->cmn.mac_addr, &skb->data[6], ETH_ALEN) == _TRUE\n\t\t\t|| _rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) == _TRUE\n\t\t\t|| _rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) == _TRUE\n\t\t) {\n\t\t\tDBG_COUNTER(padapter->tx_logs.os_tx_m2u_ignore_self);\n\t\t\tcontinue;\n\t\t}\n\n\t\tDBG_COUNTER(padapter->tx_logs.os_tx_m2u_entry);\n\n\t\tnewskb = rtw_skb_copy(skb);\n\n\t\tif (newskb) {\n\t\t\t_rtw_memcpy(newskb->data, psta->cmn.mac_addr, ETH_ALEN);\n\t\t\tres = rtw_xmit(padapter, &newskb);\n\t\t\tif (res < 0) {\n\t\t\t\tDBG_COUNTER(padapter->tx_logs.os_tx_m2u_entry_err_xmit);\n\t\t\t\tRTW_INFO(\"%s()-%d: rtw_xmit() return error! res=%d\\n\", __FUNCTION__, __LINE__, res);\n\t\t\t\tpxmitpriv->tx_drop++;\n\t\t\t\trtw_skb_free(newskb);\n\t\t\t}\n\t\t} else {\n\t\t\tDBG_COUNTER(padapter->tx_logs.os_tx_m2u_entry_err_skb);\n\t\t\tRTW_INFO(\"%s-%d: rtw_skb_copy() failed!\\n\", __FUNCTION__, __LINE__);\n\t\t\tpxmitpriv->tx_drop++;\n\t\t\t/* rtw_skb_free(skb); */\n\t\t\treturn _FALSE;\t/* Caller shall tx this multicast frame via normal way. */\n\t\t}\n\t}\n\n\trtw_skb_free(skb);\n\treturn _TRUE;\n}\n#endif /* CONFIG_TX_MCAST2UNI */\n\n\nint _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);\n\tstruct xmit_priv *pxmitpriv = &padapter->xmitpriv;\n#ifdef CONFIG_TX_MCAST2UNI\n\textern int rtw_mc2u_disable;\n#endif /* CONFIG_TX_MCAST2UNI\t */\n#ifdef CONFIG_TX_CSUM_OFFLOAD\t\n\tstruct sk_buff *skb = pkt;\n\tstruct sk_buff *segs, *nskb;\n\tnetdev_features_t features = padapter->pnetdev->features;\n#endif\n\ts32 res = 0;\n\n\tif (padapter->registrypriv.mp_mode) {\n\t\tRTW_INFO(\"MP_TX_DROP_OS_FRAME\\n\");\n\t\tgoto drop_packet;\n\t}\n\tDBG_COUNTER(padapter->tx_logs.os_tx);\n\n\tif (rtw_if_up(padapter) == _FALSE) {\n\t\tDBG_COUNTER(padapter->tx_logs.os_tx_err_up);\n\t\t#ifdef DBG_TX_DROP_FRAME\n\t\tRTW_INFO(\"DBG_TX_DROP_FRAME %s if_up fail\\n\", __FUNCTION__);\n\t\t#endif\n\t\tgoto drop_packet;\n\t}\n\n\trtw_check_xmit_resource(padapter, pkt);\n\n#ifdef CONFIG_TX_MCAST2UNI\n\tif (!rtw_mc2u_disable\n\t\t&& MLME_IS_AP(padapter)\n\t\t&& (IP_MCAST_MAC(pkt->data)\n\t\t\t|| ICMPV6_MCAST_MAC(pkt->data)\n\t\t\t#ifdef CONFIG_TX_BCAST2UNI\n\t\t\t|| is_broadcast_mac_addr(pkt->data)\n\t\t\t#endif\n\t\t\t)\n\t\t&& (padapter->registrypriv.wifi_spec == 0)\n\t) {\n\t\tif (pxmitpriv->free_xmitframe_cnt > (NR_XMITFRAME / 4)) {\n\t\t\tres = rtw_mlcst2unicst(padapter, pkt);\n\t\t\tif (res == _TRUE)\n\t\t\t\tgoto exit;\n\t\t} else {\n\t\t\t/* RTW_INFO(\"Stop M2U(%d, %d)! \", pxmitpriv->free_xmitframe_cnt, pxmitpriv->free_xmitbuf_cnt); */\n\t\t\t/* RTW_INFO(\"!m2u ); */\n\t\t\tDBG_COUNTER(padapter->tx_logs.os_tx_m2u_stop);\n\t\t}\n\t}\n#endif /* CONFIG_TX_MCAST2UNI\t */\n\n#ifdef CONFIG_TX_CSUM_OFFLOAD\n\tif (skb_shinfo(skb)->gso_size) {\n\t/*\tsplit a big(65k) skb into several small(1.5k) skbs */\n\t\tfeatures &= ~(NETIF_F_TSO | NETIF_F_TSO6);\n\t\tsegs = skb_gso_segment(skb, features);\n\t\tif (IS_ERR(segs) || !segs)\n\t\t\tgoto drop_packet;\n\n\t\tdo {\n\t\t\tnskb = segs;\n\t\t\tsegs = segs->next;\n\t\t\tnskb->next = NULL;\n\t\t\trtw_mstat_update( MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, nskb->truesize);\n\t\t\tres = rtw_xmit(padapter, &nskb);\n\t\t\tif (res < 0) {\n\t\t\t\t#ifdef DBG_TX_DROP_FRAME\n\t\t\t\tRTW_INFO(\"DBG_TX_DROP_FRAME %s rtw_xmit fail\\n\", __FUNCTION__);\n\t\t\t\t#endif\n\t\t\t\tpxmitpriv->tx_drop++;\n\t\t\t\trtw_os_pkt_complete(padapter, nskb);\n\t\t\t}\n\t\t} while (segs);\n\t\trtw_os_pkt_complete(padapter, skb);\n\t\tgoto exit;\n\t}\n#endif\n\n\tres = rtw_xmit(padapter, &pkt);\n\tif (res < 0) {\n\t\t#ifdef DBG_TX_DROP_FRAME\n\t\tRTW_INFO(\"DBG_TX_DROP_FRAME %s rtw_xmit fail\\n\", __FUNCTION__);\n\t\t#endif\n\t\tgoto drop_packet;\n\t}\n\n\tgoto exit;\n\ndrop_packet:\n\tpxmitpriv->tx_drop++;\n\trtw_os_pkt_complete(padapter, pkt);\n\nexit:\n\n\n\treturn 0;\n}\n\nint rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev)\n{\n\t_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);\n\tstruct\tmlme_priv\t*pmlmepriv = &(padapter->mlmepriv);\n\tint ret = 0;\n\n\tif (pkt) {\n\t\tif (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) {\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))\n\t\t\trtw_monitor_xmit_entry((struct sk_buff *)pkt, pnetdev);\n#endif\n\t\t}\n\t\telse {\n\t\t\trtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, pkt->truesize);\n\t\t\tret = _rtw_xmit_entry(pkt, pnetdev);\n\t\t}\n\n\t}\n\n\treturn ret;\n}\n"
  },
  {
    "path": "os_dep/osdep_service.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2007 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n\n#define _OSDEP_SERVICE_C_\n\n#include <drv_types.h>\n\n#define RT_TAG\t'1178'\n\n#ifdef DBG_MEMORY_LEAK\n#ifdef PLATFORM_LINUX\natomic_t _malloc_cnt = ATOMIC_INIT(0);\natomic_t _malloc_size = ATOMIC_INIT(0);\n#endif\n#endif /* DBG_MEMORY_LEAK */\n\n\n#if defined(PLATFORM_LINUX)\n/*\n* Translate the OS dependent @param error_code to OS independent RTW_STATUS_CODE\n* @return: one of RTW_STATUS_CODE\n*/\ninline int RTW_STATUS_CODE(int error_code)\n{\n\tif (error_code >= 0)\n\t\treturn _SUCCESS;\n\n\tswitch (error_code) {\n\t/* case -ETIMEDOUT: */\n\t/*\treturn RTW_STATUS_TIMEDOUT; */\n\tdefault:\n\t\treturn _FAIL;\n\t}\n}\n#else\ninline int RTW_STATUS_CODE(int error_code)\n{\n\treturn error_code;\n}\n#endif\n\nu32 rtw_atoi(u8 *s)\n{\n\n\tint num = 0, flag = 0;\n\tint i;\n\tfor (i = 0; i <= strlen(s); i++) {\n\t\tif (s[i] >= '0' && s[i] <= '9')\n\t\t\tnum = num * 10 + s[i] - '0';\n\t\telse if (s[0] == '-' && i == 0)\n\t\t\tflag = 1;\n\t\telse\n\t\t\tbreak;\n\t}\n\n\tif (flag == 1)\n\t\tnum = num * -1;\n\n\treturn num;\n\n}\n\ninline void *_rtw_vmalloc(u32 sz)\n{\n\tvoid *pbuf;\n#ifdef PLATFORM_LINUX\n\tpbuf = vmalloc(sz);\n#endif\n#ifdef PLATFORM_FREEBSD\n\tpbuf = malloc(sz, M_DEVBUF, M_NOWAIT);\n#endif\n\n#ifdef PLATFORM_WINDOWS\n\tNdisAllocateMemoryWithTag(&pbuf, sz, RT_TAG);\n#endif\n\n#ifdef DBG_MEMORY_LEAK\n#ifdef PLATFORM_LINUX\n\tif (pbuf != NULL) {\n\t\tatomic_inc(&_malloc_cnt);\n\t\tatomic_add(sz, &_malloc_size);\n\t}\n#endif\n#endif /* DBG_MEMORY_LEAK */\n\n\treturn pbuf;\n}\n\ninline void *_rtw_zvmalloc(u32 sz)\n{\n\tvoid *pbuf;\n#ifdef PLATFORM_LINUX\n\tpbuf = _rtw_vmalloc(sz);\n\tif (pbuf != NULL)\n\t\tmemset(pbuf, 0, sz);\n#endif\n#ifdef PLATFORM_FREEBSD\n\tpbuf = malloc(sz, M_DEVBUF, M_ZERO | M_NOWAIT);\n#endif\n#ifdef PLATFORM_WINDOWS\n\tNdisAllocateMemoryWithTag(&pbuf, sz, RT_TAG);\n\tif (pbuf != NULL)\n\t\tNdisFillMemory(pbuf, sz, 0);\n#endif\n\n\treturn pbuf;\n}\n\ninline void _rtw_vmfree(void *pbuf, u32 sz)\n{\n#ifdef PLATFORM_LINUX\n\tvfree(pbuf);\n#endif\n#ifdef PLATFORM_FREEBSD\n\tfree(pbuf, M_DEVBUF);\n#endif\n#ifdef PLATFORM_WINDOWS\n\tNdisFreeMemory(pbuf, sz, 0);\n#endif\n\n#ifdef DBG_MEMORY_LEAK\n#ifdef PLATFORM_LINUX\n\tatomic_dec(&_malloc_cnt);\n\tatomic_sub(sz, &_malloc_size);\n#endif\n#endif /* DBG_MEMORY_LEAK */\n}\n\nvoid *_rtw_malloc(u32 sz)\n{\n\tvoid *pbuf = NULL;\n\n#ifdef PLATFORM_LINUX\n#ifdef RTK_DMP_PLATFORM\n\tif (sz > 0x4000)\n\t\tpbuf = dvr_malloc(sz);\n\telse\n#endif\n\t\tpbuf = kmalloc(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);\n\n#endif\n#ifdef PLATFORM_FREEBSD\n\tpbuf = malloc(sz, M_DEVBUF, M_NOWAIT);\n#endif\n#ifdef PLATFORM_WINDOWS\n\n\tNdisAllocateMemoryWithTag(&pbuf, sz, RT_TAG);\n\n#endif\n\n#ifdef DBG_MEMORY_LEAK\n#ifdef PLATFORM_LINUX\n\tif (pbuf != NULL) {\n\t\tatomic_inc(&_malloc_cnt);\n\t\tatomic_add(sz, &_malloc_size);\n\t}\n#endif\n#endif /* DBG_MEMORY_LEAK */\n\n\treturn pbuf;\n\n}\n\n\nvoid *_rtw_zmalloc(u32 sz)\n{\n#ifdef PLATFORM_FREEBSD\n\treturn malloc(sz, M_DEVBUF, M_ZERO | M_NOWAIT);\n#else /* PLATFORM_FREEBSD */\n\tvoid *pbuf = _rtw_malloc(sz);\n\n\tif (pbuf != NULL) {\n\n#ifdef PLATFORM_LINUX\n\t\tmemset(pbuf, 0, sz);\n#endif\n\n#ifdef PLATFORM_WINDOWS\n\t\tNdisFillMemory(pbuf, sz, 0);\n#endif\n\n\t}\n\n\treturn pbuf;\n#endif /* PLATFORM_FREEBSD */\n}\n\nvoid _rtw_mfree(void *pbuf, u32 sz)\n{\n\n#ifdef PLATFORM_LINUX\n#ifdef RTK_DMP_PLATFORM\n\tif (sz > 0x4000)\n\t\tdvr_free(pbuf);\n\telse\n#endif\n\t\tkfree(pbuf);\n\n#endif\n#ifdef PLATFORM_FREEBSD\n\tfree(pbuf, M_DEVBUF);\n#endif\n#ifdef PLATFORM_WINDOWS\n\n\tNdisFreeMemory(pbuf, sz, 0);\n\n#endif\n\n#ifdef DBG_MEMORY_LEAK\n#ifdef PLATFORM_LINUX\n\tatomic_dec(&_malloc_cnt);\n\tatomic_sub(sz, &_malloc_size);\n#endif\n#endif /* DBG_MEMORY_LEAK */\n\n}\n\n#ifdef PLATFORM_FREEBSD\n/* review again */\nstruct sk_buff *dev_alloc_skb(unsigned int size)\n{\n\tstruct sk_buff *skb = NULL;\n\tu8 *data = NULL;\n\n\t/* skb = _rtw_zmalloc(sizeof(struct sk_buff)); */ /* for skb->len, etc. */\n\tskb = _rtw_malloc(sizeof(struct sk_buff));\n\tif (!skb)\n\t\tgoto out;\n\tdata = _rtw_malloc(size);\n\tif (!data)\n\t\tgoto nodata;\n\n\tskb->head = (unsigned char *)data;\n\tskb->data = (unsigned char *)data;\n\tskb->tail = (unsigned char *)data;\n\tskb->end = (unsigned char *)data + size;\n\tskb->len = 0;\n\t/* printf(\"%s()-%d: skb=%p, skb->head = %p\\n\", __FUNCTION__, __LINE__, skb, skb->head); */\n\nout:\n\treturn skb;\nnodata:\n\t_rtw_mfree(skb, sizeof(struct sk_buff));\n\tskb = NULL;\n\tgoto out;\n\n}\n\nvoid dev_kfree_skb_any(struct sk_buff *skb)\n{\n\t/* printf(\"%s()-%d: skb->head = %p\\n\", __FUNCTION__, __LINE__, skb->head); */\n\tif (skb->head)\n\t\t_rtw_mfree(skb->head, 0);\n\t/* printf(\"%s()-%d: skb = %p\\n\", __FUNCTION__, __LINE__, skb); */\n\tif (skb)\n\t\t_rtw_mfree(skb, 0);\n}\nstruct sk_buff *skb_clone(const struct sk_buff *skb)\n{\n\treturn NULL;\n}\n\n#endif /* PLATFORM_FREEBSD */\n\ninline struct sk_buff *_rtw_skb_alloc(u32 sz)\n{\n#ifdef PLATFORM_LINUX\n\treturn __dev_alloc_skb(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);\n#endif /* PLATFORM_LINUX */\n\n#ifdef PLATFORM_FREEBSD\n\treturn dev_alloc_skb(sz);\n#endif /* PLATFORM_FREEBSD */\n}\n\ninline void _rtw_skb_free(struct sk_buff *skb)\n{\n\tdev_kfree_skb_any(skb);\n}\n\ninline struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb)\n{\n#ifdef PLATFORM_LINUX\n\treturn skb_copy(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);\n#endif /* PLATFORM_LINUX */\n\n#ifdef PLATFORM_FREEBSD\n\treturn NULL;\n#endif /* PLATFORM_FREEBSD */\n}\n\ninline struct sk_buff *_rtw_skb_clone(struct sk_buff *skb)\n{\n#ifdef PLATFORM_LINUX\n\treturn skb_clone(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);\n#endif /* PLATFORM_LINUX */\n\n#ifdef PLATFORM_FREEBSD\n\treturn skb_clone(skb);\n#endif /* PLATFORM_FREEBSD */\n}\ninline struct sk_buff *_rtw_pskb_copy(struct sk_buff *skb)\n{\n#ifdef PLATFORM_LINUX\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))\n\treturn pskb_copy(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);\n#else\n\treturn skb_clone(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);\n#endif\n#endif /* PLATFORM_LINUX */\n\n#ifdef PLATFORM_FREEBSD\n\treturn NULL;\n#endif /* PLATFORM_FREEBSD */\n}\n\ninline int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb)\n{\n#if defined(PLATFORM_LINUX)\n\tskb->dev = ndev;\n\treturn netif_rx(skb);\n#elif defined(PLATFORM_FREEBSD)\n\treturn (*ndev->if_input)(ndev, skb);\n#else\n\trtw_warn_on(1);\n\treturn -1;\n#endif\n}\n\n#ifdef CONFIG_RTW_NAPI\ninline int _rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb)\n{\n#if defined(PLATFORM_LINUX)\n\tskb->dev = ndev;\n\treturn netif_receive_skb(skb);\n#else\n\trtw_warn_on(1);\n\treturn -1;\n#endif\n}\n\n#ifdef CONFIG_RTW_GRO\ninline gro_result_t _rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb)\n{\n#if defined(PLATFORM_LINUX)\n\treturn napi_gro_receive(napi, skb);\n#else\n\trtw_warn_on(1);\n\treturn -1;\n#endif\n}\n#endif /* CONFIG_RTW_GRO */\n#endif /* CONFIG_RTW_NAPI */\n\nvoid _rtw_skb_queue_purge(struct sk_buff_head *list)\n{\n\tstruct sk_buff *skb;\n\n\twhile ((skb = skb_dequeue(list)) != NULL)\n\t\t_rtw_skb_free(skb);\n}\n\n#ifdef CONFIG_USB_HCI\ninline void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma)\n{\n#ifdef PLATFORM_LINUX\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\treturn usb_alloc_coherent(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma);\n#else\n\treturn usb_buffer_alloc(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma);\n#endif\n#endif /* PLATFORM_LINUX */\n\n#ifdef PLATFORM_FREEBSD\n\treturn malloc(size, M_USBDEV, M_NOWAIT | M_ZERO);\n#endif /* PLATFORM_FREEBSD */\n}\ninline void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma)\n{\n#ifdef PLATFORM_LINUX\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\tusb_free_coherent(dev, size, addr, dma);\n#else\n\tusb_buffer_free(dev, size, addr, dma);\n#endif\n#endif /* PLATFORM_LINUX */\n\n#ifdef PLATFORM_FREEBSD\n\tfree(addr, M_USBDEV);\n#endif /* PLATFORM_FREEBSD */\n}\n#endif /* CONFIG_USB_HCI */\n\n#if defined(DBG_MEM_ALLOC)\n\nstruct rtw_mem_stat {\n\tATOMIC_T alloc; /* the memory bytes we allocate currently */\n\tATOMIC_T peak; /* the peak memory bytes we allocate */\n\tATOMIC_T alloc_cnt; /* the alloc count for alloc currently */\n\tATOMIC_T alloc_err_cnt; /* the error times we fail to allocate memory */\n};\n\nstruct rtw_mem_stat rtw_mem_type_stat[mstat_tf_idx(MSTAT_TYPE_MAX)];\n#ifdef RTW_MEM_FUNC_STAT\nstruct rtw_mem_stat rtw_mem_func_stat[mstat_ff_idx(MSTAT_FUNC_MAX)];\n#endif\n\nchar *MSTAT_TYPE_str[] = {\n\t\"VIR\",\n\t\"PHY\",\n\t\"SKB\",\n\t\"USB\",\n};\n\n#ifdef RTW_MEM_FUNC_STAT\nchar *MSTAT_FUNC_str[] = {\n\t\"UNSP\",\n\t\"IO\",\n\t\"TXIO\",\n\t\"RXIO\",\n\t\"TX\",\n\t\"RX\",\n};\n#endif\n\nvoid rtw_mstat_dump(void *sel)\n{\n\tint i;\n\tint value_t[4][mstat_tf_idx(MSTAT_TYPE_MAX)];\n#ifdef RTW_MEM_FUNC_STAT\n\tint value_f[4][mstat_ff_idx(MSTAT_FUNC_MAX)];\n#endif\n\n\tint vir_alloc, vir_peak, vir_alloc_err, phy_alloc, phy_peak, phy_alloc_err;\n\tint tx_alloc, tx_peak, tx_alloc_err, rx_alloc, rx_peak, rx_alloc_err;\n\n\tfor (i = 0; i < mstat_tf_idx(MSTAT_TYPE_MAX); i++) {\n\t\tvalue_t[0][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc));\n\t\tvalue_t[1][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].peak));\n\t\tvalue_t[2][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc_cnt));\n\t\tvalue_t[3][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc_err_cnt));\n\t}\n\n#ifdef RTW_MEM_FUNC_STAT\n\tfor (i = 0; i < mstat_ff_idx(MSTAT_FUNC_MAX); i++) {\n\t\tvalue_f[0][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc));\n\t\tvalue_f[1][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].peak));\n\t\tvalue_f[2][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc_cnt));\n\t\tvalue_f[3][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc_err_cnt));\n\t}\n#endif\n\n\tRTW_PRINT_SEL(sel, \"===================== MSTAT =====================\\n\");\n\tRTW_PRINT_SEL(sel, \"%4s %10s %10s %10s %10s\\n\", \"TAG\", \"alloc\", \"peak\", \"aloc_cnt\", \"err_cnt\");\n\tRTW_PRINT_SEL(sel, \"-------------------------------------------------\\n\");\n\tfor (i = 0; i < mstat_tf_idx(MSTAT_TYPE_MAX); i++)\n\t\tRTW_PRINT_SEL(sel, \"%4s %10d %10d %10d %10d\\n\", MSTAT_TYPE_str[i], value_t[0][i], value_t[1][i], value_t[2][i], value_t[3][i]);\n#ifdef RTW_MEM_FUNC_STAT\n\tRTW_PRINT_SEL(sel, \"-------------------------------------------------\\n\");\n\tfor (i = 0; i < mstat_ff_idx(MSTAT_FUNC_MAX); i++)\n\t\tRTW_PRINT_SEL(sel, \"%4s %10d %10d %10d %10d\\n\", MSTAT_FUNC_str[i], value_f[0][i], value_f[1][i], value_f[2][i], value_f[3][i]);\n#endif\n}\n\nvoid rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz)\n{\n\tstatic systime update_time = 0;\n\tint peak, alloc;\n\tint i;\n\n\t/* initialization */\n\tif (!update_time) {\n\t\tfor (i = 0; i < mstat_tf_idx(MSTAT_TYPE_MAX); i++) {\n\t\t\tATOMIC_SET(&(rtw_mem_type_stat[i].alloc), 0);\n\t\t\tATOMIC_SET(&(rtw_mem_type_stat[i].peak), 0);\n\t\t\tATOMIC_SET(&(rtw_mem_type_stat[i].alloc_cnt), 0);\n\t\t\tATOMIC_SET(&(rtw_mem_type_stat[i].alloc_err_cnt), 0);\n\t\t}\n\t\t#ifdef RTW_MEM_FUNC_STAT\n\t\tfor (i = 0; i < mstat_ff_idx(MSTAT_FUNC_MAX); i++) {\n\t\t\tATOMIC_SET(&(rtw_mem_func_stat[i].alloc), 0);\n\t\t\tATOMIC_SET(&(rtw_mem_func_stat[i].peak), 0);\n\t\t\tATOMIC_SET(&(rtw_mem_func_stat[i].alloc_cnt), 0);\n\t\t\tATOMIC_SET(&(rtw_mem_func_stat[i].alloc_err_cnt), 0);\n\t\t}\n\t\t#endif\n\t}\n\n\tswitch (status) {\n\tcase MSTAT_ALLOC_SUCCESS:\n\t\tATOMIC_INC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_cnt));\n\t\talloc = ATOMIC_ADD_RETURN(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc), sz);\n\t\tpeak = ATOMIC_READ(&(rtw_mem_type_stat[mstat_tf_idx(flags)].peak));\n\t\tif (peak < alloc)\n\t\t\tATOMIC_SET(&(rtw_mem_type_stat[mstat_tf_idx(flags)].peak), alloc);\n\n\t\t#ifdef RTW_MEM_FUNC_STAT\n\t\tATOMIC_INC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_cnt));\n\t\talloc = ATOMIC_ADD_RETURN(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc), sz);\n\t\tpeak = ATOMIC_READ(&(rtw_mem_func_stat[mstat_ff_idx(flags)].peak));\n\t\tif (peak < alloc)\n\t\t\tATOMIC_SET(&(rtw_mem_func_stat[mstat_ff_idx(flags)].peak), alloc);\n\t\t#endif\n\t\tbreak;\n\n\tcase MSTAT_ALLOC_FAIL:\n\t\tATOMIC_INC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_err_cnt));\n\t\t#ifdef RTW_MEM_FUNC_STAT\n\t\tATOMIC_INC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_err_cnt));\n\t\t#endif\n\t\tbreak;\n\n\tcase MSTAT_FREE:\n\t\tATOMIC_DEC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_cnt));\n\t\tATOMIC_SUB(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc), sz);\n\t\t#ifdef RTW_MEM_FUNC_STAT\n\t\tATOMIC_DEC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_cnt));\n\t\tATOMIC_SUB(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc), sz);\n\t\t#endif\n\t\tbreak;\n\t};\n\n\t/* if (rtw_get_passing_time_ms(update_time) > 5000) { */\n\t/*\trtw_mstat_dump(RTW_DBGDUMP); */\n\tupdate_time = rtw_get_current_time();\n\t/* } */\n}\n\n#ifndef SIZE_MAX\n\t#define SIZE_MAX (~(size_t)0)\n#endif\n\nstruct mstat_sniff_rule {\n\tenum mstat_f flags;\n\tsize_t lb;\n\tsize_t hb;\n};\n\nstruct mstat_sniff_rule mstat_sniff_rules[] = {\n\t{MSTAT_TYPE_PHY, 4097, SIZE_MAX},\n};\n\nint mstat_sniff_rule_num = sizeof(mstat_sniff_rules) / sizeof(struct mstat_sniff_rule);\n\nbool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size)\n{\n\tint i;\n\tfor (i = 0; i < mstat_sniff_rule_num; i++) {\n\t\tif (mstat_sniff_rules[i].flags == flags\n\t\t\t&& mstat_sniff_rules[i].lb <= size\n\t\t\t&& mstat_sniff_rules[i].hb >= size)\n\t\t\treturn _TRUE;\n\t}\n\n\treturn _FALSE;\n}\n\ninline void *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)\n{\n\tvoid *p;\n\n\tif (match_mstat_sniff_rules(flags, sz))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s(%d)\\n\", func, line, __FUNCTION__, (sz));\n\n\tp = _rtw_vmalloc((sz));\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL\n\t\t, sz\n\t);\n\n\treturn p;\n}\n\ninline void *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)\n{\n\tvoid *p;\n\n\tif (match_mstat_sniff_rules(flags, sz))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s(%d)\\n\", func, line, __FUNCTION__, (sz));\n\n\tp = _rtw_zvmalloc((sz));\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL\n\t\t, sz\n\t);\n\n\treturn p;\n}\n\ninline void dbg_rtw_vmfree(void *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line)\n{\n\n\tif (match_mstat_sniff_rules(flags, sz))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s(%d)\\n\", func, line, __FUNCTION__, (sz));\n\n\t_rtw_vmfree((pbuf), (sz));\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, MSTAT_FREE\n\t\t, sz\n\t);\n}\n\ninline void *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line)\n{\n\tvoid *p;\n\n\tif (match_mstat_sniff_rules(flags, sz))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s(%d)\\n\", func, line, __FUNCTION__, (sz));\n\n\tp = _rtw_malloc((sz));\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL\n\t\t, sz\n\t);\n\n\treturn p;\n}\n\ninline void *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)\n{\n\tvoid *p;\n\n\tif (match_mstat_sniff_rules(flags, sz))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s(%d)\\n\", func, line, __FUNCTION__, (sz));\n\n\tp = _rtw_zmalloc((sz));\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL\n\t\t, sz\n\t);\n\n\treturn p;\n}\n\ninline void dbg_rtw_mfree(void *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line)\n{\n\tif (match_mstat_sniff_rules(flags, sz))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s(%d)\\n\", func, line, __FUNCTION__, (sz));\n\n\t_rtw_mfree((pbuf), (sz));\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, MSTAT_FREE\n\t\t, sz\n\t);\n}\n\ninline struct sk_buff *dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, int line)\n{\n\tstruct sk_buff *skb;\n\tunsigned int truesize = 0;\n\n\tskb = _rtw_skb_alloc(size);\n\n\tif (skb)\n\t\ttruesize = skb->truesize;\n\n\tif (!skb || truesize < size || match_mstat_sniff_rules(flags, truesize))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\\n\", func, line, __FUNCTION__, size, skb, truesize);\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL\n\t\t, truesize\n\t);\n\n\treturn skb;\n}\n\ninline void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)\n{\n\tunsigned int truesize = skb->truesize;\n\n\tif (match_mstat_sniff_rules(flags, truesize))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s, truesize=%u\\n\", func, line, __FUNCTION__, truesize);\n\n\t_rtw_skb_free(skb);\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, MSTAT_FREE\n\t\t, truesize\n\t);\n}\n\ninline struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line)\n{\n\tstruct sk_buff *skb_cp;\n\tunsigned int truesize = skb->truesize;\n\tunsigned int cp_truesize = 0;\n\n\tskb_cp = _rtw_skb_copy(skb);\n\tif (skb_cp)\n\t\tcp_truesize = skb_cp->truesize;\n\n\tif (!skb_cp || cp_truesize < truesize || match_mstat_sniff_rules(flags, cp_truesize))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s(%u), skb_cp:%p, cp_truesize=%u\\n\", func, line, __FUNCTION__, truesize, skb_cp, cp_truesize);\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, skb_cp ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL\n\t\t, cp_truesize\n\t);\n\n\treturn skb_cp;\n}\n\ninline struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line)\n{\n\tstruct sk_buff *skb_cl;\n\tunsigned int truesize = skb->truesize;\n\tunsigned int cl_truesize = 0;\n\n\tskb_cl = _rtw_skb_clone(skb);\n\tif (skb_cl)\n\t\tcl_truesize = skb_cl->truesize;\n\n\tif (!skb_cl || cl_truesize < truesize || match_mstat_sniff_rules(flags, cl_truesize))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s(%u), skb_cl:%p, cl_truesize=%u\\n\", func, line, __FUNCTION__, truesize, skb_cl, cl_truesize);\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, skb_cl ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL\n\t\t, cl_truesize\n\t);\n\n\treturn skb_cl;\n}\n\ninline int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)\n{\n\tint ret;\n\tunsigned int truesize = skb->truesize;\n\n\tif (match_mstat_sniff_rules(flags, truesize))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s, truesize=%u\\n\", func, line, __FUNCTION__, truesize);\n\n\tret = _rtw_netif_rx(ndev, skb);\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, MSTAT_FREE\n\t\t, truesize\n\t);\n\n\treturn ret;\n}\n\n#ifdef CONFIG_RTW_NAPI\ninline int dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)\n{\n\tint ret;\n\tunsigned int truesize = skb->truesize;\n\n\tif (match_mstat_sniff_rules(flags, truesize))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s, truesize=%u\\n\", func, line, __FUNCTION__, truesize);\n\n\tret = _rtw_netif_receive_skb(ndev, skb);\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, MSTAT_FREE\n\t\t, truesize\n\t);\n\n\treturn ret;\n}\n\n#ifdef CONFIG_RTW_GRO\ninline gro_result_t dbg_rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)\n{\n\tint ret;\n\tunsigned int truesize = skb->truesize;\n\n\tif (match_mstat_sniff_rules(flags, truesize))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s, truesize=%u\\n\", func, line, __FUNCTION__, truesize);\n\n\tret = _rtw_napi_gro_receive(napi, skb);\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, MSTAT_FREE\n\t\t, truesize\n\t);\n\n\treturn ret;\n}\n#endif /* CONFIG_RTW_GRO */\n#endif /* CONFIG_RTW_NAPI */\n\ninline void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line)\n{\n\tstruct sk_buff *skb;\n\n\twhile ((skb = skb_dequeue(list)) != NULL)\n\t\tdbg_rtw_skb_free(skb, flags, func, line);\n}\n\n#ifdef CONFIG_USB_HCI\ninline void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, int line)\n{\n\tvoid *p;\n\n\tif (match_mstat_sniff_rules(flags, size))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s(%zu)\\n\", func, line, __FUNCTION__, size);\n\n\tp = _rtw_usb_buffer_alloc(dev, size, dma);\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL\n\t\t, size\n\t);\n\n\treturn p;\n}\n\ninline void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, int line)\n{\n\n\tif (match_mstat_sniff_rules(flags, size))\n\t\tRTW_INFO(\"DBG_MEM_ALLOC %s:%d %s(%zu)\\n\", func, line, __FUNCTION__, size);\n\n\t_rtw_usb_buffer_free(dev, size, addr, dma);\n\n\trtw_mstat_update(\n\t\tflags\n\t\t, MSTAT_FREE\n\t\t, size\n\t);\n}\n#endif /* CONFIG_USB_HCI */\n\n#endif /* defined(DBG_MEM_ALLOC) */\n\nvoid *rtw_malloc2d(int h, int w, size_t size)\n{\n\tint j;\n\n\tvoid **a = (void **) rtw_zmalloc(h * sizeof(void *) + h * w * size);\n\tif (a == NULL) {\n\t\tRTW_INFO(\"%s: alloc memory fail!\\n\", __FUNCTION__);\n\t\treturn NULL;\n\t}\n\n\tfor (j = 0; j < h; j++)\n\t\ta[j] = ((char *)(a + h)) + j * w * size;\n\n\treturn a;\n}\n\nvoid rtw_mfree2d(void *pbuf, int h, int w, int size)\n{\n\trtw_mfree((u8 *)pbuf, h * sizeof(void *) + w * h * size);\n}\n\ninline void rtw_os_pkt_free(_pkt *pkt)\n{\n#if defined(PLATFORM_LINUX)\n\trtw_skb_free(pkt);\n#elif defined(PLATFORM_FREEBSD)\n\tm_freem(pkt);\n#else\n\t#error \"TBD\\n\"\n#endif\n}\n\ninline _pkt *rtw_os_pkt_copy(_pkt *pkt)\n{\n#if defined(PLATFORM_LINUX)\n\treturn rtw_skb_copy(pkt);\n#elif defined(PLATFORM_FREEBSD)\n\treturn m_dup(pkt, M_NOWAIT);\n#else\n\t#error \"TBD\\n\"\n#endif\n}\n\ninline void *rtw_os_pkt_data(_pkt *pkt)\n{\n#if defined(PLATFORM_LINUX)\n\treturn pkt->data;\n#elif defined(PLATFORM_FREEBSD)\n\treturn pkt->m_data;\n#else\n\t#error \"TBD\\n\"\n#endif\n}\n\ninline u32 rtw_os_pkt_len(_pkt *pkt)\n{\n#if defined(PLATFORM_LINUX)\n\treturn pkt->len;\n#elif defined(PLATFORM_FREEBSD)\n\treturn pkt->m_pkthdr.len;\n#else\n\t#error \"TBD\\n\"\n#endif\n}\n\nvoid _rtw_memcpy(void *dst, const void *src, u32 sz)\n{\n\n#if defined(PLATFORM_LINUX) || defined (PLATFORM_FREEBSD)\n\n\tmemcpy(dst, src, sz);\n\n#endif\n\n#ifdef PLATFORM_WINDOWS\n\n\tNdisMoveMemory(dst, src, sz);\n\n#endif\n\n}\n\ninline void _rtw_memmove(void *dst, const void *src, u32 sz)\n{\n#if defined(PLATFORM_LINUX)\n\tmemmove(dst, src, sz);\n#else\n\t#error \"TBD\\n\"\n#endif\n}\n\nint\t_rtw_memcmp(const void *dst, const void *src, u32 sz)\n{\n\n#if defined(PLATFORM_LINUX) || defined (PLATFORM_FREEBSD)\n\t/* under Linux/GNU/GLibc, the return value of memcmp for two same mem. chunk is 0 */\n\n\tif (!(memcmp(dst, src, sz)))\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n#endif\n\n\n#ifdef PLATFORM_WINDOWS\n\t/* under Windows, the return value of NdisEqualMemory for two same mem. chunk is 1 */\n\n\tif (NdisEqualMemory(dst, src, sz))\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n\n#endif\n\n\n\n}\n\nvoid _rtw_memset(void *pbuf, int c, u32 sz)\n{\n\n#if defined(PLATFORM_LINUX) || defined (PLATFORM_FREEBSD)\n\n\tmemset(pbuf, c, sz);\n\n#endif\n\n#ifdef PLATFORM_WINDOWS\n#if 0\n\tNdisZeroMemory(pbuf, sz);\n\tif (c != 0)\n\t\tmemset(pbuf, c, sz);\n#else\n\tNdisFillMemory(pbuf, sz, c);\n#endif\n#endif\n\n}\n\n#ifdef PLATFORM_FREEBSD\nstatic inline void __list_add(_list *pnew, _list *pprev, _list *pnext)\n{\n\tpnext->prev = pnew;\n\tpnew->next = pnext;\n\tpnew->prev = pprev;\n\tpprev->next = pnew;\n}\n#endif /* PLATFORM_FREEBSD */\n\n\nvoid _rtw_init_listhead(_list *list)\n{\n\n#ifdef PLATFORM_LINUX\n\n\tINIT_LIST_HEAD(list);\n\n#endif\n\n#ifdef PLATFORM_FREEBSD\n\tlist->next = list;\n\tlist->prev = list;\n#endif\n#ifdef PLATFORM_WINDOWS\n\n\tNdisInitializeListHead(list);\n\n#endif\n\n}\n\n\n/*\nFor the following list_xxx operations,\ncaller must guarantee the atomic context.\nOtherwise, there will be racing condition.\n*/\nu32\trtw_is_list_empty(_list *phead)\n{\n\n#ifdef PLATFORM_LINUX\n\n\tif (list_empty(phead))\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n\n#endif\n#ifdef PLATFORM_FREEBSD\n\n\tif (phead->next == phead)\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n\n#endif\n\n\n#ifdef PLATFORM_WINDOWS\n\n\tif (IsListEmpty(phead))\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n\n#endif\n\n\n}\n\nvoid rtw_list_insert_head(_list *plist, _list *phead)\n{\n\n#ifdef PLATFORM_LINUX\n\tlist_add(plist, phead);\n#endif\n\n#ifdef PLATFORM_FREEBSD\n\t__list_add(plist, phead, phead->next);\n#endif\n\n#ifdef PLATFORM_WINDOWS\n\tInsertHeadList(phead, plist);\n#endif\n}\n\nvoid rtw_list_insert_tail(_list *plist, _list *phead)\n{\n\n#ifdef PLATFORM_LINUX\n\n\tlist_add_tail(plist, phead);\n\n#endif\n#ifdef PLATFORM_FREEBSD\n\n\t__list_add(plist, phead->prev, phead);\n\n#endif\n#ifdef PLATFORM_WINDOWS\n\n\tInsertTailList(phead, plist);\n\n#endif\n\n}\n\ninline void rtw_list_splice(_list *list, _list *head)\n{\n#ifdef PLATFORM_LINUX\n\tlist_splice(list, head);\n#else\n\t#error \"TBD\\n\"\n#endif\n}\n\ninline void rtw_list_splice_init(_list *list, _list *head)\n{\n#ifdef PLATFORM_LINUX\n\tlist_splice_init(list, head);\n#else\n\t#error \"TBD\\n\"\n#endif\n}\n\ninline void rtw_list_splice_tail(_list *list, _list *head)\n{\n#ifdef PLATFORM_LINUX\n\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27))\n\tif (!list_empty(list))\n\t\t__list_splice(list, head);\n\t#else\n\tlist_splice_tail(list, head);\n\t#endif\n#else\n\t#error \"TBD\\n\"\n#endif\n}\n\ninline void rtw_hlist_head_init(rtw_hlist_head *h)\n{\n#ifdef PLATFORM_LINUX\n\tINIT_HLIST_HEAD(h);\n#else\n\t#error \"TBD\\n\"\n#endif\n}\n\ninline void rtw_hlist_add_head(rtw_hlist_node *n, rtw_hlist_head *h)\n{\n#ifdef PLATFORM_LINUX\n\thlist_add_head(n, h);\n#else\n\t#error \"TBD\\n\"\n#endif\n}\n\ninline void rtw_hlist_del(rtw_hlist_node *n)\n{\n#ifdef PLATFORM_LINUX\n\thlist_del(n);\n#else\n\t#error \"TBD\\n\"\n#endif\n}\n\ninline void rtw_hlist_add_head_rcu(rtw_hlist_node *n, rtw_hlist_head *h)\n{\n#ifdef PLATFORM_LINUX\n\thlist_add_head_rcu(n, h);\n#else\n\t#error \"TBD\\n\"\n#endif\n}\n\ninline void rtw_hlist_del_rcu(rtw_hlist_node *n)\n{\n#ifdef PLATFORM_LINUX\n\thlist_del_rcu(n);\n#else\n\t#error \"TBD\\n\"\n#endif\n}\n\nvoid rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx)\n{\n\t_adapter *adapter = (_adapter *)padapter;\n\n#ifdef PLATFORM_LINUX\n\t_init_timer(ptimer, adapter->pnetdev, pfunc, ctx);\n#endif\n#ifdef PLATFORM_FREEBSD\n\t_init_timer(ptimer, adapter->pifp, pfunc, ctx);\n#endif\n#ifdef PLATFORM_WINDOWS\n\t_init_timer(ptimer, adapter->hndis_adapter, pfunc, ctx);\n#endif\n}\n\n/*\n\nCaller must check if the list is empty before calling rtw_list_delete\n\n*/\n\n\nvoid _rtw_init_sema(_sema\t*sema, int init_val)\n{\n\n#ifdef PLATFORM_LINUX\n\n\tsema_init(sema, init_val);\n\n#endif\n#ifdef PLATFORM_FREEBSD\n\tsema_init(sema, init_val, \"rtw_drv\");\n#endif\n#ifdef PLATFORM_OS_XP\n\n\tKeInitializeSemaphore(sema, init_val,  SEMA_UPBND); /* count=0; */\n\n#endif\n\n#ifdef PLATFORM_OS_CE\n\tif (*sema == NULL)\n\t\t*sema = CreateSemaphore(NULL, init_val, SEMA_UPBND, NULL);\n#endif\n\n}\n\nvoid _rtw_free_sema(_sema\t*sema)\n{\n#ifdef PLATFORM_FREEBSD\n\tsema_destroy(sema);\n#endif\n#ifdef PLATFORM_OS_CE\n\tCloseHandle(*sema);\n#endif\n\n}\n\nvoid _rtw_up_sema(_sema\t*sema)\n{\n\n#ifdef PLATFORM_LINUX\n\n\tup(sema);\n\n#endif\n#ifdef PLATFORM_FREEBSD\n\tsema_post(sema);\n#endif\n#ifdef PLATFORM_OS_XP\n\n\tKeReleaseSemaphore(sema, IO_NETWORK_INCREMENT, 1,  FALSE);\n\n#endif\n\n#ifdef PLATFORM_OS_CE\n\tReleaseSemaphore(*sema,  1,  NULL);\n#endif\n}\n\nu32 _rtw_down_sema(_sema *sema)\n{\n\n#ifdef PLATFORM_LINUX\n\n\tif (down_interruptible(sema))\n\t\treturn _FAIL;\n\telse\n\t\treturn _SUCCESS;\n\n#endif\n#ifdef PLATFORM_FREEBSD\n\tsema_wait(sema);\n\treturn  _SUCCESS;\n#endif\n#ifdef PLATFORM_OS_XP\n\n\tif (STATUS_SUCCESS == KeWaitForSingleObject(sema, Executive, KernelMode, TRUE, NULL))\n\t\treturn  _SUCCESS;\n\telse\n\t\treturn _FAIL;\n#endif\n\n#ifdef PLATFORM_OS_CE\n\tif (WAIT_OBJECT_0 == WaitForSingleObject(*sema, INFINITE))\n\t\treturn _SUCCESS;\n\telse\n\t\treturn _FAIL;\n#endif\n}\n\ninline void thread_exit(_completion *comp)\n{\n#ifdef PLATFORM_LINUX\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0))\n\tkthread_complete_and_exit(comp, 0);\n#else\n\tcomplete_and_exit(comp, 0);\n#endif\n#endif\n\n#ifdef PLATFORM_FREEBSD\n\tprintf(\"%s\", \"RTKTHREAD_exit\");\n#endif\n\n#ifdef PLATFORM_OS_CE\n\tExitThread(STATUS_SUCCESS);\n#endif\n\n#ifdef PLATFORM_OS_XP\n\tPsTerminateSystemThread(STATUS_SUCCESS);\n#endif\n}\n\ninline void _rtw_init_completion(_completion *comp)\n{\n#ifdef PLATFORM_LINUX\n\tinit_completion(comp);\n#endif\n}\ninline void _rtw_wait_for_comp_timeout(_completion *comp)\n{\n#ifdef PLATFORM_LINUX\n\twait_for_completion_timeout(comp, msecs_to_jiffies(3000));\n#endif\n}\ninline void _rtw_wait_for_comp(_completion *comp)\n{\n#ifdef PLATFORM_LINUX\n\twait_for_completion(comp);\n#endif\n}\n\nvoid\t_rtw_mutex_init(_mutex *pmutex)\n{\n#ifdef PLATFORM_LINUX\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))\n\tmutex_init(pmutex);\n#else\n\tinit_MUTEX(pmutex);\n#endif\n\n#endif\n#ifdef PLATFORM_FREEBSD\n\tmtx_init(pmutex, \"\", NULL, MTX_DEF | MTX_RECURSE);\n#endif\n#ifdef PLATFORM_OS_XP\n\n\tKeInitializeMutex(pmutex, 0);\n\n#endif\n\n#ifdef PLATFORM_OS_CE\n\t*pmutex =  CreateMutex(NULL, _FALSE, NULL);\n#endif\n}\n\nvoid\t_rtw_mutex_free(_mutex *pmutex);\nvoid\t_rtw_mutex_free(_mutex *pmutex)\n{\n#ifdef PLATFORM_LINUX\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))\n\tmutex_destroy(pmutex);\n#else\n#endif\n\n#ifdef PLATFORM_FREEBSD\n\tsema_destroy(pmutex);\n#endif\n\n#endif\n\n#ifdef PLATFORM_OS_XP\n\n#endif\n\n#ifdef PLATFORM_OS_CE\n\n#endif\n}\n\nvoid\t_rtw_spinlock_init(_lock *plock)\n{\n\n#ifdef PLATFORM_LINUX\n\n\tspin_lock_init(plock);\n\n#endif\n#ifdef PLATFORM_FREEBSD\n\tmtx_init(plock, \"\", NULL, MTX_DEF | MTX_RECURSE);\n#endif\n#ifdef PLATFORM_WINDOWS\n\n\tNdisAllocateSpinLock(plock);\n\n#endif\n\n}\n\nvoid\t_rtw_spinlock_free(_lock *plock)\n{\n#ifdef PLATFORM_FREEBSD\n\tmtx_destroy(plock);\n#endif\n\n#ifdef PLATFORM_WINDOWS\n\n\tNdisFreeSpinLock(plock);\n\n#endif\n\n}\n#ifdef PLATFORM_FREEBSD\nextern PADAPTER prtw_lock;\n\nvoid rtw_mtx_lock(_lock *plock)\n{\n\tif (prtw_lock)\n\t\tmtx_lock(&prtw_lock->glock);\n\telse\n\t\tprintf(\"%s prtw_lock==NULL\", __FUNCTION__);\n}\nvoid rtw_mtx_unlock(_lock *plock)\n{\n\tif (prtw_lock)\n\t\tmtx_unlock(&prtw_lock->glock);\n\telse\n\t\tprintf(\"%s prtw_lock==NULL\", __FUNCTION__);\n\n}\n#endif /* PLATFORM_FREEBSD */\n\n\nvoid\t_rtw_spinlock(_lock\t*plock)\n{\n\n#ifdef PLATFORM_LINUX\n\n\tspin_lock(plock);\n\n#endif\n#ifdef PLATFORM_FREEBSD\n\tmtx_lock(plock);\n#endif\n#ifdef PLATFORM_WINDOWS\n\n\tNdisAcquireSpinLock(plock);\n\n#endif\n\n}\n\nvoid\t_rtw_spinunlock(_lock *plock)\n{\n\n#ifdef PLATFORM_LINUX\n\n\tspin_unlock(plock);\n\n#endif\n#ifdef PLATFORM_FREEBSD\n\tmtx_unlock(plock);\n#endif\n#ifdef PLATFORM_WINDOWS\n\n\tNdisReleaseSpinLock(plock);\n\n#endif\n}\n\n\nvoid\t_rtw_spinlock_ex(_lock\t*plock)\n{\n\n#ifdef PLATFORM_LINUX\n\n\tspin_lock(plock);\n\n#endif\n#ifdef PLATFORM_FREEBSD\n\tmtx_lock(plock);\n#endif\n#ifdef PLATFORM_WINDOWS\n\n\tNdisDprAcquireSpinLock(plock);\n\n#endif\n\n}\n\nvoid\t_rtw_spinunlock_ex(_lock *plock)\n{\n\n#ifdef PLATFORM_LINUX\n\n\tspin_unlock(plock);\n\n#endif\n#ifdef PLATFORM_FREEBSD\n\tmtx_unlock(plock);\n#endif\n#ifdef PLATFORM_WINDOWS\n\n\tNdisDprReleaseSpinLock(plock);\n\n#endif\n}\n\n\n\nvoid _rtw_init_queue(_queue *pqueue)\n{\n\t_rtw_init_listhead(&(pqueue->queue));\n\t_rtw_spinlock_init(&(pqueue->lock));\n}\n\nvoid _rtw_deinit_queue(_queue *pqueue)\n{\n\t_rtw_spinlock_free(&(pqueue->lock));\n}\n\nu32\t  _rtw_queue_empty(_queue\t*pqueue)\n{\n\treturn rtw_is_list_empty(&(pqueue->queue));\n}\n\n\nu32 rtw_end_of_queue_search(_list *head, _list *plist)\n{\n\tif (head == plist)\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\n\n\nsystime _rtw_get_current_time(void)\n{\n\n#ifdef PLATFORM_LINUX\n\treturn jiffies;\n#endif\n#ifdef PLATFORM_FREEBSD\n\tstruct timeval tvp;\n\tgetmicrotime(&tvp);\n\treturn tvp.tv_sec;\n#endif\n#ifdef PLATFORM_WINDOWS\n\tLARGE_INTEGER\tSystemTime;\n\tNdisGetCurrentSystemTime(&SystemTime);\n\treturn SystemTime.LowPart;/* count of 100-nanosecond intervals */\n#endif\n}\n\ninline u32 _rtw_systime_to_ms(systime stime)\n{\n#ifdef PLATFORM_LINUX\n\treturn jiffies_to_msecs(stime);\n#endif\n#ifdef PLATFORM_FREEBSD\n\treturn stime * 1000;\n#endif\n#ifdef PLATFORM_WINDOWS\n\treturn stime / 10000 ;\n#endif\n}\n\ninline systime _rtw_ms_to_systime(u32 ms)\n{\n#ifdef PLATFORM_LINUX\n\treturn msecs_to_jiffies(ms);\n#endif\n#ifdef PLATFORM_FREEBSD\n\treturn ms / 1000;\n#endif\n#ifdef PLATFORM_WINDOWS\n\treturn ms * 10000 ;\n#endif\n}\n\ninline systime _rtw_us_to_systime(u32 us)\n{\n#ifdef PLATFORM_LINUX\n\treturn usecs_to_jiffies(us);\n#else\n\t#error \"TBD\\n\"\n#endif\n}\n\n/* the input parameter start use the same unit as returned by rtw_get_current_time */\ninline s32 _rtw_get_passing_time_ms(systime start)\n{\n\treturn _rtw_systime_to_ms(_rtw_get_current_time() - start);\n}\n\ninline s32 _rtw_get_remaining_time_ms(systime end)\n{\n\treturn _rtw_systime_to_ms(end - _rtw_get_current_time());\n}\n\ninline s32 _rtw_get_time_interval_ms(systime start, systime end)\n{\n\treturn _rtw_systime_to_ms(end - start);\n}\n\ninline bool _rtw_time_after(systime a, systime b)\n{\n#ifdef PLATFORM_LINUX\n\treturn time_after(a, b);\n#else\n\t#error \"TBD\\n\"\n#endif\n}\n\nvoid rtw_sleep_schedulable(int ms)\n{\n\n#ifdef PLATFORM_LINUX\n\n\tu32 delta;\n\n\tdelta = (ms * HZ) / 1000; /* (ms) */\n\tif (delta == 0) {\n\t\tdelta = 1;/* 1 ms */\n\t}\n\tset_current_state(TASK_INTERRUPTIBLE);\n\tif (schedule_timeout(delta) != 0)\n\t\treturn ;\n\treturn;\n\n#endif\n#ifdef PLATFORM_FREEBSD\n\tDELAY(ms * 1000);\n\treturn ;\n#endif\n\n#ifdef PLATFORM_WINDOWS\n\n\tNdisMSleep(ms * 1000); /* (us)*1000=(ms) */\n\n#endif\n\n}\n\n\nvoid rtw_msleep_os(int ms)\n{\n\n#ifdef PLATFORM_LINUX\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))\n\tif (ms < 20) {\n\t\tunsigned long us = ms * 1000UL;\n\t\tusleep_range(us, us + 1000UL);\n\t} else\n#endif\n\t\tmsleep((unsigned int)ms);\n\n#endif\n#ifdef PLATFORM_FREEBSD\n\t/* Delay for delay microseconds */\n\tDELAY(ms * 1000);\n\treturn ;\n#endif\n#ifdef PLATFORM_WINDOWS\n\n\tNdisMSleep(ms * 1000); /* (us)*1000=(ms) */\n\n#endif\n\n\n}\nvoid rtw_usleep_os(int us)\n{\n#ifdef PLATFORM_LINUX\n\n\t/* msleep((unsigned int)us); */\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))\n\tusleep_range(us, us + 1);\n#else\n\tif (1 < (us / 1000))\n\t\tmsleep(1);\n\telse\n\t\tmsleep((us / 1000) + 1);\n#endif\n#endif\n\n#ifdef PLATFORM_FREEBSD\n\t/* Delay for delay microseconds */\n\tDELAY(us);\n\n\treturn ;\n#endif\n#ifdef PLATFORM_WINDOWS\n\n\tNdisMSleep(us); /* (us) */\n\n#endif\n\n\n}\n\n\n#ifdef DBG_DELAY_OS\nvoid _rtw_mdelay_os(int ms, const char *func, const int line)\n{\n#if 0\n\tif (ms > 10)\n\t\tRTW_INFO(\"%s:%d %s(%d)\\n\", func, line, __FUNCTION__, ms);\n\trtw_msleep_os(ms);\n\treturn;\n#endif\n\n\n\tRTW_INFO(\"%s:%d %s(%d)\\n\", func, line, __FUNCTION__, ms);\n\n#if defined(PLATFORM_LINUX)\n\n\tmdelay((unsigned long)ms);\n\n#elif defined(PLATFORM_WINDOWS)\n\n\tNdisStallExecution(ms * 1000); /* (us)*1000=(ms) */\n\n#endif\n\n\n}\nvoid _rtw_udelay_os(int us, const char *func, const int line)\n{\n\n#if 0\n\tif (us > 1000) {\n\t\tRTW_INFO(\"%s:%d %s(%d)\\n\", func, line, __FUNCTION__, us);\n\t\trtw_usleep_os(us);\n\t\treturn;\n\t}\n#endif\n\n\n\tRTW_INFO(\"%s:%d %s(%d)\\n\", func, line, __FUNCTION__, us);\n\n\n#if defined(PLATFORM_LINUX)\n\n\tudelay((unsigned long)us);\n\n#elif defined(PLATFORM_WINDOWS)\n\n\tNdisStallExecution(us); /* (us) */\n\n#endif\n\n}\n#else\nvoid rtw_mdelay_os(int ms)\n{\n\n#ifdef PLATFORM_LINUX\n\n\tmdelay((unsigned long)ms);\n\n#endif\n#ifdef PLATFORM_FREEBSD\n\tDELAY(ms * 1000);\n\treturn ;\n#endif\n#ifdef PLATFORM_WINDOWS\n\n\tNdisStallExecution(ms * 1000); /* (us)*1000=(ms) */\n\n#endif\n\n\n}\nvoid rtw_udelay_os(int us)\n{\n\n#ifdef PLATFORM_LINUX\n\n\tudelay((unsigned long)us);\n\n#endif\n#ifdef PLATFORM_FREEBSD\n\t/* Delay for delay microseconds */\n\tDELAY(us);\n\treturn ;\n#endif\n#ifdef PLATFORM_WINDOWS\n\n\tNdisStallExecution(us); /* (us) */\n\n#endif\n\n}\n#endif\n\nvoid rtw_yield_os(void)\n{\n#ifdef PLATFORM_LINUX\n\tyield();\n#endif\n#ifdef PLATFORM_FREEBSD\n\tyield();\n#endif\n#ifdef PLATFORM_WINDOWS\n\tSwitchToThread();\n#endif\n}\n\nbool rtw_macaddr_is_larger(const u8 *a, const u8 *b)\n{\n\tu32 va, vb;\n\n\tva = be32_to_cpu(*((u32 *)a));\n\tvb = be32_to_cpu(*((u32 *)b));\n\tif (va > vb)\n\t\treturn 1;\n\telse if (va < vb)\n\t\treturn 0;\n\n\treturn be16_to_cpu(*((u16 *)(a + 4))) > be16_to_cpu(*((u16 *)(b + 4)));\n}\n\n#define RTW_SUSPEND_LOCK_NAME \"rtw_wifi\"\n#define RTW_SUSPEND_TRAFFIC_LOCK_NAME \"rtw_wifi_traffic\"\n#define RTW_SUSPEND_RESUME_LOCK_NAME \"rtw_wifi_resume\"\n#ifdef CONFIG_WAKELOCK\nstatic struct wake_lock rtw_suspend_lock;\nstatic struct wake_lock rtw_suspend_traffic_lock;\nstatic struct wake_lock rtw_suspend_resume_lock;\n#elif defined(CONFIG_ANDROID_POWER)\nstatic android_suspend_lock_t rtw_suspend_lock = {\n\t.name = RTW_SUSPEND_LOCK_NAME\n};\nstatic android_suspend_lock_t rtw_suspend_traffic_lock = {\n\t.name = RTW_SUSPEND_TRAFFIC_LOCK_NAME\n};\nstatic android_suspend_lock_t rtw_suspend_resume_lock = {\n\t.name = RTW_SUSPEND_RESUME_LOCK_NAME\n};\n#endif\n\ninline void rtw_suspend_lock_init(void)\n{\n#ifdef CONFIG_WAKELOCK\n\twake_lock_init(&rtw_suspend_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_LOCK_NAME);\n\twake_lock_init(&rtw_suspend_traffic_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_TRAFFIC_LOCK_NAME);\n\twake_lock_init(&rtw_suspend_resume_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_RESUME_LOCK_NAME);\n#elif defined(CONFIG_ANDROID_POWER)\n\tandroid_init_suspend_lock(&rtw_suspend_lock);\n\tandroid_init_suspend_lock(&rtw_suspend_traffic_lock);\n\tandroid_init_suspend_lock(&rtw_suspend_resume_lock);\n#endif\n}\n\ninline void rtw_suspend_lock_uninit(void)\n{\n#ifdef CONFIG_WAKELOCK\n\twake_lock_destroy(&rtw_suspend_lock);\n\twake_lock_destroy(&rtw_suspend_traffic_lock);\n\twake_lock_destroy(&rtw_suspend_resume_lock);\n#elif defined(CONFIG_ANDROID_POWER)\n\tandroid_uninit_suspend_lock(&rtw_suspend_lock);\n\tandroid_uninit_suspend_lock(&rtw_suspend_traffic_lock);\n\tandroid_uninit_suspend_lock(&rtw_suspend_resume_lock);\n#endif\n}\n\ninline void rtw_lock_suspend(void)\n{\n#ifdef CONFIG_WAKELOCK\n\twake_lock(&rtw_suspend_lock);\n#elif defined(CONFIG_ANDROID_POWER)\n\tandroid_lock_suspend(&rtw_suspend_lock);\n#endif\n\n#if  defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)\n\t/* RTW_INFO(\"####%s: suspend_lock_count:%d####\\n\", __FUNCTION__, rtw_suspend_lock.stat.count); */\n#endif\n}\n\ninline void rtw_unlock_suspend(void)\n{\n#ifdef CONFIG_WAKELOCK\n\twake_unlock(&rtw_suspend_lock);\n#elif defined(CONFIG_ANDROID_POWER)\n\tandroid_unlock_suspend(&rtw_suspend_lock);\n#endif\n\n#if  defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)\n\t/* RTW_INFO(\"####%s: suspend_lock_count:%d####\\n\", __FUNCTION__, rtw_suspend_lock.stat.count); */\n#endif\n}\n\ninline void rtw_resume_lock_suspend(void)\n{\n#ifdef CONFIG_WAKELOCK\n\twake_lock(&rtw_suspend_resume_lock);\n#elif defined(CONFIG_ANDROID_POWER)\n\tandroid_lock_suspend(&rtw_suspend_resume_lock);\n#endif\n\n#if  defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)\n\t/* RTW_INFO(\"####%s: suspend_lock_count:%d####\\n\", __FUNCTION__, rtw_suspend_lock.stat.count); */\n#endif\n}\n\ninline void rtw_resume_unlock_suspend(void)\n{\n#ifdef CONFIG_WAKELOCK\n\twake_unlock(&rtw_suspend_resume_lock);\n#elif defined(CONFIG_ANDROID_POWER)\n\tandroid_unlock_suspend(&rtw_suspend_resume_lock);\n#endif\n\n#if  defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)\n\t/* RTW_INFO(\"####%s: suspend_lock_count:%d####\\n\", __FUNCTION__, rtw_suspend_lock.stat.count); */\n#endif\n}\n\ninline void rtw_lock_suspend_timeout(u32 timeout_ms)\n{\n#ifdef CONFIG_WAKELOCK\n\twake_lock_timeout(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms));\n#elif defined(CONFIG_ANDROID_POWER)\n\tandroid_lock_suspend_auto_expire(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms));\n#endif\n}\n\n\ninline void rtw_lock_traffic_suspend_timeout(u32 timeout_ms)\n{\n#ifdef CONFIG_WAKELOCK\n\twake_lock_timeout(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms));\n#elif defined(CONFIG_ANDROID_POWER)\n\tandroid_lock_suspend_auto_expire(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms));\n#endif\n\t/* RTW_INFO(\"traffic lock timeout:%d\\n\", timeout_ms); */\n}\n\ninline void rtw_set_bit(int nr, unsigned long *addr)\n{\n#ifdef PLATFORM_LINUX\n\tset_bit(nr, addr);\n#else\n\t#error \"TBD\\n\";\n#endif\n}\n\ninline void rtw_clear_bit(int nr, unsigned long *addr)\n{\n#ifdef PLATFORM_LINUX\n\tclear_bit(nr, addr);\n#else\n\t#error \"TBD\\n\";\n#endif\n}\n\ninline int rtw_test_and_clear_bit(int nr, unsigned long *addr)\n{\n#ifdef PLATFORM_LINUX\n\treturn test_and_clear_bit(nr, addr);\n#else\n\t#error \"TBD\\n\";\n#endif\n}\n\ninline void ATOMIC_SET(ATOMIC_T *v, int i)\n{\n#ifdef PLATFORM_LINUX\n\tatomic_set(v, i);\n#elif defined(PLATFORM_WINDOWS)\n\t*v = i; /* other choice???? */\n#elif defined(PLATFORM_FREEBSD)\n\tatomic_set_int(v, i);\n#endif\n}\n\ninline int ATOMIC_READ(ATOMIC_T *v)\n{\n#ifdef PLATFORM_LINUX\n\treturn atomic_read(v);\n#elif defined(PLATFORM_WINDOWS)\n\treturn *v; /* other choice???? */\n#elif defined(PLATFORM_FREEBSD)\n\treturn atomic_load_acq_32(v);\n#endif\n}\n\ninline void ATOMIC_ADD(ATOMIC_T *v, int i)\n{\n#ifdef PLATFORM_LINUX\n\tatomic_add(i, v);\n#elif defined(PLATFORM_WINDOWS)\n\tInterlockedAdd(v, i);\n#elif defined(PLATFORM_FREEBSD)\n\tatomic_add_int(v, i);\n#endif\n}\ninline void ATOMIC_SUB(ATOMIC_T *v, int i)\n{\n#ifdef PLATFORM_LINUX\n\tatomic_sub(i, v);\n#elif defined(PLATFORM_WINDOWS)\n\tInterlockedAdd(v, -i);\n#elif defined(PLATFORM_FREEBSD)\n\tatomic_subtract_int(v, i);\n#endif\n}\n\ninline void ATOMIC_INC(ATOMIC_T *v)\n{\n#ifdef PLATFORM_LINUX\n\tatomic_inc(v);\n#elif defined(PLATFORM_WINDOWS)\n\tInterlockedIncrement(v);\n#elif defined(PLATFORM_FREEBSD)\n\tatomic_add_int(v, 1);\n#endif\n}\n\ninline void ATOMIC_DEC(ATOMIC_T *v)\n{\n#ifdef PLATFORM_LINUX\n\tatomic_dec(v);\n#elif defined(PLATFORM_WINDOWS)\n\tInterlockedDecrement(v);\n#elif defined(PLATFORM_FREEBSD)\n\tatomic_subtract_int(v, 1);\n#endif\n}\n\ninline int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i)\n{\n#ifdef PLATFORM_LINUX\n\treturn atomic_add_return(i, v);\n#elif defined(PLATFORM_WINDOWS)\n\treturn InterlockedAdd(v, i);\n#elif defined(PLATFORM_FREEBSD)\n\tatomic_add_int(v, i);\n\treturn atomic_load_acq_32(v);\n#endif\n}\n\ninline int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i)\n{\n#ifdef PLATFORM_LINUX\n\treturn atomic_sub_return(i, v);\n#elif defined(PLATFORM_WINDOWS)\n\treturn InterlockedAdd(v, -i);\n#elif defined(PLATFORM_FREEBSD)\n\tatomic_subtract_int(v, i);\n\treturn atomic_load_acq_32(v);\n#endif\n}\n\ninline int ATOMIC_INC_RETURN(ATOMIC_T *v)\n{\n#ifdef PLATFORM_LINUX\n\treturn atomic_inc_return(v);\n#elif defined(PLATFORM_WINDOWS)\n\treturn InterlockedIncrement(v);\n#elif defined(PLATFORM_FREEBSD)\n\tatomic_add_int(v, 1);\n\treturn atomic_load_acq_32(v);\n#endif\n}\n\ninline int ATOMIC_DEC_RETURN(ATOMIC_T *v)\n{\n#ifdef PLATFORM_LINUX\n\treturn atomic_dec_return(v);\n#elif defined(PLATFORM_WINDOWS)\n\treturn InterlockedDecrement(v);\n#elif defined(PLATFORM_FREEBSD)\n\tatomic_subtract_int(v, 1);\n\treturn atomic_load_acq_32(v);\n#endif\n}\n\ninline bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u)\n{\n#ifdef PLATFORM_LINUX\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 15))\n\treturn atomic_add_unless(v, 1, u);\n#else\n\t/* only make sure not exceed after this function */\n\tif (ATOMIC_INC_RETURN(v) > u) {\n\t\tATOMIC_DEC(v);\n\t\treturn 0;\n\t}\n\treturn 1;\n#endif\n#else\n\t#error \"TBD\\n\"\n#endif\n}\n\n#ifdef PLATFORM_LINUX\n/*\n* Open a file with the specific @param path, @param flag, @param mode\n* @param fpp the pointer of struct file pointer to get struct file pointer while file opening is success\n* @param path the path of the file to open\n* @param flag file operation flags, please refer to linux document\n* @param mode please refer to linux document\n* @return Linux specific error code\n*/\nstatic int openFile(struct file **fpp, const char *path, int flag, int mode)\n{\n\tstruct file *fp;\n\n\tfp = filp_open(path, flag, mode);\n\tif (IS_ERR(fp)) {\n\t\t*fpp = NULL;\n\t\treturn PTR_ERR(fp);\n\t} else {\n\t\t*fpp = fp;\n\t\treturn 0;\n\t}\n}\n\n/*\n* Close the file with the specific @param fp\n* @param fp the pointer of struct file to close\n* @return always 0\n*/\nstatic int closeFile(struct file *fp)\n{\n\tfilp_close(fp, NULL);\n\treturn 0;\n}\n\nstatic int readFile(struct file *fp, char *buf, int len)\n{\n\tint rlen = 0, sum = 0;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))\n\tif (!(fp->f_mode & FMODE_CAN_READ))\n#else\n\tif (!fp->f_op || !fp->f_op->read)\n#endif\n\t\treturn -EPERM;\n\n\twhile (sum < len) {\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))\n\t\trlen = kernel_read(fp, buf + sum, len - sum, &fp->f_pos);\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))\n\t\trlen = __vfs_read(fp, buf + sum, len - sum, &fp->f_pos);\n#else\n\t\trlen = fp->f_op->read(fp, buf + sum, len - sum, &fp->f_pos);\n#endif\n\t\tif (rlen > 0)\n\t\t\tsum += rlen;\n\t\telse if (0 != rlen)\n\t\t\treturn rlen;\n\t\telse\n\t\t\tbreak;\n\t}\n\n\treturn  sum;\n\n}\n\nstatic int writeFile(struct file *fp, char *buf, int len)\n{\n\tint wlen = 0, sum = 0;\n\n\tif (!fp->f_op || !fp->f_op->write)\n\t\treturn -EPERM;\n\n\twhile (sum < len) {\n\t\twlen = fp->f_op->write(fp, buf + sum, len - sum, &fp->f_pos);\n\t\tif (wlen > 0)\n\t\t\tsum += wlen;\n\t\telse if (0 != wlen)\n\t\t\treturn wlen;\n\t\telse\n\t\t\tbreak;\n\t}\n\n\treturn sum;\n\n}\n\n/*\n* Test if the specifi @param path is a file and readable\n* If readable, @param sz is got\n* @param path the path of the file to test\n* @return Linux specific error code\n*/\nstatic int isFileReadable(const char *path, u32 *sz)\n{\n\tstruct file *fp;\n\tint ret = 0;\n\t\n\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))\n\tmm_segment_t oldfs;\n\t#endif;\n\t\n\tchar buf;\n\n\tfp = filp_open(path, O_RDONLY, 0);\n\tif (IS_ERR(fp))\n\t\tret = PTR_ERR(fp);\n\telse {\n\t\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))\n\t\toldfs = get_fs();\n\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0))\n\t\tset_fs(KERNEL_DS);\n\t\t#else\n\t\tset_fs(get_ds());\n\t\t#endif\n\t\t#endif\n\n\t\tif (1 != readFile(fp, &buf, 1))\n\t\t\tret = PTR_ERR(fp);\n\n\t\tif (ret == 0 && sz) {\n\t\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))\n\t\t\t*sz = i_size_read(fp->f_path.dentry->d_inode);\n\t\t\t#else\n\t\t\t*sz = i_size_read(fp->f_dentry->d_inode);\n\t\t\t#endif\n\t\t}\n\t\t\n\t\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))\n\t\tset_fs(oldfs);\n\t\t#endif\n\t\t\n\t\tfilp_close(fp, NULL);\n\t}\n\treturn ret;\n}\n\n/*\n* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most\n* @param path the path of the file to open and read\n* @param buf the starting address of the buffer to store file content\n* @param sz how many bytes to read at most\n* @return the byte we've read, or Linux specific error code\n*/\nstatic int retriveFromFile(const char *path, u8 *buf, u32 sz)\n{\n\tint ret = -1;\n\t\n\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))\n\tmm_segment_t oldfs;\n\t#endif\n\t\n\tstruct file *fp;\n\n\tif (path && buf) {\n\t\tret = openFile(&fp, path, O_RDONLY, 0);\n\t\tif (0 == ret) {\n\t\t\tRTW_INFO(\"%s openFile path:%s fp=%p\\n\", __FUNCTION__, path , fp);\n\t\t\t\n\t\t\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))\n\t\t\toldfs = get_fs();\n\t\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0))\n\t\t\tset_fs(KERNEL_DS);\n\t\t\t#else\n\t\t\tset_fs(get_ds());\n\t\t\t#endif\n\t\t\t#endif\n\t\t\t\n\t\t\tret = readFile(fp, buf, sz);\n\t\t\t\n\t\t\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))\n\t\t\tset_fs(oldfs);\n\t\t\t#endif\n\t\t\t\n\t\t\tcloseFile(fp);\n\n\t\t\tRTW_INFO(\"%s readFile, ret:%d\\n\", __FUNCTION__, ret);\n\n\t\t} else\n\t\t\tRTW_INFO(\"%s openFile path:%s Fail, ret:%d\\n\", __FUNCTION__, path, ret);\n\t} else {\n\t\tRTW_INFO(\"%s NULL pointer\\n\", __FUNCTION__);\n\t\tret =  -EINVAL;\n\t}\n\treturn ret;\n}\n\n/*\n* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file\n* @param path the path of the file to open and write\n* @param buf the starting address of the data to write into file\n* @param sz how many bytes to write at most\n* @return the byte we've written, or Linux specific error code\n*/\nstatic int storeToFile(const char *path, u8 *buf, u32 sz)\n{\n\tint ret = 0;\n\t\n\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))\n\tmm_segment_t oldfs;\n\t#endif\n\t\n\tstruct file *fp;\n\n\tif (path && buf) {\n\t\tret = openFile(&fp, path, O_CREAT | O_WRONLY, 0666);\n\t\tif (0 == ret) {\n\t\t\tRTW_INFO(\"%s openFile path:%s fp=%p\\n\", __FUNCTION__, path , fp);\n\t\t\t\n\t\t\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))\n\t\t\toldfs = get_fs();\n\t\t\t#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0))\n\t\t\tset_fs(KERNEL_DS);\n\t\t\t#else\n\t\t\tset_fs(get_ds());\n\t\t\t#endif\n\t\t\t#endif\n\t\t\t\n\t\t\tret = writeFile(fp, buf, sz);\n\t\t\t\n\t\t\t#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))\n\t\t\tset_fs(oldfs);\n\t\t\t#endif\n\t\t\t\n\t\t\tcloseFile(fp);\n\n\t\t\tRTW_INFO(\"%s writeFile, ret:%d\\n\", __FUNCTION__, ret);\n\n\t\t} else\n\t\t\tRTW_INFO(\"%s openFile path:%s Fail, ret:%d\\n\", __FUNCTION__, path, ret);\n\t} else {\n\t\tRTW_INFO(\"%s NULL pointer\\n\", __FUNCTION__);\n\t\tret =  -EINVAL;\n\t}\n\treturn ret;\n}\n#endif /* PLATFORM_LINUX */\n\n/*\n* Test if the specifi @param path is a file and readable\n* @param path the path of the file to test\n* @return _TRUE or _FALSE\n*/\nint rtw_is_file_readable(const char *path)\n{\n#ifdef PLATFORM_LINUX\n\tif (isFileReadable(path, NULL) == 0)\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n#else\n\t/* Todo... */\n\treturn _FALSE;\n#endif\n}\n\n/*\n* Test if the specifi @param path is a file and readable.\n* If readable, @param sz is got\n* @param path the path of the file to test\n* @return _TRUE or _FALSE\n*/\nint rtw_is_file_readable_with_size(const char *path, u32 *sz)\n{\n#ifdef PLATFORM_LINUX\n\tif (isFileReadable(path, sz) == 0)\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n#else\n\t/* Todo... */\n\treturn _FALSE;\n#endif\n}\n\n/*\n* Test if the specifi @param path is a readable file with valid size.\n* If readable, @param sz is got\n* @param path the path of the file to test\n* @return _TRUE or _FALSE\n*/\nint rtw_readable_file_sz_chk(const char *path, u32 sz)\n{\n\tu32 fsz;\n\n\tif (rtw_is_file_readable_with_size(path, &fsz) == _FALSE)\n\t\treturn _FALSE;\n\n\tif (fsz > sz)\n\t\treturn _FALSE;\n\t\n\treturn _TRUE;\n}\n\n/*\n* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most\n* @param path the path of the file to open and read\n* @param buf the starting address of the buffer to store file content\n* @param sz how many bytes to read at most\n* @return the byte we've read\n*/\nint rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz)\n{\n#ifdef PLATFORM_LINUX\n\tint ret = retriveFromFile(path, buf, sz);\n\treturn ret >= 0 ? ret : 0;\n#else\n\t/* Todo... */\n\treturn 0;\n#endif\n}\n\n/*\n* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file\n* @param path the path of the file to open and write\n* @param buf the starting address of the data to write into file\n* @param sz how many bytes to write at most\n* @return the byte we've written\n*/\nint rtw_store_to_file(const char *path, u8 *buf, u32 sz)\n{\n#ifdef PLATFORM_LINUX\n\tint ret = storeToFile(path, buf, sz);\n\treturn ret >= 0 ? ret : 0;\n#else\n\t/* Todo... */\n\treturn 0;\n#endif\n}\n\n#ifdef PLATFORM_LINUX\nstruct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv)\n{\n\tstruct net_device *pnetdev;\n\tstruct rtw_netdev_priv_indicator *pnpi;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\tpnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4);\n#else\n\tpnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator));\n#endif\n\tif (!pnetdev)\n\t\tgoto RETURN;\n\n\tpnpi = netdev_priv(pnetdev);\n\tpnpi->priv = old_priv;\n\tpnpi->sizeof_priv = sizeof_priv;\n\nRETURN:\n\treturn pnetdev;\n}\n\nstruct net_device *rtw_alloc_etherdev(int sizeof_priv)\n{\n\tstruct net_device *pnetdev;\n\tstruct rtw_netdev_priv_indicator *pnpi;\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))\n\tpnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4);\n#else\n\tpnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator));\n#endif\n\tif (!pnetdev)\n\t\tgoto RETURN;\n\n\tpnpi = netdev_priv(pnetdev);\n\n\tpnpi->priv = rtw_zvmalloc(sizeof_priv);\n\tif (!pnpi->priv) {\n\t\tfree_netdev(pnetdev);\n\t\tpnetdev = NULL;\n\t\tgoto RETURN;\n\t}\n\n\tpnpi->sizeof_priv = sizeof_priv;\nRETURN:\n\treturn pnetdev;\n}\n\nvoid rtw_free_netdev(struct net_device *netdev)\n{\n\tstruct rtw_netdev_priv_indicator *pnpi;\n\n\tif (!netdev)\n\t\tgoto RETURN;\n\n\tpnpi = netdev_priv(netdev);\n\n\tif (!pnpi->priv)\n\t\tgoto RETURN;\n\n\tfree_netdev(netdev);\n\nRETURN:\n\treturn;\n}\n\nint rtw_change_ifname(_adapter *padapter, const char *ifname)\n{\n\tstruct dvobj_priv *dvobj;\n\tstruct net_device *pnetdev;\n\tstruct net_device *cur_pnetdev;\n\tstruct rereg_nd_name_data *rereg_priv;\n\tint ret;\n\tu8 rtnl_lock_needed;\n\n\tif (!padapter)\n\t\tgoto error;\n\n\tdvobj = adapter_to_dvobj(padapter);\n\tcur_pnetdev = padapter->pnetdev;\n\trereg_priv = &padapter->rereg_nd_name_priv;\n\n\t/* free the old_pnetdev */\n\tif (rereg_priv->old_pnetdev) {\n\t\tfree_netdev(rereg_priv->old_pnetdev);\n\t\trereg_priv->old_pnetdev = NULL;\n\t}\n\n\trtnl_lock_needed = rtw_rtnl_lock_needed(dvobj);\n\n\tif (rtnl_lock_needed)\n\t\tunregister_netdev(cur_pnetdev);\n\telse\n\t\tunregister_netdevice(cur_pnetdev);\n\n\trereg_priv->old_pnetdev = cur_pnetdev;\n\n\tpnetdev = rtw_init_netdev(padapter);\n\tif (!pnetdev)  {\n\t\tret = -1;\n\t\tgoto error;\n\t}\n\n\tSET_NETDEV_DEV(pnetdev, dvobj_to_dev(adapter_to_dvobj(padapter)));\n\n\trtw_init_netdev_name(pnetdev, ifname);\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0)\n\t_rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN);\n#else\n\tdev_addr_set(pnetdev, adapter_mac_addr(padapter));\n#endif\n\n\tif (rtnl_lock_needed)\n\t\tret = register_netdev(pnetdev);\n\telse\n\t\tret = register_netdevice(pnetdev);\n\n\tif (ret != 0) {\n\t\tgoto error;\n\t}\n\n\treturn 0;\n\nerror:\n\n\treturn -1;\n\n}\n#endif\n\n#ifdef PLATFORM_FREEBSD\n/*\n * Copy a buffer from userspace and write into kernel address\n * space.\n *\n * This emulation just calls the FreeBSD copyin function (to\n * copy data from user space buffer into a kernel space buffer)\n * and is designed to be used with the above io_write_wrapper.\n *\n * This function should return the number of bytes not copied.\n * I.e. success results in a zero value.\n * Negative error values are not returned.\n */\nunsigned long\ncopy_from_user(void *to, const void *from, unsigned long n)\n{\n\tif (copyin(from, to, n) != 0) {\n\t\t/* Any errors will be treated as a failure\n\t\t   to copy any of the requested bytes */\n\t\treturn n;\n\t}\n\n\treturn 0;\n}\n\nunsigned long\ncopy_to_user(void *to, const void *from, unsigned long n)\n{\n\tif (copyout(from, to, n) != 0) {\n\t\t/* Any errors will be treated as a failure\n\t\t   to copy any of the requested bytes */\n\t\treturn n;\n\t}\n\n\treturn 0;\n}\n\n\n/*\n * The usb_register and usb_deregister functions are used to register\n * usb drivers with the usb subsystem. In this compatibility layer\n * emulation a list of drivers (struct usb_driver) is maintained\n * and is used for probing/attaching etc.\n *\n * usb_register and usb_deregister simply call these functions.\n */\nint\nusb_register(struct usb_driver *driver)\n{\n\trtw_usb_linux_register(driver);\n\treturn 0;\n}\n\n\nint\nusb_deregister(struct usb_driver *driver)\n{\n\trtw_usb_linux_deregister(driver);\n\treturn 0;\n}\n\nvoid module_init_exit_wrapper(void *arg)\n{\n\tint (*func)(void) = arg;\n\tfunc();\n\treturn;\n}\n\n#endif /* PLATFORM_FREEBSD */\n\n#ifdef CONFIG_PLATFORM_SPRD\n\t#ifdef do_div\n\t\t#undef do_div\n\t#endif\n\t#include <asm-generic/div64.h>\n#endif\n\nu64 rtw_modular64(u64 x, u64 y)\n{\n#ifdef PLATFORM_LINUX\n\treturn do_div(x, y);\n#elif defined(PLATFORM_WINDOWS)\n\treturn x % y;\n#elif defined(PLATFORM_FREEBSD)\n\treturn x % y;\n#endif\n}\n\nu64 rtw_division64(u64 x, u64 y)\n{\n#ifdef PLATFORM_LINUX\n\tdo_div(x, y);\n\treturn x;\n#elif defined(PLATFORM_WINDOWS)\n\treturn x / y;\n#elif defined(PLATFORM_FREEBSD)\n\treturn x / y;\n#endif\n}\n\ninline u32 rtw_random32(void)\n{\n#ifdef PLATFORM_LINUX\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0))\n\treturn get_random_u32();\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))\n\treturn prandom_u32();\n#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 18))\n\tu32 random_int;\n\tget_random_bytes(&random_int , 4);\n\treturn random_int;\n#else\n\treturn random32();\n#endif\n#elif defined(PLATFORM_WINDOWS)\n#error \"to be implemented\\n\"\n#elif defined(PLATFORM_FREEBSD)\n#error \"to be implemented\\n\"\n#endif\n}\n\nvoid rtw_buf_free(u8 **buf, u32 *buf_len)\n{\n\tu32 ori_len;\n\n\tif (!buf || !buf_len)\n\t\treturn;\n\n\tori_len = *buf_len;\n\n\tif (*buf) {\n\t\tu32 tmp_buf_len = *buf_len;\n\t\t*buf_len = 0;\n\t\trtw_mfree(*buf, tmp_buf_len);\n\t\t*buf = NULL;\n\t}\n}\n\nvoid rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len)\n{\n\tu32 ori_len = 0, dup_len = 0;\n\tu8 *ori = NULL;\n\tu8 *dup = NULL;\n\n\tif (!buf || !buf_len)\n\t\treturn;\n\n\tif (!src || !src_len)\n\t\tgoto keep_ori;\n\n\t/* duplicate src */\n\tdup = rtw_malloc(src_len);\n\tif (dup) {\n\t\tdup_len = src_len;\n\t\t_rtw_memcpy(dup, src, dup_len);\n\t}\n\nkeep_ori:\n\tori = *buf;\n\tori_len = *buf_len;\n\n\t/* replace buf with dup */\n\t*buf_len = 0;\n\t*buf = dup;\n\t*buf_len = dup_len;\n\n\t/* free ori */\n\tif (ori && ori_len > 0)\n\t\trtw_mfree(ori, ori_len);\n}\n\n\n/**\n * rtw_cbuf_full - test if cbuf is full\n * @cbuf: pointer of struct rtw_cbuf\n *\n * Returns: _TRUE if cbuf is full\n */\ninline bool rtw_cbuf_full(struct rtw_cbuf *cbuf)\n{\n\treturn (cbuf->write == cbuf->read - 1) ? _TRUE : _FALSE;\n}\n\n/**\n * rtw_cbuf_empty - test if cbuf is empty\n * @cbuf: pointer of struct rtw_cbuf\n *\n * Returns: _TRUE if cbuf is empty\n */\ninline bool rtw_cbuf_empty(struct rtw_cbuf *cbuf)\n{\n\treturn (cbuf->write == cbuf->read) ? _TRUE : _FALSE;\n}\n\n/**\n * rtw_cbuf_push - push a pointer into cbuf\n * @cbuf: pointer of struct rtw_cbuf\n * @buf: pointer to push in\n *\n * Lock free operation, be careful of the use scheme\n * Returns: _TRUE push success\n */\nbool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf)\n{\n\tif (rtw_cbuf_full(cbuf))\n\t\treturn _FAIL;\n\n\tif (0)\n\t\tRTW_INFO(\"%s on %u\\n\", __func__, cbuf->write);\n\tcbuf->bufs[cbuf->write] = buf;\n\tcbuf->write = (cbuf->write + 1) % cbuf->size;\n\n\treturn _SUCCESS;\n}\n\n/**\n * rtw_cbuf_pop - pop a pointer from cbuf\n * @cbuf: pointer of struct rtw_cbuf\n *\n * Lock free operation, be careful of the use scheme\n * Returns: pointer popped out\n */\nvoid *rtw_cbuf_pop(struct rtw_cbuf *cbuf)\n{\n\tvoid *buf;\n\tif (rtw_cbuf_empty(cbuf))\n\t\treturn NULL;\n\n\tif (0)\n\t\tRTW_INFO(\"%s on %u\\n\", __func__, cbuf->read);\n\tbuf = cbuf->bufs[cbuf->read];\n\tcbuf->read = (cbuf->read + 1) % cbuf->size;\n\n\treturn buf;\n}\n\n/**\n * rtw_cbuf_alloc - allocte a rtw_cbuf with given size and do initialization\n * @size: size of pointer\n *\n * Returns: pointer of srtuct rtw_cbuf, NULL for allocation failure\n */\nstruct rtw_cbuf *rtw_cbuf_alloc(u32 size)\n{\n\tstruct rtw_cbuf *cbuf;\n\n\tcbuf = (struct rtw_cbuf *)rtw_malloc(sizeof(*cbuf) + sizeof(void *) * size);\n\n\tif (cbuf) {\n\t\tcbuf->write = cbuf->read = 0;\n\t\tcbuf->size = size;\n\t}\n\n\treturn cbuf;\n}\n\n/**\n * rtw_cbuf_free - free the given rtw_cbuf\n * @cbuf: pointer of struct rtw_cbuf to free\n */\nvoid rtw_cbuf_free(struct rtw_cbuf *cbuf)\n{\n\trtw_mfree((u8 *)cbuf, sizeof(*cbuf) + sizeof(void *) * cbuf->size);\n}\n\n/**\n * map_readN - read a range of map data\n * @map: map to read\n * @offset: start address to read\n * @len: length to read\n * @buf: pointer of buffer to store data read\n *\n * Returns: _SUCCESS or _FAIL\n */\nint map_readN(const struct map_t *map, u16 offset, u16 len, u8 *buf)\n{\n\tconst struct map_seg_t *seg;\n\tint ret = _FAIL;\n\tint i;\n\n\tif (len == 0) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tif (offset + len > map->len) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\t_rtw_memset(buf, map->init_value, len);\n\n\tfor (i = 0; i < map->seg_num; i++) {\n\t\tu8 *c_dst, *c_src;\n\t\tu16 c_len;\n\n\t\tseg = map->segs + i;\n\t\tif (seg->sa + seg->len <= offset || seg->sa >= offset + len)\n\t\t\tcontinue;\n\n\t\tif (seg->sa >= offset) {\n\t\t\tc_dst = buf + (seg->sa - offset);\n\t\t\tc_src = seg->c;\n\t\t\tif (seg->sa + seg->len <= offset + len)\n\t\t\t\tc_len = seg->len;\n\t\t\telse\n\t\t\t\tc_len = offset + len - seg->sa;\n\t\t} else {\n\t\t\tc_dst = buf;\n\t\t\tc_src = seg->c + (offset - seg->sa);\n\t\t\tif (seg->sa + seg->len >= offset + len)\n\t\t\t\tc_len = len;\n\t\t\telse\n\t\t\t\tc_len = seg->sa + seg->len - offset;\n\t\t}\n\t\t\t\n\t\t_rtw_memcpy(c_dst, c_src, c_len);\n\t}\n\nexit:\n\treturn ret;\n}\n\n/**\n * map_read8 - read 1 byte of map data\n * @map: map to read\n * @offset: address to read\n *\n * Returns: value of data of specified offset. map.init_value if offset is out of range\n */\nu8 map_read8(const struct map_t *map, u16 offset)\n{\n\tconst struct map_seg_t *seg;\n\tu8 val = map->init_value;\n\tint i;\n\n\tif (offset + 1 > map->len) {\n\t\trtw_warn_on(1);\n\t\tgoto exit;\n\t}\n\n\tfor (i = 0; i < map->seg_num; i++) {\n\t\tseg = map->segs + i;\n\t\tif (seg->sa + seg->len <= offset || seg->sa >= offset + 1)\n\t\t\tcontinue;\n\n\t\tval = *(seg->c + offset - seg->sa);\n\t\tbreak;\n\t}\n\nexit:\n\treturn val;\n}\n\nint rtw_blacklist_add(_queue *blist, const u8 *addr, u32 timeout_ms)\n{\n\tstruct blacklist_ent *ent;\n\t_list *list, *head;\n\tu8 exist = _FALSE, timeout = _FALSE;\n\n\tenter_critical_bh(&blist->lock);\n\n\thead = &blist->queue;\n\tlist = get_next(head);\n\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\tent = LIST_CONTAINOR(list, struct blacklist_ent, list);\n\t\tlist = get_next(list);\n\n\t\tif (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) {\n\t\t\texist = _TRUE;\n\t\t\tif (rtw_time_after(rtw_get_current_time(), ent->exp_time))\n\t\t\t\ttimeout = _TRUE;\n\t\t\tent->exp_time = rtw_get_current_time()\n\t\t\t\t+ rtw_ms_to_systime(timeout_ms);\n\t\t\tbreak;\n\t\t}\n\n\t\tif (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {\n\t\t\trtw_list_delete(&ent->list);\n\t\t\trtw_mfree(ent, sizeof(struct blacklist_ent));\n\t\t}\n\t}\n\n\tif (exist == _FALSE) {\n\t\tent = rtw_malloc(sizeof(struct blacklist_ent));\n\t\tif (ent) {\n\t\t\t_rtw_memcpy(ent->addr, addr, ETH_ALEN);\n\t\t\tent->exp_time = rtw_get_current_time()\n\t\t\t\t+ rtw_ms_to_systime(timeout_ms);\n\t\t\trtw_list_insert_tail(&ent->list, head);\n\t\t}\n\t}\n\n\texit_critical_bh(&blist->lock);\n\n\treturn (exist == _TRUE && timeout == _FALSE) ? RTW_ALREADY : (ent ? _SUCCESS : _FAIL);\n}\n\nint rtw_blacklist_del(_queue *blist, const u8 *addr)\n{\n\tstruct blacklist_ent *ent = NULL;\n\t_list *list, *head;\n\tu8 exist = _FALSE;\n\n\tenter_critical_bh(&blist->lock);\n\thead = &blist->queue;\n\tlist = get_next(head);\n\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\tent = LIST_CONTAINOR(list, struct blacklist_ent, list);\n\t\tlist = get_next(list);\n\n\t\tif (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) {\n\t\t\trtw_list_delete(&ent->list);\n\t\t\trtw_mfree(ent, sizeof(struct blacklist_ent));\n\t\t\texist = _TRUE;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {\n\t\t\trtw_list_delete(&ent->list);\n\t\t\trtw_mfree(ent, sizeof(struct blacklist_ent));\n\t\t}\n\t}\n\n\texit_critical_bh(&blist->lock);\n\n\treturn exist == _TRUE ? _SUCCESS : RTW_ALREADY;\n}\n\nint rtw_blacklist_search(_queue *blist, const u8 *addr)\n{\n\tstruct blacklist_ent *ent = NULL;\n\t_list *list, *head;\n\tu8 exist = _FALSE;\n\n\tenter_critical_bh(&blist->lock);\n\thead = &blist->queue;\n\tlist = get_next(head);\n\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\tent = LIST_CONTAINOR(list, struct blacklist_ent, list);\n\t\tlist = get_next(list);\n\n\t\tif (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) {\n\t\t\tif (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {\n\t\t\t\trtw_list_delete(&ent->list);\n\t\t\t\trtw_mfree(ent, sizeof(struct blacklist_ent));\n\t\t\t} else\n\t\t\t\texist = _TRUE;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {\n\t\t\trtw_list_delete(&ent->list);\n\t\t\trtw_mfree(ent, sizeof(struct blacklist_ent));\n\t\t}\n\t}\n\n\texit_critical_bh(&blist->lock);\n\n\treturn exist;\n}\n\nvoid rtw_blacklist_flush(_queue *blist)\n{\n\tstruct blacklist_ent *ent;\n\t_list *list, *head;\n\t_list tmp;\n\n\t_rtw_init_listhead(&tmp);\n\n\tenter_critical_bh(&blist->lock);\n\trtw_list_splice_init(&blist->queue, &tmp);\n\texit_critical_bh(&blist->lock);\n\n\thead = &tmp;\n\tlist = get_next(head);\n\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\tent = LIST_CONTAINOR(list, struct blacklist_ent, list);\n\t\tlist = get_next(list);\n\t\trtw_list_delete(&ent->list);\n\t\trtw_mfree(ent, sizeof(struct blacklist_ent));\n\t}\n}\n\nvoid dump_blacklist(void *sel, _queue *blist, const char *title)\n{\n\tstruct blacklist_ent *ent = NULL;\n\t_list *list, *head;\n\n\tenter_critical_bh(&blist->lock);\n\thead = &blist->queue;\n\tlist = get_next(head);\n\n\tif (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\tif (title)\n\t\t\tRTW_PRINT_SEL(sel, \"%s:\\n\", title);\n\t\n\t\twhile (rtw_end_of_queue_search(head, list) == _FALSE) {\n\t\t\tent = LIST_CONTAINOR(list, struct blacklist_ent, list);\n\t\t\tlist = get_next(list);\n\n\t\t\tif (rtw_time_after(rtw_get_current_time(), ent->exp_time))\n\t\t\t\tRTW_PRINT_SEL(sel, MAC_FMT\" expired\\n\", MAC_ARG(ent->addr));\n\t\t\telse\n\t\t\t\tRTW_PRINT_SEL(sel, MAC_FMT\" %u\\n\", MAC_ARG(ent->addr)\n\t\t\t\t\t, rtw_get_remaining_time_ms(ent->exp_time));\n\t\t}\n\n\t}\n\texit_critical_bh(&blist->lock);\n}\n\n/**\n* is_null -\n*\n* Return\tTRUE if c is null character\n*\t\tFALSE otherwise.\n*/\ninline BOOLEAN is_null(char c)\n{\n\tif (c == '\\0')\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\n\ninline BOOLEAN is_all_null(char *c, int len)\n{\n\tfor (; len > 0; len--)\n\t\tif (c[len - 1] != '\\0')\n\t\t\treturn _FALSE;\n\n\treturn _TRUE;\n}\n\n/**\n* is_eol -\n*\n* Return\tTRUE if c is represent for EOL (end of line)\n*\t\tFALSE otherwise.\n*/\ninline BOOLEAN is_eol(char c)\n{\n\tif (c == '\\r' || c == '\\n')\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\n\n/**\n* is_space -\n*\n* Return\tTRUE if c is represent for space\n*\t\tFALSE otherwise.\n*/\ninline BOOLEAN is_space(char c)\n{\n\tif (c == ' ' || c == '\\t')\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\n\n/**\n* IsHexDigit -\n*\n* Return\tTRUE if chTmp is represent for hex digit\n*\t\tFALSE otherwise.\n*/\ninline BOOLEAN IsHexDigit(char chTmp)\n{\n\tif ((chTmp >= '0' && chTmp <= '9') ||\n\t\t(chTmp >= 'a' && chTmp <= 'f') ||\n\t\t(chTmp >= 'A' && chTmp <= 'F'))\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\n\n/**\n* is_alpha -\n*\n* Return\tTRUE if chTmp is represent for alphabet\n*\t\tFALSE otherwise.\n*/\ninline BOOLEAN is_alpha(char chTmp)\n{\n\tif ((chTmp >= 'a' && chTmp <= 'z') ||\n\t\t(chTmp >= 'A' && chTmp <= 'Z'))\n\t\treturn _TRUE;\n\telse\n\t\treturn _FALSE;\n}\n\ninline char alpha_to_upper(char c)\n{\n\tif ((c >= 'a' && c <= 'z'))\n\t\tc = 'A' + (c - 'a');\n\treturn c;\n}\n\nint hex2num_i(char c)\n{\n\tif (c >= '0' && c <= '9')\n\t\treturn c - '0';\n\tif (c >= 'a' && c <= 'f')\n\t\treturn c - 'a' + 10;\n\tif (c >= 'A' && c <= 'F')\n\t\treturn c - 'A' + 10;\n\treturn -1;\n}\n\nint hex2byte_i(const char *hex)\n{\n\tint a, b;\n\ta = hex2num_i(*hex++);\n\tif (a < 0)\n\t\treturn -1;\n\tb = hex2num_i(*hex++);\n\tif (b < 0)\n\t\treturn -1;\n\treturn (a << 4) | b;\n}\n\nint hexstr2bin(const char *hex, u8 *buf, size_t len)\n{\n\tsize_t i;\n\tint a;\n\tconst char *ipos = hex;\n\tu8 *opos = buf;\n\n\tfor (i = 0; i < len; i++) {\n\t\ta = hex2byte_i(ipos);\n\t\tif (a < 0)\n\t\t\treturn -1;\n\t\t*opos++ = a;\n\t\tipos += 2;\n\t}\n\treturn 0;\n}\n\n"
  },
  {
    "path": "platform/custom_country_chplan.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n\n#error \"You have defined CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP to use a customized map of your own instead of the default one\"\n#error \"Before removing these error notifications, please make sure regulatory certification requirements of your target markets\"\n\nstatic const struct country_chplan CUSTOMIZED_country_chplan_map[] = {\n\tCOUNTRY_CHPLAN_ENT(\"TW\", 0x76, 1, 0x3FF), /* Taiwan */\n};\n\n"
  },
  {
    "path": "platform/platform_ARM_SUN50IW1P1_sdio.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n/*\n * Description:\n *\tThis file can be applied to following platforms:\n *\tCONFIG_PLATFORM_ARM_SUN50IW1P1\n */\n#include <drv_types.h>\n#ifdef CONFIG_GPIO_WAKEUP\n#include <linux/gpio.h>\n#endif\n\n#ifdef CONFIG_MMC\n#if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)\nextern void sunxi_mmc_rescan_card(unsigned ids);\nextern void sunxi_wlan_set_power(int on);\nextern int sunxi_wlan_get_bus_index(void);\nextern int sunxi_wlan_get_oob_irq(void);\nextern int sunxi_wlan_get_oob_irq_flags(void);\n#endif\n#ifdef CONFIG_GPIO_WAKEUP\nextern unsigned int oob_irq;\n#endif\n#endif /* CONFIG_MMC */\n\n/*\n * Return:\n *\t0:\tpower on successfully\n *\tothers: power on failed\n */\nint platform_wifi_power_on(void)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_MMC\n\t{\n\n#if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)\n\t\tint wlan_bus_index = sunxi_wlan_get_bus_index();\n\t\tif (wlan_bus_index < 0)\n\t\t\treturn wlan_bus_index;\n\n\t\tsunxi_wlan_set_power(1);\n\t\tmdelay(100);\n\t\tsunxi_mmc_rescan_card(wlan_bus_index);\n#endif\n\t\tRTW_INFO(\"%s: power up, rescan card.\\n\", __FUNCTION__);\n\n#ifdef CONFIG_GPIO_WAKEUP\n#if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)\n\t\toob_irq = sunxi_wlan_get_oob_irq();\n#endif\n#endif /* CONFIG_GPIO_WAKEUP */\n\t}\n#endif /* CONFIG_MMC */\n\n\treturn ret;\n}\n\nvoid platform_wifi_power_off(void)\n{\n#ifdef CONFIG_MMC\n#if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)\n\tint wlan_bus_index = sunxi_wlan_get_bus_index();\n\tif (wlan_bus_index < 0)\n\t\treturn;\n\n\tsunxi_mmc_rescan_card(wlan_bus_index);\n\tmdelay(100);\n\tsunxi_wlan_set_power(0);\n#endif\n\tRTW_INFO(\"%s: remove card, power off.\\n\", __FUNCTION__);\n#endif /* CONFIG_MMC */\n}\n"
  },
  {
    "path": "platform/platform_ARM_SUNnI_sdio.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n/*\n * Description:\n *\tThis file can be applied to following platforms:\n *\tCONFIG_PLATFORM_ARM_SUN6I\n *\tCONFIG_PLATFORM_ARM_SUN7I\n *\tCONFIG_PLATFORM_ARM_SUN8I\n */\n#include <drv_types.h>\n#include <mach/sys_config.h>\n#ifdef CONFIG_GPIO_WAKEUP\n#include <linux/gpio.h>\n#endif\n\n#ifdef CONFIG_MMC\nstatic int sdc_id = -1;\nstatic signed int gpio_eint_wlan = -1;\nstatic u32 eint_wlan_handle = 0;\n\n#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)\nextern void sw_mci_rescan_card(unsigned id, unsigned insert);\n#elif defined(CONFIG_PLATFORM_ARM_SUN8I)\nextern void sunxi_mci_rescan_card(unsigned id, unsigned insert);\n#endif\n\n#ifdef CONFIG_PLATFORM_ARM_SUN8I_W5P1\nextern int get_rf_mod_type(void);\n#else\nextern int wifi_pm_get_mod_type(void);\n#endif\n\nextern void wifi_pm_power(int on);\n#ifdef CONFIG_GPIO_WAKEUP\nextern unsigned int oob_irq;\n#endif\n#endif /* CONFIG_MMC */\n\n/*\n * Return:\n *\t0:\tpower on successfully\n *\tothers: power on failed\n */\nint platform_wifi_power_on(void)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_MMC\n\t{\n\t\tscript_item_u val;\n\t\tscript_item_value_type_e type;\n\n#ifdef CONFIG_PLATFORM_ARM_SUN8I_W5P1\n\t\tunsigned int mod_sel = get_rf_mod_type();\n#else\n\t\tunsigned int mod_sel = wifi_pm_get_mod_type();\n#endif\n\n\t\ttype = script_get_item(\"wifi_para\", \"wifi_sdc_id\", &val);\n\t\tif (SCIRPT_ITEM_VALUE_TYPE_INT != type) {\n\t\t\tRTW_INFO(\"get wifi_sdc_id failed\\n\");\n\t\t\tret = -1;\n\t\t} else {\n\t\t\tsdc_id = val.val;\n\t\t\tRTW_INFO(\"----- %s sdc_id: %d, mod_sel: %d\\n\", __FUNCTION__, sdc_id, mod_sel);\n\n#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)\n\t\t\tsw_mci_rescan_card(sdc_id, 1);\n#elif defined(CONFIG_PLATFORM_ARM_SUN8I)\n\t\t\tsunxi_mci_rescan_card(sdc_id, 1);\n#endif\n\t\t\tmdelay(100);\n\t\t\twifi_pm_power(1);\n\n\t\t\tRTW_INFO(\"%s: power up, rescan card.\\n\", __FUNCTION__);\n\t\t}\n\n#ifdef CONFIG_GPIO_WAKEUP\n#ifdef CONFIG_PLATFORM_ARM_SUN8I_W5P1\n\t\ttype = script_get_item(\"wifi_para\", \"wl_host_wake\", &val);\n#else\n#ifdef CONFIG_RTL8723B\n\t\ttype = script_get_item(\"wifi_para\", \"rtl8723bs_wl_host_wake\", &val);\n#endif\n#ifdef CONFIG_RTL8188E\n\t\ttype = script_get_item(\"wifi_para\", \"rtl8189es_host_wake\", &val);\n#endif\n#endif /* CONFIG_PLATFORM_ARM_SUN8I_W5P1 */\n\t\tif (SCIRPT_ITEM_VALUE_TYPE_PIO != type) {\n\t\t\tRTW_INFO(\"No definition of wake up host PIN\\n\");\n\t\t\tret = -1;\n\t\t} else {\n\t\t\tgpio_eint_wlan = val.gpio.gpio;\n#ifdef CONFIG_PLATFORM_ARM_SUN8I\n\t\t\toob_irq = gpio_to_irq(gpio_eint_wlan);\n#endif\n\t\t}\n#endif /* CONFIG_GPIO_WAKEUP */\n\t}\n#endif /* CONFIG_MMC */\n\n\treturn ret;\n}\n\nvoid platform_wifi_power_off(void)\n{\n#ifdef CONFIG_MMC\n#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)\n\tsw_mci_rescan_card(sdc_id, 0);\n#elif defined(CONFIG_PLATFORM_ARM_SUN8I)\n\tsunxi_mci_rescan_card(sdc_id, 0);\n#endif\n\tmdelay(100);\n\twifi_pm_power(0);\n\n\tRTW_INFO(\"%s: remove card, power off.\\n\", __FUNCTION__);\n#endif /* CONFIG_MMC */\n}\n"
  },
  {
    "path": "platform/platform_ARM_SUNxI_sdio.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#include <drv_types.h>\n\n#ifdef CONFIG_MMC_SUNXI_POWER_CONTROL\n#ifdef CONFIG_WITS_EVB_V13\n\t#define SDIOID\t0\n#else /* !CONFIG_WITS_EVB_V13 */\n\t#define SDIOID (CONFIG_CHIP_ID == 1123 ? 3 : 1)\n#endif /* !CONFIG_WITS_EVB_V13 */\n\n#define SUNXI_SDIO_WIFI_NUM_RTL8189ES  10\nextern void sunximmc_rescan_card(unsigned id, unsigned insert);\nextern int mmc_pm_get_mod_type(void);\nextern int mmc_pm_gpio_ctrl(char *name, int level);\n/*\n *\trtl8189es_shdn\t= port:PH09<1><default><default><0>\n *\trtl8189es_wakeup\t= port:PH10<1><default><default><1>\n *\trtl8189es_vdd_en  = port:PH11<1><default><default><0>\n *\trtl8189es_vcc_en  = port:PH12<1><default><default><0>\n */\n\nint rtl8189es_sdio_powerup(void)\n{\n\tmmc_pm_gpio_ctrl(\"rtl8189es_vdd_en\", 1);\n\tudelay(100);\n\tmmc_pm_gpio_ctrl(\"rtl8189es_vcc_en\", 1);\n\tudelay(50);\n\tmmc_pm_gpio_ctrl(\"rtl8189es_shdn\", 1);\n\treturn 0;\n}\n\nint rtl8189es_sdio_poweroff(void)\n{\n\tmmc_pm_gpio_ctrl(\"rtl8189es_shdn\", 0);\n\tmmc_pm_gpio_ctrl(\"rtl8189es_vcc_en\", 0);\n\tmmc_pm_gpio_ctrl(\"rtl8189es_vdd_en\", 0);\n\treturn 0;\n}\n#endif /* CONFIG_MMC_SUNXI_POWER_CONTROL */\n\n/*\n * Return:\n *\t0:\tpower on successfully\n *\tothers:\tpower on failed\n */\nint platform_wifi_power_on(void)\n{\n\tint ret = 0;\n#ifdef CONFIG_MMC_SUNXI_POWER_CONTROL\n\tunsigned int mod_sel = mmc_pm_get_mod_type();\n#endif /* CONFIG_MMC_SUNXI_POWER_CONTROL */\n\n\n#ifdef CONFIG_MMC_SUNXI_POWER_CONTROL\n\tif (mod_sel == SUNXI_SDIO_WIFI_NUM_RTL8189ES) {\n\t\trtl8189es_sdio_powerup();\n\t\tsunximmc_rescan_card(SDIOID, 1);\n\t\tprintk(\"[rtl8189es] %s: power up, rescan card.\\n\", __FUNCTION__);\n\t} else {\n\t\tret = -1;\n\t\tprintk(\"[rtl8189es] %s: mod_sel = %d is incorrect.\\n\", __FUNCTION__, mod_sel);\n\t}\n#endif /* CONFIG_MMC_SUNXI_POWER_CONTROL */\n\n\treturn ret;\n}\n\nvoid platform_wifi_power_off(void)\n{\n#ifdef CONFIG_MMC_SUNXI_POWER_CONTROL\n\tsunximmc_rescan_card(SDIOID, 0);\n#ifdef CONFIG_RTL8188E\n\trtl8189es_sdio_poweroff();\n\tprintk(\"[rtl8189es] %s: remove card, power off.\\n\", __FUNCTION__);\n#endif /* CONFIG_RTL8188E */\n#endif /* CONFIG_MMC_SUNXI_POWER_CONTROL */\n}\n"
  },
  {
    "path": "platform/platform_ARM_SUNxI_usb.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n/*\n * Description:\n *\tThis file can be applied to following platforms:\n *\tCONFIG_PLATFORM_ARM_SUNXI Series platform\n *\n */\n\n#include <drv_types.h>\n#include <mach/sys_config.h>\n\n#ifdef CONFIG_PLATFORM_ARM_SUNxI\nextern int sw_usb_disable_hcd(__u32 usbc_no);\nextern int sw_usb_enable_hcd(__u32 usbc_no);\nstatic int usb_wifi_host = 2;\n#endif\n\n#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)\nextern int sw_usb_disable_hcd(__u32 usbc_no);\nextern int sw_usb_enable_hcd(__u32 usbc_no);\nextern void wifi_pm_power(int on);\nstatic script_item_u item;\n#endif\n\n#ifdef CONFIG_PLATFORM_ARM_SUN8I\nextern int sunxi_usb_disable_hcd(__u32 usbc_no);\nextern int sunxi_usb_enable_hcd(__u32 usbc_no);\nextern void wifi_pm_power(int on);\nstatic script_item_u item;\n#endif\n\n\nint platform_wifi_power_on(void)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_PLATFORM_ARM_SUNxI\n#ifndef CONFIG_RTL8723A\n\t{\n\t\t/* ----------get usb_wifi_usbc_num------------- */\n\t\tret = script_parser_fetch(\"usb_wifi_para\", \"usb_wifi_usbc_num\", (int *)&usb_wifi_host, 64);\n\t\tif (ret != 0) {\n\t\t\tRTW_INFO(\"ERR: script_parser_fetch usb_wifi_usbc_num failed\\n\");\n\t\t\tret = -ENOMEM;\n\t\t\tgoto exit;\n\t\t}\n\t\tRTW_INFO(\"sw_usb_enable_hcd: usbc_num = %d\\n\", usb_wifi_host);\n\t\tsw_usb_enable_hcd(usb_wifi_host);\n\t}\n#endif /* CONFIG_RTL8723A */\n#endif /* CONFIG_PLATFORM_ARM_SUNxI */\n\n#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)\n\t{\n\t\tscript_item_value_type_e type;\n\n\t\ttype = script_get_item(\"wifi_para\", \"wifi_usbc_id\", &item);\n\t\tif (SCIRPT_ITEM_VALUE_TYPE_INT != type) {\n\t\t\tprintk(\"ERR: script_get_item wifi_usbc_id failed\\n\");\n\t\t\tret = -ENOMEM;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tprintk(\"sw_usb_enable_hcd: usbc_num = %d\\n\", item.val);\n\t\twifi_pm_power(1);\n\t\tmdelay(10);\n\n#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B))\n\t\tsw_usb_enable_hcd(item.val);\n#endif\n\t}\n#endif /* defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) */\n\n#if defined(CONFIG_PLATFORM_ARM_SUN8I)\n\t{\n\t\tscript_item_value_type_e type;\n\n\t\ttype = script_get_item(\"wifi_para\", \"wifi_usbc_id\", &item);\n\t\tif (SCIRPT_ITEM_VALUE_TYPE_INT != type) {\n\t\t\tprintk(\"ERR: script_get_item wifi_usbc_id failed\\n\");\n\t\t\tret = -ENOMEM;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tprintk(\"sw_usb_enable_hcd: usbc_num = %d\\n\", item.val);\n\t\twifi_pm_power(1);\n\t\tmdelay(10);\n\n#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B))\n\t\tsunxi_usb_enable_hcd(item.val);\n#endif\n\t}\n#endif /* CONFIG_PLATFORM_ARM_SUN8I */\n\nexit:\n\treturn ret;\n}\n\nvoid platform_wifi_power_off(void)\n{\n\n#ifdef CONFIG_PLATFORM_ARM_SUNxI\n#ifndef CONFIG_RTL8723A\n\tRTW_INFO(\"sw_usb_disable_hcd: usbc_num = %d\\n\", usb_wifi_host);\n\tsw_usb_disable_hcd(usb_wifi_host);\n#endif /* ifndef CONFIG_RTL8723A */\n#endif /* CONFIG_PLATFORM_ARM_SUNxI */\n\n#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)\n\t#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B))\n\tsw_usb_disable_hcd(item.val);\n\t#endif\n\twifi_pm_power(0);\n#endif /* defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) */\n\n#if defined(CONFIG_PLATFORM_ARM_SUN8I)\n\t#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B))\n\tsunxi_usb_disable_hcd(item.val);\n\t#endif\n\twifi_pm_power(0);\n#endif /* defined(CONFIG_PLATFORM_ARM_SUN8I) */\n\n}\n"
  },
  {
    "path": "platform/platform_ARM_WMT_sdio.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#include <drv_types.h>\n#include <mach/wmt_iomux.h>\n#include <linux/gpio.h>\n\nextern void wmt_detect_sdio2(void);\nextern void force_remove_sdio2(void);\n\nint platform_wifi_power_on(void)\n{\n\tint err = 0;\n\terr = gpio_request(WMT_PIN_GP62_SUSGPIO1, \"wifi_chip_en\");\n\tif (err < 0) {\n\t\tprintk(\"request gpio for rtl8188eu failed!\\n\");\n\t\treturn err;\n\t}\n\tgpio_direction_output(WMT_PIN_GP62_SUSGPIO1, 0);/* pull sus_gpio1 to 0 to open vcc_wifi. */\n\tprintk(\"power on rtl8189.\\n\");\n\tmsleep(500);\n\twmt_detect_sdio2();\n\tprintk(\"[rtl8189es] %s: new card, power on.\\n\", __FUNCTION__);\n\treturn err;\n}\n\nvoid platform_wifi_power_off(void)\n{\n\tforce_remove_sdio2();\n\n\tgpio_direction_output(WMT_PIN_GP62_SUSGPIO1, 1);/* pull sus_gpio1 to 1 to close vcc_wifi. */\n\tprintk(\"power off rtl8189.\\n\");\n\tgpio_free(WMT_PIN_GP62_SUSGPIO1);\n\tprintk(\"[rtl8189es] %s: remove card, power off.\\n\", __FUNCTION__);\n}\n"
  },
  {
    "path": "platform/platform_RTK_DMP_usb.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#include <drv_types.h>\n\nint platform_wifi_power_on(void)\n{\n\tint ret = 0;\n\tu32 tmp;\n\ttmp = readl((volatile unsigned int *)0xb801a608);\n\ttmp &= 0xffffff00;\n\ttmp |= 0x55;\n\twritel(tmp, (volatile unsigned int *)0xb801a608); /* write dummy register for 1055 */\n\treturn ret;\n}\n\nvoid platform_wifi_power_off(void)\n{\n}\n"
  },
  {
    "path": "platform/platform_aml_s905_sdio.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#include <linux/printk.h>\t\t/* pr_info(() */\n#include <linux/delay.h>\t\t/* msleep() */\n#include \"platform_aml_s905_sdio.h\"\t/* sdio_reinit() and etc */\n\n\n/*\n * Return:\n *\t0:\tpower on successfully\n *\tothers:\tpower on failed\n */\nint platform_wifi_power_on(void)\n{\n\tint ret = 0;\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))\n\tret = wifi_setup_dt();\n\tif (ret) {\n\t\tpr_err(\"%s: setup dt failed!!(%d)\\n\", __func__, ret);\n\t\treturn -1;\n\t}\n#endif /* kernel < 3.14.0 */\n\n#if 0 /* Seems redundancy? Already done before insert driver */\n\tpr_info(\"######%s:\\n\", __func__);\n\textern_wifi_set_enable(0);\n\tmsleep(500);\n\textern_wifi_set_enable(1);\n\tmsleep(500);\n\tsdio_reinit();\n#endif\n\n\treturn ret;\n}\n\nvoid platform_wifi_power_off(void)\n{\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))\n\twifi_teardown_dt();\n#endif /* kernel < 3.14.0 */\n}\n"
  },
  {
    "path": "platform/platform_aml_s905_sdio.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __PLATFORM_AML_S905_SDIO_H__\n#define __PLATFORM_AML_S905_SDIO_H__\n\n#include <linux/version.h>\t/* Linux vresion */\n\nextern void sdio_reinit(void);\nextern void extern_wifi_set_enable(int is_on);\n\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))\nextern void wifi_teardown_dt(void);\nextern int wifi_setup_dt(void);\n#endif /* kernel < 3.14.0 */\n\n#endif /* __PLATFORM_AML_S905_SDIO_H__ */\n"
  },
  {
    "path": "platform/platform_arm_act_sdio.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n/*\n * Description:\n *\tThis file can be applied to following platforms:\n *    CONFIG_PLATFORM_ACTIONS_ATM703X\n */\n#include <drv_types.h>\n\n#ifdef CONFIG_PLATFORM_ACTIONS_ATM705X\nextern int acts_wifi_init(void);\nextern void acts_wifi_cleanup(void);\n#endif\n\n/*\n * Return:\n *\t0:\tpower on successfully\n *\tothers: power on failed\n */\nint platform_wifi_power_on(void)\n{\n\tint ret = 0;\n\n#ifdef CONFIG_PLATFORM_ACTIONS_ATM705X\n\tret = acts_wifi_init();\n\tif (unlikely(ret < 0)) {\n\t\tpr_err(\"%s Failed to register the power control driver.\\n\", __FUNCTION__);\n\t\tgoto exit;\n\t}\n#endif\n\nexit:\n\treturn ret;\n}\n\nvoid platform_wifi_power_off(void)\n{\n#ifdef CONFIG_PLATFORM_ACTIONS_ATM705X\n\tacts_wifi_cleanup();\n#endif\n}\n"
  },
  {
    "path": "platform/platform_hisilicon_hi3798_sdio.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#include <linux/delay.h>\t\t/* mdelay() */\n#include <mach/hardware.h>\t\t/* __io_address(), readl(), writel() */\n#include \"platform_hisilicon_hi3798_sdio.h\"\t/* HI_S32() and etc. */\n\ntypedef enum hi_GPIO_DIR_E {\n\tHI_DIR_OUT = 0,\n\tHI_DIR_IN  = 1,\n} HI_GPIO_DIR_E;\n\n#define RTL_REG_ON_GPIO\t\t(4*8 + 3)\n\n#define REG_BASE_CTRL\t\t__io_address(0xf8a20008)\n\nint gpio_wlan_reg_on = RTL_REG_ON_GPIO;\n#if 0\nmodule_param(gpio_wlan_reg_on, uint, 0644);\nMODULE_PARM_DESC(gpio_wlan_reg_on, \"wlan reg_on gpio num (default:gpio4_3)\");\n#endif\n\nstatic int hi_gpio_set_value(u32 gpio, u32 value)\n{\n\tHI_S32 s32Status;\n\n\ts32Status = HI_DRV_GPIO_SetDirBit(gpio, HI_DIR_OUT);\n\tif (s32Status != HI_SUCCESS) {\n\t\tpr_err(\"gpio(%d) HI_DRV_GPIO_SetDirBit HI_DIR_OUT failed\\n\",\n\t\t\tgpio);\n\t\treturn -1;\n\t}\n\n\ts32Status = HI_DRV_GPIO_WriteBit(gpio, value);\n\tif (s32Status != HI_SUCCESS) {\n\t\tpr_err(\"gpio(%d) HI_DRV_GPIO_WriteBit value(%d) failed\\n\",\n\t\t\tgpio, value);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int hisi_wlan_set_carddetect(bool present)\n{\n\tu32 regval;\n\tu32 mask;\n\n\n#ifndef CONFIG_HISI_SDIO_ID\n\treturn;\n#endif\n\tpr_info(\"SDIO ID=%d\\n\", CONFIG_HISI_SDIO_ID);\n#if (CONFIG_HISI_SDIO_ID == 1)\n\tmask = 1;\n#elif (CONFIG_HISI_SDIO_ID == 0)\n\tmask = 2;\n#endif\n\n\tregval = readl(REG_BASE_CTRL);\n\tif (present) {\n\t\tpr_info(\"====== Card detection to detect SDIO card! ======\\n\");\n\t\t/* set card_detect low to detect card */\n\t\tregval |= mask;\n\t} else {\n\t\tpr_info(\"====== Card detection to remove SDIO card! ======\\n\");\n\t\t/* set card_detect high to remove card */\n\t\tregval &= ~(mask);\n\t}\n\twritel(regval, REG_BASE_CTRL);\n\n\treturn 0;\n}\n\n/*\n * Return:\n *\t0:\tpower on successfully\n *\tothers: power on failed\n */\nint platform_wifi_power_on(void)\n{\n\tint ret = 0;\n\n\n\thi_gpio_set_value(gpio_wlan_reg_on, 1);\n\tmdelay(100);\n\thisi_wlan_set_carddetect(1);\n\tmdelay(2000);\n\tpr_info(\"======== set_carddetect delay 2s! ========\\n\");\n\n\treturn ret;\n}\n\nvoid platform_wifi_power_off(void)\n{\n\thisi_wlan_set_carddetect(0);\n\tmdelay(100);\n\thi_gpio_set_value(gpio_wlan_reg_on, 0);\n}\n"
  },
  {
    "path": "platform/platform_hisilicon_hi3798_sdio.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2017 - 2018 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __PLATFORM_HISILICON_HI3798_SDIO_H__\n#define __PLATFORM_HISILICON_HI3798_SDIO_H__\n\ntypedef unsigned int\tHI_U32;\n\ntypedef int\t\tHI_S32;\n\n#define HI_SUCCESS\t0\n#define HI_FAILURE\t(-1)\n\nextern HI_S32 HI_DRV_GPIO_SetDirBit(HI_U32 u32GpioNo, HI_U32 u32DirBit);\nextern HI_S32 HI_DRV_GPIO_WriteBit(HI_U32 u32GpioNo, HI_U32 u32BitValue);\n\n#endif /* __PLATFORM_HISILICON_HI3798_SDIO_H__ */\n"
  },
  {
    "path": "platform/platform_ops.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef CONFIG_PLATFORM_OPS\n/*\n * Return:\n *\t0:\tpower on successfully\n *\tothers: power on failed\n */\nint platform_wifi_power_on(void)\n{\n\tint ret = 0;\n\n\n\treturn ret;\n}\n\nvoid platform_wifi_power_off(void)\n{\n}\n#endif /* !CONFIG_PLATFORM_OPS */\n"
  },
  {
    "path": "platform/platform_ops.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __PLATFORM_OPS_H__\n#define __PLATFORM_OPS_H__\n\n/*\n * Return:\n *\t0:\tpower on successfully\n *\tothers: power on failed\n */\nint platform_wifi_power_on(void);\nvoid platform_wifi_power_off(void);\n\n#endif /* __PLATFORM_OPS_H__ */\n"
  },
  {
    "path": "platform/platform_sprd_sdio.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2013 - 2017 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#include <drv_types.h>\n\nextern void sdhci_bus_scan(void);\n#ifndef ANDROID_2X\nextern int sdhci_device_attached(void);\n#endif\n\n/*\n * Return:\n *\t0:\tpower on successfully\n *\tothers:\tpower on failed\n */\nint platform_wifi_power_on(void)\n{\n\tint ret = 0;\n\n\n#ifdef CONFIG_RTL8188E\n\trtw_wifi_gpio_wlan_ctrl(WLAN_POWER_ON);\n#endif /* CONFIG_RTL8188E */\n\n\t/* Pull up pwd pin, make wifi leave power down mode. */\n\trtw_wifi_gpio_init();\n\trtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_ON);\n\n#if (MP_DRIVER == 1) && (defined(CONFIG_RTL8723A) || defined(CONFIG_RTL8723B))\n\t/* Pull up BT reset pin. */\n\trtw_wifi_gpio_wlan_ctrl(WLAN_BT_PWDN_ON);\n#endif\n\trtw_mdelay_os(5);\n\n\tsdhci_bus_scan();\n#ifdef CONFIG_RTL8723B\n\t/* YJ,test,130305 */\n\trtw_mdelay_os(1000);\n#endif\n#ifdef ANDROID_2X\n\trtw_mdelay_os(200);\n#else /* !ANDROID_2X */\n\tif (1) {\n\t\tint i = 0;\n\n\t\tfor (i = 0; i <= 50; i++) {\n\t\t\tmsleep(10);\n\t\t\tif (sdhci_device_attached())\n\t\t\t\tbreak;\n\t\t\tprintk(\"%s delay times:%d\\n\", __func__, i);\n\t\t}\n\t}\n#endif /* !ANDROID_2X */\n\n\treturn ret;\n}\n\nvoid platform_wifi_power_off(void)\n{\n\t/* Pull down pwd pin, make wifi enter power down mode. */\n\trtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_OFF);\n\trtw_mdelay_os(5);\n\trtw_wifi_gpio_deinit();\n\n#ifdef CONFIG_RTL8188E\n\trtw_wifi_gpio_wlan_ctrl(WLAN_POWER_OFF);\n#endif /* CONFIG_RTL8188E */\n\n#ifdef CONFIG_WOWLAN\n\tif (mmc_host)\n\t\tmmc_host->pm_flags &= ~MMC_PM_KEEP_POWER;\n#endif /* CONFIG_WOWLAN */\n}\n"
  },
  {
    "path": "platform/platform_zte_zx296716_sdio.c",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#include <linux/printk.h>\t\t/* pr_info(() */\n#include <linux/delay.h>\t\t/* msleep() */\n#include \"platform_zte_zx296716_sdio.h\"\t/* sdio_reinit() and etc */\n\n\n/*\n * Return:\n *\t0:\tpower on successfully\n *\tothers:\tpower on failed\n */\nint platform_wifi_power_on(void)\n{\n\tint ret = 0;\n\n\tpr_info(\"######%s: disable--1--\\n\", __func__);\n\textern_wifi_set_enable(0);\n\t/*msleep(500);*/ /* add in function:extern_wifi_set_enable */\n\tpr_info(\"######%s: enable--2---\\n\", __func__);\n\textern_wifi_set_enable(1);\n\t/*msleep(500);*/\n\tsdio_reinit();\n\n\treturn ret;\n}\n\nvoid platform_wifi_power_off(void)\n{\n\tint card_val;\n\n\tpr_info(\"######%s:\\n\", __func__);\n#ifdef CONFIG_A16T03_BOARD\n\tcard_val = sdio_host_is_null();\n\tif (card_val)\n\t\tremove_card();\n#endif /* CONFIG_A16T03_BOARD */\n\textern_wifi_set_enable(0);\n\n\t/*msleep(500);*/\n}\n"
  },
  {
    "path": "platform/platform_zte_zx296716_sdio.h",
    "content": "/******************************************************************************\n *\n * Copyright(c) 2016 - 2018 Realtek Corporation.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n * more details.\n *\n *****************************************************************************/\n#ifndef __PLATFORM_ZTE_ZX296716_SDIO_H__\n#define __PLATFORM_ZTE_ZX296716_SDIO_H__\n\nextern void sdio_reinit(void);\nextern void extern_wifi_set_enable(int val);\n#ifdef CONFIG_A16T03_BOARD\nextern int sdio_host_is_null(void);\nextern void remove_card(void);\n#endif /* CONFIG_A16T03_BOARD */\n\n#endif /* __PLATFORM_ZTE_ZX296716_SDIO_H__ */\n"
  },
  {
    "path": "rtl8822c.mk",
    "content": "EXTRA_CFLAGS += -DCONFIG_RTL8822C\n\nifeq ($(CONFIG_MP_INCLUDED), y)\n### 8822C Default Enable VHT MP HW TX MODE ###\n#EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE\n#CONFIG_MP_VHT_HW_TX_MODE = y\nendif\n\n_HAL_INTFS_FILES +=\thal/rtl8822c/rtl8822c_halinit.o \\\n\t\t\thal/rtl8822c/rtl8822c_mac.o \\\n\t\t\thal/rtl8822c/rtl8822c_cmd.o \\\n\t\t\thal/rtl8822c/rtl8822c_phy.o \\\n\t\t\thal/rtl8822c/rtl8822c_ops.o \\\n\t\t\thal/rtl8822c/hal8822c_fw.o\n\nifeq ($(CONFIG_USB_HCI), y)\n_HAL_INTFS_FILES +=\thal/rtl8822c/$(HCI_NAME)/rtl8822cu_halinit.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822cu_halmac.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822cu_io.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822cu_xmit.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822cu_recv.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822cu_led.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822cu_ops.o\n\n_HAL_INTFS_FILES +=hal/efuse/rtl8822c/HalEfuseMask8822C_USB.o\nendif\nifeq ($(CONFIG_PCI_HCI), y)\n_HAL_INTFS_FILES +=\thal/rtl8822c/$(HCI_NAME)/rtl8822ce_halinit.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822ce_halmac.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822ce_io.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822ce_xmit.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822ce_recv.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822ce_led.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822ce_ops.o\n\n_HAL_INTFS_FILES +=hal/efuse/rtl8822c/HalEfuseMask8822C_PCIE.o\nendif\nifeq ($(CONFIG_SDIO_HCI), y)\n_HAL_INTFS_FILES +=\thal/rtl8822c/$(HCI_NAME)/rtl8822cs_halinit.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822cs_halmac.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822cs_io.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822cs_xmit.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822cs_recv.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822cs_led.o \\\n\t\t\thal/rtl8822c/$(HCI_NAME)/rtl8822cs_ops.o\n\n_HAL_INTFS_FILES +=hal/efuse/rtl8822c/HalEfuseMask8822C_SDIO.o\n\n_HAL_INTFS_FILES +=hal/hal_hci/hal_sdio_coex.o\nendif\n\ninclude $(src)/halmac.mk\n\n_BTC_FILES += hal/btc/halbtc8822cwifionly.o\nifeq ($(CONFIG_BT_COEXIST), y)\n_BTC_FILES += hal/btc/halbtccommon.o \\\n\t\t\t\thal/btc/halbtc8822c.o\nendif\n"
  },
  {
    "path": "rtw88_blacklist.conf",
    "content": "alias pci:v000010ECd0000C82Fsv*sd*bc*sc*i* rtl88x2ce\nalias pci:v000010ECd0000C822sv*sd*bc*sc*i* rtl88x2ce\n"
  },
  {
    "path": "runwpa",
    "content": "#!/bin/bash\n\nif [ \"`which iwconfig`\" = \"\" ] ; then \n\techo \"WARNING:Wireless tool not exist!\"\n\techo \"        Please install it!\"\n\texit\nelse\n\tif [ `uname -r | cut -d. -f2` -eq 4 ]; then\n\t\twpa_supplicant -D ipw -c wpa1.conf -i wlan0\t\n\telse\n\tif [ `iwconfig -v |awk '{print $4}' | head -n 1` -lt  18 ] ; then\n\t\twpa_supplicant -D ipw -c wpa1.conf -i wlan0  \n\telse\t  \n\t\twpa_supplicant -D wext -c wpa1.conf -i wlan0 \n\tfi\n\n\tfi\nfi\n\n\n"
  },
  {
    "path": "wlan0dhcp",
    "content": "#!/bin/bash\n\nvar0=`ps aux|awk '/dhclient wlan0/'|awk '$11!=\"awk\"{print $2}'`\n\nkill $var0\ncp ifcfg-wlan0 /etc/sysconfig/network-scripts/\n\ndhclient wlan0\n\nvar1=`ifconfig wlan0 |awk '/inet/{print $2}'|awk -F: '{print $2}'`\n\n\nrm -f /etc/sysconfig/network-scripts/ifcfg-wlan0\n\necho \"get ip: $var1\"\n\n"
  }
]